Power supply circuit

A power supply circuit includes a first power supply for a normal power mode, a second power supply for a power saving mode, which is connected in parallel with the first power supply, a controller to which power from the first power supply and power from the second power supply are supplied via a common connection point, and a switch element which is connected between an output terminal of the first power supply and the connection point and controls power that is supplied to the controller, wherein the switch element includes a diode between a source terminal and a drain terminal of the switch element, the drain terminal of the switch element is connected to the first power supply side to prevent current flowing from the connection point toward the first power supply, and the source terminal of the switch element is connected to the connection point side.

BACKGROUND OF THE INVENTION

Field of the Invention

The present invention relates to a power supply circuit that includes a plurality of power supplies having different power supply capabilities.

Description of the Related Art

Recently, there is a demand for an image forming apparatus to consume less energy, so that reduced power consumption is now very important during a power saving mode, and not only during a normal power mode. Japanese Patent Application Laid-Open No. 2010-145653 discusses a power supply circuit that has a configuration like that illustrated inFIG. 5, for example.

InFIG. 5, the power supply circuit includes a power-saving power supply310for a power saving mode and a main power supply320for a normal power mode, for example. The power-saving power supply310for a power saving mode supplies power highly efficiently when the output is a few watts. The main power supply320for a normal power mode supplies power highly efficiently when the output is a few hundred watts. A system controller101selectively switches these plurality of power supplies based on a state of the image forming apparatus.

Specifically, in the power saving mode, power is supplied from the power-saving power supply310to the system controller101, and in the normal power mode, power is supplied from the main power supply320to the system controller101.

Operation of the circuit illustrated inFIG. 5will now be described. During the power saving mode, the system controller101sets a control signal S1to a high (Hi) state, and a first switch element312is consequently turned on. At this stage, the system controller101shuts a relay301with a control signal S3, and the main power supply is in an OFF state. The system controller101sets a control signal S2to a low (Low) state and turns off a second switch element322as well. In the power saving mode, an output Vcc1from the power-saving power supply310is supplied to the system controller101while the other power supply is in an OFF state, so that power consumption is reduced.

Further, when shifting from the power saving mode to the normal power mode, the system controller101turns on the relay301with the control signal S3to activate the main power supply320, and then sets the control signal S2to Hi to turn on the second switch element322. Consequently, the output from the main power supply320is supplied to the system controller101. Then, the system controller101sets the control signal S1to Low to turn off the first switch element312, so that the supply of power from the power-saving power supply to the system controller101is stopped. Consequently, in the normal power mode an output Vcc2from the main power supply is supplied to the system controller101.

In a power supply configuration like that inFIG. 5, in which power is supplied by connecting the outputs from a plurality of power supplies, when one power supply among that plurality of power supplies is in an ON state and the other power supply is in an OFF state, current flows from the power supply in an ON state to the power supply in an OFF state. Therefore, the flow of current to the power supply in an OFF state is prevented by, as illustrated inFIG. 5, configuring so that diodes317and327are each connected in series with the outputs from the power supplies, and the cathodes of those diodes are connected to each other.

However, in a conventional circuit configuration in which power (power supply output) is supplied to a load via a diode, a loss of power due to a voltage drop at both terminals of the diode cannot be avoided.

Specifically, after the image forming apparatus has shifted from the power saving mode to the normal power mode, if the amount of power consumed by the system controller101increases, the voltage drop in the diode327increases. Consequently, the power supply voltage input to the system controller101can fall below the minimum voltage required to guarantee operation of the system controller101. If the output voltage from the main power supply320is pre-set at a high level, the voltage drop at the diode327also decreases when the amount of current consumed by the system controller101is low. Consequently, the power supply voltage input to the system controller101can exceed the maximum voltage required to guarantee operation of the system controller101.

Thus, the greater the fluctuation in the amount of current consumed by the system controller101, the more difficult it is to satisfy the standards for both the minimum voltage and the maximum voltage required to guarantee operation of the system controller101.

SUMMARY OF THE INVENTION

The present invention is directed to a power supply circuit that has a low power loss while preventing the flow of current from one power supply to another power supply.

According to an aspect of the present invention, a power supply circuit has a normal power mode and a power saving mode, which consumes less power than when in the normal power mode. The power supply circuit includes a first power supply configured to operate in the normal power mode, a second power supply, which has a lower power supply capability than the first power supply and is connected in parallel with the first power supply, configured to operate at least when in the power saving mode, a control unit to which an output from the first power supply and an output from the second power supply are supplied via a common connection point, and a switch element, which is connected between the first power supply and the connection point, configured to control power that is supplied to the control unit. A diode configured to prevent current flowing from the connection point toward the first power supply is connected in parallel with the switch element.

DESCRIPTION OF THE EMBODIMENTS

FIG. 1is a schematic cross-sectional view illustrating the overall configuration of an image forming apparatus according to an exemplary embodiment of the present invention. The image forming apparatus according to this exemplary embodiment is an electrophotographic color copying machine.

An image forming apparatus1includes an image reading unit1R and an image output unit1P. The image reading unit1R optically reads a document image, converts the read image into an electric signal, and transmits the electric signal to the image output unit1P. The image output unit1P includes four image forming units10(10a,10b,10c, and10d), a feeding unit20(21a,21b, and27), an intermediate transfer unit30, a fixing unit40, and a cleaning unit50.

The four image forming units10respectively form yellow, magenta, cyan, and black toner images based on a known electrophotographic method. Each color toner image is superimposed and transferred onto an intermediate transfer body31. A sheet P is fed from the feeding unit20, and the toner image on the intermediate transfer body31is transferred onto the sheet P by the transfer unit30. The toner image transferred onto the sheet P is fixed by the fixing unit40, and the sheet P is then discharged onto a discharge tray48.

Next, the control system of the image forming apparatus1will be described with reference toFIG. 2. The image forming apparatus1is controlled in an integrated manner by a central processing unit (CPU)101ain a system controller101. The CPU101amainly collects and analyzes information about the drive of the various loads in the main apparatus and information from sensors. Further, the CPU101aalso performs the role of converting data from an operation unit102, namely, a user interface. The CPU101ais connected to a read-only memory (ROM)101b, a random-access memory (RAM)101c, and a timer unit101d.

A program is stored in the ROM101b. The CPU101aexecutes various sequences relating to an image forming process based on the program. The RAM101cstores rewritable data that needs to be temporarily or permanently stored during that time. Further, the RAM101cstores, for example, a high voltage setting value in a below-described high voltage control unit105, various kinds of data that are described below, and image formation instruction information from the operation unit102. The timer unit101dincludes a plurality of timers for measuring an interval between below-described patterns for registration correction and performing a count for image writing timing.

The image forming apparatus1further includes direct current (DC) loads, such as motors and a clutches/solenoids, which are operated by a direct current, and sensors, such as photo interrupters and micro power switches, in various locations in the apparatus. Namely, the system controller101conveys the transfer material and drives the various units by driving the motors and appropriately driving each DC load. Sensors109monitor this operation.

The system controller101smoothly proceeds the image formation operation by controlling each motor with a motor control unit107based on a signal from the sensors109, and activating the clutches/solenoids with a DC load control unit108. Further, the system controller101applies a suitable high voltage to the respective charging devices, which are included in a high voltage unit106, by transmitting various high voltage control signals to the high voltage control unit105. A heater111for heating a fixing roller41is provided in the fixing unit40. The heater111is turned on/off by an alternating current (AC) driver110. Further, a thermistor104for measuring the temperature of the fixing roller41is provided on the surface of the fixing roller41. An output from the thermistor104is converted into a digital signal by an analog-digital (A/D) convertor103. The converted signal is input to the system controller101as a digital value. The system controller101controls the AC driver110by detecting the temperature of the fixing roller41based on this digital value.

Further, a hard disk112is connected to the system controller101. The hard disk112stores image data transmitted from the image reading unit1R. The system controller101performs print processing by reading data stored in the hard disk112based on an operation from the operation unit102.

The operation unit102is used by a user to set information, such as copying magnification and a density setting value. Further, the operation unit102also transmits data for showing the user the number of image formation sheets, whether image formation is currently being performed, and if and where a jam has occurred.

FIG. 3illustrates a configuration of the power supply circuit in the image forming apparatus according to the present exemplary embodiment.

The power supply circuit is mainly configured from a main switch300, a power-saving power supply310, a main power supply320, the system controller101, a relay301, a first switch element312, and a second switch element322. Resistors314and315and resistors324and325work to apply necessary bias voltage for operation of the first switch element312and the second switch element322on the gates and sources. Capacitors313and323work to determine the timing of the on and off operations of the first switch element312and the second switch element322. Further, transistors316and326work to turn on or turn off the first switch element312and the second switch element322by changing the bias voltage of the first switch element312and the second switch element322. The main switch300has a function of switching power supply for manually turning on or off the image forming apparatus1. The number and type of these parts is not especially limited to this circuit configuration, and may be appropriately selected and arranged to match the apparatus.

As described above, the system controller101performs various types of control on the image forming apparatus1, and controls the switching of the power supply based on the mode of the image forming apparatus1. The relay301connects or cuts the power supply path from a commercial alternating current power supply350until the main power supply320as a first power supply. The first switch element312switches whether to supply the output from the power-saving power supply310as a second power supply to the system controller101. The second switch element322switches whether to supply the output from the main power supply320to the system controller101. The output from the main power supply320and the output from the power-saving power supply310are connected at a common connection point303, and are supplied to the system controller101.

Power supply capability of the main power supply320is about 200 W. Further, power supply capability of the power-saving power supply310, which has a smaller power supply capability than the main power supply320, is about 1 W. The main power supply320and the power-saving power supply310may be configured as independent units, or configured as an integral unit. However, the AC input unit of the main power supply320needs to be provided with one or more of some kind of cutoff unit like the relay301with regard to the common AC input unit with the power-saving power supply310.

When the image forming apparatus1is in the power saving mode, power is supplied to the system controller101from the power-saving power supply310. When the image forming apparatus1is in the normal operation mode, power is supplied to the system controller101from the main power supply320.

Operation of the power supply circuit will now be described. When in the power saving mode, the system controller101sets a control signal S1to a Hi state, so that the first switch element312is in an ON state. At this stage, the system controller101shuts the relay301with a control signal S3, so that the main power supply320is in an OFF state. Further, the system controller101sets a control signal S2to a low state, so that the second switch element322is also off. Thus, during the power saving mode, the power consumption of the overall apparatus is decreased by supplying an output Vcc1from the power-saving power supply310to the system controller101, and turning the other power supply off.

When the image forming apparatus shifts from the power saving mode to the normal power mode, the system controller101turns on the relay301with the control signal S3to start the main power supply320. Then, the system controller101sets the control signal S2to Hi to turn on the second switch element322, so that power is supplied from the main power supply320to the system controller101. The system controller101then sets the control signal S1to low to turn off the first switch element312, so that the supply of power from the power-saving power supply310to the system controller101is stopped. An operation timing is set so that the various processing operations performed by the system controller101start after the power supply source to the system controller101has switched to the main power supply320. Consequently, power is stably supplied even during the shift from the power saving mode to the normal power mode, and an output Vcc2from the main power supply320continues to be supplied to the system controller101in the normal power mode.

When the image forming apparatus shifts from the normal power mode to the power saving mode, the system controller101finishes its various processing operations. Then, after the power consumption of the system controller101has decreased to a level at which power can be supplied by the power-saving power supply310, the system controller101sets the control signal S1to Hi to turn on the first switch element312. This enables power to be supplied from the power-saving power supply310to the system controller101. The system controller101then sets the control signal S2to low to turn off the second switch element322. Further, simultaneously with or a little bit after setting the control signal S2to low, the system controller101turns off the relay301via the control signal S3, so that the supply of power from the main power supply320to the system controller101is stopped. Consequently, power is stably supplied even during the shift from the normal power mode to the power saving mode, and the output Vcc1from the power-saving power supply310continues to be supplied to the system controller101during the power saving mode in the manner described above.

If a plurality of power supply outputs are connected and power is supplied from one of those power supplies, a circuit needs to be provided that prevents current flowing from the power supply that is on to the power supplies that are off. For example, in the circuit illustrated inFIG. 3, a p-channel type field-effect transistor is used as the first switch element312and the second switch element322. This field-effect transistor includes a path along which current flows from the drain terminal to the source terminal through a body diode arranged in parallel with the channel when the field-effect transistor is in an OFF state. Namely, when the power-saving power supply310is on and the main power supply320is off, current flows to the main power supply320via a body diode of the field-effect transistor, which is the second switch element322, even if the second switch element322has been turned off. Therefore, as illustrated inFIG. 5, in a conventional configuration, current is prevented from flowing to the power supply side by connecting the diodes317and327, respectively, in series from the power-saving power supply310and the main power supply320toward the load side.

Here, in the power saving mode, the amount of current consumed by the system controller101and the amount of fluctuation in current consumption are both small. Therefore, the voltage drop caused by the diode317and the amount of fluctuation in the current decrease are also both small.

However, in the normal power mode, the amount of current consumed by the system controller101and the amount of fluctuation in current consumption are both larger. Therefore, the voltage drop caused by the diode327and the amount of fluctuation in the current consumption also increase, so that the voltage supplied from the main power supply320to the system controller101may not satisfy the input voltage range required by the system controller101.

Accordingly, in the present exemplary embodiment, the connection state of the second switch element322connected to the main power supply320and the connection state of the first switch element312connected to the power-saving power supply310are reversed. Namely, the drain terminal of the second switch element322is connected to the main power supply side, and the source terminal is connected to the connection point303side (load side). Further, the source terminal of the first switch element312that is connected to the power-saving power supply310is connected to the power-saving power supply310side, and the drain terminal is connected to the connection point303side (load side).

This enables the diode327(FIG. 5), which is conventionally provided in series, to be omitted, because the body diode (second diode) that is in parallel with the channel of the field-effect transistor is in a direction along which current does not flow to the main power supply320.

Consequently, because there is no voltage drop like there is in a conventional diode, the input voltage required for the system controller101can be satisfied even if the current consumption of the system controller101substantially increases during the normal power mode.

Further, in the power saving mode, namely, when the second switch element322is in an OFF state, a bias voltage is applied between the source terminal and the gate terminal of the second switch element322from the power-saving power supply310, which is already under operation, via the source terminal and the drain terminal of the first switch element312and the diode317.

In addition, in the normal power mode, namely, when the main power supply320has been started and the second switch element322is in an ON state, a bias voltage is applied between the source terminal and the gate terminal of the second switch element322from the main power supply320via the drain terminal and the source terminal of the second switch element322. Therefore, the second switch element322can stably operate in either power mode.

To prevent current flowing from the main power supply320to the power-saving power supply310via the body diode that is included in the first switch element312, the diode317is connected in series to the first switch element312as in the conventional manner. Further, as described above, since the amount of current consumed by the system controller101and the amount of fluctuation in current consumption are both small in the power saving mode, the voltage drop caused by this diode317is not a problem. Although the diode317is arranged downstream from the first switch element312, the diode317may also be arranged upstream from the first switch element312.

A case in which it is necessary to reduce power even further by cutting the supply of power to the system controller101will now be described with reference toFIGS. 6, 7, and 8.

FIG. 6illustrates the state of each signal and each load when the image forming apparatus1is in a power-off mode.

In a power-off mode, the supply of power to the system controller101has been cut. Consequently, the system controller101cannot output any of control signals S1, S2, or S3. Further, the first switch element312, the second switch element322, and the relay301cannot be turned on. Therefore, the only way to return the image forming apparatus from the power-off mode is for the user to manually turn on the main switch300.

Next, the state of each signal and of each load when the image forming apparatus1is in the normal power mode will be described with reference toFIG. 7. When the main switch300is turned on, the output Vcc1from the power-saving power supply310is applied on the ba e terminal of the transistor316via the main switch300, and the transistor316is turned on. Consequently, the first switch element312is turned on, and the output Vcc1from the power-saving power supply310is also supplied to the system controller101.

When the system controller101starts, the system controller101sets the control signal S1to ON (Hi state). Consequently, the first switch element312remains on regardless of the state of the main switch300. Next, the system controller101sets the control signal S3to ON (Hi state) to turn on the relay301, so that the main power supply320is turned on. Then, the system controller101sets the control signal S2to ON (Hi state) to turn on the second switch element322. Consequently, power from the main power supply320is supplied to the system controller101. Then, the system controller101sets the control signal S1to OFF (Low state) to turn off the first switch element312, so that the supply of power from the power-saving power supply310to the system controller101is stopped. Consequently, the output Vcc2from the main power supply320continues to be supplied to the system controller101in the normal power mode.

The state of each signal and of each load when the image forming apparatus1is in the power saving mode will be described with reference toFIG. 8. Since the sequence for shifting from the normal power mode to the power saving mode is similar to the sequence described above, a description thereof will be omitted here. In the power saving mode, the system controller101sets the control signal S1to ON (Hi state) to turn on the first switch element312. Further, the system controller101sets the control signals S2and S3to OFF (Low state) to turn off the relay301, the main power supply320, and the second switch element322. Consequently, the output Vcc1from the power-saving power supply310continues to be supplied to the system controller101in the power saving mode.

In the power saving mode and the normal power mode, when the system controller101detects that the main switch300has been turned off, the system controller101finishes the various processing operations, and then sets the control signals S1, S2, and S3to OFF (Low state) to shift to a power off state.

FIG. 4illustrates a flowchart of power control in the image forming apparatus1. The below-described processing is controlled in an integrated manner by the CPU101a, which is included in the system controller101.

When the power mode is the power saving mode, in step S5010, the CPU101adetermines whether a return request from the power saving mode has been made, namely, whether a print job, a scan job or the like has been input from the operation unit102. As described above, in the power saving mode, the first switch element312has been turned on by the control signal S1, and the output Vcc1from the power-saving power supply310is being supplied to the system controller101. Further, the relay301has been cut by the control signal S3, the main power supply is in an OFF state, and the second switch element322has also been turned off by the control signal S2.

If the CPU101adetermines that a job has been input so that there is a need to return to the normal power mode from the power saving mode (YES in step S5010), in step S5020, the CPU101aturns on the main power supply320with the control signal S3.

In step S5030, after the main power supply320has been turned on and the output has become stable, the CPU101aturns on the second switch element322with the control signal S2, and power is output from the main power supply320.

Then, in step S5040, the CPU101aturns off the first switch element312with the control signal S1, and stops the supply of power from the power-saving power supply310to the system controller101.

Next, in step S5050, the CPU101astarts various processing operations for the input job at a timing after the power supply source to the system controller101has switched to the main power supply320.

In step S5060, the CPU101adetermines whether the input job has finished. If the CPU101adetermines that the input job has finished (YES in step S5060), in step S5070, the CPU101adetermines whether a condition for shifting to the power saving mode is satisfied. Examples of the condition for shifting to the power saving mode may include a job not being input for a predetermined duration after the finish of a job, no operations being performed on the operation unit102of the image forming apparatus1, and an instruction from the operation unit102to shift to the power saving mode. Further, the predetermined duration may be set to a time desired by the user from the operation unit102.

If the CPU101adetermines that the condition for shifting to the power saving mode is not satisfied (NO in step S5070), in step S5080, the CPU101adetermines whether a job has been newly input. If the CPU101adetermines that a job has been input (YES in step S5080), the processing returns to step S5050, and the CPU101aperforms the processing for that job. If the CPU101adetermines that a job has not been input (NO in step S5080), the processing returns to step S5070.

If the CPU101adetermines that the condition for shifting to the power saving mode is satisfied (YES in step S5070), in step S5090, the CPU101afinishes the various processing operations for shifting to the power saving mode, and turns on the first switch element312with the control signal S1so that power can be supplied to the system controller101from the power-saving power supply310.

Then, in step S5100, the CPU101aturns off the second switch element322with the control signal S2. In step S5110, the CPU101aalso turns off the relay301with the control signal S3, so that the supply of power from the main power supply320to the system controller101is stopped.

Thus, according to an exemplary embodiment of the present invention, the loss of power supplied from the main power supply320to the system controller101during normal power mode can be prevented as much as possible, so that the power voltage required for operation can be maintained even if the system controller101consumes a large amount of current.

In the circuit illustrated inFIG. 3, similar to the second switch element322, the first switch element312may be configured without having the diode317, by arranging so that the drain terminal is on the power-saving power supply310side and the source terminal is on the connection point303side. However, in such a configuration, power is constantly supplied to the system controller101via an internal diode in the field effect transistor (FET), even if the image forming apparatus1shifts to the power saving mode. To eliminate such wasteful power consumption, in the present exemplary embodiment, the circuit is configured as illustrated inFIG. 3.

This application claims the benefit of Japanese Patent Application No. 2012-263256 filed Nov. 30, 2012, and Japanese Patent Application No. 2013-224605, filed Oct. 29, 2013, which are hereby incorporated by reference herein in their entirety.