Semiconductor device

A semiconductor device includes a semiconductor substrate of a first conductivity type having a top surface and a bottom surface, a semiconductor layer of a first conductivity type formed on the top surface of the semiconductor substrate, and having an active region and an edge termination region surrounding the active region, a first semiconductor region of a second conductivity type formed in the edge termination region adjacent to an edge of the active region, a second semiconductor region of a second conductivity type buried in the edge termination region in a sheet shape or a mesh shape substantially in parallel with a surface of the semiconductor layer, a first electrode formed on the active region of the semiconductor layer and a part of the first semiconductor region, and a second electrode formed on the bottom surface of the semiconductor substrate.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is based upon and claims the benefit of priority from prior Japanese Patent Application No. 2006-182703, filed Jun. 30, 2006, the entire contents of which are incorporated herein by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a high-voltage semiconductor device which develops a stable breakdown voltage characteristic.

2. Description of the Related Art

Conventionally, a high-voltage diode and a MOSFET have been used as a semiconductor device for electric power control. Such a kind of semiconductor device has been required to improve conflicting characteristics, such as, an improvement in breakdown voltage and a reduction in on-state resistance, and a variety of proposals on this requirement have been offered.

For example, JP-A H9-191109 (KOKAI) discloses a technique which disposes a plurality of stripe-shape p-type buried layers near by the surface of an n-type base layer of a Schottky barrier diode (FIG. 12of the patent document). This p-type buried layer is designed such that a depletion layer from a Schottky interface reaches the p-type buried layer before the electric field at the Schottky interface reaches maximum electric field of the semiconductor surface.

After that, as raising the reverse bias voltage, the depletion layer reaches the p-type buried layer, the largest point of the electric field at the Schottky interface is fixed not to be raised, and the depletion layer newly spreads onto an ohmic electrode side from the buried layer. Here, the voltage held by the epitaxial layer between the Schottky interface and the buried layer is set to a value lower than the maximum blocking (breakdown) voltage. Thereby, the electric field at the Schottky interface is fixed to a low value, and the leakage current from the Schottky interface may be decreased.

The technique disclosed in the aforementioned patent document disposes a plurality of stages of p-type buried layers as depicted inFIG. 13of said patent document, shares a breakdown voltage by means of n-type base layers divided by the plurality of stages of p-type buried layers, and develops a Schottky barrier diode which achieves a small voltage drop when conducting at a high voltage.

However, the forgoing conventional improvement is specified only for an active region under an anode electrode, and it does not take so much account to an n-type base layer under an edge termination structure. In other words, specifically, a planer-type high-voltage device, though it has high-voltage performance based on the p-type layer buried in the active region, it poses the problem that the breakdown voltage is determined by an electric field concentration at an edge termination region. If the edge termination structure is microscopic like guard rings, and when widths and intervals of the patterns vary due to a mask misalignment, the problem of lowering in breakdown voltage occurs.

Although such a problem poses, the planer device has many advantages for mass production on those points which are more stable in process, and are higher in yield ration and in throughput than a mesa-type device. Therefore, it has been desired to attain a high-breakdown-voltage device having a planar structure stable in breakdown voltage.

BRIEF SUMMARY OF THE INVENTION

According to one aspect of the invention, there is provided a semiconductor device, which includes:

a semiconductor substrate of a first conductivity type having a top surface and a bottom surface;

a semiconductor layer of a first conductivity type formed on the top surface of the semiconductor substrate, and having an active region and an edge termination region surrounding the active region;

a first semiconductor region of a second conductivity type formed in the edge termination region adjacent to an edge of the active region;

a second semiconductor region of a second conductivity type buried in the edge termination region in a sheet shape or a mesh shape substantially in parallel with a surface of the semiconductor layer.

a first electrode formed on the active region of the semiconductor layer and a part of the first semiconductor region; and

a second electrode formed on the bottom surface of the semiconductor substrate.

DETAILED DESCRIPTION OF THE INVENTION

A semiconductor device of the present invention described in the following embodiments is provided with a second semiconductor region of a second conductivity type buried in a sheet shape or a mesh shape in an edge termination region of a semiconductor layer of a first conductivity type substantially in parallel with the surface of the semiconductor layer. When a reverse voltage is applied between a first electrode and a second electrode, equipotential surfaces formed on upper parts of the semiconductor layer being bent toward a direction along the surface of the second semiconductor region so as to be converged with each other. As an electric field distribution is thus formed, the semiconductor device is hard to be broken at the edge termination region and has a stable breakdown voltage characteristic.

Hereinafter, the embodiments of the invention will be described with reference to the drawings.

First Embodiment

FIG. 1is a longitudinal sectional view of one element of a semiconductor device (vertical Schottky barrier diode) according to the first embodiment.FIG. 2illustrates a schematic transverse sectional view along a II-II line ofFIG. 1, and constituent components of one element of the embodiment are formed in a concentric circle shape in a plane except a component of reference number5. InFIG. 2, the constituent components may be modified and formed such that components of reference numbers5and7are made as rectangular rings each with a round (R) at its corners for releasing an electric field concentration.

In further detail, n-type SiC semiconductor layer2is formed on a highly doped n+-type SiC semiconductor substrate1. A RESURF layer8containing p-type impurities is formed in an annular shape so as to surround an active region A at a surface central part of the SiC semiconductor layer2. If further high-breakdown voltage is required, it is preferable to form an edge termination layer (not shown) containing p+type impurities inside the RESURF layer8so as to lie under an anode electrode edge.

P-type guard rings9are formed so as to surround the RESURF layer8of p-type in order to further enhance the breakdown voltage. In this case, the guard rings9of p-type may further enhance effect by disposing a plurality thereof. The sameness of the impurity concentration in the RESURF layer8and the guard rings9makes easy in a manufacturing process, however it may be different from one another. The semiconductor device may include either the RESURF layer8or the guard rings9.

The surface of the active region surrounded by the RESURF layer8is provided with a first electrode3so as to be contacted with the surface. The first electrode3forms a Schottky junction with the SiC semiconductor layer2, and uses, for example, Ti as a material. A pad electrode (or a field plate)11electrically connected to the first electrode3is formed thereon by, for example, Al. The pad electrode (field plate)11is formed also above the edge termination structure of the SiC semiconductor layer2with the RESURF layer8or the guard rings9formed thereon through a field plate insulating film12. The electric field being apt to concentrate to the edge part of the field plate11when the reverse electric field is applied thereto, it is preferable to be structured such that the edge part is disposed on the upper part of the RESIRF layer8or the guard rings9. A second electrode4is formed on the bottom face of the SiC semiconductor substrate1by, for instance, Ni.

In the semiconductor device, p-type semiconductor regions5and7are buried inside the n-type SiC semiconductor layer2in order to be formed in a low-loss structure, namely in a high-breakdown voltage and low on-state resistance structure. In further detail, a p-type region5having a plurality of openings is formed in order to have a high breakdown voltage structure and to secure a current path in the active region at the central part of the semiconductor device. As the buried termination structure in the edge termination region, the p-type region7is disposed in an electrically continued manner up to a device periphery on the outside of the active region. The periphery of the surface of the n-type semiconductor layer2is provided with an edge termination region10of a highly doped n+-type semiconductor.

Operations of the semiconductor device will be described hereinafter. When a reverse voltage is applied to the first electrode3that is an anode electrode, the depletion layer spreads in the device in the direction toward a second electrode through a Schottky interface, and also it spreads in the direction toward the RESURF layer8and the guard rings9, namely in a lateral direction of the device. The depletion layer extended in the lateral direction spreads in the lateral direction while being pinned by the RESURF layer8and the guard rings9.

After this, the depletion layer reaches the p-type buried regions5and7. The electric field distributes on the buried p-type region5only two-dimensionally; however the depletion layer spreads toward the p-type region7three-dimensionally. To achieve a high-breakdown voltage device, the electric field on the semiconductor surface should be kept lower than the maximum electric field intensity, and also the depletion layer should not be spread up to the second electrode.

In the case in which the p-type buried region7like one in this embodiment exists, as depicted inFIG. 3, the equipotential surface spreading in an oblique direction may be bent in a direction further parallel to the surface of the buried region7, that is, may be bent so as to be converged along with the surface of the buried region7. Conversely, in the case in which the buried region7like this does not exist, or on such a device inFIG. 4in which the buried regions5at the center are formed to extend to the periphery thereof, all of the equipotential surfaces cannot be converged along the surface of the buried regions5because gaps (openings) are present in the buried regions5at the periphery thereof.

Like this, according to the first embodiment, in comparison to the device including no p-type buried region7, the depletion layer does not reach the second electrode and a device with a further high breakdown voltage may be achieved. It is preferable for the aforementioned device to be designed such that the maximum electric field intensity becomes larger than the electric field with respect to the p-type buried regions5and7.

Next to this, a manufacturing method of the foregoing semiconductor device will be described by referring toFIGS. 5 to 8. The longitudinal sectional view of the semiconductor of the embodiment is a symmetrical shape capable of being folded at a center line of each ofFIGS. 5 to 8, so that only a right half thereof will be illustrated hereinafter to simplifyFIGS. 5 to 8.

At first, the method, as shown inFIG. 5, forms a film of the n-type SiC layer2on the n+SiC semiconductor substrate1by epitaxial growth. Here, the impurity concentration of the n-type SiC substrate1is, for example, 3×1015to 3×1016/cm3inclusive, and the present embodiment takes the case of the concentration of 1×1016/cm3as an example. The thickness of the SiC semiconductor layer2ranges from several μm to several dozen μm, and this embodiment sets it to 10 μm.

On the n-type SiC layer2, as illustrated inFIG. 6, the method forms the buried layer5under the active region and the buried layer7for burying the edge termination region simultaneously. Firstly applying and film-forming a mask material onto the surface of the SiC semiconductor layer1to perform patterning forms desired mask patterns (not shown) of the p-type buried regions5and7. Wherein, the mask material uses a resist, a silicon oxide, a silicon nitride, a metal, etc. The method implants ions of p-type impurities through multi-level implantation from the upper surface of the mask material to form the p-type buried regions5and7.

Here, as for p-type ion species, aluminum (Al), boron (B), etc., are usually used; however in the embodiment, Al suitable for a fine pattern is used. As for ion accelerating energy, energy of several keV to several hundred keV is usually used, and in the embodiment, the method uses the ion accelerating energy of 100-360 keV. An ion dose is set to its optimum value by a designed breakdown voltage and an epitaxial concentration, and the method performs Al multi-level ion implantation through the energy of for example, from 100 to 360 keV inclusive with a dose ranging from 1×1013to 1×1014/cm2inclusive. In such a case, the method may form a p-type well having a concentration ranging from 1×1017to 5×1018/cm3inclusive

The case, in which the concentrations of the p-type buried regions5and7are identical, having described in the given description, both concentrations may be different from each other. If the concentrations are different from each other, after forming the mask of only the p-type buried region5, and performing the ion implantation into the p-type buried region5, the method peels off the mask, forms the p-type buried region7again, and performs the ion implantation into the p-type buried region7. Or, after performing the ion implantation into the p-type buried region7in first, the method may implant ions into the p-type buried region5. Therefore, the sameness of the concentrations of the p-type buried regions5and7makes the method easy in process.

Subsequently, as shown inFIG. 7, the method grows again the upper part of the n-type SiC layer2onto the upper surface of the ion implantation surface by the epitaxial growth layer. The concentration and thickness of the upper part of the n-type SiC layer2is set to substantially the same as those of the aforementioned lower part of the SiC layer2. After this, the method forms an n+-type channel stopper layer10, the p-type RESURF layer8and the guard rings9on the surface of the n-type SiC layer2.

The method forms these layers by forming a mask pattern to selectively implanting ions, and it uses nitrogen (N) and phosphorus (P) for n-type ion species. Those doping concentrations being determined by the desired impurity concentration of the n-type SiC layer2, it is enough for the channel stopper layer10to become an n+layer perfectly, and the doping concentration ranges, for example, from 1×1014to 1×1016/cm2inclusive, and here, it is set to 2×1015/cm2.

The optimum values of the p-type RESURF layer8and the guard rings9are set by the designed breakdown voltage and the epitaxial concentration, the dose is set to 1×1013to 1×1014/cm2inclusive by Al multi-level ion plantation with, for example, 10-360 keV energy. In this case, the method may form p-type wells having a concentration within a range from 1×1017to 5×1018/cm3inclusive. To activate these wells, the method executes activated anneal at a high temperature within a range from 1,500 to 1,700° C. inclusive after ion implantation.

The impurity concentrations of the p-type RESURF layer8and the guard ring9being set to the same as that of the p-type buried layer7, they are not always necessary to be the same and they may be different form one another. However, the sameness of the impurity concentrations of the p-type RESURF layer8and the guard rings9makes the method easy in process.

After this, the method forms a silicon dioxide film12through thermal oxidation and a chemical vapor deposition (CVD) oxide film. After this, the method forms the second electrode on the bottom surface. The appropriate electrode material to this forming is a material to be easily ohmic-contacted, here, for example, Ni is used. Furthermore, to make sure the ohmic contact, the method preferably performs a thermal treatment at a high temperature of 900° C. or higher. To lower the contact resistance of the bottom electrode, the method preferably forms a film of a Ti/Ni/Au laminated structure, etc., onto the Ni surface.

The method then selectively performs etching to the silicon oxide film12of the surface to open a contact hole and to form a Schottky metal film3. As for the Schottky metal material, a metallic material to make a Schottky-contact to a SiC face may be preferable, and here, for example, Ti is used. The pad electrode11made of Al is formed so as to overlap on the Schottky metal film3and also on the silicon oxide film12. Finally, the method applies passivation (not shown) by polyimide, or the like, as part of a high breakdown voltage structure to complete the element.

In the given description, the case, in which the method performs the multi-level implantation by the low acceleration energy and the re-growing of the drift layer, having been described. If the drift layer has a thickness of 10 μm or less, after growing the drift layer up to the final thickness in first, the method may form the p-type buried region at only a prescribed depth thereof by performing multi-level implantation with high acceleration energy.

The first embodiment given above having described about the shape in which the p-type buried region7is arranged from almost edge part of the active region (under the inside edge part of the RESURF layer8) up to the almost edge part of the device, the invention is not limited to this.FIG. 9shows the result from a simulation of a breakdown voltage by varying a position of a start point (distance outward from active region edge) while fixing the edge of the p-type region7in the SiC semiconductor layer2to the device edge part. Here, the inside edge of the RESURF layer8is adjacent to the active region, and the width of the RESURF layer8is set to 50 μm. In addition, the RESURF layer8may be larger than 50 μm in width as long as there is some distance between the RESURF layer8and the device edge. FromFIG. 9, it is revealed that the inner edge of the p-type buried layer7located under the RESURF layer8makes the breakdown voltage higher. That is, the inner edge of the p-type buried layer7is desirably set inside the outer edge of the RESURF layer8. Of course, the result tells that the inner edge of the p-type buried layer7may be inside the active region edge.FIG. 10illustrates the result of a simulation of a breakdown voltage by varying the edge termination end point while fixing the start point to the active region edge. It is clear that the highest breakdown voltage is attainable in the case where the outside edge of the p-type region7is 20 μm or more outside from the outer edge of the RESURF layer8.

In the first embodiment, the shape, in which the buried p-type region extends from the active region edge to the device edge in a sheet shape, having been described, the invention is not limited to this embodiment. For instance, as shown inFIGS. 11A,11B to13A, and13B, even when the openings are present in the p-type region, if the p-type regions are electrically connected to each other at the edge termination part, an effect to converge the equipotential surfaces on the face of the p-type region is obtained.FIGS. 11A,11B to13A, and13B show mask design for ion implantation, they include radial elements and concentric elements. In the p-type region formed by ion implantation, the radial elements and the concentric elements are integrated (coupled).

The simple repetitive patterns depicted inFIGS. 11A and 11Bbeing easy to design and manufacture, they are appropriate for the use as long as to obtain the equipotential surfaces. In the case ofFIG. 11A, the concentric circle (ring) of p-type layers being coupled by radial p-type layers, the dose of the p-type layers is not so large that the patterns have advantages such that the electric potential of each ring becomes lower gradually, namely the electric fields are easily reduced in proportion to getting outside thereof. Conversely, in the case of dotted shape ofFIG. 11B, the patterns have advantages such that the electric fields hardly converge to a specific pattern.

InFIGS. 12A to 12C, the rings of the inside become wide in the diameter directions, these structures are effective for the use that the equipotential surfaces with high electric potentials at just outside the active regions are bent preferably inside the elements. InFIGS. 13A and 13B, the outer most periphery rings become wide in the diameter directions, and such structures are effective for the user to intend to avoid the concentrations of the electric fields at high-voltage center parts, and conversely, intend to bend the equipotential surfaces at the termination region which has become to a lower potential.

Even if the buried p-type regions7have, as shown inFIGS. 14A,14B, and15A to15C, shapes by which each element is not electrically connected to one another, when they are the p-type layers having effects to bend the equipotential surfaces spreading two-dimensionally from the RESURF layers8and the guard rings9that are the planar type edge termination parts, the shapes have the similar effects.FIGS. 14A and 14Bshow the examples making the rings at the outsides away from the active regions wide, andFIGS. 15 to 15Cshow the examples making the rings at the insides wide, and the examples have effects corresponding to each ofFIGS. 13,13B, and12A to12C, respectively.

FIG. 2depicts the shape like a stripe with respect to the p-type region5in the active region. However, the invention is not limited to the shape as long as the openings providing the current path in the p-type region5, and a variety of variations shown inFIGS. 16A to 16Care possible approaches.FIG. 16Aillustrating the p-type region5having a dotted shape, dots may be formed of n-type and the peripheries thereof may be formed of p-type.FIG. 16Bshowing the p-type region5shaped in grid, in a similar way toFIG. 16A, the p-type region and the openings may be reversed.FIG. 16Cshows the p-type region5with a ring shape. Like this, the openings in the p-type region5include openings completely surrounded by the p-type region5and the openings the part of which is surrounded by the p-type region5.

When the p-type region7is formed like a ring shape in the outside of the p-type region5and is continuously formed from the active region edge to the device edge as shown inFIG. 1, contacting of any one point of the p-type region7with the equipotential surface brings the whole of the p-type region7into an equipotential surface, so that the electric field concentration hardly occurs. The occurrence points of side etching in processing is limited to both side faces of the ring, so that the electric field concentration based on the etching shape is suppressed at minimum. When the p-type region5is formed in a dot pattern, the plural p-type regions can be separately disposed. Thus, the high breakdown voltage is attained by a smaller area. Further, it has an advantage to allow reducing the on-state resistance. Conversely, when the n-type region of the active region is formed in a dot pattern, the electric potential of the p-type regions5of a net-shape is made equal at any position therein, and the advantage of the buried p-type region is easily given. The ring shape has an advantage to easily ensure the matching property with the edge termination structure. Furthermore, even when no p-type region5exists at all, the breakdown voltage may be maintained by the effect of the p-type layer7.

As mentioned above, according to the first embodiment, since the diode includes the p-type buried region7buried in the edge termination region in a sheet shape or a mesh shape substantially in parallel with the surface of the n-type SiC layer2, when the reverse voltage is applied to the anode electrode3, and the equipotential surfaces formed at the upper part of the SiC layer2being bent toward the direction along the surface of the p-type buried region7and also bent so as to converge with one another, the diode becomes possible to have the stable high breakdown voltage characteristic.

Second Embodiment

The structure of the first embodiment is such a structure in which only one layer of the p-type regions5and7is disposed in the n-type SiC layer2. However, a plurality of stages of p-type buried regions may be disposed in the n-type SiC layer2.FIG. 17is a cross-sectional view of a semiconductor device according to a second embodiment, and in a similar manner to the first embodiment, the same components as those of the first embodiment are designated by identical numbers to eliminate duplicated descriptions.

The semiconductor in the second embodiment is also the Schottky barrier diode, and plurality (number n) of the p-type buried layers5and7are disposed in the n-type SiC layer2that is the drift layer. Also in such a device structure, optimizing the impurity concentration and the thickness of the drift layer2, and optimizing the impurity concentration of the p-type buried regions enable each of the drift layers divided by the plurality (number n) of the p-type buried layers5and7to share the breakdown voltage, and offers a device with a high breakdown voltage and a low leakage current.

Third Embodiment

FIG. 18is a cross-sectional view of a semiconductor device of the third embodiment, and depicts an embodiment in which the present invention is applied to a pn diode. The reference numbers13,111and112indicate a p-type anode region, an Ni anode electrode, and a pad electrode (field plate) of Ti/Al, respectively. The same components as those of the first embodiment are designated by identical numbers and duplicated descriptions are omitted.

In the third embodiment, the p-type region13on the semiconductor surface ohmic-contacting with the anode electrode111, the dose in the p-type region13has to be larger than that of the RESURF layer8. It is preferable for the impurity concentrations of the RESURF layer8and the guard rings9to be optimally designed so as to match with the impurity concentration of the p-type region13.

Also in the third embodiment, the pn diode with a stable breakdown voltage characteristic may be offered by disposing the p-type buried layer7that is an equipotential surface convergence structure.

Fourth Embodiment

FIG. 19is a cross-sectional view of a semiconductor device according to the fourth embodiment, and shows an embodiment in which the invention is applied to a vertical MOSFET.FIG. 19shows a p-type region14, an n-type source region15, a (gate) insulating region16, a gate electrode17, and a source electrode (first electrode)18. Other than these, the same components as those of the first embodiment are designated by identical numbers and duplicated descriptions are skipped, and the reference number4indicates the drain electrode (second electrode). Disposing the n-type SiC semiconductor layer2onto the p-type SiC semiconductor substrate1enables composing an IGBT.

In the fourth embodiment, disposing the p-type buried region7that is an equipotential surface convergence structure in an edge termination region allows achieving a vertical MOSFET having a stable breakdown voltage characteristic.

The invention having been described through the embodiments, the semiconductor material is not limited to SiC; it goes without saying that adaptation to Si, GaN, diamond, etc., are effective similarly. The conductivity type of the substrate and semiconductor layer may be reversible.