Method to improve analog fault coverage using test diodes

Implementations of integrated circuits may include: one or more diodes each having an anode and a cathode, each of the one or more diodes may be coupled with a voltage domain. One or more test pins may be coupled with one or more diodes. The test pins may be configured to be coupled to a tester. The one or more diodes may be positioned on one or more internal analog nodes to detect the presence of one or more analog faults. The one or more diodes may be configured to remain inactive during regular operation of the integrated circuit.

BACKGROUND

1. Technical Field

Aspects of this document relate generally to integrated circuits having analog nodes therein such as components for vehicles.

Conventionally, to test for analog faults in integrated circuits the structure of each analog component is tested by testing the function of the circuit. In some conventional situations, the functions of the individual circuit components are tested individually.

SUMMARY

Implementations of integrated circuits may include: one or more diodes each having an anode and a cathode, where each of the one or more diodes may be coupled with a voltage domain. One or more test pins may be coupled with the one or more diodes. The test pins may be configured to be coupled to a tester. The one or more diodes may be positioned on one or more internal analog nodes to detect the presence of one or more analog faults. The one or more diodes may be configured to remain inactive during regular operation of the integrated circuit.

Implementations of integrated circuits may include one, all, or any of the following:

The one or more diodes may be transistors.

The one or more diodes may not be active components of the integrated circuit and may not be activated after testing of the integrated circuit.

Implementations of integrated circuits may include: one or more diodes each having an anode and a cathode coupled to one or more internal analog nodes and a test pin coupled to the one or more diodes. When a test voltage is applied to the test pin, a flow of current at the one or more diodes detects the presence of a fault at the one or more internal analog nodes. The one or more diodes may be configured to remain inactive during regular operation of the integrated circuit.

Implementations of integrated circuits may include one, all, or any of the following:

The one or more diodes may be transistors.

The one or more diodes may not be active components of the integrated circuit and may not be activated after testing of the integrated circuit.

The anodes of the one or more diodes may be coupled together within a single voltage domain and when the test voltage is applied to the test pin, the flow of current at the anodes may detect the presence of the fault and the fault may be a pull-down fault.

The cathodes of the one or more diodes may be coupled together within a single voltage domain and when the test voltage is applied to the test pin, the flow of current at the cathodes may detect the presence of the fault and the fault may be a pull-up fault.

Implementations of an analog test circuits for integrated circuits may be designed using implementations of a method of designing analog testing circuits for integrated circuits. The method may include coupling one or more diodes each having an anode and a cathode, where the one or more diodes are coupled to one or more internal analog nodes. The method may also include coupling one or more test pins to the one or more diodes and when a test voltage is applied to the one or more test pins, detecting the fault by the flow of current at the one or more diodes. The method may also include the one or more diodes not being activated during normal operation of the integrated circuit.

Implementations of a method of designing analog test circuits for integrated circuits may include one, all or any of the following:

The one or more diodes may be transistors.

The one or more diodes may not be active components of the integrated circuit and may not be activated again after testing of the integrated circuit.

The presence of analog faults in an integrated circuit may be tested for by using implementations of a method of testing for the presence of analog faults in an integrated circuit. The method may include providing one or more diodes each having an anode and a cathode, the one or more diodes coupled to one or more internal analog nodes, all operably coupled with a test pin. The method may also include applying a potential across the diodes to generate a current. If a pull-up fault exists, then detecting the current may occur at the cathode. If a pull-down fault exists, then detecting the current may occur at the anode. The one or more diodes may not be an active component of the integrated circuit and may not be activated again after testing of the integrated circuit.

Implementations of a method of testing for the presence of analog faults in integrated circuits may include one, all or any of the following:

The one or more diodes may be transistors.

DESCRIPTION

This disclosure, its aspects and implementations, are not limited to the specific components, assembly procedures or method elements disclosed herein. Many additional components, assembly procedures and/or method elements known in the art consistent with the intended method to improve analog fault coverage using test diodes and integrated circuit implementations containing test diodes will become apparent for use with particular implementations from this disclosure. Accordingly, for example, although particular implementations are disclosed, such implementations and implementing components may comprise any shape, size, style, type, model, version, measurement, concentration, material, quantity, method element, step, and/or the like as is known in the art for such integrated circuits, and implementing components and methods, consistent with the intended operation and methods.

FIG. 1A-1Cillustrates examples of faults discovered on customer returned automotive parts as captured on scanning electron micrographs. EachFIG. 1A-1Cis a different particle found on exactly the same track2(nPD) in exactly the same block of the circuit as illustrated inFIG. 2. Referring toFIG. 1A, a crack1is illustrated running across the track2. Referring toFIG. 1B, a particle3was found on the track through a scanning electron micrograph. Referring toFIG. 1C, a defect5in the metal of the integrated circuit was discovered after failure of the device. These faults on the integrated circuit were not apparent to the naked eye because of the size of the integrated circuits and because the components of the integrated circuits (traces, devices, diodes, and the like) are formed into the device and cannot be later removed once formed. These faults were not discovered using conventional functional analog tests because the item that was tested, a comparator, was still functioning within specification but, further testing showed that it was not functioning at the correct speed. Specifically, leakage currents of top-mirror biased the comparator such that it still worked within specifications, but not properly enough to prevent failure/malfunction in the field. Comparator speed was not an item tested by the original testing specification. Referring toFIG. 2, the defect discovered on nPD track2may be represented by a fault4which increased resistance in the circuit leading to the leakage currents observed.

Referring toFIG. 3, an implementation of an integrated circuit having one or more testing diodes is illustrated. Testing diodes6may be connected to/with every analog node8which is not observable through functional testing or not controllable for testing during a full analog functional test of a particular integrated circuit implementation. In the implementation illustrated inFIG. 3, the anodes of each diode6are connected together for a given voltage domain. As used herein, a voltage domain is defined as a group of nodes that operates within the same voltage range. Any analog integrated circuit can be divided into a number of voltage domains by defining a certain voltage range for each of them. Here, the threshold voltage of a diode limits and also defines the maximum range for every voltage domain that is to be tested by using one test pin. The anodes of each of the one or more diodes are then coupled to a test pin10which is, during the normal operation, connected to the lowest potential in the circuit (ground) that does not disturb the normal operation of the integrated circuit. In some implementations, the test pin could be connected to a constant current source, and the resulting voltage at the test pin10is observed to detect faults. Also, in various implementations, the test pin10may be a dedicated pin used only for testing, or a pin that can be used during the testing process and then subsequently can be used for regular operation of the integrated circuit to perform functions of the integrated circuit.

When a predefined voltage is applied to the test pin, a flow of current at one of the anodes of the test diodes6detects the presence of a pull-down fault at the circuit. If no flow of current is detected, then no pull-down fault concerning those nodes exists. A pull-down fault is defined as a fault representing a defect that tends to pull the direct current (DC) voltage of a node lower than it was designed. After testing of the circuit is completed, if the circuit passes testing with no faults detected, the diodes6remain inactive during normal operation of the integrated circuit. Similarly, because the diodes6remain inactive for good circuits (those without faults) negligible loading effect may be applied to the circuitry even during operation in testing mode.

Referring toFIG. 4, another implementation of an integrated circuit having one or more test diodes is illustrated. This implementation may test for pull-up faults. A pull-up fault is defined as a fault representing a defect that tends to pull the DC voltage of a node higher than it is designed. During design of the integrated circuit testing diodes14may be connected to/with every analog node16that is not observable or not controllable using analog functional testing methods. In the implementation illustrated inFIG. 4, the cathodes of each diode14are connected together for a single voltage domain. The cathodes are then coupled to a test pin18which is, during normal operation, connected to the power supply (VDD)20. In the test mode, when a predefined voltage is applied to the test pin, a flow of current at one of the cathodes of the test diodes14detects the presence of a pull-up fault. As before, if no current is detected, then no fault exists. After testing of the circuit is completed, the diodes14remain inactive during normal operation of the integrated circuit. Similarly, because the diodes14remain inactive for good circuits, negligible loading effect may be applied to the circuitry even during test mode.

Referring toFIG. 5, another implementation of an integrated circuit having one or more testing diodes is illustrated. In this implementation, usage of multiple diodes for testing one circuit node is shown. This configuration allows connecting different voltage domains separated by multiples of the threshold voltage of a diode using a single test pin. By non-limiting example, the voltage domain of N1 may be one threshold voltage higher than the voltage domain of N2, so they can be tested together for pull-up faults. In another example fromFIG. 5, the voltage domain of N3 may be two threshold voltages lower than the voltage domain of N4 and one test pin may be enough to test pull-down faults affecting any of these nodes. Because the threshold voltages are related to each other by being multiples of a single diode threshold voltage, the deviation from that relationship is what is used during testing at the test pin to detect the presence of a fault.

In a further implementation, the testing diodes may be used for injecting or subtracting current from multiple nodes of a circuit under test by only using a limited number of test pins. This may make it possible to increase controllability of several nodes without adding large area overhead or an excessive number of additional test pins. The configuration type which is used to detect pull-down faults enables injecting current to a group of nodes from the same voltage domain in order to increase the controllability on those nodes. To subtract current from a group of nodes belonging to one voltage domain, the configuration proposed to detect pull-up faults can be used in a similar manner.

Referring toFIG. 6, a simulation circuit testing for pull-down faults is illustrated. Two faults22and24are illustrated. When a predefined voltage from the tester26is applied to the test pin28, current will be detected at the anode of diodes30and34. By non-limiting example, the diodes used are NPPWD, Nplus Pwell Diode, a typical PN-diode built using a highly doped n-region inside a Pwell. Diode30is connected to analog node32and will detect the fault22on node32. Diode34is connected to analog node36and will detect the fault24on node34. After testing of the circuit is completed, the diodes30and34remain inactive during normal operation of the integrated circuit by connecting the test pin28to the ground. Similarly, because the diodes30and34remain inactive for good circuits, negligible loading effect may be applied to the circuit even during test mode.

Referring toFIG. 7, a simulation circuit testing for pull-up faults is illustrated. Two faults38and40are illustrated. When a predefined voltage from the tester42is applied to the test pin44, current will be detected at the cathode of diodes46and50. Diode46is connected to analog node48and can detect fault38. Diode50is connected to analog node52and can detect fault40. After testing of the circuit is completed, the diodes46and50remain inactive during normal operation of the integrated circuit by connecting the test pin44to VDD. Similarly, because the diodes46and50remain inactive for good circuits, no loading effect may be applied to the circuitry even during test mode.

Referring toFIG. 8, a simulation circuit using transistors for the diodes54and56is illustrated. By non-limiting example, the transistors54and56may be p-channel metal oxide semiconductors (PMOS), n-channel metal oxide semiconductors (NMOS), or bipolar junction transistor (BJT), or any other transistor type. Two faults58and60are illustrated. When a voltage is applied by the tester62to the test pin64current can be detected at the transistors54and56. Fault58is detected by the presence of current at transistor54. Fault60is detected by the presence of current at transistor56. After testing of the circuit is completed, the transistors56and54remain inactive during normal operation of the integrated circuit by connecting the test pin64to VDD. Similarly, because the transistors remain inactive for good circuits, negligible loading effect may be applied to the circuitry even during test mode.

Circuit implementations like those disclosed herein may be designed for any integrated circuit having analog circuits. Implementations of a method of designing such circuits may involve coupling one or more testing diodes having an anode or a cathode to an internal analog node in the integrated circuit. The method may include coupling one or more diodes to the test pin such that when a test voltage is applied to the test pin a fault is detected by the flow of current at the test diodes. The one or more diodes may be transistors. The diodes may not be active components of the integrated circuit and may not be activated again after testing the integrated circuit.

Referring toFIG. 9, a graph showing the separation between the responses of good parts66and faulty parts68from the simulation circuit inFIG. 6for pull-down faults by NPPWD diodes is illustrated. The simulation was performed on two faulty and one good circuit on 8 corners and 1 typical. By inspection, there is good separation between the good circuits66, having no faults, and the faulty circuits68. The results of this simulation suggest that the implementation of this design on analog testing may be straightforward.

Referring toFIG. 10, a graph showing the separation between the responses of good parts70and faulty parts72from the circuit inFIG. 7for pull-up faults by NPPWD diodes is illustrated. The simulation was also performed on two faulty and one good circuit on 8 corners and 1 typical. Again, by inspection, there is a good separation between the good circuits70and faulty circuits72. Because of this, the ability to detect the presence of the faults in various implementations may be reliable and repeatable.

Referring toFIG. 11, a graph showing the separation between the responses of good parts74and faulty parts76from the circuit inFIG. 8detecting pull-up faults by PMOS transistor diodes is illustrated. The simulation was run for two faults and one good circuit on two corners and one typical. The separation between good and faulty circuits for each corner again indicates that it is possible to use this technique to identify faults at internal nodes in the circuit.

Referring toFIGS. 12A-12B, graphs showing transient simulations for the circuit inFIG. 8from two different corners are illustrated. InFIG. 12A, there is a good separation between the responses of a good measurement part78and the faulty parts80. InFIG. 12B, there is likewise a good separation between the responses of a good part82and faulty parts84. In combination with Dynamic Part Averaging Testing (DPAT), one corner per wafer, separation is excellent, which indicates that implementation in real test environments can be straightforward.

Referring toFIG. 13, a graph showing simulation results of an implementation on an industrial circuit is illustrated. Here, the good response is represented by85and faulty responses are represented by87. In this test, 9 pull-down faults87were detected by 4 NMOS transistor. Now referring toFIG. 14, 37 pull-down faults91were detected by 18 NMOS diodes in a real circuit. The good response is represented by89. Now referring toFIG. 15, 15 pull-up faults95were detected using 5 NMOS diodes in a real circuit, where the good response is represented by93. These results demonstrate proof of the concept of using diodes and transistors to detect the presence of the faults.

Referring toFIGS. 16A-16B, graphs showing no change in start-up behavior between integrated circuits having testing diodes (FIG. 16A) and those not having testing diodes (FIG. 16B) is illustrated. These graphs demonstrate that the testing diodes do not affect the function of the integrated circuit once testing has been completed and the testing diodes are configured to remain inactive during normal operation of the integrated circuit.

Referring toFIG. 17, a graph showing another start-up comparison as tested on regulated supply voltage VDDA is illustrated. There is almost no impact on start-up with the addition of testing diodes. Referring toFIG. 18, a graph showing another start-up comparison as tested on VBG is illustrated. Here, there is minimal impact on the start-up of bandgap voltage VBG with the addition of testing diodes.

Further tests were performed to determine whether there is negligible interference because of the testing diodes on the integrated circuit. Referring toFIG. 19, a circuit diagram showing testing diodes connected to an AC source is illustrated. Referring toFIG. 20, a graph of the AC simulation fromFIG. 19is illustrated. The results show coupling between the test pin86and test nodes88and90with reverse biased diodes92and97. The bottom line on the graph88corresponds to the node88in the circuit diagram (FIG. 19) and the top line90corresponds to the node90in the circuit diagram. The results illustrate that the addition of the test diodes may have negligible influence on most nodes in the frequency band of interest.

Referring toFIG. 21, another test was performed to determine whether negligible interference was created because of the testing diodes94and96on the nodes98and100of the analog circuit. An AC simulation was performed to check coupling between the test pin102and the test nodes98and100with reverse biased diodes94and96.FIG. 22illustrates a graph of the AC simulation of the circuit ofFIG. 21, showing that the addition of the test diodes is likely to have negligible influence on most nodes in the frequency band of interest.

Referring toFIG. 23, a graph showing the increase of fault coverage with an increase in the number of testing diodes is illustrated. Conventional methods of testing for analog faults provide less than optimal fault coverage, sometimes as little as 60% for a particular integrated circuit component. Coverage of an analog fault exists when it is observable and controllable. In contrast with conventional methods, as illustrated inFIG. 23, the use of testing diodes as described herein is capable to increase analog fault coverage to at least 85% or more in various implementations. As illustrated in the graph inFIG. 23, fault coverage increases as the number of testing diodes is increased with minimal increase in total area of the integrated circuit used and negligible interference on the nodes in the integrated circuit. In the actually fabricated circuit implementation disclosed herein, the increase in area of the circuit was 1.08% where the structure of the added diodes themselves represented only 0.0334% of the total area increase.

In places where the description above refers to particular implementations of integrated circuits, testing diodes for analog circuits and implementing components, sub-components, methods and sub-methods, it should be readily apparent that a number of modifications may be made without departing from the spirit thereof and that these implementations, implementing components, sub-components, methods and sub-methods may be applied to other analog integrated circuits.