Deskew circuit for automated test systems

This disclosure is in the field of electronics and more specifically in the field of timing control electronics. In an example, a timing control system can include or use an array of circuit cells, and each cell can provide a signal delay using a fixed delay or interpolation. The interpolation can include, in one or more cells, using three timing signals with substantially different delays to create a delayed output signal. Linearity of the delayed output signal is thereby improved. In an example, an impedance transformation circuit can be applied to improve a bandwidth in one or more of the cells to thereby improve the bandwidth of the timing control system.

BACKGROUND

A test system for electronic device testing can include a pin driver circuit that provides a voltage test pulse or current test pulse to a device under test (DUT). In response, the test system can be configured to measure a response from a DUT, such as to determine whether the DUT meets one or more specified operating criteria.

In an example, test systems can include dynamic controls for delivering timing signals, including controls for synchronizing or deskewing multiple signals to be provided to, or received from, a DUT. The timing signals can be used to perform tests on a variety of integrated circuit devices. In each test, one or more timing signals can be applied to respective pins of a DUT, and corresponding response signals can be analyzed. The timing signals may travel to each DUT pin by a different path, and response signals from the DUT can similarly travel different paths to response analysis circuitry. Such differences in propagation paths, or other influences on signal timing or propagation, can influence test results. Various techniques can be used to correct, or to more precisely control, the timing of test signals that are desired to arrive at a DUT at precise times or in synchronization.

Timing errors are generally referred to herein as “skew”. In an early approach to deskewing signals, a number of manually adjustable potentiometers were associated with each pin for aligning in time each pin's input signal. The potentiometers could be adjusted whenever the system required recalibration.

In another approach, a deskewing system can include a sequence of stages for delaying the signal. A more coarse stage can delay a signal by multiples of a predetermined delay interval and a finer stage can provide for finer adjustment of the delay interval.

SUMMARY OF THE DISCLOSURE

The present inventors have recognized, among other things, that a problem to be solved includes providing a test system that can synchronize timing signals, or edge placement in stimulus signals, and thereby reduce or eliminate timing errors at a device under test, or DUT. The inventors have further recognized that the problem can include time non-linearity at or near decision threshold regions. In an example, the non-linearity problem can be pronounced near a midscale of available delay code inputs that define a delay magnitude characteristic.

In an example, a solution to the above-described problems can include or use a deskew system for providing a programmable delay. The deskew system can include multiple delay cells coupled in a series. In an example, a first cell of the multiple delay cells includes a first input node and a first output node, and the first cell is configured to provide a maximum, minimum, or intermediate delay to an input signal at the first input node. The first cell can include one or more circuits or modules configured to generate or provide a delay. In an example, the first cell includes an early signal input node, a mid signal input node, and a late signal input node. The first cell can be configured to provide a delayed output signal at the first output node based on a delay adjust code and signals at the early, mid, and late signal input nodes. The delay adjust code can be user-specified, and indicates a delay amount to apply to the input signal. The early, mid, and late signal input nodes can be configured to receive signals sequentially in time.

In an example, the deskew system can include or use a current splitter configured to apportion early, mid, and late currents to first, second, and third current signal paths, respectively, wherein the current signal paths are respectively modulated by signals at the early, mid, and late signal input nodes. The current splitter can be configured to apportion the current signals based on the delay adjust code. When the delay adjust code indicates a minimum delay amount, the current splitter can apportion substantially all of the source current signal to the first current signal path modulated by the signal at the early signal input node, or when the delay adjust code indicates an intermediate delay amount, the current splitter can apportion substantially all of the source current to the second current signal path modulated by the signal at the mid signal input node, or when the delay adjust code indicates a maximum delay amount, the current splitter can apportion substantially all of the source current signal to the third current signal path modulated by the signal at the late signal input node.

In an example, a solution to the above-described problems can additionally or alternatively include or use a method for providing a programmable delay signal. The method can include, among other things, receiving an input signal to be delayed at a forward input node of a first deskew cell in a series of deskew cells, and receiving a delay adjust code indicative of a specified delay amount. The method can include apportioning a source current signal to first, second, and/or third current signal paths in the first deskew cell based on the delay adjust code to provide a minimum delay, maximum delay, or intermediate delay, respectively. The method can further include switching first, second, and/or third switches respectively provided in the first, second, and third current signal paths to modulate current signals therethrough, wherein switching the first switch includes using the input signal, wherein switching the third switch includes using a forward signal provided from the first deskew cell to an adjacent cell in the series of deskew cells, and wherein switching the second switch includes using a further delayed signal received from the reverse output of the same adjacent cell in the series of delay cells. The method can further include providing the output signal based on the switched signals of the first, second, and/or third switches. In an example, the method includes providing a minimum delay output signal when the first switch conducts current in the first current signal path and the second and third switches are not conducting, or providing a maximum delay output signal when the second switch conducts current in the second current signal path and the first and third switches are not conducting, or providing an intermediate delay output signal when the third switch conducts current in the third current signal path and the first and second switches are not conducting.

DETAILED DESCRIPTION

In this document, the terms “a” or “an” are used, as is common in patent documents, to include one or more than one, independent of any other instances or usages of “at least one” or “one or more.” In this document, the term “or” is used to refer to a nonexclusive or, such that “A or B” includes “A but not B,” “B but not A,” and “A and B,” unless otherwise indicated. In this document, the terms “including” and “in which” are used as the plain-English equivalents of the respective terms “comprising” and “wherein.”

Automated test equipment (ATE) systems are generally configured to perform tests and determine whether a device under test (DUT) meets one or more performance specifications. Precise and reproducible test signals, or vectors, can be provided by an ATE system to determine whether a particular DUT complies with a specified timing or response specification.

One characteristic of an ATE system is its edge placement accuracy, a characteristic that quantifies a precision and repeatability of test signals provided by the system to a DUT. Differences in circuit board traces, transmission signal length, parasitic loading effects, and other physical characteristics can influence test signal behavior and can cause timing errors, such as between signals provided at different pins on a DUT. In an example, a programmable test signal delay cell, also known as a deskew circuit or timing vernier, can be used to help synchronize vector timing or edge placement and thereby reduce or eliminate timing errors at a DUT.

FIG. 1illustrates generally an example of an output signal as a delayed version of an input signal.FIG. 1includes a first chart100that shows a result of using deskew circuit to delay an input signal in time. The first chart100includes an input signal vector101and an output signal vector102. The deskew circuit receives the input signal vector101at an input node and provides the output signal vector102as a delayed version of the input signal vector101. Under ideal conditions, the deskew circuit delays the input signal vector101by a precise, adjustable amount without altering signal fidelity or bandwidth, to provide the output signal vector102as an exact replica of the input signal vector101, except for a shift in time. The example ofFIG. 1demonstrates no bandwidth limitation when the input signal rise time TRINPUT(e.g., corresponding to the input signal vector101) matches the output signal rise time TROUTPUT(e.g., corresponding to the output signal vector102). The magnitude of the delay duration ΔT can be specified by a Delay Adjust Code, such as can include a digital or analog control signal input to a deskew circuit.

FIG. 2illustrates generally a second chart200showing a relationship between a Delay Adjust Code and a signal delay magnitude. A Delay Adjust Code can include an analog or digital signal and can be provided to a deskew circuit to indicate an amount or magnitude of delay to apply to the input signal101inFIG. 1. In the example, the Delay Adjust Code can be one of multiple different values ranging from a specified minimum (e.g., zero delay) to a specified maximum (e.g., a maximum amount of delay that can be provided by the deskew circuit). In the example ofFIG. 2, a first line201indicates there is a linear relationship between the Delay Adjust Code and the corresponding signal delay magnitude.

FIG. 3illustrates generally a third chart300showing a relationship between delay linearity error and a Delay Adjust Code. Delay linearity error is sometimes referred to as a Delay Deviation. In the example, a second line301demonstrates that there is no linearity error in the ideal deskew relationship shown inFIG. 2by the first line201. In other examples, the relationship can be non-linear, and in such case the second line301would deviate from a horizontal line. Generally, it is preferred to have a predictable and repeatable relationship between Delay Adjust Code and resulting signal delay at the output. Non-linearity or unpredictability is undesirable, since it can introduce edge placement uncertainty and thereby result in faulty or inconsistent measurement results.

Various deskew circuit topologies can be used to provide an adjustable delay. One such topology is shown inFIGS. 4A-4C.FIGS. 4A-4Cillustrate generally examples of deskew cell arrays. For example,FIG. 4Aincludes a first deskew cell array400,FIG. 4Bincludes a second deskew cell array410, andFIG. 4Cincludes a third deskew cell array420. In each example, the illustrated array, or illustrated portion of a larger array, includes three discrete cells labeled “Cell1”, “Cell2”, and “Cell3”. Each of the cells is configured to receive an input signal via a forward input node DF, delay the input signal by a delay duration, and then provide a delayed output signal via a reverse output node QR. If a greater delay amount is required than can be provided by a particular cell, then the particular cell can transmit the signal to an adjacent cell via a forward output node QF. The particular cell then receives a delayed signal from the adjacent cell via a reverse input node DR, as further explained below. The Programmed Delay line, in each example, provides an indication of the Delay Adjust Code relative to the Minimum delay and the Maximum delay available from the three-cell array.

In the example of the first deskew cell array400, the array provides a minimum delay, as shown on the Programmed Delay line. In this example, a first cell, Cell1, is configured in a loop-back configuration. In this configuration, the first deskew cell array400can receive an input signal D, delay the signal by a forward delay duration ΔFand a reverse delay ΔRin Cell1and provide a delayed output signal Q. In the example of the first deskew cell array400, a total delay from the input signal D to the delayed output signal Q is (ΔF+ΔR).

In the example of the second deskew cell array410, the array provides a first intermediate delay, greater than the minimum delay, as shown on the Programmed Delay line. The first intermediate delay is generated using a combination of Cell1and an adjacent cell, Cell2, where Cell1is configured in a pass-through configuration and Cell2is configured in a loop-back configuration. As shown in the figure, an input signal D enters the deskew, where it passes through Cell1to Cell2and back to Cell1, and exits the deskew as a delayed output signal Q. The total delay in this example is (2ΔF+2ΔR), because the signal is delayed by the forward delay ΔFof Cell1, the forward delay ΔFof Cell2, the reverse delay ΔRof Cell2, and the reverse delay ΔRof Cell1.

In the example of the third deskew cell array420, the array provides a second intermediate delay, which is greater than the minimum delay and smaller than the first intermediate delay. This delay is provided by interpolating between an early delay signal and a late delay signal, where Cell1is configured in an interpolating configuration and Cell2is configured in a loop-back configuration. The early delay signal can be generated by delaying the input signal D by a first delay amount, such as the forward delay ΔFof Cell1, for a total delay of ΔF. The late delay signal can be generated by delaying the early delay signal, which already has a delay of ΔF, by the forward delay ΔFof Cell2and the reverse delay ΔRof Cell2, for a total delay of (2ΔF+ΔR). The interpolation between the early delay signal and the late delay signal will result in an interpolation delay signal with a total delay between ΔFand (2ΔF+ΔR). Cell1, then, delays the interpolation delay signal by the reverse delay ΔRand provides a delayed output signal Q, with a total delay between 1×(ΔF+ΔR) and 2×(ΔF+ΔR). In this way, the deskew can provide any delay between the minimum delay and the first intermediate delay.

The examples ofFIGS. 4A-4Ccan be extended to understand how a deskew with many cells can provide a delay between a Minimum delay and a Maximum delay. By selecting a middle cell (e.g., Cell n) to be in an interpolation configuration, placing all previous cells (e.g., Cell1to Cell (n−1)) to be in a pass-through configuration, and placing an adjacent cell following Cell n (e.g., Cell (n+1)) to be in a loop-back configuration, a delay between n×(ΔF+ΔR) and (n+1)×(ΔF+ΔR) can be provided. In this manner, any delay amount between the Minimum delay and the Maximum delay can be provided by changing which cell is Cell n, or in an interpolation configuration, such as while keeping all previous cells in a pass-through configuration and a next or subsequent cell in a loop-back configuration.

The examples ofFIGS. 4A-4Cmotivate a need for a system or method to generate or provide fixed delays (i.e., the forward delay ΔFand the reverse delay ΔR) and a system or method to interpolate between two signals with substantially different delays. In an example, a delayed signal can be generated by switching a current into a node to charge a capacitance.

FIG. 5illustrates generally an example of a first circuit500that can be used to generate a delay. The example includes a first current source501(e.g., a fixed-amplitude DC source), a first switch502coupled to the first current source, and a signal input node503. An input signal VINat the signal input node503controls the first switch503. When the input signal VINat the signal input node503is high (e.g., when VINis at or above the midscale voltage, or 0.5 V in this example), the first switch502is closed and it conducts a source current signal ICTRLfrom the first current source501to a summing node506. The summing node506is coupled to an output node507, a load resistor504, and a capacitor505(e.g., representing a parasitic capacitance of the circuit), designated CPARA. In an example, the output node507, the load resistor504, the capacitor505, and the summing node506comprise an output circuit block that can be used or applied with other delay switching stages. When the input signal VINat the signal input node503is low (e.g., below the midscale voltage, or 0.5 V in this example), the first switch502is open and a source current signal from the first current source501is prevented from charging the summing node506.

FIG. 6illustrates generally an example showing a first relationship between an output node signal and a source current signal. The example includes a chart600showing the voltage VOUTat the output node507of the circuit ofFIG. 5. In this discussion, it is generally assumed that a signal transition occurs at a point in time when the voltage of a node crosses a midscale voltage, or 0.5 V in these examples. In an example, the input signal VINat the signal input node503transitions (e.g., from low to high) at a transition time T0. Following the transition time, the first switch502can close and the source current signal ICTRLcan charge the capacitor505and the load resistor504. When ICTRLis 1 amp, corresponding to a first trace601in the chart600, the voltage VOUTat the output node507transitions from 0 V to 1 V over a first charge interval. The voltage VOUTat the output node507charges to 0.5 V at a time T1following the transition at time T0. In this way, a signal with a fixed delay (T1−T0), such as can be used as the forward delay ΔF, can be generated from the input signal VIN. If ICTRLis reduced from 1 amp to 0.6 amps, then the voltage VOUTat the output node507charges to 0.5 V at a time T2following the transition at time T0, as illustrated by a second trace602in the chart600. When ICTRLis reduced, the time to charge the output node507to 0.5 V increases. That is, the slew rate of VOUTat the output node507depends on the magnitude of the source current signal ICTRLfrom the first current source501.

FIG. 7illustrates generally an example of a second circuit700that can be used to generate a delay. In an example, the second circuit700shows a configuration that can be used to interpolate between two input signals and generate a fixed delay (see, e.g., the discussion ofFIGS. 4A-4C). A current splitter702(e.g., a circuit configured to divide or apportion a current signal) receives the source current signal ICTRLfrom the current source501and divides the source current signal into early and late currents, IEARLYand ILATE, in respective first and second current signal paths721and722. The current splitter702divides or apportions the source current signal ICTRLbased on a specified delay amount or delay duration, such that the sum of IEARLYand ILATEis less than or equal to ICTRL. The first current signal path721includes an early switch, SWEARLY, and the second current signal path722includes a late switch, SWLATE. The early and late switches are separately actuated by input signals at early and late signal input nodes711and712, respectively. Following the early and late switches, the first and second current signal paths721and722are coupled to the summing node506, which is also coupled to the load resistor504, the capacitor505, and the output node507. As explained above in the example ofFIG. 5, the load resistor504, the capacitor505, the summing node506, and the output node507comprise an output circuit block that is used or applied with various delay switching stages; thus the summing node506inFIG. 5is understood as being part of a first output circuit block instance and the summing node506inFIG. 7is understood as being part of a different second output circuit block instance.

FIG. 8illustrates generally an example showing a second relationship between an output node signal and a source current signal. The example ofFIG. 8includes a chart800showing the voltage VOUTat the output node507of the circuit ofFIG. 7, according to examples of different delays. A first and second trace801and802correspond to circuit configurations that provide minimum and maximum delays, respectively. The first trace801corresponds to a circuit configuration wherein the current splitter702provides a 1 amp current signal to the first current signal path721and provides no current signal to the second current signal path722. This results in the output node507charging to the midscale voltage, 0.5 V, at time T1, due to a signal VEARLYtransitioning from low to high, at time TEARLY, at the early signal input node711. The second trace802corresponds to a circuit configuration wherein the current splitter702provides a 1 amp current signal to the second current signal path722and provides no current signal to the first current signal path721. This results in the output node507charging to 0.5 V at time T4, due to a signal VLATEtransitioning from low to high, at time TLATE, at the late signal input node712. The third and fourth traces803and804show intermediate delays, where the current splitter702divides the 1 amp source current signal, ICTRL, between the first and second current signal paths721and722. The third trace803corresponds to a circuit configuration where the first current signal path721has a larger current than the second current signal path722, resulting in the output node507charging to 0.5 V at time T2. The fourth trace804corresponds to a circuit configuration where the second current signal path722has a larger current than the first current signal path721, resulting in the output node507charging to 0.5 V at time T3.

The examples ofFIG. 8thus shows generally that the second circuit700inFIG. 7can produce a signal that is selectively and adjustably delayed, relative to an input signal, based on the amount of current that is provided to each of the first and second current signal paths721and722by the current splitter702. In the third trace803, where there is more current distributed to the first current signal path721, the voltage VOUTtransitions at time T2, which is closer to the minimum delay transition at time T1than the maximum delay transition at time T4. As more current is passed to the second current signal path722by the current splitter702, the resulting signal transition shifts closer to the maximum delay transition, such as corresponding to the fourth trace804. In this way, the source current signal ICTRLcan be divided in any proportion or ratio to provide an intermediate delay amount between the minimum and maximum delays.

Referring again toFIG. 8, the slew rate of the first trace801, corresponding to the minimum delay, can be substantially the same as the slew rate of the second trace802, corresponding to the maximum delay. Therefore, delay from TEARLYto T1is substantially the same as the delay from TLATEto T4. This also implies that the delay from T1to T4is substantially the same as the delay from TEARLYto TLATE. Therefore, the resulting signal transition can be an interpolation between the signals VEARLYand VLATEand a function of a fixed delay (e.g., T1-TEARLY, or T4-TLATE), such as can be represented by the reverse delay ΔR. The interpolation, which can also be considered an adjustable delay between 0 and (TLATE-TEARLY), is determined by the relationship between, or values of, IEARLYand ILATEprovided by the current splitter702.

FIG. 9illustrates generally an example of a deskew cell array900and cell detail910. The example of the cell detail910can include or use a forward delay circuit, such as the first circuit500fromFIG. 5, and an interpolation delay circuit, such as the second circuit700fromFIG. 7. The deskew cell array900includes n different deskew cells, such as including at least a first cell901, or Cell1, coupled to a second cell902, or Cell2. The examples400,410, and420illustrated generally a problem that includes generating fixed delays and interpolating between two signals with substantially different delays. The deskew cell detail910shows one example of a solution. In an example, the first circuit500can be used to generate a forward delay ΔF, and the second circuit700can be used to generate a reverse delay ΔRand interpolate two signals with substantially different delays.

Various cell configurations were discussed in the example ofFIGS. 4A-4C, including an interpolation configuration, a loop-back configuration, and a pass-through configuration. The example represented by the cell detail910can be configured to operate in any one or more of these configurations. In the interpolation configuration, a signal enters the cell through the forward input node911, is delayed by ΔFas it travels through the forward delay circuit500, and passes to the early signal input node of the interpolation delay circuit700and the forward output node912, where it can propagate to an adjacent cell in the array. A signal returns from the adjacent cell in the array, such as with an added delay, through the reverse input node913, and passes to the late signal input node of the interpolation delay circuit700. In the interpolation configuration, the current splitter702of the interpolation delay circuit700is configured to divide the source current signal ICTRLbetween IEARLYand ILATEsuch as to generate a signal with a fixed delay ΔRand a delay between that of the signal at the early signal input node and the signal at the late signal input node. This signal then passes from the output node507of the interpolation delay circuit700to the reverse output node914.

The loop-back configuration and pass-through configuration can correspond to specific settings or operating conditions of the interpolation configuration. In the loop-back configuration, the current splitter702of the interpolation delay circuit700can be configured such that all the source current signal ICTRLpasses to IEARLYand no current passes to ILATE. This results in a signal that depends on the signal at the early signal input node. In the pass-through configuration, the current splitter702of the interpolation delay circuit700is configured such that all the source current signal ICTRLpasses to ILATEand no current passes to IEARLY. This results in a signal that depends on the signal at the late signal input node and comes from the output of the next adjacent cell. Using these three configurations, any delay from a minimum of (ΔF+ΔR) up to a maximum of [n×ΔF+n×ΔR] can be generated, as described above in the discussion ofFIGS. 4A-4C.

FIG. 10illustrates generally an example showing a third relationship between an output node signal and a source current signal. The example ofFIG. 10includes a chart1000showing a potential problem with the interpolation technique provided by the circuit of example700inFIG. 7. Comparing the chart800ofFIG. 8and the chart1000, it can be seen that TLATEin chart1000arrives later than TLATEin chart800, relative to TEARLY. In other words, chart1000shows more delay between TEARLYand TLATEthan chart800. In the example ofFIG. 10, a first trace1001indicates that the voltage at the output node, VOUT, spends a relatively large amount of time near the threshold voltage, or 0.5 V. The duration of time spent in this threshold region is proportional to an amount of resulting signal delay non-linearity. As the delay between TEARLYand TLATEincreases, the duration of time spent in the threshold region increases, and therefore increases the signal delay non-linearity.

FIG. 11illustrates generally a chart1100showing a relationship between a Delay Adjust Code provided to the current splitter702of the circuit of example700inFIG. 7and a resulting Delay Deviation from an ideal delay characteristic (i.e., from a straight line, such as the line301inFIG. 3). The chart1100includes a first delay deviation trace1101that illustrates the non-linearity, particularly around the midscale of the available Delay Adjust Code inputs. That is, the non-linearity occurs and is most pronounced near the midscale Delay Adjust Code, corresponding to an equal split of the source current signal ICTRLbetween the early and late paths.

It is desirable to minimize the width of the non-linear region1011to reduce the delay non-linearity. One way to minimize the non-linear region includes reducing a slew rate of the first trace1001. However, the slew rate of one trace cannot be reduced without also reducing the slew rate of all other traces (see, e.g., second and third traces1002and1003), which leads to an undesirable decrease in signal bandwidth. Another way to minimize the non-linear region includes decreasing the delay duration between the signals that actuate the switches in the early and late current signal paths in the circuit700. This can shift TLATEto an earlier time (i.e., to the left in the chart1100), thereby reducing a magnitude or breadth of the non-linearity. However, this also shifts T4to an earlier time, thereby reducing the maximum available delay.

FIG. 12illustrates generally an example of a third circuit1200that can be used to generate a delay. The third circuit1200can include a modified version of the second circuit700from the example ofFIG. 7, such as including a third current signal path. The third current signal path1223, includes a mid switch, SWMID, which is actuated by an input signal VMIDat a mid signal input node1213. The current splitter702from the second circuit700is replaced by a current splitter1202that is configured to receive the source current signal ICTRLfrom the current source501and divide the signal into early, mid, and late currents, IEARLY, IMID, and ILATE, respectively. Following the early, late, and mid switches, the first, second, and third current signal paths721,722, and1223are coupled to an instance of the output circuit block that includes the summing node506and output node507.

FIG. 13illustrates generally an example showing a fourth relationship between an output node signal and a source current signal. The example ofFIG. 13includes a chart1300showing the voltage VOUTat the output node507of the circuit ofFIG. 12, according to examples of different output delays. The delay between TLATEand TEARLYin the chart1300is the same as the delay in chart1000ofFIG. 10. The traces1002and1003are the same in both charts since all of the current source signal is in the early path and the late path, respectively. However, chart1300adds a trace1301, which corresponds to the current splitter1202directing all of the source current signal ICTRLto the mid path, or third current signal path1223, as IMID. The input signal VMIDtransitions at a time TMID, which occurs between TEARLYand TLATE. A trace1311corresponds to a signal at the summing node when the current splitter1202divides the source current signal ICTRLequally between IEARLYand IMIDwith no current in ILATE. Likewise, a trace1312shows a signal at the summing node when the current splitter1202divides the source current signal ICTRLequally between IMIDand ILATEwith no current in IEARLY. Comparing the time spent near the logic threshold1311and1312in chart1300with1011in chart1000, it can be seen that the time near the logic threshold in chart1300is substantially reduced when the mid input signal and mid path are used.

FIG. 14illustrates generally a relationship between a Delay Adjust Code and a resulting Delay Deviation from an ideal delay characteristic.FIG. 14includes a chart1400showing the first delay deviation trace1101fromFIG. 11, such as corresponding to a relatively large delay between TEARLYand TLATE. As previously discussed, most non-linearity occurs around the midscale of the available Delay Adjust Codes. A second delay deviation trace1401demonstrates a reduced delay deviation, such as corresponding to the third circuit1200from the example ofFIG. 12, such as with substantially the same delay between TEARLYand TLATE. In this case, most of the non-linearity occurs around the Delay Adjust Code corresponding to the current splitter1202apportioning the source current signal ICTRLequally between IEARLYand IMID, with no current to ILATE, or equally between IMIDand ILATE, with no current to IEARLY. Therefore, it can be seen that the third circuit1200provides an improved delay linearity compared to the second circuit700fromFIG. 7.

FIG. 15illustrates generally an example of a second deskew cell array1500and second cell detail1510. To improve the linearity of the array inFIG. 9, the second cell detail1510includes an interpolation delay circuit1200, such as can include or use the third circuit1200from the example ofFIG. 12. In the second cell detail1510, the early signal input node of the interpolation delay circuit1200is coupled to the forward input node911at which a first timing signal (Early) can be received, the mid signal input node is coupled to the forward output node912at which a later second timing signal (Mid) can be received, the late signal input node is coupled to the reverse input node913at which a further later third timing signal (Late) can be received.

The three configurations discussed above (e.g., the interpolation configuration, the loop-back configuration, and the pass-through configuration) can be adjusted in the following manner. In the interpolation configuration, a signal enters the cell through the forward input node911and passes to both the forward delay circuit500and the early signal input node of the interpolation delay circuit1200. The signal then travels from the forward delay circuit500with an additional delay of ΔFand passes to both the mid signal input node of the interpolation delay circuit1200and the forward output node912, where it can propagate to an adjacent cell in the array. The signal returns from the adjacent cell in the array, with an additional delay, through the reverse input node913, and passes the signal to the late signal input node of the interpolation delay circuit1200. In the interpolation configuration, the current splitter1202divides the source current signal ICTRLbetween IEARLYand IMID, or between IMIDand ILATE, such as to generate a signal with a fixed delay ΔRand a delay between that of the signal at the early signal input node, the signal at the mid signal input node, and the signal at the late signal input node. This signal then passes from the output node507of the interpolation delay circuit1200to the reverse output914.

The loop-back configuration and pass-through configuration are, once again, specific settings, of multiple different available settings, of the interpolation configuration. In the loop-back configuration, the current splitter1202of the interpolation delay circuit1200is configured such that all the source current signal ICTRLpasses to IEARLYand no current passes to IMIDor ILATE, thereby providing a signal that depends on the signal at the early signal input node. This results in a signal with a delay of ΔR, as opposed to (ΔF+ΔR) in the example ofFIG. 9. This is because the signal passes from the forward input911to the early signal input node of the interpolation delay circuit1200, and from there to the reverse output914of the cell.

In the pass-through configuration, the current splitter1202of the interpolation delay circuit1200is configured such that all the source current signal ICTRLpasses to ILATEand no current passes to IMIDor ILATE, thereby providing a signal that depends on the signal at the late signal input node. This results is a signal entering the cell through the forward input911, acquiring a delay of ΔF, and passing to the forward output node912, where it can continue through the next adjacent cell. The signal then returns from the adjacent cell, through the reverse input node913, with some additional delay, passes to the late signal input node of the interpolation delay circuit1200where it is delay by ΔR, and passed to the reverse output node914. With these three configurations, any delay from a minimum of ΔRup to a maximum of [(n−1)×ΔF+n×ΔR] can be generated.

In an example, a limitation of the approach of the circuits and examples shown inFIG. 12includes bandwidth degradation that is inherent with connecting physically large switches (e.g., SWEARLY, SWMID, and SWLATE) the load resistor504. This degradation can be problematic since the circuit bandwidth is largely determined by the time constant provided by the capacitor505and the load resistor504. In an example, the capacitor505represents a capacitance of the switches SWEARLY, SWMID, and SWLATEas well as metal routing parasitic capacitances associated with connecting the switches to the summing node506. A solution to the bandwidth limitation can include reducing a capacitance at the summing node506, to reduce the time constant and increase the bandwidth.

FIG. 16illustrates generally an example1600of a circuit that provides an adjustable delay signal using n switching currents and first and second impedance transformer circuits1610and1611. In the example1600, the circuit includes a current splitter1601coupled to multiple parallel signal paths having n respective switches SW1through SWn. The parallel signal paths drive a common node, the summing node506, at a low impedance side of the first impedance transformer circuit1610, and the first impedance transformer circuit1610is coupled at a high impedance side to the load resistor504, a capacitance1604, and an intermediate node1605. The intermediate node1605is also coupled to a high impedance side of the second impedance transformer circuit1611, and the second impedance transformer circuit1611is coupled at a low impedance side to the output node507. In an example, the first and second impedance transformer circuits1610and1611are configured to reduce the capacitance1604at the intermediate node1605. The first impedance transformer circuit1610isolates the intermediate node1605from a parasitic capacitance1603that can result from the switches and routing. The second impedance transformer circuit1611isolates the intermediate node1605from any additional capacitance at the output node507, such as can be used to drive an input signal node, as seen in the previous examples.

FIG. 17illustrates generally an example1700of a transistor-level representation of a deskew cell, such as corresponding to the conceptual or schematic example of the second cell detail1510from the example ofFIG. 15. The example1700includes a forward input node1701that receives the forward input signal DFat a first differential pair1731. The first differential pair1731acts as a switch, like the switch502in the circuit500, to provide a fixed delay between the forward input signal DFand the forward output signal QF. When the forward input signal DFswitches states, a current signal1703can be switched from a first to a second side of the first differential pair1731, thereby causing a voltage transition at the resistors1704.

In an example, the example1700includes first and second impedance transformer circuits between the forward input portion1701and a forward output portion1710. The first impedance transformer circuit can include a first cascode circuit1711and the second impedance transformer circuit can include a first emitter-follower circuit1721. In the example1700, the first cascode circuit1711reduces an impedance seen by the collectors of the first differential pair1731, to reduce potential bandwidth degradation due to parasitic routing and a capacitance attributed to the first differential pair1731. The first cascode circuit1711and the first emitter-follower circuit1721also isolate the node at the summing resistors1704from effects of a parasitic capacitance by increasing an impedance at this node. In an example, the first emitter-follower circuit1721is configured to provide a signal level shift, such as to negate a level shift caused by the first cascode circuit1711.

The example1700includes second, third, and fourth differential pairs1732,1733, and1734, respectively, that represent the early, mid, and late switches, SWEARLY, SWMID, and SWLATE, respectively. A collector side of each of the second, third, and fourth differential pairs1732,1733, and1734, is coupled to a reverse summing node1750, and an emitter side of each of the pairs is coupled to a current splitter1702(e.g., corresponding to the current splitter1202from the example ofFIG. 12). The current splitter can apportion a source current signal ICTRLamong the early, mid, and late paths corresponding to the second, third, and fourth differential pairs1732,1733, and1734, respectively, and according to a delay control signal, or Delay Adjust Code.

In an example, the reverse summing node1750can be coupled to a reverse output node1760that provides the reverse output signal QR. When a signal at the output summing node1750switches states, a voltage transition occurs at resistors1705and at the reverse output signal QR. In an example, third and fourth impedance transformer circuits1712and1722can be provided between the reverse summing node1750and the reverse output node1760. The third impedance transformer circuit can include a second cascode circuit1712, such as provided between the reverse summing node1750and the resistors1705such that signal summing from the switches, and from the reverse input signal DR, occurs on emitter nodes of the devices in the second cascode circuit1712. Thus, an impedance at the reverse summing node1950can be substantially reduced. The fourth impedance transformer circuit can include a second emitter-follower circuit1722. The second cascode circuit1712and the second emitter-follower circuit1722isolate the node at the summing resistors1705from the effect of parasitic capacitance at both the reverse summing node1750and the reverse output node1760. In an example, the second emitter-follower circuit1722is also configured to provide a signal level shift, such as to negate a level shift caused by the second cascode circuit1712.

Various Notes

In the following claims, the terms “including” and “comprising” are open-ended, that is, a system, device, article, composition, formulation, or process that includes elements in addition to those listed after such a term in a claim are still deemed to fall within the scope of that claim. Moreover, in the following claims, the terms “first,” “second,” and “third,” etc. are used merely as labels, and are not intended to impose numerical requirements on their objects.