Structure and method of forming capped chips

As disclosed herein, structures and methods are provided for forming capped chips. As provided by the disclosed method, a metal base pattern is formed on a chip insulated from wiring of the chip, and a cap is formed including a metal. The cap is joined to the metal base pattern on the chip to form the capped chip. In one embodiment, a front surface of the chip is exposed which extends from a contact of the chip to an edge of the chip. In another embodiment, a conductive connection is formed to the contact, the conductive connection extending from the contact to a terminal at an exposed plane above the front surface of the chip.

BACKGROUND OF THE INVENTION

The present invention relates to microelectronic packaging.

Electronic devices referred to as surface acoustic wave or “SAW” devices process electronic signals in the form of acoustical waves, i.e., minute mechanical vibrations transmitted within the device, typically on an exposed surface region of a mass of a crystalline material. SAW devices are used, for example, as frequency-selective filters and as mixers in analog signal processing. Among other applications, SAW devices are used in radio frequency circuits of cellular telephones and other portable electronic apparatus. SAW devices normally must be provided with a cover or “cap” overlying the acoustically-active region of the surface to protect the active surface from mechanical engagement with surrounding structures and from chemical reaction with the surrounding atmosphere. Likewise, certain micro-electromechanical devices and micro machines incorporate microscopic mechanical elements within an active region of the device. The active regions of these devices must be covered by caps to protect the micromechanical elements. Such devices typically are formed using techniques commonly employed to make conventional microelectronic devices, and are commonly referred to by the acronym “MEMS.” Voltage controlled oscillators (VCOs) sometimes also require a cap to be placed over the active area.

Miniature SAW devices can be made in the form of a wafer formed from or incorporating an acoustically active material such as lithium niobate material. The wafer is treated to form a large number of SAW devices, and typically also is provided with electrically conductive contacts used to make electrical connections between the SAW device and other circuit elements. After such treatment, the wafer is severed to provide individual devices. SAW devices fabricated in wafer form have been provided with caps while still in wafer form, prior to severing. For example, as disclosed in U.S. Pat. No. 6,429,511 a cover wafer formed from a material such as silicon can be treated to form a large number of hollow projections and then bonded to the top surface of the active material wafer, with the hollow projections facing toward the active wafer. After bonding, the cover wafer is polished to remove the material of the cover wafer down to the projections. This leaves the projections in place as caps on the active material wafer, and thus forms a composite wafer with the active region of each SAW device covered by a cap.

Such a composite wafer can be severed to form individual units. The units obtained by severing such a wafer can be mounted on a substrate such as a chip carrier or circuit panel and electrically connected to conductors on the substrate by wire-bonding to the contacts on the active wafer after mounting, but this requires that the caps have holes of a size sufficient to accommodate the wire bonding process. This increases the area of active wafer required to form each unit, requires additional operations and results in an assembly considerably larger than the unit itself.

In another alternative disclosed by the ‘511 patent, terminals can be formed on the top surfaces of the caps and electrically connected to the contacts on the active wafer prior to severance as, for example, by metallic vias formed in the cover wafer prior to assembly. However, formation of terminals on the caps and vias for connecting the terminals to the contacts on the active wafer requires a relatively complex series of steps.

Similar problems occur in providing terminals for MEMS devices. For these and other reasons, further improvements in processes and structures for SAW, MEMS and other capped devices would be desirable.

SUMMARY OF THE INVENTION

According to an aspect of the invention, a method is provided for forming a capped chip. The method includes forming a metal base pattern on a front surface of a chip. A cap including a metal is joined to the metal base pattern on the chip to form a capped chip. According to such aspect, the front surface of the chip remains uncovered by the cap from at least a contact of the chip to a peripheral edge of the chip.

According to another aspect of the invention, a method of forming a capped chip is provided in which the cap is included in a microelectronic substrate. According to such aspect, a chip is provided having a front surface, a rear surface, and peripheral edges extending between the front and rear surfaces, and a metal base pattern disposed on the front surface. A microelectronic substrate including a cap is then joined to the metal base pattern to form a capped chip. According to such aspect, a front surface of the microelectronic substrate faces the front surface of the chip and extends beyond at least one the peripheral edge, whereby a terminal of the microelectronic substrate is not covered by the chip.

According to another aspect of the invention, a method is provided of forming a capped chip in which a cap is formed from a metal covered depression of a dielectric panel. According such aspect of the invention, a dielectric panel is provided having a first layer of metal disposed on a first side thereof, a depression on a second side thereof and a second layer of metal over the depression on the second side. The cap is joined to a chip to form a capped chip, wherein the metal covered depression defines a cavity facing the chip.

According to another aspect of the invention, a method is provided of forming a plurality of capped chips. According to such aspect of the invention, a plurality of chips are provided, arranged in an array, each chip having a front surface and a metal base pattern and a contact on the front surface. A cap frame is provided including an array of caps, each including a metal. The array of caps is joined to the metal base patterns of the plurality of chips to form capped chips, wherein a front surface of each chip remains uncovered by the cap joined to the chip from at least the contact of the chip to a peripheral edge of the chip.

According to yet another aspect of the invention, a method of forming a plurality of capped chips is provided in which an array of chips is provided, each chip having a front surface, a rear surface, and peripheral edges extending between the front and rear surfaces, and a metal base pattern disposed on the front surface. An array of microelectronic substrates, each including a cap, is joined to the metal base patterns to form an array of capped chips, such that a front surface of each the microelectronic substrate faces the front surface of each chip and extends beyond at least one peripheral edge of the chip.

According to yet another aspect of the invention, a method of forming a capped chip is provided in which a chip has a front surface, and a metal base pattern and a contact on the front surface. A cap substrate is provided which has a top surface and a bottom surface, a cap metal on the top surface, and at least one conductive connector exposed at the top surface and the bottom surface. The cap metal of the cap substrate is simultaneously bonded to the metal base pattern when the conductive connector is bonded to the contact of the chip to form a capped chip having a conductive connector exposed at the bottom surface of the cap substrate.

According to yet another aspect of the invention, a capped chip is provided which includes a chip having a front surface including wiring, a metal base pattern insulated from the wiring, and an active area. According to such aspect, the front surface of the chip extends between a first edge of the chip and a second edge of the chip opposite the first edge. A cap including a metal layer is joined to the chip, wherein the front surface is exposed between a contact of the chip and at least the first edge of the chip.

According to yet another aspect of the invention, a capped chip is provided which includes a chip having a metal base pattern on a front surface thereof. A microelectronic substrate having a cap metal pattern is joined to the metal base pattern of the chip in such way that the microelectronic substrate extends beyond at least one peripheral edge of the front surface of the chip. The front surface of the microelectronic substrate remains uncovered by the chip from at least a terminal to a peripheral edge of the microelectronic substrate.

According to still another aspect of the invention, a capped chip is provided in which the chip has a front surface, a metal base pattern and a contact on the front surface. A cap substrate is provided having a top surface and a bottom surface, a cap metal on the top surface, and at least one conductive connector exposed at the top surface and the bottom surface. According to such aspect, the cap metal is bonded to the metal base pattern and the conductive connector is bonded to the contact such that the conductive connector is exposed at the bottom surface of the cap substrate.

DETAILED DESCRIPTION

In the embodiments described herein, reference is made to the fabrication of a cap and the joining of the cap to a chip to form a capped chip having a cavity over an area of the chip. For example, a cap112can be joined as a cover element for hermetically sealing an active area of a surface acoustic wave (SAW) chip. Alternatively, in another type of chip, the active area may include other features requiring a sealed cavity, such as microelectromechanical devices (MEMs). As another alternative, a sealed cavity may be needed to enclose an “air dielectric” having exposed conductors which are isolated from one another by vacuum or air spaces separating individual conductors.

The description that follows should be understood to include the simultaneous fabrication of multiple caps arranged in an array, and the simultaneous joining of the caps to multiple chips, arranged in an array on a wafer or sub portion thereof. The multiple chips are simultaneously aligned to the multiple caps, prior to the joining the chips to the caps. Thereafter, the multiple capped chips are severed from each other, as by dicing. Further, the terms “edge” and “peripheral edge”, used herein in relation to a chip, shall be understood to mean the peripheral boundary of the front surface of a chip, i.e., the actual boundary of the chip when it has already been severed from other chips, or when the chip has not yet been severed, the implicit boundary, i.e., the line on which the chip will be severed.

FIG. 1is a plan view of a chip8having a surface acoustic wave (SAW) filter device10.FIG. 2is a cross-sectional view of the chip8through lines2-2. The chip8has a front surface9(FIG. 2) extending between peripheral edges13of the chip. As shown inFIG. 1, the SAW device includes a SAW active area12which is connected by wiring11to a pair of contacts14and16, all of which are located on the front surface. The SAW active area12, wiring11and contacts14and16are isolated from other elements of chip8by isolating material18. Metal conductive patterns20partially surround the SAW active area12and wiring11. In addition to contacts14and16, additional contacts22are provided on the chip8to allow for interconnection to other optional elements of the chip8, e.g., passive devices or other active devices.

As shown inFIG. 2, the active area12and contacts14,16are all located on the front surface9of the chip8. As further illustrated inFIG. 2, an insulating film24is formed over the wiring11between a contact14and SAW active area12, and over the wiring11between the SAW active area12and contact16. This can be performed as by selective deposition through a contact mask, or alternatively by blanket deposition followed by masking and subsequent etching to expose the SAW active area12and contacts14,16of the chip8.

As also shown inFIGS. 1 and 2, a metal base pattern26surrounds the SAW active area12, insulated from the metal conductive patterns20by the insulating film24. The metal base pattern26serves as a base to which a cap will be joined later by the reflowing of a metal such as tin, lead, solder or eutectic composition provided at the interface between the chip8and the cap. The metal base pattern26is formed of a metal such as aluminum or copper, preferably having a barrier layer formed thereover including a metal such as nickel. A layer of gold, platinum or palladium is preferably formed over the barrier layer as a protective layer for providing improved resistance to oxidation. A layer of tin, lead, solder or eutectic composition is optionally formed over the barrier layer, or the protective layer when present, to provide reflowable material for later joining the base pattern26to a cap.

FIGS. 3-7illustrate steps in a process of pre-forming a cap on a mandrel, to be joined to a chip8such as that having a SAW device10as illustrated inFIGS. 1-2. As shown in the cross-sectional diagram ofFIG. 3, a mandrel30is provided from a block of material having a depression32formed therein. The depression32corresponds to the general shape and size of the cap to be formed thereon. The depression is typically formed by etching the mandrel to a depth of 20 to 30 microns. In order to match the metal base pattern26of the chip8, the depression32should have a generally rectangular shape. However, the corners of the depression are preferably rounded to some minimum or greater radius, to help avoid stresses at the junctions between sides of the cap to be formed thereon. The block of material from which the mandrel is provided is preferably rigid or substantially rigid, and includes a material capable of withstanding the cap forming processes described below. For example, the mandrel30can be formed of a block of metal such as stainless steel, having an overlying layer of a low adhesion metal (not shown) such as chromium to facilitate lift-off of the cap under an appropriately applied force, after fabricating the cap and joining it to the chip8.

As shown inFIG. 4, an insulating coating34is applied to the mandrel30. The insulating coating is then removed from the depression32, as by a masked etch, after which areas36remain on mandrel30, as shown inFIG. 5. The insulating coating is preferably formed by depositing diamond material by chemical vapor deposition (CVD). Alternatively, the insulating coating can be formed of any suitable dielectric material such as silicon dioxide, silicon nitride, polyimide or other organic or inorganic dielectric material. For example, the insulating coating can be formed by a timed thermal oxidation, as commonly performed in a passivation process.

Thereafter, as shown inFIG. 6, a first metal layer38is formed on the mandrel30. In a particular embodiment, the first metal layer38is formed by electroplating onto an exposed metallic (e.g., chromium) layer of the mandrel30, such that the first metal layer38is not formed on the insulating areas36of the mandrel30. Copper or aluminum is preferred as a first metal. Further, copper is preferred over aluminum because of better adhesion during the plating process onto the overlying metal layer (e.g., chromium layer) of the mandrel30.

Then, as shown inFIG. 7, a second metal layer40is formed over the first metal layer38, again preferably by electroplating, such that the second metal layer40does not form on the insulating areas36of the mandrel30. The second metal layer preferably includes a barrier layer such as nickel. Preferably, a protective metal (not shown) which resists oxidation such as gold, platinum, or palladium is then formed over the barrier metal, and a ref lowable metal (also not shown) such as tin, lead, solder or a eutectic composition may be optionally formed, as a layer for contacting and forming a seal to the metal base pattern26of the SAW device10(FIG. 2) Collectively, these metal layers38,40and optional protective metal layer and ref lowable metal form a cap42.

Alternatively, a first metal layer, including an electrolessly platable metal such as nickel is electrolessly plated onto the surface of the mandrel. Other electrolessly platable metals include cobalt, and alloys of nickel with another metal such as tungsten, cobalt, iron, rhenium or molybdenum, and alloys of cobalt with another metal such as tungsten. Boron or phosphorous is also typically a component of electroless coatings, in controlled percentages. Thereafter, a second metal layer is formed, desirably including tin. For example, tin is electroplated onto the surface of the underlying nickel layer.

With the cap42now formed, the raised edges41of the cap42which extend above the mandrel30are contacted to the metal base pattern26of the chip8, as shown inFIG. 8. Heat and pressure are applied between the cap42and the chip8seals the cap42to the chip, leaving a cavity45between the active area12of the chip8and the cap42for the propagation of surface acoustic waves. Alternatively, when the cap42is joined to a different kind of chip other than a SAW device10, such as a MEM (micro-electromechanical) device chip, the cap42protects the exposed small and/or moving parts of the MEMs.

The cap42is joined to the metal base pattern26in such a way to hermetically seal the active area12of the chip8. The joining process is desirably performed by heating the mandrel including a multiplicity of caps42thereon and pressing the mandrel cap-side down onto the corresponding metal base patterns of a wafer containing the chips. This process can be performed with solder, or without solder when the caps or metal base patterns include a joining metal or metals such as tin or tin-gold. If the cap42is soldered, the soldering process is preferably performed in a vacuum or other substantially oxygen-free ambient to reduce the incidence of included material within the cavity under the cap42. Soldering can be performed under such conditions without the use of a flux, as flux is only needed to draw away oxidation products, which are not present in a vacuum. Whether the joining process is performed with or without solder, the joining of the caps to chips in a vacuum or substantially oxygen-free environment helps to produce a low-oxygen environment inside the cavity45enclosed by the cap.

Thereafter, the mandrel is detached from the cap42, leaving the cap42adhering to the metal base pattern26of the SAW device10, as shown inFIG. 9. When the first metal layer38includes nickel and the mandrel is a silicon wafer, mismatch of the coefficients of thermal expansion (CTE) between the silicon and nickel materials having CTEs having relative values of14and3, respectively, helps cause the cap42to detach from the mandrel as a result of cooling after it is joined to the chip8. As illustrated inFIG. 9, the cap42is now joined to the chip8in a way which leaves the front surface9of the chip8exposed, from the contacts14,16to the edges13of the chip8. Thereafter, the assembly48formed by joining the cap42to the chip8is now available for packaging according to any of several alternative ways.

For example, the assembly can be placed face up on a packaging element and then wire-bonded from the pads of the SAW device chip8to the terminals of a packaging element. In another example, the assembly is joined to other packaging elements according to any of the several alternatives disclosed in commonly assigned U.S. patent application Ser. No. 10/786,825 filed on Feb. 25, 2004, U.S. Provisional Application No. 60/449,673 filed Feb. 25, 2003 and U.S. Provisional Application No. 60/456,737 filed on Mar. 21, 2003, the entire applications of which are incorporated herein by reference.

In another example, as shown inFIG. 10A, the assembly48can be encapsulated in a polymer, epoxy, or elastomeric material, and then a set of openings44are made to the contacts14,16of the chip8, as by mechanical or laser drilling (ablation), stopping on the underlying metal of the contacts14and16. Alternatively, the openings are molded in place when the encapsulant is applied to the assembly. The openings are then filled with a connection-forming metal such as tin, solder or a eutectic composition to form conductive connectors46, which can then be joined to a microelectronic element, e.g., a packaging element at an exposed plane49above the front surface9of the chip8. As shown inFIG. 10A, the connectors46are shown extending above the openings44, as held in place by surface tension of the metal which is deposited when molten. Alternatively, connectors can be formed by placement of pre-formed metallic features, such as solder balls, within the openings44and thereafter heating to join the solder balls to the underlying contacts to form the connectors46.

In an arrangement shown inFIG. 10B, the capped chip48is mounted to a chip carrier60having a dielectric element61and metal patterns62disposed thereon. For example, the chip carrier60can be a tape-like element having a plurality of cantilevered or frangible leads62awhich are bonded to corresponding contacts14,16of the chip by pressure and/or heat from a bonding tool through a bonding window64provided in the chip carrier60. Desirably, an encapsulant63is then provided between the capped chip48and the chip carrier60.

In another arrangement, as shown inFIG. 10C, the capped chip48is mounted to a circuit panel65by solder balls66. The solder balls are provided on the contacts14,16of the chip and mounted to corresponding pads68of the circuit panel65. The cap is mounted to the circuit panel65by conductive adhesive or solder70at an interface to a pad72of the circuit panel. The pad72is desirably a thermally conductive element which carries heat away from the capped chip48, such as by way of conductive vias74provided in the circuit panel65. Desirably, an encapsulant76is then provided between the capped chip48and the circuit panel65. Still other arrangements for assembling the capped chip to a circuit panel, chip carrier, lead frame and other elements are described in the aforementioned U.S. patent application Ser. No. 10/786,825 and U.S. Provisional Application Nos. 60/449,673 and 60/456,737.

Consideration must be given to the need to simultaneously align the multiplicity of chips, having a particular coefficient of thermal expansion (CTE) corresponding to the semiconductor material of the chip, to the multiplicity of caps formed on a mandrel, which, in many cases, has a different CTE. Particularly as to wafers of 200 mm and 300 mm sizes, as common today, a factor of five difference between the CTEs of silicon chips and a metal mandrel is enough to produce a relative change in position of 36 μm over a 300 mm wafer when the temperature varies by 10 degrees C. If the temperature varies by 50 degrees C. this relative change in position can reach 200 μm or more. This is significant because chip pads typically have dimensions of less than 100 μm in each direction of the front surface9of the chip8. Therefore, thermal expansion poses a risk that the caps42will not be aligned with the chips8.

A possible solution to this problem is to fabricate the multiplicity of caps on a mandrel formed of the same semiconductor material as that of the chips, such that the mandrel, to which the caps adhere prior to joining them to the chips, expands and contracts the same in relation to the chips. Molybdenum and glass are other examples of materials having the same or similar CTEs as chips. Proper alignment can be achieved through such techniques.

In another alternative solution, the mandrel on which the caps are fabricated can be formed of a material having a different CTE than the CTE of the chips. In such case, the mandrel should be sized in a way such that the array of the caps become aligned with the array of chips when the joining temperature is reached, and joining then proceeds under such conditions. For example, when the mandrel is formed of stainless steel, its CTE is about 15 ppm/deg. C., which is about five times larger than the CTE of silicon, being about 3.0 ppm/deg. C., the material of the chip on which an exemplary SAW device10is provided. The mandrel should be formed of a material having a predictable and isotropic CTE such as metals and glass. Since the mandrel is formed of a material having a higher CTE, then at room temperature, the array-wise arrangement of the caps42on mandrel30(FIG. 7) should be somewhat smaller than the array-wise arrangement of chips. This will allow the mandrel to expand to a degree at which the caps become aligned to the chips at the joining temperature. After joining, the mandrel is detached from the caps at or only somewhat below the joining temperature. In such manner, the caps remain aligned to the chips when the mandrel is detached.

A variation of the above embodiment of the invention will now be described, with reference toFIGS. 11A-11D. According to this variation, as shown inFIG. 11A, caps52are formed integrally to a cap frame50by processing a metal sheet, as will be described more fully below. Then, the caps52are simultaneously joined to an array of chips of a wafer or subportion thereof as described above. The caps can then be severed from the cap frame at the same time that chips are severed from each other. Alternatively, as according to the needs of the particular process, caps52can be first separated from the cap frame50and then joined to respective chips on an individual basis.

InFIG. 11A, the bottom (chip-facing) side of a cap frame50is shown, including a multiplicity of caps52arranged in an array. The caps52are held together in the cap frame50by connecting members54extending between respective caps52. On the bottom, chip-facing side of each cap52is a cavity53surrounded by raised edges41. The cap frame50is formed of a base metal, for example, copper or aluminum, over which a layer of a barrier metal such as nickel is desirably formed. For example, the cap frame50can be formed by stamping a sheet of the base metal, and then electroplating the barrier metal onto the stamped sheet. The cap frame50may also be provided with a joining metal such as tin, lead, solder or eutectic composition, to facilitate adhesion to the metal base pattern on the chip, as described above.

An alternative embodiment of a cap frame51is illustrated inFIG. 11B. The cap frame51of this embodiment differs from the above-described embodiment in that the members55on some sides57of each cap have substantial area and fill the space between opposing sides of caps. Other sides59of each cap are left open to permit access to contacts on the chip by electrical connecting elements.

An individual cap52of cap frame50(FIG. 11A) is illustrated inFIG. 11C, showing connecting members, raised edges41and cavity53. The capped chip56, shown inFIG. 11D, is formed by joining the cap frame50to an array of chips8according to processes described above relative toFIG. 9except that there is no mandrel. The cap frame50as joined to chips8is then severed into individual chips by severing the cap frame simultaneously with the chips. A cross-sectional view through lines2-2of the capped chip56shown inFIG. 11Dis substantially as shown and described above relative toFIG. 9. Optionally, the capped chip can be further processed into an assembly, as discussed above with reference toFIGS. 10A through 10C.

Another embodiment is now described with reference toFIGS. 12-16, in which caps are fabricated from microelectronic substrates, e.g., semiconductor substrates. In this embodiment, as illustrated inFIG. 12, a cap is formed by a depression202in a semiconductor substrate200such as one adapted to include one or more passive devices such as resistors, inductors or capacitors, as commonly referred to as “integrated passives on chip” (IPOC). The semiconductor substrate may even include one or more active devices (as, for example, transistors and logic gates) therein.

A microelectronic substrate200, e.g., a semiconductor substrate, having a depression202is shown in plan view inFIG. 12and a cross-section thereof through lines13-13inFIG. 13. The microelectronic substrate200includes a plurality of first terminals204for providing electrical interconnection to a chip. The first terminals204are conductively coupled to conductors206, which in turn, are conductively coupled, directly or indirectly, i.e., through one or more devices (e.g., passive devices) on microelectronic substrate200, to a second set of terminals208. The microelectronic substrate200is preferably fabricated as one of many units of a wafer using conventional wafer fabrication processes, and then later diced to form a singulated die. In the description to follow, processing of the microelectronic substrate200is desirably performed while units thereof remain attached to each other, at least at a south edge205, a north edge207, or both, and only singulated after units have been fully processed and joined to chips.

FIGS. 14 and 15illustrate the preparation of the microelectronic substrate200prior to joining to the chip. A first metal layer213(FIG. 15) is provided at least on edges of the depression202by depositing a metal such as copper or aluminum, followed by a barrier metal such as nickel. Thereafter, a joining metal layer214such as tin, solder, lead or eutectic composition is formed over the metallized areas, to facilitate later joining the substrate200to a chip. These metal layers213and214are also formed on terminals204of substrate200for facilitating electrical interconnection with the chip. The metal layers213and214, which are provided at least on all the edges of depression202, are used to form a seal later between the microelectronic substrate200and the chip.

In this step, since the depression202in the microelectronic substrate200already provides a well-defined, rigid or semi-rigid internal cavity, the metallized areas need not extend much in either direction beyond the edges of the depression202and the first terminals204, and can be formed by contact lithography, for example. When the metallized areas are provided only in the vicinity of the edges210, this permits the depth212of the depression202to be less than that required than if the entire interior surface of the depression202were to be metallized. Alternatively, the metallized areas need not be confined to only the edges of the depression202, as other needs, such as shielding from electromagnetic interference, may favor metallizing the entire depression202.

Next, as shown inFIG. 16, a chip8is joined to the microelectronic substrate200to form a capped chip216such that the active area12of the chip8faces the depression202. The microelectronic substrate200is joined to the chip8in such manner that a front (terminal-bearing) surface of the microelectronic substrate200faces the front surface9of the chip8. The microelectronic substrate200also extends beyond peripheral edges13of the chip, such that the terminals208are not covered by the chip8.

As discussed above and as depicted inFIGS. 1 and 2, the chip8has a metal base pattern26and contacts14and16. As shown at27, contacts14and16are desirably metallized, prior to joining the microelectronic substrate to the chip8, with a barrier metal such as nickel, followed by a protective metal (e.g., gold, platinum or palladium), to facilitate mating of the chip to the microelectronic substrate200. The joining step is performed by soldering, or by reflowing of the joining metal214to corresponding metal patterns of the chip8including the metal base pattern26and contacts14,16of the chip8. In this embodiment, as well, the joining step desirably is performed in either an evacuated chamber or under conditions in which little or no oxygen is present in the ambient.

Because the chip8and the microelectronic substrate200are both desirably made of a semiconductor material, which can be the same semiconductor material, a joined assembly216can be provided having the same coefficient of thermal expansion (CTE) for both chip8and microelectronic substrate200. This facilitates alignment, despite expansion or contraction of the elements due to temperature fluctuations, particularly where the joining step is performed while the substrate200is part of a larger wafer or unit. Moreover, the matched CTEs of the cap200and chip8help to limit stresses imposed on the bonds at the seal during service.

Thereafter, the capped chip216is joined by further processing to another element of an electronic assembly (not shown) by any of several techniques for interconnecting the terminals208to another element. For example, terminals208can be wire-bonded to elements of a lower circuit panel (not shown) or lead frame (not shown). Alternatively, the second set of terminals208of the joined assembly216can be directly connected to frangible leads of a lead frame (not shown) of a package, as described in the aforementioned U.S. patent application Ser. No. 10/786,825 and U.S. Provisional Application Nos. 60/449,673 and 60/456,737. Thereafter, the capped chip216can be encapsulated together with the other element in an encapsulant, desirably being elastomeric, for protecting the connections between external terminals208and the other element (not shown), despite changes in temperature that may cause the capped chip216and the other element to move relative to each other.

A third embodiment is illustrated with reference toFIGS. 17-25. As shown inFIG. 17, a dielectric panel100is provided with a metal layer102thereon. The dielectric panel100is desirably provided as a flexible membrane extending tape-like or web-like in one or more horizontal directions. Alternatively, the dielectric panel100can be a rigid or semi-rigid member including elements commonly used in the fabrication of circuit boards, e.g., a polymer, epoxy, fiberglass mesh, BT resin, polyimide and the like.

The metal layer102provides an etch stop and a means of holding portions of the dielectric panel100together during subsequent processing. As shown inFIGS. 18 and 19, openings108are formed in the first metal layer102corresponding to locations where openings in the dielectric panel100will be subsequently formed. As shown inFIGS. 18 and 20, a depression104is formed in the dielectric panel100, e.g., as by a masked etch, and then a layer of metal is deposited thereover as a cap metal layer106. The cap metal layer106is formed by a series of metal depositions such as those described above with respect toFIGS. 6 and 7. The openings108can be made by a photolithographic masked etch, for example. The openings108can be formed either before or after the step in which second metal layer106is deposited to cover depression104.

As shown inFIGS. 20-21, openings110are formed in the second metal layer106which correspond to the locations of openings108in the first metal layer. Again, such openings can be made by a photolithographic masked etch, for example. Alternatively, openings110can be formed at the same time the second metal layer is formed, i.e., by selective deposition of the metal to cover dielectric panel100in all areas other than the openings110. For example, blocking features can be first formed which correspond to the locations of the openings, and the metal then deposited, such that the blocking features prevent the metal from being deposited in the openings. The blocking features are then subsequently removed.

As shown inFIG. 22, the cap structure112is now joined to the chip8, thereby forming a capped chip114having a cavity over an area of the chip8. Desirably, an adhesive (not shown) is provided for joining the cap structure112to the chip8, since an adhesive can be applied and set generally at room temperature or within the range of temperatures at which the chip is expected to operate, such that the joining of the chip8to the cap structure112does not require a temperature sufficient to melt or reflow metal. If an adhesive is used, it should be applied only to areas that are outside of the depression104when applied to the cap structure112. Otherwise, when applied to the chip8, the adhesive should be applied to the metal base pattern26, and not to the active area116or the contacts of the chip.

Alternatively, the cap structure112may be joined to the chip8by means of a reflowable metal such as tin, lead, solder or eutectic composition, which is provided to connection points, i.e., to metal base pattern26formed prior thereto on the chip8, by providing such ref lowable metal on parts of the cap structure112that lie outside of the depression104, prior to joining the chip8to the cap structure112.

Next, as illustrated inFIGS. 23 and 24, steps are performed to provide a conductive interconnection to contacts14and16at an exposed plane126above the front surface9of the chip8. First, any material of the dielectric panel100which remains between the original openings108and110(FIG. 21) in the first metal layer102and second metal layer106is removed to form openings124, as by ablation using a CO2laser, for example. Alternatively, the openings124in the dielectric panel100can be formed by etching using an etchant which attacks the dielectric in layer100, but which does not substantially attack the material of the first and second metal layers and the underlying contacts14and16of the chip8. In another example, laser drilling can be performed, stopping on the contacts14,16. As another alternative, openings in the dielectric panel100can be made at a time prior to joining the cap structure112to the chip8, by any of the above-described techniques.

Thereafter, a third layer of metal120is formed covering the capped chip114. In addition, the third metal layer120forms a conductive layer adhering to contacts14and16with which the chip8may be subsequently interconnected to external devices.

The third layer of metal120is desirably formed by sputtering. The third layer of120is also desirably formed by sequentially sputtering a series of metals such as those used to form the cap structure112. For example, if the second metal layer106of the cap structure includes copper, the third metal layer120desirably includes copper. A layer of nickel may then be sputtered over the copper as a compatible barrier metal layer for providing a surface for subsequent adhesion thereto. Thereafter, a reflowable joining metal such as tin, lead, solder or eutectic composition is preferably deposited. Other than by sputtering, the third metal layer120can be deposited by any of several well-known techniques such as chemical vapor deposition (CVD), seeding and electroless plating, electroplating, and the like. Thereafter, as shown in the plan view ofFIG. 24, the third metal layer120is patterned, as by contact lithography, and etched, as by anisotropic vertical etching (e.g., reactive ion etching). These steps result in the creation of isolating grooves122in the cap structure112surrounding the locations of the contacts of the chip. As a result of such etching, first, second and third metal layers are removed to electrically isolate the contacts from the rest of the third metal layer120.

Thereafter, as illustrated inFIG. 25A, connectors128including a joining metal such as tin, lead, solder or eutectic composition are applied to contact the third metal layer120in the areas inside the isolation patterns where the third metal layer120is joined to contacts14,16. The connectors128desirably extend above the exposed plane126defined by the uppermost surface of third metal layer120. The connectors128enable the capped chip114to be mounted to another assembly such as a circuit panel, e.g., flexible circuit, printed wiring board, etc., multi-chip carrier, or other assembly. The joining metal connectors128can be applied by any of several commonly used methods such as conductive paste screening or solder screening, or screening of pre-formed solder balls into the openings, followed by heating to join the solder balls to the underlying contacts14,16.

Thereafter, the capped chip114can be mounted by way of another assembly, such as by any of several known techniques, e.g., flip chip attach, wire bonding, mating with a lead frame, or the like such as described in the aforementioned U.S. Provisional Application Nos. 60/449,673 and 60/456,737.

FIG. 25Billustrates a variation of the embodiment shown and described above with reference toFIG. 25A. As shown inFIG. 25B, the cap includes inner terminals274patterned in the second metal layer106. In an embodiment of the invention, the terminals274are patterned at the same time that the second metal layer106is patterned. The capped chip further includes a joining metal276for joining the contacts, e.g., contact16, of the chip, to the terminals274of the cap. Connectors278are provided in openings284of the dielectric panel100according to such methods as described above.

Similarly,FIG. 25Cillustrates a variation of the embodiment described above relative toFIG. 25B, in which the cap includes outer terminals279patterned in the first metal layer102and inner terminals282patterned in the second metal layer106. In a process of making the structure according to an embodiment of the invention, the inner terminals282are formed by patterning openings284in the dielectric panel100simultaneously when forming the depression104. This step is preferably performed after forming the first metal layer102, as described above with reference toFIG. 18. Thereafter, the second metal layer106is deposited and patterned to simultaneously form the cap and inner terminals282. In another variation of this embodiment, the openings284are patterned after deposition of the second metal layer106to extend through the second metal layer and dielectric panel100, leaving the outer terminals279in place. Thereafter, a joining metal is provided in the openings284, after which the cap is joined to the chip while the joining metal simultaneously connects the contact16of the chip to the outer terminal279.

In a further embodiment of the invention, a cap substrate300(FIGS. 26-27) is formed from an air-impermeable dielectric material such as a ceramic or glass having a front surface310and an oppositely-directed rear surface320. The substrate includes a plurality of cap regions301, each having a set of metallic features to be associated with one chip as discussed below. The metallic features of each cap region include an annular cap metal pattern332on the front surface310of the substrate, as well as ground metal terminals322on the rear surface320of the substrate and conductive ground vias316connecting the cap metal patterns with the ground metal terminals for connecting the cap metal pattern332to ground. The metallic features of each cap region301further include active bonding contacts302on the front surface, active terminals304on the rear surface and active vias306connecting the active bonding contacts with the active terminals. Although only two active bonding contacts302are depicted in each cap region inFIG. 26, any number of active bonding contacts may be used. As seen inFIG. 26, the active bonding contacts302of each cap region are disposed inside of the annular cap metal pattern332of such region. The metallic features of each cap region may optionally include a ground contact334disposed inside of the cap metal pattern on the front surface and connected to the cap metal pattern extending along the front surface by trace333.

As best seen inFIG. 27, the cap metal patterns332and active bonding contacts302project from the front surface310by a projection distance312corresponding to the depth of the cap, most commonly about 20 to about 30 microns. The ground contacts334(FIG. 26), which are not visible in the view provided inFIG. 27, also project from the front surface310by the projection distance312. The metallic features may be formed using conventional techniques used in making ceramic or glass circuitized substrates, such as masking and selective deposition of a thin flash metal, typically by sputtering or electroless plating, followed by electroplating. In another process, a nonselective flash metal deposition is followed by masking and back-etching to remove the flash layer in areas covered by the mask and then followed by electroplating. Alternatively, the projecting features may be formed by initially forming the substrate with planar features having minimal or no projection and then masking the rear surface320and selectively depositing metal on the metallic features on front surface310. In a further alternative, the projecting metallic features on the front surface may be formed by providing a relatively thick metallic layer on the front surface, as by laminating the metal layer to the substrate, followed by selective etching to leave only the projecting features.

The tips or extremities340of the projecting features bear bonding metals as, for example, a solder or eutectic bonding composition as discussed above.

FIG. 28is a cross-sectional view illustrating a wafer348containing a plurality of chips350each to be joined to a respective cap region301of the cap substrate300. Each chip350includes ground contacts352for bonding to the raised cap metal patterns332of a cap substrate300and active contacts354for bonding to the active bonding contacts302.

FIG. 29illustrates an assembly of capped chips370each including a chip350, as joined to a cap301of the cap wafer300. Preferably, the cap metal patterns332and active bonding contacts302on the cap regions301are simultaneously joined to corresponding ground contacts352and active contacts354on the front surfaces of the chips350by application of heat and pressure. Desirably, the joining process is performed as a fluxless process in a vacuum or substantially oxygen-free ambient to avoid oxidation products and/or to provide a low-oxygen environment within the cavity enclosed by the cap301, as described above with reference toFIG. 8. In a particular embodiment, a solderless joining process is utilized to achieve a higher melting temperature point bond between the caps301and the chips350than in a soldered bond.

Thereafter, joining features such as solder bumps or solder balls356are applied to the metal patterns on the rear surface320of the cap substrate300. This is performed, for example, by applying a patterned solder mask (not shown) to the rear surface of the cap substrate and then depositing solder balls in the openings of the solder mask, followed by removing the solder mask. After bonding the cap substrate to the chips of the wafer and applying solder balls to the rear surface of the caps, the bonded chips and caps are severed along lines360to provide individual capped chips.

Desirably, the cap substrate is formed of a material such as molybdenum, a semiconductor material, and glass materials having a CTE close to or matching that of the wafer. Desirably, the size and shape of each cap301are the same as that of each chip350. The resulting capped chip370has the same area as the chip350, making a desirably compact unit for assembly to a larger module, including a chip carrier or circuit panel such as described above with reference toFIGS. 10B and 10C.

In a variation of that shown inFIGS. 26-29, the cap metal patterns332extend across the edges308of the cap regions, such that they are separated between respective capped chips370when the capped chips370are severed from one another.

FIG. 30illustrates an alternative arrangement in which a cap substrate400has a plurality of cap metal patterns432, a plurality of active bonding contacts402and a plurality of ground contacts434exposed at a top surface of the substrate400. This arrangement differs from the arrangement described above relative toFIGS. 26-29, in that the active bonding contacts402and ground contacts434are disposed outside of the cap metal patterns432. Otherwise, fabrication and assembly techniques are the same as those described above with reference toFIGS. 26-29.