Single input class-AB rail-to-rail output stage

An amplifier with a single-input class-AB output stage comprises an input stage providing a signal to an output stage. The output stage comprises a current-splitting stage having a bias current and providing at least two intermediate output currents, and a drive stage receiving the two intermediate output currents and driving an output signal having a positive side and a negative side.

CROSS-REFERENCE TO RELATED APPLICATIONS

TECHNICAL FIELD

The present disclosure relates generally to amplifiers, and more particularly to a single-input class-AB rail-to-rail output stage.

BACKGROUND

In an amplifier circuit, it is often desirable for the output signal to have the freedom to swing “rail-to-rail” in operation, meaning that the output should be able to swing close to the upper “supply” voltage, sometimes called “V+” “VCC” or “VDD,” and the lower supply voltage, typically called “ground,” “V−,” “VSS,” or “VEE.” Additionally, it is often desirable that the output stage offer class-AB operation, meaning that the output signal current peak not be limited by the quiescent bias current.

In some applications, output stages having a single input terminal at an input DC voltage close to the supply are critical to the operation of the preceding stage. In the prior art, this may be achieved with a p-type common-gate input stage such as a p-type MOSFET (sometimes called a “pMOS”) cascode.

In some prior art amplifiers a signal current out of the cascode device directly controls the control terminal of an output device with no further delay due to non-dominant poles, which helps with high-frequency operation. However, to control the control terminal of the complementary output device, the signal may pass through a “Monticelli” mesh (so called because a mesh of this type was first proposed by Dennis Monticelli, “A Quad CMOS Single-Supply Op Amp with Rail-to-Rail Output Swing,” IEEE Journal of Solid-State Circuits, Vol. SC-21, Nol. 6, Dec. 1986, incorporated herein by reference). That signal may suffer additional delay. For example, an exemplary prior art device may include a pMOS cascode device with its output connected to the gate of an nMOS output device and a Monticelli mesh which has one terminal connected to that same point and the other terminal connected to the gate of a pMOS output device. For the electrical path that the signal follows to control the gate of the pMOS output device, the Monticelli mesh acts as an n-type cascode with a pole given by the 1/gm of the n-type device within the Monticelli mesh and the total capacitance at the node to which the gate of the nMOS output device is connected. The Monticelli mesh then acts as an additional stage contributing a non-dominant pole when the pMOS gate is driven. In some cases, this may provide additional delay for positive output signals.

OVERVIEW OF EXAMPLE EMBODIMENTS

In one aspect, there is disclosed a single-input class-AB output stage comprising: a current-splitting stage comprising: a signal current; a tail current, the signal current and tail current together forming a splitting-stage current; a first cascode three-node transistor wherein the first node receives a cascode biasing voltage, the second node is driven by the splitting-stage current, and the third node provides a first intermediate output current; and a second cascode three-node transistor wherein the first node is biased to the cascode biasing voltage, the second node is driven by the splitting-stage current, and the third node provides a second intermediate output current; whereby the splitting-stage current is split between the second nodes of the cascode transistors and whereby each cascode transistor provides at its third node a current substantially identical to the current provided at its second node; and a drive stage comprising a first intermediate input current receiving the first intermediate output current of the current-splitting stage and a second intermediate input current receiving the second intermediate output current of the current-splitting stage, the first intermediate input current driving a first output three-node transistor and the second intermediate input current driving a second output three-node transistor.

In another aspect, there is disclosed a single-input class-AB output stage comprising: a current-splitting stage having a signal current and a tail current, the sum of the signal current and tail current being an splitting-stage current, and at least one transistor acting as a cascode for the input and providing at least one intermediate output current; and a drive stage comprising at least one intermediate input current supplied by the intermediate output current of the current-splitting stage, the intermediate input current supplying current to a drive circuit including a first output element and a second output element, the second output element having a node in common with the first output element, the common node forming a unified output signal.

In yet another aspect there is disclosed an amplifier comprising an input stage providing a signal current having a positive side and a negative side; and an output stage comprising a current-splitting stage having a tail current and providing at least two intermediate output currents, and a drive stage receiving the two intermediate output currents and driving an output signal having a positive side and a negative side.

DETAILED DESCRIPTION OF EXAMPLE EMBODIMENTS

Because amplifiers in feedback configurations need to be stable for positive and negative output signals, the loop bandwidth needs to be limited to ensure stability for positive and negative signals. This limits important performance metrics such as close-loop bandwidth, distortion, and slew-rate.

In some embodiments, two input currents into the output stage drive both output transistors directly, eliminating the non-dominant pole from the Monticelli mesh. However, this places important constraints on the stage preceding the output stage because the preceding stage must then generate two rather than one drive current.

In an exemplary embodiment of the present specification, a class-AB output stage for an amplifier such as a transconductance amplifier receives only a single signal current. The output stage is subdivided into a current-splitting stage and a drive stage. The current-splitting stage splits the combination of the signal current and a bias current, which can be received from the previous stage or generated within the current-splitting stage, between two cascode transistors, thereby generating two separate intermediate output currents. The two intermediate output currents are provided to a drive stage, which uses one to drive a pMOS transistor to source current, and the other to drive an nMOS transistor to sink current. Because both output transistors are driven directly from the current-splitting stage, the delay to pass through the Monticelli mesh is reduced.

The result is a delay from non-dominant poles that is reduced and much less signal dependent. This allows an increase of the compensating pole frequency by increasing the preceding stage bias current (which increases the transconductance) or by reducing the compensation capacitances. This in turn results into improved closed-loop bandwidth and distortion.

The slew rate is dominated by the peak signal current charging/discharging the capacitance on the gate node for the output transistors. Therefore, increasing the preceding stage bias current, which increases the peak signal current, or reducing the compensation capacitances results into a better and more symmetric slew rate.

Turning now to the figures,FIG. 1is a partial electrical schematic of an exemplary embodiment of a class-AB output stage100according to the present specification. In this embodiment, output stage100comprises a current-splitting stage102and a drive stage104.

Current-splitting stage102receives a positive supply voltage VDD110, for example from a dedicated voltage supply or as provided by a preceding circuit stage. Those having skill in the art will appreciate that VDD110will have many possible values and that in some embodiments, VDD110will be considered a “rail,” meaning a maximum voltage for an amplified signal. A negative supply voltage VSS190is also shown, and in some embodiments will be considered the opposite “rail,” so that at a minimum, no amplified signal can be driven below VSS190, and at a maximum, no amplified signal can be driven above VDD110without an additional voltage converter. By convention, VDD110is spoken of as being the most “positive” voltage and VSS190is spoken of as being the most “negative” voltage. Thus, under appropriate circumstances, either VDDor VSScould be considered a “supply” or “positive” voltage, and under other circumstances, either VDDor VSScould be considered a “ground,” “negative,” or “negative supply” voltage. Those having skill in the art will also recognize that VSS190need be neither an absolute ground (“earth” or “chassis”), nor necessarily negative with respect to earth or chassis ground. Furthermore, “positive” and “negative” may be understood in the art to refer simply to two opposite sides of a difference in potential. Thus, where a signal has a “positive side” and a “negative side,” those with skill in the art will recognize that this may be construed generally to mean that the positive side of the signal includes those portions above a reference voltage, while the negative side of the signal includes those portions below the reference voltage. In some embodiments, a zero point is defined at earth ground or chassis ground and VDD110and VSS190will have values of substantially the same magnitude but opposite sign. In general terms, a signal may be amplified “rail-to-rail” if the circuit provides the ability to drive the amplified output from a voltage at or near VDD110to a voltage at or near VSS190.

In this exemplary embodiment, a signal current120provides an amplified signal from the preceding stage. The input terminal for signal current120may be biased to a desired difference in potential from VDD110. For example, the input terminal for signal current120may be biased to 600 mV below VDD110. A tail current130may also be provided and in some embodiments its negative terminal may be biased to the same potential as the input terminal for signal current120, for example 600 mV below VDD110. Those having skill in the art will recognize that an output signal thus driven to within a small potential difference of the “rails” may still be considered a “rail-to-rail” amplifier output. Rail-to-rail operation is expressly provided as one option but is not necessary to the operation of output stage100. Those having skill in the art will also recognize that tail current130may be, for example, a dedicated current source or a current sourced by a previous stage of the circuit, or a combination of both, or a combination of current sources. Tail current130and signal current120are combined to form a single splitting-stage current134. In this exemplary embodiment, current-splitting stage cascode transistors122are biased by tail current130to 1.6 mA, and cascode transistors122carry this bias current combined with signal current120, which may be much smaller in magnitude than tail current130.

Splitting-stage current134is provided to two cascode transistors122, which in this exemplary embodiment are both pMOSs. Cascode transistors122receive a bias voltage124at their gates. Bias voltage124may be an actively- or passively-generated bias voltage. Each cascode transistor122provides at its drain node substantially the current provided at its source node, but the drain current is decoupled from the voltage at the drain node. In some embodiments, cascode transistors122are intended to be substantially identical and each is configured to receive approximately one-half of splitting-stage current134, 0.8 mA in the absence of signal in this exemplary embodiment. In other embodiments, the cascode transistors may have differing transconductance values and be configured to each receive a proportional share of the current. For example, if cascode transistor122-1has half the transconductance value of cascode transistor122-2, then cascode transistor122-1will receive one-third of the current (for example, 0.53 mA in the absence of signal) and cascode transistor122-2will receive two-thirds of the current (for example, 1.07 mA in the absence of signal). Cascode transistor122-1provides a first intermediate output current180-1, and cascode transistor122-2provides a second intermediate output current180-2.

Advantageously, cascode transistors122enable output stage100to perform as though it had two dedicated input currents.

Those with skill in the art will recognize that while this exemplary embodiment has been disclosed using p-type transistors for cascode transistors122, an exactly analogous circuit may be built with n-type cascode transistors by essentially turning the circuit upside-down (seeFIG. 3).FIG. 3shows a circuit analogous to that ofFIG. 1obtained by swapping VDD110for VSS190, changing the n-type transistors for p-type transistors, and inverting the polarity of the current sources. It is intended that the n-type cascode circuit variation be treated as exactly equivalent to the p-type cascode circuit ofFIG. 1.

Those with skill in the art will also recognize that althoughFIG. 1is disclosed with an exemplary embodiment using MOS FETs, other embodiments may employ other types of non-passive devices with three or more nodes, such as triodes, bipolar junction transistors (BJT), and JFETs by way of non-limiting example. For ease of reference, all such devices are referred to herein as “three-node transistors.” In general, a three-node transistor will have at least three nodes, which can be referred to as a first node (base, gate, or similar), second node (source, emitter, or similar), and third node (drain, collector, or similar).

Continuing withFIG. 1, drive stage104is configured to receive intermediate input currents180, which in this exemplary embodiment are identically the intermediate output currents180of current-splitting stage102. Output transistor152and output transistor154are provided and each has its drain node connected to the drain node of the other. Two intermediate input currents180are provided so that the gate nodes of output transistors152,154can each be driven directly. For example, when current signal120is positive, the signal current out of the drains of cascode devices122is positive, which increases the signal voltage at the gates of output transistor152and154, which reduces the current sourced by output transistor152and increases the current sourced by output transistor154, which decreases the output signal voltage. By driving the gates of output transistors152,154with separate intermediate input currents180, substantial delays or phase shifts can be avoided in the output signal150.

In some embodiments, a Monticelli mesh140is also provided. Current-splitting stage102preliminarily but imperfectly splits splitting-stage current134into currents180-1and180-2. This fast but imperfect split is subsequently refined by Monticelli mesh140. Monticelli mesh140may steer a fraction of intermediate input current180-1from the node to which the gate of transistor154connects to the node to which the gate of transistor152connects; similarly, it may steer intermediate input current180-2from the gate of transistor152to the gate of transistor154. For example, when current signal120is positive, intermediate input currents180out of the drains of cascode devices122increase, and Monticelli mesh140steers any unnecessary fraction of intermediate input current180-1from the gate node of output transistor154to the gate node of output transistor152. Similarly, Monticelli mesh140steers any unnecessary fraction of intermediate input current180-2from the gate node of transistor152to the gate node of transistor154. This steering is subject to some delay but it has negligible impact on the overall delay of the output stage.

Two stability compensation capacitors170are provided. An exemplary reference capacitance “C” is used throughout this specification, and stability compensation capacitor170-1may be much smaller than C and may be connected to p-type output transistor152, while stability compensation capacitor170-2may be approximately C and may be connected to n-type output transistor154.

A load current160is also shown, connected to the VSS-side of Monticelli mesh140. Load current160and tail current130together bias cascode devices122in the current-splitting stage and Monticelli mesh140in the drive stage.

In some embodiments, the voltage range for the DC voltage of the input terminal receiving signal current120can be widened by driving the output transistor152backgate beyond VDD110, to increase the source-to-drain voltage across cascode transistor122-2. For example, charge pump156may be used to drive the backgate of output transistors152beyond VDD110, which increases headroom across tail current130while maintaining cascode transistors122in saturation.

FIG. 2is a partial electrical schematic of a low-noise amplifier200disclosing an exemplary use of output stages100in situ. This circuit is similar to the one described in U.S. Pat. No. 7,088,179. Low-noise amplifier200includes an input stage210, two output stages100, with each output stage100providing a signal to a load250, loads for amplifier circuits being well known in the art. In some embodiments, loads250-1and250-2may be a single load250, in which case, each output stage100will drive one side of load250.

Two supply voltages are disclosed, VCC280, and VEE290. In some embodiments, VCC280may substantially match or be the same node as VDD110, while VEE290may substantially match or be the same node as VSS190. Input stage210includes two transistors220acting as an input pair222. In the exemplary embodiment, input pair222receives a signal at the bases260of transistors220and provides current signals232which constitute the input current to output stages100. Input stage load currents230and input stage tail current270bias the input pair transistors220, for example to 2.5 mA each.

A resistive feedback network240feeds a fraction of the output signal (present at the outputs of output stages100) back to input stage210by injecting the signal at the emitters of transistors220. Those skilled in the art will recognize that the resistive feedback network shown is just one possible embodiment of possible feedback networks, which may or not be resistive and may or not be configured as a series string of passive devices. At a node in feedback network240, input stage tail current270is provided.

FIG. 3is a partial schematic of an alternative embodiment of output stage100. Components of this output stage100are functionally identical. In this embodiment, n-type cascode transistors322have been substituted for the p-type cascode transistors122ofFIG. 1and appropriate modifications, well within the grasp of those having skill in the art, have been made to account for differences in polarity. For example, load current160is now connected between VDD110and nMOS output transistor152, while tail current130biases n-type cascode transistors322and sources current to VSS190. This alternative embodiment is disclosed to illustrate that an “upside down” version of output stage100is the equivalent of the version ofFIG. 1. To state expressly what is inherent to the disclosure of this specification, for purposes of the appended claims, any claim that is drawn to output stage100as shown inFIG. 1is also expressly intended to be drawn to output stage100as shown inFIG. 3.

FIG. 4is a partial schematic illustrating an exemplary method of actively biasing the gates of cascode transistors122. In particular, it may be desirable to actively bias the gates to compensate for perturbations in the voltage at the terminal receiving signal current120. Thus, in this exemplary embodiment, an operational amplifier410is provided with DC voltage source430generating a DC voltage which is provided to the non-inverting input of operational amplifier410. The inverting input of operational amplifier410connects to the voltage at terminal for signal current120to detect perturbations. The output of operational amplifier410is provided directly to the gates of cascode transistors122. Operational amplifier410thereby corrects for variations in voltage at the output-stage input terminal that arise as a result of signal current120.

FIG. 5is a partial electrical schematic disclosing an alternative embodiment of an output stage according to the present specification. In this embodiment, current-splitting stage502includes a tail current130. The current from this current source and signal current120together drive a single folding cascode522. This provides a single intermediate output current to drive stage504.

Drive stage504receives a single intermediate input current from folding cascode522. The current output of folding cascode522drives pMOS output transistor152directly. A stability compensating capacitor may also be provided at this node, with an exemplary value of 2.6 C.

The current output of folding cascode522must pass through Monticelli mesh140before reaching nMOS154gate. A stability compensation capacitor may also be provided at this node, with an exemplary value of 4.2 C.

In this embodiment, additional delay is experienced in passing through Monticelli mesh140to control the nMOS output transistor154, which translates into larger compensation capacitors (2.6 C and 4.2 C instead of <<C and C) and ultimately into degraded closed-loop bandwidth, distortion, and slew rate.

In operation, exemplary amplifiers built according to the exemplary embodiments ofFIG. 1andFIG. 5may be compared in simulation to an amplifier design conducted with identical constraints using a prior art output stage.

After simulation, the following performances were observed:

Thus, the output stage ofFIG. 1significantly improved on prior art devices, particularly with respect to closed-loop bandwidth, slew-rate, and loop-gain at signal frequencies. Furthermore, the output stage of the present specification is observed to significantly improve on other prior art devices having a closed-loop bandwidth no greater than 58 MHz, a slew rate no greater than 100 MV/s, and loop gain at 5 MHz no greater than 19.4 dB.

In the discussions of the embodiments above, any capacitors, clocks, DFFs, dividers, inductors, resistors, amplifiers, switches, digital core, transistors, and/or other components can readily be replaced, substituted, or otherwise modified in order to accommodate particular circuitry needs. Moreover, it should be noted that the use of complementary electronic devices, hardware, software, etc. offer an equally viable option for implementing the teachings of the present disclosure.

In one example embodiment, any number of electrical circuits of the FIGURES may be implemented on a board of an associated electronic device. The board can be a general circuit board that can hold various components of the internal electronic system of the electronic device and, further, provide connectors for other peripherals. More specifically, the board can provide the electrical connections by which the other components of the system can communicate electrically. Any suitable processors (inclusive of digital signal processors, microprocessors, supporting chipsets, etc.), memory elements, etc. can be suitably coupled to the board based on particular configuration needs, processing demands, computer designs, etc. Other components such as external storage, additional sensors, controllers for audio/video display, and peripheral devices may be attached to the board as plug-in cards, via cables, or integrated into the board itself.

In certain contexts, the features discussed herein can be applicable to medical systems, scientific instrumentation, wireless and wired communications, radar, industrial process control, audio and video equipment, current sensing, instrumentation (which can be highly precise), and other digital-processing-based systems.

Moreover, certain embodiments discussed above can be provisioned in digital signal processing technologies for medical imaging, patient monitoring, medical instrumentation, and home healthcare. This could include pulmonary monitors, accelerometers, heart rate monitors, pacemakers, etc. Other applications can involve automotive technologies for safety systems (e.g., stability control systems, driver assistance systems, braking systems, infotainment and interior applications of any kind). Furthermore, powertrain systems (for example, in hybrid and electric vehicles) can use high-precision data conversion products in battery monitoring, control systems, reporting controls, maintenance activities, etc.

In yet other example scenarios, the teachings of the present disclosure can be applicable in the industrial markets that include process control systems that help drive productivity, energy efficiency, and reliability. In consumer applications, the teachings of the signal processing circuits discussed above can be used for image processing, auto focus, and image stabilization (e.g., for digital still cameras, camcorders, etc.). Other consumer applications can include audio and video processors for home theater systems, DVD recorders, and high-definition televisions. Yet other consumer applications can involve advanced touch screen controllers (e.g., for any type of portable media device). Hence, such technologies could readily part of smartphones, tablets, security systems, PCs, gaming technologies, virtual reality, simulation training, etc.