Nanowire tunnel field effect transistors

A method for forming a nanowire tunnel field effect transistor (FET) device includes forming a nanowire suspended by a first pad region and a second pad region, forming a gate around a portion of the nanowire, forming a protective spacer adjacent to sidewalls of the gate structure and around portions of the nanowire extending from the gate structure, implanting ions in a first portion of the exposed nanowire, removing a second portion of the exposed nanowire to form a cavity defined by the core portion of the nanowire surrounded by the gate structure and the spacer, exposing a silicon portion of the substrate, and epitaxially growing a doped semiconductor material in the cavity from exposed cross section of the nanowire, the second pad region, and the exposed silicon portion to connect the exposed cross sections of the nanowire to the second pad region.

FIELD OF INVENTION

The present invention relates to semiconductor nanowire tunnel field effect transistors.

DESCRIPTION OF RELATED ART

A nanowire tunnel field effect transistor (FET) includes doped portions of nanowire that contact the channel region and serve as source and drain regions of the device. The source region may include, p-type doped silicon material, while the drain region may include n-type doped silicon material.

BRIEF SUMMARY

In one aspect of the present invention, a method for forming a nanowire tunnel field effect transistor (FET) device includes forming a nanowire suspended by a first pad region and a second pad region over a buried oxide (BOX) portion of a substrate, the nanowire including a core portion and a dielectric layer around the core portion, forming a gate structure around a portion of the dielectric layer, forming a protective spacer adjacent to sidewalls of the gate structure and around portions of the nanowire extending from the gate structure, implanting a first type of ions in a first portion of the exposed nanowire, removing a second portion of the exposed nanowire to form a cavity defined by the core portion of the nanowire surrounded by the gate structure and the spacer, removing a portion of the BOX portion to expose a silicon portion of the substrate between the second pad region and the spacer, and epitaxially growing a doped semiconductor material in the cavity from exposed cross section of the nanowire, the second pad region, and the exposed silicon portion to connect the exposed cross sections of the nanowire to the second pad region.

In another aspect of the present invention, a nanowire tunnel field effect transistor (FET) device includes a channel region including a silicon portion having a first distal end and a second distal end, the silicon portion is surrounded by a gate structure disposed circumferentially around the silicon portion, a drain region including an n-type doped silicon portion extending from the first distal end, a cavity defined by the second distal end of the silicon portion and an inner diameter of the gate structure, and a source region including a doped epi-silicon portion epitaxially extending from the second distal end of the silicon portion in the cavity, a first pad region, and a portion of a silicon substrate.

DETAILED DESCRIPTION

FIGS. 1-8illustrate a cross-sectional views of a method for forming a FET device. Referring toFIG. 1, a silicon on insulator (SOI) layer102is defined on a buried oxide (BOX) layer104that is disposed on a silicon substrate100. The SOI layer102includes a SOI pad region106, a SOI pad region108, and a silicon nanowire110. A gate112is formed around a portion of the nanowire110, and capped with a capping layer116that may include, for example, a polysilicon material. A hardmask layer118such as, for example, silicon nitride (Si3N4) is formed on the capping layer116. The gate112may include layers of materials (not shown) such as, for example, a first gate dielectric layer (high K layer), such as silicon dioxide (SiO2) around the nanowire110, a second gate dielectric layer (high K layer) such as hafnium oxide (HfO2) formed around the first gate dielectric layer, and a metal layer such as tantalum nitride (TaN) formed around the second gate dielectric layer.

FIG. 2illustrates spacer portions202formed along opposing sides of the capping layer116. The spacers are formed by depositing a blanket dielectric film such as silicon nitride and etching the dielectric film from all horizontal surfaces by reactive ion etching (RIE). The spacer portions202are formed around portions of the nanowire110that extend from the capping layer116and surround portions of the nanowires110.

FIG. 3illustrates the resultant structure following the implantation and activation of n-type ions in the SOI pad region106and the adjacent portion of the nanowire110that defines a drain region (D). The ions may be implanted by for example, forming a protective mask layer over the SOI pad region108and the adjacent nanowire110prior to ion implantation. Alternatively, the ions may be implanted at an angle such that the capping layer116and spacer202may absorb ions and prevent ions from being implanted in an undesired region.

FIG. 4illustrates the resultant structure following the formation of a conformal hardmask layer402over the exposed surfaces of the device. The conformal hardmask layer402may include for example, silicon dioxide, silicon nitride, or any other sacrificial material that will inhibit epitaxial growth and may be easily removed.

FIG. 5illustrates the resultant structure following removal of a portion of the nanowire110that extended between the SOI pad region108and the channel region of the gate112. The portion of the nanowire110may be removed by, for example, patterning and removing a portion of a portion of the conformal hardmask layer402and performing an etching process such as, for example, a wet chemical or vapor etching process that etches exposed silicon, and removes the exposed silicon nanowire110. The portion of the conformal hardmask layer402is removed using a process that preserves the conformal hardmask layer402in the region that will become the drain region (described below); the removal process is controlled to avoid compromising the integrity of the hardmask layer118over the gate112and the integrity of the spacer202.

FIG. 6illustrates the resultant structure following an optional isotropic etching process may be performed to remove a portion of the nanowire110that is surrounded by the spacer wall202and the gate112to recess the nanowire110into the gate112, and form a cavity602defined by the gate112, the nanowire110and the spacer wall202. Alternate embodiments may not include the isotropic etching process that forms the cavity602. The lateral etching process that forms cavity602may be time based. Width variation in spacer202may lead to variations in the position of the edges of the recessed nanowire110. The etching rate in the cavity602depends on the size of the cavity, with narrower orifice corresponding to slower etch rates. Variations in the nanowire size will therefore lead to variations in the depth of cavity602.

FIG. 7illustrates the resultant structure following the removal of an exposed portion of the BOX layer104that exposes a portion of the silicon substrate100.

FIG. 8illustrates cross-sectional views of the resultant structures following a selective epitaxial growth of silicon to form a source region (S)802. The source region802is epitaxially grown in the cavity602(ofFIG. 7) from the exposed nanowire110in the gate112to form the source region802. The source region802is epitaxially grown from the SOI pad region108and the exposed portion of the silicon substrate100. The source region802is formed by epitaxially growing, for example, in-situ doped silicon (Si), a silicon germanium (SiGe), or germanium (Ge) that may be p-type doped. As an example, a chemical vapor deposition (CVD) reactor may be used to perform the epitaxial growth. Precursors for silicon epitaxy include SiCl4, SiH4combined with HCL. The use of chlorine allows selective deposition of silicon only on exposed silicon surfaces. A precursor for SiGe may be GeH4, which may obtain deposition selectivity without HCL. Precursors for dopants may include B2H6for p-type doping. Deposition temperatures may range from 550° C. to 1000° C. for pure silicon deposition, and as low as 300° C. for pure Ge deposition.

Once source region (S)802is formed, the doping may be activated by, for example, a laser or flash anneal process. The laser or flash annealing may reduce diffusion of ions into the channel region804of the gate112, and result in a high uniform concentration of doping in the source region802with an abrupt junction in the nanowires110.

The hardmask layer402and118may be removed by, for example, a RIE process. A silicide may be formed on the source region802the drain region D and the gate region. Examples of silicide forming metals include Ni, Pt, Co, and alloys such as NiPt. When Ni is used the NiSi phase is formed due to its low resistivity. For example, formation temperatures include 400-600° C. Once the silicidation process is performed, capping layers and vias for connectivity (not shown) may be formed and a conductive material such as, Al, Au, Cu, or Ag may be deposited to form contacts.