Post passivation metal scheme for high-performance integrated circuit devices

A new post-passivation metal interconnect scheme is provided over the surface of a IC device that has been covered with a conventional layer of passivation. The metal scheme of the invention comprises, overlying a conventional layer of passivation, thick and wide metal lines in combination with thick layers of dielectric and bond pads. The interconnect system of the invention can be used for the distribution of power, ground, signal and clock lines from bond pads to circuits of a device that are provided in any location of the IC device without introducing significant power drop. No, or smaller ESD circuits are required due to the low impedance post-passivation interconnection, since any accumulated electrostatic discharge will be evenly distributed across all junction capacitance of the circuits on the chip. The post passivation metal scheme is connected to external circuits through bond pads, solder bonding, TAB bonding and the like. A top layer of the interconnect metal scheme is formed using a composite metal for purposes of wirebonding, the composite metal is created over a bulk conduction metal. A diffusion metal may be applied between the bulk metal and the composite metal, in addition a layer of Under-Barrier-Metal (UBM) may be required underneath the bulk conduction metal.

RELATED PATENT APPLICATION

This application is related to MEG01-010, Ser. No. 09/998,862, filed on Oct. 24, 2001, assigned to a common assignee.

BACKGROUND OF THE INVENTION

(1) Field of the Invention

The invention relates to the fabrication of integrated circuit devices, and more particularly, to a post passivation scheme that provides low-resistance metal interconnects in addition to bond pads on the surface of an Integrated Circuit device that is covered with a conventional layer of passivation.

(2) Description of the Prior Art

Improvements in semiconductor device performance are typically obtained by scaling down geometric dimensions of the Integrated Circuit (IC) devices, resulting in decreasing the cost per device while improving device performance. Metal connections, which connect the Integrated Circuit to other circuit or system components, become of relative more importance and have, with the further miniaturization of the IC, an increasingly negative impact on device performance. Parasitic capacitance and resistance of the metal interconnections increase, which degrades the chip performance significantly. Of most concern in this respect is the voltage drop along the power and ground buses and the RC delay of the critical signal paths. Attempts to reduce metal interconnect resistance by using wider metal lines result in higher capacitance of these wires.

To solve this problem, one approach has been is to develop low resistance metal (such as copper) for the wires while low dielectric materials are used in between signal lines. Current practice is to create metal interconnection networks under a layer of passivation. This approach however limits the interconnect network to fine-line interconnects, which is associated with low parasitic capacitance and high line resistance. The latter two parameters, because of their relatively high values, degrade device performance, an effect which becomes even more severe for high-frequency applications and for long interconnect lines that are, for instance, typically used for clock distribution lines. Also, fine-line interconnect metal cannot carry high values of current that is typically needed for ground busses and for power busses.

It has previously been stated that it is of interest to the semiconductor art to provide a method of creating interconnect lines that removes typical limitations that are imposed on the interconnect wires, such as unwanted parasitic capacitances and high interconnect line resistance. The invention provides such a method. An analogy can be drawn in this respect, as follows: the currently used fine-line interconnection schemes, which are created under a layer of passivation, are the streets in a city. In the post-passivation interconnection scheme of the present invention, the interconnections that are created above a layer of passivation can be considered the freeways between cities.

Due to the current trend in the creation of IC devices, the interconnection metal lines become thinner and the operating voltages that are applied to the devices become lower. For current sub-micron devices, with interconnect lines having a cross-section of about 0.18 μm, the voltage that is applied to the internal circuits is typically about 2.0 Volts or less. For such low voltage supplies, the IR voltage drop that is introduced by the interconnect lines has a relatively large impact on device functionality and performance, this in particular for circuits within a device that are removed by a considerably distance from bond pads. Most seriously affected are circuits that are located in the center of a device with wire-bonding pads located at the periphery of a chip, for those devices the IR drop that is introduced by interconnect lines can cause either device malfunction or a degradation in the operational speed of the device. The invention addresses these concerns.

SUMMARY OF THE INVENTION

A principle objective of the invention is to provide a low impedance metal interconnect system with bond pads on top of a Integrated Circuit device that is covered with a conventional layer of passivation.

Another objective of the invention is to provide a scheme for metal interconnects with bond pads that negates the effects of IR voltage drops introduced by the interconnect wires for applications where a voltage supply of 2 Volts or less is used.

Yet another objective of the invention is to provide a low-cost, high-performance post passivation metal interconnection system with bond pads that allows interconnection of power, ground, signal and clock lines over long distances.

A still further objective of the invention is to provide a low-cost, high-performance post passivation metal interconnection system that allows interconnection of power, ground, signal and clock lines to relatively far removed bond pads without introducing significant IR voltage drop introduced by the metal interconnect system.

In accordance with the objectives of the invention a new post-passivation metal interconnect scheme is provided over the surface of an IC device that has been covered with a conventional layer of passivation. The metal scheme of the invention comprises, overlying a conventional layer of passivation, thick and wide metal lines in combination with thick layers of dielectric and bond pads. The interconnect system of the invention can be used for the distribution of power, ground, signal and clock lines from bond pads to circuits of a device that are provided in any location of the IC device without introducing significant power drop. The post passivation metal scheme is connected to external circuits through wirebonding pads, solder bonding, TAB bonding and the like. A top layer of the interconnect metal scheme is formed using a composite metal for purposes of wirebonding. The composite metal is created by a bulk (low-resistance) conduction metal covered by a layer of (wire-bondable) metal to which wire bond connections can be readily made. A diffusionbarriermetal may be applied between the bulk metal and the wire-bondable metal, in addition a layer of Barrier-Metal (BM) may be required underneath the bulk conduction metal.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

FIG. 1shows a cross section of a silicon substrate on the surface of which has been created a conductive interconnect network. The structure that is shown in cross section inFIG. 1addresses prior art power and ground distribution networks. The various features that have been highlighted inFIG. 1are the following:40, a silicon substrate on the surface of which has been created an interconnect network42, a sample number of semiconductor circuits that have been created in or on the surface of the substrate4044, two electrostatic discharge (ESD) circuits created in or on the surface of the substrate40, one ESD circuit is provided for each pin that is accessible for external connections (pins52, see below)46is a layer of interconnect lines; these interconnect lines are above the surface of substrate40and under the layer48of passivation and represent a typical application of prior art fine-line interconnects; these fine-line interconnects of layer46typically have high resistance and high parasitic capacitance48is a layer of passivation that is deposited over the surface of the layer46of interconnect lines; this conventional layer48of passivation is used to protect the underlying devices and the underlying fine-line interconnections50is a power or ground bus that connects to the circuits42via fine-line interconnect lines provided in layer46; this power or ground bus is typically of wider metal since this power or ground bus carries the accumulated current or ground connection for the devices4252are two power or ground pins that pass through the layer48of passivation and that have been connected to the power or ground bus50.

From the above the following can be summarized: circuits are created in or on the surface of a silicon substrate, interconnect lines are created for these circuits for further interconnection to external circuitry. The circuits are, on a per I/O pin basis, provided with an ESD circuit, these circuits with their ESD circuit are connected to a power or ground pin that penetrates a layer of passivation. The layer of passivation is the final layer that overlies the created interconnect line structure, the interconnect line underneath the layer of passivation are fine line interconnects and have all the electrical disadvantages of fine line interconnects such as high resistance and high parasitic capacitance.

Relating to the cross section that is shown inFIG. 1, the following comments applies: ESD circuits are, as is known in the art, provided for the protection of semiconductor circuits against unexpected electrical charges. For this reason, each pin that connects to a semiconductor circuit must be provided with an ESD circuit.

FIG. 2shows a cross section of a prior art configuration that resembles the cross section shown inFIG. 1. The structure that is shown in cross section inFIG. 2however addresses clock and signal distribution networks.FIG. 2shows, in addition to the previously highlighted aspects ofFIG. 1, the following elements:45are two ESD circuits that are provided in or on the surface of the substrate40; ESD circuits are always required for any external connection to an input/output (I/O) pin45′ which are circuits that can be receiver or driver or I/O circuits for input (receiver) or output (driver) or I/O purposes respectively54is a clock or signal bus, and56are clock or signal pins that have been extended through the layer48of passivation.

The same comments apply to the cross section that is shown inFIG. 2as previously have been made with respect toFIG. 1, with as a summary statement that the layer of passivation is the final layer that overlies the created structure. The interconnect lines underneath the layer of passivation are fine line interconnects and have all the electrical disadvantages of fine line interconnects such as high resistance and high parasitic capacitance.

Further applies to the cross section that is shown inFIG. 2, where pins56are signal or clock pins:pins56must be connected to ESD and driver/receiver or I/O circuits45for signal or clock pins56, these pins must be connected not only to ESD circuits but also to driver or receiver or I/O circuits, highlighted as circuit45′ inFIG. 2after (clock and signal) stimuli have passed through the ESD and driver/receiver or I/O circuits, these stimuli are further routed using, under prior art methods, fine-line interconnect wires. A layer of passivation is deposited over the dielectric layer in which the interconnect network has been created.

It is therefore of interest to the semiconductor art to provide a method of creating interconnect lines that removes typical limitations that are imposed on the interconnect wires, such as unwanted parasitic capacitances and high interconnect line resistance. In addition, a method must be provided whereby various types of interconnect lines can be connected to bond pads without thereby introducing negative effects of voltage drop or parasitic (resistive and/or capacitive) components. The invention provides such a method, which will now be described in detail usingFIGS. 3 and 4.

Referring now specifically toFIG. 3, this figure refers to power and ground interconnects. There is shown inFIG. 3a cross section of a silicon substrate40over which a interconnect network is created according to the invention, with a wide and thick wire interconnect network created over a layer of passivation. A bond pad is provided through the surface of the thick layer of dielectric for external connection. Following are the various elements that are shown inFIG. 3:40is the silicon substrate on the surface of which interconnect lines are created in accordance with the invention42are semiconductor circuits that are created in or on the surface of substrate40, the semiconductor circuits having one or more active devices58are connection pads to the semiconductor devices42that have been created in or on the surface of substrate4060is a layer of fine-line interconnects that has been created overlying connection pads58to the semiconductor devices4261is one of the vias or a local fine line interconnections that have been provided for layer60, more such vias or local fine line interconnections are shown inFIG. 3but are, for reasons of simplicity, not highlighted62is a layer of passivation that has been deposited overlying the layer60of fine-line interconnects. In creating layer 62 of passivation, a layer of approximately 0.5 μm. PECVD oxide can be deposited first followed by a layer of approximately 0.7 μm. nitride. Passivation layer 62 is very important because it protects the device wafer from moisture and foreign ion contamination. The positioning of this layer between the sub-micron process (of the integrated circuit) and the tens-micron process (of the interconnecting metallization structure) is of critical importance since it allows for a cheaper process that possibly has less stringent clean room requirements for the process of creating the interconnecting metallization structure.63is one of vias that passes through layer62of passivation, more such vias are shown inFIG. 3but are, for reasons of simplicity, not highlighted64is a layer of post-passivation dielectric in which, as a post-passivation metal scheme process, interconnects have been created; in some applications, the metal can also be created directly on top of the layer62of passivation74is the combined (for multiple connection pads in layer58) power or ground bus67is a via or a local thick metal scheme that is created overlying the layer62of passivation, more such vias or local thick metal schemes are shown inFIG. 3but are, for reasons of simplicity, not highlighted74′ is the power or ground bond pad for the multiple semiconductor devices in layer58.

From the cross section that is shown inFIG. 3, it is clear that, most importantly, the ability to create interconnects to semiconductor devices that have been created in or on the surface of a substrate has been extended. This by creating these interconnects not only as fine-line interconnects in layer60but by extending the interconnect by creation a wide, thick wire interconnect network overlying a layer of passivation. The layer of passivation is used to protect the underlying semiconductor devices and the fine line interconnection from mobile ions, moisture and other contaminants. No further passivation layer is required to protect the wide, thick metal and the dielectrics because the structure is sturdier. Moisture and mobile ions will not significantly affect the properties and functionality of the structure. The wide, thick wire interconnect networkis furtheris connected to a power/ground bond pad6874′.

This provides immediate and significant benefits in that these wide, thick lines are further removed from the surface of the substrate while the wide, thick interconnect network that is created overlying the layer of passivation can now contain sturdier, that is thicker and wider lines. Power/ground interconnect lines are in addition directly connected to a power/ground bond pad. The thick, wide metal interconnect lines in combination with the power/ground pad can be used for power and ground distribution and for connection of ground/power signals to the semiconductor devices42. This distribution of interconnect lines and the interconnect to a ground/power bond pad takes place above a conventional layer of passivation and partially replaces and extends the conventional method of having, for purposes of ground/power distribution, a fine-line distribution interconnect network under the layer of passivation.

Prior Art

provides an ESD circuit for each pin that is used for external input/output interconnectprovides, after ESD stimuli have passed in parallel through the ESD circuits, a fine-line interconnect network for further distribution of the power and ground stimuli, andthe fine-line power and ground distribution network is created underneath a layer of passivation.

It must, in this respect and related to the above provided comments, be remembered that power and ground pins do not require drivers and/or receiver circuitry.

The inventiondoes not need to create an ESD circuit for each pin that is used for external input/output interconnect;thisin view of the more robust wiring and the power/ground bond pad that drives the ESD circuit, resulting in reduced power loss by an unexpected power surge over the interconnect line, resulting in more power being delivered to an ESD circuit, andallows for the power and ground interconnects to be directly connected to the internal circuits of a semiconductor device,thiseither without an ESD circuit or with a smaller than regular ESD circuit (as previously explained).

The method that is used to create the interconnect network that is shown in cross section inFIG. 3addresses the use of power and ground connections.FIG. 3can be summarized as follows: a silicon substrate is provided in the surface of which have been created semiconductor devices and no electrostatic discharge (ESD) circuit. A first layer of dielectric is deposited over the substrate, a fine-line interconnect network is created in the first layer of dielectric making contact with the active circuits. A layer of passivation is deposited over the surface of the first layer of dielectric. A pattern of metal plugs (or, for low aspect ratio vias and as previously pointed out, direct interconnects between the overlying layers of metal) is created in the layer of passivation that aligns with points of contact created in the surface of the first layer of dielectric. One or more layers of dielectric are deposited over the surface of the layer of passivation, a wide thick line interconnect network is created in the one or more layers of dielectric, contacting the ESD and conventional circuits of the device. For some applications, the first layer of metal of the post-passivation interconnection scheme can be created on top of the passivation, without adding thick dielectric in between. A bond pad serving as a point of electrical contact comprising a power or ground contact is provided in or on the surface of the one or more layers of dielectric.

FIG. 3shows, as highlighted and in summary, a cross section of a silicon substrate40over which a interconnect network is created according to the invention, with the interconnect network created in a thick layer of dielectric overlying a layer of passivation and remaining internal to the thick layer of dielectric. No ESD, receiver, driver or I/O circuit access pin is provided through the surface of the layer of dielectric for external to internal interface. Shown inFIG. 3is the power/ground bus interconnect line74, providing for an interconnect scheme of thick, wide lines overlying a passivation layer62. Due to the thick, wide lines of the interconnect network that is created overlying a layer62of passivation, the power/ground distribution can take place entirely within the interconnect layer64. If there is ESD stimuli, it will be spread out and be dissipated through all the junction of circuits42. This can be achieved through all the low impedance metal scheme of the invention. For fine line interconnections, the ESD stimuli cannot be distributed and would destroy the junction near the I/O pin. In addition and as highlighted in the cross section ofFIG. 3, the power/ground bus74is connected to a bond pad74′, allowing direct and relatively loss-free connection of the power/ground signals to the semiconductor circuits42.

The reason why the circuit configuration that is shown in the cross section ofFIG. 3does not required the use of ESD circuits is basically attributable to the very low impedance of the post-passivation interconnect provided by the invention. That is layer64,FIG. 3, which is a layer of post-passivation dielectric in which, as a post-passivation metal scheme process of the invention, interconnects have been created. The accumulated electrostatic discharge will be evenly distributed to the circuits42without thereby experiencing a significant resistance. The junction capacitance of all the circuits act as a collective and relatively large ESD circuit, that is the collective junction capacitance of circuits42is large enough that no ESD circuit is required. In prior art fine-line interconnect applications, the electrostatic charge will find the path of lowest resistance, which is the circuit that is close to the bond pad of the device, and destroy that circuit. This chain of events of prevented by the post-passivation interconnect scheme of the invention.

The cross section that is shown inFIG. 4is identical to the cross section that has been shown inFIG. 3, the difference being that the cross section shown inFIG. 4provides for clock/signal pulses provided over clock/signal bus74and the bond pad74′. The method that is followed for the creation of the structure that is shown in cross section inFIG. 6is therefore the same as the previously highlighted method that is used for the creation of the structure ofFIG. 3.

It must further be emphasized that, whereFIGS. 3 and 4show a fine-line interconnect network60that underlies the layer62of passivation, the invention also enables for and can be further extended with the complete elimination of the fine-line interconnect network60and creating an interconnect network64that uses only thick, wide wires. For this application of the invention, the first layer of dielectric60is not applied, the layer62of passivation is deposited directly over the surface of the created semiconductor devices58in or on the surface of substrate40.

It is further of value to briefly discuss the above implemented and addressed distinction between fine-line interconnect lines and wide, thick interconnect lines. The following points apply in this respect:the prior art fine line interconnect lines are created underneath a layer of passivation, the wide, thick interconnect lines of the invention are created above a first and second layer of passivationthe fine-line interconnect lines are typically created in a layer of inorganic dielectric, the thick wide interconnect lines are typically created in a layer of dielectric comprising polymer. This because an inorganic material cannot be deposited as a thick layer of dielectric because such a layer of dielectric would develop fissures and crack as a resultfine-line interconnect metal is typically created using methods of sputter with resist etching or of damascene processes using oxide etch with electroplating after which CMP is applied. Either one of these two approaches cannot create thick metal due to cost considerations or oxide crackingthick, wide interconnect lines can be created by first sputtering a thin metal base layer, coating and patterning a thick layer of photoresist, applying a thick layer of metal by electroplating, removing the patterned photoresist and performing metal base etching (of the sputtered thin metal base). This method allows for the creation of a pattern of very thick metal, metal thickness in excess of 1 μm can in this manner be achieved while the thickness of the layer of dielectric in which the thick metal interconnect lines are created can be in excess of 2 μmthe thick, wide metal is formed after formation of the layer of passivation. The semiconductor devices and the fine line interconnection are already well protected by the layer of passivation from mobile ions, moisture and other contaminants. The wide, thick wire can then be formed using unconventional processes which however in most Integrated Circuit fabrication facilities are restrictive in use in for instance applying polymers, Au, Cr, Ni dry film etc. Furthermore, environmental requirements during fabrication can be relaxed.

This completes discussion of the various structures that are provided by the invention. The post-passivation interconnection scheme can be a single layer of metal or can be more than one layer of metal. Where a single layer of metal is used, the post-passivation interconnection scheme provides both low-resistance interconnection and bond pad capabilities. For applications using more than one layer of metal, the bottom layer of metal is provided for low-resistance interconnect purposes while the top layer of metal provides both low resistance interconnect and bond pad capabilities.

Therefore, the post passivation interconnect structure of the present invention comprises a thick, wide metallization system formed above the passivation layer 62, wherein the thick, wide metallization system is used as a distribution network for a clock or signal voltage, and wherein the thick, wide metallization system is connected to the one or more internal circuits, wherein the thick, wide metallization system comprises a metal in the thick, wide metallization system greater than about 1 micrometer in thickness and one or more thick layers of dielectric, wherein the thick layers of dielectric each have a thickness greater than about 2 micrometers.

The bond pads, such as are highlighted as elements74′ in FIGS.3and74′ inFIG. 4, can be connected to external circuits by solder bonding, wirebonding, tape-automated bonding (TAB) and the like. As an example, the bond pad exposed through opening17,FIG. 5, is connected to external circuitry by means of bond wire18. To achieve both the low-resistance interconnect and wire-bonding capabilities, the top layers15/16inFIG. 5, must comprise a first metal, for instance copper, for purposes of low-resistance, and a second metal, for example Au, for purposes of wire-bonding. A layer of metal, for instance Ni, is required as a diffusion barrier. Where a layer of copper is used, a layer of adhesion material, such as Cr, must be created underneath the layer of copper. The top layer of metal preferably comprises a composite layer of metal such as Cr/Cu/Ni/Au. Where a bottom layer of metal, such as layer14inFIG. 5, is only used for low-resistance conduction, only low-resistance copper is required for this layer. A layer of Cr may also be required underneath the layer of low-resistance copper for adhesion purposes while a layer of Ni is required overlying the layer of low-resistance copper for applications where protection of the surface of the layer of copper is required.

In sum: for purposes of providing both wire-bonding capabilities and of achieving low IR voltage drop along the interconnections, the metallurgy of the top layer of metal requires a bulk conduction metal such as copper, gold, aluminum, and the like, in addition to a wire bondable metal such as gold and aluminum is required. In addition, a layer of diffusion barrier material, such a Ni, is required between and overlying the bulk conduction metal and the wire-bondable metal. Furthermore, a layer of adhesion material and a barrier layer may also be required under the bulk conduction metal.

For some applications, the low-resistance metal, such as Au and Al, can also be used for wire-bonding purposes, in which case, the metallurgy becomes simpler. As an example, layer14and15,FIG. 5, can both comprise TiW/Au whereby TiW is used as the adhesion layer.

First highlighted will be the cross section that is shown inFIG. 5, this cross section is to be viewed as an example of creating overlying interconnects through one or more layers of dielectric, highlighted in the cross section ofFIG. 5are:40, the cross section of the surface of a silicon substrate42, active semiconductor devices that have been created in or on the surface of substrate4060, a layer of dielectric in and through which fine-line interconnect wires have been created; these interconnect wires make contact with the underlying active semiconductor devices42and have in addition been provided with points of electrical contact or top metal in the surface of layer6010, two examples of top metal that has been provided in the surface of layer60, making contact with the fine-line interconnect wires that have been created in layer6062, a layer of passivation deposited over the surface of layer60, including the surface of top metal contacts10; the passivation layer62is used to protect the underlying active devices (layer42) and the fine-line interconnections (layer60of dielectric)11,12and13respectively a first, a second and a third thick layer of dielectric; these three layers of dielectric significantly are created over the surface of layer62of passivation and are the layers of dielectric in and through which the thick interconnect metal of the invention is created, including at least one contact pad in the surface of the upper layer of dielectric that makes electrical contact with the thick interconnect metal of layers11,12and1314, 15 and 16; for purposes of cost-reduction, the layer11can be omitted, i.e. the layer14of metal is directly formed on the surface of the layer62of passivation14, a first layer of patterned and etched metal overlying first layer11of dielectric and being in contact with top metal10by means of openings created through the first layer11of dielectric and the layer62of passivation15and16, a second layer of patterned and etched metal overlying second layer12of dielectric and being in contact with the first layer14of patterned and etched metal by means of openings created through the second layer12of dielectric; layer16can for instance serve as a contact pad, layer15provides further interconnect to surrounding circuitry (not shown); layers15and16can be used for purposes other than forming contacts, these layers can also be used as conductive layers such as layers of signal interconnects17, an opening created through the third layer13of dielectric, exposing the surface of patterned and etched layer16of metal, forming a contact pad over the surface of this exposure18, a wire bond connection that establishes electrical contact between the contact pad16and surrounding circuitry (not shown).

The composition of layers14,15and16has been previously discussed and can be summarized as follows:layer14can comprise a compound layer of Cr/Cu/Ni where the layer of Cu forms the bulk, low-resistance layer of metal, the lower layer of Cr provides adhesion to the overlying layer of Cu and the upper layer of Ni protects the surface of the layer of copper, andlayers15and16can comprise a compound layer of Cr/Cu/Ni/Au where the layer of copper provides the bulk, low-resistance layer of metal, the lower layer of Cr provides adhesion to the overlying layer of Cu and the underlying polyimide, the layer of Ni overlying the layer of Cu serves as a diffusion barrier layer while the upper layer of Au is the wire-bondable layer of metal.

FIGS. 6 through 10show specific methods and structures for the thick, heavy interconnect scheme and the wire-bonding pad of the invention. These methods and structures will now discussed in detail. It must thereby be kept in mind that the invention provides for a post-passivation interconnect scheme for the interconnections to external circuits. This interconnect to external circuits is typically provided by methods of solder bonding. The significant difference between conventional methods of interconnecting to external circuits is that the invention combined a new, post-passivation interconnect scheme with using wire-bonding techniques. In this manner, the invention solves the problem of typically experiences high IR voltage drop across interconnect lines. A significant aspect of the invention is further that it allows the application of widely available wire-bonding infrastructure and thereby negates the need for relatively expensive methods of solder bonding flip chips.

The cross sections that are shown inFIGS. 5 through 10focus on using a wire bonding approach for creating a chip and by applying post-passivation interconnections for the connection of the device to external circuits. The post-passivation can be a single layer of metal or can comprise multiple layers of metal. A first layer of metal in the post-passivation process is typically on the surface of a thick layer of dielectric. For purposes of cost-reduction, this first layer of metal can also be created directly overlying the surface of the layer of passivation.

Only the upper-most layer of metal that is created using the post-passivation scheme of the invention must provide a metal configuration that has both low resistance and good wire bonding capabilities. Lower lying layers of metal need only provide low resistance interconnects and can therefore comprise a bulk metal such as copper that is typified by low-resistance. The invention provides special insight into the creation of the upper-most layer of metal, which must have both low-resistance and good wire bonding capabilities.

For purposes of low-resistance, the invention provides a bulk metal such as Cu, Au, Al and the like. For wire-bonding purposes, the invention provides a metal of good wire-bonding characteristics such as Au, Al and the like.

Where Au or Al is used as the interconnect metal, the metal scheme is relatively simple since both of these metals have low-resistance and good wire-bonding characteristics. This will be further highlighted using the cross section ofFIG. 6andFIG. 9for Au and Al, respectively.

Where Cu is used as the interconnect metal, in view of the low-resistance of Cu, a layer of wire-bondable metal such as Au or Al is additionally required. For this application, a layer of diffusion barrier material, such as Ni, is required between the layer of Cu and the overlying layer of Au. In addition, a adhesion layer, for instance comprising Cr, is required between the layer of Cu and the underlying layer of dielectric (polyimide). This will be further highlighted using the cross section ofFIGS. 7 and 8.

Specifically referring to the cross section that is shown inFIG. 6, the following elements of this structure are high-lighted:40, the cross section ofthe surface ofa silicon substrate42, active semiconductor devices that have been created in or on the surface of substrate4060, a layer of dielectric in and through which fine-line interconnect wires have been created; these interconnect wires make contact with the underlying active semiconductor devices42and have in addition been provided with points of electrical contact or top metal in the surface of layer6010, top metal that has been provided in the surface of layer60, making contact with the fine-line interconnect wires that have been created in layer6062, a layer of passivation deposited over the surface of layer60, including the surface of top metal contact1011a first thick layer of dielectric; this layer11of dielectric is created over the surface of layer62of passivation; for purposes of-cost-reduction, the first layer11of dielectric can be omitted in some applications19and20, layers of patterned and etched metal forming a bonding pad/low resistance interconnect layer. The upper layer20comprises a selected metal which is selected for purposes of providing low-resistance interconnect while this layer can simultaneously be used for wire-bonding purposes, preferably using Au or Al. The lower layer19is used for purposes of adhesion to the layer of dielectric as well as for forming a diffusion layer to the contact pad10.The processing flow that is provided for the creation of the structure that has been shown in cross section inFIG. 6is as follows:1. conventionally performing Front-Of-Line (FOL) processing, comprising processing of layer42of active semiconductor devices, layer60of fine-line interconnect metal thereby including the creation of top metal10and layer62of passivation2. patterning and etching an opening through the layer62of passivation, this opening being aligned with a portion of the top metal10, exposing the surface of top metal10; it is clear that where at this time only one opening is indicated, the invention is not limited to the creation of one opening through the layer62of passivation but can create as many openings as are desired for a device layout3. depositing a first layer11of dielectric, preferably comprising polyimide; for purposes of cost reduction, this layer can be omitted in some applications4. patterning and etching the deposited first layer11of dielectric, creating an opening through this first layer of dielectric; this opening being aligned with the opening that has been created through the layer62of passivation, making this opening being aligned with a portion of the layer10of top metal5. successively creating layers of barrier metal such as TiW(layer19)over which a layer(layer20)of Au or Al is created, preferably using the method of metal sputtering for the creation of these layer19of metal; it must specifically be noted that layer19is a composite sputtered layer comprising about 3,000 Angstrom of TiW and about 1,000 Angstrom of Au; layer20is a thick layer of Au created by using electroplating techniques; layer20is therefore not only used as a bond pad but can additionally be used for interconnect wiring; these latter comments further emphasize that the invention provides for the creation of a metal system that can be simultaneously used for the creation of conductive interconnect traces and for wire bonding purposes; it must as a consequence be pointed out that aspects of separately creating either interconnect traces or wire bond pads are not addressed or provided for by the invention.6. creating an exposure mask, preferably comprising photoresist, over the surface of sputtered layers19, this mask exposing these layers over a surface area of the metal layers19that is to form as a metal system that can be simultaneously used for low resistance conduction and wire bonding, this mask exposing the surface areas where the wiring and the bond pad are required7. applying a Au plating to the exposed surface of the layer19;layer 20 is a thick layer of Au created by using electroplating techniques;layer20is therefore not only used as a bond pad but can additionally be used for interconnect wiring; these latter comments further emphasize that the invention provides for the creation of a metal system that can be simultaneously used for the creation of conductive interconnect traces and for wire bonding purposes; it must as a consequence be pointed out that aspects of separately creating either interconnect traces or wire bond pads are not addressed or provided for by the invention8. removing the exposed photoresist, and9. etching layers19using the plated Au is a mask. Thus, a metal system has been created for low-resistance interconnects and for wire-bonding purposes.

The cross section that is shown inFIG. 6is an application of the invention where Au or Al is used as the interconnect metal. As previously pointed out, the metal scheme is relatively simple since both of these metals have low-resistance and good wire-bonding characteristics. The layer of Cu or Al forms the low-resistance interconnect layer while this metal can also be used for good wire-bonding purposes. A Au layer can be created using conventional electroplating technology. In addition, since Au is an inert metal, a layer of Au does not require an overlying layer of polyimide.

Therefore, the method of providing at least one bond pad over the surface of the post-passivation interconnection structure may comprise the steps of:providing a substrate 40, active devices 42 having been created in or on the surface of the substrate 40, a layer 60 of fine-line interconnect metal including top metal 10 being connected to the active devices 42 having been provided over the surface of the substrate 40, a layer 62 of passivation having been provided over the surface of the layer 60 of fine-line interconnect metal;patterning and etching an opening through the layer 62 of passivation, this opening being aligned with a portion 10 of the top metal, exposing the surface 10 of top metal;successively creating a first layer (one layer of layers 19) of metal comprising TiW over which a second layer metal (one layer of layers 19) comprising Au is created, preferably using the method of metal sputtering for the creation of these layers 19;creating an exposure mask (not shown in FIG. 6), preferably comprising photoresist, over the surface of sputtered second layer of metal comprising Au, this mask exposing the second layer of metal over a surface area that is to form the low-resistance interconnection and the bond pad;applying a bulk metal 20 plating to the exposed surface of the second layer of metal comprising Au;removing the exposure mask; andetching the second layer of metal comprising Au and the first layer of metal comprising TiW in accordance with the plated layer 20 of bulk metal, leaving in place the first and the second layers 19 of metal where the plated layer 20 of bulk metal plating has been applied, thereby providing a metal system serving as both low-resistance conduction and wirebonding pads.

For subsequent cross sections ofFIG. 7 through 10, a number of the elements of the structure and therefore a number of the related processing steps are commonly valid and will therefore not be repeated. The processing steps however, in view of the importance of these step, will, for each of the cross sections ofFIG. 7 through 10, be restated.

For the cross section that is shown inFIG. 7, layers40through and including layer11are as previously highlighted underFIG. 6.FIG. 7has, in addition to or differing with the elements that have been highlighted underFIG. 6, the following elements:21, a first layer of metal, preferably comprising Cr or Ti or TiW or a compound thereof; layer21serves as an adhesion layer between the overlying layer22of Cu and the underlying layer11of dielectric; a thin layer of copper (not shown) is subsequently sputtered over the surface21to serve as a seed layer for the electroplating of layer22, layer22is not yet formed at this time22, a second layer of metal of the bond pad, preferably comprising Cu or a Cu compound, selected for its low-resistance characteristics23, a third layer of metal of the bond pad, preferably comprising Ni or a Ni compound12, a second layer of dielectric, an opening25has been created through this layer of dielectric, exposing the surface of layer23for the creation of the fourth layer24of metal of the bond pad, and24, a fourth layer of metal of the bond pad, preferably comprising Au or an Au compound.

The processing flow that is provided for the creation of the structure that has been shown in cross section inFIG. 7is as follows:1. conventionally performing Front-Of-Line (FOL) processing, comprising processing of layer42of active semiconductor devices, layer60of fine-line interconnect metal thereby including the creation of top metal10and layer62of passivation2. patterning and etching an opening through the layer62of passivation, this opening is to be aligned with a portion of the top metal10, exposing the surface of top metal103. depositing a first layer11of dielectric, preferably comprising polyimide; in some applications, this layer of dielectric can be omitted for reasons of cost-reduction4. patterning and etching the deposited first layer11of dielectric, creating an opening through this first layer of dielectric; this opening is to be aligned with the opening that has been created through the layer62of passivation making this opening being aligned with a portion of the layer10of top metal5. creating layers21(comprising Cr or Ti or TiW) and a layer of Cu (not shown), preferably using the method of metal sputtering for the creation of these layers of metal6. creating an exposure mask, preferably comprising photoresist, over the surface of sputtered layers21, this mask exposing these layers over a surface area of the metal layer21that is to form as a bond pad, this mask further covering all surface areas of the layer2221that are not serving as a bond pad7. applying a Cuplating (not shown inFIG. 7)layer 22to the exposed surface of the layer218. applying a Ni plating to the copper plated surface oflayerslayer22, creating layer239. removing the exposed photoresist, and10. etching layer21essentially in accordance with the applied Ni and Cuplatinglayers 23 and 22, leaving in place layer21where theCu andNiplating (layer22and23) haslayers 22 and 23 havebeen applied, thereby leaving in place layers21,22and23that serve as low-resistance interconnection, exposing the surface of layer23, further exposing the surface of the first layer11of dielectric11. depositing a second layer12of dielectric, preferable comprising polyimide, over the exposed surface of layer23and the exposed surface of the first layer11of dielectric12. patterning and etching the deposited second layer12of dielectric, creating an opening25through the second layer12of dielectric that aligns with the patterned and etched layers21,22and23, exposing the surface of layer23, and13. performing electroless gold plating to the exposed surface of layer23, creating bond pad24.

Therefore, the method of providing at least one bond pad over the surface of the post-passivation interconnection structure may comprise the steps of:providing a substrate 40, active devices 42 having been created in or on the surface of the substrate 40, a layer 60 of fine-line interconnect metal having been provided over the surface of the substrate 40, at least one layer 10 of patterned top metal having been provided over the surface of the layer 60 of fine-line interconnect metal, the at least one layer of patterned top metal having been connected to the layer 60 of fine-line interconnect metal, a layer 62 of passivation having been provided over the surface of the layer 60 of fine-line interconnect metal;patterning and etching at least one first opening through the layer 62 of passivation, the at least one first opening being aligned with a portion 10 of the at least one layer of top metal, exposing the surface 10 of the at least one layer of top metal;creating a first layer 21 of metal, serving as a diffusion barrier and an adhesion layer, over the surface of the layer 62 of passivation, preferably using metal sputtering for the creation of the first layer 21 of metal;creating a second layer (not shown in FIG. 7) of seed metal for subsequent processing of electroplating, preferably using methods of metal sputtering;creating an exposure mask (not shown in FIG. 7), preferably comprising photoresist, over the surface of the sputtered second layer of metal, the exposure mask exposing the second layer of metal over a surface area of the second layer of metal that is to form a low resistance interconnection;applying a first metal plating to the exposed surface of the second layer of metal, creating a third layer 22 of metal to form a low-resistance interconnection over the exposed surface area of the second layer of metal;applying a second metal plating to the exposed surface of the third layer of metal, creating a fourth layer 23 of metal to form a diffusion barrier over the surface area of the third layer 23 of metal;removing the exposure mask;etching the first and second layers (21 and seed layer) of metal in accordance with the applied third and fourth metal plating, thereby leaving in place the first, the second, the third and the fourth layers (21, seed layer, 22 and 23) of metal that serve as diffusion barrier, electroplating seed layer, low-resistance layer and diffusion barrier respectively;depositing a second layer 12 of dielectric, preferably comprising polyimide, over the exposed surface of the fourth layer 23 of metal and the exposed surface of the layer 62 of passivation;patterning and etching the deposited layer 12 of dielectric, creating an opening 25 through the layer 12 of dielectric that aligns with a portion of the patterned and etched first, second, third and fourth layers (21, seed layer, 22 and 23) of metal, exposing the surface of the fourth layer 23 of metal; andapplying a third metal plating to the exposed surface of the fifth layer 24 of metal, preferably using electroless plating, creating a bond pad.

The cross section that is shown inFIG. 8has the basic elements that have been highlighted underFIG. 7, these basic elements have however been processed in a different manner, which will become clear in following the processing flow as this processing flow applies to the cross section ofFIG. 8.

The processing flow that is provided for the creation of the structure that has been shown in cross section inFIG. 8is as follows:1. conventionally performing Front-Of-Line (FOL) processing, comprising processing of layer42of active semiconductor devices, layer60of fine-line interconnect metal thereby including the creation of top metal10and layer62of passivation2. patterning and etching an opening through the layer62of passivation, this opening is to be aligned with a portion of the top metal10, exposing the surface of top metal103. depositing a first layer11of dielectric, preferably comprising polyimide; this layer of dielectric can be omitted in some applications4. patterning and etching the deposited first layer11of dielectric, creating an opening through this first layer11of dielectric; this opening is to be aligned with the opening that has been created through the layer62of passivation making this opening being aligned with a portion of the layer10of top metal5. creating a layer21of Cr or Ti or TiW, preferably using the method of metal sputtering for the creation of these layers of metal; a thin layer of copper (not shown) is sputtered over the surface of layer21to serve as a seed layer for the electroplating of overlying layer22, layer22is not yet formed at this time6. creating a exposure mask, preferably comprising photoresist, over the surface of sputtered layer21, this mask exposing this layer over a surface area of the metal layer21that is to form as the low resistance interconnection and a bond pad, this mask further covering all surface areas of the layer21that are not serving as a bond pad7. applying a Cu plating to the exposed surface of the layers21, creating layer228. applying a Ni plating to the exposed surface of the layers22, creating layer239. applying a Au plating to the exposed surface of the layers23, creating layer24; this essentially creates a three layered mask of layers21(over which a thin layer of copper, not shown, has been sputtered),22and2310. removing the exposure mask11. etching layers21(and the thereover sputtered thin layer of copper) essentially in accordance with the applied Au plating, leaving in place layers21,22,23and24where the Au plating has been applied, thereby leaving in place layers21,22,23and24that serve as the low resistance interconnection and a bond pad, exposing the surface of layer24, further exposing the surface of the first layer11of dielectric12. depositing a second layer12of dielectric, preferable comprising polyimide, over the exposed surface of layer24and the exposed surface of the first layer11of dielectric13. patterning and etching the deposited second layer12of dielectric, creating an opening26through the second layer12of dielectric that aligns with a portion of the patterned and etched layers21,22,23and24, exposing the surface of layer24.

Therefore, the method of providing at least one bond pad over the surface of the post-passivation interconnection structure may comprise the steps of:providing a substrate 40, active devices 42 having been created in or on the surface of the substrate 40, a layer 60 of fine-line interconnect metal having been provided over the surface of the substrate 40, at least one layer 10 of patterned top metal having been provided over the surface of the layer 60 of fine-line interconnect metal, the at least one layer 10 of patterned top metal having been connected to the layer 60 of fine-line interconnect metal, a layer 62 of passivation having been provided over the surface of the layer 60 of fine-line interconnect metal;patterning and etching at least one first opening through the layer 62 of passivation, the at least one first opening being aligned with a portion of the at least one layer 10 of top metal, exposing the surface of the at least one layer 10 of top metal;creating a first layer 21 of metal over the surface of the layer 62 of passivation, preferably using the method of metal sputtering for the creation of this layer 21 of metal;sputtering a thin second layer (not shown in FIG. 8) over the surface of the first layer 21 of metal, the second layer serving as an electroplating seed layer;creating an exposure mask (not shown in FIG. 8), preferably comprising photoresist, over the surface of the sputtered second layer of metal, the exposure mask exposing the surface of the second layer of metal over a surface area that is to serve as a low-resistance interconnection and a bond pad;creating a third layer 22 of metal over the exposed surface of the second layer of metal;creating a fourth layer 23 of metal over the exposed surface of the third layer 22 of metal;creating a fifth layer 24 of metal over the exposed surface of the fourth layer 23 of metal;removing the exposure mask;etching the first and the second layers (21 and seed layer) of metal in accordance with the created fifth layer 24 of metal, leaving in place the first, second, third, fourth and fifth layers (21, seed layer, 22, 23 and 24) of metal where the fifth layer 24 of metal has been applied, these layers serving as a low-resistance interconnection and a bond pad, exposing the surface of the fifth layer 24 of metal, further exposing the surface of the layer 62 of passivation;depositing a layer 12 of dielectric, preferable comprising polyimide, over the exposed surface of the fifth layer 24 of metal and the exposed surface of the layer 62 of passivation;patterning and etching the deposited second layer 12 of dielectric, creating an opening 26 through the second layer of dielectric that aligns with a portion of the patterned and etched first, second, third, fourth and fifth layers of metal, exposing the surface of the fifth layer 24 of metal, creating a bond pad.

The cross section that is shown inFIG. 9has the simplest metal system, a thick sputtered layer of Al is used in this case.

The processing flow that is provided for the creation of the structure that has been shown in cross section inFIG. 9is as follows:1. conventionally performing Front-Of-Line (FOL) processing, comprising processing of layer42of active semiconductor devices, layer60of fine-line interconnect metal thereby including the creation of top metal10and layer62of passivation2. patterning and etching an opening through the layer62of passivation, this opening is to be aligned with a portion of the top metal10, exposing the surface of top metal103. depositing a first layer11of dielectric, preferably comprising polyimide; in some applications, this layer of dielectric can be omitted for cost reasons4. patterning and etching the deposited first layer11of dielectric, creating an opening through this first layer of dielectric; this opening is to be aligned with the opening that has been created through the layer62of passivation making this opening being aligned with a portion of the layer10of top metal5. creating a layer21of Al; this layer of Al is thicker than 1 μm and is preferably created using methods of metal sputtering6. creating an exposure mask, preferably comprising photoresist, over the surface of sputtered Al layer21; this mask exposes a surface area except the surface of the Al layer21that is to form a low-resistance interconnection and a bond pad, this mask further covering all surface areas of the metal layer that are not serving as a bond pad7. etching the Al metal layer in accordance with the exposure mask, preferably using wet etching8. removing the exposure mask9. depositing a second layer12of dielectric, preferable comprising polyimide, over the exposed surface of layer2421and the exposed surface of the first layer11of dielectric10. patterning and etching the deposited second layer12of dielectric, creating an opening26through the second layer12of dielectric that aligns with a portion of the patterned and etched layer21, exposing the surface of layer2421, the exposed surface of layer2421serving as a bond pad.

Therefore, the method of providing at least one bond pad over the surface of said post-passivation interconnection structure may comprise the steps of:providing a substrate 40, active devices 42 having been created in or on the surface of the substrate 40, a layer 60 of fine-line interconnect metal having been provided over the surface of the substrate 40, at least one layer 10 of patterned top metal having been provided over the surface of the layer 60 of fine-line interconnect metal, said at least one layer 10 of patterned top metal having been connected to said layer 60 of fine-line interconnect metal, a layer 62 of passivation having been provided over the surface of the layer 60 of fine-line interconnect metal;patterning and etching at least one first opening through the layer 62 of passivation, said at least one first opening being aligned with a portion of said at least one layer 10 of top metal, exposing the surface of said at least one layer 10 of top metal;depositing a first layer 11 of dielectric over the surface of said layer 62 of passivation, including at least one opening created through said layer 62 of passivation, said first layer 11 of dielectric preferably comprising polyimide;patterning and etching the deposited first layer 11 of dielectric, creating at least one second opening through this first layer 11 of dielectric, said at least one second opening being aligned with said at least one first opening through the layer 62 of passivation;creating a layer 21 of metal over the surface of said first layer 11 of dielectric including inside surfaces of said second opening created through said first layer 11 of dielectric, preferably using the method of metal sputtering for the creation of this layer 11 of metal;creating an exposure mask (not shown in FIG. 9), preferably comprising photoresist, over the surface of sputtered layer 21 of metal, said exposure mask covering this layer over a surface area of the metal layer 21 that is to serve as a low-resistance interconnection and a bond pad;etching the layer 21 of metal in accordance with the exposure mask, exposing the surface of said first layer 11 of dielectric;removing the exposure mask, exposing the surface of said layer 21 of metal;depositing a second layer 12 of dielectric, preferable comprising polyimide, over the exposed surface of the fourth layer of metal and the exposed surface of the first layer 11 of dielectric; andpatterning and etching the deposited second layer 12 of dielectric, creating an opening 26 through the second layer 12 of dielectric that aligns with a portion of the patterned and etched layer 21 of metal, exposing the surface of the layer 21 of metal, the exposed surface of the layer 21 of metal serving as a bond pad.

The cross section that is shown inFIG. 10has the basic elements that have been highlighted underFIG. 7, these basis elements have however processed in a different manner which will become clear in the following processing flow as this processing flow applies to the cross section ofFIG. 10.

The processing flow that is provided for the creation of the structure that has been shown in cross section inFIG. 10is as follows:1. conventionally performing Front-Of-Line (FOL) processing, comprising processing of layer42of active semiconductor devices, layer60of fine-line interconnect metal thereby including the creation of top metal10and10′ and layer62of passivation; top metal10and10′ is a metal that is wire-bondable2. patterning and etching openings28,31and32through the layer62of passivation, openings28and31to be aligned with a portion of the top metal10′, exposing the surface of top metal10′; opening32to be aligned with a portion of the top metal10, exposing the surface of top metal103. depositing a first layer11of dielectric, preferably comprising polyimide; in some applications, this layer of dielectric can be omitted4. patterning and etching the deposited first layer11of dielectric, creating openings through this first layer of dielectric; these openings are to be aligned with the openings28,31and325. creating a layer21of TiW or Ti or Cr over which a thin layer of Cu (not shown) is created; the thin layer of copper (not shown) serves as a seed layer for the electroplating of an overlying layer6. creating an exposure mask, preferably comprising photoresist, to expose area100; area100can be an interconnecting network covering a large portion of the chip area, connecting to areas10′, a portion of which forms a wire bonding pad exposed through opening28; the length of area100can be large since low resistance interconnect metal is used, while10′ should be short since higher resistance metal is used7. applying a Cu plating22to the exposed surface of the layer21in area1008. applying a Ni plating23to the exposed surface of the layers22in area1009. removing the exposure mask10. etching (the thin layer of copper, not shown) and layer21of TiW using the patterned layers22and23as a mask, for this etch a H2O2is used, thereby avoiding etch damage to the surface of layer10′ of aluminum in the bond pad2811. depositing a second layer12of dielectric, preferably comprising polyimide, over the complete surface of the wafer12. patterning and etching the layer12of dielectric outside area100′, to open region29, exposing the surface of the bond pad exposed through opening28.

Therefore, the method of providing at least one bond pad over the surface of the post-passivation interconnection structure may comprise the steps of:providing a substrate 40, active devices 42 having been created in or on the surface of the substrate 40, a layer 60 of fine-line interconnect metal including top metal being connected to the active devices 42 having been provided over the surface of the substrate 40, the top metal 10 comprising wire-bondable metal 10′, the top metal 10 comprising at least one first portion of top metal which comprises a bond pad 10′, the top metal 10 further comprising at least one second portion of top metal that needs to be connected to the first portion of top metal, a layer 62 of passivation having been provided over the surface of the layer 60 of fine-line interconnect metal;patterning and etching a first, second and a third openings 28, 31 and 32 through the layer 62 of passivation, the first opening 28 being aligned with a portion of the first portion of top metal, the second opening 31 being aligned with a portion of the second portion of top metal, the third opening 32 being aligned with a portion of the second portion of top metal, exposing the surface of the first and second portion of top metal;depositing a first layer 11 of dielectric, preferably comprising polyimide, over the surface of the layer 62 of passivation, including the first, second and third openings 28, 31 and 32 created in the layer 62 of passivation;patterning and etching the deposited first layer 11 of dielectric, creating a fourth, a fifth and a sixth openings through the first layer 11 of dielectric, the fourth opening 29 through the first layer 11 of dielectric being aligned with the first opening 28 created through the layer 62 of passivation, the fifth and sixth openings through the first layer 11 of dielectric respectively being aligned with the second and third openings 31 and 32 created through the layer 62 of passivation;creating a first layer 21 of metal over the surface of the first layer 11 of dielectric, creating a second layer (not shown in FIG. 10) of metal serving as seed layer over the surface of the first layer 21 of metal;creating an exposure mask (not shown in FIG. 10), preferably comprising photoresist, over the surface of the created second layer of metal, exposing the second layer of metal only over the surface area of the second layer of metal at least in a region over and between the second and third opening while not exposing the first opening;creating a patterned third layer 22 of metal over the exposed surface of the second layer of metal;creating a patterned fourth layer 23 of metal over the surface of the patterned third layer 22 of metal;removing the exposure mask, exposing the surface of the second layer of metal, leaving in place a mask of the patterned third and fourth layers 23 of metal in place overlying the second layer of metal;etching the second and the first layers (seed layer and 21) of metal in accordance with the mask of third and fourth layers 22 and 23 of metal overlying these second and first layers (seed layer and 21) of metal, thereby avoiding etch damage to the surface of the top metal 10′ in the bond pad, thereby exposing the surface of the first layer 11 of dielectric;depositing a second layer 12 of dielectric over the surface of the patterned fourth layer 23 of metal and the surface of the first layer 11 of dielectric, preferable comprising polyimide; andpatterning and etching the deposited second layer 12 of dielectric, creating an opening through the second layer 12 of dielectric that aligns with the bond pad.

The invention has provided methods and structures for creating thick, heavy layers of interconnect metal connected with bond pads over the surface of a conventional layer of passivation. The invention has further provided processing sequences for the creation of the bond pads and the thick heavy layers of metal.