Ultra-thin semiconductor component fabrication using a dielectric skeleton structure

In one implementation, a method for forming ultra-thin semiconductor components includes fabricating multiple devices including a first device and a second device in a semiconductor wafer, and forming a street trench within the semiconductor wafer and between the first and second devices. The method continues with forming a dielectric skeleton structure over the semiconductor wafer, the dielectric skeleton structure laterally extending to at least partially cover the first and second devices, while also substantially filling the street trench. The method continues with thinning the semiconductor wafer from a backside to expose the dielectric skeleton structure in the street trench to form a first ultra-thin semiconductor component having the first device, and a second ultra-thin semiconductor component having the second device. The method can conclude with cutting through the dielectric skeleton structure to singulate the first and second ultra-thin semiconductor components.

BACKGROUND

Background Art

Due to the potential advantages resulting from the fabrication of semiconductor devices on thin dies, such as improved electrical performance, for example, efficient and reliable techniques for providing thin and ultra-thin semiconductor dies are desired. However, as known in the art, the production and separation of thin and ultra-thin dies can be challenging because of the susceptibility of those dies to damage. For example, thin and ultra-thin dies may be chipped during sawing and singulation, or may be cracked during singulation and the handling associated with packaging of the dies.

A conventional technique directed to overcoming the challenges involved in producing thin and ultra-thin semiconductor dies includes gluing a semiconductor wafer to a handle substrate before grinding the wafer to thin it, and then mounting the thinned wafer onto dicing tape. The thinned wafer is diced, and then must be unglued from the handle substrate. Unfortunately, this conventional technique, although offering some protection for thin and ultra-thin dies during their production and separation, is undesirably costly and slow.

SUMMARY

The present disclosure is directed to ultra-thin semiconductor component fabrication using a dielectric skeleton structure, substantially as shown in and/or described in connection with at least one of the figures, and as set forth in the claims.

DETAILED DESCRIPTION

As stated above, due to the potential advantages resulting from the fabrication of semiconductor devices on thin dies, such as improved electrical performance, efficient and reliable techniques for providing thin and ultra-thin semiconductor dies are desired in the art. However, and as known in the art, the production and separation of thin and ultra-thin dies can be challenging because of the susceptibility of those dies to damage. For example, thin and ultra-thin dies may be chipped during sawing and singulation, or may be cracked during singulation and the handling associated with packaging of the dies.

As further stated above, a conventional technique directed to overcoming the challenges involved in producing thin and ultra-thin semiconductor dies includes gluing a semiconductor wafer to a handle substrate before grinding the wafer to thin it, and then mounting the thinned wafer onto dicing tape. The thinned wafer is diced, and then must be unglued from the handle substrate. Unfortunately, this conventional technique, although offering some protection for thin and ultra-thin dies during their production and separation, is undesirably costly and slow.

The present application discloses structures and methods for ultra-thin semiconductor component fabrication using a dielectric skeleton structure. According to the exemplary implementations described in the present application, such a method includes fabricating multiple devices in a semiconductor wafer, and forming street trenches within the wafer between some or all of the semiconductor devices. The method also includes forming a dielectric skeleton structure laterally extending to at least partially cover at least some of the devices while substantially filling the street trenches.

The semiconductor wafer can then be thinned, using the dielectric skeleton structure for mechanical support and stabilization. Thinning proceeds until the dielectric skeleton structure is exposed at the backside of the thinned semiconductor wafer, resulting in formation of multiple ultra-thin semiconductor components each including at least one of the multiple devices fabricated in the wafer. The ultra-thin semiconductor components may then be singulated by cutting through the dielectric skeleton structure, rather than by cutting through the semiconductor material of the wafer itself, thereby advantageously avoiding the wafer chipping and cracking that may occur during conventional thin wafer separation processes.

In contrast to conventional methods in which a semiconductor wafer must typically be unglued from a handle substrate providing mechanical support after the wafer is thinned, the dielectric skeleton structure disclosed in the present application in effect stays with the wafer through singulation of its component dies, which is unique in the art. Moreover, the ultra-thin semiconductor fabrication solution disclosed in the present application requires a minimum amount of new tooling, and advantageously results in faster and less costly processing.

FIG. 1shows flowchart100presenting an exemplary method for fabricating ultra-thin semiconductor components using a dielectric skeleton structure, according to one implementation. The exemplary method described by flowchart100is performed on a semiconductor wafer, such as a silicon (Si) or other group IV semiconductor based wafer, and may be utilized to fabricate ultra-thin semiconductor components providing one or more of a variety of device types. For example, the ultra-thin semiconductor components disclosed in the present application may include devices in the form of lateral silicon or other group IV based transistors, vertical power transistors such as vertical power field-effect transistors (FETs), insulated-gate bipolar transistors (IGBTs), and diodes, to name a few examples.

With respect toFIGS. 2A, 2B, 2C, 2D, 2E, 2F, and 2G(hereinafter “FIGS. 2A-2G”), structures201,202,203,204,205,206, and207shown respectively in those figures illustrate the result of performing the method of flowchart100, according to one implementation. For example, structure201, shown in cross-section inFIG. 2A, represents a portion of semiconductor wafer212having first and second devices220aand220bfabricated therein (action101). Structure202, shown in cross-section inFIG. 2Bshows formation of street trench230within semiconductor wafer212between devices220aand220b(action102). Structure203, shown in cross-section inFIG. 2C, shows formatin of dielectric skeleton structure240(action103), and so forth.

Referring to flowchart100, inFIG. 1, in combination withFIG. 2A, flowchart100begins with fabricating multiple devices including first device220aand second device220bin semiconductor wafer212(action101). As shown by structure201inFIG. 2A, semiconductor wafer212includes first device220aand second device220bfabricated in and over device side214of semiconductor wafer212. In addition, semiconductor wafer212includes highly doped N type drains222aand222bof respective first and second devices220aand220b, and highly doped N type sources224aand224bof respective first and second devices220aand220b, formed in device side214.

As further shown by structure201, gate226aof first device220a, which includes gate dielectric228a, and gate226bof second device220b, which includes gate dielectric228b, are situated over device side214of semiconductor die212. It is noted that highly doped drain222ais separated from highly doped source224aby a P type body region of first device220aextending under gate226a. Similarly, highly doped drain222bis separated from highly doped source224bby a P type body region of second device220bextending under gate226b. Also shown inFIG. 2Aare spacers218asituated over device side214and adjoining gate226a, spacers218balso situated over device side214but adjoining gate226b, and backside216of semiconductor wafer212opposite device side214.

Semiconductor wafer212may include a group IV based substrate, such as a silicon substrate or a silicon carbide (SiC) substrate, for example. Moreover, in some implementations, first and second devices220aand220bmay be fabricated in an epitaxial silicon or other epitaxial group IV layer included as part of semiconductor wafer212(epitaxial layer not explicitly shown inFIGS. 2A-2G). Formation of such an epitaxial layer may be performed by any suitable method, as known in the art, such as chemical vapor deposition (CVD) or molecular beam epitaxy (MBE), for example. In addition, in some implementations, semiconductor wafer212may further include a strained or unstrained germanium (Ge) layer (also not explicitly shown inFIGS. 2A-2G). Thus, first and second devices220aand220bmay be implemented as silicon or other group IV semiconductor devices.

Highly doped N type drains222aand222band highly doped N type sources224aand224bmay be formed by implantation and thermal diffusion of a suitable N type dopant in device side214of semiconductor wafer212. Such a suitable N type dopant may include arsenic (As) or phosphorous (P), for example.

Gates226aand226bmay be formed using any materials typically utilized in the art. For example, gates226aand226bmay include respective conductive gate electrodes formed of doped polysilicon or metal. Gate dielectrics228aand228bmay be formed using any material and any technique typically employed in the art. For example, gate dielectrics228aand228bmay be formed of silicon dioxide (SiO2), and may be deposited or thermally grown to produce gate dielectrics228aand228b. Spacers218aand218bmay analogously be formed using any material and any technique employed in the art. For example, spacers218aand218bmay be formed of silicon nitride (Si3N4), and may be deposited and etched as known in the art.

It is noted that although the implementation shown inFIGS. 2A-2Gdepict first and second devices220aand220bas n-channel lateral FETs (NFETs), that representation is merely exemplary. In other implementations, the described polarities of highly doped N type drains222aand222b, highly doped N type sources224aand224b, and the P type body regions separating those drains and sources may be reversed. In those implementations, one or both of first and second devices220aand220bmay be implemented as p-channel FETs (PFETs).

It is further noted that in the interests of ease and conciseness of description, the present inventive principles will in some instances be described by reference to specific implementations of a silicon based lateral FET. However, it is emphasized that such implementations are merely exemplary, and the inventive principles disclosed herein are broadly applicable for use with a wide variety of device types. For example, in other implementations, first and second devices220aand220bmay take the form of vertical power FETs, such as vertical power metal-oxide-semiconductor FETs (MOSFETs), or may take the form of IGBTs or diodes.

Moving toFIG. 2Bwith continued reference to flowchart100, inFIG. 1, flowchart100continues with forming street trench230within semiconductor wafer212and between first and second devices220aand220b(action102). For example, and as shown by structure202, street trench230may be formed by first forming mask layer232over first and second devices220aand220b. Mask layer232, which may be a photoresist layer, for example, may then be etched or otherwise patterned to enable formation of street trench230in device side214of semiconductor wafer212, between first and second devices220aand220b.

Street trench230may be etched or otherwise patterned in semiconductor wafer212to form a deep street trench. For example, street trench230may be formed to a depth of approximately eighty micrometers (80 μm), or greater, in semiconductor wafer212.

It is noted that the features identified by the same reference numbers inFIGS. 2A-2Gcorrespond respectively to one another and may share any of the characteristics attributed to them by reference to any individual figure of the present application. In other words, semiconductor wafer212, and first and second devices220aand220b, inFIGS. 2B-2G, correspond respectively to semiconductor wafer212, and first and second devices220aand220b, inFIG. 2A, and may share any of the characteristics attributed to those corresponding features in the present application.

Moving now toFIG. 2C, with continued reference to flowchart100, inFIG. 1, flowchart100continues with forming dielectric skeleton structure240over semiconductor wafer212, dielectric skeleton structure240laterally extending to at least partially cover first and second devices220aand220b, and substantially filling street trench230(action103). As shown by structure203, in some implementations, dielectric skeleton structure240may be include first dielectric material242, and second dielectric material244formed over first dielectric material242. For example, first dielectric material242may be one of silicon dioxide or silicon nitride, for example, while second dielectric material may be the other of silicon dioxide or silicon nitride.

It is noted, however, that the use of two dielectric materials to form dielectric skeleton structure240is merely exemplary. In some implementations, dielectric skeleton structure240may be formed of a single dielectric material, such as one of silicon dioxide or silicon nitride, but not the other. Moreover, in some implementations, dielectric skeleton structure240may include more than two dielectric materials.

According to the exemplary implementation shown inFIG. 2C, dielectric skeleton structure240may be formed by first depositing a blanket layer of first dielectric material242over device side214of semiconductor wafer212so as to at least partially fill street trench230. The blanket layer of first dielectric material242may be partially or fully patterned, and another blanket layer of second dielectric material244may be deposited over first dielectric material242. Patterning of first and second dielectric materials242and244results in formation of dielectric skeleton structure240.

As shown inFIG. 2C, according to the present exemplary implementation, dielectric skeleton structure240extends laterally to cover source224a, one of spacers218a, and a portion of gate226aof first device220a, as well as to cover drain222b, one of spacers218b, and a portion of gate226bof second device220b. In addition, and as further shown inFIG. 2C, dielectric skeleton structure240substantially fills street trench230.

As a result, semiconductor wafer212may have thickness236less than or approximately equal to the depth to which street trench230was formed in action102. That is to say, thickness236of wafer212after thinning may be less than or approximately equal to 80 μm. For example, thickness236may be a thickness in a range from approximately 65 μm to approximately 75 μm, or may be a thickness of less than 65 μm. As noted above, dielectric skeleton structure240can be used to provide mechanical support and stability for semiconductor wafer212during thinning.

As shown by structure204, first ultra-thin semiconductor component210ahas sidewall246aadjoined by dielectric skeleton structure240, and second ultra-thin semiconductor component210bhas sidewall246badjoined by dielectric skeleton structure240. Moreover, and as further shown by structure204, in addition to laterally extending to at least partially cover first and second devices220aand220b, dielectric skeleton structure240substantially covers each of sidewall246aof first ultra-thin semiconductor component210aand sidewall246bof second ultra-thin semiconductor component210b.

Referring toFIG. 2E, flowchart100continues with forming backside metalization layer250under semiconductor wafer212(action105). As shown by structure205, metalization layer250may be formed so as to substantially cover back surface234of semiconductor wafer212. Metalization layer250may be formed of aluminum (Al) or copper (Cu), for example, using any technique known in the conventional art.

Moving toFIG. 2F, flowchart100continues with situating semiconductor wafer212over dicing tape260(action106). As shown by structure206, semiconductor wafer212is situated over dicing tape260such that metalization layer250covering back surface234of semiconductor wafer212is in contact with dicing tape260. Dicing tape260may be formed of any material typically used as dicing tape in the art, such polyethylene or polyvinyl chloride (PVC), for example.

Continuing toFIG. 2G, flowchart100can conclude with cutting through dielectric skeleton structure240to singulate first and second ultra-thin semiconductor components210aand210b(action107). As a result of that singulation, die272aof first ultra thin semiconductor component210ais mechanically separated from die272bof second ultra-thin semiconductor componsne210b, as shown by structure207. It is noted that, according to implementations of the present inventive concepts, first and second ultra-thin semiconductor components210aand210bare singulated by cutting through dielectric skeleton structure240, rather than by cutting through semiconductor wafer212itself, thereby advantageously preventing chipping or cracking of dies272aand272bduring singulation.

It is further noted that each of dies272aand272bis an ultra-thin die having thickness236. As noted above by reference to thickness236after thinning of wafer212in action104, thickness236may be less than or approximately equal to 80 μm. For example, thickness236may be a thickness in a range from approximately 65 μm to approximately 75 μm, or may be a thickness of less than 65 μm.

Thus, the present application discloses use of a dielectric skeleton structure during fabrication of ultra-thin semiconductor components. The dielectric skeleton structure provides mechanical support and stabilization for a semiconductor wafer having multiple devices fabricated therein during thinning of the wafer. Ultra-thin semiconductor components including the devices fabricated in the wafer may be singulated by cutting through the dielectric skeleton structure, rather than by cutting through the semiconductor material of the wafer itself. As a result, the ultra-thin semiconductor fabrication solution disclosed in the present application advantageously reduces or substantially eliminates the wafer chipping and cracking that may occur in conventional thin wafer separation processes. Moreover, the ultra-thin semiconductor fabrication solution disclosed in the present application requires a minimum amount of new tooling, and advantageously results in faster and less costly processing.