SEMICONDUCTOR DEVICE WITH LATERAL BASE LINK REGION

A semiconductor device, such as a heterojunction bipolar transistor (HBT), may include an extrinsic base region an intrinsic base region, and a lateral base link region disposed between and in contact with each of the extrinsic base region and an intrinsic base region. The extrinsic base region, the lateral base link region, and a portion of the intrinsic base region each may be formed on a passivation layer disposed over an isolation region and a collector region of a substrate of the semiconductor device. The extrinsic base region and a first portion of the lateral base link region may be formed from polycrystalline semiconductor material. The intrinsic base region and a second portion of the lateral base link region may be formed from monocrystalline semiconductor material. The lateral base link region may be formed after formation of the extrinsic base region and the intrinsic base region.

TECHNICAL FIELD

Embodiments of the subject matter described herein relate generally to transistor devices, including bipolar junction transistors (BJTs) and heterojunction bipolar transistors (HBTs).

BACKGROUND

Semiconductor devices find application in a wide variety of electronic components and systems. Moreover, useful semiconductor devices for radio frequency (RF), microwave, and millimeter wave applications may include BJTs, HBTs, and related devices. In particular, HBTs are useful in high frequency applications because of their fast transit time, high cutoff frequency, high gain, and good linearity properties. These HBTs act as active gain elements and find applications as active devices in RF, microwave, and millimeter wave power amplifiers, oscillators, and other useful electronic components.

SUMMARY

A brief summary of various exemplary embodiments is presented below. Some simplifications and omissions may be made in the following summary, which is intended to highlight and introduce some aspects of the various exemplary embodiments, without limiting the scope. Detailed descriptions of an exemplary embodiment adequate to allow those of ordinary skill in the art to make and use these concepts will follow in later sections.

In an example embodiment, a method includes steps of providing a substrate that includes an isolation region that includes dielectric material and a collector region that includes semiconductor material, and a passivation layer disposed on the substrate, forming an extrinsic base layer on the passivation layer, forming an intrinsic base layer over the collector region, and forming a lateral base link region between the extrinsic base layer and the intrinsic base layer. The lateral base link region is disposed on the passivation layer and directly contacts respective side surfaces of the extrinsic base layer and the intrinsic base layer. The lateral base link region is separated from the collector region by at least the passivation layer.

In one or more embodiments, the extrinsic base layer includes polycrystalline semiconductor material, the intrinsic base layer includes monocrystalline semiconductor material, and the lateral base link region includes a first portion that includes monocrystalline semiconductor material and a second portion that includes polycrystalline semiconductor material.

In one or more embodiments, the first portion of the lateral base link region directly contacts the intrinsic base layer and the second portion of the lateral base link region directly contacts the extrinsic base layer.

In one or more embodiments, the polycrystalline semiconductor material of each of the extrinsic base layer and the first portion of the lateral base link region is selected from the group consisting of polycrystalline silicon and polycrystalline silicon germanium, and the monocrystalline semiconductor material of each of the intrinsic base layer and the second portion of the lateral base link region is selected from the group consisting of monocrystalline silicon and monocrystalline silicon germanium.

In one or more embodiments, the method includes steps of forming a first dielectric stack on the extrinsic base layer, forming an emitter window by etching a first opening in the first dielectric stack and the extrinsic base layer, where the first opening exposes a portion of the isolation region, forming an oxide layer over the first dielectric stack, and removing portions of the oxide layer via a first anisotropic etch process to form a spacer corresponding to a remaining portion of the oxide layer. The spacer is disposed in contact with a side surface of the first dielectric stack and a top surface of the passivation layer.

In one or more embodiments, the method includes steps of removing the portion of the isolation region exposed by the first opening to expose a surface of the collector region, forming a launcher layer on the exposed surface of the collector region via selective epitaxial growth, where forming the intrinsic base layer over the collector region includes forming the intrinsic base layer on the launcher layer via selective epitaxial growth, and forming an emitter cap layer on the intrinsic base layer. The emitter cap layer and the launcher layer each include silicon.

In one or more embodiments, the method includes steps of forming an emitter layer on the emitter cap layer, and forming a second dielectric stack on the emitter layer, where the emitter layer includes polycrystalline semiconductor material, each of the emitter layer and the second dielectric stack are disposed at least partially in the emitter window, and a portion of the emitter layer is disposed on the spacer.

In one or more embodiments, the method includes a step of forming an outside spacer in contact with at least a side surface and a bottom surface of the emitter layer. A portion of the outside spacer includes a portion of a first layer of the first dielectric stack.

In one or more embodiments, the method includes a step of concurrently removing the spacer, a second layer of the first dielectric stack, and a first layer of the second dielectric stack. Removal of the spacer forms a second opening that is disposed between the passivation layer and the emitter layer.

In one or more embodiments, the step of forming the lateral base link region includes forming the lateral base link region in the second opening via selective epitaxial growth of one or more semiconductor materials, respectively, on each of a side surface of the intrinsic base layer and a side surface of the extrinsic base layer.

In an example embodiment, a transistor includes a substrate including a collector region that includes semiconductor material and an isolation region that includes first dielectric material, a dielectric layer that includes second dielectric material, where the dielectric layer is formed over the substrate, a first semiconductor layer disposed on the dielectric layer overlapping the isolation region, a second semiconductor layer disposed over the collector region, where at least a portion of the second semiconductor layer is disposed on the dielectric layer, a third semiconductor layer disposed on the dielectric layer between the first semiconductor layer and the second semiconductor layer, and a fourth semiconductor layer disposed over the second semiconductor layer and the third semiconductor layer.

In one or more embodiments, the first semiconductor layer corresponds to an extrinsic base region, the second semiconductor layer corresponds to an intrinsic base region, the third semiconductor layer corresponds to a lateral base link region, and the fourth semiconductor layer corresponds to an emitter region.

In one or more embodiments, the first semiconductor layer includes semiconductor material selected from the group consisting of polycrystalline silicon and polycrystalline silicon germanium, the second semiconductor layer includes semiconductor material selected from the group consisting of monocrystalline silicon and monocrystalline silicon germanium, the third semiconductor layer includes a first portion that includes semiconductor material selected from the group consisting of monocrystalline silicon and monocrystalline silicon germanium, and the third semiconductor layer includes a second portion that includes semiconductor material selected from the group consisting of polycrystalline silicon and polycrystalline silicon germanium.

In one or more embodiments, the transistor device includes a fifth semiconductor layer disposed between the collector region and the second semiconductor layer and a sixth semiconductor layer disposed between the second semiconductor layer and the fourth semiconductor layer.

In one or more embodiments, the fifth semiconductor layer corresponds to a launcher layer formed from silicon, and the sixth semiconductor layer corresponds to an emitter cap layer formed from silicon.

In one or more embodiments, the transistor device includes an inside spacer disposed between the fourth semiconductor layer and the sixth semiconductor layer, the inside spacer including one or more layers of one or more dielectric materials, and an outside spacer disposed in contact with a side surface of the fourth semiconductor layer and a bottom surface of the fourth semiconductor layer.

In one or more embodiments, the transistor device includes an oxide layer disposed on the bottom surface of the fourth semiconductor layer between the inside spacer and the outside spacer.

In one or more embodiments, the oxide layer is disposed overlapping the third semiconductor layer and is separate from the third semiconductor layer.

In one or more embodiments, the third semiconductor layer is separated from the collector region by at least the dielectric layer.

In one or more embodiments, the third semiconductor layer has a first dopant concentration that is greater than a second dopant concentration of the second semiconductor layer.

DETAILED DESCRIPTION

The following detailed description is merely illustrative in nature and is not intended to limit the embodiments of the subject matter or the application and uses of such embodiments. Furthermore, there is no intention to be bound by any expressed or implied theory presented in the preceding technical field, background, or the following detailed description.

For simplicity and clarity of illustration, the drawing figures illustrate the general manner of construction, and descriptions and details of well-known features and techniques may be omitted to avoid unnecessarily obscuring the invention. Additionally, elements in the drawing figures are not necessarily drawn to scale. For example, the dimensions of some of the elements or regions in the figures may be exaggerated relative to other elements or regions to help improve understanding of embodiments of the invention.

The terms “first,” “second,” “third,” “fourth” and the like in the description and the claims, if any, may be used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the terms so used are interchangeable under appropriate circumstances such that the embodiments of the invention described herein are, for example, capable of operation in sequences other than those illustrated or otherwise described herein. Furthermore, the terms “comprise,” “include,” “have” and any variations thereof, are intended to cover non-exclusive inclusions, such that a process, method, article, or apparatus that comprises a list of elements is not necessarily limited to those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. The term “coupled,” as used herein, is defined as directly or indirectly connected in an electrical or non-electrical manner. As used herein the terms “substantial” and “substantially” mean sufficient to accomplish the stated purpose in a practical manner and that minor imperfections, if any, are not significant for the stated purpose. As used herein, the words “exemplary” and “example” mean “serving as an example, instance, or illustration.” Any implementation described herein as exemplary or an example is not necessarily to be construed as preferred or advantageous over other implementations.

Directional references such as “top,” “bottom,” “left,” “right,” “above,” “below,” and so forth, unless otherwise stated, are not intended to require any preferred orientation and are made with reference to the orientation of the corresponding figure or figures for purposes of illustration.

For the sake of brevity, conventional semiconductor fabrication techniques may not be described in detail herein. In addition, certain terms may also be used herein for reference only, and thus are not intended to be limiting. For instance, the terms “first”, “second”, and other such numerical terms referring to structures do not imply a sequence or order unless clearly indicated by the context.

Various embodiments described herein address the above challenges by providing a transistor, such as a heterojunction bipolar transistor (HBT) and an associated fabrication method in which a lateral base link region is formed between the extrinsic base layer and intrinsic base layer of the HBT. HBT devices typically have a maximum oscillation frequency that is limited by two primary parasitic components: base resistance (i.e., the resistance between the base electrode of the HBT and the intrinsic base region) and collector-base junction capacitance (i.e., the capacitance between the base region of the HBT and the collector region of the HBT. The design and fabrication of HBT devices typically results in a trade-off between the base resistance and collector-base junction capacitance. For example, higher doped, deeper extrinsic base junctions in an HBT tend to result decrease base resistance but result in higher-doped collector junctions, leading to increased collector-base junction capacitance.

Some conventional HBT structures typically include a base link region disposed on the extrinsic base region and connected to a side surface of the intrinsic base region or a base link region disposed under the extrinsic base region and connected to a sidewall of the intrinsic base region, typically resulting in high base resistance due to vertical and horizontal resistance between the intrinsic base region and the extrinsic base region through the base link region. Other conventional HBT structures include a lateral base link region that is disposed directly between the extrinsic base region and the collector region of the HBT, typically resulting in undesirably high collector-base junction capacitance.

In one or more embodiments described herein, an HBT device includes a lateral base link region that laterally couples the intrinsic base region of the HBT device to the extrinsic base region of the HBT. That is, the lateral base link region may extend between a side surface of the extrinsic base region and a side surface of the intrinsic base region. For example, each of the extrinsic base region, the lateral base link region, and a portion of the intrinsic base region may be formed on an upper surface of a passivation layer disposed on a substrate of the HBT device. In one or more embodiments, the lateral base link region may be formed independently from the extrinsic base region and the intrinsic base region. In one or more embodiments, the intrinsic base region may be formed, completely or partially, from monocrystalline silicon (e.g., which may advantageously reduce base resistance of the HBT device). The lateral base link region may be formed (e.g., via selective epitaxial growth) after formation of the intrinsic base region and the extrinsic base region, and may include a first portion that is polycrystalline and a second portion that is monocrystalline, where the presence of monocrystalline material in the lateral base link region may advantageously reduce base resistance of the HBT device. The lateral base link region may be separated from the collector region of the HBT device by at least the passivation layer, which may advantageously reduce collector-base capacitance of the HBT device.

FIG.1is a cross-sectional side view100of a transistor device101, according to an embodiment. The transistor device101may include a base substrate102that includes at least a buried layer104, a collector region106, an isolation region108. The base substrate102may include one or more regions of semiconductor material (e.g., the buried layer104, the collector region106), where such regions of semiconductor material may include one or more of silicon (Si), germanium (Ge), silicon germanium (SiGe), gallium arsenide (GaAs), gallium phosphide (GaP), indium gallium phosphide (InGaP), indium phosphide (InP), gallium nitride (GaN), aluminum nitride (AlN), indium nitride (InN), silicon carbide (SiC), sapphire, or other suitable materials. In some embodiments, one or more regions of semiconductor material (e.g., the buried layer104, the collector region106) of the base substrate102may include semiconductor regions that are formed via ion implantation or that are grown via epitaxial growth. In one or more embodiments, the base substrate102may be a Silicon on Insulator (SOI) substrate that includes a buried oxide layer disposed between a base silicon substrate and a top silicon layer.

It should be understood that only a portion of the base substrate102is shown in the present example. For example, elements that may be included in the base substrate102and that are not shown here may include additional semiconductor regions (as described above), back-side metallization (e.g., a reference plane), and/or one or more metallized through-substrate vias.

In one or more embodiments, the transistor device101may be a heterojunction bipolar transistor (HBT) that includes the collector region106, an intrinsic base region120(sometimes referred herein to as the “intrinsic base layer120”) that is disposed over the collector region106, an extrinsic base region112(sometimes referred to herein as the “extrinsic base layer112”) that partially overlaps the collector region106and at least partially overlaps the isolation region108, and an emitter region128(sometimes referred to herein as the “emitter layer128” that is disposed over the intrinsic base region120. In one or more embodiments, the collector region106, the intrinsic base region120, the extrinsic base region112, and the emitter region128may include one or more of Si, Ge, SiGe, or silicon-germanium-carbon (SiGeC). In one or more other embodiments, the collector region106, the intrinsic base region120, the extrinsic base region112, and the emitter region128may include one or more of Si, Ge, SiGe, GaAs, GaN, AlN, InN, InGaP, and/or other suitable semiconductor materials.

In one or more embodiments, the transistor device101may be configured as a npn transistor such that the collector region106and the emitter region128include n-type semiconductor material and the intrinsic base region120and the extrinsic base region112may each include p-type semiconductor material. In such embodiments, the buried layer104may be a heavily doped N+ buried layer (e.g., with an n-type dopant concentration in a range of around 1e19 cm−3to around 1e21 cm−3although higher or lower dopant concentrations may be used). In other embodiments, the transistor device101may be configured as a pnp transistor such that the collector region106and the emitter region128may include a p-type semiconductor and the intrinsic base region120and the extrinsic base region112may each include n-type semiconductor material. As used herein, the term “n-type semiconductor material” refers to a semiconductor material with a net electron concentration ranging from about 1e15 cm−3to about 1e21 cm−3, though other higher or lower electron concentrations may be used. As used herein, the term “p-type semiconductor material” refers to a semiconductor material with a net hole concentration ranging from about 1e15 cm−3to about 1e21 cm−3, though other higher or lower hole concentrations may be included.

In one or more embodiments, the collector region106may have a total thickness of between around 1,000 angstroms and around 3,000 angstroms. In one or more embodiments, the collector region106may have a total thickness of between around 100 angstroms and around 10,000 angstroms, though other thicknesses may be used. For embodiments in which the collector region106includes n-type semiconductor material (e.g., embodiments in which the transistor device101is a npn transistor), the collector region106may be doped with one or more of phosphorous (P), arsenic (As), antimony (Sb), lithium (Li), or other suitable n-type dopants. For embodiments in which the collector region106includes p-type semiconductor material (e.g., embodiments in which the transistor device101is a pnp transistor), the collector region106may be doped with one or more of carbon (C), boron (B), oxygen (O), or indium (In) or other suitable p-type dopants.

Herein, the term “n-type dopant” refers to material that, upon being integrated into (e.g., diffused through) a semiconductor crystal lattice structure, provides (“donates”) free electrons in the lattice structure, such that electrons become the majority charge carrier in the lattice structure. Such n-type dopants include P, As, Sb, and Li as non-limiting examples. Herein, the term “p-type dopant” refers to material that are electron acceptors and that, upon being integrated into (e.g., diffused through) a semiconductor crystal lattice structure, introduce holes (sometimes referred to as “electron holes”) in the lattice structure, such that holes become the majority charge carrier in the lattice structure. Such p-type dopants include C, B, O, and In as non-limiting examples.

In one or more embodiments, regardless of the dopant type (n-type or p-type) of the collector region106, at least a portion of the collector region106may be doped to have a dopant concentration of between about 5e18 cm−3and about 5e20 cm−3, although other higher or lower dopant concentrations may be used. In one or more embodiments, the collector region106may include multiple doped regions, each having respectively different doping concentrations (e.g., within the previously described range of dopant concentrations or another suitable range of dopant concentrations). For example, the collector region106may include an implanted region116, which may be a selectively implanted collector (SIC) region formed via ion implantation (e.g., self-aligned to an emitter window, as described in more detail below). In one or more embodiments, regardless of dopant type, the implanted region116may have a dopant concentration in a range of around 1e16 cm−3to around 1e19 cm−3although higher or lower dopant concentrations may be used. For example, the dopant concentration of the implanted region116may be selected to achieve a desired collector-base junction breakdown voltage. For example, the collector region106may have a dopant concentration that is between that of the buried layer104and the implanted layer116. In one or more embodiments, the implanted region116may be omitted, in which case the collector region106extends into the area in which the implanted region116is shown to be disposed in the present example. The collector region106may be coupled to a collector electrode (not shown).

The isolation region108may be disposed laterally adjacent to the collector region106, such that a sidewall (i.e., side surface) of the isolation region108is in direct contact with a sidewall (i.e., side surface) of the collector region106. In one or more embodiments, a portion of the isolation region108may extend over a portion of the collector region106. In one or more embodiments, the isolation region108may include one or more of silicon dioxide (SiO2), tetra-ethyl orthosilicate (TEOS), silicon nitride (SiN), silicon oxynitride (SiON), aluminum oxide (Al2O3), aluminum nitride (AlN), spin-on glass, or other suitable dielectric material(s). The buried layer104may be disposed below the collector region106and the isolation region108, and the buried layer104may be separated from the isolation region108by the collector region106(and/or other semiconductor material that may be disposed adjacent to the collector region106).

A launcher layer118(sometimes referred to as a “semiconductor launcher layer118” or as a “buffer layer118”) may be formed over the collector region106(e.g., directly on an upper surface of the collector region106or directly on the implanted region116if present). In one or more embodiments, the launcher layer118may include a low-doped (e.g., between around 1e16 cm−3and about 1e18 cm−3, although other higher or lower dopant concentrations may be used) or undoped semiconductor material (e.g., silicon). The launcher layer118may have the same doping type (e.g., n-type or p-type) as the collector region106, for embodiments in which the launcher layer118is doped. The launcher layer118may be configured to increase the velocity of electrons injected into the collector region106in one or more embodiments. In one or more embodiments, the launcher layer may be an undoped monocrystalline silicon layer that is epitaxially grown on the collector region106.

The intrinsic base region120may be formed over the collector region106(e.g., epitaxially grown directly on the launcher layer118). In one or more embodiments, the intrinsic base region120is formed using Si1-xGexwhere X is the Ge mole fraction. In one or more embodiments, one or more portions of the intrinsic base region120may have a narrower bandgap than the emitter region128and the collector region106. In one or more embodiments, the bandgap of the one or more portions of the intrinsic base region120may be adjusted by changes in the Ge mole fraction. In one or more embodiments, the Ge mole fraction, X, may vary between about 0.05 and about 0.3 though other larger or smaller values of X may be used.

In one or more embodiments, the value of the Ge mole fraction may be constant throughout the intrinsic base region120. In still other embodiments, the bandgap of the intrinsic base region120may be continuously graded. In these embodiments, the material of the intrinsic base region120(e.g., Si1-xGex) may be graded by forming an upper portion of the intrinsic base region120with a wider bandgap and continuously reducing to a narrower bandgap in a lower portion of the intrinsic base region120.

In one or more embodiments, a SiGe:C collector-base spacer (not shown) may be formed between intrinsic base region120and the launcher layer118. The SiGe:C collector-base spacer may be undoped. In one or more embodiments, a SiGe:C base-emitter spacer (not shown) may be formed on the intrinsic base region120(e.g., between the intrinsic base region120and the emitter cap layer122). The SiGe:C base-emitter spacer may be doped or may be undoped, according to various embodiments. In one or more embodiments, the intrinsic base region120may include boron-doped SiGe:C. In one or more such embodiments, the SiGe:C material of any of the collector-base spacer, base-emitter spacer, and the intrinsic base region120may have respective carbon content of around 0.1% and germanium content of around 30%. In such embodiments, the carbon content of the SiGe:C material of any of the collector-base spacer, the base-emitter spacer, and/or the intrinsic base region120may prevent or reduce undesirable diffusion of dopant impurities out of the intrinsic base region120.

In one or more embodiments in which the transistor device101is a pnp transistor, the intrinsic base region120may include n-type semiconductor material, such as semiconductor material doped with P, As, Sb, Li, or another suitable n-type dopant. In one or more embodiments in which the transistor device101is a npn transistor, the intrinsic base region120may include p-type semiconductor material, such as semiconductor material doped with C, B, O, In, or another suitable p-type dopant. The dopant concentration of the intrinsic base region120may be in a range of around 5e17 cm−3to 1e21 cm−3, although higher or lower dopant concentrations may be used.

The extrinsic base region112may be formed over the base substrate102. As shown in the present example, a first portion of the extrinsic base region112may be formed directly over the isolation region108and a second portion of the extrinsic base region112may be formed directly over the collector region106. In one or more embodiments, the extrinsic base region112may be formed from polycrystalline semiconductor material, such as polycrystalline silicon. In one or more embodiments, the extrinsic base region112may be formed from amorphous semiconductor material, such as amorphous silicon or amorphous SiGe. In one or more embodiments in which the transistor device101is a pnp transistor, the extrinsic base region112may include n-type semiconductor material, such as semiconductor material doped with P, As, Sb, Li, or another suitable n-type dopant. In one or more embodiments in which the transistor device101is a npn transistor, the extrinsic base region112may include p-type semiconductor material, such as semiconductor material doped with C, B, O, In, or another suitable p-type dopant. The dopant concentration of the extrinsic base region112may be in a range of around 1e20 cm−3to 1e21 cm−3, although higher or lower dopant concentrations may be used.

One or more dielectric layers, such as a passivation layer110, may be interposed between the extrinsic base region112and the base substrate102. The passivation layer110may at least partially separate and electrically insulate the extrinsic base region112from the collector region106. For example, the passivation layer110may be formed from dielectric material, such as SiO2, TEOS, SiN, SiON, Al2O3, AlN, spin-on glass, or other suitable dielectric material(s). In one or more embodiments, the passivation layer110may be formed from a dielectric material that is different from that of the isolation region108. For example, the isolation region108may be formed from TEOS and the passivation layer110may be formed from nitride material (e.g., AlN or SiN). The extrinsic base region112may be coupled to the intrinsic base region120by a lateral base link region134that includes semiconductor material formed over the passivation layer110. For example, a sidewall136(sometimes referred to as the “side surface136”) of the extrinsic base region112may directly contact a first sidewall (i.e., side surface) of the lateral base link region134and a sidewall137(sometimes referred to as the “side surface137”) of the intrinsic base region120may directly contact a second sidewall137of the lateral base link region134. The lateral base link region134may be doped with the same type of dopant as the extrinsic base region112and may be in a range of around 1e18 cm−3to 1e21 cm−3, although higher or lower dopant concentrations may be used.

In one or more embodiments, the lateral base link region134may include a first portion that is formed from the same semiconductor material as that of the intrinsic base region120(e.g., monocrystalline semiconductor material such as monocrystalline SiGe) and a second portion that is formed from the same semiconductor material as the extrinsic base region112(e.g., polycrystalline or amorphous semiconductor material such as polycrystalline or amorphous silicon or SiGe). In one or more embodiments, portions of each of the extrinsic base region112, the lateral base link region134, and the intrinsic base region120may be disposed directly on the top surface of the passivation layer110.

The extrinsic base region112may be coupled to a base electrode138via a contact layer113, which may be formed using one or more of titanium-tungsten (TiW), titanium tungsten nitride (TiWN), tungsten silicide (WSi), cobalt silicide (CoSi), platinum silicide (PtSi), nickel platinum silicide (NiPtSi), or one or more other suitable material(s). In one or more embodiments, the contact layer113may be formed via silicidation. The base electrode138may be formed from copper, aluminum, tungsten, or another suitable conductive material, for example.

The emitter region128may be formed over the intrinsic base region120. In one or more embodiments in which the transistor device101is a npn transistor, the emitter region128may be formed using n-type semiconductor material, such as semiconductor material doped with one or more of P, As, Sb, Li, or another suitable n-type dopant. In one or more embodiments in which the transistor device101is a pnp transistor, the emitter region128may be formed using p-type semiconductor material, such as semiconductor material doped with one or more of C, B, O, In, or another suitable p-type dopant. The dopant concentration of the emitter region128may be in a range of around 1e19 cm−3to 3e21 cm−3, although higher or lower dopant concentrations may be used.

In one or more embodiments, the emitter region128includes polycrystalline semiconductor material (e.g., polycrystalline silicon). In one or more embodiments, the emitter region128may have a thickness of between about 100 angstroms around 1000 angstroms, although it should be understood that other suitable thicknesses may be used. The intrinsic emitter region128may be coupled to an emitter electrode140via a contact layer114, which may be formed using one or more of TiW, TiWN, WSi, CoSi, PtSi, NiPtSi, or other suitable material(s). In one or more embodiments, the contact layer114may be formed via silicidation. The emitter electrode140may be formed from copper, aluminum, tungsten, or another suitable conductive material, for example.

An emitter cap layer122may be formed over (e.g., directly on) the intrinsic base region120and may be disposed beneath the emitter region128. The emitter cap layer122may form a portion of the emitter-base junction. In one or more embodiments, the emitter cap layer122may be undoped. In or more other embodiments, the emitter cap may be doped with the same type of dopant (i.e., n-type or p-type) as the intrinsic base region120and may have a dopant concentration in a range of around 1e17 cm−3to around 1e18 cm−3, although higher or lower dopant concentrations may be used

An inside spacer124may be disposed between the emitter layer128and each of the lateral base link region134and a portion of the emitter cap layer122. The inside spacer124may include one or more dielectric layers and may provide electrical insulation between the emitter layer128and each of the lateral base link region134and a portion of the emitter cap layer122. In one or more embodiments, the inside spacer124includes multiple dielectric layers, such as an oxide-nitride-oxide (ONO) stack. In one or more other embodiments, the inside spacer124may be formed from one or more layers including one or more of SiO2, TEOS, SiN, SiON, Al2O3, AlN, spin-on glass, or other suitable dielectric material(s).

An outside spacer130may be disposed in contact with a side surface of the emitter region128and a portion of the bottom surface of the emitter region128. The outside spacer130may be formed from one or more dielectric materials such as SiO2, TEOS, SiN, SiON, Al2O3, AlN, other suitable dielectric material(s). Dielectric material126(sometimes referred to as an “oxide layer126”) may be formed on (e.g., directly on) a portion of the bottom side of the emitter region128and may extend between the inside spacer124and the outside spacer130. The dielectric material126may be formed from different material than that of the outside spacer130. For example, the outside spacer130may be formed from nitride material (e.g., AlN, SiN or another suitable nitride material) and the dielectric material126may be formed from oxide material (e.g., TEOS, Al2O3, or another suitable oxide material). The dielectric material126may reduce or otherwise mitigate undesirable formation of semiconductor material on the bottom side of the emitter region128when forming the lateral base link region134(e.g., via selective epitaxial growth).

FIG.2is a process flow diagram depicting a method200for fabricating at least a portion of a transistor device (e.g., a HBT device), such as the transistor device101ofFIG.1, in accordance with various embodiments. For enhanced understanding,FIG.2may be viewed simultaneously withFIGS.3-17, which are cross sectional views depicting the transistor device101ofFIG.1at various stages of fabrication in accordance with various embodiments.

Referring first to step202ofFIG.2and toFIG.3, at a stage of fabrication300, the base substrate102is provided, which includes the buried layer104, the collector region106, and the isolation region108. The passivation layer110may be formed (e.g., deposited via sputtering, plasma deposition, chemical vapor deposition, evaporation or another suitable deposition process) on a top surface of the base substrate102, corresponding to a top surface of the isolation region108. In the present example, the passivation layer110corresponds to a nitride layer (e.g., SiN or AlN as non-limiting examples), and it should be understood that in one or more other embodiments one or more other dielectric materials may additionally or alternatively be included in the passivation layer110, as described above.

The isolation region108may completely or partially separate the collector region106from the passivation layer110at the stage of fabrication300. As described above, the present example shows only a portion of the base substrate102, and it should be understood that the base substrate102may include additional portions (e.g., additional portions of the collector region106and the isolation region108, silicon-on-insulator (SOI), backside metallization, through-silicon vias, and/or the like) not illustrated here. The semiconductor material of the collector region106may be doped with n-type dopant material or p-type dopant material prior to the stage of fabrication300, as described above.

Referring next to step204ofFIG.2and toFIG.4, during a stage of fabrication400, the extrinsic base layer112is formed on an upper surface of the passivation layer110, and a first dielectric stack401is formed on an upper surface of the extrinsic base layer112. The extrinsic base layer112may be formed on the passivation layer110via non-selective epitaxial growth of semiconductor material, such as polysilicon, poly-SiGe, amorphous Si, or amorphous SiGe as non-limiting examples. Herein, “non-selective epitaxial growth” of semiconductor material refers to a process (e.g., a “non-selective epitaxy” process) by which semiconductor material is epitaxially grown on any exposed non-crystalline (e.g., amorphous) surface and any exposed crystalline surface (e.g., on both dielectric material and semiconductor material). Herein, “selective epitaxial growth” of semiconductor material, for comparison, refers to a process (e.g., a “selective epitaxy” process) in which the use of material-selective chemistry increases the seeding time of the grown semiconductor material on non-crystalline (e.g., amorphous) surfaces to such an extent that the semiconductor material is grown on exposed crystalline surfaces and undergoes little or no growth non-crystalline surfaces. For non-selective epitaxy, the semiconductor material that is grown on monocrystalline surfaces has a monocrystalline structure, and the semiconductor material that is grown on non-crystalline surfaces or polycrystalline surfaces has a polycrystalline structure.

After forming the extrinsic base layer112and prior to forming the first dielectric stack401, dopants may be added to the extrinsic base layer112. These dopants may be added in-situ (during deposition of layer112) or added by way of ion implantation. In one or more embodiments in which the transistor device101is a pnp transistor, the extrinsic base layer112may be doped with n-type dopants, such as P, As, Sb, Li, or another suitable n-type dopant. In one or more embodiments in which the transistor device101is a npn transistor, the extrinsic base layer112may be doped with p-type dopants, such as C, B, O, In, or another suitable p-type dopant. The dopant concentration of the extrinsic base layer112may be in a range of around 1e20 cm−3to 1e21 cm−3, although higher or lower dopant concentrations may be used.

The first dielectric stack401may include a first nitride layer402, a first oxide layer404, a second nitride layer406, and a second oxide layer408, each of which may be formed via respective deposition process steps (e.g., each deposited via sputtering, plasma deposition, chemical vapor deposition, evaporation or another suitable deposition process). The first nitride layer402and the second nitride layer406may each be formed from nitride material, such as SiN or AlN, as non-limiting examples. The first oxide layer404and the second oxide layer408may each be formed from oxide material, such as SiO2or TEOS as non-limiting examples. It should be understood that these examples are intended to be illustrative and not limiting. In one or more other embodiments alternating layers of other suitable dielectric materials such as such as SiO2, TEOS, SiN, SiON, Al2O3, or AlN, may be used to form the layers of the first dielectric stack401.

Referring next to step206ofFIG.2and toFIG.5, during a stage of fabrication500, an opening502(corresponding to an emitter window in which the emitter layer128will subsequently be formed) is formed by etching portions of each of the layers of the first dielectric stack401and a portion of the extrinsic base layer112. For example, the opening502may be formed using one or more etch processes, which may include one or more wet chemical etches, reactive ion etches, or other suitable etch processes. In one or more embodiments, portions of the first dielectric stack401that are not to be etched at the stage of fabrication500may be protected using patterned photoresist material (not shown), which may be removed upon completion of the etch process(es). The opening502may be formed over the collector region106. Upon formation of the opening502, a portion of the top surface of the passivation layer110may be exposed. In one or more embodiments, an additional isotropic etch process may be performed after formation of the opening502to remove (e.g., undercut) additional portions of the extrinsic base layer112(e.g., thereby reducing the width of the extrinsic base layer112and reducing the overlap between the extrinsic base layer112and the collector region106).

Referring next to step208ofFIG.2and toFIG.6, during a stage of fabrication600, an oxide layer602(e.g., which may include SiO2or TEOS as non-limiting examples) is formed over the exposed top surface of the passivation layer110and side and top surfaces of the first dielectric stack401(e.g., in contact with side surfaces of the layers402,404,406,408and the top surface of the layer402). For example, the oxide layer602may be deposited via sputtering, plasma deposition, chemical vapor deposition, evaporation or another suitable deposition process. For example, the oxide layer602may have a thickness of around 100 Å to around 600 Å although higher or lower thicknesses may be used.

Referring next to step210ofFIG.2and toFIG.7, during a stage of fabrication700, portions of the oxide layer602, the passivation layer110, and the first nitride layer402of the first dielectric stack401are removed via one or more etch processes. For example, the etch process(es) may remove a portion of the passivation layer110that overlaps the collector region106(e.g., within the opening502), such that a portion of the isolation region108is exposed. In one or more embodiments, the one or more etch processes may be a single reactive ion etch (RIE) process that etches the material (e.g., oxide material) of the oxide layer602and the material (e.g., nitride material) of the passivation layer110and the first nitride layer402at the same or similar (e.g., within around 10% of one another) etch rates. In one or more embodiments, the one or more etch processes may include first and second etch processes, where the first etch process (e.g., a nitride-selective RIE) may etch the oxide layer602and the second etch process (e.g., an oxide-selective RIE) etches the first nitride layer402and the passivation layer110. The etch process may be anisotropic, such that a portion of the oxide layer602remains adjacent to side surfaces of the layers404,406, and408upon completion of the etch process. This remaining portion of the oxide layer602corresponds to a spacer702, which may reduce the width of the emitter window (i.e., the opening502). The removal of the portion of the passivation layer110may increase the depth of the emitter window (i.e., the opening502).

Referring next to step212ofFIG.2and continuing to refer to the stage of fabrication700ofFIG.7, after completion of the etch process(es) performed at step210, the implanted region116may be formed in the collector region106via ion implantation. For example, the implanted region116may be a selectively implanted collector (SIC) (e.g., that is self-aligned to the emitter window). For example, implanted ions may pass through the exposed portion of the isolation region108to reach the collector region106when forming the implanted region116. The implanted region116may be doped with P, As, Sb, Li, or another suitable n-type dopant as non-limiting examples and may be of the same dopant type as the collector region106and the buried layer104. In one or more embodiments, the step212and the corresponding implanted region116may be omitted.

Referring next to step214ofFIG.2and toFIG.8, during a stage of fabrication800, the first oxide layer404and a portion of the isolation region108disposed over the collector region106(and directly over the implanted region116, for one or more embodiments in which the implanted region116is present) are removed via one or more etch processes (e.g., a buffered oxide etch as a non-limiting example). Removal of the first oxide layer404at this stage may expose an upper surface of the second nitride layer406. Removal of the portion of the isolation region108at this stage may expose an upper surface of the collector region106and/or the implanted region116, in accordance with one or more embodiments.

Referring next to step216ofFIG.2and toFIG.9, during a stage of fabrication900, the launcher layer118, the intrinsic base layer120, and the emitter cap layer122are formed via a sequence of epitaxial growth processes. In one or more embodiments, the launcher layer118may be formed on the upper surface of the collector region106and/or the implanted region116via a selective epitaxial growth process, then the intrinsic base layer120may be formed on the launcher layer118via another selective epitaxial growth process, and then the emitter cap layer122may be formed on the intrinsic base region120via yet another selective epitaxial growth process. Each of the launcher layer118, the intrinsic base layer120, and the emitter cap layer122may be formed, respectively, via selective epitaxial growth of one or more semiconductor materials, such as Si, Ge, SiGeC, GaAs, GaN, AlN, InN, InGaP, or another suitable semiconductor material, where the respective type of semiconductor material grown may differ between any of the launcher layer118, the intrinsic base layer120, and the emitter cap layer122. For example, the launcher layer118and the emitter cap layer122may each be formed via selective epitaxial growth of silicon and the intrinsic base region120may be formed via selective epitaxial growth of SiGe. Each of the launcher layer118, the intrinsic base layer120, and the emitter cap layer122may be formed in the opening502, in one or more embodiments. The intrinsic base layer120and the emitter cap layer122may each contact a side surface of the spacer702.

For embodiments in which the transistor101is a npn transistor, the intrinsic base region120may be doped with p-type material, such as C, B, O, In, or another suitable p-type dopant, and the launcher layer118may be undoped or doped with n-type material, such as P, As, Sb, Li, or another suitable n-type dopant. For embodiments in which the transistor101is a pnp transistor, the intrinsic base region120may be doped with n-type material, such as P, As, Sb, Li, or another suitable n-type dopant, and the launcher layer118may be undoped or doped with p-type material, such as C, B, O, In, or another suitable p-type dopant. Emitter cap layer122may be undoped or doped with a similar type as the intrinsic base120. The dopant concentration of the intrinsic base region120may be in a range of around 5e17 cm−3to 1e21 cm−3, although higher or lower dopant concentrations may be used. The launcher layer118may include a low-doped (e.g., between around 1e16 cm−3and about 1e18 cm−3, although other higher or lower dopant concentrations may be used) or undoped semiconductor material.

Referring next to step218ofFIG.2and toFIG.10, during a stage of fabrication1000, the inside spacer124may be formed over a portion of the emitter cap layer122and in contact with a side surface of the spacer702. In one or more embodiments, the inside spacer124may be formed on one or more surfaces of a first portion of the emitter cap layer122, and not on surfaces of a second portion of the emitter cap layer122.

In one or more embodiments, the inside spacer124is formed via isotropic deposition of one or more dielectric materials, such as SiO2, TEOS, SiN, SiON, Al2O3, AlN, or other suitable dielectric materials and subsequent selective anisotropic etching of the one or more dielectric materials. Herein, an “anisotropic etch process” refers to an etch process that is directionally dependent (e.g., the etch rate for the processes in a given direction is higher than the respective etch rates for the process in one or more other directions). Herein, for comparison, [0074] an “isotropic etch process” refers to an etch process that, for a given material, has an etch rate that is constant or substantially constant in all directions (e.g., i.e., the etch rate for the process is not directionally dependent).

In one or more embodiments, the inside spacer124is formed via selective isotropic deposition of a first oxide layer, a nitride layer, and a second oxide layer, sequentially, such that the nitride layer is disposed between the first oxide layer and the second oxide layer of the inside spacer124. That is, in such embodiments, the inside spacer124may include an ONO stack.

Referring next to step220ofFIG.2and toFIG.11, during a stage of fabrication1100, the emitter layer128and a second dielectric stack1101may be formed at least partially in the opening502(i.e., at least partially in the emitter window). For example, the emitter layer128may be formed over the base substrate102via non-selective epitaxial growth of semiconductor material (e.g., Si, Ge, SiGe, GaAs, GaN, AlN, InN, InGaP, and/or other suitable semiconductor materials), then a nitride layer1102of the second dielectric stack1101may be deposited over (e.g., directly on) the emitter layer128, then an oxide layer1102of the second dielectric stack1101may be deposited over (e.g., directly on) the nitride layer1102, and then portions of each of the emitter layer128, the oxide layer1104, and the nitride layer1102may be removed via one or more etch processes.

In one or more embodiments, removal of the portions of emitter layer128, the oxide layer1104, and the nitride layer1102may be performed in conjunction with one or more photolithographic processes in which portions of the emitter layer128, the oxide layer1104, and the nitride layer1102to be preserved during the etch process(es) are protected (e.g., covered) by patterned photoresist material during the etch process(s), where the photoresist material is subsequently removed. Deposition of the nitride layer1102and the oxide layer1104may be performed using one or more deposition processes, such as sputtering, plasma deposition, chemical vapor deposition, evaporation or other suitable deposition processes. In one or more embodiments, the emitter layer128may include polycrystalline and/or amorphous Si or SiGe. In one or more embodiments, the emitter layer128may include a first portion formed from polycrystalline semiconductor material and a second portion formed from amorphous semiconductor material. In one or more other embodiments, the emitter layer128may include a first portion formed from polycrystalline or amorphous semiconductor material and a second portion that is formed from monocrystalline semiconductor material, where the second portion is disposed directly over the emitter cap layer122.

Referring next to step222ofFIG.2and toFIG.12, during a stage of fabrication1200, a first portion of the second nitride layer406of the first dielectric stack may be removed via an anisotropic etch process (e.g., RIE or another suitable anisotropic etch process). After completion of the etch process, a second portion of the second nitride layer406may remain, which may be disposed directly under the emitter layer128. For example, the second portion of the second nitride layer406that remains after the etch process may contact an underside of the emitter layer128, a side surface of the spacer702, and a top surface of the second oxide layer408. In later steps, the second portion of the second nitride layer406may form a portion of the outside spacer130.

Referring next to step224ofFIG.2and toFIG.13, during a stage of fabrication1300, a nitride layer1302is formed via deposition of dielectric material (e.g., SiN, AlN, or another suitable nitride material). In one or more other embodiments, the nitride layer1302may be formed from a material other than nitride, where such material has respectively different etch rates with respect to two or more etch processes compared to the oxide layer1104and the second oxide layer408. For example, the nitride layer1302may formed by depositing dielectric material via sputtering, plasma deposition, chemical vapor deposition, evaporation or another suitable deposition process, then selectively etching (e.g., in conjunction with a photolithographic process) to remove undesired portions of the dielectric material, such that the nitride layer1302remains. The nitride layer1302may be disposed in contact with a top surface of the second oxide layer408and side surfaces of the nitride layer1102, the emitter layer128, and the second portion of the second nitride layer406. In later steps, the nitride layer1302may form a portion of the outside spacer130.

Referring next to step226ofFIG.2and toFIG.14, during a stage of fabrication1400, the spacer702, the second oxide layer408, the oxide layer1104may be removed via an isotropic etch process (e.g., a wet chemical etch process such as a buffered oxide etch (BOE) as a non-limiting example). A portion of the spacer702, corresponding to the dielectric material126, may remain after completion of the etch process, where the dielectric material126may cover (e.g., protect) a portion of the underside (i.e., “bottom side”) of the emitter layer128. For example, the distance by which the outside spacer130extends out from the underside of the emitter layer128(corresponding to the initial height of the second nitride layer406) may be selected such that the dielectric material126is at least partially protected from etching during the etch process. The etch process may form an opening1402defined by surfaces of the passivation layer110, the extrinsic base layer112, the intrinsic base layer120, the emitter cap layer122, the inside spacer124, the dielectric material126, and the outside spacer130. In one or more other embodiments, the dielectric material126may be partially or completely etched away such that a portion of the underside of the emitter layer128is exposed, which may have little or no negative impact on the performance of the transistor101compared to embodiments in which the dielectric material126completely covers the portion the underside of the emitter layer128(e.g., compared to embodiments in which the dielectric material126prevents semiconductor material growth on the portion of the underside of the emitter layer128).

Referring next to step228ofFIG.2and toFIG.15, during a stage of fabrication1500, a selective epitaxial growth process is performed, which forms additional semiconductor material on the extrinsic base layer112(e.g., thereby increasing the thickness of the extrinsic base layer112) and which grows semiconductor material on side surface136of the extrinsic base layer112and the side surface137of the intrinsic base layer120to form the lateral base link region134. In one or more embodiments, the lateral base link region134may include a first portion that is formed from the same semiconductor material as that of the intrinsic base layer120(e.g., monocrystalline semiconductor material such as monocrystalline SiGe) and a second portion that is formed from the same semiconductor material as the extrinsic base layer112(e.g., polycrystalline or amorphous semiconductor material such as polycrystalline or amorphous silicon or SiGe). The first portion of the lateral base link region134may correspond to the semiconductor material that is grown on the side surface137of the intrinsic base layer120by the selective epitaxial growth process, and the second portion of the lateral base link region134may correspond to the semiconductor material that is grown on the side surface136of the extrinsic base layer112by the selective epitaxial growth process. The lateral base link region134may directly contact surfaces of the intrinsic base layer120, the extrinsic base layer112, the passivation layer110, the emitter cap layer122, and the inside spacer124. The lateral base link region134may be disposed entirely over the passivation layer110and the isolation region108, such that portions of the passivation layer110and the isolation region108are interposed between the lateral base link region134and the collector region106.

By forming the lateral base link region134directly over the dielectric material(s) of the passivation layer110and the isolation region108, the collector-base capacitance of the transistor101may be advantageously reduced (e.g., compared to if the base link region were formed directly on the collector region). By forming at least a portion of the base link region from monocrystalline silicon (e.g., the same material as the intrinsic base layer120) in one or more embodiments, base resistance of the transistor101may be advantageously decreased. By forming the lateral base link region134independently from formation of the intrinsic base layer120, each of the lateral base link region134and the intrinsic base layer120may be independently optimized. For example, the lateral base link region134may be more heavily doped than the intrinsic base layer120(e.g., with the same dopant type; with a doping concentration of around 1e20 cm−3to around 1e21 cm−3in one or more embodiments), which may advantageously reduce base resistance of the transistor101. In one or more embodiments, other materials (e.g., Ge) may be incorporated into the lateral base link region (e.g., independently from the intrinsic base layer120), which may improve dopant activation and lower resistance.

Referring next to step230ofFIG.2and toFIG.16, during a stage of fabrication1600, the nitride layer1102is removed via an anisotropic etch process (e.g., RIE or another suitable anisotropic etch process). Removal of the nitride layer1102may expose the top surface of the emitter layer128(e.g., for subsequent silicidation/contact formation).

Referring next to step232ofFIG.2and toFIG.17, during a stage of fabrication1700, the contact layers113and114, the base electrode138, and the emitter electrode140are formed. The contact layer113may be formed on the extrinsic base region112. The contact layer114may be formed on the emitter region128. The base electrode138may be formed over the extrinsic base region112directly on the contact layer113. The emitter electrode140may be formed over the emitter region128directly on the contact layer114. In one or more embodiments, the contact layers113and114are formed via a silicidation process. In one or more embodiments, the base electrode138and emitter electrode140are formed via one more metal deposition processes (e.g., sputtering, evaporation, plating, or another suitable metal deposition process) where the deposited metal is then patterned using suitable photolithography and etch processes. In one or more embodiments, the contact layers113and114include one or more of TiW, TiWN, WSi, CoSi, PtSi, NiPtSi, or one or more other suitable material(s). In one or more embodiments, the base electrode138and the emitter electrode140may include one or more of copper, aluminum, tungsten, or another suitable conductive material.

While, in the examples ofFIGS.2-17, the layers110,130,402,406,1102, and1302have been described as including nitride material in one or more embodiments and the layers126,404,408,602, and1104have been described as including oxide material in one or more embodiments, such arrangements are intended to be illustrative and not limiting. For example, in one or more other embodiments, the layers110,130,402,406,1102, and1302may be formed from a first dielectric material or a first group of dielectric materials and the layers126,404,408,602, and1104may be formed from a second dielectric material or a second group of dielectric materials, where the first dielectric material or first group of dielectric materials may be separately etchable from the second dielectric material or the second group of dielectric materials (and vice versa) with respect to two or more etch processes (e.g., RIE processes, wet chemical etch processes, or other suitable etch processes). That is, with respect to a first etch process, the first dielectric material or first group of dielectric materials may have comparatively higher respective etch rates and the second dielectric material or second group of dielectric materials may have comparatively lower respective etch rates, such that the first etch process may be used to remove exposed portions of the first dielectric material or first group of dielectric materials while removing little or none of the exposed portions of the second dielectric material or second group of dielectric materials. And, with respect to a second etch process (i.e., that is different from the first etch process), the second dielectric material or second group of dielectric materials may have comparatively higher respective etch rates and the first dielectric material or first group of dielectric materials may have comparatively lower respective etch rates, such that the second etch process may be used to remove exposed portions of the second dielectric material or second group of dielectric materials while removing little or none of the exposed portions of the first dielectric material or first group of dielectric materials. The first dielectric material, first group of dielectric materials, second dielectric material, and/or second group of dielectric material may include any suitable combination of dielectric materials (e.g., in view of these comparative etch rate requirements), which may include any of SiO2, TEOS, SiN, SiON, Al2O3, or AlN, or spun glass as non-limiting examples.

It should be understood that, in addition to those processing steps described herein, other processing steps may be performed to complete any of the transistor device101ofFIG.1including, but not limited to, the deposition and patterning of additional dielectric layers and/or metal layers and/or the formation of molding or underfill material.

The foregoing description refers to elements or nodes or features being “connected” or “coupled” together. As used herein, unless expressly stated otherwise, “connected” means that one element is directly joined to (or directly communicates with) another element, and not necessarily mechanically. Likewise, unless expressly stated otherwise, “coupled” means that one element is directly or indirectly joined to (or directly or indirectly communicates with) another element, and not necessarily mechanically. Thus, although the schematic shown in the figures depict one exemplary arrangement of elements, additional intervening elements, devices, features, or components may be present in one or more embodiments of the depicted subject matter.

Furthermore, the term “amplifier” used herein should be understood to refer to a “power amplifier” unless noted otherwise.