Phase locked loop

Phase locked loop circuits capable of increasing an equivalent capacitance thereof to improve stability are provided, in which an integral part comprises a first phase frequency detector providing a phase error signal, a first charge pump circuit generating a control signal according to the phase error signal, a controllable oscillator providing an output clock according to the control signal, and a sampling adjustment unit decreasing the number of times the control signal is updated according to the phase error signal. A proportional part is coupled between the controllable oscillator and a reference clock and operated in a fraction mode.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The invention relates to phase locked loops (PLLs), and more particularly, to a phase locked loop capable of improving stability without greatly increasing chip area thereof.

2. Description of the Related Art

Many different types of integrated circuits (IC) and non-integrated circuits employ clock generating circuits such as phase locked loops (PLL). Some examples of integrated circuits that employ clock generators include, but are not limited to, graphics processors, central processing units, microprocessors, and communication ICs or any other suitable IC that employs clock generators. In order to design a PLL having required characteristics (e.g. low phase noise), a loop filter in the PLL typically requires more than 10 nF of capacitance for stability of the PLL. However, a larger capacitance requires a larger chip area. Hence, there is a need to improve stability of PLLs without greatly increasing chip area.

BRIEF SUMMARY OF THE INVENTION

Embodiments of a phase locked loop are provided, in which an integral part comprises a first phase frequency detector providing a phase error signal, a first charge pump circuit generating a control signal according to the phase error signal, a controllable oscillator providing an output clock according to the control signal, and a sampling adjustment unit decreasing the number of times the control signal is updated according to the phase error signal. A proportional part is coupled between the controllable oscillator and a reference clock and operated in a fraction mode.

The invention also provides another embodiment of a phase locked loop, in which an integral part comprises a controllable oscillator providing an output clock according to a control signal, and a sampling adjustment unit decreasing an updating rate of the control signal. A proportional part is operated in a fraction mode and comprises a first phase frequency detector coupled to a reference clock and a first feedback clock, a first charge pump circuit coupled between the first phase frequency detector and the controllable oscillator, and a first frequency divider frequency-dividing the output clock by a first fractional divisor to generate the first feedback clock.

The invention also provides another embodiment of a phase locked loop, in which a proportional part is operated in a fraction mode to control a controllable oscillator according to a phase error between a reference clock and a first feedback clock. An integral part is operated in an integer mode and comprises first and second frequency dividers frequency-dividing an output clock generated by the controllable oscillator and the reference signal, respectively, to generate a frequency-divided output clock and a frequency-divided reference clock, such that integral part controls the controllable oscillator according to a phase error between the frequency-divided reference clock and the frequency-divided output clock.

The invention also provides an embodiment of a phase locked loop, in which a proportional part is operated in a fraction mode to control a controllable oscillator. An integral part controls the controllable oscillator and comprises a first frequency divider frequency-dividing an output clock generated by the controllable oscillator to generate a frequency-divided output clock, an AND logic unit selectively outputting a phase error signal from a phase frequency detector to a charge pump circuit according to an enabling signal, and a determining unit activating the enabling signal such that the AND logic unit outputs the phase error signal to the charge pump circuit, when a residue of the frequency-divided output clock is accumulated to a threshold value.

DETAILED DESCRIPTION OF THE INVENTION

In order to improve stability for phase locked loops (PLLs), embodiments of the invention increase equivalent capacitance of PLLs by decreasing an update ratio and/or update times of a control signal for a controllable oscillator therein.FIG. 1shows an embodiment of a phase locked loop according to the invention. As shown, the phase locked loop100A comprises an integral part10A and a proportional part20A, providing an output clock SOUTaccording to a reference clock SREF. The integral part10A comprises frequency dividers11and12, a phase frequency detector13, an integral charge pump circuit14, a loop filter15and a controllable oscillator16, and the proportional part20A comprises a phase frequency detector21, a proportional charge pump circuit22, a frequency divider23and a sigma delta modulator (SDM)24(here takes a third-order sigma delta modulator as an example). In this embodiment, the integral part10A is operated in an integer mode and the proportional part20A is operated in a fraction mode.

The frequency divider11frequency-divides the reference clock SREFto generate a frequency-divided input clock SD, and the frequency divider12frequency-divides the output clock SOUTto generate a frequency-divided output clock SFBI. The phase frequency detector13compares the phase and/or frequency differences of the frequency-divided input clock SDwith the frequency-divided output clock SFBIfrom the frequency divider12. Based on these differences, the phase frequency detector13generates an error signal SE. For example, the error signal SEcomprises an up signal and/or a down signal (not shown). The up signal causes the integral charge pump circuit14to source a larger amount of current to the loop filter15(e.g., provide more positive current pulses) and the down signal causes the integral charge pump circuit14to sink more current from the loop filter15(e.g., provide more negative current pulses). As such, the current signal (i.e., control signal SCPI) produced by the integral charge pump circuit14either sources current to or sinks current from the loop filter15. The loop filter15translates the current signal (i.e. the control signal SCPI) from the integral charge pump circuit14into a control voltage. The controllable oscillator16then translates the control voltage into the output clock SOUT. For example, the controllable oscillator16can be a voltage controlled oscillator (VCO) or a current controlled oscillator (CCO), but is not limited thereto.

The frequency divider23is controlled by the sigma delta modulator24to frequency-divide the output clock SOUTto generate a frequency-divided output clock SFBP. The phase frequency detector21compares the phase and/or frequency differences of the reference clock SREFwith the frequency-divided output clock SFBPfrom the frequency divider23. Based on these differences, the phase frequency detector21generates an error signal SEP. Similarly, the error signal SEPcomprises an up signal and/or a down signal (not shown). The up signal causes the proportional charge pump circuit22to source a larger amount of current to the loop filter15(e.g., provide more positive current pulses) and the down signal causes the proportional charge pump circuit22to sink more current from the loop filter15(e.g., provide more negative current pulses). As such, the current signal (i.e., control signal SCPP) produced by the proportional charge pump circuit22either sources current to or sinks current from the loop filter15.

In this embodiment, the frequency divider23and the sigma delta modulator24are configured to frequency-divide the output clock SOUTby a fractional divisor N.f, in which the fractional divisor N.f can be 10.1, 10.2, 10.3 . . . , or any fraction. For example, when the fractional division N.f is 10.1, the frequency divider23frequency-divides the output clock SOUTby 10 (i.e., N) for nine times and then frequency-divides the output clock SOUTby 11 (i.e., N+1) once, and the above frequency-dividing procedures are repeated. When the fractional divisor N.f is 10.2, and the frequency divider23frequency-divides the output clock SOUTby 10 (i.e., N) for four times and then frequency-divides the output clock SOUTby 11 (i.e., N+1) once, and the above frequency-dividing procedures are repeated. Also, the fractional divisor can be 10.5, where the frequency divider23frequency-divides the output clock SOUTby 10 (i.e., N) and 11 (i.e., N+1) in turns. As frequency of the reference clock SREFis 10 MHz, frequency of the output clock SOUTis 101 MHz, thus the fractional divisor is 10.1. With the frequency divider11absent, the output clock SOUTis required to be frequency-divided by 10.1 because the frequencies of the reference clock SREFand the output clock are 10 MHz and 101 MHz, respectively. As such, the phase frequency detector13compares the phase and/or frequency differences of two 10 MHz clocks (i.e., the reference clock SREFand the frequency-divided output clock SFBI), and transfer function of a loop of the frequency divider12, the phase frequency detector13, the integral charge pump circuit14, the loop filter15and the controllable oscillator16in the phase locked loop100A can be represented as

Hcon⁡(s)=(Kp+Kzs×C)×KvcoN×s,
wherein KPrepresents a gain value of the path from phase frequency detector21to the proportional charge pump circuit22; KZrepresents a gain value of the path from phase frequency detector13to the integral charge pump circuit14; s represents ω domain; C represents an equivalent capacitance of the loop filter15; N represents the divisor of the frequency divider12; and Kvco represents the gain of the controllable oscillator16

The frequency divider11serves as a sampling adjustment unit and is configured to cooperate with the frequency divider12thereby decreasing the number of times the control signal SCPIis updated according to the phase error signal SE. For example, the frequency divider11is configured to frequency-divide the reference clock SREFby an integral divisor Q, and the frequency divider12is configured to frequency-divide the output clock SOUTby an integral divisor P, in which

PQ
can be equal to the fractional divisor N.f. As such, the frequency FOUTof the output clock SOUTcan be represented as

FOUT=N·f×FREF=PQ×FREF,
wherein the FREFrepresents the frequency of the reference clock SREF.

Because the frequency of the reference clock SREFis 10 MHz, the fractional divisor is 10.1 and the frequency of the output clock SOUTis 101 MHz, P and Q can be designed as integers, such as 101 and 10, respectively. Since the reference clock SREFof 10 MHz is frequency-divided by 10 and the output clock SOUTof 101 MHz is frequency-divided by 101, the phase frequency detector13compares the phase and/or frequency differences of two 1 MHz clocks (i.e., the frequency-divided input clock SDand the frequency-divided output clock SFBI) rather than two 10 MHz clocks. Accordingly, the number of times the phase error signal SEis generated by the phase frequency detector13is decreased to one tenth of that of the phase locked loop100A without the frequency divider11, i.e., the sampling of the phase error signal SEis decreased to one tenth of that of the phase locked loop100A without the frequency divider11. Hence, the number of times the control signal SCPIis updated according to the phase error signal SEdecreased to one tenth of that of the phase locked loop100A without the frequency divider11, i.e., the update rate of the control signal SCPIis decreased to be one tenth. As such, the charge/discharge period of the loop filter15is increased to 10 times that of the phase locked loop100A without the frequency divider11.

Thus, transfer function of a loop of the frequency divider12, the phase frequency detector13, the integral charge pump circuit14, the loop filter15and the controllable oscillator16in the phase locked loop100A can be represented as

Hopen⁡(s)=(Kp+KzQ×s×C)×KvcoN×s.
Comparing the above two transfer functions, person skilled in the art can understand that the equivalent capacitance of loop filter15in the phase locked loop100A is Q times that of the phase locked loop100A without the frequency divider11, and thus, the system stability of the phase locked loop100A is improved accordingly because system stability of PLLs is proportional to the equivalent capacitance of the loop filter therein.

FIG. 2shows another embodiment of the phase locked loop according to the invention. As shown, the phase locked loop100B is similar to the phase locked loop100A, differing only, in that a sampling adjustment unit comprising a determining unit32and an AND logic unit33is configured to decrease a ratio of the phase error signal SEoutput to the integral charge pump circuit14″ from the phase frequency detector13″, such that the number of times the control signal SCPIis updated according to the phase error signal SEis decreased. Operations and structures of the proportional part20B are similar to those of the proportional part20A, and thus are omitted for simplification.

The frequency divider12″ is controlled by an one-order sigma delta modulator (SDM)31to frequency-divide the output clock SOUTto generate a frequency-divided output clock SFBI. In this embodiment, the frequency divider12″ is controlled to frequency-divide the output clock SOUTby the fractional divisor N.f, which is similar to the frequency divider23, thus the frequency divider12″ and the frequency divider23can be implemented to be a single element to save the layout area. The phase frequency detector13″ compares the phase and/or frequency differences of the reference clock SREFwith a frequency-divided output clock SFBIfrom the frequency divider12″. Based on these differences, the phase frequency detector13″ generates an error signal SE. For example, the error signal SEcomprises an up signal and/or a down signal. The up signal causes the integral charge pump circuit14″ to source a larger amount of current to the loop filter15″ (e.g., provide more positive current pulses) and the down signal causes the integral charge pump circuit14″ to sink more current from the loop filter15″ (e.g., provide more negative current pulses). As such, the current signal (i.e., control signal SCPI) produced by the integral charge pump circuit14″ either sources current to or sinks current from the loop filter15″. The loop filter15″ translates the current signal (i.e. the control signal SCPI) from the charge pump circuit14″ into a control voltage. The controllable oscillator16″ then translates the control voltage into the output clock SOUT.

The SDM31accumulates the residue (i.e., “.f”) generated as the frequency divider12″ frequency-divides the output clock SOUT, enabling the frequency divider12″ to selectively frequency-divide the output clock SOUTby N or N+1 according to the accumulated residue. For example, the SDM31enables the frequency divider12″ to frequency-divide the output clock SOUTby N when the accumulated residue has not overflowed and enables the frequency divider12″ to frequency-divide the output clock SOUTby N+1 when the accumulated residue has overflowed, but is not limited thereto. The determining unit32determines whether the accumulated residue is identical to or greater than a predetermined threshold value, and activates an enabling signal SENwhen the accumulated residue is identical to the predetermined threshold value. The AND logic unit33comprises two input terminals receiving the error signal SEfrom the phase frequency detector13″ and the enabling signal SENfrom the determining unit32, respectively, and outputs the received the error signal SEto the integral charge pump circuit14″ when the enabling signal SENis activated. Therefore, in some embodiments, only the proportional part20B of the phase locked loop100B processes the reference clock SREF, and until the determining unit32determines the accumulated residue is identical to or greater than a predetermined threshold value, the integral part10B joins in the process of the reference clock SREF.

For example, it is assumed that frequencies of the reference clock SREFand the output clock SOUTare 10 MHz and 101 MHz respectively, and the frequency divider12″ is controlled to frequency-divide the output clock SOUTby 10.1 (i.e., the fractional divisor). The SDM31accumulates the residue (i.e., “.f”) generated as the frequency divider12″ frequency-divides the output clock SOUTby 10. When the accumulated residue has overflowed, the SDM31enables the frequency divider12″ to frequency-divide the output clock SOUTby 11, and the accumulated residue is reset and becomes zero at this time. When determining that the accumulated residue is zero, the determining unit32activates the enabling signal SENsuch that the AND logic unit33outputs the phase error signal SEfrom the phase frequency detector13″ to the integral charge pump circuit14″. Namely, the phase error signal SEis output to the integral charge pump circuit14″ from the phase frequency detector13″ only when the accumulated residue has overflowed (i.e., the output clock SOUTis frequency-divided by 11).

In this embodiment, because the fractional divisor is 10.1, the frequency divider12″ frequency-divides the output clock SOUTby 10 for nine times and then frequency-divides the output clock SOUTby 11 once, and the above frequency-dividing procedures are repeated. Accordingly, the number of times (or ratio) the phase error signal SEfrom the phase frequency detector13being output to the integral charge pump circuit14″ is decreased, is one tenth that of the phase locked loop100B without the sampling adjustment unit (i.e., the determining unit32and the AND logic unit33). Hence, the number of times of the control signal SCPIis updated according to the phase error signal SEis decreased to one tenth that of the phase locked loop1008without the sampling adjustment unit, and thus, the update rate of the control signal SCPIis decreased to be one tenth. As such, a person skilled in the art can understand that the equivalent capacitance of the phase locked loop1008is 10 times that of the phase locked loop100B without the sampling adjustment unit, and thus, the system stability of the phase locked loop100B is improved accordingly because system stability of PLLs is proportional to the equivalent capacitance of the loop filter therein.

In some embodiments, the fractional divisor can be 10.2, and the frequency divider12″ frequency-divides the output clock SOUTby 10 for four times and then frequency-divides the output clock SOUTby 11 once, and the above frequency-dividing procedures are repeated. Because the phase error signal SEis output to the integral charge pump circuit14″ from the phase frequency detector13″ only when the accumulated residue has overflowed (i.e., the output clock SOUTis frequency-divided by 11), the number of times (or ratio) the phase error signal SEfrom the phase frequency detector13″ being output to the integral charge pump circuit14″ is decreased, is one fourth that of the phase locked loop100B without the sampling adjustment unit. As such, the equivalent capacitance of the phase locked loop100B is 10 times that of the equivalent capacitance of the phase locked loop100B without the sampling adjustment unit. Also, the fractional divisor can be 10.5, wherein the frequency divider12″ frequency-divides the output clock SOUTby 10 and 11, in turns. Accordingly, the number of times (or ratio) the phase error signal SEfrom the phase frequency detector13″ being output to the integral charge pump circuit14″ is decreased, is half that of the phase locked loop100B without the sampling adjustment unit. Thus, the equivalent capacitance of the phase locked loop100B is double that of the equivalent capacitance of the phase locked loop100B without the sampling adjustment unit.

Thus, the embodiments of the phase locked loops can increase the equivalent capacitance thereof to improve stability without greatly increasing chip area thereof.

Although the invention has been described in terms of preferred embodiment, it is not limited thereto. Those skilled in the art can make various alterations and modifications without departing from the scope and spirit of the invention. Therefore, the scope of the invention shall be defined and protected by the following claims and their equivalents.