Semiconductor device, power conversion device, and method of manufacturing semiconductor device

The present invention has an object of, in a semiconductor device having a vertical structure, providing stable withstand voltage characteristics, reducing a turn-off loss with reduction in leakage current at a time of turn-off, and improving a controllability of a turn-off operation and a blocking capability at a time of turn-off.A buffer layer includes a first buffer layer being joined to an active layer and having one peak point of an impurity concentration and a second buffer layer being joined to the first buffer layer and a drift layer, having at least one peak point of an impurity concentration, and having a maximum impurity concentration lower than that of the first buffer layer, and the maximum impurity concentration of the second buffer layer is higher than the impurity concentration of the drift layer and equal to or lower than 1.0×1015 cm−3.

BACKGROUND OF THE INVENTION

Field of the Invention

The present invention relates to a semiconductor device including a power semiconductor element such as an IGBT and a diode.

Description of the Background Art

Conventional vertical semiconductor devices such as trench-gate IGBTs and PIN diodes have a vertical-structure area. In an IGBT, an area which includes an n-type drift layer, an n-type buffer layer, and a p-type collector layer constitutes the vertical-structure area, and in a diode, an area including an n-type drift layer, an n-type buffer layer, and an n+cathode layer constitutes the vertical-structure area. International Publication No. 2014/054121 discloses the IGBT having the vertical structure.

The conventional vertical semiconductor device having the vertical-structure area such as IGBTs or diodes adopts, in some cases, wafers manufactured by FZ method instead of wafers manufactured by epitaxial growth as Si wafers from which the semiconductor devices are manufactured. In the vertical-structure area of the wafer of, for example, an IGBT, an n-type buffer layer has a high impurity concentration, and its impurity profile has an impurity with a steep gradient across a junction between the n-type buffer layer and the n-type drift layer.

SUMMARY

Such impurity concentration profiles of buffer layers in the semiconductor devices having the vertical structure have had various problems including poor controllability of a turn-off operation and reduction in blocking capability at a time of turn-off.

The present invention has an object of, in a semiconductor device having a vertical structure, providing stable withstand voltage characteristics, reducing a turn-off loss with reduction in leakage current at a time of turn-off, and improving a controllability of a turn-off operation and a blocking capability at a time of turn-off.

A semiconductor device according to a first aspect of the present invention includes a semiconductor body, a buffer layer of a first conductivity type, an active layer, a first electrode, and a second electrode. The semiconductor body has a first main surface and a second main surface and includes a drift layer of a first conductivity type as a main constituent element. The buffer layer is formed adjacent to the drift layer so as to be located closer to the second main surface with respect to the drift layer in the semiconductor body. The active layer is formed on the second main surface of the semiconductor body and has at least one of the first conductivity type and a second conductivity type. The first electrode is formed on the first main surface of the semiconductor body. The second electrode is formed on the active layer. The buffer layer has a first buffer layer and a second buffer layer. The first buffer layer is joined to the active layer and has one peak point of an impurity concentration. The second buffer layer is joined to the first buffer layer and the drift layer, has at least one peak point of an impurity concentration, and has a maximum impurity concentration lower than that of the first buffer layer. The maximum impurity concentration of the second buffer layer is higher than that of the drift layer, and is equal to or lower than 1.0×1015cm−3.

According to the semiconductor device according to the first aspect of the present invention, the second buffer layer has the maximum impurity concentration higher than that of the drift layer, and is equal to or lower than 1.0×1015cm−3, so that achieved are stable withstand voltage characteristics, a reduction in turn-off loss with reduction in leakage current at a time of turn-off, and improvements in controllability of a turn-off operation and blocking capability at a time of turn-off.

A semiconductor device according to a second aspect of the present invention includes a semiconductor body, a buffer layer of a first conductivity type, an active layer, a first electrode, and a second electrode. The semiconductor body has a first main surface and a second main surface and includes a drift layer of a first conductivity type as a main constituent element. The buffer layer is formed adjacent to the drift layer so as to be located closer to the second main surface with respect to the drift layer in the semiconductor body. The active layer is formed on the second main surface of the semiconductor body and has at least one of the first conductivity type and a second conductivity type. The first electrode is formed on the first main surface of the semiconductor body. The second electrode is formed on the active layer. The buffer layer has a first buffer layer and a second buffer layer. The first buffer layer is joined to the active layer and has one peak point of an impurity concentration. The second buffer layer is joined to the first buffer layer and the drift layer and has a maximum impurity concentration lower than that of the first buffer layer. The second buffer layer has an energy level, which is a recombination center, in a band gap of a semiconductor constituting the second buffer layer.

In the semiconductor device according to the second aspect of the present invention, the second buffer layer has an energy level, which is a recombination center, in a band gap of a semiconductor constituting the second buffer layer. Achieved thereby are stable withstand voltage characteristics, a reduction in turn-off loss with reduction in leakage current at a time of turn-off, and improvements in controllability of a turn-off operation and blocking capability at a time of turn-off.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

<Principle of Present Invention>

The present invention relates to a vertical-structure area having the following characteristics (a) to (d) in the semiconductor device including a bipolar power semiconductor element such as an IGBT (Insulated Gate Bipolar Transistor) or a diode which are key components of power modules (with withstand voltage (rated voltage) equal to or higher than 600V).

(a) A reduction in turn-off loss or an operation at high temperature is achieved by increasing the voltage blocking capability in an OFF state and reducing a leakage current at a time of holding withstand voltage at high temperature.

(b) A voltage overshoot at the end of the turn-off operations (hereinafter simply referred to as “the snap-off phenomenon”) and an oscillation caused by the snap-off phenomenon are suppressed.

(c) The blocking capability in a turn-off operation is improved.

(d) The vertical-structure area can be incorporated into a wafer process technique which is also compatible with an increase in size of a diameter, that is equal to or larger than 6 inches, of a wafer for manufacturing a semiconductor.

“The voltage blocking capability under the OFF state” in the characteristic (a) means the voltage holding capability under a static state with no current flowing. “The blocking capability in the turn-off operation” in the characteristic (c) means the voltage holding capability in a dynamic state with a current flowing.

Although an embodiment described hereinafter cites an IGBT and a diode as a typical example of the power semiconductor element, the present invention can also be applied to a power semiconductor such as an RC (Reverse Conducting)-IGBT, an RB (Reverse Blocking)-IGBT, or a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) and enables thereby an acquisition of an effect on the aforementioned object.

Moreover, a semiconductor device using Si as a semiconductor material is exemplified hereinafter, the present invention also has an effect on a semiconductor device made of a wide bandgap material such as silicon carbide (SiC) or gallium nitride (GaN). Furthermore, although a semiconductor device of high withstand-voltage class ranging from 1700 to 6500V is exemplified hereinafter, the present invention has an effect on the aforementioned object regardless of the withstand-voltage class.

FIG. 1,FIG. 2, andFIG. 3are cross-sectional views, each of which illustrates a structure of a semiconductor device having a vertical structure, and the structure illustrated in these drawings forms a base structure of the present invention.FIG. 1illustrates a trench-gate IGBT,FIG. 2illustrates a PIN diode, andFIG. 3illustrates an RFC diode. The RFC diode is a diode formed by connecting a PIN diode and a PNP transistor in parallel. “K. Nakamura et al, Proc. ISPSD2009, pp. 156-158, 2009” and “K. Nakamura et al., Proc. ISPSD2010, pp. 133-136. 2010” describe the RFC diode.

The structure of the trench-gate IGBT is described with reference toFIG. 1. A structure of an active cell area R1of the trench-gate IGBT is firstly described. An N buffer layer15is formed in an undersurface (a second main surface) of an N−drift layer14so as to be adjacent to the N−drift layer14. A P collector layer16of p-type (a second conductivity type) is formed in an undersurface of the N buffer layer15so as to be adjacent to the N buffer layer15. A collector electrode23C is formed in an undersurface of the P collector layer16so as to be adjacent to the P collector layer16. The following description may refer to, as “the semiconductor body”, a structural part at least including the N−drift layer14which is a drift layer of n-type (first conductivity type) and the N buffer layer15which is a buffer layer of n-type. The N−drift layer14forms a main constituent element of the semiconductor body.

An N layer11is formed in an upper layer portion of the N−drift layer14. A P base layer9is formed on a top surface of the N layer11. Gate electrodes13which are made of polysilicon and have a trench structure are formed to vertically penetrate through the P base layer9and the N layer11. The gate electrodes13face the N−drift layer14, the N layer11, the P base layer9, and an N+emitter layer7with a gate insulating film12therebetween. The gate electrodes13, the N+emitter layer7, the P base layer9, and the N layer11thereby form an insulated gate transistor-forming area in an IGBT.

The N+emitter layer7of n-type is formed in a surface layer of the P base layer9to be in contact with the gate insulating film12. P+layers8are formed further in the surface layer of the P base layer9. Interlayer insulating films6are formed on the gate electrodes13. An emitter electrode5E (a first electrode) is formed on a top surface (a first main surface) of the N−drift layer14to be electrically connected to the N+emitter layer7and the P+layer8. The left gate electrode13in the two gate electrodes13illustrated in the active cell area R1inFIG. 1serves as an actual gate electrode, and the right gate electrode13is a dummy electrode with an emitter potential, without serving as an actual gate electrode. An object and effect of the dummy electrode are described in Japanese Patent No. 4205128, Japanese Patent No. 4785334, and Japanese Patent No. 5634318, including, in the IGBT, a suppression in saturation current density, a suppression in oscillation in a state of no-load short-circuit by controlling capacitance characteristics, an improvement in short circuit capacity thereby, and a reduction in ON voltage caused by an improvement in carrier concentration in an emitter side, for example.

Next, a structure of an interface area R2of the trench-gate IGBT is described. A P area22is formed in the upper layer portion of the N−drift layer14. The P area22extends toward the active cell area R1, and is formed deeper than the gate electrode13which is the dummy electrode. The P area22functions as a guard ring.

An insulating film25is formed on the upper surface of the N−drift layer14, and a part of the gate electrode13which is also referred to as a surface gate electrode part and the interlayer insulating film6which surrounds the surface gate electrode part are formed on the insulating film25. An electrode5X functioning as a gate electrode is formed on the surface gate electrode part surrounded by the interlayer insulating films6. The electrode5X is formed simultaneously with the emitter electrode5E in the active cell area R1independently of the emitter electrode5E.

Next, an edge termination area R3of the trench-gate IGBT is described. The P area22is selectively formed in the upper layer portion of the N−drift layer14. The P area22functions as a field ring. Moreover, a configuration except for the P base layer9in the insulated gate transistor structure of the active cell area R1is formed.

The P area22is provided as an area which performs a withstand voltage holding function in each of the interface area R2and the edge termination area R3. The N+emitter layer7and the N layer11in the insulated gate transistor structure of the edge termination area R3are provided to prevent a depletion layer which extends from a p-n junction between the P area22and the N−drift layer14from further extending.

A laminated structure of the insulating films25and the interlayer insulating films6is selectively formed on the upper surface of the N−drift layer14. An electrode5Y electrically connected to the P area22and the gate electrode13is formed to serve as a floating electrode. The electrode5Y is formed simultaneously with the emitter electrode5E in the active cell area R1independently of the emitter electrode5E and the electrode5X.

Subsequently, a passivation film20is formed on the emitter electrode5E and the electrodes5X and5Y across the active cell area R1, the interface area R2, and the edge termination area R3, and a passivation film21is formed on the passivation film20and a part of the emitter electrode5E in the active cell region R1.

Moreover, a vertical-structure area27G is formed between the active cell area R1, the interface area R2, and the edge termination area R3for an IGBT in common. The vertical-structure area27G has a laminated structure of the N−drift layer14and the N buffer layer15which form a semiconductor body, the P collector layer16, and the collector electrode23C.

The structure of the PIN diode is described with reference toFIG. 2. The structure of the active cell area R1of the PIN diode is firstly described. The N buffer layer15is formed in the undersurface which is the second surface of the N−drift layer14. The N+cathode layer17which is an active layer is formed in the undersurface of the N buffer layer15. A cathode electrode23K is formed as a second electrode in an undersurface of the N+cathode layer17.

A P anode layer10is formed as a first electrode area in the upper layer portion of the N−drift layer14. The P anode layer10, the N−drift layer14, the N buffer layer15, and the N+cathode layer17form a PIN diode structure. Subsequently, an anode electrode5A is formed as a first electrode on a first main surface which is a top surface of the P anode layer10.

Next, the structure of the interface area R2of the PIN diode is described. The P area22is formed in the upper layer portion of the N−drift layer14. This P area22extends toward the active cell area R1, and is combined with the P anode layer10. At this time, the P area22is formed deeper than the P anode layer10. This P area22functions as a guard ring.

The insulating films25is formed on the upper surface of the N−drift layer14, the interlayer insulating film24is formed on the insulating film25, and an electrode5A is formed on a part of the interlayer insulating film24.

Next, the structure of the edge termination area R3is described usingFIG. 2. The P area22is selectively formed in the upper layer portion of the N−drift layer14. The P area22functions as a field limiting ring. Moreover, an N+layer26is selectively formed in the surface layer of the N−drift layer14independently of the P area22. The N+layer26is provided to prevent a depletion layer which extends from a junction between the P area22and the N−drift layer14from further extending. As a number of P areas increases, the withstand-voltage class of the PIN diode gets higher.

A laminated structure of the insulating films25and the interlayer insulating films24is selectively formed on the upper surface of the N−drift layer14, and an electrode5Z is formed to be electrically connected to the P area22and the N+layer26. The electrode5Z is formed simultaneously with the anode electrode5A in the active cell area R1independently of the anode electrode5A.

Subsequently, the passivation film20is formed on the anode electrode5A and the electrode5Z across the interface area R2and the edge termination area R3, and the passivation film21is formed on the passivation film20and a part of the anode electrode5A in the interface area R2.

Moreover, a vertical-structure area27D1is formed between the active cell area R1, the interface area R2, and the edge termination area R3for a diode in common. The vertical-structure area27D1has a laminated structure of the N−drift layer14and the N buffer layer15which form a semiconductor body, the N+cathode layer17, and the cathode electrode23K.

Next, the structure of the RFC diode is described usingFIG. 3. The RFC diode has the configuration similar to the PIN diode except for the configuration that a part of the N+cathode layer17which is the active layer is replaced with the P cathode layer18in the active cell area R1of the PIN diode illustrated inFIG. 2. That is to say, the active layer of the RFC diode is configured to include the N+cathode layer17which is a first partial active layer and the P cathode layer18which is a second partial active layer.

The RFC diode enables an acquisition of a characteristic effect in the diode performance, compared with the PIN diode, such as an electrical field relaxation phenomenon in which an electrical field intensity at a side of cathode is reduced, as described in Japanese Patent No. 5256357 and Japanese Patent Application Laid-Open No. 2014-241433. As described in Japanese Patent No. 5256357 or Japanese Patent Application Laid-Open No. 2014-241433 (U.S. Pat. No. 8,686,469), an implantation of a hole from the P cathode layer18is enhanced later in the recovery operation, so that the electrical field intensity at the side of cathode is reduced, the snap-off phenomenon at the end of the recovery operation and the subsequent oscillation phenomenon are suppressed, and the characteristic effect can be acquired in the diode performance such as an enhancement in ruggedness at the time of the recovery operation.

From a standpoint of securing the aforementioned effect, the N+cathode layer17and the P cathode layer18are disposed to satisfy a relationship described in Japanese Patent No. 5256357 or Japanese Patent Application Laid-Open No. 2014-241433 (U.S. Pat. No. 8,686,469). The RFC diode has a diode structure in which the PIN diode and the PNP transistor are connected in parallel when expressed by an equivalent circuit. The N−drift layer14is a variable resistance area.

FIG. 4is an explanatory drawing schematically illustrating a planar structure of a vertical semiconductor device such as an IGBT or a diode. As illustrated inFIG. 4, the plurality of active cell areas R1are formed at a center, a surface gate wiring portion R12is formed between the two active cell areas R1, and a gate pad portion R11is formed in a part of the areas.

The interface area R2is formed to surround the active cell areas R1, the gate pad portion R11, and the surface gate wiring portion R12, and the edge termination area R3is formed to further surround the interface area R2. The structures illustrated inFIG. 1,FIG. 2, andFIG. 3correspond to a cross section A1-A1inFIG. 4.

The aforementioned active cell areas R1are element forming areas for guaranteeing the base performance of a power semiconductor chip. A peripheral area made up of the interface area R2and the edge termination area R3is formed to hold the withstand voltage including reliability. The interface area R2is an area for guaranteeing the ruggedness of a power semiconductor in a joint area of the active cell areas R1and the edge termination area R3when the power semiconductor performs a dynamic operation and for supporting the intrinsic performance (of the semiconductor elements) in the active cell areas R1. The edge termination area R3is an area, in a static state, for holding withstand voltage, providing stable withstand voltage characteristics, guaranteeing the reliability, and suppressing failure in ruggedness in a dynamic operation to support the intrinsic performance in the active cell areas R1.

A vertical-structure area27(the vertical-structure area27G, the vertical-structure area27D1, and a vertical-structure area27D2) is an area for guaranteeing a performance on a total loss, holding a withstand voltage in a static state, providing stable withstand voltage characteristics and stable leakage characteristics at high temperature and guaranteeing reliability, and guaranteeing controllability and ruggedness in a dynamic operation to support the base performance of a power semiconductor. The total loss indicates a loss in which a loss in an ON state and a loss in a turn-on state and turn-off state are added.

<Method of Manufacturing the IGBT>

FIG. 5toFIG. 17are cross-sectional views illustrating a method of manufacturing the IGBT (part1). These drawings illustrate a method of manufacturing the IGBT in the active cell area R1.

A silicon wafer (a silicon wafer or a processed silicon wafer will be hereinafter referred to as a “semiconductor body”) formed by the FZ method is prepared. As illustrated inFIG. 5, an N layer128and a P base layer130are formed in the upper layer portion of the semiconductor body with the N−drift layer14. Specifically, the N layer128and the P base layer130are formed by performing an ion implantation and annealing on the N−drift layer14. A SiO2film129is formed on the P base layer130.

Next, as shown inFIG. 6, an ion implantation and annealing are performed on the semiconductor body to selectively form a plurality of N+emitter layers136in the surface of the P base layer130.

Next, as illustrated inFIG. 7, an oxide film131is formed on the upper surface of the semiconductor body and is patterned using a photograving technique. Then, a reactive ion etching using plasma is performed on portions exposed through openings in the oxide film131to form trenches137. Subsequently, a chemical dry etching and a sacrificial oxidation treatment are performed to remove crystal defects and plasma damaged layers in portions around the trenches137, to round bottom portions of the trenches137, and to flatten inner walls of the trenches137. Japanese Patent Application Laid-Open No. 7-263692, for example, discloses the chemical dry etching and the sacrificial oxidation treatment. Moreover, WO 2009-122486, for example, discloses an appropriate depth of the trenches137.

Subsequently, a gate oxide film134is formed on the trench inner walls by thermal oxidation or chemical vapor deposition (CVD) (see, for example, Japanese Patent Application Laid-Open No. 2001-085686) as illustrated inFIG. 8. Then, a polysilicon layer132doped with phosphorus is formed in the trenches137including the gate oxide film134to fill the trenches137. An oxide film150is formed on the undersurface of the semiconductor body simultaneously with the formation of the gate oxide film134, and a polysilicon layer152doped with phosphorus is formed on the oxide film150simultaneously with the formation of the polysilicon layer132.

Next, a portion of the polysilicon layer132protruding outside the trenches137is etched as illustrated inFIG. 9. After the etching, the polysilicon layer132exposed on the upper surface of the semiconductor body and the polysilicon layer132embedded in and exposed on the trenches137are oxidized or deposited by thermal oxidation or CVD to form an oxide film132a. Then, P+layers138are formed in the upper surface of the semiconductor body. Subsequently, an oxide film140doped with boron or phosphorus and a TEOS film141are formed on the upper surface of the semiconductor body by CVD. A TEOS film or a silicate glass may be formed as the oxide film140. A TEOS film154is formed on the undersurface of the semiconductor body simultaneously with the formation of the oxide film140and the TEOS film141.

Next, as illustrated inFIG. 10, the TEOS film154, the polysilicon layer152, and the oxide film150on the undersurface of the semiconductor body are etched by using a solution containing fluoric acid or a mixture acid (e.g., a mixture solution of fluoric acid, nitric acid, and acetic acid) so as to expose the N− drift layer14.

Subsequently, as shown inFIG. 11, a polysilicon layer160doped with impurities (polysilicon doped with impurities will be hereinafter referred to as “doped polysilicon”) is formed to be in contact with the N−drift layer14exposed at the undersurface of the semiconductor body. At this time, a doped polysilicon layer162which is unwanted is also formed on the upper surface of the semiconductor body. The doped polysilicon layers160and162are formed by low-pressure CVD (LPCVD). The impurities to be doped into the doped polysilicon layers160and162include phosphorus, arsenic, and antimony, for example, to cause the doped polysilicon layers160and162to become N+layers. The impurity concentrations of the doped polysilicon layers160and162are set to be equal to or higher than 1×1019(cm−3). Moreover, film thicknesses of the doped polysilicon layers160and162are set to be equal to or larger than 500 (nm).

Next, as shown inFIG. 12, the semiconductor body is heated in a nitrogen atmosphere at a temperature ranging from approximately 900 to 1000° C. so as to diffuse the impurities in the doped polysilicon layer160to the undersurface of the N−drift layer14. With this diffusion, a gettering layer164having crystal defects and high-concentration impurities is formed on the undersurface of the N−drift layer14. As described above, the gettering layer forming step is a step of forming the gettering layer164on the undersurface of the N−drift layer14exposed on the undersurface of the semiconductor body. The impurity concentration of the surface of the gettering layer164ranges, for example, from 1.0×1019to 1.0×1022(cm−3).

After the gettering layer forming step, the temperature of the semiconductor body is reduced at an arbitrary temperature reducing rate to a temperature approximately ranging from 600 to 700° C., and then the temperature is maintained for four hours or longer. This step is referred to as the annealing step. In the annealing step, the semiconductor body is heated to diffuse metal impurities, contaminant atoms, and damage which have been introduced into the N−drift layer14in the manufacturing steps, and the diffused materials are captured by the gettering layer164.

Next, as shown inFIG. 13, the doped polysilicon layer162on the upper surface of the semiconductor body is selectively removed by using a solution of fluoric acid or a mixture acid (e.g., a mixture solution of fluoric acid, nitric acid, and acetic acid). For example, WO 2014-054121 discloses the gettering processes illustrated inFIG. 11toFIG. 13.

Then, as illustrated inFIG. 14, the oxide film140and the TEO film141on the upper surface of the semiconductor body are partially etched to expose a portion thereof outside, and a trench exposed portion170having contact holes is thereby formed. The portion other than the trench exposed portion170functions as a MOS transistor portion in the IGBT.

An object to be achieved by partially forming the trench exposed portion170in an area where the trenches137filled with the polysilicon layer132, as shown inFIG. 14, is to reduce an effective gate width and adjust a capacitance by setting part of the polysilicon layer132to an emitter potential. This enables a reduction in saturated current density, a suppression of an oscillation at the time of short circuit caused by controlling capacitance, an improvement in short-circuit ruggedness (see WO 2002-058160 and WO 2002-061845 for detailed information), and a reduction in ON voltage caused by improving the carrier concentration at an emitter in an ON state.

Next, a silicide layer and a barrier metal layer are formed on the upper surface of the semiconductor body by sputtering and annealing. A high-melting-point metal material such as Ti, Pt, Co, or W is used as a metal at the time of the sputtering. Next, as shown inFIG. 15, a metal wiring layer144having approximately 1 to 3% of Si added thereto is formed by sputtering on the upper surface of the semiconductor body. Examples of the material of the metal wiring layer144include AlSi, AlSiCu, and AlCu. The metal wiring layer144is electrically connected to the trench exposed portion170.

Next, as shown inFIG. 16, the gettering layer164and the doped polysilicon layer160formed on the undersurface of the semiconductor body are removed by polishing and etching. The step of removing, for example, the gettering layer164is referred to as a removal step. In the removal step, a portion of the N−drift layer14being in contact with the gettering layer164may be removed in a desired thickness. Accordingly, a thickness tD of the semiconductor body (the N−drift layer14) is compatible with the withstand-voltage class of the semiconductor device.

Subsequently, the N buffer layer15is formed in the undersurface of the semiconductor body as illustrated inFIG. 17. The N buffer layer15is formed by implanting impurities and thermal processing such as introducing phosphorus, selenium, and sulfur, or protons (hydrogen) into Si from the undersurface of the semiconductor body and annealing. Subsequently, the p-type P collector layer16is formed on the undersurface of the N buffer layer15. Furthermore, the collector electrode23C is formed on the undersurface of the P collector layer16. The collector electrode23C is a portion to be soldered to the semiconductor body in a module, for example, when the semiconductor device is mounted on a module. Thus, it is preferred to form the collector electrode23C by stacking a plurality of metals to obtain a low contact resistance.

In the relationship betweenFIG. 17andFIG. 1, the polysilicon layers132correspond to the gate electrodes13, the gate oxide film134corresponds to the gate insulating film12, the N layer128corresponds to the N layer11, the P base layer130corresponds to the P base layer9, the N+emitter layers136correspond to the N+emitter layers7, the P+layers138corresponds to the P+layers8, and the metal wiring layer144corresponds to the emitter electrode5E.

<Method of Manufacturing the Diode>

FIG. 18toFIG. 26are cross-sectional views illustrating a method of manufacturing the RFC diode illustrated inFIG. 3.

FIG. 18illustrates the active cell area R1, and the interface area R2and the edge termination area R3formed to surround the active cell area R1. Firstly, a semiconductor body only including the N−drift layer14is prepared. Then, a plurality of P layers52are selectively formed on the surface of the N−drift layer14within the interface area R2and the edge termination area R3. The P layers52are formed by implanting ions using, as a mask, oxide films62preliminarily formed and then annealing the semiconductor body. An oxide film68is also formed on the undersurface of the semiconductor body at the time of forming the oxide films62.

Next, as illustrated inFIG. 19, a P layer50is formed on the surface of the N− drift layer14within the active cell area R1by implanting ions and annealing.

Subsequently, an N+layer56is formed at the end of the edge termination area R3in the upper surface of the semiconductor body as illustrated inFIG. 20. Next, a TEOS layer63is formed on the upper surface of the semiconductor body. Subsequently, the undersurface of the semiconductor body is exposed. Then, a doped polysilicon layer65doped with impurities is formed to be in contact with the N−drift layer14which is exposed on the undersurface of the semiconductor body. At this time, a doped polysilicon layer64is formed also on the upper surface of the semiconductor body.

Next, as illustrated inFIG. 21, the semiconductor body is heated to diffuse the impurities in the doped polysilicon layer65to the undersurface of the N−drift layer14to form a gettering layer55having crystal defects and impurities. This step is similar to the step of forming the gettering layer164in the method of manufacturing the IGBT illustrated inFIG. 12. Subsequently, the annealing step is performed to capture by the gettering layer55metal impurities, contaminant atoms, and damage in the N−drift layer14.

Then, as shown inFIG. 22, the doped polysilicon layer64formed on the upper surface of the semiconductor body is selectively removed by using a solution of fluoric acid or a mixture acid (e.g., a mixture solution of fluoric acid, nitric acid, and acetic acid). This gettering process is the same as the gettering process in the aforementioned IGBT.

Next, as illustrated inFIG. 23, contact holes are formed to expose the P layers52, the P layer50, and the N+layer56on the upper surface of the semiconductor body. That is to say, the TEOS layer63is processed as illustrated inFIG. 23. Then, an aluminum wiring5for the anode electrode5A having approximately 1 to 3% of Si added thereto is formed by sputtering.

Subsequently, a passivation film21is formed on the upper surface of the semiconductor body as illustrated inFIG. 24.

Next, as illustrated inFIG. 25, the gettering layer55and the doped polysilicon layer65formed on the undersurface of the semiconductor body are removed by polishing or etching. Thereby, the thickness tD of the semiconductor body (the N−drift layer14) is compatible with the withstand-voltage class of the semiconductor device.

Then, the N buffer layer15is formed in the undersurface of the N−drift layer14as illustrated inFIG. 26. Subsequently, the P cathode layer18is formed on the undersurface of the N buffer layer15. Then, the N+cathode layers17are partially formed in the P cathode layer18within the active cell area R1. The N buffer layer15, the N+cathode layers17, and P cathode layer18are diffusion layers formed by implanting ions and annealing. Finally, the cathode electrode23K is formed on the undersurface of the semiconductor body.

In the relationship betweenFIG. 26andFIG. 3, the P layer50corresponds to the P anode layer10, the P layers52correspond to the P areas22, the N+layer56corresponds to the N+layer26, and the aluminum wiring5corresponds to the anode electrode5A.

A substrate concentration (Cd) of a Si wafer used for the IGBT or the diode is determined in accordance with the withstand-voltage class of the semiconductor element to be manufactured. For example, Cd=1.0×1012to 5.0×1014cm−3. The Si wafer is made by the FZ method. Then, a thickness of the device is accurately adjusted in accordance with the withstand-voltage class in the wafer process illustrated inFIG. 16orFIG. 25, and the vertical-structure area27is formed in the wafer process illustrated inFIG. 17orFIG. 26. The wafer process, in which the vertical-structure area is formed in the wafer process using the FZ wafer as described above, is becoming mainstream on a background described hereinafter.

a) The wafer in which the N−drift layer14is manufactured as the wafer by the epitaxial method has a demerit that the cost of the Si wafer significantly increases by reason of a dependence on the thickness of Si formed by the epitaxial method. In contrast, an appropriate value of only the concentration of the N−drift layer14is set for each withstand-voltage class using the FZ method, and the Si wafer of the N−drift layer14having the same thickness regardless of the withstand-voltage class is used at a start of wafer process, whereby the wafer of low unit cost can be adopted and the cost of the wafer can be reduced.

b) The thickness in the device is set to have a value required for the withstand-voltage class in a final stage of the wafer process illustrated inFIG. 17or FIG.28for a purpose of utilizing the wafer manufactured by the aforementioned FZ method, and the vertical structure is formed, whereby the wafer process which enables a substantial minimization of converting the process device can be adopted. This enables the wafer process of manufacturing the Si wafer having the large diameter to be also compatible with the wafers having the various thicknesses ranging from 40 μm to 700 μm.

c) The background b) enables a manufacture of, as well as the IGBT and the diode, a MOS transistor structure formed on a surface of a wafer, various diffusion layers, and a device structure such as a wiring structure using a latest process device without change.

The impurity concentration of n drift layer and the thickness in device are device parameters which have influence on not only the withstand voltage characteristics of the IGBT and diode but also the total loss and the controllability and ruggedness in the dynamic operation, and thus need to be highly accurate.

In the wafer process illustrated inFIG. 5toFIG. 17orFIG. 18toFIG. 26, the vertical-structure area is formed after the step of forming the aluminum wiring illustrated inFIG. 15orFIG. 23or the step of forming the passivation film illustrated inFIG. 24. Accordingly, in a case of IGBT, for example, a MOS transistor structure is formed on a surface on which a vertical-structure area is not formed, thereby having an aluminum wiring or a passivation film on the surface. Thus, when the diffusion layer constituting the vertical-structure area (the N buffer layer15, the P collector layer16, the N+cathode layer17, and the P cathode layer18) is formed, required is a consideration that the surface on which the vertical-structure area is not formed needs to have a temperature lower than 660° C., which is a melting point of aluminum being a metal used for the aluminum wiring, so that the annealing is performed using a laser which has a wavelength having a temperature gradient in a depth direction of the device, or the annealing is performed at low temperature of 660° C. or less.

As a result, the impurity profile of the N buffer layer15in the IGBT or the diode manufactured in the aforementioned wafer process is distinctive in that it has a shallow junction depth, that is, a junction depth Xj,aranging from approximately 1.5 to 2.0 μm, and also has a steep concentration gradient (δa=4.52 decade cm−3/μm) across the junction between the N−drift layer14and the N buffer layer15, as the impurity profile of a conventional structure1illustrated inFIG. 33andFIG. 34. In addition, the N buffer layer15has a feature in the process of forming the n layer that the diffusion in the depth direction and a horizontal direction hardly occurs by reason that an N layer profile reproduces a profile in a depth direction at the time of implanting ions for introducing the impurity and the aforementioned annealing technique is used. A technique of forming an n-type diffusion layer having a deep and shallow concentration gradient includes annealing performed at high temperature for a long time. However, this technique cannot be applied in the step in which the metal having the low melting-point is used as described above, so that it is applied early in the wafer process illustrated inFIG. 5orFIG. 18. In the above case, the wafer is processed to have a desired thickness (40 to 700 μm) before or after the step of performing the annealing at high temperature for a long time. Accordingly, each process device needs to be converted to be able to process the wafer with the desired thickness in the subsequent processes, and a huge cost is thereby generated, so that it is unrealistic to apply this technique. Furthermore, the annealing performed at high temperature for a long time is a process technique which does not match the increase in size of the diameter of the Si wafer. The IGBT or the diode having such an N buffer layer15has three significant performance problems described below.

(1) In a high-temperature state, the turn-off loss increases due to the increase in leakage current at the time of holding the withstand voltage, and in addition, a loss of control occurs due to a thermal runaway caused by a heat generation in the device itself, so that the operation under high temperature cannot be guaranteed.

(2) When each of the IGBT and diode performs the dynamic operation such as the turn-off operation, a carrier plasma layer in the vicinity of the junction between the N−drift layer14and the N buffer layer15is depleted due to the relationship between a carrier plasma state inside of the device and the electrical field intensity distribution. The electrical field intensity thereby increases in the junction between the N−drift layer14and the N buffer layer15. Furthermore, the voltage overshoot at the end of turn-off operations (hereinafter simply referred to as “snap-off phenomenon”) and an oscillation triggered by the snap-off phenomenon occur. The snap-off phenomenon causes the voltage to be higher than the withstand voltage which can be held and thereby causes the device to break down. The result causes the IGBT and diode to have a poor controllability of a turn-off operation and a reduction in blocking capability at the time of turn-off. Moreover, the snap-off phenomenon and the subsequent oscillation may cause an inverter system including the power module with the IGBT or the diode to malfunction due to a noise generation. The carrier plasma layer means an intermediate layer in which electrons and holes have almost the same concentration, and a carrier density exceeds 1016cm−3that is higher than a doping carrier concentration Cdof the N−drift layer14by two to three orders of magnitude.

(3) In accordance with the feature at the time of forming the aforementioned N buffer layer15, the IGBT or the diode may be sensitive to a withstand voltage defect phenomenon due to a partial un-formation of the N buffer layer15caused by a scratch or a foreign material on a formation surface of the N buffer layer15generated during the wafer process at the time of forming the vertical-structure area illustrated inFIG. 16,FIG. 17,FIG. 25, andFIG. 26. This causes an increase in level of defectiveness of the IGBT or the diode chip.

Conventionally, methods for optimizing a parameter of the N−drift layer14have been selected as a means for solving the aforementioned problems, such as thickening the N−drift layer14so that the depletion layer is not in contact with the N buffer layer15in a turn-off operation, and increasing the impurity concentration of the N−drift layer14to reduce variations thereof.

However, thickening the N−drift layer14increases the ON voltage of both the IGBT and the diode, and causes a reaction of increase in total loss. On the other hand, reducing variations in impurity concentration of the N−drift layer14impose limitations on the technique for manufacturing Si wafers and on the Si wafers to be adopted, thus increasing costs of the Si wafers. As described above, the conventional IGBT and diode have technical problems that are dilemmas in improving the device performance.

As a solution of the aforementioned problem (2), U.S. Pat. No. 6,482,681, U.S. Pat. No. 7,514,750, and U.S. Pat. No. 7,538,412 propose a formation of N buffer layer15made up of a plurality of layers using protons (H+). However, in these techniques, a concentration of protons needs to be increased to hold the withstand voltage which is a basic characteristic of the power semiconductor in consideration of thinning the N−drift layer14which is a trend for reducing the total loss of the IGBT or the diode. However, since the increase in concentration of the protons is associated with an increase in crystal defect at a time of introducing the protons or an increase in defect density which causes a recombination center of the carrier due to the crystal defect, it has demerits of causing the increase in turn-off loss of the IGBT and the diode and a reduction in ruggedness of the IGBT or the diode as illustrated inFIG. 42described hereinafter. The power semiconductor is required to have the base performance of having the voltage holding capacity while reducing the total loss and guaranteeing the ruggedness. When the turn-off loss increases, an amount of heat generation of IGBT or diode itself increases, and this causes a problem in a high temperature operation or a thermal design of the power module itself provided with a power semiconductor. That is to say, the aforementioned technique does not satisfy a need of the power semiconductor in which the latest N−drift layer14tends to be thinned.

As described above, the conventional techniques on the latest IGBT and diode, in which the thickness of the N−drift layer14has been reduced to improve the performance, that is to say, to reduce the ON voltage, have difficulties in improving the controllability of the turn-off operation and the blocking capability at the time of turn-off and providing stable withstand voltage characteristics as the base performance of the power semiconductor, while controlling the internal state of the device in the dynamic operation. Accordingly, required is the N buffer layer structure which solves the aforementioned problem, using the wafer manufactured by the FZ method, by the wafer process which is also compatible with the increase in size of the diameter of the Si wafer. Moreover, also required is an insensitivity to the withstand voltage defect phenomenon of the IGBT or the diode due to the partial un-formation of the N buffer layer15caused by a bad influence during the wafer process.

The present invention is to solve a dilemma in the device performance of the conventional IGBT or diode using the aforementioned FZ wafer, thereby reducing the ON voltage, providing stable withstand voltage characteristics, reducing turn-off loss with a reduction in leakage current at the time of turn-off, improving the controllability of the turn-off operation, and significantly improving the blocking capability at the time of turn-off.

FIG. 27toFIG. 29are explanatory drawings illustrating a concept of the vertical-structure area proposed by the present invention.FIG. 27illustrates a carrier concentration CC, an impurity profile (doping profile) DP, and an electrical field intensity EF under an ON state, andFIG. 28andFIG. 29illustrate the carrier concentration CC, the impurity profile DP, and the electrical field intensity EF under a blocking voltage state and a dynamic state, respectively. InFIG. 27toFIG. 29, numbers illustrated along a horizontal axis represent constituent elements of the IGBT or the diode, such as the P anode layer10, illustrated inFIG. 1toFIG. 3.

The aforementioned technical problems caused by the problems of the vertical-structure area on the conventional IGBT and diode will be solved by achieving the structure which is the object of the vertical-structure area27, particularly, of the N buffer layer15described below. A concept described below is commonly applicable to the IGBT structure illustrated inFIG. 1and the diode structure illustrated inFIG. 2andFIG. 3.

The concept of the structure of the N buffer layers15constituting the vertical-structure area27proposed by the present invention will be described in (1) to (3) described below.

(1) With regard to a depletion phenomenon of the carrier plasma layer in the vicinity of the junction between the N−drift layer14and the N buffer layer15in a turn-off operation, as illustrated in an area A12ofFIG. 29, the concentration of the N buffer layer15is reduced so that a conductivity modulation phenomenon also occurs inside the N buffer layer15under an ON state of the device and the carrier plasma layer thereby remains. Since the concentration of the carrier plasma layer is equal to or higher than 1016cm−3, the impurity concentration of the N buffer layer15is reduced to be equal to or lower than the concentration of the carrier plasma layer, that is, an order of 1015cm−3. As described above, the impurity concentration of the N buffer layer15is reduced to an extent that the carrier plasma layer remains in the N buffer layer15.

(2) The concentration gradient in the vicinity of the junction between the N−drift layer14and the N buffer layer15is shallowed. Accordingly, as illustrated in an area A21ofFIG. 28, the electrical field intensity is stopped inside the N buffer layer15in a static state, and as illustrated in an area A22ofFIG. 29, the depletion layer smoothly extends inside the N buffer layer15in a dynamic operation.

(3) The N buffer layer15is caused to have a concentration gradient, a low impurity concentration, and an increased thickness, whereby a current amplification factor (αpnp) of a PNP bipolar transistor included in an IGBT or an RFC diode so as to achieve the reduction in turn-off loss caused by a reduction in leakage current at the time of turn-off.

Thus, the present invention aims at optimizing the impurity concentration and the depth of the N buffer layer15in the vertical-structure area27, considering the N buffer layer15as an important layer for controlling a carrier plasma state inside of the device during a device operation while guaranteeing the stable withstand voltage characteristics and the withstand voltage characteristics such as the reduction in turn-off loss.

FIG. 30toFIG. 32are cross-sectional views of the IGBT, PIN diode, and the RFC diode, each of which is the semiconductor device according to the embodiment 1 of the present invention. Each ofFIG. 30toFIG. 32is the cross-sectional view along a cross section A2-A2in the active cell area R1illustrated inFIG. 4, and illustrates the configuration of the IGBT, the PIN diode, and the RFC diode in the active cell area R1illustrated inFIG. 1toFIG. 3. A cross section E-E inFIG. 31corresponds to the horizontal axis of the depth inFIG. 27toFIG. 29described in the principle of present invention. The N−drift layers14illustrated inFIG. 30toFIG. 32are formed with an impurity concentration ranging from 1.0×1012to 5.0×1014cm−3by using the FZ wafers prepared in the FZ (Floating Zone) method. In the IGBT illustrated inFIG. 30, the junction between the P base layer9and the N layer11is a main junction. In the PIN diode illustrated inFIG. 31and the RFC diode illustrated inFIG. 32, the junction between the P anode layer10and the N−drift layer14is the main junction.

The following description exemplifies a parameter of each diffusion layer, taking the RFC diode as a typical example.

P anode layer10: A surface impurity concentration is set equal to or higher than 1.0×1016cm−3, a peak impurity concentration is set to 2.0×1016to 1.0×1018cm−3, and a depth is set to 2.0 to 10.0 μm.

N+cathode layer17: A surface impurity concentration is set to 1.0×1018to 1.0×1021cm−3, and a depth is set to 0.3 to 0.8 μm.

P cathode layer18: A surface impurity concentration is set to 1.0×1016to 1.0×1020cm−3, and a depth is set to 0.3 to 0.8 μm.

The present invention includes two types of structure regarding the N buffer layer15illustrated inFIG. 30toFIG. 32, that is to say, a first structure and a second structure. The N buffer layer15having the first structure is made up of a laminated structure of a first buffer layer15aand a second buffer layer15b. The first buffer layer15ais joined to the P collector layer16, the N+cathode layer17, or the P cathode layer18, and the second buffer layer15bis joined to the N−drift layer14. In the first structure, each of the first buffer layer15aand the second buffer layer15bhas one peak of the impurity concentration.

In the N buffer layer15having the second structure, the second buffer layer15bhaving the first structure is made up as a laminated structure of a first sub-buffer layer15b1to nthsub-buffer layer15bn. The first sub-buffer layer15b1is joined to the first buffer layer15a, and the nthsub-buffer layer15bnis joined to the N−drift layer14. Each of the sub-buffer layers15b1to15bnhas one peak of the impurity concentration. That is to say, the N buffer layer15having the second structure includes the first buffer layer15ajoined to the P collector layer16, the N+cathode layer17, or the P cathode layer18and the second buffer layer15blaminated on the first buffer layer15ato be joined to the N−drift layer14. The second buffer layer15bincludes the first sub-buffer layer15b1, the second sub-buffer layer15b2, . . . and the nthsub-buffer layer15bnlaminated in this order from a side of the first buffer layer15ato a side of the N−drift layer14. Each sub-buffer layer has one concentration peak. The parameters of the first buffer layer15aand second buffer layer15bin the first structure and the second structure are as follows.

A peak impurity concentration Ca,pof the first buffer layer15ais set to 1.0×1016to 5.0×1016cm−3, and a depth Xj,ais set to 1.2 to 5.0 μm.

A maximum peak impurity concentration (Cb,p) max, which is a maximum value of the peak impurity concentration Cb,pof the second buffer layer15bhaving the first structure and each peak impurity concentration of the sub-buffer layers15b1to15bnof the second buffer layer15bhaving the second structure, is set higher than the impurity concentration Cdof the N−drift layer14and equal to or lower than 1.0×1015cm−3. A depth Xj,bof the second buffer layer15bis set to 4.0 to 50 μm. Each of the peak impurity concentration Cb,pof the second buffer layer15bhaving the first structure and the maximum peak impurity concentration (Cb,p) max of the second buffer layer15bhaving the second structure is the maximum impurity concentration of the second buffer layer15b.

FIG. 33illustrates the impurity profile of the first structure and second structure, andFIG. 34is an enlarged view of an area A3inFIG. 33. Each horizontal axis inFIG. 33andFIG. 34illustrates a depth and corresponds to a cross section B-B inFIG. 30and a cross section C-C inFIG. 31andFIG. 32. “0” of the horizontal axis inFIG. 33andFIG. 34corresponds to “B” inFIG. 30,FIG. 31, andFIG. 32. That is to say, the undersurface of the P collector layer16in the IGBT illustrated inFIG. 30, the undersurface of the N+cathode layer17in the PIN diode illustrated inFIG. 31, and the undersurface of the N+cathode layer17or P cathode layer18in the RFC diode illustrated inFIG. 32correspond to “0” of the horizontal axis inFIG. 33andFIG. 34.

InFIG. 33andFIG. 34, an impurity profile of the first structure is illustrated by a thick dotted line L11, and an impurity profile of the second structure is illustrated by a thick solid line L12. Moreover, inFIG. 33andFIG. 34, impurity profiles of conventional structures1and2, which have the conventional vertical-structure area without having the feature of the present invention, are illustrated by a thin solid line L13and a thin dotted line L14, respectively, for comparison.

The depth and the impurity profile of the first buffer layer15aare common in the first structure and the second structure.FIG. 33illustrates the impurity profile of the second structure including the first buffer layer15aand the first sub-buffer layers15b1to fourth sub-buffer layer15b4. InFIG. 33andFIG. 34, a sign is provided to the peak of each impurity profile, and the peak to which a sign “15b1” is provided in the impurity profile of the second structure, for example, indicates the peak of the first sub-buffer layer15b1in the second structure.

The first structure is firstly described with reference toFIG. 33andFIG. 34. The N buffer layer15having the first structure is made up of the first buffer layer15aand the second buffer layer15bformed of a single layer. In the profile of the impurity concentration Cbof the second buffer layer15b(the impurity profile), the peak impurity concentration Cb,pis located at a position closer to the junction Xj,abetween the first buffer layer15aand the second buffer layer15bthan a center of the second buffer layer15b. The impurity profile of the second buffer layer15bhas a low concentration, and also has a concentration gradient δbwhich has a shallow gradient in a depth direction toward the junction between the second buffer layer15band the N−drift layer14. A peak position at a time of introducing an ion species into Si in an ion implantation and an irradiation technique, for example, for forming the second buffer layer15bis set deeper than the junction Xj,abetween the first buffer layer15aand the second buffer layer15bso as to form the peak impurity concentration Cb,pin the position closer to the junction Xj,abetween the first buffer layer15aand the second buffer layer15bthan the center of the second buffer layer15b.

A concentration inclination amount at the side of the main junction in the vicinity of the junction between the second buffer layer15band the N−drift layer14, that is to say, the concentration gradient δb(decade cm−3/μm) is expressed by the following equation (1).

Δ log10Cbrepresents a variation of the impurity concentration Cbof the second buffer layer15billustrated inFIG. 33, and log represents a common logarithm whose base is 10, and Δtbrepresents a variation of a depth tbof the second buffer layer15b.

The depth Xj,aof the junction between the first buffer layer15aand the second buffer layer15bis defined as follows. As shown inFIG. 34, a point where a tangent of an inclination of the impurity profile of the first buffer layer15aand a tangent of an inclination of the impurity profile of the second buffer layer15bcross each other, that is to say, a point at which the gradient of the impurity profile changes from a negative to a positive is defined as the depth Xj,aof the junction. Similarly, the depth Xj,bof the junction between the second buffer layer15band the N−drift layer14is also defined as a point where a tangent of an inclination of the impurity profile of the second buffer layer15band a tangent of an inclination of the impurity profile of the N−drift layer14cross each other illustrated inFIG. 33.

In the first structure, the first buffer layer15aand the second buffer layer15bsatisfy a relationship expressed by the following inequalities (2) to (4).
Ca,p>Cb,p(2)
Xj,a<Xj,b(3)
δa>δb(4)

δa=9.60 (decade cm−3/μm) and δb=0.03 to 0.06 (decade cm−3/μm). The value of δbindicates a range of a structure in which various structure parameters of the N buffer layer15of the present invention described hereinafter is set to a prescribed range to satisfy conditions a) to e) described below.

Next, the second structure is described with reference toFIG. 33andFIG. 34. In the N buffer layer15in the second structure, the second buffer layer15bis made up as a laminated structure of a plurality of sub-buffer layers.FIG. 33illustrates the impurity profile in a case where the second buffer layer15bis made up of four-layered sub-buffer layers. The impurity profile of the first buffer layer15ais similar to that of the first buffer layer15ain the first structure.

The peak impurity concentrations Cb1,p, Cb2,p, . . . , Cbn,pof each sub-buffer layer in the second buffer layer15bare set to be gradually reduced from the junction Xj,abetween the second buffer layer15band the first buffer layer15atoward the junction Xj,b, between the second buffer layer15band the N−drift layer14, that is to say, set to be reduced with a decreasing distance from the main junction, in a depth direction from the second main surface toward the first main surface. Similarly, the concentration gradients δb1, δb2, . . . , δbnthereof are also set to be gradually reduced from the junction Xj,abetween the second buffer layer15band the first buffer layer15atoward the junction Xj,bbetween the second buffer layer15band the N−drift layer14, that is to say, set to be reduced with a decreasing distance from the main junction, in the depth direction from the second main surface toward the first main surface. Distances ΔSn,n-1between the peak points in the adjacent two sub-buffers are equal to each other in the second buffer layer15b. For example, when the distance between the peak points of the impurity concentration inFIG. 33is defined as Sb1,b2between the first sub-buffer layer15b1and the second sub-buffer layer15b2, defined as Sb2,b3between the second sub-buffer layer15b2and the third sub-buffer layer15b3, and defined as Sb3,b4between the third sub-buffer layer15b3and the fourth sub-buffer layer15b4, ΔSb1,b2≈ΔSb2,b3≈ΔSb3,b4. The term “the distances between the peak points are equal to each other” described herein includes not only a case where the distances are exactly equal but also a case where the distances are equal to each other within a range of half-value width of each sub-buffer layer (2 μm).

Each impurity concentration of the sub-buffer layers15b1to15bnconstituting the second buffer layer15bis set higher than the impurity concentration Cdof the N−drift layer14over all areas including the junction between the adjacent two sub-buffer layers.

In the second structure, the first buffer layer15aand the second buffer layer15bsatisfy a relationship expressed by the following inequality (5).
Xj,a<Xj,b(5)

The first buffer layer15aand the first sub-buffer layer15b1satisfy a relationship expressed by the following inequalities (6) and (7).
Ca,p>Cb1,p(6)
δa>δb1(7)

Herein, in the concentration gradient δbnin the vicinity of the junction between the nthsub-buffer layer15bnand the N−drift layer14(also referred to as the concentration gradient at the side of the main junction), δbn=0.14 to 0.50 (decade cm−3/μm) when the various structure parameters of the N buffer layer15of the present invention described hereinafter are set to the prescribed range and the conditions a) to e) described hereinafter are satisfied.

Moreover, in a concentration gradient δ′bobtained by a linear approximation connecting the peak impurity concentrations in each of the sub-buffer layers15b1to15bn, δ′b=0.01 to 0.03 (decade cm−3/μm) when the various structure parameters of the N buffer layer15of the present invention described hereinafter are set to the prescribed range and the conditions a) to e) described hereinafter are satisfied.

In accordance with the aforementioned relationships, the functions of the first buffer layer15aand the second buffer layer15bconstituting the N buffer layer15of the present invention are as illustrated inFIG. 35toFIG. 37, in view of the function of the N buffer layer15, which is targeted, illustrated inFIG. 27toFIG. 29.FIG. 35illustrates the carrier concentration CC, the impurity profile (doping profile) DP, and the electrical field intensity EF under the ON state, andFIG. 36andFIG. 37illustrate the carrier concentration CC, the impurity profile DP, and the electrical field intensity EF under the blocking voltage state and the dynamic state, respectively. InFIG. 35toFIG. 37, numbers illustrated along a horizontal axis represent constituent elements of the IGBT or the diode, such as the P anode layer10, illustrated inFIG. 30toFIG. 32.

As illustrated in an area A21′ ofFIG. 36, the first buffer layer15ahas a function of preventing the depletion layer from extending from the main junction in the static state. Accordingly, the stable withstand voltage characteristics can be obtained, and the reduction in turn-off loss with the reduction in leakage current at the time of turn-off can be achieved.

The impurity concentration of the second buffer layer15bgets higher than the doping profile at the time of forming the second buffer layer15bby the carrier plasma layer generated by a conductivity modulation phenomenon in the ON state, that is to say, in the state where the rated principal current flows (an area A11′ inFIG. 35). As a result, the second buffer layer15bhas a function of further suppressing an extension speed of the depletion layer extending from the main junction in the dynamic state compared with an extension speed in the N−drift layer14and causing the carrier plasma layer generated in the ON state to remain, thereby controlling the electrical field intensity (an area A22′ inFIG. 37). Accordingly, achieved are the suppression of the snap-off phenomenon at the end of the turn-off operation and the oscillation phenomenon caused by the snap-off phenomenon, an improvement in controllability of a switching operation, and the improvement in ruggedness in the dynamic state.

FIG. 38illustrates an evaluation result of crystallinity of Si in the first buffer layer15aand the second buffer layer15bhaving the first structure or second structure of the present invention in accordance with a photoluminescence (PL) method. This evaluation result clarifies a defect level generated in the energy level within the band gap of Si. InFIG. 38, a horizontal axis indicates an energy (eV), and a vertical axis indicates a photoluminescence intensity (a. u.) at a temperature 30K.

InFIG. 38, an evaluation result of the first buffer layer15ais indicated by a dotted line L15, and an evaluation result of the second buffer layer15bis indicated by a solid line L16. It can be considered that the evaluation result of the first buffer layer15ais similar to the evaluation result of the conventional structures1and2which have the conventional vertical-structure area without having the feature of the present invention. Both of the first buffer layer15aand the second buffer layer15bhave a peak derived from an irradiated laser light in 0.98 eV and have a peak caused by a band-edge luminescence in 1.1 eV. The second buffer layer15bfurther has two peaks indicated by areas A31and A32inFIG. 38between the aforementioned two peaks. These peaks indicate that the energy level, which is a recombination center of the carrier (particularly, the hole) is included in the band gap of Si which is the semiconductor constituting the second buffer layer. These levels capture the carrier (herein, the hole) generated in the dynamic operation of the diode as illustrated inFIGS. 49, 53, and 54described hereinafter. As a result, the second buffer layer15bcontributes to a characteristic behavior of suppressing the operation of the PNP transistor area32in the RFC diode inFIG. 32, reducing QRRin the recovery operation of the diode illustrated inFIG. 41described hereinafter, and expanding an SOA (Safe Operation Area) in a snappy recovery mode in the diode. The relationship between the impurity concentration regarding the first structure and second structure of the present invention and the device performance of the IGBT and diode is described hereinafter usingFIGS. 42 to 44, 48, 49, 59, 60, 62, 63, 69, and71, for example. This relationship can also be considered as the result indicating the relationship with the defect density of the recombination center of the second buffer layer15b.

FIG. 39illustrates a simulation result of the electrical field intensity distribution of the RFC diode having the N buffer layer15of the present invention at the time of holding the voltage in the static state. A horizontal axis inFIG. 39indicates a normalized depth ranging from 0 to 1, and 0 corresponds to a mark A inFIG. 32, that is to say, the upper surface of the P anode layer10, and 1 corresponds to a mark B inFIG. 32, that is to say, the undersurface of the N+cathode layer17or P cathode layer18. The vertical axis inFIG. 39indicates the impurity concentration (cm−3) and the electrical field intensity (×103V/cm). Since the device of withstand voltage 1200V class is used in a simulation, the voltage of 1420V is held at a temperature of 25° C. in the static state. InFIG. 39, a dotted line L17having a moderate thickness indicates the impurity profile of the first structure, and a thick dotted line L18indicates the impurity profile of the second structure. A solid line L19having a moderate thickness indicates the electrical field intensity of the first structure, and a thick solid line L20indicates the electrical field intensity of the second structure. A thin dotted line L21indicates the impurity profile of the conventional structure1, and a thin solid line L22indicates the electrical field intensity of the conventional structure1for comparison.FIG. 40is an enlarged view of an area B inFIG. 39.

FIG. 40shows that the depletion layer stops within the first buffer layer15ain the conventional structure1, the first structure, and the second structure when the device holds the voltage. In the first structure and the second structure, the gradient of the electrical field intensity is larger in the second buffer layer15bthan the N−drift layer14, so that it is deemed that the degree of extension of the depletion layer decreases in the second buffer layer15b.

The first buffer layer15aand the second buffer layer15bhaving the aforementioned relationship and function are formed after the step of accurately forming the thickness of the device during the wafer process (FIG. 16orFIG. 25). Herein, the thickness of the device is equal to a distance tD from A to B illustrated inFIG. 30toFIG. 32. Important in the first buffer layer15aand the second buffer layer15bare the order of forming the layers and the setting of the peak position of an acceleration energy at the time of introducing the second buffer layer15b. That is to say, a first ion is implanted from the second main surface of the semiconductor body and the first ion is activated by the annealing to form the first buffer layer, and subsequently, a second ion is implanted from the second main surface of the semiconductor body and the second ion is activated by the annealing to form the second buffer layer. A method of forming them is described in detail hereinafter.

The annealing temperature at the time of forming the first buffer layer15ais higher than the annealing temperature at the time of forming the second buffer layer15b, so that when the first buffer layer15ais formed prior to the second buffer layer15b, the impurity profile after the activation of the second buffer layer15band a type of crystal defect introduced to form the second buffer layer15bare negatively influenced, and the carrier (herein, the hole) in a device ON state is negatively influenced. Accordingly, the second buffer layer15bis formed after the first buffer layer15a. The annealing is performed after introducing the ion into Si, subsequent to the formation of the first buffer layer15a, to form the P collector layer16, N+cathode layer, or the P cathode layer18or after forming the collector electrode23C or the cathode electrode23K, whereby the second buffer layer15bhaving the aforementioned characteristics can be formed.

The peak position of the concentration of the ion species introduced into Si for forming the second buffer layer15bis set as follows. In the first structure, a distance from the peak position to the junction Xj,abetween the first buffer layer15aand the second buffer layer15bis set shorter than a distance from the peak position to the center of the second buffer layer15b. This prevents the first buffer layer15aand the second buffer layer15bfrom interfering with each other, thereby enabling the formation of the second buffer layer15bwhich accurately satisfies the desired relationship between the first buffer layer15aand the second buffer layer15b. In the second structure, distances between the adjacent peak positions in each of sub-buffer layers15b1to15bnconstituting the second buffer layer15b(ΔSb1,b2, ΔSb2,b3, . . . , ΔSb(n-1),bn) is set equal to each other. The term “the distances between the peak points are equal to each other” described herein includes not only a case where the distances are exactly equal but also a case where the distances are equal to each other within a range of half-value width of each sub-buffer layer (2 μm).

Phosphorus is used as the ion species in the first buffer layer15a, and selenium, sulfur, phosphorus, protons (H+), or helium are used as the ion species in the second buffer layer15b. These ion species are introduced into Si with high acceleration energy to form the first buffer layer15aand the second buffer layer15b. When the protons or helium is used, a diffusion-layer forming process technique is used to form an N layer by the annealing at a temperature ranging from 350 to 450° C. using the protons or helium as donors. The protons or helium can be introduced into Si with an irradiation technique using a cyclotron, besides through the ion implantation.

When the protons are introduced into Si, voids occurring in introducing the protons are combined with hydrogen atoms and oxygen atoms to yield a complex defect. Since this complex defect contains hydrogen, it becomes an electron source (donor). When the density of the complex defect increases by the annealing, the donor concentration also increases, and the donor concentration further increases by a mechanism of enhancing a thermal donor phenomenon caused by the ion implantation or the irradiation process. As a result, a layer serving as a donor which has the higher impurity concentration than the N−drift layer14is formed, thus contributing to the device operation as the second buffer layer15b. However, the complex defect formed by introducing the protons also includes a defect which becomes a lifetime killer reducing a lifetime of the carrier, so that it is necessary to cause the second buffer layer15bto serve as the donor after forming the first buffer layer15aas described hereinafter, thus important are a position for performing the ion implantation step of forming the second buffer layer during the manufacturing step and the annealing condition to cause the second buffer layer15bto serve as the donor.

Different methods of annealing are used for activating the first buffer layer15aand the second buffer layer15b, respectively. The annealing temperature at this time is higher in the first buffer layer15athan in the second buffer layer15b. Thus, an activation rate Rbof the second buffer layer15bis smaller than an activation rate Raof the first buffer layer15a, and each diffusion layer is formed in a condition of Rb/Ra=0.01. An activation rate R (%) is expressed by (a dose amount calculated from the impurity profile after the activation/a dose amount of ionic atoms contained in the actual diffusion layer area)×100.

Herein, the dose amount calculated from the impurity profile after the activation indicates a dose amount calculated from a relationship between the impurity concentration and depth of the diffusion layer by Spreading Resistance Analysis. The dose amount of ionic atoms contained in the actual diffusion layer area indicates a dose amount calculated by analyzing a mass of ions in a depth direction by SIMS (Secondary Ion Mass Spectrometry) method.

FIG. 41illustrates a recovery waveform of the diode and a performance parameter extracted from the recovery waveform. InFIG. 41, a horizontal axis indicates a time (×10−6seconds), and a vertical axis indicates an anode-to-cathode voltage VAK(V) and an anode current density JA(A/cm2). A solid line L23inFIG. 41indicates the anode-to-cathode voltage VAKand a dotted line L24indicates the anode current density JA. A snap-off voltage Vsnap-offis a maximum value of VAKin the snappy recovery operation. A power supply voltage VCCcorresponds to VAKat the time of 1.0×10−6seconds. The sign of dV/dt indicates a waveform gradient of VAKwhich is 10 to 50% of VCC. The sign of JFindicates a maximum value of JAat a time of forward bias early in the recovery operation. The sign of JA(break) indicates a maximum blocking current density in the recovery operation. The sing of JRRindicates a maximum reverse recovery current density in the recovery operation. The sign of dj/dt indicates a waveform gradient of JAwhich is 0 to 50% of JF. The sign of max. dj/dt indicates a maximum blocking dj/dt in the recovery operation. The sign of djR,OFF/dt indicates a waveform gradient of JAat the end of a tail current area. The sign of QRRindicates an accumulated charge amount in the recovery operation and is obtained by integrating JAwithin a range of 0A or smaller.

FIG. 42and the subsequent drawings illustrate a relationship between the parameter and the diode performance of the second buffer layer15bof the N buffer layer15of the present invention, using the aforementioned performance parameter illustrated inFIG. 41.FIG. 42toFIG. 44includes a vertical axis, which indicates a diode performance of withstand voltage 1700V class including a withstand voltage BVRRM, a snap-off voltage Vsnap-off, a safe operating temperature in a snappy recovery operation, and a maximum blocking current density JA(break) in a recovery operation, and a vertical axis which indicates a structure parameter of the second buffer layer15bso as to illustrate the relationship between them. As the structure parameter of the second buffer layer15b,FIG. 42illustrates a total dose amount Dose,b(cm−2) of the second buffer layer15b,FIG. 43illustrates a maximum peak impurity concentration (Cb,p) max of the second buffer layer15b, andFIG. 44illustrates a ratio of the total dose amount (Dose′b) after activating the second buffer layer15bto a total dose amount after activating the N buffer layer15. The total dose amount (Dose′b) after activating the N buffer layer15is expressed by a sum of the total dose amounts after activating the first buffer layer15aand the second buffer layer15b(Dose′a+Dose′b).

FIG. 42toFIG. 44illustrate characteristics of the RFC diode inFIG. 32including the second structure. InFIG. 42toFIG. 44, with regard to the second structure, BVRRMis plotted with black circles, Vsnap-offis plotted with black rhombuses, a safe operating temperature is plotted with black triangles, and JA(break) is plotted with black squares, and each plotted point is connected by solid lines L25to L28. InFIG. 42, BVRRMhaving a structure in which the first buffer layer15ais omitted from the second structure is plotted with white circles for reference, and each plotted point is connected by a dotted line L29. Moreover, inFIG. 42, with regard to the conventional structure1, BVRRMis plotted with white circles, Vsnap-offis plotted with white rhombuses, a safe operating temperature is plotted with white triangles, and JA(break) is plotted with white squares for comparison.

The performance parameter indicated by a right axis inFIG. 42toFIG. 44is a performance parameter which is a barometer for ruggedness of the diode. In the aforementioned parameters, Vsnap-offis a performance parameter whose target value is equal to or smaller than a rated voltage. Since the diode of withstand voltage 1700V class is applied this time, the rated voltage is set to 1700V, and the target value of Vsnap-offis 1700V or smaller. The safe operating temperature indicates a safe operating temperature in a snappy recovery operation, and it is indicated that a range of the safe operating temperature increases with a decrease in the value of the temperature. It is indicated that as JA(break) becomes larger, the blocking can be performed at higher current density, and thus the ruggedness increases.

According toFIG. 42, in the second structure which does not include the first buffer layer15a, Dosebneeds to be equal to or higher than 2.0×1014cm−2to increase BVRRM. In contrast, in the second structure which includes the first buffer layer15a, BVRRMis not dependent on Doseb, however, when Dosebis higher than 1.0×1014cm−2, the safe operating temperature increases, and also indicated is a behavior of a reduction in ruggedness that JA(break) decreases. The above results shows that in the structure which does not include the first buffer layer15a, the ruggedness cannot be guaranteed while guaranteeing the voltage-holding capacity, so that the N buffer layer15made up of the first buffer layer15aand the second buffer layer15bis effective in terms of satisfying the various diode performances.

Furthermore, also in the second structure, Dosebneeds to be equal to or lower than 1.0×1014cm−2to set Vsnap-offto 1700V or smaller and guarantee the wide range of the safe operating temperature and the large JA(break) (guarantee the ruggedness). Since the second buffer layer15bneeds to have the higher concentration than the impurity concentration Cdof the N−drift layer14, Dosebneeds to be higher than the dose amount of the n−drift layer14(=Cd×tD). Thus, Dosebneeds to satisfy the following inequality (12) to guarantee the various diode performances and expand the range of the safe operating temperature of the diode. As described above, according to the second structure in which Dosebis set, the various diode performances can be guaranteed compared with the conventional structure1, and moreover, the effect of significantly expanding the range of the safe operating temperature of the diode from 0° C. to −60° C. can be obtained.
Cd×t14<Doseb≤1.0×1014cm−2(12)

According toFIG. 43, when (Cb,p) max is larger than 1.0×1015cm−3, Vsnap-offis equal to or higher than 1700V, and the range of the safe operating temperature is narrowed, so that (Cb,p) max needs to be equal to or smaller than 1.0×1015cm−3. Since the second buffer layer15bneeds to have the higher concentration than the impurity concentration Cdof the N−drift layer14, (Cb,p) max needs to be higher than Cd. Accordingly, (Cb,p) max needs to satisfy the following inequality (13).
Cd<(Cb,p)max≤1.0×1015cm−3(13)

According toFIG. 44, since Dose′b/(Dose′a+Dose′b) has the diode performance close to the conventional structure1when it is equal to or lower than 5%, the range of the safe operating temperature is narrowed. When Dose′a/(Dose′a+Dose′b) is equal to or higher than 40%, Dose′bis equal to or higher than 1.0×1014cm−2, so that Vsnap-offbecomes 1700V or higher, and the range of the safe operating temperature is narrowed. Accordingly, Dose′b/(Dose′a+Dose′b) needs to satisfy the following inequality (14).

FIGS. 45 and 46illustrate a simulation result of an inner state of the device in the analysis point AP1illustrated inFIG. 41to describe a mechanism regarding a characteristic behavior of the second structure such as illustrated inFIGS. 42 to 44. The analysis point AP1illustrated inFIG. 41is set by reference to a point at which the device is broken at a time of setting to (Cb,p) max>1.0×1015cm−3in the RFC diode inFIG. 32having the second structure. The device used in the simulation inFIGS. 45 and 46is the RFC diode illustrated inFIG. 32. In the device used in the simulation inFIG. 45, the maximum impurity concentration (Cb,p) max of the second buffer layer15bis set to (Cb,p) max≤1.0×1015cm−3, and in the device used in the simulation inFIG. 46, the maximum impurity concentration (Cb,p) max of the second buffer layer15bis set to (Cb,p) max>1.0×1015cm−3.

Each horizontal axis inFIGS. 45 and 46indicates a normalized depth.0in the horizontal axis corresponds to the mark A inFIG. 32, that is to say, the uppermost surface of the P anode layer10, and1in the horizontal axis corresponds to the mark B inFIG. 32, that is to say, the surface of the P cathode layer18. The vertical axis indicates the carrier concentration (cm−3) and the electrical field intensity (×103V/cm). InFIGS. 45 and 46, characteristics in the PIN diode area31are indicated by dotted lines, and in the characteristics, an electron concentration is indicated by a thin dotted line L30, a positive hole concentration is indicated by a dotted line L31having a moderate thickness, and the electrical field intensity is indicated by a thick dotted line L32. Characteristics in the PNP transistor area32are illustrated by solid lines, and in the characteristics, an electron concentration is indicated by a thin solid line L33, a positive hole concentration is indicated by a solid line L34having a moderate thickness, and the electrical field intensity is indicated by a thick solid line L35.

In the RFC diode illustrated inFIG. 42toFIG. 44in which the parameter of the second buffer layer15bis appropriately set, as illustrated inFIG. 45, both the PIN diode area31and the PNP transistor area32indicate an electrical strength distribution having a shape close to triangle and trapezoid which becomes maximum in the vicinity of the junction while controlling the carrier plasma layer remaining in the side of the cathode. In such an inner state of the diode, it is considered that the diode performs a stable operation, and there is no negative influence on the ruggedness. However, when the parameter of the second buffer layer15bis set to (Cb,p) max>1.0×1015cm−3as illustrated inFIG. 46, the remaining carrier plasma layer is locally distributed in the vicinity of the junction between the nthsub-buffer layer15bnin the second buffer layer15band the N−drift layer14in the PIN diode area31constituting the RFC diode. Thus, the electrical field intensity increases toward the N+cathode layer17, and unbalance of the electrical field intensity occurs.

The unbalance of the electrical field intensity occurring during the operation of the diode leads to the reduction in ruggedness. That is to say,FIG. 43illustrates the behavior that the ruggedness dramatically decreases when the maximum impurity concentration (Cb,p) max of the second buffer layer is equal to or higher than 1.0×1015cm−3. It is considered that this behavior is triggered by the unbalance of the electrical field intensity occurring in the diode during the recovery operation of the diode as illustrated inFIG. 46.

Similarly, it is also considered that the inner state of the diode in the area where the structure parameter of the horizontal axis illustrated inFIGS. 42 to 44is high is similar to the inner state illustrated inFIG. 46, thereby leading to the reduction in ruggedness. Compared to the cathode areas inFIG. 45andFIG. 46, when the maximum impurity concentration (Cb,p) max of the second buffer layer15bsatisfies (Cb,p) max>1.0×1015cm−3, the area of the carrier plasma layer remaining in the second buffer layer15bis narrowed at the time of dynamic operation, in an area A12′ inFIG. 37, which is one of the functions, which are targeted, of the N buffer layer15, and both the PIN diode are31and the PNP transistor area32are depleted in the second buffer layer15b. That is to say, when the concentration of the second buffer layer15bincreases to satisfy the inequality of (Cb,p) max>1.0×1015cm−3or Doseb>1.0×1014cm−2, the area of the carrier plasma layer remaining in the second buffer layer15bis narrowed and depleted at the time of the dynamic operation, and as a result, the ruggedness of the diode decreases. This behavior also occurs in a case where the value of Doseb/(Dosea+Doseb), which is one of the structure parameters of the second buffer layer15b, is larger than 40%.

The structure parameter of the second buffer layer15balso includes (Cb,p) max/Cdand (Cb,p) max/Ca,pbesides the structure parameters described above. (Cb,p) max/Cdexpresses a relationship between the maximum peak impurity concentration (Cb,p) max of the second buffer layer15band the impurity concentration Cdof the N−drift layer14. Secondly, (Cb,p) max/Ca,pis a parameter expressing a relationship between the maximum peak impurity concentration (Cb,p) max of the second buffer layer15band the peak impurity concentration Ca,pof the first buffer layer15a.

The impurity concentration Cdof the N−drift layer14ranges from 1.0×1012to 5.0×1014cm−3, and the peak impurity concentration Ca,pof the first buffer layer15aranges from 1.0×1016to 5.0×1016cm−3. Thus, according to the inequality (13), the aforementioned parameter needs to satisfy the following inequalities (15) and (16).

However, in view of the range covered by an actual measured data illustrated inFIG. 43, it is appropriate to set (Cb,p) max/Ca,pto satisfy a condition of an inequality (17) so as to guarantee the various performances and the wide range of the safe operating temperature of the diode.

FIG. 47is a graph indicating a relationship in the RFC diode of withstand voltage 6500V class having the second structure between, as a vertical axis, the withstand voltage BVRRMand the diode performance of the safe operating temperature at the time of snappy recovery operation and, as a horizontal axis, (Cb,p) max/Ca,pwhich is the structure parameter of the second buffer layer15b. InFIG. 47, BVRRMis plotted with black circles and each black circle is connected by a solid line L36, and the safe operating temperature is plotted with black triangles and each black triangle is connected by a solid line L37. There is no data of safe operating temperature within the range of (Cb,p) max/Ca,p>0.1, because BVRRMcan only hold the voltage lower than VCCat the time of evaluating the recovery operation, so that the evaluation cannot be performed. With regard to the horizontal axis inFIG. 47, the influence of the first buffer layer15ain the N buffer layer15decreases as (Cb,p) max/Ca,pbecomes larger, and the influence is controlled by the second buffer layer15b, so that B VRRMextremely decreases. In contrast, the influence of the second buffer layer15bin the N buffer layer15decreases as (Cb,p) max/Ca,pbecomes smaller, and the influence is controlled by the first buffer layer15a, so that the range of the safe operating temperature is narrowed. As a result ofFIG. 47, (Cb,p) max/Ca,pwhich is the structure parameter of the second buffer layer15bis set within the range to satisfy an inequality (17), whereby an effective effect satisfying the various diode performances can be obtained.

FIG. 48illustrates a relationship between Vsnap-offand VCCat the time of snappy recovery operation, applying Dosebas a parameter. The RFC diode of withstand voltage 1200V class is used as the evaluation device, and the evaluation is performed on each of the conventional structure1, the first structure, and the second structure. The evaluation result of the conventional structure1is plotted with white circles, and each plotted point is connected by a dotted line L44. The evaluation result of the first structure is plotted with white circles in a case where Doseb=5.0×1013cm−2is satisfied, white triangles in a case where Doseb=1.0×1014cm−2is satisfied, and white squares in a case where Doseb=2.0×1014cm−2is satisfied, and each plotted point is connected by solid lines L38to L40. The evaluation result of the second structure is plotted with black circles in a case where Doseb=5.0×1013cm−2is satisfied, black triangles in a case where Doseb=1.0×1014cm−2is satisfied, and black squares in a case where Doseb=2.0×1014cm−2is satisfied, and each plotted point is connected by solid lines L41to L43.

The diode performance is deemed to be better as Vsnap-offbecomes smaller, and Vsnap-offneeds to be made smaller than the rated voltage of the evaluation diode.FIG. 48shows that the value of Vsnap-offis higher in the first structure and the second structure than in the conventional structure1, and Doseb≤1.0×1014cm−2is necessary to satisfy Vsnap-off≤1200V.

FIG. 49illustrates a recovery waveform under snappy recovery condition at a temperature of −20° C. or less in the RFC diode of withstand voltage 1200V class. The other switching conditions are VCC=1000V, JF=0.1 JA, dj/dt=1000 A/cm2μs, dV/dt=12500V/μs, and Ls=2.0 μH. A horizontal axis inFIG. 49indicates a time (×10−6seconds), and a vertical axis indicates an anode-to-cathode voltage VAK(V) and an anode current density JA(A/cm2). VAKin the conventional structure1is illustrated by a thin solid line L45, and JAis illustrated by a thin dotted-line L46. VAKin the first structure1is illustrated by a solid line L47having a moderate thickness, and JAis illustrated by a dotted-line L48having a moderate thickness. VAKin the second structure is illustrated by a thick solid line L49, and JAis illustrated by a thick dotted-line L50.

FIG. 49shows, differing fromFIG. 61described hereinafter, that the snap-off phenomenon and the subsequent oscillation phenomenon do not occur at the time of snappy recovery operation. This is an effect of the RFC diode. A cross mark in the waveform of the conventional structure1inFIG. 49indicates a point at which the device has been broken. According toFIG. 49, in the conventional structure1, an enormous tail current occurs in the last half of recovery operation at a temperature of −20° C. and the device is broken. In contrast, in the first structure and the second structure, the tail current in the last half of recovery operation decreases and is blocked without the breakdown of the device. The mechanism of the behavior of the conventional structure1described above is caused by the characteristic behavior of the diode in the recovery operation. The parameter of the diode performance functioning as a barometer for determining whether the enormous tail current occurs at the time of the recovery operation of the diode is the value of QRRinFIG. 41.

The aforementioned result shows that the snappy recovery operation at the temperature of −20° C. cannot be guaranteed in the conventional structure1, but can be guaranteed in the first structure and the second structure. That is to say, the first structure and the second structure have the effect of suppressing the operation of the PNP transistor area32in the recovery operation while suppressing the snap-off phenomenon at the end of the recovery operation, which is a characteristic of the RFC diode, and the subsequent oscillation phenomenon, whereby the balanced operation is achieved.

FIG. 50illustrates a relationship between Vsnap-offand VCCat the time of snappy recovery operation using the impurity profile of the second buffer layer15bhaving the second structure as a parameter. InFIG. 50, a horizontal axis indicates VCC(V), and a vertical axis indicates Vsnap-off(V). The RFC diode of withstand voltage 1200V class is used as the evaluation device. A cross mark inFIG. 50indicates a point at which the device has been broken. InFIG. 50, characteristics in a state of δbn<δb(n-1)and Cbn,p<Cb(n-1),pare plotted with black circles, characteristics in a state of δbn=δb(n-1)and Cbn,p=Cb(n-1),pare plotted with white circles, characteristics in a state of δbn>δb(n-1)and Cbn,p>Cb(n-1),pare plotted with black triangles, and each plotted point is connected by solid lines L51to L53. The concentration profile of δbn<δb(n-1)and Cbn,p<Cb(n-1),pis the concentration profile of the second structure illustrated inFIG. 33. The concentration profile of δbn=δb(n−1) and Cbn,p=Cb(n-1),pis a flat concentration profile. The concentration profile satisfying δbn>δb(n-1)and Cbn,p>Cb(n-1),pis the concentration profile whose concentration decreases from a side of N−drift layer14of the second buffer layer15btoward a side of the first buffer layer15a.FIG. 50shows that when the concentration profile of the second buffer layer15bhaving the second structure satisfies the following condition a), the device is not broken by the snappy recovery operation and Vsnap-off≤1200V is satisfied.

FIG. 51illustrates the impurity profile after annealing the second buffer layer15bhaving the second structure. InFIG. 51, a horizontal axis indicates a depth (×10−6μm), and a vertical axis indicates an n-type impurity concentration (cm−3). An impurity profile in a case where there is one condition of acceleration energy at a time of introducing the protons (H+) into Si is indicated by a dotted line, an impurity profile in a case where there are two conditions of acceleration energy is indicated by an alternate long and short dash line, and an ideal impurity profile is indicated by a solid line. A sign provided to a peak of a solid line L56indicates each of sub-buffer layers15b1to15b4of the second buffer layer15b.

FIG. 51shows that in the case where there is one or two condition of acceleration energy, a donor layer is not formed in an area through which the protons (H+) have passed, and the n-type impurity concentration decreases. This area in which the n-type impurity concentration decreases is referred to as a P layer37. The P layer37has a low concentration equal to or lower than the impurity concentration Cdof the N−drift layer14and is high in crystal defect, thereby becoming the lifetime killer which reduces the lifetime of the carrier. When the N buffer layer15includes such a P layer37, the N buffer layer15cannot form the remaining carrier plasma layer in the side of the collector in the IGBT or in the side of the cathode in the diode. Moreover, since the area which causes the reduction in lifetime is locally included, the suppression in snap-off phenomenon and surge voltage in the turn-off operation and the reduction in leakage current in the turn-off operation cannot be achieved. The P layer37has a negative influence, on the device performance, that the ON voltage increases and the variation of the characteristics of the device increases. Thus, the second buffer layer15bneeds to be formed in the N buffer layer15without forming the P layer37having the low concentration equal to or lower than the impurity concentration Ndof the N−drift layer14. As described above, in the second buffer layer15b, the complex defect formed at the time of introducing the protons (H+) into Si is combined with hydrogen, and the donor layer is thereby formed by the mechanism of enhancing the thermal donor phenomenon. Accordingly, at the time of introducing the protons (H+) into Si, the acceleration energy needs to be changed so that the distances between the peak positions of the impurity concentration (ΔSb1,b2, ΔSb2,b3, . . . , ΔSb(n-1),bn) is set equal to each other or an implantation angle needs to be changed while keeping the acceleration energy constant, in order to prevent the formation of P layer37in the area through which the protons pass, which is caused by supplying hydrogen to be combined with the complex defect. The term “the distances between the peak points are equal to each other” described herein includes not only the case where the distances are exactly equal but also the case where the distances are equal to each other within the range of half-value width of each sub-buffer layer (2 μm).

The first buffer layer15aand the first sub-buffer layer15b1, which is in contact with the first buffer layer15ain the second buffer layer15b, have a small difference of the depth which becomes the peak concentration of each of them. This feature is based on standpoints of stabilizing each other's impurity profile and suppressing the formation of the P layer37, which is high in crystal defect, in the area through which the protons (H+) at the time of forming the first sub-buffer layer15b1. The distance between the peak positions of the impurity concentration in the first buffer layer15aand the first sub-buffer layer15b1(ΔSa,b1) needs to be smaller than the distance between the peak positions of the impurity concentration in each of the adjacent sub-buffers15b1to15bnin the second buffer layer15b(ΔSb1,b2, ΔSb2,b3, . . . , ΔSb(n-1),bn).

The impurity profile after activating the sub-buffer layers15b1to15bnconstituting the second buffer layer15bhas a feature of trailing in a direction from the first main surface toward the second main surface, that is to say, in a direction of the P collector layer16in the case of the IGBT and in a direction of the N+cathode layer17or the P cathode layer18in the case of the diode. Since such an impurity profile is formed, the extension speed of the depletion layer extending from the main junction toward the P collector layer16and the N+cathode layer17or the P cathode layer18in the device operation can be decreased in each of the sub-buffer layers15b1to15bn. Accordingly, the extension of the depletion layer as well as the remaining carrier plasma layer is controlled in the dynamic operation of the device, the controllability of the electrical field intensity in the dynamic operation is enhanced as illustrated inFIG. 45, and the controllability of the turn-off operation and the enhancement in ruggedness are achieved. The N buffer layer15needs to satisfy the following conditions b) to d) to achieve them.

b) ΔSb1,b2=ΔSb2,b3. . . =ΔSb(n-1),bnis satisfied in each of the sub-buffer layers15b1to15bnconstituting the second buffer layer15b.

c) ΔSa,b1<ΔSb1,b2is satisfied between the first buffer layer15aand the second buffer layer15b.

d) According toFIG. 33andFIG. 50, the impurity profile of each of the sub-buffer layers15b1to15bnconstituting the second buffer layer15bis the impurity profile trailing in the direction of the P collector layer16in the case of the IGBT and in the direction of the N+cathode layer17or the P cathode layer18in the case of the diode.

e) The condition d) is applied to the impurity profile of two or more sub-buffer layers15b2to15bnlocated at a side of the main junction of at least the second sub-buffer layer15b2or the subsequent second sub-buffer layer.

According toFIG. 50andFIG. 51, the second structure of the present invention needs to satisfy the conditions a) to e) described above in addition to the structure parameter of the second buffer layer15bto satisfy the various performances of the diode illustrated inFIGS. 42 to 44 and 47.

As described above, the first structure and the second structure which are the N buffer layer15of the present invention having the feature of the impurity profile illustrated inFIG. 33achieves the balanced diode which satisfies the various performances by setting the structure parameter of the second buffer layer15billustrated inFIGS. 42 to 44 and 47and additionally satisfying the conditions a) to e) described above in the second structure. Moreover, the first structure and the second structure indicate the effect of expanding the range of the safe operating temperature due to the action of suppressing the enormous tail current in the snappy recovery operation of the diode compared with the conventional structure1.

Described in the embodiment 2 is a result of the diode performance at a time of applying the various structure parameters and the conditions a) to e) described in the embodiment 1 to the N buffer layer15of the RFC diode illustrated inFIG. 32(FIG. 52toFIG. 60).

FIGS. 52 to 54illustrate an N buffer layer15dependence in the snappy recovery operation of the RFC diode of withstand voltage 1200V class. The waveform in the snappy recovery operation at the temperature of −20° C. is as illustrated inFIG. 49.FIGS. 52 and 53illustrate relationships between an operation temperature of VCC=1000V and Vsnap-offand QRR, respectively.FIG. 54illustrates a relationship between QRRand VCCat the temperature of −20° C. InFIGS. 52 to 54, the characteristics of the first structure are plotted with black triangles, the characteristics of the second structure are plotted with black circles, and each plotted point is connected by solid line L54and L55. The characteristics of the conventional structure1are plotted with white circles, and each plotted point is connected by a dotted line L56. A cross mark indicates a point at which the device has been broken.

FIGS. 52 and 53show that the device is broken at the temperature of −20° C. in the conventional structure1, however, the operation is normally operated even at a temperature of −60° C. in the first structure and the second structure. When the conventional structure1is broken at the temperature of −20° C., the characteristic recovery operation indicating the enormous value of QRRis performed, and the enormous tail current occurs in the last half of recovery operation as illustrated inFIG. 49.

As illustrated inFIG. 54, QRRis largely dependent on VCCin the conventional structure1. That is to say, it is considered that in the conventional structure1, the PNP transistor area32easily operates when VCCis high in the conventional structure1, and the device is thereby broken. In contrast, QRRis little dependent on VCCin the first structure and the second structure. That is to say, the first structure and the second structure have an effect of suppressing the operation of the PNP transistor area32in a condition where the value of VCCis high. As described above, the first structure and the second structure have a feature that the safe operating temperature in the snappy recovery operation is expanded by the effect of suppressing the operation of the PNP transistor area32.

Accordingly,FIGS. 53 and 54indicate that it is one barometer to cause the dependence of QRRon the operation temperature and VCCto be as small as possible so that the range of the snappy recovery operation temperature in the RFC diode is expanded to an extent of lower temperature and the SOA (Safe Operating Area) in the snappy recovery mode is improved.

FIG. 55illustrates characteristics of a leakage current density JR-to-reverse bias voltage VRat a temperature of 175° C. in a RFC diode of withstand voltage 4500V class. InFIG. 55, a horizontal axis indicates the reverse bias voltage VR(V), and a vertical axis indicates the leakage current density JR(A/cm2). InFIG. 55, a dotted line L57, an alternate long and short dash line L58, and a solid line L59indicate characteristics of the conventional structure1, the conventional structure2, and the second structure, respectively.

FIG. 56illustrates a relationship between a leakage current density JR(A/cm2) and an operation temperature (° C.) in a case where a reverse bias voltage VRis 4500V, and a dotted line L60, an alternate long and short dash line L61, and a solid line L62indicate characteristics of the conventional structure1, the conventional structure2, and the second structure, respectively. JRin a case where the operation temperature inFIG. 56is 175° C. coincides with JRin a case of VR=4500 inFIG. 55.

According toFIG. 55, in the conventional structure1, the voltage cannot be held due to a heat generation in the device itself when VRis approximately 2500V, and a thermal runaway indicated in an area A33occurs. In contrast, in the second structure, an amplification factor αpnpof the PNP transistor area32included in the RFC diode decreases and the leakage current at the time of turn-off is reduced, so that the turn-off loss expressed by VR×JRcan be reduced, and the amount of heat generation in the chip itself at the time of turn-off can be reduced. Accordingly, the thermal runaway does not occur in the second structure, differing from the conventional structure1, and the second structure has the voltage holding capacity in the turn-off state even at the temperature of 175° C.

Furthermore,FIG. 56shows that the leakage current at the time of turn-off is smaller in the second structure than in the conventional structure1, so that the turn-off loss is reduced. That is to say, the second structure suppresses the amount of heat generation of power semiconductor itself, thereby having an effect of suppressing the heat generation from an aspect of thermal design of the power module including the power semiconductor.

FIGS. 57 to 60illustrate a dependence of the N buffer layer15in the snappy recovery operation of the RFC diode of withstand voltage 4500V class.FIG. 57illustrates a recovery waveform at the temperature of −20° C., and the other switching conditions are VCC=3600V, JF=0.1JA, dj/dt=580 A/cm2μs, dV/dt=32000V/μs, and Ls=2.0 μH. A horizontal axis inFIG. 57indicates a time (×10−6seconds), and a vertical axis indicates an anode-to-cathode voltage VAK(V) and an anode current density JA(A/cm2). VAKin the conventional structure1is illustrated by a thin solid line L63, and JAis illustrated by a thin dotted-line L64. VAKin the conventional structure2is illustrated by a solid line L65having a moderate thickness, and JAis illustrated by a dotted-line L66having a moderate thickness. VAKin the second structure is illustrated by a thick solid line L67, and JAis illustrated by a thick dotted-line L68.

FIG. 57shows that in the conventional structure1and the conventional structure2, the enormous tail current occurs in the last half of recovery operation, and particularly in the conventional structure1, the device is broken during the recovery operation. In contrast,FIG. 57shows that in the second structure, the enormous tail current is also suppressed and blocked in the diode of withstand voltage 4500V class in a manner similar to the diode of withstand voltage 1200V class illustrated inFIG. 44.

FIG. 58illustrates a relationship between Vsnap-offand VCCat the temperature of 25° C. InFIG. 58, a horizontal axis indicates VCC(V), and a vertical axis indicates Vsnap-off(V).FIG. 59illustrates a relationship between QRRand VCCat the temperature of 25° C. InFIG. 59, a horizontal axis indicates VCC(V), and a vertical axis indicates QRR(×10−6C/cm2).FIG. 60illustrates a relationship between QRRand an operation temperature in a case of VCC=3600V. InFIG. 60, a horizontal axis indicates an operation temperature (° C.), and a vertical axis indicates QRR(×10−6C/cm2). A cross mark inFIG. 60indicates a point at which the device has been broken. InFIG. 58toFIG. 60, white circles and a dotted line L69indicate the characteristics of the conventional structure1, white triangles and a dotted line L70indicate the characteristics of the conventional structure2, and black circles and a solid line L71indicate the characteristics of the second structure.

FIGS. 58 and 59show that although Vsnap-offis low, QRRis largely dependent on VCCin the conventional structures1and2compared with the second structure. As illustrated inFIG. 60, in the conventional structure1, QRRincreases with a reduction in operation temperature, and the device is broken at the temperature of −20° C. The dependence of QRRon the operation temperature and VCCis preferably as small as possible in view of expanding the range of the operation temperature in the snappy recovery operation, including the result of the RFC diode of withstand voltage 1200V class. The first structure and the second structure, which constitute the N buffer layer15of the present invention, perform behavior to be targeted.

As described above, the first structure and the second structure of the present invention suppress the operation of the PNP transistor area32constituting the RFC diode in the recovery operation while holding the effect of suppressing the snap-off phenomenon at the end of the recovery operation, which is the characteristic of the RFC diode descried above, and the subsequent oscillation phenomenon, whereby achieving the reduction in QRRto guarantee the balanced operation of the RFC diode. As a result, the safe operating temperature in the snappy recovery operation is expanded, that is to say, the SOA in the snappy recovery mode is expanded to improve the ruggedness.

Described in the embodiment 3 is a result of the diode performance at the time of applying the various structure parameters and the conditions a) to e) described in the embodiment 1 to the N buffer layer15of the PIN diode illustrated inFIG. 31(FIG. 61toFIG. 63).

The evaluation device whose diode performance is illustrated inFIG. 61toFIG. 63is a PIN diode of withstand voltage 4500V class.FIG. 61toFIG. 63also illustrates the diode performance of the conventional structures1and2for comparison, and the impurity profiles of the conventional structures1and2are already illustrated inFIG. 33. A cross mark inFIG. 61toFIG. 63indicates a point at which the device has been broken.

FIG. 61illustrates a snappy recovery waveform of the PIN diode at a temperature of 25° C. in the PIN diode of withstand voltage 4500V class. The other switching conditions are VCC=3600V, JF=0.1 JA, dj/dt=280 A/cm2μs, dV/dt=23000V/μs, and Ls=2.0 μH. A horizontal axis inFIG. 61indicates a time (×10−6seconds), and a vertical axis indicates an anode-to-cathode voltage VAK(V) and an anode current density JA(A/cm2). VAKin the conventional structure1is illustrated by a thin solid line L72, and JAis illustrated by a thin dotted-line L73. VAKin the conventional structure2is illustrated by a solid line L74having a moderate thickness, and JAis illustrated by a dotted-line L75having a moderate thickness. VAKin the second structure is illustrated by a thick solid line L76, and JAis illustrated by a thick dotted-line L77.

Since the remaining carrier plasma layer is easily depleted in the side of the cathode of the N buffer layer15in the last half of recovery operation in the PIN diode compared with the RFC diode, the PIN diode has a small effect of suppressing the snap-off phenomenon in the recovery operation. As a result, as illustrated inFIG. 61, the snap-off phenomenon occurs in the conventional structures1and2, and particularly in the structure of the conventional structure1, the device is broken after the snap-off phenomenon. However, in the PIN diode using the second structure, the extension speed of the depletion layer extending from the main junction in the recovery operation decreases in the second buffer layer15bunder the influence of the remaining carrier plasma layer in the vicinity of the junction between the N−drift layer14and the nthsub-buffer layer15bn, so that even when the snap-off phenomenon occurs, Vsnap-offis made small compared with the conventional structure. That is to say, as indicated in the area A11′ inFIG. 35and the area A12′ inFIG. 37, in the second structure, the carrier plasma layer included in the second buffer layer15bin the ON state still remains in the recovery operation, thereby controlling the electrical field intensity distribution and delaying a snap-off point, and as a result, the breakage of the device can be avoided.

FIG. 62illustrates a relationship between Vsnap-offand VCCat the temperature of 25° C. InFIG. 62, a horizontal axis indicates VCC(V), and a vertical axis indicates Vsnap-off(V).FIG. 63illustrates a relationship between QRRand VCCat the temperature of 25° C. InFIG. 63, a horizontal axis indicates VCC(V), and a vertical axis indicates QRR(×10−6/cm2). InFIG. 62andFIG. 63, white circles and a dotted line L78indicate the characteristics of the conventional structure1, white triangles and a dotted line L79indicate the characteristics of the conventional structure2, and black circles and a solid line L80indicate the characteristics of the second structure.

FIG. 62shows that the adoption of the second structure also in the PIN diode avoids the breakage of the device even at the voltage at which the device is broken in the conventional structure, whereby the ruggedness in the snappy recovery operation is improved.FIG. 62further shows that the N buffer layer15having the second structure has the low dependence of Vsnap-offon VCCcompared with the conventional structures1and2, and is most effective in increasing the ruggedness at the side of VCC.

FIG. 63shows that the second structure has the lower dependence of QRRon VCCthan the conventional structures1and2. Accordingly, the ruggedness of the PIN diode in the snappy recovery operation is improved in the second structure. As described above, the first structure and the second structure of the present invention also have the effect of improving the ruggedness in the PIN diode.

Described in the embodiment 4 is a result of the IGBT performance at a time of applying the various structure parameters and the conditions a) to e) described in the embodiment 1 to the N buffer layer15of the IGBT having the trench-gate structure illustrated inFIG. 30(FIG. 64toFIG. 71).

FIG. 64toFIG. 71illustrate the performance of the IGBT of withstand voltage 6500V class. Parameters of each layer except for the N buffer layer15of the IGBT are as follows.

In the P base layer9, the peak impurity concentration is set to 1.0×1016to 1.0×1018cm−3, and its depth is set deeper than the N+emitter layer7and shallower than the N layer11.

In the N layer11, the peak impurity concentration is set to 1.0×1015to 1.0×1017cm−3, and its depth is set deeper than the P base layer9by 0.5 to 1.0 μm.

In the N+emitter layer7, the peak impurity concentration is set to 1.0×1018to 1.0×1021cm−3, and its depth is set to 0.2 to 1.0 μm.

In the P+layers8, the surface impurity concentration is set to 1.0×1018to 1.0×1021cm−3, and its depth is set equal to or deeper than that of the N+emitter layer7.

In the P collector layer16, the surface impurity concentration is set to 1.0×1016to 1.0×1020cm−3, and its depth is set to 0.3 to 0.8 μm.

FIGS. 64 to 66illustrate a turn-off operation waveform in an inductive load state of the IGBT of withstand voltage 6500V class.FIG. 64illustrates the turn-off operation under the high VCCcondition of VCC=4600V,FIG. 65illustrates the turn-off operation waveform under the high LS condition of LS=5.8 μH, andFIG. 66illustrates the turn-off operation waveform under the low temperature condition of −60° C. In each ofFIG. 64toFIG. 66, a horizontal axis indicates a time (×10−6seconds), and a vertical axis indicates a collector-to-emitter voltage VCE(V) and a collector current density JC(A/cm2). In each ofFIG. 64toFIG. 66, VCEin the conventional structure1is illustrated by a thin solid line L81, and JCis illustrated by a thin dotted-line L82. VCEin the second structure is illustrated by a thick solid line L83, and JCis illustrated by a thick dotted-line L84.

As indicated in areas A34,35, and36inFIG. 64toFIG. 66, the snap-off phenomenon occurs in the conventional structure1. VCE(surge) inFIG. 64indicates a maximum VCEvalue at a time of surge phenomenon or the snap-off phenomenon in the turn-off operation. The ON voltages VCE(sat) of the conventional structure1and the second structure in the same graph are substantially equal to each other.FIG. 64toFIG. 66show that in the second structure, djC/dt at the end of the turn-off operation is reduced even under a strict circuit condition for the turn-off operation of the IGBT, and as a result, the snap-off phenomenon is suppressed. In case of a condition inFIG. 65, for example, djC/dt at the end of the actual turn-off operation is 3.49×107A/cm2sec in the conventional structure1, but is smaller in the second structure, that is, 1.40×107A/cm2sec.

FIG. 67illustrates a relationship between VCE(surge) and VCE(sat) in the conventional structures1and2and the second structure. A horizontal axis indicates VCE(sat), and a vertical axis indicates VCE(surge). The other inductive load turn-off switching conditions are JC=41.2 A/cm2, VG=15V, a temperature of 25° C., VCC=4600V, and LS=2.8 μH. InFIG. 67, characteristics of the conventional structure1are plotted with white circles, characteristics of the conventional structure2are plotted with white triangles, and characteristics of the second structure are plotted with black circles.

InFIG. 67, an increase in VCE(sat) in the horizontal axis means a reduction in concentration of the P collector layer16in the IGBT ofFIG. 30. That is to say, the concentration of the carrier plasma layer at the side of the collector decreases at the time of the turn-off operation of the IGBT in a direction which VCE(sat) in the horizontal axis increases, so that VCE(surge) at the time of turn-off increases, and the snap-off phenomenon thereby easily occurs. According toFIG. 67, there is a tendency in the second structure that the value of VCE(surge) is small in relation to the same value of VCE(sat) compared to the conventional structures1and2. Furthermore, the second structure has the smaller dependence of VCE(surge) on VCE(sat) than the conventional structure1. That is to say, in the second structure, there is the remaining carrier plasma layer as indicated in an area A12′ ofFIG. 37even when the concentration of the carrier plasma layer at the side of the collector decreases in the turn-off operation of the IGBT, so that the effect of suppressing the increase in VCE(surge) and the snap-off phenomenon can be obtained.

FIG. 68illustrates a relationship between a collector-to-emitter leakage current density JCESand a collector-to-emitter voltage VCESat a temperature of 150° C. in the conventional structures1and2and the second structure. ON voltages of three samples compared inFIG. 68are substantially equal to each other. InFIG. 68, a horizontal axis indicates VCES(V), and a vertical axis indicates VCES(A/cm2). A dotted line L85, an alternate long and short dash line L86, and a solid line L87indicate characteristics of the conventional structure1, the conventional structure2, and the second structure, respectively.

FIG. 68shows that in the second structure, the leakage current JCESat the time of turn-off decreases compared with the conventional structure1. The reason is that the amplification factor αpnp of the PNP transistor included in the IGBT decreases in the second structure. Accordingly, the turn-off loss is reduced in the second structure, and the amount of heat generation in the chip itself at the time of turn-off can be reduced.

FIG. 69illustrates a relationship between a short-circuit energy ESCand an operation temperature in a state of no-load short-circuit in the conventional structures1and2and the second structure. However, with regard to the second structure, indicated are characteristics of two cases of (Cb,p) max≤1.0×1015cm−3and (Cb,p) max>1.0×1015cm−3. The former is plotted with black circles and connected by a solid line L88, and the latter is plotted with white circles and connected by a solid line L89. The characteristics of the conventional structure1are plotted by white circles and the white circles are connected by a dotted line L90, and the characteristics of the conventional structure2are plotted by white triangles and the white triangles are connected by a dotted line L91.

FIG. 69shows that the value of ESCis the largest in the case of (Cb,p) max≤1.0×1015cm−3in the second structure compared with the conventional structures1and2. However,FIG. 69also shows that even in the second structure, the blocking capability in the short-circuit state extremely decreases in the case of (Cb,p) max>1.0×1015cm−3, so that the short-circuit characteristics of the IGBT is not guaranteed. As described above, (Cb,p) max has an influence on the blocking capability in the short-circuit state in the second structure.

A mechanism of this influence is clarified from a turn-off operation waveform illustrated inFIG. 70.FIG. 70illustrates a turn-off operation waveform in a state of no-load short-circuit in an IGBT of withstand voltage 6500V class having the trench-gate structure in a simulation at a temperature of 125° C. InFIG. 70, a horizontal axis indicates a time (×10−6/second), and a vertical axis indicates VCE(V) and JC(A/cm2). InFIG. 70, a solid line L92indicates VCE, and an alternate long and short dash line L93indicates JC.

FIG. 71illustrates a carrier concentration distribution inside of the device in an analysis point AP2illustrated inFIG. 70. A horizontal axis inFIG. 71indicates a normalized depth, and 0 and 1.0 correspond to marks A and B inFIG. 30, respectively. InFIG. 30, the mark A indicates a surface of the MOS transistor part, and the mark B indicates a surface of the P collector layer16. InFIG. 71, the vertical axis indicates the carrier concentration (cm−3) and the electrical field intensity (×103V/cm). InFIG. 71, a thin solid line L94indicates the electron concentration, a thick solid line L95indicates a hole concentration, and a solid line L96having a moderate thickness indicates the electrical field intensity, in the case of (Cb,p) max≤1.0×1015cm−3, respectively. A thin dotted line L97indicates the electron concentration, a thick dotted line L98indicates a hole concentration, and a dotted line L99having a moderate thickness indicates the electrical field intensity, in the case of (Cb,p) max>1.0×1015cm−3, respectively.

FIG. 71shows that in a condition where the maximum peak impurity concentration of the second buffer layer is high, that is, (Cb,p) max>1.0×1015cm−3, the electrical field intensity inside of the device in the short-circuit state indicates a distinctive distribution that it is not high in the main junction, that is to say, the junction between the P base layer9and the N−drift layer14but is high in the junction (Xj,a) between the first buffer layer15aand the second buffer layer15b, so that the unbalance of the electrical field intensity occurs. This is caused by the reduction in the concentration of the remaining carrier plasma layer in the second buffer layer15b. The reduction in the concentration of the remaining carrier plasma layer in the second buffer layer15balso means that the second buffer layer15bcannot perform the function indicated by the area A12′ inFIG. 37.

When the unbalance of the electrical field intensity occurs, an area where heat is generated locally occurs in the vicinity of the junction between the N−drift layer14and the N buffer layer15or in the N buffer layer15, so that the IGBT is broken by heat and the blocking capability in the short-circuit state extremely decreases. That is to say, such an inner state of the device causes the extreme reduction in the blocking capability in the short-circuit state illustrated inFIG. 69.

As described above, the IGBT including the N buffer layer15having the feature of the impurity profile illustrated inFIG. 33achieves the stable withstand voltage characteristics, the reduction in the turn-off loss caused by the low leakage current at the time of turn-off, the improvement in the controllability of the turn-off operation, and the significant improvement in the blocking capability at the time of turn-off in a no-load state. Furthermore, the IGBT including the N buffer layer15has a feature that the impurity which forms the n-type diffusion layer is diffused not only in the depth direction but also in the horizontal direction at the time of forming the second buffer layer15bin the N buffer layer15of the present invention. As a result, the IGBT including the N buffer layer15has the effect that a partial un-formation area of the N buffer layer15which causes the feature at the time of forming the N buffer layer15and the negative influence during the wafer process is not generated, so that the increase in the level of defectiveness of the IGBT and the diode chip is suppressed.

The embodiment 4 describes the example of application of the present invention to the IGBT illustrated inFIG. 30. However, the present invention can be also applied to an IGBT in which the dummy electrode is not included, but all of the gate electrodes13are the gate potentials (for example, FIG. 66 in Japanese Patent No. 5908524), an IGBT which does not include the N layer11in the diffusion layer between the adjacent gate electrodes13(for example, FIG. 1 in Japanese Patent No. 5908524), and an IGBT in which the gate structure of the MOS transistor part has the planar gate structure (for example, FIGS. 79 to 52 in Japanese Patent No. 5908524), thus the similar effect can be obtained.

The semiconductor device according to the embodiment 5 has an object of further improving the blocking capability at the time of turn-off in the IGBT and the diode in accordance with the relationship between the constituent elements of the power semiconductor illustrated inFIG. 4and the characteristic N buffer layer15described in the embodiment 1 to the embodiment 4.

FIG. 72toFIG. 83are cross-sectional views illustrating a first to twelfth aspects in the semiconductor device according to the embodiment 5. These cross sections correspond to the cross section A1-A1inFIG. 4. The first, second, ninth, and eleventh aspects are improvements of the IGBT (FIG. 1andFIG. 30), the third aspect is an improvement of the PIN diode (FIG. 2andFIG. 31), and the fourth to eighth, tenth, and twelfth aspects are improvements of the RFC diode (FIG. 3andFIG. 32).

Hereinafter, the same reference numerals as those inFIG. 1toFIG. 3andFIG. 30toFIG. 32will be assigned to the same structural parts and the description thereof will be omitted as appropriate, and the characteristic portions will be mainly described.

The first aspect illustrated inFIG. 72is characterized by extendedly forming the N buffer layer15in the area where the P collector layer16is not formed, without forming the P collector layer16in the interface area R2and the edge termination area R3which are the peripheral areas of the active cell area R1, as compared to the IGBT illustrated inFIG. 1andFIG. 30. That is to say, in the interface area R2and the edge termination area R3, the collector electrode23C is joined to the N buffer layer15and provided on the N buffer layer15.

The second aspect illustrated inFIG. 73is characterized by forming the P collector layer16ewithout forming the P collector layer16in the interface area R2and the edge termination area R3which are the peripheral areas of the active cell area R1, as compared to the IGBT illustrated inFIG. 1andFIG. 30. A surface concentration of the P collector layer16eis lower than the concentration of the P collector layer16.

The third aspect illustrated inFIG. 74is characterized by extendedly forming the N buffer layer15in the area where the P collector layer16is not formed, without forming the N+cathode layer17in the interface area R2and the edge termination area R3which are the peripheral areas, as compared to the PIN diode illustrated inFIG. 2andFIG. 31. That is to say, in the interface area R2and the edge termination area R3, the cathode electrode23K is joined to the N buffer layer15and provided on the N buffer layer15.

The fourth aspect illustrated inFIG. 75is characterized by forming the P cathode layer18(a second partial active layer) without forming the N+cathode layer17(a first partial active layer) in the interface area R2and the edge termination area R3which are the peripheral areas, as compared to the RFC diode illustrated inFIG. 3andFIG. 32.

The fifth aspect illustrated inFIG. 76is characterized by extendedly forming the N buffer layer15in the area where the P cathode layer18is not formed, without forming the P cathode layer18in the interface area R2and the edge termination area R3which are the peripheral areas, as compared to the RFC diode illustrated inFIG. 3andFIG. 32. That is to say, in the interface area R2and the edge termination area R3, the cathode electrode23K is joined to the N buffer layer15and provided on the N buffer layer15.

The sixth aspect illustrated inFIG. 77is characterized by forming the N+cathode layer17(the first partial active layer) without forming the P cathode layer18(the second partial active layer) in the interface area R2and the edge termination area R3which are the peripheral areas, as compared to the RFC diode illustrated inFIG. 3andFIG. 32.

The seventh aspect illustrated inFIG. 78is characterized by forming the N+cathode layer17(the first partial active layer) instead of the P cathode layer18of the interface area R2as compared to the RFC diode of the fourth aspect illustrated inFIG. 75.

The eighth aspect illustrated inFIG. 79is characterized by forming the P cathode layer18(the second partial active layer) across the interface area R2and the edge termination area R3as compared to the PIN diode illustrated inFIG. 2andFIG. 31.

The ninth aspect illustrated inFIG. 80is characterized by forming a P area22bconnected to the P area22and a plurality of P areas22cin a floating state on the side of the first main surface in the N−drift layer14in the edge termination area R3as compared to the IGBT illustrated inFIG. 72.

The tenth aspect illustrated inFIG. 81is characterized by forming the P area22bconnected to the P area22and the plurality of P areas22cin the floating state on the side of the first main surface in the N−drift layer14in the edge termination area R3as compared to the RFC diode illustrated inFIG. 75.

The eleventh aspect illustrated inFIG. 82is characterized by causing the plurality of P areas22c, which is not in the floating state, to be in contact with the passivation film20as compared to the IGBT illustrated inFIG. 80.

The twelfth aspect illustrated inFIG. 83is characterized by causing the plurality of P areas22c, which is not in the floating state, to be in contact with the passivation film20as compared to the RFC diode illustrated inFIG. 81. The feature of the structure of the edge termination area R3inFIGS. 80 to 83and the effect thereof are described in International Publication No. 2015/114748 and Japanese Patent Application No. 2015-230229.

As described above, the first to tenth aspects of the embodiment 5 are characterized by changing, in the IGBT, the PIN diode, and the RFC diode, a structure of an area corresponding to the active layer which is in contact with the collector electrode23C or the cathode electrode23K in the active cell area R1, the interface area R2, and the edge termination area R3.

Thus, the IGBT, the PIN diode, and the RFC diode according to the first to tenth aspects have a structure for suppressing the carrier implantation from the collector or the cathode in the inter face area R2and the edge termination area R3under an ON state.

As a result, the first to tenth aspects in the embodiment 3 has effects of reducing the electrical field intensity of a p-n junction which is the main junction in the interface area R2in the turn-off operation, suppressing the increase in the local electrical field intensity, and suppressing thermal breakdown (thermal breakdown suppressing effect) caused by a local increase in temperature subject to the current concentration induced by the impact ionization.

A mechanism of this phenomenon and a detail of the effect are described in Japanese Patent No. 5708803, Japanese Patent No. 5701447, and International Publication No. 2015/114747 for the IGBT, and described in Japanese Patent Application Laid-Open No. 2014-241433 for the diode.

FIG. 84illustrates a RBSOA (Reverse Bias Safe Operating Area) of the IGBT according to the second aspect illustrated inFIG. 73in the withstand voltage 3300V class. InFIG. 84, a horizontal axis indicates a power supply voltage VCC(V) and a vertical axis indicates the maximum blocking current density JC(break) (A/cm2) at the time of turn off. Solid lines L100and101inFIG. 84indicate characteristics in a case of adopting the N buffer layer15(the second structure) of the impurity profile illustrated inFIG. 33, and a dotted line L102indicates characteristics in a case of adopting the conventional N buffer layer (the conventional structure1). Black circles and the solid line L100indicate characteristics of the second structure at a temperature of 150° C., and black triangles and the solid line L101indicate characteristics of the second structure at a temperature of 175° C. An inner side of graph lines illustrated inFIG. 84indicates the safety operating area (SOA).

FIG. 84shows that in a case where the N buffer layer15has the second structure in the IGBT of the second aspect, the RBSOA expands to a side where JC(break) and VCCare higher compared with a case where the N buffer layer15has the conventional structure1. That is to say, the second structure significantly improves the RBSOA of the IGBT.

FIG. 85illustrates a recovery SOA of the RFC diode of the fourth aspect illustrated inFIG. 75in the withstand voltage 6500V class. InFIG. 85, a horizontal axis indicates VCC(V), and a vertical axis indicates max. dj/dt, which is a maximum blocking dj/dt, and a maximum power density, in the recovery operation. In characteristics in the case where the N buffer layer15has the conventional structure1, max. dj/dt is plotted with white triangles, and the maximum power density is plotted with black triangles. In characteristics in the case where the N buffer layer15has the second structure, max. dj/dt is indicated by white circles and a solid line L103, and the maximum power density is indicated by black circles and a solid line L104.

An inner side of graph lines illustrated inFIG. 85indicates the SOA.FIG. 85shows that the RFC diode of the fourth aspect having the N buffer layer15having the second structure of the present invention has the recovery SOA expanding to a side where both max. dj/dt and the maximum power density of the recovery SOA are higher compared with the RFC diode having the N buffer layer of the conventional structure1. That is to say, the second structure significantly improves the recovery SOA of the RFC diode.

FIGS. 84 and 85show that the first structure or the second structure is adopted to the N buffer layer15in the IGBT in the first aspect of the embodiment 3 and the RFC diode in the fourth aspect of the embodiment 3, thereby significantly expanding the SOA at the time of turn-off compared with the conventional structure, and achieving the significant improvement in the blocking capability at the time of turn-off, which is one of the objects of the present invention. The effect similar to that indicated byFIG. 84andFIG. 85can be obtained by adopting the first structure or the second structure to the N buffer layer15in the IGBT and the diode in the other aspect of the embodiment 3. Moreover, also in the edge termination area R3illustrated inFIG. 80toFIG. 83, the vertical structure of contacting the electrode23in the edge termination area R3from the active cell area R1and the interface area R2is the same as that ofFIG. 72orFIG. 75, thus, with regard to the SOA at the time of turn-off in the IGBT or the diode, the effect similar to that indicated byFIG. 84andFIG. 85can be obtained by applying the first structure or the second structure to the N buffer layer15.

The present embodiment describes a method of stably manufacturing the impurity profile of the N buffer layer15in the first structure or the second structure described in the embodiment 1, particularly the impurity profile of the second buffer layer15b.

FIG. 86illustrates processes A to E considered as steps of manufacturing the IGBT, the PIN diode, and the RFC diode described in the embodiments 1 to 5. Indicated in a first column of a table inFIG. 86are step of the formation of the protective film on the surface of the wafer, the thickness control of the wafer, the second buffer layer (the introduction of the protons), the second buffer layer (the annealing), the first buffer layer (the introduction of the protons, the annealing), the second buffer layer (the introduction of the protons), the formation of the active layer, the second buffer layer (the introduction of the protons), the second buffer layer (the annealing), the formation of the collector electrode or cathode electrode, and the second buffer layer (the introduction of the protons, the annealing). These are typical steps supposed in the steps illustrated inFIG. 16andFIG. 17in the steps of manufacturing the IGBT illustrated inFIG. 5toFIG. 17or the steps illustrated inFIG. 25orFIG. 26in the steps of manufacturing the diode illustrated inFIG. 18toFIG. 26, and these steps are performed in order from the upper row to the lower row. A step on which “∘” is marked inFIG. 86is performed at a time of experimentally manufacturing a sample in each of the processes A to E. The term of “the second buffer layer (the introduction of the protons)” indicates the step of introducing the protons for forming the second buffer layer, and the term of “the second buffer layer (the annealing)” indicates the step of activating the protons introduced for forming the second buffer layer by the annealing.

That is to say, in the process A, the formation of the protective film on the surface of the wafer, the thickness control of the wafer, the formation of the first buffer layer (the introduction of the protons (the first ions), the annealing), the formation of the second buffer layer (the introduction of the protons (the second ions)), the formation of the active layer (the P collector layer16, the N+cathode layer17, and the P cathode layer18), the formation of the second buffer layer (the annealing), and the formation of the back side electrode (the collector electrode or the cathode electrode) are performed in this order.

In the process B, the formation of the protective film on the surface of the wafer, the thickness control of the wafer, the formation of the second buffer layer (the introduction of the protons (the second ions)), the formation of the first buffer layer (the introduction of the protons (the first ions), the annealing), the formation of the active layer (the P collector layer16, the N+cathode layer17, and the P cathode layer18), the formation of the second buffer layer (the annealing), and the formation of the back side electrode (the collector electrode or the cathode electrode) are performed in this order.

In the process C, the formation of the protective film on the surface of the wafer, the thickness control of the wafer, the formation of the second buffer layer (the introduction of the protons (the second ions)), the formation of the second buffer layer (the annealing), the formation of the first buffer layer (the introduction of the protons (the first ions), the annealing), the formation of the active layer (the P collector layer16, the N+cathode layer17, and the P cathode layer18), and the formation of the back side electrode (the collector electrode or the cathode electrode) are performed in this order.

In the process D, the formation of the protective film on the surface of the wafer, the thickness control of the wafer, the formation of the first buffer layer (the introduction of the protons (the first ions), the annealing), the formation of the active layer (the P collector layer16, the N+cathode layer17, and the P cathode layer18), the formation of the second buffer layer (the introduction of the protons (the second ions)), the formation of the second buffer layer (the annealing), and the formation of the back side electrode (the collector electrode or the cathode electrode) are performed in this order.

In the process E, the formation of the protective film on the surface of the wafer, the thickness control of the wafer, the formation of the first buffer layer (the introduction of the protons (the first ions), the annealing), the formation of the active layer (the P collector layer16, the N+cathode layer17, and the P cathode layer18), the formation of the back side electrode (the collector electrode or the cathode electrode), and the formation of the second buffer layer (the introduction of the protons, the annealing) are performed in this order.

FIG. 87illustrates an impurity profile of the N buffer layer15and the N−drift layer14made in the processes A to D. However, the second sub-buffer layers15b2to the nthsub-buffer layer15bnare not formed in the sample whose impurity profile is indicated inFIG. 87, and only the impurity profile of the first buffer layer15aand the first sub-buffer layer15b1of the second buffer layer15bis indicated in the N buffer layer15. InFIG. 87, a horizontal axis indicates a depth (×10−6m), and a vertical axis indicates a carrier concentration (cm−3). InFIG. 87, an alternate long and short dash line L105indicates characteristics of the process A, a solid line L106indicates characteristics of the process B, a dotted line L107indicates characteristics of the process C, and an alternate long and two short dashes line L108indicates characteristics of the process D. A number provided along the horizontal axis inFIG. 87indicates the reference numeral of the constituent element of the device.

FIG. 87shows that in the processes B and C in which the step of introducing the protons into Si is performed prior to the step of forming the first buffer layer15a, the impurity profile of the first sub-buffer layer15b1becomes unstable, and the impurity concentration of the first sub-buffer layer15b1decreases. The voids occurring in introducing the protons into Si are combined with the hydrogen atoms and the oxygen atoms, the complex defect is combined with hydrogen, and the density of the complex defect is increased by the annealing, and then, the donor layer of the protons is formed. That is to say, it is considered in the processes B and C that the complex defect formed in introducing the protons into Si is recovered at the time of the annealing in forming the first buffer layer15a, so that the function of the second buffer layer15bserving as the donor is suppressed, and the suppression leads to the reduction in the stability and concentration of the impurity profile of the first sub-buffer layer15b1.

In contrast, in the processes A and D, the step of introducing the protons into Si is performed after the step of forming the first buffer layer15a, thus the phenomenon that the complex defect formed in introducing the protons into Si is recovered, occurring in the processes B and C, does not occur. Accordingly, the function of the second buffer layer15bserving as the donor is enhanced in the annealing step for forming the second buffer layer15b, so that the stable impurity profile and the sufficient impurity concentration can be obtained in the first sub-buffer layer15b1.

FIG. 87does not illustrate the impurity profile of the N buffer layer15and the N−drift layer14in the process E. However, since the process E includes the step of introducing the protons into Si after the step of forming the first buffer layer15aas is the case with the processes A and D, the impurity profile of the first sub-buffer layer15b1is considered to be substantially the same as that of the processes A and D.

In the process E, the second buffer layer15bis formed after forming the back side electrode. Herein, when the back side electrode is made of a plurality of metals (for example, Al/Mo/Ni/Au, AlSi/Ti/Ni/Au, Ti/Ni/Au), it is also applicable to form the second buffer layer15bafter forming a metal constituting a back side metal (for example, A1, AlSi, or Ti) being in contact with the P collector layer16, N+cathode layer17, or the P cathode layer18, and subsequently form a remaining metal constituting the back side electrode (for example, Mo/Ni/Au, Ti/NI/Au, NI/Au).

Since the N buffer layer15formed in the processes B and C has the unstable and low concentration impurity profile in the first sub-buffer layer15b1, it inhibits the achievement of the effect of the present invention and causes the negative influence such as the increase in the variation of the device performance. Accordingly, the protons need to be introduced into Si after forming the first buffer layer15ato obtain the stable impurity concentration profile and the sufficient impurity concentration in each of the sub-buffer layers15b1to15bnconstituting the second buffer layer15bof the N buffer layer15. This enables the achievement of the effective effect of the N buffer layer15of the present invention described in the embodiments 1 to 4. The N buffer layer15having the first structure and the second structure of the present invention described in the embodiments 1 to 4 is made by the process A.

The semiconductor device according to the aforementioned embodiments 1 to 5 is applied to a power conversion device, in the present embodiment. Although the present invention is not limited to a specific power conversion device, described hereinafter as the embodiment 7 is a case of applying the present invention to a three-phase inverter.

FIG. 88is a block diagram illustrating a configuration of a power conversion system applying a power conversion device according to the present embodiment.

The power conversion system illustrated inFIG. 88is made up of a power source100, a power conversion device200, and a load300. The power source100, which is a direct current power source, supplies a direct current power to the power conversion device200. The power source100can be made up of various types of components such as a direct current system, a solar battery, or a rechargeable battery, or may be also made up of a rectifying circuit connected to an alternating current system or an AC/DC converter. The power source100may be also made up of a DC/DC converter which converts a direct current power being output from the direct current system into a predetermined power.

The power conversion device200, which is a three-phase inverter connected between the power source100and the load300, converts the direct current power supplied from the power source100into the alternating current power to supply the alternating current power to the load300. As illustrated inFIG. 88, the power conversion device200includes a main conversion circuit201which converts the direct current power into the alternating current power and outputs the alternating current power and a control circuit203which outputs control signals for controlling the main conversion circuit201to the main conversion circuit201.

The load300is a three-phase electrical motor driven by the alternating current power supplied from the power conversion device200. The load300is not for specific purpose of use but is the electrical motor mounted on various types of electrical devices, thus it is used as the electrical motor for a hybrid car, an electrical car, a rail vehicle, an elevator, or an air-conditioning equipment, for example.

The power conversion device200is described in detail hereinafter. The main conversion circuit201includes a switching element and a reflux diode (not shown), and when a switching is performed on the switching element, the direct current power supplied from the power source100is converted into the alternating current power and then supplied to the load300. The main conversion circuit201includes various types of specific circuit configurations, and the main conversion circuit201according to the present embodiment is a three-phase full-bridge circuit having two levels, and can be made up of six switching elements and six reflux diodes being antiparallel to each switching element. The main conversion circuit201is made up of a semiconductor module202. The semiconductor device according to any one of the aforementioned embodiments 1 to 5 is applied to at least one of each switching element and each reflux diode in the main conversion circuit201. The two switching elements among the six switching elements are series-connected to each other to constitute upper and lower arms, and each of the upper and lower arms constitutes each phase (U-phase, V-phase, and W-phase) of the full-bridge circuit. An output terminal of each of the upper and lower arms, that is to say, three output terminals of the main conversion circuit201are connected to the load300.

The main conversion circuit201includes a drive circuit (not shown) for driving each switching element. The drive circuit may be embedded in the semiconductor module202or may also be provided separately from the semiconductor module202. The drive circuit generates drive signals for driving the switching element of the main conversion circuit201, and supplies the drive signals to a control electrode of the switching element of the main conversion circuit201. Specifically, the drive circuit outputs the drive signals for switching the switching element to an ON state and the drive signals for switching the switching element to an OFF state to the control electrode of each switching element in accordance with the control signals from the control circuit203described hereinafter. The drive signals are voltage signals (ON signals) equal to or higher than a threshold voltage of the switching element when the switching element is kept in the ON state, and the drive signals are voltage signals (OFF signals) equal to or lower than the threshold voltage of the switching element when the switching element is kept in the OFF state.

The control circuit203controls the switching element of the main conversion circuit201to supply a desired power to the load300. Specifically, the control circuit203calculates a time when each switching element of the main conversion circuit201needs to enter the ON state, based on the power which needs to be supplied to the load300. For example, the main conversion circuit201can be controlled by performing PWN control for modulating an ON time of the switching element in accordance with the voltage which needs to be output. Then, the control circuit203outputs a control instruction (control signals) to the drive circuit included in the main conversion circuit201so that the drive circuit outputs the ON signals to the switching element which needs to enter the ON state and outputs the OFF signals to the switching element which needs to enter the OFF state at each time. The drive circuit outputs the ON signals or the OFF signals as the drive signals to the control electrode of each switching element in accordance with the control signals.

In the power conversion device according to the present embodiment, the semiconductor device according to the embodiments 1 to 5 is applied as the switching element and the reflux diode of the main conversion circuit201, thus it is possible to achieve the stable withstand voltage characteristics, the reduction in turn-off loss with reduction in leakage current at the time of turn-off, and improvements in controllability of the turn-off operation and blocking capability at the time of turn-off.

Although the example of applying the present invention to the three-phase inverter having the two levels is described in the present preferred embodiment, the present invention is not limited thereto, but can be applied to the various power conversion devices. Although the power conversion device having the two levels is described in the present embodiment, a power conversion device having three or multiple levels may also applied. The present invention may be applied to a single-phase inverter when the power is supplied to a single-phase load. The present invention can be also applied to a DC/DC converter or an AC/DC converter when the power is supplied to the direct current load, for example.

The power conversion device to which the present invention is applied is not limited to the case where the aforementioned load is the electrical motor, but can be used in, for example, a power source device of an electrical discharging machine, a laser processing machine, an induction heat cooking machine, or a noncontact power supply system, a power conditioner such as a solar power system or a power storage system, or a system of a driving part such as a car, a train, or a high-speed rail.

According to the present invention, the above embodiments can be arbitrarily combined, or each embodiment can be appropriately varied or omitted within the scope of the invention.