INTEGRATED CIRCUIT MEMORY DEVICES HAVING ENHANCED MEMORY CELL LAYOUTS

An integrated circuit memory device (e.g., DRAM) includes a substrate having a bit line thereon, and an electrically insulating region having a first opening therein, which exposes a first portion of the bit line. A first semiconductor active layer is provided, which lines first and second opposing sidewalls of the first opening and the exposed first portion of the bit line, such that a direct electrical connection is provided between the exposed first portion of the bit line and a portion of the first semiconductor active layer extending between the first and second sidewalls of the first opening. A first word line is provided on a first portion of the first semiconductor active layer extending opposite the first sidewall of the first opening, and a second word line is provided on a second portion of the first semiconductor active layer extending opposite the second sidewall of the first opening.

REFERENCE TO PRIORITY APPLICATION

This application claims priority under 35 U.S.C. § 119 to Korean Patent Application No. 10-2023-0086653, filed Jul. 4, 2023, the disclosure of which is hereby incorporated herein by reference.

BACKGROUND

The inventive concept relates to semiconductor devices and, more specifically, to integrated circuit memory devices.

With the continuing downscaling of semiconductor devices, the size of dynamic random access memory (DRAM) devices is also decreasing. In a DRAM device having a 1T-1C structure in which one capacitor is connected to one transistor, there is a problem in that leakage current through a channel area typically increases as the device becomes smaller. To reduce leakage current, a vertical channel transistor that uses an oxide semiconductor material as a channel layer has been proposed.

SUMMARY

The inventive concept provides a semiconductor device, such as a DRAM device, having excellent electrical performance.

According to an aspect of the inventive concept, there is provided a semiconductor device including: a bit line extending in a first horizontal direction on a substrate, and a mold structure disposed on the bit line and including a mold opening extending in a second direction perpendicular to the first horizontal direction. The mold structure may include a mold insulating layer, a cover insulating layer disposed on the mold insulating layer, and an interface insulating layer disposed on an upper surface of and on at least a portion of a sidewall of the cover insulating layer. An active semiconductor layer is also provided, and includes a first portion disposed on an inner wall of the mold opening of the mold structure and extending in a vertical direction perpendicular to an upper surface of the substrate, and a second portion connected to the bottom of the first portion and extending in the first horizontal direction. In some embodiments, the second portion is disposed on an upper surface of the bit line, and the first portion includes a first sidewall in contact with a sidewall of the mold opening and a second sidewall extending opposite to the first sidewall. A word line is also provided, and is disposed on the second sidewall of the active semiconductor layer and extends in the second horizontal direction. A gate insulating layer is provided between the active semiconductor layer and the word line, and a landing pad is provided, which extends on an upper surface of the first portion of the active semiconductor layer.

According to further embodiments, a semiconductor device is provided, which includes a bit line extending in a first horizontal direction on a substrate, a mold structure disposed on the bit and including a mold opening extending in a second direction perpendicular to the first horizontal direction, with the mold structure including a mold insulating layer, a cover insulating layer disposed on the mold insulating layer, and an interface insulating layer disposed on an upper surface of and on at least a portion of a sidewall of the cover insulating layer. An active semiconductor layer is provided, which includes a first portion disposed on an inner wall of the mold opening of the mold structure and extending in a vertical direction perpendicular to an upper surface of the substrate, and a second portion connected to the bottom of the first portion and extending in the first horizontal direction. In some embodiments, the second portion is disposed on an upper surface of the bit line, and the first portion includes a first sidewall that is in contact with a sidewall of the mold opening and a second sidewall opposite to the first sidewall. A word line is provided, which is disposed on the second sidewall of the active semiconductor layer and extends in the second horizontal direction. A gate insulating layer is provided, which is disposed between the active semiconductor layer and the word line. A landing pad is provided, which is connected to an upper surface of the first portion of the active semiconductor layer. In some embodiments, the landing pad may include an upper portion disposed on an upper surface of the mold structure and a bottom portion connected to the upper portion and disposed in a landing pad recess space, and a bottom surface of the bottom portion of the landing pad may be disposed at a same level as a bottom surface of the interface insulating layer.

According to another aspect of the inventive concept, there is provided a semiconductor device including: a bit line extending in a first horizontal direction on a substrate; a mold structure disposed on the bit line and including a mold opening extending in a second direction perpendicular to the first horizontal direction, the mold structure including a mold insulating layer, a cover insulating layer disposed on the mold insulating layer, and an interface insulating layer disposed on an upper surface of and on at least a portion of a sidewall of the cover insulating layer; an active semiconductor layer including a first portion disposed on an inner wall of the mold opening of the mold structure and extending in a vertical direction perpendicular to an upper surface of the substrate, and a second portion connected to the bottom of the first portion and extending in the first horizontal direction, wherein the second portion is disposed on an upper surface of the bit line, and the first portion includes a first sidewall that is in contact with a sidewall of the mold opening and a second sidewall opposite to the first sidewall, and the active semiconductor layer has an upper surface disposed at a lower level than an upper surface of the mold structure; a word line disposed on the second sidewall of the active semiconductor layer and extending in the second horizontal direction; a gate insulating layer disposed between the active semiconductor layer and the word line; a buried insulating layer disposed on a sidewall of the word line and filling the mold opening; a landing pad connected to an upper surface of the first portion of the active semiconductor layer, the landing pad including an upper portion disposed on the upper surface of the mold structure and a bottom portion connected to the upper portion and disposed in a landing pad recess space; and a storage node connected to the landing pad, wherein the interface insulating layer extends from the upper surface of the cover insulating layer onto a sidewall of the cover insulating layer disposed in the landing pad recess space.

According to still further embodiments of the invention, an integrated circuit memory device is provided, which includes a substrate having a bit line (BL) thereon, and an electrically insulating region having a first opening therein, which exposes a first portion of the bit line. A first semiconductor active layer is also provided, which lines first and second opposing sidewalls of the first opening and the exposed first portion of the bit line, such that a direct electrical connection is provided between the exposed first portion of the bit line and a portion of the first semiconductor active layer extending between the first and second sidewalls of the first opening. A first word line is provided on a first portion of the first semiconductor active layer extending opposite the first sidewall of the first opening, and a second word line is provided on a second portion of the first semiconductor active layer extending opposite the second sidewall of the first opening. Advantageously, a portion of the first word line extending opposite the first portion of the first semiconductor active layer operates as a gate electrode of an access transistor of a first memory cell, and a portion of the second word line extending opposite the second portion of the first semiconductor active layer operates as a gate electrode of an access transistor of a second memory cell.

DETAILED DESCRIPTION OF THE EMBODIMENTS

FIG.1is a layout diagram illustrating a semiconductor device100according to embodiments, andFIG.2is an enlarged layout diagram of a portion of a cell array area MCA ofFIG.1. In addition,FIG.3is a cross-sectional view taken along line A1-A1′ ofFIG.2,FIG.4is a cross-sectional view taken along line A2-A2′ ofFIG.2, andFIG.5is an enlarged view of portion CX1ofFIG.3.

Referring toFIGS.1to5, the semiconductor device100may include a substrate110including a cell array area MCA and a peripheral circuit area PCA. In some embodiments, the cell array area MCA may be a memory cell area of a dynamic random access memory (DRAM) device, and the peripheral circuit area PCA may be a core area or a peripheral circuit area of a DRAM device. For example, the peripheral circuit area PCA may include peripheral circuit transistors (not shown) for transmitting signals and/or power to a memory cell array included in the cell array area MCA. In embodiments, the peripheral circuit transistors (not shown) may form various circuits such as a command decoder, control logic, an address buffer, a row decoder, a column decoder, a sense amplifier, and a data input/output circuit.

As illustrated inFIG.2, in the cell array area MCA of the substrate110, a plurality of word lines WL extending in a first horizontal direction X and a plurality of bit lines BL extending in a second horizontal direction Y may be arranged. A plurality of cell transistors CTR may be arranged at intersections of the plurality of word lines WL and the plurality of bit lines BL. A plurality of storage nodes180may be arranged on each cell transistor CTR.

The plurality of word lines WL may include a first word line WL1and a second word line WL2alternately arranged in the second horizontal direction Y, and the plurality of cell transistors CTR may include a first cell transistor CTR1and a second cell transistor CTR2arranged alternately in the second horizontal direction Y. The first cell transistor CTR1may be disposed adjacent to the first word line WL1, and the second cell transistor CTR2may be disposed adjacent to the second word line WL2.

The first cell transistor CTR1and the second cell transistor CTR2may have a mirror symmetrical structure with respect to each other. For example, the first cell transistor CTR1and the second cell transistor CTR2may have a mirror symmetrical structure with respect to a center line between the first cell transistor CTR1and the second cell transistor CTR2extending in the first horizontal direction X.

As illustrated inFIG.3, a lower insulating layer112may be disposed on the substrate110. The substrate110may include silicon, for example, single crystalline silicon, polycrystalline silicon, or amorphous silicon. In some other embodiments, the substrate110may include at least one selected from Ge, SiGe, SiC, GaAs, InAs, and InP. In some embodiments, the substrate110may include a conductive region, for example, a well doped with an impurity, or a structure doped with an impurity. The lower insulating layer112may include an oxide film, a nitride film, or a combination thereof.

In some embodiments, a peripheral circuit structure may be disposed on the substrate110, and the lower insulating layer112may be disposed to cover the peripheral circuit structure. The peripheral circuit structure may include, but is not limited to, a sense amplifier electrically connected to the bit line BL and/or a sub-word line driver electrically connected to the word line WL.

A bit line BL extending in the second horizontal direction Y may be disposed on the lower insulating layer112. In embodiments, the bit line BL may include Ti, TiN, Ta, TaN, Mo, Ru, W, WN, TiSIN, WSiN, polysilicon, or a combination thereof. A bit line isolation insulating layer122extending in the second horizontal direction Y may be disposed on a sidewall of the bit line BL. For example, the bit line isolation insulating layer122may fill a space between two adjacent bit lines BL and may be formed at the same height as the bit lines BL.

A mold structure130may be disposed on the bit line BL and the bit line isolation insulating layer122. The mold structure130may include an etch stop layer132, a mold insulating layer134, a cover insulating layer136, and an interface insulating layer138. In some embodiments, the etch stop layer132may have a relatively small thickness and be disposed on upper surfaces of the bit line BL and the bit line isolation insulating layer122. The etch stop layer132may include silicon nitride.

In some embodiments, the mold insulating layer134may be disposed on the etch stop layer132. The mold insulating layer134may be formed to have a relatively large height. In embodiments, the mold insulating layer134may include silicon oxide.

In embodiments, the cover insulating layer136may be disposed on an upper surface of the mold insulating layer134. The cover insulating layer136may include a material having an etch selectivity with that of the mold insulating layer134. In embodiments, the cover insulating layer136may include silicon nitride.

In embodiments, the interface insulating layer138may be disposed on an upper surface of the cover insulating layer136and on a portion of a sidewall of the cover insulating layer136. In some embodiments, the interface insulating layer138may include silicon oxynitride or silicon oxide. In some embodiments, the interface insulating layer138may include a material layer formed by oxidizing a portion of the cover insulating layer136as a result of performing an oxygen annealing process on the upper surface of the cover insulating layer136.

In embodiments, the interface insulating layer138disposed on the sidewall of the cover insulating layer136may have a first thickness t11, and the interface insulating layer138disposed on the upper surface of the cover insulating layer136may have a second thickness t12. In embodiments, the first thickness t11and the second thickness t12may be in a range from about several angstroms to about tens of angstroms. In some embodiments, the first thickness t11may be substantially equal to the second thickness t12. In some embodiments, the first thickness t11may be less than the second thickness t12.

In embodiments, the mold structure130may include a plurality of mold openings130H. The plurality of mold openings130H may extend in the first horizontal direction X, and an upper surface of the bit line BL may be exposed at the bottom of each of the plurality of mold openings130H. For example, the plurality of mold openings130H may include a first sidewall130H1and a second sidewall130H2, and the first sidewall130H1and the second sidewall130H2may be spaced apart from each other and extend in the first horizontal direction X.

A plurality of active semiconductor layers140may be disposed on inner walls of the plurality of mold openings130H. Each of the plurality of active semiconductor layers140may include a first portion140P1and a second portion140P2. The first portion140P1may refer to a portion extending in a vertical direction Z on the first sidewall130H1and the second sidewall130H2of the mold openings130H. The second portion140P2may refer to a portion that is disposed at the bottom of the mold opening130H, disposed on the bit line BL, and in contact with the upper surface of the bit line BL. For example, each of the plurality of active semiconductor layers140may have a U-shaped vertical cross-section.

The first portion140P1of the active semiconductor layer140, which is disposed adjacent to the first sidewall130H1of the mold opening130H, may function as a vertical channel layer of the first cell transistor CTR1, and the first portion140P1of the active semiconductor layer140, which is disposed adjacent to the second sidewall130H2of the mold opening130H, may function as a vertical channel layer of the second cell transistor CTR2. Accordingly, within one mold opening130H, the first cell transistor CTR1and the second cell transistor CTR2may be arranged in a mirror symmetrical shape with each other.

The first portion140P1of the plurality of active semiconductor layers140may include a first sidewall S11and a second sidewall S12that are opposite to each other, and the first sidewall S11may be in contact with the mold insulating layer134. In embodiments, each of the plurality of active semiconductor layers140may have an upper surface disposed at a lower level than an upper surface of the mold structure130and disposed at the same level as a bottom surface of the cover insulating layer136. In some embodiments, each of the plurality of active semiconductor layers140may have an upper surface disposed at a lower level than the bottom surface of the cover insulating layer136.

In embodiments, the plurality of active semiconductor layers140may include an oxide semiconductor material. For example, the plurality of active semiconductor layers140may include at least one of indium gallium zinc oxide (InxGayZnzO), indium tungsten oxide (InxWyO), indium tin gallium oxide (InxSnyGazO), indium aluminum zinc oxide (InxAlyZnzO), indium gallium oxide (InxGayO), indium tin zinc oxide (InxSnyZnzO), indium gallium silicon oxide (InxGaySizO), indium zinc oxide (InxZnyO), indium oxide (InxO), and magnesium aluminum zinc oxide (MgxAlyZnzO), zinc tin oxide (ZnxSnyO), zirconium zinc tin oxide (ZrxZnySnzO), gallium zinc tin oxide (GaxZnySnzO), aluminum zinc tin oxide (AlxZnySnzO), and tin oxide (SnxO). In some embodiments, in addition to the materials described above, the plurality of active semiconductor layers140may include an oxide semiconductor material having a greater band gap energy than that of silicon.

A gate insulating layer150may be disposed on the second sidewall S12of the plurality of active semiconductor layers140. For example, the gate insulating layer150may be conformally arranged on the second sidewall S12of the first portion140P1and an upper surface of the second portion140P2of the plurality of active semiconductor layers140.

In some embodiments, the gate insulating layer150may have an upper surface disposed at a higher level than the upper surface of the active semiconductor layer140. The gate insulating layer150may have an upper surface disposed at the same level as the upper surface of the cover insulating layer136. In other embodiments, the gate insulating layer150may include at least one selected from a high-k dielectric material having a higher dielectric constant than silicon oxide, and a ferroelectric material. In some embodiments, the gate insulating layer150may include at least one material selected from among hafnium oxide (HfO), hafnium silicate (HfSiO), hafnium oxynitride (HfON), hafnium silicon oxynitride (HfSiON), lanthanum oxide (LaO), lanthanum aluminum oxide (LaAlO), zirconium oxide (ZrO), zirconium silicate (ZrSiO), zirconium oxynitride (ZrON), zirconium silicon oxynitride (ZrSiON), tantalum oxide (TaO), titanium oxide (TiO), barium strontium titanium oxide (BaSrTiO), barium titanium oxide (BaTiO), lead zirconate titanate (PbZrTiO), strontium bismuth tantalate (SrTaBiO), bismuth iron oxide (BiFeO), strontium titanium oxide (SrTiO), yttrium oxide (YO), aluminum oxide (AIO), or lead scandium tantalum oxide (PbScTaO).

The word line WL may be disposed on the second sidewall S12of the first portion140P1and the upper surface of the second portion140P2of the plurality of active semiconductor layers140such that the gate insulating layer150is disposed between the word line WL and the second sidewall S12. In embodiments, the word line WL may have an L-shaped vertical cross-section. In embodiments, the bit line BL may include Ti, TIN, Ta, TaN, Mo, Ru, W, WN, TiSIN, WSiN, polysilicon, or a combination thereof.

A first insulating liner162and a second insulating liner164may be disposed on sidewalls of two word lines WL spaced apart from each other within the mold opening130H, and a buried insulating layer166that fills a space between the two word lines WL spaced apart from each other, on the first insulating liner162and the second insulating liner164, may be arranged. For example, the first insulating liner162and the second insulating liner164may include silicon nitride, and the buried insulating layer166may include silicon oxide.

A landing pad170may be disposed on the mold structure130and an upper surface of the buried insulating layer166. The landing pad170may include an upper portion170U and a bottom portion170B, and the upper portion170U of the landing pad170may be disposed on the mold structure130and the upper surface of the buried insulating layer166, and the bottom portion170B of the landing pad170may be disposed inside a landing pad recess space170R.

For example, the landing pad recess space170R may be defined on an upper surface of the first portion140P1of the active semiconductor layer140, between the first and second sidewalls130H1and130H2of the mold opening130H and the gate insulating layer150. The bottom portion170B of the landing pad170may be disposed between the gate insulating layer150and the interface insulating layer138within the landing pad recess space170R. A bottom surface of the bottom portion170B of the landing pad170may contact the upper surface of the first portion140P1of the active semiconductor layer140. The bottom surface of the bottom portion170B of the landing pad170may be disposed at the same level as the bottom surface of the cover insulating layer136and a bottom surface of the interface insulating layer138.

In some embodiments, the landing pad170may have a T-shaped vertical cross-section, and the width of the upper portion170U of the landing pad170may be greater than the width of the bottom portion170B of the landing pad170. In embodiments, the landing pad170may include Ti, TiN, Ta, TaN, W, WN, TiSIN, WSiN, polysilicon, or a combination thereof.

In further embodiments, the interface insulating layer138may be disposed to cover the sidewall of the cover insulating layer136within the landing pad recess space170R, and accordingly, the bottom portion170B of the landing pad170and the cover insulating layer136may not be in contact with each other. For example, as illustrated inFIG.5, the entire sidewall of the cover insulating layer136facing the bottom portion170B of the landing pad170may be covered by the interface insulating layer138.

In a manufacturing process according to embodiments, a recess process may be performed on the upper side of the first portion140P1of the active semiconductor layer140disposed between the mold structure130and the buried insulating layer166, to thereby lower the height of the first portion140P1of the active semiconductor layer140and form the landing pad recess space170R. Then, by performing an oxygen annealing process through the upper surface of the first portion140P1of the active semiconductor layer140exposed in the landing pad recess space170R, oxygen vacancies included in the active semiconductor layer140may be passivated, thereby adjusting the carrier concentration of the active semiconductor layer140. As a result of the oxygen annealing process performed on the upper surface of the cover insulating layer136exposed on an inner wall of the landing pad recess space170R, the interface insulating layer138may be formed on the sidewall and the upper surface of the cover insulating layer136.

A landing pad isolation insulating layer172covering the landing pad170may be disposed on the mold structure130and the upper surface of the buried insulating layer166. The landing pad isolation insulating layer172may fill spaces between adjacent landing pads170and cover upper surfaces of the landing pads170, and the landing pad isolation insulating layer172may have an upper surface arranged at a higher level than the upper surfaces of the landing pads170. In other embodiments, the landing pad isolation insulating layer172may have an upper surface disposed at the same level as the upper surfaces of the landing pads170.

The storage node180may be disposed on the landing pad isolation insulating layer172. In some embodiments, the storage node180may be of a capacitor type (e.g., for a DRAM memory cell) and may include, for example, a lower electrode182, a capacitor dielectric layer184, and an upper electrode186. The lower electrode182may be disposed on the upper surfaces of the landing pads170and may extend in the vertical direction Z. The capacitor dielectric layer184may be disposed on a sidewall of the lower electrode182, and the upper electrode186may cover the lower electrode182on the capacitor dielectric layer184.

According to the embodiments described above, an oxygen annealing process may be performed through the upper surface of the active semiconductor layer140exposed in the landing pad recess space170R, and thus, the carrier concentration of the active semiconductor layer140may be adjusted, and accordingly, the semiconductor device100may have excellent electrical performance.

FIGS.6and7are cross-sectional views illustrating a semiconductor device100A according to embodiments, andFIG.8is an enlarged view of portion CX1ofFIG.6. InFIGS.6to8, the same reference numerals as those inFIGS.1to5indicate the same components. Referring toFIGS.6to8, the upper surface of the active semiconductor layer140may be disposed at a higher level than the upper surface of the mold insulating layer134. For example, the upper surface of the active semiconductor layer140may be higher than the bottom surface of the cover insulating layer136and may be disposed at a lower level than the upper surface of the cover insulating layer136. A landing pad170A may include an upper portion170U and a bottom portion170B, and the bottom portion170B of the landing pad170A may be disposed inside the landing pad recess space170R.

In some embodiments, the interface insulating layer138may be disposed to cover a portion of the sidewall of the cover insulating layer136within the landing pad recess space170R, and, for example, a lower portion of the sidewall of the cover insulating layer136may not be covered by the interface insulating layer138and may be in contact with the upper side of the first portion140P1of the active semiconductor layer140. The upper side of the sidewall of the cover insulating layer136may be covered by the interface insulating layer138and thus may not be in contact with the bottom portion170B of the landing pad170A.

In a manufacturing process according to embodiments, a recess process may be performed on the upper side of the first portion140P1of the active semiconductor layer140disposed between the mold structure130and the buried insulating layer166to thereby lower the height of the first portion140P1of the active semiconductor layer140and form the landing pad recess space170R. Here, the amount of etching in the recess process may be adjusted such that the upper surface of the active semiconductor layer140is at a lower level than the upper surface of the cover insulating layer136and at a higher level than the upper surface of the mold insulating layer134.

Then, by performing an oxygen annealing process through the upper surface of the first portion140P1of the active semiconductor layer140exposed in the landing pad recess space170R, oxygen vacancies included in the active semiconductor layer140may be passivated, thereby adjusting the carrier concentration of the active semiconductor layer140. Here, as a result of an oxygen annealing process performed on a portion of the upper surface and the sidewall of the cover insulating layer136exposed at the inner wall of the landing pad recess space170R, a portion of the cover insulating layer136may be oxidized to thereby form the interface insulating layer138.

A sidewall of the interface insulating layer138exposed in the landing pad recess space170R may be aligned with a lower sidewall of the cover insulating layer136, and the bottom surface of the interface insulating layer138may be arranged at a higher vertical level than the bottom surface of the cover insulating layer136.

FIG.9is a cross-sectional view of a semiconductor device100B according to embodiments, andFIG.10is an enlarged view of portion CX1ofFIG.9. InFIGS.9and10, the same reference numerals as those inFIGS.1to8indicate the same components. Referring toFIGS.9and10, the gate insulating layer150and the word line WL may have an L-shaped vertical cross-section, and the second insulating liner164may cover the sidewall of the word line WL and a sidewall of the gate insulating layer150and extend downwards to extend to the upper surface of the second portion140P2of the active semiconductor layer140.

According to embodiments, a portion of the active semiconductor layer140constituting the first cell transistor CTR1(seeFIG.2) within one mold opening130H may be connected to a portion of the active semiconductor layer140constituting the second cell transistor CTR2(seeFIG.2) (for example, the active semiconductor layer140is shared between the first cell transistor CTR1and the second cell transistor CTR2), and a portion of the gate insulating layer150constituting the first cell transistor CTR1within one mold opening130H may be disposed apart from a portion of the gate insulating layer150constituting the second cell transistor CTR2. In addition, within one mold opening130H, the portion of the gate insulating layer150constituting the first cell transistor CTR1may have a mirror symmetrical shape with respect to the portion of the gate insulating layer150constituting the second cell transistor CTR2.

FIG.11is a cross-sectional view illustrating a semiconductor device100C according to embodiments. InFIG.11, the same reference numerals as those inFIGS.1to10indicate the same components. Referring toFIG.11, the word line WL may have a vertical cross-section of a rectangular shape, and the upper and lower widths of the word line WL may be substantially the same. Also, the second insulating liner164described with reference toFIGS.1to5may be omitted and the buried insulating layer166may be disposed on the sidewall and upper surface of the first insulating liner162.

FIGS.12A to23are schematic diagrams showing a method of manufacturing the semiconductor device100according to embodiments, whereFIGS.12A,13A,14,15A,16A,17to21A,22, and23are cross-sectional views taken along line A1-A1′ ofFIG.2,FIGS.15B,16B, and21Bare cross-sectional views taken along line A2-A2′ ofFIG.2, andFIGS.12B,13B,15C, and16Care top views ofFIGS.12A,13A,15A, and16A. InFIGS.12A to23, the same reference numerals as those inFIGS.1to11indicate the same components.

Referring toFIGS.12A and12B, the lower insulating layer112is formed on the substrate110. Thereafter, the bit line isolation insulating layer122may be formed on the lower insulating layer112to fill a space between the plurality of bit lines BL extending in the second horizontal direction Y.

In some embodiments, the bit line isolation insulating layer122may be formed on the lower insulating layer112, and the bit line isolation insulating layer122may be patterned using a mask pattern (not shown) to form a bit line-forming space (not shown), and a conductive layer is formed within the bit line-forming space, and the upper side of the conductive layer may be removed so that the upper surface of the bit line isolation insulating layer122is exposed to thereby form the plurality of bit lines BL.

Referring toFIGS.13A and13B, a mold stack130S may be formed on the plurality of bit lines BL and the bit line isolation insulating layer122. As shown, this mold stack130S may include the etch stop layer132, the mold insulating layer134, and the cover insulating layer136. For example, the etch stop layer132may be formed using silicon nitride, the mold insulating layer134may be formed using silicon oxide, and the cover insulating layer136may be formed using silicon nitride.

Then, a mask pattern (not shown) may be formed on the mold stack130S, and the plurality of mold openings130H may be formed using the mask pattern as an etch mask. The upper surface of the bit line BL and the upper surface of the bit line isolation insulating layer122may be exposed at the bottom of the plurality of mold openings130H. The plurality of mold openings130H may be arranged to extend in the first horizontal direction X, and each of the plurality of mold openings130H may include the first sidewall130H1and the second sidewall130H2that extend in the first horizontal direction X and are opposite to each other.

Referring toFIG.14, a preliminary active semiconductor layer140P may be formed on the mold stack130S to conformally cover the inner wall of the mold opening130H. This preliminary active semiconductor layer140P may be formed using an oxide semiconductor material. For example, the preliminary active semiconductor layer140P may include at least one of indium gallium zinc oxide (InxGayZnzO), indium tungsten oxide (InxWyO), indium tin gallium oxide (InxSnyGazO), indium aluminum zinc oxide (InxAlyZnzO), indium gallium oxide (InxGayO), indium tin zinc oxide (InxSnyZnzO), indium gallium silicon oxide (InxGaySizO), indium zinc oxide (InxZnyO), indium oxide (InxO), and magnesium aluminum zinc oxide (MgxAlyZnzO), zinc tin oxide (ZnxSnyO), zirconium zinc tin oxide (ZrxZnySnzO), gallium zinc tin oxide (GaxZnySnzO), aluminum zinc tin oxide (AlxZnySnzO), and tin oxide (SnxO). In some embodiments, the preliminary active semiconductor layer140P may be formed using at least one of a chemical vapor deposition (CVD) process, a low pressure CVD process, a plasma enhanced CVD process, a metal organic CVD (MOCVD) process, and an atomic layer deposition process.

Referring toFIGS.15A to15C, a first mask layer210may be formed on the preliminary active semiconductor layer140P. The first mask layer210having a sufficiently thick thickness to entirely fill the mold opening130H may be formed.

Thereafter, a mask pattern (not shown) may be formed on the first mask layer210, and a portion of the preliminary active semiconductor layer140P may be removed using the mask pattern and the first mask layer210as an etch mask. For example, the mask pattern may have a line shape extending in the first horizontal direction X, and accordingly, the preliminary active semiconductor layer140P may also be left on the inner wall of the mold opening130H and an upper surface of the mold stack130P to extend in the first horizontal direction X. Also, as a portion of the preliminary active semiconductor layer140P is removed, the upper surface of the bit line isolation insulating layer122may be exposed again to the bottom of the mold opening130H.

Referring toFIGS.16A to16C, the first mask layer210may be removed. Then, a second mask layer220may be formed on the mold stack130S and the preliminary active semiconductor layer140P. The second mask layer220having a thickness sufficient to completely fill the mold opening130H may be formed, and thus, the upper surface of the preliminary active semiconductor layer140P disposed on the upper surface of the mold stack130S may be covered by the second mask layer220.

Thereafter, a planarization process may be performed on the upper side of the second mask layer220to remove a portion of the preliminary active semiconductor layer140P disposed on the upper surface of the mold stack130S (e.g., the cover insulating layer136) and leave the preliminary active semiconductor layer140P on the inner wall of the mold opening130H. In order that one active semiconductor layer140is disposed in a portion where one mold opening130H and one bit line BL intersect with each other as the portion of the preliminary active semiconductor layer140P disposed on the upper surface of the mold stack130S (e.g., the upper surface of the cover insulating layer136) is removed, a plurality of active semiconductor layers140spaced apart from each other in the first horizontal direction X and the second horizontal direction Y may be defined.

The active semiconductor layer140may include the first portion140P1disposed on the first and second sidewalls130H1and130H2of the mold opening130H and the second portion140P2that is disposed on the bottom of the mold opening130H and is continuously connected to the first portion140P1. The active semiconductor layer140may have a U-shaped vertical cross-section.

Referring toFIG.17, the second mask layer220may be removed. Then, the gate insulating layer150may be formed on the plurality of active semiconductor layers140. In some embodiments, the gate insulating layer150may include at least one selected from a high-k dielectric material having a higher dielectric constant than silicon oxide, and a ferroelectric material. In some embodiments, the gate insulating layer150may include at least one material selected from among hafnium oxide (HfO), hafnium silicate (HfSiO), hafnium oxynitride (HfON), hafnium silicon oxynitride (HfSiON), lanthanum oxide (LaO), lanthanum aluminum oxide (LaAIO), zirconium oxide (ZrO), zirconium silicate (ZrSiO), zirconium oxynitride (ZrON), zirconium silicon oxynitride (ZrSiON), tantalum oxide (TaO), titanium oxide (TiO), barium strontium titanium oxide (BaSrTiO), barium titanium oxide (BaTiO), lead zirconate titanate (PbZrTiO), strontium bismuth tantalate (SrTaBiO), bismuth iron oxide (BiFeO), strontium titanium oxide (SrTiO), yttrium oxide (YO), aluminum oxide (AIO), or lead scandium tantalum oxide (PbScTaO).

A word line metal layer WLP may be formed on the gate insulating layer150. In some cases, this word line metal layer WLP may be formed using Ti, TiN, Ta, TaN, Mo, Ru, W, WN, TiSIN, WSiN, polysilicon, or a combination thereof.

Referring toFIG.18, the first insulating liner162may be formed on the word line metal layer WLP, and an anisotropic etching process may be performed on the word line metal layer WLP and the first insulating liner162to remove a portion of the word line metal layer WLP disposed on the bottom of the mold opening130H and leave the word line WL on the first sidewall130H1and the second sidewall130H2of the mold opening130H. In addition, a portion of the word line metal layer WLP disposed on the upper surface of the mold stack130P may also be removed by the anisotropic etching process. After the anisotropic etching process, two word lines WL may be arranged apart from each other and disposed on the first sidewall130H1and the second sidewall130H2of the plurality of mold openings130H, respectively.

Referring toFIG.19, the second insulating liner164and the buried insulating layer166may be formed inside the mold opening130H. The second insulating liner164may be disposed on the upper surface of the active semiconductor layer140disposed at the bottom of the mold opening130H, for example, on the second portion140P2of the active semiconductor layer140. The buried insulating layer166may fill the mold opening130H on the second insulating liner164.

In embodiments, the buried insulating layer166may have an upper surface disposed at the same level as the upper surface of the mold stack130S, and the upper surface of the first portion140P1of the active semiconductor layer140and the upper surface of the gate insulating layer150may also be disposed at the same level as the upper surface of the mold stack130S.

Referring toFIG.20, a portion of the upper side of the active semiconductor layer140may be removed through an etch-back process to form the landing pad recess space170R. The landing pad recess space170R may refer to a space between the upper surfaces of the active semiconductor layers140between the upper side of the mold stack130S and the buried insulating layer166. The upper surface of the active semiconductor layer140may be disposed at the bottom of the landing pad recess space170R.

In embodiments, the landing pad recess space170R may be formed to a depth that exposes the sidewall of the cover insulating layer136, and the upper surface of the first portion140P1of the active semiconductor layer140may be disposed at the same level as the bottom surface of the cover insulating layer136.

Referring toFIGS.21A and21B, an oxygen annealing process P200may be performed through the upper surface of the active semiconductor layer140exposed in the landing pad recess space170R. In some cases, this oxygen annealing process P200may include exposing the upper surface of the active semiconductor layer140to an oxygen-containing atmosphere. For example, the oxygen annealing process P200may include supplying at least one of oxygen gas, atmospheric air, ozone, or oxygen plasma to the active semiconductor layer140so that oxygen atoms may penetrate through the upper surface of the active semiconductor layer140exposed in the landing pad recess space170R.

In embodiments, the oxygen annealing process P200may be performed under atmospheric pressure or elevated pressure. In some embodiments, the oxygen annealing process P200may be performed sequentially under vacuum and atmospheric pressure. In embodiments, the oxygen annealing process P200may be performed at room temperature or elevated temperature. In embodiments, the oxygen annealing process P200may be performed for about several minutes to about several hours.

In embodiments, by performing the oxygen annealing process P200, oxygen atoms may penetrate and/or diffuse into the active semiconductor layer140, and oxygen vacancies contained within the active semiconductor layer140may be passivated, and the carrier concentration of the active semiconductor layer140may be adjusted.

In embodiments, as the oxygen annealing process P200is performed through the upper surface of the active semiconductor layer140exposed in the landing pad recess space170R, a sufficient amount of oxygen atoms may be supplied into the active semiconductor layer140.

In embodiments, as a result of an oxygen annealing process performed on the upper surface of the cover insulating layer136exposed at the inner wall of the landing pad recess space170R, a portion of the cover insulating layer136may be oxidized to form the interface insulating layer138. The interface insulating layer138may be formed on the entire upper surface of the cover insulating layer136exposed during the oxygen annealing process P200. Additionally, the interface insulating layer138may be formed on the sidewall of the cover insulating layer136exposed within the landing pad recess space170R during the oxygen annealing process P200.

In embodiments, the interface insulating layer138formed on the sidewall of the cover insulating layer136may have the first thickness t11(seeFIG.5), and the interface insulating layer138formed on the upper surface of the cover insulating layer136may have the second thickness t12(seeFIG.5). In embodiments, the first thickness t11and the second thickness t12may be in a range from about several angstroms to about tens of angstroms. In some embodiments, the first thickness t11may be substantially equal to the second thickness t12. In some embodiments, the first thickness t11may be less than the second thickness t12. Here, the structure in which the etch stop layer132, the mold insulating layer134, the cover insulating layer136, and the interface insulating layer138are sequentially disposed is referred to as the mold structure130.

Referring toFIG.22, the landing pad170may be formed on the mold structure130and the buried insulating layer166. The landing pad170may fill the landing pad recess space170R and may contact the upper surface of the first portion140P1of the active semiconductor layer140. In some cases, the landing pad170may include Ti, TIN, Ta, TaN, W, WN, TiSIN, WSIN, polysilicon, or a combination thereof. And, in some embodiments, before forming the landing pad170in the landing pad recess space170R, a contact area may also be formed by implanting impurity ions into the upper surface of the first portion140P1of the active semiconductor layer140exposed in the landing pad recess space170R.

Referring toFIG.23, the landing pad isolation insulating layer172covering the landing pad170may be formed on the mold structure130and the buried insulating layer166. The landing pad isolation insulating layer172may be formed using silicon nitride. Then, the lower electrode182, the capacitor dielectric layer184, and the upper electrode186may be sequentially formed on the landing pad170and the landing pad isolation insulating layer172.

The semiconductor device100may be completely formed by performing the process described above. In addition, by performing the oxygen annealing process P200, oxygen atoms may be made to penetrate and/or diffuse into the active semiconductor layer140and thus oxygen vacancies within the active semiconductor layer140may be passivated, or the carrier concentration of the active semiconductor layer140may be adjusted. Accordingly, the semiconductor device100may have excellent electrical performance.

In other embodiments, in the process described with reference toFIG.20, the landing pad recess space170R may be formed to a depth that exposes only the upper portion of the sidewall of the cover insulating layer136, and the upper surface of the first portion140P1of the active semiconductor layer140A (seeFIG.6) may be disposed at a higher level than the bottom surface of the cover insulating layer136. In this case, when performing the oxygen annealing process P200in the process described with reference toFIG.21, the interface insulating layer138may be formed only on the upper portion of the sidewall of the cover insulating layer136exposed by the landing pad recess space170R. The lower portion of the sidewall of the cover insulating layer136may be covered by the active semiconductor layer140A and may not be exposed to the oxygen atmosphere, and the interface insulating layer138may not be formed on the lower portion of the sidewall of the cover insulating layer136. In this case, the semiconductor device100A described with reference toFIGS.6to8may be manufactured.