Motor controlling circuit and method

A motor control circuit includes: a detector outputting a detection signal in accordance with the motor rpm; a counter counting the number of clocks in accordance with a rotational cycle represented by the detection signal; a controller counting a DC motor based on the count value; and a divider dividing a frequency of a basic clock based on a preset division value to generate a counting clock. The divider generates a counting clock having a frequency corresponding to a rotational cycle, and the counter counts the number of counting clocks.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a motor control circuit and method controlling the rpm of a motor based on digital feedback control.

2. Description of Related Art

As a method of keeping the motor rpm constant, feedback control has been generally used.FIG. 3is a block diagram of a typical digital feedback control circuit. As shown inFIG. 3, a conventional, typical feedback control circuit101includes a comparator112, a PI (proportional plus integral) arithmetic circuit113, a constant current circuit/driver114, a DC motor115, a detector116, and a counter117.

In the digital feedback control circuit101, the rotation of the DC motor115is limited by a current value of the constant current circuit/driver114, and the detector116detects a rotational cycle (period) of the DC motor115. The counter117counts the number of clocks CLK while the detector116detects the cycle. Then, the counter sends a count value to the comparator112. The comparator112compares a current speed (motor rpm) sent from the counter117with an externally-supplied preset target speed to execute control such that the current speed approximates to the target speed. That is, the arithmetic circuit113calculates such a current value as to attain a target speed, and a current value of the constant current circuit/driver114is adjusted to drive a motor.

According to such digital feedback control, speed and cycle information are controlled as digital values. Regarding analog feedback control, a resistance or capacitance value should be adjusted in accordance with a load for stable control. In contrast, the digital feedback control has an advantage in that a constant is input as digital data and thus the adjustment is facilitated.

Incidentally, in the feedback circuit, if a target motor rpm is variable, the following problem arises. That is, although a rotational cycle is variable, a counting cycle of the clock CLK is fixed, so an accuracy of adjustment toward the target speed fluctuates. For example, if a counting cycle of clocks to be counted is reduced (frequency is increased) in step with a high rotational speed, a count value increases in the case of driving the motor at low rotational speed. Thus, it is necessary to increase a bit rate of the counter117. Meanwhile, if a counting cycle of clocks CLK is increased (frequency is decreased) in step with a low rotational speed, a control accuracy upon counting a speed is insufficient in the case of driving the motor at high rotational speed.

Meanwhile, Japanese Unexamined Patent Application Publication No. 2004-54762 (Shoji et al.) discloses a motor controlling apparatus provided with plural counter units and latch units.FIG. 4is a block diagram of the motor controlling apparatus disclosed by Shoji et al. As shown inFIG. 4, a motor controlling apparatus200disclosed by Shoji et al. includes a digital encoder201, a drive control unit203, and a motor driver unit211, and controls driving of a motor202. The digital encoder201outputs a signal of a rectangular waveform each time a mechanism is moved (rotated) by a predetermined distance (angle) as a result of driving the motor202. The drive control unit203includes an LPF (low-pass filter) unit204, a frequency detecting unit205, a first speed detecting counter unit206, a second speed detecting counter unit207, a first speed information latch unit208, a second speed information latch unit209, and a servo control unit210.

Noise components of an output signal from the digital encoder201are removed through the LPF unit204of the drive control unit203, and the resultant signal is input to the frequency detecting unit (edge detecting unit)205. The frequency detecting unit205generates a frequency detection signal based on the output signal of the digital encoder201to send the generated signal to the first speed detecting counter unit206and the second speed detecting counter unit207. The two counter units206and207measure a cycle of the output signal of the digital encoder by counting the number of input clocks. Here, the two counter units differ in terms of a unit encoder cycle. For example, the first speed detecting counter unit206counts clocks on the basis of one encoder cycle, and the second speed detecting counter unit207counts clocks on the basis of two encoder cycles.

Here, there is an asynchronous relation between an output signal of the digital encoder201, and the LPF unit204and the counter units206and207. As a result, quantization error inevitably occurs. In the case of driving the motor202at low rotational speed, a cycle of the output signal of the encoder201is long, so an influence of the quantization error is small. However, as the rotational speed increases, the influence of the quantization error becomes larger. As a measure for minimizing the influence of the quantization error upon high-speed rotation, there is a method of increasing a count frequency. However, in this case, the count value increases upon low-speed rotation, so a counter of a high bit rate should be used.

To that end, the counter unit is composed of the two counter units206and207and the latch units208and209to overcome the above problem. For example, a reference count value is set to 5 with respect to the target rpm. Even if the motor is actually driven at a speed closer to that speed, a detected count value varies from 4 to 6 (quantization error occurs) in some cases. If one counter is provided, variations of the output count value are not changed (reduced). If two counters are provided, variations of the count value with respect to two encoder cycles are about ½ of variations of the count value with respect to one encoder cycle. Therefore, variations of the count value, that is, quantization error can be suppressed. As described above, in the technique disclosed by Shoji et al., the number of clocks input during plural consecutive cycles is counted to reduce the quantization error.

In the technique disclosed by Shoji et al., plural counter units and latch units are provided, and an influence of the quantization error can be minimized thereby. However, a counting cycle for measuring the motor rpm is fixed, which results in a problem that an accuracy of adjustment toward the target speed is changed between low-speed rotation and high-speed rotation, similar to the aforementioned related art. In other words, if a clock cycle to be counted is reduced in step with a high rotational speed, the count value increases in the case of driving the motor at low speed, so a bit rate of the counter should be increased. Further, there arises another problem in that, if a clock cycle is increased in step with a low rotational speed, a control accuracy is insufficient in the case of driving the motor at high rotational speed.

The above problems are described in detail next.FIGS. 5A,5B,6A, and6B show rotational cycles (cycle of a detection signal D) and clocks CLK upon high-speed rotation and low-speed rotation. For example, if the target rpm of the DC motor is set variable from 10 Hz to 1 kHz, a counter needs to count a cycle longer than 100 ms and count a cycle shorter than 1 ms with sufficient speed detection resolution.

It is assumed that when the rotational speed is high, the cycle is set to, for example, 1 kHz, a bit rate of the counter is 8, and a target speed is about half the maximum count value, that is, 125. In this case, a cycle of the clock CLK is as follows: 1 ms/125=0.008 ms (FIG. 5A). Assuming that a rotational speed is low (10 Hz) with the cycle of the clock CLK, a required bit rate of a counter is about 15 bits (100 ms/0.008 ms=12500) (FIG. 5B). Other circuits should be accordingly configured to set a bit rate with reference to 15 bits (count value), with the result that the circuit scale is increased.

Similarly, considering that a rotational speed is low, for example, 10 Hz, the counting cycle is 100 ms/125=0.8 ms (FIG. 6A). This value is substantially equivalent to 1 bit of the above case where the rotational speed is high (1 kHz=1 ms) (FIG. 6B) The feedback control cannot be executed with sufficient accuracy at this bit rate.

SUMMARY OF THE INVENTION

An aspect of the present invention relates to a motor control circuit controlling motor driving through digital feedback control, wherein a counting cycle of counting a speed of movement due to the motor driving is set variable in accordance with the speed of movement.

Another aspect of the invention relates to a motor controlling method of controlling motor driving through digital feedback control, includes: driving a moving cycle in accordance with a speed of movement due to the motor driving; generating a counting clock having a cycle in accordance with the moving cycle; counting the counting clock; and controlling the motor based on the count value.

According to the present invention, a counting cycle of counting measuring a speed of movement due to the motor driving is set variable in accordance with the speed of movement, whereby an accuracy of adjustment toward a target speed can be almost the same between low-speed rotation and high-speed rotation.

That is, according to the present invention, it is possible to provide a motor control circuit and method that can keep a control accuracy without increasing a bit rate of the counter even if a target movement speed is different.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

Hereinafter, an embodiment of the present invention is described in detail with reference to the accompanying drawings.FIG. 1shows a motor control circuit according to the embodiment of the present invention. A motor control circuit1of this embodiment includes a divider18and a decoder11in addition to components of a conventional motor control circuit ofFIG. 3, which executes digital feedback control to keep the motor rpm constant. That is, as shown inFIG. 1, the motor control circuit1of this embodiment includes the decoder11, a comparator12, a PI arithmetic circuit13, a constant current circuit (driver)14, a DC motor15, a detector16, a counter17, and the divider18.

The decoder11divides a frequency in accordance with the target rpm of DC motor15. The comparator12compares a preset value with a count value of the counter17and supplies the comparison result to the PI arithmetic circuit13. The PI arithmetic circuit13and the constant current circuit/driver14function as controllers controlling the motor based on a count result. The PI arithmetic circuit13calculates a value of current generated with the constant current circuit/driver14based on the comparison result. Further, the constant current circuit/driver14generates a constant current based on the calculation result of the PI arithmetic circuit13.

The DC motor15is rotated in accordance with the value of current generated by the constant current circuit/driver14. The detector16outputs a detection signal in accordance with how far a device is moved. To be specific, the rotation of the DC motor15is detected, and a detection signal D representing the rotational cycle is sent to the counter17.

The divider18divides a basic clock CLK0based on a division value from the decoder11to generate a counting clock (divided clock) CLKn and supply the clock to the counter17. Incidentally, in this embodiment, the division value is set by the decoder11but may be directly and externally set in a divider18. The counter17receives the detection signal D from the detector16, and outputs a count value in accordance with the length of the cycle (rotational period). For example, the counter17counts the number of counting clocks CLKn supplied from the divider18during the rotational cycle, and supplies a count value to the comparator12.

Next, a motor controlling method of this embodiment is described. First, the detector16outputs the detection signal D in accordance with the rpm of the DC motor15. At this time, the decoder11generates a division value based on the target rpm to supply the generated value to the divider18. The divider18divides the basic clock CLK0based on the division value set by the decoder11to generate the counting clock CLKn. Then, the counting clock is supplied to the counter17.

The counter17counts the number of counting clocks CLKn in the rotational cycle represented by the above detection signal D. Then, the count value is supplied to the comparator12. The comparator12receives the count value of the target rpm (target count value) through the decoder11, and compares an actual count value from the counter17with the target count value. The PI arithmetic circuit13calculates a value of current generated by the constant current circuit/driver14based on the comparison result.

To be specific, an amount of current is increased based on the comparison result if the target count value<the actual count value, that is, if a current rotational speed of the DC motor15is lower than the target rpm. Alternatively, an amount of current is decreased based on the comparison result if the target count value>the actual count value, that is, if a current rotational speed of the DC motor15is higher than the target rpm. The constant current circuit/driver14generates a driving current for driving the DC motor15based on the preset value of the PI arithmetic circuit13.

In this embodiment, the decoder11generates a division value, and sends the generated division value to the divider18. Then, the divider divides the clock CLK0to be counted by the counter17in accordance with the division value. As a result, the target speed is made variable. Even in the case where the rotational cycle is different, the counting cycle of the counting clock is variable. Thus, it is unnecessary to increase a bit rate of the counter, and it is possible to count the number of clocks necessary for the rotational cycle. That is, it is possible to prevent a control accuracy from lowering without increasing a circuit area of the counter17, the comparator12, and the PI arithmetic circuit13.

Next, detailed description is given of operations of the motor control circuit of this embodiment based on actual numerical values. This embodiment describes an example where the DC motor15is designed to set the target rpm variable from 10 Hz to 1 kHz. In this case, the counter needs to count a cycle longer than 100 ms and count a cycle shorter than 1 ms with sufficient speed detection resolution.

FIGS. 2A and 2Bare schematic diagrams of a counting cycle and a rotational cycle in the case where the target speed is low and high, respectively. Description is made of the example where the target speed is set variable from 10 Hz to 1 kHz.FIG. 2Bshows the case where the target speed is low, that is, 100 ms. That is, the clocks (division value generated with the decoder11) are counted with the counting cycle of the counting clock CLKn set to, for example, 0.8 ms.FIG. 2Ashows the case where the target rotational speed is high, that is, 1 ms. That is, for example, the clocks are counted with the counting cycle of the counting clock CLKn set to 0.008 ms. As described above, the division value generated with the decoder11is set, and the divider18divides the clock CLK0. Thus, a target bit rate (control accuracy) after decoding is about 8 bits (7 Dh=125).

Incidentally, the above description is directed to such a division value that the bit rate of the counter is about 8 bits. In practice, it is necessary to preset the division value in consideration of the bit rate of the counter and the control accuracy.

In this embodiment, a conventional problem that the control accuracy lowers at the time of high-speed rotation can be overcome by adding the decoder11and the divider18. That is, the decoder11generates the division value in accordance with the target rpm, and the divider18divides a frequency of clocks to be counted by the counter17. At this time, a division value that makes the control accuracy (bit rate) constant between the low-speed rotation and the high-speed rotation is previously set in the decoder, making it possible to execute feedback control upon high-speed rotation without lowering the control accuracy.

In this way, in this embodiment, at the time of controlling the rpm of the motor through the digital feedback control, even if the rpm is set variable, an accuracy of adjustment toward the target speed is not changed. Further, the above can be realized only by counting the rotational cycle based on the counting clock CLKn having a frequency corresponding to the rotational speed, and in this embodiment, by adding the decoder11and the divider18for generating the counting clock CLKn. Therefore, it is unnecessary to reduce an influence of a quantization error by adding plural counter circuits to downsize a circuit.

Further, even in the case of determining a frequency of the counting clock CLKn supplied to the counter17with a control accuracy necessary for high-speed rotation, a frequency of the counting clock CLKn supplied to the counter17can be lowered upon the low-speed rotation. Thus, it is possible to suppress an increase in area of the PI arithmetic circuit13or other such circuits. As a result, the entire circuit scale can be considerably reduced.

For example, in this embodiment, the decoder11and the divider18are provided to generate the counting clock CLKn, but the present invention is not limited thereto. That is, any circuit configuration can be adopted as long as the rotational cycle can be counted based on the counting clock CLKn having a frequency variable in accordance with the motor rpm. Further, the clock cycle of the counting clock is set variable in accordance with the rotational cycle. The clock cycle of the counting clock may be set variable in accordance with the moving speed of the mechanism driven by the motor.