Non-volatile memory devices and methods of fabricating the same

A memory device may include a switching device and a storage node coupled with the switching device. The storage node may include a first electrode, a second electrode, a data storage layer and at least one contact layer. The data storage layer may be disposed between the first electrode and the second electrode and may include a transition metal oxide or aluminum oxide. The at least one contact layer may be disposed at least one of above or below the data storage layer and may include a conductive metal oxide.

PRIORITY STATEMENT

This non-provisional application claims priority under 35 U.S.C. §119 to Korean Patent Application No. 10-2005-0108125, filed on Nov. 11, 2005, in the Korean Intellectual Property Office (KIPO), the entire contents of which are incorporated herein by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

Example embodiments of the present invention relate to non-volatile memory devices that may use resistance material. For example, at least some example embodiments of the present invention may be directed to non-volatile memory devices with an improved structure providing more stable memory switching characteristics in a storage node and fabrication methods thereof.

2. Description of the Conventional Art

Conventional non-volatile memory devices using a conventional resistance material may include ferroelectric random access memory (FRAM), magnetoresistive RAM (MRAM) and phase-change RAM (PRAM). While dynamic RAM (DRAM) and flash memories store binary information using charges, FRAM, MRAM and PRAM store binary information using a polarization characteristic of a ferroelectric material, a resistance change of a magnetic tunnel junction (MTJ) according to a magnetized state of a strong magnetic material, and a resistance change due to a phase change, respectively. The FRAM, MRAM and PRAM may be integrated on a larger scale similar to DRAM and may be non-volatile similar to flash memories. Therefore, FRAM, MRAM and PRAM may be used in replacing conventional volatile or non-volatile memories.

PRAM will be described as an example non-volatile memory device. PRAM may retrieve binary information using a certain characteristic of a phase-change material such as GeSbTe (GST). This example phase-change material changes its phase into a crystalline or amorphous state by heat generated regionally when an electric pulse is applied to the phase-change material. In PRAM, a memory cell storing binary information may include a phase-change layer, a resistor and a switch transistor. The phase-change layer may be a GST-based material, for example, a material referred to as chalcogenide. The resistor may be used to heat the phase-change layer. Depending on a degree of heat, a resistance value may vary because the phase-change layer changes phase into a crystalline or amorphous state. Current flowing into the resistor may cause a voltage level to vary, and the variable voltage level may allow for PRAM to store and read binary information.

FIG. 1is a cross-sectional view briefly illustrating a conventional non-volatile memory device.FIG. 2is a graph illustrating a switching characteristic of a storage node illustrated inFIG. 1.FIG. 3Ais a graph illustrating a distribution of set and reset voltage values applied to the storage node illustrated inFIG. 1.FIG. 3Bis a graph illustrating a distribution of resistance values of the storage node depending on an on or off state.

Referring toFIG. 1, the conventional non-volatile memory device using a thin NiO layer may include a transistor20and a storage node28coupled with the transistor20. The transistor20may include a source12S, a drain12D, a channel12C, an insulating layer13and a gate electrode14. The storage node28may include an upper electrode26, a lower electrode24and a thin NiO layer25disposed there between. An insulation layer30may be disposed between the storage node28and the transistor20. The storage node28may be coupled with the transistor20through a conductive contact plug22, and a plate electrode32may be formed over the upper electrode26.

The storage node28of the conventional non-volatile memory device may have an M-I-M memory cell structure. Herein, ‘M’ represents metal-based upper and lower electrodes, and ‘I’ represents a NiO layer, which is a resistance material. In a conventional resistance material implemented memory device having the M-I-M memory cell structure, set voltage values Vsetand reset voltage values Vresetapplied to a storage node during repetitive switchings may be distributed with larger deviation. During repetitive switchings, the storage node may have non-uniform resistance values RONand ROFFdepending on an on or off state.

As a result, memory switching characteristics may be unstable in conventional non-volatile memory devices.

SUMMARY OF THE INVENTION

At least some example embodiments of the present invention provide non-volatile memory devices with an improved structure and/or more stable memory switching characteristics in a storage node, and fabrication methods thereof.

According to an example embodiment of the present invention, a non-volatile memory device may include a switching device and a storage node coupled with the switching device. The storage node may include a first electrode; a second electrode, a data storage layer disposed between the first electrode and the second electrode and at least one contact layer. The data storage layer may include a transition metal oxide or aluminum oxide. The at least one contact layer may be arranged between the first electrode and the data storage layer and/or between the data storage layer and the second electrode. The at least one contact layer may include a conductive metal oxide. The conductive metal oxide may improve interfacial characteristics between the data storage layer and the first electrode and/or between the data storage layer and the second electrode.

The conductive metal oxide may be comprised of IrO2, RuO2, SrRuO3, MoO2, OsO2, ReO2, RhO2, WO2and/or indium tin oxide (ITO). The at least one contact layer may have a thickness ranging from approximately 10 Å to approximately 500 Å. The transition metal oxide may be an oxide of a metal such as Ni, Nb, Ti, Zr, Hf, Co, Fe, Cu and/or Cr. Each of the first electrode and the second electrode may be formed of a material such as Ir, Pt, Ru, W, TiN and/or polysilicon. The switching device may be a transistor or a diode. The at least one contact layer may include a single contact layer arranged between the first electrode and the data storage layer, a single electrode arranged between the data storage layer and the second electrode or a first and a second contact layer. If the at least one contact layer includes a first and a second contact layer, the first contact layer may be arranged between the first electrode and the data storage layer and the second contact layer may be arranged between the data storage layer and the second electrode.

According to another example embodiment of the present invention a method of fabricating a non-volatile memory device may include preparing a switching device, forming a first electrode coupled with the switching device, forming a first contact layer over the first electrode, forming a data storage layer formed over the first contact layer, and forming a second electrode over the data storage layer. The first contact layer may include a conductive metal oxide, and the data storage layer may include a transition metal oxide or aluminum oxide.

In at least some example embodiments of the present invention, a second contact layer may be formed on the data storage layer using a conductive metal oxide after forming the data storage layer and before forming the second electrode.

According to another example embodiment of the present invention, a method of fabricating a non-volatile memory device may include preparing a switching device, forming a first electrode coupled with the switching device, forming a data storage layer over the first electrode, forming a contact layer over the data storage layer and forming a second electrode over the contact layer. The data storage layer may include a transition metal oxide or aluminum oxide, and the contact layer may include a conductive metal oxide

The conductive metal oxide may be one of IrO2, RuO2, SrRuO3, MoO2, OsO2, ReO2, RhO2, WO2, and ITO (indium tin oxide). The contact layer may be formed to a thickness ranging from approximately 10 Å to approximately 500 Å. The transition metal oxide may be an oxide of a metal selected from the group consisting of Ni, Nb, Ti, Zr, Hf, Co, Fe, Cu, and Cr. Each of the first electrode and the second electrode may be formed of a material selected from the group consisting of Ir, Pt, Ru, W, TiN, and polysilicon. The switching device may be a transistor or a diode.

According to example embodiments of the present invention, the non-volatile memory device may be implemented with an improved structure, which provides a more stable switching characteristic in the storage node.

DETAILED DESCRIPTION OF EXAMPLE EMBODIMENTS OF THE PRESENT INVENTION

Various example embodiments of the present invention will now be described more fully with reference to the accompanying drawings in which some example embodiments of the invention are shown. In the drawings, the thicknesses of layers and regions are exaggerated for clarity.

Detailed illustrative embodiments of the present invention are disclosed herein. However, specific structural and functional details disclosed herein are merely representative for purposes of describing example embodiments of the present invention. This invention may, however, may be embodied in many alternate forms and should not be construed as limited to only the embodiments set forth herein.

Accordingly, while example embodiments of the invention are capable of various modifications and alternative forms, embodiments thereof are shown by way of example in the drawings and will herein be described in detail. It should be understood, however, that there is no intent to limit example embodiments of the invention to the particular forms disclosed, but on the contrary, example embodiments of the invention are to cover all modifications, equivalents, and alternatives falling within the scope of the invention. Like numbers refer to like elements throughout the description of the figures.

It will be understood that when an element or layer is referred to as being “formed on” another element or layer, it can be directly or indirectly formed on the other element or layer. That is, for example, intervening elements or layers may be present. In contrast, when an element or layer is referred to as being “directly formed on” to another element, there are no intervening elements or layers present. Other words used to describe the relationship between elements or layers should be interpreted in a like fashion (e.g., “between” versus “directly between”, “adjacent” versus “directly adjacent”, etc.).

It should also be noted that in some alternative implementations, the functions/acts noted may occur out of the order noted in the FIGS. For example, two FIGS. shown in succession may in fact be executed substantially concurrently or may sometimes be executed in the reverse order, depending upon the functionality/acts involved.

FIG. 4is a cross-sectional view illustrating a non-volatile memory device according to an example embodiment of the present invention.FIG. 5is a graph illustrating a switching characteristic of a storage node illustrated inFIG. 4.

With reference toFIGS. 4 and 5, the non-volatile memory device may include a transistor120and/or a storage node128. The transistor120may be a switching device, and the storage node128may be coupled to the transistor120. An insulation layer130may be disposed between the storage node128and the transistor120. A conductive contact plug122may couple the storage node128with the transistor120. A plate electrode132may be disposed over the storage node128and coupled with the storage node128. The transistor120may include a source112S, a drain112D, a channel112C, an insulating layer113and/or a gate electrode114. Because a structure of the transistor120and a fabrication method thereof are well known in the art, detailed description thereof will be omitted. Although example embodiments of the present invention are described herein with regard the transistor120, other switching devices (e.g., diodes, etc.) may be used. A diode structure and a fabrication method thereof are also well known in the art and a detailed description thereof will be omitted.

The storage node128may include a first electrode123, a second electrode127, a data storage layer125, a first contact layer124and a second contact layer126. The data storage layer125may be disposed between the first electrode123and the second electrode127. The first and second contact layers124and126may be disposed at least beneath or above the data storage layer125.

The data storage layer125may transition to a reset state or a set state based on (or depending on) a voltage level applied to the data storage layer125(e.g., seeFIG. 5). Because the data storage layer125has different resistance values for each state, binary information may be stored and read based on a difference between the resistance values. The data storage layer125may include a transition metal oxide, aluminum oxide or the like. The transition metal oxide may be an oxide of a metal selected from, for example, nickel (Ni), niobium (Nb), titanium (Ti), zirconium (Zr), hafnium (Hf), cobalt (Co), iron (Fe), copper (Cu), chrome (Cr), a combination thereof or the like. The first electrode123and the second electrode127may include, for example, one of iridium (Ir), platinum (Pt), ruthenium (Ru), tungsten (W), titanium nitride (TiN), polysilicon, a combination thereof or the like.

The first and second contact layers124and126may include a conductive metal oxide. Because the first and second contact layers124and126are formed at least beneath or above the data storage layer125, the first and second contact layers124and126may improve interfacial characteristics between the data storage layer125and the lower electrode123and/or between the upper electrode127and the data storage layer125. The conductive metal oxide may be IrO2, RuO2, SrRuO3, MoO2, OsO2, ReO2, RhO2, WO2, indium tin oxide (ITO), a combination thereof or the like. The first and second contact layers124and126may have a thickness ranging from approximately 10 Å to approximately 500 Å, inclusive.

Compared with the conventional M-I-M memory cell structure, the storage node128of the non-volatile memory device, according to at least some example embodiments of the present embodiment, may have, for example, an M-B-I-B-M, M-B-I-M or M-I-B-M memory cell structure. ‘M’ represents the first electrode123and the second electrode127both including a metal or conductive material. ‘I’ and ‘B’ represent the data storage layer125and the first and second contact layers124and126, respectively.

Conventional resistance material based memory devices with the M-I-M memory cell structure may be limited in that set and reset voltage values Vsetand Vresetapplied to the storage node during repetitive switchings may be distributed with a larger deviation. In addition, resistance values RONand ROFFfor the storage node depending on an ON or OFF state may not be distributed uniformly. According to example embodiments of the present embodiment, however, these limitations may be improved, for example, by improving the interfacial characteristics between the data storage layer125and the first electrode123and/or between the data storage layer125and the upper electrode127. For example, in the case of repetitive switching, resistance values of the storage node128may be distributed with a decreased level of deviation due to the improved interfacial characteristics as compared with the conventional resistance material based memory device. As a result, the storage node128may have more stable memory switching characteristics.

FIGS. 6A through 7Billustrate an improved memory switching characteristic in the non-volatile memory device according to an example embodiment of the present invention.

FIG. 6Ais a graph illustrating an example distribution of set and reset voltage values applied to the storage node illustrated inFIG. 4.FIG. 6Bis a histogram of the set and reset voltage values illustrated inFIG. 6A.FIG. 7Ais a graph illustrating an example distribution of resistance values of the storage node depending on an on or off state, andFIG. 7Bis a histogram of the resistance values of the storage node illustrated inFIG. 7A.

With reference toFIGS. 6A and 6B, an example distribution of set and reset voltage values Vsetand Vresetwith respect to a switching cycle will be discussed. The storage node128according to at least some example embodiments of the present invention may have set and reset voltage values Vsetand Vresetwith decreased standard deviations. Table 1 below shows data obtained from measuring set and reset voltage values Vsetand Vresetof the conventional M-I-M memory cell structure and the M-B-I-B-M memory cell structure, according to an example embodiment of the present invention, and comparing average values, standard deviation values, maximum values and minimum values of the measured set voltage values Vsetand the reset voltage values Vreset. Herein, the set voltage values Vsetand the reset voltage values Vresetare measured in voltages.

With reference toFIGS. 7A and 7B, an example distribution of resistance values RONand ROFFof the storage node128with respect to a switching cycle will be discussed. The storage node128according to example embodiments of the present invention may have resistance values RONand ROFFwith decreased standard deviations. Table 2 below exhibits data obtained from measuring resistance values RONand ROFFof the conventional M-I-M memory cell structure and an M-B-I-B-M memory cell structure according to an example embodiment of the present invention, and comparing average values, standard deviation values, maximum values and minimum values of the measured resistance values RONand ROFF. Herein, the resistance values RONand ROFFare measured in Ohms.

Table 3 below shows data for an example structure of the storage node used in measuring the set and reset voltage values Vsetand Vreset, the resistance values RONand ROFFand various sputtering deposition conditions for depositing an IrO2contact layer.

FIGS. 8A through 8Eare cross-sectional views illustrating a method of fabricating a non-volatile memory device according to an example embodiment of the present invention. According to at least some example embodiments of the present invention, a typical vacuum deposition method such as a chemical vapor deposition (CVD) method, a physical vapor deposition (PVD) method or the like may be used to deposit target layers. The PVD method may include, for example, a sputtering method. The non-volatile memory device according to at least one example embodiment of the present invention may include a transistor120and a storage node128. The transistor120may serve as a switching device, and although example embodiments of the present invention are described with regard to transistor120, any suitable switching device may be used. The storage node128may be coupled to the transistor120. Because a diode structure and a fabrication method thereof are well known in the art, a detailed description thereof will be omitted for the sake of brevity.

Referring toFIG. 8A, the transistor120may include a source112S, a drain112D, a channel112C, an insulating layer113and/or a gate electrode114. An insulation layer130may be formed over the transistor120. Because a structure of the transistor120and a fabrication method thereof are well known in the art, a detailed description thereof will be omitted for the sake of brevity.

A contact hole may be formed in the insulation layer130. The contact hole may exposes the source112S or the drain112D. A conductive material may fill the contact hole to form a contact plug122. A first electrode123may be formed over a portion of the insulation layer130such that the first electrode123contacts the contact plug122. The first electrode123may include, for example, one of Ir, Pt, Ru, W, TiN, polysilicon, a combination thereof or the like.

Referring toFIG. 8B, a first contact layer124may be formed over the first electrode123. The first contact layer124may include a conductive metal oxide, for example, one of IrO2, RuO2, SrRuO3, MoO2, OsO2, ReO2, RhO2, WO2, ITO, a combination thereof or the like. The first contact layer124may have a thickness of approximately 10 Å to approximately 500 Å, inclusive.

Referring toFIGS. 8C to 8D, a data storage layer125may be formed over the first contact layer124. The data storage layer125may include a transition metal oxide, aluminum oxide, a combination thereof or the like. The transition metal oxide may be an oxide of a metal, for example, one of Ni, Nb, Ti, Zr, Hf, Co, Fe, Cu, Cr, a combination thereof or the like. A second contact layer126may be formed over the data storage layer125. The second contact layer126may include a transition metal oxide, for example, one of IrO2, RuO2, SrRuO3, MoO2, OsO2, ReO2, RhO2, WO2, ITO, a combination thereof or the like. The second contact layer126may have a thickness of approximately 10 Å to approximately 500 Å, inclusive. A second electrode127may be formed over the second contact layer126. The second electrode127may be, for example, Ir, Pt, Ru, W, TiN, polysilicon, a combination thereof or the like.

Referring toFIG. 8E, another insulation layer130may be formed over the above resultant structure (e.g., seeFIG. 8D), for example, until the insulation layer130covers or substantially covers (e.g., buries) the storage node128. Another contact hole, which may expose the second electrode127, may be formed in the insulation layer130, and a plate electrode132may be formed over the insulation layer130and in the other contact hole. Using the processes, according to example embodiments of the present invention, a non-volatile memory device having more stable memory switching characteristics in the storage node may be fabricated. Although the storage node128according to example embodiments of the present embodiment are described as including the first contact layer124and the second contact layer126, the storage node128according to example embodiments of the present invention may include one of the first contact layer124and the second contact layer126.

According to the example embodiments of the present invention, the non-volatile memory device may have more stable memory switching characteristics in the storage node. Using the contact layer formed of a conductive metal oxide such as IrO2may improve the interfacial characteristics between the data storage layer and the first electrode and between the data storage layer and the second electrode. As compared with the conventional non-volatile memory device, the improved interfacial characteristics may decrease a deviation in resistance values of the storage node depending on an ON or OFF state, and/or a deviation of set and reset voltage values applied to the storage node. As a result, more stable memory switching characteristics may be obtained.

In example embodiments, the data storage layer may be made of a transition metal oxide having multiple resistance states, as described above. For example, the data storage layer may be made of at least one material selected from the group consisting of NiO, TiO2, HfO, Nb2O5, ZnO, WO3, and CoO or GST (Ge2Sb2Te5) or PCMO(PrxCa1-xMnO3). The data storage layer film may be a chemical compound including one or more elements selected from the group consisting of S, Se, Te, As, Sb, Ge, Sn, In and Ag.

In some example embodiments, the data storage layer may include chalcogenide alloys such as germanium-antimony-tellurium (Ge—Sb—Te), arsenic-antimony-tellurium (As—Sb—Te), tin-antimony-tellurium (Sn—Sb—Te), or tin-indium-antimony-tellurium (Sn—In—Sb—Te), arsenic-germanium-antimony-tellurium (As—Ge—Sb—Te). Alternatively, the data storage layer may include an element in Group VA-antimony-tellurium such as tantalum-antimony-tellurium (Ta—Sb—Te), niobium-antimony-tellurium (Nb—Sb—Te) or vanadium-antimony-tellurium (V—Sb—Te) or an element in Group VA-antimony-selenium such as tantalum-antimony-selenium (Ta—Sb—Se), niobium-antimony-selenium (Nb—Sb—Se) or vanadium-antimony-selenium (V—Sb—Se). Further, the data storage layer may include an element in Group VIA-antimony-tellurium such as tungsten-antimony-tellurium (W—Sb—Te), molybdenum-antimony-tellurium (Mo—Sb—Te), or chrome-antimony-tellurium (Cr—Sb—Te) or an element in Group VIA-antimony-selenium such as tungsten-antimony-selenium (W—Sb—Se), molybdenum-antimony-selenium (Mo—Sb—Se) or chrome-antimony-selenium (Cr—Sb—Se).

Although the data storage layer is described above as being formed primarily of ternary phase-change chalcogenide alloys, the chalcogenide alloy of the data storage layer could be selected from a binary phase-change chalcogenide alloy or a quaternary phase-change chalcogenide alloy. Example binary phase-change chalcogenide alloys may include one or more of Ga—Sb, In—Sb, In—Se, Sb2—Te3or Ge—Te alloys; example quaternary phase-change chalcogenide alloys may include one or more of an Ag—In—Sb—Te, (Ge—Sn)—Sb—Te, Ge—Sb—(Se—Te) or Te81—Ge15—Sb2—S2alloy, for example.