Photo mask and method of manufacturing in-plane-switching mode liquid crystal display device using the same

A photo mask is disclosed.The photo mask includes a mask substrate, and a mask pattern formed to include a plurality of unit mask patterns which are arranged in a single line for a fine pattern formation. The unit mask pattern is configured to include a body portion positioned at a center and wing portions formed in a triangular shape at both sides of the body portion.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims priority under 35 U.S.C. 119 to Korean Patent Application No. 10-2009-0013611, filed on Feb. 18, 2009, which is hereby incorporated by reference in its entirety.

BACKGROUND

1. Field of the Disclosure

This disclosure relates to a photo mask and a method of manufacturing a liquid crystal display device of an in-plane-switching (IPS) mode using the same.

2. Description of the Related Art

In general, liquid crystal display (LCD) devices control the light transmittance of dielectric anisotropy liquid crystal using an electric field, so as to display pictures. To this end, these LCD devices each include an LCD panel configured to include a plurality of liquid crystal cells arranged in a matrix shape for the display of pictures, and a driving circuit configured to drive the LCD panel. The LCD panel is classified into an IPS mode or a vertical electric field mode, according to the direction of the electric field used for driving the liquid crystal.

An LCD device of the vertical electric field mode drives the liquid crystal using the vertical electric field between a pixel electrode and a common electrode which are respectively formed on two substrates disposed opposite to each other. As such, the vertical electric field mode LCD device has a large aperture ratio, but it has a narrow viewing angle.

On the other hand, a LCD device of the IPS mode drives the liquid crystal using the horizontal electric field between pixel and common electrodes which are disposed parallel to each other on a substrate. Accordingly, the IPS mode LCD device has a wider viewing angle than that of the vertical electric field mode LCD device.

FIG. 1is a perspective view showing an IPS mode LCD panel of the related art. Referring toFIG. 1, the IPS mode LCD panel includes an upper substrate11provided with a color filter array, a lower substrate1provided with a thin film transistor array, and a liquid crystal molecules18filled between the two substrates1and11.

The color filter array substrate includes a black matrix12, color filters14, and an overcoat layer16which are formed on the upper substrate11. The black matrix12is formed to overlap with thin film transistors (TFTs)6, gate lines2, and data lines4on the TFT array substrate1given below, and define cell regions in which the color filters14will be formed. Such a black matrix12prevents light leakage and absorbs external light so that the contrast of an LCD panel increases. The color filters14are formed on the cell regions divided by the black matrix12. The cell regions can be classified into red, green, and blue regions. As such, the color filters can include red, green, and blue color filter patterns formed on the respective red, green, and blue regions. The overcoat layer16is formed on the upper substrate11covered with the black matrix12and the color filters14.

The TFT array substrate includes TFTs6formed on the lower substrate1, pixel electrodes8each connected to the TFTs6, and common electrodes10parallel to the pixel electrodes8. Each of the TFTs6responds to a gate signal applied to its gate electrode and applies a data signal on its source electrode to the respective pixel electrode8via its drain electrode. To this end, the gate electrode of the TFT6is connected to gate line2transferring the gate signal, and the source electrode of the TFT6is connected to respective data line4transferring the data signal. The pixel electrode8is connected to the drain electrode of the respective TFT6and receives the data signal. The source and drain electrodes of the TFT6make in ohmic contact with a semiconductor pattern (not shown) which overlaps with the gate electrode in the center of a gate insulation film. The pixel electrode8and a finger portion of the common electrode10are formed parallel to each other on each of the pixel regions which are defined by crossing the gate lines2and the data lines4. Each of the common electrodes10is connected to a respective common line9parallel to the gate line2. The common electrode10receives a common voltage, which is used for driving the liquid crystal molecules18, from the common lines9.

A horizontal electric field is generated by the data signal applied to the pixel electrode8and the common voltage applied to the common electrode10. The horizontal electrode field forces the liquid crystal molecules to rotate on the basis of a horizontal direction. The light transmittance of the pixel region varies along the rotated amount of the liquid crystal molecules to the horizontal direction so that a picture is displayed on the IPS mode LCD panel. The liquid crystal molecules driven by the horizontal electric field have a lower birefringence variation ratio to a viewing angle direction, in comparison with those driven by a vertical electric field. As such, the IPS mode LCD panel can improve the viewing angle.

However, the liquid crystal molecules of the IPS mode LCD panel are not uniformly driven throughout the pixel region, as shown inFIG. 2. Actually, the liquid crystal molecules disposed between the pixel electrode8and the common electrode10are normally driven by the horizontal electric field generated between the pixel electrode8and the common electrode10, thereby controlling a transmission light amount. On the other hand, the molecules disposed to overlap with the pixel electrode8and the common electrode10cannot be driven. This results from the fact that the horizontal electric field is not formed in a space overlapping with the pixel and common electrodes8and10. As such, the aperture ratio of the pixel region is reduced.

In order to enhance the aperture ratio in the IPS mode LCD panel, the number of effective opening regions W provided by the alternately arranged fingers of the pixel and common electrodes should increase, or the width of each effective opening region W should be enlarged. To rectify this, the fingers of the pixel and common electrodes8and10parallel to each other must have a reduced width. However, the widths of the fingers of the pixel and common electrodes8and10are limited to exposure resolution in a photolithography process.

FIGS. 3A to 3Care cross-sectional view illustrating step-by-step a electrode formation method using a photolithography process according to a related art. Referring toFIG. 3A, a conductive layer22is formed on a substrate20, and a photo resist pattern24is formed on the conductive layer22. The photo resist pattern24is prepared through exposing, developing, and baking processes. The exposing process allows a photo resist film to be partially exposed to light passing through a mask, so that a mask pattern is transcribed onto the photo resist film. In this case, the exposure resolution limit of present exposure equipment makes it difficult to form a photo resist pattern in a line width below 5 μm. As such, it is also difficult to form a conductive pattern in a line width below 4 μm.

Subsequently, the conductive layer22is etched through an etching process, thereby forming an electrode26fully covered with the photo resist pattern25as shown inFIG. 3B. Then, the photo resist pattern24is removed by a strip process, as shown inFIG. 3C. Characteristically, a wet etching process forces the conductive layer22to be characteristically over-etched. As such, the electrode26is formed to have a line width narrower than that of the photo resist pattern24. Nevertheless, it is actually difficult to form the electrode26in a line width below 5 μm, even though the photo resist pattern24is prepared to have a minimum line width of 5 μm.

In other words, the minimum widths of the pixel and common electrodes in the IPS mode LCD panel are limited to the resolution of exposure equipment. Therefore, the aperture ratio of the IPS mode LCD panel can be enhanced above a critical value.

BRIEF SUMMARY

Accordingly, the present embodiments are directed to a photo mask that substantially obviates one or more of problems due to the limitations and disadvantages of the related art, and a method of manufacturing an IPS mode LCD device using the same.

An object of the present embodiment is to provide a photo mask adapted to enhance an aperture ratio, and an IPS mode LCD device manufacturing method using the same.

Additional features and advantages of the embodiments will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the embodiments. The advantages of the embodiments will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.

According to one general aspect of the present embodiment, a photo mask includes: a mask substrate; and a mask pattern formed to include a plurality of unit mask patterns which are arranged in a single line for a fine pattern formation. The unit mask pattern is configured to include a body portion positioned at a center and wing portions formed in a triangular shape at both sides of the body portion.

The body portions included in the plurality of unit mask patterns are connected to one another. The body portion is formed to have a length corresponding to a ratio of 2:1 to a height of the wing portion, and the wing portion of the triangular shape is formed to have an apex angle of substantially 90°.

The body portion is formed to have a length range of 1.5˜3.0 μm, and the wing portion is formed to have a height range of 1˜1.5 μm.

An IPS mode LCD device manufacturing method according to another aspect of the present embodiment includes: sequentially forming a conductive layer and a photo resist film on a substrate; aligning a photo mask with a mask pattern for a fine pattern formation over the substrate covered with the photo resist film; patterning the photo resist film by performing an exposing process using the photo mask and a developing process; and forming an electrode by etching the conductive layer using the photo resist pattern as an etch mask.

The mask pattern for the fine pattern formation is formed to include a plurality of unit mask patterns arranged in a single line. Each of the unit mask patterns is configured to include a body portion positioned at a center and wing portions formed in a triangular shape at both sides of the body portion.

The body portions included in the plurality of unit mask patterns are connected to one another. The body portion is formed to have a length corresponding to a ratio of 2:1 to a height of the wing portion, and the wing portion of the triangular shape is formed to have an apex angle of substantially 90°.

The electrode is configured to include a pixel electrode. The conductive layer is configured include a transparent conductive layer.

The electrode is formed in a line width range of about 1.5˜2.0 μm.

The IPS mode LCD device manufacturing method further includes: forming a gate electrode on the substrate; forming a gate insulation film on the substrate with the gate electrode; forming a semiconductor pattern, a source electrode, and a drain electrode on the substrate covered with the gate insulation film; and forming a passivation film, on the substrate with the source and drain electrodes, configured to include a contact hole which is formed by patterning the passivation film, before the conductive layer and the photo resist film are sequentially formed.

DETAILED DESCRIPTION

Reference will now be made in detail to the preferable embodiments of the present disclosure, examples of which are illustrated in the accompanying drawings. These embodiments introduced hereinafter are provided as examples in order to convey their spirits to the ordinary skilled person in the art. Therefore, these embodiments might be embodied in a different shape, so are not limited to these embodiments described here. Also, the size and thickness of the device might be expressed to be exaggerated for the sake of convenience in the drawings. Wherever possible, the same reference numbers will be used throughout this disclosure including the drawings to refer to the same or like parts.

First, a photo mask according to an embodiment of the present disclosure will be described.

FIG. 4Ais a planar view illustrating a photo mask according to an embodiment of the present disclosure, andFIG. 4Bis an enlarged planar view showing a region “A” inFIG. 4A. Referring toFIG. 4A, a photo mask100of the present embodiment includes a mask substrate99and mask patterns101which are used for forming fine patterns.

The mask substrate99includes regions on which the fine patterns101will be formed. Such a mask substrate99can be formed from a quartz material.

The mask patterns101used for forming fine patterns each includes a plurality of unit mask patterns103which are arranged in a single line, as shown inFIG. 4B. The unit mask pattern103includes a body portion105positioned at its center, and wing portions107formed in a triangular shape at both sides of the body portion105. The body portions each included in the plurality of unit mask patterns103are connected with one another, so as to form a single mask pattern101to be used for forming a single fine line pattern.

The body portion105is formed to have a length I of about 1.5˜3.0 μm, and the wing portion is formed to have a height I′ of about 1˜1.5 μm. The length I of the body portion105has a ratio of 2:1 to the height I′ of the wing portion107. The wing portion107is formed to have an apex angle I″ of substantially 90°.

As seen in the following table 1, the fine pattern has a line width range of about 0.283-1.450 μm when the ratio of the length I of the body portion105to the height I′ of the wing portion107has a ratio of 2:1 and the wing portion had an apex angle of substantially 90°.

In this way, the fine line patterns can be formed using the photo mask100with such mask patterns101. A fine pattern formation method using the photo mask100will now be explained in detail referring to the attached drawings.

FIGS. 5A to 5Care cross-sectional views illustrating a fine pattern formation method using a photo mask according to an embodiment of the present disclosure.

A fine pattern formation method of the present embodiment allows a metal film211aand a photo resist film213aof a photo-sensitive material to be sequentially deposited on a substrate200, as shown inFIG. 5A. Then, a photo mask100with a mask pattern101for a fine pattern formation is aligned above the substrate200covered with the photo resist film213a.

Subsequently, an exposing process using the photo mask100is performed as shown inFIG. 5B. The exposing process enables light111to be selectively irradiated onto the photo resist film213through the photo mask100which is aligned over the substrate200and includes the mask pattern101. The exposing process using the mask pattern101for the fine pattern formation causes diffracted light to be irradiated onto regions of the photo resist film213a, so that the photo resist film is patterned in a width range of about 2˜2.5 μm.

More specifically, the wing portions107of the mask pattern101for the fine pattern formation cause offset-interference phenomena of light111, thereby forcing diffracted light not to be irradiated onto a region of the photo resist film213aopposite to the body portion105of the mask pattern101. As such, regions of the photo resist film213acorresponding to the wing portions107and the outer regions thereof on the photo mask100can be removed. Accordingly, the photo resist film213acan be patterned in a width narrower than the length of the body portion105of the mask pattern101for the fine pattern formation. In other words, the photo resist film213acan be patterned in a width range of about 2˜2.5 μm.

Afterward, a developing process is performed for the light-exposed photo resist film213a, so as to remove a part of the photo resist film213acorresponding to the light-exposed regions. Accordingly, photo resist patterns213bare formed on the metal film211a.

As shown inFIG. 5C, a metal pattern211bis formed on the substrate200by etching the metal film211ausing the photo resist pattern213bas an etch mask. Then, the photo resist pattern213bis removed by performing a strip process for the substrate200with the metal pattern211b, so that the fine pattern formation process of the present embodiment is completed. The metal pattern211bhas a line width of 1.5˜2.0 μm narrower than that of the photo resist pattern213b. This results from the fact that the metal film211ais over-etched due to the characteristic of the etching process.

In this way, the fine pattern formation method of the present embodiment forms a metal pattern using the photo mask which includes the mask pattern101for a fine pattern formation. As such, the metal pattern having a line width smaller than the exposure resolution can be formed regardless of the exposure resolution D. For example, if the exposure resolution is in a range of 3˜4 μm, a pattern formation method of the related art cannot form a pattern having a line width below 3 μm, but the fine pattern formation method of the present embodiment can form a fine pattern having a line width of about 1.5˜2.0 μm.

Such a fine pattern formation method can be applied to a process of forming pixel electrodes which are included in an IPS mode LCD device. In this case, the line width of the pixel electrode can be greatly reduced from a previous range of about 4 μm to a range of 1.5˜2.0 μm. Accordingly, the aperture ratio of the IPS mode LCD device can become larger, and furthermore the brightness of the ISP mode LCD device can be enhanced.

Subsequently, an IPS mode LCD device manufactured using the fine pattern formation process of the present embodiment and a manufacturing method thereof will be explained.

FIG. 6is a planar view showing a thin film transistor array substrate included into an IPS mode LCD device according to an embodiment of the present disclosure, andFIG. 7is a cross-sectional view showing a thin film transistor array substrate taken along the line I-I′ inFIG. 6.

A thin film transistor array substrate shown inFIGS. 6 and 7includes: a gate line302and a data line304crossing each other in the center of a gate insulation film352on a lower substrate350and defining a pixel region; a thin film transistor TFT connected to the gate and data lines302and304and a pixel electrode318b; and a common electrode322and the pixel electrode318bforming a horizontal electric field in the pixel region. The thin film transistor array substrate further includes a common line320connected with the common electrode322, and a storage capacitor Cst connected to the pixel electrode318b.

The gate line302transfers a scan signal from a gate driver (not shown), and the data line304transfers a video data signal from a data driver (not shown). Such gate and data lines302and304are formed to cross each other in the center of the gate insulation film354and define pixel regions.

The thin film transistor TFT responds to the scan signal on the gate line302and enables the video data signal on the data line304to be charged and maintained in the pixel electrode318b. To this end, the thin film transistor TFT includes: a gate electrode308connected to the gate line302; a source electrode310connected to the data line304; and a drain electrode312, opposite to the source electrode310, connected to the pixel electrode318b. The thin film transistor TFT further includes an active layer314overlapping with the gate electrode308in the center of the gate insulation film358, and an ohmic contact layer316being in ohmic contact with the active layer314and the source/drain electrodes310and312. The active layer314forms a channel between the source electrode310and the drain electrode312. A semiconductor pattern consisting of the active layer314and the ohmic contact layer316also overlaps with the data line304.

The common line320transfers a reference voltage (i.e., the common voltage) to each of the pixels through the common electrode322. The reference voltage is used for driving liquid crystal. The fingers of the common electrode322are formed to protrude parallel to the fingers of the pixel electrode318bfrom the common line320toward the inside of the pixel region. The horizontal portion of the common electrode322is connected with the fingers of the common electrode322. The fingers of the common and pixel electrodes322and318bare formed in a zigzag shape together with the data line304, as shown inFIG. 6. Alternatively, the fingers of the common and pixel electrodes322and318bcan be formed in the zigzag shape, while the data line304can be formed in a straight stripe shape. In still another manner, all of the fingers of the common and pixel electrodes322and318band the data line304can be formed in the straight stripe shape. In other words, the fingers of the common and pixel electrodes322and318band the data line304can be formed in a variety of shapes.

The pixel electrode318bis formed to include fingers parallel to those of the common electrode322, a first horizontal portion overlapped with the drain electrode312, and a second horizontal portion overlapped with the horizontal portion of the common electrode322. The first and second horizontal portions of the pixel electrode318bare connected with the fingers of the pixel electrode318b. The first horizontal electrode of the pixel electrode318bis connected to the drain electrode312via a contact hole326which penetrates through the passivation (or protective) film356. When a video data signal is applied to the pixel electrode318bthrough the thin film transistor TFT, a horizontal electric field is generated between the fingers of the pixel electrode318band the fingers of the common electrode322which receives the common voltage.

The horizontal electric field rotates liquid crystal molecules, which are arranged in a horizontal direction between the thin film transistor array substrate and a color filter array substrate, due to their dielectric anisotropy. The rotated amount of the liquid crystal molecules changes the transmittance of light passing through the pixel region, thereby realizing a variety of gray scales.

The storage capacitor Cst is formed from the common line320and the drain electrode312which overlap with each other in the center of the gate insulation film254and the semiconductor pattern315. This storage capacitor Cst allows the video data signal charged in the pixel electrode318bto be stably maintained until the video data signal is applied again.

A method of manufacturing a thin film transistor array substrate of such a configuration will now be explained.

A plurality of first conductive patterns including gate lines302, gate electrodes322, common lines320, and common electrodes322are prepared on a substrate350by forming a first conductive layer on the substrate350and patterning the first conductive layer.

Also, a gate insulation354, semiconductor patterns315, and a plurality of second conductive patterns are formed on the substrate350with the first conductive patterns by stacking the gate insulation film354, a semiconductor layer, and a second conductive layer on the substrate with the first conductive patterns and patterning the second conductive layer and the semiconductor layer. The semiconductor pattern315includes an active layer314and an ohmic contact layer316, and a plurality of second conductive pattern includes data lines304, source electrodes310, and drain electrodes312. The semiconductor patterns315and the second conductive patterns can be formed through masking processes which are performed using separated masks.

Thereafter, a passivation (or protective) film356is formed on the substrate350partially covered with the second conductive patterns. Contact holes326are formed on the passivation film356by patterning the passivation film356. Also, pixel electrodes318bare prepared by forming a transparent conductive layer on the passivation film356and patterning the transparent conductive layer.

Meanwhile, the common electrodes322can be formed on the passivation film356together with the pixel electrodes318b. In this case, the common electrodes322are connected to the common lines320via other contact holes penetrating through the passivation film356and the gate insulation film354.

Such a method of manufacturing a thin film transistor array substrate forms the pixel electrodes318busing a fine pattern formation process of the present embodiment. In this case, the line width of fingers of each pixel electrode318bis reduced from a previous range of about 4.0 μm to a range of 1.5˜2.01 μm, so that the brightness of an IPS mode LCD device is enhanced. The fine pattern formation process of the present disclosure form forming the pixel electrodes318bwill now be described as follows.

As shown inFIG. 8A, a transparent conductive layer318aand a photo resist film403aof a sensitive material are sequentially deposited on a substrate350stacked with a common electrode322, a gate insulation film354, and a passivation film356. Then, a photo mask100with mask patterns101for a fine pattern formation is aligned over the substrate350covered with the photo resist film403a.

Subsequently, an exposing process using the photo mask100is performed as shown inFIG. 8B. The exposing process enables light111to be selectively irradiated onto the photo resist film403athrough the photo mask100, which is aligned over the substrate350and includes the mask patterns101. The exposing process using the mask patterns101for the fine pattern formation causes diffracted light to be irradiated onto regions of the photo resist film403a, so that the photo resist film403ais patterned in a width range of about 2˜2.5 μm.

More specifically, the wing portions107of the mask patterns101for the fine pattern formation cause offset-interference phenomena of light111, thereby forcing diffracted light not to be irradiated onto a region of the photo resist film403aopposite to the body portions105of the mask patterns101. As such, regions of the photo resist film403acorresponding to the wing portions107and the outer regions thereof on the photo mask100can be removed. Accordingly, the photo resist film403acan be patterned in a width narrower than the length of the body portion105of the mask pattern101for the fine pattern formation. In other words, the photo resist film403acan be patterned in a width range of about 2˜2.5 μm.

Afterward, a developing process is performed for the light-exposed photo resist film403a, so as to remove a part of the photo resist film403acorresponding to the light-exposed regions. Accordingly, photo resist patterns403bare formed on the transparent conductive layer318a.

As shown inFIG. 8C, fingers of a pixel electrode318bare formed on the passivation film356by etching the transparent conductive layer318ausing the photo resist patterns403bas an etch mask. Then, the photo resist patterns403bare removed by performing a strip process for the substrate350with the pixel electrode318b, so that the fine pattern formation process of the present embodiment is completed. The finger of the pixel electrode318bhas a line width of 1.5˜2.0 μm narrower than that of the photo resist pattern403b. This results from the fact that the transparent conductive layer318ais over-etched due to the characteristic of the etching process.

As described above, the photo mask and the IPS mode LCD device manufacturing method using the same, according to embodiments of the present disclosure, allow the line width of the pixel electrode to be reduced to a range of about 1.5˜2.0 μm. Therefore, the aperture ratio of the IPS mode LCD device can be enhanced.

Although the present disclosure has been limitedly explained regarding only the embodiments described above, it should be understood by the ordinary skilled person in the art that the present disclosure is not limited to these embodiments, but rather that various changes or modifications thereof are possible without departing from the spirit of the present disclosure. Accordingly, the scope of the present disclosure shall be determined only by the appended claims and their equivalents.