Semiconductor device and method of manufacturing the semiconductor device

A semiconductor device includes a semiconductor element having a plated portion on a part of a main surface and a protective member that seals surfaces of the semiconductor element except for the main surface, wherein the plated portion is electrically connected to a circuit in the semiconductor element.

TECHNICAL FIELD

The present invention relates to a semiconductor device and a method of manufacturing the semiconductor device.

BACKGROUND ART

Semiconductor devices in which terminals for external connection are directly mounted on a bare chip without internal wiring of bonding wires have been known. For example, PTL1 describes a semiconductor device having a structure in which bumps for external connection are provided on one surface of a bare chip and other surfaces are sealed with a protective resin.

CITATION LIST

Patent Literature

SUMMARY OF INVENTION

Technical Problem

In the conventional semiconductor device described in PTL1, the mounting terminals are formed of solder bumps. It is therefore difficult to control the thickness of the semiconductor device in its height direction.

Solution to Problem

A semiconductor device according to the 1st aspect comprises: a semiconductor element having a plated portion on a part of a main surface; and a protective member that seals surfaces of the semiconductor element except for the main surface, wherein: the plated portion is electrically connected to a circuit in the semiconductor element. A method of manufacturing a semiconductor device according to the 2nd aspect comprises: forming a plated portion on a part of a main surface of the semiconductor element, the plated portion being electrically connected to a circuit in a semiconductor element; and sealing surfaces except for the main surface of the semiconductor element, with a protective member.

Advantageous Effects of Invention

According to the present invention, the thickness in the height direction of the semiconductor device can be easily controlled.

DESCRIPTION OF EMBODIMENTS

Hereinafter, a semiconductor device, a method of manufacturing the semiconductor device, and the like according to a first embodiment will be described with reference to the drawings as required. In the following embodiment, a surface of the semiconductor device on which an external connection terminal is provided is referred to as a main surface of the semiconductor device. Further, a direction perpendicular to the main surface is referred to as a vertical direction, and a direction outward from the main surface of the semiconductor device is referred to as upward (an upper direction). Moreover, in the following embodiments, a term “connect” includes a meaning that two objects connected to each other can conduct electricity.

First Embodiment

FIG. 1is a schematic view of the semiconductor device according to the first embodiment of the present invention.FIG. 1(a)is a cross-sectional view of the semiconductor device1andFIG. 1(b)is a plan view of the semiconductor device1as viewed from the main surface side.

The semiconductor device1includes a semiconductor element10, a pad11a, a pad11b, a mounting terminal12a, a mounting terminal12b, and a sealing resin13. A terminal formation surface S of the semiconductor element10on which the pad11aand the pad11bare formed is the main surface. On the terminal formation surface S, the pad11aand the pad11bare arranged side by side. The mounting terminal12ais provided over the pad11ain the upper direction. The pad11ais electrically connected to the mounting terminal12a. A mounting terminal12bis provided over the pad11bin the upper direction. The pad11bis electrically connected to the mounting terminal12b.

In the following description, the pad11aand the pad11bare collectively referred to as pads11. Similarly, the mounting terminal12aand the mounting terminal12bare collectively referred to as mounting terminals12.

An insulating protective layer16is formed on a portion of the terminal formation surface S where the pads11are not formed. The insulating protective layer16insulates the semiconductor element10and protects the semiconductor element10from foreign matters and the like. The insulating protective layer16includes a passivation film17formed on the terminal formation surface S and a protective film18formed on the passivation film17.

The mounting terminal12includes a first conductive layer14formed on the pad11and a second conductive layer15formed on the first conductive layer14. The first conductive layer14is made of a conductor such as copper. The second conductive layer15is made of a conductor such as tin or silver.

The semiconductor element10is a bare semiconductor chip obtained by dicing a wafer which is a semiconductor substrate. The semiconductor element10is configured to include a single circuit such as a diode, or an electronic circuit such as an integrated circuit or a large scale integrated circuit. The pad11aand the pad11bare made of metal such as aluminum. The sealing resin13is a protective member that seals five surfaces of the semiconductor device1, which has six surfaces, except for the terminal forming surface S where the mounting terminals12and the insulating protective layer16are provided.

Method of Manufacturing Semiconductor Device1

Hereinafter, a method of manufacturing the semiconductor device1will be described with reference toFIGS. 2 to 5. The semiconductor device1is manufactured by sequentially performing steps 1 to 14 on a wafer20of a material.

Note thatFIGS. 2 and 3show only a region corresponding to one semiconductor device1among a large number of semiconductor devices1formed on the wafer20. In practice, a large number of semiconductor device formation regions are formed on the wafer20. In each semiconductor device formation region, the semiconductor device1shown inFIGS. 2 and 3is to be formed.

As shown inFIG. 2(a), the pad11aand the pad11bare formed on the wafer20by a method such as vapor deposition. A passivation film17is formed over the pad11on the terminal formation surface S of the wafer20on which the pad11is formed.

An opening21is formed in the passivation film17in a region over the pad11. The pad11is exposed from the opening21of the passivation film17.

In step 1, the wafer20is coated with polyimide. A polyimide resin is applied on the wafer20shown inFIG. 2(a). The polyimide resin is then exposed using a photomask having a predetermined pattern formed therein, developed, and cured. As a result, the wafer20is configured as shown inFIG. 2(b). InFIG. 2(b), a protective film18made of the polyimide resin has been formed on the passivation film17. The thickness of the protective film18is approximately 5 micrometers, for example. The protective film18is not formed over the opening21.

In step 2, a seed layer22for electroplating is formed. The seed layer22is formed on the pad11and the protective film18shown inFIG. 2(b)by sputtering or the like. The seed layer22is a thin film that functions as a UBM (Under Bump Metallurgy). The seed layer22is made of titanium (Ti) as an adhesion layer, and copper (Cu) on the adhesion layer, for example. As a result, the wafer20is configured as shown inFIG. 2(c). InFIG. 2(c), the seed layer22has been formed on the protective film18and the opening21.

In step 3, a plating resist23is formed. A plating resist is applied on the seed layer22shown inFIG. 2(c). The plating resist is then exposed using a photomask having a predetermined pattern formed therein and developed. As a result, the wafer20is configured as shown inFIG. 2(d). InFIG. 2(d), the plating resist23has been formed on the seed layer22. The plating resist23is not formed on a portion where the mounting terminals12are to be formed, that is, over the opening21.

In step 4, a first conductive layer14of the mounting terminal12is formed. The first conductive layer14is formed by electroplating on a portion where the plating resist23shown inFIG. 2(d)is not formed. The first conductive layer14is made of copper, for example. As a result, the wafer20is configured as shown inFIG. 3(a). InFIG. 3(a), a part of the mounting terminal12, that is, the first conductive layer14has been formed over the opening21.

In step 5, a second conductive layer15of the mounting terminal12is formed. The second conductive layer15is formed by electroplating on the first conductive layer14shown inFIG. 3(a). The second conductive layer15is made of metal containing tin and silver, for example. As a result, the wafer20is configured as shown inFIG. 3(b). InFIG. 3(b), the mounting terminal12including the first conductive layer14and the second conductive layer15has been formed over the opening21. Note that the thickness of the mounting terminal12as viewed from a surface of the insulating protective layer16is desirably 15 micrometers or less in order to reduce a mounting thickness of the semiconductor device1. For example, such a thickness can be realized with the thickness of the first conductive layer14of approximately 8 micrometers and the thickness of the second conductive layer15of approximately 3 micrometers.

In step 6, the plating resist23is removed. Since the first conductive layer14and the second conductive layer15shown inFIG. 3(b)have been formed, the plating resist23is unnecessary and is thus removed. As a result, the wafer20is configured as shown inFIG. 3(c). InFIG. 3(c), the plating resist23formed on portions where the mounting terminal12aand the mounting terminal12bare not located has been removed.

In step 7, the exposed seed layer22is removed. The exposed seed layer22is removed by etching so that the mounting terminals12shown inFIG. 3(c)are isolated from each other. As a result, the wafer20is configured as shown inFIG. 3(d). InFIG. 3(d), the exposed seed layer22, which existed between the mounting terminal12aand the mounting terminal12b, has been removed.

FIG. 4(a)shows a part of the wafer20that has been subjected to the above-described steps 1 to 7. Note thatFIGS. 4 and 5schematically show regions corresponding to three semiconductor devices1in the entire wafer20.

In step 8, back-grinding and attaching to a dicing tape is performed. By back-grinding, the wafer20is removed and thinned from the bottom surface side, which is opposite to the main surface, to a predetermined thickness. Thereafter, the bottom surface of the wafer20is attached to the dicing tape30. As a result, the wafer20is configured as shown inFIG. 4(b). InFIG. 4(b), the dicing tape30has been attached to the surface of the wafer20, namely, the bottom surface that is opposite to the main surface on which the mounting terminals12are formed.

In step 9, dicing of the semiconductor device1is performed. That is, the wafer20, together with the protective film18and the passivation film17, is cut from the upper side along boundaries between regions (semiconductor device formation regions) in which the semiconductor devices1are formed. The cutting is performed to the middle of the thickness of the dicing tape30. By cutting the wafer20, the regions having a large number of semiconductor devices1, which are to be obtained from the wafer20, are separated from one another. As a result, the wafer20is configured as shown inFIG. 4(c). InFIG. 4(c), individual wafer pieces separated from one another are adhered to the dicing tape30.

In step 10, a tape is again attached. A support tape31is attached to the wafer20to cover the terminal formation surface S of the wafer20, and then the dicing tape30attached to the bottom surface of the wafer20is peeled off. As a result, the wafer20is configured as shown inFIG. 4(d). InFIG. 4(d), the mounting terminals12have been buried in the support tape31. A surface16aof the insulating protective layer16is in contact with a surface of the support tape31.

In step 11, resin sealing is performed. For example, five surfaces except for the terminal formation surface S having the support tape31attached thereto are sealed with the sealing resin13by vacuum lamination. For example, the wafer20is covered with a film-like thermosetting resin, and heated at 120° C. to 150° C. with an applied pressure of 0.5 MPa under a vacuum of 1 hPa or less. As a result, as shown inFIG. 5(a), the wafer20is filled with the sealing resin13between the separated semiconductor device formation regions (wafer pieces), and one surface13aof the sealing resin13becomes flat. That is, inFIG. 5(a), the wafer pieces once separated in step 9 have been again fixed together by the sealing resin13. Further, since the resin sealing is performed while the surface16aof the insulating protective layer16is in contact with the surface of the support tape31, a surface13bof the sealing resin13in contact with the support tape31becomes flush with the surface16aof the insulating protective layer16.

Note that the thickness h of the sealing resin13on a surface (upper surface) of the wafer20is desirably 30 micrometers or less in order to further reduce the thickness of the semiconductor device1. Additionally, the sealing resin13desirably contains a filler in order to reliably seal between the wafer pieces with the sealing resin13. Micro-sized or nano-sized fillers dispersed in the resin enhance strength, heat resistance, flame retardancy, insulation properties, and facilitate thinning and planarization.

Here, pressing may be performed to planarize the surface13aof the sealing resin13. When the thickness of the upper surface of the sealing resin13has a certain amount or more, a roughness on the upper surface of the sealing resin13may occur. However, this pressing allows the upper surface of the sealing resin13to be planarized.

In step 12, each of the wafer pieces integrated with the sealing resin13is peeled off from the support tape31. In a case where the support tape31has a property of reducing its adhesive strength by heating, the support tape31is desirably peeled off while heating. After peeling off the support tape31, post-curing is performed as required to fix the sealing resin13. In a case where post-curing is performed after peeling off the support tape31, it is not necessary to consider thermal characteristics of the support tape31. If the support tape31has a high heat resistance, post-curing may be performed before peeling off the support tape31. As a result, the wafer20is configured as shown inFIG. 5(b). InFIG. 5(b), the surface13bof the sealing resin13in contact with the support tape31and the surface16aof the insulating protective layer16are continuously formed and are flush with each other, as described above.

In step 13, a dicing tape32is attached to a surface of the wafer20. As a result, the wafer20is configured as shown inFIG. 5(c).

In step 14, dicing is performed. The sealing resin13filled between the wafer pieces is cut and removed, leaving a required thickness of the sealing resin13from peripheral side edges of each wafer piece. As a result, the wafer20is configured as shown inFIG. 5(d). InFIG. 5(d), a large number of semiconductor devices1have been attached onto the dicing tape32.

According to the embodiment described above, the following operational advantages can be achieved.

(1) The semiconductor element10has the mounting terminal12formed on a part of the terminal formation surface S by plating. Surfaces of the semiconductor element10except for the terminal formation surface S are sealed with the sealing resin13. The mounting terminal12is electrically connected to a circuit in the semiconductor element10. In this way, the thickness in the height direction of the semiconductor device1can be easily controlled. In particular, the mounting thickness of the semiconductor device1can be made thinner than that in conventional semiconductor devices.

(2) Ends of the bottom surface S of the semiconductor element10(ends of the insulating protective layer16) and a surface of the sealing resin13are formed continuously, that is, they constitute a single plane. In this way, the semiconductor element10can be reliably sealed to have a high insulation ability. Further, side surfaces of the mounting terminals12are completely exposed without being buried in the sealing resin13, so that the extremely thin mounting terminals12can be formed.

In a case where the mounting terminal12is formed by thin plating instead of solder balls having a certain height, a distance from a surface of the mounting terminal12to side surfaces of the semiconductor element10is small. Therefore, solder may extend to the side surfaces of the semiconductor element10when the mounting terminal12is soldered.

By sealing the side surfaces of the semiconductor element10with the sealing resin13as in the embodiment described above, occurrence of short circuit at the time of mounting due to extension of the solder can be avoided. Moreover, according to the manufacturing method in the embodiment described above, the side surfaces and the back surface of the semiconductor element10can be reliably sealed with the sealing resin having a uniform thickness. Furthermore, according to this manufacturing method, the thickness of the sealing resin13on the side surfaces can be easily controlled by changing a dicing width.

(3) The thickness from the bottom surface S of the mounting terminal12is 15 micrometers or less. In this way, the mounting thickness of the semiconductor device1can be made significantly thinner than that in conventional semiconductor devices having a thickness of approximately 50 micrometers, for example.

(4) The sealing resin13is cured and formed uniformly in a single step 11. In this way, resin sealing can be more robustly and rapidly performed compared with the conventional art as described in PTL1 and the like, in which sealing is formed by potting in separate steps.

(5) The sealing resin13is formed by vacuum lamination. In this way, the thickness of the sealing resin on the upper surface of the semiconductor device1can be more reliably controlled.

The following modifications are also included within the scope of the present invention, and one or more of the modifications may be combined with the above-described embodiment.

First Modification

A method of forming the mounting terminal12is not limited to the method according to steps 1 to 7 described above. For example, instead of steps 1 to 7, the mounting terminal12may be formed by a method described below.

In a semiconductor device1ashown inFIG. 6(a), a mounting terminal12is formed by a method different from the method according to steps 1 to 7. First, a zincate treatment is performed on a pad11as a pretreatment for plating. Thereafter, a first conductive layer31of nickel (Ni) is formed on the pad11by electroless plating. A second conductive layer32of palladium (Pd) and a third conductive layer33of gold (Au) are sequentially formed thereon by electroless plating.

The thickness of the mounting terminal12as viewed from a surface of an insulating protective layer16is desirably 15 micrometers or less, and more preferably 10 micrometers or less, in order to reduce a mounting thickness of the semiconductor device1. For example, such a thickness can be realized with the thickness of the first conductive layer31of approximately 8 micrometers and the thickness of the second conductive layer32and the third conductive layer33of approximately 0.05 micrometers.

Forming the mounting terminal12in this way can facilitate a control of the thickness of the mounting terminal in a smaller number of steps than that in the case of using the method according to steps 1 to 7.

In a semiconductor device1bshown inFIG. 6(b), a mounting terminal12is formed by a method different from the method according to steps 1 to 7. First, a sputtering process using high frequency power is performed as pretreatment to remove an oxide film or the like on the surface of a pad11. Thereafter, as in step 2, a seed layer22of titanium (Ti), copper (Cu), or the like is formed by sputtering or the like. A first conductive layer41of nickel (Ni) is formed thereon by electroplating. A second conductive layer42of nickel (Ni), a third conductive layer43of palladium (Pd), and a fourth conductive layer44of gold (Au) are sequentially formed on the first conductive layer41by electroless plating. Then, as in step 7, the exposed seed layer22is removed by etching.

The thickness of the mounting terminal12as viewed from a surface of an insulating protective layer16is desirably 15 micrometers or less, and more preferably 10 micrometers or less, in order to reduce a mounting thickness of the semiconductor device1. For example, such a thickness can be realized with the thickness of the first conductive layer41of approximately 7 micrometers, the thickness of the second conductive layer42of 1 micrometer, and the thickness of the third conductive layer43and the fourth conductive layer44of approximately 0.05 micrometers.

Forming the mounting terminal12in this way can facilitate a control of the thickness of the mounting terminal even if electroless plating cannot be directly performed on the pads11.

Note that the third conductive layer43may be omitted.

Although the embodiment and modifications of various types have been described above, the present invention is not limited to these. Other embodiments contemplated within the scope of the technical idea of the present invention are also included within the scope of the present invention.

The disclosure of the following priority application is herein incorporated by reference:Japanese Patent Application No. 2017-106608 (filed on May 30, 2017)

REFERENCE SIGNS LIST