Semiconductor device with increased number of external connection electrodes

The semiconductor device of the present invention has a semiconductor substrate having a top surface of a quadrangular shape on which a plurality of connection pads are formed, an insulation film formed on the semiconductor substrate except the connection pads, and a plurality of external connection electrodes formed on the insulation film so as to be connected to the connection pads. The plurality of external connection electrodes constitute at least a first group of external connection electrodes which are arranged on first lines running along each of the two diagonal lines of the semiconductor substrate and second group of external connection electrodes which are arranged on second lines running along the first lines outside the first lines as seen from the diagonal lines.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a semiconductor device, and particularly relates to a semiconductor device in which multiple external connection electrodes can be arranged.

2. Description of the Related Art

There conventionally exists a so-called CSP (Chip Size Package) semiconductor device. The CSP is constructed on a semiconductor substrate on which a plurality of connection pads are formed, and wires are laid on the connection pads via an insulation film so as to be connected to the connection pads. Columnar electrodes are formed on the connection pad portions of the wires and a sealing film is formed on the wires and the insulation film in a manner that the top surface of the sealing film constitutes the same surface as the top surfaces of the columnar electrodes (see, for example, Unexamined Japanese Patent Application KOKAI Publication No. 2000-22052, FIG. 8).

There is another type of conventional semiconductor device which has solder balls as external connection terminals outside the range of the semiconductor substrate included in the device. In this device, a semiconductor substrate having a plurality of connection pads thereon is formed on a base plate, and an insulation layer is formed on the base plate portion that appears around the semiconductor substrate. An upper insulation film is formed on the semiconductor substrate and the insulation layer, and upper wires are provided on the upper insulation film so as to be connected to the connection pads on the semiconductor substrate. The portions other than the connection pad portions of the upper wires are covered with an overcoat film, and solder balls are formed on the connection pad portions of the upper wires (see, for example, Unexamined Japanese Patent Application KOKAI Publication No. 2003-298005).

It is now possible that the semiconductor device disclosed in Unexamined Japanese Patent Application KOKAI Publication No. 2000-22052 (the semiconductor device will hereinafter be referred to as semiconductor element) having the columnar electrodes be formed on the base plate disclosed in the Unexamined Japanese Patent Application KOKAI Publication No. 2003-298005 instead of the semiconductor substrate disclosed therein. To be more specific, it is possible that the semiconductor element having the columnar electrodes be formed on the base plate, an insulation layer be formed on the base plate portion that appears around the semiconductor element, an upper insulation film be formed on the semiconductor element and the insulation layer, upper wires are provided on the upper insulation film so as to be connected to the columnar electrodes of the semiconductor element, the portions other than the connection pad portions of the upper wires be covered with an overcoat film, and solder balls be formed on the connection pad portions of the upper wires.

In a case where the diameter of the columnar electrode is 120 μm, the state-of-the-art manufacture techniques tolerate about 200 μm as the limit of the arranging pitch for the columnar electrodes, and about 70 μm as the limit of the arranging pitch for the upper wires (wire width being about 35 μm and wire interval being about 35 μm). In this case, the interval between the columnar electrodes having the diameter of 120 μm and arranged with the arranging pitch of 200 μm is 80 μm, and therefore the number of upper wires having the wire width of 35 μm that can be arranged on the upper insulation film within the interval of 80 μm is 1.

If the largest number of columnar electrodes possible under the above-described conditions are arranged on the circumferential region of a semiconductor substrate having the size of 5 mm×5 mm, the semiconductor substrate will be as shown inFIG. 19. That is, in a case where a semiconductor substrate41is a square each side of which has a length of 5 mm and columnar electrodes42having a diameter of 120 μm are arranged along each side with an arranging pitch of 200 μm, the number of columnar electrodes42is 24 according to a calculation “(5000÷200)−1=24” and the total number thereof along the four sides is 92 according to a calculation “(24−1)×4=92”. That is, the total number of columnar electrodes42that are arranged for the first round along the four sides of the semiconductor substrate41is 92.

Further, since upper wires44can be arranged on the upper insulation film43within the intervals between the respective 92 columnar electrodes42arranged along the four sides on the basis of one wire for each interval as shown inFIG. 20, further columnar electrodes42can be arranged inside and along the 92 columnar electrodes42arranged along the four sides as shown inFIG. 19. In this case, the number of the second round of columnar electrodes42arranged along the first round of columnar electrodes42is 22 per side, smaller by 2 than the number of columnar electrode42arranged outside (first round). That is, the total number of the second round of columnar electrodes42arranged along the four sides of the semiconductor substrate41is 84 according to a calculation “(22−1)×4=84”. Further, since there occur 8 intervals in which no wire is arranged between the columnar electrodes42as shown inFIG. 20when the columnar electrodes42are arranged two rounds as described above, 8 more columnar electrodes42can be arranged for the third round inside the 84 columnar electrodes42arranged for the second round. As a result, in the conventional structure in which the columnar electrodes42are arranged as shown inFIG. 19andFIG. 20, the total number of columnar electrodes42is 184 according to a calculation “(92+84+8)=184”.

SUMMARY OF THE INVENTION

As described above, the number of columnar electrodes42that can be arranged in a semiconductor device having the above-described columnar electrode arrangement is limited to 184 at the most, and a larger number of columnar electrodes42than that cannot be arranged.

It is therefore an object of the present invention to provide a semiconductor device in which multiple external connection electrodes can be arranged.

The semiconductor device of the present invention has a semiconductor substrate having a top surface of a quadrangular shape on which a plurality of connection pads are formed, an insulation film formed on the semiconductor substrate except the connection pads, and a plurality of external connection electrodes formed on the insulation film so as to be connected to the connection pads. The plurality of external connection electrodes constitute at least a first group of external connection electrodes which are arranged on first lines running along each of the two diagonal lines of the semiconductor substrate and a second group of external connection electrodes which are arranged on second lines running along the first lines outside the first lines as seen from the diagonal lines.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

FIG. 1shows a top view of the principal part of a semiconductor device as one embodiment of the present invention.FIG. 2shows a top view of a semiconductor element included in the semiconductor device shown inFIG. 1.FIG. 3shows a vertical cross section of a sample part of the semiconductor device shown inFIG. 1. Note that the dimensions of each component shown are not identical inFIG. 1,FIG. 2, andFIG. 3for the illustrative purposes. First, with reference toFIG. 3, the semiconductor device comprises a base plate1made of an epoxy resin permeated into a glass fabric base or the like and having a square shape as seen from the top.

The lower surface of a semiconductor element2having a square shape as seen from the top which is substantially smaller in size than the square shape of the base plate1is adhered, via an adhesive layer made of a die bond material, to the central region of the upper surface of the base plate1. In this case, the semiconductor element2comprises wires11, columnar electrodes12, and a sealing film13which are to be described later, and is generally called CSP. The semiconductor element2according to the present invention is particularly called wafer level CSP (W-CSP) because it is obtained by dicing a silicon wafer on which the wires11, the columnar electrodes12, and the sealing film13have been formed, as will be described later. The configuration of the semiconductor element2will now be explained.

The semiconductor element2comprises a silicon substrate (semiconductor substrate)4. The lower surface of the silicon substrate4is adhered to the upper surface of the base plate1via the adhesive layer3. An integrated circuit (unillustrated) having a specific function is formed on the upper surface of the silicon substrate4, and a plurality of connection pads5made of aluminum metal or the like are formed on the circumferential region of the upper surface of the silicon substrate4so as to be connected to the integrated circuit. An insulation film6made of silicon oxide or the like is formed on the upper surface of the silicon substrate4except the central regions of the connection pads5. The central regions of the connection pads5are exposed through openings7provided in the insulation film6.

A protection film (insulation film)8made of an epoxy resin, a polyimide resin, or the like is formed on the upper surface of the insulation film6. In this case, openings9are formed in the portions of the protection film8corresponding to the openings7of the insulation film6. A base metal layer10made of copper or the like is formed on the upper surface of the protection film8. Wires11made of copper are formed on the entire upper surface of the base metal layer10. One end portion of the wire11including the corresponding portion of the base metal layer10is connected to connection pad5through both the openings7and9.

Columnar electrodes (external connection electrodes)12made of copper are formed on the upper surfaces of the connection pad portions of the wires11. A sealing film13made of an epoxy resin, a polyimide resin, or the like is formed on the upper surface of the protection film8including the upper surfaces of the wires11in a manner that the upper surface of sealing film13constitutes the same surface as the upper surfaces of the columnar electrodes12. As described above, the semiconductor element2called W-CSP is formed of the silicon substrate4, the connection pads5, the insulation film6, the protection film8, the wires11, the columnar electrodes12, and the sealing film13.

A quadrangular-frame-like insulation layer14is formed on the upper surface of the base plate1around the semiconductor element2in a manner that the upper surface of the insulation layer14constitutes almost the same surface as the upper surface of the semiconductor element2. The insulation layer14is made of a thermosetting resin such as an epoxy resin, etc., or a thermosetting resin mixed with a reinforcing material such as silica filler, etc.

An upper insulation film15is formed on the upper surfaces of the semiconductor element2and insulation layer14in a manner that the upper surface thereof is flattened.

The upper insulation film15is a so-called buildup material used for a buildup substrate, and made of a thermosetting resin such as an epoxy resin, etc. mixed with a reinforcing material such as silica filler.

Openings16are formed in the upper insulation film15in the portions corresponding to the central regions of the upper surfaces of the columnar electrodes12. An upper base metal layer17made of copper or the like is formed on the upper surface of the upper insulation film15. Upper wires18made of copper are formed on the entire upper surface of the upper base metal layer17. One end portion of the upper wire18including the corresponding portion of the upper base metal layer17is connected to the upper surface of the columnar electrode12through the opening16in the upper insulation film15.

An overcoat film19made of solder resist or the like is formed on the upper surface of the upper insulation film15and the upper surfaces of the upper wires18. Openings20are formed in the overcoat film19in the portions corresponding to the connection pad portions of the upper wires18. Solder balls21are formed in and above the openings20so as to be connected to the connection pad portions of the upper wires18.

In a case where the diameter of the columnar electrode12is 120 μm, the state-of-the-art manufacture techniques tolerate about 200 μm as the limit of the arranging pitch for the columnar electrodes12, and about 70 μm as the limit of the arranging pitch for the upper wires18(wire width being about 35 μm and wire interval being about 35 μm). In this case, the interval between the columnar electrodes12having the diameter of 120 μm and arranged with the arranging pitch of 200 μm is 80 μm, and therefore the number of upper wires18having the wire width of 35 μm that can be arranged on the upper surface of the upper insulation film15within the interval of 80 μm is 1. Note that the diameter of the opening16in the upper insulation film15is about 95 μm.

If the largest number of columnar electrodes12possible under the above-described conditions are arranged (aligned) on the silicon substrate4having the size of 5 mm×5 mm on both sides of each of the two diagonal lines of the silicon substrate4in two lines on each side with predetermined pitches for the respective lines, the silicon substrate4will be as shown inFIG. 2. Here, lines that are parallel with the diagonal lines4aand apart therefrom by 100 μm (i.e., ½ of the arranging pitch of 200 μm for the columnar electrodes12) are referred to as first lines. Lines that are parallel with the first line and apart therefrom by 200 μm (i.e., the same as the arranging pitch for the columnar electrodes12) are referred to as second lines. The largest number of columnar electrodes12possible are arranged on the first lines with the arranging pitch of 200 μm, and the largest number of columnar electrodes12possible having the diameter of 120 μm are arranged on the second lines with the arranging pitch of 200 μm.

In this case, since the length of the diagonal lines4aof the silicon substrate4is about 7 mm, 32 columnar electrodes12are arranged on each first line. The total number of columnar electrodes12on the four first lines is 124 according to a calculation “32×4−4=124”. There can be arranged 26 columnar electrodes12on each second line, and 104 columnar electrodes12on the four second lines in total according to a calculation “26×4=104”. The grand total is 228 according to a calculation “124+104=228”. As compared with the case shown inFIG. 19where the columnar electrodes42are arranged along the four sides of the semiconductor substrate (silicon substrate)41, 44 (=228−184) more columnar electrodes12can be arranged in case of the arrangement shown inFIG. 1andFIG. 2.

As shown inFIG. 1, the upper wires18connected to the columnar electrodes12arranged on the first lines (arranged more closely to the diagonal lines4a) are basically arranged on the upper insulation film15within the intervals between the columnar electrodes12arranged on the second lines (arranged outside the columnar electrodes12arranged more closely to the diagonal lines4a) one wire in each interval.

In this case, the columnar electrodes12arranged on the first lines and the outer columnar electrodes12arranged on the second lines are basically arranged at positions where the line connecting the both is perpendicular to the diagonal line4a. The upper wires18connected to the columnar electrodes12arranged on the first lines basically have linear portions that are perpendicular to the diagonal lines4abetween the columnar electrodes12arranged on the second lines. The upper wires18connected to the columnar electrodes12arranged on the first lines and the upper wires18connected to the columnar electrodes12arranged on the second lines are basically extended perpendicularly to the four sides of the silicon substrate4outside the columnar electrodes12arranged on the second lines.

The size of the base plate1is formed larger by a certain degree than the size of the semiconductor element2, in order to make the range of the region on which the solder balls21are to be arranged larger by a certain degree than the range of the semiconductor element2in accordance with increase in the number of connection pads5on the silicon substrate4, thereby to make the size and pitch of the connection pad portions of the upper wires18(the portions inside the openings20in the overcoat film19) larger than those of the columnar electrodes12. In this case, since the upper wires18are arranged over the region corresponding to the semiconductor element2entirely as shown inFIG. 1, the solder balls21are arranged only on the locations corresponding to the insulation layer14formed on the upper surface of the base plate1around the semiconductor element2.

Next, one example of the method for manufacturing the present semiconductor device will be explained. First, one example of the method for manufacturing the semiconductor element2will be explained. First, as shown inFIG. 4, a silicon substrate (semiconductor substrate)4in the form of a wafer is prepared, on which connection pads5made of aluminum metal or the like, an insulation film6made of silicon oxide or the like, and a protection film8made of an epoxy resin, a polyimide resin, or the like are formed wherein the central regions of the connection pads5are exposed through opening7formed in the insulation film6and through openings9formed in the protection film8. An integrated circuit having a specific function is formed on each region where a semiconductor element is to be formed on the silicon substrate4in the form of a wafer. The connection pads5are electrically connected to the integrated circuits formed on the corresponding regions.

Next, as shown inFIG. 5, a base metal layer10is formed on the entire upper surface of the protection film8including the upper surfaces of the connection pads5exposed through the openings7and9. In this case, the base metal layer10may be a single copper layer formed by electroless plating or a single copper layer formed by sputtering. Or, the base metal layer10may be a dual-layer including a thin film of titanium or the like formed by sputtering and a copper layer formed thereon by sputtering.

Next, a pattern of a plating resist film31is formed on the upper surface of the base metal layer10. In this case, openings32are formed in the plating resist film31in the portions corresponding to where wires11are to be formed. Wires11are then formed on the upper surface of the base metal layer10in the openings32of the plating resist film31, by applying electrolytic copper plating using the base metal layer10as plating current paths. The plating resist film31is then separated.

Next, as shown inFIG. 6, a pattern of a plating resist film33is formed on the upper surface of the base metal layer10and the upper surfaces of the wires11. In this case, openings34are formed in the plating resist film33in the portions corresponding to where columnar electrodes12are to be formed. Columnar electrodes12are formed on the upper surfaces of the connection pad portions of the wires111in the openings34of the plating resist film33, by applying electrolytic copper plating using the base metal layer10as plating current paths. The plating resist film33is then separated, and unnecessary portions of the base metal layer10are etched out by using the wires11as a mask. As a result, the base metal layer10remains only under the wires11as shown inFIG. 7.

Next, as shown inFIG. 8, a sealing film13made of an epoxy resin, a polyimide resin, or the like is formed on the entire surfaces of the columnar electrodes12, wires11, and protection film8by screen printing, spin coating, die coating, or the like, in a manner that the thickness of the sealing film13is higher than the height of the columnar electrodes12Therefore, in this state, the upper surfaces of the columnar electrodes12are covered with the sealing film13.

Next, the upper surface of the sealing film13and the upper surfaces of the columnar electrodes12are adequately polished to expose the upper surfaces of the columnar electrodes12and thereby to flatten the exposed upper surfaces of the columnar electrodes12and the upper surface of the sealing film13. The upper surfaces of the columnar electrodes12are adequately polished because there is unevenness in the height of the columnar electrodes12formed by electrolytic plating. It is necessary to eliminate the unevenness and make the height of the columnar electrodes12uniform.

Next, as shown inFIG. 10, an adhesive layer3is adhered to the entire lower surface of the silicon substrate4. The adhesive layer3is made of a die bond material such as an epoxy resin, a polyimide resin, or the like, and is fixed on the silicon substrate4in a semi-hardened state by applying heat and pressure thereto. The adhesive layer3fixed on the silicon substrate4is adhered to a dicing tape (unillustrated) and subjected to a dicing step shown inFIG. 11. After the dicing step, a plurality of semiconductor elements2in each of which the adhesive layer3is present on the lower surface of the silicon substrate4as shown inFIG. 3can be obtained by separation from the dicing tape.

Since the semiconductor element2obtained in the above-described manner has the adhesive layer3on the lower surface of the silicon substrate4, there is no need of doing the very bothersome work of individually adhering an adhesive layer to the lower surface of the silicon substrate4of all the semiconductor elements2after the dicing step. The work of separating the dicing tape after the dicing step is much easier than the work of individually adhering an adhesive layer to the lower surface of the silicon substrate4of all the semiconductor substrates2after the dicing step.

Next, one example of manufacturing a semiconductor device shown inFIG. 3using the semiconductor element2obtained in the above-described manner will be explained. First, as shown inFIG. 12, a base plate1is prepared which has an area allowing the completed semiconductor device shown inFIG. 3to be formed plurally. The base plate1has, for example, a quadrangular shape as seen from the top, although is not limited to this shape. Next, the adhesive layer3adhered to the lower surface of the silicon substrate4of each semiconductor element2is fully hardened by application of heat and pressure, and adhered to the upper surface of the base plate1at predetermined positions plurally.

Next, as shown inFIG. 13, an insulation layer forming layer14ais formed on the upper surface of the base plate1appearing around the semiconductor element2by, for example, screen printing, spin coating, etc. The insulation layer forming layer14ais made of, for example, a thermosetting resin such as an epoxy resin, etc. or a thermosetting resin mixed with a reinforcing material such as silica filler, etc.

Next, an upper insulation film forming sheet15ais formed on the upper surfaces of the semiconductor element2and insulation layer forming layer14a. The upper insulation film forming sheet15amay be made of a thermosetting resin such as an epoxy resin, etc. which is semi-hardened after mixed with silica filler.

Next, as shown inFIG. 14, the insulation layer forming layer14aand the upper insulation film forming sheet15aare heated and pressurized from both the above and beneath by using a pair of heating/pressurizing plates35and36. As a result, an insulation layer14is formed on the upper surface of the base plate1appearing around the semiconductor element2and an upper insulation film15is formed on the upper surfaces of the semiconductor element2and insulation layer14. In this case, the upper surface of the upper insulation film15becomes a flat surface because it is pressed by the lower surface of the upper heating/pressurizing plate35. Therefore, a polishing step for flattening the upper surface of the upper insulation film15becomes unnecessary.

Next, as shown inFIG. 15, openings16are formed in the upper insulation film15in the portions corresponding to the central regions of the upper surfaces of the columnar electrodes12by applying laser treatment for irradiating laser beams. Next, epoxy smears or the like that occur in the openings16and the like are removed by applying desmear treatment, if such smears do occur. Next, as shown inFIG. 16, an upper base metal layer17is formed on the entire upper surface of the upper insulation film15including the upper surfaces of the columnar electrodes12exposed through the openings16by electroless copper plating. A pattern of a plating resist film37is then formed on the upper surface of the upper base metal layer17. In this case, openings38are formed in the plating resist film37in the portions corresponding to where upper wires18are to be formed.

Next, upper wires18are formed on the upper surface of the upper base metal layer17in the openings38formed in the plating resist film37, by applying electrolytic copper plating using the upper base metal layer17as plating current paths. Next, the plating resist film37is separated and unnecessary portions of the upper base metal layer17are etched out by using the upper wires18as a mask. As a result, the upper base metal layer17remains only under the upper wires18as shown inFIG. 17.

Next, as shown inFIG. 18, an overcoat film19made of solder resist or the like is formed on the entire surfaces of the upper wires18and upper insulation film15by screen printing or the like. In this case, openings20are formed in the overcoat film19in the portions corresponding to the connection pad portions of the upper wires18. Next, solder balls21are formed in and above the openings20so as to be connected to the connection pad portions of the upper wires18. Next, the overcoat film19, the upper insulation film15, the insulation layer14, and the base plate1are diced between any adjacent two semiconductor elements2. As a result, a plurality of the semiconductor device shown inFIG. 3are obtained.

As described above, according to the above-described manufacturing method, a plurality of semiconductor devices are obtained by arranging a plurality of semiconductor elements2on the base plate1, forming the upper wires18and the solder balls21simultaneously on the plurality of semiconductor elements2, and dicing them from one another. Therefore, the manufacturing process can be simplified. Further, since the plurality of semiconductor elements2can be carried simultaneously with the base plate1in and after the manufacturing step shown inFIG. 14, this also contributes to simplification of the manufacturing process.

Another Embodiment

In the above-described embodiment, the semiconductor element2comprises the columnar electrodes12as external connection electrodes. The present invention is not limited to this, but the semiconductor element2may be configured in a manner that it comprises neither the columnar electrodes12nor the sealing film13, but comprises an overcoat film made of solder resist or the like that covers the wires11except their connection pad portions, and upper connection pads each having a base metal layer thereunder are formed as external connection electrodes on the connection pad portions of the wires11and on the overcoat film near the connection pad portions. Further, the silicon substrate4of the semiconductor element2and the base plate1may be rectangular.

According to the present invention, when a plurality of external connection electrodes formed of columnar electrodes or the like are arranged in plural lines along the diagonal lines of a semiconductor substrate having a quadrangular shape as seen from the top, a larger number of external connection electrodes formed of columnar electrodes or the like can be arranged than in a case where such external connection electrodes are arranged along the four sides of the semiconductor substrate.

This application is based on Japanese Patent Application No. 2004-72265 filed on May 15, 2004 and including specification, claims, drawings and summary. The disclosure of the above Japanese Patent Application is incorporated herein by reference in its entirety.