Testing structure and display device including the same

A display device is provided. The display device includes: a substrate including a display area including pixels at which an image is displayed and a peripheral area at which the image is not displayed, the peripheral area disposed outside the display area. In the peripheral area, the display device further includes: a plurality of thin film transistors connected to the pixels and with which operation of the pixels is tested, the thin film transistors including gate electrodes arranged separated from each other on the substrate; and a bridge wiring electrically connecting adjacent gate electrodes of the plurality of thin film transistors to each other.

This application claims priority to Korean Patent Application No. 10-2017-0104143, filed on Aug. 17, 2017, and all the benefits accruing therefrom under 35 U.S.C. § 119, the content of which in its entirety is herein incorporated by reference.

BACKGROUND

One or more embodiments relate to a display device, and more particularly, to a display device which may minimize occurrence of defect in a circuit during a manufacturing process.

2. Description of the Related Art

Generally, a display device includes a display area, and plural pixels are arranged inside the display area. When defect occurs in a circuit of the display device, the quality of an image produced at the pixels by the display device may deteriorate. Therefore, minimizing occurrence of a defect in a circuit or minimizing a defect occurrence rate of a circuit during a manufacturing process is desired.

However, in the case of a display device and manufacturing method thereof according to a related art, a relatively large number of defects occur in a circuit during a manufacturing process.

SUMMARY

One or more embodiments include a display device which may minimize occurrence of defect in a circuit during a manufacturing process.

According to one or more embodiments, a display device includes: a substrate including a display area including pixels at which an image is displayed and a peripheral area at which the image is not displayed, the peripheral area disposed outside the display area; and in the peripheral area, a plurality of thin film transistors electrically connected to the pixels in the display area and with which operation of the pixels is tested, the thin film transistors including gate electrodes arranged separated from each other on the substrate; and a bridge wiring electrically connecting adjacent gate electrodes of the plurality of thin film transistors to each other.

Each of the plurality of thin film transistors may include a source electrode and a drain electrode, and the bridge wiring may include a same material as that of the source electrodes and the drain electrodes.

Each of the plurality of thin film transistors may include a source electrode and a drain electrode, and the bridge wiring may be in a same layer as the source electrodes and the drain electrodes.

The gate electrodes and the bridge wiring may be arranged on a virtual line extended in one direction.

The bridge wiring may be a conductive layer which is formed as one body and connect at least three gate electrodes of at least three sequential thin film transistors to each other.

The at least three gate electrodes of the at least three thin film transistors and the conductive layer formed as one body may be are arranged on a virtual line extending in one direction.

The display device may further include an insulating layer between the gate electrodes of the plurality of thin film transistors and the bridge wiring, and the bridge wiring may contact the gate electrodes through contact holes in the insulating layer.

The display device may further include a plurality of data lines disposed in the display area and electrically connected to the pixels, the plurality of data lines extending from the display area to the peripheral area, and each of the plurality of thin film transistors may be electrically connected to a corresponding data line among the plurality of data lines.

Each of the plurality of thin film transistors may include a source electrode and a drain electrode, and the plurality of data lines extended from the display area to the peripheral area may include a same material as that of the source electrodes and the drain electrodes.

Each of the plurality of thin film transistors may include a source electrode and a drain electrode, and the plurality of data lines may comprise a same material as that of the source electrodes and the drain electrodes of the plurality of thin film transistors.

The display device may further include connection wirings connecting the plurality of data lines to corresponding one of the plurality of thin film transistors.

The connection wirings may include a same material as that of the gate electrodes.

The connection wirings may be arranged in in a same layer as the gate electrodes of the plurality of thin film transistors.

The display device may further include a plurality of output pads each of which locates over and contacts corresponding one of the connection wirings.

The plurality of output pads may comprise a same material as that of the source electrodes and the drain electrodes of the plurality of thin film transistors.

The plurality of output pads may be arranged in a same layer as the source electrodes and the drain electrodes are arranged.

The display device may further include a plurality of input pads arranged at a side of the plurality of thin film transistors. The side may be opposite to that at which the plurality of output pads are arranged.

The plurality of input pads may include a same material as that of the source electrodes and the drain electrodes.

The plurality of input pads may be arranged in a same layer as the source electrodes and the drain electrodes of the plurality of thin film transistors.

The plurality of input pads may extend in a direction away from the plurality of thin film transistors, and at respective ends of the plurality of input pads closest to the plurality of thin film transistors, the display device may further include a step difference adjustor arranged between the substrate and each of the plurality of input pads.

The step difference adjustor may include a same material as that of the gate electrodes.

The step difference adjustor may be arranged in a same layer as the gate electrodes of the plurality of thin film transistors.

The display device may further include a driving chip, the driving chip including input terminals electrically connected to the input pads and output terminals electrically connected to the output pads.

The display device may further include a printed circuit board. The plurality of input pads may extend in a direction away from the plurality of thin film transistors, and at respective ends of the plurality of input pads furthest from the plurality of thin film transistors, the printed circuit board may be electrically connected to the plurality of input pads.

According to one or more embodiments, a display device includes: a substrate including a display area including pixels at which an image is displayed and a peripheral area at which the image is not displayed, the peripheral area disposed outside the display area; and in the peripheral area, the display device further includes: a plurality of electrode pairs connected to the pixels in the display area, each of the plurality of electrode pairs including a source electrode and a drain electrode spaced apart from each other in a first direction; and a gate line lengthwise extending in a second direction crossing the first direction, the gate line passing between the source electrode and the drain electrode of each of the plurality of electrode pairs. The gate line passing between the source electrode and the drain electrode of each of the plurality of electrode pairs includes: first conductive layers spaced apart from each other in the second direction, and second conductive layers alternately arranged with the first conductive layers along the second direction.

The display device may further include a plurality of semiconductor layers connected to the plurality of electrode pairs.

The gate line passing between the source electrode and the drain electrode of each of the plurality of electrode pairs may pass over the plurality of semiconductor layers.

The first conductive layers may be arranged in a layer different from a layer in which the second conductive layers are arranged.

The first conductive layers spaced apart from each other may be electrically connected to each other by the second conductive layers.

According to one or more embodiment, a display device which may minimize occurrence of defect in a circuit during a manufacturing process may be implemented. The scope of the present disclosure is not limited by this effect.

DETAILED DESCRIPTION

As the disclosure allows for various changes and numerous embodiments, example embodiments will be illustrated in the drawings and described in detail in the written description. An effect and a characteristic of the disclosure, and a method of accomplishing these will be apparent when referring to embodiments described with reference to the drawings. This disclosure may, however, be embodied in many different forms and should not be construed as limited to the example embodiments set forth herein.

Hereinafter, the disclosure will be described more fully with reference to the accompanying drawings, in which example embodiments of the disclosure are shown. When description is made with reference to the drawings, like reference numerals in the drawings denote like or corresponding elements, and repeated description thereof will be omitted.

It will be understood that when a component, such as a layer, a film, a region, or a plate, is referred to as being related to another component such as being “on” another component, the component can be directly on the other component or intervening components may be present thereon. In contrast, when a component, such as a layer, a film, a region, or a plate, is referred to as being related to another component such as being “directly on” another component, no intervening components are present.

FIG. 1is a top plan view of an exemplary embodiment of a portion of a display device in a manufacturing process according to the invention,FIG. 2is an enlarged top plan view of an exemplary embodiment of a portion A ofFIG. 1,FIG. 3is a cross-sectional view taken along line III-III ofFIG. 2, andFIG. 4is a cross-sectional view taken along line IV-IV ofFIG. 2.

As illustrated inFIG. 1, the display device according to the present embodiment includes a display area DA in which a plurality of pixels are arranged to generate and display an image, and a peripheral area PA outside the display area DA and at which the image is not displayed. According to this, a substrate100of the display device may be understood to include the display area DA and the peripheral area PA. The peripheral area PA includes a pad area PADA, which is an area at which various electronic devices or printed circuit boards, etc. are electrically attached to the substrate100and/or components thereof. The substrate100and layers thereon may be otherwise referred to as a display substrate of the display device, and more particularly, a display substrate of a display panel which generates and displays an images with light by control/driving signals provided thereto from other constituent elements of the display device.

FIG. 1may be understood as a top plan view of components and elements of a display device such as a substrate, etc. during a manufacturing process of the display device. In a final display device or an electronic apparatus such as a smartphone including the display device, to minimize the planar area of the peripheral area PA recognized by a user, a portion of the substrate100, etc. may be bent. In an exemplary embodiment, for example, the peripheral area PA may include a bending area, and the bending area may be arranged between the pad area PADA and the display area DA in the top plan view. In this case, the substrate100may be bent in the bending area such that at least a portion of the pad area PADA overlaps the display area DA. In this case, the bending direction is determined such that the pad area PADA does not hide or block the display area DA and is arranged behind the display area DA in a direction away from the user. Therefore, a user recognizes that the display area DA occupies most of the display device from a viewing side thereof.

The substrate100may include various materials having flexible or bendable characteristics, e.g., polymer resins such as polyethersulphone (“PES”), polyacrylate, polyetherimide (“PEI”), polyethylene napthalate (“PEN”), polyethyleneterephthalate (“PET”), polyphenylene sulfide (“PPS”), polyarylate (“PAR”), polyimide (“PI”), polycarbonate (“PC”) or cellulose acetate propionate (“CAP”). The substrate100may be modified variously. In an exemplary embodiment, for example, the substrate100may have a multi-layered structure including two layers among the above polymer resins and a barrier layer including an inorganic material (such as a silicon oxide, a silicon nitride, a silicon oxynitride, etc.). Furthermore, in the case where the substrate100is not bent, the substrate100may include glass, etc.

The periphery of the display area DA may define a shape similar to a rectangle or a square on the whole. However, as illustrated inFIG. 1, the periphery of the display area DA may not have a sharp or linear edge portion. Specifically, the display area DA may include a first edge E1and a second edge E2facing each other, a third edge E3and a fourth edge E4facing each other and arranged between the first and second edges E1and E2. The pad area PADA is adjacent to the fourth edge E4among the first edge E1to the fourth edge E4. In this case, a portion of the overall outer edge of the display area DA which connects the first edge E1to the fourth edge E4may have a rounded shape in the top plan view. A portion of the overall outer edge of the display area DA which connects the second edge E2to the fourth edge E4may have a rounded shape and other portions may have a rounded shape.

As illustrated inFIG. 2, the display device according to the present embodiment includes a thin film transistor TT provided in plurality arranged in the peripheral area PA, specifically, the pad area PADA. The plurality of thin film transistors TT may be connected to the pixels of the display area DA. The plurality of thin film transistors TT are switching elements for testing or inspecting the display device during a manufacturing process to determine whether pixels of the display area DA normally operate.

As illustrated inFIGS. 2 to 4, each of the thin film transistors TT includes a semiconductor layer120including amorphous silicon, polycrystalline silicon or an organic semiconductor material, a gate electrode141, a source electrode161and a drain electrode162. To secure insulation between the semiconductor layer120and the gate electrode141, a gate insulating layer130including an inorganic material such as a silicon oxide, a silicon nitride and/or a silicon oxynitride may be arranged between the semiconductor layer120and the gate electrode141. Also, an interlayer insulating layer150including an inorganic material such as a silicon oxide, a silicon nitride and/or a silicon oxynitride may be arranged on the gate electrode141. The source electrode161and the drain electrode162may be arranged on the interlayer insulating layer150. In an exemplary embodiment of a method of manufacturing a display device, the insulating layer including an inorganic material may be formed by chemical vapor deposition (“CVD”) or atomic layer deposition (“ALD”). The same is true of embodiments and modified examples below.

A buffer layer110including an inorganic material such as a silicon oxide, a silicon nitride and/or a silicon oxynitride may be arranged between the thin film transistor TT and the substrate100. The buffer layer110may increase flatness of the upper surface of the substrate100or minimize or effectively prevent penetration of impurities from the substrate100, etc. to the semiconductor layer120of the thin film transistor TT such as from outside thereof.

The gate electrodes141of the thin film transistors TT may be electrically connected to each other by a bridge wiring163provided in plurality. That is, among individual layers disposed on the substrate100, the bridge wirings163are arranged in a layer different from a layer in which the gate electrodes141are arranged to electrically connect the gate electrodes141spaced apart from each other to each other.FIG. 4illustrates that the bridge wiring163electrically connects the gate electrodes141spaced apart from each other by directly contacting the gate electrodes141at contact holes of the interlayer insulating layer150, which is an insulating layer between the bridge wiring163and the gate electrode141. The same is true of embodiments and modified examples below. Therefore, as illustrated inFIG. 2, the gate electrodes141and the bridge wirings163may be arranged on a virtual straight line (extending in an x-axis direction). Each of the gate electrodes141and the bridge wirings163are a discrete (e.g., island) member.

Each of the thin film transistors TT includes the source electrode161and the drain electrode162. The bridge wirings163may include the same material as that of the source electrode161and the drain electrode162, for example, metal such as Ti or Al, and have a single-layered or multi-layered structure. Alternatively, among individual layers disposed on the substrate100, the bridge wirings163may be arranged in a layer in which the source electrode161and the source electrode162are arranged. Therefore, the bridge wirings163may be connected to the gate electrodes141therebelow at contact holes in the interlayer insulating layer150.

As illustrated inFIG. 1, a data line DL is provided in plurality each lengthwise extending along the y-axis direction across the display area DA to the peripheral area PA. The data lines DL respectively cross a virtual straight line (extending in an x-axis direction) along which the gate electrodes141and the bridge wirings163lengthwise extends and are arranged. A width of a data line DL and a gate electrode141is defined in a direction perpendicular to the length thereof, e.g., along the y-axis direction. The display device and/or components, layers, etc. thereof are disposed in a plane defined by first and second (e.g., x-axis and y-axis) directions crossing each other. A thickness of the display device and/or components, layers, etc. thereof, is defined in a third direction crossing each of the first and second direction, e.g., a z-axis direction, such as but not limited to being perpendicular thereto.

Each of the thin film transistors TT is electrically connected to a corresponding data line DL among the data lines DL. Therefore, when an electric signal is simultaneously applied to the gate electrodes141of the thin film transistors TT electrically connected to each other to turn the thin film transistors TT on, channels are simultaneously formed in the semiconductor layers120of the thin film transistors TT. When the thin film transistors TT are simultaneously turned on, an electric signal from a test signal line168is transferred to the data lines DL. Therefore, pixels of the display area DA electrically connected to the data lines DL emit light, and operation of the pixels inside the display area DA may be tested to determine whether the pixels are defective.

The gate electrodes141may include, for example, metal such as Mo or Al. In an exemplary embodiment of a manufacturing method of a display device, the gate electrodes141may be formed by a method such as sputtering. Also, after the gate electrodes141are formed, when forming the interlayer insulating layer150covering the gate electrodes141, a method such as plasma enhanced chemical vapor deposition (“PECVD”) or ALD may be used. In this case of forming the interlayer insulating layer150covering the gate electrodes141, charges may be accumulated on the already-formed gate electrodes141. Particularly, in the case of a process forming the insulating layer, etc. by PECVD after forming the gate electrodes141, since plasma is applied, charges may be accumulated on the gate electrodes141during the process.

As described above, the gate electrodes141spaced apart from each other are electrically connected to each other by the bridge wirings163.

A comparative configuration in which the gate electrodes141are not connected by the bridge wirings163, and instead one single long gate line corresponding to the gate electrodes141extends (along an x-axis direction) over the semiconductor layers120of the thin film transistors TT may be considered. However, where the one single long gate line corresponding to the gate electrodes141extends (along an x-axis direction) over the semiconductor layers120of the thin film transistors TT, since the gate line is relatively long, a total amount of charges accumulated on the gate line rapidly increases during a manufacturing process. Also, due to the large amount of accumulated charges, a relatively strong electric field may be generated by a large potential difference between the one single gate line and the semiconductor layers120therebelow. Also, a phenomenon such as insulation destruction (dielectric destruction) is generated at the gate insulating layer130covering the semiconductor layer120by the relatively strong electric field. Therefore, even though the thin film transistors TT are completed by subsequent manufacturing processes, the thin film transistors TT may not properly operate. The improper operation of the thin film transistors TT becomes a cause by which the pixels inside the display area DA cannot be tested by using the thin film transistors TT.

One or more exemplary embodiment of a display device according to the invention may effectively prevent or minimize occurrence of a defect a display device caused from a defective pixel. As described above, since the gate electrodes141of the thin film transistors TT respectively have island shapes spaced apart from each other, the planar area of each gate electrode141is less than that of the above-described one single gate line. Accordingly, even though charges are respectively accumulated on the gate electrodes141during the manufacturing process, an amount of charges respectively accumulated on the gate electrodes141is minimal. Therefore, one or more exemplary embodiment of the display device according to the invention may reduce or effectively prevent the gate insulating layer130, etc. from being damaged due to insulation destruction, etc., and thus effectively prevent or minimize occurrence of a defect of the thin film transistors TT, and further, a defect of the display device.

As described above, the plurality of data lines DL lengthwise extend to the peripheral area PA from across the display area DA. The data lines DL may include the same material as that of the source electrode161and the drain electrode162of the thin film transistors TT, for example, Ti or Al, and have a single-layered or multi-layered structure. Alternatively, the plurality of data lines DL may have a three-story structure of Ti/Al/Ti. Furthermore, the data lines DL may be arranged in a layer in which the source electrode161and the drain electrode162are arranged. Each of the thin film transistors TT is electrically connected to a corresponding data line DL among the data lines DL by a connection wiring143provided in plurality. That is, the connection wirings143connect the data lines DL to the thin film transistors TT.

The connection wirings143may include the same material as that of the gate electrode141, for example, metal such as Mo or Al, and have a single-layered or multi-layered structure. Furthermore, the connection wirings143may be arranged in a same layer in which the gate electrodes141are arranged, among layers disposed on the substrate100. As used herein, elements being in a same layer as each other may also indicate the elements are formed from a same material layer in a method of manufacturing the display device.

A first end of the connection wiring143is connected to the data line DL thereon, at a contact hole formed in the interlayer insulating layer150, and a second end of the connection wiring143opposite to the first end thereof is connected to the drain electrode162of the thin film transistor TT thereon, at a contact hole formed in the interlayer insulating layer150. The source electrodes161of the thin film transistors TT are connected to the test signal line168which lengthwise extends in the x-axis direction. Specifically, the source electrodes161may be formed as one body with the test signal line168.

As illustrated inFIGS. 2 and 3, the display device may further include an output pad165provided in plurality. Each of the output pads165may be arranged on a corresponding connection wiring143among the connection wirings143and may contact the corresponding connection wiring143. Each of the output pads165may include the same material as that of the source electrode161and the drain electrode162of the thin film transistor TT, for example, metal such as Ti or Al and may have a single-layered or multi-layered structure. Alternatively, the output pads165may have a three-story structure of Ti/Al/Ti. Furthermore, the output pads165may be arranged in a same layer in which the source electrode161and the drain electrode162are arranged among layers disposed on the substrate100. Therefore, the output pads165may be connected to the connection wiring143thereunder at a contact hole formed in the interlayer insulating layer150.

An input pad166provided in plurality may be arranged at a side of the thin film transistors TT, which is opposite to the side (+y-axis direction) of the thin film transistors TT at which the output pads165are arranged. Each of the input pads166may include the same material as that of the source electrode161and the drain electrode162of the thin film transistor TT, for example, metal such as Ti or Al and have a single-layered or multi-layered structure. Alternatively, the input pads166may have a three-story structure of Ti/Al/Ti. Furthermore, the input pads166may be arranged in a same layer in which the source electrode161and the drain electrode162are arranged among layers disposed on the substrate100.

The input pads166and the output pads165may be connected to a driving chip180of the display device. The driving chip180includes a body183and an output terminal181provided in plurality and an input terminal182provided in plurality each of which are arranged on opposite sides of the body183. SinceFIG. 3is a cross-sectional view along line III-III, only one output terminal181and one input terminal182of the driving chip180are illustrated, but the driving chip180may include a plurality of output terminals181and a plurality of input terminal182(arranged in the x-axis direction). The driving chip180may be, for example, an integrated circuit (“IC”) chip, etc.

The input pads166on the substrate100are respectively connected to the input terminals182of the driving chip180, and the output pads165on the substrate100are respectively connected to the output terminals181of the driving chip180. Therefore, when the display device is not tested and is actually driven, an electric signal transmitted into the input terminal182of the driving chip180from outside thereof is transferred from the output terminals181of the driving chip180to the data lines DL by way of the output pads165and the connection wirings143on the substrate100, and consequently, may be transferred to the thin film transistors210(seeFIG. 5) of the pixels inside the display area DA.

Information and signals for generating an image to be displayed in the display area DA may be input to the driving chip180through the input terminals182of the driving chip180. For this purpose, the display device may include a printed circuit board190including a plate192and an output terminal191. The input pads166on the substrate100extend in a direction away from the thin film transistors TT toward an edge of the substrate100, and an end portion167of the input pads166furthest away from the thin film transistors TT may be electrically connected to the output terminal191of the printed circuit board190. The printed circuit board190is a constituent element of the display device from which and through which an electric signal such as data signal, control signal, and/or driving signal for generating and displaying an image passes to the display substrate of the display device. The electrical signal for displaying the image passes from the printed circuit board190through the input pad166, the driving chip180, the output pad165and the connection wiring143, without passing through the thin film transistor TT used for testing.

As the input terminals182of the driving chip180are connected to the input pads166on the substrate100, and the output terminals181of the driving chip180are connected to the output pads165on the substrate100, the driving chip180is arranged over the thin film transistors TT which are used as a switching element for testing, as illustrated inFIG. 3. In this case, to stably arrange the driving chip180, a height h1in the z-axis direction from the lower surface of the substrate100to the upper surface of the output pads165is substantially equal to a height h2in the z-axis direction from the lower surface of the substrate100to the upper surface of the input pads166.

For this purpose, since the connection wirings143are arranged below the output pads165on the substrate100, a step difference adjustor145may be arranged below a portion of each of the input pads166at ends thereof closer to the plurality of thin film transistors TT. The step difference adjustor145may include the same material as that of the connection wirings143, that is, the same material as that of the gate electrodes141, for example, metal such as Mo or Al, and have a single-layered or multi-layered structure. Furthermore, the step difference adjustor145may be arranged in a same layer in which the connection wirings143and the gate electrodes141are arranged among layers disposed on the substrate100. Unlike the configuration illustrated inFIGS. 2 and 3, a step difference adjustor145may be arranged below the end portion167of each of the input pads166at ends thereof furthest away from the thin film transistors TT, that is, below the end portion167connected to the output terminal191of the printed circuit board190at the edge portion of the substrate100.

AlthoughFIG. 3illustrates that the input terminals182of the driving chip180directly contact the input pads166, the present disclosure is not limited thereto. In an exemplary embodiment, for example, an anisotropic conductive film, etc. may be arranged between the input terminals182of the driving chip180and the input pads166. This same configuration is also applicable between the output terminals181of the driving chip180and the output pads165on the substrate100and also applicable between the output terminals191of the printed circuit board190and the end portion167of the input pads166on the substrate100at an end thereof furthest away from the thin film transistors TT. This configuration is equally applicable to embodiments and modified examples described below.

FIG. 5is an enlarged cross-sectional view of an exemplary embodiment of a portion inside a display area DA of the display device ofFIG. 1, such as in a pixel thereof. As illustrated inFIG. 5, a display element310and a (display) thin film transistor210which is electrically connected to the display element310may be arranged in the display area DA of the substrate100.FIG. 5illustrates that an organic light-emitting diode (“OLED”) as a display element is arranged in the display area DA. A configuration in which the OLED is electrically connected to the thin film transistor210may mean that a pixel electrode311is electrically connected to the thin film transistor210.

A semiconductor layer211, a gate electrode213, a source electrode215a, and a drain electrode215bof the thin film transistor210inside the display area DA may respectively include the same materials as those of the semiconductor layer120, the gate electrode141, the source electrode161, and the drain electrode162of the thin film transistor TT in the peripheral area PA described above, and may be respectively arranged in the same layers in which the semiconductor layer120, the gate electrode141, the source electrode161, and the drain electrode162are respectively arranged among layers disposed on the substrate100.

A planarization layer170may be arranged on the thin film transistor210. In an exemplary embodiment, for example, as illustrated inFIG. 5, in the case where the OLED is arranged over the thin film transistor210, the planarization layer170may generally planarize the upper portion of the thin film transistor210. The planarization layer170may include an organic material such as acryl, benzocyclobutene (“BCB”) or hexamethyldisiloxane (“HMDSO”). ThoughFIG. 5illustrates that the planarization layer170is a single layer, the planarization layer170may be a multi-layer structure.

The display element310may be arranged on the planarization layer170in the display area DA of the substrate100. The display element310may be, for example, an OLED including the pixel electrode311, an opposite electrode315, and an intermediate layer313arranged between the pixel electrode311and the opposite electrode315and including an emission layer. The pixel electrode311is electrically connected to the thin film transistor210by contacting one of the source electrode215aand the drain electrode215bat an opening formed in the planarization layer170, etc. as illustrated inFIG. 5. The display element310may generate the light used to display an image. The pixel at which the display element310is disposed may generally be an area at which light is generated and/or emitted to display the image.

A pixel-defining layer175may be arranged on the planarization layer170. The pixel-defining layer175defines a pixel by an opening corresponding to each sub-pixel, that is, an opening exposing at least a portion such as a central portion of the pixel electrode311. Also, in the case illustrated inFIG. 5, the pixel-defining layer175prevents an electrical arc, etc. from occurring at an edge of the pixel electrode311by increasing a distance between an edge of the pixel electrode311and the opposite electrode315which is disposed over the pixel electrode311. The pixel-defining layer175may include an organic material such as polyimide or HMDSO.

The intermediate layer313of the OLED may include a relatively low molecular or polymer material. In the case where the intermediate layer313includes a relatively low molecular material, the intermediate layer313may have a structure in which a hole injection layer (“HIL”), a hole transport layer (“HTL”), an emission layer (“EML”), an electron transport layer (“ETL”), an electron injection layer (“EIL”), etc. are stacked in a single or a composite configuration. In an exemplary embodiment of a method of manufacturing a display device, the intermediate layer313may be formed by vacuum evaporation. In the case where the intermediate layer313includes a polymer material, the intermediate layer313may generally have a structure including an HTL and an EML. In this case, the HTL may include a poly(3,4-ethylenedioxythiophene (“PEDOT”) material, and the EML may include a polymer material such as polyphenylene vinylene (“PPV”)-based material and a polyfluorene-based material. In an exemplary embodiment of a method of manufacturing a display device, the intermediate layer313may be formed by screen printing, inkjet printing or laser induced thermal imaging (“LITI”), etc. The intermediate layer313is not limited thereto and may have various structures. Also, the intermediate layer313may include a layer formed as one body commonly over a plurality of pixel electrodes311or may include a layer patterned into discrete shapes to respectively correspond to the plurality of pixel electrodes311.

The opposite electrode315may be arranged in the display area DA and may cover the display area DA. That is, the opposite electrode315may be formed as one body commonly over a plurality of OLEDs and correspond to all of the plurality of pixel electrodes311.

Since the OLED may be easily damaged by external moisture or oxygen, the OLED may be protected by being covered by an encapsulation layer (not shown). The encapsulation layer may cover the display area DA and extend to at least a portion of the peripheral area PA. The encapsulation layer may include a first inorganic encapsulation layer, an organic encapsulation layer, and a second inorganic encapsulation layer.

Similar to the buffer layer110, the gate insulating layer130and the interlayer insulating layer150, the planarization layer170is arranged in the display area DA and may extend from the display area DA to be arranged in even the peripheral area PA.FIG. 6is an enlarged cross-sectional view of a modified exemplary embodiment of a portion A of a display device taken along line III-III ofFIG. 2according to the invention.FIG. 7is a cross-sectional view of the portion A of the display device ofFIG. 6taken along line IV-IV ofFIG. 2.

As illustrated inFIG. 6, the planarization layer170disposed in the display area DA may extend to the peripheral area PA, and particularly into the pad area PADA and may cover the input pads166and the output pads165on the substrate100. Accordingly, an additional input pad172and an additional output pad171may each be provided in plurality and arranged on the planarization layer170to respectively correspond to the input pads166and the output pads165. The additional input pads172and the additional output pads171are connected to the input pads166and the output pads165therebelow at contact holes formed in the planarization layer170. Also, the additional input pads172are connected to the input terminals182of the driving chip180, and the additional output pads171are connected to the output terminals181of the driving chip180. The additional input pads172and the additional output pads171may include the same material as that of the pixel electrode311of the display element310inside the display area DA, for example, indium tin oxide (“ITO”), indium zinc oxide (“IZO”) and/or In2O3. As including the same material as the pixel electrode311, the additional input pads172and the additional output pads171may be in a same layer as the pixel electrode311among layers disposed on the substrate100.

Since the planarization layer170covers the input pads166, the planarization layer170covers the end portions167of the input pads166disposed furthest from the thin film transistor TT among opposing ends of the input pads166. Therefore, an additional signal pad173may be provided in plural and arranged on the planarization layer170to correspond to the end portions167of the input pads166in the direction away from the thin film transistor TT. The additional signal pads173are connected to the end portions167of the input pads166therebelow at contact holes formed in the planarization layer170. Also, the additional signal pads173are connected to the output terminals191of the printed circuit board190. The additional signal pads173may include the same material as that of the pixel electrode311of the display element310inside the display area DA, for example, ITO, IZO and/or In2O3. As including the same material as the pixel electrode311, the additional signal pads173may be in a same layer as the pixel electrode311among layers disposed on the substrate100.

As illustrated inFIG. 7, additional bridge wirings174may be arranged on the planarization layer170corresponding to the bridge wirings163such that the additional bridge wirings174correspond to the bridge wirings163. The additional bridge wirings174may be connected to the bridge wirings163at contact holes formed in the planarization layer170. The additional bridge wirings174may include the same material as that of the pixel electrode311of the display element310inside the display area DA, for example, ITO, IZO and/or In2O3. As including the same material as the pixel electrode311, the additional bridge wirings174may be in a same layer as the pixel electrode311among layers disposed on the substrate100. Since the bridge wiring163is parallel-connected to the additional bridge wiring174, an overall electrical resistance may be reduced when a structure including the bridge wiring163and the additional bridge wiring174are considered.

The present disclosure is not limited thereto. As illustrated inFIG. 8, which is an enlarged cross-sectional view of another exemplary embodiment of the portion A of the display device ofFIG. 6taken along line IV-IV ofFIG. 2according to the invention, the bridge wirings163are not arranged between the interlayer insulating layer150and the planarization layer170, but may be arranged extended through the planarization layer170to be disposed on an upper surface thereof. In this case, the bridge wirings163may include the same material as that of the pixel electrode311of the display element310inside the display area DA, for example, ITO, IZO and/or In2O3. An individual one of the bridge wirings163is commonly disposed for two adjacent gate electrodes141at an individual one of the additional bridge wirings174.

As illustrated inFIG. 9, which is an enlarged cross-sectional view of still another exemplary embodiment of the portion A of the display device ofFIG. 6taken along line IV-IV ofFIG. 2, the bridge wirings163are not arranged between the interlayer insulating layer150and the planarization layer170, but may be arranged on an upper surface of the planarization layer170, and connection wirings163amay be arranged between the gate electrodes141and the bridge wirings163.

In this case, the bridge wirings163may include the same material as that of the pixel electrode311of the display element310inside the display area DA, for example, ITO, IZO and/or In2O3. As including the same material as the pixel electrode311, the a bridge wirings163may be in a same layer as the pixel electrode311among layers disposed on the substrate100. The connection wirings163amay include the same material as that of the source electrode161and the drain electrode162of the thin film transistor TT, for example, metal such as Ti or Al, and have a single-layered or multi-layered structure. Alternatively, the connection wirings163amay have a three-story structure of Ti/Al/Ti. As including the same material as the source electrode161and the drain electrode162, the connection wirings163amay be in a same layer as the source electrode161and the drain electrode162among layers disposed on the substrate100. In contrast toFIG. 8, more than one individual connection wirings163aare disposed for two adjacent gate electrodes141at an individual one of the bridge wirings163.

FIG. 10is a top plan view of another exemplary embodiment of a portion of a display device in a manufacturing process according to the invention. As illustrated inFIG. 10, not all of the gate electrodes141are spaced apart from each other over the thin film transistors TT, and a group of gate electrodes141may form one body over a group of adjacent thin film transistors TT.FIG. 10illustrates that each of the discrete shape gate electrodes141form one body over two adjacent thin film transistors TT. The gate electrodes141, which form one body over two adjacent thin film transistors TT, are spaced apart from other gate electrodes141of other thin film transistors TT, but are electrically connected to the other gate electrodes141of the other thin film transistors TT by the bridge wirings163.

As described above, the gate electrodes141each over more than one thin film transistor TT are electrically connected to each other as described in the display device according to the above embodiment.

A comparative configuration in which the gate electrodes141are not connected by the bridge wirings163, and instead one single long gate line corresponding to the gate electrodes141extends over the semiconductor layers120of the thin film transistors TT may be considered. However, where the one single long gate line corresponding to the gate electrodes141extends (along an x-axis direction) over the semiconductor layers120of the thin film transistors TT, a phenomenon such as insulation destruction (dielectric destruction) may occur in the gate insulating layer130covering the semiconductor layers120.

In one or more exemplary embodiment of the display device according to the invention, the gate electrodes141of the thin film transistors TT are spaced apart from each other by having an island shape. However, though the gate electrodes141each form one body corresponding to more than one of adjacent thin film transistors TT, the gate electrodes141, which form one body over more than one thin film transistor TT, are spaced apart from other gate electrodes141forming one body over other thin film transistors TT. Accordingly, the planar area of the gate electrodes141, which each form one body over more than one thin film transistor TT, is less than that of the above-described one single gate line. Therefore, even though charges are accumulated on the collection of gate electrodes141, which each form one body over more than one thin film transistor TT, an amount of charges accumulated on the gate electrodes141, is minimal. Therefore, one or more exemplary embodiment of the display device according to the invention may reduce or effectively prevent the gate insulating layer130, etc. from being damaged by insulation destruction, etc. during a manufacturing process, and consequently, may effectively prevent or minimize occurrence of defect of thin film transistors TT and further, defect of the display device.

FIG. 11is a top plan view of still another exemplary embodiment of a portion of a display device in a manufacturing process according to the invention.FIG. 11illustrates four data lines DLa, DLb, DLc, and DLd sequentially arranged (in the x-axis direction), for convenience of description.

The data lines DLa and DLc are electrically connected to corresponding thin film transistors TTa and TTc by the connection wirings143. Gate electrodes141aand141cof the thin film transistors TTa and TTc are spaced apart from each other and are electrically connected by the bridge wiring163. The thin film transistors TTa and TTc and the gate electrodes141aand141cthereof, forming a first group of thin film transistors TT are aligned on a first virtual line in the x-axis direction. The bridge wiring163of the first group of thin film transistors TT passes over a wiring electrically connected to the data line DLb between the data lines DLa and DLc.

Thin film transistors TTb and TTd and gate electrodes141band141dthereof, forming a second group of thin film transistors TT are aligned on a second virtual line in the x-axis direction different from the first virtual line, to be disposed in a staggered arrangement from the first group of thin film transistors TT. The data line DLb between the data lines DLa and DLc, and the data line DLd arranged at a side of the data line DLc, which is opposite to the data line DLb, are electrically connected to the connection wirings143. The connection wirings143connected to the data lines DLb and DLd are electrically connected to additional connection wirings143′ by auxiliary bridge wirings165′ including the same material as that of a source electrode161band a drain electrode162band arranged in a layer in which the source electrode161band the drain electrode162bare arranged. Gate electrodes141band141dof the thin film transistors TTb and TTd are spaced apart from each other and are electrically connected by the bridge wiring163′.

The additional connection wirings143′ extend to pass below the test signal line168through which a test signal may be applied to source electrodes161aand161cof the thin film transistors TTa and TTc and are electrically connected to drain electrodes162band162dof thin film transistors TTb and TTd. Also, the source electrodes161band161dof the thin film transistors TTb and TTd form one body with a test signal line168′.

The display device according to the present embodiment may allow channels to be simultaneously formed in semiconductor layers120aand120cof the thin film transistors TTa and TTc by simultaneously applying an electric signal to the gate electrodes141aand141cof the thin film transistors TTa and TTc, and thus allow the thin film transistors TTa and TTc to be simultaneously turned on. Therefore, whether the pixels inside the display area DA are defective may be tested by transferring an electric signal from the test signal line168to the data lines DLa and DLc through the source electrodes161aand161c, the semiconductor layers120aand120c, and the drain electrodes162aand162cof the thin film transistors TTa and TTc, and allowing the pixels inside the display area DA electrically connected to the data lines DLa and DLc to emit light.

Likewise, the display device may allow channels to be simultaneously formed in semiconductor layers120band120dof the thin film transistors TTb and TTd by simultaneously applying an electric signal to the gate electrodes141band141dof the thin film transistors TTb and TTd, and thus allow the thin film transistors TTb and TTd to be simultaneously turned on. Therefore, whether the pixels inside the display area DA are defective may be tested by transferring an electric signal from the test signal line168′ to the data lines DLb and DLd through the source electrodes161band161d, the semiconductor layers120band120d, and the drain electrodes162band162dof the thin film transistors TTb and TTd, and allowing the pixels inside the display area DA electrically connected to the data lines DLb and DLd to emit light.

In an exemplary embodiment, for example, if the pixels connected to the data lines DLa and DLc are pixels emitting red light and the pixels connected to the data lines DLb and DLd are pixels emitting green light, it is possible to test whether only the pixels emitting red light are defective or to test whether only the pixels emitting green light are defective. Though not illustrated inFIG. 11for convenience of description, it may be also implemented to test whether only the pixels emitting blue light are defective by using the same/similar structure.

Though the bridge wirings163have been described to electrically connect the gate electrodes141spaced apart from each other in the above, the embodiment is not limited thereto. As illustrated inFIG. 12is a top plan view of yet another exemplary embodiment of a portion of a display device in a manufacturing process according to the invention, andFIG. 13is a cross-sectional view taken along line XIII-XIII ofFIG. 12, the bridge wiring163may be a conductive layer, which is formed as one body, corresponding to more than one of the gate electrodes141. In this case, the bridge wiring163, which is a one-body type conductive layer, may have a shape lengthwise extending in one direction, for example, along the direction in which the gate electrodes141are arranged. The bridge wiring163, which is a one-body type conductive layer, may electrically connect three or more gate electrodes141by contacting the three or more gate electrodes141at a plurality of contact holes formed in the interlayer insulating layer150arranged between the bridge wiring163, which is a one-body type conductive layer, and the gate electrodes141.

ThoughFIG. 12illustrates a modified example of a display device according to the embodiment described with reference toFIG. 2, the embodiment is not limited thereto. In an exemplary embodiment, for example, even in the display devices according to the embodiments described with reference toFIGS. 7 to 11, the bridge wiring163may be a one-body type conductive layer corresponding to three or more of the gate electrodes141, and the bridge wiring163, which is a one-body type conductive layer, may have a shape lengthwise extending in one direction, for example, along the direction in which the gate electrodes141are arranged, and electrically connect three or more gate electrodes141.

In the modified example of the display device illustrated inFIG. 11, the bridge wiring163, which is a one-body type conductive layer, may electrically connect the gate electrodes141aand141cof the thin film transistors TTa and TTc to other gate electrodes arranged (in the x-axis direction) on the same line as that of the gate electrodes141aand141c. Similarly, the bridge wiring163′, which is a one-body type conductive layer, may electrically connect the gate electrodes141band141dof the thin film transistors TTb and TTd to other gate electrodes arranged (in the x-axis direction) on the same line as that of the gate electrodes141band141d. In this case, the bridge wiring163, which is a one-body type conductive layer, and the bridge wiring163′, which is a one-body type conductive layer, may extend in directions approximately parallel to each other.

Though various embodiments of the present disclosure have been described, the embodiment is not limited thereto. In an exemplary embodiment, for example, in a display device in which a (display) substrate thereof includes a display area and a peripheral area which is outside the display area, a plurality of electrode pairs including a source electrode and a drain electrode spaced apart from each other are arranged in the peripheral area. If a gate line extending in one single direction includes first conductive layers and second conductive layers alternately arranged in the extension direction, this configuration may belong to the scope of the present disclosure.

In an exemplary embodiment, for example, inFIG. 2, in a display device in which the plurality of electrode pairs including the source electrode161and the drain electrode162spaced apart from each other are arranged in the peripheral area PA and the gate line extending in one direction passes between the source electrode161and the drain electrode162of each of the electrode pairs, the gate line may be understood to include the first conductive layers141and the second conductive layers163alternately arranged in the extension direction. In this case, the first conductive layers141may be arranged in a layer different from that in which the second conductive layers163are arranged, among layers on the substrate100. In an exemplary embodiment, for example, as described above, the first conductive layers141may be arranged on the gate insulating layer130, and the second conductive layers163may be arranged on the interlayer insulating layer150. The first conductive layers141are electrically connected to the second conductive layers163.

Here, since the electrode pairs including the source electrode161and the drain electrode162are portions of the thin film transistors, the display device may further include the plurality of semiconductor layers120connected to the electrode pairs. Also, the gate line including the first conductive layers141and the second conductive layers163alternately arranged may be understood to pass over the semiconductor layers120.

As used herein, elements being in the same layer as or formed from the same material layer in a method of manufacturing the display device, may collectively define a single layer. In an exemplary embodiment, without being limited thereto, a collective gate layer may include the gate electrode141, the connection wiring143and the step difference adjustor145. A collective data layer may collectively include the data line DL, the source electrode161, the drain electrode162, the bridge wiring163, the output pad165, input pad166and the end portion167.

Although the disclosure has been described with reference to the embodiments illustrated in the drawings, this is merely provided as an example and it will be understood by those of ordinary skill in the art that various changes in form and details and equivalents thereof may be made therein without departing from the spirit and scope of the disclosure as defined by the following claims.