Method for manufacturing image sensor

A method for manufacturing an image sensor including forming a microlens array over a color filter array, forming a capping layer over the semiconductor substrate including the microlens array, forming a pad mask over the capping layer, and then exposing a pad in an interlayer dielectric layer.

The present application claims priority under 35 U.S.C. 119 and 35 U.S.C. 365 to Korean Patent Application No. 10-2007-0047887 (filed on May 17, 2007), which is hereby incorporated by reference in its entirety.

BACKGROUND

An image sensor is a semiconductor device for converting an optical image into an electrical signal. An image sensor may be classified as a charge coupled device (CCD) image sensor or a complementary metal oxide semiconductor (CMOS) image sensor (CIS).

The CIS may include a plurality of photodiodes and MOS transistors within a unit pixel for sequentially detecting electrical signals of respective unit pixels in a switching manner to realize an image.

The CIS may further include forming a microlens on and/or over a color filter to enhance light sensitivity of the CIS. The microlens may be formed in a semicircular/hemispherical shape by sequentially performing an exposure process, a development process, and a reflow process on a photosensitive organic material.

However, since the photosensitive organic material has weak physical properties and thus, the microlens may be easily damaged by physical impacts that may result in cracking, etc. in subsequent processes such as packaging and bumping, etc. Since the photosensitive organic material has relatively strong viscosity, a defect on the microlens may develop when particles are absorbed. In order to prevent this occurrence, use of a passivation layer composed of an oxide layer or a nitride layer having high hardness may be used or composing the microlens of inorganic material. Moreover, since the upper portion of the CIS is formed of a photosensitive organic material vulnerable to heat of 250° C. or more, an interface trap by a plasma process may occur. Accordingly, such damaging effects to the microlens may result in the generation of a dark current.

SUMMARY

Embodiments relate to a method for manufacturing an image sensor that can prevent generation of a dark current.

Embodiments relate to a method for manufacturing an image sensor that can include at least one of the following steps: forming an interlayer dielectric layer including a pad over a semiconductor substrate; forming a color filter array directly over the interlayer dielectric layer; forming a microlens array over the color filter array; forming a capping layer over the semiconductor substrate including the microlens array; forming a pad mask over the capping layer; and then exposing the pad.

Embodiments relate to a method for manufacturing an image sensor that can include at least one of the following steps: forming an interlayer dielectric layer including a pad over a semiconductor substrate; forming a passivation layer over the interlayer dielectric layer; forming a color filter array over the passivation layer; forming a planarization layer over the color filter array; forming a microlens array over the planarization layer including a first dielectric layer over the planarization layer and a second dielectric layer formed over the first dielectric layer; forming an organic layer over the semiconductor substrate including the microlens array; forming a pad mask over the organic layer, the pad mask including a first pad hole exposing an upper surface portion of the organic layer which spatially corresponds to the pad; exposing an uppermost surface of the pad by etching the organic layer, the second dielectric layer, the first dielectric layer, and the passivation layer using the pad mask as an etch mask; and then simultaneously removing the organic layer and the pad mask.

Embodiments relate to a method for manufacturing an image sensor that can include at least one of the following steps: forming an interlayer dielectric layer including a pad over a semiconductor substrate; forming a passivation layer over the interlayer dielectric layer; forming a color filter array over the passivation layer; forming a planarization layer over the color filter array; forming a microlens array over the planarization layer including a plurality of contacting microlenses having a zero gap therebetween, the microlens array further including a first dielectric layer over the planarization layer and a second dielectric layer formed over the first dielectric layer; forming a metal layer over the semiconductor substrate including the microlens array; forming a pad mask over the metal layer, the pad mask including a first pad hole exposing an upper surface portion of the metal layer which spatially corresponds to the pad; exposing an uppermost surface of the pad by etching the metal layer, the second dielectric layer, the first dielectric layer, and the passivation layer using the pad mask as an etch mask; removing the pad mask; and then removing the metal layer.

DESCRIPTION

As illustrated in exampleFIG. 1, interlayer dielectric layer20can be formed on and/or over semiconductor substrate10. A light detecting portion including a photodiode and a circuit region can also be formed for each unit pixel on and/or over semiconductor substrate10. The light detecting portion including the photodiode can include a device isolation layer defining an active region and a field region formed on and/or over semiconductor substrate10. Each unit pixel can include a photodiode for receiving light to generate a photo charge, and a CMOS circuit electrically connected to the photodiode for converting the generated photo charge into an electrical signal.

After related devices including the device isolation layer and the photodiode are formed, interlayer dielectric layer20can be formed on and/or over semiconductor substrate10. A plurality of metal lines electrically connected to the light detecting portion can be formed in interlayer dielectric layer20. Interlayer dielectric20including the metal lines can be formed having a multilayer structure composed of a plurality of layers. Each metal line can be formed so as not to shade or otherwise screen light incident on the photodiode.

Pad21can be formed in interlayer dielectric layer20while a final metal line of the metal lines is formed. Passivation layer30can be formed on and/or over interlayer dielectric layer20including pad21and serve to protect a device from undesirable moisture or scratching. For example, passivation layer30can be formed having a stacked, multilayer, dielectric structure including at least one of a silicon oxide layer, a silicon nitride layer, and a silicon oxide nitride layer. As illustrated in exampleFIG. 1, passivation layer30can have a structure including a first lower layer composed of tetraethyl-ortho-silicate (TEOS) layer31having a thickness of between 1,000-5,000 Å, and second upper layer composed of nitride layer32having a thickness of between 1,000-10,000 Å.

Color filter40including a plurality of filters can then be formed through a subsequent process on and/or over passivation layer30. Color filter40can also be formed directly on and/or over interlayer dielectric layer20including pad21to obtain an image sensor having a reduced thickness and overall size.

A first pad exposure process for exposing pad21can then be performed. In the first pad exposure process, photoresist patterns having a hole corresponding to a pad region can be formed on and/or over passivation layer30. Also, passivation layer30can be etched using the photoresist patterns as an etch mask to expose the uppermost surface of pad21. Therefore, after the first pad exposure process is performed, a microlens array can then be formed, and then a second pad exposure process can be performed. The first pad exposure process can be omitted.

Color filter40can then be formed on and/or over passivation layer30and can include a plurality of color filters for realizing a color image. Such color filters can represent a different color such as red, green, and blue. Examples of a material that can be used for color filter40include a dyed photoresist. Color filter40can be formed on and/or over each unit pixel to separate color from incident light such that adjacent color filters40can slightly overlap each other to have a height difference. To complement this height difference, planarization layer50can be formed on and/or over color filters40. A microlens array to be formed in a subsequent process should be formed on and/or over a planarized surface. Therefore, planarization layer50can be formed on and/or over color filters40to remove the height difference caused by overlapping color filters40. Of course, planarization layer50can be omitted.

First dielectric layer60for forming microlenses can then be formed directly on and/or over color filters40or planarization layer50. Microlens array mask200for each unit pixel can then be formed on and/or over first dielectric layer60. First dielectric layer60can be composed of at least one of an oxide layer, a nitride layer, and a nitride oxide layer. For example, first dielectric layer60can be composed of an oxide layer such as SiO2formed having a thickness of between about 2,000-20,000 Å at a temperature range of between about 50-250° C. using chemical vapor deposition (CVD), physical vapor deposition (PVD), or plasma enhanced CVD (PECVD).

Microlens array masks200can be formed including a plurality of microlens masks formed spaced apart a predetermined distance by coating first dielectric layer60with a photoresist layer and then performing a patterning process and a reflow process. Microlens mask200can then be formed having hemispherical shape.

As illustrated in exampleFIG. 2, seed microlens61array for each unit pixel can then be formed on and/or over first dielectric layer60. Seed microlens array61can be formed by performing an etching process on first dielectric layer60using microlens array masks200as an etch mask. The etching of first dielectric layer60can be performed such that a photoresist layer forming microlens array mask200and an oxide layer forming first dielectric layer60are etched at an etching ratio of between about 1:0.7-1.3. Therefore, the etching of first dielectric layer60for forming seed microlens array61can be performed until microlens array mask200composed of a photoresist material is completely etched. For example, the etching process for first dielectric layer60can be performed in a chamber by supplying an etching gas of CxHyFz(x,y,z are zeros or natural numbers), and an inert gas such as at least one of Ar, He, O2, and N2. Specifically, the etching process can be performed using a source power of between about 600-1400 W at 27 MHz, and a bias power of between about 0-500 W at 2 MHz applied in the chamber, and injecting an etching gas in the chamber including CF4of about 40-120 sccm and an inert gas such as at least one of O2of about 2-20 sccm and Ar of about 200-900 sccm.

First dielectric layer60can be etched to a thickness of between about 1,000-19,000 Å to form seed microlens array61. Seed microlens array61can be formed having a thickness of between about 1,000-6,000 Å. Particularly, the process can be progressed such that the bias power is not applied to the chamber during the etching process. This can result in reducing the energy of ions moving from plasma generated inside the chamber to semiconductor substrate10. In turn, the etching damage to first dielectric layer60can be reduced. A dark current by a trap level generated at the interface of semiconductor substrate10during a plasma process can also be prevented.

As illustrated in exampleFIG. 2, through the above-described etching process, seed microlens array61having a hemispherical shape can be formed of a lower temperature oxide layer on and/or over corresponding color filters40. Seed microlens array61can be formed such that each respective seed microlens is separated from an adjacent seed microlens to prevent a merging phenomenon.

As illustrated in exampleFIG. 3, second dielectric layer70can then formed on and/or over semiconductor layer10including seed microlens array61to form microlens array80. Second dielectric layer70can be deposited on and/or over the uppermost surface of first dielectric layer60including seed microlens array61and also in gaps between adjacent seed microlenses. Thus, each one of the seed microlenses can directly contact an adjacent seed microlens. Therefore, microlens array80including seed microlens array61and second dielectric layer70can be formed having a continuous hemispherical shape without gaps between adjacent microlenses. Second dielectric layer70can be composed of the same material as that of first dielectric layer60. For example, second dielectric layer70can be formed by depositing an oxide layer to a thickness of between about 500-20,000 Å at a temperature range of between about 50-250° C.

Because second dielectric layer70is deposited having a thin thickness on and/or over seed microlenses61and in gaps therebetween, a microlens80can be formed such that adjacent microlenses can be in direct contact. Therefore, a gap between the microlenses can be reduced to zero, thereby enhancing the image quality of the image sensor.

As illustrated in exampleFIG. 4, capping layer90can then be formed on and/or over semiconductor substrate10including microlens array80for preventing a trap level generated between semiconductor substrate10and the dielectric by an ultraviolet (UV) radiation generated during a plasma etching process.

Capping layer90can be deposited to have a thickness of between about 100-3,000 Å to cover both microlens array80and interlayer dielectric layer20formed on and/or over semiconductor substrate10. Capping layer90can be composed of an organic bottom anti-reflection coating layer (BARC). When capping layer90is formed as an organic BARC layer, capping layer90can absorb UV radiation generated during the plasma etching process to prevent a trap level generated between semiconductor substrate10and the dielectric layer.

Alternatively, capping layer90can be composed of a metal layer formed by depositing a metal material having an electrical conductivity of about 10−6ohm/m or more. Such metal materials that can be used for capping layer90include at least one of Al, Ti, W, and TiN, i.e., materials having electrical conductivity of about 10−6-10−3ohm/m. When capping layer90is formed as a metal layer, capping layer90can reflect UV radiation generated during the plasma etching process to prevent a trap level generated between semiconductor substrate10and the dielectric layer.

As illustrated in exampleFIG. 5, pad mask100including pad hole110can then be formed on and/or over capping layer90. Pad mask100can be formed by coating capping layer90with a photoresist and patterning the photoresist. An upper surface portion of capping layer90spatially corresponding to pad21can be exposed by pad hole110, and the rest of capping layer90can be covered by pad mask100.

Portions of capping layer90, second dielectric70, first dielectric60, and passivation layer30can then be etched using pad mask100as an etch mask to form pad exposure hole23exposing the uppermost surface of pad21. Pad exposure hole23can be formed through a dry etching process. For example, pad exposure hole23can be formed through the same etching process used to form seed microlens array61. Particularly, pad exposure hole23can be performed through an etching process using a source power of between about 600-1400 W at 27 MHz, a bias power of between about 0-500 W at 2 MHz, and supplying an etching gas composed of CxHyFz(x,y,z are zeros or natural numbers), and an inert gas composed of at least one of Ar, He, O2, and N2inside a chamber. Because UV radiation can be generated while the plasma etching process is performed, the use of capping layer90prevents absorbsion of the UV radiation to semiconductor substrate10. Meaning, when capping layer90is an organic BARC layer, the UV radiation is absorbed in capping layer90, thereby preventing generation of a dark current. Alternatively, when capping layer90is a metal layer, the UV radiation is reflected by capping layer90, also preventing generation of a dark current.

As illustrated in exampleFIG. 6, after the etching process to expose pad21, pad mask100can be removed by performing an ashing process at a temperature range of between about 0-50° C. Specifically, pad mask100can be removed using O2gas at a temperature of 0° C. This can be performed by lowering the temperature of a lower electrode on which semiconductor substrate10is seated.

If capping layer90is composed of an organic layer such as BARC, capping layer90can be simultaneously removed while pad mask100is removed since they are formed of an organic material. Removing pad mask100and capping layer90can typically require a temperature of 200° C. or more at which a process for removing a photoresist layer has been performed. In accordance with embodiments, such a high temperature is not required, so that the surface of the microlens array80can be prevented from being damaged by exposure to high temperatures.

If capping layer90is composed of a metal layer, pad mask100can be removed first and removal of capping layer90can be subsequently performed. Capping layer90formed of a metal material can be removed using an etching gas including an element belonging to a halogen group such as F, Cl, etc.

In accordance with embodiments, a method for manufacturing an image sensor can form a microlens array formed of an inorganic material to prevent the microlenses from being damaged by subsequent package and bump processes. Such a method can form gapless microlenses to improve the sensitivity of the image sensor. Moreover, such a method can including formation of a capping layer on and/or over the surface of the microlens array to prevent generation of a dark current by plasma during subsequent processes, and thereby enhancing the overall quality of the image sensor.