High frequency, low cost package for semiconductor devices

A direct attachment technique is described for silicon packages housing high frequency devices. A silicon package may be shaped as either a plug or a socket or the package may have both the plug and socket capability, thus enabling the package to be directly attached to other packages The plug is trapezoidal in cross section while the socket has a dovetail-joint-like aperture. The plug is inserted into the socket thereby directly attaching one package to another. The two packages are locked together when the slanted edges of the plug are fitted to the slanted edges of the socket.

DETAILED DESCRIPTION OF THE INVENTION Hereinafter, embodiments of the present invention will be described in detail with reference to the attached drawings. The present invention is not restricted to the following embodiments, and many variations are possible within the spirit and scope of the present invention. The embodiments of the present invention are provided in order to more completely explain the present invention to one skilled in the art. Referring to FIG. 1 , FIG. 1 a and FIG. 1 b , an embodiment for directly attaching at least two packages housing high frequency semiconductor devices together using a plug-and-socket approach is illustrated. FIGS. 1, 1 a and 1 b will be jointly described, thus it is important to note that FIG. 1 a and FIG. 1 b are the same double plug silicon package however, FIG. 1 a illustrates an external view of the double plug silicon package while FIG. 1 b depicts an internal (or bottom) view of the double plug silicon package. The packages may be formed of a material that can be micromachined. An example, of such a material is silicon. Although the invention is not limited to silicon for the substrate materials the following description is provided using silicon as an example of the package material and particularly of the substrate material forming the package. In this technique, two silicon structures are fabricated, each having a male and/or female component. Specifically, FIG. 1 depicts a plan view of a double socket type silicon package ( 1 ) having both a guide socket ( 4 ) and an original socket ( 6 ). FIG. 1 a and FIG. 1 b , on the other hand, illustrate a double plug silicon package ( 2 ) having both a guide plug ( 8 ) and a signal plug ( 10 ). Generally, the double plug silicon package ( 2 ) of FIG. 1 a is fitted into the matching sockets of the double socket type silicon package ( 1 ) of FIG. 1 , thereby allowing direct attachment of two devices such high frequency devices in a manner that enables efficient signal transmission for high frequency semiconductor devices. The double socket type silicon package ( 1 ) and the double plug silicon package ( 2 ) are fabricated using two high-resistivity silicon wafers for each package. The fabrication process will be fully described below. As can be seen in FIG. 1 , the double socket type silicon package ( 1 ) contains a circuit aperture ( 14 ) for housing an integrated circuit, preferably an MMIC. The double plug silicon package ( 2 ) also contains a circuit aperture ( 14 ). Any type of circuit, including passive or active circuits, can be packaged using the silicon-based packaging technology of the present invention. Other devices, such as optical fibers, may be housed using the silicon based package having a male or female component, thereby allowing optical fibers to be directly coupled to one another. Both silicon packages ( 1 ) and ( 2 ) further contain a center conductor line ( 12 b ) separated by a non-metallized channel from a ground conductor ( 12 a ) on either side that run along the flat mating surfaces of the signal plug ( 10 ) and socket ( 6 ). The electrical conductors ( 12 ) for the double plug silicon package ( 2 ) are illustrated in FIG. 1 b . Several transmission-line/waveguides variations are possible. For example, an electrical connection can be made utilizing the coplanar waveguide-stripline (CPW-stripline) technique. This technique, as depicted in FIG. 1 and FIG. 1 b , employs a center conductor ( 12 b ) surrounded by two planar ground conductors ( 12 a ). The conductors may be electroplated gold metal areas, separated by unmetallized channels which expose the high-resistivity substrate. Once the signal plug ( 10 ) is inserted into the socket ( 6 ) and a tight fit is formed (as will be fully explained below), the conductors ( 12 ) all make contact. Electrically, each pair of overlaid conductors ( 12 ) act as one. The CPW-stripline transmission line runs inside each silicon package ( 1 ) and ( 2 ), where a connection is made to the MMIC located in the circuit aperture ( 14 ). This is accomplished by forming a cavity in the upper wafer to provide clearance. At this point, the transmission line makes a transition from TEM-mode CPW-stripline (which is fully surrounded by silicon) to quasi-TEM mode CPW (with silicon below and air above the plane of the conductors) ( 16 ). This transition is achieved by tapering the center conductor ( 12 b ) to achieve equal impedance and then a wire or ribbon bond makes the connection to the MMIC. This bond couples a signal input or signal output pad of the MMIC to the center conductor ( 12 b ) of the transmission line. Unlike conventional surface mount attachment technology, in the present invention, the signal does not travel up or down between packages and through a printed circuit board. This greatly simplifies the RF design, since the transmission line maintains constant cross-section until immediately before reaching the MMIC. Such a design has inherently extremely wide bandwidth. Referring to the FIG. 1 , FIG. 1 a and FIG. 1 b , the silicon packages illustrate an embodiment of the direct attachment method of the present invention. Specifically, a double plug and socket configuration is used to join the two silicon packages together. A double plug silicon package ( 2 ) has a guide plug ( 8 ) that provides coarse alignment when signal plug ( 10 ) is inserted into signal socket ( 6 ) of the silicon package ( 1 ), wherein signal plug ( 10 ) carries the signal via the electrical conductors ( 12 ). A flexible silicon spring ( 18 ) is used to apply compressive force when the signal plug ( 10 ) is inserted into the socket ( 6 ). The spring beam ( 18 ) generates a frictional force on the signal plug ( 10 ) to secure the two packages together. Additionally, the edges of signal plug ( 10 ) and the spring beam ( 18 ) can be tapered to allow easy insertion and a positive lock when signal plug ( 10 ) is fully inserted into signal socket ( 6 ). The guide plug ( 8 ), as depicted in FIGS. 1 - 1 b , restricts the range of travel of signal plug ( 10 ) so that the movement of the signal plug ( 10 ) in the signal socket ( 6 ) does not exceed the maximum excursion of the silicon spring beam ( 18 ), regardless of the position and direction in which the two packages are brought together. Once signal plug ( 10 ) of silicon package ( 2 ) is inserted into socket ( 6 ) of silicon package ( 1 ), there is a tight fit, with only very small air gaps remaining between the silicon of the two packages. Once in a fully inserted position, the plug ( 8 )( 10 ) and socket ( 4 )( 6 ) overlap in a precise way so that the electrical conductors ( 12 ) overlap and touch, allowing the signal to flow from one package to the other. The two packages are then handled as a unit, and are mounted on a circuit board or within a separate housing to form a module. DC power and low frequency control signals may be connected by conventional surface mount connections to a circuit board or by wire bonds. Referring to FIGS. 2, 2 a and 2 b , another aspect of the present invention using a single plug and socket configuration to directly attach two silicon packages that house high frequency semiconductor devices is illustrated. FIG. 2 and FIG. 2 a depict the external surface of a single plug silicon package ( 22 ) and single socket silicon package ( 30 ) that can be interconnected by inserting signal plug ( 10 ) into socket ( 6 ). As shown in FIG. 2 , the single plug silicon package ( 20 ) has a circuit window ( 22 ), usually enclosed by a metal cap, wherein a circuit ( 24 ) is housed. Such a circuit window may be used independent of the plug/socket arrangement of the packages and thus such an optional window may be also used in the embodiment of FIGS. 1 - 15 The circuit window ( 22 ) enables circuits to be placed in the silicon package after the silicon package is fabricated. Thus, empty silicon packages can be sold such that the buyer can choose which circuit to place within the package. FIG. 2 a depicts a silicon package with a circuit window ( 22 ) ready to accept any circuit. In another embodiment of the present invention (not shown), the circuit ( 24 ) is fully encapsulated by the silicon substrates, thus a circuit window ( 22 ) is not provided. FIG. 2 b depicts a bottom portion view of single plug silicon package ( 20 ), wherein the electrical conductors ( 12 ) and non-metalized channels ( 54 ) form the transmission line ( 12 ), and circuit ( 24 ) is located within the circuit aperture ( 14 ). As described above, the signal plug ( 10 ) of the single silicon package ( 20 ) is inserted into the socket ( 6 ) of package ( 30 ). Once fully inserted, the electrical conductors of silicon package ( 30 ) and silicon package ( 20 ) make contact thereby enabling a signal to pass between the two circuits housed in individual silicon packages that are directly attached. In another aspect of the present invention depicted in FIG. 3 , the signal plug ( 10 ) and socket ( 6 ) are held together as a result of inversely slanted edges. FIG. 3 illustrates the signal plug ( 10 ) as trapezoidal in cross section while socket ( 6 ) is formed as a dovetail-joint-like aperture that accepts the signal plug ( 10 ). The angled edges of the socket ( 40 ) create a dovetail-joint like aperture that welcomes the slanted edges of the plug ( 38 ) to ensure a tight fit between the two silicon packages. The angles of the slanted edges ( 38 )( 40 ) with respect to vertical is the same on both the signal plug ( 10 ) and socket ( 6 ). The three electrical lines/conductors ( 12 ) may be gold, but any other metal may be substituted. The two gaps between the three conductors are bare silicon ( 54 ) of the substrate. Referring to FIG. 4, a cross sectional view, across a double plug inserted into a double socket is illustrated. In FIG. 4, a silicon package ( 44 ), having a signal plug ( 10 ) and a guide plug ( 8 ), is fully inserted into the silicon package ( 46 ) having two sockets ( 4 )( 6 ). Electrical contact is made upon full insertion of the plug into the socket when the overlapped metal of the plug and socket form the center conductor ( 12 b ) and ground planes ( 12 a ) of the CPW-stripline transmission line. Furthermore, the guide plug ( 8 ) may provide DC and IF connections via several gold lines on the bottom of the guide plug ( 8 ) and several gold lines on the surface of the guide socket ( 4 ). Upon insertion of the plug ( 8 ) into the socket ( 4 ), the conductors ( 12 ) come into contact thus providing DC and IF connections. The silicon piece ( 53 ) on the double socket silicon package separates the two sockets ( 4 ) and ( 6 ). The angled edges of ( 53 ), as seen in FIG. 4 , illustrates the dove-tail sockets ( 4 ) ( 6 ) that keep the two silicon packages connected to one another when the signal plug ( 10 ), having slanted edges, is inserted into the socket ( 6 ). FIGS. 5 - 5 b provide another cross sectional view of a silicon package having a plug being inserted into a silicon package having a socket. The silicon package further comprises a circuit aperture ( 14 ) for housing the integrated circuit ( 24 ) which is wire bonded ( 43 ) to the electrical metal conductors ( 16 ) of the CPW line. As illustrated in FIG. 5 , the electrical conductors ( 12 ) run the length of both silicon packages. When the signal plug ( 10 ) is inserted into the socket ( 6 ), as depicted in FIGS. 5 a and 5 b , the electrical conductors ( 12 ) overlap and touch, allowing the signal to flow from one package to the other. FIG. 5 further illustrates an embodiment of the present invention wherein the circuit is not fully encapsulated within the silicon package. This allows the circuit to be placed within the package at any given time after the silicon package is fabricated. Once a circuit is placed in the package, a lid ( 47 ) is placed over the circuit aperture ( 14 ) to protect the circuit ( 24 ). In an alternate embodiment of the present invention, the circuit is fully encapsulated within the silicon package. FIGS. 6 - 8 depict additional aspects of the present invention, wherein a silicon package is fabricated having multiple plug and socket components. These additional aspects illustrate preferred configurations for directly attaching silicon packages that house high frequency devices together, however, any and all configuration, utilizing a connector attachment structure fall within the ambit of this invention. Specifically, FIG. 6 illustrates a silicon package having a socket located at one edge of the silicon package and a plug located at the opposite edge of the silicon package. The plug and socket may be located at any point along the edges of the silicon package and is therefore not limited to the edges of the package shown. Referring to FIG. 7, a silicon package having four plugs is illustrated. One plug is located at each side of the silicon package. Any package shape having a connector formation of the present invention may be utilized. Referring to FIG. 8, a silicon package having a plug located at each end of the silicon package is illustrated. The silicon package may comprise two sockets located at each end of the silicon package. As disclosed above, the plugs/sockets may be located at any point along the silicon package. Furthermore, it is possible to have multiple chips within a package, and depending on the function, they may require any number of plug or socket components. The fabrication of the packages may be performed using standard micromachining techniques. An embodiment of the fabrication process for a double-plug silicon package wherein one guide plug provides coarse alignment while the other plug carries the RF signal, is fully described below. The silicon package fabrication process begins with two high-resistivity silicon wafers, approximately 20 mils thick, double side polished, hereinafter referred to as wafer 1 and wafer 2. The wafers are cleaned using an industry standard RCA cleaning process. A wet oxidation is performed using a conventional wetox process thereby heating the wafers to 1200 C. for four hours in a wet oxygen atmosphere. Thermal oxides approximately 1.2 microns thick are grown on both wafers. Next, a standard double-side photolithography cycle is performed. A coating of photoresist is applied to the backside of the wafer by spin coating and is then hard baked. A coating of photoresist is also applied to the front side of the wafer. The wafers are then patterned with the appropriate masks on both the top and bottom side. Following the photoresist cycle, the pattern is transferred into the silicon oxide layer by wet etching. Upon completion of the wet etch, the photoresist is stripped using a standard stripper. This oxide forms a mask that protects some areas of the silicon, while areas with no oxide are exposed. For certain types of packages, via holes are required which make electrical connection from one side of the wafer to the other. In these packages, small holes are etched from the top of wafer 1 through to the bottom side. For these holes, the aperture in the top side oxide may be square and the length of each side of the aperture is roughly twice the wafer thickness. For packages with via holes, the wafers are deep silicon etched before metal plating. For packages without via holes, the silicon etching is performed last. The wafer is subsequently cleaned and a thin film of metal is applied as a seed layer for electroplating. The thin film is deposited by vacuum or sputtering and comprises approximately 10 nm of Chrome followed by approximately 100 nm of gold. Upon completion, the standard photoresist cycle is performed again using a photomask for metal patterning. Photoresist is applied and patterned to form the openings where metal will be electroplated. For wafers with via holes, a conformal coating of photoresist is required. This requires the use of an optimized coating process typically using thicker photoresist, slower spin speeds, and low baking temperatures. The photoresist is patterned in a contact aligner. This pattern will consist of the CPW lines used to carry the RF signal down the plug into the receptacle. Also, the pattern will remove resist inside the via holes and from around the perimeter of the via hole; after plating, this will form a pad on the top and a pad on the bottom which are electrically connected. Gold metal is electroplated onto the wafer (for example 4 micron thickness), and then the resist is removed. The wafer is re-patterned for electroplating of the bonding metal. This pattern places bonding metal in any areas where the two wafers come into contact, except under the cantilevered silicon spring beam, which should not be attached to wafer 1 since it must be free to bend. The bonding metal is any metal which bonds under heat treatment. Examples are Tin/Lead eutectic or Tin/Gold eutectic. The photoresist is stripped, and the electroplating base is removed by wet etching or sputter etching. For packages which have no via holes and have not yet been etched, the wafer is now ready for deep silicon etching. The wafer is immersed in a reflux tub of TMAH that causes the silicon to be removed from areas not protected by metal or silicon oxide. The wafers are removed once the etched features have proceeded all the way through the wafer. Additionally, etching may be added as needed to round the corners and other features to the exact design and shape. Wafer 2 is bonded onto the top of Wafer 1 using an aligner-bonder. They are clamped together so that all features align correctly, and then they are bonded by a heat cycle. For example, with Sn/Pb bonding metal, a 15 minute cycle to 220 C. in a forming gas atmosphere is typically sufficient. After bonding, the stack of wafers is cut into individual packages with a dicing saw. The cuts are aligned to the package to properly define the edges of the package. In an alternate embodiment of the invention, the above photomasks are modified somewhat to improve the definition of the features. Typically, convex corners of silicon etch quickly get rounded. Thus, a standard technique is to add extensions to the corner, so that after etching it will be less rounded. The proper size of this extension for a particular etching system is determined by etching test wafers with a range of extension sizes. The mask patterns for the socket and plug silicon etches are modified to incorporate the convex-corner protection extensions. Referring to FIG. 9, a cavity/circuit aperture formed within the silicon substrate to mount a chip is illustrated. By making the cavity/circuit aperture ( 14 ) depth approximately equal to the chip thickness, the top surface of the chip ( 24 ) after mounting is made level with the silicon surface ( 68 ). This allows a shorter wire bond to be used to connect the chip ( 24 ) input/output pads to the CPW line ( 12 ) on the silicon substrate ( 68 ). The circuit aperture ( 14 ) is formed by inserting additional etching steps at the beginning of the fabrication sequence described above. The wafers are initially cleaned, and a thermal oxide grown. The oxide is then patterned with rectangular openings for the cavities. The wafer is etched in anisotropic etchant such as EDA-P to the desired depth, for example 4 mils for many MMICs. The wafer is then re-cleaned and a new thermal oxide layer is grown which seals the cavity. Upon completion of the circuit aperture/cavity, the fabrication procedure continues as described above, except that all subsequent photoresist layers are applied using a spin recipe or coater, which gives good coverage of the etched features. In an alternative embodiment of the invention, chips are mounted on the silicon wafers before the bonding step. Thus, many chips are mounted on a wafer and another wafer is bonded to the first wafer, thereby simultaneously forming several sealed packages. This creates prepackaged ICs that can be directly attached to other ICs to form a module instantaneously. FIG. 10 illustrates one example of the packaging technology of the present invention wherein an MMIC is fully encased in the silicon package. In an alternative embodiment, ICs are not mounted before wafer bonding. Instead, the IC packages are not completely sealed, but have a window etched into the silicon wafer above the site where the IC is to be mounted. The wafers are bonded together, forming empty silicon packages. The packages are diced apart, and sold as empty packages. Users then mount an IC, and an MMIC through the window in the top of the package, wire bond the connections, and finally seal the package with a metal cap. This cap is a typical package cap including, stamped metal sealed with solder preforms. Referring to FIG. 11, a nub located on both the silicon spring beam and the guide plug to provide a more positive locking action is illustrated. In this embodiment, small bumps or “nubs” ( 38 ) on both the silicon spring beam ( 18 ) and plug ( 8 ) to provide a more positive locking action when the signal plug ( 10 ) is inserted into the socket ( 6 ). The side of the plug ( 8 ) which touches the silicon spring beam ( 18 ) is slightly narrower at the tip, and moving along the plug ( 8 ) from the tip, it widens slightly, then narrows slightly. A nub/recess ( 62 ) arrangement an shown in FIG. 11 may be used. The silicon spring beam ( 18 ) may also have a tapered shape, so that when the plug ( 8 ) is inserted, the silicon spring beam ( 18 ) will flex outward, then will move back towards its original position once the nub ( 38 ) on the plug ( 8 ) and silicon beam ( 18 ) pass each other. This provides a binding force that tends to pull the plugs ( 8 ) ( 10 ) into the sockets ( 4 )( 6 ). The spring beam ( 18 ) may be located at any point on the package wherein the beam is capable of applying an attaching force (compressional and/or frictional). The nubs ( 38 ) are formed by a variety of methods. A protrusion on the photomask pattern will form such a nub, however, the etching will tend to reduce or remove this nub. Experimentation is used to find the appropriate shape for the modification to the photomask pattern. Another aspect of the present invention uses edges as shown in FIG. 11 that are angled ( 60 ) relative to the <111> crystal plane to form the nubs ( 38 ). For example, an edge ( 60 ) which is 10 degrees from the <111> plane will tend to propagate as the etch progresses, so that the angled edge ( 60 ) moves in the <111> plane at a rate of approximately five times the vertical etch rate. In a design for 20 mil thick wafers, a propagation of approximately 112 mils is typically expected. The photomask is then adjusted so that the angled edges ( 60 ) will be in the desired position when the etching is completed. That is, the angled edges ( 60 ) are offset by 112 mils from their desired final location. Referring to FIGS. 12 - 15 , a module created using the direct attachment technique of the present invention is illustrated. FIGS. 12 and 13 illustrate four silicon packages with varying direct attachment components. Specifically, Package A ( 70 ) has a plug and socket configuration whereas Package C ( 90 ) and D ( 100 ) have a single plug configuration. A double socket configuration is illustrated by Package B ( 80 ). By inserting the plug of one package into the socket of another package, an RF connection is formed between the packages. For example, a receiver can be constructed by interconnecting the following packages: Package A ( 70 ) contains a Low Noise Amplifier (LNA) MMIC chip, Package B ( 80 ) contains a mixer MMIC chip, Package C ( 90 ) contains an oscillator MMIC, and Package D ( 100 ) contains a MMIC with a printed circuit antenna (Package D ( 100 ) has no lid, so the antenna is open to the outside). Packages A ( 70 ), B ( 80 ), and C ( 90 ) have several via holes (not shown) passing through wafer 1 connecting pads on top of wafer 1 to pads on the bottom. These via holes may be for DC power and IF connections. Wire bonds are made from the DC and IF pads on the MMICs to the pads on top of wafer 1, and they are connected through via holes to pads on the bottom of the package. Package A ( 70 ) has a socket on one side for input and a plug on the opposite side for output. It has two pads on the bottom: one for DC power, and another for ground. Package B ( 80 ) has a socket on one side for RF input, and another socket on the opposite side for LO input. It has pads on the bottom for DC power and ground, and a pad for IF output. The IF output pad has a ground pad on either side. Package C ( 90 ) has a plug for RF output, and pads on the bottom for DC power and ground. Package D ( 100 ) has a plug for RF output. Referring to FIGS. 14 and 15 , a module assembled using the direct attachment technique of the present invention is illustrated. To assemble the system, the plug of Package D ( 100 ) is inserted into the socket of Package A ( 70 ). Then, the plug of package A ( 70 ) is inserted into the socket for the input on package B ( 80 ). The plug of package C ( 90 ) is inserted into the socket for a local oscillator (LO) input on package B ( 80 ). Thus, the four packages are connected and form a module ( 105 ). The module ( 105 ) is then surface-mounted onto a circuit board ( 110 ), as depicted in FIG. 14 , which provides connections to the pads on the bottom of the packages. The circuit board ( 110 ) provides power to the packages, and circuitry to perform IF amplification and processing.