A multi-chip semiconductor apparatus includes a plurality of semiconductor chips stacked and packaged therein, wherein each of the semiconductor chips includes: a through-silicon via (TSV) formed through the semiconductor chip; a probe pad exposed to an outside of the semiconductor chip so as to enable a probing test; a bump pad exposed to the outside of the semiconductor chip and electrically connected to the TSV; and a conductive layer electrically connecting the probe pad and the bump pad inside the semiconductor chip.

CROSS-REFERENCES TO RELATED APPLICATION

The present application claims priority under 35 U.S.C. §119(a) to Korean application number 10-2012-0090719 filed on Aug. 20, 2012, in the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference herein.

BACKGROUND

1. Technical Field

Various embodiments presented herein relate to a semiconductor apparatuses, and more particularly, to a multi-chip semiconductor apparatuses including a plurality of semiconductor chips stacked through through-silicon vias (TSVs).

2. Related Art

Packaging technology for semiconductor apparatuses has continuously developed to satisfy demands for miniaturization and reliability of mountings. For example, the demand for miniaturization has accelerated the technology development for packages which are close to chip size. The demand for more reliable mountings has driven the importance and development of packaging technologies capable of improving the efficiency of mounting operations and the mechanical/electrical reliability after mounting.

Furthermore, as high performance electric and electronic products are required with miniaturization, various technologies for providing a high-capacity semiconductor module have been researched and developed. As a method for providing a high-capacity semiconductor module, high integration for memory chips may be used. This high integration may be realized by integrating a larger number of cells into a limited space of a semiconductor chip. However, such high integration for memory chips requires a high-level technology and a large amount of development time. For example, a fine critical dimension (CD) may be required. Therefore, improved stack technology may provide benefits in a high integration environment.

SUMMARY

In one embodiment, a multi-chip semiconductor apparatus includes a plurality of semiconductor chips stacked and packaged therein, wherein each of the semiconductor chips includes: a through-silicon via (TSV) formed through the semiconductor chip; a probe pad exposed to an outside of the semiconductor chip so as to perform a probing test; a bump pad exposed to the outside of the semiconductor chip and electrically connected to the TSV; and a conductive layer electrically connecting the probe pad and the bump pad inside the semiconductor chip.

In another embodiment, a multi-chip semiconductor apparatus includes a plurality of semiconductor chips stacked and packaged therein, wherein each of the semiconductor chips includes: a plurality of TSVs formed through the semiconductor chip; a probe pad exposed to an outside of the semiconductor chip so as to perform a probing test; a plurality of bump pads exposed to the outside of the semiconductor chip and electrically connected to the respective TSVs; and one or more conductive layers electrically connecting the probe pad to the respective bump pads inside the semiconductor chip.

In another embodiment, a multi-chip semiconductor chip includes a plurality of semiconductor chips stacked and packaged therein, wherein each of the semiconductor chip includes: a TSV formed through the semiconductor chip; a bump pad exposed to an outside of the semiconductor chip and electrically connected to the TSV through a first conductive path; an internal circuit formed in the semiconductor chip and electrically connected to the TSV through a second conductive path; and a probe pad exposed to the outside of the semiconductor chip to perform a probing test and electrically connected to the internal circuit through a third conductive path, each of the first to third conductive paths includes a plurality of conductive layers and a plurality of conductive contacts connected between the respective conductive layers, and specific conductive layers of the first and third conductive paths are electrically connected to each other.

In another embodiment, a multi-chip semiconductor chip apparatus includes a plurality of semiconductor chips which are electrically connected and stacked through a TSV, wherein each of the semiconductor chips includes: a memory cell block; a bump pad electrically connected to the TSV and configured to transmit and receive information to and from the memory cell block; and a probe pad configured to transmit and receive test information to and from the memory cell block, and during a probe test after packaging, the probe pad of the semiconductor chip is electrically connected to the bump pad, and transmits and receives the test information on the semiconductor chip to and from outside through the probe pad of the uppermost semiconductor chip of the semiconductor chips.

Additional alternative embodiments will be apparent to a person of ordinary skill in the art according to the descriptions provided herein.

DETAILED DESCRIPTION

Hereinafter, a multi-chip semiconductor apparatus will be described below with reference to the accompanying drawings through various embodiments.

A stacked multi-chip semiconductor apparatus has a structure in which two or more semiconductor chips are stacked in one package. As a method for stacking a plurality of semiconductor chips in a package, certain structures may use through-silicon vias (TSVs). In packages using TSVs, holes are formed through the semiconductor chips, and filled with a conductive material to form the TSVs. Through the TSVs, upper and lower semiconductor chips are electrically connected.

FIG. 1is a cross-sectional view of a conventional multi-chip semiconductor apparatus including a plurality of semiconductor chips stacked through TSVs.

The multi-chip semiconductor1illustrated inFIG. 1includes a plurality of semiconductor chips10and20stacked over a substrate.

Each of the semiconductor chips10and20includes a TSV formed by filling a hole formed therein. For example, the first semiconductor chip10includes a TSV11and bump pads12and13which are electrically connected to both ends of the TSV11so as to be exposed to the outside. The bump pads of the semiconductor chips10and20facing each other may be connected through a bump18such that the TSVs of the respective semiconductor chips10and20are electrically connected to each other.

The TSV11of the first semiconductor chip10is connected to an internal circuit15through a conductive path16. That is, various voltages/signals used in internal circuits of the semiconductor chips10and20are transmitted to the respective semiconductor chips through the TSVs, and then transmitted to the internal circuits from the TSVs through the conductive paths inside the semiconductor chips.

Furthermore, each of the stacked semiconductor chips10and20includes a probe pad formed thereon, in order to perform a probing test on the semiconductor chip before the semiconductor chip is stacked and packaged. The probe pad may include various types of pads to perform various tests by transmitting and receiving a power supply voltage, various signals, data and the like. For example, the probe pad14of the first semiconductor chip10is electrically connected to the internal circuit15through the conductive path17.

Each of the conductive path16to connect the TSV11and the internal circuit15and the conductive path17to connect the probe pad14to the internal circuit15may include a plurality of conductive layers and a plurality of conductive contacts connected between the respective conductive layers. The probe pad14may be formed by opening the uppermost conductive layer among the plurality of conductive layers. The conductive layer may include a metal layer, and the conductive contact may include a metal contact.

Meanwhile, the probing test for the multi-chip semiconductor apparatus1could be performed only in a state of mono chips before the respective chips are stacked and packaged. That is because, since the probe pads of the respective chips are not connected through the TSVs, it is difficult to access the probe pads of the respective chips from outside after the packaging is completed. Currently, there is a demand for a method capable of performing a probing test even in a multi-chip semiconductor apparatus having a chip stack structure, which is completely packaged.

FIG. 2is a diagram illustrating the structure of a semiconductor chip110according to one embodiment of the present invention. The semiconductor chip110illustrated inFIG. 2includes a bump pad114and a probe pad115which are exposed to the outside of the semiconductor chip110and electrically connected through a specific conductive layer M1inside the semiconductor chip110.

More specifically, the semiconductor chip110includes a TSV (not illustrated.) The TSV may be formed by filling a hole formed therein. The bump pad114which is exposed to the outside of the semiconductor chip110is electrically connected to the TSV. The semiconductor chip110includes the probe pad115exposed to the outside of the semiconductor chip, in order to perform a probing test. The probe pad115and the bump pad114are electrically connected through the specific layer M1inside the semiconductor chip110.

Therefore, the probe pad115of the semiconductor chip110according to the embodiment illustrated byFIG. 2may be electrically connected to the bump pad114through the conductive layer M1, and electrically connected to the TSV through the bump pad114.

FIG. 3is a cross-sectional view of a multi-chip semiconductor apparatus100in which a plurality of semiconductor chips based on the structure ofFIG. 2are stacked.

The multi-chip semiconductor apparatus100illustrated inFIG. 3includes a plurality of semiconductor chips stacked over a substrate. The embodiment ofFIG. 3illustrates the multi-chip semiconductor100having first and second semiconductor chips110and120stacked therein.

The first and second semiconductor chips110and120each includes a TSV formed by filling a hole formed in the respective chip. In the embodiment illustrated byFIG. 3, the second semiconductor chip120has the same configuration as the first semiconductor chip110. In alternative embodiments, different semiconductor chips may have variations in the configuration of the chips. The following descriptions related to the embodiment ofFIG. 2will be focused on the configuration of the first semiconductor chip110.

The first semiconductor chip110includes a TSV111, first and second bump pads112and114, a probe pad115, and an internal circuit116. The TSV111is formed inside the first semiconductor chip110. The first and second bump pads112and114exposed to the outside of the semiconductor chip110are electrically connected to both ends of the TSV111. In such an embodiment, the second bump pad114formed on the same surface as the probe pad115is electrically connected to the TSV111through a first conductive path113. The first conductive path113includes a plurality of conductive layers and a plurality of conductive contacts formed between the respective conductive layers. In the embodiment ofFIG. 3, the conductive layer and the conductive contact may be formed of a material to pass a current, for example, a metallic material.

Further, in the embodiment ofFIG. 3, the internal circuit116is connected to the TSV111through a second conductive path117. That is, various voltages and/or signals used in the internal circuit116are transmitted to the first semiconductor chip110through the TSV111from outside semiconductor chip110, and are then transmitted to the internal circuit116from the TSV111through the second conductive path117inside semiconductor chip110. The second conductive path117may also include a plurality of conductive layers and a plurality of conductive contacts formed between the respective conductive layers.

The probe pad115is exposed to the outside of the semiconductor chip so as to perform a probing operation. The probe pad115may include various types of pads such as a power supply pad, a signal input/output pad, and a data input/output pad, in order to perform various tests on the semiconductor apparatus. The probe pad115is electrically connected through the internal circuit116and the third conductive pad118. The third conductive path118also includes a plurality of conductive layers and a plurality of contacts formed between the respective conductive layers. In one potential embodiment, the probe pad115may be formed by opening the uppermost conductive layer among the plurality of conductive layers forming the third conductive path118.

In one potential embodiment, specific conductive layers M1of the first and third conductive paths113and118are electrically connected to each other. Through the conductive layers M1, the probe pad115is electrically connected to the second bump pad114, and thus electrically to the TSV111.

The specific conductive layer M1may be formed at any one layer of the plurality of conductive layers of the first and third conductive paths113and118, excluding the uppermost conductive layer on which the second bump pad114and the probe pad115are formed. In this way, the second bump pad114and the probe pad115may be electrically connected without having an effect on signal interconnections and power interconnections which are arranged around the pads.

Then, as the bump pads of the first and second semiconductor chips110and120facing each other are connected through a bump119, the TSVs of the respective semiconductor chips110and120may be electrically connected to each other.

That is, in the multi-chip semiconductor apparatus according to the embodiment of the present invention, the probe pads formed on the respective semiconductor chips are electrically connected to the TSVs. Accordingly, although packaging is completed after the semiconductor chips are stacked, a probing test for the entire stack of semiconductor chips may be performed by probing the probe pads exposed to the outside of the stack.

FIG. 4is a diagram illustrating the structure of a semiconductor chip110_1according to another embodiment.

The semiconductor chip110_1illustrated inFIG. 4includes a plurality of bump pads114_1A and114_1B and a probe pad115_1which are exposed to the outside of the semiconductor chip and electrically connected through specific conductive layers M1_1A and M1_1B, respectively, inside the semiconductor chip110_1. The conductive layers M1_1A and M1_1B connecting the probe pad115_1to the respective bump pads114_1A and114_1B may be formed at the same layer, or at different layers.FIG. 4illustrates the first bump pad114_1A and the second bump pad114_1B, but the present invention is not limited thereto, and alternative embodiments may include alternative bump pad arrangements. The semiconductor chip110_1according to an alternative embodiment of the present invention may include a structure in which one probe pad such as probe pad115_1is connected to a plurality of bump pads.

More specifically, the semiconductor chip110_1includes a plurality of TSVs (not illustrated) formed by filling holes formed therein. The first and second bump pads114_1A and114_1B exposed to the outside of the semiconductor chip100_1are electrically connected to corresponding TSVs among the plurality of TSVs. The semiconductor chip110_1includes the probe pad115_1exposed to the outside to perform a probing test, and the probe pad115_1is electrically connected to the first and second bump pads114_1A and114_1B through the specific conductive layers M1_1A and M1_1B, respectively, inside the semiconductor chip100_1.

In certain embodiments, multi-chip semiconductor apparatus in which a plurality of semiconductor chips based on the structure ofFIG. 4are stacked has the same structure as illustrated inFIG. 3, except that one probe pad is electrically connected to a plurality of bump pads.

In such embodiments, the multi-chip semiconductor apparatus in which a plurality of semiconductor chips based on the structure ofFIG. 4are stacked includes a plurality of bump pads connected to the probe pad, thereby preparing for various defects which may occur during process and strengthening the connection between the semiconductor chips through the TSVs during a probe test.

FIG. 5is a block diagram of a multi-chip semiconductor apparatus according to another potential embodiment. The embodiment of a multi-chip semiconductor apparatus1000illustrated inFIG. 5has a structure in which a plurality of semiconductor chips are electrically connected through TSVs. For example,FIG. 5illustrates first and second semiconductor chips1100and1200and a TSV1200connecting the first and second semiconductor chips1100and1200. However, the present invention is not limited thereto, and in additional alternative embodiments, a larger number of semiconductor chips may be electrically connected and stacked through TSVs. In this embodiment illustrated byFIG. 5, the first semiconductor chip1100corresponds to the uppermost semiconductor chip which is electrically connected to an external substrate.

The first semiconductor chip1100includes a memory cell block1110, a bump pad1130, and a probe pad1150. The memory cell block1110is enabled when a chip select signal CSB0corresponding to the first semiconductor chip is activated. The first semiconductor chip1100is enabled in response to the first chip select signal CSB0. The memory cell block1110is configured to input/output data information according to a command applied during a normal operation. The memory cell block1110is also configured to input/output test information according to a command applied during a probe test operation.

The bump pad1130is electrically connected to the TSV1200and serves to transmit and receive signals of the semiconductor chip1100to and from outside the semiconductor chip1100. That is, when the first chip select signal CSB0is activated, the bump pad1130receives information from outside semiconductor chip1100and applies the received information to the memory cell block1110, or receives information from the memory cell block1110and outputs the received information to an output of semiconductor chip1100.

The probe pad1150serves to transmit and output signals of the semiconductor chip to and from outside of semiconductor chip1100during a probe test. That is, when the first chip select signal CSB0is activated during the probe test mode, the probe pad1150receives test information from outside semiconductor chip1100and applies the received test information to the memory cell block1110, or receives information from the memory cell block1110and outputs the received information to outside of semiconductor chip1100.

The second semiconductor chip1300also includes a memory cell block1310, a bump pad1330, and a probe pad1350.

The memory cell block1310is enabled when a chip select signal CSB1corresponding to the second semiconductor chip is activated, like the first semiconductor chip1100. The second semiconductor chip1300is enabled in response to the second chip select signal1300. The memory cell block1310inputs/outputs data information according to a command applied during a normal operation, and input/outputs test information according to a command applied during a probe test operation.

The bump pad1330is electrically connected to the TSV1200, and serves to transmit and receive signals of the semiconductor chip to and from outside semiconductor chip1300. In one potential embodiment, the bump pad1330of the second semiconductor chip1300is electrically connected to the bump pad1130of the first semiconductor chip1100positioned over the second semiconductor chip1300through the TSV1200, and transmits and receives signals to and from outside through the bump pad1130of the first semiconductor chip1100. That is, when the second chip select signal CSB1is activated, the bump pad1330receives information from outside and applies the received information to the memory cell block1310, or receives information from the memory cell block1310and outputs the received information to outside.

The probe pad1350may serve to transmit and receive signals of the semiconductor chip to and from outside during a probe test. In a state where a plurality of semiconductor chips are packaged, it may be difficult to perform a test by directly probing a probe pad, except for the uppermost semiconductor chip which exposes a probe pad. According to various embodiments, however, the probe pad1350is electrically connected to the bump pad1300. Therefore, a probe test for the second semiconductor chip1300positioned inside may be performed through the TSV1200. That is, by probing the probe pad1150of the first semiconductor chip1100positioned at the uppermost part, it is possible to perform a probe test on another semiconductor chip positioned inside, for example, the second semiconductor chip1300. Specifically, when the second chip select signal CSB1is activated during a probe test mode, test information is transmitted to or received from the probe pad1350. Then, the test information is transmitted to or received from outside the chip through the probe pad1150of the first semiconductor chip1100positioned at the uppermost part through the TSV1200.