Three-dimensional light-emitting devices and method for fabricating the same

A three-dimensional LED structure with vertically displaced active-region includes at least two groups of vertically displaced surfaces on a non-planar substrate. The first group of surfaces are separated from the second group of surfaces by a vertical distance in the growth direction of the LED structure. The first group of surfaces are connected to the second group of surfaces by sidewalls, respectively. The sidewalls can be inclined or vertical and have a sufficient height so that a layer such as an n-type layer, an active-region, or a p-type layer in a first LED structure deposited on the first group of surfaces and a corresponding layer such as an n-type layer, an active-region, or a p-type layer in a second LED structure deposited on the second group of surfaces are separated by the sidewalls. The two groups of surfaces may be vertically displaced from each other in certain areas of an LED chip, while merge into an integral surface in other areas. A method for fabricating the three-dimensional LED structure is also provided.

1. FIELD OF THE INVENTION

The present invention relates in general to light-emitting devices, and more particularly to light-emitting devices with vertically displaced active-region and reduced self-absorption and enhanced light extraction. The present invention also relates to method for fabricating light-emitting devices with vertically displaced active-region.

2. DESCRIPTION OF THE RELATED ART

Light-emitting devices in the prior art are composed by laminate structures, that is, an individual layer in a light-emitting structure such as a light-emitting diode (LED) chip usually is a continuous layer and lies in the same plane, and the structure is accomplished layer-by-layer by stacking layers of different composition and conductivity type. A conventional light-emitting device such as an LED usually includes a flat substrate, a continuous n-type layer formed on the substrate, a continuous active-region formed on the n-type layer, and a continuous p-type layer formed on the active-region. A cathode and an anode are connected to the n-type layer and the p-type layer, respectively. These LEDs for simplicity in description can be labeled as two-dimensional (2D) LEDs. Certain limitations related to 2D LEDs are proposed by the inventors of this application. First, as explained in U.S. patent application Ser. No. 12/761,708 filed on Apr. 16, 2010 by the same inventors, the content of which is hereby incorporated by reference in its entirety, the conventional 2D LED structure can exert lateral waveguide effect and result in strong light self-absorption within the n-type layer, the active-region and the p-type layer, especially within the active-region. Second, the continuous laminate structure does not favor for strain-relaxation in the n-type layer, the active-region and the p-type layer. And thirdly, for piezoelectric materials, such as III-V nitrides and II-VI oxides, the accumulated strain in the continuous laminate structure means poor light-generation efficiency in the active-region.

There are some modifications to alleviate the abovementioned limitations related to 2D LEDs in literature. Methods like surface roughening (modifying continuity of the ending surface, e.g. U.S. Pat. Nos. 7,422,962, 7,355,210), substrate patterning (modifying continuity of the starting surface, e.g. U.S. Pat. No. 7,683,386), and photonic crystal incorporation (modifying continuity of layers close to active-region, e.g. U.S. Pat. Nos. 5,955,749, 7,166,870, 7,615,398, 7,173,289, 7,642,108, 7,652,295, 7,250,635) were introduced in the prior art. In the inventors' previous U.S. patent application Ser. No. 12/824,097 filed on Jun. 25, 2010, the content of which is hereby incorporated by reference in its entirety, the active-region is displaced to interrupt the conventional laminate structure. Optionally, active-region grown on non-planar surfaces is also proposed in US patent application publication No. 2006/0060833.

3. SUMMARY OF THE INVENTION

The present invention discloses three-dimensional (3D) LED structures with vertically displaced active-region to overcome or relieve the problems associated with the prior art 2D LED structures.

According to one aspect of the present invention, a 3D LED epitaxial structure starts on a non-planar substrate or template layer which includes at least two groups of vertically displaced surfaces. The second group of surfaces are separated from the first group of surfaces by a vertical distance in the growth direction of the LED structure. The first group of surfaces are connected to the second group of surfaces by sidewalls, respectively. The sidewalls can be inclined or vertical or any other proper shape and have a sufficient height so that a layer such as an n-type layer, an active-region, or a p-type layer in a first LED structure deposited on the first group of surfaces and a corresponding layer such as an n-type layer, an active-region, or a p-type layer in a second LED structure deposited on the second group of surfaces are separated by the sidewalls. In other words, a layer such as an n-type layer, an active-region, and a p-type layer does not continuously grow over the sidewalls from the first group of surfaces to the second group surfaces. The two groups of surfaces may or may not share overlapping portions. In other words, the two groups of surfaces may be vertically displaced from each other in certain areas of an LED chip, while merge into a single or an integral surface in other areas. Upon epitaxial growth, a first LED structure is deposited on the first surfaces and a second LED structure on the second surfaces. The LED structure at least comprises an n-type layer, an active-region, and a p-type layer. The vertical distance can be chosen so that the p-type layer of the first LED structure reaches and is in contact with the n-type layer of the second LED structure. The vertical distance can also be chosen so that the p-type layer of the first LED structure does not reach and is not in contact with the n-type layer of the second LED structure, i.e., the first and second LED structures are completely separated from each other.

According to another aspect of the present invention, a light emitting diode (LED) chip is provided which comprises:a substrate including an integral region, a separating region and a slope region there between;a mesa formed on the substrate, wherein the upper surface of the mesa is vertically displaced relative to the upper surface of the substrate exposed by the mesa in the separating region, and the upper surface of the substrate exposed by the mesa in the separating region is connected to the upper surface of the mesa in the integral region via a slope surface in the slope region;a first LED structure formed on the upper surface of the substrate exposed by the mesa in the separating region and a second LED structure formed on the upper surface of the mesa in the separating region, wherein the first LED structure comprises a first n-type layer, a first active-region, and a first p-type layer, the second LED structure comprises a second n-type layer, a second active-region, and a second p-type layer, and the first and second LED structures are separated from each other in the separating region, while in the integral region, the first and second n-type layers merge into a single n-type layer, the first and second active-regions merge into a single active-region, and the first and second p-type layers merge into a single p-type layer.

The mesa can be an integral part of the substrate.

The light emitting diode (LED) chip may further comprise a template layer between the substrate and the mesa, wherein the mesa is formed on the template layer, the upper surface of the mesa is vertically displaced relative to the upper surface of the template layer exposed by the mesa in the separating region, and the upper surface of the template layer exposed by the mesa in the separating region is connected to the upper surface of the mesa in the integral region via a slope surface in the slope region, and the first LED structure is formed on the upper surface of the template layer exposed by the mesa in the separating region.

The mesa can be an integral part of the template layer, or a single insulating layer.

The mesa may comprise an insulating top layer, a mid layer, and a bottom layer, and when the first n-type layer in the first LED structure is grown from the substrate, the mid layer is in contact with the first p-type layer and the first active-region via its sidewall, and the bottom layer is in contact with the first active-region and the first n-type layer via its sidewall, while when the first p-type layer in the first LED structure is grown from the substrate, the mid layer is in contact with the first n-type layer and the first active-region via its sidewall, and the bottom layer is in contact with the first active-region and the first p-type layer via its sidewall.

When the first n-type layer in the first LED structure is grown from the substrate, the mid layer is an insulating layer and the bottom layer is an n-type layer, or the mid layer is a p-type layer and the bottom layer is an insulating layer, while when the first p-type layer in the first LED structure is grown from the substrate, the mid layer is an insulating layer and the bottom layer is a p-type layer, or the mid layer is an n-type layer and the bottom layer is an insulating layer.

The light emitting diode (LED) chip may further comprise a gap in the slope region, which separates the first and second LED structures in the slope region.

According to one aspect of the present invention, a light emitting diode (LED) chip is provided which comprises:a base for epitaxial growth thereon, having an integral region, a separating region and a slope region located between, wherein there are at least a group of first surfaces and a group of second surfaces vertically displaced from the first surfaces in the separating region, and the first surfaces and the second surfaces merge into a single surface in the integral region via a slope surface in the slope region;a first LED structure formed on the first surfaces in the separating region and a second LED structure formed on the second surfaces in the separating region, wherein the first LED structure comprises a first n-type layer, a first active-region, and a first p-type layer, the second LED structure comprises a second n-type layer, a second active-region, and a second p-type layer, and the first and second LED structures are separated from each other in the separating region, while in the integral region, the first and second n-type layers merge into a single n-type layer, the first and second active-regions merge into a single active-region, and the first and second p-type layers merge into a single p-type layer, via the slope surface in the slope region.

The first surfaces and the second surfaces are connected by sidewalls, preferably vertical sidewalls.

The base can be a single substrate. The base can include a substrate with vertically displaced upper surfaces and a template layer conformably formed on the substrate. The base can include a flat substrate and a template layer with vertically displaced upper surfaces. The base can include a flat substrate and a mesa of predetermined pattern formed on the substrate. The base can include a flat substrate, a flat template layer formed on the substrate and a mesa of predetermined pattern formed on the flat template layer, wherein the upper surfaces of the mesa in the separating region constitute the second surfaces and the upper surfaces of the template layer exposed by the mesa in the separating region constitute the first surfaces.

The mesa can comprise an insulating top layer, a mid layer, and a bottom layer, and when the first n-type layer in the first LED structure is grown from the base, the mid layer is in contact with the first p-type layer and the first active-region via its sidewall, and the bottom layer is in contact with the first active-region and the first n-type layer via its sidewall, while when the first p-type layer in the first LED structure is grown from the base, the mid layer is in contact with the first n-type layer and the first active-region via its sidewall, and the bottom layer is in contact with the first active-region and the first p-type layer via its sidewall.

When the first n-type layer in the first LED structure is grown from the base, the mid layer is an insulating layer and the bottom layer is an n-type layer, or the mid layer is a p-type layer and the bottom layer is an insulating layer, while when the first p-type layer in the first LED structure is grown from the base, the mid layer is an insulating layer and the bottom layer is a p-type layer, or the mid layer is an n-type layer and the bottom layer is an insulating layer.

The light emitting diode (LED) chip may further comprise a gap in the slope region, which separates the first and second LED structures in the slope region.

According to one aspect of the present invention, a light emitting diode (LED) chip is provided which comprises:a substrate;a mesa formed on the substrate, wherein the upper surface of the mesa is vertically displaced relative to the upper surface of the substrate exposed by the mesa;a first LED structure formed on the upper surface of the substrate exposed by the mesa and a second LED structure formed on the upper surface of the mesa, wherein the first LED structure comprises a first n-type layer, a first active-region, and a first p-type layer, the second LED structure comprises a second n-type layer, a second active-region, and a second p-type layer; andif the first and second n-type layers are grown from the substrate and the mesa, the first p-type layer is in contact with the second n-type layer via its sidewall, and if the first and second p-type layers are grown from the substrate and the mesa, the first n-type layer is in contact with the second p-type layer via its sidewall.

The mesa can be an integral part of the substrate.

The light emitting diode (LED) chip may further comprise a template layer between the substrate and the mesa, wherein the mesa is formed on the template layer, the upper surface of the mesa is vertically displaced relative to the upper surface of the template layer exposed by the mesa, and the first LED structure is formed on the upper surface of the template layer exposed by the mesa.

The mesa can be an integral part of the template layer.

The mesa can comprise a top layer and a bottom layer, and when the first and second n-type layers are grown from the substrate and mesa, the top layer is in contact with the first p-type layer and the first active-region via its sidewall, and the bottom layer is in contact with the first active-region and the first n-type layer via its sidewall, and the top layer is an insulating layer and the bottom layer is an n-type layer, or the top layer is a p-type layer and the bottom layer is an insulating layer, while when the first and second p-type layers are grown from the substrate and the mesa, the top layer is in contact with the first n-type layer and the first active-region via its sidewall, and the bottom layer is in contact with the first active-region and the first p-type layer via its sidewall, the top layer is an insulating layer and the bottom layer is a p-type layer, or the mid layer is an n-type layer and the bottom layer is an insulating layer.

According to one aspect of the present invention, a light emitting diode (LED) chip is provided which comprises:a substrate;a mesa formed on the substrate, wherein the upper surface of the mesa is vertically displaced relative to the upper surface of the substrate exposed by the mesa;a first LED structure formed on the upper surface of the substrate exposed by the mesa and a second LED structure formed on the upper surface of the mesa, wherein the first and second LED structures are completely separated by the mesa.

The mesa can be an integral part of the substrate.

The light emitting diode (LED) chip may further comprises a template layer between the substrate and the mesa, wherein the mesa is formed on the template layer, the upper surface of the mesa is vertically displaced relative to the upper surface of the template layer exposed by the mesa, and the first LED structure is formed on the upper surface of the template layer exposed by the mesa.

The mesa can be an integral part of the template layer.

The mesa can comprise a top insulating layer and a bottom layer, and when the first and second n-type layers are grown from the substrate and mesa, the top layer is in contact with the first p-type layer and the first active-region via its sidewall, and the bottom layer is in contact with the first active-region and the first n-type layer via its sidewall, and the bottom layer is an n-type layer or an insulating layer, while when the first and second p-type layers are grown from the substrate and the mesa, the top layer is in contact with the first n-type layer and the first active-region via its sidewall, and the bottom layer is in contact with the first active-region and the first p-type layer via its sidewall, the bottom layer is a p-type layer or an insulating layer.

According to one aspect of the present invention, a method for manufacturing a light emitting device is provided which comprises:providing a substrate having an integral region, a separating region and a slope region there between;forming a mesa on the substrate, wherein the upper surface of the mesa is vertically displaced relative to the upper surface of the substrate exposed by the mesa in the separating region, and the upper surface of the substrate exposed by the mesa in the separating region is connected to the upper surface of the mesa in the integral region via a slope surface in the slope region;depositing an LED structure on the mesa and the substrate to form a first LED structure on the upper surface of the substrate exposed by the mesa in the separating region and a second LED structure on the upper surface of the mesa in the separating region, wherein the first and second LED structures are separated from each other in the separating region and merge into a single LED structure in the integral region, wherein the first LED structure comprises a first n-type layer, a first active-region, and a first p-type layer, the second LED structure comprises a second n-type layer, a second active-region, and a second p-type layer,

The step of depositing the LED structure may comprises:depositing an n-type layer on the mesa and the substrate to form the first n-type layer on the upper surface of the substrate exposed by the mesa in the separating region and the second n-type layer on the upper surface of the mesa in the separating region;depositing an active-region on the n-type layer to form the first active-region on the first n-type layer and the second active-region on the second n-type layer;depositing a p-type layer on the active-region to form the first p-type layer on the first active-region and the second p-type layer on the second active-region;wherein in the integral region and via the slope region, the first and second n-type layers merge into a single n-type layer, the first and second active-regions merge into a single active-region, and the first and second p-type layers merge into a single p-type layer.

The method may further comprise depositing a template layer on the substrate before forming the mesa, wherein the mesa is formed on the template layer.

The step of forming the mesa may comprise:depositing a mesa layer on the template layer;patterning and etching the mesa layer to form the mesa of predetermined pattern;forming passivation layer on the mesa and the template layer, but exposing the template layer and sidewalls of the mesa in the slope region;growing a film with tilted upper surface on the exposed template layer and the sidewalls of the mesa in the slope region.

DETAILED DESCRIPTION OF EMBODIMENTS

FIG. 1illustrates a schematic cross-sectional view of an LED chip, or a portion of the LED chip, according to an embodiment of the present invention. The LED chip shown inFIG. 1includes a substrate10and an optional template layer20. A template layer here means one or more substantially thick epitaxial layer(s) deposited on a substrate. In the field of Group III-V nitride light-emitting devices, a substrate can be made of sapphire, silicon, gallium arsenide, silicon carbide, gallium nitride and the like. Epitaxial layer made of such as gallium nitride (GaN), aluminum nitride (AlN), indium nitride (InN), and their alloys can be used as a template layer, deposited on a substrate for following LED structure growth.

Shown inFIG. 1the substrate10is flat, and the template layer20is also flat on which a mesa25is formed. Here the template layer20can be conductive, for example, with n-type conductivity, and mesa25can be insulating, or, at least a portion of mesa25can be insulting. Upon the epitaxial growth of an LED structure, LED structure2and LED structure1are deposited on mesa25protruding from the upper surface of template layer20and on the upper surface of template layer20exposed by mesa25, respectively. The LED structure1in this embodiment comprises an n-type layer301, an active-region401, and a p-type layer501. The LED structure2in this embodiment comprises an n-type layer302, an active-region402, and a p-type layer502. In some embodiments, mesa25includes a top layer252in contact with a portion of active-region401and p-layer501along its vertical sidewall, and a bottom layer251in contact with a portion of active-region401and n-layer301along its vertical sidewall. The top layer252can be insulating or of p-type conductivity when the bottom layer251is insulating. The bottom layer251can be insulating or of n-type conductivity when the top layer252is insulating. The top layer252and the bottom layer251can be separate layers or within one layer with changing compositions. Mesa25also can be a single insulating layer. Mesa25or its top layer252and bottom layer251can be made from GaN, or AlGaN.

The height of mesa25can be in the range of 0.5 μm-10 μm, preferably from 2 μm to 5 μm. For the embodiment shown inFIG. 1, the height of mesa25should be smaller than the thickness sum of n-type layer301, active-region401and p-type layer501, while larger than the thickness sum of n-type layer301and active-region401. This means that p-type layer501and n-type layer302are in contact with each other. Via standard device fabrication process, anode contact713is fabricated on p-type layer502of LED structure2, and cathode contact711is fabricated on n-type layer301of LED structure1, whereas conductive contact712, which is in contact with both p-type layer501and n-type layer302, connects current path from LED structure2to LED structure1. In this embodiment, LED structure2and LED structure1are connected in series. The cathode contact711, conductive contact712, and anode contact713can be made of metals such as copper, nickel, gold, titanium, aluminum, palladium and the like, or transparent conducting oxides such as zinc oxide, indium tin oxide (ITO), and the like. In one embodiment, conductive contact712is formed on p-type layer501and only laterally contacts layer n-type302via its sidewall to maximize the emitting area of LED structure2. In another embodiment, conductive contact712can also be made to cover a portion of the upper surface of n-type layer302by standard lithography and etch process as shown inFIG. 1, so that a better electrical connection is achieved between conductive contact712and n-type layer302. When conductive contact712only laterally contacts n-type layer302via its sidewall, n-type layer302has to be thick enough, for example, more than 5 microns.

In the embodiment shown inFIG. 1, an n-type layer is first grown over substrate10, for example on mesa25and the upper surface of template layer20exposed by mesa25, then an active-region and a p-type layer are grown sequentially. Similarly, a p-type layer can be first grown over substrate10. In this case, layer301and layer302will be a p-type layer, while layer501and layer502will be an n-type layer. Here the template layer20can be of p-type conductivity. The top layer252can be insulating or of n-type conductivity, when the bottom layer251is insulating, and the bottom layer251can be insulating or of p-type conductivity, when the top layer252is insulating.

Instead of forming a separate mesa25as shown inFIG. 1, mesa25can be formed as an integral part of substrate10by patterning and etching substrate10.

LED structure2can have any suitable patterns, such as a comb-shaped pattern as shown inFIG. 2, or a spiral-shaped pattern as shown inFIG. 9B. An exemplary perspective view of the embodiment inFIG. 1is shown inFIG. 2. As shown, LED structure2with a comb-shaped pattern has plurality of elongated rods or fingers and a base portion connecting the fingers. Four fingers are shown inFIG. 2, but it can contain any suitable number of fingers, for example, more than 10 fingers. The width of the finger can be in the range from 10 to 200 microns, preferably 50-100 microns, more preferably 20-50 microns. The distance between two fingers can be in the range from 5 to 50 microns.

The fabrication process of the LED structure shown inFIG. 1is described below, taking the LED structure with n-type layer first growing from the substrate as an example. A substrate10with a template layer20is formed by a method known in the art. Mesa25is formed on template20by epitaxial growth, patterning and etching. Mesa25can be formed by sequentially depositing a bottom layer251and a top layer252as two separate layers, or by changing compositions along the growth direction within one single layer. An n-type layer is epitaxially grown, forming an n-type layer301on upper surface of template layer20exposed by mesa25and an n-type layer302on top layer252of mesa25simultaneously. An active-region is epitaxially grown, forming an active-region401on n-type layer301and an active-region402on n-type layer302simultaneously. A p-type layer is epitaxially grown, forming a p-type layer501on active-region401and a p-type layer502on active-region402simultaneously. Then, the obtained structure is patterned and a portion of p-type layer501and active-region401is removed to expose n-type layer301, or to etch into n-type layer301forming a trench in p-type layer501, active-region401, and an upper portion of n-type layer301. Optionally, a portion of p-type layer502and active-region302can also be removed to expose n-type layer302or to etch into n-type layer302as shown inFIG. 1. A conductive layer is deposited, forming a cathode contact711on n-type layer301, a conductive contact712on p-type layer501, and an anode contact713on p-type layer502. All the patterning, etching, depositing, and epitaxial growing steps involved in the above process can use known method in the art. In similar manner, a p-type layer can be first grown on mesa25and template layer20, then sequentially growing an active-region and an -n-type layer.

FIG. 3illustrates a schematic cross-sectional view of an LED chip according to another embodiment of the present invention. The LED chip shown inFIG. 1and the LED chip shown inFIG. 3have similar structures except that, inFIG. 3, the height of mesa25is larger than the sum of the thicknesses of n-type layer301, active-region401and p-type layer501. This means that p-type layer501and n-type layer302are not in contact and are electrically isolated from each other by mesa25. In other words, LED structure1and LED structure2are completely separated from each other. The height of mesa25is in the range of 0.5 μm-10 μm, preferably from 2 μm to 5 μm. If LED structure2and LED structure1are completely separated by mesa25, parallel electrical connection of LED structure2and LED structure1can be realized by electrically connecting cathodes of LED structures1and2, and electrically connecting anodes of LED structures1and2, respectively, as illustrated inFIG. 4AandFIG. 4B. In the structure shown inFIG. 4A, cathode711′ of LED structure2which is in electrical contact with n-type layer302is connected to cathode711of LED structure1which is in electrical contact with n-type layer301via conductive wire701′, while anode713of LED structure2which is in electrical contact with p-type layer502is connected to anode713′ of LED structure1which is in electrical contact with p-type layer501via conductive wire702′. In the structure shown inFIG. 4B, the connection is achieved via metallization layers701and702.

The fabrication process of the LED structure shown inFIG. 3is similar to the fabrication process of the LED structure shown inFIG. 1except that a portion of the top surface of n-type layer302is exposed by etching and removing a corresponding portion of p-type layer502and active-region402and, then, a conductive layer is deposited, forming a cathode contact711on n-type layer301, an anode contact713′ on p-type layer501, a cathode contact711′ on n-type layer302, and an anode contact713on p-type layer502. Cathode contacts711and711′ is connected by a conductive wire701′, and anode contacts713and713′ is connected with a conductive wire702′ as shown inFIG. 4A. Optionally, a passivation layer, preferably made of silicon dioxide, or silicon nitride, is deposited via sputtering to cover the whole LED structures shown inFIGS. 3 and 4B, in order to cover the sidewalls of LED structure2. This passivation of the sidewalls of LED structure2can prevent electric short circuit between the PN junction of LED structure2and the metallization layers702and701. The passivation sputtering process forms a passivation layer601covering LED structure1and a passivation layer602covering LED structure2and the sidewalls of LED structure2. Passivation layers601and602are patterned and etched to expose a portion of cathode contacts711,711′ and anode contacts713,713′. Then a metallization process is conducted to form metallization layers701and702that connect cathode contacts711and711′ and anode contacts713and713′, respectively, as shown inFIG. 4B.

In still another embodiment, LED structures2and1are partially separated by mesa25, i.e., in one or more portions of a LED chip, LED structures2and1merge into a single LED structure, sharing a common n-type layer, a common active-region, and a common p-type layer, while in one or more other portions of the LED chip, the n-type layers, the active-regions, and the p-type layers of LED structures2and1are physically separated in vertical direction by mesa25as schematically illustrated inFIG. 5AandFIG. 5B.FIG. 5A-5Bshow schematic perspective views of a LED chip for a more straightforward understanding of the idea. As shown inFIG. 5A, LED structure1comprises an n-type layer301, an active-region401and a p-type layer501, and LED structure2comprises an n-type layer302, an active-region402and a p-type layer502. LED structure1and LED structure2merge into one LED structure in integral region102, i.e., n-type layer301and n-type layer302are integrated as one n-type layer, active-region401and active-region402are integrated as one active-region, and p-type layer501and p-type layer502are integrated as one p-type layer in this region. While LED structures1and2are vertically separated by mesa25or by any other suitable structure or layer in separating region192, i.e., n-type layer301and n-type layer302are vertically separated, active-region401and active-region402are vertically separated, and p-type layer501and p-type layer502are vertically separated in this region. Integral region102and separating region192are connected via a slope region122.

In the structure shown inFIG. 5A, there is the possibility that the sidewall of p-type layer501of LED structure1may contact with the sidewall of n-type layer302of LED structure2in slope region122. To avoid this situation, another preferred embodiment is illustrated inFIG. 5B. By forming an isolation gap132in slope region122, the sidewall contact between LED structure1and LED structure2is forbidden. Isolation gap132is deep enough to penetrate n-type layer302of LED structure2and has a width between 1 to 10 microns, preferably 1-5 microns. Isolation gap132may have a length similar to that of the slope region122, The length of isolation gap132can also be shorter than that of the slope region122as long as it can electrically isolate the sidewall of p-type layer501of LED structure1from the sidewall of n-type layer302of LED structure2in slope region122.

FIG. 5Cis the top view ofFIG. 5Bbut with four LED structures2instead of two LED structures2. It is shown that LED structure1and LED structure2merge into one LED structure in integral region102via slope region122, while isolation gaps132prevent short current path between LED structure1and LED structure2in slope region122.

FIG. 5Dis the top view of another embodiment similar to that shown inFIG. 5C, but with an additional integral region102and additional slope region122and isolation gaps132on the other end of elongated LED structures2for reduced connection resistance.

In the embodiments shown inFIGS. 5A-5D, the width W2of LED structure2can be in the range of 10 to 200 microns, preferably 50-100 microns, more preferably 20-50 microns, the distance W1between neighboring LED structures2can be from 20 to 100 microns. The ratio W2/W1can be in the range from 0.2 to 2.

AlthoughFIGS. 5A-5Dshow LED structures2as parallel elongated rods or fingers, LED structure2is not limited to any particular shape and pattern and can take any shape and pattern as long as it can provide a vertically displaced LED structure. For example, the top view shape of the LED structures2inFIGS. 5A and 5Bcan be truncated triangle, as shown inFIG. 9AandFIG. 9B. InFIG. 9A, the truncated portions of the triangles are merged into the integral region102, while inFIG. 9Bthe bases of the triangles are merged with the integral region102. These truncated triangles can be of any type of triangles, such as equilateral, isosceles, and scalene triangles. The arrangement of these truncated triangles can take any ordered or random patterns. The top view shape of the LED structures2can also be other polygons such as pentagon, hexagonal and octagon. The surfaces of LED structure1and LED structure2and the sidewalls of LED structure2can be roughened to enhance light extraction. Shown inFIG. 9Cthe top view of the LED structures2is circle with sidewalls roughened for enhanced light extraction.FIG. 9Dis the top view of a cross pattern design according to an embodiment of the present invention, in which LED structure1has a cross shape surrounded by LED structure2. Cross-shaped LED structure1is recessed relative to LED structure2in separating region192. Cross-shaped LED structure1and LED structure2merge into one single LED structure in integral region102via slope region122at four ends of the cross-shaped LED structure1. One LED chip as shown inFIGS. 5A-5Dcan contain one or more cross pattern shown inFIG. 9D. Similarly, concave polygon shaped LED structure1, such as a star shape, are also possible with slope region at the vertices. Shown inFIG. 9Eis a spiral pattern design according to an embodiment of the present invention, in which LED structure2is a spiral shaped wall and LED structure1is a corresponding spiral shaped trench, and LED structures1and2merge into a single LED structure at two ends of the spiral shaped wall and trench in integral region102via slope region122. The width W2of LED structure2can be in the range of 10 to 200 microns, preferably 50-100 microns, more preferably 20-50 microns, the distance W1between neighboring LED structures2(in this case, it is also the width of LED structure1) can be from 20 to 100 microns. The ration W2/W1can be in the range from 0.2 to 1.

FIGS. 6A-6BandFIGS. 7A-7Billustrate two approaches to make such a slope region122. The slope region can be made on substrate10or template layer20after fabrication of integral region102and separating region192. HereFIGS. 6A-6BandFIGS. 7A-7Bpresent the cross-sectional views along the cutting line AA′ ofFIG. 5B.

As seen inFIG. 6A, via standard lithography and etch process, a mesa is formed on template layer20, which includes a mesa120in integral region102and a mesa25(not shown) in separating region192in a suitable pattern. Mesa120and mesa25may have the same height and share a continuous upper surface. With the exception of the areas that are to be used for forming slope region122, the whole surface area, including mesa25, mesa120and the exposed template layer20is coated with a passivation layer such as silicon dioxide, which includes passivation layer622in integral region102and passivation layer621in separating region192. The mesa can be made from one or more layer and epitaxially grown on template layer20or on substrate10, or the mesa can be an integral part of template layer20or substrate10. The structure inFIG. 6Ais then loaded into an epitaxial reactor such as Metalorganic Chemical Vapor Deposition (MOCVD) and Molecular Beam Epitaxy (MBE) reactors. Preferably the structure shown inFIG. 6Ais loaded into a Hydride Vapor Phase Epitaxy (HVPE) reactor, taking advantage of the fast growth rate of HVPE, which can be as high as 300 micron/hour. Epitaxial growth will start from the exposed surface of template layer20in region122and the sidewall of mesa120, forming a film1201with tilted upper surface122′. Growth on top of passivation layers621and622will result in polycrystalline films, which together with passivation layers621and622can be easily removed, for example, by wet chemical etching. After removing passivation layers621and622by etching, a structure shown inFIG. 6Bis obtained, which is then loaded into an epitaxial reactor for epitaxial growth of a LED structure thereon according to any known epitaxial growth method in the art, forming LED structure1and LED structure2simultaneously as shown inFIG. 5A. It is noted that because the thickness of passivation layer621is very small, for example, 70-150 nm, for example approximately 100 nm, so the step between layer1201and layer20is very small too. This step can be easily smoothened out during the following LED structure growth.

An alternative approach to make such a slope region122is illustrated inFIGS. 7A-7B, by adding one or more additional mesa120′ with a height smaller that that of mesa120. Similar to the method as explained previously inFIGS. 6A and 6B, by epitaxial growth and chemical etching, a film1201with a tilted surface122′ is obtained, with a smaller slope. It is understood that three or more mesas with different height can be applied to make a smoother and less steep slope region122. Mesa120′ can be fabricated by known method, for example, by patterning and etching a selected portion or portions of mesa120after forming mesa120and mesa25in the process discussed in connection withFIGS. 6A and 6B.

In the embodiments represented byFIGS. 5A and 5B, the electrical connection can be achieved according toFIGS. 8A-8C. Here mesa25includes three layers or portions: top layer253, mid layer252, and bottom layer251. Bottom layer251can be either n-type or insulating, mid layer252can be either insulating or p-type, similar to layers251and252in the embodiments shown inFIGS. 1 and 3. Top layer253is insulating. Mesa25can also be made a single insulating layer or an integral part of template layer20or substrate10. Upon epitaxial growth of an n-type layer, an active-region, and a p-type layer on a structure such as that shown inFIGS. 6B and 7B, LED structure2and LED structure1are formed on mesa25and the surrounding exposed template layer20, respectively, in separating region192. LED structure2includes n-type layer302, active-region402and p-type layer502. LED structure1includes n-type layer301, active-region401, and p-type layer501. As the sidewall of mesa25is steep and high enough, no layers in the LED structure continuously grow over the sidewall of mesa25, thus, LED structure1is separated from LED structure2in separating region192. Such discontinued LED structure is favorable in terms of reducing lateral light absorption and stress in the active-region and that in turn will improve light extraction efficiency and structural stability of a LED device. LED structures1and2merge into a single LED structure on mesa120in integral region102, the single LED structure includes an n-type layer that connects both n-type layers301and302, an active-region that connects both active-regions401and402, and a p-type layer that connects both p-type layers501and502. A p-type current spreading layer, preferably a transparent conducting layer such as indium tin oxide (ITO), is deposited, for example via sputtering or e-beam evaporation, forming a p-type current spreading layer801on p-type layer501and a p-type current spreading layer802on p-type layer502simultaneously. A portion of the p-type current spreading layer is also formed in integral region102. The thickness of p-type current spreading layer801is selected so to preserve a substantial vertical gap between the top surface of p-type current spreading layer801and the bottom surface of n-type layer302, i.e., p-type current spreading layer801and n-type layer302have to be isolated along the sidewall of mesa25. Then, a first insulating dielectric layer is deposited on top of p-type current spreading layers801and802as well as the portion of the p-type current spreading layer in integral region102, forming an insulating dielectric layer611on p-type current spreading layer801and an insulating dielectric layer612on p-type current spreading layer802. The first insulating dielectric layer preferably is made of silicon dioxide or silicon nitride, although other insulating materials can also be used, and its thickness is in the range of 100 nm to 1000 nm. Thereafter, an n-type current spreading layer901, preferably a transparent conducting layer such as indium tin oxide (ITO), is deposited on insulating dielectric layer611in separating region192, which can be achieved by depositing an n-type current spreading layer over the entire structure and, then, removing the unwanted portions of the n-type current spreading layer by etching to leave n-type current spreading layer901only in separating region192, so that n-type current spreading layer901is not in contact with p-type layer502. N-type current spreading layer901is in contact with n-type layer302via their sidewalls, and its thickness is preferably to be thicker than that of n-type layer302, but thinner than the sum of n-type layer302and active-region402. N-type current spreading layer901may or may not be in contact with active-region402. Next, a passivation layer613, such as silicon dioxide, is formed on top of n-type current spreading layer901by known method. And finally, anode contact713and cathode contact711are fabricated by a standard lithography and metallization process on p-type current spreading layer802and n-type current spreading layer901, respectively.

As p-type current spreading layers801and802merge into a single p-type current spreading layer in region102, holes injected from anode contact713will flow through p-type current spreading layer802and p-type layer502into active-region402and, in parallel, holes from anode contact713will also flow through p-type current spreading layer801and p-type layer501into active-region401. Similarly, as n-type layers301and302merge into a single n-type layer in region102, electrons injected from cathode contact711will flow through n-type current spreading layer901and n-type302into active-region402and, in parallel, electrons from cathode contact711will also flow through n-type current spreading layer901and n-type layer302to n-type layer301, then into active-region401. This means that LED structure2and1are electrically connected in parallel, via a true 3D interconnection approach.

To reduce electrical connection resistance between cathode contact and n-type layers in the LED structure, the number and density of LED structures2in one LED chip can be increased. The number of LED structures2in one LED chip, such as the elongated rod shaped LED structure2shown inFIGS. 5A-5Dcan be in the range from 1 to 50, preferably from 3-20, more preferably from 5-10. Further, an additional cathode contact712can be added, as shown inFIG. 8B.

The structure shown inFIG. 8Bis the same as that shown inFIG. 8Aexcept that an additional cathode contact712is provided on n-type layer301. The structure shown inFIG. 8Bcan be fabricated as follows. After forming n-type current spreading layer901, but before forming passivation layer613as discussed above in connection withFIG. 8A, a portion of n-type current spreading layer901, insulating dielectric layer611, p-type current spreading layer801, p-type layer501and active-region401is removed to expose n-type layer301or to etch into n-type layer301, forming a trench in n-type current spreading layer901, insulating dielectric layer611, p-type current spreading layer801, p-type layer501, and active-region401. A conductive layer is then deposited to form a cathode contact711on n-type current spreading layer901, an additional cathode contact712on n-type layer301, and an anode contact713on p-type current spreading layer802. The two cathode contacts711and712are connected via wire bonding to a cathode. All the patterning, etching, depositing, and epitaxial growing steps involved in the above process can use known method in the art.

The n-side series resistance of the LED embodiments shown inFIG. 8A-8Cis expect to be larger than the p-side series resistance since n-current spreading layer901is in contact with n-layer302of LED structure2via sidewall contacting. To reduce the n-side series resistance, the number and density of LED structures2can be increased. Besides, the width of LED structure2can be smaller than the distance W1between neighboring LED structures2. The width W2of LED structure2can be in the range of 10 to 200 microns, preferably 50-100 microns, more preferably 20-50 microns, the width W1of LED structure can be from 20 to 200 microns, preferably 20-50 microns. The ration W2/W1can be in the range from 0.2 to 1.

A thin-film structure is realized in an embodiment shown inFIG. 8C. The thin-film structure shown inFIG. 8Cis the same as the structure shown inFIG. 8Aexcept that substrate10is removed or replaced by a conductive substrate704. Conductive substrate704can be a transparent conductive material such as an ITO or ZnO wafer, or a conductive metal or silicon wafer coated with reflector on the top surface. InFIG. 8Can additional cathode contact714is formed on the bottom of a conductive substrate704. The two cathode contacts711and714are connected via wire bonding to a cathode.

Presented inFIG. 10is the schematic view of a wafer, showing the arrangement of many LED chips according to the present invention on a wafer. One wafer can contain 1500 to 20,000 LED chips depending on the chip size. Typically, the dimension of a single LED chip can be from several hundred microns to several millimeters.

The present invention has been described using exemplary embodiments. However, it is to be understood that the scope of the present invention is not limited to the disclosed embodiments. On the contrary, it is intended to cover various modifications and similar arrangement or equivalents. The scope of the claims, therefore, should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements and equivalents. For example, the above embodiments and drawings (for example,FIGS. 5A and 5B) show and describe that the lower LED structure1merges into an upper integral LED structure in integral region102via slope region122, while LED structure2is at the same level with the integral LED structure. Clearly, the integral LED structure can be made at the same level with the lower LED structure1, while LED structure2is higher than the integral LED structure.