Electrostatic discharge power clamp with fail-safe design

Electrostatic discharge protection circuits and methods of fabricating an electrostatic discharge protection circuit, as well as methods of protecting an integrated circuit from a transient electrostatic discharge event. The electrostatic discharge protection circuit includes a power clamp device, a first timing circuit with a first resistor and a first capacitor that is coupled with the first resistor at a first node, and a second timing circuit including a second resistor and a second capacitor that is coupled with the second resistor at a second node. The electrostatic discharge protection circuit further includes a logic gate with a first input coupled with the first node, a second input coupled with the second node, and an output coupled with the power clamp device. The logic gate responds to voltages at the first and second nodes to control the impedance state of the power clamp device.

BACKGROUND

The invention generally relates to semiconductor manufacturing and integrated circuits and, more particularly, to electrostatic discharge protection circuits and methods of fabricating an electrostatic discharge protection circuit, as well as methods of protecting an integrated circuit from electrostatic discharge.

An integrated circuit may be exposed to transient electrostatic discharge (ESD) events that can direct potentially large and damaging ESD currents to the integrated circuits of the chip. An ESD event involves an electrical discharge from a source, such as the human body or a metallic object, over a short duration and can deliver a large amount of current to the integrated circuit. An integrated circuit may be protected from ESD events by, for example, incorporating an ESD protection circuit into the chip. If an ESD event occurs, the ESD protection circuit triggers a power clamp device, such as a silicon-controlled rectifier, to enter a low-impedance, conductive state that directs the ESD current to ground and away from the integrated circuit. The ESD protection device holds the power clamp device in its conductive state until the ESD current is drained and the ESD voltage is discharged to an acceptable level.

Improved electrostatic discharge protection circuits that provide electrostatic discharge protection and methods of fabricating an electrostatic discharge protection circuit, as well as improved methods of protecting an integrated circuit from a transient electrostatic discharge event, are needed.

SUMMARY

In an embodiment of the invention, an electrostatic discharge protection circuit includes a power clamp device, a first timing circuit with a first resistor and a first capacitor that is coupled with the first resistor at a first node, and a second timing circuit including a second resistor and a second capacitor that is coupled with the second resistor at a second node. The electrostatic discharge protection circuit further includes a logic gate with a first input coupled with the first node, a second input coupled with the second node, and an output coupled with the power clamp device.

In an embodiment of the invention, a method is provided for fabricating an electrostatic discharge protection circuit for a chip. The method includes forming, using a substrate, a first resistor and a first capacitor of a first timing circuit, and forming, using the substrate, a second resistor and a second capacitor of a second timing circuit. A power clamp device is formed using the substrate. The method further includes forming, using the substrate, a logic gate including a first input coupled with a first node coupling the first capacitor with the first resistor, a second input coupled with a second node between the second capacitor and the second resistor, and an output coupled with the power clamp device.

In another embodiment of the invention, a method is provided for operating an electrostatic discharge protection circuit when power is applied to a chip and the electrostatic discharge protection circuit on the chip. The method includes supplying a first voltage to a first input of a logic gate from a first node between a first resistor and a first capacitor of a first timing circuit, and supplying a second voltage to a second input of the logic gate from a second node between a second resistor and a second capacitor of a second timing circuit. The method further includes outputting a third voltage from the logic gate to a power clamp device based on the first voltage and the second voltage. The third voltage places the power clamp device in a high-impedance state.

In another embodiment of the invention, an electrostatic discharge protection circuit includes a power clamp device, a timing circuit, a first field-effect transistor, and a second field-effect transistor. The timing circuit includes a resistor, a first capacitor that is coupled with the resistor at a node, and a second capacitor that is coupled with the resistor at the node. The field-effect transistor includes a first gate and is coupled in series with the first capacitor between a positive rail of a power supply and a negative rail of the power supply. The electrostatic discharge protection circuit further includes a decoder with an output line coupled with gate of the field-effect transistor. The decoder is configured to selectively output a voltage on the output line to the gate of the field-effect transistor.

DETAILED DESCRIPTION

With reference toFIGS. 1, 2and in accordance with an embodiment of the invention, an electrostatic discharge (ESD) protection circuit10for a chip generally includes a plurality of timing circuits12,13that are arranged in branches, a driving circuit14, a NOR gate40, and a power clamp device16coupled by the driving circuit14with the timing circuit12. The timing circuits12,13are coupled between a positive (VDD) rail18of a power supply and a negative (VSS) rail20of the power supply. The VDDrail18may be connected with a VDDpower pin and the VSSrail20may be connected with a VSSpower pin. Internal circuits22of a chip, which are protected by the ESD protection circuit10on the chip, are also connected with the VDDrail18and VSSrail20. The timing circuits12,13, the driving circuit14, the NOR gate40, and the power clamp device16may be located on the chip.

The timing circuits12,13are coupled in parallel between the VDDrail18and the VSSrail20. The timing circuit12includes a resistor28and a capacitor32that are coupled in series between the VDDrail18and the VSSrail20with the resistor28coupled to the capacitor32at a node36. The timing circuit13includes a resistor30and a capacitor34that are also coupled in series between the VDDrail18and the VSSrail20with the resistor30coupled to the capacitor34at a node38. Additional timing circuits like timing circuits12,13may be provided with correlated pairs of resistors and capacitors coupled in series between the VDDrail18and the VSSrail20to provide additional redundancy.

The driving circuit14of the ESD protection circuit10includes a NOR gate40and a plurality of inverters42,44that couple the NOR gate40with the power clamp device16. The NOR gate40, which is comprised of p-channel transistors and/or n-channel transistors, includes a plurality of inputs that may be equal to the number of correlated pairs of resistors28,30and capacitors32,34, which in turn is equal to the number of nodes36,38and an output that is coupled with an input of the inverter42. The NOR gate40is a digital logic gate that implements a logical NOR truth table with Boolean logic applied to input logic in order to generate output logic. If all of the inputs to the NOR gate40from the nodes36,38are at a voltage equal to logic 1 (i.e., high or VDD), the voltage for the output logic signal is equal to logic 0 (i.e., low or VSS). If at least one of the inputs to the NOR gate40from the nodes36,38is at a voltage equal to logic 1, the voltage for the output logic signal is equal to logic 0. If all of the inputs to the NOR gate40from the nodes36,38are biased at a voltage equal to logic 0, the voltage for the logic signal output by the NOR gate40is equal to logic 1.

The inverter44has an input that is coupled with an output from the inverter42and an output that is coupled at a node46with the power clamp device16. Each of the inverters42,44is a digital logic gate that implements a logical negation truth table with Boolean logic applied to input logic in order to generate output logic. If the input to either of the inverters42,44is equal to a voltage equal to logic 1 (i.e., high or VDD), the voltage for the respective output logic signal is equal to logic 0 (i.e., low or VSS). If the input to either of the inverters42,44is equal to a voltage equal to logic 0, the voltage for the respective output logic signal is equal to logic 1.

Generally, the driving circuit14includes one or more inverters42,44and features a two-stage configuration in the representative embodiment. However, the number of inverters42,44may differ from the representative two-stage configuration inFIG. 1. For example, the number of inverters42,44may comprise a four-stage configuration in order to output the correct logic in the representative embodiment. While the NOR gate40is indicated as part of the driving circuit14, the NOR gate40may be considered to be distinct from the driving circuit in some embodiments.

When the chip is unpowered and in response to a transient ESD event, the power clamp device16may be triggered to switch from its high-impedance state to its low-impedance state by the operation of the timing circuits12,13as orchestrated by the NOR gate40. In its low-impedance state, the power clamp device16provides a current path to the VSSrail20with a current-carrying capacity that is sufficient to dissipate the large current produced by a transient ESD event at the VDDpower pin or the VSSrail power pin.

The power clamp device16may be a metal-oxide-semiconductor transistor of large dimensions (e.g., a BigFET) having a gate with a width greater than one thousand microns that is coupled with the output from the driving circuit14, and may be constructed as either a p-channel field-effect transistor or an n-channel field-effect transistor. In the representative embodiment, the power clamp device16is an n-channel field-effect transistor. In alternative embodiments, the power clamp device16may comprise a silicon controlled rectifier or a bipolar junction transistor.

The resistors28,30of the timing circuit12each have a discrete resistance value and, in a representative embodiment, may be comprised of a polysilicon film resistor48(FIG. 2) that is formed by patterning a layer of polysilicon. The resistance of the polysilicon film resistor48is based on its dimensions and the resistivity of the polysilicon. In alternative embodiments, the resistors28,30may comprise diffusion resistors, well resistors, etc.

The capacitors32,34of the timing circuit12each have a discrete capacitance value. In the representative embodiment, each of the capacitors32,34may be comprised of one or more deep trench capacitors50. Each deep trench capacitor50includes capacitor plates (i.e., electrodes) and an intervening dielectric layer formed using a deep trench. In particular, each deep trench capacitor may have a construction as shown by the representative deep trench capacitor50shown inFIG. 2. Deep trench capacitor50is formed by patterning a substrate52with, for example, lithography, mask opening, and reactive ion etching to form a deep trench. After the deep trench is formed, a doped region54may be formed in the substrate by introducing a suitable p-type or n-type dopant using, for example, ion implantation. The doped region54supplies a common lower capacitor plate for the deep trench capacitor50. A dielectric layer56(e.g., silicon dioxide, silicon oxynitride, silicon nitride, and/or hafnium oxide) is formed on the bottom and sidewall surfaces of the deep trench. The deep trench is filled with a low resistivity material (e.g., copper, tungsten, titanium nitride, and/or doped polysilicon) to supply an upper capacitor plate58of the deep trench capacitor50. Deep trench capacitors50, which may be fabricated in an array, are compact structures compared with other types of capacitor structures that may be used in ESD protection timing circuits. The deep capacitor50may be coupled with the resistor48by wiring49to define a node that represents one or the other of the nodes36,38.

In an embodiment, each of the capacitors32,34may include only a single deep trench capacitor like deep trench capacitor50. In another embodiment, each of the capacitors32,34may include an array or a bank of deep trench capacitors like deep trench capacitor50that are wired together in parallel. In alternative embodiments, the capacitors32,34may comprise metal-insulator-metal capacitors, metal-oxide-semiconductor capacitors, etc.

In the representative embodiment, the power clamp device16, the NOR gate40, and the inverters42,44(as well as other devices described herein that are constructed from transistors) of the ESD protection circuit10may be comprised of n-channel or p-channel field-effect transistors that are fabricated by complementary metal-oxide-semiconductor (CMOS) processes. For example, each of the inverters42,44includes a p-channel field-effect transistor and an n-channel field-effect transistor coupled in series with the p-channel field-effect between the VDDrail18and the VSSrail20. Each of the field-effect transistors in the ESD protection circuit10may include a gate electrode, a gate dielectric layer positioned between the gate electrode and a semiconductor layer, and source/drain regions in the semiconductor layer. The conductor constituting the gate electrode may comprise, for example, metal, silicide, polycrystalline silicon (polysilicon), or any other appropriate material(s) deposited by a chemical vapor deposition process, etc. The gate dielectric may be comprised of a layer of a dielectric or insulating material such as silicon dioxide, silicon oxynitride, hafnium oxide, etc. The source/drain regions may be formed by selectively doping the semiconductor layer with ion implantation, dopant diffusion, etc. Middle-of line and back-end-of-line (BEOL) processing ensues to provide an interconnect structure with wiring for power and signal transmission. In particular, the wiring of the interconnect structure may couple together the different device structures as diagrammatically shown inFIG. 1(and other drawing views herein).

In use and with the chip unpowered, the ESD protection circuit10may respond to a transient ESD event that applies an ESD potential between the VDDrail18and the VSSrail20. The response time of the ESD protection circuit10may be governed by the shorter of a time constant characterizing the timing circuit12and a different time constant characterizing the timing circuit13. The time constant of timing circuit12is based on a product of the electrical resistance of resistor28and capacitor32. The time constant of timing circuit13is based on a product of the electrical resistance of resistor28and capacitor32,34. In an embodiment, the electrical resistance of each of the resistors28,30is equal and the capacitance of each of the capacitors32,34is equal so that the timing circuits12,13have equal time constants. Regardless of whether the capacitors32,34are functional or non-functional, each of the timing circuits12,13will output a voltage capable of triggering the power clamp device16in response to a transient ESD event at the VDDpower pin or the VSSrail power pin. The NOR gate40will output a voltage equal to high because all of the inputs to the NOR gate40are low. The driving circuit16will subsequently transfer the voltage of VDDfrom the output of the NOR gate40to the node46, which will switch on the power clamp device16to provide its low-impedance state. In its low-impedance state, the power clamp device16defines a low-impedance current path to ground at the VSSrail20such that the ESD current is safely diverted away from the internal circuits22. After the current from the transient ESD event dissipates, the power clamp device16returns to its high-impedance state as the voltage at the node46is removed.

In use and when the chip is powered on using the power supply, the ESD protection circuit10provides fail-safe operation. If the capacitors32,34are functional and non-defective, both of the inputs to the NOR gate40will be equal to logic 1 (i.e., high or VDD) when the chip is initially powered. The output from the NOR gate40will be equal to logic 0 (i.e., low or VSS), which is then applied as the corresponding voltage of VSSat the node46to the power clamp device16. In the representative embodiment, the low voltage at the node46will maintain the power clamp device16in its high-impedance state that isolates the VDDrail18from the VSSrail20while the chip is powered by the power supply.

One or more of the capacitors32,34may be fabricated in a defective condition or may become defective during use such that one or more of the capacitors32,34exhibits an abnormally-low impedance (i.e., shorted to ground relative to the respective resistor). When the chip is not powered, a defective capacitor will have a minimal effect on the performance of the ESD protection circuit10as the branch of the timing circuit12containing the defective capacitor has an infinite time constant. The timing circuit12will continue to trigger the power clamp device16to furnish ESD protection for the unpowered chip.

When an attempt is made to initially power the chip, the ESD protection circuit10is configured to react to any of the capacitors32,34being in a defective condition. In this situation, the ESD protection circuit10is configured to maintain the power clamp device16in its high-impedance state and to not allow the defective capacitor to cause the power clamp device16to be placed in its low-impedance state so that a large current is directed through the power clamp device16to ground. In an embodiment in which the power clamp device16is a BigFET with a gate length greater than or equal to one thousand microns, the unwanted large current that is averted by the ESD protection circuit10may amount to several amperes.

To permit the chip to be successfully powered on using the power supply, the ESD protection circuit10is configured to provide a fail-safe design that responds to one or the other of the capacitors32,34being in a defective condition. Specifically, if at least one but fewer than all of the capacitors32,34are in a defective condition, the NOR gate40causes a voltage equal to logic 0 (i.e., low or VSS) to be applied to the power clamp device16so that the power clamp device16is placed in its high-impedance state. The ESD protection circuit10prevents the node46feeding the power clamp device16from being pulled high due to the presence of a defective capacitor and, thereby, presents the VDDrail18from being directly shorted to the VSSrail20through the turned-on power clamp device16.

As an example, if the voltage at node36is equal to logic 0 because of a defective capacitor32and the voltage at node38is equal to logic 1 because of a non-defective (i.e., functional) capacitor34, the inputs to the NOR gate40will be equal to logic 1 and logic 0. The output from the NOR gate40will be equal to logic 0, which is then applied as the corresponding voltage of VSSat the node46to the power clamp device16. While the chip is powered, the low voltage at the node46will be maintained and the power clamp device16will be maintained in its high-impedance state so the VDDrail18is electrically isolated from the VSSrail20.

The NOR gate40outputs a voltage equal to logic 1 (i.e., high or VDD) only if all of the inputs to the NOR gate40from the nodes36,38are equal to logic 0. This represents a condition in which all of the capacitors32,34are defective. Increasing the number of timing circuits12,13operates to decrease the probability that the NOR gate40will output a voltage equal to logic 1 when the chip is powered. As a result, the fail-safe nature of the design may be improved by increasing the number of timing circuits12,13and the corresponding number of inputs to the NOR gate40. If only one of the timing circuits12,13contains a functional capacitor, then the ESD protection circuit10will permit the chip to be powered on. The redundancy present in the ESD protection circuit10allows a larger number of defective capacitors to be tolerated in comparison with conventional ESD protection circuits that lack such redundancy. Due to the redundancy in the timing circuits12,13, the chip carrying the ESD protection circuit10is less likely to be considered faulty during electrical testing and subsequently scrapped.

In an alternative embodiment in which the power clamp device16is a p-channel field-effect transistor, the number of inverters in the driving circuit14may be modified to provide the correct control logic in response to the output from the NOR gate40.

With reference toFIG. 3in which like reference numerals refer to like features inFIG. 1and in accordance with an alternative embodiment, the NOR gate40may be replaced in the ESD protection circuit10by a NAND gate60and a plurality of inverters62,64in order to form an ESD protection circuit61. In addition, the driving circuit14of the ESD protection circuit61only includes the inverter44, which couples the output of the NAND gate60with the power clamp device16. Generally, the driving circuit14includes one or more inverters44and features a one-stage configuration in the representative embodiment. However, the driving circuit14may include additional inverters to form, for example, a three-stage configuration.

The NAND gate60is a digital logic gate, which is comprised of transistors, that implements a logical conjunction truth table with Boolean logic applied to output a logic signal. The NAND gate60includes inputs that are coupled, respectively, by the inverters62,64with the nodes36,38of the timing circuit12and an output that is coupled with the input to inverter44. If any or all of the inputs to the NAND gate60from the nodes36,38, as modified by the operation of the inverters62,64, supplies a voltage equal to logic 0 (i.e., low or VSS), the voltage for the output logic signal is equal to logic 1 (i.e., high or VDD). The inverter44outputs a voltage representing the opposite logic level to the input received from the NAND gate60. As a result, the inverter44outputs a voltage equal to logic 0 if the output received from the NAND gate60is equal to logic 1 so that the power clamp device16is placed in its high-impedance state, and the inverter44outputs a voltage equal to logic 1 if the output from the NAND gate60is equal to logic 0 so that the power clamp device16is placed in its low-impedance state.

The ESD protection circuit61functions similarly to ESD protection circuit10during a transient ESD event occurring at one or the other of the VDDpower pin or the VSSrail power pin. The ESD protection circuit61will cause the power clamp device16to be placed in its low-impedance state to divert the ESD current away from the internal circuits22.

The ESD protection circuit61also functions similarly to ESD protection circuit10when the chip is powered using the power supply. For example, if the capacitors32,34are functional and the voltages at the node36,38are both equal to logic 1, the input through inverter62to the NAND gate60will be equal to logic 0 and the input through inverter62to the NAND gate60will be equal to logic 0. The output from the NAND gate60will be equal to logic 1, which is then inverted by inverter44and applied as the corresponding voltage of VSSat the node46to the power clamp device16. In the representative embodiment, the low voltage at the node46will maintain the power clamp device16in its high-impedance state that isolates the VDDrail18from the VSSrail20when the chip is powered by the power supply.

As another example, if the voltage at the node36is equal to logic 0 because of a defective capacitor32and the voltage at the node38is equal to logic 1 because of a non-defective (i.e., functional) capacitor34, the input through inverter62to the NAND gate60will be equal to logic 1 and the input through inverter64to the NAND gate60will be equal to logic 0. The output from the NAND gate60will be equal to logic 1, which is then inverted to logic 0 by the inverter44and applied as the corresponding voltage of VSSat the node46to the power clamp device16so that the power clamp device16is maintained in its high-impedance state.

The voltage for the logic signal output by the NAND gate60is equal to logic 0 (and inverted by inverter44to logic 1) only if all of the inputs to the NAND gate60from the nodes36,38are equal to logic 1. This condition exists if both of the capacitors32,34are defective. As discussed above with respect to ESD protection circuit61, increasing the number of timing circuits12,13to increase the redundancy may increase the tolerance to defective capacitors and contributes to increasing the robustness of the fail-safe design.

In an alternative embodiment in which the power clamp device16is a p-channel field-effect transistor, the number of inverters in the driving circuit14may be modified to provide the correct control logic in response to the output from the NAND gate60.

With reference toFIG. 4in which like reference numerals refer to like features inFIG. 1and in accordance with an alternative embodiment, an ESD protection circuit70includes the capacitors32,34while the resistor24includes only a single resistor that is shared in common with the capacitors32,34in the timing circuit12. The ESD protection circuit70includes a plurality of field-effect transistors72,74and a decoder76coupled in parallel with the gate of each of the field-effect transistors72,74. The source and drain of field-effect transistor72are coupled in series with capacitor32between the node36and the VSSrail20. Similarly, the source and drain of field-effect transistor74are coupled in series with capacitor34between the node38and the VSSrail20. When the chip is unpowered, the ESD protection circuit70operates as described hereinabove with respect to ESD protection circuit10to respond to a transient ESD event.

The decoder76is a digital logic device represented by a combinational circuit that converts binary information received from address pins78,80on input lines82,84to binary information output on output lines86,88. The number of input lines82,84may differ from the number of output lines86,88. The decoder76may be comprised of a plurality of field-effect transistors wired to form one or more AND gates, one or more NAND gates, etc. and coupled to provide the desired binary information conversion.

When the chip is powered, the decoder76is addressable and programmable via address pins78,80to provide voltages to the gates of the field-effect transistors72,74for controlling the field-effect transistors72,74. Specifically, in response to the input of voltages conveying binary information via the input lines82,84from the address pins78,80, the decoder76can output control logic at voltages over output lines86,88that permit the transistors72,74to be individually controlled and programmed Normally and under a condition in which the capacitors32,34are functional, the output of the decoder76biases the gates of the transistors72,74so that all of the field-effect transistors72,74are switched to a low-impedance state. As a result, each of the capacitors32,34is individually coupled in a current path with the VSSrail20if the respective one of the field-effect transistors72,74is placed by the operation of the decoder76in its low-impedance state. In one embodiment, the transistors72,74may be NMOSFETs and the pins78,80are set so that the decoder76biases the gates of the transistors72,74with a voltage equal to logic 1 that places the transistors72,74in their respective low-impedance states.

The ESD protection circuit70may be configured to detect the power clamp device16unexpectedly switching on at the time of power on and draining a large amount of current. This type of incident at chip power on may be the result of one or the other of the capacitors32,34being defective and, as a consequence, appearing as a short to its respective resistor28,30. In response, the address pins78,80of the ESD protection circuit70are used to investigate the incident and to pinpoint the capacitor that is the source of the short.

Specifically, the address pins78,80are used to systematically turn on each of the transistors72,74while turning off all other transistors with output voltages supplied through the output lines86,88. As each of the transistors72,74is individually switched to its low-impedance state by the decoder76using the address pins78,80, the VDDcurrent is monitored for a large current flow indicative of a defective capacitor. In this manner, the defective capacitor can be identified and logged. After full testing, the decoder76is programmed to switch the transistors72,74corresponding to defective capacitors to a voltage that disables such defective capacitors. If one or more of the capacitors32,34are defective, the testing to provide the programmed state permits the chip to be successfully powered on without experiencing a short to ground through the defective capacitor. In an embodiment in which the transistors72,74are n-channel field-effect transistors, the decoder76is programmed to output a voltage equal to logic 0 (i.e., low or VSS) to switch any of the transistors72,74that are in series with a defective capacitor to their high-impedance state and any of the transistors72,74that are in series with a functional capacitor to their low-impedance state.

It will be understood that when an element is described as being “connected” or “coupled” to or with another element, it can be directly connected or coupled to the other element or, instead, one or more intervening elements may be present. In contrast, when an element is described as being “directly connected” or “directly coupled” to or with another element, there are no intervening elements present. When an element is described as being “indirectly connected” or “indirectly coupled” to or with another element, there is at least one intervening element present.