A light-emitting diode (LED) package includes a package substrate, a first electrode pad, a second electrode pad, an upper insulating layer and an LED chip. The first electrode pad is disposed on an upper surface of the package substrate and includes a groove. The second electrode pad includes a protruding portion disposed in the groove of the first electrode pad. The upper insulating layer insulates the first electrode pad from the second electrode pad on the package substrate. The LED chip includes a first electrode and a second electrode which are respectively electrically connected in the form of a flip-chip to the first electrode pad and the protruding portion of the second electrode pad.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims benefit of the priority of Korean Patent Application No. 10-2013-0023939, filed on Mar. 6, 2013, in the Korean Intellectual Property Office, the entire contents of which are hereby incorporated by reference.

TECHNICAL FIELD

The present inventive concept relates to a light-emitting diode (LED) package, and more particularly, to an LED package that has a flip-chip bonding structure.

BACKGROUND

The LED chip emits light as electrons and holes, which are injected into an active layer that is formed of a compound semiconductor, are combined. The LED chip can be packaged and used. When the LED chip in the LED package is operated, heat is generated, and thus, each element is thermally expanded. Accordingly, a thermal stress is exerted on an electrode or a pad in the LED chip. Therefore, there is a need for technology for developing a structure of the LED package for reducing a thermal stress.

SUMMARY

The present inventive concept provides a light-emitting (LED) package that has a flip-chip bonding structure which may reduce a thermal stress and has excellent workability.

An aspect of the present inventive concept relates to a light-emitting diode (LED) package including a package substrate, a first electrode pad disposed on an upper surface of the package substrate and including a groove, a second electrode pad including a protruding portion disposed in the groove of the first electrode pad, an upper insulating layer for insulating the first electrode pad from the second electrode pad on the package substrate, and an LED chip including a first electrode and a second electrode which are respectively electrically connected in the form of a flip-chip to the first electrode pad and the protruding portion of the second electrode pad.

The upper insulating layer may be disposed on a surrounding portion of the package substrate. The upper insulating layer may be disposed on a surrounding portion of the second electrode pad.

External electrode pads and a lower insulating layer may be disposed on a lower surface of the package substrate. The external electrode pads may be electrically connected to the first electrode pad and the second electrode pad and apply an electrical signal from outside of the LED package. The lower insulating layer may insulate the external electrode pads.

The package substrate may include metal.

The groove may be disposed in a plural number. The protruding portion may be disposed in a plural number. The groove may have a rectangular shape of which a width in one direction is greater than a width in another direction and the protruding portion may be a rod-type protruding member that is disposed in the rectangular groove.

A size of the first electrode pad may be greater than a size of the second electrode pad.

Another aspect of the present inventive concept encompasses a light-emitting diode (LED) package including a package substrate, a first electrode pad and a second electrode pad that are disposed on an upper surface of the package substrate and are insulated from each other by using an upper insulating layer, and an LED chip including a first electrode and a second electrode which are respectively electrically connected in the form of a flip-chip to the first electrode pad and the second electrode pad. The upper insulating layer is disposed in a lower part of the LED chip and buried inside the package substrate such that the upper insulating layer does not pass through the package substrate.

The upper insulating layer may be disposed on both sidewalls of the package substrate.

On a lower surface of the package substrate, a lower insulating layer may be disposed. The upper insulating layer may be connected to the lower insulating layer.

A lower insulating layer may be buried inside the package substrate from a lower surface of the package substrate. The lower insulating layer may be connected to the upper insulating layer at a location outside the LED chip.

An external electrode pad may be disposed on the lower surface of the package substrate, such that the external electrode pad is separated by the lower insulating layer. The external electrode pad may be electrically connected to the first electrode pad and the second electrode pad to apply an electrical signal from outside of the LED chip.

A still another aspect of the present inventive concept relates to a light-emitting diode (LED) package including a package substrate, a first electrode pad disposed on an upper surface of the package substrate, a second electrode pad, an upper insulating layer for insulating the first electrode pad from the second electrode pad on the package substrate, and an LED chip including a first electrode and a second electrode which are respectively electrically connected in the form of a flip-chip to the first electrode pad and the second electrode pad. A portion of the upper insulating layer is placed between the first electrode pad and the second electrode pad. The second electrode extends in a direction perpendicular to an extending direction of the portion of the upper insulating layer between the first electrode pad and the second electrode pad.

The second electrode may have a rectangular shape, and a long edge of the second electrode may be perpendicular to the extending direction of the portion of the upper insulating layer between the first electrode pad and the second electrode pad.

DETAILED DESCRIPTION

Hereinafter, the present inventive concept will be described more fully with reference to the accompanying drawings, in which exemplary embodiments of the present inventive concept are shown. Like reference numerals in the drawings denote like elements, and thus their description will be omitted.

The embodiments of the present inventive concept are provided so that the present inventive concept is fully explained to those skilled in the art. The present inventive concept may, however, be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the present inventive concept to those skilled in the art.

It will be understood that, although the terms first, second, etc. may be used herein to describe various members, components, regions, layers, sections, and/or elements, these members, parts, regions, layers, sections, and/or elements should not be limited by these terms. These terms do not refer to a particular order, rank, or superiority, and are only used to distinguish one member, component, region, layer, section, or element from another member, component, region, layer, section, or element. Thus, a first member, component, region, layer, section, or element discussed below could be termed a second member, component, region, layer, section, or element without departing from the teachings of the example embodiments. For example, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element without departing from the scope of protection.

Meanwhile, when an exemplary embodiment can be differently implemented, a function or an operation specified in a particular process may be performed differently from an order specified in a flowchart. For example, two continuous processes may be substantially simultaneously performed, or processes may be performed in a reverse order according to a related function or operation.

In the drawings, for example, illustrated shapes may be deformed according to fabrication technology and/or tolerances. Therefore, the exemplary embodiments are not limited to certain shapes illustrated in the present specification, and may include modifications of shapes caused in fabrication processes. The embodiments herein may be implemented in a specific form, or combined in various ways.

Hereinafter, a structure of a light-emitting diode (LED) package, according to an embodiment of the present inventive concept, is described.

FIGS. 1 through 4are diagrams illustrating an LED package100according to an embodiment of the present inventive concept.

Specifically,FIGS. 1 and 4are respectively upper and lower plan views of the LED package100.FIGS. 2 and 3are cross-sectional views of the LED package100which are respectively taken along lines A-B ofFIG. 1and C-D ofFIG. 1.

The LED package100may include a package substrate1. The package substrate1may be formed of metal, ceramic, silicon, a silicon alloy, or a polymer material. An example of ceramic may include aluminium nitride (AlN), or aluminum oxide (Al2O3). An example of a silicon alloy may include silicon-aluminum (Si—Al) or silicon carbide (SiC). An example of a polymer material may include polyimide. The package substrate1may be formed of a material that effectively reflects light, or may be formed to have a color, for example, white or silver so that a surface of the package substrate1may effectively reflect light. If the package substrate1is formed of metal, package workability thereof may be improved.

An intermediate layer (not separately illustrated) may be formed between an upper surface of the package substrate100and first and second electrode pads3and7. The intermediate layer may be provided to form the first and second electrode pads3and7, regardless of a material of the package substrate100.

The package substrate1may be formed of any material that forms a lead frame. The package substrate1in an embodiment of the present inventive concept may be formed of copper (Cu). The package substrate1may be divided into a first area1aand a second area1b. However, the package substrate1may also be formed as one element. An upper insulating layer9and a lower insulating layer10that provide insulating performance, as to be described later, may be buried in the package substrate1.

The first electrode pad3may be disposed and formed on an upper surface of the first area1aof the package substrate1. The first electrode pad3may include a groove5. The groove5may be formed inside a body of the first electrode pad3. The groove5may have a rectangular shape of which a width in one direction is greater than a width in another direction. The first electrode pad3may be formed of a metal pattern, for example, a copper pattern.

The first electrode pad3may be formed of gold (Au), tin (Sn), plumbum (Pb), silver (Ag), indium (In), germanium (Ge), nickel (Ni), Si, or a combination thereof. The first electrode pad3may also formed of an Au—Sn alloy, a Pb—Ag—In alloy, a Pb—Ag—Sn alloy, a Pb—Sn alloy, an Au—Ge alloy, an Au—Si alloy, or Au. The first electrode pad3may be a thin-film electrode pad that is obtained by forming and then patterning a plating layer on the first area1aof the package substrate1.

The second electrode pad7may be disposed to be separate from the first electrode pad3. The second electrode pad7may include a protruding portion7athat is disposed inside the groove5in the first electrode pad3. The protruding portion7amay be a rod-type protruding member that is disposed in the rectangular-type groove5. The second electrode pad7may be formed of the same material as the first electrode pad3. The second electrode pad7may be a thin-film electrode pad that is obtained by forming and then patterning a plating layer on the second area1bof the package substrate1. The first electrode pad3and the second electrode pad7may be formed of a material that effectively reflects light, or formed to have a color, for example, white or silver so that a surface of the package substrate1may effectively reflect light. A size of the first electrode pad3may be greater than a size of the second electrode pad7.

On an upper surface of the package substrate1, an upper insulating layer9for insulating the first electrode pad3from the second electrode pad7may be formed. The first electrode pad3and the second electrode pad7may be insulated from each other by using the upper insulating layer9. The upper insulating layer9may be formed of an insulating resin, for example, epoxy resin.

The upper insulating layer9may include an upper insulating layer9athat may be formed on a surrounding portion of the second electrode pad7that includes the protruding portion7a. The upper insulating layer9may include an upper insulating layer9bthat may be formed on a surrounding portion of the package substrate1. The upper insulating layer9may include an upper insulating layer9cthat may be formed on a separation portion between the first electrode pad3and the second electrode pad7.

On the first electrode pad3and the second electrode pad7included in the package substrate1, an LED chip11may be disposed in the form of a flip-chip. A first electrode13and a second electrode15, included in the LED chip11, may be respectively connected in the form of a flip-chip to the first electrode pad3and the protruding portion7athat is included in the second electrode pad7. The first electrode13may be an anode electrode. The second electrode15may be a cathode electrode.

The LED chip11may be a horizontal-type LED chip. As illustrated inFIG. 2, the LED chip11may be electrically connected to the first electrode pad3and the second electrode pad7, with the first electrode13and the second electrode15facing downwards. The LED chip11may be a blue LED chip that emits blue light. The LED chip11may be an LED chip that emits light of a different color, for example, red, yellow, or blue.

As illustrated inFIG. 2, the upper insulating layer9a, which is located below the LED chip11, may be buried inside the first area1aof the package substrate1, so as not to pass through the first area1aof the package substrate1. Referring toFIGS. 3 and 4, the lower insulating layer10may include a lower insulating layer10awhich is not connected to an upper insulating layer. The lower insulating layer10may include an upper insulating layer9bthat may be formed on both sidewalls of the package substrate1. As illustrated inFIGS. 2through4, the lower insulating layer10may be formed on a lower surface of the package substrate1. The upper insulating layer9b, which is formed on both sidewalls of the package substrate1, may be connected to the lower insulating layer10b.

As illustrated inFIGS. 2 and 3, the lower insulating layer10may be buried inside the package substrate1from the lower surface of the package substrate1. As illustrated inFIG. 3, the lower insulating layer10may include a lower insulating layer10c. The lower insulating layer10cmay be disposed inside the package substrate1and, may be connected to the upper insulating layer9coutside the LED chip11. Like the upper insulating layer9, the lower insulating layer10may formed of an insulating resin, for example, epoxy resin.

A fluorescent layer17may be formed on the LED chip11. As illustrated inFIGS. 2 and 3, the fluorescent layer17may be formed to cover an entire surface of the LED chip11, other than the first electrode13and the second electrode15.

The fluorescent layer17may be formed by distributing a fluorescent material throughout a light-transmitting resin such as silicon resin or epoxy resin. If the LED chip11is a blue LED chip, a fluorescent body, which is included in a light-emitting resin, may include at least one from among garnets such as yttrium aluminum garnet (YAG) or terbium aluminum garnet (TAG), silicates, nitrides, or oxynitrides. A lens19may be formed on the fluorescent layer17.

As illustrated inFIG. 4, a plurality of external electrode pads23,25and27may be formed on a lower surface of the package substrate1. The external electrode pads are electrically connected to the first electrode pad3and the second electrode pad7and may apply an electrical signal from the outside. The lower insulating layer10for insulating the external electrode pads23,25, and27may be formed between the external electrode pads23,25, and27. As illustrated inFIG. 3, the external electrode pads23and25may be electrically connected to the first electrode pad3. As illustrated inFIG. 3, the external electrode pads27may be electrically connected to the second electrode pad7.

Then, a thermal stress, which is exerted on an LED chip due to thermal expansion of elements of an LED chip that has the configuration as provided above, is described.

FIGS. 5 and 6are diagrams for explaining a thermal stress on an LED chip, which is caused by thermal expansion of the LED package ofFIG. 1.FIGS. 7 and 8are diagrams for explaining a comparative example for comparingFIG. 5toFIG. 6

Specifically,FIG. 5is a plan view illustrating the LED package100ofFIG. 1, other than the fluorescent layer17and the lens19.FIG. 6is a cross-sectional view of an LED package100, which is taken along a line A-B ofFIG. 5.FIG. 7is a plan view illustrating the LED package100afor comparing to the LED package100ofFIG. 5.FIG. 8is a cross-sectional view of the LED package100a, which is taken along a line C-D ofFIG. 7.

As described above, with reference to the LED package100ofFIGS. 5 and 6, the upper insulating layer9and the protruding portion7a, which is included in the second electrode pad7, may be disposed inside the groove5in the first electrode pad3on the package substrate1. Additionally, the LED chip11, which includes the first electrode13and the second electrode15respectively on the first electrode pad3and the protruding portion7ain the second electrode pad7, may be attached in the form of a flip-chip to the package substrate1. Particularly, with reference to the LED package100, the second electrode15included in the LED chip11may be located vertically (i.e., extending in a top-bottom direction as illustrated inFIG. 5) perpendicular to an extending direction of the upper insulating layer9which is placed between the first electrode pad3and the second electrode pad7. The LED package100may include the lower insulating layer10that is buried inside the package substrate1from a lower surface of the package substrate1and electrically separates from the external electrode pad23.

If the upper insulating layer9is formed of epoxy resin, a coefficient of thermal expansion (CTE) is 30-70 ppm/° C. If the package substrates1(in areas1aand1b), the electrode pads3and7, and the electrodes13and15are formed of copper, a CTE is 16-17 ppm/° C. A CTE of a gallium nitride (GaN) layer, which is an element of the LED chip11, is 3-6 ppm/° C. Accordingly, as illustrated inFIGS. 5 and 6, if heat is generated from the LED chip11, the upper insulating layer9may be thermally expanded. Thus, a thermal expansion force21may affect the LED chip11.

However, as indicated by an arrow that is shown inFIG. 5, with regard to the LED package100, the thermal expansion force21of the upper insulating layer9may be applied to a short edge (that has a short width or length) of the second electrode15, rather than a long edge (that has a long width or length) of the second electrode15. Thus, a thermal stress may not be exerted on the LED chip11or may be minimally exerted on the LED chip11.

Additionally, with regard to the LED package100which is shown inFIG. 6, the upper insulating layer9may be connected to the lower insulating layer10, but not in an area underneath the LED chip11. Accordingly, the thermal expansion force21may not be transmitted to the outside of the LED chip11, and thus a thermal stress may not be exerted on the LED chip11or may be minimally exerted on the LED chip11.

On the contrary, with regard to the LED package100a, that is shown inFIGS. 7 and 8, the first electrode pad3and the second electrode7, which are insulated by the upper insulating layer9on the package substrate1, are disposed. Additionally, the LED chip11, which includes the first electrode13and a second electrode15arespectively on the first electrode pad3and the second electrode pad7, is attached in the form of a flip-chip to the package substrate1. Particularly, with regard to the LED package100a, the second electrode15aincluded in the LED chip11is located horizontally (i.e., extending in a left-right direction as illustrated inFIG. 7), compared to an extending direction of the upper insulating layer9which is placed between the first electrode pad3and the second electrode pad7.

Accordingly, as illustrated inFIGS. 7 and 8, if heat is generated from the LED chip11, the upper insulating layer9is thermally expanded. Thus, a thermal expansion force21aaffects the LED chip11.

However, unlike the LED package100that is shown inFIGS. 5 and 6, in the case of the LED package100athat is shown inFIGS. 7 and 8, the thermal expansion force21aof the upper insulating layer9is applied to a long edge (that has a long width or length) of the second electrode15, rather than a short edge (that has a short width or length) of the second electrode15. Accordingly, the LED chip11is thermally expanded as indicated by a reference numeral21b, and thus, a thermal stress on the LED chip11may be increased in comparison to the example ofFIGS. 5 and 6.

Additionally, with regard to the LED package100awhich is shown inFIGS. 7 and 8, the upper insulating layer9is connected to the lower insulating layer10, beneath the LED chip11. Accordingly, the thermal expansion force21ais transmitted to the outside of the LED chip11, and thus a thermal stress on the LED chip11may be increased in comparison to the example ofFIGS. 5 and 6.

FIGS. 9A through 9Iare cross-sectional views for explaining a method of manufacturing the LED package, according to an embodiment of the present inventive concept.FIGS. 10 through 13are plan views illustrating some processes included in the method ofFIGS. 9A through 9I.

Referring toFIGS. 9A,9B, and10, the package substrate1may be prepared as shown inFIG. 9A. As described above, the package substrate1may be formed of metal. In an embodiment of the present inventive concept, a copper substrate may be used as the package substrate1.

Then, as shown inFIG. 9B, an upper mask pattern52may be formed on an upper surface of the package substrate1. Then, a part of the upper surface of the package substrate1may be etched, and thus, an upper substrate pattern53, as shown inFIG. 10, may be formed. A plan view of the upper substrate pattern53is illustrated inFIG. 10. A cross-section of the package substrate1, which is taken along a line A-A′ inFIG. 10, is shown inFIG. 9B. Upper substrate patterns53athrough53eillustrated inFIG. 10correspond to upper substrate patterns53athrough53eillustrated inFIG. 9B. The upper substrate patterns53may include the pattern53athat is located around an upper surface of the package substrate1, the pattern53cthat is located inside the upper surface of the package substrate1, and the pattern53bthat is located between the two inside patterns53dand53e. The patterns53a,53band53cmay be a groove pattern that is grooved inside the package substrate1.

Referring toFIGS. 9C and 9D, the upper mask pattern53may be removed. Then, as illustrated inFIG. 9C, a first insulating layer55may be formed on an upper surface of the package substrate1. The first insulating layer55may be formed of epoxy resin. The first insulating layer55may be formed on the upper substrate pattern53included in the package substrate1. The first insulating layer55may be formed to fill the inside of the groove patterns53a,53band53cthat constitute the upper substrate pattern53.

Then, as shown inFIG. 9D, a lower mask pattern56may be formed on the lower surface of the package substrate1. Then, a part of a lower surface of the package substrate1may be etched, and thus, a lower substrate pattern57, as shown inFIG. 11, may be formed. A plan view of the lower substrate pattern57is illustrated inFIG. 11. A cross-section of the package substrate1, which is taken along a line B-B′ inFIG. 11, is shown inFIG. 9D. Lower substrate patterns57a,57b,57cand57dillustrated inFIG. 11correspond to lower substrate patterns57a,57b,57cand57dillustrated inFIG. 9D. The lower substrate pattern57dmay be a groove pattern that is formed inside the package substrate1.

Referring toFIGS. 9E and 9F, the lower mask pattern56may be removed. Then, as illustrated inFIG. 9E, a second insulating layer59may be formed on a lower surface of the package substrate1. The second insulating layer59may be formed of epoxy resin. The second insulating layer59may be formed on the lower substrate pattern57included in the package substrate1. The second insulating layer59may be formed to fill the inside of the groove pattern57dthat constitutes the lower substrate pattern57.

Then, as illustrated inFIG. 9E, the first insulating layer55and the second insulating layer59may be planarized on an upper surface and a lower surface of the package substrate1. Then, the first insulating layer55may become the upper insulating layer9. The second insulating layer59may become the lower insulating layer10. The upper insulating layer9and the lower insulating layer10, which are formed on both sidewalls of the package substrate1, may be connected with each other. The upper insulating layer9and the lower insulating layer10may be also connected with each other in a partial area inside the package substrate1. Resultantly, the package substrate1may be separated into the first area1aand the second area1b, such that the first area1aand the second area1bare insulated from each other.

Referring toFIGS. 9G,9H,12, and13, as illustrated inFIG. 9G, a conductive layer61may be formed on upper and lower surfaces of the package substrate1. The conductive layer61may be a conductive layer that is formed by plating the upper and lower surfaces of the package substrate1. The conductive layer61may be formed as a copper layer.

Then, as shown inFIG. 9H, an upper mask pattern62may be formed on the conductive layer61of inFIG. 9G, which is formed on an upper surface of the package substrate1. Then, the conductive layer61may be etched by using the upper mask pattern62as an etching mask, and thus, as illustrated inFIG. 12, an electrode pad63may be formed. A plan view of the electrode pad63is illustrated inFIG. 12. A cross-section of the package substrate1, which is taken along a line A-A′ inFIG. 12, is shown inFIG. 9H. Electrode pad63ofFIG. 12corresponds to the electrode pads3and7ofFIG. 9H. As described above, the electrode pad63may include the first electrode pad3that includes the groove5, and the second electrode pad7that includes the protruding portion7awhich is disposed in the groove5included in the first electrode3. Referring toFIG. 12, an upper insulating layer63emay be formed for insulating the first electrode pad3and the second electrode pad7.

Then, as shown inFIG. 9H, a lower mask pattern64is formed on the conductive layer61ofFIG. 9G, which is formed on a lower surface of the package substrate1. Then, the conductive layer61may be etched by using the lower mask pattern64as an etching mask, and thus, as illustrated inFIG. 13, an electrode pad65may be formed. A plan view of the electrode pad65is illustrated inFIG. 13. A cross-section of the package substrate1, which is taken along a line B-B′ inFIG. 13, is shown inFIG. 9H. The electrode pad65ofFIG. 13corresponds to the electrode pads23,25and27ofFIG. 9H. As described above, the external electrode pad65may include the first through third external electrode pad23,25, and27.

Referring toFIG. 9I, the upper mask pattern62and the lower mask pattern64may be etched and removed. Then, in order to improve electrical performance, additional conductive layers8and28, which are formed of, for example, Ni or Au, may be selectively further plated on the electrode pad63and the external electrode pad65. Through this process, the package substrate1, which includes the electrode pads3,7, and8and the external electrode pads23,25,27, and28, may be obtained. Then, the LED chip11may be mounted in the form of a flip-chip on the electrode pads3,7, and8, and thus the LED package100may be completed.

FIGS. 14 and 15are plan views for explaining an LED package200according to an embodiment of the present inventive concept.

Specifically,FIG. 14is a plan view illustrating the package substrate1and electrode pads3′ and7′, which are included in the LED package200.FIG. 15is a plan view illustrating a state in which an LED chip11ais mounted on the package substrate shown inFIG. 14.

With regard to the LED package200that is shown inFIGS. 14 and 15, compared to the LED package100shown inFIGS. 1 through 4, the number of the protruding portions7aand7bin the second electrode pad7′ may be plural, that is, two. Accordingly, except for the fact that the number of the second electrodes15aand15bis plural, that is, two, the LED package200may be identical to the LED package100.

As illustrated inFIGS. 14 and 15, a first electrode pad3′, which includes two groove5aand5b, may be disposed on the package substrate1. The two groove5aand5bmay be electrically insulated from the second electrode pad7′ that includes the two protruding portions7aand7bby an upper insulating layer9a′.

Referring toFIG. 15, the LED chip11amay be mounted on the package substrate1that includes the second electrode pad7′ and the first electrode pad3′. The second electrode pad7′ may include the two protruding portions7aand7b. As illustrated inFIG. 15, with regard to the LED package200, the second electrodes15aand15bin the LED chip11amay be located vertically (e.g., extending in a top-bottom direction as illustrated inFIG. 15) perpendicular to an extending direction of the upper insulating layer9cwhich is placed between the first electrode pad3′ and the second electrode pad7′.

In the case of the LED package200shown inFIGS. 14 and 15, which includes such a configuration, if a size of the LED chip11ais large, both of protruding portions7aand7bin the second electrode pad7′ may be disposed, and thus, may be applied to various designs of the LED package200.

FIG. 16is a diagram for explaining a thermal stress on an LED chip, which is caused by thermal expansion of the LED package ofFIG. 15.

Specifically, a thermal stress on the LED package200, shown inFIG. 16, is almost identical to a description about the LED package100that is shown inFIGS. 5 and 6. Thus, a description thereof will be briefly provided. As illustrated inFIG. 15, with regard to the LED package200, the second electrodes15aand15b, included in the LED chip11a, may be located vertically (e.g., extending in a top-bottom direction as illustrated inFIG. 15) perpendicular to an extending direction of the upper insulating layer9which is placed between the first electrode pad3′ and the second electrode pad7′. Accordingly, a thermal expansion force31of the upper insulating layer9, which is shown inFIGS. 15 and 16, may be applied to a short edge (having a short width or length) of the second electrodes15aand15b, rather than a long edge (having a long width or length) of the second electrodes15aand15b. Thus, a thermal stress may not be exerted on the LED chip11aor may be minimally exerted on the LED chip11.

Additionally, with regard to the LED package200which is shown inFIG. 16, the upper insulating layer9may not be connected to the lower insulating layer at a lower part of the LED chip11a. Accordingly, the thermal expansion force31is not transmitted to the outside of the LED chip11a, and thus a thermal stress may not be exerted on the LED chip11aor may be minimally exerted on the LED chip11a.