Current driven crystal oscillator

An oscillator circuit with an oscillator stage and a first current source arranged to drive the oscillator stage is presented. The oscillator stage has an oscillator stage input terminal, an oscillator stage output terminal, an oscillator arranged to provide an oscillating signal between the oscillator stage input terminal and the oscillator stage output terminal. The oscillator circuit has an operational amplifier with an inverting input, a non-inverting input and an operational amplifier output. The oscillator stage input terminal and the oscillator stage output terminal are coupled to the inverting input and non-inverting input. The operational amplifier output is coupled to the oscillator stage input terminal such that the oscillator stage input terminal and the oscillator stage output terminal are controlled to have a same DC voltage level.

TECHNICAL FIELD

The invention relates to oscillator circuits, and in particular, to crystal oscillator circuits.

BACKGROUND

A crystal oscillator is an electronic oscillator circuit that uses the mechanical resonance of a vibrating crystal of piezoelectric material to create a signal with a very precise frequency.

This frequency is commonly used to keep track of time, to provide a stable clock signal required by a digital system, and/or to stabilize frequencies for radio transmitters and receivers.

The most common type of piezoelectric material used in crystal oscillators is quartz crystal, but other materials like polycrystalline ceramics are also used.

Typically, quartz crystals are cut and mounted to vibrate best at a desired resonance frequency or a multiple of the desired resonant frequency. When the crystal is vibrating, it can be modeled as an RLC circuit producing a rapidly changing reactance with frequency, wherein the RLC circuit provides positive feedback and gain at the resonant frequency therefore producing sustained oscillations.

FIG. 1illustrates a current-controlled CMOS-inverter oscillator circuit as known from E. Vittoz, “Low-Power Crystal and MEMS Oscillators: The Experience of Watch Developments”, Integrated Circuits and Systems, FIG. 5.25, page 129, DOI 10.1007/978-90-481-9394-3. The circuit ofFIG. 1comprises a transistor T1having a gate G1, a source S1, and a drain D1, a transistor T2having a gate G2, a source S2, and a drain D2, a transistor T3having a gate G3, a source S3, and a drain D3, a capacitor C1having a first end10and a second end11, a capacitor C2having a first end12and a second end13, a capacitor C3having a first end14and a second end15, a resistor R1having a first end16and a second end17and a crystal oscillator18having a first end19and a second end20. The source S1is connected to the source S2and to the second end15of the capacitor C3. The drain D2is connected to the second end17of the resistor R1, to the second end20of the crystal oscillator18, to the drain D3and to the second end13of the capacitor C2. The gate G2is connected to the first end16of the resistor R1, to the first end19of the crystal oscillator18, to the gate G3and to the second end11of the capacitor C1. The first end10of the capacitor C1is connected to the source S3, to the first end12of the capacitor C2and to the first end14of the capacitor C3.

In the known circuit according toFIG. 1, the resistor R1is a feedback resistor from the drains D2and D3, respectively, of the transistors T2and T3, respectively, to the gates G2and G3, of the transistors T2and T3, respectively, to ensure that the DC voltage levels of these drains D2and D3and these gates G2and G3of the transistors T2and T3, are the same. Therefore, the DC voltage level at both terminals19,20of the oscillator crystal18is the same. Feedback resistor R1should have a very high resistance value in case of low power requirements, as it is consuming electrical power all the time.

SUMMARY

In a first aspect, the invention provides an oscillator circuit comprising an oscillator stage (OSC) and a first current source (Iddx) arranged to drive said oscillator stage (OSC), the oscillator stage (OSC) comprising an oscillator stage input terminal, an oscillator stage output terminal, an oscillator (X1) arranged to provide an oscillating signal between said oscillator stage input terminal and said oscillator stage output terminal, said oscillator circuit comprising an operational amplifier with an inverting input, a non-inverting input and an operational amplifier output, said oscillator stage input terminal and said oscillator stage output terminal being coupled to said inverting input and non-inverting input, and said operational amplifier output being coupled to the oscillator stage input terminal such that said oscillator stage input terminal and said oscillator stage output terminal are controlled to have a same DC voltage level.

By doing so, all elements in the oscillator circuit are current driven. This provides several features to the oscillator circuit, including much less spread over processing corners, the oscillator circuit is self-adjusting to a suitable supply voltage which will be as low as possible but not lower than a minimum value necessary for the oscillator circuit to operate properly and the individual components can be easily designed, especially scaling is simple.

The dependent claims are focusing on advantageous embodiments.

In an embodiment, as claimed in claims15and16, the oscillator circuit may work in a transceiver mode wherein stabilized frequencies for radio transmitters and/or receivers can be generated. In this mode, rising/falling edges of the generated oscillating signal as eventually produced should be as accurate as possible such that they define moments in time at which certain actions may start/end are as accurate as possible. This is achieved by injecting relatively more current in the oscillator circuit by current source Iddxsuch that lower phase noise is obtained.

In another embodiment, as claimed in claims17and18, the oscillator circuit illustrated may work in a timer mode in order to provide a stable clock signal. In this embodiment, requirements as to phase noise are less strict because the timer will count an average number of oscillation cycles by counting the number of rising/falling edges only. So, here, the current as injected into the oscillator circuit by current source Iddxcan be much less than in the transceiver mode.

The person skilled in the art will understand that the features described above may be combined in any way deemed useful.

DESCRIPTION

The examples and embodiments described herein serve to illustrate rather than to limit the invention. The person skilled in the art will be able to design alternative embodiments without departing from the scope of the claims. Reference signs placed in parentheses in the claims shall not be interpreted to limit the scope of the claims. Items described as separate entities in the claims or the description may be implemented as a single or multiple hardware items combining the features of the items described.

FIG. 2illustrates a current driven crystal oscillator circuit according to one embodiment of the invention.

The current driven crystal oscillator circuit ofFIG. 2, seen from left to right, comprises a series circuit of the following sub-circuits: a bias circuit BC, a regulator OA1and Low Pass Filter circuit R/LPF, an oscillator stage OS, a current-mode comparator CMC, and an output circuit OC. A level shifter L receives an output voltage Voutof output circuit OC.

The current driven crystal oscillator circuit ofFIG. 2comprises a plurality of transistors Ti(i=4, 5, . . . , 12). Each one of these transistors Tihas a respective gate Gi, a source Si, and a drain Di. For the sake of simplicity, a transistor Tiwill be called an ithtransistor in the specification hereinafter. It is observed that the reference number concerned may be different in the claims, as they may appear in another order in the claims.

The current driven crystal oscillator circuit ofFIG. 2includes a resonating crystal X1and a current source I1.

FIG. 2, also shows the currents received by each of the sub-circuits: the bias circuit BC receives a current Ibias, the regulator and Low Pass Filter circuit R/LPF receives a current Ireg, the oscillator stage OS receives a current Iosc, the current-mode comparator CMC receives a current Icp1, and the output circuit OC receives a current Icp2.

The bias circuit BC of the current driven crystal oscillator circuit includes a fourth P-type transistor T4and a fifth N-type transistor T5having their respective drain terminals D4and D5connected to each other, and their gate terminals G4and G5respectively connected to their drain terminals D4and D5. The source terminal S5of the N-type transistor T5is connected to ground and the source terminal S4of the P-type transistor T4is connected to the current source I1.

The R/LPF circuit of the current driven crystal oscillator circuit ofFIG. 2includes an operational amplifier OA1, a capacitor C4having a first end c41and a second end c42, a capacitor C5having a first end c51and a second end c52, a resistor R2having a first end r21and a second end r22, a resistor R3having a first end r31and a second end r32, a resistor R4having a first end r41and a second end r42, and a sixth N-type transistor T6having a source S6, a drain D6and a gate G6. The second end c42of the capacitor C4is connected to the inverting input of the operational amplifier OA1, the second end c52of the capacitor C5is connected to the non-inverting input of the operational amplifier OA1and the first end c41of the capacitor C4is connected to the first end c51of the capacitor C5and to the ground. The gate G6of the transistor T6is connected to the gate G5of the transistor T5, the drain D6of the transistor T6is connected to the negative power supply of the operational amplifier OA1, and the source S6of the transistor T6is connected to the ground. The output of the operational amplifier OA1is connected to the first end r31of the resistor R3, the second end r32of the resistor R3is connected to the second end r22of the resistor R2and to the second end r42of the resistor R4, the first end r21of the resistor R2is connected to the inverting input of the operational amplifier OA1and the first end r41of the resistor R4is connected to the non-inverting input of the operational amplifier OA1.

Furthermore, the oscillator stage OS of the current driven crystal oscillator circuit ofFIG. 2includes an eighth N-type transistor T8having a source S8, a drain D8and a gate G8, a seventh P-type transistor T7having a source S7, a drain D7and a gate G7, a capacitor C7having a first end c71and a second end c72, a resistor R5having a first end r51and a second end r52, a resistor R6having a first end r61and a second end r62. The first end r51of the resistor R5is connected to the first end c71of the capacitor C7and to the current source I1. The second end c72of the capacitor C7is connected to the ground and the second end r52of the resistor R5is connected to the source S7of the transistor T7. The gate G7of the transistor T7is connected to the second end r22of the resistor R2and the drain D7of the transistor T7is connected to the drain D8of the transistor T8. The gate G8of the transistor T8is connected to the second end r22of the resistor R2and the source S8of the transistor T8is connected to the first end r61of the resistor R6. Furthermore, the oscillator stage OS of the current driven crystal oscillator circuit ofFIG. 2includes a resistor R7having a first end r71and a second end r72and a switch S2wherein the first end r71of the resistor R7is connected to the second end c62of the capacitor C6, the second end r72of the resistor R7is connected to one end of the switch S2and the other end of the switch S2is connected to the first end c81of the capacitor C8.

The current-mode comparator CMC of the current driven crystal oscillator circuit ofFIG. 2includes a tenth N-type transistor T10having a source S10, a drain D10and a gate G10and a ninth P-type transistor T9having a source S9, a drain D9and a gate G9. The gate G9of the ninth transistor T9is connected to the gate G10of the tenth transistor T10and to second end r22of the resistor R2. The drain D9of the ninth transistor T9is connected to the drain D10of the tenth transistor T10. The source S10of the tenth transistor T10is connected to the ground and the source S9of the ninth transistor T9is connected to the current source I1.

The output circuit OC of the current driven crystal oscillator circuit ofFIG. 2includes a twelfth N-type transistor T12having a source S12, a drain D12and a gate G12and an eleventh P-type transistor T11having a source S11, a drain D11and a gate G11. The gate G11of the eleventh transistor T11is connected to the gate G12of the twelfth transistor T12which are together connected to the drains D9, D10of the ninth and tenth transistors T9, T10, respectively. The drain D11of the eleventh transistor T11is connected to the drain D12of the twelfth transistor T12, The source S12of the twelfth transistor T12is connected to the ground and the source S11of eleventh the transistor T11is connected to the current source I1.

Furthermore, the current driven crystal oscillator circuit ofFIG. 2includes a capacitor C6having a first end c61and a second end c62, a capacitor C8having a first end c81and a second end c82, a resistor R7having a first end r71and a second end r72, and crystal oscillator X1having a first end x11and a second end x12. The first end c61of the capacitor C6is connected to the ground, the second end c82of the capacitor C8is connected to the ground, the second end c62of the capacitor C6is connected to the first end r71of the resistor R7, to the first end x11of the crystal oscillator X1, and to the second end r22of the resistor R2. The second end r72of the resistor R7is connected, via a switch SW2to first end c81of the capacitor C8, to the second end x12of the crystal oscillator X1, and to the second end r42of the resistor R4.

Finally, the circuit ofFIG. 2comprises a further current source IShaving an output connected to an output of the current source I1via a switch SW1. So, all elements in the oscillator circuit shown inFIG. 2are current driven. This provides several features to the oscillator circuit, including:Much less spread over processing cornersThe oscillator circuit is now self-adjusting to a suitable supply voltage which will be as low as possible but not lower than a minimum value necessary for the oscillator circuit to operate properlyThe individual components can be easily designed, especially scaling is simple.

The basic operation of the circuit ofFIG. 2will now be described.

The person skilled in the art will recognize that the oscillator stage OS has a similar construction as the oscillator shown inFIG. 1. The main differences between the oscillator stage OS and the oscillator ofFIG. 1are that the feedback resistor R1is replaced by the regulator OA1, that source S8of eighth transistor T8is connected to ground via resistor R6, that the source S7of seventh transistor T7is connected to resistor R5, and that resistor R7(which is comparable to resistor R1inFIG. 1) is arranged in series with switch SW2. Moreover all peripheral circuits of the oscillator are supplied by current source Iddx.

FIG. 3shows a higher level block diagram of the circuit according toFIG. 3only showing the current source Iddx, the bias circuit BC, the regulator/Low Pass Filter circuit R/LPF, the oscillator stage OSC, the current mode comparator CMC, and output stage OS, and their mutual connections.

The bias circuit BC provides an output voltage VBC,out.

The regulator/Low Pass Filter circuit R/LPF receives the output voltage VBC, outof the bias circuit BC as its input voltage VR/LPF,in. Moreover, the regulator/Low Pass Filter circuit R/LPF provides an output voltage VR/LPF,outto the input of the oscillator stage OSC. Furthermore, the operational amplifier OA1in the regulator/Low Pass Filter circuit R/LPF receives a feedback signal which is derived from the voltage difference between the input and output of the oscillator stage OSC, which, in the shown embodiment is equal to the voltage across the oscillator X1.

The regulator/Low Pass Filter circuit R/LPF is arranged such that DC input voltage of the oscillator stage OSC is equal to the DC output voltage of the oscillator stage OSC. In the shown embodiment this is taken care of by the operational amplifier OA1in regulator R/LPF which charges/discharges capacitor C6so that the average input voltage of the oscillator stage OSC is equal to the average output voltage of the oscillator stage OSC. It is observed that a feedback of the voltage difference between the input and output of the oscillator stage OSC to any type of operational amplifier of which the output is coupled to the input of the oscillator stage OSC can be used for this purpose.

In contrast to most other oscillators, in the preferred embodiment, the comparator is not a ‘voltage-mode’ comparator. Such a ‘voltage-mode’ comparator would have its input connected to the output of the oscillator stage OSC. Here, the input of the current-mode comparator CMC is connected to the input of the oscillator stage OSC. The current-mode comparator CMC flags if the absolute current through transistor T7is larger or smaller than the absolute current through transistor T6. A voltage-mode comparator could be used as well, though would result in more phase noise.

The oscillator and all its peripheral circuits run at self-biasing voltage Vddx. Vddxis lower than the supply voltage Vddof other circuitry to save power in the oscillator. Inside the oscillator, apart from the level shifter, the logic level is the internal supply voltage Vddx. The output stage of the oscillator is a level-shifter L which converts the logic level of the signal as received by the output circuit OC to the supply voltage Vddof the circuitry to which the resulting oscillating signal is to be provided.

The bias circuit BC ofFIG. 3receives a current from the current source Iddxat the source S4of the transistor T4. See alsoFIG. 2. This current generates a voltage Vgs4between the gate G4/drain D4and the source S4of the transistor T4such that T4is in saturation mode. The transistor T4working in saturation provides a current Ibiasto the transistor T5. As a consequence, a voltage VPis present between the source S4and the gate G4/drain D4of the transistor T4, and a voltage VNis present between the drain D5/gate G5and the source S5of the transistor T5. Defining the output voltage of current source Iddxas Vddxthe following equation holds:
Vddx−VP=VN

Transistor T5is connected in a current mirror arrangement with transistor T6. I.e., the voltage across the gate-source of transistor T6is equal to the voltage across the gate-source of transistor T5. Since all transistors have been produced in the same manufacturing step on the same die, the current that flows through transistor T6has a fixed ratio to the one flowing through transistor T5as determined by their relative surface areas. The drain current through T6is the bias current of the operational amplifier OA1in regulator R/LPF (see e.g., the embodiment ofFIG. 4). The reference voltage at the non-inverting input of the operational amplifier OA1is the low-pass filtered output voltage of oscillator stage OSC (high frequency components in the output voltage of oscillator stage OSC are short-circuited to ground via capacitor C5). The feedback voltage of the regulator R/LPF at the inverting input of the operational amplifier OA1is the low-pass filtered input voltage of oscillator stage OSC (high frequency components in the output voltage of oscillator stage OSC are short-circuited to ground via capacitor C4). The output of the regulator R/LPF is connected to the input of the oscillator stage OSC and charges/discharges capacitor C6until the voltage at both inputs of the operational amplifier OA1in the regulator R/LPF are the same. As the Wi/Li ratio's of T7and T8are similar to T4and T5(wherein Wirepresents the channel width of transistor Tiand Lirepresents the channel length of transistor Ti) the average of input and output voltage of the oscillator stage OSC is equal to VN. The same applies for the Wi/Liratio's of the transistors of stages CMC and OC and therefore their turn-over point is close to a voltage level equal to VN.

Therefore, due to the configuration of the circuit ofFIG. 2, the same voltage difference VPis present between the output voltage Vddxof the current source Iddxand the gate G7of the transistor T7, between the output voltage Vddxof the current source Iddxand the gate G9of the transistor T9, and between the output voltage Vddxof the current source Iddxand the gate G11of the transistor T11. Also for the same reason, the same voltage difference VNis present between the gate G8of the transistor T8and ground, between the gate G10of the transistor T10and ground, and between the gate G12of the transistor T12and ground.

As can be seen in the circuit ofFIG. 2, the voltage between the output of the current source Iddxand ground is VN+VP.

In this way, all the stages of the circuit ofFIG. 3, namely the bias circuit BC, the regulator/LPF circuit R/LPF, the oscillator stage OSC, the current-mode comparator CMC and the output stage OS, are well-balanced independent of the processing corner of the total circuit, the actual temperature in use and the injected current in use.

The DC voltage at the output of the operational amplifier OA1follows the DC voltage present at the inverting and non-inverting inputs of the operational amplifier OA1which are controlled to be the same.

The resistor R3at the output of the operational amplifier OA1prevents that a rail-to-rail swing of the voltage Vx1is causing linearity errors in the regulator and LPF circuit R/LPF.

The operational amplifier OA1is connected in a closed loop wherein the output of the operational amplifier OA1, which is connected to the input of the oscillator stage OSC, is fed back to the inverting input of the operational amplifier OA1via resistor R2. The non-inverting input of the operational amplifier OA1is connected through the resistor R4to the output of the oscillator stage OSC. So, stated differently the input and the output of the oscillator stage OSC are feedback to the inverting and non-inverting inputs of the operational amplifier OA1. In use, these inverting and non-inverting inputs will have the same DC voltage level. In this way, the operational amplifier OA1of the regulator and LPF circuit R/LPF controls that the DC voltage level at the input of the oscillator stage OSC is the same as the DC voltage level at the output of the oscillator stage OSC. So, the operational amplifier OA1substitutes resistor R1in the prior art setup ofFIG. 1, the advantage being that such an operational amplifier OA1dissipates less electrical energy in use.

However, providing only this feedback circuit with the operational amplifier OA1would cause a relatively slow start-up of the total circuit.

Therefore, the series connection of resistor R7and switch SW2has been provided which has the same function as resistor R1in the circuit according to the prior art (FIG. 1), however, only at the time of starting the circuit. I.e., at the time of starting, the switches SW1and SW2are both closed such as to allow current to flow. Oscillator crystal X1oscillates and provides an oscillating signal at its output terminals x11and x12. An oscillating voltage is built up across the resistor R7. This oscillating signal across oscillator crystal X1is output to the inverting and non-inverting input terminals of the operational amplifier OA1in the R/LPF circuit such that its output also generates an oscillating signal which is, then, provided to the rest of the circuit, as explained above. In the circuit ofFIG. 3, after initialisation, i.e., when the operational amplifier OA1provides a stable oscillating signal at its output, switches SW1and SW2are opened such that no current will flow anymore through them. Then, no current will flow anymore through resistor R7either, thus saving energy. Even though, after initialisation, the resistor R7is disconnected from the circuit, the operational amplifier OA1in R/LPF circuit causes the DC voltage difference across the oscillator crystal X1to be 0 (zero). I.e., both terminals x11and x12are controlled to be at the same DC voltage VN. A method to control the opening of switches SW1and SW2is to count a predetermined number of generated pulses by the oscillator after start-up. To that end, the output signal of the oscillator can be fed to a counting circuit which counts the number of pulses of the generated signal and which is arranged to control the opening/closing of switches SW1band SW2. For example SW1and SW2are opened by such a counting circuit if1024pulses are counted.

On average, in a preferred embodiment, DC voltages Vx1, Vx2, VN, and VPare substantially the same in the circuit ofFIG. 3. Here, “substantially” means that these DC voltages are intended to have the same values but they may differ slightly in practice, due to tolerances in design of the different used transistors.

In the oscillator stage OSC of the circuit ofFIG. 2no amplitude control is required as the current source Iddxdefines the voltage Vddx. The oscillator stage OSC is a push/pull stage with a double gm if compared with a single transistor “grounded source” configuration at the same current. Apart from a small voltage drop across the respective resistors R5and R6, the voltage at the interconnected drains D7and D8swings between ground and voltage Vddx. The resistors R5and R6soften the clamping of Vx2.

Apart from the resistors R5and R6, the current mode comparator CMC is a copy of the oscillator stage OSC, but the oscillator stage OSC drives a heavy load, i.e. the load capacitors C6and C8, that requires relative high current, while the current-mode comparator CMC itself drives a tiny load, i.e. output circuit OC, that allows the output of the output circuit OC to jump from “rail to rail”, i.e. between voltage Vddxand ground. The voltage drop at peak currents over the resistors R5and R6boosts the current-gain of the current-mode comparator CMC.

The output stage OS is a copy of the current-mode comparator CMC. However, the respective sizes of the transistors T11and T12differ from the respective sizes of the transistors T9and T10, such that the current consumption is very low, the output stage OS form a relatively small load to the current-mode comparator CMC, and can drive a relatively heavy load itself.

To summarize, the basic functionalities of the respective functional blocks ofFIGS. 2 and 3are as follows:Current source Iddx: arranged to provide a constant current to the entire current driven oscillator circuit; eventually Iddxcan have a temperature coefficient to fine tune the Temperature Coefficient TC performance of the oscillator.Bias circuit BC: arranged to provide a well-defined first DC output voltage VBC,out;Regulator and LPF circuit R/LPF: arranged to provide a same second DC output voltage VR/LPCat two different output terminals while allowing an oscillating voltage signal to be present between these two output terminals;Oscillator stage OSC: arranged to provide a first oscillating signal VOSC,out;Current-mode comparator CMC: arranged to receive the oscillating signal VOSCand to provide an amplified oscillating signal. This amplified oscillating signal clamps between ground and Vddx.Output stage OS: arranged to form a small load to the output of the current mode comparator CMC and to allow driving the level shifter L.Level shifter L: arranged to convert the logic level of the output signal VCMC,outof the current-mode comparator CMC to a required logic level of the circuits receiving the oscillator signal of the oscillator as shown inFIGS. 2 and 3.

FIG. 4shows an alternative bias circuit BC′ to the one shown inFIG. 2as well as an example of the operational amplifier OA1of the oscillator circuit in which same reference number refer to the same components as inFIGS. 2 and 3.

The alternative bias circuit BC′ ofFIG. 4includes the regulator OA1and comprises a plurality of transistors Tj(j=13, 14, . . . 17). Each one of these transistors Tihas a respective gate Gj, a source Sj, and a drain Dj.

The alternative bias circuit BC′ ofFIG. 4includes a thirteenth N-type transistor T13having its source terminal S13connected to the drain terminal D5of transistor T5, its drain terminal D13connected to the drain terminal D4of transistor T4, to its gate G13and to the gate G5of transistor T5, a fourteenth N-type transistor T14having a source S14connected to the drain D6of the transistor T6and a gate G14connected to the first end r21of the resistor R2(not shown inFIG. 4), a fifteenth N-type transistor T15having a source S15connected to the drain D6of the transistor T6and a gate G15connected to the first end r41of the resistor R4(not shown inFIG. 4), a sixteenth P-type transistor T16having a drain D16connected to the drain D14of the transistor T14, a gate G16connected to the drain D14of the transistor T14, and a source S16connected to the current source Iddx, and a seventeenth P-type transistor T17having a drain D17connected to the drain D15of the transistor T15and to the first end r31of the resistor R3(not shown inFIG. 4), a gate G16connected to the drain D14of the transistor T14, and a source S17connected to the current source Iddx. By doing so, gate G15is the inverting input and gate G14is the non-inverting input, whereas the node of drain D15/drain D17is the output of the regulator.

In the set-up ofFIG. 4, the additional cascode transistor T13is characterized by having W13/L13>>β, where β=W/L of transistor T5, resulting in a lower gate-source voltage Vgs13, and the drain-source voltage Vds5across drain D5and source S5meeting the condition: Vds5>Vdsat5, where Vdsat5is the saturation voltage of transistor T5. So, transistor T5is in saturation.

In an example, transistor T6meets the condition 2*W/L and the condition Vds6>Vdsat6. So, transistor T6is in saturation too.

For both transistors T14and T15are characterized by having W14/L14>>β and W15/L15>>β.

Because of these conditions being met, the regulator stage R/LPF (here comprising transistors T6, T14, T15, T16, T17is having all transistors in saturation if:
Vin+≈Vin−≈VN≈Vddx−VP,

The current driven crystal oscillator circuit illustrated inFIG. 2may work in a transceiver mode wherein stabilized frequencies for radio transmitters and/or receivers can be generated. In this mode, rising/falling edges of the generated oscillating signal as eventually produced should be as accurate as possible such that they define moments in time at which certain actions may start/end are as accurate as possible. This is achieved by injecting relatively more current in the oscillator circuit by current source Iddxsuch that lower phase noise is obtained.

Circuit dimensions are linear proportional to a large extend to the crystal frequency. The following main parameters may apply to the circuit ofFIG. 2:

Iddxsupply current injected into the oscillator.

RSPNequivalence series resistance of resistors R5and R6in the oscillator stage OS.

RSTARTresistance of the feedback resistor in the start-up mode (R7inFIG. 2).

RSequivalence series resistance of resistor (R3inFIG. 2) and the regulator OA1in the OA/LPF.

βBIASchannel width divided by channel length of the channel of the NMOS transistor of the bias circuit BS (T5inFIG. 2).

βOSCchannel width divided by channel length of the channel of the NMOS transistor in the oscillator stage OS (T8).

βCP1channel width divided by channel length of the channel of the NMOS transistor of the current-mode comparator CMC (T10inFIG. 2).

βCP2channel width divided by channel length of the channel of the NMOS transistor of the output circuit OC (T12inFIG. 2).αPNchannel width divided by channel length of the channel of the PMOS transistor divided by channel width divided by channel length of the channel of the NMOS transistor in the bias circuit BC, oscillator stage OScurrent-mode comparator CMC and output circuit OC.

In one embodiment of the current driven crystal oscillator circuit ofFIG. 2working in a transceiver mode, the plurality of circuit dimensions ofFIG. 2may have the following values:

αPN2.5 and the channel width divided by channel length of the channel of T6is 2*βBIAS.

These parameters may have a value in a range from 50% to 150% of the above nominal values. Preferably, these parameters may have a value in a range from 75% to 125% of the above nominal values and even more preferably, these parameters may have a value in a range from 90% to 110% of the above nominal values.

In this way, the current provided by the current source Iddxof the current driven crystal oscillator circuit ofFIG. 2working in a transceiver mode will be distributed between the different blocks in the following way: current Ibiasof the bias circuit will be ≈2.5% of current Iddx, current Ioscof the oscillator stage OS will be ≈78% of current Iddx, current Icp1of the current-mode comparator CMC will be ≈14% of current Iddx, and current Icp2of the output circuit OC will be ≈0.5% of current Iddx. The remaining 5% of Iddxcurrent is consumed by the regulator (OA1).

FIG. 5,FIG. 6,FIG. 7,FIG. 8andFIG. 9illustrate simulation results of the current driven crystal oscillator circuit ofFIG. 2working in a transceiver mode. InFIG. 5,FIG. 6,FIG. 7andFIG. 8the horizontal axes represent in microamperes the current Iddxof the current driven crystal oscillator circuit ofFIG. 2working in a transceiver mode. The vertical axes represent: inFIG. 5, Vx1, Vx2, and avg_vddx represented in volts, inFIG. 6, the ratio of swing voltage represented in volts to Vddxrepresented in volts, inFIG. 7, the efficiency factor defined by the ratio of swing voltage represented in volts to current Iddxrepresented in amperes, and inFIG. 8, the duty cycle of the output signal as provided by the level shifter LInFIG. 9, the horizontal axis also represents in microamperes the current Iddx, which represents the total current of the whole current driven crystal oscillator circuit ofFIG. 2; working in a transceiver mode and along the vertical axis five curves are illustrated which represent respectively the percentage % of current Iddxthat goes to ICP2, the percentage % of current Iddxthat goes to current Ibias, the percentage % of current Iddxthat goes to current Ireg, the percentage % of current Iddxthat goes to current ICP1and the percentage % of current Iddxthat goes to current IOSC.

As shown in the simulations illustrated inFIG. 5,FIG. 6,FIG. 7,FIG. 8andFIG. 9the current Iddxis swept from 10 microampere to 300 microamperes, the capacitors C6and C8have a capacitance of 18 picofarads, and the circuit works at a temperature of 25 degrees Celsius.

To accelerate the start-up of the crystal oscillator a relative high current (ISinFIG. 2) is injected in the transceiver mode configuration while resistors R5and R6are shorted by a switches and switch SW2(inFIG. 2) is closed. More than 90% of the injected current (sum of Iddxand IS) flows in the oscillator stage (T7and T8) maximizing its transconductance. Start-up resistor RSTART(R7inFIG. 2) takes care that the input and output voltage of the oscillator stage are approximately equal at start-up independent of the regulator (OA1inFIG. 2). A 12-bit clock counter (212=4096 clock pulses) which is reset by a POR (Power-On Reset)-signal can be used to switch from start-up mode to transceiver mode after starting the oscillator. Resistor RSTART(R7inFIG. 2) can be 100 kΩ and IScan be 1 mA for a 16 MHz crystal. For a lower crystal frequency a higher value for RSTARTcan be used in combination with a lower start-up current (IS).

The current driven crystal oscillator circuit illustrated inFIG. 2can also work in a timer mode in order to provide a stable clock signal. In this embodiment, requirements as to phase noise are less strict because the timer will count an average number of oscillation cycles by counting the number of rising/falling edges only. So, here, the current as injected into the oscillator circuit by current source Iddxcan be much less than in the transceiver mode.

In one embodiment of the current driven crystal oscillator circuit ofFIG. 2working in a timer mode, the plurality of circuit dimensions ofFIG. 2may have the following values:Iddx≈fXTAL*125 fA/Hz(≈2 μA at fXTAL=16 MHz; ≈4 nA at fXTAL=32 kHz)fLPF≈fXTAL,/40 (≈400 kHz at fXTAL=16 MHz)RSPN≈0 mV/Iddx(≈0Ω at fXTAL=16 MHz→closed switch over R5and R6inFIG. 2)βBIAS≈16 μA/Iddx(≈8≈0.2*2.4 μm/60 nm at fXTAL=16 MHz;so if L=60 nm then W=0.2*2.4μ=0.48 m)βOSC≈1.25 mA/Iddx(≈640≈16*2.4 μm/60 nm at fXTAL=16 MHz)βCP1≈16 μA/Iddx(≈8≈0.2*2.4 μm/60 nm at fXTAL=16 MHz)βCP2≈8 μA/Iddx(≈4≈0.1*2.4 μm/60 nm at fXTAL=16 MHz)αPN≈2.5 and the channel width divided by channel length of the channel of T6is 2*βBIAS

These parameters may have a value in a range from 50% to 150% of the above nominal values. Preferably, these parameters may have a value in a range from 75% to 125% of the above nominal values and even more preferably, these parameters may have a value in a range from 90% to 110% of the above nominal values.

In this way, the current provided by the current source I1of the current driven crystal oscillator circuit ofFIG. 2working in a timer mode will be distributed between the different blocks in the following way: current Ibiasof the bias circuit will be ≈0.5% of current I1, current Ioscof the oscillator stage OS will be ≈97% of current I1, current Icp1of the current-mode comparator CMC will be ≈1% of current I1, and current Icp2of the output circuit OC will be ≈0.1% of current I1. The remaining 1% of I1current is consumed by the regulator (OA1).

FIG. 10,FIG. 11,FIG. 12andFIG. 13andFIG. 14illustrate simulation results of the current driven crystal oscillator circuit ofFIG. 2working in a timer mode. InFIG. 10,FIG. 11,FIG. 12andFIG. 13andFIG. 14, the same results as inFIG. 5,FIG. 6,FIG. 7,FIG. 8andFIG. 9, but for the timer mode, are represented, respectively. In the simulations for obtaining the results represented inFIG. 10,FIG. 11,FIG. 12andFIG. 13andFIG. 14, the current Iddxvaries between 0.7 microampere and 3 microamperes, the capacitors C6and C8have a capacitance of 8 picofarads, and the circuit temperature works at 25 degrees Celsius.

FIG. 15,FIG. 16,FIG. 17andFIG. 18also illustrate simulation results of the current driven crystal oscillator circuit ofFIG. 2working in a timer mode. InFIG. 15,FIG. 16,FIG. 17andFIG. 18, the horizontal axes represent temperature in degrees Celsius. The vertical axes represent: inFIG. 15, Vx1and Vx2represented in volts, inFIG. 16, the ratio of swing voltage represented in volts to Vddxrepresented in volts, inFIG. 17, the efficiency factor defined by the ratio of swing voltage represented in volts to current Iddxrepresented in amperes, and inFIG. 18, the duty cycle of the output signal as provided by the level shifter L, wherein for each of the four figures, three curves are shown for each parameter representing simulation results for nominal process corner and for the extremes of the processing corners: the so-called ‘fast’ corner and the ‘slow’ corner. In the slow corner all process parameters are set to the processing limits which results to the slowest possible circuits.

FIG. 19illustrates simulation results of the current driven crystal oscillator circuit ofFIG. 2working in a timer mode. InFIG. 19, the horizontal axis represents temperature in degrees Celsius and the vertical axis represents the percentage of current Iddxthat goes to current IOSC. Also here three curves are shown.

During the simulations for obtaining the results represented inFIG. 10-19, the current Iddxwas set at 1.5 microamperes, the capacitors C6and C8had a capacitance of 8 picofarads, and the circuit temperature sweep over processing corners.

The three embodiments described above wherein the oscillator circuit illustrated inFIG. 2can work in a transceiver mode, a timer mode, or a accelerated start-up mode, may be combined in a single circuit wherein the circuit may comprise separate, distinct (transistor) elements in the oscillator circuit for each mode and suitably arranged switches arranged to connect or disconnect them to the rest of the oscillator circuit depending on the mode the circuit should work in. For instance, the circuit according to this embodiment may comprise two versions of transistor T10, one of them with an area value of 10x and another one with an area value of 0.15x, wherein 1x=2.4 μm/60 nm. If the circuit is working in a transceiver mode the transistor from the two versions of T10with an area value of 10x will be the one connected to the circuit by means of these switches, while if the circuit is working in a timer mode, the transistor with an area of 0.15x will be the one connected to the circuit by means of these switches.

It will be clear to a person skilled in the art that the scope of the invention is not limited to the examples discussed in the foregoing, but that several amendments and modifications thereof are possible without deviating from the scope of the invention as defined in the attached claims. While the invention has been illustrated and described in detail in the figures and the description, such illustration and description are to be considered illustrative or exemplary only, and not restrictive. The present invention is not limited to the disclosed embodiments but comprises any combination of the disclosed embodiments that can come to an advantage. The invention is limited by the attached claims and their technical equivalents only.

Variations to the disclosed embodiments can be understood and effected by a person skilled in the art in practicing the claimed invention, from a study of the figures, the description and the attached claims. In the description and claims, the word “comprising” does not exclude other elements, and the indefinite article “a” or “an” does not exclude a plurality. In fact it is to be construed as meaning “at least one”. The mere fact that certain features are recited in mutually different dependent claims does not indicate that a combination of these features cannot be used to advantage. Any reference signs in the claims should not be construed as limiting the scope of the invention.