Methods for depositing amorphous silicon layers or silicon oxycarbide layers via physical vapor deposition

In some embodiments, a method of processing a substrate disposed atop a substrate support in a physical vapor deposition process chamber includes: (a) forming a plasma from a process gas within a processing region of the physical vapor deposition chamber, wherein the process gas comprises an inert gas and a hydrogen-containing gas to sputter silicon from a surface of a target within the processing region of the physical vapor deposition chamber; and (b) depositing an amorphous silicon layer atop a first layer on the substrate, wherein adjusting the flow rate of the hydrogen containing gas tunes the optical properties of the deposited amorphous silicon layer.

FIELD

Embodiments of the present disclosure generally relate to methods for depositing amorphous silicon films and silicon oxycarbide films via physical vapor deposition.

BACKGROUND

The overall size of the integrated circuit components are limited by the smallest geometrical feature that can be etched into the substrate, the critical dimension (CD). Etching features into a substrate uses a variety of materials for different purposes.

For example, amorphous silicon films can used in a variety of semiconductor manufacturing applications, for example as a sacrificial layer in a self-aligned double patterning (SADP) process or a self-aligned quadruple patterning process (SAQP). Typically, such amorphous silicon films may be formed via a chemical vapor deposition (CVD) process. However, the inventors have observed that amorphous silicon films deposited via a chemical vapor deposition (CVD) process can demonstrate bubbling and peeling and little to no optical tunability.

As a further example, silicon-based antireflective coating (Si-ARC) are often used as part of a multi-layer resist, along with for example a photoresist layer, in etching features into a substrate. A silicon-based antireflective coating (Si-ARC) are typically formed via spin-on coating methods. However, silicon-based antireflective coating (Si-ARC) can leave particle residue on underlying layer upon removal.

Accordingly, the inventors have provided improved methods for depositing amorphous silicon films via a physical vapor deposition process and an improved substitute for silicon-based antireflective coating (Si-ARC) in a multi-layer resist.

SUMMARY

Embodiments of the present disclosure include methods for processing a substrate. In some embodiments, a method of processing a substrate includes: a method of processing a substrate disposed atop a substrate support in a physical vapor deposition process chamber includes: (a) forming a plasma from a process gas within a processing region of the physical vapor deposition chamber, wherein the process gas comprises an inert gas and a hydrogen-containing gas to sputter silicon from a surface of a target within the processing region of the physical vapor deposition chamber; and (b) depositing an amorphous silicon layer atop a first layer on the substrate, wherein adjusting the flow rate of the hydrogen containing gas tunes the optical properties of the deposited amorphous silicon layer.

In some embodiments, a method of processing a substrate disposed atop a substrate support in a physical vapor deposition process chamber, includes: (a) forming a plasma from a process gas within a processing region of the physical vapor deposition chamber, wherein the process gas comprises an inert gas and a hydrogen-containing gas to sputter source material from a surface of a target within the processing region of the physical vapor deposition chamber; (b) depositing a layer of one of carbon (C), aluminum oxide (AlOx), aluminum nitride (AlN), aluminum oxynitride (AlON) silicon dioxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), silicon oxycarbide (SiOC) or titanium nitride (TiN) atop the substrate wherein adjusting the flow rate of the hydrogen containing gas tunes optical properties, stress, film morphology and surface properties of the deposited layer. In some embodiments, depositing of (b) further includes depositing a layer of one of carbon, metal oxide, aluminum oxide (AlOx), aluminum nitride (AlN), aluminum oxynitride (AlON) silicon dioxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), silicon oxycarbide (SiOC), tantalum oxide (TaOx), tin oxide (SnOx), tin silicon oxide (SnSiOx), or titanium nitride (TiN) atop the substrate wherein adjusting a flow rate of the hydrogen containing gas tunes optical properties, stress, film morphology and surface properties of the deposited layer.

In some embodiments, a method of processing a substrate disposed atop a substrate support in a physical vapor deposition chamber, includes: (a) forming a plasma from a process gas within a processing region of the physical vapor deposition chamber, wherein the process gas comprises an inert gas and a carbon monoxide (CO) gas to sputter silicon from a surface of a target within the processing region of the physical vapor deposition chamber; and (b) depositing a silicon oxycarbide (SiOC) layer having a density between 1.67 and 2.3 g/cm3atop the substrate by tuning at least one of a pressure and a temperature of the physical vapor deposition chamber.

DETAILED DESCRIPTION

The present disclosure relates to methods of depositing amorphous silicon layers or films via a physical vapor deposition process. In at least some embodiments, the inventive methods described herein advantageously deposits an amorphous silicon layer without bubbling or peeling of the amorphous silicon layer during subsequent SADP (self-aligned double patterning) or SAQP (self-aligned quadruple patterning) processing. In at least some embodiments, the inventive methods described herein further advantageously provide for tuning the optical properties of the amorphous silicon film. The present disclosure further relates to methods of depositing silicon oxycarbide (SiOC) layers or films via a physical vapor deposition process. In at least some embodiments, the inventive methods described herein further advantageously provide for tuning the density and the optical properties of the silicon oxycarbide (SiOC) layers.

FIG. 1depicts a simplified, cross-sectional view of an illustrative physical vapor deposition (PVD) processing system100, in accordance with some embodiments of the present disclosure.FIG. 2depicts a flow chart of a method200for depositing amorphous silicon films atop a substrate disposed in a physical vapor deposition process system of the type described inFIG. 1. The method200is described below with respect to the stages of processing a substrate as depicted inFIGS. 3A-3I. Examples of PVD chambers suitable for performing the method200described herein include the CIRRUS™, AVENIR™ and IMPULSE PVD processing chambers, commercially available from Applied Materials, Inc., of Santa Clara, Calif.

The physical vapor deposition process chamber (process chamber104) depicted inFIG. 1comprises a substrate support106, a target assembly114having an optional backing plate assembly160and source material113which is disposed on a substrate support facing side of the backing plate assembly160. The process chamber104further comprises an RF power source182to provide RF energy to the target assembly114. Additional details relating to the illustrative PVD processing system100are discussed below.

The method may be performed on an exemplary substrate108disposed within the process chamber104. The substrate108may be any suitable substrate having any suitable geometry, such as a round wafer, square, rectangular, or the like. The substrate108may comprise any suitable materials, such as one or more of silicon (Si), silicon oxide (SiO2), silicon nitride (SiN), glass, other dielectric materials, or the like. In some embodiments, the substrate108may be a semiconductor wafer (e.g., a 200 mm, 300 mm, or the like silicon wafer). In some embodiments, the substrate108may include additional layers, for example a dielectric layer. In some embodiments, the substrate may be a partially fabricated semiconductor device such as Logic, DRAM, or a Flash memory device. In addition, features, such as trenches, vias, or the like, may be formed in one or more layers of the substrate108.

In some embodiments, as depicted inFIG. 3A, the substrate108has a first layer300disposed atop the substrate108. In the embodiments, the first layer300is directly atop the substrate108. In some embodiments, the first layer300is a dielectric layer such as a tetraethylorthosilicate (TEOS) layer having the formula Si(OC2H5)4), or silicon nitride, or silicon oxide.

The method200begins at202by forming a plasma from a process gas within a processing region120of the process chamber104. In some embodiments, the process gas comprises an inert gas and a hydrogen containing gas. In some embodiments, the process gas consists of, or consists essentially of, an inert gas and a hydrogen containing gas. In some embodiments, the inert gas is a noble gas such as argon, helium, neon or xenon. In some embodiments, the hydrogen containing gas is hydrogen (H2) gas, ammonia (NH3), or a hydrocarbon, such as an alkane having the formula CnH2n+2(e.g. CH4, C2H6, C3H8). In some embodiments, the hydrogen containing gas is one of hydrogen (H2) gas, ammonia (NH3), or a hydrocarbon, such as an alkane having the formula CnH2n+2(e.g. CH4, C2H6, C3H5). In some embodiments, the hydrogen containing gas is hydrogen (H2) gas, ammonia (NH3), a hydrocarbon, such as an alkane having the formula CnH2n+2(e.g. CH4, C2H6, C3H8), and combinations thereof. The hydrogen containing gas is not a compound of hydrogen and a halogen (e.g. HCl, HBr, or HF)

The inert gas is provided to the processing region120of the process chamber104at a flow rate of about 50 sccm to about 1000 sccm. The hydrogen containing gas is provided to the processing region120of the process chamber104at a flow rate of about 2 to about 100 sccm. In some embodiments, the process gas comprises about 1% to about 50% hydrogen and the balance inert gas.

The process gas may be formed into a plasma by coupling sufficient energy, from a power source to ignite the process gas described above to form the plasma. The power source may be operable in a continuous wave (CW) or pulsed mode. The power source may include direct current (DC), pulsed DC, or radio frequency (RF) power. In some embodiments, the power source may illustratively provide RF power at about 500 W to about 6 kW of power, for example about 2 kW, at a suitable frequency, such as about 13.56 MHz to form the plasma. In some embodiments, the power source may provide pulsed DC power at a pulse frequency of about 100 to about 250 kHz and at a duty cycle (e.g., the percentage of on time during the total of on time and off time in a given cycle) of about 10% to about 40%.

Next at204, an amorphous silicon layer302is deposited atop the first layer300on the substrate108. As used herein, amorphous silicon refers to a non-crystalline form of silicon. In some embodiments, as depicted inFIG. 3B, the amorphous silicon layer302is formed directly atop the first layer300. In some embodiments, the amorphous silicon layer302is deposited to a thickness suitable for patterning processes in various semiconductor processes. For example, the amorphous silicon layer302can be deposited to a thickness of about 200 to about 550 Angstroms.

The plasma formed in202facilitates a sputtering of the source material113, for example silicon source material, from the target assembly114, causing a deposition of material on the first layer300atop the substrate108, to form the amorphous silicon layer302. The inventors have observed that deposition of the amorphous silicon layer302via the inventive methods described herein advantageously deposits an amorphous silicon layer302that does not bubble or peel during subsequent SADP (self-aligned double patterning) or SAQP (self-aligned quadruple patterning) processing as can be found in a CVD deposited amorphous silicon layer.

Furthermore, the introduction of the hydrogen containing gas to deposit the amorphous silicon layer302allows for the tuning of the optical properties of the amorphous silicon layer302. Specifically, adjusting the flow rate of the hydrogen containing gas tunes or adjusts the k-value of the amorphous silicon layer between about 0.1 and 0.41 and tunes or adjusts the n-value of the amorphous silicon layer between about 4.22 and 3.54. As used herein, the n-value refers to the refractive index of a material and the k-value refers to the extinction coefficient of the material.

FIG. 4Adepicts a graph400showing the k-value of an amorphous silicon layer formed at hydrogen (H2) gas flow rates of 0 sccm H2, 5 sccm H2and 10 sccm and at varying source power of 1.25 kW, 2 kW, and 3 kW. Line402shows the k-value for an amorphous silicon layer formed with a 0 sccm flow rate of H2gas. Line404shows the k-value for an amorphous silicon layer formed with a 5 sccm flow rate of H2gas. Line406shows the k-value for an amorphous silicon layer formed with a 10 sccm flow rate of H2gas. As seen from graph400, increasing the flow rate of hydrogen (H2) gas decreases the k-value of the amorphous silicon layer at a constant source power. For example, at a source power of 1.25 kW, the k-value for H2gas flow rates of 0 sccm, 5 sccm, and 10 sccm are 0.39, 0.19, and 0.09, respectively. Accordingly, increasing the H2gas flow rate decreases the k-value of the amorphous silicon layer by about 77%. The k-value of the amorphous silicon layer formed with an increasing flow rate of H2gas at the source power of 2 kW and 3 kW similarly shows a decrease of about 70% and 63% respectively. While keeping the H2gas flow rate constant and decreasing the source power also shows a decrease in k-value, the magnitude of the decrease is not as pronounced as compared to adjusting the H2gas flow rate and keeping the source power constant. For example, line406shows that keeping the H2gas flow rate at a constant 10 sccm while reducing the source power from 3 kW to 1.25 kW only reduces the k-value of the amorphous silicon layer by about 40 percent. A person of ordinary skill in the art will recognize that a specific k-value can be obtained through routine experimentation to determine the proper H2gas flow rate and source power combination.

FIG. 4Bdepicts a graph408showing the 2-value of an amorphous silicon layer formed at hydrogen (H2) gas flow rates of 0 sccm H2, 5 sccm H2 and 10 sccm and at a varying source power of 1.25 kW, 2 kW, and 3 kW. Line410shows the n-value for an amorphous silicon layer formed with a 0 sccm flow rate of H2gas. Line412shows the n-value for an amorphous silicon layer formed with a 5 sccm flow rate of H2gas. Line414shows the n-value for an amorphous silicon layer formed with a 10 sccm flow rate of H2gas. As seen from graph408, increasing the flow rate of hydrogen (H2) gas decreases the n-value of the amorphous silicon layer at a constant source power. For example, at a source power of 1.25 kW, the n-values for H2gas flow rates of 0 sccm, 5 sccm, and 10 sccm are 4.05, 3.74, and 3.52, respectively. Accordingly, increasing the H2gas flow rate decreases the n-value of the amorphous silicon layer by about 13%. The n-value of the amorphous silicon layer formed with an increasing flow rate of H2gas at the source power of 2 kW and 3 kW similarly shows a decrease of about 11% and 9% respectively. While keeping the H2gas flow rate constant and decreasing the source power also shows a decrease in n-value, the magnitude of the decrease is not as pronounced as compared to adjusting the H2gas flow rate and keeping the source power constant. For example, line414shows that keeping the H2gas flow rate at a constant 10 sccm while reducing the source power from 3 kW to 1.25 kw only reduces the k-value of the amorphous silicon layer by about 8 percent. A person of ordinary skill in the art will recognize that a specific n-value can be obtained through routine experimentation to determine the proper H2gas flow rate and source power combination.

Reducing the optical properties (i.e. the n-value and k-value) of the amorphous silicon layer increases the transparency (i.e. the optical property of allowing light to pass through material without scattering) of the amorphous silicon layer, which is beneficial for subsequent lithographic, alignment, and overlay processes. The inventors have also observed that the method200can tune or adjust other film properties of the amorphous silicon layer, such as film stress, film morphology (i.e. film crystallinity) and film surface properties (i.e. physical surface properties such as surface roughness and chemical surface properties such as tuning surface bonding sites). For example, the stress of the deposited amorphous silicon layer can be reduced (i.e. brought closer to neutral by depositing the deposited amorphous silicon layer at a process temperature of between about 350 and 400 degrees Celsius.

General processing conditions for depositing the amorphous silicon layer includes maintaining process chamber pressure at about 3 millitorr to about 10 millitorr and maintaining process chamber temperature at about 25 to about 400 degrees Celsius.

In some embodiments, following deposition of the amorphous silicon layer302via the method200described above, the substrate can undergo further processing, for example a self-aligned double patterning (SADP) process. The self-aligned double patterning (SADP) process described herein is chosen for illustration purpose. The concept of the disclosure is equally applicable to other processes, single or dual patterning scheme, such as via/hole shrink process, self-aligned triple patterning (SATP) process, or self-aligned quadruple patterning (SAQP) process, etc. that may use an amorphous silicon layer in patterning processes in various semiconductor processes such as NAND flash application, DRAM application, or CMOS application.

In some embodiments, as depicted inFIG. 3C, a patterned mask layer306is formed atop the amorphous silicon layer302. In some embodiments, the patterned mask layer306may be a hard mask layer. The patterned mask layer306may comprise any materials suitable to provide a template to facilitate etching features into the underlying amorphous silicon layer302. For example, in embodiments where the patterned mask layer306is a hard mask, the patterned mask layer306may comprise at least one of oxides, such as silicon dioxide (SiO2), silicon oxynitride (SiON), silicon oxycarbide (SiOC) or the like, or nitrides, such as titanium nitride (TiN), silicon nitride (SiN), or the like, silicides, such as titanium silicide (TiSi), nickel silicide (NiSi) or the like, or silicates, such as aluminum silicate (AlSiO), zirconium silicate (ZrSiO), hafnium silicate (HfSiO), or the like. In some embodiments, patterned mask layer306is a hard mask comprising one or more metal oxides such as tantalum oxide (TaOx), tin oxide (SnOx), tin silicon oxide (SnSiOx), or the like. In some embodiments, the patterned mask layer306may comprise an amorphous carbon, such as Advanced Patterning Film (APF), available from Applied Materials, Inc., located in Santa Clara, Calif., or a tri-layer resist (e.g., a photoresist layer, a Si-rich anti-reflective coating (ARC) layer, and a carbon-rich ARC, or bottom ARC (BARC) layer), a dielectric antireflective coating (DARC), or the like, a spin-on hard mask (SOH), or the like.

Patterned features310formed from the amorphous silicon layer302are produced on the first layer300using standard photo-lithography and etching techniques, as shown inFIG. 3D. The patterned features310are sometimes referred to as placeholders, mandrels or cores and have specific line widths and/or spacing based upon the hard mask material used. After the pattern has been transferred into the amorphous silicon layer302, any residual photoresist and hard mask material are removed using a suitable photoresist stripping process.

As shown inFIG. 3E, a conformal layer of hard mask material308such as silicon oxide or silicon nitride is subsequently deposited over the patterned amorphous silicon302mandrels. As shown inFIG. 3F, hard mask spacers312are then formed on the sides of the patterned amorphous silicon302mandrels by preferentially etching the hard mask material308from horizontal surfaces with an anisotropic plasma etch to open the hard mask material308deposited on top of the patterned amorphous silicon302mandrels as well as remove the hard mask material308deposited at the bottom between the two sidewalls of the patterned amorphous silicon302mandrels. As shown inFIG. 3G, the patterned amorphous silicon302mandrels may then be removed, leaving behind hard mask spacers312. As shown inFIG. 3H, the hard mask spacers312may be used as an etch mask for transferring the pattern to the first layer300. The hard mask spacers312are subsequently removed as shown inFIG. 3I. Therefore, the density of the pattern formed in the first layer300is twice that of the photo-lithographically patterned amorphous silicon302mandrels, and the pitch of the pattern formed in the first layer300is half the pitch of the photo-lithographically patterned amorphous silicon302mandrels.

The method200is described above with respect to an amorphous silicon layer. However, the method200can also be used to deposit materials other than amorphous silicon, such as carbon, metal oxide, aluminum oxide (AlOx), aluminum nitride (AlN), aluminum oxynitride (AlON) silicon dioxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), silicon oxycarbide (SiOC) or titanium nitride (TiN). Non-limiting examples of suitable metal oxides for deposition include tantalum oxide (TaOx), tin oxide (SnOx), tin silicon oxide (SnSiOx), and combinations thereof. Further, a plasma from a process gas can be formed within a processing region of the physical vapor deposition chamber. The process gas comprises an inert gas and a hydrogen-containing gas to sputter source material from a surface of a target within the processing region of the physical vapor deposition chamber. The process gas can also comprise oxygen and/or nitrogen depending on the material to be deposited. However, similar to the amorphous silicon layer described above, tuning or adjusting the flow rate of the hydrogen containing gas allows for tuning the optical properties, stress, film morphology and surface properties of the particular deposited material.

FIG. 5depicts a flow chart of a method500for depositing a silicon oxycarbide (SiOC) layer atop a substrate disposed in a physical vapor deposition process system of the type described inFIG. 1. Examples of PVD chambers suitable for performing the method200described herein include the CIRRUS™, AVENIR™ and IMPULSE PVD processing chambers, commercially available from Applied Materials, Inc., of Santa Clara, Calif.

The method may be performed on an exemplary substrate108disposed within the process chamber104. The substrate108may be any suitable substrate having any suitable geometry, such as a round wafer, square, rectangular, or the like. The substrate108may comprise any suitable materials, such as one or more of silicon (Si), silicon oxide (SiO2), silicon nitride (SiN), glass, other dielectric materials, or the like. In some embodiments, the substrate108may be a semiconductor wafer (e.g., a 200 mm, 300 mm, or the like silicon wafer). In some embodiments, the substrate108may include additional layers, for example a dielectric layer. In some embodiments, the substrate may be a partially fabricated semiconductor device such as Logic, DRAM, or a Flash memory device. In addition, features, such as trenches, vias, or the like, may be formed in one or more layers of the substrate108.

The method500begins at502by forming a plasma from a process gas within a processing region of the physical vapor deposition chamber. The process gas comprises an inert gas and a carbon monoxide (CO) gas or carbon dioxide (CO2) gas. In some embodiments, the process gas consists of, or consists essentially of, an inert gas and a carbon monoxide (CO) gas or carbon dioxide (CO2) gas. In some embodiments, the inert gas is a noble gas such as argon, helium, neon or xenon.

In some embodiments, the process gas comprises inert gas, a carbon monoxide (CO) gas or carbon dioxide (CO2) gas, and oxygen (O2) gas. In some embodiments, the process gas consists of, or consists essentially of, an inert gas, a carbon monoxide (CO) gas or carbon dioxide (CO2) gas, and oxygen (O2) gas. The flow rate of the oxygen (O2) gas in relation to the flow rate of the carbon monoxide (CO) gas or carbon dioxide (CO2) gas tunes or adjusts the optical properties (n-value and k-value) of the silicon oxycarbide (SiOC) layer. In addition, as discussed below the application of bias power in conjunction with the flow rate of oxygen (O2) gas impacts film stress.

The process gas may be formed into a plasma by coupling sufficient energy from a power source to ignite the process gas described above to form the plasma. The power source may be operable in a continuous wave (CW) or pulsed mode. The power source may include direct current (DC), pulsed DC, or radio frequency (RF) power. In some embodiments, the power source may illustratively provide RF power at about 500 W to about 6 kW of power, for example about 2 kW, at a suitable frequency, such as about 13.56 MHz to form the plasma. In some embodiments, the power source may provide pulsed DC power at a pulse frequency of about 100 to about 250 kHz and at a duty cycle (e.g., the percentage of on time during the total of on time and off time in a given cycle) of about 10% to about 40%.

The inert gas is provided to the processing region120of the process chamber104at a flow rate of about 10 sccm to about 200 sccm. The carbon monoxide (CO) gas or carbon dioxide (CO2) gas is provided to the processing region120of the process chamber104at a flow rate of about 10 to about 200 sccm. The oxygen (O2) gas is provided to the processing region120of the process chamber104at a flow rate of about 0 to about 200 sccm. The ratio of the flow rate of inert gas to the flow rate of the carbon monoxide (CO) gas or carbon dioxide (CO2) gas is 1:1. The ratio of the flow rate of the carbon monoxide (CO) gas or carbon dioxide (CO2) gas to the oxygen (O2) gas is 1:0 to 1:1.

In some embodiments, a bias power may be applied to the substrate108to facilitate directing ions from the plasma towards the substrate108and reducing surface roughness of the silicon oxycarbide (SiOC) layer from about 10 angstroms without bias to less than about 2 angstroms with bias. For example, in some embodiments, the bias power may be about 100 to about 1000 watts.FIG. 6shows a graph600of the film stress for a film formed with bias and without bias at varying oxygen (O2) flow rates. At low oxygen (O2) flow rates of 20 sccm (labeled O2-2on the graph600) and 30 sccm (labeled O2-3on the graph600), there is a significant difference in film stress for films formed with and without bias. However, higher oxygen (O2) flow rates of 30 sccm to 60 sccm show minor impact of bias on film stress.FIG. 1, shows a bias power source134, which may be an RF bias power source coupled to the substrate support106in order to form the plasma within the processing region120.

Next at504, the silicon oxycarbide (SiOC) layer is deposited atop the substrate108. In some embodiments, the silicon oxycarbide (SiOC) layer is formed atop one or more additional layers atop the substrate108. In some embodiments, the silicon oxycarbide (SiOC) layer is deposited to a thickness suitable for patterning processes in various semiconductor processes. For example, the silicon oxycarbide (SiOC) layer can be deposited to a thickness of about 50 to about 500 angstroms.

The pressure within the processing region120of the process chamber104during deposition of the silicon oxycarbide (SiOC) layer is about 3 milliTorr to about 20 milliTorr. The temperature within the processing region120of the process chamber104during deposition of the silicon oxycarbide (SiOC) layer is about 25 to about 375 degrees Celsius. By adjusting the temperature and pressure within the processing region120the inventors have observed that the density of the deposited silicon oxycarbide (SiOC) layer can be tuned between 1.67 and 2.3 g/cm3. The inventors have observed that increasing the pressure within the processing region120decreases the density of the deposited silicon oxycarbide (SiOC) layer while increasing the temperature within the processing region120increases the density of the deposited silicon oxycarbide (SiOC) layer. The density of the deposited silicon oxycarbide (SiOC) layer impacts the etch rate of the silicon oxycarbide (SiOC) layer. A lower etch rate equates to a higher etch selectivity and a higher etch rate equates to a lower etch selectivity.

FIG. 7shows graph700, wherein a silicon oxycarbide (SiOC) layer is deposited at room temperature (RT), e.g. 25 degrees Celsius, at 120 degrees Celsius, and at 200 degrees Celsius and at a carbon monoxide gas flow rate of 20 sccm (SiOC-20), 40 sccm (SiOC-40), 70 sccm (SiOC-70), and 100 sccm (SiOC-100). The graph700also shows that at a constant carbon monoxide gas flow rate the density of the deposited silicon oxycarbide (SiOC) layer decreases as the temperature increases.

In addition to tuning the density of the deposited silicon oxycarbide (SiOC) layer, the inventors have observed that the optical properties of the silicon oxycarbide (SiOC) layer can be tuned to provide optical properties similar to an Si-ARC layer by adjusting the flow rate of carbon monoxide (CO) gas to the flow rate of oxygen (O2) gas. The n-value and k-value of a Si-ARC layer is 1.72 and 0.25 respectively. Table 1 shows how the flow rate of carbon monoxide (CO) gas relative to the flow rate of oxygen (O2) gas impacts the n-value and k-value of the silicon oxycarbide (SiOC) layer. For example, row 2 shows that a silicon oxycarbide (SiOC) layer formed with a flow rate of 40 sccm of carbon monoxide (CO) gas relative to 20 sccm of oxygen (O2) gas has a n-value of 1.86 and a k-value of 0.647. As shown in row 2 of Table 1, increasing the flow rate of the oxygen (O2) gas relative to the carbon monoxide (CO) gas decreases the n-value and k-value of the silicon oxycarbide (SiOC) layer, and can provide optical properties similar to the Si-ARC layer. The silicon oxycarbide (SiOC) layer discussed in table 1 was formed at 50 degrees Celsius, with 3 kW of source power, 200 watts of bias power, gate open (GO) pressure and 40 sccm of argon.

The silicon oxycarbide (SiOC) layer described in method500above advantageously replaces a Si-ARC layer as part of a multi-layer resist, while having similar optical properties and a tunable density and without leave particle residue on underlying layer upon removal. In some embodiments, following formation of the silicon oxycarbide (SiOC) layer, a photoresist layer is formed atop the silicon oxycarbide (SiOC) layer. The photoresist layer and the silicon oxycarbide (SiOC) layer form a multi-layer resist suitable for etching a pattern into any suitable semiconductor manufacturing process material layer underlying the multi-layer resist.

The method500is described above with respect to an silicon oxycarbide (SiOC) layer. However, the method500can also be used to deposit materials other than silicon oxycarbide (SiOC) layer, such as aluminum oxynitride (AlON) or aluminum oxycarbon nitride (AlONC) with similar density and optical property tunability.

Returning toFIG. 1, a second energy source183, optionally coupled to the target assembly114, may provide DC power to the target assembly114to direct the plasma towards the target assembly114. In some embodiments, the DC power may range from about 200 W to about 20 kilowatts (kW), although the amount of DC power applied may vary depending upon chamber geometry (e.g., target size or the like). In some embodiments, the DC power may also be adjusted over the life of the target in the same manner as described above for the RF power. The DC power may be adjusted to control the deposition rate of sputtered metal atoms on the substrate. For example, increasing the DC power can result in increased interaction of the plasma with the source material113and increased sputtering of metal atoms from the target assembly114.

The PVD processing system100includes a chamber lid102removably disposed atop a process chamber104. The chamber lid102may include the target assembly114and a grounding assembly103. The process chamber104contains a substrate support106for receiving a substrate108. The substrate support106may be located within a lower grounded enclosure wall110, which may be a chamber wall of the process chamber104. The lower grounded enclosure wall110may be electrically coupled to the grounding assembly103of the chamber lid102such that an RF return path is provided to an RF power source182disposed above the chamber lid102. The RF power source182may provide RF energy to the target assembly114as discussed below. Alternatively or in combination a DC power source may be similarly coupled to target assembly114.

The PVD processing system100may include a source distribution plate158opposing a backside of the target assembly114and electrically coupled to the target assembly114along a peripheral edge of the target assembly114. The PVD processing system100may include a cavity170disposed between the backside of the target assembly114and the source distribution plate158. The cavity170may at least partially house a magnetron assembly196as discussed below. The cavity170is at least partially defined by the inner surface of a conductive support ring164, a target facing surface of the source distribution plate158, and a source distribution plate facing surface (e.g., backside) of the target assembly114(or backing plate assembly160).

The PVD processing system100further includes a magnetron assembly. The magnetron assembly provides a rotating magnetic field proximate the target assembly114to assist in plasma processing within the process chamber104. The magnetron assembly includes a rotatable magnet assembly148disposed within the cavity170. The rotatable magnet assembly148rotates about a central axis186of the process chamber104.

In some embodiments, the magnetron assembly includes a motor176, a motor shaft174, a gear assembly178, and the rotatable magnet assembly148. The rotatable magnet assembly148includes a plurality of magnets150and is configured to rotate the plurality of magnets150about the central axis186as described below. The motor176may be an electric motor, a pneumatic or hydraulic drive, or any other process-compatible mechanism that can provide suitable torque. While one illustrative embodiment is described herein to illustrate how the rotatable magnet assembly148may be rotated, other configurations may also be used.

In use, the magnetron assembly rotates the rotatable magnet assembly148within the cavity170. For example, in some embodiments, the motor176, motor shaft174, and gear assembly178may be provided to rotate the rotatable magnet assembly148. In some embodiments, the electrode154is aligned with the central axis186of the process chamber104, and motor shaft174of the magnetron may be disposed through an off-center opening in the ground plate156. The end of the motor shaft174protruding from the ground plate156is coupled to the motor176. The motor shaft174is further disposed through an off-center opening in the source distribution plate158and coupled to a gear assembly178.

The gear assembly178may be supported by any suitable means, such as by being coupled to a bottom surface of the source distribution plate158. The gear assembly178may be insulated from the source distribution plate158by fabricating at least the upper surface of the gear assembly178from a dielectric material, or by interposing an insulator layer (not shown) between the gear assembly178and the source distribution plate158, or the like, or by constructing the motor shaft174out of suitable dielectric material. The gear assembly178is further coupled to the rotatable magnet assembly148to transfer the rotational motion provided by the motor176to the rotatable magnet assembly148. The gear assembly178may be coupled to the rotatable magnet assembly148through the use of pulleys, gears, or other suitable means of transferring the rotational motion provided by the motor176.

The substrate support106has a material-receiving surface facing a principal surface of a target assembly114and supports the substrate108to be sputter coated in planar position opposite to the principal surface of the target assembly114. The substrate support106may support the substrate108in a processing region120of the process chamber104. The processing region120is defined as the region above the substrate support106during processing (for example, between the target assembly114and the substrate support106when in a processing position).

In some embodiments, the substrate support106may be vertically movable to allow the substrate108to be transferred onto the substrate support106through a load lock valve (not shown) in the lower portion of the process chamber104and thereafter raised to a deposition, or processing position. A bellows122connected to a bottom chamber wall124may be provided to maintain a separation of the inner volume of the process chamber104from the atmosphere outside of the process chamber104while facilitating vertical movement of the substrate support106. One or more gases may be supplied from a gas source126through a mass flow controller128into the lower part of the process chamber104.

The gas source126may be a gas box providing the gases used in the methods described above via one or more gas lines coupled to the process chamber104. For example, a first gas line may be provided from the gas source126to the process chamber104to provide hydrogen (H2) to the process chamber104. A second gas line may be provided from the gas source126to the process chamber104to provide one or more of oxygen (O2), nitrogen (N2), carbon monoxide (CO) or argon (Ar) to the process chamber104. A third gas line may be provided from the gas source126to the process chamber104to provide a backside gas (such as a mixture of argon and hydrogen or other suitable backside gas) to the substrate support106.

An exhaust port130may be provided and coupled to a pump (not shown) via a valve132for exhausting the interior of the process chamber104and to facilitate maintaining a suitable pressure inside the process chamber104.

The process chamber104further includes a process kit shield, or shield,138to surround the processing volume, or central region, of the process chamber104and to protect other chamber components from damage and/or contamination from processing. In some embodiments, the shield138may be connected to a ledge140of an upper grounded enclosure wall116of the process chamber104. As illustrated inFIG. 1, the chamber lid102may rest on the ledge140of the upper grounded enclosure wall116. Similar to the lower grounded enclosure wall110, the upper grounded enclosure wall116may provide a portion of the RF return path between the lower grounded enclosure wall116and the grounding assembly103of the chamber lid102. However, other RF return paths are possible, such as via the grounded shield138.

The shield138extends downwardly and may include a generally tubular portion having a generally constant diameter that generally surrounds the processing region120. The shield138extends along the walls of the upper grounded enclosure wall116and the lower grounded enclosure wall110downwardly to below a top surface of the substrate support106and returns upwardly until reaching a top surface of the substrate support106(e.g., forming a u-shaped portion at the bottom of the shield138). A cover ring146rests on the top of an upwardly extending inner portion of the shield138when the substrate support106is in the lower, loading position but rests on the outer periphery of the substrate support106when the substrate support is in the upper, deposition position to protect the substrate support106from sputter deposition. An additional deposition ring (not shown) may be used to protect the edges of the substrate support106from deposition around the edge of the substrate108.

In some embodiments, a magnet152may be disposed about the process chamber104for selectively providing a magnetic field between the substrate support106and the target assembly114. For example, as shown inFIG. 1, the magnet152may be disposed about the outside of the enclosure wall110in a region just above the substrate support106when in processing position. In some embodiments, the magnet152may be disposed additionally or alternatively in other locations, such as adjacent the upper grounded enclosure wall116. The magnet152may be an electromagnet and may be coupled to a power source (not shown) for controlling the magnitude of the magnetic field generated by the electromagnet.

The chamber lid102generally includes the grounding assembly103disposed about the target assembly114. The grounding assembly103may include a grounding plate156having a first surface157that may be generally parallel to and opposite a backside of the target assembly114. A grounding shield112may extending from the first surface157of the grounding plate156and surround the target assembly114. The grounding assembly103may include a support member175to support the target assembly114within the grounding assembly103.

In some embodiments, the support member175may be coupled to a lower end of the grounding shield112proximate an outer peripheral edge of the support member175and extends radially inward to support a seal ring181, and the target assembly114. The seal ring181may be a ring or other annular shape having a suitable cross-section. The seal ring181may include two opposing planar and generally parallel surfaces to facilitate interfacing with the target assembly114, such as the backing plate assembly160, on a first side of the seal ring181and with the support member175on a second side of the seal ring181. The seal ring181may be made of a dielectric material, such as ceramic. The seal ring181may insulate the target assembly114from the ground assembly103.

The support member175may be a generally planar member having a central opening to accommodate the target assembly114. In some embodiments, the support member175may be circular, or disc-like in shape, although the shape may vary depending upon the corresponding shape of the chamber lid and/or the shape of the substrate to be processed in the PVD processing system100.

The target assembly114may comprise a source material113, such as a metal, metal oxide, metal alloy, or the like, to be deposited on a substrate, such as the substrate108during sputtering. In some embodiments, the target assembly114may be fabricated substantially from the source material113, without any backing plate to support the source material113. In some embodiments, the target assembly114includes a backing plate assembly160to support the source material113. The source material113may be disposed on a substrate support facing side of the backing plate assembly160as illustrated inFIG. 1. The backing plate assembly160may comprise a conductive material, such as copper-zinc, copper-chrome, or the same material as the target, such that RF and DC power can be coupled to the source material113via the backing plate assembly160. Alternatively, the backing plate assembly160may be non-conductive and may include conductive elements (not shown) such as electrical feedthroughs or the like.

In some embodiments, the backing plate assembly160includes a first backing plate161and a second backing plate162. The first backing plate161and the second backing plate162may be disc shaped, rectangular, square, or any other shape that may be accommodated by the PVD processing system100. A front side of the first backing plate161is configured to support the source material113such that a front surface of the source material opposes the substrate108when present. The source material113may be coupled to the first backing plate161in any suitable manner. For example, in some embodiments, the source material113may be diffusion bonded to the first backing plate161.

A plurality of sets of channels169may be disposed between the first and second backing plates161,162. The first and second backing plates161,162may be coupled together to form a substantially water tight seal (e.g., a fluid seal between the first and second backing plates) to prevent leakage of coolant provided to the plurality of sets of channels169. In some embodiments, the target assembly114may further comprise a central support member192to support the target assembly114within the process chamber104.

In some embodiments, the conductive support ring164may be disposed between the source distribution plate158and the backside of the target assembly114to propagate RF energy from the source distribution plate to the peripheral edge of the target assembly114. The conductive support ring164may be cylindrical, with a first end166coupled to a target-facing surface of the source distribution plate158proximate the peripheral edge of the source distribution plate158and a second end168coupled to a source distribution plate-facing surface of the target assembly114proximate the peripheral edge of the target assembly114. In some embodiments, the second end168is coupled to a source distribution plate facing surface of the backing plate assembly160proximate the peripheral edge of the backing plate assembly160.

An insulative gap180is provided between the grounding plate156and the outer surfaces of the source distribution plate158, the conductive support ring164, and the target assembly114(and/or backing plate assembly160). The insulative gap180may be filled with air or some other suitable dielectric material, such as a ceramic, a plastic, or the like. The distance between the grounding plate156and the source distribution plate158depends on the dielectric material between the grounding plate156and the source distribution plate158. Where the dielectric material is predominantly air, the distance between the grounding plate156and the source distribution plate158may be between about 15 mm and about 40 mm.

The grounding assembly103and the target assembly114may be electrically separated by the seal ring181and by one or more of insulators (not shown) disposed between the first surface157of the grounding plate156and the backside of the target assembly114, e.g., a non-target facing side of the source distribution plate158.

The PVD processing system100has an RF power source182connected to an electrode154(e.g., a RF feed structure). The electrode154may pass through the grounding plate156and is coupled to the source distribution plate158. The RF power source182may include an RF generator and a matching circuit, for example, to minimize reflected RF energy reflected back to the RF generator during operation. For example, RF energy supplied by the RF power source182may range in frequency from about 13.56 MHz to about 162 MHz or above. For example, non-limiting frequencies such as 13.56 MHz, 27.12 MHz, 40.68 MHz, 60 MHz, or 162 MHz can be used.

In some embodiments, PVD processing system100may include a second energy source183to provide additional energy to the target assembly114during processing. In some embodiments, the second energy source183may be a DC power source or a pulsed DC power source to provide DC energy, for example, to enhance a sputtering rate of the target material (and hence, a deposition rate on the substrate). In some embodiments, the second energy source183may be a second RF power source, similar to the RF power source182, to provide RF energy, for example, at a second frequency different than a first frequency of RF energy provided by the RF power source182. In embodiments where the second energy source183is a DC power source, the second energy source may be coupled to the target assembly114in any location suitable to electrically couple the DC energy to the target assembly114, such as the electrode154or some other conductive member (such as the source distribution plate158, discussed below). In embodiments where the second energy source183is a second RF power source, the second energy source may be coupled to the target assembly114via the electrode154.

The electrode154may be cylindrical or otherwise rod-like and may be aligned with a central axis186of the process chamber104(e.g., the electrode154may be coupled to the target assembly at a point coincident with a central axis of the target, which is coincident with the central axis186). The electrode154, aligned with the central axis186of the process chamber104, facilitates applying RF energy from the RF power source182to the target assembly114in an axisymmetrical manner (e.g., the electrode154may couple RF energy to the target at a “single point” aligned with the central axis of the PVD chamber). The central position of the electrode154helps to eliminate or reduce deposition asymmetry in substrate deposition processes. The electrode154may have any suitable diameter. For example, although other diameters may be used, in some embodiments, the diameter of the electrode154may be about 0.5 to about 2 inches. The electrode154may generally have any suitable length depending upon the configuration of the PVD chamber. In some embodiments, the electrode may have a length of between about 0.5 to about 12 inches. The electrode154may be fabricated from any suitable conductive material, such as aluminum, copper, silver, or the like. Alternatively, in some embodiments, the electrode154may be tubular. In some embodiments, the diameter of the tubular electrode154may be suitable, for example, to facilitate providing a central shaft for the magnetron.

The electrode154may pass through the ground plate156and is coupled to the source distribution plate158. The ground plate156may comprise any suitable conductive material, such as aluminum, copper, or the like. The open spaces between the one or more insulators (not shown) allow for RF wave propagation along the surface of the source distribution plate158. In some embodiments, the one or more insulators may be symmetrically positioned with respect to the central axis186of the PVD processing system. Such positioning may facilitate symmetric RF wave propagation along the surface of the source distribution plate158and, ultimately, to a target assembly114coupled to the source distribution plate158. The RF energy may be provided in a more symmetric and uniform manner as compared to conventional PVD chambers due, at least in part, to the central position of the electrode154.

The PVD processing system100further comprises a substrate support impedance circuit, such as auto capacitance tuner136, coupled to the substrate support106for adjusting voltage on the substrate108. For example, the auto capacitance tuner136may be used to control the voltage on the substrate108, and thus, the substrate current (e.g., ion energy at the substrate level).

A controller194may be provided and coupled to various components of the PVD processing system100to control the operation thereof. The controller194includes a central processing unit (CPU)118, a memory172, and support circuits173. The controller194may control the PVD processing system100directly, or via computers (or controllers) associated with particular process chamber and/or support system components. The controller194may be one of any form of general-purpose computer processor that can be used in an industrial setting for controlling various chambers and sub-processors. The memory, or computer readable medium,172of the controller194may be one or more of readily available memory such as random access memory (RAM), read only memory (ROM), floppy disk, hard disk, optical storage media (e.g., compact disc or digital video disc), flash drive, or any other form of digital storage, local or remote. The support circuits173are coupled to the CPU118for supporting the processor in a conventional manner. These circuits include cache, power supplies, clock circuits, input/output circuitry and subsystems, and the like. Inventive methods as described herein, such as the method200, may be stored in the memory264as software routine that may be executed or invoked to control the operation of the PVD processing system100in the manner described herein. The software routine may also be stored and/or executed by a second CPU (not shown) that is remotely located from the hardware being controlled by the CPU118.

While the foregoing is directed to particular embodiments of the present disclosure, other and further embodiments of the disclosure may be devised without departing from the basic scope of the disclosure.