Electronic device and method for fabricating the same

An electronic device includes a semiconductor memory. A method for fabricating the electronic device includes forming a first memory cell extending vertically from a surface of substrate and having a first upper portion that protrudes laterally, forming a second memory cell extending vertically from the surface of the substrate and having a second upper portion that protrudes laterally towards the first upper portion, and forming a liner layer over the first and second memory cells, the liner layer having a first portion disposed over the first upper portion and a second portion disposed over the second upper portion, the first and second portions of the liner layer contacting each other.

CROSS-REFERENCE TO RELATED APPLICATIONS

The present application claims priority of Korean Patent Application No. 10-2019-0025229, entitled “ELECTRONIC DEVICE AND METHOD FOR FABRICATING THE SAME” and filed on Mar. 5, 2019, which is incorporated herein by reference in its entirety.

TECHNICAL FIELD

This patent document relates to memory circuits or devices and their applications in electronic devices or systems.

BACKGROUND

Recently, as electronic appliances trend toward miniaturization, low power consumption, high performance, multi-functionality, and so on, semiconductor devices capable of storing information in various electronic appliances such as computers, portable communication devices, and so on have been demanded. Such semiconductor devices include semiconductor devices that can store data by switching between different resistant states according to an applied voltage or current. Such semiconductor devices include, for example, RRAM (resistive random access memory), PRAM (phase change random access memory), FRAM (ferroelectric random access memory), MRAM (magnetic random access memory), E-fuse, etc.

SUMMARY

The present disclosure describes memory circuits and memory devices, and applications for memory circuits and memory devices in electronic devices or systems. The present disclosure further describes various implementations of an electronic device and a which can improve operating characteristics, facilitate fabricating processes, and reduce defects in the fabricating processes.

In an implementation, an electronic device may include a semiconductor memory, wherein the semiconductor memory may include: a first memory cell extending vertically from a surface of substrate and having a first upper portion that protrudes laterally; a second memory cell extending vertically from the surface of the substrate having a second upper portion that protrudes laterally towards the first upper portion; and a liner layer disposed along a profile of the first and second memory cells, the liner layer having a first portion disposed over the first upper portion and a second portion disposed over the second upper portion, the first and second portions of the liner layer contacting each other.

In another implementation, a method for fabricating an electronic device including a semiconductor memory may include: forming a first memory cell extending vertically from a surface of substrate and having a first upper portion that protrudes laterally; forming a second memory cell extending vertically from the surface of the substrate and having a second upper portion that protrudes laterally towards the first upper portion; and forming a liner layer over the first and second memory cells, the liner layer having a first portion disposed over the first upper portion and a second portion disposed over the second upper portion, the first and second portions of the liner layer contacting each other.

These and other aspects, implementations and associated advantages are described in greater detail in the drawings, the description and the claims.

DETAILED DESCRIPTION

Various examples and implementations of the disclosed technology are described below in detail with reference to the accompanying drawings.

FIG. 1is a cross-sectional view of a memory device in accordance with a comparative example.

Referring toFIG. 1, the memory device may include a plurality of memory cells MC formed over a substrate SUB.

Each of the memory cells MC may have a stacked structure of a bottom electrode BE, a variable resistance layer VR, and a top electrode TE.

The variable resistance layer VR may switch between different resistance states according to a voltage or current applied thereto through the bottom electrode BE and the top electrode TE, thereby storing data.

Here, the variable resistance layer VR may include a phase change material. The phase change material may switch between an amorphous state and a crystalline state according to Joule's heat generated by an amount of current flowing thereto through the bottom electrode BE and the top electrode TE, and a cooling time. When the phase change material is in the amorphous state, the phase change material may be in a relatively high resistance state. On the other hand, when the phase change material is in the crystalline state, the phase change material may be in a relatively low resistance state. The variable resistance layer VR may store data using such a resistance difference of the phase change material.

An operation in which the phase change material is changed from the amorphous state to the crystalline state may be referred to as a set operation, and a current required to perform the set operation may be referred to as a set current. Also, an operation in which the phase change material is changed from the crystalline state to the amorphous state may be referred to as a reset operation, and a current required to perform the reset operation may be referred to as a reset current.

When a current is applied to the phase change material and thus a temperature of the phase change material reaches a melting point, the phase change material changes from the crystalline state to the amorphous state. On the other hand, when the current is applied to the phase change material and thus the temperature of the phase change material reaches a crystallization temperature, the phase change material changes from the amorphous state to the crystalline state, the crystallization temperature being lower than the melting point. Therefore, the reset current required for changing the crystalline state to the amorphous state is greater than the set current required for changing the amorphous state to the crystalline state.

However, the heat generated for changing the resistance state of the phase change material may be lost through surroundings, for example, through an insulating material (not shown) filled in spaces between the memory cells MC, so only a portion of the generated heat may be used to change the resistance state of the phase change material. Such heat loss may increase a level of the set current and a level of the reset current to change the resistance state of the phase change material. Particularly, since it is necessary for the temperature of the phase change material to be largely increased in the reset operation, the increase of the reset current may become more problematic.

In addition, when such heat is transmitted to the surroundings, it may cause a thermal disturbance phenomenon that affects a phase change material of the adjacent memory cell MC. The thermal disturbance phenomenon may be further intensified as a memory device becomes highly integrated and thus a distance between memory cells MC becomes closer. Errors may occur in an operation of the memory device due to the thermal disturbance phenomenon and a reliability of the memory device may be deteriorated accordingly.

Hereinafter, there will be introduced a memory device and its manufacturing method, which can solve the above drawbacks by reducing heat loss and/or heat transfer to the surroundings in the memory device.

FIGS. 2A to 6Bare views for describing a method of manufacturing a memory device in accordance with an implementation of the present disclosure.FIGS. 2A, 3A, 4A, 5A, and 6Aare plan views;FIGS. 2B, 3B, 4B, 5B, and 6Bare cross-sectional views taken along a line A-A′ ofFIGS. 2A, 3A, 4A, 5A, and 6A, respectively; andFIGS. 4C and 5C, are cross-sectional views taken along a line B-B′ ofFIGS. 4A and 5A, respectively.

Referring toFIGS. 2A and 2B, a substrate100in which a required lower structure (not shown) is formed may be provided. For example, the lower structure may include a line such as a word line that is coupled to a lower end of a memory cell so that the word line supplies a voltage or current to the memory cell.

Then, a lower electrode layer110, a selection element layer120, an intermediate electrode layer130, a variable resistance layer140, and an upper electrode layer150may be sequentially stacked over the substrate100.

The lower electrode layer110may be disposed at the lowermost portion of the memory cell to provide a connection between the memory cell and a portion of the substrate100, for example, the word line. The lower electrode layer110may have a single-layered structure or a multi-layered structure including a low-resistance conductive material such as a metal or a metal nitride.

The selection element layer120may have a threshold switching characteristic. A current flowing through the selection element layer120may be blocked or hardly allowed when a magnitude of a voltage supplied to upper and lower ends of the selection element layer120is less than a predetermined threshold voltage. The current flowing through the selection element layer120may abruptly increase when the magnitude of the voltage exceeds the threshold voltage Therefore, the threshold switching characteristic of the selection element layer120is used to control access to the variable resistance layer140.

The selection element layer120may include a diode, an OTS (Ovonic Threshold Switching) material such as a chalcogenide material, an MIEC (Mixed Ionic Electronic Conducting) material such as a metal containing chalcogenide material, an MIT (Metal Insulator Transition) material such as NbO2, VO2, or the like, or a tunneling insulating material having a relatively wide band gap such as SiO2, Al2O3, or the like.

The Intermediate electrode layer130may physically separate the selection element layer120and the variable resistance layer140, and electrically connect the selection element layer120and the variable resistance layer140. The intermediate electrode layer130may have a single-layered structure or a multi-layered structure including a low-resistance conductive material such as a metal or a metal nitride.

The variable resistance layer140may have a variable resistance characteristic that switches between different resistance states depending on a voltage or current supplied to upper and lower ends of the variable resistance layer140, thereby storing different data corresponding to the different resistance states, respectively. The variable resistance layer140may have a single-layered structure exhibiting the variable resistance characteristic by a single layer or a multi-layered structure exhibiting the variable resistance characteristic by a combination of two or more layers.

For example, the variable resistance layer140may include a phase change material capable of switching between an amorphous state and a crystalline state by Joule's heat generated according to a current flowing through the variable resistance layer140. However, implementations are not limited thereto. In another implementation, the variable resistance layer140may have a single-layered structure or a multi-layered structure including one or more of materials used for an RRAM, a PRAM, an MRAM, an FRAM, or the like. The materials may include a metal oxide such as a perovskite-based oxide, a transition metal oxide, or the like, a phase change material such as a chalcogenide-based material, a ferromagnetic material, a ferroelectric material, and the like.

The present implementation may be applied to any case where it is necessary to prevent heat loss from a memory cell or heat transfer between adjacent memory cells.

The upper electrode layer150may be disposed at the uppermost portion of the memory cell to provide a connection between the memory cell and a conductive element over the memory cell, such as a bit line. The upper electrode layer150may include a single-layered structure or a multi-layered structure including a low resistance conductive material such as a metal or a metal nitride.

Then, the upper electrode layer150may be selectively etched to form an upper electrode150A of each memory cell. In a plan view, the upper electrode150A may have an island shape so that the upper electrodes150A of a plurality of memory cells may be arranged separately from each other. For convenience of explanation,FIG. 2Ashows four upper electrodes150A that are arranged in a matrix form along a first direction parallel to the A-A′ line and a second direction substantially perpendicular to the first direction. However, implementations are not limited thereto. In another implementation, the number and arrangement of the upper electrodes150A may be variously modified.

In addition, inFIG. 2A, although the upper electrode150A has a rectangular shape in a plan view, the upper electrode150A may have a shape that is different from the rectangular shape. For example, the upper electrode150A may have a shape of a circle, an ellipse, or the like.

In a cross-sectional view, the upper electrode150A may have a sidewall having an inclined shape such that a side surface thereof forms an acute angle with a surface of the substrate100. Accordingly, a width of the upper electrode150A may sharply increase from top to bottom. In an implementation, when a width at an upper portion of the upper electrode150A is determined depending on the size of a memory cell, the acute angle may be in a range of 45° to 89°. In another implementation, a ratio of the width at a lower portion to a width at the upper portion of the upper electrode150A is in a range of 1.1 to 2.

The upper electrode150A having the inclined sidewall shape may be formed by performing an anisotropic etching process using an etching gas. During the anisotropic etching process, a large amount of polymer is generated. The upper electrode150A having the inclined sidewall shape is obtained as the polymer generated in the etching process is deposited on an etched surface. However, implementations are not limited thereto. In other implementations, the upper electrode150A, which has a trapezoidal shape or the like having a gradually increasing width, may be obtained through various etching methods.

Referring toFIGS. 3A and 3B, the variable resistance layer140, the intermediate electrode layer130, the selection element layer120, and the lower electrode layer110may be etched to form a variable resistance pattern140A, an intermediate electrode130A, a selection element pattern120A, and the lower electrode110A. A stacked structure of the lower electrode110A, the selection element pattern120A, the intermediate electrode130A, the variable resistance pattern140A, and the upper electrode150A may be referred to as a memory cell MC. The memory cell MC has a pillar structure.

When etching the variable resistance layer140, the intermediate electrode layer130, the selection element layer120, and the lower electrode layer110, the upper electrode150A may be partially etched. However, since the upper electrode150A may include a material having a lower etch rate than the variable resistance layer140, the intermediate electrode layer130, the selection element layer120, and the lower electrode layer110, the upper electrode150A may maintain the inclined sidewall shape after the etching process.

In a plan view, a plurality of memory cells MC may be arranged separately from each other since the plurality of memory cells have an island shape. InFIG. 3A, four memory cells MC are arranged in a matrix form along the first direction and the second direction, but implementations are not limited thereto. In another implementation, the number and arrangement of the memory cells MC may be variously modified. AlthoughFIG. 3Ashows the memory cells MC having a rectangular planar shape, a planar shape and a size of each of the lower electrode110A, the selection element pattern120A, the intermediate electrode130A, the variable resistance pattern140A, and the upper electrode150A may be different from each other and may be variously modified.

In a cross-sectional view, a width of an upper surface of a remaining portion of the memory cell MC excluding the upper electrode150A, for example, a width of an upper surface of the variable resistance pattern140A, may be smaller than a width of a lower surface of the upper electrode150A in any direction. Therefore, an undercut region may be formed under the upper electrode150A and an edge of a lower portion of the upper electrode150A may protrude outwards from a side surface of the remaining portion of the memory cell MC that is located under the upper electrode150A. For example, the edge of the lower portion of the upper electrode150A may protrude from a side surface of the variable resistance pattern140A. Hereinafter, the protruding edge of the lower portion of the upper electrode150A may be referred to as a protruding portion of the upper electrode150A.

Furthermore, inFIG. 3B, the remaining portion of the memory cell MC, that is, a stacked structure of the lower electrode110A, the selection element pattern120A, the intermediate electrode130A, and the variable resistance pattern140A, has a substantially constant width, and thus a side surface of the stacked structure has a substantially vertical shape. In this case, the lower surface of the upper electrode150A may have a maximum width among all portions of the memory cell MC.

However, implementations are not limited toFIG. 3B. In another implementation, the stacked structure of the lower electrode110A, the selection element pattern120A, the intermediate electrode130A, and the variable resistance pattern140A may have different widths from each other, or the width of the stacked structure may increase from top to bottom on the assumption that the undercut region is formed under the upper electrode150A to form the protruding portion of the upper electrode150A.

For example, the undercut region under the upper electrode150A may be obtained when the variable resistive layer140is etched using an isotropic etching, and thus the upper surface of the variable resistance pattern140A may have a smaller width than the lower surface of the upper electrode150A in any direction. Furthermore, by etching the intermediate electrode layer130, the selection element layer120, and the lower electrode layer110using the isotropic etching, it may be possible to obtain the lower electrode110A, the selection element pattern120A, and the intermediate electrode130A that have a smaller width than the lower surface of the upper electrode150A. However, implementations are not limited thereto. The remaining portion of the memory cell MC having a smaller width than the lower surface of the upper electrode150A may be formed through various etching methods.

During the isotropic etching for forming the lower electrode110A, the selection element pattern120A, the intermediate electrode130A, and the variable resistance pattern140A, the upper electrode150A may also be etched. Therefore, when forming the protruding portion of the upper electrode150A, the protruding portion should be formed so that the undercut region still exists under the upper electrode150A after the isotropic etching.

Referring toFIGS. 4A to 4C, a liner layer160may be formed along exposed surfaces of the substrate100and the memory cell MC.

The liner layer160may include a first liner layer160A and a second liner layer160B. The first liner layer160A may encapsulate the memory cell MC to protect the memory cell MC in a subsequent process. For example, the first liner layer160A may include a nitride such as SiN, SiCN, or the like, to prevent the memory cell MC from being oxidized. The second liner layer160B may protect an interface between the first liner layer160A and a material to be buried in a space between the memory cells MC in a subsequent process.

For example, when filling the space between the memory cells MC with a flowable insulating material in a subsequent process, the second liner layer1608may prevent occurrence of voids in the flowable insulating material. The second liner layer160B may include an oxide such as SiO2or the like.

Although, in the present implementation shown inFIGS. 4A to 4C, the liner layer160has a double-layered structure of the first liner layer160A and the second liner layer1608, implementations are not limited thereto. In another implementation, a liner layer of a single-layered structure or a multi-layered structure in which three or more layers are stacked may be formed along the exposed surfaces of the memory cells MC and the substrate100.

In another embodiment, the liner layer160may have a multi-layered structure in which the first liner layer160A and the second liner layer160B are alternately stacked more than one time. Since the number of interfaces increases as the number of layers forming the liner layer160increases, heat loss from the memory cell MC and/or heat transfer to the periphery of the memory cell MC may be additionally prevented.

Herein, a portion of the liner layer160that is located on the protruding portion of the upper electrode150A of a certain one of the memory cells MC may be in contact with portions of the liner layer160that are located on the protruding portions of the upper electrodes150A of memory cells MC, which are adjacent to the certain memory cell MC in the first and second directions. Hereinafter, a portion where the portions of the liner layer160of two neighboring memory cells MC are in contact with each other may be referred to as a contact portion CP of the liner layer160. The contact portion CP may be formed by adjusting a thickness of the liner layer160or by adjusting the number of layers forming the liner layer160.

Referring toFIG. 4A, the liner layer160surrounding the certain memory cell MC may have four contact portions CP. The liner layer160surrounding the certain memory cell MC may include two contact portions CP which contact the liner layer160surrounding two neighboring memory cells MC at both sides of the certain memory cell MC in the first direction. Also, the liner layer160surrounding the certain memory cell MC may include two contact portions CP which contact the liner layer160surrounding two neighboring memory cells MC at both sides of the certain memory cell MC in the second direction.

In addition, an opening O may be defined by four adjacent contact portions CP of the liner layer160surrounding four neighboring memory cells MC arranged in the first and second directions. Accordingly, a space between two neighboring memory cells MC in the first or second direction may be covered by the liner layer160located at the contact portion CP, but a space between two adjacent memory cells MC in a third direction may not covered by the liner layer160, and instead the opening O may exist therein. The third direction may be a diagonal direction with respect to the first and second directions, and correspond to the line B-B′.

Referring toFIG. 4B, the space between the two neighboring memory cells MC in the first or second direction may include a lower space below the contact portion CP of the liner layer160and an upper space above the contact portion CP of the liner layer160. In particular, a void V covered by the liner layer160may be formed below the contact portion CP of the liner layer160. On the other hand, as shown inFIG. 4C, a space between the two adjacent memory cells MC in the third direction may be opened without being covered by the liner layer160.

The formation of the liner layer160as described above may have the following advantages.

Since the memory cells MC are supported by the contact portions CP of the liner layer160after the liner layer160is formed and before a subsequent process, e.g., a process to be described with reference toFIGS. 5A and 5B, is performed, leaning of the memory cells MC may be prevented. Therefore, two neighboring memory cells MC arranged in the first or second direction can have an enough space therebetween without a risk of leaning.

FIGS. 5A and 5Bshow a process of filling the void V with a flowable insulating material. Even if at least a portion of the void V remains without being filled with the flowable insulating material after the filling process because of various reasons, it may be possible to prevent the memory cells MC from leaning since the memory cells MC are supported by the contact portions CP of the liner layer160.

In addition, since the liner layer160is formed along the exposed surface, I.e., a profile, of the memory cell MC, the size of the void V may be maximized. As the size of the void V increases, a volume or amount of the flowable insulating material filling spaces between the memory cells MC may be maximized, so that the advantage of using the flowable insulating material, for example, prevention of heat loss from the memory cell MC and/or heat transfer between the memory cells MC, may be maximized.

Furthermore, the process of filling the void V with the flowable insulating material, shown inFIGS. 5A and 5B, may be possible by securing the opening O.

The above advantages may be secured by simply controlling the thickness of the liner layer160so that the contact portions CP are formed between the memory cells MC arranged in the first and second directions. There may be also another advantage that a manufacturing process of the memory device is simplified.

Referring toFIGS. 5A to 5C, a flowable insulating material170may be formed to cover a resultant structure ofFIGS. 4A to 4C. The flowable insulating material170may be provided to fully cover the memory cells MC as well as filling the spaces between the memory cells MC. At this time, the flowable insulating material170may be provided through the opening O and fill the void V that is clogged in the first and second directions. In this implementation, the void V is completely filled with the flowable insulating material170. However, in another implementation, a portion of the void V may remain without being filled with the flowable insulating material170. Alternatively, the void V may be completely filled with the flowable insulating material170, but a portion of the flowable insulating material170may be lost and thus a portion of the void V may remain.

Here, the flowable insulating material170may include a material having a low dielectric constant, for example, a material having a k value of less than 2.5 to sufficiently insulate the memory cells MC from each other. Furthermore, the flowable insulating material170may include a material having a low thermal conductivity, for example, a material having a K value of less than 0.04 W/mK to prevent heat loss from the memory cell MC and heat transfer between the memory cells MC. The thermal conductivity of the flowable insulating material170may be lower than a thermal conductivity of the liner layer160. In an implementation, the flowable insulating material170may include a SiOC material, and may further include impurities such as hydrogen (H), nitrogen (N), or the like.

The filling process of the flowable insulating material170may be omitted. However, when the filling process of the flowable insulating material170is omitted, the space between the memory cells MC, for example, the void V, may be in a vacuum state or may be filled with air. Even though a thermal conductivity of the vacuum or air is considerably lower than an oxide, the filling of the flowable insulating material170in the space between the memory cells MC such as the void V may be required to prevent the void V from acting as a cause of a process failure in a subsequent process.

As described above, in this implementation, the size of the space between the memory cells MC such as the void V may be maximized by forming the liner layer160along the exposed surfaces of the memory cell MC and the substrate100, and this large space may be filled with the flowable insulating material170. As a result, the heat loss from the memory cell MC and the heat transfer between the memory cells MC may be minimized and process defects may also be prevented.

Although not shown, the flowable insulating material170may be cured through a subsequent process or in the course of time.

Referring toFIGS. 6A and 6B, a planarization process, for example, a chemical mechanical polishing (CMP) process may be performed on the flowable insulating material170and the liner layer160until the upper surface of the upper electrode150A is exposed. A flowable insulating material, which remains between the memory cells MC after the planarization process, is denoted by a reference numeral170A.

Referring again toFIGS. 6A and 6B, the memory device of the present implementation may include the plurality of memory cells MC formed over the substrate100and arranged in the matrix form along the first direction and the second direction.

At least a portion of the side surface of the memory cell MC may have a protruding shape. In this implementation, each of the memory cells MC may include the stacked structure of the lower electrode110A, the selection element pattern120A, the intermediate electrode130A, the variable resistance pattern140A, and the upper electrode150A.

The undercut region may be formed under the upper electrode150A, such that the protruding portion is formed at the lower portion of the upper electrode150A. The width of the upper surface of the variable resistance pattern140A may be smaller than the width of the lower surface of the upper electrode150A in any direction.

Furthermore, the widths of the lower electrode110A, the selection element pattern120A, the intermediate electrode130A, and the variable resistance pattern140A may be substantially constant and smaller than the width of the lower surface of the upper electrode150A in any direction. In some cases, in the memory cell MC, at least one of the lower electrode110A, the selection element pattern120A, and the intermediate electrode130A may be omitted.

The liner layer160may be formed along the profile of the memory cell MC. Portions of the liner layer160that are formed on the protruding portions of the upper electrodes150A of the neighboring memory cells MC in the first or second direction may contact each other. On the other hand, portions of the liner layer160that are formed on the protruding portions of the upper electrodes150A of the memory cells MC adjacent to each other in the third direction may be spaced apart from each other.

Accordingly, the flowable insulating material170A may be introduced through the opened space between the memory cells MC in the third direction, and the flowable insulating material170A may fill the voids V that are surrounded by the liner layer160in the first and second directions. As a result, the spaces between the memory cells MC in all directions may be filled with the flowable insulating material170A.

Here, the flowable insulating material170A may have a lower thermal conductivity than the liner layer160, thereby reducing the heat loss from the memory cell MC or the heat transfer between the memory cells MC.

As a result, thermal disturbance due to the heat loss from the memory cell MC or the heat transfer between the memory cells MC can be significantly prevented by forming the liner layer160and the flowable insulating material170A as described above.

FIG. 7is a perspective view showing a memory device in accordance with another implementation of the present disclosure.

Referring toFIG. 7, the memory device may include a first stacked structure and a second stacked structure. The second stacked structure is disposed on the first stacked structure in a direction perpendicular to a surface of a substrate (not shown), e.g., in a vertical direction with respect to the orientation ofFIG. 7.

The first stacked structure may include first word lines WL1disposed over the substrate, common bit lines CBL disposed over the first word lines WL1and extending in a direction substantially perpendicular to the first word lines WL1, and memory cells MC disposed at intersections of the first word lines WL1and the common bit lines CBL and interposed between the first word lines WL1and the common bit lines CBL.

Also, the second stacked structure may include the common bit lines CBL, second word lines WL2disposed over the common bit lines CBL and extending in a direction substantially perpendicular to the common bit lines CBL, and memory cells MC disposed at intersections of the second word lines WL2and the common bit lines CBL and interposed between the second word lines WL2and the common bit lines CBL.

Here, the extending directions of the first and second word lines WL1and WL2may be any one of the first and second directions described above with reference toFIGS. 2A to 6B, and the extending direction of the common bit lines CBL may be the other of the first and second directions described above.

The memory cells MC shown inFIG. 7may have substantially the same configurations as the memory cells MC shown inFIGS. 6A and 6B. Accordingly, inFIG. 7, a liner layer may be formed along a profile of the memory cells MC, and a flowable insulating material may be provided in spaces between the memory cells MC on which the liner layer is formed. Here, liner layer portions surrounding the memory cells MC, which are adjacent to each other in the extending direction of the first and second word lines WL1and WL2and the extending direction of the common bit line CBL, may have portions that contact each other. On the other hand, liner layer portions surrounding the memory cells MC, which are adjacent to each other in other directions, may be separated from each other.

Although two stacked structures are stacked vertically in this implementation, one stacked structure may be formed, or three or more stacked structures may be vertically stacked.

The above and other memory circuits or semiconductor devices based on the disclosed technology can be used in a range of devices or systems.FIGS. 8-12provide some examples of devices or systems that can implement the memory devices disclosed herein.

FIG. 8is an example of a configuration diagram of a microprocessor implementing memory circuitry based on the disclosed technology.

Referring toFIG. 8, a microprocessor1000may perform tasks for controlling and tuning a series of processes of receiving data from various external devices, processing the data, and outputting processing results to external devices. The microprocessor1000may include a memory unit1010, an operation unit1020, a control unit1030, and so on. The microprocessor1000may be various data processing units such as a central processing unit (CPU), a graphic processing unit (GPU), a digital signal processor (DSP) and an application processor (AP).

The memory unit1010is a part which stores data in the microprocessor1000, as a processor register, register or the like. The memory unit1010may include a data register, an address register, a floating point register, and so on. Besides, the memory unit1010may include various registers. The memory unit1010may perform the function of temporarily storing data for which operations are to be performed by the operation unit1020, result data of performing the operations and addresses where data for performing of the operations are stored.

The memory unit1010may include one or more of the above-described semiconductor devices in accordance with the implementations. For example, the memory unit1010may include a plurality of memory cells formed over a substrate, a side surface of each memory cell including a first portion which is protruded relative to a second portion and the second portion which is located below the first portion; a liner layer formed along the side surface of the memory cell, the memory cells including a first memory cell and a second memory cell adjacent to the first memory cell in a certain direction, and the liner layer located over the first portion of the first memory cell being in contact with the liner layer located over the first portion of the second memory cell; and an insulating material filling at least a portion of a space between the liner layers and having a lower thermal conductivity than the liner layer. Through this, operating characteristics of the memory unit1010may be improved. As a consequence, operating characteristics of the microprocessor1000may be improved.

The operation unit1020may perform four arithmetical operations or logical operations according to results that the control unit1030decodes commands. The operation unit1020may include at least one arithmetic logic unit (ALU) and so on.

The control unit1030may receive signals from the memory unit1010, the operation unit1020, and an external device of the microprocessor1000, perform extraction, decoding of commands, and controlling input and output of signals of the microprocessor1000, and execute processing represented by programs.

The microprocessor1000according to the present implementation may additionally include a cache memory unit1040which can temporarily store data to be inputted from an external device other than the memory unit1010or to be outputted to an external device. In this case, the cache memory unit1040may exchange data with the memory unit1010, the operation unit1020, and the control unit1030through a bus interface1050.

FIG. 9is an example of a configuration diagram of a processor implementing memory circuitry based on the disclosed technology.

Referring toFIG. 9, a processor1100may improve performance and realize multi-functionality by including various functions other than those of a microprocessor which performs tasks for controlling and tuning a series of processes of receiving data from various external devices, processing the data, and outputting processing results to external devices. The processor1100may include a core unit1110which serves as the microprocessor, a cache memory unit1120which serves to storing data temporarily, and a bus interface1130for transferring data between internal and external devices. The processor1100may include various system-on-chips (SoCs) such as a multi-core processor, a graphic processing unit (GPU), and an application processor (AP).

The core unit1110of the present implementation is a part which performs arithmetic logic operations for data inputted from an external device, and may include a memory unit1111, an operation unit1112, and a control unit1113.

The memory unit1111is a part which stores data in the processor1100, as a processor register, a register, or the like. The memory unit1111may include a data register, an address register, a floating point register, and so on. Besides, the memory unit1111may include various registers. The memory unit1111may perform the function of temporarily storing data for which operations are to be performed by the operation unit1112, result data of performing the operations and addresses where data for performing the operations are stored. The operation unit1112is a part which performs operations in the processor1100. The operation unit1112may perform four arithmetical operations, logical operations, according to results that the control unit1113decodes commands, or the like. The operation unit1112may include at least one arithmetic logic unit (ALU) and so on. The control unit1113may receive signals from the memory unit1111, the operation unit1112, and an external device of the processor1100, perform extraction, decoding of commands, controlling input and output of signals of processor1100, and execute processing represented by programs.

The cache memory unit1120is a part which temporarily stores data to compensate for a difference in data processing speeds between the core unit1110operating at a high speed and an external device operating at a low speed. The cache memory unit1120may include a primary storage section1121, a secondary storage section1122, and a tertiary storage section1123. In general, the cache memory unit1120includes the primary and secondary storage sections1121and1122, and may include the tertiary storage section1123in the case where high storage capacity is required. As the occasional demands, the cache memory unit1120may include an increased number of storage sections. That is to say, the number of storage sections which are included in the cache memory unit1120may be changed according to a design. The speeds at which the primary, secondary, and tertiary storage sections1121,1122, and1123store and discriminate data may be the same or different. In the case where the speeds of the respective storage sections1121,1122, and1123are different, the speed of the primary storage section1121may be largest. At least one storage section of the primary storage section1121, the secondary storage section1122, and the tertiary storage section1123of the cache memory unit1120may include one or more of the above-described semiconductor devices in accordance with the implementations. For example, the cache memory unit1120may include a plurality of memory cells formed over a substrate, a side surface of each memory cell including a first portion which is protruded relative to a second portion and the second portion which is located below the first portion; a liner layer formed along the side surface of the memory cell, the memory cells including a first memory cell and a second memory cell adjacent to the first memory cell in a certain direction, and the liner layer located over the first portion of the first memory cell being in contact with the liner layer located over the first portion of the second memory cell; and an insulating material filling at least a portion of a space between the liner layers and having a lower thermal conductivity than the liner layer. Through this, operating characteristics of the cache memory unit1120may be improved. As a consequence, operating characteristics of the processor1100may be improved.

Although it is shown inFIG. 9that all the primary, secondary, and tertiary storage sections1121,1122, and1123are configured inside the cache memory unit1120, it is to be noted that all the primary, secondary, and tertiary storage sections1121,1122, and1123of the cache memory unit1120may be configured outside the core unit1110and may compensate for a difference in data processing speeds between the core unit1110and the external device. Meanwhile, it is to be noted that the primary storage section1121of the cache memory unit1120may be disposed inside the core unit1110and the secondary storage section1122and the tertiary storage section1123may be configured outside the core unit1110to strengthen the function of compensating for a difference in data processing speeds. In another implementation, the primary and secondary storage sections1121and1122may be disposed inside the core units1110and the tertiary storage section1123may be disposed outside the core units1110.

The bus interface1130is a part which connects the core unit1110, the cache memory unit1120, and an external device and allows data to be efficiently transmitted.

The processor1100according to the present implementation may include a plurality of core units1110, and the plurality of core units1110may share the cache memory unit1120. The plurality of core units1110and the cache memory unit1120may be directly connected or be connected through the bus interface1130. The plurality of core units1110may be configured in the same way as the above-described configuration of the core unit1110. In the case where the processor1100includes the plurality of core unit1110, the primary storage section1121of the cache memory unit1120may be configured in each core unit1110in correspondence to the number of the plurality of core units1110, and the secondary storage section1122and the tertiary storage section1123may be configured outside the plurality of core units1110in such a way as to be shared through the bus interface1130. The processing speed of the primary storage section1121may be larger than the processing speeds of the secondary and tertiary storage section1122and1123. In another implementation, the primary storage section1121and the secondary storage section1122may be configured in each core unit1110in correspondence to the number of the plurality of core units1110, and the tertiary storage section1123may be configured outside the plurality of core units1110in such a way as to be shared through the bus interface1130.

The processor1100according to the present implementation may further include an embedded memory unit1140which stores data, a communication module unit1150which can transmit and receive data to and from an external device in a wired or wireless manner, a memory control unit1160which drives an external memory device, and a media processing unit1170which processes the data processed in the processor1100or the data inputted from an external input device and outputs the processed data to an external interface device and so on. Besides, the processor1100may include a plurality of various modules and devices. In this case, the plurality of modules which are added may exchange data with the core units1110and the cache memory unit1120and with one another, through the bus interface1130.

The embedded memory unit1140may include not only a volatile memory but also a nonvolatile memory. The volatile memory may include a DRAM (dynamic random access memory), a mobile DRAM, an SRAM (static random access memory), and a memory with similar functions to above mentioned memories, and so on. The nonvolatile memory may include a ROM (read only memory), a NOR flash memory, a NAND flash memory, a phase change random access memory (PRAM), a resistive random access memory (RRAM), a spin transfer torque random access memory (STTRAM), a magnetic random access memory (MRAM), or a memory with similar functions.

The memory control unit1160is to administrate and process data transmitted between the processor1100and an external storage device operating according to a different communication standard. The memory control unit1160may include various memory controllers, for example, devices which may control IDE (Integrated Device Electronics), SATA (Serial Advanced Technology Attachment), SCSI (Small Computer System Interface), RAID (Redundant Array of Independent Disks), an SSD (solid state disk), eSATA (External SATA), PCMCIA (Personal Computer Memory Card International Association), a USB (universal serial bus), a secure digital (SD) card, a mini secure digital (mSD) card, a micro secure digital (micro SD) card, a secure digital high capacity (SDHC) card, a memory stick card, a smart media (SM) card, a multimedia card (MMC), an embedded MMC (eMMC), a compact flash (CF) card, and so on.

The media processing unit1170may process the data processed in the processor1100or the data inputted in the forms of image, voice and others from the external input device and output the data to the external interface device. The media processing unit1170may include a graphic processing unit (GPU), a digital signal processor (DSP), a high definition audio device (HD audio), a high definition multimedia interface (HDMI) controller, and so on.

FIG. 10is an example of a configuration diagram of a system implementing memory circuitry based on the disclosed technology.

Referring toFIG. 10, a system1200as an apparatus for processing data may perform input, processing, output, communication, storage, etc. to conduct a series of manipulations for data. The system1200may include a processor1210, a main memory device1220, an auxiliary memory device1230, an interface device1240, and so on. The system1200of the present implementation may be various electronic systems which operate using processors, such as a computer, a server, a PDA (personal digital assistant), a portable computer, a web tablet, a wireless phone, a mobile phone, a smart phone, a digital music player, a PMP (portable multimedia player), a camera, a global positioning system (GPS), a video camera, a voice recorder, a telematics, an audio visual (AV) system, a smart television, and so on.

The processor1210may decode inputted commands and processes operation, comparison, etc. for the data stored in the system1200, and controls these operations. The processor1210may include a microprocessor unit (MPU), a central processing unit (CPU), a single/multi-core processor, a graphic processing unit (GPU), an application processor (AP), a digital signal processor (DSP), and so on.

The main memory device1220is a storage which can temporarily store, call and execute program codes or data from the auxiliary memory device1230when programs are executed and can conserve memorized contents even when power supply is cut off. The main memory device1220may include one or more of the above-described semiconductor devices in accordance with the implementations. For example, the main memory device1220may include a plurality of memory cells formed over a substrate, a side surface of each memory cell including a first portion which is protruded relative to a second portion and the second portion which is located below the first portion; a liner layer formed along the side surface of the memory cell, the memory cells including a first memory cell and a second memory cell adjacent to the first memory cell in a certain direction, and the liner layer located over the first portion of the first memory cell being in contact with the liner layer located over the first portion of the second memory cell; and an insulating material filling at least a portion of a space between the liner layers and having a lower thermal conductivity than the liner layer. Through this, operating characteristics of the main memory device1220may be improved. As a consequence, operating characteristics of the system1200may be improved.

Also, the main memory device1220may further include a static random access memory (SRAM), a dynamic random access memory (DRAM), and so on, of a volatile memory type in which all contents are erased when power supply is cut off. Unlike this, the main memory device1220may not include the semiconductor devices according to the implementations, but may include a static random access memory (SRAM), a dynamic random access memory (DRAM), and so on, of a volatile memory type in which all contents are erased when power supply is cut off.

The auxiliary memory device1230is a memory device for storing program codes or data. While the speed of the auxiliary memory device1230is slower than the main memory device1220, the auxiliary memory device1230can store a larger amount of data. The auxiliary memory device1230may include one or more of the above-described semiconductor devices in accordance with the implementations. For example, the auxiliary memory device1230may include a plurality of memory cells formed over a substrate, a side surface of each memory cell including a first portion which is protruded relative to a second portion and the second portion which is located below the first portion; a liner layer formed along the side surface of the memory cell, the memory cells including a first memory cell and a second memory cell adjacent to the first memory cell in a certain direction, and the liner layer located over the first portion of the first memory cell being in contact with the liner layer located over the first portion of the second memory cell; and an insulating material filling at least a portion of a space between the liner layers and having a lower thermal conductivity than the liner layer. Through this, operating characteristics of the auxiliary memory device1230may be improved. As a consequence, operating characteristics of the system1200may be improved.

Also, the auxiliary memory device1230may further include a data storage system (see the reference numeral1300ofFIG. 11) such as a magnetic tape using magnetism, a magnetic disk, a laser disk using optics, a magneto-optical disc using both magnetism and optics, a solid state disk (SSD), a USB memory (universal serial bus memory), a secure digital (SD) card, a mini secure digital (mSD) card, a micro secure digital (micro SD) card, a secure digital high capacity (SDHC) card, a memory stick card, a smart media (SM) card, a multimedia card (MMC), an embedded MMC (eMMC), a compact flash (CF) card, and so on. Unlike this, the auxiliary memory device1230may not include the semiconductor devices according to the implementations, but may include data storage systems (see the reference numeral1300ofFIG. 11) such as a magnetic tape using magnetism, a magnetic disk, a laser disk using optics, a magneto-optical disc using both magnetism and optics, a solid state disk (SSD), a USB memory (universal serial bus memory), a secure digital (SD) card, a mini secure digital (mSD) card, a micro secure digital (micro SD) card, a secure digital high capacity (SDHC) card, a memory stick card, a smart media (SM) card, a multimedia card (MMC), an embedded MMC (eMMC), a compact flash (CF) card, and so on.

The interface device1240may be to perform exchange of commands and data between the system1200of the present implementation and an external device. The interface device1240may be a keypad, a keyboard, a mouse, a speaker, a mike, a display, various human interface devices (HIDs), a communication device, and so on. The communication device may include a module capable of being connected with a wired network, a module capable of being connected with a wireless network and both of them. The wired network module may include a local area network (LAN), a universal serial bus (USB), an Ethernet, power line communication (PLC), such as various devices which send and receive data through transmit lines, and so on. The wireless network module may include Infrared Data Association (IrDA), code division multiple access (CDMA), time division multiple access (TDMA), frequency division multiple access (FDMA), a wireless LAN, Zigbee, a ubiquitous sensor network (USN), Bluetooth, radio frequency identification (RFID), long term evolution (LTE), near field communication (NFC), a wireless broadband Internet (Wibro), high speed downlink packet access (HSDPA), wideband CDMA (WCDMA), ultra wideband (UWB), such as various devices which send and receive data without transmit lines, and so on.

FIG. 11is an example of a configuration diagram of a data storage system implementing memory circuitry based on the disclosed technology.

Referring toFIG. 11, a data storage system1300may include a storage device1310which has a nonvolatile characteristic as a component for storing data, a controller1320which controls the storage device1310, an interface1330for connection with an external device, and a temporary storage device1340for storing data temporarily. The data storage system1300may be a disk type such as a hard disk drive (HDD), a compact disc read only memory (CDROM), a digital versatile disc (DVD), a solid state disk (SSD), and so on, and a card type such as a USB memory (universal serial bus memory), a secure digital (SD) card, a mini secure digital (mSD) card, a micro secure digital (micro SD) card, a secure digital high capacity (SDHC) card, a memory stick card, a smart media (SM) card, a multimedia card (MMC), an embedded MMC (eMMC), a compact flash (CF) card, and so on.

The storage device1310may include a nonvolatile memory which stores data semi-permanently. The nonvolatile memory may include a ROM (read only memory), a NOR flash memory, a NAND flash memory, a phase change random access memory (PRAM), a resistive random access memory (RRAM), a magnetic random access memory (MRAM), and so on.

The controller1320may control exchange of data between the storage device1310and the interface1330. To this end, the controller1320may include a processor1321for performing an operation for, processing commands inputted through the interface1330from an outside of the data storage system1300and so on.

The interface1330is to perform exchange of commands and data between the data storage system1300and the external device. In the case where the data storage system1300is a card type, the interface1330may be compatible with interfaces which are used in devices, such as a USB memory (universal serial bus memory), a secure digital (SD) card, a mini secure digital (mSD) card, a micro secure digital (micro SD) card, a secure digital high capacity (SDHC) card, a memory stick card, a smart media (SM) card, a multimedia card (MMC), an embedded MMC (eMMC), a compact flash (CF) card, and so on, or be compatible with interfaces which are used in devices similar to the above mentioned devices. In the case where the data storage system1300is a disk type, the interface1330may be compatible with interfaces, such as IDE (Integrated Device Electronics), SATA (Serial Advanced Technology Attachment), SCSI (Small Computer System Interface), eSATA (External SATA), PCMCIA (Personal Computer Memory Card International Association), a USB (universal serial bus), and so on, or be compatible with the interfaces which are similar to the above mentioned interfaces. The interface1330may be compatible with one or more interfaces having a different type from each other.

The temporary storage device1340can store data temporarily for efficiently transferring data between the interface1330and the storage device1310according to diversifications and high performance of an interface with an external device, a controller and a system. The temporary storage device1340for temporarily storing data may include one or more of the above-described semiconductor devices in accordance with the implementations. The temporary storage device1340may include a plurality of memory cells formed over a substrate, a side surface of each memory cell including a first portion which is protruded relative to a second portion and the second portion which is located below the first portion; a liner layer formed along the side surface of the memory cell, the memory cells including a first memory cell and a second memory cell adjacent to the first memory cell in a certain direction, and the liner layer located over the first portion of the first memory cell being in contact with the liner layer located over the first portion of the second memory cell; and an insulating material filling at least a portion of a space between the liner layers and having a lower thermal conductivity than the liner layer. Through this, operating characteristics of the storage device1310or the temporary storage device1340may be improved. As a consequence, operating characteristics and data storage characteristics of the data storage system1300may be improved.

FIG. 12is an example of a configuration diagram of a memory system implementing memory circuitry based on the disclosed technology.

Referring toFIG. 12, a memory system1400may include a memory1410which has a nonvolatile characteristic as a component for storing data, a memory controller1420which controls the memory1410, an interface1430for connection with an external device, and so on. The memory system1400may be a card type such as a solid state disk (SSD), a USB memory (universal serial bus memory), a secure digital (SD) card, a mini secure digital (mSD) card, a micro secure digital (micro SD) card, a secure digital high capacity (SDHC) card, a memory stick card, a smart media (SM) card, a multimedia card (MMC), an embedded MMC (eMMC), a compact flash (CF) card, and so on.

The memory1410for storing data may include one or more of the above-described semiconductor devices in accordance with the implementations. For example, the memory1410may include a plurality of memory cells formed over a substrate, a side surface of each memory cell including a first portion which is protruded relative to a second portion and the second portion which is located below the first portion; a liner layer formed along the side surface of the memory cell, the memory cells including a first memory cell and a second memory cell adjacent to the first memory cell in a certain direction, and the liner layer located over the first portion of the first memory cell being in contact with the liner layer located over the first portion of the second memory cell; and an insulating material filling at least a portion of a space between the liner layers and having a lower thermal conductivity than the liner layer. Through this, operating characteristics of the memory1410may be improved. As a consequence, operating characteristics and data storage characteristics of the memory system1400may be improved.

Also, the memory1410according to the present implementation may further include a ROM (read only memory), a NOR flash memory, a NAND flash memory, a phase change random access memory (PRAM), a resistive random access memory (RRAM), a magnetic random access memory (MRAM), and so on, which have a nonvolatile characteristic.

The memory controller1420may control exchange of data between the memory1410and the interface1430. To this end, the memory controller1420may include a processor1421for performing an operation for and processing commands inputted through the interface1430from an outside of the memory system1400.

The interface1430is to perform exchange of commands and data between the memory system1400and the external device. The interface1430may be compatible with interfaces which are used in devices, such as a USB memory (universal serial bus memory), a secure digital (SD) card, a mini secure digital (mSD) card, a micro secure digital (micro SD) card, a secure digital high capacity (SDHC) card, a memory stick card, a smart media (SM) card, a multimedia card (MMC), an embedded MMC (eMMC), a compact flash (CF) card, and so on, or be compatible with interfaces which are used in devices similar to the above mentioned devices. The interface1430may be compatible with one or more interfaces having a different type from each other.

The memory system1400according to the present implementation may further include a buffer memory1440for efficiently transferring data between the interface1430and the memory1410according to diversification and high performance of an interface with an external device, a memory controller and a memory system. For example, the buffer memory1440for temporarily storing data may include one or more of the above-described semiconductor devices in accordance with the implementations. The buffer memory1440may include a plurality of memory cells formed over a substrate, a side surface of each memory cell including a first portion which is protruded relative to a second portion and the second portion which is located below the first portion; a liner layer formed along the side surface of the memory cell, the memory cells including a first memory cell and a second memory cell adjacent to the first memory cell in a certain direction, and the liner layer located over the first portion of the first memory cell being in contact with the liner layer located over the first portion of the second memory cell; and an insulating material filling at least a portion of a space between the liner layers and having a lower thermal conductivity than the liner layer. Through this, operating characteristics of the buffer memory1440may be improved. As a consequence, operating characteristics and data storage characteristics of the memory system1400may be improved.

Moreover, the buffer memory1440according to the present implementation may further include an SRAM (static random access memory), a DRAM (dynamic random access memory), and so on, which have a volatile characteristic, and a phase change random access memory (PRAM), a resistive random access memory (RRAM), a spin transfer torque random access memory (STTRAM), a magnetic random access memory (MRAM), and so on, which have a nonvolatile characteristic. Unlike this, the buffer memory1440may not include the semiconductor devices according to the implementations, but may include an SRAM (static random access memory), a DRAM (dynamic random access memory), and so on, which have a volatile characteristic, and a phase change random access memory (PRAM), a resistive random access memory (RRAM), a spin transfer torque random access memory (STTRAM), a magnetic random access memory (MRAM), and so on, which have a nonvolatile characteristic.

Features in the above examples of electronic devices or systems inFIGS. 8-12based on the memory devices disclosed in this document may be implemented in various devices, systems or applications. Some examples include mobile phones or other portable communication devices, tablet computers, notebook or laptop computers, game machines, smart TV sets, TV set top boxes, multimedia servers, digital cameras with or without wireless communication functions, wrist watches or other wearable devices with wireless communication capabilities.

Only a few implementations and examples are described. Other implementations, enhancements and variations can be made based on what is described and illustrated in this patent document.