Method and apparatus for transfer control and undervoltage detection in an automatic transfer switch

An automatic transfer switch is disclosed that features a novel arrangement for detecting a failure of the power source as well as a novel arrangement for preventing cross-conduction between the first and second signal sources during a rapid transfer.

BACKGROUND OF THE INVENTION

The simplest mechanical automatic transfer switch comprises a single form C relay. It is desirable to have the relay switch quickly to minimize the power disruption to the load. However, rapid relay switching creates a possible shoot-through problem, i.e., an arc will form between the opening contacts, and if this arc is still conducting when the closing contacts close, a current path is created between the two input sources, shorting them together through the arc.

This problem was addressed in, for example, U.S. Pat. No. 4,811,163 which discloses the use of solid state snubbers in parallel with two mechanical form A or form B relays, with the relays used to accomplish the transfer. The arc is quenched by the solid state snubbers in parallel with the opening switch contact. Conversely, the present invention uses a relay in series with the contact for arc quenching rather than a parallel snubber. Furthermore the control circuit timing used in the present invention has significant advantages over the control circuit disclosed in the '163 Patent. The control circuit of the '163 Patent uses a pair of solid state switches to short the inputs together if one fails or is fired by noise or a failure of the drive circuit. This creates a potential backfeed problem, i.e., if one of the inputs is unplugged, a person touching the power pins on the end of the cord could be shocked by power coming from the other source. Furthermore, if both circuits are powered, a catastrophic short circuit would result. These safety problems render the system disclosed in the '163 Patent unacceptable under UL safety standard UL1950. Conversely, the system of the present invention meets these safety requirements.

An additional challenge facing designers and users of automatic transfer switches is detecting a failure of the primary source, so that a transfer to the secondary source can be initiated. A typical technique is to extract the level of the AC signal as a DC signal and compare it to a fixed DC reference. Most of the known techniques for detecting the level of an AC signal by converting it to a DC signal require long time constant filters to remove the AC component of the signal. Digital voltmeters, for example, use either a rectifier or an RMS to DC converter followed by a long time constant, low pass filter to smooth the ripple. These long time constant filters have long delays that are unacceptable in a transfer switch application, which must detect an AC signal failure in a quarter cycle or less.

One known technique to avoid this problem is to use a computer chip to compare the voltage in real time to an ideal sine wave reference signal calculated by the CPU. A transfer is initiated if the voltage deviates from the ideal sine wave by more than a predetermined amount. One shortcoming of this technique is that a dead band exists around the zero crossings of the voltage waveform. Because the source voltage is nearly zero during this portion of the cycle, it is difficult to differentiate between the normal waveform zero crossing and a source failure. One prior art solution to this problem has been to wait a sufficient time until it is known that the voltage is supposed to be higher. If he voltage has not risen, a failure has occurred. In addition to the undesirable delay, an additional disadvantage of this technique is that it requires a CPU, with the associated complexity, noise and reliability problems.

Conversely, the automatic transfer switch of the present invention solves this problem by tracking the slope of the AC signal in addition to its magnitude. Because the slope of a sine wave is highest at the zero crossings, the slope signal is strongest at exactly the same point where the magnitude signal is weakest. Therefore, adding the magnitude and slope creates a signal that reliably and quickly indicates a voltage source failure at all points along the waveform.

SUMMARY OF THE INVENTION

One feature of the present invention is a relay sequencing scheme that prevents undesirable cross-conduction between the two input AC sources of an automatic transfer switch. Cross-conduction is caused by contact arcing that starts when the relays of one source are opened and continues after the relays of a second source are closed. The present invention solves this problem by placing an extra set of relays in series with an upstream of the main transfer relay. The extra relays independently control switching of the inputs. Because the inputs are switched independently, a time delay may be introduced between the opening of the first set of contacts and the closing the other set, thereby allowing sufficient time for the arcing to stop and preventing the undesirable cross-conduction between the two sources.

Another feature of the present invention is a fast detection technique for sensing an under voltage condition in an AC signal and, more generally, for extracting the envelope of an AC signal. The technique involves adding the signal with a phase shifted version of itself, converting the summed signal to a DC level through a non-linear process, e.g. rectifying or squaring, and then comparing the DC level to a fixed threshold.

DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS

An automatic transfer switch in accordance with the present invention is illustrated in FIG.1. Automatic transfer switch7connects first alternating current (“AC”) voltage source3and second AC voltage source4to load2. For purposes of the following discussion, first AC voltage source3will be referred to as the primary source and AC voltage source4will be referred to as the secondary source. Under normal conditions, i.e., when primary source3is available, transfer switch7will connect primary source3to load2. If primary source3fails, transfer switch7will automatically and rapidly connect second source4to load2to prevent disruption of power to load2.

Automatic transfer switch7comprises switch1, illustrated as a form C relay, as the primary transfer element. To minimize power disruption to the load, it is desirable that switch1switch as rapidly as possible upon failure of the normal source. However, rapid switching of switch1creates a potential shoot through, i.e., cross-conduction, problem. Because of inductance in the system, when switch1opens the connection between source3and load2, an arc may strike between the switch contacts. If this arcing is still present when the switch1closes connecting the standby source4to load2, undesirable cross-conduction between the two sources will result.

According to the present invention, a solution to this cross-conduction problem is to use a form A (or form B) relay in series with each source. Turning again toFIG. 1, switch5is series connected between primary source3and switch1. Similarly, switch6is series connected between secondary source4and switch1. Upon failure of normal source3, switch5is opened at the same time form C switch1is changing states. After switch1has changed states, switch6closes thereby completing the circuit from secondary source4to load2. A delay is interposed before closing switch6to guarantee that a voltage zero crossing occurs between the opening of switch5and the closing of switch6. This zero crossing insures any arc across switch1will die out before secondary source4is connected.

There are multiple alternatives for determining the delay to be interposed before closing switch6. One approach is to use a fixed time delay equal to one-half cycle of the AC input voltage. A one-half cycle delay guarantees that there will be a zero crossing during the delay interval. The arcing will stop no later than the zero crossing and, thus, will have stopped before relay6closes.

Another approach to determining the delay before switch6may be closed is to sense the arc and close switch6as soon the arcing stops. This can be done in one of three ways. The first is to monitor the current through switch1and close after a zero crossing. A second way is to monitor the voltage across switch1and close after a zero crossing. A third method is to monitor the voltage across switch1and close after a high voltage is detected. Of the latter alternatives, it is preferable switch after a voltage zero crossing because the arc will be quenched at the zero crossing. Conversely, a high voltage will not be detectable until some fraction of a cycle after the zero crossing.

Still another alternative technique for determining when switch6may be closed is to use a combination of the two methods discussed above, i.e., sensing the arc but transferring after one-half cycle even if a “no arc” reading has not been detected.

A timing diagram illustrating switching of transfer switch7is given in FIG.2. At a first time t1, the switch from primary source3to secondary source4begins. At time t1, transfer switch1switches from primary source3to secondary source4. At the same time, relay5is opened to prevent arcing across transfer switch1. After a delay time tdthat extends from tdto t2, switch6is closed connecting secondary source4to load.FIG. 2also illustrates a retransfer to the primary source, beginning at time t3. First, Switch1transfer from secondary source4to primary source3. Simultaneously, switch6is opened to prevent arcing across switch1. After a delay time td, which ends time t4, switch5is closed reconnecting to load2to primary source3.

Another problem of existing automatic transfer switches is that of rapidly detecting a source failure so that a secondary source may be connected quickly, minimizing load disruption. Various circuits and techniques are known for detecting a source failure of using the source voltage waveform. One such circuit is illustrated inFIG. 3a. The circuit detects a failure of delta connected three phase voltage source301.FIG. 3bshows the line to line voltages produced by source301: VAC311, VCB312and VBA(313).

Source301is connected to the input of three phase bridge rectifier303. The output of rectifier303is connected to the input of differential amplifier304, which converts the rectified sinusoidal produced by rectifier303to a DC voltage signal that is referenced to ground. If source301is operating normally, the output of differential amplifier304will be rectified sinusoid314. The rectified sinusoid314is input to comparator305, which compares the rectified sinusoid to DC reference source306. The voltage of reference source306is the threshold voltage for failure detection. The detection threshold is chosen as 85% of the minimum value of rectified sinusoid314. If the instantaneous output voltage of differential amplifier304drops below voltage of reference source306, i.e., voltage level315, then the output307of comparator305will go to a logic high signal indicating a failure of source301.

The detection circuit illustrated inFIG. 3also includes switch302connected in one phase of the circuit between source301and rectifier303. Opening switch302, simulates a single phase failure of source301. A single phase failure of source301changes the output of differential amplifier304from rectified sinusoid314to pure sinusoid316. Comparator305will transition to a logical high output when the instantaneous voltage of signal316drops below the DC detection threshold315.

To determine the maximum time between failure of source301and detection of the failure by a transition on output307, it is necessary to determine the maximum time required for the instantaneous voltage of differential amplifier304output signal316to drop below the voltage of reference306, i.e., detection threshold315. The longest detection time will result if the failure occurs when voltage waveform316has just passed above detection threshold315, identified as to inFIG. 3c. The failure of source301will be detected at time t2when signal116again drops below detection threshold315. The elapsed time between t1and t2, which is the maximum detection time, is 0.237 cycles of the source AC waveform. For a 60 Hz system, this time is approximately 3.95 milliseconds. For a 50 Hz system, the time is 4.74 milliseconds.

The detection circuit ofFIG. 3may be adapted for use with a wye connected source as illustrated in FIG.4. The circuit comprises wye-connected, three phase source401, connected to the input of three phase rectifier403. The output of rectifier403is connected to the input of comparator405, which compares the rectifier output signal to DC reference source406. Operation of this circuit is basically the same as the circuit discussed above. The maximum time required to detect a source failure is also the same, i.e., 0.237 cycles of the AC waveform.

A variation on the detection circuits described above is illustrated inFIG. 5a.Each phase of three phase delta connected source501is connected to a differential amplifier504to isolate the individual phase voltages. The isolated phase voltage are G1rectified by full wave rectifiers503. The three rectifier output waveforms are added together by summing amplifier508. The output of summing amplifier508is connected to a first input of comparator505. Voltage signal509, shown inFIG. 5b, is the output of summing amplifier508when source501is operating normally.

A second input of comparator505is DC reference506. Voltage signal510is the voltage of DC reference506and is also the source failure detection threshold. The failure detection threshold is chosen as 85% of the minimum value of detection waveform509. If one phase of source501fails, the output of summing amplifier508becomes voltage waveform311. The source failure will be detected when waveform311drops below detection threshold510, causing output507of comparator505to transition to a logic high value.

The maximum detection time is required when the failure occurs just after signal511rises above detection threshold510, shown at time t1. The failure will not be detected until signal311falls below threshold level510, which occurs at time t2. The elapsed time between t1and t2is 0.237 cycles of the AC voltage waveform, the same detection time required by the circuits described above.

The detection circuit ofFIG. 5may be adapted for use with a wye connected source, as shown in FIG.6. Each phase of source601is connected to the input of one of full wave rectifiers603. The outputs of rectifiers603are connected to the input of summing amplifier608. Voltage signal609, shown inFIG. 6B, is the output of summing amplifier608when all phases of source601are operating normally.

The output of summing amplifier608is connected to an input comparator605. Comparator605compares the output of summing amplifier608to reference voltage606. Voltage signal610is the DC voltage of reference source606and is the source failure detection threshold. If a failure has not occurred, the output voltage of summing amplifier408is greater than the voltage of DC reference606, and comparator405generates a logic low signal at output607. If source601fails, the output voltage of summing amplifier608becomes signal611, shown inFIG. 6b. When signal611drops below the detection threshold610, comparator605will generate a logic high signal at output607.

The maximum time required to detect a failure will occur if the failure occurs at the point where signal611rises above detection threshold610, shown at t1. The failure will not be detected until the signal drops below detection threshold610, which occurs at t2. The elapsed time between points t1and t2is 0.176 cycles, which corresponds to 2.93 milliseconds for a 60 Hz system or 3.52 milliseconds for a 50 Hz system. Although the circuit ofFIG. 6exhibits slightly faster detection circuits than the circuits discussed above, this circuit may be used only if a neutral connection is available.

Another detection circuit is illustrated in FIG.7. The circuit ofFIG. 7is suitable for use with a three phase, delta connected source. The detection circuit comprises differential amplifiers704, squaring circuits703, summing amplifier708, DC reference source706, and comparator705. Each phase of source701connected to an input of one of differential amplifiers704to isolate the individual phase voltages. The outputs of differential amplifiers704are connected to the inputs of squaring circuits703. The outputs of the squaring circuits are connected to the inputs of summing amplifier708, which adds the three voltages. Signal709shown inFIG. 7bis the normal output signal for summing amplifier708. Signal711is the output of summing amplifier708when one phase of source701has failed, which can be simulated by opening switch702.

The output of summing amplifier708is connected to a first input of comparator705. The second input of comparator705is connected to DC reference706. Detection threshold710, shown inFIG. 7b, is the voltage of DC reference706. As in the other examples, the detection threshold is selected as 85% of the normal detection waveform. If the instantaneous output voltage of summing amplifier708output signal is less than the voltage of DC reference706, the output707of comparator705will be a logical high value, indicating a failure of voltage source701.

The maximum failure detection time will result when the failure occurs immediately after summing amplifier708output signal711has risen above detection threshold710, which occurs at t1. The failure will not be detected until signal711drops below threshold710at time t2. The elapsed time between t1and t2is 0.189 cycles of the AC waveform, which corresponds to 3.15 milliseconds for a 60 Hz system or 3.78 milliseconds for a 50 Hz system. This detection time is slightly faster than the methods discussed above. An additional advantage of this circuit is that it produces a DC signal representing the squared envelope of the waveform in real time.

The novel detection circuit illustrated inFIG. 8aderives a phase shifted (quadrature) signal using a differentiator (slope) circuit. By including the quadrature signal in the detection circuit, a fault detection time of zero is theoretically possible at all phase angles. However, the differentiation function is inherently noise sensitive. Therefore, in practice it is frequently necessary to follow the differentiator circuit with a low pass filter, which introduces some slight detection delay.

The circuit ofFIG. 8comprises single phase AC source801, differentiator804, full wave rectifiers803, summing amplifier808, comparator805, DC reference806and an optional low pass filter809. Summing amplifier808adds a full-wave rectified version of the output waveform of source801to a full-wave rectified version of the derivative of the voltage of source801. The output of summing amplifier808may be passed through optional low pass filter809.

AC waveform810is the output of the summing amplifier808, which is a first input signal for comparator805. The second input to comparator805is reference source806. Failure detection threshold811is the voltage of DC reference806. If the instantaneous output voltage of summing amplifier808is less than the voltage of DC reference806, comparator805generates a logic high signal at output807to indicate a source failure.

The inherent detection delay time of this circuit is zero. If source801fails, the sense voltage810goes to zero immediately because the input signal and its derivative are zero. The detection delay is also independent of phase angle. As noted above, however, the circuit ofFIG. 8is noise sensitive. Therefore, low pass filtering is generally beneficial, although the filtering does slightly slow detection times from the ideal case.

Another novel detection circuit is illustrated in FIG.9. This circuit is similar to the circuit ofFIG. 8, except that the direct and quadrature signals are converted to DC by squaring instead of rectification. As opposed to rectification, squaring the voltage signals theoretically produces a pure DC voltage with no AC ripple. The circuit ofFIG. 9produces an instantaneous DC voltage corresponding to the square of the AC signal envelope. The circuit ofFIG. 9does have the noise disadvantage described above, although low pass filters may be added to reduce the noise sensitivity. As with the circuit ofFIG. 8, the inherent detection delay time for this circuit is zero.

The circuit ofFIG. 9comprises AC voltage source901, differentiator circuit904, squaring circuits903, summing amplifier908, DC reference source906and comparator905. The circuit operates by adding the square of the voltage waveform produced by source901to the square of the derivative of the voltage waveform produced by source901. This summed signal is then compared to a DC reference value, and a failure of source901is indicated by the output907of comparator905generating a logical high signal, caused when the summed squared waveforms fall below the DC reference value.

If the voltage waveform goes to zero, the sense voltage also immediately goes to zero, independent of phase angle. An additional novel feature of this detection circuit is that it generates an instantaneous DC voltage that is equal to the envelope of the sine wave.

The circuit ofFIG. 10extends the circuits ofFIG. 8or9to a three phase, wye connected system. The circuit comprises three phase, wye connected source1001and includes three copies of the circuit disclosed inFIG. 8or9, one copy for each phase. The technique described in conjunction withFIG. 8or9is applied independently to each phase of the three phase circuit. The results are, therefore, the same as described above. The failure detection outputs for each phase are logically “OR'd” together. The circuit thus produces a failure signal if any one or more of the individual phases fails.

The circuits described below compromise between the noise sensitivity of the quadrature circuits ofFIGS. 8,9and10with the slower detection times of the rectification circuits. These circuits operate by adjusting the ratio of the direct and quadrature signals.

The first such combination circuit is illustrated in FIG.11. Each phase connection of three phase, delta connected source1101is connected to the input of one of differential amplifiers1104, which isolate the individual phase voltages. The isolated phase voltages are input into full-wave rectifiers1103. The full-wave rectified signals are summed by summing amplifier1108a. The isolated voltages are fed in parallel into differentiator circuits1109, and the output of the differentiator circuits are input into full-wave rectifiers1103′, and the rectified derivative signals are summed by summing amplifier1108b. The summed rectified signals are added to the scaled sum of the rectified differentiator signals by summing amplifier1108. Scaling is performed by variable mixer1110, which operates in conjunction with variable DC source1111. The summed signal output of summing amplifier1108is input into comparator1105, which also receives an input from constant DC reference source1106. If the output of summing amplifier1108is less than the reference source voltage, the comparator generates a logical high signal, indicating a failure of AC source1101.

The circuit ofFIG. 11uses the method 3 discussed above but includes a fraction of the rectified quadrature signal derived in method 6 to make a compromise hybrid approach. The hybrid approach has lower delay times than method 3 but is less susceptible to noise than a full quadrature detection system.FIG. 11billustrates the relevant waveforms generated by the circuit ofFIG. 11with the ratio of base signal to quadrature signal of 2.5 to 1. Waveform1112is the output of summing amplifier1108with all phases operational, while waveform1114is the output of summing amplifier1108with phase A failed by opening switch1102. DC waveform1113is the DC value of reference1106. When a failure of the source1101occurs, the worst case detection time will result if the failure occurs immediately when waveform1114rises above the detection threshold level, which occurs at point1115. The failure will not be detected until sense waveform1114again drops below detection level1113, which occurs at point1116. The elapsed time between points1115and1116is 0.157 cycles, which is a significant improvement over the 0.237 cycles required by the non-quadrature method.

The ratio of quadrature signal to non-quadrature signal may be adjusted to change the worst case time interval required to detect a failure. The ratio may be optimized by iterative techniques, and it turns out that the optimum ratio is 0.522186. With this ratio of quadrature signal to normal signal, the relevant waveforms are illustrated inFIG. 11c.The normal signal with source1101operating properly is signal1117. The detection threshold is signal1119. Signal1118is the detection signal with one phase of source1101faulted by opening switch1102. As can be clearly seen, the detection time should be zero, as the detection signal1118is below DC reference1119for all times when source1101is faulted.

Another detection circuit is illustrated in FIG.12. The circuit comprises three phase delta connected source1201. Source1201is input into differential amplifiers1204to isolate the individual phase voltages. The isolated voltages are then input into squaring circuits1203, and the squared signals are summed by summing amplifier1208a.The isolated voltages are then parallel fed into differentiator circuits1209, and the output of the differentiator circuits are input into squaring circuits1203′, and the squared derivative signals are summed by summing amplifier1208b. The summed squared signals are added to the scaled sum of the squared differentiator signals by summing amplifier1208. Scaling is performed by variable mixer1210, which operates in conjunction with variable DC source1211. The summed signal output of summing amplifier1208is input into comparator1205, which also receives an input from constant DC reference source1206. If the output of summing amplifier1208is less than the reference source voltage, the comparator generates a logical high signal, indicating a failure of AC source1201.

The circuit illustrated inFIG. 12is similar to the circuit disclosed inFIG. 11but operates by squaring the voltage signals rather than rectifying them. The relevant waveforms for the circuit ofFIG. 12, with the ratio of quadrature signal to unshifted signal of4to1, are illustrated inFIG. 12a. Signal1212is the output of summing amplifier1208with source1201normal. Signal1213is the detection threshold, which corresponds to the DC voltage of reference source1206. Signal1214is the detection signal output of summing amplifier1208with one phase of source1201faulted by opening switch1202. A failure will be detected when the value of signal1214is below reference voltage level1213. The worst case detection time will occur when the failure occurs at point1215, i.e., right after the level of signal1214has risen above the detection threshold. The failure will not be detected until the signal again drops below detection threshold1213, i.e., at1216. The time interval between these two may be calculated as 0.205 cycles.

The detection time may be adjusted by adjusting the ratio of quadrature signal to unshifted signal, which is accomplished by adjusting variable voltage DC source1211. The optimum ratio of quadrature signal to unshifted signal may be determined mathematically as 0.713053, which results in zero detection time as illustrated inFIG. 12c.

FIG. 13illustrates another circuit that may be used for three phase voltage failure detection. In the circuit ofFIG. 13, both the three phase signals and the quadrature signals are full-wave rectified. The circuit comprises three phase delta connected source1301, which inputs into differential amplifiers1304a,1304band1304c, which isolate the three individual phase voltages. The three individual phase voltages are input into three phase bridge rectifier1303b, which outputs into differential amplifier1304d, which generates a DC signal referenced to ground. The isolated three phase signals generated by differential amplifiers1304a,1304band1304care also input into differentiation circuits1309. The output of the differentiator circuits, i.e., the derivatives of the isolated signals are input into three phase bridge rectifier1303a. The output of three phase rectifier1303ais input into differential amplifier1304c, which produces a signal referenced to ground. The now ground-referenced rectified derivative signal is passed through variable mixer circuit1310and into summing amplifier1308, where it is added to the rectified full-wave three phase signal produced by differential amplifier1304d. The ratio of rectified derivative signal to rectified signal is controlled by mixer1310, which is controlled by the DC voltage of variable DC source1311. The output of summing amplifier1308is then input into comparator1305, which also receives an input from DC reference source1306. If the output of summing amplifier1308is less than the value of DC reference source1306, then the output1307of comparator1305goes high, indicating a failure of source1301.

The relevant waveforms for the circuit illustrated inFIG. 13are illustrated inFIG. 13a. Voltage signal1312is the output of summing amplifier1308with the ratio of quadrature signal to normal signal of 1 to 1. DC voltage signal1313is the voltage failure detection threshold level, which corresponds to the voltage of DC reference source1306. Voltage signal1314is the output of summing amplifier1308when a failure of source1301is simulated by opening switch1302. As discussed above, the worst case detection time will result when the failure occurs at the time when the detection signal rises above the level of the reference source, illustrated at point1315. The failure will not be detected until the detection signal1314again drops below detection threshold1313, which occurs at point1316.

Another method compromises between delay time and noise rejection by using an all-pass filter to generate the quadrature signal instead of a differentiator (slope-detector) is illustrated in FIG.14. The circuit comprises AC voltage source1401, which inputs into full-wave rectifier1403b. The rectified output is input into summing amplifier1408. The voltage signal from source1401is also input into all-pass phase shifter1404, which shifts the phase angle of the waveform by 90 degrees. The 90-degree shifted waveform is then input into full-wave rectifier1403a. The rectified quadrature waveform is then input into summing amplifier1408, where it is summed with the rectified line voltage. The summed signals are then input into comparator1405, which has as an input DC reference source1406. A line failure signal, i.e., a logical high, is generated at the output1407of comparator1405if the output of summing amplifier1408is less than the DC value of reference source1406.

This circuit does not have the noise problem of the differentiator method since an all-pass filter has a flat frequency response. Operation of the circuit is complicated by the transient response of the all-pass filter. Unlike a low-pass filter, the all-pass filter responds instantaneously to a change on the input but the response is more complicated than a differentiator. The response to a step function in instantaneous but in the wrong direction; then over time it decays, crosses zero, and then ends up in the right direction. The result is that the delay is zero at either the peak or zero-crossing of the waveform and is worst case at a point half way between, at 135 degrees. But even at this point, the delay is only about 1.2 milliseconds for a circuit set up for 50 or 60 Hz.

It turns out by using empirical simulations that the all-pass is a better compromise between noise and speed than the differentiator followed by a low-pass filter. Also, a rectifying scheme works better than squaring with the all-pass approach.

In summary, the advantages of this method include: fast sensing time (0.066 cycles), good noise rejection, very simple and cheap circuit, no firmware or CPU required, and same circuit works at either 50 or 60 Hz without any modifications. The latter most feature is accomplished by actually designing it for 55 Hz, giving a negligible and equal error in the all-pass filter at either 50 or 60 Hz.

Additional modification and adaptations of the present invention will be obvious to one of ordinary skill in the art, and it is understood that the invention is not to be limited to the particular illustrative embodiments set forth herein. It is intended that the invention embrace all such modified forms as come within the scope of the following claims.

REFERENCES