Low-power redundancy for non-volatile memory

A static RAM redundancy memory for use in combination with a non-volatile memory array, such as ferroelectric RAM (FRAM), in which the power consumption of the SRAM redundancy memory is reduced. Each word of the redundancy memory includes data bit cells for storing addresses of memory cells in the FRAM array to be replaced by redundant elements, and also enable bits indicating whether redundancy is enabled for those addresses. A logical combination of the enable bits in a given word determines whether the data bit cells in that word are powered-up. As a result, the power consumption of the redundancy memory is reduced to the extent that redundancy is not enabled for segments of the FRAM array.

Not applicable.

BACKGROUND OF THE INVENTION

This invention is in the field of solid-state memory as realized in semiconductor integrated circuits. Embodiments of this invention are more specifically directed to the use of redundant memory cells to functionally replace defective memory cells in such memories.

Many modern electronic devices and systems now include substantial computational capability for controlling and managing a wide range of functions and useful applications. Many of these electronic devices and systems are now portable or handheld devices. For example, many mobile devices with significant computational capability are now available in the market, including modern mobile telephone handsets such as those commonly referred to as “smartphones”, personal digital assistants (PDAs), mobile Internet devices, tablet-based personal computers, handheld scanners and data collectors, personal navigation devices, and the like. The power consumption of the electronic circuitry in those devices and systems is therefore of great concern, as battery life is often a significant factor in the buying decision as well as in the utility of the device or system. One type of mobile devices includes implantable battery-powered medical devices, such as pacemakers, defibrillators, and the like. Battery life is of special concern in these implantable medical devices, because surgery is required to replace the battery.

Many mobile devices, including implantable medical devices, now rely on solid-state memory not only for data storage during operation, but also as non-volatile memory for storing program instructions (e.g., firmware) and for storing the results and history of previous operations and calculations. Electrically-erasable programmable read-only memory (EEPROM) is a common type of solid-state non-volatile memory, particularly EEPROM of the “flash” type. Ferroelectric random-access memory (FeRAM or FRAM) is a popular non-volatile solid-state memory technology, particularly in implantable medical devices. Modern mobile devices typically include substantial non-volatile memory capacity, often amounting to as much as one or more gigabytes.

A continuing trend in the industry, particularly as applied to mobile devices including implantable medical devices, is to realize as many system functions as possible in a single integrated circuit. As such, large-scale integrated circuits now often include one or more central processing units (CPUs), co-processor functions as desired, one or more memory resources embedded on-chip for use as program and data memory, and various input/output and control functions. Examples of these large-scale integrated circuits are often referred to as a single-chip microcomputer, or a so-called “system-on-a-chip” (SoC).

The miniaturization of these integrated circuit functions is an important design goal, whether to minimize manufacturing cost or to provide a minimum form factor. Given the substantial memory capacity now required by these computationally sophisticated, a significant portion of the overall chip area is consumed in realizing solid-state memory, particularly non-volatile solid-state memory, even in large-scale SoC implementations. As such, memory cells are often realized by minimum size transistor gates and other features, considering the relatively large number of memory cells in even modest-sized memories. The manufacturing yield of modern SoC integrated circuits is thus often dominated by manufacturing defects in the memory arrays, considering that a relatively large portion of the overall chip area is consumed by the memory arrays, and that the memory arrays are constructed of a large number of closely-packed, minimum feature size, memory cells. A defective embedded on-chip memory causes the entire SoC to be unsuitable for system use, regardless of the functionality of the remainder of the integrated circuit.

As known in the art, yield loss due to memory defects can be alleviated by the use of redundant rows or columns (or both) of memory cells associated with the memory arrays. In a general sense, if one or more memory cells in the memory array fails electrical test, the memory is remapped to access a redundant row or column of memory cells instead of the row or column of the main array containing the defective cell or cells. To the outside, the memory appears to have all cells fully functional.

U.S. Patent Application Publication No. US 2010/0211853 A1, published Aug. 19, 2010, entitled “High Reliability and Low Power Redundancy for Memory”, commonly assigned herewith and incorporated herein by this reference, describes a memory architecture with an FeRAM main array and a redundancy circuit. This publication discloses an example in which the redundancy circuit includes a static random access memory (SRAM) that stores the memory addresses to be replaced in each of multiple array segments, along with a repair enable bit that enables selection of the redundant row or column upon the redundant address matching the address of the desired memory location. A portion of FeRAM is provided for non-volatile storage of the redundant address and enable information; upon power-up, the contents of that FeRAM portion are written into the SRAM redundancy memory; the use of SRAM memory allows the redundancy decision to be made within the memory access cycle itself.

As mentioned above, power consumption of integrated circuit functions is an important concern in the design and manufacture of mobile electronic devices and systems, especially for implantable medical devices. It has been observed, however, that significant power remains being consumed by the SRAM redundancy memory, considering that this memory has at least one data word for each segment of the non-volatile array.

BRIEF SUMMARY OF THE INVENTION

Embodiments of this invention provide a non-volatile memory with redundant memory elements, and a method of operating the same, in which the power requirements of the redundancy circuit selecting the main array or redundant memory cells are reduced.

Embodiments of this invention provide such a non-volatile memory and method of operating the same that is well-suited for memory arrays arranged in multiple segments.

Embodiments of this invention provide such a non-volatile memory and method that is well-suited for memory arrays arranged into multiple partitions within each of the multiple segments.

Embodiments of this invention provide such a non-volatile memory and method that reduces vulnerability to soft-errors in the contents of the redundant memory.

Embodiments of this invention provide such a non-volatile memory and method that enables additional redundant memory resources within a given power consumption budget.

Other objects and advantages of embodiments of this invention will be apparent to those of ordinary skill in the art having reference to the following specification together with its drawings.

Embodiments of this invention may be realized by an integrated circuit containing a data array with redundant memory elements. A redundancy circuit that determines whether main memory array cells or redundant cells are accessed includes a static random access memory (SRAM) that stores the addresses to be replaced. Each data word in the redundancy SRAM includes the address to be replaced along with one or more enable bits indicating whether replacement is to be performed in the event of an address match. Power to the redundancy SRAM memory cells storing the addresses to be replaced is gated by the state of the enable bits. To the extent that redundancy is not enabled, power consumption in the redundancy SRAM is reduced.

According to another aspect of the invention, multiple redundant elements (rows and columns) are available for each main memory array segment, each associated with an address and an enable bit. The enabling of any one of the multiple redundant elements enables all redundant elements for the segment. An enable signal for the segment is generated from a “majority encoding” of the multiple enable bits. Vulnerability to soft-error failure of a single redundant enable bit in the redundancy SRAM is thus eliminated.

DETAILED DESCRIPTION OF THE INVENTION

The present invention will be described in connection with its embodiments, namely as implemented into an integrated circuit including a ferroelectric random access memory (FRAM, or FeRAM), because it is contemplated that this invention will be of particular benefit in such an application. However, it is also contemplated that this invention may be used to advantage in other memory and integrated circuit architectures beyond that described herein. Accordingly, it is to be understood that the following description is provided by way of example only, and is not intended to limit the true scope of this invention as claimed.

Modern solid-state memory is realized by various memory technologies. Static random access memory (SRAM) is now commonplace in many modern electronic systems. As is fundamental in the art, SRAM cells store data “statically”, in that the stored data state remains latched in each cell so long as power is applied to the memory. Typically, each SRAM cell is constructed as a cross-coupled pair of inverters, in a six-transistor (6-T) arrangement. Another solid-state memory type is referred to as dynamic RAM (DRAM), which realizes each memory cell as a single capacitor in combination with a single pass transistor; refresh of the stored data states is necessary in DRAM. Various types of non-volatile memory, including mask-programmable read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), ferroelectric RAM (FRAM, or FeRAM), and the like are well-known in the art. In particular, FRAM cells may be implemented in various forms, including as a one-transistor, one-capacitor (1-T, 1-C) memory cell similar to a typical DRAM cell, and also in combination with a six-transistor (6-T) SRAM cell in which one or two ferroelectric capacitors are coupled to corresponding cross-coupled nodes to retain the data state after power is removed. As will become evident from the following description and as noted above, while embodiments of this invention will be described as applied to an FRAM memory array, it is contemplated that this invention can also be beneficially implemented in connection with other solid-state memory types.

FIG. 1illustrates an example of large-scale integrated circuit10, in the form of a so-called “system-on-a-chip” (“SoC”), as now popular in many electronic systems. Integrated circuit10is a single-chip integrated circuit into which an entire computer architecture is realized. As such, in this example, integrated circuit10includes a central processing unit of microprocessor12, which is connected to system bus SBUS. Various memory resources, including non-volatile random access memory of the ferroelectric type (FRAM)18and read-only memory (ROM)19, reside on system bus SBUS and are thus accessible to microprocessor12. Typically, ROM19serves as program memory, storing the program instructions executable by microprocessor12, while FRAM18serves as data memory; in some cases, program instructions may reside in FRAM18for recall and execution by microprocessor12, considering its non-volatility. Cache memory16(such as level 1, level 2, and level 3 caches), typically implemented as SRAM provides another memory resource, and resides within microprocessor12itself and therefore does not require bus access. Other system functions are shown, in a generic sense, in integrated circuit10by way of system control14and input/output interface17.

Those skilled in the art having reference to this specification will recognize that integrated circuit10may include additional or alternative functions to those shown inFIG. 1, or may have its functions arranged according to a different architecture from that shown inFIG. 1. The architecture and functionality of integrated circuit10is thus provided only by way of example, and is not intended to limit the scope of this invention.

By way of example, embodiments of this invention will be described in this specification in connection with FRAM18. It is contemplated that those skilled in the art having reference to this specification, and the example of the application of embodiments of this invention to the memory array of FRAM18, can readily apply the invention in the construction of other types of memory, and in the construction of array-based logic and other integrated circuit functions.

FIG. 2illustrates the logical arrangement of memory array100in FRAM18, according to one example. In this case, memory array100is arranged in multiple memory segments1020through102R. In this illustrative example, each segment102consists of 80 columns and 513 rows of memory cells, where each row spans all 80 columns. Segments102having a different number of rows and columns may alternatively be realized. According to embodiments of this invention, one or more of the rows, one or more of the columns, or both rows and columns, in each segment102are reserved as redundant rows or columns for “repair” of other rows or columns in that memory segment that are defective. The manner of this “repair” is re-mapping of the address of the defective row or column to a redundant row or column. For example, each memory segment102may contain one redundant row, and one redundant column per word width.

FIG. 3illustrates the architecture of FRAM18according to an embodiment of this invention. The architecture shown inFIG. 3and described herein is described in further detail in U.S. Patent Application Publication No. US 2007/0211853 A1, commonly assigned herewith and incorporated herein by this reference. As shown inFIG. 3, FRAM18includes FRAM memory array100, arranged as described above, in combination with redundancy circuit30. Redundancy circuit30includes redundancy memory35, which in this example is implemented by SRAM; redundancy error correction circuit31; buffers32R,32C for storing corrected address results from redundancy error correction circuit31; and address matching circuit34. Redundancy memory35is arranged to include multiple redundancy words330through33R, each associated with a corresponding segment1020through1028, respectively, in FRAM data array100. For example, redundancy word331in redundancy memory35has a one-to-one correspondence with memory segment1021in FRAM data array100. This association of redundancy words33with corresponding memory segments102avoids the need to check each word in redundancy memory35for a possible match in response to a particular address; only the redundancy word33associated with the particular one of segments102indicated by the memory address need be checked.

FRAM18according to this embodiment of the invention also includes peripheral circuitry29, which refers to the usual address, clock, control, and input/output circuits typically involved in FRAM18and other memory architectures. Error correction circuit25for performing conventional error correction on data words retrieved from an addressed location of FRAM data array100, or error correction coding on data words to be written to an addressed location. As such, error correction circuit25is in communication with memory array100and with peripheral circuitry29, in the usual manner. In addition, FRAM18according to embodiments of this invention also includes redundancy control circuit27, which includes the appropriate control circuitry for storing the memory addresses to be replaced in the appropriate redundancy words33, and for setting the corresponding enable bits.

The architecture of FRAM18shown inFIG. 3and described above is, of course, provided only by way of example. FRAM18including memory array100and redundancy memory35may be constructed according to the other architectures described in the above-incorporated U.S. Patent Application Publication No. US 2007/0211853 A1, and in such other architectures as will be apparent to those skilled in the art having reference to this specification.

In its general operation, redundancy words33in redundancy memory35of FRAM18will store the row and column addresses of memory locations within corresponding segments102that are to be replaced by a redundant row or redundant column in that segment102, and corresponding enable bits within redundancy word33will be set. In this example, as shown in connection with segment102nand as described above, each segment102includes one redundant row and two redundant columns. Of course, the particular number of rows and columns, and redundant rows and columns, may vary from this example, and indeed may vary among segments102in array100. As will be described in further detail below, the addresses that require repair may be stored within one of segments102in memory array100during final test, so as to remain in non-volatile storage within FRAM18after power-down. At power up, these repair addresses are written by redundancy control circuit27into the corresponding redundancy words33in redundancy memory35, along with error correcting bits. FRAM18is then ready for access.

In this example, periphery circuit29issues a memory access request for data from a particular address in a particular segment, as indicated in a segment address value forwarded to redundancy memory35; the particular row and column address is forwarded to address matching circuit34. Redundancy circuit30causes selection of the corresponding redundancy word33, the contents of which are forwarded to redundancy ECC circuit31for verification. The contents of the selected redundancy word33(corrected if needed) are buffered in buffers32R,32C. Address matching circuit34determines whether the repair enable bit for the selected segment102is set, and if so, compares the contents of buffers32R,32C with the memory address value forwarded from peripheral circuit29. If no match is present, address matching circuit34forwards the address value from peripheral circuit29to array100for selection and access of the corresponding memory location in the desired segment102. If a match is present (with the enable bit set), address matching circuit34forwards the address of the appropriate redundant row or column (or both) to array100, so that the memory location in the redundant row or column in the desired segment102is instead accessed, effectively remapping the address of the row or column previously found to be defective. In either case, read or write access of the appropriate location within the desired segment102of array100is carried out by peripheral circuit29, along with error correction coding or detection and correction by ECC25in the usual manner.

In this architecture, redundancy memory35is constructed as CMOS SRAM, to provide relatively fast access to the desired memory locations in FRAM array100. However, as mentioned above, this SRAM implementation will involve some level of static power consumption, even though realized by way of CMOS inverters. Certain system implementations, such as implantable medical devices, are especially sensitive to power consumption, in that battery replacement is inconvenient and costly. According to embodiments of this invention, the power consumed by redundancy memory35is greatly reduced by virtue of its construction and operation, as will now be described.

FIG. 4illustrates an example of an arrangement of the contents of one of redundancy words33nstored in redundancy memory35, according to embodiments of this invention. In this example, each segment102includes one redundant row of memory cells and two redundant columns, with one redundant column associated with even-numbered columns in segment102, and the other redundant column associated with odd-numbered columns in that segment102. As such, redundancy word33nassociated with segment102nstores one row address and two column addresses, those addresses indicating the row and columns of associated segment102nthat are to be replaced with the redundant row and columns, respectively, if indicated by enable bits also stored within redundancy word33n. Redundancy word33nalso stores parity bits that result from the application of an error correction code to the data bits to be stored in the address and enable bit fields. These parity bit values are typically generated a priori, at the time of manufacture. Error correction of the contents of redundancy word33nis especially useful in embodiments of this invention that are applied to error-sensitive systems, such as implantable medical devices.

In the example shown inFIG. 4, bits within redundancy word33nare assigned as:

FieldBits in redundancy word 33nReplaced row address<0:2, 4:9>Replaced column address 1 (for even-<10, 12:16>numbered columns)Replaced column address 2 (for odd-<17:19, 21:23>numbered columns)Segment enable bits<3, 11, 20>Error correction code (parity) bits<24:29>
Of course, the particular bits assigned to particular fields can vary from that shown inFIG. 4. In this example, as will become apparent from the following description, the three enable bits are not necessarily assigned to specific fields, as the redundant row and both redundant columns are all enabled if any one of the elements is to be enabled. This arrangement eliminates the vulnerability of soft-error failure at one of the enable bits. Alternatively, at the cost of such vulnerability, one enable bit may be assigned to each of the addresses, such that the redundant row, and the redundant columns, may be separately enabled based on the state of that single enable bit (e.g., enable bit <3> in a set state enables row redundancy, even if enable bits <11> and <20> are clear because neither of the redundant columns are used).

According to embodiments of this invention, data bit cells in redundancy memory35used to store the address values and error correction code parity bits are constructed differently than are the enable bit cells used to store the enable bits. More specifically, the power supply bias applied to the data bit cells is gated by the state of the enable bit cells. In the example shown inFIG. 4, the enable bit cells are biased directly from power supply node Vdd, while the data bit cells are biased from power supply node Vdd_DBIT generated by majority logic36within redundancy circuit30. Majority logic36generates (i.e., forwards) bias voltage from power supply node Vdd responsive to the current states of enable bits <3>, <11>, <20> in redundancy word33n. According to this embodiment of the invention, the data bit cells in redundancy words33associated with segments102in which redundancy is not enabled (e.g., if none of the memory cells in its associated segment is defective) will not be biased, and thus will not consume power.

Especially as the manufacturing yield goes up (the probability of defective memory cells goes down), the power savings provided by embodiments of this invention will increase.

FIG. 5aillustrates the construction of data bit cell40das used within redundancy words33of redundancy memory35, according to an embodiment of this invention. In this example, data bit cell40dis based on a pair of cross-coupled CMOS inverters, one inverter of series-connected p-channel load transistor53pand n-channel driver transistor53n, and the other inverter of series-connected p-channel load transistor54pand n-channel transistor54n; the gates of the transistors in each inverter are connected together and to the common drain node of the transistors in the other inverter, in the usual manner. The common drain node of transistors53p,53nconstitutes storage node SNT, and the common drain node of transistors54p,54nconstitutes storage node SNB, in this example. The source nodes of load transistors53p,54pare biased from power supply node Vdd_DBIT in this embodiment of the invention, and the source nodes of driver transistors53n,54nare connected to ground reference voltage NRSC, which is a gated ground voltage as will be described in further detail below.

To reduce power consumption, data bit cell40dalso includes read buffer42and write circuit44. Read buffer42in this example is constructed as a CMOS inverter of p-channel transistor56pand n-channel transistor56nwith their drains connected in common to output node D_OUT, and their gates connected in common to storage node SNT. P-channel transistor55phas its drain connected to the source of transistor56p, and n-channel transistor55nhas its source-drain path connected between the source of transistor56nand gated ground reference voltage node NRSC. The source of transistor55pis coupled to power supply voltage VddSW through p-channel transistor59, which has its gate controlled by a majority logic signal MAJ_ as will be described in further detail below. The gates of transistors55n,55preceive complementary read word line signals WLR, WLR_, respectively. Write circuit44includes true and complementary portions, similarly constructed as one another. On the “true” side, write circuit44includes n-channel transistor57awith its drain connected to storage node SNT and its gate connected to bit line BLT, and n-channel transistor58awith its drain connected to the source of transistor57a, its source at ground Vss, and its gate receiving write word line WLW. The “complement” side of write circuit44similarly includes re-channel transistors57b,58bconnected in series between storage node SNB and ground, with the gate of transistor57bconnected to bit line BLB and the gate of transistor58breceiving write word line WLW. To further minimize power consumption, the body node (i.e., “back gate”) of each of the p-channel transistors in data bit cell40dare preferably biased to a higher voltage than the power supply voltages VddSW and Vdd_DBIT. For example, if power supply voltage Vdd is nominally at 1.5 volts, a back-gate bias of 1.9 volts to the body nodes of the p-channel transistors would further reduce the leakage through these devices.

FIG. 5cillustrates the construction of word line driver70nassociated with redundancy word33nin redundancy memory35, according to an example of embodiments of this invention. Word line driver70nincludes AND gate72, which has a first input receiving address signal _seg_ and a second input receiving the request control signal req. Address signal _seg_ may be a control signal generated by row address decode circuitry (not shown), as decoded in the conventional manner from the segment portion of the address of FRAM array100being accessed in a particular memory address cycle, and indicating, when active, that a memory address in segment102ncorresponding to redundancy word33nis being accessed. Additional decoded (or undecoded) address portions may also or instead be applied to AND gate72, as appropriate for the architecture. Request control signal req is a control signal from peripheral circuit29(FIG. 3) indicating that a memory access is desired, and enabling circuits in redundancy circuit30accordingly, and thus enables AND gate72to respond to the decoded address signal _seg_.

Request control signal req is also involved in power-switching power supply voltage VddSW, as shown inFIG. 5d. In this example, p-channel pass transistor76receives request control signal req_, and connects power supply voltage Vdd to gated power supply voltage node VddSW in response to request control signal req_ being asserted (active low). This gating of power supply voltage node VddSW enables read buffers42in each bit cell of redundancy memory35to be isolated from power supply voltage Vdd during such time as FRAM18, and thus redundancy memory35, are in standby, further reducing power consumption in this mode.

Referring back toFIG. 5c, a high logic level output from AND gate72, in this example, indicates that redundancy word33nis to be accessed for comparison against a received memory address. This active level is forwarded as an active high level on read word line WLR, and via inverter73as an active low logic level on read word line WLR_, to read buffers44in each of data bit cells40dand enable bit cells40e1through40e3. As shown inFIG. 5c, this output of AND gate72is also applied to one input of AND gate74, a second input of which receives write control signal WR. Write control signal WR in this example indicates a write cycle is to be performed by an active high level, and conversely indicates a read cycle when at a low logic level. Write word line WLW is driven active high by AND gate74in word line driver70nonly during write cycles to redundancy word33n.

Gated ground reference voltage NSRC is also produced individually for each redundancy word33n, by its corresponding word line driver70nin this example. As shown in the example ofFIG. 5c, the output of AND gate72is applied to the gate of re-channel transistor77, which has its drain at node NSRC and its source at ground (Vss). N-channel transistor78is connected in diode fashion, and in parallel with the source/drain path of transistor77, having its gate and drain at node NSRC and its source at ground. Accordingly, in response to the selection of redundancy word33nfor access in a given memory cycle (the output of AND gate72active high), transistor77is turned on and gated ground reference voltage node NSRC is biased directly to ground through transistor77. During such time as redundancy word33nis not selected, the output of AND gate72is inactive low, transistor77is turned off, and gated ground reference node NSRC is allowed to float up to a level no more than a diode voltage drop (Vtof transistor78) above ground voltage Vss. In this state, leakage current of the bit cells of redundancy word33nis further reduced in standby, while not affecting data state retention.

The operation of data bit cell40din an enabled redundancy word33nassumes that power supply voltage Vdd_DBIT is at or near power supply voltage Vdd, and control signal MAJ_ is at a low logic level to turn on transistor59, both conditions to be described below. In read cycles, read word lines WLR, WLR_ are energized to their respective active high and low levels, allowing the inverter of transistors56p,56nto output the state of data bit cell40d; in write cycles, read word lines WLR, WLR_ are held low and high, respectively, preventing power consumption through read buffer42. In write cycles, write word line WLW is energized to a high level after the desired data state is applied to bit lines BLB, BLT; transistors58a,58bare both turned on in this event, allowing the complementary logic levels at bit lines BLT, BLB to determine which of storage nodes SNT, SNB is pulled to ground, setting the state of data bit cell40d.

Data bit cell40dmay be constructed in alternative ways from that shown inFIG. 5a, of course. For example, cell40dmay be constructed as a conventional six-transistor (6-T) static memory cell, biased between the voltage at power supply node Vdd_DBIT and ground reference voltage Vss.

FIG. 5billustrates the construction of enable bit cells40e1through40e3, and of majority logic36, according to an embodiment of this invention. In this embodiment of the invention, each of enable bit cells40e1through40e3is constructed similarly as data bit cell40ddescribed above relative toFIG. 5a. To summarize, as shown inFIG. 5b, each of enable bit cells40e1through40e3includes cross-coupled inverters52T,52B, read buffer42, and write circuit44. In this example, however, inverters52T,52B are biased from power supply voltage Vdd, rather than from power supply node Vdd_DBIT. This power supply voltage Vdd (or a similar power supply voltage) is also applied to majority logic36, as shown inFIG. 5b. While not shown inFIG. 5b, each of enable bit cells40e1through40e3is biased, on the ground side, from gated ground reference NSRC as described above for data bit cell40d, and read buffers42in enable bit cells40e1through40e3is biased from switched power supply voltage VddSW.

Storage node SNT of each of enable bit cells40e1,40e2,40e3is applied to majority logic36, via lines SNT1, SNT2, SNT3, respectively. In this embodiment of the invention, lines SNT1through SNT3directly convey the state of enable bit cells40e1through40e3without requiring the energizing of read buffers42. Within majority logic36, three pairs of series-connected n-channel transistors60operate to selectively generate the voltage at power supply node Vdd_DBIT from power supply voltage Vdd, based on the majority “vote” of the states of enable bit cells40e1through40e3. In this example, transistors60a,60bhave their source-drain paths connected in series between power supply voltage Vdd and power supply node Vdd_DBIT, and their gates receiving lines SNT1, SNT3, respectively. Similarly, transistors60c,60dhave their source-drain paths connected in series between power supply voltage Vdd and power supply node Vdd_DBIT, and their gates receiving lines SNT2, SNT1, respectively. And transistors60e,60fhave their source-drain paths connected in series between power supply voltage Vdd and power supply node Vdd_DBIT, and their gates receiving lines SNT3, SNT2, respectively. Accordingly, if storage node SNT is at a high logic level (i.e., indicating that its enable bit cell40eis “set”) in any two of enable bit cells40e1,40e2,40e3, then at least one pair of transistors60will both be turned on, connecting power supply voltage Vdd to power supply node Vdd_DBIT and thus powering-up data bit cells40din that redundancy word33. Conversely, if at most one of enable bit cells40e1,40e2,40e3is set, then none of the pairs of transistors60will have both transistors on, and power supply node Vdd_DBIT will be isolated from power supply voltage Vdd; data bit cells40din that redundancy word33will thus not be powered up, and no power will be dissipated by those data bit cells40d. Majority control signal MAJ_ is generated from power supply voltage Vdd_DBIT (via an inverter as shown), and is applied to the gates of p-channel transistors59in each of data bit cells40dand enable bit cells40e1through40e3for this redundancy word33, as described above.

According to embodiments of this invention, therefore, the states of enable bit cells40e(e.g., the majority of enable bit cells40ein a given redundancy word33) determine whether the corresponding data bit cells40din the same redundancy word33are biased and thus operable. Of course, data bit cells40dmust have this power supply bias in order to store the desired memory address portions to be repaired by redundant rows and columns. It is therefore beneficial for write cycles to redundancy memory35to be relatively long cycles. More specifically, redundancy memory write cycles to each redundancy word33should be sufficiently long that the set states written into enable bit cells40ecan propagate through majority logic36, and energize power supply node Vdd_DBIT for sufficient time that data bit cells40din that redundancy word33are biased to reliably retain the written data state.

Also according to this embodiment of the invention, as discussed above, if any redundant element (row or column) is enabled for use for a given segment102, then all redundant elements for that segment102will be enabled, and all of enable bit cells40efor that redundancy circuit30will be set. In this embodiment of the invention, the majority vote scheme enforced by majority logic36allows for the possibility of a “soft” error at one of enable bit cells40e. In the case in which all of enable bit cells40e1,40e2,40e3are set, and a soft error changes the state of one of those cells to “clear”, the state of two of lines SNT1, SNT2, SNT3will still remain high, and majority logic36will still connect power supply node Vdd_DBIT to power supply voltage Vdd, maintaining power supply bias to data cells40din that redundancy word33. Conversely, if all of enable bit cells40e1,40e2,40e3are intended to be “clear”, but a soft error causes one of those cells to change state to “set”, the single “set” state on only one of lines SNT1, SNT2, SNT3will not cause power supply node Vdd_DBIT to connect to power supply voltage Vdd, and data cells40din that redundancy word33will remain powered down.

It is understood that the requirement of enabling all redundant elements for a segment102if any redundant elements are to be enabled (i.e., a “set one, set all” scheme) will cause replacement of known “good” cells in the main data array of that segment102. However, it is contemplated that segments102in array100will be constructed so that the use of a redundant memory cell rather than a main memory cell is effectively transparent to the user. In that event, the particular memory address retained within the address fields for the replacement of the otherwise “good” row or columns is not important, and may simply remain at a random or otherwise initialized value. Since the number of rows is a power of two, in this implementation, row repair will necessarily be enabled if two of the three enable bits are set; on the other hand, column repair can be disabled by storing an “out of range” address in the address field of the corresponding redundancy word33.

Alternatively, of course, other combinational logic functions may be applied to the states of enable bit cells40ein redundancy words33, as desired for the particular function to be carried out. As mentioned above, individual portions of each redundancy word33may instead have their power supply bias gated by one or more of enable bit cells40ein that redundancy word. Further in the alternative, the number of enable bit cells40emay of course vary from three, and the particular combination of that number of enable bit cells40emay differ from a simple majority vote. Furthermore, as described above in this embodiment of the invention, the biasing of data bit cells40dis performed individually for each redundancy word33. It is contemplated that this power supply bias control may be varied from this by-word approach in some implementations. It is contemplated that those skilled in the art having reference to this specification can readily derive the particular logical combination of these enable bits40e, and the granularity of control, for biasing the data bit cells40din redundancy words33according to such other alternative realization as deemed useful in a particular application.

Referring back toFIG. 3, power consumption within redundancy circuit30is further reduced by the provision of another instance of majority logic48, beyond that contained within each redundancy word33as described above. Majority logic48receives the state of enable bits40ein the contents of an accessed redundancy word33n, and generates an output signal in similar manner as majority signal MAJ_ described above relative toFIG. 5b. This output signal is applied to the gate of power p-channel transistor49, which has its source/drain path connected between gated power supply voltage node VddSW, and power supply voltage node VddSW_M. Power supply voltage node VddSW_M biases the decoding circuitry in redundancy circuit30in this embodiment of the invention, such decoding circuitry including redundancy ECC circuit31, redundancy address buffers32R,32C, and address matching circuit34. Accordingly, this decoding circuitry is only biased during the operation of redundancy circuit30, and only then in response to the majority “vote” of enable bit cells40eof the accessed redundancy word33nindicating that redundancy is properly enabled for those redundant addresses. Active and leakage power consumption are thus reduced in this decoding circuitry, during such time as the addressed segment102does not require redundancy repair.

FIG. 6illustrates an example of the architecture of redundancy control circuit27, and its interaction with redundancy memory35, according to embodiments of this invention. As illustrated inFIG. 6, redundancy memory35includes memory array35A, which includes data bit cells40dand enable bit cells40eof the SRAM type, as described above, arranged in rows and columns. Each row of data bit cells42dand enable bit cells42econstitutes an instance of redundancy words33, in this example. Redundancy memory35also includes conventional memory peripheral circuits such as row decoder35RD, write buffers35WB, read buffers35RB, and other necessary and similar circuitry (not shown). Read buffers35RB drive output lines Q, which are connected to redundancy ECC circuit31for error detection and correction, as described above relative toFIG. 3.

Redundancy control circuit27includes read/write control circuitry65, which generally includes the appropriate logic for accessing redundancy memory array35A. It is contemplated that those skilled in the art having reference to this description will be readily able to select and realize the appropriate logic and other circuitry appropriate for a particular implementation of read/write control circuitry65. In this example in which each redundancy word33is associated with a segment102of array100, and occupies a row of redundancy memory array35A, the FRAM segment address indicates the row of redundancy memory array35A to be accessed. As such, read/write control circuitry65generates and forwards FRAM segment address values to row decoder35RD via multiplexer70A to access one of redundancy words33for read or write operations.

For normal writes to redundancy memory35, read/write control circuitry65generates and forwards write enable control signal WE to write buffers35WB via multiplexer70W (control signal SCRUB being inactive for this operation, as will be described below). The contents to be written to this selected redundancy word33(including data, enable bit states, and the corresponding ECC parity bit values) are generally determined at the time of manufacture of integrated circuit10, and stored in non-volatile memory, for example in segment102R of array100. In this case, these contents are typically read from segment102R on power-up of integrated circuit10(error-corrected via ECC circuit25ofFIG. 3), and forwarded to read/write control circuitry65, which in turn forwards those values to write buffers35B on lines D_IN via multiplexer70Q (control signal SCRUB inactive). As mentioned above, write cycles to redundancy memory35should be of relatively long duration, to allow the newly-written set states of enable bits40eof redundancy word33to enable power supply bias to be applied to data bits40dof that redundancy word33, ensuring reliable storage of the addresses to be replaced. And as discussed above relative toFIG. 3, on access of a particular address location in array100, read/write control circuitry65will provide an FRAM segment address value to row decoder35RD via multiplexer70A (control signal SCRUB inactive), along with an inactive write enable level on line WE. These signals will access redundancy word33in redundancy memory array35A for the addressed segment102, in response to which read buffers35RB will provide output data on lines Q to redundancy ECC circuit31. After error correction and detection, the resulting corrected (if necessary) address and enable states stored in the accessed redundancy word are provided by redundancy ECC circuit on lines RED_ADDR/EN to buffers32R,32C (FIG. 3).

According to this embodiment of the invention, and as mentioned above, each redundancy word33includes a number of data bit cells42dfor storing parity bits generated from the data and enable portion of that redundancy word33according to an error correction code. As such, one or more errored bits in redundancy word33can be detected and, depending on the code, corrected. A typical example of such an error correction scheme applied to redundancy memory35in this example is a double-detect, single-correct coding.

According to this embodiment of the invention, the reliability of redundancy memory35is enhanced by the re-writing of corrected data into redundancy memory35upon the detection of a single-bit error. In this manner, errors in the stored redundancy information will tend not to accumulate over time. Redundancy control circuit27of the embodiment of the invention shown inFIG. 6includes the appropriate circuitry for attaining that enhanced reliability, as will now be described with reference toFIG. 6.

As mentioned above, one input of multiplexer70A receives the FRAM segment address from read/write control circuitry65, one input of multiplexer70W receives write enable signal WE from read/write control circuitry65, and one input of multiplexer70Q receives input data on lines D_IN from read/write control circuitry65. According to this embodiment of the invention, a second input of multiplexer70A receives scrub address value SCRUB_ADDR from scrub pointer register58, while a second input of multiplexer70W receives write enable signal WE_SCRB from scrub pointer register58. A second input of multiplexer70Q receives the corrected contents for an addressed redundancy word on lines Q_WB from redundancy ECC circuit31.

Scrub pointer register68contains the appropriate logic for issuing a control signal on line SCRUB, as well as for issuing a scrub address value on lines SCRUB_ADDR and the write enable signal on line WE_SCRB, in response to an indication of error from redundancy ECC circuit31. In this example, scrub pointer register68receives signal SEC from redundancy ECC circuit31, that signal indicating that a single-bit error was detected and correctable in the most recently accessed redundancy word33.

According to this embodiment of the invention, scrub pointer register68initiates a “scrub” of one of redundancy words33upon a read of that word having a single-bit correctable error. In this example, scrub pointer register68drives an active level of control signal SCRUB in response to an indication via signal SEC that the most recently accessed redundancy word33had such a single-bit error. In combination with this control signal SCRUB in this event, scrub pointer register68also issues the address of the errored redundancy word to multiplexer70A on lines SCRUB_ADDR, and an active level of write enable signal WE_SCRB to multiplexer70W. The active level of control signal SCRUB causes multiplexer70A to select the address on lines SCRUB_ADDR for application to row decoder35RD, and to apply the write enable signal on line WE_SCRB to write buffers35WB. Meanwhile, the corrected contents of the accessed redundancy word33are provided on lines Q_WE by redundancy ECC circuit31, and multiplexer70Q applies those contents to write buffers35WB in response to control signal SCRUB. In this manner, upon detection of a single-bit error, the accessed redundancy word33is re-written with the corrected contents in this embodiment of the invention. The accumulation of multiple bit (and thus uncorrectable) errors is thus prevented.

Variations on this approach can also be realized. For example, the single row “scrub” operation can be delayed until a certain number of errored accesses of that redundancy word33occur; this minimizes the performance impact of constant re-writing of redundancy data if a “hard” bit error is present in redundancy memory35. Scrub pointer register68can, in this case, include counters to maintain the appropriate error counts for the redundancy words33in array35A.

FIG. 6also illustrates signal DED issued by redundancy ECC circuit31. According to another variation or alternative, this signal DED indicates whether the most recently read contents of one of redundancy words33contains an uncorrectable error, for example two errored bits in a double-detect, single-correct ECC scheme. This signal DED may be forwarded to peripheral circuitry29or other control circuitry associated with FRAM18, in response to which one or all of redundancy words33are re-written with the contents of segment102R in similar manner as occurred on power-up, thus removing the uncorrectable errored condition.

These error correction and flush operations are optional in connection with embodiments of this invention. However, when used in combination with the power reduction approach of this invention, the utility of FRAM18in a high-reliability application is enhanced even further.

Embodiments of this invention thus provide a low power arrangement for the use of high-performance SRAM as redundancy memory. The use of high-performance SRAM, rather than FRAM or some other non-volatile memory, allows for the redundancy match decision to be performed with little or no impact on the memory access cycle time. Embodiments of this invention enable the use of such SRAM redundancy memory while mitigating the power penalty for doing so. As such, this architecture is well-suited for highly power-conscious circuits and systems, for example implantable medical devices. In addition, techniques for improving the reliability of the redundancy decision from a soft-error standpoint are provided by variations on this architecture.

While this invention has been described according to its embodiments, it is of course contemplated that modifications of, and alternatives to, these embodiments, such modifications and alternatives obtaining the advantages and benefits of this invention, will be apparent to those of ordinary skill in the art having reference to this specification and its drawings. It is contemplated that such modifications and alternatives are within the scope of this invention as subsequently claimed herein.