Semiconductor devices including resistor structures

A semiconductor device is provided including a resistor structure, the semiconductor device including a substrate having an upper surface perpendicular to a first direction; a resistor structure including a first insulating layer on the substrate, a resistor layer on the first insulating layer, and a second insulating layer on the resistor layer; and a resistor contact penetrating the second insulating layer and the resistor layer. The tilt angle of a side wall of the resistor contact with respect to the first direction varies according to a height from the substrate. The semiconductor device has a low contact resistance and a narrow variation of contact resistance.

CLAIM OF PRIORITY

This application is related to and claims priority from Korean Patent Application No. 10-2017-0080734, filed on Jun. 26, 2017, in the Korean Intellectual Property Office, the disclosure of which is hereby incorporated herein by reference in its entirety.

FIELD

The present inventive concept relates generally to semiconductor devices and, more particularly, to semiconductor devices including resistor structures.

BACKGROUND

A resistor layer of a resistor device included in a semiconductor device may be connected to a metal interconnection through a contact. Therefore, the total resistance of the resistor device is the sum of the resistance of the resistor layer itself and the resistance of the contact. The resistor layer generally needs to be thinned for reduction in size of semiconductor devices. As the resistor layer becomes thinner, the contact area between the resistor layer and the contact decreases. As a result, the contact resistance increases and the variation in the contact resistance also increases. Therefore, there is a need to reduce the contact resistance of the resistor device and the variation of the contact resistance of the resistor device.

SUMMARY

Some embodiments of the present inventive concept include semiconductor devices having a resistor structure including a low contact resistance and a narrow variation of contact resistance.

In further embodiments, a semiconductor device includes a substrate having an upper surface perpendicular to a first direction; a resistor structure including a first insulating layer on the substrate, a resistor layer on the first insulating layer, and a second insulating layer on the resistor layer; and a resistor contact penetrating the second insulating layer and the resistor layer. The tilt angle of a side wall of the resistor contact with respect to the first direction varies according to a height from the substrate.

In still further embodiments of the inventive concept, a semiconductor device includes a substrate having an upper surface perpendicular to a first direction and having a transistor area and a resistor area; a lower structure on the resistor area and the transistor area; a resistor structure on a portion of the lower structure on the resistor area and including a first insulating layer, a resistor layer on the first insulating layer, and a second insulating layer located on the resistor layer; and a resistor contact penetrating the second insulating layer and the resistor layer. A tilt angle of a side wall of the resistor contact with respect to the first direction varies according to a height from the substrate.

In some embodiments of the inventive concept, a semiconductor device includes a substrate having an upper surface perpendicular to a first direction and having a transistor area and a resistor area; a lower structure on the transistor area and the resistor area, and including a plurality of gate structures, a lower interlayer insulating layer filling spaces in between the plurality of gate structures, an active region below the gate structures on the transistor area, and a source/drain region contacting the active region; a resistor structure on a portion of the lower structure on the resistor area and including a first insulating layer, a resistor layer on the first insulating layer, and a second insulating layer on the resistor layer; an upper interlayer insulating layer covering the resistor structure and the lower structure; a resistor contact penetrating the upper interlayer insulating layer, the second insulating layer, and the resistor layer; and a source/drain contact contacting the source/drain region through the upper interlayer insulating layer and the lower interlayer insulating layer, wherein a tilt angle of a side wall of the resistor contact with respect to the first direction varies according to a height from the substrate.

DETAILED DESCRIPTION OF THE EMBODIMENTS

The inventive concept will now be discussed more fully hereinafter with reference to the accompanying drawings, in which exemplary embodiments of the inventive concept are shown. The inventive concept and methods of achieving the inventive concept will be apparent from the following exemplary embodiments that will be discussed in more detail with reference to the accompanying drawings. The embodiments of the inventive concept may, however, be embodied in different forms and should not be constructed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the inventive concept to those skilled in the art.

As used herein, the singular terms “a,” “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. As used herein, the term “and/or” includes any and all combinations of some of the associated listed items. It will be understood that when an element is referred to as being “connected” or “coupled” to another element, it may be directly connected or coupled to the other element or intervening elements may be present. It will be further understood that the terms “comprises”, “comprising,”, “includes” and/or “including”, when used herein, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of some other features, integers, steps, operations, elements, components, and/or groups thereof.

Similarly, it will be understood that when an element such as a layer, region or substrate is referred to as being “on” another element, it can be directly on the other element or intervening elements may be present. In contrast, the term “directly” means that there are no intervening elements. Additionally, the embodiments in the detailed description will be discussed with sectional views as ideal exemplary views of the inventive concept. Accordingly, shapes of the exemplary views may be modified according to manufacturing techniques and/or allowable errors. Therefore, the embodiments of the inventive concept are not limited to the specific shape illustrated in the exemplary views, but may include other shapes that may be created according to manufacturing processes.

Exemplary embodiments of aspects of the present inventive concept explained and illustrated herein include their complementary counterparts. The same reference numerals or the same reference designators denote the same elements throughout the specification.

Referring now toFIGS. 1, 2, and 3A, a perspective view, a cross-sectional view, and a plan view, respectively, of a semiconductor device according to some embodiments of the present inventive concept. As illustrated inFIGS. 1, 2, and 3A, a semiconductor device100according to some embodiments of the present inventive concept includes a substrate110, a lower structure130located on the substrate110, a resistor structure150located on the lower structure130, and a resistor contact190in contact with the resistor structure150. In some embodiments, the semiconductor device100may not include the lower structure130as illustrated, and the resistor structure150may be located directly on the substrate110without departing from the scope of the present inventive concept.

The substrate110may have an upper surface110U that is perpendicular to a first direction D1and extends in a second direction D2and a third direction D3. Hereinafter, a height from the substrate110means a distance from the upper surface110U of the substrate110in the first direction D1. The first direction D1, the second direction D2, and the third direction D3may be perpendicular to each other. The substrate110may include a semiconductor material such as a Group IV semiconductor material, a Group III-V semiconductor material, or a Group II-VI semiconductor material. The Group IV semiconductor material may include, for example, silicon (Si), germanium (Ge), or silicon (Si)-germanium (Ge). The Group III-V semiconductor material includes, for example, gallium arsenide (GaAs), indium phosphide (InP), gallium phosphide (GaP), indium arsenide (InAs), indium antimony (InSb), or indium gallium arsenide (InGaAs). The Group II-VI semiconductor material may include, for example, zinc telluride (ZnTe), or cadmium sulfide (CdS). In some embodiments, the substrate110may be a bulk wafer or an epitaxial layer.

The lower structure130may be located on the substrate110. The lower structure130may have various structures. For example, the lower structure130may include only a single layer or a single pattern. In some embodiments, the lower structure130may include a complex structure including a combination of a plurality of layers and a plurality of patterns.

The resistor structure150may be located on the lower structure130. The width of the resistor structure150in the second direction D2and the width of the resistor structure150in the third direction D3may each be determined according to a target resistance value. The cross-section of the resistor structure150, perpendicular to the first direction D1inFIG. 3A, has a rectangular shape. However, the shape and width of the cross-section of the resistor structure150may be variously modified according to the device design.

The resistor structure150may include a first insulating layer151located on the lower structure130, a resistor layer153located on the first insulating layer151, and a second insulating layer155located on the resistor layer153. In some embodiments, the first insulating layer151, the resistor layer153, and the second insulating layer155may have a substantially similar planar area.

The first insulating layer151may include, for example, an oxide, such as aluminum oxide (Al2O3) or silicon oxide (SiO2). In some embodiments, the first insulating layer151may have a thickness of about 10 Å to about 100 Å. The resistor layer153may include a metal-based material such as a metal, a conductive metal nitride, or a metal silicide. For example, the resistor layer153may include titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), tungsten (W), or tungsten silicide (WSi). The resistor layer153may have a thickness of about 10 Å to about 100 Å. The second insulating layer155may include, for example, silicon nitride (SiN). In some embodiments, the second insulating layer155may have a thickness of about 10 Å to about 100 Å.

Unlike the embodiments illustrated inFIGS. 1 and 2, in some embodiments, the resistor structure150may be located on the substrate110. In other words, a semiconductor device according to some embodiments may not include the lower structure130. Unlike the embodiments illustrated inFIGS. 1 and 2, in some embodiments, the resistor structure150may further include a third insulating layer157(seeFIG. 6B) located on the second insulating layer155. The third insulating layer157(seeFIG. 6B) may include an oxide, such as aluminum oxide (Al2O3), or silicon oxide (SiO2). In some embodiments, the third insulating layer157may have a thickness of about 10 Å to about 100 Å.

Referring toFIG. 2, the resistor contact190penetrates the second insulating layer155and the resistor layer153of the resistor structure150, and a bottom surface of the resistor contact190may contact the first insulating layer151. The resistor contact190may include a resistor contact core layer and a resistor contact barrier layer surrounding the side walls and bottom of the resistor contact core layer.

The resistor contact core layer may include a metal, a metal nitride, or an alloy. Examples of the metal are tungsten (W), copper (Cu), titanium (Ti), tantalum (Ta), ruthenium (Ru), manganese (Mn), and cobalt (Co). The metal nitride may include, for example, titanium nitride (TiN), tantalum nitride (TaN), cobalt nitride (CoN), or tungsten nitride (WN). The alloy may include cobalt tungsten phosphorus (CoWP), cobalt tungsten boron (CoWB), or cobalt tungsten boron phosphorous (CoWBP). The resistor contact barrier layer may include, for example, titanium (Ti), tantalum (Ta), titanium nitride (TiN), or tantalum nitride (TaN).

Unlike the embodiments illustrated inFIGS. 1 and 2, in some embodiments, the resistor contact190may contact the lower structure130through the first insulating layer151. In some embodiments to be explained in connection withFIG. 6Bin which the third insulating layer157(seeFIG. 6B) is further placed on the second insulating layer155, the resistor contact190may penetrate the third insulating layer157(seeFIG. 6B), the second insulating layer155, and the resistor layer153of the resistor structure150.

A semiconductor device according to some embodiments may include a plurality of resistor contacts, each being the resistor contact190. AlthoughFIGS. 1, 2, and 3Aillustrate two resistor contacts arranged in the second direction D2, the number and arrangement of the resistor contacts may vary according to design.

FIGS. 3B and 3Care plan views of semiconductor devices100according to some embodiments of the present inventive concept. Referring toFIGS. 3B and 3C, the shape of the cross-section of the resistor contact190may vary. For example, the cross-section of the resistor contact190may be circular as illustrated inFIG. 3Cor oval as illustrated inFIG. 3B. In some embodiments, the arrangement of resistor contacts, each being the resistor contact190, may be variously modified. For example, as illustrated inFIG. 3B, resistor contacts may be arranged line by line along two facing edges of the resistor structure150in the third direction D3. For example, as illustrated inFIG. 3C, resistor contacts may be arranged in two lines along each of two facing edges of the resistor structure150in the third direction D3.

FIGS. 4A, 4B, and 4Care enlarged cross sections of various modifications of the resistor contact190included in a semiconductor device according to some embodiments of the present inventive concept. Referring toFIG. 4A, a tilt angle θx of a side wall190S of the resistor contact190with respect to the first direction D1perpendicular to the upper surface110U of the substrate110may vary depending on a height Hx from the upper surface110U of the substrate110. For example, the tilt angle θx may change at a first height H1from the upper surface110U of the substrate110and a second height H2being greater than the first height H1. In some embodiments, the tilt angle θx corresponding to a portion between a lower end height HL of a lower end190L of the resistor contact190and the first height H1of the resistor contact190is a first tilt angle θ1, the tilt angle θx corresponding to a portion between the first height H1and the second height H2is a second tilt angle θ2, and the tilt angle θx corresponding to a portion between the second height H2and an upper end height HU of an upper end190U of the resistor contact190is a third tilt angle θ3. That is, the resistor contact190may include a first region R1having the first tilt angle θ1, a second region R2located on the first region R1and having the second tilt angle θ2, and a third region R3located on the second region R2and having the third tilt angle θ3.

In some embodiments, the first tilt angle θ1may be less than the second tilt angle θ2, and the second tilt angle θ2may be greater than the third tilt angle θ3. The first tilt angle θ1and the third tilt angle θ3may each be, for example, equal to or greater than about 0 degrees and less than or equal to about 20 degrees or less. In some embodiments, the first tilt angle θ1and the third tilt angle θ3are sufficiently small such that the side wall190S of the resistor contact190in the first region R1and the third region R3may be substantially parallel to the first direction D1. In some embodiments, the second tilt angle θ2may be equal to or greater than about 20 degrees and less than or equal to about 70 degrees. The side wall190S of the resistor contact190in the second region R2may not be substantially parallel to the first direction D1.

Referring to4B and4C, unlike the embodiments discussed above with respect toFIG. 4A, in some embodiments, at the boundary between the first region R1and the second region R2and the boundary between the second region R2and the third region R3, the side wall190S of the resistor contact190may have a round corner, rather than a sharp corner. In other words, the tilt angle θx of the side wall190S of the resistor contact190with respect to the first direction D1may be continuously changed depending on the height Hx from the substrate110. In this regard, the maximum points of the magnitude of the change rate d(θx)/d(Hx) of the tilt angle with respect to the height from the substrate110may be defined as the first height H1and the second height H2. In other words, when the tilt angle θx of the side wall190S of the resistor contact190with respect to the first direction D1is expressed as a function of the height Hx from the substrate110, the second derivative of the tilt angle d2(θx)/d(Hx)2at the first height H1and the second height H2may be 0. The following equations may be satisfied at the first height H1and the second height H2.

In this regard, a region from the lower end height HL of the resistor contact190to the first height H1may be defined as the first region R1, a region from the first height H1to the second height H2may be defined as the second region R2, and a region from the second height H2to the upper end height HU may be defined as the third region R3. The first tilt angle θ1, which is the tilt angle of the first region R1, may be defined as an average value of tilt angles θx of the side wall190S of the resistor contact190in the range from the lower end height HL to the first height H1of the resistor contact190. Similarly, the second tilt angle θ2, which is the tilt angle of the second region R2, may be defined as an average value of tilt angles θx of the side wall190S of the resistor contact190in the range from the first height H1to the second height H2. Similarly, the third tilt angle θ3, which is the tilt angle of the third region R3, may also be defined as an average value of the tilt angle θx of the side wall190S of the resistor contact190in the range from the second height H2to the upper end height HU. That is, the first tilt angle θ1, the second tilt angle θ2, and the third tilt angle θ3may satisfy the following equations.

Therefore, even in embodiments where the side wall190S of the resistor contact190has a round corner at the boundary between the first region R1and the second region R2and at the boundary between the second region R2and the third region R3, the resistor contact190may include the first region R1having the first tilt angle θ1, the second region R2located on the first region R1and having the second tilt angle θ2, and the third region R3located on the second region R2and having the third tilt angle θ3. In these embodiments, the first tilt angle θ1may be less than the second tilt angle θ2, and the second tilt angle θ2may be greater than the third tilt angle θ3.

Referring toFIG. 4C, a length L1of the first region R1in the first direction D1may be less than a length L3of the third region R3in the first direction D1. A length L2of the second region R2in the first direction D1may be less than the length L3of the third region R3in the first direction D1.

In some embodiments, a maximum width Wmax1of the first region R1in the second direction D2may be in a range of, for example, from about 10 nm to about 100 nm. In some embodiments, the maximum width Wmax1of the first region R1in the second direction D2perpendicular to the first direction D1may be less than a maximum width Wmax3of the third region R3in the second direction D2. The difference between the maximum width Wmax1of the first region R1in the second direction D2and a minimum width Wmin1of the first region R1in the second direction D2may be less than the difference between a maximum width Wmax2of the second region R2in the second direction D2and a minimum width Wmin2of the second region R2in the second direction D2. The difference between the maximum width Wmax2of the second region R2in the second direction D2and the minimum width Wmin2of the second region R2in the second direction D2may be greater than the difference between the maximum width Wmax3of the third region R3in the second direction D2and a minimum width Wmin3of the third region R3in the second direction D2.

FIGS. 5A, 5B, 5C, and 5Dare enlarged views to explain various modifications of the area A inFIG. 2. Referring toFIGS. 5A to 5D, the first region R1may contact the first insulating layer151. The second region R2may contact the resistor layer153. The third region R3may contact the second insulating layer155. A contact surface between the second region R2and the resistor layer153may not be parallel to the first direction D1. That is, a contact surface between the second region R2and the resistor layer153may have the second tilt angle θ2, not 0 degrees, with respect to the first direction D1. In this case, the contact surface between the second region R2and the resistor layer153increases as compared with the case where the contact surface is parallel to the first direction D1. Therefore, by obtaining a sufficient contact area between the resistor contact190and the resistor layer153, the contact resistance and the variation in the contact resistance may be reduced.

For example, when the contact surface between the second region R2and the resistor layer153is parallel to the first direction D1, the width of the second region R2in the second direction D2is maintained at about 66 nm, and a length L2of the second region R2in the first direction D1is about 4.5 nm, the contact area between the resistor contact190and the resistor layer153is about 932.6 nm2. According to some embodiments of the present inventive concept, when the length L2of the second region R2in the first direction D1is about 4.5 nm, the width of the second region R2corresponding to the first height H1in the second direction D2is about 66 nm, and the width of the second region R2corresponding to the second height H2in the second direction D2is approximately 76 nm, the contact area between the resistor contact190and the resistor layer153is about 1003.2 nm2. Therefore, the contact area between the second region R2and the resistor layer153is increased by about 7.6%. In some embodiments, the contact area between the resistor contact190and the resistor layer153may be increased by about 5% to about 15%, as compared to when the contact surface between the second region R2and the resistor layer153is perpendicular to the first direction D1.

In addition, when the tilt angle of the side wall of the resistor contact190varies according to the height, a maximum width of the resistor contact190in the second direction D2to obtain the same contact area may be less than when the tilt angle is constant regardless of the height. For example, by increasing the second tilt angle θ2to secure the contact area between the resistor contact190and the resistor layer153and reducing the third tilt angle θ3, the maximum width of the resistor contact190in the second direction D2may be reduced. Therefore, by changing the tilt angle of the resistor contact190according to the height, a sufficient contact area may be obtained without an excess increase in the size of the resistor contact190.

In terms of the height from the upper surface110U of the substrate, the first height H1may be less than a height HUR of an upper surface of the resistor layer153from the upper surface110U of the substrate, and the second height H2may be greater than the height HLR of a lower surface of the resistor layer153from the upper surface110U of the substrate. In some embodiments, as illustrated inFIG. 5A, the first height H1may be between the height HUR of the upper surface of the resistor layer153and a height HLR of the lower surface of the resistor layer153, and the second height H2may be between the height HUR of the upper surface of the resistor layer153and the height HLR of the lower surface of the resistor layer153. In some embodiments, as illustrated inFIG. 5B, the first height H1may be less than the height HLR of the lower surface of the resistor layer153, and the second height H2may be between the height HUR of the upper surface of the resistor layer153and the height HLR of the lower surface of the resistor layer153. In some embodiments, as illustrated inFIG. 5C, the first height H1may be between the height HLR of the lower surface of the resistor layer153and the height HUR of the upper surface of the resistor layer153, and the second height H2may be greater than the height HUR of the upper surface of the resistor layer153. In some embodiments, as illustrated inFIG. 5D, the first height H1may be less than the height HLR of the lower surface of the resistor layer153and the second height H2may be greater than the height HUR of the upper surface of the resistor layer153. That is, at least a portion of the side wall of the second region R2may contact the resistor layer153.

FIG. 6Ais a plan view of a semiconductor device200according to some embodiments of the present inventive concept.FIG. 6Bis a cross section taken along line BB′ and line CC′ illustrated inFIG. 6A.FIG. 6Cis a cross section taken along line DD′ and line EE′ illustrated inFIG. 6A. Referring toFIGS. 6A to 6C, the semiconductor device200according to some embodiments may include the substrate110. The substrate110may have the upper surface110U perpendicular to the first direction D1. In addition, the substrate110may include a transistor area TA and a resistor area RA.

The lower structure130may be located on the transistor area TA and the resistor area RA. The lower structure130may include an active region ACT, a device isolation layer290, a source/drain region240, a gate structure210, and a lower interlayer insulating layer220. A portion of the lower structure130located on the transistor area TA may include the active region ACT, the device isolation layer290, the source/drain region240, the gate structure210, and the lower interlayer insulating layer220. The active region ACT, the source/drain region240, and the gate structure210which are located on the transistor area TA may constitute a transistor structure. A portion of the lower structure130located on the resistor area RA may not include at least one selected from the active region ACT, the device isolation layer290, the gate structure210, the source/drain region240, and the lower interlayer insulating layer220.

The active region ACT may be located on the transistor area TA and the resistor area RA. The active region ACT may be located below the gate structure210. In some embodiments, unlike the embodiments explained in connection withFIGS. 6B and 6C, the active region ACT may be located only on the transistor area TA. That is, the active region ACT may be located only below the gate structure210located on the transistor area TA. In some embodiments, the active region ACT may be located inside the substrate110. In some embodiments, as illustrated inFIG. 6B, the active region ACT may be in the form of a pin protruding from the upper surface110U of the substrate110in the first direction D1. The active region ACT in the form of the pin may be formed by etching the substrate110or may be an epitaxial layer grown from the substrate110. The active region ACT in the form of the pin may extend in the second direction D2. In some embodiments, the lower structure130may include a plurality of active areas ACT.

The device isolation layer290may be located on each of facing side walls of the active region ACT. The device isolation layer290may be formed to have such a height that a top portion of the pinned active region ACT is exposed. The device isolation layer290may include, for example, silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof. A low-k material may include, for example, boron phospho-silicate glass (BPSG), tonen silazene (TOSZ), undoped silicate glass (USG), spin on glass (SOG), flowable oxide (FOX), tetra ethyl ortho silicate (TEOS), or high density plasma-chemical vapor deposition (HDP-CVD) oxide. In some embodiments, the device isolation layer290may include a plurality of layers. For example, the device isolation layer290may include a stressor liner and a burying insulating film.

The source/drain region240may be in contact with the active region ACT. The source/drain regions240may be located under the side walls of the gate structure210. As illustrated inFIG. 6B, the source/drain region240may be located only on the transistor area TA. In some embodiments, unlikeFIGS. 6A through 6C, the source/drain region240may be located on the transistor area TA and the resistor area RA. The source/drain regions240may include N-type or P-type impurities. The N-type impurity may include phosphorus (P) or arsenic (As). The P-type impurity may include boron (B). The source/drain region240may include a semiconductor layer that has been epitaxially grown from the active region ACT. For example, the source/drain region240may include an epitaxially grown silicon germanium (SiGe) layer, an epitaxially grown silicon (Si) layer, or an epitaxially grown silicon carbide (SiC) layer. In some embodiments, the source/drain regions240may include multiple epitaxial semiconductor layers. For example, the source/drain region240may include a silicon germanium (SiGe) layer containing a low concentration of germanium (Ge), a silicon germanium (SiGe) layer containing a high concentration of germanium (Ge), and a silicon (Si) layer. Unlike the embodiments explained in connection withFIGS. 6A to 6C, in some embodiments, the source/drain region240may be located inside the substrate110.

In some embodiments, the gate structure210may extend in the third direction D3perpendicular to the second direction D2in which the active region ACT extends. Unlike the embodiments explained in connection withFIGS. 6A to 6C, in some embodiments, the gate structure210may be located only on the transistor area TA, not on the resistor area RA. In some embodiments, the gate structure210may be located on the resistor area RA and the transistor area TA. In some embodiments, the gate structure210may be located on the active region ACT. In some embodiments, the lower structure130may include a plurality of gate structures, each being the gate structure210. The gate structure210located on the resistor area RA may be a dummy gate structure that does not constitute a transistor. In some embodiments, the gate structure210located on the resistor area RA may extend over the transistor area TA to constitute a transistor.

The gate structure210may include a gate dielectric layer211, a gate electrode213, a gate capping layer215, and a gate spacer217. The gate electrode213may extend in the third direction D3on the active region ACT. The gate dielectric layer211may be located between the active region ACT and the gate electrode213and on facing side surfaces of the gate electrode213. The gate capping layer215may be located on the gate electrode213. The gate capping layer215may cover both the gate dielectric layer211and the gate electrode213. The gate spacer217may be located on the gate dielectric layer211on each of the facing side walls of the gate electrode213. The gate spacer217may cover a side wall of the gate capping layer215. An upper end of the gate spacer217may lie at a higher level than an upper end of the gate dielectric layer211and an upper end of the gate electrode213.

The gate dielectric layer211may include silicon oxide, silicon nitride, silicon oxynitride, gallium oxide, germanium oxide, high-k dielectric, or a combination thereof. In some embodiments, the gate dielectric layer211may include an interface film and a high-k film located on the interface film. The interface film may be located between the active region ACT and a lower surface of the gate electrode213, and the high-k film may be located on the lower surface and facing side walls of the gate electrode213. That is, between the side wall of the gate electrode213and the gate spacer217, located is only the high-k film, not the interface film.

The interface film may include a low-k material having a relative dielectric constant of about 9 or less, for example, silicon oxide, silicon nitride, silicon oxynitride, gallium oxide, or germanium oxide, but a material for the interface film is not limited thereto. The interface film may include an oxide, nitride, or oxynitride of a material that constitutes the substrate110. In one embodiment, the interface film may have a thickness of about 5 Å to about 20 Å, but the thickness thereof is not limited thereto. The interface film may be formed by thermal oxidation, atomic layer deposition (ALD), chemical vapor deposition (CVD), or physical vapor deposition (PVD).

The high-k film may include a high-k material of which a relative dielectric constant is greater than that of the interface film. For example, the relative dielectric constant of the high-k material may be in the range of about 10 to about 25. The high-k film may be formed of, for example, a hafnium-based material or a zirconium-based material. For example, the high-k film may include at least one selected from hafnium oxide (HfO2), hafnium silicon oxide (HfSiO), hafnium silicon oxynitride (HfSiON), hafnium oxynitride (HfON), hafnium aluminum oxide (HfAlO), hafnium lanthanum oxide (HfLaO), zirconium oxide (ZrO2), zirconium silicon oxide (ZrSiO), or the like. In addition, the material for forming the high-k film is not limited to the hafnium-based material or the zirconium-based material. For example, the high-k film may include other materials, for example, lanthanum oxide (La2O3), lanthanum aluminum oxide (LaAlO3), tantalum oxide (Ta2O5), titanium oxide (TiO2), strontium titanium oxide (SrTiO3), yttrium oxide (Y2O3), or aluminum oxide (Al2O3). However, the material constituting the high-k film is not limited to these materials. The high-k film may be formed by an ALD process, a CVD process, or a PVD process. In one embodiment, the high-k film may have a thickness of about 10 Å to about 40 Å. However, the thickness of the high-k film is not limited thereto.

The gate electrode213may include at least one metal selected from titanium (Ti), tantalum (Ta), aluminum (Al), tungsten (W), ruthenium (Ru), niobium (Ni), molybdenum (Mo), hafnium (Hf), nickel (Ni), cobalt (Co), platinum (Pt), and palladium (Pd); a metal nitride containing at least one metal; a carbon-doped metal; or a carbon-doped metal compound, such as a carbon-doped metal nitride.

In some embodiments, the gate electrode213may include a plurality of films. The gate electrode213may include, for example, a work-function control layer and a gap-fill metal layer that fills a space above the work-function control layer. The work-function control layer may include an aluminum (Al) compound including titanium (Ti) or tantalum (Ta). For example, the work-function control layer may include titanium aluminum carbide (TiAlC), titanium aluminum nitride (TiAlN), titanium aluminum carbonitride (TiAlC—N), titanium aluminum (TiAl), tantalum aluminum carbide (TaAlC), tantalum aluminum nitride (TaAlN), tantalum aluminum carbonitride (TaAlC—N), tantalum aluminum (TaAl), or a combination thereof. The work-function controlling layer may include molybdenum (Mo), palladium (Pd), ruthenium (Ru), platinum (Pt), titanium nitride (TiN), tungsten nitride (WN), tantalum nitride (TaN), iridium (Ir), tantalum carbide (TaC), ruthenium nitride (RuN), molybdenum nitride (MoN), or combinations thereof. The gap-fill metal layer may include, for example, a metal such as tungsten (W) or aluminum (Al), a metal silicide, a metal nitride such as titanium nitride (TiN), tantalum nitride (TaN), or a combination thereof.

As another example, the gate electrode213may have a structure in which a metal nitride layer, a metal layer, a conductive capping layer, and a gap-fill metal layer are sequentially stacked. The conductive capping layer may include a metal nitride, such as titanium nitride (TiN) or tantalum nitride (TaN), or a combination thereof, but a material for the conductive capping layer is not limited thereto.

The gate capping layer215and the gate spacer217may each include, for example, a silicon nitride film, a silicon oxynitride film, a silicon oxynitride film containing carbon, or a composite film thereof. In some embodiments, the gate spacer217may further have an air gap or a low-k film therein. The height of an upper surface of the lower interlayer insulating layer220from the substrate110may be the same as the height of the upper surface of the gate structure210from the substrate110. That is, the height of the upper surface of the lower interlayer insulating layer220from the substrate110may be the same as the height of an upper surface of the gate capping layer215from the substrate110and the height of an upper surface of the gate spacer217from the substrate110. Accordingly, the upper surface of the lower interlayer insulating layer220, the upper surface of the gate capping layer215, and the upper surface of the gate spacer217may constitute a co-planar surface parallel to the upper surface110U of the substrate110.

The lower interlayer insulating layer220may contact side walls of the gate structure210. When the semiconductor device200includes a plurality of gate structures, each being the gate structure210, the lower interlayer insulating layer220may fill a space between the plurality of gate structures210. The lower interlayer insulating layer220may include a silicon oxide film such as fluoro silicate glass (FSG) or TEOS, but embodiments of the present inventive concept is not limited thereto.

The resistor structure150may be located on a portion of the lower structure130on the resistor area RA. The resistor structure150may include the first insulating layer151, the resistor layer153, the second insulating layer155, and the third insulating layer157. Respective layers included in the resistor structure150are the same as described in connection withFIGS. 1 to 3C.

An upper interlayer insulating layer230may cover the resistor structure150and the lower structure130. The upper interlayer insulating layer230may cover the upper surface of the gate structure210, an upper surface of an lower interlayer insulating layer220, and the upper surface and side walls of the resistor structure150. The upper interlayer insulating layer230may be located in the transistor area TA and the resistor area RA. For example, like the lower interlayer insulating layer220, the upper interlayer insulating layer230may include, for example, a film of silicon oxide, such as FSG or TEOS, but embodiments of the present inventive concept are not limited thereto.

The resistor contact190penetrating the upper interlayer insulating layer230, the third insulating layer157, the second insulating layer155, and the resistor layer153may be located on the resistor area RA. In some embodiments, the resistor contact190may also pass through the first insulating layer151. The tilt angle of the side wall of the resistor contact190with respect to the first direction D1perpendicular to the substrate110may vary according to the height from the substrate110. The detailed shape of the resistor contact190is the same as that described with reference toFIGS. 1 to 5D.

The source/drain contact250on the transistor area TA may penetrate the upper interlayer insulating layer230and the lower interlayer insulating layer220and contact the source/drain region240. A cross-section of the source/drain contact250perpendicular to the first direction D1is not limited to a circular shape and may have various other shapes. The source/drain contact250may include a source/drain contact core layer and a source/drain contact barrier layer surrounding the side walls and bottom of the source/drain contact core layer. The source/drain contact core layer may include a metal, a metal nitride, or an alloy. Examples of the metal are tungsten (W), copper (Cu), titanium (Ti), tantalum (Ta), ruthenium (Ru), manganese (Mn), and cobalt (Co). The metal nitride may include, for example, titanium nitride (TiN), tantalum nitride (TaN), cobalt nitride (CoN), or tungsten nitride (WN). The alloy may include cobalt tungsten phosphorus (CoWP), cobalt tungsten boron (CoWB), or cobalt tungsten boron phosphorous (CoWBP). The source/drain contact barrier layer may include, for example, titanium (Ti), tantalum (Ta), titanium nitride (TiN), or tantalum nitride (TaN).

In some embodiments, a metal silicide layer may be located between the source/drain contact250and the source/drain region240. The silicide layer may include a metal silicide formed by reacting a material for the source/drain contact core layer and the source/drain region240or formed by reacting a separate metal material with the source/drain region240. The silicide layer may include, for example, titanium silicide (TiSi).

Referring toFIG. 6C, in some embodiments, on the transistor area TA, a gate contact270may penetrate the upper interlayer insulating layer230and the gate capping layer215and contact the gate electrode213. The gate contact270may include a gate contact core layer and a gate contact barrier layer surrounding the side walls and bottom of the gate contact core layer. The gate contact core layer may include a metal, a metal nitride, or an alloy. Examples of the metal are tungsten (W), copper (Cu), titanium (Ti), tantalum (Ta), ruthenium (Ru), manganese (Mn), and cobalt (Co). The metal nitride may include, for example, titanium nitride (TiN), tantalum nitride (TaN), cobalt nitride (CoN), or tungsten nitride (WN). The alloy may include cobalt tungsten phosphorus (CoWP), cobalt tungsten boron (CoWB), or cobalt tungsten boron phosphorous (CoWBP). The gate contact barrier layer may include, for example, titanium (Ti), tantalum (Ta), titanium nitride (TiN), or tantalum nitride (TaN).

FIG. 7is an enlarged cross section of the resistor contact190and the source/drain contact250included in a semiconductor device according to some embodiments of the present inventive concept.

Referring toFIG. 7, when the tilt angle of the side wall of the resistor contact190with respect to the first direction D1is changed at the first height H1from the substrate110and the second height H2higher than the first height H1, the tilt angle of the side wall of the source/drain contact250with respect to the first direction D1may not be changed at the first height H1and the second height H2. In some embodiments, the tilt angle of the side wall of the source/drain contact250with respect to the first direction D1may be constant regardless of the height from the substrate110.

In some embodiments, a height HUT of the upper end of the source/drain contact250from the substrate110may be the same as the height HU of the upper surface of the resistor contact190from the substrate110. A height HLT of the lower end of the source/drain contact250from the substrate110may be lower than the height HL of the lower end of the resistor contact190from the substrate110.

FIGS. 8A to 8Dare cross sections illustrating processing steps in the fabrication of a semiconductor device according to some embodiments of the present inventive concept.FIGS. 9A to 9Care enlarged cross sections to explain a process of etching a resistor contact hole in a fabrication process of a semiconductor device according to some embodiments of the present inventive concept.

Referring toFIGS. 8A and 6C, the active region ACT is formed on the substrate110having the transistor area TA and the resistor area RA. The active region ACT may be pin-shaped. The active region ACT in the shape of pin may be formed by forming an epitaxial layer on the substrate110and patterning the same. In some embodiments, the active area ACT in the shape of pin may be formed by patterning the substrate110to form a trench (not shown) defining a pin-shaped active area.

A device isolation layer290may be formed. First, the trench is filled with an insulating material and then planarized. Next, a portion of the insulating material filling the trench is removed to expose the top of the trench. Accordingly, the upper portion of the active region ACT may protrude from the device isolation layer290.

Next, the gate structure210is formed on the substrate110. In some embodiments, the gate structure210may be formed by a replacement gate method. For example, a sacrificial gate pattern (not shown) is formed, and then, the gate spacer217is formed on the side walls of the sacrificial gate pattern. Next, the lower interlayer insulating layer220covering the side wall of the gate spacer217is formed. Thereafter, the sacrificial gate pattern may be removed. Next, the resultant space generated due to the removal of the sacrificial gate pattern is filled with the gate dielectric layer211, the gate electrode213, and the gate capping layer215, thereby forming the gate structure210.

The source/drain regions240may be formed under the side walls of the gate structure210on the substrate110. In some embodiments, after the sacrificial gate pattern is formed and before the gate structure210is formed, the source/drain regions240may be formed. For example, a portion of the substrate110below the side walls of the sacrificial gate pattern is removed to form a recessed region, and an epitaxial layer containing impurities is grown in the recessed region to form the source/drain region240. Alternatively, impurities may be implanted into the substrate110to form the source/drain regions240. After the source/drain region240is formed, the lower interlayer insulating layer220and the gate structure210may be formed.

Next, the lower interlayer insulating layer220covering the side walls of the gate structure210may be formed. The lower interlayer insulating layer220may be deposited by, for example, chemical vapor deposition (CVD) or plasma enhanced CVD (PECVD).

Referring toFIG. 8B, the resistor structure150is formed. The resistor structure150may be formed by sequentially depositing the first insulating layer151, the resistor layer153, the second insulating layer155, and the third insulating layer157and then patterning them. The first insulating layer151and the third insulating layer157may be deposited by atomic layer deposition (ALD), for example. The second insulating layer155and the resistor layer153may be deposited by, for example, PVD, CVD, or ALD. The patterning may be performed using a lithographic process.

Referring toFIG. 8C, formed is the upper interlayer insulating layer230which covers the upper surface and side walls of the resistor structure150, the upper surface of the gate structure210, and the upper surface of the lower interlayer insulating layer220. The upper interlayer insulating layer230may be deposited by, for example, CVD or PECVD.

After forming the upper interlayer insulating layer230, a resistor contact hole190H, a source/drain contact hole250H, and a gate contact hole (not shown) are formed. Referring toFIG. 9A, after a photoresist mask (not shown) is formed on the upper interlayer insulating layer230, a first etching process is performed on the resultant structure to pattern the upper interlayer insulating layer230, the third insulating layer157, and the second insulating layer155, thereby forming the resistor contact hole190H. The first etching process may be a dry etching process. The first etching process may be a process in which the etch selectivity of the second insulating layer155with respect to the resistor layer153is low. Accordingly, a part of the upper surface of the resistor layer153may be etched by the first etching process. That is, a lower portion190HL of the resistor contact hole190H may expose the resistor layer153. In some embodiments, unlike the embodiments discussed above with respect toFIG. 9A, the resistor contact hole190H formed by the first etching process may not pass through the second insulating layer155. That is, the lower portion190HL of the resistor contact hole may expose the second insulating layer155.

Referring toFIG. 9B, a second etching process is performed in which the resistor layer153is etched by using, as a mask, the second insulating layer155which is formed by the patterning. The second etching process may be a dry etching process. The second etching process may be performed by using an etching material having a low chemical reactivity with a material that constitutes the resistor layer153. That is, in the second etching process, the resistor layer153may be etched by physical collision with etching materials. For example, when the resistor layer153is titanium nitride (TiN), fluoroform (CHF3) may be used as an etch gas. In the second etching process, due to the collision, particles constituting the resistor layer153are separated from the lower portion190HL of the resistor contact hole190H, and then deposited on a side wall190HS of the resistor contact hole190H. Due to the side wall re-deposition phenomenon, an angle formed by the side wall190HS of the resistor contact hole190H and the first direction D1being perpendicular to the substrate110is changed where the resistor contact hole190H contacts the resistor layer153.

Referring toFIG. 9C, the second etching process further proceeds so that the lower portion190HL of the resistor contact hole190H exposes the first insulating layer151. The first insulating layer151is etched by using the patterned resistor layer153as an etch mask. From among particles separated from the lower portion190HL of the resistor contact hole190H, the amount of particles that are re-deposited on the side wall of the resistor contact hole190H may be small. This may be due to the fact that a chemical reactivity between a material constituting the first insulating layer151and an etching material is different from a chemical reactivity between the material constituting the resistor layer153and an etching material. Accordingly, the angle formed by the side wall190HS of the resistor contact hole190H and the first direction D1perpendicular to the substrate110may be changed where the resistor contact hole190H contacts the first insulating layer151. The second etching process may be performed until the lower portion190HL of the resistor contact hole190H exposes the first insulating layer151. In some embodiments, as illustrated inFIG. 8C, the second etching process may be finished when the resistor contact hole190H penetrates the first insulating layer151to expose the lower interlayer insulating layer220.

According to the etched depth of the resistor contact hole190H when the first etching process is finished, the amount of material re-deposited at the side wall190HS of the resistor contact hole190H during the second etching process, and the etched depth of the resistor contact hole190H when the second etching process is finished, as described in connection withFIGS. 5A through 5D, the first height111and the second height H2at which the tilt angle of the side wall of the resistor contact190are changed may each vary.

The source/drain contact holes250H and the gate contact holes (not shown) may be formed in a separate process from the resistor contact holes190H, or may be formed together through the same process. Even when the source/drain contact hole250H and the resistor contact hole190H are formed in the same process, the tilt angle of the side wall of the source/drain contact hole250H with respect to the first direction D1may be constant regardless of the height from the substrate110. This is because, during the second etching process, in source/drain contact holes250H, the side wall re-deposition does not occur or even when the side wall re-deposition does occur, the amount of material re-deposited at the side wall may be constant regardless of the height from the substrate110. That is, since a material or structure to be etched to form the source/drain contact hole250H is different from a material or structure to be etched to form the resistor contact hole190H, the shape of the source/drain contact hole250H is different from the shape of the resistor contact hole190H. In some embodiments, the tilt angle of the side wall of the source/drain contact hole250H with respect to the first direction D1may vary according to the height from the substrate110, but at the first height H1(seeFIG. 7) and the second height H2(seeFIG. 7) at which the tilt angle of the side wall of the resistor contact190is changed, the tilt angle of the side wall of the source/drain contact hole250H with respect to the first direction D1may not be changed.

The source/drain contact hole250H may extend through the upper interlayer insulating layer230and the lower interlayer insulating layer220to expose the source/drain region240. In some embodiments, a gate contact hole may be formed through the upper interlayer insulating layer230and the gate capping layer215to expose the gate electrode213.

Referring toFIG. 8D, formed is a barrier layer310conformally covering the resistor contact hole190H, the source/drain contact hole250H, and the upper surface of the upper interlayer insulating layer230. A core layer320covering the barrier layer310and filling the source/drain contact hole250H and the resistor contact hole190H is formed. Thereafter, so that the upper interlayer insulating layer230is exposed, a portion of the core layer320and a portion of the barrier layer310may be removed to form the source/drain contact250and the resistor contact190. In some embodiments for forming a gate contact hole, the barrier layer310and the core layer320are formed even on a gate contact hole, and then, a portion of the barrier layer310and a portion of the barrier layer310may be removed so that the upper interlayer insulating layer230is exposed, thereby forming the gate contact270.

FIG. 10is a block diagram of an electronic system1000according to some embodiments of the present inventive concept.

Referring toFIG. 10, the electronic system1000includes a controller1010, an input/output device1020, a memory1030, and an interface1040, which are interconnected to one another through a bus1050.

The controller1010may include at least one of a microprocessor, a digital signal processor, or a processing device similar to these. The input/output device1020may include at least one of a keypad, a keyboard, and a display. The memory1030may be used to store instructions executed by the controller1010. For example, the memory1030may be used to store user data.

The electronic system1000may constitute a wireless communication device, or a device capable of transmitting and/or receiving information under a wireless environment. In the electronic system1000, the interface1040may be configured as a wireless interface for transmitting/receiving data through the wireless communication network. The interface1040may include an antenna and/or a wireless transceiver. In some embodiments, the electronic system1000may be used in a communication interface protocol of a third-generation communication system. Examples of the third-generation communication system include code division multiple access (CDMA), global system for mobile communications (GSM), north american digital cellular (NADC), extended-time division multiple access (E-TDMA), and/or wide band code division multiple access (WCDMA). The electronic system1000includes at least one of the semiconductor devices described in connection withFIGS. 1 to 9C, and semiconductor devices which are manufactured by using various methods obtained by changing the method according to some embodiments of the present inventive concept within the scope of the present inventive concept.