System and method for I/O ESD protection with polysilicon regions fabricated by processes for making core transistors

A system and method for electrostatic discharge protection. The system includes a first transistor coupled to a first system and including a first gate, a first dielectric layer located between the first gate and a first substrate, a first source, and a first drain. The first system includes or is coupled to a core transistor, and the core transistor includes a second gate, a second dielectric layer located between the second gate and a second substrate, a second source, and a second drain. The first transistor is selected from a plurality of transistors, and the plurality of transistors include a plurality of gate regions, a plurality of source regions, and a plurality of drain regions. Each of the plurality of gate regions intersects a polysilicon region.

CROSS-REFERENCES TO RELATED APPLICATIONS

This application claims priority to Chinese Patent Application No. 200610027589.X, filed Jun. 12, 2006, commonly assigned, incorporated by reference herein for all purposes.

This application is related to U.S. patent application Ser. No. 11/517,546, filed Sep. 6, 2006, commonly assigned, incorporated by reference herein for all purposes.

Not Applicable

Not Applicable

BACKGROUND OF THE INVENTION

The present invention is directed to integrated circuits. More particularly, the invention provides a system and method for electrostatic discharge (ESD) protection with polysilicon regions fabricated by processes for making core transistors. Merely by way of example, the invention has been applied to input/output (I/O) devices. But it would be recognized that the invention has a much broader range of applicability.

Integrated circuits or “ICs” have evolved from a handful of interconnected devices fabricated on a single chip of silicon to millions of devices. Current ICs provide performance and complexity far beyond what was originally imagined. In order to achieve improvements in complexity and circuit density (i.e., the number of devices capable of being packed onto a given chip area), the size of the smallest device feature, also known as the device “geometry”, has become smaller with each generation of ICs. Semiconductor devices are now being fabricated with features less than a quarter of a micron across.

Increasing circuit density has not only improved the complexity and performance of ICs but has also provided lower cost parts to the consumer. An IC fabrication facility can cost hundreds of millions, or even billions, of dollars. Each fabrication facility will have a certain throughput of wafers, and each wafer will have a certain number of ICs on it. Therefore, by making the individual devices of an IC smaller, more devices may be fabricated on each wafer, thus increasing the output of the fabrication facility. Making devices smaller is very challenging, as a given process and/or device layout often work down to only a certain feature size. An example of such a limit is the ESD protection provided by I/O transistors. An effective protection often requires lowering breakdown voltages of the I/O transistors, but reducing the breakdown voltages can be difficult. Conventionally, an ESD implant has been used for adjusting the breakdown voltages, but the ESD implant often increases fabrication complexity with limited effectiveness.

From the above, it is seen that an improved technique for ESD protection is desired.

BRIEF SUMMARY OF THE INVENTION

The present invention is directed to integrated circuits. More particularly, the invention provides a system and method for electrostatic discharge (ESD) protection with polysilicon regions fabricated by processes for making core transistors. Merely by way of example, the invention has been applied to input/output (I/O) devices. But it would be recognized that the invention has a much broader range of applicability.

In a specific embodiment, the invention provides a system for electrostatic discharge protection. The system includes a first transistor coupled to a first system and including a first gate, a first dielectric layer located between the first gate and a first substrate, a first source, and a first drain. For example, the system includes a plurality of pairs of transistors, and each pair of transistors includes an NMOS transistor and a PMOS transistor. The first system includes or is coupled to a core transistor. For example, the first system includes a core transistor. In another example, the first system includes an I/O transistor that is coupled to a core transistor. In yet another example, the first system includes a core transistor that is coupled to another core transistor. The core transistor includes a second gate, a second dielectric layer located between the second gate and a second substrate, a second source, and a second drain. The first transistor is selected from a plurality of transistors, and the plurality of transistors include a plurality of gate regions, a plurality of source regions, and a plurality of drain regions. Each of the plurality of gate regions intersects a polysilicon region. The polysilicon region is separated from the first substrate by a third dielectric layer, and at least a part of the polysilicon region is located on an active area. The polysilicon region is adjacent to a first doped region and a second doped region, and the first doped region and the second doped region are associated with opposite charge polarities. For example, the first doped region is a heavily doped region, such as an N+ region. In another example, the first doped region is a LDD region. In yet another example, the second doped region is a pocked implant region. The second dielectric layer and the third dielectric layer are associated with the same composition and the same thickness, and the second gate and the polysilicon region are associated with the same composition and the same thickness. For example, the second drain includes a third doped region and a fourth doped region, and the third doped region and the fourth doped region are associated with opposite charge polarities. The first doped region and the third doped region are associated with the same doping profile, and the second doped region and the fourth doped region are associated with the same doping profile.

According to another embodiment, a system for electrostatic discharge protection includes a first transistor coupled to a first system and including a first gate, a first dielectric layer located between the first gate and a first substrate, a first source, and a first drain. For example, the system includes a plurality of pairs of transistors, and each pair of transistors includes an NMOS transistor and a PMOS transistor. The first system includes or is coupled to a core transistor. For example, the first system includes a core transistor. In another example, the first system includes an I/O transistor that is coupled to a core transistor. In yet another example, the first system includes a core transistor that is coupled to another core transistor. The core transistor includes a second gate, a second dielectric layer located between the second gate and a second substrate, a second source, and a second drain. The first transistor is selected from a plurality of transistors, and the plurality of transistors includes a plurality of gate regions, a plurality of source regions, and a plurality of drain regions. The first substrate is separated from a first plurality of polysilicon regions by a first plurality of dielectric layers, and at least a part of each of the first plurality of polysilicon regions is located on an active area. The first plurality of polysilicon regions is not in direct contact with each other. Each of the first plurality of polysilicon regions is adjacent to a first doped region and a second doped region, and the first doped region and the second doped region are associated with opposite charge polarities. For example, the first doped region is a heavily doped region, such as an N+ region. In another example, the first doped region is a LDD region. In yet another example, the second doped region is a pocked implant region. The second dielectric layer and the first plurality of dielectric layers are associated with the same composition and the same thickness, and the second gate and the first plurality of polysilicon regions are associated with the same composition and the same thickness. For example, the second drain includes a third doped region and a fourth doped region, and the third doped region and the fourth doped region are associated with opposite charge polarities. The first doped region and the third doped region are associated with the same doping profile, and the second doped region and the fourth doped region are associated with the same doping profile.

According to yet another embodiment, a system for electrostatic discharge protection includes a first transistor coupled to a first system and including a first gate, a first dielectric layer located between the first gate and a first substrate, a first source, and a first drain. For example, the system includes a plurality of pairs of transistors, and each pair of transistors includes an NMOS transistor and a PMOS transistor. The first system includes or is coupled to a core transistor. For example, the first system includes a core transistor. In another example, the first system includes an I/O transistor that is coupled to a core transistor. In yet another example, the first system includes a core transistor that is coupled to another core transistor. The first system includes or is coupled to a core transistor, and the core transistor includes a second gate, a second dielectric layer located between the second gate and a second substrate, a second source, and a second drain. The first transistor is selected from a plurality of transistors, and the plurality of transistors includes a plurality of gate regions, a plurality of source regions, and a plurality of drain regions. The first substrate is separated from a plurality of polysilicon regions by a plurality of dielectric layers, and the plurality of polysilicon regions is on one of the plurality of drain regions or one of the plurality of source regions. The plurality of polysilicon regions is not in direct contact with each other, and each of the plurality of polysilicon regions is not in direct contact with anyone of the plurality of gate regions. Each of the plurality of polysilicon regions is adjacent to a first doped region and a second doped region, and the first doped region and the second doped region are associated with opposite charge polarities. For example, the first doped region is a heavily doped region, such as an N+ region. In another example, the first doped region is a LDD region. In yet another example, the second doped region is a pocked implant region. The second dielectric layer and the plurality of dielectric layers are associated with the same composition and the same thickness, and the second gate and the plurality of polysilicon regions are associated with the same composition and the same thickness. For example, the second drain includes a third doped region and a fourth doped region, and the third doped region and the fourth doped region are associated with opposite charge polarities. The first doped region and the third doped region are associated with the same doping profile, and the second doped region and the fourth doped region are associated with the same doping profile.

Many benefits are achieved by way of the present invention over conventional techniques. For example, the present technique provides an easy to use system and method. According to certain embodiments, the system and method are compatible with conventional technology. Some embodiments of the present invention improve the I/O ESD protection technique. For example, the junction breakdown voltages of MOS transistors are significantly lowered. In another example, the I/O transistors can turn on junction breakdown and thus prevent or reduce damages for self-protection from ESD stress. Certain embodiments of the present invention can effectively delay the time when the ESD stress current reaches the gate regions. Some embodiments of the present invention comply with the ESD design rule. For example, to dissipate significant heat generated by high-density ESD current, the ESD design rule often allows relatively large spacing between the gate regions and drain contacts. In another example, the polysilicon regions can be inserted to the drain regions of the I/O transistors in order to increase lengths of the current paths and raise the drain resistance without violating the ESD design rule. Certain embodiments of the present invention provide junction doping profiles between heavily doped regions and pocket implant regions related to floating and/or biased polysilicon regions, which are steeper than junction doping profiles between heavily doped regions and pocket implant regions for I/O transistors. For example, the heavily doped regions and pocket implant regions related to floating and/or biased polysilicon regions are made with the same implant processes as ones used for making the heavily doped regions and pocket implant regions for core transistors. Some embodiments of the present invention provide junction doping profiles between LDD regions and pocket implant regions related to floating and/or biased polysilicon regions, which are steeper than junction doping profiles between LDD regions and pocket implant regions for I/O transistors. For example, the LDD regions and pocket implant regions related to floating and/or biased polysilicon regions are made with the same implant processes as ones used for making the LDD regions and pocket implant regions for core transistors. Certain embodiments of the present invention make junction breakdown voltages related to floating and/or biased polysilicon regions significantly lower than junction breakdown voltages of conventional I/O transistors. When an ESD event occurs, the lower junction breakdown voltages allow turning on the junction breakdown more quickly; therefore the I/O transistors can be protected from ESD damage more effectively. Depending upon the embodiment, one or more of these benefits may be achieved. These and other benefits will be described in more detail throughout the present specification and more particularly below.

DETAILED DESCRIPTION OF THE INVENTION

The present invention is directed to integrated circuits. More particularly, the invention provides a system and method for electrostatic discharge (ESD) protection with polysilicon regions fabricated by processes for making core transistors. Merely by way of example, the invention has been applied to input/output (I/O) devices. But it would be recognized that the invention has a much broader range of applicability.

FIG. 1is a simplified conventional system for electrostatic discharge protection. The system1100includes gate regions1110, source regions1120, drain regions1130, an active area1150, and a polysilicon region1160. The gate regions1110, the source regions1120, and the drain regions1130are used to form I/O transistors in the active area1150. The gate regions are electrically shorted to each other by the polysilicon region1160, and the polysilicon region1160is located completely outside the active area1150.

FIG. 2is a simplified system for electrostatic discharge protection according to yet another embodiment of the present invention. This diagram is merely an example, which should not unduly limit the scope of the claims. One of ordinary skill in the art would recognize many variations, alternatives, and modifications. The system1200includes a PMOS transistor1210and an NMOS transistor1220. The source of the PMOS transistor1210is biased to a voltage level VDD, and the source of the NMOS transistor1220is biased to a voltage level VSS. The drain of the PMOS transistor1210and the drain of the NMOS transistor1220are connected to an I/O pad1230, and the gate of the PMOS transistor1210and the gate of the NMOS transistor1220are connected to an internal system1240. For example, the internal system1240is protected by the system1200. In another example, the internal system1240includes one or more core transistors and/or is coupled to one or more core transistors. The PMOS transistor1210represents one or more I/O transistors and the NMOS transistor1220represents one or more I/O transistors as shown inFIGS. 3,4,5,6,7(A) and (B),8(A),8(B),8(C),9(A),9(B),9(C), and/or9(D). For example, the system1200includes one or more pairs of I/O transistors, and each pair of I/O transistors includes an NMOS transistor and a PMOS transistor.

FIG. 3is a simplified system for electrostatic discharge protection according to an embodiment of the present invention. This diagram is merely an example, which should not unduly limit the scope of the claims. One of ordinary skill in the art would recognize many variations, alternatives, and modifications. The system100includes the following components:

Although the above has been shown using a selected group of components for the system100, there can be many alternatives, modifications, and variations. For example, some of the components may be expanded and/or combined. Other components may be inserted to those noted above. Depending upon the embodiment, the arrangement of components may be interchanged with others replaced. For example, the I/O transistors in the active area150are PMOS transistors. Further details of these components are found throughout the present specification and more particularly below.

The gate regions110, the source regions120, and the drain regions130are used to form I/O transistors in the active area150. For example, the active area150includes the source regions120and the drain regions130. In another example, each of the source regions120includes a doped region, and each of the drain regions130includes a doped region. In yet another example, the I/O transistors in the active area150are NMOS transistors. As shown inFIG. 2, the polysilicon region140intersects the gate regions110. The gate regions110are electrically connected to the polysilicon region140. In one embodiment, the polysilicon region140has the same voltage potential as the gate regions110. In another embodiment, the polysilicon region140surrounds the source regions120and the drain regions130. For example, the polysilicon region140is partially or completely located within the active area150. In another example, the gate regions110are electrically shorted to each other by another polysilicon region located outside the active area150.

FIG. 4is a simplified cross-section for the system100for electrostatic discharge protection according to an embodiment of the present invention. This diagram is merely an example, which should not unduly limit the scope of the claims. One of ordinary skill in the art would recognize many variations, alternatives, and modifications. As shown inFIG. 4, the active area150is isolated by shallow trench isolation (STI) regions210. For example, in the top view, the polysilicon region140is partially located within the active area150for the I/O transistors. Additionally, the system100also includes a substrate160and a dielectric layer170. The substrate160includes the active area150, and is separated from the polysilicon region140by the dielectric layer170. For example, the dielectric layer170includes silicon oxide.

In one embodiment, the substrate160is doped to p-type. The source regions120and the drain regions130include N+ regions. For example, the substrate160also includes a p-well. In another example, the substrate160also includes at least two LDD regions for each of the N+ regions. The two LDD regions are in direct contact with the corresponding N+ region. In yet another example, the substrate160also includes two p-type regions made by pocket implants for each of the N+ regions.

The I/O transistors of the system100can be used in the system1200, which can provide protection to the system1240. For example, the internal system1240includes one or more core transistors and/or is coupled to one or more core transistors. A core transistor includes a gate region and a gate dielectric layer, such as a gate oxide layer. For example, the gate region of the core transistor has the same composition and the same thickness as the polysilicon region140. In another example, the gate dielectric layer of the core transistor has the same composition and the same thickness as the dielectric layer170.

According to an embodiment of the present invention, a core transistor is directly or indirectly coupled between a ground voltage level of VSS,COREand a supply voltage level of VDD,CORE. For example, the source or the drain of the core transistor is biased to the supply voltage level of VDD,CORE. In another example, the source or the drain of the core transistor is biased to the ground voltage level of VSS,CORE. As shown inFIG. 2, the transistors1210and1220each represent one or more I/O transistors and each are indirectly coupled between the ground voltage level of VSSand the supply voltage level of VDD. For example, the ground voltage level of VSS,COREis the same as the ground voltage level of VSS, and the supply voltage level of VDD,CORE, is smaller in magnitude than the supply voltage level of VDD. In another example, the ground voltage level of VSS,COREis the same as the ground voltage level of VSS, and the supply voltage level of VDD,CORE, is equal to 1.8 volts and the supply voltage level of VDDis equal to 3.3 volts.

As discussed above and further emphasized here,FIGS. 3 and 4are merely examples, which should not unduly limit the scope of the claims. One of ordinary skill in the art would recognize many variations, alternatives, and modifications.FIG. 5is a simplified system for electrostatic discharge protection according to another embodiment of the present invention. The polysilicon region140in the system100is replaced by polysilicon regions410,420, and430. For example, the polysilicon regions410,420, and430and the gate regions110surround the drain regions130. The polysilicon regions410,420, and430are partially or completely located within the active area150, and separated from the substrate by dielectric layers. For example, the dielectric layers include silicon oxide. In another example, the dielectric layers are separated from each other or in contact with each other. In yet another example, the gate regions110are electrically shorted to each other by another polysilicon region located outside the active area150.

In one embodiment, the substrate is doped to p-type. The source regions120and the drain regions130include N+ regions. For example, the substrate also includes a p-well. In another example, the substrate160also includes at least two LDD regions for each of the N+ regions. The two LDD regions are in direct contact with the corresponding N+ region. In yet another example, the substrate160also includes two p-type regions made by pocket implants for each of the N+ regions.

The I/O transistors of the system100can be used in the system1200, which can provide ESD protection to the system1240. For example, the internal system1240includes one or more core transistors and/or is coupled to one or more core transistors. A core transistor includes a gate region and a gate dielectric layer, such as a gate oxide layer. For example, the gate region of the core transistor has the same composition and the same thickness as the polysilicon regions410,420, and430. In another example, the gate dielectric layer of the core transistor has the same composition and the same thickness as the dielectric layers separating the polysilicon regions410,420, and430from the substrate.

According to an embodiment of the present invention, a core transistor is directly or indirectly coupled between a ground voltage level of VSS,COREand a supply voltage level of VDD,CORE. For example, the source or the drain of the core transistor is biased to the supply voltage level of VDD,CORE. In another example, the source or the drain of the core transistor is biased to the ground voltage level of VSS,CORE. As shown inFIG. 2, the transistors1210and1220each represent one or more I/O transistors and each are indirectly coupled between the ground voltage level of VSSand the supply voltage level of VDD. For example, the ground voltage level of VSS,COREis the same as the ground voltage level of VSS, and the supply voltage level of VDD,CORE, is smaller in magnitude than the supply voltage level of VDD. In another example, the ground voltage level of VSS,COREis the same as the ground voltage level of VSS, and the supply voltage level of VDD,CORE, is equal to 1.8 volts and the supply voltage level of VDDis equal to 3.3 volts.

FIG. 6is a simplified system for electrostatic discharge protection according to yet another embodiment of the present invention. This diagram is merely an example, which should not unduly limit the scope of the claims. One of ordinary skill in the art would recognize many variations, alternatives, and modifications. The system500includes the following components:

Although the above has been shown using a selected group of components for the system500, there can be many alternatives, modifications, and variations. For example, some of the components may be expanded and/or combined. Other components may be inserted to those noted above. Depending upon the embodiment, the arrangement of components may be interchanged with others replaced. For example, the I/O transistors in the active area550are PMOS transistors. Further details of these components are found throughout the present specification and more particularly below.

The gate regions510, the source regions520, and the drain regions530are used to form I/O transistors in the active area550. For example, the active area550includes the source regions520and the drain regions530. In another example, the I/O transistors in the active area550are NMOS transistors. As shown inFIG. 6, the polysilicon region540does not intersect the gate regions510. The gate regions510are not in direct contact with the polysilicon region540. For example, the polysilicon region540includes a plurality of sub-regions, and the plurality of sub-regions is not in direct contact with each other.

In one embodiment, the polysilicon region540is at least partially around the source regions520and the drain regions530. In another embodiment, the polysilicon region540is partially or completely located within the active area550. In yet another embodiment, the polysilicon region540is separated from the substrate by dielectric layers. For example, the dielectric layers include silicon oxide. In another example, the dielectric layers are separated from each other or in direct contact with each other. In yet another embodiment, the gate regions510are electrically shorted to each other by another polysilicon region located outside the active area550.

In another embodiment, the substrate is doped to p-type. The source regions520and the drain regions530include N+ regions. For example, the substrate also includes a p-well. In another example, the substrate560also includes at least two LDD regions for each of the N+ regions. The two LDD regions are in direct contact with the corresponding N+ region. In yet another example, the substrate560also includes two p-type regions made by pocket implants for each of the N+ regions.

The I/O transistors of the system500can be used in the system1200, which can provide ESD protection to the system1240. For example, the internal system1240includes one or more core transistors and/or is coupled to one or more core transistors. A core transistor includes a gate region and a gate dielectric layer, such as a gate oxide layer. For example, the gate region of the core transistor has the same composition and the same thickness as the polysilicon region540. In another example, the gate dielectric layer of the core transistor has the same composition and the same thickness as the dielectric layer separating the polysilicon region540from the substrate.

According to an embodiment of the present invention, a core transistor is directly or indirectly coupled between a ground voltage level of VSS,COREand a supply voltage level of VDD,CORE. For example, the source or the drain of the core transistor is biased to the supply voltage level of VDD,CORE. In another example, the source or the drain of the core transistor is biased to the ground voltage level of VSS,CORE. As shown inFIG. 2, the transistors1210and1220each represent one or more I/O transistors and each are indirectly coupled between the ground voltage level of VSSand the supply voltage level of VDD. For example, the ground voltage level of VSS,COREis the same as the ground voltage level of VSS, and the supply voltage level of VDD,CORE, is smaller in magnitude than the supply voltage level of VDD. In another example, the ground voltage level of VSS,COREis the same as the ground voltage level of VSS, and the supply voltage level of VDD,CORE, is equal to 1.8 volts and the supply voltage level of VDDis equal to 3.3 volts.

FIGS. 7(A)and (B) are simplified diagrams showing system for electrostatic discharge protection according to yet another embodiment of the present invention. This diagram is merely an example, which should not unduly limit the scope of the claims. One of ordinary skill in the art would recognize many variations, alternatives, and modifications. The system700includes the following components:

Although the above has been shown using a selected group of components for the system700, there can be many alternatives, modifications, and variations. For example, some of the components may be expanded and/or combined. Other components may be inserted to those noted above. For example, the regions720can serve as drains, and the regions730can serve as sources. Depending upon the embodiment, the arrangement of components may be interchanged with others replaced. For example, the I/O transistors in the active area750are PMOS transistors. Further details of these components are found throughout the present specification and more particularly below.

The gate regions710, the source regions720, and the drain regions730are used to form I/O transistors in the active area750. For example, the active area750includes the source regions720and the drain regions730. In another example, the I/O transistors in the active area750are NMOS transistors.

As shown inFIG. 7(A), the polysilicon regions740are not in direct contact with the gate regions710, and the polysilicon regions740are not in direct contact with each other. In one embodiment, the polysilicon regions740are located within the drain regions730in the top view. In another embodiment, the polysilicon regions740are located within the source regions720in the top view. In yet another embodiment, the polysilicon regions740are located within both the source regions720and the drain regions730in the top view. In yet another embodiment, the gate regions710are electrically shorted to each other by another polysilicon region located outside the active area750.

As shown inFIG. 7(B), the substrate760includes the active area750, and is separated from the polysilicon regions740by the dielectric layers770. For example, the dielectric layers770include silicon oxide. In another example, the dielectric layers770are separated from each other or in direct contact with each other. Each of the source regions720includes a doped region, and each of the drain regions730includes doped regions2732,2734, and2736in the substrate760. The doped regions2732,2734, and2736are not in direct contact with each other. In one embodiment, the substrate760is doped to p-type, and the doped regions2732,2734, and2736are N+ regions. For example, the substrate760also includes a p-well. In another example, the substrate760also includes at least two LDD regions for each of the doped regions2732,2734, and2736. The two LDD regions are in direct contact with the corresponding doped region. In yet another example, the substrate760also includes two p-type regions made by pocket implants for each of the doped regions2732,2734, and2736.

The I/O transistors of the system700can be used in the system1200, which can provide ESD protection to the system1240. For example, the internal system1240includes one or more core transistors and/or is coupled to one or more core transistors. A core transistor includes a gate region and a gate dielectric layer, such as a gate oxide layer. For example, the gate region of the core transistor has the same composition and the same thickness as the polysilicon regions740. In another example, the gate dielectric layer of the core transistor has the same composition and the same thickness as the dielectric layers770separating the polysilicon regions740from the substrate760.

According to an embodiment of the present invention, a core transistor is directly or indirectly coupled between a ground voltage level of VSS,COREand a supply voltage level of VDD,CORE. For example, the source or the drain of the core transistor is biased to the supply voltage level of VDD,CORE. In another example, the source or the drain of the core transistor is biased to the ground voltage level of VSS,CORE. As shown inFIG. 2, the transistors1210and1220each represent one or more I/O transistors and each are indirectly coupled between the ground voltage level of VSSand the supply voltage level of VDD. For example, the ground voltage level of VSS,COREis the same as the ground voltage level of VSS, and the supply voltage level of VDD,CORE, is smaller in magnitude than the supply voltage level of VDD. In another example, the ground voltage level of VSS,COREis the same as the ground voltage level of VSS, and the supply voltage level of VDD,CORE, is equal to 1.8 volts and the supply voltage level of VDDis equal to 3.3 volts.

As discussed above and further emphasized here,FIGS. 7(A)and (B) are merely examples, which should not unduly limit the scope of the claims. One of ordinary skill in the art would recognize many variations, alternatives, and modifications.FIGS. 8(A), (B), and (C) are simplified diagrams showing systems for electrostatic discharge protection according to yet other embodiments of the present invention. These diagrams are merely examples, which should not unduly limit the scope of the claims. One of ordinary skill in the art would recognize many variations, alternatives, and modifications.

InFIG. 8(A), the polysilicon regions740are added to the system100as shown inFIG. 3to form a system2810for EDS protection. The polysilicon regions740are not in direct contact with the gate regions110or the polysilicon regions140, and the polysilicon regions740are not in direct contact with each other. Additionally, the polysilicon regions740are separated from the substrate by the dielectric layers. For example, the dielectric layers include silicon oxide. In another example, the dielectric layers are separated from each other or in direct contact with each other. In one embodiment, the polysilicon regions740are located within the drain regions130in the top view. In another embodiment, the polysilicon regions740are located within the source regions120in the top view. In yet another embodiment, the polysilicon regions740are located within both the source regions120and the drain regions130in the top view. For example, each of the drain regions130includes several doped regions in the substrate. The doped regions are not in direct contact with each other. In one embodiment, the substrate is doped to p-type, and the doped regions are N+ regions. For example, the substrate also includes a p-well. In another example, the substrate also includes at least two LDD regions for each of the doped regions. The two LDD regions are in direct contact with the corresponding doped region. In yet another example, the substrate also includes two p-type regions made by pocket implants for each of the doped regions. In yet another embodiment, the gate regions110are electrically shorted to each other by another polysilicon region located outside the active area150.

InFIG. 8(B), the polysilicon regions740are added to the system100as shown inFIG. 5to form a system2820for EDS protection. The polysilicon regions740are not in direct contact with the gate regions110or the polysilicon regions410,420, and430, and the polysilicon regions740are not in direct contact with each other. Additionally, the polysilicon regions740are separated from the substrate by the dielectric layers. For example, the dielectric layers include silicon oxide. In another example, the dielectric layers are separated from each other or in direct contact with each other. In one embodiment, the polysilicon regions740are located within the drain regions130in the top view. In another embodiment, the polysilicon regions740are located within the source regions120in the top view. In yet another embodiment, the polysilicon regions740are located within both the source regions120and the drain regions130in the top view. For example, each of the drain regions130includes several doped regions in the substrate. The doped regions are not in direct contact with each other. In one embodiment, the substrate is doped to p-type, and the doped regions are N+ regions. For example, the substrate also includes a p-well. In another example, the substrate also includes at least two LDD regions for each of the doped regions. The two LDD regions are in direct contact with the corresponding doped region. In yet another example, the substrate also includes two p-type regions made by pocket implants for each of the doped regions. In yet another embodiment, the gate regions110are electrically shorted to each other by another polysilicon region located outside the active area150.

InFIG. 8(C), the polysilicon regions740are added to the system500as shown inFIG. 6to form a system2830for EDS protection. The polysilicon regions740are not in direct contact with the gate regions110or the polysilicon regions540, and the polysilicon regions740are not in direct contact with each other. Additionally, the polysilicon regions740are separated from the substrate by the dielectric layers. For example, the dielectric layers include silicon oxide. In another example, the dielectric layers are separated from each other or in direct contact with each other. In one embodiment, the polysilicon regions740are located within the drain regions530in the top view. In another embodiment, the polysilicon regions740are located within the source regions520in the top view. In yet another embodiment, the polysilicon regions740are located within both the source regions520and the drain regions530in the top view. For example, each of the drain regions530includes several doped regions in the substrate. The doped regions are not in direct contact with each other. In one embodiment, the substrate is doped to p-type, and the doped regions are N+ regions. For example, the substrate also includes a p-well. In another example, the substrate also includes at least two LDD regions for each of the doped regions. The two LDD regions are in direct contact with the corresponding doped region. In yet another example, the substrate also includes two p-type regions made by pocket implants for each of the doped regions. In yet another embodiment, the gate regions510are electrically shorted to each other by another polysilicon region located outside the active area550.

The I/O transistors as shown inFIGS. 8(A), (B), and/or (C) can be used in the system1200, which can provide ESD protection to the system1240. For example, the internal system1240includes one or more core transistors and/or is coupled to one or more core transistors. A core transistor includes a gate region and a gate dielectric layer, such as a gate oxide layer. For example, the gate region of the core transistor has the same composition and the same thickness as the polysilicon regions740. In another example, the gate dielectric layer of the core transistor has the same composition and the same thickness as the dielectric layers770separating the polysilicon regions740from the substrate760.

According to an embodiment of the present invention, a core transistor is directly or indirectly coupled between a ground voltage level of VSS,COREand a supply voltage level of VDD,CORE. For example, the source or the drain of the core transistor is biased to the supply voltage level of VDD,CORE. In another example, the source or the drain of the core transistor is biased to the ground voltage level of VSS,CORE. As shown inFIG. 2, the transistors1210and1220each represent one or more I/O transistors and each are indirectly coupled between the ground voltage level of VSSand the supply voltage level of VDD. For example, the ground voltage level of VSS,COREis the same as the ground voltage level of VSS, and the supply voltage level of VDD,CORE, is smaller in magnitude than the supply voltage level of VDD. In another example, the ground voltage level of VSS,COREis the same as the ground voltage level of VSS, and the supply voltage level of VDD,CORE, is equal to 1.8 volts and the supply voltage level of VDDis equal to 3.3 volts.

FIGS. 9(A), (B), (C), and (D) are simplified diagrams showing certain details of systems for electrostatic discharge protection according to certain embodiments of the present invention. These diagrams are merely examples, which should not unduly limit the scope of the claims. One of ordinary skill in the art would recognize many variations, alternatives, and modifications.

FIG. 9(A)shows a core transistor2100. The core transistor2100includes a gate region2110, a gate dielectric layer2120, LDD regions2130, pocket implant regions2140, heavily doped regions2150, and a substrate2160. In one embodiment, the core transistor2100is a part of or is coupled to the internal system1240.

FIG. 9(B)shows an I/O transistor2200. The I/O transistor2200includes a gate region2210, a gate dielectric layer2220, LDD regions2230, pocket implant regions2240, heavily doped regions2250, and a substrate2260. In one embodiment, the I/O transistor2200is one of the I/O transistors of the systems100,500,700,2810,2820, and/or2830. For example, one of the heavily doped regions2250corresponds to the doped region for the source region120, and another of the heavily doped regions2250corresponds to the doped region for the drain region130. In another example, one of the heavily doped regions2250corresponds to the doped region2732or2736, and another of the heavily doped regions2250corresponds to the doped region for the source region720.

FIG. 9(C)shows a structure2300. The structure2300includes a polysilicon region2310, a dielectric layer2320, an LDD region2330, a pocket implant region2340, a heavily doped region2350, and a substrate2360. In one embodiment, the structure2300is a cross-section related to the polysilicon regions140,410,420,430, and/or540. For example, the polysilicon region2310corresponds to the polysilicon regions140,410,420,430, or540. In another example, the heavily doped region2350corresponds to the doped region for the source region120adjacent to the polysilicon region140.

FIG. 9(D)shows a structure2400. The structure2400includes a polysilicon region2410, a dielectric layer2420, LDD regions2430, pocket implant regions2440, heavily doped regions2450, and a substrate2460. In one embodiment, the structure2400is a cross-section related to the polysilicon regions740. For example, the polysilicon region2410corresponds to one of the polysilicon regions740. In another example, one of the heavily doped regions2450corresponds to the doped region2732or2736, and another of the heavily doped regions2450corresponds to the doped region for the source region720.

Although the above has been shown using a selected group of components for the structures2100,2200,2300, and2400, there can be many alternatives, modifications, and variations. For example, some of the components may be expanded and/or combined. Other components may be inserted to those noted above. Depending upon the embodiment, the arrangement of components may be interchanged with others replaced. Further details of these components are found throughout the present specification and more particularly below.

As shown inFIGS. 9(A), (B), and (C), the gate region2110has the same composition and the same thickness as the polysilicon region2310. The dielectric layer2120has the same composition and the same thickness as the dielectric layer2320. The LDD regions2130have the same doping profile as the LDD region2330, and a different doping profile from the LDD regions2230. For example, the LDD regions2130and the LDD region2330are formed by implantation of arsenic ions with implant energy of 3 KeV and dose of 1.05×1015cm−3. The implant direction is perpendicular to the surface of the substrate2160or the surface of the substrate2360. In another example, the LDD regions2230are formed by implantation of phosphors ions with implant energy of 10 KeV and dose of 1.3×1014cm−3. The implant direction is perpendicular to the surface of the substrate2260.

The pocket implant regions2140have the same doping profile as the pocket implant region2340, and a different doping profile from the pocket implant regions2240. For example, the pocket implant regions2140and the pocket implant region2340are formed by implantation of indium ions with implant energy of 100 KeV and does of 4.0×1013cm−3. The implant direction is 30 degrees from the direction that is perpendicular to the surface of the substrate2160or the surface of the substrate2360. In another example, the pocket implant regions2140and the pocket implant region2340are formed by implantation of boron ions with implant energy of 14 KeV and does of 1.0×1013cm−3. The implant direction is 30 degrees from the direction that is perpendicular to the surface of the substrate2160or the surface of the substrate2360. In yet another example, the pocket implant regions2240are formed by implantation of indium ions with implant energy of 130 KeV and does of 2.6×1013cm−3. The implant direction is 30 degrees from the direction that is perpendicular to the surface of the substrate2260. In yet another example, the junction depth for the LDD regions2130and the pocket implant regions2140is the same as the junction depth for the LDD region2330and the pocket implant region2340. In yet another example, the junction depth for the LDD region2330and the pocket implant region2340is different from the junction depth for the LDD regions2230and the pocket implant regions2240. In yet another example, the junction doping profile for the LDD region2330and the pocket implant region2340is steeper than the junction doping profile for the LDD regions2230and the pocket implant regions2240. In yet another example, the junction breakdown voltage for the LDD region2330and the pocket implant region2340is lower in magnitude than the junction breakdown voltage for the LDD regions2230and the pocket implant regions2240. In yet another example, the junction doping profile for the heavily doped region2350and the pocket implant region2340is steeper than the junction doping profile for the heavily doped regions2250and the pocket implant regions2240. In yet another example, the junction breakdown voltage for the heavily doped region2350and the pocket implant region2340is lower in magnitude than the junction breakdown voltage for the heavily doped regions2250and the pocket implant regions2240. In yet another example, the structures2100and2300are formed by at least some same fabrication processes.

As shown inFIGS. 9(A), (B), and (D), the gate region2110has the same composition and the same thickness as the polysilicon region2410. The dielectric layer2120has the same composition and the same thickness as the dielectric layer2420. The LDD regions2130have the same junction depth as the LDD regions2430, and a different junction depth from the LDD regions2230. For example, the LDD regions2130and the LDD regions2430are formed by implantation of arsenic ions with implant energy of 3 KeV and dose of 1.1×1015cm−3. The implant direction is perpendicular to the surface of the substrate2160or the surface of the substrate2460. In another example, the LDD regions2230are formed by implantation of phosphors ions with implant energy of 10 KeV and dose of 1.3×1014cm−3. The implant direction is perpendicular to the surface of the substrate2260.

The pocket implant regions2140have the same doping profile as the pocket implant regions2440, and a different doping profile from the pocket implant regions2240. For example, the pocket implant regions2140and the pocket implant regions2440are formed by implantation of indium ions with implant energy of 100 KeV and does of 4.0×1013cm−3. The implant direction is 30 degrees from the direction that is perpendicular to the surface of the substrate2160or the surface of the substrate2460. In another example, the pocket implant regions2140and the pocket implant regions2440are formed by implantation of boron ions with implant energy of 14 KeV and does of 1.0×1013cm−3. The implant direction is 30 degrees from the direction that is perpendicular to the surface of the substrate2160or the surface of the substrate2460. In yet another example, the pocket implant regions2240are formed by implantation of indium ions with implant energy of 130 KeV and does of 2.6×1013cm−3. The implant direction is 30 degrees from the direction that is perpendicular to the surface of the substrate2260. In yet another example, the junction depth for the LDD regions2130and the pocket implant regions2140is the same as the junction depth for the LDD regions2430and the pocket implant regions2440. In yet another example, the junction depth for the LDD regions2430and the pocket implant regions2440is different from the junction depth for the LDD regions2230and the pocket implant regions2240. In yet another example, the junction doping profile for the LDD regions2430and the pocket implant regions2440is steeper than the junction doping profile for the LDD regions2230and the pocket implant regions2240. In yet another example, the junction breakdown voltage for the LDD regions2430and the pocket implant regions2440is lower in magnitude than the junction breakdown voltage for the LDD regions2230and the pocket implant regions2240. In yet another example, the junction doping profile for the heavily doped regions2450and the pocket implant regions2440is steeper than the junction doping profile for the heavily doped regions2250and the pocket implant regions2240. In yet another example, the junction breakdown voltage for the heavily doped regions2450and the pocket implant regions2440is lower in magnitude than the junction breakdown voltage for the heavily doped regions2250and the pocket implant regions2240. In yet another example, the structures2100and2400are formed by at least some same fabrication processes.

In some embodiments, the structures2100,2200, and2300are parts of the systems100,500,2810,2820, and/or2830. In certain embodiments, the structures2100,2200, and2400are parts of the systems700,2810,2820, and/or2830.

According to another embodiment of the present invention, a system for electrostatic discharge protection includes a first transistor coupled to a first system and including a first gate, a first dielectric layer located between the first gate and a first substrate, a first source, and a first drain. The first system includes or is coupled to a core transistor, and the core transistor includes a second gate, a second dielectric layer located between the second gate and a second substrate, a second source, and a second drain. The first transistor is selected from a plurality of transistors, and the plurality of transistors include a plurality of gate regions, a plurality of source regions, and a plurality of drain regions. Each of the plurality of gate regions intersects a polysilicon region. The polysilicon region is separated from the first substrate by a third dielectric layer, and at least a part of the polysilicon region is located on an active area. The polysilicon region is adjacent to a first doped region and a second doped region, and the first doped region and the second doped region are associated with opposite charge polarities. The second dielectric layer and the third dielectric layer are associated with the same composition and the same thickness, and the second gate and the polysilicon region are associated with the same composition and the same thickness. For example, the system is implemented according toFIG. 2,FIG. 3,FIG. 4,FIG. 8(A),FIG. 9(A),FIG. 9(B),FIG. 9(C), and/orFIG. 9(D).

According to yet another embodiment, a system for electrostatic discharge protection includes a first transistor coupled to a first system and including a first gate, a first dielectric layer located between the first gate and a first substrate, a first source, and a first drain. The first system includes or is coupled to a core transistor, and the core transistor includes a second gate, a second dielectric layer located between the second gate and a second substrate, a second source, and a second drain. The first transistor is selected from a plurality of transistors, and the plurality of transistors includes a plurality of gate regions, a plurality of source regions, and a plurality of drain regions. The first substrate is separated from a first plurality of polysilicon regions by a first plurality of dielectric layers, and at least a part of each of the first plurality of polysilicon regions is located on an active area. The first plurality of polysilicon regions is not in direct contact with each other. Each of the first plurality of polysilicon regions is adjacent to a first doped region and a second doped region, and the first doped region and the second doped region are associated with opposite charge polarities. The second dielectric layer and the first plurality of dielectric layers are associated with the same composition and the same thickness, and the second gate and the first plurality of polysilicon regions are associated with the same composition and the same thickness. For example, the system is implemented according toFIG. 2,FIG. 5,FIG. 6,FIG. 8(B),FIG. 8(C),FIG. 9(A),FIG. 9(B),FIG. 9(C), and/orFIG. 9(D).

According to yet another embodiment, a system for electrostatic discharge protection includes a first transistor coupled to a first system and including a first gate, a first dielectric layer located between the first gate and a first substrate, a first source, and a first drain. The first system includes or is coupled to a core transistor, and the core transistor includes a second gate, a second dielectric layer located between the second gate and a second substrate, a second source, and a second drain. The first transistor is selected from a plurality of transistors, and the plurality of transistors includes a plurality of gate regions, a plurality of source regions, and a plurality of drain regions. The first substrate is separated from a plurality of polysilicon regions by a plurality of dielectric layers, and the plurality of polysilicon regions is on one of the plurality of drain regions or one of the plurality of source regions. The plurality of polysilicon regions is not in direct contact with each other, and each of the plurality of polysilicon regions is not in direct contact with anyone of the plurality of gate regions. Each of the plurality of polysilicon regions is adjacent to a first doped region and a second doped region, and the first doped region and the second doped region are associated with opposite charge polarities. The second dielectric layer and the plurality of dielectric layers are associated with the same composition and the same thickness, and the second gate and the plurality of polysilicon regions are associated with the same composition and the same thickness. For example, the system is implemented according toFIG. 2,FIG. 7(A),FIG. 7(B),FIG. 8(A),FIG. 8(B),FIG. 8(C),FIG. 9(A),FIG. 9(B),FIG. 9(C), and/orFIG. 9(D).

The present invention has various advantages. Some embodiments of the present invention improve the I/O ESD protection technique. For example, the junction breakdown voltages of MOS transistors are significantly lowered. In another example, the I/O transistors can turn on junction breakdown and thus prevent or reduce damages for self-protection from ESD stress. Certain embodiments of the present invention can effectively delay the time when the ESD stress current reaches the gate regions. For example, as shown inFIGS. 7(A)and (B) and8(A), (B), and (C), the channels formed under the polysilicon regions740have significant resistance, which can lengthen the current paths. Some embodiments of the present invention comply with the ESD design rule. For example, to dissipate significant heat generated by high-density ESD current, the ESD design rule often allows relatively large spacing between the gate regions and drain contacts as shown inFIGS. 7(A)and (B) and8(A), (B), and (C). In another example, the spacing is equal to or longer than 1.72 μm. Accordingly, the polysilicon regions740can be inserted to the drain regions of the I/O transistors in order to increase lengths of the current paths and raise the drain resistance without violating the ESD design rule. Certain embodiments of the present invention provide junction doping profiles between heavily doped regions and pocket implant regions related to floating and/or biased polysilicon regions, which are steeper than junction doping profiles between heavily doped regions and pocket implant regions for I/O transistors. For example, the heavily doped regions and pocket implant regions related to floating and/or biased polysilicon regions are made with the same implant processes as ones used for making the heavily doped regions and pocket implant regions for core transistors. Some embodiments of the present invention provide junction doping profiles between LDD regions and pocket implant regions related to floating and/or biased polysilicon regions, which are steeper than junction doping profiles between LDD regions and pocket implant regions for I/O transistors. For example, the LDD regions and pocket implant regions related to floating and/or biased polysilicon regions are made with the same implant processes as ones used for making the LDD regions and pocket implant regions for core transistors. Certain embodiments of the present invention make junction breakdown voltages related to floating and/or biased polysilicon regions significantly lower than junction breakdown voltages of conventional I/O transistors. When an ESD event occurs, the lower junction breakdown voltages allow turning on the junction breakdown more quickly; therefore the I/O transistors can be protected from ESD damage more effectively. Depending upon the embodiment, one or more of these benefits may be achieved. These and other benefits will be described in more detail throughout the present specification and more particularly below.