Forming field effect transistor device spacers

A method for forming field effect transistors comprises forming a first dummy gate stack over a first fin, forming a second dummy gate stack over a second fin, depositing a first layer of spacer material on the first dummy gate stack, the first fin, the second dummy gate stack, and the second fin, patterning a first masking layer on the first dummy gate stack and the first fin, etching to remove portions of the first layer of spacer material and form a spacer adjacent to the second dummy gate stack, removing the first masking layer, epitaxially growing a silicon material on the second fin, depositing a layer of oxide material on the first layer of spacer material, the first epitaxial material and the second dummy gate stack, and depositing a second layer of spacer material on the layer of oxide material.

BACKGROUND

The present invention relates to field effect transistors (FET), and more specifically, to finFET devices.

FinFET devices typically include semiconductor fins that are arranged on a substrate. Gate stacks are arranged on the fins and define channel regions of the device. The source and drain active regions of the device are adjacent to the channel region.

In fabrication, sacrificial dummy gate stacks are often formed prior to forming the active regions of the device. The dummy gate stacks define the channel region, and are formed from a material such as polysilicon. A material such as nitride or oxide is often used to form spacers adjacent to the gate stacks. The dummy gate stacks allow fabrication processes such as ion implantation and annealing or epitaxial growth process to be performed prior to forming the gate stacks. Such high temperature processes can undesirably degrade the materials in the gate stacks, thus the dummy gate is used to define and protect the channel region while the active regions are formed.

Often a wafer includes nFET and pFET devices. The devices are distinguished by the type of materials in the active regions of the devices. The active regions may be formed by ion implantation and/or epitaxially growing doped silicon materials.

SUMMARY

According to one embodiment of the present invention, a method for forming field effect transistors comprises forming a first dummy gate stack over a first fin, forming a second dummy gate stack over a second fin, depositing a first layer of spacer material on the first dummy gate stack, the first fin, the second dummy gate stack, and the second fin, patterning a first masking layer on the first dummy gate stack and the first fin, etching to remove portions of the first layer of spacer material and form a spacer adjacent to the second dummy gate stack, removing the first masking layer, epitaxially growing a silicon material on the second fin, depositing a layer of oxide material on the first layer of spacer material, the first epitaxial material and the second dummy gate stack, and depositing a second layer of spacer material on the layer of oxide material.

According to another embodiment of the present invention, a method for forming spacers of a field effect transistor comprises patterning a first fin, forming a first dummy gate stack on the first fin, forming a first layer of spacer material on the first fin and the first dummy gate stack, removing portions of the first layer of spacer material to define a spacer adjacent to the first dummy gate stack, epitaxially growing a silicon material on exposed portions of the first fin, forming a layer of oxide material on the silicon material, the spacer, and the dummy gate stack, and forming a second layer of spacer material on the oxide layer.

According to yet another embodiment of the present invention, a field effect transistor device comprises a first semiconductor fin arranged on a substrate, the first semiconductor fin is doped with n-type dopants, a second semiconductor fin arranged on the substrate, the second semiconductor fin is doped with p-type dopants, a first gate stack arranged over the first semiconductor fin, a second gate stack arranged over the second semiconductor fin, a first spacer arranged adjacent to the first gate stack, the first spacer having a substantially uniform thickness, and a second spacer arranged adjacent to the second gate stack, the second spacer having a substantially uniform thickness, wherein the thickness of the first spacer is substantially similar to the thickness of the second spacer.

DETAILED DESCRIPTION

The formation of nFET and pFET devices on a single wafer often includes forming the active regions of the nFET devices and the pFET devices in separate fabrication steps to allow the formation of active regions having different types of dopant materials. For example, when the active regions of the nFET devices are being formed, the pFET devices are protected by a layer of material that prevents exposure of the pFET to the nFET active region fabrication process. Likewise, when the active regions of the pFET devices are being fabricated, the nFET devices are protected to prevent contamination of the nFET devices. This process often results in asymmetric pFET and nFET spacers that affect the performance of the devices. The embodiments described below provide for symmetrical spacers in pFET and nFET devices formed on a substrate.

FIG. 1illustrates a cross sectional view of two finFET devices having fins102aand102band dummy gate stacks104aand104b. A layer of spacer material106aand106bis deposited over the devices and formed into spacers. A second layer of spacer material108is formed over the devices. In the illustrated example, the active region of the fin102bhas been formed by an epitaxial growth that was performed prior to the deposition of the second layer of spacer material108, while the spacer108awas formed prior to the epitaxial growth on the fin102a. The resulting structure includes finFET devices having asymmetrical spacers108where the spacer material108aat the base of the gate stack104ain region101ahas a greater thickness than the spacer material108bat the base of the gate stack104bin region101b. When NFET and PFET have different spacer thickness (asymmetrical spacers), forming balanced junctions for good device behavior becomes difficult. Unbalanced junctions may either cause higher external resistance or may short channel control. The thickness of the spacers also affects the contact area, and thus, it is desirable to minimize the spacer thickness.

FIGS. 2-15illustrate an exemplary method of forming symmetrical spacers for nFET and pFET fin FET devices on a wafer.FIG. 2illustrates a side cut-away view of fins204aand204bare formed on a substrate202using, for example, a photolithographic patterning and etching method such as reactive ion etching (RIE). Dummy gate stacks206aand206bare arranged on the fins204aand204brespectively. The dummy gate stacks206are formed by for example, depositing a layer of polysilicon material or oxide material208aand208band an oxide or nitride material210over the layer of polysilicon material208aand208b. The photolithographic patterning and etching process may be used to pattern the dummy gate stacks206. Following the patterning of the dummy gate stacks206, a layer of spacer material212is deposited over the exposed surfaces. In the illustrated embodiment, the spacer material212includes a low-k material such as, for example, SiN, SiBCN, SiOCN, or SiOC that may be deposited by, for example, a chemical vapor deposition (CVD) process.

FIG. 3illustrates the resultant structure following the patterning and deposition of a masking layer302over the dummy gate stack206aand fin204a. The masking layer may include, for example, an organic material. After the masking layer302is patterned, an anisotropic etching process such as, for example, RIE is performed to form the spacers304adjacent to the dummy gate stack206b. The etching process removes a portion of the spacer material212to expose portions of the fin204b.

FIG. 4illustrates the resultant structure following the removal of the masking layer302(ofFIG. 3) and an epitaxial growth process. The masking layer may be removed by, for example, a plasma ashing process. The epitaxial growth process grows an epitaxial material, such as, for example, silicon or silicon germanium on exposed silicon surfaces of the fin204bto further define source and drain regions (active regions)402. The layer of spacer material212over the dummy gate stack206aand the fins204aprotects the silicon material of the fin204afrom seeding the epitaxy. In some embodiments, the epitaxially grown material in the active regions402may be in-situ doped with either n-type dopants or p-type dopants during the epitaxial growth process.

FIG. 5illustrates the deposition of an oxide layer502over the exposed portions of the spacer material layer212, the spacers304, the active regions402, and the dummy gate stacks206. The oxide layer502is relatively thin approximately 1 to 5 nanometers. The oxide layer502is formed using, for example a CVD process.

FIG. 6illustrates the deposition of a second layer of spacer material602over the oxide layer502. The second layer of spacer material602may include, for example, a nitride material that is deposited by a CVD process.

FIG. 7illustrates the patterning of a mask layer702. The masking layer702may be formed by, for example, a lithographic deposition and patterning process. The mask layer702is patterned over the second layer of spacer material602on the dummy gate stack206b, and the active regions402.

FIG. 8illustrates the resultant structure following an etching process such as, for example, a chemical wet etching process or a reactive ion etching process that removes the exposed portions of the second layer of spacer material602. The etching process is selective to the material in the oxide layer502such that the oxide layer502is exposed, but not substantially etched.

FIG. 9illustrates the resultant structure following an etching process such as, for example, a diluted hydrofluoric (HF) or a buffered HF etching process. That removes the exposed portions of the oxide layer502. The removal of the exposed portions of the oxide layer502exposes a portion of the spacer material layer212over the dummy gate stack602aand the fin204a.

FIG. 10illustrates the formation of spacers1002adjacent to the dummy gate stack206a. The spacers1002are formed by an anisotropic etching process such as, for example, RIE that removes the exposed horizontal surfaces of the layer of spacer material layer212(ofFIG. 9).

FIG. 11illustrates the formation of source and drain regions (active regions)1102using, for example, an epitaxial growth process that grows a silicon material on the exposed portions of the fin204a. The source and drain regions1102may be in-situ doped during the epitaxial growth process with n-type or p-type dopants. In the illustrated embodiment, the source and drain regions402and the source and drain regions1102are dissimilar. In this regard, in one embodiment, if the regions402are doped as p-type regions, the regions1102are doped as n-type regions. In an alternate embodiment, if the regions402are doped as n-type regions, the regions1102may be doped as p-type regions.

FIG. 12illustrates the patterning of a masking layer1202over the source and drain regions1102, the dummy gate stack206a, and the spacers1002. The masking layer1202may be formed by, for example, a lithographic patterning and etching process. Following the patterning of the masking layer1202, an etching process such as, for example, a chemical etching process, is performed that removes exposed portions of the second layer of spacer material602(ofFIG. 11). The removal of the second layer of spacer material602exposes the oxide material502. The etching process is selective to the oxide layer502such that the etching process does not substantially remove the oxide layer502material.

FIG. 13illustrates the removal of the masking layer1202to expose the source and drain region1102, the spacers1002and the dummy gate stack206a.

FIG. 14illustrates the resultant structure following the deposition of an insulating layer1402such as, for example an oxide material layer. The insulating layer1402may be formed by, for example, a CVD process. The insulating layer1402is formed over the source and drain regions1002, the dummy gate stack206a, the spacers1002and the oxide layer502that is over the dummy gate stack206b, the spacers304, and the source and drain regions402.

FIG. 15illustrates the resultant structure after a planarizing process such as, for example, chemical mechanical polishing (CMP) has been performed, which removes a portion of the insulator layer1402and exposes the dummy gate stacks206aand206b(ofFIG. 14). The dummy gate stacks206are removed, and gate stacks1502aand1502bare formed. The gate stacks1502include a dielectric layer1504and a gate electrode layer1506. The finFET device1500aincludes the gate stack1502a, the spacers1002, and the source and drain regions (active regions)1102. The finFET device1500bincludes the gate stack1502b, the spacers304and the source and drain regions (active regions)402. In one exemplary embodiment, the finFET device1500ais a pFET type device and the finFET device1500bis an nFET type device. In alternate exemplary embodiments, the finFET device1500ais an nFET type device and the finFET device1500bis a pFET type device. The finFET devices1500aand1500bhave spacers1002and304that have substantially similar thicknesses (t) for the length of the spacer (i.e., from the top surface of the gate stacks1502to the top of the fins204aand204b.

The exemplary methods and structures described herein include finFET devices having different type active regions and spacers having substantially similar thicknesses, which improves the performance of the devices.