Clock regeneration circuit, light receiving circuit, photocoupler, and frequency synthesizer

A clock regeneration circuit includes: a signal input terminal; a D flip-flop circuit; a reset signal generation circuit; a delay circuit; a comparator; a first capacitor; and a feed back circuit. The signal input terminal is inputted with a pulse width modulation signal. The D flip-flop circuit includes a clock terminal, an output terminal, and a reset terminal. The reset signal generation circuit is configured to input a reset signal generated in synchronization with the pulse width modulation signal to the reset terminal at a first time. The delay circuit is configured to delay the pulse width modulation signal. The feedback circuit includes a current source having a control terminal. The feedback circuit is configured to change one of charge rise time and discharge fall time in response to the signal of the comparator to control duty cycle of the signal of the comparator.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is based upon and claims the benefit of priority from Japanese Patent Application No. 2012-263207, filed on Nov. 30, 2012; the entire contents of which are incorporated herein by reference.

FIELD

Embodiments described herein relate generally a clock regeneration circuit, a light receiving circuit, a photocoupler, and a frequency synthesizer.

BACKGROUND

In a photocoupler type insulating device for transmitting analog signals, an analog input signal is A/D converted, and digital data are transmitted in the insulated section. That is, by using one LED (light emitting diode), digital data and a clock signal are modulated and transmitted. In the receiving circuit, the clock signal is regenerated from the modulated signal, and the digital data are demodulated. Such a photocoupler type insulating device can transmit high-accuracy analog signals with e.g. the input/output circuit electrically insulated. Thus, in industrial equipment operated at high voltage, a high-accuracy control signal can be correctly transmitted and received.

Pulse width modulation (PWM) can be used as a modulation scheme for the photocoupler type insulating device. In this case, a delay-locked loop (DLL) circuit can be used to regenerate the clock signal. Polyphase clocks generated by the DLL circuit can be used to demodulate the digital data.

However, the PWM signal including multibit information in one period requires a very large number of polyphase clock signals to demodulate the digital data. Thus, in the receiving circuit in which a delay-locked loop circuit and a demodulation circuit are integrated, the circuit area and the power consumption are increased. This may make it difficult to reduce the size and power consumption of the circuit.

DETAILED DESCRIPTION

In general, according to one embodiment, a clock regeneration circuit includes: a signal input terminal; a D flip-flop circuit; a reset signal generation circuit; a delay circuit; a comparator; a first capacitor; and a feed back circuit. The signal input terminal is inputted with a pulse width modulation signal having a prescribed period and a fixed average duty cycle. The D flip-flop circuit includes a clock terminal, an input terminal supplied with a power supply voltage, an output terminal, and a reset terminal. The reset signal generation circuit is connected to the signal input terminal and configured to input a reset signal generated in synchronization with the pulse width modulation signal to the reset terminal. The delay circuit is connected to the signal input terminal and configured to delay the pulse width modulation signal by a first delay time and output toward the clock terminal. The comparator includes a first input terminal, a second input terminal supplied with a reference voltage, and an output terminal, and configured to output a signal having the prescribed period. The first capacitor is provided between the first input terminal and ground. The feedback circuit includes a current source having a control terminal. The current source is configured to change one of charge rise time and discharge fall time of the first capacitor by voltage of the control terminal changed in response to the signal of the comparator to control duty cycle of the signal of the comparator to a prescribed value.

FIG. 1is a block diagram showing the configuration of a clock regeneration circuit.

The clock regeneration circuit10includes a signal input terminal12, a D flip-flop circuit (D-FF)20, a delay circuit24, a comparator26, a first capacitor32, a feedback circuit34, and a controller50. In the clock regeneration circuit10, a pulse sequence of a PWM signal VPWMencoded with binary data and having a prescribed period Ts is inputted to the signal input terminal12. The clock regeneration circuit10generates a clock signal φ0having the prescribed period Ts and a prescribed duty cycle D. It is assumed that the pulse sequence of the PWM signal VPWMhas a prescribed value of average duty cycle (e.g., 50%).

The D-FF20includes a clock terminal20a, an input terminal (D)20b, and an output terminal (Q)20c. The input terminal20bof the D flip-flop circuit20is supplied with a power supply voltage VDD. The signal state of the input terminal20bat the rise timing of the clock signal is outputted to the output terminal20c. Until the next clock signal is inputted, the state of the output terminal20cis held.

The delay circuit24delays the PWM signal VPWMinputted to the signal input terminal12by a first delay time td1 from its rise timing and outputs the delayed PWM signal VDPWMtoward the clock terminal20a. The delay circuit24can be e.g. a circuit in which an even number of inverter circuits are series connected, or a circuit composed of a logic circuit and a CR circuit.

The comparator26includes a first input terminal26a, a second input terminal26bsupplied with a reference voltage Vcp, and an output terminal26c. One terminal of the first capacitor32with capacitance C is connected to the first input terminal26aof the comparator26, and the other terminal is grounded.

The feedback circuit34can include e.g. a charge pump36, a second capacitor46with capacitance Ccp, and a voltage controlled current source48. The input side of the charge pump36is connected to the output terminal26cof the comparator26, and the output side is connected to a control terminal44. The charge pump36includes a first current source40provided between the control terminal44and the power supply terminal, and a second current source42provided between the control terminal44and the ground.

One terminal of the second capacitor46is connected to the control terminal44, and the other terminal is connected to the power supply voltage VDD.

The voltage controlled current source48can control the temporal change of the voltage Vc of the first capacitor32by the control voltage Vcont of the control terminal44. That is, by the current I48depending on transconductance K (>0), the charge of the first capacitor32is discharged.

The controller50includes a first switch (SW1)52provided between the output terminal20cof the D-FF20and the voltage controlled current source48, and a second switch (SW2)54provided between the output terminal20cof the D-FF20and the first input terminal26aof the comparator26.

As shown inFIG. 1, the controller50further includes one of a reset signal generation circuit22, a signal detection circuit58, a third switch (SW3)56, and an OR circuit23. The reset terminal20eof the D-FF20is inputted at a first time with a reset signal Vrst synchronized with the rise timing of the PWM signal. If the reset signal Vrst is generated in synchronization with the rise of the PWM signal, the reset signal Vrst is outputted before the rise of the delayed PWM signal VDPWM. Thus, the D-FF20can be returned to the state before the rise of the delayed PWM signal VDPWM. Then, the voltage Vc of the first capacitor32and the clock signal φ0being the output voltage signal of the comparator26are changed in conformity with the period of the delayed PWM signal VDPWM.

In the case where the PWM signal VPWMis not inputted, the third switch56is shorted by the output signal Vdet of the signal detection circuit58. Thus, the control voltage Vcont of the feedback circuit34can be set to a fixed value so that the circuit does not operate. On the other hand, in the case where the PWM signal VPWMis inputted, the third switch56is opened by the output signal Vdet of the signal detection circuit58. Thus, the voltage controlled current source48is controlled by the control voltage Vcont of the control terminal44. Accordingly, the feedback circuit34controls the clock regeneration circuit10toward the steady state while following the output pulse sequence of the delayed PWM signal VDPWM.

FIG. 2Ais a block diagram of a delay-locked loop circuit connected to the clock regeneration circuit according to the first embodiment.FIG. 2Bis a waveform diagram of the delayed PWM signal VDPWMand polyphase clock signals.

As shown inFIG. 2A, the delay-locked loop (DLL) circuit is a negative feedback circuit including e.g. a phase comparator92, a charge pump94, a voltage controlled delay line (VCDL) circuit62, and a lock detection circuit96.

The clock regeneration circuit10is inputted with a pulse width modulation (PWM) signal VPWM. The clock regeneration circuit10outputs a clock (CLK) signal φ0having a period equal to the period Ts of the PWM signal and having a prescribed duty cycle D. In the case where the transmitted digital data is of 1.5 bits, the pulse width of the inputted PWM signal VPWMcan be set to e.g. three levels of Ts/4, 2Ts/4, and 3Ts/4. The DLL circuit60is inputted with the regenerated clock signal φ0. The lock detection circuit96is inputted with the delayed PWM signal VDPWM. If the phase difference between the clock signals φ0and φ8becomes Ts/2 or more, the phase comparator92fails to operate normally. Furthermore, when there is no signal, the DLL should be stopped. For these reasons, the delayed PWM signal VDPWMis used.

The VCDL circuit62is configured so that voltage controlled delay elements62aare series connected in multiple stages. The voltage controlled delay element62ais composed of e.g. a transistor including a MOSFET (metal-oxide-semiconductor field-effect transistor) and a capacitance element. When the DLL circuit60is normally locked in the steady state, the respective voltage controlled delay elements62agenerate polyphase clock signals by delaying the rise timing of the clock signal φ0little by little within the prescribed period Ts. For instance, as shown inFIG. 2B, polyphase clock signals φ1-φ8with a time interval of Ts/8 can be generated and outputted.

The lock detection circuit96is inputted with the delayed PWM signal VDPWMand the clock signals φ0-φ8. If the phase difference between the clock signals φ0and φ8becomes Ts/2 or more, the phase comparator92fails to operate normally. Thus, the lock detection circuit96is used to detect the phase difference. The lock detection circuit96determines, in a wide range, the phase difference between the clock signals φ0and φ8, i.e., the delay amount of the clock signal φ8relative to the clock φ0. When the delay amount is smaller than a prescribed value, the lock detection circuit96outputs an UNDER signal. When the delay amount is larger than the prescribed value, the lock detection circuit96outputs an OVER signal. The UNDER signal and the OVER signal are outputted to the phase comparator circuit92. Furthermore, when the delayed PWM signal VDPWMis not inputted, the lock detection circuit96determines that it is in the “initial state”. Thus, the lock detection circuit96stops the operation of the charge pump94and outputs a control signal to each voltage controlled delay element62a.

FIG. 6Ais a block diagram of a DLL circuit according to a comparative example.FIG. 6Bis a timing chart thereof.

The comparative example illustrates a DLL circuit in which the clock regeneration circuit is not used. As shown inFIG. 6A, the DLL circuit160includes a phase comparator192, a charge pump194, a VCDL circuit162, and a lock detection circuit196. The T-FF circuit190converts the input PWM signal VPWMto a voltage signal having a fixed duty cycle. This enables the lock detection circuit196to detect the phase difference.

However, the period of the polyphase clock is twice the period of the PWM signal VPWM. As shown inFIG. 6B, demodulation of the PWM signal VPWMof Ts/4, 2Ts/4, and 3Ts/4 requires polyphase clocks of φ3(between Ts/4 and 2Ts/4), φ5(between 2Ts/4 and 3Ts/4), φ11(between 5Ts/4 and 6Ts/4), and φ13(between 6Ts/4 and 7Ts/4). As a result, the area of the VCDL circuit162is enlarged, and the power consumption is also increased.

In contrast, the clock regeneration circuit according to the first embodiment can generate a clock signal having the same period Ts as the PWM signal and having a fixed duty cycle. Thus, without using the T-FF circuit, the DLL circuit including a lock detection circuit can be driven. For instance, PWM signals of three levels can be demodulated by two clock signals of φ3and φ5. That is, the area of the VCDL circuit is generally halved, and the power consumption can also be reduced to generally one half. Furthermore, downsizing of the light receiving circuit and the photocoupler is facilitated.

FIG. 3is a timing chart illustrating the operation of the clock regeneration circuit of the first embodiment.

At time t1, the reset signal Vrst synchronized with the rise of the PWM signal VPWMis issued from the reset signal generation circuit22and inputted to the reset terminal20eof the D-FF20. Thus, the positive phase output Q of the D-FF20is set to low (L) level, and the negative phase output (denoted by Q−) is set to high (H) level. Then, after a fixed time, the reset state is canceled. At this time, the first switch52is short, and the second switch54is open. Thus, the voltage Vc of the first capacitor is not affected. At time t2, the PWM signal VDPWMof period Ts delayed by the first delay time td1 is inputted to the clock terminal20aof the D-FF20. The input terminal20bof the D-FF20is connected to power supply. Thus, in synchronization with the rise of the delayed PWM signal VPWM, the positive phase output Q turns to high (H) level. Here, the first delay time td1 is set so that Vrst has been canceled at the rise time of VDPWM.

In synchronization with the rise of the positive phase output Q of the D-FF20, the first switch52is opened, and the second switch54is shorted. This state continues for the duration of the second delay time td2. During this time, the voltage Vc of the first capacitor32is equipotential to the positive phase output Q of the D-FF20. At time t3 after the second delay time td2 from time t2, the potential of the positive phase output Q of the D-FF20is at the power supply voltage VDD(H level). Thus, the voltage Vc of the first capacitor32at this time is also set to VDD. Accordingly, the clock signal φ0being the output voltage signal of the comparator26is set to H level.

Subsequently, at time t3, the first switch52is shorted, and the second switch54is opened. Then, the first capacitor32is disconnected from the positive phase output terminal of the D-FF20, and extraction of charge from the first capacitor32is started by the voltage controlled current source48. Thus, the voltage Vc of the first capacitor starts to decrease. That is, the fall time of the potential Vc of the first capacitor32can be controlled by the control voltage Vcont of the voltage controlled current source48. Here, if the transconductance of the voltage controlled current source48is K (>0), the current I48can be expressed as K·Vcont. The second input terminal26bof the comparator26is supplied with Vcp as a reference voltage. When the potential Vc of the first capacitor32is lowered to the reference voltage Vcp at time t4, the clock signal φ0being the output voltage signal of the comparator26turns to L level.

Even if the clock signal φ0turns to L level, the state of the first switch52and the second switch54remains unchanged. Thus, the voltage Vc of the first capacitor32continues to change toward the ground potential (L level). This state continues until the occurrence of the reset signal Vrst issued in synchronization with the next rise of the delayed PWM signal VPWM. At time t5, the state turns to H level like the state at time t2. Thus, the positive pulse duty cycle D of the clock signal φ0in this case is (t4−t2)/Ts.

In the case where the positive pulse duty cycle of the clock signal φ0being the output voltage signal of the comparator26is larger than a prescribed value (e.g., 50%), the feedback circuit34acts to raise the control voltage Vcont. If the control voltage Vcont is raised, the fall time of the voltage Vc of the first capacitor32is made shorter. Thus, the positive pulse duty cycle of the clock signal φ0is decreased and matched with the prescribed value. On the other hand, in the case where the positive pulse duty cycle of the clock signal φ0is smaller than the prescribed value (e.g., 50%), the feedback circuit34acts to lower the control voltage Vcont. If the control voltage Vcont is lowered, the fall time of the voltage Vc of the first capacitor32is made longer. Thus, the positive pulse duty cycle D of the clock signal φ0is increased and matched with the prescribed value.

For instance, it is assumed that the feedback circuit34includes a charge pump36and a second capacitor46, and that the charge pump36is connected to the output terminal26cof the comparator26. Consider the case where the positive pulse duty cycle D of the clock signal φ0being the output voltage signal of the comparator26inputted to the charge pump36is smaller than the prescribed cycle (e.g., 50%). When φ0is at H level, the first current source40is turned on, and the second current source42is turned off. On the other hand, when φ0is at L level, the second current source42is turned on, and the first current source40is turned off. Consider the change of Vcont during one period of the clock signal φ0. The negative pulse width of the clock signal φ0is larger than its positive pulse width. Thus, the average output current of the charge pump36serves as a sink current, and increases the accumulated charge of the second capacitor46. This results in lowering the control voltage Vcont and decreasing the current I48of the voltage controlled current source48. Thus, the fall time of the voltage Vc of the first capacitor32is made longer. Accordingly, the positive pulse duty cycle D of the clock signal φ0can be increased and made close to the prescribed cycle (e.g., 50%).

On the other hand, consider the case where the positive pulse duty cycle D of the clock signal φ0being the output voltage signal of the comparator26inputted to the charge pump36is larger than the prescribed cycle (e.g., 50%). Consider the change of Vcont during one period of the clock signal φ0. The positive pulse width of the clock signal φ0is larger than its negative pulse width. Thus, the average output current of the charge pump36serves as a source current, and decreases the accumulated charge of the second capacitor46. This results in raising the control voltage Vcont and increasing the current I48of the voltage controlled current source48. Thus, the fall time of the voltage Vc of the first capacitor32is made shorter. Accordingly, the positive pulse duty cycle D of the clock signal φ0can be decreased and made close to the prescribed cycle (e.g., 50%).

Thus, depending on the duty cycle D of the clock signal φ0, the feedback circuit34controls the charge pump36, and controls the control voltage Vcont of the voltage controlled current source48to constitute a negative feedback circuit. Accordingly, in the case where the pulse sequence of the delayed PWM signal VDPWMis inputted to the clock regeneration circuit10, the duty cycle D of the clock signal φ0converges to the prescribed cycle (e.g., 50%) and leads to the steady state. As a result, a clock signal having period Ts with the duty cycle D being the prescribed cycle (e.g., 50%) can be generated.

Most of the current consumed in the first embodiment occurs in charging and discharging the first capacitor32. In one period Ts, the first capacitor32charges and discharges a charge of C×VDD. Thus, the consumption current IDDcan be approximated by equation (1).
IDD=C×VDD/Ts(1)

The values of the power supply voltage VDDand the period Ts are determined by the purpose of the system. Thus, the consumption current IDDcan be reduced by reducing the capacitance C. The lower limit value of the capacitance C is not limited by the negative feedback operation. Thus, the capacitance C can be reduced to the value determined by the limit of the semiconductor process (e.g., tradeoff of formation accuracy, leakage current and the like).

In the case where the clock signal φ0is continuously outputted and can be regarded as being in the steady state after a sufficient passage of time, the positive pulse duty cycle D of the clock signal φ0is determined by the sink current source (current source42) and the source current source (current source40) of the charge pump36. In the first embodiment, the absolute values of the sink current and the source current of the charge pump36are set equal. Thus, the positive pulse duty cycle D is 50%. The sink current is denoted by Icp snk, and the source current is denoted by Icp sre. Then, the positive pulse duty cycle D after a sufficient passage of time is expressed by equation (2).
D(t→∞)=1/(1+Icp sre/Icp snk)  (2)

That is, by setting the ratio of Icp sreto Icp snk, the positive pulse duty cycle D of the outputted clock signal φ0is determined. The setting accuracy of the duty cycle D depends on the accuracy of current mirror ratio of the sink current source (current source42) and the source current source (current source40) of the charge pump.

The signal detection circuit58can be constituted by a low-pass filter, inverter elements having an input threshold of 0.25VDDand 0.75VDD, and normal logic elements. In the case where the time constant of the low-pass filter is much larger than the period of the VPWMsignal, the signal is detected by utilizing the fact that the low-pass filter outputs a signal corresponding to the average duty cycle D of the input signal. For instance, if the average duty cycle D of the VPWMsignal is 50%, the low-pass filter output in response to input of the VPWMsignal is 0.5VDD. On the other hand, the low-pass filter output with no input of the VPWMsignal is VDDor the ground potential. Thus, the presence or absence of the input signal can be easily detected by detecting the low-pass filter output by the inverter elements having an input threshold of 0.25VDDand 0.75VDD.

The voltage controlled current source48can be made of e.g. an NMOSFET.

In the case where the PWM signal VPWMis not inputted, the signal detection circuit58is operated to set the circuit to the initial state. When the PWM signal VPWMis inputted, the control voltage Vcont is controlled by the feedback circuit34, and the duty cycle D of the clock signal φ0being the output voltage converges to a prescribed value. Here, in the initial state of the first embodiment, preferably, the output current I48of the voltage controlled current source48is maximized, i.e., the control voltage Vcont is set to the maximum (VDD). That is, the control voltage Vcont is generally lowered with the passage of time.

The reset signal Vrst can be generated in synchronization with the rise of the PWM signal VPWM. The clock signal φ0being the output voltage signal of the comparator26is switched from H level to L level in the time during which the potential Vc of the first capacitor32is lowered to generally 0.5VDD.

If the capacitance Ccp of the second capacitor46is made larger and the current Icp of the charge pump circuit is made smaller, then the variation ΔVcont of the control voltage Vcont in one period Ts of the PWM signal VDPWMcan be approximated by equation (3) as the sum of the increase during time t2-t4 at H level and the decrease during time t4-t5 at L level.
ΔVcont=D×Ts×Icp/Ccp−(1−D)×Ts×Icp/Ccp=(2D−1)×Icp/Ccp(3)

Here, it is assumed that the absolute values of the sink current and the source current are equal and set to Icp. When the time t becomes sufficiently large, the variation ΔVcont of the control voltage Vcont comes close to zero by the function of the feedback circuit34, and the control voltage Vcont converges to a fixed value. Thus, it is found from equation (3) that, irrespective of the current value Icp and the capacitance Ccp of the second capacitor46, the duty cycle D of the output voltage signal comes close to 0.5.

FIG. 4Ais a block diagram of a clock regeneration circuit of a second embodiment.FIG. 4Bis a timing chart thereof.

As shown inFIG. 4A, in the second embodiment, the first input terminal26aof the comparator26is inputted with the negative phase output from the output terminal20d(denoted by Q−) of the D-FF20. Simultaneously, the voltage controlled current source49is connected in the direction of charging the first capacitor32.

That is, as shown inFIG. 4B, at time n, the reset signal Vrst synchronized with the rise of the PWM signal VPWMis issued from the reset signal generation circuit22and inputted to the reset terminal20eof the D-FF20. Thus, the positive phase output of the D-FF20is set to L level, and the negative phase output is set to H level. Then, after a fixed time, the reset state is canceled. At this time, the first switch52is short, and the second switch54is open. Thus, the voltage Vc of the first capacitor32is not affected. At time t2, the PWM signal VDPWMdelayed by the first delay time td1 is inputted to the clock terminal20aof the D-FF20. The input terminal20bof the D-FF20is connected to power supply. Thus, in synchronization with the rise of the delayed PWM signal VDPWM, the negative phase output turns to L level. Here, the first delay time td1 is set so that Vrst has been canceled at the rise time of VDPWM. In synchronization with the fall of the negative phase output of the D-FF20, the first switch52is opened, and the second switch54is shorted. This state continues for the duration of the second delay time td2. During this time, the voltage Vc of the first capacitor32is equipotential to the negative phase output of the D-FF20. At time t3 after the second delay time td2 from time t2, the potential of the negative phase output of the D-FF20is at the ground potential (L level). Thus, the voltage Vc of the first capacitor32at this time is also set to the ground potential. Accordingly, the clock signal φ0being the output voltage signal of the comparator26is set to L level.

Subsequently, at time t3, the first switch52is shorted, and the second switch54is opened. Then, the first capacitor32is disconnected from the negative phase output terminal of the D-FF20, and charging to the first capacitor32is started by the voltage controlled current source49. Thus, the voltage Vc of the first capacitor32starts to increase. That is, the rise time of the potential Vc of the first capacitor32can be controlled by the control voltage Vcont of the voltage controlled current source49. Here, if the transconductance of the voltage controlled current source49is K (>0), the current I49can be expressed as K·(VDD−Vcont). The second input terminal26bof the comparator26is supplied with Vcp as a reference voltage. When the potential Vc of the first capacitor32is raised to the reference voltage Vcp at time t4, the clock signal φ0being the output voltage signal of the comparator26turns to H level.

Even if the clock signal φ0turns to H level, the state of the first switch52and the second switch54remains unchanged. Thus, the voltage Vc of the first capacitor continues to change toward the power supply potential (H level). This state continues until the occurrence of the reset signal Vrst issued in synchronization with the next rise of the delayed PWM signal VDPWM. At time t5, the state turns to L level like the state at time t2. Thus, the positive pulse duty cycle D of the clock signal φ0in this case is (t5−t4)/Ts.

In the case where the positive pulse duty cycle D of the clock signal φ0being the output voltage signal of the comparator26is larger than a prescribed value (e.g., 50%), the feedback circuit34acts to raise the control voltage Vcont. If the control voltage Vcont is raised, the rise time of the voltage Vc of the first capacitor32is made longer. Thus, the positive pulse duty cycle D of the clock signal φ0is increased and matched with the prescribed value. On the other hand, in the case where the positive pulse duty cycle D of the clock signal φ0is smaller than the prescribed value (e.g., 50%), the feedback circuit34acts to lower the control voltage Vcont. If the control voltage Vcont is lowered, the rise time of the voltage Vc of the first capacitor32is made shorter. Thus, the positive pulse duty cycle D of the clock signal φ0is increased and matched with the prescribed value.

Here, in the initial state of the second embodiment, preferably, the output current I49of the voltage controlled current source49is maximized, i.e., the control voltage Vcont is set to the minimum (ground potential). That is, the control voltage Vcont is generally raised with the passage of time. After a sufficient passage of time, the control voltage Vcont converges toward a fixed value. That is, the positive pulse duty cycle D of the clock signal φ0converges toward the prescribed value (e.g., 50%).

The D-FF20may have a set terminal instead of the reset terminal. Moreover, the clock regeneration circuit may have a set signal generation circuit instead of the reset signal generation circuit22.

FIG. 5Ais a block diagram of a photocoupler including a light receiving circuit including the clock regeneration circuit according to the first and second embodiments.FIG. 5Bis an operation timing chart of the light receiving circuit.

As shown inFIG. 5A, the light receiving circuit69includes e.g. a light receiving element (PD)66, a transimpedance amplifier (TIA)67, a clock regeneration circuit10, a delay-locked loop (DLL) circuit60, and a demodulation circuit68. Furthermore, a light emitting element64modulatable by an input signal VIN PWMcan be optically coupled to the light receiving circuit69to constitute a photocoupler.

The light emitting element64emits an optical signal modulated by the input PWM signal VIN PWM. The emitted optical signal is converted to a current signal Ip by the light receiving element66, and amplified by the transimpedance amplifier (TIA)67and the like. Thus, the current signal Ip is converted to a PWM (voltage) signal VPWM. The PWM signal VPWMis inputted to the clock regeneration circuit10, which outputs a delayed PWM signal VDPWMand a clock signal φ0. Polyphase clocks synchronized with the clock signal φ0are generated in the DLL circuit60and inputted to the demodulation circuit68. The demodulation circuit68determines the delayed PWM signal VDPWMat the polyphase clock timing to demodulate the digital data modulated on VDPWM. Such a configuration can realize a photocoupler in which input/output is electrically insulated and a high-accuracy analog electrical signal can be transmitted.

Here, the PWM signal can also be transmitted/received by an electric field coupled system or a magnetically coupled system without the intermediary of an optically coupled system.

By changing the pulse width of the PWM signal, “0” and “1” signals as binary data can be assigned thereto.

As shown inFIG. 5B, it is assumed that the average duty cycle D of the PWM signal VPWMis 50%, and signals having a pulse width of Ts/4, 2Ts/4, and 3Ts/4 are demodulated. For instance, the binary data “1” is modulated to 2Ts/4, and the binary data “0” is modulated to Ts/4 and 3Ts/4 with a probability of 50%. Then, irrespective of the binary data, the duty cycle of the VPWMsignal is 50%. That is, a 0.5-bit worth is used to fix the average duty cycle.

In the case where the pulse width of the PWM signal VPWMhas three levels, eight kinds of polyphase clocks are preferably used for demodulation. That is, the DLL circuit60performs control so that the delay difference period between φ0and φ8is Ts. Thus, when the PWM signal VDPWMdelayed by the clock signals φ3(corresponding to a time of 3Ts/8) and φ5(corresponding to a time of 5Ts/8) is detected, the hold time is maximized, and the digital data can be stably demodulated.

In general, in the case where one period of the PWM signal VPWMcontains K bits (K being an integer) of information, the pulse width of VPWMhas 2K levels. In this case, the hold time in the demodulation circuit can be maximized by preparing 2×(2K+1) kinds of polyphase clocks.

FIG. 7is a block diagram of a frequency synthesizer based on the first and second clock regeneration circuits.

The frequency synthesizer includes the clock regeneration circuit10of the first to third embodiments, and a phase locked loop (PLL) circuit80.

The PLL circuit80includes a phase comparator70having a first input terminal70aand a second input terminal70b, a loop filter72for smoothing the output from the phase comparator70, a voltage controlled oscillator (VCO)74, and a frequency divider76for lowering the frequency of the output signal of the VCO74to 1/N (N being an integer) for input to the second terminal70bof the phase comparator70.

The PLL circuit80produces a signal corresponding to the phase difference between the clock signal inputted to the first input terminal70aand the output signal of the frequency divider76inputted to the second input terminal70b. The PLL circuit80inputs the signal corresponding to the phase difference to the loop filter72. The loop filter72smoothes the signal for output to the VCO74. The VCO74can control the oscillation frequency by the input voltage signal. The frequency divider76lowers the output frequency of the VCO74to 1/N for input as a feedback to the second terminal70bof the phase comparator70. Thus, the frequency divider76performs control so that the signals at the first input terminal70aand the second input terminal70bare matched.

In the case where the PLL circuit80normally converges, the VCO74outputs, from the output terminal78, an output voltage signal having a frequency equal to N times the frequency of the clock signal and synchronized with the clock signal. In the case of demodulation, by using a counter circuit and the like, the phase difference between the PLL output signal and the PWM signal VPWMcan be calculated to determine the pulse width of the PWM signal VPWM. In the case where the digital signal contained in the PWM signal VPWMis of 1.5 bits, the hold time is maximized in the demodulation circuit68by setting N=8. On the other hand, in the case where the PWM signal VPWMcontains K bits (K being an integer) of information, the hold time is maximized in the demodulation circuit68by setting N=2×(2K+1).

Because the PLL circuit80includes a loop filter72, the PLL circuit80can suppress jitter in the input signal. Furthermore, the duty cycle D of the signal inputted to the PLL circuit80can be kept at a prescribed cycle. Thus, the frequency synthesizer of the present embodiments can enhance the frequency pulling performance of the VCO74and stably operate the PLL circuit80.