Interconnect using embedded carbon nanofibers

Embodiments relate to the design of a device capable of increasing the electrical performance of an interconnect feature by amplifying the current carrying capacity of an interconnect feature. The device comprises a first body comprising a first surface with at least one nanoporous conductive structure protruding from the first surface. The device further comprises a second body comprising a second surface with arrays of nanofibers extending from the second surface and penetrating into corresponding nanoporous conductive structures to form conductive pathways between the first body and the second body.

BACKGROUND

The present disclosure relates to an interconnect for connecting conductive portions in electronic components, and in particular to, interconnects of one or more carbon nanofiber structures to connect conductive portions in the electronic components.

As pitch sizes of electronic devices have decreased, techniques involved in the development of such devices have also evolved in order to maintain their performance capability. However, with this increased performance, additional constraints on the electric power and thermal distribution of the semiconductor device have been discovered. As the system performance of a device increases, the density of the interconnect feature also increases, and, as a result, each interconnect feature is limited to usage at specific technology nodes in one particular semiconductor material.

More specifically, different device technologies may be associated with different connective properties which constrain the techniques which can be used in additive processing. For example, the connectivity of GaN devices to silicon technologies has thermal limits to incorporating one layer. GaN layers are generally deposited around a temperature of 1000° C., whereas silicon technologies often have a thermal limitation of approximately 400° C. As a result, conventionally, the two materials must be formed separately and joined together to form the final interconnect feature.

However, as the pitch, or size, of an interconnect feature decreases, conventional techniques are no longer as effective. For smaller interconnect features, adjoining materials requires a greater capacity for thermal expansion, which means with lower interconnect temperatures, additional bonding may be required for materials with lower bonding temperatures, further complicating the design process. Moreover, interconnect features of smaller pitch sizes will have different electrical characteristics than the same bulk material, for example a higher electrical resistance due to the reduced geometry of the material which causes a decrease in the electrical performance of the interconnect, for example the current carrying capacity. As a result, there exists a need for a technique for designing small interconnect features which accounts for technical considerations, such as thermal limitations and increased resistance readings.

SUMMARY

Embodiments relate to an interconnect feature that includes one or more carbon nanofiber structures, for forming conductive pathways between a first body and a second body. The first body has a surface with at least one nanoporous conductive structure protruding from the first surface. The second body has a surface comprising an array of nanofibers extending from its surface and penetrating into the corresponding conductive structures to form conductive pathways between the first body and the second body. In some embodiments, the first body is a driver chip and the second body is a substrate onto which the chip is mounted.

Each carbon nanofiber is metallic such that the current carrying capacity of the interconnect feature is improved after penetrating the nanoporous conductive material. Due to their physical properties, each carbon nanofiber penetrates the nanoporous material when aligned and after the application of pressure.

When adjoined with the carbon nanofibers, the nanoporous conductive structures compress to a height that allows the tip of each carbon nanofiber to make contact with the first surface of the first body. By integrating an electrically conductive material into the conductive structures, the ampacity of the interconnect feature increases, therefore accommodating a larger current flow. In turn, the larger current flow offsets the increase in electrical resistance.

DETAILED DESCRIPTION

Embodiments relate to an interconnect feature including carbon nanofiber structures extending from a body and nanoporous conductive structures on another body where the nanofiber structures penetrate the nanoporous conductive structures to form a connection. The interconnect feature formed in this matter accommodates a larger current flow through the interconnect feature. The nanofiber arrays may be formed of carbon nanofibers (CNF) and the conductive structures may be formed of nanoporous gold (NPG) structures.

As used herein, a body of the interconnect feature refers to an electrical component. In one implementation, one of the bodies may be a chip and the other body may be a substrate on which the chip is mounted.

Conductive Bodies of the Interconnect Feature

FIG. 1Ais a perspective view illustrating an array of carbon nanofibers (CNF) formed on a silicon substrate, according to an embodiment. As illustrated inFIG. 1A, the substrate110has multiple conductive pads125, each aligned with other conductive pads125over the horizontal and vertical axis of the substrate110. Grown on each conductive pad125is an array of CNFs120extending away from the surface of the conductive pads125. In the illustrated embodiment ofFIG. 1, each CNF is conically shaped such that the end connected to the conductive pad125is a wider than the end pointing away from the conductive pad125(e.g., a needle-like shape). In alternate implementations, the CNFs115may be shaped differently. Areas of the silicon substrate110other than the conductive pads125are not formed with the CNFs120.

In some embodiments, CNFs115are structurally rigid (e.g., elastic modulus within the range of 25 to 48 GPa) compared to the nanoporous metals (e.g., elastic modulus of nanoporous gold is 2 GPa or lower) that form the nanoporous conductive structures mounted to the first body. As a result, the arrays of CNFs120are able to penetrate the nanoporous metal structures when aligned and pressured into contact. Compositionally, CNFs115may be metallic, rather than semi-conductive, to improve the conductivity of the interconnect feature. In some embodiments, the CNFs115are replaced with alternative structures, for example, carbon nanotubes (CNT), or carbon nano-spheres.

In one embodiment, the conductive pads125are placed in a regular pattern. In other embodiments, the conductive pads125are placed in an irregular pattern. The conductive pads125may all be of the same size and shape. Alternatively, the conductive pads125may be of different sizes and shapes. Furthermore, the number of CNFs115in each of the conductive pads125may be the same or different.

The CNF arrays120are grown on the surface of the body (e.g., silicon substrate110or another electrical component) at a temperature within the range of 350° C. to 400° C. In one embodiment, one or more carbon nanofibers are deposited on the surface of an electrical component (i.e., silicon substrate110) using a plasma enhanced chemical vapor deposition process (PECVD). In alternate implementations, the carbon nanofibers are deposited using alternate growth techniques. During growth, individual CNFs are mounted to conductive pads125such that each conductive pad125corresponds to an array of CNFs120. Within the above temperature range, CNFs115may be grown directly on the same surface of the body (i.e., the silicon substrate110) as the conductive pads125which may be fabricated using a silicon complimentary metal-oxide semiconductor (CMOS) without causing physical damage to the driver chip or silicon substrate. Conventional techniques do not allow for the implementation of such high processing temperatures.

After CNFs115are grown, an average CNF115array may have an average diameter within the range of 50 nanometers, but not exceeding 1 micrometer. This range of diameters is advantageous, among other reasons, because, at this diameter, multiple CNFs115may be incorporated into the nanoporous metal structures mounted to the second body. Incorporating multiple carbon nanofibers into a single nanoporous metal structures improves the overall performance of the interconnect. Additionally, a CNF115may have a height within the range of 50 to 75 micrometers while maintaining its structural integrity. This range of heights is advantageous, among other reasons, because, within this range of heights, the interconnect feature may be designed at the same full height as the tallest carbon nanofiber such that the entire carbon nanofiber embeds into the corresponding nanoporous metal structure to allow connectivity between the first and second surface. In some embodiments, CNFs115may grow to a height within the range of 1 to 1.5 micrometers.

CNFs115in the array120may be spaced over the conductive pads125such that individual CNFs do not grow within a proximity of other fibers of the array. In one embodiment, each CNF115is positioned at the same distance in the X and Y directions away from adjacent CNFs. In one embodiment, a growth catalyst is applied to the surface of the body from which the CNFs extend, for example Fe, Ni, Co, to facilitate or expedite the growth of the CNF arrays120. The growth catalyst may be applied at the tip of CNF115during growth. The growth catalyst may be incompatible with other surfaces or materials and accordingly may be removed prior to the adjoining of the CNFs115with a metallic conductor at a second substrate by using surface polishing techniques or by flycutting the surface using a tool, for example a diamond coated cutting tool.

FIG. 1Bis a perspective view illustrating an array of nanoporous metal structures on a GaN chip, according to an embodiment. As illustrated inFIG. 1B, the second body (i.e., GaN chip150) has multiple conductive pads125, each aligned with other conductive pads125of the chip150in X and Y direction. Mounted to each conductive pad125is a nanoporous metal structure160extending away from the surface of the conductive pads125. In the illustrated embodiment ofFIG. 1B, each nanoporous metal structure160is cylindrically shaped such that the areas of both the face mounted to the conductive pad125and the face extending away from the chip150are larger than the area of the corresponding array of CNFs120(i.e., when the silicon substrate110and the GaN chips150are adjoined, all of CNF115in the array120penetrate into the nanoporous metal structure160).

GaN chip150is a substrate that mechanically supports and electrically couples the electronic components using conductive structures (e.g., nanoporous metal structures160). The chip150may include circuits that are completed once one or more substrates110are placed onto the chip150. In some embodiments, the chip150carries an amplified amount of current when the tips of the CNFs115penetrate the nanoporous metal structures160to make contact with the conductive pads125mounted to the chip150.

In alternate embodiments, the nanoporous metal structures160may be shaped differently to accommodate an array of CNFs120. The number of nanoporous metal structures160on a body (e.g., the GaN chip150) is proportional to the number of arrays of CNFs120on the corresponding body (e.g., the silicon substrate110) to which the former is adjoined. For example, the number of nanoporous metal structures160mounted to the GaN chip150is equivalent to the number of arrays of CNFs120such that each array120may adjoin with a nanoporous metal structure160.

In embodiments in which the nanoporous metal structures160comprise nanoporous gold, the nanoporous gold structures are fabricated using selective dissolution (also known as dealloying). For example, the nanoporous gold structure160can be fabricated by dealloying Au-based alloy, e.g., Au—Ag alloy. Tertiary alloy compositions such as Au—Ag—Pt could also be employed. During the dealloying process, Ag is removed from the alloy in a strong corrosive environment, producing an open pore network structure that consists mostly of Au. Morphology of the nanoporous gold structure may be further modified by thermal treatment. For example, the nanoporous gold structure may be heated to increase the surface diffusion of gold atoms and resultantly increase average pore size. In addition or alternatively to nanoporous gold, the structures160may include one or more different type of nanoporous metal, for example, nanoporous silver, nanoporous copper, another single, binary, or tertiary metallic species, or some combination thereof. In some embodiments, the nanoporous conductive structures may be fabricated using a non-metal nanoporous material.

To prevent buckling or breaking of CNFs115, the height of each nanoporous metal structure160may be greater than the height of the tallest CNF115in an array120. When pressure is applied to adjoin an array of CNFs120to a nanoporous metal structure160, the height of the each nanoporous metal structure decreases due to the compression of the nanoporous metal.

In alternative embodiments (not shown), both the CNFs115and the nanoporous metal structures are mounted to the same body of the interconnect feature, for example the silicon substrate110or the GaN chip150, and the second body of the interconnect feature includes metal bond pads to which the nanoporous metal-CNF structures of the first body would couple to establish an electrical connection, for example a nanoporous gold or nanoporous copper bond bad would be implemented with nanoporous metal structures. The metal bond pads would be positioned on the second body in a uniform or non-uniform pattern depending on the positioned on the nanporous metal-CNF structures on the first body. In one embodiment, the number of metal bond pads on the second body is proportional to the number of nanoporous metal-CNF structures, for example a 1:1 ratio. To form the nanoporous metal-CNF structures, the techniques described above in reference toFIGS. 1A and 1Bmay be implemented such that the nanoporous metal structures are formed as coatings over the CNFs grown on the conductive pads of the first body. CNFs are grown on the body prior to the formation of the nanoporous metal structures on the same body. In one embodiment, the CNFs are grown on the surface of the first body and coated with the nanoporous metal before the second body is bonded to the first body. Using a thin metal coating to pre-plate the CNFs may be used to improve the overall performance of the interconnect feature.

Adjoining Carbon Nanofibers to Nanoporous Gold Structures

FIGS. 2A-2Care cross-sectional views illustrating a process of adjoining CNFs with nanoporous gold structures, according to an embodiment.FIG. 2Aillustrates the initial positioning of substrate110and chip150prior to being adjoined, according to an embodiment. The nanoporous metal structures160and the array of CNFs120are not in contact, but are aligned such that if either surface were moved towards the other along a linear path, each array of CNFs120would make contact with a nanoporous metal structure160. The movement of either the substrate110or the chip150to align the CNFs120and nanoporous metal structure160may be made, for example, by a mount310, as described below with reference toFIG. 3.

FIG. 2Billustrates an updated position of the substrate110relative to the GaN chip150where the arrays of CNFs120are moved closer to the nanoporous metal structures160, according to one embodiment. At the position illustrated inFIG. 2B, the tips of the CNFs115are at first contact with the nanoporous metal structures160. At such a position, the nanoporous metal structures160individually begin to penetrate the corresponding nanoporous metal structures160, and in the process, also compress the nanoporous metal structures160.

FIG. 2Cillustrates a completed example device including a substrate110connected to multiple arrays of CNFs120at conductive pads125, according to one embodiment. The device may be for example, a micro light emitting diode (LED) assembly including a GaN chip150. The substrate110may include a conductive trace and/or electrical circuit (not shown inFIG. 2A-C) to provide an electrical current to the GaN chip150.

As illustrated, each CNF115is embedded into a nanoporous metal structure160to improve the electrical performance of the device. Due to their electrical conductivity properties, when in contact with each other, the arrays of CNFs120and nanoporous metal structures160compensate for the increased resistance of the interconnect feature by increasing the current carrying capacity of the interconnect feature.

In one or more embodiments, an adhesive underfill layer is applied at the junction between each CNF115and nanoporous metal structure160to improve the adhesion between the substrate110and the chip150. The underfill layer may be applied after each CNF has been completely immersed in nanoporous metal structure160. Alternatively or in addition, the underfill layer may be applied to surfaces of chip150and substrate110to form a partially cured adhesive that will become fully cured during the process of applying pressure and temperature to form the final junction between the nanoporous metal structures of the chip150and the CNFs of the substrate110. In some embodiments, the two bodies may be applied with heat, for example by increasing the temperature, to enable the CNFs115to penetrate the nanoporous metal structures160with greater ease.

As described above in reference toFIG. 1B, before coupling an array of nanoporous metal structures160with an array of CNFs120, the height of each nanoporous metal structure160is greater than that of the corresponding CNFs120. After applying pressure to the side of the substrate110opposite the arrays of CNFs120, the final height of the adjoined nanoporous metal CNF structure may be equal to the height of the tallest CNF115of the array120. As a result, the extruding point of each CNF115makes contact with a conductive pad125mounted to the GaN chip150and the surface of the NPG structure160makes contact with the corresponding conductive pad125mounted to the substrate110.

Although embodiments described above with reference toFIGS. 1A-2Chave nanoporous metal structure160formed on the chip150and the array of CNFs120on the substrate110, in other embodiments, the nanoporous metal structure can be formed on the substrate110and the CNFs120can be formed on the chip150. In additional embodiments, the CNFs and the nanoporous metal structures can be formed at different locations of the substrate while corresponding nanoporous metal structures and CNFs can be formed on the chip.

Mechanism for Adjoining Carbon Nanofibers and Nanoporous Metal Structures

FIG. 3is a block diagram illustrating components for adjoining CNFs with nanoporous metal structures, according to an embodiment. The components include, among others, a mount310, an actuator320operating the mount310, a computer330and a sensor340. The mount310is attached to the substrate110and places the substrate110onto the chip150by aligning the array of CNFs120of the substrate110with the nanoporous metal structures160of the GaN chip150. If a voltage difference is applied between the CNFs115and if the substrate110is properly placed, the substrate110conducts current through nanoporous metal structures160to the chip150. CNFs

The sensor340detects the alignment of the chip150and the substrate110and may also detect the distance between the surface of the substrate110with the conductive pads125and the surface of the chip150with the nanoporous metal structures160. The sensor340generates image signals that function as real time feedback to update the position of the substrate110during the coupling process. The sensor340sends measurement signals342to the computer330. Although only a single sensor340is illustrated inFIG. 3, multiple sensors can be used to detect the alignment and the distance between the substrate110and the chip150.

The sensor340may be an image capturing device that captures the images of the substrate110to determine whether the tips of each CNF115have made contact with the conductive pads125of the chip150. In alternative embodiments, the sensor340may detect a distance between interior facing surface of the substrate110and the interior facing surface of the chip150. As the actuator moves the substrate110closer to the chip150, the sensor340periodically updates the spatial measurement until the measurement is within a threshold distance. After detecting a threshold distance, the sensor340may cause the actuator320to stop the movement of the mount310.

Using the measurement signals342, the computer330sends control signals332to the actuator320. The actuator320is attached to the mount310and provides instructions for the mount310to apply pressure to exterior facing surface of the substrate110such that the arrays of CNFs120move closer to the NPG structures160.

The mount310moves the substrate110according to the movement of the actuator320to place the substrate110onto the chip150. The mount310can support any number of substrates110and can place multiple substrates onto the chip150at once. In some embodiments, the sensor340is placed on top of the mount310that is transparent to allow the sensor340to capture alignment of the array of CNFs120and the NPG structures160.

The actuator320is coupled to the mount310and controls movement of the mount310. By moving the mount310, the actuator120aligns the mount310and the substrate110with the chip150by aligning the arrays of CNFs120with the nanoporous metal structures160. In some embodiments, the actuator320is a multiple degree of freedom actuator, such as an actuator that is configured to move the mount310up and down, left and right, forward and back. The actuator320may also adjust yaw, tilt, or rotate the mount310. In some embodiments, multiple actuators320couple to multiple mounts319to perform substrate110position tasks in parallel to increased throughput.

The computer330controls the overall operation of joining the substrate110and the chip150. For this purpose, the computer330provides control signals332to the actuator320and receives the measurement signals342received from the sensor340. The computer330is further described with reference toFIGS. 4-5.

In some embodiments, the apparatus comprises a heat plate (not shown inFIG. 3) capable of controlling the temperature of the chip150by heating or cooling the substrate110. This may be advantageous for bonding the arrays of CNFs120to the nanoporous metal structures160.

FIG. 4is a block diagram of the computer330for performing the operation of adjoining the CNFs with nanoporous metal structures, according to an embodiment. The computer330may include, among other components, a processor410, a memory420, a user interface430, a control interface440, a video interface450and a bus460connecting these components. Some embodiments of the computer330have different and/or other components than those shown inFIG. 2.

The computer330may be a personal computer (PC), a video game console, a tablet PC, a smartphone, or any machine capable of executing instructions (sequential or otherwise) that specify actions to be taken by that device. The computer330can operate as a standalone device or a connected (e.g., networked) device that connects to other machines. Furthermore, while only a single device is illustrated, the term “device” shall also be taken to include any collection of devices that individually or jointly execute instructions to perform any one or more of the methodologies discussed herein.

The processor410is a processing circuitry configured to carry out instructions stored in the memory420. For example, the processor410can be a central processing unit (CPU) and/or a graphics processing unit (GPU). The processor410may be a general-purpose or embedded processor using any of a variety of instruction set architectures (ISAs). Although a single processor410is illustrated inFIG. 4, the computer330may include multiple processors410.

The memory420is a non-transitory machine-readable medium which stores data and instructions (e.g., software) embodying any one or more of the methodologies or functions described herein. For example, the memory420may store instructions which when executed by the processor410configure the processor410to perform the method, described below in detail with reference toFIG. 6. Instructions may also reside, completely or at least partially, within the processor410(e.g., within the processor's cache memory) during execution thereof by the computer330.

The user interface430is hardware, software, firmware, or a combination thereof that enables a user to interact with the computer330. The user interface430can include an alphanumeric input device (e.g., a keyboard) and a cursor control device (e.g., a mouse, a trackball, a joystick, a motion sensor, or other pointing instrument). For example, a user uses a keyboard and mouse to select position parameters for position a substrate110on the chip150.

The control interface440transmits control signals to the actuator320. For example, the control interface440is a circuit or a combination of circuits and software that interfaces with the actuator320to transmit the control signals.

The video interface450is a circuit or a combination of circuit and software that receives image data via the measurement signals from the sensor340and transfers the image data to the memory420and/or processor410to be stored and processed.

The computer330executes computer program modules for providing functionality described herein. As used herein, the term “module” refers to computer program instructions and/or other logic used to provide the specified functionality. Thus, a module can be implemented in hardware, firmware, and/or software. In some embodiments, program modules formed of executable computer program instructions are loaded into the memory420, and executed by the processor410. For example, program instructions for the method ofFIG. 6described herein can be loaded into the memory420, and executed by the processor410.

FIG. 5is a block diagram of software modules in the memory of the computer, according to one embodiment. The memory420may store, among other modules, an actuator control module302, a temperature control module304, a vision recognition module306, and a parameter adjuster module308. The memory204may include other modules not illustrated inFIG. 3.

The actuator control module520provides instructions for generating control signals to control the actuator320to adjust one or more position parameters. The position parameters relate to the positions of one or more substrates110on the chip150. The position parameters include a position location, a position angle, a position pressure, a position temperature, and a position time. The position location is the location of the substrate110relative to the chip150. The position angle is the angle of the substrate110relative to the chip150and, more specifically, the angle of the CNFs115relative to the nanoporous metal structures160. The position pressure is the pressure applied to the substrate110by the mount310once it is placed on the chip150. The position time is the amount of time that the position pressure and the position temperature are applied to the substrate110. The position temperature is the temperature of the chip150or a temperature change of the chip150during the position of the substrate110.

The vision recognition module530performs analysis on the measurement data to measurement signals to determine the position of the substrate110. Specifically, the vision recognition module530determines whether the position of the substrate110fails one or more criteria. The criteria form a standard for determining proper position of one or more substrates110. The position of the substrate110may fail under the criteria for any number of reasons, such as, for example, a substrate110is placed at an incorrect position location, position angle, position time, position pressure, position temperature, etc.

The temperature control module540sets the position temperature by controlling the temperature, for example using a heat plate. In some embodiments, the position parameters also include heating ramp shape, underfill or flux behavior, the influence of lateral movements (e.g. caused by thermal expansion) on position formation, the influence of metal oxides, allowable pressure range, and allowable temperature range.

Process for Adjoining Carbon Nanofibers and Nanoporous Metal Structures

FIG. 6is a flow chart describing the process for adjoining CNFs with nanoporous metal structures, according to an embodiment. The process may include different or additional steps than those described in conjunction withFIG. 5in some embodiments or perform steps in different orders than the order described in conjunction withFIG. 5.

As illustrated inFIGS. 2A-2C and 3, the first body of the interconnect feature (i.e., substrate110) on which the arrays of CNFs120are grown is positioned610such that the arrays of CNFs120are oriented towards a second body to which the nanoporous metal structures are mounted (i.e., GaN chip150). The second body is positioned620such that one or more nanoporous metal structures160are oriented towards the first body. The position of the first body is moved630such that the distance between the two bodies decreases. Accordingly, as the first body moves closer to the second body, the tips of the arrays of CNFs120come in contact with the opposing nanoporous metal structures160. In one embodiment, the body to which the array of nanoporous metal structures are mounted is held at a fixed position relative to the movement of the other body. In an alternate embodiment, the body including the nanoporous metal structures is also adjusted by a second actuator while the position of the other body is simultaneously adjusted by the first actuator. The position of the body on which the CNFs115are grown is moved640until the CNFs115make contract with the conductive pads mounted to the other body.

In some embodiments, the arrays of CNFs120and the nanoporous metal structures are mounted to the opposite bodies of the interconnect feature compared to the above description, for example the arrays of CNFs120grown on the GaN chip150and the nanoporous metal structures160grown on the substrate110. In additional embodiments, the actuator may adjust the position of the body to which the nanoporous metal structures are mounted while holding the body on which the CNFs are grown at a fixed position. Regardless of the orientation of the nanoporous metal structures and the CNFs or the surface adjusted by the actuator, the device created by coupling a nanoporous metal structure160and an array of CNFs120is consistent with the above description. Additionally, the GaN chip150may be replaced with an alternate electronic element, for example an LED.