FREQUENCY SYNTHESIZER CIRCUIT

A frequency synthesizer circuit for a car radar system is disclosed, the circuit comprising: a phase locked loop for providing a frequency chirp at a range of tuning voltages, said phase locked loop comprising: a phase detector and a voltage controlled oscillator, wherein said phase locked loop has an open loop gain dependent on the tuning voltage and a gain of the voltage controlled oscillator; a first varactor unit for altering the gain of the voltage controlled oscillator over a first subset range of tuning voltages; and a second varactor unit for altering the gain of the voltage controlled oscillator over a second subset range of tuning voltages, wherein the second subset range of tuning voltages is higher than the first subset range of tuning voltages; such that variations in the open loop gain over the first and second subset range of tuning voltages of the range of tuning voltages are compensated for by the varactor units.

The present disclosure relates to a frequency synthesizer circuit for a radar system. In particular, the present disclosure relates to the use of varactors to compensate for variations in the open loop gain of such circuits.

Various example embodiments of systems, methods, apparatuses, devices, articles of manufacture and computer readable mediums for frequency synthesizer circuits are now discussed. Phase locked loops (known as PLLs) are control systems (frequency synthesiser circuits) used to generate output signals. A phase locked loop generates an output signal with a phase related to the phase of a highly accurate input signal (reference signal). A PLL is typically used to ensure that the clock frequencies of signal inputs of various registers and flip-flops match the frequency generated by an oscillator. Without a PLL, clock skew may result in the registers and flip-flops not receiving the clock at the same time.

Traditional analogue PLLs utilise a voltage controlled oscillator (VCO) to provide an oscillating waveform with a variable frequency. The output of the VCO is compared to a reference input signal by a phase detector, which compares the phase of the input and output signals and adjusts the oscillator to keep the phases matched. This acts as a feedback loop.

The frequency of the output may be varied by introducing a divider that allows the output frequency to be a multiplied copy of the lower reference frequency, which is usually insensitive to process voltage and temperature variations. However, this provides the constraint that the oscillator frequency is equal to an integer multiple of the reference frequency. Such analogue circuits are called integer-N frequency synthesisers.

This limitation may be overcome by introducing a modulator or dither to divide the value of the divider to achieve fractional divide values. The resulting variations are smoothed by the PLL using a loop filter. Such analogue PLL's are called fractional-N frequency synthesisers.

The gain of the phase lock loop is a design parameter that is used to optimize the bandwidth, locking time and noise performance of the PLL. For example, both the charge pump gain, KD(PFD/CP gain) and the oscillator gain, Kvco (VCO gain) are parameters that are ideally linear. This is broadly the case in traditional PLLs for the charge pump gain, but for the voltage controlled oscillator gain the gain is typically peaked due to the electrical response of the varactor used to tune the PLL.

The gain of the voltage controlled oscillator operates in this narrow window due to the peak gain response. This is in most applications acceptable since the PLL is locked to one frequency that corresponds to a mid-tune voltage. In systems where the tuned voltage is changing in time, for example to generate frequency chirp, this decrease in Kvco leads to a phase noise variation and linearity variation of this frequency chirp. This is unsuitable in some applications, such as in sensors for car radar systems. In such systems, a frequency synthesiser circuit with a more constant gain profile over the tuning voltage is desirable.

SUMMARY

According to a first aspect of the present disclosure, there is provided a frequency synthesiser circuit for a radar system, the circuit comprising: a phase locked loop for providing a frequency chirp at a range of tuning voltages, said phase locked loop comprising: a phase detector, and a voltage controlled oscillator, wherein said phase locked loop has an open loop gain dependent on the tuning voltage and the gain of the voltage controlled oscillator; a first varactor unit for altering the gain of the voltage controlled oscillator over a first subset range of tuning voltages; and a second varactor unit for altering the gain of the voltage controlled oscillator over a second subset range of tuning voltages wherein the second subset range of tuning voltages is higher than the first subset range of tuning voltages, such that variations in the open loop gain over the first and second subset range of tuning voltages of the range of tuning voltages are compensated for by the varactor units.

The gain of the voltage controlled oscillator is at least partly determined by the varactor units. Accordingly, by altering the characteristics and/or number of varactor units and/or the bias voltages supplied to the varactor units, the gain of the voltage controlled oscillator can be controlled.

Consequently, the varactor units within the voltage controlled oscillator act to alter the gain of the voltage controlled oscillator, which in turn alters the frequency response of the voltage controlled oscillator with respect to the range of tuning voltages supplied to the voltage controlled oscillator. Variations in the supplied frequency response of the voltage controlled oscillator at different applied tuning voltages are therefore reduced.

In embodiments, a charge pump may be provided to supply the tuning voltage either directly or via a loop filter. The charge pump may have a gain that contributes to the overall open loop gain of the phase locked loop.

In other embodiments, a divider may be provided for varying the frequency output at a tuning voltage.

In embodiments, the varactor units may be scaled or sized to alter the voltage controlled oscillator gain that is higher at low and high tuning voltages to compensate for drop-off in the gain of the charge pump. This allows the overall open loop gain of the phase locked loop to remain substantially constant.

By altering the gain of the voltage controlled oscillator, the response of the open loop gain across the sweeping tuning voltage can be flattened, reducing variations across different voltage ranges.

In embodiments, the circuit further comprises a third varactor unit for altering the gain of the voltage controlled oscillator over a third subset range of tuning voltages. In such examples, the third subset range of tuning voltages are generally lower than the second subset range of tuning voltages and higher than the first subset range of tuning voltages. Furthermore, the third varactor may alter the gain of the voltage controlled oscillator by a lower amount than the first or second varactor.

This may be further generalised to an nth varactor unit for altering the gain of the voltage controlled oscillator over an nth subset range of tuning voltages of the range of tuning voltages. It can be appreciated that more of less varactor units may be employed within the voltage controlled oscillator depending upon the required application. Additionally, although shown as pairs of varactors, each varactor unit may be a single varactor biased by a single bias voltage, a triplet of varactors each biased by a single bias voltage, or 4 or more varactors each biased by a single bias voltage. However, as the number of varactor units used increases, the reactance of the circuit increases as well as parasitic which can lead to increased phase noise, so a tradeoff is necessary.

Typically each varactor unit may comprise a pair of varactors biased by a bias voltage. The bias voltage may be generated by a current and a low pass filter. Low pass filters may be used to lower in-band noise.

The amount of compensation in the open loop gain by the varactor units may be dependent upon the size of the varactor unit, such as the capacitance of the varactor unit, and the bias voltage of the varactor unit. This allows the varactor unit to be tailored to compensate over the desired range of the sweeping tuning voltage. For example, the varactor units may compensate for variations in the open loop gain at high and low sweeping tune voltages.

In embodiments, the varactor units contain diodes. Alternatively or additionally, the varactor units may contain capacitors.

In examples, the frequency chirp generated by the phase locked loop relates to a distance measurement for use in a radar system. In such scenarios a stable gain of the voltage controlled oscillator and therefore the open loop gain of the circuit is particular useful in such applications.

In other examples, a divider is provided and implemented with a sigma-delta to obtain a fractional-N phase locked loop. This can allow a greater control of the frequency chirp generated by the phase locked loop. In embodiments, the frequency chirp of the phase locked loop may be generated by changing a division ratio of a divider. Alternatively, or additionally, the frequency chirp of the phase locked loop may be generated by changing an input reference frequency signal.

In a second aspect of the present disclosure, there is provided a sensor for determining a distance between objects, said sensor comprising a circuit according to any example of the first aspect.

There may be provided a computer program, which when run on a computer, causes the computer to configure any apparatus, including a circuit, controller, sensor, filter, or device disclosed herein or perform any method disclosed herein. The computer program may be a software implementation, and the computer may be considered as any appropriate hardware, including a digital signal processor, a microcontroller, and an implementation in read only memory (ROM), erasable programmable read only memory (EPROM) or electronically erasable programmable read only memory (EEPROM), flash memory, or a chip as non-limiting examples. The software implementation may be an assembly program.

The computer program may be provided on a computer readable medium, which may be a physical computer readable medium, such as a disc or a memory device, or may be embodied as a transient signal. Such a transient signal may be a network download, including an internet download.

DETAILED DESCRIPTION OF EMBODIMENTS

An example of a frequency synthesiser circuit, known as a Phase Locked Loop (PLL) is shown inFIG. 1A. The phase locked loop110comprises a Phase Detector122that receives an incident reference frequency signal120and divider signal164. Charge Pumps124(CPs), biased by a drive voltage126, are provided to translate the phase difference of the reference signal120and the divider signal164into a voltage130that is filtered by a low pass filter arrangement132. A tuning voltage140is then supplied to a voltage controlled oscillator150(VCO) and a voltage controlled oscillator frequency signal160generated. As noted above, the divider signal164is generated by a divider162, which is used to control a frequency sweep or chirp of the voltage controlled oscillator frequency signal160. The divider162is often implemented with a sigma-delta to obtain a fractional-N PLL.

The gain of the phase lock loop110is a design parameter that is used to optimize the bandwidth, locking time and noise performance of the PLL. For example, both the charge pump gain, KD(PFD/CP gain) and the oscillator gain, Kvco (VCO gain) are parameters that are ideally linear.FIG. 1Bshows168a typical response172of the gain KD170as a function of the tuning voltage140. The response172is broadly flat except at low and high tuning voltages.

The response178,182of the gain180of the voltage controlled oscillator150as a function of the tuning voltage140is shown inFIG. 1C. This response, is typically defined by the varactor transfer function, which in embodiments is modelled by a Hyperbolic Tangent function. Hence it is dependent upon the voltage used to tune the PLL, the Vtunevoltage resulting in a peaked derivative response as shown in178. As shown, the gain of the voltage controlled oscillator, KVCO, typically has a sharply peaked variation as the tuning voltage is swept from 0 to a maximum drive voltage VDD. In most applications this variation is acceptable, since calibration of the varactor is used to operate the PLL around a mid Vtunevoltage (VDD/2), which is broadly level for KDand KVCO. The PLL subsequently locks onto this mid tuning voltage which is related to the phase and frequency of the driving signal, as well as the gain from the oscillator. If the PLL is operated outside of this sweet spot frequency errors occurs as the degraded phase noise.

However, not all applications allow a steady input frequency or voltage. In some applications, such as car radar systems the frequency is swept and a chirp generated (by changing the division ratio) from a starting frequency by an amount dependent upon the bandwidth. Such a sweep is shown inFIG. 2A210as a function of the tuning voltage and inFIG. 2B220as a function of the frequency. InFIG. 2A, the tuning voltage140or varactor is swept over almost its full range of voltages (220—dashed line inFIG. 2A) over a period of time212, minus a small chargepump/VCO headroom240above zero voltage and below the drive voltage126. However, crossing these headroom boundaries240results in a large open loop gain variation, large variation in PLL bandwidth, high settling times and also to poor phase noise performance in the system. If the voltage is low, sources are lost and the charge pump gain drops. Accordingly, the systems are overdesigned, resulting in a higher Kvco gain and a reduced Vtune range as the tuning voltage range is swept (idealized overdesigned gain230—solid line inFIG. 2A).

FIG. 2Bshows the variation250of the frequency252over the period of time212by varying the voltage as shown inFIG. 2Afor the idealized overdesigned gain230, which provides frequency response260.

As noted above, the variation of the response of a phase locked loop is at least partially determined by the electrical configuration of components known as varactors. In the present disclosure a number of varactors are employed within a phase locked loop system.FIG. 3ashows310how the frequency response330of a number of varactors340,350,360varies as the tuning voltage320varies or is swept in a PLL system. As shown, a drive voltage322is typically moderated down to a maximum tuning voltage324. A headroom326due mainly to the chargepump is also present. The upper headroom328is generally between the ideal maximum tuning voltage324and the drive voltage322.

It can be seen that the frequency response of the varactors at subset ranges of tuning voltages Vb1, Vb2, Vb3can be chosen to provide the frequency response desired. For example, the first varactor340is configured to generate a varying capacitance and therefore a varying frequency response over a first subset range of tuning voltages Vb1ranging from a negative voltage to a positive voltage broadly centred around zero volts. The second varactor350is configured to generate a varying capacitance and therefore a varying frequency response over a second subset range of tuning voltages Vb2between zero volts and the tuning or drive voltage322. Similarly the third varactor360is configured to generate a varying capacitance and therefore a varying frequency response over a third subset range of tuning voltages Vb3broadly centred around the tuning voltage324.

A derivative representation370of the frequency response372of the varactors plotted inFIG. 3aas the voltage320varies is shown inFIG. 3b. The first varactor, having a tuning range of Vb1, has a derivative frequency response342broadly centred around Vtune=0. The third varactor, having a tuning range of Vb3, has a derivative frequency response362centred broadly around the maximum tuning voltage Vtune324, with the second varactor, having tuning range Vb2, sitting between. The overall derivative frequency response of all three varactors is curve378.

Applying the use of several varactors to a phase lock loop circuit such as shown inFIG. 1Aallows the gain of the voltage controlled oscillator150to be altered to reduce the large variation at high and low tuning voltages as shown inFIG. 1B.FIG. 3Cshows380how the gain382of the phase detector KDvaries as the tuning voltage320is altered. The response384is broadly flat except at high and low tuning voltages. This is similar to the gain characteristics of the phase detector of known phase locked loops as shown inFIG. 1B.

However, for the gain of the voltage controlled oscillator, the use of several varactors provides a greatly altered response as shown390inFIG. 3D, in comparison toFIG. 1C. The response394of the gain392of the voltage controlled oscillator150as the tuning voltage320is swept from 0 to a drive voltage is broadly similar to the derivative frequency response shown inFIG. 3b. Instead of the single peak at around half the drive voltage as shown inFIG. 1C, the response390has a number of peaks at voltages equal to the maximum differential response of each varactor. In the example shown, three varactors are employed, the first varactor340has a maximum derivative frequency response at the drive voltage, the second varactor350has a maximum response at half the drive voltage and the third varactor has a maximum response at 0 V. The combined response provides a gain response of the open loop gain of the frequency synthesiser circuit in which the varactors are used with peaks at the same respective voltages as the varactors used, however the overall response is broadly more even with less variation than the single varactor response shown inFIG. 1C.

FIG. 4shows an exemplary system400of varactor units used with a voltage controlled oscillator of a PLL according to the present disclosure. In the present example, the voltage controlled oscillator has a first varactor unit comprising a first and second varactor410,410′ biased by a drive or bias voltage412. A second varactor unit is provided, which comprises a first and second varactor420,420′ biased by a second bias voltage422. Additionally a third pair of varactors430,430′ are also provided to form a third varactor unit, biased by a third bias voltage432.

A tuning voltage440is supplied to the voltage controlled oscillator, driven by the charge pump124, which produces a frequency response of the voltage controlled oscillator dependent on the bias of the voltage controlled oscillator and the value of the tuning voltage (as shown inFIG. 2A).

The gain of the voltage controlled oscillator is determined by the varactor units and the inherent gain of the voltage controlled oscillator. Accordingly, by altering the characteristics and/or number of varactor units and/or the bias voltages supplied to the varactor units, the gain of the voltage controlled oscillator can be controlled.

Consequently, the varactor units within the voltage controlled oscillator act to alter the gain of the voltage controlled oscillator, which in turn alters the frequency response of the voltage controlled oscillator with respect to the range of tuning voltages supplied to the voltage controlled oscillator as shown inFIG. 2A. It is therefore possible to smooth out variations in the overall open-loop gain of the PLL and therefore in the frequency response of the voltage controlled oscillator at different applied tuning voltages.

In particular, the varactor units are scaled or sized to alter the voltage controlled oscillator gain that is higher at low and high tuning voltages to compensate for drop-off in the gain of the charge pump. This allows the overall open loop gain of the phase locked loop to remain substantially constant. In other words, by providing a non-linear bias of the voltage controlled oscillator by choosing the number and/or characteristics of the varactors within the voltage controlled oscillator, a linear open loop gain of the phase locked loop can be achieved.

It can be appreciated that more of less varactor units may be employed within the voltage controlled oscillator depending upon the required application. Additionally, although shown as pairs of varactors, each varactor unit may be a single varactor biased by a single bias voltage, a triplet of varactors each biased by a single bias voltage, or 4 or more varactors each biased by a single bias voltage.

Each varactor410,420,430(and corresponding pair) in the example shown comprises a capacitor. However diodes or other electrical components that have a gain response that varies with frequency may be used as varactors.

The bias voltages are provided from a current source450in series with a resistor414: and in parallel with a capacitor416for the first bias voltage412; in series with a second resistor424and in parallel with a second capacitor426for the second bias voltage422; and in series with the second424and a third resistor434for the third bias voltage432.

The total capacitance of each varactor shown inFIG. 4is given by:

where Cvaris the total capacitance of the varactor; Cvar,minis the natural capacitance of the varactor electrical components; Cais the portion of the varactor capacitance dependent upon voltage, which is dependent on the tan h function; Vgis the current gain voltage supplied to the varactor by current that flows into a resistor, which is normally constant; Vs/dis the tuning voltage applied to the PLL; and Vnomis the nominal voltage of the varactor, typically determined by the process or system use.

It can be appreciated that Vgand Vs/dcan be swapped, resulting in an inverse graph to that shown inFIG. 3b. Consequently, if Vgis used as a tuning voltage and Vs/dis constant, then the slope of the transfer function of the varactor is positive, whilst its frequency response and slope is negative (the frequency is roughly proportional to the inverse square root of the capacitance of the varactor

Tuning of the varactor units is possible by adding further varactors, altering the varactor components or by altering the bias voltage characteristics. Although shown as three pairs of varactors, any number such as 10 or more pairs may be used, however phase noise considerations provide a notable trade off as the total number of varactors increases.

The phase locked loop100comprising the varactors400described above may be used to generate a frequency chirp for applications such as sensors. One example may be a sensor for radar systems suitable for use within a car radar system. In such applications, as the tuning voltage is swept, the frequency output of the PLL varies due to the variance in the open loop gain (due to the variance in the voltage controlled oscillator gain caused by the varactors410,420,430).