Control facility with adaptive fault compensation

A control facility for controlling a controlled system experiencing a disturbance includes a front nodal point receiving a target value and an actual value outputted by the controlled system and supplying a difference value corresponding to a difference between the target value and the actual value to a compensation circuit. The compensation circuit supplies a frequency-filtered and time-delayed signal formed as the sum of the weighted difference value and a weighted feedback signal as an input to a controller for the controlled system. The sum of a filter delay time and of first and second propagation delays is an integer multiple of the cycle duration of the disturbance, and a sum of the filter delay time and the first propagation delay is an integer multiple of the cycle duration minus a propagation time, which elapses until a change in the target value causes a change in the actual value.

CROSS-REFERENCES TO RELATED APPLICATIONS

This application claims the priority of European Patent Application, Serial No. EP 14181404, filed Aug. 19, 2014, pursuant to 35 U.S.C. 119(a)-(d), the content of which is incorporated herein by reference in its entirety as if fully set forth herein.

BACKGROUND OF THE INVENTION

The present invention relates to a control facility for controlling a controlled system.

The present invention further relates to a software module comprising machine code, wherein the control facility is embodied as a software-programmable control facility.

Control facilities of this type and the associated software modules are generally known.

With some controlled technical parameters, in particular position values in the case of rotary axes, periodic disturbances often occur. Such disturbances can occur for instance on account of inertia or processing forces in machine tools or other production machines. A suppression of such disturbances significantly improves the quality of the closed loop control, sometimes by more than one order of magnitude.

In order to suppress such periodic disturbances, adaptive closed loop controls are known. The relevant technical term for such adaptive closed loop controls is Repetitive Control. The precise implementation of such adaptive closed loop controls is however generally not made public by manufacturers of such closed loop controls.

It would therefore be desirable and advantageous to obviate prior art shortcomings and to provide an improved a control facility which operates in a simple and reliable manner in a control facility of the type mentioned in the introduction, in which the acquired actual value is subjected to a disturbance comprising a cycle duration, by means of which control facility the periodic fault is compensated for highly accurately.

SUMMARY OF THE INVENTION

According to one aspect of the present invention, a control facility includesa front nodal point having a first input receiving a target value and a second input receiving an actual value outputted by the controlled system, said actual value comprising a disturbance having a cycle duration, the front nodal point further having an output supplying a difference value corresponding to a difference between the target value and the actual value,a compensation circuit receiving the difference value and supplying a compensation signal,a rear nodal point having a first input receiving the difference value and a second input receiving the compensation signal, and further having an output supplying a sum value corresponding to a sum of the difference value and the compensation signal, anda controller receiving the sum value and supplying a control signal to the controlled system,
wherein the compensation circuit comprisesa first multiplier circuit forming a first product by multiplying the difference value with a first weighting factor,a second multiplier circuit forming a second product by multiplying a feedback signal with a second weighting factor,
wherein the feedback signal is generated byfrequency filtering, with a frequency filter having a filter delay time, a sum signal outputted by an inner nodal point and representing a sum of the first product and the second product, and bytime-delaying the sum in a front buffer store having a first propagation delay and supplying the compensation signal,and thereafter time-delaying the compensation signal in a rear buffer store arranged downstream of the front buffer store and having a second propagation delay,
wherein the a sum of the filter delay time, the first propagation delay and the second propagation delay is an integer multiple of the cycle duration of the disturbance and a sum of the filter delay time and the first propagation delay is an integer multiple of the cycle duration of the disturbance minus a propagation time, which elapses until a change in the target value causes a change in the actual value.

The compensation circuit corresponds to a so-called inner model of the controlled system. Inner models are known in the field of control technology.

The frequency filter can be embodied as required. For instance the frequency filter can be embodied as a linear non-recursive digital filter (finite impulse response=FIR). Such filters have the same propagation time for all frequencies.

The frequency filter can be embodied in particular as a low pass filter. A filter order of the frequency filter can be permanently predetermined or adjustable.

Certain frequency ranges of the control deviation can be filtered by means of a non-recursive digital filter. In some instances, it is however only necessary to filter a single or a few precisely specified frequencies and to compensate for their disturbance. In such a case, the frequency filter can, alternatively to an embodiment as a non-recursive digital filter, comprise a number of orthogonal correlation filters, by means of which an individual frequency component is filtered out in each case. The number of orthogonal correlation filters amounts in such a case to a minimum of 1. It may however also be larger.

The first weighting factor determines how quickly the compensation circuit learns an occurring disturbance. The second weighting factor determines how well the compensation circuit notices a disturbance which has been learnt once. The weighting factors can be fixedly predetermined. They can however preferably be adjusted.

The output of the frequency filter can preferably be separated from the inner tapping point. With the output of the frequency filter which is separated from the inner tapping point, it is in particular easily possible to check the stability of the compensation circuit and also the control structure as a whole and if necessary parameters of the compensation circuit, in particular to adjust the filter order of the non-recursive digital filter and/or the weighting factors, such that the compensation circuit and with it the entire closed loop control also then remains stable if the compensation circuit is closed, the output of the frequency filter is therefore connected to the inner tapping point.

In particular, the first weighting factor, the second weighting factor and the frequency filter are preferably adjusted such that with an output of the frequency filter which is separated from the inner tapping point, an amplification from the inner tapping point to the output of the frequency filter irrespective of a frequency of a signal present at the inner tapping point is less than or at most equal to 1. This setting ensures, provided the actual control loop is stable as such, the stability of the control structure as a whole.

The amplification can preferably be output by way of an output facility to a user of the control facility as a function of the frequency. As a result the user obtains feedback detailing whether or not adjustments performed by him to the compensation circuit endanger the stability of the control structure as a whole.

It is possible for at least one further controller to be subordinate to the controller. In this case a pre-control signal derived from the signals stored in the front buffer store is preferably supplied to the subordinate controller. As a result the quality of the closed loop control can be still further increased.

The cycle duration of the disturbance can vary over the course of time in some instances. The cycle duration of the disturbance is often indirectly proportional to a rotational speed of the rotary axis particularly in the case of a rotary axis. In such a case, at least the delay time of the front buffer store is preferably dynamically traced according to the cycle duration.

As already mentioned, the controlled system can be embodied as a rotary axis. If in such a case the controller is embodied as a position controller, an associated position value is preferably assigned to the signals stored in the front and rear buffer store in each case. It is therewith possible when varying the cycle duration of the compensation circuit to determine the compensation signal by taking the position values assigned to the signals stored in the front and in the rear buffer store into account.

According to an advantageous feature of the present invention, the control facility may be embodied as a software-programmable control facility and may be programmed with a software module.

According to another aspect of the invention, the processing of the machine code of the software modules by a software-programmable control facility means that the control facility is embodied in accordance with the invention. The software module can be stored in machine-readable form in particular on a non-transitory data carrier.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

Turning now to the drawing, and in particular toFIG. 1, there is shown a control facility for controlling a controlled system1comprises a front nodal point2, a rear nodal point3, a controller4and a compensation circuit5. An actual value x and a corresponding target value x* are supplied to the front nodal point2. The actual value x is acquired using measuring technology on the output side of the controlled system1by means of a measuring facility6. The front nodal point2determines a control deviation δx by forming the difference between target value x* and actual value x. The control deviation6xand a compensation signal K are supplied to the rear nodal point3. The rear nodal point3adds the control deviation δx and the compensation signal K and as a result forms a sum signal, subsequently also referred to as external sum signal. The rear nodal point3supplies the external sum signal to the controller4. The controller4determines a control signal S for the controlled system1with the aid of the external sum signal supplied thereto. The controller4outputs the control signal S to the controlled system1.

The acquired actual value x is subject to a disturbance z. The disturbance z is a periodic function of time t in accordance with the diagram inFIG. 2. It therefore has a cycle duration T. The compensation circuit5and the compensation signal K determined by the compensation circuit5are used to compensate for the disturbance z.

In order to be able to determine the compensation signal K, an external tapping point7is arranged between the front and the rear nodal point2,3. The control deviation δx is tapped at the external tapping point7and supplied to the compensation circuit5. The compensation circuit5determines the compensation signal K and supplies it to the rear nodal point3.

The compensation circuit5comprises an inner nodal point8, a frequency filter9, a front buffer store10and a rear buffer store11. Two multipliers12,13are superordinate to the inner nodal point8. The control deviation δx is supplied to the multiplier12, a feedback signal R is supplied to the multiplier13. The multipliers12,13multiply the signals δx, R supplied thereto by a respective weighting factor γ, β and supply the products to the inner nodal point8. The inner nodal point8adds the control deviation δx weighted with the weighting factor γ and the feedback signal R weighted with the weighting factor β and thus forms a further sum signal, subsequently referred to as inner sum signal. The inner sum signal supplies the inner nodal point8to the frequency filter9.

The frequency filter9implements a frequency filtering. The frequency filter9can for this purpose be embodied in accordance with the diagram inFIG. 1as a non-recursive digital filter for instance, in particular as a low pass filter. A filter order of the frequency filter9can be adjusted by adjusting corresponding parameters P. The frequency filter9supplies the correspondingly filtered signal to the front buffer store10.

The front buffer store10implements a first propagation delay T1of the signal supplied thereto. The front buffer store10supplies the accordingly delayed signal to the rear buffer store11. Similarly the rear buffer store11implements a second propagation delay T2. The rear buffer store11outputs the correspondingly delayed signal as a feedback signal R.

An inner tapping point14is arranged between the front buffer store10and the rear buffer store11. The compensation signal K is tapped at the inner tapping point14and supplied to the rear nodal point3.

The frequency filter9comprises, as already mentioned, a filter order. The filter order corresponds to a delay time TF. According to the invention the frequency filter9and the two buffer stores10,11are configured such that the relation
TF+T1+T2=n·T(1)
applies. n is a whole number. The number n is generally as small as possible. The number n often comprises the value 1 or the value 2.

The controlled system1, in conjunction with the normal closed loop control (i.e. without compensation circuit5) comprises a propagation time TL. The propagation time TL is the time taken until a signal supplied to the front nodal point2effects a change in the actual value x. The rear buffer store11is configured in accordance with the invention such that the relation
T2−TL=m·T(2)
applies. m is a whole number. The number m is generally as small as possible. The number m often comprises the value 0. In individual cases, the number m can comprise the value 1. Larger values should preferably not comprise the number m. The sum of the delay times TF, T1of the frequency filter9and the front buffer store10is thus an integer multiple of the cycle duration T of the disturbance z minus the propagation time TL.

The first weighting factor y and the second weighting factor β can preferably be adjusted in accordance withFIG. 1by a user15of the control facility. The same preferably also applies to the parameters P of the frequency filter9. As a result the compensation circuit5can be adjusted by the user15such that a stable closed loop control of the controlled system1is guaranteed. The weighting factors γ, β are preferably frequency-independent.

In order to adjust the compensation circuit5, the control facility, like also in the prior art, is firstly parameterized as such, i.e. without the compensation circuit5and its parameterizable components9,10and11, so that the control facility controls the controlled system1as such in a stable manner. This procedure is known and trusted by persons skilled in the art and therefore does not need to be explained in more detail. The compensation circuit5is then activated, in other words a control-specific connection of the inner tapping point14is established with the rear nodal point3.

In order to determine suitable adjustments of the weighting factors γ, β and the parameters P of the frequency filter9, an output16of the frequency filter9is further firstly separated from the inner tapping point14in accordance withFIG. 3. This state of the compensation circuit5is then referred to as an open compensation circuit5. In this state (in other words with an open compensation circuit5), a signal u is then applied to the inner tapping point14and the amplification is determined, which is produced at the output16of the frequency filter9.

FIG. 4shows by way of example the amplification as a function of the frequency. The frequency is plotted to the right inFIG. 4in a logarithmic scale, the amplification is shown in decibels to the top. As apparent fromFIG. 4, the amplification depends on the frequency of the signal u and on the adjustments of the weighting factors γ, β and the parameters P of the frequency filter9. If the weighting factors γ and β both have the value 1, and the frequency filter9is parameterized such that it does not implement a filtering but instead acts as a pure buffer store, the amplification—see the curve designated with I inFIG. 4—is in many frequencies greater than 1. If by contrast the weighting factors γ and/or β assume smaller values, for instance lie between 0.6 and 0.8, and/or the frequency filter9is parameterized as a low pass filter, it is possible to ensure—see curve designated with II inFIG. 4—that the amplification is always less than or at most equal to 1 irrespective of the frequency of the signal u. The control facility also then remains stable with such a parameterization if the signal present at the output16of the frequency filter9is supplied to the inner tapping point14via the front buffer store10(and from there to the rear buffer store11).

The amplification as a function of the frequency of the signal u is also often referred to as transmission function. According toFIG. 3the transmission function can preferably be output to the user15of the control facility via a display facility17. The user15can therefore adjust the weighting factors γ, β and the parameters P of the frequency filter9when the compensation circuit5is open, the latter reading the resulting transmission function and then varying the weighting factors γ, β and the parameters P of the frequency filter9if necessary until the amplification is always less than or at most equal to 1 irrespective of the frequency of the signal u.

In individual cases, it is possible for the transmission function to be less than 1 for all frequencies, although the frequency filter9is parameterized such that it does not perform a filtering, but instead only acts as a (further) buffer store. The frequency filter9is in this case degraded. A (real) filtering is however generally necessary. In particular the frequency filter9can be parameterized such that it dampens the amplification precisely in frequency ranges in which the transmission function would on the other hand be greater than 1.

The parameterization of the frequency filter9preferably takes place such that the filter order is as low as possible. The behavior of the compensation circuit5then improves with higher frequencies of the disturbance z. Moreover, attempts are generally made to adjust the so-called breaking frequency of the frequency filter9as high as possible.

In many instances the control facility is embodied as a cascaded control facility. In the case of an embodiment of the controller4as a speed or rotational speed controller, an acceleration, moment or current controller can underlie the controller4. Similarly in the case of an embodiment of the controller4as a position controller, a speed or rotational speed or acceleration, moment or current controller can be subordinate to the controller4.FIG. 5shows an embodiment in which the controller4is embodied as a position controller which is subordinate to a speed or rotational speed controller18. An acceleration, moment or current controller19is subordinate to the speed or rotational speed controller18for its part.

In the presence of subordinate controllers18,19, a respective nodal point20,21is superordinate to the respective subordinate controller18,19. The output signal of the respective superordinate controller4,18and the associated actual value are supplied on the one hand to the respective nodal point20,21as a target value. For instance, the actual value for the speed or rotational speed controller18can be derived from the actual position value x by means of a differentiator22. An actual value for the current controller19can be acquired for instance by means of a corresponding measuring facility23.

In the case of the embodiment of the control facility as a cascaded control facility, a compensation can take place by means of the compensation signal K in accordance with the diagram inFIG. 5similarly toFIG. 1. It is also possible however to supply a pre-control signal V1to the subordinate controller18, to supply a pre-control signal V2to the subordinate controller19or to supply a respective pre-control signal V1, V2to both subordinate controllers18,19. The pre-control signals V1, V2for the subordinate controllers18,19are derived from the signals in accordance withFIG. 5, said signals being stored in the front buffer store10.

In particular, in accordance with the diagram inFIG. 5, the buffer stores9,10are modified marginally compared with the diagram inFIG. 1. Moreover, the compensation circuit5comprises additional buffer stores24,25. Finally, the compensation circuit5comprises determination elements26,27.

The modification of the buffer store9,10consists in the front buffer store9being marginally shortened, generally by one storage cell. Because the overall control facility is generally operated in switch-mode, this shortening corresponds to a shortening by a clock cycle. The rear buffer store10is lengthened by the same amount. The sum of the propagation time delays T1, T2of the front and rear buffer store9,10is therefore unchanged.

The additional buffer store24has exactly the length by which the front buffer store9is shortened. In the embodiment according toFIG. 5, the compensation signal K is thus switched on at precisely the same point in time as in the embodiment according toFIG. 1.

The determination element26performs the same determinations, which are required to determine the pre-control signal V1. A determination time is generally required herefor. The additional buffer store25is dimensioned such that it effects a delay, which, in conjunction with the delay effected by the determination element26, corresponds to the length of the additional buffer store24.

The determination element27performs the same determinations, which are required to determine the pre-control signal V2. A determination time is generally required herefor. This determination time is generally greater than the determination time of the determination element26.

No buffer store is subordinate or superordinate to the determination element27. This is possible in that the additional buffer store24is dimensioned such that its delay corresponds to the determination time of the determination element27.

The determination times of the determination elements26,27can correspond individually to integer multiples of the clock cycle. The determination times nevertheless often only correspond to integer multiples of half of the clock cycle. It is in particular possible for the determination time of the determination element26to correspond to a half clock cycle and for the determination time of the determination element27to correspond to a full clock cycle. In such a case the additional buffer store25must realize a delay by a half clock cycle. In order to be able to realize a delay of this type (or also a different delay which differs from a full clock cycle), the additional buffer store25is embodied such as is explained in more detail below in conjunction withFIG. 6. In conjunction withFIG. 6, how the buffer store25has to be embodied is explained here in order to be able to realize as a result a delay between0and a full clock cycle. This is sufficient because a realization of full clock cycles can be realized completely by a corresponding number of storage cells of the buffer store25. Moreover, buffer stores other than buffer store25can naturally also realize a delay between0and a full clock cycle on account of an embodiment similar toFIG. 6.

According toFIG. 6, the buffer store25comprises a nodal point28, an individual storage cell29, two multipliers30,31and a nodal point32. The signal supplied to the buffer store25is supplied to the two branches at nodal point28, of which one contains the storage cell29and the multiplier30and the other contains the multiplier31. The storage cell29effects a delay by a full clock cycle. Weighting factors a and1-a are supplied to the multipliers30,31. A summation of the two weighted signals takes place at the nodal point32. As a result, the structure according toFIG. 6affects a delay by a fractions of a clock cycle.

In some cases the cycle duration T is constant. In other cases the cycle duration T varies over the course of time t. If the cycle duration T varies over the course of time t, the control facility inFIG. 1is preferably modified in accordance with the embodiment according toFIG. 7. A similar modification would also be possible with respect to the control facility inFIG. 5.

According toFIG. 7, a variable G is acquired by means of a measuring facility33, which is characteristic of the cycle duration T. The variable G is supplied to a determination facility34, which determines the first delay time T1of the front buffer store10therefrom and accordingly configures the front buffer store10dynamically. The first delay time T1is thus traced dynamically. The variable G as such can be determined if required. If the controlled system1is embodied for instance as a drive, in some cases the frequency of the disturbance z can be proportional to a rotational speed of the drive. The cycle duration T is in this case reciprocal to the rotational speed. If the rotational speed is determined in such a case by means of the measuring facility33, the cycle duration T can be concluded as a result.

In many instances the controlled system1is embodied as a rotary axis, in other words as an axis which rotates and whose physical state thus repeats with each full revolution. Moreover, in such cases the controller4is often embodied as a position controller. If in such instances the rotational speed of the rotary axis and thus the cycle duration T can vary, the control facility inFIG. 1is preferably modified, as is explained in more detail below in conjunction withFIG. 8. Similar modifications would also be possible with respect to the control facilities inFIG. 5andFIG. 7.

According toFIG. 8, an associated position value p is also supplied in each case to the compensation circuit5in addition to the control deviation δx. The position value p can correspond to the target value x*, the actual value x or a combination of the two values x*, x. The compensation circuit5also comprises a shift register35, into which the position values p are inscribed. The inscription of the position values p takes place in synchrony with the takeover of the control deviation δx in the frequency filter9. An associated position value p is thus assigned in particular to the signals (in precise terms also the signals processed within the frequency filter9) stored in the front and in the rear buffer stores10,11.

In the case of the embodiment according toFIG. 8, a control facility36of the compensation circuit5checks in accordance withFIG. 9in a step S1whether the cycle duration T of the disturbance z has changed. If this is not the case, the control facility36moves to a step S2. Step S2proceeds as was explained above in conjunction withFIG. 1. If conversely the cycle duration T of the disturbance z has changed, in other words the cycle duration T has varied, the control facility36moves to a step S3. In step S3the control facility36determines, by taking the position values p stored in the shift register35into account, the positions of the signal stored in the front or in the rear buffer store10,11that are to be supplied to the rear nodal point3as a compensation signal K. The corresponding signal is supplied to the rear nodal point3in a step S4.

The procedure inFIG. 9generally also then produces good results, if the cycle duration T changes relatively quickly. This applies in particular if the correct point in the front and rear buffer store10,11is determined within the scope of a few iterations (for instance 3 to 5 iterations).

The present invention was explained above in conjunction with a frequency filter9, which is embodied as a non-recursive digital filter. The frequency filter9can however alternatively comprise a number of orthogonal correlation filters37according to the diagram inFIG. 10, by means of which an individual frequency component is filtered out respectively. Orthogonal correlation filters37calculate the coefficients of Fourier rows by orthogonal correlation and then generate the monofrequent and phase-correct signal. The design and mode of operation of orthogonal correlation filters37are generally known to persons skilled in the art and do not therefore need to be explained in greater detail.

The number of orthogonal correlation filters37can be determined if necessary. A single orthogonal correlation filter37is if necessary available as a minimum. If a number of orthogonal correlation filters37are available, these are switched in parallel in accordance with the diagram inFIG. 10.

The control facility is preferably embodied as a software programmable control facility according to the diagram inFIG. 11. It therefore includes a microprocessor38. The control facility is in this case programmed with a software module39. On account of the programming with the software module39, the control facility is embodied in accordance with the invention. The software module39includes machine codes40. The processing of the machine code40by the control facility thus means that the control facility is embodied in accordance with the invention.

The software module39can be supplied to the control facility in broadly speaking any manner. In particular, the software module39can be stored on the data carrier41in machine-readable form. The diagram inFIG. 11, in which the data carrier41is shown as a USB memory stick, is nevertheless understood to be purely exemplary and non-restrictive.

In summary, the present invention thus relates to the following situation:

A control facility for controlling a controlled system1comprises a front nodal point2, a rear nodal point3, a controller4and a compensation circuit5. An actual value x and a corresponding target value x* acquired on the output side of the controlled system1are supplied to the front nodal point2. It determines a control deviation δx. The acquired actual value x is subject to a disturbance z. The control deviation δx and a compensation signal K are supplied to the rear nodal point3. It supplies an external sum signal formed from the control deviation δx and the compensation signal K to the controller4. The controller4determines a control signal S for the controlled system1and outputs the same to the controlled system1. An external tapping point7is arranged between the front and the rear nodal point2,3, at which the control deviation δx is tapped and supplied to the compensation circuit5. The compensation circuit5determines the compensation signal K and supplies it to the rear nodal point3. The compensation circuit5comprises an inner nodal point8, a frequency filter9, a front buffer store10and a rear buffer store11, The control deviation δx and a feedback signal R are supplied to the inner nodal point8weighted with weighting factors γ, β. The inner nodal point8supplies an inner sum signal formed therefrom to the frequency filter9. The frequency filter9implements a frequency filtering and supplies the filtered signal to the front buffer store10. The buffer stores10,11implement a respective propagation delay T1, T2and supply the correspondingly delayed signal to the rear buffer store11or output it as a feedback signal R. An inner tapping point14is arranged between the buffer stores10,11, at which the compensation signal K is tapped. The sum of the delay times TF, T1, T2of the frequency filter9and both buffer stores10,11is an integer multiple of the cycle duration T of the disturbance z. The sum of the delay times TF, T1of the frequency filter9and the front buffer store10is an integer multiple of the cycle duration T of the disturbance z minus the propagation time TL, which elapses until a signal supplied to the front nodal point2effects a change in the actual value x.

The present invention has many advantages. Periodic disturbances can be adjusted almost completely. The known conventional window functions can be used for the design of the frequency filter9, as are known from the digital signal processing. By checking the transmission function with an open compensation circuit, the stability of the closed loop control can be monitored in advance.