Method for manufacturing thin film transistor array panel

The present invention relates to a method of manufacturing a thin film transistor array panel and apparatus and more particularly to an apparatus containing an in-situ fluorine generation chamber.

This application claims the benefit of Korean Patent Application No. 2003-0038713, filed on Jun. 16, 2003, which is hereby incorporated by reference for all purposes as if fully set forth herein.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a method for manufacturing a thin film transistor array panel and apparatus and more particularly to an apparatus containing an in-situ fluorine generation chamber.

2. Description of Related Art

A thin film transistor (“TFT”) array panel may be used for individually driving each pixel of a display. The display may be a liquid crystal display (“LCD”), organic electro luminescence (“EL”) display, and the like. The TFT array panel includes scanning signal lines or gate lines for transmitting scanning signals. Also, the TFT array panel includes image signal lines or data lines formed on the TFT array for transmitting image signals. Further, the TFT array panel includes TFTs connected to gate lines, data lines and pixel electrodes.

A gate insulating layer is formed in order to insulate the gate lines. A passivation layer is formed to insulate the TFTs and the data lines. The gate insulating layer, semiconductor layer, ohmic contact layer, and passivation layer are formed using a chemical vapor deposition (“CVD”) process that may be well known in the art.

In the related art, films or layers are formed with chemical reactions using a CVD process. That is, by providing one or more gases (e.g., simple or compound substance(s) including element(s)) films and/or layers may be formed on a substrate. During the CVD deposition processes on the insulating substrate extraneous films and/or layers are formed on the CVD. The present invention also discloses a more environmentally friendly process chamber and/or on the surface of a diffuser. These extraneous films and/or layers create differences in thermal expansion coefficients between the diffuser and the films deposited thereon. These differences create thermal stresses in the deposited films. As a result, the deposited film deteriorates and may peel off, generating undesired minute particles. Accordingly, a cleaning process is used to remove the extraneous film deposits on inner walls of the chamber and/or on the surface of the diffuser. For example, a nitrogen trifluoride (NF3) plasma etching process may be performed as a way to clean the CVD chamber.

A remote plasma source (“RPS”) box may be used for forming nitrogen trifluoride (NF3) plasma. The RPS box may be placed in gas piping. The RPS box generates nitrogen trifluoride (NF3) and argon (Ar) plasmas and transmits these plasmas into the CVD chamber. These plasmas remove the accumulated films formed inside the chamber during deposition and restore the chamber to its initial state.

The related art processes required a stable supply of nitrogen trifluoride (NF3). Nitrogen trifluoride (NF3) is typically purchased in a cylinders that need to be replaced regularly. However, a stable supply of nitrogen trifluoride (NF3) may not be possible as it is dependent on its availability from the supplier. Additionally, nitrogen trifluoride (NF3) systems are very expensive as there is a very high initial investment cost. Moreover, nitrogen trifluoride (NF3) is an environmentally unfriendly gas as it is categorized as a PFC restriction gas.

SUMMARY OF THE INVENTION

Accordingly, the present invention is directed a method for manufacturing a TFT array panel that substantially obviates one or more of the problems mentioned above.

The present invention discloses a stable supply of fluorine gas for fluorine plasma formation, achieving cost reduction in manufacturing an TFT apparatus. The present invention also discloses an environmentally friendly process and provides a cleaning method for a CVD apparatus in order to produce improved TFT arrays.

To achieve these and other advantages and in accordance with the purpose of the present invention, as embodied and broadly described, A method of forming a thin film transistor (TFT) array panel, comprising providing a substrate. Forming a plurality of gate lines on the insulating substrate. Successively forming a gate insulating layer on the plurality of gate lines, a semiconductor layer on the gate insulating layer, and an ohmic contact layer on the semiconductor layer in a first chemical vapor deposition (CVD) apparatus. Cleaning the first CVD apparatus with a fluorine plasma after a predetermined number of the successively forming steps has been preformed on different substrates.

In another aspect of the present invention, a method of forming thin film transistor (TFT) array panel, comprising providing an insulating substrate into a first CVD apparatus. Forming a plurality of gate lines on the insulating substrate. Successively forming a gate insulating layer on the plurality of gate lines, a semiconductor layer on the gate insulating layer, and an ohmic contact layer on the semiconductor layer in a first chemical vapor deposition (CVD) apparatus, wherein the first CVD apparatus is cleaned prior to successively forming with a first fluorine plasma generated in a RPS box. Forming a plurality of data lines. Forming a passivation layer over the plurality of data lines and forming contact holes into the passivation layer in a second CVD apparatus, wherein the second CVD apparatus is cleaned with a second fluorine plasma prior forming the passivation layer. Forming pixel electrodes on the passivation layer and electrically connected to the second conductive layer.

In another aspect of the present invention, a thin film transistor (TFT) array panel, comprising an insulating substrate, a first adhesion material formed on the insulating substrate. A first conductive material formed on the first adhesion material, wherein the first adhesion material and the first conductive material form gate lines and a gate insulating layer formed on the first conductive material. A source and drain region formed from a second adhesion material, a second conductive material, and an ohmic contact. A passivation layer formed over the second conductive material and a pixel electrode connected to a drain region.

In another aspect of the present invention, a chemical vapor deposition (CVD) apparatus, comprising a deposition chamber. A gas pipe having a first end connected to the deposition chamber and a second end opposite the first end and a fluorine supplier connected to the second end to generate fluorine gas. A RPS box arranged in the CVD apparatus to form plasma from fluorine gas received from the gas pipe and a backing plate to support a diffuser arranged in the deposition chamber. A diffusion plate to diffuse reaction gas into injection holes arranged in the diffuser. A susceptor that receives a substrate and a susceptor carrier that adjusts the position of the susceptor.

DETAILED DESCRIPTION OF THE ILLUSTRATED EMBODIMENTS

FIG. 1Aillustrates a layout view showing a TFT array panel manufactured by a method according to an embodiment of the present invention.FIG. 1Billustrates a sectional view of the TFT array panel ofFIG. 1Ataken along the line IB-IB′. Referring toFIGS. 1A and 1B, a plurality of gate lines121,124, and129are formed on a transparent insulating substrate110. Each gate line has a double-layered structure including a first adhesive metal pattern211,241, and291and a first wire metal pattern212,242, and292. The first adhesive metal pattern211,241and291provides for better adhesion between the first wire metal pattern212,242, and292and the insulating substrate110.

The gate line121extends in a substantially transverse direction and a portion of each gate line121serves as gate electrode124. A portion129near one end of each gate line121is a gate pad. It may be wider than the other portions of the gate line .121and used for connection to an external circuit. A gate insulating layer140may cover the entire substrate including the gate lines121,124, and129.

A plurality of semiconductor patterns151,154, and159made of a semiconductor material are formed. For example, an amorphous silicon layer may be formed on the gate insulating layer140opposite the gate electrodes124. A plurality of ohmic contact patterns161,163, and165made of a semiconductor material are formed. For example, amorphous silicon which may be heavily doped with an n-type impurity may be formed on semiconductor patterns151,154, and159. Additionally, a plurality of data lines171,173,175,177, and179may be formed on the ohmic contact patterns161,163, and165and the gate insulating layer140.

Data lines171intersect the gate lines121and are formed to be substantially perpendicular to each other. The area between the intersection of these lines define pixel areas. A portion of each data line171may serve as a source electrode173and may be connected to the ohmic contact pattern163. The drain electrodes175are separated from the source electrodes173and are located opposite the source electrodes173. That is, the drain electrode is located on portion165of the respective pairs of the ohmic contact patterns163and165with respect to the corresponding gate electrodes124. A portion179near one end of each data line171is a data pad. It may be wider than the other portions of the data line and is used for connection to an external circuit. A plurality of storage electrodes177may be overlapped with the gate lines121and may be formed to increase storage capacitance.

Each of the data lines171,173,175, and179and the storage electrodes177may be formed in multiple-layered structure. For example, these multiple-layered structures may include a second adhesive metal pattern711,731,751, and791and a second wire metal pattern712,732,752, and792. The second adhesive metal patterns711,731,751, and791provide for better adhesion between the second wire metal pattern712,732,752, and792and the ohmic contact patterns161,163, and162.

A passivation layer180may be formed on the substrate. The passivation layer180may include a plurality of first contact holes181exposing the drain electrodes175, a plurality of second contact holes182exposing the end portions129of the gate lines, a plurality of third contact holes183exposing the end portions179of the data lines, and a plurality of fourth contact holes exposing the storage electrodes177.

A plurality of pixel electrodes190may be connected to the drain electrodes175and the storage electrodes177via the first contact hole181and the fourth contact hole184, respectively. A plurality of gate contacts95may be connected to the end portions129of the gate lines via the second contact holes182. A plurality of data contacts97may be connected to the end portions179of the data lines via the third contact holes183. The pixel electrodes190may be formed to overlap the gate lines121and the data lines171, thereby partly increasing an aspect ratio. Alternatively, they may be formed not to overlap the gate line and the data line. Signal interference between the pixel electrode190and the data line171can be decreased by using a passivation layer180having a low dielectric constant. Accordingly, the pixel electrodes190may be formed to overlap with the data line171.

Now a method of manufacturing a TFT array panel according to an embodiment of the present invention will be described in detail with reference to the drawings.

Referring toFIGS. 2A and 2B, a first adhesive layer and a first wire layer are sequentially deposited on a transparent insulating substrate110. The deposited layers are patterned using photolithography to form a plurality of gate lines121,124, and129including first adhesive metal patterns211,241, and291and first wire metal patterns212,242, and292. The two layers may be simultaneously wet etched during the photolithography step using an acid mixture containing, for example, acetic acid, phosphoric acid, and/or nitric acid mixed at predetermined ratios.

The first adhesive layer may be made of a metal having good contact characteristics in order to form silicides with the transparent insulating substrate110. For example, the metal may be cobalt, cobalt alloy, nickel, nickel alloy, or the like.

The first wire layer may be made of a metal having good conductivity. For example, the first wire layer may be made of copper. This is a suitable even though the contact characteristics with the substrate are not very good. Additionally, the lateral surfaces of the gate line121may be inclined at an angle ranging from about 30° to about 80° measured from a horizontal plane.

Referring toFIG. 3, a gate insulating layer140may be formed on the substrate and over the gate lines121,124, and129. The gate insulating layer140may be silicon nitride or silicon oxide. A semiconductor layer150may be formed over the gate insulating layer140and the semiconductor layer is not doped with impurities. An ohmic contact layer160, which may be highly doped with n-type impurities, is formed on the gate insulating layer140. The semiconductor material may be amorphous silicon.

The gate insulating layer140, the semiconductor layer150, and the ohmic contact layer160are formed with a first CVD apparatus. The gate insulating layer140, the semiconductor layer150, and the ohmic contact layer160are successively formed.

The successive process will be described in detail with reference to the drawings as follows. The insulating substrate110on which the gate lines121are formed is brought into the first CVD apparatus. Next, the gate insulating layer140, the semiconductor layer150, and the ohmic contact layer160are successively formed on the insulating substrate110.

FIG. 4illustrates a schematic diagram of the first CVD apparatus. Referring toFIG. 4, the first CVD apparatus includes a chamber100. The chamber100is a reaction room in which a film is deposited using reaction gas and is isolated from outside. The chamber100includes a lower part10and a lid20. An O-ring30may be placed on a joint portion between the lid20and the lower part10in order to effectively isolate the reaction room from the outside.

A slot valve60may be arranged along a sidewall on the lower part10of the chamber100. The slot valve60may be opened in order to transport the insulating substrate110into the lower part10from a load lock part. A susceptor40may be arranged inside the chamber lower part10. The insulating substrate110is arranged on the susceptor40. The susceptor40may be moved up and down by a susceptor carrier45. Optionally, a heater is arranged in the susceptor40for heating the insulating substrate110.

A gas injecting pipe80amay be arranged on a joint portion of the gas piping400for injecting gas into the chamber100. A backing plate90may be arranged in front of the gas injection pipe80afor supporting a diffuser70. The backing plate90may be made of a conductive material in order to serve as a transfer metal for transferring RF power to the diffuser. In operation, reaction gas is injected through the gas injection pipe80aand strikes the diffusion plate90aformed in the backing plate90, thereby flowing around the diffusion plate90aand dispersing near the diffuser70.

The diffuser70is arranged under the backing plate90and separated from the backing plate90by a predetermined distance. The diffuser70allows the reaction gas to be substantially uniformly dispersed above the insulating substrate110and also may simultaneously serve as a plasma electrode. A plurality of injection holes70amay be formed on one a side of the diffuser70opposing the insulating substrate110. The gas is provided to the diffuser70via the gas injection pipe80aand may be uniformly dispersed over an entire surface of the insulating substrate110through the injection holes70a.The dispersed gas may be vented or exhausted via a gas exhaust pipe80b.

The diffuser70may be connected to an RF power generator200in this configuration the diffuser may serve as a plasma electrode and the susceptor40may be grounded. Power generated from the RF power generator200is tuned by a RF matcher300and transmitted to the backing plate90via the gas injection pipe80a.RF power is transferred to the diffuser70connected to the backing plate90.

Since the diffuser may serve as a plasma electrode, it should be made of a conductive material, for example, the diffuser may be made of aluminum. To protect the surface of the diffuser, the surface of the diffuser may be anodized as an oxide. A piping insulator410may be placed between the gas piping400and the gas injection pipe80ain order to prevent power from being transferred to the gas piping400.

An RPS box420and the piping insulator410may be arranged in sequence on the gas piping400, thereby creating a pathway for injecting gas into the chamber lower part10. A reaction gas box440may be filled with reaction gases. A nitrogen (N2) gas box450is connected to the chamber lower part10to create atmospheric pressure in the chamber. A fluorine (F2) supplier460is connected to an end portion of the gas piping400and used for generating an etching plasma. Additionally, the reaction gas box440may include a gate insulating layer formation box441, a semiconductor layer formation box442, and an ohmic contact layer formation box443.

FIG. 4also shows a flow of reaction gas during a CVD deposition process, more specifically, a flow of reaction gas during the deposition process of the gate insulating layer. During this process reaction gas in the gate insulating layer formation box441is injected into the lower part10. This is accomplished by passing gas through the gas injection pipe80a,the backing plate90, and the diffuser70via the gas piping400in order to form the gate insulating layer140. During this process the RPS box420serves as a piping pathway.

After the gate insulating layer140is formed, the gate insulating layer formation box441is closed and the semiconductor layer formation box442is open. Accordingly, reaction gas in the semiconductor layer formation box442is injected into the lower part10via the gas piping400, thereby forming the semiconductor layer150.

After the semiconductor layer150is formed on the gate insulating layer140, the semiconductor layer formation box442is closed and the ohmic contact layer formation box443is open. Accordingly, reaction gas in the ohmic contact layer formation box443is injected into the chamber lower part10via the gas piping400in order to form the ohmic contact layer160. After performing the foregoing processes the insulating substrate is transported to the next fabrication apparatus that may conduct different processes.

These processes may be repeated on multiple insulating substrates that may have gate lines121formed thereon prior to the processes. The successive processes may be performed from about 6 to about 9 times in the first CVD apparatus before cleaning. After about 6 to about 9 successive processes, the first CVD apparatus is cleaned with fluorine (F2). Optionally, the inside of the first CVD apparatus may be cleaned with fluorine (F2) before forming the gate insulating layer140, the semiconductor layer150, and the ohmic contact layer160.

The layers, for example, the gate insulating layer140, the semiconductor layer150, and/or the ohmic contact layer160, are deposited not only on the insulating substrate110but also on the surface of a diffuser70, thereby creating differences in thermal expansion coefficients between the diffuser70and the films deposited thereon. As a result, thermal stresses along the deposited films cause these films to become deteriorated, peel and/or flake off, and generate undesired minute particles. Accordingly, after a predetermined number of cycles, films on the inner walls of the chamber lower part10or the surface of the diffuser70may be etched by generating a fluorine (F2) plasma from the RPS box420arranged on the gas piping400.

FIG. 5shows the gas flow during a cleaning process of the first CVD apparatus using fluorine (F2) plasma etching. Referring toFIG. 5, the fluorine (F2) supplier460includes a fluorine (F2) cylinder461for storing fluorine (F2) and a fluorine (F2) generator462for generating fluorine (F2) by electrolysis. Additionally, the supplier460includes a hydrofluoric (HF) acid box463for supplying (HF) to a fluorine (F2) generator462.

The fluorine (F2) generator462generates fluorine (F2) gas via electrolysis using hydrofluoric acid (HF) provided from the hydrofluoric acid (HF) box463. Hydrogen (H2) and other impurities are generated during hydrofluoric acid (HF) electrolysis and are removed using a filter464placed between the fluorine (F2) generator and the fluorine (F2) cylinder461. Pure fluorine (F2) gas is passed through the filter464and is compressed by a compressor465and provided to the fluorine (F2) cylinder461. The compressor465is used to supply fluorine (F2) gas to the CVD apparatus at a constant pressure.

As shown inFIG. 5, during the cleaning of the first CVD apparatus, the reaction gas box440is closed while the fluorine (F2) supplier460is opened. In this configuration, the RPS box420performs an operation for forming plasma using fluorine (F2) gas injected from the fluorine (F2) supplier460. Fluorine (F2) plasma generated in the RPS box420is injected into the chamber lower part10in order to remove the film(s) deposited on the inner walls of the chamber lower part10and/or the surface of the diffuser70, thereby cleaning the CVD apparatus.

Referring toFIGS. 6A and 6B, the semiconductor layer150and the ohmic contact layer160may be etched using photolithography for creating the semiconductor patterns151and154and the ohmic contact patterns161and165directly on the gate insulating layer140.

Referring toFIGS. 7A and 7B, the second adhesive layer and the second wire layer are formed on the substrate including the ohmic contact patterns160and161. These layers are patterned via photolithography to form the data lines171,173,175, and179and the storage electrodes177, forming a multi-layered structure with the second adhesive metal patterns711,731,751, and791and the second wire metal patterns712,732,752, and792. This process is the same as the process for forming the first adhesive metal patterns and wire metal patterns.

The semiconductor layer is formed between the source electrode173and the drain electrode175. The channel portion154is formed by not overlapping a portion of the source electrode173with the semiconductor layer. The channel portion154is completed by forming the source electrode173and the drain electrode175and etching to remove the ohmic contact layer160. The source electrode173and the drain electrodes173and175are used as an etching mask during this process. Accordingly, the ohmic contact layer is divided into a source portion and a drain portion. Simultaneously, an upper portion of the channel portion154may be partially etched.

Referring toFIGS. 8A and 8B, an insulating material is applied to the entire surface of the substrate covering the data lines171,173,175, and179and the storage electrodes177, thereby forming passivation layer180. Forming the passivation layer, a first contact hole181, a second contact hole182, a third contact hole183and the fourth contact hole184are formed by photolithography in the passivation layer180.

The passivation layer180is formed with the second CVD apparatus. The formation process of the passivation layer180in the second CVD apparatus will now be described in detail with reference to the drawings.

FIG. 9illustrates a flow of reaction gas during CVD process for forming the passivation layer180. Referring toFIG. 9, the second CVD apparatus is substantially similar to the first CVD apparatus except that the reaction gas box440of the first CVD apparatus is replaced with a passivation layer formation box444.

The passivation layer deposition process will now be described. In this process reaction gas in the passivation layer formation box444is injected into the chamber lower part10. The reaction gas passes through the gas injection pipe80a,the backing plate90, and the diffuser70via the gas piping400, thereby forming the passivation layer180. In this situation the RPS box420serves as a piping pathway. After forming the passivation layer180the insulating substrate is transported to the next fabrication apparatus. This process is repeated by forming a passivation layer on another insulating substrate110, which may have data lines171formed thereon.

The second CVD apparatus is cleaned after about 12 to about 20 passivation layer deposition processes. The process forming the passivation layer180requires less number of cleaning processes as compared to the CVD apparatus forming the gate insulating layer140. This is because the thickness of the film formed during the passivation formation process is less than that of the successive processes used in forming the gate insulating layer140, the semiconductor layer150, and the ohmic contact layer160. Additionally, the inside of the second CVD apparatus may be cleaned using fluorine (F2) prior to forming the passivation layer180.

FIG. 10illustrates a gas flow during the cleaning process of the second CVD apparatus using fluorine (F2) plasma etching. Referring toFIG. 10, the passivation layer formation box444is closed while the fluorine (F2) supplier460is open. In this configuration, the RPS box420forms plasma using fluorine (F2) gas injected from the fluorine (F2) supplier460. Fluorine (F2) plasma generated in the RPS box420is injected into the lower part10in order to remove the films deposited onto the inner walls of the lower part10and/or the surface of the diffuser70.

On the other hand, as shown inFIGS. 1A and 1B, a transparent conductive layer may be formed on the insulating substrate110after the passivation layer180has been formed. This transparent conductive layer may be patterned to form the pixel electrodes190, gate contact95, and data contact97.

In the manufacturing method of a TFT array panel according to the present invention, the inside of the CVD apparatus is cleaned prior to and/or after the various deposition processes. The cleaning may be done with fluorine (F2), which is environmentally friendly and generated by the fluorine (F2) generator, thereby minimizing pollution and decreasing manufacturing costs.

Additionally, unlike nitrogen trifluoride (NF3), the conventional cleaning gas, which is purchased by the cylinder, the present invention utilizes fluorine (F2) provided by the cylinder that is connected to the hydrofluoric (HF) electrolysis apparatus. Thus, the present invention can ensure the supply of cleaning gas.