Maximum power tracking among distributed power sources

Optimum power tracking for distributed power sources may be provided by a family of power system architectures having distributed-input series-output (DISO) converters. The DISO converters may be controlled to achieve uniform input voltages across their respective distributed power sources while also tracking an optimum power point of the power system. Each DISO converter may be operably connected to a corresponding power source to form a power-processing channel. A controller may be operably connected to the plurality of DISO converters to control the operation thereof.

FIELD

The present invention generally relates to uniform input voltage distribution (UIVD) control, and more particularly, to UIVD control for distributed input series output (DISO) converter power systems.

BACKGROUND

Certain issues can arise in conventional power and control architectures that employ multiple solar arrays. Distributed array voltages may fail to achieve uniform distribution when their array panels are not identical, such as their current-voltage (I-V) curves having approximately the same peak-power voltages that respectively deliver different peak-power ratings. Also, too many maximum power tracking (MPT) controllers may be employed dedicated to their respective array panels, leading to a high part count. Further, a simpler and common MPT controller may not be present that tolerates at least a power source failure while the non-identical power sources are independently sourcing their powers to a power system consisting of distributed power channels for processing their respective distributed power sources. Accordingly, an improved power system control architecture may be beneficial.

SUMMARY

Certain embodiments of the present invention may provide solutions to the problems and needs in the art that have not yet been fully identified, appreciated, or solved by conventional power and control architectures. For example, some embodiments of the present invention pertain to a family of power system architectures where distributed-input series-output (DISO) converters are controlled to achieve uniform input voltages across their respective distributed power sources while also tracking an optimum power point of the power system. The optimum power point is a maximum power drawn from distributed power sources while voltages of the distributed power sources are uniformly distributed. With sufficient uniform input voltage distribution control, near maximum use of the power sources is achieved by employing a single MPT controller instead of multiple MPT controllers dedicated for each power source. Provided that the maximum power point voltages of the input power sources are similar, the resulting power system architectures offer near-maximum power transfer with a lower parts count.

In accordance with an embodiment of the present invention, an apparatus is provided. The apparatus includes a plurality of DISO converters connected to a corresponding power source. The apparatus also includes a controller connected to the plurality of DISO converters, the controller configured to provide uniform input voltages across each power source while tracking an optimum power point.

In another embodiment of the present invention, an apparatus is provided. The apparatus includes a multi-channel DISO power system. The multi-channel DISO power system includes outputs that are connected in series across a battery bank. The apparatus also includes a controller configured to apply a plurality of distributed control voltages. Each of the plurality of distributed control voltages is connected across a control input port of each independently sourced DISO converter such that uniform input voltage is achieved across each of a plurality of power sources.

In yet another embodiment of the present invention, an apparatus is provided. The apparatus includes a plurality of distributed-input series-output (DISO) converters and a system controller. Each of the plurality of DISO converters comprises an input connected to a corresponding power source, and is configured to provide a total output bus current signal fulfilling a system load demand and a total sourcing current signal. The total sourcing current signal may be a summation of all sourcing current signals drawn from a plurality of distributed power sources. The system controller is configured to receive a plurality of sourcing voltage signals from the plurality of distributed power sources, and generate a plurality of output voltage control signals for equal sourcing voltages at all times. The system controller is further configured to receive the total sourcing current signal or the total output bus current signal, and generate a plurality of the output voltage control signals to draw a total maximum power from the plurality of distributed power sources when in a maximum power tracking mode. The system controller is also configured to regulate a system output voltage signal received from the plurality of DISO converters when in a non-maximum power tracking mode.

DETAILED DESCRIPTION OF THE EMBODIMENTS

Distributed power sources, such as solar array panels where power flows are individually processed through their respective DC-DC converters, have become practical for flexible and reliable direct current (DC) power transmission from the sources to the loads that are commonly terminated across the system output. Currently, there are at least three possible approaches for drawing power from distributed power sources: (1) drawing power directly across each distributed power source with GT-UCD control among distributed source currents (seeFIG. 1); (2) drawing power directly across the distributed power sources with GT-UVD control of their sourcing voltages (seeFIG. 2); and (3) drawing power directly across the individual power sources, with each power source possessing its own IMPT (see system diagram300ofFIG. 3). However, each of these three approaches has at least the limitations that are discussed below.

FIG. 1illustrates a diagram100for an energy harvesting approach with GT-UCD.FIG. 1illustrates a single MPT controller102, converters104A-C, and power sources PS#1, PS#2, and PS#3. Each power source PS#1, PS#2, and PS#3is represented by a respective current source IS1, IS2, IS3, a respective source resistor RS1, RS2, RS3, and a respective diode D1, D2, D3. Each converter104A,104B, and104C is represented by a respective controlled current sink G1, G2, G3that is controlled in common by the commanding peak-power current signal IMP. The GT-UCD approach shown inFIG. 1is not only inefficient, but also fails to fully utilize distributed power sources PS#1, PS#2, and PS#3, especially when power sources PS#1, PS#2, and PS#3possess non-identical I-V characteristics.

Further, the delivered peak power from the GT-UCD approach shown inFIG. 1is below the ideal available peak power when a power source becomes weak and acts as a power dissipater instead of a power provider. Weak solar panels may include a bypass diode across their two sourcing terminals to clamp their negative voltage to a minimum. However, power delivery can still fall significantly below the available peak power. In this embodiment, G1, G2, and G3may be controlled current sinks, each of which can be realized as a DC-DC converter104A,104B,104C that has its input current controlled to follow the commanding peak-power current signal IMP.

FIG. 2illustrates a system diagram200for an energy harvesting approach with GT-UVD control.FIG. 2illustrates a single MPT controller202, converters204A-C, and power sources PS#1, PS#2, and PS#3. InFIG. 2, the GT-UVD approach employs distributed DC-DC converters204A-C, which are individually connected across their respective power sources PS#1, PS#2, and PS#3to regulate their sourcing voltages VSA1, VSA2, VSA3to be uniformly distributed at all times. In most cases, the GT-UVD approach results in a much higher delivered peak power compared to that obtained by the GT-UCD approach. For example, when the maximum power point voltages VMPof the sources are similar, uniform distribution of the power source voltages ensures that they all become power providers.

For cases having input power sources with similar peak power voltages, the power delivered by the GT-UVD system approaches the ideal peak power obtained by the IMPT approach, as shown inFIG. 3. InFIG. 3, each power source PS#1, PS#2, PS#3possesses its own IMPT controller302A,302B,302C, respectively. In this example, each MPT controller302A,302B,302C uses a respective converter304A,304B,304C to track the maximum power for each respective power source PS#1, PS#2, PS#3. The IMPT controller enables the ideal peak power to be obtainable as a summation of all available peak powers being extracted from all of the power sources in the system. However, the IMPT configuration shown inFIG. 3increases complexity, and as a result, increases cost.

FIG. 4shows the delivered power as a function of the total sourcing voltage that is the summation of all distributed voltages across the individual power sources. The three energy-harvesting approaches shown inFIGS. 1-3are analyzed through computer simulation using IS1=6 A, IS2=21.67 A, and IS3=20 A with RS1=10Ω, RS2=3Ω, and RS3=4Ω, respectively, representing power sources PS#1, PS#2, and PS#3.

The IMPT curve shown inFIG. 4provides the delivered power when IMPT controllers are distributed to their respective power sources, revealing the highest peak power that is achievable. The delivered power shown in the GT-UVD curve is obtained by the MPT controller ofFIG. 2. The MPT controller actively regulates all of the source voltages to be identical. In this example, the delivered peak power through the GT-UVD control (831.2 W) is only 1.23% off from the ideal peak power obtained by the IMPT control (842 W).

The delivered power shown in the GT-UCD curve is accomplished by the GT-UCD approach shown inFIG. 1. In the GT-UCD approach, the three non-identical power sources are terminated with their respective bypassing diodes, equivalently representing three solar array panels that are exposed to different solar illuminations, i.e., due to non-uniform shading or different array-tilting angles facing the sun. However, in this example, the GT-UCD approach can only deliver a peak power of 750.9 W, which is far from the ideal system peak power of 842 W, leading to an unattractive tracking efficiency of 89.1%. Consequently, the three P-V characteristics labeled as IMPT, GT-UVD, and GT-UCD inFIG. 4serve as comparable examples to recognize potential merits of GT-UVD control.

The GT-UVD approach for distributed power sources results in an economical and simple energy harvesting method through the use of a single MPT controller that can be managed to blend with the existing power and control architectures, whether system outputs are battery-dominated buses or dual-regulated buses. The embodiments of the present invention described below improve the efficiency of the GT-UVD approach shown inFIG. 2and offer near-maximum power transfer with reduced complexity.

FIG. 5illustrates a DC-DC converter500with an opto-isolated control input VCi, which is electrically isolated from the input power and return terminals of the converter. InFIG. 5, an output-isolated DC-DC converter502with an optocoupler circuit504is configured to provide electrical isolation to control the power flow of the converter using control input VCi. Many isolated-control converters can have their input power ports individually connected to their respective power sources while the converters are independently controllable through their respective control inputs VCiand their outputs may be connected in parallel for power delivery to a shared load. In general, each converter's input-power return −IN and the system controller's reference ground may not have the same operating voltage or may not be the same electrical node. Thus, output-isolated DC-DC converter502with optocoupler circuit504provides flexibilities for interconnection among many converters such that their input power returns do not need to be tied together to the reference ground of the system controller. A voltage at the common collector VCCis utilized to bias a voltage signal of optocoupler circuit504. An input-filter capacitor CINof sufficient capacitance is terminated across each converter input for achieving an acceptable AC input-ripple voltage, particularly when the converter input voltage is controlled to meet a certain control objective.

Output-isolated DC-DC converter502shown inFIG. 5can be a single converter power stage or a group of converter power stages that are connected in parallel. These parallel-connected converter power stages of a current-mode type may be preferred. The current-mode converter power stages allow for a common shared-bus SB voltage signal to command the converter power stages in unison to achieve uniform current sharing, and at the same time, serve other control objectives.

FIG. 6illustrates a battery dominated power system600, according to an embodiment of the present invention. In battery dominated power system600, a common bus is connected to a battery bank608. To that end,FIG. 6illustrates a battery dominated DISO converter power system architecture utilizing three distributed input converters604A,604B,604C with their outputs being series-connected across a battery bank608having an output voltage VBUS. In certain embodiments, distributed input converters604A,604B,604C include series-connected outputs to form a two-terminal network of series connected voltages across a battery bank. It should be appreciated that the number of converters may depend on the number of power sources (PS#1, PS#2, PS#3, . . . , PS#N) in the system.

A system load606may be terminated across the output to become a battery dominated voltage bus. A bus stabilizer network may be terminated across the system output voltage VBUSlocated as close to the system output port as possible to damp out AC energy, thus ensuring system stability. Each isolated-control DC-DC converter604A,604B,604C shares the following attributes: (1) a shared-bus control input SBi, which allows an external signal to take control of the converter power stage; (2) a number of parallel-connected converter modules configured with shared-bus control inputs tied together to form a common shared-bus control port to achieve nearly uniform current-sharing; (3) operation in a standalone configuration such that the output is regulated at a pre-determined voltage and its shared-bus input is left unconnected; and (4) provision of electrical isolation between input and output. In this embodiment, output-isolated converter500shown inFIG. 5is represented by each of converters604A,604B,604C shown inFIG. 6.

In this embodiment, system controller602includes six feedback input signals, e.g., battery bus voltage signal VBUS, system bus current signal IBUS, battery bank current signal IBAT, and distributed input voltages V1, V2, V3. Each input voltage V1, V2, V3corresponds to a respective converter604A,604B,604C. Voltages V1, V2, V3provide system controller602with the voltage from the power sources PS#1, PS#2, PS#3. Based on the six feedback input signals, system controller602may track power of each power source and transmit control voltage signals VC1, VC2, VC3to each converter604A,604B,604C to ensure peak performance of each power source PS#1, PS#2, PS#3. For example, based on the input signals, system controller602may detect when any of power sources PS#1, PS#2, PS#3are experiencing a reduction in power. To ensure that each of power sources PS#1, PS#2, PS#3act as a power provider and not a dissipater, system controller602transmits a voltage control signal to either each converter604A,604B,604C or to one of converters604A,604B,604C connected to the power source that is experiencing a reduction in power.

Also, in this embodiment, capacitors C1, C2, C3are terminated across respective distributed power sources PS#1, PS#2, PS#3or across respective inputs of the converters604A,604B,604C. Capacitors C1, C2, C3are configured to provide sufficient filtering of distributed currents drawn by converters604A,604B,604C such that the currents drawn from respective power sources PS#1, PS#2, PS#3have negligible AC content at the converter switching frequency. Since distributed power sources PS#1, PS#2, PS#3possess non-zero sourcing impedances, each capacitor C1, C2, C3and each associated sourcing impedance form a low-pass filtering network across the respective converter input. Such an inherent low-pass filter contributes to negligible AC switching-ripple voltage superimposed on the associated sourcing voltage, producing better signal-to-noise ratio and allowing the MPT control to effectively search for the peak power voltages across distributed power sources PS#1, PS#2, PS#3.

FIG. 7illustrates a system controller700, according to an embodiment of the present invention. It should be appreciated that system controller700shown inFIG. 7may be employed in battery dominated power system600ofFIG. 6in some embodiments.

In this embodiment, system controller700provides at least four basic control functions. First, system controller700can control the system battery charge via a battery charge controller702. Second, system controller700can perform system distributed input-voltage regulation via an input voltage regulator706. Third, system controller700can perform uniform input voltage distribution via a UIVD controller708. Fourth, system controller700can perform system maximum power tracking via MPT controller704. This embodiment also includes a bus stabilizer network terminated across the system output VBUSlocated as close to the system output port as possible to damp out AC energy, thus ensuring system stability.

In this embodiment, battery charge controller702is configured to regulate battery bus voltage signal VBUSto a preset value in accordance with its voltage-temperature (V/T) profile to prevent a battery or battery bank, such as the one shown inFIG. 6, from overcharging. When battery bus voltage signal VBUS falls below a preset value that is pre-assigned as a function of temperature, battery-bank current signal IBATmay be regulated at a preset charge-current set point determined by battery charge controller702. Active battery regulation of either battery bus voltage signal VBUSor battery bank current signal IBATcauses a forward-voltage bias across pull-down diode D.

In this embodiment, when battery bus voltage signal VBUSand battery bank current signal IBATare respectively below the preset voltage value and the preset charge-current set point, system controller700may regulate the system distributed-input voltage V1at the optimum peak power voltage that is determined by MPT controller704. For example, MPT controller704may receive a system bus current signal IBUSand an optimum peak power voltage V1to generate a commanding set point voltage signal VSPTthat includes a set point reference voltage signal VSP.

It should be appreciated that as long as operating battery bus voltage signal VBUSand battery bank current signal IBATare below their preset voltage/charge-current values, the DISO converter power system shown inFIG. 6may be controlled to have an optimum power transfer from all distributed power sources by utilizing a single MPT controller704that dominates its control over battery charge controller702through a primary control voltage signal VCand the reverse-biased diode D.

One of the following three operational modes may be active at a time in some embodiments—battery voltage regulation for compliance with a V/T profile, battery charge-current regulation for serving a commanding charge rate, or distributed-input voltage regulation (IVR) for tracking a system optimum-power voltage. Uniform voltage distribution among converter-input voltages delivered by all distributed power sources is actively regulated at all times by UIVD controller708. During any of these three operating modes, converter-input voltages V1, V2, V3across the distributed power sources PS#1, PS#2, PS#3are regulated to be equal by UIVD controller708. UIVD controller708is configured to distribute, in this embodiment, three voltage control signals VC1, VC2, VC3to their respective isolated-control converters604A,604B,604C.

FIG. 8illustrates a UIVD controller800for three series connected converters, according to an embodiment of the present invention. It should be appreciated that a DISO power system may include N isolated-control DC-DC converters with their respective N distributed power sources PS#1, PS#2, . . . , PS#N.

During battery voltage and/or current regulation, or during the distributed input voltage regulation, input voltage distribution controller802may produce secondary voltage control signals (Vd1, Vd2, . . . , VdN). The number of secondary voltage control signals depends upon the number of converters in the DIPO power system. In this embodiment, controller802produces or generates three secondary voltage control signals Vd1, Vd2, Vd3based on at least voltage signals V1, V2, V3. Determination of secondary voltage control signals Vd1, Vd2, Vd3is discussed with respect toFIGS. 9 and 10. Secondary voltage control signals Vd1, Vd2, Vd3may be subtracted from the voltage control signal VCat nodes804A,804B,804C to create modified control voltages VC1, VC2, VC3to regulate the respective converter to accomplish uniform input voltage distribution.

FIG. 9illustrates a central-limit UIVD controller900, according to an embodiment of the present invention. InFIG. 9, a common distributed voltage reference signal VDIS=V1/N may be generated as a central-limit (CL) distribution reference. In this case, N=3 for the number of distributed converters, but N may change based on the number of distributed converters in the given architecture.

Each voltage distribution error amplifier902A-C is configured to amplify the voltage difference between a common distributed voltage reference signal VDISand each converter-input voltage V1, V2, V3. Each voltage distribution error amplifier902A-C is further configured to compensate for the frequency and generate a voltage distribution control signal (Vd1, Vd2, Vd3) for each converter. Each voltage distribution control signal Vdiis configured to provide a minor control correction to voltage control signal VC, thus ensuring uniform input voltage distribution.

However, it should be appreciated that UIVD controller900may not be fault-tolerant when the common distributed voltage reference signal VDIS=V1/N is the central-limit (CL) distribution reference. For example, if a single converter fails and cannot be controlled due to a short circuit across its input, the system may lose regulation.

To overcome such issues,FIG. 10illustrates a fault-tolerant UIVD controller1000using a maximum limit (ML) distribution reference, according to an embodiment of the present invention. For example,FIG. 10shows a UIVD controller1000having voltage distribution error amplifiers1002A-N that are based on the ML distribution reference VDIS=MAX(V1, V2, . . . , VN). To achieve fault-tolerance, a set of ideal rectifiers1004is included as part of UIVD controller1000to produce a common distributed voltage reference signal VDIS, which is the highest converter-input voltage obtained from one of the distributed converters within the power system. In other words, VDISis the maximum limit selection candidate. Common distributed voltage reference signal VDIScorresponds to the sourcing input voltage of the strongest power source among N distributed power sources, wherein the strongest power source provides the highest power among distributed powers delivered by the N power sources.

Using such a configuration, if a converter fails due to an input short circuit, common distributed voltage reference signal VDISmay be automatically updated to compensate for the loss of a failed converter or the failure of its respective input power source. For the system to tolerate at least one converter input short circuit failure, two ideal rectifiers may be required to sense the output voltage from any two converters. Up to N ideal rectifiers may be included in UIVD controller1000for an N-converter DISO system for tolerance up to N−1 power source failures.

In this embodiment,FIG. 10illustrates UIVD controller1000for a three-converter DISO power system with fault-tolerance. A common distributed voltage reference signal VDISmay be derived from N cathode-parallel-connected ideal rectifiers1004to individually sense the input voltages of converters, e.g., converters604A,604B,604C ofFIG. 6. For example, if one converter fails to build up its input voltage, the N−1 remaining converters will be controlled to have uniform input voltage distribution. A protection fuse may be inserted in series with either the positive input of each DISO converter or the positive output of its respective power source provides a simple method of fault clearing to prevent thermal overstress on the power system.

Furthermore, the DC gain for each voltage distribution error amplifier1002A,1002B, . . . ,1002N does not need to be too high in order to achieve uniform input voltage distribution. To the contrary, excessive DC gain within each distribution error amplifier1002A,1002B, . . . ,1002N causes UIVD controller1000to dominate the battery charge control and the distributed-input voltage regulation modes of operation, resulting in insufficient charging to the battery bank.

FIG. 11illustrates a dual-regulated bus power system1100with UIVD control, according to an embodiment of the present invention. In this embodiment, dual-regulated bus power system1100includes a 3-channel DISO converter power system1104. 3-channel DISO converter power system1104includes three independently sourced input converters (not shown), each converter having outputs that are series-connected across a battery bank1112. Battery bank1112has a battery bus output voltage VBUS. A system load1110may be terminated across output voltage VBUS to become a battery dominated voltage bus.

Similar to capacitors C1, C2, C3ofFIG. 6, capacitors C1, C2, C3shown inFIG. 11are terminated across respective distributed power sources PS#1, PS#2, PS#3or across respective inputs of 3-channel DISO converter power system1104. Capacitors C1, C2, C3are configured to provide sufficient filtering of distributed currents drawn by 3-channel DISO converter power system1104such that the currents drawn from their respective power sources PS#1, PS#2, PS#3have negligible AC content at the converter switching frequency. Since distributed power sources PS#1, PS#2, PS#3possess non-zero sourcing impedances, each capacitor C1, C2, C3and each associated sourcing impedance form a low-pass filtering network across the respective converter input. Such an inherent low-pass filter contributes to negligible AC switching-ripple voltage superimposed on the associated sourcing voltage, producing better signal-to-noise ratio and allowing the MPT control to effectively search for the peak power voltages across distributed power sources PS#1, PS#2, PS#3.

Bus load1108may be terminated across a regulated bus voltage signal VOUT. Bus load1108may be a single load or a group of load circuits that can share the same bus voltage signal VOUT. Load characteristics may include a resistive load, a constant current-sink, a constant-power load, or a combination of one or more load types. As long as bus load1108is compatible with a regulated bus sourcing impedance (i.e., the sourcing impedance exhibits a lower magnitude than a load impedance), a closed loop control for regulated bus voltage signal VOUTcan robustly regulate bus voltage signal VOUTwithout any instability. Since bus load1108may include various load types that require tight voltage regulation, regulated bus voltage signal VOUTenables more types of load to draw power off of bus load1108.

Each independently sourced input converter may share the same four attributes as previously described in relation toFIG. 6. In this embodiment, however, system controller1102has seven feedback input signals: a battery bus voltage signal VBUS, a regulated bus output voltage signal VOUT, a system battery bus current signal IBUS, a charging battery bank current signal IBAT, and distributed input voltages V1, V2, V3from the three independently sourced input converters, or from 3-channel DISO converter power system1104. System controller1102can provide system voltage regulation of bus output voltage signal VOUT. System controller1102can also provide battery charge control. Further, system controller1102can provide system distributed-input voltage regulation, as well as uniform input voltage distribution. Additionally, system controller1102can provide system maximum power tracking.

A bus stabilizer network may be terminated across the regulated bus output voltage signal VOUTlocated as close to the system output port as possible to damp out AC energy, thus ensuring system stability. Regulated bus output voltage signal VOUTis on a closed-loop and controlled by an output isolated DC-DC converter1106with its output port VO4that is series-connected with battery bus voltage VBUS. The output-series-connected converter significantly improves the system efficiency since output voltage signal VO4can be a minor portion of the overall output voltage signal VOUTand battery voltage signal VBUScan be the major portion. Voltage control signal VC4may drive the power stage of output isolated DC-DC converter1106to regulate the output voltage VOUTat a fixed value above the system battery-bus voltage VBUS.

FIG. 12illustrates a system controller1200for the dual regulated bus power system1100shown inFIG. 11, according to an embodiment of the present invention. System controller1200generally provides more fault-tolerant coverage than system controller700ofFIG. 7. In this embodiment, MPT controller1210receives a system battery bus current signal IBUSand a dither voltage signal VDITHERand generates a set point reference voltage signal VSP. The summation of the dither voltage signal VDITHERand set point reference signal VSPmay generate a commanding set point voltage signal VSPTfor regulation of the common distributed voltage reference signal VDIS.

Like battery charge controller702, battery charge controller1202may have a similar function in this embodiment. Similarly, UIVD controller1208may have similar functionality as UIVD controller708. Unlike inFIG. 7, input voltage regulator1204receives a common distributed voltage reference signal VDISas its feedback input instead of voltage V1from PS#1. Since common distributed voltage reference signal VDISis the maximum-limit voltage, i.e., the maximum voltage detected from power sources or VDIS=MAX(V1, V2, . . . , VN), input voltage regulator1204can provide an active control on the common distributed voltage reference signal VDISto follow a commanding set point voltage VSPT. In this embodiment, there will always be an input voltage from one converter that is the highest among all of the distributed-input voltages while they are controlled to have a uniform distribution at all times. This maximum-limit input voltage regulation allows the converter power system to tolerate more than one failure due to short circuit or open circuit of power sources, as well as short circuit or overload across distributed inputs of DISO converters.

Also, in this embodiment, system control1200includes an output voltage regulator1206that generates a control voltage signal VC4to be transmitted to an output isolated DC-DC converter1106shown inFIG. 11. Control voltage signal VC4may regulate system output voltage signal VOUT. Control voltage signal VC4is the amplified frequency-compensated error signal that is proportional to the difference between reference voltage signal VREFand system output voltage signal VOUT. As control voltage signal VC4increases, output isolated DC-DC converter1106absorbs more input current drawn from the battery voltage signal VBUSto provide sufficient output voltage VO4so that system output voltage signal VOUTis tightly regulated to the target value corresponding to the voltage reference signal VREF. In this manner, output voltage regulator1206can be an operational amplifier (OP-AMP) analog circuit that serves as an error-voltage amplifier that accepts two inputs, system output voltage signal VOUTand voltage reference signal VREF, and delivers one output control voltage signal VC4.

FIG. 13illustrates a streamlined MPT controller1300, according to an embodiment of the present invention. In this embodiment, MPT processing circuit1302receives and processes two signals—total system battery bus current signal IBUSand AC dither signal VDITHERhaving a low frequency. MPT processing circuit1302generates a commanding set point voltage signal VSPTthat includes a set point reference voltage signal VSPand the AC dither signal VDITHER. It should be appreciated that streamlined MPT controller1300has a single feedback input, e.g., the total system battery bus current signal IBUS. This embodiment does not require additional feedback inputs, such as a feedback input for voltage V1.

FIG. 14is a block diagram illustrating a MPT processing circuit1400similar to that shown inFIG. 13, according to an embodiment of the present invention. In this embodiment, the main feedback signal for MPT processing circuit1400is total system battery current signal IBUSof the entire converter power system that is controlled to provide a maximum output current. Front-end differential-mode high-pass filter (HPF)1402removes the DC content from the total system battery current signal IBUSand provides a differential-mode AC output signal across voltage-limiting diodes D1and D2. The high-pass-filtered AC current signal is then biased with a common-mode voltage and a low-pass filter (LPF)1406to remove high-frequency noise. In this manner, cascaded differential-mode HPF1402and LPF1406stages produce a band-limited AC power signal Pacthat is proportional to the incremental power delivered by the solar array source. Subsequently, a voltage comparator circuit1410converts Pacinto a logical voltage signal.

Simultaneously, in a parallel path, differential-mode HPF1404and LPF1408stages extract an AC voltage signal Vacfrom the dither voltage signal VDITHERthat is also converted into another logical voltage signal through voltage comparator circuit1412. The filtered AC dither signal Vacmay be in-phase with the solar array dither voltage. Incremental power signal Pacand AC dither voltage signal Vacmay be processed through an exclusive OR (XOR) gate1414to decode their phase relationship Vx. Depending on the phase shift between the power signal Pacand dither voltage signal Vac, the DC value of voltage signal Vxmay drift from its idle DC value, usually set to 50 percent of the supplying voltage to XOR gate1414. The deviation of the voltage signal's Vxaverage voltage from its idle DC value can cause downstream voltage integrator circuit1416to slowly update the set point reference output signal VSPtoward a value corresponding to the peak-power voltage Vmp, of the solar array.

To ensure a proper idle state of MPT processing circuit1400, the reference voltage feeding the positive input of voltage integrator1416may be slightly reduced by a small value Δ, such that the idle state of the set point reference voltage signal VSPcorresponds to the array voltage just below the array peak-power voltage. This causes streamlined MPT controller1300to stay in an idle state and be triggered for active maximum power tracking when the solar array voltage reduces to the idle set point voltage VSPMIN.

When the DISO converter power system is controlled under the MPT mode of operation in some embodiments, a transient response of distributed sourcing input voltage V1is simulated to verify a stable transition during two simultaneous step changes of power source PS#1open-circuit voltage from 60 V to 80 V and power source PS#3open-circuit voltage from 60 V to 50 V at time t=5 s. As shown in the middle of graph2100ofFIG. 21, three operating sourcing voltages V1, V2, V3are 31 V before t=5 s and 32.23 V after t=8.5 s. This shows that operating sourcing voltages V1, V2, V3are nearly the same as the ideal peak-power voltages of 30 V and 32.04 V depicted inFIG. 21. In other words, graph2100shows that MPT controller1300tracks the group peak power using the UIVD approach. As a consequence, the battery charge current IBATincreases from 9.8 A to 11.39 A, as shown in the bottom plot ofFIG. 21. This reveals a power increase of 136.8 W, which is absorbed by the 90 V battery. As compared to theoretical P-V characteristics shown inFIG. 17, the two tracked peak powers of 1.16 kW and 1.35 kW shown in the top plot ofFIG. 21are respectively at 99.1% and 99.5% tracking efficiency.

FIG. 15is a graph1500illustrating a simulated response of battery dominated power system600ofFIG. 6, according to an embodiment of the present invention. In this embodiment, graph1500illustrates a simulated response of battery dominated power system600during both input voltage regulation with GT-UVD and battery-charge current regulation modes of operation and their transient transition. The simulation result demonstrates a mode transition from an input-voltage regulation mode to a normal battery-charge current regulation mode. During the mode transition, the charge-current set point reference is reduced from above 12 A to about 9.8 A at time t=5.04 s. This change of the set point reference command causes the battery current IBATto drop from 11.3 A to 9.8 A (see the lower plot ofFIG. 15) and the distributed sourcing voltages V1, V2, V3to increase from 32.24 V to 44.4 V (see the upper plot ofFIG. 15).

During both modes of operation in steady state and their transient mode transitions, the three distributed sourcing voltages V1, V2, V3are controlled across the individual inputs of three respective converters to have uniform distribution at all times, as shown in the three overlapping traces of the upper plot inFIG. 15. The MPT controller is active during the input-voltage regulation mode. Thus, all of the sourcing voltages contain a 20 Hz sinusoidal voltage VDITHERthat provides a continuous perturbation to all sourcing voltages and subsequently produces a 20 Hz response that is superimposed on the total system battery current signal IBUS.

FIG. 15also shows that the 20-Hz frequency component within total system battery bus current signal IBUSis extracted and processed by the MPT controller to update the set point reference voltage signal VSP. The commanding set point voltage signal VSPT, including set point reference voltage signal VSPand a small-amplitude dither voltage signal VDITHER, serves as the commanding voltage signal for regulation of the feedback voltage signal VDIS. In some embodiments, feedback voltage signal VDISis the maximum-limit distribution reference, as shown inFIG. 10.

FIG. 16is another graph1600illustrating a simulated response of the battery dominated power system600ofFIG. 6, according to an embodiment of the present invention. Graph1600shows a simulated response of battery dominated power system (or three-converter DISO power system)600during an input-voltage regulation with GT-UVD and battery-charge current regulation modes of operation and their transient transition.

For example, the simulation result shown inFIG. 16reveals a transition from the battery charge current regulation mode to the input voltage regulation mode. Three sourcing input voltages V1, V2, V3shown in the middle plot are all regulated at a commanding set point voltage signal VSPT, i.e., autonomously updated to approach a voltage corresponding to the system peak power voltage of 32.5 V (and eventually to 32.24 V) with 0.5 V peak-to-peak dither voltage ripple. The change in the operation mode occurs as a result of a step-change in the commanding charge-current reference signal from 0.1 V (corresponding to 10-A charge-current) to 0.5 V (corresponding to 50-A charge current), as shown in the top plot ofFIG. 16. The increased charger command causes diode D ofFIG. 7to be reverse-biased since input voltage regulator706has entered its active linear region to prevent the system input voltages V1, V2, V3from collapsing below their existing commanding set point voltage VSPT. The maximum power tracking operation, e.g., MPT controller704, takes over the battery charge current regulation since the available system peak power cannot deliver enough current to charge the battery at the 50 A current corresponding to the 0.5 V commanding charge-current reference signal. Consequently, battery current IBATis saturated at 11.35 A as shown in the bottom plot ofFIG. 16.

FIG. 17is a graph1700illustrating an anticipated response of battery dominated power system600ofFIG. 6with a single MPT controller, according to an embodiment of the present invention. Graph1700shows a possible transition from a lower peak power to a higher peak power due to changes in I-V characteristics of two power sources among three power sources controlled by DISO converters604A,604B,604C ofFIG. 6.

In graph1700, the theoretical delivered power is shown as a function of the total sum of the distributed converter-input voltages under UVD control. For instance, when the three sources have identical open-circuit voltages of 60 VDC, the total peak-power voltage is 89.928 V, or 29.976 V per power source, and the total peak power is 1170 W, as shown in the lower curve. When open-circuit voltages of power source PS#1and power source PS#3are respectively changed to 80 V and 50 V, the total peak-power voltage becomes 96.122 V, or 32.04 V per power source, and the delivered peak power is 1357 W, as shown in the upper curve. Therefore, the peak power voltage per power source changes from 29.976 V to 32.04 V when MPT controller602is enabled.

DISO converters604A,604B,604C have outputs connected in series across a battery that exhibits a very low impedance, such that output current IBUSis proportional to the total power delivered by power sources PS#1, PS#2, PS#3. A delta change in net output current ΔIBUSdelivered by DISO converters604A,604B,604C always reflects a delta change in the total power delivered by power sources PS#1, PS#2, PS#3(ΔPSOURCE). Superimposing a small AC dither voltage signal onto uniformly controlled converter input voltage signal ΔV1results in an AC output current signal ΔIBUShaving three major phase responses. First, net output current signal ΔIBUSand uniformly controlled converter input voltage signal ΔV1are in-phase when the DC operating voltage across distributed converter input signal V1is below the peak-power voltage. Second, net output current signal ΔIBUSand uniformly controlled converter input voltage signal ΔV1are 180° out of phase when input voltage signal V1has a DC voltage above the peak-power voltage. Third, net output current signal ΔIBUSand uniformly controlled converter input voltage signal ΔV1are 90° out of phase when input voltage signal V1is at the peak-power voltage.

As shown in graphs1800,1900, and2000ofFIGS. 18-20, the phase response between the two AC signals provide a basis for developing MPT controller602ofFIG. 6or MPT controller1102ofFIG. 11. MPT controller602,1102ofFIGS. 6 and 11can compare the two AC signals and slowly update the set point reference voltage signal VSP. Set point reference voltage signal VSPcommands the input voltage regulator to exert a control voltage signal VCto regulate the distributed-input voltage signal V1at the system peak power voltage.

FIG. 22is a graph2200illustrating a simulated response of three input voltage signals V1, V2, V3and a system regulated bus voltage signal VOUTfor dual-regulated bus power system1100ofFIG. 11, according to an embodiment of the present invention. Graph2100illustrates the simulated response of system output bus voltage signal VOUTin the bottom plot and the distributed-input voltages signal V1, V2, V3depicted as three overlapping traces in the middle plot. Output bus voltage signal VOUTis regulated at 120 VDC at all times despite a 7 A step-load shown as a system load current trace ILOADin the bottom plot. The 7 A step-load causes battery charge current IBATto drop from 9.4 A to 1.99 A at time t=15 s since MPT controller1102still tracks the group peak-power voltage, V1=32.12 VDC, without loss of UIVD control.

FIG. 23is a graph2300illustrating a simulated response of distributed source voltage signals V1, V2, V3, system output voltage signal VOUT, and total sourcing power signal PINfor dual-regulated bus power system1100shown inFIG. 11, according to an embodiment of the present invention. In particular, the simulated response includes GT-UVD control before, during, and after a power source failure. Graph2300shows the simulated response result of the distributed source voltage signals V1, V2, V3in the bottom plot, the system output voltage signal VOUTin the middle plot, and total sourcing power signal PINin the top plot. In other words, graph2300shows the system tolerance of more than one power source failures.

As shown in graph2300, for time 5<t<9 s, power source PS#3fails to deliver power (V3=0), and remaining power sources PS#1and PS#2are able to deliver their total sourcing power of 1137 W, resulting in 99.9% of tracking efficiency for power sources PS#1and PS#2. For time 9<t<15 s, power source PS#2fails (V2=0), and power sources PS#1and PS#3are able to deliver 1 kW as their total optimum power, revealing 99.7% of tracking efficiency for power sources PS#1and PS#3. For time 15<t<21 s, power source PS#1fails (V1=0), and 605 W of the total optimum power is produced from power sources PS#2and PS#3, demonstrating 99.98% tracking efficiency. For time 21<t<27 s, two power sources, PS #1and #3, fail and power source PS#2delivers its optimum power of 359 W, which is almost the same as the 360 W ideal peak power that PS#2can provide. As all three power sources PS#1, PS#2, PS#3are restored to normal after time t=27 s, power sources PS#1, PS#2, PS#3return to 1357 W, which is the total optimum power. During all five of these simulated scenarios, the system output voltage signal VOUT(the middle plot ofFIG. 23) is well regulated at 120 V, and the voltages across any remaining functioning power sources are uniformly distributed as anticipated.

FIGS. 24A and 24Bare block diagrams of a three-channel DISO converter power system2400A,2400B, according to an embodiment of the present invention. Power systems2400A,2400B include a system controller2402that has five feedback signals, i.e., voltage signals V1, V2, V3, output voltage signal VOUT, and total sourcing current signal Is (or alternatively total output bus current IBUS), to serve as inputs to system controller2402. In this embodiment, sourcing voltage signals V1, V2, V3are basic feedback signals for system controller2402to properly distribute three voltage control output signals VC1, VC2, VC3for equal sourcing voltages V1=V2=V3. System output voltage signal VOUTof DISO converters2404A,2404B,2404C is fed back to system controller2402such that output voltage signal VOUTis regulated under normal operating conditions, which are considered to be in a non-maximum power tracking (non-MPT) mode. Total sourcing current signal ISmay serve as a mandatory signal for computation of the total sourcing power signal instead of the use of the total output bus current IBUS. It should be appreciated that system controller2402may operate in the same or similar manner as system controller602ofFIG. 6and/or system controller1102ofFIG. 11.

Resistor RsinFIGS. 24A and 24Bserves as a current sensor of all sourcing currents drawn from distributed power sources PS#1, PS#2, PS#3. In this manner, the voltage drop across resistor Rs is proportional to the total sourcing current contributed by each power source PS#1, PS#2, PS#3. When one terminal of resistor Rs is tied to the system ground, the other terminal of resistor RSis connected to node Is to provide a negative voltage having the magnitude being proportional to the total sourcing current. Again, each capacitor C1, C2, and C3is terminated across its respective distributed power source PS#1, PS#2, PS#3or across the respective input of DISO converter2404A,2404B,2404C. Capacitors C1, C2, C3are configured to provide sufficient filtering of distributed currents drawn by DISO converters2404A,2404B,2404C such that the currents drawn from respective power sources PS#1, PS#2, PS#3have negligible AC content at the converter switching frequency.

InFIG. 24B, power system2400B includes a selectable switch S1. Selectable switch S1is configured to provide for two design choices of power architectures with a regulated system bus voltage signal VOUT:position A and position B of selectable switch S1.

In the embodiment associated with position A, power system2400B uses a non-isolated input-series connection to DISO converters2404A,2404B,2404C. In the non-isolated input-series connection, distributed sourcing voltage signals V1, V2, V3may be a direct contributor of system output voltage signal VOUT. Also, in this embodiment, three paralleled paths of distributed sourcing voltage signals V1, V2, V3are connected in series with an output voltage string comprising three series-connected outputs of DISO converters2404A,2404B,2404C. Three paralleled-cathode diodes CR1, CR2, CR3may provide a common sourcing voltage signal VRTNconfigured to collect three currents drawn from distributed power sources PS#1, PS#2, PS#3having distributed sourcing voltage signals V1, V2, V3, respectively connected to anodes of diodes CR1, CR2, CR3.

As a result, when selectable switch S1is in position A, a non-isolated power architecture can be achieved. In the non-isolated power architecture, the output power return of DISO converters'2404A,2404B,2404C series-connected output is connected to common sourcing voltage node VRTN, leading to a non-isolated system output voltage signal VOUT. Output voltage signal VOUTmay become the summation of series-connected output voltages of DISO converters2404A,2404B,2404C and common sourcing voltage signal VRTN. When selectable switch S1is in position A, a higher power conversion efficiency can be easily obtained since common sourcing voltage signal VRTNat the common sourcing voltage node VRTNmay provide a direct power contribution to the total system output power. System output voltage signal VOUTincludes four series-connected voltage signals: output voltage signals VO1, VO2, VO3obtained from three DISO converters2404A,2404B,2404C, and common sourcing voltage signal VRTN.

When selectable switch S1is moved to position B, power system2400B utilizes an isolated output-series connection with DISO converters2404A,2404B,2404C. In this embodiment, the series-connected outputs of DISO converters2404A,2404B,2404C are the contributor of system output voltage signal VOUT. Also, in this embodiment, paralleled-cathode diodes CR1, CR2, CR3are not used and may also be removed from power system2400B.

When selectable switch S1is in position B, an isolated input/output power architecture can be achieved. For example, the power return of the series connected output of DISO converters2404A,2404B,2404C is grounded, and common sourcing voltage signal VRTNor paralleled-cathode diodes CR1, CR2, and CR3are not used. This leads to an input-output isolation capability where isolated system output voltage signal VOUTincludes the series-connected output voltages of DISO converters2404A,2404B,2404C. The input power return for all DISO converter inputs can be electrically isolated (as an option) from the system GROUND, i.e. the ground symbol connected to the negative terminal of capacitor C3can be removed or replaced by a different ground node that is isolated from the system output ground node.

B position of switch S1is also configured to provide electrical isolation between distributed power sources PS#1, PS#2, PS#3and system output voltage signal VOUT. This way, system output voltage signal VOUTincludes the summation of three series-connected voltage signals: output voltage signals VO1, VO2, VO3obtained from DISO converters2404A,2404B,2404C.

FIGS. 25A and 25Bare block diagrams illustrating system controller2500A,2500B, according to an embodiment of the present invention. System controller2500A,2500B may be system controller2402shown inFIGS. 24A and 24B, respectively. InFIGS. 25A and 25B, the following control functions may be implemented: output voltage regulation (OVR)2502, identification of a maximum-power voltage candidate through MPT controller2506, input voltage regulation (IVR)2508, and uniform input voltage distribution (UIVD)2504.

InFIG. 25B, system controller2500B also includes a selectable switch S2configured to select feedback current signal as total output bus current signal IBUS(position A) or total sourcing current signal IS(position B).

In one embodiment, selectable switch S2selects position A when total output bus current signal IBUSis used for MPT control. This occurs when system load2406shown inFIG. 24Bincludes a sufficiently large filtering capacitance as compared to the internal filtering capacitance across the total output of the DISO converters. As the system load possesses a large load capacitance, total output bus current signal IBUSmay provide an AC ripple content representing the total AC power ripple, which is the main ingredient for MPT control to detect the control direction toward the peak power condition.

In a further embodiment, selectable switch S2selects position B when total sourcing current signal ISis used for MPT control instead of total output bus current signal IBUS. This may occur when system load2406does not possess a sufficiently large filtering capacitance as compared to the internal filtering capacitance across the total output of the DISO converters, leading to the inability of total bus current signal IBUSto represent the small-signal variation of the power signal. When selectable switch moves to position B, power signal PLis computed using multiplier2510. For example, multiplier2510computes power signal PLthrough multiplication between total sourcing current signal ISand maximum-limit voltage signal VS. Consequently, computed power signal PLis fed to the input of MPT controller2506input as the power signal PS. Power signal PLprovides a true representative of small-signal variation of power at the cost of an extra multiplier. In either position A or position B of selectable switch S2, streamlined MPT controller2506is applicable since the internal dither signal is used to feed the other input of MPT controller2506instead of maximum-limit voltage signal VS.

Under a non-MPT mode of operation, OVR controller2502may actively regulate system output voltage signal VOUTby delivering a primary control signal VCwhile MPT controller2506and IVR controller2508are in stand-by mode. This way, MPT controller2506and IVR controller2508do not interfere with the normal OVR function. Diode D may be reverse-biased to prevent the IVR control from being in conflict with the output voltage regulation since the sourcing voltages under normal OVR mode are above the minimum sourcing voltage corresponding to the stand-by minimum set-point voltage signal VSP-MINor idle VSP=VSP_MIN.

Whenever the load demand across output voltage signal VOUTexceeds the system maximum power, OVR controller2502loses its active regulation, and the sourcing voltages collapse toward idle minimum sourcing voltage signal VSP=VSP_MIN. The sourcing voltage collapse triggers MPT controller2506and IVR controller2508to engage control contribution to primary control signal VCsince diode D becomes forward-biased. Forward-biased diode D provides an active pull-down to system control voltage signal VCthat is no longer controlled by OVR controller2502since the output impedance of IVR controller2508becomes significantly less than the output impedance of OVR controller2502. When the transition from OVR mode to MPT mode occurs, the set point voltage signal VSPstarts increasing from its minimum idle voltage signal VSP_MIN, which corresponds to the minimum sourcing voltage. Consequently, maximum-limit sourcing voltage signal VSis regulated by IVR controller2508to track a voltage value corresponding to maximum-power set point voltage signal VSP. In certain embodiments, maximum-limit sourcing voltage signal VSis obtained from the strongest power source among the three distributed power sources through the maximum-limit detection circuit, e.g., three paralleled-cathode diodes D1, D2, and D3. Furthermore, maximum-limit sourcing voltage signal VSalso possesses a low-frequency AC signal content that is in phase with the AC dither signal being superimposed on the maximum-power set-point voltage signal VSP.

In this embodiment, UIVD controller2504has sufficient gain and control bandwidth such that the sourcing voltages belonging to weak power sources can be regulated to track the sourcing voltage belonging to the strongest power source. UIVD controller2504may still function properly even with the presence of a short circuit fault across any power source because voltages across the remaining functional power sources are controllable to be uniformly distributed or nearly equal. This allows the 3-channel DISO power system to tolerate failures in up to two of the three power sources.

FIG. 26is a block diagram illustrating a HKPS2600, according to an embodiment of the present invention. In this embodiment, HKPS2600includes input voltage signals V1, V2, and V3and output voltage signal VOUT. Diodes D5, D6, D7form a parallel-cathode network that supplies the highest sourcing voltage among voltage signals V1, V2, V3to a front-end linear regulator circuit2610. Front-end linear regulator circuit2610includes passive components and an N-channel metal-oxide-semiconductor field-effect transistor MOSFET, and is configured to provide a start-up input voltage across capacitor C1for HKPS converter2604to process into +12 V and −12 V DC output voltages. The ±12 V voltages shown inFIG. 26provide necessary supply voltages to OVR and UIVD controller PCB2608and IVR and MPT controller PCB2606.

A +5 V regulator2602is configured to provide +5 VDC output from the +12 V input. The +5 V bias is supplied to three opto-coupler interface circuits that transport distributed control signals VC1, VC2, VC3through their respective opto-couplers to shared buses SB1, SB2, SB3, respectively. It should be appreciated that a +VCC node associated with each opto-coupler interface circuit, as shown inFIG. 5, is biased by the +5V. A dither signal injection is fed externally at the DITHER input of MPT and IVR controller PCB2606through a step-down transformer2612that converts a 60 Hz 110 VAC utility grid voltage to a 12 VAC voltage with a potentiometer serving as a voltage divider for fine tuning a proper amount of the small-signal injection into the MPT control loop.

FIG. 27is a block diagram illustrating a MPT controller2700with a multiplier2718for power calculation, according to an embodiment of the present invention. In this embodiment, multiplier2718is configured to compute total input power signal PSas the feedback input to high pass filter2702instead of sourcing output bus current IBUS, as shown inFIG. 14. This power signal Ps extraction, based on multiplication between input voltage signal VSand total input sourcing current signal Is, can be used instead of sourcing output bus current signal IBUSbecause the COTS converters possess significant internal output capacitances that distort the phase response of sourcing output bus current signal IBUS.

It should be appreciated that high pass filters2702,2704, low pass filters2706,2708, voltage comparators2710,2712, XOR gate2714, and voltage integrator2716have similar functionalities to high pass filters1402,1404, low pass filters,1406,1408, voltage comparators1410,1412, XOR gate1414, and voltage integrator1416, respectively, ofFIG. 14.

Some embodiments discussed herein pertain to UIVD control for a DISO converter power system. The UIVD control for DISO converters achieves grouped maximum power throughput from non-identical renewable power sources. Also, in some embodiments, a single MPT controller is configured to facilitate simultaneous processing of distributed power flows. For example, when distributed power sources have similar peak power voltages with an achievable tracking efficiency of greater than 96%, multiple MPT controllers are not necessary. By utilizing UIVD control, near-maximum use of available power is achieved using a single MPT controller. Thus, the resulting power system and control architecture offers near-maximum power transfer with a lower part count.