High-speed and high-precision phase locked loop

A phase lock loop includes a charge pump, a voltage controlled oscillator (VCO), and a phase frequency detector. The phase frequency detector has a dynamic logic structure. The phase frequency detector generates up and down signals for directing the charge pump to provide a voltage signal to the VCO to vary the frequency of the VCO clock. The difference between the up and down signals is indicative of the phase difference between the reference clock signal and the VCO clock. The phase frequency detector includes up and down signal generators for generating the up and down signals, respectively.

FIELD OF THE INVENTION

This invention relates to phase-lock loop circuits, and more particularly to high speed and high-precision phase frequency detectors.

BACKGROUND OF THE INVENTION

Phase lock loops (PLL) typically include a phase frequency detector (PFD) that provides control signals indicative of a phase difference between a reference clock and an oscillation signal or a VCO clock of a voltage controlled oscillator (VCO). A charge pump provides a voltage signal to the VCO in response to the control signals. The VCO provides the oscillation signal responsive to the voltage signal.

As the frequency of the reference clock is increased, the performance requirements of the phase lock loop becomes more stringent. A high performance PLL has low clock jitter at its operation frequency. The PLL jitter is caused by two major factors. First, the supply noise can abruptly change the frequency of the VCO and result in PLL clock output jitter. This type of jitter can be reduced by increasing the noise immunity of the VCO circuitry. The second major factor is the precision of the phase frequency detector. A low precision of phase frequency detector typically has a large minimum detectable phase difference (or “dead zone”), which increases the jitter. The jitter caused by the low precision phase frequency detector can be reduced by increasing the precision of the phase frequency detector. A phase frequency detector including a conventional static logic gate structure has a speed limitation due to the propagation delay through multiple logic gate stages. This speed limitation increases the dead zone in the operation of the phase frequency detector at high frequency, and hence increases the jitter.

It is desirable to have a PLL that operates at higher frequencies with less jitter.

SUMMARY OF THE INVENTION

The present invention provides a phase lock loop that includes a dynamic phase frequency detector that includes dynamic logic, instead of static logic, to decrease the propagation delay through the detector.

The dynamic phase frequency detector increases the maximum operating frequency of the PLL with higher precision and less jitter at the PLL output clock. The dynamic phase frequency detector is simpler. The number of transistors and the layout area is reduced for an efficient implementation. As a result, the conventional static phase frequency detector is replaced by the dynamic phase frequency detector for high precision and low jitter operation of PLL.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

Referring toFIG. 1, there is shown a block diagram illustrating a phase lock loop (PLL) circuit100, which includes a phase frequency detector102, a charge pump104, a loop filter106, and a voltage controlled oscillator (VCO)108. A reference clock signal and a VCO clock signal from the VCO108are applied to respective input terminals of the phase frequency detector102. The phase frequency detector102compares the phase of the reference clock signal and the VCO clock signal and provides an up signal and a down signal to respective input terminals of the charge pump104. The up and down signals indicate respective positive and negative charge directions for the charge pump104to provide a voltage control signal to the VCO108for varying the frequency of the oscillation signal or VCO clock signal from the VCO108.

The phase frequency detector102generates the phase difference between the up and down signals to be substantially equal to the phase difference between the reference clock signal and the VCO clock signal. In particular, the phase difference of the reference clock signal and the VCO clock signal is copied and realized by the difference in the durations of the up and down signals. When the VCO clock signal is slower than the reference clock signal, the duration of the up signal is larger than the duration of the down signal to thereby increase the frequency of the VCO clock signal. When the VCO clock signal is faster than the reference clock signal, the duration of the down signal is larger than the duration of the up signal to thereby decrease the frequency of the VCO clock signal.

Referring toFIG. 2, there is shown a block diagram illustrating a conventional static phase shift detector200, which includes NAND gates202,204,206,208,210,212,214,216, and218, and inverters220and222. Schematic diagrams of two, three, and four input NAND gates are shown to illustrate the Field Effect Transistor (FET) implementation of such NAND gates. In such an implementation, the static phase shift detector200includes 44 transistors.

Referring toFIGS. 3a-3e, there are shown timing diagrams illustrating the operation of the conventional static phase frequency detector200when the VCO clock signal is slower than the reference clock signal. Referring now toFIGS. 3aand3e, there are shown the timing diagrams of the reference clock signal and the up signal, respectively. At a time t0, in response to a leading edge of the reference clock signal, the NAND gates202,216, and the inverter220generate the up signal. Referring now toFIGS. 3band3e, there are shown timing diagrams of the VCO clock signal and the down signal, respectively. At a time t1, in response to a leading edge of the VCO clock signal, the NAND gates212,218, and the inverter222generate the down signal. The difference between times t0and t1is the phase difference between the up and down signals. Referring now toFIG. 3c, there is shown a timing diagram of a set signal. In response to the reference clock, the NAND gate202resets the NAND gates204and206which are configured as a static RS flip-flop. In response to the VCO clock, the NAND gate218changes the state of the NAND gate212to thereby reset the NAND gates208and210which are configured as a static RS flip-flop. This causes the NAND gate214to provide a set B signal to the NAND gates216and218to reset these NAND gates and disable the up and down signals. This timing is repeated for each subsequent pulse of the reference clock and of the VCO clock.

Referring toFIGS. 4a-4e, there are shown timing diagrams of the reference clock signal, the VCO clock signal, the set signal, the up signal, and the down signal, respectively, when the VCO clock signal is faster than the reference clock signal. In contrast to the timing shown inFIGS. 3a-3e, the leading edge of the VCO clock signal occurs at time t0before the leading edge of the reference clock signal which occurs at time t1. Thus the down signal becomes active before the up signal. Here, upon the occurrence of the leading edge of the reference clock, the NAND gate214provides the set B signal to the NAND gates216and218to disable the up and down signals. This timing is repeated for each subsequent pulse of the reference clock and the VCO clock.

As shown inFIG. 3, when the VCO clock is slower than the reference clock, the duration of the up signal is larger than the duration of the down signal, and the difference of the durations is the phase difference.

Referring toFIG. 5, there is shown a schematic diagram illustrating the critical timing path of the static phase frequency detector200. The static phase frequency detector200is a state machine. Before moving to another state from the current state, all internal nodes of the static phase frequency detector200must be set to either a high state or a low state. Accordingly, the delay time for setting all internal nodes to either state determines the overall speed of the detector200. The critical path of the static phase frequency detector202determines the maximum delay time to set all nodes to either a high state or a low state.

The critical timing path of the static phase frequency detector200is the feedback path compressing the NAND gates212,210,208,214, and218. Because of the cross coupling between the NAND gates208and210, the critical path is a six gate delay. As a result, the6gate delay determines the overall speed of conventional static phase frequency detector200.

Referring toFIG. 6, there is shown a schematic diagram illustrating a dynamic phase frequency detector602in accordance with the present invention. The phase frequency detector602includes an up signal generator604, a down signal generator606, and a reset circuit607. The up signal generator provides an up signal to the charge pump104in response to a reference clock. Likewise, the down signal generator606provides a down signal to the charge pump104in response to a VCO clock signal from the voltage controlled oscillator108. The reset circuit607resets both the up signal generator604and the down signal generator606a predetermined time after the occurrence of the leading edges of both the reference clock and the VCO clock.

The up signal generator604includes p FETS608,610, and612, n FETS614,616, and618, and an inverter620. The drain-source junction of the p FET608couples the source of the p FET transistor610to an external power source (not shown). The drain-source junction of the n FET614couples the common node of the drain of the p FET transistor610and the signal line622to a ground line. A set signal from the reset circuit607is applied to the gates of the p FET608and the n FET614. The reference clock is applied to the gate of the p FET610. The drain-source junction of the p FET transistor612couples the common node of the source terminal of the n FET616and a signal line624to the external power source. The drain-source junction of the n FET618couples the drain terminal of the n FET616to the ground line. The reference clock is applied to the gate of the n FET616. The signal line622is applied to the common node of the gates of the p FET612and the n FET618. The inverter620provides the up signal in response to the signal on the signal line624.

The down signal generator606includes p FETS626,628, and630, n FETS632,634, and636and an inverter642. The drain-source junction of the p FET626couples the source of the p FET transistor628to an external power source (not shown). The drain-source junction of the n FET632couples the common node of the drain of the p FET transistor628and a signal line638to a ground line. A set signal from the reset circuit607is applied to the common node of the gates of the p FET626and the n FET632. The VCO clock is applied to the gate of the p FET628. The drain-source junction of the p FET transistor630couples the common node of the source terminal of the n FET634and a signal line640to the external power source. The drain-source junction of the n FET636couples the drain terminal of the n FET634to the ground line. The VCO clock is applied to the gate of the n FET634. The signal line638is applied to the gates of the p FET630and the n FET636. The inverter642provides the down signal in response to the signal on the signal line640.

As implemented, the dynamic phase frequency detector602uses dynamic logic which includes 16 transistors. In contrast, the static logic of the static phase frequency detector200includes 44 transistors. By using less transistors, the dynamic phase frequency detector602requires less implementation area than the static phase frequency detector200.

Referring toFIGS. 7a-7e, there are shown timing diagrams illustrating the operation of the dynamic phase frequency detector602, when the VCO clock signal is slower than the reference clock signal. Referring now toFIGS. 7aand7e, there are shown the timing diagrams of the reference clock signal and the up signal, respectively. At a time t0, in response to a leading edge of the reference clock signal, the up signal generator604generates the up signal. Referring now toFIGS. 7band7e, there are shown timing diagrams of the VCO clock signal and the down signal, respectively. At a time t1, in response to a leading edge of the VCO clock signal, the down signal generator606generates the down signal. Referring now toFIG. 7c, there is shown a timing diagram of a set signal. The signals on the signal lines624and640both provide low signals to the reset circuit607, which provides a set signal to both the up signal generator604and the down signal generator606. The set signal remains high until the set signal propagates through the generators604and606. The signal on the signal lines624and640goes high to thereby drive the up signal, the down signal, and the set signal low at a time t2. This timing is repeated for each subsequent pulse of the reference clock and the VCO clock.

Referring toFIGS. 8a-8e, there are shown timing diagrams of the reference clock signal, the VCO clock signal, the set signal, the up signal, and the down signal, respectively, when the VCO clock signal is faster than the reference clock signal. In contrast to the timing shown inFIGS. 7a-7e, the leading edge of the VCO clock signal occurs at time t0before the leading edge of the reference clock signal. Thus the down signal becomes active before the up signal. Here, upon the occurrence of the leading edge of the reference clock, both signals on the signal lines624and640each provide a low signal to the reset circuit607to thereby provide the set signal to the up and down signal generators604and606, respectively. After the set signal propagates through the generators604and606, the generators604and606turn off the up and down signals, respectively. This timing is repeated for each subsequent pulse of the reference clock and the VCO clock.

As shown in FIG.7andFIG. 8, the functionality of the dynamic phase frequency detector602is substantially identical to that of conventional static phase frequency detector200.

Referring toFIG. 9, there is shown a schematic diagram illustrating the critical timing path of the dynamic phase frequency detector602. The critical timing path of the dynamic phase frequency detector602is the feedback path comprising the reset circuit607, the p FET628, and the n FET634.

Assuming that each gate delay is identical, the operating frequency of the dynamic phase frequency detector602can be twice of that of conventional static phase frequency detector200because, as previously mentioned, the critical path of the conventional static phase frequency detector200is a six gate feedback path.

Referring toFIG. 10a, there is shown a graph illustrating the phase difference characteristics of an ideal phase frequency detector. Referring toFIG. 10b, there is shown the timing relation between the reference clock and the VCO clock of the ideal phase frequency detector.

As shown inFIG. 10a, an ideal phase frequency detector converts the phase difference between the reference clock signal and the VCO clock signal to the difference in the durations of the up and down signals, in an exact linear relationship to the phase difference over the entire range of the phase difference. In this case, the feed back loop of the phase lock loop operates linearly across the entire range of the phase difference. Consequently, the phase error of the reference clock signal and the VCO clock signal is reduced to zero by the ideal phase frequency detector and the overall feedback loop, as shown inFIG. 10b.

But a non-ideal phase frequency detector has a precision limit, caused by the limit of the operating frequency. If the operating frequency is higher than the operating frequency allowed by a phase frequency detector, the precision of the phase frequency detector is not predeterminable. This precision-limit results in the “dead zone” of the phase frequency detector, the smallest phase difference detectable by the phase frequency detector. Thus, a higher precision means a smaller dead zone.

Referring toFIG. 11a, there is shown a graph illustrating the characteristics of a non-ideal phase frequency detector. Referring toFIG. 11b, there is shown the timing relation between the reference clock signal and the VCO clock signal for the non-ideal phase frequency detector.

As shown inFIG. 11a, a non-ideal phase frequency detector has a “dead zone”. If the phase difference of the reference clock signal and the VCO clock signal is smaller than the “dead zone”, the non-ideal phase frequency detector cannot detect the phase difference. So, the difference of the duration of the up and down signals is zero, even if there is a phase difference smaller than the “dead zone”. As a result, the correct feed back operation of the PLL fails if the phase difference is smaller than the “dead zone”. In this case, there exists an unavoidable phase error between the reference clock signal and the VCO clock signal, which is the jitter caused by a low precision of the phase frequency detector. As shown inFIG. 11b, the “dead zone” of the phase frequency detector is copied to the unavoidable phase error of the reference clock signal and the VCO clock signal. The relation between the “dead zone” and the maximum phase errorMaximum⁢⁢Phase⁢⁢Error=2⁢π×TdeadzoneTperiod.(1)

By reducing the dead zone of the phase frequency detector, the PLL jitter (unavoidable phase error between the reference clock and the VCO clock) is reduced. In the low frequency operation, a conventional phase frequency detector can do work with a reasonable dead zone. But as the operating frequency is increased, the phase error between the reference clock and the VCO clock is increased because the “dead zone” of the phase frequency detector is fixed and the period of the reference clock is reduced. Because the conventional phase frequency detector can not guarantee the high precision nor a small “dead zone” in the higher frequency operation than allowed by its frequency limitation. The dynamic phase frequency detector of the present invention, increases the operating frequency to at least twice the operating frequency of a conventional phase frequency detector. The dynamic phase frequency detector may be used in the higher frequency applications because of the higher precision and smaller dead zone.