Semiconductor memory apparatus

A semiconductor memory apparatus of the technology includes a current sink circuit configured to allow a portion of a current flowing through a memory cell to flow to a negative voltage terminal in a read operation and a sense amplifier configured to detect data of the memory cell and a detection result in response to a sense amplifier enable signal in the read operation. The current sink circuit varies an amount of the current flowing to the negative voltage terminal in response to the sense amplifier enable signal.

CROSS-REFERENCES TO RELATED APPLICATION

The present application claims priority under 35 U.S.C. § 119(a) to Korean application number 10-2016-0140347, filed on Oct. 26, 2016, in the Korean Intellectual Property Office, which is incorporated herein by reference in its entirety.

BACKGROUND

1. Technical Field

Various embodiments may generally relate to a semiconductor integrated circuit, and more particularly, to a semiconductor memory apparatus.

2. Related Art

Semiconductor memory apparatuses may be configured to store data and output the stored data.

Semiconductor memory apparatuses have been developed to store data faster and output the stored data faster due to a high speed of the semiconductor memory apparatuses.

SUMMARY

In an embodiment of the present disclosure, a semiconductor memory apparatus may include: a current sink circuit configured to allow a portion of a current flowing through a memory cell to flow to a negative voltage terminal in a read operation; and a sense amplifier configured to detect data of the memory cell and output a detection result in response to a sense amplifier enable signal in the read operation. The current sink circuit may vary an amount of the current flowing to the negative voltage terminal in response to the sense amplifier enable signal.

In another embodiment of the present disclosure, a semiconductor memory apparatus may include: a read voltage generation circuit configured to generate a read voltage and output the generated read voltage in response to a read signal; a first switch configured to couple the read voltage generation circuit and a memory cell in response to the read signal so that the read voltage is transferred to the memory cell; a second switch configured to couple the memory cell and a detection node in response to the read signal so that a current flowing through the memory cell is transferred to the detection node; a current sink circuit configured to allow a portion of a current flowing in the current sink circuit from the detection node to is flow to a negative voltage terminal and vary an amount of a current flowing from the current sink circuit to the negative voltage terminal in response to a sense amplifier enable signal; and a sense amplifier configured to detect a voltage level of the detection node and output a detection result in response to the sense amplifier enable signal.

DETAILED DESCRIPTION

Various embodiments of the present disclosure will be described in greater detail with reference to the accompanying drawings. The drawings are schematic illustrations of various embodiments (and intermediate structures). As such, variations from the configurations and shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, the described embodiments should not be construed as being limited to the particular configurations and shapes illustrated herein but may include deviations in configurations and shapes which do not depart from the spirit and scope of the present disclosure as defined in the appended claims.

The present disclosure is described herein with reference to cross-section and/or plan illustrations of idealized embodiments of the present disclosure. However, embodiments of the present disclosure should not be construed as limiting the inventive concept. Although a few embodiments of the present disclosure will be shown and described, it will be appreciated by those of ordinary skill in the art that changes may be made in these embodiments without departing from the principles and spirit of the present disclosure.

As illustrated inFIG. 1, a semiconductor memory apparatus according to an embodiment may include a read voltage generation circuit100, first and second switches210and220, a memory cell300, a current sink circuit400, and a sense amplifier500.

The read voltage generation circuit100may generate a read voltage V_rd and output the generated read voltage V_rd in a read operation.

The first switch210may turn on in the read operation and transfer the read voltage V_rd to the memory cell300. For example, the first switch210may allow the read voltage V_rd to be transferred to the memory cell300or may prevent the read voltage V_rd from being transferred to the memory cell300, in response to a read signal Read. In this example, the first switch210may turn on and transfer the read voltage V_rd to the memory cell300when the read signal Read is enabled. The first switch210may turn off and prevent the read voltage V_rd from being transferred to the memory cell300when the read signal Read is disabled. The first switch210may couple and separate the read voltage generation circuit100and the memory cell300in response to the read signal Read. The first switch210may couple the read voltage generation circuit100to the memory cell300when the read signal Read is enabled and may separate the read voltage generation circuit100from the memory cell300when the read signal Read is disabled.

The memory cell300may be a unit circuit of the semiconductor memory apparatus which stores data. A resistance level of the memory cell300may be changed according to a data value of data stored therein.

The second switch220may turn on in the read operation and transfer a current flowing from the memory cell300to the current sink circuit400. For example, the second switch220may transfer the current flowing from the memory cell300to the current sink circuit400in response to the read signal Read. In this example, the second switch220may turn on and transfer the current flowing from the memory cell300to the current sink circuit400when the is read signal Read is enabled. The second switch220may turn off and prevent the current flowing from the memory cell300from being transferred to the current sink circuit400when the read signal Read is disabled. The second switch220may couple and separate the memory cell300and the current sink circuit400in response to the read signal Read. The second switch210may couple the current sink circuit400to the memory cell300when the read signal Read is enabled and may separate the current sink circuit400from the memory cell300when the read signal Read is disabled. A node in which the second switch220and the current sink circuit400are coupled may be referred to as a detection node Node_det. Further, a current flowing through the memory cell300may be transferred to the detection node Node_det.

The current sink circuit400may allow a fixed amount of current of the current flowing from the second switch220to flow to a negative voltage terminal VBB and may vary an amount of the current flowing to the negative voltage terminal VBB in response to a bias voltage V_bias and a sense amplifier enable signal SA_en.

The current sink circuit400may include a fixed sink circuit410and a variable sink circuit420.

The fixed sink circuit410may allow a first fixed amount of current of the current flowing in the current sink circuit400from the second switch220, for example the detection node Node_det, to flow to the negative voltage terminal VBB in response to a voltage level of the bias voltage V_bias.

The fixed sink circuit410may include a first transistor N1. A gate of the first transistor N1may receive the bias voltage V_bias, the detection node Node_det may be coupled to a drain of the first transistor N1, and the negative voltage terminal VBB may be coupled to a source of the first transistor N1.

The variable sink circuit420may allow a second fixed amount of current of the current flowing in the current sink circuit400from the second switch220, for example the detection node Node_det, to flow to the negative voltage terminal VBB or may interrupt the second fixed amount of current flowing to the negative voltage terminal VBB, in response to the sense amplifier enable signal SA_en. For example, the variable sink circuit420may interrupt the second fixed amount of current flowing from the detection node Node_det to the negative voltage terminal VBB when the sense amplifier enable signal SA_en is enabled. The variable sink circuit420may allow the second fixed amount of current to flow from the detection node Node_det to the negative voltage terminal VBB when the sense amplifier enable signal SA_en is disabled.

The variable sink circuit420may include a second transistor N2and an inverter IV1. The inverter IV1may receive the sense amplifier enable signal SA_en. A gate of the second transistor N2may receive an output signal of the inverter IV1, the detection node Node_det may be coupled to a drain of the second transistor N2, and the negative voltage terminal VBB may be coupled to a source of the second transistor N2. Further, the current sink circuit400, the sense amplifier500, and the memory cell300may be commonly coupled to the detection node Node_det in the read operation.

The current sink circuit400may be configured in such a manner that both the fixed sink circuit410and the variable sink circuit420may allow a fixed amount of current to flow to the negative voltage terminal VBB when the sense amplifier enable signal SA_en is disabled, and only the fixed sink circuit410may allow a fixed amount of current to flow to the negative voltage terminal VBB when the sense amplifier enable signal SA_en is enabled. Accordingly, the current sink circuit400may be configured to allow a smaller amount of current to flow to the negative voltage terminal VBB when the sense amplifier enable signal SA_en is enabled than when the sense amplifier enable signal SA_en is disabled.

The sense amplifier500may detect the voltage level of the detection node Node_det and output the detection result as an output signal SA_out in response to the sense amplifier enable signal SA_en. For example, the sense amplifier500may be activated when the sense amplifier enable signal SA_en is enabled, detect the voltage level of the detection node Node_det, and output the detection result as the output signal SA_out. The activated sense amplifier500may determine a level of the output signal SA_out according to whether the voltage level of the detection node Node_det is larger or smaller than a target level. The sense amplifier500may be inactivated when the sense amplifier enable signal SA_en is disabled.

An operation of the semiconductor memory apparatus having the above-described configuration according to an embodiment will be described.

In the read operation, the read signal Read may be enabled.

In the read operation, the read voltage generation circuit100may generate the read voltage V_rd and output the generated read voltage V_rd in response to the read signal Read.

When the read signal Read is enabled, the first switch210may transfer the read voltage V_rd to the memory cell300.

A resistance level of the memory cell300may be varied according to a level of data stored therein.

When the read signal Read is enabled, the second switch220may transfer the current flowing from the memory cell300to the current sink circuit400.

The current sink circuit400may allow a portion of the current flowing from the second switch220, for example the current flowing from the memory cell300, to flow to the negative voltage terminal VBB, and the current sink circuit400may vary an amount of current flowing to the negative voltage terminal VBB of the current flowing from the memory cell300in response to the sense amplifier enable signal SA_en. The current sink circuit400may receive the current flowing through the memory cell300and may allow a smaller is amount of current to flow to the negative voltage terminal VBB when the sense amplifier enable signal SA_en is enabled than when the sense amplifier enable signal SA_en is disabled.

When the sense amplifier enable signal SA_en is enabled, the sense amplifier500may detect the voltage level of the detection node Node_det in which the second switch220and the current sink circuit400are coupled and output the detection result as the output signal SA_out in response to the sense amplifier enable signal SA_en in the read operation.

For example, in the read operation, that is, when the read signal Read is enabled, the first and second switches210and220may turn on, the read voltage V_rd may be applied to the memory cell300, and the current sink circuit400may allow a portion of the current flowing through the memory cell300to flow to the negative voltage terminal VBB through the current sink circuit400. When the sense amplifier enable signal SA_en is disabled, for example, when the sense amplifier500does not detect the voltage level of the detection node Node_det, both the fixed sink circuit410and the variable sink circuit420of the current sink circuit400may allow the fixed amount of current of the current flowing from the memory cell300to flow to the negative voltage terminal VBB and thus the voltage level of the detection node Node_det may be maintained to the target level or less. Accordingly, the sense amplifier500may quickly detect the resistance level of the memory cell300in the read operation. Subsequently, when the sense amplifier enable signal SA_en is enabled, the variable sink circuit420of the current sink circuit400may stop the flow of the fixed amount of current and only the fixed sink circuit410may allow a portion of the current flowing through the memory cell300to flow to the negative voltage terminal VBB. Accordingly, the current sink circuit400may allow a smaller amount of current to flow to the negative voltage terminal VBB when the sense amplifier enable signal SA_en is enabled than when the sense amplifier enable signal SA_en is disabled. For example, because a smaller amount of current flows from the current sink circuit400to the negative voltage terminal VBB when the sense amplifier enable signal SA_en is enabled than when the sense amplifier enable signal SA_en is disabled, the voltage level of the detection node Node_det may be raised to the target level according to a resistance level of the memory cell300faster than the related art. Because the voltage level of the detection node Node_det is raised to the target level or quicker than the related art, the sense amplifier500may determine the voltage level of the output signal SA_out quicker than the related art.

The semiconductor memory apparatus according to an embodiment may raise the voltage level of the detection node faster than the related art by varying the amount of current flowing from the detection node to the negative voltage terminal when the sense amplifier enable signal is enabled with respect to the amount of current flowing when the sense amplifier enable signal is disabled. Accordingly, data detection speed of the memory cell may be improved.

The above described embodiments of the present disclosure are intended to illustrate and not to limit the present disclosure. Various alternatives and equivalents are possible. The disclosure is not limited by the embodiments described herein. Nor is the disclosure limited to any specific type of semiconductor device. Other additions, subtractions, or modifications are obvious in view of the present disclosure and are intended to fall within the scope of the appended claims.

The semiconductor memory apparatus discussed above (seeFIG. 1) is particularly useful in the design of memory devices, processors, and computer systems. For example, referring toFIG. 2, a block diagram of a system employing a semiconductor memory apparatus in accordance with the various embodiments are illustrated and generally designated by a reference numeral1000. The system1000may include one or more processors (i.e., Processor) or, for example but not limited to, central processing units (“CPUs”)1100. The processor (i.e., CPU)1100may be used individually or in combination with other processors (i.e., CPUs). While the processor (i.e., CPU)1100will be referred to primarily in the singular, it will be understood by those skilled in the art that a system1000with any number of physical or logical processors (i.e., CPUs) may be implemented.

A chipset1150may be operably coupled to the processor (i.e., CPU)1100. The chipset1150is a communication pathway for signals between the processor (i.e., CPU)1100and other components of the system1000. Other components of the system1000may include a memory controller1200, an input/output (“I/O”) bus1250, and a disk driver controller1300. Depending on the configuration of the system1000, any one of a number of different signals may be transmitted through the chipset1150, and those skilled in the art will appreciate that the routing of the signals throughout the system1000can be readily adjusted without changing the underlying nature of the system1000.

As stated above, the memory controller1200may be operably coupled to the chipset1150. The memory controller1200may include at least one semiconductor memory apparatus as discussed above with reference toFIG. 1. Thus, the memory controller1200can receive a request provided from the processor (i.e., CPU)1100, through the chipset1150. In alternate embodiments, the memory controller1200may be integrated into the1ochipset1150. The memory controller1200may be operably coupled to one or more memory devices1350. In an embodiment, the memory devices1350may include the at least one semiconductor memory apparatus as discussed above with relation toFIG. 1, the memory devices1350may include a plurality of word lines and a is plurality of bit lines for defining a plurality of memory cells. The memory devices1350may be any one of a number of industry standard memory types, including but not limited to, single inline memory modules (“SIMMs”) and dual inline memory modules (“DIMMs”). Further, the memory devices1350may facilitate the safe removal of the external data storage devices by storing both instructions and data.

The disk driver controller1300may be operably coupled to the chipset1150. The disk driver controller1300may serve as the communication pathway between the chipset1150and one internal disk driver1450or more than one internal disk driver1450. The internal disk driver1450may facilitate disconnection of the external data storage devices by storing both instructions and data. The disk driver controller1300and the internal disk driver1450may communicate with each other or with the chipset1150using virtually is any type of communication protocol, including, for example but not limited to, all of those mentioned above with regard to the I/O bus1250.

It is important to note that the system1000described above in relation toFIG. 2is merely one example of a system1000employing a semiconductor apparatus as discussed above with relation toFIG. 1. In alternate embodiments, such as, for example but not limited to, cellular phones or digital cameras, the components may differ from the embodiments illustrated inFIG. 2.