Method and apparatus for high performance class D audio amplifiers

The present disclosure provides a method and apparatus for high performance class D audio amplifier circuit that includes: a modulator circuit for receiving a PWM input signal and generating a control signal, a driver control circuit, a switching circuit, and a feedback circuit. The driver control circuit is adapted to generate a drive signal for the switching circuit. The driving signal provides compensation for noise and distortions in a PWM output signal at each cycle by selecting either a first pulse signal or a second pulse signal based on the information of the control signal.

TECHNICAL FIELD

The present disclosure relates generally to the field of analog integrated circuits, and more specifically, the present disclosure relates to class-D power amplifiers.

BACKGROUND

In recent years, the use of class D amplifiers has become widespread in audio applications. Class D amplifiers are highly efficient and compact, which leads to the reduced cooling requirements and power supply. The operating principle of these class-D power amplifiers is to convert analog or digital audio signals to high frequency pulse width modulation (PWM) signals, and then use the generated PWM signals to drive power MOSFETs in either half-bridge or full-bridge topologies. Passive low pass filters are finally used to convert the output signal of the power MOSFETs into a low frequency analog waveform suitable for audio speakers.

The above approach to implement a class-D amplifier is relatively straightforward. However, to produce high-quality audio signals, there are still a number of issues associated with these amplifiers worth addressing. One major issue is the degradation of the output analog signal by power supply noise and the non-ideal output stage.

For half-bridge topologies, there is no common-mode rejection since they are single-ended by nature, and any noise on the amplifier's power supply will be directly coupled to the output. This undesirable effect becomes even worse for digital class-D amplifiers, in which the power MOSFETs are switched between the supply and the output, and essentially the supply is used as a voltage reference. Hence, without additional noise cancellation structures, the power supply rejection ratio (PSRR) performance of half-bridge class-D amplifiers is unacceptable. Unlike half-bridge topologies, full-bridge class-D amplifiers have sufficient common mode rejection capability to remove the power supply noise effect on the output since the resulting differential output is powered from the same supply. However, they still suffer from the transient behavior of the power supply, which can result from the changes of DC supply level due to load variations. Furthermore, non-ideal power MOSFETs and mismatches in switching circuitry will also degrade the PSRR performance of the full-bridge topologies.

Another approach often used to suppress the noise in a class D audio amplifier is a sigma delta modulator configuration. A sigma delta modulator shapes the noise in high frequency and then uses low pass filters to output only audio analog signals. Referring toFIG. 1, a schematic diagram of a prior-art class D amplifier100that illustrates the use of a sigma-delta modulator configuration to improve its noise performance is illustrated. Prior art class D amplifier100receives an analog input signal (VIN) at an input terminal101. The sigma delta modulator includes a summing circuit102, an integrator103connected to a comparator104, and a latch105converting the difference between a feedback output signal and the analog input signal (VIN) into a bit stream that carries quantized noise spikes imposed on the original analog input signal (VIN). A switching circuit107including a high-side MOSFET transistor107_1and a low-side MOSFET transistor107_2operating in push-pull mode is then used to pulse modulate the bit stream. In order to regain the original PWM input signal (VIN), a simple LC low pass filter109is used to filter out the noise spikes shaped at high frequency. However, the technique has drawbacks for PWM inputs, since the output frequency is not directly controlled and is subject to component variations. Further, distortions caused by non-idealities of the power MOSFET transistors107_1and107_2and integrator103are left uncorrected by prior art class D audio amplifier100. The time constant of integrator103may affect the switching rate of switching circuit107. Moreover, the inductor current at the output of switching circuit107often inadvertently stretches or shortens the pulse widths of the drive signal.

SUMMARY

The present disclosure provides a high performance class D audio amplifier circuit that can handle both noise and distortion. A class D amplifier of the present disclosure includes: a modulator circuit for receiving a PWM input signal and generating a control signal, a driver control circuit, a switching circuit, and a feedback circuit. The driver control circuit is adapted to generate a drive signal for the switching circuit. The drive signal includes compensation for noise and distortion in an output signal at each cycle by selecting either a first pulse signal or a second pulse signal based on the information of the control signal.

A method of providing low signal distortion in a class D audio amplifier is also disclosed that includes: providing a feedback output signal, quantizing the difference signal between the feedback output signal and an input signal to obtain a control signal; and compensating for the output signal at the end of each cycle by modulating the duty cycle of the output signal based on the control signal.

DETAILED DESCRIPTION

Turning toFIG. 2, a block diagram showing a structure of a class D audio amplifier200in accordance with an embodiment of the present disclosure is illustrated. Class D audio amplifier200receives and converts a Pulse Width Modulation input signal (PWMIN) into a PWM input current signal using a first resistor202. An output PWM signal (PWMOUT) is also converted into an PWM output current signal using a second resistor210. The PWM output current signal is fedback toward input terminal201by means of a feedback circuit209. A subtractor203subtracts the PWM input current signal from the PWM output current signal. The resulting difference signal (PWMΔ) which includes both noise spikes and PWM input signal is introduced into an integrator204so that the average value (PWMa) of the difference signal can be estimated. Subsequently, the average value of the difference signal (PWMa) is quantized by a comparator205to obtain a control signal (PWMq). Those skilled in the art should realize that205herein could be a multi-level circuit, and it is not limited to a comparator. The comparator205compares the average difference signal (PWMa) with a first voltage level VREF+and a second voltage level VREF−. Only those noise spikes that surpass these two reference values would be quantized into either a logic HIGH signal or a logic LOW signal. In other words, unwanted noise spikes are shaped into high frequency. A driver control circuit206receives the control signal (PWMq) and modulates the pulse width of each pulse based on the information contained in the PWM input current signal so as to compensate for the distortions caused by non-idealities of a subsequent switching circuit207. In one embodiment, driver control circuit206selects either a longer pulse signal or a shorter pulse signal whose pulse widths are determined by pulse stretching distortions caused by elements of switching circuit207. The PWM output signal (PWMOUT) is input into a low pass filter211where noise is filtered out and only the desired audio signal (VOUT) is retained. In addition, in accordance with an embodiment of the present disclosure, any distortion in the pulse width PWM output signal (PWMOUT) is also corrected by driver control circuit206. Finally, the output of low pass filter211is connected to an audio speaker212. Those skilled in the art  could realize that for an inductive load, i.e. an inductive speaker, the LPF211is not required.

Referring toFIG. 3, a block diagram of an embodiment of class D audio amplifier300that includes a structure of a driver control circuit in accordance with the present disclosure is illustrated. Class D audio amplifier300includes a PWM input terminal301that receives a PWM input signal (PWMIN). Next, a level shifter circuit302is connected to the PWM input terminal301to bring the PWM input signal to the signal level of power MOSFET transistors of a switching circuit320. Then a modulator circuit303is connected to receive the output of level shifter circuit302and the PWM output signal (PWMOUT). In one embodiment, the output of level shifter circuit302and PWM output signal (PWMOUT) are first converted to current signals prior to determining the difference between them. The output of modulator circuit303is input to driver control circuit310. The output of driver control circuit310, in turn, drives switching circuit320.

Still referring toFIG. 3, in one embodiment, driver control circuit310includes a delay circuit311, a first pulse-width modulation circuit312, a second pulse-width modulation circuit313, a multiplexer314, a latch316, and an inverter315. Delay circuit311receives a PWM input signal (PWMIN) to generate a delayed signal (PWMdly). Next, the delayed signal (PWMdly) is coupled to first pulse-width modulation circuit312and second pulse-width modulation circuit313respectively. An output (PWML) of first pulse-width modulation circuit312and an output (PWMS) of second pulse-width modulation circuit313are coupled to multiplexer314. Latch316is coupled to receive control signal (PWMq) from modulator circuit303at an input terminal of latch316. The clock terminal of latch316is connected to the output of inverter315whose input terminal is connected to the output (PWMdly) of delay circuit311. The operation of class D audio amplifier300with driver control circuit310will be described in detail below with reference toFIG. 5andFIG. 6.

Turning toFIG. 4, a schematic diagram of a driver control circuit400in accordance with an embodiment of the present disclosure is illustrated. Structurally, driver control circuit400includes a delay circuit402connected to an input terminal401adapted to receive a Pulse Width Modulation input signal (PWMIN). The output of delay circuit402is connected to a NAND gate403and a NOR gate404. In this embodiment, NAND gate403is an example of first pulse-width modulation circuit312while NOR gate404is an example of second pulse-width modulation circuit313inFIG. 3. The other input terminals of both NAND gate403and NOR gate404are connected to input terminal401. The output terminal of NOR gate404is input to a multiplexer405. An output terminal409outputs either an output signal (PWMS) of NAND gate403or an output signal of NOR gate404(PWML) depending on a command of a latch407connected to an inverter408. In one embodiment, latch407is a clocked D flip flop.

The D input terminal of clocked D flip flop407is connected to receive a control signal (PWMq) from modulator circuit303at terminal406. The Q output terminal of clocked D flip flop407is connected to the input terminal of inverter408and to a second selecting terminal of multiplexer405. The output terminal of inverter408is connected to a first selecting terminal of multiplexer405. In one embodiment, as shown inFIG. 4, multiplexer405includes a first inverter405_1and a second inverter405_2.

Referring now toFIG. 5, signal graphs500(also referred to as signal timing diagrams) of PWM signals of driver control circuit400in accordance with an embodiment of the present disclosure is shown. A representative PWM input signal (PWMIN) received at input terminal401is illustrated by graph501. As shown, PWM input signal (PWMIN)501is a Pulse Width Modulation signal with varying pulse widths. A graph502that represents an output of delay circuit402(PWMdly) is shown. The delayed signal (PWMdly)502is PWM input signal (PWMIN) delayed by a delay amount δ. In one embodiment, delay value δ is carefully chosen to be larger than the equivalent pulse width of the maximum difference between the desirable PWM output signal (PWMOUT) and the distorted PWM output signal. Otherwise, feedback loop209cannot correct the distorted PWM output signal (PWMOUT) in the worst case scenario. Next, a graph504that represents the output signal (PWMS) of NAND gate403is shown. As shown inFIG. 4, NAND gate403receives PWM input signal (PWMIN) at its first input terminal and the delayed PWM input signal (PWMdly) at its second input terminal. The output signal (PWMS) only goes HIGH when either input signal goes LOW. On the other hand, graph503representative of an output signal (PWML) of the output of NOR gate404is shown. Naturally, the output signal (PWML) signal only goes HIGH when both input signals to NOR gate404go LOW. Finally, the drive signal (PWMDR) of multiplexer405is illustrated by a graph505. In one embodiment, clocked D flip flop407is clocked by the output signal (PWMS) of NAND gate403. Every time the output signal (PWMS) goes LOW, clocked D flip flop407latches out either a shorted PWM signal (PWMS) or a stretched PWM signal (PWML).

Referring back toFIG. 2,FIG. 4, andFIG. 5, it can be seen that PWM input signal (PWMIN) which is the desirable signal from input terminal201, and the delayed version (PWMdly) enter NAND gate403and NOR gate404respectively. The resulting output will be a PWM signal with shorter pulse width (PWMS) at the output of NAND gate403and/or a PWM signal with longer pulse width (PWML) at the output of NOR gate404. Each cycle, one of these two PWM signals (PWMLand PWMS) is selected to be applied to the gates of MOSFET transistors207_1and207_2, which is determined by the control signal from the output of comparator205. For instance, at the end of one cycle, the output of comparator205turns to be high, which means the average voltage value of the distorted PWM output signal (PWMOUT) is smaller than that of the desirable input PWM signal (PWMIN). Thus, this is an unwanted shortening in pulse width of PWM output signal (PWMOUT). To correct this distorted PWM output signal (PWMOUT), an PWM with longer pulse width (PWML) than the desirable input PWM input signal (PWMIN) is required to be applied to the gates of MOSFET transistors207_1and207_2; thus this “high” control signal selects the signal (PWML) at the output of the NOR gate404through a clocked D flip-flop407, so that in the next cycle a PWM signal with longer pulse width than that of the PWM input signal (PWMIN) is applied to the gates of MOSFET transistors207_1and207_2.

On the other hand, if the control signal turns to be low, which means the average voltage value of the distorted PWM output signal (PWMOUT) is larger than that of the desirable input PWM input signal (PWMIN). So, this is a case of unwanted stretch in the pulse width of the PWM output signal (PWMOUT). Therefore, a PWM signal with a narrower pulse width (PWMS) at the output of NAND gate403is selected to compensate the difference between the desirable PWM input signal (PWMIN) and the distorted PWM output signal (PWMOUT).

Now referring toFIG. 6, a series of graphs600illustrating the operation of class D audio amplifier400ofFIG. 4is shown. Again, a graph601of the input PWM input signal (PWMIN) at terminal301is shown. Next, a graph602represents the drive signal (PWMDR) at the output of multiplexer314is shown. As shown in graph602, the falling edge of each pulse is either stretched or shortened. More particularly, a first pulse602_V is stretched out and a second pulse602_W is shortened at their respective falling edge. Similarly, a third pulse602_X is shorted while a fourth pulse602_Y is stretched out at their relative falling edge. Some of the causes of the delays could be finite rise, nonlinear rise time due to power devices of switching circuit320, and/or linear or nonlinear delays through the system. Nonlinear rise time errors may cause by the turn-on time of power devices inside switching circuit320, and/or body diode recovery time, etc.

Continuing withFIG. 6, each pulse at the input of switching circuit320creates a corresponding pulse at its output terminal which is represented by a graph603. At a pulse603_V, there is a small negative error at the rising edge. Obviously, the PWM output signal (PWMOUT) can not change until drive signal (PWMDR) changes, so there is a delay. These unwanted delays will cause high-side power MOSFET transistor207_1and low-side MOSFET transistor207_2to be turned ON or turned OFF slowly. Consequently, instantaneous inductor current (IL) in low pass filter211will cause distortions in the pulse width of drive signal (PWMDR). An inductor current (IL) that flows toward input terminal201will cause unwanted stretch in the pulse width of PWM output signal (PWMOUT). Otherwise, an inductor current (IL) that flows out toward output filter211will cause unwanted shortening in the pulse width of PWM output signal (PWMOUT). Thus, a graph604shows the difference signal (PWMΔ) that contains the signal distortions of PWM output signal (PWMOUT). A graph605representing the average difference signal after integrator204is also illustrated. Finally, a graph606illustrates the audio output signal (VOUT) received at the output of low pass filter211. Graph606is achieved after noise spikes have been filtered out by low pass filter211and pulse width distortions are compensated by driver control circuit206.

Referring next toFIG. 7, a flow chart that illustrates a method800of providing a low distortion signal in a class D audio amplifier is illustrated. Method700includes providing a feedback output signal, quantizing the difference signal between the feedback output signal and an input signal to obtain a control signal; and compensating for the output signal at the end of each cycle by modulating the duty cycle of the output signal based on the control signal.

More particularly, at step701, a feedback output signal is provided. In one embodiment, step701further includes converting a Pulse Width Modulation input signal (PWMIN) into an input current signal and converting an output of a switching circuit (PWMOUT) into an output second current signal. Then, the output second current signal is fedback to be subtracted from the input current signal. Step701is implemented by a feedback path209, a first resistor202, and a subtractor203.

Next, at step702, the difference between the feedback output signal and the input signal is quantized to obtain a control signal. Step702is implemented by integrator204connected between subtractor203and comparator205as shown inFIG. 2. The control signal selects whether a longer pulse signal or a shorter pulse signal is selected to drive switching circuit207.

Finally, referring to step703, at each cycle, the pulse width of the driving signal that drives the switching circuit is modulated using the control signal. In particularly, the control signal selects a longer pulse when the PWM output signal is shortened. On the other hand, the control signal selects a shorter pulse when the PWM output signal is stretched by power MOSFET transistors207_1and207_2. Step703is implemented by driver control circuit310and class D audio amplifier300. In one embodiment, step703is implemented by driver control circuit400inFIG. 4of the present disclosure.

Modifications and variations of the present disclosure are possible in light of the above teachings. It is therefore to be understood that within the scope of the appended claims the invention may be practiced otherwise than as specifically described. It should be understood, of course, the foregoing disclosure relates only to a specific embodiment (or embodiments) of the invention and that numerous modifications may be made therein without departing from the spirit and the scope of the invention as set forth in the appended claims. Various modifications are contemplated and they may be resorted to by those skilled in the art without departing from the spirit and the scope of the invention as hereinafter defined by the appended claims as only a specific embodiment(s) thereof has been disclosed.