INTEGRATED CIRCUIT FOR POWER CLAMPING

An integrated circuit for power clamping is provided. The integrated circuit for power clamping is electrically coupled to an internal circuit of an integrated circuit through a power line and a ground line, and includes a switch, a first resistor, a capacitor, an inverter and a voltage detection circuit. The voltage detection circuit detects a voltage of the power line, and when the voltage of the power line exceeds a threshold value, the voltage detection circuit electrically connects a first node to the ground line, such that a low potential signal from the ground line is input to the input terminal of the inverter, and then the switch is turned on to form a discharge path.

CROSS-REFERENCE TO RELATED PATENT APPLICATION

This application claims the benefit of priority to Taiwan Patent Application No. 111116888, filed on May 5, 2022. The entire content of the above identified application is incorporated herein by reference.

FIELD OF THE DISCLOSURE

The present disclosure relates to an integrated circuit (IC), and more particularly to an integrated circuit for power clamping capable of forming a discharge path for an electrical overstress (EOS) event.

BACKGROUND OF THE DISCLOSURE

An integrated circuit (IC) may be provided with a power clamping circuit to form a discharge path for electrostatic discharge (ESD), so as to prevent an ESD surge current from flowing into an internal circuit of the IC and protect the IC from burning out. However, an electrical overstress (EOS) event (also referred to as a system ESD) may occur during normal operation of the IC, and the EOS events typically last in an order of microseconds compared to ESD events, which typically last in an order of nanoseconds. Therefore, it is difficult for the existing integrated circuit for power clamping to form a discharge path for the EOS event to prevent the EOS surge current from flowing into the internal circuit of the IC and burning the IC out.

SUMMARY OF THE DISCLOSURE

In response to the above-referenced technical inadequacies, the present disclosure provides an integrated circuit for power clamping that can form a discharge path for an electrical overstress (EOS) event, so as to prevent an EOS surge current from flowing into an internal circuit of an IC and protecting the IC from burning out.

In one aspect, the present disclosure provides an integrated circuit for power clamping. The integrated circuit for power clamping is electrically coupled to an internal circuit of another integrated circuit through a power line and a ground line, and the integrated circuit for power clamping includes a switch, a first resistor, a capacitor, an inverter and a voltage detection circuit. The switch is electrically coupled between the power line and the ground line. The first resistor is electrically coupled between the power line and the first node. The capacitor is electrically coupled between the first node and the ground line. The inverter is electrically coupled between the first node and the control terminal of the switch. An input terminal of the inverter is electrically coupled to the first node, and an output terminal of the inverter is electrically coupled to the control terminal of the switch. The voltage detection circuit is electrically coupled to the power line, the first node and the ground line, and is configured to detect a voltage of the power line. In response to detecting that the voltage of the power line exceeds a threshold value, the voltage detection circuit is further configured to electrically connect the first node to the ground line, such that the input terminal of the inverter electrically coupled with the first node is pulled low to activate the switch and forming a discharge path in the switch.

DETAILED DESCRIPTION OF THE EXEMPLARY EMBODIMENTS

Reference is made toFIG.1, which is a schematic diagram of an integrated circuit for power clamping according to one embodiment of the present disclosure. The integrated circuit for power clamping1is electrically coupled to an internal circuit20of another integrated circuit (IC) through a power line PL and a ground line GL. The ground line GL is electrically coupled to the ground voltage GND, and the integrated circuit for power clamping1includes a switch10, a resistor R1, a capacitor C, an inverter14and a voltage detection circuit16. The switch10is electrically coupled between the power line PL and the ground line GL. The resistor R1is electrically coupled between the power line PL and a first node N1. The capacitor C is electrically coupled between the first node N1and the ground line GL. The inverter14is electrically coupled between the first node N1and a control terminal of the switch10. The input terminal of the inverter14is electrically coupled to the first node N1, and the output terminal of the inverter14is electrically coupled to the control terminal of the switch10. The voltage detection circuit16is electrically coupled to the power line PL, the first node N1and the ground line GL, and is configured to detect whether a voltage of the power line PL exceeds a threshold. When the voltage of the power line PL exceeds the threshold value, the voltage detection circuit16further electrically couples the first node N1with the ground line GL, such that the input terminal of the inverter14electrically coupled with the first node N1is pulled low to activate the switch10and forming a discharge path in the switch10.

Specifically, the switch10can be an N-channel metal-oxide-semiconductor field-effect transistor (N-MOSFET) Mn1, a drain of the N-MOSFET Mn1is electrically coupled to the power line PL, and a source of the N-MOSFET Mn1is electrically coupled to the ground line GL, and a gate of the N-MOSFET Mn1is taken as the control terminal electrically coupled to the output terminal of the inverter14. In other embodiments, the switch10can also be an NPN bipolar junction transistor (BJT), a collector of the NPN-BJT is electrically coupled to the power line PL, an emitter of the NPN-BJT is electrically coupled to the ground line GL, and a base of the NPN-BJT is taken as the control terminal electrically coupled to the output terminal of the inverter14, but the present disclosure is not limited thereto. The present disclosure does not limit a specific implementation of the switch10, but for the convenience of the following description, only the N-MOSFET Mn1is used as the switch10provided by the present disclosure as an example. The N-MOSFET Mn1is turned on in response to the gate receiving a high potential signal output from the inverter14and is turned off in response to the gate receiving a low potential signal output from the inverter14.

In addition, the inverter14outputs a low-level signal in response to a high-level signal being input from the first node N1to the input terminal of the inverter14, and the inverter14further outputs a high-level signal in response to a low-level signal being input from the first node N1to the input terminal of the inverter14. The resistor R1and the capacitor C are connected in series between the power line PL and the ground line GL to form an RC circuit, and the RC circuit is also connected in parallel with the N-MOSFET Mn1. In other embodiments, the resistor R1can also be replaced by a P-MOSFET or an N-MOSFET, and the capacitor C can also be replaced by a diode, but the present disclosure is not limited thereto. It should be noted that, in response to a power supply voltage VDD being applied to the power supply line PL to be supplied to the internal circuit20of the IC during normal operation, the integrated circuit for power clamping1enables a high potential signal from the power supply line PL to be input from the first node N1to the input terminal of the inverter14, such that the N-MOSFET Mn1is turned off.

However, in a case where the integrated circuit for power clamping1is provided without the voltage detection circuit16, after an EOS surge is applied to the power line PL (i.e., an EOS event occurs), the RC circuit charges the capacitor C according to an RC time constant of the resistor R1and the capacitor C. Since the EOS event is usually last in an order of microseconds, and the RC time constant of the resistor R1and the capacitor C is also usually set to enable a time required for the capacitor C to be fully charged to be in the order of microseconds, there is a chance that the capacitor C may be fully charged when the EOS event occurs, so that the first node N1may be in a high potential state to generate a high potential signal to input to the input terminal of the inverter14, while the N-MOSFET Mn1is turned off such that no discharge path can be formed. Therefore, the EOS surge current at this time flows into the internal circuit20of the IC.

On the other hand, when the voltage of the power line PL rises to a breakdown voltage of the N-MOSFET Mn1, the integrated circuit for power clamping1can only form a discharge path through the drain and a base of the N-MOSFET Mn1. However, in the N-MOSFET Mn1, a path from the drain to the base is usually non-uniformly turned on, thereby limiting its discharge capability, so that it can be difficult to prevent the EOS surge current from flowing into the internal circuit20of the IC. In order to address the above issues, the integrated circuit for power clamping1provided by the present disclosure can electrically connect the first node N1to the ground line GL through the voltage detection circuit16when the EOS event occurs, such that the low potential signal from the ground line GL is input from the first node N1to the input terminal of the inverter14, and then the N-MOSFET Mn1is turned on to form the discharge path. Therefore, the EOS surge current at this time can flow to the ground line GL through the N-MOSFET Mn1.

It should be understood that the voltage detection circuit16determines that the EOS event occurs in response to detecting that the voltage of the power line PL exceeds a threshold. Therefore, the threshold value is determined according to a voltage defined by the integrated circuit for EOS protection. Next, various specific implementations of the voltage detection circuit16are described below while making reference toFIGS.2to6. Reference is made toFIG.2, which is a schematic diagram of a voltage detection circuit according to a first embodiment of the present disclosure. In the first embodiment, the voltage detection circuit16may include a plurality of diodes D_1to D_n, a resistor R2, and an N-MOSFET Mn2. The diodes D_1to D_n are connected in series between the power line PL and a second node N2, and n is an integer greater than 1.

Specifically, an anode of a first diode D_1among the diodes D_1to D_n is electrically coupled to the power line PL, and a cathode of an n-th diode D_n among the diodes D_1to D_n is electrically coupled to the second nodes N2, and a cathode of an i-th diode D_i among the diodes D_1to D_n is electrically coupled to an anode of an (i+1)-th diode D_i+1, where i is an integer from 1 to n−1. In addition, the resistor R2is electrically coupled between the second node N2and the ground line GL. A drain of the N-MOSFET Mn2is electrically coupled to the first node N1, a gate of the N-MOSFET Mn2is electrically coupled to the second node N2, and a source of the N-MOSFET Mn2is electrically coupled to the ground line GL.

It can be seen that the diodes D1to Dn are used as the switch electrically coupled between the power line PL and the second node N2, and a quantity (namely n) of the diodes D1to Dn is determined according to a threshold voltage of each of the diodes and the power supply voltage VDD supplied to the IC. For example, assuming that the threshold voltage of each diode is 0.8 volts, it means that only when the voltage of the power line PL exceeds (n*0.8) volts, the diodes D_1to D_n can then all be turned on, that is, at this time, the current can flow to the second node N2through the diodes D_1to D_n. Therefore, if the power supply voltage VDD supplied to the IC is 1.8 volts, in the present embodiment, the quantity of the diodes D_1to D_n can be determined to be 3. Alternatively, if the power supply voltage VDD supplied to the IC is 3.3 volts, in the present embodiment, the quantity of the diodes D_1to D_n can be determined to be 5. That is, during the normal operation, since the power supply voltage VDD supplied to the IC is less than (n*0.8) volts, the current does not flow to the second node N2through the diodes D_1to D_n, such that the N-MOSFET Mn2is turned off, and the voltage detection circuit16will not cause additional current leakage and malfunction.

On the other hand, when the voltage of the power line PL exceeds (n*0.8) volts, the current will flow to the second node N2through the diodes D_1to D_n, such that the N-MOSFET Mn2is turned on, and the voltage detection circuit16electrically connects the first node N1to the ground line GL. Therefore, a low potential signal from the ground line GL is input into the input terminal of the inverter14from the first node N1, and then the N-MOSFET Mn1is turned on to form the discharge path. Since the operating principles of the diodes D_1to D_n, the resistor R2and the N-MOSFETs Mn1and Mn2are known to those skilled in the art, details of the voltage detection circuit16of the first embodiment are omitted hereinafter.

Reference is made toFIG.3, which is a schematic diagram of a voltage detection circuit according to a second embodiment of the present disclosure. The voltage detection circuit16of the second embodiment is similar to the voltage detection circuit16of the first embodiment, and thus the similarities between the two embodiments will not be repeated. It should be noted that, different from the first embodiment using the diodes D_1to D_n as the switch electrically coupled between the power line PL and the second node N2, the second embodiment utilizes a plurality of P-MOSFETs Mp1_1to Mp1_nto serve as the switch electrically coupled between the power line PL and the second node N2. In other words, the voltage detection circuit16of the second embodiment includes the P-MOSFETs Mp1_1to Mp1_n, a resistor R2and an N-MOSFET Mn2. The P-MOSFETs Mp1_1to Mp1_nare connected in series between the power line PL and the second node N2.

Specifically, a source of a first P-MOSFET Mp1_1among the P-MOSFETs Mp1_1to Mp1_nis electrically coupled to the power line PL, and a drain of the n-th P-MOSFET Mp1_namong the P-MOSFETs Mp1_1to Mp1_nis electrically coupled to the second node N2. In addition, a gate and a drain of each of the P-MOSFETs Mp1_1to Mp1_nare electrically coupled to one another, and a drain of the i-th P-MOSFET MP1_iamong the P-MOSFETs Mp1_1to Mp1_nis electrically coupled to a source of the (i+1)-th P-MOSFET Mp1_i+1 among the P-MOSFETS Mp1_1to Mp1_n. Therefore, when the voltage of the power line PL exceeds the threshold value, the P-MOSFETs Mp1_1-Mp1_ncan be turned on, such that the current flows to the second node N2through the P-MOSFETs Mp1_1to Mp1_n, and the N-MOSFET Mn2is also turned on.

Reference is made toFIG.4, which is a schematic diagram of a voltage detection circuit according to a third embodiment of the present disclosure. The voltage detection circuit16of the third embodiment is also similar to the voltage detection circuit16of the second embodiment, and thus the similarities between the two embodiments will not be repeated. It should be noted that, different from the second embodiment using the P-MOSFETs Mp1_1to Mp1_nas the switch electrically coupled between the power line PL and the second node N2, the third embodiment utilizes a plurality of N-MOSFETs Mn3_1to Mn3_nto serve as the switch electrically coupled between the power line PL and the second node N2. In other words, the voltage detection circuit16of the third embodiment includes the N-MOSFETs Mn3_1to Mn3_n, a resistor R2and an N-MOSFET Mn2. The N-MOSFETs Mn3_1to Mn3_nare connected in series between the power line PL and the second node N2.

Specifically, a source of a first N-MOSFET Mn3_1among the N-MOSFETs Mn3_1to Mp3_nis electrically coupled to the power line PL, and a drain of an n-th N-MOSFET Mn3_namong the N-MOSFETs Mn3_1to Mn3_nis electrically coupled to the second node N2. In addition, a gate and a drain of each of the N-MOSFETs Mn3_1to Mn3_nare electrically coupled to one another, and a source of an i-th N-MOSFET Mn3_iamong the N-MOSFETs Mn3_1to Mn3_nis electrically coupled to a drain of an (i+1)-th N-MOSFET Mn3_i+1 among the N-MOSFETS Mn3_1to Mn3_n. Therefore, when the voltage of the power line PL exceeds the threshold value, the N-MOSFETs Mn3_1to Mn3_ncan be turned on, such that the current flows to the second node N2through the N-MOSFETs Mn3_1to Mn3_n, and the N-MOSFET Mn2is also turned on.

Reference is made toFIG.5, which is a schematic diagram of a voltage detection circuit according to a fourth embodiment of the present disclosure. Different from the first embodiment, the fourth embodiment uses a P-MOSFET Mp2to replace the resistor R2and is electrically coupled between the second node N2and the ground line GL. In other words, the voltage detection circuit16of the fourth embodiment includes a plurality of diodes D_1to D_n, the P-MOSFET Mp2and an N-MOSFET Mn2. Specifically, a source of the P-MOSFET Mp2is electrically coupled to the second node N2, a drain of the P-MOSFET Mp2is electrically coupled to the ground line GL, and a gate and the drain of the P-MOSFET Mp2are electrically coupled together. Since the operation principle of the P-MOSFET Mp2replacing the resistor R2is known to those skilled in the art, details of the fourth embodiment will not be repeated hereinafter.

Similarly, reference is made toFIG.6, which is a schematic diagram of a voltage detection circuit according to a fifth embodiment of the present disclosure. Different from the fourth embodiment, the fifth embodiment uses an N-MOSFET Mn4to replace the resistor R2, and the N-MOSFET Mn4is electrically coupled between the second node N2and the ground line GL. In other words, the voltage detection circuit16of the fifth embodiment includes a plurality of diodes D_1to D_n, a N-MOSFET Mn2and the N-MOSFET Mn4. Specifically, a drain of the N-MOSFET Mn4is electrically coupled to the second node N2, a source of the N-MOSFET Mn4is electrically coupled to the ground line GL, and a gate of the N-MOSFET Mn4is electrically coupled to the power line PL. Since the operation principle of replacing the resistor R2by the N-MOSFET Mn4is known to those skilled in the art, details of the fifth embodiment will not be repeated hereinafter.

On the other hand, the inverter14can be a static complementary metal oxide semiconductor (CMOS) inverter, but the present disclosure is not limited thereto. The static CMOS inverter includes a P-MOSFET Mp3and an N-MOSFET Mn5. A source of the P-MOSFET Mp3is electrically coupled to the power line PL, a gate of the P-MOSFET Mp3is electrically coupled to the first node N1, and a drain of the P-MOSFET Mp3is electrically coupled to a gate of the N-MOSFET Mn1through the third node N3. In addition, a source of the N-MOSFET Mn5is electrically coupled to the ground line GL, a gate of the N-MOSFET Mn5is electrically coupled to the gate of the P-MOSFET Mp3, and a drain of the N-MOSFET Mn5is electrically coupled to the third node N3. Since the operation principle of the static CMOS inverter is known to those skilled in the art, the details thereof will not be repeated hereinafter.

Furthermore, in addition to the N-MOSFET or the NPN-BJT, the switch10can also be a P-MOSFET or a PNP BJT. In this case, since the switch10is turned on in response to the control terminal receiving the low potential signal, the integrated circuit for power clamping1provided by the present disclosure can further include an odd number of inverters electrically coupled between the input terminal of the inverter14and the control terminal of the switch10, such that the P-MOSFET or the PNP BJT that is taken as the switch10can also be turned on to form a discharge path when the EOS event occurs. The odd number of the inverters can be implemented in the same manner as the inverter14, but the present disclosure is not limited thereto.

In conclusion, in the integrated circuit for power clamping provided by the present disclosure, the first node can be connected to the ground line through the voltage detection circuit when the EOS event occurs, such that the low potential signal from the ground line can be input to the input terminal of the inverter from the first node, and the N-MOSFET can then be turned on to form the discharge path.