Class DH amplifier

A class DH amplifier is provided. The amplifier is generally comprised of a tracking power supply, a class D amplifier section, and a carrier generator. The tracking power supply receives a supply voltage and an analog input signal, and the tracking power supply provides an input for the carrier generator. Based on its input from the tracking power supply, the carrier generator can output a positive ramp signal and a negative ramp signal to the class D amplifier section. The class D amplifier section can generate an output signal base on the analog input signal and the ramp signals from the carrier generator.

TECHNICAL FIELD

The invention relates generally to amplifiers and, more particularly, to audio and motor control amplifiers.

BACKGROUND

SUMMARY

In accordance with a preferred embodiment of the present invention, an apparatus is provided, The apparatus comprises a power supply that receives a supply voltage and the analog input signal and that outputs a positive regulated signal and a negative regulated signal; a carrier generator that receives the positive regulated signal and the negative regulated signal and that outputs a positive ramp signal and a negative ramp signal; a pulse generator that receives the analog input signal, the positive ramp signal, and the negative ramp signal and that outputs a plurality of pulse width modulation (PWM) signals; and a power stage that receives the plurality of PWM signals, the positive regulated signal, and the negative regulated signal and that outputs the output signal.

In accordance with a preferred embodiment of the present invention, the positive regulated signal is the greater of a first predetermined value and a first value within a first predetermined range above the output signal, and wherein the negative regulated signal is the lesser of a second predetermined value and a second value within a second predetermined range below the output signal.

In accordance with a preferred embodiment of the present invention, the pulse generator further comprises a subtractor that outputs a difference between the analog input signal and the output signal; an integrator that receives the difference between the analog input signal and the output signal; a first comparator that receives an output from the integrator and the positive ramp signal; a second comparator that receives the output from the integrator and the negative ramp signal; and switch control logic that receives outputs from the first and second comparators and that outputs the plurality of PWM signals.

In accordance with a preferred embodiment of the present invention, the power stage further comprises three transistors, wherein each transistor receives at least one PWM signal at its control electrode.

In accordance with a preferred embodiment of the present invention, the three transistors further comprise n-channel enhancement mode MOSFETs.

In accordance with a preferred embodiment of the present invention, an apparatus is provided. The apparatus comprises a tracking power supply that receives a supply voltage and an analog input signal; a carrier generator that receives an output from the tracking power supply and that outputs a positive ramp signal and a negative ramp signal, wherein the amplitudes of positive and negative ramp signals are proportional to the output of the tracking power supply; and a class D amplifier section that receives the analog input signal, the positive ramp signal, and the negative ramp signal and that outputs an output signal.

In accordance with a preferred embodiment of the present invention, the tracking power supply further comprises a switch-mode power supply that receives the supply voltage and the analog input signal and that outputs the positive regulated signal and the negative regulated signal, wherein the positive regulated signal is the greater of a first predetermined value and a first value within a first predetermined range above the output signal, and wherein the negative regulated signal is the lesser of a second predetermined value and a second value within a second predetermined range below the output signal.

In accordance with a preferred embodiment of the present invention, the class D amplifier section further comprises a pulse generator that receives the analog input signal, the positive ramp signal, and the negative ramp signal and that outputs a plurality of PWM signals; and a power stage that receives the plurality of PWM signals, the positive regulated signal, and the negative regulated signal and that outputs the output signal.

In accordance with a preferred embodiment of the present invention, an apparatus is provided. The apparatus comprises a power supply that receives a supply voltage and an analog input signal and that outputs a positive regulated signal and a negative regulated signal, wherein the positive regulated signal is the greater of a first predetermined value and a first value within a first predetermined range above the output signal, and wherein the negative regulated signal is the lesser of a second predetermined value and a second value within a second predetermined range below the output signal; a carrier generator including: a phase section that receives the positive regulated signal and a positive ramp signal and that generates a plurality of phase signals; a positive ramp generator that receives the positive regulated signal and the plurality of phase signals and that outputs the positive ramp signal; and a negative ramp generator that receives the negative regulated signal and the plurality of phase signals and that outputs a negative ramp signal; a pulse generator that receives the analog input signal, the positive ramp signal, and the negative ramp signal and that outputs a plurality of PWM signals; and a power stage that receives the plurality of PWM signals, the positive regulated signal, and the negative regulated signal and that outputs an output signal.

In accordance with a preferred embodiment of the present invention, the power supply is a switched-mode power supply.

In accordance with a preferred embodiment of the present invention, the phase section further comprises a first comparator that receives the positive regulated voltage and the positive ramp signal; a second comparator that receives the ground and the positive ramp signal; a first NOR gate that receives an output from the first comparator, that receives a second phase signal of the plurality of phase signals and that outputs a first phase signal of the plurality of phase signals; and a second NOR gate that receives an output from the second comparator, that receives the first phase signal, and that outputs the second phase signal.

In accordance with a preferred embodiment of the present invention, the power stage further comprises a first FET that receives the positive regulated signal at is drain, a first PWM signal of the plurality of PWM signals at its gate; a second FET that is coupled to ground at is source, a second PWM signal of the plurality of PWM signals at its gate; and a third FET that receives the negative regulated signal at is source, a third PWM signal of the plurality of PWM signals at its gate.

DETAILED DESCRIPTION

Referring toFIG. 1of the drawings, the reference numeral100generally designates a class DH amplifier in accordance with an embodiment of the invention. The amplifier100is generally comprised of a tracking power supply, a carrier generator200, and a class D amplifier section. The tracking power supply generally includes a switch-mode power supply102, while the class D amplifier section generally includes a pulse generator104and a power stage118.

In operation, power supply102, preferably, receives an analog input signal AIN(and/or the output signal AOUT) and a supply voltage VDCand, preferably, outputs the positive regulated signal VDDand the negative regulated signal VSS. As can be seen inFIG. 3, the positive and negative regulated signals VDDand VSSare generally a predetermined value or generally track the output signal AOUT(remaining within a predetermined band or range from the output signal AOUT). Preferably, the positive regulated signal VDDis maintained at a generally constant voltage level (generally about 0.6V) while the output signal AOUTis below a first predetermined threshold (generally about 0.35V), and the positive regulated signal VDDis preferably within a predetermined band or range above the output signal AOUTwhen the output signal AOUTis above the first predetermined threshold. Preferably, the negative regulated signal VSSis maintained at a generally constant voltage level (generally about −0.6V) while the output signal AOUTabove a second predetermined threshold (generally about −0.35V), and the negative regulated signal VSSis preferably within a predetermined band or range below the output signal AOUTwhen the output signal AOUTis below the second predetermined threshold. Based on the positive and negative regulated signals VDDand VSS, the carrier generator200can generate positive and negative ramp signals VDRAMPand VSRAMP.

As can be seen inFIG. 4, the positive and negative ramp signals VDRAMPand VSRAMPgenerally track the output signal AOUT. Preferably, the positive ramp signal VDRAMPhas a peak that is proportional to the positive regulated signal VDD, and, preferably, the negative ramp signal VSRAMPhas a peak that is proportional to the negative regulated signal VSS.

To generate the positive and negative ramp signals VDRAMPand VSRAMP, various types of carrier generators can be used; however, by way of example, a carrier generator200is shown inFIG. 2in greater detail. The carrier generator200is generally comprised of a positive ramp generator218, a phase section220, and a negative ramp generator222.

In operation, the phase section220generates phase signals φ andφ, which operate as control signals for the positive ramp generator218and the negative ramp generator222. The phase section220is generally comprised of comparators204and206, which each receive the positive ramp voltage VDRAMPas a feedback signal. Preferably, comparator204receives the positive ramp signal VDRAMPthrough its inverting input, while comparator206receives the positive ramp signal VDRAMPthrough its non-inverting input. Additionally, the non-inverting input of comparator204preferably receives the positive regulated signal VDD, while the inverting input of comparator206is grounded. NOR gate210can then receive the output from comparator204and phase signalφto generate phase signal φ, and NOR gate212can then receive the output from comparator206and phase signal φ to generate phase signalφ.

Each of the positive and negative ramp generators218and222can then generate their respective positive ramp signals VDRAMPand VSRAMPbased on the phase signals φ andφ, positive regulated signal VDD, and negative regulated signal VSS. Positive ramp generator218generally comprises amplifier202, transistors Q4through Q11, resistors R1through R3, and diodes D1and D2, and negative ramp generator222generally comprises amplifier208, transistors Q12through Q19, resistors R4through R6, and diodes D3and D4. In operation, the amplifiers202and208preferably generate currents that are proportional to the generally instantaneous regulated signals VDDand VSS, making ramp signals VDRAMPand VSRAMPgenerally proportional to regulated signals VDDand VSS, respectively. These currents are then transferred to integrators214and216or are generally shunted based on the phase signals φ andφ, thus generating the ramp signals VDRAMPand VSRAMP. Additionally, resistors R1and R4should, preferably, have equal values, and capacitors C1and C2of integrations214and216should, preferably, have equal values.

The pulse generator104can then receive the analog input signal AIN, the output signal AOUT, the positive ramp signal VDRAMP, the negative ramp signal VSRAMPin order to output a plurality of pulse width modulation (PWM) signals VDSW, VGSW, and VSSW. The pulse generator104generally comprises a subtractor120, an integrator114, comparators106and108, NOR gate110, and switch control logic112. In operation, the subtractor120provides a difference between the analog input signal AINand the output signal AOUTto the integrator114, which provides an integrated signal VIto the comparators106and108. Based on the integrated signal VI, the positive ramp signal VDRAMP, and the negative ramp signal VSRAMP, the comparators106and108can generate positive and negative comp signals VDCOMPand VSCOMP. The positive and negative comp signals VDCOMPand VSCOMP, along with a neutral comp signal VGND(the positive and negative comp signals VDCOMPand VSCOMPNORed by gate110), are generally received by the switch control logic112and converted into the positive, negative, and neutral PWM signals VDSW, VSSW, and VGSW.

These PWM signals VDSW, VGSW, and VSSWcan then be used by the power stage118to generate an output signal AOUT. The power stage118is generally comprised of transistors Q1through Q3. Preferably, each of the transistors Q1through Q3is an n-channel enhancement mode MOSFET. As shown, the drain of transistor Q1receives the positive regulated signal VDDand is actuated at its gate by positive PWM signal VDSW. The source of transistor Q2is generally coupled to ground and is actuated at its gate by neutral PWM signal VGSW. Additionally, the source of transistor Q3receives the negative regulated signal VSSand is actuated at its gate by positive PWM signal VSSW. The source of transistor Q1is tied to the output node. Each of the drains of transistors Q2through Q3is preferably coupled to an output node. Thus, as the transistors Q1through Q3are actuated to generate the output signal AOUT, which can be output to load116(i.e., speaker).

Turning toFIG. 5, the ramp signals VDRAMPand VSRAMP, the integrated signal VI, and PWM signals VDSWand VSSWare shown. As can been seen, the more negative or more positive the integrated signal VIis, the wider the pulse widths of PWM signals VDSWand VSSW(respectively). Since ramp signals VDRAMPand VSRAMPare generally proportional to VDDand VSS, respectively, the pulse widths for smaller output signals are typically wider than for the case where ramp signals VDRAMPand VSRAMPhave a fixed amplitude. This increase in pulse width generally indicates longer actuation periods, the transistors Q1and Q3, generally assisting decreasing distortion. Also, as can be seen inFIG. 6, the neutral PWM signal VGSWgenerally operates to ground the output node when both transistors Q1and Q3are “off,” thus, generally preventing the load106from “floating.”

Overall, the amplifier100offers better power dissipation and consumption characteristics as well as less distortion compared to other classes of amplifiers.