Processing system having a supported page size information register

A processing system includes initialization software that is executable by a processor to identify one or more memory page sizes supported by the processing system. The supported memory page sizes that are identified by the initialization software are stored in one or more memory page size identification registers. Individual bits of the one or more memory page size identification registers may be respectively associated with a memory page size. Whether a memory page size is supported by the processing system may be determined by checking the logic state of the individual bit corresponding to the memory page size.

BACKGROUND OF THE INVENTION

1. Technical Field

The present invention relates to memory management in a processing system and, more particularly, to a processing system having a supported page size information register.

2. Related Art

There are different manners in which the memory of a processing system may be organized. One such system uses virtual memory. Virtual memory allows software to run in a memory address space in which the size and addressing of the memory space is not tied strictly to the physical memory of the processing system. In virtual memory systems, the operating system maps virtual memory to physical memory. The operating system uses this mapping to detect when an address is required that does not currently relate to main memory so that the requested data can be accessed.

Virtual memory may be implemented through paging. When the processing system uses paging, the low order bits of the virtual address are preserved and used directly as the low order bits of the actual physical address. In contrast, the high order bits may be treated as a key or index to one or more address translation tables that correspond to a range of consecutive physical addresses. The memory referenced by such a range may be called a page. Page sizes may range in size, for example, from 512 bytes through 8 megabytes.

The mappings between virtual memory and physical memory may be stored in page table entries of a page table array. These page table entries may be used by the operating system to translate the virtual address to a physical address. The processing system may include a translation lookaside buffer (TLB) to enhance the efficiency with which virtual memory addresses are translated to the corresponding physical addresses. The TLB may be a memory that has a fixed number of entries containing parts of various page table entries that improve the speed of the translation of a virtual address to its corresponding physical address. A TLB may include a content-addressable memory in which the search key is the virtual address and the search result is the physical address and access permissions. If the search of the TLB yields a match, the translation is known very quickly, and the physical address is used to access memory. If the virtual address is not in the TLB, the translation proceeds via the page table, which may take longer to complete.

The page size of the virtual/physical address space may be fixed and/or difficult to dynamically change. Nevertheless, the page size(s) used in the page table entries and the TLB entries may have an impact on the performance of the system memory. Smaller page sizes may be advantageous when high granularity control of the memory access permissions is required. Likewise, small page sizes may be advantageous when applications only require small portions of the virtual memory space for their operation. Large page sizes, however, may be advantageous when used in connection with a TLB since TLB misses are less likely to occur when the virtual memory space is organized into large pages.

Many systems that use multiple page sizes do so in a static manner. The versatility of such systems may be limited. Other systems implement multiple page sizes in a dynamic manner using hardware. Multiple TLBs also may be used with different characteristics associated with each page size. However, the manner in which the multiple page sizes may be realized is restricted to the manner in which it is implemented in the hardware and may add a significant amount of cost to the system.

Different chip implementations, even within the same CPU architectures, may have differing methods of reporting their page size support capabilities. Of the will page size support may be provided in code that is specific to the CPU architecture. This may require writing new kernel code for each CPU configuration, which can be costly and time-consuming. Therefore, a need exists for an improved system that can isolate supported page sizes from the kernel while concurrently supporting variable page sizes.

SUMMARY

A processing system includes initialization software that is executable by a processor to identify one or more memory page sizes supported by the processing system. The supported memory page sizes that are identified by the initialization software are stored in one or more memory page size identification registers. Individual bits of the one or more memory page size identification registers may be respectively associated with a memory page size. Whether a memory page size is supported by the processing system may be determined by checking the logic state of the individual bit corresponding to the memory page size.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

FIG. 1is a block diagram of a processing system100that may implement variable page size memory organization. The processing system100includes a processor105that accesses physical memory110. Processor105is shown as a single processor. However, system100may be implemented as a multiprocessor system, a parallel processing system, or other architectures.

Physical memory110may include software instruction space115and data space120. The software instruction space115may include memory management software125and other software code130. The memory management software125may be executable by processor105to manage the memory space of the processing system100. InFIG. 1, the memory management software125manages the memory of system100using virtual memory addressing or methods that address memory separate from the main memory.

InFIG. 1, the processing system100uses one or more page tables135that provides a mapping between virtual memory addresses and corresponding physical addresses of physical memory space110. Multiple page tables may be used and managed. Page table135may reside in the physical memory space110, in a memory management unit, and/or in other physical memory space.

A translation lookaside buffer (TLB)140is adapted to cache certain entries of the page table135. The cache provides faster translations between a virtual address provided by processor105at145and a physical address provided at150. The physical address150, in turn, is used to access the corresponding entries of physical memory space110. The TLB140may be part of the processor105, part of a memory management unit, or maybe part of a separate hardware module.

Memory page size support may vary between processing architectures, even within the same processor family. The software used to identify the supported memory page sizes may be directly linked into the kernel of the operating system. The processing system100, however, isolates the supported memory page sizes from the kernel so that the supported sizes may be identified and accessed during initialization and/or reset operations without further reference to the kernel.

FIG. 2shows initialization software200that may be executed by the processing system100during a system initialization/reset operation. At205, the processor(s) is reset/initialized. The entries of the TLB140are initialized at210. At215, the memory space used in the processing system100is initialized. Any inquiries relating to the memory page sizes supported by the processing system100are made at220. The software that controls these inquiries may be made initially through the kernel of the operating system and may be generic to multiple processor architectures. However, the software need not be directly linked into the kernel and, therefore, may easily be varied from system to system. Information identifying the supported memory page sizes may be stored in a canonical format in memory at225. The supported memory page sizes may subsequently be accessed through reference to the stored information.

FIG. 3shows a register format that may be used to store the memory page size information identified at225. The memory page size identification register305ofFIG. 3is comprised of 16 bits. Each of these bits is in a predetermined logic state, such as a true or false state, depending on whether the memory page size corresponding to that location is supported or unsupported. The correlation between the 16 bits of register305and their memory page size is designated by the lines connecting a given bit to an alphanumeric character corresponding to the memory page size. If a bit in register305is set to a true logic state, the memory page size corresponding to that bit is supported by the processing system100. For example, if the memory page size identification register305stored a word having a value 0X17H, it would indicate that the supported page sizes are 1 kilobyte, 4 kilobytes, 16 kilobytes, and 256 kilobytes. Any time a software process is in need of the supported page size information, it can access the information stored in the register305.

FIG. 4illustrates a structure for the page table135and TLB140. In these tables, the low order bits of the binary representation of a virtual address are preserved and may be used as the low order bits of the physical address. The high order bits may be treated as a key into one or more page tables. The page tables, in turn, include virtual address to physical address translation information. The page table135may include a plurality of page table entries405,425-450. Each of the illustrated page table entries405,425-450may include information for translating a virtual address to a corresponding physical address410. Entries may also include memory page size information420identifying the page size of the corresponding virtual address page and access permission information415for the corresponding virtual address page. Other information about the virtual address page such as whether the page has been written to by a process, when it was last used, also may be included in each of the page table entries.

The translation lookaside buffer140is used to cache selected entries of the page table135. Each of the TLB entries, such as those shown at470,473,475, and480may include a subset, additional information, or the same information as that found in the page table entries of page table135. InFIG. 4, each of the TLB entries may include information for translating a virtual address to a corresponding physical address455and memory page size information465for a identifying the page size of the corresponding virtual address page. It may also include access permission information460identifying the access permissions for the corresponding virtual address page. As with the page table entries, other information relating to the address page such as whether the page has been written to by a process and/or, when it was last used also may be included in each of the TLB entries.

The TLB140may have a limited number of TLB entries. The number of entries may be less than the number of page table entries in page table135. The selection of the page table entries that are to be cached in the TLB140may be determined by one or more caching processes. Such processes may rely on the relative locality of requested/accessed virtual memory locations, the frequency with which the virtual memory locations are accessed by various software applications, and/or other criteria. One or more such processes may be employed based on detailed system requirements, which may vary from system to system. To facilitate explanation, page table entry405is cached at TLB entry470, page table entry435is cached at TLB entry473, page table entry440is cached at TLB entry475, and page table entry445is cached at TLB entry480.

FIG. 5is a diagram showing operations that may be used to process a request associated with virtual memory. A virtual memory request is executed at505. At510, the process determines whether the virtual memory page associated with the virtual memory request is cached in the TLB140. If it is not, the smay execute one or more operations associated with TLB miss handling hardware/software at515. However, if the virtual memory page associated with the virtual memory request is cached in the TLB140, the process determines whether the request complies with the access permissions associated with the virtual memory page. The process may check the access permissions460of the corresponding TLB entry to make sure that the request does not violate the permissions for the virtual memory page. Such permissions may identify the corresponding virtual memory page as read-only, write-only, read/write, or another state. If the virtual memory request at505is invalid as determined by the check at520, the process may execute one or more operations associated with permission violation handling software525. Otherwise, the TLB140uses the upper bits of the virtual memory to generate the upper portion of a physical address page, while the lower bits of the virtual memory address may be used as an offset into the physical address page. These operations may be executed at530. Execution of the virtual memory request using the corresponding physical address is executed at535.

FIG. 6shows operations that may be executed to implement variable page size memory organization. At605, a page table operation is executed. This operation may include any operation that alters the page table135such as, for example, accessing page table entries, adding page table entries, removing page table entries, updating page table entries, or other operations. At610, the process checks the page table135to determine whether the operation executed at605has changed a page table entry. Such changes may include whether a new page table entry has been added, whether an existing page table entry has been removed, or other operations. If the operation executed at605has not resulted in such a change to one or more of the page table entries, the processing system100continues with the execution of other operations at615.

If the operation executed at605has resulted in a change to the page table entries of the page table135, a further check is made at620. In this check, the processing system100determines whether the changes have resulted in a run of contiguous page table entries having common characteristics. Contiguous page table entries may be those that have both contiguous virtual addresses and contiguous physical addresses. At620, the check involves locating contiguous page table entries having substantially the same or identical access permission information. To increase the efficiency of this check, the operations at620may be limited to a check of page table entries within a certain locational distance of the changed page table entry. If no such contiguous page table entries are found during the check at620, the processing system100may continue execution of other operations at615.

If a run of contiguous page table entries having the requisite common characteristics are found, the contiguous page table entries are identified at625and analyzed at630. The analysis at630may include, for example, an analysis of whether any run of the contiguous page table entries may be consolidated into one or more page table entries having a larger page size than the page size of the original contiguous page table entries. The new, larger page size may be a multiple of the smallest page size used to organize the virtual memory space of the processing system100. For example, if there are at least sixteen contiguous page table entries identified at625that have a page size of 4 kilobytes each, the page size for the contiguous page table entries may be updated to a larger virtual page size of 64 kilobytes. Similarly, if there are 256 contiguous page table entries identified at625that have a page size of 4 kilobytes each, the page size for the contiguous page table entries may be updated to a larger virtual page size of 1 megabyte.

Contiguous page table entries meeting the analysis criterion applied at630are updated at635with the new page size information. The updating operation applied at635may involve replacing each of the contiguous page table entries with the same information, including the new page size information. Alternatively, if permitted by the architecture of the page table, it may be possible to consolidate the contiguous page table entries into a single page table entry having the new page size information thereby releasing the memory associated with the remaining contiguous page table entries.

Entries in the TLB140corresponding to the page table entries updated at635are updated at640with the new page size information. The updating operation applied at640may involve consolidating all of the TLB entries corresponding to any of the consolidated contiguous page table entries into a single TLB entry with new information, including the new page size information. The remaining TLB entries corresponding to the consolidated contiguous page table entries may be removed from the TLB140thereby freeing TLB memory and allowing the TLB140to cache more page table entries.

The number of contiguous page table entries identified at620ofFIG. 6that are consolidated to entries having a larger page size may vary. For example, it may be possible to consolidate all of the contiguous page table entries identified at620. Alternatively, it may be possible to consolidate one or more subsets of the identified contiguous page table entries to corresponding page table entries of the same or different page sizes. Which of the contiguous page table entries identified at620are ultimately consolidated, if any, may depend on system design specifications and the specific analysis requirements applied to the identified entries at630.

FIG. 7is a diagram showing operations that may be executed by the processing system100during the analysis operation shown at630ofFIG. 6. InFIG. 7, the operations are executed to determine whether any of the identified contiguous page table entries of625meet the criterion for consolidating them into one or more page table entries having a larger page size. The number of identified contiguous page table entries are determined at705. At710, a check is made to determine whether there are a sufficient number of contiguous page table entries in the identified range to consolidate into one or more page table entries having a larger page size. The number of contiguous page table entries that should exist in the decision operation at710before they are consolidated to a page table entry having a larger page size may vary from system to system. In the illustrated example, a decision on whether to consolidate the contiguous page table entries to a page table entry having a larger virtual page size may be based on whether the number of original contiguous page table entries are sufficient to form a page table entry having a new virtual page size that is supported by the system100. The page sizes supported in the processing system100may be querying the information found in register305ofFIG. 3.

At operation710, the process may consider whether the consolidation will result in wasted memory space. If the consolidation will result in an excess amount of memory space toward the end of a consolidated virtual page, a decision may be made at710to prevent consolidation or to consolidate the page table entries to a new supported page size. The new page size may be larger than the page size of the original contiguous page table entries but smaller than the largest page size value that could otherwise be used to consolidate the contiguous page table entries.

As a result of the operation shown at710, an initial decision may be made on whether a consolidation will take place, which of the identified contiguous page table entries are susceptible of consolidation, and the proposed page size that will be used for the consolidation. If a decision is made at710to forgo consolidation of any of the identified contiguous page table entries, then the processing system100may continue execution of other processes at715. However, if a decision is made at710to consolidate any run of contiguous page table entries, a further analysis occurs at720. The analysis at720determines whether the run of contiguous page table entries are located on page table boundaries suitable for use with the proposed larger page size value. For example, if a set of 4 kilobytes/page contiguous page table entries are to be consolidated to a page table entry having a page size of 64 kilobytes, the first page table entry of the set of contiguous page table entries should begin at a 64 kilobyte boundary of the memory space110.

If the contiguous page table entries meet the memory boundary criterion of720, then the contiguous page table entries that are to be consolidated and the proposed page size are passed to635ofFIG. 6at725. Otherwise, the proposed page size may be decreased to the next smaller page size supported by the process at730. At735, the process determines whether the decreased page size is equal to or less than the original page size of the contiguous page table entries. If the smaller page size is equal to or less than the original page size, then there is no need to consolidate the contiguous page table entries and the processing system100may continue execution of other processes at715. However, if the decreased page size is greater than the original page size, the memory boundary check at720may be executed using the smaller page size. These operations may be repeated until the memory boundary check is met or the proposed page size is decreased so that it is equal to or less than the original page size of the contiguous page table entries that are tagged for consolidation.

FIG. 8shows a process that may be used to reduce the page size of contiguous page table entries when necessary. At805a page table operation is executed. This operation may include any operation that alters the page table135such as, for example, accessing page table entries, adding page table entries, removing page table entries, updating page table entries, or other operations. At810, the processing system100determines whether the operation executed at805has changed a page table entry. Such changes may include whether an existing page table entry has been removed or similar operation. If the operation at805has not resulted in such a change to one or more of the page table entries, the processing system100continues with the execution of other operations at815.

If the entries of the page table change at805, a further check is made at820. At820, the processing system100checks the changed page table to determine whether the changes have occurred in a contiguous page table entry range with large pages. At820, the check may involve determining whether the changed page table entry is in a range of page table entries that were previously consolidated into a page table entry having a large page size. If no such contiguous page table entries are found during the check at820, the processing system100may continue execution of other operations at815.

If such contiguous page table entries are found at820, the contiguous page table entries are identified at825and analyzed at830. The analysis at830may include an analysis of whether the contiguous page table entries may be divided into multiple page table entries having a reduced page size when compared to the original page size of the contiguous page table entries. The new, reduced page size may be a multiple of the smallest page size used to organize the virtual memory space of the processing system100, and which is supported by the system100as indicated by register305.

Contiguous page table entries meeting the analysis criterion applied at830are updated at835with the new page size information. The updating operation applied at835may replace each of the contiguous page table entries with the same information, including the new page size information and/or dividing a previously consolidated page table entry range into multiple ranges having a smaller page size.

Entries in the TLB140corresponding to the page table entries updated at835are updated at840with the new page size information. The updating operation applied at840may involve adding further TLB entries corresponding to the contiguous page table entries analyzed at830.

FIG. 9shows a manner of implementing the memory management software125architecture. The memory management software125may include portions of the system reset/initialization software200, page table management software705, TLB management software710, and memory page size management software715. The memory management software125and the system reset/initialization software may support memory page sizes of the system in a canonical format such as the format shown inFIG. 3. The supported page size information is subsequently available to the page table management software705, the TLB management software710, and the memory page size management software715without resort to kernel specific code or calls. The page table management software may manage a page table, such as page table135, having a plurality of page table entries. Each of the plurality of page table entries may include information for translating a virtual address to a corresponding physical address, memory page size information for a corresponding virtual address page, and access permission information for the corresponding virtual address page. The translation lookaside buffer management software may manage a translation lookaside buffer that is adapted to cache information corresponding to a plurality of the page table entries, including corresponding memory page size information. The translation lookaside buffer management software may manage multiple translation lookaside buffers.

The memory page size management software may be responsive to changes in the page table made by the page table management software to identify contiguous page table entries having substantially same access permission information. The memory page size management software may update the memory page size information for at least one of the identified contiguous page table entries with new memory page size information if an analysis of the identified contiguous page table entries warrants a change to the memory page size. The new memory page size information may correspond to a largest supported memory page size to which any run of the identified contiguous page table entries may be mapped. The new memory page size may correspond to a larger page size than originally assigned to the identified contiguous page table entries. Alternatively, the new memory page size information may correspond to a reduced supported memory page size of a previously consolidated range of contiguous page table entries. The memory page size management software also may facilitate updating one or more corresponding entries, if any, of the translation lookaside buffer with the new memory page size information.

The memory page size management software may limit its analysis operations to a predefined range of page table entries to increase efficiency. Analysis may be limited to contiguous page table entries that are locally proximate page table entries that have been changed in the page table, deleted from the page table, and/or added to the page table. The change, deletion, and/or addition may correspond to the change in the page table to which the memory page size management software has responded to make the check. Further, the memory page size management software may be responsive to changes in the page table to facilitate updating the memory page size information for all of the contiguous page table entries with the new memory page size information.

The specific functionality of each of the components of the memory management software125set forth above may be shared between them. There need not be any strict divisions of that functionality. In one system, the memory page size management software715may directly update the corresponding entries of the translation lookaside buffer. In another example, the memory page size management software715may cooperate with the translation lookaside buffer management software710to execute the TLB update.

As shown inFIG. 1, the memory management software125may reside in a physical memory110. The physical memory110may be a random access memory, a static memory, or a distributed storage medium. In the other systems, the memory management software125may reside on other storage media for use, storage, and or transfer of the software code. Such storage media may include, for example, a hard disk drive, a USB drive, flash memory, read only memory, optical storage media, or other storage media.