Circuit and method for expanding a serial bus

A serial bus expansion circuit, system, and method are provided. In one embodiment, the serial bus expansion circuit comprises a bus distribution circuit selectively coupling a serial bus to one of a number of serial bus outputs. The serial bus expansion circuit also includes a distribution controller having a control output coupled to a control input of the bus distribution circuit, and, a number of power-up pull resistors coupling each of the serial bus outputs to a power-up pull source.

TECHNICAL FIELD

The present invention is generally related to the field of data communications and, more particularly, is related to a system and method for expanding a serial bus.

BACKGROUND OF THE INVENTION

In consumer electronics, telecommunications, and industrial electronics, there are often many similarities between seemingly unrelated designs. For example, nearly every system includes some intelligent control such as a single integrated circuit (IC) microcontroller. Such systems may also include general-purpose circuits like liquid crystal display drivers, remote input/output ports, memory devices, or data converters, etc.

To exploit the similarity in system components and other characteristics to the benefit of both systems designers and equipment manufacturers, as well as to maximize hardware efficiency and circuit simplicity, a simple bi-directional two wire bus for efficient Inter-IC control was developed by Philips Semiconductors™ headquartered in Eindhoven, The Netherlands having operations throughout the world. The Inter-IC (I2C) bus is outlined in the I2C-Bus Specification, Version 2.1, January 2000, promulgated by Philips Semiconductors™, such specification being incorporated herein by reference in its entirety.

The I2C Specification provides for the coupling of multiple devices including at least one master device and a number of slave devices to a two wire serial bus to facilitate serial data communications there between. A unique address is assigned to each slave device so that each slave device may be identified by the master device to facilitate serial communications therewith, etc. However, the number of devices that may be included on the serial bus is limited to the number of available addresses.

SUMMARY OF THE INVENTION

In view of the foregoing, a serial bus expansion circuit, system, and method are provided. In one embodiment, the serial bus expansion circuit comprises a bus distribution circuit selectively coupling a serial bus to one of a number of serial bus outputs. The serial bus expansion circuit also includes a distribution controller having a control output coupled to a control input of the bus distribution circuit, and, a number of power-up pull resistors coupling each of the serial bus outputs to a power-up pull source.

In another embodiment, a system for serial bus expansion is provided that comprises means for selecting one of a number of devices to be coupled to a serial bus, wherein each of the devices is capable of communicating on the serial bus, means for selectively coupling the serial bus to one of the number of devices, and, means for sequentially pulling a voltage potential of each of a number of serial bus inputs of the respective devices to a predefined source voltage potential and then to a predefined common voltage potential upon an occurrence of a system power-up condition.

In still another embodiment, a serial bus expansion method is provided that comprises the steps of providing a bus distribution circuit to selectively couple a serial bus to one of a number of serial bus outputs; determining a select one of the serial bus outputs to which the serial bus is to be coupled; controlling the bus distribution circuit to couple the serial bus to the select one of the serial bus outputs; and providing a number of power-up pull resistors that couple each of the serial bus outputs to a power-up pull source.

DETAILED DESCRIPTION OF THE INVENTION

With reference toFIG. 1, shown is a serial bus expansion circuit100according to an embodiment of the present invention. The serial bus expansion circuit100is electrically coupled to a serial bus103that facilitates serial data communication between a number of independent devices as set forth in the I2C-Bus Specification, Version 2.1, January 2000, the entire content of which is incorporated herein by reference. The serial bus103includes two conductors, namely, a serial data line SDA and a serial clock line SCL as is set forth in the above-referenced specification. A unique address is associated with each device coupled to the serial bus103as can be appreciated by those with ordinary skill in the art. In cases where the number of devices coupled to the serial bus103exceeds the number of available addresses, then the serial bus expansion circuit100provides for the coupling of multiple devices that share the same address to the serial bus103.

The serial bus expansion circuit100includes a distribution controller106, a bus distribution circuit109, and a power-up pull source113. The distribution controller106includes a serial bus input116for coupling to the serial data line SDA and the serial clock line SCL. The distribution controller106also includes a control output119that is coupled to a control input123of the bus distribution circuit109. The bus distribution circuit109includes a serial bus input126to which the serial data line SDA is coupled. The bus distribution circuit109also includes a number of serial bus outputs129, each of the serial bus outputs129being adapted for coupling to a respective serial device1300-N. The bus distribution circuit109may have any number serial bus outputs129to accommodate a respective number of the serial devices1300-N.

In this respect, the bus distribution circuit109may comprise, for example, a multiplexer or other appropriate circuit. The bus distribution circuit109thus acts as a switch that couples the serial bus input126to a respective one of the serial bus outputs129based upon a control signal131applied to the control input123. The control input123and control output119may comprise a multiple conductor inputs and outputs to accommodate a parallel bus therebetween. In such case, the control signal131would be a parallel signal. Alternatively, serial communication can be established between the distribution controller106and the bus distribution circuit109to communicate the control signal131therebetween to control the state of the bus distribution circuit109in coupling the serial data line SDA to one of the serial bus outputs129.

The power-up pull source113includes a state circuit133and a switch circuit136. The state circuit133controls the state of the switch circuit136. In this respect, the switch circuit136maybe, for example, a transistor or other type of switch circuit. The switch circuit136includes a source voltage input139that is coupled to a source voltage Vcc. The switch circuit136also includes a second input143that is coupled to a common voltage146. The common voltage146may be, for example, a chassis ground connection or other common voltage source having a zero voltage potential as set forth in the I2C-Bus Specification. Alternatively, the common voltage146may be another voltage potential that represents a relative low voltage value. The output of the switch circuit136is coupled to a number of power-up pull resistors149that are in turn coupled to a respective one of the serial bus outputs129as shown. In this respect, the power-up pull source113controls the voltage seen on the respective serial bus outputs129during power-up as will be discussed.

The serial clock line SCL is coupled to all devices as well as to the distribution controller106to provide a time reference by which serial information may be communicated via the serial data line SDA. In addition, the serial communication via the serial data line SDA is controlled by one or more master devices or various slave devices coupled thereto. In conducting serial communication via the serial data line SDA, these devices are capable of pulling voltage on the serial data line SDA to a relative low voltage representing a logical “0” as is set forth in the I2C-Bus Specification, Version 2.1, January 2000 as referenced above. This may be done, for example, when a device couples the serial data line SDA to the common voltage146. The I2C-Bus Specification also specifies external pull sources that act as pull-up sources pulling the voltage on the serial data line SDA to a relative high voltage that represents a logical “1”. The external pull sources may be, for example, external pull resistors coupled between an external voltage source (not shown) and the serial data line SDA or constant current sources coupled to the serial data line SDA. In either case, when no device couples the serial data line SDA to a relative low voltage, the external pull sources pull the voltage potential on the serial data line to the relative high voltage. However, the effect of the external pull sources is overridden by the action of a device that couples the serial data line SDA to the common voltage146. The actual values of the high and low voltages employed that represent the logical values may vary from circuit to circuit as can be appreciated by those with ordinary skill in the art.

In order to pull the voltage low on the serial data line SDA, the master or slave devices may act to couple the serial data line SDA to a common voltage146. Otherwise, the voltage on the serial data line SDA is pulled to a relative high voltage by one or more external pull sources. The value of the resistance of the power-up pull resistors149is much greater than the value of any resistors employed as the external pull sources coupling an external voltage source to the serial bus103. The specific value of the power-up pull resistors149is high enough relative to the value of any pull resistors employed in corresponding external pull sources (assuming that a current source is not employed as the external pull source) so that the external pull resistors can pull the voltage on the serial data line SDA to a relative high voltage when the power-up pull source113has coupled the power-up pull resistors149to the common voltage. In other words, the value of the power-up pull resistors149is large enough relative to any external pull resistors to allow a voltage potential placed on the serial data line SDA to be overridden by a voltage applied by the external pull sources and by any master or slave devices coupled to the serial bus103regardless of the state of the power-up pull switch113.

Next, the operation of the serial bus expansion circuit100is described. The distribution controller106generates the control signal131that is applied to the control input123of the bus distribution circuit109. The bus distribution circuit109responds by coupling the serial bus input126to a respective one of the serial bus outputs129that corresponds to the value of the control signal131. Thus, the distribution controller106includes state circuitry that responds to a selection message received from a remote device (not shown) via the serial bus103. The selection message is addressed to the distribution controller106. The distribution controller106ultimately generates the control signal131that controls the toggling of the bus distribution circuit109to connect a selected one of the serial devices1300-Nto the serial data line SDA. The distribution controller106generates the control signal131based upon a data payload in the selection message.

During power-up of the serial bus expansion circuit100, the power-up pull source113prevents all of the serial bus outputs129from “floating” by coupling the source voltage Vccand/or the common voltage146to their respective serial bus outputs129through the power-up pull resistors149. Specifically, the power-up pull source113first couples the power-up pull resistors149to the source voltage Vccduring power-up. This applies a high voltage on all of the serial bus outputs129that is applied to the serial devices130. Thereafter, the power-up pull source113causes the common voltage146to be applied to the power-up pull resistors149. This causes a transition from high to low on each of the serial bus outputs129that is seen by each of the serial devices130.

In the typical situation, the serial clock line SCL is in a high state during the power-up of the serial bus expansion circuit100. Due to the high to low transition on the serial data line SDA caused by the power-up pull source113, all of the serial devices130perceive a start condition as is set forth in the I2C-Bus Specification except for the serial device130actually coupled to the serial data line SDA through the bus distribution circuit109that may or may not perceive the start condition depending upon the state of the serial data line SDA. The respective serial device130that is coupled to the serial data line SDA through the bus distribution circuit109may then receive further data that is transmitted by a respective device on the serial bus103. However, the remaining serial devices130coupled to the remaining serial bus outputs129that are not coupled to the serial data line SDA through the bus distribution circuit109continue to perceive the common voltage146due to the action of the power-up pull source113. Thus, the voltage on these lines does not float and the serial devices130coupled thereto do not react to data communication over the serial data line SDA as they do not see the shared address or any other logical information beyond the logical zero imposed by the power-up pull source113. Thus, these serial devices130ignore the logic zero that is maintained on the serial data line SDA while various clock pulses occur during the ordinary course of communication between other devices on the serial bus103.

However, for some serial data circuits that employ the serial bus103, a byte of zeros or other predefined value transmitted as the address value on the serial data line SDA sets a “general call condition” as is set forth, for example, in the I2C-Bus Specification. In a general call condition, all devices coupled to the serial bus103respond thereto. If the general call condition is triggered, for example, by a string of zeros in a predefined serial data circuit, then after power-up, the serial devices130not coupled directly to the serial data line SDA through the bus distribution circuit106will perceive a general call condition. This is because they see a string of zeros as the value on the serial bus outputs129not coupled to the serial data line SDA through the bus distribution circuit109is maintained in a low state after power-up. To address this problem, according to an aspect of the present invention, the serial devices130are configured so as not to respond to the general call condition if such condition is a string of zeros.

From time to time, the distribution controller106toggles the bus distribution circuit109so that a respective transmitting or receiving device coupled to the serial bus103may communicate with a different one of the serial devices130coupled to the serial bus outputs129. The toggling of the bus distribution circuit109in this manner occurs during an acknowledge bit on the serial data line SDA during an acknowledge clock pulse by the serial clock line SCL.

With reference toFIG. 2, shown is a timing diagram200that depicts the signals on the serial data line SDA and the serial clock line SCL with respect to time. As shown, a number of clock pulses203are generated on the serial clock line SCL by a respective master that is coupled to the serial bus103. In synchronization with the clock pulses203, the data bits206are transmitted on the serial data line SDA in individual bytes209. The first byte209includes an address213and the second byte209comprises a data payload216. At the left most end of the timing diagram200is a start condition219in which a transition from high to low occurs in the serial data line SDA while the serial clock line SCL is maintained in a high state as is set forth by the I2C-Bus Specification previously incorporated by reference. The start condition219informs all devices coupled to the serial bus103(FIG. 1) that an address213and a data payload216are forthcoming on the serial bus103.

Depending on the address213transmitted, only one device on the serial bus103associated with such address will respond to the data in the payload216. Although only two bytes209are shown, it is understood that the message may be any number of bytes long. After the transmission of each byte209, an acknowledge bit223is provided that coincides with every ninth clock pulse. The acknowledge bit223provides an opportunity for a receiving device on the serial bus103to transmit an acknowledgement to the transmitting device via the serial data line SDA as is set forth in the I2C-Bus Specification. In particular, during the acknowledge bit223the transmitting device frees the serial data line SDA so that the receiving device may transmit an acknowledge pulse in coordination with the acknowledge clock pulse as is set forth in the I2C-Bus Specification. In this manner, the transmitting device knows that the byte209that was transmitted was successfully received by the receiving device via the serial bus103.

The timing diagram200also includes a stop/restart condition226that is detected by an appropriate transition in the serial data line SDA while the serial clock line SCL is held high as is set forth in the I2C-Bus Specification. With respect to the serial bus expansion circuit100, the address213indicates a message for the distribution controller106and the data payload216is interpreted by the distribution controller106to generate an appropriate control output119that selects a desired state of the bus distribution circuit109as will be discussed. The actual switching of the bus distribution circuit109by the application of an appropriate control output119thereto occurs, for example, during the acknowledge bit223. This may be done, for example, so that any one of the serial devices130(FIG. 1) that are subsequently coupled to the serial data line SDA after a toggling of the bus distribution circuit109do not perceive an inadvertent start condition219.

With reference toFIG. 3, shown is second timing diagram300according to an aspect of the present invention. The timing diagram300depicts the operation of the power-up pull source113(FIG. 1) relative to signals on the serial data line SDA and the serial clock line SCL as shown. During power-up, the state circuit133in the power-up pull source113couples the source voltage Vccto the power-up pull resistors149(FIG.1), thereby causing the serial bus outputs129to be pulled into a high state. In particular, the state circuit133(FIG. 1) places the switch circuit136(FIG. 1) in a first state that couples the source voltage Vccto the power-up pull resistors149. Thereafter, the state circuit133in the power-up pull source113toggles the switch circuit136into a second state that couples the common voltage146to the power-up pull resistors149causing a transition of the serial bus outputs129to a low state with the exception of the serial bus output129that is coupled to the serial data line SDA through the bus distribution circuit109. Specifically, the serial bus output129coupled to the serial data line SDA takes the value that is placed on the serial data line SDA. Assuming that the serial clock line SCL is in a high state, then a start condition219is observed by the remaining serial devices130coupled to the serial bus outputs129. In addition, the switching of the power-up pull source113during power-up of the serial bus expansion circuit100should occur before a start condition occurs on the serial bus103to prevent data corruption.

Where a respective one of the serial devices130is coupled to the serial data line SDA by the bus distribution circuit109, then subsequent communication by other devices coupled to the serial bus103transmitted thereto may include a restart condition where the serial data line SDA is controlled by a device beyond the serial bus expansion circuit100. However, those serial devices130that are not coupled to the serial bus line SDA perceive a constant low state at their serial data line inputs and, consequently, they ignore all activity until the bus distribution circuit109is toggled to an appropriate position.