Multichip module including a plurality of semiconductor chips, and printed circuit board including a plurality of components

A multichip module includes at least one first semiconductor chip and at least one second semiconductor chip. The semiconductor chips are arranged in coplanar fashion on or in a support medium and respectively include matching components and contact areas arranged on their active top sides. At least one second semiconductor chip includes an arrangement of contact areas which is mirror-inverted in relation to a first semiconductor chip. At least one first semiconductor chip and at least one second semiconductor chip are arranged next to and/or behind one another (i.e., adjacent to one another) such that those of their edges which respectively have a matching arrangement of contact areas are opposite one another. Wiring arrangements extend between respectively opposite contact areas and between contact areas at the outer edges of the semiconductor chips and external contacts.

FIELD OF THE INVENTION

The invention relates to a multichip module including a plurality of semiconductor chips and also to a printed circuit board including a plurality of components.

BACKGROUND

Electronic devices are known which have a plurality of semiconductor chips arranged next to one another on a mounting substrate. In this arrangement, these semiconductor chips have contact areas which are the starting point for wiring arrangements both for connecting the semiconductor chips to one another and for connection to external contacts on the mounting substrate. The wiring arrangement connecting the semiconductor chips to one another is often very complex and very cost intensive.

SUMMARY OF THE INVENTION

It is an object of the invention to provide a multichip module that includes a plurality of semiconductor chips and a simple wiring arrangement.

It is another object of the invention to provide a printed circuit board that includes a plurality of components and a simple wiring arrangement.

The above and further objects are achieved individually and/or in combination, and it is not intended that the present invention be construed as requiring two or more of the objects to be combined unless expressly required by the claims attached hereto.

In accordance with the present invention, a multichip module comprises at least two semiconductor chips arranged in one plane on or in a support medium. The semiconductor chips each include at least one integrated circuit, and at least one second semiconductor chip is designed relative to a first semiconductor chip such that the contact areas arranged on an active top side of the second semiconductor chip are at least partly mirror-image symmetrical with respect to the contact areas on the first semiconductor chip. In this context, mirror-image symmetry is understood to mean mirroring at a mirror plane that is arranged perpendicular to the active top side of the semiconductor chip.

The term second semiconductor chips, as used herein, refers to those semiconductor chips whose contact areas are each designed to be mirror-image symmetrical with respect to the contact areas on a first semiconductor chip. The term first semiconductor chips, as used herein, refer to un-mirrored semiconductor chips.

At least one first and at least one second semiconductor chip are arranged in the multichip module next to and/or behind one another (i.e., adjacent to one another) such that their edges, each including at least a partly matching arrangement of contact areas, are opposite one another. Respective contact areas that are directly opposite one another are connected to one another by first wiring arrangements. Second wiring arrangements run from the outer edges of the semiconductor chips, which are directly followed by no further semiconductor chips, to external contacts on the multichip module, which are arranged particularly on a top side of the support medium.

In accordance with an embodiment of the invention, electronic devices comprising a plurality of semiconductor chips, particularly to the same specification, include first semiconductor chips and second semiconductor chips, the second semiconductor chips having a mirror-image symmetrical arrangement of contact areas in relation to the contact areas of the first semiconductor chip, arranged alternately next to and/or behind one another. In this embodiment, the semiconductor chip edges that are opposite one another always have matching arrangements of contact areas. This results in significantly reduced wiring complexity in comparison with multichip modules which use just one variant of semiconductor chips.

In particular, the invention is based upon the insight that opposite edges of semiconductor chips can have a respectively identical arrangement of contact areas only if the contact areas of the first one of the semiconductor chips which are opposite one another are arranged in mirror-inverted fashion with respect to the contact areas of the second semiconductor chip.

Such a multichip module based on the invention results in a short and effective wiring arrangement among the individual semiconductor chips, with it being possible to avoid long line runs which cross one another and reduce or eliminate the need to provide vias. This is advantageous particularly in the case of wide buses. A bus, as used herein, refers to a multiplicity of lines.

Multichip modules based on the invention can be produced using any conceivable chip-to-chip connection types. The inventive arrangement of semiconductor chips can also be implemented advantageously using conventional printed circuit boards and packaged components or chips arranged thereon.

In accordance with a first embodiment of the invention, the number of first and second semiconductor chips is the same. The first and second semiconductor chips are arranged alternately next to one another and/or behind one another in one plane on or in the support medium and can form an essentially checkerboard-like pattern. In this embodiment, this essentially checkerboard-like pattern can be in rectangular or square form or, alternatively, can have an irregular profile of outer edges. It is sufficient, in this embodiment, for precisely one version of first semiconductor chips and precisely one further version of second semiconductor chips to be used. A checkerboard-like pattern of first and second semiconductor chips may easily be achieved if appropriate by rotating the semiconductor chips.

When designing the first and second semiconductor chips, or when planning a multichip module based on the invention, it is necessary to remember which edges of the first and second semiconductor chips form the outer edge of the checkerboard-like pattern. These outer edges are the location which is preferable to arrange the contact areas for the external communication, while the remaining edges of the semiconductor chips are best provided with contact areas for the internal communication. In an embodiment using ball grid arrays or BGAs, this difficulty does not arise, because in this embodiment the external contacts can be inside and the internal contacts can be outside.

In an embodiment of the invention, not only the contact areas of the second semiconductor chips but also all devices, particularly active devices, and also all internal line runs in the second semiconductor chips are designed to be at least partly or even fully mirror-inverted with respect to the first semiconductor chips. The result is a particularly simple and inexpensive fabrication of the semiconductor chips, because the intermediate masks or reticules used for fabricating the semiconductor chips can be used for both versions of the semiconductor chips or easily adapted such that they can be used to produce both second and first semiconductor chips in respectively matching number. In this embodiment, first and second semiconductor chips can be produced inexpensively using a single mask set.

The supply lines and/or the grounding lines of the semiconductor chips can also be arranged in mirror invariant form. For such supply and/or grounding lines, it is possible to provide wirebonds, known as downbonds, onto the mounting substrate, for example in the interspaces between the individual semiconductor chips of the multichip module.

When the contact areas of the semiconductor chips are used, and when care is taken to ensure that the arrangement of the supply lines is mirror invariant, it is also possible to transfer the test technology from the first semiconductor chip to the second semiconductor chip by redesignating the tester channels.

In one embodiment of the invention, the multichip module is produced using bonding technology. The support medium is in the form of a circuit substrate which has contact pads on its first top side which are connected, particularly via through contacts, to external contacts arranged on the second top side of the circuit substrate. The passive reverse sides of the semiconductor chips are put onto the first top side of the circuit substrate, particularly bonded using a conductive adhesive. The first wiring arrangements are in the form of first bonding connections. Portions of the second wiring arrangements are formed by second bonding connections, which connect the contact areas to the contact pads. The entire multichip module is encased in a plastic compound, particularly in an epoxy resin.

In a further embodiment of the invention, the multichip module is produced using flip chip technology. The multichip module comprises as support medium a primary board whose first top side facing the semiconductor chips holds metal wiring arrangements in at least one rewiring layer. These metal wiring arrangements are connected, particularly by through contacts, to external contacts arranged on the second top side of the primary board. The semiconductor chips are connected to these metal wiring arrangements by flip chip contacts. A plastic compound encapsulates the semiconductor chips and also the first top side of the primary board.

In another embodiment of the inventive multichip module, a direct rewiring layer is provided on the semiconductor chips, and the support medium is formed by a plastic compound which encloses the passive reverse sides and the lateral faces of the semiconductor chips. A patterned insulating layer comprising polyimide (PI) or benzocyclobutene (BCB), in particular, can extend over the active top sides of the semiconductor chips. This insulating layer leaves the contact areas of the semiconductor chips free, so that rewiring arrangements on one or more rewiring layers can make contact with the contact areas. The rewiring arrangements connect contact areas to adjacent contact areas and/or to external contacts. The external contacts are situated on the insulating layer, either above the active top sides of the semiconductor chips or above the regions of the plastic compound which are situated between or next to the semiconductor chips. The rewiring arrangements run at least partly via regions of the insulating layer.

In a further embodiment of the inventive multichip module, the passive reverse side of the semiconductor chips is preferably bonded using a conductive adhesive layer and is put onto a circuit carrier. The wiring arrangements are situated in at least one patterned rewiring layer which extends over the active top sides of the semiconductor chips and over the intermediate or adjacent regions of the top side of the circuit carrier. The level difference between the active top side of the semiconductor chips and the top side of the circuit carrier allow the rewiring layer to be in corrugated form. The patterned rewiring layer has external contact areas particularly in edge regions of the multichip module which hold the external contacts. To allow simple connection of the inventive multichip module to further devices, the top sides of the external contacts project upward over the level of the active top sides of the semiconductor chips and are situated at a common level.

In this embodiment of the invention, the support medium used may advantageously be a very stable circuit carrier made of plastic or made of metal, which improves the stability and useful life of the multichip modules. When a metal circuit carrier is provided, it is advantageous to arrange a patterned insulating layer below the rewiring layer and resting on the top side of the circuit carrier. This insulating layer extends at least over the regions of the top side of the circuit carrier which are not covered by the semiconductor chips. In production, it is not always possible for the regions of the patterned insulating layer to end flush with the lateral faces of the semiconductor chips. Rather, negligibly small interspaces may be produced there.

If there is a level difference between the active top sides of the semiconductor chips and the surface of the circuit carrier or the surface of the insulating layer, it is advantageous to provide transitional points made of rubber-elastic material, particularly made of an elastomer, adjacent to the semiconductor chips. In this case, these transitional points made of rubber-elastic material may be in the form of a second insulating layer. The rewiring arrangements of the rewiring layer rest on this rubber-elastic material and are routed from the active top side of the semiconductor chip to the top side of the circuit carrier or to the top side of the insulating layer, avoiding kinks. By providing such additional transitional points, a robust and reliable wiring arrangement is ensured.

If the layer thickness of the insulating layer (or, if two stacked insulating layers are provided, the layer thickness of the two insulating layers) is greater than or equal to the sum of the height of the semiconductor chips and the layer thickness of the adhesive layer, the wiring arrangements in the rewiring layer are essentially planar in form. This results in an even more reliable and more robust wiring arrangement which may be in the form of a thin film circuit, in particular, and multilayered.

The semiconductor chip arrangement described above and illustrated inFIGS. 1 and 2(as described below) may also be produced mutatis mutandis on a plastic printed circuit board having a plurality of circuit components arranged thereon whose functions are largely identical. In this context, the circuit components may be of any type and, by way of example, may be in the form of semiconductor chips or ICs in one or more ball grid arrays or flat conductor frame based packages. The circuit components can be put onto the printed circuit boards using any conceivable methods, for example by bonding using insulating or conductive adhesive or by soldering. In this case, the circuit components are divided into first and second circuit components. The second circuit components have an at least partly or even fully mirror-inverted arrangement of contact areas or contact pads with respect to the first circuit components. The contact between the first and second circuit components and also between said components and the conductor tracks on the printed circuit board can be made by wires or by making direct contact between the contact areas of the semiconductor chips or the external contact areas of the circuit components and the rewiring layers. Largely crossing-free and reliable contact is obtained which can be produced with little wiring complexity and hence easily and inexpensively.

The invention also relates to an electronic device which has one or more semiconductor chips whose passive reverse side is put onto the top side of a circuit carrier made of metal or made of an alloy using an insulating or conductive adhesive layer. These semiconductor chips are thin-ground, which means that they have a relatively small height of less than 150 μm. Arranged next to and/or between the semiconductor chips there is a photopatterned insulating layer, particularly made of cardo, made of benzocyclobutene or made of polyimide, which extends over the top side of the circuit carrier and leaves free the regions of the semiconductor chips in each case and also the saw channels. As used herein, saw channels refer to those regions between the devices in which the electronic devices are later sawn apart. Arranged between the lateral faces of the semiconductor chips and the photopatterned insulating layer there are trenches whose dimensions are relatively small on account of production and which have a width of less than 100 μm, for example, and are filled with an insulating material at the top.

In accordance with the invention, the layer thickness of the photopatterned insulating layer corresponds roughly to the sum of the height of the thin-ground semiconductor chips and the layer thickness of the adhesive layer arranged below the semiconductor chips. Line paths in at least one rewiring layer run on the photopatterned insulating layer and/or on the insulating material of the trenches and/or on the passivation layer of the active top side of the semiconductor chips and/or on the saw channel. These line paths connect the contact areas of the semiconductor chips and/or the external contact areas and/or the support and hence possibly the chip reverse sides to one another. In this arrangement, the external contact areas are preferably put on the photopattemed insulating layer and bear external contacts, which may be rigid or flexible in form.

The inventive design of the electronic device ensures that the line paths in the rewiring layer or in the rewiring layers respectively run in one plane and are respectively very stable in form.

The circuit carrier may advantageously be chosen such that its coefficient of expansion corresponds roughly to the coefficient of expansion of the printed circuit board on which the electronic device is later mounted. Such coefficients of thermal expansion are preferably 11.3 to 16.6 ppm/° K. In this case, suitable circuit carrier materials are, in particular, iron/chromium/nickel alloys, whose coefficients of thermal expansion between 11.3-16.6 ppm/° K can be matched to the coefficient of expansion of a higher printed circuit board using different proportions of iron, chromium and nickel. Breaks, cracks and other damage which may arise during temperature fluctuations or heating on account of different coefficients of thermal expansion are reliably prevented thereby.

In accordance with one embodiment of the invention, the insulating material of the trenches has the material of the insulating adhesive layer which is arranged below the semiconductor chip or below the semiconductor chips. Such an electronic device can be fabricated very inexpensively, especially since the trenches can be filled with insulating adhesive at the same time as the semiconductor chips are inserted into the free regions of the photopatterned insulating layer.

In accordance with a further embodiment of the invention, the insulating material of the trenches comprises benzocyclobutene, polyimide or cardo, such that the semiconductor chip can also be bonded in electrically conductive form and the chip reverse side is thus grounded. If the insulating material of the trenches differs from the material of the photopatterned insulating layer, the trenches and their adjacent regions of the photopatterned insulating layer can be distinguished particularly clearly in the electronic device. Even if the insulating material of the trenches and of the photopatterned insulating layer is the same, it is possible to establish a boundary layer between the edge regions of the photopatterned insulating layer and the trenches.

With an electronic device of this type, the height of the insulating material in the trenches can be matched very accurately to the layer thickness of the photopatterned insulating layer and/or to the height of the semiconductor chip and also to the layer thickness of the adhesive layer arranged below the semiconductor chips. Typically, this matching is performed as part of the spin coating method.

The invention also relates to a method for fabricating electronic devices. In this case, a disk-like or rectangular circuit carrier, particularly made of metal, e.g. made of an alloy as already described above, is first fabricated.

Semiconductor chips are then provided and are thin-ground to a height of less than 150 μm. This is achieved by a technique of “dicing before grinding”, for example. The top side of these semiconductor chips is preferably provided with a photoimide passivation layer.

An insulating layer is then applied to one surface of the circuit carrier. This application can be performed using a spin coating method, in which uniform and continuous coating of the surface of the circuit carrier can be achieved with a smooth and even nature of the surface. Using a suitable photoimide, it is possible to achieve relatively large layer thicknesses for the insulating layer in the region of up to 150 μm. In this case, cardo can be used to achieve layer thicknesses of up to 150 μm, polyimide can be used to achieve layer thicknesses of up to 30 μm and benzocyclobutene can be used to achieve layer thicknesses of up to 50 μm. In accordance with the invention, the layer thickness of the insulating layer to be applied is set such that it corresponds roughly to the sum of the height of the thin-ground semiconductor chip(s) and the layer thickness of the adhesive layer which is to be put onto the circuit carrier in order to mount the semiconductor chips. For example, such adhesive layers can include a layer thickness of 20 μm.

The insulating layer is then photopatterned such that depressions are produced in the insulating layer or free regions are produced on the circuit carrier for the semiconductor chips which are to be put on and for the saw channels. In practice, the free regions are frequently of only slightly larger design than the base area of the semiconductor chips.

The adhesive layer is then used to put or insert the reverse side of the thin-ground semiconductor chips onto the top side of the circuit carrier in coplanar fashion, specifically into the insulating layer's free regions produced by the photopatteming. In this case, an insulating adhesive is recommended for the adhesive layer if said adhesive is intended to fill the trenches completely.

The resultant trenches (which have relatively small dimensions on account of production) between the lateral faces of the semiconductor chips and the photopatterned insulating layer are then (or even when the semiconductor chips are put on) filled with an insulating material, which means that an essentially continuous, planar surface of the electronic device is produced. In the subsequent method step, arbitrary line paths in at least one rewiring layer are put onto this surface and can connect the contact areas of the semiconductor chips to one another, to external contact areas and to the support. In principle, any number of rewiring layers can be put on in this method step.

Finally, external contacts are put onto the external contact areas. The inventive device is suitable for putting on all conceivable solid, rigid or flexible, elastic external contacts, as described in DE 100 16 132 A1, for example. It is also possible to use any combinations or hybrid forms of such external contacts.

It is advantageous if the external contacts are not put on over the semiconductor chips, but rather, as a better measure, on the regions of the insulating layer which are situated between or next to the semiconductor chips. This is because the semiconductor chips have a different coefficient of expansion than the printed circuit board to which they are connected via the external contacts, which can result in damage to the external contacts or to the electrical device. If the external contacts are fitted over the semiconductor chips, it is necessary to ensure that the external contacts are not arranged too far away from the center of gravity of the semiconductor chip, in order to prevent damage.

Finally, the circuit carrier is sawed up into individual multichip modules in the saw channel by the respective outer edges of the multichip module positions.

This method can be used to process semiconductor chips very reliably, in a flat and space-saving form, to produce electronic devices. The inventive method also allows the use of particularly robust circuit carriers made of metal or made of alloys, which increases the stability of the electronic devices fabricated in accordance with the invention.

In accordance with an embodiment of this method, the top side of the semiconductor chips is situated at the same level as the top sides of the insulating layer, which ensures that the line paths in the rewiring layer or in the rewiring layers do not need to overcome a level difference. Rather, the line paths run essentially horizontally, which achieves a particularly reliable and stable wiring arrangement. This makes it possible to implement a multilayer feature very advantageously.

In line with a first particularly reliable variant of the method described, the trenches between the lateral faces of the semiconductor chips and the photopatterned insulating layer are filled by putting on and photopatterning a further insulating layer, which allows the use of conductive adhesives. In this case, the photopatterning ensures that the contact areas of the semiconductor chips remain freely accessible.

This further insulating layer likewise has a photoimide, particularly polyimide, benzocyclobutene or cardo and may likewise be applied to the electronic device using a spin coating method.

In accordance with a second embodiment of the method of the invention, the trenches between the lateral faces of the semiconductor chips and the photopatterned insulating layer are filled by the, in particular insulating, adhesive in capillary fashion. The quantity of adhesive which is used for putting each semiconductor chip onto the circuit carrier is proportioned such that the sum of the volume of the quantity of adhesive and the volume of the semiconductor chip corresponds roughly to the volume of a respective free region of the photopattemed insulating layer. In practice, a slight excess is used.

The adhesive fills the trenches and ensures that the top side of the electronic device is in essentially planar and continuous form. An additional method step for closing the trenches can thus be saved to the benefit of cost.

The methods described above for fabricating electronic devices may also be used to fabricate a multichip module having an arrangement of first and second semiconductor chips as described above. In this case, the first and second semiconductor chips are first thin-ground to a height of less than 150 μm and are then put into free regions of the photopatterned insulating layer such that those of their edges which respectively have an at least partly matching arrangement of contact areas are opposite one another. When the rewiring layer or the rewiring layers are put on, the line paths are designed such that respectively opposite contact areas are connected to one another and also the external contacts are connected to the contact areas of the semiconductor chip(s) and such that the support is thus grounded.

As a result, arbitrary rewiring layers can be put on and the rewiring complexity can be significantly reduced. It is often possible to connect the entire electronic device just using one wiring layer. In this case, it is possible to dispense with the provision of a second wiring layer so as to save cost.

The above and still further objects, features and advantages of the present invention will become apparent upon consideration of the following detailed description of specific embodiments thereof, particularly when taken in conjunction with the accompanying drawings where like numerals designate like components.

DETAILED DESCRIPTION

FIG. 1shows a plan view of a semiconductor chip arrangement1with semiconductor chips arranged in rows and in columns, where the active top sides of the semiconductor chips are shown.

The following terms “next to one another”, “behind one another”, “above one another” and “on one another”, as used in relation toFIGS. 1 and 2, are standardized according to an axis system with the coordinate axes x, y and z as shown next to the semiconductor chip arrangement1inFIG. 1. In this context, the term “next to one another” is used with reference to the x axis, the term “behind one another” is used with reference to the y axis and the term “above one another” and “on one another” are used with reference to the z axis.

The semiconductor chip arrangement1ofFIG. 1is designed as a square 4×4 matrix. However, and as also shown inFIG. 1, it is noted that semiconductor chip arrangements based on the invention may also be in the form of 2×1, 2×2 or 3×3 matrices or in the form of such arrangements of arbitrary size. Generally, the size of the inventive semiconductor chip arrangement can be described by xij, where i is defined as i=1, . . . , n and j as a function of i is defined as j(i)=1, . . . , mi.

The semiconductor chip arrangement1comprises 16 semiconductor chips which are divided into eight first semiconductor chips2and into eight second semiconductor chips3. The first semiconductor chips2and the second semiconductor chips3are arranged alternately next to and behind one another, resulting in a checkerboard-like pattern. First semiconductor chips2respectively form the left-hand front and the right-hand rear corners of the semiconductor chip arrangement1. Second semiconductor chips3respectively form the left-hand rear and the right-hand front corners of the semiconductor chip arrangement1.

The circular, oval, rectangular and rhombic symbols clarify the geometry and the mirroring of the first semiconductor chips2and of the second semiconductor chips3. For this purpose,FIG. 1also shows the semiconductor chip corners A, B, C and D of the semiconductor chips2,3.

Upon considering the order of the semiconductor chip corners A, B, C and D and the circular, oval, rectangular and rhombic symbols, it becomes clear that the first semiconductor chips2have a clockwise order A-B-C-D and the second semiconductor chips3have an anticlockwise arrangement D-C-B-A of the semiconductor chip corners. This means that respective identical edges of the first semiconductor chips2and of the second semiconductor chips3, which edges have a mirror-image symmetrical arrangement of contact areas, are opposite one another.

The semiconductor chips2,3arranged in rows2and4of the semiconductor chip arrangement1correspond entirely to the semiconductor chips2,3arranged in rows1and3, with the semiconductor chips2,3arranged in rows2and4respectively being arranged so as to be rotated through 180° in the x-y plane.

The semiconductor chip arrangement1ensures that the respectively opposite edges of the first semiconductor chips2and of the second semiconductor chips3respectively match. These respectively matching edges of the semiconductor chips2,3are connected by means of buses4, which are shown by arrows inFIG. 1. The respectively matching arrangement of contact areas situated on opposite edges ensures that the wiring arrangements of the buses4can be of very short proportions and that crossings, vias and long runs of wiring arrangements are avoided.

Another striking feature of the semiconductor arrangement1is that its outer edges are respectively formed by the edges A-B and also B-C of the semiconductor chips2,3. The edges A-D and C-D form respective internal edges of the semiconductor chip arrangement1. Accordingly, when designing the semiconductor chips2,3it should be remembered that contact areas for external communication are best arranged at the edges A-B and B-C and that contact areas for internal communication in the semiconductor chips2,3are predominantly situated at the edges A-D and C-D.

In semiconductor chip arrangements with other dimensions, the contact areas for external communication and for internal communication may also be situated at other edges, as revealed by a consideration of the 2×1 matrix shown inFIG. 1, for example, in which the edges A-B, B-C and C-D are situated on the outside and only the edges A-D are situated on the inside.

A sectional line Q-Q runs transversely through the first array of semiconductor chips2,3in the semiconductor chip arrangement1. The subsequentFIGS. 3-7depict cross-sectional views in which the semiconductor chip arrangement1is shown along this sectional line Q-Q viewed from behind.

FIG. 2shows a schematic illustration of a plan view of a first semiconductor chip wiring arrangement11and of a second semiconductor chip wiring arrangement12in an enlarged 2×2 detail from the semiconductor chip arrangement1. This 2×2 detail is formed by the middle four semiconductor chips2,3in the top two rows of the semiconductor chip arrangement1.

The first semiconductor chip wiring arrangement11may be used for bonded semiconductor chips or for leadframe or flat conductor frame based devices, particularly for quad flat packages, for example.

The first semiconductor chip wiring arrangement11shows evenly arranged contact areas A1-A16at the respective edges of the active top sides of the semiconductor chips2,3, with each edge having five contact areas A1-A5, A5-A9, A9-A13and A13-A1situated at it. The contact areas A1-A16are arranged clockwise in the case of the first semiconductor chips2and, in the case of the second semiconductor chips3, are arranged anticlockwise at the edges of the active top sides. The contact areas A5-A13arranged at respectively opposite edges are respectively connected to one another by first wiring arrangements110.

The second semiconductor chip wiring arrangement12is suitable, by way of example, for implementation using semiconductor chips in flip chip technology and using ball grid arrays. The second semiconductor chip wiring arrangement12is an implementation of the inventive wiring arrangement in flip chip technology. The implementation of the inventive wiring arrangement as a ball grid array differs only slightly from the second semiconductor chip wiring arrangement12described inFIG. 2.

The second semiconductor chip wiring arrangement12shows contact areas A1-A5, B1-B5, C1-C5, D1-D5and E1-E5which are distributed inFIG. 2in a 5×5 matrix over the active top sides of the semiconductor chips2,3. In this case, the contact areas A1-A5, B1-B5, C1-C5, D1-D5and E1-E5of the second semiconductor chips3are arranged in mirror-image symmetrical form with respect to the contact areas A1-A5, B1-B5, C1-C5, D1-D5and E1-E5of the first semiconductor chips2. In the case of the second semiconductor chip wiring arrangement12, not only the directly opposite contact areas B5, C5, D5, E2, E3, E4and E5at the edges of the semiconductor chips2,3but also the contact areas B4, C4, D2, D3and D4arranged in the rows or columns which are respectively next to or behind them are connected to one another by means of second wiring arrangements120.

FIG. 3shows a first multichip module5, fabricated using bonding technology, with the semiconductor chip arrangement1in cross section Q-Q. The arrangement of the contact areas A1-A16of the first multichip module5corresponds to the illustration of the first semiconductor chip wiring arrangement11inFIG. 2.

FIG. 3likewise shows an axis system which is used to standardize the use of the terms “next to one another”, “behind one another”, “on one another” and “above one another”. Specifically, the term “next to one another” is used with reference to the x axis, the term “behind one another” is used with reference to the y axis and the terms “on one another” and “above one another” are used with reference to the z axis. The logical use of these terms relates to the subsequentFIGS. 3-7.

The first multichip module5comprises a circuit substrate51which comprises laminate, particularly FR/BT IV, for example. The passive reverse sides of the semiconductor chips2,3are put, particularly bonded, onto the top side of this circuit substrate51. The illustration of the adhesive layer between the passive reverse sides of the semiconductor chips2,3, which are often connected to ground, and the illustration of the top side of the circuit substrate51have been omitted inFIG. 3.

The edges of the circuit substrate51have first through contacts53made of metal which extend from contact pads52on the top side of the circuit substrate51downward through the circuit substrate51. At the underside of the circuit substrate51, the first through contacts53are adjoined by humped first external contacts54which can be used to connect the first multichip module5to other electronic devices.

The illustration inFIG. 3gives a particularly good view of the contact areas A1and A5on the active top sides of the semiconductor chips2,3. The wiring arrangement of the contact areas below one another and also of the contact areas with the contact pads52on the circuit substrate51are produced using bonding technology in the case of the first multichip module5. In this context, very short first bonding connections55are provided which respectively connect the contact areas of adjacent first semiconductor chips2and second semiconductor chips3to one another. In this case,FIG. 3shows the contact areas A1and A5by way of example. In addition, second bonding connections56are provided which connect contact areas situated at the outer edges of the semiconductor chip arrangement1to the contact pads52of the circuit substrate51and thus allow external contact to be made with all of the semiconductor chips2,3in the first multichip module5.FIG. 3shows the second bonding connections56from the contact areas A1to the contact pads52.

The first multichip module5is provided with a first plastic encapsulation57such that the semiconductor chips2,3, the bonding connections55,56and the contact pads52are totally encased by the plastic compound.

FIG. 4shows a second multichip module6, fabricated using flip chip technology, with the semiconductor chip arrangement1in cross section Q-Q. The arrangement of the contact areas A1-E5in the second multichip module6corresponds to the illustration of the second semiconductor chip wiring arrangement12inFIG. 2.

The second multichip module6comprises a primary board61which comprises plastic. By the edges of the primary board61there are conductive, particularly metal, second through contacts64running through the primary board61. These second through contacts64are adjoined at the top side of the primary board61by humped second external contacts65.

On the underside of the primary board61, metal wiring arrangements62arranged in a rewiring plane lie on the primary board61. In this case, the metal wiring arrangements62are connected to the second through contacts64and serve to make contact between the semiconductor chips2,3and between the semiconductor chips and the outside. The metal wiring arrangements62do not have to be in one rewiring plane as shown inFIG. 4. There may also be a plurality of rewiring planes arranged above one another.

The semiconductor chips2,3are arranged below the primary board61and have their active top sides oriented toward the underside of the primary board61. Flip chip contacts63are used to connect the contact areas A1-E5to the metal wiring arrangements62. The semiconductor chips2and3, the metal wiring arrangements62and the flip chip contacts63are optionally totally encased by a second plastic encapsulation66.

The metal wiring arrangements62are divided into metal wiring arrangements62which connect respectively opposite contact areas to one another and into metal wiring arrangements62which route the other contact areas situated on the semiconductor chip arrangement1to the second through contacts64.FIG. 4shows those metal wiring arrangements62which connect the opposite contact areas A1and A5to one another and which connect the contact areas A1to the second through contacts64. The metal wiring arrangements62are in very short form and are simple to implement, especially since the respective contact areas to be connected on the semiconductor chips2,3are opposite one another.

The inventive use of photopattemed wiring provides the beneficial result that the second external contacts65may be arranged both at the edges and centrally, particularly above the central regions of the semiconductor chips2,3. This results in a particularly space-saving form of the second multichip module6.

FIG. 5shows a third multichip module7with the semiconductor chip arrangement1in cross section Q-Q. The arrangement of the contact areas A1-A16of the third multichip module7corresponds to the illustration of the first semiconductor chip wiring arrangement11inFIG. 2. The third multichip module7, which is also called a universal package, has electrical contact made with it by precisely one direct rewiring layer. For other multichip modules (not shown here), there may also be rewiring using a plurality of rewiring layers.

InFIG. 5, the semiconductor chips2,3are shown with their active top sides oriented toward the top of the module. The passive reverse sides and also the lateral faces, but not the active top sides of the semiconductor chips2,3, are surrounded by a plastic compound, particularly by an epoxy resin, which forms a plastic support71for the semiconductor chips2,3. In this case, the plastic support71is in a form such that its top side is situated between and next to the semiconductor chips2,3at the same level as the active top sides of the semiconductor chips2,3or slightly higher than the active top sides of the semiconductor chips2,3.

The top side of the semiconductor chips2,3includes a patterned polyimide layer72that leaves free only the contact areas A1-A16on the active top sides of the semiconductor chips2,3. Working multichip modules may also be produced without a patterned polyimide layer72of this type. The polyimide layer72shown inFIG. 5may also be photopatterned such that it extends only over the active top sides of the semiconductor chips2,3and leaves free the regions of the plastic support71which are situated between or next to the semiconductor chips2,3.

In this embodiment, first rewiring arrangements73and second rewiring arrangements74in the rewiring layer are put onto the patterned polyimide layer72. The first rewiring arrangements73connect the individual semiconductor chips2,3to one another. The second rewiring arrangements74connect the contact areas situated at the edge of the semiconductor chip arrangement1to third external contacts75, which project upward and are supported on the second rewiring arrangements74. In this embodiment of the invention, the first and second rewiring arrangements73,74run in essentially planar form and may be of multilayer design.

The inventive semiconductor chip arrangement1and the very short and easily produced first and second rewiring arrangements73,74which are dependent thereon allow all of the rewiring arrangements73,74in the third multichip module7to be produced in a single rewiring layer. This means that such multichip modules can be produced more quickly and with greater cost savings.

FIG. 6shows a fourth multichip module7bwith the semiconductor chip arrangement1in cross section Q-Q. The arrangement of the contact areas A1-A6in the fourth multichip module7bcorresponds to the illustration of the first semiconductor chip wiring arrangement11inFIG. 2.

In many respects, the fourth multichip module7bcorresponds to the third multichip module7fromFIG. 5, with the semiconductor chips2,3not being surrounded by a plastic support71but rather having their passive reverse sides put or bonded onto a thermally and mechanically stable and even support, in the exemplary embodiment onto a support plate76made of metal or made of silicon. The semiconductor chips2,3preferably have a height of less than 150 μm.

The support plate76has a photoimide layer77disposed thereon which encloses the sides of the semiconductor chips2,3and supports the patterned polyimide layer72. This photoimide layer77has a photopatternable insulator, for example CARDU. Two insulating layers are thus arranged above one another, namely the patterned polyimide layer72and the photoimide layer77. The height of these two layers72,77should altogether be at least as much as the height of the semiconductor chips2,3and the adhesive layer (not shown) arranged below them.

FIG. 7shows a fifth multichip module8with the semiconductor chip arrangement1in cross section Q-Q. The arrangement of the contact areas A1-A16in the fifth multichip module8corresponds to the illustration of the first semiconductor chip wiring arrangement11inFIG. 2.

The fifth multichip module8is constructed on a first circuit carrier81arranged right at the bottom, which comprises metal in particular. The passive reverse side of the semiconductor chips2,3is mounted on the top side of the first circuit carrier81. This mounting is implemented by a patterned first adhesive layer82inFIG. 5. Between the semiconductor chips2,3and in the edge regions of the fourth multichip module8, there is a first photopatterned insulating layer83on the top side of the first circuit carrier81. InFIG. 5, this photopatterned first insulating layer83is shown such that it ends flush with the lateral faces of the semiconductor chips2,3. The first photopatterned insulating layer83shown in idealized form inFIG. 7is preferably designed such that it does not run right up to the lateral faces of the semiconductor chips2,3.

To ensure that a level transition from the active top side of the semiconductor chips2,3to the first photopatterned insulating layer83is not abrupt but rather continuous, rubber-elastic transitional points84produced from an elastomer, in particular, are provided on the edge faces of the semiconductor chips2,3.

The regions of the first photopatterned insulating layer83that are not covered by the transitional points84and also the transitional points84themselves have third and fourth line paths85,86made of metal running on them. In this case, the third line paths85connect opposite contact areas of the first and second semiconductor chips2,3. The fourth line paths86connect the contact areas situated at the edges of the semiconductor chip arrangement1to fourth external contacts87which are supported on external contact areas88arranged in edge regions of the fourth multichip module8. In this arrangement, these fourth external contacts87protrude upward clearly over the active top sides of the semiconductor chips2,3.

FIG. 8shows an electronic device9in cross section. The electronic device9comprises a second circuit carrier91made of an iron/chromium/nickel alloy whose surface has the passive reverse sides of a first thin-ground semiconductor chip92and of a second thin-ground semiconductor chip93put on it using second adhesive layers95. The thin-ground semiconductor chips92,93have a height of 120 μm and the second adhesive layers95have a layer thickness of 20 μm. The active top side of the thin-ground semiconductor chips92,93includes contact areas94and regions of a photoimide passivation layer (not shown) provided thereon (alternatively, the entire surface of the electronic device9can be passivated).

Arranged between and next to the thin-ground semiconductor chips92,93there is a second photopatterned insulating layer96that ends flush with the second circuit carrier91on the left and right sides, respectively. The second photopatterned insulating layer96comprises cardo and in the present exemplary embodiment has a layer thickness of 140 μm. Formed between the edge faces of the thin-ground semiconductor chips92,93and the respective edge regions of the second photopatte med insulating layer96which are arranged next to these there are trenches97, which in the present exemplary embodiment each have a width of 50 μm and extend downward as far as the surface of the second circuit carrier91.

In the exemplary embodiment shown inFIG. 8, the trenches97are filled completely using a filling material98. The surfaces of the second photopattemed insulating layer96and of the filling material98of the trenches97are situated on one plane with the active top sides of the thin-ground semiconductor chips92,93. In this embodiment, the filling material98filling the trenches97may also have slight bulges toward the top.

In the exemplary embodiment shown inFIG. 8, the filling material98is formed from a photoimide.

In a modification of the embodiment ofFIG. 8, the filling material98for the trenches97may also be the insulating adhesive of the second adhesive layers95, which fills the trenches97when the thin-ground semiconductor chips92,93are inserted.

The surfaces of the filling material98for the trenches97and the surfaces of the second photopatterned insulating layer96have fifth line paths99running on them which connect the contact areas94of the thin-ground semiconductor chips92,93both to one another and to external contacts101which have been connected to external contact areas situated in edge regions of the top side of the second photopatterned insulating layer96. In this embodiment, the fifth line paths99may also run over the active top sides of the thin-ground semiconductor chips92,93, especially since these are provided with the photoimide passivation layer.

When the electronic device9is fabricated, the second circuit carrier91is first provided. Next, the insulating layer96is put onto the second circuit carrier91and photopatterned such that free regions for holding the thin-ground semiconductor chips92,93and also saw channels (not shown inFIG. 8) between the electronic device9and adjacent electronic devices (likewise not shown inFIG. 8) are produced.

The semiconductor chips92,93are first of all thin-ground. This method is known to the person skilled in the art and requires no further explanation here. Next, the thin-ground semiconductor chips92,93are inserted into the free regions of the second photopatterned insulating layer96and at the same time are connected to the second circuit carrier91by the second adhesive layers95. In this case, these adhesive layers95may also be conductive.

Next, a further insulating layer (not shown explicitly inFIG. 8) is put onto the electronic device9and is photopatterned such that only the contacts94and the saw channel remain free and such that the trenches97are filled.

In a variant of the electronic device9which is not shown inFIG. 8, inserting the thin-ground semiconductor chips92,93into the free regions of the second photopatterned insulating layer96involves providing exactly the quantity of insulating adhesive for the adhesive not just to form second adhesive layers95with a layer thickness of 20 μm, which mount the passive reverse side of the thin-ground semiconductor chips92,93on the second circuit carrier91, but for this adhesive also to fill the trenches97fully in capillary fashion.

In a subsequent method step, the fifth line paths99are put on, which can also ground the circuit carrier91via the saw channel. Finally, external contacts101are also put onto the external contact areas100in order to be able to connect the electronic device9to a higher printed circuit board, for example.