Wire bonding method and apparatus for electromagnetic interference shielding

Apparatuses relating generally to a microelectronic package having protection from electromagnetic interference are disclosed. In an apparatus thereof, a platform has an upper surface and a lower surface opposite the upper surface and has a ground plane. A microelectronic device is coupled to the upper surface of the platform. Wire bond wires are coupled to the ground plane with a pitch. The wire bond wires extend away from the upper surface of the platform with upper ends of the wire bond wires extending above an upper surface of the microelectronic device. The wire bond wires are spaced apart from one another to provide a fence-like perimeter to provide an interference shielding cage. A conductive layer is coupled to at least a subset of the upper ends of the wire bond wires for electrical conductivity to provide a conductive shielding layer to cover the interference shielding cage.

FIELD

The following description relates generally to integrated circuits (“ICs”). More particularly, the following description relates generally to wire bonding for electromagnetic interference shielding.

BACKGROUND

Some passive or active microelectronic devices may be shielded from electromagnetic interference (“EMI”), including without limitation radio frequency interference (“RFI”). However, conventional shielding may be complicated to fabricate, too heavy for some mobile applications, too expensive to produce and/or assemble, and/or too large for some low-profile applications. Moreover, some shielding may not be suitable for a stacked die or a stacked package, generally referred to as three-dimensional (“3D”) ICs or “3D ICs.”

DETAILED DESCRIPTION

In the following description, numerous specific details are set forth to provide a more thorough description of the specific examples described herein. It should be apparent, however, to one skilled in the art, that one or more other examples or variations of these examples may be practiced without all the specific details given below. In other instances, well known features have not been described in detail so as not to obscure the description of the examples herein. For ease of illustration, the same number labels are used in different diagrams to refer to the same items; however, in alternative examples the items may be different.

Exemplary apparatus(es) and/or method(s) are described herein. It should be understood that the word “exemplary” is used herein to mean “serving as an example, instance, or illustration.” Any example or feature described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other examples or features.

Interference may be electromagnetic interference (“EMI”), including without limitation radio frequency interference (“RFI”), and/or another electrical and/or magnetic field that would produce undesirable EMI outside of the source generating the field. The following description of interference shielding may be used for EMI or other types of interference. EMI may be emitted from one device to another separate device, and compatibility of a device with respect to such out-of-package or out-of-device EMI emissions may be referred to as electromagnetic compatibility (“EMC”). For a device to have EMC, such a device may be precluded from emitting levels of EM energy sufficient to cause EMI harm in another device in an EMI environment of the EM emitting device. A common EMI emitting device is a mobile phone, and a mobile phone may have an EMC problem with respect to medical devices, which is a reason people are asked to turn-off their mobile phones in hospitals. For purposes of clarity by way of example and not limitation, generally only shielding from EMI is described below in additional detail; however, it shall become apparent from the following description that this shielding may also be used to enhance EMC. Along those lines, it will be appreciated that the following description is applicable to thin profile devices, such as mobile phones, wearables and/or Internet of Things devices, for reducing EM emission therefrom, and in some implementations enhancing EMC.

With the above general understanding borne in mind, various configurations for protection from interference are generally described below.

Along those lines, an apparatus generally relates to protection from electromagnetic (“EM”) interference. In such an apparatus, a platform has an upper surface and a lower surface opposite the upper surface and has a ground plane. A microelectronic device is coupled to the upper surface of the platform. Wire bond wires are coupled to the ground plane. The wire bond wires have a pitch. The wire bond wires extend away from the upper surface of the platform with upper ends of the wire bond wires extending above an upper surface of the microelectronic device. The wire bond wires are spaced apart from one another to provide a fence-like perimeter to provide an interference shielding cage. A conductive layer is coupled to at least a subset of the upper ends of the wire bond wires for electrical conductivity to provide a conductive shielding layer to cover the interference shielding cage. To achieve enhanced suppression of EMI, spacings between each pair of adjacent wire bond wires may be substantially smaller than electrical wavelengths of interest, including without limitation the electrical wavelength of the highest operation frequency of interest. Along those lines, spacing between two adjacent wires can be less than approximately one tenth of the electromagnetic wavelength in a medium. For example, in a microelectronic package with conventional dielectric materials, the spacing between two adjacent wires can be less than 500 microns (“um”) for an operational frequency of approximately 3 GHz, and less than 50 um for an operational frequency of approximately 30 GHz.

In the apparatus in the immediately preceding paragraph, the microelectronic device can be shielded from the interference outside of the interference shielding cage. The microelectronic device can be shielded by the interference shielding cage to reduce spread of the interference generated by the microelectronic device. The interference can be electromagnetic interference. The conductive layer can have an overhang extending beyond the perimeter. At least a subset of the wire bond wires can have gaps therebetween narrower than the pitch of at least the subset of the wire bond wires. The wire bond wires can have a-like shape. The wire bond wires can have a-like shape. The wire bond wires can have a r-like shape. The perimeter can have a shape corresponding to a layout of the microelectronic device. The perimeter can have a contour or non-parallel sides shape. The perimeter can have a circular shape. The microelectronic device can be a first microelectronic device, and the apparatus can further include a second microelectronic device coupled to the platform and located outside of the interference shielding cage. The platform can be selected from a leadframe, a circuit board, a substrate, and a redistribution layer. The wire bond wires having the pitch can be first wire bond wires having a first pitch, the interference shielding cage can be a first interference shielding cage having a first perimeter, and the conductive layer can be a first conductive layer; and the apparatus can further include: second wire bond wires coupled to the ground plane with a second pitch, with the second wire bond wires extending away from the upper surface of the platform with upper ends of the second wire bond wires being above an upper surface of the second microelectronic device and the upper ends of the first wire bond wires; the second wire bond wires can be spaced apart from one another to provide a second fence-like perimeter to provide a second interference shielding cage, with the first perimeter being within the second perimeter; and a second conductive layer can be coupled to at least a subset of the upper ends of the second wire bond wires for electrical conductivity to at least provide a shield cover over the first interference shielding cage and the second interference shielding cage including overlapping the first conductive layer for having the first interference shielding cage within the second interference shielding cage. The wire bond wires having the pitch can be first wire bond wires having a first pitch, and the interference shielding cage can be a first interference shielding cage having a first perimeter; and the apparatus can further include: second wire bond wires coupled to the ground plane with a second pitch, with the second wire bond wires extending away from the upper surface of the platform with upper ends of the second wire bond wires being above an upper surface of the second microelectronic device and at a same level as the upper ends of at least the subset of the first wire bond wires; the second wire bond wires can be spaced apart from one another to provide a second fence-like perimeter to provide a second interference shielding cage with the first perimeter being within the second perimeter; and the conductive layer can be coupled to at least a subset of the upper ends of the second wire bond wires for electrical conductivity to at least provide a shield cover over the second interference shielding cage. The first microelectronic device can be coupled to the second microelectronic device though a gap in the interference shielding cage. The first microelectronic device can be a stronger electromagnetic interference source than the second microelectronic device. The wire bond wires having the pitch can be first wire bond wires having a first pitch, and the interference shielding cage can be a first interference shielding cage having a first perimeter; and the apparatus can further include: second wire bond wires coupled to the ground plane with a second pitch wider than the first pitch to provide a second interference for providing a portion of a second interference shielding cage having less shielding against interference than the first interference shielding cage. The conductive layer can define a ring-like hole therein having a pad therein isolated from a remainder of the conductive layer by the ring-like hole. The conductive layer can be a ground plane. The pad can be a signal pad or a power pad. The wire bond wires having the pitch can be first wire bond wires having a first pitch, and the interference shielding cage can be a first interference shielding cage having a first perimeter; and the apparatus can further include: second wire bond wires coupled to the ground plane with a second pitch with the second wire bond wires extending away from the upper surface of the platform with upper ends of the second wire bond wires being above an upper surface of the second microelectronic device and at a same level as the upper ends of at least the subset of the first wire bond wires; the second wire bond wires can be spaced apart from one another to provide a second fence-like perimeter in combination with a portion of the first wire bond wires to provide a second interference shielding cage with the first perimeter bordering the second perimeter; and the conductive layer can be coupled to at least a subset of the upper ends of the second wire bond wires for electrical conductivity to at least provide a shield cover over the second interference shielding cage.

A method relates generally to protection from EM interference. In such a method, a platform is obtained having an upper surface and a lower surface opposite the upper surface and having a ground plane. A microelectronic device is coupled to the upper surface of the platform. Wire bond wires are bonded to the ground plane, where the wire bond wires have a pitch. The wire bond wires extend away from the upper surface of the platform with upper ends of the wire bond wires being above an upper surface of the microelectronic device. The wire bond wires are spaced apart from one another to provide a fence-like perimeter to provide an interference shielding cage. A molding layer is deposited over the upper surface of the platform. A conductive layer is formed for coupling to at least a subset of the upper ends of the wire bond wires to provide a conductive shielding layer for electrical conductivity to cover the interference shielding cage.

Other features will be recognized from consideration of the description and claims, which follow.

FIG. 1-1is a top-down perspective view illustratively depicting an exemplary microelectronic package100having interference protection.FIG. 1-2is the top-down perspective view illustratively depicting the exemplary microelectronic package100ofFIG. 1-1after the addition of a conductive layer112. With simultaneous reference toFIGS. 1-1 and 1-2, microelectronic package100is further described.

In microelectronic package100, a platform104has an upper surface102and a lower surface106opposite upper surface102. Platform104further includes a ground plane107, which in this example is subsurface with respect to upper surface102, with surface accessible bond pads (not shown in this figure for purposes of clarity and not limitation) coupled to such ground plane107. Platform104may be selected from a leadframe, a circuit board, a redistribution layer, a substrate, or other circuit base.

A microelectronic device105may be coupled to other bond pads (not shown in this figure for purposes of clarity and not limitation) on upper surface102of platform104. Microelectronic device105for example may be an integrated circuit die, such as a resonator for example, or any other microelectronic component that generates EMI noise. Wire bond wires101may be coupled to ground plane107with a pitch108. Wire bond wires101extend away from upper surface102of platform104with upper ends103of wire bond wires101being above an upper surface109of microelectronic device105. For purposes of clarity by way of example and not limitation, wire bond wires101may have a height of approximately 0.4 mm and a diameter of 20 microns, with a pitch of approximately 80 microns. Distance between a wire bond wire101used to provide a perimeter for shielding and a microelectronic device105may be approximately 0.5 mm. An interference shielding cage in accordance therewith may provide approximately 30 to 33 dB of EMI suppression at maximum radiation direction for a frequency in a range of approximately 3.0 to 4.5 GHz with E-field radiation and radiation power both reduced by approximately over 97 percent or higher. By implementing EMI shielding as described herein, applications with operating frequencies of 5 GHz or greater frequencies may be have EMI suppression as described herein, including without limitation EMC enhancement. However, these or other parameter details to provide EMI shielding may be used as may vary from application-to-application.

Wire bond wires101are spaced apart from one another to provide a picket fence-like wall or perimeter110. Such a picket-fence like or bars on a cage-like perimeter of wire bond wires101may be used to provide an interference shielding wall for an interference shielding cage111, such as a bond via array (“BVA”) cage. Interference shielding cage111further includes a conductive layer112having a lower surface. Such lower surface of conductive layer112may be mechanically coupled, such as by applying solder or other eutectic masses to at least a subset, if not all, of upper ends103of wire bond wires101to provide attachment of a conductive shielding layer for electrical conductivity to cover interference shielding cage111. Conductive surface112in this example is a sheet material, which may be used to provide an EMI shield cap or cover of an interference shielding cage111. However, in another implementation, a mesh of material may be deposited for use as a shield cover of an interference shielding cage111.

FIG. 1-3is a cut-away diagram of the top-down perspective view illustratively depicting the exemplary microelectronic package100ofFIG. 1-1after the addition of a molding layer113and a conductive layer112. In this optional implementation, after forming molding layer113over upper surface102and around bases and shafts of wire bond wires101, at least a subset, if not all, of upper ends103of wire bond wires101may be temporarily exposed above an upper surface114of molding layer113. A mold assist film (removed in this figure) may be used in an injection mold for example to have upper ends103available for mechanical or other coupling. In this implementation, upper ends of wire bond wires101do not have to be exposed by back grinding, planarizing, etching back, polishing or otherwise from molding layer113.

Along those lines, conductive layer112may be mechanically coupled as previously described. However, optionally conductive layer112may be formed by spraying, sputtering, printing, painting, ink stamping, or otherwise forming a conductive shielding layer on upper surface114for interconnect with upper ends103. By forming conductive layer112by spraying, sputtering, printing, painting, ink stamping, or otherwise depositing a conductive material, conductive layer112may be selectively applied. Along those lines, a mesh or solid surface, or a combination of part mesh and part solid surface, for conductive layer112may be formed.

For purposes of clarity, conductive layer112is illustratively depicted as extending toward a front edge139of microelectronic package100and covering only a portion of an upper surface114of molding layer113. However, in another implementation, conductive layer112may extend to none, or one or more edges139of microelectronic package100. Along those lines,FIG. 1-4is a block diagram of the top-down perspective view illustratively depicting the exemplary microelectronic package100ofFIG. 1-1after the addition of a molding layer113and a conductive layer112, where conductive layer112covers an upper surface of microelectronic package100.

In this example, there are four edges139to which conductive layer112extends; however, conductive layer112may be formed to cover an upper surface area of any shape of a microelectronic package100. By having conductive layer112overhang or otherwise extend beyond a perimeter110formed by wire bond wires101associated with an interference shielding cage111, EMI shielding may be enhanced over a corresponding interference shielding cage111where conductive layer112does not extend beyond perimeter110formed of wire bond wires101. For minimally effective EMI shielding, such an overhang or extension may be approximately minimally half of the vertical or perpendicular height (“H”) of wire bond wires101. Thus, a perimeter of conductive layer112may be greater than a surface area associated with a perimeter110of wire bond wires101of an interference shielding cage111minimally by ½ H in each direction toward one or more edges139. Though a ½ H overhang can reduce EMI emissions, such as of an evanescent or standing wave, a larger overhang may suppress EMI emission further, as EMI emission may include both radial emission and an evanescent wave. Based on electromagnetic wave theory, only the lowest transverse electric (TE) mode is propagation wave, other higher order modes are evanescent waves that decay to negligible small after propagating distance of perpendicular height H. Thus, an overhang of H can significantly further suppress the EMI radiation. Along those lines, an overhang for extending conductive layer112beyond perimeter110in each direction by approximately H may be used. Thus, conductive layer112may be extended to all edges139of a package part for an overhang of H or greater beyond perimeter110in all directions toward edges139.

In any of the above configurations, microelectronic device105may be shielded from interference outside of interference shielding cage111, such as outside of a perimeter110of wire bond wires101. However, for purposes of clarity by way of example and not limitation, it shall be assumed that during operation microelectronic device105is an EMI generator. Along those lines, microelectronic device105may be shielded by interference shielding cage111, such as by perimeter110of wire bond wires101, to reduce or prevent spread of EMI, namely size of an EM environment, generated by microelectronic device105. For example, interference generated by microelectronic device105without interference shielding cage111may generate an EMI environment affecting EMC. For purposes of clarity by way of example and not limitation, it shall be assumed that microelectronic device105is an RF component. Microelectronic device105may be a stacked die, such as a 3D IC or may be shielded from such a stacked die.

FIGS. 2-1 through 2-7are respective block diagrams of side views illustratively depicting exemplary profiles of wire bond wires101. InFIG. 2-1, wire bond wires101have a generally vertical profile, such as previously described. Along those lines, gaps between such generally vertical profile wire bond wires101may have a generally consistent pitch108, where such wire bond wires101are bonded for example to platform104, and closest spaces or gaps115between such wires moving up from such platform104may be generally a consistent spacing or gapping. Routing wiring, such as signal, power, or ground traces for microelectronic package100may extend through one or more gaps between adjacent wire bond wires101. Thus, wiring layers (not shown) may include routing on upper surface102of platform104without interfering with corresponding EMI shielding, thereby simplifying routing over traditional “can” style EMI shielding mechanisms, which would experience an electrical short if the solid conductive surface contacted surface routing.

ForFIGS. 2-2 through 2-7, the closest spacings of gaps115may be narrower than pitch108. By “pitch”, it is generally meant a predetermined center-to-center spacing between bases of wire bond wires, which may be contrast for example from slant of such wire bond wires. Along those lines, at least a subset, if not all, of wire bond wires101may have gaps115therebetween narrower than a corresponding pitch108of at least a subset of wire bond wires101. Wire bond wires101may have a slash-like or “/” shape or profile, such as inFIGS. 2-2 and 2-6. InFIG. 2-3, wire bond wires101have a squared-off vertical-z-like, or a kinked or rounded shaped profile. Of course, the wires shown by way of example inFIGS. 2-1 through 2-7may have additional bends not shown in the schematic drawings. For instance, the “/” shaped wires may have portions that do not have a straight line profile and instead have slightly more vertical or horizontal portions at either end due to tooling parameters. Thus, the wire may have be considered to have an imaginary axis extending from one end of the wire to the other with portions of the wire bond extending outside of that axis in the x, y, and/or z directions.

InFIGS. 2-4 and 2-5wire bond wires may have a vertical partial four-like shape or profile. Other shapes, such as chevron (“<” or “>” shapes), arc (“(” or “)” shapes), or coil shaped configurations are optional. Even though non-curved angles and/or segments are illustratively depicted, in other implementations, such angles and/or segments may have curves, such as for example a curved-el-like profile shape. Moreover, wire bond wires101may be loops, such as having an open loop omega-like “Ω” shaped profile or a closed loop el-like “l” shaped profile. The wire loops may each be formed on a single pad and may be offset or angled relative to each other in the x and y direction (i.e., in a layout similar to “\\\” when viewed down the z direction) to facilitate a more tightly packed layout than might be possible if the wires in the wire loop extended in the same plane (i.e., in a layout similar to “- - - ” when viewed down the z direction).

FIG. 3-1is the exemplary microelectronic package100though with slash-like shaped wire bond wires101, andFIG. 3-2is the exemplary microelectronic package100though with squared-off vertical-z-like shaped wire bond wires101. Along those lines, pitch, shape, and diameter of wire bond wires101, including without limitation irregularly shaped wire bond wires101, may be used to further reduce EM emissions from a fence-like perimeter, such as perimeter110for example, formed of wire bond wires101. Some of adjacent wire bond wires101may be in contact with each other, and some wires101may not extend to conductive layer112, such as illustrative depicted inFIG. 2-7for purposes of clarity by way of example and not limitation, and these or other options described herein may be selectable by a designer for a given EMI shield design or characteristic.

As above with reference toFIG. 1-1, perimeter110formed by layout of wire bond wires101may have a shape corresponding to a layout of microelectronic device105. However, microelectronic device105may have a layout shape other than that of a square, rectangle or other similar polygon. Moreover, microelectronic device105may have a layout shape of a circle, oval or other curvilinear shape. Shaping fence-like perimeters, such as for example perimeter110and/or below described perimeter120, formed of wire bond wires101to a microelectronic device105layout shape or footprint may be used to provide more compact designs and/or better shielding performance than not contouring fence-like perimeters to such footprint.

FIG. 4-1is a top-down perspective view illustratively depicting an exemplary microelectronic package100having interference protection, as inFIG. 1-1, though with a triangularly shaped microelectronic device105. Correspondingly, perimeter110formed of wire bond wires101may have a corresponding triangular shape. In this example, wire bond wires101have a slash-like profile.FIG. 4-2is a cut-away diagram of the top-down perspective view illustratively depicting the exemplary microelectronic package100ofFIG. 4-1after the addition of a molding layer113and a triangular conductive layer112. Accordingly, more generally, a perimeter may have one or more contoured sides, non-parallel sides and/or non-orthogonal sides in order to follow a layout of an irregularly shaped microelectronic device105.

FIG. 5is a block diagram of the top-down perspective view illustratively depicting the exemplary microelectronic package100after the addition of a molding layer113and a conductive layer112. Circles116generally indicate upper ends of wire bond wires101positioned for providing an oval shaped perimeter110of wire bond wires101, as previously described though for an oval shaped microelectronic device105. Microelectronic devices105as described herein may be passive or active devices. Conductive layer112may have an oval shape as generally indicated by dashed oval112A. However, conductive layer112may overhang an oval shaped perimeter110and need not be contoured like perimeter110. Thus, for example, conductive layer112may extend to edges of a package, as generally indicated by arrow112B. Moreover, in another implementation, conductive layer112may have an oval shape to extend beyond perimeter110, as generally indicated by dashed oval112C.

FIG. 6is a block diagram of a cross-sectional view illustratively depicting an exemplary microelectronic package100with inner and outer interference shielding cages111and121, respectively. In this example, inner interference shielding cage111has therein a microelectronic device105surrounded by a perimeter of wire bond wires101, where location of a conductive layer112is generally indicated with a dashed line bridging such wire bond wires101, such as previously described for example. In this example, conductive layer112of inner interference shielding cage111does not overhang or extend beyond an inner perimeter formed of wire bond wires101.

An outer interference shielding cage121has one or more microelectronic devices117, as well as inner interference shielding cage111, therein. One or more of microelectronic devices117may be taller than microelectronic device105. In other words, an upper surface of such one or more taller microelectronic devices117may be above, though not necessarily overlapping, an upper surface of microelectronic device105.

Microelectronic devices117may be coupled to an upper surface of platform104and may be located outside of inner interference shielding cage111. In this example, inner interference shielding cage111is surrounded by a perimeter of wire bond wires101of outer interference shielding cage121. For outer interference shielding cage121, location of a conductive layer122therefor is generally indicated with a dashed line bridging such wire bond wires101, such as previously described with reference to conductive layer112for example, as well as extending beyond an outer perimeter of wire bond wires101of outer interference shielding cage121.

Having both inner and outer interference shielding cages111and121within a same plot may be used for different types or levels of interference noise, such as EMI and EMC for example, as well as more or less compact and/or complex shielding implementations as described elsewhere herein. Along those lines, an overhang or eave171may extend beyond each side of a perimeter of wire bond wires101of outer interference shielding cage121by approximately a distance H, for H also a vertical height of wire bond wires101used to provide such a perimeter.

FIG. 7-1is a top-down perspective view illustratively depicting an exemplary microelectronic package100having inner and outer interference protection.FIG. 7-2is the top-down perspective view illustratively depicting the exemplary microelectronic package100ofFIG. 7-1after the addition of conductive layer122. With simultaneous reference toFIGS. 1-1 through 7-2, microelectronic package100ofFIGS. 7-1 and 7-2is further described. As much of the above description is applicable to describing microelectronic package100ofFIGS. 7-1 and 7-2, some of such description is not repeated for purposes of clarity and not limitation.

Inner perimeter wire bond wires101may have a pitch108for an inner interference shielding cage111having a conductive layer112. Conductive layer112may not have sufficient room for an overhang. Outer wire bond wires101may be coupled to a ground plane107though with a same or different pitch128with reference to pitch108. Outer wire bond wires101extend away from an upper surface of platform104with upper ends103of outer wire bond wires101being above an uppermost upper surface of microelectronic devices117, as well as above upper ends of inner wire bond wires101and inner conductive layer112.

Outer wire bond wires101may be spaced apart from one another to provide an outer picket fence-like perimeter120to provide an outer interference shielding cage121. Inner perimeter110may be completely within outer perimeter120.

An upper conductive layer122may be coupled to at least a subset of upper ends103of outer wire bond wires101for electrical conductivity to cover inner interference shielding cage111and outer interference shielding cage121, where upper conductive layer122is above and overlapping inner-lower conductive layer112for having inner interference shielding cage111within outer interference shielding cage121. Outer interference shielding cage121may be for EMC shielding, whereas inner interference shielding cage111may be for EMI shielding. Along those lines, conductive layer122may extend beyond perimeter120to provide an overhang171, of at least approximately ½ H in order to enhance EMC, and overhangs greater than ½ H, such as an overhang of at least H may provide more EMI evanescent wave suppression.

Even though a mechanical coupling is illustratively depicted inFIG. 7-2, such coupling of conductive layer122may be after forming another molding layer over molding layer113.FIG. 7-3is a cut-away diagram of the top-down perspective view illustratively depicting the exemplary microelectronic package100ofFIG. 7-1after the addition of a molding layer123and a conductive layer122. In this optional implementation, after forming molding layer123over conductive layer112and molding layer113, at least a subset, if not all, of upper ends103of outer wire bond wires101may be temporarily exposed above an upper surface124of molding layer123. A mold assist film (removed in this figure) may be used in an injection mold for example to have upper ends103of outer wire bond wires101available for mechanical or other coupling.

Along those lines, conductive layer122may be mechanically coupled as previously described. However, optionally conductive layer122may be formed by spraying, sputtering, printing, painting, ink stamping, or otherwise forming a conductive shielding layer on upper surface124for interconnect with upper ends103of outer wire bond wires101. Conductive layer122may provide an overhang171, which may or may not extend to outer edges139of microelectronic package100. Conductive layer122is illustratively depicted as being short of outer edges139in order to more clearly indicate a perimeter of conductive layer122.

FIG. 8is a block diagram of a cross-sectional view illustratively depicting an exemplary microelectronic package100with inner and outer interference shielding cages111and121, respectively. In this example, inner interference shielding cage111has therein a microelectronic device105surrounded by a perimeter of wire bond wires101, where location of a conductive layer122is generally indicated with a dashed line bridging such wire bond wires101. In this example, conductive layer122provides a common cover for both of inner interference shielding cages111and121and also provides an overhang171to extend beyond an outer perimeter formed of wire bond wires101by approximately ½ H.

An outer interference shielding cage121has one or more microelectronic devices117, as well as inner interference shielding cage111, therein. One or more of microelectronic devices117may be taller than microelectronic device105. In other words, an upper surface of such one or more taller microelectronic devices117may be above, though not necessarily overlapping, an upper surface of microelectronic device105.

Microelectronic devices117may be coupled to an upper surface of platform104and may be located outside of a perimeter of inner interference shielding cage111. In this example, inner interference shielding cage111is surrounded by a perimeter of wire bond wires101of outer interference shielding cage121. Location of a conductive layer122is generally indicated with a dashed line bridging wire bond wires101for both inner interference shielding cage111and outer interference shielding cage121, namely being an EMI shielding cover common to both of cages111and121without having a separate cover for inner interference shielding cage111. Conductive layer122extends beyond an outer perimeter of wire bond wires101of outer interference shielding cages121. Having both inner and outer interference shielding cages111and121within a same plot may be used for different types or levels of interference noise, such as EMI and EMC for example, as well as more compact and less complex shielding implementations. Along those lines, an overhang or eave171may extend beyond each side of a perimeter of wire bond wires101of each outer interference shielding cage121by approximately at least a distance ½ H, for H also a vertical height of wire bond wires101used to provide such a perimeter. Effectively, because a common conductive layer122is used for both outer interference shielding cages121and inner interference shielding cage111, common sections172provide overhangs173for EMI shielding, such as for EMI suppression of higher order modes and evanescent waves.

FIG. 9-1is a top-down perspective view illustratively depicting an exemplary microelectronic package100having inner and outer interference protection.FIG. 9-2is the top-down cutaway perspective view illustratively depicting the exemplary microelectronic package100ofFIG. 9-1after the addition of conductive layer122. With simultaneous reference toFIGS. 1-1 through 9-2, microelectronic package100ofFIGS. 9-1 and 9-2is further described. As much of the above description is applicable to describing microelectronic package100ofFIGS. 9-1 and 9-2, some of such description is not repeated for purposes of clarity and not limitation.

Inner perimeter wire bond wires101may have a pitch108for an inner interference shielding cage111having a separate conductive layer112independent of another interference shielding cage or having a common conductive layer122for a common cover with another interference shielding cage. Outer wire bond wires101of outer interference shielding cage121may be coupled to a ground plane107, though with a same or different pitch128with reference to pitch108as inner wire bond wires101of inner interference shielding cage111. Outer wire bond wires101coupled to ground plane107with a pitch128wider than pitch108may be for EMC for providing an outer interference shielding cage121having less shielding against EMI than inner interference shielding cage111. Conductive layer122may have an overhang171extending beyond a perimeter120of outer wire bond wires101for enhancing EMC.

Outer wire bond wires101extend away from an upper surface of platform104with upper ends103of outer wire bond wires101being above an uppermost upper surface of microelectronic devices117, but at a same level as upper ends of at least a subset, if not all, of inner wire bond wires101with no inner conductive layer112.

Outer wire bond wires101may be spaced apart from one another to provide an outer picket fence-like perimeter120to provide an outer interference shielding cage121. Inner perimeter110may be completely within outer perimeter120.

A conductive layer122may be mechanically coupled to at least subsets of upper ends103of both inner and outer wire bond wires101for electrical conductivity to cover inner interference shielding cage111and outer interference shielding cage121, where conductive layer122is above and overlapping inner interference shielding cage111within outer interference shielding cage121. Outer interference shielding cage121may be for EMI and/or EMC shielding, and inner interference shielding cage111may be for EMI shielding, with a single conductive layer122for providing a ceiling for both inner and outer interference shielding cages.

Again, even though a mechanical coupling is illustratively depicted inFIG. 9-2, such coupling of conductive layer122may be after forming another molding layer123over molding layer113, as previously described.

Even though concentric inner and outer perimeters110and120of wire bond wires101has been described for forming inner and outer interference shielding cages111and121, respectively, a microelectronic package100may include multiple types of interference shielding cages in accordance with the description herein.

Along those lines,FIG. 10is a top-down perspective view illustratively depicting an exemplary microelectronic package100having plots for interference shielding cages as inFIG. 1-1and as inFIG. 7-1for example. With simultaneous reference toFIGS. 1-1 through 10, microelectronic package100ofFIG. 10is further described, while much of the above description which is the same is not repeated for purposes of clarity and not limitation.

Though four plots with both one and two interference shielding cages are illustratively depicted, other combinations of plots as described herein may be implemented in other configurations of microelectronic package100. In this configuration, wire bond wires101forming one or more picket fence-like perimeters110and/or120of one plot may be adjacent another picket fence-like outer perimeter110or120. Thus, a portion of one picket fence-like perimeter may be used in combination with a portion of a neighboring or bordering picket fence-like perimeter to provide an interference shielding cage. Along those lines, a multiplex of interference shielding cages121, with or without one or more inner interference shielding cages111, may be provided with a single microelectronic package100. Inner perimeters110of these interference shield cages111provided by wire bond wires101may, but do not need to, run perpendicular to an edge or follow a straight line. Rather, such inner perimeters can be laid out or shaped to follow a contour or other irregular pattern. Conductive layer122, which is left off for clarity inFIG. 10, may be formed over multiple outer interference shielding cages121, as previously described herein.

A microelectronic device105in an inner or only interference shielding cage111or a microelectronic device117in an outer interference shielding cage121of a plot may be coupled to another microelectronic device105or117in another interference shielding cage111or121in another plot by routing between pairs of adjacent wire bond wires101in one or more intervening perimeters110and/or120, such as routings140and141for example. By coupling microelectronic devices between one or more gaps in one or more interference shielding cages, a microelectronic device which is a stronger EMI source, such as a signal pad without grounding, than another microelectronic device, such as a ground pad which may not be caged, may be directly coupled to one another while still providing sufficient EMI shielding to such stronger EMI source. This may be used for more compact designs with fewer fences to provide sufficient shielding.

Furthermore, it should be understood that one interference shielding cage121may directly border, space apart or not, another interference shielding cage121without having to provide isolation gaps, such as in a molding layer for example, for electrical isolation between such neighboring interference shielding cages. By routing through fences of cages as described herein, routing may be at lower levels, rather than having to run such routing over on top of a microelectronic package. In conventional isolation, trenches are formed which can significantly increase topside routing complexity, and this complexity may be significantly reduced with routing through cage fences, in addition to not having EMI isolation trenches. Moreover, wire bond wires101may be shared among such neighboring interference shielding cages, as previously described. Accordingly, either or both of these configurations may be used to provide a more densely populated microelectronic package100, namely a microelectronic package that has a smaller footprint.

FIG. 11is a block diagram of a top-down view illustratively depicting an exemplary microelectronic package100, andFIG. 12-1is a block diagram of a cross-section along A1-A2ofFIG. 11. With simultaneous reference toFIGS. 1 through 12-1, microelectronic package100ofFIGS. 11 and 12-1is further described.

A conductive layer112or122may be a ground plane, which as a hole160, such as a ring-like hole, cut or ablated therein, such as laser ablated for example, to define an electrical island or pad161therein, namely pad161is not in contact with, nor isolated from, a remainder of conductive layer112or122. Pad161may be a signal pad or a power pad coupled to at least one wire bond wire101C, not part of an interference shielding cage111or121, located for interconnection with pad161. Isolation of pad161may be used for system-in-package (“SiP”) integration. As one example, a decoupling capacitor or other passive or active device may be coupled to one or more of such isolated pads161. This implementation allows passive and/or active devices to be placed on a level above EMI shielding with interconnects through microelectronic package100formed at the same time as one or more interference shielding cages, thereby simplifying package processing. Of course, multiple pads161maybe formed singularly or in an array of two or more pads. Devices may be attached to one or more pads161, conductive layer112/122, or both, for an application. Moreover, while pad161is illustratively depicted as surrounded by a conductive layer, this is for illustrative purposes only. Conductive layer112/122may be generally adjacent to only one or more of the sides of contact pad161.

FIG. 12-2is a block diagram of a cross-section along A1-A2ofFIG. 11after addition of a molding layer113. With simultaneous reference toFIGS. 1 through 12-2, microelectronic package100ofFIGS. 11 and 12-2is further described. In another implementation, one or more pads161may be selectively formed on an upper surface of a molding layer113. Along those lines, molding layer113may be a dielectric, and such one or more pads161may be electrically isolated from one another along an upper surface of molding layer113. By forming conductive layer112by plating, spraying, sputtering, printing, painting, ink stamping, or otherwise selectively depositing a conductive material, conductive layer112may be selectively applied in any applicable pattern or design to an upper surface of molding layer113.

FIG. 13is a top-down perspective view illustratively depicting an exemplary microelectronic package100having interference shielding cages, as described above. In this example, interference shielding cages may include multiple odd-shaped divisions or sections. Thus, there may be multiple isolation zones, which need not, though may, be orthogonal to one another.FIG. 13is further described with simultaneous reference toFIGS. 1 through 13.

Along those lines, microelectronic package100may be a SiP having passive devices181, flip-chip (“FC”) dies182, and wire bond (“WB”) dies183all coupled to an upper surface102of a platform104. WB dies183may be bonded to platform104with wire bonds185. The wire bonds185and/or surface traces (not shown) on platform104may be configured to extend between adjacent wire bond wires101A-101D to other die, or to pads located on the platform104, on the other side of an EMI shielded area. In certain implementations, this allows the EMI shield wire bond wires101A-101D to be formed closer to the EMI source or EMI protected device than the pad on the the platform104. This also allows for more routing flexibility through the sides of the EMI cage than would be possible through conventional techniques such as those EMI shields configured using either a solid conductive side surface or wire bond arches. Other interconnection techniques are shown inFIG. 13, such as FC dies182being “flip-chip” coupled to platform104, along with having an underfill layer184for such coupling.

Wire bond wires101B and101D may form separate EMI shielding perimeters, such as perimeters110for example, around respective FC dies182. Wire bond wires101C may form a separate EMI shielding perimeter, such as a perimeter110for example, around a WB die183. Wire bond wires101A may form an EMI shielding perimeter, such as a perimeter120for example, around components coupled to upper surface102of platform104for EMI shielding to enhance EMC.

A SiP may be a number of active or/and passive components enclosed in a single IC package module, such as microelectronic package100. SiPs are widely used in RF applications, including without limitation mobile devices, wearables and Internet of Things (“IoT”) devices. For example, an RF SiP can contain some active chips such as one or more ASIC and/or memory chips, and some passive components such as RF resistors, capacitors, inductors, oscillators, etc. A SiP is particularly useful in space constrained environments, as a SiP significantly reduces complexity of a printed circuit board (“PCB”) and system design. Recently, SiPs are attracting interest in small form factor electronics, including without limitation IoT devices.

It should be appreciated that issues of EMI and EMC may be more problematic in future SiP designs because more components with multiple frequencies may be integrated into a single RF SiP. For example, a SiP for 5G wireless devices may handle multiple RF functions including WiFi, 3G, 4G LTE, ZigBee, etc. However, by having the ability to selectively apply wire bond wire perimeters for EMI shielding, as previously described, EMI shielding may be provided for different domains within a same SiP. Wire bond wires101may be implemented with high-frequency wire bonding machines for cost effective and high volume production. Moreover, wire bond wires, whether ball bonded or wedge bonded, may be used to make good ground contacts without block surface signal routings between domains.

FIGS. 14-1 and 14-2are block diagrams of a top-down view illustratively depicting respective exemplary wire bond wire patterns191and192for neighboring EMI isolation regions. With simultaneous reference toFIGS. 1 through 14-2, wire bond wire patterns191and192are further described. A row of wire bond wires101B and a row of wire bond wires101D may be back-to-back and spaced apart from one another. Having two or more rows of wire bond wires may be laid out to create concentric perimeters with an array of wires instead of lines of wire bond wires as illustratively depicted in the earlier figures, or a combination thereof.

In wire bond wire pattern191, bases of wire bond wires101B and101D are horizontally- or vertically-aligned to one another, so gaps between wire bond wires101B correspond to gaps between wire bond wires101D. This arrangement or pattern may be useful for allowing direct surface routing to pass through fence-like EMI shield perimeters formed by wire bond wires101B and101D. In another implementation, wire bond wires101B and/or101D may include loop-like structures, such as open loop omega-like structures, as generally indicated with dashed lines189.

In wire bond wire pattern192, bases of wire bond wires101B and101D are offset-aligned to one another, so gaps between wire bond wires101B correspond to bases of wire bond wires101D, and gaps between wire bond wires101D correspond to bases of wire bond wires101B. This arrangement or pattern may be useful for having an overlapping and/or interspersing of wire bond wires with respect to EMI emissions to effectively provide a more dense mesh, for example by a combination of fence-like EMI shield perimeters formed by wire bond wires101B and101D.

Moreover, wire bond wires101B and101D may have same or different diameters, and may be made out of same or different materials. Pattern selection, as well as thickness and/or material selection, may be tailored to an application, such as may be associated with parameters of sources of EMI emission, including without limitation frequency of operation.

FIGS. 15-1 through 15-3are block diagrams of a side view illustratively depicting respective exemplary wire bond wire patterns193and194for neighboring EMI isolation regions. With simultaneous reference toFIGS. 1 through 15-3, wire bond wire patterns193and194are further described. A row of wire bond wires101B and a row of wire bond wires101D may be back-to-back and spaced apart from one another, and both sets of these rows of wire bond wires may be slanted. Wire bond wires101D are illustrated with dashed lines to indicate they are in back of wire bond wires101B. An outer ring or other perimeter of an EMI cage may have wires slanted in one direction, while an inner ring or other perimeter of another EMI cage may be slanted in a second direction opposite the first direction. For example, such a second direction may be generally an opposite angle with respect to the angle in such a first direction in any of x, y, or z directions.

More particularly by way of non-limiting example, in left wire bond wire pattern193, bases of wire bond wires101B and101D are horizontally- or vertically-aligned to one another, so gaps between wire bond wires101B correspond to gaps between wire bond wires101D. As mentioned above with reference toFIG. 10, this arrangement or pattern may be useful for allowing surface-based routing to pass through fence-like EMI shield perimeters formed by wire bond wires101B and101D. However, wire bond wires101B and101D are slanted in opposite directions in order to form a crosswise mesh for a combination of fence-like EMI shield perimeters formed by wire bond wires101B and101D.

Right wire bond pattern193is the same as left wire bond pattern, except bases of wire bond wires101B and101D are offset-aligned to one another, so gaps between wire bond wires101B correspond to bases of wire bond wires101D, and gaps between wire bond wires101D correspond to bases of wire bond wires101B. This arrangement or pattern may be useful for forming a bi-directional mesh for a combination of fence-like EMI shield perimeters formed by wire bond wires101B and101D.

In wire bond wire pattern194, bases of wire bond wires101B and101D are offset-aligned to one another, so gaps between wire bond wires101B correspond to bases of wire bond wires101D, and gaps between wire bond wires101D correspond to bases of wire bond wires101B. This arrangement or pattern may be useful for forming a unidirectional mesh for a combination of fence-like EMI shield perimeters formed by wire bond wires101B and101D.

FIG. 16is a flow diagram illustratively depicting a EMI shield forming process200for forming a microelectronic package100having wire bond wires101for interference shielding for protection from EMI. Process200is further described with simultaneous reference toFIGS. 1 through 16.

At201, a platform104is obtained having an upper surface102and a lower surface106opposite upper surface102and having a ground plane107. At202, a microelectronic device105is coupled to upper surface102of platform104. At203, wire bond wires101are wire bonded, such as ball, wedge or stitch bonded, for electrical interconnection with ground plane107. Such wire bond wires101may have a pitch, as previously described. Wire bond wires101extend away from upper surface102of platform104with upper ends of wire bond wires101being above an upper surface of microelectronic device105. Such wire bond wires101are spaced apart from one another to provide a fence-like perimeter to provide at least one interference shielding cage, such as previously described. At204, a molding layer113may be deposited over upper surface102of platform104, as previously described. At205, a conductive layer may be formed, as previously described, for being coupled to at least a subset of upper ends of wire bond wires101for electrical conductivity to provide a conductive shielding layer112and/or122to cover such an interference shielding cage111and/or121. Along those lines, operation202may be for coupling multiple microelectronic devices to an upper surface of a platform, and operation203may be for forming multiple wire bond perimeters, such as described elsewhere herein. Thus, at operation205one or more conductive layers may be formed.