SEMICONDUCTOR MEMORY DEVICE

A semiconductor device includes a substrate having an active region and a gate structure crossing the active region. The gate structure may include a gate pattern penetrating an upper portion of the active region in a first direction perpendicular to a bottom surface of the substrate, a metal-containing pattern on the gate pattern, and a barrier pattern interposed between the gate pattern and the metal-containing pattern and extended to face opposite side surfaces of the metal-containing pattern.

CROSS-REFERENCE TO RELATED APPLICATION

This U.S. non-provisional patent application claims priority under 35 U.S.C. § 119 to Korean Patent Application No. 10-2022-0021101, filed on Feb. 17, 2022, in the Korean Intellectual Property Office, the entire contents of which are hereby incorporated by reference.

BACKGROUND

The present disclosure relates to a semiconductor device, and in particular, to a semiconductor device including gate structures.

2. Description of the Related Art

Due to their small-size, multifunctionality, and/or low-cost characteristics, semiconductor devices are being esteemed as important elements in the electronics industry. The semiconductor devices are classified into a semiconductor memory device for storing data, a semiconductor logic device for processing data, and a hybrid semiconductor device including both memory and logic elements.

With the recent trend of high speed and low power consumption of electronic devices, semiconductor devices in the electronic devices are also required to have high operating speeds and/or low operating voltages, and in order to satisfy this requirement, it is necessary to increase an integration density of the semiconductor device. However, the increase of the integration density of the semiconductor device may lead to deterioration in reliability and electric characteristics of the semiconductor device. Thus, many studies are being conducted to improve reliability and electric characteristics of the semiconductor device.

SUMMARY

According to an embodiment, a semiconductor device may include a substrate including an active region and a gate structure crossing the active region. The gate structure may include a gate pattern penetrating an upper portion of the active region in a first direction perpendicular to a bottom surface of the substrate, a metal-containing pattern on the gate pattern, and a barrier pattern interposed between the gate pattern and the metal-containing pattern and extended to face opposite side surfaces of the metal-containing pattern.

According to an embodiment, a semiconductor device may include a substrate including active regions, a first gate structure and a second gate structure crossing the active regions, respectively, and a buried semiconductor pattern interposed between the substrate and the second gate structure. Each of the first and second gate structures may include a gate pattern penetrating an upper portion of each of the active regions, a metal-containing pattern on the gate pattern, and a barrier pattern interposed between the gate pattern and the metal-containing pattern and extended to face opposite side surfaces of the metal-containing pattern.

According to an embodiment, a semiconductor device may include a substrate including active regions and a first gate structure and a second gate structure crossing the active regions, respectively. The first gate structure may include a gate pattern penetrating an upper portion of one of the active regions, a metal-containing pattern on the gate pattern, and a barrier pattern interposed between the gate pattern and the metal-containing pattern and extended to face opposite side surfaces of the metal-containing pattern. The second gate structure may include a horizontal gate pattern, a horizontal barrier pattern, and a horizontal metal-containing pattern, which are sequentially stacked on a top surface of another of the active regions.

DETAILED DESCRIPTION

FIG.1is a block diagram illustrating a semiconductor device according to an embodiment.

Referring toFIG.1, a semiconductor device may include cell blocks CB and a peripheral block PB, which is provided to surround each of the cell blocks CB. The semiconductor device may be a memory device, and each of the cell blocks CB may include a cell circuit (e.g., a memory integrated circuit). The peripheral block PB may include various peripheral circuits, which are used to operate the cell circuit, and the peripheral circuits may be electrically connected to the cell circuit.

The peripheral block PB may include sense amplifier circuits SA and sub-word line driver circuits SWD. In an embodiment, the sense amplifier circuits SA may be provided to face each other with the cell blocks CB interposed therebetween, and the sub-word line driver circuits SWD may be provided to face each other with the cell blocks CB interposed therebetween. The peripheral block PB may further include power and ground circuits for driving a sense amplifier.

FIG.2is a plan views illustrating a semiconductor device according to an embodiment.FIGS.3A to3Dare cross-sectional views along lines A-A′ to D-D′ ofFIG.2, respectively.

Referring toFIGS.2and3A to3D, a substrate100including a first peripheral region PR1, a second peripheral region PR2, a third peripheral region PR3, and a fourth peripheral region PR4may be provided. The substrate100may be a semiconductor substrate. For example, the substrate100may be a silicon substrate, a germanium substrate, or a silicon-germanium substrate. In an embodiment, the substrate100may be a silicon-on-insulator (SOI) substrate. The first to fourth peripheral regions PR1, PR2, PR3, and PR4may be regions of the substrate100, in which the peripheral block PB ofFIG.1is provided. For example, as illustrated inFIG.2, the first to fourth peripheral regions PR1, PR2, PR3, and PR4may be arranged side by side, e.g., adjacent to each other along the second direction D2.

As further illustrated inFIGS.2and3A to3D, a first active region ACT1, a second active region ACT2, a third active region ACT3, and a fourth active region ACT4may be provided on the first peripheral region PR1, the second peripheral region PR2, the third peripheral region PR3, and the fourth peripheral region PR4, respectively. The first to fourth active regions ACT1, ACT2, ACT3, and ACT4may be protruding portions of the substrate100, and may extend in the first direction D1perpendicular to a bottom surface100yof the substrate100. Thus, a top surface100xof the substrate100may correspond to a top surface of the first to fourth active regions ACT1, ACT2, ACT3and ACT4.

A device isolation layer120may be disposed in the substrate100to define the first to fourth active regions ACT1, ACT2, ACT3and ACT4. In an embodiment, the device isolation layer120may be formed of or include at least one of, e.g., silicon oxide, silicon nitride, or silicon oxynitride or combination thereof.

Referring toFIGS.2and3A, a first gate structure GS1may be provided to cross the first active region ACT1. A lower portion of the first gate structure GS1may be buried in the substrate100. The first gate structure GS1may include a gate pattern310, a metal-containing pattern330, and a barrier pattern331.

The gate pattern310may constitute a lower portion of the first gate structure GS1and may penetrate an upper portion of the first active region ACT1in the first direction D1. A top surface310xof the gate pattern310may be located at a height higher than a top surface of the first active region ACT1, and a bottom surface310yof the gate pattern310may be located at a height lower than the top surface of the first active region ACT1, e.g., relative to the bottom surface100yof the substrate100. The gate pattern310may be extended in the second direction D2and the third direction D3. The second and third directions D2and D3may be parallel to the bottom surface100yof the substrate100and may be non-parallel (e.g., orthogonal) to each other. The top surface310xof the gate pattern310may be parallel to the second and third directions D2and D3. In other words, the top surface310xof the gate pattern310may be substantially parallel to the bottom surface100yof the substrate100. The gate pattern310near, e.g., along, the top surface310xof the gate pattern310may have a first width W1in the second direction D2. In an embodiment, the gate pattern310may be formed of or include, e.g., doped or undoped polysilicon.

The metal-containing pattern330may be provided on the gate pattern310. The metal-containing pattern330may be provided on the top surface310xof the gate pattern310. The metal-containing pattern330may be extended in the second and third directions D2and D3. A bottom surface330yof the metal-containing pattern330may be parallel to the second and third directions D2and D3. In other words, the bottom surface330yof the metal-containing pattern330may be substantially parallel to the bottom surface100yof the substrate100. The metal-containing pattern330near, e.g., along, the bottom surface330yof the metal-containing pattern330may have a second width W2in the second direction D2. The first width W1may be larger than the second width W2. In an embodiment, the metal-containing pattern330may be formed of or include at least one of metallic materials (e.g., tungsten, titanium, or tantalum).

The barrier pattern331may be interposed between the gate pattern310and the metal-containing pattern330. The barrier pattern331may be interposed, e.g., directly, between the top surface310xof the gate pattern310and the bottom surface330yof the metal-containing pattern330, and may be extended to face opposite side surfaces330zof the metal-containing pattern330, e.g., the barrier pattern331may extend continuously along opposite side surfaces330zof the metal-containing pattern330. The barrier pattern331may, e.g., completely, cover the bottom surface330yand the opposite side surfaces330zof the metal-containing pattern330. The topmost surface331xof the barrier pattern331may be located at substantially the same height as the top surface330xof the metal-containing pattern330, and may be coplanar with the top surface330xof the metal-containing pattern330. Each of opposite side surfaces331zof the barrier pattern331may be coplanar with and aligned with a corresponding one of opposite side surfaces310zof the gate pattern310. In the present specification, the opposite side surfaces331zof the barrier pattern331may mean outer side surfaces of the barrier pattern331. The opposite side surfaces310zof the gate pattern310and the opposite side surfaces331zof the barrier pattern331may constitute opposite side surfaces GS1zof the first gate structure GS1. The barrier pattern331may be formed of or include at least one of metal nitride materials (e.g., TiN, TSN, and TaN). For example, a peripheral ohmic pattern may be provided between the barrier pattern331and the gate pattern310, e.g., the peripheral ohmic pattern may be formed of or include at least one of metal silicide materials.

A gate insulating pattern GI may be interposed between the bottom surface310yof the gate pattern310and the substrate100, and may be extended to face the opposite side surfaces310zof the gate pattern310, e.g., and may extend along opposite side surfaces310zof the gate pattern310. The gate insulating pattern GI may be further extended to face the opposite side surfaces331zof the barrier pattern331, and the barrier pattern331may be interposed between each of the side surfaces330zof the metal-containing pattern330and the gate insulating pattern GI. In other words, the gate insulating pattern GI may be extended to face the opposite side surfaces GS1zof the first gate structure GS1. The gate insulating pattern GI may be straightly, e.g., continuously, extended from an inner portion of the first active region ACT1to a height of the topmost surface331xof the barrier pattern331in the first direction D1. The gate insulating pattern GI may be straightly e.g., linearly, extended from a region, which is adjacent to the top surface of the first active region ACT1(i.e., the top surface100xof the substrate100), in the first direction D1. Each of opposite side surfaces GIz of the gate insulating pattern GI may have a profile that is linearly extended in the first direction D1. In the present specification, the opposite side surfaces GIz of the gate insulating pattern GI may mean outer side surfaces of the gate insulating pattern GI. The topmost surface GIx of the gate insulating pattern GI may be located at substantially the same height as the top surface330xof the metal-containing pattern330and the topmost surface331xof the barrier pattern331.

The gate insulating pattern GI may be formed of or include at least one of, e.g., high-k dielectric materials. In the present specification, the high-k dielectric material may mean a material having a dielectric constant higher than silicon oxide (SiO2). For example, the high-k dielectric materials may include at least one of hafnium oxide (HfO), hafnium silicate (HfSiO), hafnium oxynitride (HfON), hafnium silicon oxynitride (HfSiON), lanthanum oxide (LaO), lanthanum aluminum oxide (LaAlO), zirconium oxide (ZrO), zirconium silicate (ZrSiO), zirconium oxynitride (ZrON), zirconium silicon oxynitride (ZrSiON), tantalum oxide (TaO), titanium oxide (TiO), barium strontium titanium oxide (BaSrTiO), barium titanium oxide (BaTiO), strontium titanium oxide (SrTiO), yttrium oxide (YO), aluminum oxide (AlO), or lead scandium tantalum oxide (PbScTaO) or combination thereof.

A first conductive pattern CP1may be interposed between the first gate structure GS1and the gate insulating pattern GI, e.g., the first conductive pattern CP1may completely separate between the first gate structure GS1and the gate insulating pattern GI. In an embodiment, the first conductive pattern CP1may be composed of a single layer. The first conductive pattern CP1may be formed of or include an n-type work-function metal. In an embodiment, the first conductive pattern CP1may be formed of or include at least one of, e.g., lanthanum (La), lanthanum oxide (LaO), tantalum (Ta), tantalum nitride (TaN), niobium (Nb), titanium nitride (TiN) or combination thereof. The first conductive pattern CP1may, e.g., completely, cover the opposite side surfaces330zof the metal-containing pattern330. The topmost surface CP1xof the first conductive pattern CP1may be located at substantially the same height as the topmost surface GIx of the gate insulating pattern GI and may be coplanar with the topmost surface GIx of the gate insulating pattern GI.

A pair of first impurity regions110amay be disposed adjacent to the opposite side surfaces GS1zof the first gate structure GS1. The pair of first impurity regions110amay be provided in the first active region ACT1. In an embodiment, the pair of first impurity regions110amay contain impurities of n-type.

A pair of first spacers SP1may be disposed on the opposite side surfaces GS1zof the first gate structure GS1. The pair of first spacers SP1may be disposed on the top surface100xof the substrate100. The metal-containing pattern330, the barrier pattern331, a portion of the gate insulating pattern GI, and a portion of the first conductive pattern CP1may be interposed between the pair of first spacers SP1. In an embodiment, each of the first spacers SP1may be formed of or include at least one of, e.g., silicon nitride, silicon oxide, or silicon oxynitride or combination thereof. In an embodiment, each of the first spacers SP1may be composed of a single or multiple layer.

An interlayer insulating layer ILD may be provided on the substrate100. The interlayer insulating layer ILD may cover the pair of first spacers SP1and the top surface100xof the substrate100. In an embodiment, the interlayer insulating layer ILD may be formed of or include at least one of, e.g., silicon nitride, silicon oxide, or silicon oxynitride or combination thereof.

A peripheral capping pattern PC may cover the interlayer insulating layer ILD and the first gate structure GS1. The peripheral capping pattern PC may be formed of or include at least one of, e.g., silicon nitride, silicon oxide, or silicon oxynitride or combination thereof. A plurality of interconnection layers may be provided on the peripheral capping pattern PC, and the interconnection layers may be used as a part of a circuit for driving the semiconductor device.

Referring toFIGS.2and3B, a second gate structure GS2may be provided to cross the second active region ACT2. For concise description, an element described with reference toFIG.3Amay be identified by the same reference number without repeating an overlapping description thereof. The second gate structure GS2may include the gate pattern310, the metal-containing pattern330, and the barrier pattern331.

The gate pattern310may constitute a lower portion of the second gate structure GS2. The gate pattern310may include a first portion311, which is provided to penetrate an upper portion of the second active region ACT2, and a second portion312, which is provided on the first portion311and is extended in the second direction D2. The second portion312may protrude from the first portion311in the second direction D2and an opposite direction of the second direction D2, e.g., the second portion312may be wider than the first portion311in the second direction D2and may protrude beyond the first portion311on both sides of the first portion311. Accordingly, each of the opposite side surfaces310zof the gate pattern310may have a stepwise profile. The second portion312may be located at a height higher than the top surface100xof the substrate100, e.g., relative to the bottom surface100yof the substrate100. The top surface310xof the gate pattern310may be parallel to the second and third directions D2and D3.

The gate pattern310may have a third width W3and a fifth width W5. The third width W3may be a width of the gate pattern310, which is measured in the second direction D2near, e.g., along, the top surface310xof the gate pattern310. The fifth width W5may be a width of the gate pattern310, which is measured in the second direction D2near, e.g., along, the top surface100xof the substrate100. The third width W3may be larger than the fifth width W5.

The metal-containing pattern330may be provided on the gate pattern310. The metal-containing pattern330near, e.g., along, the bottom surface330yof the metal-containing pattern330may have a fourth width W4in the second direction D2. The third width W3may be larger than the fourth width W4. The barrier pattern331may be interposed between the gate pattern310and the metal-containing pattern330and may be extended to face the opposite side surfaces330zof the metal-containing pattern330.

The gate insulating pattern GI may be interposed between the bottom surface310yof the gate pattern310and the substrate100and may be extended to face the opposite side surfaces310zof the gate pattern310. In other words, the gate insulating pattern GI on opposite side surfaces of the first and second portions311and312may be extended in the first direction D1. The gate insulating pattern GI near a boundary between the first and second portions311and312may be extended along a protruding bottom surface of the second portion312and in the second direction D2. Accordingly, the opposite side surfaces GIz of the gate insulating pattern GI may have a stepwise profile. The gate insulating pattern GI may be formed of or include at least one of high-k dielectric materials.

A buried semiconductor pattern BSP may be interposed between the gate insulating pattern GI and the substrate100. The buried semiconductor pattern BSP may be placed in the substrate100to cover the gate insulating pattern GI. The buried semiconductor pattern BSP may be buried in the second active region ACT2. The buried semiconductor pattern BSP in the second active region ACT2may have opposite side surfaces BSPz, each of which is coplanar with a corresponding one of the opposite side surfaces GIz of the gate insulating pattern GI placed at a height higher than the top surface of the second active region ACT2(i.e., the top surface100xof the substrate100) and is aligned thereto in the first direction D1. In the present embodiment, the opposite side surfaces BSPz of the buried semiconductor pattern BSP mean outer side surfaces of the buried semiconductor pattern BSP (i.e., in contact with the second active region ACT2).

A lattice constant of the buried semiconductor pattern BSP may be larger than a lattice constant of the substrate100. As an example, the buried semiconductor pattern BSP may be formed of or include silicon germanium.

Conductive patterns CP1and CP2may be interposed between the second gate structure GS2and the gate insulating pattern GI. The conductive patterns CP1and CP2may include a first conductive pattern CP1and a second conductive pattern CP2. The first conductive pattern CP1may be interposed between the second gate structure GS2and the gate insulating pattern GI, and the second conductive pattern CP2may be interposed between the first conductive pattern CP1and the gate insulating pattern GI. The conductive patterns CP1and CP2may be composed of a multiple layer. Opposite side surfaces of the conductive patterns CP1and CP2may have a profile corresponding to the opposite side surfaces310zof the gate pattern310. For example, each of the opposite side surfaces of the conductive patterns CP1and CP2may have a stepwise profile, e.g., each of the opposite side surfaces of the conductive patterns CP1and CP2may be conformal or trace the stepwise profile of the opposite side surfaces310zof the gate pattern310. The topmost surface CP2xof the second conductive pattern CP2may be located at substantially the same height as the topmost surface CP1xof the first conductive pattern CP1and may be coplanar with the topmost surface CP1xof the first conductive pattern CP1.

The first conductive pattern CP1may be formed of or include an n-type work-function metal. As an example, the first conductive pattern CP1may be formed of or include at least one of lanthanum (La), lanthanum oxide (LaO), tantalum (Ta), tantalum nitride (TaN), niobium (Nb), or titanium nitride (TiN) or combination thereof. The second conductive pattern CP2may be formed of or include a p-type work-function metal. As an example, the second conductive pattern CP2may be formed of or include at least one of aluminum (Al), aluminum oxide (AlO), titanium nitride (TiN), tungsten nitride (WN), or ruthenium oxide (RuO2) or combination thereof.

A pair of second impurity regions110bmay be disposed adjacent to opposite side surfaces GS2zof the second gate structure GS2. The pair of second impurity regions110bmay be provided in the second active region ACT2. The pair of second impurity regions110bmay contain impurities that are of a different conductivity type (e.g., p-type) from the first impurity regions110aofFIG.3A.

A pair of second spacers SP2may be disposed on the opposite side surfaces GS2zof the second gate structure GS2. The pair of second spacers SP2may be disposed on the top surface100xof the substrate100. The metal-containing pattern330, the barrier pattern331, a portion of the gate insulating pattern GI, a portion of the first conductive pattern CP1, and a portion of the second conductive pattern CP2may be interposed between the pair of second spacers SP2.

The interlayer insulating layer ILD may be provided on the substrate100. The interlayer insulating layer ILD may cover the pair of second spacers SP2and the top surface100xof the substrate100. The peripheral capping pattern PC may cover the interlayer insulating layer ILD and the second gate structure GS2. A plurality of interconnection layers may be provided on the peripheral capping pattern PC.

Referring toFIGS.2and3C, a third gate structure GS3may be provided to cross the third active region ACT3. For concise description, a previously described element may be identified by the same reference number without repeating an overlapping description thereof. The third gate structure GS3may include a horizontal gate pattern310a,a horizontal barrier pattern331a,and a horizontal metal-containing pattern330a,which are sequentially stacked on a top surface of the third active region ACT3. The horizontal gate pattern310a,the horizontal barrier pattern331a,and the horizontal metal-containing pattern330amay be formed of or include the same materials as the gate pattern310, the barrier pattern331, and the metal-containing pattern330, respectively, ofFIG.3A. A bottom surface of the third gate structure GS3may be located at a height higher than the bottom surface of the first gate structure GS1ofFIG.3A, e.g., relative to the bottom surface100yof the substrate100.

A horizontal gate insulating pattern GIa may be interposed between the third gate structure GS3and the substrate100, and a first horizontal conductive pattern CP1amay be interposed between the third gate structure GS3and the horizontal gate insulating pattern GIa. The horizontal gate insulating pattern GIa may be formed of or include, e.g., the same material as the gate insulating pattern GI ofFIG.3A, and the first horizontal conductive pattern CP1amay be formed of or include, e.g., the same material as the first conductive pattern CP1ofFIG.3A.

The pair of first impurity regions110amay be disposed to be adjacent to opposite side surfaces of the third gate structure GS3and may contain impurities of n-type. A pair of third spacers SP3may be disposed on the opposite side surfaces of the third gate structure GS3. The interlayer insulating layer ILD may cover the pair of third spacers SP3and the top surface100xof the substrate100. The peripheral capping pattern PC may cover the interlayer insulating layer ILD and the third gate structure GS3. A plurality of interconnection layers may be provided on the peripheral capping pattern PC.

Referring toFIGS.2and3D, a fourth gate structure GS4may be provided to cross the fourth active region ACT4. For concise description, an element described with reference toFIG.3Cmay be identified by the same reference number without repeating an overlapping description thereof. The fourth gate structure GS4may include the horizontal gate pattern310a,the horizontal barrier pattern331a,and the horizontal metal-containing pattern330a,which are sequentially stacked on a top surface of the fourth active region ACT4. A bottom surface of the fourth gate structure GS4may be located at a height higher than the bottom surface of the second gate structure GS2ofFIG.3B, e.g., relative to the bottom surface100yof the substrate100.

The horizontal gate insulating pattern GIa may be interposed between the fourth gate structure GS4and the substrate100, and horizontal conductive patterns CP1aand CP2amay be interposed between the fourth gate structure GS4and the horizontal gate insulating pattern GIa. The horizontal conductive patterns CP1aand CP2amay include the first horizontal conductive pattern CP1a,which is provided between the fourth gate structure GS4and the horizontal gate insulating pattern GIa, and a second horizontal conductive pattern CP2a,which is provided between the first horizontal conductive pattern CP1aand the horizontal gate insulating pattern GIa. The first and second horizontal conductive patterns CP1aand CP2amay be formed of or include, e.g., the same materials as the first and second conductive patterns CP1and CP2, respectively, ofFIG.3B.

The pair of second impurity regions110bmay be disposed to be adjacent to opposite side surfaces of the fourth gate structure GS4and may contain impurities of p-type. A pair of fourth spacers SP4may be disposed on the opposite side surfaces of the fourth gate structure GS4. The interlayer insulating layer ILD may cover the pair of fourth spacers SP4and the top surface100xof the substrate100. The peripheral capping pattern PC may cover the interlayer insulating layer ILD and the fourth gate structure GS4. A plurality of interconnection layers may be provided on the peripheral capping pattern PC.

FIGS.4A to11Bare cross-sectional views illustrating stages in a method of fabricating a semiconductor device, according to an embodiment. Here,FIGS.4A to11Aare cross-sectional views, which are taken along line A-A′ ofFIG.2, andFIGS.4B to11Bare cross-sectional views, which are taken along line B-B′ ofFIG.2. Hereinafter, a method of fabricating a semiconductor device according to an embodiment will be described in more detail with reference toFIGS.4A to11B. For concise description, a previously described element may be identified by the same reference number without repeating an overlapping description thereof.

Referring toFIGS.4A and4B, the first and second active regions ACT1and ACT2may be formed on the first and second peripheral regions PR1and PR2of the substrate100. The formation of the first and second active regions ACT1and ACT2may include partially etching an upper portion of the substrate100to form a trench region and forming a device isolation layer (e.g., ofFIG.2) to fill the trench region. Some regions of a remaining portion of the substrate100may be used as the first and second active regions ACT1and ACT2.

A protection layer PL, a first sacrificial layer SL1, a second sacrificial layer SL2, and a mask pattern MP may be sequentially formed on the substrate100. In an embodiment, the protection layer PL may be formed of or include, e.g., at least one of silicon nitride, or silicon oxynitride or combination thereof. The first sacrificial layer SL1may be formed of or include, e.g., at least one of silicon oxide, or silicon oxynitride or combination thereof. The second sacrificial layer SL2may be formed of or include, e.g., at least one of silicon oxide, silicon nitride, or silicon oxynitride or combination thereof. The mask pattern MP may include, e.g., a carbon-containing hard mask. However, the materials for the protection layer PL, the first sacrificial layer SL1, the second sacrificial layer SL2, and the mask pattern MP may include may other suitable materials. The formation of the mask pattern MP may include forming a mask layer on the second sacrificial layer SL2and patterning the mask layer. The mask pattern MP may include a first opening OP1on the first peripheral region PR1and a second opening OP2on the second peripheral region PR2.

Referring toFIGS.5A and5B, first and second recess regions RE1and RE2may be formed on the first and second peripheral regions PR1and PR2, respectively, to penetrate an upper portion of the substrate100, the protection layer PL, the first sacrificial layer SL1, and the second sacrificial layer SL2. The first and second recess regions RE1and RE2may be vertically overlapped with the first and second openings OP1and OP2ofFIGS.4A and4B, respectively. The formation of the first and second recess regions RE1and RE2may include performing an anisotropic etching process using the mask pattern MP as an etch mask. The first and second recess regions RE1and RE2may be formed to expose an inner portion of the substrate100. The mask pattern MP may be removed during or after the process of forming the first and second recess regions RE1and RE2.

Referring toFIGS.6A and6B, the buried semiconductor pattern BSP may be formed in the second recess region RE2. The buried semiconductor pattern BSP may be formed, e.g., conformally, by a selective epitaxial growth (SEG) process, in which the inner portion of the substrate100exposed by the second recess region RE2is used as a seed layer, e.g., so the buried semiconductor pattern BSP may be grown only on the exposed surfaces of the substrate100. In an embodiment, during the SEG process, an inner portion of the first recess region RE1may be veiled by an additional mask, and such a mask may be removed after the SEG process.

Thereafter, a gate insulating layer GIL may be formed to conformally cover inner surfaces of the first and second recess regions RE1and RE2. The gate insulating layer GIL may be extended to face a top surface of the second sacrificial layer SL2. In the second recess region RE2, the gate insulating layer GIL may cover the buried semiconductor pattern BSP. Accordingly, the gate insulating layer GIL on the second peripheral region may have a stepwise profile in a region adjacent to a top surface of the buried semiconductor pattern BSP. The gate insulating layer GIL may be formed of or include, e.g., at least one of high-k dielectric materials. In an embodiment, the gate insulating layer GIL may be formed by an atomic layer deposition (ALD) process.

Referring toFIGS.7A and7B, a second conductive line CL2may be formed to conformally cover the gate insulating layer GIL. The second conductive line CL2may partially fill inner spaces of the first and second recess regions RE1and RE2and may be extended to face a top surface of the second sacrificial layer SL2. Thereafter, the second conductive line CL2may be removed from the first peripheral region PR1. The second conductive line CL2on the second peripheral region PR2may have a profile (e.g., a stepwise profile) corresponding to the gate insulating layer GIL.

A first conductive line CL1may be conformally formed on the entire top surface of the substrate100. The first conductive line CL1on the first peripheral region PR1may conformally cover the gate insulating layer GIL. The first conductive line CL1on the second peripheral region PR2may conformally cover the second conductive line CL2. The first conductive line CL1on the second peripheral region PR2may have a profile (e.g., a stepwise profile) corresponding to the second conductive line CL2. The first conductive line CL1may be formed of or include, e.g., an n-type work-function metal, and the second conductive line CL2may be formed of or include, e.g., a p-type work-function metal.

Referring toFIGS.8A and8B, a gate layer310L may be formed to fill remaining portions of the first and second recess regions RE1and RE2. The gate layer310L may be extended to face the top surface of the second sacrificial layer SL2, e.g., a single (e.g., a same) gate layer310L may completely fill both the first and second recess regions RE1and RE2and extend to cover the top surface of the second sacrificial layer SL2. The gate layer310L may cover the first conductive line CL1. In an embodiment, the gate layer310L may be formed of or include, e.g., doped or undoped polysilicon.

Referring toFIGS.9A and9B, an upper portion of the gate layer310L may be removed, and then, the gate layer310L may be divided into a plurality of gate patterns310, e.g., so each of the plurality of gate patterns310is in a separate recess region. The removal process of the gate layer310L may include performing an etch-back process on the gate layer310L. The gate patterns310may be formed in the first and second recess regions RE1and RE2, respectively. A top surface of the gate pattern310may be higher than the top surface of the substrate100but may be lower than the top surface of the second sacrificial layer SL2, e.g., the top surface of the gate pattern310may be higher than the top surface of the protection layer PL and lower than the bottom surface of the second sacrificial layer SL2. Thus, empty regions may be formed in upper portions of the first and second recess regions RE1and RE2, and a portion of the first conductive line CL1may be exposed.

Referring toFIGS.10A and10B, a barrier layer331L may be formed to conformally cover top surfaces of the gate patterns310and the exposed portion of the first conductive line CL1. In the first and second recess regions RE1and RE2, the barrier layer331L may be extended from the first conductive line CL1in the first direction D1. In an embodiment, the barrier layer331L may be formed of or include at least one of metal nitride materials (e.g., TiN, TSN, and TaN).

A metal-containing layer330L may be formed to fill remaining portions of the first and second recess regions RE1and RE2. The metal-containing layer330L may be extended to face the top surface of the second sacrificial layer SL2or to cover the barrier layer331L. In an embodiment, the metal-containing layer330L may be formed of or include at least one of metallic materials (e.g., tungsten, titanium, and tantalum). A peripheral ohmic pattern, which includes at least one of metal silicide materials, may be formed between the barrier layer331L and the gate pattern310.

Referring toFIGS.11A and11B, an upper portion of the metal-containing layer330L, an upper portion of the barrier layer331L, an upper portion of the first conductive line CL1, an upper portion of the second conductive line CL2, an upper portion of the gate insulating layer GIL, and the second sacrificial layer SL2may be removed. Accordingly, the metal-containing pattern330, the barrier pattern331, the first conductive pattern CP1, the second conductive pattern CP2, and the gate insulating pattern GI may be formed on each of the first and second peripheral regions PR1and PR2. An upper portion of the first sacrificial layer SL1may also be removed during this process. A top surface of the metal-containing pattern330, a top surface of the barrier pattern331, a top surface of the first conductive pattern CP1, a top surface of the second conductive pattern CP2, a top surface of the gate insulating pattern GI, and a top surface of the first sacrificial layer SL1may be located at substantially the same height and may be coplanar with each other. In an embodiment, the removal process may include a planarization (e.g., CMP) process.

The first and second gate structures GS1and GS2may be formed on the first and second peripheral regions PR1and PR2, respectively. Each of the first and second gate structures GS1and GS2may include the metal-containing pattern330, the barrier pattern331, and the gate pattern310.

Referring back toFIGS.3A and3B, the first sacrificial layer SL1and the protection layer PL may be removed. The removal process may include an etching process. The first and second impurity regions110aand110bmay be formed to be adjacent to opposite side surfaces of the gate structures GS1and GS2, and the first and second spacers SP1and SP2may be formed on the opposite side surfaces of the gate structures GS1and GS2. Thereafter, the interlayer insulating layer ILD may be formed to cover the first and second spacers SP1and SP2, and the top surface100xof the substrate100. The peripheral capping pattern PC may cover the interlayer insulating layer ILD and the gate structures GS1and GS2.

According to an embodiment, the first and second recess regions RE1and RE2may be formed, before the formation of the first and second gate structures GS1and GS2. Thereafter, a node-separation process of the first and second gate structures GS1and GS2may be performed by an etch-back process, not by a process including exposure and etching steps. That is, it may be possible to prevent a misalignment issue caused by an exposure process, and thus, it may be possible to improve reliability and electric characteristics of a semiconductor device.

In addition, the top surface310xof the gate pattern310and the bottom surface330yof the metal-containing pattern330may be substantially parallel to the bottom surface100yof the substrate100, e.g., the top surface310xof the gate pattern310and the bottom surface330yof the metal-containing pattern330may be completely flat in their entirety. Accordingly, it may be possible to prevent a seam from being formed in the first and second gate structures GS1and GS2and thereby to improve reliability and electric characteristics of a semiconductor device.

FIGS.12A to12Dare cross-sectional views, which are respectively taken along lines A-A′ to D-D′ ofFIG.2to illustrate a semiconductor device according to an embodiment. For concise description, a previously described element may be identified by the same reference number without repeating an overlapping description thereof.

Referring toFIGS.12A and12D, a gate capping pattern GC may be provided on each of the gate structures GS1, GS2, GS3, and GS4. The gate capping pattern GC may cover a top surface of the metal-containing pattern330. As shown inFIG.12A, the gate capping pattern GC on the first gate structure GS1may be extended to cover a top surface of the barrier pattern331, a top surface of the first conductive pattern CP1, and a top surface of the gate insulating pattern GI. As shown inFIG.12B, the gate capping pattern GC on the second gate structure GS2may be extended to cover a top surface of the barrier pattern331, a top surface of the first conductive pattern CP1, a top surface of the second conductive pattern CP2, and a top surface of the gate insulating pattern GI. In an embodiment, the gate capping pattern GC may be formed of or include, e.g., at least one of silicon nitride, or silicon oxide or combination thereof.

Each of the spacers SP1, SP2, SP3, and SP4may be extended to face a side surface of the gate capping pattern GC, and the interlayer insulating layer ILD may be provided to cover the spacers SP1, SP2, SP3, and SP4. The peripheral capping pattern PC may be provided to cover a top surface of the gate capping pattern GC and a top surface of the interlayer insulating layer ILD.

In an embodiment, the gate capping pattern GC may be selectively provided on some of the gate structures GS1, GS2, GS3, and GS4(e.g., on only the third and fourth gate structures GS3and GS4). In an embodiment, the gate capping pattern GC may be provided on all of the gate structures GS1, GS2, GS3, and GS4. In an embodiment, a plurality of first gate structures GS1may be provided, and the gate capping pattern GC may be selectively provided on some of the first gate structures GS1.

FIG.13is a plan view illustrating a semiconductor device according to an embodiment.FIG.14is a cross-sectional view, which is taken along line E-E′ ofFIG.13to illustrate a semiconductor device according to an embodiment.

Referring toFIGS.13and14, the substrate100including a cell region CR may be provided. The cell region CR may be a region of the substrate100, in which the cell blocks CB ofFIG.1are provided.

Cell active patterns ACTc may be disposed on the cell region CR of the substrate100. When viewed in a plan view, the cell active patterns ACTc may be spaced apart from each other in the second and third directions D2and D3. The cell active patterns ACTc may be bar-shaped patterns extended in a fourth direction D4, which is parallel to a bottom surface of the substrate100and is not parallel to the second and third directions D2and D3.

Cell device isolation layers120cmay be disposed on the cell region CR and between the cell active patterns ACTc. The cell device isolation layers120cmay be disposed in the substrate100to define the cell active patterns ACTc.

Word lines WL may be provided on the cell region CR to cross the cell active patterns ACTc and the cell device isolation layers120c.The word lines WL may be disposed in grooves, which are formed in the cell active patterns ACTc and the cell device isolation layers120c.The word lines WL may be extended in the second direction D2and may be spaced apart from each other in the third direction D3. In an embodiment, the word lines WL may be buried in the substrate100.

Third and fourth impurity regions110cand110dmay be provided in the cell active patterns ACTc. Each of the third impurity regions110cmay be provided in a pair of the word lines WL, which are provided to cross each of the cell active patterns ACTc. The fourth impurity regions110dmay be provided in opposite edge regions of each of the cell active patterns ACTc. The third impurity regions110cmay contain impurities that are of the same conductivity type (e.g., n-type) as the fourth impurity regions110d.

A buffer pattern306may be provided on the substrate100to cover the cell active patterns ACTc, the cell device isolation layers120c,and the word lines WL. In an embodiment, the buffer pattern306may be formed of or include, e.g., at least one of silicon oxide, silicon nitride, or silicon oxynitride or combination thereof.

Bit lines BL may be disposed on the buffer pattern306. The bit lines BL may be extended in the third direction D3and may be spaced apart from each other in the second direction D2. Each of the bit lines BL may include a cell barrier pattern331cand a cell metal-containing pattern330csequentially stacked. The cell barrier pattern331cand the cell metal-containing pattern330cmay be formed of or include, e.g., the same materials as the barrier pattern331and the metal-containing pattern330, respectively, ofFIG.3A.

Cell polysilicon patterns310cmay be interposed between the bit lines BL and the buffer pattern306. The cell polysilicon patterns310cmay be formed of or include, e.g., the same material as the gate pattern310ofFIG.3A. A first cell ohmic pattern may be provided between the cell barrier pattern331cand the cell polysilicon pattern310ccorresponding thereto. In an embodiment, the first cell ohmic pattern may be formed of or include, e.g., at least one of metal silicide materials.

Bit line contacts DC may be respectively interposed between the bit lines BL and the third impurity regions110c.The bit lines BL may be electrically connected to the third impurity regions110cthrough the bit line contacts DC. The bit line contacts DC may be formed of or include, e.g., doped or undoped polysilicon.

The bit line contacts DC may be disposed in a third recess region RE3. The third recess region RE3may be provided in an upper portion of the third impurity regions110cand an upper portion of the cell device isolation layers120cadjacent thereto. A first gapfill insulating pattern314cand a second gapfill insulating pattern315cmay be provided to fill a remaining portion of the third recess region RE3.

A cell capping pattern350cmay be provided on each of the bit lines BL and may be extended in the second direction D2. In an embodiment, the cell capping pattern350cmay be formed of or include, e.g., silicon nitride.

A side surface of each of the cell polysilicon patterns310c,an upper side surface of each of the bit line contacts DC, a side surface of each of the bit lines BL, and a side surface of the cell capping pattern350cmay be covered with a bit line spacer SPc. The bit line spacer SPc may be provided on each of the bit lines BL and may be extended in the first direction D1.

The bit line spacer SPc may include a first sub-spacer321and a second sub-spacer325, which are spaced apart from each other. In an embodiment, the first sub-spacer321and the second sub-spacer325may be spaced apart from each other by an air gap AG. The first sub-spacer321may be in contact with a side surface of each of the bit lines BL and may be extended to cover the side surface of the capping pattern350. The second sub-spacer325may be provided along a side surface of the first sub-spacer321. Each of the first and second sub-spacer321and325may be formed of or include, e.g., silicon nitride.

An upper spacer360may cover the side surface of the first sub-spacer321and may be extended to a top surface of the second sub-spacer325. The upper spacer360may cover or stop the air gap AG.

Storage node contacts BC may be interposed between adjacent ones of the bit lines BL. The storage node contacts BC may be spaced apart from each other in the second and third directions D2and D3. The storage node contacts BC may be formed of or include, e.g., doped or undoped polysilicon.

A second cell ohmic pattern341cmay be disposed on each of the storage node contacts BC. In an embodiment, the second cell ohmic pattern341cmay be formed of or include, e.g., at least one of metal silicide materials.

A cell diffusion-prevention pattern342cmay be provided to conformally cover the second cell ohmic pattern341c,the bit line spacer SPc, and the cell capping pattern350c.In an embodiment, the cell diffusion-prevention pattern342cmay be formed of or include at least one of metal nitride materials (e.g., TiN, TSN, and TaN). The second cell ohmic pattern341cmay be interposed between the cell diffusion-prevention pattern342cand each of the storage node contacts BC.

Landing pads LP may be disposed on the storage node contacts BC, respectively. The landing pads LP may be spaced apart from each other in the second and third directions D2and D3. The landing pads LP may be formed of or include at least one of metallic materials (e.g., tungsten).

A gap-fill pattern400may be provided to enclose each of the landing pads LP. The gap-fill pattern400may be interposed between adjacent ones of the landing pads LP.

Bottom electrodes BE may be disposed on the landing pads LP, respectively. The bottom electrodes BE may be formed of or include, at least one of doped polysilicon, metal nitride materials (e.g., titanium nitride), or metallic materials (e.g., tungsten, aluminum, and copper) or combination thereof. Each of the bottom electrodes BE may be shaped like, e.g., a circular pillar, a hollow cylinder, or a cup. An upper supporting pattern SS1may be provided to support upper side surfaces of the bottom electrodes BE, and a lower supporting pattern SS2may be provided to support lower side surfaces of the bottom electrodes BE. The upper and lower supporting patterns SS1and SS2may be formed of or include at least one of insulating materials (e.g., silicon nitride, silicon oxide, and silicon oxynitride).

An etch stop pattern420may be provided between the bottom electrodes BE and on the gap-fill pattern400. A dielectric layer DL may be provided to cover the bottom electrodes BE and the upper and lower supporting patterns SS1and SS2. In an embodiment, the dielectric layer DL may be formed of or include, e.g., at least one of silicon oxide, silicon nitride, silicon oxynitride, or high-k dielectric materials or combination thereof. A top electrode TE may be disposed on the dielectric layer DL to fill a space between the bottom electrodes BE. The top electrode TE may be formed of or include at least one of doped poly-silicon, doped silicon germanium, metal nitride materials (e.g., titanium nitride), or metallic materials (e.g., tungsten, aluminum, and copper) or combination thereof. The bottom electrodes BE, the dielectric layer DL, and the top electrode TE may constitute a capacitor CA.

By way of summation and review, an embodiment provides a semiconductor device with improved reliability and electrical characteristics. That is, according to an embodiment, an etch-back process may be performed for a node-separation process of separating gate structures from each other. In this case, it may be possible to prevent a misalignment issue caused by an exposure process, and thus, it may be possible to improve reliability and electric characteristics of a semiconductor device. In addition, it may be possible to prevent a seam from being formed in the gate structures, and thereby to further improve the reliability and electric characteristics of the semiconductor device.