Methods and devices for reducing clock skew in bidirectional clock trees

The present disclosure provides systems and methods for improving operation of integrated circuit device including a logic region, which includes a plurality of logic gates that operate based at least in part on a clock signal to facilitate providing a target function, and a clock tree, which includes a clock switch block that receives a source clock signal from a clock source and a branch communicatively coupled between the clock switch block and the logic region, in which the branch operates to provide the clock signal to the logic region based at least in part on the source clock signal and the branch includes a tunable delay buffer that operates to apply a delay to the clock signal based at least in part on a clock skew expected to be introduced by the branch.

BACKGROUND

The present disclosure generally relates to integrated circuit devices and, more particularly, to clock trees implemented in an integrated circuit device.

Generally, an electronic device or an electrical system may include one or more integrated circuit (IC) devices. To improve operational flexibility, in some instances, an integrated circuit device may be a programmable logic device that is programmable (e.g., configurable) after manufacturing to provide one or more target (e.g., desired) functions, such as a field programmable gate array (FPGA). To facilitate providing a target function, an integrated circuit device may include one or more logic elements (e.g., blocks and/or gates), for example, programmed (e.g., configured) to operate based at least in part on corresponding configuration data.

In some instances, the logic elements in an integrated circuit device may be organized into multiple logic regions, for example, with each logic region providing a target function and/or multiple logic regions cooperating to provide a target function. Thus, in operation, the integrated circuit device may coordinate (e.g., synchronize) operation of multiple logic regions. Since logic elements generally operates based at least in part on a received clock signal, in some instances, the integrated circuit device may coordinate operation of multiple logic regions by supplying the clock signal to corresponding logic elements using a clock tree (e.g., a clock network-on-chip). For example, the clock tree may include multiple branches that each communicates the clock signal through a corresponding logic region.

However, in some instances, a clock signal may become skewed (e.g., time-shifted or phase-shifted) as it is communicated through the clock tree, for example, due to length of the branches and/or stages (e.g., muxes or buffers) along the branches. In fact, likelihood and/or magnitude of clock skew may increase as size of the clock tree increases, variation in length of the branches increases, and/or due to programming of the integrated circuit device. Since operating based at least in part on the clock signal, clock skew may affect operation of the logic elements and, thus, the integrated circuit device, for example, by decreasing operational efficiency and/or increasing operational latency

SUMMARY

A summary of certain embodiments disclosed herein is set forth below. It should be understood that these aspects are presented merely to provide the reader with a brief summary of these certain embodiments and that these aspects are not intended to limit the scope of the present disclosure. Indeed, the present disclosure may encompass a variety of aspects that may not be set forth below.

The present disclosure generally relates to integrated circuit (IC) devices, which may operate to perform one or more target (e.g., desired) functions in an electrical system. To facilitate performing a target function, in some embodiments, an integrated circuit device may include one or more logic elements (e.g., blocks or gates) that operate based at least in part on a received clock signal, for example, to perform a logic operation and/or an arithmetic operation used in providing a combinational function, a sequential function, an arithmetic functions, a logic function, and/or a custom function. Thus, in some embodiments, the integrated circuit device may include a clock tree (e.g., a clock network-on-chip) that communicates a clock signal to various logic elements. However, in some instances, the clock signal may become skewed as it is communicated through the clock tree, thereby affecting operation of the logic elements and, thus, the integrated circuit device.

Accordingly, the present disclosure provides techniques to improve operation (e.g., operational efficiency and/or operational latency) of an integrated circuit device by reducing likelihood of clock skew affecting operation. In some embodiments, an integrated circuit device includes a logic region, which includes a plurality of logic gates that operate based at least in part on a clock signal to facilitate providing a target function, and a clock tree, which includes a clock switch block that receives a source clock signal from a clock source and a branch communicatively coupled between the clock switch block and the logic region, in which the branch operates to provide the clock signal to the logic region based at least in part on the source clock signal and the branch includes a tunable delay buffer that operates to apply a delay to the clock signal based at least in part on a clock skew expected to be introduced by the branch.

Additionally, in some embodiments, a method for controlling operation of an integrated circuit device includes routing, using a clock switch block, a source clock signal to a first branch in a clock tree to enable a first logic region of the integrated circuit device communicatively coupled to the first branch to operate based at least in part on the source clock signal; routing, using the clock switch block, the source clock signal to a second branch in the clock tree to enable a second logic region of the integrated circuit device communicatively coupled to the second branch to operate based at least in part on the source clock signal; receiving, using the clock switch block, a first feedback clock signal from the first branch, in which the first feedback clock signal includes the source clock signal with a first delay introduced by the first branch; receiving, using the clock switch block, a second feedback clock signal form the second branch, in which the second feedback clock signal includes the source clock signal with a second delay introduced by the second branch; and determining, using the clock switch block, skew data indicative of phase variation between the first feedback clock signal and the second feedback clock signal to enable the integrated circuit device to adjust the first delay, the second delay, or both to reduce magnitude of the phase variation.

Furthermore, in some embodiments, a tangible, non-transitory, computer-readable medium stores instructions executable by one or more processors in an electrical system, in which the instructions comprise instruction to determine, using the one or more processors, skew data indicative of difference between a first delay introduced on a source clock signal resulting from routing the source clock signal to a first portion of an integrated circuit device via a clock tree and a second delay introduced on the source clock signal resulting from routing the source clock signal to a second portion of the integrated circuit device via the clock tree; and instruct, using the one or more processors, one or more tunable delay buffers to adjust delay applied to the source clock signal by the clock tree based at least in part on the skew data to facilitate coordinating operation of the first portion of the integrated circuit device and the second portion of the integrated circuit device.

DETAILED DESCRIPTION

Generally, an integrated circuit device operates to provide one or more target functions in an electrical system. For example, the target functions may include combinational functions, sequential functions, arithmetic functions, logic functions, and/or custom function. Thus, in some embodiments, an integrated circuit device may operate to process data, analyze data, store data, and/or read data.

To help illustrate, one embodiment of an electrical system10including an integrated circuit device12is shown inFIG. 1. In some embodiments, the electrical system10may be included in an industrial system, a manufacturing system, an automation system, or the like, such as a factory or plant. Additionally, in some embodiments, the electrical system10may be included in an electronic device, such as a handheld computing device, a tablet computing device, a notebook computer, a desktop computer, or the like. Furthermore, in some embodiments, electrical system10may be included in an automotive system, such as an airplane, boat, or car.

Thus, although one integrated circuit device12is depicted, it should be appreciated that this is merely intended to be illustrative and not limiting. In other words, in other embodiments, the electrical system10may include multiple integrated circuit devices12. For example, the electrical system10may include a first integrated circuit12(e.g., central processing unit or graphics processing unit) communicatively coupled with a second integrated circuit12(e.g., random-access memory).

In any case, as depicted, the integrated circuit device12includes a logic element array14, a clock tree16, and a controller18. In some embodiments, the controller18may control operation of the logic element array14and/or the clock tree16. To facilitate controlling operation, the controller18may include a controller processor20and controller memory22. In some embodiments, the controller18may control operation based at least in part on circuit connections (e.g., logic gates) formed in the controller18.

Additionally or alternatively, the controller processor20may execute instructions stored in the controller memory22. Thus, in some embodiments, the controller processor20may include one or more general purpose microprocessors, one or more application specific processors (ASICs), one or more field programmable logic arrays (FPGAs), and/or the like. Additionally, in some embodiments, the controller memory22may include one or more tangible, non-transitory, computer-readable mediums. For example, the controller memory22may include random access memory (RAM), read only memory (ROM), rewritable non-volatile memory, such as flash memory, hard drives, optical discs, and/or the like.

As described above, the integrated circuit device12may operate to perform one or more target functions in the electrical system10. To facilitate providing a target function, the logic element array14may include communicatively coupled logic elements (e.g., blocks or gates) that operate to perform combinational functions, sequential functions, arithmetic functions, logic functions, and/or custom functions. Additionally, in some embodiments, the logic element array14may be divided into one or more logic regions, which each includes one or more logic elements.

To help illustrate, one embodiment of a logic element array14organized into multiple logic regions48is shown inFIG. 2. In particular, the depicted embodiment includes a first logic region48A, a second logic region48B, a third logic region48C, and a fourth logic region48D, which each includes one or more logic elements50. In some embodiments, a logic element50may include one or more muxes, one or more flip-flops, one or more logic gates, one or more logic blocks, one or more look-up-tables, and/or one or more registers.

In some embodiments, the logic element array14may be organized such that different logic regions48operate to perform different target functions. Additionally or alternatively, the logic element array14may be organized such that multiple logic regions48cooperate to perform a target function. Thus, to facilitate proper operation of the integrated circuit device12, operation of different logic regions48may be coordinated (e.g., synchronized) and/or data communication may be provided.

To facilitate data communication, the logic element array14may include input/output circuitry42, input/output pins44, and an internal communication network46(e.g., a network-on-chip). In some embodiments, the input/output circuitry42may facilitate external data communication via the input/output pins44, for example, between the logic element array14and another integrated circuit device12. Additionally, in some embodiments, internal communication network46may facilitate internal data communication, for example, between logic regions48and/or with input/output circuitry42. Thus, in some embodiments, the internal communication network46may include interconnects, such as conductive lines and/or busses. Furthermore, in some embodiments, the internal communication network46may include fixed interconnects and/or programmable interconnects.

Additionally, in some embodiments, the logic elements50and, thus, the logic regions48operate based at least in part on a received clock signal. In particular, operations may be performed based on rising edges and/or falling edges of the received clock signal. Thus, to facilitate coordinating operation of multiple logic regions48, approximately the same clock signal may be communicated to corresponding logic elements50in the logic regions48.

Returning to the integrated circuit device12ofFIG. 1, the clock tree16may facilitate communicating a clock signal to the various logic regions48. To help illustrate, one embodiment of a clock tree16is shown inFIG. 3. In particular, in the depicted embodiment, the clock tree16is a bi-directional H-tree formed using a pre-built clock grid. It should be appreciated that the described embodiment of the clock tree16is merely intended to be illustrative and not limiting. In other words, in other embodiments, the techniques described in the present disclosure may be implement in other clock tree configurations.

With regard to the depicted embodiment, the clock tree16includes clock interconnects63, clock switch blocks64, and tunable delay buffers74(e.g., delay devices). In operation, a clock switch block64may receive a source clock signal from a clock source62, for example, directly from the clock source62and/or via an upstream clock switch block64. Additionally, the clock switch block64may route the source clock through a one or more tunable delay devices74via a block interconnect63and/or to a target logic region48.

In this manner, the clock tree16may route the source clock signal to logic elements50and/or logic regions48in the logic element array14. For example, in the depicted embodiment, the clock tree16includes a first branch60A that may be used to route the source clock signal to the first logic region48A. Additionally, in the depicted embodiment, the clock tree16includes a second branch60B that may be used to route the source clock signal to the fourth logic region48D.

Additionally, in some embodiments, the clock tree16may route a feedback clock signal from logic elements50and/or logic regions48in the logic element array14to one or more clock switch block64. For example, in the depicted embodiment, the first branch60A may be used to route a first feedback clock signal from the first logic region48A. Additionally, the second branch60B may be used to route a second feedback clock signal from the fourth logic region48D. It should be appreciated that the clock tree16may additionally or alternatively be implemented to include one or more branches60to route the source clock signal to and/or feedback clock signals from other logic regions48(e.g., second logic region48B and/or third logic region48C).

As described above, in some instances, routing clock signals through the clock tree16may introduce clock skew, for example, due to variations in branch length, stages (e.g., muxes or buffers) along the branches, and/or other electrical factors (e.g., process variation). However, as described above, clock skew may affect operation of the logic elements50and, thus, coordination between different logic regions48in an integrated circuit device12. Thus, in some embodiments, operation of one or more tunable delay buffers74along a branch60may be controlled based at least in part on expected clock skew.

To help illustrate, a portion74of the clock tree16is shown inFIG. 4. As depicted, the portion74includes a first clock switch block64A communicatively coupled to a second clock switch block64B via clock interconnects63through a tunable delay device72. Additionally, as depicted, the controller18is communicatively coupled to the tunable delay device72. In this manner, the controller18may instruct the tunable delay buffer72to adjust delay applied on a corresponding clock interconnect63based at least in part on expected clock skew, for example, to implement a phase-locked loop (PLL) and/or a delay-locked loop (DLL).

In some embodiments, a clock switch block64may facilitate determining the clock skew expected to be introduced by a branch60, for example, with reference to clock skew introduced by another branch60. To help illustrate, one embodiment of a clock switch block64is shown inFIG. 5. As depicted, the clock switch block64includes a phase detector76and a clock signal router78. Additionally, as depicted, the clock switch block64receives a reference clock signal80, a feedback clock signal82, and a source clock signal84.

In some embodiments, the source clock signal84may be received from an upstream clock switch block64and/or from the clock source62. For example, with regard toFIG. 4, the second clock switch block64B may receive the source clock signal84from the first clock switch block64A. Additionally, in some embodiments, the feedback clock signal82may be received from a downstream clock switch block64. For example, the first clock switch block64A may receive the feedback clock signal82from the second clock switch block64B.

Returning toFIG. 5, the clock signal router78may determine routing of the source clock signal84and/or the feedback clock signal82. For example, the clock signal router78may determine whether to route the source clock signal84to a downstream clock switch block64or to a corresponding logic region48via a clock signal interface86. In some embodiments, operation of the clock signal router78and/or the logic element array14may be programmable (e.g., configurable), for example, by a programming system.

To help illustrate, one embodiment of a programming system88that may be used to program (e.g., configure) operation of an integrated circuit device12is shown inFIG. 12. In some embodiments, the programming system88may enable programming operation of the integrated circuit device12during semiconductor manufacturing, for example, using mask programming arrangements. Additionally, in some embodiments, the programming system88may enable one-time programming of the integrated circuit device12after manufacture, for example, using fuses and/or antifuses.

Furthermore, in some embodiments, the programming system88may enable dynamically programming (e.g., reprogramming) operation of the integrated circuit device12when the integrated circuit device12is a programmable (e.g., reconfigurable) logic device, such as a field programmable gate array (FPGA). In some embodiments, the integrated circuit device12may be programmed using design software90, such as a version of Quartus by Altera™. Additionally, the design software90may use a compiler92to generate configuration data94, such as a low-level circuit-design kernel program, sometimes known as a program object file.

To program the integrated circuit device12, the configuration data94may be stored, for example, in configuration memory52shown inFIG. 2. In some embodiments, the configuration memory52may be implemented as random-access-memory (RAM) cells. Since these RAM cells are loaded with configuration data during programming, they are sometimes referred to as configuration RAM cells (CRAM). Based at least in part on the configuration data, control signals may be generated to control operation96of the integrated circuit device12.

For example, based at least in part on target function configuration data, a control signal may be applied to the gate of a metal-oxide-semiconductor (e.g., logic element50) to control operation in a manner that facilitates implementing a corresponding target function. In some embodiments, based at least in part on data routing configuration data, a control signal may be supplied to the internal communication network46to control data routing in a manner that facilitate implementing a corresponding target data routing configuration. Additionally or alternatively, based at least in part on clock routing configuration data, a control signal may be supplied to the clock switch blocks64to control clock signal routing in a manner that facilitates implementing a corresponding clock routing configuration (e.g., implementation of branches60in the clock tree16).

In some instances, programming (e.g., reprogramming) an integrated circuit device12to adjust operation and/or configuration of the clock tree16may affect electrical factors. For example, reprogramming a branch60from a first routing configuration to a second routing configuration may affect branch length and/or stages (e.g., muxes or buffers) along the branch60. Thus, in such instances, programming (e.g., reprogramming) the integrated circuit device12may further increase likelihood and/or magnitude of clock skew introduced by a clock tree16.

To facilitate reducing likelihood of clock skew affecting operation of the integrated circuit device12, returning toFIG. 5, the phase detector76may determine skew (e.g., phase-shift or time-shift) data based at least in part on the feedback clock signal82and the reference clock signal80. As described above, in some embodiments, clock skew expected to be introduced by one branch60may be determined with reference to clock skew introduced by another branch60in the clock tree16. In other words, in such embodiments, the reference clock signal80may be received from a different branch60compared to the feedback clock signal82. For example, with regard toFIG. 3, the central clock switch block64C may receive a first feedback signal82from the first branch60A and a second feedback signal82from the second branch60B. Thus, to determine clock skew on the second branch60B, the central clock switch block64C may use the first feedback signal82as the reference clock signal80. In other embodiments, the reference clock signal80may be predetermined, for example, by time shifting and/or phase shifting the source clock signal84.

One embodiment of a process98for determining expected clock skew and adjusting operation of a clock tree16accordingly is described inFIG. 7. Generally, the process98includes determining a reference clock signal (process block100), determining a feedback clock signal (process block102), determining skew data (process block104), and adjusting operation of a tunable delay buffer based at least in part on the skew data (process block106). In some embodiments, the process98may be implemented based on circuit connections formed in one or more clock switch blocks64and/or the controller18. Additionally or alternatively, in some embodiments, the process98may be implemented by executing instructions stored in a tangible, non-transitory, computer-readable medium, such as the controller memory22, using a processor, such as the controller processor20.

Accordingly, in some embodiments, a clock switch device64may determine a reference clock signal80(process block100) and determine a feedback clock signal82(process block102). In some embodiments, the feedback clock signal82determined may correspond with the branch60for which expected clock skew is to be determined. Additionally, in some embodiments, the reference clock signal80may be the feedback clock signal82corresponding with another branch60in the clock tree16.

As described above, a clock switch block64may receive feedback clock signals82from downstream clock switch blocks64. For example, with regard toFIG. 3, a central clock switch block64C may receive a first feedback signal82from the first branch60A and a second feedback signal82from the second branch60B. As described above, the feedback signal80used as the reference clock signal80may be determined based at least in part on branch60for which the expected clock skew is to be determined. For example, to determine expected clock skew associated with the second branch60B, the central clock switch block64C may use the first feedback clock signal82as the reference clock signal80. On the other hand, to determine expected clock skew associated with the first branch60A, the central clock switch block64C may use the second feedback clock signal82as the reference clock signal80.

Additionally, in some embodiments, more than two branches60may be implemented in a clock tree16. For example, the central clock switch block64C may potentially route the source clock signal84through four different branches60and, thus, potentially receive four feedback signals82. Thus, in some embodiments, a clock switch block64may include a first mux to select which clock signal is input to the phase detector76as the reference clock signal80and a second mux to select which clock signal is input to the phase detector76as the feedback clock signal82.

Based at least in part on the feedback clock signal82and the reference clock signal80, the phase detector76in the clock switch block64may determine skew (e.g., time-shift or phase-shift) data (process block104). In some embodiments, the skew data may indicate whether the feedback clock signal82is leading or lagging the reference clock signal80. Additionally, in some embodiments, the clock skew data may indicate magnitude (e.g., duration, time period, or phase angle) of variation between the feedback clock signal82and the reference clock signal80.

Thus, in some embodiments, the phase detector76may determine the skew data by comparing the feedback clock signal82and the reference clock signal80. For example, the phase detector76may determine the skew data based at least in part whether a rising edge on the reference clock signal80lead or lags a corresponding (e.g., closest in time) rising edge on the feedback clock signal82and duration between the rising edge on the reference clock signal80and the corresponding rising edge on the feedback block signal82. Additionally or alternatively, the phase detector76may determine the skew data based at least in part whether a falling edge on the reference clock signal80lead or lags a corresponding (e.g., closest in time) falling edge on the feedback clock signal82and duration between the falling edge on the reference clock signal80and the corresponding falling edge on the feedback block signal82.

Based at least in part on the skew data, the controller18may instruct one or more tunable delay buffers72to adjust applied delay (process block106). In some embodiments, the controller18may receive the skew data from the clock switch block64and communicate control signals (e.g., commands) to a tunable delay buffer72indicating amount of delay that should be applied to subsequently communicated source clock signals84. In this manner, operation of the tunable delay buffers72may be controlled to reduce likelihood and/or magnitude of variation in clock skew introduced by different branches60, which may improve operation of the integrated circuit device12, for example, by facilitating coordinated operation of multiple logic regions48with improved operational efficiency and/or reduced operational latency.

To help illustrate, timing diagrams108describing clock signals received by a clock switch block64are shown inFIG. 8. In particular, a first timing diagram108A includes a first waveform110representative of a reference clock signal80. Additionally, a second timing diagram108B includes a second waveform112representative of a first feedback clock signal82and a third timing diagram108C includes a third waveform114representative of a second feedback clock signal82.

Based on the rising edges and/or falling edges of first waveform110and the second waveform112, the clock switch block64may determine skew data that indicates that the first feedback clock signal82leads the reference clock signal80by approximately one-eighth of the clock cycle (T). As such, based at least in part on the skew data, the controller18may instruct one or more tunable delay buffers74on a corresponding branch60to increase delay applied to subsequently communicated source clock signals84such that the resulting first feedback clock signal82is expected to be delayed an additional one-eighth of the clock cycle (T). Additionally or alternatively, the controller18may instruct one or more tunable delay buffers74on a corresponding branch60to reduce delay applied to subsequently communicated source clock signals84such that the resulting first feedback clock signal82is expected to be advanced seven-eighths of the clock cycle (T).

Additionally, based on the rising edges and/or falling edges of first waveform110and the third waveform114, the clock switch block64may determine skew data that indicates that the second feedback clock signal82lags the reference clock signal80by approximately one-eighth of the clock cycle (T). As such, based at least in part on the skew data, the controller18may instruct one or more tunable delay buffers74on a corresponding branch60to increase delay applied to subsequently communicated source clock signals84such that the resulting first feedback clock signal82is expected to be delayed an additional seven-eighths of the clock cycle (T). Additionally or alternatively, the controller18may instruct one or more tunable delay buffers74on the corresponding branch60to reduce delay applied to subsequently communicated source clock signals84such that the resulting first feedback clock signal82is expected to be advanced one-eighth of the clock cycle (T).

While the embodiments set forth in the present disclosure may be susceptible to various modifications and alternative forms, specific embodiments have been shown by way of example in the drawings and have been described in detail herein. However, it may be understood that the disclosure is not intended to be limited to the particular forms disclosed. The disclosure is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the disclosure as defined by the following appended claims.