Data control circuit, and semiconductor memory apparatus and semiconductor system including the same

A semiconductor memory apparatus may include a data control circuit, an input/output circuit block, and a data line repeater block. The data control circuit may generate a data control flag signal based on an operation control signal and data. The input/output circuit block may perform a data bus inversion operation for the data, based on the data control flag signal. The data line repeater block may perform a data masking operation for the data based on the data control flag signal.

CROSS-REFERENCES TO RELATED APPLICATION

The present application claims priority under 35 U.S.C. § 119(a) to Korean application number 10-2017-0115194, filed on Sep. 8, 2017, in the Korean Intellectual Property Office, which is incorporated herein by reference in its entirety.

BACKGROUND

1. Technical Field

Various embodiments generally relate to a semiconductor technology, and, more particularly, to a data control circuit, and a semiconductor apparatus and a semiconductor system including the same.

2. Related Art

Electronic systems may consist of a large number of electronic components. Among the electronic systems, a computer system may have many semiconductor apparatuses, which are electronic components that exploit electronic properties of semiconductor materials. The semiconductor apparatuses which configure the computer system may communicate by performing data input/output operations.

The semiconductor memory apparatus includes a memory bank region where a plurality of memory cells are disposed.

SUMMARY

Various embodiments are directed to a semiconductor apparatus and a semiconductor system including an integrated data control circuit capable of controlling a data bus inversion operation and a data masking operation.

In an embodiment, a semiconductor memory apparatus may include: a data control circuit configured to generate a data control flag signal based on an operation control signal and data; an input/output circuit block configured to invert or not-invert the data based on the data control flag signal, and output an output; and a data line repeater block configured to selectively output the data based on the data control flag signal.

In an embodiment, a semiconductor memory apparatus may include: a data control circuit configured to generate a data control flag signal based on an operation control signal such that one of a data bus inversion operation for read data and a data masking operation for write data is performed; an input/output circuit block configured to invert or not-invert the read data transmitted through a data transmission line based on the data control flag signal, and output an output; and a data line repeater block configured to selectively output the write data transmitted through the data transmission line to a memory bank region based on the data control flag signal.

DETAILED DESCRIPTION

Hereinafter, a data control circuit, and a semiconductor apparatus and a semiconductor system including the same will be described below with reference to the accompanying drawings through various examples of embodiments.

FIG. 1is a diagram illustrating a representation of an example configuration of a semiconductor system1in accordance with an embodiment. InFIG. 1, the semiconductor system1may include a first semiconductor apparatus110and a second semiconductor apparatus120. The first semiconductor apparatus110and the second semiconductor apparatus120may be electronic components which communicate with each other. In an embodiment, the first semiconductor apparatus110may be a master apparatus, and the second semiconductor apparatus120may be a slave apparatus which operates by being controlled by the first semiconductor apparatus110. For example, the first semiconductor apparatus110may be a host apparatus such as a processor or a controller, and may include a central processing unit (CPU), a graphic processing unit (GPU), a multimedia processor (MMP), a digital signal processor (DSP), or a memory controller. Further, the first semiconductor apparatus110may be realized in the form of a system-on-chip by combining processor chips having various functions, such as application processors (AP). The second semiconductor apparatus120may be a memory apparatus, and the memory apparatus may include a volatile memory or a nonvolatile memory. The volatile memory may include an SRAM (static RAM), a DRAM (dynamic RAM), or an SDRAM (synchronous DRAM). The nonvolatile memory may include a ROM (read only memory), a PROM (programmable ROM), an EEPROM (electrically erasable and programmable ROM), an EPROM (electrically programmable ROM), a flash memory, a PRAM (phase change RAM), an MRAM (magnetic RAM), an RRAM (resistive RAM) or an FRAM (ferroelectric RAM).

The first semiconductor apparatus110may provide various control signals to control the second semiconductor apparatus120and thereby perform data communications. For example, the first semiconductor apparatus110may be coupled with the second semiconductor apparatus120through a command bus101, an address bus102, a clock bus103, and a data bus104. The command bus101may be a unidirectional signal transmission line for transmitting a command signal CMD. The address bus102may be a unidirectional signal transmission line for transmitting an address signal ADD. The clock bus103may be a unidirectional signal transmission line for transmitting a clock signal CLK. In an embodiment, the clock signal CLK may be plural and include a system clock signal and a data clock signal. The data clock signal may be a clock signal which is used to transmit data through synchronization, and the system clock signal may be a signal which is used to transmit remaining control signals except data. The data bus104may be a bidirectional signal transmission line for transmitting data DQ. An operation in which data is transmitted from the first semiconductor apparatus110to the second semiconductor apparatus120and is stored in the second semiconductor apparatus120may be a data input operation and/or a write operation, and an operation in which data stored in the second semiconductor apparatus120is transmitted from the second semiconductor apparatus120to the first semiconductor apparatus110may be a data output operation and/or a read operation. In order to perform the write operation, the first semiconductor apparatus110may provide the command signal CMD, the address signal ADD, and the data DQ to the second semiconductor apparatus120. In order to perform the read operation, the first semiconductor apparatus110may provide the command signal CMD and the address signal ADD to the second semiconductor apparatus120, and the second semiconductor apparatus120may provide the data DQ to the first semiconductor apparatus110.

InFIG. 1, the second semiconductor apparatus120may include a memory bank region121, an input/output circuit block122, a data line repeater block123, and a data control circuit124. The memory bank region121may be a core region, and may include a plurality of memory cells capable of storing data. A plurality of bit lines and a plurality of word lines may be disposed in the memory bank region121, and memory cells may be coupled to points where the plurality of bit lines and the plurality of word lines intersect with each other. The memory bank region121may include various core control circuits for storing data in memory cells or outputting data stored in the memory cells. The input/output circuit block122may be coupled with the first semiconductor apparatus110through the data bus104. The input/output circuit block122may be coupled with the memory bank region121through data transmission lines125. The input/output circuit block122may output data transmitted from the first semiconductor apparatus110, to the data transmission lines125in a write operation, and may output data transmitted through the data transmission lines125, to the first semiconductor apparatus110in a read operation. Hereinbelow, data transmitted from the first semiconductor apparatus110and transmitted through the data transmission lines125in the write operation may be referred to as write data, and data outputted from the memory bank region121and transmitted through the data transmission lines125in the read operation may be referred to as read data. The input/output circuit block122may perform a data bus inversion operation in the read operation. The input/output circuit block122may perform the data bus inversion operation for the read data in the read operation, based on data control flag signals DBIF<1:m> (m is an integer of 2 or more).

The data line repeater block123may be coupled between the data transmission lines125and the memory bank region121. The data line repeater block123may drive or repeat write data transmitted through the input/output circuit block122and the data transmission lines125, and may provide the write data to the memory bank region121. The data line repeater block123may drive or repeat data outputted from the memory bank region121and may output the data to the data transmission lines125. That is to say, the data line repeater block123may drive the data transmission lines125based on the data outputted from the memory bank region121. The data line repeater block123may perform a data masking operation in the write operation. The data line repeater block123may perform the data masking operation for the write data based on the data control flag signals DBIF<1:m>.

The data control circuit124may be coupled with the data transmission lines125, and may receive data transmitted through the data transmission lines125. The data control circuit124may generate the data control flag signals DBIF<1:m> based on an operation control signal RDWTP and the received data. The operation control signal RDWTP may include information on whether the second semiconductor apparatus120performs a write operation or a read operation. The operation control signal RDWTP may be generated based on the command signal CMD. For example, the operation control signal RDWTP may be enabled based on a read command signal in the read operation, and may be disabled based on a write command signal in the write operation. The data control circuit124may generate the data control flag signals DBIF<1:m> such that one of the data bus inversion operation and the data masking operation may be performed. The data control circuit124may generate the data control flag signals DBIF<1:m> such that the data bus inversion operation is performed for the read data in the read operation, and may generate the data control flag signals DBIF<1:m> such that the data masking operation is performed for the write data in the write operation. The data control circuit124may be an integrated logic circuit for the data bus inversion operation and the data masking operation. The data control flag signals DBIF<1:m> may be provided in common to the input/output circuit block122and the data line repeater block123. Therefore, the semiconductor memory apparatus in accordance with an embodiment may increase design efficiency and sufficiently secure a circuit area. The data control circuit124may generate the data control flag signals DBIF<1:m> by determining the levels of all the bits of the data transmitted through the data transmission lines125in the read operation. The data control circuit124may generate the data control flag signals DBIF<1:m> by determining levels of some bits of the data transmitted through the data transmission lines125in the write operation.

FIG. 2is a diagram illustrating a representation of an example configuration of a semiconductor memory apparatus200in accordance with an embodiment. The semiconductor memory apparatus200shown inFIG. 2may be applied as the second semiconductor apparatus120shown inFIG. 1. InFIG. 2, the semiconductor memory apparatus200may include a memory bank region, an input/output circuit block, a data line repeater block, and a data control circuit240. The memory bank region may include a first memory bank region211and a second memory bank region212. While it is illustrated inFIG. 2that the semiconductor memory apparatus200includes two memory bank regions, it is not intended that that embodiment be limited thereto. The semiconductor memory apparatus200may include at least two memory bank regions where there may be an even number of memory bank regions. In an embodiment, the semiconductor memory apparatus200may operate in a first byte mode and a second byte mode. The first byte mode may be, for example, an X16 operation mode, and may be an operation mode in which successive input/output of 16-bit data is possible. The second byte mode may be, for example, an X8 operation mode, and may be an operation mode in which successive input/output of 8-bit data is possible. In the second byte mode, any one of the first and second memory bank regions211and212may selectively perform data input/output operations.FIG. 2shows components of the semiconductor memory apparatus200for operating in the second byte mode.

The input/output circuit block may include a plurality of input/output circuits221,222,223,224, . . . ,22n-1, and22n. The plurality of input/output circuits221,222,223,224, . . . ,22n-1, and22nmay be coupled between data buses DQ<1:n> (n is an integer of 2 or more) and coupled with an external apparatus such as the first semiconductor apparatus110shown inFIG. 1and data transmission lines250. The plurality of input/output circuits221,222,223,224, . . . ,22n-1, and22nmay receive data through the data buses DQ<1:n> or output data to the data buses DQ<1:n>. The plurality of input/output circuits221,222,223,224, . . . ,22n-1, and22nmay parallelize data received through the data buses DQ<1:n> and output the parallelized data to the data transmission lines250. The plurality of input/output circuits221,222,223,224, . . . ,22n-1, and22nmay serialize data received through the data transmission lines250and output the serialized data to the data buses DQ<1:n>. Each of the plurality of input/output circuits221,222,223,224, . . . ,22n-1, and22nmay include a parallelizer and a serializer for parallelizing and serializing received data. The plurality of input/output circuits221,222,223,224, . . . ,22n-1, and22nmay perform a data bus inversion operation for read data. The plurality of input/output circuits221,222,223,224, . . . ,22n-1, and22nmay invert or not-invert the read data received through the data transmission lines250based on data control flag signals DBIF<1:m>, and may output the inverted or not-inverted read data to the data buses DQ<1:n>. The plurality of input/output circuits221,222,223,224, . . . ,22n-1, and22nmay include read multiplexers for inverting or not-inverting the data received through the data transmission lines250, and outputting the inverted or not-inverted data based on the data control flag signals DBIF<1:m>. Descriptions will be made later for the read multiplexers.

The data line repeater block may include a plurality of repeaters RPT11, RPT12, . . . , RPT1m, RPT21, RPT22, . . . and RPT2m. The plurality of repeaters RPT11, RPT12, . . . , RPT1m, RPT21, RPT22, . . . and RPT2mmay be coupled between the first and second memory bank regions211and212and the data transmission lines250. The plurality of repeaters RPT11, RPT12, . . . , RPT1m, RPT21, RPT22, . . . and RPT2mmay drive and/or repeat data received through the data transmission lines250, and may provide the repeated data to the first and second memory bank regions211and212. The plurality of repeaters RPT11, RPT12, . . . , RPT1m, RPT21, RPT22, . . . and RPT2mmay drive and/or repeat data outputted from the first and second memory bank regions211and212, and may output the repeated data to the data transmission lines250. The plurality of repeaters RPT11, RPT12, . . . , RPT1m, RPT21, RPT22, . . . and RPT2mmay include write drivers for repeating data received through the data transmission lines250and read drivers for repeating data outputted from the first and second memory bank regions211and212. The plurality of repeaters RPT11, RPT12, . . . , RPT1m, RPT21, RPT22, . . . and RPT2mmay perform a data masking operation for write data. The plurality of repeaters RPT11, RPT12, . . . , RPT1m, RPT21, RPT22. . . and RPT2mmay provide the write data received is through the data transmission lines250, selectively to the first and second memory bank regions211and212based on the data control flag signals DBIF<1:m>. For example, when performing a data masking operation, the plurality of repeaters RPT11, RPT12, . . . , RPT1m, RPT21, RPT22, . . . and RPT2mmay block write data received through the data transmission lines250from being outputted to the first and second memory bank regions121and122when the data masking signal DM is enabled. In one example, the plurality of repeaters RPT11, RPT12, . . . , RPT1m, RPT21, RPT22. . . and RPT2mmay output data received through the data transmission lines250to the first and second memory bank regions211and212when the data masking signal is disabled. The plurality of repeaters RPT11, RPT12, . . . , RPT1m, RPT21, RPT22, . . . and RPT2mmay include write multiplexers which generate a data masking signal based on the data control flag signals DBIF<1:m> such that data received through the data transmission lines250may be selectively outputted. Descriptions will be made later for the write multiplexers.

InFIG. 2, the semiconductor memory apparatus200may operate in, for example, the second byte mode, and one of the first and second memory bank regions211and212may selectively perform a write operation and a read operation according to control of the external apparatus such as the first semiconductor apparatus110shown inFIG. 1. For example, the semiconductor memory apparatus200may be coupled with n number of data buses, and may operate with the burst length of m. A number, such as m*n, of data transmission lines250may be provided. InFIG. 2, the plurality of input/output circuits221,222,223,224, . . . ,22n-1, and22nand the plurality of repeaters RPT11, RPT12, . . . , RPT1m, RPT21, RPT22, . . . and RPT2mmay be coupled with each other by the data transmission lines250. For the sake of clarity in explanation, inFIG. 2, data to be inputted/outputted by the plurality of input/output circuits221,222,223,224, . . . ,22n-1, and22nand data to be inputted/outputted by the plurality of repeaters RPT11, RPT12, . . . , RPT1m, RPT21, RPT22, . . . and RPT2mare separately represented. The first input/output circuit221may input/output first data GIO1<1> to GIOm<1> of first to m{circumflex over ( )}th burst lengths, and the second input/output circuit222may input/output second data GIO1<2> to GIOm<2> of the first to m{circumflex over ( )}th burst lengths. The third input/output circuit223may input/output third data GIO1<3> to GIOm<3> of the first to m{circumflex over ( )}th burst lengths, and the fourth input/output circuit224may input/output fourth data GIO1<4> to GIOm<4> of the first to m{circumflex over ( )}th burst lengths. The (n−1){circumflex over ( )}th input/output circuit22n-1may input/output (n−1){circumflex over ( )}th data GIO1<n−1> to GIOm<n−1> of the first to m{circumflex over ( )}th burst lengths, and the n{circumflex over ( )}th input/output circuit22nmay input/output n{circumflex over ( )}th data GIO1<n> to GIOm<n> of the first to m{circumflex over ( )}th burst lengths. Each of the first repeater RPT11coupled with the first memory bank region211and the first repeater RPT21coupled with the second memory bank region212may input/output the first to n{circumflex over ( )}th data GIO1<1:n> of the first burst length. Each of the second repeater RPT12coupled with the first memory bank region211and the second repeater RPT22coupled with the second memory bank region212may input/output the first to n{circumflex over ( )}th data GIO2<1:n> of the second burst length. Each of the m{circumflex over ( )}th repeater RPT1mcoupled with the first memory bank region211and the m{circumflex over ( )}th repeater RPT2mcoupled with the second memory bank region212may input/output the first to n{circumflex over ( )}th data GIOm<1:n> of the m{circumflex over ( )}th burst length.

The data control circuit240may receive both an operation control signal RDWTP and the data GIO1<1:n> to GIOm<1:n> transmitted through the data transmission lines250. The data control circuit240may generate the data control flag signals DBIF<1:m> based on the operation control signal RDWTP such that one of the data bus inversion operation and the data masking operation may be performed. The data control circuit240may generate the data control flag signals DBIF<1:m> for a data bus inversion operation based on the operation control signal RDWTP which is enabled in the read operation, and may generate the data control flag signals DBIF<1:m> for a data masking operation based on the operation control signal RDWTP which is disabled in the write operation. The data control circuit240may generate each of the data control flag signals DBIF<1:m> by determining the levels of a plurality of data for configuring one burst length. The data control flag signals DBIF<1:m> may have the number of bits corresponding to the burst length. The data control circuit240may generate each of the data control flag signals DBIF<1:m> by determining the levels of all the data bits of one burst length in the read operation. For example, the data control circuit240may enable each of the data control flag signals DBIF<1:m> when the number of bits having a predetermined level among data configuring one burst length is a majority, and may disable each of the data control flag signals DBIF<1:m> when the number is not a majority. The data control circuit240may generate each of the data control flag signals DBIF<1:m> by determining the levels of some data bits of one burst length in the write operation. For example, the data control circuit240may enable each of the data control flag signals DBIF<1:m> when the number of bits having a predetermined level among some data bits of one burst length is greater than or equal to a predetermined number, and may disable each of the data control flag signals DBIF<1:m> when the number is less than the predetermined number.

The plurality of input/output circuits221,222,223,224, . . . ,22n-1and22nmay invert the data GIO1<1> to GIOm<n> based on the data control flag signals DBIF<1:m> which are enabled, and may output the inverted data to the data buses DQ<1:n>. The plurality of input/output circuits221,222,223,224, . . . ,22n-1, and22nmay not-invert the data GIO1<1> to GIOm<n> based on the data control flag signals DBIF<1:m> which are disabled, and may output the not-inverted data to the data buses DQ<1:n>. In order to provide notification of whether the data GIO1<1> to GIOm<n> transmitted through the data transmission lines250are inverted by the plurality of input/output circuits221,222,223,224, . . . ,22n-1and22nand thus the inverted data are outputted to the data buses DQ<1:n> or are not-inverted and thus the not-inverted data are outputted to the data buses DQ<1:n>, the data control flag signals DBIF<1:m> may be outputted to the external apparatus through separate pads and buses.

The plurality of repeaters RPT11, RPT12, . . . , RPT1m, RPT21, RPT22, . . . and RPT2mmay enable the data masking signal based on the data control flag signals DBIF<1:m> which are enabled to block the data GIO1<1:n> to GIOm<1:n> from being outputted to the first and second memory bank regions211and212. The plurality of repeaters RPT11, RPT12, . . . , RPT1m, RPT21, RPT22. . . and RPT2mmay disable the data masking signal based on the data control flag signals DBIF<1:m> which are disabled to output the data GIO1<1:n> to GIOm<1:n> to the first and second memory bank regions211and212.

FIG. 3is a diagram illustrating a representation of an example configuration of the data control circuit240shown inFIG. 2. InFIG. 3, the data control circuit240may include a control signal generator310and a plurality of majority determiners321,322, . . . and32m. The control signal generator310may generate a first bit select signal DBI12and a second bit select signal DBI38based on the operation control signal RDWTP and operation setting signals RDDBI and WTDBI. The operation setting signals RDDBI and WTDBI generated based on the operation setting information of the semiconductor memory apparatus200may be signals generated from, for example, a mode register set which stores information based on a command signal (CMD). The operation setting signals RDDBI and WTDBI may include a data bus inversion setting signal RDDBI which indicates whether to perform a data bus inversion operation in a read operation, and a data masking setting signal WTDBI which indicates whether to perform a data masking operation in a write operation. When the data bus inversion setting signal RDDBI is enabled, the data control circuit240may generate the data control flag signals DBIF<1:m> for a data bus inversion operation. When the data masking setting signal WTDBI is enabled, the data control circuit240may generate the data control flag signals DBIF<1:m> for the data masking operation. The control signal generator310may enable both the first and second bit select signals DBI12and DBI38when the operation control signal RDWTP and the data bus inversion setting signal RDDBI are a state in which they are enabled. The control signal generator310may disable the first bit select signal DBI12and enable the second bit select signal DBI38when the operation control signal RDWTP is disabled and the data masking setting signal WTDBI is enabled.

The plurality of majority determiners321,322, . . . and32mmay receive the data GIO1<1:n>, GIO2<1:n>, . . . and GIOm<1:n>, respectively, of the allocated burst lengths and the first and second bit select signals DBI12and DBI38. The plurality of majority determiners321,322, . . . and32mmay generate the data control flag signals DBIF<1:m> by determining levels of all the bits or some bits of the data GIO1<1:n>, GIO2<1:n>, . . . and GIOm<1:n>, respectively, of the allocated burst lengths, based on the first and second bit select signals DBI12and DBI38. The first bit select signal DBI12may be for selecting partial bits of data received by the plurality of majority determiners321,322, . . . and32m, and the second bit select signal DBI38may be for selecting the remaining bits of data received by the plurality of majority determiners321,322, . . . and32m. For example, when one burst length is configured by eight data bits, that is, when n is 8, the first bit select signal DBI12may be a signal which selects first and second bits among the eight data bits, and the second bit select signal DBI38may be a signal which selects third to eighth bits among the eight data bits. However, the number of bits to be selected by the first and second bit select signals DBI12and DBI38may be changed variously. The first majority determiner321may receive data GIO1<1:n> of the first burst length, and may generate a data control flag signal DBIF<1> by determining levels of all the bits of the data GIO1<1:n> of the first burst length when both the first and second bit select signals DBI12and DBI38are enabled. For example, the first majority determiner321may enable the data control flag signal DBIF<1> when a majority of the first to eighth bits have a high level, and may disable the data control flag signal DBIF<1> when a majority of the first to eighth bits have a low level. The first majority determiner321may receive data GIO1<1:n> of the first burst length, and may generate the data control flag signal DBIF<1> by determining levels of some bits of the data GIO1<1:n> is of the first burst length when the first bit select signal DBI12is disabled and the second bit select signal DBI38is enabled. For example, the first majority determiner321may determine levels of the third to eighth bits of data, may enable the data control flag signal DBIF<1> when the number of data bits having a high level among the third to eighth bits of the data is greater than or equal to the predetermined number, and may disable the data control flag signal DBIF<1> when the number of data bits having a high level among the third to eighth data bits is less than the predetermined number. The second to m{circumflex over ( )}th majority determiners322, . . . and32mmay receive the data GIO2<1:n>, . . . and GIOm<1:n>, respectively, of the allocated burst lengths, and may generate the data control flag signals DBIF<2:m> by determining levels of all the bits or some bits of the received data GIO2<1:n>, . . . and GIOm<1:n>, based on the first and second bit select signals DBI12and DBI38.

FIG. 4is a diagram illustrating a representation of an example configuration of the control signal generator310shown inFIG. 3. InFIG. 4, the control signal generator310may include a first inverter411, a first NAND gate412, a second NAND gate413, a third NAND gate414, a second inverter415, a fourth NAND gate416, a third inverter417, a fifth NAND gate418, a fourth inverter419, and a NOR gate420. The first inverter411may receive the operation control signal RDWTP, invert the operation control signal RDWTP, and output the inverted operation control signal RDWTP. The first NAND gate412may receive the inverted operation control signal RDWTP and the data masking setting signal WTDBI. The second NAND gate413may receive the operation control signal RDWTP and the data bus inversion setting signal RDDBI. The third NAND gate414may receive and perform a NAND operation on the outputs of the first and second NAND gates412and413. The second inverter415may invert the output of the second NAND gate413and output the inverted output. The fourth NAND gate416may receive the outputs of the third NAND gate414and the NOR gate420, and the third inverter417may invert the output of the fourth NAND gate416and generate the second bit select signal DBI38. The fifth NAND gate418may receive the output of the second inverter415and the NOR gate420, and the fourth inverter419may invert the output of the fifth NAND gate418and generate the first bit select signal DBI12. The NOR gate420may receive a training signal TR and a test mode signal TM. The semiconductor memory apparatus200might not perform a data bus inversion operation and the data masking operation during a training operation and a test operation. The NOR gate420may generate an output signal of a low level when even one of the training signal TR and the test mode signal TM is enabled, and may thereby disable the first and second bit select signals DBI12and DBI38to low levels. When the semiconductor memory apparatus200does not perform the training operation or the test operation but a normal operation, the training signal TR and the test mode signal TM may be disabled, and the NOR gate420may output a signal of a high level. If the data bus inversion setting signal RDDBI is enabled to a high level and the operation control signal RDWTP is enabled to a high level, the fourth and fifth NAND gates416and418receive signals of high levels, and both the first and second bit select signals DBI12and DBI38may be enabled to high levels. If the data masking setting signal WTDBI is enabled to a high level and the operation control signal RDWTP is disabled to a low level, the fourth NAND gate416may receive a signal of the high level, but the fifth NAND gate418may receive a signal of a low level. Therefore, the first bit select signal DBI12may be disabled to the low level, and the second bit select signal DBI38may be enabled to the high level.

FIG. 5is a diagram illustrating an example configuration of the first majority determiner321shown inFIG. 3. The second to m{circumflex over ( )}th majority determiners322, . . . and32mshown inFIG. 3may have substantially the same configuration as the first majority determiner321except for the data received therein. The first majority determiner321may include a data bit selector510and a decoder520. The data bit selector510may receive the data GIO1<1:8> of the first burst length and the first and second bit select signals DBI12and DBI38. The data bit selector510may include a plurality of AND gates. When data configuring of one burst length is eight, the data bit selector510may include eight AND gates. First and second AND gates511and512may receive allocated data GIO1<1:2>, respectively, and the first bit select signal DBI12. The first and second AND gates511and512may output the allocated data GIO1<1:2>, respectively, when the first bit select signal DBI12is enabled, and may block the allocated data GIO1<1:2>, respectively, from being outputted when the first bit select signal DBI12is disabled. Third to eighth AND gates513,514,515,516,517, and518may receive allocated data GIO1<3:8>, respectively, and the second bit select signal DBI38. The third to eighth AND gates513,514,515,516,517and518may output the allocated data GIO1<3:8>, respectively, when the second bit select signal DBI38is enabled, and may block the allocated data GIO1<3:8>, respectively, from being outputted when the second bit select signal DBI38is disabled. Thus, the data bit selector510may output all bits of received data GIO1<1:8> when both the first and second bit select signals DBI12and DBI38are enabled. Further, the data bit selector510may output some of the received data bits when the first bit select signal DBI12is disabled and the second bit select signal is enabled.

The decoder520may receive and decode the outputs of the data bit selector510. The decoder520may enable the data control flag signal DBIF<1> when the majority of bits has the predetermined level among the outputs of the data bit selector510in a read operation, and may disable the data control flag signal DBIF<1> when the number of bits is not a majority. The decoder520may enable the data control flag signal DBIF<1> when the number of bits having the predetermined level among the outputs of the data bit selector510in the write operation is greater than or equal to the predetermined number, and may disable the data control flag signal DBIF<1> when the number of bits is less than the predetermined number. For example, the decoder520may enable the data control flag signal DBIF<1> when at least five bits among the outputs of the data bit selector510are a logic high level, and may disable the data control flag signal DBIF<1> when at most four bits among the outputs of the data bit selector510are the logic high level.

FIG. 6is a diagram illustrating a representation of an example configuration of a read multiplexer600in accordance with an embodiment. The read multiplexer600may be applied as a portion of the plurality of input/output circuits221,222,223,224, . . . ,22n-1, and22nshown inFIG. 2. The read multiplexer600may include first to fifth inverters611,612,613,614, and615and a pass gate616. The first inverter611may invert an allocated data control flag signal DBIF<k> (k is an integer between 1 and m) and output or provide an output. The second inverter612may invert allocated data GIOk<I> (I is an integer between 1 and n) and provide an output. The third inverter613may invert the output of the first inverter611and provide an output. The fourth inverter614may be a tri-state inverter having a PMOS terminal controlled by the output of the first inverter611and an NMOS terminal is controlled by the output of the third inverter613. The fourth inverter614may invert the output of the second inverter612and provide an output, by being turned on when the allocated data control flag signal DBIF<k> is enabled to a high level. The pass gate616may be controlled by the output of the third inverter613in the PMOS terminal thereof and may be controlled by the output of the first inverter611in the NMOS terminal thereof. The pass gate616may output the output of the second inverter612by being turned on when the allocated data control flag signal DBIF<k> is disabled to a low level. The fifth inverter615may be coupled in common with the pass gate616and the output terminal of the fourth inverter614. Further, the fifth inverter615invert the output of the pass gate616or the fourth inverter614, and generate an output signal DOUT. Therefore, the read multiplexer600may invert the allocated data GIOk<I> and output the inverted data as the output signal DOUT when the allocated data control flag signal DBIF<k> is enabled, and may not-invert the allocated data GIOk<I> and output the not-inverted data as the output signal DOUT when the allocated data control flag signal DBIF<k> is disabled. The inverted and not-inverted data may be output to the data bus104(seeFIG. 1).

FIG. 7is a diagram illustrating a representation of an example configuration of a write multiplexer700in accordance with an embodiment. The write multiplexer700may be applied as a portion of the plurality of repeaters RPT11, RPT12, . . . , RPT1m, RPT21, RPT22, . . . and RPT2mshown inFIG. 2. The write multiplexer700may receive an allocated data control flag signal DBIF<k> and a strobe pulse signal STBP. InFIG. 2, the plurality of repeaters RPT11, RPT12, . . . , RPT1m, RPT21, RPT22, . . . and RPT2mmay drive and/or repeat received data in synchronization with the strobe pulse signal STBP, and may selectively output the repeated data based on the data masking signal DM. The write multiplexer700may include first to sixth inverters711,712,713,714,715and716. The first inverter711may invert the strobe pulse signal STBP and provide an output. The second inverter712may be a tri-state inverter having a PMOS terminal controlled by the output of the first inverter711and an NMOS terminal is controlled by the strobe pulse signal STBP. The second inverter712may invert the allocated data control flag signal DBIF<k> and provide an output, when the strobe pulse signal STBP is enabled to a high level. The third inverter713may invert the output of the second inverter712and drive a node721. The fourth inverter714may be a tri-state inverter having a PMOS terminal controlled by the strobe pulse signal STBP and an NMOS terminal controlled by the output of the first inverter711. The fourth inverter714may latch the voltage level of the node721together with the third inverter713when the strobe pulse signal STBP is disabled to a low level. The fifth and sixth inverters715and716may sequentially invert the voltage level of the node721and generate the data masking signal DM. Therefore, the write multiplexer700may generate the data masking signal DM based on the allocated data control flag signal DBIF<k> when the strobe pulse signal STBP is enabled, and may retain the level of the data masking signal DM when the strobe pulse signal STBP is disabled. In other words, the write multiplexer700may enable the data masking signal DM when the data control flag signal DBIF<k> is in an enabled state, and may disable the data masking signal DM when the data control flag signal DBIF<k> is in a disabled state. Thus, inFIG. 2, the plurality of repeaters RPT11, RPT12, . . . , RPT1m, RPT21, RPT22, . . . and RPT2mmay receive the data masking signal DM, and may output the data GIO1<1:n> to GIOm<1:n> received through the data transmission lines250, selectively to the first and second memory bank regions211and212.

While various embodiments have been described above, it will be understood to those skilled in the art that the embodiments described are examples only. Accordingly, the data control circuit, and the semiconductor apparatus and the semiconductor system including the same described herein should not be limited based on the described embodiments.