SEMICONDUCTOR DEVICE

A semiconductor device includes a semiconductor body having first and second surfaces opposite to each other. The semiconductor body includes a first well region having a first conductivity type, second and third well regions spaced apart from each other in a first direction with the first well region interposed therebetween and having a second conductivity type, first doped regions spaced apart from each other in a second direction intersecting the first direction in the first well region, a second doped region, which is adjacent to the second well region and has the second conductivity type, and a third doped region, which is adjacent to the third well region and has the second conductivity type. The second surface of the semiconductor body includes bottom surfaces of the first to third well regions, the plurality of first doped regions, the second doped region, and the third doped region.

CROSS-REFERENCE TO RELATED APPLICATIONS

This U.S. non-provisional patent application claims priority under 35 U.S.C. § 119 to Korean Patent Application No. 10-2022-0043345, filed on Apr. 7, 2022, and Korean Patent Application No. 10-2022-0131369, filed on Oct. 13, 2022, in the Korean Intellectual Property Office, the entire contents of which are hereby incorporated by reference.

BACKGROUND OF THE INVENTION

The present disclosure relates to a semiconductor device including a bipolar junction transistor.

A semiconductor device may include an integrated circuit including metal-oxide-semiconductor (MOS) field effect transistors (MOSFETs) and upper interconnection lines connected to the MOS field effect transistors. The MOS field effect transistors and the upper interconnection lines may be disposed on a top surface of a semiconductor substrate. As a size and a design rule of semiconductor devices have been reduced, the MOS field effect transistors and the upper interconnection lines have been scaled down. Operating characteristics of semiconductor devices may be diminished by the scale-down of the MOS field effect transistors and the upper interconnection lines. Thus, various methods for forming a semiconductor device, which has desirable performance characteristics while overcoming limitations caused by high integration have been studied. For example, a semiconductor device may further include lower interconnection lines disposed on a bottom surface of the semiconductor substrate, and a through-electrode penetrating the semiconductor substrate and connecting the lower interconnection lines to the MOS field effect transistors and the upper interconnection lines. A reduction in thickness of the semiconductor substrate may be required to form the through-electrode, and in this case, an operable bipolar junction transistor structure compatible with the through-electrode may be desired.

SUMMARY

Embodiments of the inventive concepts may provide a semiconductor device including a bipolar junction transistor capable of being realized in a relatively thin semiconductor body.

Embodiments of the inventive concepts may also provide a semiconductor device including a bipolar junction transistor capable of relatively easy control of operating characteristics.

In an aspect, a semiconductor device may include a semiconductor body having a first surface and a second surface which are opposite to each other. The semiconductor body may include a first well region having a first conductivity type: a second well region and a third well region, which are spaced apart from each other in a first direction with the first well region interposed therebetween and have a second conductivity type different from the first conductivity type; a plurality of first doped regions spaced apart from each other in a second direction intersecting the first direction in the first well region, the plurality of first doped regions having the first conductivity type, wherein a concentration of dopants having the first conductivity type in each of the plurality of first doped regions is greater than a concentration of dopants having the first conductivity type in the first well region; a second doped region, which is adjacent to the second well region and has the second conductivity type; and a third doped region, which is adjacent to the third well region and has the second conductivity type. The second well region may be disposed between the first well region and the second doped region, and the third well region may be disposed between the first well region and the third doped region. The second surface of the semiconductor body may include bottom surfaces of the first to third well regions, the plurality of first doped regions, the second doped region, and the third doped region.

In an aspect, a semiconductor device may include a semiconductor body having a first surface and a second surface, which are opposite to each other. The semiconductor body may include a first well region having a first conductivity type: a second well region and a third well region, which are spaced apart from each other in a first direction with the first well region interposed therebetween and have a second conductivity type different from the first conductivity type; a plurality of first doped regions spaced apart from each other in a second direction intersecting the first direction in the first well region, the plurality of first doped regions having the first conductivity type; first contacts on the plurality of first doped regions, respectively; a second doped region, which is adjacent to the second well region and has the second conductivity type; and a third doped region, which is adjacent to the third well region and has the second conductivity type. The second well region may be between the first well region and the second doped region, and the third well region may be between the first well region and the third doped region. The first surface of the semiconductor body includes top surfaces of the first to third well regions, the plurality of first doped regions, the second doped region, and the third doped region. The second surface of the semiconductor body includes bottom surfaces of the first to third well regions, the plurality of first doped regions, the second doped region, and the third doped region.

In an aspect, a semiconductor device may include a semiconductor body having a first surface and a second surface which are opposite to each other, and isolation patterns penetrating the semiconductor body. The semiconductor body may include: first well regions having a first conductivity type, the first well regions extending in a first direction and spaced apart from each other in a second direction intersecting the first direction: a second well region on a side surface of each of the first well regions and having a second conductivity type different from the first conductivity type; first doped regions in each of the first well regions and spaced apart from each other in the first direction, the first doped regions having the first conductivity type, wherein a concentration of dopants having the first conductivity type in the first doped regions is greater than a concentration of dopants having the first conductivity type in the first well regions; and a second doped region in each of the first well regions and between the first doped regions, the second doped region having the second conductivity type, wherein a concentration of dopants having the second conductivity type in the second doped region is greater than a concentration of dopants having the second conductivity type in the second well region. The isolation patterns may penetrate each of the first well regions and may be between the second doped region and the first doped regions. Bottom surfaces of the isolation patterns may be at a same height in a third direction perpendicular to a plane formed by the first direction and the second direction as the second surface of the semiconductor body.

DETAILED DESCRIPTION

Embodiments of the inventive concepts will now be described more fully with reference to the accompanying drawings. The present disclosure may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Like reference numerals refer to like elements throughout this application. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items. It is noted that aspects described with respect to one embodiment may be incorporated in different embodiments although not specifically described relative thereto. That is, all embodiments and/or features of any embodiments can be combined in any way and/or combination.

FIG.1is a plan view illustrating a semiconductor device according to some embodiments of the inventive concepts.FIG.2Ais a cross-sectional view taken along a line A-A′ ofFIG.1, andFIG.2Bis a cross-sectional view taken along a line B-B′ ofFIG.1.

Referring toFIGS.1,2A, and2B, a semiconductor body SB having a first surface S1and a second surface S2, which are opposite to each other may be provided. The semiconductor body SB may include a semiconductor material (e.g., silicon and/or germanium). The semiconductor body SB may include a first well region110having a first conductivity type, and a second well region130and a third well region140which are disposed at both sides of the first well region110and have a second conductivity type different from the first conductivity type. The second well region130and the third well region140may be spaced apart from each other in a first direction D1with the first well region110interposed therebetween, and the first to third well regions110,130, and140may extend in a second direction D2. The first direction D1and the second direction D2may be parallel to the first surface S1of the semiconductor body SB and may intersect each other. For some examples, the first conductivity type may be an N-type, and the second conductivity type may be a P-type. For certain examples, the first conductivity type may be a P-type, and the second conductivity type may be an N-type. Top surfaces of the first well region110, the second well region130, and the third well region140may correspond to the first surface S1of the semiconductor body SB, and bottom surfaces of the first well region110, the second well region130and the third well region140may correspond to the second surface S2of the semiconductor body SB.

The semiconductor body SB may further include a plurality of first doped regions120disposed in the first well region110. The plurality of first doped regions120may be spaced apart from each other in the second direction D2in the first well region110. In some embodiments, the plurality of first doped regions120may extend in the first direction D1. For example, each of the plurality of first doped regions120may have a bar shape extending in the first direction D1. Each of the plurality of first doped regions120may have a length120L in the first direction D1and a width120A in the second direction D2. The length120L of each of the plurality of first doped regions120may be greater than the width120A of each of the plurality of first doped regions120. In some embodiments, a distance120S in the second direction D2between adjacent two of the plurality of first doped regions120may be greater than the width120A of each of the plurality of first doped regions120. In some embodiments, each of the plurality of first doped regions120may penetrate the first well region110in a third direction D3. The third direction D3may be perpendicular to the first surface S1of the semiconductor body SB. The first well region110may extend in the first direction D1between the plurality of first doped regions120.

Top surfaces of the plurality of first doped regions120may correspond to the first surface S1of the semiconductor body SB, and bottom surfaces of the plurality of first doped regions120may correspond to the second surface S2of the semiconductor body SB. The plurality of first doped regions120may have the first conductivity type. A concentration of dopants having the first conductivity type in each of the plurality of first doped regions120may be greater than a concentration of dopants having the first conductivity type in the first well region110.

The semiconductor body SB may further include a second doped region150, which is adjacent to the second well region130and has the second conductivity type, and a third doped region160which is adjacent to the third well region140and has the second conductivity type. The second well region130may be disposed between the first well region110and the second doped region150. The second doped region150may be spaced apart from the first well region110in the first direction D1with the second well region130interposed therebetween and may extend in the second direction D2. The second doped region150and the first well region110may be in contact with both side surfaces of the second well region130, respectively. The third well region140may be disposed between the first well region110and the third doped region160. The third doped region160may be spaced apart from the first well region110in the first direction D1with the third well region140interposed therebetween and may extend in the second direction D2. The third doped region160and the first well region110may be in contact with both side surfaces of the third well region140, respectively. Side surfaces of the first to third well regions110,130and140, the second doped region150and the third doped region160may be in contact with each other in the first direction D1. Top surfaces of the second doped region150and the third doped region160may correspond to the first surface S1of the semiconductor body SB, and bottom surfaces of the second doped region150and the third doped region160may correspond to the second surface S2of the semiconductor body SB.

A concentration of dopants having the second conductivity type in the second doped region150may be greater than a concentration of dopants having the second conductivity type in the second well region130, and a concentration of dopants having the second conductivity type in the third doped region160may be greater than a concentration of dopants having the second conductivity type in the third well region140. The concentration of the dopants having the second conductivity type in the second well region130may be equal to or different from the concentration of the dopants having the second conductivity type in the third well region140. For some examples, the concentration of the dopants having the second conductivity type in the second well region130may be greater than the concentration of the dopants having the second conductivity type in the third well region140. For certain examples, the concentration of the dopants having the second conductivity type in the second well region130may be less than the concentration of the dopants having the second conductivity type in the third well region140.

First contacts CT1, second contacts CT2and third contacts CT3may be disposed on the first surface S1of the semiconductor body SB. The first contacts CT1may be disposed on the plurality of first doped regions120and may be electrically connected to the plurality of first doped regions120. The first contacts CT1may be spaced apart from each other in the first direction D1and the second direction D2. First contacts CT1, spaced apart from each other in the first direction D1, of the first contacts CT1may be disposed on a corresponding first doped region of the plurality of first doped regions120and may be connected in common to the corresponding first doped region. First contacts CT1, spaced apart from each other in the second direction D2, of the first contacts CT1may be disposed on the plurality of first doped regions120, respectively, and may be connected to the plurality of first doped regions120, respectively. The plurality of first doped regions120and the first contacts CT1may constitute a plurality of bases of a bipolar junction transistor.

The second contacts CT2may be disposed on the second doped region150and may be electrically connected to the second doped region150. The second doped region150and the second contacts CT2may constitute an emitter of the bipolar junction transistor. The third contacts CT3may be disposed on the third doped region160and may be electrically connected to the third doped region160. The third doped region160and the third contacts CT3may constitute a collector of the bipolar junction transistor. The first contacts CT1, the second contacts CT2and the third contacts CT3may include a conductive material (e.g., a metal).

A plurality of gate structures GS may be disposed on the first surface S1of the semiconductor body SB. The plurality of gate structures GS is omitted inFIG.1for the purpose of ease and convenience in illustration. The plurality of gate structures GS may be spaced apart from each other in the first direction D1and may extend in the second direction D2. The first contacts CT1, the second contacts CT2and the third contacts CT3may be disposed between the plurality of gate structures GS.

Each of the plurality of gate structures GS may include a gate electrode GE extending in the second direction D2, a gate dielectric pattern GI between the gate electrode GE and the first surface S1of the semiconductor body SB, gate spacers GSP on side surfaces of the gate electrode GE, and a gate capping pattern CAP on a top surface of the gate electrode GE. The gate dielectric pattern GI may extend between the gate electrode GE and the gate spacers GSP, and a topmost surface of the gate dielectric pattern GI may be substantially coplanar with the top surface of the gate electrode GE. The gate capping pattern CAP may extend onto top surfaces of the gate spacers GSP. The gate electrode GE may include a doped semiconductor material, a conductive metal nitride, and/or a metal. The gate dielectric pattern GI may include a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, and/or a high-k dielectric layer. The high-k dielectric layer may include a material (e.g., a hafnium oxide (HfO) layer, an aluminum oxide (AlO) layer, or a tantalum oxide (TaO) layer) of which a dielectric constant is higher or greater than that of a silicon oxide layer. Each of the gate spacers GSP and the gate capping pattern CAP may include a silicon oxide layer, a silicon nitride layer, and/or a silicon oxynitride layer. The plurality of gate structures GS may be electrically floated dummy gate structures.

An upper interlayer insulating layer180may be disposed on the first surface S1of the semiconductor body SB and may cover the plurality of gate structures GS and the first to third contacts CT1, CT2, and CT3. The plurality of gate structures GS and the first to third contacts CT1, CT2, and CT3may penetrate the upper interlayer insulating layer180in the third direction D3. For example, the upper interlayer insulating layer180may include a silicon oxide layer, a silicon nitride layer, and/or a silicon oxynitride layer.

A lower insulating layer170may be disposed on the second surface S2of the semiconductor body SB. For example, the lower insulating layer170may include a silicon oxide layer, a silicon nitride layer, and/or a silicon oxynitride layer.

A first voltage may be applied to the second contacts CT2, and a second voltage may be applied to the first contacts CT1and the third contacts CT3. The second voltage may be different from the first voltage and may be, for example, a ground voltage. In this case, a first current IC may flow from the emitter constituted by the second contacts CT2and the second doped region150to the collector constituted by the third doped region160and the third contacts CT3. In addition, a second current IB may flow from the emitter constituted by the second contacts CT2and the second doped region150to the plurality of bases constituted by the plurality of first doped regions120and the first contacts CT1. Thus, the bipolar junction transistor may operate in this manner.

The first current IC and the second current IB may be controlled by adjusting the length120L and the width120A of the plurality of first doped regions120and the distance120S between the plurality of first doped regions120. For some examples, the second current IB may be increased by increasing the length120L of the plurality of first doped regions120. For certain examples, the first current IC may be increased by increasing the distance120S between the plurality of first doped regions120. For certain examples, when the distance120S between the plurality of first doped regions120is greater than the width120A of the plurality of first doped regions120, the first current IC may be increased.

According to some embodiments of the inventive concepts, the side surfaces of the first to third well regions110,130and140, the plurality of first doped regions120, the second doped region150and the third doped region160may be in contact with each other in a horizontal direction (e.g., in the first direction D1and the second direction D2), and the plurality of first doped regions120may be spaced apart from each other in the second direction D2in the first well region110. Top surfaces of the first to third well regions110,130and140and the first to third doped regions120,150and160may constitute the first surface S1of the semiconductor body SB, and bottom surfaces of the first to third well regions110,130and140and the first to third doped regions120,150and160may constitute the second surface S2of the semiconductor body SB. In this case, even though a thickness of the semiconductor body SB in the third direction D3is relatively thin, the bipolar junction transistor operable in the semiconductor body SB may be easily realized. In addition, a current (e.g., the first current IC and the second current IB) flowing through the bipolar junction transistor may be controlled by adjusting the length120L and the width120A of the plurality of first doped regions120and the distance120S between the plurality of first doped regions120, and thus operating characteristics of the bipolar junction transistor may be easily controlled.

FIGS.3A and3Bare cross-sectional views corresponding to the lines A-A′ and B-B′ ofFIG.1, respectively, to illustrate a semiconductor device according to some embodiments of the inventive concepts. Hereinafter, differences between the present embodiments and the above embodiments ofFIGS.1,2A, and2Bwill be mainly described for the purpose of ease and convenience in explanation.

Referring toFIGS.1,3A, and3B, the semiconductor body SB may further include a plurality of first doped patterns125penetrating each of the plurality of first doped regions120. The plurality of first doped patterns125may be spaced apart from each other in the first direction D1in a corresponding first doped region120of the plurality of first doped regions120and may be disposed under the first contacts CT1arranged in the first direction D1, respectively. The plurality of first doped patterns125may be electrically connected to the first contacts CT1arranged in the first direction D1, respectively. In some embodiments, each of the plurality of first doped patterns125may penetrate the corresponding first doped region120in the third direction D3. Top surfaces of the plurality of first doped patterns125may correspond to the first surface S1of the semiconductor body SB, and bottom surfaces of the plurality of first doped patterns125may correspond to the second surface S2of the semiconductor body SB.

The plurality of first doped patterns125may have the first conductivity type and may be epitaxial patterns formed by an epitaxial growth process. A concentration of dopants having the first conductivity type in each of the plurality of first doped patterns125may be equal to or greater than the concentration of the dopants having the first conductivity type in each of the plurality of first doped regions120. The plurality of first doped patterns125may be used to reduce a contact resistance between the first contacts CT1and the plurality of first doped regions120.

The semiconductor body SB may further include second doped patterns155penetrating the second doped region150, and third doped patterns165penetrating the third doped region160.

The second doped patterns155may be spaced apart from each other in the second doped region150and may be disposed under the second contacts CT2, respectively. The second doped patterns155may be electrically connected to the second contacts CT2, respectively. In some embodiments, each of the second doped patterns155may penetrate the second doped region150in the third direction D3. Top surfaces of the second doped patterns155may correspond to the first surface S1of the semiconductor body SB, and bottom surfaces of the second doped patterns155may correspond to the second surface S2of the semiconductor body SB. The second doped patterns155may have the second conductivity type and may be epitaxial patterns formed by an epitaxial growth process. A concentration of dopants having the second conductivity type in each of the second doped patterns155may be equal to or greater than the concentration of the dopants having the second conductivity type in the second doped region150. The second doped patterns155may be used to reduce a contact resistance between the second contacts CT2and the second doped region150.

The third doped patterns165may be spaced apart from each other in the third doped region160and may be disposed under the third contacts CT3, respectively. The third doped patterns165may be electrically connected to the third contacts CT3, respectively. In some embodiments, each of the third doped patterns165may penetrate the third doped region160in the third direction D3. Top surfaces of the third doped patterns165may correspond to the first surface S1of the semiconductor body SB, and bottom surfaces of the third doped patterns165may correspond to the second surface S2of the semiconductor body SB. The third doped patterns165may have the second conductivity type and may be epitaxial patterns formed by an epitaxial growth process. A concentration of dopants having the second conductivity type in each of the third doped patterns165may be equal to or greater than the concentration of the dopants having the second conductivity type in the third doped region160. The third doped patterns165may be used to reduce a contact resistance between the third contacts CT3and the third doped region160.

Except for the differences described above, other components and features of the semiconductor device according to the present embodiments may be substantially the same as corresponding components and features of the semiconductor device described with reference toFIGS.1,2A, and2B.

FIG.4is a plan view illustrating a semiconductor device according to some embodiments of the inventive concepts.FIG.5Ais a cross-sectional view taken along a line A-A′ ofFIG.4, andFIG.5Bis a cross-sectional view taken along a line B-B′ ofFIG.4. Hereinafter, differences between the present embodiments and the above embodiments ofFIGS.1,2A, and2Bwill be mainly described for the purpose of ease and convenience in explanation.

Referring toFIGS.4,5A, and5B, the semiconductor body SB may include a plurality of first doped patterns125disposed in the first well region110. In some embodiments, the plurality of first doped regions120described with reference toFIGS.1,2A, and2Bmay be omitted. The plurality of first doped patterns125may be spaced apart from each other in the first direction D1and the second direction D2in the first well region110and may be disposed under the first contacts CT1, respectively. The plurality of first doped patterns125may be electrically connected to the first contacts CT1, respectively. In some embodiments, each of the plurality of first doped patterns125may penetrate the first well region110in the third direction D3. Top surfaces of the plurality of first doped patterns125may correspond to the first surface S1of the semiconductor body SB, and bottom surfaces of the plurality of first doped patterns125may correspond to the second surface S2of the semiconductor body SB.

The plurality of first doped patterns125may have the first conductivity type and may be epitaxial patterns formed by an epitaxial growth process. A concentration of dopants having the first conductivity type in the plurality of first doped patterns125may be greater than the concentration of the dopants having the first conductivity type in the first well region110. The plurality of first doped patterns125may also be referred to as a plurality of first doped regions. According to the present embodiments, the plurality of first doped patterns125and the first contacts CT1may constitute a plurality of bases of a bipolar junction transistor.

The semiconductor body SB may further include second doped patterns155penetrating the second doped region150, and third doped patterns165penetrating the third doped region160. The second doped patterns155and the third doped patterns165may be substantially the same as the second doped patterns155and the third doped patterns165described with reference toFIGS.1,3A, and3B.

Except for the differences described above, other components and features of the semiconductor device according to the present embodiments may be substantially the same as corresponding components and features of the semiconductor device described with reference toFIGS.1,2A and2B.

FIGS.6A and6Bare cross-sectional views corresponding to the lines A-A′ and B-B′ ofFIG.4, respectively, to illustrate a semiconductor device according to some embodiments of the inventive concepts. Hereinafter, differences between the present embodiments and the above embodiments ofFIGS.4,5A, and5Bwill be mainly described for the purpose of ease and convenience in explanation.

Referring toFIGS.4,6A, and6B, according to some embodiments, each of the first doped patterns125may penetrate a portion of the first well region110in the third direction D3. Top surfaces of the plurality of first doped patterns125may correspond to the first surface S1of the semiconductor body SB, and bottom surfaces of the plurality of first doped patterns125may be located at a height higher than the second surface S2of the semiconductor body SB. As used herein, the ‘height’ may be a distance measured from the second surface S2of the semiconductor body SB in the third direction D3. The first well region110may extend under the plurality of first doped patterns125and may at least partially cover the bottom surfaces of the plurality of first doped patterns125. Each of the plurality of first doped patterns125may have a thickness125T in the third direction D3, and the thickness125T of each of the plurality of first doped patterns125may be less than a thickness SB_T of the semiconductor body SB in the third direction D3.

Each of the second doped patterns155may penetrate a portion of the second doped region150in the third direction D3. Top surfaces of the second doped patterns155may correspond to the first surface S1of the semiconductor body SB, and bottom surfaces of the second doped patterns155may be located at a height higher than the second surface S2of the semiconductor body SB. The second doped region150may extend under the second doped patterns155and may cover the bottom surfaces of the second doped patterns155. Each of the second doped patterns155may have a thickness155T in the third direction D3, and the thickness155T of each of the second doped patterns155may be less than the thickness SB_T of the semiconductor body SB in the third direction D3.

Each of the third doped patterns165may penetrate a portion of the third doped region160in the third direction D3. Top surfaces of the third doped patterns165may correspond to the first surface S1of the semiconductor body SB, and bottom surfaces of the third doped patterns165may be located at a height higher than the second surface S2of the semiconductor body SB. The third doped region160may extend under the third doped patterns165and may cover the bottom surfaces of the third doped patterns165. Each of the third doped patterns165may have a thickness165T in the third direction D3, and the thickness165T of each of the third doped patterns165may be less than the thickness SB_T of the semiconductor body SB in the third direction D3.

Except for the differences described above, other components and features of the semiconductor device according to the present embodiments may be substantially the same as corresponding components and features of the semiconductor device described with reference toFIGS.4,5A, and5B.

FIG.7is a plan view illustrating a semiconductor device according to some embodiments of the inventive concepts.FIG.8Ais a cross-sectional view taken along a line A-A′ ofFIG.7,FIG.8Bis a cross-sectional view taken along a line B-B′ ofFIG.7, andFIG.8Cis a cross-sectional view taken along a line C-C′ ofFIG.7. Hereinafter, differences between the present embodiments and the above embodiments ofFIGS.1,2A, and2Bwill be mainly described for the purpose of ease and convenience in explanation.

Referring toFIGS.7,8A,8B and8C, the first well region110may have a width110W in the first direction D1, and the width110W of the first well region110may be less than the length120L of each of the plurality of first doped regions120. An end portion of each of the plurality of first doped regions120may extend into the second well region130and may penetrate the second well region130. Another end portion of each of the plurality of first doped regions120may extend into the third well region140and may penetrate the third well region140.

First contacts CT1, spaced apart from each other in the first direction D1, of the first contacts CT1may be disposed on a corresponding first doped region of the plurality of first doped regions120and may be connected in common to the corresponding first doped region. First contacts CT1, spaced apart from each other in the second direction D2, of the first contacts CT1may be disposed on the plurality of first doped regions120, respectively, and may be connected to the plurality of first doped regions120, respectively. The plurality of first doped regions120and the first contacts CT1may constitute a plurality of bases of a bipolar junction transistor.

According to the present embodiments, the width110W of the first well region110may be less than the length120L of each of the plurality of first doped regions120, and in this case, the first current IC flowing from the emitter constituted by the second contacts CT2and the second doped region150to the collector constituted by the third doped region160and the third contacts CT3may be increased. In addition, the second current IB flowing from the emitter constituted by the second contacts CT2and the second doped region150to the plurality of bases constituted by the plurality of first doped regions120and the first contacts CT1may be reduced. As a result, a current (e.g., the first current IC and the second current IB) flowing through the bipolar junction transistor may be controlled by adjusting the width110W of the first well region110and the length120L of each of the plurality of first doped regions120, and thus operating characteristics of the bipolar junction transistor may be easily controlled.

FIG.9is a plan view illustrating a semiconductor device according to some embodiments of the inventive concepts.FIG.10Ais a cross-sectional view taken along a line A-A′ ofFIG.9,FIG.10Bis a cross-sectional view taken along a line B-B′ ofFIG.9, andFIG.10Cis a cross-sectional view taken along a line C-C′ ofFIG.9. Hereinafter, differences between the present embodiments and the above embodiments ofFIGS.1,2A, and2B will be mainly described for the purpose of ease and convenience in explanation.

Referring toFIGS.9,10A,10B, and10C, the first well region110may include a first portion110P1having a first width110W1in the first direction D1and a second portion110P2having a second width110W2in the first direction D1, and the first width110W1and the second width110W2may be different from each other. Some of the plurality of first doped regions120may be disposed in the first portion110P1of the first well region110and may penetrate the first portion110P1of the first well region110in the third direction D3. Others of the plurality of first doped regions120may be disposed in the second portion110P2of the first well region110and may penetrate the second portion110P2of the first well region110in the third direction D3.

For example, the first width110W1may be less than the second width110W2. In this case, a first current IC1flowing through the first portion110P1of the first well region110may be greater than a first current IC2flowing through the second portion110P2of the first well region110. In addition, a second current IB1flowing through the first portion110P1of the first well region110may be less than a second current IB2flowing through the second portion110P2of the first well region110. As a result, a current (e.g., the first current IC and the second current IB) flowing through the bipolar junction transistor may be controlled because the first well region110is formed to include the first and second portions110P1and110P2having the different widths110W1and110W2, and thus operating characteristics of the bipolar junction transistor may be easily controlled.

FIGS.11to16are cross-sectional views corresponding to the line A-A′ ofFIG.1to illustrate a method of manufacturing a semiconductor device according to some embodiments of the inventive concepts. Hereinafter, the descriptions of the same features as mentioned with reference toFIGS.1,2A, and2Bwill be omitted for the purpose of ease and convenience in explanation.

Referring toFIG.11, first semiconductor layers102and second semiconductor layers104may be alternately stacked on a substrate100. The substrate100may be a semiconductor substrate. The first semiconductor layers102may include, for example, silicon, and the second semiconductor layers104may include, for example, silicon-germanium.

Referring toFIGS.1and12, a first well region110, a second well region130and a third well region140may be formed in the first semiconductor layers102and the second semiconductor layers104. For example, the formation of the second well region130and the third well region140may include injecting dopants having a second conductivity type into the first semiconductor layers102and the second semiconductor layers104. A concentration of the dopants having the second conductivity type in the second well region130may be equal to a concentration of the dopants having the second conductivity type in the third well region140. For example, the formation of the first well region110may include injecting dopants having a first conductivity type into the first semiconductor layers102and the second semiconductor layers104between the second well region130and the third well region140. The first well region110, the second well region130and the third well region140may constitute a semiconductor body SB, and side surfaces of the first well region110, the second well region130and the third well region140may be in contact with each other in the first direction D1.

Referring toFIGS.1and13, a plurality of first doped regions120may be formed in the first well region110. The plurality of first doped regions120may be spaced apart from each other in the second direction D2in the first well region110and may extend in the first direction D1. Each of the plurality of first doped regions120may penetrate the first well region110in the third direction D3. For example, the formation of the plurality of first doped regions120may include injecting dopants having the first conductivity type into the first well region110. A concentration of the dopants having the first conductivity type in each of the plurality of first doped regions120may be greater than a concentration of the dopants having the first conductivity type in the first well region110.

Referring toFIGS.1and14, in some embodiments, dopants having the second conductivity type may be additionally injected into the second well region130or the third well region140. In this case, the concentration of the dopants having the second conductivity type in the second well region130may be different from the concentration of the dopants having the second conductivity type in the third well region140.

A second doped region150may be formed in the second well region130. The second doped region150may penetrate the second well region130in the third direction D3. For example, the formation of the second doped region150may include injecting dopants having the second conductivity type into the second well region130. A concentration of the dopants having the second conductivity type in the second doped region150may be greater than the concentration of the dopants having the second conductivity type in the second well region130. A portion of the second well region130may be disposed between the second doped region150and the first well region110.

A third doped region160may be formed in the third well region140. The third doped region160may penetrate the third well region140in the third direction D3. For example, the formation of the third doped region160may include injecting dopants having the second conductivity type into the third well region140. A concentration of the dopants having the second conductivity type in the third doped region160may be greater than the concentration of the dopants having the second conductivity type in the third well region140. A portion of the third well region140may be disposed between the third doped region160and the first well region110.

Side surfaces of the first to third well regions110,130and140, the second doped region150, and the third doped region160may be in contact with each other in the first direction D1. The first to third well regions110,130and140, the plurality of first doped regions120, the second doped region150and the third doped region160may constitute the semiconductor body SB. The semiconductor body SB may have a first surface S1and a second surface S2which are opposite to each other, and the second surface S2of the semiconductor body SB may be adjacent to the substrate100.

Referring toFIGS.1and15, a plurality of gate structures GS may be formed on the first surface S1of the semiconductor body SB. The plurality of gate structures GS may be spaced apart from each other in the first direction D1and may extend in the second direction D2. Each of the plurality of gate structures GS may include a gate electrode GE extending in the second direction D2, a gate dielectric pattern GI between the gate electrode GE and the first surface S1of the semiconductor body SB, gate spacers GSP on side surfaces of the gate electrode GE, and a gate capping pattern CAP on a top surface of the gate electrode GE. The gate dielectric pattern GI may extend between the gate electrode GE and the gate spacers GSP, and a topmost surface of the gate dielectric pattern GI may be substantially coplanar with the top surface of the gate electrode GE. The gate capping pattern CAP may extend onto top surfaces of the gate spacers GSP.

An upper interlayer insulating layer180may be formed on the first surface S1of the semiconductor body SB and may cover the plurality of gate structures GS. First contacts CT1, second contacts CT2and third contacts CT3may be formed in the upper interlayer insulating layer180and between the plurality of gate structures GS. For example, the formation of the first to third contacts CT1, CT2and CT3may include forming first contact holes, second contact holes and third contact holes in the upper interlayer insulating layer180between the plurality of gate structures GS, and forming the first contacts CT1, the second contacts CT2and the third contacts CT3in the first contact holes, the second contact holes and the third contact holes, respectively.

Referring toFIGS.1and16, the substrate100may be removed. For example, the removal of the substrate100may include grinding the substrate100to expose the second surface S2of the semiconductor body SB. Thereafter, as illustrated inFIGS.1and2A, a lower insulating layer170may be formed on the second surface S2of the semiconductor body SB.

FIGS.17to20are cross-sectional views corresponding to the line A-A′ ofFIG.4to illustrate a method of manufacturing a semiconductor device according to some embodiments of the inventive concepts. Hereinafter, differences between the present embodiments and the above embodiments ofFIGS.11to16will be mainly described for the purpose of ease and convenience in explanation.

First, as described with reference toFIGS.11and12, first semiconductor layers102and second semiconductor layers104may be alternately stacked on a substrate100, and a first well region110, a second well region130and a third well region140may be formed in the first semiconductor layers102and the second semiconductor layers104. In some embodiments, as described with reference toFIG.14, dopants having the second conductivity type may be additionally injected into the second well region130or the third well region140. In this case, a concentration of dopants having the second conductivity type in the second well region130may be different from a concentration of dopants having the second conductivity type in the third well region140. A second doped region150may be formed in the second well region130, and a third doped region160may be formed in the third well region140. In some embodiments, the formation of the plurality of first doped regions120described with reference toFIG.13may be omitted.

Referring toFIGS.4and17, the first to third well regions110,130and140, the second doped region150and the third doped region160may constitute a semiconductor body SB. The semiconductor body SB may have a first surface S1and a second surface S2which are opposite to each other, and the second surface S2of the semiconductor body SB may be adjacent to the substrate100.

Sacrificial gate structures SGS may be formed on the first surface S1of the semiconductor body SB. The sacrificial gate structures SGS may be spaced apart from each other in the first direction D1and may extend in the second direction D2. Each of the sacrificial gate structures SGS may include a sacrificial gate pattern SGP and a gate mask pattern MP sequentially stacked on the first surface S1of the semiconductor body SB, and gate spacers GSP on both side surfaces of the sacrificial gate pattern SGP. The gate spacers GSP may extend onto both side surfaces of the gate mask pattern MP. For example, the formation of the sacrificial gate pattern SGP may include forming a sacrificial gate layer (not shown) on the first surface S1of the semiconductor body SB, forming the gate mask pattern MP defining a region, in which the sacrificial gate pattern SGP will be formed, on the sacrificial gate layer, and patterning the sacrificial gate layer using the gate mask pattern MP as an etch mask. The formation of the gate spacers GSP may include forming a gate spacer layer (not shown) covering the gate mask pattern MP and the sacrificial gate pattern SGP on the first surface S1of the semiconductor body SB, and anisotropically etching the gate spacer layer. The sacrificial gate pattern SGP may include, for example, poly-silicon, and the gate mask pattern MP and the gate spacers GSP may include, for example, silicon nitride.

Referring toFIGS.4and18, first doped patterns125may be formed in the first well region110, second doped patterns155may be formed in the second doped region150, and third doped patterns165may be formed in the third doped region160. In some embodiments, a plurality of first doped regions120may be formed in the first well region110as described with reference toFIGS.1and13, and in this case, the first doped patterns125may be formed in the plurality of first doped regions120.

For example, the formation of the first doped patterns125may include patterning the first well region110between the sacrificial gate structures SGS to form first holes penetrating the first well region110, and performing an epitaxial growth process to form the first doped patterns125in the first holes, respectively. The formation of the first doped patterns125may further include injecting dopants having the first conductivity type into the first doped patterns125in the epitaxial growth process or after the epitaxial growth process. A concentration of the dopants having the first conductivity type in the first doped patterns125may be greater than the concentration of the dopants having the first conductivity type in the first well region110. In some embodiments, the first doped patterns125may be formed in the plurality of first doped regions120formed as described with reference toFIGS.1and13, and in this case, the concentration of the dopants having the first conductivity type in the first doped patterns125may be equal to or greater than the concentration of the dopants having the first conductivity type in each of the plurality of first doped regions120.

For example, the formation of the second doped patterns155may include patterning the second doped region150between the sacrificial gate structures SGS to form second holes penetrating the second doped region150, and performing an epitaxial growth process to form the second doped patterns155in the second holes, respectively. The formation of the second doped patterns155may further include injecting dopants having the second conductivity type into the second doped patterns155in the epitaxial growth process or after the epitaxial growth process. A concentration of the dopants having the second conductivity type in each of the second doped patterns155may be equal to or greater than the concentration of the dopants having the second conductivity type in the second doped region150.

For example, the formation of the third doped patterns165may include patterning the third doped region160between the sacrificial gate structures SGS to form third holes penetrating the third doped region160, and performing an epitaxial growth process to form the third doped patterns165in the third holes, respectively. The formation of the third doped patterns165may further include injecting dopants having the second conductivity type into the third doped patterns165in the epitaxial growth process or after the epitaxial growth process. A concentration of the dopants having the second conductivity type in each of the third doped patterns165may be equal to or greater than the concentration of the dopants having the second conductivity type in the third doped region160.

Referring toFIGS.4and19, an upper interlayer insulating layer180may be formed on the first surface S1of the semiconductor body SB to at least partially cover the sacrificial gate structures SGS. Thereafter, the sacrificial gate pattern SGP and the gate mask pattern MP of each of the sacrificial gate structures SGS may be removed. Thus, gap regions180G may be formed in the upper interlayer insulating layer180and between the gate spacers GSP. The gap regions180G may expose the first surface S1of the semiconductor body SB.

Referring toFIGS.4and20, a gate dielectric pattern GI and a gate electrode GE may be formed to fill each of the gap regions180G. The formation of the gate dielectric pattern GI and the gate electrode GE may include forming a gate dielectric layer conformally covering an inner surface of each of the gap regions180G, forming a gate conductive layer filling a remaining portion of each of the gap regions180G, and performing a planarization process on the gate conductive layer and the gate dielectric layer to expose the upper interlayer insulating layer180, thereby locally forming the gate dielectric pattern GI and the gate electrode GE in each of the gap regions180G. Upper portions of the gate dielectric pattern GI, the gate electrode GE and the gate spacers GSP may be recessed to form a groove region in each of the gap regions180G. A gate capping pattern CAP may be formed in the groove region. The formation of the gate capping pattern CAP may include forming a gate capping layer filling the groove region on the upper interlayer insulating layer180, and planarizing the gate capping layer to expose the upper interlayer insulating layer180.

The gate dielectric pattern GI, the gate electrode GE, the gate spacers GSP and the gate capping pattern CAP may be referred to as a gate structure GS.

First contacts CT1, second contacts CT2and third contacts CT3may be formed in the upper interlayer insulating layer180between a plurality of the gate structures GS. For example, the formation of the first to third contacts CT1, CT2, and CT3may include forming first contact holes, second contact holes and third contact holes in the upper interlayer insulating layer180between the plurality of gate structures GS, and forming the first contacts CT1, the second contacts CT2, and the third contacts CT3in the first contact holes, the second contact holes, and the third contact holes, respectively. The first contact holes may expose top surfaces of the first doped patterns125, respectively. The second contact holes may expose top surfaces of the second doped patterns155, respectively, and the third contact holes may expose top surfaces of the third doped patterns165, respectively.

The first contacts CT1may be formed on the first doped patterns125, respectively, and may be electrically connected to the first doped patterns125, respectively. The second contacts CT2may be formed on the second doped patterns155, respectively, and may be electrically connected to the second doped patterns155, respectively. The third contacts CT3may be formed on the third doped patterns165, respectively, and may be electrically connected to the third doped patterns165, respectively.

Thereafter, the substrate100may be removed. For example, the removal of the substrate100may include grinding the substrate100to expose the second surface S2of the semiconductor body SB. Next, as illustrated inFIGS.4and5A, a lower insulating layer170may be formed on the second surface S2of the semiconductor body SB.

FIG.21is a plan view illustrating a semiconductor device according to some embodiments of the inventive concepts.FIG.22Ais a cross-sectional view taken along a line A-A′ ofFIG.21, andFIG.22Bis a cross-sectional view taken along a line B-B′ ofFIG.21.

Referring toFIGS.21,22A, and22B, a semiconductor body SB having a first surface S1and a second surface S2which are opposite to each other may be provided. The semiconductor body SB may include a semiconductor material (e.g., silicon and/or germanium). The semiconductor body SB may include first well regions310having a first conductivity type, and a second well region330having a second conductivity type different from the first conductivity type. The first well regions310may extend in the first direction D1and may be spaced apart from each other in the second direction D2. Each of the first well regions310may have a bar shape extending in the first direction D1. Each of the first well regions310may penetrate the second well region330in the third direction D3, and a side surface of each of the first well regions310may be in contact with the second well region330. The second well region330may be disposed between the first well regions310and may extend in the first direction D1between the first well regions310. The second well region330may border or at least partially surround the side surface of each of the first well regions310and may be in contact with the side surface of each of the first well regions310. Side surfaces of the first well regions310and the second well region330may be in contact with each other in a horizontal direction (e.g., in the first direction D1and the second direction D2). Top surfaces of the first well regions310and the second well region330may correspond to the first surface S1of the semiconductor body SB, and bottom surfaces of the first well regions310and the second well region330may correspond to the second surface S2of the semiconductor body SB. For some examples, the first conductivity type may be an N-type, and the second conductivity type may be a P-type. For certain examples, the first conductivity type may be a P-type, and the second conductivity type may be an N-type.

The semiconductor body SB may further include first doped regions320, which are disposed in each of the first well regions310and are spaced apart from each other in the first direction D1. Each of the first doped regions320may have a bar shape extending in the first direction D1and may penetrate each of the first well regions310in the third direction D3. Top surfaces of the first doped regions320may correspond to the first surface S1of the semiconductor body SB, and bottom surfaces of the first doped regions320may correspond to the second surface S2of the semiconductor body SB. The first doped regions320may have the first conductivity type. A concentration of dopants having the first conductivity type in the first doped regions320may be greater than a concentration of dopants having the first conductivity type in the first well regions310.

The semiconductor body SB may further include a second doped region350disposed between the first doped regions320in each of the first well regions310. The second doped region350may have a bar shape extending in the first direction D1and may penetrate each of the first well regions310in the third direction D3. A top surface of the second doped region350may correspond to the first surface S1of the semiconductor body SB, and a bottom surface of the second doped region350may correspond to the second surface S2of the semiconductor body SB. The second doped region350may have the second conductivity type. A concentration of dopants having the second conductivity type in the second doped region350may be greater than a concentration of dopants having the second conductivity type in the second well region330.

Isolation patterns400may be disposed in each of the first well regions310. The isolation patterns400may be spaced apart from each other in the first direction D1with the second doped region350interposed therebetween. The second doped region350may be disposed between the isolation patterns400, and the second doped region350and the isolation patterns400may be disposed between the first doped regions320. One of the isolation patterns400may be disposed between one of the first doped regions320and the second doped region350, and the other of the isolation patterns400may be disposed between the other of the first doped regions320and the second doped region350. Each of the isolation patterns400may have a bar shape extending in the second direction D2and may penetrate each of the first well regions310in the third direction D3. Top surfaces of the isolation patterns400may be located at the same height in the D3direction as the first surface S1of the semiconductor body SB, and bottom surfaces of the isolation patterns400may be located at the same height in the D3direction as the second surface S2of the semiconductor body SB. In the present specification, the ‘height’ may be a distance measured from the second surface S2of the semiconductor body SB in the third direction D3.

A length400L of each of the isolation patterns400in the second direction D2may be greater than a length350L1of the second doped region350in the second direction D2. A length310L1of each of the first well regions310in the second direction D2may be greater than the length400L of each of the isolation patterns400in the second direction D2. The isolation patterns400may include an insulating material, such as silicon oxide, silicon nitride, and/or silicon oxynitride.

The semiconductor body SB may further include third doped regions360, which are disposed in the second well region330and are spaced apart from each other in the first direction D1. Each of the first well regions310may be disposed between the third doped regions360. The first doped regions320, the second doped region350, and the isolation patterns400, which are disposed in each of the first well regions310, may be disposed between the third doped regions360. One of the first doped regions320may be disposed between one of the isolation patterns400and one of the third doped regions360, and the other of the first doped regions320may be disposed between the other of the isolation patterns400and the other of the third doped regions360. Each of the third doped regions360may have a bar shape extending in the first direction D1and may penetrate the second well region330in the third direction D3. Top surfaces of the third doped regions360may correspond to the first surface S1of the semiconductor body SB, and bottom surfaces of the third doped regions360may correspond to the second surface S2of the semiconductor body SB. The third doped regions360may be spaced apart from other third doped regions360adjacent thereto in the second direction D2. The third doped regions360may have the second conductivity type. A concentration of dopants having the second conductivity type in the third doped regions360may be greater than the concentration of the dopants having the second conductivity type in the second well region330. The concentration of the dopants having the second conductivity type in the second doped region350may be equal to or greater than the concentration of the dopants having the second conductivity type in the third doped regions360.

First contacts CT1, second contacts CT2and third contacts CT3may be disposed on the first surface S1of the semiconductor body SB. The first contacts CT1may be disposed on the first doped regions320and may be electrically connected to the first doped regions320. The first contacts CT1may be spaced apart from each other in the first direction D1on each of the first doped regions320. Each of the first doped regions320and the first contacts CT1connected thereto may constitute a base of a bipolar junction transistor.

The second contacts CT2may be disposed on the second doped region350and may be electrically connected to the second doped region350. The second contacts CT2may be spaced apart from each other in the first direction D1on the second doped region350. The second doped region350and the second contacts CT2connected thereto may constitute an emitter of the bipolar junction transistor. The third contacts CT3may be disposed on the third doped regions360and may be electrically connected to the third doped regions360. The third contacts CT3may be spaced apart from each other in the first direction D1on each of the third doped regions360. Each of the third doped regions360and the third contacts CT3connected thereto may constitute a collector of the bipolar junction transistor. The first contacts CT1, the second contacts CT2, and the third contacts CT3may include a conductive material (e.g., a metal).

A space ES extending in the first direction D1may be defined between a pair of the first well regions310directly adjacent to each other in the second direction D2. The space ES may be a portion of the semiconductor body SB, which extends in parallel to the pair of first well regions310between the pair of first well regions310. A length of the space ES in the first direction D1may be defined to be substantially equal to a length, in the first direction D1, of each of the pair of first well regions310, and a width ES_W of the space ES in the second direction D2may be defined as a distance between the isolation patterns400in one of the pair of first well regions310and the isolation patterns400in the other of the pair of first well regions310. The first contacts CT1and the second contacts CT2may not be disposed in the space ES.

A plurality of gate structures GS may be disposed on the first surface S1of the semiconductor body SB. The plurality of gate structures GS is omitted inFIG.21for the purpose of ease and convenience in illustration. The plurality of gate structures GS may be spaced apart from each other in the first direction D1and may extend in the second direction D2. The first contacts CT1, the second contacts CT2, and the third contacts CT3may be disposed between the plurality of gate structures GS. Each of the plurality of gate structures GS may include a gate electrode GE extending in the second direction D2, a gate dielectric pattern GI between the gate electrode GE and the first surface S1of the semiconductor body SB, gate spacers GSP on side surfaces of the gate electrode GE, and a gate capping pattern CAP on a top surface of the gate electrode GE. The gate dielectric pattern GI may extend between the gate electrode GE and the gate spacers GSP, and a topmost surface of the gate dielectric pattern GI may be substantially coplanar with the top surface of the gate electrode GE. The gate capping pattern CAP may extend onto top surfaces of the gate spacers GSP. The gate electrode GE, the gate dielectric pattern GI, the gate spacers GSP, and the gate capping pattern CAP may be substantially the same as the gate electrode GE, the gate dielectric pattern GI, the gate spacers GSP and the gate capping pattern CAP, described with reference toFIGS.1,2A, and2B. The plurality of gate structures GS may be electrically floated dummy gate structures.

An upper interlayer insulating layer380may be disposed on the first surface S1of the semiconductor body SB and may be on and at least partially cover the plurality of gate structures GS and the first to third contacts CT1, CT2, and CT3. The plurality of gate structures GS and the first to third contacts CT1, CT2, and CT3may penetrate the upper interlayer insulating layer380in the third direction D3. For example, the upper interlayer insulating layer380may include a silicon oxide layer, a silicon nitride layer, and/or a silicon oxynitride layer.

A lower insulating layer370may be disposed on the second surface S2of the semiconductor body SB. For example, the lower insulating layer370may include a silicon oxide layer, a silicon nitride layer, and/or a silicon oxynitride layer.

A first voltage may be applied to the second contacts CT2, and a second voltage may be applied to the first contacts CT1and the third contacts CT3. The second voltage may be different from the first voltage and may be, for example, a ground voltage. In this case, a first current IC may flow from the emitter consisting of the second contacts CT2and the second doped region350to the collector consisting of each of the third doped regions360and the third contacts CT3. In addition, a second current IB may flow from the emitter consisting of the second contacts CT2and the second doped region350to the base consisting of each of the first doped regions320and the first contacts CT1. Thus, the bipolar junction transistor may operate in this manner.

According to the embodiments of the inventive concepts, the side surfaces of the first and second well regions310and330and the first to third doped regions320,350, and360may be in contact with each other in a horizontal direction (e.g., in the first direction D1and the second direction D2). The top surfaces of the first and second well regions310and330and the first to third doped regions320,350, and360may constitute the first surface S1of the semiconductor body SB, and the bottom surfaces of the first and second well regions310and330and the first to third doped regions320,350, and360may constitute the second surface S2of the semiconductor body SB. In this case, even though a thickness of the semiconductor body SB in the third direction D3is relatively thin, the bipolar junction transistor operable in the semiconductor body SB may be easily realized. In addition, the isolation patterns400may be disposed between the second doped region350and the first doped regions320, respectively, in each of the first well regions310. Thus, the flow of the second current IB may be controlled, and the flow of the first current IC may be increased. As a result, operating characteristics of the bipolar junction transistor may be controlled.

FIGS.23A and23Bare cross-sectional views corresponding to the lines A-A′ and B-B′ ofFIG.21, respectively, to illustrate a semiconductor device according to some embodiments of the inventive concepts. Hereinafter, differences between the present embodiments and the above embodiments ofFIGS.21,22A, and22Bwill be mainly described for the purpose of ease and convenience in explanation.

Referring toFIGS.21,23A and23B, the semiconductor body SB may further include first doped patterns325penetrating each of the first doped regions320. The first doped patterns325may be spaced apart from each other in the first direction D1in each of the first doped regions320and may be disposed under the first contacts CT1, respectively. The first doped patterns325may be electrically connected to the first contacts CT1, respectively. Each of the first doped patterns325may penetrate each of the first doped regions320in the third direction D3. Top surfaces of the first doped patterns325may correspond to the first surface S1of the semiconductor body SB, and bottom surfaces of the first doped patterns325may correspond to the second surface S2of the semiconductor body SB. The first doped patterns325may have the first conductivity type and may be epitaxial patterns formed by an epitaxial growth process. A concentration of dopants having the first conductivity type in the first doped patterns325may be equal to or greater than the concentration of the dopants having the first conductivity type in the first doped regions320. The first doped patterns325may be used to reduce a contact resistance between the first contacts CT1and the first doped regions320.

The semiconductor body SB may further include second doped patterns355penetrating the second doped region350. The second doped patterns355may be spaced apart from each other in the first direction D1in the second doped region350and may be disposed under the second contacts CT2, respectively. The second doped patterns355may be electrically connected to the second contacts CT2, respectively. Each of the second doped patterns355may penetrate the second doped region350in the third direction D3. Top surfaces of the second doped patterns355may correspond to the first surface S1of the semiconductor body SB, and bottom surfaces of the second doped patterns355may correspond to the second surface S2of the semiconductor body SB. The second doped patterns355may have the second conductivity type and may be epitaxial patterns formed by an epitaxial growth process. A concentration of dopants having the second conductivity type in the second doped patterns355may be equal to or greater than the concentration of the dopants having the second conductivity type in the second doped regions350. The second doped patterns355may be used to reduce a contact resistance between the second contacts CT2and the second doped regions350.

The semiconductor body SB may further include third doped patterns365penetrating each of the third doped regions360. The third doped patterns365may be spaced apart from each other in the first direction D1in each of the third doped regions360and may be disposed under the third contacts CT3, respectively. The third doped patterns365may be electrically connected to the third contacts CT3, respectively. Each of the third doped patterns365may penetrate each of the third doped regions360in the third direction D3. Top surfaces of the third doped patterns365may correspond to the first surface S1of the semiconductor body SB, and bottom surfaces of the third doped patterns365may correspond to the second surface S2of the semiconductor body SB. The third doped patterns365may have the second conductivity type and may be epitaxial patterns formed by an epitaxial growth process. A concentration of dopants having the second conductivity type in the third doped patterns365may be equal to or greater than the concentration of the dopants having the second conductivity type in the third doped regions360. The third doped patterns365may be used to reduce a contact resistance between the third contacts CT3and the third doped regions360.

Except for the differences described above, other components and features of the semiconductor device according to the present embodiments may be substantially the same as corresponding components and features of the semiconductor device described with reference toFIGS.21,22A and22B.

FIGS.24A and24Bare cross-sectional views corresponding to the lines A-A′ and B-B′ ofFIG.21, respectively, to illustrate a semiconductor device according to some embodiments of the inventive concepts. Hereinafter, differences between the present embodiments and the above embodiments ofFIGS.21,23A, and23Bwill be mainly described for the purpose of ease and convenience in explanation.

Referring toFIGS.21,24A and24B, in some embodiments, each of the first doped patterns325may penetrate a portion of each of the first doped regions320in the third direction D3. Top surfaces of the first doped patterns325may correspond to the first surface S1of the semiconductor body SB, and bottom surfaces of the first doped patterns325may be located at a higher height in the third direction D3than the second surface S2of the semiconductor body SB. Here, the ‘height’ may be a distance measured from the second surface S2of the semiconductor body SB in the third direction D3. Each of the first doped regions320may extend under the first doped patterns325and may be on and at least partially cover the bottom surfaces of the first doped patterns325. Each of the first doped patterns325may have a thickness325T in the third direction D3, and the thickness325T of each of the first doped patterns325may be less than a thickness SB_T of the semiconductor body SB in the third direction D3.

Each of the second doped patterns355may penetrate a portion of the second doped region350in the third direction D3. Top surfaces of the second doped patterns355may correspond to the first surface S1of the semiconductor body SB, and bottom surfaces of the second doped patterns355may be located at a higher height in the third direction D3than the second surface S2of the semiconductor body SB. The second doped region350may extend under the second doped patterns355and may be on and at least partially cover the bottom surfaces of the second doped patterns355. Each of the second doped patterns355may have a thickness355T in the third direction D3, and the thickness355T of each of the second doped patterns355may be less than the thickness SB_T of the semiconductor body SB in the third direction D3.

Each of the third doped patterns365may penetrate a portion of each of the third doped regions360in the third direction D3. Top surfaces of the third doped patterns365may correspond to the first surface S1of the semiconductor body SB, and bottom surfaces of the third doped patterns365may be located at a higher height in the third direction D3than the second surface S2of the semiconductor body SB. Each of the third doped regions360may extend under the third doped patterns365and may be on and at least partially cover the bottom surfaces of the third doped patterns365. Each of the third doped patterns365may have a thickness365T in the third direction D3, and the thickness365T of each of the third doped patterns365may be less than the thickness SB_T of the semiconductor body SB in the third direction D3.

Except for the differences described above, other components and features of the semiconductor device according to the present embodiments may be substantially the same as corresponding components and features of the semiconductor device described with reference toFIGS.21,23A and23B.

FIG.25is a cross-sectional view corresponding to the line A-A′ ofFIG.21to illustrate a semiconductor device according to some embodiments of the inventive concepts. Hereinafter, differences between the present embodiments and the above embodiments ofFIGS.21,22A and22Bwill be mainly described for the purpose of ease and convenience in explanation.

Referring toFIGS.21,25and22B, in some embodiments, the plurality of gate structures GS may be omitted. In this case, the first to third contacts CT1, CT2, and CT3may be disposed on the first surface S1of the semiconductor body SB so as to be electrically connected to the first to third doped regions320,350and360, and the upper interlayer insulating layer380may at least partially fill a space between the first to third contacts CT1, CT2, and CT3and may be in direct contact with the top surfaces of the first to third doped regions320,350, and360. Except for the differences described above, other components and features of the semiconductor device according to the present embodiments may be substantially the same as corresponding components and features of the semiconductor device described with reference toFIGS.21,22A, and22B.

FIG.26is a cross-sectional view corresponding to the line A-A′ ofFIG.21to illustrate a semiconductor device according to some embodiments of the inventive concepts. Hereinafter, differences between the present embodiments and the above embodiments ofFIGS.21,22A, and22Bwill be mainly described for the purpose of ease and convenience in explanation.

Referring toFIGS.21,26, and22B, in some embodiments, some of the plurality of gate structures GS may be omitted. For example, the plurality of gate structures GS may extend in the second direction D2to intersect the first doped regions320and the third doped regions360, and the first contacts CT1and the third contacts CT3may be disposed between the plurality of gate structures GS. The plurality of gate structures GS may not be disposed on the second doped region350. The second contacts CT2may be disposed on the second doped region350so as to be electrically connected to the second doped region350. The upper interlayer insulating layer380may at least partially fill a space between the second contacts CT2and may be in direct contact with the top surface of the second doped region350.

According to some embodiments, the semiconductor body SB may further include first doped patterns325penetrating each of the first doped regions320, and third doped patterns365penetrating each of the third doped regions360. The first doped patterns325and the third doped patterns365may be substantially the same as the first doped patterns325and the third doped patterns365, described with reference toFIGS.21,23A, and23B. In the case in which the plurality of gate structures GS is not disposed on the second doped region350, the second doped patterns355described with reference toFIGS.21,23A and23Bmay not be provided.

Except for the differences described above, other components and features of the semiconductor device according to the present embodiments may be substantially the same as corresponding components and features of the semiconductor device described with reference toFIGS.21,22A, and22B.

FIG.27is a plan view illustrating a semiconductor device according to some embodiments of the inventive concepts. Cross-sectional views taken along lines A-A′ and B-B′ ofFIG.27are substantially the same as those ofFIGS.22A and22B, respectively. Hereinafter, differences between the present embodiments and the above embodiments ofFIGS.21,22A, and22Bwill be mainly described for the purpose of ease and convenience in explanation.

Referring toFIG.27, in some embodiments, each of the third doped regions360may continuously extend in the second direction D2at a side of the first well regions310spaced apart from each other in the second direction D2. Each of the third doped regions360may have a line shape extending in the second direction D2and may continuously extend along side surfaces of the first well regions310spaced apart from each other in the second direction D2. The first well regions310spaced apart from each other in the second direction D2may be disposed between the third doped regions360. According to the present embodiments, the second doped regions350respectively disposed in the first well regions310and the second contacts CT2connected to the second doped regions350may constitute a plurality of emitters, and the first doped regions320respectively disposed in the first well regions310and the first contacts CT1connected to the first doped regions320may constitute a plurality of bases. Each of the third doped regions360and the third contacts CT3connected to each of the third doped regions360may constitute a collector, and the plurality of emitters and the plurality of bases may share the collector.

FIG.28is a plan view illustrating a semiconductor device according to some embodiments of the inventive concepts, andFIG.29is a cross-sectional view taken along a line B-B′ ofFIG.28. A cross-sectional view taken along a line A-A′ ofFIG.28is substantially the same as that ofFIG.22A. Hereinafter, differences between the present embodiments and the above embodiments ofFIGS.21,22A, and22Bwill be mainly described for the purpose of ease and convenience in explanation.

Referring toFIGS.28and29, in some embodiments, the semiconductor body SB may further include extension well regions310E between the first well regions310. The extension well regions310E may be disposed between the first well regions310spaced apart from each other in the second direction D2, and the first well regions310may be electrically connected to each other through the extension well regions310E. A length310EL of each of the extension well regions310E in the first direction D1may be less than a length310L2of each of the first well regions310in the first direction D1. The extension well regions310E may penetrate the second well region330in the third direction D3. Top surfaces of the first well regions310, the extension well regions310E, and the second well region330may correspond to the first surface S1of the semiconductor body SB, and bottom surfaces of the first well regions310, the extension well regions310E and the second well region330may correspond to the second surface S2of the semiconductor body SB. The extension well regions310E may have the first conductivity type, and a concentration of dopants having the first conductivity type in the extension well regions310E may be equal to the concentration of the dopants having the first conductivity type in the first well regions310.

According to some embodiments, the second doped region350may extend in the second direction D2to intersect the first well regions310and the extension well regions310E. The second doped region350may have a line shape extending in the second direction D2and may penetrate the first well regions310and the extension well regions310E in the third direction D3. A top surface of the second doped region350may correspond to the first surface S1of the semiconductor body SB, and a bottom surface of the second doped region350may correspond to the second surface S2of the semiconductor body SB. A length350L2of the second doped region350in the first direction D1may be less than the length310EL of each of the extension well regions310E in the first direction D1.

In some embodiments, each of the third doped regions360may continuously extend in the second direction D2at a side of the first well regions310and the extension well regions310E. Each of the third doped regions360may have a line shape extending in the second direction D2and may continuously extend along side surfaces of the first well regions310and the extension well regions310E. The first well regions310and the extension well regions310E may be disposed between the third doped regions360. According to the present embodiments, the second doped region350and the second contacts CT2connected to the second doped region350may constitute an emitter. The first doped regions320respectively disposed in the first well regions310and the first contacts CT1connected to the first doped regions320may constitute a plurality of bases. Each of the third doped regions360and the third contacts CT3connected to each of the third doped regions360may constitute a collector. The plurality of bases may share the emitter and the collector.

FIG.30is a cross-sectional view corresponding to the line A-A′ ofFIG.21to illustrate a semiconductor device according to some embodiments of the inventive concepts. Hereinafter, differences between the present embodiments and the above embodiments ofFIGS.21,22A, and22Bwill be mainly described for the purpose of ease and convenience in explanation.

Referring toFIGS.21and30, the semiconductor body SB may further include first doped patterns325penetrating each of the first doped regions320, second doped patterns355penetrating the second doped region350, and third doped patterns365penetrating each of the third doped regions360. The first to third doped patterns325,355, and365may be substantially the same as the first to third doped patterns325,355and365described with reference toFIGS.21,23A and23B. In some embodiments, each of the isolation patterns400may extend into the upper interlayer insulating layer380in the third direction D3and may penetrate the upper interlayer insulating layer380in the third direction D3. Top surfaces400U of the isolation patterns400may be located at a higher height in the third direction D3than the first surface S1of the semiconductor body SB and may be located at substantially the same height in the third direction D3as a top surface of the upper interlayer insulating layer380and top surfaces of the gate structures GS (i.e., top surfaces of the gate capping patterns CAP). Bottom surfaces of the isolation patterns400may be located at the same height in the third direction D3as the second surface S2of the semiconductor body SB. Except for the differences described above, other components and features of the semiconductor device according to the present embodiments may be substantially the same as corresponding components and features of the semiconductor device described with reference toFIGS.21,22A, and22B.

FIGS.31to35are cross-sectional views corresponding to the line A-A′ ofFIG.21to illustrate a method of manufacturing a semiconductor device according to some embodiments of the inventive concepts. Hereinafter, the descriptions of the same features as mentioned with reference toFIGS.21,22A and22Bwill be omitted for the purpose of ease and convenience in explanation.

Referring toFIG.31, first semiconductor layers302and second semiconductor layers304may be alternately stacked on a substrate300. The substrate300may be a semiconductor substrate. The first semiconductor layers302may include, for example, silicon, and the second semiconductor layers304may include, for example, silicon-germanium.

Referring toFIGS.21and32, first well regions310and a second well region330may be formed in the first semiconductor layers302and the second semiconductor layers304. For example, the formation of the first well regions310may include injecting or implanting dopants having a first conductivity type into the first semiconductor layers302and the second semiconductor layers304. The first well regions310may extend in the first direction D1and may be spaced apart from each other in the second direction D2. Each of the first well regions310may have a bar shape extending in the first direction D1. For example, the formation of the second well region330may include injecting or implanting dopants having a second conductivity type into the first semiconductor layers302and the second semiconductor layers304. The second well region330may be formed to border or at least partially surround a side surface of each of the first well regions310. Side surfaces of the first well regions310and the second well region330may be in contact with each other in a horizontal direction (e.g., in the first direction D1and the second direction D2). The first well regions310and the second well region330may constitute a semiconductor body SB.

Referring toFIGS.21and33, first doped regions320may be formed in each of the first well regions310. The first doped regions320may be formed to be spaced apart from each other in the first direction D1in each of the first well regions310. Each of the first doped regions320may penetrate each of the first well regions310in the third direction D3. For example, the formation of the first doped regions320may include injecting or implanting dopants having the first conductivity type into each of the first well regions310. A concentration of dopants having the first conductivity type in the first doped regions320may be greater than a concentration of dopants having the first conductivity type in the first well regions310.

A second doped region350may be formed between the first doped regions320in each of the first well regions310. The second doped region350may have a bar shape extending in the first direction D1and may penetrate each of the first well regions310in the third direction D3. For example, the formation of the second doped region350may include injecting or implanting dopants having the second conductivity type into each of the first well regions310. A concentration of dopants having the second conductivity type in the second doped region350may be greater than a concentration of dopants having the second conductivity type in the second well region330.

Third doped regions360may be formed in the second well region330. The third doped regions360may be spaced apart from each other in the first direction D1with each of the first well regions310interposed therebetween. Each of the third doped regions360may have a bar shape extending in the first direction D1and may penetrate the second well region330in the third direction D3. For example, the formation of the third doped regions360may include injecting or implanting dopants having the second conductivity type into the second well region330. A concentration of dopants having the second conductivity type in the third doped regions360may be greater than the concentration of the dopants having the second conductivity type in the second well region330. The concentration of the dopants having the second conductivity type in the second doped region350may be equal to or greater than the concentration of the dopants having the second conductivity type in the third doped regions360.

Side surfaces of the first and second well regions310and330and the first to third doped regions320,350, and360may be in contact with each other in a horizontal direction (e.g., in the first direction D1and the second direction D2). The first and second well regions310and330and the first to third doped regions320,350, and360may constitute the semiconductor body SB. The semiconductor body SB may have a first surface S1and a second surface S2, which are opposite to each other, and the second surface S2of the semiconductor body SB may be adjacent to the substrate300.

Referring toFIGS.21and34, a plurality of gate structures GS may be formed on the first surface S1of the semiconductor body SB. The plurality of gate structures GS may be spaced apart from each other in the first direction D1and may extend in the second direction D2. Each of the plurality of gate structures GS may include a gate electrode GE extending in the second direction D2, a gate dielectric pattern GI between the gate electrode GE and the first surface S1of the semiconductor body SB, gate spacers GSP on side surfaces of the gate electrode GE, and a gate capping pattern CAP on a top surface of the gate electrode GE. The gate dielectric pattern GI may extend between the gate electrode GE and the gate spacers GSP, and a topmost surface of the gate dielectric pattern GI may be substantially coplanar with the top surface of the gate electrode GE. The gate capping pattern CAP may extend onto top surfaces of the gate spacers GSP. An upper interlayer insulating layer380may be formed on the first surface S1of the semiconductor body SB and may be on and at least partially cover the plurality of gate structures GS.

Holes400H may be formed in the upper interlayer insulating layer380and may extend into each of the first well regions310. Each of the holes400H may penetrate the upper interlayer insulating layer380and each of the first well regions310. In each of the first well regions310, the holes400H may be spaced apart from each other in the first direction D1with the second doped region350interposed therebetween. One of the holes400H may be formed between one of the first doped regions320and the second doped region350, and the other of the holes400H may be formed between the other of the first doped regions320and the second doped region350. Each of the holes400H may have a bar shape extending in the second direction D2and may penetrate the upper interlayer insulating layer380and each of the first well regions310in the third direction D3. In some embodiments, the formation of the holes400H may include removing the upper interlayer insulating layer380between the plurality of gate structures GS to expose portions of each of the first well regions310, and etching the exposed portions of each of the first well regions310.

Referring toFIGS.21and35, isolation patterns400may be formed in the holes400H, respectively. Each of the isolation patterns400may at least partially fill a lower portion of each of the holes400H and may penetrate each of the first well regions310in the third direction D3. For example, the formation of the isolation patterns400may include forming an isolation insulating layer at least partially filling the holes400H on the upper interlayer insulating layer380, and recessing the isolation insulating layer until the isolation insulating layer having a desired thickness remains in each of the holes400H. Since the isolation insulating layer is recessed, the isolation insulating layer may be removed from an upper portion of each of the holes400H, and each of the isolation patterns400may be locally formed in the lower portion of each of the holes400H. Thereafter, an additional insulating layer may be formed to at least partially fill the upper portion of each of the holes400H. The additional insulating layer may be referred to as the upper interlayer insulating layer380.

Referring again toFIGS.21and22A, first contacts CT1, second contacts CT2, and third contacts CT3may be formed in the upper interlayer insulating layer380and between the plurality of gate structures GS. For example, the formation of the first to third contacts CT1, CT2, and CT3may include forming first contact holes, second contact holes and third contact holes in the upper interlayer insulating layer380between the plurality of gate structures GS, and forming the first contacts CT1, the second contacts CT2and the third contacts CT3in the first contact holes, the second contact holes, and the third contact holes, respectively.

Thereafter, the substrate300may be removed. For example, the removal of the substrate300may include grinding the substrate300to expose the second surface S2of the semiconductor body SB. After the removal of the substrate300, a lower insulating layer370may be formed on the second surface S2of the semiconductor body SB.

FIG.36is a cross-sectional view corresponding to the line A-A′ ofFIG.21to illustrate a method of manufacturing a semiconductor device according to some embodiments of the inventive concepts. Hereinafter, differences between the present embodiments and the embodiments mentioned with reference toFIGS.21,22A, and31to35will be mainly described for the purpose of ease and convenience in explanation.

First, as described with reference toFIGS.21and31to33, the first semiconductor layers302and the second semiconductor layers304may be alternately stacked on the substrate300, and the first well regions310and the second well region330may be formed in the first semiconductor layers302and the second semiconductor layers304. The first doped regions320and the second doped region350may be formed in each of the first well regions310, and the third doped regions360may be formed in the second well region330. The first and second well regions310and330and the first to third doped regions320,350and360may constitute the semiconductor body SB.

Referring toFIGS.21and36, sacrificial gate structures SGS may be formed on the first surface S1of the semiconductor body SB. The sacrificial gate structures SGS may be spaced apart from each other in the first direction D1and may extend in the second direction D2. Each of the sacrificial gate structures SGS may include a sacrificial gate pattern SGP and a gate mask pattern MP sequentially stacked on the first surface S1of the semiconductor body SB, and gate spacers GSP on both side surfaces of the sacrificial gate pattern SGP. The gate spacers GSP may extend onto both side surfaces of the gate mask pattern MP. For example, the formation of the sacrificial gate pattern SGP may include forming a sacrificial gate layer (not shown) on the first surface S1of the semiconductor body SB, forming the gate mask pattern MP defining a region, in which the sacrificial gate pattern SGP will be formed, on the sacrificial gate layer, and patterning the sacrificial gate layer using the gate mask pattern MP as an etch mask. The formation of the gate spacers GSP may include forming a gate spacer layer (not shown) on and at least partially covering the gate mask pattern MP and the sacrificial gate pattern SGP on the first surface S1of the semiconductor body SB, and anisotropically etching the gate spacer layer. The sacrificial gate pattern SGP may include, for example, poly-silicon, and the gate mask pattern MP and the gate spacers GSP may include, for example, silicon nitride.

First doped patterns325may be formed in each of the first doped regions320. The first doped patterns325may be spaced apart from each other in the first direction D1in each of the first doped regions320, and each of the first doped patterns325may penetrate each of the first doped regions320in the third direction D3. For example, the formation of the first doped patterns325may include forming first holes penetrating each of the first doped regions320between the sacrificial gate structures SGS, and performing an epitaxial growth process to form the first doped patterns325in the first holes, respectively. The formation of the first doped patterns325may further include injecting dopants having the first conductivity type into the first doped patterns325during the epitaxial growth process or after the epitaxial growth process. A concentration of the dopants having the first conductivity type in the first doped patterns325may be equal to or greater than the concentration of the dopants having the first conductivity type in the first doped regions320.

Second doped patterns355may be formed in the second doped region350. The second doped patterns355may be spaced apart from each other in the first direction D1in the second doped region350, and each of the second doped patterns355may penetrate the second doped region350in the third direction D3. For example, the formation of the second doped patterns355may include forming second holes penetrating the second doped region350between the sacrificial gate structures SGS, and performing an epitaxial growth process to form the second doped patterns355in the second holes, respectively. The formation of the second doped patterns355may further include injecting dopants having the second conductivity type into the second doped patterns355during the epitaxial growth process or after the epitaxial growth process. A concentration of the dopants having the second conductivity type in the second doped patterns355may be equal to or greater than the concentration of the dopants having the second conductivity type in the second doped regions350.

Third doped patterns365may be formed in each of the third doped regions360. The third doped patterns365may be spaced apart from each other in the first direction D1in each of the third doped regions360, and each of the third doped patterns365may penetrate each of the third doped regions360in the third direction D3. For example, the formation of the third doped patterns365may include forming third holes penetrating each of the third doped regions360between the sacrificial gate structures SGS, and performing an epitaxial growth process to form the third doped patterns365in the third holes, respectively. The formation of the third doped patterns365may further include injecting dopants having the second conductivity type into the third doped patterns365during the epitaxial growth process or after the epitaxial growth process. A concentration of the dopants having the second conductivity type in the third doped patterns365may be equal to or greater than the concentration of the dopants having the second conductivity type in the third doped regions360.

The upper interlayer insulating layer380described with reference toFIG.34may be formed on the first surface S1of the semiconductor body SB and may be on and at least partially cover the sacrificial gate structures SGS. Thereafter, the sacrificial gate pattern SGP and the gate mask pattern MP of each of the sacrificial gate structures SGS may be removed. Thus, gap regions may be formed in the upper interlayer insulating layer380and between the gate spacers GSP.

Referring again toFIGS.21and34, a gate dielectric pattern GI and a gate electrode GE may be formed to at least partially fill each of the gap regions. Upper portions of the gate dielectric pattern GI, the gate electrode GE and the gate spacers GSP may be recessed to form a groove region in each of the gap regions, and a gate capping pattern CAP may be formed in the groove region. The gate dielectric pattern GI, the gate electrode GE, the gate spacers GSP and the gate capping pattern CAP may be referred to as a gate structure GS.

Except for the differences described above, other processes and features of the manufacturing method according to the present embodiments may be substantially the same as corresponding processes and features of the manufacturing method described with reference toFIGS.21,22A, and31to35.

FIGS.37to39are cross-sectional views corresponding to the line A-A′ ofFIG.21to illustrate a method of manufacturing a semiconductor device according to some embodiments of the inventive concepts. Hereinafter, differences between the present embodiments and the embodiments mentioned with reference toFIGS.21,22A, and31to35will be mainly described for the purpose of ease and convenience in explanation.

First, as described with reference toFIGS.21and31to33, the first semiconductor layers302and the second semiconductor layers304may be alternately stacked on the substrate300, and the first well regions310and the second well region330may be formed in the first semiconductor layers302and the second semiconductor layers304. The first doped regions320and the second doped region350may be formed in each of the first well regions310, and the third doped regions360may be formed in the second well region330. The first and second well regions310and330and the first to third doped regions320,350, and360may constitute the semiconductor body SB. Thereafter, as described with reference toFIGS.21and36, the sacrificial gate structures SGS may be formed on the first surface S1of the semiconductor body SB, and the first doped patterns325, the second doped patterns355, and the third doped patterns365may be formed in the first doped regions320, the second doped regions350, and the third doped regions360, respectively, between the sacrificial gate structures SGS.

Referring toFIGS.21and37, an upper interlayer insulating layer380may be formed on the first surface S1of the semiconductor body SB and may be on and at least partially cover the sacrificial gate structures SGS. Thereafter, the sacrificial gate pattern SGP and the gate mask pattern MP of each of the sacrificial gate structures SGS may be removed. Thus, gap regions may be formed in the upper interlayer insulating layer380and between the gate spacers GSP. A gate dielectric pattern GI and a gate electrode GE may be formed to at least partially fill each of the gap regions. Upper portions of the gate dielectric pattern GI, the gate electrode GE, and the gate spacers GSP may be recessed to form a groove region in each of the gap regions, and a gate capping pattern CAP may be formed in the groove region. The gate dielectric pattern GI, the gate electrode GE, the gate spacers GSP, and the gate capping pattern CAP may be referred to as a gate structure GS.

Referring toFIGS.21and38, holes400H may be formed in the upper interlayer insulating layer380and may extend into each of the first well regions310. Each of the holes400H may penetrate the upper interlayer insulating layer380and each of the first well regions310. In each of the first well regions310, the holes400H may be spaced apart from each other in the first direction D1with the second doped region350interposed therebetween. One of the holes400H may be formed between one of the first doped regions320and the second doped region350, and the other of the holes400H may be formed between the other of the first doped regions320and the second doped region350. Each of the holes400H may have a bar shape extending in the second direction D2and may penetrate the upper interlayer insulating layer380and each of the first well regions310in the third direction D3. In some embodiments, the formation of the holes400H may include removing portions of corresponding ones of the plurality of gate structures GS to expose portions of each of the first well regions310, and etching the exposed portions of each of the first well regions310.

Referring toFIGS.21and39, isolation patterns400may be formed in the holes400H, respectively. Each of the isolation patterns400may penetrate each of the first well regions310in the third direction D3. Each of the isolation patterns400may extend into the upper interlayer insulating layer380in the third direction D3and may penetrate the upper interlayer insulating layer380in the third direction D3. For example, the formation of the isolation patterns400may include forming an isolation insulating layer at least partially filling the holes400H on the upper interlayer insulating layer380, and planarizing the isolation insulating layer to expose a top surface of the upper interlayer insulating layer380. By the planarization process, the isolation patterns400may be locally formed in the holes400H.

Referring again toFIGS.21and30, first contacts CT1, second contacts CT2, and third contacts CT3may be formed in the upper interlayer insulating layer380and between the plurality of gate structures GS. The first contacts CT1, the second contacts CT2and the third contacts CT3may be electrically connected to the first doped patterns325, the second doped patterns355and the third doped patterns365, respectively. Thereafter, the substrate300may be removed, and a lower insulating layer370may be formed on the second surface S2of the semiconductor body SB.

FIG.40is a plan view illustrating a semiconductor device according to some embodiments of the inventive concepts, andFIG.41is a cross-sectional view taken along a line A-A′ ofFIG.40. A cross-sectional view taken along a line B-B′ ofFIG.40is substantially the same as that ofFIG.22B. Hereinafter, differences between the present embodiments and the above embodiments ofFIGS.21,22A, and22Bwill be mainly described for the purpose of ease and convenience in explanation.

Referring toFIGS.40and41, additional isolation patterns410may be disposed between the first doped regions320and the third doped regions360. One of the additional isolation patterns410may be disposed between one of the first doped regions320and one of the third doped regions360, and the other of the additional isolation patterns410may be disposed between the other of the first doped regions320and the other of the third doped regions360. Each of the additional isolation patterns410may have a bar shape extending in the second direction D2. Each of the additional isolation patterns410may penetrate the semiconductor body SB in the third direction D3. For example, each of the additional isolation patterns410may penetrate the second well region330in the third direction D3. Top surfaces of the additional isolation patterns410may be located at the same height in the D3direction as the first surface S1of the semiconductor body SB, and bottom surfaces of the additional isolation patterns410may be located at the same height in the D3direction as the second surface S2of the semiconductor body SB. Except for the positions of the additional isolation patterns410, other features of the additional isolation patterns410may be substantially the same as corresponding features of the isolation patterns400described with reference toFIGS.21,22A, and22B.

FIG.42is a cross-sectional view illustrating a semiconductor device according to some embodiments of the inventive concepts. Hereinafter, differences between the present embodiments and the above embodiments ofFIGS.1,2A, and2Bwill be mainly described for the purpose of ease and convenience in explanation.

Referring toFIG.42, the semiconductor body SB may include a device region CR and a peripheral region PR. In some embodiments, the peripheral region PR of the semiconductor body SB may include the first to third well regions110,130, and140, the plurality of first doped regions120, the second doped region150and the third doped region160, described with reference toFIGS.1,2A, and2B. The plurality of gate structures GS and the first to third contacts CT1, CT2, and CT3, described with reference toFIGS.1,2A and2B, may be disposed on the first surface S1of the peripheral region PR of the semiconductor body SB. In certain embodiments, unlikeFIG.42, the peripheral region PR of the semiconductor body SB may include substantially the same components as at least one of the semiconductor devices described with reference toFIGS.3A to10C,21to30,40and41.

The device region CR of the semiconductor body SB may include semiconductor patterns102vertically spaced apart from each other (e.g., in a direction perpendicular to the first surface S1of the semiconductor body SB), source/drain patterns210disposed at both sides of the semiconductor patterns102, and a device isolation pattern220disposed between the source/drain patterns210. The semiconductor patterns102may include silicon, and the source/drain patterns210may include silicon, silicon-germanium, and/or silicon carbide. The device isolation pattern220may include an oxide, a nitride, and/or an oxynitride.

Cell gate structures CGS may be disposed on the first surface S1of the device region CR of the semiconductor body SB and may intersect the semiconductor patterns102. Each of the cell gate structures CGS may include a cell gate electrode CGE intersecting the semiconductor patterns102, a cell gate dielectric pattern CGI between the cell gate electrode CGE and the first surface S1of the device region CR of the semiconductor body SB, cell gate spacers CGSP on side surfaces of the cell gate electrode CGE, and a cell gate capping pattern CCAP on a top surface of the cell gate electrode CGE. The cell gate electrode CGE, the cell gate dielectric pattern CGI, the cell gate spacers CGSP and the cell gate capping pattern CCAP may be substantially the same as the gate electrode GE, the gate dielectric pattern GI, the gate spacers GSP and the gate capping pattern CAP described with reference toFIGS.1,2A, and2B, respectively. The cell gate electrode CGE may extend between the semiconductor patterns102, and the cell gate dielectric pattern CGI may extend between each of the semiconductor patterns102and the cell gate electrode CGE. The cell gate dielectric pattern CGI may further extend between the cell gate electrode CGE and the cell gate spacers CGSP.

Sidewall spacers215may be disposed between the semiconductor patterns102, and the cell gate electrode CGE and the cell gate dielectric pattern CGI may be disposed between the sidewall spacers215. The cell gate dielectric pattern CGI may further extend between each of the sidewall spacers215and the cell gate electrode CGE. The cell gate electrode CGE and the cell gate dielectric pattern CGI may be spaced apart from the source/drain patterns210with the sidewall spacers215interposed therebetween.

Source/drain contacts240may be disposed on the first surface S1of the device region CR of the semiconductor body SB and between the cell gate structures CGS. The source/drain contacts240may be electrically connected to the source/drain patterns210, respectively.

An upper interlayer insulating layer180may be disposed on the first surface S1of the semiconductor body SB and may be on and at least partially cover the device region CR and the peripheral region PR. The upper interlayer insulating layer180may be substantially the same as the upper interlayer insulating layer180described with reference toFIGS.1,2A, and2B or the upper interlayer insulating layer380described with reference toFIGS.21,22A, and22B. The upper interlayer insulating layer180may be on and at least partially cover the cell gate structures CGS and the source/drain contacts240on the device region CR of the semiconductor body SB and may be on and at least partially cover the gate structures GS and the first to third contacts CT1, CT2, and CT3on the peripheral region PR of the semiconductor body SB.

Upper interconnection lines200may be disposed on the upper interlayer insulating layer180. The source/drain contacts240and the first to third contacts CT1, CT2, and CT3may be electrically connected to the upper interconnection lines200. The upper interconnection lines200may include a conductive material (e.g., a metal).

A lower insulating layer170may be disposed on the second surface S2of the semiconductor body SB and may be on and at least partially cover the device region CR and the peripheral region PR. The lower insulating layer170may be substantially the same as the lower insulating layer170described with reference toFIGS.1,2A, and2Bor the lower insulating layer370described with reference toFIGS.21,22A, and22B.

Lower interconnection lines174and lower vias176may be disposed on the lower insulating layer170. The lower insulating layer170may be disposed between the second surface S2of the semiconductor body SB and the lower vias176, and the lower vias176may be disposed between the lower insulating layer170and the lower interconnection lines174. The lower vias176may be electrically connected to the lower interconnection lines174. The lower interconnection lines174and the lower vias176may include a conductive material (e.g., a metal). In some embodiments, the lower interconnection lines174and the lower vias176may constitute a power delivery network.

A lower interlayer insulating layer172may be disposed on the lower insulating layer170and may be on and at least partially cover the lower interconnection lines174and the lower vias176. The lower insulating layer170may be disposed between the second surface S2of the semiconductor body SB and the lower interlayer insulating layer172, and the lower interconnection lines174and the lower vias176may be disposed in the lower interlayer insulating layer172. For example, the lower interlayer insulating layer172may include a silicon oxide layer, a silicon nitride layer, and/or a silicon oxynitride layer.

A through-electrode230may penetrate the upper interlayer insulating layer180, the semiconductor body SB, and the lower insulating layer170. The through-electrode230may penetrate the device isolation pattern220of the semiconductor body SB. The through-electrode230may be electrically connected to a corresponding upper interconnection line200of the upper interconnection lines200and may be electrically connected to a corresponding lower via176of the lower vias176. The through-electrode230may be electrically connected to a corresponding lower interconnection line174of the lower interconnection lines174through the corresponding lower via176. The through-electrode230may include a conductive material (e.g., a metal).

In some embodiments, to form the through-electrode230penetrating the semiconductor body SB, it may be desired that a vertical thickness (e.g., a thickness in a direction perpendicular to the first surface S1of the semiconductor body SB) of the semiconductor body SB is relatively thin. According to embodiments of the inventive concepts, in the peripheral region PR of the semiconductor body SB, the side surfaces of the first to third well regions110,130and140and the first to third doped regions120,150and160may be in contact with each other in a horizontal direction (e.g., in the first direction D1and the second direction D2). The top surfaces of the first to third well regions110,130, and140and the first to third doped regions120,150, and160may constitute the first surface S1of the semiconductor body SB, and the bottom surfaces of the first to third well regions110,130, and140and the first to third doped regions120,150, and160may constitute the second surface S2of the semiconductor body SB. In this case, even though the vertical thickness of the semiconductor body SB is relatively thin, an operable bipolar junction transistor may be realized in the semiconductor body SB. Thus, the operable bipolar junction transistor compatible with the through-electrode230may be realized.

According to embodiments of the inventive concepts, even though the thickness of the semiconductor body is relatively thin, the operable bipolar junction transistor may be realized in the semiconductor body. In addition, it may be possible to control the flow of the current flowing through the bipolar junction transistor (e.g., the first current flowing from the emitter to the collector and the second current flowing from the emitter to the base), and thus the operating characteristics of the bipolar junction transistor may be controlled.

As a result, it is possible to provide the semiconductor device including the bipolar junction transistor capable of being realized in a relatively thin semiconductor body and in which the operating characteristics may be relatively easily controlled.