Method for forming a FinFET structure

A method for forming a FinFET structure includes providing a substrate, a first region and a second region being defined on the substrate, a first fin structure and a second fin structure being disposed on the substrate within the first region and the second region respectively. A first oxide layer cover the first fin structure and the second fin structure. Next a first protective layer and a second protective layer are entirely formed on the substrate and the first oxide layer in sequence, the second protective layer within the first region is removed, and the first protective layer within the first region is then removed. Afterwards, the first oxide layer covering the first fin structure and the second protective layer within the second region are removed simultaneously, and a second oxide layer is formed to cover the first fin structure.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates generally to fin-type field effect transistors (FinFET) and more particularly to the method for forming an improved FinFET structure that includes multiple gate dielectric thicknesses.

2. Description of the Prior Art

Semiconductor structure includes both passive semiconductor devices such as resistors, as well as active devices such as transistors and diodes. Field effect transistor devices are common transistor devices within semiconductor structures.

Field effect transistor structure and device dimensions have been scaled effectively to increasingly smaller dimensions over the period of several decades. Various field effect transistor structures having desirable properties are known in the semiconductor fabrication art. One recent advance in transistor technology is the introduction of fin type field effect transistors that are known as FinFET.

In the conventional process, the method for forming individual FinFETs on one substrate comprises: first, a substrate having at least two fin structure is provided, and a first oxide layer is then formed on these two fin structures, next, parts of the first oxide layer, especially the portion that covers on one of the fin structure is then removed, afterwards, a second oxide layer is then formed on the exposed fin structure. However, since there is no other layer that is formed during the process, the fin structure or the isolating region surrounding each fin structure is easily damaged by the etching processes, influencing the yield and the performance of the FinFET.

SUMMARY OF THE INVENTION

The present invention provides a method for forming a FinFET structure, at least comprising the following steps: first, a substrate is provided, a first region and a second region are defined on the substrate, a first fin structure and a second fin structure are disposed on the substrate, within the first region and the second region respectively, a first oxide layer covering the first fin structure and the second fin structure, next a first protective layer and a second protective layer are entirely formed on the substrate and the first oxide layer in sequence, the second protective layer within the first region is removed, the first protective layer within the first region is then removed, afterwards, the first oxide layer covering the first fin structure and the second protective layer within the second region are removed simultaneously, and a second oxide layer is formed to cover the first fin structure.

The features of the present invention further comprise a first protective layer and a second protective layer, which are made of different materials, for example, in the embodiment mentioned above. The first protective layer comprises silicon nitride, and the second protective layer comprises silicon oxide, and these two dielectric layers protect the oxide region disposed in the substrate and surrounding the fin structure from the damages occurring during the etching processes. Besides, since the silicon nitride first protective layer has high selectivity with the first oxide layer disposed on the fin structure and the oxide region, so during the process for removing the silicon nitride first protective layer, the first oxide layer and the oxide region will not be ruined by the etching processes, thereby enhancing the yield and the performance of the FinFET.

DETAILED DESCRIPTION

To provide a better understanding of the present invention to users skilled in the technology of the present invention, preferred embodiments are detailed as follows. The preferred embodiments of the present invention are illustrated in the accompanying drawings with numbered elements to clarify the contents and effects to be achieved.

Please note that the figures are only for illustration and the figures may not be to scale. The scale may be further modified according to different design considerations. When referring to the words “up” or “down” that describe the relationship between components in the text, it is well known in the art and should be clearly understood that these words refer to relative positions that can be inverted to obtain a similar structure, and these structures should therefore not be precluded from the scope of the claims in the present invention.

FIG. 1-9are schematic diagrams showing the manufacturing process for forming a FinFET structure according to one preferred embodiment of the present invention. As shown inFIG. 1, first, a substrate10is provided, such as a silicon substrate. There are at least two fin structures12on the substrate10, and an oxide region14, disposed on the substrate10and surrounding the fin structure12. Usually, the oxide region such as the shallow trench isolation (STI), is used to isolate different components on the substrate10. A first oxide layer16is disposed on the fin structures12, but does not cover the oxide region14. In other words, the oxide region14is exposed. In addition, there are two regions: a first region A and a second region B which are defined on the substrate, the region A and region B comprising at least one fin structure12therein. It is worth noting that in the following process, devices with different oxide layer thicknesses will be formed in the region A and in the region B respectively, such as the low voltage (LV) devices, the memory, the core devices, electrostatic-sensitive device (ESD), IO devices or high voltage (HV) devices, and these devices have different oxide layer thicknesses.

Please refer toFIGS. 2-3, a first protective layer18and a second protective layer20are then formed in sequence, covering the first oxide layer16and the oxide region14. In this embodiment, the first protective layer18comprises silicon nitride, and the second protective layer20comprises silicon oxide. The first protective layer18and the second protective layer20are preferably formed through an atomic layer deposition (ALD) process, but not limited thereto.

Next, please refer toFIGS. 4-5. As shown inFIG. 4, a patterned photoresist layer22is formed on the second protective layer20within the second region B. As shown inFIG. 5, an etching process (not shown) is then performed, to remove parts of the second protective layer20which are not covered by the photoresist layer22. In other words, only the second protective layer20within the first region A is removed. Afterwards, the patterned photoresist layer22is then removed. In this embodiment, the etching process for removing the second protective layer20comprises a dilute hydrofluoric acid (DHF) containing cleaning process, a sulfuric acid-hydrogen peroxide mixture (SPM) containing cleaning process or a standard clean 1 (SC1) process, but not limited thereto. It is worth noting that, in this step, the first protective layer18still remains on the oxide region14and on the first oxide layer16, helping protect the first oxide layer16and the oxide region14from damages occurring during the etching process.

Please refer toFIG. 6. Another etching process is then performed to remove the first protective layer18within the first region A. In this step, the etching process uses the solvent such as phosphate (H3PO4) which has high selectivity to the silicon nitride and the silicon oxide. In other words, only the first protective layer18mainly made of silicon nitride can easily be removed by the etching process, but the second protective layer20and the oxide region14mainly made of silicon oxide are hardly removed by the etching process, so the oxide region14disposed under the first protective layer18is not easily ruined by the etching process.

Please refer toFIG. 7. An etching process (not shown) is performed, to remove the first oxide layer16disposed on the fin structure12within the region A, and the second protective layer20within the second region B simultaneously, so as to completely remove the first oxide layer16and to expose the fin structure12within the first region A. Since in this embodiment, both the first oxide layer16and the second protective layer20mainly comprise silicon oxide, they can be removed in a same etching process simultaneously. It is worth noting that, in order to avoid the oxide region14being damaged by the etching process, in this step, the etching process preferably selects a dry-etching process. Usually, a dry-etching process has a better performance in controlling the etching rate, so compared with a wet-etching process, a dry-etching process is a preferred choice to avoid the oxide region14from being damaged.

Afterwards, referring toFIGS. 8-9, the first protective layer18within the first region B is then removed, and as shown inFIG. 9, a second oxide layer24is then formed to cover the exposed fin structure12within the first region A. It is worth noting that the thickness of the first oxide layer16and the second oxide layer24are different. Preferably, the first oxide layer16is thicker than the second oxide layer24, thereby achieving two individual FinFETs on one substrate10. For example, a FinFET 1 and a FinFET 2 are a n-FET device and a p-FET device respectively, or selected from the group of the low voltage (LV) devices, the memory, the core devices, electrostatic-sensitive device (ESD), IO devices or high voltage (HV) devices, and these devices have different oxide layer thicknesses, having individual work functions.

In another case of the present invention, after the second protective layer20within the second region B is removed (corresponding toFIG. 7), the second oxide layer24can be formed before the first protective layer18within the second region B is removed. In other words, the first protective layer18within the second region B may remain until the second oxide layer24is formed. This process should be contained in the scope of the present invention. However, preferably forming the second oxide layer24is the final process in order to avoid the second oxide layer24being exposed in air for a long time and influencing the performance of the FinFET caused by oxidation.

In summary, the distinguishing feature of the present invention is the use of a first protective layer and a second protective layer, which are made of different materials. For example, in the embodiment mentioned above, the first protective layer comprises silicon nitride, and the second protective layer comprises silicon oxide. These two dielectric layers protect the oxide region disposed in the substrate and surround the fin structure from the damages occurring during the etching processes. Besides, since the silicon nitride first protective layer has high selectivity with the first oxide layer disposed on the fin structure and the oxide region, during the process for removing the silicon nitride first protective layer, the first oxide layer and the oxide region are not ruined by the etching processes, thereby enhancing the yield and the performance of the FinFET.