Power semiconductor device

According to one embodiment, a power semiconductor device includes an IGBT region, first and second electrodes, and a first conductivity-type second semiconductor layer. The region functions as an IGBT element. The first electrode is formed in a surface of a second conductivity-type collector layer opposite to a first conductivity-type first semiconductor layer in the region. The second electrode is connected onto a first conductivity-type emitter layer and a second conductivity-type base layer in a surface of the first conductivity-type base layer and insulated from a gate electrode in the region. The first conductivity-type second semiconductor layer extends from the surface of the first conductivity-type base layer to the first conductivity-type first semiconductor layer around the IGBT region, and connected to the first electrode.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2009-190527, filed on Aug. 19, 2009; the entire contents of which are incorporated herein by reference.

FIELD

Embodiments described herein relate generally to a power semiconductor device used in an electric appliance.

BACKGROUND

IGBTs (insulated gate bipolar transistors) are widely used as power semiconductor elements with a breakdown voltage of approximately 300 V or more. Such IGBTs are often used as switching elements in power supply circuits and inverter circuits. In this case, a free-wheeling diode connected in reverse parallel to the IGBT is needed to pass a sustaining current due to the inductor in these circuits or in the loads connected to these circuits. There is demand for downsizing of power semiconductor devices. Furthermore, there is demand for a power semiconductor device including a free-wheeling diode and an IGBT element in the same chip.

In a power semiconductor device including an IGBT and a free-wheeling diode in the same chip, in order to prevent extension of the depletion layer to the dicing line of the chip, an n-type channel stopper layer is provided at the surface of the terminal portion of the IGBT chip. This serves as a cathode layer electrically connected to the collector electrode of the IGBT. Furthermore, a p-type diffusion layer formed at the outer periphery of the IGBT element region serves as an anode layer connected to the emitter electrode of the IGBT element. A free-wheeling diode, with this p-type diffusion layer serving as an anode layer and the channel stopper layer serving as a cathode layer, is integrally formed so as to be connected in reverse parallel to the IGBT region.

In such a power semiconductor device, when a positive voltage relative to the collector electrode of the IGBT is applied to the emitter electrode, a current flows in the free-wheeling diode along a path composed of the emitter electrode, p-type semiconductor layer, n-type epitaxial layer, channel stopper layer, and collector electrode. However, in this free-wheeling diode, the current concentrates near the surface of the n-type epitaxial layer, and hence the on-resistance of the free-wheeling diode is relatively high.

DETAILED DESCRIPTION

In general, according to one embodiment, a power semiconductor device includes an IGBT region, a first main electrode, a second main electrode, a first conductivity-type second semiconductor layer. The IGBT region includes a plurality of IGBT units. Each of the IGBT units includes a first conductivity-type base layer, a second conductivity-type base layer, a first conductivity-type emitter layer, a gate electrode, a first conductivity-type first semiconductor layer, and a second conductivity-type collector layer. The first conductivity-type base layer has a first surface and a second surface opposed to the first surface. The second conductivity-type base layer is selectively formed on the first surface of the first conductivity-type base layer. The first conductivity-type emitter layer is formed in a surface of the second conductivity-type base layer opposite to the first conductivity-type base layer. The gate electrode is formed on the first conductivity-type base layer, the second conductivity-type base layer, and the first conductivity-type emitter layer via a gate insulating film. The first conductivity-type first semiconductor layer is formed on the second surface of the first conductivity-type base layer. The first conductivity-type first semiconductor layer has a higher impurity concentration than the first first conductivity-type base layer. The second conductivity-type collector layer is formed in a surface of the first conductivity-type first semiconductor layer opposite to the first conductivity-type base layer. The first main electrode is formed in a surface of the second conductivity-type collector layer opposite to the first conductivity-type first semiconductor layer. The second main electrode is electrically connected onto the first conductivity-type emitter layer and the second conductivity-type base layer and insulated from the gate electrode by an interlayer insulating film. The first conductivity-type second semiconductor layer extends from the first surface of the first conductivity-type base layer to the first conductivity-type first semiconductor layer around the IGBT region and electrically connected to the first main electrode.

Embodiments of the invention will now be described with reference to the drawings. Although the embodiments are described assuming that the first conductivity type is n-type and the second conductivity type is p-type, the embodiments can also be practiced with these types interchanged. In the case where n-type impurity layers are labeled with symbols n(−), n, and n(+), the n-type impurity concentration in those layers increases in the order of n(−)≦n≦n(+). This also applies to p-type impurity layers. Furthermore, unless otherwise specified, the impurity concentration refers to the net impurity concentration after compensation between the conductivity types.

The figures used in describing the embodiments are schematic for ease of description, and the shape, dimension, size relation and the like of components in the figures are not necessarily the same as shown in the figures when they are actually put into practice. Furthermore, the shape, dimension, size relation, impurity concentration, material and the like can be modified as long as the effect of the invention is achieved.

Furthermore, unless otherwise specified, the semiconductor layer (including the base layer, collector layer, emitter layer, anode layer, cathode layer and the like) refers to a semiconductor layer illustratively made of Si (silicon). However, other semiconductor layers, such as those made of SiC and GaN, can also be used.

FIG. 1is a plan view of a power semiconductor device of Embodiment 1 of the invention, andFIG. 2shows the A-A cross section ofFIG. 1as viewed in the direction of the arrows. InFIG. 1, a first guard ring layer8, n(−)-type base layer1, n-type second semiconductor layer9, and IGBT region13are shown in plan view, but the detailed structure in the IGBT region13and other components are omitted.

A power semiconductor device100of this embodiment includes an n(−)-type (first conductivity-type) base layer1having a first surface and a second surface opposed to the first surface. The impurity concentration of the n-type base layer1is e.g. approximately 1e12 to 1e15/cm3, and suitably selected depending on the breakdown voltage required for the power semiconductor device100. A p-type (second conductivity-type) base layer2is formed in the first surface of the n(−)-type base layer1. The impurity concentration of the p-type base layer2is e.g. approximately 1e16 to 1e18/cm3. An n-type emitter layer3is selectively formed in the surface of the p-type base layer2. The impurity concentration of the n-type emitter layer3is suitably selected so that ohmic contact can be formed with the emitter electrode (second main electrode)11described later. A trench16penetrating from the surface of the n-type emitter layer3through the n-type emitter layer3and the p-type base layer2into the n(−)-type base layer is formed, and a gate electrode5is formed in this trench via a gate insulating film4so as to fill the trench16. The gate insulating film4is illustratively an oxide film formed by thermally oxidizing the Si surface of the trench16. The gate electrode5is illustratively made of polysilicon. An interlayer insulating film14is formed above the gate electrode5so that the gate electrode5is insulated from the n(−)-type base layer1, the p-type base layer2, the n-type emitter layer3, and the emitter electrode11described later.

An n-type first semiconductor layer6is formed on the second surface of the n(−)-type base layer1, and has a higher impurity concentration than the n(−)-type base layer1, such as 1e15 to 1e17/cm3. A p(+)-type collector layer7is formed on the surface of the n-type first semiconductor layer6opposite to the n(−)-type base layer1.

With the gate electrode5at the center, the region composed of the p(+)-type collector layer7, the n-type first semiconductor layer6, the n(−)-type base layer1, the p-type base layer2, the gate electrode5, and the n-type emitter layer3opposed to the gate electrode5on both ends of the gate electrode5via the gate insulating film4is an IGBT unit12functioning as one IGBT element. This IGBT unit12is repeated in the plane of the n(−)-type base layer1to form an IGBT region13. Here, as shown inFIG. 2, it is also possible to use a structure in which the n-type emitter layer3is not provided on the outer peripheral side of the outermost IGBT unit12to suppress latch-up due to avalanche current in the end portion of the p-type base layer2.

A p-type first guard ring layer8extends from the first surface toward the second surface of the n(−)-type base layer1so as to surround the IGBT region13. More specifically, the first guard ring layer8can have a ring-shaped structure surrounding the IGBT region13. The depth of the first guard ring layer8is formed more deeply than the bottom of the p-type base layer2. The first guard ring layer8has an impurity concentration of approximately 1e18 to 1e20/cm3and serves to cause the depletion layer extending from the interface between the p-type base layer2and the n(−)-type base layer1at the outer peripheral end of the p-type base layer2to extend not only toward the n-type first semiconductor layer6but also toward a chip end portion. This suppresses breakdown at the outer peripheral end of the p-type base layer2due to electric field concentration. The first guard ring layer8can be formed illustratively by ion implantation of a p-type impurity such as boron followed by a thermal diffusion process.

An n(+)-type second semiconductor layer9extends from the first surface of the n(−)-type base layer1to the n-type first semiconductor layer6so as to further surround the first guard ring layer8outside the IGBT region13. As shown inFIG. 1, in the case where the first guard ring layer8is illustratively shaped like a rectangle, such as a square, in plan view, the n(+)-type second semiconductor layer9may have a rectangular ring-shaped structure so as to surround all the four sides of the first guard ring layer, or may be shaped like a letter U so that three sides, except one side, of the first guard ring layer8are enclosed in plan view (not shown). Alternatively, the n(+)-type second semiconductor layer9may be formed opposite to only one side of the first guard ring layer8in plan view (not shown). However, in this case, the area in which the n(+)-type second semiconductor layer9serving as a cathode layer is opposed to the first guard ring layer8, i.e., the cross-sectional area of the current path of the free-wheeling diode, decreases, and hence the on-resistance is higher than in the case where the n(+)-type second semiconductor layer9has a ring-shaped structure.

Furthermore, as long as the n(+)-type second semiconductor layer9reaches the n-type first semiconductor layer6and is electrically joined thereto, it may be joined at the surface of the n-type first semiconductor layer6on the n(−)-type base layer1side, may be joined by digging into the n-type first semiconductor layer6, or may penetrate through the n-type first semiconductor layer6to the p-type collector layer7. The impurity concentration of the n(+)-type second semiconductor layer9can be at least comparable to, and preferably higher than the impurity concentration of the n-type first semiconductor layer6. The n(+)-type second semiconductor layer9serves as a cathode layer of the free-wheeling diode described later. Hence, to reduce the on-resistance of the free-wheeling diode, for instance, the impurity concentration is desirably set to approximately 1e18 to 1e20/cm3. However, even for a lower impurity concentration, there is an effect of accelerating the switching rate of the free-wheeling diode, for instance.

The n(+)-type second semiconductor layer9can be formed by ion implantation from the first surface of the n(−)-type base layer1followed by a thermal diffusion process. Alternatively, it can also be formed by forming a trench illustratively by anisotropic etching such as dry etching or isotropic etching such as wet etching, and filling the trench with an n-type semiconductor layer such as an Si epitaxial layer or polysilicon layer.

A first main electrode10is formed on the surface of the p(+)-type collector layer7opposite to the n-type first semiconductor layer6and electrically connected to the p(+)-type collector layer7. A second main electrode is electrically connected to the upper surface of each of the p-type base layer2and the n-type emitter layer3, insulated from the gate electrode5by the interlayer insulating film14, and electrically connected to the upper surface of the first guard ring layer8beyond the gate electrode5.

A cathode electrode15is formed on the surface of the n(+)-type second semiconductor layer9opposite to the first main electrode side and electrically joined to the first main electrode. For instance, such a junction can be formed by using a bonding wire or the like (not shown) to electrically join the cathode electrode15to a lead frame electrically joined to the power semiconductor device100via the first main electrode.

By the aforementioned electrode connection, in the IGBT region13, an IGBT structure is formed in which the first main electrode acts as a collector electrode, the second main electrode acts as an emitter electrode, and the current flowing from the first main electrode toward the second main electrode is controlled by the gate electrode. Furthermore, a free-wheeling diode is formed in which the p-type first guard ring layer8and the p-type base layer2function as an anode layer and the n-type first semiconductor layer6and the n(+)-type second semiconductor layer9function as a cathode layer. In this free-wheeling diode, the p-type first guard ring layer8and the p-type base layer2serving as an anode layer are connected to the second main electrode11, and the n-type first semiconductor layer6and the n(+)-type second semiconductor layer9serving as a cathode layer are electrically connected to the first main electrode10via the cathode electrode15. Thus, the free-wheeling diode constitutes a reverse parallel connection with the IGBT region13, and they are formed in the same semiconductor chip.

Next, the operation of the power semiconductor device100of this embodiment is described. In the state of voltage application in which the first main electrode10is placed at a positive potential with respect to the second main electrode11, a voltage is applied so that the gate electrode5is placed at a positive potential higher than a threshold with respect to the second main electrode11. Then, an n-channel layer is formed in the portion of the p-type base layer2opposed to the gate electrode5by inversion distribution. When electrons are injected from the second main electrode through the n-type emitter layer3and the channel layer into the n(−)-type drift layer1, holes are injected from the first main electrode through the p(+)-type collector layer7and the n-type first semiconductor layer6into the n(−)-type drift layer1, causing conductivity modulation and resulting in the on-state. The holes subsequently flow through the p-type base layer2to the second main electrode, and the electrons flow through the n-type first semiconductor layer6and the p(+)-type collector layer7to the first main electrode. Consequently, in the IGBT region13, the current flows from the first main electrode to the second main electrode. On the other hand, when the IGBT region is turned off and a voltage is applied so that the second main electrode is placed at a positive potential with respect to the first main electrode, the current flows from the second main electrode to the p-type first guard ring layer8, (1) part of the current flows into the second semiconductor layer9through a current path C1radially extending in the surface of the n(−)-type drift layer1from the p-type first guard ring layer8toward the n-type second semiconductor layer9, and (2) another part flows into the first semiconductor layer6through a current path C2radially extending in the depth direction of the n(−)-type drift layer1from the p-type first guard ring layer8toward the n-type first semiconductor layer6, and flows along the plane of the first semiconductor layer into the second semiconductor layer9. Furthermore, (3) the current flows from the second main electrode to the p-type base layer2, flows into the first semiconductor layer6through a current path C3in the depth direction of the n(−)-type drift layer1from the p-type base layer2toward the n-type first semiconductor layer6, and flows along the plane of the first semiconductor layer6into the second semiconductor layer9. The current through the current path C1and the current through the current paths C2and C3merge in the second semiconductor layer9and flow through the cathode electrode15to the first main electrode. Consequently, this turns on the free-wheeling diode in which the first guard ring layer8and the p-type base layer2serve as an anode layer and the first semiconductor layer6and the second semiconductor layer9serve as a cathode layer, and a current flows from the second main electrode toward the first main electrode.

The free-wheeling diode of the power semiconductor device100of this embodiment has a structure in which the n(+)-type second semiconductor layer9serving as a cathode layer extends from the first surface toward the second surface of the n(−)-type base layer1, reaches the n-type first semiconductor layer6, and is electrically connected to the n-type first semiconductor layer6. Hence, it is characterized in causing not only the n(+)-type second semiconductor layer9to function as a cathode layer, but also the n-type first semiconductor layer6to function as a cathode layer. Consequently, in contrast to the conventional power semiconductor device including the free-wheeling diode described in JP-A H11-54747 (Kokai) in which the current of the free-wheeling diode flows only near the surface of the n(−)-type base layer1(includes only the current path C1near the surface), the free-wheeling diode of this embodiment further includes the current paths C2and C3for flow in the depth direction of the n(−)-type base layer1, and hence the on-resistance of the free-wheeling diode can be further reduced. Here,FIG. 3shows a result of simulation-based comparison between the voltage-current characteristics of the free-wheeling diode of the conventional structure with a cathode layer formed like a ring in the surface of the n(−)-type base layer and those of the free-wheeling diode according to this embodiment. As shown, according to the invention, at the same on-voltage, the current density can be increased by 30% or more. This effect is attributed to the fact that the distance from the p-type first guard ring layer8and the p-type base layer2to the n-type first semiconductor layer6is typically shorter than the distance from the p-type first guard ring layer8to the n(+)-type second semiconductor layer9, in addition to the increased area of the cathode of the free-wheeling diode according to this embodiment. Thus, this is a special effect of the invention.

The on-resistance of the free-wheeling diode of this embodiment is determined by the distance from the p-type first guard ring layer8and the p-type base layer2to the n-type first semiconductor layer6and the n(+)-type second semiconductor layer9, and the respective impurity concentrations. Increasing the impurity concentration of the n-type first semiconductor layer6is undesirable because it suppresses the injection of holes from the p(+)-type collector layer7in the operation of the IGBT. Hence, it is desirably suppressed to approximately 1e15 to 1e17/cm3. Thus, the reduction of the on-resistance of the free-wheeling diode desirably relies on increasing the impurity concentration of the n(+)-type second semiconductor layer9. The impurity concentration of the n(+)-type second semiconductor layer is desirably set to approximately 1e18 to 1e20/cm3but can be as low as that of the n-type first semiconductor layer6. In this case, at the expense of on-resistance, the fast responsiveness of the free-wheeling diode is improved.

The trench gate electrode in the IGBT region may be shaped like a stripe extending in one direction, or can have a lattice or staggered structure, for instance. In the case where the gate electrode5is shaped like a stripe, the n-type emitter layer3may be shaped like a stripe extending along the stripe direction of the gate electrode5, or it is also possible to use a structure in which the n-type emitter layer3and the p-type base layer2are alternately arranged. Furthermore, although the gate electrode has been described in the case of a trench gate structure, naturally it is also possible to use a planar gate electrode described later in Variation1of this embodiment. Furthermore, it is clear that any known IGBT structure can be combined with the free-wheeling diode according to the invention.

The first guard ring layer8has been described as a layer which is independent of and deeper than the p-type base layer2. In reality, the p-type base layer2is often formed to also serve as the first guard ring layer8primarily for cost reduction. However, even in this case, it is clear that the p-type base layer2functions as the anode layer of the free-wheeling diode according to the invention and is applicable to the structure of the invention.

These modifications are all applicable also to the following embodiments and variations.

As described above, the distance from the p-type first guard ring layer8and the p-type base layer2to the n-type first semiconductor layer6is typically shorter than the distance from the p-type first guard ring layer8to the n(+)-type second semiconductor layer9. This assumes the case where the distance from the p-type first guard ring layer8to the n(+)-type second semiconductor layer9is lengthened to weaken the surface electric field to obtain a desired breakdown voltage. However, rather than the conventional n(+)-type second semiconductor layer formed only in the surface, the n(+)-type second semiconductor layer9formed to reach the n-type first semiconductor layer6as in this invention can suppress extension of the surface electric field to the terminal portion. Hence, the length of the terminal portion can be shortened. This is a special effect of the invention, which can also further improve the characteristics of the diode. That is, the invention can achieve the double effect of improving the characteristics of the integrated diode and reducing the area of the terminal portion.

FIG. 4shows a sectional view of the major part of a power semiconductor device200of Variation1of Embodiment 1 of the invention. The plan view of the power semiconductor device200is generally the same asFIG. 1, andFIG. 4corresponds to the sectional view of the A-A cross section ofFIG. 1as viewed in the direction of the arrows. In the following description, portions identical or similar to those of the above Embodiment 1 are labeled with like reference numerals, and only the portions different from those of Embodiment 1 are described.

The power semiconductor device200of this variation is different from the power semiconductor device100of Embodiment 1 in that the gate electrode has a planar structure instead of the trench structure. Another difference from the power semiconductor device100of Embodiment 1 is that a p-type second guard ring layer29is provided between the p-type first guard ring layer8and the n(+)-type second semiconductor layer9. The rest is similar to Embodiment 1. This difference is described below.

In the power semiconductor device200of this variation, a p-type base layer22is selectively formed on the first surface of the n(−)-type base layer1. An n-type emitter layer23is selectively formed in the surface of the p-type base layer22. A planar gate electrode25is formed on the surface of the n-type emitter layer23, the p-type base layer22, and the n(−)-type base layer1via a gate insulating film24. An interlayer insulating film26is formed so as to cover the gate electrode25. The second main electrode is insulated from the gate electrode25by the interlayer insulating film26and electrically connected to the surface of the n-type emitter layer23, the p-type base layer22, and the p-type first guard ring layer8.

The p-type second guard ring layer29extends from the surface of the n(−)-type base layer1toward the first main electrode so as to surround the p-type first guard ring layer8, more specifically in a ring-shaped structure, between the p-type first guard ring layer8and the n-type second semiconductor layer9. This second guard ring layer29is integrally formed in the same process as the first guard ring layer, and the depth and impurity concentration are the same as the first guad ring layer. These layers can be formed by ion implantation of a p-type impurity followed by thermal diffusion. Alternatively, they can also be formed by forming trenches and filling the trenches with an Si epitaxial layer, polysilicon layer or the like. InFIG. 4, the second guard ring layer29is formed in a ring-shaped structure at three positions concentrically about the center of the IGBT region. However, whether it is formed singly or in a plurality can be suitably selected.

On the surface of the respective second guard ring layers29at three positions, guard ring electrodes30electrically connected thereto are formed, and these are insulated from each other and placed in a floating state.

Like the free-wheeling diode of the power semiconductor device100of Embodiment 1, the power semiconductor device200of this variation also has a structure in which the n(+)-type second semiconductor layer9serving as a cathode layer extends from the first surface toward the second surface of the n(−)-type base layer1, reaches the n-type first semiconductor layer6, and is electrically connected to the n-type first semiconductor layer6. Hence, it is characterized in causing not only the n(+)-type second semiconductor layer9to function as a cathode layer, but also the n-type first semiconductor layer6to function as a cathode layer. Consequently, in addition to flowing near the surface of the n(−)-type base layer1(including the current path near the surface), the current of the free-wheeling diode also includes the current paths for flow in the depth direction, and hence the on-resistance of the free-wheeling diode can be reduced.

Furthermore, the second guard ring layer29serves to increase the breakdown voltage in the chip terminal portion as compared with the power semiconductor device100of Embodiment 1.

FIG. 5shows a sectional view of the major part of a power semiconductor device300of Variation2of Embodiment 1 of the invention. The plan view of the power semiconductor device300is generally the same asFIG. 1, andFIG. 5corresponds to the sectional view of the A-A cross section ofFIG. 1as viewed in the direction of the arrows. In the following description, portions identical or similar to those of the above Embodiment 1 are labeled with like reference numerals, and only the portions different from those of Embodiment 1 are described.

The power semiconductor device300of this variation is different from the power semiconductor device100of Embodiment 1 in that the n-type first semiconductor layer6further includes an n(+)-type third semiconductor layer42in its plane. In other words, in the power semiconductor device300, the region of the n-type first semiconductor layer6extending at least from immediately below the p-type first guard ring layer8to the portion where the n(+)-type second semiconductor layer9reaches the n-type first semiconductor layer6, constitutes an n(+)-type third semiconductor layer42having a higher impurity concentration than the n-type first semiconductor layer6. The rest is similar to Embodiment 1.

Like the free-wheeling diode of the power semiconductor device100of Embodiment 1, the power semiconductor device300of this variation also has a structure in which the n(+)-type second semiconductor layer9serving as a cathode layer extends from the first surface toward the second surface of the n(−)-type base layer1, reaches the n(+)-type third semiconductor layer42constituting part of the n-type first semiconductor layer6, and is electrically connected to the n-type first semiconductor layer6and the n(+)-type third semiconductor layer42. Hence, it is characterized in causing not only the n(+)-type second semiconductor layer9to function as a cathode layer, but also the n-type first semiconductor layer6and the n(+)-type third semiconductor layer42to function as a cathode layer. Consequently, in addition to flowing near the surface of the n(−)-type base layer1(including the current path C1near the surface), the current of the free-wheeling diode also includes the current paths C2and C3for flow in the depth direction, and hence the on-resistance of the free-wheeling diode can be reduced.

Furthermore, the region of the n-type first semiconductor layer6extending at least from immediately below the p-type first guard ring layer8to the portion where the n-type second semiconductor layer9reaches the n-type first semiconductor layer6, constitutes an n(+)-type third semiconductor42layer having a higher impurity concentration than the n-type first semiconductor layer6. Hence, the resistance of the current path C2for flow from the first guard ring layer through the n(−)-type base layer1and the n(+)-type third semiconductor layer42to the n-type second semiconductor layer9can be made lower than that of Embodiment 1. Consequently, the on-resistance of the free-wheeling diode can be further reduced as compared with Embodiment 1.

In this variation, the n-type first semiconductor layer6is not completely turned into the n(+)-type third semiconductor layer42having a high impurity concentration. This is because if the impurity concentration of the n-type first semiconductor layer6is increased in the IGBT region13, injection of holes from the p(+)-type collector layer7into the n(−)-type base layer1is suppressed in the IGBT region13in the on-state of the IGBT, hence increasing the collector-emitter on-resistance in the IGBT region13.

An example method for forming the n(+)-type third semiconductor layer42is as follows. After the n-type first semiconductor layer6is formed, an n-type impurity is ion-implanted into the region of the n-type first semiconductor layer6extending from immediately below the p-type first guard ring layer8to the portion where the n(+)-type second semiconductor layer9reaches the n-type first semiconductor layer6. Subsequently, an n(−)-type base layer1is formed by epitaxial growth. Thus, the n(+)-type third semiconductor layer42can be formed.

FIG. 6is a sectional view of the major part of a power semiconductor device400of Embodiment 2 of the invention. The plan view of the power semiconductor device400is generally the same asFIG. 1, andFIG. 6corresponds to the sectional view of the A-A cross section ofFIG. 1as viewed in the direction of the arrows. In the following description, portions identical or similar to those of the above Embodiment 1 are labeled with like reference numerals, and only the portions different from those of Embodiment 1 are described.

The power semiconductor device400of this embodiment is different from the power semiconductor device100of Embodiment 1 in that the n(+)-type second semiconductor layer9reaching the n-type first semiconductor layer6is replaced by an n(+)-type second semiconductor layer51reaching the first main electrode10. The rest is similar to Embodiment 1. This difference is described below.

The n(+)-type second semiconductor layer51of the power semiconductor device400of this embodiment has a structure surrounding the first guard ring layer8, preferably a ring-shaped structure surrounding the first guard ring layer8, extends from the first surface toward the second surface of the n(−)-type base layer1, penetrates through the n-type first semiconductor layer6and the p(+)-type collector layer7, reaches the first main electrode10, and is electrically connected to the first main electrode. Here, the ring-shaped structure of the second semiconductor layer51may, in its entire region, penetrate through the n-type first semiconductor layer6and the p(+)-type collector layer7and reach the first main electrode10, but this is not necessary. In other words, it may penetrate through the n-type first semiconductor layer6and the p(+)-type collector layer7and be connected to the first main electrode10while maintaining the ring-shaped structure, but this is not necessary. For instance, the n-type second semiconductor layer51may have a structure of extending from the first surface toward the second surface of the n(−)-type base layer1and being connected to the n-type first semiconductor layer6while maintaining the ring-shaped structure, part of the ring-shaped structure being further turned into a columnar structure, which penetrates through the n-type first semiconductor layer6and the p(+)-type collector layer7and reaches the first main electrode10. The portion of the n(+)-type second semiconductor layer51penetrating through the n-type first semiconductor layer6and the p(+)-type collector layer7only needs to have a structure of enabling the n-type first semiconductor layer6and the n(+)-type second semiconductor layer51to be electrically connected to the first main electrode10.

The aforementioned n(+)-type second semiconductor layer51is directly joined to the first main electrode10. Thus, the free-wheeling diode in which the p-type first guard ring layer8and the p-type base layer2serve as an anode layer and the n-type first semiconductor layer6and the n(+)-type second semiconductor layer51serve as a cathode layer, is connected in reverse parallel to the IGBT region13. In contrast to Embodiment 1, there is no need to provide a cathode electrode15electrically joined to the upper surface of the n(+)-type second semiconductor layer51, and there is no need of wire bonding and the like for electrically joining the cathode electrode15to the lead frame on which the power semiconductor device400is mounted via the first main electrode. This further simplifies assembly of the semiconductor device.

Like the free-wheeling diode of the power semiconductor device100of Embodiment 1, the power semiconductor device400of this embodiment also has a structure in which the n(+)-type second semiconductor layer51serving as a cathode layer extends from the first surface toward the second surface of the n(−)-type base layer1, reaches the n-type first semiconductor layer6, and is electrically connected to the n-type first semiconductor layer6. Hence, it is characterized in causing not only the n(+)-type second semiconductor layer51to function as a cathode layer, but also the n-type first semiconductor layer6to function as a cathode layer. Consequently, in addition to flowing near the surface of the n(−)-type base layer1(including the current path C1near the surface), the current of the free-wheeling diode also includes the current paths C2and C3for flow in the depth direction, and hence the on-resistance of the free-wheeling diode can be reduced.

FIG. 7shows a plan view of a power semiconductor device500of Embodiment 3 of the invention, andFIG. 8is a sectional view in which the B-B cross section inFIG. 7is viewed in the direction of the arrows. The sectional view in which the A-A cross section ofFIG. 7is viewed in the direction of the arrows is the same asFIG. 2. In the following description, portions identical or similar to those of the above Embodiment 1 are labeled with like reference numerals, and only the portions different from those of Embodiment 1 are described.

The power semiconductor device500of this embodiment is different from the power semiconductor device100of Embodiment 1 in further including a conductor71which passes through part of the cross section, parallel to the first surface of the n(−)-type base layer1, of the n(+)-type second semiconductor layer9surrounding the p-type first guard ring layer8, extends from the first surface of the n(−)-type base layer1to the first main electrode10, and is electrically connected to the first main electrode10. In other words, the conductor71penetrates from the first surface of the n(−)-type base layer1through the n(+)-type second semiconductor layer9and the p(+)-type collector layer7to the first main electrode10and is electrically connected to the first main electrode10so that the n(+)-type second semiconductor layer9is electrically connected to the first main electrode10. Thus, the free-wheeling diode in which the p-type first guard ring layer8and the p-type base layer2serve as an anode layer and the n-type first semiconductor layer6and the n(+)-type second semiconductor layer9serve as a cathode layer is connected in reverse parallel to the IGBT region13.

The conductor71only needs to be made of a conductive material, and either a semiconductor layer or a metal may be used. For instance, a conductive material having good filling capability, such as polysilicon as a semiconductor, or tungsten as a metal, is preferable. The conductor71can be formed by forming a via penetrating from the first surface of the n(−)-type base layer1through the n(+)-type second semiconductor layer9and the p(+)-type collector layer7to the first main electrode10, by etching or the like, and burying a conductor71in this via.

Also in the power semiconductor device500of this embodiment, like the power semiconductor device400of Embodiment 2, in contrast to the power semiconductor device100of Embodiment 1, there is no need to provide a cathode electrode15electrically joined to the upper surface of the n(+)-type second semiconductor layer9, and there is no need of wire bonding and the like for electrically joining the cathode electrode15to the lead frame on which the power semiconductor device500is mounted via the first main electrode. This further simplifies assembly of the semiconductor device.

Like the free-wheeling diode of the power semiconductor device100of Embodiment 1, the power semiconductor device500of this embodiment also has a structure in which the second semiconductor layer9serving as a cathode layer extends from the first surface toward the second surface of the n(−)-type base layer1, reaches the n-type first semiconductor layer6, and is electrically connected to the n-type first semiconductor layer6. Hence, it is characterized in causing not only the n(+)-type second semiconductor layer9to function as a cathode layer, but also the n-type first semiconductor layer6to function as a cathode layer. Consequently, in addition to flowing near the surface of the n(−)-type base layer1(including the current path C1near the surface), the current of the free-wheeling diode also includes the current paths C2and C3for flow in the depth direction, and hence the on-resistance of the free-wheeling diode can be reduced.

In the power semiconductor device500of this embodiment, the conductor71is made of a metal material. Hence, the on-resistance of the free-wheeling diode can be further reduced as compared with the power semiconductor device400of Embodiment 2.

Furthermore, this embodiment has a structure in which a via extending from the first surface of the n(−)-type base layer1to the first main electrode10is formed in the n(+)-type second semiconductor layer9and the conductor71is buried in this via. This is different from the structure in which the conductor71is exposed to the chip end portion of the power semiconductor device500. However, the chip can be diced along the extending direction of the n(+)-type second semiconductor layer9so that the dicing line cuts the conductor71to separate the chip, allowing a structure in which the conductor71is exposed to the chip end portion (dicing plane).

FIG. 9is a sectional view of the major part of a power semiconductor device600of Embodiment 4 of the invention. The plan view of the power semiconductor device600is generally the same asFIG. 1, andFIG. 9corresponds to the sectional view of the A-A cross section ofFIG. 1as viewed in the direction of the arrows. In the following description, portions identical or similar to those of the above Embodiment 1 are labeled with like reference numerals, and only the portions different from those of Embodiment 1 are described.

The power semiconductor device600of this embodiment is different from the power semiconductor device100of Embodiment 1 in that a buried layer83is formed in the n(+)-type second semiconductor layer81via an insulating film82. The insulating film82only needs to be made of an insulating material, such as oxide film and nitride film. Because the buried layer83is intended for being buried, it may be made of either a conductive material or an insulating material. As an example, it can be a polysilicon layer or the like.

An example method for forming the n(+)-type second semiconductor layer81, the insulating film82, and the buried layer83is as follows. A trench extending from the first surface to the second surface of the n(−)-type base layer1is formed around the p-type first guard ring layer8, preferably in a ring-shaped structure. An n-type impurity such as P (phosphorus) or As (arsenic) is ion-implanted into the sidewall and bottom of the trench, and then thermally diffused. Thus, an n(+)-type second semiconductor layer81can be formed. Alternatively, after the trench is formed, the sidewall and bottom of the trench are exposed to an atmosphere containing POCl3(phosphorus oxychloride) at high temperature so that phosphorus is diffused from the sidewall and bottom of the trench into the n(−)-type base layer1, and thus an n(+)-type second semiconductor layer81can be formed.

Subsequently, the surface of the n(+)-type second semiconductor layer81formed at the sidewall and bottom of the trench is thermally oxidized to form an oxide film (SiO2) constituting an insulating film82. Alternatively, this formation of the insulating film82may be based on deposition of SiO2film or nitride film (SiN) by CVD (chemical vapor deposition). In any case, the insulating film82is formed along the sidewall and bottom of the trench and directly inherits the shape of the trench.

Subsequently, after a buried layer83is formed so as to fill the trench, the surface of the buried layer83is made flush with the first surface of the n(−)-type base layer1by a surface planarization process such as CMP (chemical mechanical polishing) or CDE (chemical dry etching). Here, the buried layer83may be made of either a conductive material or an insulating material as long as it can be buried flat. An example material having good filling capability can be polysilicon as a semiconductor or tungsten as a metal. In this embodiment, the buried layer83is formed via the insulating film82. However, without the intermediary of the insulating film82, the buried layer83can also be directly formed on the surface of the n(+)-type second semiconductor layer81to fill the trench. In the case where silicon is formed on the surface of the insulating film82by CVD, a silicon epitaxial layer is not formed, but polysilicon is deposited. Because polysilicon has higher trench filling capability than a silicon epitaxial layer, it is preferable that a buried layer83made of polysilicon be buried via the insulating film82. The structure according to this embodiment is characterized in that a deep n-type second semiconductor layer81serving as a cathode region of the diode can be easily formed. In other words, while deep diffusion, or trench formation followed by epitaxial formation, is needed to form a deep n-type second semiconductor layer9according to Embodiment 1 and the like, this embodiment is characterized in that burying can be easily performed using polysilicon and the like.

Like the free-wheeling diode of the power semiconductor device100of Embodiment 1, the power semiconductor device600of this embodiment also has a structure in which the n(+)-type second semiconductor layer81serving as a cathode layer extends from the first surface toward the second surface of the n(−)-type base layer1, reaches the n-type first semiconductor layer6, and is electrically connected to the n-type first semiconductor layer6. Hence, it is characterized in causing not only the n(+)-type second semiconductor layer81to function as a cathode layer, but also the n-type first semiconductor layer6to function as a cathode layer. Consequently, in addition to flowing near the surface of the n(−)-type base layer1(including the current path C1near the surface), the current of the free-wheeling diode also includes the current paths C2and C3for flow in the depth direction, and hence the on-resistance of the free-wheeling diode can be reduced.

In the power semiconductor device600of this embodiment, the cathode electrode is formed on the surface of the n(+)-type second semiconductor layer81, preferably on the surface of the buried layer83as well, so as to be electrically connected at least to the n(+)-type second semiconductor layer81.

FIGS. 10A and 10Bshow schematic views of a power semiconductor device700of Embodiment 5 of the invention, whereFIG. 10Ais a plan view thereof, andFIG. 10Bis a schematic view of the C-C cross section ofFIG. 10Aas viewed in the direction of the arrows. InFIG. 10A, a p-type first guard ring layer8, n(−)-type base layer1, n(+)-type second semiconductor layer91, and IGBT region13are shown in plan view, but the detailed structure in the IGBT region13and other components are omitted. InFIG. 10B, the detailed structure of the IGBT region13is as shown in the cross section ofFIG. 2, and hence is omitted.

As shown in the plan view ofFIG. 10Ain which the power semiconductor device100illustrated in Embodiment 1 is used as a unit, the power semiconductor device700of this embodiment is formed by repeating the structure of the power semiconductor device100three times laterally in the semiconductor chip. Here, the structure of the IGBT region13has the same cross-sectional structure as the IGBT region of Embodiment 1 shown inFIG. 2, and its detail is omitted. The power semiconductor devices100are formed successively and repeatedly so that the adjacent power semiconductor devices100share the adjacent portion of the n(+)-type second semiconductor layer9. Consequently, the n(+)-type second semiconductor layer9of Embodiment 1 is formed like a ladder, constituting an n(+)-type second semiconductor layer91in which the IGBT region13is formed in the opening of the ladder. The n(+)-type second semiconductor layer91has a planar shape surrounding each IGBT region13in the opening of the ladder.

More specifically, the power semiconductor device700is configured as follows. The IGBT region13is composed of a plurality of IGBT units described in Embodiment 1. Each of the IGBT units includes an n-type (first conductivity-type) base layer1having a first surface and a second surface opposed to the first surface. A p-type (second conductivity-type) base layer is selectively formed on the first surface of the n(−)-type base layer. An n-type emitter layer3is formed in the surface of the p-type base layer2opposite to the n(−)-type base layer1. A gate electrode5is formed on the n(−)-type base layer1, the p-type base layer2, and the n-type emitter layer3via a gate insulating film4. An n-type first semiconductor layer6having a higher impurity concentration than the n(−)-type base layer1is formed on the second surface of the n(−)-type base layer1. A p(+)-type collector layer7is formed in the surface of the n-type first semiconductor layer6opposite to the n(−)-type base layer1.

The aforementioned IGBT regions13are arranged so as to repeat three units, and a p-type first guard ring layer8is formed deeper than the p-type base layer2from the first surface toward the second surface of the n(−)-type base layer1so as to surround each of the IGBT regions13in a ring shape. A first main electrode10is formed on the surface of the p(+)-type collector layer7opposite to the n-type first semiconductor layer6. A second main electrode11(not shown) is formed, electrically connected onto the n-type emitter layer3and the p-type base layer2and onto the p-type first guard ring layer8, and insulated from the gate electrode5by an interlayer insulating film.

Furthermore, an n(+)-type second semiconductor layer91is formed from the first surface of the n(−)-type base layer1to the n-type first semiconductor layer so as to surround each of the IGBT regions13and each of the p-type first guard ring layers8in a ring shape. In other words, the n(+)-type second semiconductor layer91is formed like a ladder, and each of the IGBT regions13surrounded by the p-type first guard ring layer8is arranged in its opening.

Like Embodiment 1, a cathode electrode15(not shown) is formed on and electrically connected to the surface of the n(+)-type second semiconductor layer91. By wire bonding or the like, the cathode electrode15is electrically connected (not shown) to a lead frame on which the power semiconductor device700is electrically connected and mounted via the first main electrode10.

Like Embodiment 1, by the aforementioned electrode connection, in each of the plurality of IGBT regions13, an IGBT structure is formed in which the first main electrode acts as a collector electrode, the second main electrode11acts as an emitter electrode, and the current flowing from the first main electrode10toward the second main electrode11is controlled by the gate electrode5. Furthermore, a free-wheeling diode is formed in which the p-type first guard ring layer8and the p-type base layer2function as an anode layer and the n-type first semiconductor layer6and the n(+)-type second semiconductor layer91function as a cathode layer. The p-type first guard ring layer8and the p-type base layer2serving as an anode layer are connected to the second main electrode, and the n-type first semiconductor layer6and the n(+)-type second semiconductor layer91serving as a cathode layer are electrically connected to the first main electrode10via the cathode electrode15. Thus, this free-wheeling diode constitutes a reverse parallel connection with the IGBT region, and they are formed in the same semiconductor chip.

Like the free-wheeling diode of the power semiconductor device100of Embodiment 1, the power semiconductor device700of this embodiment also has a structure in which the n(+)-type second semiconductor layer91serving as a cathode layer extends from the first surface toward the second surface of the n(−)-type base layer1, reaches the n-type first semiconductor layer6, and is electrically connected to the n-type first semiconductor layer6. Hence, it is characterized in causing not only the n(+)-type second semiconductor layer91to function as a cathode layer, but also the n-type first semiconductor layer6to function as a cathode layer. Consequently, in addition to flowing near the surface of the n(−)-type base layer1(including the current path C1near the surface), the current of the free-wheeling diode also includes the current paths C2and C3for flow in the depth direction, and hence the on-resistance of the free-wheeling diode can be reduced. Furthermore, the area occupied by the free-wheeling diode in a chip can be increased as compared with the power semiconductor device100of Embodiment 1, and hence the current capacity of the free-wheeling diode can be increased.

This embodiment has a structure in which the IGBT region13is laterally repeated three times. However, naturally, it is also possible to repeat more times. Furthermore, it is also possible to repeat multiple times both longitudinally and laterally in a matrix arrangement. In addition, the technical features of Variations1or2of Embodiment 1 are also applicable to this embodiment. In other words, the trench gate structure can be replaced by a planar gate structure. Naturally, the p-type second guard ring layer and the n-type third semiconductor layer are also applicable to this embodiment.

In this embodiment, a cathode electrode15, not shown, is formed on the surface of the n(+)-type second semiconductor layer91, and electrically connected (not shown), by wire bonding or the like, to a lead frame on which the power semiconductor device700is mounted via the first main electrode10. Thus, the cathode layer is electrically connected to the first main electrode. The electrical connection between the cathode layer and the first main electrode in this embodiment can be based on an n(+)-type second semiconductor layer51or a conductor71as illustrated in Embodiment 2 or 3. Alternatively, as illustrated in Embodiment 4, it can be based on the n(+)-type second semiconductor layer81, insulating film82, buried layer83, and cathode electrode15.

FIG. 11is a sectional view of the major part of a power semiconductor device800of Embodiment 6 of the invention. The plan view of the power semiconductor device800is generally the same asFIG. 1, andFIG. 11corresponds to the sectional view of the A-A cross section ofFIG. 1as viewed in the direction of the arrows. In the following description, portions identical or similar to those of the above Embodiment 1 are labeled with like reference numerals, and only the portions different from those of Embodiment 1 are described.

The power semiconductor device800of this embodiment is different from the power semiconductor device100of Embodiment 1 in that an n(+)-type fourth semiconductor layer17is further formed in the p(+)-type collector layer7below the IGBT region13. The n(+)-type fourth semiconductor layer penetrates through the p(+)-type collector layer7and is connected to the n-type first semiconductor layer6on one hand and to the first main electrode on the other. The connection between the n(+)-type fourth semiconductor layer and the n-type first semiconductor layer6and the connection between the n(+)-type fourth semiconductor layer and the first main electrode allow intervention of other conductive layers therebetween as long as electrical connection is ensured. The n(+)-type fourth semiconductor layer can be formed as a plurality of stripes extending in the plane parallel to the first surface of the n(−)-type base layer1. Alternatively, the n(+)-type fourth semiconductor layer can be formed like a lattice or discretely distributed as a plurality of pinholes in the plane parallel to the first surface of the n(−)-type base layer1.

In this embodiment, like the n(+)-type second semiconductor layer9, the n(+)-type fourth semiconductor layer17also functions as a cathode layer. In other words, a diode is formed in which the current flows along the second main electrode11, p-type base layer2, n(−)-type base layer1, n-type first semiconductor layer6, n(+)-type fourth semiconductor layer17, and first main electrode10.

Like the free-wheeling diode of the power semiconductor device100of Embodiment 1, the power semiconductor device800of this embodiment also has a structure in which the n(+)-type second semiconductor layer9serving as a cathode layer extends from the first surface toward the second surface of the n(−)-type base layer1, reaches the n-type first semiconductor layer6, and is electrically connected thereto. Hence, it is characterized in causing not only the n(+)-type second semiconductor layer9to function as a cathode layer, but also the n-type first semiconductor layer6to function as a cathode layer. Consequently, in addition to flowing near the surface of the n(−)-type base layer1(including the current path C1near the surface), the current of the free-wheeling diode also includes the current paths C2and C3for flow in the depth direction, and hence the on-resistance of the free-wheeling diode can be reduced.

Furthermore, a diode is formed in which the current flows along the second main electrode11, p-type base layer2, n(−)-type base layer1, n-type first semiconductor layer6, n(+)-type fourth semiconductor layer17, and first main electrode10. Hence, the on-resistance of the free-wheeling diode can be further reduced as compared with Embodiment 1.

The aspects according to the invention have been described with reference to the above embodiments. However, the invention is not limited to the configuration illustrated in the embodiments, and it is understood that the constituent material, layer thickness, pattern configuration and the like can be modified within the scope not departing from the spirit of the invention. Furthermore, the film formation method, film formation condition, etching method, and etching condition of the layers, or the method for planarizing the substrate surface and the like, can be modified within the scope not departing from the spirit of the invention.

In particular, it is understood that each structural difference from Embodiment 1 described in Embodiments 2 to 5 is also applicable to Variations1and2of Embodiment 1.