Fabrication and integration of devices with top and bottom electrodes including magnetic tunnel junctions

An electronic device manufacturing process includes depositing a bottom electrode layer. Then an electronic device is fabricated on the bottom electrode layer. Patterning of the bottom electrode layer is performed after fabricating the electronic device and in a separate process from patterning a top electrode. A first dielectric layer is then deposited on the electronic device and the bottom electrode layer followed by a top electrode layer. The top electrode is then patterned in a separate process from the bottom electrode. Separately patterning the top and bottom electrodes improves yields by reducing voids in the dielectric material between electronic devices. One electronic device the manufacturing process is well-suited for is magnetic tunnel junctions (MTJs).

TECHNICAL FIELD

The present disclosure generally relates to manufacturing of electronic devices. More specifically, the present disclosure relates to manufacturing processes for magnetic tunnel junctions in magnetic random access memory.

BACKGROUND

Unlike conventional random access memory (RAM) chip technologies, in magnetic RAM (MRAM) data is not stored as electric charge, but is instead stored by magnetic polarization of storage elements. The storage elements are formed from two ferromagnetic layers separated by an insulating layer. One of the two layers has at least one pinned magnetic polarization (or fixed layer) set to a particular polarity by an anti-ferromagnetic layer (AFM). The magnetic polarity of the other magnetic layer (or free layer) is altered to represent either a “1” (i.e., anti-parallel polarity) or “0” (i.e., parallel polarity). One such device having a fixed layer, an insulating layer, and a free layer is a magnetic tunnel junction (MTJ). The electrical resistance of an MTJ is dependent on the magnetic polarity of the free layer compared to the magnetic polarity of the fixed layer. A memory device such as MRAM is built from an array of individually addressable MTJs.

FIG. 4Ais a block diagram illustrating a spin-torque transfer (STT) magnetic tunnel junction in a low resistance state. A magnetic tunnel junction (MTJ)400includes a fixed layer402stacked with a tunnel barrier404and a free layer406. A magnetic polarization of the fixed layer402is pinned in one direction by an anti-ferromagnetic layer (AFM) (not shown). A magnetic polarization of the free layer406is free to change between parallel and anti-parallel states. A resistance of the MTJ400depends, in part, on the magnetic polarization of the free layer406. For example, when the magnetic polarization of the free layer406and the fixed layer402are substantially aligned, the MTJ400has a low resistance. The other stable state of the free layer406is examined inFIG. 4B.

FIG. 4Bis a block diagram illustrating a spin-torque transfer (STT) magnetic tunnel junction in a high resistance state. For example, the magnetic polarization of the free layer406and the magnetic polarization of the fixed layer402are in substantially opposite directions. In this case, the MTJ400has a high resistance.

MRAM is a non-volatile memory device in which data is stored as a magnetic polarity of the free layer. Read and write speed of MRAM is faster than NAND flash memory. As cell sizes shrink and densities increase, yields and process margin of conventional manufacturing processes decrease, resulting in an increase in cost per die or potential reliability issues with the MRAM. One cause of MRAM failure is electrical shorting between neighboring conductors.

A bottom electrode and a top electrode in an MRAM bitcell can be etched during the same manufacturing process to save costs. After etching the top and bottom electrodes to form individual cells, a dielectric is deposited to fill the space between cells. As cells are spaced closer together to reach higher densities, the aspect ratio of the opening (depth of the opening divided by width of the opening) between cells increases. Dielectric deposition techniques such as chemical vapor deposition (CVD) or physical vapor deposition (PVD) are unable to completely fill large aspect ratio spaces leading to voids in the dielectric layer. If filled with conductive material, the voids may lead to unintentional electrical shorting of conductors later in processing.

The shorting is now described in more detail referencingFIG. 3.FIG. 3is a top-down view of an array of magnetic tunnel junctions. An array300of magnetic tunnel junctions334includes top conductors320(for example manufactured as trenches). An individual MTJ334may be accessed by coupling the top conductor320to the desired individual MTJ334through top electrodes332. As discussed above, during manufacturing, voids may form in the dielectric layer between the top electrodes332and the top conductors320. During deposition of the top conductor material, the conducting material may fill the void resulting in a short340between top conductors320. The short340may result in failure of the array300. Thus, manufacturing yield decreases.

Conventionally, the number of shorts340are reduced by increasing a height of a top via (not shown) coupled between the top electrode332and the top conductor320. The top via is manufactured taller than the height of the void to prevent overlap of the void and the top conductor320, preventing the shorts from occurring. The height of the via is defined, in part, by each generation of technology. Because technology is scaled by 70% for each new generation, the height of the via is significantly reduced at each new generation. Process yields may suffer as the shorting issue increases at new generations.

BRIEF SUMMARY

According to one aspect of the disclosure, an electronic device manufacturing process includes depositing a first electrode layer. The process also includes fabricating a magnetic device on the first electrode layer. The process further includes patterning the first electrode layer after fabricating the magnetic device. The process also includes depositing a first dielectric layer on the magnetic device and the first electrode layer after patterning the first electrode layer. The process further includes depositing a second electrode layer after depositing the first dielectric layer. The process also includes patterning the second electrode layer after depositing the second electrode layer.

According to another aspect of the disclosure, an electronic device includes a substrate. The electronic device also includes a first contact embedded in the substrate. The electronic device further includes a patterned first electrode on the substrate and coupled to the first contact. The electronic device also includes a patterned electronic device on the patterned first electrode. The electronic device further includes a patterned second electrode on the patterned electronic device. The electronic device also includes a trench contacting the patterned second electrode.

According to yet another aspect of the disclosure, an electronic device includes a substrate, and means for magnetically storing states. Each magnetic storing means is coupled between a first electrode and a second electrode. The electronic device further includes a dielectric substantially filling space between the first electrode, the second electrode, and adjacent magnetic storing means. The electronic device also includes means for coupling to the second electrode a surface of the magnetic storing means.

DETAILED DESCRIPTION

The processes disclosed below allow fabrication of electronic devices having reduced risk of electrical shorting that reduces process yield. For example, magnetic tunnel junctions may be fabricated by the processes in a magnetic random access memory. Electronic devices manufactured by the processes disclose may be employed in wireless networks.

FIG. 1is a block diagram showing an exemplary wireless communication system100in which an embodiment of the disclosure may be advantageously employed. For purposes of illustration,FIG. 1shows three remote units120,130, and150and two base stations140. It will be recognized that wireless communication systems may have many more remote units and base stations. Remote units120,130, and150include magnetic tunnel junction (MTJ) devices125A,125B and125C, as disclosed below. It will be recognized that any device containing a magnetic tunnel junction may also include semiconductor components having the disclosed features and/or components manufactured by the processes disclosed here, including the base stations, switching devices, and network equipment.FIG. 1shows forward link signals180from the base station140to the remote units120,130, and150and reverse link signals190from the remote units120,130, and150to base stations140.

InFIG. 1, the remote unit120is shown as a mobile telephone, the remote unit130is shown as a portable computer, and the remote unit150is shown as a fixed location remote unit in a wireless local loop system. For example, the remote units may be a device such as a music player, a video player, an entertainment unit, a navigation device, a communications device, a personal digital assistant (PDA), a fixed location data unit, and a computer. AlthoughFIG. 1illustrates remote units according to the teachings of the disclosure, the disclosure is not limited to these exemplary illustrated units. The disclosure may be suitably employed in any device which includes MTJ components, as described below. Although this is described for MTJ devices, the present disclosure also contemplates other electronic devices.

FIG. 2is a block diagram illustrating a design workstation used for circuit, layout, logic, wafer, die, and layer design of a semiconductor part as disclosed below. A design workstation200includes a hard disk201containing operating system software, support files, and design software such as Cadence or OrCAD. The design workstation200also includes a display to facilitate manufacturing of a semiconductor part210that may include a circuit, a semiconductor wafer, a semiconductor die, or layers contained within a semiconductor wafer or semiconductor die. A storage medium204is provided for tangibly storing the semiconductor part210. The semiconductor part210may be stored on the storage medium204in a file format such as GDSII or GERBER. The storage medium204may be a CD-ROM, DVD, hard disk, flash memory, or other appropriate device. Furthermore, the design workstation200includes a drive apparatus203for accepting input from or writing output to the storage medium204.

Data recorded on the storage medium204may specify logic circuit configurations, pattern data for photolithography masks, or mask pattern data for serial write tools such as electron beam lithography. The data may further include logic verification data such as timing diagrams or net circuits associated with logic simulations. Providing data on the storage medium204facilitates the design of the semiconductor part210by decreasing the number of processes for manufacturing circuits, semiconductor wafers, semiconductor dies, or layers contained within a semiconductor wafer or semiconductor die.

Examples of electronic devices with a top electrode and bottom electrode on opposing sides of the electronic device include, for example, magnetic tunnel junctions and giant magnetoresistive devices. Magnetic tunnel junctions (MTJs) are used in magnetic random access memory (MRAM) as data storage elements. In one embodiment, an MTJ includes a free layer, a tunnel barrier layer, and a fixed layer. The free layer magnetic moment may be parallel or anti-parallel to the fixed layer magnetic moment, to represent a “1” or a “0”. The magnetic moment of a ferromagnetic layer may be pinned with an anti-ferromagnetic layer (AFM). In another embodiment, multiple AFM layers are coupled to the free and the fixed layer.

FIG. 5is a flow chart illustrating an exemplary manufacturing process for an electronic device with top and bottom electrodes on a die and/or wafer according to one embodiment. At block505an electronic device is patterned using a first mask on a die and/or wafer. At block510a bottom electrode is patterned using a second mask on the die and/or wafer. At block515, a dielectric film is deposited to conformally coat the die and/or wafer including the electronic device and the bottom electrode. A large space exists between devices because no top electrode has been placed on the electronic device. Thus, the dielectric layer is able to substantially fill space between devices without leaving a void. The dielectric layer is etched back or chemical mechanical polished and planarized to a level similar to a top surface of the electronic device. That is, the top surface of the electronic device is exposed to allow contact with a top electrode.

At block520, a top electrode is deposited as a conformal conducting layer on the planarized dielectric. The top electrode is patterned to form individual top electrodes. In a two mask process, the top electrode may be patterned using the same mask previously employed to pattern the bottom electrode. In a three mask process, a third mask patterns the top electrode. In the event a bottom via is used, the bottom via mask may be reused to pattern the top and/or bottom electrode.

At block525, a second dielectric film is deposited and planarized. At block530, electrical paths are patterned into the second dielectric film. The electrical paths may be vias and/or trenches that allow contact with the top electrode. The electrical paths may be filled with a conducting material such as copper, aluminum, or an alloy.

Contacts to the top electrode manufactured according to this approach have a significantly reduced likelihood of shorting the electronic device. The inter-metal dielectric layer substantially fills the space between electronic devices leaving a small or no gap, which may be filled during electrical path formation. Thus, trenches may directly contact the top electrode without causing an electrical short of the electronic device.

Electronic devices manufactured according to this approach have a significantly reduced likelihood of shorting electrical paths. The inter-metal dielectric layer substantially fills the space between electronic devices leaving little or no gap. Thus, trenches may directly contact the top electrode without likelihood of trenches shorting to other trenches.

The flow chart illustrated inFIG. 5may be adapted for processing different electrical devices. Turning now to FIGS.6and7A-7H, an exemplary manufacturing process for magnetic tunnel junctions (MTJs) will be described.

FIG. 6is a flow chart illustrating an exemplary manufacturing process for a magnetic tunnel junction with top and bottom electrodes according to one embodiment.FIGS. 7A-7Hare cross-sectional views illustrating various states of an exemplary electronic device during the manufacturing process. The process disclosed may be applied to a single electronic device, a die having many electronic devices, or a wafer having multiple dies of electronic devices.

At block605, an MTJ is fabricated as illustrated inFIG. 7A. A die and/or wafer700has an inter-layer or inter-metal dielectric substrate702, which includes vias708and contacts706for coupling to a bottom electrode layer710. An isolation layer704separates the bottom electrode layer710from the inter-layer or inter-metal dielectric substrate702. A device layer720is stacked on the bottom electrode layer710. The device layer720may include multiple layers such as, for example multiple magnetic layers separated by an insulating layer. After deposition of the device layer720the device layer720may be annealed in a magnetic field to set a polarization of a fixed layer in the MTJ. An etch hard mask730is stacked on the device layer720and a photoresist732is patterned on the etch hard mask730. The pattern in the photoresist732is transferred into layers below the photoresist732stopping at the bottom electrode layer710to create MTJs721, as seen inFIG. 7B.

At block610, a first capping layer734is deposited as shown inFIG. 7B. For example, the first capping layer734may be silicon carbide (SiC) film or a silicon nitride (SiN) film, and may be deposited without breaking vacuum after the pattern transfer, to protect the MTJs721from damage during future processing. In one case, the first capping layer734prevents oxidation of magnetic materials in the MTJs721. An in-situ sputter process may clean the top and side surfaces of the MTJs721before the first capping layer734is deposited. For example, an Argon (Ar) sputter etch with a DC or an RF power supply bombards the MTJs721with Ar atoms, which physically remove contaminants from the surface of the MTJs721.

At block615the bottom electrode layer710and a first capping layer734are patterned, as seen inFIG. 7C. The patterned bottom electrode layer710forms discrete bottom electrodes711. In one embodiment these bottom electrodes711may be individually addressable. After patterning of the bottom electrodes711, a cleaning process cleans the wafer and remove any remaining photoresist materials and/or etch byproducts.

The bottom electrodes711are patterned earlier at a separate time during manufacturing than top electrodes (not yet shown). Patterning of the bottom electrodes711separate from the top electrode patterning reduces the aspect ratio for depositing dielectrics during manufacturing reducing the likelihood of gap formation and shorting of trenches (not yet shown).

At block620the first capping layer734is etched back to remove the capping layer from the top of the MTJs721. As seen inFIG. 7D, the first capping layer734remains on the sidewalls of the MTJs721after etch back in order to protect the sidewalls. According to one embodiment, the etch back is an oxygen free etch, preventing oxidation of metal materials in the MTJs721. If however, oxidation occurs on the top metal surface, an etch process may remove the oxidation. A second capping layer740is deposited in-situ over the die and/or wafer including over the MTJs721. The second capping layer740may be, for example, silicon nitride or silicon carbide. According to one embodiment, the second capping layer740is not the same material as the first capping layer734.

At block625, inter-metal dielectric layer processing occurs. A intermediate inter-metal dielectric layer742is deposited on the die and/or wafer, as seen inFIG. 7D. The intermediate inter-metal dielectric layer742is etched back and planarized, with for example a chemical mechanical polishing, as seen inFIG. 7E. According to one embodiment, planarization includes etching the intermediate inter-metal dielectric layer742and the second capping layer740to be substantially level with the MTJs721. In this case the top surface of the MTJs721are exposed for contact with a subsequent layer. In another embodiment, planarization only etches back the intermediate inter-metal dielectric layer742. A subsequent spin on organic material and etch back then exposes the top surface of the MTJs721. In yet another embodiment, an etch back process removes the first capping layer734and the second capping layer740from a portion of the side of the MTJs721depending upon location of the die and/or wafer to improve contact with the top electrode750.

A sputter clean, as described earlier, may clean the top surface of the MTJs721in either of the previously mentioned embodiments for planarization. Pre-sputter clean performed earlier in the process enlarges a process window by removing oxide from the MTJs721.

After the top surface is exposed, a top electrode layer750is deposited on the die and/or wafer, which couples to the MTJs721. The top electrode layer750is a conducting layer, such as tantalum, aluminum, or an alloy of metals. The top electrode layer750is flat after deposition because the intermediate inter-metal dielectric layer742below the top electrode layer750is also flat and lacks any voids.

As seen inFIG. 7F, at block630the top electrode layer750is patterned to form discrete top electrodes751. According to one embodiment, the mask for patterning the top electrodes751is the same mask that patterns the bottom electrodes711, resulting in electrodes of substantially similar size.

At block635, vias762and trenches764are fabricated to the top electrodes751.FIG. 7Gillustrates one embodiment of the electrical path. A top inter-metal dielectric layer760is deposited on the wafer and/or die. Planarization of the top inter-metal dielectric layer760obtains a substantially flat surface. In one embodiment, planarization employs chemical mechanical polishing processes.

After planarization, the top inter-metal dielectric layer760is patterned to form vias762and trenches764for connecting with the top electrodes751. After patterning the top inter-metal dielectric layer760, a sputter clean and/or wet clean removes remaining contaminants or polymers from a top surface of the top electrodes751.

The vias762and the trenches764are filled with a conducting material to create a top conductor. For example, copper (Cu) may be electroplated to fill the vias and trenches. The electrodeposited copper may be planarized using, for example, a chemical mechanical polishing process. After deposition of the conducting material a capping film (not shown) may be deposited on the wafer and/or die.

In another embodiment illustrated inFIG. 7H, no via is patterned in the top inter-metal dielectric layer760. Instead, the trenches764exposes contact to the top electrodes751. In this embodiment, after etch of the trenches764a sputter clean and/or a wet etch removes polymer residue from the top electrodes751.

During processing of the electronic devices as described above, the top electrode is etched in a separate process than etching of the bottom electrode. Using the exemplary manufacturing process described above reduces the likelihood of voids forming between electronic devices. As a result, process yield is improved because the risk of shorting trenches is reduced or eliminated.

Not only does the exemplary manufacturing process for arrays of electronic devices, such as MTJs, disclosed above reduce void filling issues that short electrical paths to the MTJs, but the process also results in a flat top electrode surface, improving contact with the top electrode. The bottom electrode is etched in a separate process from the top electrode, although the same mask may pattern both the top and bottom electrodes.