Mixing restartable and non-restartable requests with performance enhancements

A computer-implemented method includes setting a respective flag in a first buffer of a hardware accelerator. The first buffer includes the respective flag of the first buffer, and a second buffer of the hardware accelerator includes a respective flag of the second buffer. A hardware state of the hardware accelerator is maintained in the first buffer, based on the respective flag of the first buffer being set. A first request directed to the hardware accelerator is received. It is determined that that the first buffer has the respective flag set. The first request is passed to the hardware accelerator, where passing the first request includes passing to the hardware accelerator a pointer to the first buffer, based on the first buffer having the respective flag set.

BACKGROUND

The present invention relates to hardware accelerators and, more specifically, to mixing restartable and non-restartable requests with performance enhancements.

Hardware acceleration is the performance of certain functions in hardware, such that those functions may potentially be performed more efficiently than they might be if performed in software, or so as to enable the software to focus on other functionality. The hardware used in hardware acceleration may be integrated with a central processing unit (CPU) of a host machine, or that hardware may be a separate device known as a hardware accelerator.

Generally, a hardware accelerator is connected to the CPU, such as through an input/output adapter. Software on the host machine uses a hardware accelerator through one or more libraries, each of which utilize a common interface, through which the software can communicate with a device driver of the hardware accelerator. In other words, the library communicates with the device driver, which communicates with the hardware accelerator. Requests can be executed on the hardware accelerator through the interface. In some cases, however, a request will need to be restarted, potentially on a different hardware accelerator. This may be the case, for example, if the hardware accelerator initially executing the request fails during the execution.

To enable restarts of requests, the interface provides for an input buffer and an output buffer, also referred to respectively as an input state area and an output state area, which are managed by the device driver. Generally, the input buffer and the output buffer are used to maintain input states and output states of the hardware accelerator. To enable restartable requests, the input state existing at the beginning of execution of the request needs to be maintained in the input buffer while a request is being executed by the hardware accelerator. To this end, for instance, the device driver copies the input state from the input buffer to a secondary buffer, and the device driver processes the request using the secondary buffer. The result of the request is written to the output buffer. This maintains the input state in pristine condition in the input buffer. Thus, if the accelerator fails while processing the request, the request can be restarted with its original input state.

Because the output buffer contains the current state of the hardware accelerator after execution of a request, the library will instruct the device driver to swap the input buffer and the output buffer at the conclusion of the request. For instance, a pointer indicating the input buffer can be updated to reference the output buffer, and a pointer indicating the output buffer can be updated to reference the input buffer. As a result, the output buffer becomes the input buffer for the next request received. The acts of writing to the current state to the output buffer and then swapping the input and output buffers occurs at the conclusion of each successful request.

SUMMARY

Embodiments of the present invention are directed to a computer-implemented method for executing requests on a hardware accelerator. A non-limiting example of the computer-implemented method includes setting a respective flag in a first buffer of a hardware accelerator. The first buffer includes the respective flag of the first buffer, and a second buffer of the hardware accelerator includes a respective flag of the second buffer. A hardware state of the hardware accelerator is maintained in the first buffer, based on the respective flag of the first buffer being set. A first request directed to the hardware accelerator is received. It is determined that that the first buffer has the respective flag set. The first request is passed to the hardware accelerator, where passing the first request includes passing to the hardware accelerator a pointer to the first buffer, based on the first buffer having the respective flag set.

Embodiments of the present invention are directed to a system for executing requests on a hardware accelerator. A non-limiting example of the system includes a memory having computer-readable instructions and one or more processors for executing the computer-readable instructions. The computer-readable instructions include instructions for setting a respective flag in a first buffer of a hardware accelerator. The first buffer includes the respective flag of the first buffer, and a second buffer of the hardware accelerator includes a respective flag of the second buffer. Further according to the computer-readable instructions, a hardware state of the hardware accelerator is maintained in the first buffer, based on the respective flag of the first buffer being set. A first request directed to the hardware accelerator is received. It is determined that that the first buffer has the respective flag set. The first request is passed to the hardware accelerator, where passing the first request includes passing to the hardware accelerator a pointer to the first buffer, based on the first buffer having the respective flag set.

Embodiments of the invention are directed to a computer-program product for executing requests on a hardware accelerator, the computer-program product including a computer-readable storage medium having program instructions embodied therewith. The program instructions are executable by a processor to cause the processor to perform a method. A non-limiting example of the method includes setting a respective flag in a first buffer of a hardware accelerator. The first buffer includes the respective flag of the first buffer, and a second buffer of the hardware accelerator includes a respective flag of the second buffer. Further according to the method performed by the processor, a hardware state of the hardware accelerator is maintained in the first buffer, based on the respective flag of the first buffer being set. A first request directed to the hardware accelerator is received. It is determined that that the first buffer has the respective flag set. The first request is passed to the hardware accelerator, where passing the first request includes passing to the hardware accelerator a pointer to the first buffer, based on the first buffer having the respective flag set.

In the accompanying figures and following detailed description of the disclosed embodiments, the various elements illustrated in the figures are provided with two- or three-digit reference numbers. With minor exceptions, the leftmost digit(s) of each reference number correspond to the figure in which its element is first illustrated.

DETAILED DESCRIPTION

Turning now to an overview of technologies that are more specifically relevant to aspects of the invention, as accelerator technology improves, there is no longer a requirement to swap the input and output buffers from one request to the next. Rather, while a new hardware accelerator may not necessarily support restartable requests, it may be capable of executing requests in place. Writing the complete output state to the output buffer can be an expensive process, because the full output state may be quite large. Thus, for a newer accelerator only a single buffer may be required, and the output state need not be written in full into an output buffer. Further, a new accelerator is likely to be more closely connected to the CPU, resulting in reduced latency and increased throughput. It is desirable to leverage these features.

Turning now to an overview of the aspects of the invention, one or more embodiments of the invention address the above-described shortcomings of the prior art by providing a mechanism to mark, or flag, one of the input and output buffers to indicate that the buffer includes the hardware state. However, the software state may continue to switch back and forth between the two buffers. In some embodiments of the invention, the device driver is able to recognize, based on the flag, which buffer maintains the hardware state and can therefore pass the hardware state to the accelerator, regardless of which buffer is currently acting as the input buffer for maintaining the present software state.

The above-described aspects of the invention address the shortcomings of the prior art by enabling hardware accelerators to process data in place when they are capable of doing so while maintaining backward compatibility with libraries that switch the input and output buffers between requests. By keeping the hardware state in a single buffer, latency can be significantly reduced, as the hardware state tends to be significantly larger than the software state. Further, device drivers of older accelerators can continue to behave as usual, by writing the software state to the output buffer and then swapping the input buffer and the output buffer after executing a request.

Turning now to a more detailed description of aspects of the present invention,FIG. 1is a diagram of a request system100according to some embodiments of the invention. As shown inFIG. 1, the request system100may include and be associated with a hardware accelerator110, which may be installed on, or otherwise integrated with, a host machine. Although not shown inFIG. 1, to take advantage of various features of embodiments of the invention, the host machine may include at least two hardware accelerators110, thereby enabling a request to be restarted on a second hardware accelerator110after a first hardware accelerator110fails. However, for the hardware accelerator110to operate as intended, it is not required that additional hardware accelerators110be present on the host machine.

Each hardware accelerator110may have an associated a device driver130, with which software can communicate via an interface140, implemented by one or more software libraries150. The interface140enables access to a first buffer160and a second buffer160, each of which is capable of maintaining a state of the hardware accelerator110. More specifically, in some embodiments of the invention, each buffer160may include reserved space for a flag170, a software state180, and a hardware state190of the hardware accelerator110. Alternatively, however, only one buffer160may include a reserved space for the hardware state190, while the other buffer160includes space only for the flag170and the software state180. In either case, however, both buffers160may include reserved space for the flag170and the software state180.

Each library150used to access the hardware accelerator may be a new library150or a legacy library150. Generally, after executing a request, a legacy library150takes the current output buffer160and then switches the input buffer160and the output buffer160, while a new library150need not switch the input buffer160and the output buffer160. In some embodiments of the invention, the request system100supports both of these library types.

Generally, embodiments of the invention leverage the capabilities of a hardware accelerator110that is more closely connected to the CPU than are older hardware accelerators110. As a result, latency can be reduced, and throughput can be increased. Thus, for such a hardware accelerator110it is desirable to optimize requests on the hardware accelerator110in order to take advantage of these features. However, conventionally, by writing the full output state to the current output buffer160at the conclusion of each request, latency is unnecessarily increased for new hardware accelerators110. In some embodiments of the invention, a hardware accelerator110is able to process data in place and thus does not need a distinct input buffer160and output buffer160. However, legacy libraries150exist that will expect these two buffers160and will automatically swap them after a request. Thus, embodiments of the invention are backward compatible with such legacy libraries150while also supporting new libraries150that do not swap the input buffer160and the output buffer160but, rather, use only a single buffer160.

To this end, as mentioned above, each buffer160may include space for a software state180, a flag170, and a hardware state190, but only a single of these buffers160actually maintains the current hardware state190. Generally, the hardware state190may be much larger than the software state180, and the flag170may be implemented by a single bit. In this disclosure, the portion of a buffer160reserved for the hardware state190is referred to as an extended buffer, while the portion of the buffer160reserved for the software state180is referred to as the standard buffer160. In some embodiments of the invention, the software state180and the flag170are incorporated into the buffer160as a header, while the hardware state190takes up the remainder of the buffer160. However, it will be understood that various implementations are available.

Generally, the software state180is a current state of software associated with the hardware accelerator110, while the hardware state190is a current state of the hardware of the hardware accelerator110. Typically, the hardware state190is significantly larger than the software state180. In some embodiments of the invention, it is unnecessary for both the buffers160to maintain this large hardware state190. Rather, in some embodiments of the invention, the flag170indicates which buffer160maintains the actual hardware state190. In some embodiments of the invention, the buffer160that does not include hardware state190may instead include blanked data, such as a series of zeroes.

The library150that uses the hardware accelerator110may initialize the buffers160before executing the first request to the device driver130. For instance, this may be performed at the instruction of an initialization function implemented by a new library150. To this end, the device driver130may set all bits in each buffer160to zero on the first call. The device driver130may then flag one of such buffers160as maintaining the hardware state190. More specifically, the device driver130may set the flag170by changing the flag bit from0to1. This flagged buffer160may thus be the only buffer160that maintains the hardware state190of the hardware accelerator110.

A newer hardware accelerator110need not utilize both an input buffer160and an output buffer and may, instead, be capable of performing computations in place. Thus, a new library150, potentially developed with knowledge of the capabilities of such a new hardware accelerator, need not swap the input buffer160and the output buffer160after performing a request on the hardware accelerator110. In some embodiments of the invention, when a new library150is utilized to run a request on the hardware accelerator110, the device driver130passes to the hardware accelerator110the software state180written in the current input buffer160and a pointer to the hardware state190in the flagged buffer160, which does not move. While the request is executed, the input buffer160is updated, and at the conclusion of the request, the input buffer160may still include the current software state180. After the request is executed, in some embodiments of the invention, the new library therefore does not swap the input buffer160and the output buffer160. Thus, the current input buffer160may remain the input buffer160for the next request. As a result, the hardware accelerator110may operate with reduced latency, because the large hardware state190need not be copied by being written to the current output buffer160.

In some embodiments of the invention, when the device driver130receives control again, the device driver130knows which buffer160is the current input buffer160. Further, the device driver130may determine which buffer160has its flag170set and, therefore, may determine the location of the hardware state190. Because legacy libraries150still swap the input and output buffers160, the hardware state190is not necessarily stored in the current input buffer160. The next time a request is received by way of a library, the device driver130is able to pass the hardware accelerator110the correct software state180, in the current input buffer160, and the correct hardware state190, in the flagged buffer160.

Each legacy library150may continue to swap the input buffer160and the output buffer160after a request is performed. Further, in some embodiments of the invention, a legacy library150need not be concerned with, or even aware of, the existence of the flag170and the hardware state190. Rather, upon completing a request, the device driver130may write to the current output buffer160, specifically, to the software state180of the current output buffer160, while leaving the flag170and the hardware state190untouched. The legacy library150may then switch the input buffer160and the output buffer160.

Thus, when the device driver130receives control again, the device driver130has access to the current input buffer160as well as the current output buffer160. The device driver130may check whether the input buffer160, as indicated by the library150after the switch, has the flag set. If the flag is set, then the device driver130knows that the current input buffer160maintains the hardware state190in addition to the software state180. However, if the flag is not set in the input buffer160, then the device driver130knows that the current output buffer160maintains the hardware state190. As discussed above, after initialization, the placement of the hardware state does not change, according to some embodiments of the invention.

FIG. 2is a flow diagram of an example method200of managing both restartable and non-restartable requests through the request system100, according to some embodiments of the invention. According to some embodiments of the invention, this method200enables a hardware accelerator110to receive requests via libraries150that expect processing to be performed in place, without swapping the input buffer160and the output buffer160, as well as via libraries150that expect to swap the input buffer160and the output buffer160. As a result, restartable requests are supported through the use of two distinct buffers160, and performance is improved through leveraging the capabilities of a hardware accelerator110that does not require the swap to occur.

As shown inFIG. 2, at block205, upon receiving a first request, the device driver130initializes the buffers160associated with the hardware accelerator110. To this end, for instance, the device driver130can check whether the flag170is set in either the current input buffer160or the current output buffer160. If no flag170is set in either buffer160, then the device driver130may set the various bits in both buffers160to zeroes, thus blanking the buffers160. Additionally, the device driver130may set the flag170in the input buffer160to a value of 1. At the conclusion of the request, after the input buffer160has been updated with an output state, including both an output software state180and an output hardware state190, a subset of the input buffer160may be copied to the output buffer160. More specifically, for instance, this subset may include the software state180, while excluding the flag170and the hardware state190. Thus, after this first request, the input buffer160may have a set flag170and may include both the software state180and the hardware state190, while the output buffer160has its flag170unset and includes the software state180but blanked data in place of the hardware state190. Although the input buffer160is flagged in the above example, and thus maintains the hardware state190, one of skill in the art will understand that the output buffer160could be flagged alternatively. In some embodiments of the invention, a new library150provides an initialization method, or the like, to instruct the device driver130to perform these initialization tasks upon receipt of its first request.

At block210, after initialization, another request is issued to the hardware accelerator110and received at the device driver130. If the request is made through a new library150, then the method200may proceed to block215. However, if the request is made through a legacy library150, then the method200may proceed block235. It will be understood that the device driver130need not detect whether the library150being used is a legacy library150or a new library150. Rather, depending on the library type, one of these paths will be utilized, according to some embodiments of the invention.

At block215, when the request has been issued to the hardware accelerator110through a new library150, the device driver130determines which buffer160has its flag170set. At block220, the device driver130adjusts a pointer to the hardware state190to point to the hardware state190in the buffer160with the set flag170. This may be the input buffer160or the output buffer160, because the buffers160may switch from time to time. At block225, the device driver130passes the request to the hardware accelerator110for processing. At block230, while completing the request, the hardware accelerator110writes the resulting software state180back to the input buffer160. As such, in some embodiments of the invention, the input buffer160maintains the current software state180, and the flagged buffer160maintains the current hardware state190. The method200may then return to block210, where additional requests are received.

At block235, when a new request has been issued to the hardware accelerator110through a legacy library150, the device driver130determines which buffer160has its flag170set. At block240, the device driver130adjusts a pointer to the hardware state190to point to the hardware state190in the buffer160with the set flag170. At block245, the device driver130passes the new request to the hardware accelerator110for processing. At block250, while completing the request, at the instruction of the legacy library150, the device driver130writes the output state to the current output buffer160. More specifically, in some embodiments of the invention, this output state includes the software state180and does not include a flag170or the hardware state190, as the legacy library150is unconcerned with the hardware state190. Thus, at this point, the output buffer160may have the current software state180, and the flagged buffer160may maintain the current hardware state190. At block255, at the instruction of the legacy library150, the device driver130swaps the input buffer160and the output buffer160. Therefore, in some embodiments of the invention, the new input buffer160maintain the current software state180, and the flagged buffer160maintains the current hardware state190. The method200may then return to block210, where additional requests are received.

It will be understood that, regardless of which library150is used to make a request, at the conclusion of processing the request, the input buffer160maintains the software state180and the flagged buffer160maintains the hardware state190. Further, it will be understood that, regardless of whether the next request arrives through a legacy library150or a new library150, the current input buffer160may be used to provide the software state180, and the flagged buffer160may be used to provide the hardware state190. Thus, regardless of which library150is used, the hardware accelerator110will operate as intended. This enables a newer hardware accelerator110to be used effectively by taking advantage of reduced latency and thus improved performance, while also maintaining backward compatibility, including the support for restartable requests.

FIG. 3is a block diagram of a computer system300for implementing some or all aspects of the request system100, according to some embodiments of this invention. The request systems100and methods described herein may be implemented in hardware, software (e.g., firmware), or a combination thereof. In some embodiments, the methods described may be implemented, at least in part, in hardware and may be part of the microprocessor of a special or general-purpose computer system300, such as a personal computer, workstation, minicomputer, or mainframe computer. For example, and not by way of limitation, the hardware accelerator110may be integrated with, or installed in, a computer system300, which acts as its host machine.

In some embodiments, as shown inFIG. 3, the computer system300includes a processor305, memory310coupled to a memory controller315, and one or more input devices345and/or output devices340, such as peripherals, that are communicatively coupled via a local I/O controller335. These devices340and345may include, for example, a printer, a scanner, a microphone, and the like. Input devices such as a conventional keyboard350and mouse355may be coupled to the I/O controller335. The I/O controller335may be, for example, one or more buses or other wired or wireless connections, as are known in the art. The I/O controller335may have additional elements, which are omitted for simplicity, such as controllers, buffers (caches), drivers, repeaters, and receivers, to enable communications.

The processor305is a hardware device for executing hardware instructions or software, particularly those stored in memory310. The processor305may be a custom made or commercially available processor, a CPU, an auxiliary processor among several processors associated with the computer system300, a semiconductor-based microprocessor (in the form of a microchip or chip set), a macroprocessor, or other device for executing instructions. The processor305includes a cache370, which may include, but is not limited to, an instruction cache to speed up executable instruction fetch, a data cache to speed up data fetch and store, and a translation lookaside buffer (TLB) used to speed up virtual-to-physical address translation for both executable instructions and data. The cache370may be organized as a hierarchy of more cache levels (L1, L2, etc.).

The memory310may include one or combinations of volatile memory elements (e.g., random access memory, RAM, such as DRAM, SRAM, SDRAM, etc.) and nonvolatile memory elements (e.g., ROM, erasable programmable read only memory (EPROM), electronically erasable programmable read only memory (EEPROM), programmable read only memory (PROM), tape, compact disc read only memory (CD-ROM), disk, diskette, cartridge, cassette or the like, etc.). Moreover, the memory310may incorporate electronic, magnetic, optical, or other types of storage media. Note that the memory310may have a distributed architecture, where various components are situated remote from one another but may be accessed by the processor305.

The instructions in memory310may include one or more separate programs, each of which comprises an ordered listing of executable instructions for implementing logical functions. In the example ofFIG. 3, the instructions in the memory310include a suitable operating system (OS)311. The operating system311essentially may control the execution of other computer programs and provides scheduling, input-output control, file and data management, memory management, and communication control and related services.

Additional data, including, for example, instructions for the processor305or other retrievable information, may be stored in storage320, which may be a storage device such as a hard disk drive or solid-state drive. The stored instructions in memory310or in storage320may include those enabling the processor to execute one or more aspects of the request systems100and methods of this disclosure.

The computer system300may further include a display controller325coupled to a display330. In some embodiments, the computer system300may further include a network interface140for coupling to a network365. The network365may be an IP-based network for communication between the computer system300and an external server, client and the like via a broadband connection. The network365transmits and receives data between the computer system300and external systems. In some embodiments, the network365may be a managed IP network administered by a service provider. The network365may be implemented in a wireless fashion, e.g., using wireless protocols and technologies, such as WiFi, WiMax, etc. The network365may also be a packet-switched network such as a local area network, wide area network, metropolitan area network, the Internet, or other similar type of network environment. The network365may be a fixed wireless network, a wireless local area network (LAN), a wireless wide area network (WAN) a personal area network (PAN), a virtual private network (VPN), intranet or other suitable network system and may include equipment for receiving and transmitting signals.

Request systems100and methods according to this disclosure may be embodied, in whole or in part, in computer program products or in computer systems300, such as that illustrated inFIG. 3.