SEMICONDUCTOR DEVICE, SEMICONDUCTOR MODULE, AND ELECTRONIC APPARATUS

A semiconductor device (1) includes an insulated-gate field-effect transistor (2) that includes: a channel layer (21); a pair of main electrodes (24(s), 24(D)) spaced from each other and provided on the channel layer; a barrier layer (22) provided on the channel layer between the pair of main electrodes and including a recessed region (22A) that goes through the barrier layer in a thickness direction; a gate insulating film (25A, 25B) provided on the channel layer in the recessed region and having two or more kinds of thicknesses; and a gate electrode (26) provided on the channel layer through the gate insulating film.

TECHNICAL FIELD

The present disclosure relates to a semiconductor device, a semiconductor module, and an electronic apparatus.

BACKGROUND ART

GaN has been used as a wide-gap semiconductor material. A device manufactured with GaN has characteristics of being high in dielectric breakdown voltage, allowing for high-temperature operation, being high in saturated drift velocity, etc. Furthermore, a two-dimensional electron gas (2DEG) produced at a GaN-based heterojunction has characteristics of being high in mobility and high in sheet electron density.

These characteristics enable a GaN-based hetero FET (HFET) to be of low resistance and allow for high-speed operation and high-voltage operation. Thus, its application to power devices, radio-frequency (RF) devices, etc. has been expected.

In terms of reduction of leakage current and a fail-safe at the time of operation of an integrated circuit, normally-off operation is generally desirable. Thus, there has been used a technique to realize the normally-off operation by means of a cascode circuit or a technique to realize the normally-off operation by means of an FET alone.

PTL 1 described below discloses a semiconductor device including an FET having a MIS gate structure that realizes the normally-off operation. In this FET, a barrier layer on a channel layer is provided with a groove that goes through this barrier layer, and a gate electrode is disposed in the groove through a gate insulating film.

CITATION LIST

Patent Literature

SUMMARY OF INVENTION

In the FET disclosed in PTL 1 described above, inside the groove of the barrier layer, the gate insulating film having a uniform thickness is formed on the channel layer. To raise a drain current at the time of on operation of the FET, it is preferable that the thickness of the gate insulating film be thin. Meanwhile, if the thickness of the gate insulating film becomes thin, the strength of an electric field applied from the gate electrode to the gate insulating film becomes high, which is likely to cause a breakdown of the gate insulating film. That is, current characteristics and the breakdown voltage are in a trade-off relationship to the film thickness of the gate insulating film.

Thus, improving the current characteristics and the breakdown voltage is desired.

The present technology provides a semiconductor device, a semiconductor module, and an electronic apparatus that make it possible to improve the current characteristics and the breakdown voltage.

A semiconductor device according to a first aspect of the present disclosure includes an insulated-gate field-effect transistor that includes: a channel layer: a pair of main electrodes spaced from each other and provided on the channel layer: a barrier layer provided on the channel layer between the pair of main electrodes and including a recessed region that goes through the barrier layer in a thickness direction: a gate insulating film provided on the channel layer in the recessed region and having two or more kinds of thicknesses; and a gate electrode provided on the channel layer through the gate insulating film.

A semiconductor module according to a second aspect of the present disclosure includes a semiconductor device including an insulated-gate field-effect transistor, the insulated-gate field-effect transistor including: a channel layer: a pair of main electrodes spaced from each other and provided on the channel layer: a barrier layer provided on the channel layer between the pair of main electrodes and including a recessed region that goes through the barrier layer in a thickness direction: a gate insulating film provided on the channel layer in the recessed region and having two or more kinds of thicknesses; and a gate electrode provided on the channel layer through the gate insulating film.

An electronic apparatus according to a third aspect of the present disclosure includes a semiconductor device including an insulated-gate field-effect transistor, the insulated-gate field-effect transistor including: a channel layer: a pair of main electrodes spaced from each other and provided on the channel layer: a barrier layer provided on the channel layer between the pair of main electrodes and including a recessed region that goes through the barrier layer in a thickness direction; a gate insulating film provided on the channel layer in the recessed region and having two or more kinds of thicknesses; and a gate electrode provided on the channel layer through the gate insulating film.

MODES FOR CARRYING OUT THE INVENTION

With reference to the drawings, some embodiments of the present disclosure will be described in detail below. It is to be noted that the description will be given in the following order.1. First EmbodimentA first embodiment is a first example where the present technology is applied to a semiconductor device including an insulated-gate field-effect transistor. Here is described a vertical cross-section structure, a planar structure, a manufacturing method, and current-voltage characteristics of the insulated-gate field-effect transistor.2. Second EmbodimentA second embodiment is a second example where in the semiconductor device according to the first embodiment, the gate structure of the insulated-gate field-effect transistor is modified.3. Third EmbodimentA third embodiment is a third example where in the semiconductor device according to the first embodiment, the structure of a gate insulating film of the insulated-gate field-effect transistor is modified.4. Fourth EmbodimentA fourth embodiment is a fourth example where in the semiconductor device according to the first embodiment, the structure of the gate insulating film of the insulated-gate field-effect transistor is further modified.5. Fifth EmbodimentA fifth embodiment is a fifth example that describes an insulated-gate field-effect transistor of a depression structure that is able to be equipped in the semiconductor devices according to the first to fourth embodiments.6. Sixth EmbodimentA sixth embodiment is a sixth example that describes a semiconductor module mounted with the semiconductor device according to the first to fifth embodiments.7. Seventh EmbodimentA seventh embodiment is a seventh example that describes an electronic apparatus mounted with the semiconductor device according to the first to fifth embodiments.8. Other Embodiments

1. First Embodiment

A semiconductor device1according to the first embodiment of the present disclosure is described withFIGS.1to9.

Here, in the drawings, when appropriate, a direction of arrow X illustrated indicates a direction of one plane surface of the semiconductor device1conveniently set on the plane. A direction of arrow Y indicates a direction of another one plane surface perpendicular to the direction of arrow X. Furthermore, a direction of arrow Z indicates an upward direction perpendicular to the direction of arrow X and the direction of arrow Y. That is, the direction of arrow X, the direction of arrow Y, and the direction of arrow Z just coincide with an X-axis direction, a Y-axis direction, and a Z-axis direction of a three-dimensional coordinate system, respectively.

It is to be noted that these respective directions are illustrated to help understanding of the description, and do not limit the direction of the present technology.

FIG.1illustrates a vertical cross-section structure of a main part of the semiconductor device1according to the first embodiment of the present disclosure.FIG.2illustrates a planar structure of the main part of the semiconductor device1illustrated inFIG.1. It is to be noted thatFIG.1illustrates the vertical cross-section structure along a section line A-A illustrated inFIG.2.

As illustrated inFIGS.1and2, the semiconductor device1according to the first embodiment includes a substrate10as a base. An insulated-gate field-effect transistor (IGFET) (hereinafter, referred to simply as “transistor”)2is provided on the substrate10(here, in the direction of arrow Z) through a buffer layer11. The transistor2includes at least a metal-insulator-semiconductor field-effect transistor (MISFET).

The transistor2includes, within a region surrounded by an isolation region4, a channel layer21, a barrier layer22, a two-dimensional electron gas (2DEG)23, a pair of main electrodes24, a gate insulating film25, and a gate electrode26as main components. The two-dimensional electron gas23is produced by polarization at a heterojunction interface between the channel layer21and the barrier layer22. This transistor2is a high electron mobility transistor (HEMT).

Furthermore, although its structure will be described later, the transistor2is of a depression type (an enhancement type), and normally-off operation is realized.

(2) Configuration of Substrate10

The substrate10includes a semiconductor material. For example, a III-V compound semiconductor material is used in the substrate10, and more specifically, a semi-insulating single-crystal GaN substrate is used.

Furthermore, here, the buffer layer11is used, thus, a lattice constant is able to be controlled by means of the buffer layer11. Therefore, it is possible to use the substrate10having a lattice constant different from a lattice constant of the channel layer21. For example, a SiC substrate, a sapphire substrate, a Si substrate, or the like is able to be used as the substrate10.

(3) Configuration of Buffer Layer11

The buffer layer11is provided on the substrate10, and includes a compound semiconductor layer. For example, an epitaxial growth method is used to form the buffer layer11.

As described above, in a case where the substrate10and the channel layer21differ in the lattice constant, the lattice constant is controllable in the buffer layer11. Thus, the crystalline state of the channel layer21is able to be kept in a good state by the buffer layer11. In addition, a warp of the substrate10(in a manufacturing process, a warp of a wafer) is able to be controlled by the buffer layer11.

For example, in a case where single-crystal Si is used in the substrate10, and GaN is used in the channel layer21, AlN, AlGaN, GaN, or the like is able to be used in the buffer layer11.

It is to be noted that the buffer layer11is not limited to a single layer, and, for example, may include a multi-layered film in which two or more semiconductor materials selected from above-described AlN, AlGaN, and GaN are stacked in layers. Furthermore, in a case where it is formed using a ternary semiconductor material, the composition of the buffer layer11may be gradually changed in a stacking direction (the direction of arrow Z).

(4) Configuration of Channel Layer21

The channel layer21is provided on the buffer layer11, and includes a compound semiconductor layer. The channel layer21is a region in which carriers are accumulated through the polarization with the barrier layer22. The channel layer21includes, for example, GaN. For example, the epitaxial growth method is used to form the channel layer21. Here, undoped GaN with no impurity added is used in the channel layer21. The channel layer21has no added impurity, which makes it possible to suppress the scattering of carriers caused by an impurity in the channel layer21. As a result, it is possible to achieve the high mobility of carriers.

It is to be noted that a back barrier layer may be provided between the buffer layer11and the channel layer21. The back barrier layer includes a compound semiconductor material that raises a back-barrier-layer-side energy band in the channel layer21. For example, Al1-x-yGaxInyN (0≤ x<1, 0≤ y<1) or undoped Al1-x-yGaxInyN is able to be practically used as the back barrier layer. The back barrier layer is able to be formed, for example, by use of the epitaxial growth method.

By providing the back barrier layer, it becomes possible to effectively suppress the short channel effect of the transistor2.

(5) Configuration of Barrier Layer22

The barrier layer22is provided, between the pair of main electrodes24, on the channel layer21. The barrier layer22includes a compound semiconductor material, and is formed by use of the epitaxial growth method. The barrier layer22causes carriers to be accumulated in the channel layer21through the polarization with the channel layer21to produce a two-dimensional electron gas. For example, Al1-x-yGaxInyN (0≤ x<1, 0≤ y<1) is able to be used in the barrier layer22. The barrier layer22is formed to have a thickness of, for example, 5 nm or more and 30 nm or less.

Furthermore, the barrier layer22may include undoped Al1-x-yGaxInyN (0≤ x<1, 0≤ y<1) with no impurity added. In this case, it is possible to effectively suppress the scattering of carriers caused by an impurity in the channel layer21. As a result, it is possible to achieve the high mobility of carriers of the transistor2.

Moreover, the barrier layer22is not limited to a single layer, and, for example, may be a multi-layered film of above-described Al1-x-yGaxInyN (0≤ x<1, 0≤ y<1) whose composition is changed with each layer. Furthermore, the composition of the barrier layer22may be gradually changed in the stacking direction.

It is to be noted that a spacer layer may be provided between the channel layer21and the barrier layer22. The spacer layer is able to be formed, for example, using a single layer of Al1-xGaxN (0≤ x<1) or a multi-layered film of Al1-xGaxN whose composition is changed with each layer. The spacer layer is formed to have a thickness of, for example, 0.5 nm or more and 2 nm or less.

By providing the spacer layer, it becomes possible to effectively suppress the scattering of carriers caused by an impurity in the channel layer21. As a result, it is possible to achieve the high mobility of carriers of the transistor2.

Between the pair of main electrodes24, the barrier layer22is provided with a recessed region22A. The recessed region22A is a gate opening formed to go through the barrier layer22in a thickness direction (the direction of arrow Z). The recessed region22A is provided, between the pair of main electrodes24and in an intermediate part in a gate length direction, throughout the entire area in a gate width direction. The gate length direction here is a direction coincident with the direction of arrow X. Furthermore, the gate width direction is a direction coincident with the direction of arrow Y. In the gate length direction, an end of the recessed region22A (a gate opening end) is spaced from the main electrode24.

Although a method of manufacturing the semiconductor device1will be described later, the recessed region22A is formed in the barrier layer22by use of a photolithographic technique and an etching technique. As the etching technique, there is used wet etching using chemical liquid that allows a high degree of etch selectivity of the channel layer21and the barrier layer22. In addition, the etching amount is highly accurately controlled by the adoption of wet etching. That is, with respect to the channel layer21, only the barrier layer22is selectively removed, and the recessed region22A is formed.

A surface of the channel layer21within the recessed region22A configured in this way is substantially over-etched. Thus, it is possible to match the position of the surface of the channel layer21within the recessed region22A with the position of an interface between the channel layer21and the barrier layer22. The position of the surface of the channel layer21within the recessed region22A is the height position of an interface between the channel layer21and the gate insulating film25in the direction of arrow Z.

Here, if the above-described spacer layer is left within the recessed region22A, it is possible to raise an on-state current of the transistor2. Conversely, if the spacer layer is completely removed, it is possible to reduce an off-state current of the transistor2.

It is to be noted that in the first embodiment, within the recessed region22A, the surface of the channel layer21may be partially etched.

(6) Configuration of Main Electrodes24

The pair of main electrodes24is configured as an ohmic electrode. One of the pair of main electrodes24is coupled to one end of the two-dimensional electron gas23in the gate length direction with low resistance, and is used, for example, as a source electrode. Conveniently, the source electrode is assigned a reference numeral of the main electrode24with code (S) added to the end thereof. The other one of the pair of main electrodes24is coupled to the other end of the two-dimensional electron gas23in the gate length direction with low resistance, and is used, for example, as a drain electrode. Likewise, the drain electrode is assigned the reference numeral of the main electrode24with code (D) added to the end thereof.

The main electrode24here is provided on the channel layer21through the barrier layer22. The main electrode24includes, for example, a multi-layered film in which Ti, Al, Ni, and Au are stacked in layers in this order upward from a surface of the barrier layer22.

Furthermore, a contact region may be provided between the main electrode24and the two-dimensional electron gas23. In the contact region, the main electrode24and the two-dimensional electron gas23are able to be coupled with low resistance. As the contact region, for example, a high-concentration n-type semiconductor region is able to be used. The contact region is able to be formed from the main electrode24to near the two-dimensional electron gas23or up to the two-dimensional electron gas23, or to be deeper than the two-dimensional electron gas23.

The contact region is able to be formed, for example, by partially removing the barrier layer22and the channel layer21by etching and causing a semiconductor layer to grow in a removed portion by use of a selective regrowth method. In this case, as the semiconductor layer to be regrown, n-type In1-xGaxN (0≤ x<1) is able to be used.

Furthermore, the contact region may be formed by implantation of an n-type impurity using an ion implantation method.

(7) Configuration of Gate Insulating Film25

In the first embodiment, the gate insulating film25includes a first insulating film25A and a second insulating film25B having a different thickness from the first insulating film25A.

The second insulating film25B is provided on the channel layer21, on the barrier layer22, and on the pair of main electrodes24to cover these. The second insulating film25B is formed using an insulating material that has insulation performance on the channel layer21and the barrier layer22and protects the surfaces of the channel layer21and the barrier layer22from an impurity such as ions. In addition, the second insulating film25B is formed using an insulating material that keeps respective interfaces with the channel layer21and the barrier layer22in a good state and keeps a device property of the transistor2in a good condition.

The second insulating film25B includes, for example, a single-layer film of at least one selected from Al2O3, HfO2, SiO2, and SiN, or a multi-layered film in which at least two or more selected therefrom are stacked in layers.

Here, Al2O3and HfO2are each able to be formed into a film, for example, by use of an atomic vapor deposition (ALD) method. Furthermore, SiO2and SiN are each able to be formed into a film, for example, by a chemical vapor deposition (CVD) method.

In the first embodiment, the second insulating film25B includes a single-layer film of SiO2or SiN, or a multi-layered film in which SiO2and SiN are stacked in layers. Furthermore, the second insulating film25B may include a single-layer film of Al2O3or HfO2, or a multi-layered film in which HfO2is stacked on top of Al2O3or a multi-layered film in which Al2O3is stacked on top of HfO2. Moreover, the second insulating film25B is formed to have a thickness t2of, for example, 25 nm or more and 100 nm or less, regardless of whether it is a single-layer film or a multi-layered film.

Here, the thickness t2of the second insulating film25B is a thickness in a film formation direction from the surface of the channel layer21within the recessed region22A and a thickness that allows it to effectively serve as the gate insulating film25of the transistor2.

The second insulating film25B is provided with a gate opening251, which goes through the second insulating film25B in the thickness direction, within the recessed region22A, further inside than the peripheral edge of the recessed region22A. Here, in the gate length direction, the gate opening251is provided in an intermediate part of the recessed region22A. Likewise, in the gate length direction, a separation distance L1from the peripheral edge of the recessed region22A to a side wall of the gate opening251is formed to be a larger dimension than a thickness t1of the first insulating film25A (L1>t1). The separation distance L1is set to, for example, 25 nm or more. Furthermore, it is practical to set the separation distance L1to, for example, 400 nm or less.

The gate opening251is provided, in the gate width direction, throughout the entire area of at least an active region of the transistor2.

The first insulating film25A is provided on the surface of the channel layer21within the gate opening251and on the second insulating film25B outside the gate opening251to cover these. The first insulating film25A is formed using an insulating material that has insulation performance on the channel layer21and protects the surface of the channel layer21from an impurity such as ions. In addition, the first insulating film25A is formed using an insulating material that keeps the interface with the channel layer21in a good state and keeps the device property of the transistor2in a good condition.

As with the second insulating film25B, the first insulating film25A includes, for example, a single-layer film of at least one selected from Al2O3, HfO2, SiO2, and SiN, or a multi-layered film in which at least two or more selected therefrom are stacked in layers. The first insulating film25A is able to be formed using a film formation method similar to the film formation method of the second insulating film25B.

The first insulating film25A is formed to have the thickness t1of, for example, 5 nm or more and 20 nm or less, regardless of whether it is a single-layer film or a multi-layered film.

Therefore, the gate insulating film25includes, within the gate opening251, the first insulating film25A having the thickness t1, and includes, within the recessed region22A outside the gate opening251, the second insulating film25B having the thickness t2and the first insulating film25A having the thickness t1. That is, the gate insulating film25has two or more thicknesses including the first insulating film25A having the thickness t1(corresponding to a “thin film part” according to the present technology), the second insulating film25B having the thickness t2, and an insulating film of the first insulating film25A and the second insulating film25B stacked on top of each other (corresponding to a “thick film part” according to the present technology).

It is to be noted that the first insulating film25A here is formed along the side wall of the gate opening251. In the first insulating film25A on this side wall, the thickness from the surface of the channel layer21in the direction of arrow Z is larger; however, the thickness in the film formation direction is a thickness from the side wall, and therefore it is the thickness t1.

(8) Configuration of Gate Electrode26

The gate electrode26is provided on the first insulating film25A of the gate insulating film25in the gate opening251and on the first insulating film25A with the second insulating film25B interposed therebetween within the recessed region22A. The gate electrode26is embedded in the gate opening251and extends outside the gate opening251. Preferably, the gate electrode26extends over the outside of the recessed region22A. Such a configuration makes it possible to enhance a gate modulation effect of the transistor2.

Furthermore, the gate electrode26is formed into a T-shape as viewed from the gate width direction. Thus, in the transistor2, it is possible to reduce the gate impedance.

In the first embodiment, the gate electrode26includes, for example, a multi-layered film in which Ni and Au are stacked in layers in this order upward from a surface of the first insulating film25A.

[Method of Manufacturing Semiconductor Device1]

Subsequently, the method of manufacturing the semiconductor device1according to the first embodiment is described.FIGS.3to8illustrate a cross-section of a process to describe the manufacturing method.

First, the buffer layer11is formed on the substrate10(seeFIG.3).

Then, the channel layer21is formed on the buffer layer11(seeFIG.3). The channel layer21is formed, for example, using GaN grown on the buffer layer11by use of the epitaxial growth method.

And then, the barrier layer22is formed on the channel layer21(seeFIG.3). The barrier layer22is formed, for example, using undoped AlGaN grown on the channel layer21by use of the epitaxial growth method. Specifically, the barrier layer22is formed, for example, using a Al0.3—Ga0.7—N crystal. When the barrier layer22has been formed, the two-dimensional electron gas23is produced in the channel layer21near the interface with the barrier layer22.

Next, as illustrated inFIG.3, an insulating film30is formed on the barrier layer22. The insulating film30is formed as a selection mask material that forms the recessed region22A in the barrier layer22.

Here, the isolation region4is formed around an active region where the transistor2is formed. The isolation region4is formed, for example, by implanting an impurity into the channel layer21by use of the ion implantation method and making the channel layer21high-resistance. As the impurity, for example, B is used. Furthermore, the active region is formed into an insular shape.

It is to be noted that the isolation region4may be formed in a process of forming the main electrodes24or after a process of forming the gate electrode26.

Next, the insulating film30is subjected to patterning, and the insulating film30with an opening30A provided on a portion thereof is formed (seeFIG.4). In the patterning, the photolithographic technique and the etching technique are used.

As illustrated inFIG.4, the insulating film30is used as a selection mask, and the recessed region22A is formed by patterning the barrier layer22. In the patterning, the etching technique is used.

In etching technique, there is used wet etching that makes it possible to secure the etch selectivity of the channel layer21and the barrier layer22. By using the wet etching, it becomes possible to selectively remove the barrier layer22without the surface of the channel layer21being over-etched. Furthermore, dry etching is not used, which does not cause etching damage on the surface of the channel layer21.

As illustrated inFIG.5, the insulating film30is removed. In the removal, for example, the etching technique is used. It is to be noted that the insulating film30may be left as a protective film without being removed.

As illustrated inFIG.6, the pair of main electrodes24is formed in regions on the barrier layer22spaced from each other. For example, the main electrode24is formed by sequentially evaporating Ti, Al, Ni, and Au by use of a mask evaporation method.

Next, the second insulating film25B of the gate insulating film25is formed, within the recessed region22A, on the channel layer21, on the barrier layer22, and on the main electrodes24(seeFIG.7). In this manufacturing method, the second insulating film25B is formed, for example, using SiO2. The second insulating film25B is formed, for example, by use of the CVD method.

As illustrated inFIG.7, within the recessed region22A, the gate opening251is formed on the second insulating film25B. When the gate opening251has been formed, the surface of the channel layer21is exposed within the gate opening251. The gate opening251is formed by use of the photolithographic technique and the etching technique. In the etching technique, dry etching is used. If the dry etching is used, it is possible to achieve the miniaturization of the opening diameter of the gate opening251.

Furthermore, in the etching technique, it is possible to use wet etching in addition to the dry etching or use wet etching instead of the dry etching. If the wet etching is used, it is possible to selectively remove the second insulating film25B without the surface of the channel layer21being over-etched. Moreover, the dry etching is not used at least just before the surface of the channel layer21is exposed, which does not cause etching damage on the surface of the channel layer21.

As illustrated inFIG.8, the first insulating film25A is formed on the channel layer21and on the second insulating film25B within the gate opening251. In this manufacturing method, the first insulating film25A is formed, for example, using Al2O3. The first insulating film25A is formed, for example, by use of the ALD method.

When the first insulating film25A has been formed, the gate insulating film25including the first insulating film25A and the second insulating film25B and having two or more thicknesses is formed.

As illustrated inFIGS.1and2described above, the gate electrode26is formed on the gate insulating film25. Within the gate opening251, the gate electrode26is formed on the channel layer21through the first insulating film25A. The gate electrode26is embedded in the gate opening251. Furthermore, outside the gate opening251and within the gate opening251, the gate electrode26is formed on the channel layer21through the second insulating film25B and the first insulating film25A. Outside the gate opening251, the gate electrode26extend around the gate opening251.

For example, the gate electrode26is formed by sequentially evaporating Ni and Au by use of the mask evaporation method.

When a series of these manufacturing processes is finished, the transistor2is formed, and the semiconductor device1according to the first embodiment is completed.

As illustrated inFIGS.1and2, the semiconductor device1according to the first embodiment includes the transistor2. The transistor2includes the channel layer21, the pair of main electrodes24, the barrier layer22, the gate insulating film25, and the gate electrode26. The pair of main electrodes24are spaced from each other and provided on the channel layer21. The barrier layer22is provided on the channel layer21between the pair of main electrodes24. The barrier layer22includes the recessed region22A that goes through the barrier layer22in the thickness direction. The gate insulating film25is provided on the channel layer21in the recessed region22A, and has two or more thicknesses. The gate electrode26is provided on the channel layer21through the gate insulating film25.

Thus, since the gate insulating film25has two or more thicknesses, it is possible to provide the thin film part of the gate insulating film25in a region where the amount of current at the time of on operation of the transistor2becomes high. Furthermore, it is possible to provide the thick film part of the gate insulating film25in a region where the strength of an electric field applied from the gate electrode26becomes high.

To describe it in detail, within the gate opening251of the transistor2, the first insulating film25A having the thickness t1as the thin film part is provided on the channel layer21. Meanwhile, outside the gate opening251of the transistor2and within the recessed region22A, the second insulating film25B having the thickness t2as the thick film part and the first insulating film25A having the thickness t1are provided on the channel layer21. That is, the gate insulating film25is optimized, and the thin film part makes it possible to improve the current characteristics of the transistor2, and the thick film part makes it possible to improve the breakdown voltage of the gate insulating film25of the transistor.

FIG.9illustrates current-voltage characteristics of the transistor2. The horizontal axis indicates voltage, and the vertical axis indicates current. Code A indicates the current-voltage characteristics of the transistor2according to the first embodiment. A voltage of 0 [V] is applied to the main electrode24(S) used as a source electrode, and a drain voltage of the same potential is applied to the main electrode24(D) used as a drain electrode and the gate electrode26.

Code B indicates current-voltage characteristics of a transistor according to a first comparative example. A gate insulating film of the transistor according to the first comparative example is an insulating film having one kind of small thickness. Furthermore, code C indicates current-voltage characteristics of a transistor according to a second comparative example. A gate insulating film of the transistor according to the second comparative example is an insulating film having one kind of large thickness.

As indicated by code A, the transistor2according to the first embodiment is able to raise a threshold voltage Vth and raise the breakdown voltage of the gate insulating film25with respect to the first comparative example indicated by code B. In addition, the transistor2according to the first embodiment is able to effectively suppress an increase in the off-state current and effectively increase the drain current with respect to the second comparative example indicated by code C. That is, the transistor2is able to manage both of improvements in the current-voltage characteristics and the breakdown voltage.

Furthermore, as illustrated inFIG.1, in the semiconductor device1, the distance between the thin film part of the gate insulating film25of the transistor2that has the smallest thickness and the end of the recessed region22A is larger than the thickness of the thin film part. To describe it in detail, in the transistor2, in the gate length direction, the separation distance L1from the peripheral edge of the recessed region22A to the side wall of the gate opening251is formed to be a larger dimension than the thickness t1of the first insulating film25A of the gate insulating film25(L1>t1).

Thus, the distance between the first insulating film25A of the gate insulating film25and the two-dimensional electron gas23becomes longer, which makes it possible to improve the dielectric strength of the first insulating film25A.

Moreover, in the semiconductor device1, the separation distance L1illustrated inFIG.1is equal to or more than 25 nm. Thus, the first insulating film25A is able to secure a dielectric strength of 20 [V] or higher.

Furthermore, as illustrated inFIG.1, in the semiconductor device1, the second insulating film25B as the thick film part of the gate insulating film25of the transistor2is provided outside of the first insulating film25A as the thin film part. To describe it in detail, the first insulating film25A is provided within the gate opening251, and the second insulating film25B is provided outside the gate opening251and within the recessed region22A.

Thus, the distance between the first insulating film25A of the gate insulating film25and the two-dimensional electron gas23becomes longer, which makes it possible to improve the dielectric strength of the first insulating film25A. In addition, the second insulating film25B lies between the first insulating film25A of the gate insulating film25and the two-dimensional electron gas23; therefore, the second insulating film25B is thick, and it is possible to improve the dielectric strength of the gate insulating film25.

2. Second Embodiment

The semiconductor device1according to the second embodiment of the present disclosure is described.FIG.10illustrates a vertical cross-section structure of the main part of the semiconductor device1according to the second embodiment of the present disclosure.FIG.11illustrates a planar structure of the main part of the semiconductor device1illustrated inFIG.10. It is to be noted thatFIG.10illustrates the vertical cross-section structure along a section line B-B illustrated inFIG.11.

Furthermore, in the second and subsequent embodiments to be described below, the same component as the first embodiment or substantially the same component is assigned the same reference numeral, and a repetition of description is omitted.

In the semiconductor device1according to the second embodiment, the thin film part of the gate insulating film25of the transistor2is in contact with a portion of the barrier layer22.

To describe it in detail, in the gate length direction, a portion of the gate opening251on the side of the main electrode24(D) used as a drain electrode is provided outside the recessed region22A. On the side of the main electrode24(D) within the recessed region22A, the first insulating film25A as the thin film part constitutes the gate insulating film25. Meanwhile, on the side of the main electrode24(S) used as a source electrode within the recessed region22A, the second insulating film25B as the thick film part and the first insulating film25A constitute the gate insulating film25. In the transistor2, high voltage is applied to between the gate electrode26and the main electrode24(S).

Components other than those described above are the same as the components of the semiconductor device1according to the first embodiment.

[Method of Manufacturing Semiconductor Device1]

A method of manufacturing the semiconductor device1according to the second embodiment is substantially the same as the method of manufacturing the semiconductor device1according to the first embodiment, except that the position of a mask used to form the gate opening251overlaps with the position of a mask used to form the recessed region22A.

The semiconductor device1according to the second embodiment is able to achieve the action and effects similar to those achieved by the semiconductor device1according to the first embodiment.

Furthermore, as illustrated inFIGS.10and11, in the semiconductor device1, a portion of the first insulating film25A as the thin film part of the gate insulating film25of the transistor2is in contact with a portion of the barrier layer22. The breakdown voltage of the transistor2used in a general circuit is determined by electric field concentration between the gate electrode26and the main electrode24(D) or between the gate electrode26and the main electrode24(S). For example, in a case where the breakdown voltage is determined by electric field concentration between the gate electrode26and the main electrode24(S), a portion of the first insulating film25A is in contact with a portion of the barrier layer22on the main electrode24(D) side.

Thus, on the main electrode24(D) side, there are no regions where the two-dimensional electron gas23is depleted; therefore, it is possible to reduce on-resistance. In addition, on the main electrode24(S) side, the gate insulating film25serves as a thick film part because of the first insulating film25A and the second insulating film25B, and therefore is able to maintain the high breakdown voltage.

The semiconductor device1according to the third embodiment of the present disclosure is described.FIG.12illustrates a vertical cross-section structure of the main part of the semiconductor device1according to the third embodiment of the present disclosure.

In the semiconductor device1according to the third embodiment, the gate insulating film25of the transistor2includes the first insulating film25A, the second insulating film25B, and a third insulating film25C. The third insulating film25C is provided beneath the second insulating film25B.

To describe it in detail, the third insulating film25C is provided, outside the gate opening251and on the periphery of the recessed region22A, on the surface of the channel layer21, on the barrier layer22, and on the main electrodes24. The third insulating film25C is formed, for example, using a similar insulating material to the first insulating film25A, and is formed using an insulating material having the etch selectivity with respect to the second insulating film25B. For example, the third insulating film25C is formed to have a thickness t3that is larger than the thickness t1of the first insulating film25A and smaller than the thickness t2of the second insulating film25B. The thickness t3is set, for example, to 5 nm or more and 30 nm or less.

Components other than those described above are the same as the components of the semiconductor device1according to the first embodiment.

[Method of Manufacturing Semiconductor Device1]

A method of manufacturing the semiconductor device1according to the third embodiment is described.FIGS.13to20illustrate a cross-section of a process to describe the manufacturing method.

First, as with the method of manufacturing the semiconductor device1according to the first embodiment, the buffer layer11is formed on the substrate10(seeFIG.13).

Then, the channel layer21is formed on the buffer layer11(seeFIG.13).

And then, the barrier layer22is formed on the channel layer21(seeFIG.13). When the barrier layer22has been formed, the two-dimensional electron gas23is produced in the channel layer21near the interface with the barrier layer22.

Next, as illustrated inFIG.13, the insulating film30is formed on the barrier layer22. The insulating film30is formed as a selection mask material.

Next, the insulating film30is subjected to patterning, and the insulating film30with the opening30A provided on a portion thereof is formed (seeFIG.14).

As illustrated inFIG.14, the insulating film30is used as a selection mask, and the recessed region22A is formed on the barrier layer22.

As illustrated inFIG.15, the insulating film30is removed.

As illustrated inFIG.16, the pair of main electrodes24is formed in regions on the barrier layer22spaced from each other.

Next, the third insulating film25C of the gate insulating film25is formed, within the recessed region22A, on the channel layer21, on the barrier layer22, and on the main electrodes24(seeFIG.17). Then, as illustrated inFIG.17, the second insulating film25B is formed on the third insulating film25C.

As illustrated inFIG.18, within the recessed region22A, the gate opening251is formed on the second insulating film25B. The gate opening251is formed by use of the photolithographic technique and the etching technique. In the etching technique, for example, dry etching is used. When the gate opening251has been formed, a surface of the third insulating film25C is exposed within the gate opening251.

As illustrated inFIG.19, the third insulating film25C within the gate opening251is removed using the gate opening251as a mask. When the third insulating film25C has been removed, the surface of the channel layer21is exposed within the gate opening251. In the removal of the third insulating film25C, the etching technique is used. In the etching technique, for example, wet etching is used. If the wet etching is used, etching damage on the surface of the channel layer21is reduced.

Here, by the wet etching, the third insulating film25C is isotropically etched in a lateral direction with respect to the gate opening251, and a side-etched part252is formed.

As illustrated inFIG.20, within the gate opening251and within the side-etched part252, the first insulating film25A is formed on the channel layer21and on the second insulating film25B. In this manufacturing method, the first insulating film25A is formed, for example, using Al2O3. The first insulating film25A is formed, for example, by use of the ALD method.

When the first insulating film25A has been formed, the gate insulating film25including the first insulating film25A, the second insulating film25B, and the third insulating film25C and having two or more thicknesses is formed.

As illustrated inFIG.12described above, the gate electrode26is formed on the gate insulating film25.

When a series of these manufacturing processes is finished, the transistor2is formed, and the semiconductor device1according to the third embodiment is completed.

The semiconductor device1according to the third embodiment is able to achieve the action and effects similar to those achieved by the semiconductor device1according to the first embodiment.

Furthermore, as illustrated inFIG.12, in the semiconductor device1, the gate insulating film25includes, at least in the recessed region22A of the barrier layer22, the third insulating film25C on the surface of the channel layer21.

Here, in the manufacturing method, the gate opening251is formed on the second insulating film25B as illustrated inFIG.18, and after that, the third insulating film25C is removed as illustrated inFIG.19. Dry etching is used in the formation of the gate opening251, and wet etching is used in the removal of the third insulating film25C.

Thus, etching damage on the surface of the channel layer21is reduced while the miniaturization of the opening diameter of the gate opening251is achieved. The etching damage is reduced, and therefore it is possible to achieve the suppression of degradation in crystallinity of the channel layer21, the suppression of formation of a fixed charge caused by implantation of an impurity, the improvement of interface characteristics, etc. As a result, it is possible to improve on and off characteristics of the transistor2.

The semiconductor device1according to the fourth embodiment of the present disclosure is described.FIG.21illustrates a vertical cross-section structure of the main part of the semiconductor device1according to the fourth embodiment of the present disclosure.

In the semiconductor device1according to the fourth embodiment, the gate insulating film25of the transistor2includes the first insulating film25A and the second insulating film25B.

To describe it in detail, the first insulating film25A is provided, within the gate opening251, on the channel layer21. The second insulating film25B is provided, outside the gate opening251and within the recessed region22A, on the channel layer21. The first insulating film25A and the second insulating film25B are not stacked on top of each other. That is, the thin film part of the gate insulating film25is the first insulating film25A having the thickness t1. Furthermore, the thick film part of the gate insulating film25is the second insulating film25B having the thickness t2.

Components other than those described above are the same as the components of the semiconductor device1according to the first embodiment.

The semiconductor device1according to the fourth embodiment is able to achieve the action and effects similar to those achieved by the semiconductor device1according to the first embodiment.

The semiconductor device1according to the fifth embodiment of the present disclosure is described.FIG.22illustrates a vertical cross-section structure of the main part of the semiconductor device1according to the fifth embodiment of the present disclosure.

The respective semiconductor devices1according to the first to fifth embodiments described above include the transistor2of an enhancement type that presents normally-off operation. The semiconductor device1according to the fifth embodiment includes, besides the transistor2, a transistor5of a depression type that presents normally-on operation.

To describe it in detail, in the transistor5, the recessed region22A is not provided in the barrier layer22, and the gate electrode26is provided on the barrier layer22through the gate insulating film25. Beneath the gate electrode26, the two-dimensional electron gas23is produced in the channel layer21near the interface with the barrier layer22.

In a method of manufacturing the semiconductor device1, the transistor5is able to be easily formed only by changing the shape of a mask used to form the recessed region22A of the transistor2.

Components other than those described above are the same as the components of the semiconductor device1according to the first embodiment.

The semiconductor device1according to the fifth embodiment is able to achieve the action and effects similar to those achieved by the semiconductor device1according to the first embodiment.

Furthermore, the semiconductor device1is able to include a mix of the enhancement-type transistor2illustrated inFIG.1described above and the depression-type transistor5illustrated inFIG.22.

A semiconductor module100according to the sixth embodiment of the present disclosure is described.FIG.23illustrates a schematic structure of the semiconductor module100according to the sixth embodiment of the present disclosure.

The semiconductor module100according to the sixth embodiment is, for example, an antennas-integrated module with edge antennas101provided in an array and front-end parts mounted on a substrate110as one module. The front-end parts include a switch102, a low-noise amplifier103, a bandpass filter104, a power amplifier105, etc. The semiconductor module100is able to be used, for example, as a communication transceiver.

For example, the semiconductor module100includes the semiconductor device1according to any of the first to fifth embodiments as a transistor included in the switch102, the low-noise amplifier103, the power amplifier105, or something.

The semiconductor module100according to the sixth embodiment includes the semiconductor device1, thus it is possible to achieve further speed-up, higher efficiency, and lower power consumption of wireless communication.

A wireless communication apparatus200according to the seventh embodiment of the present disclosure is described.FIG.24illustrates a schematic block configuration of the wireless communication apparatus200according to the seventh embodiment of the present disclosure.

[Configuration of Wireless Communication Apparatus200]

The wireless communication apparatus200according to the seventh embodiment includes an antenna ANT, an antenna switch circuit201, a high power amplifier HPA, a radio frequency integrated circuit RFIC, a baseband unit BB, an audio output unit MIC, a data output unit DT, and an interface unit I/F. The interface unit I/F includes, for example, a wireless local area network (W-LAN), a Bluetooth (registered trademark), etc. The wireless communication apparatus200is, for example, a cell-phone system having multiple functions of voice and data communications, LAN connection, etc.

The wireless communication apparatus200includes the semiconductor device1according to any of the first to fifth embodiments as a transistor included in the antenna switch circuit201, the high power amplifier HPA, the radio frequency integrated circuit RFIC, the baseband unit BB, or something.

The wireless communication apparatus200according to the seventh embodiment includes the semiconductor device1, thus it is possible to achieve further speed-up, higher efficiency, and lower power consumption of wireless communication. Therefore, in a case where the wireless communication apparatus200is a portable communication terminal, the wireless communication apparatus200is able to further increase the uptime, which makes it possible to further improve the portability.

8. Other Embodiments

The present technology is not limited to the above-described embodiments, and allows for various modifications without departing from its scope.

For example, in the respective semiconductor devices according to the above-described embodiments, the transistor includes GaN-based semiconductor. The present technology is applicable to a semiconductor device with a transistor including a GaAs-based, InP-based, or SiGe-based compound semiconductor. Furthermore, the present technology is also applicable to a semiconductor device with a transistor including a Si semiconductor.

Moreover, the present technology realizes normally-off operation while managing both of high drain current and high withstand voltage, and thus is applicable to not only an RF transistor but also a protection transistor for electrostatic discharge (ESD) breakdown prevention.

<Configuration of Present Technology>

The present technology has the following configuration. According to the present technology of the following configuration, it is possible for a semiconductor device, a semiconductor module, and an electronic apparatus to improve current characteristics and the breakdown voltage.

A semiconductor device including an insulated-gate field-effect transistor, the insulated-gate field-effect transistor including:a channel layer;a pair of main electrodes spaced from each other and provided on the channela barrier layer provided on the channel layer between the pair of main electrodes and including a recessed region that goes through the barrier layer in a thickness direction;a gate insulating film provided on the channel layer in the recessed region and having two or more thicknesses; anda gate electrode provided on the channel layer with the gate insulating film interposed therebetween.
(2)

The semiconductor device according to (1), in which a distance between a thin film part that is a thinnest part of the gate insulating film and an end of the recessed region is greater than a thickness of the thin film part.

The semiconductor device according to (2), in which the distance between the thin film part and the end is equal to or more than 25 nm.

The semiconductor device according to (2) or (3), in which a thick film part of the gate insulating film thicker than the thin film part is provided outside the thin film part.

The semiconductor device according to (4), in which the thin film part includes a material different from a material included in the thick film part.

The semiconductor device according to (4) or (5), in which the thick film part includes a portion of the thin film part.

The semiconductor device according to any one of (1) to (6), in which the gate insulating film includes multiple materials stacked in layers.

The semiconductor device according to any one of (1) to (7), in which the gate electrode extends from the recessed region to the barrier layer.

The semiconductor device according to any one of (1) to (8), in which a position of an interface between the channel layer and the gate insulating film coincides with a position of an interface between the channel layer and the barrier layer.

The semiconductor device according to (2) or (3), in which the thin film part is in contact with a portion of the barrier layer.

A semiconductor module including a semiconductor device including an insulated-gate field-effect transistor,the insulated-gate field-effect transistor including:a channel layer;a pair of main electrodes spaced from each other and provided on the channel layer;a barrier layer provided on the channel layer between the pair of main electrodes and including a recessed region that goes through the barrier layer in a thickness direction;a gate insulating film provided on the channel layer in the recessed region and having two or more thicknesses; anda gate electrode provided on the channel layer with the gate insulating film interposed therebetween.
(12)

An electronic apparatus including a semiconductor device including an insulated-gate field-effect transistor,the insulated-gate field-effect transistor including:a channel layer;a pair of main electrodes spaced from each other and provided on the channel layer;a barrier layer provided on the channel layer between the pair of main electrodes and including a recessed region that goes through the barrier layer in a thickness direction;a gate insulating film provided on the channel layer in the recessed region and having two or more thicknesses; anda gate electrode provided on the channel layer with the gate insulating film interposed therebetween.
(13)

The semiconductor device according to (2) or (3), in which the distance between the thin film part and the end is 25 nm or more and 400 nm or less.

The semiconductor device according to any one of (1) to (10), in which the gate insulating film includes a single-layer film of at least one selected from Al2O3, HfO2, SiO2, and SiN, or a multi-layered film in which at least two or more selected therefrom are stacked in layers.

The semiconductor device according to (4), in whichthe thin film part includes a single-layer film of Al2O3or HfO2, or a multi-layered film in which Al2O3and HfO2are stacked in layers, andthe thick film part includes a single-layer film of SiO2or SiN, or a multi-layered film in which SiO2and SiN are stacked in layers.
(16)

The semiconductor device according to (4), in whichthe thin film part has a thickness of 5 nm or more and 20 nm or less, andthe thick film part has a thickness of 25 nm or more and 100 nm or less.

The present application claims the benefit of Japanese Priority Patent Application JP2021-115092 filed with the Japan Patent Office on Jul. 12, 2021, the entire contents of which are incorporated herein by reference.