Capacitor structure with MIM layer over metal pillars

A capacitor structure for an integrated circuit (IC) is provided. The capacitor structure includes a plurality of spaced metal pillars with each metal pillar positioned on a corresponding underlying metal wire of an underlying metal layer. A metal-insulator-metal layer is positioned over and between the metal pillars. At least one contact is operatively coupled to a first metal pillar of the plurality of metal pillars. The metal-insulator-metal layer creates a MIM capacitor that undulates over the metal pillars, creating a higher density capacitance compared to conventional planar MIM capacitors. The metal pillars extend into the metal-insulator-metal layer, which reduces contact resistance. The capacitor structure can be integrated into an IC with no major integration issues. A related method is also provided.

BACKGROUND

The present disclosure relates to integrated circuit (IC) fabrication, and more specifically, to a capacitor structure with metal pillars over which a metal-insulator-metal (MIM) layer undulates to create a higher density MIM capacitor. A related method is also provided.

Capacitors are used widely in integrated circuits, such as accelerated processing units (APU) or graphics processing units (GPU), to store a charge. Capacitors can take a variety of forms such as vertical natural capacitors (VNCAP) and metal-oxide-metal (MOM) capacitors. Current capacitors are also formed from a combination of metal-insulator-metal (MIM) layers. MIM layers are typically arranged in a planar fashion in the IC, and electrical contacts are made to each of the metal layers to form the capacitor. Planar MIM capacitors use a relatively large area due to their planar layout. Consequently, the density of planar MIM capacitors and the capacitance per unit semiconductor area for planar MIM capacitors are not competitive. One approach to improve capacitance uses undulating MIM layers with contacts to ends of the layer, but this provides poor contact resistance. Finger-based MIM capacitors employ complex finger elements, but are more difficult to manufacture.

SUMMARY

A first aspect of the disclosure is directed to a capacitor structure for an integrated circuit (IC), the capacitor structure comprising: a plurality of spaced metal pillars, each metal pillar positioned on a corresponding underlying metal wire of an underlying metal layer; and a metal-insulator-metal layer over and between the plurality of spaced metal pillars.

A second aspect of the disclosure includes a capacitor structure for an integrated circuit (IC), the capacitor structure comprising: a first metal pillar over a first underlying metal wire of an underlying metal layer; a second metal pillar over a second underlying metal wire of the underlying metal layer, the first metal pillar and the first underlying metal wire spaced from the second metal pillar and the second underlying metal wire; and a metal-insulator-metal layer over and between the first metal pillar and the second pillar, wherein the metal-insulator-metal layer includes a first capacitor metal layer over and between the first and second metal pillars, an insulator layer over the first capacitor metal layer, a second capacitor metal layer over the insulator layer; and at least one contact operatively coupled to the second capacitor metal layer.

A third aspect of the disclosure related to a method of forming a metal-insulator-metal (MIM) capacitor for an integrated circuit, the method comprising: forming a metal pillar over each of a selected plurality of spaced underlying metal wires of an underlying metal layer; and forming a metal-insulator-metal layer over and between the metal pillars to form the MIM capacitor.

The foregoing and other features of the disclosure will be apparent from the following more particular description of embodiments of the disclosure.

DETAILED DESCRIPTION

Embodiments of the disclosure provide a capacitor structure for an integrated circuit (IC). The capacitor structure includes a plurality of spaced metal pillars with each metal pillar positioned on a corresponding underlying metal wire of an underlying metal layer. A metal-insulator-metal (MIM) layer is positioned over and between the metal pillars. At least one contact may be operatively coupled to an upper capacitor metal layer. The MIM layer creates a MIM capacitor that undulates over the metal pillars, creating a higher density capacitance compared to conventional planar MIM capacitors. The metal pillars extend into the MIM layer, which reduces contact resistance. The capacitor structure can be integrated into an IC with no major integration issues. A related method is also provided.

Referring toFIGS. 1-7, embodiments of a method of forming a capacitor structure100(FIG. 7), namely a MIM capacitor, for an integrated circuit (IC)102, are illustrated.

FIGS. 1-3show cross-sectional views of forming a metal pillar110(FIG. 3) over each of a selected plurality of spaced underlying metal wires112of an underlying metal layer114. Underlying metal layer114may include any metal layer in IC102. In one example, underlying metal layer114may be a first metal layer, i.e., over a device layer (not shown). However, underlying metal layer114may be any back end of line (BEOL) layer. As understood, a BEOL layer is any layer formed on the semiconductor wafer (not shown) in the course of device manufacturing following first metallization. Underlying metal layer114may include any interlayer dielectric (ILD)120. ILD120may include but is not limited to: carbon-doped silicon dioxide materials; fluorinated silicate glass (FSG); organic polymeric thermoset materials; silicon oxycarbide; SiCOH dielectrics; fluorine doped silicon oxide; spin-on glasses; silsesquioxanes, including hydrogen silsesquioxane (HSQ), methyl silsesquioxane (MSQ) and mixtures or copolymers of HSQ and MSQ; benzocyclobutene (BCB)-based polymer dielectrics, and any silicon-containing low-k dielectric. Examples of spin-on low-k films with SiCOH-type composition using silsesquioxane chemistry include HOSP™ (available from Honeywell), JSR 5109 and 5108 (available from Japan Synthetic Rubber), Zirkon™ (available from Shipley Microelectronics, a division of Rohm and Haas), and porous low-k (ELk) materials (available from Applied Materials). Examples of carbon-doped silicon dioxide materials, or organosilanes, include Black Diamond™ (available from Applied Materials) and Coral™ (available from Lam Research). An example of an HSQ material is FOx™ (available from Dow Corning).

Metal wires112in underlying metal layer114may be formed in any now known or later developed fashion. In one non-limiting example, metal wires112may be formed by lithographically defining openings124in ILD120, then depositing metal to fill resulting trenches, and then removing excess metal, e.g., by means of chemical-mechanical polishing (planarization). Openings124may be etched in ILD120, i.e., using a mask (not shown). Etching generally refers to the removal of material from a substrate (or structures formed on the substrate), and is often performed with a mask in place so that material may selectively be removed from certain areas of the substrate, while leaving the material unaffected, in other areas of the substrate. There are generally two categories of etching, (i) wet etch and (ii) dry etch. Wet etch is performed with a solvent (such as an acid) which may be chosen for its ability to selectively dissolve a given material (such as oxide), while, leaving another material (such as polysilicon) relatively intact. This ability to selectively etch given materials is fundamental to many semiconductor fabrication processes. A wet etch will generally etch a homogeneous material (e.g., oxide) isotropically, but a wet etch may also etch single-crystal materials (e.g. silicon wafers) anisotropically. Dry etch may be performed using a plasma. Plasma systems can operate in several modes by adjusting the parameters of the plasma. Ordinary plasma etching produces energetic free radicals, neutrally charged, that react at the surface of the wafer. Since neutral particles attack the wafer from all angles, this process is isotropic. Ion milling, or sputter etching, bombards the wafer with energetic ions of noble gases which approach the wafer approximately from one direction, and therefore this process is highly anisotropic. Reactive-ion etching (RIE) operates under conditions intermediate between sputter and plasma etching and may be used to produce deep, narrow features, such as STI trenches. Openings124for metal wires112may be etched, for example, using RIE.

“Depositing” may include any now known or later developed techniques appropriate for the material to be deposited including but are not limited to, for example: chemical vapor deposition (CVD), low-pressure CVD (LPCVD), plasma-enhanced CVD (PECVD), semi-atmosphere CVD (SACVD) and high density plasma CVD (HDPCVD), rapid thermal CVD (RTCVD), ultra-high vacuum CVD (UHVCVD), limited reaction processing CVD (LRPCVD), metalorganic CVD (MOCVD), sputtering deposition, ion beam deposition, electron beam deposition, laser assisted deposition, thermal oxidation, thermal nitridation, spin-on methods, physical vapor deposition (PVD), atomic layer deposition (ALD), chemical oxidation, molecular beam epitaxy (MBE), plating, evaporation. Here, the metal may be deposited using, for example, ALD. A refractory metal liner (not shown) of, for example, ruthenium (Ru), tantalum (Ta), titanium (Ti), tungsten (W), iridium (Jr), rhodium (Rh), platinum (Pt), etc., or mixtures of thereof, may be deposited prior to metal deposition. Metal wires112may include any conductor employed in IC wiring, for example, copper. While three metal wires112are shown in the drawing, two or more than three may be employed. The number of metal wires112may be chosen to create a certain size capacitor structure, as will be described. As will be described, metal wires (not shown inFIG. 1) may also be formed for underlying metal layer114in a non-MIM region158(FIGS. 4-7), e.g., for logic, adjacent to the MIM capacitor.

FIG. 1also shows forming a material layer130over an etch stop layer (ESL)132over selected plurality of spaced underlying metal wires112. That is, material layer130and etch stop layer (ESL)132are formed over underlying metal layer114. ESL132may include any material typically used to stop etching such as but not limited to silicon nitride (e.g., n-Blok), and may be formed by any appropriate deposition technique, e.g., CVD. Material layer130is formed over ESL132, e.g., by CVD. Material layer130may include any sacrificial material capable of defining cavities for metal pillar110(FIG. 3) formation. For example, material layer130may include any ILD material listed herein.FIG. 1also shows patterning a cavity140in material layer130and ESL132over each of selected plurality of spaced underlying metal wires112. Cavities140may be patterned by forming a mask (not shown), patterning the mask and etching to remove material layer130and ESL132over underlying metal wires112. The etching may include, for example, a RIE. While shown with each cavity140aligned over metal wires112, some misalignment may be allowed. Further, while a cavity140is shown over each metal wire112, a cavity140is not necessarily required over each metal wire, e.g., where more than two metal wires112are provided between outermost metal wires. The number of cavities140(and hence the number of metal pillars110formed therein) may be defined to customize the number of undulations in an eventually formed MIM layer, and hence, used to control the capacitance of capacitor structure100(FIG. 7), i.e., by controlling its length created in the undulations. In one embodiment, at least three metal wires112and at least three metal pillars110are provided.

FIG. 2shows a cross-sectional view of filling each cavity140with a metal142. Metal142may be deposited, e.g., by ALD, followed by a planarization step to remove excess metal. Metal142may be the same as or different than metal wires112. In one embodiment, metal142may include copper (Cu). In other embodiments, metal142may include but is not limited to: titanium, titanium nitride, ruthenium, tungsten, cobalt or any other conductive metal.FIG. 3shows a cross-sectional view of removing material layer130to leave a metal pillar110over each of selected plurality of spaced underlying metal wires112. An upper portion of metal pillars110are exposed by this process. Material layer130may be removed using any appropriate etching process selective to metal142(FIG. 2), e.g., a RIE. Metal pillars110are spaced apart per the spacing of underlying metal wires112.

FIGS. 4-7show cross-sectional views of forming a metal-insulator-metal (MIM) layer150over and between spaced metal pillars110to form capacitor structure100(FIG. 7). Forming MIM layer150over and between spaced metal pillars110includes forming a first capacitor metal layer152over and between metal pillars110, forming an insulator layer154over first capacitor metal layer152, and forming a second capacitor metal layer156over insulator layer154. Each layer152,154,156may be formed by any appropriate deposition for the materials used, e.g., ALD. As illustrated inFIG. 4, each metal pillar110is contacted on three sides by first capacitor metal layer152, which improves a contact resistance of metal wire112to first capacitor metal layer152that provides a first electrode of capacitor structure100(FIG. 7). Capacitor metal layers152,156may include any now known or later developed capacitor electrode material including but not limited to: titanium nitride (TiN), ruthenium (Ru), tantalum nitride (TaN), or any other conductive materials. Insulator layer154may include any now known or later developed high dielectric constant (high-K) material appropriate for a MIM capacitor. In one embodiment, insulator layer154may include but is not limited to: tantalum oxide (Ta2O5), barium titanium oxide (BaTiO3), hafnium oxide (HfO2), zirconium oxide (ZrO2), aluminum oxide (Al2O3), hafnium silicate oxide (HfSixOy) or hafnium silicon oxynitride (HfSixOyNz), where x, y, and z represent relative proportions, each greater than or equal to zero.

As illustrated inFIG. 4, spacing between metal pillars110may be such that first capacitor metal layer152and insulator layer154undulate over metal pillars110. That is, first capacitor metal layer152and insulator layer154extend in valleys between metal pillars110and peaks over metal pillars110, in a somewhat sinusoidal fashion. In this manner, the length of capacitor structure100(FIG. 7) can be increased without increasing geographic area within IC102. As shown in the example inFIG. 4, second capacitor metal layer156may fill any remaining space between metal pillars110(e.g., left between insulator layer154as it passes over metal pillars110). Second capacitor metal layer156also extends over metal pillars110. Any excess second capacitor metal layer156may be removed, e.g., by planarizing. MIM layer150forms capacitor structure100.FIGS. 4-6also show an additional metal wire112(right side) in underlying metal layer114in non-MIM (e.g., logic) region158that is not covered by a metal pillar110.

As shown in the cross-sectional view ofFIG. 5, embodiments of the method may further include forming an ILD160over capacitor structure100. ILD160may include any now known or later developed ILD such as listed herein relative to ILD120. Any necessary planarization may be carried out at this stage.

FIG. 6shows a cross-sectional view of patterning capacitor structure100to a selected dimension(s), e.g., trimming a length across page and/or depth into and out of page. Capacitor structure100may be patterned, for example, by patterning a mask164over capacitor structure100and etching to remove any un-desired MIM layer150. In the example shown, a length L1is shorter inFIG. 6than a length L2inFIG. 5. It is understood that a depth of capacitor structure100into and out of the page could be similarly customized. In this manner, dimension(s) of capacitor structure100can be customized to deliver the desired capacitance. Any MIM layer150that may be present in non-MIM region158of IC102can also be removed as part of the patterning of capacitor structure100.

FIG. 7shows a cross-sectional view of forming at least one contact170,174operatively coupled to second capacitor metal layer156. While one contact may be employed, at least two spaced contacts170,174operatively coupled to second capacitor metal layer156are advantageous to reduce contact resistance. Note, the embodiment shown inFIG. 7also includes more than three metal pillar110and metal wire112pairs with MIM layer150thereover, and is longer than theFIG. 6embodiment. The contact forming process may include replacing any ILD160removed during the patterning ofFIG. 6. ILD160may also be replaced over non-MIM region158, which is shown larger inFIG. 7than inFIGS. 4-6for clarity. Contact(s)170,174may be formed using any now known or later developed process. In one non-limiting example, contact(s)170,174may be formed by lithographically defining openings162in ILD160, then depositing metal to fill resulting trenches, and then removing excess metal, e.g., by means of chemical-mechanical polishing (planarization). Openings162may be etched in ILD160, e.g., using RIE. Here, the contact metal may be deposited using, for example, ALD. A refractory metal liner (not shown) of, for example, ruthenium (Ru), tantalum (Ta), titanium (Ti), tungsten (W), iridium (Jr), rhodium (Rh), platinum (Pt), etc., or mixtures of thereof, may be deposited prior to metal deposition. Contact(s)170,174may include any contact conductor employed in IC wiring, for example, copper. In one embodiment, contact170is aligned over a first metal pillar110A, and contact174is aligned over second metal pillar110B, but this is not necessary in all instances. A number of contacts170,174may be customized to reduce contact resistance. As illustrated, metal wires, and/or contacts176for non-MIM region158may be formed with contact(s)170,174.

FIG. 8shows a cross-sectional view of another embodiment similar toFIG. 7but in which the spacing between metal pillar110and metal wire112pairs is non-uniform. As illustrated, MIM layer150thus may have non-uniform length valleys and/or non-uniform length peaks.

FIGS. 7 and 8also show cross-sectional views of capacitor structure100for IC102, according to embodiments of the disclosure. Capacitor structure100may include a plurality of spaced metal pillars110with each metal pillar110positioned on a corresponding underlying metal wire112of underlying metal layer114. Metal wires112may include copper. ESL132may be adjacent a lower end of plurality of metal pillars110, i.e., over underlying metal layer114. Capacitor structure100also includes MIM layer150over and between plurality of spaced metal pillars110. MIM layer150includes first capacitor metal layer152over and between plurality of spaced metal pillars110, insulator layer154over first capacitor metal layer152, and second capacitor metal layer156over insulator layer154. The materials for capacitor metal layers152,156and insulator layer154may be as previously described. As illustrated inFIG. 7, first capacitor metal layer152and insulator layer154undulate over spaced metal pillars110. Again, first capacitor metal layer152and insulator layer154extend in valleys between metal pillars110and peaks over metal pillars110, in a somewhat sinusoidal fashion. As shown in the example inFIG. 7, second capacitor metal layer156may fill any remaining space between metal pillars110, e.g., left between insulator layer154as it passes over metal pillars110. Second capacitor metal layer156extends over metal pillars110. MIM layer150thus forms capacitor structure100, i.e., a MIM capacitor. One or more metal pillars110may be positioned between the outermost metal pillars110A,110B (FIG. 7), allowing customization of the length and thus capacitance value of MIM layer150and capacitor structure100. Capacitor structure200may also include at least one contact170,174operatively coupled to second capacitor metal layer156, i.e., a second electrode of capacitor structure100.

Embodiments of the disclosure provide capacitor structure100that undulates over metal pillars110, creating a higher density capacitance compared to conventional planar MIM capacitors. Metal pillars110extend into MIM layer150with MIM layer on three sides of each pillar, which reduces contact resistance. As is apparent from the description, capacitor structure100can be integrated into IC102with no major integration issues. Capacitor structure100is also compatible with decreasing dimensions of the latest technology nodes, e.g., 7 nanometers and beyond.