PCI express packet filter including descrambler

A packet detecting device used in a receiver employing PCI Express protocol is disclosed. The packet detecting device includes: a physical layer packet detecting unit for detecting a physical layer packet from a PCI express packet received and parallelized to 16 bit data through a physical deserializer; a descrambling unit for descrambling a physical layer packet from a PCI express packet received and parallelized to 16 bit data through a physical deserializer; a data link layer packet detecting unit for detecting a data link layer packet from a descrambled packet outputted from the descrambling unit; and a transaction layer packet detecting unit for detecting a transaction layer packet from a descrambled packet outputted from the descrambling unit.

FIELD OF THE INVENTION

The present invention relates to a packet detecting device used in a receiver employing a peripheral component interconnect express (PCI Express) 1x protocol that is an input/output (IO) standard.

DESCRIPTION OF RELATED ARTS

Peripheral component interconnect express (PCI Express) is a layered protocol, consisting of a transaction layer, a data link layer, and a physical layer. Packets are processed at a layer different from those processed at other layers in types and formats.

In a PCI Express protocol, a control character and a data character formed in a byte unit of 8 bits, are transformed to data formed in a symbol unit, and the transformed data is transmitted using 2.5 Gbps of high frequency. In the high frequency transmission, energy is concentrated at a predetermined frequency due to radiation pattern. It generates electromagnetic interference (EMI) noise. In order to prevent the EMI noise from being generated, a scrambling scheme is used. Therefore, it requires a packet detection device to have a descrambling function.

The data bandwidth for 2.5 Gbps signal can be designed as 8 bits at 250 MHz of data transfer speed. Since a circuit with a low speed device is generally designed as 125 MHz of data transfer speed, the data bandwidth of 2.5 Gbps is required to be 16 bits. However, the PCI Express standard introduces a descrambling method for only 8 bits parallel processing. Therefore, it requires the data bandwidth to be extended for 16 bits parallel processing.

Since a simple scrambler is used in the conventional technology, a storing buffer is required to previously inspect a packet to process unscrambled packets used in a physical layer. Since the packets are doubly processed at the physical layer, the overlapping problem of the related circuits is arisen.

SUMMARY OF THE INVENTION

It is, therefore, an object of the present invention to provide a PCI express packet detection device for detecting packets at each layer by equipping a descrambling function in a packet receiver in a PCI express protocol.

In accordance with an aspect of the present invention, there is provided a PCI express packet detection device including: a physical layer packet detecting unit for detecting a physical layer packet from a PCI express packet received and parallelized to 16 bit data through a physical deserializer; a descrambling unit for descrambling a physical layer packet from a PCI express packet received and parallelized to 16 bit data through a physical deserializer; a data link layer packet detecting unit for detecting a data link layer packet from a descrambled packet outputted from the descrambling unit; and a transaction layer packet detecting unit for detecting a transaction layer packet from a descrambled packet outputted from the descrambling unit.

DETAILED DESCRIPTION OF THE INVENTION

Hereinafter, a PCI Express packet filter having a descrambler will be described in more detail with reference to the accompanying drawings.

FIG. 1is a block diagram illustrating a PCI Express standard according to related art, which is used in PCI Express specification or general design.

The PCI Express standard includes a physical layer deserializer100, a physical layer110, a data link layer120, and a transaction layer130. The physical layer110includes a descrambler111, a packet detector112, a physical layer processing engine113, a packet generator114and a scrambler115.

The physical layer deserializer100receives serial data, parallelizes the received serial data to 16-bit parallel data, and outputs the 16-bit parallel data to the descrambler111. The descrambler111descrambles the 16-bit parallel data and outputs the descrambled data to the physical layer processing engine113through the packet detector112. The physical layer processing engine113substitutes the scrambled data with a detection signal if the scrambled packet is used in the physical layer engine. Otherwise, the physical layer processing engine113passes the scrambled packets to the data link layer120.

The data link layer120receives not only a packet processed in the data link layer120but also a packet processed in the transaction layer130. The data link layer processed the related packets and transfers the packet to be processed in the transaction link layer130to the transaction link layer130.

FIG. 2is a diagram illustrating a descrambler210according to the related art shown inFIG. 1.

Referring toFIG. 2, the descrambler210according to the related art includes a packet buffer211, a physical layer packet detector212, and a descrambler engine213.

The descrambler210requires an additional packet buffer211for detecting a physical layer packet which is not scrambled, thereby generating a delay time. The descrambler210also requires the physical layer packet detector212for determining whether the packet stored in the packet buffer211is a physical layer packet or not.

A PCI express packet receiver receives 2.5 Gbps serial input signal to a 16-bit parallel signal using a deserializer.

An object of the present invention is to extract packets used in each layer of the PCI express from the 16 bit parallel data. Since a physical layer packet is not scrambled, the physical layer packet is not required to pass through the descrambler210when packets are detected.

A packet transmitter transforms 8-bit packets to 10 bit symbols and transmits the 10 bit symbols. A received signal is not always sorted in 16-bit units. Therefore, it requires a circuit to detect not only packets arranged in 16-bit units but also packets not arranged in 16-bit units.

Since the data link layer packet and the transaction layer packet are transmitted as scrambled format, a descrambler is required. Also, the conventional circuit requires the received data to be extended to 8 bits, to detect packet regardless of whether it is arranged or not, and to output a packet arranged in 16-bit units at a final output end.

FIG. 3is a block diagram illustrating a PCI express packet detection device in accordance with an embodiment of the present invention.

Referring toFIG. 3, the PCI express packet detection device according to the present embodiment includes a physical layer packet detector310, a data link layer packet detector320, a transaction layer packet detector330, and a descrambler340. The physical layer packet detector310detects a physical layer packet from a PCI express packet which is received and parallelized to 16 bits data through the physical deserializer100. The descrambler340descrambles a PCI express packet which is received and parallelized to 16 bits data through the physical deserializer100. The data link layer packet detector320detects data link layer packet from the described packet outputted from the descrambler340. The transaction layer packet detector330detects a transaction layer packet layer packet from the described packet outputted from the descrambler340.

Since the physical packet is not a scrambled packet, the physical packet detector310directly receives a signal from the deserializer100, not from the descrambler340. The descrambler340descrambles all of the received packets without determining whether the received packet is the physical layer packet or not. Therefore, the descrambler340does not require the packet buffer211and the physical layer packet detector212as shown inFIG. 2. The scrambler340can be embodied with including only a descrambler engine213.

FIG. 4is a block diagram illustrating a method of embodying a PCI express packet detection device according to an embodiment of the present invention in a PCI express engine.

Referring toFIG. 4, since the PCI express packet detection device according to the present embodiment classifies packets into physical layer packets to be processed at the physical layer processing engine430, data link layer packets to be processed at the data link layer440, and transaction layer packets to be processed at the transaction layer450, each layer can be independently designed. If such a structure is applied to a packet transmitting side, a physical layer processing engine430can transmit a packet without scrambling the packet using the scrambler470. A data link layer440and a transaction layer450scramble the packet through the scrambler470and transmit the scrambled packet. Therefore, the scrambler470also does not require the physical link packet determiner212and the packet buffer211shown inFIG. 2.

Instead of having the physical link packet determiner212and the packet buffer211, the scrambler470requires a packet multiplexer480. However, it is not a complicated circuit because an order of generating a packet at each layer is defined in the PCI express protocol.

Since a scrambling algorithm is basically equal to a descrambling algorithm, the descrambler210inFIG. 2can be used as the scrambler470inFIG. 4.

FIG. 5is a block diagram illustrating a physical layer packet detector in a PCI express packet detection device420in accordance with an embodiment of the present invention. That is,FIG. 5shows a circuit for arranging packets used in the physical layer packet detector310.

The physical layer packet detector310has an identical structure compared to the data link layer packet detector320and the transaction layer packet detector330excepting a packet start detection circuit510.

If a packet start is detected from a lower 8 bit data560, the packet start detection circuit510outputs a control signal to an upper 8-bit multiplexer530to output an upper 8-bit data555and a lower 8 bit multiplexer540to output a lower 8-bit data560. If a packet start is detected from the upper 8-bit data560, the packet start detection circuit510outputs a control signal to an upper 8-bit multiplexer530to output the lower 8-bit data555and the lower 8-bit multiplexer540to output an output signal from a 8-bit flip-flop520. Therefore, data outputted as the lower 8-bit always denotes the start of a corresponding packet.

A polynomial expression of a linear feedback shift register (LFSR) of a PCI express scrambler is shown in Eq. 1, andFIG. 6shows a circuit for scrambling in a bit unit.
G(X)=X16+X5+X4+X3+1  Eq. 1

FIG. 6is a circuit diagram illustrating a scrambler shown inFIG. 4. That is,FIG. 6shows a LFSR calculated in a bit unit and a scrambled output data.

The LFSR has FFFF as an initial value, and the LFSR changes by feed-backing the value thereof in response to a data clock cycle.

When a COM symbol is inputted to the LFSR, the value thereof is initialized to FFFF, and when a SKP symbol is inputted to the LFSR, a feedback function and a shift function of the LFSR are interrupted.

Since the bit unit computation is operated at 2 GHz, that is, 1 bit×2 GHz=2 Gps, a 8-bit computation requires a 250 MHz operation speed because 8 bit×250 MHz=2 Gbps. Also, a 16-bit computation requires a 125 MHz operation speed because 16 bit×125 MHz=2 Gps. A symbol is 10-bit data transformed from 8-bit data, a 8 bit design is proper. However, it is difficult to operate a low speed device at 250 MHz. Therefore, in the present embodiment, a circuit operated at 125 MHz is designed.

Since the symbol is originally a 8-bit unit, the symbol is not guaranteed to be arranged in 16 bit unit. Therefore, it requires a circuit to be designed to accurately output a LFSR and a data output value not only for a unarranged symbol but also for an arranged symbol.

In the present embodiment, LFSR calculating equations are composed with all combinations in COM, general data symbol (sym), and SKP as follows.

The lower 8 bits among data output values are output as it is if the lower 8 bit of the input data is a control character. If the lower 8 bit of the input data is a data character, the lower 8 bits are outputted as follows.
output data[0]=input data[0]⊕LFSR[15];
output data[1]=input data[1]⊕LFSR[14];
output data[2]=input data[2]⊕LFSR[13];
output data[3]=input data[3]⊕LFSR[12];
output data[4]=input data[4]⊕LFSR[11];
output data[5]=input data[5]⊕LFSR[10];
output data[6]=input data[6]⊕LFSR[9];
output data[7]=input data[7]⊕LFSR[8];

The upper 8 bits among the data output value are outputted as it is if the upper 8 bit data is a control character.

The above described method according to the present invention can be embodied as a program and stored on a computer readable recording medium. The computer readable recording medium is any data storage device that can store data which can be thereafter read by the computer system. The computer readable recording medium includes a read-only memory (ROM), a random-access memory (RAM), a CD-ROM, a floppy disk, a hard disk and an optical magnetic disk.

According to the present invention, packets are classified and distributed by layers in the PCI express protocol, thereby reducing unnecessary uses of buffers. Also, 2.5 Gbps can be embodied at 125 MHz operation speed using a 16 bit descrambler which can be used in a low speed device. The packet detection device according to the present invention outputs data with data sorted using a sorter included inside thereof. Thus, an additional sorter is not required. Furthermore, the packets are not doubly inspected in the present invention, thereby reducing the waste of circuit.

The present application contains subject matter related to Korean patent application Nos. 2005-0116138 and 2006-0061386, filed with the Korean patent office on Dec. 1, 2005, and Jun. 30, 2006, respectively, the entire contents of which being incorporated herein by reference.

While the present invention has been described with respect to certain preferred embodiments, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the spirits and scope of the invention as defined in the following claims.