Soft error robust flip-flops

A flip-flop circuit is provided with an improved robustness to radiation induced soft errors. The flip-flop cell comprises the following elements. A transfer unit for receiving at least one data signal and at least one clock signal, a storage unit coupled to the transfer unit and a buffer unit coupled to the storage unit. The transfer unit includes a plurality of input nodes adapted to receive said at least one data signal and said at least one clock signal; a first output node for providing a sampled data signal in response to said at least one clock signal and said at least one data signal; and a second output node for providing a sampled inverse data signal, the sampled inverse data signal provided in response to said at least one clock signal and said at least one data signal. The storage unit comprises a first and a second storage nodes configured to receive and store the sampled data signal and the sampled inverse data signal. The storage unit comprises drive transistors configured to selectively couple one of the first and second storage nodes to ground; load transistors configured to selectively couple the other one of the first and second storage nodes to a power supply; and at least one stabilizer transistor configured to provide a corresponding redundant storage node and limit feedback between the first and second storage nodes, the redundant storage node being capable of restoring the first or second storage nodes in case of a soft error. The buffer unit provides an output sampled data signal as received from the storage unit.

BACKGROUND OF THE INVENTION

Flip-flops are widely used in integrated circuits, such as in microprocessors and other digital circuits to temporarily store data. A flip-flop stores data by sampling an input data signal with a clock signal at a particular instant of time, typically at an edge of the clock. The output of the flip-flop is sensitive to the input data signal at the clock edge. At all other times, the output does not respond to changes in the input data signal.

A flip-flop can be realized in a variety of ways as understood by a person skilled in the art. A typical way of realizing a flip-flop is to use two series connected latches called a master and a slave as illustrated inFIG. 8. In the illustrated example, the master latch is transparent to a low (0) clock signal level while the slave is transparent to a high (1) clock signal, making the output of the flip-flop sensitive only to 0 to 1 transition of the clock. However, such master-slave flip-flops present several shortcomings. For example, in order to change the output of the master-slave flip-flop, a signal propagates through both the master and the slave stages. The resulting delay poses limitations in high speed circuits. Further, the data values in the master and the slave stages can be susceptible to ionizing radiation. Types of ionizing radiation may include alpha particles and cosmic neutrons. These particles can generate a large number of electron hole pairs, which may be collected by the storage nodes and result in a data upset, which is known as a soft error (SE). This is particularly true for nanoscaled circuits where the charge representing a data state on a storage node is very small due to low node capacitance and supply voltage.

The SE problem is addressed by using SE immune latches, such as the Dual Interlocked Cell (DICE) latch, for the master and slave stages. For example, referring toFIG. 9, a schematic diagram of an SE immune flip-flop having master slave stages is illustrated. However, this type of flip-flop has a large number of transistors, which can cause significant delay, an increase in area, and power penalties. In addition, the flip-flop increases the clock load and hence the clock power consumption. As a consequence, this type of flip-flop is not suitable for high speed or low power applications.

Due to the growing need for technology scaling and the corresponding susceptibility to radiation induced soft error, it would be advantageous to provide soft error robust flip flops. Further, it is desirable to improve the flip flop circuit immunity against soft error while limiting the number of extra transistors. Reducing the number of transistors allows the flip-flops to occupy less space and permits higher cell density. As well, fewer transistors reduce delay, and allow for more efficient power usage such that the flip flops may be suitable for high speed or low power applications.

SUMMARY OF THE INVENTION

In accordance with an aspect of the present invention there is provided a flip-flop comprising a transfer unit for receiving at least one data signal and at least one clock signal, a storage unit coupled to the transfer unit and a buffer unit coupled to the storage unit; the transfer unit comprising: a plurality of input nodes adapted to receive said at least one data signal and said at least one clock signal; a first output node for providing a sampled data signal in response to said at least one clock signal and said at least one data signal; and a second output node for providing a sampled inverse data signal complementary to the sampled data signal, the sampled inverse data signal provided in response to said at least one clock signal and said at least one data signal; the storage unit comprising a first and a second storage nodes configured to receive and store the sampled data signal and the sampled inverse data signal, the storage unit comprising: drive transistors configured to selectively couple one of the first and second storage nodes to ground; load transistors configured to selectively couple the other one of the first and second storage nodes to a power supply; and at least one stabilizer transistor configured to provide a corresponding redundant storage node and limit feedback between the first and second storage nodes, the redundant storage node being capable of restoring the first or second storage nodes in case of a soft error; the buffer unit for receiving input from at least one of the storage nodes and the redundant storage node and for providing an output sampled data signal.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

For convenience, like numerals in the description refer to like structures in the drawings. Referring toFIG. 1, a standard six-transistor SRAM cell is illustrated generally by numeral100. The SRAM cell100comprises a pair of n-type drive transistors N1and N2and a pair of p-type load transistors P1and P2in a cross-coupled configuration. A further pair of n-type access transistors N3and N4couples the cell100to a complementary bit-line pair BL and BLB. The sources of the drive transistors N1and N2are coupled to ground, and the sources of the load transistors P1and P2are coupled to a supply voltage VDD.

The SRAM cell100is coupled to the bit-line pair BL and BLB in a response to a word-line control signal WL from a row decoder (not shown). Accordingly, when the word-line control signal WL is active, the SRAM cell100is electrically connected to the bit-line pair BL and BL.

Referring toFIG. 4, a soft error robust (SER) SRAM cell in accordance with an embodiment of the invention is illustrated generally by numeral400. The SER SRAM cell400is similar to SRAM cell illustrated inFIG. 1. For ease of description, the node at the junction of the drain of load transistor P1and the source of drive transistor N1will be referred to as storage node A. Similarly, the node at the junction of the drain of load transistor P2and the source of drive transistor N2will be referred to as storage node B. The nodes A and B are referred to as storage node because they store respective voltages when the access transistors N3and N4are turned off, as is known in the art.

However, in the present embodiment, the drive transistors N1and N2are designed to be stronger than their corresponding load transistors P1and P2, respectively. Further, the cell comprises an additional two n-type stabilizer transistors N5and N6. Stabilizer transistor N5is coupled between the gate of load transistor P1and the gate of drive transistor N1. Stabilizer transistor N6is coupled between the gate of load transistor P2and the gate of drive transistor N2. The gates of the stabilizer transistors N5and N6are connected to the word line WL. For ease of description, the node at the gate of stabilizer transistor N5will be referred to as storage node C and the node at the gate of stabilizer transistor N6will be referred to as storage node D. Storage nodes C and D are provide redundant storage.

The SER SRAM cell400is able to hold two states when the access transistors N3and N4are turned off. The states are associated with a binary one and a binary zero. Accordingly, when the access transistors N3and N4are turned off storage nodes A and B store voltages for a corresponding binary number.

From the description above as well as fromFIG. 4, it will be appreciated that the stabilizer transistors N5and N6break the inherent positive feedback between the storages nodes A and B and provide additional storage nodes C and D. That is, the gates of the stabilizer transistors N5and N6are controlled by the word line WL so that the feedback mechanism only works when the word line WL goes high. Further, the stabilizer transistors N5and N6are designed to have a very low threshold voltage, and hence a higher leakage. This feature helps achieve almost full swing at the storage nodes C and D. Alternatively, the word line WL may be overdriven to achieve full swing signal at the storage nodes C and D.

It will be appreciated that breaking the inherent feedback of the cross-coupled drive and load transistors N1, N2, P1, and P2, respectively, and providing additional storages nodes improves the robustness of an SRAM cell significantly.

For example, consider the case when storage nodes A and D store a logic 1 while storage nodes B and C store a logic 0. If the voltage at storage node A becomes logic 0 due to a soft error, such as cosmic radiation, the load transistor P2turns on. However, drive transistor N2is also on because storage node D stores a logic 1.

Since drive transistor N2is designed to be stronger than load transistor P2, storage node B will retain its original logic value of 0. This will, in turn, keep load transistor P1turned on. Since load transistor P1remains on, it will ensure the storage node A recovers its original logic value of 1. Similarly, a radiation incident on storage node B will not also result in a data upset.

Referring toFIG. 5, a SER SRAM cell in accordance with an alternate embodiment is illustrated generally by numeral500. The SER SRAM cell500of the present embodiment is similar to the SER SRAM400as described with reference toFIG. 4. However, in the present embodiment, the SER SRAM cell500includes only one stabilizer transistor N5.

Referring toFIG. 6, a SER SRAM cell in accordance with yet an alternate embodiment is illustrated generally by numeral600. The SER SRAM cell600of the present embodiment is similar to the SER SRAM400as described with reference toFIG. 4. However, in the present embodiment, the SER SRAM cell600includes supply transistors P3and P4. As shown, the supply transistor P3is coupled between the power supply VDD and storage node C, and is gated by the voltage stored on storage node A. Similarly, the supply transistor P4is coupled between the power supply VDD and storage node D, and is gated by the voltage stored on storage node B.

Although the SER SRAM cell600operates in a similar manner to the SER SRAM cell400described with reference toFIG. 4, the two supply transistors P3and P4are added to provide more stable complementary voltages at storage nodes C and D, respectively.

Referring toFIG. 7, a SER SRAM cell in accordance with yet an alternate embodiment is illustrated generally by numeral700. Load transistors P1and P2are coupled at the source to the power supply VDD. The drain of load transistor P1is coupled to storage node A. The drain of load transistor P2is coupled to storage node B. Load transistor P2is gated by storage node A and load transistor P1is gated by storage node B.

The drain of drive transistor N2is coupled to storage node B. The drain of drive transistor N1is coupled to storage node A. Both drive transistors N1and N2are coupled at the source to ground. Drive transistor N1is driven by storage node C and drive transistor N2is driven by storage node D.

Stabilizer transistor P4is coupled between the power supply and storage node D, and is driven by storage node B. Stabilizer transistor N6is coupled between storage node D and ground, and is driven by storage node C.

Stabilizer transistor P3is coupled between the power supply and storage node C, and is driven by storage node A. Stabilizer transistor N5is coupled between storage node C and ground, and is driven by storage node D.

Storage nodes A and B are coupled to bit-line pair BL and BLB by access transistors N3and N4, respectively.

Similar to the previously described embodiments, the gates of the drive transistors N1and N2are driven by the storage nodes C and D. However, in the present embodiment, the complementary logic voltages at the internal nodes are held very strongly either at logic 1 or logic 0 by cross-coupled stabilizer transistors P3, P4, N5and N6. Accordingly, the load transistors P1and P2and the drive transistors N1and N2are effectively cross coupled via the cross-coupled stabilizer transistors P3, P4, N5and N6.

Such an arrangement provides two strong redundant storage nodes C and D. Consequently, in the event of a particle strike at one of the nodes A, B, C or D, there are three unaffected nodes that can restore the logic state of the affected node. Thus, the SER SRAM cell greatly reduces the likelihood of a SRAM cell experiencing a soft error.

In accordance with another embodiment, the SER cells described above in reference toFIGS. 4-7are used as storage units for providing SER flip-flop circuits. Preferably, the circuit illustrated inFIG. 7is utilized as a storage unit for the flip-flop circuits described below.

Referring generally toFIG. 14, shown is a block diagram of soft error robust (SER) flip-flop in accordance with an embodiment of the invention illustrated generally by numeral1400. As will be discussed,FIGS. 10-12illustrate implementations of the SER flip-flop illustrated inFIG. 14.

As illustrated inFIG. 14, the SER flip-flop1400comprises a transfer unit1410, a storage unit1420, and a buffer unit1430. Each transfer unit1410comprises one or more input nodes for receiving at least one data signal1040and at least one clock signal1050. The transfer unit1410is activated by the one or more clock signals1050to conditionally transfer a sample of the input data1046and a sample of the inverse of the data1044as output to two of the storage nodes of the storage unit1420. As will be understood, the sampled data signal1046and the sampled inverse data signal1044are complementary to one another. As will be described below, the storage unit1420preferably includes two storage nodes for receiving input from the transfer unit1410and two redundant storage nodes for storing a copy of each of the samples1046and1044received.

As illustrated inFIG. 14, each transfer unit1410has two separate data paths from the input data1040to the sampled data1044and1046provided to the storage unit1420. The two data paths comprise a first data path1412for providing the sampled data inverse1044and the sampled data1046in response to receiving the one or more data signals1040and the one or more clock signals1050. As will be described, the two separate data paths, allow the transfer unit1410to be relatively robust against soft errors. That is, if either one of the first and second data paths1412or1414is affected by a soft error, the transfer unit1410remains unaffected. This is because the sampled data1046(also shown as Data_L) and the sampled data inverse1044(also shown as Datab_L) need to be the complement or inverse of one another in order to be stored on the storage unit1420. Thus, the previous value stored on the storage unit1420remains until both the sampled data1046and the sampled data inverse1044are both provided as complementary values to the storage unit1420. It will be appreciated that the clock controlled transfer unit1410is thus SE robust as it masks any propagation of particle induced transients to the storage unit1420.

Once the sampled data1046and the sampled data inverse1044are received by the storage unit1420, these samples are preserved in the storage unit1420on a plurality of nodes (e.g. nodes A′-D′ as described below) such that there is a redundant node for each sample. Thus, in the event of particle strike at a node, there are three unaffected nodes that can restore the logic voltage of the affected node. Consequently, the storage unit1420does not experience a SE. Finally, the buffer unit1430is driven by a node of the SE immune storage unit1420, and thus keeps the output of the flip-flop1048immune to SE.

Referring toFIG. 10, a schematic of a soft-error robust flip-flop (SER-FF) in accordance with an embodiment of the flip-flop1400is illustrated generally by the numeral1000. The transfer unit1410acomprises a stack of NMOS and PMOS transistors for receiving the one or more data signals (a data signal1040aand an inverse data signal1040b) and the plurality of clock signals1050. As described earlier, the transfer unit1410athen provides the sampled data signal1046and its inverse1044to the storage unit1420in response to the clock signals1050.

Referring toFIG. 10, the input data1040ais processed by a first data path1412aand the input data complement signal1040bis processed by a second data path1414a. The transfer unit1410aprovides an additional data path (the second data path1414a) for receiving the complementary data signal Datab1040bas input. The additional datapath is provided in parallel to the first data path having data1040aas its input. Preferably, according to the present embodiment, the transistors of the first data path1412aare placed at a predetermined distance from the transistors of the second data path1414aon the flip-flop1000. In this way, only one of the first and second data paths1412a,1414ais sensitive to soft errors and the overall transfer unit1410aremains SER.

In the present embodiment, the plurality of clock signals1050comprises a plurality of phase shifted clock signals. Specifically, the plurality of clock signals1050comprises a first clock (Clk) signal, and three other clock signals Clkb, Clkbd, and Clkd, which are generated from the first clock Clk signal using an inverter chain illustrated inFIG. 10. At the falling edge of the first clock signal (e.g. when Clk goes from 1 to 0), Clk, Clkb, Clkbd, and Clkd generate a pulse of narrow time window during which a sample of the input data1040aand its inverse1040b(Datab) passes to the storage unit1420as sampled inverse data Datab_L1044and sampled data Data_L1046, respectively. Accordingly, it is only during this narrow time window where both the sampled input data1046and the sampled inverse data1044are transferred to the storage unit1420. At all other times, the output of the transfer unit1410ais tri-stated and thus remains robust against soft error (SE).

Accordingly, the transfer unit1410ais operational through a small timing window (provided by the plurality of clock signals1050) that samples the input data1040aas well as its complement1040b. As described, this timing window is implemented by combining different phases of a clock signal. The FF1000updates its output1048according to the input data (e.g.1040aand1040b) on the falling edge of the clock Clk signal, and thus is a negative edge triggered FF1000. Thus, the storage unit1420can indefinitely retain the data in its storage nodes (e.g. nodes A′-D′) if the flip-flop1000is powered and there is no activity on the clock input (e.g.1050).

The storage unit1420illustrated inFIGS. 10-12comprises eight NMOS and PMOS transistors and four storage nodes: A′, B′, C′, and D′. The transistors in the storage unit1420are connected in such a way that stable logical values at nodes A′, B′, C′, D′ can only be either (0, 1, 0, 1) or (1, 0, 1, 0), respectively. Thus, for every node, there is a redundant node (e.g. C′ is the redundant node to A′ and B′ is the redundant node to D′). In the event of particle strike at a node, the redundant node coupled with two other unaffected nodes restores the logic state of the affected node. Thus, the storage unit1420and hence the logic states at the sampled data inverse1044Datab_L and the sampled data1046Data_L never experience an SE. Finally, referring toFIGS. 10-12, since the buffer unit1430is a simple inverter, which is driven by the value of the input sampled data inverse1044Datab_L signal to drive the output, the output1048also becomes SE immune.

Referring toFIG. 11, a circuit schematic of an SER-FF in accordance with an alternate embodiment of the flip-flop1400is illustrated generally by numeral1100. The SER flip flop1100is similar to the SER flip flop1000. However, in the present embodiment, the transfer unit1410bis provided by a multiple stage, single phase clock controlled inverters placed in two parallel paths. The transfer unit1410aprovides two separate data paths (1412band1414b) for resulting in SER flip-flops. In the illustrated embodiment, the transfer unit1410bcomprises the first path1412band the second parallel path1414badapted to generate a sample of the input data signal Data_L1046and a sample of the inverted data signal1044Datab_L.

As illustrated inFIG. 11, the first and second paths (1412band1414b) are inverters controlled by a single phase clock Clk signal1050. The first path1412bgenerates the sampled inverted data signal Datab_L1044using three clock-controlled stages with the same single phase clock signal1050. The first path1412breceives the input data signal1040and the clock signal1050at its input and is coupled at the output to one of the nodes of the storage unit1420(e.g. node B′). The second path1414breceives the input data signal1040and the clock signal1050at its input and is coupled at the output to another node of the storage unit (e.g. C′).

The first stage of the first path1412bcomprises two PMOS transistors (P1, P2) and one NMOS transistor (N1). While each of second and third stages comprises two NMOS transistors (N2, N3; N4, N5) and one PMOS transistor (P3; P4). The first stage is coupled between VDD and ground.

As described earlier, the second path1414balso comprises two stage single phase clock controlled inverters to generate the sampled data signal1046Data_L. The second path1414bis also driven by the same single phase clock signal1050and the data signal1040. The second path1414bis coupled between VDD and ground.

The organization of the transistors and their control by the clock signal Clk1050and the data signal1050provides the transfer unit1410bwith robustness against SE. That is, the redundancy provided by the two parallel data paths1412band1414bdriven by the same clock signal1050which independently provide an output data sample1046and its complementary data sample1044improve the reliability of the transfer unit1410b.

The storage unit1420and the buffer unit1430of the flip-flop1100are the same as those in the SER-FF1000and are SE robust for the reasons described above. It will be appreciated that the difference between the transfer unit1410band transfer unit1410ais that the transfer unit1410b(and thus the SER FF1100) samples the input data at the rising edge of the clock signal Clk1050.

Referring toFIG. 12, there is illustrated a circuit schematic of an SER-FF in accordance with yet another alternate embodiment of the flip-flop1400and shown generally by numeral1200. Unlike the SER-FF1100, the SER-FF1200configuration uses a two phase clock (Clk and Clkb) and the clocked CMOS logic to generate each of the sampled data signal Data_L1046and the sampled inverse data signal Datab_L1044through two parallel paths1412cand1414c. The transfer unit1410cincludes two parallel data paths (1412cand1414c) for providing an SE robust flip-flop. The first path1412cgenerates the sampled data Data_L1046signal using two clocked CMOS inverter stages, each of which consists of two PMOS transistors (P1, P2; P3, P4) and two NMOS transistors (N1, N2; N3, N4). The second path1414cgenerates the sampled data inverse Datab_L1044signal using one of such inverter stages.

As illustrated inFIG. 12, the first path1412chas its input coupled to the data signal1040and complementary clock signals1050(Clk and Clkb). The output of the first path1412cis coupled to one of the nodes of the storage unit (e.g. node C′). Further, the second path1414chas its input coupled to the data signal1040, complementary clock signals1050(Clk and Clkb). The output of the second path is coupled to another one of the nodes of the storage unit (e.g. node B′).

Since each of the nodes in the transfer unit1410cis controlled by the clock signals Clk or Clkb and the input data signal1040, the transfer unit1410cexhibits robustness against SE. As described earlier in reference toFIGS. 10 and 11, the first and second parallel paths1412cand1414care independent of one another and provide a redundancy such that if one of the paths is affected by a soft error, the output from the affected path is not stored onto the storage unit1420.

For the reasons described earlier, the storage unit1420and buffer unit1430are also SE robust.

FIG. 13shows a generalized implementation of digital logic which comprises sequential logic gates that provide memory such as flip-flops as well as combinational logic gates. The memory state illustrated inFIG. 13may refer to any one of the flip-flops1000,1100,1200discussed earlier. Therefore, it will be appreciated that using any one of the flip-flops1000,1100,1200one may realize an SE robust digital logic.

Accordingly, it will be appreciated by a person of ordinary skill in the art that the present invention provides improved robustness for flip-flop circuits in the face of soft errors. Further, although the invention has been described with reference to certain specific embodiments, various modifications thereof will be apparent to those skilled in the art without departing from the scope of the invention as defined by the appended claims.