Resistive element and method of manufacturing the same

A resistive element includes: a semiconductor substrate; a field insulating film deposited on the semiconductor substrate; a plurality of resistive layers separately deposited on the field insulating film; an interlayer insulating film deposited to cover the field insulating film and the resistive layers; a pad-forming electrode deposited on the interlayer insulating film, and electrically connected to one edges of the resistive layers; a relay wire deposited on the interlayer insulating film separately from the pad-forming electrode, and including a first terminal electrically connected to another edges of the resistive layers and a second terminal provided so as to form an ohmic contact to the semiconductor substrate; and a rear surface electrode provided under the semiconductor substrate to form an ohmic contact to the semiconductor substrate, wherein the resistive element uses, as a resistor, an electric channel between the pad-forming electrode and the rear surface electrode.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims benefit of priority under 35 USC 119 based on Japanese Patent Application No. 2019-110579 filed on Jun. 13, 2019, the entire contents of which are incorporated by reference herein.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a resistive element used as a gate resistive element of a switching element, and a method of manufacturing the resistive element.

2. Description of the Related Art

JP H08-306861 A discloses a resistive element used for a semiconductor device such as a semiconductor integrated circuit (IC), and including a silicon substrate, an insulating layer deposited on the silicon substrate, and a resistive layer of a thin film deposited on the insulating layer. The resistive element disclosed in JP H08-306861 A further includes two electrodes at side edges opposed to each other in the resistive layer, and aluminum thin wires bonded to the two electrodes.

The resistive element disclosed in JP H08-306861 A is provided with the two electrodes present on the top surface of the resistive layer and connected to the side edges opposed to each other. This structure inevitably increases the chip size and requires the two bonding wires connected to the two electrodes.

SUMMARY OF THE INVENTION

In view of the foregoing problems, the present invention provides a resistive element with a chip size reduced and the number of bonding wires decreased, and a method of manufacturing the resistive element.

An aspect of the present invention inheres in a resistive element including: a semiconductor substrate; a field insulating film deposited on the semiconductor substrate; a plurality of resistive layers separately deposited on the field insulating film; an interlayer insulating film deposited to cover the field insulating film and the plurality of resistive layers; a pad-forming electrode deposited on the interlayer insulating film, and electrically connected to one edge of at least one resistive layer selected from the plurality of resistive layers; a relay wire deposited on the interlayer insulating film separately from the pad-forming electrode, and including a first terminal electrically connected to another edge of the selected resistive layer and a second terminal provided so as to form an ohmic contact to the semiconductor substrate; and a rear surface electrode provided under the semiconductor substrate to form an ohmic contact to the semiconductor substrate, wherein the resistive element uses, as a resistor, an electric channel between the pad-forming electrode and the rear surface electrode.

Another aspect of the present invention inheres in a method of manufacturing a resistive element, including: depositing a field insulating film on a semiconductor substrate; depositing a plurality of resistive layers on the field insulating film; depositing an interlayer insulating film to cover the field insulating film and the plurality of resistive layers; forming, in the interlayer insulating film, a first contact hole on which one edge of one resistive layer selected from the plurality of resistive layers is exposed, a second contact hole on which another edge of the selected resistive layer is exposed at position separated from the first contact hole, and a third contact hole on which a top surface of the semiconductor substrate is partly exposed at position separated from the first and second contact holes; forming a pad-forming electrode electrically connected to the one edge of the selected resistive layer via the first contact hole, and a relay wire electrically connected to another edge of the selected resistive layer via the second contact hole to form an ohmic contact to the semiconductor substrate via the third contact hole; and forming a rear surface electrode under the semiconductor substrate, wherein the resistive element uses, as a resistor, an electric channel between the at least one pad-forming electrode and the rear surface electrode.

DETAILED DESCRIPTION

With reference to the Drawings, embodiments and modified examples of the present invention will be described below. In the Drawings, the same or similar elements are indicated by the same or similar reference numerals. The Drawings are schematic, and it should be noted that the relationship between thickness and planer dimensions, the thickness proportion of each layer, and the like are different from real ones. Accordingly, specific thicknesses or dimensions should be determined with reference to the following description. Moreover, in some drawings, portions are illustrated with different dimensional relationships and proportions. The embodiments described below merely illustrate schematically devices and methods for specifying and giving shapes to the technical idea of the present invention, and the span of the technical idea is not limited to materials, shapes, structures, and relative positions of elements described herein. Further, definitions of directions such as an up-and-down direction in the following description are merely definitions for convenience of understanding, and are not intended to limit the technical ideas of the present invention. For example, as a matter of course, when the subject is observed while being rotated by 90°, the subject is understood by converting the up-and-down direction into the right-and-left direction. When the subject is observed while being rotated by 180°, the subject is understood by inverting the up-and-down direction. When the subject is observed while being rotated by 180°, the definitions of “front” and “back” are reversed.

EMBODIMENT

A resistive element according to an embodiment of the present invention has a rectangular planar pattern surrounded by the first to fourth sides, as illustrated inFIG. 1. The resistive element according to the embodiment has a chip size of about 3×3 millimeters, for example, which may be determined as appropriate. While the chip illustrated inFIG. 1has a rectangular shape, the chip of the resistive element according to the embodiment is not limited to this shape. The resistive element according to the embodiment includes, along the circumference of the chip having the shape illustrated inFIG. 1, a first resistive layer31aarranged on the first side, a second resistive layer31barranged on the second side, a third resistive layer31carranged on the third side, and a fourth resistive layer31darranged on the fourth side. As used herein, the names of the elements “first resistive layer31a” to “fourth resistive layer31d” are indicated by the ordinal numerals for illustration purposes, and the first resistive layer31ato the fourth resistive layer31dcan be collectively referred to as “a plurality of resistive layers”.

The resistive element according to the embodiment of the present invention includes, in a cross-sectional structure as illustrated inFIG. 2, a semiconductor substrate1having a low specific resistivity, a field insulating film (a first insulating film)2deposited on the semiconductor substrate1, and the first resistive layer31aand the third resistive layer31cof thin films deposited on the field insulating film2. Although not illustrated in the cross-sectional view ofFIG. 2, the second resistive layer31band the fourth resistive layer31dillustrated inFIG. 1are also deposited on the field insulating film2in the same manner as the first resistive layer31aand the third resistive layer31cillustrated inFIG. 2.

The semiconductor substrate1has a thickness of about 350 micrometers, for example. The semiconductor substrate1may be a substrate, such as a silicon substrate, having a low specific resistivity and doped with n-type impurity ions at a high concentration. The content of a resistive component of the semiconductor substrate1is preferably decreased to a level which can be ignored with respect to a resistive component of the first resistive layer31ato the fourth resistive layer31d. In particular, the content of the resistive component of the semiconductor substrate1is preferably about one hundredth or less of that of the first resistive layer31ato the fourth resistive layer31d. The specific resistivity of the semiconductor substrate1may be set in a range of about 2 to 60 mΩ·cm. Alternatively, the semiconductor substrate1used may be a silicon substrate doped with p-type impurity ions at a high concentration, or a semiconductor substrate made of material other than silicon.

The field insulating film2has a thickness of about 800 nanometers, for example. Increasing the thickness of the field insulating film2can reduce a parasitic capacitance. The field insulating film2may be a silicon oxide film (a SiO2film), a silicon nitride film (a Si3N4film), or a composite film of these films. The field insulating film2may also be an insulating film (a TEOS film) obtained by a chemical vapor deposition (CVD) method using tetraethoxysilane (TEOS) gas of an organic silicon compound.

As illustrated inFIG. 1, the first resistive layer31ato the fourth resistive layer31dhave a rectangular planar pattern. The first resistive layer31ato the fourth resistive layer31dhave a thickness of about 500 nanometers, and a sheet resistance of about 150 Ω/sq, for example. The first resistive layer31ato the fourth resistive layer31dmay each be a doped polysilicon (DOPOS) layer of n-type, for example. The n-type DOPOS layer can be obtained such that n-type impurity ions such as phosphorus (P) are implanted in polycrystalline silicon (polysilicon), or such that n-type impurity ions are doped in polycrystalline silicon upon the deposition with a CVD device. A resistance value of the first resistive layer31ato the fourth resistive layer31dcan be regulated such that a width W1and a length L1of the first resistive layer31ato the fourth resistive layer31dare adjusted. The resistance value of the first resistive layer31ato the fourth resistive layer31dcan also be regulated, when using the DOPOS layer, such that the amount of impurity ions doped to the polysilicon is adjusted.

The first resistive layer31ato the fourth resistive layer31dpreferably have a temperature coefficient of zero ppm/° C. or lower, namely, the first resistive layer31ato the fourth resistive layer31dpreferably have a temperature coefficient of zero or a negative number. The temperature coefficient set as described above can avoid an increase in the resistance value during operation at a high temperature. When the resistive element according to the embodiment is used as a gate resistive element of an insulated gate bipolar transistor (IGBT), for example, a loss of the IGBT when turned on can be suppressed. The temperature coefficient of the DOPOS can be regulated such that a dose of impurity ions implanted in the polysilicon is adjusted. For example, when the dose is set to about 7.0×1015cm−2or less, the temperature coefficient of the DOPOS can be set to zero ppm/° C. or lower. The temperature coefficient of the first resistive layer31ato the fourth resistive layer31dis not intended to be limited to zero ppm/° C. or lower. The first resistive layer31ato the fourth resistive layer31dmay have a temperature coefficient of a positive number.

The first resistive layer31ato the fourth resistive layer31dmay be a DOPOS layer of p-type. The p-type DOPOS layer can also be obtained such that p-type impurity ions such as boron (B) are implanted in polysilicon, for example. The first resistive layer31ato the fourth resistive layer31dare not limited to the DOPOS layer, and may be a nitride film of transition metal such as tantalum nitride (TaNx), or a stacked metallic film including a chromium (Cr) film, a nickel (Ni) film, and a manganese (Mn) film stacked in this order and having a high melting point. Alternatively, the first resistive layer31ato the fourth resistive layer31dmay each be a thin film of silver-palladium (AgPd) or ruthenium oxide (RuO2). Alternatively, the first resistive layer31ato the fourth resistive layer31dmay be implemented by p-type diffusion layers or n-type diffusion layers deposited on the semiconductor surface, which differ from the structure illustrated inFIG. 1andFIG. 2.

As illustrated on the left side inFIG. 1, a first dummy layer32aand a second dummy layer32bare arranged separately from the first resistive layer31aon the first side of the square shape to interpose the first resistive layer31a. As illustrated on the upper side inFIG. 1, a third dummy layer32cand a fourth dummy layer32dare arranged separately from the second resistive layer31bon the second side of the square shape to interpose the second resistive layer31b. As illustrated on the right side inFIG. 1, a fifth dummy layer32eand a sixth dummy layer32fare arranged separately from the third resistive layer31con the third side to interpose the third resistive layer31c. As illustrated on the lower side inFIG. 1, a seventh dummy layer32gand an eighth dummy layer32hare arranged separately from the fourth resistive layer31don the fourth side to interpose the fourth resistive layer31d. As used herein, the names of the elements “first dummy layer32a” to “eighth dummy layer32h” are indicated by the ordinal numerals for illustration purposes, and the first dummy layer32ato the eighth dummy layer32hcan be collectively referred to as “a plurality of dummy layers”.

The first dummy layer32ato the eighth dummy layer32hinclude the same material as the first resistive layer31ato the fourth resistive layer31dsuch as the n-type DOPOS, and have the same thickness as the first resistive layer31ato the fourth resistive layer31d. The first dummy layer32ato the eighth dummy layer32hmay have the same width W1and the length L1as the first resistive layer31ato the fourth resistive layer31d, or may have a different width and length. The first dummy layer32ato the eighth dummy layer32hare not necessarily provided.

Although not illustrated inFIG. 1, an interlayer insulating film (a second insulating film)4is deposited to cover the field insulating film2and the first resistive layer31ato the fourth resistive layer31d, as illustrated inFIG. 2. The interlayer insulating film4has a thickness of about 1,500 nanometers, for example. The interlayer insulating film4may be a silicon oxide film (a SiO2film) without containing phosphorus (P) or boron (B) which is typically referred to as a non-doped silicate glass (NSG) film, a phosphosilicate glass film (a PSG film), a borosilicate glass film (a BSG film), a single-layer film of a borophosphosilicate glass film (a BPSG film) or a silicon nitride (Si3N4) film, or a composite film of any of the above films combined together. For example, the interlayer insulating film4may be a composite film including a NSG film with a thickness of about 770 nanometers and a PSG film with a thickness of about 650 nanometers stacked together. The NSG film is presumed to decrease a variation in resistance. The PSG film is presumed to ensure the strength of the wire bonding.

A pad-forming electrode51is allocated above the field insulating film2, as illustrated inFIG. 2. The pad-forming electrode51has a rectangular planar pattern as illustrated inFIG. 1. The center O of the pad-forming electrode51in the rectangular planar pattern is common to the center of the chip. As illustrated inFIG. 1andFIG. 2, the left edge portion of the pad-forming electrode51overlaps with one edge on the right side of the first resistive layer31ain the depth direction. The pad-forming electrode51is connected to the one edge of the first resistive layer31avia first electrode contact regions61a.

As illustrated inFIG. 1, the upper edge portion of the pad-forming electrode51overlaps with one edge of the second resistive layer31bin the depth direction. The pad-forming electrode51is connected to the one edge of the second resistive layer31bvia second electrode contact regions61b. As illustrated inFIG. 1andFIG. 2, the right edge portion of the pad-forming electrode51overlaps with one edge on the left side of the third resistive layer31cin the depth direction. The pad-forming electrode51is connected to the one edge of the third resistive layer31cvia third electrode contact regions61c. As illustrated inFIG. 1, the lower edge portion of the pad-forming electrode51overlaps with one edge of the fourth resistive layer31din the depth direction. The pad-forming electrode51is connected to the one edge of the fourth resistive layer31dvia fourth electrode contact regions61d.

As illustrated inFIG. 1andFIG. 2, a first relay wire52a, a second relay wire52b, a third relay wire52c, and a fourth relay wire52dare deposited on the interlayer insulating film4to separately surround the pad-forming electrode (the front surface electrode)51located in the middle. As illustrated inFIG. 1, the first relay wire52ais arranged on the first side of the rectangular shape. The second relay wire52bis arranged on the second side of the rectangular shape. The third relay wire52cis arranged on the third side of the rectangular shape. The fourth relay wire52dis arranged on the fourth side of the rectangular shape. As used herein, the names of the elements “first relay wire52a” to “fourth relay wire52d” are indicated by the ordinal numerals for illustration purposes, and the first relay wire52ato the fourth relay wire52dcan be collectively referred to as “a plurality of relay wires”.

The planar pattern including the pad-forming electrode51, the first resistive layer31ato the fourth resistive layer31d, and the first relay wire52ato the fourth relay wire52dhas four-fold rotational symmetry about the center O of the chip. This arrangement allows the resistive element according to the embodiment to be turned by 90 or 180 degrees upon packaging, so as to facilitate the process of assembly.

As illustrated inFIG. 2, the right edge portion of the first relay wire52aoverlaps with the other edge of the first resistive layer31ain the depth direction. A resistive layer connection terminal, which is one edge (a first edge portion) of the first relay wire52a, is in contact with the other edge of the first resistive layer31avia first wire contact regions62a. The left edge portion of the third relay wire52coverlaps with the other edge of the third resistive layer31cin the depth direction. A resistive layer connection terminal, which is one edge (a first edge portion) of the third relay wire52c, is in contact with the other edge of the third resistive layer31cvia third wire contact regions62c.

Although not illustrated, the edge portion of the second relay wire52boverlaps with the other edge of the second resistive layer31bin the depth direction on the back side of the sheet ofFIG. 2. A resistive layer connection terminal, which is one edge (a first edge portion) of the second relay wire52b, is in contact with the other edge of the second resistive layer31bvia second wire contact regions62b. The edge portion of the fourth relay wire52doverlaps with the other edge of the fourth resistive layer31din the depth direction on the front side of the sheet ofFIG. 2. A resistive layer connection terminal, which is one edge (a first edge portion) of the fourth relay wire52d, is in contact with the other edge of the fourth resistive layer31dvia fourth wire contact regions62d.

As illustrated inFIG. 1andFIG. 2, a substrate connection terminal, which is the other edge (a second edge portion) of each of the first relay wire52ato the fourth relay wire52d, forms an ohmic contact to the semiconductor substrate1at a low contact resistance via first substrate contact regions63ato fourth substrate contact regions63d. Contact regions having the same conductivity type as the semiconductor substrate1and having a higher impurity concentration (a lower specific resistivity) than the semiconductor substrate1may be provided in the upper portion of the semiconductor substrate1at the contact positions between the semiconductor substrate1and each of the first substrate contact regions63ato the fourth substrate contact regions63d.

The pad-forming electrode51and the first relay wire52ato the fourth relay wire52dhave a thickness of about three micrometers, for example. The pad-forming electrode51and the first relay wire52ato the fourth relay wire52dmay be a stacked film including a titanium/titanium nitride (Ti/TiN) film with a thickness of about 120 nanometers serving as barrier metal, an aluminum-silicon (Al—Si) film with a thickness of about three micrometers, and a TiN/Ti film with a thickness of about 45 nanometers serving as a reflection preventing film. Instead of Al—Si, Al or an Al alloy such as Al—Cu—Si or Al—Cu may be used. The pad-forming electrode51is connected with a bonding wire (not illustrated) having a diameter of about 300 micrometers made of metal such as aluminum (Al).

Although not illustrated inFIG. 1, a guard ring layer53is arranged on the interlayer insulating film4, as illustrated inFIG. 2. The guard ring layer53is delineated into a ring shape along the outer periphery of the chip of the resistive element according to the embodiment. The guard ring layer53is in contact with the semiconductor substrate1via peripheral contact regions64aand64b. The guard ring layer53includes the same material as the pad-forming electrode51and the first relay wire52ato the fourth relay wire52d. The guard ring layer53can prevent moisture from entering from the side surface of the chip.

As illustrated inFIG. 2, a passivation insulating film (a third insulating film: a passivation film)7is laminated on the pad-forming electrode51, the first relay wire52ato the fourth relay wire52dand the guard ring layer53. The passivation insulating film7may be a composite film including a TEOS film, a Si3N4film, and a polyimide film stacked in this order. The passivation insulating film7is provided with an opening7a.FIG. 1indicates only the opening7aby the dash-dotted line while omitting the illustration of the passivation insulating film7. The part of the pad-forming electrode51exposed on the opening7aserves as a pad region to be connected with the bonding wire.

As illustrated inFIG. 2, a rear surface electrode (a counter electrode)9is provided on the bottom surface of the semiconductor substrate1. The rear surface electrode9may be a single film made of gold (Au), or a metallic film including a titanium (Ti) film, a nickel (Ni) film, and a gold (Au) film stacked in this order. The outermost layer of the rear surface electrode9may be made of material which can be soldered. The rear surface electrode9is fixed to a metal plate (not shown) by soldering, for example. The resistive element according to the embodiment includes the four resistive layers of the first resistive layer31ato the fourth resistive layer31dconnected in parallel between the pad-forming electrode51and the rear surface electrode9so as to implement a vertical resistive element having electric channels serving as resistors between the pad-forming electrode51and the rear surface electrode9.

The resistive element according to the embodiment including the four resistive layers can selectively use the first resistive layer31ato the fourth resistive layer31dsuch that the presence or absence of each of the first electrode contact regions61ato the fourth electrode contact regions61d, the first wire contact regions62ato the fourth wire contact regions62d, and the first substrate contact regions63ato the fourth substrate contact regions63dis determined. For example, when the first resistive layer31ais chosen from the first resistive layer31ato the fourth resistive layer31dto be used, at least the first electrode contact regions61a, the first wire contact regions62a, and the first substrate contact regions63aare only required to be provided, each being chosen from the first electrode contact regions61ato the fourth electrode contact regions61d, the first wire contact regions62ato the fourth wire contact regions62d, and the first substrate contact regions63ato the fourth substrate contact regions63d.

When the first resistive layer31ato the fourth resistive layer31deach have a resistance value of 120Ω, and one of the first resistive layer31ato the fourth resistive layer31dis connected, the resistive element according to the embodiment has a resistance value of 120Ω. When three of the first resistive layer31ato the fourth resistive layer31dare connected in parallel, the resistive element according to the embodiment has a resistance value of 40Ω. When two of the first resistive layer31ato the fourth resistive layer31dare connected in parallel, the resistive element according to the embodiment has a resistance value of 60Ω. When all of the first resistive layer31ato the fourth resistive layer31dare connected in parallel as illustrated inFIG. 1andFIG. 2, the resistive element according to the embodiment has a resistance value of 30Ω. The increase/decrease in the number of the first resistive layer31ato the fourth resistive layer31dconnected in parallel thus can regulate the resistance value of the resistive element according to the embodiment.

The resistive element according to the embodiment can be used for an inverter module100for driving a three-phase motor having a u-phase, a v-phase, and a w-phase, for example, as illustrated inFIG. 3. The inverter module100includes a first main element TR1, a second main element TR2, a third main element TR3, and a fourth main element TR4for driving the u-phase. The inverter module100also includes a fifth main element TR5, a sixth main element TR6, a seventh main element TR7, and an eighth main element TR8for driving the v-phase, and a ninth main element TR9, a tenth main element TR10, an eleventh main element TR11, and a twelfth main element TR12for driving the w-phase. The first main element TR1to the twelfth main element TR12are each connected to a freewheeling diode (not shown). The first main element TR1to the twelfth main element TR12may each be an IGBT. The gate electrodes of the IGBTs are connected with a first gate resistive element R1to a twelfth gate resistive element R12so as to avoid an oscillation phenomenon during the switching operation.

The resistive element according to the embodiment can be used as each of the first gate resistive element R1to the twelfth gate resistive element R12. For example, when the resistive element according to the embodiment is used as the first gate resistive element R1, the terminal on the side on which the gate resistive element R1is connected to the gate electrode of the first main electrode TR1corresponds to the terminal toward the pad-forming electrode51illustrated inFIG. 1andFIG. 2. The other terminal on the side opposite to the side on which the gate resistive element R1is connected to the gate electrode of the first main electrode TR1corresponds to the terminal toward the rear surface electrode9illustrated inFIG. 2.

The resistive element according to the embodiment includes the four resistive layers of the first resistive layer31ato the fourth resistive layer31dconnected in parallel between the pad-forming electrode51and the rear surface electrode9so as to implement the vertical resistive element having electric channels serving as resistors between the pad-forming electrode51and the rear surface electrode9. The resistive element according to the embodiment includes a single pad region implemented by the top surface of the pad-forming electrode51connected with the first resistive layer31ato the fourth resistive layer31d, and thus only requires a single bonding wire, so as to decrease the total number of the bonding wires, as compared with a lateral resistive element. Further, the area of the pad region on the top surface side can be decreased as compared with a lateral resistive element, decreasing the size of the chip accordingly.

The resistive element according to the embodiment can selectively use any of or all of the first resistive layer31ato the fourth resistive layer31dsuch that the presence or absence of each of the first electrode contact regions61ato the fourth electrode contact regions61d, the first wire contact regions62ato the fourth wire contact regions62d, and the first substrate contact regions63ato the fourth substrate contact regions63dis determined. Determining the number of the first resistive layer31ato the fourth resistive layer31dconnected in parallel as appropriate depending on the purpose of the resistive element according to the embodiment, can regulate the resistance value of the resistive element according to the embodiment.

Method of Manufacturing Resistive Element

A method of manufacturing the resistive element according to the embodiment of the present invention is illustrated below with reference toFIG. 4toFIG. 13. It should be understood that the method of manufacturing the resistive element is an example, and the embodiment can be implemented by various manufacturing methods other than the following method including modified examples within the scope of the invention as defined by the appended claims.

First, the semiconductor substrate1such as a silicon substrate doped with n-type impurity ions at a high concentration is prepared. As illustrated inFIG. 4, the field insulating film2such as a TEOS film is deposited on the semiconductor substrate1by a low-pressure CVD (LPCVD) method, for example. The field insulating film2may be a composite film including a thermal oxide film formed by a thermal oxidation method and an insulating film further deposited on the thermal oxide film by a CVD method so as to be stacked together.

A photoresist film is then coated on the top surface of the field insulating film2, and is delineated by photolithography. Using the delineated photoresist film as an etching mask, a part of the field insulating film2is selectively removed by dry etching such as reactive ion etching (RIE). The photoresist film is then removed, so as to partly provide the pattern of the field insulating film2on the top surface of the semiconductor substrate1, as illustrated inFIG. 5.

Next, a non-doped polysilicon layer is formed on the semiconductor substrate1and the field insulating film2by a CVD method, for example. N-type impurity ions such as phosphorus (P) are implanted in the polysilicon layer. For example, the phosphorus (P) impurity ions are implanted under the conditions of an acceleration voltage of 80 keV and a dose of about 6.0×1015cm−2or less. The impurity ions implanted are activated by annealing, so as to form the DOPOS layer3doped with the n-type impurity ions at a high concentration on the top surface, as illustrated inFIG. 6.

A photoresist film is then coated on the top surface of the DOPOS film3, and is delineated by photolithography. Using the delineated photoresist film as an etching mask, a part of the DOPOS layer3is selectively removed by RIE, for example. The photoresist film is then removed, so as to form the first resistive layer31aand the third resistive layer3con the field insulating film2, as illustrated inFIG. 7. At the same time, the second resistive layer31band the fourth resistive layer31dillustrated inFIG. 1are also formed on the field insulating film2.

Next, as illustrated inFIG. 8, the interlayer insulating film4is deposited to cover the field insulating film2and the first resistive layer31ato the fourth resistive layer31d. The interlayer insulating film4may be made of a composite film including a NSG film and a PSG film sequentially stacked by a CVD method, for example.

A photoresist film is then coated on the interlayer insulating film4, and is delineated by photolithography. Using the delineated photoresist film as an etching mask, a part of the interlayer insulating film4is selectively removed by RIE, for example. The photoresist film is then removed, so as to open first pad contact holes4aand third pad contact holes4bin the interlayer insulating film4, as illustrated inFIG. 9. Although not illustrated, the interlayer insulating film4is simultaneously provided with second pad contact holes open on the back side of the sheet ofFIG. 9and fourth pad contact holes open on the front side of the sheet ofFIG. 9. As used herein, the first to fourth pad contact holes are correctively referred to as “first contact holes”.

At the same time, first inner relay contact holes4cand third inner relay contact holes4dare provided together with the first contact holes. Although not illustrated, the interlayer insulating film4is simultaneously provided with second inner relay contact holes open on the back side of the sheet ofFIG. 9and fourth inner relay contact holes open on the front side of the sheet ofFIG. 9. As used herein, the first to fourth inner relay contact holes are correctively referred to as “second contact holes”.

At the same time, first outer relay contact holes4eand third outer relay contact holes4fare provided together with the first and second contact holes. Although not illustrated, the interlayer insulating film4is simultaneously provided with second outer relay contact holes open on the back side of the sheet ofFIG. 9and fourth outer relay contact holes open on the front side of the sheet ofFIG. 9. As used herein, the first to fourth outer relay contact holes are correctively referred to as “third contact holes”. Further, guard ring contact holes4gand4hare open together with the first to third contact holes.

Next, as illustrated inFIG. 10, the metallic film5is deposited on the interlayer insulating film4to fill the first pad contact holes4a, the third pad contact holes4b, the first inner relay contact holes4c, the third inner relay contact holes4d, the first outer relay contact holes4e, the third outer relay contact holes4f, and the guard ring contact holes4gand4hby vacuum evaporation or sputtering, for example. The metallic film5may be made of a Ti/TiN film, an Al—Si film, and a TiN/Ti film sequentially stacked by a CVD method, for example.

A photoresist film is then coated on the metallic film5, and is delineated by photolithography. Using the delineated photoresist film as an etching mask, a part of the metallic film5is selectively removed, so as to provide the patterns of the pad-forming electrode51, the first relay wire52ato the fourth relay wire52d, and the guard ring layer53separated from each other on the interlayer insulating film4, as illustrated inFIG. 11.

At the same time, the first electrode contact regions61aburied in the first pad contact holes4aare formed to be in contact with the first resistive layer31a, and the third electrode contact regions61cburied in the third pad contact holes4bare formed to be in contact with the third resistive layer31c. The pad-forming electrode51and the first resistive layer31aare thus connected via the first electrode contact regions61a, and the pad-forming electrode51and the third resistive layer31care connected via the third electrode contact regions61c. Although not illustrated, the second electrode contact regions connecting the pad-forming electrode51to the second resistive layer31bvia the second pad contact holes are formed on the back side of the sheet ofFIG. 11. The fourth electrode contact regions connecting the pad-forming electrode51to the fourth resistive layer31dvia the fourth pad contact holes are formed on the front side of the sheet ofFIG. 11.

Further, the first wire contact regions62aburied in the first inner relay contact holes4care formed to be in contact with the first resistive layer31atogether with the formation of the pattern of the first relay wire52a. The first substrate contact regions63aburied in the first outer relay contact holes4eare formed to be in contact with the semiconductor substrate1. The third wire contact regions62cburied in the third inner relay contact holes4dare formed to be in contact with the third resistive layer31c. The third substrate contact regions63cburied in the third outer relay contact holes4fare formed to be in contact with the semiconductor substrate1.

Although not illustrated, the second wire contact regions connecting the second resistive layer31bto the second relay wire52bvia the second inner relay contact holes, and the second substrate contact regions connecting the second relay wire52bto the semiconductor substrate1via the second outer relay contact holes are formed on the back side of the sheet ofFIG. 11. The fourth wire contact regions connecting the fourth resistive layer31dto the fourth relay wire52dvia the fourth inner relay contact holes, and the fourth substrate contact regions connecting the fourth relay wire52dto the semiconductor substrate1via the fourth outer relay contact holes are formed on the front side of the sheet ofFIG. 11.

Further, the peripheral contact regions64aand64bburied in the guard ring contact holes4gand4hare formed to be in contact with the semiconductor substrate1.

Next, as illustrated inFIG. 12, the passivation film7is formed on the pad-forming electrode51, the first relay wire52ato the fourth relay wire52d, and the guard ring layer53. For example, the passivation film7including a TEOS film, a Si3N4film, and a polyimide film is formed such that the TEOS film and the Si3N4film are sequentially stacked, and the polyimide film is further coated on the stacked film by a plasma CVD method or the like.

A photoresist film is then coated on the passivation film7, and is delineated by photolithography. Using the delineated photoresist film as an etching mask, a part of the passivation film7is selectively removed, so as to provide the opening7ain the passivation film7, as illustrated inFIG. 13. The part of the pad-forming electrode51is exposed on the opening7aso as to serve the pad region.

Next, the bottom surface of the semiconductor substrate1is polished by chemical mechanical polishing (CMP) so as to decrease the thickness of the semiconductor substrate1to about 350 micrometers. The rear surface electrode9illustrated inFIG. 2is then formed on the bottom surface of the semiconductor substrate1by vacuum evaporation or sputtering, for example. A plurality of elements, each being equivalent to the resistive element illustrated inFIG. 1andFIG. 2, are formed in chip regions arranged into a matrix form in a single wafer. The chip regions are then diced and divided into chips each corresponding to the resistive element as illustrated inFIG. 1andFIG. 2.

The method of manufacturing the resistive element according to the embodiment facilitates the fabrication of the resistive element with the chip size reduced and the number of the bonding wires decreased. Choosing an appropriate mask in the step illustrated inFIG. 9to change the presence or absence of the first electrode contact regions61ato the fourth electrode contact regions61d, the first wire contact regions62ato the fourth wire contact regions62d, and the first substrate contact regions63ato the fourth substrate contact regions63d, can selectively use any of or all of the first resistive layer31ato the fourth resistive layer31dso as to adjust the number of the resistive layers connected in parallel.

First Modified Example

A resistive element according to a first modified example of the embodiment of the present invention differs from the resistive element according to the embodiment illustrated inFIG. 1andFIG. 2in that three of the first resistive layer31ato the fourth resistive layer31d, which are the first resistive layer31a, the second resistive layer31b, and the fourth resistive layer31d, are selectively used and connected in parallel, as illustrated inFIG. 14andFIG. 15. The resistive element according to the first modified example is not provided with the third electrode contact regions61cconnecting the pad-forming electrode51and the third resistive layer31c, the third wire contact regions62cconnecting the third resistive layer31cand the third relay wire52c, or the third substrate contact regions63cconnecting the third relay wire52cand the semiconductor substrate1illustrated inFIG. 1andFIG. 2. The other configurations of the resistive element according to the first modified example are the same as those of the resistive element according to the embodiment illustrated inFIG. 1andFIG. 2, and overlapping explanations are not repeated below.

The resistive element according to the first modified example including the three resistive layers of the first resistive layer31a, the second resistive layer31b, and the fourth resistive layer31d, is decreased in the number of the resistive layers connected in parallel as compared with the resistive element according to the embodiment illustrated inFIG. 1andFIG. 2, so as to increase the resistance value of the resistive element according to the first modified example.

A method of manufacturing the resistive element according to the first modified example can use a mask different from that used in the step illustrated inFIG. 9in the method of manufacturing the resistive element according to the embodiment, so as to exclude the step of forming the third electrode contact regions61c, the third wire contact regions62c, and the third substrate contact regions63c. The other steps of the method of manufacturing the resistive element according to the first modified example are the same as those of the manufacturing method for the resistive element according to the embodiment described above, and overlapping explanations are not repeated below.

Second Modified Example

A resistive element according to a second modified example of the embodiment of the present invention has a configuration common to the resistive element according to the first modified example illustrated inFIG. 14andFIG. 15in that three of the first resistive layer31ato the fourth resistive layer31d, which are the first resistive layer31a, the second resistive layer31b, and the fourth resistive layer31d, are selectively used and connected in parallel, as illustrated inFIG. 16andFIG. 17. The resistive element according to the second modified example differs from the resistive element according to the first modified example illustrated inFIG. 14andFIG. 15in excluding only the third electrode contact regions61cconnecting the pad-forming electrode51and the third resistive layer31c, while including the third wire contact regions62cconnecting the third resistive layer31cand the third relay wire52cand the third substrate contact regions63cconnecting the third relay wire52cand the semiconductor substrate1illustrated in FIG.1andFIG. 2. The other configurations of the resistive element according to the second modified example are the same as those of the resistive element according to the first modified example illustrated inFIG. 14andFIG. 15, and overlapping explanations are not repeated below.

The resistive element according to the second modified example only excluding the third electrode contact regions61ccan lead the third resistive layer31cnot to be used. The resistive element according to the second modified example can lead the third resistive layer31cnot to be used also when excluding either the third wire contact regions62cor the third substrate contact regions63cwhile including the third electrode contact regions61c. Namely, the resistive element according to the second modified example can lead the third resistive layer31cnot to be used when excluding at least one of the third electrode contact regions61c, the third wire contact regions62c, and the third substrate contact regions63c.

A method of manufacturing the resistive element according to the second modified example can use a mask different from that used in the step illustrated inFIG. 9in the method of manufacturing the resistive element according to the embodiment, so as to exclude the step of forming the third electrode contact regions61c.

Third Modified Example

A resistive element according to a third modified example of the embodiment of the present invention differs from the resistive element according to the embodiment illustrated inFIG. 1andFIG. 2in that the width W1of the first resistive layer31aand the third resistive layer31cis different from the width W2of the second resistive layer31band the fourth resistive layer31d, as illustrated inFIG. 18. The width W1of the first resistive layer31aand the third resistive layer31cis smaller than the width W2of the second resistive layer31band the fourth resistive layer31d, and the resistance value is thus greater for the first resistive layer31aand the third resistive layer31cthan for the second resistive layer31band the fourth resistive layer31d. The other configurations of the resistive element according to the third modified example are the same as those of the resistive element according to the embodiment illustrated inFIG. 1andFIG. 2, and overlapping explanations are not repeated below.

The resistive element according to the third modified example has a configuration in which the width W1of the first resistive layer31aand the third resistive layer31cis different from the width W2of the second resistive layer31band the fourth resistive layer31d, so as to allow the resistance value of the first resistive layer31aand the third resistive layer31cand the resistance value of the second resistive layer31band the fourth resistive layer31dto differ from each other. This expands the possibility of the resistance value to be set in the resistive element according to the third modified example when selectively using the first resistive layer31ato the fourth resistive layer31d. The resistive element according to the third modified example has been illustrated with the case of leading the resistance value of the first resistive layer31aand the third resistive layer31cto differ from the resistance value of the second resistive layer31band the fourth resistive layer31d, but is not limited to this case. For example, the respective widths of the first resistive layer31ato the fourth resistive layer31dmay differ from each other so as to change the respective resistance values of the first resistive layer31ato the fourth resistive layer31dfrom each other.

Fourth Modified Example

A resistive element according to a fourth modified example of the embodiment of the present invention differs from the resistive element according to the embodiment illustrated inFIG. 1andFIG. 2in that the two resistive layers of the first resistive layer31aand the second resistive layer31bare arranged on the opposite sides to interpose the pad-forming electrode51, as illustrated inFIG. 19. The planar pattern including the first resistive layer31a, the second resistive layer31b, the pad-forming electrode51, the first relay wire52a, and the second relay wire52bhas two-fold rotational symmetry about the center O of the chip, so as to allow the resistive element according to the fourth modified example to be turned by 180 degrees upon packaging to facilitate the process of assembly. The other configurations of the resistive element according to the fourth modified example are the same as those of the resistive element according to the embodiment illustrated inFIG. 1andFIG. 2, and overlapping explanations are not repeated below.

The resistive element according to the fourth modified example including the two resistive layers can selectively use one of or both of the first resistive layer31aand the second resistive layer31bsuch that the presence or absence of each of the first electrode contact regions61aand the second electrode contact regions61b, the first wire contact regions62aand the second wire contact regions62b, and the first substrate contact regions63aand the second substrate contact regions63bis determined.

Fifth Modified Example

A resistive element according to a fifth modified example of the embodiment of the present invention differs from the resistive element according to the embodiment illustrated inFIG. 1andFIG. 2in that a plurality of (three) resistive layers, the first resistive layer31ato the third resistive layer31c, are arranged on one side of the rectangular planar pattern of the pad-forming electrode51, as illustrated inFIG. 20. The other configurations of the resistive element according to the fifth modified example are the same as those of the resistive element according to the embodiment illustrated inFIG. 1andFIG. 2, and overlapping explanations are not repeated below.

The resistive element according to the fifth modified example including the three resistive layers of the first resistive layer31ato the third resistive layer31con one side of the rectangular planar pattern of the pad-forming electrode51, can selectively use any of or all of the first resistive layer31ato the third resistive layer31csuch that the presence or absence of each of the first electrode contact regions61ato the third electrode contact regions61c, the first wire contact regions62ato the third wire contact regions62c, and the first substrate contact regions63ato the third substrate contact regions63cis determined.

Sixth Modified Example

A resistive element according to a sixth modified example of the embodiment of the present invention differs from the resistive element according to the embodiment illustrated inFIG. 1andFIG. 2in including a plurality of (two) pad-forming electrodes, a first pad-forming electrode51aand a second pad-forming electrode51b, arranged separately from each other, and further including a first resistive layer31ato a sixth resistive layer31fbetween the first pad-forming electrode Ma and the second pad-forming electrode51b, as illustrated inFIG. 21andFIG. 22.

The first pad-forming electrode Ma is connected with the respective edges on one side of the first resistive layer31ato the third resistive layer31cvia the first electrode contact regions61ato the third electrode contact regions61c. The respective edges on the other side of the first resistive layer31ato the third resistive layer31care connected with the first relay wire52ato the third relay wire52cvia the first wire contact regions62ato the third wire contact regions62c. The first relay wire52ato the third relay wire52care connected to the semiconductor substrate1via the first substrate contact regions63ato the third substrate contact regions63c. A first contact region10ato a third contact region10cand a peripheral contact region11having the same conductivity type as the semiconductor substrate1and having a higher impurity concentration (a lower specific resistivity) than the semiconductor substrate1, are provided in the upper portion of the semiconductor substrate1at the contact positions between the semiconductor substrate1and each of the first substrate contact regions63ato the third substrate contact regions63c. The contact regions10and the periphery contact region11may also be provided in the other examples of the embodiment.

The second pad-forming electrode51bis connected with the respective edges on one side of the fourth resistive layer31dto the sixth resistive layer31fvia the fourth electrode contact regions61dto the sixth electrode contact regions61f. The respective edges on the other side of the fourth resistive layer31dto the sixth resistive layer31fare connected with the first relay wire52ato the third relay wire52cvia the fourth wire contact regions62dto the sixth wire contact regions62fThe resistive element according to the sixth modified example can be used as the pair of the first gate resistive element R1and the second gate resistive element R2illustrated inFIG. 3, for example. The other configurations of the resistive element according to the sixth modified example are the same as those of the resistive element according to the embodiment illustrated inFIG. 1andFIG. 2, and overlapping explanations are not repeated below.

The resistive element according to the sixth modified example including the plural (two) pad-forming electrodes of the first pad-forming electrode Ma and the second pad-forming electrode51b, can selectively use any of or all of the first resistive layer31ato the sixth resistive layer31fsuch that the presence or absence of each of the first electrode contact regions61ato the sixth electrode contact regions61f, the first wire contact regions62ato the sixth wire contact regions62f, and the first substrate contact regions63ato the sixth substrate contact regions63fis determined.

Seventh Modified Example

A resistive element according to a seventh modified example of the embodiment of the present invention differs from the resistive element according to the embodiment illustrated inFIG. 1andFIG. 2in including a first auxiliary pad65ato a fourth auxiliary pad65delectrically connected to the first relay wire63ato the fourth relay wire63d, as illustrated inFIG. 23.FIG. 23omits the illustration of the passivation insulating film, and only indicates openings7bto7eof the passivation insulating film by the broken lines. The first auxiliary pad65ato the fourth auxiliary pad65dare exposed to the openings7bto7eof the passivation insulating film. The first auxiliary pad65ato the fourth auxiliary pad65dinclude the same material as the first relay wire63ato the fourth relay wire63d, and can be formed simultaneously with the first relay wire63ato the fourth relay wire63d. The other configurations of the resistive element according to the seventh modified example are the same as those of the resistive element according to the embodiment illustrated inFIG. 1andFIG. 2, and overlapping explanations are not repeated below.

FIG. 24is an equivalent circuit diagram of the resistive element according to the seventh modified example of the embodiment of the present invention. InFIG. 24, the pad-forming electrode51corresponds to a pad-side terminal101, the rear surface electrode9corresponds to a rear surface-side terminal102, and the first auxiliary pad65ato the fourth auxiliary pad65dcorrespond to auxiliary terminals103ato103d. Resistors Rpoly1to Rpoly4connected in parallel corresponding to the first resistive layer31ato the fourth resistive layer31dare connected in series to a resistor Rsubof the semiconductor substrate1between the pad-side terminal101and the rear surface-side terminal102. The auxiliary terminals103ato103dare connected between the resistor Rsubof the semiconductor substrate1and each of the resistors Rpoly1to Rpoly4corresponding to the first resistive layer31ato the fourth resistive layer31d.

The resistive element according to the seventh modified example including the first auxiliary pad65ato the fourth auxiliary pad65d, can measure the electric characteristics of the resistors Rpoly1to Rpoly4corresponding to the first resistive layer31ato the fourth resistive layer31d, excluding the component of the resistor Rsubof the semiconductor substrate1, between the pad-forming electrode51and each of the first auxiliary pad65ato the fourth auxiliary pad65d.

Eighth Modified Example

A resistive element according to an eighth modified example of the embodiment of the present invention differs from the resistive element according to the embodiment illustrated inFIG. 1andFIG. 2in including an auxiliary film33in a floating state in terms of electric potential allocated on the field insulating film2and separated from the first resistive layer31ato the fourth resistive layer31d, as illustrated inFIG. 25andFIG. 26.

The auxiliary film33is deposited under the pad-forming electrode51and is separated from the first resistive layer31ato the fourth resistive layer31d. The auxiliary film33includes the same material as the first resistive layer31ato the fourth resistive layer31d, such as n-type DOPOS, and has the same thickness as the first resistive layer31ato the fourth resistive layer31d. The auxiliary film33has a rectangular planar pattern, for example. The auxiliary film33may be obtained such that a part of the DOPOS layer3is selectively removed so as to be formed together with the first resistive layer31ato the fourth resistive layer31din the step illustrated inFIG. 13. The other configurations of the resistive element according to the eighth modified example are the same as those of the resistive element according to the embodiment illustrated inFIG. 1, and overlapping explanations are not repeated below.

The resistive element according to the eighth modified example including the auxiliary film33in the floating state allocated on the field insulating film2, can reduce a parasitic capacitance under the pad-forming electrode51, as in the case of increasing the thickness of the field insulating film2. The resistive element according to the eighth modified example thus can avoid a decrease in the total resistance upon a reduction in impedance during operation at a high frequency, so as to prevent an oscillation phenomenon.

Ninth Modified Example

A resistive element according to a ninth modified example of the embodiment of the present invention differs from the resistive element according to the embodiment illustrated inFIG. 1andFIG. 2in further including a fifth resistive layer34ato a twelfth resistive layer34hand a fifth relay wire54ato a twelfth relay wire54h, as illustrated inFIG. 27. The fifth resistive layer34aand the sixth resistive layer34bare arranged to interpose the first resistive layer31a. The seventh resistive layer34cand the eighth resistive layer34dare arranged to interpose the second resistive layer31b. The ninth resistive layer34eand the tenth resistive layer34fare arranged to interpose the third resistive layer31c. The eleventh resistive layer34gand the twelfth resistive layer34hare arranged to interpose the fourth resistive layer31d.

The fifth relay wire54aand the sixth relay wire54bare arranged to interpose the first relay wire52a. The seventh relay wire54cand the eighth relay wire54dare arranged to interpose the second relay wire52b. The ninth relay wire54eand the tenth relay wire54fare arranged to interpose the third relay wire52c. The eleventh relay wire54gand the twelfth relay wire54hare arranged to interpose the fourth relay wire52d. The other configurations of the resistive element according to the ninth modified example are the same as those of the resistive element according to the embodiment illustrated inFIG. 1andFIG. 2, and overlapping explanations are not repeated below.

The resistive element according to the ninth modified example can increase/decrease the number of the first resistive layer31ato the fourth resistive layer31dconnected in parallel, and the number of the fifth resistive layer34ato the twelfth resistive layer34hconnected in parallel such that the presence or absence of the fifth electrode contact regions to the twelfth electrode contact regions, the fifth wire contact regions to the twelfth wire contact regions, and the fifth substrate contact regions to the twelfth substrate contact regions used for connecting the fifth resistive layer34ato the twelfth resistive layer34hconnected in parallel is determined, so as to regulate the resistance value of the resistive element according to the ninth modified example more finely. The resistive element according to the ninth modified example is not limited to the number or the arranged positions of the resistive layers described above, which can be determined as appropriate.

Tenth Modified Example

A resistive element according to a tenth modified example of the embodiment of the present invention differs from the resistive element according to the embodiment illustrated inFIG. 1andFIG. 2in including a first projection51xto a third projection51zon one side of the rectangular planar pattern of the pad-forming electrode51, as illustrated inFIG. 28. The first projection51xis connected to one edge of the first resistive layer31avia the first electrode contact regions61a. The second projection51yis connected to one edge of the second resistive layer31bvia the second electrode contact regions61b. The third projection51zis connected to one edge of the third resistive layer31cvia the third electrode contact regions61c.

The other edge of the first resistive layer31ais connected to the first relay wire52avia the first wire contact regions62a. The other edge of the second resistive layer31bis connected to the second relay wire52bvia the second wire contact regions62b. The other edge of the third resistive layer31cis connected to the third relay wire52cvia the third wire contact regions62c.

The first relay wire52ais connected to the semiconductor substrate1via the first substrate contact regions63a. The second relay wire52bis connected to the semiconductor substrate1via the second substrate contact regions63b. The third relay wire52cis connected to the semiconductor substrate1via the third substrate contact regions63c.

The resistive element according to the tenth modified example has a configuration in which the three resistive layers of the first resistive layer31ato the third resistive layer31care connected in parallel. As schematically indicated by the arrows inFIG. 28, a first current channel I1is formed through which a current flows from the first projection51xof the pad-forming electrode51to the semiconductor substrate1via the first resistive layer31aand the first relay wire52a. A second current channel12is also formed through which a current flows from the second projection51yof the pad-forming electrode51to the semiconductor substrate1via the second resistive layer31band the second relay wire52b. A third current channel13is also formed through which a current flows from the third projection51zof the pad-forming electrode51to the semiconductor substrate1via the third resistive layer31cand the third relay wire52c. The other configurations of the resistive element according to the tenth modified example are the same as those of the resistive element according to the embodiment illustrated inFIG. 1andFIG. 2, and overlapping explanations are not repeated below.

The resistive element according to the tenth modified example including the three resistive layers of the first resistive layer31ato the third resistive layer31c, can selectively use any of or all of the first resistive layer31ato the third resistive layer31csuch that the presence or absence of each of the first electrode contact regions61ato the third electrode contact regions61c, the first wire contact regions62ato the third wire contact regions62c, and the first substrate contact regions63ato the third substrate contact regions63cis determined.

Eleventh Modified Example

A resistive element according to an eleventh modified example of the embodiment of the present invention differs from the resistive element according to the tenth modified example illustrated inFIG. 28in that the first projection51xand the third projection51zare separated from the pad-forming electrode51, as illustrated inFIG. 29. The resistive element according to the eleventh modified example has a configuration in which the current channel I1is formed through which a current flows from the second projection51yof the pad-forming electrode51to the semiconductor substrate1via the second resistive layer31band the second relay wire52b. The other configurations of the resistive element according to the eleventh modified example are the same as those of the resistive element according to the tenth modified example illustrated inFIG. 28, and overlapping explanations are not repeated below.

The resistive element according to the eleventh modified example selectively separates the first projection51xto the third projection51zfrom the pad-forming electrode51, without changing the presence or absence of the first electrode contact regions61ato the third electrode contact regions61c, the first wire contact regions62ato the third wire contact regions62c, or the first substrate contact regions63ato the third substrate contact regions63c, so as to selectively use any of or all of the first resistive layer31ato the third resistive layer31c.

Twelfth Modified Example

A resistive element according to a twelfth modified example of the embodiment of the present invention differs from the resistive element according to the tenth modified example illustrated inFIG. 28in that a plurality of (three) resistive layers, the first resistive layer31ato the third resistive layer31c, are connected in series, as illustrated inFIG. 30. The resistive element according to the twelfth modified example includes a first inter-resistor wire54aat a position in which the second relay wire52band the third relay wire52cillustrated inFIG. 28are located, and a second inter-resistor wire54bat a position in which the first projection51xand the second projection51yillustrated inFIG. 28are located.

The first inter-resistor wire54ais connected to the second resistive layer31band the third resistive layer31cvia the second wire contact regions62band the third wire contact regions62c. The second inter-resistor wire54bis connected to the first resistive layer31aand the second resistive layer31bvia the first electrode contact regions61aand the second electrode contact regions61b.

The resistive element according to the twelfth modified example has a configuration in which the first current channel I1is formed through which a current flows from the third projection51zof the pad-forming electrode51to the semiconductor substrate1via the third resistive layer31c, the first inter-resistor wire54a, the second resistive layer31b, the second inter-resistor wire54b, the first resistive layer31a, and the first relay wire52a, as schematically indicated by the arrows inFIG. 30. The other configurations of the resistive element according to the twelfth modified example are the same as those of the resistive element according to the tenth modified example illustrated inFIG. 28, and overlapping explanations are not repeated below.

The resistive element according to the twelfth modified example including the first inter-resistor wire54aand the second inter-resistor wire54bconnects the first resistive layer31ato the third resistive layer31cin series, so as to increase the resistance value.

Thirteenth Modified Example

A resistive element according to a thirteenth modified example of the embodiment of the present invention differs from the resistive element according to the tenth modified example illustrated inFIG. 28in that a plurality of (two) resistive layers, the first resistive layer31aand the third resistive layer31c, are connected in series, as illustrated inFIG. 31. The resistive element according to the thirteenth modified example includes an inter-resistor wire55at a position in which the first projection51x, the second projection51y, the second relay wire52b, and the third relay wire52care located. The inter-resistor wire55is connected to the first resistive layer31avia the first electrode contact regions61a, and is connected to the third resistive layer31cvia the third wire contact regions62c.

The resistive element according to the thirteenth modified example has a configuration in which the first current channel I1is formed through which a current flows from the third projection51zof the pad-forming electrode51to the semiconductor substrate1via the third resistive layer31c, the inter-resistor wire55, the first resistive layer31a, and the first relay wire52a, as schematically indicated by the arrows inFIG. 31. The other configurations of the resistive element according to the thirteenth modified example are the same as those of the resistive element according to the tenth modified example illustrated inFIG. 28, and overlapping explanations are not repeated below.

The resistive element according to the thirteenth modified example including the inter-resistor wire55connects the first resistive layer31aand the third resistive layer31cin series while avoiding the substrate contact adjacent to the pad-forming electrode51, so as to increase the resistance value.

OTHER EMBODIMENTS

While the present invention has been illustrated by reference to the above embodiment, it should be understood that the present invention is not intended to be limited to the descriptions and the drawings composing part of this disclosure. It will be apparent to those skilled in the art that the present invention includes various alternative embodiments, examples, and technical applications according to the technical idea disclosed in the above embodiments.

While the present invention has been illustrated with the case of using the resistive element according to the embodiment as the first gate resistive element R1to the twelfth gate resistive element R12as illustrated inFIG. 3, the resistive element according to the present invention is not limited to the first gate resistive element R1to the twelfth gate resistive element R12, and may be used as a resistive element for various types of ICs.