Bleeder circuitry for an electronic device

Devices and methods include voltage buses. The devices also include one or more power amplifiers coupled to the voltage bus. Each of the one or more power amplifiers include one or more transistors. The devices also include a model that is configured to emulate leakage from at least one of the one or more transistors. A current mirror with a first transistor coupled to the model and a second transistor coupled to the voltage bus. The current mirror is configure to draw charge from the voltage bus based at least in part on the emulated leakage from the model.

BACKGROUND

Field of the Present Disclosure

Embodiments of the present disclosure relate generally to sinks for electrical charges in electronic devices. For example, bleeder circuitry may be used to sink current from one or more transistors (e.g., PMOS) to mitigate voltage drift on one or more voltage buses due to leakage currents.

Description of Related Art

Various operations in a memory device and/or other electronic devices may rely on power amplifiers that utilize one or more transistors. For example, the one or more transistors may include p-channel metal oxide semiconductor (PMOS) transistors and/or n-channel metal oxide semiconductor (NMOS) transistors. The power amplifiers may utilize the one or more transistors to provide a relatively large current (e.g., 1 mA) for the memory device and/or electronic device. However, the one or more transistors may leak some current during some standby modes. For instance, the one or more transistors may leak switch-off currents (Ioff) when the one or more transistors are turned off. Bleeder circuitry may be used to sink the leakage currents to maintain a bus voltage. However, some implementations of bleeder circuitry may be relatively large when numerous (e.g., 100 or more) power amplifiers are used in the memory device and/or other electronic devices. This is especially true for amplifier-based bleeder circuitry implementations. Additionally, the bleeder circuitry may consume additional power (e.g., via amplifiers) that wastes power. Indeed, some amplifier-based bleeder circuitries may consume power even when the bleeder circuitry is not bleeding current from a connected voltage bus.

Embodiments of the present disclosure may be directed to one or more of the problems set forth above.

DETAILED DESCRIPTION

As previously discussed, bleeder circuitry may be used to sink the leakage currents to maintain a bus voltage. However, amplifier-based implementations of bleeder circuitry may be relatively large when numerous (e.g., 100 or more) power amplifiers are used in the memory device and/or other electronic devices. Additionally, the bleeder circuitry may consume additional power (e.g., via amplifiers) that wastes power, such as consuming power even when the bleeder circuitry is not actively bleeding off charge from a voltage bus or when bleeding off currents of various sizes. Instead, as discussed below, a current-mirror-based implementation of bleeder circuitry may consume less power and size. The current-mirror-based implementation includes one or more (e.g., 2) current mirrors. As discussed below, the current-mirror-based implementation of the bleeder circuitry may include a model configured to model leakage from at least one of the one or more transistors of the power amplifiers. For instance, the model may include a transistor of a same type and size as a transistor of a single power amplifier. For example, the model transistor may be a p-channel metal oxide semiconductor (PMOS) transistor that is the same size as the PMOS transistors in the power amplifiers.

One leg of one of the current mirrors couples to the model and another leg of the same current mirror couples to the voltage bus that has a voltage that may fluctuate due to leakages in the power amplifiers. The gates of transistors of the two legs of the current mirror are coupled together to implement the current mirror. A size of the transistor of the left leg may be proportional to a size of the transistor of the right leg. For instance, the transistor of the left leg may be N times larger than the transistor of the right leg. N is the number of power amplifier transistors whose leakage is being mitigated. The transistors of the right and left legs are of a same type, such as PMOS-type transistors.

The bleeder circuitry also includes another current mirror with a left leg coupled to the left leg of the other current mirror and a right leg coupled to the right leg of the other current mirror. The transistors of the left and right legs of this current mirror are also proportional with the transistor of the left leg being N times larger than the transistor of the right leg with N being the number of power amplifier transistors whose leakage is being mitigated. These transistors may be the same type as each other while being of a different type than the transistors of the other current mirror. For instance, the transistors of the left and right legs may be n-channel metal oxide semiconductor (NMOS) transistors connected to the PMOS transistors of the other current mirror.

In some situations, the bleeder circuitry may be susceptible to an independent operation of the two between the two current mirrors. For instance, during a startup of the electronic device or the bleeder circuitry, at least one of the current mirrors may independently loop. To balance the current mirrors during the startup, a startup transistor may be coupled between the gates of the transistors of the first current mirror and the gates of the transistors of the second current mirror.

Turning now to the figures,FIG.1is a simplified block diagram illustrating certain features of an electronic device10having one or more power amplifiers12. Specifically, the block diagram ofFIG.1is a functional block diagram illustrating only certain functionality of the electronic device10. The power amplifiers12amplify signals/voltages/currents to a desired amplified level. In accordance with one embodiment, the electronic device10may be a double data rate type five synchronous dynamic random access memory (DDR5 SDRAM) device or a double data rate type four synchronous dynamic random access memory (DDR4 SDRAM). Additionally or alternatively, the electronic device10may include any type of electronic device that includes the one or more power amplifiers12. The one or more power amplifiers12receive an input power level14(e.g., voltage and/or current) and outputs an amplified power level16that is transmitted to target circuitry18that utilizes the amplified power level16. The target circuitry18may include any circuitry in the electronic device10that performs one or more functions using the amplified power level16. For example, the amplified power level16may include an array voltage provided to the target circuitry18as a memory array of the electronic device10. Furthermore, the amplified power level16may be delivered using a power bus. For instance, the array voltage may be provided to the memory array via an array voltage bus.

FIG.2is a block diagram of an embodiment of the power amplifier12. As illustrated, the power amplifier12receives the input power level14at an amplifier20that outputs a gate voltage22to a gate of a transistor24. In some embodiments, the input power level14may be input to the amplifier20at a non-inverting input of the amplifier20. The value of the gate voltage22controls how much current passes through the transistor24from a supply voltage (VDD). The transistor24may include a p-channel metal-oxide-semiconductor (PMOS) transistor that is large enough to provide the amplified power level16to a node26using the VDD. For example, the node26may be coupled to a bus and/or the target circuitry18. The node26may be connected to ground through some resistance38. For instance, the resistance38may include the overall resistance between the node26and ground through the target circuitry18. The value of the node26may also be fed back to the amplifier20. For example, the feedback from the node may be applied to an inverting input of the amplifier20. The amplified power level16may only be used when the power amplifier12is in an active mode, such as when the target circuitry18has a demand. At other times, the power amplifier12may be in standby or off modes. In many electronic devices, the amplified power level16may be in the standby mode most of the time.

To place the power amplifier12in a standby mode, the gate voltage22may be pulled high to VDD via a line30. This line30may be used to dynamically pull the gate voltage22to VDD using a switch32. In other words, when the switch closes the connection between the gate of the transistor and the VDD connection via the line30, the gate voltage and the source voltage are tied to the VDD. Accordingly, the gate-to-source voltage is negligible thereby causing the transistor24to switch off. However, when the gate voltage22is pulled to VDD causing the transistor24to turn off, the transistor24may leak some current Ioff34. Ioff34may be leaked due to the switching from an active mode to a standby mode for the power amplifier12and/or may be leaked during the standby mode. The electronic device10may sink this leaked current Ioff34with a dynamic connection to ground. However, if the electronic device10includes many (e.g., 100+) power amplifiers12in an electronic device10each having their own Ioff34(e.g., 1 mA), the amount of current to sink may be too big for simple ground connections to sink properly. Instead, bleeder circuitry36may be used to bleed off the Ioff34from the power amplifiers.

FIG.3is a block diagram of an embodiment of the bleeder circuitry36ofFIG.2implemented using an amplifier40. The amplifier40is coupled to some voltage bus, such as a voltage bus for a memory array (VARY), from which leakage charge is to be dissipated by the bleeder circuitry36. Additionally or alternatively, the voltage to the amplifier40may be a reference voltage indicative of a voltage of the voltage bus. The amplifier40is also coupled to bias circuitry42that provides a bias voltage44to the amplifier40to enable the amplifier to amplify the voltage from the voltage bus to an appropriate level in an amplified voltage46. The amplified voltage46is provided to pulldown circuitry48. The pulldown circuitry48is used to pull down a voltage50to bleed off Ileak52(e.g., Ioff34) from the voltage bus. Although the bleeder circuitry36may be successfully implemented using the amplifier-based implementation shown, the amplifier-based implementation may consistently consume a relatively large current (e.g., 8-10 microamps) regardless of how much charge is being dissipated. Additionally, the amplifier-based implementation may consume a relatively large size (e.g., 1,400 square micrometers) relative to a size of a bonding pad (e.g., 4,000 square micrometers) regardless of whether the amplifier-based implementation is not large relative to the size of an overall chip.

In addition or alternative to the amplifier-based implementation of the bleeder circuitry36, the bleeder circuitry36may be implemented using a current-mirror-based implementation as illustrated inFIG.4. As such,FIG.4is a schematic diagram of an embodiment of the bleeder circuitry36using a current-mirror-based implementation. In the illustrated current-mirror-based implementation, the bleeder circuitry36may utilize current mirrors60and62to bleed off leakage current/excess charge. Additionally, the bleeder circuitry36may include a model64that includes a transistor66that is connected to a voltage VPERI at a source and gate of the transistor66. The transistor66may include a PMOS-type transistor. The voltage VPERI may be the same voltage or a similar voltage to the voltages applied to power amplifiers12. Using this voltage, the transistor66is used to generate Ileak68that emulates/models leakages at power amplifiers in the electronic device10. For instance, the transistor66may be proportional to and/or the same size as the transistor24such that the Ileak68matches the Ioff34when the power amplifier12is placed in a standby state. In some embodiments, the bleeder circuitry36may be configured to ensure that the current bled through the bleeder circuitry36is at least as large as an overall leakage current of the power amplifiers12.

The voltage of VARY voltage bus may be based on this voltage VPERI. Accordingly, the voltages VPERI and VARY may change together. Specifically, when the power amplifier(s)12and/or the model64are turned off, the current mirrors60and62may be used to maintain VARY levels. In other words, the bleeder circuitry36may utilize the current mirrors60and62to sink the Ioff34for the power amplifiers12. Otherwise, any currents Ioff34in the power amplifiers12may cause the VARY to be charged to a different voltage level. The sinkage of the leakage current via the bleeder circuitry36enables the VARY to remain consistent between on and standby states.

The current mirror60includes a transistor69that has a source coupled to the drain of the transistor66. The current mirror60also includes a transistor70. The transistors69and70are in respective legs of the current mirror with the gates of the transistors69and70tied together. The transistors69and70may have a same type as each other, such as a PMOS type. The source of the transistor70is coupled to the voltage VARY bus. The drain and gate of the transistor70are also tied together. Additionally, to compensate for an overall leakage current based on the model current, Ileak68, the size of the transistor70may be a multiple of the size of the transistor69. For instance, the size of the transistor70may be at least N times the size the size of the transistor69, where N is the number of power amplifiers12in the electronic device10. This enables the model64to use a much smaller current to emulate the leakage currents of many different power amplifiers12.

The current mirror62is coupled to the current mirror60. For instance, the current mirror62includes a transistor72that is coupled to the transistor69. For instance, the drain of the transistor69may be coupled to the drain of the transistor72. The source of the transistor72may be coupled to a common return, such as VSSDN or ground. The current mirror62also includes a transistor74that is coupled to the transistor70. For instance, the drain of the transistor70may be coupled to the drain of the transistor74. The transistors72and74may be of the same type as each other, such as an N-channel metal oxide semiconductor (NMOS) transistor. The source of the transistor74may be coupled to the common return, such as VSSDN or ground. In other words, the transistors69and70may be of a first type (e.g., PMOS) while the transistors72and74may be of another type (e.g., NMOS). Additionally, the gates of the transistors72and74are coupled together in the current mirror62. Similar to the proportion of the sizes of the transistors69and70, the sizes of the transistors72and74may be proportional. In fact, the proportion between the sizes of the transistors72and74may be the same as the proportion of the sizes of the transistors69and70. In other words, the size of the transistor74may be a multiple of the size of the transistor72. Indeed, the size of the transistor74may be at least N times greater than the size of the transistor72, where N is the number of power amplifiers12in the electronic device10. In some embodiments, the sizes of the transistors69and70may be proportional to each other while also much greater than the sizes of the transistors72and74that are also proportional to each other. Indeed, in certain embodiments, the sizes of the transistors72and74may be designed to reduce the sizes of the transistors72and74to as small as possible.

The current mirrors60and62provide a balanced loop that enables a relatively small current (e.g., <1 microamp to 10 microamps) to be used to compensate for multiple leakage currents using a compensation current Icomp79. However, in some situations such as a startup condition, it may be possible that the current mirrors60and62may function independently to interfere with the described operation of the current mirrors60and62above. For instance, when VPERI=0, the voltage at the source of the transistor69, the voltage at a node76, the voltage at a node78, and at the gates of transistors72and74may all be 0. However, upon startup when VPERI transitions high, the voltage at the node76may transition high with VPERI while it is possible that the voltage at the node78remains at 0. To mitigate the possibility of startup issues, in some embodiments, the bleeder circuitry36may include startup circuitry to address such potential issues.

FIG.5is a schematic diagram of an embodiment of the current-mirror-based implementation of the bleeder circuitry36utilizing startup circuitry80. Indeed, the bleeder circuitry36inFIG.5is identical to the bleeder circuitry36ofFIG.4except that the bleeder circuitry36inFIG.5utilizes the startup circuitry80. As illustrated, the startup circuitry80is coupled between the node76and the node78. The startup circuitry80includes a transistor82. The transistor82is coupled between the node76and the node78. The transistor82may include an NMOS transistor or any other suitable type of transistor. A source of the transistor82may be coupled to the node78. A drain of the transistor82may be coupled to the node76. A gate of the transistor82may also be coupled to the node78. During normal operation of the bleeder circuitry36, the current through the transistor82may be minimal since the voltages of the node76and the node78may be really close in voltage levels. After startup, the voltage at the node76may be VARY-VTH, where VTH is the threshold voltage of the transistor82. During such times, the voltage at the node78may be VTH. Furthermore, although the amplifier-based implementation of the bleeder circuitry36uses a somewhat consistent large current (e.g., 10-20 μA), the current mirror-based implementation of the bleeder circuitry36may use a smaller current (e.g.,<1 μA to 10 μA). Furthermore, the current mirror-based implementation of the bleeder circuitry36may vary based on process corner. For instance, in a TT process corner, the current mirror-based implementation of the bleeder circuitry36may use a current of less than 1 μA while the current used in an FF process corner may be 8-10 μA.

Although the foregoing discusses various logic-low and/or logic-high assertion polarities, at least some of these polarities may be inverted in some embodiments. While the present disclosure may be susceptible to various modifications and alternative forms, specific embodiments have been shown by way of example in the drawings and have been described in detail herein. For instance, PMOS and NMOS transistors may be swapped and polarities of voltages may be reversed. However, it should be understood that the present disclosure is not intended to be limited to the particular forms disclosed. Rather, the present disclosure is intended to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the present disclosure as defined by the following appended claims.