DRIVE CONTROL DEVICE AND MOTOR DEVICE

A drive control device for a motor that is driven by an inverter, the drive control device including a control circuit. The control circuit includes a variable gain amplifier that outputs a first voltage value indicating a current value acquired from the inverter, a comparator that compares the first voltage value acquired from the variable gain amplifier and a reference voltage value, and an overcurrent detection processor that stops driving the motor when the first voltage value exceeds the reference voltage value as a result of comparison by the comparator.

CROSS REFERENCE TO RELATED APPLICATION

The present application claims priority under 35 U.S.C. § 119 to Japanese Application No. 2019-103636 filed on Jun. 3, 2019 the entire contents of which are hereby incorporated herein by reference.

1. FIELD OF THE INVENTION

The present disclosure relates to a drive control device and a motor device.

In order to safely drive a motor, research and development of a safety device that stops the motor when an overcurrent condition occurs has been underway.

In view of this, in a usage environment where safety is more important from among various usage environments of a motor, measures for safety have been demanded, such as installing multiple safety devices as described above, or providing a self-diagnosis function for determining whether the safety devices are normal or abnormal.

In this regard, a drive control device, for a motor, configured as described below has been known. Specifically, the drive control device includes a control circuit provided with a comparison unit that compares a reference voltage value and a first voltage value which increases or decreases according to a current value acquired from an inverter unit of the motor, and an arithmetic processing unit that determines whether or not an overcurrent occurs based on the comparison result of the comparison unit, wherein the arithmetic processing unit includes: a first terminal to which the comparison result of the comparison unit is input; an overcurrent detection processing unit which determines that an overcurrent state occurs when the first voltage value exceeds the reference voltage value in the comparison result, and stops the driving of the motor; a second terminal that receives the first voltage value and repeatedly outputs an operation check signal to the comparison unit at a preset timing; and an operation check processing unit that determines the state of the first terminal based on an output timing of the operation check signal.

In such a drive control device, a current detection unit, the comparison unit, and the arithmetic processing unit are separately provided. Therefore, it may be difficult to reduce the number of components in the drive control device. As a result, the manufacturing cost of the drive control device may not be reduced.

SUMMARY

An example embodiment of the present disclosure provides a drive control device for a motor that is driven by an inverter, the drive control device including a control circuit. The control circuit includes a variable gain amplifier to output a first voltage value indicating a current value acquired from the inverter, a comparator to compare the first voltage value acquired from the variable gain amplifier and a reference voltage value, and an overcurrent detection processor to stop driving the motor when the first voltage value exceeds the reference voltage value as a result of comparison by the comparator.

Another example embodiment of the present disclosure provides a motor device including the motor and the drive control device described above.

DETAILED DESCRIPTION

Example embodiments of the present disclosure will be described below with reference to the drawings. In the present example embodiment, a conductor that transmits an electric signal will be referred to as a transmission path. The transmission path may be, for example, a conductor printed on a substrate, or a conductive wire such as a linearly formed conductor.

First, a configuration of a drive control device1according to the example embodiment will be described with reference toFIG. 1.FIG. 1is a diagram showing an example of the configuration of the drive control device1according to the example embodiment.

The drive control device1supplies a drive current S32to a motor9. Thus, the drive control device1controls the drive of the motor9.

The motor9is, for example, a motor that operates a blower of a bathroom dryer. The motor9may be another motor mounted on a product other than the bathroom dryer, instead of the motor that operates the blower of the bathroom dryer.

The motor9is, for example, a three-phase brushless DC (direct current) motor. That is, the motor9has U-phase, V-phase, and W-phase stator windings. When the drive current S32is supplied to the stator winding of each phase, torque is generated in the motor9between the stator and the rotor, so that the rotor is rotationally driven. The motor9may be another motor driven by an inverter, such as a single-phase motor or a brushed motor.

As shown inFIG. 1, the drive control device1includes a power supply unit2, an inverter3, and a control circuit4. The drive control device1may include other circuits and other devices in addition to the above components. Further, the drive control device1may be configured separately from at least one of the power supply unit2and the inverter3. That is, the drive control device1may not include at least one of the power supply unit2and the inverter3.

The power supply unit2includes an AC power supply21, a diode bridge22, and a smoothing capacitor23.

Any power supply may be used for the AC power supply21, as long as it supplies an AC voltage. The AC power supply21is, for example, a commercial power supply, but may be another external power supply device. The AC power supply21outputs an AC voltage to the diode bridge22.

The diode bridge22is a full-wave rectifier circuit having four diodes. The diode bridge22has two input terminals221. An AC voltage is supplied between these two input terminals221from the AC power supply21. The AC voltage supplied between the two input terminals221is subjected to full-wave rectification in the diode bridge22. The voltage after the full-wave rectification is a full-wave rectified voltage having a voltage waveform of only a positive voltage. This full-wave rectified voltage is output between two output terminals222of the diode bridge22.

The smoothing capacitor23smooths the full-wave rectified voltage that has been subjected to full-wave rectification in the diode bridge22. Thus, the smoothing capacitor23converts the full-wave rectified voltage into a DC voltage Vbus. Then, the DC voltage Vbus is output to a voltage input terminal31of the inverter3.

The inverter3supplies the drive current S32to the motor9according to a pulse signal S45input from the control circuit4. The inverter3has the voltage input terminal31, six switching elements, a shunt resistor Rs, and three motor connection terminals.

The six switching elements included in the inverter3include a switching element Tu1, a switching element Tu2, a switching element Tv1, a switching element Tv2, a switching element Tw1, and a switching element Tw2. Each of the six switching elements includes a transistor and a diode which are connected in parallel. For example, an IGBT (insulated gate bipolar transistor) or the like is used as the transistor, but the transistor is not limited thereto.

Two switching elements, switching element Tu1and switching element Tu2, are connected in series between the voltage input terminal31and the shunt resistor Rs. Further, two switching elements, switching element Tv1and switching element Tv2, are also connected in series between the voltage input terminal31and the shunt resistor Rs. Further, two switching elements, switching element Tw1and switching element Tw2, are also connected in series between the voltage input terminal31and the shunt resistor Rs. The combination of the switching element Tu1and the switching element Tu2, the combination of the switching element Tv1and the switching element Tv2, and the combination of the switching element Tw1and the switching element Tw2are connected in parallel with each other.

The shunt resistor Rs has one end connected to each of the switching element Tu2, the switching element Tv2, and the switching element Tw2, and has the other end grounded. A bus current Ibus flows from the inverter3to the shunt resistor Rs when the motor9is driven.

The three motor connection terminals of the inverter3include a motor connection terminal32u, a motor connection terminal32v, and a motor connection terminal32w. The motor connection terminal32uis located on a transmission path connecting the switching element Tu1and the switching element Tu2. The motor connection terminal32vis located on a transmission path connecting the switching element Tv1and the switching element Tv2. The motor connection terminal32wis located on a transmission path connecting the switching elements Tw1and Tw2.

With the configuration described above, in the U phase of the inverter3, the pulse signal S45is input to each of a base terminal of the switching element Tu1and a base terminal of the switching element Tu2, when the motor9is driven. In the V phase of the inverter3, the pulse signal S45is input to each of a base terminal of the switching element Tv1and a base terminal of the switching element Tv2, when the motor9is driven. In the W phase of the inverter3, the pulse signal S45is input to each of a base terminal of the switching element Tw1and a base terminal of the switching element Tw2, when the motor9is driven. Accordingly, ON/OFF of each of the six switching elements is switched. As a result, the drive current S32is input to the U, V, and W phases of the motor9from the three motor connection terminals, respectively.

The control circuit4monitors the bus current Ibus of the motor9and controls the inverter3.FIG. 2is a diagram illustrating an example of the configuration of the control circuit4. As shown inFIG. 2, the control circuit4includes, for example, an arithmetic processor40.

The arithmetic processor40is, for example, a microcomputer. Note that the arithmetic processor40may be a random logic circuit such as an ASIC (application specific integrated circuit).

The arithmetic processor40includes a connection terminal41, a current detection unit42, a comparison-unit input terminal43, a comparator44, and a control unit45.

The connection terminal41is one of a plurality of input/output terminals of the arithmetic processor40. The connection terminal41is connected to a shunt voltage terminal TM. The shunt voltage terminal TM is located on a transmission path that connects the three switching elements Tu2, Tv2, and Tw2of the inverter3and the shunt resistor Rs. When the bus current Ibus flows through the shunt resistor Rs, the voltage value of the shunt voltage terminal TM becomes the shunt voltage Vs that increases or decreases according to the current value of the bus current Ibus. That is, in this case, the shunt voltage Vs is supplied to the connection terminal41.

The current detection unit42is an amplifier circuit that amplifies the shunt voltage Vs input to the connection terminal41. As shown inFIG. 2, the current detection unit42is a differential amplifier circuit including a variable gain amplifier P1and a plurality of resistors.

The variable gain amplifier P1is, for example, a programmable gain amplifier. Note that the variable gain amplifier P1may be another amplifier capable of changing a gain for amplifying the shunt voltage Vs, instead of the programmable gain amplifier.

The non-inverting input terminal of the variable gain amplifier P1is connected to the connection terminal41via a resistor. The inverting input terminal of the variable gain amplifier P1is grounded via a resistor. Therefore, a first voltage value S42proportional to the voltage difference between the shunt voltage Vs and the ground voltage is output to the output terminal of the current detection unit42.

Further, the current detection unit42has a gain controller421.

The gain controller421sets the gain received by the arithmetic processor40from a user to the variable gain amplifier P1. That is, the gain for amplifying the shunt voltage Vs by the variable gain amplifier P1is the gain set by the gain controller421.

The comparison-unit input terminal43is an output terminal of the current detection unit42. The comparison-unit input terminal43is also an input terminal of the comparator44. The first voltage value S42output from the current detection unit42is input to the comparator44via the comparison-unit input terminal43. The comparison-unit input terminal43is also connected to a first terminal (not shown) of the control unit45. Therefore, the first voltage value S42output from the current detection unit42is also input to the control unit45via the comparison-unit input terminal43.

The comparator44is a comparison circuit having a comparator P2. The comparator44has a reference voltage controller442that inputs a fixed reference voltage value S441to the non-inverting input terminal of the comparator P2. The reference voltage controller442outputs the voltage value received by the arithmetic processor40from the user to the non-inverting input terminal of the comparator P2as the reference voltage value S441. Thus, the drive control device can use the voltage desired by the user as the reference voltage.

Meanwhile, the inverting input terminal of the comparator P2is connected to the comparison-unit input terminal43. Therefore, when the first voltage value S42from the current detection unit42is input to the comparison-unit input terminal43, the comparator P2compares the reference voltage value S441with the first voltage value S42. Then, the comparator P2outputs a voltage value corresponding to the magnitude relationship between the two input voltage values from an output terminal (not shown).

The output terminal of the comparator44is connected to a second terminal (not shown) of the control unit45. Therefore, a determination voltage S44indicating the comparison result by the comparator44is input to the second terminal. Specifically, when the first voltage value S42is smaller than the reference voltage value S441, the determination voltage S44is at an H (High) level. In addition, when the first voltage value S42is equal to or higher than the reference voltage value S441, the determination voltage S44is at an L (Low) level smaller than the H level.

The control unit45is, for example, a CPU (central processor). Note that the control unit45may be another processor instead of the CPU.

The control unit45controls the operation of the six switching elements of the inverter3. The control unit45outputs the pulse signal S45to the inverter3based on a motor drive command signal input from the outside, the first voltage value S42input from the first terminal of the control unit45, and the determination voltage S44input from the second terminal of the control unit45.

The control unit45periodically outputs a first operation check signal S453to the non-inverting input terminal of the variable gain amplifier P1from a third terminal (not shown) at a preset timing. Thus, the first operation check signal S453is input to the variable gain amplifier P1.

Here, the control unit45can output at least two signals having different voltage values from the third terminal of the control unit45as the first operation check signal S453. Specifically, the control unit45outputs two types of signals, a signal at an allowable level having a voltage value lower than the reference voltage value S441, and a signal at an overcurrent equivalent level having a voltage value higher than the reference voltage value S441, from the third terminal of the control unit45.

Further, the control unit45includes, for example, a current value detection processor450, a pulse signal generation unit451, an overcurrent detection processor452, and a first operation check processor453. These functional units of the control unit45are implemented by the control unit45performing arithmetic processing according to a preset program. Note that the control unit45may include other functional units in addition to these functional units. Further, the control unit45may have either the current value detection processor450or the pulse signal generation unit451or may not include both of them. In this case, the functional unit not included in the control unit45out of the current value detection processor450and the pulse signal generation unit451is implemented by a processor separate from the control unit45.

The current value detection processor450acquires the first voltage value S42input to the first terminal of the control unit45from the current detection unit42. The current value detection processor450detects the current value of the bus current Ibus based on the acquired first voltage value S42. The first voltage value S42is acquired in synchronization with the pulse signal S45.

The pulse signal generation unit451outputs the pulse signal S45to the inverter3based on the motor drive command signal (not shown) input from the outside and the current value of the bus current Ibus detected by the current value detection processor450.

The overcurrent detection processor452performs a monitoring process for monitoring whether or not an overcurrent occurs. More specifically, the overcurrent detection processor452performs, as the monitoring process, a process of detecting that the motor9is in the overcurrent state based on the comparison result of the comparator44. The motor9being in the overcurrent state means that the current value of the bus current Ibus of the motor9is abnormally high. In other words, the motor9being in the overcurrent state means that the current value of the bus current Ibus of the motor9is higher than a predetermined value (that is, abnormally high). The predetermined value is a value determined according to a current value of the bus current Ibus of the motor9at which a failure or the like due to the bus current Ibus of the motor9starts to occur. The predetermined value is lower than this current value. In the example embodiment, the overcurrent detection processor452repeatedly performs the monitoring process while the first operation check processor453described later is not operating. Thus, the overcurrent detection processor452can constantly monitor whether or not an overcurrent occurs while the first operation check processor453is not operating.

In the monitoring process, the overcurrent detection processor452determines whether the determination voltage S44from the comparator44input to the second terminal of the control unit45is at the L level or the H level. With this process, the overcurrent detection processor452determines whether or not the motor9is in the overcurrent state.

In the monitoring process, when determining that the determination voltage S44is at the L level, the overcurrent detection processor452determines that the motor9is in the overcurrent state. Then, in this case, the overcurrent detection processor452stops outputting the pulse signal S45from the pulse signal generation unit451. Accordingly, in this case, the overcurrent detection processor452stops driving of the motor9. That is, when determining that the motor9is in the overcurrent state, the overcurrent detection processor452stops driving of the motor9.

On the other hand, in the monitoring process, the overcurrent detection processor452determines that the motor9is in a normal state, when determining that the determination voltage S44is at the H level. Then, in this case, the overcurrent detection processor452does not stop the operation of the pulse signal generation unit451. That is, in this case, the pulse signal generation unit451continues to output the pulse signal S45to the inverter3.

The first operation check processor453performs a first determination process of checking (determining) whether or not at least one of the current detection unit42and the comparator44is abnormal at a preset timing. More specifically, the first operation check processor453checks, at the timing, whether or not at least one of the variable gain amplifier P1and the comparator P2is abnormal in the first determination process. The first operation check processor453temporarily disables the monitoring process performed by the overcurrent detection processor452at the timing, outputs the first operation check signal S453from the third terminal of the control unit45, and executes the first determination process.

FIG. 3is a diagram showing an example of operation timings of the current value detection processor450, the overcurrent detection processor452, and the first operation check processor453in the control unit45. As shown inFIG. 3, the current value detection processor450executes a process of detecting the current value of the bus current Ibus at preset time intervals. In the example shown inFIG. 3, the cycle of the detection process of the current value detection processor450is 40 microseconds. In addition, the control unit45executes the first determination process by the first operation check processor453during a period when the detection process by the current value detection processor450is not executed. In the present example embodiment, the first determination process by the first operation check processor453is performed once while the detection process by the current value detection processor450is performed a plurality of times.

In addition, as shown inFIG. 3, the overcurrent detection processor452executes the monitoring process whenever the first determination process by the first operation check processor453is not performed. When executing the first determination process by the first operation check processor453, the control unit45temporarily stops the monitoring process by the overcurrent detection processor452.

As described above, in the drive control device1according to the example embodiment, the control circuit4is achieved by the arithmetic processor40which is implemented by one microcomputer. Therefore, the number of components constituting the control circuit4can be reduced in the drive control device1. Note that, in the arithmetic processor40, the control unit45may be implemented by one or more microcomputers. In this case, the arithmetic processor40includes a microcomputer, and the current detection unit42and the comparator44that are separate from the microcomputer. Also in this case, the arithmetic processor40uses the variable gain amplifier P1instead of the operational amplifier in the current detection unit42, so that the number of components such as resistors can be reduced in the arithmetic processor40, compared with the case where the operational amplifier is used in the current detection unit42. Further, since the variable gain amplifier P1is used in the arithmetic processor40instead of the operational amplifier, the drive control device1can be applied to motors having various winding specifications without changing the configuration. That is, the drive control device1has a smaller number of components and can improve versatility. As a result, the manufacturing cost of the drive control device1can be reduced.

Next, the operation of the control circuit4will be described with reference toFIGS. 4 and 5.FIG. 4is a diagram showing an example of an operation flow of the control circuit4when the motor9is driven.FIG. 5is a diagram showing an example of an operation flow of the first operation check processor453during the first determination process.

The control circuit4determines whether or not an overcurrent occurs in the motor9using the current detection unit42and the comparator44, which are electric circuits outside the control unit45, and the control unit45. During the detection of the overcurrent state using the electric circuit as described above, if short-to-power, ground-fault, or open state occurs due to the failure of the electric circuit, the overcurrent in the motor9may not be detected.

In view of this, the control circuit4outputs the first operation check signal S453from the third terminal of the control unit45, and performs the first determination process by the first operation check processor453. Thus, the control circuit4determines whether or not a failure has occurred in the electric circuit part outside the control unit45of the control circuit4. Specifically, the control circuit4determines whether or not a failure has occurred in at least one of the current detection unit42and the comparator44(that is, the electric circuit part). The control circuit4performs the current value detection process, the monitoring process, and the first determination process for checking the operation by the control circuit4when the motor9is driven, according to the following procedure.

As shown inFIG. 4, when the pulse signal generation unit451starts outputting the pulse signal S45to the inverter3, the control unit45resets a count number N to 1 (step ST101).

Next, the control unit45resets a time t to 0 (step ST102). The time t is incremented every 1 [microsecond]. Further, the processes in step ST101and step ST102may be performed in the reverse order, or may be performed in parallel.

When the setting of the count number N and the time t is completed, the current value detection processor450performs the process of detecting the current value of the bus current Ibus (step ST103). In step ST103, the current value detection processor450detects the current value of the bus current Ibus based on the first voltage value S42input to the first terminal of the control unit45. The detected current value of the bus current Ibus is used to generate the pulse signal S45in the pulse signal generation unit451.

In the present example embodiment, the process of detecting the current value of the bus current Ibus ends in about [microseconds]. After the end of step ST103, the control unit stops the detection process by the current value detection processor450.

When the detection process in step ST103ends, the control unit45determines whether or not the count number N is 1 (step ST104).

When the count number N is 1 (step ST104—YES), the control unit45causes the first operation check processor453to perform the first determination process (step ST105). The detailed procedure of the first determination process will be described later. In the present example embodiment, the first determination process ends in about 4 [microseconds]. The control unit45stops the process of detecting the current value of the bus current Ibus by the overcurrent detection processor452while the first determination process is being performed.

On the other hand, when the count number N is not 1 (step ST104—NO), the control unit45proceeds to step ST106without performing the process in step ST105.

When the first determination process in step ST105ends, or when the count number N is not 1 in step ST104, the control unit45determines whether the time t is equal to or greater than (step ST106). That is, the control unit45determines whether or not 40 [microseconds] have elapsed since the reset of the time t in step ST102.

When the time t is less than 40 (step ST106—NO), the control unit45returns to step ST106and waits.

On the other hand, when the time t is equal to or greater than 40 (step ST106—YES), the control unit45increments the count number N (step ST107). Thereafter, the control unit45determines whether or not the count number N is greater than 4 (step ST108).

When determining that the count number N is equal to or less than 4 in step ST108(step ST108—NO), the control unit45returns to step ST102. Then, the control unit45repeats the processes in steps ST102to ST107. During the repeated processes, while the count number N is 2 to 4, the control unit45determines that the count number N is not 1 in step ST104, and thus the determination process in ST105is skipped.

On the other hand, when determining in step ST108that the count number N is greater than 4 (step ST108—YES), the control unit45returns to step ST101and resets the count number N.

As described above, in the present example embodiment, the first determination process by the first operation check processor453is performed once while the detection process by the current value detection processor450is performed four times. However, the first determination process by the first operation check processor453may be performed once while the detection process performed by the current value detection processor450is performed one to three times, or while the detection process is performed five or more predetermined times. In order to reduce the load on the control unit45, it is preferable to reduce the frequency of the first determination process as long as safety can be ensured.

Next, the first determination process by the first operation check processor453in step ST105will be described with reference toFIG. 5. When ground-fault, short-to-power, or open state occurs due to the failure of the current detection unit42, the first voltage value S42acquired by the current value detection processor450does not change. Therefore, in this case, the control unit45can recognize an abnormality by the first determination process. In addition, if short-to-power occurs on the output terminal of the comparator44despite the current detection unit42being not in failure, the voltage input to the second terminal of the control unit45is at a level equal to or higher than the H level of the determination voltage S44. When ground-fault occurs on the output terminal of the comparator44, the voltage input to the second terminal of the control unit45is at a level equal to or lower than the L level of the determination voltage S44. Further, when the output terminal of the comparator44is in the open state, the voltage input to the second terminal of the control unit45is undefined regardless of the voltage value input to the comparison-unit input terminal43. For these reasons, when ground-fault, short-to-power, or open state occurs due to an occurrence of failure in the comparator44, the control circuit4can recognize the abnormality by the first determination process.

In the first determination process, first, the first operation check processor453outputs the first operation check signal S453at an overcurrent equivalent level having a voltage value higher than the reference voltage value S441from the third terminal (step ST201). The first operation check signal S453at the overcurrent equivalent level is input to the non-inverting input terminal of the variable gain amplifier P1. When the current detection unit42(that is, the variable gain amplifier P1) is normal and the comparator44is normal, the determination voltage S44output from the comparator44is at the L level. The first operation check processor453determines whether or not the determination voltage S44output from the comparator44has changed to the L level (step ST202).

In step ST202, when the determination voltage S44output from the comparator44does not change to the L level (step ST202—NO), it is highly likely that short-to-power occurs in the comparator44, the comparator44is in an open state, or the current detection unit42is in failure. Therefore, the first operation check processor453determines that at least one of the current detection unit42and the comparator44is abnormal, and ends the first determination process. Then, the first operation check processor453stops outputting the pulse signal S45from the pulse signal generation unit451to the inverter3.

On the other hand, when the determination voltage S44output from the comparator44has changed to the L level (step ST202—YES) in step ST202, the first operation check processor453outputs the first operation check signal S453at an allowable level having a voltage value lower than the reference voltage value S441from the third terminal of the control unit45(ST203). The first operation check signal S453at the allowable level is input to the non-inverting input terminal of the variable gain amplifier P1. When the variable gain amplifier P1is normal, the variable gain amplifier P1outputs the first voltage value S42smaller than the reference voltage value S441. The first voltage value S42is input to the comparison-unit input terminal43. When the comparator44is normal, the determination voltage S44output from the comparator44is at the H level. The first operation check processor453determines whether or not the determination voltage S44output from the comparator44has changed to the H level (step ST204).

In step ST204, when the determination voltage S44output from the comparator44does not change to the H level (step ST204—NO), it is highly likely that ground-fault occurs in the comparator44, or the comparator44is in an open state. Therefore, the first operation check processor453determines that the comparator44is abnormal, and ends the determination process. Then, the first operation check processor453stops outputting the pulse signal S45from the pulse signal generation unit451to the inverter3.

On the other hand, in step ST204, when the determination voltage S44output from the comparator44changes to the H level (step ST204—YES), it is determined that both the current detection unit42and the comparator44are normal, and the determination process ends.

As described above, the drive control device1according to the example embodiment can check whether or not both the current detection unit42and the comparator44for detecting an overcurrent are operating normally. Further, in the drive control device1, the arithmetic processor40is implemented by one microcomputer. Therefore, the drive control device1enables reduction in the number of components.

In addition, in the drive control device1according to the example embodiment, the first operation check processor453performs the first determination process in a state where the detection process by the overcurrent detection processor452is stopped. Therefore, the driving of the motor9is not stopped by a high-voltage signal output from the first operation check processor453during the first determination process.

In the drive control device1according to the example embodiment, the process of detecting a current value by the current value detection processor450is performed at fixed time intervals, and the first operation check processor453performs the first determination process during the period when the detection process is not performed. Therefore, it is possible to check the operations of both the current detection unit42and the comparator44without reducing the operation frequency of the current value detection processor450.

Further, in the drive control device1according to the example embodiment, the variable gain amplifier P1serving as an amplifier and the comparator P2included in the comparator are connected in series as shown inFIG. 2. With this configuration, the drive control device1can be configured to have a simpler circuit configuration, compared to a configuration in which the variable gain amplifier P1and the comparator P2are connected in parallel.

Hereinafter, a modification of the example embodiment will be described. In the modification of the example embodiment, the same components as those of the example embodiment are denoted by the same reference numerals, and the description thereof is omitted.

The control unit45described above may include a second operation check processor454instead of the first operation check processor453as shown inFIG. 6.FIG. 6is a diagram illustrating another example of the configuration of the control circuit4.

The second operation check processor454performs a second determination process of checking (determining) whether or not the comparator44is abnormal at a preset timing. More specifically, the second operation check processor454checks, at the timing, whether or not the comparator P2is abnormal in the second determination process. The second operation check processor454temporarily disables the monitoring process of the overcurrent detection processor452at the timing, outputs a second operation check signal S454to the inverting input terminal (the comparison-unit input terminal43in the example inFIG. 6) of the comparator P2from a fourth terminal (not shown) of the control unit45, and executes the second determination process. Note that the first terminal of the control unit45described above may serve as the fourth terminal.

The timing at which the second operation check processor454performs the second determination process is the same as the timing at which the first operation check processor453performs the first determination process. Therefore, the description of the timing at which the second operation check processor454performs the second determination processing is omitted.

In the drive control device1according to the modification of the example embodiment, the second operation check processor454performs the second determination process instead of the first determination process in step ST105shown inFIG. 4.

Here, the second determination process by the second operation check processor454will be described with reference toFIG. 7.FIG. 7is a diagram showing an example of an operation flow of the second operation check processor454during the second determination process.

In the second determination process, first, the second operation check processor454outputs the second operation check signal S454at an overcurrent equivalent level having a voltage value higher than the reference voltage value S441from the fourth terminal (step ST301). The second operation check signal S454at the overcurrent equivalent level is input to the inverting input terminal of the comparator P2. When the comparator44is normal, the determination voltage S44output from the comparator44is at the L level. The second operation check processor454determines whether or not the determination voltage S44output from the comparator44has changed to the L level (step ST302).

In step ST302, when the determination voltage S44output from the comparator44does not change to the L level (step ST302—NO), it is highly likely that short-to-power occurs in the comparator44, or the comparator44is in an open state. Therefore, the second operation check processor454determines that the comparator44is abnormal, and ends the second determination process. Then, the second operation check processor454stops outputting the pulse signal S45from the pulse signal generation unit451to the inverter3.

On the other hand, in step ST302, when the determination voltage S44output from the comparator44has changed to the L level (step ST302—YES), the second operation check processor454outputs the second operation check signal S454at an allowable level having a voltage value lower than the reference voltage value S441from the fourth terminal of the control unit45(ST303). The second operation check signal S454at the allowable level is input to the inverting input terminal of the comparator P2. When the comparator P2is normal, the determination voltage S44output from the comparator44is at the H level. The second operation check processor454determines whether or not the determination voltage S44output from the comparator44has changed to the H level (step ST304).

In step ST304, when the determination voltage S44output from the comparator44does not change to the H level (step ST304—NO), it is highly likely that ground-fault occurs in the comparator44, or the comparator44is in an open state. Therefore, the second operation check processor454determines that the comparator44is abnormal, and ends the determination process. Then, the second operation check processor454stops outputting the pulse signal S45from the pulse signal generation unit451to the inverter3.

On the other hand, in step ST304, when the determination voltage S44output from the comparator44changes to the H level (step ST304—YES), it is determined that the comparator44is normal, and the determination process ends.

As described above, the drive control device1according to the modification of the example embodiment can check whether or not the comparator44for detecting an overcurrent is operating normally. Further, in the drive control device1, the arithmetic processor40is implemented by one microcomputer. Therefore, the drive control device1enables reduction in the number of components.

In the drive control device1described above, the control circuit4may include both the first operation check processor453and the second operation check processor454. In this case, for example, the control unit45may perform the first determination process and the second determination process alternately or randomly in a predetermined sequence or at a timing determined by another method.

Further, the gain controller421described above may vary the gain of the variable gain amplifier P1according to the shunt voltage Vs (that is, the magnitude of the value of the bus current Ibus flowing through the shunt resistor Rs) input to the arithmetic processor40via the connection terminal41. Thus, the drive control device1can perform control such as increasing the gain when the value of the bus current Ibus is small, and decreasing the gain when the value of the bus current Ibus is large. As a result, the drive control device1can obtain a sufficiently large signal even when, for example, the bus current Ibus is small.

The drive control device1described above constitutes a motor device (not shown) together with the motor9. The motor device may include other circuits and other devices in addition to the drive control device1and the motor9.

Further, the first operation check processor453described above may sequentially output the first operation check signal S453at the overcurrent equivalent level and the first operation check signal S453at the allowable level continuously or intermittently.

As described above, the drive control device (the drive control device1in the example described above) according to the example embodiment is a drive control device for a motor (the motor in the example described above) driven by an inverter (the inverter3in the example described above), the drive control device including a control circuit (the control circuit4in the example described above), wherein the control circuit includes: a variable gain amplifier (the variable gain amplifier P1in the example described above) that outputs a first voltage value indicating a current value acquired from the inverter; a comparator (the comparator44in the example described above) that compares the first voltage value acquired from the variable gain amplifier and a reference voltage value; and an overcurrent detection processor (the overcurrent detection processor452in the example described above) that stops driving of the motor, when the first voltage value exceeds the reference voltage value as a result of comparison by the comparator. Thus, the drive control device enables reduction in the number of components.

In the drive control device, the control circuit may include a first operation check processor (the first operation check processor453) that outputs a first operation check signal (the first operation check signal S453in the example described above) to the variable gain amplifier at a preset timing and that determines a state of the variable gain amplifier based on an output timing of the output first operation check signal.

In the drive control device, the control circuit may include a second operation check processor (the second operation check processor454) that repeatedly outputs a second operation check signal (the second operation check signal S454in the example described above) to the comparator at a preset timing, and that determines a state of the comparator based on an output timing of the output second operation check signal.

In the drive control device, the control circuit may include a gain controller (the gain controller421in the example described above) that varies a gain of the variable gain amplifier according to a magnitude of the current value.

In the drive control device, the control circuit may include a reference voltage controller (the reference voltage controller442in the example described above) that varies the reference voltage value set to the comparator according to a received operation.

In the drive control device, the control circuit may include an arithmetic processor, and the arithmetic processor may be provided with the variable gain amplifier, the comparator, and the overcurrent detection processor.

While the example embodiment of the present disclosure has been described above in detail with reference to the drawings, a specific configuration is not limited to the example embodiment, and various changes, substitutions, deletions, etc. may be possible without departing from the scope of the present disclosure.