Voltage converter and operating method of voltage converter

A voltage converter includes a first transistor, a second transistor, a third transistor, a fourth transistor connected, an output capacitor, a flying capacitor, a first gate driver configured to output a first power supply voltage as a first high level and a first voltage as a first low level, a second gate driver configured to output a second power supply voltage as a second high level and a second voltage as a second low level, a third gate driver configured to output a third power supply voltage as a third high level and a third voltage as a third low level, a fourth gate driver configured to output a fourth power supply voltage as a fourth high level and a ground voltage as a fourth low level.

BACKGROUND

Example embodiments of the inventive concepts disclosed herein relate to semiconductor circuits, and more particularly, to voltage converters and/or operating methods thereof.

A voltage converter is configured to convert a level of an input voltage and output the converted input voltage as an output voltage. The voltage converter is used in various electronic devices. Generally, a supply voltage provided in a home, a company, or a public facility has a level of 110 V or 220 V.

However, electronic devices usually use internal voltages having a level lower than 110 V or 220 V. To convert the supply voltage to internal voltages, various voltage converters are used in an electronic device. Accordingly, there is an increasing demand for highly reliable voltage converters to be used in various electronic devices.

SUMMARY

Some example embodiments of the inventive concepts provide voltage converters with improved reliability and/or an method of operating the same.

According to an example embodiment, a voltage converter includes a first transistor connected between an input node and a first node, a second transistor connected between the first node and the output node, a third transistor connected between a second node and a third node, a fourth transistor connected between the third node and a ground node, an output capacitor connected between the third node and the ground node, a flying capacitor connected between the first node and the fourth node, a first gate driver connected to a first gate of the first transistor and configured to output a first power supply voltage as a first high level and a first voltage of the first node as a first low level, a second gate driver connected to a second gate of the second transistor and configured to output a second power supply voltage as a second high level and a second voltage of the second node as a second low level, a third gate driver connected to a third gate of the third transistor and configured to output a third power supply voltage as a third high level and a third voltage of the third node as a third low level, a fourth gate driver connected to a fourth gate of the fourth transistor and configured to output a fourth power supply voltage as a fourth high level and a ground voltage of the ground node as a fourth low level, and a regulator configured to receive an input voltage from the input node, the first voltage from the first node, the second voltage from the second node and the third voltage from the third node, and generate the first power supply voltage being higher than the first voltage, the second power supply voltage being higher than the second voltage, the third power supply voltage being higher than the third voltage and the fourth power supply voltage being higher than a ground voltage of the ground node.

According to an example embodiment, a method of operating a voltage converter includes obtaining a first voltage between a first transistor and a second transistor, a second voltage between the second transistor and a third transistor, and a third voltage between the third transistor and a fourth transistor, the first through fourth transistors being connected in series between an input node and a ground node, generating a first power supply voltage higher than the first voltage based on the first voltage, generating a second power supply voltage higher than the second voltage based on the second voltage, generating a third power supply voltage higher than the third voltage based on the third voltage, generating a fourth power supply voltage higher than a ground voltage of the ground node, applying the first power supply voltage to a gate of the first transistor in a first phase and the first voltage to the gate of the first transistor in a second phase, applying the second voltage to a gate of the second transistor in the first phase and the second power supply voltage to the gate of the second transistor in the second phase, applying the third power supply voltage to a gate of the third transistor in the first phase and the third voltage to the gate of the third transistor in the second phase, and applying the ground voltage to a gate of the fourth transistor in the first phase and the fourth power supply voltage to the gate of the fourth transistor in the second phase. An output capacitor is connected between the ground node and a first node between the second and third transistors. A flying capacitor is connected between a second node and a third node, the second node being between the first transistor and the second transistor, the third node being between the third transistors and the fourth transistors.

According to an example embodiment, a voltage converter comprises a first transistor connected between an input node and a first node, a second transistor connected between the first node and the output node, a third transistor connected between a second node and a third node, a fourth transistor connected between the third node and a ground node, an output capacitor connected between the third node and the ground node, a flying capacitor connected between the first node and the fourth node, a first gate driver connected to a first gate of the first transistor and configured to output a first power supply voltage as a first high level and a first voltage of the first node as a first low level, a second gate driver connected to a second gate of the second transistor and configured to output a second power supply voltage as a second high level and a second voltage of the second node as a second low level, a third gate driver connected to a third gate of the third transistor and configured to output a third power supply voltage as a third high level and a third voltage of the third node as a third low level, a fourth gate driver connected to a fourth gate of the fourth transistor and configured to output a fourth power supply voltage as a fourth high level and a fourth voltage of the fourth node as a fourth low level, a regulator configured to receive an input voltage from the input node, the first voltage from the first node, the second voltage from the second node and the third voltage from the third node, and generate the first power supply voltage being higher than the first voltage, the second power supply voltage being higher than the second voltage, the third power supply voltage being higher than the third voltage and the fourth power supply voltage being higher than a ground voltage of the ground node, a controller configured to output a first driving signal, a second driving signal, a third driving signal and a fourth driving signal, the first through fourth driving signals belong to a voltage domain between a common power supply voltage and the ground voltage, a first level shifter configured to convert the first driving signal to a first voltage domain to output the converted first driving signal to the first gate driver, the first voltage domain being between the first power supply voltage and the first voltage, a second level shifter configured to convert the second driving signal to a second voltage domain to output the converted second driving signal to the second gate driver, the second voltage domain being between the second power supply voltage and the second voltage, and a third level shifter configured to convert the third driving signal to a third voltage domain to output the converted third driving signal to the third gate driver, the third voltage domain being between the third power supply voltage and the third voltage. The fourth driving signal is transferred to the fourth gate driver. The regulator includes a charge pump configured to receive a common power supply voltage, the input voltage and a clock signal, and output a pump voltage which is the common power supply voltage plus the input voltage in response to the clock signal, a first generator configured to receive the pump voltage and the first voltage, and output the first power supply voltage, a second generator configured to receive the pump voltage and the second voltage, and output the second power supply voltage, and a third generator configured to receive the pump voltage and the third voltage, and output the third power supply voltage.

DETAILED DESCRIPTION

Below, some example embodiments of the inventive concepts may be described in detail and clearly to such an extent that an ordinary one in the art easily implements the inventive concepts.

FIG. 1illustrates a voltage converter10according to an example embodiment of the inventive concepts. Referring toFIG. 1, the voltage converter10includes first and second transistors12and13, first and second gate drivers14and15, a level shifter16, a diode17, a controller18, an output capacitor COUT, an inductor “L”, and a boost capacitor CBST.

The voltage converter10may convert an input voltage VIN of an input node NIN to an output voltage VOUT of an output node NOUT. For example, the voltage converter10may be a buck converter that steps down a level of the input voltage VIN to output the output voltage VOUT.

The first and second transistors12and13may be connected in series between a ground node GND supplied with a ground voltage and the input node NIN. A node between the first and second transistors12and13may be a switch node NSW. The inductor “L” is connected between the switch node NSW and the output node NOUT. The output capacitor COUT is connected between the output node NOUT and the ground node GND.

The first gate driver14is biased by a power supply voltage VDD and the ground voltage. The first gate driver14may output a first gate driving signal GD1to control a gate of the first transistor12. The second gate driver15is biased by a boost voltage VBST of a boost node NBST and a switch voltage VSW of the switch node NSW. The second gate driver15may output a second gate driving signal GD2to control a gate of the second transistor13.

The controller18may receive a clock signal CLK and the output voltage VOUT. The controller18may control the first and second gate drivers14and15in response to the clock signal CLK and the output voltage VOUT. A first driving signal DRV1of the controller18is transmitted to the first gate driver14.

A second driving signal DRV2of the controller18is transmitted to the second gate driver15through the level shifter16. The level shifter16may convert (e.g., increase) a level of the second driving signal DRV2to a level defined by the boost voltage VBST and the switch voltage VSW.

The boost capacitor CBST is connected between the boost node NBST and the switch node NSW. The power supply voltage VDD is transmitted to the boost capacitor CBST through the diode17. When the first transistor12is turned on, the boost capacitor CBST may be charged by the power supply voltage VDD. The first and second transistors12and13, the first and second gate drivers14and15, the level shifter16, the diode17, and the controller18may be implemented with a single chip11.

When the first transistor12is turned off, the boost capacitor CBST may maintain the boost voltage VBST to be higher, by an amount of the charged voltage, than the switch voltage VSW. That is, the boost capacitor CBST may control the boost voltage VBST for biasing the second gate driver15to be greater than the switch voltage VSW, so as to output a level that allows the second gate driver15to turn on the second transistor13.

However, some issues may occur in the voltage converter10illustrated inFIG. 1. For example, when the voltage converter10is powered on, the boost capacitor CBST may not be charged. That is, the boost voltage VBST may be the same as the switch voltage VSW, and the second gate driving signal GD2of the second gate driver15may fail to turn on the second transistor13. Accordingly, the voltage converter10may cause an abnormal operation.

The voltage converter10may enter a power saving mode or a sleep mode or may stop voltage conversion under control of an external device. For example, stopping of the voltage conversion is called a “pulse skip”. During the pulse skip, a voltage charged in the boost capacitor CBST may be leaked out. Accordingly, the second gate driving signal GD2may fail to turn on the second transistor13, thereby causing an abnormal operation of the voltage converter10.

The first gate driving signal GD1and the second gate driving signal GD2of the voltage converter10are complementary. When a duty ratio of the second gate driving signal GD2is close to 100%, the second gate driving signal GD2has a max duty. If the second gate driving signal GD2has the max duty, a duty ratio of the first gate driving signal GD1is close to 0%. That is, when the max duty occurs in the second gate driving signal GD2, the first transistor12may not be turned on, and the boost capacitor CBST may not be charged. Accordingly, an abnormal operation that the second gate driving signal GD2fails to turn on the second transistor13may occur in the voltage converter10.

FIG. 2illustrates a voltage converter100according to an example embodiment of the inventive concepts, for solving the above-described issues. Referring toFIG. 2, the voltage converter100includes first and second transistors120and130, first and second gate drivers140and150, a level shifter160, a controller180, a regulator190, an inductor “L”, an output capacitor COUT, and a boost capacitor CBST.

The voltage converter100may convert an input voltage VIN of an input node NIN to an output voltage VOUT of an output node NOUT. For example, the voltage converter100may be a buck converter that steps down a level of the input voltage VIN to output an output voltage VOUT.

The first and second transistors120and130may be connected in series between a ground node GND supplied with a ground voltage and the input node NIN. A node between the first and second transistors120and130may be a switch node NSW. The inductor “L” is connected between the switch node NSW and the output node NOUT. The output capacitor COUT is connected between the output node NOUT and the ground node GND.

The first and second gate drivers140and150may control the first and second transistors120and130, respectively, under control of the controller180. The first gate driver140is biased by a power supply voltage VDD and the ground voltage. The first gate driver140may output a first gate driving signal GD1to control a gate (or a gate voltage) of the first transistor120.

The second gate driver150is biased by a boost voltage VBST of a boost node NBST and a switch voltage VSW of the switch node NSW. The second gate driver150may output a second gate driving signal GD2to control a gate (or a gate voltage) of the second transistor130.

The controller180may receive a clock signal CLK, the output voltage VOUT, and the switch voltage VSW. The controller180may control the first and second driving signals DRV1and DRV2in response to the clock signal CLK, the output voltage VOUT, and/or the switch voltage VSW. For example, the controller180may control the first and second driving signals DRV1and DRV2such that the output voltage VOUT or the switch voltage VSW is maintained at a target level.

The first driving signal DRV1of the controller180is transmitted to the first gate driver140. The second driving signal DRV2of the controller180is transmitted to the second gate driver150through the level shifter160. The level shifter160may translate (e.g., increase) a level of the second driving signal DRV2to a level defined by the boost voltage VBST and the switch voltage VSW.

The controller180may further receive the boost voltage VBST and a pulse skip signal PSK. The controller180may generate control signals CP in response to the clock signal CLK, the boost voltage VBST, the switch voltage VSW, and the pulse skip signal PSK. The control signals CP may be transmitted to the regulator190to control an operation of the regulator190.

The pulse skip signal PSK may be received from an external device (e.g., logic) that controls a pulse skip. If the voltage converter100is controlled to operate in a pulse skip mode, the pulse skip signal PSK may be activated (e.g., to a high level). If the voltage converter100exits from the pulse skip mode and a given time elapses, the pulse skip signal PSK may be deactivated (for example, a low level).

The regulator190may receive the control signals CP from the controller180. The regulator190may further receive the input voltage VIN and the output voltage VOUT. The regulator190may control a voltage of the boost node NBST in response to the control signals CP, the input voltage VIN, and the output voltage VOUT. The boost capacitor CBST is connected between the boost node NBST and the switch node NSW.

The regulator190may operate in at least three modes under control of the control signals CP. The at least three modes may include a normal mode, an input voltage pumping mode, and an output voltage pumping mode. In the normal mode, the regulator190may output the power supply voltage VDD to the boost node NBST.

In the input voltage pumping mode, the regulator190may output a voltage pumped from the input voltage VIN to the boost node NBST. In the output voltage pumping mode, the regulator190may output a voltage pumped from the output voltage VOUT to the boost node NBST. An operation of the regulator190will be described in detail later.

The first and second transistors120and130, the first and second gate drivers140and150, the level shifter160, the controller180, and the regulator190may be implemented with a single chip110. However, components included in the single chip110are not limited to the first and second transistors120and130, the first and second gate drivers140and150, the level shifter160, the controller180, and the regulator190.

FIG. 3is a flowchart illustrating an operating method of the voltage converter100according to an example embodiment of the inventive concepts. Referring toFIGS. 2 and 3, in operation S110, the voltage converter100determines whether the boost voltage VBST is insufficient. For example, when a difference between the boost voltage VBST and the switch voltage VSW is lower than a reference voltage, the voltage converter100may determine that the boost voltage VBST is insufficient. As another example, when the voltage converter100exits from the pulse skip mode, the voltage converter100may determine that the boost voltage VBST is insufficient.

If the boost voltage VBST is insufficient, the voltage converter100enters the output voltage pumping mode. In operation S120, the voltage converter100may control the boost voltage VBST by pumping the output voltage VOUT. For example, the regulator190may control the boost voltage VBST to be higher in level, by an amount of the power supply voltage VDD, than the output voltage VOUT.

The boost voltage VBST may be insufficient in two cases. For example, when the voltage converter100start to be powered, the boost voltage VBST may be insufficient. When the voltage converter100exits from the pulse skip mode, the boost voltage VBST may be insufficient.

In the case where the voltage converter100is used in a mobile device including a battery, the output voltage VOUT may be a voltage of the battery. When power is not supplied to the voltage converter100or when the voltage converter100is in the pulse skip mode, the switch voltage VSW may gradually increase to the output voltage VOUT.

If the boost voltage VBST is pumped from the output voltage VOUT when power starts to be supplied to the voltage converter100or when the voltage converter100exits from the pulse skip mode, then the boost voltage VBST to be greater than the switch voltage VSW may be secured. Accordingly, an abnormal operation in which the second transistor130is not turned on may be prevented or mitigated.

For example, if the boost voltage VBST is sufficient, the voltage converter100may enter the normal mode. For example, in the normal mode, the voltage converter100may control the boost voltage VBST depending on operation S150, which will be described below.

If the boost voltage VBST is sufficient, operation S130is performed. In operation S130, the voltage converter100may determine whether a max duty occurs. For example, when a duty ratio of the second driving signal DRV2is greater than a threshold value, the max duty may be determined. If the max duty is determined, the voltage converter100may enter an input voltage pumping mode. In the input voltage pumping mode, operation S140is performed.

In operation S140, the voltage converter100may control the boost voltage VBST through pumping from the input voltage VIN. If the max duty occurs, in an operation period of the first and second transistors120and130, a time when the second transistor130is turned on is longer than a time when the first transistor120is turned on.

When the second transistor130is turned on, the switch voltage VSW is the same as the input voltage VIN. If the boost voltage VBST is pumped from the input voltage VIN when the second transistor130is turned on, then the boost voltage VBST to be greater than the switch voltage VSW may be secured. Accordingly, an abnormal operation in which the second transistor130is not turned on may be prevented or mitigated.

For example, if the voltage converter100does not have the max duty any longer, the voltage converter100may enter the normal mode. For example, in the normal mode, the voltage converter100may control the boost voltage VBST depending on operation S150, which will be described below.

If the boost voltage VBST is sufficient and the max duty is not determined, the voltage converter100may operate in the normal mode. In the normal mode, operation S150is performed. In operation S150, the regulator190may output the power supply voltage VDD to the boost node NBST. When the first transistor120is turned on, the boost capacitor CBST may be charged to the power supply voltage VDD.

When the second transistor130is turned on, the boost voltage VBST may be a voltage that corresponds to a sum of the switch voltage VSW (e.g., the input voltage VIN) and a charging voltage of the boost capacitor CBST. Thus, the boost voltage VBST to be greater than the switch voltage VSW may be secured. Accordingly, an abnormal operation in which the second transistor130is not turned on may be prevented or mitigated.

FIG. 4is a block diagram illustrating the controller180according to an example embodiment of the inventive concepts. Referring toFIG. 4, the controller180includes a pulse width modulator181, a gate drive voltage generator183, a max duty detector185, a boost voltage detector187, and a regulation signal generator189.

The pulse width modulator181may receive the clock signal CLK and the output voltage VOUT. The pulse width modulator181may output a pulse width modulation signal PWM having a pulse width that varies depending on a level of the output voltage VOUT. The pulse width modulation signal PWM is transmitted to the gate drive voltage generator183.

The gate drive voltage generator183may output the first and second driving signals DRV1and DRV2in response to the pulse width modulation signal PWM. For example, the gate drive voltage generator183may increase (or decrease) a high level interval or a low level interval of the first driving signal DRV1or the second driving signal DRV2as a pulse width of the pulse width modulation signal PWM increases.

The first and second driving signals DRV1and DRV2may be complementary. If the high level interval of the first driving signal DRV1increases (or the low level interval thereof decreases), the high level interval of the second driving signal DRV2may decrease (or the low level interval thereof may increase). Likewise, if the high level interval of the first driving signal DRV1decreases (or the low level interval thereof increases), the high level interval of the second driving signal DRV2may increase (or the low level interval thereof may decrease).

The pulse width modulator181and the gate drive voltage generator183may adjust lengths of high level intervals or low level intervals of the first and second driving signals DRV1and DRV2depending on a level of the output voltage VOUT. The output voltage VOUT may be controlled to a target level by adjusting the first and second driving signals DRV1and DRV2.

The max duty detector185receives the clock signal CLK and the first driving signal DRV1. The max duty detector185may determine whether the second driving signal DRV2has the max duty in response to the clock signal CLK and the first driving signal DRV1. The max duty detector185may output the determination result as a max duty signal DMAX.

If the second driving signal DRV2has the max duty, the max duty detector185may activate the max duty signal DMAX (or may make the max duty signal DMAX high). If the second driving signal DRV2does not have the max duty, the max duty detector185may deactivate the max duty signal DMAX (or may make the max duty signal DMAX low).

The boost voltage detector187may receive the boost voltage VBST and the switch voltage VSW. The boost voltage detector187may determine whether a difference between the boost voltage VBST and the switch voltage VSW is less than a reference voltage. If the difference is less than the reference voltage, the boost voltage detector187may activate a boost voltage signal DVBST (or may make the boost voltage signal DVBST low). If the difference is not less than the reference voltage, the boost voltage detector187may deactivate the boost voltage signal DVBST (or may make the boost voltage signal DVBST high).

The regulation signal generator189may receive the clock signal CLK, the max duty signal DMAX, the boost voltage signal DVBST, the pulse skip signal PSK, and the second driving signal DRV2. The regulation signal generator189may control first to fourth control signals CP_S1to CP_S4in response to the clock signal CLK, the max duty signal DMAX, the boost voltage signal DVBST, the pulse skip signal PSK, and the second driving signal DRV2.

The first to fourth control signals CP_S1to CP_S4may be transmitted to the regulator190. The regulation signal generator189may allow the regulator190to operate in one of at least three modes including the input voltage pumping mode, the output voltage pumping mode, and the normal mode, by using the first to fourth control signals CP_S1to CP_S4.

FIG. 5illustrates an example of the max duty detector185according to an example embodiment of the inventive concepts. The max duty detector185may determine the max duty of the second driving signal DRV2in response to the clock signal CLK and the first driving signal DRV1. Referring toFIGS. 4 and 5, the max duty detector185includes first to third blocks185a,185b, and185cand a flip-flop185d.

In an example embodiment, the max duty detector185may detect the max duty of the second driving signal DRV2from the first driving signal DRV1based on a complementary characteristic of the first and second driving signals DRV1and DRV2. However, the scope and spirit of the inventive concepts are not limited thereto. In some example embodiments, the max duty detector185may detect the max duty directly from the second driving signal DRV2.

The first block185amay periodically output a max duty detection pulse DMD for detecting the max duty of the second driving signal DRV2. The first block185amay include a first delay185a1, a first inverter185a2, and a first AND element185a3.

The first delay185a1may delay the clock signal CLK to output a delayed clock signal CLKP. The first inverter185a2may invert the clock signal CLK to output an inverted clock signal CLKB. The first AND element185a3may perform an AND operation on the delayed clock signal CLKP and the inverted clock signal CLKB to output the max duty detection pulse DMD.

The second block185bmay output a reset signal RST representing that the second driving signal DRV2does not have the max duty. The second block185bmay include a second AND element185b1, a second delay185b2, and a third AND element185b3. The second AND element185b1may output the result of performing an AND operation on the max duty detection pulse DMD and the first driving signal DRV1as a first internal signal A1.

The second delay185b2may delay the first internal signal A1to output a second internal signal A2. The third AND element185b3may output the result of performing an AND operation on the first and second internal signals A1and A2as the reset signal RST. The reset signal RST may be transmitted to a reset input of the flip-flop185d.

In an example embodiment, the second delay185b2and the third AND element185b3may prevent or mitigate the reset signal RST from fluctuating when a level of the max duty detection pulse DMD or the first driving signal DRV1is converted. In an anti-fluctuation system, the output of the second AND element185b1may be used as the reset signal RST.

The third block185cmay output a set signal SET representing that the second driving signal DRV2has the max duty. The set signal SET may be transmitted to a set input of the flip-flop185d. The third block185cmay include a second inverter185c1, a fourth AND element185c2, a third delay185c3, and a fifth AND element185c4.

The second inverter185c1may invert the first driving signal DRV1to output an inverted first driving signal DRV1B. The fourth AND element185c2may output the result of performing an AND operation on the max duty detection pulse DMD and the inverted first driving signal DRV1B as a third internal signal A3.

The third delay185c3may delay the third internal signal A3to output a fourth internal signal A4. The fifth AND element185c4may output the result of performing an AND operation on the third and fourth internal signals A3and A4as the set signal SET. The output of the flip-flop185dmay be set in response to the set signal SET and may be reset in response to the reset signal RST. The output of the flip-flop185dmay be the max duty signal DMAX. The flip-flop185dmay include a set-reset flip-flop (SRFF).

In an example embodiment, the third delay185c3and the fifth AND element185c4may prevent or mitigate the set signal SET from fluctuating when a level of the max duty detection pulse DMD or the first driving signal DRV1is converted. In an anti-fluctuation system, the output of the fourth AND element185c2may be used as the set signal SET.

FIG. 6illustrates an example in which the max duty detection signal DMD is generated from the clock signal CLK, the inverted clock signal CLKB, and the delayed clock signal CLKP. Referring toFIGS. 2, 5, and 6, the inverted clock signal CLKB may have an inverted waveform of the clock signal CLK. The delayed clock signal CLKP may have a waveform of the inverted clock signal CLKB delayed as much as a delay time DT.

The max duty detection pulse DMD may be generated through a logical AND of the inverted clock signal CLKB and the delayed clock signal CLKP. Accordingly, the max duty detection pulse DMD has high levels in intervals in which the inverted clock signal CLKB and the delayed clock signal CLKP all have a high level.

The max duty detection pulse DMD has low levels in intervals in which at least one of the inverted clock signal CLKB and the delayed clock signal CLKP has a low level. The max duty detection pulse DMD is illustrated inFIG. 6as first to fifth pulses P1to P5having a high level periodically. In an example embodiment, a delay amount of the first delay185a1may be adjusted to set a pulse width of the max duty detection pulse DMD to a desired value.

FIG. 7illustrates an example in which the second block185bgenerates the reset signal RST as a pulse width of the first driving signal DRV1changes. Referring toFIGS. 2, 5, and7, the first to fifth pulses P1to P5are illustrated as the max duty detection pulse DMD. The pulse width of the first driving signal DRV1may gradually decrease. That is, the pulse width of the second driving signal DRV2may gradually increase.

For example, the pulse width of the first driving signal DRV1may gradually decrease with regard to the first to third pulses P1to P3. A pulse of the first driving signal DRV1may not be generated with regard to the fourth and fifth pulses P4and P5. The second driving signal DRV2may have the max duty with regard to the fourth and fifth pulses P4and P5.

The internal signal A1may be generated by performing an AND operation on the max duty detection pulse DMD and the first driving signal DRV1. Accordingly, when the max duty detection pulse DMD and the first driving signal DRV1all have a high level, the first internal signal A1has a high level. When at least one of the max duty detection pulse DMD and the first driving signal DRV1has a low level, the first internal signal A1has a low level.

The second internal signal A2may be a signal generated by delaying the first internal signal A1. The reset signal RST is generated by performing an AND operation on the first and second internal signals A1and A2. Accordingly, when the first and second internal signals A1and A2all have a high level, the reset signal RST may have a high level.

With regard to the first and second pulses P1and P2, the first and second internal signals A1and A2have an interval in which high levels thereof overlap with each other. Accordingly, the second block185bmay output (or activate) the reset signal RST with regard to the first and second pulses P1and P2. That is, with regard to the first and second pulses P1and P2, the second block185bmay determine that the second driving signal DRV2does not have the max duty.

The max duty signal DMAX, which is the output of the flip-flop185d, may be periodically reset in response to the activated reset signal RST. For example, with regard to the first and second pulses P1and P2, the flip-flop185dmay reset the max duty signal DMAX to a low level.

With regard to the third to fifth pulses P3to A5, the first and second internal signals A1and A2do not have an interval in which high levels thereof overlap with each other. Accordingly, with regard to the third to fifth pulses P3to P5, the second block185bmay not output (or activate) the reset signal RST. For example, the second block185bmay not determine that the second driving signal DRV2does not have the max duty.

FIG. 8illustrates an example in which the third block185cgenerates the set signal SET as a pulse width of the first driving signal DRV1changes. Referring toFIGS. 2, 5, and 8, the first to fifth pulses P1to P5are illustrated as the max duty detection pulse DMD. The pulse width of the first driving signal DRV1may gradually decrease. That is, the pulse width of the second driving signal DRV2may gradually increase.

The inverted first driving signal DRV may be an inverted waveform of the first driving signal DRV1. The third internal signal A3may be generated by performing an AND operation on the max duty detection pulse DMD and the inverted first driving signal DRV1B. Accordingly, the third internal signal A3has high levels in intervals where the max duty detection pulse DMD and the inverted first driving signal DRV1B all have high levels.

The fourth internal signal A4may be a signal generated by delaying the third internal signal A3. The set signal SET is generated by performing an AND operation on the third and fourth internal signals A3and A4. Accordingly, the set signal SET may have high levels in intervals where the third and fourth internal signals A3and A4all have high levels.

With regard to the first and second pulses P1and P2, the third internal signal A3does not have a high level. Accordingly, with regard to the first and second pulses P1and P2, the third block185cmay not output (or activate) the set signal SET. With regard to the third to fifth pulses P3to P5, the third internal signal A3has high levels.

With regard to the third to fifth pulses P3to P5, the third and fourth internal signals A3and A4have intervals in which high levels thereof overlap with each other. Accordingly, with regard to the third to fifth pulses P3to P5, the third block185cmay output (or activate) the set signal SET representing that the second driving signal DRV2has the max duty.

As the third block185cactivates the set signal SET, the flip-flop185dmay activate the max duty signal DMAX to a high level. For example, with regard to the third to fifth pulses P3to P5, the third block185cmay periodically set the max duty signal DMAX of the flip-flop185dto a high level.

The inventive concepts are not limited to the case that the max duty detector185activates the max duty signal DMAX only when the second driving signal DRV2completely has the max duty. In some example embodiments, the max duty detector185may activate the max duty signal DMAX when the duty ratio of the second driving signal DRV2is greater than a threshold value. The threshold value may be determined by parameters of the voltage converter100that have high levels in intervals where the third and fourth internal signals A3and A4overlap with each other.

As described above, if the duty ratio of the second driving signal DRV2(or a duty ratio of a low level of the first driving signal DRV1) is greater than the threshold value, the max duty detector185may activate the max duty signal DMAX to a high level. If the duty ratio of the second driving signal DRV2is not greater than the threshold value, the max duty detector185may deactivate the max duty signal DMAX to a low level. Accordingly, the max duty detector185may detect the max duty of the second driving signal DRV2.

FIG. 9illustrates an example of the boost voltage detector187according to an example embodiment of the inventive concepts. Referring toFIGS. 5 and 9, the boost voltage detector187includes first to fourth resistors187ato187d, a first comparator187e, a fifth resistor187f, and a second comparator187g.

The first and second resistors187aand187bmay divide the boost voltage VBST. A first voltage V1, which is the result obtained by dividing the boost voltage VBST by the first and second resistors187aand187b, may be transmitted to a positive input of the first comparator187e. The third and fourth resistors187cand187dmay divide the switch voltage VSW. A second voltage V2, which is the result obtained by dividing the switch voltage VSW by the third and fourth resistors187cand187d, may be transmitted to a negative input of the first comparator187e.

In an example embodiment, a division ratio of the first and second resistors187aand187band a division ratio of the third and fourth resistors187cand187dmay be the same. That is, a difference between the first and second voltages V1and V2may be proportional to a difference between the boost voltage VBST and the switch voltage VSW.

The first comparator187emay compare the first voltage V1and the second voltage V2. The first comparator187emay output a third voltage V3that is proportional to a difference between the first voltage V1and the second voltage V2. The third voltage V3may be proportional to a difference between the boost voltage VBST and the switch voltage VSW. The third voltage V3may be transmitted to a positive input of the second comparator187g.

The fifth resistor187fmay allow the third voltage V3to be generated at an output of the first comparator187e. The second comparator187gmay compare the third voltage V3and a reference voltage VREF. If the third voltage V3is greater than the reference voltage VREF, that is, if a difference between the boost voltage VBST and the switch voltage VSW (or a voltage proportional to the difference) is greater than the reference voltage VREF, the second comparator187gmay deactivate the boost voltage signal DVBST (or may make the boost voltage signal DVBST high).

If the third voltage V3is not greater than the reference voltage VREF, that is, if the difference between the boost voltage VBST and the switch voltage VSW (or the voltage proportional to the difference) is not greater than the reference voltage VREF, the second comparator187gmay activate the boost voltage signal DVBST (or may make the boost voltage signal DVBST low).

If the boost voltage signal DVBST is deactivated (e.g., to a high level), the boost voltage VBST is determined as being sufficiently greater than the switch voltage VSW. For example, the boost voltage VBST is determined to be sufficient if the second gate driver150drives the second transistor130to be turned on.

If the boost voltage signal DVBST is activated (e.g., to a low level), the boost voltage VBST is determined as being not sufficiently greater than the switch voltage VSW. For example, the boost voltage VBST is determined to be insufficient if the second gate driver150fails to drive the second transistor130to be turned on.

FIG. 10illustrates an example of the regulation signal generator189according to an example embodiment of the inventive concepts. Referring toFIGS. 2, 5, and 10, the regulation signal generator189includes a status determination block189aand a regulation signal generation block189b. The status determination block189amay determine the status of the voltage converter100in response to the max duty signal DMAX, the boost voltage signal DVBST, and the pulse skip signal PSK.

The status determination block189amay control first and second signals S1and S2based on the determined status. For example, if a difference between the boost voltage VBST and the switch voltage VSW is less than a reference voltage or if it is determined that the voltage converter100exist from the pulse skip mode, and thus, the boost voltage VBST is insufficient, the status determination block189amay activate the first signal S1to a high level.

In the case where the boost voltage VBST is sufficient, the status determination block189amay deactivate the first signal S1to a low level. If the boost voltage VBST is sufficient, but that the second driving signal DRV2is determined to have the max duty (refer to operation S130ofFIG. 3), the status determination block189amay activate the second signal S2to a high level.

The status determination block189aincludes a first status determination inverter189a_1, a first status determination AND element189a_2, a status determination NOR element189a_3, a second status determination inverter189a_4, and a second status determination AND element189a_5. The first status determination inverter189a_1may invert and output the boost voltage signal DVBST.

The first status determination AND element189a_2may output a logical product of the boost voltage signal DVBST and the pulse skip signal PSK. The status determination NOR element189a_3may output logical NOR of an output of the first status determination inverter189a_1and an output of the first status determination AND element189a_2.

The second status determination inverter189a_4may invert the output of the status determination NOR element189a_3to output the first signal S1. The second status determination AND element189a_5may output a logical product of the max duty signal DMAX and the output of the status determination NOR element189a_3to output the second signal S2.

If the boost voltage signal DVBST has a low level (e.g., the boost voltage VBST is not sufficiently high) or the pulse skip signal PSK has a high level (e.g., if the voltage converter100exits from the pulse skip mode), the status determination block189amay determine that the boost voltage VBST is insufficient (refer to operation S110ofFIG. 3). The first signal S1may have values of Table 1 depending on the boost voltage signal DVBST and the pulse skip signal PSK.

If the boost voltage VBST is sufficient, but the second driving signal DRV2has the max duty, the status determination block189amay activate the second signal S2. The second signal S2may have values of Table 2 depending on the first signal S1and the max duty signal DMAX.

The regulation signal generation block189bmay control the first to fourth control signals CP_S1to CP_S4in response to the first and second signals S1and S2, the clock signal CLK, and the second driving signal DRV2. The regulation signal generation block189bincludes a first regulation inverter189b_1, a regulation NAND element189b_2, a second regulation inverter189b_3, a first regulation AND element189b_4, a regulation NOR element189b_5, a second regulation AND element189b_6, a regulation OR element189b_7, a third regulation inverter189b_8, a regulation NOR element189b_9, and a fourth regulation inverter189b_10.

The first regulation inverter189b_1may invert the clock signal CLK to output the inverted clock signal CLKB. The regulation NAND element189b_2may output the result of performing a NAND operation on the second driving signal DRV2, the inverted clock signal CLKB, and the second signal S2as a third signal S3.

The second regulation inverter189b_3may invert the third signal S3to output the second control signal CP_S2. The first regulation AND element189b_4may output the result of performing an AND operation on the third signal S3, the clock signal CLK, and the second signal S2as a fourth signal S4. The regulation NOR element189b_5may output the result of performing a NOR operation on the second signal S2and the first signal S1as a fifth signal S5.

The second regulation AND element189b_6may output the result of performing an AND operation on the first signal S1and the clock signal CLK as a sixth signal S6. The regulation OR element189b_7may output the result of performing an OR operation on the fourth signal S4, the fifth signal S5, and the sixth signal S6as the first control signal CP_S1.

The third regulation inverter189b_8may invert the first signal S1to output a seventh signal S7. The regulation NOR element189b_9may output the result of performing a NOR operation on the seventh signal S7and the sixth signal S6as the fourth control signal CP_S4. The fourth regulation inverter189b_10may invert the first signal S1to output the third control signal CP_S3. The first to fourth control signals CP_S1to CP_S4may be transmitted to the regulator190.

FIG. 11illustrates an example of the regulator190according to an example embodiment of the inventive concepts. Referring toFIGS. 2 and 11, the regulator190includes first to fourth transistors191ato194a, first to fourth drivers191bto194b, a level shifter192c, first to third diodes195ato195c, and a capacitor196.

The first and second transistors191aand192aare connected in series between the ground node GND and the input node NIN. A node between the first and second transistors191aand192amay be a low node LN. A gate voltage of the first transistor191ais controlled by the first driver191b. A gate voltage of the second transistor192ais controlled by the second driver192b.

The third and fourth transistors193aand194aare connected in series between the ground node GND and the output node NOUT. A gate voltage of the third transistor193ais controlled by the third driver193b. A gate voltage of the fourth transistor194ais controlled by the fourth driver194b.

A cathode of the first diode195ais connected to the low node LN. An anode of the first diode195ais connected to a node between the third and fourth transistors193aand194a. The second and third diodes195band195care connected in series between a power node, to which the power supply voltage VDD is supplied, and the boost node NBST. A node between the second and third diodes195band195cmay be a high node HN.

The first driver191bis biased by the power supply voltage VDD and the ground voltage of the ground node GND. The first driver191bmay operate in response to the first control signal CP_S1. The second driver192bis biased by a high boost voltage VBST_H of the high node HN and a low boost voltage VBST_L of the low node LN.

The second driver192bmay be controlled according to a signal that is generated by translating a level of the second control signal CP_S2at the level shifter192c. For example, the level shifter192cmay translate (e.g., increase) a level of the second control signal CP_S2to a level defined by the high boost voltage VBST_H and the low boost voltage VBST_L.

The third driver193bis biased by the power supply voltage VDD and the ground voltage. The third driver193bmay be controlled by the third control signal CP_S3. The fourth driver194bis biased by the power supply voltage VDD and the ground voltage. The fourth driver194bis controlled by the fourth control signal CP_S4. The capacitor196is connected between the high node HN and the low node LN.

FIG. 12illustrates an example of signals associated with the regulation signal generation block189bwhen the first signal S1and the second signal S2are deactivated. That is,FIG. 12illustrates signals when the voltage converter100is at a normal state. In other words,FIG. 12illustrates signals when a difference between the boost voltage and the switch voltage is not less than a reference voltage, when the voltage converter does not exit from a pulse skip mode, and when a duty ratio of the gate voltage of the second transistor is not greater than a threshold value. Referring toFIGS. 2, 10, and 12, the clock signal CLK and the second driving signal DRV2are illustrated.

The third signal S3has a low level when the second signal S2is at a high level (e.g., is activated), the clock signal CLK is at a low level, and the second driving signal DRV2is at a high level. BecauseFIG. 12assumes that the second signal S2is at a low level (e.g., is deactivated), the third signal S3is fixed to a high level.

The fourth signal S4has a high level when the third signal S3, the clock signal CLK, and the second signal S2all are at a high level. BecauseFIG. 12assumes that the second signal S2is at a low level (e.g., is deactivated), the fourth signal S4is fixed to a low level. The fifth signal S5has a high level when both the first and second signals S1and S2are at a low level. BecauseFIG. 12assumes that both the first signal S1and the second signal S2are at a low level, the fifth signal S5is fixed to a high level.

The sixth signal S6has a high level when both the first signal S1and the clock signal CLK are at a high level. BecauseFIG. 12assumes that the first signal S1is at a low level, the sixth signal S6is fixed to a low level. The first control signal CP_S1has a low level only when all the fourth to sixth signals S4to S6are at a low level. BecauseFIG. 12assumes that the fifth signal S5is at a high level, the first control signal CP_S1is fixed to a high level.

The second control signal CP_S2may be an inverted version of the third signal S3. Because the third signal S3is at a high level, the second control signal CP_S2is fixed to a low level. The third control signal CP_S3may be an inverted version of the first signal S1. BecauseFIG. 12assumes that the first signal S1is at a low level, the third control signal CP_S3is fixed to a high level.

The fourth control signal CP_S4has a high level only when both the sixth and seventh signals S6and S7are at a low level. The sixth signal S6may be an inverted version of the first signal S1. Accordingly, the fourth control signal CP_S4has a high level only when the first signal S1is at a high level and the sixth signal S6is at a low level. Because the first signal S1has a low level, the fourth control signal CP_S4is fixed to a low level.

FIG. 13illustrates how the regulator190is controlled by signals ofFIG. 12. Referring toFIGS. 2, 12, and 13, because the second and fourth control signals CP_S2and CP_S4are fixed to a low level, the second and fourth transistors192aand194amaintain a turn-off state. Because the first and third control signals CP_S1and CPS_3are fixed to a high level, the first and third transistors191aand193amaintain a turn-on state.

A voltage of the low node LN is a ground voltage. The power supply voltage VDD is supplied to the boost node NBST through the second and third diodes195band195c. While the first transistor120is turned on, the boost capacitor CBST is charged by the power supply voltage VDD output from the regulator190.

At timing when the first transistor120is turned off and the second transistor130is turned on, the boost voltage VBST may be greater than the switch voltage VSW by a voltage (e.g., the power supply voltage VDD) charged in the boost capacitor CBST. Accordingly, the second gate driver150may turn on the second transistor130based on the boost voltage VBST.

FIG. 14illustrates an example of signals associated with the regulation signal generation block189bwhen the first signal S1is activated and the second signal S2are deactivated. That is,FIG. 14illustrates signals that are controlled to the output voltage pumping mode due to the insufficiency of the boost voltage VBST in the voltage converter100. Referring toFIGS. 2, 10, and 14, the clock signal CLK and the second driving signal DRV2are illustrated.

The third signal S3has a low level when the second signal S2is at a high level (e.g., is activated), the clock signal CLK is at a low level, and the second driving signal DRV2is at a high level. BecauseFIG. 14assumes that the second signal S2is at a low level (e.g., is deactivated), the third signal S3is fixed to a high level.

The fourth signal S4has a high level when the third signal S3, the clock signal CLK, and the second signal S2all are at a high level. BecauseFIG. 14assumes that the second signal S2is at a low level (e.g., is deactivated), the fourth signal S4is fixed to a low level. The fifth signal S5has a high level when both the first signal S1and the second signal S2are at a low level. BecauseFIG. 14assumes that the first signal S1is at a high level, the fifth signal S5is fixed to a low level.

The sixth signal S6has a high level when both the first signal S1and the clock signal CLK are at a high level. BecauseFIG. 14assumes that the first signal S1is at a high level, the sixth signal S6may have the same waveform as the clock signal CLK. The first control signal CP_S1has a low level only when all the fourth to sixth signals S4to S6are at a low level. InFIG. 14, because the fourth and fifth signals S4and S5are fixed to a low level, the first control signal CP_S1has the same waveform as the sixth signal S6.

The second control signal CP_S2may be an inverted version of the third signal S3. InFIG. 14, because the third signal S3is at a high level, the second control signal CP_S2is fixed to a low level. The third control signal CP_S3may be an inverted version of the first signal S1. BecauseFIG. 14assumes that the first signal S1is at a high level, the third control signal CP_S3is fixed to a low level.

The fourth control signal CP_S4has a high level only when the first signal S1is at a high level and the sixth signal S6is at a low level. BecauseFIG. 14assumes that the first signal S1is at a high level and the sixth signal S6switches between a high level and a low level, the fourth control signal CP_S4has an inverted waveform of the sixth signal S6. The fourth control signal CP_S4may be complementary to the first control signal CP_S1.

FIG. 15illustrates how the regulator190is controlled by signals ofFIG. 14. Referring toFIGS. 2, 14, and 15, because the second and third control signals CP_S2and CP_S3are fixed to a low level, the second and third transistors192aand193amaintain a turn-off state. As illustrated by an arrow, each of the first and fourth control signals CP_S1and CP_S4may switch between a high level and a low level and may transmit a voltage pumped from the output voltage VOUT to the boost node NBST.

When the first transistor191ais turned on and the fourth transistor194ais turned off, the capacitor196is charged with the power supply voltage VDD transmitted through the second diode195b. When the first transistor191ais turned off and the fourth transistor194ais turned on, a voltage of the high node HN increases to a voltage corresponding to a sum of the output voltage VOUT and a voltage (e.g., the power supply voltage VDD) charged in the capacitor196. That is, a voltage pumped from the output voltage VOUT by an amount as much as the power supply voltage VDD is transmitted to the boost node NBST.

FIG. 16illustrates an example of signals associated with the regulation signal generation block189bwhen the first signal S1is deactivated and the second signal S2are activated. That is,FIG. 16illustrates signals that are controlled to the input voltage pumping mode when the max duty occurs in the voltage converter100. Referring toFIGS. 2, 10, and 16, the clock signal CLK and the second driving signal DRV2are illustrated.

The third signal S3has a low level when the second signal S2is at a high level (e.g., is activated), the clock signal CLK is at a low level, and the second driving signal DRV2is at a high level. BecauseFIG. 16assumes that the second signal S2is at a high level (e.g., is activated), the third signal S3has low levels in intervals where the clock signal CLK is at a low level and the second driving signal DRV2is at a high level. In the remaining intervals, the third signal S3has a high level.

The fourth signal S4has a high level when the third signal S3, the clock signal CLK, and the second signal S2all are at a high level. BecauseFIG. 16assumes that the second signal S2is at a high level (e.g., is activated), the fourth signal S4has high levels in intervals where the third signal S3and the clock signal CLK are at a high level. In the remaining intervals, the fourth signal S4has low levels.

The fifth signal S5has a high level when the first and second signals S1and S2all are at a low level. BecauseFIG. 16assumes that the second signal S2is at a high level, the fifth signal S5is fixed to a low level. The sixth signal S6has a high level when the first signal S1and the clock signal CLK all are at a high level. BecauseFIG. 16assumes that the first signal S1is at a low level, the sixth signal S6is fixed to a low level.

The first control signal CP_S1has a low level only when the fourth to sixth signals S4to S6all are at a low level. BecauseFIG. 16assumes that the fifth and sixth signals S5and S6are fixed to a low level, the first control signal CP_S1has the same waveform as the fourth signal S4. The second control signal CP_S2may be an inverted version of the third signal S3.

The third control signal CP_S3may be an inverted version of the first signal S1. BecauseFIG. 16assumes that the first signal S1is at a low level, the third control signal CP_S3is fixed to a high level. The fourth control signal CP_S4has a high level only when the first signal S1is at a high level and the sixth signal S6is at a low level. BecauseFIG. 16assumes that the first signal S1is at a low level, the fourth control signal CP_S4is fixed to a low level.

The first and second control signals CP_S1and CP_S2may be complementary in intervals where the second driving signal DRV2is at a high level. For example, in intervals where the second driving signal DRV2is at a high level, if the first control signal CP_S1is at a high level, the second control signal CP_S2may be at a low level.

In intervals where the second driving signal DRV2is at a high level, if the first control signal CP_S1is at a low level, the second control signal CP_S2may be at a high level. The first and second control signals CP_S1and CP_S2may have low levels in intervals where the second driving signal DRV2is at a low level.

FIG. 17illustrates how the regulator190is controlled by signals ofFIG. 16. Referring toFIGS. 2, 16, and 17, since the fourth control signal CP_S4is fixed to a low level, the fourth transistor194amaintains a turn-off state. Because the third control signal CP_S3is fixed to a high level, the third transistor193amaintains a turn-on state.

As illustrated by an arrow, each of the first and second control signals CP_S1and CP_S2may switch between a high level and a low level in intervals where the second driving signal DRV2is at a high level and may transmit a voltage pumped from the input voltage VIN to the boost node NBST. When the first transistor191ais turned on and the second transistor192ais turned off, the capacitor196is charged with the power supply voltage VDD transmitted through the second diode195b.

When the first transistor191ais turned off and the second transistor192ais turned on, a voltage of the high node HN increases to a voltage corresponding to a sum of a voltage of the high node HN and a voltage (e.g., the power supply voltage VDD) charged in the capacitor196. That is, a voltage pumped from the input voltage VIN by an amount as much as the power supply voltage VDD is transmitted to the boost node NBST.

FIG. 18illustrates a voltage converter200according to an example embodiment of the inventive concepts. Referring toFIG. 18, the voltage converter200includes first and second transistors220and230, first and second gate drivers240and f, a level shifter260, a controller280, a regulator290, an inductor “L”, an input capacitor CIN, an output capacitor COUT, and a boost capacitor CBST.

The voltage converter200may convert an input voltage VIN of an input node NIN to an output voltage VOUT of an output node NOUT. For example, the voltage converter200may be a boost converter that steps up a level of the input voltage VIN to output the output voltage VOUT.

The first and second transistors220and230may be connected in series between a ground node GND supplied with a ground voltage and the output node NOUT. A node between the first and second input transistors120and130may be a switch node NSW. The inductor “L” is connected between the switch node NSW and the input node NIN. The input capacitor CIN is connected between the input node NIN and the ground node GND.

The boost capacitor CBST is connected between the switch node NSW and the boost node NBST. The output capacitor COUT is connected between the output node NOUT and the ground node GND. The first and second transistors220and230, the first and second gate drivers240and250, the level shifter260, the controller280, and the regulator290are the same as described with reference toFIG. 2, and thus, a description thereof will not be repeated here.

The voltage converter200may enter the input voltage pumping mode when the boost voltage VBST is insufficient. The voltage converter200may enter the output voltage pumping mode when the second driving signal DRV2has the max duty. The regulator290may have the same structure ofFIG. 11except that the input node NIN and the output node NOUT are exchanged. The controller280may have the same structure as described with reference toFIGS. 4 to 10.

According to an example embodiment of the inventive concepts, the voltage converter100or200in which switching transistors may be implemented with NMOS transistors. Because PMOS transistors are not used, the size of the voltage converter100or200may be reduced. By configuring the regulator190or290to operate in at least three modes including the normal mode, the output voltage pumping mode, and the input voltage pumping mode, the second transistor130or230can be securely turned on at all times. Accordingly, the voltage converter100or200with improved reliability can be implemented.

FIG. 19illustrates a voltage converter300according to another example embodiment of the inventive concepts. Referring toFIG. 19, the voltage converter300includes a first transistor321, a second transistor322, a third transistor323and a fourth transistor connected in series between an input node NIN to which an input voltage VIN is applied.

The voltage converter300further includes a first gate driver351, a second gate driver352, a third gate driver353and a fourth gate driver354. The first gate driver351may output a first gate driving signal GD1to turn on or turn off the first transistor351. The first gate driver351is biased with a first power supply voltage VDD1and a first voltage V1of a first node N1between the first transistor321and the second transistor322. The first gate driver351may output the first power supply voltage VDD1as a high level and output the first voltage V1as a low level.

The second gate driver352may output a second gate driving signal GD2to turn on or turn off the second transistor322. The second gate driver352is biased with a second power supply voltage VDD2and a second voltage V2of a second node N2between the second transistor322and the third transistor323. The second gate driver352may output the second power supply voltage VDD2as a high level and output the second voltage V2as a low level.

The third gate driver353may output a third gate driving signal GD3to turn on or turn off the third transistor323. The third gate driver353is biased with a third power supply voltage VDD3and a third voltage V3of a third node N3between the third transistor323and the fourth transistor324. The third gate driver353may output the third power supply voltage VDD3as a high level and output the third voltage V3as a low level.

The fourth gate driver354may output a fourth gate driving signal GD4to turn on or turn off the fourth transistor324. The fourth gate driver354is biased with a fourth power supply voltage VDD4and a ground voltage GND of a ground node. The fourth gate driver354may output the fourth power supply voltage VDD4as a high level and output the ground voltage GND as a low level.

The voltage converter300further includes a first level shifter361, a second level shifter362, a third level shifter363and a fourth level shifter364. The first level shifter361may receive a first driving signal DRV1belong to a first voltage domain between a common power supply voltage (VDD) and the ground voltage GND, shift the first voltage domain to a second voltage domain between the first power supply voltage VDD1and the first voltage V1, and output the shifted signal to the first gate driver351.

The first voltage domain may have the common power supply voltage (VDD) as a high level and the ground voltage GND as a low level. The second voltage domain may have the first power supply voltage VDD1as a high level and the first voltage V1as a low level.

The second level shifter362may receive a second driving signal DRV2belong to a second voltage domain between the common power supply voltage (VDD) and the ground voltage GND, shift the second voltage domain to a fourth voltage domain between the second power supply voltage VDD2and the second voltage V2, and output the shifted signal to the second gate driver352. The fourth voltage domain may have the second power supply voltage VDD2as a high level and the second voltage V2as a low level.

The third level shifter363may receive a third driving signal DRV3belong to a fifth voltage domain between the common power supply voltage (VDD) and the ground voltage GND, shift the fifth voltage domain to a sixth voltage domain between the third power supply voltage VDD3and the third voltage V3, and output the shifted signal to the third gate driver353. The sixth voltage domain may have the third power supply voltage VDD3as a high level and the third voltage V3as a low level.

The fourth level shifter364may receive a fourth driving signal DRV4belong to a seventh voltage domain between the common power supply voltage (VDD) and the ground voltage GND, shift the seventh voltage domain to a eighth voltage domain between the fourth power supply voltage VDD4and the ground voltage GND, and output the shifted signal to the fourth gate driver354. The eighth voltage domain may have the fourth power supply voltage VDD4as a high level and the ground voltage GND as a low level.

The voltage converter300further includes a controller380. The controller380may receive a first clock signal CLK1. The controller380may control the first driving signal DRV1, the second driving signal DRV2, the third driving signal DRV3and the fourth driving signal DRV4for turning on or turning off the first transistor321, the second transistor322, the third transistor323and the fourth transistor324respectively based on the first clock signal CLK1.

The controller380may control the first driving signal DRV1and the third driving signal DRV3identically. The controller380may turn on or turn off the first transistor321and the third transistor323simultaneously. The controller380may control the second driving signal DRV2and the fourth driving signal DRV4identically. The controller380may turn on or turn off the second transistor322and the fourth transistor324simultaneously.

The controller380may control the first driving signal DRV1(or the third driving signal DRV3) and the second driving signal DRV2(or the fourth driving signal DRV4) complementally. When the controller380turns on the first transistor321and the third transistor323, the controller380turns off the second transistor322and the fourth transistor324. When the controller380turns off the first transistor321and the third transistor323, the controller380turns on the second transistor322and the fourth transistor324.

The controller380may generate a second clock signal CLK2based on the first clock signal CLK1. The controller may output the second clock signal CLK2to a regulator390.

The voltage converter300may further include the regulator390. The regulator390receives the input voltage VIN, the first voltage V1, the second voltage V2, the third voltage V3and the second clock signal CLK2. The paths delivering the first voltage V1, the second voltage V2and the third voltage V3are omitted to avoid unnecessary complexity of the drawing.

The regulator390may generate the first power supply voltage VDD1, the second power supply voltage VDD2, the third power supply voltage VDD3and the fourth power supply voltage VDD4based on the input voltage VIN, the first voltage V1, the second voltage V2, the third voltage V3and the second clock signal CLK2.

The regulator390may control the first power supply voltage VDD1being higher than the first voltage V1such that the first gate driving signal GD1is able to turn on the first transistor321when the first gate driving signal GD1has a high level which is the first power supply voltage VDD1.

The regulator390may control the second power supply voltage VDD2being higher than the second voltage V2such that the second gate driving signal GD2is able to turn on the second transistor322when the second gate driving signal GD2has a high level which is the second power supply voltage VDD2.

The regulator390may control the third power supply voltage VDD3being higher than the third voltage V3such that the third gate driving signal GD3is able to turn on the third transistor323when the third gate driving signal GD3has a high level which is the third power supply voltage VDD3.

The regulator390may control the fourth power supply voltage VDD4being higher than the ground voltage GND such that the fourth gate driving signal GD4is able to turn on the fourth transistor324when the fourth gate driving signal GD4has a high level which is the fourth power supply voltage VDD4.

The voltage converter300may further include a output capacitor COUT and a flying capacitor CFLY. The output capacitor COUT is connected between the second node N2and the ground node. The flying capacitor CFLY is connected between the first node N1and the third node N3. The second node N2may be an output node NOUT from which the second voltage V2is output as a output voltage VOUT.

The first transistor321, the second transistor322, the third transistor323, the fourth transistor324, the first gate driver351, the second gate driver352, the third gate driver353, the fourth gate driver354, the first level shifter361, the second level shifter362, the third level shifter363, the fourth level shifter364, the controller380and the regulator390may be included in a single chip310. The output capacitor COUT and the flying capacitor CFLY may be connected to the single chip310.

In at least one example embodiment, the fourth power supply voltage VDD4may be the common power supply voltage (VDD). In this case, the eighth voltage domain of the fourth level shifter364may be identical with the seventh voltage domain. Thus, the fourth level shifter364is able to be omitted. The common power supply voltage (VDD) may be supplied from any component (not excluding the regulator390) to the fourth gate driver354. In at least one example embodiment, the first transistor321, the second transistor322, the third transistor323and the fourth transistor324may be high voltage transistors having endurances for high voltages.

FIG. 20illustrates a first phase of the voltage converter300. Only some elements of the voltage converter300which are necessary for describing the first phase are illustrated inFIG. 20. Referring toFIGS. 19 and 20, in the first phase, the controller380may turn on the first transistor321and the third transistor using the first gate driving signal GD1and the third gate driving signal. The controller380may turn off the second transistor322and the fourth transistor324using the second gate driving signal GD2and the fourth gate driving signal GD4.

The output capacitor COUT and the flying capacitor CFLY are connected in series between the input node NIN and the ground node through the first transistor321and the third transistor323. The output capacitor COUT and the flying capacitor CFLY are charged with the input voltage VIN.

FIG. 21illustrates a second phase of the voltage converter300subsequent to the first phase ofFIG. 20. Referring toFIGS. 19 and 21, in the second phase, the controller380may turn off the first transistor321and the third transistor using the first gate driving signal GD1and the third gate driving signal. The controller380may turn on the second transistor322and the fourth transistor324using the second gate driving signal GD2and the fourth gate driving signal GD4.

The output capacitor COUT and the flying capacitor CFLY are connected in parallel between the output node NOUT and the ground node through the second transistor322and the fourth transistor324. Thus, the output voltage VOUT may become a half of the input voltage VIN.

By repeating the first phase and the second phase in response to the first clock signal, the output voltage VOUT may converge on the half of the input voltage. The voltage converter300may perform 2:1 capacitor voltage division.

In at least one example embodiment, the first voltage V1may swing between the half of the input voltage VIN and the input voltage VIN. The third voltage may swing between the ground voltage and the half of the input voltage VIN. The flying capacitor CFLY may be charged with the half of the input voltage VIN.

When outputting the half of the input voltage VIN as the output voltage VOUT, the first voltage V1and the third voltage V3swing. When the first transistor321and the third transistor323are turned on, the first voltage V1and the third voltage V3increase. When the second transistor322and the fourth transistor324are turned on, the first voltage V1and the third voltage V3decrease. Thus, maintaining the first power supply voltage VDD1, the second power supply voltage VDD2and the third power supply voltage VDD3respectively being higher than the first voltage V1, the second voltage V2and the third voltage V3is very important for successfully turning on or off the first transistor321, the second transistor322, the third transistor323and the fourth transistor324.

The regulator390according to at least one example embodiment of the inventive concepts control the first power supply voltage VDD1, the second power supply voltage VDD2and the third power supply voltage VDD3respectively being higher than the first voltage V1, the second voltage V2and the third voltage V3.

FIG. 22illustrates at least one example embodiment of the regulator390. Referring toFIGS. 19 and 22, the regulator390may include a charge pump391, a first generator392, a second generator393and a third generator394.

The charge pump391may include a first Schottky diode SD1and a second Schottky diode SD2connected in series. The charge pump391may further include a first pump capacitor CP1having a first terminal connected to a node between the first Schottky diode SD1and the second Schottky diode SD2, a first pump transistor CT1connected between a second terminal of the first pump capacitor CP1and the ground node, and a second pump transistor CT2connected between the second terminal of the first pump capacitor CP1and a common power supply node through which the common power supply voltage VDD is supplied.

The first pump transistor CT1may be a NMOS transistor and have a gate controlled by the second clock signal CLK2. The second pump transistor CT2may be a PMOS transistor and have a gate controlled by the second clock signal. The first pump transistor CT1and the second pump transistor CT2may have complementary types. The regulator390may further include a second pump capacitor CP2connected in parallel with the first Schottky diode SD1and the second Schottky diode SD2.

When the second clock signal CLK2has a high level, the first pump transistor CT1may be turned on, and the second pump transistor CT2may be turned off. The first pump capacitor CP1may be charged with the input voltage VIN. When the second clock signal CLK2has a low level, the first pump transistor CT1may be turned off, and the second pump transistor CT2may be turned on. The second terminal of the first pump capacitor CP1is supplied with the common power supply voltage CDD. Thus, the first pump capacitor CP1may charge the second pump transistor with the common power supply voltage VDD.

The pump voltage VCP, which is an output voltage of the charge pump391, may be the input voltage VIN plus the common power supply voltage VDD. The pump voltage VCP is applied to the first generator392, the second generator393and the third generator394. The first Schottky diode SD1and the second Schottky diode SD2may prevent a reversal of current. In at least one example embodiment, the first pump transistor CT1and the second pump transistor CT2may be high voltage transistors.

The first generator may receive the pump voltage VCP and the first voltage V1. The first generator may include a voltage resistor RV, a first voltage Schottky diode SDV1, and a Zener diode ZD connected in series between a node through which the pump voltage VCP is supplied and another node through which the first voltage V1is supplied.

The first generator392may further include a first voltage capacitor CV1connected between the node through which the first voltage V1is supplied and another node between the first voltage Schottky diode SDV1and the Zener diode ZD. The regulator390may further include a voltage transistor TV, a second voltage Schottky diode SDV2and a second voltage capacitor CV2connected in series between the node through which the pump voltage VCP is supplied and the node through the first voltage V1is supplied.

The voltage transistor TV may be shown as a model having a body diode to help thorough understanding of the inventive concepts. Because of the body diode, there may be a reversal of current. The first voltage Schottky diode SDV1and the second voltage Schottky diode SDV2may prevent the reversal of the current.

A voltage of the node between the Zener diode ZD and the first voltage Schottky diode SDV1(hereinafter, a voltage of the Zener diode ZD) is determined by characteristics or features of the Zener diode ZD. The voltage transistor TV may flow current in response to the voltage of the Zener diode ZD. The current may cause a voltage at a node between the second voltage Schottky diode SDV2and the second voltage capacitor CV2.

The voltage of the node between the second voltage Schottky diode SDV2and the second voltage capacitor CV2may be output as the first power supply voltage VDD1. Because the voltage of the Zener diode ZD is higher than the first voltage V1, the first power supply voltage V1may be higher than the first power supply voltage.

The second generator393has the same structure with the first generator392. Instead of receiving the first voltage V1and outputting the first power supply voltage VDD1, the second generator393may receive the second voltage V2and output the second power supply voltage VDD2higher than the second voltage V2.

The third generator394has the same structure with the first generator392. Instead of receiving the first voltage V1and outputting the first power supply voltage VDD1, the third generator394may receive the third voltage V3and output the third power supply voltage VDD3higher than the third voltage V3. The regulator390may output the common power supply voltage VDD as the fourth power supply voltage VDD.

InFIG. 22, the first voltage Schottky diode SDV1, the second voltage Schottky diode SDV2, the first voltage capacitor CV1, the second voltage capacitor CV2and the voltage transistor TV are named using a term ‘voltage’. The term ‘voltage’ merely means that these elements are related with generating a voltage, and does not limit the scope and sprit of the inventive concepts.

In at least one example embodiment, the charge pump391may be implemented with the regulator190which operates as shown inFIG. 17. In at least one example embodiment, when the voltage converter300employs additional transistors between the input node NIN and the ground node, additional power supply voltages for the additional transistors may be obtained by adding generators as shown inFIG. 22. Thus, the voltage converter300provides enhanced flexibility.

In the above-described example embodiments, components according to example embodiments of the inventive concepts are referred to by using the term “block”. The “block” may be implemented with various hardware devices, such as an integrated circuit, an application specific IC (ASCI), a field programmable gate array (FPGA), and a complex programmable logic device (CPLD), software, such as firmware and applications driven in hardware devices, or a combination of a hardware device and software. Also, “block” may include circuits or intellectual property (IP) implemented with semiconductor devices.

According to at least one example embodiment of the inventive concepts, a voltage converter adjusts a gate voltage of a switching transistor such that the switching transistor is turned on according to a change in environment. Accordingly, the voltage converter with improved reliability and/or an operating method thereof may be provided.