Semiconductor devices including control logic levels, and related memory devices, control logic assemblies, electronic systems, and methods

A semiconductor device comprises a stack structure comprising decks each comprising a memory element level comprising memory elements, and a control logic level in electrical communication with the memory element level and comprising control logic devices. At least one of the control logic devices of the control logic level of one or more of the decks comprises at least one device exhibiting transistors laterally displaced from one another. A memory device, a thin film transistor control logic assembly, an electronic system, and a method of operating a semiconductor device are also described.

TECHNICAL FIELD

Embodiments of the disclosure relate to the field of semiconductor device design and fabrication. More specifically, embodiments of the present disclosure relate to semiconductor devices including stack structures having control logic levels in decks thereof, and to related memory devices, control logic assemblies, electronic systems, and methods of operating a semiconductor device.

BACKGROUND

Semiconductor device designers often desire to increase the level of integration or density of features within a semiconductor device by reducing the dimensions of the individual features and by reducing the separation distance between neighboring features. In addition, semiconductor device designers often desire to design architectures that are not only compact, but offer performance advantages, as well as simplified designs.

One example of a semiconductor device is a memory device. Memory devices are generally provided as internal integrated circuits in computers or other electronic devices. There are many types of memory including, but not limited to, random-access memory (RAM), read-only memory (ROM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), Flash memory, and resistance variable memory. Non-limiting examples of resistance variable memory include resistive random access memory (ReRAM), conductive bridge random access memory (conductive bridge RAM), magnetic random access memory (MRAM), phase change material (PCM) memory, phase change random access memory (PCRAM), spin-torque-transfer random access memory (STTRAM), oxygen vacancy-based memory, and programmable conductor memory.

A typical memory cell of a memory device includes one access device, such as a transistor, and one memory storage structure, such as a capacitor. Modern applications for semiconductor devices can employ significant quantities of memory cells, arranged in memory arrays exhibiting rows and columns of the memory cells. The memory cells may be electrically accessed through digit lines (e.g., bit lines) and word lines (e.g., access lines) arranged along the rows and columns of the memory cells of the memory arrays. Memory arrays can be two-dimensional (2D) so as to exhibit a single deck (e.g., a single tier, a single level) of the memory cells, or can be three-dimensional (3D) so as to exhibit multiple decks (e.g., multiple levels, multiple tiers) of the memory cells.

Control logic devices within a base control logic structure underlying a memory array of a memory device have been used to control operations (e.g., access operations, read operations, write operations) on the memory cells of the memory device. An assembly of the control logic devices may be provided in electrical communication with the memory cells of the memory array by way of routing and interconnect structures. However, as the number of decks of a 3D memory array increases, electrically connecting the memory cells of the different decks of the 3D memory array to the assembly of control logic devices within the base control logic structure can create sizing and spacing complications associated with the increased quantities and dimensions of routing and interconnect structures required to facilitate the electrical connection. In addition, the quantities, dimensions, and arrangements of the different control logic devices employed within the base control logic structure can also undesirably impede reductions to the size of a memory device, increases to the storage density of the memory device, and/or reductions in fabrication costs.

It would, therefore, be desirable to have improved semiconductor devices, control logic assemblies, and control logic devices facilitating higher packing densities, as well as methods of forming the semiconductor devices, control logic assemblies, and control logic devices.

DETAILED DESCRIPTION

Semiconductor devices including stack structures having control logic levels in decks thereof are described, as are memory devices, control logic assemblies, electronic systems, and methods of operating a semiconductor device. In some embodiments, a semiconductor device includes a stack structure including multiple decks (e.g., tiers) each individually including a control logic level (e.g., a TFT control logic level), an access device level on or over the control logic level, and a memory element level on or over the access device level. The control logic level of each individual deck of the stack structure is in electrical communication with the access device level and the memory element level of the individual deck. The control logic level of each individual deck of the stack structure may also be in electrical communication with a base control logic structure of the semiconductor device. The control logic level of each of the decks of the stack structure includes control logic devices and circuitry for controlling different operations of the memory element level and the access device level associated therewith. The control logic devices and circuitry included in the control logic level of each of the decks of the stack structure are different than additional control logic devices and circuitry included in the base control logic structure of the semiconductor device. The additional control logic devices and circuitry included in the base control logic structure work in conjunction with the control logic devices and circuitry included in the control logic level of each of the decks of the stack structure to facilitate desired operations (e.g., access operations, read operations, write operations) of the semiconductor device. In addition, the control logic devices included in the control logic level of at least one deck of the stack structure include at least one device including transistors (e.g., vertical transistors, horizontal transistors, fin field-effect transistors (FinFETs)) laterally (e.g., horizontally) displaced (e.g., spaced apart, separated) from one another. The devices, structures, assemblies, systems, and methods of the disclosure may facilitate increased efficiency, performance, simplicity, and durability in semiconductor devices (e.g., 3D memory devices) that rely on high packing density.

The following description provides specific details, such as material types, material thicknesses, and processing conditions in order to provide a thorough description of embodiments of the disclosure. However, a person of ordinary skill in the art will understand that the embodiments of the disclosure may be practiced without employing these specific details. Indeed, the embodiments of the disclosure may be practiced in conjunction with conventional fabrication techniques employed in the industry. In addition, the description provided below does not form a complete process flow for manufacturing a semiconductor device (e.g., a memory device). The semiconductor device structures described below do not form a complete semiconductor device. Only those process acts and structures necessary to understand the embodiments of the disclosure are described in detail below. Additional acts to form the complete semiconductor device from the semiconductor device structures may be performed by conventional fabrication techniques. Also note, any drawings accompanying the application are for illustrative purposes only, and are thus not drawn to scale. Additionally, elements common between figures may retain the same numerical designation.

As used herein, the terms “longitudinal,” “vertical,” “lateral,” and “horizontal” are in reference to a major plane of a substrate (e.g., base material, base structure, base construction, etc.) in or on which one or more structures and/or features are formed and are not necessarily defined by earth's gravitational field. A “lateral” or “horizontal” direction is a direction that is substantially parallel to the major plane of the substrate, while a “longitudinal” or “vertical” direction is a direction that is substantially perpendicular to the major plane of the substrate. The major plane of the substrate is defined by a surface of the substrate having a relatively large area compared to other surfaces of the substrate.

As used herein, the term “substantially” in reference to a given parameter, property, or condition means and includes to a degree that one of ordinary skill in the art would understand that the given parameter, property, or condition is met with a degree of variance, such as within acceptable manufacturing tolerances. By way of example, depending on the particular parameter, property, or condition that is substantially met, the parameter, property, or condition may be at least 90.0% met, at least 95.0% met, at least 99.0% met, at least 99.9% met, or even 100.0% met.

As used herein, the term “NMOS” transistor means and includes a so-called metal-oxide transistor having a P-type channel region. The gate of the NMOS transistor may comprise a conductive metal, another conductive material, such as polysilicon, or a combination thereof. As used herein, the term “PMOS” transistor means and includes a so-called metal-oxide transistor having an N-type channel region. The gate of the PMOS transistor may comprise a conductive metal, another conductive material, such as polysilicon, or a combination thereof. Accordingly, the gate structures of such transistors may include conductive materials that are not necessarily metals.

FIG. 1shows a simplified side elevation view of a semiconductor device100(e.g., a 3D memory device), in accordance with embodiments of the disclosure. As shown inFIG. 1, the semiconductor device100includes a base control logic structure102, and a stack structure103overlying the base control logic structure102. As described in further detail below, the stack structure103includes decks104(e.g., tiers) each individually including a thin film transistor (TFT) control logic level, an access device level over the TFT control logic level, a memory element level over the access device level, and interconnect structures extending between the TFT control logic level and each of the access device level and the memory element level. Each TFT control logic level of the decks104may individually include one or more control logic devices (e.g., CMOS devices) exhibiting neighboring, laterally displaced transistors (e.g., NMOS transistors, PMOS transistors), as also described in further detail below. The base control logic structure102is in electrical communication with one or more (e.g., each) of the decks104of the stack structure103by way of interconnect structures112extending between the base control logic structure102and one or more levels (e.g., the TFT control logic level) of the one or more decks104of the stack structure103.

The base control logic structure102may include devices and circuitry for controlling various operations of the stack structure103. The devices and circuitry included in the base control logic structure102may be selected relative to devices and circuitry included in the TFT control logic levels of the decks104of the stack structure103. The devices and circuitry included in the base control logic structure102may be different than the devices and circuitry included in the TFT control logic levels of the decks104of the stack structure103, and may be used and shared by different decks104of the stack structure103to facilitate desired operation of the stack structure103. By way of non-limiting example, the base control logic structure102may include one or more (e.g., each) of charge pumps (e.g., VCCPcharge pumps, VNEGWLcharge pumps, DVC2 charge pumps), delay-locked loop (DLL) circuitry (e.g., ring oscillators), drain supply voltage (Vdd) regulators, and various chip/deck control circuitry. The devices and circuitry included in the base control logic structure102may employ different conventional CMOS devices (e.g., conventional CMOS inverters, conventional CMOS NAND gates, conventional CMOS transmission pass gates, etc.), which are not described in detail herein. In turn, as described in further detail below, the devices and circuitry included in the TFT control logic level of each of the decks104of the stack structure103may not be shared by different decks104of the stack structure103, and may be dedicated to effectuating and controlling various operations (e.g., access device level operations, and memory element level operations) of the deck104associated therewith not encompassed within the functions of the devices and circuitry included in the base control logic structure102.

With continued reference toFIG. 1, the stack structure103may include any desired number of the decks104. For clarity and ease of understanding of the drawings and related description,FIG. 1shows the stack structure103as including three (3) decks104. A first deck106may include a first TFT control logic level106A, a first access device level106B on or over the first TFT control logic level106A, a first memory element level106C on or over the first access device level106B, and first interconnect structures106D extending between and electrically coupling the first TFT control logic level106A to each of the first access device level106B and the first memory element level106C. A second deck108may overlie the first deck106and may include a second TFT control logic level108A, a second access device level108B on or over the second TFT control logic level108A, a second memory element level108C on or over the second access device level108B, and second interconnect structures108D extending between and electrically coupling the second TFT control logic level108A to each of the second access device level108B and the second memory element level108C. A third deck110may overlie the second deck108and may include a third TFT control logic level110A, a third access device level110B on or over the third TFT control logic level110A, a third memory element level110C on or over the third access device level110B, and third interconnect structures110D extending between and electrically coupling the third TFT control logic level110A to each of the third access device level110B and the third memory element level110C. In additional embodiments, the stack structure103includes a different number of decks104. For example, the stack structure103may include greater than three (3) decks104(e.g., greater than or equal to four (4) decks104, greater than or equal to eight (8) decks104, greater than or equal to sixteen (16) decks104, greater than or equal to thirty-two (32) decks104, greater than or equal to sixty-four (64) decks104), or may include less than three (3) decks104(e.g., two (2) decks104).

The memory element levels (e.g., the first memory element level106C, the second memory element level108C, the third memory element level110C) of the each of the decks104(e.g., the first deck106, the second deck108, the third deck110) of the stack structure103may each individually include an array of memory elements. The array may, for example, include rows of the memory elements extending in a first lateral direction, and columns of the memory elements extending in a second lateral direction perpendicular to the first lateral direction. In additional embodiments, the array may include a different arrangement of the memory elements, such as hexagonal close packed arrangement of the memory elements. The memory elements of the array may comprise RAM elements, ROM elements, DRAM elements, SDRAM elements, Flash memory elements, resistance variable memory elements, or another type of memory element. In some embodiments, the memory elements comprise DRAM elements. In additional embodiments, the memory elements comprise resistance variable memory elements. Non-limiting examples of resistance variable memory elements include ReRAM elements, conductive bridge RAM elements, MRAM elements, PCM memory elements, PCRAM elements, STTRAM elements, oxygen vacancy-based memory elements, and programmable conductor memory elements.

The access device levels (e.g., the first access device level106B, the second access device level108B, the third access device level110B) of the each of the decks104(e.g., the first deck106, the second deck108, the third deck110) of the stack structure103may each individually include an array of access devices (e.g., TFT access devices). The access devices of the access device level (e.g., the first access device level106B, the second access device level108B, the third access device level110B) of a given deck104(e.g., the first deck106, the second deck108, the third deck110) may be operatively associated with the memory elements of the memory element level (e.g., the first memory element level106C, the second memory element level108C, the third memory element level110C) of the given deck104. The quantity and lateral positioning of the access devices of the access device level of the given deck104may, for example, correspond to the quantity and lateral positioning of the memory elements of the memory element level of the given deck104. The access devices of the access device level may underlie (or overlie) and be in electrical communication with the memory elements of the memory element level. Together the access devices of the access device level and the memory elements of the memory element level operatively associated therewith may form memory cells for each of the decks104of the stack structure103. The access devices may, for example, each individually include a channel region between a pair of source/drain regions, and a gate configured to electrically connect the source/drain regions to one another through the channel region. The access devices may comprise planar access devices (e.g., planar TFT access devices) or vertical access devices (e.g., vertical TFT access devices). Planar access devices can be distinguished from vertical access devices based upon the direction of current flow between the source and drain regions thereof. Current flow between the source and drain regions of a vertical access device is primarily substantially orthogonal (e.g., perpendicular) to a primary (e.g., major) surface of a substrate or base (e.g., the base control logic structure102) thereunder, and current flow between source and drain regions of a planar access device is primarily parallel to the primary surface of the substrate or base thereunder. In additional embodiments, the access device levels (e.g., the first access device level106B, the second access device level108B, the third access device level110B) are omitted (e.g., absent) from the decks104(e.g., the first deck106, the second deck108, the third deck110) of the stack structure103. For example, in place of the access device levels separate from the memory element levels (e.g., the first memory element level106C, the second memory element level108C, the third memory element level110C), each of the decks104of the stack structure103may include a single (e.g., only one) level including memory elements and access devices.

The TFT control logic levels (e.g., the first TFT control logic level106A, the second TFT control logic level108A, the third TFT control logic level110A) of the each of the decks104(e.g., the first deck106, the second deck108, the third deck110) of the stack structure103may include devices and circuitry for controlling various operations of the memory element level (e.g., the first memory element level106C, the second memory element level108C, the third memory element level110C) and the access device level (e.g., the first access device level106B, the second access device level108B, the third access device level110B) (or of a single level including memory elements and access devices) of the deck104not encompassed (e.g., effectuated, carried out, covered) by the devices and circuitry of the base control logic structure102. By way of non-limiting example, the TFT control logic levels may each individually include one or more (e.g., each) of decoders (e.g., local deck decoders, column decoders, row decoders), sense amplifiers (e.g., equalization (EQ) amplifiers, isolation (ISO) amplifiers, NMOS sense amplifiers (NSAs), PMOS sense amplifiers (PSAs)), word line (WL) drivers, repair circuitry (e.g., column repair circuitry, row repair circuitry), I/O devices (e.g., local I/O devices), test devices, array multiplexers (MUX), error checking and correction (ECC) devices, and self-refresh/wear leveling devices. As described in further detail below, the devices and circuitry included in the TFT control logic levels may employ TFT CMOS devices including laterally displaced transistors (e.g., PMOS transistors, NMOS transistors). The devices and circuitry of the TFT control logic level of each of the decks104may only be utilized to effectuate and control operations within a single (e.g., only one) deck104of the stack structure103(e.g., may not be shared between two or more of the decks104), or may be utilized to effectuate and control operations within multiple (e.g., more than one) decks104of the stack structure103(e.g., may be shared between two or more of the decks104). In addition, each of the TFT control logic levels (e.g., the first TFT control logic level106A, the second TFT control logic level108A, and the third TFT control logic level110A) of the stack structure103may exhibit substantially the same configuration (e.g., substantially the same components and component arrangements), or at least one of the TFT control logic levels of the stack structure103may exhibit a different configuration (e.g., different components and/or a different component arrangement) than at least one other of the TFT control logic levels.

Thus, a semiconductor device according to embodiments of the disclosure comprises a stack structure comprising decks each comprising a memory element level comprising memory elements, and a control logic level in electrical communication with the memory element level and comprising control logic devices. At least one of the control logic devices of the control logic level of one or more of the decks comprises at least one least one device exhibiting transistors laterally displaced from one another.

FIG. 2is a block diagram of a configuration of a TFT control logic level200for use in one or more of the decks104(FIG. 1) of the stack structure103(FIG. 1) of the semiconductor device100shown inFIG. 1. The TFT control logic level200may include a variety of control logic devices and circuits that would otherwise be included in off-deck circuitry (e.g., circuitry not presented within the TFT control logic level200), such as circuitry within a base control logic structure (e.g., the base control logic structure102shown inFIG. 1). For example, as shown inFIG. 2, an assembly of control logic devices and circuits present within the TFT control logic level200may include one or more (e.g., each) of a local deck decoder202, multiplexers (MUX)204(illustrated inFIG. 2as a first MUX204a, second MUX204b, and a third MUX204c), a column decoder206, a row decoder208, sense amplifiers210, local I/O devices212, word line (WL) drivers214, a column repair device216, a row repair device218, a memory test device222, an ECC device220, and a self-refresh/wear leveling device224. One or more of the control logic devices and circuits may exhibit laterally-displaced transistors (e.g., laterally-displaced vertical transistors, laterally-displaced horizontal transistors, laterally-displaced FinFETs), as described in further detail below. The assembly of control logic devices and circuits present within the TFT control logic level200may be operatively associated with (e.g., in electrical communication with) off-deck devices236(e.g., a controller, a host, global I/O devices) located outside of the TFT control logic level200, such as within the base control logic structure102shown inFIG. 1. The off-deck devices236may send a variety signals to the TFT control logic level200, such as a deck enable signal226, a row address signal230, a column address signal232, a global clock signal234; and may also receive a variety of signals from the TFT control logic level200, such as a global data signal228. WhileFIG. 2depicts a particular configuration of the TFT control logic level200, one of ordinary skill in the art will appreciate that different control logic assembly configurations, including different control logic devices and circuits and/or different arrangements of control logic devices and circuits, are known in the art which may be adapted to be employed in embodiments of the disclosure.FIG. 2illustrates just one non-limiting example of the TFT control logic level200.

Thus, in accordance with embodiments of the disclosure, a method of operating a semiconductor device comprises controlling functions of a stack structure having multiple decks each comprising memory cells using control logic levels of the multiple decks. The control logic levels each comprise at least one control logic device exhibiting laterally-displaced transistors. Additional functions of the stack structure are controlled using a base control logic structure in electrical communication with the control logic levels of the stack structure.

As shown inFIG. 2, one or more off-deck devices236located outside of the TFT control logic level200(e.g., in the base control logic structure102shown inFIG. 1) may be configured and operated to convey signals (e.g., a deck enable signal226, a row address signal230, a column address signal232) to different devices of the TFT control logic level200. For example, the off-deck devices236may send a deck enable signal226to the local deck decoder202, which may decode the deck enable signal226and activate one or more of the MUX204(e.g., the first MUX204a, the second MUX204b, and/or the third MUX204c) of the TFT control logic level200. As described in further detail below, when activated, the MUX204may individually be configured and operated to select one of several input signals and then forward the selected input into a single line.

The local deck decoder202of the TFT control logic level200may be configured and operated to receive activation (e.g., trigger) signals from a deck enable signal226and communicate with the off-deck devices236to generate control signals, which are then directed to one or more of the MUX204(e.g., the first MUX204a, the second MUX204b, and/or the third MUX204c) of the TFT control logic level200to activate and/or deactivate the one or more of the MUX204. When activated, the MUX204may individually be configured and operated to select one of several input signals, and then forward the selected input into a single line.

The first MUX204a(e.g., a row MUX) of the TFT control logic level200may be in electrical communication with the local deck decoder202and the row decoder208of the TFT control logic level200. The first MUX204amay be activated by signal(s) from the local deck decoder202, and may be configured and operated to selectively forward at least one row address signal230from the off-deck devices236to the row decoder208. The row decoder208may be configured and operated to select particular word lines of a deck (e.g., one of the first deck106, the second deck108, and the third deck110shown inFIG. 1) including the TFT control logic level200based on the row address signal230received thereby.

With continued reference toFIG. 2, the row repair device218of the TFT control logic level200may be in electrical communication with the row decoder208, and may be configured and operated to substitute a defective row of memory elements of a memory element array of a memory element level (e.g., one of the memory element levels106C,108C,110C shown inFIG. 1) operatively associated with (e.g., within the same deck104shown inFIG. 1) the TFT control logic level200for a spare, non-defective row of memory elements of the memory element array of the memory element level. The row repair device218may transform a row address signal230directed to the row decoder208(e.g., from the first MUX204a) identifying the defective row of memory elements into another row address signal identifying the spare, non-defective row of memory elements. Defective rows (and columns) of memory elements may, for example, be determined using the memory test device222of the TFT control logic level200, as described in further detail below.

The WL drivers214of the TFT control logic level200may be in electrical communication with the row decoder208, and may be configured and operated to activate word lines of a deck (e.g., one of the first deck106, the second deck108, and the third deck110shown inFIG. 1) including the TFT control logic level200based on word line selection commands received from the row decoder208. The memory elements of a memory element level (e.g., one of the memory element levels106C,108C,110C shown inFIG. 1) operatively associated with the TFT control logic level200may be accessed by way of access devices of an access device level (e.g., one of the access device levels106B,108B,110B shown inFIG. 1) operatively associated with the TFT control logic level200for reading or programming by voltages placed on the word lines using the WL drivers214.

The self-refresh/wear leveling device224of the TFT control logic level200may be in electrical communication with the row decoder208, and may be configured and operated to periodically recharge the data stored in memory elements of a memory element level (e.g., one of the memory element levels106C,108C,110C shown inFIG. 1) operatively associated with (e.g., within the same deck104shown inFIG. 1) the TFT control logic level200. During a self-refresh/wear leveling operation, the self-refresh/wear leveling device224may be activated in response to an external command signal, and may generate different row address signals that may be forwarded to the row decoder208. The row decoder208may then select particular word lines of a deck (e.g., one of the first deck106, the second deck108, and the third deck110shown inFIG. 1) including the TFT control logic level200based on the different row address signals received from the self-refresh/wear leveling device224. The row decoder208may then communicate with the WL drivers214to activate the selected word lines, and charges accumulated in capacitors of memory elements operatively associated with the selected word lines may then be amplified by a sense amplifier and then stored in the capacitors again.

Still referring toFIG. 2, the second MUX204b(e.g., a column MUX) of the TFT control logic level200may be in electrical communication with the local deck decoder202and the column decoder206of the TFT control logic level200. The second MUX204bmay be activated by signal(s) from the local deck decoder202, and may be configured and operated to selectively forward at least one column address signal232from the off-deck devices236to the column decoder206. The column decoder206may be configured and operated to select particular digit lines (e.g., bit lines) of a deck (e.g., one of the first deck106, the second deck108, and the third deck110shown inFIG. 1) including the TFT control logic level200based on the column address selection signal received thereby.

The column repair device216of the TFT control logic level200may be in electrical communication with the column decoder206, and may be configured and operated to substitute a defective column of memory elements of a memory element array of a memory element level (e.g., one of the memory element levels106C,108C,110C shown inFIG. 1) operatively associated with (e.g., within the same deck104shown inFIG. 1) the TFT control logic level200for a spare, non-defective column of memory elements of the memory element array of the memory element level. The column repair device216may transform a column address signal232directed to the column decoder206(e.g., from the second MUX204b) identifying the defective column of memory elements into another column address signal identifying the spare, non-defective column of memory elements. As previously discussed, defective columns (and rows) of memory elements may, for example, be determined using the memory test device222of the TFT control logic level200, as described in further detail below.

The ECC device220of the TFT control logic level200may be configured and operated to generate an ECC code (also known as “check bits”). The ECC code may correspond to a particular data value, and may be stored along with the data value in a memory element of a memory element level (e.g., one of the memory element levels106C,108C,110C shown inFIG. 1) operatively associated with (e.g., within the same deck104shown inFIG. 1) the TFT control logic level200. When the data value is read back from the memory element, another ECC code is generated and compared with the previously-generated ECC code to access the memory element. If non-zero, the difference in the previously-generated ECC code and the newly-generated ECC code indicates that an error has occurred. If an error condition is detected, the ECC device220may then be utilized to correct the erroneous data.

The memory test device222of the TFT control logic level200may be configured and operated to identify defective (e.g., faulty) memory elements of a memory element array of a memory element level (e.g., one of the memory element levels106C,108C,110C shown inFIG. 1) operatively associated with (e.g., within the same deck104shown inFIG. 1) the TFT control logic level200. The memory test device222may attempt to access and write test data to memory elements at different addresses (e.g., different column addresses, different row addresses) within the memory element array. The memory test device222may then attempt to read data stored at the memory elements, and compare the read data to the test data expected at the memory elements. If the read data is different than the expected test data, the memory test device222may identify the memory elements as defective. The defective memory elements (e.g., defective rows of memory elements, defective columns of memory elements) identified by the memory test device222may then be acted upon and/or avoided by other components (e.g., the row repair device218, the column repair device216) of the TFT control logic level200.

With continued reference toFIG. 2, the local I/O devices212of the TFT control logic level200may be configured and operated to receive data from digit lines selected by the column decoder206during read operations, and to output data to digit lines selected by the column decoder206during write operations. As shown inFIG. 2, the local I/O devices212may include sense amplifiers210configured and operated to receive digit line inputs from the digit lines selected by the column decoder206and to generate digital data values during read operations. During write operations, the local I/O devices212may program data into memory elements of a memory element level operatively associated with the TFT control logic level200by placing proper voltages on the digit lines selected by the column decoder206. For binary operation, one voltage level is typically placed on a digit line to represent a binary “1” and another voltage level to represent a binary “0”.

The third MUX204cof the TFT control logic level200may be in electrical communication with the local I/O devices212and the local deck decoder202. The third MUX204cmay be activated by signal(s) received from the local deck decoder202, and may be configured and operated to receive digital data values generated by the local I/O devices212and to generate a global data signal228therefrom. The global data signal228may be forwarded to one or more off-deck devices236(e.g., a controller).

In accordance with embodiments of the disclosure, one or more of the components (e.g., one or more of the local deck decoder202, the MUX204(the first MUX204a, the second MUX204b, the third MUX204c), the column decoder206, the row decoder208, the sense amplifiers210, the local I/O devices212, the WL drivers214, the column repair device216, the row repair device218, the ECC device220, the memory test device222, the self-refresh/wear leveling device224) of the TFT control logic level200may employ one or more TFT CMOS devices including horizontally-neighboring transistors (e.g., horizontally-neighboring NMOS and PMOS transistors) thereof. The horizontally-neighboring transistors may comprise vertical transistors (e.g., vertical NMOS transistor(s), vertical PMOS transistor(s)) exhibiting channels vertically extending between vertically-displaced source and drain regions, or may comprise horizontal transistors (e.g., horizontal NMOS transistor(s), horizontal PMOS transistor(s)) exhibiting channels horizontally extending between horizontally displaced source and drain regions Accordingly, one or more components of at least one of the TFT control logic levels (e.g., the first TFT control logic level106A, the second TFT control logic level108A, the third TFT control logic level110A) of one or more of the decks104(e.g., the first deck106, the second deck108, the third deck110) of the stack structure103of the semiconductor device100previously described with reference toFIG. 1may include one or more TFT CMOS devices including at least one NMOS transistor (e.g., a vertical NMOS transistor, a horizontal NMOS transistor, an NMOS fin field-effect transistor (FinFET)) horizontally-neighboring at least one PMOS transistor (e.g., a vertical PMOS transistor, a horizontal PMOS transistor, a PMOS FinFET). Non-limiting examples of such TFT CMOS devices are described in further detail below with reference toFIGS. 3A through 5.

Thus, a thin film transistor control logic assembly according to embodiments of the disclosure comprises control logic devices selected from the group comprising decoders, sense amplifiers, word line drivers, repair devices, memory test devices, multiplexers, error checking and correction devices, and self-refresh/wear leveling devices. At least one of the control logic devices comprises at least one device exhibiting a transistor having an N-type channel region laterally displaced from a transistor having a P-type channel region.

FIG. 3Ashows a simplified cross-sectional view of a CMOS inverter300, in accordance with embodiments of the disclosure. The CMOS inverter300includes a CMOS circuit302comprising a vertical NMOS transistor304, and a vertical PMOS transistor306horizontally displaced from the vertical NMOS transistor304. The vertical NMOS transistor304includes a first semiconductive pillar308including an N-type source region308A, an N-type drain region308C, and a P-type channel region308B vertically between the N-type source region308A and the N-type drain region308C. The vertical PMOS transistor306includes a second semiconductive pillar310including a P-type source region310A, a P-type drain region310C, and an N-type channel region310B vertically between the P-type source region310A and the P-type drain region310C. The vertical NMOS transistor304and the vertical PMOS transistor306of the CMOS circuit302also include gate electrodes312horizontally adjacent the respective channel regions (e.g., the P-type channel region308B, the N-type channel region310B) thereof. In addition, the CMOS inverter300includes a ground (GND) structure314connected to the N-type source region308A of the vertical NMOS transistor304; a supply voltage (Vcc) structure316connected to the P-type source region310A of vertical PMOS transistor306; an output structure318connected to the N-type drain region308C of the vertical NMOS transistor304and the P-type drain region310C of the vertical PMOS transistor306; and an input structure connected to each of the gate electrodes312.

The gate electrodes312may each individually be formed of and include electrically conductive material including, but not limited to, a metal (e.g., tungsten, titanium, nickel, platinum, gold), a metal alloy, a metal-containing material (e.g., metal nitrides, metal silicides, metal carbides, metal oxides), a conductively-doped semiconductor material (e.g., conductively-doped silicon, conductively-doped germanium, conductively-doped silicon germanium, etc.), or combinations thereof. By way of non-limiting example, the gate electrodes312may each individually comprise at least one of titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), titanium aluminum nitride (TiAlN), elemental titanium (Ti), elemental platinum (Pt), elemental rhodium (Rh), elemental aluminum (Al), elemental copper (Cu), elemental iridium (Ir), iridium oxide (IrOx), elemental ruthenium (Ru), ruthenium oxide (RuOx), alloys thereof, or combinations thereof. In some embodiments, the gate electrodes312are formed of TiN.

As shown inFIG. 3A, the vertical NMOS transistor304may include one of the gate electrodes312laterally adjacent a side of the P-type channel region308B thereof opposing another side laterally adjacent another of the gate electrodes312; and the vertical PMOS transistor306may include an additional one of the gate electrodes312laterally adjacent a side of the N-type channel region310B opposing another side laterally adjacent yet another of the gate electrodes312. The gate electrodes312may be unshared by the vertical NMOS transistor304and the vertical PMOS transistor306. Each of the vertical NMOS transistor304and the vertical PMOS transistor306may be considered to be “double-gated” in that two of the gate electrodes312are disposed laterally adjacent two opposing sides of the P-type channel region308B of the vertical NMOS transistor304; and two other of the gate electrodes312are disposed laterally adjacent two opposing sides of the N-type channel region310B of the vertical PMOS transistor306.

In additional embodiments, one or more of the vertical NMOS transistor304and the vertical PMOS transistor306of the CMOS circuit302exhibit(s) a different gate configurations than that depicted inFIG. 3A. At least one (e.g., each) of the vertical NMOS transistor304and the vertical PMOS transistor306may, for example, exhibit a gate configuration other than a “double-gate” configuration. As a non-limiting example, in accordance with additional embodiments of the disclosure,FIG. 3Bshows a simplified cross-sectional view of the CMOS inverter300, wherein the vertical NMOS transistor304and the vertical PMOS transistor306of the CMOS circuit302each exhibit a “single-gate” configuration. As shown inFIG. 3B, only one gate electrode312′ may be disposed laterally adjacent the P-type channel region308B of the vertical NMOS transistor304; and only one other gate electrode312′ may be disposed laterally adjacent the N-type channel region310B of the vertical PMOS transistor306. Put another way, only one side of the P-type channel region308B of the vertical NMOS transistor304may have a gate electrode312′ laterally adjacent thereto; and only one side of the N-type channel region310B of the vertical PMOS transistor306may have a gate electrode312′ laterally adjacent thereto. The gate electrodes312′ may have material compositions substantially similar to those previously described with respect to the gate electrodes312(FIG. 3A). As another non-limiting example, in accordance with future embodiments of the disclosure,FIG. 3Cshows a simplified cross-sectional view of the CMOS inverter300, wherein the vertical NMOS transistor304and the vertical PMOS transistor306of the CMOS circuit302each exhibit a “gate-all-around” configuration. One gate electrode312″ may substantially laterally surround all sides of the P-type channel region308B (e.g., four sides if the P-type channel region308B exhibits a rectangular cross-sectional shape) of the vertical NMOS transistor304; and another gate electrode312″ may substantially laterally surround all sides of the N-type channel region310B (e.g., four sides if the N-type channel region310B exhibits a rectangular cross-sectional shape) of the vertical PMOS transistor306. The gate electrodes312″ may have material compositions substantially similar to those previously described with respect to the gate electrodes312(FIG. 3A).

With returned reference toFIG. 3A, the P-type channel region308B of the vertical NMOS transistor304may be formed of and include at least one P-type conductivity material. The P-type conductivity material may, for example, comprise polysilicon doped with at least one P-type dopant (e.g., boron ions). The P-type channel region308B of the vertical NMOS transistor304may comprise a solid P-type conductivity material substantially completely filling the entire volume thereof; or the P-type channel region308B of the vertical NMOS transistor304may include an opening (e.g., a hollow, a void, a space) extending through the P-type conductivity material thereof, such that the P-type channel region308B exhibits a “hollow-channel” configuration. In addition, the N-type source region308A and the N-type drain region308C of the vertical NMOS transistor304may each individually be formed of and include at least one N-type conductivity material. The N-type conductivity material may, for example, comprise polysilicon doped with at least one N-type dopant (e.g., arsenic ions, phosphorous ions, antimony ions). The first semiconductive pillar308including the N-type source region308A, the P-type channel region308B, and the N-type drain region308C may exhibit any desired dimensions (e.g., channel width, channel thickness, channel length) and shape (e.g., a rectangular column shape, a cylindrical column shape, a combination thereof). By way of non-limiting example, a channel thickness (laterally extending in the X-direction) of the first semiconductive pillar308may be within a range of from about 10 nanometers (nm) to about 50 nm, a channel width (laterally extending perpendicular to the channel thickness) of the first semiconductive pillar308may be within a range of from 20 nm to about 200 nm, and a channel length (vertically extending in the Z-direction) of the first semiconductive pillar308may be within a range of from about 50 nm to about 200 nm.

The N-type channel region310B of the vertical PMOS transistor306may be formed of and include at least one N-type conductivity material. The N-type conductivity material may, for example, comprise polysilicon doped with at least one N-type dopant (e.g., arsenic ions, phosphorous ions, antimony ions). The N-type channel region310B of the vertical PMOS transistor306may comprise a solid N-type conductivity material substantially completely filling the entire volume thereof; or the N-type channel region310B of the vertical PMOS transistor306may include an opening (e.g., a hollow, a void, a space) extending through the N-type conductivity material thereof, such that the N-type channel region310B exhibits a “hollow-channel” configuration. In addition, the P-type source region310A and the P-type drain region310C of the vertical PMOS transistor306may each individually be formed of and include at least one P-type conductivity material. The P-type conductivity material may, for example, comprise polysilicon doped with at least one P-type dopant (e.g., boron ions). The second semiconductive pillar310including the P-type source region310A, the N-type channel region310B, and the P-type drain region310C may exhibit any desired dimensions (e.g., channel width, channel thickness, channel length) and shape (e.g., a rectangular column shape, a cylindrical column shape, a combination thereof). By way of non-limiting example, a channel thickness (laterally extending in the X-direction) of the second semiconductive pillar310may be within a range of from about 10 nanometers (nm) to about 50 nm, a channel width (laterally extending perpendicular to the channel thickness) of the second semiconductive pillar310may be within a range of from 20 nm to about 200 nm, and a channel length (vertically extending in the Z-direction) of the second semiconductive pillar310may be within a range of from about 50 nm to about 200 nm. The dimensions of the second semiconductive pillar310may be substantially the same as or different than the dimensions of the first semiconductive pillar308.

The GND structure314, the Vccstructure316, the output structure318, and the input structure of the CMOS inverter300may exhibit conventional configurations (e.g., conventional dimensions, conventional shapes, conventional conductive material compositions, conventional material distributions, conventional orientations, conventional arrangements), which are not described in detail herein.

FIGS. 4A through 5(includingFIGS. 4A, 4B, 4C, and 5) show simplified cross-sectional views of additional TFT CMOS devices according to embodiments of the disclosure that may be included in TFT control logic levels (e.g., the TFT control logic level200shown inFIG. 2; one or more of the first TFT control logic level106A, the second TFT control logic level108A, and the third TFT control logic level110A shown inFIG. 1) of the disclosure. ThroughoutFIGS. 4A through 5and the written description associated therewith, functionally similar features (e.g., structures) are referred to with similar reference numerals incremented by 100. To avoid repetition, not all features shown inFIGS. 4A through 5are described in detail herein. Rather, unless described otherwise below, throughoutFIGS. 4A through 5(and the written description associated therewith), a feature designated by a reference numeral that is a 100 increment of the reference numeral of a previously-described feature (whether the previously-described feature is first described before the present paragraph, or is first described after the present paragraph) will be understood to be substantially similar to the previously-described feature.

FIG. 4Ashows a simplified cross-sectional view of a CMOS inverter400, in accordance with additional embodiments of the disclosure. The CMOS inverter400includes a CMOS circuit402comprising a horizontal NMOS transistor404, and a horizontal PMOS transistor406horizontally (e.g., laterally) displaced from the horizontal NMOS transistor404. The horizontal NMOS transistor404comprises a first semiconductive section408of a semiconductive structure401, wherein the first semiconductive section408includes an N-type source region408A, an N-type drain region408C, and a P-type channel region408B laterally (e.g., horizontally) between the N-type source region408A and the N-type drain region408C. The horizontal PMOS transistor406includes a second semiconductive section410of the semiconductive structure401, the second semiconductive section410including a P-type source region410A, a P-type drain region410C, and an N-type channel region410B laterally between the P-type source region310A and the P-type drain region310C. The horizontal NMOS transistor404and the horizontal PMOS transistor406of the CMOS circuit402also include gate electrodes412vertically adjacent the respective channel regions (e.g., the P-type channel region408B, the N-type channel region410B) thereof. In addition, the CMOS inverter400includes a ground (GND) structure414connected to the N-type source region408A of the horizontal NMOS transistor404; a supply voltage (Vcc) structure416connected to the P-type source region410A of the horizontal PMOS transistor406; an output structure418connected to the N-type drain region408C of the horizontal NMOS transistor404and the P-type drain region410C of the horizontal PMOS transistor406; and an input structure connected to each of the gate electrodes412.

As shown inFIG. 4A, in some embodiments, the gate electrodes412vertically overlie the P-type channel region408B of the horizontal NMOS transistor404and the N-type channel region410B of the horizontal PMOS transistor406, such that the horizontal NMOS transistor404and the horizontal PMOS transistor406of the CMOS circuit402each exhibit a “top-gate” configuration. In additional embodiments, one or more of the horizontal NMOS transistor404and the horizontal PMOS transistor406of the CMOS circuit402exhibit(s) a different gate configuration than that depicted inFIG. 4A. At least one (e.g., each) of the horizontal NMOS transistor404and the horizontal PMOS transistor406may, for example, exhibit a gate configuration other than a “top-gate” configuration. As a non-limiting example, in accordance with additional embodiments of the disclosure,FIG. 4Bshows a simplified cross-sectional view of the CMOS inverter400wherein the horizontal NMOS transistor404and the horizontal PMOS transistor406of the CMOS circuit402each exhibit a “bottom-gate” configuration. As shown inFIG. 4B, the gate electrodes412vertically underlie the P-type channel region408B of the horizontal NMOS transistor404and the N-type channel region410B of the horizontal PMOS transistor406.

With returned reference toFIG. 4A, the semiconductive structure401may be formed of and include at least one semiconductive material, such as one or more of silicon (e.g., amorphous silicon, polysilicon), silicon-germanium, germanium, gallium arsenide, gallium nitride, and indium phosphide. The horizontal NMOS transistor404and the horizontal PMOS transistor406may be at least partially (e.g., substantially) located within the semiconductive structure401. The material compositions of the horizontal NMOS transistor404(including the material compositions of the N-type source region408A, the N-type drain region408C, and the P-type channel region408B thereof) and the horizontal PMOS transistor406(including the material compositions of the P-type source region410A, the P-type drain region410C, and the N-type channel region410B thereof) may respectively be substantially similar to those of the vertical NMOS transistor304(including the material compositions of the N-type source region308A, the N-type drain region308C, and the P-type channel region308B thereof) and the vertical PMOS transistor306(including the material compositions of the P-type source region310A, the P-type drain region310C, and the N-type channel region310B thereof) previously described with reference toFIG. 3A.

As shown inFIG. 4A, vertical boundaries of the different regions (e.g., the N-type source region408A, the N-type drain region408C, the P-type channel region408B) of the horizontal NMOS transistor404may be substantially coplanar with one another; and vertical boundaries of the different regions (e.g., the P-type source region410A, the P-type drain region410C, the N-type channel region410B) of the horizontal PMOS transistor406may also be substantially coplanar with one another. In additional embodiments, vertical boundaries of at least one of the different regions (e.g., the P-type channel region408B) of the horizontal NMOS transistor404may be offset from vertical boundaries of at least one other of the different regions (the N-type source region408A, the N-type drain region408C) of the horizontal NMOS transistor404; and/or vertical boundaries of at least one of the different regions (e.g., the N-type channel region410B) of the horizontal PMOS transistor406may be offset from vertical boundaries of at least one other of the different regions (the P-type source region410A, the P-type drain region410C) of the horizontal PMOS transistor406. As a non-limiting example, in accordance with additional embodiments of the disclosure,FIG. 4Cshows a simplified cross-sectional view of the CMOS inverter400wherein upper vertical boundaries of the P-type channel region408B of the horizontal NMOS transistor404are offset from (e.g., vertically overlie) upper vertical boundaries of the N-type source region408A and the N-type drain region408C of the horizontal NMOS transistor404; and wherein upper vertical boundaries of the N-type channel region410B of the horizontal PMOS transistor406are offset from (e.g., vertically overlie) upper vertical boundaries of the P-type source region410A and the P-type drain region410C of the horizontal PMOS transistor406. As shown inFIG. 4C, upper vertical boundaries of the P-type channel region408B of the horizontal NMOS transistor404and the N-type channel region410B of the horizontal PMOS transistor406may be substantially coplanar with uppermost vertical boundaries of the semiconductive structure401; upper vertical boundaries of the N-type source region408A and the N-type drain region408C of the horizontal NMOS transistor404may be offset from (e.g., vertically underlie) the uppermost vertical boundaries of the semiconductive structure401; and upper vertical boundaries of the P-type source region410A and the P-type drain region410C of the horizontal PMOS transistor406may be offset from (e.g., vertically underlie) the uppermost vertical boundaries of the semiconductive structure401.

The GND structure414, the Vccstructure416, the output structure418, and the input structure of the CMOS inverter400may exhibit conventional configurations (e.g., conventional dimensions, conventional shapes, conventional conductive material compositions, conventional material distributions, conventional orientations, conventional arrangements), which are not described in detail herein.

FIG. 5shows a simplified cross-sectional view of a CMOS inverter500, in accordance with additional embodiments of the disclosure. The CMOS inverter500includes a CMOS circuit502comprising a NMOS FinFET504, and a PMOS FinFET506horizontally (e.g., laterally) displaced from the NMOS FinFET504. The NMOS FinFET504comprises a first semiconductive fin508including an N-type source region508A, an N-type drain region508C, and a P-type channel region508B horizontally between the N-type source region508A and the N-type drain region508C. The PMOS FinFET506includes a second semiconductive fin510including a P-type source region510A, a P-type drain region510C, and an N-type channel region510B horizontally between the P-type source region510A and the P-type drain region510C. The NMOS FinFET504and the PMOS FinFET506of the CMOS circuit502also include gate electrodes512adjacent (e.g., vertically adjacent, laterally adjacent) the respective channel regions (e.g., the P-type channel region508B, the N-type channel region510B) thereof. The NMOS FinFET504and the PMOS FinFET506of the CMOS inverter500may be located on or over an insulative structure501. In addition, the CMOS inverter500includes a ground (GND) structure514connected to the N-type source region508A of the NMOS FinFET504; a supply voltage (Vcc) structure516connected to the P-type source region510A of the PMOS FinFET506; an output structure518connected to the N-type drain region508C of the NMOS FinFET504and the P-type drain region510C of the PMOS FinFET506; and an input structure connected to each of the gate electrodes512.

As shown inFIG. 5, one of the gate electrodes512may extend over opposing sides (e.g., opposing side surfaces) and a top (e.g., an upper surface) of the P-type channel region508B of the first semiconductive fin508of the NMOS FinFET504. In addition, another of the gate electrodes512may extend over opposing sides (e.g., opposing side surfaces) and a top (e.g., an upper surface) of the N-type channel region510B of the second semiconductive fin510of the PMOS FinFET506. In additional embodiments, one or more (e.g., each) of the NMOS FinFET504and the PMOS FinFET506exhibit(s) a “gate-all-around” configuration. For example, one of the gate electrodes512may substantially surround the opposing sides, the top, and a bottom of the P-type channel region508B of the NMOS FinFET504; and another of the gate electrodes512may substantially surround the opposing sides, the top, and a bottom of the N-type channel region510B of the PMOS FinFET506. In some such embodiments, the P-type channel region508B of the NMOS FinFET504comprises one or more (e.g., multiple) P-type conductivity structures, and a conductive material of one of the gate electrodes512substantially surrounds surfaces of the P-type conductivity structures between the N-type source region508A and the N-type drain region508C; and the N-type channel region510B of the PMOS FinFET506comprises one or more (e.g., multiple) N-type conductivity structures, and a conductive material of another of the gate electrodes512substantially surrounds surfaces of the N-type conductivity structures between the P-type source region510A and the P-type drain region510C.

The insulative structure501, the GND structure514, the Vccstructure516, the output structure518, the input structure, and the additional input structure of the CMOS inverter500may exhibit conventional configurations (e.g., conventional dimensions, conventional shapes, conventional conductive material compositions, conventional material distributions, conventional orientations, conventional arrangements), which are not described in detail herein.

WhileFIGS. 3A through 5(includingFIGS. 3A, 3B, 3C, 4A, 4B, 4C, and 5) show non-limiting examples of different CMOS inverters that may be included in one or more components of at least one of the TFT control logic levels (e.g., the first TFT control logic level106A, the second TFT control logic level108A, the third TFT control logic level110A) of one or more of the decks104(e.g., the first deck106, the second deck108, the third deck110) of the stack structure103previously described with reference toFIG. 1, one or more components of at least one of the TFT control logic levels may include other devices (e.g., other CMOS devices) in addition to or in place of the CMOS inverters previously described with reference toFIGS. 3A through 5. By way of non-limiting example, one or more components of at least one of the TFT control logic levels of one or more of the decks104(FIG. 1) of the semiconductor device100(FIG. 1) may include one of more of other inverters (e.g., other CMOS inverters, such as balanced CMOS inverters), transmission pass gates (e.g., CMOS transmission pass gates, such as balanced CMOS transmission pass gates), ring oscillators, and negative-AND (NAND) gates (e.g., two-input NAND gates, such as balanced two-input NAND gates).

Thus, a memory device in accordance with embodiments of the disclosure comprises a base control logic structure comprising control logic devices, and a stack structure in electrical communication with the base control logic structure. The stack structure comprises decks each comprising a memory element level comprising memory elements, and a control logic level in electrical communication with the memory element level. The control logic level comprises additional control logic devices selected from the group comprising decoders, sense amplifiers, word line drivers, repair devices, memory test devices, multiplexers, error checking and correction devices, and self-refresh/wear leveling devices. At least one of the additional control logic devices comprises a circuit comprising neighboring, laterally-displaced transistors having different channel conductivities than one another.

Semiconductor devices (e.g., the semiconductor device100previous described with reference toFIG. 1) including semiconductor device structures (e.g., the stack structure103and the base control logic structure102previous described with reference toFIG. 1) in accordance with embodiments of the disclosure may be used in embodiments of electronic systems of the disclosure. For example,FIG. 6is a block diagram of an illustrative electronic system600according to embodiments of disclosure. The electronic system600may comprise, for example, a computer or computer hardware component, a server or other networking hardware component, a cellular telephone, a digital camera, a personal digital assistant (PDA), portable media (e.g., music) player, a Wi-Fi or cellular-enabled tablet such as, for example, an iPad® or SURFACE® tablet, an electronic book, a navigation device, etc. The electronic system600includes at least one memory device602. The at least one memory device602may include, for example, an embodiment of a semiconductor device previously described herein (e.g., semiconductor device100previously previous described with reference toFIG. 1), wherein different decks (e.g., the decks104) of a stack structure (e.g., the stack structure102) of the semiconductor device each include a control logic level (e.g., the TFT control logic level200previously described with reference toFIG. 2) comprising an assembly of control logic devices, at least one of the control logic devices including at least one device (e.g., a TFT CMOS device) exhibiting laterally-displaced transistors (e.g., laterally-displaced vertical transistors, laterally-displaced horizontal transistors, laterally-displaced FinFETs). The electronic system600may further include at least one electronic signal processor device604(often referred to as a “microprocessor”). The electronic signal processor device604may, optionally, include an embodiment of a semiconductor device previously described herein (e.g., semiconductor device100previously previous described with reference toFIG. 1). The electronic system600may further include one or more input devices606for inputting information into the electronic system600by a user, such as, for example, a mouse or other pointing device, a keyboard, a touchpad, a button, or a control panel. The electronic system600may further include one or more output devices608for outputting information (e.g., visual or audio output) to a user such as, for example, a monitor, a display, a printer, an audio output jack, a speaker, etc. In some embodiments, the input device606and the output device608may comprise a single touchscreen device that can be used both to input information to the electronic system600and to output visual information to a user. The one or more input devices606and output devices608may communicate electrically with at least one of the memory device602and the electronic signal processor device604.

Thus, in accordance with embodiments of the disclosure, an electronic system comprises a semiconductor device comprising a stack structure. The stack structure comprises decks each comprising a memory element level comprising memory elements and a control logic level in electrical communication with the memory element level and comprising control logic devices. At least one of the control logic devices of the control logic level of one or more of the decks comprises at least one device exhibiting laterally-displaced transistors.

The devices, structures, assemblies, systems, and methods of the disclosure advantageously facilitate improved semiconductor device performance, reduced costs (e.g., manufacturing costs, material costs), increased miniaturization of components, and greater packaging density as compared to conventional devices, conventional structures, conventional assemblies, conventional systems, and conventional methods. The devices, structures, assemblies, systems, and methods of the disclosure may also improve performance, scalability, efficiency, and simplicity as compared to conventional devices, conventional structures, conventional assemblies, conventional systems, and conventional methods.

While the disclosure is susceptible to various modifications and alternative forms, specific embodiments have been shown by way of example in the drawings and have been described in detail herein. However, the disclosure is not limited to the particular forms disclosed. Rather, the disclosure is to cover all modifications, equivalents, and alternatives falling within the scope of the following appended claims and their legal equivalents.