Semiconductor device

According to one embodiment, a semiconductor device includes first to third regions, and first to third electrodes. The first region includes a first partial region, a second partial region, and a third partial region between the first and second partial regions. A direction from the first partial region toward the first electrode is aligned with a first direction. A second direction from the first electrode toward the second electrode crosses the first direction. A direction from the third partial region toward the third electrode is aligned with the first direction. A position of the third electrode is between a position of the first electrode and a position of the second electrode in the second direction. At least a portion of the second region is provided between the first and second electrodes. At least a portion of the third region is provided between the first and second regions.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is based upon and claims the benefit of priority from Japanese Patent Application No. 2018-093030, filed on May 14, 2018; the entire contents of which are incorporated herein by reference.

FIELD

BACKGROUND

For example, there is a semiconductor device such as a HEMT or the like including a GaN layer and an AlGaN layer. It is desirable to improve the characteristics of the semiconductor device.

DETAILED DESCRIPTION

According to one embodiment, a semiconductor device includes first to third regions, and first to third electrodes. The first region includes a first material including at least one selected from the group consisting of silicon carbide, silicon, carbon, and germanium. The first region includes a first partial region, a second partial region, and a third partial region between the first partial region and the second partial region. A direction from the first partial region toward the first electrode is aligned with a first direction. A direction from the second partial region toward the second electrode is aligned with the first direction. A second direction from the first electrode toward the second electrode crosses the first direction. A direction from the third partial region toward the third electrode is aligned with the first direction. A position of the third electrode in the second direction is between a position of the first electrode in the second direction and a position of the second electrode in the second direction. The second region includes Alx2Ga1-x2N (0<x2≤1). At least a portion of the second region is provided between the first electrode and the second electrode in the second direction. The third region includes a dielectric. At least a portion of the third region is provided between the first region and the second region.

According to another embodiment, a semiconductor device includes first to third regions, and first to third electrodes. The first region includes a first material including at least one selected from the group consisting of silicon carbide, silicon, carbon, and germanium. The first region includes a first partial region, a second partial region, and a third partial region between the first partial region and the second partial region. A direction from the first partial region toward the first electrode is aligned with a first direction. A direction from the second partial region toward the second electrode is aligned with the first direction. A second direction from the first electrode toward the second electrode crosses the first direction. A direction from the third partial region toward the third electrode is aligned with the first direction. A position of the third electrode in the second direction is between a position of the first electrode in the second direction and a position of the second electrode in the second direction. The second region includes Alx2Ga1-x2N (0<x2≤1). At least a portion of the second region is provided between the first electrode and the second electrode in the second direction. The third region includes at least one selected from the group consisting of silicon oxide, silicon oxynitride, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride, boron nitride, and hafnium oxide. At least a portion of the third region is provided between the first region and the second region.

According to another embodiment, a semiconductor device includes first and second regions, and first to third electrodes. The first region includes a first material including at least one selected from the group consisting of silicon carbide, silicon, carbon, and germanium. The first region includes a first partial region, a second partial region, and a third partial region between the first partial region and the second partial region. A direction from the first partial region toward the first electrode is aligned with a first direction. A direction from the second partial region toward the second electrode is aligned with the first direction. A second direction from the first electrode toward the second electrode crosses the first direction. A direction from the third partial region toward the third electrode is aligned with the first direction. A position of the third electrode in the second direction is between a position of the first electrode in the second direction and a position of the second electrode in the second direction. The second region including Alx2Ga1-x2N (0<x2≤1). At least a portion of the second region is provided between the first electrode and the second electrode in the second direction. The first material has a first lattice constant in an axis direction crossing the first direction when unstrained. The Alx2Ga1-x2N (0<x2≤1) has a second lattice constant in the axis direction when unstrained. The second region has a second lattice length in the axis direction. A ratio of an absolute value of a difference between the first lattice constant and the second lattice length to an absolute value of a difference between the first lattice constant and the second lattice constant is 0.15 or more.

First Embodiment

FIG. 1is a schematic cross-sectional view illustrating a semiconductor device according to a first embodiment.

As shown inFIG. 1, the semiconductor device110according to the first embodiment includes a first region10, a second region20, a third region30, and first to third electrodes51to53. An insulating portion40is further provided in the example.

The first region10includes a first material. The first material includes at least one selected from the group consisting of silicon carbide, silicon, carbon, and germanium. In the case where the first material includes SiC, the SiC includes, for example, at least one selected from the group consisting of 6H—SiC and 4H—SiC. For example, the first region10includes a crystal. The first region10may include, for example, diamond.

The first region10includes first to third partial regions11to13. The third partial region13is between the first partial region11and the second partial region12.

The direction from the first partial region11toward the first electrode51is aligned with a first direction.

The first direction is taken as a Z-axis direction. One direction perpendicular to the Z-axis direction is taken as an X-axis direction. A direction perpendicular to the Z-axis direction and the X-axis direction is taken as a Y-axis direction.

The direction from the second partial region12toward the second electrode52is aligned with the first direction (the Z-axis direction). A second direction from the first electrode51toward the second electrode52crosses the first direction. The second direction is, for example, the X-axis direction.

The direction from the third partial region13toward the third electrode53is aligned with the first direction (the Z-axis direction). The position of the third electrode53in the second direction (in the example, the X-axis direction) is between the position of the first electrode51in the second direction and the position of the second electrode52in the second direction.

The second region20includes Alx2Ga1-x2N (0<x2≤1). The second region20includes, for example, AlN. At least a portion of the second region20is provided between the first electrode51and the second electrode52in the second direction (e.g., the X-axis direction). In the example, at least a portion of the second region20is provided between the first region10and at least a portion of the third electrode53in the first direction (the Z-axis direction). For example, the second region20includes a crystal.

The third region30includes a dielectric. The third region30includes, for example, at least one selected from the group consisting of silicon oxide, silicon oxynitride, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride, boron nitride, and hafnium oxide.

For example, at least a portion of the third region30may be amorphous. For example, at least a portion of the third region30may include a polycrystal. For example, the crystallinity of at least a portion of the third region30may be lower than the crystallinity of the first region10. For example, the crystallinity of at least a portion of the third region30may be lower than the crystallinity of the second region20.

At least a portion of the third region30is provided between the first electrode51and the second electrode52in the second direction (e.g., the X-axis direction). At least a portion of the third region30is provided between the second region20and the first region10in the first direction (the Z-axis direction). In the example, at least a portion of the third region30is provided between the third electrode53and the first region10in the first direction (the Z-axis direction).

In the example, the third region30contacts the first region10. The third region30contacts the second region20.

At least a portion of the second region20is provided between the insulating portion40and the first region10in the first direction (the Z-axis direction). At least a portion of the second region20is provided between the third electrode53and the third region30in the first direction (the Z-axis direction). In the example, at least a portion of the insulating portion40is provided between the third electrode53and the second region20in the first direction (the Z-axis direction).

In the example, the insulating portion40includes a first insulating layer41and a second insulating layer42. The second insulating layer42is provided between the first insulating layer41and the second region20in the first direction (the Z-axis direction). The first insulating layer41includes oxygen. The second insulating layer42includes nitrogen. The second insulating layer42does not include oxygen. Or, the concentration of oxygen in the second insulating layer42is lower than the concentration of oxygen in the first insulating layer41. For example, the first insulating layer41includes silicon oxide. The second insulating layer42includes, for example, silicon nitride or silicon oxynitride. For example, the stability of the second region20is increased by providing the second insulating layer42including nitrogen between the second region20(e.g., AlN) and the first insulating layer41including oxygen. More stable characteristics are obtained easily.

In the embodiment, a thickness t3 along the first direction (the Z-axis direction) of the third region30(referring toFIG. 1) is thinner than a thickness t1 along the first direction of the first region10(referring toFIG. 1). For example, the thickness t1 of the first region10is 100 nm or more. The thickness t3 of the third region30is not less than 1 nm and not more than 20 nm.

The thickness t3 is the length along the first direction (the Z-axis direction). The at least a portion of the third region30recited above has a first surface30aand a second surface30b(referring toFIG. 1). The first surface30aand the second surface30bare aligned with the second direction (e.g., the X-axis direction). For example, these surfaces are along the X-Y plane. The first surface30ais the surface on the first region10side. The first surface30aopposes the first region10. The second surface30bopposes the second region20. The distance along the first direction (the Z-axis direction) between the first surface30aand the second surface30bcorresponds to the thickness t3.

A thickness t2 along the first direction (the Z-axis direction) of the second region20is thinner than the thickness t1 along the first direction of the first region10(referring toFIG. 1). In the embodiment, the thickness t2 is, for example, not less than 5 nm and not more than 500 nm.

For example, the first electrode51is electrically connected to the first partial region11of the first region10. For example, the second electrode52is electrically connected to the second partial region12of the first region10.

For example, the first electrode51functions as a source electrode. For example, the second electrode52functions as a drain electrode. For example, the third electrode53functions as a gate electrode. As described below, a carrier region is formed in the portion of the first region10on the third region30side.

As described above, the second region20includes Alx2Ga1-x2N (0<x2≤1). The second region20has polarity. On the other hand, the polarity of the first region10is smaller than the polarity of the second region20. For example, the first region10substantially does not have polarity.

Because such a second region20has polarization (e.g., spontaneous polarization), a carrier region is induced in the first region10via the third region30including the dielectric. A current flows between the first electrode51and the second electrode52via the carrier region. The induction of the carrier region can be controlled by the third electrode53.

The carrier region includes, for example, a two-dimensional electron gas10E. The semiconductor device110is, for example, a HEMT (High Electron Mobility Transistor). In other embodiments as described below, the carrier region may include a two-dimensional hole gas.

The orientation of the polarity of the second region20is the <0001> direction or the <000-1> direction. In the example shown inFIG. 1, the <0001> direction crosses the X-Y plane. In the example, the <0001> direction has a component in the direction from the first region10toward the second region20. In another embodiment, the <000-1> direction may have a component in the direction from the first region10toward the second region20.

The case will now be described where the <0001> direction of the second region20is aligned with the orientation from the first region10toward the second region20. Hereinbelow, the orientation from the first region10toward the second region20is taken as the +Z orientation; and the orientation from the second region20toward the first region10is taken as the −Z orientation.

An example of simulation results of characteristics of the semiconductor device110will now be described.

FIG. 2is a schematic view illustrating characteristics of the semiconductor device according to the first embodiment.

FIG. 2illustrates simulation results of the characteristics of the semiconductor device110. InFIG. 2, the horizontal axis is a position pZ (nm) along the Z-axis direction. The vertical axis is an energy E1 (eV). The energies of a conduction band CB and a valence band VB are shown inFIG. 2. In the example, the first region10is a 6H—SiC substrate. The second region20is AlN; and the thickness t2 of the second region20is 30 nm. The third region30is SiO2; and the thickness t3 of the third region30is 3 nm.

As shown inFIG. 2, a local bottom is observed in the conduction band CB on the second region20side of the first region10. The local bottom corresponds to the carrier region (e.g., the two-dimensional electron gas10E).

For example, the first region10which is a SiC layer and the second region20which is an AlGaN layer (or an AlN layer) are included in the embodiment. On the other hand, there is a first reference example in which a GaN layer is used as the first region10, and AlGaN layers are used as the second region20and the third region30. The heat dissipation of SiC is higher than the heat dissipation of GaN. Therefore, the heat dissipation of the embodiment is higher than the heat dissipation of the first reference example.

For example, the breakdown voltage of SiC is higher than the breakdown voltage of GaN. For example, a higher breakdown voltage is obtained in the embodiment than in the first reference example.

On the other hand, there is a second reference example in which the second region20(Alx2Ga1-x2N (0<x2≤1)) is provided in contact with the first region10. The third region30is not provided in the second reference example. In the second reference example, the lattice length of the second region20is greatly affected by the lattice length of the first region10. To simplify the description hereinbelow, the first region10is taken to be 6H—SiC; and the second region20is taken to be AlN. The unstrained a-axis direction lattice length (the lattice constant) of the first region10(6H—SiC) is 0.3073 nm. The unstrained a-axis direction lattice length (the lattice constant) of the second region20(the AlN) is 0.3112. When the second region20is grown on such a first region10, the lattice length of the second region20is affected by the lattice length of the first region10and reduced. For example, compressive stress is applied to the second region20.

When stress is applied to the second region20, piezoelectric polarization occurs in addition to the spontaneous polarization. For example, in the case where tensile stress is applied to the second region20, the orientation of the piezoelectric polarization generated based on the tensile stress is the same as the orientation (the <0001> direction) of the spontaneous polarization. Therefore, the magnitude of the polarization of the second region20is the sum of the spontaneous polarization and the piezoelectric polarization.

Conversely, in the case where compressive stress is applied to the second region20, the orientation of the piezoelectric polarization generated based on the compressive stress is the reverse of the orientation (the <0001> direction) of the spontaneous polarization. Therefore, the magnitude of the polarization of the second region20corresponds to the difference between the spontaneous polarization and the piezoelectric polarization.

Carriers that correspond to the sum total of the spontaneous polarization and the piezoelectric polarization (the sum of the spontaneous polarization and the piezoelectric polarization or the difference between the spontaneous polarization and the piezoelectric polarization) are generated in the first region10. The carrier density of the first region10can be increased by increasing the sum total of the spontaneous polarization and the piezoelectric polarization.

In the embodiment, the third region30is provided between the first region10and the second region20. The transfer of the crystalline state of the first region10to the second region20can be suppressed by the third region30. Thereby, the application of the compressive stress to the second region20can be suppressed. For example, the sum total of the spontaneous polarization and the piezoelectric polarization can be large. The carrier density of the first region10can be increased. For example, according to the embodiment, the ON-resistance can be low. According to the embodiment, a semiconductor device can be provided in which the characteristics can be improved.

In the embodiment, for example, the thickness t3 along the first direction (the Z-axis direction) of the third region30is thinner than the thickness t2 along the first direction of the second region20. The thickness t3 is, for example, 1 nm or more. By setting the thickness t3 to be 1 nm or more, the transfer of the crystalline state of the first region10to the second region20can be suppressed. For example, the compressive stress of the second region20can be suppressed. The thickness t3 is, for example, 20 nm or less. In the case where the thickness t3 is excessively thick, the effects on the first region10of the polarization (the sum total of the spontaneous polarization and the piezoelectric polarization) generated in the second region20are weaker. There are cases where the carrier density of the first region10is insufficiently high. By setting the thickness t3 to be 20 nm or less, the effects of the polarization generated in the second region20are effectively applied to the first region10. The carrier density of the first region10can be increased.

Examples of characteristics of the semiconductor device will now be described.

FIG. 3AandFIG. 3Bare graphs illustrating characteristics of the semiconductor device.

These figures illustrate simulation results of the relationship between the characteristics of the third region30and the carrier concentration generated in the first region10. The first region10is a 6H—SiC substrate in the model of the simulation. The second region20is an AlN layer of which the thickness t2 is 30 nm. The AlN layer is unstrained.

The thickness t3 of the third region30is 5 nm inFIG. 3A. The horizontal axis ofFIG. 3Ais a relative dielectric constant εr of the third region30. The vertical axis ofFIG. 3Ais a carrier concentration CC (×1019cm−3) generated in the region of the first region10on the third region30side. As shown inFIG. 3A, the carrier concentration CC increases as the relative dielectric constant εr increases.

The horizontal axis ofFIG. 3Bis the thickness t3 (nm) of the third region30. The vertical axis ofFIG. 3Bis the carrier concentration CC (×1019cm−3) generated in the region of the first region10on the third region30side. The characteristic when the relative dielectric constant εr is 3.8 and the characteristic when the relative dielectric constant εr is 8.8 are shown inFIG. 3B. As shown inFIG. 3B, the carrier concentration CC increases as the thickness t3 decreases.

In the second reference example in which the second region20contacts the first region10without providing the third region30, the lattice length of the a-axis direction of the second region20is the same as the lattice length (e.g., the unstrained lattice constant) of the a-axis direction of the first region10. In the embodiment, the lattice of the second region20can be relaxed by providing the third region30. In the embodiment, the lattice length of the second region20approaches the unstrained lattice length (the lattice constant) of the material of the second region20.

The following “relaxation rate α” is introduced as a parameter corresponding to the relaxation state of the lattice. The first material recited above included in the first region10has a first lattice constant when unstrained. The first lattice constant is a lattice length in one axis direction crossing the first direction (the Z-axis direction). The Alx2Ga1-x2N (0<x2≤1) that is included in the second region20has a second lattice constant when unstrained. The second lattice constant is a lattice length in the axis direction recited above. The axis direction recited above is, for example, the a-axis direction of the Alx2Ga1-x2N (0<x2≤1). For example, in the case where the first region10is 6H—SiC, the first lattice constant (unstrained) is about 0.3073 nm. For example, in the case where the second region20is AlN, the second lattice constant (unstrained) is about 0.3112 nm. The second region20has a second lattice length in the axis direction. The second lattice length is the actual lattice length of the second region20of the semiconductor device110. The relaxation rate α is defined as the “ratio of the absolute value of the difference between the first lattice constant and the second lattice length to the absolute value of the difference between the first lattice constant and the second lattice constant.”

For example, C1 is the first lattice constant; C2 is the second lattice constant; and L2 is the second lattice length. The relaxation rate α corresponds to |C1−L2|/|C1−C2|.

The relaxation rate α is 1 in the case where the second lattice length L2 of the second region20is the same as the second lattice constant C2. This case corresponds to full relaxation. On the other hand, the relaxation rate α is 0 in the case where the second lattice length L2 of the second region20is the same as the first lattice constant C1. In such a case, the lattice of the second region20fully matches the lattice of the first region10; and a large compressive strain is generated in the second region20.

In the embodiment, the relaxation rate α (the ratio recited above) is greater than 0. For example, the relaxation rate α is 0.15 or more. The relaxation rate α may be 0.58 or more. The relaxation rate α may be 0.74 or more.

By setting the relaxation rate α to be greater than 0 (e.g., 0.15 or more), the compressive strain in the second region20is weaker compared to the case where the lattice of the second region20fully matches the lattice of the first region10. Thereby, the sum total of the spontaneous polarization and the piezoelectric polarization can be large. The carrier density of the first region10can be higher.

Information relating to the lattice length recited above (including the lattice constant) is obtained by, for example, X-ray diffraction analysis, etc. Information relating to the lattice constant of the second region20is obtained based on, for example, Vegard's law, analysis results of the composition of the second region20, etc. Information relating to the lattice constant of the first region10is obtained based on, for example, analysis results of the composition of the first region10, etc.

FIG. 4AandFIG. 4Bare schematic cross-sectional views illustrating semiconductor devices according to the first embodiment.

In a semiconductor device111as shown inFIG. 4A, the configurations of the first electrode51and the second electrode52are different from the configurations of the first electrode51and the second electrode52of the semiconductor device110. Otherwise, the configuration of the semiconductor device111is the same as the configuration of the semiconductor device110.

In the semiconductor device111, at least a portion of the first electrode51overlaps the first region10in the second direction (e.g., the X-axis direction). At least a portion of the second electrode52overlaps the first region10in the second direction. At least one of the at least a portion of the first electrode51or the at least a portion of the second electrode52may be buried in the first region10.

As shown inFIG. 4B, a fourth region10dand a fifth region10eare provided in a semiconductor device112. Otherwise, the configuration of the semiconductor device112is the same as the configuration of the semiconductor device110.

The fourth region10dis provided between the first partial region11and the first electrode51. The fifth region10eis provided between the second partial region12and the second electrode52. The impurity concentration in the fourth region10dis higher than the impurity concentration in the first partial region11. The impurity concentration in the fifth region10eis higher than the impurity concentration in the second partial region12.

The impurity includes, for example, at least one selected from the group consisting of nitrogen (N) and phosphorus (P). For example, the fourth region10dand the fifth region10eare obtained by implanting these elements as the impurity into the region used to form the first region10.

The fourth region10dand the fifth region10emay be provided in the semiconductor device111recited above.

Second Embodiment

FIG. 5is a schematic cross-sectional view illustrating a semiconductor device according to a second embodiment.

As shown inFIG. 5, the semiconductor device120according to the second embodiment also includes the first region10, the second region20, the third region30, and the first to third electrodes51to53. The arrangement of these components in the semiconductor device120are the same as the arrangement in the semiconductor device110. In the semiconductor device120, the <000-1> direction has a component in the direction from the first region10toward the second region20.

Hereinbelow, it is taken that the <000-1> direction of the second region20is aligned with the orientation (the +Z orientation) from the first region10toward the second region20.

FIG. 6is a schematic view illustrating characteristics of the semiconductor device according to the second embodiment.

FIG. 6illustrates simulation results of the characteristics of the semiconductor device120. InFIG. 6, the horizontal axis is the position pZ (nm) along the Z-axis direction. The vertical axis is the energy E1 (the eV). The energies of the conduction band CB and the valence band VB are shown inFIG. 6. In the example, the first region10is a 6H—SiC substrate. The second region20is AlN; and the thickness t2 of the second region20is 30 nm. The third region30is SiO2; and the thickness t3 of the third region30is 3 nm.

As shown inFIG. 6, a local peak of the valence band VB is observed in the first region10on the third region30side. The local peak corresponds to the carrier region (e.g., a two-dimensional hole gas10H).

In the semiconductor device120as well, for example, the compressive stress in the second region20can be suppressed. Thereby, the two-dimensional hole gas10H that has a high concentration is obtained. According to the embodiment, for example, the ON-resistance can be low. According to the embodiment, a semiconductor device can be provided in which the characteristics can be improved.

In the second embodiment as well, the relaxation rate α is greater than 0. For example, the relaxation rate α may be 0.15 or more. The relaxation rate α may be 0.58 or more. The relaxation rate α may be 0.74 or more.

FIG. 7AandFIG. 7Bare schematic cross-sectional views illustrating semiconductor devices according to the second embodiment.

In the second embodiment as in a semiconductor device121shown inFIG. 7A, at least a portion of the first electrode51may overlap the first region10in the second direction (e.g., the X-axis direction). At least a portion of the second electrode52may overlap the first region10in the second direction.

As in a semiconductor device122shown inFIG. 7B, the fourth region10dand the fifth region10emay be provided. The fourth region10dis provided between the first partial region11and the first electrode51. The fifth region10eis provided between the second partial region12and the second electrode52. The impurity concentration in the fourth region10dis higher than the impurity concentration in the first partial region11. The impurity concentration in the fifth region10eis higher than the impurity concentration in the second partial region12.

In the second embodiment, the impurity includes, for example, at least one selected from the group consisting of aluminum (Al) and boron (B). For example, the fourth region10dand the fifth region10eare obtained by implanting these elements as the impurity into the region used to form the first region10.

The fourth region10dand the fifth region10emay be provided in the semiconductor device121recited above.

In the first and second embodiments as well, the Al composition ratio x2 of the second region20is, for example, 0.5 or more. Thereby, for example, a high carrier concentration is obtained easily. The Al composition ratio x2 may be 0.8 or more. The Al composition ratio x2 may be 0.9 or more, and may be substantially 1.

Third Embodiment

FIG. 8AtoFIG. 8Dare schematic cross-sectional views illustrating semiconductor devices according to a third embodiment.

As shown in these drawings, semiconductor devices140ato140dinclude the first region10, the second region20, the third region30, the first to third electrodes51to53, and the insulating portion40. In the semiconductor devices140ato140d, the <0001> direction is aligned with the orientation from the first region10toward the second region20. Other than the description recited below, for example, the configurations of the semiconductor devices140ato140dare similar to the configuration of the semiconductor device110.

In the semiconductor devices140ato140d, a portion of the second region20is provided between the third electrode53and the first region10in the first direction (the Z-axis direction). Another portion of the second region20does not overlap the third electrode53in the first direction (the Z-axis direction). For example, a hole (or a recess) is provided in the second region20; and a portion of the insulating portion40is provided in the hole (or the recess).

In the semiconductor devices140ato140d, for example, a portion of the insulating portion40overlaps the second region20in the second direction (e.g., the X-axis direction).

In the semiconductor devices140cand140d, at least a portion of the third electrode53overlaps the third region30in the second direction (e.g., the X-axis direction).

In the semiconductor device140d, a portion of the insulating portion40overlaps the first region10in the second direction (e.g., the X-axis direction). In the example of the semiconductor device140d, at least a portion of the third electrode53overlaps the second region20in the second direction (the X-axis direction). In the example of the semiconductor device140d, at least a portion of the third electrode53overlaps the first region10in the second direction (the X-axis direction).

In the semiconductor devices140ato140d, a portion of the first insulating layer41is between the third partial region13and the third electrode53in the first direction (the Z-axis direction).

As in the semiconductor devices140bto140d, the portion of the first insulating layer41recited above may contact the third partial region13in the first direction (the Z-axis direction).

For example, a normally-OFF operation is obtained in the semiconductor devices140ato140d. In the semiconductor devices140ato140d, a carrier region (e.g., the two-dimensional electron gas10E) that has a high carrier concentration is obtained.

In the semiconductor device140a, a portion of the second region20(the portion that overlaps the third electrode53) may be thinner than the other portions of the second region20. Even in such a case, for example, the normally-OFF operation is obtained.

Fourth Embodiment

FIG. 9AtoFIG. 9Dare schematic cross-sectional views illustrating semiconductor devices according to a fourth embodiment.

As shown in these drawings, semiconductor devices141ato141dalso include the first region10, the second region20, the third region30, the first to third electrodes51to53, and the insulating portion40. In the semiconductor devices141ato141d, the <000-1> direction is aligned with the orientation from the first region10toward the second region20. Otherwise, the configurations of the semiconductor devices141ato141dare respectively similar to the configurations of the semiconductor devices140ato140d. In the semiconductor devices141ato141d, for example, a carrier region (e.g., the two-dimensional hole gas10H) that has a high carrier concentration is obtained.

In the third embodiment and the fourth embodiment, at least part of the portion of the second region20overlapping the third electrode53in the first direction may be 5 nm or less.

In the first to fourth embodiments recited above, for example, the third region30can be formed by at least one method of chemical vapor deposition (CVD), sputtering, atomic layer deposition (ALD), metal-organic vapor phase epitaxy (MOCVD), molecular beam epitaxy (MBE), etc.

Fifth Embodiment

FIG. 10is a schematic cross-sectional view illustrating a semiconductor device according to a fifth embodiment.

As shown inFIG. 10, the semiconductor device150according to the fifth embodiment includes the first region10, the second region20, and the first to third electrodes51to53. The insulating portion40is further provided in the example. The third region30of the semiconductor device110is not provided in the semiconductor device150. Otherwise, the configuration of the semiconductor device150may be the same as the configuration of the semiconductor device110.

In the semiconductor device150as well, the first region10includes the first material. The first material includes at least one selected from the group consisting of silicon carbide, silicon, carbon, and germanium. The first region10includes the first partial region11, the second partial region12, and the third partial region13. The first region10includes, for example, a crystal.

The direction from the first partial region11toward the first electrode51is aligned with the first direction (the Z-axis direction). The direction from the second partial region12toward the second electrode52is aligned with the first direction. The direction from the third partial region13toward the third electrode53is aligned with the first direction. The second direction (e.g., the X-axis direction) from the first electrode51toward the second electrode52crosses the first direction. The position of the third electrode53in the second direction is between the position of the first electrode51in the second direction and the position of the second electrode52in the second direction.

The second region20includes Alx2Ga1-x2N (0<x2≤1). For example, the second region20includes AlN. At least a portion of the second region20is provided between the first electrode51and the second electrode52in the second direction. The second region20includes, for example, a crystal.

In the embodiment, the thickness t2 along the first direction of the second region20is, for example, not less than 10 nm and not more than 500 nm. Thereby, the high relaxation rate α is easier to obtain. The thickness t2 of the second region20is the thickness (the length) along the first direction (the Z-axis direction). At least a portion of the second region20has a third surface20aand a fourth surface20b(referring toFIG. 10). The third surface20aand the fourth surface20bare aligned with the second direction (e.g., the X-axis direction). For example, these surfaces are along the X-Y plane. The third surface20ais the surface on the first region10side. The third surface20aopposes the first region10. The fourth surface20bis the surface opposite to the third surface20a. In the example, the fourth surface20bopposes the insulating portion40. The distance along the first direction (the Z-axis direction) between the third surface20aand the fourth surface20bcorresponds to the thickness t2.

In the semiconductor device150, the relaxation rate α is greater than 0. For example, the first material of the first region10has the first lattice constant (C1) in one axis direction when unstrained. The Alx2Ga1-x2N (0<x2≤1) has the second lattice constant (C2) in the axis direction recited above when unstrained. The axis direction recited above crosses the first direction. The axis direction recited above is, for example, the a-axis of the second region20. The second region20has the second lattice length (L2) in the axis direction recited above. In the semiconductor device150, the ratio (the relaxation rate α) of the absolute value of the difference between the first lattice constant and the second lattice length to the absolute value of the difference between the first lattice constant and the second lattice constant is greater than 0. The ratio is, for example, 0.15 or more. Thereby, the compressive strain in the second region20can be suppressed; and the sum total of the spontaneous polarization and the piezoelectric polarization can be large. The carrier density of the first region10can be higher.

For example, the relaxation rate α can be controlled by modifying the conditions when forming the second region20. An example will now be described.

FIG. 11AtoFIG. 11Care graphs illustrating characteristics of the semiconductor device.

These figures are examples of reciprocal lattice mapping images of X-ray diffraction measurements of first to third samples CN-1 to CN-3. The horizontal axis is a reciprocal Qx (nm−1) of the lattice plane spacing in the (11-20) plane of the <11-20> direction perpendicular to the growth direction. The reciprocal Qx is a value proportional to the reciprocal of the lattice spacing of the a-axis. The vertical axis is a reciprocal Qy (nm−1) of the lattice plane spacing of the plane of the <0001> direction parallel to the growth direction. The reciprocal Qy is a value proportional to the reciprocal of the lattice spacing of the c-axis.

In the first to third samples CN-1 to CN-3, the first region10is 6H—SiC. A crystal of AlN used to form the second region20is grown on the first region10by modifying the growth conditions. In the example, the flow rate ratio of the source gas is modified. For the first sample CN-1, the ratio of the flow rate of the Group III source material to the flow rate of ammonia is 250000. For the second sample CN-2, the ratio of the flow rate of the Group III source material to the flow rate of ammonia is 8300. For the third sample CN-3, the ratio of the flow rate of the Group III source material to the flow rate of ammonia is 210. In these figures, a point p10corresponds to the lattice of the first region10. A point p20corresponds to the lattice of the second region20.

It can be seen from these figures that the distance in the reciprocal Qx direction between the point p10and the point p20changes greatly as the growth conditions are modified. Also, the position of the point p20changes greatly as the growth conditions are modified. The lattice length (the second lattice length) of the second region20is dependent on the growth conditions.

For example, the relaxation rate α of the first sample CN-1 is 0.74. For example, the relaxation rate α of the second sample CN-2 is 0.58. For example, the relaxation rate α of the third sample CN-3 is 0.15.

In the embodiment, for example, the relaxation rate α can be set to be, for example, 0.15 or more by modifying the growth conditions. For example, the relaxation rate α can be set to be, for example, 0.58 or more by modifying the growth conditions. For example, the relaxation rate α can be set to be, for example, 0.74 or more by modifying the growth conditions. The compressive stress in the second region20can be suppressed by the high relaxation rate α.

FIG. 12is a microscope photograph illustrating the semiconductor device according to the fifth embodiment.

FIG. 12is an example of a TEM image of the cross section of a sample made using the growth conditions of the first sample CN-1. As shown inFIG. 12, a region20rand a region20sare observed in the second region20formed on the first region10. The region20ris provided between the region20sand the first region10. As shown inFIG. 12, the dislocation density in the region20ris higher than the dislocation density in the region20s. In such a region20r, a disturbance of the crystal occurs due to the lattice mismatch between the second region20and the first region10. The lattice is relaxed by the disturbance of the crystal. For example, the region20ris a transition region of the lattice. High uniformity is observed in the region20s. A high relaxation rate α is obtained in the region20s.

FIG. 13is a schematic cross-sectional view illustrating the semiconductor device according to the fifth embodiment.

FIG. 13illustrates a portion of a semiconductor device150aaccording to the fifth embodiment; and the first to third electrodes51to53are not illustrated. In the semiconductor device150a, the region20rwhich is a portion of the second region20is formed on the first region10. On the other hand, the region20swhere the strain is small is separately formed. For example, this region20sis bonded to the region20r. By such a configuration as well, a high relaxation rate α is obtained.

FIG. 14AandFIG. 14Bare schematic cross-sectional views illustrating semiconductor devices according to the third embodiment.

In a semiconductor device151as shown inFIG. 14A, at least a portion of the first electrode51overlaps the first region10in the second direction (e.g., the X-axis direction). At least a portion of the second electrode52overlaps the first region10in the second direction. At least one of the at least a portion of the first electrode51or the at least a portion of the second electrode52may be buried in the first region10.

As shown inFIG. 14B, the fourth region10dand the fifth region10emay be provided in the semiconductor device152. The impurity concentration in the fourth region10dis higher than the impurity concentration in the first partial region11. The impurity concentration in the fifth region10eis higher than the impurity concentration in the second partial region12. The impurity includes, for example, at least one selected from the group consisting of nitrogen (N) and phosphorus (P). For example, the fourth region10dand the fifth region10eare obtained by implanting these elements as the impurity into the region used to form the first region10. The fourth region10dand the fifth region10emay be provided in the semiconductor device151recited above.

Sixth Embodiment

FIG. 15is a schematic cross-sectional view illustrating a semiconductor device according to a sixth embodiment.

As shown inFIG. 15, the semiconductor device160according to the sixth embodiment also includes the first region10, the second region20, and the first to third electrodes51to53. In the semiconductor device120, the <000-1> direction of the second region20has a component in the orientation (the +Z orientation) from the first region10toward the second region20. In such a case as well, a carrier region (e.g., the two-dimensional hole gas10H) is obtained. In the semiconductor device160as well, the relaxation rate α is greater than 0. For example, the relaxation rate α may be 0.15 or more. The relaxation rate α may be 0.58 or more. The relaxation rate α may be 0.74 or more. In the semiconductor device160as well, for example, the compressive stress in the second region20can be suppressed. Thereby, the two-dimensional hole gas10H that has a high concentration is obtained. According to the embodiment, for example, the ON-resistance can be low.

FIG. 16AandFIG. 16Bare schematic cross-sectional views illustrating semiconductor devices according to the sixth embodiment.

As in a semiconductor device161shown inFIG. 16A, at least a portion of the first electrode51may overlap the first region10in the second direction (e.g., the X-axis direction). At least a portion of the second electrode52may overlap the first region10in the second direction.

As in a semiconductor device162shown inFIG. 16B, the fourth region10dand the fifth region10emay be provided. The impurity concentration in the fourth region10dis higher than the impurity concentration in the first partial region11. The impurity concentration in the fifth region10eis higher than the impurity concentration in the second partial region12. The impurity includes, for example, at least one selected from the group consisting of aluminum (Al) and boron (B). For example, the fourth region10dand the fifth region10eare obtained by implanting these elements as the impurity into the region used to form the first region10. The fourth region10dand the fifth region10emay be provided in the semiconductor device161recited above.

In the fifth and sixth embodiments, the Al composition ratio x2 of the second region20is, for example, 0.5 or more. Thereby, for example, a high carrier concentration is obtained easily. The Al composition ratio x2 may be 0.8 or more. The Al composition ratio x2 may be 0.9 or more, and may be substantially 1.

Seventh Embodiment

FIG. 17AtoFIG. 17Dare schematic cross-sectional views illustrating semiconductor devices according to a seventh embodiment.

As shown in these figures, semiconductor devices170ato170dinclude the first region10, the second region20, the first to third electrodes51to53, and the insulating portion40. In the semiconductor devices170ato170d, the <0001> direction is aligned with the orientation from the first region10toward the second region20. Other than the description recited below, the configurations of the semiconductor devices170ato170dmay be similar to, for example, the configuration of the semiconductor device150.

In the semiconductor devices170ato170d, a portion of the second region20is provided between the third electrode53and the first region10in the first direction (the Z-axis direction). Another portion of the second region20does not overlap the third electrode53in the first direction (the Z-axis direction). Other than the third region30not being provided, the configurations of the semiconductor devices140ato140dare applicable to the semiconductor devices170ato170d.

Eighth Embodiment

FIG. 18AtoFIG. 18Dare schematic cross-sectional views illustrating semiconductor devices according to an eighth embodiment.

As shown in these figures, semiconductor devices171ato171dalso include the first region10, the second region20, the first to third electrodes51to53, and the insulating portion40. In the semiconductor devices171ato171d, the <000-1> direction is aligned with the orientation from the first region10toward the second region20. Otherwise, the configurations of the semiconductor devices171ato171dare respectively similar to the configurations of the semiconductor devices170ato170d.

In the semiconductor devices171ato171d, for example, a carrier region (e.g., the two-dimensional hole gas10H) that has a high carrier concentration is obtained.

Other than the third region30not being provided, the configurations of the semiconductor devices141ato141dare applicable to the semiconductor devices171ato171d.

In the first to eighth embodiments recited above, for example, the second region20is formed by at least one selected from the group consisting of MOCVD (metal organic chemical vapor deposition), molecular beam epitaxy (MBE), hydride vapor phase epitaxy (HVPE), sputtering, and pulsed laser deposition.

In the first to eighth embodiments recited above, the absolute value of the difference of the angle between the first direction (the Z-axis direction) and the <0001> direction of the second region20is, for example, 8 degrees or less; or the absolute value of the difference of the angle between the first direction (the Z-axis direction) and the <000-1> direction is, for example, 8 degrees or less. The <0001> direction or the <000-1> direction may be parallel to the first direction (the Z-axis direction). The <0001> direction or the <000-1> direction may be tilted at an angle of 8 degrees or less from the first direction. For example, the absolute value of the angle between the third surface20aon the first region10side of the second region20(referring toFIG. 10, etc.) and the <0001> direction of the second region20is not less than 82 degrees and not more than 98 degrees; or the absolute value of the angle between the third surface20aand the <000-1> direction of the second region20is not less than 82 degrees and not more than 98 degrees. Due to such angles, carriers based on the spontaneous polarization of the crystal of the second region20are generated efficiently in the first region10.

According to the embodiments, a semiconductor device can be provided in which the characteristics can be improved.

In this specification, the “state of being electrically connected” includes the state in which multiple conductive bodies are physically in contact, and a current flows between the multiple conductive bodies. The “state of being electrically connected” includes the state in which another conductive body is inserted between multiple conductive bodies, and a current flows between the multiple conductive bodies.

Moreover, all semiconductor devices practicable by an appropriate design modification by one skilled in the art based on the semiconductor devices described above as embodiments of the invention also are within the scope of the invention to the extent that the spirit of the invention is included.