Intergrating a silicon photonics photodetector with CMOS devices

A method of forming an integrated photonic semiconductor structure having a photonic device and adjacent CMOS devices may include depositing a first silicon nitride layer over the adjacent CMOS devices and depositing an oxide layer over the first silicon nitride layer, wherein the oxide layer conformally covers the first silicon nitride layer and the underlying adjacent CMOS devices to form a substantially planarized surface over the adjacent CMOS devices. A second silicon nitride layer is then deposited over the oxide layer and a region corresponding to forming the photonic device. A germanium layer is deposited over the oxide layer and the region corresponding to forming the photonic device. The germanium layer deposited over the adjacent CMOS devices is etched to form a germanium active layer within the photonic region, whereby the oxide layer and the second silicon nitride layer protect the adjacent CMOS devices during the etching of the germanium.

BACKGROUND

a. Field of the Invention

The present invention generally relates to semiconductor devices, and particularly to integrated photonic semiconductor devices.

b. Background of Invention

The use of both photonic devices in high-speed switching and transceiver devices in data communications are but a few examples that highlight the advantages of processing both optical and electrical signals within a single integrated device. For example, an integrated photonic device may include both photodetector and CMOS type devices that may be fabricated on a single silicon substrate. However, during the fabrication process, certain processes, while benefiting or being necessary for the formation and/or operation of one type of device (e.g., CMOS FET), may be detrimental to the formation and/or operation of the other type of device (e.g., Photodetector).

It may therefore, among other things, be advantageous to maintain, within an integrated photonic device, the integrity of both photonic and non-photonic type devices during fabrication processes.

BRIEF SUMMARY

According to at least one exemplary embodiment, a method of forming an integrated photonic semiconductor structure having a photonic device and adjacent CMOS devices may include depositing a first silicon nitride layer over the adjacent CMOS devices and depositing an oxide layer over the first silicon nitride layer, whereby the oxide layer conformally covers the first silicon nitride layer and the adjacent CMOS devices to form a substantially planarized surface over the adjacent CMOS devices. A second silicon nitride layer is deposited over the oxide layer and a region corresponding to forming the photonic device. A germanium layer is then deposited over the oxide layer and the region corresponding to forming the photonic device. The germanium layer deposited over the adjacent CMOS devices is etched thereby forming a germanium active layer within the region corresponding to forming the photonic device. The oxide layer and the second silicon nitride layer protect the adjacent CMOS devices during the etching of the germanium.

According to at least one other exemplary embodiment, a method of forming an integrated photonic semiconductor structure having a photonic device and adjacent CMOS devices may include depositing an oxide layer over a spacer layer corresponding to the adjacent CMOS devices, whereby the oxide layer conformally covers the spacer layer and the adjacent CMOS devices to form a substantially planarized surface over the adjacent CMOS devices. A silicon nitride layer is deposited over the oxide layer and a region corresponding to forming the photonic device. A germanium layer is then deposited over the oxide layer and the region corresponding to forming the photonic device. The germanium layer deposited over the adjacent CMOS devices is etched to create a germanium active layer within the region corresponding to forming the photonic device such that the oxide layer protects the adjacent CMOS devices during the etching of the germanium.

According to another exemplary embodiment, an integrated photonic semiconductor structure may include a substrate, a photonic device located on the substrate, the photonic device having an active region, and a first silicon nitride layer located on the substrate between the active region and an optical waveguide within the substrate, whereby the first silicon nitride layer mitigates intermixing between the active region and the optical waveguide. The structure further includes adjacent CMOS devices located on the substrate and electrically isolated from the photonic device. Encapsulating layers are located over the active region and encapsulate the active region. A second silicon nitride layer is located on the substrate that covers at least one of the adjacent CMOS devices and the encapsulating layers, such that the second silicon nitride layer protects the at least one of the adjacent CMOS devices and the encapsulating layers during silicide processes. The first and the second silicon nitride layer are separated from each other on the substrate.

DETAILED DESCRIPTION

The following structure and processes provide exemplary embodiments of a CMOS integrated nanophotonics device that includes, for example, both a photonic device such as a germanium (Ge) photodetector and CMOS devices such as adjacent FET transistors. Within CMOS integrated nanophotonic circuits, crystalline materials such as germanium or III-V compounds may be utilized as an active element of the photodetector component based on their high quantum efficiency. Using a rapid melt growth technique, films (e.g., germanium) can be deposited at low temperatures in an amorphous state using techniques such as physical vapor deposition (PVD), plasma enhanced chemical vapor deposition (PECVD), and rapid thermal chemical vapor deposition (RTCVD), and subsequently crystallized thermally. During the crystallization process, the germanium material forming the photodetector active region may be encapsulated, using a multi-layer film stack, in order to prevent crystalline defects and contamination as a result of outdiffusion. However, the deposition of the active region Ge material prior to encapsulation and crystallization of the photodetector may create gaps in the deposited Ge layer in a region over the adjacent FET transistors. These gaps may be caused by a lack of conformity in the deposited Ge layer, which may in turn degrade the underlying structure of the FET transistors. Thus, device integration processes utilizing CMOS device protective layers for preserving the structural integrity of CMOS devices during photonic device formation is described.

FIGS. 1A-1Hare vertical cross-sectional views of an integrated photonic semiconductor device structure according to an exemplary embodiment, which illustrates the formation of a gap or void over the CMOS device region of the structure during Germanium (Ge) layer formation. Referring toFIG. 1A, an integrated photonic semiconductor structure100is illustrated. The integrated photonic semiconductor structure100may include a photonic device formation region101for fabricating, for example, a Germanium (Ge) photodetector (FIG. 1E: photodetector102) and adjacent CMOS devices such as adjacent FET transistors104aand104b. The integrated photonic semiconductor structure100may further include an optical waveguide structure106, a buried oxide (BOX) region108, shallow trench isolation (STI) regions110a-110c, and a silicon substrate112. The BOX region108is located over the silicon substrate112. The optical waveguide structure106may be formed within a silicon-on-insulator (SOI) layer (not shown) of structure100, whereby the STI regions110a-110band BOX region108surrounding the waveguide106facilitate optical confinement (i.e., cladding) and low-loss waveguiding. In addition, STI region110bmay provide electrical isolation between a subsequently formed Germanium (Ge) photodetector within region101and the FET transistors104aand104b.

As depicted, CMOS FET transistor104amay include a gate dielectric114a, a polysilicon gate116a, spacer oxide regions118a, spacer nitride regions120a, source/drain (S/D) regions122a,122b, and halo and extension implants123aand123b. Similarly, CMOS FET transistor104bmay include a gate dielectric114b, a polysilicon gate116b, spacer oxide regions118b,spacer nitride regions120b, source/drain (S/D) regions122b,122c, and halo and extension implants123cand123d. Well region107, the S/D regions122a-122c, and the halo and extension implants123a-123dof FET transistors104aand104bare also formed within the silicon-on-insulator (SOI) layer (not shown). As depicted in the exemplary embodiment, S/D region122bis shared between FET transistors104aand104b.

Referring toFIG. 1B, fabrication of integrated photonic device structure130includes the formation of a Ge crystallization window region within structure100ofFIG. 1A. Prior to creating the crystallization window, a silicon nitride layer136of approximately 500 Å or less may be formed over the surface S of the photonic device formation region101, the STI regions110a-110c, and the CMOS FET transistors104a,104b. As depicted, an opening138may be formed within the silicon nitride layer136and a surface portion of the optical waveguide106by photolithographically patterned resist layer125. During the subsequent formation of a Ge active region132(seeFIG. 1E), a portion of the Ge active region fills opening138in order for the Ge active region132to establish contact with the silicon material of optical waveguide106. Such contact may enable the Ge active region132to utilize the silicon material of optical waveguide106as a seed layer during the crystallization process of the Ge active region at a later process stage.

As shown inFIG. 1C, fabrication of integrated photonic device structure135includes the formation of a deposited Ge layer over structure130ofFIG. 1B. In the illustrated embodiment, upon removal of the patterned resist layer125(FIG. 1B), a PECVD deposition method may be used to deposit a layer of germanium (Ge)137both within opening138and over silicon nitride layer136. A silicon nitride (Si3N4) hard mask layer140is also formed over the top surface of the GE layer137. A photolithographically patterned resist layer142is then formed on the hard mask layer140over portion P of the photonic device formation region101. Based on the PECVD deposition method used, the Ge layer137is deposited with relatively good conformity, such that no gaps or voids are created as a result of depositing Ge material in the narrowly spaced region R located between FET transistors104aand104b. For example, the pitch between the gates of the FET transistors104a,104bmay be in the region of about 0.14 μm or less.

As shown inFIG. 1D, fabrication of integrated photonic device structure135′ includes the formation of a deposited Ge layer over structure130ofFIG. 1Busing a different deposition method. Referring toFIG. 1D, following the removal of the patterned resist layer125(FIG. 1B), a PVD deposition method (e.g., sputter PVD) may be used to deposit a layer of germanium (Ge)137′ both within opening138and over silicon nitride layer136. Likewise, a silicon nitride (Si3N4) hard mask layer140′ is also formed over the top surface of the Ge layer137′. A photolithographically patterned resist layer142′ is then formed over portion P′ of the photonic device formation region101. However, in contrast withFIG. 1C, based on the PVD deposition method used, the Ge layer137′ is deposited with relatively poor conformity, such that a gap G and void V are created within the deposited Ge layer in the narrowly spaced region R located between FET transistors104aand104b. As previously described, the pitch between the gates of the FET transistors104a,104bmay be in the region of about 0.14 μm or less. It may be appreciated that PVD deposition conformity degrades with decreases in the pitch between the gates of the FET devices. Although, PVD provides less conformity relative to CVD deposition processes, PVD is a less costly deposition technique.

FIGS. 1E-1Hillustrate the occurrence of structural degradation within the FET transistors104a,104bduring subsequent process steps based on the poor conformity of the deposited GE layer137′ depicted in structure135′ ofFIG. 1D. Referring toFIG. 1E, the fabrication of integrated photonic device structure140includes the formation of GE active region132by etching the GE layer137′ (FIG. 1D) of structure135′ (FIG. 1D). The region of the Ge layer137′ (FIG. 1D) located under photo resist layer142′ (FIG. 1D) remains to form Ge active region132, while the remaining Ge material is etched away. As depicted, during the etch process, etch gas may pass through the gap G (FIG. 1D) and void V (FIG. 1D) causing some thinning of the silicon nitride layer136, as defined by Tt, within the narrowly spaced region R located between FET transistors104aand104b.

As illustrated, portion F of the bottom portion of the Ge active region132acts as a seed layer by contacting the silicon material of the optical waveguide106. The remaining regions131a,131bof the bottom portion of Ge active region132may be isolated from the silicon optical waveguide106by the silicon nitride layer136. The isolation between the remaining portions131a,131bof the Ge active region132and the silicon optical waveguide106may facilitate the avoidance of the intermixing of germanium from the Ge active region132with the silicon of the optical waveguide106. For example, one effect of such intermixing would be to reduce the responsivity of the Ge active region132and consequently the formed photodetector102.

The optical signal traversing within the optical waveguide structure106may be received by the active region132through the silicon nitride layer136. Although any received optical signal received by the active region132is attenuated by layer136, based on the thickness of this layer136, the attenuation is low enough in order to not impede the operation and sensitivity of the photodetector102.

Referring toFIG. 1F, integrated photonic device structure150includes the formation of encapsulating layers152-158within structure140ofFIG. 1E. As illustrated, a silicon nitride layer152may be deposited over silicon nitride layer136using a low stress plasma enhanced chemical vapor deposition (PECVD) process. The silicon nitride layer152may include a thickness in the range of about 100-1000 Å. Preferably, silicon nitride layer152may have a thickness of approximately 500 Å and act as a buffer layer for subsequently deposited layers such as, for example, oxide layer154and silicon nitride layer156.

An oxide layer154may then be deposited over silicon nitride layer152using either a PECVD or a low temperature thermally activated CVD deposition process. The oxide layer154may have a thickness in the range of about 100-2000 Å. Preferably, oxide layer154may have a thickness of approximately 500 Å and mitigates germanium expansion during the crystallization melt process of the Ge active region132. A silicon nitride layer156may be deposited over oxide layer154using a PECVD deposition process. The silicon nitride layer156may have a thickness in the range of about 500-3000 Å. Preferably, silicon nitride layer156may have a thickness of approximately 1000 Å and mitigates germanium expansion during the crystallization melt process.

Another silicon nitride layer158may optionally be deposited over silicon nitride layer156using a RTCVD deposition process. The silicon nitride layer158may have a thickness in the range of about 500-2000 Å. Preferably, silicon nitride layer158may have a thickness of approximately 1000 Å and acts as a sealant of seams and controller of PECVD morphology.

Referring to integrated photonic device structure160ofFIG. 1G, the formed encapsulating layers152-158of structure150are partially etched from the FET transistors104a,104bduring a first etch process (e.g., a reactive ion etch). During the first etch process, silicon nitride layers156and158are etched down to oxide layer154, while the encapsulating layers152-158covering the Ge active region132remain protected by patterned photoresist layer162. As depicted, residual silicon nitride164from the silicon nitride layer152may remain.

Referring to integrated photonic device structure170ofFIG. 1H, the remaining encapsulating layers152,154of structure160are partially etched from the FET transistors104a,104bduring a second etch process (e.g., a reactive ion etch). During the second etch process, silicon nitride layers152and154are etched, while the encapsulating layers152-158covering the Ge active region132still remain protected by patterned photoresist layer162. As depicted, residual silicon nitride168from the silicon nitride layer156may remain. Also, an over etched region180within the S/D region122bof the FET transistors104a,104bmay ultimately be created as a result of the thinning of silicon nitride136(FIG. 1G), as defined by Tt(FIG. 1G), within the narrowly spaced region R (FIG. 1G) located between FET transistors104aand104b(FIG. 1G). Such over etching may, for example, affect the S/D doping of the S/D region122b,which in turn may cause an undesirable increase in FET device leakage current.

FIGS. 2A-2Lillustrate vertical cross-sectional views of an integrated photonic semiconductor device structure, whereby Ge layer deposition conformity is preserved over the CMOS devices according to a first embodiment. Although, the above described embodiment shows a gap or void (seeFIG. 1D) based on the poor conformity of the deposited Ge layer using a PVD process, the following integration process maintains the conformity of the deposited Ge layer while using such less costly PVD processes (e.g., sputter PVD).

Referring toFIG. 2A, an integrated photonic semiconductor structure200is illustrated. The integrated photonic semiconductor structure200may be identical or similar to that of integrated photonic semiconductor structure100. Thus, integrated photonic semiconductor structure200may include a photonic device formation region201for fabricating, for example, a Germanium (Ge) photodetector (FIG. 2G: photodetector202) and adjacent CMOS devices such as adjacent FET transistors204aand204b. The integrated photonic semiconductor structure200may further include an optical waveguide structure206, a buried oxide (BOX) region208, shallow trench isolation (STI) regions210a-210c, and a silicon substrate212. The BOX region208is located over the silicon substrate212. The optical waveguide structure206may be formed within a silicon-on-insulator (SOI) layer (not shown) of structure200, whereby the STI regions210a-210band BOX region208surrounding the waveguide206facilitate optical confinement (i.e., cladding) and low-loss waveguiding. In addition, STI region210bmay provide electrical isolation between a subsequently formed Germanium (Ge) photodetector within region201and the FET transistors204aand204b.

As depicted, CMOS FET transistor204amay include a gate dielectric214a, a polysilicon gate216a, spacer oxide regions218a, spacer nitride regions220a, source/drain (S/D) regions222a,222b, and halo and extension implants223aand223b. Similarly, CMOS FET transistor204bmay include a gate dielectric214b, a polysilicon gate216b, spacer oxide regions218b,spacer nitride regions220b, source/drain (S/D) regions222b,222c, and halo and extension implants223cand223d. Well region207, the S/D regions222a-222c, and the halo and extension implants223a-223dof FET transistors204aand204bare also formed within the silicon-on-insulator (SOI) layer (not shown). As depicted in the exemplary embodiment, S/D region222bis shared between FET transistors204aand204b.

Referring toFIG. 2B, the fabrication of integrated photonic device structure230includes the deposition of a silicon nitride layer237of approximately 1000 Å or less over the surface S (FIG. 2A) of the photonic device formation region201, the STI regions210a-210c, and the CMOS FET transistors204a,204bof integrated photonic device structure200. The silicon nitride layer237may be used to protect the spacer nitride regions220a,220bduring subsequent etching and silicide processes.

Referring toFIG. 2C, fabrication of integrated photonic device structure235includes a thermal CVD deposition of an oxide layer (e.g., low temperature silicon dioxide)239having a thickness of approximately 500-4000 Å over the silicon nitride layer237of integrated photonic device structure230. As depicted, the deposited thick oxide layer (e.g., silicon dioxide)239creates a substantially planar surface Spover the relatively tightly pitched (e.g.,0.14 μm pitch) CMOS FET transistors204a,204b. The deposited thick oxide layer, therefore, provides a protective layer for the underlying FET transistors204a,204b.

Referring toFIG. 2D, fabrication of integrated photonic device structure240includes the etching (e.g., RIE) of a portion of the deposited oxide layer239(FIG. 2C) and silicon nitride layer237(FIG. 2C) from the photonic device formation region201and the STI regions210a,210bof integrated photonic device structure235(FIG. 2C). As depicted, based on the patterning of a layer of deposited photoresist (not shown), photoresist region241protects underlying oxide region or layer244and silicon nitride layer243, whereby the remaining oxide layer (FIG. 2C) and silicon nitride layer (FIG. 2C) covering the photonic device formation region201and STI regions210a,210bis etched.

Referring toFIG. 2E, fabrication of integrated photonic device structure245includes the formation of a Ge crystallization window region within structure240ofFIG. 2D. Prior to creating the crystallization window, a silicon nitride layer246of approximately 500 Å or less may be formed over the surface S of the photonic device formation region201, the STI regions210a,210b, and the protective oxide layer244. As depicted, an opening248may be formed within the silicon nitride layer246and a surface portion of the optical waveguide206by photolithographically patterned resist layer250. During the subsequent formation of a Ge active region252(seeFIG. 2G), a portion of the Ge active region fills opening248in order for the Ge active region252to establish contact with the silicon material of optical waveguide206. Such contact may enable the Ge active region252to utilize the silicon material of optical waveguide206as a seed layer during the crystallization process of the Ge active region at a later process stage.

As shown inFIG. 2F, fabrication of integrated photonic device structure260includes the formation of a deposited Ge layer over structure245ofFIG. 2E. In the illustrated embodiment, upon removal of the patterned resist layer250(FIG. 2E), a PVD deposition method may be used to deposit a layer of germanium (Ge)262both within opening248and over silicon nitride layer246. A silicon nitride (Si3N4) hard mask layer263is also formed over the top surface of the Ge layer262. A photolithographically patterned resist layer264is then formed on the hard mask layer263over portion P of the photonic device formation region201. Despite utilizing a PVD deposition process, in contrast to the fabricated structure135′ ofFIG. 1D, the Ge layer262is deposited with good conformity, such that no gaps or voids are created. This occurs as a result of growing the Ge layer262over the substantially planar surface of the protective oxide region244rather than within the high aspect ratio region R′ located between FET transistors204aand204b. For example, as previously indicated, the pitch between the gates of the FET transistors204a,204bmay be in the region of about 0.14 μm or less. Moreover, as transistor scaling and gate pitch reduces with technological advancement, further increases in aspect ratio may be observed. Deposition of the layer of germanium (Ge)262over the oxide region244negates such conformity issues, particularly conformity associated with adequately filling high aspect ratio areas located between tightly pitched devices.

Referring toFIG. 2G, the fabrication of integrated photonic device structure265includes the formation of Ge active region252by etching the Ge layer262(FIG. 2F) of structure260(FIG. 2F). The region of the Ge layer262(FIG. 2F) located under photo resist layer264(FIG. 2F) is protected to form Ge active region252, while the remaining Ge material is etched away.

As illustrated, portion F′ of the bottom portion of the Ge active region252may act as a seed layer by contacting the silicon material of the optical waveguide206. The remaining regions231a,231bof the bottom portion of Ge active region252may be isolated from the silicon optical waveguide206by the silicon nitride layer246. The isolation between the remaining portions231a,231bof the Ge active region252and the silicon optical waveguide206may facilitate the avoidance of the intermixing of germanium from the Ge active region252with the silicon of the optical waveguide206. As previously indicated, one effect of such intermixing may be to reduce the responsivity of the Ge active region252and consequently the formed photodetector202.

The optical signal traversing within the optical waveguide structure206may be received by the active region252through the silicon nitride layer246. Although any received optical signal received by the active region252is attenuated by layer246, based on the thickness of this layer246, the attenuation is low enough in order to not impede the operation and sensitivity of the photodetector202.

Referring toFIG. 2H, fabricating integrated photonic device structure270includes the formation of encapsulating layers266-272within structure265ofFIG. 2G. As illustrated, a silicon nitride layer266may be deposited over silicon nitride layer246using a low stress plasma enhanced chemical vapor deposition (PECVD) process. The silicon nitride layer266may include a thickness in the range of about 100-1000 Å. Preferably, silicon nitride layer266may have a thickness of approximately 500 Å and act as a buffer layer for subsequently deposited layers such as, for example, oxide layer268and silicon nitride layer270.

An oxide layer268may then be deposited over silicon nitride layer266using either a PECVD or a low temperature thermally activated CVD deposition process. The oxide layer268may have a thickness in the range of about 100-2000 Å. Preferably, oxide layer268may have a thickness of approximately 500 Å and mitigates germanium expansion during the crystallization melt process of the Ge active region252. A silicon nitride layer270may be deposited over oxide layer268using a PECVD deposition process. The silicon nitride layer270may have a thickness in the range of about 500-3000 Å. Preferably, silicon nitride layer270may have a thickness of approximately 1000 Å and mitigates germanium expansion during the crystallization melt process.

Another silicon nitride layer272may optionally be deposited over silicon nitride layer270using a RTCVD deposition process. The silicon nitride layer272may have a thickness in the range of about 500-2000 Å. Preferably, silicon nitride layer272may have a thickness of approximately 1000 Å and acts as a sealant of seams and controller of PECVD morphology.

Referring to integrated photonic device structure275ofFIG. 2I, the formed encapsulating layers266-272(FIG. 2H) and silicon nitride layer246(FIG. 2H) of structure270(FIG. 2H) are etched from over the protective oxide region244(FIG. 2H) covering the FET transistors204a,204b(FIG. 2H). As depicted inFIG. 2I, the encapsulating layers266-272covering the Ge active region252remain protected by patterned photoresist layer276, while the remaining portion of the encapsulating layers266-272and the silicon nitride layer246are removed. As shown, since the oxide region244includes no gaps or voids at location R′ between the FET transistors204a,204b, the subsequent etching of the encapsulating layers246-272does not cause a thinning of the silicon nitride layer243covering and protecting the FET transistors204a,204bat region280.

Referring to integrated photonic device structure285ofFIG. 2J, the formed oxide region or oxide layer244(FIG. 2I) of structure275(FIG. 2I) is then etched from over the silicon nitride layer243(FIG. 2I) of the FET transistors204a,204b(FIG. 2I). As depicted inFIG. 2J, the processes ofFIGS. 2A-2Jseparate, as defined by S, the silicon nitride layer243deposited over the FET transistors204a,204bfrom the silicon nitride layer246buffered between the optical waveguide206and the bottom portion of Ge active region252. Silicon nitride layer246may be optimized (e.g., thickness) for facilitating receiving optical signals from the waveguide206. The silicon nitride layer243on the other hand may be optimized to protect the spacer regions of the FET transistors204a,204b, as well as providing other properties (e.g., tensile or compressive stress characteristics) that may enhance the electrical properties of the FET transistors204a,204b. Thus, separating the nitride layers243,246may enable the application of independent control over the properties of these layers243,246.

Integrated photonic device structures290and295that are depicted inFIGS. 2K and 2L, respectively, illustrate an optional etching process for facilitating a silicide process for integrated photonic device structure285(FIG. 2J). Referring toFIG. 2K, by depositing a patterned photoresist layer292over both FET transistor204aand encapsulating layers266-272of the Ge active region252, the silicon nitride layer243(FIG. 2J) covering FET transistor204bis etched away in order to accommodate the siliciding process. As illustrated inFIG. 2L, the photoresist layer292is removed and the remaining portion296of silicon nitride layer243(FIG. 2J) protects FET transistor204aduring the siliciding (not shown) of FET transistor204b.

It may be appreciated that according to an alternative embodiment, FET transistors204a,204b(FIG. 2A) may not be fabricated over an active region such as well region207(FIG. 2A). For example, FET transistors204a,204b(FIG. 2A) may be fabricated over an STI region. In such an embodiment, the degradation, as depicted inFIG. 1H, of the region located between the FET transistors may be more prominently impacted by the etch process (e.g., gas, pressure, temp., RF plasma, etc.) since the insulation material of the STI region is more susceptible to the etch process than silicon (e.g.,FIG. 1H: well region107). For example, referring toFIG. 1H, if the FET transistors104a,104bare not located over the well region107, and instead, are fabricated over an STI region (not shown), the etched region180would be larger to the extent that some of the STI material under the gate region of the FET transistors104a,104bmay be removed. In this case, one or both of the FET transistors104a,104bmay lift-off from the STI surface (not shown).

FIGS. 3A-3Jillustrate vertical cross-sectional views of an integrated photonic semiconductor device structure, whereby Ge layer deposition conformity is preserved over the CMOS devices according to a first embodiment. Although, the above described embodiment shows a gap or void (seeFIG. 1D) based on the poor conformity of the deposited Ge layer using a PVD process, the following integration process also maintains the conformity of the deposited GE layer while using such less costly PVD processes (e.g., sputter PVD).

Referring toFIG. 3A, an integrated photonic semiconductor structure300is illustrated. Integrated photonic semiconductor structure300may include a photonic device formation region301for fabricating, for example, a Germanium (Ge) photodetector (FIG. 3F: photodetector302) and adjacent CMOS devices such as adjacent FET transistors304aand304b. The integrated photonic semiconductor structure300may further include an optical waveguide structure306, a buried oxide (BOX) region308, shallow trench isolation (STI) regions310a-310c, and a silicon substrate312. The BOX region308is located over the silicon substrate312. The optical waveguide structure306may be formed within a silicon-on-insulator (SOI) layer (not shown) of structure300, whereby the STI regions310a-310band BOX region308surrounding the waveguide306facilitate optical confinement (i.e., cladding) and low-loss waveguiding. In addition, STI region310bmay provide electrical isolation between a subsequently formed Germanium (Ge) photodetector within region301and the FET transistors304a,304b.

As depicted, CMOS FET transistor304amay include a gate dielectric314a, a polysilicon gate316a, spacer oxide regions318a, source/drain (S/D) formation regions322a,322b, and halo and extension implants323aand323b. Similarly, CMOS FET transistor304bmay include a gate dielectric314b, a polysilicon gate316b, spacer oxide regions318b, source/drain (S/D) formation regions322b,322c, and halo and extension implants323cand323d. In the depicted embodiments ofFIGS. 3A-3H, the source/drain (S/D) formation regions, as defined by dotted regions322a-322c, are indicative of the region where the S/D regions are ultimately formed during subsequent process steps. Well region307, the S/D formation regions322a-322c, and the halo and extension implants323a-323dof FET transistors304aand304bare also formed within the silicon-on-insulator (SOI) layer (not shown). As depicted in the exemplary embodiment, S/D formation region322bis shared between FET transistors304aand304b. A silicon nitride layer320is deposited over region301, the STI regions310a-310c, and the FET transistors304a,304b. The silicon nitride layer320may be used to form nitride spacers for the FET transistors304a,304bduring subsequent processing steps.

Since the formed nitride spacers define the source/drain regions, the source/drain regions are not formed until after the nitride layer320is etched (FIG. 3I) to form the spacers. After the nitride spacers are formed (FIG. 3I), then the S/D implant process occurs to form the S/D regions322a′-322c′ (FIG. 3I) at source/drain (S/D) formation regions322a-322c. Thus, following the removal of encapsulation films and protective oxide layer inFIG. 3H, the photodetector regions are masked with resist and the nitride spacer layer343(FIG. 3H) is etched, as shown inFIG. 3I. S/D dopants are then implanted into S/D regions of the FETs and the resist mask is subsequently removed. This applies not only to S/D implants but to other implants that occur after the nitride spacers are formed, including, for example, photonic modulator implants and CMOS resistor implants.

Referring toFIG. 3B, fabrication of integrated photonic device structure335includes a thermal CVD deposition of an oxide layer (e.g., low temperature silicon dioxide)339having a thickness of approximately 500-4000 Å over the silicon nitride layer320of integrated photonic device structure300. As depicted, the deposited thick oxide layer (e.g., silicon dioxide)339creates a substantially planar surface Spover the relatively tightly pitched (e.g., 0.14 μm pitch) CMOS FET transistors304a,304b. The deposited thick oxide layer, therefore, provides a protective layer for the underlying FET transistors304a,304b.

Referring toFIG. 3C, fabrication of integrated photonic device structure340includes the etching (e.g., RIE) of a portion of the deposited oxide layer339(FIG. 3B) and silicon nitride layer320(FIG. 3B) from the photonic device formation region301and the STI regions310a,310bof integrated photonic device structure335(FIG. 3B). As depicted, based on the patterning of a layer of deposited photoresist (not shown), photoresist region341protects underlying oxide region or layer344and silicon nitride layer343, whereby the remaining oxide layer (FIG. 3B) and silicon nitride layer (FIG. 3B) covering the photonic device formation region301and STI regions310a,310bis etched.

Referring toFIG. 3D, fabrication of integrated photonic device structure345includes the formation of a Ge crystallization window region within structure340ofFIG. 3C. Prior to creating the crystallization window, a silicon nitride layer346of approximately 500 Å or less may be formed over the surface S of the photonic device formation region301, the STI regions310a,310b, and the protective oxide layer344. As depicted, an opening348may be formed within the silicon nitride layer346and a surface portion of the optical waveguide306by photolithographically patterning resist layer350. During the subsequent formation of a Ge active region352(seeFIG. 3F), a portion of the Ge active region fills opening348in order for the Ge active region352to establish contact with the silicon material of optical waveguide306. As previously described, such contact may enable the Ge active region352to utilize the silicon material of optical waveguide306as a seed layer during the crystallization process of the Ge active region at a later process stage.

As shown inFIG. 3E, fabrication of integrated photonic device structure360includes the formation of a deposited Ge layer over structure345ofFIG. 3D. In the illustrated embodiment, upon removal of the patterned resist layer350(FIG. 3D), a PVD deposition method may be used to deposit a layer of germanium (Ge)362both within opening348and over silicon nitride layer346. A silicon nitride (Si3N4) hard mask layer363is also formed over the top surface of the GE layer362. A photolithographically patterned resist layer364is then formed on the hard mask layer363over portion P of the photonic device formation region301. Despite utilizing a PVD deposition process, in contrast to the fabricated structure135′ ofFIG. 1D, the Ge layer362is deposited with good conformity, such that no gaps or voids are created. This occurs as a result of growing the Ge layer362over the substantially planar surface of the protective oxide region344rather than within the high aspect ratio region R′ located between FET transistors304aand304b. For example, as previously indicated, the pitch between the gates of the FET transistors304a,304bmay be in the region of about 0.14 μm or less. Moreover, as transistor scaling and gate pitch reduces with technological advancement, further increases in aspect ratio may be observed. Deposition of the layer of germanium (Ge)362over the oxide region344negates such conformity issues, particularly conformity associated with adequately filling high aspect ratio areas located between tightly pitched devices.

Referring toFIG. 3F, the fabrication of integrated photonic device structure365includes the formation of Ge active region352by etching the Ge layer362(FIG. 3E) of structure360(FIG. 2F). The region of the Ge layer362(FIG. 3E) located under photo resist layer364(FIG. 3E) is protected to form Ge active region352, while the remaining Ge material is etched away.

As illustrated, portion F′ of the bottom portion of the Ge active region352may act as a seed layer by contacting the silicon material of the optical waveguide306. The remaining regions331a,331bof the bottom portion of Ge active region252may be isolated from the silicon optical waveguide306by the silicon nitride layer346. The isolation between the remaining portions331a,331bof the Ge active region352and the silicon optical waveguide306may facilitate the avoidance of the intermixing of germanium from the Ge active region352with the silicon of the optical waveguide306. As previously indicated, one effect of such intermixing may be to reduce the responsivity of the Ge active region352and consequently the formed photodetector302.

The optical signal traversing within the optical waveguide structure306may be received by the active region352through the silicon nitride layer346. Although any received optical signal received by the active region352is attenuated by layer346, based on the thickness of this layer346, the attenuation is low enough in order to not impede the operation and sensitivity of the photodetector302.

Referring toFIG. 3G, fabricating integrated photonic device structure370includes the formation of encapsulating layers366-372within structure365ofFIG. 3F. As illustrated, a silicon nitride layer366may be deposited over silicon nitride layer346using a low stress plasma enhanced chemical vapor deposition (PECVD) process. The silicon nitride layer366may include a thickness in the range of about 100-1000 Å. Preferably, silicon nitride layer366may have a thickness of approximately 500 Å and act as a buffer layer for subsequently deposited layers such as, for example, oxide layer368and silicon nitride layer370.

An oxide layer368may then be deposited over silicon nitride layer366using either a PECVD or a low temperature thermally activated CVD deposition process. The oxide layer368may have a thickness in the range of about 100-2000 Å. Preferably, oxide layer368may have a thickness of approximately 500 Å and mitigates germanium expansion during the crystallization melt process of the Ge active region352. A silicon nitride layer370may be deposited over oxide layer368using a PECVD deposition process. The silicon nitride layer370may have a thickness in the range of about 500-3000 Å. Preferably, silicon nitride layer370may have a thickness of approximately 1000 Å and mitigates germanium expansion during the crystallization melt process.

Another silicon nitride layer372may optionally be deposited over silicon nitride layer370using a RTCVD deposition process. The silicon nitride layer372may have a thickness in the range of about 500-2000 Å. Preferably, silicon nitride layer372may have a thickness of approximately 1000 Å and acts as a sealant of seams and controller of PECVD morphology.

Referring to integrated photonic device structure375ofFIG. 3H, the formed encapsulating layers366-372(FIG. 3G) and silicon nitride layer346(FIG. 3G) of structure370(FIG. 3G) are etched from over the protective oxide region344(FIG. 3G) covering the FET transistors304a,304b(FIG. 3G). As depicted inFIG. 3H, the encapsulating layers366-372covering the Ge active region352remain protected by patterned photoresist layer376, while the remaining portion of the encapsulating layers366-372and the silicon nitride layer346are removed.

As shown inFIG. 3G, since the oxide region344includes no gaps or voids at location R′ between the FET transistors304a,304b, any subsequent etching (FIG. 3H) of the encapsulating layers346-372does not cause a thinning of the silicon nitride layer343(FIG. 3H) forming the nitride spacers of the FET transistors304a,304b(FIG. 3H) at region380(FIG. 3H).

Further referring toFIG. 3H, the formed oxide region or oxide layer344(FIG. 3G) of structure370(FIG. 3G) is etched from over the silicon nitride layer343of the FET transistors304a,304b(FIG. 3G). For example, oxide layer344may be removed by an HF wet etch process.

As illustrated inFIG. 3I, fabricating integrated photonic device structure380includes forming nitride spacers385aand385bfrom the silicon nitride layer343(FIG. 3H) of integrated photonic device structure375. Portions of the silicon nitride layer343(FIG. 3H) are etched to form nitride spacers385aand385b. In particular, nitride spacers385aand385bare formed by etching regions387a-387cand regions390a-390bof the silicon nitride layer343(FIG. 3H). Although not shown, the photodetector region is protected with a photoresist layer identical to resist layer376(FIG. 3H) during the etching and S/D implant, as well as any other post nitride spacer formation implant processes. As previously indicated, the formed nitride spacers385a,385bdefine the source/drain regions. Thus, after the nitride spacers are formed385a,385b, then the S/D implant process (e.g., S/D implant process) occurs to form the S/D regions322a′-322c′ at source/drain (S/D) formation regions322a-322c(e.g.,FIG. 3A).

Referring toFIG. 3J, fabricating integrated photonic device structure390includes forming additional protective silicon nitride layers392and394over integrated photonic device structure380ofFIG. 3I. As depicted, silicon nitride layer392is deposited over encapsulating layer372in order to protect the underlying Ge active region352from contamination caused by silicide clean process chemicals penetrating cracks in the encapsulating layers366-372. Thus, silicon nitride layer392provides an added layer of encapsulating protection for the Ge active layer352. Similarly, silicon nitride layer394may be deposited over one of the FET transistors304a,304bin order to protect the FET transistor from a silicide process applied to the other FET transistor. As depicted, for example, silicon nitride layer394may be deposited over and protect FET transistor304aduring the siliciding of FET transistor304b. Layers392and394can be one continuous layer such that the gap between392and394is filled in with nitride. However, as depicted, it may be separated.

It may be appreciated that according to an alternative embodiment, FET transistors304a,304b(FIG. 3A) may not be fabricated over an active region such as well region307(FIG. 3A). For example, FET transistors304a,304b(FIG. 3A) may be fabricated over an STI region. In such an embodiment, the degradation, as depicted inFIG. 1H, of the region located between the FET transistors may be more prominently impacted by the etch process since the insulation material of the STI region is more susceptible to the etch process than silicon (e.g.,FIG. 1H: well region107). For example, referring toFIG. 1H, if the FET transistors104a,104bare not located over the well region107, and instead, are fabricated over an STI region (not shown), the etched region180(FIG. 1H) would be larger to the extent that some of the STI material under the gate region of the FET transistors104a,104bmay be removed. In this case, one or both of the FET transistors104a,104bmay lift-off from the STI surface (not shown).

Accordingly, the foregoing described embodiments may provide, among other things, fabrication processes for forming a protective low temperature oxide layer over adjacent FET transistors in order to protect the FETs during subsequent Ge layer deposition and other processes. Although the conformal deposition of the oxide layers is carried by thermal CVD, the oxide layer deposition occurs using a low temperature CVD in comparison to directly depositing a Ge layer over the FETs using thermal CVD at a higher temperature. Depositing the Ge layer over the FETs using thermal CVD at a higher temperature may adversely affect the underlying FET devices in terms of their respective electrical characteristics. Moreover, the directly deposited Ge layer may include different impurities such as metals, which when directly applied over the FETs using the higher temperature CVD process, can ultimately interact with and, for example, affect the electrical characteristics of the FET transistors. Thus, the foregoing exemplary embodiments depositing an oxide layer over the FETs alleviate, among other things, one or more adverse consequences associated with directly depositing a layer of Ge over adjacent FET transistors.

FIG. 4shows a block diagram of an exemplary design flow900used for example, in semiconductor IC logic design, simulation, test, layout, and manufacture. Design flow900includes processes and mechanisms for processing design structures or devices to generate logically or otherwise functionally equivalent representations of the design structures and/or devices described above and shown inFIGS. 2L and 3J. The design structure processed and/or generated by design flow900may be encoded on machine-readable transmission or storage media to include data and/or instructions that when executed or otherwise processed on a data processing system generate a logically, structurally, mechanically, or otherwise functionally equivalent representation of hardware components, circuits, devices, or systems.

FIG. 4illustrates multiple such design structures including an input design structure920that is preferably processed by a design process910. In one embodiment, the design structure920comprises design data used in a design process and comprising information describing the embodiments of the invention with respect to the structures as shown inFIGS. 2L and 3J. The design data in the form of schematics or HDL, a hardware-description language (e.g., Verilog, VHDL, C, etc.) may be embodied on one or more machine readable media. For example, design structure920may be a text file, numerical data or a graphical representation of the embodiments of the invention shown inFIGS. 2L and 3J. Design structure920may be a logical simulation design structure generated and processed by design process910to produce a logically equivalent functional representation of a hardware device. Design structure920may also or alternatively comprise data and/or program instructions that when processed by design process910, generate a functional representation of the physical structure of a hardware device. Whether representing functional and/or structural design features, design structure920may be generated using electronic computer-aided design (ECAD) such as implemented by a core developer/designer. When encoded on a machine-readable data transmission, gate array, or storage medium, design structure920may be accessed and processed by one or more hardware and/or software modules within design process910to simulate or otherwise functionally represent an electronic component, circuit, electronic or logic module, apparatus, device, or system such as those shown inFIGS. 2L and 3J. As such, design structure920may comprise files or other data structures including human and/or machine-readable source code, compiled structures, and computer-executable code structures that when processed by a design or simulation data processing system, functionally simulate or otherwise represent circuits or other levels of hardware logic design. Such data structures may include hardware-description language (HDL) design entities or other data structures conforming to and/or compatible with lower-level HDL design languages such as Verilog and VHDL, and/or higher level design languages such as C or C++.

Design process910employs and incorporates logic and physical design tools such as HDL compilers and simulation model build tools to process design structure920together with some or all of the depicted supporting data structures along with any additional mechanical design or data (if applicable), to generate a second design structure990comprising second design data embodied on a storage medium in a data format used for the exchange of layout data of integrated circuits and/or symbolic data format (e.g. information stored in a GDSII (GDS2), GL1, OASIS, map files, or any other suitable format for storing such design structures). In one embodiment, the second design data resides on a storage medium or programmable gate array in a data format used for the exchange of data of mechanical devices and structures (e.g. information stored in a IGES, DXF, Parasolid XT, JT, DRG, or any other suitable format for storing or rendering such mechanical design structures). Similar to design structure920, design structure990preferably comprises one or more files, data structures, or other computer-encoded data or instructions that reside on transmission or data storage media and that when processed by an ECAD system generate a logically or otherwise functionally equivalent form of the embodiments of the invention shown inFIGS. 2L and 3J. In one embodiment, design structure990may comprise a compiled, executable HDL simulation model that functionally simulates the devices shown inFIGS. 2L and 3J.

Design structure990may also employ a data format used for the exchange of layout data of integrated circuits and/or symbolic data format (e.g. information stored in a GDSII (GDS2), GL1, OASIS, map files, or any other suitable format for storing such design data structures).

Design structure990may comprise information such as, for example, symbolic data, map files, test data files, design content files, manufacturing data, layout parameters, wires, levels of metal, vias, shapes, data for routing through the manufacturing line, and any other data required by a manufacturer or other designer/developer to produce devices or structures as described above and shown inFIGS. 2L and 3J. Design structure990may then proceed to a stage995where, for example, design structure990: proceeds to tape-out, is released to manufacturing, is released to a mask house, is sent to another design house, is sent back to the customer, etc.