High-speed data recovery with minimal clock generation and recovery

A data transmission link includes a transmitter superpositioning a data signal and a clock signal to generate a first signal. The transmitter transmits the first signal, through a link, wherein, the clock signal has a frequency equal to or higher than a Nyquist frequency of the data signal.

TECHNICAL FIELD

The invention relates to high-speed data transmission links, and more particularly to clock generation and recovery in high-speed data transmission links.

BACKGROUND ART

High-speed transmissions links, including transceivers, are used for a wide variety of applications. For example, among others, consumer electronics, such as smart phones, base stations, and between servers and switches in high-performance computing and networking are common applications.

This wide use is due in part to the advancement of technology allowing for high-speed transmission of information, for example in the Gigabits/second range. As technology continues to improve, there is an increasing demand on communications links/channel to keep up and reliably transmit data. In general, high-speed transmission links currently suffer from noise-induced disruptions and even loss of data in some cases.

SUMMARY OF VARIOUS EMBODIMENTS

In an embodiment of the invention, a data transmission link includes a receiver responsive to a first transmitted signal through a transmission link. The first transmitted signal includes a clock signal superpositioned onto a data signal. Particularly in applications requiring high-speed communications, the skew error between the data signal and the clock signal that is used to sample the data signal, at the destination receiver, is eliminated or minimized. At the link destination, a first filter receives the first transmitted signal and substantially removes the clock signal from the first transmitted signal, thereby extracting a first data signal therefrom. A second filter receives the first transmitted signal and substantially removes the data signal from the first transmitted signal, thereby extracting a first clock signal therefrom. An adjustable de-skew circuit is coupled to the second filter, receives the first clock signal and substantially removes the first clock signal skew error relative to the data signal, to generate a second clock signal, wherein the first data signal is sampled using the second clock signal to increase the timing margin at sampling point thus the reliability of data detection.

In some embodiments, the data transmission link includes a skew-error detection circuit that detects the skew error between the first clock signal of the transmitted first signal and the center of at least some of the each of the data symbols of the series of data symbols. The skew-error detection circuit is coupled with a skew-control circuit that receives the skew error and performs averaging of the skew error over a predetermined number of data symbols and applies the averaged skew errors to the adjustable de-skew circuit.

In some embodiments, the transmitted first signal is a form of a first signal after the first signal travels through the transmission link, the first signal includes a differential data signal and a common-mode dock signal, where the first signal is transmitted by a transmitter that includes a differential transmission channel that superpositions the differential data signal and the common-mode dock signal before the first signal is transmitted to the receiver.

DETAILED DESCRIPTION OF SPECIFIC EMBODIMENTS

In various embodiments, a receiver of a data transmission link receives a transmitted first signal through a transmission link, the transmitted first signal including a transmitted superposition of a data signal and a clock signal, where the data signal is made of a series of data symbols. The data transmission link further includes a first filter and a second filter where the first filter receives the transmitted first signal and substantially removes the clock signal from the transmitted superposition of a data signal and a clock signal, extracting the data signal therefrom. The second filter also receives the transmitted first signal and substantially removes the data signal of the transmitted superposition of a data signal and a clock signal, extracting a first clock signal therefrom. The first clock signal includes a skew error relative to the data signal at the destination (transceiver/receiver), introduced to the transmitted first signal during transmission of a first signal through the transmission link, separate filtering process and buffering of data signal and clock signal. The data transmission link further includes an adjustable de-skew circuit coupled to the second filter and receiving the first clock signal to substantially remove the skew error relative to the data signal from the first clock signal and generate a second clock signal. The receiver samples the extracted data signal using the second clock signal by sampling at least some of each of the data symbols of the series of data symbols of the extracted data signal substantially at a center of each data symbol.

FIGS. 1, 2A, and 2Bschematically illustrate transmitters of various embodiments of the invention. With reference toFIG. 1, a transmitter100, which is typically a part of a data transmission link, is shown to include a clock signal generator102, a data converter104, and a combiner106(also referred to herein as the “summer”), in accordance with some of the embodiments of the invention. The data converter104is shown to receive digital data, i.e. data/information in digital form, and convert the received digital data to analog data, at a sampling rate dictated by a clock signal that is generated by the clock signal generator102. The analog data and the clock signal from the generator102are combined with each other, by the combiner106, to generate an output signal. That is, data and clock are superpositioned or superimposed onto each other. The output signal, generated by the combiner106, is therefore made of superpositioned (or superimposed) clock signal and analog data in analog form. The combiner106is merely an exemplary embodiment of superpositioning and other methods, suitable for the data and clock, may be substituted. The output signal is typically transmitted from the transmitter100to a transceiver or (destination) receiver over a transmission link, as will be further discussed below. The converter104needs to sample data at a rate that is at least equal to the Nyquist rate/frequency of data symbol rate.

The transmitter100, along with any of the transmitter of the various embodiments of the invention, may be employed in any application that requires the transmission of information over a link at high speeds. In some embodiments, the transmitter100is formed in a semiconductor, IC (Integrated Circuit) or “chip” that communicates with another chip of a device that is physically located externally to a device that houses it or located in the same device as that which houses it. For instance, the transmitter100may be formed in a smart phone that is in communication with the transceiver (or receiver) of a base station or it may be located in the same smart phone as that which houses a receiver.

FIG. 2Aschematically illustrates a differential transmitter of various embodiments of the invention. The embodiment ofFIG. 2Ais analogous to that ofFIG. 1except that the transmitter200, inFIG. 2A, has a combiner206instead of the combiner106and the data converter204has a differential output, i.e. differential analog data, in place of the analog data, the output of the data converter104. The clock signal of the transmitter200, generated from the clock signal generator202, is input to both inputs of the combiner206. The clock signal is added equally and with same polarity to each of the data outputs of the differential analog data, as shown inFIG. 2A. Therefore, two summation operations are performed by the combiner206, one for each output of the differential analog data. In this respect, the output of the combiner206is two signals, each carrying data and clock information wherein output is composed collectively of a differential data signal plus a common-mode clock signal. This is referred to herein as the “common-mode clock”.

FIG. 2Bschematically illustrates a yet another transmitter embodiment in accordance with some embodiments of the invention. InFIG. 2B, the transmitter300is shown to include a clock signal generator302and a data converter304, much in the same manner as that which is shown relative to the transmitter100except that the output of the converter304and the clock signal generated by the clock signal generator302are transmitted independently over separate channels. The clock generator can be formed on the same or a different chip (or device) relative to the transmitter and transmitted to the transmitter304as well as to the destination receiver located on a receiving part of the link.

FIG. 3shows a graph of the power spectrum density (PSD) of various transmitters of the invention. InFIG. 3, the curve301represents the (analog) data spectrum, for example, representing the output of each of the transmitters100,200, and300of the invention although it is understood that other transmitters may be employed and that the transmitters100,200, and300or any others shown and/or discussed herein are merely examples provided for the purposes of discussion.FIG. 3also shows the Nyquist frequency, at fNyquist, the minimum rate at which the data at the output of the transmitter must be sampled without introducing errors into the data. The Nyquist frequency is half the data signal symbol rate, or half the minimum required clock sampling frequency for proper reconstruction of the data post sampling. The graph ofFIG. 3also shows a couple of examples of the frequency (or rate) of the clock signal generated by the clock signal generator, such as, without limitation, the clock signals used to generate the output data signals in the transmitters100,200, and300. In one example, the clock rate is 2×fNyquist, that falls in the notch frequency of the data signal power spectrum. In this scenario, the clock signal is filtered out from the data signal by any low-pass filter with a above fNyquistand below 2×fNyquist. Such large range for the low-pass filter bandwidth relaxes the filter design implementation; however, transmitting & recovering the clock signal at such high frequency in a very low-pass channels leads to very small clock signal at the receiver, and thus can add to the receiver clock recovery challenges. In another example, clock signal frequency is M/N times the Nyquist frequency, with “M” and “N” each representing an integer value. In accordance with an exemplary and practical implementation, the M/N ratio may be between one and two. Maintaining the ratio of M/N above unity generally keeps the clock signal frequency outside of the data signal Nyquist (frequency) band allowing for ease-of-recovery of the data by a low-pass filter with a bandwidth of fNyquist. In contrast, maintaining the ratio of M/N below the value two (2) reduces the attenuation typically experienced by the clock signal when traveling through a low-pass transmission channel.

On the receiver side, a clock frequency at 2×fNyquistis generally required for the purpose of sampling the data signal in an effort to recover the data signal by sampling data symbols, which form, at least in part, the data signal. In the event the clock signal has a frequency of 2×fNyquistor thereabout, when transmitted, the receiver only needs to extract the clock signal, a bandpass filter with a bandwidth of 2×fNyquistor thereabout, can be employed to de-skew (or adjust) the timing of the clock signal for reliable data sampling.

In the case where the clock signal has a frequency that is M/N times the fNyquist, or thereabout, when transmitted, the receiver needs to extract the clock signal with a bandpass filter having a bandwidth frequency of about M/N×fNyquist. The filtered clock signal is multiplied by 2×N/M to arrive at a frequency of 2×fNyquist. Alternatively, the clock signal is multiplied by a ratio N/M to generate a clock signal with the frequency fNyquist, or thereabout, and that is a differential signal, to cause sampling at the both edges of the clock signal, i.e. rising and falling edges, therefore resulting in an effective sampling rate of approximately 2×fNyquist.

FIGS. 4A-4Hschematically illustrate data transmission links, in accordance with some embodiments of the invention. InFIG. 4A, a data communication link400is shown to include a transmitter402and a transceiver412, in communication with each other through a link408, which may be a wired or a wireless link. Typically, in applications where data is communicated at a fast rate, the embodiments of the invention offer an advantage over those currently known in the art.

The transmitter402is similar to the transmitter100and therefore includes a clock signal generator401, a data converter404and a combiner406. The converter404may also be viewed as a data transmitter, as with all transmitters shown and discussed herein. Data to be transmitted, typically in digital form, is received by the converter404and processed at a rate dictated by the clock signal which is generated by the clock signal generator401. The data is ultimately output in analog form, by the converter404, and combined (or summed) with the clock, generated by the clock signal generator401, also referred to herein as the “transmitter clock”, and the combination thereof is output onto the link408and received by the transceiver412. At the transceiver412however, the data arrives with some noise interjected by the link408, and is therefore in altered form. It is obviously desirable to reconstruct the data at the output of the transmitter402. This is done by the transceiver412.

The transceiver412is shown to include a transmitter410(also referred to herein as “transmitter sampler), a receiver sampler418, a summer414, a low pass filter420, a bandpass filter422, a skew error detector424, a skew controller416, an adjustable de-skewer circuit428(sometimes referred to herein as the “de-skewer”), and a clock amplifier (or clock buffer)426although the amplifier426is optional. The low pass filter420and the bandpass filter422each receive the data from the link408and one is used to extract the data transmitted by the transmitter402and the other is used to extract the clock signal transmitted by the transmitter402.

The combination of the skew error detector424, the skew controller416and the de-skewer428is referred to herein as the “skew-error detection circuit”. The skew-error detection circuit detects the skew error between the extracted clock signal and the center of a data symbol. The skew controller416of the skew-error detection circuit receives the skew error (from the skew error detector424) and performs averaging of the skew error over a predetermined number of data symbols and applies the averaged skew errors. The clock signal is adjusted using the skew error such that, for example, in the case where the skew error is 10 pico seconds, the edges of the clock signal are delayed by 10 pico seconds or adjusted ahead by 10 pico seconds. The adjustable de-skew circuit428makes this correction therefore substantially removing the clock signal-to-data signal skew error.

The receiver sampler418is shown coupled to the low pass filter420and samples the output of the low pass filter420, at a rate of the receiver clock signal, which is received from the de-skewer428. The de-skewer428is shown to receive input from the amplifier426and from the skew controller416and uses the same to generate the receiver clock employed by the receiver sampler418. The sampled values, generated by the sampler418, is shown as the “digital receiver data” and provided as input to the skew error detector424. The skew controller416acts as the interface between the de-skewer428and the skew error detector424in that it determines how much and when to provide the skew error correction, generated by the skew error detector424, and when not to do so. The averaged skew error from the skew error detector424is ultimately used by the de-skewer428to remove the timing skew between the sampling clock and the data received at the input of the transceiver412. The de-skewer428is an adjustable de-skewer circuit that essentially adjusts the clock signal used by the sampler418to sample the in-coming data signal (the product of the low pass filtered data), at a location within each of the data samples that is substantially in the middle of the data symbol to increase the reliability of the data being received from the transmitter. A data symbol is made of a set of data samples and represents a value or information, in digital form, that is transmitted from the transmitter402to the transceiver412.

The de-skewer428is able to remove the skew from the data by providing an output that is used by the sampler418to sample the output from the low pass filter420. In this manner, the time of sampling of the data signal is adjusted to account for the skew error introduced during signal transmission. The use of the low pass filter420causes the data signal, rather than the clock signal to remain in the signal received at the time of sampling by sampler418. As shown in the graph ofFIG. 3, a suitable low pass filter should eliminate signals with frequencies higher than the Nyquist rate or thereabouts. Because the clock rate, an example of which is also shown inFIG. 3, is higher than the Nyquist rate, the clock signal, sent in combination with data, should be removed.

Conversely, a bandpass filter, such as the filter422, which eliminates signals having a lower frequency, such as signals with frequencies at the Nyquist frequency or lower, is employed to eliminate the relevant part of the data signal while leaving the clock signal. After substantial elimination of the data signals, the filtered clock signal (or output of the filter422), also referred to herein as the “recovered clock”, is received by the amplifier426and the output of the amplifier426is received as input by the de-skewer428. The amplifier426may be a buffer in some embodiments of the invention.

The receiver clock, i.e. output of the de-skewer428, is also shown to be provided to the summer414of the transceiver412. This is done for use in transmitting data by the transceiver412. More specifically, digital data can be transmitted by the transceiver412, in analog form, by converting the digital data using the converter410, with the digital data being sampled at the rate of the receiver clock, and then summed, by the summer414with the receiver clock before being transmitted. Accordingly, the output of the summer414, which is essentially the output of the transceiver412, is a signal made of both data and clock. In scenarios where the transceiver412transmits data signals back to the transceiver402or any other transceiver/receiver that uses a clock signal from a source common to the transceiver402, there is no need to add the clock and data signals at the transceiver412because the clock signal is already available at the destination receiver and clock recovery from the received data signal is therefore unnecessary.

FIG. 4Bshows a data transmission link500, in accordance with another embodiment of the invention. The data transmission link500is a combination of the transmitter200ofFIG. 2A, referenced as the transmitter502inFIG. 4B, with the transceiver512. Thus, the output of the transmitter502is a differential output that carries a combination of data and a common-mode clock and is transmitted by the transmitter502, through the link508, to the transceiver512.

The transceiver512is shown to include a receiver sampler518, a transmitter510(or “converter”), an amplifier526, a summer522and another summer514, a de-skewer528, a subtractor520, which can be a summer, a skew error detector524, and a skew controller516. As discussed with reference toFIG. 4A, the transceiver512may also transmit data, in addition to receiving data. The transmitter is made of the summer514and the converter (or “data transmitter”)510, the latter using a recovered clock signal generated by the transceiver512, to sample the data that is to be transmitted (or convert the data from a digital form to an analog form using the recovered clock), and the former combining in analog domain the recovered clock signal with the data signal from the transmitter510, into a combined signal that is output by the summer514. The common-mode clock signal is added to both transmitter510differential output signals by the summer514, to generate a new pair of output signals for transmission.

The receiver portion of the transceiver512is made of all other components shown within the transceiver512(except the summer514and the sampler510). A differential link508carries a differential signal that is a combination of differential data signal and common-mode clock signal. When received through the link508, by the transceiver512, the combined data and clock signals, i.e. the received differential signal, includes a skew error introduced during transmission through the link508, which must be removed, at least substantially. This is done by the receiver portion of the transceiver512by adding the two parts of the received differential signals together, using the summer522, to generate a single signal where the differential data signal is substantially removed while the common-mode clock signal remains. The single signal is amplified by the amplifier526, and ultimately provided, after amplification, to the de-skewer528for removal of the skew error.

Additionally, the received differential signals are subtracted from one another by the subtractor520and provided as a single input to the sampler518for sampling and conversion from analog form to digital form. It is understood that the receiver samplers of the transceivers shown and discussed herein, such as the samplers418,618,718, . . . , are samplers and converters from analog form to digital form, a function that is reverse relative to the sampling by associated transmitters404,604, . . . . The addition of the two differential signals by the summer522has the effect of cancelling out the data and leaving in the clock signal that is received by the transceiver512. Whereas, subtraction of the two signals by the subtractor520has the effect of removing the clock signal and leaving in the data signal that is received by the transceiver512.

Traditional techniques employ phase lock loops to lock in the clock signal, which is cumbersome and prove unreliable for applications requiring fast transmission speeds. This is particularly true for wideband applications. Whereas, various embodiments of the invention use common-mode approaches or combine data and clock signals allowing reliable communication in wideband applications. The following equations lend visibility into the outcome achieved by combining clock and data signals.

Referring back toFIG. 4B, the recovered clock, provide by the summer522, is amplified by the amplifier526, as previously noted, and after amplification, provided to the de-skewer528as input. The de-skewer528, much like its counterpart de-skewer428, generates a clock signal adjusted to account for the skew error introduced during transmission through the link508and sampling the received data, at the output of the substractor520, substantially in the middle of each of the data samples. Sampling data at substantially the center thereof helps ensure against errors resulting from sampling at outer edges thereof. That is, the closer to the middle of the data being sampled, the greater the reliability of the received data.

“LineP” and “LineN” are each shown inFIG. 2Aas outputs of the transmitter200. Accordingly, as noted in Eqs. (3) and (4), Vdata and Vclk are each extracted as signals from Vdiff and Vcom, respectively in the far-side receiver.

The de-skewer528, much like its counterpart de-skewer428, under the control of the skew controller516, receives a skew error, generated by the skew error detector524. The skew error detector524detects the skew error and the clock signal is adjusted to align substantially with the center of a data sample, as previously discussed relative to the link400, which applies to all data transmission links show and discussed herein.

FIG. 4Cshows yet another embodiment of a data transmission link, in accordance with various embodiments of the invention. The data transmission link600ofFIG. 4Cis shown to include a transmitter602, analogous to the transmitter100ofFIG. 1, and a transceiver612. As with other embodiments, the data transmission link600is concerned with reconstructing the clock signal generated and transmitted by Clock generator601and data signal generated and transmitted by the transmitter602to the transceiver612as such transmission introduces errors and therefore reduces reliability by exposure to noise through a link traveled by both signals. In the embodiment ofFIG. 4Chowever, the link is made of two physically separate wires or channels, i.e.608aand608b. Channel608acarries data signals, in analog form, while channel608bcarries a clock signal. The transmitter602is analogous to the transmitter300ofFIG. 2B. In this link configuration, the clock generator601does not need to be located inside, or a part of the transceiver600and can instead be a stand-alone clock generator. For example, it can be a part of yet a third chip (or device) that supplies a clock signal to both transceivers600and610.

Accordingly, data and clock signals are received through the two channels608aand608bby the transceiver612. The transceiver612is shown to include a receiver sampler618, a transmitter610, an amplifier626, a de-skewer628, a skew controller616, and a skew error detector624, in accordance with an embodiment of the invention. Because two channels are employed for transmission and data and clock are not combined, as some of the previously-discussed embodiments of the invention, signal from both channels are received independently of one another. Analog data transmitted by the transmitter602, through the channel608a, is received (with noise) by the sampler618and the clock signal transmitted by the clock generator601, through the channel608a, is received by the amplifier626.

The received clock signal is amplified by the amplifier626and provided, amplified, to the de-skewer628. The de-skewer628generates a receiver clock signal that is employed by the sampler618to sample the received data signal, at data samples forming data symbols, much like those discussed hereinabove relative to other embodiments. The sampler618samples or converts the received data to digital form using the clock signal generated by the de-skewer628. This clock signal is adjusted by the de-skewer628, to cause sampling by the sampler618at substantially the middle of each data sample. The skew error detector624generates the skew error used by the control of the skew controller516to adjust the clock skew for sampling using the de-skewer628, as discussed hereinabove relative to other embodiments.

The transceiver612is further shown to include the transmitter610for receiving digital data that is to be transmitted and converting the same to analog data using the receive clock signal generated by the de-skewer628to perform the sampling/conversion. The transmitter can alternatively use the clock signal before the de-skew as well. The output of the transmitter610, i.e. analog data, is ultimately transmitted on one link or channel and its associated clock signal is transmitted on another link or channel, much like how the link608, made of the channels608aand608b, transmits the data and clock. In scenarios where the transceiver612transmits a data signal to another transceiver (e.g. transceiver600) that already receives the clock signal from the clock generator601, there is no need to transmit the clock signal with the data signal from the transmitter610

FIG. 4Dshows a data transmission link700, in accordance with another embodiment of the invention. The link700is analogous to the link400ofFIG. 4Aexcept that the former includes a frequency fractional multiplier (or divider), with a ratio of M/N, in the clock generator701output path and a frequency fractional multiplier (or divider), with a ratio of N/M, in the clock recovery path of the transceiver712. This multiplier, of transceiver712, is referenced, inFIG. 4D, as the divider/multiplier711and serves to divide (or multiply) the received clock signal, post bandpass filtering the signal received through the link708, by some fraction or integer. Accordingly, the multiplied clock signal is substantially at the same frequency as the original clock signal generated by the clock signal generator701and no longer at the same or substantially the same rate as the clock signal embedded in the signal from the link708.

FIG. 4Eshows a data transmission link800, in accordance with another embodiment of the invention. The link800, much like the link500ofFIG. 4Bto which it is analogous, uses differential signals and operates much like the link500except that its transceiver812has an added bandpass filter823positioned between the summer822and the amplifier826. Thus, after the two differential signals, each including data and clock, are transmitted through the link808and combined by the summer822to extract (or recover) the clock signal and eliminate the data signals, the recovered clock is fed through the bandpass filter823to further extract the clock signal and eliminate the data signal. The clock is double-processed during recovery to ensure even better or more accurate clock recovery.

FIG. 4Fshows a data transmission link900, in accordance with another embodiment of the invention. The link900is analogous to the data transmission link ofFIG. 4Cexcept that the clock signal generator901is shown located externally to the transceiver902. Therefore, the channel908bis shown coupling the generator901to the transceiver912directly rather than through the transmitter902. In this case, neither the transceivers on either side of the link include a clock generator and all transceivers can receive their clock from a single clock generator. In another embodiment, a single clock generator is shared among several transceivers in parallel data transmission links on both sides.

FIG. 4Gshows a data transmission link1000, in accordance with another embodiment of the invention. InFIGS. 4G through 4I, data transmission links are shown to include skew controllers and de-skewers in their transmitters. This helps to minimize the complexity of clock de-skewing on one side of the link where circuit complexity and/or power need be limited, such as in an application where a mobile device is located on an opposite end of the link. For example, inFIG. 4G, the transmitter1002is shown to include a de-skewer1040and a skew controller1060that controls the de-skewer1040. The transceiver1012is shown to include a skew error detector1016and a clock extractor105. The sampler1018receives analog signals from the transmitter1002through the link1008. The analog signal being transmitted across the link1008includes a combination of data and clock signals, generated by the summer1006of the transmitter1002. The clock extractor1050, in some embodiments of the invention is analogous to the bandpass filter ofFIG. 4A, the summer ofFIG. 4B, or a combination thereof, as shown inFIG. 4E. In all cases, the clock signal is extracted from the combined clock and data signals received from the link1008and provided to both sampler1018and transmitter1010and in the case of transmission from the transceiver1012, the extracted clock is combined with data before being transmitted out of the transceiver1012, if necessary.

The skew error detector1016, analogous to previously-shown and discussed embodiments herein, generates a clock skew error and transmits it to the skew controller1060of the transceiver1002where, under the latter's control, the skew error is utilized by the de-skewer1040in transceiver1002to adjust the phase of recovered clock signal post extraction in transceiver1012already to be, substantially, in the middle of a data symbol at the input of the receiver sampler1018. In other words, the clock signal, embedded in the signal that arrives at the input of the transceiver1012, is on the most part, already adjusted to sample data samples substantially at the middle of each data sample and only needs to be extracted by the transceiver1012.

It is worthy to note that the coupling/link between the skew error detector1016and the skew controller1060need not operate at fast speeds and can be a rather slow link, thus, reducing costs.

Similarly, inFIG. 4H, the data transmission link1100uses the skew controller1160and de-skewer1140, of the transceiver1102, to adjust the extracted clock signal of the transceiver1112. In this configuration, the skew controller1140, of the transmitter1102receives the skew error from the skew-error detector1116, of the transceiver1112, which is transmitted back to the transceiver1102, through the same link1108. Basically, the skew error, having a very slow rate, is added to the link1108at transceiver1112using a summer1106and after the link in transceiver1102, it is low-pass filtered by very low-bandwidth filter1061before feeding the skew error values to the skew control. The skew control block applies a correction to the de-skew block1140to adjust the skew on the clock from the Clock generator1101. To this end, as in the embodiment ofFIG. 4G, the output of the de-skewer1140, not the output of the clock signal generator1101, serves as input to the summer1106. The summer1106combines an already de-skewed clock signal to the data signal before transmitting the combined data and clock signal through the link1108. The de-skewer1104is coupled between the clock signal generator1101and the summer1106. The summer1106receives analog data from the converter1104.

On the transceiver1112side, while a clock extractor1150exits, it extracts the clock signal not directly from the link1108, as in the embodiment ofFIG. 4G, but rather from a filtered version thereof with the skew error removed. That is, the high pass filter1063is coupled between the summer1122and the clock signal extractor1150and eliminates low-frequency skew error signals therefore only allowing the clock signal and high-speed data signals to pass through. Otherwise, the transceiver1112functions similarly to the transceiver1012. ofFIG. 4G, where the extracted clock is already de-skewed and samples data at substantially the center of the data symbols.

The skew error detector1116measures the skew error between the sampling point of the clock signal and the center of the data symbol, carried on the data signal that is superpositioned onto the clock signal. Therefore, a skew error output is generated by the skew error detector1116accordingly.

The skew error output is updated at a slow rate, as previously discussed relative to prior figures. The rate of change of the skew error output therefore has a very low frequency associated with it.

The skew error output is coupled to the link1108by the summer1122. The skew error output is then removed by filtering, using the high pass filter1163. The filtering is performed to ensure no interference with the high speed data signal and high speed clock signal coupled across the link1108.

Low pass filter1161removes high speed data signals and high speed clock signals transmitted by the transmitter1104and the summer1106and therefore substantially only allows the low speed skew error signal through to the skew controller1141and the adjustable de-skew circuit1140. The skew error signal adjusts for the skew experienced by the clock signal that serves as an input to the summer1106such that by the time the clock signal arrives at the transceiver1112and is extracted, its sampling phase is aligned with the center of the data signal.

FIG. 4Ishows a data transmission link1200, in accordance with another embodiment of the invention. The data transmission link1200is analogous to the data transmission link1100except that the former further includes a series capacitor (or a high-pass filter)1203in its transmitter1202coupled between the de-skewer1240of the transmitter1202and the summer1214of the transceiver1212. The capacitor1203serves as a filter and in this respect, blocks the low-speed skew error signal from the transceiver1212to allow the clock signal to the transceiver1212to be de-skewed by the de-skewer in the transceiver1202before it is sent through the link1208a, to the transceiver1212.

In some embodiments of the invention, the transmitters of the various exemplary data transmission links shown and discussed herein are each formed on a semiconductor (or chip) separate and apart from a semiconductor onto which each transceiver is formed. For example, the transmitter1202may be formed on chip A and the transceiver1212may be formed on chip B. Chips A and B may be on the same device and therefore connected through a wire, such as a smart phone, or rather far apart and communicating through a wireless transmission link. For example, one chip may be a part of a smart phone while the other chip may be a part of the base station with which the smart phone may communicate. In other embodiments, the transmitters and transceivers may each be a device or a combination of a device and a chip. Various configurations are contemplated.

FIGS. 5A-5Ceach show a schematic illustration of an exemplary embodiment of an adjustable de-skew circuit. Each of these embodiments may serve as the adjustable skew circuit of the embodiments of the invention. InFIG. 5A, an adjustable skew circuit1300is shown to include an adjuster circuit1302, a clock circuit1304, and a phase interpolator1314, in accordance with an embodiment of the invention. The adjuster circuit1302is shown to include a phase detector, a charge pump, and a regulator although it is understood that alternative circuitry may be employed. The clock circuit1304is shown to include four clock delay circuits1306-1309, although other number of clock delays may be employed without deviating from the scope and spirit of the invention.

The circuit1300is shown to receive a single-ended recovered clock from, for example, one of the receiver samplers of prior embodiments shown and discussed herein. The single-ended recovered clock is coupled through the clock delay circuits1306-1309, with each serving as a stage. The clock signal, i.e. single-ended recovered clock, is delayed at each of the clock delay circuits, therefore, four delay stages are experienced by the single-ended recovered clock. The delay at each stage is adjusted to be a quarter of a clock cycle and serves as an input to the phase interpolator1314, as shown inFIG. 5A.

The phase interpolator1314generates an output clock with a phase that is approximately between the phases of two selected input clocks, also typically included in a phase interpolator, such as the interpolator1314. The phases of the two clocks are typically adjacent to one another.

The phase of the output clock, such as the output of the circuit1312, is controlled by the input control that adjusts the weights applied to the output of an immediately adjacent clock delay circuit whose output serves as input to the next clock stage. Based on the signal generated by a skew controller, such as those depicted and described herein, applied to the phase interpolator1314, the output clock phase is adjusted.

Each of the clock stages, of the circuits1306-1309, introduces a clock delay or delays the single-ended recovered clock by a quarter of clock period. For example, the single-ended recovered clock is delayed by 90 degrees at the output of the circuit1307and 180 degrees at the output of the circuit1308and 270 degrees at the output of the circuit1309. The circuits1306-1309need not be precise in shifting the clock, in other words, a 90-degree phase shift need not be exact because the skew error adjustment/correction that is done by the feedback correction loop formed of the receiver sampler, the skew error detector, skew control, the adjustable de-skew circuit of the various embodiments of the invention allow for this fairly loose tolerance and correct any small phase discrepancies that may result from a less-than-exact phase shift.

FIG. 5Bshows an adjustable skew circuit1400that is analogous to the adjustable skew circuit1300except that the output of the phase interpolator1414is input to a clock delay circuit1404, similar to each of the circuits1306-1309. This clock delay circuit1404using one or two 90-degree delay stage similar to delay stages in1306-1309generates phase delays that are the 90 degree or 180 degree phase shifted of the output clock (RxClk). Accordingly, an additional output clock (RxCIkQ) is generated and used by the skew error detector of a transceiver, such as the transceivers discussed herein. There is therefore no need for an additional phase interpolator to generate RxCIkQ separately. As can be appreciated, phase interpolators generally consume a large amount of power and consume a large amount of real estate. In applications where there is an adequate timing margin, this delay stage does not need to be very accurately set. Fig. C shows an adjustable skew circuit1500that is analogous to the adjustable skew circuit1400except that input clocks are differential.

In parallel point-to-point data transmission links one clock deskew circuit can be used for multiple data links. A method to find the error free window that is best across all the parallel data links is to sweep the delay settings of the clock deskew block and capture settings for the error free window of each data link. The best clock deskew adjustment across all the parallel links is at the middle deskew setting of the common denominator of error free windows of all links. To avoid the delay mismatches between clock and data over time, the clock and data paths are to be designed to have similar delay variations over PVT (Process, Temperature, Voltage) changes. For sampling clock in receiver (RxClk) to track data signals over time, the deskew error of one of the data links, whose best sampling phase is closest to the middle deskew setting of the common denominator of all links error free windows, can continuously be measured and used to correct the clock skew error. Alternatively, each data link can fine tune its own RxClk phase for tracking and sampling the data symbol at its center by adding switchable capacitor and/or resistors in the RxClk path. By switching in and out capacitors and/or resistor in the RxClk path, the minor clock delay adjustment can be achieved.