Frequency control system with dual-input bias generator to separately receive management and operational controls

Methods and systems to control an output frequency relative to a reference frequency. A frequency control system includes a dual-input bias generator to separately receive management and operational controls. The bias generator includes a first bias generator circuit to generate a bias control based on a difference between the management control and a bias feedback reference during a first mode of operation, a second bias generator circuit to generate the bias control based on a difference between the operational control and the bias feedback reference during a second mode of operation, and a bias feedback reference circuit to generate the bias feedback reference based on the bias control. The first mode may include a characterization and/or a start-up mode. The second mode may include an operational mode, such as a feedback-controlled mode.

BACKGROUND

A phase locked loop (PLL) may include a phase detector, loop filter, VCO, reference input, and frequency divider. After an initial power-on, the PLL may perform a lock acquisition process in to attempt to phase and/or frequency lock a VCO output to the reference input. Lock acquisition may take time due to an indeterminate state of the PLL at power-on.

A PLL may be calibrated or characterized to determine or generate a frequency versus tuning voltage curve for the VCO, which may be used to optimize PLL operation. Characterization may include comparing a range of voltages applied to the bias generator, to corresponding output frequencies of the VCO.

In the drawings, the leftmost digit(s) of a reference number identifies the drawing in which the reference number first appears.

DETAILED DESCRIPTION

FIG. 1is a block diagram of a frequency control system100, including a bias generator110to generate one or more bias controls to control an output frequency, FOUT, relative to a reference frequency FREF114.

In the example ofFIG. 1, system100includes a phase detector102, charge pumps104and106, loop filters108and109, a voltage-controlled oscillator (VCO)112, and a frequency divider228. Frequency control system100may represent a phase locked loop (PLL). For illustrative purposes, frequency control system100is illustrated as a self-biased phase locked loop (SBPLL). Methods and systems disclosed herein are not, however, limited to SBPLLs or PLLs.

Bias generator110is implemented to generate bias controls Nbias126and Pbias124. Nbias126is provided to VCO112and charge pumps104and106. Pbias124is provided to VCO112.

Charge pumps104and106may be implemented to vary corresponding output current drives based on Nbias126.

Phase detector102may be implemented to compare a reference clock, input FREF114, and a feedback clock, input FIN116, and to control or assert an Up control118and/or a Down control120based on a phase difference. Phase detector102may generate a pulse width having a width substantially equal to the phase difference. The pulse may be provided as Up control118when FREF leads FIN, and as Down control120when FREF lags FIN. In the example ofFIG. 1, Up control118and Down control120are provided to charge pumps104and106.

Charge pump104generates and/or regulates an operating control V1122110based on Up control118and Down control120.

Charge pump106generates and/or regulates a control V2123, which may be further regulated as Pbias124by bias generator110, such as illustrated inFIG. 4with a Pbias generator309.

InFIG. 1, loop filters108and109include capacitors C1 and C2, each to filter a corresponding one of V1122and V2123/Pbias124. Loop filter108and109may include low-pass filters. Loop filter108may be implemented to integrate current generated by charge pump104, such as to smooth operational control V1122. Loop filter109may be implemented to integrate current generated by charge pump106, such as to smooth V2123.

Charge pumps104and106and loop filters108and109may define a loop filter circuit180to translate an output of phase detector102into an operational control or control voltage. Loop filter circuit180is not, however, limited to the example ofFIG. 1, as one or more features of loop filter circuit180may be omitted and/or replaced with other components. In an embodiment, one or both of charge pumps104and106, and/or loop filters108and109may be replaced with one or more other loop filter components. For example, one or more of loop filters108and109may be replaced with sample-reset type filters. As another example, charge pump104may be replaced with a sample and hold circuit, a counter, a passive component, and/or combinations thereof. In such embodiments, a control module may assert appropriate control over the loop filter circuit components to implement features disclosed herein.

System100may be implemented to operate in a closed-loop feedback-controlled mode to control and/or minimize phase and/or frequency differences between FREF114and FIN116, such as to lock the frequency and/or phase of FIN116with that of FREF114. A feedback loop may include phase detector102, charge pumps104and106, loop filters108and109, bias generator110, VCO112, and divider128. The closed-loop feedback-controlled mode may also be referred to as a feedback-controlled mode and an operating mode of system100.

Upon power-up of system100, one or more loop signals may have an indeterminate and/or known state that differs from a desired state. In time, and without assistance, bias generator110may converge on bias levels to lock the frequency and/or phase of FREF116with that of FIN116.

Described below are methods and systems to selectively implement a startup mode prior to the feedback controlled mode, such as to reduce the lock or acquisition time after power-on. Also described below are methods and systems to selectively implement a characterization mode, such as to perform a frequency versus tuning voltage (FV) characterization or calibration of VCO112.

A frequency control system as disclosed herein may be configurable to operate in multiple modes. A first mode may include the start-up mode and/or the characterization mode during which bias generator110receives a management control. A second mode may include the feedback-controlled mode during which bias generator110receives a feedback control, illustrated here as operational control V1122.

FIG. 2is a block diagram of a frequency control system200, including frequency control system100ofFIG. 1and a management control module204having a controller206to generate management control CV.

InFIG. 2, bias generator110includes a single input211to receive management control CV during the first mode of operation and operational control V1122during the second mode of operation.

Control module204may further include a switch device, illustrated here as a pass gate PG1, to provide management control CV to input211. Controller206may be implemented to control PG1 to selectively provide management control CV to input211during the first mode of operation. Charge pump104may be disabled during the first mode of operation.

When PG1 is open, system100may operate in the second mode of operation, or feedback-controlled mode, to provide operational control V1122to input211of bias generator110.

Where the first mode includes the FV characterization mode, controller206may increment management control CV through a tuning range of voltages, which may include voltages between zero volts and an operating voltage, Vcc, of system100. Corresponding frequencies and/or phases of FOUT may be monitored and/or recorded to generate FV characteristics, which may be used to calibrate system100and/or another frequency control system.

Where the first mode includes the start-up mode, controller206may set management control CV to a nominal tuning voltage, which may be approximately midway between Vss and Vcc. Thereafter, power may be applied to charge pump104and PG1 may be opened to operate system100in the feedback-controlled mode.

In the feedback-controlled mode, where PG1 is open, a leakage current may flow through PG1, which may offset operational control V1122. Charge pump104may compensate for the offset, but the compensation may result in a static phase error. Excessive leakage may preclude frequency and/or phase locking.

FIG. 3is a block diagram of a frequency control system300, including a bias generator310having a first input311to receive a management control Vlx from a control module304during the first mode of operation, and a second input312to receive operational control V1122during the second mode of operation. In other words, bias generator310is implemented to receive management control Vlx and operational control V1122via separate paths, which may reduce and/or eliminate the current leakage flow described above with reference toFIG. 2.

Bias generator310may be implemented to receive management control Vlx during the first mode of operation and to receive operational control V1122during the second mode of operation, and to control bias control Nbias126during each of the first and second modes to control output frequency FOUT. Management control V1x may include a start-up control and/or a FV characterization control, such as described above.

System300further includes charge pumps104and106, and VCO112, as described above with reference to system100. For ease of illustration, phase detector102and divider108are omitted inFIG. 3.

InFIG. 3, bias generator310includes an Nbias generator308to generate Nbias126based on one of inputs311and312, and a Pbias generator309to control Pbias124based on Nbias126. Bias generator310further includes a capacitor Cnbias connected to an electrical path of Nbias126and to a voltage reference Vss, which may correspond to ground.

FIG. 4is a circuit diagram400of an example implementation of system300.

InFIG. 4, Nbias generator308includes a first bias Nbias generator circuit420, a second bias generator circuit422, and a bias feedback reference circuit424.

First Nbias generator circuit420may be implemented to generate Nbias126based on a difference between management control Vlx and a bias feedback reference Vfbk from bias feedback reference circuit424.

Second Nbias generator420may be implemented to generate Nbias126based on a difference between operational control V1122and bias feedback reference Vfbk.

Bias feedback reference circuit424may be implemented to generate bias feedback reference Vfbk based on Nbias126.

Control module304may be implemented to selectively enable one of first and second Nbias generator circuits420and422with corresponding controls Strt1 and Strt2, to generate Nbias124based on a corresponding one of management control Vlx and operational control V1122.

First bias generator circuit420may include an operational amplifier (OpAmp)421to receive and compare management control Vlx and bias feedback reference Vfbk.

Second bias generator422may include an operational amplifier (OpAmp)423to receive and compare operational control V1 and bias feedback reference Vfbk.

OpAmp421may be implemented or fabricated with a smaller scale process technology (i.e., smaller channel length, smaller channel width, and/or smaller feature size), than OpAmp423. A larger scale process for OpAmp423may help to reduce device noise and offsets during the feedback-controlled mode. Device noise and offsets may be of little or no concern in FV characterization mode and/or start-up mode, and a smaller scale process technology for OpAmp421may help to conserve power and/or area. Example implementations of OpAmps421and423are described further below with reference toFIG. 5.

One or more elements of system300may be controllable to be placed in a reduced power-consumption state. In the example ofFIG. 4, circuit diagram400includes gates N1 and P1, which may be referred to as power gates, to place bias generator310in a reduced power-consumption state. Gate N1 may represent an N-type device to pull-down Nbias126to Vss responsive to a PGn control, to effectively turn-off charge pumps104and106. Gate P1 may represent a P-type device to pull-up V1122to Vcc responsive to a PGp control, which may help to prevent oscillations within bias generator310. Controls PGn and PGp may be generated by control module304.

To enter the FV characterization mode from the reduced power-consumption mode, gate N1 may be opened, gate P1 may remain closed, first bias generator circuit420may be enabled with Strt1, and second bias generator circuit422may be disabled with Strt2. Management control V1x may then be incremented by control module304to cause first bias generator circuit420to generate Nbias126based on management control V1x and Vfbk. Calibration data may be collected as described above.

To transition from the FV characterization mode to the start-up mode, gate P1 may be opened, first bias generator circuit420may be enabled with Strt1, and second bias generator circuit422may be disabled with Strt2.

To enter the start-up mode directly from the reduced power-consumption mode, gates N1 and P1 may be opened, first bias generator circuit420may be enabled with Strt1, and second bias generator circuit422may be disabled with Strt2.

When gate P1 is closed, Vcc may be applied to input312through capacitor C1108. When gate P1 is initially opened, charge within capacitor C1108may hold input312at Vcc. In start-up mode, control module304may be implemented to control charge pump104to cause charge pump104to draw charge from capacitor C1108, which may reduce the voltage at input312.

For example, control module304may be implemented to assert Down control120until operational control V1122on input312reaches a nominal value, referred to herein as a reference startup voltage, Vstrtup. Vstrtup may correspond to a midpoint between Vss and Vcc. Assertion of Down control120may include pulling Down control120to Vss. Assertion of Down control120may cause charge pump104to draw charge from C1108. The nominal value of operational control V1122may drive Nbias126to a relatively low voltage, which may cause charge pump104to draw a relatively high current from C1108, which may discharge capacitor C1 relatively quickly.

To transition from the start-up mode to the feedback-controlled mode, first bias generator circuit420may be disabled with Strt1, and second bias generator circuit422may be enabled with Strt2.

Control module304may be implemented to monitor operational control V1122as capacitor C1 is discharged through charge pump104, and to transition to the feedback-controlled mode when operational control V1122falls to or below a threshold value. Control module304may include, for example, a comparator to receive and compare operational control V1122with reference startup voltage Vstrtup. Control module304may be implemented to transition to the feedback-controlled mode when operational control V1122is equal to or less than Vstrtup.

System300may be implemented and/or controllable to transition between any pair of the reduced power-consumption mode, the FV characterization mode, the start-up mode, and the feedback-controlled mode, and may be implemented to traverse through one or more combinations of the modes. For example, and without limitation, system300may be implemented to sequentially transition from the reduced power-consumption mode, to the FV characterization mode, to the power-up mode, and to feedback-controlled mode. Alternatively, or additionally, system300may be implemented to sequentially transition from the reduced power-consumption mode, to the power-up mode, and to feedback-controlled mode.

FIG. 5is a diagram of a circuit500in which first and second bias generator circuits420and422are integrated in a differential transistor pair configuration.

Circuit500includes a first set of differentially configured p-channel devices P5 and P6, which may represent an example implementation of OpAmp421ofFIG. 4.

Circuit500further includes second set differentially configured p-channel devices P3 and P4, which may represent an example implementation of OpAmp423ofFIG. 4.

The first and second sets of differentially configured devices may share a load circuit and/or a bias circuit. InFIG. 5, a shared bias circuit is illustrated as a p-channel device P11. A shared load circuit is illustrated as n-channel device N2 and N3. Circuit sharing may help to conserve power and area.

InFIG. 5, complementary OpAmp enable and disable controls, stup and stupb, respectively, may represent controls Strt1 and Strt2 inFIG. 4, and may be controlled to selectively enable and disable corresponding first and second bias generator circuits420and422. For example, when stup is low, or logic 0, P3 and P4 turn on to generate Nbias126based on a difference between V1 and Vfbk. When stup is high, or logic 1, the P5 and P6 turn on to generate Nbias126based on a difference between V1x and Vfbk.

Methods and systems disclosed herein may be implemented with respect to one or more of a variety of systems such as described below with reference toFIG. 6. Methods and systems disclosed herein are not, however, limited to the example ofFIG. 6.

FIG. 6is a block diagram of a system600, including a frequency control system602to provide an output frequency as a reference clock to one or more other modules of system600. Frequency control system602may include a bias generator, such as described in one or more examples herein.

System600may further include one or more of a processor604, a communication system606, a user interface system610, and communication infrastructure to communicate amongst processor604, communication system606, and user interface system610. Communication system606may include a wired and/or wireless communication system.

System600or portions thereof may be implemented within one or more integrated circuit dies, and may be implemented as a system-on-a-chip (SoC).

User interface system610may include a monitor or display632to display information from processor604and/or communication system606.

User interface system610may include a human interface device (HID)634to provide user input to processor604and/or communication system606. HID634may include, for example and without limitation, one or more of a key board, a cursor device, a touch-sensitive device, and or a motion and/or image sensor. HID634may include a physical device and/or a virtual device, such as a monitor-displayed or virtual keyboard.

User interface system610may include an audio system636to receive and/or output audible sound.

System600may represent, for example, a computer system, a personal communication device, and/or a television set-top box.

System600may include a housing, and one or more of system602, processor604, communication system606, and user interface system610, or portions thereof may be positioned within the housing. The housing may include, without limitation, a rack-mountable housing, a desk-top housing, a lap-top housing, a notebook housing, a net-book housing, a set-top box housing, a portable housing, and/or other conventional electronic housing and/or future-developed housing. System600may further include a battery, and system600may be portable.

As disclosed herein, a frequency control apparatus may include a bias generator to control an output frequency during each of first and second modes of operation. The bias generator may include a first input to receive a management control during the first mode of operation and a second input to receive an operational control during the second mode of operation.

The bias generator may include a first bias generator circuit, including the first input to receive the management control, to generate a bias control based on a difference between the management control and a bias feedback reference during the first mode of operation. The bias generator may further include a second bias generator circuit, including the second input to receive the operational control, to generate the bias control based on a difference between the operational control and the bias feedback reference during the second mode of operation. The bias generator may further include a bias feedback reference circuit to generate the bias feedback reference based on the bias control.

The first and second bias generator circuits may each include a respective one of first and second operational amplifiers.

The first and second operational amplifiers may be integrated as a differential transistor pair.

The first and second operational amplifiers may be implemented to share a common load circuit and a common bias circuit.

The first and second operational amplifiers may be implemented on an integrated circuit die, and wherein the first operational amplifier is implemented with one or more of smaller channel lengths, smaller channel widths, and smaller feature sizes, than that of the second operational amplifier.

The frequency control apparatus may include a control module to provide the management control.

The control may be implemented to disable the first bias generator circuit, enable the second bias generator circuit, and provide the management control during the first mode, and to enable the first bias generator and disable the second bias generator during the second mode.

The first mode may include a characterization mode, and the control module may be implemented to provide the management control at each of multiple voltage levels to generate calibration data in the characterization mode.

The first mode may include a start-up mode and the second mode may include a feedback-controlled mode. The frequency control apparatus may include a loop filter circuit, which include a charge pump to provide the operational control during the feedback-controlled mode, and to vary a current drive of the charge pump output based on the bias control. The control module may be implemented to provide the management control during the start-up mode to initialize the charge pump output current drive, and to switch the bias generator from the start-up mode to the feedback-controlled mode after the charge pump output current drive is initialized. The control module may be implemented to compare a voltage of the charge pump output to a reference during the start-up mode, and to switch from the start-up mode to the feedback-controlled mode when the voltage of charge pump output is equal to the reference.

The control module may be implemented to configure the frequency control system in a reduced power-consumption mode, transition the frequency control system from the reduced power-consumption mode to the start-up mode, and transition the frequency control system from the start-up mode to the feedback-controlled mode.

The bias generator may correspond to an Nbias generator to generate the bias control as an Nbias control, and the frequency control apparatus may further include a Pbias generator to generate a Pbias control. The frequency control apparatus may further include a voltage controlled oscillator (VCO) to generate the output frequency, and a loop filter circuit to provide the operational control to the bias generator. The Nbias control may be applied to a component of the loop filter circuit and to the Pbias generator. The Pbias control may be provided to the VCO.

As further disclosed herein, a system may include a processor, a communication system to communicate with a network, communication infrastructure to permit communications amongst the processor, the communication system, and a user interface system, and a frequency control apparatus as described in one or more examples above, to provide an output frequency as a reference clock to one or more of the processor, the communication system, and the user interface system.

The processor, the communication system, and the frequency control system may be positioned within a housing.

The communication system may include a wireless communication system.

The processor, the communication system, a battery, and at least a portion of the user interface system may be positioned within the housing.

Methods and systems disclosed herein may be implemented in hardware, software, firmware, and combinations thereof, including discrete and integrated circuit logic, application specific integrated circuit (ASIC) logic, and microcontrollers, and may be implemented as part of a domain-specific integrated circuit package, and/or a combination of integrated circuit packages.

Methods and systems are disclosed herein with the aid of functional building blocks illustrating functions, features, and relationships thereof. At least some of the boundaries of these functional building blocks have been arbitrarily defined herein for the convenience of the description. Alternate boundaries may be defined so long as the specified functions and relationships thereof are appropriately performed.

While various embodiments are disclosed herein, it should be understood that they have been presented by way of example only, and not limitation. It will be apparent to persons skilled in the relevant art that various changes in form and detail may be made therein without departing from the spirit and scope of the methods and systems disclosed herein. Thus, the breadth and scope of the claims should not be limited by any of the examples provided herein.