Semiconductor device and method for fabricating the same

A method for fabricating semiconductor device includes the steps of: forming a first magnetic tunneling junction (MTJ) and a second MTJ on a substrate; forming a first top electrode on the first MTJ and a second top electrode on the second MTJ; forming a passivation layer on the first MTJ and the second MTJ; removing part of the passivation layer so that a top surface of all of the remaining passivation layer is lower than a top surface of the first electrode; and forming a ultra low-k (ULK) dielectric layer on the first MTJ and the second MTJ.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The invention relates to a semiconductor device and method for fabricating the same, and more particularly to a magnetoresistive random access memory (MRAM) and method for fabricating the same.

2. Description of the Prior Art

Magnetoresistance (MR) effect has been known as a kind of effect caused by altering the resistance of a material through variation of outside magnetic field. The physical definition of such effect is defined as a variation in resistance obtained by dividing a difference in resistance under no magnetic interference by the original resistance. Currently, MR effect has been successfully utilized in production of hard disks thereby having important commercial values. Moreover, the characterization of utilizing GMR materials to generate different resistance under different magnetized states could also be used to fabricate MRAM devices, which typically has the advantage of keeping stored data even when the device is not connected to an electrical source.

The aforementioned MR effect has also been used in magnetic field sensor areas including but not limited to for example electronic compass components used in global positioning system (GPS) of cellular phones for providing information regarding moving location to users. Currently, various magnetic field sensor technologies such as anisotropic magnetoresistance (AMR) sensors, GMR sensors, magnetic tunneling junction (MTJ) sensors have been widely developed in the market. Nevertheless, most of these products still pose numerous shortcomings such as high chip area, high cost, high power consumption, limited sensibility, and easily affected by temperature variation and how to come up with an improved device to resolve these issues has become an important task in this field.

SUMMARY OF THE INVENTION

According to an embodiment of the present invention, a method for fabricating semiconductor device includes the steps of: forming a first magnetic tunneling junction (MTJ) and a second MTJ on a substrate; forming a first top electrode on the first MTJ and a second top electrode on the second MTJ; forming a passivation layer on the first MTJ and the second MTJ; removing part of the passivation layer so that a top surface of all of the remaining passivation layer is lower than a top surface of the first electrode; and forming a ultra low-k (ULK) dielectric layer on the first MTJ and the second MTJ.

According to another aspect of the present invention, a semiconductor device includes: a first magnetic tunneling junction (MTJ) and a second MTJ on a substrate; a first top electrode on the first MTJ and a second top electrode on the second MTJ; a passivation layer between the first MTJ and the second MTJ, wherein a top surface of the passivation layer comprises a V-shape; and an ultra low-k (ULK) dielectric layer on the passivation layer and around the first MTJ and the second MTJ.

DETAILED DESCRIPTION

Referring toFIGS. 1-7,FIGS. 1-7illustrate a method for fabricating a semiconductor device, or more specifically a MRAM device according to an embodiment of the present invention. As shown inFIG. 1, a substrate12made of semiconductor material is first provided, in which the semiconductor material could be selected from the group consisting of silicon (Si), germanium (Ge), Si—Ge compounds, silicon carbide (SiC), and gallium arsenide (GaAs), and a MTJ region14and a logic region (not shown) are defined on the substrate12.

Active devices such as metal-oxide semiconductor (MOS) transistors, passive devices, conductive layers, and interlayer dielectric (ILD) layer18could also be formed on top of the substrate12. More specifically, planar MOS transistors or non-planar (such as FinFETs) MOS transistors could be formed on the substrate12, in which the MOS transistors could include transistor elements such as gate structures (for example metal gates) and source/drain region, spacer, epitaxial layer, and contact etch stop layer (CESL). The ILD layer18could be formed on the substrate12to cover the MOS transistors, and a plurality of contact plugs could be formed in the ILD layer18to electrically connect to the gate structure and/or source/drain region of MOS transistors. Since the fabrication of planar or non-planar transistors and ILD layer is well known to those skilled in the art, the details of which are not explained herein for the sake of brevity.

Next, metal interconnect structures20,22are sequentially formed on the ILD layer18on the MTJ region14and the edge region16to electrically connect the aforementioned contact plugs, in which the metal interconnect structure20includes an inter-metal dielectric (IMD) layer24and metal interconnections26embedded in the IMD layer24, and the metal interconnect structure22includes a stop layer28, an IMD layer30, and metal interconnections32embedded in the stop layer28and the IMD layer30.

In this embodiment, each of the metal interconnections26from the metal interconnect structure20preferably includes a trench conductor and each of the metal interconnections32from the metal interconnect structure22on the MTJ region14includes a via conductor. Preferably, each of the metal interconnections26,32from the metal interconnect structures20,22could be embedded within the IMD layers24,30and/or stop layer28according to a single damascene process or dual damascene process. For instance, each of the metal interconnections26,32could further includes a barrier layer34and a metal layer36, in which the barrier layer34could be selected from the group consisting of titanium (Ti), titanium nitride (TiN), tantalum (Ta), and tantalum nitride (TaN) and the metal layer36could be selected from the group consisting of tungsten (W), copper (Cu), aluminum (Al), titanium aluminide (TiAl), and cobalt tungsten phosphide (CoWP). Since single damascene process and dual damascene process are well known to those skilled in the art, the details of which are not explained herein for the sake of brevity. In this embodiment, the metal layers36are preferably made of copper, the IMD layers24,30are preferably made of silicon oxide, and the stop layers28is preferably made of nitrogen doped carbide (NDC), silicon nitride, silicon carbon nitride (SiCN), or combination thereof.

Next, a MTJ stack38or stack structure is formed on the metal interconnect structure22, a cap layer40is formed on the MTJ stack38, and another cap layer42formed on the cap layer40. In this embodiment, the formation of the MTJ stack38could be accomplished by sequentially depositing a first electrode layer44, a fixed layer46, a barrier layer48, a free layer50, and a second electrode layer52on the IMD layer30. In this embodiment, the first electrode layer44and the second electrode layer52are preferably made of conductive material including but not limited to for example Ti, Ta, Pt, Cu, Au, Al, or combination thereof, in which the second electrode layer52further includes an electrode layer70made of Ta and an electrode layer74made of Ti. The fixed layer46could be made of antiferromagnetic (AFM) material including but not limited to for example ferromanganese (FeMn), platinum manganese (PtMn), iridium manganese (IrMn), nickel oxide (NiO), or combination thereof, in which the fixed layer46is formed to fix or limit the direction of magnetic moment of adjacent layers. The barrier layer48could be made of insulating material including but not limited to for example oxides such as aluminum oxide (AlOx) or magnesium oxide (MgO). The free layer50could be made of ferromagnetic material including but not limited to for example iron, cobalt, nickel, or alloys thereof such as cobalt-iron-boron (CoFeB), in which the magnetized direction of the free layer50could be altered freely depending on the influence of outside magnetic field. Preferably, the cap layer40and cap layer42are made of different materials. For instance, the cap layer40is preferably made of silicon nitride and the cap layer42is made of silicon oxide, but not limited thereto.

Next, a patterned mask54is formed on the cap layer42. In this embodiment, the patterned mask54could include an organic dielectric layer (ODL)56, a silicon-containing hard mask bottom anti-reflective coating (SHB)58, and a patterned resist60.

Next, as shown inFIG. 2, one or more etching process is conducted by using the patterned mask54as mask to remove part of the cap layers40,42, part of the MTJ stack38, and part of the IMD layer30to form MTJ62and MTJ72on the MTJ region14, in which the first electrode layer44at this stage preferably becomes a bottom electrode76for the MTJs62,72while the second electrode layer52becomes a top electrode78for the MTJs62,72and the cap layers40,42could be removed during the etching process. It should be noted that this embodiment preferably conducts a reactive ion etching (RIE) process by using the patterned mask54as mask to remove part of the cap layers40,42and part of the MTJ stack38, strips the patterned mask54, and then conducts an ion beam etching (IBE) process by using the patterned cap layer42as mask to remove part of the MTJ stack38and part of the IMD layer30to form MTJs62,72. Due to the characteristics of the IBE process, the top surface of the remaining IMD layer30is slightly lower than the top surface of the metal interconnections32after the IBE process and the top surface of the IMD layer30also reveals a curve or an arc.

It should also be noted that when the IBE process is conducted to remove part of the IMD layer30, part of the metal interconnections32are removed at the same time so that a first slanted sidewall64and a second slanted sidewall66are formed on the metal interconnections32adjacent to the MTJ62, in which each of the first slanted sidewall64and the second slanted sidewall66could further include a curve (or curved surface) or a planar surface.

Next, as shown inFIG. 3, a cap layer68is formed on the MTJ62,72to cover the surface of the IMD layer30. In this embodiment, the cap layer68is preferably made of silicon nitride, but could also be made of other dielectric material including but not limited to for example silicon oxide, silicon oxynitride, or silicon carbon nitride.

Next, as shown inFIG. 4, an etching process is conducted to remove part of the cap layer68to form spacers80,82adjacent to the MTJ62and spacer84,86adjacent to the MTJ72, in which the spacers80,82,84,86are disposed on the sidewalls of the MTJs62,72and at the same time covering and contacting the first slanted sidewalls64and second slanted sidewalls66of the metal interconnections32directly.

Next, as shown inFIG. 5, an atomic layer deposition (ALD) process is conducted to form a passivation layer88on the surface of the IMD layer30to cover the MTJs62,72completely while the top surface of the passivation layer88is higher than the top surface of the MTJs62,72. It should be noted that at this stage the top surface of the passivation layer88directly on top of the MTJs62,72preferably forms one or more surface concave downward while the top surface of the passivation layer88between the MTJs62,72forms a surface concave upward and a recess90is formed between the MTJs62,72, in which the angle included by the recess90is preferably greater than 90 degrees or most preferably at 97 degrees.

Next, as shown inFIG. 6, an etching back process is conducted to remove part of the passivation layer88so that the top surface of all of the remaining passivation layer88is less than the top surface of the top electrode78. Specifically, all of the passivation layer88adjacent to the spacers80,86are removed at the stage so that all of the remaining passivation layer88is between the spacers82,84, in which the top surface of the remaining passivation layer88between the MTJs62,72includes a V-shape, all of the V-shape is lower than the top surface of the top electrode78, and the angle included by the V-shape is preferably greater than 100 degrees.

Next, as shown inFIG. 7, an ultra low-k (ULK) dielectric layer92is formed on the passivation layer88, a planarizing process such as a chemical mechanical polishing (CMP) process is conducted to remove part of the ULK dielectric layer92, and a metal interconnective process is conducted to form IMD layers (not shown) and metal interconnections (not shown) embedded within the IMD layers for electrically connecting the MTJs62,72. Since the formation of IMD layers and metal interconnections electrically connecting the MTJs62,72, are well known to those skilled in the art, the details of which are not explained herein for the sake of brevity. This completes the fabrication of a MRAM device according to an embodiment of the present invention.

Referring again toFIG. 7,FIG. 7further illustrates a structural view of a semiconductor device according to an embodiment of the present invention. As shown inFIG. 7, the semiconductor device preferably includes an IMD layer30disposed on the substrate12, metal interconnections32disposed within the IMD layer30, MTJs62,72disposed on the metal interconnections32, bottom electrodes76disposed between the MTJs62,72and metal interconnections32, top electrodes78disposed on the MTJs62,72, spacers80,82disposed adjacent to two sides of the MTJ62, spacers84,86disposed adjacent to two sides of the MTJ72, a passivation layer88disposed between the MTJs62,72, and a ULK dielectric layer92disposed on the passivation layer88and surrounding the MTJs62,72.

Viewing from a more detailed perspective, the top surface of the passivation layer88includes V-shape, all of the V-shape is lower than the top surface of the top electrodes78, and the angle included by the V-shape is greater than 100 degrees. The passivation layer88preferably contacts the spacers82,84directly, the passivation layer88between the spacers82,84contacts the IMD layer30directly, and the ULK dielectric layer92contacts the top electrodes78directly. The passivation layer88and the ULK dielectric layer92are preferably made of different materials, in which the passivation layer88preferably includes silicon oxide but could also include other dielectric material including but not limited to for example tetraethyl orthosilicate (TEOS), silicon nitride, or combination thereof while the ULK dielectric layer92could include porous dielectric materials including but not limited to for example silicon oxycarbide (SiOC).

Referring toFIGS. 8-10,FIGS. 8-10illustrate a method for fabricating a MRAM device according to an embodiment of the present invention. As shown inFIG. 8, it would be desirable to first conduct the aforementioned process fromFIGS. 1-3to form a cap layer68on the MTJs62,72to cover the surface of the IMD layer30, omit the etching process conducted to remove part of the cap layer68for forming spacers80,82,84,86adjacent to the MTJs62,72inFIG. 4, follow the processes conducted inFIGS. 5-6to conduct an ALD process to form a passivation layer88covering the MTJs62,72completely, and then conduct an etching back process to remove part of the passivation layer88so that the top surface of all of the remaining passivation layer88is lower than the top surface of the top electrodes78. Similar toFIG. 6, the passivation layer88on left side of MTJ62and right side of MTJ72are removed at this stage so that all of the remaining passivation layer88is between the MTJs62,72, in which the top surface of the remaining passivation layer88between the MTJs62,72includes a V-shape, all of the V-shape is lower than the top surface of the top electrode78, and the angle included by the V-shape is preferably greater than 100 degrees.

Next, as shown inFIG. 9, a photo-etching process is conducted to remove all of the cap layer68outside the MTJ region14, including all of the cap layer68on left side of MTJ62and right side of MTJ72so that the remaining cap layer68is still disposed on the top surface of the MTJs62,72, sidewalls of the MTJs62,72, and the surface of the IMD layer30between the MTJs62,72. It should be noted that since the cap layer68between the MTJs62,72is untouched throughout the process, after the cap layer68outside the MTJ region14is removed by the aforementioned etching process the remaining cap layer68is still disposed between the passivation layer88and the IMD layer30.

Next, as shown inFIG. 10, a ULK dielectric layer92is formed on the passivation layer88, a planarizing process such as a chemical mechanical polishing (CMP) process is conducted to remove part of the ULK dielectric layer92, and a metal interconnective process is conducted to form one or more IMD layers (not shown) and metal interconnections (not shown) embedded within the IMD layers for electrically connecting the MTJs62,72. Since the formation of IMD layers and metal interconnections electrically connecting the MTJs62,72, are well known to those skilled in the art, the details of which are not explained herein for the sake of brevity. This completes the fabrication of a MRAM device according to an embodiment of the present invention.