Level shifter circuit

Techniques are disclosed for a level shifter configured to adjust current flow in response to measured current fluctuations due to common mode noise in the level shifter. For example, the level shifter includes a low-side control circuit configured to adjust a first current flowing into a first low-side terminal of an active high voltage level shifter device in response to a difference between the first low-side current and a second low-side current flowing into a second low-side terminal of an inactive high voltage level shifter device. The level shifter further includes a high-side receiver circuit configured to detect a difference between a first high-side current flowing into a first high-side terminal of the active high voltage level shifter device and a second high-side current flowing into a second high-side terminal of the inactive high voltage level shifter device.

TECHNICAL FIELD

This disclosure generally relates to techniques for increasing the stability of high voltage level shifter circuits.

BACKGROUND

A level shifter is an electrical component that converts digital signals from a low-side voltage domain to into a high-side voltage domain. The input signals are connected to a ground in the low-side domain, while the output signals are connected to a ground in the high-side domain. Both the low-side ground and high-side ground are separate and electrically isolated from each other.

One type of level shifter is an Ultra-high Voltage (UHV) level shifter. UHV level shifters operate to convert a control signal from a low-side control circuit into a driver signal for a high-side gate driver of a half bridge circuit. A low-side control circuit generates the control signal and further drives a low-side switch of the half-bridge circuit. Therefore, the negative supply of the low-side domain is connected to the negative supply of the half-bridge. UHV level shifters typically are used in LLC converters or motor drives and have a half bridge supply voltage of approximately 400 V. In other words, the voltage difference between the high-side domain and low-side domain oscillates from 0 V to 400 V and back.

SUMMARY

In general, the disclosure describes techniques for a level shifter configured to adjust current flow in response to measured current fluctuations due to common mode noise in the level shifter. For example, the level shifter includes a low-side control circuit configured to adjust a first current flowing into a first low-side terminal of an active high voltage level shifter device in response to a difference between the first current and a second current flowing into a second low-side terminal of an inactive high voltage level shifter device. The level shifter further includes a high-side receiver circuit configured detect a difference between a first output current flowing from a first high-side terminal of the active high voltage level shifter device driven in an active state and a second output current flowing from a second high-side terminal of the inactive high voltage level shifter device.

In one example, this disclosure describes a high voltage level shifter configured to translate an input signal from a low-side low voltage domain to a high-side low voltage domain, the high voltage level shifter including: a first high voltage level shifter device, wherein the first high voltage level shifter device includes a first high-side terminal, a first low-side terminal, and a first control terminal, and wherein the first control terminal is configured to control a first current flowing into the first high-side terminal to the first low-side terminal; a second high voltage level shifter device, wherein the second high voltage level shifter device includes a second high-side terminal, a second low-side terminal, and a second control terminal, and wherein the second control terminal is configured to control a second current flowing into the second high-side terminal to the second low-side terminal; a low-side control circuit configured to drive the first control terminal and the second control terminal, wherein the low-side control circuit is further configured to drive, in response to the input signal, one of the first high voltage level shifter device and the second high voltage level shifter device to an active state while the other of the first high voltage level shifter device and the second high voltage level shifter device remains in an inactive state; a high-side receiver circuit configured to set a state of a high-side output signal in response to the one of the first high voltage level shifter device and the second high voltage level shifter device driven in the active state; wherein the high-side receiver circuit is configured to monitor a first difference between the first current flowing into the first high-side terminal of the first high voltage level shifter device and the second current flowing into the second high-side terminal of the second high voltage level shifter device; and wherein the low-side control circuit is configured to control a concomitant control terminal of the first control terminal and the second control terminal corresponding to the one of the first high voltage level shifter device and the second high voltage level shifter device driven in the active state in response to a second difference between the first current and the second current monitored flowing out of the first low-side terminal and the second low-side terminal.

In another example, this disclosure describes a method including: receiving, via a low-side control circuit of a high voltage level shifter, an input signal from a low-side low voltage domain; driving, by the low-side control circuit and in response to the received input signal, one of a first high voltage level shifter device and a second high voltage level shifter device to an active state while the other of the first high voltage level shifter device and the second high voltage level shifter device remains in an inactive state, wherein the first high voltage level shifter device includes a first high-side terminal, a first low-side terminal, and a first control terminal, wherein the first control terminal is configured to control a first current flowing into the first high-side terminal to the first low-side terminal, wherein the second high voltage level shifter device includes a second high-side terminal, a second low-side terminal, and a second control terminal, and wherein the second control terminal is configured to control a second current flowing into the second high-side terminal to the second low-side terminal; setting, by a high-side receiver circuit, a state of a high-side output signal in response to a monitored first difference between the first current flowing into the first high-side terminal of the first high voltage level shifter device and the second current flowing into the second high-side terminal of the second high voltage level shifter device; and controlling, by the low-side control circuit and in response to a second difference between the first current monitored flowing out of the first low side terminal and the second current monitored flowing out of the second low side terminal, a concomitant control terminal of the first control terminal and the second control terminal corresponding to the one of the first high voltage level shifter device and the second high voltage level shifter device driven in the active state.

In another example, this disclosure describes a high voltage level shifter configured to translate an input signal from a low-side low voltage domain to a high-side low voltage domain, the high voltage level shifter including: a first high voltage level shifter device, wherein the first high voltage level shifter device includes a first high-side terminal, a first low-side terminal, and a first control terminal, and wherein the first control terminal is configured to control a first current flowing into the first high-side terminal to the first low-side terminal; a second high voltage level shifter device, wherein the second high voltage level shifter device includes a second high-side terminal, a second low-side terminal, and a second control terminal, and wherein the second control terminal is configured to control a second current flowing into the second high-side terminal to the second low-side terminal; means for low-side control, wherein the means for low-side control is configured to drive the first control terminal and the second control terminal, wherein the means for low-side control is further configured to drive, in response to the input signal, one of the first high voltage level shifter device and the second high voltage level shifter device to an active state while the other of the first high voltage level shifter device and the second high voltage level shifter device remains in an inactive state; means for high-side receiving, wherein the means for high-side receiving is configured to set a state of a high-side output signal in response to the one of the first high voltage level shifter device and the second high voltage level shifter device driven in the active state; wherein the means for high-side receiving is configured to monitor a first difference between the first current flowing into the first high-side terminal of the first high voltage level shifter device and the second current flowing into the second high-side terminal of the second high voltage level shifter device; and wherein the means for low-side control is configured to control a concomitant control terminal of the first control terminal and the second control terminal corresponding to the one of the first high voltage level shifter device and the second high voltage level shifter device driven in the active state in response to a second difference between the first current monitored flowing out of the first low side terminal and the second current monitored flowing out of the second low side terminal.

DETAILED DESCRIPTION

Techniques and circuit designs are disclosed for a high voltage level shifter that is configured to adjust current flow in response to measured current fluctuations due to common mode noise in the level shifter. For example, the level shifter may include a low-side control circuit configured to adjust a first current flowing into a first low-side terminal of an active high voltage level shifter device in response to a difference between the first current and a second current flowing into a second low-side terminal of an inactive high voltage level shifter device. The level shifter may further include a high-side receiver circuit configured detect a difference between a first output current flowing from a first high-side terminal of the active high voltage level shifter device driven in an active state and a second output current flowing from a second high-side terminal of the inactive high voltage level shifter device.

Typically, an electrical company provides mains voltage as an alternating current (AC) at a high voltage. A power converter within a consumer application is used to convert the supply into a lower voltage direct current (DC) before it is suitable for household or business use. In some examples, the mains voltage is a nominal supply voltage of 100-240 Volts (V) AC at 50-60 Hertz (Hz). In some examples, the power converter includes a power factor correction (PFC) circuit performs power factor correction on the nominal supply voltage and converts the nominal supply voltage to approximately 400 V direct current (DC). The power converter further includes an LLC resonant half-bridge converter circuit that converts the 400 VDC to approximately 400 VAC at 100-200 KHz. This, in turn, is passed through a transformer in the power converter to step down the supply to approximately 10-20 VAC. Finally, the 10-20 VAC is passed through a rectifier circuit in the power converter to convert the supply to a suitable low-level DC voltage for the end application. For example, the low-level DC voltage may be between 5-20 VDC, as is used by various components in consumer television applications.

The LLC resonant half-bridge converter circuit converts DC power into AC power. As illustrated by the example ofFIG. 1, the LLC resonant half-bridge converter circuit operates by using a driver to switch two power transistors connected in series between the DC input voltage and ground on and off in opposing phase, such that each transistor is active for half of the duty cycle, and only while the other transistor is inactive. In response to commands from the driver circuit, the transistors generate a square wave at their output. One or more LLC tanks connected to the midpoint of the transistors undergo excitation in response to the square wave to create an AC sinusoidal output.

The LLC resonant half-bridge converter circuit typically provides a small dead-time between the turn-off of each transistor and the turn-on of the complementary transistor. The role of this dead-time ensures that each transistor does not cross-conduct, which, in high voltage applications, may damage the circuit.

Typically, a level shifter is used to implement the driver circuit of the LLC resonant half-bridge converter circuit. A level shifter functions to transfer input signals in one voltage domain into output signals in a different voltage domain. The input signals are connected to a ground in the low-side domain, while the output signals are connected to a ground in the high-side domain. Both the low-side ground and high-side ground are separate and electrically isolated from each other. For example, a level shifter may be used to convert control signals in a TTL voltage level (i.e., 3-5 VDC) to driver signals in a higher voltage domain, such as 10 VDC.

In ultra-high voltage applications, the voltage difference between the low voltage domain and the high voltage domain may be hundreds of Volts, and other level shifters may not provide suitable isolation between the domains. Isolation between the domains is important because the ground of the high-side domain is connected to the midpoint of the half-bridge. During normal operation of the level shifter, the midpoint of the half-bridge commutates between 0 V and 400 V at a slew rate of up to 10 V/nanosecond (ns). Further, because the slew rate, or change in voltage at the midpoint of the transistors, can be in the order of 10V/nanosecond (ns), other level shifters may generate improper switching commands in response to these large changes in voltage. In some situations, rapid changes in common-mode voltage across the transistors may prevent a turn-off command from other level shifters from reaching a transistor. This may result in a shoot-through condition where both transistors are turned on, shorting the high voltage rail to ground. This may result in near-instantaneous destruction of the circuit. Furthermore, other types of common mode noise, such as ringing and electromagnetic interference (EMI) may prevent commands from other level shifters from reaching a transistor.

One approach to this problem involves coreless transformer technology, which transfers switching commands from a control circuit to a high side gate driver through an integrated planar microtransformer. However, this approach requires two separate chips isolated from each other, which leads to relatively high assembly cost.

According to the techniques of the disclosure, an ultra-high voltage level shifter is described which is more resistant to common-mode changes in voltage and noise than other level shifters. In one example, the level shifter includes a low-side control circuit configured to adjust a first current flowing into a first low-side terminal of an active high voltage level shifter device in response to a difference between the first current and a second current flowing into a second low-side terminal of an inactive high voltage level shifter device. The level shifter further includes a high-side receiver circuit configured detect a difference between a first output current flowing from a first high-side terminal of the active high voltage level shifter device driven in an active state and a second output current flowing from a second high-side terminal of the inactive high voltage level shifter device. Furthermore, the ultra-high voltage level shifter described herein may be implemented on a single monolithic integrated chip, which reduces both the production cost and package size of an ultra-high voltage level shifter.

FIG. 2is a block diagram illustrating an example high voltage level shifter100configured to adjust a low-side current112or114of an active high voltage level shifter device102according to the techniques of the disclosure. In this example, high voltage level shifter100includes two high voltage level shifter devices102A-102B (“collectively, high voltage level shifter devices102”) for converting voltage signals in low-side domain101A to voltage signals in high-side domain101B. A low-side control circuit104receives a low-side voltage domain input signal103, which causes low-side control circuit104to drive one of high voltage level shifter devices102into an active state while driving the other of high voltage level shifter devices102into an inactive state. A high-side receiver circuit106receives high-side currents114A-114B from high voltage level shifter devices102, causing high-side receiver circuit106to output a signal116for setting a high-side latch118for defining the state of the high-side gate driver.

High voltage level shifter devices102include low-side terminals120A-120B, each of which receives low-side currents112A-112B, respectively, from low-side power supply119A. High voltage level shifter devices102further include control terminals121A-121B for receiving control signals115A-115B from low-side control circuit104. High voltage level shifter devices102further include high-side terminals122A-122B for transmitting a high-side output current114. In some examples, high voltage level shifter devices102include one or more power transistors. In another example, high voltage level shifter devices102include one of a lateral N-channel MOSFET or a cascode of a high voltage JFET, as well as a low voltage N-channel transistor. In response to a monitored difference between currents112A-112B (collectively, “low-side currents112”), low-side control circuit104adjusts a control signal115A,115B of the high voltage level shifter device102operating in the active state.

Low-side control circuit104receives a low-side voltage domain input signal103. In response to input signal103, low-side control circuit104generates control signals115A-115B, which activate one of high voltage level shifter devices102, while the other of high voltage level shifter devices102remains inactive.

High-side receiver circuit106receives high-side current signals114A-114B from high-side terminals122of high voltage level shifter devices102. In response to high-side current signals114A-114B, high-side receiver circuit106generates an output signal116which sets the state of high-side latch118. High-side latch118sets an output130of the level shifter circuit as a high-side voltage domain101B equivalent to the state of input signal103of low-side voltage domain101A. Output130controls operation of high side switch Q1ofFIG. 1.

According to the techniques of this disclosure, while one of high voltage level shifter devices102is active, low-side control circuit104monitors the low-side current112of the inactive high voltage level shifter device102. As an example, low-side control circuit104drives high voltage level shifter device102A into the active state and high voltage level shifter device102B into the inactive state. Because high voltage level shifter device102A is active, low-side current112A is predicted to reach a target value. Further, because high voltage level shifter device102B is inactive, low-side current112B is expected to be approximately zero. Thus, the difference between low-side currents112A and112B is expected to be substantially the same as the predicted value of low-side current112A while high voltage level shifter device102A is active. Low-side control circuit104receives a signal from differential amplifier108indicative of the measured difference between low-side currents112A and112B. Due to fabrication tolerances, temperature dependency, and voltage dependency, low-side current112A is unlikely to match the target value immediately after activation. By measuring the low-side current112A via differential amplifier108and comparing it to the target value, low-side control circuit104adjusts control signal115A until the low-side current112A matches the target value.

In the presence of disturbances like noise, common mode voltage change, ringing or EMI, the low-side current112A does not accurately indicate the current flowing through level shifter device102A. Therefore, in other devices, the low-side control circuit104, by monitoring only the low-side current112A, may adjust control signal115A to cause an incorrect level of current to flow through the level shifter device102A. The techniques of the disclosure assume that the effect of disturbances such as noise, common mode voltage change, ringing, EMI, and the like is the same on both high voltage level shifter devices102A and102B. Therefore, in the presence of such disturbances, the low-side control circuit104monitors the difference between low-side currents112A and112B and adjusts the control signal115A until the difference between low-side currents112A and112B matches a target value. In doing so, the current flowing through level shifter device102A is regulated to the target value, even in the presence of such disturbances.

Furthermore, without the presence of these disturbances, the high-side current114A is assumed to be equal to the low-side current112A, while high-side current114B is assumed to be equal to low-side current112B. The presence of these disturbances causes high-side current114A to differ from low-side current112A and high-side current114B to differ from low-side current112B. The techniques of the disclosure assume that the difference of high-side current114A and low-side current112A on the active device102A is the same as the difference of high-side current114B and low-side current112B on the inactive device102B. Therefore, by measuring the difference of low-side current112A and low-side current112B via differential amplifier108, and by using control signal115A to adjust the difference between low-side current112A and low-side current112B to a target value via low-side control circuit104, the difference between high-side current114A and high-side current114B may be controlled to match the target value, even in the presence of these disturbances. Finally, by monitoring the difference between high-side current114A and high-side current114B, high-side receiver circuit106may receive a signal undisturbed by noise, common mode voltage change, ringing, EMI, and the like.

Thus, a high voltage level shifter as described herein is expected to transmit signals that are insensitive to disturbances or noise in the circuit. This noise, if left unchecked, may induce false switching commands in high voltage level shifter devices102and high-side latch118, or prevent switching commands from reaching high voltage level shifter device102or high-side latch118altogether. Accordingly, the high voltage level shifter as described herein may prevent damage to the half bridge due to noise due to common-mode voltage change, ringing, or EMI. Furthermore, the high voltage level shifter as described herein may continue to transfer control signals, even during large common mode voltage changes in the high-side circuit, without losing command signals. Thus, the high voltage level shifter100described herein may be more robust against higher levels of noise and common-mode voltage change than other level shifters.

The architecture of high voltage level shifter100illustrated inFIG. 2is shown as an example. The techniques as set forth in this disclosure may be implemented in the example high voltage level shifter100ofFIG. 2, as well as other types of high voltage level shifters not described specifically herein. Nothing in this disclosure should be construed so as to limit the techniques of this disclosure to the example architecture illustrated byFIG. 2.

FIG. 3is a circuit diagram illustrating in further detail an example low-side control circuit104and high-side receiver circuit106of the example high voltage level shifter100ofFIG. 2according to the techniques of the disclosure. In the example ofFIG. 3, a low-side control circuit104senses, via differential amplifier108, the difference between low-side current112A and low-side current112B. In response to the differential signal generated by differential amplifier108, low-side control circuit104provides control signal115A to adjust the difference between low-side current112A and low-side current112B to a target value. In doing so, low-side control circuit104controls the difference between high-side current114A and high-side current114B so as to match a target difference. Furthermore, a differential amplifier208of high-side receiver circuit106monitors a difference between high-side currents114A of active transistor202A and124B of inactive transistor202B. High-side receiver circuit106generates an output signal indicative of this difference which sets the state of high-side latch118(not depicted).

In some examples, transistors202A-202B (collectively, “transistors202”) are ultra-high voltage power transistors. In some examples, transistors202are capable of performing under voltages greater than 600 V. In some examples, transistors202are vertical bi-polar junction transistors (BJTs). In other examples, transistors202are vertical metal-oxide-semiconductor field effect transistors (MOSFETs). In some examples, transistors202are source-down or source-up transistors. In some examples, transistors202are lateral MOSFETs. In some examples, transistors202are lateral n-type channel MOSFETs built on a p-type substrate. In some examples, transistors202are lateral n-type channel MOSETs built on Silicon-on-Insulator (SOI) substrate. In some examples, transistors202are a cascode of an n-type channel junction-gate field effect transistor (JFET) in series with a low-voltage MOSFET. In some examples, transistors202are superjunction MOSFETs. In some examples, transistors202have high switching speed and low gate charge. In some examples, transistors202have low capacitance from drain to source and from drain to substrate.

In this way, high-side receiver circuit106may reduce or eliminate current flowing through the inactive MOSFET102B due to noise or common-mode voltage change. This noise, if left unchecked, may induce false switching commands in high-side latch118, or prevent switching commands from reaching high-side latch118altogether. Accordingly, high-side receiver circuit106may prevent damage to high voltage level shifter100due to noise due to common-mode voltage change, ringing, EMI. Furthermore, high-side receiver circuit106may continue to transfer signals, even during large common mode voltage changes in the high-side circuit, without losing command signals. Thus, the high voltage level shifter100described herein may be more robust against higher levels of noise and common-mode voltage change than other level shifters.

The architecture of high-side receiver circuit106illustrated inFIG. 3is shown as an example only. The techniques as set forth in this disclosure may be implemented in the example high-side receiver circuit106ofFIG. 3, as well as other types of high-side receiver circuits not described specifically herein. Nothing in this disclosure should be construed so as to limit the techniques of this disclosure to the example architecture illustrated byFIG. 3.

FIG. 4is a circuit diagram illustrating further details of an example high voltage level shifter according to the techniques of the disclosure. According to the techniques of the disclosure, in response to a monitored difference between currents112A-112B flowing through transistors302A-302B (collectively, “transistors302”), low-side control circuit104adjusts the current112A flowing through transistor302A operating in the active state. Further, high-side receiver circuit106monitors a difference between currents114A-114B and provides the difference as an output for setting a high-side latch118(not depicted) for defining the state of the high-side gate driver.

According to the techniques of the invention, while one of transistors302is active, low-side control circuit104monitors the low-side current112flowing through the inactive one of the transistors302.

As an example, low-side control circuit104drives transistor302A into the active state and transistor302B into the inactive state. Because transistor302A is active, low-side current112A is predicted to reach a target value. Further, because transistor302B is inactive, low-side current112B is expected to be approximately zero. Thus, the difference between low-side currents112A and112B is expected to be substantially the same as the predicted value of low-side current112A while high voltage level shifter device102A is active. Due to fabrication tolerances, temperature dependency, and voltage dependency, low-side current112A is unlikely to match the target value immediately after activation. By measuring the low-side current112A via differential amplifier108and comparing it to the target value, low-side control circuit104adjusts control signal115A until the low-side current112A matches the target value.

In the presence of disturbances like noise, common mode voltage change, ringing or EMI, the low-side current112A does not accurately indicate the current flowing through level shifter device102A. Therefore, in other devices, the low-side control circuit104, by monitoring only the low-side current112A, may adjust control signal115A to cause an incorrect level of current to flow through the level shifter device102A. The techniques of the disclosure assume that the effect of disturbances such as noise, common mode voltage change, ringing, EMI, and the like is the same on both high voltage level shifter devices102A and102B. Therefore, in the presence of such disturbances, the low-side control circuit104monitors the difference between low-side currents112A and112B and adjusts the control signal115A until the difference between low-side currents112A and112B matches a target value. In doing so, the current flowing through level shifter device102A is regulated to the target value, even in the presence of such disturbances.

Furthermore, without the presence of these disturbances, the high-side current114A is assumed to be equal to the low-side current112A, while high-side current114B is assumed to be equal to low-side current112B. The presence of these disturbances causes high-side current114A to differ from low-side current112A and high-side current114B to differ from low-side current112B. The difference of high-side current114A and low-side current112A on the active device102A is assumed to be the same as the difference of high-side current114B and low-side current112B on the inactive device102B. Therefore, by measuring the difference of low-side current112A and low-side current112B via differential amplifier108, and by using control signal115A to adjust the difference between low-side current112A and low-side current112B to a target value via low-side control circuit104, the difference between high-side current114A and high-side current114B may be controlled to match the target value, even in the presence of these disturbances. Finally, by monitoring the difference between high-side current114A and high-side current114B, high-side receiver circuit106may receive a signal undisturbed by noise, common mode voltage change, ringing, EMI, and the like.

Thus, a high voltage level shifter as described herein is expected to transmit signals that are insensitive to disturbances or noise in the circuit. This noise, if left unchecked, may induce false switching commands in high voltage level shifter devices102and high-side latch118(not depicted), or prevent switching commands from reaching high voltage level shifter device102or high-side latch118altogether. Accordingly, the high voltage level shifter as described herein may prevent damage to the half bridge due to noise due to common-mode voltage change, ringing, or EMI. Furthermore, the high voltage level shifter as described herein may continue to transfer control signals, even during large common mode voltage changes in the high-side circuit, without losing command signals. Thus, the high voltage level shifter100described herein may be more robust against higher levels of noise and common-mode voltage change than other level shifters.

In the example ofFIG. 4, reference current310defines the target value. The collector current of the BJTs of differential amplifier108is a function of the difference of the currents112A and112B. The collector current is compared against the reference current310. If the collector current is less, the greater current of the reference will pull up the input of low-side control circuit104, leading to an increase of the gate voltage of the active one of the transistors302. If the collector current is greater, it will pull down the input of low-side control circuit104against the reference current310, leading to a decrease of the gate voltage of the active one of the transistors302.

In some examples, each of low-side control circuit differential amplifier108and high-side receiver differential amplifier106include a first and second pair of current divider resistors320and322. With respect to differential amplifier108, each of the current sensing resistors (e.g., resistor320A from302A to ground and resistor320B from302B to ground) in relation to the each of the resistors in series with the bipolar transistors of differential amplifier108(e.g., resistors322A and322B) defines a current divider ratio. In some examples, this divider ratio is in the order from 2:1 to 10:1. In other words, the value of resistors322is two to ten times greater than the value of resistors320. Therefore, the current flowing through the corresponding bipolar transistor is smaller than currents112and114. Each of the current sensing resistors320A-320B should have the same value (e.g., 1:1), while each of the resistors322A and322B in series with the bipolar transistors should have the same value (e.g., 1:1). Resistors320C-320D and322C-322D of high-side receiver differential amplifier106are configured in a similar fashion.

In some examples, differential amplifier108and high-side receiver circuit106include one or more vertical BJT transistors. Vertical BJTs may provide certain advantages over other types of transistors. For example, the voltage of the base/emitter complex of an NPN vertical BJT has no direct P-N junction to the substrate. Therefore, it can operate far below the substrate potential, which is ground or the low-side voltage rail. For example, the base/emitter complex of the PNP vertical BJT has no direct P-N junction to an N-well/N-buried layer region which isolates the high side circuit from the rest of the chip. Therefore, it can operate far above the high-side voltage rail, which is also the voltage level of the N-well/N-buried layer region. Therefore, the common mode range of the emitter/base regions of a vertical BJT may only be limited by the device breakdown voltage in one direction and the supply voltage in the other direction. Further, this value is much higher than the signal threshold for the differential signal, which is typically around 0.7V for BJTs.

In other examples, differential amplifier108and high-side receiver circuit106include one or more vertical MOSFETs. In some examples, the MOSFETs are DMOS transistors having a bulk connected to the source. Otherwise, providing a separate supply to the bulk may drastically reduce the common mode range. For example, the source/bulk region of the vertical MOSFETs included in the differential amplifier108have no direct P-N-junction to substrate and the source/bulk region of the vertical MOSFETs included in the high-side receiver circuit106have no direct P-N junction to the N-well/N-buried layer region which isolates the high side circuit from the rest of the chip.

High-side receiver circuit106receives high-side current signals114A-114B and generates output signals116A-116B which sets the state of high-side latch118ofFIG. 1(not depicted). High-side latch118sets an output which controls operation of high side switch Q1ofFIG. 1.

In one example, differential amplifier108includes a first low-side cross-coupled device and a second low-side cross-coupled device, each having a control terminal, an output terminal, and a common or ground terminal. In some examples, the first and second cross-coupled devices are transistors having an emitter, a base, and a collector terminal. In an example configuration, the common terminal of the first low-side cross-coupled device is connected to the control terminal of the second low-side cross-coupled device102A and the first low-side terminal of the first high voltage level shifter device. Further, the common terminal of the second low-side cross-coupled device is connected to the control terminal of the first low-side cross-coupled device and the second low-side terminal of the second high voltage level shifter device102B.

In another example, high-side receiver circuit106includes a first high-side cross-coupled device and a second high-side cross coupled device, each having a control terminal, an output terminal, and a common or ground terminal. In some examples, the first and second cross-coupled devices are transistors having an emitter, a base, and a collector terminal. In an example configuration, the common terminal of the first high-side cross-coupled device is connected to the control terminal of the second high-side cross-coupled device and to the first high-side terminal of the first high voltage level shifter device102A. Further, the common terminal of the second high-side cross-coupled device is connected to the control terminal of the first high-side cross-coupled device and to the second high-side terminal of the second high voltage level shifter device102B.

According to the techniques of this disclosure, while one of high voltage level shifter devices102is active, low-side control circuit104monitors the low-side current112of the inactive high voltage level shifter device102. As an example, low-side control circuit104drives transistor302A into the active state and transistor302B into the inactive state. Because transistor302A is active, low-side current112A is predicted to reach a target value. Further, because transistor302B is inactive, low-side current112B is expected to be approximately zero. Thus, the difference between low-side currents112A and112B is expected to be substantially the same as the predicted value of low-side current112A while transistor302A is active. Low-side control circuit104receives a signal from differential amplifier108indicative of the measured difference between low-side currents112A and112B. Due to fabrication tolerances, temperature dependency, and voltage dependency, low-side current112A is unlikely to match the target value immediately after activation. By measuring the low-side current112A via differential amplifier108and comparing it to the target value, low-side control circuit104adjusts control signal115A until the low-side current112A matches the target value.

In the presence of disturbances like noise, common mode voltage change, ringing or EMI, the low-side current112A does not accurately indicate the current flowing through transistor302A. Therefore, in other devices, the low-side control circuit104, by monitoring only the low-side current112A, may adjust control signal115A to cause an incorrect level of current to flow through transistor302A. The techniques of the disclosure assume that the effect of disturbances such as noise, common mode voltage change, ringing, EMI, and the like is the same on both high voltage level shifter devices102A and102B. Therefore, in the presence of such disturbances, the low-side control circuit104monitors the difference between low-side currents112A and112B and adjusts the control signal115A until the difference between low-side currents112A and112B matches a target value. In doing so, the current flowing through transistor302A is regulated to the target value, even in the presence of such disturbances.

Furthermore, without the presence of these disturbances, the high-side current114A is assumed to be equal to the low-side current112A, while high-side current114B is assumed to be equal to low-side current112B. The presence of these disturbances causes high-side current114A to differ from low-side current112A and high-side current114B to differ from low-side current112B. The difference of high-side current114A and low-side current112A on the active device102A is assumed to be the same as the difference of high-side current114B and low-side current112B on the inactive device102B. Therefore, by measuring the difference of low-side current112A and low-side current112B via differential amplifier108, and by using control signal115A to adjust the difference between low-side current112A and low-side current112B to a target value via low-side control circuit104, the difference between high-side current114A and high-side current114B may be controlled to match the target value, even in the presence of these disturbances. Finally, by monitoring the difference between high-side current114A and high-side current114B, high-side receiver circuit106may receive a signal undisturbed by noise, common mode voltage change, ringing, EMI, and the like.

Thus, a high voltage level shifter as described herein is expected to transmit signals that are insensitive to disturbances or noise in the circuit. This noise, if left unchecked, may induce false switching commands in high voltage level shifter devices102and high-side latch118, or prevent switching commands from reaching high voltage level shifter device102or high-side latch118altogether. Accordingly, the high voltage level shifter as described herein may prevent damage to the half bridge due to noise due to common-mode voltage change, ringing, or EMI. Furthermore, the high voltage level shifter as described herein may continue to transfer control signals, even during large common mode voltage changes in the high-side circuit, without losing command signals. Thus, the high voltage level shifter100described herein may be more robust against higher levels of noise and common-mode voltage change than other level shifters.

In some examples, low-side control circuit104is edge sensitive. In other examples, an edge detection circuit is located upstream of low-side control circuit104, as depicted in the example ofFIG. 4. While the input signal112is static, both high voltage level shifter devices102are in an inactive state. Only when low-side control circuit104detects a signal edge on the input112, does the edge detection circuit generate a short pulse, either on the input controlling the gate of transistor302A (e.g., the buffer generating current115A ofFIG. 4) or on the input controlling the gate of transistor302B (e.g. the buffer generating current115B ofFIG. 4). It should be noted that directly coupling input signals112without edge detection to the gates of transistors302would theoretically work. However, the power dissipation required may exceed the capability of transistors302if static current flows through one of transistors302. High side latch118is only needed if edge detection is used on the low-side circuit to store the last pulse of low-side control circuit104while the input is static and none of high voltage level shifter devices102or transistors302is active.

The architecture of high voltage level shifter100illustrated inFIG. 4is shown as an example. The techniques as set forth in this disclosure may be implemented in the example high voltage level shifter100ofFIG. 4, as well as other types of high voltage level shifters not described specifically herein. Nothing in this disclosure should be construed so as to limit the techniques of this disclosure to the example architecture illustrated byFIG. 4.

FIG. 5is a flowchart illustrating an example operation of a high voltage level shifter according to the techniques of the disclosure. For convenience,FIG. 5is described with respect toFIG. 2although other circuits may be used to implement the techniques.

As shown in the example ofFIG. 5, low-side control circuit106receives an input signal103from a low-side voltage domain (400). In response to the input signal103, low-side control circuit106drives one of high voltage level shifter devices102into an active state while driving the other of high voltage level shifter devices102into an inactive state (402).

While one of high voltage level shifter devices102is active, low-side control circuit104monitors the low-side current112of the inactive high voltage level shifter device102(404). Because high voltage level shifter device102A is active, low-side current112A is predicted to reach a target value. Further, because high voltage level shifter device102B is inactive, low-side current112B is expected to be approximately zero. Thus, the difference between low-side currents112A and112B is expected to be substantially the same as the predicted value of low-side current112A while high voltage level shifter device102A is active. Low-side control circuit104receives a signal from differential amplifier108indicative of the measured difference between low-side currents112A and112B. Due to fabrication tolerances, temperature dependency, and voltage dependency, low-side current112A is unlikely to match the target value immediately after activation. By measuring the low-side current112A via differential amplifier108and comparing it to the target value, low-side control circuit104adjusts control signal115A until the low-side current112A matches the target value (406). Low-side control circuit104continuously monitors the low-side current112of the inactive high voltage level shifter device102(404) and adjusts control signals115until the low-side current112A matches the target value (406) while one of the high voltage level shifter devices102is active.

In the presence of disturbances like noise, common mode voltage change, ringing or EMI, the low-side current112A does not accurately indicate the current flowing through level shifter device102A. Therefore, in other devices, the low-side control circuit104, by monitoring only the low-side current112A, may adjust control signal115A to cause an incorrect level of current to flow through the level shifter device102A. The techniques of the disclosure assume that the effect of disturbances such as noise, common mode voltage change, ringing, EMI, and the like is the same on both high voltage level shifter devices102A and102B. Therefore, in the presence of such disturbances, the low-side control circuit104monitors the difference between low-side currents112A and112B and adjusts the control signal115A until the difference between low-side currents112A and112B matches a target value. In doing so, the current flowing through level shifter device102A is regulated to the target value, even in the presence of such disturbances.

In parallel to low-side control circuit104monitoring the low-side current112and adjusting control signals115, high-side receiver circuit106monitors a difference between high-side output currents114A and114B (408). In response to high-side current signals114A-114B, high-side receiver circuit106generates an output signal116which sets the state of high-side latch118. High-side latch118sets an output130of the level shifter circuit as a high-side voltage domain101B equivalent to the state of input signal103of low-side voltage domain101A. Output130controls operation of high side switch Q1ofFIG. 1(410).

Without the presence of disturbances in the current, the high-side current114A is assumed to be equal to the low-side current112A, while high-side current114B is assumed to be equal to low-side current112B. The presence of these disturbances causes high-side current114A to differ from low-side current112A and high-side current114B to differ from low-side current112B. The techniques of the disclosure assume that the difference of high-side current114A and low-side current112A on the active device is the same as the difference of high-side current114B and low-side current112B on the inactive device102B. Therefore, by measuring the difference of low-side current112A and low-side current112B via differential amplifier108, and by using control signal115A to adjust the difference between low-side current112A and low-side current112B to a target value via low-side control circuit104, the difference between high-side current114A and high-side current114B may be controlled to match the target value, even in the presence of these disturbances. Finally, by monitoring the difference between high-side current114A and high-side current114B, high-side receiver circuit106may receive a signal undisturbed by noise, common mode voltage change, ringing, EMI, and the like.

Thus, a high voltage level shifter as described herein is expected to transmit signals that are insensitive to disturbances or noise in the circuit. This noise, if left unchecked, may induce false switching commands in high voltage level shifter devices102and high-side latch118, or prevent switching commands from reaching high voltage level shifter device102or high-side latch118altogether. Accordingly, the high voltage level shifter as described herein may prevent damage to the half bridge due to noise due to common-mode voltage change, ringing, or EMI. Furthermore, the high voltage level shifter as described herein may continue to transfer control signals, even during large common mode voltage changes in the high-side circuit, without losing command signals. Thus, the high voltage level shifter100described herein may be more robust against higher levels of noise and common-mode voltage change than other level shifters.

The operation of high voltage level shifter100illustrated inFIG. 5is shown as an example. The techniques as set forth in this disclosure may be implemented in the example operation ofFIG. 5, as well as other operations not described specifically herein. Nothing in this disclosure should be construed so as to limit the techniques of this disclosure to the example operation illustrated byFIG. 5.

The following examples may illustrate one or more aspects of the disclosure.

A high voltage level shifter configured to translate an input signal from a low-side low voltage domain to a high-side low voltage domain, the high voltage level shifter comprising: a first high voltage level shifter device, wherein the first high voltage level shifter device comprises a first high-side terminal, a first low-side terminal, and a first control terminal, and wherein the first control terminal is configured to control a first current flowing into the first high-side terminal to the first low-side terminal; a second high voltage level shifter device, wherein the second high voltage level shifter device comprises a second high-side terminal, a second low-side terminal, and a second control terminal, and wherein the second control terminal is configured to control a second current flowing into the second high-side terminal to the second low-side terminal; a low-side control circuit configured to drive the first control terminal and the second control terminal, wherein the low-side control circuit is further configured to drive, in response to the input signal, one of the first high voltage level shifter device and the second high voltage level shifter device to an active state while the other of the first high voltage level shifter device and the second high voltage level shifter device remains in an inactive state; a high-side receiver circuit configured to set a state of a high-side output signal in response to the one of the first high voltage level shifter device and the second high voltage level shifter device driven in the active state; wherein the high-side receiver circuit is configured to monitor a first difference between the first current flowing into the first high-side terminal of the first high voltage level shifter device and the second current flowing into the second high-side terminal of the second high voltage level shifter device; and wherein the low-side control circuit is configured to control a concomitant control terminal of the first control terminal and the second control terminal corresponding to the one of the first high voltage level shifter device and the second high voltage level shifter device driven in the active state in response to a second difference between the first current and the second current monitored flowing out of the first low-side terminal and the second low-side terminal.

The high voltage level shifter of example 1, wherein each of the low-side low voltage domain and the high-side low voltage domain comprises a positive rail and a negative rail; the first high-side terminal of the first high voltage level shifter device is connected to the positive rail of the high-side domain via a first high-side current sensing device; the second high-side terminal of the second high voltage level shifter device is connected to the positive rail of the high-side domain via a second high-side current sensing device; the first low-side terminal of the first high voltage level shifter device is connected to the negative rail of the low-side domain via a first low-side current sensing device; and the second low-side terminal of the second high voltage level shifter device is connected to the negative rail of the low-side domain through a second low-side current sensing device.

The high voltage level shifter of any of examples 1-2, wherein each of the first high-side current sensing device and the second high-side current sensing device comprise a resistor of a first value; wherein each of the first low-side current sensing device and the second low-side current sensing device comprise a resistor of a second value; and wherein the first value and the second value have a predetermined ratio.

The high voltage level shifter of any of examples 1-3, wherein the predetermined ratio is substantially equal to 1.

The high voltage level shifter of any of examples 1-4, wherein the high-side receiver circuit comprises a first high-side cross-coupled device and a second high-side cross-coupled device, wherein each of the first high-side cross-coupled device and the second high-side cross-coupled device comprises: a control terminal; an output terminal; and a common terminal; wherein the common terminal of the first high-side cross-coupled device is connected to the control terminal of the second high-side cross-coupled device and the first high-side terminal of the first high voltage level shifter device; and wherein the common terminal of the second high-side cross-coupled device is connected to the control terminal of the first high-side cross-coupled device and the second high-side terminal of the second high voltage level shifter device.

The high voltage level shifter of any of examples 1-5, wherein the low-side control circuit comprises a first low-side cross-coupled device and a second cross-coupled device, wherein each of the first low-side cross-coupled device and the second cross-coupled device comprise: a control terminal; an output terminal; and a common terminal; wherein the common terminal of the first low-side cross-coupled device is connected to the control terminal of the second low-side cross-coupled device and to the first low-side terminal of the first high voltage level shifter device; and wherein the common terminal of the second low-side cross-coupled device is connected to the control terminal of the first low-side cross-coupled device and to the second low-side terminal of the second high voltage level shifter device.

The high voltage level shifter of any of examples 1-6, wherein a monolithic integrated circuit comprises the high voltage level shifter, and wherein the high-side receiver circuit is isolated from a substrate of the monolithic integrated circuit by an n-doped well connected to the positive rail of the high-side domain.

The high voltage level shifter of any of examples 1-7, wherein each of the first high-side cross-coupled device and the second high-side cross-coupled device is a vertical bipolar transistor; wherein each corresponding control terminal of the first high-side cross-coupled device and the second high-side cross-coupled device is a base terminal of the vertical bipolar transistor; wherein each corresponding common terminal of the first high-side cross-coupled device and the second high-side cross-coupled device is an emitter terminal of the vertical bipolar transistor; wherein each corresponding output terminal of the first high-side cross-coupled device and the second high-side cross-coupled device is a collector terminal of the vertical bipolar transistor; and wherein each of an emitter region and a base region of the vertical bipolar transistor has no direct PN junction to the n-doped well.

The high voltage level shifter of any of examples 1-8, wherein each of the first high-side cross-coupled device and the second high-side cross-coupled device is a vertical MOS transistor; wherein each corresponding control terminal of the first high-side cross-coupled device and the second high-side cross-coupled device is a gate terminal of the vertical MOS transistor; wherein each corresponding common terminal of the first high-side cross-coupled device and the second high-side cross-coupled device is a source terminal of the vertical MOS transistor; wherein each corresponding output terminal of the first high-side cross-coupled device and the second high-side cross-coupled device is a drain terminal of the vertical MOS transistor; and wherein a source region of the vertical MOS transistor has no direct PN junction to the n-doped well.

A method comprising: receiving, via a low-side control circuit of a high voltage level shifter, an input signal from a low-side low voltage domain; driving, by the low-side control circuit and in response to the received input signal, one of a first high voltage level shifter device and a second high voltage level shifter device to an active state while the other of the first high voltage level shifter device and the second high voltage level shifter device remains in an inactive state, wherein the first high voltage level shifter device comprises a first high-side terminal, a first low-side terminal, and a first control terminal, wherein the first control terminal is configured to control a first current flowing into the first high-side terminal to the first low-side terminal, wherein the second high voltage level shifter device comprises a second high-side terminal, a second low-side terminal, and a second control terminal, and wherein the second control terminal is configured to control a second current flowing into the second high-side terminal to the second low-side terminal; setting, by a high-side receiver circuit, a state of a high-side output signal in response to a monitored first difference between the first current flowing into the first high-side terminal of the first high voltage level shifter device and the second current flowing into the second high-side terminal of the second high voltage level shifter device; and controlling, by the low-side control circuit and in response to a second difference between the first current monitored flowing out of the first low side terminal and the second current monitored flowing out of the second low side terminal, a concomitant control terminal of the first control terminal and the second control terminal corresponding to the one of the first high voltage level shifter device and the second high voltage level shifter device driven in the active state.

The method of example 10, wherein each of the low-side low voltage domain and the high-side low voltage domain comprises a positive rail and a negative rail; the first high-side terminal of the first high voltage level shifter device is connected to the positive rail of the high-side domain via a first high-side current sensing device; the second high-side terminal of the second high voltage level shifter device is connected to the positive rail of the high-side domain via a second high-side current sensing device; the first low-side terminal of the first high voltage level shifter device is connected to the negative rail of the low-side domain via a first low-side current sensing device; and the second low-side terminal of the second high voltage level shifter device is connected to the negative rail of the low-side domain through a second low-side current sensing device.

The method of any of examples 10-11, wherein each of the first high-side current sensing device and the second high-side current sensing device comprise a resistor of a first value; wherein each of the first low-side current sensing device and the second low-side current sensing device comprise a resistor of a second value; and wherein the first value and the second value have a predetermined ratio.

The method of any of examples 10-12, wherein the predetermined ratio is substantially equal to 1.

The method of any of examples 10-13, wherein the high-side receiver circuit comprises a first high-side cross-coupled device and a second high-side cross-coupled device, wherein each of the first high-side cross-coupled device and the second high-side cross-coupled device comprises: a control terminal; an output terminal; and a common terminal; wherein the common terminal of the first high-side cross-coupled device is connected to the control terminal of the second high-side cross-coupled device and the first high-side terminal of the first high voltage level shifter device; and wherein the common terminal of the second high-side cross-coupled device is connected to the control terminal of the first high-side cross-coupled device and the second high-side terminal of the second high voltage level shifter device.

The method of any of examples 10-14, wherein the low-side control circuit comprises a first low-side cross-coupled device and a second cross-coupled device, wherein each of the first low-side cross-coupled device and the second cross-coupled device comprise: a control terminal; an output terminal; and a common terminal; wherein the common terminal of the first low-side cross-coupled device is connected to the control terminal of the second low-side cross-coupled device and to the first low-side terminal of the first high voltage level shifter device; and wherein the common terminal of the second low-side cross-coupled device is connected to the control terminal of the first low-side cross-coupled device and to the second low-side terminal of the second high voltage level shifter device.

The method of any of examples 10-15, wherein a monolithic integrated circuit comprises the high voltage level shifter, and wherein the high-side receiver circuit is isolated from a substrate of the monolithic integrated circuit by an n-doped well connected to the positive rail of the high-side domain.

The method of any of examples 10-17, wherein each of the first high-side cross-coupled device and the second high-side cross-coupled device is a vertical bipolar transistor; wherein each corresponding control terminal of the first high-side cross-coupled device and the second high-side cross-coupled device is a base terminal of the vertical bipolar transistor; wherein each corresponding common terminal of the first high-side cross-coupled device and the second high-side cross-coupled device is an emitter terminal of the vertical bipolar transistor; wherein each corresponding output terminal of the first high-side cross-coupled device and the second high-side cross-coupled device is a collector terminal of the vertical bipolar transistor; and wherein each of an emitter region and a base region of the vertical bipolar transistor has no direct PN junction to the n-doped well.

The method of any of examples 10-17, wherein each of the first high-side cross-coupled device and the second high-side cross-coupled device is a vertical MOS transistor; wherein each corresponding control terminal of the first high-side cross-coupled device and the second high-side cross-coupled device is a gate terminal of the vertical MOS transistor; wherein each corresponding common terminal of the first high-side cross-coupled device and the second high-side cross-coupled device is a source terminal of the vertical MOS transistor; wherein each corresponding output terminal of the first high-side cross-coupled device and the second high-side cross-coupled device is a drain terminal of the vertical MOS transistor; and wherein a source region of the vertical MOS transistor has no direct PN junction to the n-doped well.

A high voltage level shifter configured to translate an input signal from a low-side low voltage domain to a high-side low voltage domain, the high voltage level shifter comprising: a first high voltage level shifter device, wherein the first high voltage level shifter device comprises a first high-side terminal, a first low-side terminal, and a first control terminal, and wherein the first control terminal is configured to control a first current flowing into the first high-side terminal to the first low-side terminal; a second high voltage level shifter device, wherein the second high voltage level shifter device comprises a second high-side terminal, a second low-side terminal, and a second control terminal, and wherein the second control terminal is configured to control a second current flowing into the second high-side terminal to the second low-side terminal; means for low-side control, wherein the means for low-side control is configured to drive the first control terminal and the second control terminal, wherein the means for low-side control is further configured to drive, in response to the input signal, one of the first high voltage level shifter device and the second high voltage level shifter device to an active state while the other of the first high voltage level shifter device and the second high voltage level shifter device remains in an inactive state; means for high-side receiving, wherein the means for high-side receiving is configured to set a state of a high-side output signal in response to the one of the first high voltage level shifter device and the second high voltage level shifter device driven in the active state; wherein the means for high-side receiving is configured to monitor a first difference between the first current flowing into the first high-side terminal of the first high voltage level shifter device and the second current flowing into the second high-side terminal of the second high voltage level shifter device; and wherein the means for low-side control is configured to control a concomitant control terminal of the first control terminal and the second control terminal corresponding to the one of the first high voltage level shifter device and the second high voltage level shifter device driven in the active state in response to a second difference between the first current monitored flowing out of the first low side terminal and the second current monitored flowing out of the second low side terminal.

The high voltage level shifter of example 19, wherein each of the low-side low voltage domain and the high-side low voltage domain comprises a positive rail and a negative rail; the first high-side terminal of the first high voltage level shifter device is connected to the positive rail of the high-side domain via a first high-side current sensing device; the second high-side terminal of the second high voltage level shifter device is connected to the positive rail of the high-side domain via a second high-side current sensing device; the first low-side terminal of the first high voltage level shifter device is connected to the negative rail of the low-side domain via a first low-side current sensing device; and the second low-side terminal of the second high voltage level shifter device is connected to the negative rail of the low-side domain through a second low-side current sensing device.

The techniques described in this disclosure may be implemented within the same device or within separate devices to support the various operations and functions described in this disclosure. In addition, any of the described units, modules, or components may be implemented together or separately as discrete but interoperable components. Depiction of different features as modules or units is intended to highlight different functional aspects and does not necessarily imply that such modules or units must be realized by separate hardware components. Rather, functionality associated with one or more modules or units may be performed by separate hardware components, or integrated within common or separate hardware components.