Memory device sampling data using control signal transmitted through TSV

A memory die of a memory device includes a first first-in first-out (FIFO) circuit that samples data output from a memory cell array and outputs the data to a buffer die through a first through silicon via, based on a control signal transmitted from the buffer die. A buffer die of the memory device includes a second FIFO circuit that samples the data output from the first FIFO unit based on the control signal transmitted from the memory die through a second through silicon via, a calibration circuit that generates a delay code, based on a latency of a path from the buffer die to the first FIFO circuit and from the first FIFO circuit to the second FIFO circuit, and a delay control circuit that generates the control signal transmitted to the memory die through a third through silicon via, based on the read command and the delay code.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims priority under 35 U.S.C. § 119 to Korean Patent Application No. 10-2018-0037151 filed on Mar. 30, 2018, in the Korean Intellectual Property Office, the disclosure of which is incorporated by reference herein in its entirety.

BACKGROUND

The present disclosure relates to a semiconductor device, and more particularly, relates to a memory device sampling data using a control signal transmitted through a through silicon via (TSV).

A plurality of memory dies may be stacked to increase the degree of integration of a memory device. A memory device with three-dimensional structure may store and process a large amount of data. For forming the three-dimensional structure, various packaging technologies may be applied to semiconductor dies. In particular, since a through silicon via (TSV) is appropriate for miniaturization and high speed of the memory device, the through silicon via may be used to stack semiconductor dies.

Time points at which signals are output from stacked memory dies may vary due to process, voltage, and temperature variations of the memory dies. The difference between the output time points may make it difficult for the memory device to operate at a high speed. Also, in the case where a circuit of compensating for the output time points is positioned on a buffer die where memory dies are stacked, the area of the buffer die may increase.

SUMMARY

Embodiments of the present disclosure provide a memory device which samples data by using a control signal transmitted through a through silicon via.

According to an exemplary embodiment, a memory device may include a buffer die receiving a read command, and a memory receiving the read command transmitted from the buffer die. The memory die may include a memory cell array that outputs data in response to the read command, and a first first-in first-out (FIFO) circuit that samples the data output from the memory cell array, and outputs the data to the buffer die through a first through silicon via, based on a control signal transmitted from the buffer die. The buffer die may include a second FIFO circuit that samples the data output from the first FIFO circuit through the first through silicon via, based on the control signal transmitted from the memory die through a second through silicon via, a calibration unit that generates a delay code, based on a latency of a path from the buffer die to the first FIFO circuit and from the first FIFO circuit to the second FIFO circuit, and a delay control circuit that generates the control signal transmitted to the memory die through a third through silicon via, based on the read command and the delay code.

According to an exemplary embodiment, a memory device may include a buffer die receiving a read command, and a memory die receiving the read command transmitted from the buffer die. The memory die may include a memory cell array that outputs data in response to the read command, a delay control circuit that generates a control signal, based on the read command and a delay code output from the buffer die, and a first FIFO circuit that samples the data output from the memory cell array and outputs the data to the buffer die through a first through silicon via, based on the control signal. The buffer die may include a second FIFO circuit that samples the data output from the first FIFO circuit through the first through silicon via, based on the control signal transmitted from the memory die through a second through silicon via, and a calibration unit that generates the delay code, based on a latency of a path from the buffer die to the first FIFO circuit and from the first FIFO circuit to the second FIFO circuit.

According to an exemplary embodiment, a memory device may include a buffer die receiving a read command, and a plurality of memory dies that receive the read command transmitted from the buffer die. Each of the plurality of memory dies may include a memory cell array that outputs data in response to the read command, and a first FIFO circuit that samples the data output from the memory cell array and outputs the data to the buffer die through at least one first through silicon via, based on the control signal. The buffer die may include a second FIFO circuit that samples the data output from the first FIFO circuit through the at least one first through silicon via, based on the control signal transmitted from each of the plurality of memory dies through at least one second through silicon via, and a calibration unit that generates a delay code indicating a delay of the control signal, based on a latency of a path from the buffer die to the first FIFO circuit and from the first FIFO circuit to the second FIFO circuit.

DETAILED DESCRIPTION

Below, embodiments of the inventive concept may be described in detail and clearly to such an extent that an ordinary one in the art easily implements the inventive concept.

FIG. 1is a diagram illustrating an electronic device according to an embodiment of the inventive concept. An electronic device10may include a memory device11, a system on chip (SoC)13, and an interposer15.

As used herein, a memory device may refer to various items such as a semiconductor memory device, one or more logic devices or memory cells formed in or on a semiconductor substrate, a semiconductor chip, a memory chip, a memory die, a logic chip, a package, a package including one or more memory chips and optionally one or more logic chips, or combinations thereof. A memory device such as a semiconductor chip, a memory chip, or a logic chip may be formed from a wafer. A memory device may comprise a package which may include one or more chips stacked on a package substrate, or a package-on-package device including a plurality of packages.

An electronic device, as used herein, may refer to one of these devices and may also include products that include these devices, such as a memory card, a memory module, a hard drive including additional components, a mobile phone, laptop, tablet, desktop, camera, server, computing system, or other consumer electronic device, etc.

The memory device11may include first to eighth memory dies11_1to11_8and a buffer die11_9. The first to eighth memory dies11_1to11_8may be sequentially stacked on the buffer die11_9in a perpendicular direction. The first to eighth memory dies11_1to11_8and the buffer die11_9may be electrically connected to each other through micro bumps and through silicon vias TSV arranged in a matrix form. The TSV may be referred to as a through substrate via. Locations of the through silicon vias and the micro bumps are not limited to illustration ofFIG. 1. For example, though a plurality of through silicon vias and micro bumps of the first to eighth memory dies11_1to11_8and a buffer die11_9disposed in a first column COL1are connected to each other, the through silicon vias of the first to eighth memory dies11_1to11_8disposed in the first column COL1may be connected to a through silicon via of the buffer die11_9disposed in a second column COL2, a third column COL3, or a fourth column COL4.

The first to eighth memory dies11_1to11_8may be identically manufactured. The first to eighth memory dies11_1to11_8may constitute a stack. The memory device11is illustrated inFIG. 1as including eight memory dies11_1to11_8. However, the inventive concept is not limited thereto. Here, a memory die may be referred to as a “core die”, a “slave die”, etc., and a die may be referred to as a “chip”.

The buffer die11_9may communicate with a device (e.g., the SoC13) positioned at the outside of the memory device11. The buffer die11_9may transmit an address and data provided from the SoC13to the first to eighth memory dies11_1to11_8and may receive data from the first to eighth memory dies11_1to11_8. The buffer die11_9may provide an interface between the first to eighth memory dies11_1to11_8and the buffer die11_9. The buffer die11_9may include a physical layer (PHY)12electrically connected with the SoC13. Here, the buffer die11_9may be referred to as an “interface die”, a “master die”, a logic die”, etc.

In an embodiment, the memory device11may be a general-purpose dynamic random access memory (DRAM) device such as a double data rate (DDR) synchronous DRAM (SDRAM), a DDR2 SDRAM device, a DDR3 SDRAM device, a DDR4 SDRAM device, or a DDR5 SDRAM device. The memory device11may be a mobile DRAM device such as a low power double data rate (LPDDR) SDRAM device, an LPDDR2 SDRAM device, an LPDDR3 SDRAM device, an LPDDR4 SDRAM device, an LPDDR4X SDRAM device, or an LPDDR5 SDRAM device. The memory device11may be a graphics DRAM device such as a graphics double data rate (GDDR) synchronous graphics random access memory (SGRAM) device, a GDDR2 SGRAM device, a GDDR3 SGRAM device, a GDDR4 SGRAM device, a GDDR5 SGRAM device, or a GDDR6 SGRAM device. The memory device11may be a memory device, which provides a large capacity and a high bandwidth, such as wide I/O, a high bandwidth memory (HBM), a HBM2, a HBM3, a hybrid memory cube (HMC).

The SoC13may include a processor, which may perform various operations, for applications which the electronic device10supports. For example, the SoC13may include at least one of a central processing unit (CPU), an image signal processing unit (ISP), a digital signal processing unit (DSP), a graphics processing unit (GPU), a vision processing unit (VPU), and a neural processing unit (NPU). The SoC13may include a physical layer (PHY)14electrically connected with the buffer die11_9. The SoC13may store data necessary for an operation to the memory device11or may read data necessary for an operation from the memory device11.

The interposer15may connect the memory device11and the SoC13. In particular, the interposer15may provide physical paths which are interposed between the memory device11and the SoC13and are formed of conductive materials for an electrical connection. In some examples, the interposer15may be a silicon interposer. In some examples, the interposer15may be a printed circuit board (PCB) or a package substrate.

FIG. 2is a block diagram illustrating a buffer die and a first memory die of the memory device ofFIG. 1according to example embodiments.FIG. 2will be described with reference toFIG. 1. A first memory die110may be the first memory die11_1ofFIG. 1. A buffer die120may be the buffer die11_9ofFIG. 1. A memory device100may include the first memory die110and the buffer die120. The memory device100may be the memory device11ofFIG. 1. In some examples, the first memory die110may be any one of the second to eighth memory dies11_2to11_8ofFIG. 1. A first through silicon via TSV1, a second through silicon via TSV2, a third through silicon via TSV3, and a sixth through silicon via TSV6, which are used for a communication between the first memory die110and the buffer die120may pass through the buffer die120. As well as through silicon vias illustrated inFIG. 2, other through silicon vias may be further formed in the buffer die120.

In example embodiments, each of the first through silicon via, second through silicon via, third through silicon via, and sixth through silicon via may penetrate the buffer die120or the first memory die110, and the first through silicon via, second through silicon via, third through silicon via, and sixth through silicon via may be horizontally spaced apart from each other.

The first memory die110may include a first command decoder111, a first memory cell array112, a first delay control circuit113, and a first first-in first-out (FIFO) unit116. As used herein, a “unit” may refer to a “circuit”.

The first command decoder111may receive addresses (or, command addresses) from the buffer die120through the sixth through silicon via. Here, the address may constitute AWORD, and may include a row command, a row address, a column command, a column address, etc. For brevity of drawing, the sixth through silicon via is illustrated as including one through silicon via, but the number of the sixth through silicon via may be one or more. In example embodiments, the buffer die120may further include a command buffer (not shown). In some examples, the command buffer may delay the AWORD signal. Thus, the first command decoder111may receive the delayed signal of the AWORD signal from the command buffer of the buffer die120.

The first command decoder111may decode various commands, which are transmitted from the buffer die120, such as an activation command, a write command, a refresh command, a read command, a precharge command, etc. The first command decoder111may decode a command and may control circuits (the first memory cell array112, the first delay control circuit113, etc.) constituting the first memory die110.

The first memory cell array112may include memory cells (not illustrated) at intersections of word lines (i.e., rows) and bit lines (i.e., columns). For example, a memory cell may be a DRAM cell, a static random access memory (SRAM) cell, a NAND flash memory cell, a NOR flash memory cell, a resistive random access memory (RRAM) cell, a ferroelectric random access memory (FRAM) cell, a phase change random access memory (PRAM) cell, a thyristor random access memory (TRAM) cell, a magnetic random access memory (MRAM) cell, etc.

The first memory cell array112may be divided into a plurality of banks depending on the number of banks, a capacity, etc. which a memory device100supports. The number of the first memory cell array112is not limited to this disclosure.

The first memory cell array112may store data in response to a write command. The first memory cell array112may output the stored data in response to a read command. A row decoder and a column decoder, which control the first memory cell array112under control of the first command decoder111, are not illustrated.

The first delay control circuit113may generate a first control signal CTRL1for sampling data output from the first memory cell array112in response to the read command. For example, the first delay control circuit113may generate the first control signal CTRL1, based on a first internal read signal IRS1of the first command decoder111. The first delay control circuit113may generate the first control signal CTRL1after a time needed for data to be output from the first memory cell array112depending on the read command.

In an embodiment, the first command decoder111may generate the first internal read signal IRS1after the time needed for the data to be output from the first memory cell array112depending on the read command. In another embodiment, the first delay control circuit113receives the first internal read signal IRS1, and then the first delay control circuit113may generate the first control signal CTRL1after the time needed for the data to be output from the first memory cell array112depending on the read command. An interval between the read command and the first control signal CTRL1may be set to a multiple of a period of a clock which the memory device100receives. Alternatively, the interval between the read command and the first control signal CTRL1may be set to an absolute value regardless of the clock which the memory device100receives.

The first FIFO unit116may sample data output from the first memory cell array112, based on the first control signal CTRL1. The first FIFO unit116may output the sampled data to the buffer die120through the first through silicon via, based on a second control signal CTRL2. In detail, the data may be composed of a plurality of bits. The first FIFO unit116may sequentially output sampled bits from a first sampled bit to a lastly sampled bit. A depth of the first FIFO unit116may indicate the number of bits which the first FIFO unit116may sample.

In an embodiment, the depth of the first FIFO unit116may be determined depending on a characteristic (e.g., a process, a voltage and a temperature (PVT) variation of the first memory die110) of the first memory die110and a characteristic of the buffer die120. In detail, the depth of the first FIFO unit116may be determined depending on the following condition: a time needed for data to be output from the first memory cell array112depending on a read command, a time needed from data to be output from the buffer die120, a read latency of the memory device100, etc.

Each of memory dies (e.g., the first to eighth memory dies11_1to11_8ofFIG. 1) may include the first FIFO unit116, and the depths of the first FIFO units116in the memory dies may be identical to or different from each other. For example, each of the memory dies may include the first FIFO unit116so that output time points (or read time points) of data output from the memory dies are synchronized with each other regardless of the PVT variation of the memory dies.

The buffer die120may include a second command decoder121, a second delay control circuit122, an output control circuit123, a second FIFO unit126, and a calibration unit127.

As in the first command decoder111, the second command decoder121may decode a command transmitted from the outside (e.g., the SoC13ofFIG. 1) of the memory device100. The second command decoder121may control circuits (the second delay control circuit122, the output control circuit123, the calibration unit127, etc.) constituting the buffer die120. The second command decoder121may provide a second internal read signal IRS2to the second delay control circuit122and the output control circuit123in response to the read command.

The second delay control circuit122may generate the second control signal CTRL2, based on the read command input to the memory device100and a delay code provided from the calibration unit127. The second control signal CTRL2may be transmitted to the first memory die110through the third through silicon via. The second delay control circuit122may generate the second control signal CTRL2in consideration of an output timing of the first FIFO unit116and a sampling timing of the second FIFO unit126. Alternatively, the second command decoder121may generate the second internal read signal IRS2in consideration of the output timing of the first FIFO unit116and the sampling timing of the second FIFO unit126.

The output control circuit123may generate an output control signal CTRL_OUT, based on the read command input to the memory device100. Here, the output control signal CTRL_OUT may correspond to a data strobe signal DQS used to sample data output from the memory device100. The output control circuit123may generate the output control signal CTRL_OUT in consideration of a read latency in advance determined, and a path between the second FIFO unit126and a DQ input/output pad (not illustrated). For example, the read latency may be in advance defined in compliance with a protocol between a memory device and a SoC, a JEDEC (Joint Electron Device Engineering Council) standard, etc.

The second FIFO unit126may sample data transmitted through the first through silicon via from the first FIFO unit116, based on the second control signal CTRL2transmitted from the first memory die110. Due to a location difference of the first FIFO unit116and the second FIFO unit126, a physical length of a path through which the second control signal CTRL2is transmitted, etc., the second FIFO unit126may receive the second control signal CTRL2to be later than the first FIFO unit116.

The second FIFO unit126may output the sampled data to the outside of the buffer die120(e.g., the SoC13). As in the first FIFO unit116, the second FIFO unit126may output sampled bits from a first sampled bit to a lastly sampled bit. The depth of the second FIFO unit126may indicate the number of bits which the second FIFO unit126may sample.

In an embodiment, the first memory die110may include the first FIFO unit116, and the buffer die120may include the second FIFO unit126. For example, the depth, the sampling time point, and the output time point of the first FIFO unit116and the depth, the sampling time point, and the output time point of the second FIFO unit126may be calibrated or adjusted to compensate for the PVT variation (or a PVT difference) between the first memory die110and the buffer die120.

In an embodiment, the second FIFO unit126may not immediately receive the second control signal CTRL2generated by the buffer die120. The second FIFO unit126may receive data through the first through silicon via from the first memory die110, and may similarly receive the second control signal CTRL2through the second through silicon via from the first memory die110. For example, the second FIFO unit126may receive the second control signal CTRL2passing through the second through silicon via.

In the case where an operating voltage of the memory device100decreases and an operating frequency increases, a capture margin (or a sampling margin) in which the second FIFO unit126samples data may decrease. Also, the capture margin may vary due to the PVT variation between the first memory die110and the buffer die120. Accordingly, to improve and uniformly maintain the capture margin, the memory device100may include a path through which data are transmitted from the first FIFO unit116to the second FIFO unit126and a path through which the second control signal CTRL2is transmitted from the first FIFO unit116to the second FIFO unit126. The paths may be implemented identically to each other, and loadings of the paths may be identical to each other.

Bits of data output from the second FIFO unit126may correspond to any one DQ (i.e., a data input/output signal). The number of DQs of the memory device100may be determined in compliance with the JEDEC standard. For example, the buffer die120may include the second FIFO units126as much as the number of DQs. The DQs may constitute “DWORD”. Also, the first memory die110may include a plurality of the first FIFO units116, based on the number of DQs.

Circuits which drive all DQs supported by the memory device100may be positioned at the buffer die120. Circuits for transmitting data to the circuits driving the DQs of the buffer die120may be distributed into the memory dies11_1to11_8ofFIG. 1. For example, the number of the second FIFO units126positioned at the buffer die120may be more than the number of the first FIFO units116positioned at the first memory die110. For example, the number of the first FIFO units116may be not more than half the number of the second FIFO units126. A CCD (CAS to CAS Delay or Read to Read Delay) of the buffer die120may be greater than a CCD of the first memory die110. The area of a physical layer (refer to PHY12ofFIG. 1) in the buffer die120may be limited by the area of a physical layer (refer to PHY14ofFIG. 1) in the SoC13ofFIG. 1. Accordingly, a limitation on the area of the buffer die120, in which the second FIFO units126are positioned, may be worse than a limitation on the area of the first memory die110, in which the first FIFO units116are positioned.

In an embodiment, the depth of the second FIFO unit126may be smaller than the depth of the first FIFO unit116. As described above, since the depth indicates the number of bits to be sampled, the area of the second FIFO unit126may decrease as the depth becomes smaller. For example, the depth of the second FIFO unit126may be not more than 2, and a time difference of the second control signal CTRL2and the output control signal CTRL_OUT which the second FIFO unit126receives may be within two times the period of the clock.

The calibration unit127may calculate a latency, which the buffer die120needs, of the read latency and may generate the delay code. For example, the read latency may be divided into an interval from a time point when the read command is input to a time point when data are output from the first memory cell array112, an interval from a time point when the data are output from the first memory cell array112to a time point when data are output from the first memory die110, and an interval from a time point when the data are output from the first memory die110to a time point when data are output from the buffer die120.

The calibration unit127may count a latency of a first path Path1(illustrated by an alternate long and short dash line), which includes a path from the buffer die120to the first FIFO unit116and a path from the first FIFO unit116to the second FIFO unit126, and may generate the delay code. Based on the delay code generated by the calibration unit127, the second delay control circuit122may delay the second internal read signal IRS2and may generate the second control signal CTRL2, so that the area of the second FIFO unit126is minimized and the depth of the second FIFO unit126is not more than 2. For example, the first path may indicate a path in which any signal generated by the second command decoder121passes through the second delay control circuit122, the third through silicon via, the first memory die110, and the second through silicon via. Only the first path between the first memory die110and the buffer die120is illustrated inFIG. 2, but the memory device100may further include any other path between any one of the remaining memory dies and the buffer die120. The calibration unit127may generate the delay code in further consideration of a latency of the other path.

FIG. 3is a block diagram illustrating a buffer die and a memory die of the memory device ofFIG. 1according to example embodiments.FIG. 3will be described with reference toFIGS. 1 and 2. A memory device200may include a first memory die210and a buffer die220. The memory device200may be the memory device11ofFIG. 1, the first memory die210may be the first memory die11_1ofFIG. 1, and the buffer die220may be the buffer die11_9ofFIG. 1. The first memory die210may include a first command decoder211, a first memory cell array212, a first delay control circuit213, and a first FIFO unit216. Operations of components in the first memory die210may be identical to operations of the components in the first memory die110ofFIG. 2, which have similar reference numerals.

The buffer die220may include a second command decoder221, a second delay control circuit222, an output control circuit223, a second FIFO unit226, and a calibration unit227. Operations of components in the buffer die220may be identical to operations of the components in the buffer die120ofFIG. 2, which have similar reference numerals.

The first memory die210may further include first and second shift registers218_1and218_2. The first and second shift registers218_1and218_2may respectively shift the first and second control signals CTRL1and CTRL2and may generate delayed signals. The first FIFO unit216may sequentially sample bits of data output from the first memory cell array212by using delayed signals which the first control signal CTRL1is shifted. The first FIFO unit216may sequentially output the sampled bits of the data by using delayed signals which the second control signal CTRL2is shifted.

The buffer die220may further include third and fourth shift registers228_3and228_4. The third and fourth shift registers228_3and228_4may shift the second control signal CTRL2, which is transmitted through the second through silicon via, and the output control signal CTRL_OUT, respectively. The third and fourth shift registers228_3and228_4may generate delayed signals, respectively. The second FIFO unit226may sequentially sample bits of data output from the first FIFO unit216by using delayed signals which the second control signal CTRL2transmitted through the second through silicon via is shifted. The second FIFO unit226may sequentially output the sampled bits of the data by using delayed signals which the output control signal CTRL_OUT is shifted.

In example embodiments, the second shift register218_2may be disposed between the second delay control circuit222and the third through silicon via. In this case, the third shift register228_3may be omitted. For example, the second control signal CTRL2transmitted through the second through silicon via directly transmits to the second FIFO unit226.

FIG. 4is a block diagram illustrating a first FIFO unit ofFIG. 2 or 3.FIG. 4will be described with reference toFIG. 3. The first FIFO unit216may include first to fourth input switches SWI1to SWI4, first to fourth latches L1to L4, and first to fourth output switches SWO1to SWO4. In an embodiment, an example is illustrated inFIG. 4as the depth of the first FIFO unit216is “4”. The number of input switches, the number of latches, and the number of output switches may be determined depending on the depth of the first FIFO unit216.

The first to fourth input switches SWI1to SWI4may be turned on sequentially depending on first to fourth input control signals CTRL11to CTRL14. The first to fourth input control signals CTRL11to CTRL14are signals generated by shifting the first control signal CTRL1at the first shift register218_1. The first to fourth latches L1to L4may sequentially store data bits. The first to fourth output switches SWO1to SWO4may be turned on sequentially depending on first to fourth output control signals CTRL21to CTRL24. The first to fourth output control signals CTRL21to CTRL24are signals generated by shifting the second control signal CTRL2transmitted through the second through silicon via at the second shift register218_2. The first to fourth latches L1to L4may sequentially output stored or sampled data bits. In an embodiment, the second FIFO unit226may be implemented to be similar to the first FIFO unit216. However, as described above, the depth of the second FIFO unit226may be smaller than the depth of the first FIFO unit216.

FIG. 5is a block diagram illustrating a calibration unit ofFIG. 2 or 3according to an embodiment of the inventive concept.FIG. 5will be described with reference toFIGS. 2 and 3. The calibration unit227(or,127) may include an inverter227_1, a flip-flop227_2, an AND gate227_3, a counter227_4, and a subtractor227_5.

The inverter227_1may invert a measurement mode enable signal MEAS_MODE_EN indicating a measurement mode being a test mode of the memory device200. For example, the measurement mode enable signal MEAS_MODE_EN may be activated when the memory device100or200powers up. The flip-flop227_2may output logic “1”, for example, when the measurement mode enable signal MEAS_MODE_EN is activated. When receiving a delay clock signal DCK, which a clock signal CK is delayed, through a reset terminal, the flip-flop227_1may reset an output. For example, the flip-flop227_2may be reset to logic “0” when the delay clock signal DCK has a logic “1”. Depending on a logical value of the output of the flip-flop227_2, the AND gate227_3may output the clock signal CK or may not output the clock signal CK. When the measurement mode enable signal MEAS_MODE_EN is activated in the measurement mode, the AND gate227_3may provide the clock signal CK to the counter227_4and constitute the first path. The first path ofFIG. 5is identical to the first path ofFIG. 2.

In an embodiment, the clock signal CK may be input to the buffer die220from an outside of the buffer die220(e.g., the SoC13). The clock signal CK may be input to the buffer die220from the outside in synchronization with any signal (e.g., a CKE signal indicating a clock enable) input to the buffer die220in compliance with the JEDEC standard. In some examples, the clock signal CK may be generated by the second command decoder221which decodes a command, which indicates a measurement mode, such as a mode register set (MRS) command. In some examples, the clock signal CK may be generated within the buffer die220when the measurement mode enable signal MEAS_MODE_EN is activated. The clock signal CK may have the same period as an external clock signal input to a memory device200. The clock signal CK may be a pulse signal, the logical state of which is changed.

In an embodiment, inFIG. 5, the numbers of inverters, the number of flip-flops, the number of AND gates, a logic state of an output of the flip-flop227_2, a phase of an output of the AND gate227_3, etc. are only exemplary. The calibration unit227may further include any other logic gates which perform any other operations (e.g., NAND, NOR, OR, XOR, and XNOR operations), in addition to logic gates illustrated inFIG. 5.

The counter227_4may count an interval from a time when the clock signal CK is received to a time when the delay clock signal DCK transmitted through the first path is received. When receiving the clock signal CK, the counter227_4may start a counting operation. When the flip-flop227_2is reset by the delay clock signal DCK, the counter227_4may stop the counting operation. For example, the counter227_4may count a delay of the clock signal CK transmitted through the first path.

Referring toFIG. 5, the second delay control circuit222, the third through silicon via, and one of the first and second through silicon vias may be included in the first path, but components, which are included in the first path, of the buffer die220and the first memory die210are not limited to this disclosure. For example, the second control signal CTRL2may be transmitted to the first through silicon via through one or more switches when the first path includes the first through silicon via. When the measurement mode enable signal MEAS_MODE_EN is activated, the second delay control circuit222may not delay the clock signal CK based on the delay code described with reference toFIG. 2.

In detail, when the measurement mode enable signal MEAS_MODE_EN is not activated, the second delay control circuit222may receive the second internal read signal IRS2and may delay the second internal read signal IRS2depending on the delay code as much as a multiple of a clock. When the measurement mode enable signal MEAS_MODE_EN is activated, the second delay control circuit222may receive the clock signal CK and may not delay the clock signal CK regardless of the delay code.

In an embodiment, the first path may include any one of the first and second through silicon vias. The calibration unit227may select one of the first and second through silicon vias by using a through silicon via (TSV) enable signal TSV EN. The clock signal CK may pass through the first through silicon via through which data are transmitted, or may pass through the second through silicon via through which the second control signal CTRL2for sampling data is transmitted. As described above, since a path of transmitting data and a path of transmitting the second control signal CTRL2are identically implemented for the uniform capture margin, even though the clock signal CK passes through any one of the first and second through silicon vias, a delay amount of the delay clock signal DCK may be identically maintained.

The subtractor227_5may calculate the delay code ofFIGS. 2 and 3by subtracting a counting value of the counter227_4from a value RL indicating a read latency in advance determined. The value RL indicating the read latency in advance determined may be a value obtained by dividing the read latency by one period of a clock and may be in advance stored in the buffer die220. The delay code which is an output of the subtractor227_5may correspond to the depth of the first FIFO units116and216, and the counting value of the counter227_4may correspond to the depth of the second FIFO units126and226.

In an embodiment, a value of the delay code may be set to a value which is obtained by subtracting the counting value of the counter227_4from the value RL indicating the read latency in advance determined. In another embodiment, the value of the delay code may be set to at least one of values in advance stored in a fuse array, regardless of the counting value. The fuse array may be implemented with various nonvolatile memories such as an electrically programmable fuse, a laser programmable fuse, an anti-fuse, and a flash memory. That is, the value of the delay code may be set based on the counting value, or may be set to a value determined in advance.

FIG. 6is a block diagram illustrating a calibration unit ofFIG. 2 or 3according to another embodiment of the inventive concept.FIG. 6will be described with reference toFIGS. 2, 3, and 5. A calibration unit327may include an inverter327_1, a flip-flop327_2, an AND gate327_3, a counter327_4, and a subtractor327_5. Operations of components in the calibration unit327ofFIG. 6may be identical to operations of the components in the calibration unit227ofFIG. 5, which have similar reference numerals.

Compared with the calibration unit227ofFIG. 5, the calibration unit327may further include command replica paths327_6and327_7and data replica paths327_8and327_9. The command replica paths327_6and327_7and the data replica paths327_8and327_9are circuits obtained by identically modeling the first path ofFIGS. 2 and 5.

In detail, the command replica path327_6may be obtained by modeling a path through which a signal generated by the buffer die120depending on the read command is transmitted to the first memory die110. The command replica path327_7may be obtained by modeling a path through which a signal transmitted from the buffer die120depending on the read command is transmitted to the first FIFO unit116. The data replica path327_8may be obtained by modeling a path through which data of the first FIFO unit116are transmitted to the buffer die120. The data replica path327_9may be obtained by modeling a path through which data transmitted from the first FIFO unit116are transmitted to the second FIFO unit126. For example, the calibration unit327may directly transmit the clock signal CK to the first path, or may transmit the clock signal CK to a modeling circuit of the first path.

FIG. 7is a block diagram illustrating a buffer die, a first memory die, and a second memory die of a memory device ofFIG. 1according to example embodiments. A memory device400may include a first memory die410, a second memory die430, and a buffer die420. The memory device400may be the memory device11ofFIG. 1, the first memory die410may be the first memory die11_1ofFIG. 1, the second memory die430may be the second memory die11_2ofFIG. 1, and the buffer die420may be the buffer die11_9ofFIG. 1. The first memory die410may include a first command decoder411, a first memory cell array412, a first delay control circuit413, and a first FIFO unit416. The second memory die430may be implemented substantially identically to the first memory die410. The second memory die430may include a third command decoder431, a second memory cell array432, a third delay control circuit433, and a third FIFO unit436. Operations of components in the first and second memory dies410and430may be identical to operations of the components in the first memory die110ofFIG. 2, which have similar reference numerals.

The buffer die420may include a second command decoder421, a second delay control circuit422, an output control circuit423, a second FIFO unit426, and a calibration unit427. Operations of components in the buffer die420may be identical to operations of the components in the buffer die120ofFIG. 2, which have similar reference numerals.

The second memory die430may be stacked on the first memory die410. The second memory die430may be any one of the second to eighth memory dies11_2to11_8ofFIG. 1. The first memory die410may receive addresses from the buffer die420through the sixth through silicon via. The second memory die430may receive the same addresses as addresses which the first memory die410receives through the sixth through silicon via and at least one ninth through silicon via from the buffer die420. For example, the first memory die410and the second memory die430may support the same channel. In this case, the second memory die430may be the fifth memory die11_5ofFIG. 1.

The third command decoder431may decode a read command transmitted from the buffer die420. The second memory cell array432may output second data under control of the third command decoder431(i.e., in response to the read command). The third delay control circuit433may generate a third control signal CTRL3, based on a third internal read signal IRS3of the third command decoder431.

The third FIFO unit436may sample the second data, based on the third control signal CTRL3. The third FIFO unit436may output the sampled data, based on a fourth control signal CTRL4transmitted from the buffer die420through the third through silicon via and at least one eighth through silicon via. The sampled data may be transmitted to the second FIFO unit426of the buffer die420through at least one fourth through silicon via TSV4and the first through silicon via. For example, the first and second memory dies410and430constituting (or supporting) the same channel may share the first through silicon via for a data output. The fourth control signal CTRL4may be transmitted to the second FIFO unit426of the buffer die420through at least one fifth through silicon via TSV5and a seventh through silicon via TSV7.

In an embodiment, for a communication between the second memory die430and the buffer die420, through silicon vias may be interposed between the second memory die430and the buffer die420. Also, the number of the at least one fourth through silicon via, the number of the at least one fifth through silicon via, the number of the at least one eighth through silicon via TSV8, and the number of the at least one ninth through silicon via TSV9may be determined depending on the number of memory dies stacked between the buffer die420and the second memory die430.

The second FIFO unit426of the buffer die420may sample first data of the first FIFO unit416, based on the second control signal CTRL2transmitted through the second through silicon via. The second FIFO unit426may sample the second data transmitted from the third FIFO unit436through the at least one fourth through silicon via and the first through silicon via, based on the fourth control signal CTRL4transmitted from the second memory die430through the at least one fifth through silicon via and the seventh through silicon via.

The calibration unit427may receive the second control signal CTRL2passing through the first path (not illustrated) (refer toFIG. 1) and may receive the fourth control signal CTRL4passing through a second path Path2(illustrated by an alternated long and short dash line) from the buffer die420to the third FIFO unit436and from the third FIFO unit436to the second FIFO unit426. Similar to the first path ofFIG. 5, the second path may further include the at least one eighth through silicon via and any one of the at least one fourth through silicon via and the at least one fifth through silicon via as the second memory die430is stacked on the first memory die410, and may be longer than the first path.

The calibration unit427may generate a delay code based on a further delayed signal of the second and fourth control signals CTRL2and CTRL4. Since the calibration unit427uses the further delayed signal of the second and fourth control signals CTRL2and CTRL4, a time point when the first data are output from the first memory die410and a time point when the second data are output from the second memory die430may be identically set. Although not illustrated inFIG. 7, in the case where more memory dies are stacked on the buffer die420compared with this disclosure, the calibration unit427may generate a delay code based on the latest delayed signal of respective control signals of the stacked memory dies.

The second delay control circuit422may generate the second control signal CTRL2, based on the read command and the delay code. The second control signal CTRL2may be transmitted to the first memory die410through the third through silicon via, and may be transmitted to the second memory die430through the third through silicon via and the at least one eighth through silicon via. For example, the fourth control signal CTRL4may be identical to the second control signal CTRL2.

In example embodiments, each of the fourth, fifth, eighth and ninth through silicon vias ofFIG. 7may penetrate the first memory die410or the second memory die430.

FIG. 8is a block diagram illustrating a calibration unit ofFIG. 7according to example embodiments. Referring toFIG. 8, the calibration unit427may include an inverter427_1, a flip-flop427_2, an AND gate427_3, a counter427_4, and a subtractor427_5. Operations of components in the calibration unit427may be identical to operations of the components in the calibration units227and327ofFIGS. 5 and 6, which have similar reference numerals.

The calibration unit427may further include a compare unit427_6. The compare unit427_6may provide the flip-flop427_2with a further delayed signal of a first delay clock signal DCK1passing through the first path and a second delay clock signal DCK2passing through the second path. The compare unit427_6may include an OR gate which performs an OR operation on the first delay clock signal DCK1and the second delay clock signal DCK2. The counter427_4may count an interval from a time when the clock signal CK is received to a time when the flip-flop427_2receives a further delayed signal of the first and second delay clock signals DCK1and DCK2.

Referring toFIG. 8, the first path may include the second delay control circuit422, the third through silicon via, and any one of the first through silicon via and the second through silicon via, and may be identical to the first path ofFIGS. 2 and 5. The memory device400may select one of the first and second through silicon vias by using a first through silicon via (TSV) enable signal TSV_EN1. The second path may include the second delay control circuit422, the third through silicon via, the eighth through silicon via and either the fourth through silicon via and the first through silicon via or the fifth through silicon via and the seventh through silicon via, and may be identical to the second path ofFIG. 7. The memory device400may select a path of either the fourth through silicon via and the first through silicon via or the fifth through silicon via and the seventh through silicon via by using a second TSV enable signal TSV_EN2. Although not illustrated inFIG. 8, as inFIG. 6, the calibration unit427may include circuits obtained by modeling the first path and the second path.

In example embodiments, the calibration unit427may receive first to nth delay clock signals DCK1to DCKn when the memory device400includes n memory dies. Here, n is a natural number greater than 2.

FIG. 9is a block diagram illustrating a calibration unit ofFIG. 7.FIG. 9will be described with reference toFIG. 8according to example embodiments. The calibration unit427may further include delay circuits427_7, an OR gate427_8, and flip-flops427_9, in addition to the components ofFIG. 8.

The calibration unit427may include the serially connected delay circuits427_7. The delay circuits427_7may delay the internal read signal IRS2ofFIG. 7and may output delay internal read signals DIRS1to DIRS3. The OR gate427_8may provide the flip-flops427_9with a further delayed clock signal of the first delay clock signal DCK1and the second delay clock signal DCK2. The flip-flops427_9may compare the further delayed clock signal of the first delay clock signal DCK1and the second delay clock signal DCK2with the delay internal read signals DIRS1to DIRS3and may output a delay enable code DLYEN[1:4].

The calibration unit427may determine whether to calculate the delay code ofFIG. 8by using the counting value based on the delay enable code DLYEN[1:4] or whether to determine the delay code ofFIG. 8as at least one of values in advance stored in a fuse array. For example, in the case where the further delayed clock signal of the first delay clock signal DCK1and the second delay clock signal DCK2is prior to the delay internal read signals DIRS1to DIRS3, the calibration unit427may calibrate the delay code ofFIG. 8as at least one of the values in advance stored in the fuse array. The numbers of the delay circuits427_7and the flip-flops427_9are not limited to illustration ofFIG. 9.

FIG. 10is a block diagram illustrating a buffer die, a first memory die, and a second memory die of a memory device ofFIG. 1according to example embodiments. A memory device400may include a first memory die410, a second memory die430, and a buffer die420. The first memory die410and the second memory die430ofFIG. 10may be identical to the first memory die410and the second memory die430ofFIG. 7.

The buffer die420ofFIG. 10may further include second delay control circuits422_1and422_2compared with the buffer die420ofFIG. 7. Each of the second delay control circuits422_1and422_2may be implemented identically to the second delay control circuit422ofFIG. 7.

The second delay control circuit422_1may generate the second control signal CTRL2to be transmitted to the first memory die410through the third through silicon via, based on the read command and the delay code. The second delay control circuit422_2may generate the fourth control signal CTRL4to be transmitted to the second memory die430through a tenth through silicon via TSV10and the at least one eighth through silicon via, based on the read command and the delay code. For example, the second control signal CTRL2and the fourth control signal CTRL4may be respectively generated by independent delay control circuits and may be respectively transmitted through independent paths.

FIG. 11is a block diagram illustrating a buffer die, a first memory die, and a second memory die of a memory device ofFIG. 1according to example embodiments. A memory device500may include a first memory die510, a second memory die530, and a buffer die520. The memory device500may be the memory device11ofFIG. 1, the first memory die510may be the first memory die11_1ofFIG. 1, the second memory die530may be the second memory die11_2ofFIG. 1, and the buffer die520may be the buffer die11_9ofFIG. 1. The first memory die510may include a first command decoder511, a first memory cell array512, a first delay control circuit513, a first FIFO unit516, and a first compare unit519. Operations of components in the first memory die510may be identical to operations of the components in the first memory die410ofFIG. 7, which have similar reference numerals. The second memory die530may include a third command decoder531, a second memory cell array532, a third delay control circuit533, a third FIFO unit536, and a second compare unit539. Operations of components in the second memory die530may be identical to operations of the components in the second memory die430ofFIG. 7, which have similar reference numerals. For brevity of drawing, illustration of through silicon vias between the first FIFO unit516, the third FIFO unit536, and a buffer die520are skipped.

The first compare unit519may determine a further delayed control signal of the first control signal CTRL1and the third control signal CTRL3transmitted from the second memory die530through at least one twelfth through silicon via and may generate a first delay code by counting the further delayed control signal. The second compare unit539may determine a further delayed control signal of the third control signal CTRL3and the first control signal CTRL1transmitted from the first memory die510through at least one eleventh through silicon via TSV11and may generate a third delay code by counting the further delayed control signal. Each of the first compare unit519and the second compare unit539may include an OR gate which performs an OR operation on the first control signal CTRL1and the third control signal CTRL3. The first and second memory dies510and530may share the first control signal CTRL1and the third control signal CTRL3through the at least one eleventh through silicon via and the at least one twelfth through silicon via TSV12.

A time difference may be present between the first control signal CTRL1and the third control signal CTRL3due to the PVT variation between the first memory die510and the second memory die530. Nevertheless, a calibration unit527may adjust a time point, at which the first data are output from the first FIFO unit516, and a time point, at which the second data are output from the third FIFO unit536, so as to be identical to each other by using the first and third delay codes.

The calibration unit527of the buffer die520may receive the first delay code through a fourteenth through silicon via TSV14, and may receive the third delay code through at least one thirteenth through silicon via TSV13and a fifteenth through silicon via TSV15. The calibration unit527may generate a second delay code by further using the first and third delay codes, as well as a counting value which is based on a further delayed signal of the first and second delay clock signals DCK1and DCK2. A second delay control circuit522may generate the second and fourth control signals CTRL2and CTRL4, based on the second delay code.

In example embodiments, each of the eleventh, twelfth, and thirteenth through silicon vias ofFIG. 11may penetrate the first memory die510or the second memory die530.

FIG. 12is a block diagram illustrating a buffer die and a first memory die of a memory device ofFIG. 1according to example embodiments. A memory device600may include a first memory die610and a buffer die620. The memory device600may be the memory device11ofFIG. 1, the first memory die610may be the first memory die11_1ofFIG. 1, and the buffer die620may be the buffer die11_9ofFIG. 1. The first memory die610may include a first command decoder611, a first memory cell array612, a first delay control circuit613, a second delay control circuit614, and a first FIFO unit616. Operations of components in the first memory die610may be identical to operations of the components in the first memory die110ofFIG. 2, which have similar reference numerals. The buffer die620may include a second command decoder621, an output control circuit623, a second FIFO unit626, and a calibration unit627. Operations of components in the buffer die620may be identical to operations of the components in the buffer die120ofFIG. 2, which have similar reference numerals.

Returning toFIG. 2, the second delay control circuit122which generates the second control signal CTRL2may be positioned at the buffer die120. In contrast, referring toFIG. 12, the second delay control circuit614which generates the second control signal CTRL2may be positioned at the first memory die610. The calibration unit627may generate a delay code and may transmit the delay code to the second delay control circuit614through the third through silicon via. The second delay control circuit614may generate the second control signal CTRL2, based on the first internal read signal IRS1of the first command decoder611and the delay code. As in the first path ofFIG. 2, a first path Path1ofFIG. 12may include the third through silicon via, the second delay control circuit614, and any one of the first and second through silicon vias.

In example embodiments, the first memory die610may further include a first shift register618_1and a second shift register618_2(not shown). The first and second shift registers618_1and618_2may respectively shift the first and second control signals CTRL1and CTRL2and may generate delayed signals. The first FIFO unit616may sequentially sample bits of data output from the first memory cell array612by using the delayed signal in which the first control signal CTRL1is shifted. The first FIFO unit616may sequentially output the sampled bits of the data by using the delayed signal in which the second control signal CTRL2is shifted.

In example embodiments, the buffer die620may further include third and fourth shift registers628_3and628_4(not shown). The third and fourth shift registers628_3and628_4may shift the second control signal CTRL2, which is transmitted through the second through silicon via, and the output control signal CTRL_OUT, respectively. The third and fourth shift registers628_3and628_4may generate delayed signals, respectively. The second FIFO unit626may sequentially sample bits of data output from the first FIFO unit616by using the delayed signal in which the second control signal CTRL2transmitted through the second through silicon via is shifted. The second FIFO unit626may sequentially output the sampled bits of the data by using the delayed signal in which the output control signal CTRL_OUT is shifted.

FIG. 13is a block diagram illustrating a buffer die, a first memory die, and a second memory die of a memory device ofFIG. 1according to example embodiments. A memory device700may include a first memory die710, a second memory die730and a buffer die720. The memory device700may be the memory device11ofFIG. 1, the first memory die710may be the first memory die11_1ofFIG. 1, the second memory die730may be the second memory die11_2ofFIG. 1, and the buffer die720may be the buffer die11_9ofFIG. 1. The first memory die710may include a first command decoder711, a first memory cell array712, a first delay control circuit713, a second delay control circuit714, and a first FIFO unit716. The second memory die730may be implemented substantially identically to the first memory die710. A second memory die730may include a third command decoder731, a second memory cell array732, a third delay control circuit733, a fourth delay control circuit734, and a third FIFO unit736. Operations of components in the first and second memory dies710and730may be identical to operations of the components in the first memory die610ofFIG. 12, which have similar reference numerals, or to operations of the components in the first and second memory dies410and430ofFIG. 7, which have similar reference numerals.

The buffer die720may include a second command decoder721, an output control circuit723, a second FIFO unit726, and a calibration unit727. Operations of components in the buffer die720may be identical to operations of the components in the buffer dies420and620ofFIGS. 7 and 12, which have similar reference numerals.

Referring toFIG. 13, the first memory die710may include the second delay control circuit714which generates the second control signal CTRL2, and the second memory die730may include the fourth delay control circuit734which generates the fourth control signal CTRL4. The calibration unit727of the buffer die720may transmit the delay code to the second delay control circuit714through the third through silicon via, and may transmit the delay code to the fourth delay control circuit734through the third through silicon via and the at least one eighth through silicon via. As in the second path ofFIG. 7, the second path may include the third through silicon via, the at least one eighth through silicon via, the fourth delay control circuit734, and any one of the at least one fifth through silicon via to the seventh through silicon via and the at least one fourth through silicon via to the first through silicon via.

In example embodiments, each of the fourth, fifth, eighth and ninth through silicon vias ofFIG. 13may penetrate the first memory die710or the second memory die730.

FIG. 14is a block diagram illustrating first and second memory dies ofFIG. 1according to example embodiments. A memory device800may include a first memory die810, a second memory die830and a buffer die. The memory device800may be the memory device11ofFIG. 1, the first memory die810may be the first memory die11_1ofFIG. 1, and the second memory die830may be the second memory die11_2ofFIG. 1. InFIG. 14, illustration of the buffer die is skipped. The first memory die810may include a first command decoder811, a first memory cell array812, a first delay control circuit813, a second delay control circuit814, a first FIFO unit816, and a first compare unit819. The second memory die830may be implemented substantially identically to the first memory die810. A second memory die830may include a third command decoder831, a second memory cell array832, a third delay control circuit833, a fourth delay control circuit834, a third FIFO unit836, and a second compare unit839. Operations of components in the first and second memory dies810and830may be identical to operations of the components in the memory dies510,530,710, and730ofFIGS. 11 and 13, which have similar reference numerals.

Since the second and fourth delay control circuits814and834are respectively positioned at the first and second memory dies810and830, the first compare unit819may provide the second delay control circuit814with a first delay code without using a through silicon via, and the second compare unit839may also provide the fourth delay control circuit834with the third delay code without using a through silicon via. The second delay control circuit814may generate the second control signal CTRL2by using the first delay code of the first compare unit819and a second delay code of a calibration unit (not illustrated) in the buffer die. The fourth delay control circuit834may generate the fourth control signal CTRL4by using the third delay code of the second compare unit839and the second delay code of the calibration unit (not illustrated) in the buffer die.

FIG. 15is a timing diagram illustrating an operation in which data are output from memory devices ofFIGS. 2 to 14according to example embodiments. The memory devices100to800ofFIGS. 2 to 14may operate depending on the timing diagram ofFIG. 15. However, for convenience of description,FIG. 15will be described with reference toFIG. 2.

At a time point T1, the memory device100may receive a read command synchronized with the clock signal CK input from an external source such as the SoC13inFIG. 1. After the time point T1, the memory device100may further receive read commands with intervals of CCD. InFIG. 15, in an embodiment, the CCD interval is illustrated as being “1×tCK”, and the CCD is “1”. Here, “tCK” indicates a period of the clock signal CK.

At a time point T2, the first delay control circuit113of the first memory die110may generate the first control signal CTRL1. As an interval between the time points T1and T2, “a” may indicate an interval from a time point when the read command is input to the memory device100to a time point when the first control signal CTRL1is generated. After the time point T2, data (e.g., D1, D2, and D3) may be output from the first memory cell array110(i.e., a core). For example, an interval from a time point when the read command is input to the memory device100to a time point when data are output from the first memory cell array112may be “X×tCK”.

At a time point T3, the second delay control circuit122of the buffer die120may generate the second control signal CTRL2. An interval from a time point when a time corresponding to “X×tCK” elapses from the time point T1to a time point when the second control signal CTRL2is generated may be “b”. After the time point T3, data (e.g., D1, D2, and D3) may be output from the first FIFO unit116.

After the time point T3, the output control circuit123may generate the output control signal CTRL_OUT. The second FIFO unit126may output the data (e.g., DQ1, DQ2, and DQ3) to the outside as the DQ (“DWORD). An interval from a time point when a time corresponding to a read latency RL elapses from the time point T1to a time point when the output control signal CTRL_OUT is generated may be “c”. For example, the read latency RL may be in advance defined in compliance with a protocol between a memory device and a SoC, a JEDEC standard, etc.

First, the margin of the first FIFO unit116will be described. A data input time point of the first FIFO unit116should be prior to a data output time point of the first FIFO unit116. Accordingly, the following Equation 1 may be established. “amax” indicates a maximum interval of “a”. “bmax” indicates a maximum interval of “b”.
amax<bmax+X×tCK[Equation 1]

Also, the data output time point of the first FIFO unit116should be prior to the data input time point of the first FIFO unit116depending on a next read command. Accordingly, the following Equation 2 may be established. “amin” indicates a minimum interval of “a”. “bmin” indicates a minimum interval of “b”. “n” may indicate the depth of the first FIFO unit116.
bmin+X×tCK<amin+n×CCD×tCK[Equation 2]

Next, the margin of the second FIFO unit126will be described. A data input time point of the second FIFO unit126should be prior to a data output time point of the second FIFO unit126. Accordingly, the following Equation 3 may be established. “cmax” indicates a maximum interval of “c”.
bmax<cmax+(RL−X)×tCK[Equation 3]

Also, the data output time point of the second FIFO unit126should be prior to the data input time point of the second FIFO unit126depending on a next read command. Accordingly, the following Equation 4 may be established. “cmin” indicates a minimum interval of “c” “m” may indicate the depth of the second FIFO unit126.
cmin+(RL−X)×tCK<bmin+m×CCD×tCK[Equation 4]

When Equation 1 and Equation 3 are summarized, a condition of “tCKmin” may be derived as shown in Equation 5. Referring to Equation 5, “tCKmin”, which is a minimum period of a clock of the memory device100, may be determined based on “X”, which indicates a time taken for the first memory cell array112to output data in response to the read command.

When Equation 2 and Equation 4 are summarized, a condition of “tCKmax” may be derived as shown in Equation 6. When “X” which is needed to obtain “tCKmin” is determined, the depths “n” and “m” of the first and second FIFO units116and126may be determined without a limitation on “tCKmax”.

To remove the limitation on “tCKmax”, “n” indicating the depth of the first FIFO unit116should be greater than “X/CCD”, and the depth of the second FIFO unit126should be greater than “(RL−X)/CCD”. When “m” increases, the area of the second FIFO unit126may become larger. However, as described above, there is a limitation on the area of the physical layer12in the buffer die11_9ofFIG. 1, in which the second FIFO unit126is positioned. Accordingly, according to an embodiment of the inventive concept, “n” and “X” may be adjusted instead of “m”. Here, “m” may be fixed to not more than 2. In detail, “X” may vary with “tCK” and a value of “bmin−cmin”. For example, as “tCK” decreases and the value of “bmin−cmin” increases, “RL−X” may increase. In contrast, as “tCK” increases and the value of “bmin−cmin” decreases, “RL−X” may decrease.

According to an embodiment of the inventive concept, data and a signal for sampling may be transmitted from a memory die to a buffer die through TSVs. Accordingly, a capture margin between the data and the signal for sampling may be uniformly maintained.

According to another embodiment of the inventive concept, output time points of data output from memory dies may be identically adjusted.

According to another embodiment of the inventive concept, a FIFO unit positioned at the buffer die may be minimized.