POWER GATING USING NANOELECTROMECHANICAL SYSTEMS (NEMS) IN BACK END OF LINE (BEOL)

One aspect of the present disclosure pertains to a device. The device includes a substrate, a logic circuit disposed on the substrate, and a nanoelectromechanical systems (NEMS) device electrically connected to the logic circuit and formed on the substrate. The NEMS device includes a first electrode electrically connected to the logic circuit, a second electrode electrically connected to a first power supply, a movable feature electrically connected to the second electrode, and a control electrode operable to move the movable feature relative to the first electrode.

BACKGROUND

The electronics industry has experienced an ever-increasing demand for smaller and faster electronic devices that are simultaneously able to support a greater number of increasingly complex and sophisticated functions. To meet these demands, there is a continuing trend in the integrated circuit (IC) industry to manufacture low-cost, high-performance, and low-power ICs. Thus far, these goals have been achieved in large part by reducing IC dimensions (for example, minimum IC feature size), thereby improving production efficiency and lowering associated costs. However, such scaling has also increased complexity of the IC manufacturing processes. Thus, realizing continued advances in IC devices and their performance requires similar advances in IC manufacturing processes and technology.

As technology nodes become smaller, issues with leakage power become more pronounced. Leakage power refers static power consumed while the circuit is inactive or idle. In a CMOS circuit, even when transistors are turned off, leakage power is dissipated as leakage current flow from input power to ground. One technique in reducing power leakage is with power gating. Power gating refers to turning off functional blocks of an IC when they are not being used or when they are in an inactive mode. Power gating may be implemented through one or more gating transistors that disconnect the path between power supply (VDD) and ground (VSS). These gating transistors may be n-type or p-type header transistors that gate the VDD rails or n-type or p-type footer transistors that gate the VSS rails.

However, the gating transistors take up additional footprint in front end of line (FEOL) portions of the IC. This means that they will compete for space with neighboring logic device components. Further, these gating transistors may still exhibit some leakage current in the off state. Even further, using n-type transistors may induce headroom loss (voltage drop) for the virtual VDD when the circuit path is turned on, while using p-type transistors means lower driving capability than that of the n-type transistors.

Therefore, although existing methods and structures for power gating have been generally adequate for their intended purposes, they have not been entirely satisfactory in every aspect.

DETAILED DESCRIPTION

Further, when a number or a range of numbers is described with “about,” “approximately,” “substantially,” and the like, the term is intended to encompass numbers that are within a reasonable range considering variations that inherently arise during manufacturing as understood by one of ordinary skill in the art. For example, the number or range of numbers encompasses a reasonable range including the number described, such as within +/−10% of the number described, based on known manufacturing tolerances associated with manufacturing a feature having a characteristic associated with the number. For example, a material layer having a thickness of “about 5 nm” can encompass a dimension range from 4.5 nm to 5.5 nm where manufacturing tolerances associated with depositing the material layer are known to be +/−10% by one of ordinary skill in the art. And when comparing a dimension or size of a feature to another feature, the phrases “substantially the same,” “essentially the same,” “of similar size,” and the like, can be understood to be within +/−10% between the compared features. Further, disclosed dimensions of the different features can implicitly disclose dimension ratios between the different features. Still further, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

The present disclosure relates to semiconductor structures having an integrated NEMS device for power gating control. The NEMS device controls when to turn on and turn off a supply voltage (VDD) to a functional circuit, such as a logic circuit or a memory circuit. The NEMS device includes an input terminal, an output terminal, and a control terminal. In an embodiment, when a control voltage is applied to the control terminal, the NEMS device is turned on, thereby allowing current to flow from the input terminal to the output terminal such that the supply voltage VDD is applied at the output terminal and to a functional circuit.

In various embodiments, the present disclosure describes incorporating the NEMS device in the back end of line (BEOL). Since the NEMS devices are formed in the BEOL, power gating footprint in the front end of line (FEOL) is eliminated. For example, transistor regions in FEOL previously reserved for forming power gating transistors are removed and replaced with additional functional devices. FEOL generally refers to portions of the circuit where functional devices such as logic devices are formed. The FEOL generally includes everything up to but not including metal interconnect layers. These regions may include the substrate, source/drain features, active regions, gate, and device-level contacts. BEOL generally refers to circuit regions outside of the FEOL. These regions may include the metal interconnect layers, backside of the substrate, or another wafer as part of a 3DIC structure. Besides eliminating FEOL footprint, the present disclosure offers other advantages in power gating. Since the NEMS devices do not need to be formed in the FEOL, it can be formed in various places in the BEOL, allowing flexibility. Further, by using NEMS devices, there is no headroom loss when the circuit path is turned on (no VDD voltage drop). Further, in the off state, the NEMS device is physically off due to the mechanical switching nature of the NEMS device, so there is no leakage current. Further, various types of NEMS devices are provided, where at low additional cost, they allow for process easiness and high CMOS logic compatibility. The various types of NEMS devices may include cantilever NEMS devices, piezoelectric NEMS devices, vertical NEMS devices, in-plane NEMS devices, and comb structure NEMS devices.

FIG.1illustrates a circuit schematic of a semiconductor structure100having a nanoelectromechanical systems (NEMS) device200for power gating, according to an embodiment of the present disclosure. The semiconductor structure100may include one or more semiconductor devices that form one or more circuit structures. As shown, the semiconductor structure100includes a NEMS device200electrically connected to a functional circuit such as a logic circuit300. In another embodiment, the functional circuit may be a memory circuit. As shown, the NEMS device200acts as a switch. When the switch is turned on, power (e.g., supply voltage VDD) is supplied to the logic circuit300. When the switch is turned off, power is not supplied to the logic circuit300. Note that inside the logic circuit300, there may also be transistor switches that switch on or off depending on if the logic circuit300is in operation. In any case, if the logic circuit is not being used or is in an idle state, the NEMS device physically cuts off supply voltage to the logic circuit,

Still referring toFIG.1, the NEMS device200may be a three-terminal device that includes an input terminal D, a control terminal G, and an output terminal S. The input terminal D functionally represents a drain terminal, which is electrically connected to a power supply (e.g., supply voltage VDD). The control terminal G functionally represents a gate terminal, which is electrically connected to a control voltage (not shown). And the output terminal S functionally represents a source terminal, which is electrically connected to the logic circuit300. The output terminal S corresponds to virtual power supply (e.g., virtual VDD), which supplies power to the logic circuits300depending on the operation of the NEMS device200. The virtual power supply may supply voltage to a drain of a logic device in the logic circuit300, and a source of a logic device in the logic circuit300may be electrically connected ground (e.g., VSS).

For ease of description, various electrodes that correspond to the input, control, and output terminals D, G, and S are similarly labeled inFIGS.2A-7. The electrodes are similarly referred to as an input electrode D, a control electrode G, and an output electrode S. Note that the mechanics described inFIG.1may equally apply to the various semiconductor structures100inFIGS.2A-7.

FIGS.2A-2Billustrates a semiconductor structure100having a NEMS device200, according to various embodiments of the present disclosure.FIGS.2A-2Billustrates a cantilever NEMS device200having an input electrode D, a control electrode G, an output electrode S, and a movable feature208physically attached to the input electrode D. The cantilever NEMS device200is embedded in a larger semiconductor structure100as part of a BEOL process. The cantilever NEMS device200may be located in various BEOL locations, as described with respect toFIGS.3A-3C. An air gap250surrounds the cantilever NEMS device200and allows a bendable end of the movable feature208to move freely (i.e., bend down or bend up). The bendable end may bend at a bending angle between 3 degrees to 20 degrees relative to a horizontal direction. In an embodiment, the bending angle is between about 5 degrees to about 15 degrees. Note that the range of the bending angle is not trivial. If the bending angle is too small, the bending end may not contact the output electrode S, and if the bending angle is too large, the movable feature208may inadvertently contact the control electrode G. In the present embodiment, the bendable end is at the output electrode S. Note that in other embodiments, the input electrode D and the output electrode S may be switched such that the movable feature208is physically attached to the output electrode S and the bendable end is at the input electrode D. In any case, when the movable feature electrically connects the input electrode D to the output electrode S, supply voltage at the input electrode D is equal to the virtual voltage VDD at the output electrode S, which then supplies power to the logic circuit300. The input electrode D, the control electrode G, the output electrode S, and the movable feature may each include Cu, W, Pt, Ru, Al, Co TaN, TiN, or a combination thereof.

Referring now toFIG.2A, the cantilever NEMS device200is a normal-off device. In other words, when no control voltage is applied to the control electrode G, the movable feature208does not move and no power (i.e., supply voltage VDD) is supplied to the logic circuit300. And when control voltage is applied to the control electrode G, the movable feature208bends such that the movable feature208contacts the output electrode S and power (i.e., supply voltage VDD) is supplied to the logic circuit300. The movable feature208bends through electrostatic pull-in effect, where positive charges at the control electrode G attracts negative charges at the movable feature208(or vice versa). As shown, the movable feature has a movable end that bends down when control voltage is applied to the control electrode G. It may be desirable that the control voltage at the control electrode G be greater than the supply voltage VDD at the input electrode. This is so that the charge effect is dominated by the control voltage without being substantially affected by the supply voltage VDD. In an embodiment, the control voltage ranges between 2 volts to 10 volts, and the supply voltage VDD ranges between 0.6 volts to 1.2 volts. In the embodiment shown, the control electrode G and the control electrode S have coplanar (or substantially coplanar) top surfaces, and the input electrode D has a top surface above top surfaces of the control electrode G and the control electrode S. Further, the electrodes D, G, and S may have coplanar (or substantially coplanar) bottom surfaces.

Referring now toFIG.2B, the cantilever NEMS device200is a normal-on device. In other words, when no control voltage is applied to the control electrode G, the movable feature208contacts the output electrode S and power (i.e., supply voltage VDD) is supplied to the logic circuit300. And when control voltage is applied to the control electrode G, the movable feature208bends such that the movable feature208bends upwards to disconnect from the output electrode S and no power (i.e., supply voltage VDD) is supplied to the logic circuit300. Like inFIG.2A, the movable feature208bends through electrostatic pull-in effect, where positive charges at the control electrode G attracts negative charges at the movable feature208(or vice versa). As shown, the movable feature has a movable end that bends up when control voltage is applied to the control electrode G. Like inFIG.2A, it may be desirable that the control voltage at the control electrode G be greater than the supply voltage VDD at the input electrode. This is so that the charge effect is dominated by the control voltage without being substantially affected by the supply voltage VDD. In an embodiment, the control voltage ranges between 2 volts to 10 volts, and the supply voltage VDD ranges between 0.6 volts to 1.2 volts. In the embodiment shown, the input electrode D and the output electrode S have coplanar (or substantially coplanar) top surfaces, and the control electrode G is above the top surfaces of the input electrode D and output electrode S. The control electrode G is also above the movable feature208for a normal-on device. Further, the electrodes D and S may have coplanar (or substantially coplanar) bottom surfaces.

FIGS.3A-3Cillustrates cantilever NEMS devices200in various BEOL locations of a semiconductor structure100.FIGS.3A-3Cillustrates normal-off NEMS devices such as the one shown inFIG.2A. However, in other embodiments, normal-on devices such as the one shown inFIG.2Bmay be used.

Referring now toFIG.3A, the NEMS device200may be formed in or above a metal interconnect structure300bof a semiconductor structure100. The semiconductor structure100includes a substrate102, a logic circuit300over the substrate, and a NEMS device200electrically connected to the logic circuit300and formed on the substrate102. The substrate102may be a silicon (Si) substrate, or a substrate having other semiconductor materials such as germanium (Ge), silicon carbide (SiC), silicon germanium (SiGe), or diamond. The logic circuit300includes logic devices300aover the substrate102, an interconnect structure300bover the logic devices300a, and a passivation structure300cover the interconnect structure300b. The logic circuit300may also include a backside interconnect structure300don a backside of the substrate102. The backside interconnect structure300dmay electrically connect to the logic devices300athrough one or more through-substrate vias116.

Still referring toFIG.3A, the logic devices300aare formed in a transistor region of the semiconductor structure100as part of a FEOL process. There may be one or more through-device vias115that penetrates through the transistor region and the substrate102for direct connection between the backside interconnect structure300dand the interconnect structure300b. In an embodiment, the logic devices300aare functional devices for arithmetic, logic, controlling, and I/O operations. Each of the logic devices300amay include a field effect transistor (FET) having a channel region104between source/drain (S/D) epitaxial features106, a gate structure110over the channel region104, S/D contacts112over the S/D epitaxial features, and a gate contact112over the gate structure. In the embodiment shown, the channel region104includes a stack of semiconductor channels wrapped around by the gate structure110.

Still referring toFIG.3A, the interconnect structure300bis formed over the logic devices300a. The interconnect structure300bincludes features that electrically couple various devices (for example, transistors, resistors, capacitors, and/or inductors) and/or components (for example, gate structures and/or source/drain features of the logic devices300a), such that the various devices and/or components can operate as specified by design requirements. The interconnect structure300bincludes a combination of dielectric layers315such as interlayer dielectric (ILD) and/or intermetal dielectric (IMD) layers and electrically conductive layers. The conductive layers are configured to form vertical interconnect features, such as metal vias312, and/or horizontal interconnect features, such as conductive metal lines318. Vertical interconnect features typically connect horizontal interconnect features in different layers (or different planes) of the interconnect structure300b. During operation, the interconnect structure300bis configured to route signals between the logic devices300aand/or the components of the logic devices300aand/or distribute signals (for example, clock signals, voltage signals, and/or ground signals) to the logic devices300aand/or the components of the logic devices

Still referring toFIG.3A, the NEMS device200is formed in or above the interconnect structure300b. For example, the NEMS device200may be formed over a top metal line318of the interconnect structure300band landing on a top metal via312(as shown). For another example, the NEMS device200may be embedded and formed within the metal interconnect structure300b, such as vertically between metal lines318. The input, control, and output electrodes D, G, and S of the NEMS device200may be surrounded by a dielectric layer210. As shown, the control electrode G and output electrode S have top surfaces coplanar (or substantially coplanar) with a top surface of the dielectric layer210. And the top surface of the input electrode D protrudes above the top surface of the dielectric layer210and has a top portion exposed in an air gap250. The air gap250surrounds the NEMS device200such that the movable feature208of the NEMS device200can freely bend to connect and disconnect from the output electrode S. The input electrode D is electrically connected to a power supply (e.g., supply voltage VDD), the control electrode G is electrically connected to a control voltage, and the output electrode S is electrically connected to the logic devices300athrough the interconnect structure300b. The output electrode S is the VDD input to the logic devices300aand acts as a virtual VDD.

Still referring toFIG.3A, the passivation structure300cis formed over the interconnect structure300b. The passivation structure300cmay include redistribution layers and bonding pads surrounded by passivation layers. The redistribution layers and bonding pads may route electrical connections for package or die-level connections. Note that portions of the NEMS device200may be formed in the passivation structure300c(as shown). In other embodiments, the NEMS device200may be wholly formed in the passivation structure300c.

Still referring toFIG.3A, the NEMS device200is disposed above and vertically separated from the logic devices300a. In an embodiment, there may be 8 to 13 metal lines318between the NEMS device200and the logic devices300a. In the present embodiment, when no control voltage is applied, the movable feature208of the NEMS device200does not touch the output electrode S and supply voltage VDD is disconnected from the logic devices300a. When control voltage is applied to the control electrode G, the movable feature208of the NEMS device200bends and touches the output electrode S. Supply voltage VDD is then connected to the output electrode S and power is supplied to the logic devices300a.

The dielectric layers described herein (e.g., dielectric layers210and315) may include silicon oxide, a silicon oxide containing material, or a low-K dielectric layer such as TEOS oxide, undoped silicate glass (USG), or doped silicon oxide such as BPSG, FSG, PSG, BSG, and/or other suitable low-K dielectric material. Note that the dielectric layers210and315may each include multiple layers, but they are referred to as distinct layers for the sake of simplicity. One or more of the multiple layers may be a device-level interlayer dielectric (ILD) that embed and surround the logic devices300a. The passivation layers described herein may include silicon oxide, silicon nitride, or a suitable dielectric material. In various examples, the various dielectric and passivation layers may be deposited by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or combinations thereof.

Referring now toFIG.3B, the NEMS device200may be formed on a backside of a substrate102, according to an embodiment of the present disclosure. For example, the semiconductor structure100is flipped such that the substrate102is further processed from a backside. The processing may include forming a backside interconnect structure300dhaving backside metal lines and vias (not shown). As part of forming the backside interconnect structure300d, the NEMS device200may be formed on the backside of the substrate102opposite to the logic devices300a. As shown, when the movable feature208bends up to contact the output electrode S, supply voltage at the input electrode D is supplied from a backside of the substrate102to the output electrode S. Then, the supply voltage at the output electrode S powers the logic devices300athrough one or more through-substrate vias116. Note that one or more through-device vias115may electrically connect between the NEMS device200and the interconnect structure300b(e.g., between control electrode G and a metal line318of the interconnect structure300b). As such, control voltage may route from a frontside of the substrate102to the backside of the substrate via the through-device via115. In other respects, the semiconductor structure inFIG.3Bmay be similar to the semiconductor structure100inFIG.3A.

Referring now toFIG.3C, the NEMS device200may be formed as part of a 3DIC structure, according to an embodiment of the present disclosure. As shown, the semiconductor structure100is a 3D stacked semiconductor structure having two wafers or dies on top of each other. As shown, it is possible that the NEMS device200is formed in one wafer but electrically connects to a logic circuit formed in another wafer. In the embodiment shown, one wafer/die includes a logic circuit300having a substrate102, logic devices300aover the substrate102, and an interconnect structure300bover the logic devices300a. The logic circuit300may be similar to what has been described inFIGS.3A-3B. Another wafer/die includes a logic circuit400is disposed over the logic circuit300. The logic circuit400includes a substrate402, logic devices400aover the substrate402, and an interconnect structure400bover the logic devices400a. Each of the logic devices400amay include a field effect transistor (FET) having a channel region404between source/drain (S/D) epitaxial features406, a gate structure410over the channel region404, S/D contacts412over the S/D epitaxial features406, and a gate contact (not shown) over the gate structure410. In the embodiment shown, the channel region404includes a stack of semiconductor channels wrapped around by the gate structure410. The interconnect structure400bis connected to the logic devices400asimilar to how the interconnect structure300bconnects to the logic devices300a(e.g., via metal lines418). A dielectric layer415similar to the dielectric layer315may embed various features in the interconnect structure400band surrounding the logic devices400a.

Still referring toFIG.3C, the NEMS device200is formed as part of the logic circuit400. As shown, the NEMS device200is directly above both the substrate102and the substrate402. In an embodiment, supply voltage may be applied to the input electrode D through a through-substrate via416. When a control voltage is applied to the control electrode G, the movable feature208bends within the air gap250to contact the output electrode S, and the output electrode S receives the supply voltage. In an embodiment, the output electrode S then supplies the supply voltage to logic devices300ain the logic circuit300by routing through the interconnect structure300band other through-substrate vias416(not shown). In another embodiment, the output electrode S supplies the supply voltage to logic devices400ain the logic circuit400.

Although logic circuits300and400have been described with respect toFIGS.3A-3C, the present disclosure is not limited thereto. In other embodiments, the NEMS device200may perform power gating on memory circuits having memory devices such as SRAM devices for storage and read/write operations.

FIGS.4A-4Billustrates a piezoelectric NEMS device200, according to various embodiments of the present disclosure. The piezoelectric NEMS device200resembles the cantilever NEMS device200described inFIGS.3A-3Band the piezoelectric NEMS device200may be similarly incorporated in the semiconductor structures100described inFIGS.3A-3B. However, the piezoelectric NEMS device200has a different movement mechanism and it is configured differently from the cantilever NEMS device200. Specifically, instead of bending through electrostatic pull-in effect, the bending in the piezoelectric NEMS device200is through contraction (or expansion) of the piezoelectric material.FIGS.4A-4Billustrates normal-on devices but note that normal-off devices is also possible. For example, the piezoelectric NEMS device200is modified to have the bending direction and electrode height configurations shown inFIGS.3A-3C.

Referring now toFIG.4A, the piezoelectric NEMS device200includes an input electrode D, an output electrode S, a movable feature208over the input and output electrodes D and S, and a control electrode over the movable feature208. The movable feature208has a fixed end attached to the input electrode D and a movable end over the output electrode. The movable end is operable to bend up or down depending on the control voltage applied. The control electrode G directly lands on a top surface of the movable feature208. The input electrode D, the output electrode S, and the control electrode G may each include Cu, W, Pt, Ru, Al, Co TaN, TiN, or a combination thereof.

Still referring toFIG.4A, the movable feature208includes a conducting metal layer207landing on the input electrode D and landing on the output electrode S (when device is on), an insulator layer206landing on the conducting metal layer207, a bottom piezoelectric electrode202blanding on the insulator layer, a piezoelectric layer204landing on the bottom piezoelectric electrode202b, and a top piezoelectric electrode202alanding on the piezoelectric layer204. The control electrode G then lands on the top piezoelectric electrode202a. In the present embodiment, the control electrode G is directly opposite the input electrode D at the fixed end of the movable feature208. If the control electrode G is not at the fixed end, it may move around during NEMS operation and causing reliability issues. In an embodiment, the conducting metal layer207includes Cu, W, Pt, Ru, Al, Co TaN, TiN, or a combination thereof. In an embodiment, the insulator layer206includes SiO2, Si3N4, SiOC, SiCN, SiON, SiCON, or a combination thereof. In an embodiment, the bottom and top piezoelectric electrodes202band202ainclude Cu, W, Pt, Ru, Al, Co TaN, TiN, or a combination thereof. In an embodiment, the piezoelectric layer204includes BaTiO3, PbTiO3, Pb(ZrTi)O3, or a combination thereof.

The piezoelectric NEMS device200operates through a supply voltage at the input electrode D and a control voltage at the control electrode G. The two different voltages are insulated from each other by the insulating layer206. When no control voltage is applied, the movable feature208is at rest, and the supply voltage at the input electrode D is supplied to the output electrode S through the conducting metal layer207. When control voltage is applied, the bendable end of the movable feature208bends up and disconnects from the output electrode S. As such, the supply voltage is cut off from the output electrode. The movable feature208bends due to contraction of the piezoelectric layer204. In the present embodiment, control voltage is applied to the top piezoelectric electrode202a, and the bottom piezoelectric electrode202bis connected to ground, thereby biasing the piezoelectric layer204. As a result, the piezoelectric layer204may expand in the vertical direction due to the electric field, thereby causing contraction in the horizontal direction. The contraction then causes the bending up of the movable feature208. The direction of bending may be controlled by the thickness of the piezoelectric layer204relative to the thickness of the insulating layer206and the conducting metal layer207. For example, when the piezoelectric layer204is thicker than the combined thickness of the insulating layer206and the conducting metal layer207, the movable feature bends up (as shown). For another example, when the piezoelectric layer204is thinner than the combined thickness of the insulating layer206and the conducting metal layer207, the movable feature bends down. Other ways to control the direction of bending may include reversing polarity of the electric field such that the piezoelectric layer204may shrink in the vertical direction, thereby causing expansion in the horizontal direction.

Still referring toFIG.4A, the control voltage may range between 2 volts to 10 volts, and the supply voltage may range between 0.6 volts to 1.2 volts. In an embodiment, the supply voltage is less than the control voltage (e.g., less than 2 volts). The length of the movable feature208may be between 200 nm to 1000 nm in the x direction. The thickness of the movable feature208may be between 75 nm to about 250 nm in the z direction. In an embodiment, the top and bottom piezoelectric electrodes202aand202bhas a thickness ranging between about 5 nm to about 30 nm. In an embodiment, the piezoelectric layer204has a thickness ranging between about 50 nm to about 100 nm. In an embodiment, the insulator layer206has a thickness ranging between about 10 nm to about 50 nm. In an embodiment, the conducting metal layer207has a thickness ranging between about 10 nm to about 40 nm. The bendable end of the movable feature208may bend at a bending angle between 3 degrees to 20 degrees relative to a horizontal direction. In an embodiment, the bending angle is between about 5 degrees to about 15 degrees. Note that the range of the bending angle is not trivial. If the bending angle is too small, the bending end may not properly disconnect from the output electrode S, and if the bending angle is too large, the movable feature208may inadvertently contact other features in the semiconductor structure100.

FIG.4Billustrates a piezoelectric NEMS device200similar to that ofFIG.4A. The similar features will not be repeated again for the sake of brevity. The difference is in the location of the control electrode G. InFIG.4A, the control electrode G lands on top of the movable feature208. Here, the control electrode G may be formed in a same layer as the input and output electrodes D and S. The control electrode G is then electrically routed to the top piezoelectric electrode202athrough metal routings such as metal vias and interconnects.

FIG.5illustrates a semiconductor structure100having a vertical NEMS device200, according to an embodiment of the present disclosure. The semiconductor structure100includes similar features as those described with respect toFIGS.3A-3C. The similar features will not be repeated again for the sake of brevity. The difference is in how the vertical NEMS device200is oriented and configured. As shown, the vertical NEMS device200includes an input electrode D, a control electrode G, an output electrode S, and a movable feature208physically attached to the input electrode D. The input electrode D, the control electrode G, the output electrode S, and the movable feature208may each include Cu, W, Pt, Ru, Al, Co TaN, TiN, or a combination thereof. The input electrode D may be disposed adjacent to the logic devices300a. In an embodiment, the input electrode D may land on (or electrically connect) to an S/D epitaxial feature of a transistor device separate from the logic devices300a. In this way, the separate transistor device is not power gated and is always connected to a power supply, and only the logic devices300aare. The output electrode S is directly above and landing on a metal via319of the interconnect structure300b. In an embodiment, the output electrode S may be a metal line318of the interconnect structure300b. Although not shown, there may be additional metal lines318over the output electrode S. The control electrode G is disposed above the logic devices300aand under the output electrode S. In an embodiment, the control electrode G may be another metal line318of the interconnect structure300b. Each of the input electrode D, output electrode S, and control electrode G are embedded in a dielectric layer (e.g., dielectric layer315). The movable feature208is exposed and surrounded by an air gap250, which allows the movable feature208to move freely (i.e., bend in the x direction along the x-z plane). The movable feature208may bend at a bending angle between 3 degrees to 20 degrees relative to a vertical direction (z direction). In an embodiment, the bending angle is between about 5 degrees to about 15 degrees. As shown, the movable feature208may be a vertical metal pillar (or beam) having multiple metal lines connected by metal vias. The movable feature208may have a height h1in the z direction and is distanced away from the output electrode S by a spacing s1in the x direction. In an embodiment, the height h1is in a range between about 200 nm to about 1000 nm, such as between 200 nm to 500 nm. In an embodiment, the spacing s1is in a range between about 10 nm to about 200 nm, such as between 20 nm to 100 nm. In any case, to ensure contact between the movable feature208and the output electrode S, a tangent of the bending angle is equal to a ratio of the spacing s1to the height h1.

Like the cantilever NEMS device200described inFIGS.3A-3B, the vertical NEMS device200operates through electrostatic pull-in effect.FIG.4shows a normal-off device, however in other embodiments, the vertical NEMS device200may be a normal-on device. As shown here, when no control voltage is applied to the control electrode S, the movable feature is at rest, and supply voltage at the input electrode D is disconnected from the output electrode S. When control voltage is applied to the control electrode S, the movable feature208bends towards the control electrode G until the movable feature208contacts the output electrode S. The movable feature208may bend through electrostatic pull-in effect, where positive charges at the control electrode G attracts negative charges at the movable feature208(or vice versa), and the movable feature bends towards the control electrode G. It may be desirable that the control voltage at the control electrode G be greater than the supply voltage at the input electrode. This is so that the charge effect is dominated by the control voltage without being substantially affected by the supply voltage. In an embodiment, the control voltage ranges between 2 volts to 10 volts, and the supply voltage VDD ranges between 0.6 volts to 1.2 volts.

Still referring toFIG.5, the movable feature directly lands on a top surface of the input electrode D. As the vertical NEMS device200bends over time, stress may accumulate at the base of the movable feature208. In some embodiments, to maintain structural integrity and prevent breakage, the movable feature208may partially penetrate into the input electrode D for structural support.

FIG.6illustrates a semiconductor structure100having an in-plane NEMS device200, according to an embodiment of the present disclosure. As shown, the in-plane NEMS device200includes a movable feature208that bends in the x-y plane (as opposed to the x-z plane as shown inFIG.5). The in-plane NEMS device200may be embedded in a dielectric layer315and exposed in an air gap250. The in-plane NEMS device200may be disposed over logic devices400ain the logic circuit400. In the embodiment shown, the in-plane NEMS device200includes an input electrode D, a first control electrode G1, an output electrode S, a movable feature208extending from the output electrode S, a second control electrode G1, and a ground electrode GND. Each of these electrodes and the movable feature208may include Cu, W, Pt, Ru, Al, Co TaN, TiN, or a combination thereof. Each of these electrodes and the movable feature208may have substantially coplanar top and bottom surfaces as they are formed within a same layer of the semiconductor structure100. The same layer may be a layer of an interconnect structure300bover logic devices300a, where additional interconnect layers may be formed thereon. The same layer may range between about 50 nm to about 150 nm. The length of the movable feature208may be between 200 nm to 1000 nm in the y direction, such as between about 200 nm to about 500 nm.

As shown, the in-plane NEMS device200may be a five terminal device. The first control electrode G1controls the bending towards input electrode D. And the second control electrode G2controls the bending towards the ground electrode GND. As shown, by applying separate control voltages to the first control electrode G1or the second control electrode G2, the output electrode S either electrically connects to a supply voltage or to ground. By having the additional option to ground the output electrode S, performance of the logic devices300amay be improved. The movable feature208may bend through electrostatic pull-in effect, where positive charges at the control electrodes G1/G2attracts negative charges at the movable feature208(or vice versa), and the movable feature bends towards the control electrodes G1/G2. It may be desirable that the control voltage at the control electrode G be greater than the supply voltage at the input electrode. This is so that the charge effect is dominated by the control voltage without being substantially affected by the supply voltage. In an embodiment, the control voltage for the first and the second control electrode G1and G2ranges between 2 volts to 10 volts, and the supply voltage VDD ranges between 0.6 volts to 1.2 volts. The movable feature208may bend at a bending angle between 3 degrees to 20 degrees relative to a horizontal direction. In an embodiment, the bending angle is between about 5 degrees to about 15 degrees. AlthoughFIG.6shows a5terminal device, the present disclosure is not limited thereto. For example, the control gate electrode G2and the ground electrode GND may be removed to form a3terminal device. The3terminal device includes the input electrode D, the first control electrode G1, and the output electrode S. In this way, when the movable feature208disconnects from the input electrode D, the output electrode S is floating instead of grounded.

FIG.7illustrates a semiconductor structure100having a comb structure NEMS device200, according to an embodiment of the present disclosure. The comb structure NEMS device200has an input electrode D, a control electrode G, an output electrode S, and a movable feature208. The movable feature208is coupled to the control electrode G through a NEMS body502having a first set of conductive combs. The first set of conductive combs are capacitively coupled to a second set of conductive combs extending from the control electrode G. Each of the conductive combs may have a comb width ranging between about 5 nm to about 20 nm, and a comb length of about 50 nm to about 200 nm. There may be a gap width of about 10 nm between conductive combs. With more overlap area between the conductive combs, the switching time of the NEMS device may be reduced. As shown, the movable feature208further includes an insulator layer506and a metal layer507, where the insulator layer506insulates the metal layer507from the NEMS body502. The insulator layer506includes SiO2, Si3N4, SiOC, SiCN, SiON, SiCON, or a combination thereof. The metal layer507includes Cu, W, Pt, Ru, Al, Co TaN, TiN, or a combination thereof. The control electrode G and the NEMS body502of the movable feature208may include silicon doped with phosphorous. In other embodiments, the control electrode G and the NEMS body502may include similar materials as the metal layer507.

Like the cantilever NEMS device200described inFIGS.3A-3B, the comb structure NEMS device200operates through electrostatic pull-in effect.FIG.7shows a normal-on device, however in other embodiments, the comb structure NEMS device200may be a normal-off device. The movable feature208is designed with a fixed portion functioning as a rotation axis508and is able to rotate around the rotation axis508. Especially, the rotation axis508is configured such that the movable feature208rests at a level higher than that of the control gate G. In the disclosed embodiment, the rotation axis508is configured in the NEMS body502. As shown here, when no control voltage is applied to the control electrode G, the metal layer507rests on the input electrode D and the output electrode S, and therefore electrically connects the input electrode D to the output electrode S and power (i.e., supply voltage VDD) is supplied to the logic circuit300. And when control voltage is applied to the control electrode G, the movable feature208rotates such that the MEMS body502of the movable feature208moves down toward the second set of conductive combs extending from the control electrode G while the metal layer507of the movable feature208moves upwards to disconnect the output electrode S from the input electrode D and no power (i.e., supply voltage VDD) is supplied to the logic circuit300. The movable feature208may rotates through electrostatic pull-in effect, where positive charges attract negative charges at the interdigitated conductive combs, thereby causing the movable feature208to move. In an embodiment, the movable feature208is designed with a rotation angle ranging between 3 degrees to 20 degrees relative to a horizontal direction. In an embodiment, the rotation angle is between about 5 degrees to about 15 degrees. Note that the range of the rotation angle is not trivial. If the rotation angle is too small, the bending end may not properly disconnect from the output electrode S, and if the rotation angle is too large, the movable feature208may inadvertently contact other features in the semiconductor structure100. In an embodiment, the max movement of the movable feature208is 20 nm in the vertical direction. Like inFIG.2A, it may be desirable that the control voltage at the control electrode G be greater than the supply voltage VDD at the input electrode. This is so that the charge effect is dominated by the control voltage without being substantially affected by the supply voltage VDD. In an embodiment, the control voltage ranges between 2 volts to 10 volts, and the supply voltage VDD ranges between 0.6 volts to 1.2 volts. In the embodiment shown, the input electrode D and the output electrode S have coplanar (or substantially coplanar) top surfaces, and the control electrode G is above the top surfaces of the input electrode D and output electrode S. Further, the electrodes D and S may have coplanar (or substantially coplanar) bottom surfaces. The comb structure NEMS device200may be designed with a different structure and a configuration to achieve the same function according to some other embodiments.

FIG.8illustrates a flowchart of a method1000to form a semiconductor structure100having a NEMS device200for power gating, according to an embodiment of the present disclosure. At operation1002, the method1000forms a logic circuit over a substrate such as the logic circuit300and substrate102described herein. Forming the logic circuit may include forming various logic devices300ahaving a channel region104between source/drain (S/D) epitaxial features106, a gate structure110over the channel region104, S/D contacts112over the S/D epitaxial features, and a gate contact112over the gate structure. The method1000then forms a nanoelectromechanical systems (NEMS) device200electrically connected to the logic circuit300. The forming of the NEMS device200includes operations1004to1010to form various features of the NEMS device200. At operation1004, the method1000forms a first electrode (e.g., output electrode S) electrically connected to the logic circuit (or specifically to a source/drain feature of a logic device in the logic circuit). At operation1006, the method1000forms a second electrode (e.g., input electrode D) electrically connected to a first power supply (e.g., VDD). At operation1008, the method1000forms a movable feature (e.g., movable feature208) electrically connected to the second electrode. And at operation1010, the method1000forms a control electrode (e.g., control electrode G) operable to move the movable feature relative to the first electrode. As part of the method1000, other features may also be formed such as various interconnect structures described herein.

The various NEMS devices200described herein may be formed by any suitable method that includes depositions, lithography processes, and etching processes. In some embodiments, these NEMS devices are first formed embedded in a dielectric material, such as in one or more interlayer dielectric (ILD) layers. Then, portions of the dielectric material surrounding the NEMS device200is etched away by a suitable process, thereby forming an air gap (e.g., air gap250). As shown in the various figures, the air gaps250may expose various horizontal and/or vertical surfaces of the input electrode D, output electrode S, and control electrode D. Further, for purposes of illustration, for example, the method of forming the vertical NEMS device200includes forming the logic devices300aand the vertical NEMS device structure, then removing the dielectric material around the vertical NEMS device structure. For purposes of illustration, for example, the method of forming the in-plane NEMS device200includes forming the logic devices300aand one or more metal layers over the logic circuit (i.e., portion of the interconnect structure300b), then performing a dual damascene process to form a trench over the one or more metal layers, then forming copper fill in the trench and perform CMP to form the in-plane NEMS device structure, then performing HF vapor etch to remove the dielectric surrounding the in-plane NEMS device structure.

Although not limiting, the present disclosure offers advantages for power gating logic devices. One example advantage is integrating the NEMS device in various BEOL locations to save device footprint in FEOL. Another example advantage is the mechanical nature of the NEMS device, thereby eliminating or significantly reducing leakage current. Another example advantage is the ease of integration and high CMOS logic compatibility, which allows for various types of NEMS devices such as cantilever NEMS devices, piezoelectric NEMS devices, vertical NEMS devices, in-plane NEMS devices, and comb structure NEMS devices. The various types of NEMS devices allow flexibility in design.

One aspect of the present disclosure pertains to a device. The device includes a substrate, a logic circuit disposed on the substrate, and a nanoelectromechanical systems (NEMS) device electrically connected to the logic circuit and formed on the substrate. The NEMS device includes a first electrode electrically connected to the logic circuit, a second electrode electrically connected to a first power supply, a movable feature electrically connected to the second electrode, and a control electrode operable to move the movable feature relative to the first electrode.

In an embodiment, the logic circuit includes logic devices over the substrate and an interconnect structure over the logic devices. Each of the logic devices includes a field effect transistor (FET) having a channel region between source/drain (S/D) epitaxial features, a gate structure over the channel region, S/D contacts over the S/D epitaxial features, and a gate contact over the gate structure. The interconnect structure includes metal lines and vias that electrically connect to one or more of the logic devices.

In a further embodiment, a first S/D epitaxial feature of the logic devices is electrically connected to the first electrode; and a second S/D epitaxial feature of the logic devices is electrically connected to a second power supply different from the first power supply.

In a further embodiment, the NEMS device is disposed above the logic devices and is embedded in or above the interconnect structure.

In a further embodiment, the NEMS device is disposed below the logic devices on a backside of the substrate.

In a further embodiment, the device further includes a second logic circuit over the logic circuit, where the second logic circuit includes second logic devices over a second substrate and a second interconnect structure over the second logic devices. The NEMS device is disposed above the second substrate.

In an embodiment, the movable feature lands on a horizontal surface of the first electrode. In an embodiment, each of the first electrode, the second electrode, the control electrode, and the movable feature includes Cu, W, Pt, Ru, Al, Co TaN, TiN, or a combination thereof.

In a further embodiment, the movable feature further includes a piezoelectric layer electrically connected to the control electrode, a conductive layer electrically connected to the second electrode, and an insulator layer separating the piezoelectric layer from the conductive layer.

In an embodiment, a top surface of the first electrode is substantially coplanar with a top surface of the second electrode.

Another aspect of the present disclosure pertains to a device. The device includes a substrate, a logic circuit disposed on the substrate, and a nanoelectromechanical systems (NEMS) device formed on the substrate and electrically connected to the logic circuit. The NEMS device includes a first electrode electrically connected to the logic circuit, a second electrode electrically connected to a power supply VDD, a NEMS structure having a bendable end over the first electrode and a fixed end attached to the second electrode. The NEMS structure includes a piezoelectric layer. The NEMS device further includes a control electrode electrically connected to the NEMS structure. The control electrode and the piezoelectric layer are configured such that the bendable end is operable to bend and disconnect from the first electrode.

In an embodiment, the control electrode lands on a top surface of the fixed end of the NEMS structure.

In an embodiment, the NEMS structure further includes: a conducting metal layer, an insulator layer, a bottom piezoelectric electrode, and a top piezoelectric electrode, where the conducting metal layer is disposed on the second electrode, the insulator layer is disposed on the conducting metal layer, the bottom piezoelectric electrode is disposed on the insulator layer, the piezoelectric layer is disposed on the bottom piezoelectric electrode, and the top piezoelectric electrode is disposed on the piezoelectric layer. The control electrode is disposed on the top piezoelectric electrode.

In a further embodiment, the conducting metal layer includes Cu, W, Pt, Ru, Al, Co TaN, TiN, or a combination thereof, the insulator layer includes SiO2, Si3N4, SiOC, SiCN, SiON, SiCON, or a combination thereof, the bottom and top piezoelectric electrodes include Cu, W, Pt, Ru, Al, Co TaN, TiN, or a combination thereof, and the piezoelectric layer includes BaTiO3, PbTiO3, Pb(ZrTi)O3, or a combination thereof.

In an embodiment, the NEMS structure has a length that ranges between 200 nm to 1000 nm and a thickness that ranges between 75 nm to 250 nm.

In an embodiment, the bendable end bends upwards such that the NEMS structure bends by a bending angle between about 5 degrees to about 15 degrees relative to a horizontal direction.

Another aspect of the present disclosure pertains to a method. The method includes forming a logic circuit over a substrate and forming a nanoelectromechanical systems (NEMS) device electrically connected to the logic circuit. The forming of the NEMS device includes forming a first electrode electrically connected to the logic circuit, forming a second electrode electrically connected to a first power supply, forming a movable feature electrically connected to the second electrode, and forming a control electrode operable to move the movable feature relative to the first electrode.

In an embodiment, the first electrode is electrically connected to a source/drain feature of a logic device in the logic circuit.

In an embodiment, the forming of the NEMS device includes forming the first electrode, the second electrode, the movable feature, and the control electrode in an interlayer dielectric (ILD) layer, and the method further includes etching a portion of the ILD layer surrounding the NEMS device to form an air gap surrounding the movable feature. In a further embodiment, the air gap exposes a horizontal surface of the first electrode.