Integrated transistors having gate material passing through a pillar of semiconductor material, and methods of forming integrated transistors

Some embodiments include an integrated assembly having a pillar of semiconductor material. The pillar has a base region, and bifurcates into two segments which extend upwardly from the base region. The two segments are horizontally spaced from one another by an intervening region. A conductive gate is within the intervening region. A first source/drain region is within the base region, a second source/drain region is within the segments, and a channel region is within the segments. The channel region is adjacent to the conductive gate and is vertically disposed between the first and second source/drain regions. Some embodiments include methods of forming integrated assemblies.

TECHNICAL FIELD

Integrated assemblies (e.g., memory arrays). Integrated assemblies having transistors with gate material passing through pillars of semiconductor material. Methods of forming integrated assemblies.

BACKGROUND

Memory is one type of integrated circuitry, and is used in computer systems for storing data. An example memory is DRAM (dynamic random-access memory). DRAM cells may each comprise a transistor in combination with a capacitor. The DRAM cells may be arranged in an array; with wordlines extending along rows of the array, and digit lines extending along columns of the array. The wordlines may be coupled with the transistors of the memory cells. Each memory cell may be uniquely addressed through a combination of one of the wordlines with one of the digit lines.

A continuing goal is to increase the level of integration of integrated circuitry, with a related goal being to increase packing density of integrated circuit components. It is desired to develop new DRAM architectures which are scalable to high levels of integration, and to develop methods for fabricating such DRAM architectures.

DETAILED DESCRIPTION OF THE ILLUSTRATED EMBODIMENTS

Some embodiments include assemblies having integrated transistors with conductive gate material extending through a pillar of semiconductor material. The integrated transistors may be incorporated into memory arrays (e.g., DRAM arrays). Some embodiments include methods of forming the integrated transistors. Example embodiments are described with reference toFIGS. 1-16.

Referring toFIG. 1, an integrated assembly10includes a memory array14supported over a base12.

The base12may comprise semiconductor material; and may, for example, comprise, consist essentially of, or consist of monocrystalline silicon. The base12may be referred to as a semiconductor substrate. The term “semiconductor substrate” means any construction comprising semiconductive material, including, but not limited to, bulk semiconductive materials such as a semiconductive wafer (either alone or in assemblies comprising other materials), and semiconductive material layers (either alone or in assemblies comprising other materials). The term “substrate” refers to any supporting structure, including, but not limited to, the semiconductor substrates described above. In some applications, the base12may correspond to a semiconductor substrate containing one or more materials associated with integrated circuit fabrication. Such materials may include, for example, one or more of refractory metal materials, barrier materials, diffusion materials, insulator materials, etc.

A gap is provided between the base and the memory array14to indicate that other materials and components may be formed between the base12and the memory array14. For instance, the memory array may be supported by an insulative material (not shown).

The memory array14includes digit lines (bitlines, sense lines)16which extend along a first direction represented by a y-axis, and includes wordlines (access lines)18which extend along a second direction represented by an x-axis. In some embodiments the wordlines18may be considered to extend along a row direction of the memory array14, and the digit lines16may be considered to extend along a column direction of the memory array. One of the x and y axis directions may be referred to as a first horizontal direction, and the other may be referred to as a second horizontal direction; with the first horizontal direction crossing (intersecting) the second horizontal direction. In the illustrated embodiment the first horizontal direction (the direction of either the x-axis or the y-axis) is substantially orthogonal to the second horizontal direction (the direction of the other of the x-axis and the y-axis); with the term “substantially orthogonal” meaning orthogonal to within reasonable tolerances of fabrication and measurement.

The digit lines16and the wordlines18may comprise any suitable electrically conductive composition(s); such as, for example, one or more of various metals (e.g., titanium, tungsten, cobalt, nickel, platinum, ruthenium, etc.), metal-containing compositions (e.g., metal silicide, metal nitride, metal carbide, etc.), and/or conductively-doped semiconductor materials (e.g., conductively-doped silicon, conductively-doped germanium, etc.). The digit lines16and the wordlines18may comprise a same composition as one another, or may comprise different compositions relative to one another.

Pillars20extend upwardly from the digit lines16. The pillars comprise semiconductor material22. The semiconductor material22may comprise any suitable composition(s); and in some embodiments may comprise, consist essentially of; or consist of one or more of silicon, germanium, III/V semiconductor material (e.g., gallium phosphide), semiconductor oxide, etc.; with the term III/V semiconductor material referring to semiconductor materials comprising elements selected from groups III and V of the periodic table (with groups III and V being old nomenclature, and now being referred to as groups13and15). In some embodiments, the semiconductor material22may comprise, consist essentially of, or consist of silicon.

The pillars20extend vertically along a z-axis direction; with the z-axis direction being shown to be substantially orthogonal to both the x-axis direction and the y-axis direction.

The pillars20may have any suitable dimensions; and in some embodiments may have heights, H, within a range of from about 100 nanometers (nm) to about 300 nm; widths, W, within a range of from about 5 nm to about 30 nm (and in some embodiments less than or equal to about 25 nm); and lengths, L, within a range of from about 5 nm to about 30 nm (and in some embodiments less than or equal to about 25 nm). The widths, W, may be equal to the lengths, L, or may be different than the lengths.

The wordlines18are diagrammatically illustrated to pass through central regions of the pillars20(with the term “central region of a pillar” meaning a region interior to the pillar, which may or may not be centered relative to the pillar). In some embodiments each of the pillars20is incorporated into an integrated transistor. The wordlines comprise gate regions within the pillars, and are utilized to operate the integrated transistors. The transistors may be ferroelectric transistors or non-ferroelectric transistors, as will be discussed in more detail below.

If the transistors are ferroelectric transistors, they may be utilized as memory cells within a memory array.

If the transistors are non-ferroelectric transistors, they may be utilized as access transistors within a memory array. Storage-elements (e.g. capacitors) may be coupled with the access transistors, and may be utilized within memory cells of the memory array (e.g., a DRAM array). Example storage-elements are described in more detail below.

FIG. 1diagrammatically illustrates some of the wordlines being electrically coupled with driver circuitry (e.g., CMOS)24through connections26at ends of the wordlines. An advantage of having the wordlines passing through the central regions of the semiconductor pillars20is that such may provide more space between neighboring wordlines than would be available in conventional configurations (in which the wordlines pass along edges of semiconductor pillars, rather than passing through the semiconductor pillars), which may simplify the fabrication of the connections26; and which may otherwise improve scalability of the memory array14as compared to conventional configurations of analogous memory arrays.

FIGS. 2A and 2Bshow the memory array14in a pair of example configurations.

The configuration ofFIG. 2Ashows neighboring wordlines18aand18bbeing coupled with connections26aand26b, respectively, with such connections being coupled to the driver circuitry24. The connections26aand26bare at ends of the wordlines18aand18b, and are offset relative to one another along the row-axis direction (x-axis direction, wordline (WL) direction). The offset connections26aand26bmay be at the same ends of the neighboring wordlines18aand18bas one another, or may be at opposite ends of the neighboring wordlines relative to one another (as shown).

The configuration ofFIG. 2Bshows the connections26aand26bbeing directly adjacent to one another relative to the row-axis direction, and being offset only along the column-axis direction (y-axis direction, digit line (DL) direction). In the illustrated embodiment ofFIG. 2B, the connections26aand26bare at both ends of the wordlines18aand18b. In other embodiments, the connections26aand26bmay be at only one end of the wordlines. Regardless,FIG. 2Billustrates an advantage which may be achieved utilizing memory configurations described herein as compared to conventional configurations. Specifically, passage of the wordlines18through the semiconductor pillars20may enable wider spacing between the wordlines than is achieved when the wordlines pass along edges of the semiconductor pillars in conventional configurations. Such may enable the connections26aand26bto be directly adjacent one another in highly-integrated memory configurations described herein even though such would not be possible in conventional memory configurations at similar levels of integration.

The memory array14may be formed with any suitable processing. Example processing is described with reference toFIGS. 3-12.

Referring toFIGS. 3A and 3B, the assembly10is illustrated at a process stage after semiconductor material22is formed over the digit lines16. The views ofFIGS. 3A and 3Bare orthogonal to one another; with the view ofFIG. 3Abeing along the line A-A ofFIG. 3B, and the view ofFIG. 3Bbeing along the line B-B ofFIG. 3A. The view ofFIG. 3Amay be considered to be along a direction corresponding to the y-axis ofFIG. 1, and the view ofFIG. 3Bmay be considered to be along a direction corresponding to the x-axis ofFIG. 1.

The semiconductor material22is patterned into the pillars20, with such pillars extending upwardly from the digit lines16.

Protective material28is over tops of the pillars20. The protective material28may comprise any suitable composition(s); and in some embodiments may comprise, consist essentially of, or consist of silicon dioxide.

An insulative material30laterally surrounds the pillars20. The insulative material30may comprise any suitable composition(s); and in some embodiments may comprise, consist essentially of, or consist of silicon dioxide. The insulative material30may correspond to a spin-on dielectric (SOD).

In some embodiments the configuration ofFIGS. 3A and 3Bmay be considered to comprise a mass32extending across the digit lines16; with such mass including the semiconductor pillars20, and the materials28and30surrounding the pillars.

The base12(FIG. 1) is not shown inFIGS. 3A and 3Bin order to simplify the drawings, but would generally be present under the digit lines16.

Referring toFIGS. 4A and 4B, the insulative material30is recessed relative to the protective material28. In the illustrated embodiment an upper surface31of the insulative material30is coextensive with a bottom surface29of the protective material28after the recessing of the material30.

Referring toFIGS. 5A and 5B, a second protective material34is formed over the upper surface31of the recessed material30, and adjacent to the first protective material28. The second protective material34may comprise any suitable composition(s); and in some embodiments may comprise, consist essentially of, or consist of a material comprising silicon and carbon (e.g., a silicon carbide). In the illustrated embodiment a planarized surface35is formed to extend across the first and second protective materials28and34. The planarized surface35may be formed with any suitable processing; including, for example, chemical-mechanical polishing (CMP).

The materials22,30,28and34may be together considered to be incorporated into the mass32which extends across the digit lines16.

Referring toFIGS. 6A and 6B, the first protective material28(FIGS. 5A and 5B) is removed to form openings36extending into the mass32. The openings36are directly over the semiconductor pillars22, and expose upper surfaces23of the semiconductor pillars.

A material38is formed over the mass32. The material38may comprise any suitable composition(s); and in some embodiments may comprise, consist essentially of, or consist of silicon nitride.

The material38is conformal to a top surface of the mass32, and extends into the openings36. An upper topography of the material38has valleys40over the semiconductor pillars20, and has peaks42between the valleys. In some embodiments the material38may be referred to as a patterned material to indicate that the material has the patterned topography comprising the illustrated peaks42and valleys40.

Referring toFIGS. 7A and 7B, the valleys40(FIGS. 6A and 6B) are extended into the semiconductor pillars20form openings44in the semiconductor pillars. In the illustrated embodiment such openings are incorporated into slits46which extend into the page relative to the cross-section ofFIG. 7A, and which extend along the cross-section ofFIG. 7B. The utilization of the openings44may assist in aligning the slits46with central regions of the pillars20. However, the slits46may be patterned with any suitable processing. For instance, the slits46may correspond to trenches patterned utilizing a photolithographically-patterned photoresist mask (not shown) in addition to, or alternatively to, the formation of the openings46with the conformal material38.

Each of the patterned pillars20includes a base region48, and a pair of segments (projections)50and52extending upwardly from the base region. In some embodiments the pillars20may be considered to extend vertically from upper surfaces of the digit lines16; to comprise the base regions48directly over the digit lines; and to bifurcate into the first and second segments50and52which extend upwardly from the base region.

The first and second segments50and52are horizontally-spaced from one another by intervening regions (gaps)54. In some embodiments each of the patterned pillars20may be considered to have a slit46associated therewith, and to have an intervening gap54corresponding to the associated slit.

In the shown embodiment lower regions of the pillars20are conductively doped to form first source/drain regions56within the lower regions. Approximate upper boundaries of the first source/drain regions are diagrammatically illustrated utilizing dashed lines57. The upper boundaries of the source/drain regions56may be at any suitable locations within the pillars20, and may be above or below the illustrated locations57in some embodiments.

The source/drain regions56may be formed at any suitable process stage, including process stages prior toFIGS. 7A and 7B(such as, for example, blanket doping prior to the process stage ofFIGS. 3A and 3B). However, it may be advantageous to form the source/drain regions56at the process stage ofFIGS. 7A and 7Bas such may enable the source/drain regions to be aligned with the semiconductor pillars20.

Referring toFIGS. 8A and 8B, insulative material58is formed along sidewalls47of the slits46; and in the shown embodiment is also formed along bottoms49of the slits. The insulative material58may be referred to as a first insulative material to distinguish it from other insulative materials that may also be formed within the slits46. In some embodiments the insulative material58may be referred to as gate dielectric material.

The insulative material58may comprise any suitable composition(s); and in some embodiments may comprise silicon dioxide and/or one or more high-k dielectric materials (where the term high-k means a dielectric constant greater than that of silicon dioxide). Example high-k dielectric materials include aluminum oxide, hafnium oxide, zirconium oxide, etc.

In some embodiments, the insulative material58may comprise ferroelectric material suitable for utilization in ferroelectric transistors. The ferroelectric material may comprise any suitable composition(s); and may, for example, comprise, consist essentially of, or consist of one or more materials selected from the group consisting of transition metal oxide, zirconium, zirconium oxide, hafnium, hafnium oxide, lead zirconium titanate, tantalum oxide, and barium strontium titanate; and having dopant therein which comprises one or more of silicon, aluminum, lanthanum, yttrium, erbium, calcium, magnesium, strontium, and a rare earth element. The ferroelectric material may be provided in any suitable configuration; such as, for example, a single homogeneous material, or a laminate of two or more discrete separate materials.

In some embodiments, the insulative material58may consist of non-ferroelectric material (e.g., silicon dioxide).

The insulative material58may be oxidatively grown from the semiconductor material22of the semiconductor pillars20. For instance, if the semiconductor material22comprises silicon, the insulative material58may comprise, consist essentially of, or consist of silicon dioxide which is oxidatively grown from such semiconductor material.

The insulative material58may be deposited along the sidewalls47and bottoms49of the slits46in addition to, or alternatively to, being oxidatively grown. Such deposition may utilize any suitable processing; including, for example, atomic layer deposition (ALD), chemical vapor deposition (CVD), etc.

FIG. 8Ashows an embodiment in which the material58is selectively formed along the surfaces47and49of the semiconductor material22relative to surfaces of the materials34and38. Such may be accomplished with selective deposition of the material58and/or by oxidatively growing material58from exposed surfaces of the semiconductor material22. In other embodiments (discussed below), the material58may be formed along surfaces of the materials34and38, in addition to being formed along the surfaces of the semiconductor material22.

Conductive material19is formed within the slits46and adjacent to (over) the insulative material58. The conductive material19is ultimately utilized to form the wordlines18, and may be referred to as wordline material. The conductive material19may comprise any suitable electrically conductive composition(s); such as, for example, one or more of various metals (e.g., titanium, tungsten, cobalt, nickel, platinum, ruthenium, etc.), metal-containing compositions (e.g., metal silicide, metal nitride, metal carbide, etc.), and/or conductively-doped semiconductor materials (e.g., conductively-doped silicon, conductively-doped germanium, etc.). In some embodiments, the conductive material19may comprise one or more metals (e.g., tungsten, titanium, etc.); and/or one or more metal-containing compositions (e.g., metal nitride, metal carbide, metal silicide, etc.). The wordline material19may be the same composition as the digit line material17, or may be a different composition relative to the digit line material.

An upper surface of the wordline material19may be planarized to remove some of the excess material19.

FIGS. 8C and 8Dshow processing stages which may be utilized alternatively to the process stage ofFIG. 8A.

FIG. 8Cillustrates an embodiment in which the insulative material58is deposited along surfaces of all of the materials22,34and38, and then the conductive material19is formed within the slits46and over the insulative material58.

FIG. 8Dillustrates an embodiment in which another insulative material60is formed within the slits46prior to forming the insulative material58and the conductive material46. The insulative material60may be referred to as a second insulative material to distinguish it from the first insulative material58. The insulative material60may comprise any suitable composition(s); and in some embodiments may comprise, consist essentially of, or consist of silicon dioxide, low-k dielectric material and/or high-k dielectric material. The term “low-k” means a dielectric constant less than that of silicon dioxide. An example low-k dielectric material is porous silicon dioxide. In some embodiments the insulative material60may be a same composition as the insulative material58, and in other embodiments the insulative material60may be a different composition than the insulative material58.

The insulative material60may form a step which elevates the wordline material19to a desired location within the slits46. Ultimately, the wordline material19is patterned into wordlines18, and the insulative material60may be utilized to align such wordlines in a desired location relative to bottom portions of the projections50and52of the semiconductor pillars20.

Although the insulative material58is shown to not extend across an upper surface of the insulative material60in the embodiment ofFIG. 8D, it is to be understood that other embodiments similar to that ofFIG. 8Dmay be formed in which the material58is deposited (analogously to the deposition shown inFIG. 8C) to extend across the upper surface of material60, as well as across surfaces of the materials34and38.

Referring toFIGS. 9A and 9B, the assembly10is shown at a processing stage subsequent to that ofFIGS. 8A and 8B. The materials19and58are recessed within the slits46to form openings62within upper regions of the slits46. The patterned material19becomes wordlines18analogous to those described above with reference toFIG. 1.

Second source/drain regions64are formed within the segments50and52of the semiconductor pillars20. Approximate lower boundaries of the second source/drain regions are diagrammatically illustrated with dashed lines65. The lower boundaries of the source/drain regions64may be at any suitable locations within the pillars20, and may be above or below the illustrated locations65in some embodiments.

The source/drain regions64may be formed at any suitable process stage, including process stages prior toFIGS. 9A and 9B(such as, for example, blanket doping prior to the process stage ofFIGS. 3A and 3B). However, it may be advantageous to form the source/drain regions64at the process stage ofFIGS. 9A and 9Bas such may enable the source/drain regions to be aligned with the semiconductor pillars20and with the upper surfaces of the wordlines18.

Channel regions66are within the vertically-extending segments50and52, and are vertically disposed between the lower source/drain regions56and the upper source/drain regions64(in some embodiments, the source/drain regions56and64may be considered to be vertically spaced from one another by the channel regions66). The channel regions66may be doped to any suitable level with any suitable dopant (and in some embodiments may be intrinsically doped). The doping of the channel regions may occur at the processing stage ofFIGS. 9A and 9B, and/or at another processing stage (e.g., utilizing blanket doping at the processing stage prior to that ofFIGS. 3A and 3B).

In some embodiments the regions56,64and66are incorporated into n-channel devices; and accordingly the source/drain regions56and64are n-type doped. In other embodiments the regions56,64and66are incorporated into p-channel devices; and accordingly the source/drain regions56and64are p-type doped.

The wordlines18each have a pair of opposing sidewall surfaces67, a top surface69and a bottom surface71; with the sidewall surfaces extending between the top and bottom surfaces. Regions of the wordlines18within the pillars20may be utilized as gates of transistor devices; and may be referred to as gate regions, as transistor gates, or as transistor gate regions.

Referring toFIGS. 10A and 10B, insulative material68is formed within the opening62of the slits46. The insulative material68is over the upper surfaces69of the wordlines18. The insulative material62may comprise any suitable composition(s); and in some embodiments may comprise, consist essentially of, or consist of silicon dioxide. The insulative material68may comprise a same composition as the insulative material58(as shown), or may comprise a different composition relative to the insulative material58. In some embodiments the insulative material68may be referred to as a second insulative material to distinguish it from the first insulative material58. In some embodiments the assembly10may include the insulative material60(FIG. 8D) in addition to the insulative materials58and68. In such embodiments the insulative materials58,68and60may be referred to as first, second and third insulative materials to distinguish them from one another.

Referring toFIGS. 11A and 11B, the insulative material68is removed from over the materials38and34with a planarization process (e.g., CMP); and a patterned material70is formed over regions of the insulative material68and the materials38and34. The patterned material70may comprise any suitable composition(s); and in some embodiments may comprise a combination of silicon and carbon (e.g., silicon carbide), and may be a same composition as the material34. The material70may be patterned with any suitable process, including a so-called “pitch-doubling” process.

The patterned material70has openings72extending therethrough, with such openings being aligned with the digit lines16.

The openings72are extended into the insulative material68.

In some embodiments the conductive material74may be provided to overfill openings72, and excess material74(together with the material70) may be removed with a planarization process. A planarized surface73extends across the materials34,38and74.

The conductive material74ofFIGS. 12A and 12Bis patterned into conductive interconnects76.

In some embodiments the slits46may be considered to have a first dimension, D, along the cross-section ofFIG. 12A, and the conductive interconnects76may be considered to have a second dimension along the cross-section; with the second dimension being the same as the first dimension.

The pillars20may be considered to be incorporated into transistors78. Each of the transistors has a lower source/drain region56electrically coupled with a digit line16, and has an upper source/drain region64electrically coupled with a conductive interconnect76. The transistors have conductive gates80between the vertically-extending segments50and52of the pillars20. The gates80are operatively adjacent the channel regions66so that the gates may be utilized to impart electric fields on adjacent (associated) channel regions to couple source/drain regions56and64to one another through the channel regions. The gates80are along the wordlines18, and electric fields imparted by the gates80may be controlled through operation of the wordlines18.

In some embodiments the insulative material58between the gates80and the channel regions66may comprise ferroelectric material, and accordingly the transistors78may be ferroelectric transistors which may be utilized as memory cells within a memory array. In other embodiments the insulative material58between the gates80and the channel regions66may comprise non-ferroelectric material, and the transistors may be field effect transistors (FETs) utilized as access devices within a memory array. In such embodiments, storage-elements may be electrically coupled with the source/drain regions64through the interconnects76.

FIG. 13shows a three-dimensional view of a region of an example memory array14, and shows the interconnects76electrically coupled with storage-elements82. The storage-elements82may be any suitable devices having at least two detectable states; and in some embodiments may be, for example, capacitors, resistive-memory devices, conductive-bridging devices, phase-change-memory (PCM) devices, programmable metallization cells (PMC), etc.

FIG. 14illustrates a region of the memory array14ofFIG. 13, and shows an individual transistor78. The transistor is incorporated into a memory cell84as an access transistor. The memory cell84has a storage-element82configured as a capacitor. The capacitor82has an electrode83which is electrically coupled with the interconnect76, and has another electrode85which is electrically coupled with a reference voltage87. The reference voltage87may be any suitable voltage including, for example, ground, VCC/2, etc.

The capacitor82also includes an insulative material89between the electrodes83and85. The insulative material89may be ferroelectric material may comprise any of the ferroelectric compositions described above as being suitable for utilization in the material58), and may be utilized in a ferroelectric capacitor. Alternatively, the insulative material89may consist only of one or more non-ferroelectric compositions (e.g., silicon dioxide).

The view ofFIG. 14shows the interconnect76being directly over the digit line16. In the illustrated embodiment the interconnect76is configured as a plate, and specifically is configured as a rectangular plate. A portion86of the rectangular plate is between the projections50and52of the semiconductor pillar20, and another portion88is above the projections50and52of the semiconductor material pillar20.

FIG. 14Ashows a transistor78similar to that ofFIG. 14, but in which the insulative material60described above with reference toFIG. 8Dis provided under the wordline18.

To the extent that the transistors78described above are utilized as access transistors of a memory array, such memory array may have any suitable configuration.FIG. 15shows a region of an example memory array14configured as a DRAM array utilizing one-transistor-one-capacitor (1T-1C) memory cells84. The memory array14includes wordlines (WL1-WL4) extending along a first direction (row direction) of the memory array, and includes digit lines (DL1-DL4) extending along a second direction (column direction) of the memory array. Each of the memory cells84is uniquely addressed with a combination of one of the wordlines and one of the digit lines.

In some embodiments the memory arrays (e.g.,14) may be within a memory tier (i.e., memory deck) which is within a vertically-stacked arrangement of tiers (or decks). The vertically-stacked arrangement may be referred to as a multitier assembly.FIG. 16shows a portion of an example multitier assembly200comprising a vertically-stacked arrangement of tiers202,204and206. The vertically-stacked arrangement may extend upwardly to include additional tiers. The tiers202,204and206may be considered to be examples of levels that are stacked one atop the other. The levels may be within different semiconductor dies, or at least two of the levels may be within the same semiconductor die.

The bottom tier202may include control circuitry and/or sensing circuitry208(e.g., may include drivers, sense amplifiers, etc.); and in some applications may comprise CMOS circuitry. The upper tiers204and206may include memory arrays, such as, for example, the memory arrays14described above; with an example memory array being shown as “memory”210within the tier204.

The circuitry from the upper tiers may be electrically connected to the circuitry of the lower tiers through electrical interconnects. An example electrical interconnect212is shown electrically coupling the memory circuitry210from the tier204with the circuitry208of the tier202. In some embodiments the interconnect212may connect digit lines from the memory circuitry210with sense amplifiers of the circuitry208; may connect wordlines, mux lines and/or plate lines of the memory circuitry210with drivers of the circuitry208; etc.

The assemblies and structures discussed above may be utilized within integrated circuits (with the term “integrated circuit” meaning an electronic circuit supported by a semiconductor substrate); and may be incorporated into electronic systems. Such electronic systems may be used in, for example, memory modules, device drivers, power modules, communication modems, processor modules, and application-specific modules, and may include multilayer, multichip modules. The electronic systems may be any of a broad range of systems, such as, for example, cameras, wireless devices, displays, chip sets, set top boxes, games, lighting, vehicles, clocks, televisions, cell phones, personal computers, automobiles, industrial control systems, aircraft, etc.

The terms “dielectric” and “insulative” may be utilized to describe materials having insulative electrical properties. The terms are considered synonymous in this disclosure. The utilization of the term “dielectric” in some instances, and the term “insulative” (or “electrically insulative”) in other instances, may be to provide language variation within this disclosure to simplify antecedent basis within the claims that follow, and is not utilized to indicate any significant chemical or electrical differences.

The terms “electrically connected” and “electrically coupled” may both be utilized in this disclosure. The terms are considered synonymous. The utilization of one term in some instances and the other in other instances may be to provide language variation within this disclosure to simplify antecedent basis within the claims that follow.

The cross-sectional views of the accompanying illustrations only show features within the planes of the cross-sections, and do not show materials behind the planes of the cross-sections, unless indicated otherwise, in order to simplify the drawings.

When a structure is referred to above as being “on”, “adjacent” or “against” another structure, it can be directly on the other structure or intervening structures may also be present. In contrast, when a structure is referred to as being “directly on”, “directly adjacent” or “directly against” another structure, there are no intervening structures present. The terms “directly under”, “directly over”, etc., do not indicate direct physical contact (unless expressly stated otherwise), but instead indicate upright alignment.

Structures (e.g., layers, materials, etc.) may be referred to as “extending vertically” to indicate that the structures generally extend upwardly from an underlying base (e.g., substrate). The vertically-extending structures may extend substantially orthogonally relative to an upper surface of the base, or not.

Some embodiments include an integrated assembly having a pillar of semiconductor material. The pillar has a base region, and bifurcates into two segments which extend upwardly from the base region. The two segments are a first segment and a second segment, and are horizontally spaced from one another by an intervening region. A conductive gate is within the intervening region. A first source/drain region is within the base region, a second source/drain region is within the first and second segments, and a channel region is within the first and second segments. The channel region is adjacent to the conductive gate and is vertically disposed between the first and second source/drain regions.

Some embodiments include a memory array having digit lines which extend horizontally along a first direction. Pillars of semiconductor material extend upwardly from the digit lines. Wordlines passing through central regions of the pillars. The wordlines extend horizontally along a second direction which intersects the first direction. Each of the wordlines has a pair of opposing sidewall surfaces which extend between a top surface and a bottom surface. The semiconductor material of the pillars is along both of the opposing sidewall surfaces of said pair of opposing sidewall surfaces. First source/drain regions are within the pillars and are electrically coupled with the digit lines. Second source/drain regions are within the pillars and are vertically offset from the first source/drain regions. Channel regions are within the pillars, are adjacent the wordlines, and are vertically disposed between the first and second source/drain regions. Storage-elements are electrically coupled with the second source/drain regions.

Some embodiments include a method of forming an integrated assembly. An arrangement is formed to comprise semiconductor pillars extending upwardly from digit lines. The digits lines extend along a first direction. Slits are patterned to extend partially into the pillars. Each of the pillars has an associated one of the slits patterned therein and is configured to have a base region, and to have a pair of segments extending upwardly from the base region. The segments of said pair are spaced from one another by an intervening gap corresponding to said associated one of the slits. First insulative material is formed along sidewalls of the slits. Conductive wordlines are formed within the slits and adjacent the first insulative material. The conductive wordlines along a second direction which crosses the first direction. First source/drain regions are formed within the base regions of the pillars. Second source/drain regions are formed within the segments of the pillars, and are vertically spaced from the first source/drain regions by channel regions. Second insulative material is formed within the slits and over the wordlines. Conductive interconnects are formed within the slits and over the second insulative material.