Fast dynamic register

A fast dynamic register circuit including first and second precharge circuits, a keeper circuit and an output circuit. The first and second precharge circuits each precharge a corresponding one of a pair of precharge nodes and cooperate to minimize setup and hold times. If an input data node is low when the clock goes high, the first precharge node remains high causing the second precharge node to be discharged. Otherwise if the input node is high, the first precharge node is discharged and the second remains charged. Once either precharge node is discharged, the output state of the register remains fixed until the next rising clock edge independent of changes of the input data node. The fast dynamic register may be implemented with multiple inputs to perform common logic operations, such as OR, NOR, AND and NAND logic operations.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to latch and register circuits, and more particularly to a fast dynamic register.

2. Description of the Related Art

Dynamic logic circuits often exhibit relatively long setup and/or hold times to ensure proper operation. In many dynamic register circuits, the data had to be held while the clock was at a particular state, which was significantly disadvantageous for certain clock signals at or near 50% duty cycle. In a fast path of a digital circuit, buffers were often required to hold the data for the requisite amount of time. Buffers, however, consume valuable space and power. One method of reducing the hold time was to provide a pulsed clock generator. A pulse clock generator, however, also consumes valuable space and power.

There is a need for providing a fast dynamic register circuit with minimal setup and hold times without the overhead of buffers and/or pulsed clock circuits.

SUMMARY OF THE INVENTION

A fast dynamic register circuit according to one embodiment includes first and second precharge circuits, a full keeper circuit and an output circuit. The first precharge circuit precharges a first precharge node high while a clock node is low, maintains the first precharge node high after the clock node goes high when a data node is low, discharges the first precharge node low if the data node is high when the clock node goes high, and keeps the first precharge node discharged low while the clock node is high if the first precharge node was discharged low when the clock node went high. The second precharge circuit precharges a second precharge node high while the clock node is low, and discharges the second precharge node low if the first precharge node remains high after the clock node went high. The full keeper circuit keeps a state of the second precharge node immediately after either one of the first and second precharge nodes switches state while the clock node is high. The output circuit drives an output node to a state based on the second precharge node immediately after either one of the first and second precharge nodes switches state after the clock signal goes high and which otherwise maintains a state of the output node.

The fast dynamic register circuit may be implemented as a multiple input NOR logic gate in which multiple data nodes form the inputs. In this case, the first precharge circuit precharges the first precharge node high while the clock node is low, maintains the first precharge node high after the clock node goes high when each of the data nodes is low, discharges the first precharge node low if any of the data nodes are high when the clock node goes high, and keeps the first precharge node discharged low while the clock node is high if the first precharge node was discharged when the clock node went high.

The fast dynamic register circuit may be implemented as a multiple input NAND logic gate. In this case, multiple first precharge circuits are provided, each precharging a corresponding one of multiple first precharge nodes high while the clock node is low, each maintaining a corresponding one of the first precharge nodes high after the clock node goes high when a corresponding data node is low, each discharging a corresponding first precharge node low if a corresponding data nodes is high when the clock node goes high, and each keeping a corresponding first precharge node discharged low while the clock node is high if the corresponding first precharge node was discharged low when the clock node went high. Also, the second precharge circuit precharges the second precharge node high while the clock node is low and discharges the second precharge node low if at least one first precharge node remains high after the clock node goes high.

An integrated circuit, according to one embodiment includes combinatorial logic which provides a data signal and a fast dynamic register for registering the data.

A method of registering data according to one embodiment includes precharging a first precharge node high while a clock node is low, maintaining the first precharge node high after the clock node goes high when a data node is low, discharging the first precharge node low if the data node is high when the clock node goes high, keeping the first precharge node discharged low while the clock node is high if the first precharge node was discharged low when the clock node went high, precharging a second precharge node high while the clock node is low, discharging the second precharge node low if the first precharge node remains high after the clock node went high, keeping a state of the second precharge node immediately after either one of the first and second precharge nodes switches state while the clock node is high, and asserting an output node to a state based on the second precharge node immediately after either one of the first and second precharge nodes switches state after the clock signal goes high and otherwise maintaining a state of the output node.

DETAILED DESCRIPTION

The present inventor has observed that dynamic logic circuits often exhibit relatively long setup and/or hold times to ensure proper operation. In many dynamic register circuits, the data had to be held while the clock was at a particular state, which was significantly disadvantageous for certain clock signals at or near 50% duty cycle. In a fast path of a digital circuit, buffers were often required to hold the data for the requisite amount of time. Buffers, however, consume valuable space and power. One method of reducing the hold time was to provide a pulsed clock generator. A pulse clock generator, however, also consumes valuable space and power. The present inventor has therefore developed a fast dynamic register, as will be further described below with respect toFIGS. 1-13.

FIG. 1is a block diagram of a fast dynamic register100according to one embodiment. The register100includes a first precharge circuit102(PC1), a second precharge circuit104(PC2), an output circuit106, and a full keeper circuit108all coupled between upper and lower source voltages VDD and VSS, respectively. VDD may be any suitable source voltage level, such as 1.1 Volts (V), 1.3V, 1.5V, 3V, 5V, etc., and VSS is also any appropriate voltage level, such as 0V or ground. An input node101provides a data signal D to an input of the precharge circuit102, which has an output coupled to node103providing a signal PC1to an input of the precharge circuit104. The precharge circuit104outputs a signal PC2on node105, which is coupled to one input of the output circuit106. The output of the output circuit106provides an output signal QB on node107. A clock signal CLK is provided via node109to each of the circuits102,104and106. The full keeper circuit108is coupled to node105to maintain the state of PC2as further described below. The signals described herein generally operate between the source voltage levels VDD and VSS unless otherwise specified. For example, the CLK signal toggles between voltage levels VSS and VDD having any suitable duty cycle. As described herein, the fast dynamic register100is configured to provide relatively short set-up and hold times regardless of the duty cycle of CLK. CLK does not have to be a pulse clock signal so that a separate pulse clock generator is not necessary.

In operation of the fast dynamic register100, PC1and PC2are pre-charged high to VDD while CLK is low. When CLK goes high, D is effectively sampled by the precharge circuit102which either maintains PC1high or discharges PC1low. If PC1remains high, PC2is discharged low by the precharge circuit104. When PC2is discharged low, QB goes high (or stays high). If PC1is discharged low, then PC2stays high and QB goes low (or stays low). Once either PC1or PC2discharges low while CLK is high, the output QB of the fast dynamic register100is determined and the D signal may change state without changing QB. The state of QB is determined by the state of PC2relatively quickly after the rising edge of CLK. In this manner, the hold time of the register100is relatively short. When CLK goes back low, the PC1and PC2signals are once again pre-charged high and the state of QB is maintained by the precharge circuit106.

FIG. 2is a schematic diagram of the precharge circuit102according to one embodiment. Node109providing the CLK signal is coupled to the gate of a P-channel device P1, having its source coupled to VDD and its drain coupled to node103developing the PC1signal. The D signal is provided to the gate of an N-channel device N1, having its drain coupled to node103and its source coupled to the drain of another N-channel device N2. N2has its source coupled to VSS and its gate coupled to node109for receiving the CLK signal. Node103is further coupled to a clocked half-keeper circuit202including an inverter I1and two N-channel devices N3and N4. Node103is coupled to the input of inverter I1, having its output coupled to the gate of N3. The drain of N3is coupled to node103and its source is coupled to the drain of N4. The source of N4is coupled to VSS and its gate is coupled to node109for receiving the CLK signal.

In operation of the precharge circuit102, when CLK is low P1is turned on precharging node103pulling the PC1signal high to VDD. The output of the inverter I1is low so that N3is off, and N2is also off. When CLK goes high, P1is turned off and N2and N4are turned on. If D is high when CLK goes high, then node103is discharged via N1and N2so that PC1goes low. After PC1goes low, any change of D is inconsequential and does not change the state of PC1. Also, the output of the inverter I1of the clocked half-keeper circuit202goes high turning on N3. In this manner, node103is kept discharged via N3and N4to VSS so that PC1is kept low while CLK is high. If instead D is low when CLK goes high, then N1is off so that node103remains charged and PC1remains high. PC1is maintained at a high logic level while CLK is high. It is noted that if D goes from low to high while CLK is high, node103is discharged pulling PC1low. As described further below, however, if PC1remains high when CLK goes high, PC2is discharged low relatively quickly. Once PC2is discharged low, PC2remains low even if PC1is subsequently pulled low while CLK is high, so that the change of the input D signal is inconsequential. In this manner, the fast dynamic register100has a relatively minimal hold time in that the state remains registered once either PC1or PC2is pulled low.

FIG. 3is a schematic diagram of the precharge circuit104according to one embodiment. The clock node109is coupled to the input of an inverter I2and to the gate of a P-channel device P2. The output of the inverter I2is coupled to a node301developing an inverted clock signal CLKB. A “B” appended to the end of a signal name denotes a logically inverted signal unless otherwise specified. For example, when CLK is high, CLKB is low and vice-versa. The source of P2is coupled to VDD and its drain is coupled to node105. The drain of an N-channel device N5is coupled to node105, its gate is coupled to node103for receiving the PC1signal, and its source is coupled to node301.

In operation of the precharge circuit104, when CLK is low, P2is on which pre-charges node105to VDD thus pulling PC2to a high logic level. The inverter I2drives node301high so that node301is pre-charged high and CLKB is high. Although PC1is pre-charged high as previously described, N5is off since CLKB is also high. When CLK goes high, P2is turned off and inverter I2begins discharging node301low. If PC1remains high after CLK goes high (such as when D is low), then N5turns on as CLKB decreases so that PC2is pulled low by the inverter I2. If instead PC1is pulled low (such as when D is high) after CLK goes high, then N5remains off so that PC2remains high.

FIG. 4is a schematic diagram of the output circuit106according to one embodiment. Node109providing the CLK signal is provided to the gate of an N-channel device N6and to the gate of a P-channel device P5. Node105providing PC2is coupled to the gate of a P-channel device P3, to the gate of an N-channel device N7, and to one input of a two-input logic NAND gate402. The output of the NAND gate402provides the output signal QB. The source of P3is coupled to VDD and its drain is coupled to node401developing a preliminary output signal PO. The drain of N6is coupled to node401and its source is coupled at node403to the drain of N7, which has its source coupled to VSS. Node401is coupled to the input of an inverter I3, having its output coupled to node405developing an inverted output signal Q. Node405is further coupled to the gate of a P-channel device P4, to the gate of an N-channel device N8, and to the other input of the NAND gate402. P4has its source coupled to VDD and its drain coupled to the source of P5, which has its drain coupled to node401. N8has its drain coupled to node401and its source coupled to node403. It is noted that the output circuit106may be configured as an SR latch with cross-coupled NAND gates as understood by those skilled in the art. In the cross-coupled configuration, the NAND gate402is configured as shown with PC2and Q as inputs and QB as its output. The second NAND gate (not shown) has one input receiving QB, its other input receiving CLKB, and its output asserting signal Q. Operation is substantially similar.

In operation of the output circuit106, when CLK is low, N6is off and PC2is precharged high turning off P3and turning N7on thereby discharging node403. If the inverter I3asserts Q high (such as from a prior cycle), then P4is off and N8is on pulling PO low via N7and N8thereby keeping Q high. Q and PC2are both high so that QB is low. Otherwise, if the inverter I3asserts Q low, then N8is off and P4is on so that PO is pulled high via P4and P5. In this case, QB is high. The devices P4, P5, N7and N8and the inverter I3collectively operate as a full keeper circuit to maintain the state of PO and Q while CLK is low.

When CLK goes high, N6is turned on and P5is turned off. It is noted that when CLK initially goes high while PC2is high and if PO was also high, N6and N7are both turned on to discharge node401to begin pulling PO low. If PC1stays high (such as when D is low), then the inverter I2discharges nodes301and105relatively quickly so that PC2drops sufficiently fast before node401is discharged by a significant amount. As PC2decreases, N7begins turning off to reduce discharge current from node401while P3begins turning on to add charging current to node401. Thus, if PO is initially high, it momentarily “glitches” below VDD. When PC2is sufficiently low, P3is turned on and N7is turned off so that PO is pulled back high. The devices N5, N6and N7, and the inverter I2are configured such that the voltage of node401does not drop significantly during this condition so that PO remains at a logic high level, so that the inverter I3maintains Q low. If instead PO was initially low when CLK goes high and PC1stays high, then this condition is inconsequential and PO is eventually pulled high by P3when PC2goes low. When PO is high, the inverter I3pulls Q low. In either case, Q goes low turning P4on. When CLK next goes back low, P5turns on pulling PO high via P4and P5to maintain Q low. In either case, QB remains high.

If instead PC1is pulled low (such as when D is high) after CLK goes high, then N5remains off so that PC2remains high. N6is turned on and node401is discharged low to pull PO low via N6and N7. Thus, if PO was high it goes low, and if PO was already low, then it does not change state in response to CLK going high. In this case the inverter I3pulls Q high turning N8on to pull PO low via N8and N7to maintain the high state of Q. Since PC2and QB are both high, QB is low. When CLK next goes low, PC1and PC2are once again pre-charged high and the states of Q and QB are maintained.

FIG. 5is a schematic diagram of the full keeper circuit108according to an exemplary embodiment. Node105providing the PC2signal is coupled to the input of an inverter I4, which has its output coupled to node501to drive an inverted precharge signal PC2B. A P-channel device P6has its source coupled to VDD, its gate coupled to VSS, and its drain coupled to the source of another P-channel device P7. P7has its drain coupled to node105and its gate coupled to node501. An N-channel device N9has its drain coupled to node105, its gate coupled to node501, and its source coupled to the drain of another N-channel device N10. N10has its gate coupled to VDD and its source coupled to VSS. P6and N10are kept on and generally operate to make the keeper circuit108weaker. In one embodiment, P6and N10are long-channel devices. It is noted that P7and N9may alternatively be made as long-channel devices thereby eliminating P6and N10, except that such configuration would increase the gate capacitance of P7and N9so that the drive capacity of the inverter I4would be increased.

In operation of the keeper circuit108, when CLK is low, PC2is pre-charged high as previously described and the inverter I4drives PC2B low turning on P7and turning off N9. Thus, PC2is pulled high via P6and P7. When CLK goes high, if PC2stays high and is not otherwise driven low, the inverter I4maintains PC2B to keep PC2pulled high via P6and P7. If PC2is driven low by the inverter I2, then the inverter14switches to pull PC2B high turning on N9and turning off P7. PC2is pulled low via N9and N10while CLK is high. When CLK goes back high, PC2is once again pre-charged high pulling PC2B low. In an alternative embodiment, the full keeper circuit108is configured as a clocked full keeper circuit using clock signals CLK and CLKB as understood by those of ordinary skill in the art.

FIG. 6is a timing diagram illustrating operation of the fast dynamic register100according to one embodiment. The signals CLK, CLKB, D, PC1, PC2, PO, Q and QB are plotted versus time. The CLK signal is low at an initial time t0and generally toggles between high and low logic values at a selected frequency with any suitable duty cycle, such as, for example, a 50% duty cycle. It is noted that successful register operation is achieved without CLK having to be pulsed. CLKB toggles in similar manner opposite CLK with slight delay (operation of inverter I2). D is initially low and PC1and PC2are both pre-charged high at time t0. PO and QB are both initially high and Q is low. D goes high at about time t1just before CLK goes high at subsequent time t2. Since D and CLK are both high at time t2, PC1is discharged through N1and N2just after time t2and thus goes low at subsequent time t3. CLKB also goes low at about time t3even though N5is turned off so that PC2remains asserted high after time t2. Since Q and CLK are both low before time t2, PO is held high via P4and P5. As CLK goes high, P5turns off while N6turns on so that PO is pulled low via N6and N7after time t2at about time t3. The inverter I3pulls Q high at subsequent time t4in response to PO going low. The output signal QB goes low at about time t5in response to Q going high. Anytime after time t3when PC1falls low, D may change state without affecting operation. As shown at602, D toggles several times after time t3with no effect on the signals PC1, PC2, PO, Q or QB.

CLK goes back low at about time t6. The inverter I2pulls CLKB high and P2pre-charges PC1back high at subsequent time t7and PC2stays high. Since Q is high after time t6, N8is turned on keeping PO low, so that the inverter I3keeps Q high while CLK is low. At subsequent time t8, D goes low just before CLK goes back high at subsequent time t9. N1is turned off so that PC1remains high just after time t9. The inverter I2pulls CLKB low at time t10turning N5on since PC1remains high. The inverter I2further pulls PC2low at subsequent time t11as N5turns on. As PC2goes low, it turns P3on which pulls PO high at subsequent time t12. Also, the output circuit106pulls QB high at about time t12. The inverter I3pulls Q low at subsequent time t13in response to PO going high. Anytime after time t11when PC2is low, D may change state without affecting operation. As shown at604, D toggles several times after time t11with no effect on the signals PC2, PO, Q or QB. This is true even though PC1goes low in response to D going high as shown at606, where PC1stays low until precharged once again when CLK next goes low at time t14. When CLK next goes low at subsequent time t14, PC1and PC2are once again pre-charged high and CLKB also goes high at subsequent time t15. Further toggling of D has no effect during the pre-charged state. Since Q and CLK are both low, PO is held high via P4and P5, so that the inverter I3keeps Q low while CLK is low.

CLK goes high once again at time t16while D is low and while PC2is still high. As CLK rises, N6is turning on while P5is turning off. There is a slight contention since while the pull up of P4and P5for PO is turning off, the pull down of N6and N7for PO starts turning on. In one embodiment, P4and P5are configured as weak keeper devices. Meanwhile, CLKB goes low at subsequent time t17turning N5on since PC1remains high. As N5turns on, PC2discharges low at subsequent time t18. PC2eventually turns N7off removing the pull down of N6and N7, and PC2turns P3on adding further pull up on PO. The devices are sized and configured to maintain PO high after time t17, although a slight “glitch” shown at608may appear on PO as previously described. The slight dip of PO shown at608has no effect since the inverter I3does not change state, so that the states of PO, Q and QB remain unmodified.

FIG. 7is a block diagram of a fast dynamic register700operating as a multi-input NOR gate according to one embodiment. The register700is configured in similar manner as the register100except that the precharge circuit102is replaced by a similar precharge circuit702. The remaining portion of the register700is configured in substantially identical manner as the register100including the precharge circuit104, the output circuit106and the keeper circuit108coupled together in the same manner. The precharge circuit702has four inputs for receiving a corresponding four input signals D1, D2, D3and D4and asserts the PC1signal at its output on node103.FIG. 8is a logic truth table of the inputs D1-D4and the output QB illustrating logical operation of the register700configured as a NOR gate. If each of the inputs D1-D4is a logic zero (0) as shown in the first row of the truth table, then the output QB is a logic one (1). Otherwise, if any of the inputs D1-D4is a logic one, as shown in the remaining 4 rows of the table, then the output QB is a logic zero regardless of the logic value of the other inputs (as illustrated by an “X” denoting a “don't care” value).

FIG. 9is a schematic diagram of the precharge circuit702according to one embodiment. The precharge circuit702is configured in substantially the same manner as the precharge circuit102, except that N1is replaced by four N-channel devices N11, N12, N13and N14effectively coupled in parallel between node103and the drain of N2. In particular, the drains of N11-N14are coupled together at node103and the sources of N11-N14are coupled together and to the drain of N2. D1is provided to the gate of N11, D2is provided to the gate of N12, D3is provided to the gate of N13, and D4is provided to the gate of N14. In operation, if D1-D4are each low at the rising edge of CLK, then PC1remains high and QB is asserted high in a similar manner as previously described. If instead any one of D1-D4is high at the rising edge of CLK, then PC1is discharged low by the inverter I2and QB is asserted low in a similar manner as previously described.

FIG. 10is a block diagram of a fast dynamic register1000operating as a multi-input NAND gate according to one embodiment. The register1000is configured in similar manner as the register100except that it includes a pair of precharge circuits102each configured in the same manner and receiving a corresponding data signal and providing a corresponding PC1signal. In particular, a first precharge circuit102, shown as PC1_1, receives a first data signal D1and provides a corresponding output signal PC1_1, and a second precharge circuit102, shown as PC1_2, receives a second data signal D2and provides a corresponding output signal PC1_2. Although only two precharge circuits102are shown, additional precharge circuits102may be included to increase the number of inputs of the register1000. The precharge circuit104is replaced by a similar precharge circuit1004, which receives the PC1signals PC1_1and PC1_2and which provides the PC2signal to the output circuit106. The full keeper circuit108is replaced by another full keeper circuit1008which is further described below.FIG. 11is a logic truth table of the inputs D1and D2and the output QB illustrating logical operation of the register1000configured as a NAND gate. In accordance with NAND gate operation, if either of the inputs D1or D2is a logic zero as shown in the first three rows of the truth table ofFIG. 11, then the output QB is a logic one. Otherwise, if both inputs D1and D2are logic ones, as shown in the fourth row of the truth table, then the output QB is a logic zero.

FIG. 12is a schematic diagram of the precharge circuit1004according to one embodiment. The precharge circuit1004is configured in a similar manner as the precharge circuit104, except that N5is replaced by a pair of N-channel devices N15and N16coupled in parallel between nodes105and301for receiving multiple input signals on corresponding input nodes. In particular, the drains of N15-N16are coupled together at node105and the sources of N15-N16are coupled together at node301. D1is provided to the gate of N15and D2is provided to the gate of N16. In operation, if either D1or D2is low at the rising edge of CLK, then the corresponding PC1signal (PC1_1or PC1_2) remains high and QB is asserted high in a similar manner as previously described. For example, if D1is high when CLK goes high, then PC1_1remains high and N15turns on as the inverter I2pulls node301low. If instead both D1and D2are high at the rising edge of CLK, then both PC1_1and PC1_2are discharged low so that PC2stays high and QB is asserted low. Several other circuit modifications may be made. The size of the inverter I2may be increased to turn on multiple N-channel devices more quickly. Also, although only two inputs are shown, additional precharge circuits102may be included in the register1000in which the precharge circuit1004is configured with additional N-channel devices in parallel to receive more input signals. Operation is similar in that the output QB is high unless each of the inputs is high upon the rising edge of CLK.

FIG. 13is a schematic diagram of the full keeper circuit1008according to one embodiment. A P-channel device P8has its source coupled to VDD, its drain coupled to node105, and its gate coupled to node1001developing the inverted PC2B signal. The input of an inverter I5is coupled to node105and its output is coupled to node1001. Node105is further coupled to the drain of an N-channel device N17, having its gate coupled to node1001and its source coupled to the drain of another N-channel device N18. The gate of N18is coupled to VDD and its source is coupled to VSS. In operation, N18remains turned on. When node105is high, the inverter I5pulls node1001low turning on P8to keep node105pulled high. When node105is low, the inverter I5pulls node1001high turning on N17to keep node105pulled low through N17and N18.

A fast dynamic register according to embodiments of the present invention are particularly advantageous on integrated circuits such as shown inFIG. 14. As shown, an integrated circuit1402incorporates any type of combinatorial logic1404generating one or more data signals DN which are registered by a corresponding one or more fast dynamic registers1406implemented as described herein. Although only one combinatorial logic1404and one set of dynamic registers1406is shown, it is appreciated that additional logic and registers may be included as needed or desired. For example, multiple sets of dynamic registers are contemplated, such as implementing one or more pipeline stages. The integrated circuit1402may be implemented according to any desired function or implementation, such as a microprocessor or the like. An integrated circuit incorporating fast dynamic registers according to that described herein provides many advantages. The integrated fast dynamic register logic has significantly reduced setup and hold times as compared to conventional register circuits enabling faster logic circuits that may be clocked at increased speeds. Furthermore, pulse clock logic is avoided since the fast dynamic register achieves minimal setup and hold times without the use of a pulsed clock signal.

A fast dynamic register circuit according the various embodiments as described herein includes first and second precharge circuits, a keeper circuit and an output circuit. The first and second precharge circuits each precharge a corresponding one of a pair of precharge nodes and cooperate to minimize setup and hold times. If an input data node is low when the clock goes high, the first precharge node remains high which causes the second precharge node to be discharged. Otherwise if the input node is high, the first precharge node is discharged and the second remains charged. Once either precharge node is discharged, the output state of the register remains fixed until the next rising clock edge independent of changes of the input data node. The fast dynamic register may be implemented with multiple inputs to perform common logic operations, such as OR, NOR, AND and NAND logic operations. Note, for example, that the NOR configuration ofFIG. 7may be converted to an OR configuration by inverting the output. Likewise, the NAND configuration ofFIG. 10is easily converted to an AND configuration in similar manner.

Although the present invention has been described in considerable detail with reference to certain preferred versions thereof, other versions and variations are possible and contemplated. For example, the circuits described herein may be implemented in any suitable manner including logic devices or circuitry or the like. Any number of the functions described for the logic circuits may be implemented in software or firmware within an integrated device. Those skilled in the art should appreciate that they can readily use the disclosed conception and specific embodiments as a basis for designing or modifying other structures for carrying out the same purposes of the present invention without departing from the spirit and scope of the invention as defined by the appended claims.