Semiconductor device having metal bit line

Disclosed herein is a device that includes: a semiconductor substrate including a memory cell region and a peripheral circuit region arranged around the memory cell region; an element isolation region formed in the memory cell region and the peripheral circuit region; a cell active region defined by the element isolation region formed in the memory cell region; a first interlayer insulation film disposed on the cell active region, the first interlayer insulation film having a bit contact hole passing therethrough to expose a portion of an upper surface of the cell active region; and a bit line having a first metal laminated film, the bit line being disposed on the first interlayer insulation film so as to fill the bit contact hole.

BACKGROUND OF THE INVENTION

The present invention relates to a semiconductor device and a method of manufacturing the semiconductor device.

As one of semiconductor devices, there is DRAM (Dynamic Random Access Memory) that includes a memory cell section which contains word lines and bit lines, and a peripheral circuit section which is arranged around the memory cell section and drives memory cells of the memory cell section.

In order to respond to demands for miniaturization, the DRAM employs a structure in which the word lines that select the memory cells are embedded in a semiconductor substrate and the bit lines are formed on the semiconductor substrate (For example, see Japanese Patent Application Laid-open No. 2011-129771).

Japanese Patent Application Laid-open No. 2011-129771 discloses a method of forming at once gate electrodes of planar transistors in a peripheral circuit region along with bit lines when the bit lines are formed in a memory cell region.

More specifically, first, a laminated film is formed as a high-concentration n-type impurity implantation polysilicon film, a metal film and a silicon nitride film are laminated on both the memory cell region and the peripheral circuit region.

The high-concentration n-type impurity implantation polysilicon film and metal film formed on the memory cell region are conductive films that are used as base material of the bit lines. The high-concentration n-type impurity implantation polysilicon film and metal film formed on the peripheral circuit region are conductive films that are used as base material of the gate electrodes of planar transistors, which are disposed in the peripheral circuit region.

After that, the photolithographic and dry-etching techniques are used to perform patterning of the laminated film. As a result, the bit lines that are disposed on the memory cell region, and the gate electrodes of the planar transistors that are disposed on the peripheral circuit region are formed at once.

In the case of Japanese Patent Application Laid-open No. 2011-129771, the bit lines and the gate electrodes of the planar transistors disposed in the peripheral circuit region employ a poly-metal gate structure.

The poly-metal gate structure is made up of a polysilicon film and a metal film, which is laminated on the polysilicon film.

FIG. 15is a cross-sectional view illustrating a process of manufacturing a structure (or a structure containing bit lines) that is disposed on the memory cell region.FIG. 15is an enlarged cross-sectional view of a portion in which a bit line contact plug306and a bit line321are placed, in a memory cell section300that is disposed in the memory cell region.

FIG. 16is across-sectional view illustrating a process of manufacturing a structure (or a structure containing gate electrodes of planar transistors) that is disposed on the peripheral circuit region.FIG. 16is an enlarged cross-sectional view of a region in which a gate electrode335of a planar transistor is placed, in a peripheral circuit section330that is disposed in the peripheral circuit region. InFIG. 16, the same components as those of the memory cell section300shown inFIG. 15are represented by the same reference symbols.

With reference toFIG. 15, a method of manufacturing the memory cell section300disposed in the memory cell region will be described.

First, the well-known photolithographic and dry-etching techniques are used to form a bit contact hole304A: the bit contact hole304A passes through a bit-contact interlayer insulation film304, which covers an upper surface of an active region301and an upper surface of an element isolation region302defining the active region301(cell active region), and the bit contact hole304A exposes the upper surface of the active region301.

Then, a well-known technique is used to fill the bit contact hole304A with polysilicon film. As a result, what is formed is a bit line contact plug306that is made of the polysilicon film and whose lower end is in contact with the upper surface of the active region301.

Then, a well-known technique is used to sequentially laminate a Poly-Si film308, which covers an upper end surface of the bit line contact plug306and an upper surface of the bit-contact interlayer insulation film304, a metal laminated film309, and a silicon nitride film312.

The metal laminated film309is formed by sequentially laminating a TiSi film314, a TiN film315, a WSi film316, and a W film317.

Then, a well-known technique is used to perform patterning of the silicon nitride film312. As a result, what is formed is a cap insulation film319that is made of the silicon nitride film312and which covers an upper surface of the W film317corresponding to a formation region of the bit line321.

Then, the cap insulation film319is used as an etching mask, and patterning of the Poly-Si film308and the metal laminated film309by anisotropic dry etching is performed. As a result, what is formed is the bit line321that is made up of the Poly-Si film308and the metal laminated film309.

Then, a well-known technique is used to form a sidewall323that covers a side surface of the bit line321and a side surface of the cap insulation film319.

Then, a well-known technique is used to form a capacitance-contact interlayer insulation film325, which fills the space formed between adjacent sidewalls323. In this manner, the memory cell section300is produced.

With reference toFIG. 16, a method of manufacturing the peripheral circuit section330disposed in the peripheral circuit region will be described.

First, a well-known technique is used to form a gate insulation film333on an active region331(or an active region where a peripheral-circuit transistor is formed) that is located in the peripheral circuit region.

Then, on an upper surface of the gate insulation film333, a step-reduction Poly-Si film334, a Poly-Si film308, a metal laminated film309, and a silicon nitride film312are sequentially laminated.

Incidentally, the Poly-Si film308, the metal laminated film309, and the silicon nitride film312are formed at the same time for the peripheral circuit region and the memory cell region.

Then, a well-known technique is used to perform patterning of the silicon nitride film312. As a result, what is formed is a cap insulation film319that is made of the silicon nitride film312and which covers an upper surface of the W film317corresponding to a formation region of the gate electrode335of the planar transistor.

Then, the cap insulation film319is used as an etching mask, and patterning of the step-reduction Poly-Si film334, the Poly-Si film308, and the metal laminated film309by anisotropic dry etching is performed. As a result, what is formed is the gate electrode335that is made up of the step-reduction Poly-Si film334, the Poly-Si film308, and the metal laminated film309. The gate electrode335is formed at the same time as the bit line321, which is disposed in the memory cell region, is formed.

After that, a well-known technique is used to form an interlayer insulation film337, which fills the space between the gate electrodes335. In this manner, the peripheral circuit section330is formed.

The step-reduction Poly-Si film334is a film that is designed to offset a difference in height between the bit line321and the gate insulation film333disposed in the peripheral circuit region, which is caused by a step that is equal in thickness to the bit-contact interlayer insulation film304between the memory cell region and the peripheral circuit region.

The bit line321is made up of the Poly-Si film308and metal laminated film309that are laminated. The gate electrode335disposed in the peripheral circuit region is made up of the step-reduction Poly-Si film334, Poly-Si film308, and metal laminated film309that are laminated.

The problem is that the use of Poly-Si film (i.e. the Poly-Si film308and the step-reduction Poly-Si film334), which is higher in resistance than metal, leads to an increased wiring resistance as the miniaturization goes on. In particular, this problem becomes conspicuous when the Poly-Si film308is used in the bit line321.

SUMMARY

In one embodiment, there is provided a semiconductor device that includes: a semiconductor substrate including a memory cell region and a peripheral circuit region arranged around the memory cell region; an element isolation region formed in the memory cell region and the peripheral circuit region; a cell active region defined by the element isolation region formed in the memory cell region; a first interlayer insulation film disposed on the cell active region, the first interlayer insulation film having a bit contact hole passing therethrough to expose a portion of an upper surface of the cell active region; and a bit line having a first metal laminated film, the bit line being disposed on the first interlayer insulation film so as to fill the bit contact hole.

According to the semiconductor device of the present invention, a first interlayer insulation film is formed so as to cover an upper surface on a cell active region and an upper surface of a silicon film. Then, anisotropic dry etching is performed to form a bit contact hole that passes through the first interlayer insulation film and exposes a portion of the upper surface of the cell active region, as well as to remove the first interlayer insulation film disposed on the silicon film. Then, a metal laminated film, which covers an upper surface of the first interlayer insulation film and an upper surface of the silicon film, is formed so as to fill the bit contact hole. Then, patterning of the metal laminated film and the silicon film is performed. As a result, a bit line, which is made of the metal laminated film and fills the bit contact hole, and a gate electrode of a peripheral circuit transistor, which is made up of the metal laminated film and a step-reduction silicon film, are formed at once. Therefore, without the use of a bit line contact plug made of silicon film, the bit line, which is made of the metal laminated film (i.e., the bit line that does not contain, among its components, a silicon film that is higher in resistance than metal), can be connected directly to the cell active region (or an active region where an impurity diffusion region is formed).

Therefore, even if the memory cell section is miniaturized (or if the diameter of the opening of the bit contact hole is made smaller), a rise in the resistance of the bit line is curbed.

Moreover, on the main surface of the semiconductor substrate that corresponds to the peripheral circuit region, an insulation film, which serves as base material of the peripheral circuit gate insulation film, a silicon film, which serves as base material of the step-reduction silicon film, and the first interlayer insulation film are sequentially formed. Then, in the first interlayer insulation film, the bit contact hole is formed so as to expose the upper surface of the cell active region, and the first interlayer insulation film formed in the peripheral circuit region is removed. Then, the metal laminated film, which covers the upper surface of the first interlayer insulation film and the upper surface of the silicon film, is formed so as to fill the bit contact hole. Then, patterning of the metal laminated film and the silicon film is performed. As a result, the bit line, which is made of the metal laminated film, and the gate electrode of the peripheral circuit transistor, which is made up of the metal laminated film and the step-reduction silicon film, are formed at once. In this manner, the thickness of the bit line disposed on the first interlayer insulation film can be reduced by an amount equivalent to the thickness of the step-reduction silicon film.

Therefore, the parasitic capacitance of the bit line can be reduced. Thus, it is possible to increase the accuracy of the operation of the semiconductor device (or, more specifically, the accuracy of the operation of DRAM, for example).

Furthermore, when the bit contact hole is formed, the first interlayer insulation film disposed above the peripheral circuit region is removed. Therefore, there is no need to separately provide a step of removing the first interlayer insulation film disposed above the peripheral circuit region. Thus, it is possible to reduce the number of manufacturing steps for the semiconductor device.

Moreover, in planar view, the area of the silicon film disposed above the peripheral circuit region is quite large. Therefore, when the bit contact hole is formed by anisotropic dry etching, the time when the silicon film becomes exposed can be easily detected as an end point of etching following the disappearance of the first interlayer insulation film disposed above the peripheral circuit region.

DETAILED DESCRIPTION OF THE EMBODIMENTS

Hereinafter, an embodiment of the present invention will be described in detail with reference to the accompanying drawings. Incidentally, for ease of explanation, some of the drawings used in the following description are enlarged views of characteristic portions in order to make the characteristics easy-to-understand; dimensions, proportions, and other factors of each component are not necessarily identical to those of actual components.

The materials, dimensions and other factors illustrated below are one example. The present invention is not necessarily limited to them. The present invention may be appropriately modified and embodied without changing the subject matter of the invention.

Referring now toFIG. 1, the positional relationship between element isolation regions15-1and15-2, cell active regions17, peripheral active regions18, first and second grooves21and22, embedded gate electrodes83and91, bit lines33, and gate electrodes109of components included in the semiconductor device10of the present embodiment is shown.

Accordingly, the only things that are shown inFIG. 1are the element isolation regions15-1and15-2, the cell active regions17, the peripheral active regions18, the first and second grooves21and22, the embedded gate electrodes83and91, the bit lines33, and the gate electrodes109of the components included in the semiconductor device10of the present embodiment. The other components included in the semiconductor device10are not shown inFIG. 1.

As one example of the semiconductor device10of the present embodiment,FIGS. 1 to 5show DRAM (Dynamic Random Access Memory). InFIGS. 1 to 5, the same components are represented by the same reference symbols.

InFIGS. 1 to 5, an X-direction indicates a direction in which the bit lines33and the gate electrodes109(or gate electrodes of peripheral circuit transistors41) extend. A Y-direction indicates a direction in which the first and second grooves21and22and the embedded gate electrodes83and91extend.

InFIGS. 1 to 5, an X1-direction indicates a direction in which the cell active regions17extend. A Z-direction indicates a thickness direction of a semiconductor substrate13.

With reference toFIGS. 1 to 5, the semiconductor device10of the present embodiment includes a memory cell section11, which is provided in a memory cell region E; and a peripheral circuit section12, which is provided in a peripheral circuit region F that is located around the memory cell section11.

The semiconductor device10includes the semiconductor substrate13; the element isolation regions15-1and15-2; the cell active regions17; the peripheral active regions18; the first and second grooves21and22(two grooves); first and second transistors25and26; embedded insulation films27; a first interlayer insulation film28; bit contact holes28A; the bit lines33; cover insulation films34-1and34-2; sidewalls36-1and36-2; peripheral circuit transistors41; a second interlayer insulation film43; first contact holes45and46; second contact holes48; capacitance contact plugs51and52; first contact plugs53; first wiring patterns55; stopper films57; a third interlayer insulation film59; cylinder holes62; capacitors64; first and second memory cells MC1and MC2; a fourth interlayer insulation film66; third contact holes68; second contact plugs71; second wiring patterns73; and a protective insulation film75.

The semiconductor substrate13is a plate-like substrate. The semiconductor substrate13includes the memory cell region E and the peripheral circuit region F, which is located around the memory cell region E.

For example, the semiconductor substrate13may be a p-type single crystal silicon substrate, a n-type single crystal silicon substrate, a TFT silicon substrate, or the like.

Hereinafter, as one example of the semiconductor substrate13, the case where the p-type single crystal silicon substrate is used will be described.

The element isolation regions15-1are formed in the memory cell region E of the semiconductor substrate13to define a plurality of cell active regions17. The element isolation regions15-1include first portions, which extend in the X1-direction and are arranged at predetermined intervals in the Y-direction; and second portions, which extend in the Y-direction and are arranged at predetermined intervals in the X-direction.

The element isolation regions15-1include a first element isolation groove (not shown), which is disposed in the memory cell region E; and a first element isolation insulation film (not shown), which fills the first element isolation groove and whose upper surface is flush with a main surface13aof the semiconductor substrate13.

The depth of the first element isolation groove (not shown) relative to the main surface13aof the semiconductor substrate13is configured so as to be deeper than the depth of the first and second grooves21and22.

For example, the first element isolation insulation film (not shown) may be a silicon oxide film (SiO2film), a silicon nitride film (SiN film), a laminated film of those films, or the like.

The element isolation regions15-2are formed in the peripheral circuit region F of the semiconductor substrate13to define a plurality of peripheral active regions18. The element isolation regions15-2include first portions, which extend in the X-direction and are arranged at predetermined intervals in the Y-direction; and second portions, which extend in the Y-direction and are arranged at predetermined intervals in the X-direction.

The element isolation regions15-2include a second element isolation groove (not shown), which is disposed in the peripheral circuit region F; and a second element isolation insulation film (not shown), which fills the second element isolation groove and whose upper surface is flush with the main surface13aof the semiconductor substrate13.

The element isolation regions15-1and15-2can be formed at once.

The depth of the second element isolation groove (not shown) relative to the main surface13aof the semiconductor substrate13may be equal to the depth of the first element isolation groove (not shown) formed in the memory cell region E.

The second element isolation insulation film (not shown) may be made of the same insulation film as that of the first element isolation insulation film (not shown).

The cell active regions17are regions of the semiconductor substrate13that are defined by the element isolation regions15-1. One cell active region17is defined by two first portions (which are two of the above first portions included in the element isolation regions15-1) that are arranged adjacent to each other in the Y-direction, and two second portions (which are two of the above second portions included in the element isolation regions15-1) that are arranged adjacent to each other in the X-direction. Therefore, the cell active region17extends in the X1-direction.

A plurality of cell active regions17are disposed at predetermined intervals in the X1- and Y-directions. In each of the cell active regions17, the first and second transistors25and26are placed (i.e., the two transistors are placed in each of the cell active regions17).

For example, the distance between the cell active regions17that are disposed adjacent to each other in the Y-direction may be equal to the width of the Y-direction cell active regions17, or may be smaller; the distance is not particularly limited.

Incidentally, as one example of the shape of the cell active regions17,FIG. 1shows a parallelogram that has the long sides in the X1-direction and whose corners have been rounded. However, the shape of the cell active regions17is not limited to this shape. For example, as the shape of the cell active regions17, a parallelogram may be used.

The peripheral active regions18are regions of the semiconductor substrate13that are defined by the element isolation regions15-2. One peripheral active region18is defined by two first portions (which are two of the above first portions included in the element isolation regions15-2) that are arranged adjacent to each other in the Y-direction, and two second portions (which are two of the above second portions included in the element isolation regions15-2) that are arranged adjacent to each other in the X-direction. Therefore, the peripheral active region18extends in the Y-direction.

A plurality of peripheral active regions18are disposed at predetermined intervals in the X- and Y-directions. In each of the peripheral active regions18, one peripheral circuit transistor41is placed.

Incidentally, the shape, number, arrangement, and other factors of the peripheral active regions18shown inFIG. 1are one example. The peripheral active regions18are not limited to this example.

The first and second grooves21and22extend in the Y-direction, and are provided in the memory cell region E of the semiconductor substrate13. The first and second grooves21and22are disposed so as to divide an upper portion of one cell active region17into three.

The first and second grooves21and22are placed in such a way as to go over a plurality of cell active regions17arranged in the Y-direction, and the element isolation regions15-1disposed between the cell active regions17.

The depth of the first and second grooves21and22relative to the main surface13aof the semiconductor substrate13is configured so as to be smaller than the depth of the element isolation regions15-1and15-2. The depth of the first and second grooves21and22is 150 nm, for example.

The first and second transistors25and26are cell transistors (selection transistors), and are provided in the cell active regions17. One first transistor25and one second transistor26are provided in the same cell active region17. The first and second transistors25and26are placed adjacent to each other in the direction (X1-direction) in which the cell active regions17extend.

The first transistor25includes a gate insulation film81, an embedded gate electrode83, a first capacitance impurity diffusion region85, and a bit line impurity diffusion region87.

The gate insulation film81is placed in such a way as to cover an inner surface of the first groove21formed in the cell active region17.

For example, the gate insulation film81may be a single-layer silicon oxide film (SiO2film), a silicon oxynitride film (SiON film), a laminated silicon oxide film (SiO2film), a laminated film made by laminating a silicon nitride film (SiN film) on a silicon oxide film (SiO2film), or the like.

The embedded gate electrode83is placed in such a way as to fill a lower portion of the first groove21through the gate insulation film81.

As a metal film that constitutes the embedded gate electrode83, for example, a laminated film made by sequentially laminating a titanium nitride film (TiN film) and a tungsten film (W film) may be used.

The first capacitance impurity diffusion region85is disposed in one end portion17A of a cell active region17that is located between an upper portion of the first groove21and the element isolation region15-1(i.e., in the cell active region17that makes up one side surface of the first groove21(InFIG. 3, the side surface of the first groove21that is closer to the element isolation region15-1)). The first capacitance impurity diffusion region85functions as a source/drain region of the first transistor25.

If the depth of the first groove21is 150 nm and the Z-direction height of the embedded gate electrode83is 80 nm, the depth of the first capacitance impurity diffusion region85relative to the main surface13aof the semiconductor substrate13may be 70 nm, for example.

The bit line impurity diffusion region87is placed in a central portion of the cell active region17that is located between an upper portion of the first groove21and an upper portion of the second groove22(i.e., in the cell active region17that makes up the other side surface of the first groove21(InFIG. 3, the side face of the first groove21that is closer to the second groove22)).

The bit line impurity diffusion region87functions a common impurity diffusion region (source/drain region) for the first and second transistors25and26that are placed in the cell active region17(or the same active region).

If the depth of the first and second grooves21and22is 150 nm and the Z-direction height of the embedded gate electrode83is 80 nm, the depth of the bit line impurity diffusion region87relative to the main surface13aof the semiconductor substrate13may be 70 nm, for example.

If the semiconductor substrate13is a p-type single crystal silicon substrate, the first capacitance impurity diffusion region85and the bit line impurity diffusion region87may be n-type impurity diffusion regions, for example.

The second transistor26includes a gate insulation film81, an embedded gate electrode91, a second capacitance impurity diffusion region93, and a bit line impurity diffusion region87.

The gate insulation film81is placed in such a way as to cover an inner surface of the second groove22formed in the cell active region17.

The embedded gate electrode91is placed in such a way as to fill a lower portion of the second groove22through the gate insulation film81.

As a metal film that constitutes the embedded gate electrode91, for example, the same metal film that constitutes the embedded gate electrode83may be used.

The second capacitance impurity diffusion region93is disposed in the other end portion17B of a cell active region17that is located between an upper portion of the second groove22and the element isolation region15-1(i.e., in the cell active region that makes up one side surface of the second groove22(InFIG. 3, the side surface of the second groove22that is closer to the element isolation region15-1)). The second capacitance impurity diffusion region93functions as a source/drain region of the second transistor26.

If the depth of the second groove22is 150 nm and the Z-direction height of the embedded gate electrode91is 80 nm, the depth of the second capacitance impurity diffusion region93relative to the main surface13aof the semiconductor substrate13may be 70 nm, for example.

If the semiconductor substrate13is a p-type single crystal silicon substrate, the second capacitance impurity diffusion region93may be a n-type impurity diffusion region, for example.

The embedded insulation films27are placed so as to fill upper portions of the first and second grooves21and22. Therefore, an upper surface of the embedded gate electrode83placed in the lower portion of the first groove21, and an upper surface of the embedded gate electrode91placed in the lower portion of the second groove22are covered with the embedded insulation films27, respectively. The upper surfaces of the embedded insulation films27are flush with the main surface13aof the semiconductor substrate13.

For example, each of the embedded insulation films27may be a silicon oxide film (SiO2film), a silicon nitride film (SiN film), a laminated film of those films, or the like.

The first interlayer insulation film28is provided in the memory cell region E (including the cell active region17). The first interlayer insulation film28is placed in such a way as to cover an upper surface of the element isolation region15-1and upper surfaces of the embedded insulation films27.

For example, the first interlayer insulation film28may be a silicon oxide film (SiO2film) formed by CVD (Chemical Vapor Deposition) method, or a coating-type insulation film (silicon oxide film (SiO2film)) formed by SOG (Spin On Glass) method.

The bit contact hole28A is provided in the first interlayer insulation film28in such away as to pass through the first interlayer insulation film28located on the bit line impurity diffusion region87and to expose an upper surface87aof the bit line impurity diffusion region87(or part of the upper surface17aof the cell active region17).

The bit line33is placed on the first interlayer insulation film28in such a way as to fill the bit contact hole28A and extend in the X-direction.

Therefore, a lower end of the bit line33is connected directly to the upper surface87aof the bit line impurity diffusion region87(or the surface that is flush with the main surface13aof the semiconductor substrate13and the upper surface17aof the cell active region17).

The bit line33is made of a first metal laminated film97-1, which does not contain any film other than metal film (e.g. a silicon film or the like that is higher in resistance than the metal film).

In that manner, without using a bit line contact plug made of silicon film, the bit line33, which is made of the first metal laminated film97-1(i.e., the bit line that does not contain, among its components, a silicon film that is higher in resistance than metal), can be connected directly to the bit line impurity diffusion region87formed in the cell active region17.

Therefore, even if the memory cell section11is miniaturized (or if the diameter of the opening of the bit contact hole28A is made smaller), a rise in the resistance of the bit line33is curbed.

In the first metal laminated film97-1, a metal silicide film101, a titanium nitride film102, a tungsten silicide film103, and a tungsten film104are sequentially laminated.

The metal silicide film101is a metal film that is placed on the bottom layer, among the metal films that make up the first metal laminated film97-1. The metal silicide film101is placed so as to cover the upper surface87aof the bit line impurity diffusion region87, which is exposed via the bit contact hole28A. For example, the metal silicide film101may be a titanium silicide film.

In this manner, the metal silicide film101, which is placed on the bottom layer of the first metal laminated film97-1that constitutes the bit line33, is placed in such a way as to cover the upper surface87aof the bit line impurity diffusion region87, which is exposed via the bit contact hole28A. Therefore, it is possible to lower the contact resistance between the bit line33and the bit line impurity diffusion region87(or the impurity diffusion region made of single crystal silicon containing n-type impurities).

The thickness of each of the films that make up the first metal laminated film97-1may be as follows: the metal silicide film101is 5 nm, the titanium nitride film102is 10 nm, the tungsten silicide film103is 2 nm, and the tungsten film104is 20 nm.

In this case, if the opening diameter of the bit contact hole28A is 30 nm and the depth thereof is 20 nm, the bit contact hole28A is filled with the metal silicide film101, the titanium nitride film102, and the tungsten silicide film103.

If the opening diameter of the bit contact hole28A is reduced to 20 nm or less, the bit contact hole28A is filled with the metal silicide film101and the titanium nitride film102. In either case, the metal laminated film placed on the first interlayer insulation film28is made up of the three-layer films, or the titanium nitride film102, the tungsten silicide film103, and the tungsten film104.

Incidentally, in the present embodiment, the film in which the metal silicide film101, the titanium nitride film102, the tungsten silicide film103, and the tungsten film104are sequentially laminated is described as one example of the first metal laminated film97-1. However, the metal films that make up the first metal laminated film97-1are not limited to those films; the metal films may be appropriately selected.

The cover insulation film34-1is disposed so as to cover an upper surface of the bit line33. An upper surface of the cover insulation film34-1is flat. The cover insulation film34-1protects the upper surface of the bit line33, and functions as an etching mask when patterning is performed by anisotropic dry etching of a metal laminated film (or a metal laminated film97shown inFIG. 10A, described later), which serves as base material of the bit line33. The film used as base material of the cover insulation film34-1may be a silicon nitride film (SiN film), for example.

The cover insulation film34-2is disposed so as to cover an upper surface of the gate electrode109that is part of the peripheral circuit transistor41. The upper surface of the cover insulation film34-2is flat. The cover insulation film34-2protects the upper surface of the gate electrode109, and functions as an etching mask when patterning is performed by anisotropic dry etching of a metal laminated film (or the metal laminated film97shown inFIG. 10A, described later), which serves as base material of the gate electrode109.

The film used as base material of the cover insulation film34-2may be a silicon nitride film (SiN film), for example.

The sidewalls36-1are disposed so as to cover side surfaces of the bit line33and side surfaces of the cover insulation film34-1.

The sidewalls36-2are disposed so as to cover side surfaces of the gate electrode109that is part of the peripheral circuit transistor41, and side surfaces of the cover insulation film34-2. The Y-direction width of each of the sidewall36-2is equal to the Y-direction width of a low-concentration impurity diffusion region112.

The sidewalls36-2function as a mask when a pair of high-concentration impurity diffusion regions113is formed in the peripheral active region18by ion implantation method.

The insulation film that constitutes the sidewalls36-1and36-2may be a silicon nitride film (SiN film), for example.

The peripheral circuit transistor41is a planar transistor provided in the peripheral active region18. The peripheral circuit transistor41includes a peripheral circuit gate insulation film108, a gate electrode109, a pair of low-concentration impurity diffusion regions112, and a pair of high-concentration impurity diffusion regions113.

The peripheral circuit gate insulation film108is placed at the center of an upper surface18a(or a surface that is flush with the main surface13aof the semiconductor substrate13located in the peripheral circuit region F) of the peripheral active region18.

For example, the peripheral circuit gate insulation film108may be a high dielectric constant film (High-K film) that has a dielectric constant of 3.9 or more and which is higher than the relative permittivity of a thermally-oxidized film. For example, the high dielectric constant film (High-K film) may be an insulation film containing hafnium oxide, tantalum oxide, lanthanum oxide, or the like.

In that manner, as the peripheral circuit gate insulation film108, the high dielectric constant film (High-K film), which has a dielectric constant of 3.9 or more and which is higher than the relative permittivity of a thermally-oxidized film, is used. Therefore, even if the semiconductor device10is miniaturized, it is possible to reduce leakage current, as well as to increase the amount of current of the peripheral circuit gate insulation film108.

The gate electrode109is placed on an upper surface of the peripheral circuit gate insulation film108. In the gate electrode109, a step-reduction silicon film115and a second metal laminated film97-2are sequentially laminated.

The step-reduction silicon film115is disposed in such a way as to cover the upper surface of the peripheral circuit gate insulation film108. For example, the step-reduction silicon film115may be a polysilicon film.

An upper surface of the step-reduction silicon film115is flush with an upper surface of the first interlayer insulation film28disposed in the memory cell region E. The thickness of the step-reduction silicon film115is 20 nm, for example.

The second metal laminated film97-2has the same laminated structure as the first metal laminated film97-1that makes up the bit line33described above. That is, in the second metal laminated film97-2, a metal silicide film101, a titanium nitride film102, a tungsten silicide film103, and a tungsten film104are sequentially laminated.

In the gate electrode109, the step-reduction silicon film115, which is one layer of polysilicon film, and the second metal laminated film97-2are laminated.

Accordingly, compared with the gate electrode335shown inFIG. 16that includes two layers of polysilicon film (i.e., the step-reduction Poly-Si film334and the Poly-Si film308), the gate electrode109has a smaller resistance value.

Incidentally, as one example,FIG. 1shows the gate electrode109that extends in the X-direction in such a way as to traverse longitudinally through the center of the peripheral active regions18. However, the layout of the gate electrode109is not limited to this.

The pair of low-concentration impurity diffusion regions112is placed in the peripheral active region18on both sides of the peripheral circuit gate insulation film108in such away that the peripheral circuit gate insulation film108is sandwiched therebetween in the Y-direction. If the semiconductor substrate13is a p-type single crystal silicon substrate, the pair of low-concentration impurity diffusion regions112may be low-concentration n-type impurity diffusion regions, for example.

As the pair of low-concentration impurity diffusion regions112, for example, LDD (Lightly Doped Drain) regions may be used.

The pair of high-concentration impurity diffusion regions113is provided in both end portions of the peripheral active region18in such a way that the peripheral circuit gate insulation film108is sandwiched therebetween through the low-concentration impurity diffusion regions112.

The depth of the high-concentration impurity diffusion regions113relative to the main surface13aof the semiconductor substrate13is configured so as to be deeper than the depth of the low-concentration impurity diffusion regions112. The high-concentration impurity diffusion regions113are higher in impurity concentration than the low-concentration impurity diffusion regions112.

If the semiconductor substrate13is a p-type single crystal silicon substrate, the pair of high-concentration impurity diffusion regions113may be n-type impurity diffusion regions that are higher in n-type impurity concentration than the low-concentration impurity diffusion regions112, for example.

The second interlayer insulation film43is disposed so as to cover an upper surface of the first interlayer insulation film28and an upper surface of the element isolation region15-2. An upper surface of the second interlayer insulation film43is flat. The upper surface of the second interlayer insulation film43is flush with upper surfaces of cover insulation films34-1and34-2.

For example, the second interlayer insulation film43may be a silicon oxide film (SiO2film) formed by CVD (Chemical Vapor Deposition) method, or a coating-type insulation film (silicon oxide film (SiO2film)) formed by SOG (Spin On Glass) method.

The first contact hole45is placed in such a way as to pass through the first and second interlayer insulation films28and43that are located on the first capacitance impurity diffusion region85. The first contact hole45exposes the upper surface of the first capacitance impurity diffusion region85.

The first contact hole46is placed in such a way as to pass through the first and second interlayer insulation films28and43that are located on the second capacitance impurity diffusion region93. The first contact hole46exposes the upper surface of the second capacitance impurity diffusion region93.

The second contact hole48is placed in such a way as to pass through the second interlayer insulation film43located on the high-concentration impurity diffusion region113. The second contact hole48exposes the upper surface of the high-concentration impurity diffusion region113.

The capacitance contact plug51is placed in such a way as to fill the first contact hole45. Accordingly, a lower end of the capacitance contact plug51is in contact with the first capacitance impurity diffusion region85. An upper-end surface of the capacitance contact plug51is flat, and flush with the upper surface of the second interlayer insulation film43.

The capacitance contact plug52is placed in such a way as to fill the first contact hole46. Accordingly, a lower end of the capacitance contact plug52is in contact with the second capacitance impurity diffusion region93.

An upper-end surface of the capacitance contact plug52is flat, and flush with the upper surface of the second interlayer insulation film43.

The first contact plug53is placed in such a way as to fill the second contact hole48. Accordingly, a lower end of the first contact plug53is in contact with the high-concentration impurity diffusion region113.

An upper-end surface of the first contact plug53is flat, and flush with the upper surface of the second interlayer insulation film43.

The first wiring pattern55is provided on the second interlayer insulation film43disposed in the peripheral circuit region F. The first wiring pattern55includes a wiring section and a pad section55A, which is formed integrally with the wiring section and is greater in width than the wiring section. The pad section55A is connected to the upper end of the first contact plug53.

In this manner, the first wiring pattern55is electrically connected to the high-concentration impurity diffusion region113via the first contact plug53.

The stopper film57is placed on the upper surface of the second interlayer insulation film43disposed in the memory cell region E and peripheral circuit region F, in such a way as to cover the first wiring pattern55. The stopper film57is an insulation film that functions as a stopper film when anisotropic dry etching is performed of the third and fourth interlayer insulation films59and66.

The stopper film57may be an insulation film that is unlikely to be etched during the anisotropic dry etching under conditions for etching the third and fourth interlayer insulation films59and66.

More specifically, if a silicon oxide film (SiO2film) is used as the third and fourth interlayer insulation films59and66, the stopper film57may be a silicon nitride film (SiN film), for example.

The third interlayer insulation film59is disposed so as to cover an upper surface of the stopper film57. The thickness of the third interlayer insulation film59is set in such a way that the cylinder hole62formed in the stopper film57and third interlayer insulation film59has a desired depth.

For example, the third interlayer insulation film59may be a silicon oxide film (SiO2film) formed by CVD method, or a coating-type insulation film (silicon oxide film (SiO2film)) formed by SOG method.

The cylinder hole62is provided in such a way as to pass through the stopper film57and third interlayer insulation film59located on an associated one of the capacitance contact plugs51and52. The cylinder hole62is a cylindrical space, and exposes the upper-end surface of the associated one of the capacitance contact plug51and52.

The capacitor64is disposed so as to fill the cylinder holes62. The capacitor64includes a lower electrode117, a capacitance insulation film118, and an upper electrode119.

The lower electrode117is formed into the shape of a crown (crown shape), and is disposed so as to cover an inner wall of the cylinder holes62. The lower electrode117is connected to an upper end of the capacitance contact plug51and an upper end of the capacitance contact plug52.

Accordingly, the lower electrode117placed on the capacitance contact plug51is electrically connected to the first capacitance impurity diffusion region85via the capacitance contact plug51.

The lower electrode117placed on the capacitance contact plug52is electrically connected to the second capacitance impurity diffusion region93via the capacitance contact plug52.

The metal film that constitutes the lower electrode117may be a titanium nitride film (TiN film), for example.

The capacitance insulation film118is disposed so as to cover a surface of the lower electrode117and an upper surface of the third interlayer insulation film59. The thickness of the capacitance insulation film118is so set as not to completely fill an internal portion of each of the cylinder holes62.

For example, the capacitance insulation film118may be a hafnium oxide film (HfO2film), a zirconium oxide film (ZrO2film), an aluminum oxide film (Al2O3film), a strontium titanate film (SrTiO3film), a laminated film of those films, or the like.

The upper electrode119is provided so as to cover a surface of the capacitance insulation film118. The thickness of the upper electrode119is set in such a way that the upper electrode119fills the cylinder holes62through the lower electrode117and the capacitance insulation film118. An upper surface of the upper electrode119is flat.

The metal film that constitutes the upper electrode119may be a titanium nitride film (TiN film), for example.

Among the capacitors64with the above configuration, the capacitor64disposed on the capacitance contact plug51is electrically connected to the first transistor25via the capacitance contact plug51.

Among the capacitors64, the capacitor64disposed on the capacitance contact plug52is electrically connected to the second transistor26via the capacitance contact plug52.

Incidentally, as one example of the capacitors64, FIG.3shows cylinder-type capacitors that are configured so as to fill the cylinder holes62. However, the shape of the capacitors64is not limited to that. For example, as the capacitors64, crown-type capacitors may be used.

The first memory cell MC1includes the first transistor25; and the capacitor64that is placed above the capacitance contact plug51and electrically connected to the first transistor25.

The second memory cell MC2includes the second transistor26; and the capacitor64that is placed above the capacitance contact plug52and electrically connected to the second transistor26.

The fourth interlayer insulation film66is disposed so as to cover an upper surface of the upper electrode119and an upper surface of the third interlayer insulation film59that is placed in the peripheral circuit region F.

For example, the fourth interlayer insulation film66may be a silicon oxide film (SiO2film) formed by CVD method, or a coating-type insulation film (silicon oxide film (SiO2film)) formed by SOG method.

The third contact hole68is provided so as to pass through the stopper film57that is located on the pad section55A of the first wiring pattern55, the third interlayer insulation film59, and the fourth interlayer insulation film66. In this manner, the third contact hole68exposes the upper surface of the pad section55A of the first wiring pattern55.

The second contact plug71is provided so as to fill the third contact hole68. A lower end of the second contact plug71is connected to the pad section55A of the first wiring pattern55.

Therefore, the second contact plug71is electrically connected to the high-concentration impurity diffusion region113of the peripheral circuit transistor41via the first wiring pattern55.

The second wiring pattern73is placed on an upper surface of the fourth interlayer insulation film66that is located in the peripheral circuit region F. The second wiring pattern73is connected to an upper end of the second contact plug71.

Accordingly, the second wiring pattern73is electrically connected to the peripheral circuit transistor41via the second contact plug71.

The protective insulation film75is provided so as to cover the second wiring pattern73and an upper surface of the fourth interlayer insulation film66that is located in the memory cell region E and peripheral circuit region F. The protective insulation film75has a function of protecting the second wiring pattern73, which is placed on the top layer.

For example, the protective insulation film75may be an insulation film made of polyimide resin, for example.

The semiconductor device of the present embodiment includes: the semiconductor substrate13, which includes the memory cell region E and the peripheral circuit region F disposed around the memory cell region E; the element isolation regions15-1and15-2, which are respectively placed in the memory cell region E and the peripheral circuit region F; the cell active region17, which is disposed in the memory cell region E and defined by the element isolation regions15-1; the first interlayer insulation film28, which is disposed on the cell active region17; the bit contact hole28A, which passes through the first interlayer insulation film28and exposes the upper surface87aof the bit line impurity diffusion region87(or part of the upper surface17aof the cell active region17); and the bit line33, which is placed on the first interlayer insulation film28in such a way as to fill the bit contact hole28A and which is made of the first metal laminated film97-1. Therefore, the bit line33made of the first metal laminated film97-1(i.e., the bit line that does not contain, among its components or films, a silicon film that is higher in resistance than the metal films) can be connected directly to the bit line impurity diffusion region87.

Therefore, even if the memory cell section11is miniaturized (or if the diameter of the opening of the bit contact hole28A is made smaller), a rise in the resistance of the bit line33is curbed.

Moreover, as the bottom-layer metal film that constitutes the first metal laminated film97-1, a metal silicide film is used. Accordingly, a rise in the contact resistance between the bit line33and the bit line impurity diffusion region87can be curbed.

With reference to mainlyFIGS. 6 to 14, a method of manufacturing the semiconductor device of the present embodiment will be described. Incidentally, as for the method of manufacturing the semiconductor device10, the subsequent processes following those shown inFIG. 14will be described with reference toFIGS. 2 and 3.

First, in the process shown inFIGS. 6A,6B, and6C, a p-type single crystal silicon substrate is prepared as the semiconductor substrate13. Then, the well-known STI (Shallow Trench Isolation) method is used to form, at once, the element isolation regions15-1and15-2in the main surface13a's side of the semiconductor substrate13.

More specifically, for example, in the memory cell region E and the peripheral circuit region F, element isolation trenches (not shown) are formed by photolithographic technique and anisotropic dry etching technique. Then, element isolation insulation film is formed in such a way as to fill the element isolation trenches. In this manner, the element isolation regions15-1and15-2are formed at once.

In that manner, the following regions are formed at once (seeFIG. 1): a plurality of cell active regions17, which are defined by the element isolation regions15-1disposed in the memory cell region E and which extend in the X1-direction and are arranged at predetermined intervals in the X1- and Y-directions; and a plurality of peripheral active regions18, which are defined by the element isolation regions15-2disposed in the peripheral circuit region F and which extend in the Y-direction and are arranged at predetermined intervals in the X- and Y-directions.

The element isolation insulation films (not shown) may be a silicon oxide film (SiO2film), a silicon nitride film (SiN film), a laminated film of those films, or the like, for example.

The depth of the element isolation regions15-1and15-2relative to the main surface13aof the semiconductor substrate13is 250 nm, for example.

Then, the photolithographic technique and the anisotropic dry etching technique are used to form, in the cell active region17located in the memory cell region E, the first and second grooves21and22(two grooves), which extend in the Y-direction that crosses the direction (X1-direction) in which the cell active region17extends and which divides the upper portion of the cell active region17into three.

At this time, the first and second grooves21and22are formed in such a way as to go over a plurality of cell active regions17arranged in the Y-direction and the element isolation regions15-1.

The depth of the first and second grooves21and22relative to the main surface13aof the semiconductor substrate13is 150 nm, for example.

Then, a well-known technique is used to form the gate insulation film81that covers the inner surfaces of the first and second grooves21and22.

More specifically, for example, a thermal oxidation method is used to oxidize the cell active region17exposed at the inner surfaces of the first and second grooves21and22(i.e., the semiconductor substrate13made of the single crystal silicon substrate). As a result, a silicon oxide film (SiO2film) is formed in such a way as to cover the inner surfaces of the first and second grooves21and22. In this manner, the gate insulation film81made of the silicon oxide film (SiO2film) is formed.

Incidentally, any method other than the thermal oxidation method may be used to form the gate insulation film81that covers the inner surfaces of the first and second grooves21and22.

In this case, for example, the gate insulation film81may be a single-layer silicon oxide film (SiO2film), a silicon oxynitride film (SiON film), a laminated silicon oxide film (SiO2film), a laminated film made by laminating a silicon nitride film (SiN film) on a silicon oxide film (SiO2film), or the like.

Then, a well-known technique is used to form the following electrodes at once: the embedded gate electrode83, which is placed in such a way as to fill the lower portion of the first groove21through the gate insulation film81and which extends in the Y-direction; and the embedded gate electrode91, which is placed in such a way as to fill the lower portion of the second groove22through the gate insulation film81and which extends in the Y-direction.

More specifically, for example, the method described below is used to form the embedded gate electrodes83and91. First, a titanium nitride film (TiN film) and a tungsten film (W film), which are base materials of the embedded gate electrodes83and91, are sequentially formed in such a way as to fill the first and second grooves21and22.

After that, etching-back is performed by anisotropic dry etching in such a way that the titanium nitride film (TiN film) and the tungsten film (W film) remain only in the lower portions of the first and second grooves21and22. In this manner, the embedded gate electrodes83and91are formed.

Then, a well-known technique is used to form the embedded insulation films27, which fill the upper portions of the first and second grooves21and22, respectively, and whose upper surface is flush with the main surface13aof the semiconductor substrate13.

As a result, the upper surfaces of the embedded gate electrodes83and91are covered with the embedded insulation films27, respectively. For example, each of the embedded insulation films27may be a silicon oxide film (SiO2film), a silicon nitride film (SiN film), a laminated film of those films, or the like.

Then, the photolithographic technique and the ion implantation technique are used to perform ion implantation of n-type impurities into the upper surface17aof the cell active region17. As a result, the following regions are formed at once: the first capacitance impurity diffusion region85, which is disposed in one end portion17A (seeFIG. 1) of the cell active region17; the second capacitance impurity diffusion region93, which is disposed in the other end portion17B (seeFIG. 1) of the cell active region17; and the bit line impurity diffusion region87, which is disposed in the cell active region17between the first groove21and the second groove22.

At this time, the first capacitance impurity diffusion region85, the second capacitance impurity diffusion region93, and the bit line impurity diffusion region87are formed in such a way that the upper surfaces of the regions85,93, and87are flush with the upper surface17aof the cell active region17(or the main surface13aof the semiconductor substrate13).

In that manner, the first transistor25and the second transistor26are formed: the first transistor25includes the gate insulated film81formed on the inner surface of the first groove21, the embedded gate electrode83, the first capacitance impurity diffusion region85, and the bit line impurity diffusion region87; and the second transistor26includes the gate insulated film81formed on the inner surface of the second groove22, the embedded gate electrode91, the second capacitance impurity diffusion region93, and the bit line impurity diffusion region87.

Then, a well-known technique is used to sequentially form an insulation film125, which covers the upper surface of the peripheral active region F and the upper surface of the element isolation region15-2, and a polysilicon film127, which covers an upper surface of the insulation film125.

The insulation film125is a film that is base material of the peripheral circuit gate insulation film108, which is one of components of the peripheral circuit transistor41. The insulation film125may be a high dielectric constant film (High-K film), for example.

More specifically, for example, the method described below is used to form the insulation film125disposed in the peripheral circuit region F, and the polysilicon film127.

First, the insulation film125(e.g. high dielectric constant film) is formed in such a way as to cover the upper surfaces of the element isolation regions15-1and15-2, the upper surface17aof the cell active region17, the upper surface18aof the peripheral circuit region18, and the upper surface of the embedded insulation film27. Then, the polysilicon film127is formed to cover the upper surface of the insulation film125.

Then, the photolithographic technique is used to form a resist mask (not shown) that covers the upper surface of the polysilicon film127formed in the peripheral circuit region F. As a result, the upper surface of the polysilicon film127formed in the memory cell region E is exposed from the resist mask (not shown).

Then, the resist mask (not shown) is used as an etching mask, and anisotropic dry etching is performed to remove the insulation film125and polysilicon film127formed in the memory cell region E. As a result, the upper surface17aof the cell active region17and the upper surface of the element isolation region15-1are exposed.

Accordingly, only in the peripheral circuit region F, the laminated insulation film125and polysilicon film127remain.

As the high dielectric constant film that becomes the insulation film125, for example, an insulation film that has a dielectric constant of 3.9 or more and which is higher than the relative permittivity of a thermally-oxidized film may be formed. For example, the high dielectric constant film may be an insulation film containing hafnium oxide, tantalum oxide, lanthanum oxide, or the like.

In the process shown inFIGS. 11A to 11Ddescribed later, patterning of the insulation film125is performed, and the peripheral circuit gate insulation film108is formed as a result.

That is, the insulation film125is an insulation film that is base material of the peripheral circuit gate insulation film108. The thickness of the insulation film125may be 3 nm, for example.

In the process shown inFIGS. 11A to 11Ddescribed later, patterning of the polysilicon film127is performed. As a result, the polysilicon film127becomes part of the gate electrode109of the peripheral circuit transistor41. That is, the polysilicon film127is a conductive film that is base material of the gate electrode109. The thickness of the polysilicon film127may be 15 nm, for example.

Then, a well-known technique is used to form the first interlayer insulation film28that covers the element isolation regions15-1, the upper surface of the embedded insulation film27, the upper surface of the first capacitance impurity diffusion region85, the upper surface87aof the bit line impurity diffusion region87, the upper surface of the second capacitance impurity diffusion region93, and the upper surface of the polysilicon film127formed in the peripheral circuit region F.

As a result, in the peripheral circuit region F, the first interlayer insulation film28that is equal in thickness to the first interlayer insulation film28formed in the memory cell region E is formed. The thickness of the first interlayer insulation film28may be 20 nm, for example.

More specifically, for example, as the first interlayer insulation film28, a coating-type insulation film (silicon oxide film (SiO2film)) is formed by SOG method.

Incidentally, instead of the coating-type insulation film, for example, a silicon oxide film (SiO2film) may be formed by CVD method as the first interlayer insulation film28.

Then, in the process shown inFIGS. 7A,7B,7C, and7D, the photolithographic technique is used to form an etching mask131having openings131A, on the upper surface of the first interlayer insulation film28disposed in the memory cell region E. Therefore, the upper surface of the polysilicon film127formed in the peripheral circuit region F is exposed from the etching mask131.

The openings131A are formed so as to expose a surface located above the bit line impurity diffusion region87which is part of the upper surface of the first interlayer insulation film28.

Then, anisotropic dry etching is performed by using the etching mask131, thereby removing the first interlayer insulation film28located below the openings131A. As a result, the bit contact hole28A is formed so as to pass through the first interlayer insulation film28and expose the upper surface87aof the bit line impurity diffusion region87. The diameter of the bit contact hole28A may be 30 nm, for example.

The thickness of the first interlayer insulation film28that is exposed from the etching mask131and formed in the peripheral circuit region F is equal to the thickness of the first interlayer insulation film28disposed below the openings131A.

Therefore, when the first interlayer insulation film28located below the openings131A is removed, the first interlayer insulation film28(seeFIG. 6A) formed in the peripheral circuit region F is also removed, and the upper surface of the polysilicon film127disposed in the peripheral circuit region F is exposed.

That is, the etching mask131is formed in such a way that the first interlayer insulation film28(seeFIG. 6A) formed in the peripheral circuit region F is to be exposed, and etching of the first interlayer insulation film28is performed through the etching mask131. Therefore, there is no need to separately perform a step of removing the first interlayer insulation film28formed in the peripheral circuit region F. In this manner, the process of manufacturing the semiconductor device10is simplified.

When the bit contact holes28A are formed by anisotropic dry etching, an end point system may be employed so as to able to detect when the polysilicon film127formed in the peripheral circuit region F becomes exposed. Moreover, over-etching of the first interlayer insulation film28may be performed in accordance with the influence of micro-loading effects of the bit contact holes28A with a small opening diameter.

Incidentally, the “micro-loading effects” mean a phenomenon of a decreased etching rate in a region whose aspect ratio is large compared with a region whose aspect ratio (or ratio of depth and width) of mask-pattern openings is small.

In planar view, the area of the polysilicon film127disposed above the peripheral circuit region F is quite large. Therefore, when the bit contact holes28A are to be formed by anisotropic dry etching, the time when the polysilicon film127becomes exposed is detected as an end point of etching following the disappearance of the first interlayer insulation film28disposed in the peripheral circuit region F. Thus, the accuracy of the etching of the bit contact holes28A can be improved.

Furthermore, the time when the polysilicon film127becomes exposed is recognized as an end point of etching, and a predetermined amount of over-etching is set from that end point. Therefore, it is possible to ensure that a portion of the upper surface of the cell active region17is exposed from the bottom of the bit contact hole28A formed on within the surface of the semiconductor substrate13. Thus, the accuracy of processing of the bit contact holes28A can be improved.

As a result, a contact failure is less likely to occur between the bit line33, which fills the bit contact hole28A, and the bit line impurity diffusion region87. Therefore, the yield of the semiconductor devices10can be improved.

Furthermore, if the bit contact holes28A are formed by anisotropic dry etching, the conditions that make it easy to etch the first interlayer insulation film28and make it difficult to etch the semiconductor substrate13(i.e., the bit line impurity diffusion region87) may be used.

Under such etching conditions, the bit contact holes28A are formed by anisotropic dry etching. Accordingly, within the plane of the semiconductor substrate13, it is possible to keep the bit line impurity diffusion region87from being etched.

Then, in the process shown inFIGS. 8A,8B,8C, and8D, a well-known technique is used to remove the etching mask131shown inFIGS. 7A,7B, and7D. As a result, the upper surface of the first interlayer insulation film28remaining in the memory cell region E is exposed.

Then, a well-known technique is used to form the metal silicide film101on the upper surface87aof the bit line impurity diffusion region87, which is exposed through the bit contact hole28A, and the upper surface of the polysilicon film127. The metal silicide film101may be a titanium silicide film (TiSi film), for example.

A method of forming the metal silicide film101will be described below with the use of an example in which the titanium silicide film is formed as the metal silicide film101.

First, a well-known technique is used to form a titanium film134that covers the inner surface of the bit contact hole28A, the upper surface of the first interlayer insulation film28, and the upper surface of the polysilicon film127. The thickness of the titanium film134may be 2 nm, for example.

Then, heat treatment is performed in such a way that the upper surface87aof the bit line impurity diffusion region87(or the main surface13aof the semiconductor substrate13) and the polysilicon film127react with the titanium film134. As a result, the titanium silicide film (TiSi film) is formed as the metal silicide film101.

In that manner, the metal silicide film101, which is the titanium silicide film, is formed on the upper surface87aof the bit line impurity diffusion region87, which is exposed through the bit contact hole28A, and the upper surface of the polysilicon film127.

The titanium silicide film101that is formed on the upper surface87aof the bit line impurity diffusion region87, which is exposed through the bit contact hole28A, is one of the components of the bit line33shown inFIG. 11A. A portion of the titanium silicide film101that is formed on the upper surface of the polysilicon film127is part of the gate electrode109shown inFIG. 11C.

Incidentally, the titanium film134that is disposed so as to be in contact with the first interlayer insulation film28does not react with silicon during the heat treatment. Therefore, the titanium film134does not become a titanium silicide film, and remains unchanged.

Then, in the process shown inFIGS. 9A,9B,9C, and9D, a well-known technique is used to remove the titanium film134(seeFIG. 8A) remaining on the first interlayer insulation film28. As a result, the upper surface of the first interlayer insulation film28disposed in the memory cell region E is exposed.

At this stage, the thickness of the insulation film125, the thickness of the polysilicon film127, the thickness of the first interlayer insulation film28, and the thickness of the metal silicide film101may be adjusted in advance in such a way that the upper surface of the metal silicide film101formed on the polysilicon film127will be flush with the upper surface of the first interlayer insulation film28formed in the memory cell region E containing the cell active region17.

Accordingly, the upper surface of the metal silicide film101formed on the polysilicon film127is flush with the upper surface of the first interlayer insulation film28formed in the memory cell region E containing the cell active region17. Therefore, it is possible to avoid generating a difference in height between the bit line33formed in the memory cell region E and the gate electrode109formed in the peripheral circuit region F.

Then, in the process shown inFIGS. 10A,10B,10C, and10D, a well-known technique is used to form the titanium nitride film102that covers the inner surface of the bit contact hole28A in which the metal silicide film101is formed, the upper surface of the first interlayer insulation film.28, and the upper surface of the polysilicon film127.

At this time, the thickness of the titanium nitride film102is set in such a way as not to fully fill the bit contact hole28A in which the metal silicide film101is formed. For example, the thickness of the titanium nitride film102may be 5 nm.

Then, a well-known technique is used to form, on the surface of the titanium nitride film102, the tungsten silicide film103that is thick enough to fill the bit contact hole28A through the titanium nitride film102. At this time, the tungsten silicide film103is formed in such a way that the upper surface thereof is flat. For example, the thickness of the tungsten silicide film103is 10 nm.

Then, a well-known technique is used to form, on the surface of the tungsten silicide film103, the tungsten film104(10 nm in thickness, for example).

As a result, in the memory cell region E and the peripheral circuit region F, the metal laminated film97is formed: In the metal laminated film97, the metal silicide film101, the titanium nitride film102, the tungsten silicide film103, and the tungsten film104are sequentially laminated.

Incidentally, a portion of the metal laminated film97shown inFIG. 10Athat is formed on the bit line impurity diffusion region87works as the first metal laminated film97-1, which makes up the bit line33shown inFIG. 3. A portion of the metal laminated film97that is formed at the center of the peripheral active region18works as the second metal laminated film97-2shown inFIG. 5.

Then, a well-known technique is used to form a silicon nitride film136that covers the upper surface of the metal laminated film97(or the upper surface of the tungsten film104). In the process shown inFIG. 11described later, patterning of the silicon nitride film136is performed to produce the cover insulation films34-1and34-2.

That is, the silicon nitride film136is an insulation film that is base material of the cover insulation films34-1and34-2. For example, the thickness of the silicon nitride film136may be 30 nm.

Then, in the process shown inFIGS. 11A,11B,11C, and11D, the photolithographic technique and the anisotropic dry etching technique are used to perform patterning of the silicon nitride film136. As a result, the cover insulation films34-1and34-2are formed at once: the cover insulation film34-1is disposed in the memory cell region E and made of the silicon nitride film136, and the cover insulation film34-2is disposed in the peripheral circuit region F and made of the silicon nitride film136.

At this time, the cover insulation film34-1is formed in such a way as to cover the upper surface of the tungsten film104corresponding to a formation region of the bit line33. The cover insulation film34-2is formed in such a way as to cover the upper surface of the tungsten film104corresponding to a formation region of the gate electrode109.

Then, the cover insulation films34-1and34-2are used as an etching mask, and anisotropic dry etching is performed. Accordingly, unnecessary portions of the metal laminated film shown inFIG. 10A(i.e., the first and second metal laminated films97-1and97-2) and insulation film125are removed. As a result, the bit line33, the peripheral circuit gate insulation film108, and the gate electrode109are formed at once: the bit line33is disposed immediately below the cover insulation film34-1and made of the first metal laminated film97-1(metal laminated film97); the peripheral circuit gate insulation film108is disposed at the center of the peripheral active region18and made of the insulation film125; and the gate electrode109is disposed immediately below the cover insulation film34-2and made up of the step-reduction silicon film115(whose base material is the polysilicon film127) and the second metal laminated film97-2(metal laminated film97).

Accordingly, the bit line33is formed so as to extend in the X-direction shown inFIG. 1and fill the bit contact hole28A, with a lower end thereof connected to the upper surface87aof the bit line impurity diffusion region87.

Moreover, the gate electrode109is formed on the peripheral circuit gate insulation film108in such a way as to extend in the X-direction shown inFIG. 1.

In that manner, the bit line33, which is made of the first metal laminated film97-1, is formed so as to fill the bit contact hole28A that exposes the upper surface87aof the bit line impurity diffusion region87. Therefore, without the use of a bit line contact plug made of silicon film, the bit line33, which is made of the first metal laminated film97-1(i.e., the bit line that does not contain, among its components, a silicon film that is higher in resistance than metal), can be connected directly to the upper surface87aof the bit line impurity diffusion region87.

Therefore, even if the memory cell section11is miniaturized (or if the diameter of the opening of the bit contact hole28A is made smaller), a rise in the resistance of the bit line33is curbed.

Moreover, as a metal film that constitutes the bottom layer of the first metal laminated film97-1, the metal silicide film101(or, more specifically, a titanium silicide film, for example) is used. Therefore, even if the memory cell section11is miniaturized, a rise in the contact resistance between the bit line33and the bit line impurity diffusion region87(or a region where ion implantation of n-type impurities has been performed into the single crystal silicon substrate) can be curbed.

Moreover, on the upper surface18aof the peripheral active region18and the upper surface of the element isolation region15-2, the insulation film125and the polysilicon film127are sequentially laminated. Then, in the first interlayer insulation film28that covers the upper surface of the cell active region17and the upper surface of the element isolation region15-1, the bit contact hole28A is formed so as to expose the upper surface87aof the bit line impurity diffusion region87. Then, the metal laminated film97that covers the upper surface of the first interlayer insulation film28and the upper surface of the polysilicon film127is formed in such a way as to fill the bit contact hole28A. Then, patterning of the metal laminated film97and polysilicon film127is performed to form the bit line33and the gate electrode109at once: the bit line33is made of the metal laminated film97, and the gate electrode109is made up of the metal laminated film97and the step-reduction silicon film115whose base material is the polysilicon film127. Therefore, the thickness of a portion of the bit line33that is disposed above the first interlayer insulation film28can be reduced by an amount equivalent to the thickness of the step-reduction silicon film115.

Therefore, the parasitic capacitance of the bit line33can be reduced. Thus, it is possible to increase the accuracy of the operation of the semiconductor device10(or, more specifically, the accuracy of the operation of DRAM, for example).

Then, in the process shown inFIGS. 12A,12B,12C, and12D, ion implantation of low-concentration n-type impurities into the peripheral active region18shown inFIG. 11Ais performed by an ion implantation method using the cover insulation films34-1and34-2and the first interlayer insulation film28as a mask. As a result, the pair of low-concentration impurity diffusion regions112is formed.

More specifically, as the pair of low-concentration impurity diffusion regions112, for example, LDD regions are formed.

Incidentally, although not shown in the diagrams, at this stage, even in the peripheral active region18corresponding to the formation regions of the high-concentration impurity diffusion regions113shown inFIG. 12A, the low-concentration impurity diffusion regions112are formed.

Then, a well-known technique is used to form, at once, the sidewalls36-1and the sidewalls36-2: the sidewalls36-1are placed on the first interlayer insulation film28and covers the side surfaces of the bit line33disposed above the upper surface of the first interlayer insulation film28and the cover insulation film34-1, respectively; and the sidewalls36-2are placed on the low-concentration impurity diffusion regions112and covers the side surfaces of the gate electrode109and the cover insulation film34-2, respectively.

More specifically, for example, after the pair of low-concentration impurity diffusion regions112is formed, a silicon nitride film (SiN film) is formed so as to cover the whole upper surface of the structure shown inFIG. 11A. After that, an anisotropic dry etching method is used to perform etching-back of the silicon nitride film to form the sidewalls36-1and36-2.

Then, ion implantation of high-concentration n-type impurities is performed by using the cover insulation films34-1and34-2, the first interlayer insulation film28, and the sidewalls36-2as a mask. As a result, the pair of high-concentration impurity diffusion regions113is formed in portions of the peripheral active region18between the sidewalls36-2and the element isolation regions15-2in the Y-direction shown inFIG. 1(i.e., the low-concentration impurity diffusion regions112(not shown) that are formed in portions corresponding to formation regions of the high-concentration impurity diffusion regions113).

At this time, the high-concentration impurity diffusion regions113are formed in such a way as to be deeper than the depth of the low-concentration impurity diffusion regions112relative to the main surface13aof the semiconductor substrate13.

The pair of high-concentration impurity diffusion regions113is disposed in both end portions of the peripheral active region18in such a way that the peripheral circuit gate insulation film108is sandwiched therebetween in the Y-direction across the pair of low-concentration impurity diffusion region112.

In that manner, in one peripheral active region18, one peripheral circuit transistor41(planar transistor) is formed.

The peripheral circuit transistor41includes the peripheral circuit gate insulation film108, the gate electrode109, the pair of low-concentration impurity diffusion regions112, and the pair of high-concentration impurity diffusion regions113.

Then, a well-known technique is used to form the second interlayer insulation film43: The second interlayer insulation film43fills the spaces formed between the sidewalls36-1, between the sidewalls36-1and36-2, and between the sidewalls36-2, and the upper surface thereof is flush with the upper surfaces of the sidewalls36-1and36-2.

More specifically, for example, the method described below is used to form the second interlayer insulation film43.

First, the CVD method is used to form a silicon oxide film (SiO2film) that covers the memory cell region E and the peripheral circuit region F. Then, the CMP method is used to polish and thereby remove an unnecessary portion of silicon oxide film (SiO2film) formed above the upper surfaces of the cover insulation films34-1and34-2and the upper surfaces of the sidewalls36-1and36-2. As a result, the second interlayer insulation film43, which is made of the silicon oxide film (SiO2film), is formed.

At the above polishing step, the cover insulation films34-1and34-2, which are made of the silicon nitride film (SiN film), and the sidewalls36-1and36-2are used as a stopper film for the polishing. Accordingly, the thickness of the second interlayer insulation film43can be accurately controlled.

Incidentally, instead of the silicon oxide film (SiO2film) formed by the CVD method, a coating-type insulation film (silicon oxide film (SiO2film)) formed by the SOG method may be used.

Then, the photolithographic technique and the anisotropic dry etching technique are used to form, at once, the following contact holes: the first contact hole45, which passes through the first and second interlayer insulation films28and43located on the first capacitance impurity diffusion region85; the first contact hole46, which passes through the first and second interlayer insulation films28and43located on the second capacitance impurity diffusion region93; and the second contact holes48, which pass through the second interlayer insulation film43located on the high-concentration impurity diffusion regions113, respectively.

In that manner, the first contact hole45is formed in such a way as to expose the upper surface of the first capacitance impurity diffusion region85. The first contact hole46is formed in such a way as to expose the upper surface of the second capacitance impurity diffusion region93.

Each of the second contact hole48is formed in such a way as to expose the upper surface of the corresponding high-concentration impurity diffusion region113.

Then, a well-known technique is used to form the following contact plugs at once: the capacitance contact plug51, which is placed in the first contact hole45and the lower end of which is in contact with the upper surface of the first capacitance impurity diffusion region85; the capacitance contact plug52, which is placed in the first contact hole46and the lower end of which is in contact with the upper surface of the second capacitance impurity diffusion region93; and the first contact plugs53, which are placed in the second contact holes48and the lower ends of which are in contact with the upper surfaces of the high-concentration impurity diffusion regions113, respectively.

At this time, the capacitance contact plugs51and52and the first contact plugs53are formed in such a way that the upper surfaces of the capacitance contact plugs51and52and the upper surfaces of the first contact plugs53are flush with the upper surface of the second interlayer insulation film43.

Then, in the process shown inFIGS. 13A and 13B, a well-known technique is used to form, on the second interlayer insulation film43disposed in the peripheral circuit region F, the first wiring pattern55that includes the wiring section (not shown) and the pad section55A connected to the upper end of the first contact plug53.

Then, a well-known technique (e.g. CVD method) is used to form the stopper film57, which covers the upper surface of the first interlayer insulation film43, the upper surfaces of the cover insulation films34-1and34-2, the upper surface of the sidewalls36-1, and the first wiring pattern55.

The stopper film57is an insulation film that functions as a stopper film when anisotropic dry etching of the third and fourth interlayer insulation films59and66(seeFIG. 2) is performed.

Therefore, the stopper film57may be an insulation film that is less likely to be etched during the anisotropic dry etching under conditions for etching the third and fourth interlayer insulation films59and66.

More specifically, if a silicon oxide film (SiO2film) is used as the third and fourth interlayer insulation films59and66, what is formed as the stopper film57may be a silicon nitride film (SiN film), for example.

Then, a well-known technique is used to form the third interlayer insulation film59that covers the upper surface of the stopper film57. More specifically, for example, the CVD method is used to form a silicon oxide film (SiO2film). In this manner, the third interlayer insulation film59, which is made of the silicon oxide film (SiO2film), is formed.

Incidentally, instead of the silicon oxide film (SiO2film) formed by the CVD method, a coating-type insulation film (silicon oxide film (SiO2film)) formed by the SOG method may be used to form the third interlayer insulation film59.

Then, in the process shown inFIGS. 14A and 14B, the photolithographic technique and the anisotropic dry etching are used to form the cylinder holes62, which pass through the stopper film57and third interlayer insulation film59disposed on the capacitance contact plugs51and52, respectively.

At this time, the cylinder holes62are formed in such a way as to expose the upper-end surface of the capacitance contact plug51and the upper-end surface of the capacitance contact plug52, respectively.

More specifically, for example, the method described below is used to form the cylinder hall62.

First, the photolithographic technique is used to form an etching mask (not shown) on the third interlayer insulation film59. Then, by using the conditions under which the silicon oxide film (SiO2film) is likely to be etched and the silicon nitride film (SiN film) is unlikely to be etched (i.e., the conditions under which the silicon oxide film (SiO2film) is selectively etched), etching of the third interlayer insulation film59by anisotropic dry etching is performed.

At this time, the stopper film57made of silicon nitride film (SiN film) functions as a stopper film during the anisotropic dry etching. Therefore, an over-etching time can be made longer. Therefore, it is possible to ensure that, on the semiconductor substrate13, the upper surface of the stopper film57is exposed.

Then, by using the conditions under which the silicon nitride film (SiN film) is likely to be etched and the silicon oxide film (SiO2film) is unlikely to be etched (i.e., the conditions under which the silicon nitride film (SiN film) is selectively etched), etching of the thin stopper film57by anisotropic dry etching is performed, thereby forming a plurality of cylinder holes62.

Then, a well-known technique is used to form the lower electrode117that covers the inner surface of the cylinder hole62and which is formed into the shape of a crown (crown shape). Therefore, the lower electrode117formed in the cylinder hole62that exposes the upper-end surface of the capacitance contact plug51is connected to the capacitance contact plug51, and is electrically connected to the first capacitance impurity diffusion region85via the capacitance contact plug51.

The lower electrode117formed in the cylinder hole62that exposes the upper-end surface of the capacitance contact plug52is connected to the capacitance contact plug52, and is electrically connected to the second capacitance impurity diffusion region93via the capacitance contact plug52.

The lower electrode117is formed in such a way as to have a thickness that does not fully fill the cylinder holes62. The metal film that serves as base material of the lower electrode117may be a titanium nitride film (TiN film), for example. The titanium nitride film (TiN film) can be formed by such methods as CVD method or ALD (Atomic Layer Deposition) method, for example.

Then, a well-known technique is used to form the capacitance insulation film118that covers the upper surface of the lower electrode117and the upper surface of the third interlayer insulation film59. At this time, the capacitance insulation film118is formed in such a way as to have a thickness that does not fully fill the cylinder holes62through the lower electrode117.

For example, the capacitance insulation film118may be a hafnium oxide film (HfO2film), a zirconium oxide film (ZrO2film), an aluminum oxide film (Al2O3film), a strontium titanate film (SrTiO3film), a laminated film of those films, or the like.

Then, a well-known technique is used to form the upper electrode119that covers the surface of the capacitance insulation film118and which fills the cylinder holes62through the capacitance insulation film118and the lower electrode117. At this time, the upper electrode119is formed in such a way that the upper surface thereof is flat.

The metal film that constitutes the upper electrode119may be a titanium nitride film (TiN film), for example. The titanium nitride film (TiN film) can be formed by CVD method or ALD method, for example.

In that manner, in each cylinder hole62, the capacitor64, which includes the lower electrode117, the capacitance insulation film118, and the upper electrode119, is formed. Moreover, the first memory cell MC1and the second memory cell MC2are formed (seeFIG. 3): the first memory cell MC1includes the first transistor25and the capacitor64formed above the capacitance contact plug51, and the second memory cell MC2includes the second transistor26and the capacitor64formed above the capacitance contact plug52.

Among the capacitors64, the capacitor64formed above the capacitance contact plug51is electrically connected to the first transistor25via the capacitance contact plug51(seeFIG. 3).

Among the capacitors64, the capacitor64formed above the capacitance contact plug52is electrically connected to the second transistor26via the capacitance contact plug52(seeFIG. 3).

In the subsequent process, as shown inFIGS. 2 and 3, a well-known technique is used to form, on the upper surface of the third interlayer insulation film59, the fourth interlayer insulation film66that covers the upper electrode119and the upper surface of which is flat.

More specifically, for example, the method described below may be used to form the fourth interlayer insulation film66. First, the CVD method is used to form a silicon oxide film (SiO2film) that serves as base material of the fourth interlayer insulation film66. Then, the CMP method is used to polish and thereby remove an upper portion of the silicon oxide film (SiO2film). In this manner, what is formed is the fourth interlayer insulation film66that is made of the silicon oxide film (SiO2film) and the upper surface of which is flat.

Incidentally, instead of the silicon oxide film (SiO2film) formed by CVD method, a coating-type insulation film (silicon oxide film (SiO2film)) may be formed by SOG method as base material of the fourth interlayer insulation film66.

Then, the photolithographic technique and the anisotropic dry etching technique are used to remove the third and fourth interlayer insulation films59and66located above the pad section55A. As a result, the third contact hole68is formed so as to expose the upper surface of the pad section55A.

Then, a well-known technique (which is similar to the method of forming the capacitance contact plugs51and52and the first contact plug53, for example) is used to form the second contact plug71that fills the third contact hole68and the lower end of which is connected to the pad section55A of the first wiring pattern55.

At this time, the second contact plug71is formed in such a way that the upper surface thereof is flush with the upper surface of the fourth interlayer insulation film66.

The second contact plug71is electrically connected to the high-concentration impurity diffusion regions113of the peripheral circuit transistor41via the first wiring pattern55.

Then, a well-known technique is used to form, on the upper surface of the fourth interlayer insulation film66located in the peripheral circuit region F, the second wiring pattern73that is connected to the upper end of the second contact plug71.

Accordingly, the second wiring pattern73is electrically connected to the peripheral circuit transistor41via the second contact plug71.

Then, a well-known technique is used to form, on the upper surface of the fourth interlayer insulation film66, the protective insulation film75that covers the second wiring pattern73. The protective insulation film75may be an insulation film made of polyimide resin, for example.

In that manner, the semiconductor device10is produced in such a way as to have the memory cell section11, which is disposed in the memory cell region E, and the peripheral circuit section12, which is disposed in the peripheral circuit region F.

According to the manufacturing method of the semiconductor device of the present embodiment, the bit line33, which is made of the metal laminated film97, is formed in such away as to fill the bit contact hole28A, which exposes the upper surface87aof the bit line impurity diffusion region87. Therefore, without the use of a bit line contact plug made of silicon film, the bit line33, which is made of the metal laminated film97(i.e., the bit line that does not contain, among its components, a silicon film that is higher in resistance than metal), can be connected directly to the upper surface87aof the bit line impurity diffusion region87.

Therefore, even if the memory cell section11is miniaturized (or if the diameter of the opening of the bit contact hole28A is made smaller), a rise in the resistance of the bit line33is curbed.

Moreover, as a metal film that constitutes the bottom layer of the metal laminated film97, the metal silicide film101(or, more specifically, a titanium silicide film, for example) is formed. Therefore, even if the memory cell section11is miniaturized, a rise in the contact resistance between the bit line33and the bit line impurity diffusion region87(or a region where ion implantation of n-type impurities has been performed into the single crystal silicon substrate) can be curbed.

Moreover, on the upper surface18aof the peripheral active region18and the upper surface of the element isolation region15-2, the insulation film125and the polysilicon film127are sequentially laminated. Then, in the first interlayer insulation film28that covers the upper surface of the cell active region17and the upper surface of the element isolation region15-1, the bit contact hole28A is formed so as to expose the upper surface87aof the bit line impurity diffusion region87. Then, the metal laminated film97, which covers the upper surface of the first interlayer insulation film28and the upper layer of the polysilicon film127, is formed so as to fill the bit contact hole28A. After that, patterning of the metal laminated film97and the polysilicon film127is performed. As a result, the bit line33, which is made of the metal laminated film97, and the gate electrode109, which is made up of the metal laminated film97and the step-reduction silicon film.115whose base material is the polysilicon film127, are formed at once. Therefore, the thickness of a portion of the bit line33that is disposed on the first interlayer insulation film28can be reduced by an amount equivalent to the thickness of the step-reduction silicon film115.

Therefore, the parasitic capacitance of the bit line33can be reduced. Thus, it is possible to increase the accuracy of the operation of the semiconductor device10(or, more specifically, the accuracy of the operation of DRAM, for example).

The preferred embodiment of the present invention has been described in detail. However, the present invention is not limited to that specific embodiment. Within the scope of the present invention described in the appended claims, various modifications and changes may be made.

In addition, while not specifically claimed in the claim section, the applicant reserves the right to include in the claim section of the application at any appropriate time the following methods:

A1. A method of manufacturing a semiconductor device, comprising:

forming an insulation film that serves as base material of a peripheral circuit gate insulation film that constitutes a peripheral circuit transistor in a peripheral circuit region of a main surface of a semiconductor substrate having a cell active region and the peripheral circuit region;

forming a silicon film that serves as base material of a step-reduction silicon film on the insulation film;

forming a first interlayer insulation film that covers the cell active region and an upper surface of the silicon film;

performing anisotropic dry etching to form a bit contact hole that passes through the first interlayer insulation film and exposes a portion of the upper surface of the cell active region while removing the first interlayer insulation film disposed above the silicon film;

forming a metal laminated film that covers the upper surface of the first interlayer insulation film and the upper surface of the silicon film in such a way as to fill the bit contact hole;

forming, at once, a first cover insulation film that is disposed on the metal laminated film located in the cell active region and functions as an etching mask, and a second cover insulation film that is disposed on the metal laminated film located in the peripheral circuit region and functions as an etching mask; and

performing patterning of the metal laminated film and silicon film disposed in the cell active region and peripheral circuit region by anisotropic dry etching through the first and second cover insulation films, thereby forming, at once, a bit line that is made of the metal laminated film disposed below the first cover insulation film and fills the bit contact hole, and a gate electrode of the peripheral circuit transistor that is made of the metal laminated film disposed below the second cover insulation film and the step-reduction silicon film.

A2. The method of manufacturing the semiconductor device as described in A1, wherein

the forming the metal laminated film includes forming a metal silicide film on an upper surface of the cell active region exposed through the bit contact hole and on an upper surface of the silicon film formed in the peripheral circuit region.

A3. The method of manufacturing the semiconductor device as described in A2, wherein

the thickness of the insulation film, the thickness of the silicon film, the thickness of the first interlayer insulation film, and the thickness of the metal silicide film are adjusted in such a way that an upper surface of the metal silicide film formed on the silicon film is flush with an upper surface of the first interlayer insulation film formed in the cell active region.

A4. The method of manufacturing the semiconductor device as described in any one of A1 to A3, wherein

the peripheral circuit gate insulation film is formed by patterning of the insulation film during the anisotropic dry etching that is performed to form the gate electrode.

A5. The method of manufacturing the semiconductor device as described in anyone of A1 to A4, further comprising:

forming a groove that extends in a direction crossing a direction in which the cell active region extends and divides an upper portion of the cell active region before the metal silicide film is formed; and

forming a transistor including a gate insulation film, which covers an inner surface of the groove formed in the cell active region, an embedded gate electrode, which is disposed so as to fill a lower portion of the groove through the gate insulation film, a capacitance impurity diffusion region, which is disposed in the cell active region that constitutes one side surface of the groove, and a bit line impurity diffusion region, which is disposed in the cell active region that constitutes the other side surface of the groove, wherein

the bit contact hole is formed so as to expose an upper surface of the bit line impurity diffusion region.

A6. The method of manufacturing the semiconductor device as described in A5, wherein:

at the forming the groove, the two grooves are formed so as to divide the cell active region into three; and

at the forming the transistor, the two transistors are formed in the cell active region, and the bit line impurity diffusion region is formed in the cell active region located between the two grooves.

A7. The method of manufacturing the semiconductor device as described in any one of A2 to A6, wherein

at the forming the metal silicide film, a titanium silicide film is formed as the metal silicide film.

A8. The method of manufacturing the semiconductor device as described in any one of A2 to A7, wherein

at the forming the metal laminated film, after the formation of the metal silicide film, a titanium nitride film, a tungsten silicide film, and a tungsten film are sequentially laminated.

A9. The method of manufacturing the semiconductor device as described in any one of A1 to A8, wherein a polysilicon film is formed as the silicon film.

A10. The method of manufacturing the semiconductor device as described in any one of A5 to A9, comprising:

forming a capacitance contact plug whose upper end is disposed above the bit line on the capacitance impurity diffusion region; and

forming a capacitor on the capacitance contact plug.

A11. The method of manufacturing the semiconductor device as described in any one of A1 to A10, wherein

the semiconductor substrate includes a memory cell region where a plurality of the cell active regions are formed; and

the method includes a step of forming, in the memory cell region, an element isolation region that is deeper than the groove and defines a plurality of the cell active regions.

A12. The method of manufacturing the semiconductor device as described in any one of A1 to A11, wherein

the peripheral circuit region includes a peripheral active region where a plurality of the peripheral circuit transistors are formed, and

the method further comprising forming an element isolation region that defines a plurality of the peripheral active regions in the peripheral circuit region.

A13. The method of manufacturing the semiconductor device as described in A12, further comprising

forming a planar transistor in the peripheral active region as the peripheral circuit transistor that contains the peripheral circuit gate insulation film and the gate electrode as components.