Control device for an interleaving power factor corrector

In an interleaving power factor corrector, a control device interleavingly drives first and second converting circuits such that the power factor corrector generates a voltage output (Vo), and includes first and second control modules generating respectively first and second driving signals (Q_master, Q_slave) that correspond respectively to first and second control signals for controlling operations of power switches of the first and second converting circuits. A phase modulating module generates a reset signal (S_PTCL) based on an inverted first driving signal (Qn_master) and a feedback compensation signal (Vcomp) outputted by the first control module, and a reset signal (S_syn) outputted by the second control module. When one of the reset signals (S_syn, S_PTCL) has a predetermined level, the second driving signal (Q_slave) has a level for switching the power switch of the second converting circuit to an OFF-mode.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The invention relates to a control device, more particularly to a control device for an interleaving power factor corrector.

2. Description of the Related Art

Referring toFIG. 1, a conventional interleaving power factor corrector900is shown to include first and second control modules910,920, first and second power switches930,940, and an interleaving circuit950. The first control module910outputs a first control signal (VD1) based on a current (IL1) flowing through an inductor (L1) such that the first power switch930is operable between an ON-mode and an OFF-mode in response to the first control signal (VD1) from the first control module910. When the first control module910detects that the current (IL1) is zero, the first control signal (VD1) outputted by the first control module910has a high level such that the first power switch930is switched to the ON-mode. The second control module920outputs a second control signal (VD2) based on a current (IL2) flowing through an inductor (L2) such that the second power switch940is operable between an ON-mode and an OFF-mode in response to the second control signal (VD2) from the second control module920. When the second control module920detects that the current (IL2) is zero, the second control signal (VD2) outputted by the second control module920has a high level such that the second power switch930is switched to the ON-mode. The first and second control modules910,920are controlled by the interleaving circuit950so that the first and second control signals (VD1, VD2) outputted respectively thereby have a phase difference of T/2 therebetween, i.e., 180°, where T is a cycle period of the current (IL1), as shown inFIG. 2a.

Referring toFIGS. 2ato2e,FIG. 2aillustrates waveforms of the currents (IL1, IL2), wherein S1and S2represent respectively the current (IL1, IL2) in an ideal condition, S3represents the current (IL2) having a lead zero point, and S4represent the current (IL2) having a lag zero point.FIG. 2billustrates a waveform of the first control signal (VD1) corresponding to S1ofFIG. 2a.FIG. 2cillustrates a waveform of the second control signal (VD2) corresponding to S2ofFIG. 2a.FIGS. 2dand2eillustrate waveforms of the second control signal (VD2) corresponding respectively to S3and S4ofFIG. 2a. S1ofFIG. 2aindicates that the current (IL2) has a zero point at t0in the ideal condition. However, the zero point of the current (IL2) may drift as a result of external interference. For example, S3ofFIG. 2aindicates that the current (IL2) has a lead zero point at t2, and S4ofFIG. 2aindicates that the current (IL2) has a lag zero point at t1. Therefore, drift of the zero point of the current (IL2) incurs apparent variation of the duty cycle of the second control signal (VD2), as shown inFIG. 2d, or the diverged duty cycle of the second control signal (VD2), as shown in Figure and2e. Therefore, the conventional interleaving power factor corrector900cannot provide a stable voltage output to the load.

SUMMARY OF THE INVENTION

Therefore, an object of the present invention is to provide a control device for an interleaving power factor corrector that can overcome the aforesaid drawbacks of the prior art.

According to one aspect of the present invention, there is provided a control device for interleavingly driving first and second converting circuits of an interleaving power factor corrector such that the interleaving power factor corrector generates a voltage output (Vo). Each of the first and second converting circuits includes a combination of an inductor and a power switch. The power switches of the first and second converting circuits have control ends for receiving respectively first and second control signals such that the power switch of each of the first and second converting circuits is operable between an ON-mode and an OFF-mode in response to a corresponding one of the first and second control signals. The control device comprises:

a first control module adapted for detecting a current flowing through the inductor of the first converting circuit, outputting a feedback compensation signal (Vcomp) based on the voltage output (Vo) generated by the interleaving power factor corrector, and generating a first driving signal (Q_master) corresponding to the first control signal based on a result of current detection performed thereby and the feedback compensation signal (Vcomp), the first control module further outputting an inverted first driving signal (Qn_master);

a second control module adapted for detecting a current flowing through the inductor of the second converting circuit, receiving the inverted first driving signal (Qn_master) from the first control module, outputting a first reset signal (S_syn) based on the inverted first driving signal (Qn_master) received thereby, and generating a second driving signal (Q_slave) corresponding to the second control signal based on a result of current detection performed thereby, the first reset signal (S_syn) and a second reset signal (S_PTCL), the second control module further outputting an inverted second driving signal (Qn_slave); and

a phase modulating module includinga reference signal generator coupled to the first and second control modules, receiving the inverted first driving signal (Qn_master) and the feedback compensation signal (Vcomp) from the first control module, and the first reset signal (S_syn) from the second control module, and generating a reference signal (Sref) based on the inverted first driving signal (Qn_master), the feedback compensation signal (Vcomp) and the first reset signal (S_syn) received thereby,a ramp generator coupled to the second control module, receiving the inverted second driving signal (Qn_slave) from the second control module, and generating a first ramp signal (Sramp1) based on the inverted second driving signal (Qn_slave) received thereby, anda comparator unit coupled to the reference signal generator and the ramp generator for receiving respectively the reference signal (Sref) and the first ramp signal (Sramp1) therefrom, comparing the reference signal (Sref) and the first ramp signal (Sramp1) received thereby, and outputting the second reset signal (S_PTCL) that has a predetermined level when a level of the first ramp signal (Sramp1) is greater than that of the reference signal (Sref);

When one of the first and second reset signals (S_syn, S_PTCL) has the predetermined level, the second driving signal (Q_slave) generated by the second control module has a level for switching the power switch of the second converting circuit to the OFF-mode.

According to another aspect of the present invention, an interleaving power factor corrector comprises:

first and second converting circuits each including a combination of an inductor and a power switch, the power switches of the first and second converting circuits having control ends for receiving respectively first and second control signals such that the power switch of each of the first and second converting circuits is operable between an ON-mode and an OFF-mode in response to a corresponding one of the first and second control signals; and

a control device for interleavingly driving the first and second converting circuits such that the interleaving power factor corrector outputs a voltage output (Vo), the control device includinga first control module coupled to the first converting circuit, detecting a current flowing through the inductor of the first converting circuit, outputting a feedback compensation signal (Vcomp) based on the voltage output (Vo), and generating a first driving signal (Q_master) corresponding to the first control signal based on a result of current detection performed thereby and the feedback compensation signal (Vcomp), the first control module further outputting an inverted first driving signal (Qn_master),a second control module coupled to the second converting circuit, detecting a current flowing through the inductor of the second converting circuit, receiving the inverted first driving signal (Qn_master) from the first control module, outputting a first reset signal (S_syn) based on the inverted first driving signal (Qn_master) from the first control module, and generating a second driving signal (Q_slave) corresponding to the second control signal based on a result of current detection performed thereby, the first reset signal (S_syn) and a second reset signal (S_PTCL), the second control module further outputting an inverted second driving signal (Qn_slave), anda phase modulating module includinga reference signal generator coupled to the first and second control modules, receiving the inverted first driving signal (Qn_master) and the feedback compensation signal (Vcomp) from the first control module, and the first reset signal (S_syn) from the second control module, and generating a reference signal (Sref) based on the inverted first driving signal (Qn_master), the feedback compensation signal (Vcomp) and the first reset signal (S_syn) received thereby,a ramp generator coupled to the second control module for receiving the inverted second driving signal (Qn_slave) therefrom, and generating a first ramp signal (Sramp1) based on the inverted second driving signal (Qn_slave) received thereby, anda comparator unit coupled to the reference signal generator and the ramp generator for receiving respectively the reference signal (Sref) and the first ramp signal (Sramp1) therefrom, comparing the reference signal (Sref) and the first ramp signal (Sramp1) received thereby, and outputting the second reset signal (S_PTCL) that has a predetermined level when a level of the first ramp signal (Sramp1) is greater than that of the reference signal (Sref).

When one of the first and second reset signals (S_syn, S_PTCL) has the predetermined level, the second driving signal (Q_slave) generated by the second control module has a level for switching the power switch of the second converting circuit to the OFF-mode.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

Referring toFIG. 3, the preferred embodiment of an interleaving power factor corrector100according to the present invention is shown to include an EMI filter40, a bridge rectifier50, a first converting circuit10, a second converting circuit20, and a control device30. In this embodiment, the interleaving power factor corrector100is a boundary condition mode (BCM) power factor corrector.

The filter40is adapted to be coupled to a voltage source101for filtering a voltage input therefrom to eliminate electromagnetic interference.

The bridge rectifier50is coupled to the filter40for rectify the voltage input filtered by the filter40.

In this embodiment, the first and second converting circuits10,20are coupled in parallel each other. Each of the first and second converting circuits10,20includes a combination of an inductor (L1, L2) and a power switch11,12. The power switched11,12of the first and second converting circuits10,20have control ends for receiving respectively first and second control signals such that the power switch11,12of each of the first and second converting circuits10,20is operable between an ON-mode and an OFF-mode in response to a corresponding one of the first and second control signals.

The control device30interleavingly drives the first and second converting circuits10,20such that the first and second converting circuits10,20provide a current output to charge a capacitor (C). Thus, a voltage across the capacitor (C) serves as a voltage output (Vo) that is adapted to be applied to a load60. The control device30includes a first control module31, a second control module32, and a phase modulating module33.

In this embodiment, the first control module31includes a voltage divider311, a feedback amplifier unit, a comparator314, a zero-current detector316, an RS latch317, a ramp generator315, and a driver318. The voltage divider311receives the voltage output (Vo), and generates a divided voltage in accordance with the voltage output (Vo). The feedback amplifier unit includes an amplifier312and a compensation circuit313. The amplifier312has an inverting input end serving as a first input and coupled to the voltage divider for receiving the divided voltage therefrom, a non-inverting input end serving as a second input for receiving a reference voltage (Vref), and an output. The compensation circuit313is coupled between the first input and the output of the amplifier312such that the feedback amplifier unit outputs a feedback compensation signal (Vcomp) at the output of the amplifier312. The feedback compensation signal (Vcomp) is a voltage of 2.5V in this embodiment. The comparator314has an inverting input end coupled to the output of the amplifier412for receiving the feedback compensation signal (Vcomp) therefrom, a non-inverting input end for receiving a ramp signal (Vr), as shown inFIG. 4a,and an output end. The comparator314compares the feedback compensation signal (Vcomp) and the ramp signal (Vr) received thereby, and outputs a reset signal (Rm) based on a comparison result made thereby. The zero-current detector316is coupled to the inductor (L1) of the first converting circuit10for detecting a current (IL1) flowing therethrough, and generates an activating signal (ZCD_master), as shown inFIG. 4b,upon detecting that the current (IL1) flowing through the inductor (L1) of the first converting circuit is zero. The RS latch317has a set input coupled to the zero-current detector316for receiving the activating signal (ZCD_master) therefrom, a reset input coupled to the output end of the comparator314for receiving the reset signal (Rm) therefrom, a data output for outputting a first driving signal (Q_master) corresponding to the first control signal, and an inverted data output for outputting an inverted first driving signal (Qn_master). The ramp generator315is coupled to the inverted data output of the SR latch317and the non-inverting input end of the comparator314, receives the inverted first driving signal (Qn_master) from the inverted data output of the SR latch317, and output the ramp signal (Vr) to the non-inverting input end of the comparator314based on the inverted first driving signal (Qn_master) received thereby. The driver318is coupled to the data output of the RS latch317and the control end of the power switch11of the first converting circuit10, receives the first driving signal (Q_master) from the data output of the RS latch317, and outputs the first control signal to the control end of the power switch11of the first converting circuit10based on the first driving signal (Q_master) received thereby. Referring toFIGS. 4ato4d, when the activating signal (ZCD_master) generated by the zero-current detector316has a high level, the first driving signal (Q_master) has a high level until the ramp signal (Vr) generated by the ramp generator315is greater than the feedback compensation signal (Vcomp), i.e., 2.5V, such that the reset signal (Rm) outputted at the output of comparator314has a high level. Then, the first driving signal (Q_master) is switched from the high level to a low level.

In this embodiment, the second control module32includes an off-time synchronizer321, a zero-current detector322, an RS latch323, and a driver324. The off-time synchronizer321is coupled to the inverted data output of the RS latch317of the first control module31for receiving the inverted first driving signal (Qn_master) therefrom, and outputs a first reset signal (S_syn) upon detecting that the inverted first driving signal (Qn_master) has a predetermined level for a predetermined duration. In this embodiment, the predetermined level is a high level, and the predetermined duration is TS/2, where TSis the time period of a previous cycle of the first driving signal (Q_master), as shown inFIG. 8. The zero-current detector322is coupled to the inductor (L2) of the second converting circuit20for detecting a current (IL2) flowing therethrough, and generates an activating signal (ZCD_slave) upon detecting that the current (IL2) flowing through the inductor (L2) of the second converting circuit20is zero. The RS latch323has a set input coupled to the zero-current detector322for receiving the activating signal (ZCD_slave) therefrom, a reset input for receiving an output signal (Rs), a data output for outputting a second driving signal (Q_slave), and an inverted data output for outputting an inverted second driving signal (Qn_slave). The driver324is coupled to the data output of the RS latch323and the control end of the power switch21of the second converting circuit20, receives the second driving signal (Q_slave) from the data output of the RS latch323, and outputs the second control signal to the control end of the power switch21of the second converting circuit20based on the second driving signal (Q_slave) received thereby.

The phase modulating module33includes a reference signal generator37, a ramp generator36, a comparator unit38, and a logic gate35.

The ramp generator36is coupled to the inverted data output of the RS latch323of the second control module32for receiving the inverted second driving signal (Qn_slave) therefrom, and generates a first ramp signal (Sramp1) based on the inverted second driving signal (Qn_slave) received thereby. Referring further toFIG. 5, in this embodiment, the ramp generator36includes a current source361, and a parallel connection of a switch (Sw1) and a capacitor362coupled between the current source361and a reference node, such as ground. The switch (Sw1) has a control end365coupled to the inverted data output of the SR latch323of the second control module32for receiving the inverted second driving signal (Qn_slave) therefrom. A voltage across the capacitor362serves as the first ramp signal (Sramp). Referring toFIGS. 6band6c, when the inverted second driving signal (Qn_slave) has a low level, the switch (Sw1) is in an OFF-mode such that the capacitor362is charged by a current (Is) from the current source361to a level equal to that of the feedback compensation signal (Vcomp), thereby obtaining the first ramp signal (Sramp). Thus, a charge period (TON) of the capacitor362is represented as follows:

Cs·Vcomp=Is·TON⁢⁢TON=Cs·VcompIs(Equation⁢⁢1)
where Cs is the capacitance of the capacitor362. In this embodiment, the charge period (TON) of the capacitor362serves as the duty cycle of the second driving signal (Q_slave).

The reference signal generator37is coupled to the first and second control modules31,32, receives the inverted first driving signal (Qn_master) and the feedback compensation signal (Vcomp) from the first control module31, and generates a reference signal (Sref) based on the inverted first driving signal (Qm_master), the feedback compensation signal (Vcomp) and the first reset signal (S_syn) received thereby. As shown inFIG. 5, in this embodiment, the reference signal generator37includes a ramp circuit371and a buffer372. The ramp circuit371includes a series connection of a first current source374, a first switch (Sw2), a second switch (Sw3) and a second current source375, a capacitor376, a third switch (Sw4), a fourth switch (Sw5), and an SR latch373. Each of the first and second switches (Sw2, Sw3) has a control end. The capacitor376is coupled between a first common node (n1) of the first and second switches (Sw2, Sw3), and the second current375. The third switch (Sw4) is coupled in parallel to the capacitor376, and has a control end coupled to the off-time synchronizer321for receiving the first reset signal (S_syn) therefrom. The fourth switch (Sw5) is coupled to the first common node (n1), and has a control end. The RS latch373has a set input coupled to the off-time synchronizer321of the second control module32for receiving the first reset signal (S_syn) therefrom, a reset input coupled to the inverted data output of the RS latch317of the first control module31for receiving the inverted first driving signal (Qn_master) therefrom, a data output coupled to the control end of the first switch (Sw2), and an inverted data output coupled to the control ends of the second and fourth switches (Sw3, Sw5). The buffer372is a unity gain buffer in this embodiment, and has a non-inverting input serving as a first input and coupled to the output of the amplifier312of the first control module31for receiving the feedback compensation signal (Vcomp) therefrom, and a second input and an output coupled to a common node (n2) of the second current source375and the capacitor376. A second ramp signal (Sramp2) is generated at the first common node (n1), and serves as the reference signal (Sref) when the fourth switch (Sw5) is in an ON-mode. Referring toFIGS. 7ato7d,during a period from t1to t2, when the first reset signal (S_syn) has a high level, the first and fourth switches (Sw2, Sw5) conduct and the second and third switches (Sw3, Sw4) do not conduct such that the capacitor376is charged by a current (Is2) from the first current source374for the period from t1to t2. Thus, a voltage (Vn) across the capacitor376is represented as follows:

CS⁢⁢2·Vn=IS⁢⁢2·12·Ts⁢⁢Vn=12·IS⁢⁢2CS⁢⁢2·Ts(Equation⁢⁢2)
where CS2is the capacitance of the capacitor376, and Ts is the cycle of the first driving signal (Q_master). The potential at the second common node (n2) maintains a level equal to that of the feedback compensation signal (Vcomp). In this case, the reference signal (Sref) has a level equal to that of the feedback compensation signal (Vcomp). On the other hand, during a period from t2to t3, when the inverted first driving signal (Qn_master) has a high level, the first and fourth switches (Sw2, Sw5) do not conduct and the second and third switches (Sw3, Sw4) conduct such that the capacitor376discharges through the second switch (Sw3). In this case, the second ramp signal (Sramp2) serves as the reference signal (Sref).

The comparator unit38is coupled to the reference signal generator37and the ramp generator36for receiving respectively the reference signal (Sref) and the first ramp signal (Sramp1) therefrom, compares the reference signal (Sref) and the first ramp signal (Sramp1) received thereby, and outputs the second reset signal (S_PTCL) that has a predetermined level when a level of the first ramp signal (Sramp1) is greater than that of the reference signal (Sref). In this embodiment, the predetermined level is a high level. As shown inFIG. 5, the comparator unit38includes a comparator381and a one-shot circuit382. The comparator381has first and second input ends, such as inverting and non-inverting input ends, coupled respectively to the reference signal generator37and the ramp generator36for receiving respectively the reference signal (Sref) and the first ramp signal (Sramp1) therefrom, and an output end for outputting an output based on the reference signal (Sref) and the first ramp signal (Sramp1) received thereby. The one-shot circuit382is coupled to the output end of the comparator, receives the output from the output end of the comparator381, and converts the output received thereby in the form of a pulse. The output converted by the one-shot circuit serves as the second reset signal (S_PTCL).

As shown inFIGS. 3 and 5, the logic gate35is an OR gate in this embodiment, and has first and second inputs351,352coupled respectively to the one-shot circuit381of the comparator unit38and the off-time synchronizer321of the second control module32for receiving respectively the second and first reset signals (S_PTCL, S_syn) therefrom, and an output353coupled to the reset input of the RS latch323of the second control module32for outputting the output signal (Rs) therero. Therefore, when one of the first and second reset signals (S_syn, S_PTCL) has the predetermined level, i.e., the high level, the second driving signal (Q_slave) has a level, i.e., a low level, for switching the power switch21of the second converting circuit20to the OFF-mode.

FIG. 8illustrates waveforms of the first driving signal (Q_master), the inverted first driving signal (Qn_master), the first reset signal (S_syn), the activating signal (ZCD_slave), the first ramp signal (Sramp1), the reference signal (Sref), the second reset signal (S_PTCL), the output signal (Rs) and the second driving signal (Q_slave) when the preferred embodiment is operated in an ideal condition, where delay on the zero-current detector322of the second control module32does not occur and there is no external noise interference in the current (IL2) flowing through the inductor (L2). Referring toFIGS. 3,5and8, during an nthcycle period of the first driving signal (Q_master), i.e., Ts(n), the inverted first driving signal (Qn_master) is switched to a high level at t1. When the inverted first driving signal (Qn_master) maintains the high level for half the period (Ts(n−1)) of an (n−1)thcycle of the first driving signal (Q_master), the off-time synchronizer321outputs the first reset signal (S_syn) having a high level at t5. The activating signal (ZCD_slave) outputted by the zero-current detector322of the second control module32has a high level at t3such that the second driving signal (Q_slave) is switched to a high level at t3and that the inverted second driving signal (Qn_slave) has a low level at t3. Thus, the capacitor362of the ramp generator36is charged to the level of feedback compensation signal (Vcomp) during a period from t3to t5. In other words, the first ramp signal (Sramp1) gradually increases during the period from t3to t5. Since the inverted first driving signal (Qn_master) is switched to the high level at t1, the capacitor367of the ramp circuit371discharges through the second switch (Sw3) during a period of t1to t5such that the reference signal (Sref) gradually decreases to the level of the feedback compensation signal (Vcomp) during the period from t1to t5. The second reset signal (S_PTCL) maintains a low level during the period from t1to t5because the first ramp signal (Sramp1) is not greater than the reference signal (Sref), and the first reset signal (S_syn) is switched to the high level at t5such that the output signal (Rs) is switched to a high level at t5. Thus, the second driving signal (Q_slave) is switched from the high level to a low level at t5.

In this embodiment, the first driving signal (Q_master) has a frequency that varies with the load60. Therefore, a time point at which the activating signal (ZCD_slave) is triggered to have the high level will change.

FIG. 9illustrates waveforms of the first driving signal (Q_master), the inverted first driving signal (Qn_master), the first reset signal (S_syn), the activating signal (ZCD_slave), the first ramp signal (Sramp1), the reference signal (Sref), the second reset signal (S_PTCL), the output signal (Rs), the second driving signal (Q_slave), and the current (IL2) when the preferred embodiment is operated in a lead condition, where a time point at which the current (IL2) becomes zero leads that in the ideal condition.

Referring toFIGS. 3,5and9, during an nthcycle period (Ts(n)) of the first driving signal (Q_master), the activating signal (ZCD_slave) generated by the zero-current detector322is triggered to have the high level at t2earlier to t3at which the activating signal (ZCD_slave), as indicated by dotted lines, is triggered to have the high level in the ideal condition. As a result, a charging period of the capacitor362, i.e., a period from t2to t5, is longer than that in the ideal condition, i.e., the period from t3to t5, such that the first ramp signal (Sramp1) is greater than the reference signal (Sref) at t4. Thus, the second reset signal (S_PTCL) is triggered to have a high level at t4such that the output signal (Rs) is switched to a high level, and the second driving signal (Q_slave) is switched from a high level to a low level at t4earlier to t5at which the second driving signal (Q_slave), as indicated by dotted lines, is switched from a high level to a low level in the ideal condition. In this case, the current (IL2) does not diverge.

FIG. 10illustrate waveforms of the first driving signal (Q_master), the inverted first driving signal (Qn_master), the first reset signal (S_syn), the activating signal (ZCD_slave), the first ramp signal (Sramp1), the reference signal (Sref), a second reset signal (S_PTCL), the output signal (Rs), the second driving signal (Q_slave), and the current (IL2) when the preferred embodiment is operated in a lag condition, where a time point at which the current (IL2) becomes zero lags that in the ideal condition as a result of interference.

Referring toFIGS. 3,5and10, during an nthcycle period (Ts(n)) of the first driving signal (Q_master), the activating signal (ZCD_slave) is triggered to have the high level at t3′ later to t3at which the activating signal (ZCD_slave), as indicated by dotted lines, is triggered to have the high level in the ideal condition. As a result, a charging period of the capacitor362, i.e., a period from t3′ to t5, is shorter than that in the ideal condition, i.e., the period from t3to t5, such that the first ramp signal (Sramp1) is not greater than the reference signal (Sref) during the period from t3′ to t5. Thus, the second reset signal (S_PTCL) maintains a low level during Ts(n). The output signal (Rs) is switched to a high level at t5in response to the first reset signal (S_syn). It is noted that the second driving signal (Q_slave) has a duty cycle, i.e., the period from t3′ to t5, that is shorter than that in the ideal condition, i.e., the period from t3to t5. Therefore, the current (IL2) has a maximum at t5smaller than that in the ideal condition. In other words, energy stored in the inductor (L2) of the second converting circuit20is less than that in the ideal condition.

During an (n+1)thcycle period (Ts(n+1)) of the first driving signal (Q_master), the activating signal (ZCD_slave) is triggered to have the high level at t12earlier to t13at which the activating signal (ZCD_slave), as indicated by dotted lines, is triggered to have the high level in the ideal condition. As a result, a charging period of the capacitor362, i.e., a period from t12to t15, is longer than that in the ideal condition, i.e., the period from t13to t15, such that the first ramp signal (Sramp1) is greater than the reference signal (Sref) at t14. Thus, the second reset signal (S_PTCL) is switched to a high level at t14such that the output signal (Rs) is switched to a high level at t14in response to the second reset signal (S_PTCL), and the second driving signal (Q_slave) is switched from a high level to a low level at t14earlier to t5at which the second driving signal (Q_slave), as indicated by dotted lines, is switched from a high level to a low level in the ideal condition. It is noted that a duty cycle of the second driving signal (Q_slave) in the (n+1)thcycle, i.e., the period from t12to t14, is greater than that in the nthcycle, i.e., the period from t3′ to t5. Therefore, the current (IL2) has a value at t14larger than that at t5. In other words, energy stored in the inductor (L2) of the second converting circuit20during the (n+1)thcycle period (Ts(n+1)) is greater than that during the nthcycle period (Ts(n)).

Similarly, During an (n+2)thcycle period (Ts(n+2)) of the first driving signal (Q_master), the second driving signal (Q_slave) is switched to a high level at t22earlier to t23in the ideal condition. During an (n+3)thcycle period (Ts(n+3)) of the first driving signal (Q_master), the second driving signal (Q_slave) is switched to a high level at t32earlier to t33in the ideal condition. It is noted that a period from t32to t33is less than a period from t22to t23that is less than a period from t12to t13. Therefore, the phase modulating module33is operable so that the second driving signal (Q_slave) gradually converges to approach that in the ideal condition.

In sum, no matter whether drift of the activating signal (ZCD_slave) occurs, i.e., the zero point of the current (IL2) drifts, the phase modulating module33is operable to control the duty cycle of the second driving signal (Q_slave) using the first reset signal (S_syn) or the second reset signal (S_PTCL). Therefore, the second driving signal (Q_slave) can follow variance of the first driving signal (Q_master) even though the duty cycle of the first driving signal (Q_master) varies with the load60, thereby ensuring a stable current (IL2). Thus, the interleaving power factor corrector100of this invention can ensure the stable voltage output (Vo).