Method for manufacturing semiconductor structure with capacitor landing pad

The present disclosure provides a method for manufacturing a semiconductor structure with capacitor landing pads. The method includes the following operations: providing a semiconductor substrate; forming a bit line structure protruding from the semiconductor substrate; depositing a landing pad layer to cover the bit line structure; planarizing a top surface of the landing pad layer; limning a trench in the landing pad layer to form the capacitor landing pads; forming an air gap within a sidewall of the bit line structure; and filling a first dielectric layer in the trench to seal the air gap.

TECHNICAL FIELD

The present disclosure relates to method for manufacturing a semiconductor structure with a capacitor landing pad, and more particularly, to a method for manufacturing the capacitor landing pad in memory device.

DISCUSSION OF THE BACKGROUND

In the semiconductor industry, the products develop toward direction of miniaturization. The design of memory units also moves toward the direction of higher integration and higher density. In order to achieve higher density and high integration, the pitch size is designed smaller and smaller. However, the smaller pitch size causes higher aspect ratio. In other words, elements in the memory unit are designed to have higher aspect ratio. On the other hand, elements having high aspect ratio cause an issue of structural stability during manufacturing which affects the throughput of the manufacturing. Therefore, the stability issue needs to be improved when the aspect ratio keeps increasing.

SUMMARY

One aspect of the present disclosure provides a method for manufacturing a semiconductor structure with capacitor landing pads. The method includes the following operations: providing a semiconductor substrate; forming a bit line structure protruding from the semiconductor substrate; depositing a landing pad layer to cover the bit line structure; planarizing a top surface of the landing pad layer; forming a trench in the landing pad layer to form the capacitor landing pads; forming an air gap within a sidewall of the bit line structure; and filling a first dielectric layer in the trench to seal the air gap.

In some embodiments, the operation of forming the trench in the landing pad layer to form the capacitor landing pads includes the following operations: depositing a plurality of masking layers on the landing pad layer; performing a forward double patterning on the plurality of masking layers to form a hard mask on the landing pad layer; and etching the landing pad layer to form the trench according to the hard mask.

In some embodiments, the operation of depositing the plurality of masking layers on the landing pad layer includes the following operations: depositing a first carbon layer on the landing pad layer; and depositing a second dielectric layer on the first carbon layer.

In some embodiments, the operation of depositing the plurality of masking layers on the landing pad layer further includes the following operations: forming a second carbon layer on the second dielectric layer; forming a third dielectric layer on the second carbon layer; forming a third carbon layer on the third dielectric layer; and forming a fourth dielectric layer on the third carbon layer.

In some embodiments, a height of the first carbon layer is substantially equal to 90 nm, the second dielectric layer includes silicon nitride, the third dielectric layer is a dielectric anti-reflective coating including silicon, and the fourth dielectric layer is a dielectric anti-reflective coating including oxygen.

In some embodiments, the operation of performing the forward double patterning on the plurality of masking layers to form the hard mask on the landing pad layer includes the following operations: patterning the fourth dielectric layer and the third dielectric layer; and etching the fourth dielectric layer, the third carbon layer, the third dielectric layer, and the second carbon layer to form a plurality of carbon rods in the second carbon layer.

In some embodiments, the operation of performing the forward double patterning on the plurality of masking layers to form the hard mask on the landing pad layer further includes deposition an oxide layer to cover the plurality of carbon rods.

In some embodiments, the oxide layer is deposited by an atomic layer deposition (ALD) technology.

In some embodiments, the operation of performing the forward double patterning on the plurality of masking layers to form the hard mask on the landing pad layer further planarizing a top surface of the oxide layer, wherein the top surface of the oxide layer and a top surface of the plurality of carbon rods are coplanar. The remained oxide layer is an upper portion of the hard mask.

In some embodiments, the operation of performing the forward double patterning on the plurality of masking layers to form the hard mask on the landing pad layer further includes etching the plurality of carbon rods, the second dielectric layer, and the first carbon layer to limn the hard mask according to the remained oxide layer.

In some embodiments, the operation of etching the landing pad layer to form the trench according to the hard mask includes etching a portion of the sidewall and a portion of a nitride layer of the bit line structure to expose a top surface of the sidewall of the bit line structure.

In some embodiments, the operation of etching the landing pad layer to form the trench according to the hard mask further includes the following operations: etching the landing pad layer to reach a top surface of the bit line structure; and etching a portion of an adhesive layer of the bit line structure, wherein the adhesive layer includes titanium nitride.

In some embodiments, the operation of forming the trench in the landing pad layer to form the capacitor landing pads further includes performing an aching etching to remove the plurality of masking layers.

In some embodiments, the sidewall of the bit line structure includes an inner dielectric layer, an outer dielectric layer, and a middle oxide layer disposed between the inner dielectric layer and the outer dielectric layer. The operation of forming the air gap within the sidewall of the bit line structure includes etching the middle oxide layer.

In some embodiments, the middle oxide layer is etched by gaseous hydrofluoric acid.

In some embodiments, the method further includes the following operations: planarizing the first dielectric layer, wherein the first dielectric layer and the capacitor landing pads are coplanar; and depositing a fifth dielectric layer on the first dielectric layer and the capacitor landing pads. The fifth dielectric layer includes silicon nitride.

In some embodiments, the trench is partially aligned with the bit line structure.

In some embodiments, the semiconductor substrate includes a first active region, a second active region, and an isolation region disposed between the first active region and the second active region. A bit line contact structure of the bit line structure is formed in contact with the first active region.

In some embodiments, the method further includes the following operations: forming a landing pad contact structure coupled the second active region of the semiconductor substrate; and forming a cobalt silicide layer coupled the landing pad contact structure.

In some embodiments, each of the capacitor landing pads has a step shape. A width of an upper portion of the capacitor landing pads is greater than a width of a bottom portion of the capacitor landing pads.

DETAILED DESCRIPTION

The making and using of the embodiments of the disclosure are discussed in detail below. It should be appreciated, however, that the embodiments provide many applicable inventive concepts that can be embodied in a wide variety of specific contexts. The specific embodiments discussed are merely illustrative of specific ways to make and use the embodiments, and do not limit the scope of the disclosure. Throughout the various views and illustrative embodiments, like reference numerals are used to designate like elements. Reference will now be made in detail to exemplary embodiments illustrated in the accompanying drawings. Wherever possible, the same reference numbers are used in the drawings and the description to refer to the same or like parts. In the drawings, the shape and thickness may be exaggerated for clarity and convenience. This description will be directed in particular to elements forming part of, or cooperating more directly with, an apparatus in accordance with the present disclosure. It is to be understood that elements not specifically shown or described may take various forms. Reference throughout this specification to “one embodiment” or “an embodiment” means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment. Thus, the appearances of the phrases “in one embodiment” or “in an embodiment” in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. It should be appreciated that the following figures are not drawn to scale; rather, these figures are merely intended for illustration.

FIG. 1is a schematic view of a semiconductor structure10according to some embodiments of the present disclosure. The semiconductor structure10includes a semiconductor substrate100, bit line structures200, capacitor landing pads300, a dielectric layer400, and a dielectric layer500. The bit line structures200protrudes from the semiconductor substrate100. The capacitor landing pads300are disposed between the bit line structures200. The dielectric layer400is filled between the capacitor landing pads300to isolate the capacitor landing pads300from each other. The dielectric layer500is disposed above the capacitor landing pads300and the dielectric layer400. As illustrated inFIG. 1, the capacitor landing pads300and the dielectric layer400are coplanar.

InFIG. 1, the semiconductor structure10further includes an adhesive layer600and a contact structure700. The contact structure700is electrically coupled to the active region101. In some embodiments, the contact structure700is configured to provide an ohmic contact for the active region101to the capacitor landing pad300. In other words, the contact structure700is configured to enhance the transportation of the electrical carriers between the active region101and the capacitor landing pad300. The adhesive layer600is disposed between the capacitor landing pad300and the contact structure700. In some embodiments, the adhesive layer60is configured to provide better adhesion between the contact structure700and the capacitor landing pad300. The capacitor landing pad300is electrically coupled to the active region101via the adhesive layer600and the contact structure700in some embodiments, the adhesive layer600includes cobalt silicide (Co2Si). In some embodiments, the contact structure700includes polysilicon.

The semiconductor substrate100includes conductive regions and isolation regions, and the isolation regions are configured to isolate the conductive regions to each other. As shown inFIG. 1, the semiconductor substrate100includes an active region101, an active region102, an active region103, an isolation region104, and an isolation region105. The isolation region104is disposed between the active region101and the active region102, and the isolation region1015is disposed between the active region102and the active region103.

In some embodiments, the active region101, the active region102, and the active region103are silicon doped with dopants. In some embodiments, the active region101, the active region102, and the active region103have the same dopant type, for example, N-type. In some embodiments, the isolation region104and the isolation region105are shallow trench isolation (STI). In some embodiments, the isolation region104and the isolation105are further configured to prevent the capacitor landing pads300from electrically coupling to the active region102.

In order to facilitate understanding, only one bit line structure200is described and denoted with numerals inFIG. 1. The bit line structure200is electrically coupled to the active region102. InFIG. 1, the bit line structure200includes metal layer201, a dielectric layer202, an adhesive layer203, a contact structure204, an adhesive layer205, and a sidewall210.

The metal layer201, the dielectric layer202, the adhesive layer203, and the contact structure204are sandwiched by the sidewall210. The dielectric layer202is disposed on the metal layer201, and in contact with the metal layer201and the dielectric layer400. The metal layer201is coupled to the contact structure204via the adhesive layer203. The contact structure204is disposed above the active region102of the semiconductor substrate100to form electrically contact between the metal layer210and the active region102. In some embodiments, the contact structure204is configured to provide an ohmic contact for the active region102to the metal layer201. The adhesive layer205is formed to cover the sidewall210and the dielectric layer202, and in contact with the dielectric layer400and the capacitor landing pads300,

In some embodiments, the metal layer201includes tungsten (W). In some embodiments, the dielectric layer202includes nitride, for example, silicon nitride (SiN). In some embodiments, the adhesive layer203includes titanium nitride (TiN). In some embodiments, the adhesive layer205includes TiN.

The sidewall210is configured to isolate the metal layer201from the capacitor landing pad300. The sidewall210is a multilayer structure which includes an inner dielectric layer211, an outer dielectric layer212, and an air gap213. The air gap213is disposed between the inner dielectric layer211and the outer dielectric layer212. The inner dielectric layer211is in contact with the dielectric layer202, the metal layer201, the adhesive layer203, the contact structure204, the active region102, and the dielectric layer400. The outer dielectric layer212is in contact with the adhesive layer205, the adhesive layer600, the contact structure700, the isolation region104, and the dielectric layer400. A top surface214of the sidewall210is covered by the dielectric layer400. In some embodiments, the air gap213is configured to decrease the capacitance of the parasitic capacitance in the semiconductor structure10.

The capacitor landing pad300is in contact with the adhesive layer205of the bit line structure200and the dielectric layer400. As shown inFIG. 1, the capacitor landing pad300has a step shape. In some embodiments, a width W1of an upper portion of the capacitor landing pad300is greater than a width W2of a bottom portion of the capacitor landing pad300. In some embodiments, the capacitor landing pad300includes W.

The above configuration of the semiconductor structure10is provided for illustrated purposes. Various configurations of the semiconductor structure10are within the contemplated scope of the present disclosure. For example, in various embodiments, the semiconductor structure10includes other suitable material to form the capacitor landing pad300, the contact structure700, and the contact structure204.

In some embodiments, the semiconductor structure10is part of a memory device, for example, a dynamic random access memory (DRAM). The memory device includes at least one transistor, the transistor has a gate coupled to a word line of the memory device, a source/drain coupled to a bit line of the memory device, and another source/drain coupled to a capacitor of the memory device. The source/drain coupled to the bit line corresponds to the active region102coupled to the bit line structure200. The source/drain coupled to the capacitor corresponds to the active region101coupled to the capacitor landing pads300. In other embodiments, the semiconductor structure10further includes recess (no shown) in the semiconductor substrate100. The gate of the memory device corresponds to the recess of the semiconductor structure10.

FIG. 2is illustrated a flowchart of a method20for manufacturing the semiconductor structure10shown inFIG. 1according to some embodiments of the present disclosure. The method20includes an operation S201, an operation S202, an operation S203, an operation S204, an operation S205, an operation S206, an operation S207, an operation S208, an operation S209, an operation S210, and an operation S211.FIG. 3toFIG. 7are illustrated detailed flowcharts of the operations of the method20shown inFIG. 2according the some embodiments of the present disclosure.FIG. 8toFIG. 28are illustrate schematic views in each steps of the manufacturing process of the semiconductor structure10shown inFIG. 1according to some embodiments of the present disclosure. In addition, the method20inFIG. 2toFIG. 7are described with respect to the schematic view V8to the schematic view V28inFIG. 8toFIG. 28, and the like elements shown inFIG. 8toFIG. 28are designated with the same numerals inFIG. 1to facilitate understanding.

Reference is made toFIG. 2andFIG. 8. In operation S201, the semiconductor substrate100is provided. In operation S202, the bit line structure200is formed protruding from the semiconductor substrate100. In operation S203, the landing pad contact structure700is formed and coupled to the active region101of the semiconductor substrate100. In operation S204, the cobalt silicide layer600(i.e., adhesive layer600) is formed and coupled the landing pad contact structure700.

As illustrated inFIG. 8, the schematic view V8shows that the semiconductor substrate100is provided with the active region101, the active region102, the active region103, the isolation region104, and the isolation region105. The bit line structure200is formed with bit line contact structure204, the metal layer201, the dielectric layer202, the adhesive layer203, the sidewall210, and the adhesive layer205. The sidewall210is formed with the inner dielectric layer211, the outer dielectric layer212, and an middle oxide layer216disposed between the inner dielectric layer211and the outer dielectric layer212.

Compared to the semiconductor structure10, the sidewall210in the schematic view V8includes the middle oxide layer216in the sidewall210, and does not includes air gap213in the sidewall210. The middle oxide layer216would be etched in the later operation to form the air gap216. The details will be described with respect to the operation S208below.

Reference is further made toFIG. 9. In operation S205, the landing pad layer310is deposited to cover the bit line structure200. In operation S206, the top surface of the land pad layer310is planarized. As illustrated inFIG. 9, the schematic view V9shows that the landing pad layer310covers the contour of the bit line structure200. After planarization, the landing pad layer310has a substantially flat top surface. The landing pad layer310will be etched in the later operation to form the capacitor landing pads300. Therefore, the landing pad layer310and the capacitor landing pads300have the same material.

Reference is further made toFIG. 3andFIG. 10toFIG. 24. In operation S207, trenches TC in the landing pad layer310is formed for forming the capacitor landing pads300. In some embodiments, the operation S207includes an operation S2071, an operation S2072, an operation S2073, and an operation S2074.

In operation S2071, masking layers ML are deposited on the landing pad layer310. In operation S2072, a forward double patterning is performed on the masking layers ML to form a hard mask HM on the landing pad layer310. In operation S2073, the landing pad layer310is etched to form the trenches TC according to the hard mask HM. In operation S2074, an ashing etching is performed to remove the masking layers ML.

In some embodiments, the masking layers ML includes carbon layers and dielectric layers alternatively disposed. The masking layers ML are configured to be etched so as to form the hard mask HK for the formation of the trenches TC. In some embodiments, the operation S2071includes an operation S20711, an operation S20712, an operation S20713, an operation S20714, an operation S20715, and an operation S20716.

In operation S20711, a carbon layer C1is deposited on the landing pad layer310. InFIG. 10, the schematic view V11shows the deposition of the carbon layer C1on the landing pad layer310. In some embodiments, the carbon layer C1has a height which is substantially equal to 90 nm.

In operation S20712, a dielectric layer D1is deposited on the carbon layer C1. InFIG. 11, the schematic view V11shows the deposition of the dielectric layer D1on the carbon layer C1. In some embodiments, the dielectric layer D1includes SiN.

In operation S20713, a carbon layer C2is deposited on the dielectric layer D1. InFIG. 12, the schematic view V12shows the deposition of the carbon layer C2on the dielectric layer D1.

In operation S20714, a dielectric layer D2is deposited on the carbon layer C2. InFIG. 13, the schematic view V13shows the deposition of the dielectric layer D2on the carbon layer C2. In some embodiments, the dielectric layer D2includes S1. In some embodiments, the dielectric layer D2is dielectric anti-reflective coating.

In operation S20715, a carbon layer C3is deposited on the dielectric layer D2. InFIG. 14, the schematic view V14shows the deposition of the carbon layer C3on the dielectric layer D2.

In operation S20716, a dielectric layer D3is deposited on the carbon layer C3. InFIG. 15, the schematic view V15shows the deposition of the dielectric layer D3on the carbon layer C3, in some embodiments, the dielectric layer D3includes O. In some embodiments, the dielectric layer D3is dielectric anti-reflective coating.

In this embodiments, the masking layer ML includes the carbon layer C1, the carbon layer C2, the carbon layer (73, the dielectric layer D1, the dielectric layer D2, and the dielectric layer D3. After the masking layers ML are formed, the operation S2072is performed. In some embodiments, the operation S2072includes an operation S20721, an operation S20722, an operation S20723, an operation S20724, and an operation S20725.

In operation S20721, the dielectric layer D3and the dielectric layer S2are patterned. InFIG. 16, the schematic view V16shows the dielectric layer D3is patterned. InFIG. 17, the schematic view V17shows the dielectric layer D2is patterned. In some embodiments, the patterned dielectric layer D2and the patterned dielectric layer D3are not aligned. The configuration of the patterned dielectric layer D2and the patterned dielectric layer D3is provided for illustrative purposes but not limited thereto.

In operation S20723, an oxide layer OX is deposited to cover the carbon rods C2R. In operation S20724, a top surthce of the oxide layer OX is planarized. In some embodiments, the operation S20724is performed by chemical mechanical polishing (CMP). In other embodiments, the operation S2.0724is performed by etching back. In some embodiments, the top surface of the oxide layer OX and a top surface of the carbon rods C2R are coplanar after the operation S20724, InFIG. 19, the schematic view V19shows the oxide layer OX filled between the carbon rods C2R, and the oxide layer OX and the carbon rods C2R are coplanar after the planarization.

In operation S20725, the carbon rods C2R, the dielectric layer D2, and the carbon layer C1are etched to form the hard mask HM according to the remained oxide layer OX. The carbon rods C2R are etched during the operation S20725. In addition, a portion of the dielectric layer D1and a portion of the carbon C1corresponding to the carbon rods C2R are also etched during the operation S20725. InFIG. 20, the schematic view V20shows that the carbon rods C2R are removed and the oxide layer OX are remained on the dielectric layer D1. InFIG. 21, the schematic view V21shows the etched dielectric layer D1corresponding to the etched carbon rods C2R. InFIG. 22, the schematic view V22shows the etched carbon layer C1corresponding to the etched carbon rods C2R and the etched dielectric layer D1. More specifically, the etched dielectric layer D1and the etched carbon layer C1are aligned with the carbon rods C2R. The hard mask HM thus includes the remained oxide layer OX in the upper portion, the remained dielectric layer D1in the middle portion, and the remained carbon layer C1in the bottom portion.

After the hard mask HM is formed, the operation S2073is performed. In some embodiments, the operation S2073includes an operation S20731, an operation S20732, and an operation S20733. In some embodiments, the trenched TC are partially aligned with the bit line structure200. More specifically, the landing pad layer310being etched (i.e., the positions where the trenches TC will be located) overlaps a portion of bit line structure200. Therefore, during etching the landing pad layer310, the portion of the bit line structure200will be etched.

In operation S20731, the landing pad layer310is etched to reach a top surface of the bit line structure200. InFIG. 23, the schematic view V23shows that the landing pad layer310is etched to have a bottom reaching the bit line structure200.

In operation S20732, the adhesive layer205of the bit line structure200is etched. InFIG. 24, the schematic view V24shows a portion of adhesive layer205is etched.

In operation S20733, a portion sidewall210and a portion of the dielectric layer202of the bit line structure200are etched to expose the top surface214of the sidewall210of the bit line structure200. InFIG. 25, the schematic view V25shows that the capacitor landing pads300are formed after the landing pad layer310is etched. Further, the portion of sidewall210and the portion of dielectric layer202are etched. The top surface210of the sidewall210is then exposed. The top surface214includes three sections which are a top surface of the inner dielectric layer211, a top surface of the outer dielectric layer212, and a top surface of the middle oxide layer216.

After the operations S20731, S20732, and207233are perfbnned, the trenches TC and the capacitor landing pads300are formed. The hard mask HM (i.e., the remained masking layers ML) are removed by the operation S2074as illustrated inFIG. 26. InFIG. 26, the schematic view V26also shows that the formed capacitor landing pads300have the width W1of the upper portion greater than the width W2of the bottom portion. The width W1is associated the dimension of the hard mask HM. The dimension of the hard mask HM is further associated with the dimension of the carbon rods C2R. The dimension of the carbon rods C2R is controlled by the forward double patterning performed in the operation S2072. Alternatively stated, the width W1is controlled by the operation S2072.

In operation S208, the air gap213within the sidewall210of the bit line structure200is formed. In some embodiments, the operation S208includes an operation S2081, in operation S2081, the middle oxide layer216is etched, and the space occupied by the original middle oxide layer216becomes the air gap213. InFIG. 27, the schematic view V27shows that the air gap213which is connected to the trenches TC. In some embodiments, the middle oxide layer216is etched by gaseous hydrofluoric acid. However, the etchant used in the operation S2081is not limited to gaseous hydrofluoric acid. In other embodiments, the operation S2081uses other suitable etchant to etch the middle oxide layer216.

In operation S209, the dielectric layer400is filled in the trenches TC to seal the air gap213. In operation S210, the dielectric layer400is planarized. InFIG. 28, the schematic view V28shows that the top surface214of the sidewall210is covered by the dielectric layer400, and the air gap213is sealed by the filled dielectric layer400. In addition, the dielectric layer400and the capacitor landing pads300are coplanar after the planarization.

In operation S211, the dielectric layer500is deposited on the capacitor land pads300. After the operation S211, the semiconductor structure10shown inFIG. 1is formed.

In some embodiments, after the operation S211, a planarization process is performed to planarize the dielectric layer500so as to form another capacitor pad (not shown) on the dielectric layer500opposite to the capacitor landing pads300.

One aspect of the present disclosure provides a method for manufacturing a semiconductor structure with capacitor landing pads. The method includes the following operations: providing a semiconductor substrate; forming a bit line structure protruding from the semiconductor substrate; depositing a landing pad layer to cover the bit line structure; planarizing a top surface of the landing pad layer; forming a trench in the landing pad layer to form the capacitor landing pads; forming an air gap within a sidewall of the bit line structure; and filling a first dielectric layer in the trench to seal the air gap.