Memory device performing control of discarding packet

According to one embodiment, a memory device includes a nonvolatile first memory, a second memory, a controller, and an interface unit. When receiving a first packet from the interface unit, the controller transmits a second packet to an initiator via the interface unit. In the case where a header of a third packet does not match the second packet, the controller does not store the third packet to a second memory, the third packet being discarded.

FIELD

Embodiments described herein relate generally to a memory device and a memory controller having a nonvolatile memory.

BACKGROUND

UFS (Universal Flash Storage) is a storage standard which is developed for the purpose of achieving high throughput and low power consumption. In the UFS standard, a host is referred to as an initiator, and a memory device serving as an external storage device is referred to as a target. The target includes a nonvolatile memory such as a NAND-type flash memory.

In the UFS standard, when the target receives a write command from the initiator, the target prepares for the write command, and transmits Ready To Transfer UPIU designating the receivable data size and the like to the initiator. In response thereto, the initiator transmits Data Out UPIU serving as write data to the target. A packet based on UFS standard is referred to as UPIU.

DETAILED DESCRIPTION

In general, according to one embodiment, a memory device includes a nonvolatile first memory, a second memory, an interface unit, and a controller. The controller is configured to control the interface unit. when receiving a first packet from the interface unit, the controller transmits a second packet to an initiator via the interface unit, the first packet being a write command received from the initiator, the second packet requesting data transfer to the initiator, the second packet specifying content of a third packet. the interface unit includes a comparison unit configured to compare the second packet transmitted to the initiator with a header of the third packet received from the initiator, the third packet including the header and data. In the case where the header of the third packet matches the second packet, the controller temporarily stores the third packet to the second memory, and writes the data of the temporarily stored third packet to the first memory. In the case where the header of the third packet does not match the second packet, the controller does not store the third packet to the second memory, the third packet being discarded.

Exemplary embodiments of a memory device and a memory controller will be explained below in detail with reference to the accompanying drawings. The present invention is not limited to the following embodiments.

First Embodiment

FIG. 1is a block diagram illustrating an example of internal configuration of a target1which is a memory device according to a first embodiment to which UFS standard is applied. The target1is connected to an initiator2, serving as a host, via a communication path20, and functions as an external storage device of the initiator2. The target1and the initiator2are based on UFS standard. The initiator2is, for example, a cellphone, a personal computer, or an imaging device.

The target1includes a controller3and a NAND-type flash memory (hereinafter abbreviated as NAND)4serving as a nonvolatile memory. The NAND4includes one or more memory chips having memory cell arrays. The memory cell array has a plurality of memory cells arranged in a matrix form. Each of memory cell arrays has a plurality of blocks arranged therein, the blocks are units of erasing of data. Each block includes a plurality of pages. The page is the minimum unit of reading and writing. The controller3executes data transfer control between the initiator2and the NAND4.

The nonvolatile memory4is not limited to a NAND flash. The nonvolatile memory4may be three-dimensional structure flash memory, ReRAM (Resistance Random Access Memory)), FeRAM (Ferroelectric Random Access Memory), a hard disk, and the like.

The initiator2issues a write command and write data to the target1. The initiator2issues a read command to the target1. The write command, the read command, and the write data is transmitted, as a packet based on UFS standard, to the initiator2.

The target1includes an initiator interface5, an internal memory6, a NAND interface7, a CPU (processor)8, and a bus9.

The initiator I/F5transmits and receives a command packet and data packet to/from the initiator2via the communication path20. The initiator I/F5includes a reception unit10, and receives a packet from the initiator2. The initiator I/F5includes a transmission unit11, and transmits a packet to the initiator2. Hereinafter, a packet will be referred to as UPIU.

In accordance with the control of the CPU8, the NAND I/F7executes the write control to NAND4, and the read control from the NAND4.

The internal memory6is a memory allowing for a higher speed access than the NAND4. The internal memory6has a storage area for temporarily storing the data before data received from the initiator2are written to the NAND4via the NAND I/F7. The internal memory6has a storage area for temporarily storing data read from the NAND4via the NAND I/F7. The internal memory6has a storage area for storing and updating management information for managing the target1. The management information includes a mapping table indicating relationship between a logical address designated by the initiator2and a storage position (physical address) on the NAND4. The management information is backed up by the NAND4. For example, the SRAM (Static Random Access Memory) and the DRAM (Dynamic Random Access Memory) are used as the internal memory6.

The CPU8achieves the function by executing the firmware. The CPU8totally controls internal constituent elements of the target1. The CPU8controls transmission/reception of UPIU between the initiator2and the initiator I/F5. The CPU8reads a command received by the reception unit10of the initiator I/F5, and executes processing according to the read command. When write data is received from the initiator2, the CPU9controls the initiator I/F5to temporarily store the write data to the internal memory6. The CPU8reads the write data from the internal memory6, and writes the read data to the NAND4via the NAND I/F7. The CPU8updates the management information in the internal memory6in accordance with the write processing.

When the read command is received from the initiator2, the CPU8identifies the position on the NAND4designated by the read command on the basis of the management information, and reads data from the NAND4on the basis of the identified position information. The read data is temporarily stored to the internal memory6via the NAND I/F7, and thereafter, the read data is transmitted via the transmission unit11of the initiator I/F5to the initiator2.

In the UFS standard, a Command UPIU is used as a request of reading and writing given by the initiator2. The Command UPIU includes a field of a logical address and a field of size information (data length). The Response UPIU is a UPIU issued by the target1when the execution of the processing requested by the initiator2with the Command UPIU has been finished. More specifically, when the processing requested by the Command UPIU is finished, the target1transmits a Response UPIU corresponding to the Command UPIU.

In the UFS standard, the transfer of data between the initiator2and the target1is executed such that the data is divided into small data in a size DS. The Data In UPIU is used to transfer read data from the target1to the initiator2. More specifically, the Data In UPIU is an UPIU issued by the target1when the divided small data is transferred from the target1to the initiator2. A Ready To Transfer UPIU (hereinafter abbreviated as RTT UPIU) is a UPIU issued by the target1every time it is ready to receive divided small data. A Data Out UPIU is used when write data is transferred from the initiator2to the target1. More specifically, a Data Out UPIU is a UPIU issued by the initiator2when divided small data is transferred from the initiator2to the target1. The divided small data is transferred as a payload of the Data In UPIU or the Data Out UPIU through the communication path20.

FIG. 2is a timing chart for explaining an example of communication procedure during writing. First, the initiator2transmits a write command in a format of Command UPIU to the target1. As described above, the write command includes a field of Logical Unit Number (LUN), a field of Task Tag, a field of logical address, a field of data length, and the like. The LUN designates a partition number on the NAND4. The Task Tag is information for identifying the Command UPIU.

When the target1receives the write command, an area for receiving the write data is assigned in the internal memory6. And when the target1is ready to receive the data, the target1transmits the RTT UPIU to the initiator2. The RTT UPIU includes LUN, Task Tag, data size DS, and write address WAD. The LUN and the Task Tag included in the RTT UPIU are the same as the LUN and the Task Tag included in the corresponding write command UPIU from the initiator2.

The data size DS is a data size that can be currently received by the target1, and indicates the size of the divided small data. The write address indicates the logical address at the head of the divided small data.

When this RTT UPIU is received, the initiator2extracts, from the write data designated by the write command, data starting from the write address WAD and having a size designated by the data size DS, and transmits the extracted data to the target1, using the Data Out UPIU as a header. The Data Out UPIU includes the same LUN, Task Tag, data size DS, and write address WAD as the LUN, Task Tag, data size DS, and write address WAD included in the corresponding RTT UPIU. Thus, RTT UPIU requests data transfer to the initiator and specifies contents of Data Out UPIU.

When the target1receives this Data Out UPIU, the target1buffers the data included in the payload of the Data Out UPIU to the internal memory6. The transmission and the reception of the RTT UPIU and the divided small data are repeated until the transfer of all the write data designated by the write command has been finished. The data size DS designated by the RTT UPIU may be different for each RTT UPIU. When the target1receives all the data to be written, the target1transmits the Response UPIU to the initiator2. The LUN and the Task Tag included in the Response UPIU are the same as the LUN and the Task Tag included in the corresponding write command UPIU from the initiator2.

FIG. 3is a timing chart for explaining another example of communication procedure during writing. In the UFS communication inFIG. 3, up to N RTT UPIUs can be transmitted continuously. In the case ofFIG. 3, N is 2. The communication between the initiator2and the target1determines that up to N RTT UPIUs can be transmitted continuously. In the case ofFIG. 3, the target1transmits two RTT UPIUs continuously to the initiator2. In response thereto, the initiator2transmits two Data Out UPIUs continuously to the target1.

In the communication of the write command according to the UFS standard, information included in the RTT UPIU and header information in the Data Out UPIU actually received may be different. Such situation may occur in a case where there is discrepancy between the processing contents of the initiator2and the target1. For example, the initiator2interrupts writing of data corresponding to the write command, and before the interruption processing of the initiator2is completed, processing of another write command is performed. In this case, discrepancy occurs between the information of the RTT UPIU and the header information of the Data Out UPIU.

In the UFS standard, the target1is a slave for the initiator2, and therefore, the reception operation cannot be kept waiting. In a method according to a comparative example for storing all the received data to the internal memory6, the internal memory6also stores data included in the Data Out UPIU having a header different from the RTT UPIU commanded by the initiator2. For this reason, even if it thereafter tries to receive normal Data Out UPIU, the normal Data Out UPIU may not be received because of the shortage of the internal memory6.

Therefore, in the present embodiment, the target1saves a history of the transmitted RTT UPIU, and compares header of the received Data Out UPIU with the saved history of the RTT UPIU, and does not store, to the internal memory6, the Data Out UPIU that does not match the history of the RTT UPIU saved, and discards the Data Out UPIU.

InFIG. 1, the reception unit10of the initiator I/F5includes an RTT storing unit12and an RTT comparator13. The CPU8generates one or more RTT UPIUs on the basis of the write command in the format of the Command UPIU received from the initiator2, and inputs the generated RTT UPIU into the transmission unit11. The transmission unit11transmits the RTT UPIU to the initiator2, and outputs the transmitted RTT UPIU to the reception unit10.

The RTT storing unit12stores the transmitted RTT UPIU which is input from the transmission unit11. The RTT comparator13compares the header of the Data Out UPIU received from the initiator2with the RTT UPIU stored in the RTT storing unit12. When the header is determined to match therewith by the RTT comparator13, the matching RTT UPIU is deleted from the RTT storing unit12.

As illustrated inFIG. 2, in a case of UFS communication in which RTT UPIUs are transmitted one by one, the RTT storing unit12store only a single RTT UPIU, and therefore, there is only one RTT UPIU which is to be compared with the Data Out UPIU in the RTT comparator. However, up to N RTT UPIUs can be transmitted continuously as illustrated inFIG. 3, the RTT storing unit12stores up to N RTT UPIUs. The UFS communication does not permit overtaking of Data Out UPIU. The overtaking of the Data Out UPIU means a Data Out2is received earlier than a Data Out1by the target1inFIG. 3. For this reason, in a case where up to N RTT UPIUs can be transmitted continuously, what is to be compared with the Data Out UPIU by the RTT comparator is an RTT UPIU stored at the earliest point in time in the RTT storing unit12, and in other words, it is an RTT UPIU stored first. In a case of a standard where overtaking is permitted, a determination is made as to whether the header of the Data Out UPIU matches any one of the RTT UPIUs stored in the RTT storing unit12.

FIG. 4is a flowchart illustrating reception processing of RTT UPIU by the reception unit10. The reception unit10receives the header of a Data Out UPIU (step S100). When the reception unit10receives the header of the Data Out UPIU, the RTT comparator13compares the header of the received Data Out UPIU with the comparison target RTT UPIU stored in the RTT storing unit12(step S110). In this comparison, the LUN, the Task Tag, the data size DS, and the write address WAD in the UPIU are compared.

When the comparison result matches by the RTT comparator13, the reception unit10stores the payload of the received Data Out UPIU to the internal memory6, and deletes the matching RTT UPIU from the RTT storing unit12(step S120). However, when the comparison result does not match in step S110, the reception unit10does not store the payload of the received Data Out UPIU to the internal memory6, and discards the payload (step S130).

FIG. 5is a timing chart for explaining an example of communication procedure during writing according to the present embodiment. The initiator2transmits the write command in the format of the Command UPIU to the target1. As described above, the write command includes the field of the LUN, the field of the Task Tag, the field of the logical address, the field of the data length, and the like.

When the target1receives the write command, an area for receiving the write data is assigned in the internal memory6, and when it is ready to receive data, the RTT UPIU1is transmitted to the initiator2. The RTT UPIU1includes the LUN, the Task Tag, the data size DS, and the write address WAD. The transmitted RTT UPIU is temporarily stored in the RTT storing unit12.

Thereafter, suppose that the initiator2transmits a Data Out UPIU X having a header different from the RTT UPIU1. The reception unit10of the target1compares the RTT UPIU1temporarily stored in the RTT storing unit12as described above with the header of the received Data Out UPIU X. This comparison does not match, and therefore, the payload of the Data Out UPIU X is not stored to the internal memory6, and is discarded. Thereafter, when the Data Out UPIU1having the header matching the RTT UPIU1is received, the payload of this Data Out UPIU1is stored to the internal memory6.

Therefore, in the present embodiment, even when the Data Out UPIU having the header different from the RTT UPIU is received, there would be no shortage of the remaining capacity of the internal memory6, and the normal Data Out UPIU can be received. By the way, when the Data Out UPIU1having the header matching the RTT UPIU1is received, the header and the payload of this Data Out UPIU1may be stored to the internal memory6.

By the way, an abort request of write command may be transmitted from the initiator2. For example, after the initiator2transmits the write command, the target1transmits the RTT UPIU corresponding to the write command to the initiator2. Thereafter, because of the loss of data which is to be written and which corresponds to the write command or because of the interruption of the writing itself, the initiator2cannot send the data corresponding to the RTT UPIU. In such case, the initiator2issues an abort request of the write command to the target1.

In the present embodiment, when the abort request of the write command is received from the initiator2after the RTT UPIU is transmitted to the initiator2, the RTT UPIU corresponding to the abort request is deleted from the RTT storing unit12. For this reason, thereafter, only the normal Data Out UPIU, which is scheduled, can be received. By the way, when the aborted Data Out UPIU is transmitted by the initiator2by mistake, this does not match the RTT transmission history stored in the RTT storing unit12, and therefore the data is discarded.

Second Embodiment

In a second embodiment, when a payload of a Data Out UPIU is discarded, a target1notifies an initiator2that the writing has failed.FIG. 6is a flowchart illustrating reception processing of RTT UPIU in a reception unit10according to the second embodiment. InFIG. 6, the processing contents in steps S100to S130are the same processing contents in steps S100to S130as illustrated inFIG. 4, and repeated explanation is omitted.

InFIG. 6, when the comparison result does not match in step S110, the reception unit10does not store the payload of the received Data Out UPIU to the internal memory6, and discards the payload (step S130). Subsequently, the initiator I/F5notifies the interruption to the CPU8(step S141). In response to this notification, the CPU8stops the write processing (step S142). The CPU8transmits the Response UPIU, notifying that the writing has failed, to the initiator2via the transmission unit11of the initiator I/F5(step S143).

As described above, in the second embodiment, when the payload of the Data Out UPIU is discarded, the target1uses the Response UPIU in response to the write command to notify the initiator2that the writing has failed, and this allows efficient recovery back to normal communication.

Third Embodiment

In a third embodiment, when a normal Data Out UPIU is received, a target1transmits a subsequent RTT UPIU.FIG. 7is a block diagram illustrating an example of internal configuration of the target1according to the third embodiment. InFIG. 7, an RTT transmission FIFO15is added to the transmission unit11ofFIG. 1. The RTT transmission FIFO15stores multiple RTT UPIUs, which are to be transmitted to the initiator2, in accordance with FIFO (First in First out) method. More specifically, the RTT UPIUs generated by the CPU8are successively stored to the RTT transmission FIFO15.

FIG. 8is a flowchart illustrating reception processing of RTT UPIU in the reception unit10according to the third embodiment. InFIG. 8, the processing contents in steps S100to S130are the same processing contents in steps S100to S130as illustrated inFIG. 4, and repeated explanation is omitted. When the comparison result matches in the RTT comparator13, the reception unit10stores the payload of the received Data Out UPIU to the internal memory6, and deletes the matching RTT UPIU from the RTT storing unit12(step S120). When the processing in step S120is finished, the transmission unit11determines whether an RTT UPIU, which is to be subsequently transmitted, is stored in the RTT transmission FIFO15or not (step S150). When the determination result in step S150is Yes, the transmission unit11transmits a subsequent RTT UPIU stored in the RTT transmission FIFO15to the initiator2(step S150). When the determination result in step S150is Yes, the transmission unit11terminates the processing.

As described above, according to the third embodiment, when the normal Data Out UPIU is received, the target1transmits the subsequent RTT UPIU, and therefore, the RTT UPIU can be transmitted efficiently.