CLOCK GATING CELL FOR LOW SETUP TIME FOR HIGH FREQUENCY DESIGNS

According to certain aspects, a method for clock gating includes receiving an enable signal, and latching a logic value of the enable signal on an edge of an input clock signal. The method also includes passing the latched logic value of the enable signal to a clock-gating output when the input clock signal is logically high, blocking the latched logic value of the enable signal from the clock-gating output when the input clock signal is logically low, and pulling the clock-gating output logically low when the input clock signal is logically low.

BACKGROUND

Field

Aspects of the present disclosure relate generally to clock gating, and more particularly, to clock gating cells.

Background

Reducing power consumption in a mobile device is important in order to extend the battery life of the mobile device. A significant contributor to power consumption of a chip (die) in a mobile device is dynamic power dissipation, which is due to switching of transistors on the chip. In this regard, various power reduction schemes have been developed to reduce dynamic power consumption on a chip. One scheme involves selectively gating a clock signal to a circuit block on the chip using a clock gating cell, in which the clock gating cell gates the clock signal when the circuit block is not in use. Gating the clock signal stops transistors in the circuit block from switching, thereby reducing the dynamic power dissipation of the circuit block.

SUMMARY

A first aspect relates to a clock gating cell. The clock gating cell includes a latch having an input and an output, wherein the latch is configured to receive an enable signal at the input of the latch, to latch a logic value of the enable signal on an edge of an input clock signal, and to output the latched logic value at the output of the latch. The clock gating cell also includes a transmission gate coupled between the output of the latch and an output of the clock gating cell, wherein the transmission gate is configured to couple the output of the latch to the output of the clock gating cell when the input clock signal is logically high, and to decouple the output of the latch from the output of the clock gating cell when the input clock signal is logically low. The clock gating cell further includes a pull-down transistor coupled between the output of the clock gating cell and a ground, wherein the pull-down transistor is configured to pull the output of the clock gating cell to the ground when the input clock signal is logically low.

A second aspect relates to a clock gating cell. The clock gating cell includes a latch having an input and an output, wherein the latch is configured to receive an enable signal at the input of the latch, to latch an inverted logic value of the enable signal on an edge of an input clock signal, and to output the latched inverted logic value of the enable signal at the output of the latch. The clock gating cell also includes a transmission gate coupled between the output of the latch and a transmission node, wherein the transmission gate is configured to couple the output of the latch to the transmission node when the input clock signal is logically high, and to decouple the output of the latch from the output of the transmission node when the input clock signal is logically low. The clock gating cell further includes an output inverter having an input coupled to the transmission node and an output coupled to an output of the clock gating cell, and a pull-up transistor coupled between the transmission node and a supply rail, wherein the pull-up transistor is configured to pull the transmission node to the supply rail when the input clock signal is logically low.

A third aspect relates to a method for clock gating. The method includes receiving an enable signal, and latching a logic value of the enable signal on an edge of an input clock signal. The method also includes passing the latched logic value of the enable signal to a clock-gating output when the input clock signal is logically high, blocking the latched logic value of the enable signal from the clock-gating output when the input clock signal is logically low, and pulling the clock-gating output logically low when the input clock signal is logically low.

A fourth aspect relates to a method for clock gating. The method includes receiving an enable signal, and latching an inverted logic value of the enable signal on an edge of an input clock signal. The method also includes passing the latched inverted logic value of the enable signal to a transmission node when the input clock signal is logically high, blocking the latched inverted logic value of the enable signal from the transmission node when the input clock signal is logically low, and pulling the transmission node logically high when the input clock signal is logically low. The method further includes inverting the latched inverted logic value of the enable signal at the transmission node.

DETAILED DESCRIPTION

A clock gating cell (CGC)110typically includes a latch for latching an enable signal, and one or more logic gates for selectively gating a clock signal based on the logic value of the latched enable signal. In this regard,FIG. 1shows an exemplary implementation of a clock gating cell (CGC)110for selectively gating a clock signal (denoted “clk_in”). In this example, the CGC110includes a negative-edge triggered latch120and an AND gate130. The latch120has an enable input that receives an enable signal (denoted “en”), a clock input that receives the input clock signal clk_in, and an output. The AND gate130has a first input coupled to the output of the latch120, a second input that receives the input clock signal clk_in, and an output that outputs the output clock signal clk_out of the CGC110. The output of the CGC110may be coupled to the clock input of a circuit block (not shown).

In this example, the CGC110gates the clock signal clk_in when the enable signal en is low (logic zero). In this case, the CGC110outputs a logic zero to the circuit block regardless of the logic state of the input clock signal clk_in. The CGC110passes the clock signal clk_in to the circuit block when the enable signal en is high (logic one).

In operation, the latch120latches the logic value of the enable signal en on a falling edge of the clock signal clk_in, and outputs the latched logic value of the enable signal en to the first input of the AND gate130. If the latched logic value of the enable signal en is logic one, then the AND gate130passes the clock signal clk_in to the output of the CGC110. If the latched logic value of the enable signal en is logic zero, then the AND gate130outputs a logic zero regardless of the logic state of the input clock signal clk_in, effectively gating the clock signal.

A CGC has a setup time that specifies the minimum amount of time that an edge of the enable signal needs to arrive at the latch of the CGC before an edge of the input clock signal in order for the latch to properly latch the logic value of the enable signal. It is desirable for the CGC to have a low setup time. This is because a low setup time allows the edge of the enable signal to arrive at the latch of the CGC closer to the edge of the input clock signal without causing a setup time violation. This makes it easier to meet timing requirements in critical signal paths for higher clock frequencies.

In current CGC designs, when the enable signal changes from logic one to logic zero, an internal node of the latch needs to discharge to ground through a path that includes two gates in order for the latch to properly latch the logic value of zero of the enable signal. As a result, the setup time for these designs is at least two gate delays.

Embodiments of the present disclosure provide CGCs with low setup times, as discussed further below.

FIG. 2shows an exemplary CGC210according to certain aspects of the present disclosure. The CGC210includes a latch215, a transmission gate220, and a pull-down transistor260. The latch215has an enable input216that receives the enable signal en, and an output218. As discussed further below, the latch215is configured to latch the logic value of the enable signal en on a rising edge of the input clock signal clk_in, and output the latched logic value of the enable signal en at the output218of the latch215.

The transmission gate220is coupled between the output218of the latch215and the output265of the CGC210, which provides the output clock signal clk_out to a circuit block (not shown). The pull-down transistor260is coupled between the output265of the CGC210and ground.

In operation, when the input clock signal clk_in is low (logic zero), the transmission gate220is turned off (opened) and the pull-down transistor260is turned on. As a result, the pull-down transistor260pulls the output265of the CGC210to ground (i.e., pulls the output265low). Thus, when the input clock signal clk_in is low (logic zero), the output clock signal clk_out is also low (logic zero).

When the input clock signal clk_in is high (logic one), the transmission gate220is turned on (closed) and the pull-down transistor260is turned off. As a result, the transmission gate220passes the latched logic value of the enable signal en at the output218of the latch215to the output265of the CGC210. Thus, the logic value at the output265of the CGC210depends on the latched logic value of the enable signal en. If the latched logic value of the enable signal en is logic one, then the output265of the CGC210is logic one. If the latched logic value of the enable signal en is logic zero, then the output265of the CGC210is logic zero.

Thus, when the enable signal en is logic one, the output265of the CGC210is logic one when the input clock signal clk_in is logic one, and therefore tracks the input clock signal clk_in. As a result, the input clock signal clk_in is effectively passed to the output265of the CGC210in this case. When the enable signal en is logic zero, the output265of the CGC210stays at logic zero when the input clock signal clk_in is logic one, effectively gating the input clock signal clk_in. Accordingly, in this example, the input clock signal clk_in is gated when the enable signal is logic zero, and un-gated when the enable signal is logic one.

In the example inFIG. 2, the pull-down transistor260is implemented with an n-type metal-oxide-semiconductor (NMOS) transistor having a drain coupled to the output265of the CGC210, a source coupled to ground, and a gate that receives the inverse of the input clock signal (denoted “nclk_in). The inverted clock signal nclk_in is generated by inverting the input clock signal clk_in with an inverter212. When the input clock signal clk_in is logic zero, the inverted clock signal nclk_in is logic one. This causes the NMOS transistor to turn on, and provide a conduction path between the output265of the CGC210and ground, which pulls the output265to ground. When the input clock signal clk_in is logic one, the inverted clock signal nclk_in is logic zero. This causes the NMOS transistor to turn off.

In the example inFIG. 2, the transmission gate220is implemented with an NMOS transistor255and a p-type metal-oxide-semiconductor (PMOS) transistor250coupled in parallel between the output218of the latch215and the output265of the CGC210. The gate of the NMOS transistor255receives the input clock signal clk_in, and the gate of the PMOS transistor250receives the inverted clock signal nclk_in. As discussed above, the inverted clock signal nclk_in is generated by inverter212. When the input clock signal clk_in is logic zero (inverted clock signal nclk_in is logic one), both the NMOS transistor255and the PMOS transistor250are turned off. As a result, the output265of the CGC is decoupled from the output218of the latch215. When the input clock signal clk_in is logic one (inverted clock signal nclk_in is logic zero), both the NMOS transistor255and the PMOS transistor250are turned on. As a result, the transmission gate220passes the latched logic value of the enable signal at the output218of the latch215to the output265of the CGC210.

In the example inFIG. 2, the latch215includes PMOS transistors222,224,230and235, NMOS transistors226,228and245, an inverter240, and a NOR gate248.

PMOS transistors222and224are coupled in series between the supply rail Vcc and node pn1. The gate of PMOS transistor222is coupled to node pn2, and the gate of PMOS transistor224is coupled to the enable input216of the latch215. In the example shown inFIG. 2, the source of PMOS transistor222is coupled to the supply rail Vcc, the drain of PMOS transistor222is coupled to the source of PMOS transistor224, and the drain of PMOS transistor224is coupled to node pn1. However, it is to be appreciated that placement of PMOS transistors222and224may be reversed.

NMOS transistors226and228are coupled in series between node pn1and ground. The gate of NMOS transistor226is coupled to the enable input216of the latch215, and the gate of NMOS transistor228is coupled to the inverted clock signal nclk_in, which is generated by inverter212. In the example shown inFIG. 2, the drain of NMOS transistor226is coupled to the node pn1, the source of NMOS transistor226is coupled to the drain of NMOS transistor228, and the source of NMOS transistor228is coupled to ground. However, it is to be appreciated that placement of NMOS transistors226and228may be reversed.

PMOS transistors230and235are coupled in series between the supply rail Vcc and node pn1. The gate of PMOS transistor230is coupled to the inverted clock signal nclk_in. The inverter240is coupled between node pn1and the gate of PMOS transistor235. The inverter240is configured to invert the logic value of node pn1, and input the inverse of the logic value of node pn1to the gate of PMOS transistor235. In the example inFIG. 2, the source of PMOS transistor230is coupled to the supply rail Vcc, the drain of PMOS transistor230is coupled to the source of PMOS transistor235, and the drain of PMOS transistor235is coupled to node pn1.

NMOS transistor245is coupled between node pn1and ground. In the example inFIG. 2, the drain of NMOS transistor245is coupled to node pn1, the gate of NMOS transistor245is coupled to node pn2, and the source of NMOS transistor245is coupled to ground.

The NOR gate248has a first input coupled to the inverted clock signal nclk_in, a second input coupled to node pn1, and an output coupled to node pn2. As discussed further below, the NOR gate248functions as an inverter between nodes pn1and pn2when the inverted clock signal nclk_in is low (input clock signal clk_in is high).

Operation of the latch215will now be described according to certain aspects of the present disclosure.

When the input clock signal clk_in is low (logic zero), the inverted clock signal nclk_in is high (logic one). The logic one of the inverted clock signal nclk_in causes NMOS transistor228to turn on. The logic one of the inverted clock signal nclk_in also causes the NOR gate248to output a logic zero at node pn2regardless of the logic value at node pn1. As a result, node pn2is low (logic zero). The logic zero at node pn2causes PMOS transistor222to turn on.

Thus, when the input clock signal clk_in is low (inverted clock signal nclk_in is high), both NMOS transistor228and PMOS transistor222are turned on. PMOS transistor222couples the source of PMOS transistor224to the supply rail Vcc, and NMOS transistor228couples the source of NMOS transistor226to ground. As a result, PMOS transistor224and NMOS transistor226form an input inverter that inverts the enable signal en at the enable input216of the latch215and outputs the inverted enable signal at node pn1. Thus, when the clock signal clk_in is low, the logic value of node pn1is the inverse of the logic value of the enable signal en.

When the input clock signal clk_in switches from low (logic zero) to high (logic one) on a rising edge of the input clock signal clk_in, the inverted clock signal nclk_in switches from high (logic one) to low (logic zero). The logic zero of the inverted clock signal nclk_in (which is input to the first input of the NOR gate248) causes the NOR gate248to function as a first latch inverter that inverts the logic value of node pn1, and outputs the inverted logic value at node pn2. Thus, the logic value of node pn2is the inverse of the logic value of node pn1.

The logic zero of the inverted clock signal nclk also causes PMOS transistors222and235and NMOS transistor245to form a second latch inverter that inverts the logic value of node pn2, and outputs the inverted logic value at node pn1, as explained further below. Thus, the logic value of node pn1is the inverse of the logic value of node pn2.

Thus, when the input clock signal switch from low to high (inverted clock signal nclk_in switches from high to low), the NOR gate248forms a first latch inverter having an input coupled to node pn1and an output coupled to node pn2, and PMOS transistors222and235and NMOS transistor245form a second latch inverter having an input coupled to node pn2and an output coupled to node pn1. The first and second latch inverters are coupled in a closed loop, which causes the latch215to latch the inverted logic value of the enable signal at node pn1on a rising edge of the input clock signal clk_in.

In the example inFIG. 2, the output218of the latch215is taken at the output of inverter240, which inverts the latched inverted logic value of the enable signal at node pn1. Thus, the inverter240outputs the latched logic value of the enable signal at the output218of the latch215.

The input inverter formed by PMOS transistor224and NMOS transistor226when the input clock signal clk_in is low is disabled when the input clock signal clk_in is high. This is because NMOS transistor228is turned off when the input clock signal clk_in is high (inverted clock signal nclk_in is low), and therefore decouples the source of NMOS transistor226from ground when the input clock signal clk_in is high. This closes the enable input of the latch215, allowing the first and second latch inverters discussed above to latch the logic value of the enable signal. The input inverter is enabled when the input clock signal clk_in is low (inverted clock signal nclk_in is high) because NMOS transistor228is turned on in this case, and therefore couples the source of NMOS transistor226to ground.

The latch215shown inFIG. 2has a low setup time. This is because node pn1is only one device away from the enable input216of the latch215. More particularly, when the input clock signal clk_in is low, the enable signal en only needs to propagate through the input inverter formed by PMOS224and NMOS226to reach node pn1for latching on the rising edge of the input clock signal clk_in. The setup time of the latch215is lower than other designs in which an internal node of the latch needs to discharge to ground through a path that includes two gates in order to latch a logic value of zero.

As discussed above, PMOS transistors222and235and NMOS transistor245form the second latch inverter when the input clock signal clk_in is high (inverted clock signal nclk_in is low). An explanation of how the second latch inverter is formed will now be provided according to certain aspects of the present disclosure.

When the inverted clock signal nclk_in is low (logic zero), PMOS transistor230turns on and couples the source of PMOS transistor235to the supply rail Vcc. This causes PMOS transistor235and NMOS transistor245to form an inverter that inverts the logic value at node pn2and outputs the inverted logic value at node pn1. Note that the gate of PMOS transistor235is coupled to the output of the inverter240, which has the same logic value as node pn2. This is because the logic value at node pn2is the inverse of the logic value at node pn1, as discussed above.

PMOS transistor222and NMOS transistor245also form an inverter depending on whether the enable signal en is high or low. When the enable signal en is low, PMOS transistor224is turned on, thereby coupling the drain of PMOS transistor222to the drain of NMOS transistor245. In this case, PMOS transistor222and NMOS transistor245form an inverter that inverts the logic value at node pn2and outputs the inverted logic value at node pn1. When the enable signal en is high, PMOS transistor224is turned off. In this case, the drain of PMOS transistor222is decoupled from the drain of NMOS transistor244. In either case, PMOS transistor235and NMOS transistor245form an inverter that inverts the logic value at node pn2and outputs the inverted logic value at node pn1, as discussed above.

Thus, the second inverter latch includes the inverter formed by PMOS transistor235and NMOS transistor245and the inverter formed by PMOS transistor222and NMOS transistor245when the enable signal en is low (logic zero), and includes the inverter formed by PMOS transistor235and NMOS transistor245when the enable signal is high (logic zero).

FIG. 3shows another exemplary CGC310according to certain aspects of the present disclosure. The CGC310in this example includes the transmission gate220and the pull-down transistor260shown inFIG. 2. The CGC310also includes a latch315that is similar to the latch215inFIG. 2. The latch315in this example differs from the latch215inFIG. 2in that the latch315also includes an output inverter340coupled between node pn1and the output318of the latch315. The input of the output inverter340is coupled to node pn1, and the output of the output inverter340is coupled to the output318of the latch315, as shown inFIG. 3.

The output inverter340inverts the latched inverted logic value of the enable signal at node pn1. Thus, the output inverter340outputs the latched logic value of the enable signal at the output318of the latch215.

The output inverter340may have a high current drive capability for driving a large output load (e.g., a large load coupled to the output of the CGC). Thus, in this example, the output inverter340helps isolate node pn1of the latch from the output load, making the latch less sensitive to the output load.

FIG. 4shows another exemplary CGC410according to certain aspects of the present disclosure. The CGC410in this example includes the transmission gate220and latch215shown inFIG. 2. The CGC410differs from the CGC210inFIG. 2in that the output418of the latch215is taken at node pn1instead of the output of inverter240. Thus, in this example, the latch215outputs the latched inverted logic value of the enable signal at node pn1.

The CGC410also differs from the CGC210inFIG. 2in that the pull-down transistor260is replaced by a pull-up transistor430. In addition, the CGC410further includes an output inverter420having an input coupled to the transmission gate220and an output coupled to the output265of the CGC410.

The pull-up transistor430is coupled between the supply rail Vcc and a transmission node425of the CGC410(i.e., node between the transmission gate220and the input of the output inverter420). The pull-up transistor430is configured to pull the transmission node425to the supply rail Vcc (i.e., pull the transmission node425high) when the input clock signal is low (logic zero), as discussed further below.

In operation, when the input clock signal clk_in is low (logic zero), the transmission gate220is turned off (opened) and the pull-up transistor430is turned on. As a result, the pull-up transistor430pulls the transmission node425to the supply rail Vcc (i.e., pulls the transmission node425high). The output inverter420inverts the logic value of one at the transmission node425, and therefore outputs a logic value of zero at the output256of the CGC410. Thus, when the input clock signal clk_in is low (logic zero), the output clock signal clk_out at the output265of the CGC410is also low (logic zero).

When the input clock signal clk_in is high (logic one), the transmission gate220is turned on (closed) and the pull-up transistor430is turned off. As a result, the transmission gate220passes the latched inverted logic value of the enable signal en at node pn1to the input of the output inverter420. The output inverter420undoes the inversion of the enable signal, and therefore output the latched logic value of the enable signal at the output265of the CGC410. Thus, the logic value at the output265of the CGC410is the latched logic value of the enable signal en. If the latched logic value of the enable signal en is logic one, then the output265of the CGC410is logic one. If the latched logic value of the enable signal en is logic zero, then the output265of the CGC410is logic zero.

Thus, when the enable signal en is logic one, the output265of the CGC410is logic one when the input clock signal clk_in is logic one, and therefore tracks the input clock signal clk_in. As a result, the input clock clk_in is effectively passed to the output265of the CGC410in this case. When the enable signal en is zero, the output265of the CGC410stays at logic zero when the input clock signal clk_in is logic one, effectively gating the input clock signal clk_in. Accordingly, in this example, the input clock signal clk_in is gated when the enable signal is logic zero, and un-gated when the enable signal is logic one.

In the example inFIG. 4, the pull-up transistor430is implemented with a PMOS transistor having a source coupled to the supply rail Vcc, a drain coupled to the transmission node425, and a gate that receives the input clock signal clk_in. When the input clock signal clk_in is low (logic zero), the PMOS transistor is turned on. In this case, the PMOS transistor provides a conduction path between the transmission node425and the supply rail Vcc, which pulls the transmission node425to the supply rail Vcc. When the input clock signal clk_in is high (logic one), the PMOS transistor is turned off.

In this example, the output inverter420may have a high current drive capability for driving a large output load (e.g., a large load coupled to the output of the CGC). This helps isolate node pn1of the latch from the output load, making the latch less sensitive to the output load.

FIG. 5shows an exemplary implementation of the NOR gate248according to certain aspects of the present disclosure. In this example, the NOR gate248includes PMOS transistors510and520and NMOS transistors530and540.

PMOS transistors510and520are coupled in series between the supply rail Vcc and node pn2. The gate of PMOS transistor510is coupled to the inverted clock signal nclk_in, and the gate of PMOS transistor520is coupled to the node pn1. In the example shown inFIG. 5, the source of PMOS transistor510is coupled to the supply rail Vcc, the drain of PMOS transistor510is coupled to the source of PMOS transistor520, and the drain of PMOS transistor520is coupled to node pn2. However, it is to be appreciated that placement of PMOS transistors510and520may be reversed.

NMOS transistors530and540are coupled in parallel between node pn2and ground. The gate of NMOS transistor530is coupled to the inverted clock signal clk_in, and the gate of NMOS transistor540is coupled to node pn1. The drain of each of the NMOS transistors530and540is coupled to node pn2, and the source of each of the NMOS transistors530and540is coupled to ground.

In operation, when the inverted clock signal nclk_in is high (logic one), NMOS transistor530is turned on and PMOS transistor510is turned off. As a result, NMOS transistor530pulls node pn2to ground (i.e., pulls node pn2low). In this case, node pn2is low (logic zero) regardless of the logic value of node pn1.

When the inverted clock signal nclk_in is low (logic zero), NMOS transistor530is turned off and PMOS transistor510is turned on. As a result, PMOS transistor510couples the source of PMOS transistor520to the supply rail Vcc. In this case, PMOS transistor510and NMOS transistor540form an inverter that inverts the logic value of node pn1, and outputs the inverted logic value at node pn2.

FIG. 6shows an exemplary system610including a CGC620, a clock gate controller630, a clock source640, and a circuit block650. The CGC620may be implemented using any of the exemplary CGCs210,310and410discussed above.

In this example, the CGC620receives the input clock signal clk_in from the clock source640via a clock path (e.g., clock path in a clock distribution network). The clock source640may include a phase locked loop (PLL) or another type of clock source. The CGC620receives the enable signal en from the clock gate controller630. The clock gate controller630controls gating of the input clock signal clk_in by controlling the logic value of the enable signal en, as discussed further below. The output of the CGC620is coupled to the clock input of the circuit block650. The circuit block650uses the output clock signal clk_out from the CGC620for timing operations of the circuit block650. The circuit block650may include a processor, a sequential logic circuit, a pipeline, and/or one or more flip-flops, etc.

In operation, the clock gate controller630may monitor an activity state of the circuit block650, and determine whether to gate the clock signal clk_in based on the monitored state. For example, if the circuit block650is in an inactive state (e.g., not processing data, not receiving data, etc.), then the clock gate controller630may gate the clock signal clk_in by asserting the enable signal en to the CGC620low (logic zero). The inactive state may also be referred to as an idle state. If the circuit block650is in an active state (e.g., processing data, receiving data, etc.), then the clock gate controller630may un-gate the clock signal clk_in by asserting the enable signal en to the CGC620high (logic one).

FIG. 7shows an example in which the circuit block650inFIG. 6includes one or more flip flops710. For simplicity, only one flip flop is shown inFIG. 7. In this example, the flop-flop710has a clock input that receives the clock signal clk_out from the CGC620, a data input D that receives an input data signal (denoted “data_in), and an output Q. In operation, the flip flop710latches (captures) a logic value of the input data signal on an active edge of the clock signal clk_out, and outputs the latched logic value at the output Q. The active edge may be a rising edge or a falling edge depending on whether the flip flop is positive-edge triggered or negative-edge triggered. More particularly, if the flip flop710is a positive-edge triggered flip flop, then the flip flop710latches the logic value of the data signal on a rising edge of the clock signal clk_out. If the flip flop710is a negative-edge edge triggered flip flop, then the flip flop710latches the logic value of the data signal on a falling edge of the clock signal clk_out.

In this example, the clock gate controller630may monitor the input D and/or output Q of the flip flop710to determine whether to gate the clock signal clk_in. For example, if the logic values at the input D and output Q of the flip flop710are the same over one or more clock cycles (e.g., of the input clock signal clk_in), then the clock gate controller630may determine to gate the clock signal to the flip flop710to conserve power. This may occur when the flip flop710is not receiving new data that needs to be latched. In this case, clock gate controller630may gate the clock signal clk_in by asserting the enable signal en to the CGC620low (logic zero). If the logic values at the input D and output Q of the flip flop710are different, then the clock gate controller630may determine to un-gate the clock signal. In this case, the gate clock gate controller630may un-gate the clock signal clk_in by asserting the enable signal en to the CGC620high (logic one).

The flip flop710may be used, for example, to latch data in a sequential logic circuit, a pipeline, a processor, a shift register, etc. The flip flop710may also be used to synchronize a data signal with the clock signal clk_out by latching logic values of the data signal on rising or falling edges of the clock signal clk_out.

FIG. 8is a flowchart illustrating a method800for clock gating according to certain aspects. The method800may be performed by CGC210or310.

At step810, an enable signal is received. For example, the enable signal may be received from a clock gate controller (e.g., clock gate controller630).

At step820, a logic value of the enable signal is latched on an edge of an input clock signal. For example, the logic value may be latched on a rising edge of the input clock signal (e.g., input clock signal clk_in).

At step830, the latched logic value of the enable signal is passed to a clock-gating output when the input clock signal is logically high. For example, the latched logic value may be passed to the clock-gating output (e.g., output265) by turning on a transmission gate (e.g., transmission gate220).

At step840, the latched logic value of the enable signal is blocked from the clock-gating output when the input clock signal is logically low. For example, the latched logic value may be blocked by turning off the transmission gate.

At step850, the clock-gating output is pulled logically low when the input clock signal is logically low. For example, the output may be pulled low (e.g., to ground) by turning on a pull-down transistor (e.g., pull-down transistor260).

FIG. 9is a flowchart illustrating a method900for clock gating according to certain aspects. The method900may be performed by CGC410.

At step910, an enable signal is received. For example, the enable signal may be received from a clock gate controller (e.g., clock gate controller630).

At step920, an inverted logic value of the enable signal is latched on an edge of an input clock signal. For example, the inverted logic value may be latched on a rising edge of the input clock signal (e.g., input clock signal clk_in).

At step930, the latched inverted logic value of the enable signal is passed to a transmission node when the input clock signal is logically high. For example, the latched inverted logic value may be passed to the transmission node (e.g., transmission node425) by turning on a transmission gate (e.g., transmission gate220).

At step940, the latched inverted logic value of the enable signal is blocked from the transmission node when the input clock signal is logically low. For example, the latched inverted logic value may be blocked by turning off the transmission gate.

At step950, the transmission node is pulled logically high when the input clock signal is logically low. For example, the transmission node may be pulled high (e.g., to supply rail Vcc) by turning on a pull-up transistor (e.g., pull-up transistor430).

At step960, the latched inverted logic value of the enable signal is inverted. For example, the latched inverted logic value may be inverted using an inverter (e.g., output inverter420). The resulting inverted latched inverted logic value may be output to the clock input of a circuit block (e.g., circuit block650).

It is to be appreciated that the present disclosure is not limited to the exemplary terminology used above. For example, a transmission gate may also be referred to as a switch, a pass gate, or another term. Also, a CGC may be referred to as a clock gating circuit or another term.

In the present disclosure, the term “logically low” corresponds to a logic value of zero, and the term “logically high” corresponds to a logic value of one. A logic value of zero may correspond to a voltage approximately equal to ground, and a logic value of one may correspond to a voltage approximately equal to the supply voltage of the supply rail Vcc.

The clock gate controller630discussed above may be implemented with a general-purpose processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, discrete hardware components (e.g., logic gates), or any combination thereof designed to perform the functions described herein. A processor may perform the functions described herein by executing software comprising code for performing the functions. The software may be stored on a computer-readable storage medium, such as a RAM, a ROM, an EEPROM, an optical disk, and/or a magnetic disk.