Semiconductor packages including thermal blocks

A semiconductor package includes a package substrate including a first region, a thermal block penetrating the first region and exposed at top and bottom surfaces of the package substrate, a semiconductor chip on the package substrate, bumps disposed between the package substrate and the semiconductor chip and including first bumps being in contact with the thermal block, and terminals disposed on the bottom surface of the package substrate and including first terminals being in contact with the thermal block. The thermal block is one of a power path and a ground path.

CROSS-REFERENCE TO RELATED APPLICATION

This U.S. non-provisional patent application claims priority under 35 U.S.C. §119 to Korean Patent Application No. 10-2014-0157411, filed on Nov. 12, 2014, in the Korean Intellectual Property Office, the disclosure of which is hereby incorporated by reference in its entirety.

BACKGROUND

The inventive concepts relate to semiconductor packages. More particularly, the inventive concepts relate to semiconductor packages with improved electrical characteristics.

As performance of electronic products has been improved, heat energy generated from devices included in the electronic products has been increased. To solve this generation problem, performance of the device may be limited to adjust a temperature of the device when the temperature of the device is equal to or higher than a desired, or alternatively predetermined temperature. However, the performance of the device may be often limited by the generated heat energy, so the efficiency of the device may be reduced.

SUMMARY

Embodiments of the inventive concepts may provide semiconductor packages capable of improving electrical characteristics.

In one example embodiment, a semiconductor package may include a package substrate including a first region, a thermal block penetrating the first region of the package substrate, the thermal block exposed at a top surface and a bottom surface of the package substrate, a semiconductor chip disposed on the package substrate, bumps disposed between the package substrate and the semiconductor chip, the bumps including first bumps being in contact with the thermal block, and terminals disposed on the bottom surface of the package substrate and including first terminals being in contact with the thermal block. The thermal block may be one of a power path and a ground path.

In an embodiment, the package substrate may further include a second region spaced apart from the first region, and the semiconductor package may further include a second thermal block penetrating the second region of the package substrate.

In an embodiment, the bumps may further include second bumps, and the terminals may further include second terminals. The second bumps and the second terminals may be in contact with the second thermal block.

In an embodiment, the second thermal block may be the other of the power path and the ground path.

In an embodiment, the first bumps may include first edge bumps vertically overlapping with an outermost region of the first region, and the bumps may further include third bumps surrounding the first edge bumps in a plan view. The second bumps may include second edge bumps vertically overlapping with an outermost region of the second region, and the bumps may further include fourth bumps surrounding the second edge bumps in a plan view.

In an embodiment, the package substrate may include first interconnecting parts electrically connecting the third bumps to some of the terminals, and second interconnecting parts electrically connecting the fourth bumps to others of the terminals. Each of the thermal block and the second interconnecting part may be one of the power path and the ground path, and each of the second thermal block and the first interconnecting part may be the other of the power path and the ground path.

In an embodiment, the first terminals may include first edge terminals vertically overlapping with the outermost region of the first region, and the terminals may include third terminals surrounding the first edge terminals in a plan view. The second terminals may include second edge terminals vertically overlapping with the outermost region of the second region, and the terminals may include fourth terminals surrounding the second edge terminals in a plan view. The third terminals may be the terminals connected to the first interconnecting parts, and the fourth terminals may be the terminals connected to the second interconnecting parts.

In an embodiment, the package substrate comprises first interconnecting parts electrically connecting the third bumps to some of the terminals, and second interconnecting parts electrically connecting the fourth bumps to others of the terminals. The second thermal block may be one of the power path and the ground path, and each of the first and second interconnecting parts may be the other of the power path and the ground path.

In an embodiment, the first terminals may include first edge terminals vertically overlapping with the outermost region of the first region, and the second terminals may include second edge terminals vertically overlapping with the outermost region of the second region. The terminals may include third terminals surrounding the first edge terminals and the second edge terminals in a plan view. The third terminals may be the terminals connected to the first and second interconnecting parts.

In an embodiment, the first bumps may include first edge bumps vertically overlapping with an outermost region of the first region, and the bumps may further include second bumps surrounding the first edge bumps in a plan view. The second bumps may be connected to the other of the power path and the ground path.

In another example embodiment, a semiconductor package may include a package substrate including a first region and a second region; a first thermal block penetrating the first region of the package substrate, the first thermal block exposed at a top surface and a bottom surface of the package substrate, a second thermal block penetrating the second region of the package substrate, the second thermal block exposed at the top surface and the bottom surface of the package substrate, a semiconductor chip disposed on the package substrate, and bumps disposed between the package substrate and the semiconductor chip. The bumps may include first bumps in contact with the first thermal block and second bumps in contact with the second thermal block. A voltage difference may occur between the first bumps and the second bumps when the semiconductor package is operated.

In example embodiments, a semiconductor package includes a package substrate including at least one thermal block, a semiconductor chip on the package substrate, a plurality of bumps at a first surface of the package substrate between the package substrate and the semiconductor chip, and a plurality of terminals at a second surface of the package substrate, at least one of the plurality of bumps being in electrical contact with at least one of the plurality of terminals.

DETAILED DESCRIPTION

The inventive concepts will now be described more fully hereinafter with reference to the accompanying drawings, in which example embodiments of the inventive concepts are shown. The advantages and features of the inventive concepts and methods of achieving them will be apparent from the following example embodiments that will be described in more detail with reference to the accompanying drawings. It should be noted, however, that the inventive concepts are not limited to the following example embodiments, and may be implemented in various forms. Accordingly, the example embodiments are provided only to disclose the inventive concepts and let those skilled in the art know the category of the inventive concepts. In the drawings, embodiments of the inventive concepts are not limited to the specific examples provided herein and are exaggerated for clarity.

Similarly, it will be understood that when an element such as a layer, region or substrate is referred to as being “on,” “connected” or “coupled” to another element, it can be directly on, connected or coupled to the other element or intervening elements may be present. In contrast, the term “directly” means that there are no intervening elements. As used herein the term “and/or” includes any and all combinations of one or more of the associated listed items. Further, it will be understood that when a layer is referred to as being “under” another layer, it can be directly under or one or more intervening layers may also be present. In addition, it will also be understood that when a layer is referred to as being “between” two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present. It will be further understood that the terms “comprises”, “comprising,”, “includes” and/or “including”, when used herein, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

Additionally, the embodiment in the detailed description will be described with sectional views as ideal example views of the inventive concepts. Accordingly, shapes of the example views may be modified according to manufacturing techniques and/or allowable errors. Therefore, the embodiments of the inventive concepts are not limited to the specific shape illustrated in the example views, but may include other shapes that may be created according to manufacturing processes. Areas exemplified in the drawings have general properties, and are used to illustrate specific shapes of elements. Thus, this should not be construed as limited to the scope of the inventive concepts. In the drawing figures, the dimensions of layers and regions may be exaggerated for clarity of illustration Like reference numerals refer to like elements throughout. The same reference numbers indicate the same components throughout the specification.

Accordingly, the cross-sectional view(s) illustrated herein provide support for a plurality of devices according to various example embodiments described herein that extend along two different directions in a plan view and/or in three different directions in a perspective view. For example, when a single active region is illustrated in a cross-sectional view of a device/structure, the device/structure may include a plurality of active regions and transistor structures (or memory cell structures, gate structures, etc., as appropriate to the case) thereon, as would be illustrated by a plan view of the device/structure.

FIGS. 1A and 1Bare plan views illustrating a semiconductor package according to some example embodiments of the inventive concepts.FIG. 2is a cross-sectional view taken along a line I-I′ ofFIGS. 1A and 1Bto illustrate a semiconductor package according to a first example embodiment of the inventive concepts.

Referring toFIGS. 1A, 1B, and 2, a semiconductor chip200may be disposed on a package substrate100. The package substrate100may be a printed circuit board, a flexible substrate, or a tape substrate. In some example embodiments, the package substrate100may be formed of or include copper-clad laminates, so the package substrate100may include a plurality of metal layers (not shown). The metal layers may include metal patterns (not shown). An insulating layer102may be disposed between the metal layers. The package substrate100may include a top surface101aand a bottom surface101b.

A first thermal block104and a second thermal block106may be disposed in the package substrate100. The first thermal block104and the second thermal block106may be spaced apart from each other and may penetrate the package substrate100. The first thermal block104and the second thermal block106may be respectively disposed in a first region110and a second region112of the package substrate100that vertically overlap with a hot spot area210of the semiconductor chip200. A top surface of the first thermal block104may be exposed at the top surface101aof the package substrate100, and a bottom surface of the first thermal block104may be exposed at the bottom surface101bof the package substrate100. For example, the top surface of the first thermal block104may be disposed at the substantially same level as the top surface101aof the package substrate100, and the bottom surface of the first thermal block104may be disposed at the substantially same level as the bottom surface101bof the package substrate100. In other words, the top surface of the first thermal block104may be substantially coplanar with the top surface101aof the package substrate100, and the bottom surface of the first thermal block104may be substantially coplanar with the bottom surface101bof the package substrate100. A top surface of the second thermal block106may be exposed at the top surface101aof the package substrate100, and a bottom surface of the second thermal block106may be exposed at the bottom surface101bof the package substrate100. For example, the top surface of the second thermal block106may be disposed at the substantially same level as the top surface101aof the package substrate100, and the bottom surface of the second thermal block106may be disposed at the substantially same level as the bottom surface101bof the package substrate100. In other words, the top surface of the second thermal block106may be substantially coplanar with the top surface101aof the package substrate100, and the bottom surface of the second thermal block106may be substantially coplanar with the bottom surface101bof the package substrate100. A barrier layer108may be disposed between the package substrate100and each of the first and second thermal blocks104and106. The barrier layer108may electrically insulate each of the first and second thermal blocks104and106from the metal layers included in the package substrate100. The first and second thermal blocks104and106may include, for example, at least one of copper, tungsten, or aluminum. The barrier layer108may include, for example, at least one of a silicon oxide layer, a silicon nitride layer, or a silicon oxynitride layer.

The semiconductor chip200may be mounted on the top surface101aof the package substrate100by a flip chip bonding technique. Terminals or bumps120may be disposed between the semiconductor chip200and the top surface101aof the package substrate100. A plurality of redistribution lines (not shown) may be disposed on a bottom surface of the semiconductor chip200. The redistribution lines may be in contact with the bumps120, respectively. The semiconductor chip200may be, for example, a logic chip. The logic chips may include elements (e.g., a transistor) and a plurality of circuit areas. At least one of the circuit areas may correspond to the hot spot area210. The hot spot area210of the semiconductor chip200may be an area that includes, for example, at least one of a central processing unit (CPU), a graphic processing unit (GPU), a memory interface unit, or a universal serial bus (USB).

The terminals or bumps120may be arranged in a first direction and a second direction perpendicular to the first direction when viewed from a plan view. The bumps120may include first bumps122, second bumps124, and third bumps126. The first bumps122and the second bumps124may overlap with the hot spot area210of the semiconductor chip200when viewed from a plan view. In more detail, the first bumps122may be in electrical contact with the first thermal block104, and the second bumps124may be in electrical contact with the second thermal block106. The third bumps126may be in electrical contact with chip pads114that are disposed on the top surface101aof the package substrate100. The third bumps126may not be disposed between the first bumps122and the second bumps124nearest to the first bumps122. Each of the first bumps122may be one of a power terminal or bump and a ground terminal or bump, and each of the second bumps124may be the other of the terminal or power bump and the terminal or ground bump. A voltage difference may occur between the first bump122and the second bump124when the semiconductor package is operated. For example, if the first terminal or bump122is the power terminal or bump, the second terminal or bump124may be the ground terminal or bump. The third terminals or bumps126may be signal terminals or bumps.

Terminals130may be disposed on the bottom surface101bof the package substrate100. The terminals130may be arranged in the first direction and the second direction when viewed from a plan view. The terminals130may include first terminals132, second terminals134, and third terminals136. The first terminals132may be in electrical contact with the first thermal block104, so the first bumps122may be electrically connected to the first terminals132through the first thermal block104. The second terminals134may be in electrical contact with the second thermal block106, so the second bumps124may be electrically connected to the second terminals134through the second thermal block106. The third terminals136may be in electrical contact with terminal pads116that are disposed on the bottom surface101bof the package substrate100. The third bumps126may be electrically connected to the third terminals136through signal interconnection parts118.

The third terminals136may not be disposed between the first terminals132and the second terminals134nearest to the first terminals132. Each of the first terminals132may be one of a power terminal and a ground terminal, and each of the second terminals134may be the other of the power terminal and the ground terminal. A voltage difference may occur between the first terminals132and the second terminals134when the semiconductor package is operated. For example, if the first terminal132is the power terminal, the second terminal134may be the ground terminal. The third terminals136may be signal terminals.

If the first bump122and the first terminal132are the power bump and the power terminal, respectively, the first thermal block104may be a power path. If the second bump124and the second terminal134are the ground bump and the ground terminal, respectively, the second thermal block106may be a ground path. The signal interconnection part118may correspond to a signal transmission path.

The first and second thermal blocks104and106may have a function that exhausts heat generated from the semiconductor chip200to the outside of the semiconductor package. The first and second thermal blocks104and106may be insulated from the package substrate100by the barrier layer108and may be connected to the bumps120and the terminals130. Thus, each of the first and second thermal blocks104and106may perform the heat-exhausting function and may be used as one of a power connection portion and a ground connection portion. For example, if the first thermal block104is used as the power path, the first bumps122and the first terminals132which are in contact with the first thermal block104may be used as the power bumps and the power terminals, respectively. If the second thermal block106is used as the ground path, the second bumps124and the second terminals134which are in contact with the second thermal block106may be used as the ground bumps and the ground terminals, respectively. In other words, the first and second thermal blocks104and106may be used as heat-exhausting paths, and the bumps and terminals being in contact with the first and second thermal blocks104and106may be used as the power and ground bumps and the power and ground terminals, so that an area of the package substrate100may be effectively and optimally used. In addition, since the first and second thermal blocks104and106are adjacent to each other, a distance between the power and the ground may be short. As a result, power characteristics of the semiconductor package may be improved. For example, a Loop-L value between the power and the ground may be reduced to improve characteristics of a power voltage and a ground voltage.

FIG. 3is a cross-sectional view taken along a line I-I′ ofFIGS. 1A and 1Bto illustrate a semiconductor package according to an example embodiment of the inventive concepts. In the present example embodiment, the same elements as described in the first example embodiment will be indicated by the same reference numerals or the same reference designators. For the purpose of ease and convenience in explanation, the descriptions to the same elements as in the first example embodiment will be omitted or mentioned briefly.

Referring toFIG. 3, bumps120may further include a fourth bump128and terminals130may further include a fourth terminal138. The fourth bump128and the fourth terminal138may be connected to a capacitor140. In more detail, the capacitor140may be embedded in the package substrate100. The capacitor140may include two electrodes and a dielectric layer disposed between the two electrodes. One of the two electrodes may be a chip pad114which is in contact with the fourth bump128, and the other of the two electrodes may be electrically connected to the fourth terminal138through an interconnection142.

Since the first and second thermal blocks104and106are disposed in the package substrate100, a distance L1between the hot spot area210and the thermal blocks104and106may be smaller than a distance L2between the hot spot area210and the capacitor140.

The capacitor140may be mounted in the package substrate100to improve power integrity (PI) of the semiconductor package. The first and second thermal blocks104and106may be disposed in a portion, adjacent to the semiconductor chip200, of the package substrate100, so the capacitor140may be far away from the circuit area of the semiconductor chip200. Thus, the power integrity of the semiconductor package may be deteriorated. However, according to example embodiments of the inventive concepts, the first bumps122and the first terminals132connected to the first thermal block104may be used as the power bumps and the power terminals, and the second bumps124and the second terminals134connected to the second thermal block106may be used as the ground bumps and the ground terminals. In other words, the distance between the power and the ground may be reduced to improve the power characteristics of the power and the ground, as described above. As a result, the power integrity of the semiconductor package may not be deteriorated even though the distance between the capacitor140and the semiconductor chip200increases.

FIG. 4is a cross-sectional view taken along a line I-I′ ofFIGS. 1A and 1Bto illustrate a semiconductor package according to an example embodiment of the inventive concepts. In the example embodiment, the same elements as described in the example embodiment ofFIGS. 1A and 1Bwill be indicated by the same reference numerals or the same reference designators. For the purpose of ease and convenience in explanation, the descriptions to the same elements as in the first example embodiment will be omitted or mentioned briefly.

Referring toFIG. 4, an upper package2000may be stacked on a lower package1000. The lower package1000may include a lower package substrate100, a lower semiconductor chip200disposed on the lower package substrate100, and a lower molding layer250.

The lower package substrate100may be formed of or include copper-clad laminates, so it may include a plurality of metal layers (not shown). The metal layers may consist of or include metal patterns (not shown). A lower insulating layer102may be disposed between the metal layers. The lower package substrate100may include a top surface101aand a bottom surface101b.

A first thermal block104and a second thermal block106may be disposed in the lower package substrate100. The first thermal block104and the second thermal block106may be spaced apart from each other and penetrate the lower package substrate100. The first thermal block104and the second thermal block106may be respectively disposed in first and second regions110and112of the lower package substrate100that are adjacent to a hot spot area210of the lower semiconductor chip200. A lower barrier layer108may be disposed between the lower package substrate100and each of the first and second thermal blocks104and106.

The lower semiconductor chip200may be mounted on the top surface101aof the lower package substrate100. In more detail, the lower semiconductor chip200may be mounted on the lower package substrate100by a flip chip bonding technique with bumps120interposed therebetween. The bumps120may include first bumps122, second bumps124, and third bumps126. The first bumps122may be in electrical contact with the first thermal block104, and the second bumps124may be in electrical contact with the second thermal block106. The third bumps126may be in electrical contact with chip pads114that are disposed on the top surface101aof the lower package substrate100. Each of the first bumps122may be one of a power terminal or bump and a ground terminal or bump, and each of the second bumps124may be the other of the power terminal or bump and the ground terminal or bump. A voltage difference may occur between the first bump122and the second bump124when the lower package1000is operated. For example, if the first bumps122are the power terminals or bumps, the second bumps124may be the ground terminals or bumps. The third bumps126may be signal terminals or bumps.

Terminals130may be disposed on the bottom surface101bof the lower package substrate100. The terminals130may include first terminals132, second terminals134, and third terminals136. The first terminals132may be in electrical contact with the first thermal block104, so the first bumps122may be electrically connected to the first terminals132through the first thermal block104. The second terminals134may be in electrical contact with the second thermal block106, so the second bumps124may be electrically connected to the second terminals134through the second thermal block106. Each of the first terminals132may be one of a power terminal and a ground terminal, and each of the second terminals134may be the other of the power terminal and the ground terminal. A voltage difference may occur between the first terminals132and the second terminals134when the lower package1000is operated. For example, if the first terminals132are the power terminal, the second terminals134may be the ground terminals. The third bumps126may be electrically connected to the third terminals136through signal interconnection parts118. The third terminals136may be signal terminals.

The lower molding layer250may be disposed on the lower package substrate100to cover the lower semiconductor chip200and the bumps120. The lower molding layer250may expose a top surface of the lower semiconductor chip200.

The upper package2000may include an upper package substrate300, an upper semiconductor chip400disposed on the upper package substrate300, and an upper molding layer450. The upper package substrate300may be, for example, a printed circuit board, a flexible substrate, or a tape substrate. In an example embodiment, the upper package substrate300may be formed of or include copper-clad laminates, so the upper package substrate300may include a plurality of metal layers. The metal layers may consist of or include interconnections (not shown). An upper insulating layer302may be disposed between the interconnections.

A third thermal block304may be disposed in the upper package substrate300. The third thermal block304may penetrate the upper package substrate300. A top surface and a bottom surface of the third thermal block304may be exposed at a top surface and a bottom surface of the upper package substrate300, respectively. The third thermal block304may be disposed in a third region310of the upper package substrate300that vertically overlaps with the hot spot area210of the lower semiconductor chip200. An upper barrier layer308may be disposed between the third thermal block304and the upper package substrate300. The third region310of the upper package substrate300may face the first and second regions110and112of the lower package substrate100. In other words, the third region310of the upper package substrate300may vertically overlap with the first and second regions110and112of the lower package substrate100. Alternatively, even though not shown in the drawings, the third region310of the upper package substrate300may not face the first and second regions110and112of the lower package substrate100.

The upper semiconductor chip400may be disposed on the upper package substrate300. The upper semiconductor chip400may be mounted on the top surface of the upper package substrate300with an adhesive layer402interposed therebetween. The upper semiconductor chip400may be, for example, a memory chip. Chip pads404may be disposed on a top surface of the upper semiconductor chip400, and bonding pads408may be disposed on the top surface of the upper package substrate300. The chip pads404may be electrically connected to the bonding pads408through bonding wires406.

The upper molding layer450covering the upper semiconductor chip400may be disposed on the upper package substrate300. Heat generated from the lower semiconductor chip200may be exhausted through the third thermal block304as well as the first and second thermal blocks104and106.

Package interconnection parts420may be disposed between the lower package1000and the upper package2000. The package interconnection parts420may be in contact with some of the chip pads114of the lower package substrate100and chip pads314of the upper package substrate300to electrically connect the lower package1000to the upper package2000.

A heat transmission layer121may be disposed between the lower package1000and the upper package2000. The heat transmission layer121may include a thermal interface material (TIM). Heat diffused toward the upper package2000may be effectively transmitted to the third thermal block304through the heat transmission layer121.

FIGS. 5A and 5Bare plan views illustrating a semiconductor package according to an example embodiment of the inventive concepts.FIG. 6Ais a cross-sectional view taken along a line II-II′ ofFIGS. 5A and 5Bto illustrate the semiconductor package according to an example embodiment of the inventive concepts.FIG. 6Bis a cross-sectional view taken along a line III-III′ ofFIGS. 5A and 5Bto illustrate the semiconductor package according to an example embodiment of the inventive concepts.

In an example embodiment illustrated inFIGS. 5A, 5B, 6A, and 6B, the same elements as described in the first example embodiment will be indicated by the same reference numerals or the same reference designators. For the purpose of ease and convenience in explanation, the descriptions to the same elements as in the first example embodiment will be omitted or mentioned briefly.

Referring toFIGS. 5A, 5B, 6A, and 6B, a package substrate100may include a first thermal block104, a second thermal block106, a third thermal block105, and a fourth thermal block107. The first thermal block104and the third thermal block105may be disposed in the first region110of the package substrate100, and the second thermal block106and the fourth thermal block107may be disposed in the second region112of the package substrate100. The first thermal block104and the third thermal block105may be electrically insulated from each other by a barrier layer108disposed between the first and third thermal blocks104and105. The second thermal block106and the fourth thermal block107may be electrically insulated from each other by a barrier layer108disposed between the second and fourth thermal blocks106and107.

The first thermal block104may be in contact with first bumps122and first terminals132. The second thermal block106may be in contact with second bumps124and the second terminals134. The third thermal block105may be in contact with fourth bumps128and fourth terminals138. The fourth thermal block107may be in contact with fifth bumps129and fifth terminals139.

The first bumps122, the fourth bumps128, the first terminals132, and the fourth terminals138may be provided with the same voltage. The second bumps124, the fifth bumps129, the second terminals134, and the fifth terminals139may be provided with the same voltage. Here, a difference may occur between the voltage supplied to the first and fourth bumps122and128and the voltage supplied to the second and fifth bumps124and129Likewise, a difference may occur between the voltage supplied to the first and fourth terminals132and138and the voltage supplied to second and fifth terminals134and139. Each of the first and fourth bumps122and128may be one of a power bump and a ground bump, and each of the second and fifth bumps124and129may be the other of the power bump and the ground bump. Each of the first and fourth terminals132and138may be one of a power terminal and a ground terminal, and each of the second and fifth terminals134and139may be the other of the power terminal and the ground terminal.

For example, if the first bumps122and the first terminals132are the power bumps and the power terminals, respectively, the first thermal block104may be a power path. If the fourth bumps128and the fourth terminals138are the power bumps and the power terminals, respectively, the third thermal block105may be the power path. If the second bumps124and the second terminals134are the ground bumps and the ground terminals, respectively, the second thermal block106may be a ground path. If the fifth bumps129and the fifth terminals139are the ground bumps and the ground terminals, respectively, the fourth thermal block107may be the ground path.

The thermal block may be a lump of metal, so an area of the thermal block may be greater than areas of interconnections and/or through-vias. The maximum temperature of the hot spot area210of the semiconductor chip200may be higher than the maximum temperatures of other areas of the semiconductor chip200. Thus, a temperature difference between the maximum and minimum temperatures of the hot spot area210may be greater than a difference between the maximum and minimum temperatures of the other areas of the semiconductor chip200. The thermal block adjacent to the hot spot area210may repeatedly shrink and expand because of the temperature difference. In addition, degrees of the shrinkage and expansion of the thermal block may increase as the area of the thermal block increases. Thus, cracks may occur in the thermal block.

In the present example embodiment, at least two thermal blocks may be formed in one region of the package substrate100to reduce or substantially prevent the above discussed disadvantage. For example, the first and third thermal blocks104and105may be formed in the first region110of the package substrate100. The thermal blocks disposed in the one region may be in contact with the bumps and terminals which are supplied with the same voltage. Thus, the thermal blocks in the one region may be used as the power paths or the ground paths and may transmit the same voltage. Since the number of the thermal blocks is increased and the area of each of the thermal blocks is reduced in the one region, power characteristics of the power and the voltage may be maintained and the generation of cracks may be reduced or substantially prevented in the thermal blocks.

FIGS. 7A and 7Bare plan views illustrating a semiconductor package according to an example embodiment of the inventive concepts.FIGS. 8 and 9are cross-sectional views taken along a line I-I′ ofFIGS. 7A and 7Bto illustrate semiconductor packages according to an example embodiment of the inventive concepts. In the example embodiment ofFIGS. 7A, 7B, 8, and 9, the same elements as de example scribed in the example embodiment ofFIGS. 1A and 1Bwill be indicated by the same reference numerals or the same reference designators. For the purpose of ease and convenience in explanation, the descriptions to the same elements as in the first example embodiment will be omitted or mentioned briefly.

Referring toFIGS. 7A, 7B, 8, and 9, the semiconductor chip200may be disposed on the package substrate100. A thermal block103may be disposed in the package substrate100. The thermal block103may penetrate the package substrate100. The thermal block103may be disposed in a first region110of the package substrate100which vertically overlaps with a hot spot area210of the semiconductor chip200. A top surface of the thermal block103may be exposed at the top surface101aof the package substrate100, and a bottom surface of the thermal block103may be exposed at the bottom surface101bof the package substrate100. For example, the top surface of the thermal block103may be disposed at the same level as the top surface101aof the package substrate100, and the bottom surface of the thermal block103may be disposed at the same level as the bottom surface101bof the package substrate100. A barrier layer108may be disposed between the thermal block103and the package substrate100. At least one signal interconnection part118may be disposed in the package substrate100.

At least one interconnecting part may be disposed in the package substrate100. The interconnecting part may be a through-via111ofFIG. 8or a linking interconnection113ofFIG. 9.

The semiconductor chip200may be mounted on the top surface101aof the package substrate100. In more detail, the semiconductor chip200may be mounted on the package substrate100by a flip chip bonding technique with bumps120interposed therebetween. The bumps120may be bonded on the top surface101aof the package substrate100.

The bumps120may be arranged in a first direction and a second direction perpendicular to the first direction when viewed from a plan view. The bumps120may include first bumps122, second bumps124, and third bumps126. The first bumps122may vertically overlap with the hot spot area210of the semiconductor chip200. Thus, the first bumps122may be in electrical contact with the thermal block103. The first bumps122may include first edge bumps123. The first edge bumps123may vertically overlap with the outermost region of the hot spot area210. The second bumps124may surround the first edge bumps123when viewed from a plan view. The second bumps124may be in electrical contact with the through-vias111ofFIG. 8and/or the linking interconnections113ofFIG. 9. The third bumps126may be in electrical contact with chip pads114which are disposed on the top surface101aof the package substrate100. Each of the first bumps122may be one of a power terminal or bump and a ground terminal or bump, and each of the second bumps124may be the other of the power terminal or bump and the ground terminal or bump. A voltage difference may occur between the first bump122and the second bump124. For example, if the first bumps122are the power terminals or bumps, the second bumps124may be the ground terminals or bumps. The third bumps126may be signal bumps.

Terminals130may be disposed on the bottom surface101bof the package substrate100. The terminals130may be arranged in the first direction and the second direction when viewed from a plan view. The terminals130may include first terminals132, second terminals134, and third terminals136. The first terminals132may vertically overlap with the first region110of the package substrate100. The first terminals132may be in electrical contact with the thermal block103, so the first bumps122may be electrically connected to the first terminals132through the thermal block103. The first terminals132may include first edge terminals133. The first edge terminals133may vertically overlap with the outermost region of the first region110of the package substrate100. The second terminals134may surround the first edge terminals133when viewed from a plan view. The second terminals134may be in electrical contact with the through-vias111ofFIG. 8and/or the linking interconnections113ofFIG. 9. Thus, the second terminals134may be electrically connected to the second bumps124through the through-vias111and/or the linking interconnections113connected to the chip pads114. The third terminals136may be in electrical contact with terminal pads116which are disposed on the bottom surface101bof the package substrate100. The third bumps126may be electrically connected to the third terminals136through signal interconnection parts118disposed in the package substrate100.

Each of the first terminals132may be one of a power terminal and a ground terminal, and each of the second terminals134may be the other of the power terminal and the ground terminal. A voltage difference may occur between the first terminals132and the second terminals134. For example, if the first terminals132are the power terminals, the second terminals134may be the ground terminals. The third terminals136may be signal terminals.

If the first bumps122and the first terminals132are the power bumps and the power terminals, respectively, the thermal block103may be a power path. If the second bumps124and the second terminals134are the ground bumps and the ground terminals, respectively, the through-vias111and/or the linking interconnections113may be ground paths. The signal interconnection parts118connecting the third bumps126to the third terminals136may correspond to signal transmission paths.

According to the an example embodiment described above, the thermal block103may be used as the heat-exhausting path and the electrical connection path and the second bump124may be disposed between the first bump122and the third bump126. Thus, a distance between the thermal block103and the third bump126transmitting a signal may be sufficient to improve power characteristics. For example, a Loop-L value between the power and the ground may be reduced and a guard ring effect may be obtained by a via-fence that is formed by the second bumps124.

FIGS. 10A and 10Bare plan views illustrating a semiconductor package according to an example embodiment of the inventive concepts.FIGS. 11 and 12are cross-sectional views taken along a line I-I′ ofFIGS. 10A and 10Bto illustrate semiconductor packages according to an example embodiment of the inventive concepts. In an example embodiment ofFIGS. 10A, 10B, 11, and 12, the same elements as described in the example embodiment ofFIGS. 1A and 1Bwill be indicated by the same reference numerals or the same reference designators. For the purpose of ease and convenience in explanation, the descriptions to the same elements as in the first example embodiment will be omitted or mentioned briefly.

Referring toFIGS. 10A, 10B, 11, and 12, a semiconductor chip200may be disposed on a package substrate100. A first thermal block104and a second thermal block106may be disposed in the package substrate100. The first and second thermal blocks104and106may be spaced apart from each other and may penetrate the package substrate100. The first thermal block104may be disposed in a first region110of the package substrate100that vertically overlaps with a first hot spot area210of the semiconductor chip200. The second thermal block106may be disposed in a second region112of the package substrate100that vertically overlaps with a second hot spot area211of the semiconductor chip200. A top surface of the first thermal block104may be exposed at the top surface101aof the package substrate100, and a bottom surface of the first thermal block104may be exposed at the bottom surface101bof the package substrate100. A top surface of the second thermal block106may be exposed at the top surface101aof the package substrate100, and a bottom surface of the second thermal block106may be exposed at the bottom surface101bof the package substrate100. One or more signal interconnection parts118may be disposed in the package substrate100.

At least one interconnecting part may be disposed in the package substrate100. The interconnecting part may be a through-via111ofFIG. 11or a linking interconnection113ofFIG. 12.

The semiconductor chip200may be mounted on the top surface101aof the package substrate100, and bumps120may be disposed between the semiconductor chip200and the package substrate100. The bumps120may include first bumps122, second bumps124, third bumps126, fourth bumps128, and fifth bumps129. The first bumps122may be connected to the first hot spot area210of the semiconductor chip200and may be in electrical contact with the first thermal block104. The first bumps122may include first edge bumps123. The first edge bumps123may be connected to the outermost region of the first hot spot area210. The third bumps126may surround the first edge bumps123when viewed from a plan view. The second bumps124may be connected to the second hot spot area211of the semiconductor chip200and may be electrical contact with the second thermal block106. The second bumps124may include second edge bumps125. The second edge bumps125may be connected to the outermost region of the second hot spot area211. The fourth bumps128may surround the second edge bumps125. The fifth bumps129may be in contact with chip pads114.

Each of the first, second, third, and fourth bumps122,124,126,128may be a power terminal or bump or a ground terminal or bump. Each of the first bumps122may be one of the power terminal or bump and the ground terminal or bump, and each of the third bumps126the other of the power terminal or bump and the ground terminal or bump. Thus, a voltage difference may occur between the first bumps122and the third bumps126. Each of the second bumps124may be one of the power terminal or bump and the ground terminal or bump, and each of the fourth bumps128may be the other of the power terminal or bump and the ground terminal or bump. Thus, a voltage difference may occur between the second bumps124and the fourth bumps128. The voltage applied to the first bumps122may be equal to the voltage applied to the second bumps124, and the voltage applied to the third bumps126may be equal to the voltage applied to the fourth bumps128. Alternatively, a voltage difference may occur between the first bumps122and the second bumps124, and a voltage difference may occur between the third bumps126and the fourth bumps128. For example, if the first bumps122are the power terminals or bumps and the second bumps124are the ground terminals or bumps, the third bumps126may be the ground terminals or bumps and the fourth bumps128may be the power terminals or bumps. Alternatively, if the first bumps122and the second bumps124are the power terminals or bumps, the third bumps126and the fourth bumps128may be the ground terminals or bumps. The fifth bumps129may be signal bumps.

Terminals130may be disposed on the bottom surface101bof the package substrate100. The terminals130may include first terminals132, second terminals134, third terminals136, fourth terminals138, and fifth terminals139. The first terminals132may vertically overlap with the first region110of the package substrate100. Thus, the first terminals132may be in electrical contact with the first thermal block104so as to be electrically connected to the first bumps122. The second terminals134may vertically overlap with the second region112of the package substrate100. Thus, the second terminals134may be in electrical contact with the second thermal block104so as to be electrically connected to the second bumps124. The first terminals132may include first edge terminals133. The first edge terminals133may vertically overlap with the outermost region of the first region110of the package substrate100. The third terminals136may surround the first edge terminals133when viewed from a plan view. The second terminals134may include second edge terminals135. The second edge terminals135may vertically overlap with the outermost region of the second region112of the package substrate100. The fourth terminals138may surround the second edge terminals135when viewed from a plan view. The third and fourth terminals136and138may be electrically connected to the third and fourth bumps126and128through the through-vias111ofFIG. 11and/or the linking interconnections113ofFIG. 12. The fifth terminals139may be in electrical contact with terminal pads116which are disposed on the bottom surface101bof the package substrate100. The fifth terminals139may be electrically connected to the fifth bumps129through signal interconnection parts118disposed in the package substrate100.

Each of the first, second, third, and fourth terminals132,134,136,138may be a power terminal or a ground terminal. In more detail, each of the first terminals132may be one of the power terminal and the ground terminal, and each of the third terminals136may be the other of the power terminal and the ground terminal. Thus, a voltage difference may occur between the first terminals132and the third terminals136. Each of the second terminals134may be one of the power terminal and the ground terminal, and each of the fourth terminals138may be the other of the power terminal and the ground terminal. Thus, a voltage difference may occur between the second terminals134and the fourth terminals138. The voltage applied to the first terminals132may be equal to the voltage applied to the second terminals134, and the voltage applied to the third terminals136may be equal to the voltage applied to the fourth terminals138. Alternatively, a voltage difference may occur between the first terminals132and the second terminals134, and a voltage difference may occur between the third terminals136and the fourth terminals138. For example, if the first terminals132are the power terminals and the second terminals134are the ground terminals, the third terminals136may be the ground terminals and the fourth terminals138may be the power terminals. Alternatively, if the first and second terminals132and134are the power terminals, the third and fourth terminals136and138may be the ground terminals. The fifth terminals139may be signal terminals.

For example, if the first bumps122and the first terminals132are the power bumps and the power terminals, the first thermal block104may correspond to a power path. If the second bumps124and the second terminals134are the ground bumps and the grounder terminals, the second thermal block106may correspond to a ground path. If the third bumps126and the third terminals136are the ground bumps and the ground terminals, the through-vias111and/or the linking interconnections113connected thereto may be ground paths. If the fourth bumps128and the fourth terminals138are the power bumps and the power terminals, the through-vias111and/or the linking interconnections113connected thereto may be power paths. The signal interconnections parts118connected to the fifth bumps and terminals129and139may correspond to signal transmission paths.

FIGS. 13A and 13Bare plan views illustrating a semiconductor package according to an example embodiment of the inventive concepts.FIG. 14is a cross-sectional view taken along a line I-I′ ofFIGS. 13A and 13Bto illustrate the semiconductor package according to an example embodiment of the inventive concepts. In an example embodiment ofFIGS. 13A,13B, and14, the same elements as described in previous example embodiments will be indicated by the same reference numerals or the same reference designators. For the purpose of ease and convenience in explanation, the descriptions to the same elements as in previous example embodiments will be omitted or mentioned briefly.

Referring toFIGS. 13A, 13B, and 14, the first and second thermal blocks104and106may be disposed in the package substrate100. The first thermal block104may be disposed in the first region110of the package substrate100which is adjacent to the first hot spot area210of the semiconductor chip200. The second thermal block106may be disposed in the second region112of the package substrate100which is adjacent to the second hot spot area211of the semiconductor chip200. The first and second hot spot areas210and211may be spaced apart from each other.

Bumps120may be disposed on the top surface101aof the package substrate100. The bumps120may include first bumps122, second bumps124, third bumps126aand126b, and fourth bumps128. The first bumps122may be connected to the first hot spot area210and may be in electrical contact with the first thermal block104. The second bumps124may be connected to the second hot spot area211and may be in electrical contact with the second thermal block106. The third bumps126aand126bmay surround first edge bumps123of the first bumps122and second edge bumps125of the second bumps124when viewed from a plan view. The first edge bumps123may vertically overlap with the outermost region of the first hot spot area210, and the second edge bumps125may vertically overlap with the outermost region of the second hot spot area211. As illustrated inFIG. 13A, some of the third bumps126amay be disposed between the first and second hot spot areas210and211and others of the third bumps126bmay be disposed around the first and second hot spot areas210and211when viewed from a plan view. The third bumps126adisposed between the first and second hot spot areas210and211in a plan view may be arranged to constitute a plurality of columns. In an example embodiment, the third bumps126abetween the first and second hot spot areas210and211may be arranged along two columns when viewed from a plan view.

The same voltage may be applied to the first bumps122and the second bumps124. On the other hand, a voltage difference may occur between the first bump122and each of the third bumps126aand126band between the second bump124and each of the third bumps126aand126b. For example, if the first bumps122and the second bumps124are power terminals or bumps, the third bumps126aand126bmay be ground terminals or bumps. The fourth bumps128may be signal bumps.

Terminals130may be disposed on the bottom surface101bof the package substrate100. The terminals130may include first terminals132, second terminals134, third terminals136aand136b, and fourth terminals138. The first terminals132may vertically overlap with the first region110of the package substrate100so as to be electrically connected to the first thermal block104. The second terminals134may vertically overlap with the second region112of the package substrate100so as to be electrically connected to the second thermal block106. The third terminals136aand136bmay surround first edge terminals133of the first terminals132and second edge terminals135of the second edge terminals134. The first edge terminals133may vertically overlap with the outermost region of the first region110of the package substrate100, and the second edge terminals135may vertically overlap with the outermost region of the second region112of the package substrate100. As illustrated inFIG. 13B, some136aof the third terminals may be disposed between the first and second regions110and112and others136bof the third terminals may be disposed around the first and second regions110and112when viewed from a plan view. The third terminals136abetween the first and second regions110and112may be arranged to constitute one or more columns when viewed from a plan view. In an example embodiment, the third terminals136abetween the first and second regions110and112may be arranged to constitute one column when viewed from a plan view. In some example embodiments, the number of the columns of the third bumps126abetween the first and second hot spot areas210and211may be more than the number of the column of the third terminals136abetween the first and second regions110and112when viewed from a plan view.

The same voltage may be applied to the first and second terminals132and134. On the other hand, a voltage difference may occur between the first terminal132and each of the third terminals136aand136band between the second terminal134and each of the third terminals136aand136b. For example, if the first and second terminals132and134are power terminals, the third terminals136aand136bmay be ground terminals. The fourth terminals138may be signal terminals.

For example, the first bumps122may be electrically connected to the first terminals132through the first thermal block104, and the second bumps124may be electrically connected to the second terminals134through the second thermal block106. The third bumps126abetween the first and second hot spot areas210and211may be electrically connected to the third terminal136adisposed between the first and second regions110and112through first and second interconnecting parts115and117. The first interconnecting part115may be connected to one of the third bumps126a, and the second interconnecting part117may be connected to another of the third bumps126a. The third bumps126bnot connected to the first and second interconnecting parts115and117may be electrically connected to the third terminals136b, not connected to the first and second interconnecting parts115and117, through linking interconnections113. If the first and second thermal blocks104and106are the power paths, the first and second interconnecting part115and117and the linking interconnections113may be the ground paths. Signal interconnection parts118electrically connecting the fourth bumps128to the fourth terminals138may correspond to signal transmission paths.

FIG. 15is a schematic block diagram illustrating an example embodiment of an electronic system including a semiconductor package according to example embodiments of the inventive concepts.FIG. 16is a schematic block diagram illustrating an example embodiment of a memory system including a semiconductor package according to example embodiments of the inventive concepts.

Referring toFIG. 15, an electronic system3000may include a controller3100, an input/output (I/O) device3200, and a memory device3300. The controller3100, the I/O device3200, and the memory device3300may communicate with each other through a data bus3500. The data bus3500may correspond to a path through which electrical data are transmitted. For example, the controller3100may include at least one of a microprocessor, a digital signal processor, a microcontroller, or another logic device having the same function as any one thereof. At least one of the controller3100and the memory device3300may include at least one of the semiconductor packages according to the aforementioned embodiments of the inventive concepts. The I/O device3200may include a keypad, a keyboard and/or a display device. The memory device3300is a device storing data. The memory device3300may store data and/or commands executed by the controller3100. The memory device3300may include a volatile memory device and/or a non-volatile memory device. In an embodiment, the memory device3300may include a flash memory device. For example, the flash memory device implemented with the semiconductor package according to the inventive concepts may be installed in the electronic system3000such as a mobile device and a desk top computer. The flash memory device may be realized as a solid state disk (SSD). In this case, the electronic system3000may stably store massive data in the flash memory device. The electronic system3000may further include an interface unit3400that is used to transmit electrical data to a communication network and/or to receive electrical data from the communication network. The interface unit3400may operate by wireless or cable. For example, the interface unit3400may include an antenna or a wireless/cable transceiver. Although not shown in the drawings, the electronic system3000may further include an application chipset and/or a camera image processor (CIS).

The electronic system3000may be realized as a mobile system, a personal computer, an industrial computer, or a logic system performing various functions. For example, the mobile system may be a personal digital assistant (PDA), a portable computer, a web tablet, a mobile phone, a wireless phone, a laptop computer, a memory card, a digital music player, or other electronic products receiving and/or transmitting information data. If the electronic system3000is a device capable of performing wireless communication, the electronic system3000may be used in a communication interface protocol of a communication system such as CDMA, GSM, NADC, E-TDMA, WCDMA, CDMA2000, Wi-Fi, Muni Wi-Fi, Bluetooth, DECT, Wireless USB, Flash-OFDM, IEEE 802.20, GPRS, iBurst, WiBro, WiMAX, WiMAX-Advanced, UMTS-TDD, HSPA, EVDO, LTE-Advanced, or MMDS.

Referring toFIG. 16, a memory system4000may include a non-volatile memory device4100and a memory controller4200. The non-volatile memory device4100and the memory controller4200may store logical data and/or read stored data. The non-volatile memory device4100may include at least one of the semiconductor packages according to the aforementioned embodiments of the inventive concepts. The memory controller4200may control the non-volatile memory device4100to read stored data and/or to store data in response to read request and/or write request of a host4300.

According to embodiments of the inventive concepts, one thermal block may be used as one of the power path and the ground path, and another thermal block and/or the interconnecting part adjacent to the one thermal block may be used as the other of the power path and the ground path. In other words, the thermal block may be used as the heat-exhausting path and the electrical connection path at the same time, so the area of the package substrate may be effectively used. In addition, the distance between the power and the ground may be shortened, so the power characteristics of the semiconductor package may be improved.