Process monitoring by comparing delays proportional to test voltages and reference voltages

An evaluation circuit includes a test circuit configured to provide a test voltage indicative of a characteristic of a semiconductor device, a reference circuit configured to provide a first reference voltage, a first delay circuit configured to convert the test voltage into a first delay, a second delay circuit configured to convert the first reference voltage into a second delay, and a first latching circuit configured to determine a relationship between the first delay and the second delay.

BACKGROUND

In semiconductor manufacturing, it is difficult to design and build a semiconductor chip having the same process for a positive channel field effect transistor (pFET) or negative channel field effect transistor (nFET) and the same characteristics in every batch of chips. Varying processes and characteristics of semiconductor chips from chip to chip can affect the performance of the semiconductor chip including the electrical behavior, set-up and hold times, off chip driver slew rate, etc. Sometimes these varying processes and characteristics can be so extreme that the semiconductor chip fails to meet specifications.

A representative pFET or nFET of a semiconductor chip can be tested to determine whether the process for the pFETs and nFETs in the chip are fast (strong) or slow (weak). Based on the test results, action can be taken to offset any undesirable characteristics of the semiconductor chip due to the process. In addition, if an external voltage supplied to the semiconductor chip varies, by determining the variation, action can be taken to adjust for any effects the variation may cause. For example, by evaluating the characteristics of a pFET, nFET, and/or external voltage supplied to the semiconductor chip, an off-chip driver (OCD) on the chip can be adjusted as needed to compensate for any effects due to variations in the characteristics from nominal values.

SUMMARY

One embodiment of the invention provides an evaluation circuit. The evaluation circuit comprises a test circuit configured to provide a test voltage indicative of a characteristic of a semiconductor device, a reference circuit configured to provide a first reference voltage, a first delay circuit configured to convert the test voltage into a first delay, a second delay circuit configured to convert the first reference voltage into a second delay, and a first latching circuit configured to determine a relationship between the first delay and the second delay.

DETAILED DESCRIPTION

FIG. 1is a block diagram illustrating one embodiment of a memory system100having a voltage/process evaluation circuit. Memory system100includes a semiconductor chip102and a memory device106. Semiconductor chip102is electrically coupled to memory device106through path104. Semiconductor chip102includes voltage/process evaluation circuit108and off chip driver (OCD) circuit112. Voltage/process evaluation circuit108is electrically coupled to OCD112through path110. In one embodiment, semiconductor chip102includes a receiver circuit, generator circuit, a set up and hold time adjustment circuit, or any other suitable circuit. In one embodiment, memory device106and semiconductor chip102are a single semiconductor chip.

Voltage/process evaluation circuit108evaluates the incoming voltage supplied to chip102and the process of a negative channel field effect transistor (nFET) and a positive channel field effect transistor (pFET) in chip102. The nFET and pFET that are evaluated are representative of all the nFETs and pFETs in chip102. The evaluation results are passed to portions of OCD112through path110. Based on the evaluation results, portions of OCD112are adjusted such that chip102meets specified specifications.

Voltage/process evaluation circuit108utilizes a number of circuits to perform the evaluations. A test circuit is used to evaluate the external voltage supplied to chip102. The supplied voltage is converted into a delayed clock signal, where the delay is proportional to the value of the supplied voltage. A reference voltage representing a nominal value for the supplied voltage is also converted into a delayed clock signal, where the delay is proportional to the value of the reference voltage. The delay proportional to the supplied voltage is compared to the delay proportional to the reference voltage to compare the supplied voltage to the reference voltage.

Voltage/process evaluation circuit108also includes test circuits to evaluate the processes for the nFETs and pFETs in chip102. The test circuits provide test voltages indicative of the processes for the FETs. The test voltages are converted into delayed clock signals, where the delays are proportional to the values of the test voltages. Reference voltages representing nominal values for the test voltages are also converted into delayed clock signals, where the delays are proportional to the reference voltages. The delays proportional to the FET processes are compared to the delays proportional to the reference voltages to compare the processes for the FETS to the reference values.

By converting the test voltages and reference voltages to delays rather than comparing them directly using comparators, power is conserved and process detection and evaluation is completed more quickly than if comparators were used. This voltage and process evaluation can occur each time chip102is reset or whenever desired.

Memory device106includes a dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate (DDR) SDRAM, or other suitable memory. Memory device106communicates with chip102through path104.

The VINTsignal is a voltage signal supplied by an external voltage source, internal voltage source, or other suitable voltage source. Test circuit124receives the VINTsignal on VINTsignal path120as an input and outputs a test voltage proportional to VINTto inverter chain128through signal path126. The test voltage is received by inverter chain128and controls inverter chain128. Inverter chain128receives the CLK signal through CLK signal path122as an input. Based on the test voltage received from test circuit124, the CLK signal is delayed as it propagates through inverter chain128. Inverter chain128outputs a delayed clock signal, which is proportional to the test voltage received from test circuit124, to inverter chain136through signal path130.

Reference circuit142receives the VINTvoltage on VINTsignal path120as an input and outputs a reference voltage to inverter chain146through signal path144. In one embodiment, the reference voltage is a nominal voltage for the test voltage. The reference voltage is received by inverter chain146and controls inverter chain146. Inverter chain146receives the CLK signal through CLK signal path122as an input. Based on the reference voltage received from reference circuit142, the CLK signal is delayed as it propagates through inverter chain146. Inverter chain146outputs a delayed clock signal, which is proportional to the reference voltage received from reference circuit142, to inverter chain154through signal path148.

Reference circuit132receives the VINTsignal on VINTsignal path120as an input and outputs a reference voltage to inverter chain136through signal path134. In one embodiment, the reference voltage is a voltage indicating a nominal process for either an nFET or pFET. The reference voltage is received by inverter chain136and controls inverter chain136. Inverter chain136receives the delayed clock signal from inverter chain128through signal path130as an input. Based on the reference voltage received from reference circuit132, the delayed clock signal is further delayed as it propagates through inverter chain136. Inverter chain136outputs a delayed clock signal, which is proportional to both the test voltage received from test circuit124and the reference voltage received from reference circuit132, to latch140through signal path138.

Test circuit150receives the VINTsignal on VINTsignal path120as an input and outputs a test voltage to inverter chain154through signal path152. In one embodiment, the test voltage is indicative of the process for a pFET or nFET. The test voltage is received by inverter chain154and controls inverter chain154. Inverter chain154receives the delayed clock signal from inverter chain146through signal path148as an input. Based on the test voltage received from test circuit150, the delayed clock signal is further delayed as it propagates through inverter chain154. Inverter chain154outputs a delayed clock signal, which is proportional to both the reference voltage received from reference circuit142and the test voltage received from test circuit152, to latch140through signal path156.

Latch140receives the delayed clock signal from inverter chain136through signal path138and the delayed clock signal from inverter chain154through signal path156. If the rising edge of the delayed clock signal on signal path138arrives to the input of latch140before the rising edge of the delayed clock signal on signal path156, latch140outputs a logic high level signal on D1signal path158and a logic low level signal on D2signal path160. If the rising edge of the delayed clock signal on signal path156arrives to the input of latch140before the rising edge of the delayed clock signal on signal path138, latch140outputs a logic low level signal on D1signal path158and a logic high level signal on D2signal path160. Latch140maintains the output signals on D1signal path158and D2signal path160until another evaluation is performed.

The length of inverter chains128,136,146, and154are set such that the effect of the supplied voltage and the process of an nFET or pFET on semiconductor chip102can be balanced for evaluation.

FIGS. 3aand3bare schematic diagrams illustrating one embodiment of current starved inverter chain128. Inverter chains136,146, and154are similar to inverter chain128. As illustrated inFIG. 3a, inverter chain128includes inverters200a-200(n). The CLK signal on CLK signal path122is electrically coupled to the input of inverter200a. The output of inverter200ais electrically coupled to the input of inverter200bthrough path202a. The output of inverter200bis electrically coupled to the next inverter in inverter chain128through path202b, etc., until the input of the last inverter200(n) in inverter chain128is coupled to the output of the previous inverter in inverter chain128. The output of inverter200(n) is electrically coupled to path202(n), which is the same as signal path130. The controlling inputs of inverters200a-200(n) are electrically coupled to signal path126. The length of inverter chain128is based on the desired length of the delay for the CLK signal. The CLK signal on CLK signal path122is delayed as it propagates through each inverter200a-200(n) in proportion to the test voltage on signal path126.

VINT320is electrically coupled to one side of the source-drain path of transistor214athrough path212a. The other side of the source-drain path of transistor214ais electrically coupled to one side of the source-drain path of transistor216aand the gates of transistors214band216bthrough path202a. The gate of transistor214aand the gate of transistor216aare electrically coupled to CLK signal path122. The other side of the source-drain path of transistor216ais electrically coupled to one side of the source-drain path of transistor220athrough path218a. The other side of the source-drain path of transistor220ais electrically coupled to ground or common224through path222a. The gate of transistor220ais electrically coupled to the gates of transistors220b-220(n) through signal path126.

VINT320is electrically coupled to one side of the source-drain path of transistor214bthrough path212b. The other side of the source-drain path of transistor214bis electrically coupled to one side of the source-drain path of transistor216band the gates of the next transistor214and transistor216in inverter chain128. The other side of the source-drain path of transistor216bis electrically coupled to one side of the source-drain path of transistor220bthrough path218b. The other side of the source-drain path of transistor220bis electrically coupled to ground or common224through path222b.

VINT320is electrically coupled to one side of the source-drain path of transistor214(n) through path212(n). The other side of the source-drain path of transistor214(n) is electrically coupled to signal path202(n), which is the same as signal path130, and one side of the source-drain source path of transistor216(n). The other side of the source-drain path of transistor216(n) is electrically coupled to one side of the source-drain path of transistor220(n) through path218(n). The other side of the source-drain path of transistor220(n) is electrically coupled to common or ground224through path222(n).

Inverters200a-200(n) are current starved inverters controlled by the test voltage from test circuit124through signal path126. The CLK signal on CLK signal path122is delayed as it propagates through inverters200a-200(n). The delay of the CLK signal through inverters200a-200(n) is proportional to the test voltage on signal path126applied to the gates of transistors220a-220(n). Inverter chains136,146, and154operate in a similar manner as inverter chain128.

FIG. 4is a schematic diagram illustrating one embodiment of latch140. Latch140includes NAND gates300,304,306, and310. One input of NAND gate300is electrically coupled to signal path138and the other input of NAND gate300is electrically coupled to the output of NAND gate306and one input of NAND gate310through path308. The output of NAND gate300is electrically coupled to one input of NAND gate304and one input of NAND gate306through path302. The other input of NAND gate306is electrically coupled to signal path156. The output of NAND gate304is electrically coupled to the other input of NAND gate310through D1signal path158. The output of NAND gate310is electrically coupled to the other input of NAND gate304through D2signal path160.

In operation, if a rising edge of the delayed clock signal on signal path138arrives to the input of NAND gate300before a rising edge of the delayed clock signal on signal path156arrives to the input of NAND gate306, the output on D1signal path158transitions to a logic high level and the output on D2signal path160transitions to a logic low level. If a rising edge of the delayed clock signal on signal path156arrives to the input of NAND gate306before a rising edge of the delayed clock signal on signal path138arrives to the input of NAND gate300, the output on D2signal path160transitions to a logic high level and the output on D1signal path158transitions to a logic low level. The signals on D1signal path158and D2signal path160will remain constant until another evaluation is performed.

FIG. 5is a schematic diagram illustrating one embodiment of test circuit124for evaluating a supplied voltage. Test circuit124includes resistor322and resistor324. Resistor322is electrically coupled to VINT320through path321and resistor324through divided voltage (VDIV) signal path126. Resistor324is electrically coupled to common or ground224through path326.

In operation, test circuit124receives the VINTsignal, which is supplied by an external circuit to semiconductor chip102, and divides the VINTbetween resistor322and324. Test circuit124outputs the VDIVsignal on signal path126to inverter chain128. The VDIVsignal is proportional to the VINTsignal.

FIG. 6is a schematic diagram illustrating one embodiment of reference circuit142for evaluating a supplied voltage. Reference circuit142includes voltage source328. Voltage source328is electrically coupled to reference voltage (VREF) signal path144and common or ground224through path330. Reference circuit142provides a reference voltage, VREF, which indicates a nominal value for the supplied voltage for comparison to the VDIVsignal from test circuit124.

Test circuit124receives the VINTsignal on VINTsignal path120as an input and outputs the VDIVsignal to inverter chain128through signal path126. The VDIVsignal is received by inverter chain128and controls inverter chain128. Inverter chain128receives the CLK signal through CLK signal path122as an input. Based on the VDIVsignal received from test circuit124, the CLK signal is delayed as it propagates through inverter chain128. Inverter chain128outputs a delayed clock signal, which is proportional to the VDIVsignal received from test circuit124, to latch140through signal path332.

Reference circuit142receives the VINTvoltage on VINTsignal path120as an input and outputs the VREFsignal to inverter chain146through signal path144. In one embodiment, the VREFsignal is a nominal voltage for the VDIVsignal. The VREFsignal is received by inverter chain146and controls inverter chain146. Inverter chain146receives the CLK signal through CLK signal path122as an input. Based on the VREFsignal received from reference circuit142, the CLK signal is delayed as it propagates through inverter chain146. Inverter chain146outputs a delayed clock signal, which is proportional to the VREFsignal received from reference circuit142, to latch140through path334.

Latch140receives the delayed clock signal from inverter chain128through signal path332and the delayed clock signal from inverter chain146through signal path334. If the rising edge of the delayed clock signal on signal path332arrives to the input of latch140before the rising edge of the delayed clock signal on signal path334, latch140outputs a logic high level signal on D1signal path158and a logic low level signal on D2signal path160. If the rising edge of the delayed clock signal on signal path334arrives to the input of latch140before the rising edge of the delayed clock signal on signal path332, latch140outputs a logic low level signal on D1signal path158and a logic high level signal on D2signal path160. Latch140maintains the output signals on D1signal path158and D2signal path160until another evaluation is performed.

If VDIVis greater than VREF, which indicates the supplied voltage is greater than the nominal voltage, then a logic high level signal is latched on D1signal path158and a logic low level signal is latched on D2signal path160. If VDIVis less than VREF, which indicates the supplied voltage is less than the nominal voltage, then a logic low level signal is latched on D1signal path158and a logic high level signal is latched on D2signal path160.

FIG. 8is a schematic diagram illustrating one embodiment of test circuit150, indicated as test circuit150a, for evaluating the process of an nFET. Test circuit150aincludes resistor342, transistor344, and voltage source348. Transistor344is an nFET. Resistor342is electrically coupled to VINT320through path340and one side of the source-drain path of transistor344through VnMsignal path152a. The other side of the source-drain path of transistor344is electrically coupled to common or ground224through path352. The gate of transistor344is electrically coupled to voltage source348through path346. Voltage source348is electrically coupled to common or ground224through path350.

Voltage source348provides a voltage to the gate of transistor344to turn transistor344on (conducting). VINTvoltage320is divided between resistor342and the source-drain path of transistor344to output a voltage, VnM, on VnMsignal path152a. The VnMvoltage on VnMsignal path142ais indicative of the process for transistor344. Transistor344is representative of all nFET transistors of semiconductor chip102.

FIG. 9is a schematic diagram illustrating one embodiment of reference circuit132, indicated as reference circuit132a, for evaluating the process of an nFET. Reference circuit132aincludes resistor362and current source364. Resistor362is electrically coupled to VINT320through path360and current source364through VnRsignal path134a. Current source364is electrically coupled to common or ground224through path366. The resistance of resistor362is substantially equal to the resistance of resistor342.

Reference circuit134aprovides a reference voltage output on VnRsignal path134afor comparison to the VnMvoltage on signal path152a. The voltage on VnRsignal path134aindicates a nominal process for transistor344.

Reference circuit132areceives the VINTvoltage on VINTsignal path120as an input and outputs the VnRsignal to inverter chain136athrough signal path134a. In one embodiment, the VnRsignal is a nominal voltage for the VnMsignal. The VnRsignal is received by inverter chain136aand controls inverter chain136a. Inverter chain136areceives the CLK signal through CLK signal path122as an input. Based on the VnRsignal received from reference circuit132a, the CLK signal is delayed as it propagates through inverter chain136a. Inverter chain136aoutputs a delayed clock signal, which is proportional to the VnRsignal received from reference circuit132a, to latch140through signal path138a.

Test circuit150areceives the VINTsignal on VINTsignal path120as an input and outputs the VnMsignal to inverter chain154athrough signal path152a. The VnMsignal is received by inverter chain154aand controls inverter chain154a. Inverter chain154areceives the CLK signal through CLK signal path122as an input. Based on the VnMsignal received from test circuit150a, the CLK signal is delayed as it propagates through inverter chain154a. Inverter chain154aoutputs a delayed clock signal, which is proportional to the VnMsignal received from test circuit150a, to latch140through signal path156a.

Latch140receives the delayed clock signal from inverter chain136athrough signal path138aand the delayed clock signal from inverter chain154athrough signal path156a. If the rising edge of the delayed clock signal on signal path138aarrives to the input of latch140before the rising edge of the delayed clock signal on signal path156a, latch140outputs a logic high level signal on D1signal path158and a logic low level signal on D2signal path160. If the rising edge of the delayed clock signal on signal path156aarrives to the input of latch140before the rising edge of the delayed clock signal on signal path138a, latch140outputs a logic low level signal on D1signal path158and a logic high level signal on D2signal path160. Latch140maintains the output signals on D1signal path158and D2signal path160until another evaluation is performed.

If VnMis greater than VnR, which indicates the process of nFET344is slower than nominal, then a logic low level signal is latched on D1signal path158and a logic high level signal is latched on D2signal path160. If VnMis less than VnR, which indicates the process of nFET344is faster than nominal, then a logic high level signal is latched on D1signal path158and a logic low level signal is latched on D2signal path160.

FIG. 11is a schematic diagram illustrating another embodiment of a test circuit150, indicated as test circuit150b, for evaluating the process of a pFET. Test circuit150bincludes voltage source402, transistor408, and resistor410. Transistor408is a pFET. Voltage source402is electrically coupled to VINT320through path400and the gate of transistor408through path404. One side of the source-drain path of transistor408is electrically coupled to VINT320through path406. The other side of the source-drain path of transistor408is electrically coupled to resistor410thorough VpMsignal path152b. Resistor410is electrically coupled to common or ground224through path412.

Voltage source402provides a voltage to the gate of transistor408to turn transistor408on (conducting). VINT320is divided between the source-drain path of transistor408and resistor410to output a voltage VpM, on VpMsignal path152b. The VpMvoltage on VpMsignal path152bis indicative of the process for transistor408. Transistor408is representative of all pFET transistors of semiconductor chip102.

FIG. 12is a schematic diagram illustrating another embodiment of reference circuit132, indicated as reference circuit132b, for evaluating the process of a pFET. Reference circuit132bincludes current source422and resistor424. Current source422is electrically coupled to VINT320through path420and resistor424through VpRsignal path134b. Resistor424is electrically coupled to common or ground224through path426. The resistance of resistor424is substantially equal to the resistance of resistor410.

Reference circuit132bprovides a reference voltage output on VpRsignal path134bfor comparison to the VpMvoltage on signal path152b. The voltage on VpRsignal path134bindicates a nominal process for transistor408.

FIG. 13is a block diagram illustrating one embodiment of an evaluation circuit428for evaluating the process for pFET408. Evaluation circuit428includes reference circuit132b, test circuit150b, inverter chains136band154b, and latch140.

Reference circuit132breceives the VINTvoltage on VINTsignal path120as an input and outputs the VpRsignal to inverter chain136bthrough signal path134b. In one embodiment, the VpRsignal is a nominal voltage for the VpMsignal. The VpRsignal is received by inverter chain136band controls inverter chain136b. Inverter chain136breceives the CLK signal through CLK signal path122as an input. Based on the VpRsignal received from reference circuit132b, the CLK signal is delayed as it propagates through inverter chain136b. Inverter chain136boutputs a delayed clock signal, which is proportional to the VpRsignal received from reference circuit132b, to latch140through signal path138b.

Test circuit150breceives the VINTsignal on VINTsignal path120as an input and outputs the VpMsignal to inverter chain154bthrough signal path152b. The VpMsignal is received by inverter chain154band controls inverter chain154b. Inverter chain154breceives the CLK signal through CLK signal path122as an input. Based on the VpMsignal received from test circuit150b, the CLK signal is delayed as it propagates through inverter chain154b. Inverter chain154boutputs a delayed clock signal, which is proportional to the VpMsignal received from test circuit150b, to latch140through signal path156b.

Latch140receives the delayed clock signal from inverter chain136bthrough signal path138band the delayed clock signal from inverter chain154bthrough signal path156b. If the rising edge of the delayed clock signal on signal path138barrives to the input of latch140before the rising edge of the delayed clock signal on signal path156b, latch140outputs a logic high level signal on D1signal path158and a logic low level signal on D2signal path160. If the rising edge of the delayed clock signal on signal path156barrives to the input of latch140before the rising edge of the delayed clock signal on signal path138b, latch140outputs a logic low level signal on D1signal path158and a logic high level signal on D2signal path160. Latch140maintains the output signals on D1signal path158and D2signal path160until another evaluation is performed.

If VpMis greater than VpR, which indicates the process of pFET408is faster than nominal, then a logic low level signal is latched on D1signal path158and a logic high level signal is latched on D2signal path160. If VpMis less than VpR, which indicates the process of pFET408is slower than nominal, then a logic high level signal is latched on D1signal path158and a logic low level signal is latched on D2signal path160.

FIG. 14is a schematic diagram illustrating one embodiment of a reference circuit500for providing multiple reference signals for evaluating the process of an nFET. Reference circuit500includes resistors502,506,510, and514, and current source518. Resistor502is electrically coupled to VINT320through path501and resistor506through slowest process nFET reference voltage (VnRSS) signal path504. Resistor506is electrically coupled to resistor510through slow process nFET reference voltage (VnRS) signal path508. Resistor510is electrically coupled to resistor514through fast process nFET reference voltage (VnRF) signal path512. Resistor514is electrically coupled to current source518through fastest process nFET reference voltage (VnRFF) signal path516. Current source518is electrically coupled to common or ground224through path520. The sum of the resistances of resistors502,506,510, and514is substantially equal to the resistance of resistor342.

Reference circuit500provides four reference voltages to compare to VnMfrom test circuit150a. VnRSSindicates the slowest process for nFET344. VnRSindicates a slow process for nFET344, but faster than VnRSS. VnRFindicates a fast process for nFET344and VnRFFindicates the fastest process for nFET344. In other embodiments, reference circuit500includes more than four resistors to provide more than four reference voltages. Any suitable number of resistors to provide any suitable number of reference voltages can be provided.

FIG. 15is a block diagram illustrating one embodiment of an evaluation circuit521having multiple latches for evaluating the process for nFET344. Process evaluation circuit521includes inverter chains522,526,542,546,562,566,582, and586, and latches530,550,570, and590. In one embodiment, inverter chains526,546,566, and586, are replaced with a single inverter chain having an output coupled to latches530,550,570, and590. Inverter chains522,526,542,546,562,566,582, and586are similar to inverter chain128. Latches530,550,570, and590are similar to latch140.

Inverter chain522is electrically coupled to VnRSSsignal path504, CLK signal path122, and latch530through signal path524. Inverter chain526is electrically coupled to VnMsignal path152a, CLK signal path122, and latch530through signal path528. Latch530is electrically coupled to nFET latch A data one (Dn1a) signal path532and nFET latch A data two (Dn2a) signal path534.

Inverter chain562is electrically coupled to VnRFsignal path512, CLK signal path122, and latch570through signal path564. Inverter chain556is electrically coupled to VnMsignal path152a, CLK signal path122, and latch570through signal path568. Latch570is electrically coupled to nFET latch C data one (Dn1c) signal path572and nFET latch C data two (Dn2c) signal path574.

Reference circuit500outputs the VnRSSsignal to inverter chain522through signal path504. The VnRSSsignal is received by inverter chain522and controls inverter chain522. Inverter chain522receives the CLK signal through CLK signal path122as an input. Based on the VnRSSsignal received from reference circuit500, the CLK signal is delayed as it propagates through inverter chain522. Inverter chain522outputs a delayed clock signal, which is proportional to the VnRSSsignal received from reference circuit500, to latch530through signal path524.

Test circuit150aoutputs the VnMsignal to inverter chain526through signal path152a. The VnMsignal is received by inverter chain526and controls inverter chain526. Inverter chain526receives the CLK signal through CLK signal path122as an input. Based on the VnMsignal received from test circuit150a, the CLK signal is delayed as it propagates through inverter chain526. Inverter chain526outputs a delayed clock signal, which is proportional to the VnMsignal received from test circuit150a, to latch530through signal path528.

Latch530receives the delayed clock signal from inverter chain522through signal path524and the delayed clock signal from inverter chain526through signal path528. If the rising edge of the delayed clock signal on signal path524arrives to the input of latch530before the rising edge of the delayed clock signal on signal path528, latch530outputs a logic high level signal on Dn1a signal path532and a logic low level signal on Dn2a signal path534. If the rising edge of the delayed clock signal on signal path528arrives to the input of latch530before the rising edge of the delayed clock signal on signal path524, latch530outputs a logic low level signal on Dn1a signal path532and a logic high level signal on Dn2a signal path534. Latch530maintains the output signals on Dn1a signal path532and Dn2a signal path534until another evaluation is performed.

Reference circuit500outputs the VnRSsignal to inverter chain542through signal path508. The VnRSsignal is received by inverter chain542and controls inverter chain542. Inverter chain542receives the CLK signal through CLK signal path122as an input. Based on the VnRSsignal received from reference circuit500, the CLK signal is delayed as it propagates through inverter chain542. Inverter chain542outputs a delayed clock signal, which is proportional to the VnRSsignal received from reference circuit500, to latch550through signal path544.

Test circuit150aoutputs the VnMsignal to inverter chain546through signal path152a. The VnMsignal is received by inverter chain546and controls inverter chain546. Inverter chain546receives the CLK signal through CLK signal path122as an input. Based on the VnMsignal received from test circuit150a, the CLK signal is delayed as it propagates through inverter chain546. Inverter chain546outputs a delayed clock signal, which is proportional to the VnMsignal received from test circuit150a, to latch550through signal path548.

Latch550receives the delayed clock signal from inverter chain542through signal path544and the delayed clock signal from inverter chain546through signal path548. If the rising edge of the delayed clock signal on signal path544arrives to the input of latch550before the rising edge of the delayed clock signal on signal path548, latch550outputs a logic high level signal on Dn1b signal path552and a logic low level signal on Dn2b signal path554. If the rising edge of the delayed clock signal on signal path548arrives to the input of latch550before the rising edge of the delayed clock signal on signal path544, latch550outputs a logic low level signal on Dn1b signal path552and a logic high level signal on Dn2b signal path554. Latch550maintains the output signals on Dn1b signal path552and Dn2b signal path554until another evaluation is performed.

Reference circuit500outputs the VnRFsignal to inverter chain562through signal path512. The VnRFsignal is received by inverter chain562and controls inverter chain562. Inverter chain562receives the CLK signal through CLK signal path122as an input. Based on the VnRFsignal received from reference circuit500, the CLK signal is delayed as it propagates through inverter chain562. Inverter chain562outputs a delayed clock signal, which is proportional to the VnRFsignal received from reference circuit500, to latch570through signal path564.

Test circuit150aoutputs the VnMsignal to inverter chain566through signal path152a. The VnMsignal is received by inverter chain566and controls inverter chain566. Inverter chain566receives the CLK signal through CLK signal path122as an input. Based on the VnMsignal received from test circuit150a, the CLK signal is delayed as it propagates through inverter chain566. Inverter chain566outputs a delayed clock signal, which is proportional to the VnMsignal received from test circuit150a, to latch570through signal path568.

Latch570receives the delayed clock signal from inverter chain562through signal path564and the delayed clock signal from inverter chain566through signal path568. If the rising edge of the delayed clock signal on signal path564arrives to the input of latch570before the rising edge of the delayed clock signal on signal path568, latch570outputs a logic high level signal on Dn1c signal path572and a logic low level signal on Dn2c signal path574. If the rising edge of the delayed clock signal on signal path568arrives to the input of latch570before the rising edge of the delayed clock signal on signal path564, latch570outputs a logic low level signal on Dn1c signal path572and a logic high level signal on Dn2c signal path574. Latch570maintains the output signals on Dn1c signal path572and Dn2c signal path574until another evaluation is performed.

Reference circuit500outputs the VnRFFsignal to inverter chain582through signal path516. The VnRFFsignal is received by inverter chain582and controls inverter chain582. Inverter chain582receives the CLK signal through CLK signal path122as an input. Based on the VnRFFsignal received from reference circuit500, the CLK signal is delayed as it propagates through inverter chain582. Inverter chain582outputs a delayed clock signal, which is proportional to the VnRFFsignal received from reference circuit500, to latch590through signal path584.

Test circuit150aoutputs the VnMsignal to inverter chain586through signal path152a. The VnMsignal is received by inverter chain586and controls inverter chain586. Inverter chain586receives the CLK signal through CLK signal path122as an input. Based on the VnMsignal received from test circuit150a, the CLK signal is delayed as it propagates through inverter chain586. Inverter chain586outputs a delayed clock signal, which is proportional to the VnMsignal received from test circuit150a, to latch590through signal path588.

Latch590receives the delayed clock signal from inverter chain582through signal path584and the delayed clock signal from inverter chain586through signal path588. If the rising edge of the delayed clock signal on signal path584arrives to the input of latch590before the rising edge of the delayed clock signal on signal path588, latch590outputs a logic high level signal on Dn1d signal path592and a logic low level signal on Dn2d signal path594. If the rising edge of the delayed clock signal on signal path588arrives to the input of latch590before the rising edge of the delayed clock signal on signal path584, latch590outputs a logic low level signal on Dn1d signal path592and a logic high level signal on Dn2d signal path594. Latch590maintains the output signals on Dn1d signal path592and Dn2d signal path594until another evaluation is performed.

Table I below indicates the values for Dn1a, Dn2a, Dn1b, Dn2b, Dn1c, Dn2c, Dn1d, and Dn2d based on the value of VnM. A “0” indicates a logic low level and a “1” indicates a logic high level. The outputs indicating the process for nFET344are passed to OCD112or other circuits to adjust the circuits based on the process.

FIG. 16is a schematic diagram illustrating one embodiment of a reference circuit600for providing multiple reference signals for evaluating the process for a pFET. Reference circuit600includes current source604and resistors608,612,616, and619. Current source604is electrically coupled to VINT320through path602and resistor608through fastest process pFET reference voltage (VpRFF) signal path606. Resistor608is electrically coupled to resistor612through fast process pFET reference voltage (VpRF) signal path610. Resistor612is electrically coupled to resistor616through slow process pFET reference voltage (VpRS) signal path614. Resistor616is electrically coupled to resistor619through slowest process pFET reference voltage (VpRSS) signal path618. Resistor619is electrically coupled to common or ground224through path620. The sum of the resistances of resistors608,612,616, and619is substantially equal to the resistance of resistor410.

Reference circuit600provides four reference voltages to compare to VpMfrom test circuit150b. VpRSSindicates the slowest process for pFET408. VpRSindicates a slow process for pFET408, but faster than VpRSS. VpRFindicates a fast process for pFET408and VpRFFindicates the fastest process for pFET408. In other embodiments, reference circuit600includes more than four resistors to provide more than four reference voltages. Any suitable number of resistors to provide any suitable number of reference voltages can be provided.

FIG. 17is a block diagram illustrating one embodiment of an evaluation circuit621having multiple latches for evaluating the process for pFET408. Evaluation circuit621includes inverter chains622,626,642,646,662,666,682, and686, and latches630,650,670, and690. In one embodiment, inverter chains626,646,666, and686, are replaced with a single inverter having an output coupled to latches630,650,670, and690. Inverter chains622,626,642,646,662,666,682, and686are similar to inverter chain128. Latches630,650,670, and690are similar to latch140.

Inverter chain622is electrically coupled to VpRFFsignal path606, CLK signal path122, and latch630through signal path624. Inverter chain626is electrically coupled to VpMsignal path152b, CLK signal path122, and latch630through signal path628. Latch630is electrically coupled to pFET latch A data one (Dp1a) signal path632and pFET latch A data two (Dp2a) signal path634.

Inverter chain662is electrically coupled to VpRSsignal path614, CLK signal path122, and latch670through signal path664. Inverter chain666is electrically coupled to VpMsignal path152b, CLK signal path122, and latch670through signal path668. Latch670is electrically coupled to pFET latch C data one (Dp1c) signal path672and pFET latch C data two (Dp2c) signal path674.

Reference circuit600outputs the VpRFFsignal to inverter chain622through signal path606. The VpRFFsignal is received by inverter chain622and controls inverter chain622. Inverter chain622receives the CLK signal through CLK signal path122as an input. Based on the VpRFFsignal received from reference circuit600, the CLK signal is delayed as it propagates through inverter chain622. Inverter chain622outputs a delayed clock signal, which is proportional to the VpRFFsignal received from reference circuit600, to latch630through signal path624.

Test circuit150boutputs the VpMsignal to inverter chain626through signal path152b. The VpMsignal is received by inverter chain626and controls inverter chain626. Inverter chain626receives the CLK signal through CLK signal path122as an input. Based on the VpMsignal received from test circuit150b, the CLK signal is delayed as it propagates through inverter chain626. Inverter chain626outputs a delayed clock signal, which is proportional to the VpMsignal received from test circuit150b, to latch630through signal path628.

Latch630receives the delayed clock signal from inverter chain622through signal path624and the delayed clock signal from inverter chain626through signal path628. If the rising edge of the delayed clock signal on signal path624arrives to the input of latch630before the rising edge of the delayed clock signal on signal path628, latch630outputs a logic high level signal on Dp1a signal path632and a logic low level signal on Dp2a signal path634. If the rising edge of the delayed clock signal on signal path628arrives to the input of latch630before the rising edge of the delayed clock signal on signal path624, latch630outputs a logic low level signal on Dp1a signal path632and a logic high level signal on Dp2a signal path634. Latch630maintains the output signals on Dp1a signal path632and Dp2a signal path634until another evaluation is performed.

Reference circuit600outputs the VpRFsignal to inverter chain642through signal path610. The VpRFsignal is received by inverter chain642and controls inverter chain642. Inverter chain642receives the CLK signal through CLK signal path122as an input. Based on the VpRFsignal received from reference circuit600, the CLK signal is delayed as it propagates through inverter chain642. Inverter chain642outputs a delayed clock signal, which is proportional to the VpRFsignal received from reference circuit600, to latch650through signal path644.

Test circuit150boutputs the VpMsignal to inverter chain646through signal path152b. The VpMsignal is received by inverter chain646and controls inverter chain646. Inverter chain646receives the CLK signal through CLK signal path122as an input. Based on the VpMsignal received from test circuit150b, the CLK signal is delayed as it propagates through inverter chain646. Inverter chain646outputs a delayed clock signal, which is proportional to the VpMsignal received from test circuit150bto latch650through signal path648.

Latch650receives the delayed clock signal from inverter chain642through signal path644and the delayed clock signal from inverter chain646through signal path648. If the rising edge of the delayed clock signal on signal path644arrives to the input of latch650before the rising edge of the delayed clock signal on signal path648, latch650outputs a logic high level signal on Dp1b signal path652and a logic low level signal on Dp2b signal path654. If the rising edge of the delayed clock signal on signal path648arrives to the input of latch650before the rising edge of the delayed clock signal on signal path644, latch650outputs a logic low level signal on Dp1b signal path652and a logic high level signal on Dp2b signal path654. Latch650maintains the output signals on Dp1b signal path652and Dp2b signal path654until another evaluation is performed.

Reference circuit600outputs the VpRSsignal to inverter chain662through signal path614. The VpRSsignal is received by inverter chain662and controls inverter chain662. Inverter chain662receives the CLK signal through CLK signal path122as an input. Based on the VpRSsignal received from reference circuit600, the CLK signal is delayed as it propagates through inverter chain662. Inverter chain662outputs a delayed clock signal, which is proportional to the VpRSsignal received from reference circuit600, to latch670through signal path664.

Test circuit150boutputs the VpMsignal to inverter chain666through signal path152b. The VpMsignal is received by inverter chain666and controls inverter chain666. Inverter chain666receives the CLK signal through CLK signal path122as an input. Based on the VpMsignal received from test circuit150b, the CLK signal is delayed as it propagates through inverter chain666. Inverter chain666outputs a delayed clock signal, which is proportional to the VpMsignal received from test circuit150b, to latch670through signal path668.

Latch670receives the delayed clock signal from inverter chain662through signal path664and the delayed clock signal from inverter chain666through signal path668. If the rising edge of the delayed clock signal on signal path664arrives to the input of latch670before the rising edge of the delayed clock signal on signal path668, latch670outputs a logic high level signal on Dp1c signal path672and a logic low level signal on Dp2c signal path674. If the rising edge of the delayed clock signal on signal path668arrives to the input of latch670before the rising edge of the delayed clock signal on signal path664, latch670outputs a logic low level signal on Dp1c signal path672and a logic high level signal on Dp2c signal path674. Latch670maintains the output signals on Dp1c signal path672and Dp2c signal path674until another evaluation is performed.

Reference circuit600outputs the VpRSSsignal to inverter chain682through signal path618. The VpRSSsignal is received by inverter chain682and controls inverter chain682. Inverter chain682receives the CLK signal through CLK signal path122as an input. Based on the VpRSSsignal received from reference circuit600, the CLK signal is delayed as it propagates through inverter chain682. Inverter chain682outputs a delayed clock signal, which is proportional to the VpRSSsignal received from reference circuit600, to latch690through signal path684.

Test circuit150boutputs the VpMsignal to inverter chain686through signal path152b. The VpMsignal is received by inverter chain686and controls inverter chain686. Inverter chain686receives the CLK signal through CLK signal path122as an input. Based on the VpMsignal received from test circuit150b, the CLK signal is delayed as it propagates through inverter chain686. Inverter chain686outputs a delayed clock signal, which is proportional to the VpMsignal received from test circuit150b, to latch690through signal path688.

Latch690receives the delayed clock signal from inverter chain682through signal path684and the delayed clock signal from inverter chain686through signal path688. If the rising edge of the delayed clock signal on signal path684arrives to the input of latch690before the rising edge of the delayed clock signal on signal path688, latch690outputs a logic high level signal on Dp1d signal path692and a logic low level signal on Dp2d signal path694. If the rising edge of the delayed clock signal on signal path688arrives to the input of latch690before the rising edge of the delayed clock signal on signal path684, latch690outputs a logic low level signal on Dp1d signal path692and a logic high level signal on Dp2d signal path694. Latch690maintains the output signals on Dp1d signal path692and Dp2d signal path694until another evaluation is performed.

Table II below indicates the values for Dp1a, Dp2a, Dp1b, Dp2b, Dp1c, Dp2c, Dp1d, and Dp2d based on the value of VpM. A “0” indicates a logic low level and a “1” indicates a logic high level. The outputs indicating the process for pFET408are passed to OCD112or other circuits to adjust the circuits based on the process.

The evaluation circuits described herein enable high speed evaluation of the process and voltage characteristics of a semiconductor chip. The information obtained from the evaluation circuits can be used to adjust the semiconductor chip to compensate for any effects due to variations in the process or voltage characteristics.