Method for planarizing semiconductor devices

A method for planarizing semiconductor devices, wherein the method comprises steps as follows: At least one patterned metal layer is formed on a substrate. A material layer having a first area and a second area is provided on the patterned metal layer and the substrate, in which there is a step height existing between the first area and the second area. A first polishing process having a first selection ratio of relative speeds for removing the material layer at the first area to that at the second area is then performed on the material layer. Subsequently, a second polishing process having a second selection ratio of relative speeds for removing the material layer at the first area to that at the second area is performed on the material layer, and the second selection ratio is greater than the first selection ratio.

FIELD OF THE INVENTION

The present invention relates to a method for fabricating semiconductor devices, and more particularly to a method for planarizing semiconductor devices.

BACKGROUND OF THE INVENTION

A semiconductor integrated circuit is typically formed on a substrate by the sequential deposition of conductive, semiconductor or insulation material layers on a silicon wafer. After each material layer is deposited, the material layer is etched to create circuitry features. As a series of material layers are sequentially deposited and etched, the outer or uppermost surface of the semiconductor integrated circuit, i.e., the exposed surface of the material layer becomes increasingly non-planar. This non-planar surface presents problems in the photolithographic steps of the semiconductor integrated circuit fabrication process. Therefore, there is a need to periodically planarize the exposed material layers.

Chemical mechanical polishing (CMP) process is one accepted method of planarization. This planarization method typically requires polishing slurry, including at least one chemically reactive agent, and abrasive particles supplied to the exposed surface of the material layer against a rotating polishing pad. However, there are problems and drawbacks in CMP process, for example, since variations found in the initial thickness of the material layers, the slurry composition, the polishing pad condition, the relative removing speeds between the polishing pad and the different material layers, and the load on the substrate can cause variations in the material removal rate, thus it is difficult to determine whether the polishing process has reached completion, i.e., whether a material layer has been planarized to a desired flatness or thickness in order to globally planarize the semiconductor integrated circuit, whereby merely a local planarization of semiconductor integrated circuit is thereby accomplished, and step height that may adversely effect the performance of the subsequent process for fabricating the semiconductor integrated circuit occurs between the local planarization area and the peripheral area that is not equally or sufficiently planarized.

Therefore, there is a need of providing an improved method for planarizaing semiconductor devices to obviate the drawbacks encountered from the prior art.

SUMMARY OF THE INVENTION

In accordance with one aspect, the present invention provides a method for planarizing semiconductor devices, wherein the method comprises steps as follows: A material layer having a first area and a second area is firstly provided, wherein there is a step height existing between the first area and the second area. A first polishing process is then performed on the material layer, wherein the first polishing process has a first selection ratio of relative speeds for removing the material layer at the first area to that at the second area. Subsequently, a second polishing process is performed on the material layer, wherein the second polishing process has a second selection ratio of relative speeds for removing the material layer at the first area to that at the second area, and the second selection ratio is greater than the first selection ratio.

In one embodiment of the present invention, the first polishing process comprises a first slurry having silicon dioxide (SiO2) ranging from 0.95% to 1.05% by weight.

In one embodiment of the present invention, the first selection ratio is about 1:7.

In one embodiment of the present invention, the second polishing process comprises a second slurry having cerium dioxide (CeO2) ranging from 1.45% to 1.85% by weight.

In one embodiment of the present invention, the second slurry further comprises a buffer reagent ranging from 0.95% to 1.05% by weight.

In one embodiment of the present invention, the buffer reagent comprises a chemical activator, an inhibitor polymer or a combination thereof.

In one embodiment of the present invention, the second selection ratio is about 1:30.

In one embodiment of the present invention, each of the first polishing process and the second polishing process utilizing an optical monitoring system to determine an end-point corresponding to the first polishing process and the second polishing process, respectively.

In one embodiment of the present invention, the first polishing process is ended when the step height is reduced by half.

In one embodiment of the present invention, the second polishing process is ended when the step height is equal to or reduced to 0.

In one embodiment of the present invention, the first polishing process is terminated or ended after the first polishing process has lasted or endured for a predetermined first polishing time.

In one embodiment of the present invention, the second polishing process is end after the second polishing process has lasted or endured for a predetermined second polishing time.

In one embodiment of the present invention, the material layer is a dielectric layer formed on a substrate.

In one embodiment of the present invention, the step of providing the material layer further comprises forming a patterned metal layer between the dielectric layer and the substrate.

In accordance with the aforementioned embodiments of the present invention, a method for planarizing a semiconductor device is provided, wherein at least two polish processes using different slurries are performed to planarize a material layer of a semiconductor device that has a first area, a second area and a step height existing there between, wherein the first polishing process has a first selection ratio of relative speeds for removing the material layer at the first area to that at the second area, and a second selection ratio of relative speeds for removing the material layer at the first area to that at the second area; and the second selection ratio is greater than the first selection ratio.

Since most of the material layer can be rapidly removed by the first polishing process having a lower selection ratio for removing the material layer at the first area and at the second area, respectively; and the step height existing between the first area and the second area can be diminished or lowered by the second polishing process having a higher selection ratio for removing the material layer at the first area and at the second area, respectively, thus the processing time can be significantly reduced, and the end point of the planarization can be determined more easily in comparison with the traditional planarization process. Accordingly, the material layer can be globally planarized, and the performance of the subsequent process for forming the semiconductor devices can be improved.

In addition, because it is not necessary to form a polishing stop layer to determine whether the polishing process is complete, thus the processing cost can be reduced due to the omission of steps and material for forming the same.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

A method for planarizing semiconductor devices is provided by the present invention to globally planarize a material layer of a semiconductor device, whereby the subsequent process for forming the semiconductor devices can be improved. The present invention will now be described more specifically with reference to the following embodiments. It is to be noted that the following descriptions of preferred embodiments of this invention are presented herein for purpose of illustration and description only. It is not intended to be exhaustive or to be limited to the precise form disclosed.

FIGS. 1A-1Dare cross-sectional views of the processing structures for fabricating a semiconductor device100in accordance with one embodiment of the present invention, wherein the method for fabricating a semiconductor device100comprises steps as follows:

Firstly, a substrate101having at least one patterned metal layer102and at least one material layer103formed thereon is provided. In some embodiments of the present invention, the substrate101is a silicon substrate. The patterned metal layer102comprises a plurality of openings102aused to expose the substrate101in order to define a plurality of metal lines102bserving as interconnections of the semiconductor device100on the substrate101. The material layer103is a dielectric layer that is blanketed over the substrate101and the patterned metal layer102. In the present embodiment, the material layer103is made of silicon dioxide deposited on and conforms to the substrate101and the patterned metal layer102. Because the patterned metal layer102formed on the substrate101has an uneven topography, thus the material layer103conforming to the patterned metal layer102also has an uneven topography (seeFIG. 1A).

In some embodiments, the material layer103with the uneven topography can be divided into at least two areas, and there is a step height that exists between these at least two areas. For example, in the present embodiment, the portion of the material layer103overlying on the metal lines102bis referred as to a first area103a, and the portion of the material layer103overlying on the openings102ais referred as to a second area103b, and there exists a step height H, i.e. the height difference measured from the top surface of the material layer103to the base of the material layer103at between the first area103aand the second area103b. Since this non-planar surface of the material layer103may present problems in the subsequent photolithographic steps for fabricating the semiconductor device100, thus a planarization process is required.

FIG. 3is a block diagram illustrating a planarization process for reducing the step height H which exists between the first area103aand the second area103bof the material layer103in accordance with one embodiment of the present invention.

Referring to step301, a first polishing process104having a first selection ratio for removing the material layer103at the first area103aand at the second area103b, respectively, is performed on the material layer103(seeFIG. 1B). In some embodiments of the present invention, the first polishing process104has different speeds for removing the material layer103at the first area103aand at the second area103b, wherein the ratio of the relative speeds for removing the material layer103at the first area103ato that at the second area103bis referred as to a first selection ratio.

The first polishing process104preferably is a CMP process utilizing slurry105having silicon dioxide (SiO2) supplied to an exposed surface of the material layer103against a rotating polishing pad106. In the present embodiment, the slurry105utilized by the first polishing process104comprises SiO2ranging from 0.95% to 1.05% by weight, and the first selection ratio is about 1:7.

During the first polishing process104, an end-point determining step is performed to determine whether the first polishing process104is completed. In some embodiments of the present invention, the step height H that is diminished or reduced gradually by the first polish process104may serve as a reference in determining the endpoint of the first polishing process104. For example, in one embodiment of the present invention, the first polishing process104is ended when half of the step height H (measured at the start thereof) is reduced by polishing.

In some embodiments of the present invention, the remaining step height H can be estimated by considering the correlation between the polishing time of the first polishing process104and its polishing speed (removal rate) for removing the material layer103at the first area103a. As a result, the endpoint of the first polishing process104can be determined by referencing the estimated step height H. In the present embodiment, the first polishing process104is ended after the first polishing process104lasting for a predetermined first polishing time upon when the step height H is removed by half.

Alternatively, in some other embodiment (seeFIG. 2), an optical monitoring system200includes a light source201and a light detector202is adapted to detect the thickness of the material layer103and/or the remaining step height H in determining the endpoint of the first polishing process104. A spectrum of white light203provided from the light source201, passing through an optical access204, such as an aperture or a window formed through the polishing pad206, is reflected from the material layer103back through the optical access204, and travels to the light detector202; the thickness of the material layer103and/or the remaining step height H can be estimated by measuring the spectrum of white light203received by the light detector202. As a result, the endpoint of the first polishing process104can be determined by referencing the step height H. Since, the method for estimating a thickness of a polished layer has been well known, thus the detailed steps for performing the same will not be redundantly described, and for clarification and brevity, identical elements are designated by identical numeral references.

Referring to step302ofFIG. 3, a second polishing process107having a second selection ratio for removing the material layer103at the first area103aand at the second area103b, respectively, is performed on the material layer103(also seeFIG. 1C). In some embodiments of the present invention, the second polishing process107has different speeds for removing the material layer103located at the first area103aand at the second area103b, wherein the ratio of the relative speeds for removing the material layer103at the first area103ato that at the second area103bis referred as to a second selection ratio, wherein the second selection ratio of the second polishing process107is greater than the first selection ratio of the first polishing process104.

The second polishing process107preferably is a CMP process utilizing slurry109having cerium dioxide (CeO2) supplied to the exposed surface of the material layer103against a rotating polishing pad108. In some embodiments of the present invention, the slurry109utilized by the second polishing process107comprises CeO2 ranging from 1.45% to 1.85% by weight. In the present embodiment, the second polishing process107further comprises a buffer reagent ranging from 0.95% to 1.05% by weight. The buffer reagent preferably comprises a re-dispersible polymer. In the present embodiment, buffer reagent comprise cAiPTM provided by Du Pont Air Products NanoMaterials L.L.C., and the second selection ratio is about 1:30.

During the second polishing process107, an end-point determining step is performed to determine whether the second polishing process107is completed. In the embodiments of the present invention, the step height H that is diminished or reduced gradually by the second polish process107may serve as a reference in determining the endpoint of the second polishing process107. For example, in one embodiment of the present invention, the second polishing process107is ended until when the step height H is equal to 0.

In one embodiments of the present invention, the remaining step height H can be estimated by considering the correlation between the polishing time of the second polishing process107and its polishing speed (removal rate) for removing the material layer103at the first area103a. As a result, the endpoint of the second polishing process107can be determined by referencing the estimated step height H. In the present embodiment, the second polishing process107is ended after lasting for a predetermined second polish time until when the step height H is equal to 0.

Similarly, the optical monitoring system200depicted inFIG. 2can be adapted to detect the thickness of the material layer103and/or the remaining step height H in determining the endpoint of the second polishing process107.

Subsequently referring to step303ofFIG. 3, a global polishing process is performed to globally polish the planarized material layer103without the step height H existing between the first area103aand the second area103b. In some embodiments of the present invention, the global polishing process is a continuing CMP process of the second polishing process107utilizing the same slurry that the second polishing process107utilizes (such as the slurry109).

Thereinafter, at least one subsequent process, such as a planarization process (not shown), is performed on the globally planarized surface of the material layer103(seeFIG. 1D), meanwhile the semiconductor device100is completed.

In accordance with the aforementioned embodiments of the present invention, a method for planarizing a semiconductor device is provided, wherein at least two polish processes using different slurries are performed to planarize a material layer of a semiconductor device that has a first area, a second area and a step height existing therebetween, wherein the first polishing process has a first selection ratio of relative speeds for removing the material layer at the first area to that at the second area, and a second selection ratio of relative speeds for removing the material layer at the first area to that at the second area; and the second selection ratio is greater than the first selection ratio.

Since most of the material layer can be rapidly removed by the first polishing process having a lower selection ratio for removing the material layer at the first area and at the second area, respectively; and the step height existing between the first area and the second area can be reduced or lowered by the second polishing process having a higher selection ratio for removing the material layer at the first area and at the second area, respectively, thus the processing time can be significantly reduced and the end point of the planarization can be determined more easily in comparison with the traditional planarization process. Accordingly, the material layer can be globally planarized, and the performance of the subsequent process for forming the semiconductor devices can be improved.

In addition, because it is not necessary to form a polishing stop layer to determine whether the polishing process is complete, thus the processing cost can be reduced due to the omission of steps and material for forming the same.