Interface circuit

According to an embodiment, an interface circuit is provided with an output buffer which generates an output waveform on the basis of the ON/OFF operation of a transistor and a driver circuit which drives the transistor and is capable of independently changing a turn-ON speed and a turn-OFF speed of the transistor.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is based upon and claims the benefit of priority from Japanese Patent Application No. 2012-48889, filed on Mar. 6, 2012; the entire contents of which are incorporated herein by reference.

FIELD

Embodiments described herein relate generally to an interface circuit.

BACKGROUND

In semiconductor chips such as NAND flash memories, the speed of an interface which exchanges data with a controller chip and the like has been increased. Such an interface is used in various forms, so that a plurality of chips are stacked and used, a plurality of packages are used by being connected to the same bus, or different wiring is used between a memory chip and a controller chip which controls the memory chip. In order to achieve a desired high-speed operation under such various environments, an output buffer is designed to optimize an output waveform by controlling the slew rate of an off-chip driver (OCD).

DETAILED DESCRIPTION

According to an interface circuit of an embodiment, an output buffer and a driver circuit are provided. The output buffer generates an output waveform on the basis of the ON/OFF operation of a transistor. The driver circuit drives the transistor and is capable of independently changing a turn-ON speed and a turn-OFF speed of the transistor.

Hereinafter, an interface circuit according to embodiments will be described with reference to the drawings. The invention is not limited to the embodiments.

First Embodiment

FIG. 1is a block diagram schematically illustrating the configuration of an interface circuit according to a first embodiment.

InFIG. 1, the interface circuit is provided with an output buffer1which generates an output waveform and a driver circuit2which drives the output buffer1. The output buffer1is provided with a P-channel field-effect transistor PM and an N-channel field-effect transistor NM. Here, the P-channel field-effect transistor PM and the N-channel field-effect transistor NM are connected to each other in series, and a drain terminal of the P-channel field-effect transistor PM and a drain terminal of the N-channel field-effect transistor NM are connected to a pad electrode PD. The size of the P-channel field-effect transistor PM can be increased more than that of the N-channel field-effect transistor NM.

The driver circuit2is provided with a P-driver circuit3P which drives the P-channel field-effect transistor PM and an N-driver circuit3N which drives the N-channel field-effect transistor NM. The P-driver circuit3P is provided with a P-slew rate control unit4P and a P-reset rate control unit5P, and the N-driver circuit3N is provided with an N-slew rate control unit4N and an N-reset rate control unit5N.

The P-slew rate control unit4P can turn on the P-channel field-effect transistor PM by pulling down a gate potential of the P-channel field-effect transistor PM on the basis of an input voltage IN. In addition, the P-slew rate control unit4P can change a turn-ON speed of the P-channel field-effect transistor PM on the basis of an intermediate voltage FN.

Here, the P-slew rate control unit4P is provided with a P-channel field-effect transistor P11and N-channel field-effect transistors N11and N12. The P-channel field-effect transistor P11and the N-channel field-effect transistor N11are connected to each other in series. In addition, a drain terminal of the P-channel field-effect transistor P11and a drain terminal of the N-channel field-effect transistor N11are connected to a gate terminal of the P-channel field-effect transistor PM through the N-channel field-effect transistor N12. An input voltage IN is applied to a gate terminal of the P-channel field-effect transistor P11and a gate terminal of the N-channel field-effect transistor N11, and an intermediate voltage FN is applied to a gate terminal of the N-channel field-effect transistor N12. The intermediate voltage FN can be set so that the N-channel field-effect transistor N12acts as a resistance.

The P-reset rate control unit5P can turn off the P-channel field-effect transistor PM by pulling up a gate potential of the P-channel field-effect transistor PM on the basis of an input voltage IN. In addition, the P-reset rate control unit5P can change a turn-OFF speed of the P-channel field-effect transistor PM on the basis of an intermediate voltage FPR.

Here, the P-reset rate control unit5P is provided with P-channel field-effect transistors P12and P13. The P-channel field-effect transistors P12and P13are connected to each other in series. In addition, a drain terminal of the P-channel field-effect transistor P13is connected to the gate terminal of the P-channel field-effect transistor PM. An input voltage IN is applied to a gate terminal of the P-channel field-effect transistor P12, and an intermediate voltage FPR is applied to a gate terminal of the P-channel field-effect transistor P13. The intermediate voltage FPR can be set so that the P-channel field-effect transistor P13acts as a resistance.

The N-slew rate control unit4N can turn on the N-channel field-effect transistor NM by pulling up a gate potential of the N-channel field-effect transistor NM on the basis of an input voltage IN. In addition, the N-slew rate control unit4N can change a turn-ON speed of the N-channel field-effect transistor NM on the basis of an intermediate voltage FP.

Here, the N-slew rate control unit4N is provided with P-channel field-effect transistors P21and P22and an N-channel field-effect transistor N21. The P-channel field-effect transistor P21and the N-channel field-effect transistor N21are connected to each other in series. In addition, a drain terminal of the P-channel field-effect transistor P21and a drain terminal of the N-channel field-effect transistor N21are connected to a gate terminal of the N-channel field-effect transistor NM through the P-channel field-effect transistor P22. An input voltage IN is applied to a gate terminal of the P-channel field-effect transistor P21and a gate terminal of the N-channel field-effect transistor N21, and an intermediate voltage FP is applied to a gate terminal of the P-channel field-effect transistor P22. The intermediate voltage FP can be set so that the P-channel field-effect transistor P22acts as a resistance.

The N-reset rate control unit5N can turn off the N-channel field-effect transistor NM by pulling down a gate potential of the N-channel field-effect transistor NM on the basis of an input voltage IN. In addition, the N-reset rate control unit5N can change a turn-OFF speed of the N-channel field-effect transistor NM on the basis of an intermediate voltage FNR.

Here, the N-reset rate control unit5N is provided with N-channel field-effect transistors N22and N23. The N-channel field-effect transistors N22and N23are connected to each other in series. In addition, a drain terminal of the N-channel field-effect transistor N22is connected to the gate terminal of the N-channel field-effect transistor NM. An input voltage IN is applied to a gate terminal of the N-channel field-effect transistor N23, and an intermediate voltage FNR is applied to a gate terminal of the N-channel field-effect transistor N22. The intermediate voltage FNR can be set so that the N-channel field-effect transistor N22acts as a resistance.

In the P-driver circuit3P, when an input voltage IN rises, the P-channel field-effect transistors P11and P12are turned off, and the N-channel field-effect transistor N11is turned on. Therefore, the gate potential of the P-channel field-effect transistor PM is pulled down through the N-channel field-effect transistors N11and N12, and the P-channel field-effect transistor PM is turned on. At this time, the gradient of the fall-off of the gate potential of the P-channel field-effect transistor PM is adjusted through the N-channel field-effect transistor N12, and the turn-ON speed of the P-channel field-effect transistor PM is adjusted.

In addition, in the N-driver circuit3N, when an input voltage IN rises, the P-channel field-effect transistor P21is turned off, and the N-channel field-effect transistors N21and N23are turned on. Therefore, the gate potential of the N-channel field-effect transistor NM is pulled down through the N-channel field-effect transistors N22and N23, and the N-channel field-effect transistor NM is turned off. At this time, the gradient of the fall-off of the gate potential of the N-channel field-effect transistor NM is adjusted through the N-channel field-effect transistor N22, and the turn-OFF speed of the N-channel field-effect transistor NM is adjusted.

On the other hand, in the P-driver circuit3P, when an input voltage IN falls, the P-channel field-effect transistors P11and P12are turned on, and the N-channel field-effect transistor N11is turned off. Therefore, the gate potential of the P-channel field-effect transistor PM is pulled up through the P-channel field-effect transistors P12and P13, and the P-channel field-effect transistor PM is turned off. At this time, the gradient of the fall-off of the gate potential of the P-channel field-effect transistor PM is adjusted through the P-channel field-effect transistor P13, and the turn-OFF speed of the P-channel field-effect transistor PM is adjusted.

In addition, in the N-driver circuit3N, when an input voltage IN falls, the P-channel field-effect transistor P21is turned on and the N-channel field-effect transistors N21and N23are turned off. Therefore, the gate potential of the N-channel field-effect transistor NM is pulled up through the P-channel field-effect transistor P21, and the N-channel field-effect transistor NM is turned on. At this time, the gradient of the rise of the gate potential of the N-channel field-effect transistor NM is adjusted through the P-channel field-effect transistor P22, and the turn-ON speed of the N-channel field-effect transistor NM is adjusted.

Here, by providing the P-slew rate control unit4P and the N-slew rate control unit4N, the turn-ON speeds of the P-channel field-effect transistor PM and the N-channel field-effect transistor NM can be adjusted, and by providing the P-reset rate control unit5P and the N-reset rate control unit5N, the turn-OFF speeds of the P-channel field-effect transistor PM and the N-channel field-effect transistor NM can be adjusted. Therefore, the P-channel field-effect transistor PM and the N-channel field-effect transistor NM can be turned on/off gradually, and an immediate change in the current flowing to the pad electrode PD can be suppressed. As a result, even when external wiring connected to the pad electrode PD contains an inductance component, noise caused in the output waveform can be reduced.

FIGS. 2A to 2Care diagrams illustrating a waveform when changing the reset rate of a driver output of the interface circuit ofFIG. 1.

InFIG. 2A, when the intermediate voltage FN ofFIG. 1is reduced, the gradient of the fall-off of the gate potential of the P-channel field-effect transistor PM becomes gentle. Therefore, as illustrated inFIG. 2C, the gradient of the rise of the output waveform of the pad electrode PD becomes gentle. At this time, in order to reduce OFF-noise when the N-channel field-effect transistor NM is turned off, when the intermediate voltage FNR ofFIG. 1is reduced, the gradient of the fall-off of the gate potential of the N-channel field-effect transistor NM becomes gentle as illustrated inFIG. 2.

Here, when the gradient of the fall-off of the gate potential of the N-channel field-effect transistor NM becomes gentle, the P-channel field-effect transistor PM is turned on while the N-channel field-effect transistor NM is not turned off, and this leads to an increase in the through current. Therefore, a time lag may be provided between an input voltage IN which is input to the P-driver circuit3P and an input voltage IN which is input to the N-driver circuit3N so that the P-channel field-effect transistor PM and the N-channel field-effect transistor NM are not turned on at the same time.

FIG. 3is a block diagram illustrating a configuration in which the interface circuit ofFIG. 1has a time lag generation circuit attached thereto.

InFIG. 3, a time lag generation circuit7is connected to the front stage of the interface circuit ofFIG. 1, and a level shifter6is connected to the front stage of the time lag generation circuit7. An input signal DI is level-shifted by the level shifter6, and is then input to the time lag generation circuit7. In the time lag generation circuit7, input voltages IN1and IN2are generated and output to the P-driver circuit3P and the N-driver circuit3N, respectively, to add a period of time in order to turn off both of the P-channel field-effect transistor PM and the N-channel field-effect transistor NM at the same time in accordance with the input signal DI.

FIG. 4is a circuit diagram illustrating an example of the configuration of the time lag generation circuit ofFIG. 3.

InFIG. 4, the time lag generation circuit7is provided with a NAND circuit G1, a NOR circuit G2, and inverters V1to V6. An input signal DI sequentially passes through the inverters V1and V2, and is input to the NAND circuit G1and the NOR circuit G2. In addition, an output of the NAND circuit G1is input to the NOR circuit G2through the inverter V3. In addition, an output of the NOR circuit G2is input to the NAND circuit G1through the inverter V4.

In the NAND circuit G1, NAND operation of the output of the inverter V2and the output of the inverter V4is performed, and the result thereof is output to the P-driver circuit3P through the inverter V5. In addition, in the NOR circuit G2, NOR operation of the output of the inverter V2and the output of the inverter V3is performed, and the result thereof is output to the N-driver circuit3N through the inverter V6.

Second Embodiment

FIG. 5is a block diagram schematically illustrating the configuration of an interface circuit according to a second embodiment.

InFIG. 5, in this interface circuit, a driver circuit12is provided in place of the driver circuit2ofFIG. 1.

The driver circuit12is provided with a P-driver circuit13P which drives a P-channel field-effect transistor PM and an N-driver circuit13N which drives an N-channel field-effect transistor NM. The P-driver circuit13P is provided with a P-slew rate control unit4P, a P-reset rate control unit15P, and an inverter PV, and the N-driver circuit13N is provided with an N-slew rate control unit4N, an N-reset rate control unit15N, and an inverter NV.

The P-reset rate control unit15P can turn off the P-channel field-effect transistor PM by pulling up a gate potential of the P-channel field-effect transistor PM on the basis of an input voltage IN. In addition, the P-reset rate control unit15P can change a turn-OFF speed of the P-channel field-effect transistor PM on the basis of a selection signal CTP.

Here, the P-reset rate control unit15P is provided with P-channel field-effect transistors P33and P34and a NAND circuit GP. The P-channel field-effect transistors P33and P34are connected to each other in parallel. In addition, drain terminals of the P-channel field-effect transistors P33and P34are connected to a gate terminal of the P-channel field-effect transistor PM. An input voltage IN is applied to a gate terminal of the P-channel field-effect transistor P33through the inverter PV, and an output of the NAND circuit GP is applied to a gate terminal of the P-channel field-effect transistor P34. An input voltage IN and a selection signal CTP are input to the NAND circuit GP.

The selection signal CTP can be made active on the basis of a power-supply voltage and an operation speed of the driver circuit12. For example, when a power-supply voltage of the driver circuit12corresponds to two power supplies of 1.8 V and 3.3 V, in the case of the 1.8-V power supply, the selection signal CTP is made active, and thus the gate potential of the P-channel field-effect transistor PM can be pulled up by the P-channel field-effect transistors P33and P34, and in the case of the 3.3-V power supply, the selection signal CTP is made inactive, and thus the gate potential of the P-channel field-effect transistor PM can be pulled up by the P-channel field effect transistor P33.

The inverter PV is provided with a P-channel field-effect transistor P32and an N-channel field-effect transistor N32. Here, the P-channel field-effect transistor P32and the N-channel field-effect transistor N32are connected to each other in series, and a drain terminal of the P-channel field-effect transistor P32and a drain terminal of the N-channel field-effect transistor N32are connected to gate terminals of the P-channel field-effect transistors P11and P33and a gate terminal of the N-channel field-effect transistor N11. An input voltage IN is applied to a gate terminal of the P-channel field-effect transistor P32and a gate terminal of the N-channel field-effect transistor N32.

The N-reset rate control unit15N can turn off the N-channel field-effect transistor NM by pulling down a gate potential of the N-channel field-effect transistor NM on the basis of an input voltage IN. In addition, the N-reset rate control unit15N can change a turn-OFF speed of the N-channel field-effect transistor NM on the basis of a selection signal CTN.

Here, the N-reset rate control unit15N is provided with N-channel field-effect transistors N43and N44and a NOR circuit GN. The N-channel field-effect transistors N43and N44are connected to each other in parallel. In addition, drain terminals of the N-channel field-effect transistors N43and N44are connected to a gate terminal of the N-channel field-effect transistor NM. An input voltage IN is applied to a gate terminal of the N-channel field-effect transistor N43through the inverter NV, and an output of the NOR circuit GN is applied to a gate terminal of the N-channel field-effect transistor N44. An input voltage IN and a selection signal CTN are input to the NOR circuit GN.

The selection signal CTN can be made active on the basis of a power-supply voltage and an operation speed of the driver circuit12. For example, when a power-supply voltage of the driver circuit12corresponds to two power supplies of 1.8 V and 3.3 V, in the case of the 1.8-V power supply, the selection signal CTN is made active, and thus the gate potential of the N-channel field-effect transistor NM can be pulled down by the N-channel field-effect transistors N43and N44, and in the case of the 3.3-V power supply, the selection signal CTN is made inactive, and thus the gate potential of the N-channel field-effect transistor NM can be pulled down by the N-channel field effect transistor N43.

The inverter NV is provided with a P-channel field-effect transistor P42and an N-channel field-effect transistor N42. Here, the P-channel field-effect transistor P42and the N-channel field-effect transistor N42are connected to each other in series, and a drain terminal of the P-channel field-effect transistor P42and a drain terminal of the N-channel field-effect transistor N42are connected to a gate terminal of the P-channel field-effect transistor P21and gate terminals of the N-channel field-effect transistors N21and N43. An input voltage IN is applied to a gate terminal of the P-channel field-effect transistor P42and a gate terminal of the N-channel field-effect transistor N42.

In the P-driver circuit13P, when an input voltage IN falls, the P-channel field-effect transistors P11and P33are turned off and the N-channel field-effect transistor N11is turned on. Therefore, the gate potential of the P-channel field-effect transistor PM is pulled down through the N-channel field-effect transistors N11and N12, and the P-channel field-effect transistor PM is turned on. At this time, the gradient of the fall-off of the gate potential of the P-channel field-effect transistor PM is adjusted through the N-channel field-effect transistor N12, and the turn-ON speed of the P-channel field-effect transistor PM is adjusted.

In addition, in the N-driver circuit13N, when an input voltage IN falls, the P-channel field-effect transistor P21is turned off and the N-channel field-effect transistors N21and N43are turned on. Therefore, the gate potential of the N-channel field-effect transistor NM is pulled down through the N-channel field-effect transistor N43, and the N-channel field-effect transistor NM is turned off. At this time, the N-channel field-effect transistor N44is turned on in response to a selection signal CTN. Therefore, the gradient of the fall-off of the gate potential of the N-channel field-effect transistor NM is adjusted through the N-channel field-effect transistor N44in response to the selection signal CTN, and the turn-OFF speed of the N-channel field-effect transistor NM is adjusted.

Here, in order to adjust the turn-OFF speed of the N-channel field-effect transistor NM, the number of the N-channel field-effect transistors N43and N44which pull down the gate potential of the N-channel field-effect transistor NM is changed, and thus it is possible to prevent an excessive load from being applied in series to the N-channel field-effect transistors N43and N44, and it is possible to suppress an increase in the sizes of the N-channel field-effect transistors N43and N44.

On the other hand, in the P-driver circuit13P, when an input voltage IN rises, the P-channel field-effect transistors P11and P33are turned on, and the N-channel field-effect transistor N11is turned off. Therefore, the gate potential of the P-channel field-effect transistor PM is pulled up through the P-channel field-effect transistor P33, and the P-channel field-effect transistor PM is turned off. At this time, the P-channel field-effect transistor P34is turned on in response to a selection signal CTP. Therefore, the gradient of the rise of the gate potential of the P-channel field-effect transistor PM is adjusted through the P-channel field-effect transistor P34in response to the selection signal CTP, and the turn-OFF speed of the P-channel field-effect transistor PM is adjusted.

Here, in order to adjust the turn-OFF speed of the P-channel field-effect transistor PM, the number of the P-channel field-effect transistors P33and P34which pull up the gate potential of the P-channel field-effect transistor PM is changed, and thus it is possible to prevent an excessive load from being applied in series to the P-channel field-effect transistors P33and P34, and it is possible to suppress an increase in the sizes of the P-channel field-effect transistors P33and P34.

In addition, in the N-driver circuit13N, when an input voltage IN rises, the P-channel field-effect transistor P21is turned on, and the N-channel field-effect transistors N21and N43are turned off. Therefore, the gate potential of the N-channel field-effect transistor NM is pulled up through the P-channel field-effect transistors P21and P22, and the N-channel field-effect transistor NM is turned on. At this time, the gradient of the rise of the gate potential of the N-channel field-effect transistor NM is adjusted through the P-channel field-effect transistor P22, and the turn-ON speed of the N-channel field-effect transistor NM is adjusted.

Third Embodiment

FIG. 6is a block diagram schematically illustrating the configuration of an interface circuit according to a third embodiment.

InFIG. 6, in this interface circuit, a driver circuit22is provided in place of the driver circuit12ofFIG. 5.

The driver circuit22is provided with a P-driver circuit23P which drives a P-channel field-effect transistor PM and an N-driver circuit23N which drives an N-channel field-effect transistor NM. In the P-driver circuit23P, a P-reset rate control unit25P is provided in place of the P-reset rate control unit15P. In the N-driver circuit23N, an N-reset rate control unit25N is provided in place of the N-reset rate control unit15N.

The P-reset rate control unit25P can turn off the P-channel field-effect transistor PM by pulling up a gate potential of the P-channel field-effect transistor PM on the basis of an input voltage IN. In addition, the P-reset rate control unit25P can change a turn-OFF speed of the P-channel field-effect transistor PM on the basis of selection signals CTP1and CTP2.

Here, the P-reset rate control unit25P is provided with P-channel field-effect transistors P33to P35and NAND circuits GP1and GP2. The P-channel field-effect transistors P33to P35are connected to each other in parallel. In addition, drain terminals of the P-channel field-effect transistors P33to P35are connected to a gate terminal of the P-channel field-effect transistor PM. An input voltage IN is applied to a gate terminal of the P-channel field-effect transistor P33through an inverter PV, an output of the NAND circuit GP1is applied to a gate terminal of the P-channel field-effect transistor P34, and an output of the NAND circuit GP2is applied to a gate terminal of the P-channel field-effect transistor P35. An input voltage IN and a selection signal CTP1are input to the NAND circuit GP1, and an input voltage IN and a selection signal CTP2are input to the NAND circuit GP2. Selection signals CTP1and CTP2can be made active on the basis of a power-supply voltage and an operation speed of the driver circuit22. The values of the power-supply voltage and the operation speed are memorized in registers.

The N-reset rate control unit25N can turn off the N-channel field-effect transistor NM by pulling down a gate potential of the N-channel field-effect transistor NM on the basis of an input voltage IN. In addition, the N-reset rate control unit25N can change a turn-OFF speed of the N-channel field-effect transistor NM on the basis of selection signals CTN1and CTN2.

Here, the N-reset rate control unit25N is provided with N-channel field-effect transistors N43to N45and NOR circuits GN1and GN2. The N-channel field-effect transistors N43to N45are connected to each other in parallel. In addition, drain terminals of the N-channel field-effect transistors N43to N45are connected to a gate terminal of the N-channel field-effect transistor NM. An input voltage IN is applied to a gate terminal of the N-channel field-effect transistor N43through an inverter NV, an output of the NOR circuit GN1is applied to a gate terminal of the N-channel field-effect transistor N44, and an output of the NOR circuit GN2is applied to a gate terminal of the N-channel field-effect transistor N45. An input voltage IN and a selection signal CTN1are input to the NOR circuit GN1, and an input voltage IN and a selection signal CTN2are input to the NOR circuit GN2. Selection signals CTN1and CTN2can be made active on the basis of a power-supply voltage and an operation speed of the driver circuit22. The values of the power-supply voltage and the operation speed are memorized in registers.

In the N-driver circuit23N, when an input voltage IN falls, a P-channel field-effect transistor P21is turned off and the N-channel field-effect transistors N21and N43are turned on. Therefore, the gate potential of the N-channel field-effect transistor NM is pulled down through the N-channel field-effect transistor N43, and the N-channel field-effect transistor NM is turned off. At this time, the N-channel field-effect transistors N44and N45are turned on in response to selection signals CTN1and CTN2, respectively. Therefore, the gradient of the fall-off of the gate potential of the N-channel field-effect transistor NM is adjusted through the N-channel field-effect transistors N44and N45in response to the respective selection signals CTN1and CTN2, and the turn-OFF speed of the N-channel field-effect transistor NM is adjusted.

Here, by increasing the number of the N-channel field-effect transistors N43to N45which can be used in pulling down the gate potential of the N-channel field-effect transistor NM, the sizes of the N-channel field-effect transistors N43to N45can be suppressed from being increased, and the turn-OFF speed of the N-channel field-effect transistor NM can be precisely adjusted.

In the above-described embodiment, although the method has been described in which the number of the N-channel field-effect transistors N43to N45which can be used in pulling down the gate potential of the N-channel field-effect transistor NM is set to three, the above number may be set to four or greater.

On the other hand, in the P-driver circuit23P, when an input voltage IN rises, the P-channel field-effect transistors P11and P33are turned on, and the N-channel field-effect transistor N11is turned off. Therefore, the gate potential of the P-channel field-effect transistor PM is pulled up through the P-channel field-effect transistor P33, and the P-channel field-effect transistor PM is turned off. At this time, the P-channel field-effect transistors P34and P35are turned on in response to selection signals CTP1and CTP2, respectively. Therefore, the gradient of the rise of the gate potential of the P-channel field-effect transistor PM is adjusted through the P-channel field-effect transistor P34in response to the respective selection signals CTP1and CTP2, and the turn-OFF speed of the P-channel field-effect transistor PM is adjusted.

Here, by increasing the number of the P-channel field-effect transistors P33to P35which can be used in pulling up the gate potential of the P-channel field-effect transistor PM, the sizes of the P-channel field-effect transistors P33to P35can be suppressed from being increased, and the turn-OFF speed of the P-channel field-effect transistor PM can be precisely adjusted.

In the above-described embodiment, although the method has been described in which the number of the P-channel field-effect transistors P33to P35which can be used in pulling up the gate potential of the P-channel field-effect transistor PM is set to three, the above number may be set to four or greater.

Fourth Embodiment

FIG. 7is a block diagram schematically illustrating the configuration of an interface circuit according to a fourth embodiment.

InFIG. 7, in this interface circuit, a driver circuit32is provided in place of the driver circuit22ofFIG. 6.

The driver circuit32is provided with a P-driver circuit33P which drives a P-channel field-effect transistor PM and an N-driver circuit33N which drives an N-channel field-effect transistor NM. In the P-driver circuit33P, a P-slew rate control unit24P is provided in place of the P-slew rate control unit4P ofFIG. 6. In the N-driver circuit33N, an N-slew rate control unit24N is provided in place of the N-slew rate control unit4N ofFIG. 6.

The P-slew rate control unit24P can turn on the P-channel field-effect transistor PM by pulling down a gate potential of the P-channel field-effect transistor PM on the basis of an input voltage IN. In addition, the P-slew rate control unit24P can change a turn-ON speed of the P-channel field-effect transistor PM on the basis of selection signals CTN1′ and CTN2′.

Here, the P-slew rate control unit24P is provided with N-channel field-effect transistors N33to N35and NOR circuits GP1′ and GP2′. The N-channel field-effect transistors N33to N35are connected to each other in parallel. In addition, drain terminals of the N-channel field-effect transistors N33to N35are connected to a gate terminal of the P-channel field-effect transistor PM. An input voltage IN is applied to a gate terminal of the N-channel field-effect transistor N33through an inverter PV, an output of the NOR circuit GP1′ is applied to a gate terminal of the N-channel field-effect transistor N34, and an output of the NOR circuit GP2′ is applied to a gate terminal of the N-channel field-effect transistor N35. An input voltage IN and a selection signal CTN1′ are input to the NOR circuit GP1′, and an input voltage IN and a selection signal CTN2′ are input to the NOR circuit GP2′. Selection signals CTN1′ and CTN2′ can be made active on the basis of a power-supply voltage and an operation speed of the driver circuit32. The values of the power-supply voltage and the operation speed are memorized in registers.

The N-slew rate control unit24N can turn on the N-channel field-effect transistor NM by pulling up a gate potential of the N-channel field-effect transistor NM on the basis of an input voltage IN. In addition, the N-slew rate control unit24N can change a turn-ON speed of the N-channel field-effect transistor NM on the basis of selection signals CTP1′ and CTP2′.

Here, the N-slew rate control unit24N is provided with P-channel field-effect transistors P43to P45and NAND circuits GN1′ and GN2′. The P-channel field-effect transistors P43to P45are connected to each other in parallel. In addition, drain terminals of the P-channel field-effect transistors P43to P45are connected to the gate terminal of the P-channel field-effect transistor PM. An input voltage IN is applied to a gate terminal of the P-channel field-effect transistor P43through an inverter NV, an output of the NAND circuit GN1′ is applied to a gate terminal of the P-channel field-effect transistor P44, and an output of the NAND circuit GN2′ is applied to a gate terminal of the P-channel field-effect transistor P45. An input voltage IN and a selection signal CTP1′ are input to the NAND circuit GN1′, and an input voltage IN and a selection signal CTP2′ are input to the NAND circuit GN2′. Selection signals CTP1′ and CTP2′ can be made active on the basis of a power-supply voltage and an operation speed of the driver circuit32. The values of the power-supply voltage and the operation speed are memorized in registers.

In the P-driver circuit33P, when an input voltage IN falls, a P-channel field-effect transistor P33is turned off, and the N-channel field-effect transistor N33is turned on. Therefore, the gate potential of the P-channel field-effect transistor PM is pulled down through the N-channel field-effect transistor N33, and the P-channel field-effect transistor PM is turned on. At this time, the N-channel field-effect transistors N34and N35are turned on in response to selection signals CTN1′ and CTN2′, respectively. Therefore, the gradient of the fall-off of the gate potential of the P-channel field-effect transistor PM is adjusted through the N-channel field-effect transistors N34and N35in response to the respective selection signals CTN1′ and CTN2′, and the turn-ON speed of the P-channel field-effect transistor PM is adjusted.

Here, in order to adjust the turn-ON speed of the P-channel field-effect transistor PM, the number of the N-channel field-effect transistors N33to N35which pull down the gate potential of the N-channel field-effect transistor NM is changed, and thus it is possible to prevent an excessive load from being applied in series to the N-channel field-effect transistors N33to N35, and it is possible to suppress an increase in the sizes of the N-channel field-effect transistors N33to N35.

In the above-described embodiment, although the method has been described in which the number of the N-channel field-effect transistors N33to N35which can be used in pulling down the gate potential of the N-channel field-effect transistor NM is set to three, the above number may be set to four or greater.

On the other hand, in the N-driver circuit33N, when an input voltage IN rises, the P-channel field-effect transistor P43is turned on, and the N-channel field-effect transistor N43is turned off. Therefore, the gate potential of the N-channel field-effect transistor NM is pulled up through the P-channel field-effect transistor P43, and the N-channel field-effect transistor NM is turned on. At this time, the P-channel field-effect transistors P44and P45are turned on in response to selection signals CTP1′ and CTP2′, respectively. Therefore, the gradient of the rise of the gate potential of the N-channel field-effect transistor NM is adjusted through the P-channel field-effect transistors P44and P45in response to the respective selection signals CTP1′ and CTP2′, and the turn-ON speed of the N-channel field-effect transistor NM is adjusted.

Here, in order to adjust the turn-ON speed of the N-channel field-effect transistor NM, the number of the N-channel field-effect transistors N43to N45which pull up the gate potential of the N-channel field-effect transistor NM is changed, and thus it is possible to prevent an excessive load from being applied in series to the N-channel field-effect transistors N43to N45, and it is possible to suppress an increase in the sizes of the N-channel field-effect transistors N43to N45.

In the above-described embodiment, although the method has been described in which the number of the N-channel field-effect transistors N43to N45which can be used in pulling up the gate potential of the P-channel field-effect transistor PM is set to three, the above number may be set to four or greater.

Fifth Embodiment

FIG. 8Ais a block diagram schematically illustrating the configuration of a semiconductor storage device to which an interface circuit according to a fifth embodiment is applied,FIG. 8Bis a perspective view schematically illustrating the configuration of the NAND memory103-1ofFIG. 8A, andFIG. 8Cis a perspective view schematically illustrating the configuration of the semiconductor chip CP1of the NAND memory103-1ofFIG. 8B.

InFIGS. 8A to 8C, the semiconductor storage device is provided with n (n is an integer of 2 or greater) NAND memories103-1to103-n, and a controller101which controls the driving of the NAND memories103-1to103-n. Examples of the control of the driving of the NAND memories103-1to103-ninclude control of reading and writing from and on the NAND memories103-1to103-n, block selection, error correction, and wear levelling.

The NAND memories103-1to103-nare connected to the controller101in parallel through a channel102. Here, for example, the NAND memory103-1is provided with m (m is an integer of 2 or greater) semiconductor chips CP1to CPm. Each of the semiconductor chips CP1to CPm has a NAND flash memory113mounted thereon, and pad electrodes PD1to PDm, each of which is connected to the NAND flash memory113, are formed, respectively. In the NAND flash memory113, for example, a unit cell array, a decoder, a sense amplifier, a charge pump circuit, a page buffer, and the like can be provided.

In addition, each of the semiconductor chips CP1to CPm is provided with an input interface circuit111, an output interface circuit112, and a rate setting portion116. The input interface circuit111can transfer write data sent from the controller101and a control signal such as an address to the NAND flash memory113and the like. The output interface circuit112can transfer readout data read out from the NAND flash memory113and the like to the controller101.

The output interface circuit112can use any of the configurations ofFIGS. 1 and 5to7. In addition, the time lag generation circuit7ofFIG. 3may be added to the output interface circuit112.

The rate setting portion116can independently set the turn-ON speeds and the turn-OFF speeds of a P-channel field-effect transistor PM and an N-channel field-effect transistor NM on the basis of parameter setting. Here, the rate setting portion116is provided with a resister114and a generator115.

When the output interface circuit112uses the configuration ofFIG. 1, values of intermediate voltages FN, FP, FNR, and FPR can be stored in the resister114. At this time, the generator115can generate intermediate voltages FN, FP, FNR, and FPR on the basis of a value of the resister114, and can supply the voltages to the output interface circuit112.

When the output interface circuit112uses the configuration ofFIG. 5, values of intermediate voltages FN and FP and selection signals CTP and CTN can be stored in the resister114. At this time, the generator115can generate intermediate voltages FN and FP and selection signals CTP and CTN on the basis of a value of the resister114, and can supply the voltages and signals to the output interface circuit112.

When the output interface circuit112uses the configuration ofFIG. 6, values of intermediate voltages FN and FP and selection signals CTP1, CTP2, CTN1, and CTN2can be stored in the resister114. At this time, the generator115can generate intermediate voltages FN and FP and selection signals CTP1, CTP2, CTN1, and CTN2on the basis of a value of the resister114, and can supply the voltages and signals to the output interface circuit112.

When the output interface circuit112uses the configuration ofFIG. 6, values of selection signals CTP1, CTP2, CTN1, CTN2, CTP1′, CTP2′, CTN1′ and CTN2′ can be stored in the resister114. At this time, the generator115can generate selection signals CTP1, CTP2, CTN1, CTN2, CTP1′, CTP2′, CTN1′ and CTN2′ on the basis of a value of the resister114, and can supply the signals to the output interface circuit112.

The m semiconductor chips CP1to CPm are mounted on one semiconductor package PK1, and an external terminal TM of the semiconductor package PK1is shared with the pad electrodes PD1to PDm of the m semiconductor chips CP1to CPm. As a method of mounting the semiconductor chips CP1to CPm on the semiconductor package PK1, a method of stacking the semiconductor chips CP1to CPm, or a method of arranging the semiconductor chips CP1to CPm on the same plane may be used. In addition, the semiconductor chips CP1to CPm may be face-down-mounted, or may be face-up-mounted. In addition, as a method of sharing one external terminal TM with the m pad electrodes PD1to PDm, the m pad electrodes PD1to PDm and one external terminal TM can be connected using a bonding wire BW. Otherwise, the semiconductor chips CP1to CPm may be flip-mounted, and the pad electrodes PD1to PDm and the external terminal TM may be connected to each other through bump electrodes formed in the pad electrodes PD1to PDm. Otherwise, penetration electrodes may be formed in the semiconductor chips CP1to CPm, and the pad electrodes PD1to PDm and the external terminal TM may be connected to each other through the penetration electrodes. The NAND memories103-2to103-nother than the NAND memory103-1also have a similar configuration. In addition, the semiconductor storage device can be used as a storage device such as a memory card or SSD.

FIG. 9is a perspective view schematically illustrating an example of the configuration of the NAND memory103-1ofFIG. 8A. In the example ofFIG. 9, m is 4.

InFIG. 9, in semiconductor chips CP1to CP4, pad electrodes PD1to PD4are formed, respectively. The pad electrodes PD1to PD4can be used as, for example, an address terminal, a read/write terminal, a chip select terminal, or a data terminal. In addition, in a semiconductor package PK1, external terminals TM1to TM17are formed. When the four semiconductor chips CP1to CP4are stacked and mounted on the semiconductor package PK1, the semiconductor chips CP1to CP4can be stacked stepwise so as to expose the pad electrodes PD1to PD4. In addition, for example, one external terminal TM1can be shared with the pad electrodes PD1to PD4of the four semiconductor chips CP1to CP4by connecting the pad electrodes PD1to PD4to the external terminal TM1in common through a bonding wire BW.

FIG. 10is a diagram illustrating an example of the pin arrangement of the semiconductor chip CP1ofFIG. 9.

InFIG. 10, for example, 29 pad electrodes PD1can be provided in the semiconductor chip CP1. Here, VSSQ, VCCQ, DQ[0], DQ[1], DQ[2], DQ[3], VSSQ, VCCQ, DQS, /DQS, VSSQ, VCCQ, DQ[4], DQ[5], DQ[6], DQ[7], VSSQ, VCCQ, RE, /RE, VREF, VCC, VSS, /CE, CLE, ALE, /WE, /WP, and RB can be assigned to each pad electrode. VCC and VSS are power, VSSQ and VCCQ are I/O power, DQ[0], DQ[1], DQ[2], DQ[3], DQ[4], DQ[5], DQ[6], and DQ[7] are data signals, DQS and /DQS are data strobe signals, RE is a read enable signal, VREF is a reference signal, CE is a chip enable signal, CLE is a chip latch enable signal, ALE is an address latch enable signal, WE is a read/write signal, WP is a write protect signal, and RB is a ready/busy signal.