Semiconductor memory device

A semiconductor memory device includes a cell array layer including a first and a second wiring, which cross each other; a third wiring formed on a first wiring layer below the cell array layer; a fourth wiring formed on a second wiring layer above the cell array layer; and a contact extending in a stacking direction for connecting the third and the fourth wiring, wherein the device further comprises a redundant wiring layer being formed between the first and the second wiring layer, the redundant wiring layer being formed with a redundant wiring having a portion extending in the same direction as at least one of the third and the fourth wiring, and the third and the redundant wiring, and the fourth and the redundant wiring being connected by a plurality of contacts arranged along the portion extending in the same direction as the third or the fourth wiring.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2009-70849, filed on Mar. 23, 2009, the entire contents of which are incorporated herein by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a semiconductor memory device having a multi-layer structure in which cross-point type memory cells are stacked.

2. Description of the Related Art

There has conventionally been known a flash memory, as an electrically rewritable nonvolatile memory, which includes a memory cell array of NAND-connected or NOR-connected memory cells having a floating gate structure. A ferroelectric memory is also known as a nonvolatile fast random access memory.

On the other hand, technologies of pattering memory cells much finer include a resistance variable memory, which uses a variable resistor in a memory cell as proposed. Known examples of the variable resistor include a phase change memory element that varies the resistance in accordance with the variation in crystal/amorphous states of a chalcogenide compound; an MRAM element that uses a variation in resistance due to the tunnel magneto-resistance effect; a polymer ferroelectric RAM (PFRAM) memory element including resistors formed of a conductive polymer; and a ReRAM element that causes a variation in resistance on electrical pulse application (Patent Document 1: Japanese Patent Application Laid-Open No. 2006-344349, paragraph 0021).

The resistance variable memory may configure a memory cell with a serial circuit of a Schottky diode and a resistance variable element in place of the transistor. Accordingly, it can be stacked easily and three-dimensionally structured to achieve much higher integration advantageously (Patent Document 2: Japanese Patent Application Laid-Open No. 2005-522045).

However, in the above-mentioned memory having the multi-layer structure, the length of the wiring at the contact portion in the stacking direction increases, so that the resistance value at the contact portion increases with the microfabrication of the wiring pitch. Therefore, there arises a problem of increasing an IR drop.

SUMMARY OF THE INVENTION

A semiconductor memory device according to one aspect of the present invention includes a semiconductor substrate; a cell array layer which is formed above the semiconductor substrate and includes a first wiring and a second wiring, which cross each other, and a memory cell connected to the first and second wirings at an intersection thereof; a third wiring formed on a first wiring layer below the cell array layer; a fourth wiring formed on a second wiring layer above the cell array layer; and a contact extending in a stacking direction for connecting the third wiring and the fourth wiring, wherein the semiconductor memory device further comprises a redundant wiring layer being formed between the first wiring layer and the second wiring layer, the redundant wiring layer being formed with a redundant wiring having a portion extending in the same direction as at least one of the third wiring and the fourth wiring, and the third wiring and the redundant wiring, and the fourth wiring and the redundant wiring being connected by a plurality of contacts arranged along the portion extending in the same direction as the third wiring or the fourth wiring.

A semiconductor memory device according to another aspect of the present invention includes a semiconductor substrate; a cell array layer which is formed above the semiconductor substrate and includes a first wiring and a second wiring, which cross each other, and a memory cell connected to the first and second wirings at an intersection thereof; a third wiring formed on a first wiring layer below the cell array layer; a fourth wiring formed on a second wiring layer above the cell array layer; and a contact extending in a stacking direction for connecting the third wiring and the fourth wiring, wherein the semiconductor memory device further comprises a redundant wiring layer being formed between the first wiring layer and the second wiring layer, and the third wiring and the redundant wiring, and the fourth wiring and the redundant wiring being connected by a contact having a width, in the direction in which the third wiring or the fourth wiring extends, greater than a width of the third wiring or the fourth wiring.

A semiconductor memory device according to still another aspect includes a semiconductor substrate; a plurality of memory blocks formed above the semiconductor substrate in a matrix and each of which includes stacked cell array layers, the cell array layer including a first wiring and a second wiring, which cross each other, and a memory cell connected to the first and second wirings at an intersection thereof; a third wiring formed on a first wiring layer below the cell array layer; a fourth wiring formed on a second wiring layer above the cell array layer; and a contact extending in a stacking direction for connecting the third wiring and the fourth wiring, wherein the semiconductor memory device further comprises a redundant wiring layer being formed between the first wiring layer and the second wiring layer, the redundant wiring being formed on the redundant wiring layer and having a portion extending in the same direction as at least one of the third wiring and the fourth wiring, and the third wiring and the redundant wiring, and the fourth wiring and the redundant wiring being connected by a plurality of contacts arranged along the portion extending in the same direction as the third wiring or the fourth wiring.

DETAILED DESCRIPTION OF THE EMBODIMENTS

The embodiments according to the present invention will now be described with reference to the drawings.

FIG. 1illustrates a basic structure of a resistance variable memory device, such as ReRAM, according to the embodiment of the present invention, i.e., the structure having a semiconductor substrate1, a wiring area3formed on the semiconductor substrate1and having wirings such as global pass formed thereon, and a memory block2stacked thereon.

As illustrated inFIG. 1, the memory block2includes four memory cell arrays MA0to MA3in this example. The wiring area3is formed on the semiconductor substrate1immediately below the memory block2. The global pass or the like is provided on the wiring area3for externally sending and receiving data, which is to be written in the memory block2or read from the memory block2. The wiring area3may be provided with a column control circuit including a column switch or a row control circuit including a row decoder.

A vertical wiring (via contact) is required at the side face of the memory block2in order to connect a word line WL that is a first wiring and a bit line BL that is a second wiring of each of the stacked memory cell arrays MA to the wiring area3formed on the semiconductor substrate1. A bit-line contact area4and a word-line contact area5are formed at four sides of the wiring area3. A bit-line contact6and a word-line contact7for connecting the bit line BL and the word line WL to a control circuit are formed at the bit-line contact area4and the word-line contact area5. The word line WL is connected to the wiring area3through the word-line contact7whose one end is formed at the word-line contact area5. The bit line BL is connected to the wiring area3through the bit-line contact6whose one end is formed at the bit-line contact area4.

FIG. 1illustrates a single memory block2having a plurality of memory cell arrays MA stacked in the direction vertical to the semiconductor substrate1(in a z direction inFIG. 1). However, in actuality, a plurality of the memory blocks2of this type is arranged in a matrix in the direction in which the word line WL extends (in an x direction inFIG. 1) and in the direction in which the bit line BL extends (in a y direction inFIG. 1).

FIG. 2is a plan view illustrating a part of the resistance variable memory having a plurality of memory blocks2arranged in a matrix.

The word-line contact area5including a word-line driver is formed between the adjacent memory blocks2in the direction of the word line WL. For example, a third wiring11is formed on a first wiring layer M1at the upper portion of the word-line contact area5, while a fourth wiring12is formed on a second wiring layer M2above the layer where the memory block2is formed.

FIG. 3is a schematic sectional view of the resistance variable memory. In the figure, the bit-line contact area4and the word-line contact area5are formed at both sides of the memory block2. However, in actuality, the bit line BL extends in the direction orthogonal to the surface of the sheet, so that the bit-line contact area4is arranged at both sides of the memory block2in the direction orthogonal to the surface of the sheet.

A 0th wiring layer M0(wiring15), a first wiring layer M1, and a second wiring layer M2are formed, in this order from the semiconductor substrate1, above the semiconductor substrate1as the wiring layers. The memory block2having the four-layer structure is formed between the first wiring layer M1and the second wiring layer M2. Each of the memory cell arrays MA0to MA in the memory block2is a cross-point memory cell array, and composed by stacking memory cells MC, each including a serial circuit made of a diode D and a variable resistor VR, between the word line WL and the bit line BL that are at right angles to each other. The third wiring11on the first wiring layer M1and the fourth wiring12on the second wiring layer M2are connected to each other by contacts141to144that extend in the stacking direction through one or plural redundant wirings131to133formed between both layers. The redundant wirings13are formed simultaneously with the word line WL or the bit line BL on the same layer as the word line WL or the bit line BL.

Next, the manner of connecting the third wiring11, the fourth wiring12, and the redundant wirings13with the contacts14will be described.

First Embodiment

FIG. 4is a perspective view illustrating a connection manner of the contact area according to the first embodiment.

In this embodiment, the third wiring11and the fourth wiring12extend in parallel to each other. The redundant wiring13arranged between the third wiring11and the fourth wiring12also extends in the direction of the wirings11and12. Specifically, the present embodiment has a reed shape. The third wiring11and the redundant wiring13, and the redundant wiring13and the fourth wiring12are connected by a plurality of contacts141and142arranged in the longitudinal direction of the redundant wiring13. Since the upper and lower wirings11and12are connected by the plurality of contacts141and142, the connection resistance value between the wirings11and12can sufficiently be reduced, even if the line and space (L/S) of the wirings11and12are as finely formed as several tens of nanometers. Consequently, the influence of the IR drop can be eliminated.

Second Embodiment

FIG. 5is a perspective view illustrating a connection manner of the contact area according to the second embodiment.

In the first embodiment, a single redundant wiring layer is employed. However, in the present embodiment, three redundant wiring layers are employed. The third wiring11and the fourth wiring12extend in parallel to each other. The redundant wirings131,132, and133arranged between the third wiring11and the fourth wiring12also extend in the direction of the wirings11and12. Specifically, the present embodiment has a reed shape. The third wiring11and the redundant wiring131, the redundant wiring131and the redundant wiring132, the redundant wiring132and the redundant wiring133, and the redundant wiring133and the fourth wiring12, are connected by a plurality of contacts141,142,143, and144arranged in the longitudinal direction of the redundant wiring131,132, and133respectively. In this case, the redundant wirings131,132, and133are formed on the same layer as the word line WL or the bit line BL, so that there is no addition in the process. Further, the length of each of the contacts141,142,143, and144can be decreased, which is advantageous upon processing.

Third Embodiment

FIG. 6is a perspective view illustrating a connection manner of the contact area according to the third embodiment.

In the first and second embodiments, the third wiring11and the fourth wiring12are parallel to each other. In this embodiment, the third wiring11and the fourth wiring12are orthogonal to each other. The redundant wiring131of the redundant wirings131and132formed between the third wiring11and the fourth wiring12is formed into an L shape having a portion extending in the direction in which the third wiring11extends and a portion extending in the direction in which the fourth wiring12extends. The third wiring11and the portion of the L-shaped redundant wiring131extending in the direction in which the third wiring11extends are connected by a plurality of contacts141arranged along the third wiring11. The redundant wiring131and the redundant wiring133, and the redundant wiring132and the fourth wiring12, are connected by a plurality of contacts142and143arranged along the fourth wiring12. The adjacent redundant wirings131are arranged so as to be slightly shifted respectively in the direction in which the third wiring11extends and in the direction in which the fourth wiring12extends.

According to the third embodiment, the connection resistance between the mutually orthogonal wirings11and12can be reduced.

Fourth Embodiment

FIG. 7is a perspective view illustrating a connection manner of the contact area according to the fourth embodiment.

In this embodiment, the third wiring11and the fourth wiring12cross each other. However, the redundant wiring13does not have an L-shape as in the third embodiment, but has a rectangular shape. The contact141that connects the third wiring11and the redundant wiring13is formed to have a width, in the direction in which the third wiring11extends, greater than the width thereof in the widthwise direction of the third wiring11. The contact142that connects the redundant wiring13and the fourth wiring12is formed to have a width, in the direction in which the fourth wiring12extends, greater than the width thereof in the widthwise direction of the fourth wiring12. The redundant wiring13is formed to have the width and the length greater than the widths of the third wiring11and the fourth wiring12according to the greater width of the contacts141or142. Since the redundant wiring13is formed to have the rectangular shape, the production quality is more enhanced than in the third embodiment.

Other Embodiment

The present invention is not limited to the memory cell structure. The present invention is applicable to various cross-point multi-layer memories, such as a phase change memory element, MRAM device, PFRAM, and ReRAM.