Silicon carbide semiconductor device

According to one embodiment, a semiconductor device includes a first semiconductor region, a second semiconductor region, a third semiconductor region, a fourth semiconductor region, an insulating film, a control electrode, a first electrode, and a second electrode. The first semiconductor region includes silicon carbide, and has a first portion. The second semiconductor region is provided on the first semiconductor region, and includes silicon carbide. The third semiconductor region and the fourth semiconductor region are provided on the second semiconductor region, and includes silicon carbide. The electrode is provided on the film. The second semiconductor region has a first region and a second region. The first region contacts with the third semiconductor region and the fourth semiconductor region. The second region contacts with the first portion. The impurity concentration of the first region is higher than an impurity concentration of the second region.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2012-043648, filed on Feb. 29, 2012; the entire contents of which are incorporated herein by reference.

FIELD

BACKGROUND

Silicon carbide (SiC) has physical properties which are superior by three times in band gap, by about ten times in breakdown electric field strength, and by about three times in thermal conductivity compared with silicon (Si). Using such characteristics of SiC, it is possible to realize a semiconductor device which has low loss and superior high temperature operation.

In the semiconductor device using SiC, it is desired that on-resistance is decreased and avalanche resistance is enhanced to realize stable breakdown voltage.

DETAILED DESCRIPTION

In general, according to one embodiment, a semiconductor device includes a first semiconductor region, a second semiconductor region, a third semiconductor region, a fourth semiconductor region, an insulating film, a control electrode, a first electrode, and a second electrode. The first semiconductor region includes silicon carbide of a first conductivity type. The first semiconductor region has a first portion. The second semiconductor region is provided adjacent to the first portion on the first semiconductor region. The second semiconductor region includes silicon carbide of a second conductivity type. The third semiconductor region is provided spaced from the first portion on the second semiconductor region. The third semiconductor region includes silicon carbide of the first conductivity type. The fourth semiconductor region is provided on the second semiconductor region. The fourth semiconductor region includes silicon carbide of the second conductivity type. The insulating film is provided on the first semiconductor region, the second semiconductor region and the third semiconductor region. The control electrode is provided on the insulating film. The first electrode is electrically connected to the third semiconductor region. The second electrode is electrically connected to the first semiconductor region. The second semiconductor region has a first region and a second region. The first region contacts with the third semiconductor region and the fourth semiconductor region. The second region contacts with the first portion. The impurity concentration of the first region is higher than an impurity concentration of the second region.

The drawings are schematic and conceptual, and thus, the relationship between the thickness and width of each part, the ratio between the sizes of respective parts, and the like are not necessarily the same as in real parts. Further, even in a case where the same part is shown, the size or ratio thereof may be differently shown according to the drawings.

Further, in the specification and each drawing, the same elements as those described with reference to the previous drawings are given the same reference signs, and description thereof will be appropriately omitted.

Further, in the embodiments, specific examples in which a first conductivity type is an n-type and a second conductivity type is a p-type will be described.

Further, in the following description, the indications of n+, n, n−, p+, p and p−represent a relative level of impurity concentration in the respective conductivity types. That is, as the number of + is large, the impurity concentration is relatively high, and as the number of − is large, the impurity concentration is relatively low.

First Embodiment

FIGS. 1A and 1Bare cross-sectional views schematically illustrating a configuration of a semiconductor device according to a first embodiment.

FIG. 2is a plan view schematically illustrating the configuration of the semiconductor device according to the first embodiment.

FIG. 3is an enlarged cross-sectional view schematically illustrating the periphery of a channel.

FIG. 3shows the periphery of the channel inFIG. 1A.

As shown inFIGS. 1A and 1B, a semiconductor device110according to the first embodiment includes a first semiconductor region10, a second semiconductor region20, a third semiconductor region30, a fourth semiconductor region40, an insulating film60, a control electrode G, a first electrode D1, and a second electrode D2. The semiconductor device110according to the first embodiment is a DIMOSFET (Double Implantation MOSFET) using silicon carbide (SiC).

The first semiconductor region10includes a first portion11which protrudes upward. The first semiconductor region10includes SiC of the first conductivity type (n−-type).

In the embodiment, the first semiconductor region10is formed on an upper surface S1of a substrate S which includes SiC of the first conductivity type (n+-type) formed by epitaxial growth, for example.

Here, in the embodiment, a direction orthogonal to the upper surface S1of the substrate S is referred to as the Z direction, one of directions orthogonal to the Z direction is referred to as the X direction, and a direction orthogonal to the Z direction and the X direction is referred to as the Y direction. Further, a direction which directs toward the first semiconductor region10from the substrate S is referred to as up (upper side), and a direction which directs toward the substrate S from the first semiconductor region10is referred to as down (lower side).

The first semiconductor region10includes the first portion11and a second portion12. The first portion11is provided on a part of the second portion12. The first portion11is a JFET (Junction Field Effect Transistor) region of the DIMOSFET. The second portion12is a drift region of the DIMOSFET.

The second semiconductor region20is provided on the first semiconductor region10. The second semiconductor region20extends along the X direction (seeFIG. 2). The second semiconductor region20includes a channel section21. The channel section21is a part of the DIMOSFET channel. The channel section21is provided adjacent to the first portion11and has a first impurity concentration. The second semiconductor region20includes SiC of the second conductivity type (p-type). That is, the second semiconductor region20is provided in a part other than the part in which the first portion11is provided, on the second portion12. The second semiconductor region20is a p-type well of the DIMOSFET.

The third semiconductor region30is provided on the second semiconductor region20. The third semiconductor region30extends along the X direction (seeFIG. 3). The third semiconductor region30is provided above a surface layer portion of the second semiconductor region20and includes SiC of the first conductivity type. The third semiconductor region30is a source region of the DIMOSFET.

In the semiconductor device110, the third semiconductor region30includes a high resistance region31, and a low resistance region32which has a resistance value lower than that of the high resistance region31. The high resistance region31is an n+-type, and the low resistance region32is an n++-type. The high resistance region31is provided on a second region52which will be described later. The low resistance region32is provided on a region which is not the upper side of the second region52(which will be described later), but on the second semiconductor region20.

The fourth semiconductor region40is provided on a side which is opposite to the channel section21of the third semiconductor region30, at an inner side from outer edges e2of the second semiconductor region20. The fourth semiconductor region40includes SiC of the second conductivity type. The fourth semiconductor region40has a p++-type which has an impurity concentration higher than that of the second semiconductor region20, and is used as a contact region with the first electrode D1(which will be described later).

The second semiconductor region20includes a high concentration region50. The high concentration region50is a region of the second semiconductor region20which is in contact with the third semiconductor region30and the fourth semiconductor region40. The impurity concentration of the high concentration region50is higher than the impurity concentration of a region of the second semiconductor region20which is in contact with the first portion11. That is, the second semiconductor region20has the high concentration region50having an impurity concentration (second impurity concentration) higher than the impurity concentration (first impurity concentration) of the channel section21. The high impurity concentration50includes SiC of the second conductivity type (p+-type or p++-type). The high concentration region50includes a first region51and the second region52.

The first region51is provided between the channel section21and the third semiconductor region30. The first region51functions as a channel buffer of the DIMOSFET. In the semiconductor device110according to the embodiment, the channel includes the channel section21and the first region51which functions as the channel buffer.

Low on-resistance and high breakdown voltage are realized by providing the first region51which functions as the channel buffer.

The second region52which is a part of the high concentration region50electrically connects the first region51to the fourth semiconductor region40.

The first region51is provided along the side of the channel section21of the third semiconductor region30. The second region52is a by-pass region where the first region51is electrically connected to the fourth semiconductor region40. As shown inFIG. 2, the second region52is provided to connect a part of the first region51to a part of the fourth semiconductor region40. The second region52is provided on the lower side of the third semiconductor region30. Specifically, the second region52is provided on the lower side of the high resistance region31of the third semiconductor region30as viewed in the Z direction.

In the semiconductor device110in which the second region52is provided, when the semiconductor device110is in an off-state, holes (positive holes) in the second semiconductor region20flow to the fourth semiconductor region40through the second region52. Thus, avalanche resistance of the semiconductor device110is improved.

An insulating film60is provided on the first semiconductor region10, the second semiconductor region20, and the third semiconductor region30. When an upper surface, where the first portion11of the first semiconductor region10is exposed and the XY plane which is an extension plane thereof, is represented as a first main surface10a, the insulating film60has a portion which is continuously provided along the first main surface10a. A part of the insulating film60which is provided between the first main surface10aand the control electrode G (which will be described later) is a DIMOSFET gate insulating film. Further, the insulating film60functions as a film which forms insulation between the control electrode G and the first electrode D1(which will be described later).

The control electrode G is provided on the insulating film60. That is, the control electrode G is provided through the part (gate insulating film) of the insulating film60which is provided on the main surface10a. Thus, the control electrode G functions as a gate electrode of the DIMOSFET.

The first electrode D1is electrically connected to the third semiconductor region30. The first electrode D1is electrically insulated from the control electrode G by the insulating film60. The first electrode D1is in contact with the third semiconductor region30which is exposed to the first main surface10a. The first electrode D1is a source electrode of the DIMOSFET.

Here, since the high resistance region31is provided on the second region52, the first electrode D1obtains a superior contact through the low resistance region32of the third semiconductor region30.

In the embodiment, the first electrode D1is also in contact with the fourth semiconductor region40which is exposed to the first main surface10a. Thus, the first electrode D1functions as a common electrode of the source region and the p-type well of the DIMOSFET.

The second electrode D2is electrically connected to the first semiconductor region10. The first semiconductor region10is connected to the substrate S on a second main surface10bwhich is a surface opposite to the first main surface10aof the first semiconductor region10. The second electrode D2is provided on a lower surface S2opposite to the upper surface S1of the substrate S. The second electrode D2is a drain electrode of the DIMOSFET.

In the semiconductor device110according to the embodiment, one pair of second semiconductor regions20, one pair of third semiconductor regions30, and one pair of fourth semiconductor regions40are provided, with the JFET region which is the first portion11being interposed therebetween. The JFET region is a region between the pair of second semiconductor regions20(one pair of channel sections21).

Further, the insulating film60is continuously formed on the first portion11, on one pair of second semiconductor regions20(one pair of channel sections21and one pair of first regions51), and on one pair of third semiconductor regions30. The control electrode G is provided on the insulating film60. Accordingly, one pair of channels is controlled using one control electrode G.

Next, a specific example of the semiconductor device110will be described.

The substrate S is a hexagonal crystal SiC substrate (n+substrate) which includes, for example, nitrogen (N) as an n-type impurity, having an impurity concentration of approximately 5×1018cm−3or more and 1×1019cm−3or less.

On the upper surface S1of the substrate S, there is formed the first semiconductor region10(n−layer) of the n-type having an impurity concentration of the n-type impurity of approximately 5×1015cm−3or more and 2×1016cm−3or less. The thickness of the first semiconductor region10is 5 μm or more and 10 μm or less, for example.

On the surface of a part of the first semiconductor region10, there is formed the second semiconductor region20(p-type well) of the p-type having an impurity concentration of the p-type impurity of approximately 5×1015cm−3or more and 1×1017cm−3or less. The depth of the second semiconductor region20is approximately 0.6 μm, for example.

On the surface of a part of the semiconductor region20, there is formed the third semiconductor region30(source region) of the n-type having an impurity concentration of the n-type impurity of approximately 1×1020cm−3. The third semiconductor region30is provided to be in parallel with the channel section21of the second semiconductor region20. The depth of the third semiconductor region30is lower than the depth of the second semiconductor region20, and for example, is approximately 0.3 μm.

Further, on the surface of a part of the second semiconductor region20and beside the third semiconductor region30, there is formed the fourth semiconductor region (p-type well contact region) of the p-type having an impurity concentration of the p-type impurity of approximately 1×1019cm−3or more and 1×1020cm−3or less. The depth of the fourth semiconductor region40is lower than the depth of the second semiconductor region20, and for example, is approximately 0.4 μm.

Further, the first region51of the p-type which is formed between the channel section21and the third semiconductor region30and has an impurity concentration higher than that of the channel section21, on the front surface of the part of the second semiconductor region20, is formed. The first region51is a channel buffer region.

Further, the insulating film60is formed to continuously cover the surfaces of the first semiconductor region10, the second semiconductor region20and the third semiconductor region30. As the insulating film60, for example, silicon oxide, silicon nitride and high dielectric constant materials (high-k materials) are used.

Further, the control electrode G (gate electrode) is formed on the insulating film60. As the control electrode G, for example, polycrystalline silicon and metallic materials (TiN, Al, Ru, W, TaSiN or the like) are used.

The channel section21and the first region51of the second semiconductor region20which is interposed between the third semiconductor region30and the first portion11under the control electrode G form the channel.

Further, the semiconductor device110includes the first electrode D1(source region and p-type well common electrode) which is electrically connected to the low resistance region32of the third semiconductor region30and the fourth semiconductor region40. The first electrode D1includes a metal layer of nickel (Ni) and a metal layer of aluminum (Al) on the metal layer, for example. The first electrode D1may include an alloy generated by reaction of the Ni metal layer and the Al metal layer. Further, the second electrode D2(drain electrode) is formed on the side of the lower surface S2of the substrate S.

In the embodiment, as the n-type impurity, for example, N or phosphorous (P) is favorable, but arsenic (As) or the like may be used. Further, as the p-type impurity, for example, Al is favorable, but boron (B) or the like may be used.

In the semiconductor device110according to the embodiment, the high concentration p-type first region51(channel buffer region) is formed on the side of the channel region of the third semiconductor region30. Thus, for example, even though a channel length Lch of the semiconductor device110(seeFIG. 3) has a size of 1.0 μm or less, leakage current is suppressed in an off-state. Accordingly, low on-resistance and stable breakdown voltage are realized.

In the semiconductor device110according to the embodiment, it is desired that the impurity concentration of the channel section21in the second semiconductor region20is 5×1015cm−3or more and 1×1017cm−3or less, and that the impurity concentration of the first region (channel buffer region) is 1×1018cm−3or more and 1×1019cm−3or less. It is desired that the impurity concentration of the lower side of the second region52of the second semiconductor region20is 1×1017cm−3or more and 5×1018cm−3or less.

If the impurity concentration of the channel section21is out of the above-mentioned range, it is difficult to set an appropriate threshold voltage of the MOSFET, which is not desired. Here, the impurity concentration means a concentration compensated with N or P.

Further, if the impurity concentration of the first region51(channel buffer region) is below the above-mentioned range, it is difficult to realize sufficient breakdown voltage, which is not desired. Further, if the impurity concentration of the first region51exceeds the range, the on-resistance may be excessively increased, which is not desired.

From the viewpoint of realizing low on-resistance and high-breakdown voltage, it is desired that the impurity concentration of the first region (channel buffer region)51is two or more digits higher than the impurity concentration of the channel section21.

The impurity concentration of the channel section21may be evaluated by SIMS (Secondary Ion Mass Spectrometry) analysis, for example. The impurity concentration of the channel section21is represented by the impurity concentration of the central portion of the channel region under the insulating film60. Further, the impurity concentration of the first region51is represented by a maximum impurity between the channel section21and the third semiconductor region30.

In a case where the distance between a boundary of the first portion11and the second semiconductor region20, and a boundary of the third semiconductor region30and the first region (channel buffer region)51, immediately under the insulating film60, is set to the channel length Lch (seeFIG. 3), it is desired that the length (Lcb shown inFIG. 3) of the first region (channel buffer region)51is 0.1×Lch or more and 0.2×Lch or less.

If the length Lcb of the channel buffer region is below the above-mentioned range, it is difficult to realize sufficient breakdown voltage, which is not desired. Further, if the length Lcb of the channel buffer region exceeds the range, the on-resistance may be excessively increased, which is not desired.

If the channel length Lch or the length Lcb of the channel buffer region is determined by impurity concentration distribution obtained by SIMS analysis or the like, for example. The length Lcb of the channel buffer region is set to the length of a region which has an impurity concentration one digit higher than the impurity concentration of the channel section21.

Further, in the embodiment, it is desired that the channel length Lch is less than 0.5 μm. Particularly, this is because a notable reduction in on-resistance and reduction in leakage current in the region are expected.

In the semiconductor device110, in a state where a ground electric potential is applied to the first electrode D1, which is the source electrode, and a positive electric potential is applied to the second electrode D2, which is the drain electrode, if the voltage of the control electrode G is at a threshold value or higher, a channel is formed in the channel section21. Thus, electrons are injected into the first semiconductor region10through the third semiconductor region30and the channel section21from the first electrode D1, and thus, the semiconductor device110is in the on-state.

On the other hand, if the voltage applied to the control electrode G is lower than the threshold value voltage, the channel is not formed in the channel section21, and thus, the semiconductor device110is in the off-state. Here, the semiconductor device110is switched from the on-state to the off-state, electron-hole pairs may be generated in a depletion layer formed in the interface portion between the second semiconductor region20and the first semiconductor region10. That is, if an electric potential difference between the third semiconductor region30and the first semiconductor region10is rapidly increased and temporarily exceeds the original electric potential difference in the off-state to enter an overvoltage state, electron-hole pairs may be generated due to carriers accelerated by an electric field in the depletion layer. If the generated carriers receive energy from the electric field again and a chain reaction generating the electron-hole pairs occurs, avalanche breakdown occurs.

In the semiconductor device110, according to the embodiment, since the second region52is provided in the MOSFET which includes the first region51which functions as the channel buffer, the electric potential of the first region51is stable. Thus, changes in the electric field distribution of the first region51and the second semiconductor region20are suppressed with respect to the electric potential variation between the first semiconductor region10and the third semiconductor region30, and a local electric field concentration in the semiconductor device110is suppressed. Further, even though holes are generated in the second semiconductor region20due to avalanche breakdown, it is possible to efficiently cause the holes to flow to the fourth semiconductor region40through the second region52. Accordingly, avalanche resistance of the semiconductor device110is improved.

FIG. 4is a plan view schematically illustrating another example (first example) of a semiconductor device according to the first embodiment.

FIG. 4is also a plan view schematically illustrating a semiconductor device111according to another example (first example), in which the insulating film60, the control electrode G and the first electrode D1are not shown.

The second semiconductor region20of the semiconductor device111extends in the X direction along the first main surface10a. Further, the plurality of third semiconductor regions30of the semiconductor device111are provided to be spaced from each other in the X direction.FIG. 4shows two third semiconductor regions30A and30B which are spaced from each other in the X direction.

The first region51of the high concentration region50is provided along the side of the first portion11of the third semiconductor region30, and the second region52is provided between the plurality of third semiconductor regions30A and30B as viewed in the normal direction (Z direction) of the first main surface10a.

According to the semiconductor device111, low on-resistance and stable breakdown voltage are realized, and avalanche resistance is enhanced.

FIG. 5is a plan view schematically illustrating another example (second example) of a semiconductor device according to the first embodiment.

FIG. 5is also a plan view schematically illustrating a semiconductor device112according to another example (second example), in which the insulating film60, the control electrode G and the first electrode D1are not shown.

As shown inFIG. 5, in the semiconductor device112, the high resistance region31is provided between the plurality of third semiconductor regions30A and30B. The second region52is provided on the lower side of the high resistance region31. Except for this configuration, the semiconductor device112is the same as the semiconductor device111shown inFIG. 4.

According to the semiconductor device112, in addition to the improvement of avalanche resistance, compared with the semiconductor device111, since electric current also flows to the high resistance region31, reduction in on-resistance is achieved.

FIG. 6is a plan view schematically illustrating another example (third example) of a semiconductor device according to the first embodiment.

FIG. 6is a plan view schematically illustrating a semiconductor device113according to another example (third example), in which the insulating film60, the control electrode G and the first electrode D1are not shown.

The plurality of semiconductor regions20of the semiconductor device113are provided to be spaced from each other in the X direction along the first main surface10a.FIG. 6shows two second semiconductor regions20A and20B which are spaced from each other in the X direction.

The plurality of second semiconductor regions20(20A and20B) are provided in rectangular forms as viewed in the normal direction (Z direction) of the first main surface10a. In the example shown inFIG. 6, the plurality of second semiconductor regions20are provided to be spaced from each other in the X direction and the Y direction, respectively. That is, the plurality of second semiconductor regions20are disposed in a matrix form as viewed in the Z direction. The first portion11is provided to face the outer edges e2of the second semiconductor regions20(20A and20B) as viewed in the Z direction.

The third semiconductor region30of the semiconductor device113is provided in a rectangular form inside the outer edges e2of the second semiconductor regions20(20A and20B) as viewed in the Z direction. That is, the third semiconductor region30A is provided inside the outer edges e2of the second semiconductor region20A, and the third semiconductor region30B is provided inside the outer edges e2of the second semiconductor region20B.

The fourth semiconductor region40is provided in a rectangular form inside outer edges e3of the third semiconductor regions30(30A and30B) as viewed in the Z direction. That is, the fourth semiconductor region40A is provided inside the outer edges e3of the third semiconductor region30A, and the fourth semiconductor region40B is provided inside the outer edges e3of the third semiconductor region30B.

Further, in the semiconductor device113, the first region51of the high concentration region50is provided along the outer edges e3of the third semiconductor region30as viewed in the Z direction. Further, the second region52of the high concentration region50is provided in the fourth semiconductor region40inside the outer edges e3of the third semiconductor region as viewed in the Z direction. The plurality of second regions52may be provided with respect to one second semiconductor region20. Further, for the third semiconductor region30, the high resistance region31(not shown) may be provided on the second region52.

According to the semiconductor device113, in addition to the improvement of avalanche resistance, compared with the semiconductor device112, the channel concentration is improved, and reduction in on-resistance is achieved.

FIG. 7is a plan view schematically illustrating another example (fourth example) of a semiconductor device according to the first embodiment.

FIG. 7is a plan view schematically illustrating a semiconductor device114according to another example (fourth example), in which the insulating film60, the control electrode G and the first electrode D1are not shown.

The plurality of second semiconductor regions20of the semiconductor device114are provided to be spaced from each other along the first main surface10a. The outer edges e2of the second semiconductor region20are provided in a hexagonal form as viewed in the Z direction. In the example shown inFIG. 7, in two adjacent second semiconductor regions20, the plurality of second semiconductor regions20are disposed so that the sides of the hexagons face each other. The first portion11is disposed between the two adjacent second semiconductor regions20.

The third semiconductor region30of the semiconductor device114is provided in a hexagonal form inside the outer edges e2of the second semiconductor regions20as viewed in the Z direction. The fourth semiconductor region40is provided in a hexagonal form inside the outer edges e3of the third semiconductor regions30as viewed in the Z direction.

Further, in the semiconductor device114, the first region51of the high concentration region50is provided along the outer edges e3of the third semiconductor region30as viewed in the Z direction. Further, the second region52of the high concentration region50is provided in the fourth semiconductor region40inside the outer edges e3of the third semiconductor region as viewed in the Z direction. The plurality of second regions52may be provided with respect to one second semiconductor region20.

According to the semiconductor device114, in addition to the improvement of avalanche resistance, compared with the semiconductor devices111and112, the channel concentration is improved, and reduction in on-resistance is achieved.

Further, in the semiconductor devices113and114, in a case where the interval between two second semiconductor regions20, which face each other as viewed in the Z direction, is the same L1, with respect to the respective corner portions which face each other, of the plurality of adjacent second semiconductor regions20, intervals between the respective corner portions and a point equidistant from the respective corner portions, (an interval L21shown inFIG. 6in the semiconductor device113, and an interval L22shown inFIG. 7in the semiconductor device114) satisfy the relationship of L22<L21.

As the interval L22is shorter than the interval L21, in the semiconductor device114, the electric field applied to the insulating film60which is on the upper side of the first portion11is alleviated compared with the semiconductor device113. Thus, the reliability of the semiconductor device114is enhanced.

In the semiconductor device114shown inFIG. 7, the outer edges e4and e5of the second semiconductor region20, the third semiconductor region30, the fourth semiconductor region40and the first region51of the high concentration region50, as viewed in the Z direction, are provided in a hexagonal form, respectively, but other polygonal forms may be provided.

Second Embodiment

FIG. 8is a cross-sectional view schematically illustrating a semiconductor device according to a second embodiment.

As shown inFIG. 8, a semiconductor device120according to the second embodiment is an IGBT (Insulated Gate Bipolar Transistor).

In the semiconductor device120, a conductivity type of a substrate SS is different from the conductivity type of the substrate S of the semiconductor device110according to the first embodiment. That is, the conductivity type of the substrate SS of the semiconductor120is the p+-type, whereas the conductivity type of the substrate S of the semiconductor device110is the n+-type. The semiconductor device120is the same as the semiconductor device110except that the conductivity types of the substrates S and SS are different from each other.

The substrate SS is a hexagonal crystal SiC substrate which includes for example, Al, as a p-type impurity, having an impurity concentration of approximately 5×1018cm−3or more and 1×1019cm−3or less. In the semiconductor device120which is the IGBT, the control electrode G is a gate electrode, the first electrode D1is an emitter electrode, and the second electrode D2is a collector electrode. In the semiconductor device120, low on-resistance and stable breakdown voltage are realized, and avalanche resistance is enhanced, in a similar way in the semiconductor device110.

As described above, according to the semiconductors according to the embodiments, it is possible to achieve low on-resistance and to realize stable breakdown voltage, and to enhance avalanche resistance.

The embodiments have been described as above, but the invention is not limited to these examples. For example, in the above-described respective embodiments, addition, deletion or design change of components appropriately performed, or a combination of characteristics of the respective embodiments appropriately performed by those skilled in the art is included in the scope of the invention as long as it falls within the spirit of the invention.

For example, in the above-described respective embodiments, the first conductivity type is the n-type and the second conductivity type is the p-type, but the invention may also be applied to a case where the first conductivity type is the p-type and the second conductivity type is the n-type. Further, the semiconductor devices110,111,112,113and114may also be applied to the MOSFET other than the DIMOSFET.