Semiconductor device and method of manufacture

A device includes a substrate with a die over the substrate. A molding compound surrounds the die and includes a structural interface formed along a peripheral region of the molding compound.

BACKGROUND

Semiconductor devices are used in a variety of electronic applications, such as personal computers, cell phones, digital cameras, and other electronic equipment, as examples. Semiconductor devices are typically fabricated by sequentially depositing various insulating or dielectric layers, conductive layers, and semiconductive layers of material over a semiconductor substrate, and patterning the various material layers using lithography to form circuit components and elements thereon. Dozens or hundreds of integrated circuits are typically manufactured on a single semiconductor wafer. The individual dies are singulated by sawing the integrated circuits along a scribe line. The individual dies are then packaged separately, in multi-chip modules, or in other types of packaging, for example.

The semiconductor industry continues to improve the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continual reductions in minimum feature size, which allow more components to be integrated into a given area. These smaller electronic components require smaller and more advanced packaging systems than packages of the past, in some applications.

DETAILED DESCRIPTION

FIGS. 1A through 1Dillustrate a semiconductor device or package100according to an illustrative embodiment. Referring now primarily toFIGS. 1A and 1B, the semiconductor device100is illustrated in cross-section, according to some embodiments, in intermediary stages of manufacturing. The semiconductor device100includes a substrate102and a device die104positioned over the substrate102.

The substrate102may be a semiconductor substrate in some embodiments. The semiconductor substrate may comprise, for example, bulk silicon, doped or undoped, or an active layer of a semiconductor-on-insulator (SOI) substrate. Generally, an SOI substrate comprises a layer of a semiconductor material, such as silicon, formed on an insulator layer. The insulator layer may be, for example, a buried oxide (BOX) layer or a silicon oxide layer. The insulator layer is provided on a substrate, such as a silicon or glass substrate. Alternatively, the substrate may include another elementary semiconductor, such as germanium; a compound semiconductor including silicon carbide, gallium arsenic, gallium phosphide, indium phosphide, indium arsenide, and/or indium antimonide; an alloy semiconductor including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and/or GaInAsP; or combinations thereof. Other substrates, such as multi-layered or gradient substrates, may also be used.

Active devices (not shown) such as transistors, capacitors, resistors, diodes, photo-diodes, fuses, and the like may be formed at the top side103of the substrate102. An interconnect structure (not shown) may be formed over the active devices and the substrate102. The interconnect structure may include inter-layer dielectric (ILD) and/or inter-metal dielectric (IMD) layers containing conductive features (e.g., conductive lines and vias comprising copper, aluminum, tungsten, combinations thereof, and the like) formed using any suitable method. The ILD and IMDs may include low-k dielectric materials having k values, for example, lower than about 4.0 or even 2.0 disposed between such conductive features. In some embodiments, the ILD and IMDs may be made of, for example, phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), fluorosilicate glass (FSG), SiOxCy, Spin-On-Glass, Spin-On-Polymers, silicon carbon material, compounds thereof, composites thereof, combinations thereof, or the like, formed by any suitable method, such as spinning, CVD, and plasma-enhanced CVD.

The interconnect structure electrically connects various active devices to form functional circuits. The functions provided by such circuits may include memory structures, processing structures, sensors, amplifiers, power distribution, input/output circuitry, or the like. The above examples are provided for illustrative purposes only to further explain applications of the present invention and are not meant to limit the present invention in any manner. Other circuitry may be used as appropriate for a given application.

Input/output (I/O) and passivation features (not separately illustrated) may be formed over the interconnect structure. For example, contact pads may be formed over the interconnect structure and may be electrically connected to the active devices through the various conductive features in the interconnect structure, and a passivation layer may be formed over the interconnect structure and the contact pads. Under bump metallurgies (UBMs) may be formed on such contact pads and connectors (e.g., BGA balls, C4 bumps, microbumps, combinations thereof, and the like) may be formed on the UBMs. Additionally, in embodiments where the device die104is a semiconductor die, connectors may be formed on a backside105of the substrate102(e.g., the side of the substrate102opposing a side having active devices formed thereon), and through vias may be formed in the substrate102to provide electrical connection between connectors and the interconnect structure of the device die104.

The device die104has a first surface106and a second opposing surface108. The first surface106of the device die104faces the substrate102such that the device die104is bonded (e.g., flip chip bonded) to a top side103of the substrate102. In some embodiments, the device die104is bonded to contact pads (not shown) on the top side103of substrate102by a plurality of connectors110, such as ball grid array (BGA) balls, controlled collapse chip connector (C4) bumps, microbumps, or the like. The device die104may be a semiconductor die and could be any type of integrated circuit, such as a processor, logic circuitry, memory, analog circuit, digital circuit, mixed signal, and the like. The device die104may include a substrate, active devices, and an interconnect structure (not individually illustrated).

Referring toFIGS. 1A through 1D, the semiconductor device100further includes a molding compound112. The molding compound112is over the substrate102and surrounds the device die104. In some embodiments, the molding compound112may be a molded underfill (MUF) comprising a polymer material (e.g., epoxy, a resin, and the like) either with or without hardeners, fillers (e.g., silica filler, glass filler, aluminum oxide, silicon oxide, and the like), adhesion promoters, combinations thereof, and the like.

The molding compound112may be formed using a suitable process, such as a transfer molding process. The substrate102and the device die104may be disposed between a top mold chase and a bottom mold chase in a molding apparatus. The top and bottom mold chases may comprise a suitable material for providing structural support/pressure. The top and/or bottom mold may be moved to cover features of the substrate102and/or the device die104during the molding process, which may prevent the formation of the molding compound112over such features of the substrate102and/or the device die104. Protective films may be disposed between the mold chases and contact various features of the substrate102and/or device die104. Protective films protect such features from damage due to contact with top or bottom chases. In some embodiments, protective films comprise rubber, polyethylene terephthalate (PET), teflon, or any other material that can be removed from the substrate102and/or the device die104after molding.

In another embodiment, the molding compound112may be initially formed to cover the device die104. Next, a planarization step such as a Chemical Mechanical Polish (CMP) step or a grinding step is performed to planarize the molding compound112until the device die104is exposed. Due to the planarization, the top surface of the device die104is substantially level (coplanar) with the top surface of molding compound112.

Referring still toFIGS. 1A through 1D, the molding compound112includes a structural interface114.FIG. 1Cis a quarter-sectional view of the semiconductor device100illustrated inFIG. 1B, shown in an isometric arrangement, with the structural interface114shown by hidden lines.FIG. 1Dis a detailed, isometric view ofFIG. 1C, illustrating the molding compound112with the structural interface114in accordance with some embodiments. In some aspects, the structural interface114is formed along an outer portion or peripheral region116of the molding compound112. The outer portion or peripheral region116of the molding compound112is distal to an outer edge123of the device die104.

In some aspects, the structural interface114is a groove124formed in the molding compound112. In an embodiment, the groove124is broken into segments along the outer portion or peripheral region116of the molding compound112. In another embodiment, the groove124is positioned in the outer portion or peripheral region116of the molding compound112but only in one or more corner regions126of the molding compound112. The groove124may have a first leg extending along one side of the molding compound112and a second leg extending along and adjacent side of the molding compound112. In some aspects, the first and second legs are perpendicular to each other. In yet some aspects, the groove124is L-shaped. In an alternative embodiment, the groove124is continuous, e.g., the groove124extends along the outer portion or peripheral region116of the molding compound112without interruption.

In an illustrative embodiment, an outer edge128of the groove124is approximately 850 micrometers (μm) from an outer edge130of the molding compound112. In another illustrative embodiment, the outer edge128of the groove124is approximately 300 μm from the outer edge130of the molding compound112. The outer edge128of the groove124may be approximately 300 μm to 850 μm from the outer edge130of the molding compound112.

In some embodiments, the groove124has a width, W, of approximately 1 millimeters (mm). In yet some embodiments, the groove124has a width, W, of approximately 1 to 1.5 mm. In some other embodiments, the groove124has a length, L, of approximately 4 to 4.5 mm. In an embodiment, the groove124has a depth, D, of approximately 50 μm to 150 μm. The depth, D, extends from a topmost surface132of the molding compound112to a bottommost surface134of the groove124. However, any suitable dimensions may be utilized.

The groove124may be formed by a laser ablation process that uses, for example, an EO Laser Ablation-BMC502PI offered by EO Technics Co, Ltd. having a laser power setting of approximately 3.7 W plus or minus 0.3 W. In an embodiment the laser ablation process may be performed by irradiating or ablating the molding compound112with a series of laser pulses to form the grooves124.

In other embodiments, the groove124may be formed or patterned using a laser drill or a mold trace. In such a method, a protective layer, such as a light-to-heat conversion (LTHC) layer or a hogomax layer, is first deposited over the molding compound112. Once protected, a laser is directed towards those portions of the molding compound112which are desired to be removed in order to form the groove124. During the laser drilling process the drill energy may be in a range from 0.1 mJ to about 30 mJ and a drill angle of about 0 degree (perpendicular to the molding compound112) to about 85 degrees to normal of the molding compound112.

Referring primarily toFIGS. 1B and 1C, the semiconductor device100includes a thermal interface material118and may further include a lid120. The thermal interface material118is positioned over the molding compound112and the second surface108at the device die104. The thermal interface material118is used for thermal interconnection between the lid120and the device die104. In some embodiments, the thermal interface material118is used to join the lid120to the device die104. In yet some other embodiments, the thermal interface material118is used to join the lid120to the molding compound112. In still some other embodiments, the thermal interface material118is used to join the lid120to the molding compound112and the device die104.

The lid120is placed over and bonded to the device die104and/or the molding compound112. The lid120may have a flat top surface. In some embodiments, the lid120may be formed of a homogeneous material throughout, which means all the parts of the lid120are formed of the same material. In an embodiment, the lid120is a metal lid. For example, the lid120may be made of copper (Cu) with a thin layer of nickel (Ni), although other metals or metal alloys such as aluminum or aluminum alloys may be used.

The thermal interface material118may be selectively deposited. In some embodiments, the thermal interface material118is selectively deposited over the device die104. The thermal interface material118, in an illustrative embodiment, is deposited over the device die104with the quantity of approximately 16 to 28 grams (g). In yet some embodiments, the grooves124act to catch excess thermal interface material118when the lid120is placed on the device die104.

The thermal interface material118has a high thermal conductivity and adheres to both the lid120and the device die104and/or the molding compound112. In some embodiments, the thermal interface material118is made of silicones, such as polymers including silken, carbon, hydrogen, oxygen and sometimes other elements. Alternatively, the thermal interface material118may also be made of other materials such as alumina (Al3O3) or zinc oxide (ZnO2) mixed with silicone and other applicable materials.

In some embodiments, the thickness, T, of the thermal interface material118between the device die104and the lid120is in a range from about 10 micrometers (μm) to about 300 μm. In some embodiments, the thermal interface material118has a thermal conductivity, of between about 3 watts per meter kelvin (W/m·K) to about 5 W/m·K or more. Accordingly, the heat generated in the device die104may dissipate to the lid120, and then dissipate to the external environment. Certain types of device dies generate a large amount of heat during operation. For example, device dies that include central processing unit (CPU), graphical processing unit (GPU), and/or field-programmable gate array (FPGA) tend to generate large amount of heat.

In operation, the chip or device die104is positioned over the substrate102and includes the connectors110to provide electrical connections for the device die104. The device die104and the substrate102are placed in a mold. A molding process is performed in which the molding compound112is formed above the substrate102and around the device die104. The molding process is operable to position the molding compound112in between voids136, e.g., spaces between the connectors110, and around the device die104to support the device die104and provide structural integrity. The substrate102, the device die104and the molding compound112form the package structure122. The package structure122is removed from the mold. After the package structure122has been removed from the mold the groove124is formed in the outer portion or peripheral region116of the molding compound112. The thermal interface material118is then applied over the second surface108at the device die104and at least a portion of the molding compound112where the groove124is located, such that the thermal interface material118fills the groove124. The lid120is then positioned over the thermal interface material118and bonded thereto.

The groove124helps prevent the thermal interface material118from bleeding or otherwise extending past the outer edge130of the molding compound112. Bleeding of the thermal interface material118may cause warpage within the semiconductor device100, which can create issues in yielding and contamination. The groove124acts to catch excess thermal interface material118when the lid120is placed on the device die104.

Referring now toFIGS. 2A through 2D, a semiconductor device or package200according to another illustrative embodiment is presented. Similar to the embodiments described above with respect toFIGS. 1A through 1D, the semiconductor device200includes the substrate102and the device die104positioned over the substrate102. The device die104is bonded to the top side103of the substrate102. The first surface106of the device die104faces the substrate102and the device die104is electrically connected to the substrate102via the connectors110.

The semiconductor device200further includes the molding compound112formed over the substrate102and surrounding the device die104. The molding compound112includes the structural interface114.FIG. 2Cis a quarter-sectional view of the semiconductor device200illustrated inFIG. 2Bshown in an isometric arrangement, with the structural interface114shown by hidden lines.FIG. 2Dis a detailed, isometric view ofFIG. 2C, illustrating the molding compound112with the structural interface114in accordance with some embodiments.

In some aspects, the structural interface114is formed along the outer portion or peripheral region116of the molding compound112. The outer portion or peripheral region116of the molding compound112is distal to the outer edge123of the device die104.

In some aspects, the structural interface114is a lip or dam140extending from a top surface142of the molding compound112along the outer region or peripheral region116of the molding compound112. In some aspects, the lip or dam140extends along the outer edge130of the molding compound112such that the outer surface of the lip140is flush, or otherwise coplanar, with the outer edge130of the molding compound112. In some aspects, the lip140is an integral part of the molding compound112. In an embodiment, the mold is configured such that the lip140will be formed during the molding process such that the lip140is an integral part of the molding compound112.

In another aspect, the molding compound112is reduced or planarized by, for example, grinding, CMP, etching, or another process to form the lip or dam140. In some embodiments, the molding compound112may be formed to initially extend over and cover top surfaces of device die104. The planarization process (e.g., a mechanical grinding, chemical mechanical polish (CMP), or other etch back technique) may be employed to remove portions of the molding compound112to form the lip or dam140. In some embodiments, the planarization process (e.g., a mechanical grinding, chemical mechanical polish (CMP), or other etch back technique) may be employed to remove excess portions of the molding compound112over the device die104to expose the device die.

In an embodiment, the lip140extends continuously along the outer edge of the molding compound112. In an alternative embodiment, the lip140is one of a plurality of lips each of which is positioned in the corner region126of the molding compound112. In an embodiment, the lip140includes a first leg150and a second leg152. In some embodiments, the lip140has a height, h, of between approximately 100 um and 200 um. In some embodiments, the lip140has a width, w, of between approximately 300 um and 350 um. And in some embodiments, the lip140has a length of between approximately 300 um and 350 um. The lip or dam140helps prevent the thermal interface material118from extending beyond the outer edge130of the molding compound112.

The semiconductor device200further includes the thermal interface material118and the lid120. The thermal interface material118is positioned over the molding compound112and the device die104. The thermal interface material118joins the lid120to one or both of the molding compound112and the device die104.

Referring toFIG. 3, another embodiment illustrating a second groove or a second trench260may be formed around the outer edge of a first groove224, such as the groove124shown inFIGS. 1A through 1D, in the molding compound112. In some embodiments, a perimeter of the first groove224is encircled by the second groove or the second trench260. The second groove260may be formed in a separate step than the first groove224. In one aspect, the second groove260is formed before the first groove224. Yet in another aspect, the second groove260is formed after the first groove224. The second groove260may have a depth of approximately 50 μm to 150 μm. In some embodiments, the second groove260is formed after the first groove224and merely extends the first groove224such that the second groove260becomes part of the first groove224. The depth of the first groove224and the depth of the second groove260may be the same or different so long as the respective depths are between approximately 50 μm to 150 μm. In some aspects, the first groove224has a depth greater than the second groove260. And yet, in alternative aspects, the second groove260has a depth greater than the first groove224. For example, in an embodiment, the first groove224has a length, L, of approximately 4 mm, and the second groove260has a length of approximately 4 to 4.5 mm. In this embodiment, the first groove224may have a width, W, of approximately 1 mm, and the second groove260has a width of approximately 1 to 1.5 mm.

In an illustrative embodiment, an outer edge262of the second groove260is approximately 850 micrometers (μm) from the outer edge130of the molding compound112. In another illustrative embodiment, the outer edge262of the second groove260is approximately 300 μm from the outer edge130of the molding compound112. The outer edge262of the second groove260may be approximately 300 μm to 850 μm from the outer edge130of the molding compound112.

Referring now toFIG. 4, experimental data is presented via a box-plot type graph. Experiments were conducted on four different packages. Each of the four different packages was subjected according to a high temperature warpage specification. In the high temperature warpage specification, each of the four different packages was heated to 260° C. and then allowed to cool. The amount of warpage, measured in micrometers, was then measured. It is desirable for the package warpage to be under 60 μm.

In experiment 1, the packages tested did not include grooves in the molding compound that surrounded the device die. A thermal interface material was deposited only over the device die such that no thermal interface material was deposited over the molding compound. The median warpage for these type packages was 81 μm, which is above the desired 60 μm threshold.

In experiment 2, the packages tested did not include grooves in the molding compound that surrounded the device die. The thermal interface material was deposited over the device die, the same as was deposited in experiment 1, and, additionally, over portions of the molding compound. The thermal interface material was deposited in an L-shaped over the molding compound in the four corners of the package. The median warpage for these types of packages was 66 μm, which is above the 60 μm threshold.

In experiment 3, the packages tested included a groove formed in the four corners of the package. The groove had two perpendicular legs extending partially along a respective edge of the package. The clearance between the outer edge of the package, which in this case is the outer edge of the molding compound, and an outer edge of the groove was approximately 850 μm. Each leg had a width of approximately 1 mm, a length of approximately 4 mm and a depth of approximately 100 μm. The thermal interface material was deposited over the device die and over each of the grooves in the same manner as it was deposited in experiment 2. The median warpage for these types of packages was 55 μm, which is within the desired 60 μm threshold.

In experiment 4, the packages tested included a groove formed in the four corners of the package. The groove had two perpendicular legs extending partially along a respective edge of the package. The clearance between outer edge of the package, which in this case is the outer edge of the molding compound, and an outer edge of the groove was approximately 300 μm. Each leg had a width of approximately 1 μm, a length of approximately 4 mm and a depth of approximately 100 μm. The thermal interface material was deposited over the device die in over each of the grooves in the same manner as it was deposited in experiments 2 and 3. The median warpage for these types of packages was 43 μm, which is within the desired 60 μm threshold.

It is desirable for a packages warpage to be less than 60 μm as specifications often require the warpage to be less than 60 μm. Additionally, it is also desirable to prevent the thermal interface material, which is sometimes used to combat warpage, from bleeding or otherwise extending beyond the outer edge of the package, which in some instances is the outer edge of the molding compound. Thermal interface material bleeding from package edge can create issues with yielding, contamination and warpage control.

In an embodiment, a device includes a substrate with a die over the substrate. A molding compound surrounds the die and includes a structural interface formed along a peripheral region of the molding compound.

In an embodiment, a device includes a substrate and a chip over the substrate. A molding compound surrounds the chip. The molding compound includes a peripheral region distal to the chip with a groove formed in the peripheral region of the molding compound.

In an embodiment, a method includes the steps of positioning a die over a substrate, forming a molding compound around the die, and forming a groove in a peripheral region of the molding compound.