Technical solutions are described for executing a plurality of computer-executable synchronous input/output (I/O) commands received by a storage control unit in a multiple virtual storage system. An example method includes receiving a set of synchronous I/O commands, each of the commands received from a respective operating system from a plurality of operating systems. The method further includes selecting, from the set of synchronous I/O operations, a subset of synchronous I/O commands, and allocating a shared resource to the subset of synchronous I/O commands. The method further includes executing each synchronous I/O command from the selected subset of synchronous I/O commands concurrently.

The present application relates generally to input/output (I/O) on a multiple virtual storage (MVS), and more specifically, to improving execution of synchronous I/O operations from multiple operating systems accessing the MVS.

BACKGROUND

In general, the technical field discussed herein includes communications between servers and storage control units over a storage area network (SAN) involving multiple switches and multiple layers of a protocol stack. Contemporary implementations of these communications between servers and storage control units include asynchronous access operations by operating systems within the SAN. Asynchronous access operations require queues and schedulers for initiating the requests, along with interruptions for any associated context switch for processing a completion status. The queues, schedulers, and interruptions result in asynchronous overhead that adds significant latency and processing delays across the SAN.

A SAN, as described by the Storage Networking Industry Association (SNIA), is a high performance network that facilitates storage devices and computer systems to communicate with each other. In large enterprises, multiple computer systems or servers have access to multiple storage control units within the SAN. Typical connections between the servers and control units use technologies such as Ethernet or Fibre-Channel, with associated switches, I/O adapters, device drivers and multiple layers of a protocol stack. Fibre-channel, for example, as defined by the INCITS T11 Committee, defines physical and link layers FC0, FC1, FC2 and FC-4 transport layers such as the Fibre Channel Protocol (FCP) for SCSI and FC-SB-3 for Fibre Connectivity (FICON).

Synchronous I/O causes a software thread to be blocked while waiting for the I/O to complete, but avoids context switches and interrupts. Synchronous I/O works well when the I/O is locally attached with minimal access latency, but as access times increase, the non-productive processor overhead of waiting for the I/O to complete becomes unacceptable for large multi-processing servers. Hence, server access to SAN storage generally uses asynchronous I/O access techniques, due to the large variation in access times, and even the minimum access times of the SAN storage when using synchronous I/O access with the protocols such as Fibre-Channel.

SUMMARY

According to an embodiment, a computer-implemented method for executing a plurality of computer-executable synchronous input/output (I/O) commands in a multiple virtual storage system, includes receiving, by a processor, a set of synchronous I/O commands. The set of commands includes a plurality of synchronous I/O commands, each received from a respective operating system from a plurality of operating systems. The computer-implemented method also includes selecting, from the set of synchronous I/O commands, a subset of synchronous I/O commands. The computer-implemented method also includes allocating a shared resource to the subset of synchronous I/O commands. The computer-implemented method also includes executing, concurrently, each synchronous I/O command from the selected subset of synchronous I/O commands.

According to another embodiment, a computer program product facilitates executing a plurality of computer-executable synchronous input/output (I/O) commands in a multiple virtual storage system. The computer program product includes a computer readable storage medium having program instructions executable by a processor. The program instructions include instructions to receive a set of synchronous I/O commands that includes the plurality of synchronous I/O commands, each received from a respective operating system from a plurality of operating systems. The program instructions also includes instructions to select, from the set of synchronous I/O commands, a subset of synchronous I/O commands, where the subset of synchronous I/O commands includes a predetermined number of synchronous I/O commands to be executed concurrently. The program instructions also includes instructions to allocate a shared resource to the subset of synchronous I/O commands. The program instructions also includes instructions to execute, concurrently, each synchronous I/O command from the selected subset of synchronous I/O commands.

According to another embodiment, a system for managing execution of a plurality of computer-executable synchronous input/output (I/O) commands includes a memory and a processor communicably coupled with the memory. The processor receives a set of synchronous I/O commands that includes the plurality of synchronous I/O commands, each received from a respective operating system from a plurality of operating systems. The processor also selects, from the set of synchronous I/O commands, a subset of synchronous I/O commands, where the subset of synchronous I/O commands includes a predetermined number of synchronous I/O commands to be executed concurrently. The processor also allocates a shared resource to the subset of synchronous I/O commands. The processor also executes, concurrently, each synchronous I/O command from the selected subset of synchronous i/o commands.

DETAILED DESCRIPTION

In view of the above, technical solutions disclosed herein may include a synchronous system, method, and/or computer program product (herein synchronous system) that concurrently executes multiple synchronous I/O operations, each from a respective operating system, for efficient work-load management.

The technical solutions described herein further improve a synchronous input/output (I/O) central processing unit (CPU) that receives synchronous read and write I/O operations from multiple operating systems, or the initiation of an I/O operation and subsequent synchronous test for completion. For example enterprise servers, which may use MVS, may attempt to share I/O adapters. The technical solutions described herein facilitate the MVS to facilitate enterprise servers, which may execute different operating systems and applications, to share I/O adapters to provide virtualization and sharing of such adapters even in case the enterprise servers use synchronous I/O access. For example, the MVS may implement a firmware-based approach with minimal over-head and large scalability for access to shared hardware resources.

The system, for example, uses a synchronous low latency protocol running over an interface link such as peripheral component interconnect express (PCIe) to communicate directly between a processor (also referred to herein as a server) and a storage subsystem. The storage subsystem receives mailbox commands, delivered from the CPU over the PCIe link, that request the synchronous execution of read/write commands. In the context of the technical solutions described herein, a mailbox is a named, logical queue of ordered messages that is maintained by a cross-system coupling facility to hold messages that have been sent to a dispatched unit but have not yet been received by that dispatcher unit. Should the message not be delivered or received as expected, the original sender receives return and reason codes from several sources, including the cross-system coupling facility and the receiver. A command that is associated with accessing and/or operating on one or more of the mailboxes may be referred to as a mailbox command.

For example, in a read command, if the data is not already in the control unit cache the synchronous command ends unsuccessfully. The control unit may initiate processing to asynchronously read the data into the control unit cache so that it can be read via traditional I/O processing. If the data was in the cache, the data may be transferred to the host memory and the synchronous I/O CPU instruction completes successfully. Write operations can transfer data from host memory to the control unit cache of one or more nodes within the control unit.

Embodiments of synchronous I/O described herein when compared to traditional I/O may be utilized to eliminate the overhead associated with a dispatcher, improve transactional latency, preserve contents of L1 and L2 cache by eliminating a context switch, and can reduce lock contention on data by reducing latency.

Described herein is a dynamic I/O paradigm for storage that can perform both synchronous and asynchronous (or traditional) processing from the application/middleware point of view. When applied to middleware, such as DB2® from IBM®, this new paradigm can result in faster performance. Current versions of DB2 can only have one I/O operation writing to the log at any one time. This single threaded process is highly dependent on the latency of these log write commands for the total throughput that can be accommodated for processing transactions. Embodiments of the synchronous I/O paradigm described herein can reduce the amount of time that it takes to write to the log. Note, that multi-write technology (e.g., zHyperWrite® technology produced by IBM) provides a way of eliminating the latency required by synchronous replication of data. The combination of embodiments described herein with the use of multi-write technology can provide the ability to maintain continuous availability with multi-switch technology (e.g., HyperSwap technology produced by IBM) while getting the benefits of synchronous I/O.

The workloads that run on the z/OS® (an OS from IBM) can typically see very high cache hit ratios (e.g., 90 percent) for read operations. This means that a high percent of the time the data is found in a dynamic random access memory (DRAM) cache in the storage subsystem (e.g., a persistent storage control unit), resulting in reduced I/O service times. These high cache hit ratios can be the result of a long tradition of close integration of the I/O stack from the applications ability to pass cache hints on I/O operations through optimized caching algorithms in the storage subsystem. When the data required for a read request is in DRAM in the storage subsystem it is amenable to being transferred to the host with the new synchronous I/O paradigm. If a cache miss occurs, the storage subsystem can initiate the process to bring the data into cache but synchronously notify the host to execute the I/O operation using the traditional asynchronous model.

Utilizing embodiments described herein to avoid the un-dispatching and re-dispatching of critical applications and middleware, can lead to a reduction in OS overhead and eliminate the L1 and L2 cache damage that can occur when a context switch occurs for a different application. Reducing the L1 and L2 cache damage and re-dispatching of work can lead to a significant reduction in CPU cost.

When embodiments are applied to DB2 executing on a z/OS platform, utilizing embodiments to accelerate read I/O and database logging can reduce DB2 transactional latency and accelerate transaction processing on the z/OS platform.

In addition, improving database log throughput can reduce cost by requiring fewer data sharing instances (LPARs, I/O connections, log devices) to achieve the workload requirements. It can also avoid forcing clients to re-engineer the workloads in order to avoid hitting constraints.

Turning now toFIG. 1, communication schematics100of a traditional I/O and a synchronous I/O when updating data stored on a peripheral storage device are generally shown in accordance with embodiments. As shown on the right side ofFIG. 1, performing traditional I/O operations includes receiving a unit of work request124at an operating system (OS)122in a logical partition (LPAR). The unit of work can be submitted, for example, from an application or middleware that is requesting an I/O operation. As used herein the term “unit of work” refers to dispatchable tasks or threads.

In response to receiving the unit of work request, the OS122performs the processing shown in block104to request a data record. This processing includes scheduling an I/O request by placing the I/O request on a queue for the persistent storage control unit (CU)102that contains the requested data record, and then un-dispatching the unit of work. Alternatively, the application (or middleware) can receive control back after the I/O request is scheduled to possibly perform other processing, but eventually the application (or middleware) relinquishes control of the processor to allow other units of work to be dispatched and the application (or middleware) waits for the I/O to complete and to be notified when the data transfer has completed with or without errors.

When the persistent storage control unit (SCU)102that contains the data record is available for use and conditions permit, the I/O request is started by the OS issuing a start sub-channel instruction or other instruction appropriate for the I/O architecture. The channel subsystem validates the I/O request, places the request on a queue, selects a channel (link) to the persistent SCU102, and when conditions permit begins execution. The I/O request is sent to a persistent SCU102, and the persistent SCU102reads the requested data record from a storage device(s) of the persistent SCU102. The read data record along with a completion status message is sent from the persistent SCU102to the OS122. Once the completion status message (e.g., via an I/O interrupt message) is received by the OS122, the OS122requests that the unit of work be re-dispatched by adding the unit of work to the dispatch queue. This includes re-dispatching the LPAR to process the interrupt and retrieving, by the I/O supervisor in the OS, the status and scheduling the application (or middleware) to resume processing. When the unit of work reaches the top of the dispatch queue, the unit of work is re-dispatched.

Still referring to the traditional I/O, once the data record is received by the OS122, the OS122performs the processing in block106to update the data record that was received from the persistent SCU102. At block108, the updated data record is written to the persistent SCU102. As shown inFIG. 1, this includes the OS122scheduling an I/O request and then un-dispatching the instruction. The I/O request is sent to a persistent SCU102, and the persistent SCU102writes the data record to a storage device(s) of the persistent SCU102. A completion status message (e.g., an interruption message) is sent from the persistent SCU102to the OS122. Once the completion status message is received by the OS122, the OS122requests that the unit of work be re-dispatched by adding the unit of work to the dispatch queue. When the unit of work reaches the top of the dispatch queue, the unit of work is re-dispatched. At this point, the unit of work is complete. As shown inFIG. 1, the OS122can perform other tasks, or multi-task, while waiting for the I/O request to be serviced by the persistent SCU102.

The traditional I/O process is contrasted with a synchronous I/O process. As shown inFIG. 1, performing a synchronous I/O includes receiving a unit of work request at the OS122. In response to receiving the unit of work request, the OS122performs the processing shown in block114which includes synchronously requesting a data record from the persistent SCU112and waiting until the requested data record is received from the persistent SCU112. Once the data record is received by the OS122, the OS122performs the processing in block116to update the data record. At block118, the updated data record is synchronously written to the persistent SCU112. A synchronous status message is sent from the persistent SCU112to the OS122to indicate the data has been successfully written. At this point, the unit of work is complete. As shown inFIG. 1, the OS122is waiting for the I/O request to be serviced by the persistent SCU112and is not performing other tasks, or multi-tasking, while waiting for the I/O request to be serviced. Thus, in an embodiment, the unit of work remains active (i.e., it is not un-dispatched and re-dispatched) until the OS122is notified that the I/O request is completed (e.g., data has been read from persistent SCU, data has been written to persistent SCU, error condition has been detected, and the like).

Thus, as shown inFIG. 1, synchronous I/O provides an interface between a server and a persistent SCU that has sufficiently low overhead to allow an OS to synchronously read or write one or more data records. In addition to the low overhead protocol of the link, an OS executing on the server can avoid the scheduling and interruption overhead by using a synchronous command to read or write one or more data records. Thus, embodiments of synchronous I/O as described herein when compared to traditional I/O not only reduce the wait time for receiving data from a persistent SCU, they also eliminate steps taken by a server to service the I/O request. Steps that are eliminated can include the un-dispatching and re-dispatching of a unit of work both when a request to read data is sent to the persistent SCU and when a request to write data is sent to the persistent SCU. This also provides benefits in avoiding pollution of the processor cache that would be caused by un-dispatching and re-dispatching of work.

As used herein, the term “persistent storage control unit” or “persistent SCU” refers to a storage area network (SAN) attached storage subsystem with a media that will store data that can be accessed after a power failure. As known in the art, persistent SCUs are utilized to provide secure data storage even in the event of a system failure. Persistent SCUs can also provide backup and replication to avoid data loss. A single persistent SCU is typically attached to a SAN and accessible by multiple processors.

As used herein, the term “synchronous I/O” refers to a CPU synchronous command that is used to read or write one or more data records, such that when the command completes successfully, the one or more data records are guaranteed to have been transferred to or from the persistent storage control unit into host processor memory.

Turning now toFIG. 2, a block diagram of a system200(e.g., synchronous system) for performing synchronous I/O is generally shown in accordance with an embodiment. The system200shown inFIG. 2includes one or more application/middleware210, one or more physical processors220, and one or more persistent SCUs230. The application/middleware210can include any application software that requires access to data located on the persistent SCU230such as, but not limited to a relational database manager212(e.g. DB2®), an OS214, a filesystem (e.g., z/OS Distributed File Service System, z File System produced by IBM), a hierarchical database manager (e.g. IMS® produced by IBM), or an access method used by applications (e.g. virtual storage access method, queued sequential access method, basic sequential access method). As shown inFIG. 2, the database manager212can communicate with an OS214to communicate a unit of work request that requires access to the persistent SCU230. The OS214receives the unit of work request and communicates with firmware224located on the processor220to request a data record from the persistent SCU230, to receive the data record from the persistent SCU230, to update the received data record, to request the persistent SCU230to write the updated data record, and to receive a confirmation that the updated data recorded was successfully written to the persistent SCU230. The firmware224accepts the synchronous requests from the OS214and processes them. Firmware232located on the persistent SCU230communicates with the firmware224located on the processor220to service the requests from the processor220in a synchronous manner.

As used herein, the term “firmware” refers to privileged code executing on a processor that interfaces with the hardware used for the I/O communications; a hypervisor; and/or other OS software.

Embodiments described herein utilize peripheral component interconnect express (PCIe) as an example of a low latency I/O interface that may be implemented by embodiments. Other low latency I/O interfaces, such as, but not limited to Infiniband™ as defined by the InfiniBand Trade Association and zSystems coupling links can also be implemented by embodiments.

Turning now toFIG. 3, a block diagram of an environment300including a synchronous I/O link interface305is depicted in accordance with an embodiment. As shown inFIG. 3, the environment300utilizes the synchronous I/O link interface305as an interface between a server310and a persistent SCU320. The synchronous I/O link interface305has sufficiently low latency and protocol overhead to allow an OS of the server310to synchronously read or write one or more data records from the persistent SCU320. In addition to the low protocol overhead of the link, the OS can avoid the overhead associated with scheduling and interrupts by using a synchronous command via the synchronous I/O link interface305to read or write one or more data records. The synchronous I/O link interface305, for example, can be provided as an optical interface based on any PCIe base specification (as defined by the PCI-SIG) using the transaction, data link, and physical layers. The synchronous I/O link interface305may further include replay buffers and acknowledgement credits to sustain full bandwidth.

The server310is configured to provide at least one synchronous I/O link interface305having at least one synchronous I/O link315to allow connection to at least one persistent SCU (e.g., persistent SCU320). It can be appreciated that two or more synchronous I/O links315may be required for each connection to a persistent SCU. It can also be appreciated that two or more synchronous I/O links315may support switch connections to a persistent SCU. In an exemplary embodiment, where PCIe is utilized, the server310comprises a PCIe root complex330for the interface link315, while the persistent SCU320comprises a PCIe endpoint335for the control unit synchronous I/O interface305.

Turning now toFIG. 4, a block diagram of an environment400for performing synchronous I/O with respect to a mailbox command and read operation is depicted in accordance with an embodiment. As shown inFIG. 4, the environment400includes the server310(e.g., includes the application/middleware210and processor220illustrated inFIG. 2) and a persistent SCU320(e.g., includes persistent CU230illustrated inFIG. 2). The server310includes a LPAR411that may execute an operating system, and may include memory locations for a data record413and an associated suffix415. The server310may further include a status area421comprising a device table423that includes one or more device table entries (DTE) and a status table427that includes one or more status pages. The status area421further may include I/O address translation table (IOAT)425. The device table423and the IOAT table427are data structures used by the firmware224to store the mappings, such as, between virtual addresses and physical addresses, and the devices (SCUs) being accessed using the physical addresses. In addition, the status area421may include a function table entry (FTE), which is a data structure used by a function table to indicate access to a specified synchronous I/O link. The persistent SCU320includes at least one mailbox440and a data record450. In an example, the status area421may be part of the LPAR411.

In operation, synchronous I/O commands issued by the OS of the LPAR411are processed by the firmware224to build a mailbox command460that is forwarded to the persistent SCU320. For example, upon processing a synchronization I/O command for the OS by the firmware224of the server310, the firmware224prepares hardware of the server310and sends the mailbox command460to the persistent SCU320. The mailbox command460is sent to the persistent SCU320in one or more memory write operations (e.g., over PCIe, using a PCIe base mailbox address that has been determined during an initialization sequence described below). A plurality of mailboxes can be supported by the persistent SCU320for each synchronous I/O link305. A first mailbox location of the plurality of mailboxes can start at the base mailbox address, with each subsequent mailbox location sequentially located 256-bytes after each other. After the mailbox command460is sent, the firmware224polls the status area421(e.g., a status field427) for completion or error responses. In embodiments, the status area421is located in privileged memory of the server310and is not accessible by the OS executing on the LPAR411. The status area421is accessible by the firmware224on the server310and the firmware224can communicate selected contents (or information related to or based on contents) of the status area421to the OS (e.g., via a command response block).

In general, a single mailbox command460is issued to each mailbox at a time. A subsequent mailbox command will not issue to a mailbox440until a previous mailbox command to the mailbox440has completed or an error condition (such as a timeout, when the data is not in cache, error in the command request parameters, etc.) has been detected. Successive mailbox commands for a given mailbox440can be identified by a monotonically increasing sequence number. Mailboxes can be selected in any random order. The persistent SCU320polls all mailboxes for each synchronous I/O link315and can process the commands in one or more mailboxes in any order. In an embodiment, the persistent SCU320polls four mailboxes for each synchronous I/O link315. Receipt of a new mailbox command with an incremented sequence number provides confirmation that the previous command has been completed (either successfully or in error by the server310). In an embodiment, the sequence number is also used to determine an offset of the status area421. The mailbox command can be of a format that includes 128-bytes. The mailbox command can be extended by an additional 64-bytes or more in order to transfer additional data records. In an embodiment, a bit in the mailbox command is set to indicate the absence or presence of the additional data records.

The mailbox command can further specify the type of data transfer operations, e.g., via an operation code. Data transfer operations include read data and write data operations. A read operation transfers one or more data records from the persistent SCU320to a memory of the server310. A write operation transfers one or more data records from the memory of the server310to the persistent SCU320. In embodiments, data transfer operations can also include requesting that the persistent SCU320return its World Wide Node Name (WWNN) to the firmware in the server. In further embodiments, data transfer operations can also request that diagnostic information be gathered and stored in the persistent SCU320.

In any of the data transfer operations the contents of the mailbox command can be protected using a cyclic redundancy check (CRC) (e.g., a 32 bit CRC). In an embodiment, the mailbox command can be protected by a checksum. In an embodiment, if the persistent SCU320detects a checksum error, a response code to indicate the checksum error is returned. Continuing withFIG. 4, a synchronous I/O read data record operation will now be described. For instance, if a mailbox command460includes an operation code set to read, the persistent SCU320determines if the data record or records450are readily available, such that the data transfer can be initiated in a sufficiently small time to allow the read to complete synchronously. If the data record or records450are not readily available (or if any errors are detected with the mailbox command460), a completion status is transferred back to the server310. If the read data records are readily available, the persistent SCU320provides the data record450.

In an embodiment, the persistent SCU320processes the mailbox command460, fetches the data record450, provides CRC protection, and transfers/provides the data record450over the synchronous I/O link315. The persistent SCU320provides the data record450as sequential memory writes over PCIe, using the PCIe addresses provided in the mailbox command460. Each data record may use either one or two PCIe addresses for the transfer as specified in the mailbox command460. For example, if length fields in the mailbox command460indicate the data record is to be transferred in a single contiguous PCIe address range, only one starting PCIe address is used for each record, with each successive PCIe memory write using contiguous PCIe addresses. In embodiments, the length fields specify the length in bytes of each data record to be transferred.

The data record450can include a data portion and a suffix stored respectively on data record413and suffix415memory locations of the logical partition411after the data record450is provided. The data record413can be count key data (CKD) or extended count key data (ECKD). The data record413can also be utilized under small computer system interface (SCSI) standards, such as SCSI fixed block commands. Regarding the suffix, at the end of each data record450, an additional 4-bytes can be transferred comprising a 32-bit CRC that has been accumulated for all the data in the data record450. The metadata of the suffix415can be created by an operating system file system used for managing a data efficiently. This can be transferred in the last memory write transaction layer packet along with the last bytes of the data record450, or in an additional memory write.

In addition, a host bridge of the server310performs address translation and protection checks (e.g., on the PCIe address used for the transfers) and provides an indication in the DTE423to the firmware224of the server310when the data read command462is complete. The host bridge can also validate that the received CRC matches the value accumulated on the data transferred. After the last data record and corresponding CRC have been initiated on the synchronous I/O link315, the persistent SCU320considers the mailbox command460complete and is readied to accept a new command in this mailbox440.

In an exemplary embodiment, the server310will consider the mailbox command460complete when all the data records450have been completely received and the corresponding CRC has been successfully validated. For example, the firmware224performs a check of the status area421to determine if the data read462was performed without error (e.g., determines if the DTE423indicates ‘done’ or ‘error’). If the data read462was returned without error and is complete, the firmware then completes the synchronous I/O command. The server310will also consider the mailbox command460complete if an error is detected during the data read462or CRC checking process, error status is received from the persistent SCU320, or the data read462does not complete within the timeout period for the read operation.

Embodiments of the mailbox command460can also include a channel image identifier that corresponds to a logical path previously initialized by the establish-logical-path procedure, for example over a fibre-channel interface. If the logical path has not been previously established, a response code corresponding to this condition can be written to the status area421to indicate that the logical path was not previously established.

The mailbox command block can also include a persistent SCU image identifier that corresponds to a logical path previously initialized by the establish-logical-path procedure. If the logical path has not been previously established, a response code corresponding to this condition can be written to the status area421to indicate that the logical path was not previously established.

The mailbox command block can also include a device address within the logical control unit (e.g., a specific portion of the direct access storage device located in the storage control unit) that indicates the address of the device to which the mailbox command is directed. The device address should be configured to the persistent SCU specified, otherwise the persistent SCU320can return a response code (e.g., to the status area421in the server310) to indicate this condition.

The mailbox command block can also include a link token that is negotiated by the channel and the persistent SCU320each time the synchronous I/O link is initialized. If the persistent SCU320does not recognize the link token, it can return a value to the status area421that indicates this condition.

The mailbox command block can also include a WWNN that indicates the WWNN of the persistent SCU to which the command is addressed. In embodiments, it is defined to be the 64-bit IEEE registered name identifier as specified in the T11 Fibre-Channel Framing and Signaling 4 (FC-FS-4) document. If the specified WWNN does not match that of the receiving persistent SCU, then a response code indicating this condition is returned to the processor.

The mailbox command block can also include device specific information that is used to specify parameters specific to this command. For example, for enterprise disk attachment when a write or read is specified by the operation code, device specific information can include the prefix channel command. In another example, when the operation code specifies that the command is a diagnostic command, the device specific information can include a timestamp representing the time at which this command was initiated and a reason code.

The mailbox command can also include a record count that specifies the number of records to be transferred by this synchronous I/O command (or mailbox command). A synchronous I/O link is accessible by an OS using a unique function handle that is associated with a specific virtual function.

When PCIe is being utilized with a mailbox command that includes multiple 32 bit words, the mailbox command can include one or more PCIe data addresses in the following format: PCIe data address bits 63:32 in word “n” to specify the word-aligned address of the location in memory (e.g., in the processor) where data will be fetched for a write and stored for a read operation; and PCIe data addressing bits 31:2 in word “n+1”. In addition word n+1 can include an end or record bit that can be set to indicate that the last word specified is the last word of the record that is to be read or written.

The mailbox command can also include a mailbox valid bit(s) that indicates whether the mailbox command is valid and whether the entire mailbox command has been received.

In view of the above, a synchronous I/O write data record operation will now be described with respect toFIG. 5in accordance with an embodiment. As shown inFIG. 5, the environment500includes the server310and the persistent SCU320. The server310includes the logical partition411comprising memory locations for the data record413and the suffix415and the status area421comprising the DTE423and the status field427. The persistent SCU320includes at least one mailbox440and a data record550once written. Additional components are not illustrated to avoid repetition.

In operation, for example, upon processing a synchronization I/O command for the OS by a firmware of the server310, the firmware prepares hardware of the server310and sends the mailbox command560to mailbox540of the persistent SCU320. As noted above, a plurality of mailboxes can be supported by the persistent SCU320for each synchronous I/O link315. Further, after the mailbox command560is sent, the firmware224polls the status area421(e.g., a status field427) for completion or error responses.

If the mailbox command560, issued to mailbox440, includes an operation code set to write, the persistent SCU320determines if it is able to accept the transfer of the data record or records550. If the persistent SCU320is not able to accept the transfer (or if any errors are detected with this mailbox command560), a completion status is transferred back to the server310. If the persistent SCU320is able to accept the transfer, the persistent SCU320issues memory read requests565for the data.

In an embodiment, the persistent SCU320processes the mailbox command560and issues a read request565over PCIe (using the PCIe addresses provided in the mailbox command560) to fetch the data including the data record413and the suffix415. In response to the read request565, the host bridge of the server310performs address translation and protection checks on the PCIe addresses used for the transfers.

Further, the server310responds with memory read responses570to these requests. That is, read responses570are provided by the server310over the synchronous I/O link305to the persistent SCU320such that the data record550can be written. Each data record may require either one or two PCIe addresses for the transfer as specified in the mailbox command560. For example, if the length fields in the mailbox command560indicate the entire record can be transferred using a single contiguous PCIe address range, only one starting PCIe address is required for each record, with each successive PCIe memory read request using contiguous PCIe addresses. At the end of each data record, the additional data (for example, 8-bytes) will be transferred consisting of the CRC (for example, 32-bit) that has been accumulated for all the data in the record and optionally a longitudinal redundancy check (LRC) or other protection data that has also been accumulated. The total number of bytes requested for each record can be greater than the length of the record (such as by 8-bytes) to include the CRC protection bytes and the additional data (such as 4-bytes long) for the LRC.

After the data and CRC/LRC protection bytes have been successfully received, the persistent SCU320responds by issuing a memory write572(e.g., of 8-bytes of data). The persistent SCU320considers this mailbox command560complete after initiating this status transfer and must be ready to accept a new command in this mailbox540. The server310will consider the mailbox command560complete when the status transfer has been received. For example, the firmware performs a check of the status area521(e.g., determines if the DTE523indicates ‘done’ or ‘error’). The server310will also consider the mailbox command560complete if an error is detected during the data transfer, error status is received from the persistent SCU320, or the status is not received within the timeout period for this operation.

FIG. 6illustrates a block diagram of an environment600performing synchronous I/O with respect to a status operation in accordance with an embodiment. The status operation, for example, can be a completion status. As shown inFIG. 6, the environment600includes the server310and the persistent SCU320. The server310includes a logical partition411and a status area421comprising one or more status fields427. The persistent SCU320includes at least one mailbox440.

In response to a status request670, the completion status (as detected and recorded by the persistent SCU320) is transferred672by the persistent SCU320to the server310. In an embodiment where PCIe is utilized that status is transferred672to a 64-bit PCIe address that is offset from a status base address specified during an initialization exchange sequence. The status offset can be calculated as indicated in Equation 1.
Offset=(Node#*4096)+(Mailbox#*1024)+(Sequence#*256)  Equation 1

In embodiments, when the persistent SCU320completes a read operation successfully, no status is written after the data transfer. The successful reception of the received data with valid CRC is an indication that the operation has completed successfully. In embodiments, when the persistent SCU320completes a write operation, the status is written after the write data has been successfully received. In embodiments, when the persistent SCU320completes a command other than a read operation or a write operation, or it is unable to complete a read or write operation successfully, it transfers672status information to the server.

In embodiments, the status information can include a bit(s) that indicates whether the status information is valid or invalid. The server310can poll on this bit(s) looking for it to indicate valid status information so that it knows that status information has been written.

The status information can also include an error status indicator that indicates whether the mailbox command completed successfully (e.g., write data was successfully written to the persistent SCU320) or not (e.g., write of data was not successfully written to the persistent SCU320). In the event that the mailbox command was not successfully completed, the status information provides additional details about the error that was encountered by the persistent SCU320.

In the event of an error, the status information can include a record number that specifies the record (if any) to which the status information pertains.

In the event of an error, the status information can include a control unit response code that indicates the reason for the synchronous I/O operation failure. Response codes can include, but are not limited to indications that: device-dependent data (e.g., invalid track) is not valid, see response code qualifier for details; incorrect length (e.g., length of data does not match record length); SCU device address invalid; device-dependent error status presented (e.g., data record not available); logical path not established; persistent SCU synchronous I/O busy; read data not immediately available on persistent SCU; write data space not immediately available on persistent SCU; persistent SCU in recovery; checksum error; invalid operation code; sequence number does not match (e.g., mailbox command dropped); link token does not match (e.g., link re-initialized); WWNN does not match (e.g., link connection changed); and/or invalid length.

In the event of an error, the status information can include a persistent SCU response code qualifier whose value may include either an architected value or a model or device dependent value that further describes the condition specified by the response code.

In the event of an error, the status information can include a WWNN of the persistent SCU returning the status information.

In the event of an error, the status information can include a control unit timestamp that indicates when the status condition was detected.

In the event of an error, the status information can include a diagnostic information identifier that indicates that diagnostic information is available in the persistent SCU and can be uniquely identified by the value in this field.

In the event of an error, the status information can include device specific status.

FIG. 7illustrates an example in which the SCU320is being accessed by multiple servers310A and310B. Each of the servers310A and310B are similar to the server310described herein. Thus, the server310A includes one or more LPARs411A-411B and the status area421. Each of the LPARs411A-411B operates a respective operating system, which may be distinct from each other. The status area421includes the device table423, the IOAT table425, and the status table427. The data structures in the status area421may be shared across the operating systems of the LPARs411A-411B. In an example, each LPAR may have a respective status area. The SCU320includes one or more mailboxes440A-440B and one or more data records450A-450B.

The operating systems of the LPARs411A-411B, in response to an I/O operation, may issue a synchronous I/O command to access the data records450A-450B on the persistent SCU320. In response, the firmware224of the server310issues a mailbox command via the synchronous I/O link315, as specified by the synchronous I/O command. The server310may also use the synchronous I/O link315for a mailbox command. Depending on the type of the mailbox command, the persistence SCU320operates as described herein. Of course, it is understood that although only two servers310A and310B are illustrated, the technical solutions described herein may be used in case of more or fewer number of servers.

Thus, for example, an enterprise server may use the persistent SCU112for synchronous I/O operations as described herein to have dynamic access via the low latency links305(such as PCI links), without impairing the access latency of another operating system from the multiple operating systems that may be executing on the enterprise server. To ensure that a first operating system is not affected by operations, or errors in a second operating system, the technical solutions described herein further facilitate full isolation between the operating systems, and in particular errors incurred by the first operating system cannot impair the access by the second operating system. The technical solutions described herein ensure such isolation by managing a pool of shared resources that the multiple operating systems may use. The shared resources may be part of the enterprise server, the SCU, and/or the link.

The technical solutions described herein facilitate controlling access to shared resources in both the server310and the SCU320. For example, the pool of shared resources may include the shared physical link315, the mailboxes440A-440B in the SCU320, the address translation and data protection data structures in the status area421(such as the device table, the IOAT table, and the status table). The system may have a different number of each of the shared resources. For example, the SCU320may include four mailboxes, whereas the server310may contain 1024 DTEs (or any other number of shared resources). Thus, one type of shared resource may have fewer instances than another type of shared resource. In order to minimize firmware access times of control structures, the device table entries used for address translation and protection in typical I/O infrastructures may be extended to also serve as data protection (CRC) context and also for control unit mailbox access controls.

The technical solutions described herein may facilitate the system firmware224to dynamically allocate one or more shared resources to a synchronous I/O command. The firmware224allocates the resources to maintain the isolation among the multiple operating systems of the respective LPARs411A-411B. For example, the firmware224dedicates the shared resources associated with the mailbox command (such as modules updating the DTE, the IOAT table, the CRC computation context, and the mailbox access) to the single OS instance that issued the synchronous I/O command for the duration of that I/O command. After completion of the mailbox command the firmware224frees the shared resources to be available for a subsequent mailbox command for any OS with access to the shared link. Further, the technical solution described herein facilitate executing multiple mailbox commands maintaining the isolation among the multiple operating systems that issued the synchronous I/O commands that result in the mailbox commands.

For example, the multiple operating systems may initiate, substantially concurrently, multiple synchronous I/O commands. Each operating system has its own Function Handle for explicit access to a synchronous I/O link. A link is accessible by an operating system by using the function handle that is associated with a specific virtual function. The multiple synchronous I/O commands may specify a common synchronous I/O link to access the pertinent SCU320. The server firmware224may initiate a mailbox command corresponding to each respective synchronous I/O command. For executing the mailbox command, the firmware224may allocate the data structures of the status area421of the server310. Thus, the firmware allocates shared resources in the server, such as the DTEs and IOAT table entries, which provide address translation and protection and data integrity checking. In addition, the firmware224allocates the mailboxes440A-440B of the SCU320for execution of the mailbox command. The firmware224also allocates the synchronous I/O link as requested by the synchronous I/O commands issued by the operating systems.

FIG. 8illustrates an example of allocation of the shared resources by the firmware224to a synchronous I/O command.FIG. 9illustrates an example flowchart for allocating the shared resources to the synchronous I/O command. For example, the processor220receives one or more synchronous I/O commands from the one or more operating systems that may be executing on the one or more LPARs411A-411B, respectively, as shown at block910. The synchronous I/O commands may be distinct from each other. The firmware224initiates at least one mailbox command for each of the respective synchronous I/O commands. As described herein, for executing the mailbox commands, the firmware uses the shared resources, such as the synchronous I/O link315, the device table423, the IOAT table425, and the status table427. The firmware224, using the technical specifications described herein, allocates the shared resources among a subset of the received synchronous I/O commands for facilitating concurrent execution of the selected subset of synchronous I/O commands, as shown at block920. The selected subset of synchronous I/O commands may include more than one synchronous I/O commands from the received synchronous I/O commands such that each of the selected synchronous I/O commands is associated with the same synchronous I/O link315.

For example, allocating the shared resources among the synchronous I/O commands includes identifying a limiting shared resource, as shown at block922. For example, the resource that has the least number of instances, may be the limiting resource. For example, referring to the example system ofFIG. 8, the system may include four mailboxes per synchronous I/O link and a status page corresponding to each mailbox440. In an example, the status pages427may be divided into groups for each node in the persistent SCU320. For example, the persistent SCU320may include one or more nodes, each node including a mailbox page, where a mailbox page is a collection of mailboxes. In the illustration,FIG. 8depicts a persistent SCU320with two nodes, each including a mailbox page of four mailboxes each. Of course, other persistent SCUs, with different configuration than that illustrated, may be used. The server310may include multiple device table entries and IOAT table entries. Typically, the device table entries and the IOAT table entries outnumber the mailboxes. Thus, the mailboxes440A-B is identified as the limiting resource.

Alternatively, or in addition, the firmware224may be preconfigured with the limiting resource. For example, the firmware224may be preprogrammed to identify the mailboxes440A-B as the limiting resource. Of course, in other examples, some other resource may be identified as the limiting resource.

The firmware224, based on the number of instances of the limiting resource (such as the mailboxes) selects a subset of the received synchronous I/O commands, as shown at block924. For example, the firmware224may select the first X synchronous I/O commands from the received synchronous I/O commands, where X is the number of instances of the limiting resource. The firmware224may select the subset of synchronous I/O commands in any other manner, such as a randomized selection, selection of the last X, or any other selection technique. In addition, each of the synchronous I/O commands in the selected subset use the same common synchronous I/O link315.

Further, the firmware224configures the shared resources for allocation among the selected subset of synchronous I/O commands, as shown at block926. The shared resources are allocated based on the limiting resource. For example, the number of shared resources allocated may be multiples of the number of instances of the limiting resource. For example, the firmware224allocates a predetermined number of DTEs for execution of the selected subset of synchronous I/O commands. For example, the firmware224allocates a block of 8, 12, 16, 32, or any other number of DTEs for the selected subset of synchronous I/O commands. The first DTE in the allocated block may include the lock and toggle bit for the corresponding mailbox. The firmware may further allocate specific DTEs for the specific synchronous command by associating a DTE to a specific mailbox. For example, as shown inFIG. 8, the persistent SCU320has 8 mailboxes (2mailbox pages each with 4 mailboxes), and the firmware224divides the allocated DTEs for the concurrent execution of the selected subset such that each mailbox has a corresponding DTE. In addition, the firmware224may allocate a predetermined number of IOAT table entries for the synchronous I/O command. For example, as illustrated inFIG. 8, the firmware224allocates128IOAT table entries per mailbox in the persistent SCU320. Accordingly, the firmware224allocates128IOAT table entries for the first synchronous I/O command from the selected subset. Further, the firmware224allocates a predetermined number of the status pages for the first synchronous I/O command. For example, in the example illustrated inFIG. 8, each mailbox is allocated a specific status page.

Thus, in an example, the firmware224allocates a first mailbox to the first synchronous I/O command, and further allocates a predetermined number of DTEs, a predetermined number of IOAT table entries, and a status page associated with the first mailbox, to the first synchronous I/O command. In the same manner, the firmware224allocates a second mailbox to the second synchronous I/O command, and further allocates the predetermined number of DTEs, the predetermined number of IOAT table entries, and a status page associated with the second mailbox, to the second synchronous I/O command. The DTEs allocated to the first synchronous I/O command, and the DTEs allocated to the second synchronous I/O command are part of the same device table423, and distinct from each other. The IOAT table entries allocated to the first synchronous I/O command, and the IOAT table entries allocated to the second synchronous I/O command are part of the same IOAT table425, and distinct from each other. The firmware224may allocate resources to the first synchronous I/O command concurrently during allocation of the resources to the second synchronous I/O command. Here, concurrently indicates that the two resource allocation operations may be performed entirely or partially in parallel. Alternatively, the firmware224allocates the resources to the synchronous I/O commands sequentially, such as allocating the resources to the second synchronous I/O command after completing allocation of the resources to the first synchronous I/O command. Once the resources are allocated to a synchronous I/O command, the resources cannot be used by any other operations until the synchronous I/O command completes execution either successfully or in error.

In an example, the server310may share an IOAT table per 32 synchronous I/O links. The IOAT table may include 128K entries shared across the mailboxes from persistent SCUs connected via the synchronous I/O links. The firmware224may allocate32IOAT table entries (which may also be referred to as page table entries (PTE)) per synchronous I/O command.

Once the resources have been allocated, the firmware224proceeds to execute the synchronous I/O commands. For example, each of the selected subset of synchronous I/O commands are executed concurrently, as shown at block930. Since each of the selected subset of synchronous I/O commands is allocated distinct parts of the shared resources, such as the device table423, the IOAT table425, the status table427, and the mailboxes440, and since each of the selected subset of synchronous I/O commands uses the same synchronous I/O link315, the firmware224can execute the commands concurrently. The first synchronous I/O command of the selected subset of synchronous I/O commands does not rely on, and thus does not have to wait for completion of the second synchronous I/O command. Accordingly, the synchronous I/O commands can be executed concurrently. The synchronous I/O commands in the selected subset may not be from the same LPAR, and thus may be from different operating systems.

Once a synchronous I/O command completes execution (either successfully or in error), the firmware224deallocates the shared resources that were allocated to the command, as shown at block940. In an example, the firmware224deallocates the shared resources after each of the selected subset of synchronous I/O commands completes execution. The firmware224may continue to select a next subset of synchronous I/O commands for execution from the received synchronous I/O commands.

For example, consider an example scenario in which eight separate operating systems, executing in respective LPARs, each issue a respective synchronous I/O command. Further consider that the shared resources are as illustrated inFIG. 8, where the persistent SCU has four mailboxes per synchronous I/O link. Thus, the limiting resource in this case is the mailboxes. Accordingly, in such an exemplary scenario, the firmware224selects four of the received eight synchronous I/O commands. Each of the selected synchronous I/O command is allocated a corresponding mailbox and the predetermined number of DTEs, IOAT table entries, and status pages. Thus, each selected synchronous I/O command is allocated isolated parts of the resources from the shared pool of resources. Accordingly, the four selected synchronous I/O commands are concurrently executable. The remaining four synchronous I/O commands from the received eight commands, may receive a resources not available response from the firmware224, which may prompt the respective operating systems to retry after a predetermined duration. Alternatively or in addition, the remaining four commands may be queued for further execution, initiated on an alternate link, or selected as in a next subset of synchronous I/O commands for concurrent execution.

Referring now toFIG. 10, there is shown an embodiment of a processing system1000for implementing the technical solutions herein. In this embodiment, the processing system1000has one or more central processing units (processors)1001a,1001b,1001c, etc. (collectively or generically referred to as processor(s)1001). The processors1001, also referred to as processing circuits, are coupled via a system bus1002to system memory1003and various other components. The system memory1003can include read only memory (ROM)1004and random access memory (RAM)1005. The ROM1004is coupled to system bus1002and may include a basic input/output system (BIOS), which controls certain basic functions of the processing system1000. RAM is read-write memory coupled to system bus1002for use by processors1001.

FIG. 10further depicts an input/output (I/O) adapter1006and a network adapter907coupled to the system bus1002. I/O adapter1006may be a small computer system interface (SCSI) adapter that communicates with a hard disk1008and/or tape storage drive1009or any other similar component. I/O adapter1006, hard disk1008, and tape storage drive909are collectively referred to herein as mass storage1010. Software1011for execution on processing system1000may be stored in mass storage1010. The mass storage1010is an example of a tangible storage medium readable by the processors1001, where the software1011is stored as instructions for execution by the processors1001to perform a method, such as the process flows as noted above. Network adapter1007interconnects system bus1002with an outside network1012enabling processing system1000to communicate with other such systems. A screen (e.g., a display monitor)1015is connected to system bus1002by display adapter1016, which may include a graphics controller to improve the performance of graphics intensive applications and a video controller. In one embodiment, adapters1006,1007, and1016may be connected to one or more I/O buses that are connected to system bus1002via an intermediate bus bridge (not shown). Suitable I/O buses for connecting peripheral devices such as hard disk controllers, network adapters, and graphics adapters typically include common protocols, such as the Peripheral Component Interconnect (PCI). Additional input/output devices are shown as connected to system bus1002via an interface adapter1020and the display adapter1016. A keyboard1021, mouse1022, and speaker1023can be interconnected to system bus1002via interface adapter1020, which may include, for example, a Super I/O chip integrating multiple device adapters into a single integrated circuit.

Thus, as configured inFIG. 10, processing system1000includes processing capability in the form of processors1001, and, storage capability including system memory1003and mass storage1010, input means such as keyboard1021and mouse1022, and output capability including speaker1023and display1015. In one embodiment, a portion of system memory1003and mass storage1010collectively store an OS, such as the z/OS or AIX OS from IBM Corporation, to coordinate the functions of the various components shown inFIG. 10.

Technical effects and benefits of the embodiments herein provide advantages over asynchronous/traditional I/O commands by avoiding overhead of interrupt processing, context switch and un-dispatch/re-dispatch of the unit of work.

For instance, asynchronous/traditional I/O commands include the disadvantage that while waiting on an I/O operation to complete, a processor executes other productive work, causing overhead for un-dispatch and re-dispatch, context switch overhead with the I/O interrupt and the processor cache content change. In contrast, embodiments herein allows multiple synchronous I/O commands to be initiated, thus allowing multiple synchronous I/O operations to begin, while also allowing additional work to be performed before resuming the command to determine when the I/O operation completes. Further, synchronous I/O commands allow an operating system to issue multiple synchronous I/O commands to multiple targets or transfer multiple records to the same or different targets, to achieve parallelism, and thus improved performance over multiple operations.

In another example, traditional enterprise storage attachments, such as Fiber Connection (FICON) and Fibre Channel Protocol (FCP), have multiple protocol layers that require several hardware, firmware and software levels of processing which cause overhead and add latency. In contrast, the synchronous I/O of embodiments herein eliminates many of these layers, thus improving system efficiency while providing the enterprise qualities of service that includes end-to-end data integrity checking, in-band instrumentation and measurements, work load management and continuous availability with predictable and repeatable high performance.

Embodiments described herein provide SAN attached external persistent storage for synchronous access. In addition, embodiments provide the dynamic switching between synchronous I/O and asynchronous I/O access. Shareable external SAN storage typically will have a mix of short and long running I/O operations which can utilized and benefit from this ability to dynamically switch between the synchronous and asynchronous selection. Embodiments also provide a means for notifying software when the data is not available for synchronous access and the dynamic switching to asynchronous access.

Embodiments described herein provide a low-latency protocol for server to SAN storage communication that allows synchronous I/O access with its inherent advantages of avoiding context switches, interruptions and processor cache pollution, while also providing mechanisms for avoiding processor blocking when access times become too great. Mechanisms are described for dynamic notification and selection of synchronous or asynchronous I/O access.

Thus, embodiments described herein are necessarily rooted in processing system to perform proactive operations for efficiently replicating data across multiple storage subsystems in order to provide continuous availability to overcome problems specifically arising in the realm of traditional I/O and storage subsystem failures.

The technical solutions facilitate controlling access to shared resources in both the server and the storage control unit. The shared resources may include physical links, mailboxes in the control unit, address translation, and data protection resources in the server. Further, in order to minimize firmware access times of control structures, the device table entries used for address translation and protection in typical I/O infrastructures may be extended to also serve as data protection (CRC) context and also control unit mailbox access controls. Using the technical solutions described herein, the firmware dynamically allocates parts of the shared resources per I/O operation. The firmware thus facilitates concurrently executing synchronous I/O commands from multiple operating systems, by allocating each command respective parts of the DTE, address translation and protection, CRC computation context based on mailbox access. The allocated portions of the shared resources are dedicated to a single OS instance for the duration of the corresponding I/O command. After completion of the I/O command the resources are freed such that they can be made available for a new I/O operation for any OS with access to the synchronous I/O link. Thus, the technical solutions described herein facilitate dynamically configuring DTEs and IOAT entries for isolation and protection of an individual synchronous I/O operation by managing shared resources in the server, link, and the persistent SCU.