In one embodiment of the invention, an integrated circuit, such as an FPGA, has one or more programmable termination schemes, each having a plurality of resistive termination legs connected in parallel, and a calibration circuit designed to control each termination scheme for process, voltage, and temperature (PVT) variations. The sense element in the calibration circuit and each resistive leg in each termination scheme has a transistor-based transmission gate connected in series with a non-silicided poly (NSP) resistor. The negative temperature coefficient of resistivity of each NSP resistor offsets the positive temperature coefficient of resistivity of the corresponding transmission gate to provide a temperature-independent sense element and temperature-independent termination legs. The temperature-independence and constant IV characteristic of the sense element and termination legs enable a single calibration circuit to simultaneously control multiple termination schemes operating at different termination voltage levels.

TECHNICAL FIELD

The present invention relates to electronics, and, in particular, to input/output (I/O) interfaces for integrated devices.

BACKGROUND

Signal integrity has become a critical issue in the design of high-speed chip-to-chip communications systems. Using the proper termination scheme can be critical to maintaining good signal integrity. Improper terminations can lead to poor quality due to reflections or signal attenuation. On-chip termination can eliminate the need for external termination resistors on the board, thereby avoiding signal reflections caused by stubs between an on-chip buffer and an off-chip termination resistor.

Unfortunately, in high-speed operations, signals can be distorted as a result of non-linearities in the IV (current-voltage) curve of the on-chip termination resistance. In differential I/O signaling, non-linearity can contribute to different edge rates between the pair of signals, which can adversely impact timing and reduce the data valid window. In addition, conventional on-chip termination schemes are susceptible to process, voltage, and temperature (PVT) variations. As a result, the termination resistance levels will typically vary over different PVT conditions.

As a particular technology matures, process variations usually decrease sufficiently to enable acceptable implementation of on-chip termination. However, the resistance of on-chip termination resistors can vary by 10% to 60% across a temperature range of operation of −40 C. to +125 C., especially in termination schemes that use transistors as the resistive elements. In addition to their wide variations in resistance with respect to temperature, transistors also have inherent non-linearities in their IV curves. Both of these characteristics make it very difficult to control the accuracy and constancy of on-chip impedances implemented using transistors. To compensate for such wide variations in resistance as a function of temperature, elaborate PVT calibration circuits are typically employed to control the configuration of programmable, on-chip termination schemes used for I/O buffers. These calibration circuits increase the complexity of the I/O buffers and require additional layout area.

Moreover, in certain applications, such as in field-programmable gate arrays (FPGAs), I/O buffer modes that operate at different power supply voltage levels are frequently deployed on a single chip. Because of the non-linearity of the IV curve of the on-chip impedance, a separate PVT calibration circuit may need to be implemented for each different voltage level and/or each different I/O bank, since the calibration circuit for one voltage level will typically not properly calibrate the on-chip impedance used for a different voltage level. Implementing multiple calibration circuits, each of which may require one or more pads and may need to be placed close to its associated I/O bank, increases die size and reduces the number of pads that can be used as I/O signal pads.

SUMMARY

In one embodiment, the present invention is an integrated circuit having a termination scheme having at least one leg comprising a first resistive element having a positive temperature coefficient of resistivity connected to a second resistive element having a negative temperature coefficient of resistivity.

In another embodiment, the present invention is an integrated circuit comprising a programmable termination scheme and a calibration circuit adapted to generate at least one control signal for configuring the termination scheme. The calibration circuit comprises a sense element comprising a first resistive sense component having a positive temperature coefficient of resistivity connected to a second resistive sense component having a negative temperature coefficient of resistivity, wherein the sense element is used to generate the at least one control signal.

In yet another embodiment, the present invention is a method for controlling a termination scheme in an integrated circuit. A sense voltage is generated using an on-chip sense element comprising a first resistive sense component having a positive temperature coefficient of resistivity connected to a second resistive sense component having a negative temperature coefficient of resistivity. The sense voltage and a reference voltage are applied to a comparator to generate a control signal. The control signal is applied to control whether a leg of the termination scheme is on or off, wherein the leg comprises a first resistive element having a positive temperature coefficient of resistivity connected to a second resistive element having a negative temperature coefficient of resistivity.

DETAILED DESCRIPTION

FPGA ArchitectureFIG. 1shows a high-level block diagram of the layout of an exemplary FPGA100of the present invention, having a logic core102surrounded by an input/output (I/O) ring104. Logic core102includes an array of programmable logic blocks (PLBs)106(also known by other names such as configurable logic blocks or logic array blocks) intersected by rows of block memory108. Each PLB contains circuitry that can be programmed to perform a variety of different functions. The memory blocks in each row are available to store data to be input to the PLBs and/or data generated by the PLBs. I/O ring104includes sets of I/O buffers110programmably connected to the logic core by multiplexor/demultiplexor (mux/demux) circuits112. The I/O buffers support external interfacing to FPGA100. Also located within the I/O ring are a number of phase-locked loop (PLL) circuits114that are capable of providing different timing signals for use by the various elements within FPGA100. Those skilled in the art will understand that FPGAs, such as FPGA100, will typically include other elements, such as configuration memory, that are not shown in the high-level block diagram ofFIG. 1. In addition, general routing resources, including clocks, buses, general-purpose routing, high-speed routing, etc. (also not shown inFIG. 1), are provided throughout the FPGA layout to programmably interconnect the various elements within FPGA100.

The layout of an FPGA, such as FPGA100ofFIG. 1, comprises multiple instances of a limited number of different types of blocks of circuitry. For example, an I/O ring may contain a number of instances of the same basic block of circuitry repeated around the periphery of the device. In the example of FPGA100, I/O ring104is made up of multiple instances of the same basic programmable I/O circuit (PIC), where each PIC provides a particular number of the I/O buffers of the I/O ring.

Programmable Termination Scheme

FIG. 2shows a schematic circuit diagram of a programmable termination scheme200, according to one embodiment of the present invention. Instances of programmable termination scheme200may be employed, for example, in one or more I/O buffers of FPGA100ofFIG. 1.

As shown inFIG. 2, termination scheme200comprises n termination legs202connected in parallel between the termination voltage VTT and pad204, where each leg202comprises a transistor-based transmission gate206connected in series with an n-type or p-type non-silicided poly (NSP) resistor208. The transmission gate of the ith leg is controlled by two1-bit digital control signals: Ai and its complement AiN. In general, if Ai is high, then AiN is low and the ith transmission gate is on (i.e., its closed-switch state). Similarly, if Ai is low, then AiN is high and the ith transmission gate is off (i.e., its open-switch state). If its transmission gate is on, then the effective resistance of the ith leg affects the net resistance of termination scheme200. On the other hand, if its transmission gate is off, then the ith leg does not affect the net resistance of termination scheme200.

By selectively turning on different numbers of transmission gates using control signals Ai and AiN, the net resistance of termination scheme200can be varied in a controlled manner. In one possible implementation, the dimensions of each NSP resistor208and of the transistors in each transmission gate206are selected such that the (minimum available) net resistance of termination scheme200with all of the transmission gates turned on matches the resistance value for the worst-case slow PVT condition. Turning off one or more transmission gates provides higher and higher net resistance levels for termination scheme200, as will be appropriate for other (i.e., faster) PVT conditions.

FIG. 3graphically represents the relationship between temperature and resistance for each transistor-based transmission gate206(curve R2), each non-silicided poly resistor208(curve R3), and each leg202of termination scheme200(curve R1) ofFIG. 2. As indicated by curve R2, the resistance of transmission gate206increases with temperature (i.e., the temperature coefficient of resistivity of transmission gate206is positive). However, due to the transport properties of NSP resistors and as indicated by curve R3, the resistance of NSP resistor208decreases with temperature (i.e., the temperature coefficient of resistivity of NSP resistor208is negative). By appropriately selecting the dimensions of the transistors used to implement transmission gate206and the dimensions of NSP resistor208, leg202can be designed such that its resistance is substantially temperature-independent (e.g., less than 1-2% variation) over the temperature range of −40 C. to +125 C. (i.e., the effective temperature coefficient of resistivity of the leg is substantially zero), as indicated by curve R1. Moreover, each leg202will have a substantially linear IV characteristic.

FIG. 4shows a schematic circuit diagram of a PVT calibration circuit400used to generate the 1-bit control signals Ai and AiN used to configure programmable termination scheme200ofFIG. 2. Calibration circuit400adjusts the control signals for variations in process, voltage, and temperature to provide PVT-control to termination scheme200. Moreover, since each leg of termination scheme200has a substantially linear IV characteristic, a single calibration circuit400can be used to simultaneously control two or more different on-chip instances of termination scheme200operating at the same or even different termination voltage levels.

As shown inFIG. 4, voltage amplifier402receives input voltage VB (e.g., from an on-chip resistor tree) and a feedback voltage signal from node404and generates a stable voltage level at the gate of NFET device N1that keeps device N1turned on. In one possible implementation, Rref is an off-chip resistor. In that case, node404corresponds to a pad on the chip, where off-chip resistor Rref is connected between that pad and reference voltage VSS (e.g., ground). Alternatively, resistor Rref could be implemented on-chip.

Turning device N1on pulls the voltages at the gates of PFET devices P1and P2low, thereby turning on devices P1and P2, where the current through device P1is mirrored through device P2. The on-chip sense element (Rsense) for calibration circuit400corresponds to the series combination of transmission gate406and resistor408, which are preferably implemented using the identical types of devices as those used to implement each transistor-based transmission gate206and each NSP resistor208, respectively, in termination scheme200ofFIG. 2. In this way, sense element Rsense should have substantially identical PVT characteristics as those of each leg in termination scheme200.

With transmission gate406turned on, a sense voltage Vs at node410is generated and applied to one input of each of n comparators412. In addition, each comparator412receives a different reference voltage Vi (e.g., from an on-chip resistor tree), with levels ranging from just above VSS to just below VCCAUX, e.g., in uniform intervals. If sense voltage Vs is greater than reference voltage Vi, then the output Ai of the corresponding ith comparator will be high; otherwise, Ai will be low.

Like each leg in termination scheme200, sense element Rsense in calibration circuit400is substantially temperature-independent. As such, sense voltage Vs is also substantially temperature-independent. As a result, if a temperature-insensitive circuit is used to generate the reference voltages, then control signals Ai will also be substantially temperature-independent. By properly adjusting the reference voltages Vi based on the variation of sense voltage Vs with respect to process variations, calibration circuit400can configure programmable termination scheme200ofFIG. 2to less than 10% variation with respect to typical ranges of PVT conditions.

The present invention has been described in the context of a programmable on-chip termination scheme having a resistor array consisting of a plurality of termination legs connected in parallel, where each leg consists of a transistor-based transmission gate connected in series with a non-silicided poly resistor, where the transmission gate has a positive temperature coefficient of resistivity, the poly resistor decreases has a negative temperature coefficient of resistivity, and the sizes of the devices are selected to provide the leg with a temperature coefficient of resistivity of substantially zero. In general, embodiments of termination schemes of the present invention can be implemented having other characteristics, such as one or more of the following:Any number of resistor legs, including as few as one (e.g., for a non-programmable termination scheme);Resistive elements having a positive temperature coefficient of resistivity, other than transistor-based transmission gates, such as other transistor-based devices or even non-transistor-based devices;Resistive elements having a negative temperature coefficient of resistivity, other than non-silicided poly resistors;Each resistor leg comprising one or more resistive elements having a positive temperature coefficient of resistivity and one or more resistive elements having a negative temperature coefficient of resistivity, where the resistive elements are not necessarily all connected in series; andThe resistive elements in each resistor leg are selected to achieve an effective temperature coefficient of resistivity other than zero, including different resistor legs possibly having different effective temperature coefficients of resistivity.

Although the present invention has been described in the context of FPGAs, those skilled in the art will understand that the present invention can be implemented in the context of other types of devices, such as, without limitation, application-specific integrated circuits (ASICs), programmable logic devices (PLDs), mask-programmable gate arrays (MPGAs), simple programmable logic device (SPLDs), and complex programmable logic devices (CPLDs). More generally, the present invention can be implemented in the context of any kind of electronic device having programmable elements.