Method and apparatus for copying data using cache

A cache and a method for performing data copying are provided. The cache includes a copy logic and be connected to a processor through a first bus and to a memory controller through a second bus, which is different from the first bus. Moreover, the copy logic may perform data copying through the second bus based on a data copy command received from the processor.

CROSS-REFERENCE TO RELATED APPLICATION(S)

This application claims the benefit under 35 U.S.C. § 119(a) of a Korean patent application filed on Sep. 26, 2013 in the Korean Intellectual Property Office and assigned Serial No. 10-2013-0114658, the entire disclosure of which is hereby incorporated by reference.

TECHNICAL FIELD

The present disclosure relates to a method and apparatus for copying data on a memory using cache.

BACKGROUND

In a general computing device, the term “copying” means that a processor such as a Central Processing Unit (CPU) reads data from certain memory blocks and writes the data to other memory blocks. General memory copying (or data copying) techniques generally include Programmed Input Output (PIO) and Direct Memory Access (DMA) techniques.

FIG. 1Ais a conceptual view of copying data by using the PIO technique according to the related art.

Referring toFIG. 1A, in the case of the PIO technique, a CPU100directly repeats load/store data commands until the operation of copying data to be copied is completed. For example, in order to copy data corresponding to memory addresses 0x0 to 0x100 into memory addresses 0x300 to 0x400 of a memory200, the CPU100is generally required to continue to transmit copy commands.

FIG. 1Bis a conceptual view of copying data by using the DMA technique according to the related art.

Referring toFIG. 1B, in contrast to the PIO technique, the DMA technique further uses a DMA Controller (DMAC)110. When data needs to be copied from the memory addresses 0x0 to 0x100 into the memory addresses 0x300 to 0x400 as mentioned in the example above, in the case of the DMA technique, the CPU100transmits to the DMAC110a command copying source data on memory address 0x0 to 0x100 into destinations, memory addresses 0x300 to 0x400. The DMAC110performs data copying on a memory200. If copying is completed, the DMAC110generates an interrupt and notifies the CPU100that copying is completed.

FIG. 1Cis a conceptual view of a data flow in copying data according to the PIO or DMA technique according to the related art.

Referring toFIG. 1C, the CPU100or the DMAC110provides a copy data command to a memory controller180. The command is transmitted through a system bus102. The memory controller180reads data to be copied from the memory200. The read data is transmitted back to the CPU100(e.g., by using the PIO technique) or the DMA controller110(e.g., by using the DMA technique) through the system bus102and then is written to a target memory block of the memory by the memory controller180.

SUMMARY

Aspects of the present disclosure are to address at least the above-mentioned problems and/or disadvantages and to provide at least the advantages described below.

In the case of the Programmed Input Output (PIO) technique generally, all data/commands pass through the Central Processing Unit (CPU), so heavy load occurs on the CPU and a system becomes slow. Moreover, in the case of the Direct Memory Access (DMA) technique, the CPU has no load because the CPU100only needs to command data copying and check last interrupt, but the CPU unnecessarily occupies the bandwidth of the system bus in the similar way as the PIO technique. For example, both the PIO technique and the DMA technique occupy the bandwidth of the system bus when copying data and may thus decrease system performance.

In order to improve some of the above-identified drawbacks of the related art, an aspect of the present disclosure is provided to decrease bus traffic occurring when copying data by using cache and enhance system performance.

Another aspect of the present disclosure is provided to enhance the operation performance of a memory controller through buffering data to be copied by using a buffer in a cache.

Another aspect of the present disclosure is not limited thereto but includes matters that are mentioned through the detailed description or the claims or may be grasped obviously therefrom.

In accordance with an aspect of the present disclosure, a cache for performing data copying is provided. The cache includes a copy logic, and the cache is connected to a processor through a first bus and to a memory controller through a second bus, which is different from the first bus. The copy logic performs data copying through the second bus based on a data copy command received from the processor.

In accordance with another aspect of the present disclosure, the cache may be a stand-alone device in relation to the processor and the memory controller.

In accordance with another aspect of the present disclosure, the first bus may be a system bus, and the second bus may be a local bus.

In accordance with another aspect of the present disclosure, the data copy command may include a control signal, information on source data to be copied, and information on a destination to which the source data is copied.

In accordance with another aspect of the present disclosure, the information on source data to be copied may include start and last addresses of the source data on a memory, or a start address of the source data on the memory and a length of the source data.

In accordance with another aspect of the present disclosure, if the performing of the data copying is completed, the cache may notify the processor of completion of the data copying through the first bus.

In accordance with another aspect of the present disclosure, the cache may further include a buffer. The copy logic may allow the memory controller to read data from the memory and to store the data to the buffer, and write data stored in the buffer to a predetermined memory block on the memory.

In accordance with another aspect of the present disclosure, a method of performing data copying is provided. The method includes receiving, at a cache, a data copy command from a processor through a first bus, and performing, at the cache, data copying based on the received copy data command through a second bus, which is different from the first bus.

In accordance with another aspect of the present disclosure, the cache may be a stand-alone device in relation to a device connected to the cache by the first bus or the second bus.

In accordance with another aspect of the present disclosure, the first bus may be a system bus, and the second bus may be a local bus.

In accordance with another aspect of the present disclosure, the first bus may be a first local bus, and the second bus may be a second local bus.

In accordance with another aspect of the present disclosure, the data copy command may include a control signal, information on source data to be copied, and information on a destination to which the source data is copied.

In accordance with another aspect of the present disclosure, the cache may be connected to the memory controller through the second bus, and the performing, at the cache, of the data copying may include, at a cache side, allowing the memory controller to write data corresponding to the information on source data to a memory block corresponding to the information on a destination

In accordance with another aspect of the present disclosure, the information on source data to be copied may include start and last addresses of the source data on a memory, or a start address of the source data on the memory and a length of the source data.

In accordance with another aspect of the present disclosure, the cache may further include a buffer, and the performing, at the cache, of the data copying may include, at a cache side, allowing the memory controller to read data from a memory and to buffer the data to the buffer and, allowing the memory controller to write buffered data to a destination on the memory.

In accordance with another aspect of the present disclosure, a computing device for performing data copying is provided. The computing device includes a processor, a cache connected to the processor by a system bus, a memory controller connected to the cache by a local bus, and a memory connected to the memory controller, wherein the cache performs data copying on the memory by using the local bus based on a data copy command received from the processor.

DETAILED DESCRIPTION

Moreover, in the drawings, some components may be exaggerated, omitted, or schematically illustrated. Moreover, the size of each component does not entirely reflect an actual size and thus the present disclosure is not limited to the relative size or interval of components drawn on each drawing.

A bus disclosed herein corresponds to a path through which information flows between devices configuring a system. The information may include data, addresses indicating at which data is stored, and control signals that are used for a read/write operation on data, a read/write operation on input and output devices, or a request/approve operation on a bus.

A computing device may include various types of a bus. For example, various names are used in relation to the location of the bus or a device to which the bus is connected, include a system bus, a local bus, an Input/Output (I/O) bus, an external (or expansion) bus, a Central Processing Unit (CPU) bus, a memory bus, and the like. The system bus disclosed herein corresponds to a bus that allows a processor to access a memory, another processor, input and output devices, and/or the like. In contrast, the local bus corresponds to a bus that allows a device connected to a system bus to be connected to another device not connected to the system bus or that allows the internal connection between other devices that are not connected to the system bus. For example, it may be understood that a CPU for accessing a memory is connected to a memory controller through the system bus but the memory controller is connected to the memory through the local bus. When the CPU includes a certain cache, a cache controller, and/or a memory controller and accesses a memory and other input/output devices by using the certain cache, the cache controller, and/or the memory controller, a bus used by the CPU for internally communicating with the cache, the cache controller, and/or the memory controller becomes the local bus. However, a bus used by the CPU for accessing the memory and other input/output devices corresponds to the system bus. Such definitions are consistently used herein, and different configurations from the examples above in relation to the characteristics disclosed herein will be described in detail with respect toFIGS. 4 and 5.

The processor disclosed herein corresponds to a device that is connected to the system bus and that may perform operations for delivering specific commands or processing data. For example, a CPU100, a Direct Memory Access (DMA)110, an I/O controller120, a Graphics Processor Unit (GPU), a Digital Signal Processor (DSP), a Micro Processor Unit (MPU), a hardware accelerator, and a general Memory Access Unit (MAU) may correspond to the processor.

FIG. 2is a conceptual view of a data flow in copying data using a cache according to an embodiment of the present disclosure.

Referring toFIG. 2, a copy data command is delivered from the CPU100or the DMA controller110to a system cache150via a system bus102. The CPU100and the DMA controller110as shown inFIG. 2are processors and the present disclosure is not limited thereto.

The cache150receiving the copy data command provides the copy data command to a memory controller180. More particularly, the cache150allows the memory controller180to read data to be copied from the memory200, and then if the data is read, the cache150allows the memory controller180to write corresponding data to write a target region of the memory200.

The memory as shown inFIG. 2generally corresponds to a Random Access Memory (RAM). However, various embodiments of the present disclosure are not limited thereto. The process shown inFIG. 2may also be applied to other types of memory, for example, a flash memory, a hard disk, an optical disk, and/or the like.

According to various embodiments of the present disclosure, similar to the data flow illustrated inFIG. 2, a data flow through the system bus102may be distinguished from a data flow through the local bus by using the cache150. However, according to various embodiments of the present disclosure, an MAU may be connected to the memory controller180without being directly connected to the system bus102. By locating the cache150between the memory controller180and the MAU, distinguishing a data flow through a first local bus (e.g., connecting MAU-cache) from a data flow through a second local bus (e.g., connecting cache-memory controller) may be possible.

FIG. 3is a conceptual view of an example of a cache according to an embodiment of the present disclosure.

Referring toFIG. 3, the cache150includes logic152and a buffer154. The logic152may be copy logic for performing a copy memory command. However, including logic for general control signals, such as logic for transmitting an interrupt that copying is completed, and/or the like may be possible.

According to various embodiments of the present disclosure, the buffer154is a member for temporarily storing data read by the memory controller180. When the cache150is independent of the memory controller180or the processor180, a constraint on the size of the buffer154relatively decreases. In general, the memory controller180performs an Out-of-Order Execution (OOE) on a command to enhance performance, and to this end, there is a need for a space to store access memory commands for the memory controller180. In this case, if data is stored in the buffer154located outside the memory controller180, regions at which the memory controller180performs the OOE relatively increase and thus enhancing the performance of the memory controller180is possible.

Thereafter, the cache150receives the copy data command from the processor. The copy data command may include information on source data to be copied, information on a destination to which the source data is copied, and a control signal for providing a copy command. Information on source data may include a start address that represents a memory block from which the source data starts on the memory200. In addition, source data may include an end (last) address that represents the last memory block of the source data, or the length of the source data. The destination information may include the length and/or address of a memory block to which the source data is scheduled to be copied.

Specifically, through a register setup, the start and last addresses of a memory for data to be copied to the logic152of the cache150, or the start address of a memory and a length to be copied are set up. Such a command is delivered to through the system bus102. Thereafter, the logic152instructs the memory controller180to read data from the memory200based on the copy data command. The data read by the memory controller180is temporarily stored in the buffer154. If data corresponding to the capacity of the buffer154is accumulated, the copy logic152allows the memory controller182to write the buffered data to a destination. Such processes are repeated to the last address of data to be copied, or by the defined length of data. If the last data is transmitted, the cache150ends data copying.

FIG. 4is a conceptual view of a data copying system using a cache according to an embodiment of the present disclosure.

Referring toFIG. 4, the system may include a CPU100, a DMA controller110, an I/O controller120, and other peripheral devices130. Devices that may approach a memory200through a system bus102are collectively referred to as processors. Such processors are connected to a cache150through the system bus102. The cache150is connected to the memory controller180through a local bus202. The memory controller180is also connected to the memory200through another local bus204.

Referring toFIG. 4, the cache150is a stand-alone device with respect to the processor and the memory controller180. Because the cache150is a stand-alone device that is located outside the memory controller180, the performance of the memory controller180is enhanced as described above. Moreover, because the cache150exists independently and may be connected to a typical system bus102and local buses202and204, enhancing compatibility with a typical system without increasing the complexity of a typical processor or memory controller180is possible.

Both the system bus102and the local buses202and204generally include an address bus, a data bus, and a control bus. The address bus is a unidirectional bus that is used when the processor designates the address of an external memory or input and output devices. The data bus is a bidirectional bus that is used as a data transmission path when outputting data to the memory or an output device or when inputting data from the memory or an input device. The control bus is a unidirectional bus through which an output signal, which notifies the type or state of a task being currently performed by the processor of the memory or the input and output devices, and an input signal for requesting an external processor to take a certain action flow.

Referring back toFIG. 4, the processor transmits the copy data command to the cache150through the system bus102. A control signal included in the copy data command is delivered through the control bus, and the address of source data to be copied is delivered through the address bus. Based on such information, the cache150controls the memory controller180and performs data copying on the memory200. Because the cache150performs the copy data command, the data copied from when the copy data command is received from the processor to when data copying is completed flows through the local buses202and204. If copying is completed, the cache150sends to the processor a copying completion signal through the system bus102(e.g., control bus).

Because typical data copying using the PIO and DMA techniques is performed without the stand-alone cache150, copied data flows via the system bus102. Because the flow of copied data through the system bus102occupies the bandwidth of the system bus and thus increases traffic, typical data copying using the PIO and DMA techniques results in a decrease in system performance. However, according to various embodiments of the present disclosure, decreasing the bandwidth occupancy of the system bus and thus promoting enhancement in system performance is possible by using the cache150that is located between the system bus and the local bus.

FIG. 5is a conceptual view of a data bus in a data copying system using a cache according to an embodiment of the present disclosure.

Referring toFIG. 5, details for which a description is already provided with respect toFIG. 4are skipped. A region over the broken line around the cache150corresponds to a region sharing the system bus102, and a region under the broken line corresponds to a region connected by the local buses202and204.

If the cache150receives the copy data command from the processor, the cache150allows the memory controller180to read source data through the local bus202. The memory controller180references address information on the source data included in the copy data command and reads data from a corresponding memory block of the memory200. The data may be stored in the buffer154of the cache150through the data bus of the local buses202and204. If data is buffered at maximum capacity in the buffer154, the cache150or the copy logic152of the cache150may allow the memory controller180to write the buffered data to a memory block on the memory200to which copying is performed. The location (address) of the memory block may be included as destination information in the copy data command. If copying is completed, the cache150may send a copying completion notification through the system bus102.

FIG. 6is a flowchart of a process in which a processor performs data copying using a cache according to an embodiment of the present disclosure.

Referring toFIG. 6, at operation610, the process in which a processor performs data copying using a cache starts.

At operation620, the processor transmits the start address of data to be copied to the cache150through the system bus102.

At operation630, the processor transmits to the cache150the last address of data to be copied or the length of the data to be copied. The start and last addresses of data correspond to the start and last locations of a memory block in which data is stored on the memory200. The length of data corresponds to the length of a memory block in which data to be copied is stored.

At operation640, a control signal for starting data copying is transmitted to the cache150.

At operation645, the processor determines whether copying is completed. For example, the processor determines whether a notification indicating that copying is completion is received from the cache150.

If the processor determines that copying is not completed (e.g., that the notification indicating that copying is completion is not received from the cache150) at operation645, then the processor may continue to poll for an indication that the copying is completed. Moreover, if the processor determines that copying is not completed at operation645, then the processor may continue to perform copying using the cache150.

If the processor determines that copying is completed (e.g., that the notification indicating that copying is completion is received from the cache150) at operation645, then the processor may proceed to operation650at which the processor may transmit to the cache150a control signal instructing to terminate copying in operation650. However, according to various embodiments of the present disclosure, operation650is not essential, so the transmission of the control signal may be skipped depending on the type of the processor or a memory copying task.

At operation660, the process terminates if copying and signal transmissions are all completed, the process terminates.

FIG. 7is a flowchart of a process in which a cache performs data copying according to a copy data command according to an embodiment of the present disclosure.

Referring toFIG. 7, at operation710, the process in which a cache performs data copying according to a copy data command starts.

At operation720, the cache150receives the copy data command from the processor through the system bus102. According to various embodiments of the present disclosure, operation720may be divided into an operation of transmitting/receiving the start address of source data to be copied, an operation of transmitting/receiving the last address thereof, and an operation of transmitting/receiving a control signal for starting copying, as described above with reference toFIG. 6. Moreover, the copy data command may include information a destination to which source data is copied.

At operation730, the cache150performs data copying through the local bus. In particular, the cache150may allow the memory controller180to read data from a memory block corresponding to source data information included in the copy data command and write the read data to a memory block corresponding to destination information.

At operation735, the cache150determines whether data copying is completed.

If the cache150determines that copying is not completed at operation735, then the cache150continues to copy data.

In contrast, if the cache150determines that copying is completed at operation735, then the cache150proceeds to operation740at which the cache150notifies the processor of data copying completion through the system bus102. According to various embodiments of the present disclosure, the notification of data copying completion may be a control signal such as interrupt.

At operation750, if the cache150receives a final data copying termination signal from the processor, then the cache150terminates data copying.

As described above, if there is, for example, no continuous copying task using a queue, the cache150may transmit the copying completion notification to the processor and immediately terminate the process at operation760.

FIG. 8is a flowchart of a process in which a cache performs data copying using a buffer according to an embodiment of the present disclosure.

Referring toFIG. 8, at operation810, the process in which a cache performs data copying using a buffer starts.

At operation820, the cache150receives a copy data command.

At operation830, the cache150performs data copying. According to various embodiments of the present disclosure, the data copying may further involve the following operations.

At operation840, the cache150allows the memory controller180to read data and buffer the data in the buffer154of the cache150. This task may be performed until data is buffered at maximum capacity in the buffer154. For example, at operation845, the cache150may determine whether the buffer154is full. If the cache150determines that the buffer154is not full at operation845, then the cache150may return to operation840at which the cache150allows the memory controller180to read data and buffer the data in the buffer154of the cache150. In contrast, if the cache150determines that the buffer154is full at operation845, then the cache150may proceed to operation850.

At operation850, the cache150allows the memory controller180to write the buffered data to the memory200if the buffer154has data.

At operation855, the cache150determines whether copying is completed.

If the cache150determines that copying is not completed at operation855, then the cache150proceeds to operation830at which operations830to855are again performed.

In contrast, if the cache150determines that copying is completed at operation855, then the cache150proceeds to operation860at which data copying is terminated. As described above, the cache150may send interrupt to the processor if data copying is completed.

At operation870, process in which a cache performs data copying using a buffer is terminated.

According to various embodiments of the present disclosure, when performing data copying on the memory, data does not flow to the system bus due to the cache that is located between the processor and the memory controller. Thus, traffic occurring on the system bus when copying data decreases as compared to the typical PIO/DMA techniques. As a result, the cache enhance system perform by securing the bandwidth of the system bus.

Moreover, according to various embodiments of the present disclosure, if the cache located outside the memory controller performs data buffering, the cache increase the flexibility of an OOE for typical memory access commands of the memory controller and thus decreases the load of the memory controller. As a result, cache enhances the operation performance of the memory controller.

Moreover, according to various embodiments of the present disclosure, if the cache is independently located outside the processor, the memory, or the memory controller, the cache may be easily compatible with typical devices. Additionally, it is possible to have a relatively large buffer capacity as compared to when the cache is located in the processor or the memory controller, and the cache contributes to enhancement in the performance of the above-described memory controller.

The component represented as a means for performing a specific function covers any method of performing the specific function and such a component may include a combination of circuit components performing specific functions, or any form of software that is combined with suitable circuits to execute software for performing the specific functions and include firmware, micro-codes, and the like.

For example, it will be appreciated that various embodiments of the present disclosure according to the claims and description in the specification can be realized in the form of hardware, software or a combination of hardware and software.

Any such software may be stored in a non-transitory computer readable storage medium. The non-transitory computer readable storage medium stores one or more programs (software modules), the one or more programs comprising instructions, which when executed by one or more processors in an electronic device, cause the electronic device to perform a method of the present disclosure.

In the specification, ‘an embodiment’ of the principles of the present disclosure and the various modified names of such an expression mean that specific characteristics, structures, and properties related to the embodiment are included in at least one embodiment of the principle of the present disclosure. Thus, the expression ‘an ‘embodiment’ and any other modified examples disclosed throughout the specification do not necessarily indicate the same embodiment.