Body-tied, strained-channel multi-gate device and methods of manufacturing same

A fin-FET or other multi-gate transistor is disclosed. The transistor comprises a semiconductor substrate having a first lattice constant, and a semiconductor fin extending from the semiconductor substrate. The fin has a second lattice constant, different from the first lattice constant, and a top surface and two opposed side surfaces. The transistor also includes a gate dielectric covering at least a portion of said top surface and said two opposed side surfaces, and a gate electrode covering at least a portion of said gate dielectric. The resulting channel has a strain induced therein by the lattice mismatch between the fin and the substrate. This strain can be tuned by selection of the respective materials.

TECHNICAL FIELD

The present invention relates generally to multi-gate transistor structures and more specifically to a multi-gate transistor having a strained channel region.

BACKGROUND

Multi-gate structures are known in the art and are increasingly employed because of the advantageous features of scalability, drive current improvement, and switching speed, among others. Double gate transistors, triple gate transistors, omega transistors, and fin-FET transistors are among the multi-gate structures that have been proposed and that are finding increased acceptance.

Typically, multi-gate structures are formed on a so-called silicon on insulator (SOI) substrate. This is because multi-gate transistors are generally formed on mesa or island structures. These mesas or islands are preferably highly electrically isolated to prevent noise and cross talk, and the SOI substrate readily lends itself to this process.

Recently, a so-called body-tied multi-gate structure has been proposed by Park et al.,Fabrication of Body-Tied FinFETs(Omega MOSFETs)Using Bulk Si Wafers,2003 Symposium on VLSI Technology Digest of Technical Papers, which article is incorporated herein by reference. Park et al. describe a multi-gate structure that is formed on a bulk silicon wafer. Advantageously, bulk wafer processing provides cost savings over the more expensive SOI wafers. Additionally, tying the transistor body to the bulk substrate also provides improved thermal dissipation and improved grounding and, hence, improved noise reduction.

While the prior art devices show improvement over planar transistors, further improvement in device performance is still needed. One such improvement is described herein.

SUMMARY OF THE INVENTION

In one aspect, the present invention provides for a fin-FET transistor. The transistor comprises a semiconductor substrate having a first lattice constant, and a semiconductor fin extending from the semiconductor substrate. The fin has a second lattice constant, different from the first lattice constant, and a top surface and two opposed side surfaces. The transistor also includes a gate dielectric covering at least a portion of said top surface and said two opposed side surfaces, and a gate electrode covering at least a portion of said gate dielectric.

In another aspect, the present invention provides for an integrated circuit. The integrated circuit includes a semiconductor substrate having a top surface with a first lattice constant, and an insulating film on said top surface of said semiconductor substrate. A plurality of islands extends from said top surface of the semiconductor substrate. The islands have a second lattice constant that is different from the first lattice constant, the islands further extend above a top surface of the insulating film. The integrated circuit also includes at least multi-gate FET device. The multi-gate device includes a gate dielectric overlying a portion of at least one of the plurality of islands, and gate electrode overlying the gate dielectric.

In yet another aspect, the present invention provides for a method of manufacturing a transistor. The method provides a substrate having a top surface, the top surface having a first lattice constant, and forming an insulating layer over the top surface. The method further provides forming an opening in the insulating layer to expose a portion of the top surface, and epitaxially growing an extension on the top surface in the opening. The extension has a second lattice constant that is different from the first lattice constant. The method further provides forming a doped region in the extension, forming a gate dielectric over at least a portion of extension, and forming a gate electrode over the gate dielectric.

An advantageous feature of the invention is the ability to tune the strain in the channel of the multi-gate transistor, by stress arising from the interface between the underlying substrate and islands extending therefrom.

Corresponding numerals and symbols in the different figures generally refer to corresponding parts unless otherwise indicated. The figures are drawn to clearly illustrate the relevant aspects of the preferred embodiments and are not necessarily drawn to scale. In fact, certain features of the illustrations are exaggerated in relative size in order to more clearly illustrate those and other features. To more clearly illustrate certain embodiments, a letter indicating variations of the same structure, material, or process step may follow a reference number.

DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS

FIG. 1aillustrates an intermediate structure in the manufacture of a first illustrative embodiment body-tied, strained-fin device. While the illustrative embodiments illustrate fin-FET devices, one skilled in the art will recognize that the present invention is applicable to other multi-gate transistors as well. At the step in the process illustrated inFIG. 1a, a substrate2is provided upon which an oxide layer4and a nitride layer6over oxide layer4have been formed. In the illustrative embodiment, substrate2is a conventional p-type bulk silicon wafer.

Oxide layer4is preferably formed by chemical vapor deposition (CVD), thermal oxidation, or other conventional oxide deposition techniques. Oxide layer4is preferably at least 50 Å thick and more preferably between about 100 Å and about 300 Å in thickness.

Nitride layer6may be formed by conventional deposition techniques, such as CVD, plasma enhanced chemical vapor deposition (PECVD), and the like. In the illustrative embodiment, it is desirable that the combined thickness of oxide4and nitride6ranges between about 500 Å and about 1,000 Å, depending upon the desired height of the subsequently formed fin, as will be discussed below. In the illustrative embodiments in which oxide4ranges from about 100 to 300 Å, nitride6will range from about 200 to 400 Å (for a 500 Å fin) and from about 700 to 900 Å (for a 1,000 Å fin).

As shown inFIG. 1a, nitride6and oxide4have been patterned, using a photoresist layer (not shown) and conventional photolithography processes. Nitride6is anisotropically etched, using e.g., conventional dry etching techniques, followed by an anisotropic etch of oxide6, using e.g., plasma etch. The patterning and etching of oxide4and nitride6form a trench8and expose the top surface of underlying substrate2. For clarity, only one trench is shown in oxide4and nitride6. One skilled in the art will recognize that a plurality (in fact, millions) of such trenches will be formed in a typical integrated circuit on a typical wafer.

Silicon germanium (SiGe) is next epitaxially grown on the exposed surface of substrate2, filling trench8, as shown inFIG. 1b. This epitaxially grown SiGe will form a fin10of the resulting fin-FET transistor, as will be explained in greater detail below. The various methods and processes for epitaxially growing SiGe fin10will be evident to one skilled in the art and are matters of design choice. For example, a typical SiGe alloy could be formed by a decomposition of approximately 20 sccm of dichlorosilane (SiH2Cl2) approximately 50-150 sccm of one percent hydrogen diluted germane (GeH4) at a temperature of between 550° C.-750° C. and a pressure of approximately 10-200 torrs. Fin10is preferably grown to a height of from about 500 Å to about 1,000 Å. This is the reason why the combined thickness of oxide4and nitride6is preferably about 500 Å to about 1,000 Å. In the figure, fin10is grown to be substantially coplanar with the top surface of nitride6. In other embodiments, fin10may grow slightly above the top surface of nitride6, although care must be taken that epitaxial growth does not spread out laterally over the top surface of nitride6. In yet other embodiments, epitaxial growth of fin10ceases prior to fin10reaching the top of trench8. These are design choices that can be established with routine experimentation.

A crystal lattice mismatch occurs at the interface between SiGe fin10and substrate2. This lattice mismatch causes stress and applies a strain on fin10. The lattice mismatch also causes strain in substrate2, but that strain is not significant for the purposes of the illustrative embodiments of the present invention. As is known in the art, stress improves charge carrier mobility in a crystalline semiconductor device. More particularly, the lattice mismatch between substrate2and SiGe fin10results in bi-axial compressive strain in SiGe fin10. Compressive strain improves hole mobility in p-type devices. This ability to engineer strain in the thin fin provides a significant advantageous feature over the prior art.

Continuing toFIG. 1c, nitride layer6is removed, such as by a wet or dry etch. The particular etch chemistry and process is a matter of design choice. The main constraint on the etch process is that it has high selectivity to silicon nitride, relative to underlying silicon oxide layer4. It is desirable that silicon oxide layer4not be significantly attacked during the removal of silicon nitride layer6. The removal of nitride layer6could be done, for instance, by using the phosphate (H3PO4) at a temperature of approximately 80-120° C. (a “wet etch” process). Removing nitride layer6exposes the top surface and portions of the sidewalls of fin10. At this stage, appropriate impurities can be implanted into fin10. For instance, fin10can be doped with either p-type or n-type impurities to establish a desired nominal impurity concentration. Alternatively, fin10can be doped in situ by introducing appropriate impurities at the desired concentration during the epitaxial growth process. Source and drain regions can then be implanted, as is known in the art.

As shown inFIG. 1c, a silicon cap layer, or sacrificial layer,12is formed on the exposed surfaces of fin10. This sacrificial layer is preferably epitaxially grown. Because the silicon will epitaxially grow on the exposed SiGe regions, but not on the exposed surface of oxide layer4, the epitaxial growth of polysilicon cap layer12is self-aligned. In the illustrative embodiments, in which a gate oxide of ten to twenty angstroms is desired, sacrificial cap layer12is grown to about five to ten angstroms.

As illustrated inFIG. 1d, cap layer12is converted to silicon oxide layer14by exposing cap layer12to an oxidizing environment, such as a steam environment. Silicon cap layer12combines with oxygen to form silicon oxide layer14(layer14will sometimes be referred to as a gate dielectric layer14), which will serve as the gate dielectric for a subsequently formed fin-FET transistor. An advantageous feature of cap layer12is that it prevents SiGe fin10from oxidizing. Oxidation of SiGe fin10would cause a re-distribution of the germanium atoms within fin10, which is undesirable. It is also undesirable to have Ge impurities in the gate dielectric.

Finally, as shown inFIG. 1e, a gate electrode16is formed over gate dielectric layer14and surrounding oxide layer4. In the illustrative embodiment, gate electrode16comprises polysilicon. Gate electrode16can be deposited and doped in situ or can be deposited undoped and subsequently doped via ion implantation or other known techniques.

In an alternative embodiment, gate dielectric14can be formed of a high dielectric constant (high k) material rather than SiO2. Materials such as HfO2, HfSiO can be employed, as can metal oxides and/or metal silicates of e.g., hafnium, aluminum, zirconium, lanthalum, and the like.

Likewise, in an alternative embodiment, and particularly when a high-k dielectric material is used, gate electrode16could be formed of metal, in lieu of polysilicon. One exemplary metal material is TaC, although other materials, including metals (Ta, Ti, Ru, Mo, etc.), metal alloys, metal nitrides (TaN, TiN, Mo2N, etc.), metal carbides (TaC, etc.), and conducting metal oxides (RuO2, etc.) and the like, could also be employed for the gate electrode.

FIGS. 2athrough2fillustrate another exemplary embodiment. In this embodiment, as shown inFIG. 2a, substrate2comprises three sub-components. The first component is a silicon wafer1a, typically a conventional p-type bulk silicon wafer. Buffer layer3is formed atop silicon wafer1. A relaxed SiGe layer5, having perhaps ten to thirty percent concentration of Ge, is formed atop buffer layer3. Buffer layer3, as the name implies, serves as to buffer, or ameliorate, the effects of lattice mismatch between silicon wafer1and relaxed SiGe layer5. Buffer layer3accomplishes this by having a germanium concentration of essentially nil at the interface with silicon wafer1—meaning essentially no lattice mismatch between layers1and3, and a germanium concentration that essentially matches the germanium concentration of relaxed SiGe layer5—meaning essentially no lattice mismatch between layers3and5. The germanium concentration gradually increases as one proceeds from the bottom of buffer layer3(near the silicon wafer1interface) to the top of buffer layer3(near the relaxed SiGe layer interface). By virtue of this gradient in concentration, the effects of the lattice mismatch are virtually eliminated, or at least substantially reduced. In this way, SiGe layer5is not affected by the lattice mismatch with silicon wafer1.

In the illustrative embodiments, buffer layer3is thick enough so that dislocations7arising at the buffer3/SiGe layer5interface do not propagate completely through the layer. In the illustrative embodiments, buffer layer3has a thickness ranging from about 5,000 Å to about 10,000 Å. Relaxed SiGe layer5preferably has a thickness ranging from about 2,000 Å to about 3 000 Å. The resulting structure, as illustrated inFIG. 2a, provides a “virtual” SiGe substrate upon which devices can be fabricated.

As shown inFIG. 2b, processing continues in a manner similar to that illustrated inFIG. 1a. Oxide layer4and nitride layer6are formed and patterned to form trench8, as has been previously discussed. As a design consideration, thermal budget should be kept in mind when forming oxide4, nitride6, and in subsequent process steps. This is because exceeding a thermal budget may result in degradation of the desirable properties of SiGe layer5including, in some cases, a relaxation of the stress developed between SiGe layer5and Si fin20(discussed below with reference toFIG. 2c). Process temperatures not exceeding range from about 700C to about 800C are preferable for maintaining a satisfactory thermal budget. In this embodiment, the substrate exposed at the bottom of trench8is SiGe layer5. For simplicity of illustration, silicon wafer1is not illustrated inFIG. 2band the remaining figures.

Continuing on toFIG. 2c, fin20is epitaxially grown on the exposed surface of SiGe layer3at the bottom of trench8, filling trench8. In this embodiment, wherein the underlying substrate (layer3) is SiGe, fin20comprises Si. In this way, a lattice mismatch is again created at the interface between silicon fin20and underlying SiGe substrate3. Because SiGe has a larger lattice constant than Si, a biaxial tensile strain is imposed on Si fin20. Tensile strain tends to improve the electron carrier mobility of n-type transistors, so this embodiment is particularly well suited for n-type fin-FETs.

As illustrated inFIG. 2d, processing continues with the removal of nitride layer6, similar to the process discussed above with reference toFIG. 1c. For simplicity of illustration, buffer layer3is not shown inFIG. 2dor the following figures. In this embodiment, there is no need for a sacrificial Si cap layer to be formed on Si fin20. Rather, and as shown inFIG. 2e, gate dielectric14can be formed directly on Si fin20, such as by thermally growing gate dielectric14on the exposed surfaces of fin20. One skilled in the art will recognize that some part of Si fin20will be consumed in the process of growing gate dielectric14. This can be compensated for by nominally designing fin20height and thickness to accommodate the loss due to formation of gate dielectric14.

Finally, and as shown inFIG. 2f, gate electrode16is formed atop gate dielectric14and the surrounding oxide layer4. As explained above with reference toFIG. 1e, gate conductor16may comprise polysilicon, or alternatively may comprise a metal, metal alloy, or conductive metal nitride or metal oxide. Likewise and as also explained above with reference to the embodiment illustrated inFIG. 1e, gate dielectric may alternatively be formed of a high-k dielectric such as HfO2, HfSiO, or other well-known alternatives.

Yet another illustrative embodiment is illustrated inFIGS. 3athrough3f. In this embodiment, as shown inFIG. 3a, substrate2comprises a silicon wafer1, a buffer layer9, and a relaxed SiC layer11. In this case, buffer layer9has a carbon concentration that varies from near nil at the bottom (at the interface with silicon wafer1) to a concentration equivalent to that contained in relaxed SiC layer11(at the interface with that layer).

As shown inFIG. 3b, oxide layer4and nitride layer6are formed over SiC layer11, using processes such as described above. Next, oxide layer4and nitride layer6are patterned, also such as described above, to form trench8. In this embodiment, trench8exposes underlying SiC layer11. As shown inFIG. 3c, trench8is filled with epitaxially grown silicon, much as described above with reference toFIG. 2c, to form fin20. In this embodiment, Si fin20is grown upon underlying SiC layer11. As is known, SiC has a lesser lattice constant than does silicon. This means that a biaxial compressive stress arises at the interface of SiC layer11and Si film20, resulting in a compressive strain in fin20. This compressive strain enhances hole mobility and, hence, is particularly beneficial when forming p-type MOSFETs.

Continuing on toFIG. 3d, nitride layer6is removed, exposing Si fin20and underlying oxide layer4. Next, Si fin20is exposed to an oxidizing environment, wherein a portion of the top surface and exposed sidewalls of Si fin20are converted to silicon oxide. This process forms gate dielectric14, as illustrated inFIG. 3e. Polysilicon gate electrode16is deposited over gate dielectric14, as shown inFIG. 3f. As in the prior described embodiments, gate dielectric14may alternatively be a high-k dielectric and gate electrode16may alternatively comprise a metal, metal alloy, metal nitride, or metal oxide.

Employing the materials and processes described above, it is envisioned that localized strain in the range of up to 500 MPa to 1,000 MPa is achievable. As a potential design constraint, however, it should be recognized that the strain imposed on fin10,20is greatest at the interface with underlying layer2,5, or11. The further from the interface, the lesser the imposed strain. The phenomenon is illustrated schematically inFIG. 7, which illustrates a highly magnified view of a portion ofFIG. 1e. Fin10is shown, and superimposed on fin10are strain lines25. These strain lines schematically illustrate the relative magnitude of strain imposed on fin10. Areas where the strain lines are highly dense (closely spaced) illustrate areas of high strain, whereas areas where the strain lines are less dense (spaced apart) illustrate areas of relatively lower strain. As schematically illustrated, the strain imposed on fin10(and analogously on fin20in the other embodiments), is the highest at the interface with the underlying layer and steadily decreases as the distance from the interface increases. This phenomenon imposes a practical limit on the height h of fin10(and analogously fin20) of no more than perhaps 500 Å to 1,000 Å, using presently available processes and materials. This is a practical limitation on present embodiments, but should not be considered as a limitation on the application or teaching of the present invention—it being envisioned that the current invention will be applicable to future developed materials and processes.

Various other combinations of materials can be employed in forming the substrate and fin. Depending upon the desired strain in the fin, one can employ a substrate/fin combination of Si/SiGe, SiGe/Si, SiC/Si, Si/SiC, or other combinations. The combinations are not limited to the above-described materials. In fact, any Group III, Group IV, or Group V element that can be introduced into the silicon lattice and change the lattice constant could be employed. Design constraints such as cost, ease of manufacturing, potential contamination concerns, and the like, are the only limitations.

In the illustrated embodiments, only a single fin10,20is shown. One skilled in the art will recognize that millions of fins are likely to be formed on a single wafer and, in fact, in a single integrated circuit. As was discussed above, certain fin/substrate combinations produce compressive strain and, hence, are particularly advantageous for improving carrier mobility in p-type devices, whereas other fin/substrate combinations produce tensile strain in the fin and, hence, are particularly advantageous to improve carrier mobility in n-type devices. It may be advantageous, therefore, to employ different fin structures in a single integrated circuit for the different transistor types (n-type, p-type), particularly when employing so-called CMOS technology.

One approach to accommodating CMOS devices is shown inFIGS. 4athrough4e.FIG. 4aillustrates substrate2upon which oxide4and nitride6have been formed. Trenches8aand8bhave been formed, as described above. For simplicity of illustration, only two such trenches are shown. Also not shown, are the various well regions, isolation structures, noise isolation rings, and other features commonly formed in substrate2. Photoresist material30has been formed and patterned, leaving first trench8acovered and second trench8bexposed. Silicon germanium is then epitaxially grown on the exposed surface of Si substrate2at the bottom of trench8b, filling trench8bto form SiGe fin10b, as shown inFIG. 4b. Optionally, fin10bcan be implanted with n-type impurities at this point to form source and drain regions (not shown). No extra mask step is required, as fin10ahas not yet been formed, and trench8ais covered by photoresist30.

Also shown inFIG. 4b, photoresist30is stripped off, re-applied, and re-patterned such that fin10bis covered and trench8ais exposed. Then, silicon carbide is epitaxially grown in trench8aon the exposed surface of underlying substrate2, filling trench8ato form fin10a. Fin10acan then be implanted with appropriate p-type impurities to form source and drain regions. This is preferably done while fin10bis protected by photoresist30, although the relative doping concentrations could alternatively be adjusted such that fin10bis heavily enough doped with n-type impurities so that source/drain regions of fin10bremain n-type, even after p-type counter doping. Photoresist30is then stripped off, followed by removal of nitride layer6and the formation of silicon cap layers14aand14b, as shown inFIG. 4c.

The device is then exposed to an oxidizing environment to convert silicon cap layers12a,12bto gate oxides14a,14b, respectively, as shown inFIG. 4d. Next gate electrodes16aand16bare formed and patterned. In the illustrated embodiment, a substrate had grown thereon both SiC fins and SiGe fins to achieve the desired strained fin. Alternatively, a SiC or SiGe virtual substrate could have grown thereon Si or other material fins for strain engineering. The respective materials chosen are a matter of design choice and routine experimentation.

FIG. 4eschematically illustrates in plan view the structure shown in cross-sectional view inFIG. 4d. A p-type fin-FET is provided by fin10a, which has n-type source/drain regions32implanted at its respective ends. A channel region is defined between source and drain regions32and gate electrode16aoverlies the channel region (along the top surface of fin10bas well as along the sidewalls of fin10b). Likewise, an n-type fin-FET is provided by fin10b, which has p-type source/drain regions34formed at either end and a channel region defined therebetween. Gate electrode16boverlies the channel region (along the top surface of fin10bas well as along the sidewalls of fin10b). For point of reference,FIGS. 1,2,3, and4a-4dillustrate the cross-section indicated at line A-A inFIG. 4e.

Yet another approach to CMOS integration of a strained-fin p-type fin-FET and a strained-fin n-type fin-FET is shown inFIGS. 5athrough5e, which illustrate a so-called split wafer approach.FIG. 5aillustrates a silicon wafer2in which a deep trench36has been formed by anisotropic etching or a combination of isotropic and anisotropic etching. Photoresist material30is employed to define the position and size of the deep trench. Buffer layer3and SiGe layer5are epitaxially and selectively grown on the exposed silicon surfaces of deep trench36. During the epitaxial growth of buffer layer3, germanium is gradually introduced as a precursor so as to gradually increase the germanium concentration of the buffer layer from effectively nil to the nominal concentration in SiGe layer5. Epitaxial growth continues with the nominal SiGe concentration, resulting in SiGe layer5. As will be apparent to one skilled in the art, buffer layer3and SiGe layer5are illustrated as distinct layers. In practice, however, the interface between these layers may be indistinct or entirely indistinguishable.

FIG. 5cillustrates the formation and patterning of oxide layer4over substrate2, and SiGe layer5, and nitride layer6over oxide layer4, to form trenches8. Note that certain trenches expose substrate2and other trenches expose SiGe layer5.

Through appropriate masking and epitaxial growth steps, fins of varying composition can be grown in the respective trenches8. For instance, as shown inFIG. 5d, SiGe fins10may be grown over substrate2, whereas Si fins20may be grown over SiGe layer5. One skilled in the art will recognize that this can be accomplished by masking certain trenches8, while growing SiGe in the exposed trenches, followed by exposing the previously masked trenches8, masking the SiGe fins, and growing Si in the exposed trenches. Also shown inFIG. 5d, by way of illustration, are exemplary SiC fins40. These fins likewise are grown in trenches that are masked when the other fins are formed, and likewise the other fins are masked while SiC is epitaxially grown in the appropriate trenches. Obviously, the placement and arrangement of fins10,20, and40inFIG. 5dis for illustration only. Likewise, the relative size and placement of buffer layer3/SiGe layer5, relative to Si substrate2is for illustration only. In practice, numerous trenches of different sizes and configurations would likely be used. Also, while a SiGe virtual substrate formed in a silicon wafer is illustrated, various other materials for the wafer and the virtual substrate will be apparent to one skilled in the art.

For completeness,FIG. 5eillustrates the integrated circuit ofFIG. 5dwith nitride layer6removed and after the formation of respective gate dielectrics14and gate electrodes16, using the processes discussed above with reference toFIGS. 1 through 4.

In yet another illustrative embodiment, a single integrated circuit employs both body-tied, strained-fin fin-FET devices and planar transistors. As illustrated inFIG. 6, the manufacturing processes for a body-tied, strained-channel multi-channel transistor of the illustrative embodiments is fully compatible with conventional planar transistor CMOS process flows. In one integration scheme, oxide layer4, which is used in the fabrication of exemplary multi-gate transistor42, can be employed as an oxide liner layer for a planar transistor device44, or alternatively as at least a portion of an ILD layer for the transistor device44. In another embodiment (not shown), oxide layer4could serve as the gate oxide for planar device48. Again numerous features and elements necessary for an actual device are omitted fromFIG. 6in order to clarify features of the embodiment.

Advantageous embodiments of the invention include a method of manufacturing a transistor. The method includes providing a substrate having a top surface, the top surface having a first lattice constant, forming an insulating layer over said top surface, forming an opening in said insulating layer to expose a portion of said top surface, and epitaxially growing an extension on said top surface in said opening, the extension having a second lattice constant that is different from said first lattice constant. The method further includes forming a doped region in said extension, forming a gate dielectric over at least a portion of said extension, and forming a gate electrode over said gate dielectric. In some embodiments, providing a substrate includes providing a wafer; forming a buffer layer on said wafer, and forming a semiconductor layer on said buffer layer, the semiconductor layer having said first lattice constant. Forming an insulating layer could include forming an oxide layer on said top surface and forming a nitride layer on the oxide layer. Forming a doped region in the extension could include ion implanting impurities to form a first source/drain region and a second source/drain region. Forming a gate dielectric could include oxidizing a portion of said extension. In some embodiments, forming a gate dielectric includes forming a semiconductor layer on a portion of said extension, and oxidizing said semiconductor layer on a portion of said extension.