Memory devices and methods of forming memory devices

Some embodiments include an integrated assembly having pillars arranged in an array. The pillars have channel regions between upper and lower source/drain regions. Gating structures are proximate to the channel regions and extend along a row direction. Digit lines are beneath the pillars, extend along a column direction, and are coupled with the lower source/drain regions. Linear structures are above the pillars and extend along the column direction. Bottom electrodes are coupled with the upper source/drain regions. The bottom electrodes have horizontal segments adjacent the upper source/drain regions and have vertical segments extending upwardly from the horizontal segments. The vertical segments are adjacent to lateral sides of the linear structures. Ferroelectric-insulative-material and top-electrode-material are over the bottom electrodes. A slit passes through the top-electrode-material, is directly over one of the linear structures, and extends along the column direction.

TECHNICAL FIELD

Memory devices (e.g., devices comprising FeRAM configurations), and methods of forming memory devices.

BACKGROUND

Memory may utilize memory cells which individually comprise an access transistor in combination with a capacitor. In some applications, the capacitor may be a ferroelectric capacitor and the memory may be ferroelectric random-access memory (FeRAM).

It would be desirable to develop improved memory architecture, and improved methods of forming memory architecture. It would also be desirable for such methods to be applicable for fabrication of FeRAM.

DETAILED DESCRIPTION OF THE ILLUSTRATED EMBODIMENTS

Some embodiments include methods of forming memory architecture (e.g., FeRAM, etc.) in which bottom electrodes are configured as angle plates (e.g., “L-shaped” plates) having vertically-extending legs joining to horizontally-extending legs. The angle plates may be supported by insulative structures (rails) that extend along the angle plates and are adjacent to the vertically-extending legs. The insulative structures may extend along a same direction as digit lines (e.g., a column direction). Ferroelectric material and top-electrode-material may be over the bottom electrodes and the insulative structures. One or more slits may pass through the top-electrode-material and may be aligned with the insulative structures to pattern the top-electrode-material into two or more plates. Voltage of the individual plates may be controlled during various operations associated with a memory array (e.g., READ/WRITE operations). Example embodiments are described with reference toFIGS.1-17.

Referring toFIGS.1-1B, a construction10includes vertically-extending pillars12. The pillars12comprise semiconductor material14. The pillars12are all substantially identical to one another, with the term “substantially identical” meaning identical to within reasonable tolerances of fabrication and measurement.

The semiconductor material14may comprise any suitable composition(s), and in some embodiments may comprise, consist essentially of, or consist of one or more of silicon, germanium, III/V semiconductor material (e.g., gallium phosphide), semiconductor oxide, etc.; with the term III/V semiconductor material referring to semiconductor materials comprising elements selected from groups III and V of the periodic table (with groups III and V being old nomenclature, and now being referred to as groups13and15). In some embodiments, the semiconductor material14may comprise, consist essentially of, or consist of appropriately-doped silicon. The silicon may be in any suitable form, and in some embodiments may be monocrystalline, polycrystalline and/or amorphous.

Each of the pillars12includes a channel region20between an upper source/drain region16and a lower source/drain region18. Stippling is utilized in the drawings to indicate that the source/drain regions16and18are heavily doped. In some embodiments, the source/drain regions16and18may be n-type doped by incorporating one or both of phosphorus and arsenic into the semiconductor material (e.g., silicon)14of the pillars12. In some embodiments, one or both of the source/drain regions16and18may comprise additional conductive material besides the conductively-doped semiconductor material14. For instance, one or both of the source/drain regions16and18may include metal silicide (e.g., titanium silicide, tungsten silicide, etc.) and/or other suitable conductive materials (e.g., titanium, tungsten, etc.). In some embodiments, the pillars12may be considered to be capped by the upper source/drain regions16, with the term “capped” indicating that the upper source/drain regions may or may not include the semiconductor material14of the pillars12.

The pillars12may be considered to be arranged in an array15. The array may be considered to comprise rows17extending along an indicated x-axis direction, and to comprise columns19extending along an indicated y-axis direction.

Insulative material22extends between the upper source/drain regions16. The insulative material22may comprise any suitable composition(s); and in some embodiments may comprise, consist essentially of, or consist of silicon nitride, silicon dioxide, aluminum oxide, etc. In some embodiments, the insulative material22may be referred to as a first insulative material.

A planarized upper surface23extends across the insulative material22and the source/drain regions16. The planarized surface23may be formed utilizing chemical-mechanical polishing (CMP) and/or any other suitable process(es). In some embodiments, the surface23may be referred to as an upper surface of the construction10.

The construction includes conductive structures (digit lines)24under the pillars12. The digit lines24extend along the column direction (the illustrated y-axis direction) and are electrically coupled with the lower source/drain regions18of the pillars. The digit lines may comprise any suitable electrically conductive composition(s); such as, for example, one or more of various metals (e.g., titanium, tungsten, cobalt, nickel, platinum, ruthenium, etc.), metal-containing compositions (e.g., metal silicide, metal nitride, metal carbide, etc.), and/or conductively-doped semiconductor materials (e.g., conductively-doped silicon, conductively-doped germanium, etc.).

In the illustrated embodiment, the digit lines are physically against the lower source/drain regions18. In some embodiments, the digit lines may comprise metal (e.g., titanium, tungsten, etc.), the source/drain regions18may comprise conductively-doped silicon, and metal silicide be present where the silicon of the source/drain regions18interfaces with the digit lines24.

Gating structures (wordlines)25are alongside the pillars12and comprise gates26. The gates26are spaced from the pillars by dielectric material (also referred to as gate dielectric material)28. The gating structures25extend along the row direction (i.e., along the illustrated x-axis direction).

The dielectric material28may comprise any suitable composition(s); and in some embodiments may comprise, consist essentially of, or consist of one or more of silicon nitride, silicon dioxide, aluminum oxide, hafnium oxide, etc.

The dielectric material28is provided between the gates26and the channel regions20, and may extend to any suitable vertical dimension. In the shown embodiment the dielectric material28extends upwardly beyond the uppermost surfaces of the gates26. In other embodiments the dielectric material28may or may not extend vertically beyond the gates26.

The gates (transistor gates)26may be considered to be operatively adjacent to (operatively proximate to) the channel regions20such that a sufficient voltage applied to an individual gate26(specifically along a wordline25comprising the gate) will induce an electric field on a channel region near the gate which enables current flow through the channel region to electrically couple the source/drain regions on opposing sides of the channel region with one another. If the voltage to the gate is below a threshold level, the current will not flow through the channel region, and the source/drain regions on opposing sides of the channel region will not be electrically coupled with one another. The selective control of the coupling/decoupling of the source/drain regions through the level of voltage applied to the gate may be referred to as gated coupling of the source/drain regions.

Shield lines30are alongside the pillars12, and are spaced from the pillars by dielectric material32. The shield lines may be electrically coupled with ground or any other suitable reference voltage. The shield lines30extend along the row direction (i.e., along the illustrated x-axis direction). The shield lines30may be considered to be within regions between the pillars12along the cross-sectional view ofFIG.1A.

The dielectric material32may comprise any suitable composition(s); and in some embodiments may comprise, consist essentially of, or consist of one or more of silicon dioxide, silicon nitride, aluminum oxide, hafnium oxide, etc. In the shown embodiment the dielectric material32extends vertically beyond the shield lines30. In other embodiments the dielectric material32may or may not extend vertically beyond the shield lines30.

In the shown embodiment, each of the pillars12shown along the cross-section ofFIG.1Ahas one side adjacent a gate26, and has an opposing side adjacent a shield line30.

In the shown embodiment, insulative material34is over the gates26and the shield lines30. The insulative material34may comprise any suitable composition(s); and may, for example, comprise silicon dioxide, silicon nitride, aluminum oxide, etc. In some embodiments the material34may comprise a same composition as one or both of the dielectric materials28and32, and in other embodiments the material34may comprise a different composition than at least one of the dielectric materials28and32.

Each of the pillars12is coupled to one of the wordlines25and one of the digit lines24; and accordingly each of the pillars12may be considered to be uniquely addressed by one of the wordlines and one of the digit lines.

The construction10may be supported by a semiconductor base (not shown). The base may comprise semiconductor material; and may, for example, comprise, consist essentially of, or consist of monocrystalline silicon. The base may be referred to as a semiconductor substrate. The term “semiconductor substrate” means any construction comprising semiconductive material, including, but not limited to, bulk semiconductive materials such as a semiconductive wafer (either alone or in assemblies comprising other materials), and semiconductive material layers (either alone or in assemblies comprising other materials). The term “substrate” refers to any supporting structure, including, but not limited to, the semiconductor substrates described above. In some applications, the base may correspond to a semiconductor substrate containing one or more materials associated with integrated circuit fabrication. Such materials may include, for example, one or more of refractory metal materials, barrier materials, diffusion materials, insulator materials, etc.

In some embodiments, the construction10ofFIGS.1-1Bmay be considered to represent a portion of an integrated assembly36.

In the embodiment ofFIGS.1A and1B, a gap is provided within the construction10to break a region of the pillars12above the lower source/drain regions18. The gap enables the view of construction10to be collapsed into a smaller area, which leaves more room for additional materials formed over the construction10at subsequent process stages. It is to be understood that the pillars12extend across the illustrated gap.FIGS.1A-1and1B-1show views along the same cross-sections asFIG.1AandFIG.1B, and show the construction10without the gap ofFIGS.1A and1B.FIGS.1A-1and1B-1are provided to assist the reader in understanding the arrangement of construction10. The views ofFIGS.1A and1B(i.e., the views with the gaps in construction10) will be used for the remaining figures of this disclosure.

Referring toFIGS.2-2B, the assembly36is shown at a process stage subsequent to that ofFIGS.1-1B. Linear insulative structures (rails, beams)38are formed over the upper surface23of construction10. The structures38comprise insulative material39. The material39may comprise any suitable composition(s); and in some embodiments may comprise, consist essentially of, or consist of silicon dioxide, silicon nitride, aluminum oxide, etc. It may be desirable for the material39to be a different composition than the material22so that the material39may be patterned selectively relative to the material22during the formation of the linear structures38.

The illustrated linear structures38are labeled38aand38bso that they may be distinguished relative to one another.

The linear structures38extend along the column direction (the illustrated y-axis direction), and are formed to be between columns of the pillars12. Each of the linear structures38has a pair of opposing lateral surfaces41and43. The surfaces41and43may be referred to as first and second lateral sides, respectively, of the linear structures38.

Each of the linear structures38may be considered to be associated with a pair of the columns19of the pillars12, with such associated columns being along the sides41and43. For instance, the columns19ofFIG.2are labeled as19a-d. Columns19aand19bare along the sides41and43of the linear structure38aand may be considered to be associated with such linear structure. Similarly, columns19cand19dare along the sides41and43of the linear structure38band may be considered to be associated with such linear structure.

In the shown embodiment, the linear structures38laterally overlap portions of the source/drain regions16of the associated columns19, as shown inFIG.2B. In other embodiments, the linear structures38may be formed between the associated columns and may not laterally overlap the source/drain regions16of the associated columns (as described in more detail below with reference toFIG.17).

The linear structures38may be formed with any suitable processing. For instance, an expanse of the material39may be formed across the upper surface23, and such expanse may be patterned utilizing a patterned mask (not shown) and one or more suitable etches.

In the illustrated embodiment, the sidewall surfaces41and43are substantially vertical and extend substantially orthogonally relative to the substantially horizontal upper surface23. The term “substantially vertical” means vertical to within reasonable tolerances of fabrication and measurement, the term “substantially orthogonal” means orthogonal to within reasonable tolerances of fabrication and measurement, and the term “substantially horizontal” means horizontal to within reasonable tolerances of fabrication and measurement.

FIG.2Bshows the pillars12to be on a pitch P along the cross-section of the figure. The linear structures38aand38bare spaced from one another by a gap having width W. The width W may be any suitable dimension, and in some embodiments may be within a range of from about one-fourth of the pitch P to about one-half of the pitch P. In some embodiments, the width W may be within a range of from about 20 nanometers (nm) to about 60 nm. The structures38aand38bhave widths W1along the cross-section ofFIG.2B. In some embodiments, a ratio of W1:W may be within a range of from about 1:2 to about 1:1.

Referring toFIGS.3-3B, bottom-electrode-material40is formed to extend conformally along the linear structures38, and along regions of the upper surface23between the linear structures. The bottom-electrode-material40extends across the upper source/drain regions16, and is electrically coupled with such source/drain regions. In the illustrated embodiment, the bottom-electrode-material40is directly against upper surfaces of the source/drain regions16. The bottom-electrode-material40may have any suitable thickness; and in some embodiments may have a thickness within a range of from about 1 nanometer (nm) to about 5 nm. The source/drain regions16and associated pillars12are shown in dashed-line (phantom) view inFIG.3to indicate that they are under other materials.

A patterning material42is formed over the bottom-electrode-material40. The patterning material42has an undulating topography which includes peaks44over the linear structures38, and valleys46between the peaks. The material42may be formed to any suitable thickness (e.g., a thickness within a range of from about 10 nm to about 30 nm); and may comprise any suitable composition(s). In some embodiments, the material42may comprise, consist essentially of, or consist of one or more of silicon dioxide, silicon nitride and silicon oxynitride. In the embodiment ofFIGS.3-3B, the materials22and42may comprise silicon nitride, and the material34may comprise silicon dioxide.

Referring toFIGS.4-4B, the assembly36is subjected to one or more etches, and possibly also planarization, to remove the materials40and42from over the linear structures (insulative structures)38; and to extend the valleys46through the materials40and42, and to the insulative material22. The valleys46thus become openings46which extend through the materials42and40to the material22. In the illustrated embodiment, the openings46stop at an upper surface of the material22. In other embodiments, the openings46may penetrate into the material22(or may even penetrate through the material22and stop at the underlying material34).

The illustrated embodiment shows the upper surfaces of materials39,40and42being substantially coplanar. In other embodiments at least one of such upper surfaces may be at a different elevational level relative to one or more of the others of such upper surfaces.

The illustrated opening46may, for example, have a width W2along the cross-section ofFIG.4Awithin a range of from about 10 nm to about 30 nm.

Referring toFIGS.5-5B, fill material48is formed within the opening46. Subsequently, CMP and/or other suitable planarization is utilized to form a planar surface47extending across the materials39,40,42and48.

The fill material48may comprise any suitable composition(s); and in some embodiments may comprise, consist essentially of, or consist of one or more of silicon dioxide, silicon nitride and silicon oxynitride. Accordingly, the fill material48may or may not be a same composition as the patterning material42.

Referring toFIGS.6-6B, mask structures (beams, rails)50are formed on the planar surface47, and extend along the row direction (the illustrated x-axis direction). The mask structures50may comprise any suitable composition(s)51; and in some embodiments may comprise, consist essentially of, or consist of carbon-containing material (e.g., amorphous carbon, resist, etc.).

The mask structures50are spaced from one another by intervening gaps (also referred to as spacings or openings)52.

The mask structures50may have any suitable dimensions; and may, for example, have widths W3along the cross-section ofFIG.6Awithin a range of from about 10 nm to about 30 nm.

The embodiment ofFIGS.6and6Ashows the spacings52varying in width along the y-axis direction. In other embodiments, the mask structures may be patterned to be wider than shown inFIGS.6and6Aso that the spacings52are all of about the same width along the y-axis direction, as shown inFIGS.6-1and6A-1.

Referring toFIGS.7-7B, the gaps52are extended through the materials40,42and48, and to an upper surface of the insulative material22. In other embodiments (not shown), the gaps52may punch into the material22, or even through the material22and into the underlying insulative material34.

The gaps52may be extended through the materials42,48and40with any suitable processing, including, for example, dry etching to anisotropically etch through the materials42,48and40. Alternatively, dry etching may be utilized to anisotropically etch through the materials42and48, and then a wet etch may be utilized to extend the openings52through the thin layer corresponding to the bottom-electrode-material40.

The patterning of the bottom-electrode-material40at the process stage ofFIG.4(which forms the bottom-electrode-material40into strips extending along the y-axis as shown in the top view ofFIG.4), and the subsequent processing shown inFIG.7(which subdivides the strips utilizing the trenches52that extend along the x-axis direction) may be considered to pattern the bottom-electrode-material40into bottom-electrode-structures (bottom electrodes)54. Each of the bottom-electrode-structures is over one of the source/drain regions16, and may be considered to be associated with a corresponding one of the vertically-extending pillars12.

FIGS.7-1and7A-1show the embodiment ofFIGS.6-1and6A-1patterned in the manner described above relative toFIGS.7-7B. An advantage of the embodiment ofFIGS.7-1and7A-1is that such may enable larger capacitors to eventually be formed (and may thereby enable associated higher capacitance per capacitor). Another advantage is that such may enable good contact to be obtained between a lower electrode of a capacitor and an underlying source/drain region, even if there is mask misalignment (i.e., may enable better tolerances for mask misalignment). The remaining figures of this disclosure (except for11A-1) show embodiments followingFIGS.6,6A,7and7A(i.e., show embodiments in which the spacings52vary along the y-axis direction), but it is to be understood that analogous embodiments could follow the illustrated processing stages ofFIGS.6-1,6A-1,7-1and7A-1. An example of such analogous embodiments is shown inFIG.11A-1and described below.

Referring toFIGS.8-8C, the materials51,42and48are removed with one or more suitable etches. The bottom electrodes54remain along the linear structures38.

Each of the bottom-electrode-structures54has a vertical segment56along one of sidewalls (41,43) of a linear structure38, and has a horizontal segment58along a source/drain region16. The horizontal segments58join to the vertical segments56at corners60. The corners60may be about 90° (i.e., may be approximately right angles), with the term “about 90°” meaning 90° to within reasonable tolerances of fabrication and measurement. In some embodiments, the term about 90° may mean 90°±10°.

In some embodiments, the horizontal segments58may be referred to as first segments and the vertical segments56may be referred to as second segments. The first and second segments58and56may or may not be substantially orthogonal to one another, depending on whether the sidewalls (41,43) are vertical (as shown) or tapered.

In the illustrated embodiment, the vertical segments56are longer than the horizontal segments58. In other embodiments, the segments56and58may be about the same length as one another, or the horizontal segments58may be longer than the vertical segments56.

The bottom-electrode-structures54may be considered to be configured as angle plates, and in the shown embodiment are in one-to-one correspondence with the upper source/drain regions16. Each of the bottom electrodes54may be considered to be electrically coupled with an associated source/drain region16of an associated pillar12.

The bottom-electrode-structures54adjacent the first lateral sides41of the linear structures38may be considered to correspond to a first set55of the bottom-electrode-structures54, and the bottom-electrode-structures54adjacent the second lateral sides43of the linear structures38may be considered to correspond to a second set57of the bottom-electrode-structures54. The horizontal segments58of the bottom electrodes54within the first set55project in a first direction Q (with direction Q being shown inFIG.8B), and the horizontal segments58of the bottom electrodes54within the second set57project in a second direction R (with direction R being shown inFIG.8B). The direction R is opposite to the direction Q. In some embodiments, the bottom electrodes of the first set55may be considered to be substantially mirror images of the bottom electrodes of the second set57, where the term “substantial mirror image” means a mirror image to within reasonable tolerances of fabrication and measurement.

Referring toFIGS.9-9B, ferroelectric-insulative-material70is formed over the bottom-electrode-structures54, and is directly against the bottom-electrode-structures54. In the shown embodiment the ferroelectric-insulative-material70extends across the material22between the bottom electrodes54, as well as extending over the bottom electrodes, and over the linear features38.

The ferroelectric-insulative-material70may comprise any suitable composition or combination of compositions; and in some example embodiments may include one or more of transition metal oxide, zirconium, zirconium oxide, niobium, niobium oxide, hafnium, hafnium oxide, lead zirconium titanate, and barium strontium titanate. Also, in some example embodiments the ferroelectric-insulative-material may have dopant therein which comprises one or more of silicon, aluminum, lanthanum, yttrium, erbium, calcium, magnesium, strontium, and a rare-earth element.

The ferroelectric-insulative-material70may be formed to any suitable thickness; and in some embodiments may be formed to a thickness within a range of from about 30 Å to about 250 Å.

The top-electrode-material72may have any suitable thickness, and in some embodiments may have a thickness of at least about 10 Å, at least about 100 Å, at least about 500 Å, etc.

The electrode materials40and72may comprise a same composition as one another in some embodiments, or may comprise different compositions relative to one another. In some embodiments, the electrode materials40and72may both comprise, consist essentially of, or consist of titanium nitride.

The integrated assembly36ofFIGS.10-10Bmay be considered to correspond to a portion of a memory array (memory device)78. Such memory array includes memory cells80which each include a capacitor82(with one of the memory cells80and its associated capacitor being diagrammatically indicated inFIG.8B, and with another of the memory cells80and its associated capacitor being diagrammatically indicated inFIG.8A). The capacitors each include one of the bottom electrodes54; and includes regions of the ferroelectric-insulative-material70and the top-electrode-material72.

The individual memory cells80each include an access transistor84coupled with the capacitor82(one of the access transistors84is diagrammatically indicated inFIG.10A). Each of the access transistors84includes a pillar12and a region of a transistor gate26adjacent such pillar.

Each of the memory cells80is uniquely addressed by one of the wordlines25in combination with one of the digit lines24. In some embodiments, the memory cells80may be considered to be substantially identical to one another, and to be representative of a large number of substantially identical memory cells which may be formed across the memory array78. For instance, the memory array may comprise hundreds, thousands, hundreds of thousands, millions, hundreds of millions, etc., of the memory cells. The wordlines25may be representative of a large number of substantially identical wordlines that may extend along rows of the memory array, and the digit lines24may be representative of a large number of substantially identical digit lines that may extend along columns of the memory array. The term “substantially identical” means identical to within reasonable tolerances of fabrication and measurement.

The capacitors82are ferroelectric capacitors comprising the ferroelectric-insulative-material. Accordingly, the memory array78may comprise FeRAM.

Some embodiments include recognition that it may be advantageous to subdivide the top-electrode-material72into multiple plates. Voltage to the individual plates may be independently controlled, which may enable the electric field across the ferroelectric-insulative-material70to be tailored within specific regions of the memory array78during memory operations (e.g., READ/WRITE operations). Such may enable charge/discharge rates of the capacitors82to be increased, which may improve operational speeds associated with memory cells80of the memory array78. It may be particularly advantageous for the top electrode material to be subdivided with slits extending along the column direction (i.e., the y-axis direction of the figures).

FIGS.11-11Bshow the assembly10after slits76are formed to extend through the top-electrode-material72. In the shown embodiment, the slits76stop at the ferroelectric-insulative-material70. In other embodiments (described below with reference toFIGS.15and16) the slits may penetrate through the ferroelectric-insulative-material.

The slits76may be patterned with any suitable processing. For instance, a photoresist mask (not shown) may be used to define locations of the slits, one or more etches may be used to etch through the material72and form the slits in such locations, and then the mask may be removed to leave the configuration ofFIGS.11-11B.

The illustrated slits76extend along the column direction (i.e., the illustrated y-axis direction) and are directly over the linear structures38. Although two slits76are shown, there may or may not be a slit aligned with every one of the linear structures38. Generally, there will be at least one of the slits76.

The slits76subdivide the top-electrode-material72into plate structures (plates)79. Although three of the plates79are formed in the shown embodiment, in other embodiments there may be a different number of plates formed depending on the number of the slits76formed. Generally, there will be at least two of the plates79formed utilizing the slits76.

Control circuitry81(which may also be referred to as a control circuit) may be utilized to provide desired voltages to the plates79(i.e., to independently control voltages to the different plates79). The control circuitry is only shown inFIG.11Bto simplify the drawings.

At least two of the plates may be at a different voltage relative to one another. Specifically, one of the plates may be at a first voltage, and another of the plates may be at a second voltage which is different than the first voltage. In the shown embodiment, the control circuitry81provides voltages D, E and F to the three separate plates79ofFIG.11B. At least one of such voltages may be different than the others. In some embodiments, only one of such voltages is different while the other two are the same as one another.

FIG.11A-1shows an embodiment similar to that ofFIG.11A, but at a process stage following the embodiment described above relative toFIG.7A-1.

The memory array78ofFIG.11may have any suitable configuration. An example FeRAM array78is described schematically with reference toFIG.12. The memory array includes a plurality of substantially identical memory cells80, which each include a ferroelectric capacitor82and an access transistor84. Wordlines25extend along rows of the memory array, and digit lines24extend along columns of the memory array. Each of the memory cells is uniquely addressed utilizing a combination of a wordline and a digit line. The wordlines extend to driver circuitry (Wordline Driver Circuitry)110, and the digit lines24extend to detecting (sensing) circuitry (Sense Amplifier Circuitry)112. The top electrodes of the capacitors82are shown coupled with plate structures79, and the plate structures are shown to be coupled with the control circuitry81.

At least some of the circuitry110,112and81may be directly under the memory array78. One or more of the circuitries110,112and81may include CMOS (complementary metal-oxide-semiconductor), and accordingly some embodiments may include CMOS-under-array architecture.

FIGS.11and12show an embodiment in which each plate structure is shared by two columns of memory cells. In other embodiments, a different number of memory cells may share a plate structure, depending on the number of slits76that are formed. For instance,FIG.13shows an embodiment similar to that ofFIG.11B, but in which a slit76is formed over one of the shown linear structures38and not the other. Thus, only two of the plates79are formed in the shown region of the assembly36.

FIG.14schematically illustrates a region of the memory array78ofFIG.13. The region ofFIG.14is similar to that ofFIG.12, except that three columns of the memory cells80share one of the plate structures79.

The embodiment ofFIG.8Bshows etches utilized for removal of various materials stopping at an upper surface of the material22. In other embodiments, such etches may penetrate into or through the material22, and possibly also into the material34underlying the material22. For instance,FIGS.15and16show embodiments in which etching has penetrated into the material22to form a cavity (gap)88, and in which the ferroelectric-insulative-material70extends into the cavity (FIG.15), or extends across the cavity (FIG.16). In the embodiment ofFIG.16, the cavity (gap)88may be a gas-filled void which is sealed by the ferroelectric-insulative-material70.

FIGS.15and16also illustrate example embodiments in which the slits76penetrate through the ferroelectric-insulative-material70. The slits76are shown to stop at an upper surface of the insulative material39of the linear structures38. In other embodiments, the slits may penetrate into the insulative material39.

The embodiment ofFIG.2Bshows the insulative material39of the linear structures38extending partially across the source/drain regions16adjacent lateral edges of the linear structures. In other embodiments, the linear structures38may not extend across the source/drain regions16. For instance,FIG.17shows an embodiment in which the insulative material39of the linear structures38does not extend across any of the upper source/drain regions16that are adjacent to lateral edges of the linear structures.

The assemblies and structures discussed above may be utilized within integrated circuits (with the term “integrated circuit” meaning an electronic circuit supported by a semiconductor substrate); and may be incorporated into electronic systems. Such electronic systems may be used in, for example, memory modules, device drivers, power modules, communication modems, processor modules, and application-specific modules, and may include multilayer, multichip modules. The electronic systems may be any of a broad range of systems, such as, for example, cameras, wireless devices, displays, chip sets, set top boxes, games, lighting, vehicles, clocks, televisions, cell phones, personal computers, automobiles, industrial control systems, aircraft, etc.

The terms “dielectric” and “insulative” may be utilized to describe materials having insulative electrical properties. The terms are considered synonymous in this disclosure. The utilization of the term “dielectric” in some instances, and the term “insulative” (or “electrically insulative”) in other instances, may be to provide language variation within this disclosure to simplify antecedent basis within the claims that follow, and is not utilized to indicate any significant chemical or electrical differences.

The terms “electrically connected” and “electrically coupled” may both be utilized in this disclosure. The terms are considered synonymous. The utilization of one term in some instances and the other in other instances may be to provide language variation within this disclosure to simplify antecedent basis within the claims that follow.

The cross-sectional views of the accompanying illustrations only show features within the planes of the cross-sections, and do not show materials behind the planes of the cross-sections, unless indicated otherwise, in order to simplify the drawings.

When a structure is referred to above as being “on”, “adjacent” or “against” another structure, it can be directly on the other structure or intervening structures may also be present. In contrast, when a structure is referred to as being “directly on”, “directly adjacent” or “directly against” another structure, there are no intervening structures present. The terms “directly under”, “directly over”, etc., do not indicate direct physical contact (unless expressly stated otherwise), but instead indicate upright alignment.

Structures (e.g., layers, materials, etc.) may be referred to as “extending vertically” to indicate that the structures generally extend upwardly from an underlying base (e.g., substrate). The vertically-extending structures may extend substantially orthogonally relative to an upper surface of the base, or not.

Some embodiments include an integrated assembly having a first memory cell and a second memory cell. The first memory cell comprising a first pillar of semiconductor material, with the first pillar comprising a first upper source/drain region and a first channel region under the first upper source/drain region. The second memory cell comprising a second pillar of semiconductor material, with the second pillar comprising a second upper source/drain region and a second channel region under the second upper source/drain region. A gating structure passes across the first and second channel regions and comprises regions proximate the first and second channel regions, the gating structure extends along a first direction. An insulative structure is over regions of the first and second pillars. The insulative structure extends along a second direction which is substantially orthogonal to the first direction. A first bottom electrode is electrically coupled with the first upper source/drain region, and a second bottom electrode is electrically coupled with the second upper source/drain region. The first and second bottom electrodes are configured as first and second angle plates, respectively. The second angle plate is substantially a mirror image of the first angle plate. The first and second angle plates have horizontal segments adjacent the first and second upper source/drain regions, respectively; and having vertical segments extending upwardly from the horizontal segments. The vertical segments of the first and second angle plates are adjacent lateral sides of the insulative structure. Ferroelectric-insulative-material is over the first and second bottom electrodes. Top-electrode-material is over the ferroelectric-insulative-material. A slit passes through the top-electrode-material and extends along the second direction. The slit is directly over the insulative structure.

Some embodiments include an integrated assembly having pillars arranged in an array. The array has a row direction and a column direction. The pillars have upper source/drain regions, lower source/drain regions, and channel regions between the upper and lower source/drain regions. Gating structures are proximate to the channel regions and extend along the row direction. Conductive structures are beneath the pillars and are electrically coupled with the lower source/drain regions. The conductive structures extend along the column direction. Insulative structures are above the pillars and extend along the column direction. Each of the insulative structures has a first lateral side and an opposing second lateral side, and are associated with a pair of the columns of the pillars along said first and second lateral sides. Bottom electrodes are electrically coupled with the upper source/drain regions. The bottom electrodes are configured as angle plates. The angle plates have horizontal segments adjacent the upper source/drain regions and have vertical segments extending upwardly from the horizontal segments. The vertical segments are adjacent to the lateral sides of the insulative structures. The bottom electrodes include a first set adjacent the first lateral sides and a second set adjacent the second lateral sides. The first set of the bottom electrodes has their horizontal segments projecting in a first direction from their vertical segments. The second set of the bottom electrodes has their horizontal segments projecting in a second direction from their vertical segments. The second direction is opposite to the first direction. A ferroelectric-insulative-material is over the bottom electrodes. A top-electrode-material over the ferroelectric-insulative-material. One or more slits pass through the top-electrode-material and extend along the column direction. Each of the slits is directly over an insulative structure.

Some embodiments include an integrated assembly having pillars arranged in an array. The array has a row direction and a column direction. The pillars have upper source/drain regions, lower source/drain regions, and channel regions between the upper and lower source/drain regions. Shield lines extend along the row direction and are in regions between the pillars. Gating structures are proximate the channel regions and extend along the row direction. Conductive structures are beneath the pillars and are electrically coupled with the lower source/drain regions. The conductive structures extend along the column direction. Linear structures are above the pillars and extend along the column direction. Each of the linear structures has a first lateral side and an opposing second lateral side, and is associated with a pair of the columns of the pillars along said first and second lateral sides. Bottom electrodes are electrically coupled with the upper source/drain regions. The bottom electrodes have first segments adjacent the upper source/drain regions and have second segments extending upwardly from the first segments. The second segments are directly against the lateral sides of the linear structures. The bottom electrodes include a first set along the first lateral sides and a second set along the second lateral sides. The bottom electrodes of the first set have their first segments projecting from their second segments in a first direction. The bottom electrodes of the second set have their first segments projecting from their second segments in a second direction which is opposite to the first direction. A ferroelectric-insulative-material is over the bottom electrodes. A top-electrode-material is over the ferroelectric-insulative-material. One or more slits pass through the top-electrode-material and extend along the column direction. Each of the slits is directly over an associated one of the linear structures.

Some embodiments include a method of forming an integrated assembly. A construction is formed to have an array of pillars comprising semiconductor material. The array comprises rows and columns. The pillars have upper source/drain regions, lower source/drain regions, and channel regions between the upper and lower source/drain regions. The construction includes gating structures extending along the row direction and being proximate the channel regions, and includes conductive structures extending along the column direction and being coupled with the lower source/drain regions. The construction includes a first insulative material between the upper source/drain regions of the pillars. An upper surface of the construction extends across the first insulative material and across upper surfaces of the upper source/drain regions. Linear structures are formed over the upper surface and extend along the column direction. Each of the linear structures has a first lateral side and an opposing second lateral side, and is associated with a pair of columns of the pillars along said first and second lateral sides. Bottom-electrode-material is formed conformally along the linear structures and along regions of the upper surface between the linear structures. The bottom-electrode-material is patterned into bottom-electrode-structures. The bottom-electrode-structures have first segments along the upper surfaces of the upper source/drain regions and have second segments along the sidewalls of the linear structures. Ferroelectric-insulative-material is formed over the bottom-electrode-structures. Top-electrode-material is formed over the ferroelectric-insulative-material. One or more slits are formed to pass through the top-electrode-material. The slits extend along the column direction and each of the slits is directly over an associated one of the linear structures. The slits divide the top-electrode-material into two or more plates.