Semiconductor structure with a multilayer gate oxide and method of fabricating the same

A semiconductor structure with a multilayer gate oxide is provided. The structure includes a substrate. A multilayer gate oxide is disposed on the substrate, wherein the multilayer gate oxide includes a first gate oxide and a second gate oxide. The first gate oxide contacts the substrate and the second gate oxide is disposed on and contacts the first gate oxide. The second gate oxide is hydrophilic. The first gate oxide is formed by a thermal oxidation process. The second gate oxide is formed by a chemical treatment.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a multilayer gate oxide, and more particularly to a semiconductor structure with a multilayer gate oxide and method of fabricating the same.

2. Description of the Prior Art

Field effect transistors (FETs) are commonly used in conventional integrated circuit (IC) design. Due to shrinking technology nodes, devices and shrinking ground rules are the keys to enhance performance and to reduce cost.

In standard MOS devices, silicon oxide is the standard gate dielectric. As the devices are scaled down, the gate dielectric needs to become thinner. The gate dielectric is formed by a thermal oxidation process, since this kind of silicon oxide has better quality. For next generation devices, the thickness of the silicon oxide has to be much smaller than before. Silicon oxide made by thermal oxidation will have pin holes when its thickness is shrunk down to a certain level, however, and the quality of will be deteriorated.

Therefore, a method of making silicon oxide having fewer pin holes is needed.

SUMMARY OF THE INVENTION

One embodiment of the present invention sets forth a semiconductor structure with a multilayer gate oxide. Such a structure includes a substrate. A multilayer gate oxide is disposed on the substrate, wherein the multilayer gate oxide includes a first gate oxide and a second gate oxide. The first gate oxide contacts the substrate and the second gate oxide is disposed on and contacts the first gate oxide. The second gate oxide is hydrophilic.

Another embodiment of the present invention sets forth a method of fabricating a semiconductor structure with a multilayer gate oxide. The method includes providing a substrate. A thermal oxidation process is performed to form a silicon oxide layer on the substrate. Later, a thickness of the silicon oxide layer is reduced to form a first gate oxide. Subsequently, a chemical treatment is performed to the first gate oxide so as to form a second gate oxide on the first gate oxide. A high-K material is then formed to contact the second gate oxide. Finally, a metal gate is formed on the high-K material.

DETAILED DESCRIPTION

FIG. 1illustrates flow charts of an exemplary method of the present invention for forming a multilayer gate oxide.FIG. 2toFIG. 4schematically describe a method of fabricating a multilayer gate oxide according to a first preferred embodiment of the present invention. As shown inFIG. 1andFIG. 2, in step1, a substrate10is provided. The substrate10may be a bulk silicon substrate, a germanium substrate, a gallium arsenide substrate, a silicon germanium substrate, an indium phosphide substrate, a gallium nitride substrate, a silicon carbide substrate, or a silicon on insulator (SOI) substrate. In step2, a thermal oxidation process is performed to form a silicon oxide layer12on the substrate10. The thermal oxidation process may be performed by oxidizing the substrate10at a temperature not less than 1050 degrees Celsius. According to a preferred embodiment of the present invention, a thickness t0of the silicon oxide layer12is above 10 angstroms. Advantageously, the silicon oxide layer12may have a thickness t0of 10 to 20 angstroms. As shown inFIG. 3and step3inFIG. 1, the thickness t0of the silicon oxide layer12is reduced preferably by an etching back process to form a first gate oxide14. The remaining silicon oxide layer12becomes the first gate oxide14, and a first thickness t1of the first gate oxide14is greater than 0. Preferably, a first thickness t1of the first gate oxide14may be 6 to 8 angstroms.

Please refer toFIG. 4and step4inFIG. 1. A chemical treatment is performed on the first gate oxide14so as to form a second gate oxide16on the first gate oxide14. More specifically, the chemical treatment preferably includes using a mixture comprising ammonia hydroxide and hydrogen peroxide to wash the first gate oxide14. After the chemical treatment, the second gate oxide16will grow on the first gate oxide14through the chemical reaction. It is noteworthy that the second gate oxide16is hydrophilic. At this point, a multilayer gate oxide18including the first gate oxide14and the second gate oxide16is completed.

Please refer toFIG. 4. A multilayer gate oxide is provided in the present invention. The multilayer gate oxide18of the present invention is disposed on a substrate10. The multilayer gate oxide18includes a first gate oxide14contacting the substrate10and a second gate oxide16disposed on and contacting the first gate oxide14. The second gate oxide16is hydrophilic. A first thickness t1of the first gate oxide14is greater than a second thickness t2of the second gate oxide16. The first gate oxide14may have the first thickness t1of 6 to 8 angstroms. The second thickness t2of the second gate oxide16is preferably 2 to 6 angstroms. The present invention is not limited to the abovementioned first and second thicknesses t1/t2of the first gate oxide14and the second gate oxide16, however. According to a preferred embodiment of the present invention, the ratio of the first thickness t1to the second thickness t2is not smaller than 3/2. Preferably, the ratio of the first thickness t1to the second thickness t2is 3/2 or 7/3. Furthermore, the first gate oxide14has a chemical formula of SiAOB. The second gate oxide16has chemical formula of SiXOY. The ratio of B to A is greater than the ratio of Y to X. For example, the ratio of B to A is 1.94/1, and the ratio of Y to X is 0.96/1. That is, the first gate oxide14and the second gate oxide16have different physical properties. Moreover, because the silicon oxide layer12is grown to a determined thickness, such as 10 to 20 angstroms, the pin hole problem can be eliminated by making the silicon oxide layer12to have sufficient thickness. Since the silicon oxide layer12does not have the pin hole problem, the first gate oxide14formed by etching back silicon oxide layer12also does not have the pin hole problem, so the quality of the first gate oxide14is enhanced. Because the second gate oxide16is formed by the chemical treatment, the second gate oxide16has hydroxides bonded thereon, and the hydrophilic property of the second gate oxide16is thus increased. The second gate oxide16is more hydrophilic than the first gate oxide14. In other words, the second gate oxide16has a smaller water contact angle than the first gate oxide14has.

The method illustrated inFIG. 1toFIG. 4can be applied to fabricating semiconductor structures such as high-K metal gate transistors. The method of forming a multilayer gate oxide of the present invention can also be utilized in other fields, and is not limited to the high-K metal gate transistors. For example, the method of forming a multilayer gate oxide of the present invention can be applied to make polysilicon gate transistors.

FIG. 2toFIG. 7schematically show a method of fabricating a high-K metal gate transistor with a multilayer gate oxide by a high-K dielectric first process according to a second preferred embodiment of the present invention, wherein like reference numerals are used to refer to like elements throughout. A multilayer gate oxide18is formed according to the method illustrated inFIG. 2toFIG. 4. As shown inFIG. 2toFIG. 4, a first gate oxide14is formed on a substrate10by a thermal oxidation process and followed by an etching back process. A second gate oxide16is formed on the first gate oxide14by a chemical treatment. For details of the fabricating methods and properties of the first gate oxide14and the second gate oxide16, please refer to the first preferred embodiment of the present invention.

As shown inFIG. 5, a high-K dielectric20is formed on the second gate oxide16. Because the second gate oxide16is formed by chemical treatment, the second gate oxide16is hydrophilic. Therefore, the high-K dielectric20can attach well to the second gate oxide16. After that, a barrier layer (not shown) can be optionally formed on the high-K dielectric20. The barrier layer is for protecting the high-K dielectric20from being damaged when a dummy gate is removed in a subsequent process. Then, a polysilicon layer22and a cap layer24are formed on the high-K dielectric20in sequence. As shown inFIG. 6, the first gate oxide14, the second gate oxide16, the high-K dielectric20, the polysilicon layer22, and the cap layer24are patterned to form a gate structure26. The patterned polysilicon layer22becomes a dummy gate122. Therefore, the first gate oxide14, the second gate oxide16, the high-K dielectric20, the dummy gate122, and the cap layer24constitute the gate structure26. The first gate oxide14, the second gate oxide16and the high-K dielectric20are all in a rectangular profile. A spacer28is formed to surround the gate structure26. After that, a source/drain doped region30is formed in the substrate10at two sides of the gate structure26. Later, a dielectric layer32is formed to cover the gate structure26, the spacer28and the substrate10.

As shown inFIG. 7, the dielectric layer32is planarized and the cap layer24is removed to expose the dummy gate122. Later, the dummy gate122is removed to form a recess34. Then, a work function layer221fills in the recess34. Later, a metal filling layer222is formed to fill in the recess34. At this point, a high-K metal gate transistor100with a multilayer gate oxide18fabricated by a high-K dielectric first process is completed. As shown inFIG. 7, the semiconductor structure with a multilayer gate oxide, such as the high-K metal gate transistor100is provided. The high-K metal gate transistor100has a multilayer gate oxide18disposed on a substrate10. For details of the fabricating methods and properties of the first gate oxide14and the second gate oxide16please refer to the first preferred embodiment of the present invention. A high-K dielectric20contacts the second gate oxide16of the multilayer gate oxide18. The high-K dielectric20can be thicker or thinner than the multilayer gate oxide18. The high-K dielectric20includes ZrO2, HfO2Al2O3, BST, PZT, ZrSiO2, HfSiO2, TaO2or other suitable high-K materials.

FIG. 8toFIG. 10schematically show a method of fabricating a high-K metal gate transistor with a multilayer gate oxide by a high-K dielectric last process according to a third embodiment of the present invention, wherein like reference numerals are used to refer to like elements throughout. As shown inFIG. 8, a substrate10is provided. Later, a dummy gate oxide layer118, a dummy gate122, a cap layer24are formed in sequence to forma gate structure126on the substrate10. The dummy gate122may include polysilicon. After that, a spacer28is formed to surround the gate structure126. After that, a source/drain doped region30is formed at two sides of the gate structure126. Later, a dielectric layer32is formed to cover the gate structure126, the spacer28and the substrate10.

As shown inFIG. 9, the dielectric layer32is planarized and the cap layer24is removed to expose the dummy gate122. Then, the dummy gate122and the dummy gate oxide layer118are removed to form a recess134. The substrate10is exposed through the recess134. As shown inFIG. 10, a multilayer gate oxide18is formed in the recess134and on the substrate10according to the method illustrated inFIG. 2toFIG. 4. For details of the fabricating methods and properties of the first gate oxide14and the second gate oxide16, please refer to the first preferred embodiment of the present invention.

As shown inFIG. 10, the first gate oxide14and the second gate oxide16form a rectangular profile. After that, a high-K dielectric120is formed to conformally cover two sidewalls of the recess134, and the high-K dielectric120contacts the second gate oxide16. Therefore, the high-K dielectric120forms a U-shaped profile. Later, a work function layer221is formed in the recess134. Then, a metal filling layer222is formed in the recess134. At this point, a high-K metal gate transistor200with a multilayer gate oxide18fabricated by a high-K dielectric last process is completed. As shown inFIG. 10, the semiconductor structure with a multilayer gate oxide, such as the high-K metal gate transistor200is provided. The primary difference between the high-K metal gate transistor100and the high-K metal gate transistor200is that the high-K dielectric120of the high-K metal gate transistor200is U-shaped and the high-K dielectric20of the high-K transistor100is rectangular.

One advantage of the semiconductor structure with a multilayer gate oxide disclosed and described herein is that, because the second gate oxide is formed by chemical treatment, the second gate oxide is hydrophilic. Therefore, the high-K material can contact to the second gate oxide tightly. Furthermore, the first gate oxide is formed by a thermal oxidation process. Therefore, the first gate oxide has good quality without pin holes thereon.