Liquid crystal display having pixel data self-retaining functionality and operation method thereof

A liquid crystal display having pixel data self-retaining functionality includes a gate line for delivering a gate signal, a data line for delivering a data signal, a control unit for providing a first control signal and a second control signal, a data switch, a voltage-control inverter, a liquid crystal capacitor, and a pass transistor. The data switch is utilized for inputting the data signal to become a first data signal according to the gate signal. The voltage-control inverter is utilized for inverting the first data signal to generate a second data signal furnished to the liquid crystal capacitor according to the enable operation of the first control signal. The pass transistor is used for passing the second data signal to become the first data signal or for passing the first data signal to become the second data signal according to the second control signal.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a liquid crystal display and an operation method thereof, and more particularly, to a liquid crystal display having pixel data self-retaining functionality and an operation method thereof.

2. Description of the Prior Art

Along with the advantages of thin appearance, low power consumption, and low radiation, liquid crystal displays (LCDs) have been widely applied in various electronic products for panel displaying. The operation of a liquid crystal display is featured by varying voltage drops between opposite sides of a liquid crystal layer for twisting the angles of the liquid crystal molecules in the liquid crystal layer so that the transmittance of the liquid crystal layer can be controlled for illustrating images with the aid of light source provided by a backlight module or ambient light.FIG. 1is a schematic diagram showing a prior-art liquid crystal display100. As shown inFIG. 1, the liquid crystal display100comprises a gate driver110, a source driver120, a gate line130, a data line140and a pixel unit150. The pixel unit150includes a data switch155, a liquid crystal capacitor180and a storage capacitor185. The source driver120is utilized for providing a data signal to be written into the pixel unit150. The gate driver110is employed to generate a gate signal for providing a control of writing the data signal into the pixel unit150.

In the operation of the liquid crystal display100, even though the image being displayed is still, the gate driver110and the source driver120continue outputting the gate signal and the data signal so as to continue performing a periodical operation of writing the data signal into the pixel unit150. That is, the power consumption of displaying a still frame is substantially identical to that of displaying motion frames. With the aim of reducing the power consumption of displaying a still frame, existing technology normally embeds a memory unit in each pixel unit. The memory unit embedded is devised based on the complicated architecture of static random access memory (SRAM). In view of that, the aperture ratio of each pixel unit is significantly reduced.

SUMMARY OF THE INVENTION

In accordance with an embodiment of the present invention, a liquid crystal display having pixel data self-retaining functionality is provided. The liquid crystal display comprises a gate line for delivering a gate signal, a data line for delivering a data signal, a data switch, a voltage-control inverter, a liquid crystal capacitor, a pass transistor, a control unit, a common voltage generation unit, and a power source. The data switch comprises a first end electrically connected to the data line for receiving the data signal, a gate end electrically connected to the gate line for receiving the gate signal, and a second end. The voltage-control inverter comprises an input end electrically connected to the second end of the data switch, an output end, and an enable end. The liquid crystal capacitor is electrically connected to the output end of the voltage-control inverter. The pass transistor comprises a first end electrically connected to the output end of the voltage-control inverter, a second end electrically connected to the input end of the voltage-control inverter, and a gate end. The control unit, electrically connected to the enable end of the voltage-control inverter and the gate end of the pass transistor, is utilized for controlling circuit operations of the voltage-control inverter and the pass transistor. The common voltage generation unit is electrically connected to the liquid crystal capacitor. The power source, electrically connected to the control unit and the common voltage generation unit, is put in use for powering the control unit and the common voltage generation unit.

The present invention further provides an operation method for use in a liquid crystal display. The liquid crystal display comprises a gate driver for providing a gate signal, a source driver for providing a data signal, a control unit for providing a first control signal and a second control signal, a data switch, a voltage-control inverter, a liquid crystal capacitor, a pass transistor, and a common voltage generation unit for providing a common voltage. The data switch is employed to provide a control of inputting the data signal to become a first data signal according to the gate signal. The voltage-control inverter is utilized for inverting the first data signal to generate a second data signal according to an enable operation of the first control signal. The liquid crystal capacitor is used for controlling liquid-crystal transmittance according to the second data signal and the common voltage. The pass transistor is put in use for providing a control of passing the second data signal to become the first data signal according to the second control signal, or for providing a control of passing the first data signal to become the second data signal according to the second control signal. The operation method comprises: the control unit providing the second control signal for turning off the pass transistor during a first still interval after the liquid crystal display enters a still mode; the control unit providing the first control signal so as to enable the voltage-control inverter for inverting the first data signal to generate the second data signal which is furnished to the liquid crystal capacitor during the first still interval; the control unit providing the first control signal for disabling the voltage-control inverter during a second still interval; the control unit providing the second control signal for turning off the pass transistor during the second still interval; the control unit providing the first control signal for disabling the voltage-control inverter during a third still interval; the control unit providing the second control signal for turning on the pass transistor so as to pass the second data signal to become the first data signal during the third still interval; the control unit providing the first control signal for disabling the voltage-control inverter during a fourth still interval; and the control unit providing the second control signal for turning off the pass transistor during the fourth still interval.

Moreover, the present invention provides another operation method for use in a liquid crystal display. The liquid crystal display comprises a gate driver for providing a gate signal, a source driver for providing a data signal, a control unit for providing a control signal, a data switch, a voltage-control inverter, a liquid crystal capacitor, a pass transistor, and a common voltage generation unit for providing a common voltage. The data switch is employed to provide a control of inputting the data signal to become a first data signal according to the gate signal. The voltage-control inverter is utilized for inverting the first data signal to generate a second data signal according to an enable operation of the control signal. The liquid crystal capacitor is used for controlling liquid-crystal transmittance according to the second data signal and the common voltage. The pass transistor is put in use for providing a control of passing the second data signal to become the first data signal according to the control signal, or for providing a control of passing the first data signal to become the second data signal according to the control signal. The operation method comprises: the control unit providing the control signal having a first voltage level for turning off the pass transistor and for enabling the voltage-control inverter so as to invert the first data signal for generating the second data signal furnished to the liquid crystal capacitor during a first still interval after the liquid crystal display enters a still mode; and the control unit providing the control signal having a second voltage level for disabling the voltage-control inverter and for turning on the pass transistor so as to pass the second data signal to become the first data signal during a second still interval.

DETAILED DESCRIPTION

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. Here, it is to be noted that the present invention is not limited thereto. Furthermore, the step serial numbers regarding the operation method are not meant thereto limit the operating sequence, and any rearrangement of the operating sequence for achieving same functionality is still within the spirit and scope of the invention.

FIG. 2is a schematic diagram showing a liquid crystal display200in accordance with a first embodiment of the present invention. The liquid crystal display200is preferable to be a transflective-mode LCD or a reflective-mode LCD. However, the liquid crystal display200may be a transmission-mode LCD. As shown inFIG. 2, the liquid crystal display200comprises a gate driver210, a source driver220, a plurality of gate lines230, a plurality of data lines240, a plurality of pixel units250, a control unit295, a common voltage generation unit296, and a power source297. In one embodiment, the pixel units250may comprise plural red pixel units, plural green pixel units and plural blue pixel units. For ease of explanation, the liquid crystal display200illustrates a gate line GLi of the gate lines230, a data line DLn of the data lines240, and a pixel unit PUa of the pixel units250. The pixel unit PUa may be a red pixel unit, a green pixel unit, or a blue pixel unit. The gate line GLi is electrically connected to the gate driver210and functions to deliver a gate signal SGi. The data line DLn is electrically connected to the source driver220and functions to deliver a data signal SDn. The control unit295comprises a first signal output end for outputting a first control signal SLC1, a second signal output end for outputting a second control signal SLC2, a first voltage output end for outputting a first power voltage Vdd, and a second voltage output end for outputting a second power voltage Vss. The first control signal SLC1, the second control signal SLC2, the first power voltage Vdd and the second power voltage Vss are all furnished to each pixel unit250so that the liquid crystal display200is able to perform a still mode operation accordingly.

The common voltage generation unit296comprises an output end for outputting a common voltage Vcom furnished to each pixel unit250. The common voltage Vcom can be a direct-current (DC) voltage or an alternating-current (AC) voltage. The power source297, electrically connected to the control unit295and the common voltage generation unit296, is utilized for powering the control unit295and the common voltage generation unit296. The power source297comprises a solar cell module298which is used to perform an energy conversion operation for powering the control unit295and the common voltage generation unit296. If the electrical energy generated by the solar cell module298is insufficient to power the control unit295and the common voltage generation unit296, the control unit295and the common voltage generation unit296are powered by the other power supply (not shown) of the power source297. The pixel unit PUa comprises a data switch255, a voltage-control inverter260, a liquid crystal capacitor280, a storage capacitor285and a pass transistor290. The data switch255provides a control of inputting the data signal SDn to become a first data signal SDx1according to the gate signal SGi. The data switch255comprises a first end electrically connected to the data line DLn for receiving the data signal SDn, a gate end electrically connected to the gate line GLi for receiving the gate signal SGi, and a second end electrically connected to the voltage-control inverter260and the pass transistor290. The data switch255can be a thin film transistor or a field effect transistor. The voltage-control inverter260is enabled by the first control signal SLC1so as to invert the first data signal SDx1for generating a second data signal SDx2. The voltage-control inverter260comprises an input end electrically connected to the second end of the data switch255, an enable end261electrically connected to the first signal output end of the control unit295for receiving the first control signal SLC1, an output end electrically connected to the liquid crystal capacitor280, the storage capacitor285and the pass transistor290, a first power input end electrically connected to the first voltage output end of the control unit295for receiving the first power voltage Vdd, and a second power input end electrically connected to the second voltage output end of the control unit295for receiving the second power voltage Vss.

The liquid crystal capacitor280comprises a first end electrically connected to the output end of the voltage-control inverter260and a second end electrically connected to the output end of the common voltage generation unit296for receiving the common voltage Vcom. The liquid crystal capacitor280provides a liquid crystal voltage Vp based on the second data signal SDx2and the common voltage Vcom. And the liquid crystal voltage Vp is used to control the liquid-crystal transmittance of the pixel unit PUa. The storage capacitor285, electrically connected between the first and second ends of the liquid crystal capacitor280, is employed to assist in storing the second data signal SDx2. The pass transistor290is employed to control an electrical connection between the input and output ends of the voltage-control inverter260according to the second control signal SLC2. That is, the pass transistor290is put in use for providing a control of passing the second data signal SDx2to become the first data signal SDx1or passing the first data signal SDx1to become the second data signal SDx2. The pass transistor290comprises a first end electrically connected to the output end of the voltage-control inverter260, a gate end electrically connected to the second signal output end of the control unit295for receiving the second control signal SLC2, and a second end electrically connected to the input end of the voltage-control inverter260. The pass transistor290can be a thin film transistor or a field effect transistor.

After the liquid crystal display200enters a still mode for displaying a still frame, each pixel unit250is able to perform a pixel data self-retaining operation by making use of the voltage-control inverter260and the pass transistor290therein. In addition, although the voltage level of the second data signal SDx2may drift around, which causes the liquid crystal voltage Vp to drift as well, the voltage level of the second data signal SDx2can be refreshed to become the first power voltage Vdd or the second power voltage Vss through an inversion operation of the voltage-control inverter260. That is, the inversion operation of the voltage-control inverter260can also be employed to provide a data self-refreshing functionality for refreshing the second data signal SDx2. Compared with the pixel unit based on SRAM architecture in the prior-art liquid crystal display, the circuit structure of each pixel unit250in the liquid crystal display200is significantly simplified to increase the aperture ratio of each pixel unit250and also to bring the cost down.

FIG. 3is a schematic diagram showing a liquid crystal display300in accordance with a second embodiment of the present invention. As shown inFIG. 3, the circuit structure of the liquid crystal display300is similar to that of the liquid crystal display200shown inFIG. 2, differing in that the common voltage generation unit296is replaced with a common voltage generation unit396and the pixel units250are replaced with a plurality of pixel units350, wherein the pixel unit PUa is replaced with a pixel unit PUb. The pixel unit Pub may be a red pixel unit, a green pixel unit, or a blue pixel unit. The pixel unit Pub comprises the data switch255, a voltage-control inverter360, a liquid crystal capacitor380, a storage capacitor385and the pass transistor290. The voltage-control inverter360comprises a first transistor361, a second transistor362, a third transistor363and a fourth transistor364. The second transistor362and the third transistor363are put in use together for enabling/disabling the circuit output operation of the voltage-control inverter360according to the first control signal SLC1. The first transistor361, the second transistor362and the third transistor363are P-type thin film transistors or P-type field effect transistors. The fourth transistor364and the pass transistor290are N-type thin film transistors or N-type field effect transistors. The common voltage generation unit396comprises a first output end for outputting a first common voltage Vcom1and a second output end for outputting a second common voltage Vcom2. The first common voltage Vcom1and the second common voltage Vcom2can be DC voltages or AC voltages.

The first transistor361comprises a first end electrically connected to the first voltage output end of the control unit295for receiving the first power voltage Vdd, a gate end electrically connected to the second end of the data switch255, and a second end. The second transistor362comprises a first end electrically connected to the second end of the first transistor361, a gate end electrically connected to the first signal output end of the control unit295for receiving the first control signal SLC1, and a second end electrically connected to the liquid crystal capacitor380, the storage capacitor385and the first end of the pass transistor290. The third transistor363comprises a first end electrically connected to the second end of the second transistor362, a gate end electrically connected to the gate end of the second transistor362, and a second end. It is noted that the gate ends of the second transistor362and the third transistor363are functioning as an enable end of the voltage-control inverter360. The fourth transistor364comprises a first end electrically connected to the second end of the third transistor363, a gate end electrically connected to the gate end of the first transistor361, and a second end electrically connected to the second voltage output end of the control unit295for receiving the second power voltage Vss. The liquid crystal capacitor380comprises a first end electrically connected to the second end of the second transistor362and a second end electrically connected to the first output end of the common voltage generation unit396for receiving the first common voltage Vcom1. The liquid crystal capacitor380provides a liquid crystal voltage Vq based on the second data signal SDx2and the first common voltage Vcom1. And the liquid crystal voltage Vq is used to control the liquid-crystal transmittance of the pixel unit Pub. The storage capacitor385comprises a first end electrically connected to the first end of the liquid crystal capacitor380and a second end electrically connected to the second output end of the common voltage generation unit396for receiving the second common voltage Vcom2. The storage capacitor385is employed to assist in storing the second data signal SDx2.

FIG. 4is a schematic diagram showing a liquid crystal display400in accordance with a third embodiment of the present invention. As shown inFIG. 4, the circuit structure of the liquid crystal display400is similar to that of the liquid crystal display300shown inFIG. 3, differing in that the pixel units350are replaced with a plurality of pixel units450, wherein the pixel unit PUb is replaced with a pixel unit PUc. The pixel unit PUc may be a red pixel unit, a green pixel unit, or a blue pixel unit. The pixel unit PUc comprises the data switch255, a voltage-control inverter460, the liquid crystal capacitor380, the storage capacitor385and a pass transistor490. The voltage-control inverter460comprises a first transistor461, a second transistor462, a third transistor463and a fourth transistor464. The second transistor462and the third transistor463are put in use together for enabling/disabling the circuit output operation of the voltage-control inverter460according to the first control signal SLC1. The first transistor461and the pass transistor490are P-type thin film transistors or P-type field effect transistors. The second transistor462, the third transistor463and the fourth transistor464are N-type thin film transistors or N-type field effect transistors. The pass transistor490comprises a first end electrically connected to the first end of the liquid crystal capacitor380, a gate end electrically connected to the second signal output end of the control unit295for receiving the second control signal SLC2, and a second end electrically connected to the second end of the data switch255.

The first transistor461comprises a first end electrically connected to the first voltage output end of the control unit295for receiving the first power voltage Vdd, a gate end electrically connected to the second end of the data switch255, and a second end. The second transistor462comprises a first end electrically connected to the second end of the first transistor461, a gate end electrically connected to the first signal output end of the control unit295for receiving the first control signal SLC1, and a second end electrically connected to the liquid crystal capacitor380, the storage capacitor385and the first end of the pass transistor490. The third transistor463comprises a first end electrically connected to the second end of the second transistor462, a gate end electrically connected to the gate end of the second transistor462, and a second end. It is noted that the gate ends of the second transistor462and the third transistor463are functioning as an enable end of the voltage-control inverter460. The fourth transistor464comprises a first end electrically connected to the second end of the third transistor463, a gate end electrically connected to the gate end of the first transistor461, and a second end electrically connected to the second voltage output end of the control unit295for receiving the second power voltage Vss.

FIG. 5is a schematic diagram showing related signal waveforms regarding a first circuit operation case of the liquid crystal display200shown inFIG. 2, having time along the abscissa. The signal waveforms inFIG. 5, from top to bottom, are the gate signal SGi, the data signal SDn, the common voltage Vcom, the first control signal SLC1, the second control signal SLC2, the first power voltage Vdd, and the second power voltage Vss. When the liquid crystal display200is working in a normal mode, the data signal SDn provided by the source driver220is a multi-level analog voltage Vanalog, the gate driver210provides the gate signal SGi based on a normal scanning mode, the data switch255inputs the data signal SDn to become the first data signal SDx1according to the gate signal SGi under the normal scanning mode, the common voltage Vcom provided by the common voltage generation unit296is an AC voltage or a DC voltage required for normal-mode operation, the control unit295provides the first control signal SLC1having high voltage level for disabling the voltage-control inverter260, the control unit295provides the second control signal SLC2having high voltage level so as to turn on the pass transistor290for passing the first data signal SDx1to become the second data signal SDx2, and both the first power voltage Vdd and the second power voltage Vss generated by the control unit295are low voltage Vb.

After the liquid crystal display200enters a still mode for displaying a still frame, during a preliminary interval Tpre1, the data signal SDn provided by the source driver220is a bi-level digital voltage Vdigital, the data switch255inputs the bi-level digital voltage Vdigital to become the first data signal SDx1according to the gate signal SGi under the normal scanning mode, the common voltage generation unit296provides the common voltage Vcom having a first voltage level, the control unit295provides the first control signal SLC1having high voltage level so as to continue disabling the voltage-control inverter260, the control unit295provides the second control signal SLC2having high voltage level so as to continue turning on the pass transistor290and thereby to continue passing the first data signal SDx1to become the second data signal SDx2, and both the first power voltage Vdd and the second power voltage Vss generated by the control unit295hold low voltage Vb. It is noted that the second data signal SDx2is then becoming the bi-level digital voltage Vdigital. Besides, the gate driver210is turned off after the data switch255inputs the bi-level digital voltage Vdigital to become the first data signal SDx1. Further, the source driver220is turned off after the gate driver210is turned off and thus the data signal SDn becomes a floating voltage.

During a first still interval T11, the common voltage generation unit296switches the voltage level of the common voltage Vcom from the first voltage level to a second voltage level. The control unit295switches the first power voltage Vdd from low voltage Vb to high voltage Vh. The control unit295provides the second control signal SLC2having low voltage level for turning off the pass transistor290. The control unit295provides the first control signal SLC1having low voltage level so as to enable the voltage-control inverter260for inverting the first data signal SDx1to generate the second data signal SDx2which is furnished to the liquid crystal capacitor280. During a second still interval T12, the control unit295provides the first control signal SLC1having high voltage level and the second control signal SLC2having low voltage level for disabling the voltage-control inverter260and for turning off the pass transistor290respectively. During a third still interval T13, the control unit295provides the first control signal SLC1having high voltage level for disabling the voltage-control inverter260. And the control unit295provides the second control signal SLC2having high voltage level so as to turn on the pass transistor290for passing the second data signal SDx2to become the first data signal SDx1. During a fourth still interval T14, the control unit295provides the first control signal SLC1having high voltage level and the second control signal SLC2having low voltage level for disabling the voltage-control inverter260and for turning off the pass transistor290respectively. It is noted that the falling edge of the first control signal SLC1is not required to align the falling/rising edge of the common voltage Vcom.

The circuit operations during a fifth still interval T15, a sixth still interval T16, a seventh still interval T17and an eighth still interval T18are similar to the aforementioned circuit operations during the first still interval T11, the second still interval T12, the third still interval T13and the fourth still interval T14respectively, differing only in that the common voltage generation unit296switches the voltage level of the common voltage Vcom from the second voltage level to the first voltage level. In another embodiment, after entering the still mode, the common voltage generation unit296may provide the common voltage Vcom having fixed voltage level. After the eighth still interval T18, as long as the operation of the still mode continues, the liquid crystal display200performs the aforementioned circuit operations of the first through eighth still intervals T11˜T18periodically and repetitively. When the liquid crystal display200ceases the operation of the still mode, the operation of the liquid crystal display200may return to the normal mode. If the operation of the liquid crystal display200changes from the still mode to the normal mode after disabling the voltage-control inverter260and turning on the pass transistor290which are corresponding to the circuit operations during the third still interval T13, the control unit295switches the first power voltage Vdd from high voltage Vh to low voltage Vb, the source driver220is turned on for providing the data signal SDn having the multi-level analog voltage Vanalog, the gate driver210is turned on for providing the gate signal SGi based on the normal scanning mode, and the common voltage Vcom provided by the common voltage generation unit296returns to the AC or DC voltage required for normal-mode operation. If the common voltage Vcom inFIG. 5is replaced with the first and second common voltages Vcom1/Vcom2, the signal waveforms illustrated inFIG. 5can be applied to make clear the operation of the liquid crystal display300shown inFIG. 3.

FIG. 6is a schematic diagram showing related signal waveforms regarding the second circuit operation case of the liquid crystal display200shown inFIG. 2, having time along the abscissa. The signal waveforms inFIG. 6, from top to bottom, are the gate signal SGi, the data signal SDn, the common voltage Vcom, the first control signal SLC1, the second control signal SLC2, the first power voltage Vdd, and the second power voltage Vss. When the liquid crystal display200is working in a normal mode or during a preliminary interval Tpre8under a still mode, the signal waveforms shown inFIG. 6are identical to the signal waveforms of the first circuit operation case illustrated inFIG. 5, and for the sake of brevity, further similar discussion thereof is omitted.

During a fourth still interval T81under the still mode, the common voltage generation unit296still provides the common voltage Vcom having the first voltage level. The control unit295switches the first power voltage Vdd from low voltage Vb to high voltage Vh. The control unit295provides the first control signal SLC1having high voltage level and the second control signal SLC2having low voltage level for disabling the voltage-control inverter260and for turning off the pass transistor290respectively. It is noted that the rising edge of the first power voltage Vdd is required only to occur before the first falling edge of the first control signal SLC1after entering the still mode, i.e. the rising edge of the first power voltage Vdd is not required to align the falling edge of the second control signal SLC2.

During a first still interval T82under the still mode, the control unit295provides the second control signal SLC2having low voltage level for turning off the pass transistor290. The control unit295provides the first control signal SLC1having low voltage level so as to enable the voltage-control inverter260for inverting the first data signal SDx1to generate the second data signal SDx2which is furnished to the liquid crystal capacitor280. And the common voltage generation unit296switches the voltage level of the common voltage Vcom from the first voltage level to the second voltage level. The rising/falling edge of the common voltage Vcom is not required to align the rising/falling edge of the first control signal SLC1. During a second still interval T83under the still mode, the control unit295provides the first control signal SLC1having high voltage level and the second control signal SLC2having low voltage level for disabling the voltage-control inverter260and for turning off the pass transistor290respectively. During a third still interval T84under the still mode, the control unit295provides the first control signal SLC1having high voltage level for disabling the voltage-control inverter260. And the control unit295provides the second control signal SLC2having high voltage level so as to turn on the pass transistor290for passing the second data signal SDx2to become the first data signal SDx1. It is noted that the fourth still interval T81is followed by the first, second and third intervals T82˜T84sequentially.

The circuit operations during plural still intervals T85, T86, T87and T88are similar to the aforementioned circuit operations during the fourth still interval T81, the first still interval T82, the second still interval T83and the third still interval T84respectively, differing only in that the common voltage generation unit296switches the voltage level of the common voltage Vcom from the second voltage level to the first voltage level during the still interval T86. In another embodiment, after entering the still mode, the common voltage generation unit296may provide the common voltage Vcom having fixed voltage level. After the still interval T88, as long as the operation of the still mode continues, the liquid crystal display200performs the aforementioned circuit operations of the still intervals T81˜T88periodically and repetitively. When the liquid crystal display200ceases the operation of the still mode, the operation of the liquid crystal display200may change from the still mode to the normal mode after disabling the voltage-control inverter260and turning on the pass transistor290which are corresponding to the circuit operations during the third still interval T84, and the corresponding signal waveforms thereof shown inFIG. 6are identical to those of the first circuit operation case illustrated inFIG. 5. Similarly, if the common voltage Vcom inFIG. 6is replaced with the first and second common voltages Vcom1/Vcom2, the signal waveforms illustrated inFIG. 6can be applied to make clear the operation of the liquid crystal display300shown inFIG. 3.

FIG. 7is a schematic diagram showing related signal waveforms regarding the circuit operation of the liquid crystal display400shown inFIG. 4, having time along the abscissa. The signal waveforms inFIG. 7, from top to bottom, are the gate signal SGi, the data signal SDn, the first and second common voltages Vcom1/Vcom2, the first control signal SLC1, the second control signal SLC2, the first power voltage Vdd, and the second power voltage Vss. When the liquid crystal display400is working in a normal mode, the data signal SDn provided by the source driver220is a multi-level analog voltage Vanalog, the gate driver210provides the gate signal SGi based on a normal scanning mode, the data switch255inputs the data signal SDn to become the first data signal SDx1according to the gate signal SGi under the normal scanning mode, the first and second common voltages Vcom1/Vcom2provided by the common voltage generation unit396are AC or DC voltages required for normal-mode operation, the control unit295provides the first control signal SLC1having low voltage level for disabling the voltage-control inverter460, the control unit295provides the second control signal SLC2having low voltage level so as to turn on the pass transistor490for passing the first data signal SDx1to become the second data signal SDx2, and both the first power voltage Vdd and the second power voltage Vss generated by the control unit295are low voltage Vb.

After the liquid crystal display400enters a still mode for displaying a still frame, during a preliminary interval Tpre2, the data signal SDn provided by the source driver220is a bi-level digital voltage Vdigital, the data switch255inputs the bi-level digital voltage Vdigital to become the first data signal SDx1according to the gate signal SGi under the normal scanning mode, the common voltage generation unit396provides the first and second common voltages Vcom1/Vcom2having a first voltage level, the control unit295provides the first control signal SLC1having low voltage level so as to continue disabling the voltage-control inverter460, the control unit295provides the second control signal SLC2having low voltage level so as to continue turning on the pass transistor490and thereby to continue passing the first data signal SDx1to become the second data signal SDx2, and both the first power voltage Vdd and the second power voltage Vss generated by the control unit295hold low voltage Vb. Besides, the gate driver210is turned off after the data switch255inputs the bi-level digital voltage Vdigital to become the first data signal SDx1. Further, the source driver220is turned off after the gate driver210is turned off and thus the data signal SDn becomes a floating voltage.

During a first still interval T21, the common voltage generation unit396switches the voltage level of the first and second common voltages Vcom1/Vcom2from the first voltage level to a second voltage level. The control unit295switches the first power voltage Vdd from low voltage Vb to high voltage Vh. The control unit295provides the second control signal SLC2having high voltage level for turning off the pass transistor490. And the control unit295provides the first control signal SLC1having high voltage level so as to enable the voltage-control inverter460for inverting the first data signal SDx1to generate the second data signal SDx2which is furnished to the liquid crystal capacitor380. During a second still interval T22, the control unit295provides the first control signal SLC1having low voltage level and the second control signal SLC2having high voltage level for disabling the voltage-control inverter460and for turning off the pass transistor490respectively. During a third still interval T23, the control unit295provides the first control signal SLC1having low voltage level for disabling the voltage-control inverter460. And the control unit295provides the second control signal SLC2having low voltage level so as to turning on the pass transistor490for passing the second data signal SDx2to become the first data signal SDx1. During a fourth still interval T24, the control unit295provides the first control signal SLC1having low voltage level and the second control signal SLC2having high voltage level for disabling the voltage-control inverter460and for turning off the pass transistor490respectively. It is noted that the rising edge of the first control signal SLC1is not required to align the falling/rising edge of the first and second common voltages Vcom1/Vcom2.

The circuit operations during a fifth still interval T25, a sixth still interval T26, a seventh still interval T27and an eighth still interval T28are similar to the aforementioned circuit operations during the first still interval T21, the second still interval T22, the third still interval T23and the fourth still interval T24respectively, differing only in that the common voltage generation unit396switches the voltage level of the first and second common voltages Vcom1/Vcom2from the second voltage level to the first voltage level. In another embodiment, after entering the still mode, the common voltage generation unit396may provide the first and second common voltages Vcom1/Vcom2having fixed voltage level. After the eighth still interval T28, as long as the operation of the still mode continues, the liquid crystal display400performs the aforementioned circuit operations of the first through eighth still intervals T21˜T28periodically and repetitively. When the liquid crystal display400ceases the operation of the still mode, the liquid crystal display400may return to the normal mode. If the operation of the liquid crystal display400changes from the still mode to the normal mode, the control unit295switches the first power voltage Vdd from high voltage Vh to low voltage Vb, the source driver220is turned on for providing the data signal SDn having the multi-level analog voltage Vanalog, the gate driver210is turned on for providing the gate signal SGi based on the normal scanning mode, and the first and second common voltages Vcom1/Vcom2provided by the common voltage generation unit396return to the AC or DC voltages required for normal-mode operation.

FIG. 8is a schematic diagram showing a liquid crystal display500in accordance with a fourth embodiment of the present invention. The liquid crystal display500is preferable to be a transflective-mode LCD or a reflective-mode LCD. However, the liquid crystal display500may be a transmission-mode LCD. As shown inFIG. 8, the liquid crystal display500comprises a gate driver510, a source driver520, a plurality of gate lines530, a plurality of data lines540, a plurality of pixel units550, a control unit595, a common voltage generation unit596, and a power source597. In one embodiment, the pixel units550may comprise plural red pixel units, plural green pixel units and plural blue pixel units. For ease of explanation, the liquid crystal display500illustrates a gate line GLj of the gate lines530, a data line DLm of the data lines540, and a pixel unit PUd of the pixel units550. The pixel unit PUd may be a red pixel unit, a green pixel unit, or a blue pixel unit. The gate line GLj is electrically connected to the gate driver510and functions to deliver a gate signal SGj. The data line DLm is electrically connected to the source driver520and functions to deliver a data signal SDm. The control unit595comprises a signal output end for outputting a control signal SLCx, a first voltage output end for outputting a first power voltage Vdd, and a second voltage output end for outputting a second power voltage Vss. The control signal SLCx, the first power voltage Vdd and the second power voltage Vss are all furnished to each pixel unit550so that the liquid crystal display500is able to perform a still mode operation accordingly. The circuit functionalities of the common voltage generation unit596and the power source597are respectively identical to the circuit functionalities of the common voltage generation unit296and the power source297shown inFIG. 2, and for the sake of brevity, further similar discussion thereof is omitted.

The pixel unit PUd comprises a data switch555, a voltage-control inverter560, a liquid crystal capacitor580, a storage capacitor585and a pass transistor590. The data switch555provides a control of inputting the data signal SDm to become a first data signal SDy1according to the gate signal SGj. The data switch555comprises a first end electrically connected to the data line DLm for receiving the data signal SDm, a gate end electrically connected to the gate line GLj for receiving the gate signal SGj, and a second end electrically connected to the voltage-control inverter560and the pass transistor590. The data switch555can be a thin film transistor or a field effect transistor. The voltage-control inverter560is enabled by the control signal SLCx so as to invert the first data signal SDy1for generating a second data signal SDy2. The voltage-control inverter560comprises an input end electrically connected to the second end of the data switch555, an enable end561electrically connected to the signal output end of the control unit595for receiving the control signal SLCx, an output end electrically connected to the liquid crystal capacitor580, the storage capacitor585and the pass transistor590, a first power input end electrically connected to the first voltage output end of the control unit595for receiving the first power voltage Vdd, and a second power input end electrically connected to the second voltage output end of the control unit595for receiving the second power voltage Vss.

The liquid crystal capacitor580comprises a first end electrically connected to the output end of the voltage-control inverter560and a second end electrically connected to the output end of the common voltage generation unit596for receiving the common voltage Vcom. The storage capacitor585, electrically connected between the first and second ends of the liquid crystal capacitor580, is employed to assist in storing the second data signal SDy2. The pass transistor590is employed to control an electrical connection between the input and output ends of the voltage-control inverter560according to the control signal SLCx. That is, the pass transistor590is put in use for providing a control of passing the second data signal SDy2to become the first data signal SDy1or passing the first data signal SDy1to become the second data signal SDy2. The pass transistor590comprises a first end electrically connected to the output end of the voltage-control inverter560, a gate end electrically connected to the signal output end of the control unit595for receiving the control signal SLCx, and a second end electrically connected to the input end of the voltage-control inverter560. The pass transistor590can be a thin film transistor or a field effect transistor.

After the liquid crystal display500enters a still mode for displaying a still frame, each pixel unit550is able to perform a pixel data self-retaining operation by making use of the voltage-control inverter560and the pass transistor590therein. Besides, the voltage level of the second data signal SDy2can be refreshed to become the first power voltage Vdd or the second power voltage Vss through an inversion operation of the voltage-control inverter560. That is, the inversion operation of the voltage-control inverter560can also be employed to provide a data self-refreshing functionality for refreshing the second data signal SDy2. Compared with the pixel unit based on SRAM architecture in the prior-art liquid crystal display, the circuit structure of each pixel unit550in the liquid crystal display500is significantly simplified to increase the aperture ratio of each pixel unit550and also to bring the cost down. Compared with the liquid crystal display200shown inFIG. 2, only one control signal, i.e. the control signal SLCx, is required for each pixel unit550to control the operation of the voltage-control inverter560and the pass transistor590, and therefore the number of connection lines can be reduced for further increasing the aperture ratio of each pixel unit550.

FIG. 9is a schematic diagram showing a liquid crystal display600in accordance with a fifth embodiment of the present invention. As shown inFIG. 9, the circuit structure of the liquid crystal display600is similar to that of the liquid crystal display500shown inFIG. 8, differing in that the common voltage generation unit596is replaced with a common voltage generation unit696and the pixel units550are replaced with a plurality of pixel units650, wherein the pixel unit PUd is replaced with a pixel unit PUe. The pixel unit PUe may be a red pixel unit, a green pixel unit, or a blue pixel unit. The pixel unit PUe comprises the data switch555, a voltage-control inverter660, a liquid crystal capacitor680, a storage capacitor685and the pass transistor590. The voltage-control inverter660comprises a first transistor661, a second transistor662, a third transistor663and a fourth transistor664. The second transistor662and the third transistor663are put in use together for enabling/disabling the circuit output operation of the voltage-control inverter660according to the control signal SLCx. The first transistor661, the second transistor662and the third transistor663are P-type thin film transistors or P-type field effect transistors. The fourth transistor664and the pass transistor590are N-type thin film transistors or N-type field effect transistors. The common voltage generation unit696comprises a first output end for outputting a first common voltage Vcom1and a second output end for outputting a second common voltage Vcom2.

The first transistor661comprises a first end electrically connected to the first voltage output end of the control unit595for receiving the first power voltage Vdd, a gate end electrically connected to the second end of the data switch555, and a second end. The second transistor662comprises a first end electrically connected to the second end of the first transistor661, a gate end electrically connected to the signal output end of the control unit595for receiving the control signal SLCx, and a second end electrically connected to the liquid crystal capacitor680, the storage capacitor685and the first end of the pass transistor590. The third transistor663comprises a first end electrically connected to the second end of the second transistor662, a gate end electrically connected to the gate end of the second transistor662, and a second end. It is noted that the gate ends of the second transistor662and the third transistor663are functioning as an enable end of the voltage-control inverter660. The fourth transistor664comprises a first end electrically connected to the second end of the third transistor663, a gate end electrically connected to the gate end of the first transistor661, and a second end electrically connected to the second voltage output end of the control unit595for receiving the second power voltage Vss. The liquid crystal capacitor680comprises a first end electrically connected to the second end of the second transistor662and a second end electrically connected to the first output end of the common voltage generation unit696for receiving the first common voltage Vcom1. The storage capacitor685comprises a first end electrically connected to the first end of the liquid crystal capacitor680and a second end electrically connected to the second output end of the common voltage generation unit696for receiving the second common voltage Vcom2. The storage capacitor685is employed to assist in storing the second data signal SDy2.

FIG. 10is a schematic diagram showing a liquid crystal display700in accordance with a sixth embodiment of the present invention. As shown inFIG. 10, the circuit structure of the liquid crystal display700is similar to that of the liquid crystal display600shown inFIG. 9, differing in that the pixel units650are replaced with a plurality of pixel units750, wherein the pixel unit PUe is replaced with a pixel unit PUf. The pixel unit PUf may be a red pixel unit, a green pixel unit, or a blue pixel unit. The pixel unit PUf comprises the data switch555, a voltage-control inverter760, the liquid crystal capacitor680, the storage capacitor685and a pass transistor790. The voltage-control inverter760comprises a first transistor761, a second transistor762, a third transistor763and a fourth transistor764. The second transistor762and the third transistor763are put in use together for enabling/disabling the circuit output operation of the voltage-control inverter760according to the control signal SLCx. The first transistor761and the pass transistor790are P-type thin film transistors or P-type field effect transistors. The second transistor762, the third transistor763and the fourth transistor764are N-type thin film transistors or N-type field effect transistors. The pass transistor790comprises a first end electrically connected to the first end of the liquid crystal capacitor680, a gate end electrically connected to the signal output end of the control unit595for receiving the control signal SLCx, and a second end electrically connected to the second end of the data switch555.

The first transistor761comprises a first end electrically connected to the first voltage output end of the control unit595for receiving the first power voltage Vdd, a gate end electrically connected to the second end of the data switch555, and a second end. The second transistor762comprises a first end electrically connected to the second end of the first transistor761, a gate end electrically connected to the signal output end of the control unit595for receiving the control signal SLCx, and a second end electrically connected to the liquid crystal capacitor680, the storage capacitor685and the first end of the pass transistor790. The third transistor763comprises a first end electrically connected to the second end of the second transistor762, a gate end electrically connected to the gate end of the second transistor762, and a second end. It is noted that the gate ends of the second transistor762and the third transistor763are functioning as an enable end of the voltage-control inverter760. The fourth transistor764comprises a first end electrically connected to the second end of the third transistor763, a gate end electrically connected to the gate end of the first transistor761, and a second end electrically connected to the second voltage output end of the control unit595for receiving the second power voltage Vss.

FIG. 11is a schematic diagram showing related signal waveforms regarding the first circuit operation case of the liquid crystal display500shown inFIG. 8, having time along the abscissa. The signal waveforms inFIG. 11, from top to bottom, are the gate signal SGj, the data signal SDm, the common voltage Vcom, the control signal SLCx, the first power voltage Vdd, and the second power voltage Vss. When the liquid crystal display500is working in a normal mode, the data signal SDm provided by the source driver520is a multi-level analog voltage Vanalog, the gate driver510provides the gate signal SGj based on a normal scanning mode, the data switch555inputs the data signal SDm to become the first data signal SDy1according to the gate signal SGj under the normal scanning mode, the common voltage Vcom provided by the common voltage generation unit596is an AC voltage or a DC voltage required for normal-mode operation, the control unit595provides the control signal SLCx having high voltage level for disabling the voltage-control inverter560and for turning on the pass transistor590so as to pass the first data signal SDy1to become the second data signal SDy2, and both the first power voltage Vdd and the second power voltage Vss generated by the control unit595are low voltage Vb.

After the liquid crystal display500enters a still mode for displaying a still frame, during a preliminary interval Tpre3, the data signal SDm provided by the source driver520is a bi-level digital voltage Vdigital, the data switch555inputs the bi-level digital voltage Vdigital to become the first data signal SDy1according to the gate signal SGj under the normal scanning mode, the common voltage generation unit596provides the common voltage Vcom having a first voltage level, the control unit595provides the control signal SLCx having high voltage level for continuously disabling the voltage-control inverter560and for continuously turning on the pass transistor590so as to continue passing the first data signal SDy1to become the second data signal SDy2, and both the first power voltage Vdd and the second power voltage Vss generated by the control unit595hold low voltage Vb. Besides, the gate driver510is turned off after the data switch555inputs the bi-level digital voltage Vdigital to become the first data signal SDy1. Further, the source driver520is turned off after the gate driver510is turned off and thus the data signal SDm becomes a floating voltage.

During a first still interval T31, the common voltage generation unit596switches the voltage level of the common voltage Vcom from the first voltage level to a second voltage level. The control unit595switches the first power voltage Vdd from low voltage Vb to high voltage Vh. The control unit595provides the control signal SLCx having low voltage level for turning off the pass transistor590and for enabling the voltage-control inverter560. And the voltage-control inverter560enabled then inverts the first data signal SDy1for generating the second data signal SDy2furnished to the liquid crystal capacitor580. During a second still interval T32, the control unit595provides the control signal SLCx having high voltage level for disabling the voltage-control inverter560and for turning on the pass transistor590. And the pass transistor590turned on is then utilized for passing the second data signal SDy2to become the first data signal SDy1. It is noted that the falling edge of the control signal SLCx is not required to align the falling/rising edge of the common voltage Vcom.

The circuit operations during a third still interval T33and a fourth still interval T34are similar to the aforementioned circuit operations during the first still interval T31and the second still interval T32respectively, differing only in that the common voltage generation unit596switches the voltage level of the common voltage Vcom from the second voltage level to the first voltage level. In another embodiment, after entering the still mode, the common voltage generation unit596may provide the common voltage Vcom having fixed voltage level. After the fourth still interval T34, as long as the operation of the still mode continues, the liquid crystal display500performs the aforementioned circuit operations of the first through fourth still intervals T31˜T34periodically and repetitively. When the liquid crystal display500ceases the operation of the still mode, the liquid crystal display500may return to the normal mode. If the operation of the liquid crystal display500changes from the still mode to the normal mode, the control unit595switches the first power voltage Vdd from high voltage Vh to low voltage Vb, the source driver520is turned on for providing the data signal SDm having the multi-level analog voltage Vanalog, the gate driver510is turned on for providing the gate signal SGj based on the normal scanning mode, and the common voltage Vcom provided by the common voltage generation unit596returns to the AC or DC voltage required for normal-mode operation. If the common voltage Vcom inFIG. 11is replaced with the first and second common voltages Vcom1/Vcom2, the signal waveforms illustrated inFIG. 11can be applied to make clear the operation of the liquid crystal display600shown inFIG. 9.

FIG. 12is a schematic diagram showing related signal waveforms regarding a second circuit operation case of the liquid crystal display500shown inFIG. 8, having time along the abscissa. The signal waveforms inFIG. 12, from top to bottom, are the gate signal SGj, the data signal SDm, the common voltage Vcom, the control signal SLCx, the first power voltage Vdd, and the second power voltage Vss. When the liquid crystal display500is working in a normal mode or during a preliminary interval Tpre9under a still mode, the signal waveforms shown inFIG. 12are identical to the signal waveforms of the first circuit operation case illustrated inFIG. 11, and for the sake of brevity, further similar discussion thereof is omitted.

During a first still interval T91under the still mode, the common voltage generation unit596switches the voltage level of the common voltage Vcom from the first voltage level to the second voltage level. The control unit595switches the first power voltage Vdd from low voltage Vb to high voltage Vh. The control unit595provides the control signal SLCx having low voltage level for turning off the pass transistor590and for enabling the voltage-control inverter560. And the voltage-control inverter560enabled then inverts the first data signal SDy1for generating the second data signal SDy2furnished to the liquid crystal capacitor580.

During a second still interval T92under the still mode, the control unit595provides the control signal SLCx having high voltage level for disabling the voltage-control inverter560and for turning on the pass transistor590. And the pass transistor590turned on is then utilized for passing the second data signal SDy2to become the first data signal SDy1. It is noted that the falling/rising edge of the control signal SLCx is not required to align the falling/rising edge of the common voltage Vcom. Besides, the rising edge of the first power voltage Vdd is required only to occur before the first falling edge of the control signal SLCx after entering the still mode, i.e. the rising edge of the first power voltage Vdd is not required to align the falling edge of the control signal SLCx.

The circuit operations during a third still interval T93and a fourth still interval T94are similar to the aforementioned circuit operations during the first still interval T91and the second still interval T92respectively, differing only in that the common voltage generation unit596switches the voltage level of the common voltage Vcom from the second voltage level to the first voltage level during the third still interval T93. In another embodiment, after entering the still mode, the common voltage generation unit596may provide the common voltage Vcom having fixed voltage level. After the fourth still interval T94, as long as the operation of the still mode continues, the liquid crystal display500performs the aforementioned circuit operations of the first through fourth still intervals T91˜T94periodically and repetitively. When the liquid crystal display500ceases the operation of the still mode, the operation of the liquid crystal display500may change from the still mode to the normal mode, and the corresponding signal waveforms thereof shown inFIG. 12are identical to those of the first circuit operation case illustrated inFIG. 11. Similarly, if the common voltage Vcom inFIG. 12is replaced with the first and second common voltages Vcom1/Vcom2, the signal waveforms illustrated inFIG. 12can be applied to make clear the operation of the liquid crystal display600shown inFIG. 9.

FIG. 13is a schematic diagram showing related signal waveforms regarding the circuit operation of the liquid crystal display700shown inFIG. 10, having time along the abscissa. The signal waveforms inFIG. 13, from top to bottom, are the gate signal SGj, the data signal SDm, the first and second common voltages Vcom1/Vcom2, the control signal SLCx, the first power voltage Vdd, and the second power voltage Vss. When the liquid crystal display700is working in a normal mode, the data signal SDm provided by the source driver520is a multi-level analog voltage Vanalog, the gate driver510provides the gate signal SGj based on a normal scanning mode, the data switch555inputs the data signal SDm to become the first data signal SDy1according to the gate signal SGj under the normal scanning mode, the first and second common voltages Vcom1/Vcom2provided by the common voltage generation unit696are AC or DC voltages required for normal-mode operation, the control unit595provides the control signal SLCx having low voltage level for disabling the voltage-control inverter760and for turning on the pass transistor790so as to pass the first data signal SDy1to become the second data signal SDy2, and both the first power voltage Vdd and the second power voltage Vss generated by the control unit595are low voltage Vb.

After the liquid crystal display700enters a still mode for displaying a still frame, during a preliminary interval Tpre4, the data signal SDm provided by the source driver520is a bi-level digital voltage Vdigital, the data switch555inputs the bi-level digital voltage Vdigital to become the first data signal SDy1according to the gate signal SGj under the normal scanning mode, the common voltage generation unit696provides the first and second common voltages Vcom1/Vcom2having a first voltage level, the control unit595provides the control signal SLCx having low voltage level for continuously disabling the voltage-control inverter760and for continuously turning on the pass transistor790so as to continue passing the first data signal SDy1to become the second data signal SDy2, and both the first power voltage Vdd and the second power voltage Vss generated by the control unit595hold low voltage Vb. Besides, the gate driver510is turned off after the data switch555inputs the bi-level digital voltage Vdigital to become the first data signal SDy1. Further, the source driver520is turned off after the gate driver510is turned off and thus the data signal SDm becomes a floating voltage.

During a first still interval T41, the common voltage generation unit696switches the voltage level of the first and second common voltages Vcom1/Vcom2from the first voltage level to a second voltage level. The control unit595switches the first power voltage Vdd from low voltage Vb to high voltage Vh. The control unit595provides the control signal SLCx having high voltage level for turning off the pass transistor790and for enabling the voltage-control inverter760. And the voltage-control inverter760enabled then inverts the first data signal SDy1for generating the second data signal SDy2furnished to the liquid crystal capacitor680. During a second still interval T42, the control unit595provides the control signal SLCx having low voltage level for disabling the voltage-control inverter760and for turning on the pass transistor790. And the pass transistor790turned on is then utilized for passing the second data signal SDy2to become the first data signal SDy1. It is noted that the rising edge of the control signal SLCx is not required to align the falling/rising edge of the first and second common voltages Vcom1/Vcom2.

The circuit operations during a third still interval T43and a fourth still interval T44are similar to the aforementioned circuit operations during the first still interval T41and the second still interval T42respectively, differing only in that the common voltage generation unit696switches the voltage level of the first and second common voltages Vcom1/Vcom2from the second voltage level to the first voltage level. In another embodiment, after entering the still mode, the common voltage generation unit696may provide the first and second common voltages Vcom1/Vcom2having fixed voltage level. After the fourth still interval T44, as long as the operation of the still mode continues, the liquid crystal display700performs the aforementioned circuit operations of the first through fourth still intervals T41˜T44periodically and repetitively. When the liquid crystal display700ceases the operation of the still mode, the liquid crystal display700may return to the normal mode. If the operation of the liquid crystal display700changes from the still mode to the normal mode, the control unit595switches the first power voltage Vdd from high voltage Vh to low voltage Vb, the source driver520is turned on for providing the data signal SDm having the multi-level analog voltage Vanalog, the gate driver510is turned on for providing the gate signal SGj based on the normal scanning mode, and the first and second common voltages Vcom1/Vcom2provided by the common voltage generation unit696return to the AC or DC voltages required for normal-mode operation.

FIG. 14is a flowchart depicting an operation method according to the present invention. The operation method regarding the flow800shown inFIG. 14is implemented based on the liquid crystal display200shown inFIG. 2. The operation method illustrated in the flow800comprises the following steps:

Step S805: The control unit provides the first control signal for disabling the voltage-control inverter.

Step S810: The control unit provides the second control signal for turning on the pass transistor so as to pass the first data signal to become the second data signal furnished to the liquid crystal capacitor.

Step S815: The source driver converts the voltage level of the data signal from multi-level analog mode into bi-level digital mode.

Step S820: The data switch inputs the data signal with bi-level digital mode to become the first data signal and the second data signal according to the gate signal under scanning mode.

Step S825: The common voltage generation unit provides the common voltage having the first voltage level.

Step S830: Turn off the gate driver after the data switch inputs the data signal with bi-level digital mode to become the first data signal.

Step S835: Turn off the source driver after the gate driver is turned off.

Step S840: The control unit switches the first power voltage from low voltage to high voltage.

Step S845: The control unit provides the second control signal for turning off the pass transistor.

Step S850: The control unit provides the first control signal so as to enable the voltage-control inverter for inverting the first data signal to generate the second data signal which is furnished to the liquid crystal capacitor.

Step S855: The common voltage generation unit switches the voltage level of the common voltage from the first voltage level to the second voltage level.

Step S860: The control unit provides the first control signal for disabling the voltage-control inverter.

Step S865: The control unit provides the second control signal for turning on the pass transistor so as to pass the second data signal to become the first data signal.

Step S870: The control unit provides the second control signal for turning off the pass transistor.

Step S875: The control unit provides the first control signal so as to enable the voltage-control inverter for inverting the first data signal to generate the second data signal which is furnished to the liquid crystal capacitor.

Step S880: The common voltage generation unit switches the voltage level of the common voltage from the second voltage level to the first voltage level.

Step S885: The control unit provides the first control signal for disabling the voltage-control inverter.

Step S890: The control unit provides the second control signal for turning on the pass transistor so as to pass the second data signal to become the first data signal.

Step S895: The control unit provides the second control signal for turning off the pass transistor. Go to step S850.

In another embodiment, the aforementioned voltage level of the common voltage in the flow800is a fixed voltage level, i.e. the second voltage level equals the first voltage level. Besides, if the common voltage is replaced with the first and second common voltages in the flow800, the operation method disclosed in the flow800can be applied to both the liquid crystal display300inFIG. 3and the liquid crystal display400inFIG. 4. It is noted that if the control unit provides the first control signal having high voltage level for disabling the voltage-control inverter, the control unit provides the first control signal having low voltage level for enabling the voltage-control inverter, and vice versa. Similarly, if the control unit provides the second control signal having high voltage level for turning on the pass transistor, the control unit provides the second control signal having low voltage level for turning off the pass transistor, and vice versa.

FIG. 15is a flowchart depicting another operation method according to the present invention. The operation method regarding the flow900shown inFIG. 15is implemented based on the liquid crystal display500shown inFIG. 8. The operation method illustrated in the flow900comprises the following steps:

Step S905: The control unit provides the control signal for disabling the voltage-control inverter and for turning on the pass transistor so as to pass the first data signal to become the second data signal furnished to the liquid crystal capacitor.

Step S910: The source driver converts the voltage level of the data signal from multi-level analog mode into bi-level digital mode.

Step S915: The data switch inputs the data signal with bi-level digital mode to become the first data signal and the second data signal according to the gate signal under scanning mode.

Step S920: The common voltage generation unit provides the common voltage having the first voltage level.

Step S925: Turn off the gate driver after the data switch inputs the data signal with bi-level digital mode to become the first data signal.

Step S930: Turn off the source driver after the gate driver is turned off.

Step S935: The control unit switches the first power voltage from low voltage to high voltage.

Step S940: The control unit provides the control signal for turning off the pass transistor and for enabling the voltage-control inverter to invert the first data signal for generating the second data signal furnished to the liquid crystal capacitor.

Step S945: The common voltage generation unit switches the voltage level of the common voltage from the first voltage level to the second voltage level.

Step S950: The control unit provides the control signal for disabling the voltage-control inverter and for turning on the pass transistor so as to pass the second data signal to become the first data signal.

Step S955: The control unit provides the control signal for turning off the pass transistor and for enabling the voltage-control inverter to invert the first data signal for generating the second data signal furnished to the liquid crystal capacitor.

Step S960: The common voltage generation unit switches the voltage level of the common voltage from the second voltage level to the first voltage level.

Step S965: The control unit provides the control signal for disabling the voltage-control inverter and for turning on the pass transistor so as to pass the second data signal to become the first data signal. Go to step S940.

In another embodiment, the aforementioned voltage level of the common voltage in the flow900is a fixed voltage level, i.e. the second voltage level equals the first voltage level. Besides, if the common voltage is replaced with the first and second common voltages in the flow900, the operation method disclosed in the flow900can be applied to both the liquid crystal display600inFIG. 9and the liquid crystal display700inFIG. 10. It is noted that if the control unit provides the control signal having high voltage level for disabling the voltage-control inverter and for turning on the pass transistor, the control unit provides the control signal having low voltage level for enabling the voltage-control inverter and for turning off the pass transistor, and vice versa.

In conclusion, the liquid crystal display of the present invention provides the pixel data self-retaining functionality based on simplified pixel circuit structure for reducing the power consumption of displaying a still frame and also for performing a data self-refreshing operation. Accordingly, compared with the prior-art liquid crystal display having pixel units based on SRAM architecture, the circuit structure of the pixel units in the liquid crystal display of the present invention is significantly simplified to increase the aperture ratio of each pixel unit and also to bring the cost down.

The present invention is by no means limited to the embodiments as described above by referring to the accompanying drawings, which may be modified and altered in a variety of different ways without departing from the scope of the present invention. Thus, it should be understood by those skilled in the art that various modifications, combinations, sub-combinations and alternations might occur depending on design requirements and other factors insofar as they are within the scope of the appended claims or the equivalents thereof.