Method and system for transmitting/receiving serial data in serial communication system and serial communication system for the same

A method and a system for transmitting/receiving serial data efficiently by minimizing the transitions of bits in a serial communication system, as well as a serial communication system for the same, are provided. The method for converting coded parallel data into serial data and transmitting the serial data in a serial communication system includes determining a position, in which an information bit of the coded parallel data is found first, the information bit being defined as a bit having a predetermined bit value so that the information bit is not compressed; and serially transmitting the information bit found first and at least one bit following the information bit found first as compressed serial data until the determined position is reached.

PRIORITY

This application claims priority to an application entitled “Method and System for Transmitting/Receiving Serial Data in Serial Communication System and Serial Communication System for the Same” filed with the Korean Intellectual Property Office on Jan. 29, 2007 and assigned Serial No. 2007-008889, the contents of which are incorporated herein by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a method for transmitting/receiving serial data in a serial communication system, as well as a serial communication system for the same. More particularly, the present invention relates to a method and a system for transmitting/receiving serial data efficiently by minimizing the transitions of bits in a serial communication system, as well as a serial communication system for the same.

2. Description of the Related Art

As generally known in the art, conventional on-chip or off-chip parallel communication systems require a large number of wires, which result in problems including crosstalk between wires, skew, etc. Therefore, off-chip serial communication systems (e.g. Ethernet, USB (Universal Serial Bus), IEEE 1394, PCI-EXPRESS, etc.) are used for wired communication between electric products, Internet communication between computers, communication between functional blocks inside chips, etc. Even in the case of on-chip communication systems, which have adopted only the parallel bus scheme, on-chip serial communication systems are being studied to solve not only the above-mentioned problems of crosstalk between wires and skew, but also the wiring congestion of parallel wires. Such an on-chip serial communication scheme has been adopted for a multifunction, high-performance multicore SoC (System-on-Chip), such as an NoC (Network-on-Chip).

FIG. 1is a block diagram showing an apparatus for transmitting/receiving serial data according to the prior art.

The conventional serial communication system includes a transmitter110for converting input N-bit parallel data101into serial data105and transmitting it, and a receiver150for receiving the serial data from the transmitter110and converting it into N-bit parallel data109.

The transmitter110successively converts N-bit parallel data101, which is stored in a first signal processor111of a FIFO (First In First Out) type, into serial data105through a serial converter115, and loads the serial data105onto a serial transmission wire130. The MSB (Most Significant Bit) of the serial data105is generally transmitted first.

The receiver150converts the successively inputted serial data105into parallel data through a parallel converter151, stores the parallel data in a second signal processor155, and outputs N-bit parallel data109.

The first and second signal processors111and155according to the prior art shown inFIG. 1may be omitted, and a coder113and a decoder153may be added if a separate coding scheme is adopted.

Coding schemes applicable to the coder113and the decoder153shown inFIG. 1will now be described.

When clocks are extracted from data without separate clock signals, such as in the case of Ethernet (IEEE 802.3), DC-balanced codes (e.g. 8 B/10 B codes) are used. Particularly, according to the DC-balanced coding scheme, transitions are so created in the serial transmission wire130that less than five consecutive symbols (0 or 1) should occur. This makes it easier to extract clocks from the serial transmission wire130.

However, the DC-balanced coding scheme increases the transmitting/receiving power due to the increased number of transitions in the serial transmission wire130. In addition, 25% overhead occurs because, in order to transmit effective data of 8 bits 10 bits are actually transmitted. The DC-balanced coding scheme is even unnecessary if separate clock signals are used or if the transmitter110and the receiver150are synchronized as in the case of on-chip communication systems.

There are analog and digital methods for minimizing the transmitting/receiving power when the transmitter110and the receiver150are synchronized. The analog method includes a low-swing signaling scheme, according to which the signal level is lowered. The digital method includes a scheme (e.g. SILENT coding scheme), according to which the bit transitions on the serial transmission wire130are minimized.

The SILENT coding scheme, which has been studied as one of the conventional digital methods, applies XOR (Exclusive OR) codes to the serial transmission scheme, as disclosed in “SILENT: Serialized Low Energy Transition Coding for On-Chip Interconnection Networks”, Kangmin Lee, et al., IEEE ICCAD 2004, pp. 448-451.

The scheme will now be described with reference toFIG. 1on an assumption that N-bit parallel data is 8-bit data.

The first signal processor111shown inFIG. 2is a buffer of an FIFO type, and transmits successively inputted parallel data W0-W3to the coder113. The coder113adopts a SILENT coding scheme, which applies XOR codes to a serial transmission scheme, and creates data W′0-W′3201that has been coded successively in such a manner that, if a currently transmitted data bit is identical to a previously transmitted data bit, 0 is used, and, if they are different, 1 is used. The serial converter115serializes the created data203, and loads the SILENT-coded serial data205onto the serial transmission wire130as shown inFIG. 2A.

It is clear fromFIG. 2that, as a result of applying the SILENT coding scheme, there are 6 bit transitions in the SILENT-coded serial data205as shown inFIG. 2A, but there are 17 bit transitions in the original serial data207to which the SILENT coding has not been applied. The reason the number of bit transitions is reduced by the SILENT coding is that there exists locality between the consecutive parallel data.

However, when such SILENT coding is applied to a serial communication system, the power is reduced efficiently compared with conventional methods applying no coding, while the bit rate has no gain. In other words, even if the SILENT coding is applied to a serial communication system for conversion into serial data, neither the bit rate nor the bandwidth can be increased during serial data transmission.

In addition, serial transmission schemes adopted by serial communication systems employ a small number of transmission wires and, therefore, have a much smaller bandwidth than parallel transmission schemes which employ many transmission wires to transmit a number of bits simultaneously. In an attempt to solve the problem of small transmission bandwidth, the bit rate is increased by a number of times. This results in difficulty in high-speed design, as well as problems related to the area and power resulting from high-speed circuits.

Therefore, there is a need for a scheme capable of increasing the available bandwidth by compressing SILENT-coded data so that the transitions of bits in serial communication systems can be minimized.

SUMMARY OF THE INVENTION

Accordingly, the present invention has been made to solve the above-mentioned problems occurring in the prior art, and it is an aspect of the present invention to provide a method and a system for transmitting/receiving serial data efficiently by minimizing the transitions of bits in a serial communication system, as well as a serial communication system for the same.

It is another aspect of the present invention to provide a method and a system for transmitting/receiving serial data in a serial communication system by compressing coded data so that the available bandwidth increases, as well as a serial communication system for the same.

In order to accomplish these aspects of the present invention, there is provided a method for converting coded parallel data into serial data and transmitting the serial data in a serial communication system, the method including determining a position, an information bit of the coded parallel data being found first in the position, the information bit being defined as a bit having a predetermined bit value so that the information bit is not compressed; and serially transmitting the information bit found first and at least one bit following the information bit found first as compressed serial data until the determined position is reached.

In accordance with another aspect of the present invention, there is provided a method for converting serial data into coded parallel data and receiving the coded parallel data in a serial communication system, the method including receiving each bit of compressed serial data until a signal indicating an end of the compressed serial data is inputted; and outputting the coded parallel data including each received data and at least one bit following each received data, the bit having a predetermined bit value.

In accordance with a further aspect of the present invention, there is provided an apparatus for converting coded parallel data into serial data and transmitting the serial data in a serial communication system, the apparatus including a compressor for outputting a count while increasing the count until a position is reached, an information bit of the coded parallel data being found first in the position, the information bit being defined as a bit having a predetermined bit value so that the information bit is not compressed, the compressor transmitting a signal indicating an end of compressed serial data when the position is reached; and a serial converter for serially transmitting a bit of the coded parallel data as the compressed serial data, the bit corresponding to a position indicated by the outputted count.

In accordance with a still further aspect of the present invention, there is provided an apparatus for converting serial data into coded parallel data and receiving the coded parallel data in a serial communication system, the apparatus including a decompressor for outputting a count while increasing the count until a signal indicating an end of compressed serial data is inputted; and a parallel converter having a plurality of latches pre-storing predetermined bit values, the parallel converter receiving each bit of the compressed serial data and storing a bit corresponding to the outputted count in a corresponding latch, the parallel converter outputting bits stored in the latches as the coded parallel data when a signal indicating an end of the compressed serial data is inputted.

In accordance with a yet further aspect of the present invention, there is provided a serial communication system for converting coded parallel data into serial data and transmitting/receiving the serial data, the system including a serial data transmitting apparatus for outputting a first count while increasing the first count until a position is reached, an information bit of the coded parallel data being found first in the position, the information bit being defined as a bit having a predetermined bit value so that the information bit is not compressed, the serial data transmitting apparatus transmitting a signal indicating an end of compressed serial data when the position is reached, the serial data transmitting apparatus serially transmitting a bit of the coded parallel data as the compressed serial data, the bit corresponding to a position indicated by the outputted first count; and a serial data receiving apparatus for outputting a second count while increasing the second count until a signal indicating an end of the compressed serial data is inputted, the serial data receiving apparatus having a plurality of latches having predetermined bit values, the serial data receiving apparatus receiving each bit of the compressed serial data and storing a bit corresponding to the second count in a corresponding latch, the serial data receiving apparatus outputting bits stored in the latches as the coded parallel data when a signal indicating an end of the compressed serial data is inputted.

DETAILED DESCRIPTION OF THE EXEMPLARY EMBODIMENTS

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. In the following description of the present invention, a detailed description of known functions and configurations incorporated herein is omitted to avoid making the subject matter of the present invention unclear. The terminology used herein is defined based on consideration of relevant functionality according to the present invention, and may vary depending on the intention or practice of the user or operator. Therefore, the definition must be understood based on the overall context of the specification.

The basic concept of the present invention will now be described. According to the present invention, coded parallel data is converted into compressed serial data in such a manner that, if a bit of the coded parallel data has no difference from the corresponding bit of previously transmitted data, the bit (“an identical bit”,) is removed. In other words, identical bits are removed from parallel data, which is compressed and converted into serial data so that the amount of data to be transmitted/received is reduced. This shortens the time necessary to transmit/receive the serial data and improves the available bandwidth of the actual transmission wire.

In order to compress bits which have no difference from previously transmitted parallel data, the coding scheme and bits not to be compressed must be determined during the initial setting of the serial communication system.

An embodiment of the present invention will now be described on an assumption that, during the initial setting of a serial communication system, SILENT coding is applied to a coder and a decoder and that, ‘0’ bits of the SILENT-coded parallel data are bits to be compressed, while ‘1’ bits are bits not to be compressed ( “information bits”).

FIG. 3is a block diagram showing an apparatus for transmitting/receiving compressed serial data according to an embodiment of the present invention.

Referring toFIG. 3, the serial communication system includes a transmitter310for applying a SILENT coding scheme to inputted N-bit parallel data301to convert it into compressed serial305, and a receiver350for receiving the compressed serial data305, decomposing it, and applying a SILENT decoding scheme to it so that it is decoded into initially inputted N-bit parallel data309.

The transmitter310includes a first signal processor311, a coder313, a serial converter315and a compressor317. The receiver350includes a parallel converter351, a decoder353, a second signal processor355and a decompressor357.

The first and second signal processors311and355, as well as the coder313and the decoder353of the transmitter310and the receiver350, respectively, are operated in the same manner as in the case of the prior art, and detailed description thereof will be omitted herein.

The compressor317of the transmitter310shown inFIG. 3receives coded parallel data from the coder313as an input and outputs a serial conversion control signal C1and a signal303for indicating the end of the compressed serial data305( “end_of_word”,). The end_of_word303includes [HIGH] and [LOW] signals. It will be assumed in the following description that, if the end_of_word303is a [HIGH] signal, it indicates the end of the compressed serial data305. The compressor317will be described later in more detail with reference toFIG. 4.

The serial converter315converts the coded parallel data into the serial data305by using the serial conversion control signal C1. The serial converter315may be implemented as shown inFIG. 5by using a multistage multiplexer.

The decompressor357of the receiver350outputs a parallel conversion control signal C2by using the input of the end_of_word303. The decompressor357may be implemented as shown inFIG. 6by using a first counter601, and will be described later in more detail with reference toFIG. 6.

The parallel converter351converts the transmitted and compressed serial data305into coded parallel data by using the parallel conversion control signal C2, and may be implemented as shown inFIG. 7by using a demultiplexer701and a plurality of latches703.

FIG. 4is a block diagram showing in detail the compressor317shown inFIG. 3.

The compressor317, according to an embodiment of the present invention, is implemented by a logic circuit, and includes an encoder401, a first counter403and a comparator405.

The encoder401shown inFIG. 4receives coded parallel data307as an input and scans each bit to determine the position in which the first information bit ‘1’ is found. The scanning of each bit by the encoder401to find the information bit starts from either the Most Significant Bit (MSB) or the Least Significant Bit (LSB). However, it is to be noted that, when multimedia contents or digital signals are processed, upper bits do not undergo rapid transitions very often, and that, since the addresses increase one after another during memory processing, the transition between previously transmitted data and currently transmitted data mainly occurs in lower bits. This means that upper bits need to be compressed more frequently. Therefore, it will be assumed in the following description that the scanning starts from the MSB. For example, when 8-bit coded parallel data307inputted to the encoder401is [00000100], the encoder401starts the scanning from the MSB and finds the first information bit ‘1’ in the position of the 2ndpit (the counting begins from the 0thbit). Therefore, [010] is outputted as the position of the first bit.

The first counter403of the compressor317outputs a count, which increases from 0 by 1, to the comparator405and as the serial conversion control signal C1. It will be assumed that, unless otherwise indicated, the count is outputted by the first counter403.

When the first counter403receives a [HIGH] signal from the comparator405, it resets the count. For example, if the count increases from [000] to [010] by 1 and if the first counter403receives a [HIGH] signal from the comparator405, the first counter403outputs [000→001→010→reset] to the comparator405and as serial conversion control signal C1.

If the position of the first information bit found is identical to the count inputted from the first counter403, the comparator405transmits a [HIGH] signal (1 bit) to the first counter403, and transmits a clock having a [HIGH] signal to the end_of_word303. For example, if the position of the first information bit found is [010] and if the count inputted from the first counter403is [010], the comparator405transmits a [HIGH] signal to the first counter403, and transmits a clock having a [HIGH] clock to the end_of_word303. On the other hand, if the position of the first information bit found is different from the count input from the first counter403, the comparator405outputs a [LOW] signal to the end_of_word303.

FIG. 5is a block diagram showing in detail the serial converter included in the transmitter310shown inFIG. 3.

Referring toFIG. 5, the serial converter315may be implemented by using a plurality of multiplexers depending on the number of bits of the coded parallel data307. The serial converter315receives coded parallel data307from the coder313and outputs a bit, which corresponds to the position indicated by the count, based on the serial conversion control signal C1outputted by the first counter403. For example, if data inputted to the serial converter315is [00000100] and if the serial conversion control signal C1outputted by the first counter403while increasing by 1 is [000], the serial converter315outputs the 0thbit of the serial data305, i.e. [0]. If the serial conversion control signal C1is [010], the serial converter315outputs the 1stdata of the serial data305, i.e. [0]. If the serial conversion control signal C1is [010], the serial converter315outputs the 2ndbit of the serial data305, i.e. [1].

FIG. 6is a block diagram showing in detail the decompressor included in the receiver shown inFIG. 3.

Referring toFIG. 6, when compressed serial data305is inputted to the receiver350, the second counter601of the decompressor357outputs a parallel conversion control signal C2, which increases from 0 by 1. Upon receiving a [HIGH] signal as the end_of_word303, the second counter601does not increase the count but resets it. This means that the second counter601conducts the same operation as the first counter403of the compressor317. For example, if the count increases from [000] to [010] by 1 and if a [HIGH] signal is inputted as the end_of_word303, the second counter601outputs [000→001→010→reset] as the parallel conversion control signal C2.

FIG. 7is a block diagram showing in detail the parallel converter included in the receiver shown inFIG. 3.

Referring toFIG. 7, the parallel converter351includes a demultiplexer701and a plurality of latches703. The demultiplexer701of the parallel converter351receives compressed serial data305from the transmitter110and outputs respective bits to corresponding latches based on the parallel conversion control signal C2. Assuming that the compressed serial data305inputted to the demultiplexer701is [00000100], if the parallel conversion control signal C2is [000], the 0thbit of the compressed serial data305, i.e. [0], is outputted to the latch0; if the parallel conversion control signal C2is [001], the 1stbit of the compressed serial data305, i.e. [0], is outputted to the latch1; and, if the parallel conversion control signal C2is [010], the 2ndbit of the compressed serial data305, i.e. [1], is outputted to the latch2.

The number of the latches703is the same as that of bits outputted by the demultiplexer701so that the latches703are reset by the initial end_of_word303before respective bits are inputted. Respective bits outputted by the demultiplexer701are stored in the corresponding latches703. If no bit is outputted to one of the latches703according to the parallel conversion control signal C2, the corresponding latch stores [0] as the initial reset. For example, if [0] is outputted to the latch0as the 0thbit of the compressed serial data305, [0] is stored in the latch0; if [0] is outputted to the latch1as the 1stbit of the compressed serial data305, [0] is stored in the latch1; and, if [1] is outputted to the latch2as the 2ndbit of the compressed serial data305, [1] is stored in the latch2. If no bits are outputted to the latches3-7, they store [0] as the initial reset. Meanwhile, if ‘1’ and ‘0’ bits of the coded parallel data have been set as the compression and information bits, respectively, during the initial setting of the serial communication system, [1] must be set as the initial reset.

As such, the parallel converter351including a demultiplexer701and a plurality of latches703converts compressed serial data305into N-bit coded parallel data307.

FIG. 8is a flowchart showing a process for transmitting compressed serial data according to an embodiment of the present invention.

Referring toFIG. 8, when the transmitter310receives parallel data in step801, the coder313of the transmitter310subjects respective bits of the previous parallel data and the inputted parallel data to SILENT coding in step803. Then, in step805, the encoder401of the compressor317receives the coded parallel data307, scans respective bits, and determines the position in which the first information bit ‘1’ is found.

In step807, the serial converter315outputs a bit of the coded parallel data307, which corresponds to the position indicated by the count, based on the serial conversion control signal C1corresponding to the count. In step807, in the initial case of the serial communication system, the serial converter315outputs a bit corresponding to the position indicated by the initial count value 0.

The comparator405confirms in step809if the inputted count is identical to the position of the first information bit found. If it is confirmed in step809that the inputted count is identical to the position of the first information bit found, the comparator405proceeds to step813; and, if they are different, it proceeds to step811. In step811, the first counter403increases the count by 1 and transmits the increased count to the serial converter315in step807.

If the count is identical to the position of the first information bit found, the comparator405inputs a [HIGH] signal to the first counter403in step813so that the first counter403resets the count. The resetting prevents further transmission of coded data. The comparator405outputs a [HIGH] signal as the end_of_word303in step815. Then, the transmitter310finishes transmitting compressed serial data305in step817.

FIG. 9shows a process for transmitting compressed serial data by a transmitting apparatus according to an embodiment of the present invention.

Based on an assumption that 8-bit parallel data [01010011] is inputted to the transmitter310and that the coder313outputs SILENT-coded parallel data [00000100], a process for converting the coded parallel data [00000100] into compressed serial data [100] and transmitting it by the transmitter310according to an embodiment of the present invention will now be described.

Referring toFIG. 9, the encoder401of the compressor317receives [00000100] as an input of the coded parallel data, scans the MSB first, and, based on the finding that the position of the first information bit ‘1’ found corresponds to 2, outputs [010]. The first counter403counts [000] and outputs it to the comparator405and as the serial conversion control signal C1. The serial converter315outputs a bit of the coded data, i.e. [1], which corresponds to the position indicated by the count [000], based on the serial conversion control signal C1corresponding to the count [000]. The comparator405compares the count [000] with the position of the first information bit found, i.e. [010], and, after finding that they are different, outputs a [LOW] signal as the end_of_word303.

In addition, since the count [000] is different from the position of the first information bit found [010], the first counter403increases the count by1and outputs the resulting count [001] to the comparator405and as the serial conversion control signal C1. The serial converter315outputs a bit of the coded data, i.e. [0], which corresponds to the count [001], based on the serial conversion control signal C1corresponding to the count [001]. The comparator405compares the count [001] with the position of the first information bit found [010] and, after finding that they are different, outputs a [LOW] signal as the end_of_word303.

In addition, since the count [001] is different from the position of the first information bit found [010], the first counter403increases the count by 1 and outputs the resulting count [010] to the comparator405and as the serial conversion control signal C1. The serial converter315outputs a bit of the coded data, i.e. [1], which corresponds to the count [010], based on the serial conversion control signal C1corresponding to the count [010]. The comparator405compares the count [010] with the position of the first information bit found [010] and, after finding that they are identical, outputs a [HIGH] signal as the end_of_word303. After receiving the [HIGH] signal from the comparator405, the first counter403resets the count and prevents the upper 5 bits [00000] of the coded parallel data from being transmitted. As such, the transmitter310transmits [HIGH-LOW-LOW] as the end_of_word303and [100] as the compressed serial data305to the receiver350.

FIG. 10is a flowchart showing a process for receiving compressed serial data according to an embodiment of the present invention.

Referring toFIG. 10, the receiver350receives respective bits of compressed serial data305from the transmitter310in step1001. The parallel converter351stores a bit corresponding to the count in the corresponding latch in step1003. In the initial case of the serial communication system, in step1003, the parallel converter351stores a bit corresponding to the initial count [0] in the corresponding latch.

The second counter601determines if the end_of_word303is a [HIGH] signal in step1005. If the end_of_word303is a [HIGH] signal, the second counter601proceeds to step1009and, in the case of a [LOW] signal, proceeds to step1007. The second counter601increases the count by 1 in step1007so that the next bit is stored in the corresponding latch, and proceeds to step1003.

If the end_of_word303is a [HIGH] signal, the parallel converter351outputs bits stored in a plurality of latches703in step1009. Those of the latches703, in which the bit corresponding to the count is not stored, output [0] as a result of the latch reset operation occurred when the previous compressed serial data was received. The parallel converter351resets the plurality of latches in step1011, in order to store the next transmitted serial data. In step1013, the receiver350converts the compressed serial data, which has been transmitted by the transmitter310, into N-bit coded parallel data307, decodes it, and finishes receiving the parallel data309.

FIG. 11shows a process for receiving compressed serial data by a receiving apparatus according to an embodiment of the present invention.

Based on an assumption that the receiver350has received [HIGH-LOW-LOW] (as the end_of_word) and compressed serial data [100] from the transmitter310as described with reference toFIG. 9, a process for converting the compressed serial data [100] into parallel data by the receiver350according to an embodiment of the present invention will be described.

Referring toFIG. 11, when the receiver350receives respective bits of the compressed serial data [100] from the transmitter310, the second counter601of the decompressor357included in the receiver350counts [000]. The parallel converter701stores [0], which is the bit corresponding to the count [000], in the latch0. Since the end_of_word303is a [LOW] signal in the case of the count [000], the second counter601increases the count by 1 in order to store the next bit in the corresponding latch.

The next bit stored in the parallel converter701is [0], which is the bit corresponding to the increased count [001], in the latch1. Since the end_of_word303is a [LOW] signal in the case of the count [001], the second counter601increases the count by 1.

The next bit stored in the parallel converter701is [1], which is the bit corresponding to the increased count [010], in the latch1. Since the end_of_word303is a [HIGH] signal in the case of the count [010], the second counter601outputs respective bits [00000100] stored in a plurality of latches. Those of the latches, in which the bit corresponding to the count is not stored, i.e. latches3-7output 0 as a result of the latch reset operation occurred when the previous serial data was received. The parallel converter351resets the plurality of latches in order to store the next transmitted serial data.

The receiver350decodes the coded parallel data307, i.e. bits [00000100] outputted by the plurality of latches703, and finishes receiving the initially transmitted parallel data [01010011].

As mentioned above, the present invention compresses serial data by removing 0 bits resulting from SILENT coding.

A detailed comparison to a prior art run-length code scheme is now described to further illustrate the advantages of the present invention. According to the run-length scheme, when the same value is repeated consecutively on a serial data stream, the overall stream amount is reduced by writing the number of repetition and the corresponding value only once. For example, in the case of a stream [AAAAAAAAAAAABAAAAAAAAAAAAABBBAAAAAABAAAAAAAAAA], the corresponding run-length code is [12]A B[13]A[3]B[6]AB[10]A, which is a combination of numbers and symbols (each number denotes the number of repetition of the symbol). The run-length code scheme is basically adapted to a stream of characters, not binary numbers, and is effective when the stream is long and when characters are repeated consecutively a large number of times.

In the case of the 8-bit data [00000100] described with reference toFIGS. 9 and 11, the corresponding run-length code is [5]01[2]0. If this is expressed in terms of binary digits, there is unclear distinction between the numbers and symbols because both of them are expressed in terms of binary digits. Particularly, the binary expression is [101010100]. This binary data exceeds8bits, and this information alone cannot be decoded. If a method for differentiating the numbers and symbols in the run-length code (e.g. conversion to ASCII character codes) is employed, the total bit number substantially exceeds 8 bits. In summary, the run-length code is inefficient to use when a relative small unit of data (e.g. 8 bit, 32 bit, 64 bit) is transmitted at a high rate, unlike the present invention.

As mentioned above, the present invention is advantageous in that, when parallel data is converted into serial data and transmitted in a serial communication system, a conventional coding scheme is used to reduce the number of bit transitions and minimize the dynamic power consumed during the transmission.

In addition, a compression coding scheme is adopted to reduce the amount of transmission and shorten the transmission time. This makes it possible to transmit a larger amount of data in the same amount of time and increases the effective transmission bandwidth.