Semiconductor device and insulated gate bipolar transistor with transistor cells and sensor cell

A transistor cell region of a semiconductor device includes transistor cells that are electrically connected to a first load electrode. An idle region includes a gate wiring structure that is electrically connected to gate electrodes of the transistor cells. A transition region, which is disposed between the transistor cell region and the idle region, includes at least one sensor cell that is electrically connected to a sense electrode. The at least one sensor cell is configured to convey a unipolar current during an on state of the transistor cells.

PRIORITY CLAIM

This application claims priority to German Patent Application No. 10 2014 116 773.2 filed on 17 Nov. 2014, the content of said application incorporated herein by reference in its entirety.

BACKGROUND

Semiconductor switching devices for power applications include transistor cells arrays with a plurality of transistor cells electrically arranged in parallel. The transistor cells control a load current in a load path of the power application. Sense transistor cells integrated in the cell array sense a current through a sense path. The transistor and sense cells may be commonly controlled. On the basis of voltage differences in the sense and load paths, an overcurrent detection circuit may estimate the current flowing through the transistor cells and may turn off the semiconductor switching device when the estimated load current exceeds a predefined threshold.

It is desirable to precisely detect a load current at low complexity and low loss of device performance.

SUMMARY

According to an embodiment, a semiconductor device includes a transistor cell region with transistor cells, wherein the transistor cells are electrically connected to a first load electrode. An idle region includes a gate wiring structure electrically connected to gate electrodes of the transistor cells. A transition region disposed between the transistor cell region and the idle region includes a sensor cell electrically connected to a sense electrode. The sensor cell conveys a unipolar current during an on-state of the transistor cells.

According to an embodiment, an insulated gate bipolar transistor includes a transistor cell region with transistor cells, wherein the transistor cells are electrically connected to a first load electrode. An idle region includes a gate wiring structure electrically connected to gate electrodes of the transistor cells. A transition region disposed between the transistor cell region and the idle region includes a sensor cell electrically connected to a sense electrode. The sensor cell conveys a unipolar current during an on-state of the transistor cells.

DETAILED DESCRIPTION

The term “electrically connected” describes a permanent low-ohmic connection between electrically connected elements, for example a direct contact between the concerned elements or a low-ohmic connection via a metal and/or highly doped semiconductor. The term “electrically coupled” includes that one or more intervening element(s) adapted for signal transmission may be provided between the electrically coupled elements, for example resistors or elements that are controllable to temporarily provide a low-ohmic connection in a first state and a high-ohmic electric decoupling in a second state.

FIGS. 1A to 1Drefer to a semiconductor device500including a bipolar device, e.g., an IGBT (insulated gate bipolar transistor), for example, a PT-IGBT (punch through IGBT), an NPT-IGBT (non-punch through IGBT), an RC-IGBT (reverse conducting IGBT) or a semiconductor device integrating an IGBT and one or more further logic or analogue circuits, e.g., a gate driver circuit and/or an overcurrent protection circuit.

The semiconductor device500is based on a semiconductor body100of a crystalline semiconductor material, for example silicon (Si), silicon carbide (SiC), germanium (Ge), silicon germanium (SiGe), gallium nitride (GaN), gallium arsenide (GaAs) or any other AIIIBVsemiconductor. At a front side the semiconductor body100has a first surface101which is planar or which is spanned by coplanar surface sections. A minimum distance between the first surface101and a planar second surface102at an opposite rear side and parallel to the first surface101defines the voltage blocking capability of the semiconductor device500. For example, the semiconductor body100of an IGBT specified for a blocking voltage of about 1200 V may have a thickness between 90 μm and 110 μm. Embodiments related to higher blocking capabilities may be based on semiconductor bodies100with a thickness of several 100 μm.

In a plane perpendicular to the cross-sectional plane, the semiconductor body100may have an approximately rectangular shape with an edge length in the range of several millimeters. A normal to the first surface101defines a vertical direction and directions orthogonal to the vertical direction are horizontal directions.

The semiconductor body100includes a drift structure120of a first conductivity type, wherein a main portion of the drift structure120forms a drift zone121. In the drift zone121, a dopant concentration may gradually or in steps increase or decrease with increasing distance to the first surface101at least in portions of its vertical extension. According to other embodiments, the dopant concentration may be approximately uniform in the complete drift zone121. A mean dopant concentration in the drift zone121may be between 1E12 cm−3and 1E15 cm−3, for example in a range from 5E12 cm−3to 5E13 cm−3.

The semiconductor body100further includes a collector structure130between the drift structure120and the second surface102. The collector structure130may be a contiguous layer of the second conductivity type, which is the opposite of the first conductivity type. According to embodiments related to RC-IGBTs, the collector structure130may include zones of both conductivity types. The dopant concentration in the collector structure130is sufficiently high to ensure a low ohmic contact to a metal structure adjoining the second surface102. For example, a maximum dopant concentration in the collector structure130along the second surface102may be at least 1E18 cm−3, for example at least 5E19 cm−3.

A transistor cell region610of the semiconductor body100includes transistor cells TC, e.g., IGFET (insulated gate field effect transistor) cells. The transistor cells TC may be vertical transistor cells including planar gate structures formed outside the semiconductor body100along the first surface101.

The semiconductor device500ofFIG. 1Ais based on vertical transistor cells TC with trench gate structures150extending from the first surface101into the semiconductor body100.

The gate structures150include a conductive gate electrode155and a gate dielectric151separating the gate electrode155from the semiconductor body100. The gate electrode155may be a homogeneous structure or may have a layered structure including one or more metal containing layers. According to an embodiment, the gate electrode155may include or consist of a heavily doped polycrystalline silicon layer.

The gate dielectric151may have uniform thickness and may include or consist of a semiconductor oxide, for example thermally grown or deposited silicon oxide, a semiconductor nitride, for example deposited or thermally grown silicon nitride, or a semiconductor oxynitride, for example silicon oxynitride.

Semiconducting portions of the transistor cells TC are formed in active cell mesas170aadjoining at least one gate structure150. The active mesas170ainclude source zones110of the first conductivity type and body zones115of the second conductivity type, wherein the body zones115separate the source zones110from the drift structure120and form first pn junctions pn1 with the drift structure120and second pn junctions pn2 with the source zones110.

A layer structure including an interlayer dielectric210separates electrode structures310,330,340from the semiconductor body100. The interlayer dielectric210may include one or more dielectric layers from silicon oxide, silicon nitride, silicon oxynitride, doped or undoped silicate glass, for example BSG (boron silicate glass), PSG (phosphorus silicate glass) or BPSG (boron phosphorus silicate glass), by way of example. The layer structure may include further layers, e.g., portions of a gate electrode.

In the transistor cell region610contact structures315extending through the interlayer dielectric210electrically connect a first load electrode310with the source zones110and the body zones115of the transistor cells TC, wherein heavily doped body contact zones115xmay form low-ohmic contacts between the body zones115and the contact structures315. The first load electrode310may form or may be electrically coupled or connected to an emitter terminal E. A second load electrode310directly adjoining the second surface102and the collector layer130may form or may be electrically coupled or connected to a collector terminal C.

In an idle region630of the semiconductor device500, a gate wiring structure330electrically connected to the gate electrodes155of the transistor cells TC is arranged at the front side and outside of the semiconductor body100. A layer structure including at least the interlayer dielectric210may separate the gate wiring structure330from the semiconductor body100. The gate wiring structure330may form or may be electrically coupled or connected to a gate terminal G or to an output of an internal gate driver circuit integrated in the semiconductor device500.

The gate wiring structure330may include at least one of a gate pad, a gate finger and a gate runner, wherein a gate pad is a metal pad suitable as a landing pad for a bondwire or another chip-to-lead frame or a chip-to-chip connection like a soldered clip. A gate runner is a conductive line running along at least one edge of the transistor cell region610, wherein the conductive line may be a metal line or a connection line consisting of or including a heavily doped semiconductor material. A gate finger is a conductive line dividing a transistor cell region610into separate transistor cell fields, wherein the conductive line may be a metal line or a connection line consisting of or including a heavily doped semiconductor material.

A transition region620sandwiched between the idle region630and the transistor cell region610includes at least one sense cell SC as illustrated inFIG. 1A. According to an embodiment, the transition region620exclusively includes sense cells SC. According to other embodiments, the transition region620may include purge cells PC as illustrated inFIG. 1Bin addition to one or more sense cells SC.

The sense cell SC includes a purge zone117of the conductivity type of the body zones115. The purge zone117is formed at least along one edge of the transistor cell region610and may directly adjoin a gate structure150of the outermost transistor cell TC of the transistor cell region610. A vertical extension of the purge zone117in the transition region620may correspond to the vertical extension of the body zones115in the active cell mesas170aor to a vertical extension of other doped zones of the same conductivity type that extend from the first surface101into the semiconductor body100.

Further contact structures317extending through the interlayer dielectric210electrically connect a sense electrode340with the purge zones117of the sense cells SC in the transition region620, wherein heavily doped purge contact zones117xmay form a low-ohmic contact between the purge zones117and the further contact structures317. The sense electrode340may form or may be electrically coupled or connected with a sense terminal SNS, with an internal sense load and/or with an internal sense circuit integrated in the semiconductor device500.

According to an embodiment, an external sense load or shunt is electrically connected to the sense terminal SNS and an external sense circuit senses the voltage drop across the external sense load. The external sense circuit may output a signal indicating an overcurrent or overload condition of the semiconductor device500or may directly shutdown a signal applied to the gate terminal G.

The purge cells PC differ from the sense cells SC in that the purge zones117of the purge cells PC are not directly electrically connected to the sense electrode340but to first load electrode310.

The following description of the effects of the purge and sense cells PC, SC refers to n-channel IGBTs with p-type body zones115. Similar considerations as outlined below apply to embodiments with the body zones115being p-type.

When a voltage applied to the gate wiring structure330exceeds a preset threshold voltage, electrons in the body zones115accumulate in channel portions directly adjoining the gate dielectrics151. The accumulated electrons form inversion channels between the source zones110and the drift structure120. Electrons passing through the inversion channels into the drift structure120are effective as a base current for a bipolar transistor structure formed by the p-type body zones115, the n-type drift structure120and the p-type collector layer130such that a bipolar current involving both types of carriers, i.e., electrons and holes, flows between the first load electrode310and the second load electrode320and turns on the semiconductor device500. Charge carriers of both types flood the drift structure and a charge carrier plasma with high carrier density builds up in the semiconductor body100.

During the on-state, the purge cells PC drain off holes from the semiconductor body100. In this way, the purge cells PC keep the hole density low in the idle and transition regions630,620while contributing to the total on-state current.

When the semiconductor device turns off, the charge carrier plasma is removed by draining the charge carriers off through the load electrodes310,320. The less charge carriers have to be removed during the off-state, the lower are the switching losses of the semiconductor device500. Since yet during the on-state the purge cells PC drain off such holes that otherwise may flood the idle region630in the on-state of the IGBT501without contributing to a low on-state resistance RDSon, only few charge carriers have to be removed from the idle region630. In this way the purge cells PC significantly reduce switching losses of the semiconductor device500.

A sense cell SC which is arranged in the transition region620and which differs from the purge cells PC only in that the sense cell SC is electrically connected to a sense electrode340where the purge cells PC are electrically connected to the first load electrode310may be used for sensing a hole current proportional to the load current without losing useful area for active transistor cells TC. The sense cells SC further contribute in keeping the charge carrier plasma low in the idle regions630. Formation of the sense cells requires only few and low-critical modifications in existing process flows.

As illustrated inFIG. 10an edge of a first load electrode310oriented to the gate wiring structure330may have one or more notches in which one or more sense electrodes340may be formed. The sense electrode340may form a sense terminal SNS of the semiconductor device500or may be electrically coupled or connected to a sense terminal SNS or an input of an integrated sense circuit. For example, a bondwire may electrically connect the sense electrode340with the sense terminal. According to another embodiment a conductor line in the plane of the electrodes310,330,340or in another wiring layer may electrically connect the sense electrode340with the sense terminal SNS or with an integrated sense circuit.

FIG. 1Dshows a sense cell SC electrically connected between a collector terminal C and a sense terminal SNS and/or an integrated sense circuit510that may include a defined sense resistor for sensing a charge carrier flow through the sense cell SC. The integrated sense circuit may output a control signal that controls a gate driver electrically connected to the gate wiring structure330. If the integrated sense circuit indicates that the sense current exceeds a predetermined threshold, the control signal may turn off the gate driver.

InFIG. 2A, line701plots a load current ITC through the transistor cells TC of an n-channel IGBT as a function of a gate-to-emitter voltage VGE. Line702plots a corresponding unipolar charge carrier flow ISC through sense cells SC as a function of the gate voltage VGE, respectively.

The transistor cells TC turn on, when the gate voltage VGE exceeds at a first threshold voltage Vth1at which the inversion channels through the body zones of the transistor cells TC are formed. A unipolar electron current flows into the semiconductor body100and at first no holes are detectable through the sense cells SC which can only convey a hole current. When the gate voltage VGE exceeds the second threshold voltage Vth2, hole injection starts and the sense cells SC start detecting a hole current. Since in the resulting charge carrier plasma, the number of electrons corresponds to the number of holes, the load current ITC through the transistor cells TC can be estimated on the basis of the detected hole current ISC through the sense cells SC.

InFIG. 2Ba conductor line in the plane of the electrodes310,330,340or in another wiring layer may electrically connect the sense electrode340with a sense pad390and a bondwire391electrically connects the sense pad390with the first load electrode310. Semiconductor devices with and without sense cells can be manufactured using the same processes up to wiring bonding.

FIGS. 3A to 3Brefer to a semiconductor device500with stripe-shaped gate structures150in the transistor cell region, wherein stripe-shaped cell mesas170between the gate structures150may include active cell mesas170aincluding source zones110and passive cell mesas170bwithout source zones110. Active and passive cell mesas170a,170bmay alternate along the longitudinal extension of the cell mesas170or may alternate along a horizontal direction orthogonal to the longitudinal extension of the cell mesas170or both.

In addition, the transistor cell region610may include trench field electrode structures160extending between neighboring gate structures150from the first surface101into the semiconductor body100. The field electrode structures160may include a conductive field electrode165and field dielectrics161insulating the field electrode165against the semiconductor body100. Materials and configuration of the field electrode165may be the same as that of the gate electrode155and materials and configuration of the field dielectrics161may be the same as that of the gate dielectrics151. The field electrode165may be electrically connected with the first load electrode310or with another structure in the semiconductor device500.

Active cell mesas170adirectly adjoining gate structures150form the transistor cells TC. Passive cell mesas170bwithout any source zones110or with source zones without low-ohmic connection to the first load electrode310form idle cells IC. In the idle cells IC, a vertical extension of the body zones115between the first surface101and the respective first pn junction pn1 may correspond to a distance between the first surface101and the first pn junction pn1 in an active cell mesa170a.

According to other embodiments, the vertical extension of the body zones115in the idle cells IC may be greater than the distance between the first surface101and the first pn junctions pn1 in the active cell mesas170a. For example, a vertical extension of the body zones115in the passive cell mesas170bmay be approximately equal to the vertical extension of the gate structures150.

For RC-IGBTs, the body zones115of the idle cells IC may be electrically connected to the first load electrode310. The body zones115of idle cells IC in non-reverse conducting IGBTs may be floating body zones.

A further portion of the drift structure120between the drift zone121and the collector structure130may form a field stop layer128or a buffer layer wherein a mean net dopant concentration in the field stop layer128is at least five times as high as a mean net dopant concentration in the drift zone121.

For further details reference is made to the description ofFIGS. 1A to 1D.

FIG. 3Bshows a comb-like sense electrode340including dent portions341extending into notches in the adjoining edge of the first load electrode310. The comb-like sense electrode340further includes a connecting portion342connecting the dent portions341. The comb-like sense electrode240allows for connecting a plurality of sense cells SC in the metallization plane of the gate wiring structure330and the first load electrode310.

FIGS. 4A to 4Brefer to a semiconductor device500with gate structures150including ring-shaped trench portions150aextending from the first surface101into the semiconductor body100as well as a connecting portion150bextending outside the semiconductor body100along the first surface101.

Dot-shaped active cell mesas170aincluding body zones115and source zones110are formed within the ring-shaped trench portions150a. A grid-shaped passive cell mesa170bwithout source zones110is formed outside the ring-shaped trench portions150a. A body zone115in the passive cell mesa170bmay float and may have a vertical extension that exceeds a distance between the first surface101and the first pn junctions pn1 in the active cell mesas170a. For example, the vertical extension of the body zone115in the passive cell mesas170bmay be equal to or greater than a vertical extension of the ring-shaped trench portions150a.

A vertical extension of the purge zone117in the transition region620may correspond to the vertical extension of the body zone115in the passive cell mesas170bor to the vertical extension of the body zones115in the active cell mesas170a.

The connecting portion150bof the gate structure150may extend through the transition region620into the idle region630. A gate contact313may extend through an interlayer dielectric210, which separates the electrode structures310,330,340from the connecting portion150bof the gate structure150, to or into the connecting portion150b.

FIG. 5shows a semiconductor device500with a gate wiring structure330including a gate pad330bin a center of the semiconductor body100and gate fingers330aseparating a first load electrode310into several separated sections. A sense electrode340may include a strip connection340a, e.g., an aluminum connection line, along the edges of the gate wiring structure330. The sense electrode340may further include a sense pad340bconnected with the strip connection340aand adjoining the gate pad330b. The sense pad340bas well as the gate pad330bmay be landing pads for bondwires. According to other embodiments at least one of the gate and sense pads330b,340bis arranged close to a lateral side surface103of the semiconductor body100.