Split dual gate field effect transistor

A semiconductor device with at least two gate regions. The device includes a substrate region including a surface, a source region in the substrate region, and a drain region in the substrate region. The drain region and the source region are separate from each other. Additionally, the device includes a first gate region on the surface, a second gate region on the surface, and an insulation region on the surface and between the first gate region and the second gate region. The first gate region and the second gate region are separated by the insulation region. The first gate region is capable of forming a first channel in the substrate region. The first channel is from the source region to the drain region. The second gate region is capable of forming a second channel in the substrate region. The second channel is from the source region to the drain region.

CROSS-REFERENCES TO RELATED APPLICATIONS

This application claims priority to Chinese Patent Application No. 200610023748.9, filed Feb. 6, 2006, commonly assigned, incorporated by reference herein for all purposes.

The following two commonly-owned co-pending applications, including this one, are being filed concurrently and the other one is hereby incorporated by reference in its entirety for all purposes:

1. U.S. patent application Ser. No. 12/549,192, filed Aug. 27, 2011 in the name of Deyuan Xiao, Gary Chen, Tan Leong Seng, and Roger Lee, titled, “Method for Making Split Dual Gate Field Effect Transistor,”; and

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BACKGROUND OF THE INVENTION

The present invention is directed to integrated circuits. More particularly, the invention provides a split dual gate field effect transistor. Merely by way of example, the invention has been applied to a logic system. But it would be recognized that the invention has a much broader range of applicability.

Integrated circuits or “ICs” have evolved from a handful of interconnected devices fabricated on a single chip of silicon to millions of devices. Current ICs provide performance and complexity far beyond what was originally imagined. In order to achieve improvements in complexity and circuit density (i.e., the number of devices capable of being packed onto a given chip area), the size of the smallest device feature, also known as the device “geometry”, has become smaller with each generation of ICs. Semiconductor devices are now being fabricated with features less than a quarter of a micron across.

Increasing circuit density has not only improved the complexity and performance of ICs but has also provided lower cost parts to the consumer. An IC fabrication facility can cost hundreds of millions, or even billions, of dollars. Each fabrication facility will have a certain throughput of wafers, and each wafer will have a certain number of ICs on it. Therefore, by making the individual devices of an IC smaller, more devices may be fabricated on each wafer, thus increasing the output of the fabrication facility. Making devices smaller is very challenging, as a given process, device layout, and/or system design often work down to only a certain feature size.

An example of such a limit is how to reduce the transistor leakage current and improve the transistor drive current. For example, reducing the source-drain voltage of a transistor can lower the active power, but doing so often reduces the transistor drive current. The transistor drive current can be improved by reducing the threshold voltage and thinning the gate dielectric, but such actions often raise the transistor leakage current.

From the above, it is seen that an improved transistor structure is desired.

BRIEF SUMMARY OF THE INVENTION

The present invention is directed to integrated circuits. More particularly, the invention provides a split dual gate field effect transistor. Merely by way of example, the invention has been applied to a logic system. But it would be recognized that the invention has a much broader range of applicability.

In a specific embodiment, the invention provides a semiconductor device with at least two gate regions. The device includes a substrate region including a surface, a source region in the substrate region, and a drain region in the substrate region. The drain region and the source region are separate from each other. Additionally, the device includes a first gate region on the surface, a second gate region on the surface, and an insulation region on the surface and between the first gate region and the second gate region. The first gate region and the second gate region are separated by the insulation region. The first gate region is capable of forming a first channel in the substrate region. The first channel is from the source region to the drain region. The second gate region is capable of forming a second channel in the substrate region. The second channel is from the source region to the drain region.

According to another embodiment, a semiconductor transistor with at least two gate regions includes a substrate region including a surface, a source region in the substrate region, and a drain region in the substrate region. The drain region and the source region are separate from each other. Additionally, the transistor includes a first gate region on the surface, a second gate region on the surface, and an insulation region on the surface and between the first gate region and the second gate region. Moreover, the transistor includes a first spacer region. The first spacer region is in contact with the first gate region, the second gate region, and the insulation region. Also, the transistor includes a second spacer region. The second spacer region is in contact with the first gate region, the second gate region, and the insulation region. The first gate region and the second gate region are separated by the insulation region. The first gate region is capable of forming a first channel from the source region to the drain region in the substrate region, and the second gate region is capable of forming a second channel from the source region to the drain region in the substrate region. The first channel and the second channel are not in contact to each other.

According to yet another embodiment, a transistor with at least two gate regions includes a substrate region including a surface, a source region in the substrate region, and a drain region in the substrate region. The drain region and the source region are separate from each other. Additionally, the transistor includes a first gate region on the surface, a second gate region on the surface, and an insulation region on the surface and between the first gate region and the second gate region. Moreover, the transistor includes a first spacer region. The first spacer region is in contact with the first gate region, the second gate region, and the insulation region. Also, the transistor includes a second spacer region. The second spacer region is in contact with the first gate region, the second gate region, and the insulation region. The first gate region and the second gate region are separated by the insulation region. The first gate region is capable of forming a first channel from the source region to the drain region in the substrate region, and the second gate region is capable of forming a second channel from the source region to the drain region in the substrate region. The first channel and the second channel are not in contact to each other. The first channel is associated with a first channel length, the first channel length being equal to or shorter than 200 nm. The insulation region is associated with a width in a direction from the first gate region to the second gate region, and the width ranges from 10 nm to 10,000 nm.

Many benefits are achieved by way of the present invention over conventional techniques. Some embodiments of the present invention provide a new planar split dual gate transistor device. Certain embodiments of the present invention provide dual gates that can be biased independently. For example, the independent gate biases can provide dynamical control of the device characteristics such as threshold voltage, sub-threshold swing, and/or the saturation drain current. Some embodiments of the present invention can significantly reduce transistor leakage current. For example, the reduction can reach about 67%. In another example, the reduction can reach about 75%. Certain embodiments of the present invention can provide adjustable threshold voltage without varying gate oxide thickness or doping profile. Some embodiments of the present invention provide an energy band that varies along all three dimensions.

DETAILED DESCRIPTION OF THE INVENTION

The present invention is directed to integrated circuits. More particularly, the invention provides a split dual gate field effect transistor. Merely by way of example, the invention has been applied to a logic system. But it would be recognized that the invention has a much broader range of applicability.

FIG. 1is a simplified diagram for split dual gate field effect transistor according to an embodiment of the present invention. This diagram is merely an example, which should not unduly limit the scope of the claims. One of ordinary skill in the art would recognize many variations, alternatives, and modifications. The device100includes the following components:

Although the above has been shown using a selected group of components for the device100, there can be many alternatives, modifications, and variations. For example, some of the components may be expanded and/or combined. Other components may be inserted to those noted above. Depending upon the embodiment, the arrangement of components may be interchanged with others replaced. For example, the device100is an NMOS transistor. In another example, the device100is a PMOS transistor. Further details of these components are found throughout the present specification and more particularly below.

In one embodiment, the substrate region110is made of a semiconductor material. For example, the semiconductor material is silicon. The semiconductor substrate region110is intrinsic or doped to p-type or n-type. For example, the substrate region110is doped to p-type, with a dopant concentration ranging from 1.0×1015cm−3to 2.0×1015cm−3. In another example, the substrate region110is doped to n-type, with a dopant concentration ranging from 1.0×1015cm−3to 2.0×1015cm−3.

The source region120and the drain region130are doped to n-type or p-type. For example, the source region120is doped to n-type with a dopant concentration ranging from 1.0×1018cm−3to 1.0×1019cm−3, and the drain region130is doped to n-type with a dopant concentration ranging from 1.0×1018cm−3to 1.0×1019cm−3. In another example, the source region120is doped to p-type with a dopant concentration ranging from 1.0×1018cm−3to 1.0×1019cm−3, and the drain region130is doped to p-type with a dopant concentration ranging from 1.0×1018cm−3to 10×1019cm−3.

The gate dielectric region180is located on the top surface112of the substrate region110. For example, the gate dielectric region180is made of silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof. In another example, the gate dielectric region is a dielectric layer. The gate regions140and150and the insulation region160are located on the gate dielectric region180. For example, the gate regions140and150each are made of polysilicon. As shown inFIG. 1, the gate regions140and150are not in direct contact with each other but are separated by the insulation region160. For example, the insulation region160has two side surfaces, one of which is in direct contact with the gate region140and the other one of which is in direct contact with the gate region150. In another example, the insulation region160includes a gap, such as an air gap. In yet another example, the insulation region160includes silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof. In yet another example, the insulation region160includes a salicide block layer (SAB), such as an silicon-rich oxide layer.

The spacer regions170and172are located on the top surface112. The spacer region170is in direct contact with the gate regions140and150and the insulation region160on one side, and the spacer region172is in direct contact with the gate regions140and150and the insulation region160on another side. For example, the spacer regions170and172each are made of silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof.

FIG. 2is a simplified top-view layout diagram for split dual gate field effect transistor according to another embodiment of the present invention. This diagram is merely an example, which should not unduly limit the scope of the claims. One of ordinary skill in the art would recognize many variations, alternatives, and modifications. The device100includes at least the source region120, the drain region130, the gate regions140and150, and the insulation region160. Although the above has been shown using a selected group of components for the device100, there can be many alternatives, modifications, and variations. For example, some of the components may be expanded and/or combined. Other components may be inserted to those noted above. Depending upon the embodiment, the arrangement of components may be interchanged with others replaced. Further details of these components are found throughout the present specification and more particularly below.

As shown inFIG. 2, the gate regions140and150are separated by the insulation region160. The gate regions140and150and the insulation region160form a continuous region, and the continuous region separates the source region120and the drain region130in the top view. The gate region140includes side surfaces142and144, the gate region150includes side surfaces152and154, and the insulation region160includes side surfaces162and164. For example, the side surfaces142,152, and162form a continuous surface, and the side surfaces144,154, and164form another continuous surface. In another example, the source region120is aligned with the side surfaces142,152, and162. In yet another example, the drain region130is aligned with the side surfaces144,154, and164.

The source region120has a width124, and the drain region130has a width134. For example, the width124ranges from 10 nm to 20,000 nm. In another example, the width134ranges from 10 nm to 10,000 nm. In one embodiment, the widths124and134are the same. In another embodiment, the widths124and134are different. The gate region140has a length146, and the gate region150has a length156. For example, the length146ranges from 10 nm to 1,000 nm. In another example, the length156ranges from 10 nm to 1,000 nm. In one embodiment, the lengths146and156are the same. In another embodiment, the lengths146and156are different. The gate region140has a width148, the gate region150has a width158, and the insulation region160has a width168. For example, the total width for the width148, the width158, and the width168is equal to the width124and/or the width134. In another example, the width148ranges from 10 nm to 15,000 nm. In yet another example, the width158ranges from 10 nm to 15,000 nm. In yet another example, the width168ranges from 10 nm to 15,000 nm. In yet another example, the width168ranges from 10 nm to 10,000 nm. In one embodiment, the widths148and158are the same. In another embodiment, the widths148and158are different.

As shown inFIGS. 1 and 2, the gate regions140and150are physically separated by the insulation region160according to an embodiment of the present invention. For example, the gate regions140and150can be biased to different voltage levels. In another embodiment, the gate region140with proper bias can form a channel from the source region120to the drain region130in the substrate region110, and the gate region150with proper bias can form another channel from the source region120to the drain region130in the substrate region110. For example, the channel under the gate region140has a length146, and the channel under the gate region150has a length156.

FIGS. 3(A), (B), (C), and (D) are simplified three-dimensional energy-band diagrams for split dual gate field effect transistor according to an embodiment of the present invention. These diagrams are merely examples, which should not unduly limit the scope of the claims. One of ordinary skill in the art would recognize many variations, alternatives, and modifications. For example, as shown inFIG. 1, the energy-band diagrams describe the energy band along a line123between the source region120and the drain region130. In one embodiment, the line123is in close proximity and substantially parallel to the top surface112. In another embodiment, the device100is an NMOS transistor, and a bottom surface114of the substrate region110is biased to zero volt.

FIG. 3(A)shows the energy band in equilibrium with zero volt applied to both the gate region140and the gate region150. The source region120and the drain region130each are biased also to zero volt.FIG. 3(B)shows the energy band in equilibrium with a non-zero-volt applied to both the gate regions140and150. The source region120and the drain region130each are biased to zero volt.

FIG. 3(C)shows the energy band in non-equilibrium state with a non-zero-volt bias being applied to the gate regions140and150. The source region120is biased to zero volt, and the drain region130is biased to non-zero volt. The energy band bends downward from the source region120to the drain region130.FIG. 3(D)shows the energy band in non-equilibrium state with a non-zero-volt bias applied to the gate region140and another different non-zero-volt bias applied to the gate region150. The source region120is biased to zero volt, and the drain region130is biased to non-zero volt. As shown inFIG. 3(D), the energy band is twisted in a first direction and bends downward in a second direction from the source region120to the drain region130. For example, the first direction is parallel to the widths148,158, and168. In another example, the second direction is parallel to the lengths146and156.

FIGS. 4(A), (B), (C), (D), and (E) are simplified diagrams showing charges, electric field, and potential distribution for split dual gate field effect transistor according to an embodiment of the present invention. These diagrams are merely examples, which should not unduly limit the scope of the claims. One of ordinary skill in the art would recognize many variations, alternatives, and modifications. For example, the split dual gate field effect transistor is the device100.

To derive certain characteristics of the split dual gate field effect transistor, the following assumptions are made:1. The gate structure corresponds to an ideal MOS diode;2. Only drift current is considered;3. Carrier mobility in the inversion layer is constant;4. Dopant concentration in the channel region is uniform;5. Reverse leakage current is negligible;6. The transverse electric field that is generated by the gate region140and/or the gate region150and perpendicular to the current flow is much greater than the longitudinal electric field created by the drain region130and parallel to the current flow. Accordingly, the gradual channel approximation is used. Charges in the surface depletion region is assumed to be induced only by the transverse electric field.7. By applying different voltages to the gate regions140and150, the electric field perpendicular to the current flow is not uniform in a direction that is parallel to the widths148,158, and168.

The charge per unit area in the inversion layer is given by:
Qn(y,z)=Qs(y,z)−Qsc(y,z)  (Equation 1)
Qs(y,z)=−[VG(z)−ψs(y)]C(Equation 2)

The surface potential ψsfor inversion at (y,z) can be approximated as:

Substituting this into the equation for the charge in the inversion layer, the following can be obtained:

where V(y) is the reverse drain bias at point of (y, z). The conductivity of the channel at a position y is given by:
σ(x)=en(x)μn(x)  (Equation 5)

For a constant mobility, the channel conductance is then

where Qnis the total charge per unit area in the inversion layer. The resistance of an elemental section of the channel dydz is as follows:

The voltage drop across the same elemental section dy is,

If the equation for Qn(y,z) is substitued and integrated from the source region120(y=0, V(0)=0) to the drain region130(y=L, V(L)=VD) and from the gate region140(z=0) to the gate region (z=W), the total current flow from source to drain can be expressed by:

where Z1represents the width148, Z2represents the width168, and Z3represents the width158. The sum of Z1, Z2, and Z3is equal to W. In one embodiment of the present invention, Z1, Z2, and Z3are equal. Accordingly, Equation 9 can be transformed as follows:

FIG. 5is a simplified diagram showing drain current as a function of gate biases for split dual gate field effect transistor according to an embodiment of the present invention. This diagram is merely an example, which should not unduly limit the scope of the claims. One of ordinary skill in the art would recognize many variations, alternatives, and modifications.

For example, the split dual gate field effect transistor is the device100. A horizontal axis502represents the voltage applied to the gate region140, and a vertical axis504represents the drain current. The drain region130is biased to 50 mV, and the source region120and the bottom surface114are grounded. The total width of the width148, the width158, and the width168is equal to about 10 μm, and each of the lengths146and156is equal to about 0.18 μm. For curves510,520,530, and540, the gate region150is biased to 1.8 volts, 1.2 volts, 0.6 volts, and 0 volt respectively. As an example, the curves510,520,530, and540each are determined based on Equation 10.

FIG. 6is a simplified diagram showing drain current as a function of drain bias for split dual gate field effect transistor according to an embodiment of the present invention. This diagram is merely an example, which should not unduly limit the scope of the claims. One of ordinary skill in the art would recognize many variations, alternatives, and modifications.

For example, the split dual gate field effect transistor is the device100. Horizontal axes602and612each represent the voltage applied to the drain region130, and vertical axes604and614each represent the drain current. The source region120and the bottom surface114are grounded. The total width of the width148, the width158, and the width168is equal to about 10 μm, and each of the lengths146and156is equal to about 0.18 μm. For curves622,624, and626, the gate region150is biased to 1.5 volts, and for curves632and634, the gate region150is biased to 0 volt. The curves622,624, and626correspond to 1.2, 1.0, and 0.8 volts respectively, which are applied to the gate region140. The curves632and634correspond to 1.2 volts and 1.0 volts respectively, which are applied to the gate region140. As an example, the curves622,624,626,632, and634each are determined based on Equation 10.

According to an embodiment of the present invention, drifting is assumed to be the dominant transport mechanism for carriers in the charge sheet, and Z1, Z2, and Z3are assumed to be equal. When the channel regions under both the gate regions140and150are in weak inversion,

where

ψs≅VG-VT,β=qkT.
The drain current density JDis equal to ID/A as follows:

FIG. 7is a simplified diagram showing drain current density as a function of gate biases under weak inversion for split dual gate field effect transistor according to an embodiment of the present invention. This diagram is merely an example, which should not unduly limit the scope of the claims. One of ordinary skill in the art would recognize many variations, alternatives, and modifications.

For example, the split dual gate field effect transistor is the device100. A horizontal axis702represents the voltage applied to the gate region140, and a vertical axis704represents the drain current density. The drain region130is biased to 2 volts, and the source region120and the bottom surface114are grounded. Each of the lengths146and156is equal to about 0.18 μm. For curves710,720,730,740,750,760, and770, the gate region150is biased to 0.5, 0.4, 0.3, 0.2, 0.1, 0, −0.1, and −0.2 volts respectively. As an example, the curves710,720,730,740,750,760, and770each are determined based on Equation 12

According to an embodiment of the present invention, sub-threshold conduction in split dual gate field effect transistor is governed by the potential distribution in the entire device. For example, the split dual gate field effect transistor is the device100.

FIG. 8is a simplified diagram showing drain current as a function of gate biases for split dual gate field effect transistor according to an embodiment of the present invention. This diagram is merely an example, which should not unduly limit the scope of the claims. One of ordinary skill in the art would recognize many variations, alternatives, and modifications.

For example, the split dual gate field effect transistor is the device100. A horizontal axis802represents the voltage applied to the gate region140, and a vertical axis804represents the drain current. The drain region130is biased to 1.8 volts, and the source region120and the bottom surface114are grounded. Each of the lengths146and156is equal to about 0.18 μm, and the gate oxide region180is about 16 Å in thickness. For curves810and820, the gate region150is biased to 0 and −1.5 volts respectively. As shown inFIG. 8, the leakage current is equal to about 7.5×10−11A/μm if the gate region150is biased to 0 volt. Additionally, the leakage current is equal to about 3.4×10−11A/μm if the gate region150is biased to −1.5 volt. The saturation current is equal to about 1.344 mA/μm. As an example, the curves810and820each are determined by computer simulation.

FIG. 9is a simplified diagram showing a cross-sectional SEM image along the channel length direction for split dual gate field effect transistor according to an embodiment of the present invention. This diagram is merely an example, which should not unduly limit the scope of the claims. One of ordinary skill in the art would recognize many variations, alternatives, and modifications. The channel length direction points from one of the source region120and the drain region130to the other of the source region120and the drain region130. For example, the split dual gate field effect transistor is the device100.

FIG. 10is a simplified diagram showing a cross-sectional SEM image along the channel width direction for split dual gate field effect transistor according to an embodiment of the present invention. This diagram is merely an example, which should not unduly limit the scope of the claims. One of ordinary skill in the art would recognize many variations, alternatives, and modifications. For example, the split dual gate field effect transistor is the device100.

FIG. 11is a simplified diagram showing measured drain current as a function of gate biases at low drain voltage for split dual gate field effect transistor according to an embodiment of the present invention. This diagram is merely an example, which should not unduly limit the scope of the claims. One of ordinary skill in the art would recognize many variations, alternatives, and modifications.

For example, the split dual gate field effect transistor is the device100. A horizontal axis1102represents the voltage applied to the gate region140, and a vertical axis1104represents the drain current. The drain region130is biased to 50 mV, and the source region120and the bottom surface114are grounded. The total width of the width148, the width158, and the width168is equal to about 10 μm, and each of the lengths146and156is equal to about 0.18 μm. Z1, Z2, and Z3are substantially equal. For the curves1110, the gate region150is biased to 1.0, 0.5, 0, −0.5, and −1.0 volt respectively.

FIG. 12is a simplified diagram showing measured drain current as a function of gate biases at low drain voltage for split dual gate field effect transistor according to another embodiment of the present invention. This diagram is merely an example, which should not unduly limit the scope of the claims. One of ordinary skill in the art would recognize many variations, alternatives, and modifications.

For example, the split dual gate field effect transistor is the device100. A horizontal axis1202represents the voltage applied to the gate region140, and a vertical axis1204represents the drain current. The drain region130is biased to 500 mV, and the source region120and the bottom surface114are grounded. The total width of the width148, the width158, and the width168is equal to about 10 μm, and each of the lengths146and156is equal to about 0.18 μm. Z1, Z2, and Z3are substantially equal. For the curves1210, the gate region150is biased to various voltages respectively.

FIG. 13is a simplified diagram showing measured drain current as a function of gate biases at high drain voltage for split dual gate field effect transistor according to yet another embodiment of the present invention. This diagram is merely an example, which should not unduly limit the scope of the claims. One of ordinary skill in the art would recognize many variations, alternatives, and modifications.

For example, the split dual gate field effect transistor is the device100. A horizontal axis1302represents the voltage applied to the gate region140, and a vertical axis1304represents the drain current. The drain region130is biased to 1.8 volts, and the source region120and the bottom surface114are grounded. The total width of the width148, the width158, and the width168is equal to about 10 μm, and each of the lengths146and156is equal to about 0.18 μm. Z1, Z2, and Z3are substantially equal. For the curves1310, the gate region150is biased to 0, −0.1, −0.2, −0.3, −0.4, and −0.5 volts respectively. As shown inFIG. 13, Ioffis equal to 2.97×10−10Å if the gate region150is biased at −0.4 volts. Ioffis equal to 6.11×10−10Å if the gate region150is biased to 0 volt. The Ioffcan be reduced by as much as 50% with proper biasing of the gate region150.

FIG. 14is a simplified diagram showing measured drain current as a function of gate biases at high drain voltage for split dual gate field effect transistor according to yet another embodiment of the present invention. This diagram is merely an example, which should not unduly limit the scope of the claims. One of ordinary skill in the art would recognize many variations, alternatives, and modifications.

For example, the split dual gate field effect transistor is the device100. A horizontal axis1402represents the voltage applied to the gate region140, and a vertical axis1404represents the drain current. The drain region130is biased to 1.8 volts, and the source region120and the bottom surface114are grounded. The total width of the width148, the width158, and the width168is equal to about 10 μm, and each of the lengths146and156is equal to about 0.18 μm. Z1and Z3are substantially equal, and Z2is equal to about 8×Z1. For the curves1410, the gate region150is biased to 0, −0.1, −0.2, −0.3, −0.4, and −0.5 volts respectively. As shown inFIG. 14, Ioffis equal to 4.28×10−11A if the gate region150is biased at −0.5 volts. Ioffis equal to 1.77×10−10A if the gate region150is biased to 0 volt. The Ioffcan be reduced by as much as 75% with proper biasing of the gate region150.

FIG. 15is a simplified diagram showing measured drain current as a function of drain bias for split dual gate field effect transistor according to an embodiment of the present invention. This diagram is merely an example, which should not unduly limit the scope of the claims. One of ordinary skill in the art would recognize many variations, alternatives, and modifications.

For example, the split dual gate field effect transistor is the device100. Horizontal axes1502and1512each represent the voltage applied to the drain region130, and vertical axes1504and1514each represent the drain current. The source region120and the bottom surface114are grounded. The total width of the width148, the width158, and the width168is equal to about 10 μm, and each of the lengths146and156is equal to about 0.18 μm. For curves1520, the gate region150is biased to 0 volts, and for curves1530, the gate region150is biased to 1.8 volts. The curves1520correspond to 1.8, 1.2, 0.6, and 0 volt respectively, which are applied to the gate region140. Additionally, the curves1530correspond to 1.8, 1.2, 0.6, and 0 volt respectively, which are applied to the gate region140.

FIG. 16is a simplified diagram showing measured sub-threshold swing as a function of gate bias for split dual gate field effect transistor according to an embodiment of the present invention. This diagram is merely an example, which should not unduly limit the scope of the claims. One of ordinary skill in the art would recognize many variations, alternatives, and modifications.

For example, the split dual gate field effect transistor is the device100. In another example, the split dual gate field effect transistor is an n-channel transistor. A horizontal axis1602represents the voltage applied to the gate region140, and a vertical axis1604represents the sub-threshold swing. The drain region130is biased to 1.8 volts, and the source region120and the bottom surface114are grounded. The total width of the width148, the width158, and the width168is equal to about 10 μm, and each of the lengths146and156is equal to about 0.18 μm. Z1and Z3are substantially equal, and Z2is equal to about 8×Z1. For curve1610, the gate region150is biased to 0 volt. The two independent gate biases for the gate regions140and150can modulate the threshold voltage, and provide dynamical control on device characteristics. For example, the device characteristics include the threshold voltage and the sub-threshold swing.

According to another embodiment, a semiconductor device with at least two gate regions includes a substrate region including a surface, a source region in the substrate region, and a drain region in the substrate region. The drain region and the source region are separate from each other. Additionally, the device includes a first gate region on the surface, a second gate region on the surface, and an insulation region on the surface and between the first gate region and the second gate region. The first gate region and the second gate region are separated by the insulation region. The first gate region is capable of forming a first channel in the substrate region. The first channel is from the source region to the drain region. The second gate region is capable of forming a second channel in the substrate region. The second channel is from the source region to the drain region. For example, the device is implemented according to the device100.

According to yet another embodiment, a semiconductor transistor with at least two gate regions includes a substrate region including a surface, a source region in the substrate region, and a drain region in the substrate region. The drain region and the source region are separate from each other. Additionally, the transistor includes a first gate region on the surface, a second gate region on the surface, and an insulation region on the surface and between the first gate region and the second gate region. Moreover, the transistor includes a first spacer region. The first spacer region is in contact with the first gate region, the second gate region, and the insulation region. Also, the transistor includes a second spacer region. The second spacer region is in contact with the first gate region, the second gate region, and the insulation region. The first gate region and the second gate region are separated by the insulation region. The first gate region is capable of forming a first channel from the source region to the drain region in the substrate region, and the second gate region is capable of forming a second channel from the source region to the drain region in the substrate region. The first channel and the second channel are not in contact to each other. For example, the transistor is implemented according to the device100.

According to yet another embodiment, a transistor with at least two gate regions includes a substrate region including a surface, a source region in the substrate region, and a drain region in the substrate region. The drain region and the source region are separate from each other. Additionally, the transistor includes a first gate region on the surface, a second gate region on the surface, and an insulation region on the surface and between the first gate region and the second gate region. Moreover, the transistor includes a first spacer region. The first spacer region is in contact with the first gate region, the second gate region, and the insulation region. Also, the transistor includes a second spacer region. The second spacer region is in contact with the first gate region, the second gate region, and the insulation region. The first gate region and the second gate region are separated by the insulation region. The first gate region is capable of forming a first channel from the source region to the drain region in the substrate region, and the second gate region is capable of forming a second channel from the source region to the drain region in the substrate region. The first channel and the second channel are not in contact to each other. The first channel is associated with a first channel length, the first channel length being equal to or shorter than 200 nm. The insulation region is associated with a width in a direction from the first gate region to the second gate region, and the width ranges from 10 nm to 10,000 nm. For example, the device is implemented according to the device100.

FIG. 17is a simplified method for making split dual gate field effect transistor according to an embodiment of the present invention. This diagram is merely an example, which should not unduly limit the scope of the claims herein. The method2100includes the following processes:1. Process2110for forming shallow trench isolation;2. Process2115for forming doped well;3. Process2120for forming gate region for splitting;4. Process2125for forming LDD region and spacer region;5. Process2130for forming heavily doped source region and heavily doped drain region;6. Process2135for forming split dual gates;7. Process2140for forming salicide layer and insulation layer;8. Process2145for forming inter-layer dielectric layer;9. Process2150for forming contact layer;10. Process2155for forming metal layer;11. Process2160for forming passivation layer.

The above sequence of processes provides a method according to an embodiment of the present invention. Other alternatives can also be provided where processes are added, one or more processes are removed, or one or more processes are provided in a different sequence without departing from the scope of the claims herein. For example, the split dual gate field effect transistor made by the method2100is the device100. Future details of the present invention can be found throughout the present specification and more particularly below.

At the process2110, one or more shallow trench isolations are formed.FIGS. 18(A)and (B) show a simplified method for forming shallow trench isolation for making split dual gate field effect transistor according to an embodiment of the present invention. These diagrams are merely examples, which should not unduly limit the scope of the claims. One of ordinary skill in the art would recognize many variations, alternatives, and modifications.

As shown inFIGS. 18(A)and (B), a starting semiconductor wafer2210is provided. For example, the starting wafer2210includes silicon. In another example, the starting wafer2210includes a substrate region. On the starting wafer2210, a silicon oxide layer2220, a silicon nitride layer2230, and a silicon oxynitride layer are formed sequentially. Additionally, a trench2240is formed by etching part of the silicon oxynitride layer, the silicon nitride layer2230, the silicon oxide layer2220, and the starting wafer2210. The bottom surface and side surfaces of the trench2240are covered by an oxide layer2250. Afterwards, the trench is filled by an oxide material2260. For example, the oxide material2260includes high density plasma (HDP) CVD oxide.

At the process2115, one or more doped wells are formed.FIG. 19shows a simplified method for forming doped well for making split dual gate field effect transistor according to an embodiment of the present invention. This diagram is merely an example, which should not unduly limit the scope of the claims. One of ordinary skill in the art would recognize many variations, alternatives, and modifications.

As shown inFIG. 19, the silicon oxynitride layer, the silicon nitride layer2230, and the silicon oxide layer2220are removed from the wafer2210. On the wafer2210, another oxide layer2310is formed. Afterwards, in one example, an n-well is formed in the wafer2210. Additionally, an anti-punch-through ion implantation is performed with p-type dopants, and a threshold-adjustment ion implantation is performed also with p-type dopants. In another example, a p-well is formed in the wafer2210. Additionally, an anti-punch-through ion implantation is performed with n-type dopants, and a threshold-adjustment ion implantation is performed also with n-type dopants.

At the process2120, one or more gate regions are formed for splitting.FIGS. 20(A)and (B) show a simplified method for forming gate region for splitting for making split dual gate field effect transistor according to an embodiment of the present invention. These diagrams are merely examples, which should not unduly limit the scope of the claims. One of ordinary skill in the art would recognize many variations, alternatives, and modifications.

As shown inFIGS. 20(A)and (B), the oxide layer2310is removed, and another oxide layer2410is deposited on the wafer2210. On the oxide layer2410, a polysilicon layer2420is formed. Afterwards, the polysilicon layer2420is partially etched to form polysilicon gate regions2430and2432. The polysilicon gate regions2430and2432are then partially oxidized under certain conditions.

At the process2125, one or more LDD regions and one or more spacer regions are formed.FIG. 21shows a simplified method for forming LDD region and spacer region for making split dual gate field effect transistor according to an embodiment of the present invention. This diagram is merely an example, which should not unduly limit the scope of the claims. One of ordinary skill in the art would recognize many variations, alternatives, and modifications.

As shown inFIG. 21, one or more ion implantation processes are performed to form one or more LDD regions. For example, the LDD regions2510and2520are p-type doped for PMOS. In another example, the LDD regions2530and2540are n-type doped for NMOS. Additionally, one or more spacers are formed. For example, each of the spacers2550,2560,2570, and2580includes a nitride layer sandwiched between two oxide layers.

At the process2130, one or more heavily doped source regions and one or more heavily doped drain regions are formed.FIG. 22shows a simplified method for forming heavily doped source region and heavily doped drain region for making split dual gate field effect transistor according to an embodiment of the present invention. This diagram is merely an example, which should not unduly limit the scope of the claims. One of ordinary skill in the art would recognize many variations, alternatives, and modifications.

As shown inFIG. 22, one or more ion implantation processes are performed to form one or more heavily doped source regions and heavily doped drain regions. For example, the formed regions2610and2620are doped to p+ for PMOS. In another example, the formed regions2630and2640are doped to n+ for NMOS.

At the process2135, split dual gates are formed.FIGS. 23(A), (B), and (C) show a simplified method for forming split dual gates for making split dual gate field effect transistor according to an embodiment of the present invention.FIG. 23(B)is a simplified cross-section along B and B′, andFIG. 23(C)is a simplified cross-section along C and C′. These diagrams are merely examples, which should not unduly limit the scope of the claims. One of ordinary skill in the art would recognize many variations, alternatives, and modifications.

As shown inFIGS. 23(A), (B), and (C), part of the polysilicon gate region2430is removed. As a result, dual gate regions2710and2720are formed. Additionally, the dual gate regions2710and2720are separated by a gap2730, such an air gap. In another example, similar dual gate regions are formed by removing part of the polysilicon gate region2432.

At the process2140, one or more salicide layers are formed.FIGS. 24(A), (B), and (C) show a simplified method for forming salicide layer and insulation layer for making split dual gate field effect transistor according to an embodiment of the present invention.FIG. 24(B)is a simplified cross-section along B and B′, andFIG. 24(C)is a simplified cross-section along C and C′. These diagrams are merely examples, which should not unduly limit the scope of the claims. One of ordinary skill in the art would recognize many variations, alternatives, and modifications.

As shown inFIGS. 24(A), (B), and (C), salicide layers2810and2820are formed on the dual gate regions2710and2720. Additionally, at least salicide layers2812and2814are formed on the wafer2210. Additionally, within the gap2730, an insulation layer2822is formed. For example, the insulation layer2822includes a salicide block layer (SAB), such as an silicon-rich oxide layer. In another example, the insulation layer2822includes an insulation material, such as silicon oxide, silicon nitride, and/or silicon oxynitride. In yet another example, the insulation layer2822and the remaining part of the gap2730form an insulation region that separates the dual gate regions2710and2720. In yet another example, similar salicide layers and insulation layer are formed for dual gate regions made from the polysilicon gate region2432.

In another embodiment, to form the insulation layer2822, a photolithography is performed to pattern the SAB layer. The SAB photo mask is aligned to Active Area (AA) layer mark, for example, OVERLAY SAB/AA=±0.07 μm. After the photolithography, the SAB layer is etched by plasmas dry etch and then wet etch. For example, the wet etch process uses the chemical 49% HF: H2O (1:100) solvent at the temperature of 22.5° C.˜23.5° C. for 270 seconds.

At the process2145, one or more inter-layer dielectric layer is formed.FIG. 25shows a simplified method for forming inter-layer dielectric layer for making split dual gate field effect transistor according to an embodiment of the present invention. This diagram is merely an example, which should not unduly limit the scope of the claims. One of ordinary skill in the art would recognize many variations, alternatives, and modifications.

As shown inFIG. 25, a silicon oxynitride layer2910is formed to cover at least part of the structure that results from the process2140. Additionally, a BPSG layer2920is deposited on the silicon oxynitride layer2910and undergoes a reflow process. On the BPSG layer2920, an oxide layer2930is formed and planarized by a CMP process.

At the process2150, one or more contact layers are formed.FIG. 26shows a simplified method for forming contact layer for making split dual gate field effect transistor according to an embodiment of the present invention. This diagram is merely an example, which should not unduly limit the scope of the claims. One of ordinary skill in the art would recognize many variations, alternatives, and modifications.

As shown inFIG. 26, one or more contact holes are formed. For example, contact holes3010and3020expose the salicide layer2814and the salicide layer on the polysilicon gate region2432. In one embodiment, the polysilicon gate region2432is etched to become dual gate regions at the process2135. In another embodiment, the polysilicon gate region2432is not etched to become dual gate regions at the process2135. In the contact holes, a layer3030is formed to cover the bottom surfaces and side surfaces. For example, the layer3030includes Ti and TiN. Afterwards, the contact holes are filled by tungsten material3040.

At the process2155, one or more metal layers are formed.FIGS. 27(A)and (B) show a simplified method for forming metal layer for making split dual gate field effect transistor according to an embodiment of the present invention. These diagrams are merely examples, which should not unduly limit the scope of the claims. One of ordinary skill in the art would recognize many variations, alternatives, and modifications.

As shown inFIGS. 27(A)and (B), one or more metal layers are formed. For example, a metal layer3110is in contact with the contact holes3010and3020filled with the tungsten material3040. In another example, at least one of the additional metal layers3120,3130,3140,3150, and3160are also formed. The different metal layers are separated by at least an inter-metal dielectric layer. The inter-metal dielectric layer is punched through to form one or more conductive plugs, which provide conductive connections between the metal layers.

In one embodiment, the following processes are performed to form a metal layer:METAL1Sputter (Ti/TiN/AlCu/Ti/TiN: THICKNESS 100 Å/200 Å/4KÅ/50 Å/300 Å) (for example, Ti for better TiO2adhesion; in another example, TiN to prevent TiAl3)ScrubberMETAL1_PHOTO DARC (320 Å SiON)ScrubberMETAL1PHOTO (0.22±0.015)METAL1ETCH (0.24±0.02)

At the process2160, one or more passivation layers are formed.FIG. 28shows a simplified method for forming passivation layer for making split dual gate field effect transistor according to an embodiment of the present invention. This diagram is merely an example, which should not unduly limit the scope of the claims. One of ordinary skill in the art would recognize many variations, alternatives, and modifications.

As shown inFIG. 28, one or more passivation layers are formed. For example, an oxide layer3210is formed on at least a metal layer, such as the metal layer3160. In another example, a nitride layer3220is also formed on the oxide layer3210.

In one embodiment, the following processes are performed to form a metal layer:Passivation HDP Oxide DEPOSITION 10 KÅPassivation Nitride DEPOSITION 6 KÅ

FIGS. 29(A)and (B) show a simplified method for making split dual gate field effect transistor according to another embodiment of the present invention. This diagram is merely an example, which should not unduly limit the scope of the claims herein. The method3300includes some or all of the 168 processes. AlthoughFIGS. 29(A)and (B) have been shown using a selected sequence of processes, there can be many alternatives, modifications, and variations. For example, some of the processes may be expanded and/or combined. Other processes may be inserted to those noted above. Depending upon the embodiment, the specific sequence of processes may be interchanged with others replaced. Some of the processes may be expanded and/or combined, and/or other processes may be inserted to those noted above. For example, the split dual gate field effect transistor made by the method3300is the device100.

The present invention has various advantages. Some embodiments of the present invention provide a new planar split dual gate transistor device. Certain embodiments of the present invention provide dual gates that can be biased independently. For example, the independent gate biases can provide dynamical control of the device characteristics such as threshold voltage, sub-threshold swing, and/or the saturation drain current. Some embodiments of the present invention can significantly reduce transistor leakage current. For example, the reduction can reach about 67%. In another example, the reduction can reach about 75%. Certain embodiments of the present invention can provide adjustable threshold voltage without varying gate oxide thickness or doping profile. Some embodiments of the present invention provide an energy band that varies along all three dimensions.