MAGNETORESISTIVE RANDOM ACCESS MEMORY DEVICES AND METHODS OF MANUFACTURING THE SAME

In a method of manufacturing an MRAM device, a lower electrode, a first pinning layer pattern, a tunnel barrier layer pattern and a free layer pattern sequentially stacked on a substrate may be formed. A first insulating interlayer may be formed on the substrate to cover the lower electrode, the first pinning layer pattern, the tunnel barrier layer pattern and the free layer pattern. The first insulating interlayer may be etched to form a recess exposing a top surface of the free layer pattern. A second pinning layer pattern may be formed to fill at least a portion of the recess. A wiring may be formed on the second pinning layer pattern.

BACKGROUND

Example embodiments relate to magnetoresistive random access memory (MRAM) devices and methods of manufacturing the same.

2. Description of the Related Art

An MRAM device is a non-volatile memory device, and may include a magnetic tunnel junction (MTJ) structure. The MTJ structure may include a fixed layer pattern structure, a tunnel barrier layer pattern and a free layer pattern sequentially stacked, which may be formed by a physical etching process such as ion sputtering. However, a magnetic material of the fixed layer pattern structure may be re-sputtered during the physical etching process, so as to be attached onto a sidewall of the MTJ structure. Thus, the MTJ structure may be deteriorated.

SUMMARY

Example embodiments provide an MRAM device having good electrical characteristics.

Example embodiments provide a method of manufacturing an MRAM device having good electrical characteristics.

According to example embodiments, there is provided a method of manufacturing an MRAM device. In the method, a lower electrode, a first pinning layer pattern, a tunnel barrier layer pattern and a free layer pattern sequentially stacked on a substrate may be formed. A first insulating interlayer may be formed on the substrate to cover the lower electrode, the first pinning layer pattern, the tunnel barrier layer pattern and the free layer pattern. The first insulating interlayer may be etched to form a recess exposing a top surface of the free layer pattern. A—second pinning layer pattern may be formed to fill at least a portion of the recess. A wiring may be formed on the second pinning layer pattern.

In example embodiments, the second pinning layer pattern may be formed to have a thickness thicker than the thickness of the first pinning layer pattern.

In example embodiments, the first and second pinning layer patterns may have magnetization directions that are opposite to each other.

In example embodiments, the recess may extend in one direction, and the wiring may be formed on the second pinning layer pattern to fill a remaining portion of the recess.

In example embodiments, when the wiring is formed, an upper portion of the first insulating interlayer may be planarized until a top surface of the first insulating interlayer is coplanar with a top surface of the second pinning layer pattern. A second insulating interlayer having an opening, which may expose the top surface of the second pinning layer pattern and extend in one direction, may be formed on the planarized first insulating interlayer. The wiring may be formed to fill the opening.

In example embodiments, when the lower electrode, the first pinning layer pattern, the tunnel barrier layer pattern and the free layer pattern are formed, a lower electrode layer, a first pinning layer, a tunnel barrier layer, a free layer and a hard mask may be sequentially formed on the substrate. The free layer, the tunnel barrier layer, the first pinning layer and the lower electrode layer may be sequentially patterned using the hard mask as an etching mask.

In example embodiments, after patterning the free layer, the tunnel battier layer, the first pinning layer and the lower electrode layer, a first spacer may be formed to surround sidewalls of the lower electrode, the first pinning layer pattern, the tunnel barrier layer pattern and the free layer pattern.

In example embodiments, when the lower electrode, the first pinning layer pattern, the tunnel barrier layer pattern and the free layer pattern are formed, the lower electrode and the first pinning layer pattern may be sequentially stacked on the substrate. A third insulating interlayer may be formed to surround the sidewalls of the lower electrode and the first pinning layer pattern. A tunnel barrier layer, a free layer and the hard mask may be formed on the third insulating interlayer and the first pinning layer pattern. The free layer and the tunnel barrier layer may be sequentially patterned using the hard mask as an etching mask.

In example embodiments, after patterning the free layer and the tunnel barrier layer, a second spacer may be formed on the third insulating interlayer to surround the sidewalls of the free layer pattern and the tunnel barrier layer pattern.

According to example embodiments, an MRAM device is provided. The MRAM device may include a lower electrode, a MTJ structure and a wiring sequentially stacked on the substrate. The MTJ structure may be formed to include a first pinning layer pattern having a first thickness, a tunnel barrier layer pattern, a free layer pattern, a second pinning layer pattern having a second thickness sequentially stacked on the lower electrode. The second thickness may be thicker than the first thickness.

In example embodiments, the wiring may extend in a direction.

In example embodiments, the second pinning layer pattern may extend in the same direction as the direction of the wiring.

In example embodiments, the first and second pinning layer patterns may have magnetization directions that are opposite to each other.

In example embodiments, the wiring may contact a top surface of the MTJ structure.

In example embodiments, the MRAM device may further comprise a spacer covering at least sidewalls of the tunnel barrier layer pattern and the free layer pattern,

According to example embodiments, the MTJ structure may be formed by the following steps. A lower electrode, a first pinning layer pattern, a tunnel barrier layer pattern and a free layer pattern may be sequentially formed on a substrate by a physical etching process. A second pinning layer pattern may be formed on the free layer pattern by a damascene process or a physical etching process. A wiring contacting the second pinning layer pattern may be formed thereon. Thus, a height of the layers, which may be patterned at each physical etching process, may be minimized when the MTJ structure is formed, and thus an attachment of a magnetic material onto a sidewall of the MTJ structure may be reduced.

Moreover, the first and second pinning layer patterns, which have magnetization directions that are substantially opposite to each other, may be formed beneath and above the free layer pattern, respectively, and thus an upper electrode may not be formed on the free layer pattern, and the deterioration of magnetic characteristics of the MRAM device including the MTJ structure may be reduced, or alternatively prevented. Example embodiments also related to a method of manufacturing a magnetoresistive random access memory (MRAM) device including forming a lower electrode on a substrate, forming a material tunnel junction (MTJ) structure, forming a hard mask on the MTJ structure, patterning the MTJ structure and the lower electrode by using the hard mask, forming a first insulating interlayer on the substrate and the patterned lower electrode, MTJ structure and hard mask, etching the first insulating interlayer to form a first recess exposing a surface of the MTJ structure, forming a second pinning layer pattern to fill at least a portion of the recess, and forming a wiring on the second pinning layer pattern.

DESCRIPTION OF EXAMPLE EMBODIMENTS

In the drawing figures, the dimensions of layers and regions may be exaggerated for clarity of illustration. Like reference numerals refer to like elements throughout. The same reference numbers indicate the same components throughout the specification.

FIG. 1is a cross-sectional view illustrating an MRAM device in accordance with example embodiments.

Referring toFIG. 1, the MRAM device may include a transistor having a lower electrode225, a first magnetic tunnel junction (MTJ) structure401and a wiring360.

The transistor may include a gate structure140on a substrate100and an impurity region160at an upper portion of the substrate100adjacent to the gate structure140. The gate structure140may include a gate insulation layer pattern110, a gate electrode120and a mask130sequentially stacked on the substrate100, and a first spacer150may surround a sidewall of the gate structure140.

The gate insulation layer pattern110may include an oxide, e.g., silicon oxide. The gate electrode120may include a conductive material, e.g., a metal such as tungsten (W) and/or polysilicon doped with impurities. The mask130and the first spacer150may include a nitride, e.g., silicon nitride.

The impurity region160may include, e.g., n-type impurities such as phosphorus, arsenic, etc., or p-type impurities such as boron, gallium, etc., and may serve as source/drain regions of the transistor.

The substrate100may include an isolation layer pattern105thereon. Accordingly, a portion of the substrate100on which the isolation layer pattern105is formed may be defined as a field region, a portion of the substrate100on which no isolation layer pattern is formed may be defined as an active region. The transistor may be formed in the active region. The substrate100may be a silicon substrate, a germanium substrate, a silicon-germanium substrate, a silicon-on-insulator (SOI) substrate, a germanium-on-insulator (GOI) substrate, etc. The isolation layer pattern105may include an oxide, e.g., silicon oxide.

A first insulating interlayer170formed on the substrate100may cover the transistor, and first and second contact plugs181and183may be formed through the first insulating interlayer170to contact top surfaces of the impurity region160. First and second pads191and193may be formed on the first insulating interlayer170to contact top surfaces of the first and second contact plugs181and183, respectively. A second insulating interlayer200formed on the first insulating interlayer170and may cover the first and second pads191and193. A third contact plug210may be formed through the second insulating interlayer200to contact a top surface of the first pad191.

The first and second insulating interlayers170and200may include an oxide, e.g., silicon oxide. The first and second pads191and193may include a conductive material, e.g., a metal. The first to third contact plugs181,183and210may include a conductive material, e.g., a metal and/or polysilicon doped with impurities.

The lower electrode225may be formed on the second insulating interlayer200to contact a top surface of the third contact plug210. The lower electrode225may include a conductive material, e.g., a metal such as tungsten (W), titanium (Ti), tantalum (Ta) and/or a metal nitride such as tungsten nitride (WN), titanium nitride (TiN), tantalum nitride (TaN). In example embodiments, the lower electrode225may extend in a first direction substantially parallel to a top surface of the substrate100, and a plurality of lower electrodes225may be formed in a second direction substantially parallel to the top surface of the substrate100and substantially perpendicular to the first direction.

The first MTJ structure401may include a first pinning layer pattern235, a first tunnel barrier layer pattern245, a free layer pattern255, a second tunnel barrier layer pattern265, a capping layer pattern275and a second pinning layer pattern310sequentially stacked on the lower electrode225.

The first pinning layer pattern235may contact the lower electrode225and has a first thickness, and the second pinning layer pattern310may have a second thickness thicker than the first thickness. The first and second pinning layer patterns235and310may have first and second magnetization directions, respectively. In example embodiments, the first and second magnetization directions may be substantially perpendicular to the top surface of the substrate100or substantially parallel to the top surface of the substrate100. The first and second magnetization directions may be substantially opposite to each other. The first and second thicknesses may not be limited and can be changed easily according to the first MTJ structure401. In example embodiments, a plurality of first pinning layer patterns235and a plurality of second pinning layer patterns310may be formed in the first and second directions.

The free layer pattern255may include a ferromagnetic material, e.g. iron (Fe), nickel (Ni), cobalt (Co), etc. In example embodiments, the free layer pattern255may have a third magnetization direction, which may be substantially perpendicular to the top surface of the substrate100or parallel to the top surface of the substrate100. In one example embodiment, the third magnetization direction may be substantially the same as the first magnetization direction, and substantially opposite to the second magnetization direction. In example embodiments, a plurality of free layer patterns255may be formed in the first and second directions.

The first and second tunnel barrier layer pattern245and265may include a metal oxide, a metal nitride, a metal oxynitride, e.g., magnesium oxide (MgO) or aluminum oxide (AIO). In example embodiments, a plurality of first tunnel barrier layer patterns245and a plurality of second tunnel barrier layer patterns265may be formed in the first and second directions.

The capping layer pattern275may include a metal e.g., tantalum (Ta). In example embodiments, a plurality of capping layer patterns275may be formed in the first and second directions.

A second spacer295may surround sidewalls of the first pinning layer pattern235, the first tunnel barrier layer pattern245, the free layer pattern255, the second tunnel barrier layer pattern265and the capping layer pattern275. The second spacer295may be formed on the second insulating interlayer200so as to also surround a sidewall of the lower electrode225. The second pinning layer pattern310may contact top surfaces of the capping layer pattern275and the second spacer295. The second spacer295may include an oxide and/or a nitride, e.g., aluminum oxide (AlO2O3), silicon oxide or silicon nitride.

A third insulating interlayer300may surround a sidewall of the second pinning layer pattern310and an outer sidewall of the second spacer295. The third insulating interlayer300may include an oxide, e.g., silicon oxide.

The wiring360may be formed on the second pinning layer pattern310to contact a top surface thereof. The wiring360may include a metal layer pattern350and a barrier layer pattern340surrounding a bottom surface and a sidewall thereof. The metal layer pattern350may include, e.g., copper (Cu). The barrier layer pa340may include a metal or a metal nitride, e.g., tantalum (Ta), tantalum nitride (TaN), titanium (Ti), titanium nitride (TN). In example embodiments, a plurality of wirings360may be formed in the second direction, each of which may extend in the first direction.

A fourth insulating interlayer330on the third insulating interlayer300may surround a sidewall of the wiring360, and an etch stop layer320may be formed between the third and fourth insulating interlayers300and330. The fourth insulating interlayer330may include an oxide, e.g., silicon oxide, and the etch stop layer320may include a nitride, silicon nitride.

FIGS. 2 to 10are cross-sectional views illustrating a method of manufacturing an MRAM device in accordance with example embodiments.

Referring toFIG. 2, an isolation layer pattern105may be formed at an upper portion of a substrate100to divide the substrate100into an active region and a field region, and a transistor including a gate structure140and an impurity region160may be formed in the active region.

The isolation layer pattern105may be formed by forming a trench (not shown) at an upper portion of the substrate100, forming an isolation layer on the substrate100to sufficiently fill the trench, and planarizing an upper portion of the isolation layer until a top surface of the substrate100may be exposed. Accordingly, a portion of the substrate100on which the isolation layer pattern105is formed may be defined as the field region, and a portion of the substrate100on which no isolation layer pattern is formed may be defined as the active region. The isolation layer may include an oxide, e.g., silicon oxide.

The transistor may be formed by forming the gate structure140on the substrate100, forming a first spacer150on a sidewall of the gate structure140, and forming the impurity region160at an upper portion of the substrate100adjacent to the gate structure140and the first spacer150.

The gate structure140may be formed by sequentially forming agate insulation layer, agate electrode layer and a mask130, and sequentially patterning the gate electrode layer and the gate insulation layer using the mask130as an etching mask. Accordingly, the gate structure140may be formed to include a gate insulation layer pattern110, a gate electrode120and the mask130sequentially stacked on the substrate100.

The first spacer150may be formed by forming a first spacer layer on the substrate100to cover the gate structure140, and anisotropically etching the first spacer layer. The first spacer layer may be formed to include a nitride, e.g., silicon nitride.

The impurity region160may be formed by performing an ion implantation process on the substrate300to include, e.g., n-type impurities such as phosphorus, arsenic, etc., or p-type impurities such as boron, gallium, etc. The impurity region160may serve as source/drain regions of the transistor.

In some example embodiments, after the impurity region160may be formed, the gate structure140and the first spacer150may be formed to define the transistor.

Referring toFIG. 3, a first insulating interlayer170may be formed on the substrate100to cover the transistor, and first and second contact plugs181and183may be formed through the first insulating interlayer170to contact a top surface of the impurity region160.

The first and second contact plugs181and183may be formed via the following steps. The first insulating interlayer170may be etched to form first contact holes (not shown) exposing top surfaces of the impurity region160. A first conductive layer may be formed on the substrate100and the first insulating interlayer170to fill the first contact holes. An upper portion of the first conductive layer may be planarized until a top surface of the first insulating interlayer170may be exposed. The first conductive layer may be formed to include a metal and/or a polysilicon doped with impurities.

Thereafter, first and second pads191and193may be formed on the first insulating interlayer170to contact top surfaces of the first and second contact plugs181and183, respectively, and a second insulating interlayer200may be formed on the first insulating interlayer170to cover the first and second pads191and193. A third contact plug210may be formed through the second insulating interlayer200to contact a top surface of the first pad191.

The first and second pads191and193may be formed by forming a second conductive layer on the first insulating interlayer170, and patterning the second conductive layer. The second conductive layer may be formed to include, e.g., a metal.

The third contact plug210may be formed by the following steps. The second insulating interlayer200may be etched to form a second contact hole (not shown) exposing the top surface of the first pad191. A third conductive layer may be formed on the first pad191and the second insulating interlayer200to fill the second contact hole. An upper portion of the third conductive layer may be planarized until a top surface of the second insulating interlayer200may be exposed. The third conductive layer maybe formed to include a metal and/or a polysilicon doped with impurities.

The first insulating interlayer170may be formed to include an oxide, e.g., silicon oxide, and the second insulating interlayer200may be formed to include a nitride, e.g., silicon nitride.

Referring toFIG. 4, a lower electrode layer220, a first pinning layer230, a first tunnel barrier layer240, a free layer250, a second tunnel barrier layer260, a capping layer270and a hard mask layer280may be sequentially formed on the second insulating interlayer200.

The lower electrode layer220may be formed to include a conductive material, e.g., a metal such as tungsten (W), titanium (Ti), tantalum (Ta) and/or a metal nitride such as, tungsten nitride (WN), titanium nitride (TiN), tantalum nitride (TaN).

The first pinning layer230may be formed to include a ferromagnetic material having a first crystal structure, and thus may have a first magnetization direction. In example embodiments, the first magnetization direction may be substantially perpendicular to the top surface of the substrate100or substantially parallel to the top surface of the substrate100. The first pinning layer230may have a first thickness.

The free layer250may be formed to include a ferromagnetic material having a third magnetization direction, e.g., iron (Fe), nickel (Ni), cobalt (Co). In example embodiments, the third magnetization direction may be substantially perpendicular to the top surface of the substrate100or substantially parallel to the top surface of the substrate100. In one example embodiment, the third magnetization may be substantially the same as the first magnetization direction.

The first and second tunnel barrier layers240and260may be formed to include a metal oxide, a metal nitride or a metal oxynitride, e.g., magnesium oxide (MgO) or aluminum oxide (AIO).

The capping layer270may be formed to include, e.g., a metal such as tantalum (Ta).

The hard mask layer280may be formed to include, e.g., a metal and/or a metal nitride.

Referring toFIG. 5, the hard mask layer280may be etched to form a hard mask285, and the capping layer270, the second tunnel barrier layer260, the free layer250, the first tunnel barrier layer240, the first pinning layer230and the lower electrode layer220may be sequentially patterned using the hard mask as an etching mask. Accordingly, a lower electrode225, a first pinning layer pattern235, a first tunnel barrier layer pattern245, a free layer pattern255, a second tunnel barrier layer pattern265, and a capping layer pattern275, sequentially stacked on the second insulating interlayer200and the third contact plug210, may be formed, and the lower electrode225may contact a top surface of the third contact plug210.

In example embodiments, the patterning process may be performed by a physical etching process such as a plasma reaction etching process or an ion sputtering process. The plasma reaction etching process may be performed using an etching gas including, e,g., HF and/or NH3, and a reaction gas including, e.g., oxygen.

In example embodiments, a plurality of hard masks285may be formed in a first direction substantially parallel to the top surface of the substrate100, and in a second direction substantially parallel to the top surface of the substrate100and substantially perpendicular to the first direction. Thus, a plurality of lower electrodes225, a plurality of first pinning layer patterns235, a plurality of first tunnel barrier layer patterns245, a plurality of free layer patterns255, a plurality of second tunnel barrier layer patterns265and a plurality of capping layer patterns275may be formed in both the first and second directions.

Referring toFIG. 6, a second spacer layer290and a third insulating interlayer300may be sequentially formed on the second insulating interlayer200to cover the lower electrode225, the first pinning layer pattern235, the first tunnel barrier layer pattern245, the free layer pattern255, the second tunnel barrier layer pattern265, the capping layer pattern275and the hard mask285.

In one example embodiment, the third insulating interlayer300may have a top surface substantially higher than a top surface of the second spacer layer290on the hard mask285.

The second spacer layer290may include an oxide and/or a nitride, e.g., aluminum oxide (Al2O3), silicon oxide or silicon nitride. The third insulating interlayer300may include an oxide, e.g., silicon oxide.

Referring toFIG. 7, the third insulating interlayer300, the second spacer layer290and the hard mask285may be etched to form at least a first recess305. By the etching process, while the third insulating interlayer300and the second spacer layer290may be partially removed, the hard mask285may be substantially or entirely removed. Accordingly, a top surface of the capping layer pattern275may be exposed, and a second spacer295may be formed to surround sidewalls of the lower electrode225, the first pinning layer pattern235, the first tunnel barrier layer pattern245, the free layer pattern255, the second tunnel barrier layer pattern265and the capping layer pattern275.

The first recess305may be formed by forming an etching mask (not shown) on the third insulating interlayer300, and performing an anisotropic etching process using the etching mask. In example embodiments, a plurality of recesses305may be formed in the first and second directions.

Referring toFIG. 8, a second pinning layer pattern310may be formed to fill at least a portion of the first recess305. Accordingly, a plurality of second pinning layer patterns310may be formed in the first and second directions, each of which may contact the top surface of the capping layer pattern275. The second pinning layer pattern310, together with the first pinning layer pattern235, the first tunnel barrier layer pattern245, the free layer pattern255, the second tunnel barrier layer pattern265and the capping layer pattern275, may be defined as a first MTJ structure401.

In example embodiments, the second pinning layer pattern310may be formed by a damascene process. That is, a second pinning layer may be formed on the capping layer pattern275, the second spacer295and the third insulating interlayer300to substantially fill the first recess305, and an upper portion of the second pinning layer may be removed by an etch back process to form the second pinning layer pattern310. Accordingly, in some example embodiments, the second pinning layer pattern310may be formed to partially fill the first recess305as shown inFIG. 8. In other example embodiments, the second pinning layer pattern310may be formed to substantially fill the first recess305.

The second pinning layer pattern310may be formed to include a ferromagnetic material having a second crystal structure that is different from the first crystal structure, and thus may have a second magnetization direction that is substantially opposite to the first magnetization direction. In example embodiments, the second magnetization direction may be substantially perpendicular the top surface of the substrate100or substantially parallel to the top surface of the substrate100.

The second pinning layer pattern310may have a second thickness that is thicker than the first thickness. The first and second thicknesses may not be limited and may be changed easily according to the first MTJ structure401.

Referring toFIG. 9, an upper portion of the third insulating interlayer300may be planarized until a top surface of the third insulating interlayer300may be substantially coplanar with the top surface of the second pinning layer pattern310. An etch stop layer320and a fourth insulating interlayer330may be sequentially formed on the planarized third insulating interlayer300and the second pinning layer pattern310. The etch stop layer320may include a nitride, e.g., silicon nitride, and the fourth insulating interlayer330may include an oxide, e.g., silicon oxide.

When the second pinning layer pattern310substantially fills the first recess305, the planarizing process may be omitted.

Referring toFIG. 10, the fourth insulating interlayer330and the etch stop layer320may be partially removed to form at least a first opening335exposing the top surface of the second pinning layer pattern310.

The first opening335may be formed by forming an etching mask (not shown) on the fourth insulating interlayer330, etching the fourth insulating interlayer330using the etching mask to expose a portion of the etch stop layer320, and removing the exposed portion of the etch stop layer320. In example embodiments, a plurality of first openings335may be formed in the second direction, each of which may extend in the first direction perpendicularly to the second direction.

Referring toFIG. 1again, a wiring360may be formed on the second pinning layer pattern310to fill the first opening335.

The wiring360may be formed by the following steps. A harrier layer may be formed on the exposed top surface of the second pinning layer pattern310, a sidewall of the first opening335and the fourth insulating interlayer330. A metal layer may be formed on the barrier layer to fill a remaining portion of the first opening335. Upper portions of the barrier layer and of the metal layer may be planarized until a top surface of the fourth insulating interlayer330may be exposed. Accordingly, the wiring360may be formed to include a metal layer pattern350and a barrier layer pattern340that surrounds a bottom surface and a sidewall of the metal layer pattern350. The metal layer may include, e.g., copper (Cu) The barrier layer may include a metal or a metal nitride, e.g., tantalum (Ta), tantalum nitride (TaN), titanium (Ti), titanium nitride (TiN).

In example embodiments, a plurality of wirings360may be formed in the second direction, and each of which may also extend in the first direction.

As described above, when the first MTJ401structure is formed, the first pinning layer pattern235having a relatively small thickness may be formed by a physical etching process together with the lower electrode225, the first tunnel barrier layer pattern245, the free layer pattern255, the second tunnel barrier layer pattern265, the capping layer pattern275, and the second pinning layer pattern310having a relatively larger thickness may be formed by a damascene process. That is, the second pinning layer pattern310may not be formed together with the patterns of the first MTJ structure401thereunder by a physical etching process. Therefore, the attachment of a magnetic material onto a sidewall of the first MTJ structure401may be reduced, or alternatively prevented.

Moreover, the first and second pinning layer patterns235and310, which may have magnetization directions that are substantially opposite to each other, may be formed both beneath and above the free layer pattern255, respectively. As a result, an upper electrode may not be formed on the free layer pattern255, and the deterioration of magnetic characteristics of the MRAM device may be reduced, or alternatively prevented.

FIG. 11is a cross-sectional view illustrating an MRAM device in accordance with example embodiments. The MRAM device ofFIG. 11may be substantially the same as or similar to the device illustrated with reference toFIG. 1, except for having a third pinning layer pattern375. Thus, like reference numerals refer to like elements, and detailed explanations thereabout may be omitted herein.

Referring toFIG. 11, the MRAM device may include a transistor containing a gate structure140and an impurity region160, a lower electrode225, a second MTJ structure403and a wiring360. The MRAM device may further include first and second spacers150and295, first to third contact plugs181,183and210, first and second pads191and193and first to third insulating interlayers170,200and300.

The second MTJ structure403may include a first pinning layer pattern235, a first tunnel barrier layer pattern245, a free layer pattern255, a second tunnel barrier layer pattern265, a capping layer pattern275and the third pinning layer pattern375sequentially stacked on the lower electrode225.

The first and third pinning layer patterns235and375may include ferromagnetic materials having crystal structures different from each other, and thus may have magnetization directions that may be substantially opposite to each other. In example embodiments, the first and third pinning layer patterns235and375may have first and fourth magnetization directions, respectively, which may be substantially perpendicular to the top surface of the substrate100or substantially parallel to the top surface of the substrate100. The first and fourth magnetization directions may be substantially opposite to each other. The first pinning layer pattern235may contact the lower electrode235and have a first thickness, and the third pinning layer pattern375may have a third thickness that is larger than the first thickness. The first and third thicknesses may not be limited and may be changed easily according to the second MTJ structure403.

In example embodiments, a plurality of first pinning layer patterns235may be formed in a first direction that is substantially parallel to the top surface of the substrate100and in a second direction that is substantially parallel to the top surface of the substrate100and substantially perpendicular to the first direction. A plurality of third pinning layer patterns375may be formed in the second direction, each of which may extend in the first direction.

A plurality of free layer patterns255may be formed in the first and second directions. In example embodiments, the free layer pattern255may have a second magnetization direction, which may be substantially perpendicular to the top surface of the substrate100or substantially parallel to the top surface of the substrate100. In one example embodiment, the second magnetization direction may be substantially the same as the magnetization direction of the first pinning layer pattern235and substantially opposite to the magnetization direction of the third pinning layer pattern375.

In example embodiments, a plurality of first tunnel barrier layer patterns245, a plurality of second barrier layer patterns265and a plurality of capping layer patterns275may be formed in the first and second directions.

The second spacer295may surround the sidewalls of the first pinning layer pattern235, the first tunnel barrier layer pattern245, the free layer pattern255, the second tunnel barrier layer patterns265and the capping layer pattern275. The second spacer295may be formed on the second insulating interlayer295so as to also surround the sidewall of the lower electrode225. The third pinning layer pattern375may contact the top surfaces of the capping layer pattern275and the second spacer295.

The third insulating interlayer300may surround a sidewall of the third pinning layer pattern375, the sidewall of the wiring360and an outer sidewall of the second spacer295.

FIGS. 12 to 13are cross-sectional views illustrating a method of manufacturing an MRAM device in accordance with example embodiments. The method may include processes substantially the same as or similar to those illustrated with reference toFIGS. 2 to 10except for forming a third pinning layer pattern375. Thus, like reference numerals refer to like elements, and detailed explanations thereabout may be omitted herein.

First, processes substantially the same as or similar to those illustrated with reference toFIGS. 2 to 6may be performed. Thus, the transistor including the gate structure140and the impurity region160, the first to third contact plugs181,183and210, the first and second pads191and193, and the first and second insulating interlayers170and200may be formed. In addition, the lower electrode225, the first pinning layer pattern235, the first and second tunnel barrier layer patterns245and265, the free layer pattern255, the capping layer pattern275and the hard mask285may be formed, and the third insulating interlayer300may be formed to cover the lower electrode225, the first pinning layer pattern235, the first and second tunnel barrier layer patterns245and265, the free layer pattern255, the capping layer pattern275and the hard mask285.

Referring toFIG. 12, the third insulating interlayer300, the second spacer layer290and the hard mask285may be etched to form at least a second recess307. By the etching process, the third insulating interlayer300and the second spacer layer290may be partially removed, and the hard mask285may be sufficiently removed. Accordingly, a top surface of the capping layer pattern275may be exposed, and a second spacer295may be formed to surround sidewalls of the lower electrode225, the first pinning layer pattern235, the first tunnel barrier layer pattern245, the free layer pattern255, the second tunnel barrier layer pattern265and the capping layer pattern275. In example embodiments, the second recess307may extend in a first direction that is substantially parallel to the top surface of the substrate100, and a plurality of second recesses307may be formed in a second direction that is substantially parallel to the top surface of the substrate100and substantially perpendicular to the first direction.

Referring toFIG. 13, the third pinning layer pattern375may be formed to fill at least a portion of the second recess307. Accordingly, the third pinning layer pattern375may contact the top surfaces of the capping layer pattern275and the second spacer295. In example embodiments, a plurality of third pinning layer patterns375may be formed in the second direction, each of which may extend in the first direction. The third pinning layer pattern375, together with the first pinning layer pattern235, the first tunnel barrier layer pattern245, the free layer pattern255, the second barrier layer pattern265and the capping layer pattern275, may be defined as a second MTJ structure403.

In example embodiments, the third pinning layer pattern375may be formed by a damascene process. That is, a third pinning layer may be formed on the second spacer295and the third insulating interlayer300to fill the second recess307, and an upper portion of the laird pinning layer may be removed by an etch back process.

Alternatively, the second recess307may be only partially filled by a damascene process to form the third pinning layer pattern375, and in this case, the etch back process may be omitted.

The third pinning layer pattern375may be formed to include a ferromagnetic material having a third crystal structure substantially different from the crystal structure of the first pinning layer pattern235. Accordingly, the third pinning layer pattern375may have a fourth magnetization direction that is substantially opposite to the magnetization direction of the first pinning layer pattern235. In example embodiments, the fourth magnetization direction may be substantially perpendicular to the top surface of the substrate100or substantially parallel to the top surface of the substrate100.

The third pinning layer pattern375may have a third thickness that is greater than the first thickness of the first pinning layer pattern235. The first and third thicknesses may not be limited but be changed easily according the second MTJ structure403.

Referring toFIG. 11again, processes substantially the same as or similar to those illustrated with reference toFIG. 1may be performed to form the wiring360filling a remaining portion of the second recess307. Accordingly, the wiring360may contact a top surface of the third pinning layer pattern375. In example embodiments, a plurality of wirings360may be formed in the second direction, each of which may extend in the first direction. The wiring360may be formed to include a metal layer pattern350and a barrier layer pattern340surrounding a bottom surface and a sidewall of the metal layer pattern350.

As described above, when the second MTJ403structure is formed, the first pinning layer pattern235having a relatively small thickness may be formed by a physical etching process together with the lower electrode225, the first tunnel barrier layer pattern245, the free layer pattern255, the second tunnel barrier layer pattern265and the capping layer pattern275, and the third pinning layer pattern375having a relatively larger thickness may be formed by a damascene process.

Particularly, the third pinning layer pattern375and the wiring360may be formed in the same recess to fill lower and upper portions thereof, respectively, and thus the present inventive concepts may have the advantage of simplification.

FIGS. 14 to 16are cross-sectional views illustrating a method of manufacturing an MRAM device in accordance with example embodiments. The method may include processes substantially the same as or similar to those illustrated with toFIGS. 2 to 10except for forming a third pinning layer pattern375. Thus, like reference numerals refer to like elements, and detailed explanations thereabout may be omitted herein.

First, processes substantially the same as or similar to those illustrated with reference toFIGS. 2 to 6may be performed. Thus, the transistor including the gate structure140and the impurity region160, the first to third contact plugs181,183and210, the first and second pads191and193and the first and second insulating interlayers170and200may be formed. In addition, the lower electrode225, the first pinning layer pattern235, the first and second tunnel barrier layer patterns245and265, the free layer pattern255, the capping layer pattern275and the hard mask285may be formed, and the third insulating interlayer300may be formed to cover the lower electrode225, the first pinning layer pattern235, the first and second tunnel barrier layer patterns245and265, the free layer pattern255, the capping layer pattern275and the hard mask285.

Referring toFIG. 14, upper portions of the second spacer layer295and third insulating interlayer300may be planarized until a top surface of the capping layer pattern275may be exposed. By the planarizing process, the hard mask285may be substantially removed, and a second spacer295may be formed to surround the sidewalls of the lower electrode225, the first pinning layer pattern235, the first tunnel barrier layer pattern245, the free layer pattern255, the second tunnel barrier layer pattern265and the capping layer pattern275.

Thereafter, a third pinning layer370may be formed on the planarized third insulating interlayer300, the second spacer295and the capping layer pattern275.

The third pinning layer370may be formed to include a ferromagnetic material having a third crystal structure that is substantially different from the crystal structure of the first pinning layer pattern235.Accordingly, the third pinning layer370may have a fourth magnetization direction that is substantially opposite to the first magnetization direction. In example embodiments, the fourth magnetization direction may be substantially perpendicular to the top surface of the substrate100or substantially parallel to the top surface of the substrate100.

The third pinning layer370may have a third thickness that is larger than the thickness of the first pinning layer pattern235. The first and third thicknesses may not be limited but be changed easily according to the second MTJ structure403.

Referring toFIG. 15, the third pinning layer370may be patterned to form a third pinning layer pattern375contacting the top surface of the capping layer pattern275. By the patterning process, the third pinning layer pattern375may extend in a first direction that is substantially parallel to the top surface of the substrate, and a plurality of third pinning layer patterns375may be formed in a second direction that is substantially parallel to the top surface of the substrate100and substantially perpendicular to the first direction.

In example embodiments, the patterning process may be performed by a physical etching process such as a plasma reaction etching process or an ion sputtering process. The plasma reaction etching process may be performed using an etching gas including, e.g., HF and/or NH3, and a reaction gas including, e.g., oxygen.

Referring toFIG. 16, a fifth insulating interlayer380may be formed on the third insulating interlayer300and the third pinning layer pattern375to sufficiently cover the third pinning layer pattern375, and the fifth insulating interlayer380may be etched to form at least a second opening385exposing a top surface of the third pinning layer pattern375. By the etching process, a plurality of second openings385may be formed in the second direction, each of which may extend in the first direction.

The fifth insulating interlayer380may be formed to include a material that is substantially the same as the material of the third insulating interlayer300. That is, the fifth insulating interlayer380may be formed to include an oxide, e.g., silicon oxide, and thus may be merged to the third insulating interlayer300. Thus, hereinafter, the merged layer structure may be referred to simply as the third insulating interlayer300.

Thereafter, processes substantially the same as or similar those illustrated with reference toFIG. 1may be performed. That is, the wiring360contacting the top surface of the third pinning layer pattern375and tilling the second opening385may be formed. As a result, the MRAM device may be manufactured as shown inFIG. 11.

As described above, after the lower electrode225, the first pinning layer pattern235, the first tunnel barrier layer pattern245, the free layer pattern255, the second tunnel barrier layer pattern265and the capping layer pattern275may be formed by a first physical etching process, the third pinning layer pattern375may be formed by a second physical etching process to form the second MTJ structure403. That is, the first and third pinning layer patterns235and375may be formed by independent physical etching processes, respectively, and thus a height of the layers, which may be patterned at each physical etching process, may be minimized. As a result, the attachment of a magnetic material onto a sidewall of the second MTJ structure403may be reduced, or alternatively prevented, and thus the MRAM device may not be electrically short.

FIG. 17is a cross-sectional view illustrating an MRAM device in accordance with example embodiments. The MRAM device ofFIG. 17may be substantially the same as or similar to the device illustrated with reference toFIG. 1except for sixth and seventh insulating interlayers390and420and a third spacer415. Thus, like reference numerals refer to like elements, and detailed explanations thereabout may be omitted herein.

Referring toFIG. 17, the MRAM device may include the transistor containing a gate structure140and an impurity region160, a lower electrode225, a first MTJ structure401and a wiring360. The MRAM device may include a first spacer150, first to third contact plugs181,183and210, first and second pads191and193, first, second and fourth insulating interlayers170,200and330, and an etch stop layer320. The MRAM device may further include the sixth and seventh insulating interlayers390and420and the third spacer415.

The first MTJ structure401may include a first pinning layer pattern235, a first tunnel barrier layer pattern245, a free layer pattern255, a second tunnel barrier layer pattern265, a capping layer pattern275and a second pinning layer pattern310sequentially stacked on the lower electrode225.

The sixth insulating interlayer390may be formed on the second insulating interlayer200to surround sidewalls of the lower electrode225and the first pinning layer pattern235. The sixth insulating interlayer390may include an oxide, e.g., silicon oxide,

The third spacer415may be formed on the sixth insulating interlayer390to surround sidewalls of the first tunnel barrier layer pattern245, the free layer pattern255, the second tunnel barrier layer pattern265and the capping layer pattern275. The second pinning e pattern310may contact a top surface of the capping layer pattern275and a top surface of the third spacer415. The third spacer415may include a nitride, e.g., silicon nitride.

The seventh insulating interlayer420may surround a sidewall of the second pinning layer pattern310and an outer sidewall of the third spacer415. The seventh insulating interlayer420may include an oxide, e.g., silicon oxide.

The wiring360may be formed on the second pinning layer pattern310to contact a top surface thereof, and the fourth insulating interlayer330may surround a sidewall of the wiring360. The fourth insulating interlayer330may be formed on the seventh insulating interlayer420, and the etch stop layer320may be formed between the seventh and fourth insulating interlayers420and330.

FIGS. 18 to 21are cross-sectional views illustrating a method of manufacturing an MRAM device in accordance with example embodiments. The method may include processes substantially the same as or similar to those illustrated with reference toFIGS. 2 to 10except for forming sixth and seventh insulating interlayers390and420and forming a third spacer415. Thus, like reference numerals refer to like elements, and detailed explanations thereabout may be omitted herein.

First, processes substantially the same as or similar to those illustrated with reference toFIGS. 2 and 3may be performed. Thus, the transistor including the gate structure140and the impurity region160, the first to third contact plugs181,183and210, the first and second pads191and193and the first and second insulating interlayers170and200may be formed,

Referring toFIG. 18, processes substantially the same as or similar to those illustrated with reference toFIG. 4may be performed. Thus, the lower electrode235and the first pinning layer pattern235may be formed. That is, the lower electrode235and the first pinning layer pattern235may be formed by sequentially forming the lower electrode layer220and the first pinning layer230on the second insulating interlayer200and the third contact plug210, and patterning the lower electrode layer220and the first pinning layer230. A plurality of lower electrodes225and a plurality of first pinning layer patterns235may be formed in a first direction that is substantially parallel to the top surface of the substrate100and a second direction that is parallel to the top surface of the top surface of the substrate100and substantially perpendicular to the first direction. The lower electrode225may contact the top surface of the third contact plug210.

In example embodiments, the patterning process may be performed by a physical etching process such as a plasma reaction etching process or an ion sputtering process. The plasma reaction etching process may be performed using an etching gas including, e.g., HF and/or NH3, and a reaction gas including, e.g., oxygen.

Referring toFIG. 19, a sixth insulating interlayer390may be formed on the second insulating interlayer200to sufficiently cover the lower electrode225and the first pinning layer pattern235, and an upper portion of the sixth insulating interlayer390may be planarized until the top surface of the first pinning layer pattern235may be exposed. The tunnel barrier layer240, the free layer250, the second tunnel barrier layer260, the capping layer270and the hard mask layer280may be sequentially formed on the planarized sixth insulating interlayer390and the first pinning layer pattern235.

By the planarizing process, the sixth insulating interlayer390may surround sidewalls of the lower electrode225and the first pinning layer pattern235. The sixth insulating interlayer390may be formed to include an oxide, e.g., silicon oxide.

A tunnel barrier layer240, a free layer250, a second tunnel barrier layer260, a capping layer270and a hard mask layer280may be formed by processes substantially the same as or similar to those illustrated with reference toFIG. 4.

Referring toFIG. 20, the hard mask layer280may be etched to form a hard mask285, and the capping layer270, the second tunnel barrier layer260, the free layer250and the first tunnel barrier layer240may be sequentially etched using the hard mask285as an etching mask. Thus, a first tunnel barrier layer pattern245, a free layer pattern255, a second tunnel barrier layer pattern265and a capping layer pattern275may be formed.

A plurality of hard masks285may be formed in the first and second directions. Accordingly, a plurality of first tunnel barrier layer patterns245, a plurality of free layer patterns255, a plurality of second tunnel barrier layer patterns265and a plurality of capping layer patterns275may be formed in the first and second directions. By the etching process, the first tunnel barrier layer pattern245may be formed to contact the top surface of the first pinning layer pattern235.

Referring toFIG. 21, a third spacer layer410and a seventh insulating interlayer420may be sequentially formed on the sixth insulating interlayer390to cover the first tunnel barrier layer pattern245, the free layer pattern255, the second tunnel barrier layer pattern265, the capping layer pattern275and the hard mask285.

In one example embodiment, the seventh insulating interlayer420may have atop surface substantially higher than a top surface of the third spacer layer410on the hard mask285.

The third spacer layer410may be formed to include an oxide and/or a nitride, e.g., aluminum oxide (Al2O3), silicon oxide or silicon nitride. The seventh insulating interlayer420may be formed to include an oxide, e.g., silicon oxide.

Thereafter, processes substantially the same as or similar to those illustrated with reference toFIGS. 7 to 10andFIG. 1may be performed. Thus, a second pinning layer pattern310and a wiring360contacting the top surface thereof may be formed. As a result, the MRAM device may be manufactured as shown inFIG. 17.

As described above, when the first MTJ structure401is formed, the lower electrode225and the first pinning layer pattern235may be formed by a first physical etching process, the first and second barrier layer patterns245and265, the free layer pattern255and the capping layer pattern275may be formed by a second physical etching process, and the second pinning layer pattern310may be formed by a damascene process. That is, the second pinning layer pattern310may not be formed together with the patterns of the first MTJ structure401thereunder at the same physical etching process, and the patterns of the first MTJ structure401thereunder may be formed by at least two independent physical etching processes. Thus, the first MTJ structure401may not be short-circuited.

FIG. 22is a cross-sectional view illustrating an MRAM device in accordance with example embodiments. The MRAM device ofFIG. 22may be substantially the same as or similar to that illustrated with reference toFIG. 17except for a third pinning layer pattern375. Thus, like reference numerals refer to like elements, and detailed explanations thereabout may be omitted herein.

Referring toFIG. 22, the MRAM device may include a transistor containing a gate structure140and an impurity region160, a lower electrode225, a second MTJ structure403and a wiring360. The MRAM device may further include first and third spacers150and415, first to third contact plugs181,183and210, first and second pads191and193and first, second, sixth and seventh insulating interlayers170,200,390and420.

The second MTJ structure403may include a first pinning layer pattern235, a first tunnel barrier layer pattern245, a free layer pattern255, a second tunnel barrier layer pattern265, a capping layer pattern275and a third pinning layer pattern375sequentially stacked on the lower electrode225.

The sixth insulating interlayer390may surround the sidewalls of the first pinning layer pattern235and the lower electrode225, and the third spacer415may surround sidewalls of the first tunnel barrier layer pattern245, the free layer pattern255, the second tunnel barrier layer pattern265and the capping layer pattern275.

The seventh insulating interlayer420may surround sidewalls of the wiring360and the third pinning layer pattern375and an outer sidewall of the third spacer415.

The MRAM device shown inFIG. 22may be manufactured by processes that are substantially the same as or similar to those illustrated with reference toFIGS. 18 to 21except for forming a third pinning layer pattern375.

First, processes substantially the same as or similar to those illustrated with reference toFIGS. 2 and 3may be performed. Thus, the transistor including the gate structure140and the impurity region160, the first to third contact plugs181,183and210, the first and second pads191and193and first and second insulating interlayers170and200may be formed.

Processes substantially the same as or similar to those illustrated with reference toFIGS. 18 and 21may be performed. Thus, the lower electrode225, the first pinning layer pattern235, the first tunnel barrier layer pattern245, the free layer pattern255, the second tunnel barrier layer pattern265and the capping layer pattern275may be formed.

Thereafter, processes substantially the same as or similar to those illustrated with reference toFIGS. 12 and 13may be performed. Thus, the third pinning layer pattern375and the wiring360may be formed. Alternatively, the third pinning layer pattern375and the wiring360may be formed by processes substantially the same as or similar to those illustrated with reference toFIGS. 14 and 16.

Therefore, the MRAM device may be manufactured.

As described above, when the second MTJ structure403is formed, the lower electrode225, the first pinning layer pattern235, the first tunnel barrier layer pattern245, the free layer pattern255, the second tunnel barrier layer pattern265and the capping layer pattern275may be formed by at least two independent physical etching processes, and the third pinning layer pattern375may be formed by a physical etching process or a damascene process. As a result, the second MTJ structure403may not be electrically short.