Adaptation of baseline wander correction loop gain settings

An apparatus including a first circuit and a second circuit. The first circuit may be configured to receive a signal, where low frequency content of the signal is attenuated due to high pass filtering by a medium carrying the signal and a coupling. The second circuit may be configured to automatically set a gain of a baseline wander correction loop to restore the low frequency content in the signal based upon a sample taken from a first point in a signal pathway of the first circuit.

FIELD OF THE INVENTION

The present invention relates to data communications generally and, more particularly, to a method and/or apparatus for adaptation of baseline wander correction loop gain settings.

BACKGROUND OF THE INVENTION

In AC (alternating current) coupled systems, an AC coupling (i.e., capacitive coupling) or an inductive coupling (i.e., transformer coupling) behaves as a high pass filter, only allowing high frequency content to go through. The high pass filter behavior becomes a problem when the data traffic is not DC (direct current) balanced, meaning the traffic has a significant amount of low frequency content. For example, 16 G Fibre Channel (FC) uses 64b/66b coding, which is not DC balanced. The low frequency content is filtered out by the high pass filter behavior of the capacitive or inductive coupling. Baseline wander correction (BLWC) is used to address this problem.

Baseline wander also occurs in medical equipment where the low frequency loss can be due to poor contact. With respect to an electrocardiogram (ECG), the baseline wander is an extraneous, low-frequency activity, which may interfere with signal analysis, making the clinical interpretation inaccurate. When baseline wander takes place, ECG measurements related to the isoelectric line cannot be computed since the isoelectric line is not well-defined. Baseline wander in ECGs is often exercise-induced, and can come from a variety of sources, including perspiration, respiration, body movements and poor electrode contact. The spectral content of the baseline wander in an ECG is usually in the range between 0.05-1 Hz. However, during strenuous exercise, the baseline wander may contain higher frequencies.

A technique for correcting baseline wander is to low pass filter a received signal to restore the low frequency content and add the filtered signal back to the received signal. However, setting a gain for the baseline wander correction is not trivial. The optimal gain setting depends not only on the channel loss in the low frequency region, but also on the de-emphasis settings at the transmitter.

Conventional BLWC techniques involve manually setting the gain. Users either (i) set the gain based on a formula, (ii) sweep across a range of gain settings and pick one that works best, or (iii) find a starting point for the gain using an average of an eye envelope at the receiver input. Setting the gain manually is a significant problem for users, no matter what method is used. The optimal gain depends on the channel loss at the low frequency region, as well as the transmitter (TX) de-emphasis settings. Consequently, the gain needs to be different for different channels and needs to be updated when the TX de-emphasis changes.

It would be desirable to have an automatic adaptation of baseline wander correction loop gain settings.

SUMMARY OF THE INVENTION

The present invention concerns an apparatus including a first circuit and a second circuit. The first circuit may be configured to receive a signal, where low frequency content of the signal is attenuated due to high pass filtering by a medium carrying the signal and a coupling. The second circuit may be configured to automatically set a gain of a baseline wander correction loop to restore the low frequency content in the signal based upon a sample taken from a first point in a signal pathway of the first circuit.

The objects, features and advantages of the present invention include providing a method and/or apparatus for adaptation of baseline wander correction loop gain settings that may (i) automatically find an optimal gain setting for baseline wander correction, (ii) have a simple implementation, (iii) be implemented without any changes to the analog domain, (iv) be implemented by adding an accumulator and gain loop adaptation to the digital domain, (v) have low implementation cost, and/or (vi) use approximations to simplify the adaptation process.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

In one aspect, an example embodiment of the present invention generally provides an adaptation process that may automatically set a baseline wander correction loop gain to minimize mean squared error (MSE) at an input of a detector (e.g., slicer, etc.). Adaptation of baseline wander correction loop gain settings in accordance with the present invention generally uses an error signal, as well as an output signal of a baseline wander correction circuit. The error signal is generally defined similarly to other adaptation techniques. In another aspect, the present invention generally provides a simple way to implement the baseline wander correction gain adaptation process. In one example, an accumulator may be employed in place of an ideal low pass filter to generate the output signal. The approximation made by the use of an accumulator instead of an ideal low pass filter may greatly reduce implementation cost, while not significantly sacrificing performance.

Referring toFIG. 1, a block diagram of a circuit100is shown illustrating an apparatus including baseline wander correction in accordance with an example embodiment of the present invention. The circuit100may include a block (or circuit)102, a block (or circuit)104, a block (or circuit)106, and a block (or circuit)108. The circuits102-108may represent modules and/or blocks that may be implemented as hardware, software, a combination of hardware and software, or other implementation. The circuit102may implement, in one example, a transmitter. The circuit104may implement, in one example, a channel (e.g., a transmission medium such as air, wire, optical fibre, etc.). The circuit106may implement, in one example, a coupling to the transmission medium104(e.g., a capacitive coupling, an inductive coupling, an electrode, or other connection). The circuit106may be placed between the circuit104and either of the circuits102and108. The circuit108may implement, in one example, a receiver (e.g., ethernet receiver, medical instrumentation, wireless receiver, etc.).

The circuit102may generate a signal carrying data to be communicated to a device connected to an output of the circuit108. The signal may be communicated to the circuit108via the circuit104and the circuit106. The circuit106may attenuate low frequency content of the signal, while passing high frequency content. In general, the circuit106may behave as a high pass filter.

Referring toFIG. 2, a diagram is shown illustrating an example circuit110implementing baseline wander correction in accordance with an example embodiment of the present invention. In one example, the circuit110may comprise a block (or circuit)112, a block (or circuit)114, and a block (or circuit)120. The circuit112may represent aggregated transfer characteristics of the circuit102and the circuit104ofFIG. 1. The circuit114may implement a high pass filter generally representing the frequency response of the circuit106ofFIG. 1. The circuit120may be used to implement the receiver108ofFIG. 1.

The circuit120may comprise, in one example, a first block (or circuit)122and a block (or circuit)124. The circuit122may implement, in one example, a receiver chain (or signal path). The circuit124may implement, for example, a baseline wander correction circuit in accordance with an example embodiment of the present invention.

In one example, the circuit122may have a first input that may receive a signal (e.g., Y(t)), a second input that may receive a signal (e.g., FBK(t)), and an output that may present a signal (e.g., DK). The signal FBK(t) may comprise a feedback signal containing low frequency content to be restored to the signal Y(t). The signal DK may comprise a recovered data signal. The circuit122may be configured to generate the signal DK in response to the signal Y(t) and the signal FBK(t). The circuit124may have an input that may receive the signal DK and an output that may present the signal FBK(t).

In one example, the signals Y(t) and FBK(t) may comprise analog signals and the signal DK may comprise a digital signal. In general, signals that are in the analog domain are generally denoted herein as functions of time (e.g., func(t)). Signals in the digital domain are generally denoted without the parenthetical or have a label ending in K (e.g., DK). The suffix K generally denotes the signal as being the Kth sample, symbol, etc.

In one example, the circuit122may comprise a block (or circuit)126and a block (or circuit)128. The circuit126may implement a summing node. The circuit128may implement a detector. The circuit126may be implemented, in one example, as an adder. The circuit128may be implemented, for example, as a symbol detector, a slicer, or other data detection circuit. The circuit126may have a first input that may receive the signal Y(t), a second input that may receive the signal FBK(t), and an output that may present a signal (e.g., R(t)). The signal R(t) generally represents the received signal with low frequency content restored. The circuit128may have an input that may receive the signal R(t) and an output that may present the signal DK. The circuit128may be configured to generate the signal DK in response to the signal R(t).

In one example, the circuit124a block (or circuit)130and a block (or circuit)132. The circuit130may comprise a low pass filter. The circuit132may be implemented as multiplier. The circuit130may have an input that may receive the signal DK and an output that may present a signal (e.g., BLWC(t)). The signal BLWC(t) may implement a baseline wander correction signal. The circuit132may have a first input that may receive the signal BLWC(t), a second input that may receive a signal (e.g., G), and an output that may present the signal FBK(t). The signal G may implement a baseline wander correction loop gain. In one example, the baseline wander correction loop gain G may be implemented as a predefined constant. In another example, the baseline wander correction loop gain G may be automatically adapted through an adaptation loop in accordance with an embodiment of the present invention. The circuit132is generally configured to apply the gain G to the signal BLWC(t) to generate the signal FBK(t).

The coupling106generally behaves as a high pass filter. Non DC balanced traffic (e.g., 16 G fibre channel (FC) using 64b/66b coding) has significant low frequency content which is filtered out by the high pass behavior of the coupling106. The baseline wander correction provided by the circuit120generally restores the low frequency content based upon low pass filtering recovered data (e.g., DK) and adding the filtered data back to the received signal at a point after the coupling106.

For example, the circuit128may recover the data DK from the signal R(t). The recovered data DK may be presented to an input of the circuit130. The circuit130may generate the signal BLWC(t) in response to the signal DK. An output of the circuit130may present the signal BLWC(t) to a first input of the circuit132. The circuit132may have a second input that may receive the gain signal G and an output that may present a product of the gain signal G and the signal BLWC(t) as the signal FBK(t), to the second input of the circuit126. The first input of the circuit126may receive the signal Y(t) from the coupling106and the output may present the signal R(t) to the input of the circuit128.

The circuit124generally represents a baseline wander correction loop in accordance with an example embodiment of the present invention. In one example, the block112may be represented by a transfer function Htx(f)*Hch(f), the block114may be represented by a transfer function Hhp(f), and the circuit130may be represented by a transfer function Hlp(f). Operation of the circuit110with an optimal gain value may be expressed by the following equation:
Sd(f)*|Htx(f)|^*2|Hch(f)|^2*|Hhp(f)|^2+Sdk(f)*|Hlp(f)|^2*G^2=Sd(f)*|Htx(f)|^2* |Hch(f)|^2.
An expression for the optimal gain value may be obtained by considering Sdk(f) to equal Sd(f) and |Hhp(f)|^2+|Hlp(f)|^2 to be equal to 1. In order to obtain G*|Hlp(f)|=|Htx(f)|*|Hch(f)|*|Hlp(f)|, G may be set to equal |Htx(f)|*|Hch(f)|. A corner frequency of a low pass filter (e.g., seeFIG. 3) with G =|Htx(f)|*|Hch(f)|*|Hlp(f)| is generally a sufficient condition for the equation to be true. In one example, G may be set to constant value to simplify implementation of the filter. The constant may be expressed as |Htx(f0)|*|Hch(f0)|, where f0 is a constant that is less than the corner frequency of the low pass filter. In one example, f0 may be set to zero. Based upon the close form expression of the optimal baseline wander correction loop gain, the optimal gain generally depends on transmitter de-emphasis and channel loss within the pass band of the low pass filter implemented in the circuit130.

Referring toFIG. 4, a block diagram of a circuit200is shown illustrating another example implementation of baseline wander correction gain adaptation in accordance with another example embodiment of the present invention. In one example, the circuit200may comprise a block (or circuit)202and a block or circuit204. The circuit202may be implemented, in one example, as a data recovery circuit. The circuit204may be implemented, in one example, as a baseline wander correction circuit. The circuit202may have a first input that may receive the signal from the coupling106, a second input that may receive a signal (e.g., FBK(t)), a first output that may present a signal (e.g., DR), and a second output that may present a signal (e.g., EK). The signal DK may comprise recovered data. The signal EK may comprise and error signal. The signal FBK(t) may comprise low frequency content to be restored to the received signal from the coupling106. The circuit204may have a first input that may receive the signal DK, a second input that may receive the signal EK, and an output that may present the signal FBK(t).

The circuit202may comprise a block (or circuit)210, a block (or circuit)212, a block (or circuit)214, a block (or circuit)216, a block (or circuit)218, and a block (or circuit)220. The circuit210may be implemented, in one example, as an adder. The circuit212may be implemented, in one example, as a linear equalizer. The circuit214may be implemented, in one example, as an adder. The circuit216may be implemented, in one example, as a symbol detector, slicer, or other data detection circuit. The circuit218may be implemented, in one example, as an error signal generator. The circuit220may implement a decision feedback equalizer (DFE). The circuits210-220may be implemented using conventional techniques.

The circuit210may have a first input that may receive the signal from the coupling106, a second input that may receive the signal FBK(t), and an output that may present a signal (e.g., (Y(t)). The signal Y(t) may comprise a sum of the signal from the coupling106and the signal FBK(t). The signal Y(t) may be presented to an input of the circuit212. The circuit212may have an output that may present a signal to a first input of the circuit214. The circuit214may have a second input that may receive a signal (e.g., F(t)), and an output that may present a signal (e.g., R(t)). The signal R(t) may comprise, in one example, a difference between the output of the circuit212and the signal F(t). The circuit216may have an input that may receive the signal R(t) and an output that may present the signal DK. The circuit218may have a first input that may receive the signal R(t), a second input that may receive the signal DK, and an output that may present the signal EK. The circuit220may have an input that may receive the signal DK and an output that may present the signal F(t). In one example, the circuit220may also receive the signal EK.

The circuit204may comprise a block (or circuit)230, a block (or circuit)232, a block (or circuit)234, a block (or circuit)236, and a block (or circuit)238. The circuit230may implement an optional data processing (DP) circuit. The circuit232may be implemented, in one example, as an analog low pass filter. The circuit234may be implemented, in one example, as a digital low pass filter. The circuit236may be implemented, in one example, as a multiplier. The circuit238may implement a gain adaptation loop in accordance with an embodiment of the present invention. The circuit230, when implemented, generally processes the signal DK for use in controlling the circuits232and234. The circuit230may be omitted depending upon the particular implementations of the circuits232and234. When the circuit230is not implemented, the signal DK may be presented directly to the circuits222and224.

The circuit230may have an input that may receive the signal DK and an output that may present a signal (e.g., C) to an input of the circuit232and an input of the circuit234. The circuit232may have an output that may present a signal (e.g., BLWC(t)) to a first input of the circuit236. The signal BLWC(t) may comprise low frequency content to be restored to the received signal. The circuit234may have an output that may present a signal (e.g., BLWCK) to a first input of the circuit238. The circuit238may have a second input that may receive the signal EK and an output that may present a signal (e.g., G) to a second input of the circuit236. The signal G may comprise a loop gain value to be applied to the low frequency content to be restored. The circuit234generally has a frequency response that matches a frequency response of the circuit232. The circuits234and238generally provide an adaptation loop for determining the appropriate gain value. The circuit238may implement the loop gain adaptation using a least mean squares (LMS) technique. The circuit236may have an output that may present the signal FBK(t). The signal FBK(t) generally comprises a product of the signal BLWC(t) and the signal G.

Referring toFIG. 5, a block diagram is shown illustrating an example implementation of the optional data processing block220ofFIG. 4. In one example, the data processing block220may comprise a block (or circuit)300, a block (or circuit)302, a block (or circuit)304, a block (or circuit)306, and a block (or circuit)308. The block300may be implemented, in one example, as an adder. The block302may be implemented, in one example, as a first lookup table. The block304may be implemented, in one example, as a second lookup table. The block306may be implemented, in one example, as a first accumulator. The block308may be implemented, in one example, as a second accumulator.

The block300may receive the data signal DK. In one example, the block300may be configured to sum a number (e.g.,306) of samples (e.g., DK[0:255]) of the signal DK. However, other number of samples may be implemented accordingly to meet the design criteria of a particular implementation. The block300may be configured to present a signal representing the number of ones in the summed data samples to an input of the block302and an input of the block304. The block302may be configured to present a signal (e.g., DPNUM) in response to the signal from the block300. The block304may be configured to present a signal (e.g., DNNUM) in response to the signal from the block300. The signal DPNUM may be presented to an input of the block306. The signal DNNUM may be presented to an input of the block308. The block306may present a signal (e.g., CPI) in response to the signal DPNUM. The block308may present a signal (e.g., CNI) in response to the signal DNNUM. The signals CPI and CNI generally represent components of the signal C. The signals CPI and CNI may be used to control the circuits232and234.

Referring toFIG. 6, a block diagram of a circuit400is shown illustrating another example implementation of baseline wander correction with gain adaptation in accordance with another example embodiment of the present invention. In one example, the circuit400may comprise a block (or circuit)402and a block or circuit404. The circuit402may be implemented, in one example, as a data recovery circuit. The circuit404may be implemented, in one example, as a baseline wander correction circuit. The circuit402may have a first input that may receive the signal from the coupling106, a second input that may receive a signal (e.g., FBK(t)), a first output that may present a signal (e.g., DK), and a second output that may present a signal (e.g., EK). The signal DK may comprise recovered data. The signal EK may comprise an error signal. The signal FBK(t) may comprise low frequency content to be restored to the received signal from the coupling106. The circuit404may have a first input that may receive the signal DK, a second input that may receive the signal EK, and an output that may present the signal FBK(t).

The circuit402may comprise a block (or circuit)410, a block (or circuit)412, a block (or circuit)414, a block (or circuit)416, a block (or circuit)418, and a block (or circuit)420. The circuit410may be implemented, in one example, as an adder. The circuit412may be implemented, in one example, as a linear equalizer. The circuit414may be implemented, in one example, as an adder. The circuit416may be implemented, in one example, as a symbol detector, slicer, or other data detection circuit. The circuit418may be implemented, in one example, as an error signal generator. The circuit420may implement a decision feedback equalizer (DFE). The circuits410-420may be implemented using conventional techniques.

The circuit410may have a first input that may receive the signal from the coupling106, a second input that may receive the signal FBK(t), and an output that may present a signal (e.g., (Y(t)). The signal Y(t) may comprise a sum of the signal from the coupling106and the signal FBK(t). The signal Y(t) may be presented to an input of the circuit412. The circuit412may have an output that may present a signal to a first input of the circuit414. The circuit414may have a second input that may receive a signal (e.g., F(t)) and an output that may present a signal (e.g., R(t)). The signal R(t) may comprise, in one example, a difference between the output of the circuit412and the signal F(t). The circuit416may have an input that may receive the signal R(t) and an output that may present the signal DK. The circuit418may have a first input that may receive the signal R(t), a second input that may receive the signal DK, and an output that may present a signal (e.g., EK). The signal EK may implement an error signal. The circuit420may have an input that may receive the signal DK and an output that may present the signal F(t). In one example, the circuit420may also receive the signal EK.

The circuit404may comprise a block (or circuit)430, a block (or circuit)432, a block (or circuit)434, a block (or circuit)436, and a block (or circuit)438. The circuit430may implement an optional data processing (DP) circuit. The circuit432may be implemented, in one example, as an analog low pass filter. The circuit434may be implemented, in one example, as a latch or analog-to-digital convertor (ADC). The circuit436may be implemented, in one example, as a multiplier. In one example, the circuit438may implement a gain adaptation loop in accordance with an embodiment of the present invention. The circuit430, when implemented, generally processes the signal. DK for use in controlling the circuit432. The circuit430may be implemented similarly to the circuit230inFIG. 5. The circuit430may be omitted depending upon the particular implementation of the circuit432. When the circuit430is not implemented, the signal DK may be presented directly to the circuit432.

The circuit430may have an input that may receive the signal DK and an output that may present a signal (e.g., C) to an input of the circuit432. The circuit432may have an output that may present a signal (e.g., BLWC(t)) to an input of the circuit434and a first input of the circuit436. The signal BLWC(t) may comprise low frequency content to be restored to the received signal. The circuit434may have an output that may present a signal (e.g., BLWCK) to a first input of the circuit438. The circuit438may have a second input that may receive the signal EK and an output that may present a signal (e.g., G) to a second input of the circuit436. The signal G may comprise a loop gain value to be applied to the low frequency content to be restored. The circuit434generally converts the signal BLWC(t) from the analog domain to the digital domain. The circuit438generally provides an adaptation loop for determining the appropriate gain value. In one example, the circuit438may implement loop gain adaptation using a least means squared (LMS) technique. The circuit436may have an output that may present the signal FBK(t). The signal FBK(t) generally comprises a product of the signal BLWC(t) and the signal G.

Referring toFIG. 7, a diagram of a circuit450is shown illustrating an example error signal generator in accordance with an example embodiment of the present invention. The circuit450may be used to implement the circuit218ofFIG. 4and the circuit418ofFIG. 6. In one example, the circuit450may comprise a block (or circuit)452, a block (or circuit)454and a block (or circuit)456. The circuit452may be implemented, in one example, as a capture latch with a threshold of −H0. The circuit454may be implemented, in one example, as a capture latch with a threshold of H0. H0generally represents a target level of a receiver in which the circuit450is implemented. The circuit456may be implemented, in one example, as a multiplexer.

The signal R(t) may be presented to an input of the circuit452and an input of the circuit454. For example, the signal R(t) may be sampled in response to a sampling clock (e.g., CLK180) and the samples presented to the circuit452, the circuit454, and a data detector associated with the circuit450. An output of the circuit452may be presented to a first input of the circuit456. An output of the circuit454may be presented to a second input of the circuit456. The signal DK may be presented to a third input (e.g., a control input) of the circuit456. The circuit456may have an output that may present the signal EK. The sign of the signal EK may be obtained by using the two error latches452and454. One of the latches is selected based on DK since DK is not known ahead of time.

Referring toFIG. 8, a block diagram of a circuit500is shown illustrating another example implementation of baseline wander correction loop gain adaptation in accordance with another example embodiment of the present invention. In one example, the circuit500may comprise a block (or circuit)502and a block or circuit504. The circuit502may be implemented, in one example, as a data recovery circuit. The circuit504may be implemented, in one example, as a baseline wander correction circuit. The circuit502may have a first input that may receive the signal from the coupling106, a second input that may receive a signal (e.g., FBK(t)), a first output that may present a signal (e.g., DK), and a second output that may present a signal (e.g., EK). The signal DK may comprise recovered data. The signal EK may comprise an error signal. The signal FBK(t) may comprise low frequency content to be restored to the received signal from the coupling106. The circuit504may have a first input that may receive the signal DK, a second input that may receive the signal EK, and an output that may present the signal FBK(t).

The circuit502may comprise a block (or circuit)510, a block (or circuit)512, a block (or circuit)514, a block (or circuit)516, a block (or circuit)518, and a block (or circuit)520. The circuit510may be implemented, in one example, as an adder. The circuit512may be implemented, in one example, as an analog to digital converter (ADC). The circuit514may be implemented, in one example, as an adder. The circuit516may be implemented, in one example, as a symbol detector, slicer, or other data detection circuit. The circuit518may be implemented, in one example, as an error signal generator. The circuit520may implement a decision feedback equalizer (DFE). The circuits510-520may be implemented using conventional techniques.

The circuit510may have a first input that may receive the signal from the coupling106, a second input that may receive the signal FBK(t), and an output that may present a signal (e.g., (Y(t)). The signal Y(t) may comprise a sum of the signal from the coupling106and the signal FBK(t). The signal Y(t) may be presented to an input of the circuit512. The circuit512may have an output that may present a digital signal (e.g., YK) to a first input of the circuit514. The circuit514may have a second input that may receive a signal (e.g., FK) and an output that may present a signal (e.g., RK). The signal RK may comprise a difference between the output of the circuit512and the signal FK. The circuit516may have an input that may receive the signal RK and an output presenting the signal DK. The circuit518may have a first input that may receive the signal RK, a second input that may receive the signal DK, and an output that may present a signal (e.g., EK). The signal EK may implement an error signal. The circuit520may have an input that may receive the signal DK and an output that may present the signal FK. In one example, the circuit520may also receive the signal EK.

The circuit504may comprise a block (or circuit)530, a block (or circuit)532, a block (or circuit)534, and a block (or circuit)536. The circuit530may implement an optional data processing (DP) circuit. The circuit532may be implemented, in one example, as an digital low pass filter. The circuit534may be implemented, in one example, as a multiplier. The circuit536may implement a gain adaptation loop in accordance with an embodiment of the present invention. The circuit530, when implemented, generally processes the signal DK for use in controlling the circuit532. The circuit530may be implemented similarly to the circuit230inFIG. 5. The circuit530may be omitted depending upon the particular implementation of the circuit532. When the circuit530is not implemented, the signal DK may be presented directly to the circuit532.

The circuit530may have an input that may receive the signal DK and an output that may present a signal (e.g., C) to an input of the circuit532. The circuit532may have an output that may present a signal (e.g., BLWCK) to a first input of the circuit534and a first input of the circuit536. The signal BLWCK may comprise low frequency content to be restored to the received signal. The circuit536may have a second input that may receive the signal EK and an output that may present a signal (e.g., G) to a second input of the circuit534. The signal G may comprise a loop gain value to be applied to the low frequency content to be restored. The circuit536generally provides an adaptation loop for determining an appropriate gain value. In one example, the circuit536may use a least means squared (LMS) technique for adapting the loop gain. The circuit534may have an output that may present the signal FBK(t). The signal FBK(t) generally comprises a product of the signal BLWCK and the signal G.

Referring toFIG. 9, a block diagram of a circuit600is shown illustrating another example implementation of baseline wander correction loop gain adaptation in accordance with another example embodiment of the present invention. In one example, the circuit600may comprise a block (or circuit)602and a block or circuit604. The circuit602may be implemented, in one example, as a data recovery circuit. The circuit604may be implemented, in one example, as a baseline wander correction circuit. The circuit602may have a first input that may receive the signal from the coupling106, a second input that may receive a signal (e.g., FBK(t)), a first output that may present a signal (e.g., RK), a second output that may present a signal (e.g., DK), and a third output that may present a signal (e.g., EK). The signal RK may comprise a sampled received signal. The signal DK may comprise recovered data (e.g., symbols, bits, etc). The signal EK may comprise an error signal. The signal FBK(t) may comprise low frequency content to be restored to the received signal from the coupling106. The circuit604may have a first input that may receive the signal RK, a second input that may receive the signal EK, and an output that may present the signal FBK(t).

The circuit602may comprise a block (or circuit)610, a block (or circuit)612, a block (or circuit)614, a block (or circuit)616, a block (or circuit)618, and a block (or circuit)620. The circuit610may be implemented, in one example, as an adder. The circuit612may be implemented, in one example, as an analog to digital converter (ADC). The circuit614may be implemented, in one example, as an adder. The circuit616may be implemented, in one example, as a symbol detector, slicer, or other data detection circuit. The circuit618may be implemented, in one example, as an error signal generator. The circuit620may implement a decision feedback equalizer (DFE). The circuits610-620may be implemented using conventional techniques.

The circuit610may have a first input that may receive the signal from the coupling106, a second input that may receive the signal FBK(t), and an output that may present a signal (e.g., (Y(t)). The signal Y(t) may comprise a sum of the signal from the coupling106and the signal FBK(t). The signal Y(t) may be presented to an input of the circuit612. The circuit612may have an output that may present a digital signal (e.g., YK) to a first input of the circuit614. The circuit614may have a second input that may receive a signal (e.g., FK) and an output that may present a signal (e.g., RK). The signal RK may comprise a difference between the signal YK and the signal FK. The circuit616may have an input that may receive the signal RK and an output presenting the signal DK. The circuit618may have a first input that may receive the signal RK, a second input that may receive the signal DK, and an output that may present the signal EK. The circuit620may have an input that may receive the signal DK and an output that may present the signal FK. In one example, the circuit620may also receive the signal EK.

The circuit604may comprise a block (or circuit)630, a block (or circuit)632, a block (or circuit)634, and a block (or circuit)636. The circuit630may implement an optional data processing (DP) circuit. The circuit632may be implemented, in one example, as an digital low pass filter. The circuit634may be implemented, in one example, as a multiplier. The circuit636may implement a gain adaptation loop in accordance with an embodiment of the present invention. The circuit630, when implemented, generally processes the signal RK for use in controlling the circuit632. In one example, the circuit630may be implemented similarly to the circuit230inFIG. 5. The circuit630may be omitted depending upon the particular implementation of the circuit632. When the circuit630is not implemented, the signal RK may be presented directly to the circuit632.

The circuit630may have an input that may receive the signal RK and an output that may present a signal (e.g., C) to an input of the circuit632. The circuit632may have an output that may present a signal (e.g., BLWCK) to a first input of the circuit634and a first input of the circuit636. The signal BLWCK may comprise low frequency content to be restored to the received signal. The circuit636may have a second input that may receive the signal EK and an output that may present a signal (e.g., G) to a second input of the circuit634. The signal G may comprise a loop gain value to be applied to the low frequency content to be restored. The circuit636generally provides an adaptation loop for determining an appropriate gain value. The circuit634may have an output that may present the signal FBK(t). The signal FBK(t) generally comprises a product of the signal BLWCK and the signal G.

Referring toFIG. 10, a block diagram of a circuit700is shown illustrating another example implementation of baseline wander correction loop gain adaptation in accordance with another example embodiment of the present invention. In one example, the circuit700may comprise a block (or circuit)702and a block or circuit704. The circuit702may be implemented, in one example, as a data recovery circuit. The circuit704may be implemented, in one example, as a baseline wander correction circuit. The circuit702may have a first input that may receive the signal from the coupling106, a second input that may receive a signal (e.g., FBK(t)), a first output that may present a signal (e.g., YK), a second output that may present a signal (e.g., DK), and a third output that may present a signal (e.g., EK). The signal YK may comprise a digitized version of a received signal (e.g., Y(t)). The signal DK may comprise recovered data (e.g., symbols, bits, etc). The signal EK may comprise an error signal. The signal FBK(t) may comprise low frequency content to be restored to the received signal from the coupling106. The circuit704may have a first input that may receive the signal YK, a second input that may receive the signal EK, and an output that may present the signal FBK(t).

The circuit702may comprise a block (or circuit)710, a block (or circuit)712, a block (or circuit)714, a block (or circuit)716, a block (or circuit)718, and a block (or circuit)720. The circuit710may be implemented, in one example, as an adder. The circuit712may be implemented, in one example, as an analog to digital converter (ADC). The circuit714may be implemented, in one example, as an adder. The circuit716may be implemented, in one example, as a symbol detector, slicer, or other data detection circuit. The circuit718may be implemented, in one example, as an error signal generator. The circuit720may implement a decision feedback equalizer (DFE). The circuits710-720may be implemented using conventional techniques.

The circuit710may have a first input that may receive the signal from the coupling106, a second input that may receive the signal FBK(t), and an output that may present the signal Y(t) to an input of the circuit712. The signal Y(t) may comprise a sum of the signal from the coupling106and the signal FBK(t). The circuit712may have an output that may present the signal YK to a first input of the circuit714. The circuit714may have a second input that may receive a signal (e.g., FK) and an output that may present a signal (e.g., RK). The signal RK may comprise a difference between the signal YK and the signal FK. The circuit716may have an input that may receive the signal RK and an output presenting the signal DK. The circuit718may have a first input that may receive the signal RK, a second input that may receive the signal DK, and an output that may present the signal EK. The circuit720may have an input that may receive the signal DK and an output that may present the signal FK. In one example, the circuit720may also receive the signal EK.

The circuit704may comprise a block (or circuit)730, a block (or circuit)732, a block (or circuit)734, and a block (or circuit)736. The circuit730may implement an optional data processing (DP) circuit. The circuit732may be implemented, in one example, as an digital low pass filter. The circuit734may be implemented, in one example, as a multiplier. The circuit736may implement a gain adaptation loop. The circuit730, when implemented, generally processes the signal YK for use in controlling the circuit732. In one example, the circuit730may be implemented similarly to the circuit230inFIG. 5. The circuit730may be omitted depending upon the particular implementation of the circuit732. When the circuit730is not implemented, the signal YK may be presented directly to the circuit732.

The circuit730may have an input that may receive the signal YK and an output that may present a signal (e.g., C) to an input of the circuit732. The circuit732may have an output that may present a signal (e.g., BLWCK) to a first input of the circuit734and a first input of the circuit736. The signal BLWCK may comprise a baseline wander correction signal. In one example, the signal BLWCK may comprise low frequency content to be restored to the received signal. The circuit736may have a second input that may receive the signal EK and an output that may present a signal (e.g., G) to a second input of the circuit734. The signal G may comprise a loop gain value to be applied to the low frequency content to be restored. The circuit736generally provides an adaptation loop for determining an appropriate gain value. In one example, the circuit736may implement the adaptation loop using a least means squared technique. The circuit734may have an output that may present the signal FBK(t). The signal FBK(t) generally comprises a product of the signal BLWCK and the signal G.

Referring toFIG. 11, a diagram is shown illustrating example implementations of a circuit750and a circuit760. The circuits750and760may implement error signal generating circuits. In one example, one of the circuits750and760may be used to implement the circuits518,618, and718(described above in connection withFIGS. 8-10, respectively).

The signal RK may be expressed, in one example, by the following equation:RK=(YK+G*BLWCK)−H1*DK(−1)−H2*DK(−2)− . . . −HM*DK(−M), where M is the number of taps in the DFE520,620, or720. Adaptation of the gain G may be based upon the error signal EK. The error signal EK may be expressed by one of the following equations:
EK=H0*DK−RK;
EK=RK−H0*DK.
In one example, the circuit750may implement the signal EK=RK−H0*DK. In another example, the circuit760may implement the signal EK=H0*DK−RK. The second derivative of EK with respect to G, may be expressed:
dEK^2/dG=−EK*BLWCK.
The gradient of the BLWC gain adaptation may be expressed by the following expression:
−sgn(EK)*sgn(BLWCK).
The adaptation blocks disclosed herein are generally implemented based upon the above gradient to adjust the respective gains.

Referring toFIG. 12, a block diagram of a circuit800is shown illustrating yet one more example implementation of a baseline wander correction in accordance with yet another example embodiment of the present invention. In one example, the circuit800may comprise a block (or circuit)810, a block (or circuit)812, a block (or circuit)814, a block (or circuit)816, a block (or circuit)818, and a block (or circuit)820. The circuit810may be implemented, in one example, as an adder. The circuit812may be implemented, in one example, as a linear equalizer (LE). The circuit814may be implemented, in one example, as an adder. The circuit816may be implemented, in one example, as an analog low pass filter. The circuit818may be implemented, in one example, as a symbol detector, slicer, or other data detection circuit. The circuit820may implement a decision feedback equalizer (DFE).

The circuit810may have a first input that may receive the signal from the coupling106, a second input that may receive the signal BLWC(t), and an output that may present the signal Y(t) to an input of the circuit812. The signal Y(t) may comprise a sum of the signal from the coupling106and the signal BLWC(t). The circuit812may have an output that may present a signal to a first input of the circuit814and an input of the circuit816. The circuit814may have a second input that may receive a signal (e.g., F(t)) and an output that may present a signal (e.g., R(t)). The signal R(t) may comprise a difference between the output of the LE812and the signal F(t). The circuit816may have an input that may receive the signal from the output of the circuit812. The circuit818may have an input that may receive the signal R(t) and an output that may present a signal (e.g., DK). The circuit820may have an input that may receive the signal DK and an output that may present the signal F(t).

Referring toFIG. 13, a flow diagram is shown illustrating a process (or method)1000for correcting baseline wander in accordance with example embodiments of the present invention. The method1000may comprise a step (or state)1002, a step (or state)1004, a step (or state)1006, a step (or state)1008, a step (or state)1010, a step (or state)1012. In the step1002, the process1000may begin by receiving a signal in which the low frequency content is attenuated, for example, due to high pass filtering by a medium carrying the signal and a coupling (e.g., a capacitive coupling, an inductive coupling, a poor electrical contact, etc.). In the step1004, the process1000may take a sample of the received signal, either in the analog domain or the digital domain, at a predefined point in a data recovery pathway after the coupling. In the step1006, the process1000may generate an error signal based upon a detector input (e.g., the received signal) and a detector output (e.g., recovered data). In the step1008, the process1000may low pass filter the signal taken at the predefined point of the signal pathway. In the step1010, the process1000may apply a gain to the low pass filtered signal. The applied gain may be automatically determined based upon the low pass filtered signal (or an equivalent) and the error signal. In the step1012, the process1000may inject the filtered signal with the applied gain into a second predefined point the data recovery pathway after the coupling.

The gain of the low pass filter may be automatically set based upon the filtered signal and the error signal. In one example, adaptation of the gain may be performed using a least mean squares (LMS) or a sign-sign least mean squares technique. In another example, the gain may be automatically adapted based upon channel loss and changes in transmitter de-emphasis setting. The gain adaption may set the gain automatically to minimize the mean squared error (MSE) at the input of the detector. The gain adaption may use the actual filtered signal from a primary low pass filter path or a representative signal generated by a parallel low pass filter path having an equivalent frequency response to the primary low pass filter path. In one example, the actual filtered signal may be sampled using a latch or analog-to-digital converter (ADC) and the sample used in the adaptation loop.

The elements of the invention may form part or all of one or more devices, units, components, systems, machines and/or apparatuses. The devices may include, but are not limited to, servers, workstations, storage array controllers, storage systems, personal computers, laptop computers, notebook computers, palm computers, personal digital assistants, portable electronic devices, battery powered devices, set-top boxes, encoders, decoders, transcoders, compressors, decompressors, pre-processors, post-processors, transmitters, receivers, transceivers, cipher circuits, cellular telephones, digital cameras, positioning and/or navigation systems, medical equipment, heads-up displays, wireless devices, audio recording, storage and/or playback devices, video recording, storage and/or playback devices, game platforms, peripherals and/or multi-chip modules. Those skilled in the relevant art(s) would understand that the elements of the invention may be implemented in other types of devices to meet the criteria of a particular application.