Display device

A display device includes a substrate including a first area and a second area, main pixel groups, auxiliary pixel groups, first signal lines, and second signal lines, wherein a distance between adjacent ones of the first signal lines in the second area gradually decreases toward outer regions of the second area from a center of the second area, and a distance between adjacent ones of the second signal lines in the second area gradually decreases toward the outer regions of the second area from the center of the second area.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims priority to and benefits of Korean Patent Application No. 10-2019-0176263 under 35 U.S.C. § 119, filed on Dec. 27, 2019, in the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference.

BACKGROUND

1. Technical Field

One or more embodiments relate to a display device having enhanced product reliability.

2. Description of Related Art

Display devices have recently been applied to a diverse range of uses. Since the thicknesses and weights of display devices have decreased, the range of use thereof has been widening.

As display devices are being utilized in various ways, the shapes of the display devices may be designed in various ways. Functions that may be combined with or linked to display devices have also increased.

SUMMARY

One or more embodiments include a display device having an area in which a sensor or the like may be arranged or disposed inside of a display area in order to increase functions that may be combined with or linked to such a display device or display devices. However, these objectives are just examples, and the scope of the disclosure is not limited thereby.

According to one or more embodiments, a display device may include a substrate including a first area and a second area, the second area having a transmission area, a plurality of main pixel groups disposed in the first area, a plurality of auxiliary pixel groups disposed in the second area, a plurality of first signal lines that electrically connect the plurality of main pixel groups to the plurality of auxiliary pixel groups, the plurality of first signal lines extending in a first direction, and a plurality of second signal lines that electrically connect the plurality of main pixel groups to the plurality of auxiliary pixel groups, the plurality of second signal lines extending in a second direction intersecting the first direction. A distance between adjacent ones of the plurality of first signal lines in the second area may gradually decrease toward outer portions of the second area from a center of the second area, and a distance between adjacent ones of the plurality of second signal lines in the second area may gradually decrease toward the outer portions of the second area from the center of the second area.

A distance between adjacent ones of the plurality of first signal lines in the first area may be less than or equal to the distance between adjacent ones of the plurality of first signal lines in the second area.

A distance between adjacent ones of the plurality of second signal lines in the first area may be less than or equal to the distance between adjacent ones of the plurality of second signal lines in the second area.

A distance between adjacent ones of the plurality of auxiliary pixel groups disposed in the first direction may gradually decrease toward the outer portions of the second area from the center of the second area.

A distance between adjacent ones of the plurality of auxiliary pixel groups disposed in the second direction may gradually decrease toward the outer portions of the second area from the center of the second area.

A distance between adjacent ones of the plurality of main pixel groups disposed in the first direction may be less than or equal to a distance between adjacent ones of the plurality of auxiliary pixel groups disposed in the first direction.

A distance between adjacent ones of the plurality of main pixel groups disposed in the second direction may be less than or equal to a distance between adjacent ones of the plurality of auxiliary pixel groups disposed in the second direction.

Each of the plurality of auxiliary pixel groups may include a first auxiliary pixel, a second auxiliary pixel, and a third auxiliary pixel that may emit light of different wavelengths.

Each of the plurality of main pixel groups may include a first main pixel, a second main pixel, and a third main pixel that may emit light of different wavelengths.

Each of the plurality of second signal lines may include a first conductive line, a second conductive line, and a third conductive line.

A portion of the first conductive line may be electrically connected to the first auxiliary pixel, a portion of the second conductive line may be electrically connected to the second auxiliary pixel, and a portion of the third conductive line may be electrically connected to the third auxiliary pixel.

The first conductive line may be electrically connected to the first main pixel, the second conductive line may be electrically connected to the second main pixel, and the third conductive line may be electrically connected to the third main pixel.

At least one of the plurality of first signal lines may include first signal lines extending in the first direction and disconnected each other by the second area between the disconnected first signal lines, and the disconnected first signal lines may be electrically connected by connection lines disposed along edges of the second area.

At least one of the plurality of second signal lines may include second signal lines extending in the second direction and disconnected each other by the second area between the disconnected second signal lines, and the disconnected second signal lines may be electrically connected by connection lines disposed along edges of the second area.

According to one or more embodiments, a display device may include a substrate including a first area and a second area, the second area having a transmission area, a plurality of main pixel groups disposed in the first area, a plurality of auxiliary pixel groups disposed in the second area, a plurality of first signal lines that electrically connect the plurality of main pixel groups to the plurality of auxiliary pixel groups, the plurality of first signal lines extending in a first direction, a plurality of second signal lines that electrically connect the plurality of main pixel groups to the plurality of auxiliary pixel groups, the plurality of second signal lines extending in a second direction intersecting the first direction, and a component disposed below the substrate to correspond to the second area and including an electronic element emitting or receiving light, wherein a distance between adjacent ones of the plurality of first signal lines in the second area gradually decreases toward outer portions of the second area from a center of the second area, and a distance between adjacent ones of the plurality of second signal lines in the second area gradually decreases toward the outer portions of the second area from the center of the second area.

A distance between adjacent ones of the plurality of first signal lines in the first area may be less than or equal to a distance between adjacent ones of the plurality of first signal lines in the second area.

A distance between adjacent ones of the plurality of second signal lines in the first area may be less than or equal to a distance between adjacent ones of the plurality of second signal lines in the second area.

A distance between adjacent ones of the plurality of auxiliary pixel groups disposed in the first direction may gradually decrease toward the outer portions of the second area from the center of the second area.

A distance between adjacent ones of the plurality of auxiliary pixel groups disposed in the second direction may gradually decrease toward the outer portions of the second area from the center of the second area.

Each of the plurality of auxiliary pixel groups may include a first auxiliary pixel, a second auxiliary pixel, and a third auxiliary pixel that may emit light of different wavelengths.

Other aspects, features, and advantages than the above-described aspects, features, and advantages will be apparent from the following drawings, the claims, and a detailed description of the disclosure.

DETAILED DESCRIPTION OF THE EMBODIMENTS

Some of the parts which are not associated with the description may not be provided in order to describe embodiments of the disclosure and like reference numerals refer to like elements throughout the specification.

As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items. Throughout the disclosure, the expression “at least one of a, b or c” indicates only a, only b, only c, both a and b, both a and c, both b and c, all of a, b, and c, or variations thereof.

The terms “and” and “or” may be used in the conjunctive or disjunctive sense and may be understood to be equivalent to “and/or.” In the specification and the claims, the phrase “at least one of” is intended to include the meaning of “at least one selected from the group of” for the purpose of its meaning and interpretation. For example, “at least one of A and B” may be understood to mean “A, B, or A and B.”

It will be further understood that when the terms “comprises,” “comprising,” “includes” and/or “including”, “have” and/or “having” are used in this specification, they or it may specify the presence of stated features, integers, steps, operations, elements and/or components, but do not preclude the presence or addition of other features, integers, steps, operations, elements, components, and/or any combination thereof.

When a layer, film, region, substrate, or area, or element is referred to as being “on” another layer, film, region, substrate, or area, or element, it may be directly on the other film, region, substrate, or area, or element, or intervening films, regions, substrates, or areas, or elements may be present therebetween. Conversely, when a layer, film, region, substrate, or area, or element, is referred to as being “directly on” another layer, film, region, substrate, or area, or element, intervening layers, films, regions, substrates, or areas, may be absent therebetween. Further when a layer, film, region, substrate, or area, or element, is referred to as being “below” another layer, film, region, substrate, or area, or element, it may be directly below the other layer, film, region, substrate, or area, or element, or intervening layers, films, regions, substrates, or areas, or elements, may be present therebetween. Conversely, when a layer, film, region, substrate, or area, or element, is referred to as being “directly below” another layer, film, region, substrate, or area, or element, intervening layers, films, regions, substrates, or areas, or elements may be absent therebetween. Further, “over” or “on” may include positioning on or below an object and does not necessarily imply a direction based upon gravity.

In the drawings, sizes and thicknesses of elements may be enlarged for better understanding, clarity, and ease of description thereof. However, the disclosure is not limited to the illustrated sizes and thicknesses. In the drawings, the thicknesses of layers, films, panels, regions, and other elements, may be exaggerated for clarity. In the drawings, for better understanding and ease of description, the thicknesses of some layers and areas may be exaggerated.

Further, in the specification, the phrase “in a plan view” means when an object portion is viewed from above, and the phrase “in a schematic cross-sectional view” means when a schematic cross-section taken by vertically cutting an object portion is viewed from the side.

Additionally, the terms “overlap” or “overlapped” mean that a first object may be above or below or to a side of a second object, and vice versa. Additionally, the term “overlap” may include layer, stack, face or facing, extending over, covering or partly covering or any other suitable term as would be appreciated and understood by those of ordinary skill in the art. The terms “face” and “facing” mean that a first element may directly or indirectly oppose a second element. In a case in which a third element intervenes between the first and second element, the first and second element may be understood as being indirectly opposed to one another, although still facing each other. When an element is described as ‘not overlapping’ or ‘to not overlap’ another element, this may include that the elements are spaced apart from each other, offset from each other, or set aside from each other or any other suitable term as would be appreciated and understood by those of ordinary skill in the art.

It will be understood that when a layer, region, or element is referred to as being “connected to” or “coupled to” another layer, region, or element, it can be directly connected or coupled to the other layer, region, or element or intervening layers, regions, or elements may be present. For example, as used herein, when a layer, region, or element is referred to as being “electrically connected to” another layer, region, or element, it can be directly electrically connected to the other layer, region, or element or intervening layers, intervening regions, or intervening elements may be present.

Also, when an element is referred to as being “in contact” or “contacted” or the like to another element, the element may be in “electrical contact” or in “physical contact” with another element; or in “indirect contact” or in “direct contact” with another element.

FIG. 1is a perspective view schematically illustrating a display device according to an embodiment.

Referring toFIG. 1, a display device1may include a display area DA, in which an image or images may be realized, and a non-display area NDA, in which an image or images may not be realized. The display area DA may include a first area1A and a second area2A, the second area2A having a transmission area TA. The display device1may provide or display a main image or images by using light emitted from main pixels Pm arranged or disposed in the first area1A and may provide or display an auxiliary image or images by using light emitted from auxiliary pixels Pa arranged or disposed in the second area2A.

The second area2A may be an area in which a component including an optical element may be located or disposed thereunder or there below, as will be described below with reference toFIG. 2. The second area2A may include the transmission area TA through which light and/or sound output from a component to the outside or proceeding toward the component from the outside may transmit. In an embodiment, when infrared rays transmit through the second area2A, light transmittance may be equal to or greater than about 30%, as an example, about 50%, about 75%, about 80%, about 85%, or about 90%.

In an embodiment, the auxiliary pixels Pa may be arranged or disposed in the second area2A, and an image or images may be provided from the second area2A by using light emitted from the auxiliary pixels Pa. The image or images provided from the second area2A may be an auxiliary image or images and may have a lower resolution than that of an image or images provided from the first area1A. For example, the second area2A may have the transmission area TA through which light and/or sound may transmit. Thus, the number of auxiliary pixels Pa that may be arranged or disposed per unit area in the second area2A may be less than the number of main pixels Pm arranged or disposed per unit area in the first area1A.

Hereinafter, an organic light-emitting display device will be described as an example of a display device1according to an embodiment. However, the display device according to the disclosure is not limited thereto. In an embodiment, a variety of types of display devices including an inorganic electroluminescent (EL) display device, a quantum dot light-emitting display device, and the like may be used within the spirit and the scope of the disclosure.

InFIG. 1, the second area2A may be at an upper side of the display area DA having a substantially rectangular shape. However, embodiments are not limited thereto. The shape of the display area DA may include a substantially circular shape, a substantially oval shape, or a substantially polygonal shape, such as a triangular shape, and the location of the second area2A and the number of second areas2A may be variously changed.

FIG. 2is a schematic cross-sectional view schematically illustrating a display device according to an embodiment.

Referring toFIG. 2, the display device1may include a display panel10, and an input sensing layer40and an optical functional layer50, which may be arranged or disposed on the display panel10. These elements may be covered or overlapped by a window60. The window60may be combined with an element thereunder or there below, for example, the optical functional layer50through an adhesive layer such as an optically clear adhesive (OCA). The display device1may be provided in a variety of types of electronic devices, such as a mobile phone, a tablet personal computer (PC), a laptop computer, and a smart watch or any other devices within the spirit and the scope of the disclosure.

The display panel10may include diodes arranged or disposed in the display area DA. The input sensing layer40may attain coordinate information according to an external input, for example, a touch event. The input sensing layer40may include a sensing electrode and trace lines electrically connected to the sensing electrode. The input sensing layer40may be arranged or disposed on the display panel10. The input sensing layer40may sense an external input by using a mutual capacitance method or self capacitance method.

The input sensing layer40may be located or disposed directly on the display panel10. Alternatively, the input sensing layer40may be combined with the display panel10through an adhesive layer, such as an OCA. In an embodiment, as shown inFIG. 2, the input sensing layer40may be located or disposed directly on the display panel10. In this case, the adhesive layer may not be disposed between the input sensing layer40and the display panel10.

The optical functional layer50may include an antireflective layer. The antireflective layer may reduce the reflectivity of light (external light) incident toward the display panel10from the outside through the window60. The optical functional layer50may include functional layers, such as a phase retarder and a polarizer. The phase retarder may be of a film type or liquid crystal coating type and may include a λ/2 phase retarder and/or a λ/4 phase retarder. The polarizer may also be of a film type or liquid crystal coating type. The film type may include an elongation-type synthetic resin film, and the liquid crystal coating type may include liquid crystals arranged or disposed in a certain or predetermined arrangement. The phase retarder and the polarizer may include a protective film.

The optical functional layer50may include structures such as a black matrix and color filters. The color filters may be arranged or disposed in consideration of colors of light emitted from the pixels of the display panel10. In an embodiment, the optical functional layer50may include a destructive interference structure. The destructive interference structure may include a first reflective layer and a second reflective layer, which may be arranged or disposed on different layers. First reflected light and second reflected light reflected from the first reflective layer and the second reflective layer, respectively, may destructively interfere. Thus, the reflectivity of external light may be reduced.

The optical functional layer50may include a lens layer. The lens layer may enhance emission efficiency of light emitted from the display panel10or may reduce color deviation. The lens layer may include a layer having a concave or convex lens shape and/or layers having different refractive indices.

The component20may be located or disposed over the second area2A. The component20may be an electronic element transmitting and/or receiving light or sound. For example, the component20may include an optical element, a sensor that may receive and use light, such as an infrared sensor, a sensor that may output or sense light or sound to measure a distance or to recognize a fingerprint, a small lamp that may output light, or a speaker that may output sound.

In an embodiment, when the display device1is used as a smart watch or a vehicle instrument panel, the component20may be a member, such as a watch needle or a needle for indicating information (for example, car speed).

The component20may include a component(s) adding a function to the display device1, as described above, or a component, such as an accessory for increasing an esthetic sense of the display panel10.

FIGS. 3A and 3Bare schematic cross-sectional views schematically illustrating a display device according to an embodiment.

Referring toFIG. 3A, the display device1may include a display panel10including a display element and a component20located or disposed under or below the display panel10to correspond to the second area2A.

The display panel10may include a substrate100, a display element layer200located or disposed on the substrate100, and an encapsulation substrate300athat may be an encapsulation member that may seal the display element layer200. The display panel10may include a lower protective film175located or disposed under or below the substrate100.

The substrate100may include glass or polymer resin. The polymer resin may include polyethersulfone, polyacrylate, polyether imide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, or cellulose acetate propionate. The substrate100including the polymer resin may be flexible, rollable, or bendable. The substrate100may have a multi-layer structure including a layer including the polymer resin described above and an inorganic layer (not shown).

The display element layer200may include a circuit layer including thin-film transistors TFT and TFT′, organic light-emitting diodes OLED and OLED′ as display elements, and an insulating layer IL therebetween. Main pixels Pm including a main thin-film transistor TFT and a main organic light-emitting diode OLED electrically connected thereto may be arranged or disposed in the first area1A, and auxiliary pixels Pa including an auxiliary thin-film transistor TFT′ and an auxiliary organic light-emitting diode OLED′ electrically connected thereto may be arranged or disposed in the second area2A.

The transmission area TA, in which the auxiliary thin-film transistor TFT′ and the display element may not be arranged or disposed, may be provided or disposed in the second area2A. The transmission area TA may be understood as an area in which light/a signal emitted from the component20or light/a signal incident toward the component20transmits.

The display element layer200may be covered or overlapped by the encapsulation substrate300a. The encapsulation substrate300amay include a glass material. For example, the encapsulation substrate300amay include a glass material having a main component of silicon oxide (SiO2). The encapsulation substrate300amay face the substrate100, and a sealant ST may be disposed between the substrate100and the encapsulation substrate300a. The sealant ST may be located or disposed on edges of the substrate100and may entirely surround the display element layer200between the substrate100and the encapsulation substrate300a. When viewed from a direction perpendicular to a top surface of the substrate100(or on a plan view), the first area1A and the second area2A may be entirely surrounded by the sealant ST.

Referring toFIG. 3B, the display element layer200may be covered or overlapped by a thin-film encapsulation layer300b. The thin-film encapsulation layer300bmay include at least one inorganic encapsulation layer and at least one organic encapsulation layer. In this regard,FIG. 3Billustrates first and second inorganic encapsulation layers310and330and an organic encapsulation layer320disposed therebetween.

The first and second inorganic encapsulation layers310and330may include one or more inorganic insulating materials of aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, zinc oxide, silicon oxide, silicon nitride, and silicon oxynitride. The organic encapsulation layer320may include a polymer-based material. The polymer-based material may include acryl-based resin, epoxy-based resin, polyimide, and polyethylene.

The lower protective film175may be attached or adhered to a lower portion of the substrate100and may support and protect the substrate100. The lower protective film175may include an opening1750P corresponding to the second area2A. The opening1750P may be provided in the lower protective film175so that light transmittance of the second area2A may be increased. The lower protective film175may include polyethylene terephthalate or polyimide, by way of example.

The area of the second area2A may be greater than an area in which the component20may be located or disposed. Thus, the area of the opening1750P provided in the lower protective film175may be different from the area of the second area2A. For example, the area of the opening1750P may be less than the area of the second area2A.

Components20may be arranged or disposed in the second area2A. The components20may have different functions.

FIG. 4is a plan view schematically illustrating a display device according to an embodiment.

Referring toFIG. 4, a variety of components that constitute the display device1may be arranged or disposed on the substrate100. The substrate100may include a display area DA and a non-display area NDA surrounding or adjacent to the display area DA. The display area DA may include a first area1A and a second area2A. The display area DA may be covered or overlapped by the encapsulation member described with reference toFIGS. 3A and 3Bdescribed above and may be protected from external air or moisture.

The display device1may include main pixels Pm arranged or disposed in the first area1A. Each of the main pixels Pm may include a display element, such as an organic light-emitting diode. Each main pixel Pm may emit red, green, blue, or white light, for example, from the organic light-emitting diode. The main pixel Pm in the specification may be understood as a pixel that may emit light of any one of red, green, blue, and white colors, as described above.

The second area2A may be located or disposed at a side of the first area1A, and auxiliary pixels Pa may be arranged or disposed in the second area2A. Each of the auxiliary pixels Pa may include a display element, such as an organic light-emitting diode. Each auxiliary pixel Pa may emit red, green, blue, or white light, for example, from the organic light-emitting diode. The auxiliary pixel Pa used herein may be understood as a pixel that may emit light of any one of red, green, blue, and white colors, as described above. The transmission area TA may be in the second area2A and may be arranged or disposed between the auxiliary pixels Pa. At least one component20may be arranged or disposed to correspond to a lower portion of the second area2A of the display device1.

In an embodiment, one main pixel Pm and one auxiliary pixel Pa may include the same pixel circuit. However, embodiments are not limited thereto. A pixel circuit included in the main pixel Pm and a pixel circuit included in the auxiliary pixel Pa may also be different from each other.

Because the second area2A may include the transmission area TA, the resolution of the second area2A may be lower than that of the first area1A. For example, the resolution of the second area2A may be about ½ of the resolution of first area1A. In an embodiment, the resolution of the first area1A may be about 400 ppi or higher, and the resolution of the second area2A may be about 100 ppi.

Each of the main and auxiliary pixels Pm and Pa may be electrically connected to outer circuits arranged or disposed in the non-display area NDA. A first scan driving circuit110, a first emission driving circuit115, a second scan driving circuit120, a terminal140, a data driving circuit150, a first power supply line160, and a second power supply line170may be arranged or disposed in the non-display area NDA.

The first scan driving circuit110may provide a scan signal to each of the main and auxiliary pixels Pm and Pa through the scan line SL. The first emission driving circuit115may provide an emission control signal to each pixel through the emission control line EL. The second scan driving circuit120may be arranged or disposed in parallel to the first scan driving circuit110with the display area DA therebetween. Part of the main and auxiliary pixels, Pm and Pa, arranged or disposed in the display area DA may be electrically connected to the first scan driving circuit110, and the other part thereof may be electrically connected to the second scan driving circuit120. In an embodiment, a second emission driving circuit (not shown) may be arranged or disposed in parallel to the first emission driving circuit115with the display area DA therebetween.

The first emission driving circuit115may be apart from the first scan driving circuit110in an x-direction and may be arranged or disposed in the non-display area NDA. In an embodiment, the first emission driving circuit115may be alternately arranged or disposed in a y-direction with the first scan driving circuit110.

The terminal140may be arranged or disposed at a side of the substrate100. The terminal140may not be covered or overlapped by an insulating layer but may be exposed and thus may be electrically connected to a printed circuit board PCB. A terminal PCB-P of the printed circuit board PCB may be electrically connected to the terminal140of the display device1. The printed circuit board PCB may transmit a signal or power of a controller (not shown) to the display device1. A control signal generated by the controller (not shown) may be transmitted to the first scan driving circuit110, the first emission driving circuit115, and the second scan driving circuit120through the printed circuit board PCB. The controller (not shown) may provide a first power supply voltage and a second power supply voltage to the first power supply line160and the second power supply line170through a first connection line161and a second connection line171, respectively. A first power supply voltage ELVDD may be provided to each of the main and auxiliary pixels Pm and Pa through a driving voltage line PL electrically connected to the first power supply line160, and a second power supply voltage ELVSS may be provided to an opposite electrode of each of the main and auxiliary pixels Pm and Pa electrically connected to the second power supply line170.

The data driving circuit150may be electrically connected to the data line DL. A data signal of the data driving circuit150may be provided to each of the main and auxiliary pixels, Pm and Pa, through a connection line151electrically connected to the terminal140and the data line DL electrically connected to the connection line151.FIG. 4illustrates that the data driving circuit150may be arranged or disposed on the printed circuit board PCB. However, in an embodiment, the data driving circuit150may be arranged or disposed on the substrate100. For example, the data driving circuit150may be arranged or disposed between the terminal140and the first power supply line160.

The first power supply line160may include a first sub-line162and a second sub-line163, which may extend in parallel to each other in the x-direction, with the display area DA between the first sub-line162and the second sub-line163. The second power supply line170may have a substantially loop shape with one open side and may partially surround the display area DA.

FIGS. 5 and 6are equivalent circuit diagrams of pixels that may be included in a display device according to an embodiment.

Referring toFIG. 5, each of the main and auxiliary pixels Pm and Pa may include a pixel circuit PC electrically connected to the scan line SL and the data line DL and an organic light-emitting diode OLED electrically connected to the pixel circuit PC.

The pixel circuit PC may include a driving thin-film transistor T1, a switching thin-film transistor T2, and a storage capacitor Cst. The switching thin-film transistor T2may be electrically connected to the scan line SL and the data line DL and may transmit a data signal Dm input through the data line DL according to a scan signal Sn input through the scan line SL to the driving thin-film transistor T1.

The storage capacitor Cst may be electrically connected to the switching thin-film transistor T2and the driving voltage line PL and may store a voltage corresponding to a difference between a voltage transmitted from the switching thin-film transistor T2and the first power supply voltage (or a driving voltage) ELVDD supplied to the driving voltage line PL.

The driving thin-film transistor T1may be electrically connected to the driving voltage line PL and the storage capacitor Cst and may control a driving current that flows through the organic light-emitting diode OLED from the driving voltage line PL in correspondence with a voltage value stored in the storage capacitor Cst. The organic light-emitting diode OLED may emit light having certain brightness according to the driving current.

InFIG. 5, the pixel circuit PC includes two thin-film transistors and one storage capacitor. However, embodiments are not limited thereto. As shown inFIG. 6, the pixel circuit PC may include seven thin-film transistors and one storage capacitor.

Referring toFIG. 6, each of the main and auxiliary pixels Pm and Pa may include a pixel circuit PC and an organic light-emitting diode OLED electrically connected to the pixel circuit PC. The pixel circuit PC may include thin-film transistors and a storage capacitor. The thin-film transistors and the storage capacitor may be electrically connected to signal lines SL, SL-1, EL and DL, an initialization voltage line VL, and the driving voltage line PL.

InFIG. 6, each of the main and auxiliary pixels Pm and Pa may be electrically connected to the signal lines SL, SL-1, EL and DL, the initialization voltage line VL, and the driving voltage line PL. However, embodiments are not limited thereto. In an embodiment, at least one of the signal lines SL, SL-1, EL and DL, the initialization voltage line VL, and the driving voltage line PL may be shared in adjacent pixels.

The thin-film transistors may include a driving thin-film transistor TFT T1, a switching TFT T2, a compensation TFT T3, a first initialization TFT T4, an operation control TFT T5, an emission control TFT T6, and a second initialization TFT T7.

The signal lines may include the signal line SL that may transmit the scan signal Sn, a previous scan line SL-1that may transmit the previous scan signal Sn-1to the first initialization TFT T4and the second initialization TFT T7, the emission control line EL that may transmit the emission control signal En to the operation control TFT T5and the emission control TFT T6, and the data line DL intersecting with the scan line SL and transmitting the data signal Dm. The driving voltage line PL may transmit the first power supply voltage (or driving voltage) ELVDD to the driving TFT T1, and the initialization voltage line VL may transmit the initialization voltage Vint that may initialize the driving TFT T1and a pixel electrode of the organic light-emitting diode OLED.

A driving gate electrode G1of the driving TFT T1may be electrically connected to a first storage capacitor plate Cst1of the storage capacitor Cst, a driving source electrode S1of the driving TFT T1may be electrically connected to the driving voltage line PL via the operation control TFT T5, and a driving drain electrode D1of the driving TFT T1may be electrically connected to the pixel electrode of the organic light-emitting diode OLED via the emission control TFT T6. The driving TFT T1may supply a driving current IDLED to the organic light-emitting diode OLED by receiving the data signal Dm according to a switching operation of the switching TFT T2.

A switching gate electrode G2of the switching TFT T2may be electrically connected to the scan line SL, a switching source electrode S2of the switching TFT T2may be electrically connected to the data line DL, and a switching drain electrode D2of the switching TFT T2may be electrically connected to the driving source electrode S1of the driving TFT T1and may be electrically connected to the driving voltage line PL via the operation control TFT T5. The switching TFT T2may be turned on according to the scan signal Sn received through the scan line SL and may perform a switching operation of transmitting the data signal Dm transmitted to the data line DL to the driving source electrode S1of the driving TFT T1.

A compensation gate electrode G3of the compensation TFT T3may be electrically connected to the scan line SL, a compensation source electrode S3of the compensation TFT T3may be electrically connected to the driving drain electrode D1of the driving TFT T1and electrically connected to the pixel electrode of the organic light-emitting diode OLED via the emission control TFT T6, a compensation drain electrode D3of the compensation TFT T3may be electrically connected to the first storage capacitor plate Cst1of the storage capacitor Cst, the first initialization drain electrode D4of the first initialization TFT T4, and the driving gate electrode G1of the driving TFT T1. The compensation TFT T3may be turned on according to the scan signal Sn transmitted through the scan line SL and may electrically connect the driving gate electrode G1to the driving drain electrode D1of the driving TFT T1, thereby diode-connecting the driving TFT T1.

A first initialization gate electrode G4of the first initialization TFT T4may be electrically connected to the previous scan line SL-1, a first initialization source electrode S4of the first initialization TFT T4may be electrically connected to a second initialization drain electrode D7of the second initialization TFT T7and the initialization voltage line VL, and a first initialization drain electrode D4of the first initialization TFT T4may be electrically connected to the first storage capacitor plate Cst1of the storage capacitor Cst, the compensation drain electrode D3of the compensation TFT T3, and the driving gate electrode G1of the driving TFT T1. The first initialization TFT T4may be turned on according to the previous scan signal Sn-1transmitted through the previous scan line SL-1and may perform an initialization operation of initializing a voltage of the driving gate electrode G1of the driving TFT T1by transmitting the initialization voltage Vint to the driving gate electrode G1of the driving TFT T1.

An operation control gate electrode G5of the operation control TFT T5may be electrically connected to the emission control line EL, an operation control source electrode S5of the operation control TFT T5may be electrically connected to the driving voltage line PL, and an operation control drain electrode D5of the operation control TFT T5may be electrically connected to the driving source electrode S1of the driving TFT T1and the switching drain electrode D2of the switching TFT T2.

An emission control gate electrode G6of the emission control TFT T6may be electrically connected to the emission control line EL, an emission control source electrode S6of the emission control TFT T6may be electrically connected to the driving drain electrode D1of the driving TFT T1and the compensation source electrode S3of the compensation TFT T3, and an emission control drain electrode D6of the emission control TFT T6may be electrically connected to the second initialization source electrode S7of the second initialization TFT T7and the pixel electrode of the organic light-emitting diode OLED.

The operation control TFT T5and the emission control TFT T6may be simultaneously turned on according to the emission control signal En transmitted through the emission control line EL such that the first power supply voltage (driving voltage) ELVDD may be transmitted to the organic light-emitting diode OLED and thus the driving current IDLED may flow through the organic light-emitting diode OLED.

A second initialization gate electrode G7of the second initialization TFT T7may be electrically connected to the previous scan line SL-1, a second initialization source electrode S7of the second initialization TFT T7may be electrically connected to the emission control drain electrode D6of the emission control TFT T6and the pixel electrode of the organic light-emitting diode OLED, and a second initialization drain electrode D7of the second initialization TFT T7may be electrically connected to the first initialization source electrode S4of the first initialization TFT T4and the initialization voltage line VL. The second initialization TFT T7may be turned on according to the previous scan signal Sn-1transmitted through the previous scan line SL-1and may initialize the pixel electrode of the organic light-emitting diode OLED.

InFIG. 6, the first initialization TFT T4and the second initialization TFT T7may be electrically connected to the previous scan line SL-1. However, embodiments are not limited thereto. In an embodiment, the first initialization TFT T4may be electrically connected to the previous scan line SL-1and may be driven according to the previous scan signal Sn-1, and the second initialization TFT T7may be electrically connected to an additional signal line (for example, a subsequent scan line) and thus may be driven according to a signal transmitted to the signal line.

A second storage capacitor plate Cst2of the storage capacitor Cst may be electrically connected to the driving voltage line PL, and the opposite electrode of the organic light-emitting diode OLED may be electrically connected to the second power supply voltage (or a common voltage) ELVSS. Thus, the organic light-emitting diode OLED may receive the driving current IDLED from the driving TFT T1and may emit light, thereby displaying an image or images.

InFIG. 6, the compensation TFT T3and the first initialization TFT T4may have a dual gate electrode. However, the compensation TFT T3and the first initialization TFT T4may have one gate electrode.

In an embodiment, the main pixel Pm and the auxiliary pixel Pa may have the same pixel circuit PC. However, embodiments are not limited thereto. The main pixel Pm and the auxiliary pixel Pa may also have pixel circuits PC having different structures. There may be a variety of modifications, wherein, for example, the main pixel Pm may employ the pixel circuit PC ofFIG. 6, and the auxiliary pixel Pa may employ the pixel circuit PC ofFIG. 5.

FIGS. 7A and 7Bare schematic cross-sectional views of a main pixel and an auxiliary pixel that may be included in a display device according to an embodiment. In more detail,FIG. 7Ais a schematic cross-sectional view of the main pixel Pm, andFIG. 7Bis a schematic cross-sectional view of the auxiliary pixel Pa.

Hereinafter, a stack structure of a display device according to an embodiment will be described with reference toFIGS. 7A and 7B.

Referring toFIG. 7A, the display device1may include thin-film transistors TFT and TFT′ arranged or disposed on the substrate100and organic light-emitting diodes OLED and OLED′. The substrate100may include a glass material or polymer resin having a main component of silicon oxide (SiO2). The polymer resin may include polyethersulfone, polyacrylate, polyether imide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, or cellulose acetate propionate. The substrate100including the polymer resin may be flexible, rollable, or bendable. The substrate100may have a multi-layer structure including a layer including the above-described polymer resin and an inorganic layer (not shown).

The buffer layer101may be arranged or disposed on the substrate100, may reduce or prevent the penetration of foreign substances, moisture, or external air from a lower portion of the substrate100, and may provide a flat surface to the substrate100. The buffer layer101may include an inorganic material, such as oxide or nitride, an organic material, or an organic/inorganic composite material and may have a single layer or multi-layer structure of an inorganic material and an organic material. A barrier layer (not shown) that may prevent the penetration of external air may be provided or disposed between the substrate100and the buffer layer101.

A main thin-film transistor TFT and an auxiliary thin-film transistor TFT′ may be arranged or disposed on the buffer layer101. The main thin-film transistor TFT may include a main semiconductor layer134a, a main gate electrode136a, a main source electrode137a, and a main drain electrode138a, and the auxiliary thin-film transistor TFT′ may include an auxiliary semiconductor layer134b, an auxiliary gate electrode136b, an auxiliary source electrode137b, and an auxiliary drain electrode138b. The main thin-film transistor TFT may be electrically connected to the main organic light-emitting diode OLED in the first area1A and may drive the main organic light-emitting diode OLED. The auxiliary thin-film transistor TFT′ may be electrically connected to the auxiliary organic light-emitting diode OLED′ in the second area2A and may drive the auxiliary organic light-emitting diode OLED′.

The main semiconductor layer134amay be arranged or disposed on the buffer layer101and may include a main channel region131a, a main source region132a, and a main drain region133a, wherein the main channel region131amay overlap the main gate electrode136a, and the main source region132aand the main drain region133amay each be at both sides of the main channel region131aand may include impurities having higher concentrations than those of the main channel region131a. The auxiliary semiconductor layer134bmay be arranged or disposed on the buffer layer101and may include an auxiliary channel region131b, an auxiliary source region132b, and an auxiliary drain region133b, wherein the auxiliary channel region131bmay overlap the auxiliary gate electrode136b, and the auxiliary source region132band the auxiliary drain region133beach may be at both sides of the auxiliary channel region131band may include impurities having higher concentrations than those of the auxiliary channel region131b. Here, the impurities may include N-type impurities or P-type impurities. Each of the main and auxiliary source regions132aand132band the main and auxiliary drain regions133aand133bmay be electrically connected to each of the main and auxiliary source electrodes137aand137band the main and auxiliary drain electrodes138aand138bof the main and auxiliary thin-film transistors TFT and TFT′.

The main semiconductor layer134aand the auxiliary semiconductor layer134bmay include an oxide semiconductor and/or a silicon semiconductor. When the main semiconductor layer134aand the auxiliary semiconductor layer134bare formed of an oxide semiconductor, the main semiconductor layer134aand the auxiliary semiconductor layer134bmay include an oxide formed of at least one of materials, such as indium (In), gallium (Ga), tin (Sn), zirconium (Zr), vanadium (V), hafnium (Hf), cadmium (Cd), germanium (Ge), chromium (Cr), titanium (Ti), and zinc (Zn). For example, the main semiconductor layer134aand the auxiliary semiconductor layer134bmay include InSnZnO (ITZO) and InGaZnO (IGZO), and the like within the spirit and the scope of the disclosure. When the main semiconductor layer134aand the auxiliary semiconductor layer134binclude a silicon semiconductor, the main semiconductor layer134aand the auxiliary semiconductor layer134bmay include amorphous silicon (a-Si) or low temperature poly-silicon (LTPS) formed by crystallizing a-Si.

The main gate electrode136aand the auxiliary gate electrode136bmay be formed of one or more metals of aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and copper (Cu) and may have a single layer or multi-layer structure. The main gate electrode136aand the auxiliary gate electrode136bmay be electrically connected to a gate line that may apply an electrical signal to the main gate electrode136aand the auxiliary gate electrode136b.

A first insulating layer103may be disposed between the main semiconductor layer134aand the main gate electrode136aand between the auxiliary semiconductor layer134band the auxiliary gate electrode136b. The first insulating layer103may include at least one inorganic insulating material of silicon oxide (SiO2), silicon nitride (SiNx), silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), and zinc oxide (ZnO2). The first insulating layer103may have a single layer or multi-layer structure including the inorganic insulating materials described above.

A second insulating layer105may be provided or disposed on the first insulating layer103to cover or overlap the main gate electrode136aand the auxiliary gate electrode136b. The second insulating layer105may include at least one inorganic insulating material of silicon oxide (SiO2), silicon nitride (SiNx), silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), and zinc oxide (ZnO2). The second insulating layer105may have a single layer or multi-layer structure including the inorganic insulating materials described above.

A main storage capacitor Cst and an auxiliary storage capacitor Cst′ may be arranged or disposed on the second insulating layer105. The main storage capacitor Cst may include a main lower electrode144aand a main upper electrode146a, the main storage capacitor Cst may overlap the main thin-film transistor TFT, the main lower electrode144aof the main storage capacitor Cst may be arranged or disposed as a one body with the main gate electrode136aof the main thin-film transistor TFT. In an embodiment, the main storage capacitor Cst may not overlap the main thin-film transistor TFT, and the main lower electrode144aof the main storage capacitor Cst may be an independent element formed separately from the main gate electrode136aof the main thin-film transistor TFT. The auxiliary storage capacitor Cst′ may include an auxiliary lower electrode144band an auxiliary upper electrode146b. The auxiliary storage capacitor Cst′ may overlap the auxiliary thin-film transistor TFT′, and the auxiliary lower electrode144bof the auxiliary storage capacitor Cst′ may be arranged or disposed as a one body with the auxiliary gate electrode136bof the auxiliary thin-film transistor TFT′. In an embodiment, the auxiliary storage capacitor Cst′ may not overlap the auxiliary thin-film transistor TFT′, and the auxiliary lower electrode144bmay be an independent element formed separately from the auxiliary gate electrode136bof the auxiliary thin-film transistor TFT′.

A third insulating layer107may be formed or disposed to cover or overlap the main upper electrode146aand the auxiliary upper electrode146b. The third insulating layer107may include silicon oxide (SiO2), silicon nitride (SiNx), silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), or zinc oxide (ZnO2).

The main and auxiliary source electrodes137aand137band the main and auxiliary drain electrodes138aand138bmay be arranged or disposed on the third insulating layer107. The main and auxiliary source electrodes137aand137band the main and auxiliary drain electrodes138aand138bmay include conductive materials including Mo, Al, Cu, and Ti and may have a multi-layer or single layer structure including the materials described above. In an example, the main and auxiliary source electrodes137aand137band the main and auxiliary drain electrodes138aand138bmay have a multi-layer structure of Ti/Al/Ti.

A planarization layer113may be arranged or disposed to cover or overlap the main and auxiliary source electrodes137aand137band the main and auxiliary drain electrodes138aand138b. The planarization layer113may have a flat top surface so that the pixel electrode of the organic light-emitting diode OLED arranged or disposed on the planarization layer113may be formed substantially flat.

The planarization layer113may include a layer including an organic material or an inorganic material and may have a single layer or multi-layer structure. The planarization layer113may include a general-purpose polymer such as benzocyclobutene (BCB), polyimide, hexamethyldisiloxane (HMDSO), polymethylmethacrylate (PMMA), or polystyrene (PS), a polymer derivative having a phenol-based group, acryl-based polymer, imide-based polymer, aryl ether-based polymer, amide-based polymer, fluorine-based polymer, p-xylene-based polymer, vinyl alcohol-based polymer, and/or a blend thereof. The planarization layer113may include silicon oxide (SiO2), silicon nitride (SiNx), silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), or zinc oxide (ZnO2). After the planarization layer113is formed or disposed, chemical mechanical polishing may be performed to provide a flat top surface to the planarization layer113.

The planarization layer113may have an opening that may expose any one of the main source electrode137aand the main drain electrode138aof the main thin-film transistor TFT. A main pixel electrode210amay be in electrical contact with the main source electrode137aor the main drain electrode138athrough the opening and may be electrically connected to the main thin-film transistor TFT.

The planarization layer113may have an opening that may expose any one of the auxiliary source electrode137band the auxiliary drain electrode138bof the auxiliary thin-film transistor TFT′. An auxiliary pixel electrode210bmay be in electrical contact with the auxiliary source electrode137bor the auxiliary drain electrode138bthrough the opening and may be electrically connected to the auxiliary thin-film transistor TFT′.

In the first area1A of the substrate100, a main organic light-emitting diode OLED may be positioned or disposed on the planarization layer113, the main organic light-emitting diode OLED including the main pixel electrode210a, a main intermediate layer220a, and a main opposite electrode230afacing the main pixel electrode210awith the main intermediate layer220adisposed between the main pixel electrode210aand the main opposite electrode230a.

In the second area2A of the substrate100, an auxiliary organic light-emitting diode OLED′ may be positioned or disposed on the planarization layer113, the auxiliary organic light-emitting diode OLED′ including the auxiliary pixel electrode210b, an auxiliary intermediate layer220b, and an auxiliary opposite electrode230bfacing the auxiliary pixel electrode210bwith the auxiliary intermediate layer220bdisposed between the auxiliary pixel electrode210band the auxiliary opposite electrode230b.

The main pixel electrode210aand the auxiliary pixel electrode210bmay be arranged or disposed on the planarization layer113. The main pixel electrode210aand the auxiliary pixel electrode210bmay include a semi-transparent, a transparent electrode or a reflective electrode. The main pixel electrode210aand the auxiliary pixel electrode210bmay include a reflective layer formed of Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, and/or a compound thereof, and a transparent or semi-transparent electrode layer formed or disposed on the reflective layer. The transparent or semi-transparent electrode layer may include at least one of indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In2O3), indium gallium oxide (IGO), and aluminum zinc oxide (AZO). The main pixel electrode210aand the auxiliary pixel electrode210bmay have a stack structure of ITO/Ag/ITO.

A pixel-defining layer180may be arranged or disposed on the planarization layer113. The pixel-defining layer180may have an opening that may expose at least part of the main pixel electrode210aand an opening that may expose at least part of the auxiliary pixel electrode210b. The pixel-defining layer180may increase a distance between edges of the main pixel electrode210aand the main opposite electrode230aon the main pixel electrode210a, thereby preventing an arc from occurring in the edges of the main pixel electrode210aand may increase a distance between edges of the auxiliary pixel electrode210band the auxiliary opposite electrode230bon the auxiliary pixel electrode210b, thereby preventing an arc from occurring in the edges of the auxiliary pixel electrode210b. The pixel-defining layer180may be formed of organic insulating materials, such as polyimide, polyamide, acryl resin, BCB, HMDSO, and phenol resin, by using a method such as spin coating, for example.

The main intermediate layer220amay be arranged or disposed on the main pixel electrode210a, wherein at least part of the main pixel electrode210amay be exposed by the pixel-defining layer180, and the auxiliary intermediate layer220bmay be arranged or disposed on the auxiliary pixel electrode210b. The main intermediate layer220aand the auxiliary intermediate layer220bmay include a light-emitting layer and optionally, although not illustrated, may include functional layers, such as a hole transport layer (HTL), a hole injection layer (HIL), an electron transport layer (ETL), and an electron injection layer (EIL), which may be arranged or disposed under or below and on the light-emitting layer.

The light-emitting layer may include an organic material including a fluorescent or phosphorescent material that may emit red, green, blue, or white light. The light-emitting layer may include a small molecular weight organic material or polymer organic material.

When the light-emitting layer includes a small molecular weight material, the main intermediate layer220aand the auxiliary intermediate layer220bmay have a structure in which, although not illustrated, an HIL, an HTL, an emission layer (EML), an ETL and an EIL may be stacked in a single or composite structure, and the small molecular weight organic material may include a variety of organic materials, such as copper phthalocyanine (CuPc), N,N′-Di(napthalene-1-yl)-N,N′-diphenyl-benzidine (NPB), and tris-8-hydroxyquinoline aluminum)(Alq3). These layers may be formed by using a method such as vacuum deposition, for example.

When the light-emitting layer includes a polymer material, the main intermediate layer220aand the auxiliary intermediate layer220bmay have a structure usually including an HTL and an EML. In this case, the HTL may include poly-(3,4)-ethylene-dihydroxy thiophene (PEDOT), and the light-emitting layer may include a poly-phenylene vinylene (PPV)-based or polyfluorene-based polymer material. The light-emitting layer may be formed by using screen printing, inkjet printing, or laser induced thermal imaging (LITI), for example.

The main opposite electrode230amay be arranged or disposed on the main intermediate layer220a. The main opposite electrode230amay be arranged or disposed on the main intermediate layer220ato entirely cover or overlap the main intermediate layer220a. The main opposite electrode230amay be arranged or disposed over the first area1A to entirely cover or overlap the first area1A. For example, the main opposite electrode230amay be formed as a one body to cover or overlap the main pixels Pm arranged or disposed in the first area1A.

The auxiliary opposite electrode230bmay be arranged or disposed on the auxiliary intermediate layer220b. The auxiliary opposite electrode230bmay be arranged or disposed on the auxiliary intermediate layer220bto entirely cover or overlap the auxiliary intermediate layer220b. The auxiliary opposite electrode230bmay be arranged or disposed over the second area2A to entirely cover or overlap the second area2A. For example, the auxiliary opposite electrode230bmay be formed as a one body to cover or overlap the auxiliary pixels Pa arranged or disposed in the second area2A and may also be arranged or disposed on a transmission area TA provided or disposed in the second area2A. As an example, the auxiliary opposite electrode230bmay be formed or disposed to cover or overlap the auxiliary pixels Pa in the second area2A but may not be arranged or disposed on the transmission area TA in the second area2A.

In an embodiment, the main opposite electrode230aand the auxiliary opposite electrode230bmay be formed as one body. For example, the main opposite electrode230ain the first area1A may extend into the second area2A and may be arranged or disposed even in the second area2A.

The main opposite electrode230aand the auxiliary opposite electrode230bmay include a conductive material having a small work function. For example, the main opposite electrode230aand the auxiliary opposite electrode230bmay include a (semi-)transparent layer including Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, Li, Ca, or an alloy thereof. Alternatively, the main opposite electrode230aand the auxiliary opposite electrode230bmay include a layer such as ITO, IZO, ZnO, or In2O3on the (semi-)transparent layer including the materials described above.

The main organic light-emitting diode OLED and the auxiliary organic light-emitting diode OLED′ may be covered or overlapped by the encapsulation substrate300a. The encapsulation substrate300amay include a glass material. For example, the encapsulation substrate300amay include a glass material having a main component of SiO2. The encapsulation substrate300amay face the substrate100.

The embodiment ofFIG. 7Bmay be different from the embodiment ofFIG. 7Ain that the display element layer may be covered or overlapped by the thin-film encapsulation layer300b. A description of the same configuration ofFIG. 7Bas that ofFIG. 7Awill be omitted, and hereinafter, only a difference therebetween will be described.

Referring toFIG. 7B, the display element layer may be covered or overlapped by the thin-film encapsulation layer300b. The thin-film encapsulation layer300bmay include at least one inorganic encapsulation layer and at least one organic encapsulation layer. In an embodiment, the thin-film encapsulation layer300bmay include first and second inorganic encapsulation layers310and330and an organic encapsulation layer320disposed therebetween.

Each of the first and second inorganic encapsulation layers310and330may include one or more inorganic insulating materials. The inorganic insulating materials may include aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, zinc oxide, silicon oxide, silicon nitride, and/or silicon oxynitride. The organic encapsulation layer320may include a polymer-based material. The polymer-based material may include acryl-based resin, epoxy-based resin, polyimide, and/or polyethylene. For example, the organic encapsulation layer320may include acryl-based resin, for example, polymethylmethacrylate, polyacrylic acid, and the like within the spirit and the scope of the disclosure.

When the display panel includes the thin-film encapsulation layer300bas an encapsulation member that may cover or overlap the display element layer, the display panel may have a smaller thickness or may be thinner than the thickness of the display panel described above inFIG. 7A.

FIG. 8is a plan view schematically illustrating a display device according to an embodiment. InFIG. 8, for convenience of illustration and explanation, seven gate lines and seven data lines may be arranged or disposed in the second area2A. However, each of the number of gate lines and the number of data lines may be substantially seven or more.

Referring toFIG. 8, the display device1according to an embodiment may include a substrate100including a first area1A and a second area2A having a transmission area TA, main pixel groups Pgm arranged or disposed in the first area1A, auxiliary pixel groups Pga arranged or disposed in the second area2A, first signal lines that may electrically connect the main pixel groups Pgm to the auxiliary pixel groups Pga and may extend in a first direction (x-direction), and second signal lines that may electrically connect the main pixel groups Pgm to the auxiliary pixel groups Pga and may extend in a second direction (y-direction) crossing or intersecting the first direction (x-direction).

In an embodiment, the first signal lines that may extend in the first direction (x-direction) may be gate lines GL1through GL16, and the second signal lines that may extend in the second direction (y-direction) may be data lines DL1through DL15. Each of the main pixel groups Pgm may include the main pixels Pm described above, and each of the auxiliary pixel groups Pga may include the auxiliary pixels Pa described above. For example, the gate lines GL1through GL16that may extend in the first direction (x-direction) may transmit the scan signal, the previous scan signal, and the emission control signal to the main pixels Pm and the auxiliary pixels Pa, and the data lines DL1through DL15may transmit the data signal and the driving voltage to the main pixels Pm and the auxiliary pixels Pa.

In an existing display device, there may be a problem that the gate lines extending in the first direction and the data lines extending in the second direction may be arranged or disposed in the second area having the transmission area by a certain or predetermined distance to form grating patterns. The grating patterns formed with the gate lines and the data lines may act as a diffraction grating and thus a blur image may be output when light emitted from a component (for example, an optical element) passes through the diffraction grating and is diffracted.

In order to solve the above-described problem, the disclosure may provide a display device having enhanced product reliability in which, in the second area2A having the transmission area, a distance between the gate lines extending in the first direction (x-direction) and a distance between the data lines extending in the second direction (y-direction) may gradually decrease toward outer portions of the second area2A from the center of the second area2A such that the gate lines and the data lines may be prevented from acting as a diffraction grating.

A distance between the gate lines GL2, GL4, GL6, GL8, GL10, GL12, and GL14extending in the first direction (x-direction) in the second area2A may gradually decrease toward the outer portions of the second area2A from the center of the second area2A. As an example, a distance between closest gate lines may gradually decrease toward the second gate line GL2and the fourteenth gate line GL14arranged or disposed at the outer portions of the second area2A from the eighth gate line GL8arranged or disposed substantially in the center of the second area2A in the first direction (x-direction). In an embodiment, a first distance d1between the eighth gate line GL8and the tenth gate line GL10arranged or disposed substantially in the center of the second area2A in the first direction (x-direction) may be greater than a second distance d2between the tenth gate line GL10and a twelfth gate line GL12.

A distance between the data lines DL2, DL4, DL6, DL8, DL10, DL12, and DL14extending in the second direction (y-direction) in the second area2A may gradually decrease toward the outer portions of the second area2A from the center of the second area2A. As an example, a distance between closest data lines may gradually decrease toward the second data line DL2and the fourteenth data line DL14arranged or disposed at the outer portions of the second area2A from the eighth data line DL8arranged or disposed substantially in the center of the second area2A in the second direction (y-direction). In an embodiment, a third distance d3between the eighth data line DL8and the tenth data line DL10arranged or disposed substantially in the center of the second area2A in the second direction (y-direction) may be greater than a fourth distance d4between the tenth data line DL10and a twelfth data line DL12.

A distance between adjacent ones of the first signal lines arranged or disposed in the first area1A may be less than or equal to a distance between adjacent ones of the first signal lines arranged or disposed in the second area2A. As an example, a distance between the gate lines GL1through GL16extending in the first direction (x-direction) in the first area1A may be less than or equal to a distance between the gate lines GL2, GL4, GL6, GL8, GL10, GL12, and GL14extending in the first direction (x-direction) in the second area2A. In an embodiment, a fifth distance d5between a fifteenth gate line GL15and a sixteenth gate line GL16arranged or disposed in the first area1A may be less than the first distance d1between the eighth gate line GL8and the tenth gate line GL10arranged or disposed substantially in the center of the second area2A and the second distance d2between the tenth gate line GL10and the twelfth gate line GL12.

A distance between the gate lines arranged or disposed in the second area2A of the display device1may gradually decrease toward the outer portions of the second area2A from the center of the second area2A, and a minimum distance between the gate lines arranged or disposed in the second area2A may be equal to a distance between the gate lines arranged or disposed in the first area1A. Thus, the distance between the gate lines arranged or disposed in the second area2A may gradually decrease to converge on the distance between the gate lines arranged or disposed in the first area1A toward the outer portions of the second area2A from the center of the second area2A.

A distance between adjacent ones of second signal lines arranged or disposed in the first area1A may be less than or equal to a distance between adjacent ones of second signal lines arranged or disposed in the second are2A. As an example, the distance between the data lines DL1through DL15extending in the second direction (y-direction) in the first area1A may be less than or equal to the distance between the data lines DL2, DL4, DL6, DL8, DL10, DL12, and DL14extending in the second direction (y-direction) in the second area2A. In an embodiment, a sixth distance d6between the twelfth data line DL12and the thirteenth data line DL13arranged or disposed in the first area1A may be less than the third distance d3between the eighth data line DL8and the tenth data line DL10arranged or disposed substantially in the center of the second area2A and less than the fourth distance d4between the tenth data line DL10and the twelfth data line DL12.

A distance between the data lines arranged or disposed in the second area2A of the display device1may gradually decrease toward the outer portions of the second area2A from the center of the second area2A, and a minimum distance between the data lines arranged or disposed in the second area2A may be equal to the distance between the data lines arranged or disposed in the first area1A. Thus, the distance between the data lines arranged or disposed in the second area2A may gradually decrease to converge on the distance between the data lines arranged or disposed in the first area1A toward the outer portions of the second area2A from the center of the second area2A.

In an embodiment, a distance between the gate lines and the distance between the data lines arranged or disposed in the first area1A may be in a range of about 50 μm to about 70 μm, and a distance between the gate lines and the data lines each adjacent to the gate lines and the data lines arranged or disposed substantially in the center of the second area2A may be in a range of about 500 μm to about 700 μm. The distance between the gate lines and the data lines arranged or disposed in the second area2A may gradually decrease toward the outer portions of the second area2A from the center of the second area2A and thus, a distance between the gate lines and the distance each adjacent to the gate lines and the data lines arranged or disposed in the outer portions of the second area2A may be in a range of about 50 μm to about 70 μm.

The main pixel groups Pgm arranged or disposed in the first area1A and the auxiliary pixel groups Pga arranged or disposed in the second area2A may be electrically connected to the first signal lines extending in the first direction (x-direction). The main pixel groups Pgm arranged or disposed in the first area1A and the auxiliary pixel groups Pga arranged or disposed in the second area2A may be electrically connected to the second signal lines extending in the second direction (y-direction).

Because the second area2A has the transmission area TA, the number of the auxiliary pixel groups Pga that may be arranged or disposed per unit area in the second area2A may be less than the number of the main pixel groups Pgm arranged or disposed per unit area in the first area1A.

Because the distance between the gate lines GL2, GL4, GL6, GL8, GL10, GL12, and GL14extending in the first direction (x-direction) in the second area2A may gradually decrease toward the outer portions of the second area2A from the center of the second area2A and the distance between the data lines DL2, DL4, DL6, DL8, DL10, DL12, and DL14extending in the second direction (y-direction) in the second area2A may gradually decrease toward the outer portions of the second area2A from the center of the second area2A, the distance between adjacent ones of the auxiliary pixel groups Pga arranged or disposed in the first direction (x-direction) and the second direction (y-direction) in the second area2A may gradually decrease toward the outer portions of the second area2A from the center of the second area2A. In an embodiment, when an auxiliary pixel group Pga arranged or disposed in the center of the second area2A may be referred to as a first auxiliary pixel group Pga1, an auxiliary pixel group Pga adjacent to the first auxiliary pixel group Pga1in the first direction (x-direction) may be referred to as a second auxiliary pixel group Pga2and an auxiliary pixel group Pga adjacent to the second auxiliary group Pga2in the first direction (x-direction) may be referred to as a third auxiliary pixel group Pga3, a seventh distance d7between the first auxiliary pixel group Pga1and the second auxiliary pixel group Pga2may be greater than an eighth distance d8between the second auxiliary pixel group Pga2and the third auxiliary pixel group Pga3. When an auxiliary pixel group Pga adjacent to the first auxiliary pixel group Pga1arranged or disposed substantially in the center of the second area2A may be referred to as a fourth auxiliary pixel group Pga4, an auxiliary pixel group Pga adjacent to the fourth auxiliary pixel group Pga4in the second direction (y-direction) may be referred to as a fifth auxiliary pixel group Pga5, a ninth distance d9between the first auxiliary pixel group Pga1and the fourth auxiliary pixel group Pga4may be greater than a tenth distance d10between the fourth auxiliary pixel group Pga4and the fifth auxiliary pixel group Pga5.

A distance between adjacent ones of the main pixel groups Pgm arranged or disposed in the first direction (x-direction) may be less than or equal to a distance between adjacent ones of the auxiliary pixel groups Pga arranged or disposed in the first direction (x-direction). As an example, when a main pixel group Pgm electrically connected to the fifteenth gate line GL15and the second data line DL2may be referred to as a first main pixel group Pgm1and a main pixel group Pgm adjacent to the first main pixel group Pgm1in the first direction (x-direction) may be referred to as a second main pixel group Pgm2, an eleventh distance d11between the first main pixel group Pgm1and the second main pixel group Pgm2may be less than or equal to the seventh distance d7between the first auxiliary pixel group Pga1and the second auxiliary pixel group Pga2and the eighth distance d8between the second auxiliary pixel group Pga2and the third auxiliary pixel group Pga3.

The distance between adjacent ones of the main pixel groups Pgm arranged or disposed in the second direction (y-direction) may be less than or equal to the distance between adjacent ones of the auxiliary pixel groups Pga arranged or disposed in the second direction (y-direction). As an example, when a main pixel group Pgm adjacent to the first main pixel group Pgm1electrically connected to the fifteenth gate line GL15and the second data line DL2in the second direction (y-direction) may be referred to as a third main pixel group Pgm3, a twelfth distance d12between the first main pixel group Pgm1and the third main pixel group Pgm3may be less than or equal to the ninth distance d9between the first auxiliary pixel group Pga1and the fourth auxiliary pixel group Pga4and the tenth distance d10between the fourth auxiliary pixel group Pga4and the fifth auxiliary pixel group Pga5.

FIGS. 9A and 9Bare plan views schematically illustrating a display device according to an embodiment. By way of an example,FIG. 9Ais a view illustrating that at least one of the first signal lines extending in the first direction (x-direction) may be disconnected by the second area2A therebetween and may be electrically connected by connection lines bypassing or disposed along edges of the second area2A, andFIG. 9Bis a view illustrating that at least one of the second signal lines extending in the second direction (y-direction) may be disconnected by the second area2A therebetween and may be electrically connected by connection lines bypassing or disposed along edges of the second area2A. InFIG. 9A, for convenience of illustration and explanation, three connection lines bypass or may be disposed along lower edges of the second area2A. However, the number of connection lines bypassing or being disposed along the lower edges of the second area2A may be substantially three or more, and the connection lines may bypass or be may disposed along upper edges of the second area2A. Also, inFIG. 9B, for convenience of illustration and explanation, three connection lines bypass or may be disposed along right edges of the second area2A. However, the number of connection lines bypassing or being disposed along the right edges of the second area2A may be substantially three or more, and the connection lines may bypass or may be disposed along left edges of the second area2A within the spirit and the scope of the disclosure.

In order to enhance transmittance of the second area2A, a smaller number of signal lines than in the first area1A may be arranged or disposed in the second area2A. For example, in order to enhance transmittance of the second area2A, the number of signal lines that may be arranged or disposed per unit area in the second area2A may be less than the number of signal lines arranged or disposed per unit area in the first area1A.

To this end, at least one of the first signal lines may include first signal lines extending in the first direction (x-direction) and disconnected by the second area2A therebetween, and the disconnected first signal lines may be electrically connected to each other by the connection lines bypassing or being disposed along the edges of the second area2A. As an example, referring toFIG. 9A, the gate lines GL9, GL11, and GL13may extend in the first direction (x-direction), may be disconnected by the second area2A therebetween and may be electrically connected by connection lines GL9-C, GL11-C, and GL13-C bypassing or being disposed along the edges of the second area2A. Each of the gate lines GL9, GL11, and GL13and the connection lines GL9-C, GL11-C, and GL13-C may be arranged or disposed on different layers and may be electrically connected to each other via a contact hole CNT or may also be arranged or disposed on the same layer.

At least one of the second signal lines may include second signal lines extending in the second direction (y-direction) and disconnected by the second area2A therebetween, and the disconnected second signal lines may be electrically connected to each other by the connection lines bypassing or being disposed along the edges of the second area2A. As an example, referring toFIG. 9B, the data lines DL9, DL11, and DL13may extend in the second direction (y-direction), may be disconnected by the second area2A therebetween and may be electrically connected by the connection lines DL9-C, DL11-C, and DL13-C bypassing or being disposed along the edges of the second area2A. Each of the data lines DL9, DL11, and DL13and the connection lines DL9-C, DL11-C, and DL13-C may be arranged or disposed on different layers and electrically connected to each other via a contact hole CNT or may also be arranged or disposed on the same layer.

FIGS. 10A and 10Bare plan views schematically illustrating a display device according to an embodiment. For example,FIG. 10Ais av plan view enlarging region A ofFIG. 8, andFIG. 10Bis a plan view enlarging region B ofFIG. 8.

Referring toFIG. 10A, each of the auxiliary pixel groups Pga may include a first auxiliary pixel Pa1, a second auxiliary pixel Pa2, and a third auxiliary pixel Pa3that may emit lights of different wavelengths, and each of the second signal lines may include a first conductive line CL1, a second conductive line CL2, and a third conductive line CL3. As an example, the auxiliary pixel group Pga may include a first auxiliary pixel Pa1that may emit light of a red wavelength, a second auxiliary pixel Pa2that may emit light of a green wavelength, and a third auxiliary pixel Pa3that may emit light of a blue wavelength. The first conductive line CL1may be electrically connected to the first auxiliary pixel Pa1, the second conductive line CL2may be electrically connected to the second auxiliary pixel Pa2, and the third conductive line CL3may be electrically connected to the third auxiliary pixel Pa3.

InFIG. 10A, three auxiliary pixels Pa1, Pa2, and Pa3may be included in one auxiliary pixel group Pga and arranged or disposed in one column. However, embodiments are not limited thereto. Four auxiliary pixels may be included in one auxiliary pixel group Pga and arranged or disposed in two columns, or eight auxiliary pixels may be included in one auxiliary pixel group Pga and arranged or disposed in four columns.

Referring toFIG. 10B, each of the main pixel groups Pgm may include a first main pixel Pm1, a second main pixel Pm2, and a third main pixel Pm3that may emit lights of different wavelengths, and each of the second signal lines may include a first conductive line CL1, a second conductive line CL2, and a third conductive line CL3. As an example, the main pixel group Pgm may include a first main pixel Pm1that may emit light of a red wavelength, a second main pixel Pm2that may emit light of a green wavelength, and a third main pixel Pm3that may emit light of a blue wavelength, and the first conductive line CL1may be electrically connected to the first main pixel Pm1, and the second conductive line CL2may be electrically connected to the second main pixel Pm2, and the third conductive line CL3may be electrically connected to the third main pixel Pm3.

InFIG. 10B, three main pixels Pm1, Pm2, and Pm3may be included in one main pixel group Pgm and arranged or disposed in one column. However, embodiments are not limited thereto. Four main pixels may be included in one main pixel group Pgm and arranged or disposed in two columns, or eight main pixels may be included in one main pixel group Pgm and arranged or disposed in four columns.

According to one or more embodiments, in order to solve a problem that, in a display device according to the related art, gate lines and data lines regularly arranged or disposed in an area in which a component may be located or disposed, act as a diffraction grating such that light emitted from the component passes through the diffraction grating and is diffracted and thus a blur image may be output, a distance between the gate lines arranged or disposed in the area in which the component may be located or disposed, and a distance between the data lines arranged or disposed in the area in which the component may be located or disposed, may be gradually decreased as getting closer to outer portions from substantially the center of the area so that the gate lines and the data lines may be prevented from acting as the diffraction grating and thus a display device having enhanced product reliability may be provided.

According to one or more embodiments described above, a display device having an enlarged display area in which an image or images may be displayed even in an area in which a component may be located or disposed, may be implemented. However, the scope of the disclosure is not limited by these effects.