Programmable pin designation for semiconductor devices

The invention allows the programmer to designate one or more pins on a semiconductor device as either address pins, which are in addition to a predetermined set of address lines or as alternate I/O pins. The object of the invention is to provide the programmer with the capability of defining with preciseness the particular size of the address bus needed for a specific application. The invention is comprised of a programming port, optional programming logic, configuration logic, selection logic and a set of pins that may be configured as per the programmer's requirements. The invention is to exist on a single, monolithic semiconductor device.

BACKGROUND OF THE INVENTION 
Field of the Invention 
This invention relates generally to semiconductor device pin designation. 
Specifically, the present invention relates to the ability of the user to 
programmably designate one or more semiconductor device pins to perform an 
expanded and flexible set of address functions, as well as other I/O 
functions. 
Description of the Prior Art 
The current state of the art describes semiconductor devices such as 
microprocessors and microcontrollers that have bi-directional I/O ports to 
a common pin that are capable of performing one function when in the input 
mode and a second function when in the output mode. 
The current state of the art also describes semiconductor devices such as 
microprocessors and microcontrollers that are capable of using a 
particular pin as either an address pin or a data pin, depending on state 
of the device with respect to the memory access cycle. For example, a 
microprocessor capable of driving a 16 bit wide data bus is likely to have 
16 pins that function as data I/O. The microprocessor has an internal 
capability that allows the same 16 pins to drive an address bus. If 
additional addressing capability is needed, then additional pins must be 
dedicated to fulfill this need. Under the prior art, the internal 
architecture of address pin assignments is defined by the semiconductor 
manufacturer and cannot be modified by the user. 
The prior art, as found in U.S. Pat. No. 5,686,844, "INTEGRATED CIRCUIT 
PINS CONFIGURABLE AS A CLOCK INPUT PIN AND AS A DIGITAL I/O PIN OR AS A 
DEVICE RESET PIN AND AS A DIGITAL I/O PIN AND METHOD THEREFOR," describes 
semiconductor devices with the capability of configuring integrated 
circuit (IC) pins as clock/reset signals or other digital I/O. 
Other schemes have described a multifunctional pin approach for test 
circuits, which purport to test multiple segments of memory 
simultaneously. See U.S. Pat. No. 4,495,603, "TEST SYSTEM FOR SEGMENTED 
MEMORY." However, this prior art describes the introduction of a "logic 
box" which contains little more than tri-state buffers that generate read 
and write test clocks for segmented memory devices. Furthermore, there is 
no suggestion that these test circuits or "logic boxes" are integral to 
the processing unit and thus are not programmable for customizing the I/O 
function of the processing unit. 
U.S. Pat. No. 5,473,758, "SYSTEM HAVING INPUT OUTPUT PINS SHIFTING BETWEEN 
PROGRAMMING MODE AND NORMAL MODE TO PROGRAM MEMORY WITHOUT DEDICATING 
INPUT OUTPUT PINS FOR PROGRAMMING MODE," claims a common set of processing 
unit I/O pins to function in either a programming mode (e.g. programming 
non-volatile memory) or a normal mode (e.g. executing program memory). 
Thus, a problem is created that manifests itself as either insufficient or 
excessive addressing capability, depending on the programmer's 
application. Furthermore, the prior art does not anticipate a flexible 
addressing capability that may be programmed for the specific application 
of the semiconductor device. 
Therefore, a need existed to provide a semiconductor device where the 
number of address pins required to meet the design specification may be 
programmably designated. 
SUMMARY OF THE INVENTION 
It is an object of the present invention to provide a system that will 
permit the user to designate the function of one or more semiconductor 
device pins. 
It is another object of the present invention to provide a system that will 
permit the user to program the designation of semiconductor device pins as 
either address pins or standard I/O pins. 
It is another object of the present invention to provide a system that will 
allow the user to permanently program a semiconductor device for the 
purpose of designating the function of the semiconductor device pins. 
It is another object of the present invention to provide a system that will 
allow the user to alterably program a semiconductor device for the purpose 
of designating the function of the semiconductor device pins. 
It is another object of the present invention to provide a system that is 
capable of encoded designation of semiconductor device pins. 
It is still another object of the present invention to provide a system 
that is capable of non-encoded designation of semiconductor device pins. 
In accordance with one embodiment of the present invention, a system for 
programmably designating semiconductor pins comprises a programming port, 
configuration logic, selection logic and at least one pin, which may be 
programmably designated to perform one of a plurality of I/O functions. 
This embodiment may further comprise a plurality of semiconductor pins, 
which are predesignated and unalterable, to perform memory address 
functions. Furthermore, in this embodiment, the above elements and 
features are co-located on a single, monolithic semiconductor device. 
In accordance with another embodiment of the present invention, a system 
for programmably designating semiconductor pins comprises a programming 
port, programming logic, configuration logic, selection logic and at least 
one pin which may be programmably designated to perform one of a plurality 
of I/O functions. This embodiment may further comprise a plurality of 
semiconductor pins, which are predesignated and unalterable, to perform 
memory address functions. This embodiment may further comprise of decoding 
pin designation assignments from an encoded format. Furthermore, in this 
embodiment, the above elements and features are co-located on a single, 
monolithic semiconductor device. 
The foregoing and other objects, features, and advantages of the invention 
will be apparent from the following, more particular, description of the 
preferred embodiments of the invention, as illustrated in the accompanying 
drawings.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT 
Referring to FIG. 1, a block diagram of the present invention 10 is shown. 
The programmable pin designation for semiconductor devices 10 [hereinafter 
"system"] is comprised of a programming port 100, optional programming 
logic 200 (shown in dashed lines to indicate an optional, not a required, 
element), configuration logic 300, selection logic 400 and at least one 
pin 500, which may be programmably designated to perform one of a 
plurality of I/O functions. The system is further comprised of a plurality 
of semiconductor pins which are predesignated and unalterable, to perform 
a memory address function. These pins are shown in FIG. 4 as AD.sub.m 
:AD.sub.0, which is a diagram demonstrating several applications of the 
invention. In the preferred embodiment, the elements described above are 
co-located on a single, monolithic semiconductor device. 
The importance of the invention is to provide a semiconductor device such 
as a microcontroller, microprocessor or other devices capable of 
performing memory access with a flexible, programmable method of selecting 
the precise address range required for the application. The objective of 
the invention is to optimize the number of semiconductor pins needed for 
memory address functions and quasi-address functions such as chip select. 
The programming port 100 may be either a serial or parallel I/O port of 
various formats, standards and protocols which are well known to those 
skilled in the art. The programming port has several functions. The port 
100 accepts semiconductor pin configuration data from a programming device 
that is beyond the scope of the invention, but is well known to those 
skilled in the art of computer science. The port 100 may also output the 
current configuration of the semiconductor pins to external devices. Also, 
the port 100 may be used for test purposes. 
In one embodiment, the configuration data is transmitted via the 
programming port directly to the configuration logic 300 where it is 
stored. In an alternative embodiment, the configuration data is read by 
the programming logic 200, which may be a processing unit. The 
configuration data is interpreted by the programming logic 200. The 
interpretted form of the configuration data is stored in the configuration 
logic 300. 
The configuration logic 300 may include one of a number of implementations. 
In one embodiment, the configuration logic 300 may be a simple register or 
a location within a programmable volatile or non-volatile memory array. 
Thus, in this embodiment, the configuration data stored in the 
configuration logic may be modified at the discretion of the programmer. 
Alternatively, the configuration logic may encompass one time only 
programmable logic such as a programmable read only memory (PROM) or other 
types of fusible devices known to those skilled in the art. 
Referring to FIGS. 1, 2, and 3, wherein like numerals represent like 
elements, the selection logic 400 is shown. The selection logic provides 
the decision mechanism for designating semiconductor pin functions. The 
selection logic 400 is comprised of a series of multiplexers 410 in the 
preferred embodiment. In another embodiment, the selection logic includes 
both the series of multiplexers 410 and one or more decoders 420. 
FIG. 1 shows that the selection logic 400 provides the bridge between the 
data stored in the configuration logic 300 and the semiconductor pins 500. 
FIG. 2 shows a non-encoded form of the selection logic 400 where there is 
one to one mapping between each bit of the configuration logic 300 and the 
select input for each multiplexer 410. FIG. 3 shows an encoded form of the 
selection logic 400 where the configuration data is stored in an encoded 
format. The encoded data is then decoded by decode logic 420 and then 
coupled to the select inputs of the multiplexers 410. 
The inputs of the multiplexers 410 are either expanded address lines or 
other I/O functions performed by a semiconductor device. The outputs of 
the multiplexers 410 are connected to the semiconductor pins 500, either 
directly or through a buffer. 
Referring to FIG. 4, a typical application of the present invention 10 is 
shown. The present invention 10 is embodied in block 20, which represents 
a processing unit such as a microprocessor or microcontroller. The 
application also illustrates memory device 30 and peripheral device 40. 
The address latch 50 is also illustrated. 
AD.sub.m :AD.sub.0 in block 20 represents a predesignated set of pins with 
an address function. In this example, these pins may be coupled to the 
data bus in addition to driving the address bus. However, in other 
embodiments the predesignated set of address pins may not be multiplexed 
with the data bus function, thus obviating the requirement for the address 
latch 50. The predesignated nature of the address function of the 
semiconductor pins corresponding to AD.sub.m :AD.sub.0 may not be altered 
or modified by the programmer. 
The memory device 30 and peripheral device 40 have addressable memory 
locations which exceed that provided for by the range defined by AD.sub.m 
:AD.sub.0. Therefore, addition memory addressing capability is required. 
The programmer defines the expanded addressing as A.sub.n :A.sub.m+1, 
where n.gtoreq.m+1. This data is stored in the configuration logic 300 and 
the selection logic 400 determines the semiconductor pin 500 assignments 
(FIGS. 1-3). 
Also in this application, because there may be redundancy in addressable 
memory locations as between memory device 30 and peripheral device 40, 
chip select logic is shown. Chip select logic is represented in block 20 
as ADDR.sub.x and ADDR.sub.y. By designating these pins as chip selects in 
the same manner as described above for expanded address pins, the 
appropriate memory/peripheral device is accessed. Thus, the present 
invention allows for flexible designation of IC pins for addressing, which 
precisely matches the addressing requirements of the design specification. 
Those pins not used for addressing are available for other I/O functions. 
Although the invention has been particularly shown and described with 
reference to a preferred embodiment thereof, it will be understood by 
those skilled in the art that changes in form and detail may be made 
therein without departing from the spirit and scope of the invention.