Buck switching regulator with improved mode transition and control method thereof

The present invention discloses a buck switching regulator with improved mode transition, and a method for controlling a buck switching regulator. The method comprises: providing a switching regulator including: an output power stage for converting an input voltage to an output voltage, the output power stage being controlled by a first PWM signal during a fixed-frequency PWM mode (FPWM mode), and being controlled by a first voltage signal during a pulse skipping mode (PSK mode), wherein the first PWM signal is generated according to the first voltage signal; and in a transition from the PSK mode to the FPWM mode, proving a second voltage signal as a starting point of the first voltage signal, the second voltage signal being substantially close to a target of the first voltage signal in the FPWM mode.

FIELD OF INVENTION

The present invention relates to a buck switching regulator and control method thereof, and particularly to a buck switching regulator with improved mode transition and control method thereof.

DESCRIPTION OF RELATED ART

In a voltage-controlled buck switching regulator, a smooth transition from a pulse skipping mode (PSK) to a fixed-frequency PWM (FPWM) is usually difficult to achieve in the industry. The main reason is that the two modes have totally different definitions in pulse width.

More specifically,FIGS. 1A and 1Bschematically show the circuit structure and the operation of a conventional buck switching regulator under the FPWM mode, whereinFIG. 1Aillustrates the circuit structure andFIG. 1Billustrates a relationship among a Vcomp signal, a Vramp signal, and a PWM signal. A feedback circuit11extracts a feedback signal Vfb from an output Vo and inputs it to an operational amplifier14. The feedback signal Vfb is compared with a reference voltage Vref to generate a Vcomp signal, which is inputted to a comparator16to be compared with the Vramp signal. A compensation circuit12is typically provided in the circuit to keep the Vcomp signal stable. The PWM signal generated from the comparator16controls an output power stage18, so that an input voltage Vin is converted to the output voltage Vo. Typically, the feedback circuit11is a voltage division circuit and the compensation circuit12is a parallel circuit including a resistor and a capacitor connected in parallel.

As shown inFIG. 1B, the higher the level of the Vcomp signal is, the longer the on time period a of the PWM signal will be, and the lager the duty cycle D=a/b, wherein b is a complete cycle period of the PWM signal. (The waveform of the PWM signal is reversed for better illustration. Actually in the circuit shown inFIG. 1A, the on time of the output signal from the comparator16is its low level.) Since the duty cycle relates to a ratio of the output voltage Vo to the input voltage Vin (Vo/Vin), the Vcomp signal should be properly determined so that the output signal Vo falls within a required specification.

On the other hand,FIGS. 2A and 2Bschematically show the circuit structure and the operation of the conventional buck switching regulator1under the PSK mode, whereinFIG. 2Ashows the circuit structure andFIG. 2Bshows the relationship among the output Vo, Vref signal, and Vcomp signal. Under this mode, the device14operates more like a comparator than an operational amplifier. When the Vfb signal is low, the Vcomp signal becomes high; hence, the output power stage18drives current to the output and causes the output voltage Vo to rise up. When the output voltage Vo rises up, the Vfb signal is higher than Vref signal; hence, the Vcomp signal falls to a low level again. The waveform of the Vcomp signal generated thereby is shown in the bottom ofFIG. 2B.

Under a light load condition, the PSK mode operates more efficiently than the FPWM mode, because the period b of the PSK mode is much longer than that in the FPWM mode. In other words, the switching loss in the PSK mode is much lower than the FPWM mode.

However, if these two operation modes are both provided in the same power chip, a switching issue occurs. In the FPWM mode, the Vcomp signal is a constant in most of the time, but in the PSK mode, the Vcomp signal is a digital signal oscillating between two levels. During the transition period from the PSK mode to the FPWM mode, the Vcomp signal gradually transits toward a correct target level, and this requires time which depends on the driving ability of the comparator/operational amplifier14, the compensation ability of the compensation circuit12, and the parasitic capacitance of the circuit. As shown inFIG. 3, however, such transition period typically lasts several switching cycles for the Vcomp signal to finally achieve the correct target level. Before the Vcomp signal achieves the correct target level, the PWM signal received by the output power stage18may lose several pulses or provide insufficient pulse widths, causing an undershoot of the output voltage Vo. The undershoot of the output voltage Vo may cause serious problems in a next-stage circuit.

Accordingly, the present invention provides a buck switching regulator with improved mode transition and control method thereof to overcome the shortcoming of the foregoing prior art.

SUMMARY OF THE INVENTION

A first objective of the present invention is to provide a buck switching convertor with improved mode transition.

A second objective of the present invention is to provide a method for controlling a buck switching regulator.

In order to achieve the foregoing objectives, in one perspective thereof, the present invention provides a buck switching regulator with improved mode transition comprising: (1) a first circuit including: an output power stage for converting an input voltage to an output voltage; a comparison and amplification circuit comparing a feedback signal relating to the output voltage with a reference signal to generate a first voltage signal; a first comparator comparing the first voltage signal with a ramp signal to generate a first PWM signal; wherein the first PWM signal controls the output power stage during a FPWM mode, and the first voltage signal controls the output power stage during a PSK mode; and (2) a second circuit generating a second voltage signal during the PSK mode, the second voltage signal being substantially close to the first voltage signal during the FPWM mode, and providing the second voltage signal as a starting point of the first voltage signal during the PWM mode.

In a preferable embodiment, the second circuit of the foregoing buck switching regulator includes: an average circuit which receives a second PWM signal, and converts the second PWM signal to an average voltage output; an operational amplifier which compares a feedback signal relating to the average voltage with the reference signal to generate the second voltage signal; and a second comparator which compares the second voltage signal with the ramp signal to generate the second PWM signal. The average circuit can be a simple RC circuit.

Additionally, in another perspective, the present invention also provides a method for controlling a buck switching regulator, comprising the steps of: providing a switching regulator including an output power stage for converting an input voltage to an output voltage, the output power stage being controlled by a first PWM signal during a FPWM mode and being controlled by a first voltage signal during a PSK mode, wherein the first PWM signal is generated according to the first voltage signal; and in a transition from the PSK mode to the FPWM mode, providing a second voltage signal as a starting point for the first voltage signal, the second voltage signal being substantially close to a target of the first voltage signal in the FPWM mode.

Preferably, the method for controlling a buck switching regulator further comprising: in the PSK mode, keeping the second voltage signal substantially close to the first voltage signal in the FPWM mode.

The objectives, technical details, features, and effects of the present invention will be better understood with regard to the detailed description of the embodiments below, with reference to the drawings, wherein resembled devices are indicated in the same unit.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

Please refer toFIG. 4, which schematically shows an embodiment of the present invention. Other than a primary loop10, the buck switching regulator100of the present invention further comprises a secondary loop20. The primary loop10comprises a feedback circuit11, a compensation circuit12, a comparator/operational amplifier14, a comparator16, and an output power stage18. The primary loop10operates in a manner similar to that in the prior art; hence, detailed description thereof is omitted. The secondary loop20comprises a feedback circuit21, a compensation circuit22, an operational amplifier24, a comparator26, and an average circuit28. The circuit further comprises switches S1-S4.

An objective of the secondary loop20is to keep the voltage at the node A in the PSK mode equal to or substantially close to the target level of the Vcomp signal in the FPWM mode. As such, since the Vcomp signal is substantially close to the target level during a transition from the PSK mode to the FPWM mode, the PWM signal neither loses a pulse nor provides an insufficient pulse width, and therefore no undershoot occurs in the output voltage Vo. However, the voltage at the node A can not be arbitrarily decided; its value is dependent on the circuit devices in the primary loop10. Therefore, the present invention provides the secondary loop20having a circuit structure which is highly similar to the primary loop10, so as to generate a Vcomp2signal in an environment similar to the primary loop10such that the voltage level of the Vcomp2signal is equal to or substantially close to the target level of the Vcomp signal in the FPWM mode. (In other words, the circuit maintains the Vcomp2signal in the PSK mode to be substantially close to the Vcomp signal in the FPWM mode.)

More specifically, in the FPWM mode, the switches S1and S2are on and the switches S3and S4are off, as shown inFIG. 5. The primary loop10generates the PWM signal according to cross-over points between the Vcomp signal and the Vramp signal, and the PWM signal controls the output power stage18to convert the input voltage Vin to the output voltage Vo. Simultaneously, the secondary loop20generates the Vcomp2signal according to its loop operation. Since the circuit devices21,22,24, and26are similar to the circuit devices11,12,14, and16(the circuit device28can also be designed the same as the circuit device18, yet in consideration of cost, it is preferably achieved by a simple average circuit which will be illustrated later), the Vcomp2signal is substantially close to the Vcomp signal in the FPWM mode. In other words, the Vcomp2signal is substantially close to the target level of the Vcomp signal.

Next referring toFIG. 6, in the PSK mode, switches S3and S4are on, and switches S1and S2are off, during which the primary loop10controls the output power stage18according to the Vcomp signal. Yet, since the switch S4is on, the voltage level at the node A maintains at the level of the Vcomp2signal. When the circuit transits from the PSK mode to the FPWM mode, the switch S1is turned on again and electrically connects the node A to an input of the comparator16. At this time point, however, the Vcomp signal starts from the voltage level of the Vcomp2signal instead of the low level (referring toFIG. 3). Moreover, the Vcomp2signal is very close to the target level of the Vcomp signal in the FPWM mode. As a result, the Vcomp signal can quickly reach the target level to avoid any undershoot of the output voltage Vo.

As mentioned earlier, in order to make the Vcopm2signal substantially close to the Vcomp signal in the FPWM mode, the overall structure of the secondary loop20should preferably be highly similar to the primary loop10. Hence, the circuit devices21,22,24and26are preferably highly similar to the circuit devices11,12,14,16, and the circuit device28can be designed to be the same as the circuit device18as well. However, the output power stage18is a more complicated and expensive circuit; hence, the circuit device28does not have to be, and is preferably not to be the same as the circuit device18. Referring toFIG. 7, the circuit device28can be a simple average circuit, such as the RC circuit as shown. This average circuit obtains an average voltage value of the PWM signal from the comparator26. Similarly, a feedback voltage Vfb2can be generated by the feedback circuit21, and the feedback voltage Vfb2is substantially close to the feedback voltage Vfb.

The present invention has been described in considerable detail with reference to certain preferred embodiments thereof. It should be understood that the description is for illustrative purpose, not for limiting the scope of the present invention. Those skilled in this art can readily conceive variations and modifications within the spirit of the present invention. For example, without departing from the spirit of the present invention, the feedback circuit and the compensation circuit can be replaced by various forms or even omitted; other circuit devices which do not affect the primary function of the present invention can be interposed between two circuit devices in the embodiments as shown. In view of the foregoing, the spirit of the present invention should cover all such and other modifications and variations, which should be interpreted to fall within the scope of the following claims and their equivalents.