Handshake free sharing in a computer architecture

A system arrangement including a memory unit having a memory interface in accordance with a handshake-free protocol between the memory and an accessing master, a bus connected to the memory unit and first and second masters. The first master operative to access the memory unit through the bus and the memory interface and operative to perform interrupts following reception of an interrupt request through an interrupt interface. The second master operative to access the memory unit through the bus and memory interface. The second master being configured to transfer an interrupt request to the first processor before accessing the memory unit.

FIELD OF THE INVENTION

The present invention relates generally to computer architectures and specifically, but not exclusively, to memory access architectures.

BACKGROUND

Processors are used for a very wide range of tasks, including, inter alia, mathematical calculations, database management, communications and the controlling of devices. In many cases, processors require a separate memory unit, for performing functions such as the storage of processing results or intermediate values, and/or from which to retrieve operation software and/or input data. A processor which controls the access to the memory is referred to as a “master”. The term master is also used to represent other units, not necessarily processors, which control access to a memory.

A variety of communication protocols have been defined for internal communication purposes, including data transfer between the processor and the memory unit. Some protocols were defined particularly for use in multi-processor configurations, wherein a plurality of processors can access a shared memory unit, such as through a bus, for example. Protocols for multiple processor applications sharing a common memory or other resource have rules governing which processor is allowed to access the memory unit and when. Such protocols generally define hand-shake methods, which are used to notify the processor when there is a problem in its communication with the memory unit. The main disadvantage of handshake protocols is their complexity, as in some applications, a simpler protocol is sufficient.

The Serial Peripheral Interface, henceforth SPI, is a simple synchronous data link protocol. SPI is designed for accessing one or more memory units by only a single master. Hence, SPI has no low layer provisions, such as hand-shake provisions, for verifying that instructions given were indeed performed. It also lacks error detection and correction provisions. Nevertheless, due to its simplicity, SPI enjoys the advantages of fast operation using a small number of communication lines. Consequently, SPI is a popular protocol for memory units associated with a single processor.

When, however, two processors require external memory units, each processor is required to have its own memory unit, regardless of how much memory space it requires and how often it accesses the memory unit.

One method of avoiding the necessity for separate memory units, is to have a first processor send access requests to a shared memory unit in a Low Pin Count (LPC) format that supports a bus-busy indication. In such a configuration, requests from the first processor are forwarded to the second processor which translates them into the SPI format and transfers them to the memory unit. It will be appreciated that this method requires the first processor supporting the LPC format and the second processor being configured to perform the format translation.

Another method of sharing a memory unit between processors is to perform a hardware handshake between two processors sharing the memory. This requires that the processors support the handshake protocol, and is complex when more than two processors are involved.

U.S. Pat. No. 5,603,055 to Evoy et al., dated Feb. 11, 1997, the disclosure of which is incorporated herein by reference, describes a method of sharing a ROM memory between a keyboard controller (i.e., processor) and a system processor. At initial boot-up, the system processor accesses the shared ROM to retrieve the system BIOS, and afterwards, the shared ROM is used by the keyboard controller. This method is unsuitable for applications wherein intermittent access to the memory is required by both processors.

U.S. Pat. No. 5,892,943 to Rockford, Dunnihoo and Wahler titled “Shared bios ROM warm boot”, the disclosure of which is incorporated herein by reference, describes the sharing of a memory unit between a host processor, which uses the memory unit for uploading the BIOS, and a keyboard controller. A logic circuitry connecting the host processor and the keyboard controller to the memory unit only allows the host processor to access the memory when the keyboard controller is disabled, such as when the computer is first turned on. When the host attempts to access the memory at a different time, the logic circuitry emulates a set of op-codes to the processor, causing it to access a copy of the BIOS located in the main memory of the host. While this may solve the problem of accessing the BIOS, it does not allow intermittent access to the memory unit. Furthermore, this solution requires a memory with a parallel access interface and is not suitable for a serial interface.

Other solutions with similar disadvantages are described in U.S. Pat. No. 5,999,476 to Dutton et al., in U.S. Pat. No. 5,794,054, to Le et al., patented Aug. 11, 1998, and in U.S. Pat. No. 6,154,838 to Le et al., patented Nov. 28, 2000, the disclosures of which are incorporated herein by reference.

SUMMARY OF THE INVENTION

An aspect of some embodiments of the present invention relates to an architecture in which a plurality of processors are connected to a single memory unit. A first processor is generally connected to the memory unit in a steady state. When a second processor is to access the memory unit, the second processor passes an interrupt request to the first processor and takes control of the memory unit on acknowledgement of the interrupt request. When the second processor completes its memory access it releases the first processor from the interrupt. During the interrupt, the first processor need not perform any useful tasks, but may instead simply be kept idle. The advantages from allowing multi-processor access to a single memory unit was determined to outweigh, in accordance with some embodiments of the invention, the disadvantage of having the first processor idle whenever the second processor accesses the memory unit.

Optionally, the memory unit operates using a single master protocol, such as SPI or Microwire. Preferably, the memory unit operates according to a handshake-free protocol. The protocol governing the operation of the memory unit need not support error detection or error correction. In some embodiments of the invention, the access to the memory unit requires fewer than 10 or even fewer than 5 pins. Optionally, the memory unit comprises a serial access memory unit.

In some embodiments of the invention, the first processor, which is generally connected to the memory, is a main processor of the architecture, which is directed at achieving a goal of the architecture, while the second processor is used for supportive tasks. The main processor thus optionally has control of the access to the memory. Optionally, the first processor has substantially more processing power than the second processor, optionally at least five times or even at least ten times the processing power of the second processor. In some embodiments of the invention, the first processor has a substantially higher instruction throughput than the second processor, for example at least five or even at least ten times greater. The first processor optionally has in these embodiments a transistor count substantially greater than the second processor, for example at least ten times or even at least twenty times greater.

In an exemplary embodiment of the invention, the first processor comprises a host processor and the second processor comprises an embedded controller. For example, the embedded controller may control one or more of a battery, keyboard, mouse and power supply unit of a computer.

In some embodiments of the invention, the memory unit stores executable code for the first and/or second processor which they execute to perform their task. For example, for the first processor, the memory unit may store code of the Basic Input/Output Services (BIOS), an Extensible Firmware Interface (EFI) or of system management code. Optionally, the memory unit stores code segments of a plurality of different applications for the first processor. In some embodiments of the invention, the memory unit stores large amounts of code for the first and/or second processors which the processor cannot hold in its internal memory and the processor performs paging with the code stored in the memory unit.

In some specific embodiments of the invention, the second processor is positioned along a bus connecting the first processor to the memory unit. Whilst not itself requiring access to the memory unit, the second processor operates as a pass-through unit which mirrors signals exchanged between the memory unit and the first processor.

There is therefore provided in accordance with an exemplary embodiment of the invention, a processor arrangement, comprising a memory unit having a memory interface in accordance with a handshake-free protocol between the memory and an accessing processor, a bus connected to the memory unit, a first processor operative to access the memory unit through the bus and the memory interface and operative to perform interrupts following reception of an interrupt request through an interrupt interface; and a second processor, or other master, operative to access the memory unit through the bus and memory interface; the second processor being configured to transfer an interrupt request to the first processor before accessing the memory unit.

Optionally, the memory interface comprises an interface in accordance with a protocol that does not support identification of collisions on the bus and/or does not support selection of a single processor to access the memory unit. Alternatively or additionally, the memory interface comprises an interface in accordance with the Serial Peripheral Interface SPI protocol.

Optionally, the first processor comprises a host of a computer. Optionally, the first processor is adapted to perform at least one of accessing the memory unit and receiving interrupt requests, through a host controller. Optionally, the second processor comprises an embedded controller of the computer. Optionally, the second processor comprises a controller of a computer. Optionally, the second processor comprises an embedded controller of a laptop computer. Alternatively or additionally, the second processor comprises a system controller of a computer. Further alternatively or additionally, the second processor comprises a keyboard controller. Optionally, the first processor has at least five times the processing power of the second processor. Optionally, the second processor is located along the bus connecting the first processor to the memory unit. Optionally, the second processor is configured to access the memory unit only after an acknowledgement is received from the first processor in response to the interrupt request. Optionally, the second processor is configured to transfer an interrupt request to the first processor before each access to the memory unit.

Optionally, the second master is configured to access the memory unit a predetermined time after transferring the interrupt request, regardless of whether an acknowledgement is received. Optionally, the first master is configured to refrain from accessing the memory unit through the bus, responsive to the interrupt request. Alternatively, the first master is configured to stop refraining from accessing the memory unit only in response to an indication from the second master. In some embodiments of the invention, the first master is configured to stop refraining from accessing the memory unit without receiving an indication from the second master.

There is further provided in accordance with an exemplary embodiment of the invention, a processor comprising a memory interface operative to control a memory unit via a handshake-free protocol, an interrupt interface for transfer of interrupt requests to processors; and a processing unit operative to perform processing tasks and to read data from a memory unit or to store data to the memory unit through the memory interface, the processing unit being configured to transfer an interrupt request through the interrupt interface and receive an acknowledgement of the interrupt request before accessing a memory through the memory interface.

Optionally, the processing unit is operative to receive the acknowledgement of the interrupt request via the interrupt interface or via a register independent of the interrupt interface. Optionally, the processing unit is operative to read code segments from the memory unit. Optionally, the processor includes an internal memory configured to store less than an entire code of an application to be performed by the processing unit, wherein the internal memory is configured to swap code segments from the memory unit through the memory interface. Optionally, the processing unit is operative to operate in a first state in which it does not transfer an interrupt request before accessing a memory through the memory interface and also to operate in a second state in which the processing unit only accesses the memory after transferring an interrupt receiving an acknowledgement of the interrupt. Optionally, the processing unit is operative to operate in the first state when there is no danger that another processor will access the memory.

There is further provided in accordance with an exemplary embodiment of the invention, a method of accessing a memory unit comprising the steps of: (i) providing one or more first processors connected to a memory unit, (ii) sending an interrupt request from a second processor to the one or more first processors, (iii) receiving an acknowledgement from the one or more first processors responsive to the interrupt request and (iv) accessing the memory unit while the one or more first processors are handling the interrupt request.

Optionally, the method includes releasing the one or more first processors from the interrupt request after completing the memory access. Optionally, accessing the memory unit comprises a read-only access. Alternatively, accessing the memory unit comprises a write access. Optionally, accessing the memory unit comprises accessing through an interface governed by a single master protocol.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

Overview

FIG. 1is a schematic illustration of memory connections of a memory unit130servicing a plurality of processors of a computer100wherein for simplicity, only portions relevant to explaining an exemplary embodiment of the present invention are shown. Memory unit130is designed with an SPI interface134, such that memory accesses to memory unit130are in accordance with the SPI protocol. Memory unit130may include substantially any suitable type of memory, such as a flash memory, a ROM and/or other non-volatile memory. Memory unit130may be of substantially any capacity, for example at least 1 Mbyte, 4 Mbyte or even at least 16 Mbyte. Memory unit130may be a read only memory or a read/write memory.

A host controller110(also known as a Southbridge and/or an I/O controller hub) is connected, via an SPI interface114thereof, to memory unit130through an SPI bus formed of a first segment102and a second segment104. In some embodiments of the invention, host controller110does not have other memory interfaces beyond SPI interface114. Alternatively, host controller110has other memory interfaces not used for accessing memory unit130in the configuration of the embodiment illustrated inFIG. 1. Optionally, host controller110accesses memory unit130to retrieve therefrom software code of one or more applications, such as the BIOS, LAN and/or system management of computer100, for example. The retrieved information optionally includes portions of the software code, which are replaced as necessary, using code swapping (paging) methods. Alternatively or additionally, host controller110accesses memory unit130in order to store updates of the software code stored in memory unit130, for example BIOS updates received by computer100over the Internet. Further alternatively or additionally, host controller110accesses memory unit130in order to store changes in the system configuration of computer100.

An embedded controller (EC)120is optionally located along the SPI bus, between first segment102and second segment104. When not accessing memory unit130, embedded controller120optionally operates in a pass-through mode, in which controller120transparently transfers signals between bus segments102and104at suitable rates.

In some embodiments of the invention, embedded controller120controls one or more peripherals of computer100, such as a keyboard, a mouse, a screen, a power supply and/or a battery (not shown). Computer100may be any of a wide variety of computers, such as a laptop computer, a desktop computer, a server computer, a point of sale computer or a thin client computer, for example. Embedded controller120optionally executes a software application it retrieves from memory unit130. Embedded controller120optionally has a small internal memory, e.g., a random access memory (RAM)122, into which it loads portions of the software application that it currently needs to execute. Occasionally, embedded controller120needs to swap one or more portions of the software application code by retrieving a different code portion from memory unit130. Alternatively or additionally, embedded controller120executes software code directly stored within memory unit130and/or accesses memory unit130for other reasons, for example to store configuration parameters of the system.

Embedded controller120optionally includes a processing unit (PU)121which executes code in RAM122retrieved from memory unit130. The code is retrieved through a memory interface123, which connects to bus segment104, through a multiplexer125. Optionally, PU121is also connected directly to interface123, so that PU121can receive data directly from memory130, without the data passing through RAM122.

Operation Flowchart

FIG. 2is a flowchart of acts performed by embedded controller120in accessing memory unit130, in accordance with an exemplary embodiment of the present invention. Thus still referring toFIG. 1, but additionally referring toFIG. 2, before taking any action, embedded unit120operates (200) as a pass-through unit which simply transfers signals between bus segments102and104substantially without delay, e.g., with a delay on the order of nano-seconds. When embedded controller120needs to read or write information to memory unit130, it optionally checks (230) whether it is in a permission-free state in which it may access memory unit130without any preparations. If not (230) in the permission-free state, embedded controller120sends (202) an interrupt request (IRQ) to host controller110on a line146, into an interrupt interface118of host controller110. Upon receiving (204) an interrupt acknowledgement from host controller110, embedded controller120disconnects (206) the pass-through connection between bus segments102and104and connects its memory interface123to bus segment104. While the interrupt is being handled, embedded controller120accesses (208) memory unit130. Since the interrupt prevents host140from performing its normal processing activities, there is no danger that host controller110will access memory unit130and interfere with the memory access of embedded controller120. Upon completion of the memory access, embedded controller120reconnects (210) the pass-through connection between bus segments102and104and terminates (212) the interrupt, thus returning to pass-through operation state (200).

If (230), however, embedded controller120is in the permission-free state when accessing memory unit130, controller120directly disconnects (206) the pass-through connection and accesses the memory. In some embodiments of the invention, embedded controller120is in the permission-free state at times at which it is clear that host140and any other master will not access memory unit130, for example when host140is reset. Optionally, in embodiments in which embedded controller120is not expected to be in the permission-free state often, or at all, act230is not performed. After accessing memory unit130in the permission-free state, the pass-through connection is reconnected (210) and controller120returns to the pass-through state (200), without (240) performing acts required to terminate the interrupt procedure. Alternatively, in the permission-free state, controller120is continuously connected to memory unit130and the acts of disconnecting (206) and reconnecting (210) the pass-through connection are not required. When controller120leaves the permission-free state, the pass-through connection is connected.

In the exemplary embodiment ofFIG. 1, the disconnection (206) of host controller110from memory130is performed using multiplexer125. Alternatively, a TRI-STATE buffer scheme is used.

In some embodiments of the invention, the interrupt request of embedded controller120causes host controller110and host140to become idle by executing an interrupt process having no otherwise useful objective, possibly without performing any useful processing. Alternatively, the interrupt causes host140to perform maintenance tasks of computer100which do not involve accessing memory unit130. Optionally, the interrupt request sends host140to check whether a register128controlled by embedded controller120is asserted and to terminate the interrupt only when register128is asserted. When embedded controller120completes the memory access, it asserts the value of the register128. Alternatively, the interrupt causes host140to perform a task for a predetermined time, thereby allowing embedded controller120sufficient time to access memory unit130, and then resume its normal operation.

In some embodiments of the invention, in which additional processors may attempt to access memory130via host controller110or through any other available interface, the interrupt process of host140also disables the additional processors in order to prevent them from accessing memory unit130, while embedded controller120is accessing memory130.

Alternatively or additionally, the interrupt request is provided in parallel to a plurality of processors which may attempt to access memory130, or hardware handshake methods are used to notify one or more of the additional processors that they are to refrain from accessing memory130.

In an exemplary embodiment of the invention, a master154connects to host controller110through a PCI bus152. The interrupt process optionally instructs host controller110to prevent access to memory unit130, by not granting access requests from master154or any other processor or non-processor master, until the interrupt is completed. Alternatively or additionally, the interrupt process disables master154until the interrupt process is completed, in order to prevent master154from interfering with the memory access of EC120.

Optionally, host140is deactivated by interrupts of embedded controller120only infrequently, such as less than 0.5% of the time or even less than 0.1% of the time, so that the memory accessing of embedded controller120does not substantially disrupt the normal operation of host140. In some embodiments of the invention, embedded controller120performs tasks which require only limited memory access, for example only up to 100, or even only up to 50 memory accesses per second, each memory access optionally requiring less than 15 microseconds or even less than 10 microseconds, or even less than 7 microseconds. Alternatively, embedded controller120intensively accesses memory unit130, for example causing host140to be idle at least 5% or even at least 10% of the time. It has been determined by the inventors of the present invention that although such disruption of the operation of host140lowers its efficiency, the gain for requiring only a single memory unit130for both embedded controller120and host controller110outweighs this disadvantage under some circumstances.

While the interrupt request from embedded controller120is described hereinabove as passing through host controller110, in other embodiments of the invention the interrupt request on line146is provided directly to host140without passing through host controller110.

Referring in more detail to receiving (204) the interrupt acknowledgement; in some embodiments of the invention, the acknowledgement is provided on a dedicated hardware line144from host controller110to EC120, or on a similar line connected directly from host140, as part of a protocol for initiating and/or performing the interrupt. Alternatively, the acknowledgement is provided as an act of the initiated interrupt process, such as writing by the interrupt process into register128of embedded controller120. In some embodiments of the invention, however, an acknowledgement is not required at all, and embedded controller120proceeds in accessing (208) memory unit130, a predetermined time, for example 20 microseconds, after the interrupt request was sent.

The memory access (208) may include access to a single byte or other data block, or may include access to a plurality of data segments consecutively. The memory access (208) is optionally performed in a short session of less than 50 microseconds or even less than 20 microseconds.

Memory Access Control

In some embodiments of the invention, embedded controller120is configured to delay at least some memory accesses to memory unit130in order to meet constraints of one or more predetermined rules limiting the access to the memory unit and the disruption to the operation of host140. Optionally, embedded controller120allows access to memory unit130only after at least a predetermined time from a previous access. Alternatively or additionally, embedded controller120accumulates a predetermined number of accesses to be performed together before sending an interrupt request to host controller110. In some embodiments of the invention, in accordance with this alternative, if additional access reasons do not accumulate for a predetermined time, embedded controller120accesses memory unit130even if additional access reasons were not collected.

Three Processor Embodiment

FIG. 3is a schematic illustration of memory connections between memory unit130and other components, in accordance with another exemplary embodiment of the present invention.FIG. 3is similar toFIG. 1, mutatis mutandis, but inFIG. 3memory unit130is connected through a switch322to both host controller110and to an embedded controller320. A switch select324, controlled by embedded controller320determines whether host controller110or embedded controller320is actively connected to memory unit130.

FIG. 3also illustrates the sharing of memory unit130by three processors. In a steady state, host controller110is connected to memory unit130. When embedded controller320needs to access memory unit130, embedded controller320sends an interrupt request to host controller110and, upon receiving an acknowledgment, sets switch select324to operate with embedded controller320and performs its memory access. Similarly, when an additional processor350needs to access memory unit130it sends an interrupt request to host controller110. Host controller110optionally only acknowledges a single interrupt at one time, such that additional processor350does not need to disable embedded controller320when accessing memory unit130. When an acknowledgement is received from host controller110, switch select324is set to operate with additional processor350. Switch select324is optionally set by embedded controller320under instructions of additional processor350. Alternatively, switch select324is directly controlled by additional processor350, for example through a multiplexer or a mutually controlled line. After completing the data retrieval, additional processor350releases host controller110.

Alternatives

Although the above description relates to an SPI bus, some of the above described methods and embodiments may be implemented with other serial and parallel bus protocols. In some embodiments of the invention, for example, the bus protocol and/or the units implementing the bus protocol do not have provisions for delegating control of the bus. Alternatively or additionally, the bus protocol does not have provisions for allowing the transmitter to determine collisions. In some embodiments of the invention, the bus protocol does not involve a handshake between the processor and memory unit.

While a single memory unit130is shown inFIG. 1, it will be appreciated that in other embodiments, the technology described hereinabove is used for sharing a plurality of parallel memory units between a plurality of processors.

While in the above description host controller110is continuously connected to memory unit130and the embedded controller120sends an interrupt request to the host controller to access the memory unit130, in other embodiments of the invention different configurations are used. In one alternative configuration, host controller110sends an interrupt request to embedded controller120when accessing memory unit130is required.

Although the above description relates to sharing a memory unit, the above described methods may be used for sharing other resources.

Conclusion

It should be appreciated that the above described description of methods and apparatus are to be interpreted as including apparatus for carrying out the methods and methods of using the apparatus. It should be understood that, where appropriate, features and/or steps described with respect to one embodiment may be used with other embodiments and that not all embodiments of the invention have all of the features and/or steps shown in a particular figure or described with respect to a specific embodiment. Variations of embodiments described will occur to persons of the art.

It is noted that at least some of the above described embodiments include non-limiting details which were provided by way of example for illustration purposes and/or to describe the best mode contemplated by the inventors and therefore may include structure, acts or details of structures and acts that are not essential to the invention. Structure and acts described herein are replaceable by equivalents known in the art, which perform the same function, even if the structure or acts are different. Many specific implementation details may be used. Therefore, the scope of the invention is limited only by the elements and limitations as used in the claims, wherein the terms “comprise,” “include,” “have” and their conjugates, shall mean, when used in the claims, “including but not necessarily limited to.”