Kink poly structure for improving random single bit failure

A memory cell having a kinked polysilicon layer structure, or a polysilicon layer structure with a top portion being narrower than a bottom portion, may greatly reduce random single bit (RSB) failures and may improve high density plasma (HDP) oxide layer fill-in by reducing defects caused by various impurities and/or a polysilicon layer short path. A kinked polysilicon layer structure may also be applied to floating gate memory cells either at the floating gate structure or the control gate structure.

BACKGROUND

1. Technical Field

The present application relates generally to semiconductor devices and includes methods and structures for improving random single bit (RSB) failure.

2. Related Art

FIG. 1is a schematic diagram illustrating a cross-sectional view of a memory device100. The memory device100includes substrate110, oxide-nitride-oxide layer120, polysilicon layer130, and hard mask layer140. For example, the hard mask layer140comprises a silicon nitride (Si3N4) layer. The memory device100also includes high density plasma (HDP) oxide portions160. In conventional methods of constructing a memory device100may result in various impurities or particles that may lead to RSB failure.

For example, in some conventional memory devices, a particle defect151may occur. The particle defect may be a silicon nitride (Si3N4) particle, an impurity particle, or an HDP particle. The particle defect151may cause a void or gap156at the interface between the HDP oxide portion160and polysilicon layer130, which may result in a path for a later conductive layer to come into contact with the substrate110. As another example, a polymer residual152may result from etching from conventional memory device manufacturing techniques. For example, if an etchant recipe is not optimum, some bi-product residue may form on a side wall of a stack of polysilicon layer130and hard mask layer140, which may also potentially result in a path between a conductive layer and the substrate110. Weak oxide residues153may also exist. For example, if the HDP oxide is not optimum, an interface between the HDP oxide layer160and the stacks may be weak, which may also result in a path between a conductive layer and the substrate110. As another example, phosphoric acid154may flow down a crack in the polysilicon layer130, which can cause chemical damage on the substrate110resulting in an increased number of RSB failures. Further, the polysilicon layer130may have a rough side wall155which may result in cracks between the polysilicon layer130and the HDP oxide portions160, which may also result in an increased number of RSB failures. Any of these failures, if present during the deposition of a conductive layer, may cause the conductive layer to leak down to the substrate, causing a short or a RSB failure.

FIG. 2is a schematic diagram illustrating transmission electronic microscopy (TEM) view of RSB failures on a wafer200for a floating flash gate. As shown in portion256, a top conductive polysilicon layer PL3270has leaked down and is in connection with the substrate210, which may cause an RSB failure.

Thus, it is desirable to find new approaches for improving memory cell processes, particularly so as to decrease the number of RSB failures in memory devices.

SUMMARY

Disclosed herein are methods and systems for forming memory cells including floating gate memory cells.

According to an aspect, one or more stacks are formed on a substrate. Each stack includes an oxide-nitride-oxide (ONO) layer and a polysilicon layer formed on a top surface of the ONO layer. An oxide layer is formed between the stacks. The polysilicon layer of each of the stacks has side surfaces adjacent to the oxide layer between the stacks, and a top portion of the side surfaces of the polysilicon layer is narrower than a bottom portion of the side surfaces of the polysilicon layer.

According to another aspect, a substrate having an oxide-nitride-oxide (ONO) layer formed thereon is provided. A polysilicon layer is formed on a top surface of the ONO layer, and a hard mask silicon nitride (Si3N4) layer is formed on a top surface of the polysilicon layer. A partial pattern is to the polysilicon layer and the hard mask silicon nitride (Si3N4) layer to form stacks. Each stack includes a portion of the polysilicon layer and a portion of the hard mask silicon nitride (Si3N4) layer, and apertures are defined in the silicon nitride (Si3N4) hard mask and polysilicon layers between the stacks. The polysilicon layer of each of the stacks has side surfaces adjacent to the apertures, and the hard mask silicon nitride (Si3N4) layer of each of the stacks has side surfaces adjacent to the apertures. A portion of the hard mask silicon nitride (Si3N4) and polysilicon layers is removed, such that a top portion of the side surfaces of the polysilicon layer of each of the stacks are substantially flush with the side surfaces of the hard mask silicon nitride (Si3N4) layer of each of the stacks, and such that the top portion of the side surfaces of the polysilicon layer is narrower than a bottom portion of the side surfaces of the polysilicon layer.

According to another aspect, a memory cell includes a substrate, one or more stacks formed on the substrate, and an oxide layer formed over and between the stacks. The stacks include an oxide-nitride-oxide (ONO) layer and a polysilicon layer formed on a top surface of the ONO layer. The polysilicon layer of each of the stacks has side surfaces adjacent to the oxide layer between the stacks, and a top portion of the side surfaces of the polysilicon layer is narrower than a bottom portion of the side surfaces of the polysilicon layer.

According to another aspect, a floating gate memory cell includes a substrate, an insulation layer formed over the substrate, and a polysilicon floating gate structure formed over the insulation layer. A top portion of the polysilicon floating gate structure is narrower than a bottom portion of the polysilicon floating gate structure.

According to another aspect, a floating gate memory cell includes a substrate, an insulation layer formed over the substrate, a polysilicon floating gate structure formed over the insulation layer, a second insulation layer formed over the polysilicon floating gate structure, and a control gate structure. A top portion of the control gate structure is narrower than a bottom portion of the control gate structure.

DETAILED DESCRIPTION

Referring toFIGS. 3-9, cross-sectional view diagrams illustrate a memory cell and a method of forming a memory cell with a reduced number of RSB failures. The memory cell is made using partial polysilicon layer etching with hard mask pull-back (e.g., silicon nitride (Si3N4) pull-back). The memory cell and the processes used for forming the memory cell improve high density plasma oxide fill-in capability and improve random single bit (RSB) failures by interrupting the polysilicon layer short path using a kinked polysilicon profile created by the polysilicon layer etching and hard mask pull-back. A kinked polysilicon profile results in multiple advantages including, but not limited to, enhanced HDP oxide layer fill-in and greatly reducing or eliminating RSB failure issues discussed above.

FIG. 3is a schematic diagram illustrating a cross-sectional view of an N-bit memory cell300. Memory cell300includes a substrate310. An oxide-nitride-oxide (ONO) layer320is formed on the substrate310, and a polysilicon layer330is formed on the ONO layer320. A hard mask layer340is formed on the polysilicon layer330. In an embodiment, the hard mask layer is a silicon nitride (Si3N4) layer.

FIG. 4is a schematic diagram illustrating a cross-sectional view of a memory cell400with a partial pattern applied. Memory cell400includes a substrate410, an oxide-nitride-oxide (ONO) layer420formed on the substrate410, a polysilicon layer430formed on the ONO layer420, and a hard mask layer440formed on the polysilicon layer430. In an embodiment, the hard mask layer440may be a silicon nitride (Si3N4) layer. A partial pattern has been applied and a hard mask pull-back (e.g., silicon nitride (Si3N4) pull-back) process is used. For example, a phosphoric acid (H3PO4) is applied and approximately 100-150 Angstroms of hard mask is removed in a partial pattern, resulting in apertures450between stacks455of the polysilicon layer430and the hard mask layer440.

FIG. 5is a schematic diagram illustrating a cross sectional view of a memory cell500with dry etching used to further define a profile. Memory cell500includes a substrate510, an oxide-nitride-oxide (ONO) layer520formed on the substrate510, a polysilicon layer530formed on the ONO layer520, and a hard mask layer540formed on the polysilicon layer530. In an embodiment, the hard mask layer540may be a silicon nitride (Si3N4) layer. Apertures550are defined in the polysilicon layer530and the hard mask layer540. Dry etching is applied to the memory device500to further define the profile of the stacks555. The dry etching is used to remove more of the polysilicon layer530. For example, a portion of the polysilicon layer530is also removed by dry etching. And a top portion of the polysilicon layer530is also removed such that the sides of the polysilicon layer530are substantially flush with the sides of the hard mask layer540for a distance535from the top portion536of the polysilicon layer.

FIG. 5Bis a schematic diagram illustrating a detailed view of an stack555ofFIG. 5. Stack555includes ONO layer520, polysilicon layer530, and hard mask layer540. The polysilicon layer530of each of the stacks555has side surfaces559adjacent to the apertures, and the hard mask layer of each of the stacks also has side surfaces adjacent to the apertures. A portions of the hard mask and polysilicon layers have been removed, such that a top portion531of the side surfaces559of the polysilicon layer530of each of the stacks555are substantially flush with the side surfaces549of the hard mask layer540of each of the stacks555. Further, the top portion531of the side surfaces559of the polysilicon layer530is narrower than a bottom portion532of the side surfaces559of the polysilicon layer530. In an embodiment, the top portion531is narrower on each side of the stack555by a first distance537.

In an embodiment, a top portion531of the side surfaces549of the polysilicon layer530of each of the stacks555extends from the top surface536of the polysilicon layer530to an intermediate cross-section539of the polysilicon layer530of each of the stacks555, the intermediate cross-section539is a line substantially parallel to the top surface536of the polysilicon layer530. A second distance535is defined by a line extending from and substantially perpendicular to the top surface536of the polysilicon layer to the cross-section539of the polysilicon layer530. In an embodiment, the second distance is in the range of 100-200 Å. In another embodiment, the second distance is in the range of 100-150 Å.

FIG. 6is a schematic diagram illustrating a cross sectional view of a memory cell600with oxide layer or dielectric layer fill in applied. Memory cell600includes a substrate610, an oxide-nitride-oxide (ONO) layer620formed on the substrate610, a polysilicon layer630formed on the ONO layer620, and a hard mask layer640formed on the polysilicon layer630. In an embodiment, the hard mask layer640may be a silicon nitride (Si3N4) layer. To form the memory device600an oxide layer660(or dielectric layer660) is deposited over the stacks. In an embodiment, a high density plasma (HDP) oxide660is used to cover the stacks655and to fill the apertures650. High density plasma (HDP)-filled apertures650are defined in the polysilicon layer630and the hard mask layer640between stacks655. The peaks665, which are oxide layer660stacked over the stacks650, result in an uneven surface of the oxide layer660.

FIG. 7is a schematic diagram illustrating a cross sectional view of a memory cell700with chemical mechanical polishing (CMP) applied. Memory cell700includes a substrate710, an oxide-nitride-oxide (ONO) layer720formed on the substrate710, a polysilicon layer730formed on the ONO layer720, and a hard mask layer740formed on the polysilicon layer730. In an embodiment, the hard mask layer740may be a silicon nitride (Si3N4) layer. HDP760oxide-filled apertures750are defined in the polysilicon layer730and the hard mask layer740between stacks755. A chemical mechanical polishing (CMP) process is used to remove the oxide layer760deposited over the stacks755. In an embodiment, the CMP process is used until a top portion766of the oxide layer760is substantially flush with a top portion746of the hard mask740.

FIG. 8is a schematic diagram illustrating a cross sectional view of a memory cell800with hard mask removal applied. Memory cell800includes a substrate810, an oxide-nitride-oxide (ONO) layer820formed on the substrate810, and a polysilicon layer830formed on the ONO layer820. A hard mask layer840formed on the polysilicon layer830has been removed.

FIG. 9is a schematic diagram illustrating a cross sectional view of a memory cell900. Memory cell900includes a substrate910, an oxide-nitride-oxide (ONO) layer920formed on the substrate910, and a polysilicon layer930formed on the ONO layer920. HDP oxide960filled apertures950are defined in the polysilicon layer930resulting in stacks of polysilicon layer930and ONO layer920. Another polysilicon layer970is formed on a top portion966of the HDP oxide960and on a top portion936of the polysilicon layer930. A silicide layer980, such as tungsten polycide (WSix), titanium silicide, cobalt silicide, nickel, etc., is formed on a top portion976of the polysilicon layer970. The memory cell900includes a indention990in the top portion936of the polysilicon layer930, resulting in an interruption or prevention of a polysilicon layer930short path. For example, even if a random particle, such as those process defects discussed above, were to appear during the manufacturing process, the interface between the polysilicon layer930and HDP oxide layer960includes the indentation990to prevent potential voids from forming down to the substrate. Accordingly, when the HDP oxide layer960is applied, the indentation990substantially prevents or minimizes a void from forming at least beneath the indentation990(i.e., between the indentation990and the ONO layer920), substantially eliminating or minimizing the likelihood of a short path.

FIG. 10is a schematic diagram illustrating a top-level perspective view of a group of memory cells1000. Memory cells1000include a polysilicon layer1030formed over a substrate (not shown) and a high density plasma (HDP) oxide layer1060deposited over apertures defined in the polysilicon layer1030. Memory cells1000also include another polysilicon layer1070formed over the polysilicon layer1030and HDP oxide layer1060.

FIG. 11is a flow diagram illustrating a method1100for forming a memory cell. A silicon substrate is provided. An oxide-nitride-oxide (ONO) layer is formed over a top surface of the substrate. A polysilicon layer is formed over a top surface of the ONO layer, and a hard mask is formed over a top surface of the polysilicon layer. At action,1101, the substrate having an oxide-nitride-oxide (ONO) layer formed thereon, a polysilicon layer formed on a top surface of the ONO layer, and a hard mask layer formed on a top surface of the polysilicon layer is provided (as shown inFIG. 3). In an embodiment, the hard mask layer may be a silicon nitride (Si3N4) layer. In some embodiments, the method includes forming the ONO layer on the substrate, forming the polysilicon layer on the top surface of the ONO layer, and/or forming the hard mask layer on the top surface of the polysilicon layer.

A partial pattern is applied to the polysilicon layer and hard mask layer at action1102. The application of the partial pattern results in stacks (as shown inFIG. 4). Each stack includes a portion of the polysilicon layer and a portion of the hard mask layer. Apertures are defined between the hard mask and polysilicon layered stacks. Action1102may include using an etchant to partially remove the hard mask layer and the polysilicon layer as a hard mask pull back (e.g., silicon nitride pull-back). In some embodiments, phosphoric acid (H3PO4) is used as the etchant.

At action1104, the profile of each stack is further defined using a dry etching. The polysilicon layer of each stack has side surfaces adjacent to the apertures, and the hard mask layer of each stack has surfaces adjacent to the apertures. Action1104may include etching a top portion of the side surfaces of the polysilicon layer such that the top portion of the side surfaces of the polysilicon layer of each stack are substantially flush with the side surfaces of the hard mask layer of each stack (as shown inFIG. 5). This results in an indentation in the polysilicon layer, which may prevent potential voids from forming down to the substrate. In some embodiments, the top portion of the side surfaces of the polysilicon layer may extend from the top surface of the polysilicon layer to an intermediate cross-section of the polysilicon layer. The intermediate cross-section of the polysilicon layer is a line parallel to the top surface of the polysilicon layer. In an embodiment, a distance defined by a line extending from and perpendicular to the top surface of the polysilicon layer to the cross-section of the polysilicon layer is in the range of 100-200 Å.

At action1106, an oxide layer filling is formed in the apertures and over the stacks of the polysilicon and hard mask layers (as shown inFIG. 6). When the HDP oxide layer is applied, the indentation substantially prevents or minimizes a void from forming at least beneath the indentation (i.e., between the indentation and the ONO layer), which may substantially eliminate or minimize the likelihood of a short path. The oxide layer filling may include a high density plasma (HDP) oxide. The partial patterning (action1102) combined with the hard mask pull back also may allow for improved high density plasma (HDP) oxide fill in. The partial patterning and hard mask pull back may result in wider than normal apertures between the stacks. HDP oxide deposition is typically done at an angle, e.g., 45°, and a wider aperture may allow for more even HDP oxide deposition.

At action1108, a chemical mechanical polishing (CMP) process is used to remove a portion of the oxide layer filling. In an embodiment, the portion removed is such that a top surface of the oxide layer filling is substantially flush with the top surface of the hard mask layer (as shown inFIG. 7).

At action1110, the hard mask layer is removed. Action1110may include using phosphoric acid (H3PO4) to remove the hard mask layer. Action1110may result in a recessed portion defined in the oxide layer filling and the top surface of the polysilicon layer (as shown inFIG. 8).

At action1112, a second polysilicon layer is formed on a top surface of the oxide layer and on the top surface of the polysilicon layer. The second polysilicon layer may be used to fill in the recessed portion be formed over the stacks (as shown inFIG. 9). This results in the benefit of further minimizing the likelihood of a second polysilicon short path. Also at action1112, a tungsten polycide (WSix) layer may be formed on a top surface of the second polysilicon layer (as shown inFIG. 9).

The kinked or indented polysilicon layer design discussed above can be applied to various other structures in memory cell manufacturing processes. For example, the kinked or indented formation can be applied to floating gate technology.

FIG. 12is a schematic diagram illustrating a floating gate memory cell1200having a kinked or indented profile1255. The floating memory cell may have a substrate1210, an insulation layer1220formed over the substrate1210, and a polysilicon floating gate structure1230formed over the insulation layer1220. The polysilicon floating gate structure1230may have a top portion1234and a bottom portion1236, and, in an embodiment, the top portion1234of the polysilicon floating gate structure1230is narrower than the bottom portion1236of the polysilicon floating gate structure1230. The polysilicon floating gate structure1230may have a top surface1235and side surfaces1233. The top portion1236may be defined by the top surface1235, a top portion of the side surfaces1233, and an intermediate cross section1238of the polysilicon floating gate structure1230. The intermediate cross section1238is defined by a line substantially parallel to the top surface1235of the polysilicon floating gate structure1230. The bottom portion1236of the polysilicon floating gate structure1230is defined by the intermediate cross section1238and a bottom portion of the side surfaces1233.

In an embodiment, the floating gate memory cell1200further includes a second insulation layer1240formed over the polysilicon floating gate structure1230. The floating gate memory cell1200may further include a polysilicon or silicide layer1250formed over the second insulation layer1240. The substrate1210may be made of a silicon material. The insulation layer1220may be made of silicon dioxide. The second insulating layer1240may comprise an oxide-nitride-oxide (ONO) layer. Using a kinked or indented profile in the floating gate structure may result in improved polysilicon or silicide material layer fill-in.

FIG. 13is a schematic diagram illustrating another floating gate memory cell1300having a kinked or indented profile1355. The floating gate memory cell1300may have a substrate1310, an insulation layer1320formed over the substrate1310, and a polysilicon floating gate structure1325formed over the insulation layer1320. The floating gate memory cell1300may further include a second insulation layer1330formed over the floating gate structure1325and a control gate structure1340formed over the second insulation layer1330. The control gate structure1340may have a top portion1344and a bottom portion1346, and, in an embodiment, the top portion1344of the control gate structure1340is narrower than the bottom portion1346of the control gate structure1340. The control gate structure1340may have a top surface1345and side surfaces1343. The top portion1346may be defined by the top surface1345, a top portion of the side surfaces1343, and an intermediate cross section1348of the control gate structure1340. The intermediate cross section1348is defined by a line substantially parallel to the top surface1345of the control gate structure1340. The bottom portion1346of the control gate structure1340is defined by the intermediate cross section1348and a bottom portion of the side surfaces1343.

In an embodiment, the floating gate memory cell1300further includes a third insulation layer1350formed over the control gate structure1340, second insulating layer1330, polysilicon floating gate structure1325, insulating layer1320, and substrate1310. The substrate1310may be made of a silicon material. The insulation layer1320may be made of a dielectric material including, but not limited to, various oxide layers. The second insulating layer1330may comprise an oxide-nitride-oxide (ONO) layer. The third insulating layer1350may be made of silicon dioxide or other suitable insulating materials. The control gate structure1340may be made of a silicide material or a polysilicon material. Using a kinked or indented profile1355in the control gate structure1340may result in improved inter layer dielectric (ILD) piping and/or self-alignment source side fill-in performance.