Method and apparatus for reading NAND flash memory array

The method for reading/verifying a NAND flash memory device alternates the select gate biasing in response to the position of the cell to be read. If the cell is closer to the top of the column, the SG(D) line is biased prior to the SG(S) line. If the cell is closer to the bottom of the column, the SG(S) line is biased prior to the SG(D) line.

TECHNICAL FIELD OF THE INVENTION

The present invention relates generally to memory devices and in particular the present invention relates to NAND flash memory devices.

BACKGROUND OF THE INVENTION

Flash memory devices have developed into a popular source of non-volatile memory for a wide range of electronic applications. Flash memory devices typically use a one-transistor memory cell that allows for high memory densities, high reliability, and low power consumption. Common uses for flash memory include personal computers, personal digital assistants (PDAs), digital cameras, and cellular telephones. Program code and system data such as a basic input/output system (BIOS) are typically stored in flash memory devices for use in personal computer systems.

Two common types of flash memory array architectures are the “NAND” and “NOR” architectures, so called for the logical form in which the basic memory cell configuration or each is arranged. In the NOR array architecture, the floating gate memory cells of the memory array are arranged in a matrix. The gates of each floating gate memory cell of the array matrix are coupled by rows to word select lines and their drains are coupled to column bit lines. The NOR architecture floating gate memory array is accessed by a row decoder activating a row of floating gate memory cells by selecting the word select line coupled to their gates. The row of selected memory cells then place their data values on the column bit lines by flowing different currents depending on if a particular cell is in a programmed state or an erased state.

A NAND array architecture also arranges its array of floating gate memory cells in a matrix such that the gates of each floating gate memory cell of the array are coupled by rows to word select lines. However each memory cell is not directly coupled to a column bit line by its drain. Instead, the memory cells of the array are coupled together in series, source to drain, between a source line and a column bit line.

The NAND architecture floating gate memory array is accessed by a row decoder activating a row of floating gate memory cells by selecting the word select line coupled to their gates. A high bias voltage is applied to a select gate drain line SG(D). In addition, the word lines coupled to the gates of the unselected memory cells of each group are driven to operate the unselected memory cells of each group as pass transistors so that they pass current in a manner that is unrestricted by their stored data values. Current then flows from the source line to the column bit line through each series coupled group, restricted only by the selected memory cells of each group. This places the current encoded data values of the row of selected memory cells on the column bit lines.

FIG. 1illustrates voltages at various times during typical prior art NAND verify and read operations. Between times T1and T3, the select gate source SG(S) line is biased with 4.5V. Also during this time, the unselected wordlines are biased with the same voltage. In this example, only WL0is shown. The selected wordlines are typically between 0V and 0.2V.

Between times T3and T4the SG(D) line is biased with 4.5V until the bitline discharges at time T5. The 4.5V bias is removed from all of the lines at time T6.

One problem that might occur with NAND arrays, however, is illustrated inFIG. 1. Due to the small geometry of the NAND architecture, WL0and SG(D) are capacitively coupled. Similarly, WL32and SG(S) are capacitively coupled. When the 4.5V bias is applied to the SG(D) line, WL0also increases by 1.0–1.5V above the 0.2V already on the line. This has the potential to cause read errors since the cells on WL0are turned on when they are not supposed to be selected.

SUMMARY

The above-mentioned problems with NAND flash memory and other problems are addressed by the present invention and will be understood by reading and studying the following specification.

The present invention encompasses a method for reading and/or verifying a NAND flash memory array. The array comprises a column of memory cells that have one end controlled by a select gate drain line and the other end controlled by a select gate source line. An input address signal is decoded to determine which cell to select. The order of biasing of the select gate drain and the select gate source lines is responsive to the position of the selected cell in the column. If the selected cell is closer to the selected gate drain line, that select gate is biased before the select gate source line.

Further embodiments of the invention include methods and apparatus of varying scope.

DETAILED DESCRIPTION

FIG. 2illustrates a schematic diagram of one embodiment of a NAND flash memory array of the present invention. The array is comprised of a large number of memory cells201and202. The quantity of memory cells varies with the size of the memory device.

Select gate lines SG(D)205and SG(S)206are enabled when a read operation is to be performed. The biasing of the select gate lines turns on their respective control transistors230and231. The select lines205and206are biased with 4.5V during the read operation. Due to the closeness of SG(D)205to WL0201and SG(S) to WL31202, capacitive coupling occurs between these lines when the select lines are biased. This capacitance is represented inFIG. 2by capacitors220and221. As is well known in the art, a bitline209is precharged to VCCduring a read operation.

When a wordline is not selected, it is biased at 4.5V along with SG(D)205and SG(S)206. When a word line is selected, it is at or close to 0V. When WL(0) is selected and SG(D)205is biased at 4.5V, the capacitance220between these lines causes the voltage of WL(0) to momentarily go above 1.7V thus causing the cells on that wordline to be momentarily unselected. Similarly, when WL(31) is selected and SG(S)206is biased at 4.5V, the capacitance221between these lines affects the read operation.

The method of the present invention for reading a NAND flash memory array switches the timing of the SG(D) and SG(S) biasing when an address within a predetermined range is detected. In one embodiment, this address range is the cell201closest to the SG(D) signal205or the cell202closest to the SG(S) signal206. In an alternate embodiment, the address range is the top three cells and the bottom three cells. The present invention is not limited to any one address range or ranges since distance from the select lines, composition of the select lines, and other factors may change the amount of capacitive coupling between the select lines and the nearby wordlines. In an alternate embodiment, the address ranges for the drain end of the column is different than the address range for the source end of the column.

In still another embodiment, only the addresses at the top of the column of cells cause the bias timing to switch. In this embodiment, if an address for the bottom of the column is detected, the SG(S) and SG(D) bias timing do not change.

FIG. 3illustrates a block diagram of one embodiment of an address decoder with a NAND flash memory array of the present invention. In one embodiment, the address decoder302encompasses both a row decoder and a column decoder.

The memory device's address bus305is input to the address decoder302. The decoder302determines if the input address is within the predetermined range for a particular embodiment. If such an address is detected, the memory device controller310is alerted in some manner so that the timing of the generation of the select line bias voltages is changed for that particular cell location. In one embodiment, the controller310is alerted by an indication signal from the address decoder302.

FIG. 4illustrates a flowchart of one embodiment of the method of the present invention for reading or verifying a NAND flash memory array. The method decodes the input address401to determine if the cell to be read or verified is within a predetermined range (e.g., top of the column). If the cell is not within the predetermine range402, the SG(D) and SG(S) lines are biased normally405. If the cell is within the predetermined range402, the bias timing of the SG(D) and SG(S) lines is switched403such that the SG(D) line is biased prior to the SG(S) line as is illustrated subsequently inFIG. 5.

FIG. 5illustrates a timing diagram of one embodiment of the method of the present invention for reading or verifying a NAND flash memory array. In this embodiment, there are six time intervals: T1–T2is the SG(D) set-up and bitline precharge operation, T1–T3is the wordline set-up, T3–T4is the SG(S) set-up, and T4–T5is the select page read and bitline discharge. After T6, the biasing of the select gate lines and the wordlines is removed.

In the embodiment ofFIG. 5, the decoded address is for a cell at the top of the column closest to the SG(D) signal. For purposes of illustration, this cell is coupled to WL0. However, the present invention is not limited to just the cells on WL0but could have been other cells close to the top of the column of cells (e.g., WL1, WL2, WL3). The further the cell is from the select gate line, the less the capacitive coupling experienced.

When SG(D) is biased to 4.5V500between T1and T2and WL0floats to 0.2V503between T1and T3, the ramp-up of SG(D) causes WL0to initially have a “bump”501in voltage between T1and T2before it settles down to the normal 0.2V. However, since SG(S) is biased to 4.5V510after this “bump” occurs (e.g., between T3and T4), the increased voltage on WL0does not affect the read/verify operation.

FIG. 5also illustrates the unselected wordlines are biased to 4.5V502. This occurs between T1and T3. The unselected bitlines are at 0V (i.e., “1” or erased cells) while the selected bitlines are at 1.1V (i.e., “0” or programmed cells).

FIG. 6illustrates an alternate embodiment of the method of the present invention for reading/verifying a NAND flash memory array. In this embodiment, there are six time intervals: T1–T2is the SG(S) set-up and bitline precharge operation, T1–T3is the wordline set-up, T3–T4is the SG(D) set-up, and T4–T5is the select page read and bitline discharge. After T6, the biasing of the select gate lines and the wordlines is removed.

In the embodiment ofFIG. 6, the decoded address is for a cell at the bottom of the column closest to the SG(S) signal. For purposes of illustration, this cell is coupled to WL31. However, the present invention is not limited to just the cells on WL31but could have been other cells close to the top of the column of cells (e.g., WL28, WL29, WL30). The further the cell is from the select gate line, the less the capacitive coupling experienced.

When SG(S) is biased to 4.5V600between T1and T2and WL31floats to 0.2V603between T1and T3, the ramp-up of SG(S) causes WL31to initially have a “bump”601in voltage between T1and T2before it settles down to the normal 0.2V. However, since SG(D) is biased to 4.5V610after this “bump” occurs (e.g., between T3and T4), the increased voltage on WL31does not affect the read/verify operation.

FIG. 6also illustrates the unselected wordlines are biased to 4.5V602. This occurs between T1and T3. The unselected bitlines are at 0V (i.e., “1” or erased cells) while the selected bitlines are at 1.1V (i.e., “0” or programmed cells).

While the embodiments of the present invention discuss biasing the wordlines and select gate lines at 4.5V and 0V, it is well known in the art that variations in materials and processes result in different bias voltages. These bias voltages may vary by tenths of a volt above or below the target bias voltage. Alternate embodiments that use different manufacturing processes may use voltages other than 4.5V for biasing.

FIG. 7illustrates a functional block diagram of a memory device700that can incorporate the NAND flash memory cells of the present invention. The memory device700is coupled to a processor710. The processor710may be a microprocessor or some other type of controlling circuitry. The memory device700and the processor710form part of an electronic system720. The memory device700has been simplified to focus on features of the memory that are helpful in understanding the present invention.

The memory device includes an array of memory cells730. In one embodiment, the memory cells are non-volatile floating-gate memory cells and the memory array730is arranged in banks of rows and columns.

An address buffer circuit740is provided to latch address signals provided on address input connections A0–Ax742. Address signals are received and decoded by a row decoder744and a column decoder746to access the memory array730. It will be appreciated by those skilled in the art, with the benefit of the present description, that the number of address input connections depends on the density and architecture of the memory array730. That is, the number of addresses increases with both increased memory cell counts and increased bank and block counts.

The memory device700reads data in the memory array730by sensing voltage or current changes in the memory array columns using sense/buffer circuitry750. The sense/buffer circuitry, in one embodiment, is coupled to read and latch a row of data from the memory array730. Data input and output buffer circuitry760is included for bi-directional data communication over a plurality of data connections762with the controller710). Write circuitry755is provided to write data to the memory array.

Control circuitry770decodes signals provided on control connections772from the processor710. These signals are used to control the operations on the memory array730, including data read, data write, and erase operations. The control circuitry770may be a state machine, a sequencer, or some other type of controller. The embodiments of the method of the present invention are executed by the control circuitry770.

The flash memory device illustrated inFIG. 7has been simplified to facilitate a basic understanding of the features of the memory. A more detailed understanding of internal circuitry and functions of flash memories are known to those skilled in the art.

CONCLUSION

In summary, the method for reading/verifying a NAND flash memory device of the present invention alternates the select gate biasing in response to the position of the cell to be read. If the cell is close to the top of the column, the SG(D) line is biased prior to the SG(S) line. If the cell is closer to the bottom of the column, the SG(S) line is biased prior to the SG(D) line. This substantially reduces or eliminates read errors caused by capacitive coupling of the wordlines with the select gate biasing.