GATE STRUCTURE OVER CORNER SEGMENT OF SEMICONDUCTOR REGION

Embodiments of the disclosure provide a gate structure over a corner segment of a semiconductor region. A structure according to the disclosure includes a semiconductor region within a substrate. The semiconductor region includes a first edge, a second edge oriented perpendicularly to the first edge, and a first corner segment connecting the first edge to the second edge. A first gate structure extends over the first edge, and entirely covers the first edge and the first corner segment of the semiconductor region.

BACKGROUND

1. Technical Field

The present disclosure relates to integrated circuit (IC) technology. Embodiments of the disclosure provide a structure with a gate structure over the corner segment of a semiconductor region.

2. Background Art

Fabricating transistors within integrated circuits (ICs) may include, in a variety of orders: doping semiconductor material, forming a gate structure over the semiconductor material, epitaxially growing source and drain terminals from the semiconductor material, forming silicide regions in active semiconductor material, and forming conductors to the source/drain terminals and gate. For source and drain terminals formed by epitaxial growth over the substrate, an electrically inactive gate (e.g., diffusion break structure) may be at an edge of the semiconductor material to provide a physical boundary to prevent subsequently formed materials from protruding into the substrate, and/or for epitaxial growth and/or silicide formation. A possible disadvantage to this methodology is that conductive contacts to the raised source or drain terminal, especially in proximity to the corner of the semiconductor material, may penetrate thinner portions of the semiconductor material near the inactive gate(s), thus directly connecting to the substrate in undesirable areas.

SUMMARY

All aspects, examples and features mentioned below can be combined in any technically possible way.

An aspect of the disclosure provides a structure including: a semiconductor region within a substrate, the semiconductor region having a first edge, a second edge oriented perpendicularly to the first edge, and a first corner segment connecting the first edge to the second edge; and a first gate structure extending over the first edge, wherein the first gate structure entirely covers the first edge and the first corner segment of the semiconductor region.

Another aspect of the disclosure provides a semiconductor region within a substrate, the semiconductor region having a width between a first edge and a second edge; and a first gate structure extending over the first edge of the semiconductor region, wherein the first gate structure includes: a first portion having a first width, and a second portion having a second width greater than the first width, wherein the second portion is over a corner segment of the semiconductor region.

Yet another aspect of the disclosure provides a structure including: a semiconductor region within a substrate, the semiconductor region having a first edge, a second edge oriented perpendicularly to the first edge, and a first corner segment connecting the first edge to the second edge; a first gate structure extending over the first edge; and a masking material over the semiconductor region and the first gate structure, wherein the first gate structure and the masking material entirely cover the first edge and the first corner segment of the semiconductor region.

Two or more aspects described in this disclosure, including those described in this summary section, may be combined to form implementations not specifically described herein.

DETAILED DESCRIPTION

Reference in the specification to “one embodiment” or “an embodiment” of the present disclosure, as well as other variations thereof, means that a particular feature, structure, characteristic, and so forth described in connection with the embodiment is included in at least one embodiment of the present disclosure. Thus, the phrases “in one embodiment” or “in an embodiment,” as well as any other variations appearing in various places throughout the specification are not necessarily all referring to the same embodiment. It is to be appreciated that the use of any of the following “/,” “and/or,” and “at least one of,” for example, in the cases of “A/B,” “A and/or B” and “at least one of A and B,” is intended to encompass the selection of the first listed option (a) only, or the selection of the second listed option (B) only, or the selection of both options (A and B). As a further example, in the cases of “A, B, and/or C” and “at least one of A, B, and C,” such phrasing is intended to encompass the first listed option (A) only, or the selection of the second listed option (B) only, or the selection of the third listed option (C) only, or the selection of the first and the second listed options (A and B), or the selection of the first and third listed options (A and C) only, or the selection of the second and third listed options (B and C) only, or the selection of all three options (A and B and C). This may be extended, as readily apparent by one of ordinary skill in the art, for as many items listed.

Embodiments of the disclosure provide a gate structure over a corner segment of a semiconductor region. The gate structure constrains epitaxial growth of source/drain (S/D) material formed on the semiconductor region, permits forming of contacts to the S/D material and maintains a desired surface area for transistor components to conform with product specifications (e.g., standard cell sizes). A structure according to the disclosure includes a semiconductor region within a substrate. The semiconductor region includes a first edge, a second edge oriented perpendicularly to the first edge. A corner segment connects the first edge to the second edge, e.g., through a rounded or otherwise curvilinear segment for joining the two differently oriented edges. A first (e.g., non-active) gate structure extends over the first edge, and entirely covers the first edge and the corner segment of the semiconductor region. Thus, the corner segment is entirely below the first gate-structure to prevent epitaxial semiconductor material from growing over the corner segment. Further embodiments may include masking material over the first gate structure and/or corner segment to further confine epitaxial growth to a desired area.

FIG.1depicts a plan view of a structure100according to embodiments of the disclosure. Structure100may represent part of a larger segment of material distributed across a two-dimensional area in plane X-Y. Structure100may be formed on a substrate of semiconductor material, which may be the base material on/within which further materials (e.g., variously doped well regions, transistor structures, insulator regions, and/or other electrical components of a device) are formed. The substrate may include but is not limited to silicon, germanium, silicon germanium (SiGe), silicon carbide, or any other common IC semiconductor substrates. In the case of SiGe, the germanium concentration in the substrate may differ from other SiGe-based structures described herein. A portion or entirety of the substrate may be strained. Various portions of structure100may be formed on or from portions of the initial substrate material, and thus it is not specifically identified in the plan view ofFIG.1and subsequent illustrations.

Structure100extends horizontally within the X-Y plane. Each material or component of structure100may have a width in the X direction and a length in the Y direction. However, the “width” and “length” directions may refer to different orientations in further embodiments. Structure100may include a group of trench isolation (TI) regions102to electrically separate various regions of doped semiconductor material104from each other. TI regions102may be composed of any insulating material such as silicon oxide, e.g., SiO2. Other materials appropriate for the composition of TI regions136may include, for example, borophosphosilicate glass (BPSG), spin-on glass and/or spin-on polymers, other insulators having an effective dielectric constant of less than approximately 3.9, and/or other currently known or later-developed materials having similar properties.

Structure100may include several semiconductor regions104adjacent and/or confined within TI regions102. Semiconductor regions104nay have a dopant to provide a selected polarity, i.e., P-type doping or N-type doping, to enable electrical functions of a transistor or other active electrical component. A “dopant” refers to an element introduced into semiconductor to establish either p-type (acceptors) or n-type (donors) conductivity. In the case of a silicon substrate, common dopants may include, e.g., boron (B), and/or indium (In), for p-type doping. For n-type doping, the doped element(s) may include, for example, phosphorous (P) arsenic (As), and/or antimony (Sb). Doping is the process of introducing impurities (dopants) into the semiconductor substrate, or elements formed on the semiconductor substrate, and is often performed with a mask (e.g., a film of photoresist material and/or other component to block dopants) in place so that only certain areas of the substrate will be doped. In the example of doping by implantation, an ion implanter may be employed. In further examples, in-situ doping or other doping techniques may be used.

Structure100may include multiple structures extending lengthwise over TI regions(s)102and semiconductor regions104. For example, structure100may include a set (i.e., one or more) of first gate structures106and a set of second gate structure108over semiconductor regions104. In the example ofFIG.1, structure100includes two first gate structures106and one second gate structure108, but the number of gate structures106,108may differ in various implementations. Each first gate structure106may include a gate body110over TI region(s)102and/or semiconductor regions104. Gate body(ies)110within first gate structure106, may be formed of polycrystalline silicon or an amorphous silicon. In this example, gate body(ies)110may be a “dummy gate” material for removal and replacement in subsequent processing. In still further embodiments gate body(ies) may include conductive metal(s) and/or other types of materials. Second gate structure108, in some implementations, may include a gate contact116including, among other things, one or more conductive materials (e.g., one or more high work function metals) suitable to provide a gate contact for a transistor. Gate body(ies)110may be formed from doped or undoped polycrystalline silicon (poly-Si) according to one example. In further examples, gate body110may include materials such as, but not limited to, aluminum (Al), zinc (Zn), indium (In), tin (Sn), tantalum (Ta), tantalum nitride (TaN), tantalum carbide (TaC), titanium (Ti), titanium nitride (TiN), titanium carbide (TiC), tungsten (W), tungsten nitride (WN), tungsten carbide (WC), and/or combinations thereof.

Applying a voltage to gate contact116of second gate structure108may put underlying areas of semiconductor region104in an operational state, e.g., allowing charge carriers to flow within semiconductor region104. Gate body110may be differentiated from gate contact116, e.g., by not producing the same effect when subject to an applied voltage. Various spacers112(e.g., layers of insulating material) may be included within and/or formed on sidewalls of gate structure(s)106,108. Spacers112are illustrated inFIG.1as only being on second gate structure108, but this is not necessarily true in all implementations.

Structure100may include several source/drain (S/D) contacts114on semiconductor region104, e.g., each adjacent one first gate structure106and on opposite sides of second gate structure108. S/D contacts114may include a pair of contacts adjacent a respective sidewall of second gate structure108to define source and drain terminals of a functional transistor structure and/or other device. S/D contacts114may extend vertically above structure100to overlying metal wires and/or vias and may be formed by deposition of conductive materials.

One or more second gate structures108of structure100may include gate contact116, e.g., to define a conductive contact and/or terminal of an active device. In the case of a transistor, applying a voltage to gate contact116and second gate structure108can enable current flow through semiconductor region104below second gate structure108. In some cases, gate contact116may be structurally incorporated into a material similar to gate body110of first gate structure106, e.g., by having a same composition as gate body110but being doped P-type or N-type to provide conductivity. Otherwise, gate contact(s)116may have one or more conductive materials otherwise used to form or define S/D contacts114. First gate structures106may differ from second gate structure108by not including gate contact116and/or other conductive materials therein. Thus, first gate structures106may be operationally inactive and present in structure100primarily or solely to constrain the growth of additional doped material(s) formed on semiconductor region104, and/or to maintain constant gate pitch for improved manufacturability and/or to prevent electrical shorting from S/D contacts114to other active components. In still further embodiments, other portions of first gate structure106(e.g., those not included within structure100) may include gate contact(s)116.

Referring toFIGS.1and2together, in whichFIG.2provides an expanded view of semiconductor region104with overlying portions of first gate structure106shown in dashed lines, additional features of structure100are described. Semiconductor region104may include a first edge120, e.g., at widthwise end of semiconductor region104, and a second edge122, e.g., at a lengthwise end of semiconductor region104. First edge120and second edge122may have different orientations, e.g., they may be substantially perpendicular to each other or otherwise may have any non-parallel orientation with respect to each other. Semiconductor region104, as well as edges120,122, may extend beyond the portion illustrated inFIG.2as indicated by the dashed lines.

A corner segment124may join first edge120of semiconductor region104to second edge122. The term “corner segment,” as used herein, may refer to any non-linear segment joining one edge of semiconductor region104to another. In the case where semiconductor region104is quadrilateral, it may have four corner segments124. However, the number of corner segments124may vary depending on the number of interconnected edges featured in semiconductor region104. It has been determined that corner segments(s)124, when not covered by overlying materials, may negatively affect the shape and size of epitaxial semiconductor material(s) formed on semiconductor region104, and/or may pose a risk of other structural defects arising from S/D contact114(FIG.1) placement. Specifically, S/D contact(s)114may “punch through” semiconductor region104to enter the underlying substrate material if they are wrongfully formed on corner segment(s)124. “Punch through” may occur, in part, due to the different compositions and/or material densities of semiconductor region104along corner segments124.

Embodiments of structure100avoid the above-noted and other technical concerns by sizing and positioning first gate structure(s)106over semiconductor region104such that first gate structure(s)106entirely cover corner segment(s)124.FIGS.1and2depict one example in which first gate structure106includes a first portion106aextending over first edge120of semiconductor region104, as well as adjacent TI region(s)102. First gate structure106also may include a second portion106badjacent first portion106a. Second portion106bmay be differently sized (e.g., wider) than first portion106asuch that it entirely covers corner segment124and any nearby portions of first edge120and second edge122. The greater width of second portion106brelative to first portion106amay arise from a variety of sources, e.g., inactive semiconductor material of first gate structure106being formed with a differently sized mask in second portion106band/or being etched back in first portion106ato yield different widths. In any case, S/D contact(s)114(FIG.1) may be substantially horizontally aligned (e.g., along the X-axis) with first portion106ato prevent physical overlap between S/D contact(s)114and second portion106bof first gate structure106.

Further embodiments of the disclosure discussed herein may provide other structural features for covering corner segment(s)124while preserving space over semiconductor region104to form S/D contact(s)114. The distance S between S/D contact(s)114and second portion106bof second gate structure106may be selected to be greater than zero (e.g., fifty nanometers, one micrometer, etc.) to further prevent overlap between second portion106band S/D contact(s)114, according for variations in S/D contact114placement. It is noted that second gate structure108, in contrast to first gate structure106, may have a uniform width over semiconductor region104, e.g., because no corner segments124are located thereunder and/or to preserve the active functions of second gate structure108in a transistor (or other device).

FIGS.3-5depict further implementation of structure100, in which first gate structure106includes differing widths in first portion106aand second portion106b, but with further structural features. It is understood that the various implementations discussed herein may be combined in various aspects and/or may be implemented together as portions of a larger device. Corner segment(s)124(FIG.2), though not shown explicitly inFIGS.3-5, may occupy(ies) the same position and/or similar positions to that shown inFIG.2and discussed elsewhere herein.

FIG.3depicts an implementation where first gate structures106are asymmetric about their lengthwise centerline axis. In this case, second portions106bmay protrude along the width of first gate structure106over corner segment124(FIG.2), but do not similarly protrude along the width in the opposite direction. In this case, portions106a,106bof each first gate structure106may have a shared sidewall W that extends continuously along the length of first gate structure106, but not on the opposite horizontal end.

FIG.4depicts a further example of structure100in which gate body110of first gate structure106are of uniform width but include differently sized spacer structures adjacent thereto. For example, first portion106amay have spacer112with a first width T1that is of a similar width to spacers112of second gate structure108, whereas second portion106bmay have a spacer132of a second width T2that is substantially larger than first width T1of spacer112to cover corner segment(s)124(FIG.2) thereunder. Thus, the differences in size and shape between portions106a,106bmay be achieved by variations and/or modification in the processing of spacer(s)112,132on first gate structures106.

FIG.5depicts yet another example in which S/D contacts114are horizontally between second portion106band second gate structure108, rather than being horizontally between first portion106aand second gate structure108. Here, gate body110of first gate structure106may have second portion106bwith a larger width N2than a width N1of an adjacent first portion106a. Hence, second portion106bis entirely over first edge120(FIG.2) and corner segment124(FIG.2) throughout semiconductor region104. In this implementation, S/D contact(s)114may be closer to first gate structure(s)106than in other implementations of structure100. However, first gate structure(s)106may be able to further constrain the growth of any semiconductor materials over semiconductor region104, e.g., by traversing an entire length of semiconductor region104.

FIG.6depicts a further implementation of structure100. In this embodiments, multiple second gate structures108are provided over semiconductor region104. Here, each second gate structure108may be embodied as and/or may include an active gate component for defining at least a portion of a transistor or similar device over semiconductor region104. First gate structures106may be located at the widthwise ends of semiconductor region104, e.g., to extend along the length of semiconductor region104at its opposite ends. Each semiconductor region104, located between two gate structures108, may or may not contain a S/D contact114depending on the intended functionality of the device. Despite the inclusion of multiple second gate structures108, first gate structures106may be the same and or similar to other implementations of structure100discussed herein. That is, first gate structures106may entirely cover any corner segment(s)124of semiconductor region104despite the presence of multiple second gate structures108. Thus, embodiments of structure100may be implemented even where multiple active gates (e.g., second gate structures108) are over semiconductor region104.

FIG.7depicts yet another implementation of structure100in which additional material(s) may be formed on first gate structure(s)106, e.g., to further protect against punch through of semiconductor region104and/or shorting between first gate structure(s)106and S/D contact(s)114. Here, structure100may include a masking material140over semiconductor region104and first gate structure106(e.g., over first portion106athereof). Masking material140may include any now known or later developed appropriate masking material, e.g., a nitride hard mask including silicon nitride (SiN) or similar insulating materials. In some implementations, masking material140may take the form of a “gate cut mask” otherwise used for targeting and removing portions of gate body110of first gate structure106and/or other materials. In implementations where masking material140is present, first gate structure106may extend lengthwise over first edge120(FIG.2) and corner segment124(FIG.2) of semiconductor region104and may have a uniform width. Masking material140, in this case, may be included to prevent electrical shorting from gate body110to S/D contact114. Masking material140thus may be horizontally between S/D contact(s)114and first gate structure106. In some cases, S/D contact(s)114may abut a portion of masking material140. Similar to other embodiments discussed herein, structure100optionally may include several first gate structure106and/or second gate structure108despite masking material140being included.

FIG.8depicts a further embodiment of structure100in which first gate structure(s)106optionally may include a plurality of graded protrusions106cextending horizontally outward from gate body110. Graded protrusions106cmay have a similar or identical composition to material(s) within gate body110of first gate structure106and/or other gate structure materials discussed herein. Graded protrusions106cmay have a changing width with respect to their lengthwise position adjacent gate body110of first gate structure106. For instance, graded protrusion(s)106cmay be widest at a lengthwise end of semiconductor region104(e.g., to cover corner segment124(FIG.2)) and may be smallest at a position nearest to S/D contact(s)114(e.g., to avoid electrical contact between S/D contact(s)114and graded protrusions106c). Graded protrusions106care shown as a group of adjacent rectangular protrusions, but they may have any desired geometry. In further examples, graded protrusion(s)106cmay have a curvilinear sidewall over corner segment(s)124while also being located apart from S/D contact(s)114.

FIG.9depicts a further implementation of structure100in which masking material140is formed in other locations with various additional structures to assist in covering corner segment(s)124(FIG.2). In this case, first gate structure(s)106may include one or more gate straps142(e.g., two shown) extending in a widthwise direction over TI region(s)102and over portions of semiconductor region104. Gate straps142may interconnect two or more first gate structures106and may include the same and/or similar material(s) to gate body110of first gate structures106. Gate straps142may be differentiated from first gate structure(s)106solely by extending widthwise over TI region(s)102and semiconductor region104, instead of lengthwise. Masking material140may be over gate strap(s)142instead of gate body110of first gate structure(s)106to cover certain portions of corner segment(s)124, and/or second edge122(FIG.2) of semiconductor region104where desired. The masking material140intends to prevent electrical short between the second gate structure108and the gate strap142and the masking material140can be a “gate cut mask” in one implementation. First gate structure106, optionally, also may include a transition segment144between gate body110and gate strap142to increase coverage of first gate structure106over corner segment(s)124. Transition segment(s)144may include, e.g., curved sidewalls to cover portions of semiconductor region104without being in close proximity with S/D contact(s)114. Transition segment(s)144may arise as process-related corner rounding when they are part of the same fabrication step together with the first gate structure106. In all other respects, structure100(including semiconductor region104, S/D contact(s)114, second gate structure108) may be the same as, or similar to, other embodiments discussed herein.

FIG.10depicts yet another implementation of structure100capable of being combined with and/or implemented separately from other embodiments of structure100discussed herein. Second portion(s)106bof first gate structure106, even when rectangular in shape, may be oriented out of parallel or perpendicular alignment with edges120,122(FIG.2) of semiconductor region.FIG.10depicts second portion(s)106bas extending diagonally over semiconductor region104, e.g., to cover corner segment(s)124thereof without further modifying the shape of second portion(s)106b. Thus, second portion(s)106bmay have any desired shape regardless of how structure100is otherwise structured. That is, in addition to substantially rectangular shapes, second portion(s)106bmay have any desired shape as well as any desired orientation to cover corner segment(s)124of semiconductor region104.

According to further implementations, and as shown inFIG.11, first gate structure106may have a partially curvilinear shape over TI region(s)102and semiconductor region104for covering corner segment(s)124. Here, first gate structure106may have a substantially uniform width but may be shaped to extend over corner segment(s)124of semiconductor region(s)104to compensate for the absence of any protrusions and/or wider segments of gate body110of first gate structure106. First gate structure106thus may include one or more curvilinear segments106dover corner segment(s)124. Other portions of first gate structure106(whether curved or not) may cover first edge120(FIG.2) of semiconductor region104such that first gate structure106entirely covers first edge120and corner segment(s)124. Structure100otherwise may be similar to and/or combinable with other implementations of structure100described herein, notwithstanding the presence of curvilinear segments106d.

Embodiments of the disclosure provide various technical and commercial advantages, examples of which are discussed herein. Structure100, however implemented, may laterally constrain any raised source or drain materials to be grown on semiconductor region(s)104. Among other benefits, this constraining of overlying semiconductor material may improve the shape of any boundaries for silicidation growth above corner segment(s)124of semiconductor region104. Furthermore, as discussed herein, first gate structure(s)106may prevent punch-through of S/D contact(s)114into underlying substrate material due to the covering of relatively weak material in corner segment(s)124. In addition, embodiments of structure100may vary the width of first gate structure106and/or include masking material140to prevent electrical shorts from arising between S/D contact(s)114and nearby portions of first gate structure106. The varying shapes and/or implementations of first gate structure106and/or other portions of structure100allow for high customization and/or a variety of implementation options to suit many devices and operating circumstances.