Electroless plating of porous and non-porous nickel layers, and gold layer in semiconductor device

A method for maintaining non-porous nickel layer at a nickel/passivation interface of a semiconductor device in a nickel/gold electroless plating process. The method can include sequentially electroless plating of each of the nickel layer and gold layer on the device layer to pre-determined thicknesses to prevent corrosion of the nickel layer from reaching the device layer during the electroless gold plating process.

DESCRIPTION

Embodiments of this invention relate generally to semiconductor fabrication and more particularly, to a structure for maintaining mechanical integrity of layer interfaces and junctions at completion of an electroless plating process.

Electroless plating is a method for plating a nickel (Ni) layer and a gold (Au) layer over metal pads (e.g. aluminum pads) of a semiconductor chip. Electroless plating is advantageous over electrolytic plating because the equipment for electroless plating is less expensive and the method consumes less nickel and gold material.

When Ni/Au electroless plating is used in plating semiconductor devices, it has been found by the inventor that the Ni reacts with the Au and creates regions of “corrosion” at critical interfaces and junctures of the device layers. This corrosion affects a bond between the Ni and underlying passivation (PO) layer in particular. Corrosion can be in the form of a very porous Ni layer along the Ni/PO interface, voids, and regions where the Ni layer is very rich in Au. Because of the corrosion, moisture and ionic contaminants can migrate toward the active area of the IC, and cause device failure.

Accordingly, a need exists to maintain the integrity of the nickel layer at device layer interfaces and junctions, even upon completion of an electroless plating process. As further explained in the exemplary embodiments herein, the integrity can be maintained by preserving a layer of non-porous nickel at the Ni/PO interface.

BRIEF SUMMARY

These and other problems are generally solved or circumvented, and technical advantages are generally achieved, by preferred exemplary embodiments herein which disclose methods for maintaining a mechanical bond between layer interfaces and junctions of a semiconductor device upon completion of an electroless plating process.

Exemplary embodiments can include determining a thickness of a gold layer, then determining a thickness of nickel needed to have a non-porous layer of nickel remaining at the Ni/PO interface and Ni/PO/Al junction upon completion of the gold plating process.

A further exemplary embodiment can include an underlying metal pad, a non-porous nickel layer at the junction of the Ni/PO/Al, a porous nickel layer over the non-porous nickel layer, a gold layer over the porous nickel, and a gold rich nickel region between the gold layer and the porous nickel region.

Additional embodiments of the disclosure will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the present disclosure. The embodiments of the disclosure will be realized and attained by means of the elements and combinations particularly pointed out in the appended claims.

DETAILED DESCRIPTION

In the following description, reference is made to the accompanying drawings that form a part thereof, and in which is shown by way of illustration specific exemplary embodiments which may be practiced. Wherever possible, the same reference numbers will be used throughout the drawings to refer to the same or like parts. These embodiments are described in sufficient detail to enable those skilled in the art to practice the embodiments and it is to be understood that other embodiments may be utilized and that changes may be made without departing from the scope of the invention. The following description is, therefore, merely exemplary.

As used herein, the term “ENIG” refers to electroless nickel immersion gold, and is a type of surface plating used for printed circuit boards. ENIG can include electroless nickel plating covered with a thin layer of immersion gold, which protects the nickel from oxidation.

According to embodiments, a mechanical integrity is maintained at the Ni/PO interface and the Ni/PO/Al junction with a layer of nonporous nickel, upon completion of the electroless plating process.

SEM micrographs, as shown inFIG. 1demonstrate the areas of corrosion in an exemplary semiconductor device100. InFIG. 1, a portion of the semiconductor device100is depicted and includes certain layers pertinent to the exemplary embodiments herein. Specifically, the device100can include a substrate110, a metal pad120on the substrate110, a passivation layer130on the substrate110and metal pad120, and a Ni/Au electroless plating layer150/160. An interface180can be seen between the nickel layer150and passivation layer130, and a junction190can be seen at a joint of the metal pad120, nickel150and passivation layer130.

The corrosion depicted inFIG. 1can be caused by a galvanic attack of gold on the nickel layer during a typical electroless process. Three regions of corrosion can be observed inFIG. 1, including: 1) an area where the galvanic attack (e.g. a hyperactive electrochemical reaction between the gold and the nickel) produced a very porous nickel layer; 2) a region where the nickel was completely dissolved creating a void; and 3) a region where an EDX detected a nickel layer very rich in gold.

It is applicant's discovery that the bond between the nickel and the passivation layer130(passivating oxide (PO)) is mechanical and not chemical. This mechanical bond is weakened when nickel becomes porous, the porosity enabling gold atoms to diffuse into the nickel layer and replace nickel atoms by substitution during the gold plating reaction. The depletion of nickel near the gold layer causes nickel atoms to diffuse towards the gold layer and thus create voids in the underlying nickel layer150. The voids allow foreign chemical agents such as moisture and ionic contaminants to penetrate, migrate through the openings, and reach an active area of the integrated circuit to damage the device, and ultimately cause device failure. In other words, if the integrity of the nickel layer at the Ni/PO interface or Ni/PO/Al junction is compromised, contaminant ions can reach the device to cause corrosion of the metal pad, and device leakages if the ions reach the active area of the device.

FIG. 2illustrates a semiconductor device200, according to the present disclosure. It should be readily apparent to those skilled in the art thatFIG. 2is exemplary and that other components can be added or existing components can be removed or modified without departing from the scope of the exemplary embodiments.

The semiconductor device200can include a substrate210, a metal contact pad220formed on the substrate210, a passivation layer230formed over the substrate210and a portion of the metal contact pad220, and an electroless plated layer of Ni250and Au260formed over the metal pad220and passivation layer230. The electroless plated Ni layer250can include a first non-porous Ni layer250A, a porous Ni layer270, and a second non-porous Ni layer250B. The porous Ni layer270is sandwiched between non-porous Ni layers250A and250B. The second non-porous nickel layer250B includes that portion of an initial electroless nickel deposition not attacked by the gold layer260during electroless plating of the gold layer260in the ENIG process.

The substrate210can include a silicon substrate as known in the art. The metal contact pad220can include, for example copper (Cu) or aluminum (Al). For purposes of the following, and without intending it to be limiting, the metal contact pad220will be referred to as the Al pad. The passivation layer230can include a passivating oxide layer as known in the art.

As described, the electroplated Ni layer250of the Ni/Au electroless plating can include the first non-porous nickel layer250A and porous nickel layer270over the first non-porous nickel layer250A. The first non-porous nickel layer250A can be at both a Ni/PO interface280and a Ni/PO/Al junction290. The first and second non-porous Ni layers250A and250B remain upon completion of the electroless plating process because of a predetermined thickness of the electroless plated Ni layer250because of a predetermined thickness of the Au layer. The gold layer260is over the porous nickel layer250, and an Au rich nickel region275can occur between the Au layer260and the porous nickel region270as a result of the electroless plating process, however, the first non-porous Ni layer250A protects the passivation layer230from being directly affected by the Au rich nickel region275. It will be appreciated that although the first and second non-porous nickel layers250A,250B and porous nickel layer270are referred to as “layers”, it is intended that these layers can also be characterized as regions of the electroless nickel250because plating and the interaction of the gold layer with the nickel does not necessarily result in a uniformity that will result in layers per se.

As depicted inFIG. 2, the electroless nickel layer250can be of a thickness to maintain a mechanical integrity of the device200at the Ni/PO interface280and the Ni/PO/Al junction290. As also depicted inFIG. 2, the electroless nickel layer250can be of a thickness sufficient to achieve a predetermined thickness of the Au layer260without a thickness of the porous Ni layer270reaching the passivation layer230, the metal pad220, or an active surface of the semiconductor device200.

FIG. 3Aillustrates a flow diagram300of one embodiment of a process for making semiconductor devices according to the present disclosure. It should be readily apparent to those of ordinary skill in the art that the flow diagram300depicted inFIG. 3represents a generalized schematic illustration and that other steps can be added or existing steps can be removed or modified.

As shown in block310ofFIG. 3A, the process begins by determining how thick the Au layer will be for a resulting structure (e.g. for wire-bonding and soldering). As shown in block320, the process includes then determining an Au plating rate and plating time to reach the determined Au thickness. As shown in block330, the process includes then determining how fast a front edge of the porous nickel layer progresses during the Au plating step. As shown in block340, the process continues by determining a thickness of Ni layer under the Au layer necessary to keep the porous (portion, i.e. spongy Ni layer) nickel layer from reaching the passivation layer and/or metal pad. Following the determination, and at block350, a semiconductor chip can be processed by plating a metal pad with a nickel layer and plating a gold layer over the nickel layer. The process can conclude at block360.

In the method, the non-porous nickel layer forms a mechanical bond with the passivation layer. The method maintains a layer of non-porous nickel at an interface of the non-porous nickel layer/passivation layer, and at a junction of the non-porous nickel layer, passivation layer, and metal contact pad. The metal contact pad can be configured of aluminum (Al). Further, the electroless plating process can be an electroless nickel immersion gold (ENIG) process.

An alternative flow is illustrated inFIG. 3Bat blocks370,380and390, whereby the Ni layer thickness is held to a fixed value and the Au thickness or plating time is optimized such that the porous Ni edge being formed remains at a reasonable distance from the metal pad/PO interface.

Advantages of the exemplary electroless plating process and resulting structure can include a cost advantage and simplicity over electrolytic plating. Another advantage is reliability at the structure in which the porous nickel region touches the metal (e.g. Al, Cu) pad. The exemplary embodiments are such that the resulting semiconductor devices are more robust in the presence of humidity and ionic contamination because the mechanical integrity at the interface between the passivation layer and the electroless Ni/Au prevents the humidity and the ions from reaching the active area of the devices.

While the invention has been described with reference to the exemplary embodiments thereof, those skilled in the art will be able to make various modifications to the described embodiments without departing from the true spirit and scope. The terms and descriptions used herein are set forth by way of illustration and are not meant as limitations. In particular, although the method has been described by examples, the steps of the method may be performed in a different order than illustrated or simultaneously. Furthermore, to the extent that the terms “including”, “includes”, “having”, “has”, “with”, or variants thereof are used in either the detailed description and the claims, such terms are intended to be inclusive in a manner similar to the term “comprising”. As used herein, the term “one or more of” with respect to a listing of items such as, for example, A and B, means A alone, B alone, or A and B.