Embedded chip package

An electronic assembly is disclosed. One embodiment includes at least one semiconductor chip and a package structure embedding the semiconductor chip. The package structure includes at least one conducting line extending into an area of the package structure outside of the outline of the chip. The electronic assembly further includes a substrate embedding the package structure.

BACKGROUND

The invention relates to embedding electronic components into a substrate.

Embedding active devices into a substrate has been realized as a promising technology for applications in which size, thickness and weight of electronic devices are sought to be minimized. Such requirements are often encountered in portable applications such as cell-phones, laptop PCs, palms, PDUs (Personal Digital Assistant) etc.

Recently, chips have been directly embedded into build-up layers of SBU (Sequential Build-up) laminate substrates. This concept is known as Chip in Polymer (CiP) technology. In this approach, chips are mounted e.g., on a core of the substrate and embedded inside a film of dielectric layer.

In another embodiment, a cavity is formed in a substrate and the chip is placed inside this cavity. The chip is then bonded by conventional bonding techniques.

DETAILED DESCRIPTION

Fan-out type packages are packages embedding a chip, wherein at least some of the package pads and/or conducting lines connecting the chip to the package pads are located laterally outside of the outline of the chip or do at least intersect the outline of the chip. Thus, in fan-out type packages, a peripherally outer part of the package of the chip is typically (additionally) used for electrically bonding the package to external applications (e.g., application boards etc.). This outer part of the package encompassing the chip effectively enlarges the contact area of the package in relation to the footprint of the chip, thus leading to relaxed constrains in view of package pad size and pitch with regard to later processing, e.g., second level assembly.

Embodiments of fan-out type packages described in the following may be of various design. The fan-out area around the chip may be provided by a surface of a mold compound used for encapsulating the chip. Another possibility is to mount the chip on a substrate (or leadframe) chip carrier having lateral dimensions larger than the chip dimensions and to exploit a peripheral region of the laminate substrate chip carrier as a fan-out area.

Embodiments of the package may use various types of chips, among them logic integrated circuits, analog integrated circuits, mixed signal integrated circuits, sensor circuits, MEMS (Micro-Electro-Mechanical Systems), power integrated circuits, chips with integrated passives, passives etc.

Embodiments of the substrate may include substrates of different type and configuration, in particular PCBs (Printed Circuit Boards), SBU (Sequential Build-Up) laminate substrates, ceramic substrates, leadframes and mold compounds, e.g., MIDs (Molded Interconnect Devices).

Embodiments for bonding the package pads to the wiring of the substrate may include thin-film technology, soldering, welding, diffusion or bond wire technologies.

FIG. 1depicts a cross-sectional view of a first embodiment of the invention. Same reference signs designate like parts in the following drawings. A fan-out type package1is embedded in a substrate2. The fan-out type package1contains a chip3, the outline of which is indicated by dashed line4.

A fan-out area5of the package1is delimited by the outline4of the chip3and the periphery of the fan-out type package1. Pads6of the fan-out type package1are located at least partially within the fan-out area5. Additional pads (not illustrated) may be distributed over a footprint area7of the fan-out type package1.

The package pads6are bonded to chip pads (not illustrated) on the chip3by means (not illustrated) which will be exemplified further below. Virtually all known bonding techniques may be utilized.

Due to the increased space around chip3provided by the fan-out area5for the pads6(i.e. the interconnect of the package1), fan-out packages1allow to increase the number of package pads6and/or the pitch of package pads6compared to fan-in packages or bare chip solutions. As a consequence, embedding fan-out type packages1in a substrate2is beneficial in view of several aspects:

A fan-out type package1provides a good protection to the chip3against outside damages. Especially, it is possible to protect all surfaces of the chip3, if the package1completely encapsulates chip3. Typically, at least the lateral edge of chip3may be protected by the package1by the part of the package1which creates the fan-out area5.

Semiconductor material is expensive resulting in that the chip size is permanently shrinking. Fan-out type packaging provides a low cost possibility to maintain package interconnect dimensions and geometry through the shrinkage of chip size. Consequently, the wiring provided within or on the substrate must not be modified when new technologies provide for smaller chips3.

Fan-out type packages might have a high level test coverage to meet the “known good die/device” aspects.

As the size and/or pitch of the package pads6may be relatively large in fan-out type packages1, geometric tolerances are less stringent for fan-out solutions than for fan-in solutions in any bonding process applied for connecting the package pads6to substrate wiring (not illustrated) or external applications. Thus, the overall yield for a package-in-substrate structure is significantly enhanced when using fan-out type packages instead of fan-in structures.

Fan-out type packages facilitate repair approaches compared to the case in which bare chips or fan-in structures are embedded in a substrate.

Fan-out type packages allow for an improved shielding of the chip3, because more space is provided on or in the package structure for applying a metallization for shielding especially in the peripheral region of the chip3.

FIG. 2depicts a fan-out type package1embedded in a substrate20. Substrate20is an SBU laminate substrate. SBU laminate substrate20includes a core21provided by one or more (here: four) core layers21a,21b,21c,21dand build-up layers22,23at both sides of the core21.

Each core layer21a,21b,21c,21dmay be composed of glass-fiber-reinforced epoxy resin. Core layers21a,21b,21c,21dmade of a fluoropolymer material such as e.g., polytetrafluoroethylene, aramid fibers, or carbon fibers may also be used. Metal layers24are arranged between the core layers21a,21b,21c,21d. By way of example, if carbon fibers are used, core layers21a,21b,21c,21dand metal layers24may form a copper-carbon fiber compound material. Core vias25are arranged to penetrate the core layers21a,21b,21c,21dand are used to electrically connect specific metal layers24of the multi-layer core21. To this end, the core via25is internally coated by a metal jacket26. As it is apparent for a person skilled in the art, the design of the core21is similar to the design of a conventional PCB and may be formed by conventional laminated PCB processing techniques. Thus, core vias25are typically formed by mechanical drilling and extend through the entire core21. Core thickness may be in the range of several hundreds μm and the via size may be in the range of one or multiple hundreds of μm.

The fan-out type package1may be mounted on the uppermost core layer21a. Here it is embedded in build-up layer22aand covered by build-up layers22b,22c. Build-up layers22a,22b,22cmay be a dielectric, e.g., silica-filled epoxies plated by metal layers27. Metallized vias28interconnect between adjacent metal layers27.

Typically, the build-up layers22, metal layers27and vias28are generated by thin-film processing techniques. For example, vias28which are typically blind and buried may be formed by laser drilling and are tapered, having different lower and upper diameters. Other techniques like photo-structuring might also be used. Metallization of vias28may be formed by sputtering or plating a metal over the entire surface of the underlying build-up layer22a,22b,22c. Then, a photoresist material is applied and patterned. The desired metal pattern is obtained by etching the unprotected metal layer27. Other techniques, such as printing, ink jetting or laser direct structuring a conductive material or catalytic starter may also be used. Multiple build-up layers22a,22b,22c, corresponding vias28and metal layers27are formed by applying an addition dielectric film and repeating the via formation and metallization processes. Passive components (not illustrated) such as capacitors, resistors and inductors may be embedded during the layer build-up process.

The lower build-up layers23are formed using a similar step-wise building process.

Typically, most of the wiring capability of the SBU laminate substrate20occurs in the build-up layers22,23. To this end, the trace and space dimensions in the build-up layers22,23are significantly finer than those in the core21. The thickness of build-up layers, e.g.,22b,22c, may be in the range of about 10 μm and the diameter of via28may be some tens of μm. Layers22aand22bmay be combined to one layer and may be thicker than the typical 10 μm at least on the package corners to incorporate the package. In SBU laminate substrate20, often signal routing is performed within the build-up layers22,23whereas power distribution is accomplished by the core21. Further, the core21provides for an adequate rigidity of the SBU laminate substrate20.

As illustrated inFIG. 2, the fan-out type package1may be attached directly on the uppermost core layer21aand/or embedded within a single build-up layer22a. However, the fan-out type package1may also be embedded in multiple build-up layers22a,22b,22c(i.e. the height of the fan-out type package1may correspond to the height of several build-up layers22a,22b,22c) or may be disposed on a build-up layer22a,22b,22crather than directly on the uppermost core layer21a. Further, it is possible that the fan-out type package1is embedded into the core21, i.e. encapsulated in one or more core layers21a,21b,21c,21d, rather than in one or more of the build-up layers22a,22b22c.

FIG. 3illustrates an embodiment of a first fan-out type package101. The fan-out type package101includes a chip103embedded in a matrix of mold compound108. More specifically, the backside of the chip103and its edges are covered with mold compound108, with the fan-out area of the mold compound108being denoted by the reference sign105. The mold compound108may be a duroplastic resin, a thermosetting plastic material, a thermoplastic resin or a composite compound. The active surface109of the chip103lies flush with the upper surface110of the fan-out area105of the mold compound108, and a first dielectric layer111a, a metal redistribution layer112and a second dielectric layer111bextend over the plane composed of the active surface109of the chip103and the upper surface110of the mold compound108, compareFIG. 4. The first and second dielectric layers111a,111band the metal redistribution layer112may be manufactured in a thin-film process onto the plane composed of the active surface109of the chip103and the upper surface110of the fan-out area105of the mold compound108. The fabrication of the first and second dielectric layers111a,111bas well as the metal redistribution layer112and the generation of via113may be accomplished by applying thin-film technology processes as explained in conjunction with the manufacturing of the build-up layers22,23depicted inFIG. 2. Thus, via113may be formed photo-lithographically, jetted or by laser drilling and the redistribution layer112may be structured by photo-lithographic processes. Higher number of layers might be applied when needed.

The second, upper dielectric layer111bmay serve as a solder stop when solder balls114are optionally applied to exposed contact regions115of the metal redistribution layer112. Instead of solder balls114, it is also possible that solder bumps of less height showing a smoother curved, lenticular surface or flat metal contact posts (which might be applied by a non-galvanic plating process) are deposited on the exposed contact region115of the metal redistribution layer112.

Fan-out type package101may be fabricated in an embedded device technology based on a molded reconfigured wafer. This embedded device wafer level packaging (eWLP) technology is developed from standard wafer level packaging (WLP) technology. Standard WLP technology is defined such that virtually all technology processes are performed on wafer level. More specifically, in standard WLP, dielectric and metal layers such as layers111a,111band112are deposited and processed on the active surface of the wafer before the wafer is cut into single chips. Consequently, standard WLPs are always fan-in solutions. In contrast to WLP technology, in eWLP technology the front-end processed and probed wafer is first singulated to obtain single chips. The chips103are then placed onto a support in a spaced-apart relationship. In the next process, the spaced-apart chips103on the support are molded, e.g., by using a liquid mold compound that is dispensed over the chips103on the support. Thereby, the gaps between the placed chips are filled with liquid mold compound. After curing the mold compound, the support is removed to obtain the reconfigured wafer, in which the chips are distributed within the mold compound in a regular, array-like fashion. This reconfigured wafer is then processed according to standard WLP technology, i.e. the dielectric layers111a,111band the metal redistribution layer112are applied typically by using thin-film processes. Moreover, appropriate connecting elements such as solder balls114, solder bumps or metal elements may optionally be applied on wafer level. Only after finishing the fan-out package interconnect, the molded reconfigured wafer is singularized into single packages such as, for instance, illustrated inFIG. 3.

FIG. 5illustrates a second fan-out type package201. The fan-out type package201distinguishes from the fan-out type package101mainly in that the package201encapsulate a chip203and a further electronic component215(more than one further component could be applied, but by way of simplification only one is depicted). The further electronic component215may be a passive element, e.g., a capacitor, a resistor or an impedance, or may be another integrated circuit. The further component215is interconnected to the chip203via an interconnect structure including first and second (for many practical cases only one dielectric will be sufficient) dielectric layers211a,211b, vias213and a structured metal redistribution layer212similar to layers111a,111b, vias113and the structured metal redistribution layer112as explained above. The second package201represents an SiP (System in Package), as it includes more than one electronic components encapsulated by the package201. For fabrication, eWLP technology may be applied in the same way as described in conjunction withFIGS. 3,4.

FIG. 6illustrates a third fan-out type package301similar to201which likewise represents an SiP. More specifically, fan-out type package301includes a chip303, a further electronic component315, first and second dielectric layers311a,311b, vias313and a metal redistribution layer312in accordance with the description of parts203,215,211a,211b,213and212, respectively, as explained above in conjunction withFIG. 5. In contrast to the fan-out type package201, fan-out type package301is equipped with a conductive layer316at the backside of chip303and/or electronic component315(which may likewise be an integrated circuit). The layer316may also be a dissipative layer having a higher specific electrical resistance than conductive layers typically used for signal distribution. The conductive layer316may be structured (not illustrated inFIG. 6). It could serve for different functions such as providing an interconnect to chip303and/or electronic component315, providing a shielding against electromagnetic interference to the fan-out type package301and providing for an improved thermal transfer of heat out of the fan-out type package301. The conductive layer316may be of a conductive polymer (especially if it is intended to provide for shielding) or may be made of metal. There might also be a dielectric layer and/or multilayers between the components303,315. Fabrication of the fan-out type package301may be again performed using eWLP technology as described above. It is to be noted that packages101,201may likewise be equipped with such conductive layer at the backside and/or at the edge of the package101,102.

Further, in all fan-out type packages101,201,301, the upper dielectric layer111b,211b,311bmay be omitted. That is because if fan-out type packages101,201,301are embedded, e.g., in an SBU laminate substrate20as illustrated inFIG. 2, the first build-up layer22bcovering the fan-out type package101,201,301may serve as a solder stop, i.e. may replace the upper dielectric layer111b,211b,311b.

Further, it is to be noted that the fan-out type packages101,201,301shall be as thin as possible in order to facilitate the accommodation in the substrate. Thus, in all embodiments described herein, the chips may be thinned e.g., by mechanical grinding or chemical etching the backside of the chip103,203,303.

Nevertheless, fan-out type packages with stacked components are feasible.FIG. 7illustrates a fan-out type package401which is designed and may be fabricated substantially in line with the descriptions ofFIGS. 3 to 6. Briefly, parts denoted by reference signs403,415,411a,411b,412and413correspond to parts illustrated inFIG. 6denoted by reference signs303,315,311a,311b,312and313. In contrast to the example of the fan-out type package301, the fan-out type package401includes a third electronic component416which is located above the chip403and the second electronic component415. Similar to the second electronic component415, the third electronic component416may be a passive element (resistor, inductor, capacitance) or an integrated circuit. The third electronic component416in the example illustrated is disposed on the first dielectric layer411aand embedded in an intermediate dielectric layer417extending in between the first and second dielectric layers411a,411b. Similar to the fan-out type packages101,201,301, the backside of the package401may be made of continuous mold compound (cf.FIGS. 3,4,5), a conductive layer316(cf.FIG. 6) or—as depicted in FIG.7—may include one or more areas of bare semiconductor material.

FIGS. 8 and 9illustrate fan-out type packages501,601which are basically different to the fan-out type packages exemplified inFIGS. 3 to 7. Packages501,601use a laminate substrate508,608as a carrier for chip503,603. The lateral dimensions of the laminate substrate chip carrier508,608in relation to the (lateral) outline504,604of the chip503,603define the available fan-out area505,605provided by the packages501,601. The laminate substrate chip carrier508,608is known as “interposer” in the art. In the depicted example it includes a core dielectric material509,609metallized on both sides by structured metal layers510,610. Thin dielectric layers511,611are applied to the structured metal layers510,610, e.g., to serve as a solder stop. The laminate substrate chip carrier508,608is equipped with metallized vias in order to interconnect the structured metal layers510,610on both sides of the core509,609. The chip503inFIG. 8is flip-chip bonded to the laminate substrate chip carrier508by flip-chip solder bumps512, whereas chip603inFIG. 9is wire-bonded to the laminate substrate chip carrier608by bond wires612. InFIG. 8an underfill material513may be introduced between the chip503and the laminate substrate chip carrier508. InFIG. 9the chip603is fixed to the chip carrier608with the die attach material613. Solder balls514,614are contacted to the structured metal layer511,611opposite to the chip503,603. Further, a mold compound520,620is provided over the laminate substrate chip carrier508,608and encapsulates the chip503,603along with the bonding elements512,612. Packages as illustrated inFIGS. 8 and 9are known as BGAs (Ball Grid Arrays). Another package group in this area which could be used is the VQFN (Very Thin Quad Flat), which is not depicted here.

Fan-out type mold compound packages101,201,301,401and fan-out type BGA packages501,601are integrated in e.g., substrates2,20as illustrated inFIGS. 1,2with reference to fan-out type package1. In other words, any description relating to the integration of fan-out type package1in substrate2or20applies to eWLP technology packages101,201,301,401as well as laminate substrate chip carrier or any interposer based fan-out type packages like501,601or/and VQFNs.

Further, substrate2may itself be a mold compound structure. An example for a process of integrating a fan-out type package1into a mold compound substrate is illustrated inFIGS. 10 to 14.

InFIG. 10, a fan-out type package1which may be designed in accordance with any of the previously described fan-out type packages1,101,201,301,401,501,601is mounted on a mounting platform1000. The mounting platform1000may be a plate made of a dielectric material, for instance an epoxy thermoset, thermoplastic material or a glass-fiber enforced epoxy. It may also be a PCB. In this case, a structured metal (e.g., copper) layer, which is not depicted inFIGS. 10 to 14, is provided on the upper surface of the dielectric mounting platform1000.

The fan-out type package1is mounted on the mounting platform1000. If the backside of the fan-out type package1is made of mold resin, the chip3is insulated from any metal layer optionally provided at the upper surface of the mounting platform1000.

In a next process, the fan-out type package1is covered by a mold compound1001. The mold compound1001is a dielectric material and may be identical to the material of the mold compound108used for encapsulating the chips103,203,303,403inFIGS. 3 to 7. According toFIG. 12, the substrate mold compound1001completely covers and extends over the top surface of the fan-out type package1.

According toFIG. 13, in order to contact the fan-out type package1, through-holes1002are produced in the substrate mold compound1001in a region above the fan-out type package1. The through-holes1002open to pads6of the fan-out type package1. As already mentioned before, pads6of the fan-out type package1are interconnected to pads (not illustrated) on chip3. As illustrated inFIG. 14, pads6of the fan-out type package1are connected to external applications by chemical or galvanic deposition of a metal layer1003on the mold compound1001, which extends through the through-holes1002down to the package pads6. The through-holes1002may be generated by laser drilling or other suitable processes. Structuring of the metal layer1003may be accomplished by using thin-film techniques such as lithographic processes. Further, e.g., using thin-film techniques, it is possible that a plurality of polymer layers and metal layers are deposited alternately over the substrate mold compound1001to provide a substrate wiring which may be the same as the top and/or bottom wiring22,23of an SBU laminate substrate20illustrated inFIG. 2.

The substrate mold compound1001may be applied by various techniques, among them laminating processes, spin-coating or dispensing of a liquid dielectric material, e.g., based on liquid epoxy.FIGS. 15 to 18illustrate a compression molding process which might be used for encapsulating fan-out type packages1into a substrate2. Besides compression molding, transfer molding or other molding techniques may be used for practicing the resin encapsulation process ofFIG. 12.

In compression molding, a fast melting or liquid mold compound1001is required, which is supplied substantially in the middle of the mounting platform1000carrying a number of fan-out type packages1. The mounting platform1000, the fan-out type packages1and dispensed mold compound1001is then transferred between two mold halves2001,2002of a molding tool. In a compression phase depicted inFIG. 16, the molding halves2001,2002are closed under the application of heat. By closing the molding halves2001,2002, the liquid mold compound1001is distributed within the cavity defined by the molding halves2001,2002. In a subsequent curing phase, the mold compound1001is cured. Then, a substrate composed of the mounting platform1000and mold compound1001encapsulating fan-out type packages1as depicted inFIG. 18and represented inFIG. 12for the case of a single embedded fan-out type package1is taken out of the mold tool. Analog to theFIGS. 4 to 7there could be integrated several different device packages1and/or different chips/passives combined into “new” eWLP.

As previously mentioned, the molding of chip3in a package1as depicted inFIGS. 3 to 7may be accomplished equally by the process of compression molding. Thus, mounting platform1000, mold compound substrate1001and mold compound fan-out type package1could be termed a (fan-out type) mold compound package-in-mold compound substrate structure. Analog to theFIGS. 4 to 7there could be integrated several different device packages1and/or different chips/passives combined into “new” eWLP.

Further, it is to be noted that fan-out type packages1may be embedded in conventional PCB single layer or multi-layer substrates (where each layer is made e.g., of glass-fiber-reinforced epoxy resin coated by a metal layer) or in ceramic substrates. In these cases, it might be necessary to form a cavity in the substrate and then to insert the fan-out type package1into the cavity.FIG. 19illustrates a substrate3000in which a recess3001has been machined. The recess3001is partially filled by a dielectric material3002, e.g., epoxy, and a fan-out type package1is inserted into the recess3001. The fan-out type package1may be interconnected by thin-film techniques using build-up layers3004,3005and vias3006as described above in connection withFIG. 2. It is to be noted that recessed substrate3000is not limited to a PCB or ceramic substrate but may be of alternate kind, including mold compound or an SBU laminate substrate. If the package1is thin enough, it is obvious that no recess is needed and such packages may be embedded into the layers22depicted inFIG. 2.