Method and apparatus for an output buffer with dynamic impedance control

A method and apparatus for an output buffer with dynamic impedance control have been disclosed.

FIELD OF THE INVENTION

The present invention pertains to output buffers. More particularly, the present invention relates to a method and apparatus for an output buffer with dynamic impedance control.

BACKGROUND OF THE INVENTION

Output buffers are an integral part of electronics. Their use is wide and diverse. They are used to drive a variety of other devices both active and passive, for example, logic, microprocessors, bus clocks, resistors, capacitors, backplanes, etc. When driving such a variety of devices and depending upon the load presented to the output buffer it is possible to have effects which may not be wanted. For example, ringing, overshoot, undershoot, EMI (electromagnetic interference), etc. This presents a problem.

For example,FIG. 1illustrates one current approach100having a dynamic output control. One of skill in the art will recognize thatFIG. 1uses a level-detect circuit (the feedback inverters connected at the output) to determine when the output has passed a fixed threshold. Once this threshold is passed, the output impedance is increased to provide more effective signal termination, thereby reducing signal over/undershoot. Such an approach is discussed by Ten Eyck in U.S. Pat. No. 6,137,322. However, the approach as illustrated inFIG. 1has a fixed threshold which limits the range of loads the output can effectively drive. This may present a problem.

FIG. 2illustrates another current approach200having an output control to reduce switching noise. One of skill in the art will recognize thatFIG. 2provides a more gradual feedback mechanism than that illustrated inFIG. 1. Such an approach is discussed by Davis in U.S. Pat. No. 5,036,222. However, the implementation inFIG. 2uses positive feedback to increase drive strength during switching. This reduces switching-induced noise, but does not aim to reduce signal over/undershoot. This may present a problem.

FIG. 3illustrates another current approach300having a current controlled switch. One of skill in the art will recognize thatFIG. 3uses a cascoded driver stage. Such an approach is discussed by Vajdic et al. in U.S. Pat. No. 4,791,326. However, in the implementation illustrated inFIG. 3, the output drive is a fixed current and there is no feedback from the output. This may present a problem.

DETAILED DESCRIPTION

The invention, as exemplified in various embodiments, illustrates how dynamic impedance control may be achieved. In one embodiment of the invention, an output buffer implements a dynamic impedance control to limit overshoot and undershoot when driving unterminated loads. In one embodiment of the invention, the impedance control is implemented with cascoded output drivers.

FIG. 4illustrates one embodiment of the invention used in an output buffer400. Here, in a simple form of the invention, the gate closest to the output (at transistor406, and416) is switched with the inverse data (403), and the cascoded gate (at transistor408, and418) which controls impedance is connected to the output via a resistive element (shown as transmission gates (410, and420) in the schematic); thus the impedance-control device (transistor408, and418) is gradually switched ‘off’ as the output (422) swings towards its final value.

FIG. 4is now discussed in detail.401represents a data input (DATA_IN) which is communicated to inverter402which drives403.403is connected to the gate of P channel type transistors (PMOS)404, and406.403is also connected to the gate of N channel type transistors (NMOS)414, and416.451represents a positive potential source with respect to453. For convenience in discussion,451may be referred to as Vdd and453as GND. Vdd is connected to the source of P channel type transistors404, and408. GND is connected to the source of N channel type transistors414, and418. Vdd and GND are also connected to transmission gates410, and420. Output422(OUT) is connected to the drain of P channel type transistors404, and406. Output422(OUT) is also connected to the drain of N channel type transistors414, and416. Output422(OUT) is also connected to transmission gates410, and420. The gate of P channel type transistor408is connected via411to transmission gate410. The gate of N channel type transistor418is connected via421to transmission gate420. The drain of P channel type transistor408is connected to the source of P channel type transistor406. The drain of N channel type transistor418is connected to the source of N channel type transistor416.

One of skill in the art will appreciate thatFIG. 4illustrates an embodiment of the invention which uses a negative feedback mechanism to minimize under/overshoot, for example, on unterminated signal lines. The negative feedback is implemented by using cascode output drivers: one gate is controlled by the data switching signal, the other is connected (via a resistive element such as a transmission gate) to the output.

FIG. 4illustrates the use of cascoded output stages for dynamic output control.FIG. 4also illustrates direct feedback of the output back to the driver stage (no intermediate switching stages) between, for example, an output pad and driver control.

FIG. 4also illustrates a simple feedback mechanism which may provide a high level of adaptability to different output loads. One of skill in the art will appreciate that the use of a cascoded output keeps output capacitance low. Additionally, the use of cascoded outputs does not need extra driver stages that subsequently must be ‘turned off’ (like, for example, inFIG. 1).

In one embodiment of the invention, ratioing of the fixed (‘DC’) driver to the impedance-controlled driver, or varying the resistance of the feedback path may change the driver behavior. For example, inFIG. 4transistors404, and414may be considered the ‘DC’ driver stage and transistors406,408,416, and418the impedance controlled driver. The feedback may be considered the transmission gates410, and420. For example, in one embodiment of the invention, by changing the device sizes associated with these transistors and transmission gates, the output drive capability as well as the output drive characteristics (AC and DC) may be varied.

In one embodiment of the invention, the feedback path transmission gate (as exemplified inFIG. 4at410and420) may be sized such that its impedance closely matches that of the cascode driver (for example406and408, and416and418inFIG. 4). This matching may minimize output buffer performance variation across process corners. Alternatively, in one embodiment of the invention, the transmission gates (as illustrated inFIG. 4at410and420) may be replaced by a simple N or P pass gate, which then allows a Vt (MOS threshold) drop to develop across the feedback path and prevent cascode turn-off before the output has transitioned more than a Vt from Vdd or GND.

In one embodiment of the invention, the feedback path may be dynamically adjusted as well. That is the feedback path may start out as a relatively high-resistance, and be switched to a lower resistance as the output transitions, through, for example a fixed threshold. This would allow more drive at the beginning of the output transition, and a faster ‘turn-off’ towards the end of the output transition.

In yet another embodiment of the invention, a multi-stage turn-on may be used to reduce switching-induced noise.

The arrangement of the transistors408and406which are in ‘series’ is often referred to as a stacked transistor array. Two or more transistors may be stacked to create the array. Since transistors408and406are driving an output, in this case422, the array may be referred to as a stacked transistor output array (or stacked output transistor array). Note that transistors418and416are a stacked output transistor array.

FIG. 5illustrates one embodiment of the invention in flow chart form. At502an input signal is received. This signal may then be used, in one embodiment, to drive one or more transistors in a stacked output transistor array504. At506a sample of the output from the stacked output transistor array is taken, and a508based on this sample a signal is sent to one or more of the transistors in the stacked output transistor array.

FIG. 6illustrates one embodiment of the invention using N and P pass gate transistors for feedback elements. P transistor610and N transistor620provide feedback from the output (Out)622to the transistors608and618respectively. One of skill in the art will appreciate that by using N and P devices as pass elements, this allows a Vt (MOS threshold) drop to develop across the feedback path and prevents cascode turn-off before the output has transitioned more than a Vt from Vdd or GND. For example, when the output transitions from, for example, GND at 0 v to Vdd, the output must be greater than a PMOS threshold (VtPMOS) before transistor610will conduct and pull up node611. For example, when transitioning from Vdd to 0 V (GND), the output must be less than (Vdd−VtNMOS) before transistor620will conduct and pull down node621.

FIG. 6is now discussed in detail.601represents a data input (DATA_IN) which is communicated to inverter602which drives603.603is connected to the gate of P channel type transistors (PMOS)604, and606.603is also connected to the gate of N channel type transistors (NMOS)614, and616.651represents a positive potential source with respect to653. For convenience in discussion,651may be referred to as Vdd and653as GND. Vdd is connected to the source of P channel type transistors604, and608. GND is connected to the source of N channel type transistors614, and618. Vdd is also connected to the gate of N channel type transistor620. GND is also connected to the gate of P channel type transistor610. Output622(OUT) is connected to the drain of P channel type transistors604, and606. Output622(OUT) is also connected to the drain of N channel type transistors614, and616. Output622(OUT) is connected to the source of transistor610, and to the drain of transistor620. The drain of transistor610is connected via611to the gate of transistor608. The source of transistor620is connected via621to the gate of transistor618. The drain of P channel type transistor608is connected to the source of P channel type transistor606. The drain of N channel type transistor618is connected to the source of N channel type transistor616.

FIG. 7illustrates one embodiment of the invention where the feedback path may start as relatively high-resistance, and be switched to lower resistance as the output transitions through a threshold.FIG. 7does not show any parallel drivers such as transistors404and414inFIG. 4. Dneg, the input (which is inverted), may be considered a signal such as403inFIG. 4for understanding purposes.

InFIG. 7a resistive element764provides an initial ‘high-resistance’. InFIG. 7the output (OUT722) is monitored, in this embodiment by a simple CMOS device (XOR760) whose detection point threshold (assuming GND=0 V) would nominally be Vdd/2. As the output transitions through this threshold, a low-impedance path (‘TG’, transmission gate766) is turned on (which is in parallel with764), thereby increasing the negative feedback.

InFIG. 7, Dneg the input is connected to XOR760, and the gate of transistor706and716. The OUT722is connected to transistor706and716, one side of resistor764, one side of transmission gate766, and one input of XOR760. The output of XOR760is connected to inverter762and one control terminal of transmission gate766. The output of inverter762is connected to the other control terminal of transmission gate766. The other side of transmission gate766, the other terminal of resistor764, and the gates of transistors708and718are connected via711.751represents Vdd a more positive voltage than753which denotes GND.

One of skill in the art will appreciate that in alternative embodiments of the invention other implementations are possible. For example, the output rather than being monitored by a simple CMOS device could be more complicated, eg: comparing the output with a reference voltage using a differential input, etc. Additionally, other variations may include two separate feedback paths for pullup and pulldown and these could also have two different threshold levels.

FIG. 8illustrates one embodiment of the invention showing staged switching. InFIG. 8a multi-stage turn-on/turn-off is used to reduce switching-induced noise. The output is split into stages that are turned on at different times, generally delayed by fractions of the output rise/fall time. A mutli-stage approach may use two or more stages. By switching at different points in time, the current associated with switching is spread over a time interval as the multiple stages switch resulting in a lower peak current versus a single large stage switching at a single point in time.

InFIG. 8transistors808-1,806-1,816-1, and818-1may be considered a first output stage. Transistors808-2,806-2,816-2, and818-2may be considered a second output stage. Dneg the input803initially drives the first output stage. Signal803is then delayed by inverters862and864and the delayed signal865drives the second output stage.811represents P channel type transistor feedback control as illustrated in various embodiments of the present invention, and as discussed.821represents N channel type transistor feedback control as illustrated in various embodiments of the present invention, and as discussed.851denotes a positive supply voltage with respect to853. Out822is connected to each output stage (denoted here as the junction of806-1and816-1, and806-2and816-2).

FIG. 9illustrates one embodiment of the invention controlling the transistors which are directly tied to an output. In comparison withFIG. 4, the gate furthest from the output (at transistor906and916) is switched, and the cascaded gate (at transistor908and918) which controls impedance is connected to the output (922).

One of skill in the art will appreciate that this alternative embodiment results in greater negative feedback than that provided inFIG. 4, with faster cascode turn-off.

FIG. 9is now discussed in detail.901represents a data input (DATA_IN) which is communicated to inverter902which drives903.903is connected to the gate of P channel type transistors (PMOS)904, and906.903is also connected to the gate of N channel type transistors (NMOS)914, and916.951represents a positive potential source with respect to953. For convenience in discussion,951may be referred to as Vdd and953as GND. Vdd is connected to the source of P channel type transistors904, and906. GND is connected to the source of N channel type transistors914, and916. Vdd and GND are also connected to transmission gates910, and920. Output922(OUT) is connected to the drain of P channel type transistors904, and408. Output922(OUT) is also connected to the drain of N channel type transistors914, and918. Output422(OUT) is also connected to transmission gates910, and920. The gate of P channel type transistor908is connected via911to transmission gate910. The gate of N channel type transistor918is connected via921to transmission gate920. The drain of P channel type transistor906is connected to the source of P channel type transistor908. The drain of N channel type transistor916is connected to the source of N channel type transistor918.

One of skill in the art will appreciate that in alternative embodiments of the invention other implementations are possible. For example, the output rather than being monitored by a simple CMOS device could be more complicated, eg: comparing the output with a reference voltage using a differential input, etc. Additionally, other variations may include two separate feedback paths for pullup and pulldown and these could also have two different threshold levels.

FIG. 10A,FIG. 10B, andFIG. 10Cillustrate embodiments of the present invention. InFIG. 10Aat1002an output signal is generated. At1004the output signal that was generated is received. At1006a signal is fed back based on the received output signal to at least one transistor in a stacked output transistor array having two or more transistors. InFIG. 10Bat1012an output signal is generated. At1014the output signal that was generated is received. At1016a signal is fed back based on the received output signal to at least one transistor in a stacked output transistor array having two or more transistors after passing the output signal through a device selected from the group consisting of a resistor, a capacitor, a n type transistor, and a p type transistor. InFIG. 10Cat1022an output signal is generated. At1024the output signal that was generated is received. At1026a signal is fed back based on the received output signal to at least one transistor in a stacked output transistor array having two or more transistors after comparing the received output signal to a reference voltage and passing the output signal through a device selected from the group consisting of a resistor, a capacitor, a n type transistor, and a p type transistor.

Thus a method and apparatus for an output buffer with dynamic impedance control have been described.

For purposes of discussing and understanding the invention, it is to be understood that various terms are used by those knowledgeable in the art to describe techniques and approaches. Furthermore, in the description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the present invention. It will be evident, however, to one of skill in the art that the present invention may be practiced without these specific details. In some instances, well-known structures and devices are shown in block diagram form, rather than in detail, in order to avoid obscuring the present invention. These embodiments are described in sufficient detail to enable those of skill in the art to practice the invention, and it is to be understood that other embodiments may be utilized and that logical, mechanical, electrical, and other changes may be made without departing from the scope of the present invention.

It should be borne in mind, however, that all of these and similar terms are to be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities.

Further, any of the methods according to the present invention can be implemented in hard-wired circuitry, by programmable logic, or by any combination of hardware and software.

It is to be understood that various terms and techniques are used by those knowledgeable in the art to describe communications, protocols, applications, implementations, mechanisms, etc. One such technique is the description of an implementation of a technique in terms of an algorithm or mathematical expression. That is, while the technique may be, for example, implemented as executing code on a computer, the expression of that technique may be more aptly and succinctly conveyed and communicated as a formula, algorithm, or mathematical expression. Thus, one of skill in the art would recognize a block denoting A+B=C as an additive function whose implementation in hardware and/or software would take two inputs (A and B) and produce a summation output (C). Thus, the use of formula, algorithm, or mathematical expression as descriptions is to be understood as having a physical embodiment in at least hardware and/or software.

A machine-readable medium is understood to include any mechanism for storing or transmitting information in a form readable by a machine (e.g., a computer). For example, a machine-readable medium includes read only memory (ROM); random access memory (RAM); magnetic disk storage media; optical storage media; flash memory devices; electrical, optical, acoustical or other form of propagated signals (e.g., carrier waves, infrared signals, digital signals, etc.); etc.

As used in this description, “one embodiment” or “an embodiment” or similar phrases means that the feature(s) being described are included in at least one embodiment of the invention. References to “one embodiment” in this description do not necessarily refer to the same embodiment; however, neither are such embodiments mutually exclusive. Nor does “one embodiment” imply that there is but a single embodiment of the invention. For example, a feature, structure, act, etc. described in “one embodiment” may also be included in other embodiments. Thus, the invention may include a variety of combinations and/or integrations of the embodiments described herein.

Thus a method and apparatus for an output buffer with dynamic impedance control have been described.