Power electronics assemblies with cio bonding layers and double sided cooling, and vehicles incorporating the same

A 2-in-1 power electronics assembly includes a frame with a lower dielectric layer, an upper dielectric layer spaced apart from the lower dielectric layer, and a sidewall disposed between and coupled to the lower dielectric layer and the upper dielectric layer. The lower dielectric layer includes a lower cooling fluid inlet and the upper dielectric layer includes an upper cooling fluid outlet. A first semiconductor device assembly and a second semiconductor device assembly are included and disposed within the frame. The first semiconductor device is disposed between a first lower metal inverse opal (MIO) layer and a first upper MIO layer, and the second semiconductor device is disposed between a second lower MIO layer and a second upper MIO layer. An internal cooling structure that includes the MIO layers provides double sided cooling for the first semiconductor device and the second semiconductor device.

TECHNICAL FIELD

The present specification generally relates to power electronics assemblies, and more particularly, power electronics assemblies having metal substrates with integral stress-relief features.

BACKGROUND

Power electronics devices are often utilized in high-power electrical applications, such as inverter systems for hybrid electric vehicles and electric vehicles. Such power electronics devices include power semiconductor devices such as power insulated-gate bipolar transistors (IGBTs) and power transistors thermally bonded to a metal substrate. With advances in battery technology and increases in electronics device packaging density, operating temperatures of power electronics devices have increased and are currently approaching 200° C. Heat sinking devices may be coupled to the power electronics devices to remove heat and lower the maximum operating temperature of a power semiconductor device. Cooling fluid may be used to receive heat generated by the power semiconductor device by convective thermal transfer, and remove such heat from the power semiconductor device. For example, a jet of cooling fluid may be directed such that it impinges a surface of the power semiconductor device. Another way to remove heat from a power semiconductor device is to couple the power semiconductor device to a finned heat sink made of a thermally conductive material, such as aluminum.

However, as power electronics devices are designed to operate at increased power levels thereby generating more heat due to the demands of newly developed electrical systems, conventional heat sinks are unable to adequately remove sufficient heat to effectively lower the operating temperature of the power electronics devices to acceptable temperature levels. Further, conventional heat sinks and cooling structures require additional bonding layers and thermal matching materials (e.g., bond layers, substrates, thermal interface materials). These additional layers add substantial thermal resistance to the overall assembly and make thermal management of the electronics system challenging.

Accordingly, a need exists for alternative power electronics assemblies and power electronics devices having internal cooling structures.

SUMMARY

In one embodiment, a 2-in-1 power electronics assembly includes a frame with a lower dielectric layer, an upper dielectric layer spaced apart from the lower dielectric layer, and a sidewall disposed between and coupled to the lower dielectric layer and the upper dielectric layer. The lower dielectric layer includes a lower cooling fluid inlet and the upper dielectric layer includes an upper cooling fluid outlet. A first semiconductor device assembly and a second semiconductor device assembly are included and disposed within the frame. The first semiconductor device is disposed between a first lower metal inverse opal (MIO) layer and a first upper MIO layer, and the second semiconductor device is disposed between a second lower MIO layer and a second upper MIO layer. A middle dielectric layer is positioned between the upper dielectric layer, the lower dielectric layer, the first semiconductor device assembly, and the second semiconductor device assembly. A lower fluid chamber may be disposed between the lower dielectric layer, the middle dielectric layer, the first semiconductor device assembly and the second semiconductor device assembly. An upper fluid chamber may be disposed between the upper dielectric layer, the middle dielectric chamber, the first semiconductor device assembly and the second semiconductor device assembly.

In embodiments, the lower dielectric layer includes a lower cooling fluid outlet and the upper dielectric layer includes an upper cooling fluid inlet. In such embodiments, a lower cooling fluid circuit includes the lower cooling fluid inlet, the second lower MIO layer, the lower fluid chamber, the first lower MIO layer and the lower cooling fluid outlet and is configured for cooling fluid to flow proximate to surfaces of the first and second semiconductor devices. Also, an upper cooling fluid circuit includes the upper cooling fluid inlet, the first upper MIO layer, the upper fluid chamber, the second upper MIO layer and the upper cooling fluid outlet and is configured for cooling fluid to flow proximate to surfaces of the first and second semiconductor devices.

The 2-in-1 power electronics assembly may include a positive electrode disposed between the upper dielectric layer and the first upper MIO layer, a negative electrode disposed between the upper dielectric layer and the second upper MIO layer, and an output electrode disposed between the lower dielectric layer, the first lower MIO layer and the second lower MIO layer. The positive electrode may be in electrical communication with the first semiconductor device through the first upper MIO layer, the negative electrode may be in electrical communication with the second semiconductor device through the second upper MIO layer, and the output electrode may be in electrical communication with the first semiconductor device and the second semiconductor device through the first bottom MIO layer and the second MIO bottom layer, respectively. In some embodiments, a first isolating MIO layer may be included and be spaced apart from the first lower MIO layer and disposed between the first semiconductor device and the lower dielectric layer. In such embodiments, a first gate electrode may be included and be disposed between the lower dielectric layer and the first isolating MIO layer such that the first gate electrode is electrically isolated from the output electrode and in electrical communication with the first semiconductor device through the first isolating MIO layer. Also, a second isolating MIO layer may be included and spaced apart from the second upper MIO layer and disposed between the second semiconductor device and the upper dielectric layer. A second gate electrode may be disposed between the upper dielectric layer and the second isolating MIO layer such that the second gate electrode is electrically isolated from the negative electrode and in electrical communication with the second semiconductor device through the second isolating MIO layer.

In some embodiments, a fluid path may extend through the middle dielectric layer between the lower fluid chamber and the upper fluid chamber. The fluid path may be in the form of an MIO column extending through the middle dielectric layer, or in the alternative, at least one metal through hole via extending through the middle dielectric layer. In such embodiments, the lower dielectric layer may include a first lower cooling fluid inlet and a second lower cooling fluid inlet, and the upper dielectric layer may include a first upper cooling fluid outlet and a second upper cooling fluid outlet. A cooling fluid circuit includes the first and second lower cooling fluid inlets, the first and second lower MIO layers, the fluid path extending through the middle dielectric layer, the first and second upper MIO layers, and the first and second upper cooling fluid outlets. Also, the cooling fluid circuit may include a first cooling fluid flow path of: first lower cooling fluid inlet—first lower MIO layer—lower fluid chamber—fluid path—first upper MIO layer—first upper cooling fluid outlet; and a second cooling fluid flow path of: second lower cooling fluid inlet—second lower MIO layer—fluid path—upper fluid chamber—second upper MIO layer—second upper cooling fluid outlet.

In another embodiment, a 2-in-1 power electronics assembly includes a lower dielectric layer with a lower cooling fluid inlet and a lower cooling fluid outlet, and an upper dielectric layer spaced apart from the lower dielectric layer and with an upper cooling fluid inlet and an upper cooling fluid outlet. A middle dielectric layer may be positioned between and spaced apart from the lower dielectric layer and the upper dielectric layer. A first semiconductor device assembly and a second semiconductor device assembly are included. The first semiconductor device assembly includes a first semiconductor device disposed between a first lower MIO layer and a first upper MIO layer and the second semiconductor device assembly includes a second semiconductor device disposed between a second lower MIO layer and a second upper MIO layer. A lower fluid chamber may be provided between the lower dielectric layer and the middle dielectric layer and an upper fluid chamber may be provided between the middle dielectric layer and the upper dielectric layer. The first semiconductor assembly and the second semiconductor device assembly may be disposed between the lower dielectric layer and the upper dielectric layer, and the middle dielectric layer may be positioned between the first semiconductor device assembly and the second semiconductor device assembly. The 2-in-1 power electronics assembly may include a lower cooling fluid circuit with a lower cooling fluid path of: lower cooling fluid inlet—second lower MIO layer—lower fluid chamber—first lower MIO layer—lower cooling fluid outlet, and an upper cooling fluid circuit with an upper cooling fluid path of: upper cooling fluid inlet—first upper MIO layer—upper fluid chamber—second upper MIO layer—upper cooling fluid outlet.

In embodiments, a positive electrode may be disposed between the upper dielectric layer and the first upper MIO layer, a negative electrode may be disposed between the upper dielectric layer and the second upper MIO layer, and an output electrode disposed may be between the lower dielectric layer, the first lower MIO layer and the second lower MIO layer. In such embodiments, the positive electrode is in electrical communication with the first semiconductor device through the first upper MIO layer, the negative electrode is in electrical communication with the second semiconductor device through the second upper MIO layer, and the output electrode is in electrical communication with the first semiconductor device and the second semiconductor device through the first bottom MIO layer and the second MIO bottom layer, respectively. A first isolating MIO layer may be included and be spaced apart from the first lower MIO layer, and a first gate electrode may be disposed between the lower dielectric layer and the first isolating MIO layer. Also, a second isolating MIO layer may be included and be spaced apart from the second upper MIO layer, and a second gate electrode may be disposed between the upper dielectric layer and the second isolating MIO layer.

In still another embodiment, a 2-in-1 power electronics assembly includes a lower dielectric layer with a first lower cooling fluid inlet and a second lower cooling fluid inlet, and an upper dielectric layer with a first upper cooling fluid outlet and a second cooling fluid outlet. A middle dielectric layer may be positioned between and spaced apart from the lower dielectric layer and the upper dielectric layer, and a fluid path may extend through the middle dielectric layer. A first semiconductor device assembly with a first semiconductor device disposed between a first lower MIO layer and a first upper MIO layer may be included. Also, a second semiconductor device assembly with a second semiconductor device disposed between a second lower MIO layer and a second upper MIO layer may be included. A lower fluid chamber may be provided between the lower dielectric layer and the middle dielectric layer, and an upper fluid chamber may be provided between the middle dielectric layer and the upper dielectric layer. The first semiconductor assembly and the second semiconductor device assembly are disposed between the lower dielectric layer and the upper dielectric layer and the middle dielectric layer is positioned between the first semiconductor device assembly and the second semiconductor device assembly. A first portion of a cooling fluid circuit may include a first fluid flow path of: first lower cooling fluid inlet—first lower MIO layer—lower fluid chamber—fluid path—first upper MIO layer—first upper cooling fluid outlet. Also, a second portion of the cooling fluid circuit may include a second fluid flow path of: second lower cooling fluid inlet—second lower MIO layer—fluid path—upper fluid chamber—second upper MIO layer—second upper cooling fluid outlet.

In some embodiments, a positive electrode may be disposed between the lower dielectric layer and the first lower MIO layer, a negative electrode may be disposed between the upper dielectric layer and the second upper MIO layer, a first output electrode may be disposed between the upper dielectric layer and the first upper MIO layer, and a second output electrode may be disposed between the lower dielectric layer and the second lower MIO layer. In such embodiments, the positive electrode is in electrical communication with the first semiconductor device through the first lower MIO layer, the negative electrode is in electrical communication with the second semiconductor device through the second upper MIO layer, the first output electrode is in electrical communication with the first semiconductor device through the first upper MIO layer, and the second output electrode is in electrical communication with the second semiconductor device through the second lower MIO layer. A first isolating MIO layer spaced apart from the first upper MIO layer and disposed between the first semiconductor device and the upper dielectric layer may be included. Also, a second isolating MIO layer spaced apart from the second upper MIO layer and disposed between the second semiconductor device and the upper dielectric layer may be included. A first gate electrode may be disposed between the upper dielectric layer and the first isolating MIO layer, and a second gate electrode may be included and disposed between the upper dielectric layer and the second isolating MIO layer.

DETAILED DESCRIPTION

One non-limiting example of a 2-in-1 power electronics assembly with an internal cooling structure includes a pair of power semiconductor devices (semiconductor devices) disposed and mounted within a frame using a plurality of metal inverse opal (MIO) layers. As used herein, the phrase “2-in-1” refers to two separate semiconductor devices disposed within a frame. The frame includes a lower dielectric layer and an upper dielectric layer spaced apart from the lower dielectric layer. The lower dielectric layer includes at least one cooling fluid inlet and the upper dielectric layer includes at least one cooling fluid outlet. A middle dielectric layer is disposed between and spaced apart from the lower dielectric layer and the upper dielectric layer such that a lower fluid chamber is provided between the lower dielectric layer and the middle dielectric layer and an upper fluid chamber is provided between the middle dielectric layer and the upper dielectric layer. A first semiconductor device assembly and a second semiconductor device assembly are disposed within and coupled to the frame. The first semiconductor device assembly includes a first semiconductor device disposed between and bonded to a first pair of MIO layers and the second semiconductor device assembly includes a second semiconductor device disposed between and bonded to a second pair of MIO layers. Double sided cooling of the first and second semiconductor devices is provided via cooling fluid flowing through the at least one cooling fluid inlet, the first and second pairs of MIO layers and the at least one cooling fluid outlet. Various embodiments of 2-in-1 power electronics assemblies with internal cooling structures will be described in more detail herein.

Referring initially toFIGS. 1A-1C, one non-limiting example of a 2-in-1 power electronics assembly10with an internal cooling structure is illustrated. The 2-in-1 power electronics assembly10generally comprises a frame100, a first semiconductor device assembly150, and a second semiconductor device assembly170. The frame100includes a lower (−Y direction) dielectric layer110and an upper (+Y direction) dielectric layer120. The lower dielectric layer110and the upper dielectric layer120may be coupled together with at least one sidewall130to form the frame100. The lower dielectric layer110may include a lower cooling fluid inlet118and a lower cooling fluid outlet116, and the upper dielectric layer120may include an upper cooling fluid inlet126and an upper cooling fluid outlet128. The first semiconductor device assembly150may include a first lower MIO layer152(FIG. 1B), a first semiconductor device155, and a first upper MIO layer158. The second semiconductor device assembly170may include a second lower MIO layer172(FIG. 1C), a second semiconductor device175, and a second upper MIO layer178. A middle dielectric layer140(FIG. 1A) may be included and be positioned with the frame100spaced apart from and between the lower dielectric layer110and the upper dielectric layer120. A lower fluid chamber102is provided between the first semiconductor device assembly150, the second semiconductor device assembly170, the lower dielectric layer110, and the middle dielectric layer140. Also, an upper fluid chamber104is provided between the first semiconductor device assembly150, the second semiconductor device assembly170, the middle dielectric layer140, and the upper dielectric layer120.

The thicknesses of the lower dielectric layer110, the upper dielectric layer120, the middle dielectric layer140(collectively referred to herein as “dielectric layers110,120,140”), the first and second lower MIO layers152,172, the first and second semiconductor devices155,175, and the first and second upper MIO layers158,178may depend on the intended use of the power electronics assembly10. In one embodiment, the dielectric layers110,120,140each have a thickness within the range of about 1.0 millimeter (mm) and about 4.0 mm, the first and second lower MIO layers152,172, and the first and second upper MIO layers158,178each have a thickness within the range of about 1.0 mm to about 5.0 mm, and the first and second semiconductor devices155,175each have a thickness within the range of about 0.1 mm to about 0.3 mm. For example and without limitation, the dielectric layers110,120,140may each have a thickness of about 2.0 mm, the first lower MIO layer152and the second upper MIO layer178may each have a thickness of about 3.0 mm, the first upper MIO layer158and the second lower MIO layer172may each have a thickness of about 1.0 mm, and the first and second semiconductor devices155,175may each have a thickness of about 0.2 mm. It should be understood that other thicknesses may be utilized.

The dielectric layers110,120,140may be formed from dielectric materials such as silicon (Si), glass, and the like, and the frame100may be formed by bonding the lower dielectric layer110and the upper dielectric layer120to the at least one sidewall130. Non-limiting examples of bonding techniques used to bond the lower dielectric layer110and the upper dielectric layer120to the at least one sidewall130include fusion bonding, eutectic bonding, electroplate bonding, and the like. For example, in embodiments, the lower dielectric layer110, the upper dielectric layer120and the sidewall130are formed from Si and the frame100is formed using Si—Si fusion bonding, Si-gold (Au) eutectic bonding, Si-Metal electroplate bonding, and the like.

The first and second lower MIO layers152,172and the first and second upper MIO layers158,178may be formed from a metallic material that can be electrolytically or electrolessly deposited such as copper (Cu), aluminum (Al), nickel (Ni), Cu alloys, Al alloys, Ni alloys, and the like. The first and second semiconductor devices155,175may be formed from a wide band gap semiconductor material suitable for the manufacture or production of power semiconductor devices such as power IGBTs and power transistors. In embodiments, the first and second semiconductor devices155,175may be formed from wide band gap semiconductor materials including without limitation silicon carbide (SiC), silicon dioxide (SiO2), aluminum nitride (AlN), gallium nitride (GaN), gallium oxide (Ga2O3), boron nitride (BN), diamond, and the like. In embodiments, the MIO layers158,178and the semiconductor devices155,175may comprise a coating, e.g., nickel (Ni) plating, to assist in the bonding of the semiconductor devices155,175to the MIO layers158,178.

Referring specifically toFIGS. 1B-1C, the first lower MIO layer152of the first semiconductor device assembly150has a first surface151(e.g., a lower surface) and a second surface153(e.g., an upper surface), the first upper MIO layer158has a first surface157and a second surface159, and the first semiconductor device155has a first surface154and a second surface156. The first surface154of the first semiconductor device155may be bonded to the second surface153of the first lower MIO layer152and the second surface156of the first semiconductor device155may be bonded to the first surface157of the first upper MIO layer158. In some embodiments, a first isolating MIO layer160with a first surface162and a second surface164may be included and be spaced apart from the first lower MIO layer152. For example, an air gap166may be between the first isolating MIO layer160and the first lower MIO layer152. Also, the second surface164of the first isolating MIO layer160may be bonded to the first surface154of the first semiconductor device155.

The second lower MIO layer172of the second semiconductor device assembly170has a first surface171and a second surface173, the second upper MIO layer178has a first surface177and a second surface179, and the second semiconductor device175has a first surface174and a second surface176. The first surface174of the second semiconductor device175may be bonded to the second surface173of the second lower MIO layer172and the second surface176of the second semiconductor device175may be bonded to the first surface177of the second upper MIO layer178. In some embodiments, a second isolating MIO layer180with a first surface182and a second surface184may be included and may be spaced apart from the second upper MIO layer178. For example, an air gap186may be between the second isolating MIO layer180and the second upper MIO layer178. Also, the first surface182of the second isolating MIO layer180may be bonded to the second surface176of the second semiconductor device175.

Referring now back toFIG. 1A, the first semiconductor device assembly150is disposed between and may be bonded to the lower dielectric layer110and the upper dielectric layer120. Particularly, the first surface151(FIG. 1B) of the first lower MIO layer152may be bonded to the second surface114of the lower dielectric layer110and the second surface159of the first upper MIO layer158may be bonded to a first surface122of the upper dielectric layer120. In embodiments where the first isolating layer160is included, the first surface162of the first isolating layer160may be bonded to the second surface114of the lower dielectric layer110.

The second semiconductor device assembly170is disposed between and may be bonded to the lower dielectric layer110and the upper dielectric layer120. Particularly, the first surface171(FIG. 1C) of the second lower MIO layer172may be bonded to the second surface114of the lower dielectric layer110and the second surface179of the second upper MIO layer178may be bonded to the first surface122of the upper dielectric layer120. In embodiments where the second isolating MIO layer180is included, the second surface184of the second isolating MIO layer180may be bonded to the first surface122of the upper dielectric layer120.

In embodiments, the second semiconductor device assembly170is spaced apart from the first semiconductor device assembly150. In such embodiments, the middle dielectric layer140may be disposed between the first semiconductor device assembly150and the second semiconductor device assembly170as schematically depicted inFIG. 1A.

Still referring toFIG. 1A, in embodiments, a positive electrode190may be disposed between the upper dielectric layer120and the first semiconductor device assembly150, a negative electrode192may be disposed between the upper dielectric layer120and the second semiconductor device assembly170, and an output electrode194may be disposed between the lower dielectric layer110and the first and second semiconductor device assemblies150,170. For example, the positive electrode190may be disposed between the first surface122of the upper dielectric layer120and the second surface159(FIG. 1B) of the first upper MIO layer158. In such an example, it should be understood that the positive electrode190may be in electrical communication (contact) with the first semiconductor device155through the first upper MIO layer158. Also, the negative electrode192may be disposed between the first surface122of the upper dielectric layer120and the second surface179(FIG. 1B) of the second upper MIO layer178, and the negative electrode192may be in electrical communication with the second semiconductor device175through the second upper MIO layer178. The output electrode194may be disposed between the second surface114of the lower dielectric layer110and the first surface151(FIG. 1B) of the first lower MIO layer152and disposed between the first surface171(FIG. 1C) of the second lower MIO layer172. It should be understood that the output electrode194may be in electrical communication with the first semiconductor device155through the first lower MIO layer152and in electrical communication with the second semiconductor device175through the second lower MIO layer172.

In some embodiments, the positive electrode190and/or the negative electrode192may be in direct contact with the first surface122of the upper dielectric layer120and the output electrode194may be in direct contact with the second surface114of the lower dielectric layer110. In other embodiments, the positive electrode190and/or the negative electrode192may not be in direct contact with the first surface122of the upper dielectric layer120and/or the output electrode194may not be in direct contact with the second surface114of the lower dielectric layer110. For example, one or more bonding layers (not shown) may be disposed between the positive electrode190and/or the negative electrode192and the first surface122of the upper dielectric layer120and/or one or more bonding layers may be disposed between the output electrode194and the second surface114of the lower dielectric layer110. It should be understood that the positive electrode190and/or the negative electrode192may extend continuously from the first surface122of the upper dielectric layer120up to (+Y direction) and across a second surface124of the upper dielectric layer120as depicted inFIG. 1A. That is, electrodes described herein may extend continuously from between a dielectric layer and an adjacent MIO layer to an oppositely disposed surface of the dielectric layer such that electrical communication with the electrodes from an outer surface of the frame100is provided.

In addition to the positive electrode190, the negative electrode192, and the output electrode194, a first gate electrode196may be included and disposed between the lower dielectric layer110and the first semiconductor device assembly150and a second gate electrode198may be disposed between the upper dielectric layer120and the second semiconductor device assembly170. Particularly, the first gate electrode196may be disposed between the second surface114of the lower dielectric layer110and the first surface162(FIG. 1B) of the first isolating MIO layer160. Accordingly, the first gate electrode196may be electrically isolated from the output electrode194and in electrical communication with the first semiconductor device155through the first isolating MIO layer160. Also, the second gate electrode198may be disposed between the first surface122of the upper dielectric layer120and the second surface184(FIG. 1C) of the second isolating MIO layer180. Accordingly, the second gate electrode198may be electrically isolated from the negative electrode192and in electrical communication with the second semiconductor device175through the second isolating MIO layer180.

The 2-in-1 power electronics assembly10comprises an internal cooling structure that includes a lower cooling fluid circuit CFCLand an upper cooling fluid circuit CFCU. In one non-limiting example the lower cooling fluid circuit CFCLprovides cooling to the first surfaces154,174of the first and second semiconductor devices155,175, respectively, and the upper cooling fluid circuit CFCUprovides cooling to the second surfaces156,176of the first and second semiconductor devices155,175, respectively. Particularly, the lower cooling fluid circuit CFCLcomprises the lower cooling fluid inlet118, the second lower MIO layer172(FIG. 1C), the lower fluid chamber102, the first lower MIO layer152(FIG. 1B) and the lower cooling fluid outlet116. Accordingly, the cooling fluid circuit CFCLis configured for cooling fluid ‘CF’ to flow through the 2-in-1 power electronics assembly10via a cooling path of: lower cooling fluid inlet118—second lower MIO layer172—lower fluid chamber102—first lower MIO layer152—lower cooling fluid outlet116. The cooling fluid CF flowing through the lower cooling fluid circuit CFCLprovides cooling to both of the semiconductor devices155,175by flowing proximate to the first surfaces154,174(FIGS. 1B-1C) of the semiconductor devices155,175, respectively, and removing heat generated by the semiconductor devices155,175. That is, heat generated by and transferred from the semiconductor devices155,175to the first and second lower MIO layers152,172, respectively, is transferred to and removed by the cooling fluid CF flowing through the lower cooling fluid circuit CFCL. As used herein, the term “proximate to” refers to a distance within 1.0 mm of an adjacent semiconductor device surface, for example, within 0.5 mm or within 0.2 mm of an adjacent semiconductor device surface. The upper cooling fluid circuit CFCUcomprises the upper cooling fluid inlet126, the first upper MIO layer158(FIG. 1B), the upper fluid chamber104, the second upper MIO layer178(FIG. 1C) and the upper cooling fluid outlet128. Accordingly, the upper cooling fluid circuit CFCUis configured for the cooling fluid CF to flow through the 2-in-1 power electronics assembly10via a cooling path of: upper cooling fluid inlet126—first upper MIO layer158—upper fluid chamber104—second upper MIO layer178—upper cooling fluid outlet128. The cooling fluid CF flowing through the upper cooling fluid circuit CFCUprovides cooling to both of the semiconductor devices155,175by flowing proximate to the second surfaces156,176(FIGS. 1B-1C) of the semiconductor devices155,175, respectively, and removing heat generated by the semiconductor devices155,175. That is, heat generated by and transferred from the semiconductor devices155,175to the first and second upper MIO layers158,178, respectively, is transferred to and removed by cooling fluid CF flowing through the upper cooling fluid circuit CFCU.

Referring now toFIGS. 2A-2B, a non-limiting example of the bonding between layers of the 2-in-1 power electronics assembly10is schematically depicted. Particularly, an exploded view of section2-2shown inFIG. 1Abefore layers of section2-2are bonded together is schematically depicted inFIG. 2Aand a view of section2-2after the layers are bonded together is schematically depicted inFIG. 2B. In the non-limiting example schematically depicted inFIGS. 2A-2Bthe layers may be bonded together via transient liquid phase (TLP) bonding and the lower dielectric layer110and the first semiconductor device155are TLP bonded together by the first isolating layer160and the first semiconductor device155and the upper dielectric layer120are TLP bonded together by the first upper MIO layer158.

Referring specifically toFIG. 2A, before TLP bonding a low melting point (LMP) lower bonding layer162bis disposed on the first surface162of the first isolating MIO layer160and a LMP upper bonding layer164bdisposed on the second surface164; a lower bonding layer154bis disposed on the first surface154of the first semiconductor device155and an upper bonding layer156bis disposed on the second surface156; a LMP lower bonding layer157bis disposed on the first surface157of the first upper MIO layer158and a LMP upper bonding layer159bis disposed on the second surface159; and a bonding layer122bis disposed on the first surface122of the upper dielectric layer120. In embodiments, the pair of LMP bonding layers162b,164band the pair of LMP bonding layers157b,159b(collectively referred to herein as “LMP bonding layers162b,164b,157b,159b”) each have a melting point that is less than a melting point of the first isolating MIO layer160, the first upper MIO layer158, the first gate electrode196, the pair of bonding layers154b,156b, and the bonding layer122b. Particularly, the LMP bonding layers162b,164b,157b,159beach have a melting point that is less than a TLP sintering temperature used to TLP bond the first semiconductor device assembly150to the lower dielectric layer110and the upper dielectric layer120. As a non-limiting example, the TLP sintering temperature is between about 280° C. and about 350° C., the LMP bonding layers162b,164b,157b,159bhave a melting point less than about 280° C., and the first isolating MIO layer160, the first upper MIO layer158, the first gate electrode196, the pair of bonding layers154b,156b, and the bonding layer122beach have a melting point greater than 350° C. For example, the LMP bonding layers162b,164b157b,159bmay be formed from tin (Sn) with a melting point of about 232° C., whereas the first isolating MIO layer160, the first upper MIO layer158, the first gate electrode196, the pair of bonding layers154b,156b, and the bonding layer122bmay be formed from materials such as Cu, Ni, Al, silver (Ag), zinc (Zn) and magnesium (Mg) with a melting point of about 1085° C., 1455° C., 660° C., 962° C., 420° C. and 650° C., respectively. Accordingly, the LMP bonding layers162b,164b,157b,159bat least partially melt, and the first isolating MIO layer160, the first upper MIO layer158, the first gate electrode196, the pair of bonding layers154b,156b, and the bonding layer122bdo not melt during TLP sintering together the layers of the 2-in-1 power electronics assembly10.

The first upper MIO layer158, and other MIO layers described herein, have a plurality of hollow spheres and a predefined porosity. In embodiments, a permeability and thermal conductivity for the first upper MIO layer158, and other MIO layers described herein, is a function of the porosity, i.e., the amount and/or size of the porosity, of the first upper MIO layer158. As used herein, the term “permeability” refers to the ability of an MIO layer to allow a liquid or gas flow through the MIO layer. The MIO layers described herein may be formed by depositing metal within a sacrificial template of packed microspheres and then dissolving the microspheres to leave a skeletal network of metal with a periodic arrangement of interconnected hollow spheres which may or may not be etched to increase the porosity and interconnection of the hollow spheres. The skeletal network of metal has a large surface area and the amount of porosity of an MIO layer can be varied by changing the size of the sacrificial microspheres. Also, the size of the microspheres and thus the size of the hollow spheres can be varied as a function of thickness (Y direction) of an MIO layer such that a graded porosity, i.e., graded hollow sphere diameter, as a function of thickness is provided. Accordingly, the permeability and thermal conductivity of the MIO layers described herein can be varied and controlled to provide a desired cooling fluid flow rate within the MIO layers and a desired heat removal rate from semiconductor devices in a 2-in-1 power electronics assembly.

In addition to a predefined porosity providing a desired permeability for an MIO layer, a stiffness for an MIO layer is a function of the predefined porosity. As used herein, the term stiffness refers to the elastic modulus (also known as Young's modulus) of a material, i.e., a measure of a material's resistance to being deformed elastically when a force is applied to the material. Similar to the permeability and thermal conductivity of an MIO layer, the stiffness of MIO layers described herein can be varied by the varying size of the microspheres and thus the size of the hollow spheres as a function of thickness (Y direction) of the MIO layer. Accordingly, a graded stiffness as a function of MIO layer thickness (Y direction) may be provided and controlled to accommodate thermal stress for a given semiconductor device—frame combination.

Generally, the MIO layers described herein comprise flat thin layers and bonding layers described herein comprise flat thin films. As non-limiting examples, the thicknesses of the first isolating MIO layer160and the first upper MIO layer158may be between about 25 micrometers (μm) and about 1000 μm. In embodiments, the first isolating MIO layer160has a thickness between about 100 μm and about 200 μm and the first upper MIO layer158has a thickness between about 25 μm and about 100 μm. Also, the thickness of each of the LMP bonding layers162b,164b,157b,159bmay each be between 1 μm and 20 μm. In embodiments, the LMP bonding layers162b,164b,157b,159beach have a thickness between about 2 μm and about 15 μm.

The electrodes and the bonding layers described herein may be formed using conventional multilayer thin film forming techniques. Non-limiting examples of thin film forming techniques used to form the electrodes and bonding layers include chemical vapor deposition (CVD) of the electrodes and/or bonding layers onto a surface, physical vapor depositing (PVD) the electrodes and/or bonding layers onto a surface, electrolytically depositing the electrodes and/or bonding layers onto a surface, electroless depositing the electrodes and/or bonding layers onto a surface, and the like.

Referring now toFIG. 2B, the first gate electrode196, the first isolating MIO layer160, the first upper MIO layer158, the pair of bonding layers154b,156b, and the bonding layer122bremain as inFIG. 2A. That is, the first gate electrode196, the first isolating MIO layer160, the first upper MIO layer158, the pair of bonding layers154b,156b, and the bonding layer122bdo not melt during the TLP bonding process and generally remain the same thickness as before the TLP bonding process. In contrast, the LMP bonding layers162b,164b,157b,159bat least partially melt, diffuse into the adjacent first gate electrode196and bonding layers154b,156b,122b, respectively, and form TLP bond layers196a,154a,156a,122a, respectively. Although TLP bond layers196a,154a,156a,122adepicted inFIG. 2Bhave consumed the LMP bonding layers162b,164b,157b,159b, respectively, in embodiments the TLP bond layers196a,154a,156a, and/or122amay not totally consume the LMP bonding layers162b,164b,157b,159b, respectively, i.e., a thin layer of the LMP bonding layers162b,164b,157b,159bmay be present after the first gate electrode196, the first isolating MIO layer160, the first semiconductor device155, the first upper MIO layer158, and the upper dielectric layer120are TLP bonded together. In other embodiments, one or more of the TLP bond layers196a,154a,156a,122amay comprise no layers, i.e., all of the LMP bonding layers162b,164b,157b, and/or159bdiffuse into the first gate electrode196, the first isolating MIO layer160, the first semiconductor device155, the first upper MIO layer158, and/or the upper dielectric layer120, respectively, thereby resulting in a clearly defined TLP bond layers196a,154a,156a, and/or122anot being present.

In embodiments, the first gate electrode196, the first isolating MIO layer160, and the first upper MIO layer158are formed from Cu. That is, the first gate electrode196is a CU electrode, and the first isolating MIO layer160and the first upper MIO layer158are copper inverse opal (CIO) layers. In such embodiments, the LMP bonding layers162b,164b,157b,159bmay be formed from Sn, the bonding layers154b,156b,122bmay be formed from Cu or Ni, and the TLP bond layers196a,154a,156a,122acomprise an intermetallic layer of Cu and Sn. In some embodiments, the TLP bond layers196a,154a,156a,122acomprise an intermetallic layer of Cu, Ni and Sn. For example and without limitation, the TLP bond layers196a,154a,156a,122amay include the intermetallic Cu6Sn5, the intermetallic (Cu, Ni)6Sn5, the intermetallic Cu3Sn or a combination of the intermetallics Cu6Sn5, (Cu, Ni)6Sn5, and/or Cu3Sn. It should be understood that the LMP bonding layers162b,164b,157b,159bformed from Sn at least partially melt at the TLP sintering temperature and then isothermally solidify during the formation of the Cu—Sn intermetallic(s) since Cu6Sn5starts to melt at 415° C. and Cu3Sn starts to melt at about 767° C. That is, a melting temperature of the TLP bond layers196a,154a,156a,122ais greater than a melting temperature of the pair of LMP bonding layers162b,164b,157b,159b, respectively.

WhileFIGS. 2A-2Bschematically depict TLP bonding of the lower dielectric layer110, the first isolating MIO layer160, the first semiconductor device155, the first upper MIO layer158and the upper dielectric layer120, it should be understood that other bonding techniques may be used to couple together the various layers of the 2-in-1 power electronics assembly10. Non-limiting bonding techniques include soldering, brazing, fusion bonding, eutectic bonding, sintering, and the like. For example, soldering may be used to couple together the various layers of the 2-in-1 power electronics assemblies since the internal cooling structures may lower the operating temperatures of the 2-in-1 power electronics assemblies such that TLP bonding and TLP bonds are not required.

Referring now toFIGS. 3A-3C, another non-limiting example of a 2-in-1 power electronics assembly20with an internal cooling structure is illustrated. The 2-in-1 power electronics assembly20generally comprises a frame200, a first semiconductor device assembly250, and a second semiconductor device assembly270. The frame200includes a lower (−Y direction) dielectric layer210and an upper (+Y direction) dielectric layer220. The lower dielectric layer210and the upper dielectric layer220may be coupled together with at least one sidewall230to form the frame200. The lower dielectric layer210may include a first lower cooling fluid inlet216and a second lower cooling fluid inlet218, and the upper dielectric layer220may include a first upper cooling fluid outlet226and a second upper cooling fluid outlet228. Referring specifically toFIGS. 3B-3C, the first semiconductor device assembly250may include a first lower MIO layer252, a first semiconductor device255, and a first upper MIO layer258. The second semiconductor device assembly270may include a second lower MIO layer272, a second semiconductor device275, and a second upper MIO layer278. A middle dielectric layer240may be included and be positioned with the frame200spaced apart from and between the lower dielectric layer210and the upper dielectric layer220. A lower fluid chamber202(FIG. 3A) is provided between the first semiconductor device assembly250, the second semiconductor device assembly270, the lower dielectric layer210, and the middle dielectric layer240. Also, an upper fluid chamber204(FIG. 3A) is provided between the first semiconductor device assembly250, the second semiconductor device assembly270, the middle dielectric layer240, and the upper dielectric layer220.

The thicknesses of the lower dielectric layer210, the upper dielectric layer220, the middle dielectric layer240(collectively referred to herein as “dielectric layers210,220,240”), the first and second lower MIO layers252,272, the first and second semiconductor devices255,275, and the first and second upper MIO layers258,278may depend on the intended use of the power electronics assembly20. In one embodiment, the dielectric layers210,220,240each have a thickness within the range of about 1.0 mm and about 4.0 mm, the first and second lower MIO layers252,272, and the first and second upper MIO layers258,278each have a thickness within the range of about 1.0 mm to about 5.0 mm, and the first and second semiconductor devices255,275each have a thickness within the range of about 0.1 mm to about 0.3 mm. For example and without limitation, the dielectric layers210,220,240may each have a thickness of about 2.0 mm, the first lower MIO layer252and the second upper MIO layer278may each have a thickness of about 3.0 mm, the first upper MIO layer258and the second lower MIO layer272may each have a thickness of about 1.0 mm, and the first and second semiconductor devices255,275may each have a thickness of about 0.2 mm. It should be understood that other thicknesses may be utilized.

The dielectric layers210,220,240may be formed from dielectric materials such as silicon (Si), glass, and the like, and the frame200may be formed by the lower dielectric layer210and the upper dielectric layer220bonded to the at least one sidewall230. The first and second lower MIO layers252,272and the first and second upper MIO layers258,278may be formed from a metallic material that can be electrolytically or electrolessly deposited such as copper (Cu), aluminum (Al), nickel (Ni), Cu alloys, Al alloys, Ni alloys, and the like. The first and second semiconductor devices255,275may be formed from a wide band gap semiconductor material suitable for the manufacture or production of power semiconductor devices such as power IGBTs and power transistors. In embodiments, the first and second semiconductor devices255,275may be formed from wide band gap semiconductor materials including without limitation silicon carbide (SiC), silicon dioxide (SiO2), aluminum nitride (AlN), gallium nitride (GaN), gallium oxide (Ga2O3), boron nitride (BN), diamond, and the like. In embodiments, the dielectric layers210,220,240, and the first and second semiconductor devices255,275may comprise a coating, e.g., nickel (Ni) plating, to assist in the bonding of the dielectric layers210,220,240, and the first and second semiconductor devices255,275to the first and second lower MIO layers252,272and the first and second upper MIO layers258,278.

Still referring toFIGS. 3B-3C, the first lower MIO layer252of the first semiconductor device assembly250(FIG. 3B) has a first surface251and a second surface253, the first upper MIO layer258has a first surface257and a second surface259, and the first semiconductor device255has a first surface254and a second surface256. The first surface254of the first semiconductor device255may be bonded to the second surface253of the first lower MIO layer252and the second surface256of the first semiconductor device255may be bonded to the first surface257of the first upper MIO layer258. In some embodiments, a first isolating MIO layer260with a first surface262and a second surface264is included and may be included and may be spaced apart from the first upper MIO layer258. For example, an air gap266may be between the first isolating MIO layer260and the first upper MIO layer258. Also, the first surface262of the first isolating MIO layer260may be bonded to the second surface256of the first semiconductor device255.

The second lower MIO layer272of the second semiconductor device assembly270(FIG. 3C) has a first surface271and a second surface273, the second upper MIO layer278has a first surface277and a second surface279, and the second semiconductor device275has a first surface274and a second surface276. The first surface274of the second semiconductor device275may be bonded to the second surface273of the second lower MIO layer272and the second surface276may be bonded to the first surface277of the second upper MIO layer278. In some embodiments, a second isolating MIO layer280with a first surface282and a second surface284is included and may be spaced apart from the second upper MIO layer278. For example, an air gap288may be between the second isolating MIO layer280and the second upper MIO layer278. Also, the first surface282of the second isolating MIO layer280may be bonded to the second surface276of the second semiconductor device275.

The first semiconductor device assembly250is disposed between and may be bonded to the lower dielectric layer210and the upper dielectric layer220. Particularly, the first surface251(FIG. 3B) of the first lower MIO layer252may be bonded to the second surface214of the lower dielectric layer210and the second surface259of the first upper MIO layer258may be bonded to the first surface222of the upper dielectric layer220. In embodiments where the first isolating MIO layer260is included, the second surface264of the first isolating MIO layer260may be bonded to the first surface222of the upper dielectric layer220.

The second semiconductor device assembly270is disposed between and may be bonded to the lower dielectric layer210and the upper dielectric layer220. Particularly, the first surface271(FIG. 3C) of the second lower MIO layer272may be bonded to the second surface214of the lower dielectric layer210and the second surface279of the second upper MIO layer278may be bonded to the first surface222of the upper dielectric layer220. In embodiments where the second isolating MIO layer280is included, the second surface284of the second isolating MIO layer280may be bonded to the first surface222of the upper dielectric layer220. In embodiments, the second semiconductor device assembly270is spaced apart from the first semiconductor device assembly250. In such embodiments, the middle dielectric layer240may be disposed between the first semiconductor device assembly250and the second semiconductor device assembly270as schematically depicted inFIG. 3A.

A fluid path extending through the middle dielectric layer240between the second lower MIO layer272and the first upper MIO layer258is provided. In some embodiments, the fluid path is provided by an MIO column232extending through the middle dielectric layer240as schematically depicted inFIG. 3B. In such embodiments, the MIO column232may extend from the second lower MIO layer272up through (+Y direction) the middle dielectric layer240to the first upper MIO layer258such that the MIO column232may be in fluid communication with the second lower MIO layer272and the first upper MIO layer258. The MIO column232may be formed as a single MIO component with the second lower MIO layer272and the first upper MIO layer258. In the alternative, the MIO column232may be formed as a separate MIO component from the second lower MIO layer272and/or the first upper MIO layer258so long as fluid and electrical communication between the MIO column232, the second lower MIO layer272and the first upper MIO layer258is provided. In embodiments where the MIO column232is formed as a separate column, the MIO column includes a first surface231that may be bonded to the second surface214of the lower dielectric layer210and a second surface233that may be bonded to the first surface222of the upper dielectric layer220.

In other embodiments, the fluid path is provided by at least one metal through hole via242extending through the middle dielectric layer240as schematically depicted inFIG. 3C. In such embodiments, the at least one metal through hole via242may extend from the second lower MIO layer272up through (+Y direction) the middle dielectric layer240to the first upper MIO layer258. In such embodiments, the at least one metal through via242may be in fluid and electrical communication with the second lower MIO layer272and the first upper MIO layer258. Also, the at least one metal through hole via242includes an electrically conductive inner surface244such that the second lower MIO layer272is in electrical communication with the first upper MIO layer258via the at least one metal through hole via242. Non-limiting examples of materials used to form the electrically conductive inner surface244include Cu, Ag, Au, Al, alloys thereof, and the like.

Referring back toFIG. 3A, in embodiments, a positive electrode290may be disposed between the lower dielectric layer210and the first semiconductor device assembly250and a negative electrode292may be disposed between the upper dielectric layer220and the second semiconductor device assembly270. Particularly, the positive electrode290may be disposed between the second surface214of the lower dielectric layer210and the first surface251(FIG. 3B) of the first lower MIO layer252, and the positive electrode290may be in electrical communication with the first semiconductor device255through the first lower MIO layer252. The negative electrode292may be disposed between the first surface222of the upper dielectric layer220and the second surface279(FIG. 3C) of the second upper MIO layer278, and the negative electrode292may be in electrical communication with the second semiconductor device275through the second upper MIO layer278.

A first output electrode293may be disposed between the upper dielectric layer220and the first semiconductor device assembly250and a second output electrode294may be disposed between the lower dielectric layer210and the second semiconductor device assembly270. Particularly, the first output electrode293may be disposed between the first surface222of the upper dielectric layer220and the second surface259of the first upper MIO layer258and the first output electrode293may be in electrical communication with the first semiconductor device255through the first upper MIO layer258. The first output electrode293may also be in electrical communication with the second semiconductor device275through the first upper MIO layer258, the MIO column232(FIG. 3B) or the at least one metal through via242(FIG. 3C), and the second lower MIO layer272. The second output electrode294may be disposed between the second surface214of the lower dielectric layer210and the first surface271of the second lower MIO layer272. The second output electrode294may be in electrical communication with the second semiconductor device275through the second lower MIO layer272. The second output electrode294may also be in electrical communication with the first semiconductor device255through the second lower MIO layer272, MIO column232(FIG. 3B) or at least one metal through via242(FIG. 3C), and the first upper MIO layer258.

In some embodiments, the positive electrode290and the second output electrode294may be in direct contact with the second surface214of the lower dielectric layer210, and the negative electrode292and the first output electrode293may be in direct contact with the first surface222of the upper dielectric layer220. In other embodiments, the positive electrode290and the second output electrode294may not be in direct contact with the second surface214of the lower dielectric layer210, and the negative electrode292and the first output electrode293may not be in direct contact with the first surface222of the upper dielectric layer220. For example, one or more bonding layers (not shown) may be disposed between the positive electrode290and/or the second output electrode294and the second surface214of the lower dielectric layer210, and one or more bonding layers (not shown) may be disposed between the negative electrode292and/or the first output electrode293and the first surface222of the upper dielectric layer220.

A first gate electrode296and a second gate electrode298may be included with the first gate electrode296disposed between the upper dielectric layer220and the first isolating MIO layer260and the second gate electrode298disposed between the upper dielectric layer220and the second isolating MIO layer280. Particularly, the first gate electrode296may be disposed between the first surface222of the upper dielectric layer220and the second surface264of the first isolating MIO layer260, and the first gate electrode296may be electrically isolated from the first output electrode293and in electrical communication with the first semiconductor device255through the first isolating MIO layer260. The second gate electrode298may be disposed between the first surface222of the upper dielectric layer220and the second surface284of the second isolating MIO layer280, and the second gate electrode298may be electrically isolated from the negative electrode292and in electrical communication with the second semiconductor device275through the second isolating MIO layer280.

Though not shown in the figures, it should be understood that the layers of the 2-in-1 power electronics assembly20may include TLP bonding layers and be TLP bonded together as schematically depicted above with reference toFIGS. 2A-2B. In the alternative, or in addition to, two or more of the layers of the 2-in-1 power electronics assembly20may be bonded together using other known bonding techniques including without limitation soldering, brazing, sintering, and the like.

Still referring toFIG. 3A, the 2-in-1 power electronics assembly20comprises a cooling fluid circuit with two lower cooling fluid inlets and two upper cooling fluid outlets. In one non-limiting example the cooling fluid circuit provides cooling to the first surfaces254,274of the first and second semiconductor devices255,275, respectively, and to the second surfaces256,276of the first and second semiconductor devices255,275, respectively. Particularly, the cooling fluid circuit comprises the lower cooling fluid inlets216,218, the first and second lower MIO layers252,272, the lower fluid chamber202, the MIO column232(FIG. 3B) or the at least one metal through hole via242(FIG. 3C), the first and second upper MIO layers258,278, the upper fluid chamber204, and the upper cooling fluid outlets226,228. Accordingly, a first portion of cooling fluid CF flows through the cooling fluid circuit via a cooling fluid path of: first lower cooling fluid inlet216—first lower MIO layer252—lower fluid chamber202—MIO column232(FIG. 3B) or metal through via242(FIG. 3C)—first upper MIO layer258—first upper cooling fluid outlet226. In the alternative, or in addition to, a first portion of cooling fluid CF flows through the cooling fluid circuit via a cooling fluid path of: first lower cooling fluid inlet216—first lower MIO layer252—lower fluid chamber202—MIO column232(FIG. 3B) or metal through via242(FIG. 3C)—upper fluid chamber204—second upper MIO layer278—second upper cooling fluid outlet228. Also, a second portion of cooling fluid CF flows through the cooling fluid circuit via a cooling fluid path of: second lower cooling fluid inlet218—second lower MIO layer272—MIO column232(FIG. 3B) or metal through via242(FIG. 3C)—upper fluid chamber204—second upper MIO layer278—second upper cooling fluid outlet228. In the alternative, or in addition to, a second portion of cooling fluid CF flows through the cooling fluid circuit via a cooling fluid path of: second lower cooling fluid inlet218—second lower MIO layer272—MIO column232(FIG. 3B) or metal through via242(FIG. 3C)—first upper MIO layer258—first upper cooling fluid outlet226.

The cooling fluid CF flowing through the cooling fluid circuit provides cooling to both of the semiconductor devices255,275by flowing proximate to the first surfaces254,274and the second surfaces256,276and removing heat generated by the semiconductor devices155,175. That is, heat generated by and transferred from the semiconductor devices155,175is transferred to and removed by the cooling fluid CF flowing through the cooling fluid circuit.

The power electronics assemblies described herein may be incorporated into an inverter circuit or system that converts direct current electrical power into alternating current electrical power and vice versa depending on the particular application. For example, in a hybrid electric vehicle application as illustrated inFIG. 4, several power electronics assemblies10a-10fmay be electrically coupled together to form a drive circuit that converts direct current electrical power provided by a bank of batteries364into alternating electrical power that is used to drive an electric motor366coupled to the wheels368of a vehicle360to propel the vehicle360using electric power. The power electronics assemblies10a-10fused in the drive circuit may also be used to convert alternating current electrical power resulting from use of the electric motor366and regenerative braking back into direct current electrical power for storage in the bank of batteries364.

Power semiconductor devices utilized in such vehicular applications may generate a significant amount of heat during operation, which require cooling of the semiconductor devices. The internal cooling structures described and illustrated herein utilize MIO bonding layers to cool the semiconductor devices while also providing a compact package design.

It should now be understood that the MIO bonding layers and internal cooling structures incorporated into the power electronics assemblies and vehicles described herein may be utilized to cool semiconductor devices, thereby providing for a more compact cooler package design.

It is noted that the term “about” and “generally” may be utilized herein to represent the inherent degree of uncertainty that may be attributed to any quantitative comparison, value, measurement, or other representation. This term is also utilized herein to represent the degree by which a quantitative representation may vary from a stated reference without resulting in a change in the basic function of the subject matter at issue. The terms “lower”, “upper” and “middle” are used in relation to the figures and are not meant to define an exact orientation of 2-in-1 power electronics assemblies or layers used to form 2-in-1 electronic assemblies described herein.