Fabrication method of polycrystalline silicon liquid crystal display device

A method for fabricating a polysilicon silicon liquid crystal display device is disclosed in which a contact hole connecting source and drain electrodes to an active layer is formed without a stepped portion. An insulation layer containing a porous silicon nitride layer is formed. Wet etching the contact hole through the porous silicon nitride layer and an underlying silicon oxide layer does not generate the stepped portion as the etch rates of the porous silicon nitride layer and the silicon oxide layer are the same. Because the stepped portion is not generated at a contact hole, disconnection of source and drain electrodes formed in the contact hole is prevented, thereby preventing deterioration of the liquid crystal display device from occurring.

This application claims the benefit of priority to Korean Patent Application No.: 30193/2004, filed on Apr. 29, 2004, which is incorporated herein by reference in its entirety.

BACKGROUND

The present invention relates to a fabrication method of a liquid crystal display device (LCD), and particularly, to a method for forming a contact hole connecting source and drain electrodes and an active layer of a thin film transistor (TFT).

2. Description of the Related Art

A liquid crystal display panel includes TFT array layer, color filter layer corresponding to the TFT array layer and liquid crystal layer therebetween. The TFT array layer includes a plurality of unit pixels arranged in a matrix form and the color filter substrate includes color filter layer to display information as color.

The unit pixels on the TFT array substrate are defined by a plurality of gate lines and a plurality of data lines which perpendicularly intersect with the gate lines, and a TFT for driving the unit pixel is formed at an intersection of the gate line and the data line.

While an amorphous silicon TFT including an active layer made of amorphous silicon has been primarily used in LCDs, other types of TFTs are currently being investigated. One such type of TFT under development is a polycrystalline silicon (polysilicon) TFT including an active layer made of polysilicon and having an operation characteristic that is better than the TFT having an active layer made of amorphous silicon layer.

A structure of a polysilicon TFT will now be described with reference toFIG. 1. The polysilicon TFT includes a buffer layer2, a silicon oxide (SiO2) layer formed on a transparent substrate1such as glass, plastic or the like, and an active layer3made of polysilicon and formed on the buffer layer2. A first insulation layer4for insulating the polysilicon layer is formed on the polysilicon active layer3.

A gate electrode5is formed on the first insulation layer4, and a second insulation layer6is formed on the gate electrode5. The second insulation layer6is a silicon oxide (SiO2) layer and insulates source and drain electrodes7and8to be formed on the second insulation layer6from the gate electrode5. A source electrode7and a drain electrode8for applying a data signal to a pixel electrode10are formed on the second insulation layer6. The source and drain electrodes7and8are connected to the active layer3through contact holes20through the first insulation layer4and the second insulation layer6.

In addition, a passivation layer9is formed on the source and drain electrodes7,8so as to protect the TFT formed under the passivation layer9and flatten the liquid crystal display device in which the TFT is fabricated. A contact hole30for connecting the drain electrode8and the pixel electrode10to each other is formed at the passivation layer9, and the pixel electrode10is connected to the drain electrode8through the contact hole30.

Hereinafter, a process for forming a contact hole20connecting the source and drain electrode7and8to the active layer3will now be described in detail with reference toFIG. 2.

A second insulation layer6is formed on a gate electrode5, and then a photoresist layer11is formed on the second insulation layer6. When the photoresist layer11is exposed and developed by using a mask, a contact hole pattern is formed as shown inFIG. 2. Wet-etching is performed using the photoresist layer11including the contact hole pattern as a mask, thereby etching the second insulation layer6and then the first insulation layer4.

Because wet-etching is isotropic, the second insulation layer6may be excessively etched under the photoresist pattern, and this etched-away portion is called undercut. Undercutting leads to a contact hole that does not satisfy a desired design rule, and thus the source and drain electrodes are formed to be larger than the desired design rule. In addition, undercutting causes a stepped contact hole20to be formed as shown by the first insulation layer4and the second insulation layer6inFIG. 2. If a metal thin layer for source/drain electrodes is deposited in the stepped contact hole20described above, the formed thin layer may be disconnected.

Thus, forming a contact hole by wet-etching does not permit satisfaction of a desired design rule, and undercut occurs. In order to solve such problems, techniques using silicon nitride layer as a second insulation layer have been introduced. In this method, the first and second insulation layers are etched by dry-etching.

However, while a silicon nitride layer is able to be dry-etched easily, a silicon oxide layer is not. This means that, as the first insulation layer4is etched, the photoresist layer used as a mask is hardened and thus is not easily removed in a stripping process subsequent to the etching process. Thus, photoresist residue remains as a foreign substance. The photoresist residue causes various connection problems between the TFT and other circuitry in the LCD.

In addition, because the etching speed of the second insulation layer6is different from that of the first insulation layer4, undercut of the first insulation layer4occurs when the first insulation layer is etched, and thus a stepped portion is again generated in the contact hole. When source and drain electrodes are formed using the contact holes having a stepped portion, connection problems between the source and drain electrodes and the TFT may occur.

BRIEF SUMMARY

A polysilicion liquid crystal display device and method for fabricating the same is provided. An active layer is formed on a substrate. A first insulation layer is formed on the active layer. A gate electrode is formed on the first insulation layer. A second insulation layer is formed on the gate electrode. A contact hole that exposes the active layer is formed in the second insulation layer. Source and drain electrodes are connected to the active layer through the contact hole. A pixel electrode is connected to the drain electrode.

The second insulation layer may contain porous silicon nitride in a single or multiple layer structure. The first insulation layer, as well as one of the layers of a multiple second insulation layer, may contain silicon oxide. The liquid crystal display device may be a transparent device, in which a backlight is used to illuminate the display, a reflective device in which ambient light is used to illuminate the display, or a transflective device in which the backlight and ambient light are used to illuminate the display. In the transflective device, a pixel electrode contains both a reflective electrode formed in a reflective region and a transparent electrode formed in a transparent region. The reflective electrode contains a reflective material that coats a passivation layer above the active layer, thereby protecting the active layer from external light. The transparent electrode contains a transparent material that partially overlaps the reflective electrode, and is formed under a portion of the passivation layer.

DETAILED DESCRIPTION

A fabrication method of a liquid crystal display device in accordance with the present invention prevents connection problems between the source and drain electrodes and the semiconductor due to a stepped portion in the contact hole by minimizing or eliminating the stepped portion.

Hereinafter, a fabrication method of a liquid crystal display device in accordance with a first embodiment of the present invention will now be described with reference toFIGS. 3A to 3F.

As shown inFIG. 3A, a buffer layer302is formed on a transparent substrate301by plasma enhanced chemical vapor deposition (PECVD). The buffer layer302is formed of, for example, silicon oxide (SiO2). After the buffer layer302is formed, an amorphous silicon layer is deposited onto the buffer layer302by PECVD. Then, the amorphous silicon layer is crystallized. The buffer layer302prevents diffusion of impurities present in the substrate301to an active layer during crystallization of the amorphous silicon.

Furnace annealing and/or laser annealing may be used to crystallize the amorphous silicon layer. In furnace annealing, the amorphous silicon layer is crystallized by placing the amorphous silicon layer in a furnace of high temperature for a predetermined amount of time. Using laser annealing, the amorphous silicon layer is crystallized using a laser that generates a high temperature in the amorphous silicon layer for a short period of time.

After the amorphous silicon layer is crystallized by one of the above-described methods, the crystallized amorphous silicon layer is patterned into an active layer303. In the patterning process, a photoresist is provided to the amorphous silicon layer. A mask is then arranged on the substrate containing the photoresist and the photoresist is then exposed through the mask. After exposure, the photoresist is developed and subsequently etched, to thereby form an active layer303.

After active layer of crystalline silicon, for example, polysilicon is formed, a first insulation layer304is formed on the active layer303. The first insulation layer304is a gate insulation layer formed from an inorganic material such as silicon oxide. The first insulation layer304electrically insulates a gate electrode formed on the active layer303from the active layer303.

A gate electrode305is formed on the first insulation layer304using a photolithographic process. The gate electrode305contains one or more conductive layers. For example, a single layer gate electrode may contain an aluminum alloy. Similarly, a multiple layer gate electrode includes two or more layers, one of which contains an aluminum alloy and another of which contains molybdenum to improve ohmic contact with the material used to form the pixel electrode discussed below. The photolithographic process for forming the gate electrode305is similar to that above. A metal layer is formed on the first insulation layer304by sputtering. A photoresist is then applied over the metal layer and exposed using a mask. The exposed photoresist is developed to form a gate pattern. The metal layer is then etched using the photoresist pattern as a mask and the photoresist pattern subsequently removed.

After the gate electrode305is formed, impurities (also referred to as impurity ions) of high concentration are injected in the active layer303to form a source and drain region303a,303busing the gate electrode305as a blocking mask. A high concentration of impurities is injected into the active layer303. The ions injected form the source and drain regions and also permit the source and drain electrodes to have ohmic contact with the active layer. Group3ions such as boron or the like may be injected into the active layer303in order to form a P-type thin film transistor, and group5ions such as phosphorus or the like may be injected into the active layer in order to form an N-type thin film transistor. Next, a second insulation layer306is formed on the gate electrode305. The second insulation layer306contains one or more inorganic layers. For example, a single layer structure may be formed using silicon nitride, while a multiple layer structure may be formed using a silicon oxide layer and a silicon nitride layer.

Using a silicon nitride layer in the second insulation layer306allows the capacitance of a storage region (not shown) to be increased compared with using a structure containing solely silicon oxide as the dielectric constant of silicon nitride is greater than that of silicon oxide. This means that a multiple layer structure containing the silicon oxide layer and the silicon nitride layer can achieve a desired capacitance and insulation by controlling the thickness of the layers. In addition, considering etching speeds of a silicon nitride layer of the second insulation layer306and a silicon oxide layer of the first insulation layer304, a thickness of a silicon oxide layer of the second insulation layer306can be controlled.

In addition, as hydrogen ions are present when the silicon nitride layer of the second insulation layer306is formed, the polysilicon active layer303may be hydrogenated by these hydrogen ions. Hydrogenation restores the active layer303, which is damaged during formation of the active layer303as well as subsequent layers. In particular, hydrogenation passivates dangling bonds that are present at a surface of the active layer.

The silicon nitride layer formed by deposition using a plasma including N2gas of about 1700 sccm to 2300 sccm (sccm: standard cubic centimeters per minute), NH3gas of about 600 to 800 sccm and SiH4 gas of about 130 to 150 sccm under conditions of voltage of about 1500 to 1700 watt and pressure of about 1400 to 1600 mTorr. Particularly, the silicon nitride layer may be formed using a plasma including N2gas of about 2000 sccm, NH3gas of about 700 sccm and SiH4 gas of about 140 sccm under conditions of voltage of about 1650 watt and pressure of about 1500 mTorr.

A silicon nitride layer formed under the above conditions has a porous structure. This porous silicon nitride layer has an etch rate when wet-etched of about 10 to 15 Å per second, which is similar to or faster than about 10 Å per second, the etch rate of the silicon oxide layer. Therefore, even if a silicon nitride layer formed under such conditions and a silicon oxide layer are simultaneously etched, undercutting can be prevented at an interface between the silicon nitride layer and the silicon oxide layer, thereby preventing generation of a stepped portion in a contact hole formed through the interface between the layers.

After the second insulation layer306is formed, as shown inFIG. 3D, contact holes307aand307bat the second insulation layer306are formed. In the present embodiment, the contact hole is formed through wet-etching. As shown inFIG. 3D, photoresist350is applied over the second insulation layer306, a mask (not shown) is arranged on the photoresist, and then a photoresist pattern including a contact hole pattern is formed through exposure and development of the photoresist. After the photoresist pattern is formed, the second insulation layer306and the first insulation layer304formed on the active layer303are etched in turn through a wet-etching process by using the photoresist pattern as an etching mask, to thereby form contact holes307aand307b.

Regions of the active layer303, where the contact holes307aand307bare formed are to be source and drain regions connected to source and drain electrodes. Even though the second insulation layer306is a silicon nitride layer, the second insulation layer306is wet-etched at a rate that is the same as or faster than the etch rate of the first insulation layer304, a silicon oxide layer, because of its porous structure. Accordingly, undercutting of the second insulation layer306does not occur when etching is performed at boundary portions of the second insulation layer306and the first insulation layer304. If the second insulation layer contains multiple layers including a silicon nitride layer and a silicon oxide layer, the silicon nitride layer and the silicon oxide layer are etched at their boundary portions at the same rate. Hence, in forming contact holes307aand307b, generation of a stepped portion of the first insulation layer306and the second insulation layer304due to undercutting can be prevented.

Next, as shown inFIG. 3E, the source and drain electrodes308and309are formed on the second insulation layer306having the contact holes307aand307b. In this process, a conductive layer is formed on the second insulation layer306and in the contact holes307aand307. The conductive layer is patterned through a photolithographic process, to thereby form source and drain electrodes308and309.

Next, as shown inFIG. 3F, a passivation layer310and a pixel electrode312are formed on the source and drain electrodes308and309. In this process, a passivation layer containing an inorganic material such as silicon nitride or an organic material such as Benzocyclobutene (BCB) is formed on the source and drain electrodes308and309, to thereby protect elements formed thereunder and simultaneously flatten the substrate. Next, a contact hole311is formed in one portion of the passivation layer310, thereby exposing the drain electrode309. After the contact hole311is formed in the passivation layer310, a transparent material for pixel electrode, such as an indium oxide (e.g. indium tin oxide, ITO, or indium zinc oxide, IZO), is deposited onto the passivation layer310and then patterned through a photolithographic process, to thereby form a pixel electrode312. Through this process, the pixel electrode312is connected to the drain electrode309through the contact hole311so as to receive a data signal.

During fabrication of the above polysilicon liquid crystal display device, because a silicon oxide layer is used as a gate insulation layer, and an insulation layer including a silicon nitride layer is used as an interinsulation layer on a gate electrode, a stepped portion is prevented from being generated in a contact hole due to different etch rates between a silicon nitride layer and a silicon oxide layer in when forming a contact hole by etching the gate insulation layer and the interinsulation layer. Hence, the stepped portion formed in a contact hole in a liquid crystal display device including a gate insulation layer which is a silicon oxide layer and an interinsulation layer including a silicon nitride layer may be prevented.

A process for fabricating a transreflective liquid crystal display device according to a second embodiment of the present invention will now be described with reference toFIGS. 4A to 4E.

In a process for fabricating a transreflective liquid crystal display device according to the second embodiment of the present invention, the process for forming the buffer layer302on a substrate to forming a second insulation layer306are the same as those of the embodiment described above with reference toFIG. 3A to 3C. After a second insulation layer306is formed on a gate electrode305, an indium oxide layer to be used as a pixel electrode is formed on the second insulation layer306.

Next, as shown inFIG. 4A, photoresist450is formed on the indium oxide layer, and diffractive exposure is performed on the photoresist450by using a diffractive mask. A thick layer of photoresist remains in a pixel region and is removed at a contact hole forming region. A thinner layer of photoresist remains in the non-pixel region, which includes the portion above the gate electrode.

FIG. 4Ashows a photoresist pattern450formed by diffractive exposure. Contact holes are formed to expose the source and drain regions by using the photoresist pattern450as an etching mask. That is, by using the photoresist pattern450as a etching mask, the indium oxide layer410, the second insulation layer306and the first insulation layer304on the source and drain regions are removed by wet-etching, thereby exposing the source and drain region of active layer303.

The second insulation layer306is formed by deposition using a plasma including N2gas of about 1700 sccm to 2300 sccm, NH3gas of about 600 to 800 sccm and SiH4 gas of about 130 to 150 sccm under conditions of a voltage of 1500 to 1700 watt and pressure of about 1400 to 1600 mTorr. Particularly, a silicon nitride layer may be formed using a plasma including N2gas of about 2000 sccm, NH3gas of about 700 sccm and SiH4 gas of about 140 sccm under conditions of a voltage of about 1650 watt and pressure of about 1500 mTorr. The second insulation layer formed under such conditions has a porous structure, and so its wet-etching rate is the same as or faster than that of the first insulation layer. Accordingly, undercutting of the first insulation layer304can be prevented from occurring at an interface between the silicon nitride layer and the silicon oxide layer, thereby preventing generation of a stepped portion in the contact hole.

After the contact holes307aand307bare formed, the photoresist pattern450is partially removed through ashing. Ashing is a method for removing the photoresist450by oxidizing the photoresist using a gas that includes an oxygen active species. This permits the diffractively-exposed photoresist on the region except the pixel region to be completely removed. After ashing, parts of the indium oxide layer are exposed.FIG. 4Bshows an exposed indium oxide layer above the gate electrode.

Next, as shown inFIG. 4C, the exposed indium oxide layer410is removed using the photoresist pattern450a, which remains in the pixel region after ashing, as an etching mask. The photoresist pattern450aabove the pixel region is removed after etching, thus forming the pixel electrode.

Next, as shown inFIG. 4D, a source and drain electrode are formed. That is, a conductive layer is formed in the contact holes307aand307band on the pixel electrode410and patterned through a photolithographic process, to thereby form source and drain electrodes308and309. The source electrode308is connected to the source region303through the contact hole307a, and the drain electrode309is connected to the drain region303and also to the pixel electrode410through the contact hole307b.

Then, as shown inFIG. 4E, an organic layer420containing BCB or photoacryl for example is applied over a reflective region, and a reflective electrode430containing a metal thin layer and connected to the drain electrode303bis formed thereon. The reflective electrode430is connected to the drain electrode303bthrough a contact hole440formed in the organic layer420over the drain electrode303band can receive a data voltage. The reflective electrode430operates as the pixel electrode in the reflective region of a unit pixel region, while the indium oxide layer410operates as the pixel electrode in a transparent region. The reflective electrode430in the reflective region and the indium oxide layer410operates in a transparent region drive a liquid crystal layer (not shown) thereabove.

AlthoughFIGS. 3 and 4show the second insulating layer as one layer, as discussed above, the second insulating layer may be a multiple layer structure. As an example,FIG. 5illustrates a portion of a second insulating layer500having a multiple layer structure (in this case a dual layer structure) on a first insulating layer506. The second insulating layer500has a porous silicon nitride layer502and a silicon oxide layer504. Although the porous silicon nitride layer502is shown as being more distal to the first insulating layer506than the silicon oxide layer504, the porous silicon nitride layer502can be more proximate to the first insulating layer506than the silicon oxide layer504.

As so far described, in forming a contact hole for connecting source and drain electrodes to source and drain regions, a contact hole without a stepped portion is formed to thereby prevent disconnection from occurring when a conductive layer is deposited in the contact hole. Accordingly, by preventing disconnection of a data line including a source electrode, line defects can be prevented. In addition, when the contact hole is formed, the second insulation layer and the first insulation layer are etched through the same wet-etching process so that the number of processes for forming a contact hole can be reduced.