Backlit photodiode and method of manufacturing a backlit photodiode

A backlit photodiode array includes a semiconductor substrate having first and second main surfaces opposite to each other. A first dielectric layer is formed on the first main surface. First and second conductive vias are formed extending from the second main surface through the semiconductor substrate and the first dielectric layer. The first and second conductive vias are isolated from the semiconductor substrate by a second dielectric material. A first anode/cathode layer of a first conductivity is formed on the first dielectric layer and is electrically coupled to the first conductive via. An intrinsic semiconductor layer is formed on the first anode/cathode layer. A second anode/cathode layer of a second conductivity opposite to the first conductivity is formed on the intrinsic semiconductor layer and is electrically coupled to the second conductive via.

BACKGROUND OF THE INVENTION

The present invention relates to a backlit photodiode array, and more particularly, to a backlit photodiode array formed on a silicon on insulator (SOI) substrate having backside contacts.

A photon detector or photodetector (also called a photodiode) is a semiconductor device that converts radiant power or light directly into electrical current. Positive-intrinsic-negative (PIN) diodes or PIN photodiodes are generally known in the art. A PIN/NIP diode is a form of photodetector.

A PIN diode is a type of photodiode with a large, neutrally doped intrinsic region sandwiched between p-doped and n-doped semiconducting regions. The PIN diode's name comes from the layering of the materials positive, intrinsic, negative (PIN). A PIN diode typically exhibits an increase in its electrical conductivity as a function of the intensity, wavelength, and/or modulation rate of the incident radiation.

A PIN diode also operates as a variable resistor at radiofrequency (RF) and microwave frequencies. The resistance value of the PIN diode is determined only by the forward biased direct current (DC) current. At high RF frequencies when a PIN diode is at zero or reverse bias, it appears as a parallel plate capacitor, essentially independent of reverse voltage.

Photoconductor arrays are groups of a plurality of photodetectors, such as PIN/NIP diodes, arranged together on a substrate or wafer.

It is desirable to provide a backlit photodiode array formed on a silicon on insulator (SOI) substrate having backside contacts.

BRIEF SUMMARY OF THE INVENTION

Briefly stated, an embodiment of the present invention comprises a photodiode that includes a semiconductor substrate having first and second main surfaces opposite to each other, a first dielectric layer formed on the first main surface, a first conductive via extending from the second main surface, and a second conductive via extended from the second main surface. The first conductive via extends through the semiconductor substrate and through the first dielectric layer. The first conductive via is isolated from the semiconductor substrate by a second dielectric material. The second conductive via extends through the semiconductor substrate and through the first dielectric layer. The second conductive via is isolated from the semiconductor substrate by the second dielectric material. The photodiode also includes a first anode/cathode layer formed on the first dielectric layer, an intrinsic semiconductor layer formed on the first anode/cathode layer, and a second anode/cathode layer formed on the intrinsic semiconductor layer. The first anode/cathode layer is electrically coupled to the first conductive via, and the first anode/cathode layer is of a first conductivity. The second anode/cathode layer is electrically coupled to the second conductive via, and the second anode/cathode layer is of a second conductivity opposite to the first conductivity.

Another embodiment of the present invention comprises a photodiode array that includes a silicon-on-insulator (SOI) substrate and a photodiode layer. The SOI substrate has first and second main surfaces opposite to each other and a dielectric layer proximate the first main surface. The photodiode layer is formed on the dielectric layer on the first main surface of the SOI substrate. The photodiode has a first anode/cathode layer proximate the dielectric layer and a second anode/cathode layer proximate an exposed surface of the photodiode. At least one anode/cathode via is formed in the photodiode layer proximate the second anode/cathode layer. The at least one anode/cathode via extends to the dielectric layer. First and second conductive vias extend from the second main surface of the SOI substrate and through the SOI substrate and the dielectric layer. The first conductive via is electrically coupled to the first anode/cathode layer and the second conductive via is electrically coupled to the second anode/cathode layer.

Still another embodiment of the present invention comprises a method of manufacturing a photodiode array including providing a silicon-on-insulator (SOI) substrate having first and second main surfaces opposite to each other. The SOI substrate has a dielectric layer proximate the first main surface. A photodiode layer is formed on the dielectric layer on the first main surface of the SOI substrate. The photodiode layer has a first anode/cathode layer proximate the dielectric layer and a second anode/cathode layer proximate an exposed surface of the photodiode. At least one anode/cathode trench is formed in the photodiode layer proximate the second anode/cathode layer. The at least one anode/cathode trench extends to the dielectric layer. Sidewalls of the at least one anode/cathode trench are doped. First and second via trenches extend from the second main surface of the SOI substrate and through the SOI substrate and the dielectric layer. A first conductive layer is formed in the first via trench. The first conductive layer is electrically coupled to the first anode/cathode layer. A second conductive layer is formed in the second via trench. The second conductive layer is electrically coupled to the second anode/cathode layer.

DETAILED DESCRIPTION OF THE INVENTION

Certain terminology is used in the following description for convenience only and is not limiting. The words “right”, “left”, “lower”, and “upper” designate directions in the drawings to which reference is made. The words “inwardly” and “outwardly” refer direction toward and away from, respectively, the geometric center of the object described and designated parts thereof. The terminology includes the words above specifically mentioned, derivatives thereof and words of similar import. Additionally, the word “a” as used in the claims and in the corresponding portion of the specification, means “at least one.”

As used herein, reference to conductivity will be limited to the embodiment described. However, those skilled in the art know that p-type conductivity can be switched with n-type conductivity and the device would still be functionally correct (i.e., a first or a second conductivity type). Therefore, where used herein, the reference to n or p can also mean that either n and p or p and n can be substituted therefor.

Furthermore, n+and p+refer to heavily doped n and p regions, respectively; n++and p++refer to very heavily doped n and p regions, respectively; n−and p−refer to lightly doped n and p regions, respectively; and n−−and p−−refer to very lightly doped n and p regions, respectively. However, such relative doping terms should not be construed as limiting.

Referring to the drawings in detail, wherein like numerals reference indicate like elements throughout, there is shown inFIG. 1a photodiode array, generally10, including several photodiodes12, in accordance with a preferred embodiment of the present invention.

Each photodiode12includes a semiconductor substrate20having first and second main surfaces20aand20bopposite to each other, a first dielectric layer22formed on the first main substrate surface20a, a first conductive via34, and a second conductive via36. The first conductive via34extends from the second main surface20bthrough the semiconductor substrate20and through the first dielectric layer22. The first conductive via34is isolated from the semiconductor substrate20by a second dielectric material38. The second conductive via34also extends from the second main surface20bthrough the semiconductor substrate20and through the first dielectric layer22. The second conductive via34is similarly isolated from the semiconductor substrate20by the second dielectric material38. The photodiode12also includes a first anode/cathode layer24formed on the first dielectric layer22and a second anode/cathode layer32formed on an intrinsic semiconductor layer26. The first anode/cathode layer24is electrically coupled to the first conductive via34, and is of a first conductivity. The second anode/cathode layer32is electrically coupled to the second conductive via36, and is of a second conductivity opposite to the first conductivity. More particularly, the photodiode array10includes a silicon-on-insulator (SOI) substrate20. The SOI substrate20has a dielectric layer22proximate the first main surface20a. A photodiode layer14is formed on the dielectric layer22on the first main surface20aof the SOI substrate20. The photodiodes12each have a first anode/cathode layer24proximate the dielectric layer22and a second anode/cathode layer32proximate an exposed surface26aof the intrinsic semiconductor layer26. At least one anode/cathode via28is formed in each photodiode12proximate the respective second anode/cathode layer32. The anode/cathode via28extends to the dielectric layer22of the SOI substrate20. A plurality of first and second conductive vias34and36are formed in the second main surface20bof the SOI substrate20. The first and second conductive vias34and36extend through the SOI substrate20and the dielectric layer22. Each of the first conductive vias34is electrically coupled to each respective first anode/cathode24and the second conductive via36is electrically coupled to the second anode/cathode32.

It should be noted that the first conductivity can be one of p-type and n-type and the second conductivity can be the other one of p-type and n-type without departing from the invention. The photodiodes12in the array10may be, for example, positive-intrinsic-negative (PIN) diodes or negative-intrinsic-positive (NIP) diodes without departing from the invention. Preferably, the semiconductor substrate20is formed of silicon (Si). But, the semiconductor substrate20may be formed of other materials such as gallium arsenide (GaAs), germanium (Ge) or the like.

Generally, if a semiconductor crystal contains no impurities, the only charge carriers present are those produced by thermal breakdown of the covalent bonds and the conducting properties are characteristic of the pure semiconductor material. Such a crystal is termed an “intrinsic” semiconductor. When used with reference to a PIN or NIP diode, conventional usage in the art includes lightly doped intrinsic areas. While used herein to refer to the semiconductor substrate or substrate/epitaxial layer as “intrinsic”, the present invention recognizes that a photodiode array in accordance with the present invention will work comparably with undoped substrates even when the semiconductor substrate has been lightly doped or even more heavily doped. Accordingly, the term “intrinsic” should not be construed as limiting and the present invention can embrace pure and doped semiconductor substrates formed of various materials.

Preferably, as shown inFIG. 8, the photodiode array10includes a plurality of anode/cathode vias28formed in the exposed surface26aand a plurality of adjacent anodes/cathodes32defined by the anode/cathode vias28. The plurality of anodes/cathodes32may be associated with pixels of an image when the photodiode array10is used in an imaging application such as X-ray or computed tomography (CT) imaging.

Referring again toFIG. 1, the photodiode array10also includes backside contacts40and42formed on or in contact with the first and second conductive vias34and36proximate the second main substrate surface20b.

FIGS. 2-7depict one possible method of manufacturing the photodiode array10. The method includes providing a silicon-on-insulator (SOI) substrate20having first and second main surfaces20aand20bopposite to each other, as shown inFIG. 2. The SOI substrate20has a dielectric layer22proximate the first main surface20a. Referring toFIG. 3A, a first anode/cathode layer24is formed on the dielectric layer22on the first main surface20aof the SOI substrate20. An intrinsic semiconductor layer26is then formed on the first anode/cathode layer24. As shown inFIG. 3B, at least one anode/cathode trench, and preferably a plurality of spaced apart anode/cathode trenches28′ are formed in the intrinsic semiconductor layer26proximate an exposed surface26a. The at least one anode/cathode trench28′ extends through the first anode/cathode layer to the dielectric layer22.

Referring toFIG. 4A, sidewalls28aand28bof the at least one anode/cathode trench28′ are doped with a dopant having a conductivity opposite to the conductivity of the first anode/cathode layer24. Referring toFIG. 4B, the anode/cathode trenches28′ may optionally be refilled with an undoped polysilicon30to form anode/cathode via28. The exposed surface26aand anode/cathode via28can then be planarized to remove excess polysilicon. As shown inFIG. 5A, the exposed surface26ais doped to form a second anode/cathode layer32. The dopant is of a conductivity opposite to the conductivity of the first anode/cathode layer24. It should be noted that the second anode/cathode layer32can also be formed before the via trenches28′ are formed.

SOI substrate20may be thinned as desired to minimize etch time of via trenches34′ and36′ described below. However, SOI substrate20should remain thick enough to maintain sufficient strength. Referring toFIG. 5B, first and second via trenches34′ and36′ are formed in the second main surface of the SOI substrate20. The first and second via trenches34′ and36′ extend through the SOI substrate20to the dielectric layer22.FIG. 6shows that the sidewalls of via trenches34′ and36′ are optionally lined with a dielectric material38, such as an oxide. The via trenches34′ and36′ may then be etched through the first dielectric22to the first anode/cathode layer24as shown inFIG. 6B. Note that trenches34′ abut the first anode/cathode layer24while trenches36′ abut one of the anode/cathode vias28. Referring toFIG. 7, a first conductive layer39is formed in the first via trench34′. The first conductive layer39is electrically coupled to the first anode/cathode24. A second conductive layer41is formed in the second via trench36′. The second conductive layer41is electrically coupled to the second anode/cathode32. Deposition of metal/metal silicide layers39and41may serve both as the conductive vias34and36and the backside contact pads40and42.

Referring toFIG. 8, the anode/cathode vias28also serve to isolate the photodiodes12from one another. As an alternative to trenching for isolation, doped isolation regions may be utilized. The exposed surface26aof the photodiode array10is selectively masked in order to dope the surface26awith a second dopant of a third conductivity. The doped isolation regions (in place of vias28) extend from the exposed surface28to at least the first main surface20aof the semiconductor substrate20.

The surfaces of the semiconductor substrate20and/or the intrinsic semiconductor layer26may be smoothed, if needed, using one or more of the following process steps:(i) an isotropic plasma etch may be used to remove a thin layer of silicon (typically 100-1000 Angstroms (Å)) from the trench surfaces;(ii) a sacrificial silicon dioxide layer may be grown on the surfaces of the trench and then removed using an etch such as a buffered oxide etch or a diluted hydrofluoric (HF) acid etch.
The use of either or both of these techniques can produce smooth trench surfaces with rounded corners while removing residual stress and unwanted contaminates. However, where it is desirable to have vertical sidewalls and square corners, an anisotropic etch process will be used instead of the isotropic etch process discussed above. Anisotropic etching, in contrast to isotropic etching, generally means different etch rates in different directions in the material being etched.

Doping is performed by one of ion implantation, solid diffusion, liquid diffusion, spin-on deposits, plasma doping, vapor phase doping, laser doping or the like. Doping with boron B results in a more p-type region, doping with phosphorus P results in a more n-type region and doping with arsenic Ar results in a more n-type region. Other dopants may be utilized such as antimony Sb, bismuth Bi, aluminum Al, indium In, gallium Ga or the like depending on the material of the intrinsic semiconductor layer26and the desired strength of the doping.

The dopants may be applied by diffusion. The intrinsic semiconductor layer26is placed in a suitable diffusion chamber at about 700° C. to about 1200° C. proximate to a solid source such as boron or phosphorous. Alternatively, the intrinsic semiconductor layer26can be exposed to a liquid source of dopant at about 700° C. to about 1200° C.

Alternatively, the dopants may be implanted. The intrinsic semiconductor layer26is implanted with boron B, phosphorus P, arsenic As or the like, at a high energy level in the range of about 40 to 1000 kilo-electronvolts (KeV). Preferably, the energy level is in the range of about 200 to 1000 KeV, but it should be recognized that the energy level should be selected to sufficiently implant the dopant. The second dopant may be boron B, phosphorus P, arsenic Ar or the like. The second anode/cathode layer is the first conductivity. Another drive in step at a temperature of up to 1200° Celsius may be performed for up to 12 hours so that implanted dopant is sufficiently driven into the substrate.

Backside contacts40or42are formed by sputtering, evaporation and/or electroplating, resulting in the photodiode array10shown inFIG. 1. The contacts40and42may be a metal such as aluminum Al, aluminum silicon Al[% Si], copper Cu, gold Au, silver Ag, titanium Ti, tungsten W, nickel Ni or the like and combinations thereof or may be doped or undoped polysilicon. The contacts40and42may also be layers of differing metals.

Other processing steps, as are known in the art, may be utilized without departing from the invention.

The bonding process may include annealing the substrates in an annealing furnace at up to 1200° C. for a period of about a few minutes to six hours. Optionally, the bonding steps may include wetting the surfaces of the silicon substrates with a solution such as water (H2O) and hydrogen peroxide (H2O2) and then pressing the wetted silicon substrates together and drying them prior to annealing at 800-1200° C. Plasma etches are used to remove impure oxides on the surfaces of the silicon substrates to be bonded. All of the other processing steps are then performed to form the photodiode array.

Another method of manufacturing a photodiode array10in accordance with a second preferred embodiment of the present invention includes providing a semiconductor substrate20having first and second main surfaces20aand20bopposite to each other. An oxide layer22is formed on the first main surface20aof the semiconductor substrate20. An epitaxial layer24of the first conductivity is deposited or grown on the oxide layer22on the first main surface20aof the semiconductor substrate20. The epitaxial growth or deposition may occur in a suitable reaction chamber at a temperature of up to about 1200° C. All of the other processing steps are then performed to form the photodiode array10.

Accordingly, a photodiode array10can be formed from a single substrate that is appropriately doped on both sides; can be formed from multiple substrates that are bonded together and appropriately doped; can be formed from a substrate with a epitaxial growth layer which is suitably doped; or can be formed from a substrate with an epitaxial growth layer wherein the substrate is appropriately doped.

From the foregoing, it can be seen that the present invention is directed to a backlit photodiode diode array formed on an SOI substrate with backside contacts and methods for manufacturing the same. It will be appreciated by those skilled in the art that changes could be made to the embodiments described above without departing from the broad inventive concept thereof. It is understood, therefore, that this invention is not limited to the particular embodiments disclosed, but it is intended to cover modifications within the spirit and scope of the present invention as defined by the appended claims.