System-on-chip and load imbalance detecting method thereof

A system-on-Chip (SoC) and a load imbalance detecting method of the same are provided. The SoC includes at least one master, a plurality of slaves, an interconnect, a measurement block, a central controller. The interconnect is configured to connect the at least one master and each of the plurality of slaves. The measurement block is configured to connect each of the plurality of slaves and the interconnect using a channel and to measure a load of each of the plurality of slaves. The central controller is configured to measure a load imbalance among the plurality of channels using the measured load information.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims priority under 35 U.S.C. § 119 to Korean Patent Application No. 10-2014-0028463, filed on Mar. 11, 2014 in the Korean Intellectual Property Office, the disclosure of which is incorporated by reference herein in its entirety.

TECHNICAL FIELD

Embodiments of the inventive concept relate to a System-on-Chip (SoC), and more particularly, to a circuit and method that detect load imbalance in the SoC.

DISCUSSION OF THE RELATED ART

A System-on-Chip (SoC) is a technique that integrates a complex system having various functions to a single semiconductor chip. Due to a convergence tendency that integrates a computer, communication, broadcast, etc., demands for Application Specific Integrated Circuit (ASIC) and Application Specific Standard Product (ASSP) move to the SoC.

The SoC includes Intellectual Property (IP) blocks. The IP blocks perform a specific function in the SoC. Generally, these IP blocks are connected through a bus.

An Advanced Microcontroller Bus Architecture (AMBA) of Advanced RISC Machine (ARM) company may be applied as an exemplary bus standard for connecting and managing the IP blocks. There are an Advanced High-Performance Bus (AHB), an Advanced Peripheral Bus (APB), an Advanced eXtensible Interface (AXI), etc., in a bus type of AMBA.

SUMMARY

Various exemplary embodiments of the inventive concept provide a system-on-chip (SoC) detecting a load imbalance.

Various exemplary embodiments of the inventive concept also provide a load imbalance detecting method of the SoC.

In accordance with one aspect of the inventive concept, the SoC is provided. The SoC includes at least one master, a plurality of slaves, an interconnect, a measurement block, and a central controller. The interconnect is configured to connect the at least one master and each of the plurality of slaves. The measurement block is configured to connect each of the plurality of slaves and the interconnect using a plurality of channels and to measure a load of each of the plurality of slaves. The central controller is configured to measure a load imbalance among the plurality of channels using the measured load information.

In an exemplary embodiment, the central controller may multiply a weight by each of a bandwidth, a latency, and an outstanding count with regard to each of the plurality of slaves, adds the multiplied results, and measures a load with regard to each of the plurality of slaves.

In an exemplary embodiment, the weight may include an importance with regard to each of the bandwidth, the latency, and the outstanding count.

In an exemplary embodiment, the central controller may calculate one of a minimum load value, a maximum load value, and a load variance with regard to a load of each of the plurality of slaves.

In an exemplary embodiment, the central controller may determine a load imbalance among the plurality of channels based on one of the minimum load value, the maximum load value, and the load variance.

In an exemplary embodiment, the at least one master may include an application processor, and the application processor may operate a dynamic voltage & frequency scaling (DVFS) based on one of the minimum load value, the maximum load value, and the load variance.

In an exemplary embodiment, the load of each of the plurality of slaves may be measured using a bandwidth, a latency, and an outstanding count with regard to each of the plurality of slaves.

In an exemplary embodiment, the interconnect may be redesigned based on the load imbalance information.

In an exemplary embodiment, each of the plurality of slaves may include a memory instance.

In an exemplary embodiment, the at least one master may transfer a request to one of the plurality of slaves, and a slave that receives the request may transfer a response corresponding to the request to the at least one master.

In accordance with an aspect of the inventive concept, a load imbalance detecting method of an SoC including at least one master, a plurality of slaves, and an interconnect that connects the at least one master and the plurality of slaves with each other is provided. The method includes measuring a load with regard to each of the plurality of slaves using a plurality of channels and measuring a load imbalance among the plurality of channels using the measured load information.

In an exemplary embodiment, the measuring of the load with regard to each of the plurality of slaves using the plurality of channels further may includes multiplying a weight by each of a bandwidth, a latency, and an outstanding count with regard to each of the plurality of slaves, adding the multiplied results with each other, and measuring the load with regard to each of the plurality of slaves based on the added results.

In an exemplary embodiment, the weight may include an importance of each of the bandwidth, the latency, and the outstanding count.

In an exemplary embodiment, the measuring of the load with regard to each of the plurality of slaves based on the added results may include calculating a minimum load value, a maximum load value, and a load variance with regard to the load of each of the plurality of slaves.

In an exemplary embodiment, the at least one master may include an application processor, and the method may further include performing a dynamic voltage & frequency scaling (DVFS) method based on the minimum load value, the maximum load value, and the load variance with regard to the load of each of the plurality of slaves by the application processor.

In accordance with an aspect of the inventive concept, a mobile device is provided. The mobile device includes a plurality of slaves, a plurality of masters, a plurality of channel efficiency enhancers, an interconnect, a plurality of measurement components, and a control controller. The plurality of masters is configured to generate requests with target addresses to access the plurality of slaves. The plurality of channel efficiency enhancers is configured to convert the target addresses received from the plurality of masters to access the plurality of slaves. The interconnect is configured to connect the at least one master and each of the plurality of slaves based on the converted target addresses. The plurality of measurement components is configured to measure loads of the plurality of slaves. The central controller is configured to measure a load imbalance information among the plurality of channels using the measured load information.

In an exemplary embodiment, the central controller may transmit the load imbalance information to at least one of the plurality of masters, the plurality of channel efficiency enhancers, and the interconnect.

In an exemplary embodiment, one of the plurality of channel efficiency enhancers may update an address conversion table to match the target addresses to the converted target addresses based on the load imbalance information.

In an exemplary embodiment, the load imbalance information may include a latency value, a bandwidth value, and an outstanding count value.

In an exemplary embodiment, the load imbalance information may further include weight values each of which corresponds to the latency value, the bandwidth value, and the outstanding count value.

DETAILED DESCRIPTION OF THE EMBODIMENTS

Various exemplary embodiments of the inventive concept are described below in sufficient detail to enable those of ordinary skill in the art to embody and practice the inventive concept. The inventive concept may be embodied in many alternative forms, and should not be construed as limited to the exemplary embodiments set forth herein.

It will be understood that, although the terms first, second, A, B, etc. may be used herein in reference to elements of the inventive concept, such elements should not be construed as limited by these terms. For example, a first element could be termed a second element, and a second element could be termed a first element, without departing from the scope of the inventive concept. Herein, the term “and/or” includes any and all combinations of one or more referents.

Embodiments of the inventive concept will be described below with reference to attached drawings.

FIG. 1shows a system-on-chip (SoC) according to an exemplary embodiment of the inventive concept.

Referring toFIG. 1, the SoC100according to an exemplary embodiment of the inventive concept includes first to third masters11to13, first to fourth slaves51to54, and an interconnect30configured to connect the first to third masters11to13and the first to fourth slaves51to54through a channel. The SoC100may be implemented with one package that is manufactured as a singular chip.

Further, each of the first to third masters11to13may be connected to each of the first to fourth slaves51to54through the channel.

The SoC100may further include a channel efficiency enhancement block20configured to connect each of the first to third masters11to13and the interconnect30to improve a channel efficiency of each of the first to third masters11to13. The SoC100may further include a measurement block40configured to measure a load of each of the first to fourth slaves51to54.

The channel efficiency enhancement block20includes a first channel efficiency enhancer21which is connected between the first master11and the interconnect30, a second channel efficiency enhancer22which is connected between the second master12and the interconnect30, and a third channel efficiency enhancer23which is connected between the third master13and the interconnect30.

The measurement block40includes a first measurement component41configured to measure a load of the first slave51, a second measurement component42configured to measure a load of the second slave52, a third measurement component43configured to measure a load of the third slave53, and a fourth measurement component44configured to measure a load of the fourth slave54.

In an exemplary embodiment, the load may be measured using a bandwidth, a latency, and an outstanding count.

Moreover, the SoC100further includes a central controller60configured to control the measurement block40. The central controller60receives load information with regard to first to fourth channels CH1to CH4from each of the first to fourth measurement components41to44. The central controller60may generate load imbalance information with regard to the first to fourth channels CH1to CH4using the load information. A system designer may reconfigure a system bus using the load imbalance information.

Further, when the SoC100is installed in a mobile device, one of the first to third masters11to13may be embodied in an application processor. The application processor may control an operation voltage and an operation clock frequency of the SoC100using a dynamic voltage & frequency scaling (DVFS) method based on the load imbalance information.

The interconnect30includes first to third slave interface units SI1to SI3and first to fourth master interface units MI1to MI4. Each of the first to third slave interface units SI1to SI3may be connected to one of the first to fourth slaves51to54. In addition, each of the first to fourth master interface units MI1to MI4may be connected to one of the first to third masters11to13.

The first slave interface unit SI1connects the first master11to one of the first to fourth slaves51to54. The second slave interface unit S12connects the second master12to one of the first to fourth slaves51to54. The third slave interface unit SI3connects the third master13to one of the first to fourth slaves51to54. The first to third slave interface units SI1to SI3are described with reference toFIGS. 2A to 2C.

The first master interface unit MI1connects the first slave51to one of the first to third masters11to13. The second master interface unit MI2connects the second slave52to one of the first to third masters11to13. The third master interface unit MI3connects the third slave53to one of the first to third masters11to13. In addition, the fourth master interface unit MI4connects the fourth slave54to one of the first to third masters11to13. The first to fourth master interface units MI1to MI4are described with reference toFIGS. 3A to 3D.

Each of the first to third masters11to13may be implemented as a microprocessor, a graphic processor, an Intellectual Property (IP) for designing an SoC, etc.

Further, the first master11may bypass the first channel efficiency enhancer21and be connected to the interconnect30. The first master11may access one of the first to fourth slaves51to54through the interconnect30.

For example, the first master11may transfer a request to the first slave51. When the first slave51receives the request output from the first master11through the interconnect30, the first slave51may transfer a response corresponding to the request to the first master11through the interconnect30.

An index may indicate a load of the interconnect30. The index may include at least one of a latency, a bandwidth, and an outstanding count. The SoC may detect the load of one of the first to fourth slaves51to54, for example, one of memory instances based on the index.

The first master11may transfer a request to one of the first to fourth slaves51to54through the interconnect30. Here, a signal path that transfers the request is referred to as a channel.

The first measurement component41may measure at least one of the latency, the bandwidth, and the outstanding count with regard to the first master11and the first slave51based on the request transferred from the first master11and the response transferred from the first slave51.

The bandwidth can be defined as an amount of transferred data during a unit of time. Bit per second (bps) may be used as the unit of the bandwidth. For example, the bandwidth means a number of bits of data transferred during 1 second. The latency can be defined a time interval between outputting a command to a slave by a master to responding to the command by the slave. The outstanding count can be defined as a number of requests that are newly requested before a previous work is completed. A method of measuring the outstanding count is described with reference toFIG. 4.

In an exemplary embodiment, the interconnect30is implemented according to an Advanced eXtensible Interface protocol of Advanced Microcontroller Bus Architecture 3 (AMBA3) or AMBA4 by ARM™.

Each of the first to fourth slaves51to54may be embodied in a memory controller, a display device, an image sensor, etc.

Further, each of the first to fourth slaves51to54may be implemented with an IP for designing an SoC.

The SoC100may be implemented with an integrated circuit. Further, the SoC100may be embedded in a mobile communication device such as a mobile phone, a smartphone, a tablet personal computer (PC), or personal digital assistant (PDA). In an exemplary embodiment, the SoC100may be embedded in an information technology device or a portable electronic device.

Each of the three indexes, e.g., the bandwidth, the latency, and the outstanding count may have an independent value. The SoC100may take into account the bandwidth, the latency, and the outstanding count as a whole to evaluate the load of one of the first to fourth slaves51to54.

A load of each of the plurality of slaves may be calculated using a method of multiplying a coefficient (e.g., a weight) to each of the three indexes and adding the multiplied results.

A system designer may check a load imbalance of the interconnect30using the load information. The system designer may check the load imbalance of the interconnect30in real time.

FIGS. 2A to 2Care block diagrams illustrating a slave interface unit shown inFIG. 1.

Referring toFIGS. 1 and 2A, the first master11transfers a request to the first slave interface unit SI1through the first channel efficiency enhancer21. The first slave interface unit SI1transfers the request to one of the first to fourth master interface units MI1to MI4. In an exemplary embodiment, the first slave interface unit SI1may be implemented with a decoder.

Referring toFIGS. 1 and 2B, the second master12transfers a request to the second slave interface unit SI2through the second channel efficiency enhancer22. The second slave interface unit SI2transfers the request to one of the first to fourth master interface units MI1to MI4. In an exemplary embodiment, the second slave interface unit SI2may be implemented with a decoder.

Referring toFIGS. 1 and 2C, the third master13transfers a request to the third slave interface unit SI3through the third channel efficiency enhancer23. The third slave interface unit SI3transfers the request to one of the first to fourth master interface units MI1to MI4. In an exemplary embodiment, the third slave interface unit SI3may be implemented with a decoder.

FIGS. 3A to 3Dare block diagrams illustrating a master interface unit shown inFIG. 1.

Referring toFIGS. 1 and 3A, the first master interface unit MI1may connect one of the first to third slave interface units SI1to SI3to the first measurement component41. In an exemplary embodiment, the first master interface unit MI1may be implemented with an arbiter.

Referring toFIGS. 1 and 3B, the second master interface unit MI2may connect one of the first to third slave interface units SI1to SI3to the second measurement component42. In an exemplary embodiment, the second master interface unit MI2may be implemented with an arbiter.

Referring toFIGS. 1 and 3C, the third master interface unit MI3may connect one of the first to third slave interface units SI1to SI3to the third measurement component43. In an exemplary embodiment, the third master interface unit MI3may be implemented with an arbiter.

Referring toFIGS. 1 and 3D, the fourth master interface unit MI4may connect one of the first to third slave interface units SI1to SI3to the fourth measurement component44. In an exemplary embodiment, the fourth master interface unit MI4may be implemented with an arbiter.

FIG. 4is a conceptual diagram for describing an outstanding count.

Referring toFIGS. 1 and 4, a first graph g1shows a request of the first master11according to an increase of time. A second graph g2shows a response of the first slave51according to an increase of time.

In a time t1, the first master11transfers a first request reg1to the first slave51through the interconnect30. Here, the outstanding count is 1.

In a time t2, the first master11transfers a second request req2to the first slave51through the interconnect30. Here, the outstanding count is 2.

In a time t3, the first master11transfers a third request req3to the first slave51through the interconnect30. Here, the outstanding count is 3.

In a time t4, the first master11transfers a fourth request req4to the first slave51through the interconnect30. Here, the outstanding count is 4.

In a time t5, the first slave51transfers a first response rest corresponding to the first request reg1to the first master11through the interconnect30. Here, the outstanding count is 3.

In a time t6, the first slave51transfers a second response res2corresponding to the second request req2to the first master11through the interconnect30. Here, the outstanding count is 2. For example, the outstanding count increases by 1, whenever the first master11transfers a request to the first slave51. The outstanding count decreases by 1, whenever the first slave51transfers a response to the first master11.

FIG. 5is a block diagram illustrating the SoC shown inFIG. 1.

Referring toFIGS. 1 and 5, the SoC100includes a plurality of masters11to13, a plurality of channel efficiency enhancer21to23, an interconnect30, a measurement block40having a plurality of measurement component41to44, a central controller60, and a plurality of slaves M1to M4.

The performance of the SoC100may be evaluated according to a processing speed of a bulk of multimedia data. The data processing speed of the SoC100may depend on how fast the SoC100processes data traffic between the first to fourth slaves51to54, for example, memories and the first to third masters11to13, for example, the internal IP in the SoC100. If traffics are concentrated in a certain slave, a bandwidth provided by the interconnect30may decrease.

The plurality of channel efficiency enhancers21to23are connected respectively between the plurality of masters11to13and the interconnect30. Each of the plurality of channel efficiency enhancer21to23may receive a read request or a write request with a target address from its corresponding master out of the masters11to13to access one of memories M1to M4through the slaves channels CH1to CH4. The first channel efficiency enhancer21may receive load imbalance information from the central controller60.

The plurality of channel efficiency enhancers21to23may change the received target address based on the received load imbalance information and distribute loads of each of the slave channels CH1to CH4. An address conversion table to match the received target address from the first master11to a converted target address may be stored in one of the memories M1to M4. For example, the plurality of channel efficiency enhancers may update an address conversion table to match the target addresses with the converted target addresses based on the load imbalance information.

The interconnect30may receive the read request or write request with the converted target address and arbitrate the read/write requests based on the load imbalance information and may change the order of responses to the read/write requests received from the plurality of masters11to13through the plurality of channel efficiency enhancers21to23. Accordingly, the interconnect30may avoid a load imbalance occasion and meet a bandwidth requirement.

Each of the first to fourth slaves51to54shown inFIG. 1may include one of the first to fourth memory instances M1to M4. In an exemplary embodiment, each of the first to fourth memory instances M1to M4may be implemented with a Dynamic Random Access Memory (DRAM) memory device.

Referring toFIG. 5, the first master11may access one of the first to fourth memory instances M1to M4through the interconnect30. For example, if the first master11accesses the first memory instance M1through the interconnect30, the first measurement component41measures a load of the first memory instance M1.

The first measurement component41may measure a bandwidth, a latency, and an outstanding count of the first channel CH1using the request from the first master11and the response from the first memory instance M1. Here, the traffic of the first channel CH1may be higher than that of each of the second to fourth channels CH2to CH4. For example, if the traffic is concentrated to the first memory instance M1, a bandwidth provided by the interconnect30and a latency provided to the first master11may be reduced.

Moreover, the second measurement component42may measure a bandwidth, a latency, and an outstanding count of the second channel CH2using the request from the second master12and the response from the second memory instance M2.

Further, the third measurement component43may measure a bandwidth, a latency, and an outstanding count of the third channel CH3using the request from the third master13and the response from the third memory instance M3.

Likewise, the fourth measurement component44may measure a bandwidth, a latency, and an outstanding count of the fourth channel CH4using the request from the fourth master14and the response from the fourth memory instance M4.

A method of increasing a bandwidth is to lower the difference of a load among the memory instances. When a SoC includes conventional IPs such as CCI-400 of ARM company, NOC of Arteris company, etc., to distribute a traffic, generality and compatibility may cause a problem only to use a data address for traffic distribution. Accordingly, an SoC designer adds a traffic distribution circuit to the IPs to solve the problem of traffic distribution.

In addition, to raise a traffic distribution effect by the interconnect30, an address transformation device may be added to input channels and output channels of the interconnect30.

To identify whether the traffic distribution circuit precisely operates, a method of measuring a load of channels is required.

To meet this requirement, the SoC100according to an exemplary embodiment of the inventive concept may detect a load imbalance among the channels. The load imbalance can be evaluated based on the three indexes, e.g., a latency, a bandwidth, and an outstanding count on each channel CH1to CH4connected to one of the first to fourth slaves51to54. The central controller60may multiply a weight to each of the bandwidth, the latency, and the outstanding count, calculate a load of each of the first to fourth slaves51to54by adding the multiplied results, and determine the load imbalance among the channels CH1to CH4connected to the first and fourth slaves51to54.

The central controller60may calculate one of a minimum load value, a maximum load value, a mean load value, and a load variance of a load corresponding to each of the first to fourth slaves51to54. The central controller60may determine a load imbalance among the first to fourth channels CH1to CH4based on one of the minimum load value, the maximum load value, the mean load value, and the load variance of a load corresponding to each of the first to fourth slaves51to54.

A method of calculating the minimum load value, the maximum load value, the mean load value, and the load variance of a load of each of the first to fourth slaves51to54is described with reference to Equations 1 to 4.

Equation 1 is a formula that calculates the minimum load value (Cmin) among the first to fourth channels CH1to CH4.
Cmin=min(CH1·W1*L+CH1·W2*B+CH1·W3*M,CH2·W1*L+CH2·W2*B+CH2·W3*M,CH3·W1*L+CH3·W2*B+CH3·W3*M,CH4·W1*L+CH4·W2*B+CH4·W3*M)  [Equation 1]

Here, W1is a weight for a latency (L), W2is a weight for a bandwidth (B), and W3is a weight for an outstanding count (M). The min function outputs the minimum load value among weighted combination values based on the indexes which correspond to the slave channels CH1to CH4.

The central controller60may calculate the minimum load value (Cmin) with regard to a load of each of the first to fourth slaves51to54using Equation 1.

Equation 2 is a formula that calculates the maximum load value (Cmax) among the first to fourth channels CH1to CH4.
Cmax=max(CH1·W1*L+CH1·W2*B+CH1·W3*M,CH2·W1*L+CH2·W2*B+CH2·W3*M,CH3·W1*L+CH3·W2*B+CH3·W3*M,CH4·W1*L+CH4·W2*B+CH4·W3*M)  [Equation 2]

The max function outputs the maximum load value among weighted combination values based on the indexes which correspond to the slave channels CH1to CH4. The central controller60may calculate the maximum load value (Cmax) with regard to a load of each of the first to fourth slaves51to54using Equation 2.

Equation 3 is a formula that calculates the mean load value (Cavg) among the first to fourth channels CH1to CH4.
Cavg=avg(CH1·W1*L+CH1·W2*B+CH1·W3*M,CH2·W1*L+CH2·W2*B+CH2·W3*M,CH3·W1*L+CH3·W2*B+CH3·W3*M,CH4·W1*L+CH4·W2*B+CH4·W3*M)  [Equation 3]

The avg function outputs the average load value among weighted combination values based on the indexes which correspond to the slave channels CH1to CH4. The central controller60may calculate the mean load value (Cavg) with regard to a load of each of the first to fourth slaves51to54using Equation 3.

Equation 4 is a formula that calculates the load variance (Cvar) among the first to fourth channels CH1to CH4.
Cvar=var(CH1·W1*L+CH1·W2*B+CH1·W3*M,CH2·W1*L+CH2·W2*B+CH2·W3*M,CH3·W1*L+CH3·W2*B+CH3·W3*M,CH4·W1*L+CH4·W2*B+CH4·W3*M)  [Equation 4]

The var function outputs the load variance among weighted combination values based on the indexes which correspond to the slave channels CH1to CH4. The central controller60may calculate the load variance (Cvar) with regard to a load of each of the first to fourth slaves51to54using Equation 4.

The central controller60may notify that a load imbalance occurs when one of the minimum load value, the maximum load value, the mean load value, and the load variance with regard to a load of each of the first to fourth slaves51to54exceeds an imbalance threshold.

For example, when the first master11is an application processor, the central controller60may notify at least one of the application processor, the channel efficiency enhancer21and the interconnect30of the occurrence of a load imbalance when the load of a slave channel that the first master11accesses exceeds a threshold load value.

A DVFS operation by the application processor or an address translation operation by the interconnect30may be performed based on one of the minimum load value, the maximum load value, the mean load value, and the load variance with regard to a load of each of the first to fourth slaves51to54.

According to the access of at least one of the masters11to13, the central controller60may assign an appropriate value to the weight value corresponding to each load index based on the load imbalance information. When the load imbalance information is changed due to the change of access requests by at least one of the masters11to13, the central controller60may change the weight value on each index, (e.g. latency, bandwidth and outstanding count).

For example, when the number of requests by the masters11to13to access one of the memories M1to M4may increase the latency value in correspondence to the requests, the central controller60may detect the change of the latency value and receive load imbalance information from one of the measurement components41to44. The central controller60may detect that the load imbalance exceeds the maximum load imbalance (Cmax). Accordingly, one of the masters11to13may perform a DVFS operation, the channel efficiency enhancers21to23may perform an address change operation from a target address to a converted address, and the interconnect30may arbitrate requests from the masters11to13.

On the other hand, when the number of requests by the masters11to13to access one of the memories M1to M4can make at least one load of the memories M1to M4under the minimum load value, the central controller may notify at least one of the masters11to13, the channel efficiency enhancer21to23and the interconnect30of the change of the load imbalance information to. At this time, one of the channel efficiency enhancer21to23may update the address conversion table to assign different slave channel from the previous slave channel and the interconnect30may distribute the requests from one of the masters11to13to the slave channels CH1to CH2in a different pattern.

If the central controller60wants to detect the load imbalance in view of latency, the central controller60may increase the weight value for the latency index to avoid the load imbalance quickly.

As the number of requests by the masters11to13to access one of the memories M1to M4increases, the outstanding count value or the bandwidth value can increase.

If the central controller60wants to detect the load imbalance in view of the outstanding count, the central controller60may increase the weight value for the outstanding count index to avoid the load imbalance quickly.

Moreover, if the central controller60wants to detect the load imbalance in view of the bandwidth, the central controller60may increase the weight value for the bandwidth index to avoid the load imbalance quickly.

FIG. 6is a flowchart for describing a method of the SoC shown inFIG. 5.

Referring toFIGS. 5 and 6, in step S11, the measurement block40may measure a load of each of the plurality of slaves using the plurality of channels. For example, the first measurement component41measures a load of the first slave51through the first channel CH1, the second measurement component42measures a load of the second slave52through the second channel CH2, the third measurement component43measures a load of the third slave53through the third channel CH3, and the fourth measurement component44measures a load of the fourth slave54through the fourth channel CH4.

In step S12, the central controller60may measure a load imbalance among the plurality of channels using the measured load information. For example, the central controller60may obtain load information of each of the first to fourth channels CH1to CH4using the measured load information.

In S13step, the SoC may distribute loads among the slave channels CH1to CH4based on the load imbalance information. The channel utilization means a channel usage ratio in an allowed time period.

The SoC100may recognize a load imbalance among the first to fourth channels CH1to CH4using the minimum load value, the maximum load value, the mean load value, and the load variance. Accordingly, the system designer may redesign the system bus to balance a load among the first to fourth channels CH1to CH4.

FIG. 7is a block diagram illustrating an exemplary embodiment of a computer system210including the SoC shown inFIG. 1.

Referring toFIG. 7, the computer system210includes a memory device211, a memory controller212configured to control the memory device211, a radio transceiver213, an antenna214, an application processor215, an input device216, and a display unit217.

The radio transceiver213may transmit or receive a radio signal via the antenna214. For example, the radio transceiver213may transform the radio signal received via the antenna214to be processed by the application processor215.

Thus, the application processor215may process a signal output from the radio transceiver213, and transmit the processed signal to the display unit217. Also, the radio transceiver213may transform a signal output from the application processor215into a radio signal, and output the radio signal to an external device (not shown) via the antenna214.

The input device216is a device through which a control signal for controlling an operation of the application processor215or data that is to be processed by the application processor215is input. For example, the input device216may be embodied as a pointing device such as a touchpad, a computer mouse, a keypad, or a keyboard.

In an exemplary embodiment, the memory controller212configured to control an operation of the memory device211may be embodied as a part of the application processor215, or may be embodied as a chip installed separately from the application processor215.

In an exemplary embodiment, the application processor315may include the SoC100illustrated inFIG. 1.

FIG. 8is a block diagram illustrating an embodiment of a computer system220including the SoC shown inFIG. 1.

Referring toFIG. 8, the computer system220may be embodied as a PC, a network server, a tablet PC, a netbook, an e-reader, a personal digital assistant (PDA), a portable multimedia player (PMP), an MP3 player, or an MP4 player.

The computer system220includes a memory device221and a memory controller222configured to control data processing operations of the memory device221, an application processor223, an input device224, and a display unit225.

The application processor223may display data stored in the memory device221on the display unit225, based on data input through the input device224. For example, the input device224may be embodied as a pointing device such as a touchpad and a computer mouse, a keypad, or a keyboard. The application processor223may control overall operations of the computer system220and an operation of the memory controller222.

In an exemplary embodiment, the memory controller222configured to control an operation of the memory device221may be embodied as a part of the application processor223, or may be embodied as a chip installed separately from the application processor223.

In an exemplary embodiment, the application processor223may include the SoC100illustrated inFIG. 1.

FIG. 9is a block diagram illustrating an embodiment of a computer system230including the SoC shown inFIG. 1.

Referring toFIG. 9, the computer system230may be embodied as either an image processing device, e.g., a digital camera, or a mobile phone, a smartphone, or a tablet PC to which a digital camera is attached.

The computer system230includes a memory device231, and a memory controller232configured to control a data processing operation (e.g., a write or read operation) of the memory device231. The computer system230may further include an application processor233, an image sensor234, and a display unit235.

The image sensor234in the computer system230transforms an optical image into digital signals, and transmits the transformed digital signals to the application processor233or the memory controller232. Under control of the application processor233, the transformed digital signals may be displayed on the display unit235, or stored in the memory device231through the memory controller232.

Also, data stored in the memory device231may be displayed on the display unit235, under control of the application processor233or the memory controller232.

In an exemplary embodiment, the memory controller232configured to control an operation of the memory device231may be embodied as a part of the application processor233, or may be embodied as a chip installed separately from the application processor233.

In an exemplary embodiment, the application processor233may include the SoC100illustrated inFIG. 1.

The inventive concept may be applied to a mobile device or a computer system including an SoC.

The SoC according to an exemplary embodiment of the inventive concept may redesign a system bus or reduce a load of the SoC using load information which is measured from each of a plurality of memory instances.

The foregoing is illustrative of embodiments of the present inventive concept and is not to be construed as limiting thereof. Although a few embodiments have been described, those skilled in the art will readily appreciate that many modifications in form and detail may be possible therein without materially departing from the spirit and scope of the present inventive concept.