Method of forming infrared detector by hydrogen plasma etching to form refractory metal interconnects

A metal interconnect fabrication process for hybrid solid state systems such as thermal imaging system (50). A plurality of vias (62) are formed in a focal plane array (60) between the thermal sensors (20) to expose a corresponding array of contact pads (84) on a silicon processor (80) bonded to the focal plane array (60). A metal film layer (30) is disposed on the focal plane array (60) to fill the vias (62). Photoresist material (32) is patterned on the metal layer (30) to correspond with the desired sensor signal flow path. With the photoresist material (32) still in place, the metal layer (30) is dry etched to produce the desired metal interconnect pattern by removing portions of the metal layer (30) unprotected by the photoresist material (32).

TECHNICAL FIELD OF THE INVENTION 
This invention relates in general to semiconductor devices and more 
particularly to an infrared detector and method. 
BACKGROUND OF THE INVENTION 
For several years hybrid solid state system such as infrared detectors have 
been successfully incorporated into integrated circuits for mass 
production and miniaturization. Typically, such infrared detectors are 
fabricated in N.times.M arrays of infrared detector elements or thermal 
sensors. Each element in the array may itself be fabricated from 
semiconductor materials such as alloys of mercury, cadmium, and tellurium 
("HgCdTe") which are operable to generate electron-hole pairs when struck 
by infrared radiation. The particular wavelength from which each element 
generates electron-hole pairs may be tuned by adjusting the ratio of 
mercury to cadmium in the semiconductor material. Infrared detectors 
typically sense electromagnetic radiation having a wavelength, generally, 
between 0.5 and 15 .mu.m corresponding to an energy level of 2 to 0.1 eV. 
Common applications for thermal sensors include thermal (infrared) imaging 
devices such as night vision equipment or target acquisition and tracking 
systems. One such class of thermal imaging devices includes a focal plane 
array of infrared detector elements or thermal sensors coupled to an 
integrated circuit substrate or silicon processor with a plurality of vias 
extending between the focal plane array and the integrated circuit 
substrate. The thermal sensors define the respective picture elements (or 
pixels) of the resulting thermal image. Examples of such infrared 
detectors and associated vias or metal interconnects between thermal 
sensors in a focal plane array and a silicon processor are shown in U.S. 
Pat. No. 4,447,291 entitled Methods for Via Formation in HgCdTe, and U.S. 
Pat. No. 5,144,138 entitled Infrared Detector and Method. For some 
infrared detectors the metal interconnect pattern is formed by using metal 
lift off techniques with evaporated indium or indium/lead/indium metal 
films. 
SUMMARY OF THE INVENTION 
In accordance with the present invention, the disadvantages and problems 
associated with previous metal interconnect and via formation processes 
for fabrication of hybrid solid state systems have been substantially 
reduced or eliminated. The present invention allows fabricating a selected 
metal interconnect pattern to couple two or more substrates of a solid 
state system such as sensor signal flow paths between the focal plane 
array of an infrared detector and an associated silicon processor. 
One aspect of the present invention includes depositioning a metal film 
layer followed by a photoresist layer at selected locations and a dry etch 
to form the desired metal interconnects for electrically coupling thermal 
sensors in a focal plane array with a silicon processor substrate. Forming 
the metal film layer before applying the photoresist reduces potential 
surface contamination and minimizes the number of electrical shorts from 
incomplete metal bonding. 
An important technical advantage of the present invention includes using 
dry etching techniques to form the desired metal interconnects which 
improve the overall yield of the fabrication process. Also, the present 
invention allows using various metals and their alloys such as indium, 
lead, aluminum, titanium, tungsten or other refractory metals to form the 
desired metal interconnect pattern to provide a plurality of sensor signal 
flow paths from a focal plane array to a silicon processor substrate. 
Another aspect of the present invention includes fabricating a metal 
interconnect pattern between a focal plane array having a plurality of 
HgCdTe thermal sensors and an associated silicon processor using dry 
etching techniques. 
A further significant technical advantage of the present invention includes 
providing a positive image of the desired interconnect metal by forming 
vias in an array of HgCdTe thermal sensors, covering the thermal sensors 
and vias with a metal film layer and forming the desired metal 
interconnect pattern using dry etching techniques in accordance with the 
present invention.

DETAILED DESCRIPTION OF THE INVENTION 
The preferred embodiments of the present invention and its advantages are 
best understood by referring to FIGS. 1a through 8b of the drawings, like 
numerals being used for like and corresponding parts of the various 
drawings. 
Infrared detectors or thermal imaging systems are typically based upon 
either the generation of a change in voltage due to a change in 
temperature resulting from incident infrared radiation striking a thermal 
sensor, or the generation of a change in voltage due to a photoelectron 
interaction within the material used to form the thermal sensor. This 
latter effect is sometimes called the internal photoelectric effect. 
Thermal sensors or infrared detector elements 20, which incorporate the 
present invention and described later in more detail, function based on 
the generation of electron-hole pairs resulting from the internal 
photoelectric effect. 
The present invention may also be used to form metal interconnects 
associated with uncooled infrared detectors. Such detectors are typically 
formed with a plurality of thermal sensors (not shown) having 
ferroelectric elements which generate a change in voltage due to a change 
in temperature of the ferroelectric material resulting from incident 
infrared radiation. Such thermal sensors may be formed from barium 
strontium titanate or other suitable ferroelectric materials. As will be 
described later in more detail, the present invention allows fabricating a 
metal interconnect pattern for use in bump bonding ferroelectric thermal 
sensors with an integrated circuit substrate. 
Infrared detector or thermal imaging system 50 may be manufactured from 
semiconductor materials which are structured as photodiodes and/or 
photocapacitors. U.S. Pat. No. 4,447,291 entitled Methods for Via 
Formation in HgCdTe, and U.S. Pat. No. 5,144,138 entitled Infrared 
Detector and Method provide information concerning infrared detectors 
fabricated from HgCdTe semiconductor materials and alloys which produce 
electron-hole pairs in response to incident infrared radiation. U.S. Pat. 
Nos. 4,447,291 and 5,144,138 are incorporated by reference for all 
purposes in this application. 
FIGS. 1a through 4b are schematic representations of selected steps in the 
fabrication of infrared detector or thermal imaging system 50. Some of the 
principal components of thermal imaging system 50 include focal plane 
array 60 and integrated circuit substrate or silicon processor 80. As 
shown in FIGS. 1a, 2a, 3a and 4a, focal plane array 60 comprises a 
plurality of individual thermal sensors or infrared detector elements 20. 
Each infrared detector element 20 may be formed from several various types 
of material including semiconductor material such as HgCdTe which 
interacts with incident infrared radiation to produce electron-hole pairs. 
The various materials used to fabricate infrared detector elements 20 are 
typically deposited in a series of layers on a suitable substrate using 
lithographic techniques. For purposes of illustration and description, 
reference is made in FIGS. 1b, 2b, 3b and 4b to infrared detector elements 
20a and 20b. However, for thermal imaging system 50, all infrared detector 
elements 20 are generally identical. 
Each infrared detector element 20 is preferably disposed on planar surface 
82 of silicon processor 80 adjacent to a corresponding contact pad 84. Via 
62 is preferably provided between adjacent thermal sensors 20 to allow 
access to the associated contact pad 84. As will be explained later, via 
62 shown in FIG. 1b between thermal sensors 20a and 20b allows forming a 
sensor signal flow path between storage gate 22 of thermal sensor 20b and 
the associated contact pad 84. 
Silicon processor 80 is used to produce a thermal image based on incident 
infrared radiation striking infrared detector elements 20 in focal plane 
array 60. Infrared detector 50 will preferably include a plurality 
(N.times.M) of infrared detector elements 20 forming focal plane array 60 
bonded to silicon processor 80. Each infrared detector element 20 
corresponds to a picture element or pixel in the resulting infrared image 
produced by infrared detector 50. 
Various types of silicon processors and/or integrated circuit substrates 
may be satisfactorily used in manufacturing infrared detector 50. U.S. 
Pat. No. 4,684,812 entitled Switching Circuit for a Detector Array 
provides information concerning one type of silicon processor satisfactory 
for use with focal plane array 60. U.S. Pat. No. 4,684,812 is incorporated 
by reference for all purposes in this application. 
As shown in FIGS. 1a and 1b, focal plane array 60, includes a plurality of 
storage gates 22 which correspond respectively with infrared detector 
elements 20. Each storage gate 22 is preferable formed from metal such as 
nickel or tantalum which is relatively transparent to incident infrared 
radiation. Also, each storage gate 22 is preferably a thin strip of metal 
(often less than 100 angstroms thick) to further promote transparency with 
respect to incident infrared radiation. Each storage gate 22 and its 
associated infrared detector element 20 are separated from adjacent 
infrared detector elements 20 with no electrical contact therebetween. 
As shown in FIGS. 1b, 2b, 3b, and 4b, each infrared detector element 20 
comprises a plurality of layers of different materials which are disposed 
on planar surface 82 of silicon processor 80. Each infrared detector 
element 20 includes bar 24 of semiconductor material such as HgCdTe, which 
is sensitive to incident infrared radiation. In the chemical formula 
Hg.sub.1-x Cd.sub.x Te for bars 24, the values of x may be varied 
depending upon the desired sensitivity of the resulting thermal sensor 20 
to different wavelengths of incident infrared radiation. Each bar 24 may 
be mounted on surface 82 of silicon processor 80 using a suitable epoxy or 
other gluing compound. In FIGS. 1b, 2b, 3b, and 4b, the respective bars 24 
are shown attached to silicon processor 80 with epoxy layer 26. 
Silicon Processor 80 typically represents one or more chips fabricated on 
the surface of a semi-conductor wafer such as semi-conductor wafers 86 
shown in FIG. 5. A plurality of bars 24 may be mounted on one or more 
chips to form a plurality of infrared detectors 50 on each semi-conductor 
wafer 86. Vias 62 are formed between adjacent bars 24 corresponding with 
the location of each contact pad 84. U.S. Pat. 4,447,291 discloses one 
process for mounting bars 24 and forming vias 62. 
An insulating layer 28 of zinc sulphide (ZnS) is preferably disposed on 
each bar 24 to protect semiconductor material HgCdTe and to position each 
storage gate 22 with respect to its associated bar 24. Each via 62 
includes an opening through insulating layer 28 and epoxy layer 26 to 
allow access to the associated contact pad 84. Applying insulating layer 
28 also assists with maintaining the cleanliness of the exposed surfaces 
of focal plane array 60. The resulting intermediate structure formed 
during fabrication of infrared detector 50 is shown in FIGS. 1a and 1b. 
The following steps in the fabrication process are directed towards forming 
a metal interconnect pattern to provide a plurality of sensor signal flow 
paths from each storage gate 22 through its associated via 62 to the 
respective contact pad 84 on silicon processor 80. The resulting metal 
interconnects 34 may sometimes be referred to as "via interconnects," 
"metal connectors," or "metal strip conductors." 
The next step in the process is to place metal film layer 30 across the 
surface of focal plane array 60. Metal film layer 30 may be formed using 
sputter deposition techniques or other techniques appropriate for the 
material selected for layer 30. 
Prior fabrication processes often involved placing a layer of photoresist 
covering the focal plane array prior to forming the desired metal 
interconnect between each thermal sensor and its associated contact pad. 
Forming metal film layer 30 on focal plane array 60 prior to applying any 
photoresist material reduces potential surface contamination, increases 
the integrity of the metal bond with the respective storage gates 22 and 
contact pads 84. The number of electrical shorts resulting from incomplete 
bonding is substantially reduced by the use of metal film layer 30. 
The present invention allows selecting various metals and metal alloys to 
form metal film layer 30. Examples of the metal film layers which may be 
satisfactorily used with the present invention include indium (In), 
indium/lead/indium (In/Pb/In), aluminum (Al), or 
aluminum/titanium-tungsten (Al/TiW). The present invention may also be 
used to form interconnect patterns from refractory metals such as 
titanium, tungsten, titanium-tungsten alloys, tantalum, molybdenum and 
alloys such as titanium silicon (Ti.sub.4 Si.sub.3) and titanium nitride 
(TIN). 
For one embodiment of the present invention film layer 30 is preferably 
formed from indium. This intermediate structure associated with the 
fabrication of infrared detector elements 20 is shown in FIGS. 2a and 2b. 
The next step in the process is to pattern a layer of photoresist material 
32 at selected locations on metal film layer 30 as shown in FIGS. 3a and 
3b. The position of each photoresist layer 32 is selected to correspond 
with the desired location of each sensor signal flow path or metal strip 
conductor 34 between its associated storage gate 22 and contact pad 84. 
The following step is dry etching to remove the portions of metal layer 30 
which are not protected by photoresist layers 32. Following the dry etch, 
photoresist layers 32 are stripped away to leave metal strip conductors 34 
as shown in FIGS. 4a and 4b. Ashing or solvent stripping may be used as 
desired to remove photoresist layers 32. Metal strip conductors 34 are 
thus formed to extend from each storage gate 22 to the associated contact 
pad 84 and provide the desired sensor signal flow path. 
The dry etching process used to form metal strip conductors 34 from metal 
film layer 30 may be conducted in various types of reactors. An RF 
discharge parallel plate reactor 90 satisfactory for use with the present 
invention is shown in FIG. 5. One of the advantages of dry etching is that 
the process may be performed at a relatively low temperature (less than 
100.degree. C.) as compared to other methods of forming metal connectors. 
Reactor 90 includes housing 92 which contains chamber 94. Inlet 96 is 
provided to supply gas from a source (not shown) to chamber 94. Outlet 98 
is provided to connect chamber 94 with a pump or other means (not shown) 
to form a vacuum within chamber 94. A pair of parallel electrodes 100 and 
102 are disposed in chamber 94. RF power used to facilitate the dry 
etching process is supplied to upper electrode 100. Wafers 86 having a 
plurality of silicon processors 80 and associated infrared detectors 50 
formed on the surface of each wafer 86 are preferably placed on lower or 
ground electrode 102. 
Various types of etching gas may be satisfactorily used with the present 
invention. The selection of etching gas is dependent upon the metal or 
metal alloy used to form film layer 30. For one embodiment, a hydrogen 
plasma with either an argon or helium carrier has been particularly 
effective in the removal of indium metal by forming indium hydride. The 
hydrogen plasma etch may be performed at temperatures less than 
100.degree. C. 
A hydrogen plasma etch may be satisfactorily used for other metals and 
metal alloys. The relatively low temperature (less than 100.degree. C.) 
required for hydrogen plasma etching in accordance with the present 
invention is particularly beneficial for forming metal interconnect 
patterns from soft alloys and low melting temperature alloys. If desired, 
various methyl alkyl groups may be used as part of the dry etching process 
depending upon the type of metal or alloys used to form the film layer. 
Semiconductor wafers 86 on ground electrode 102 are subjected to the 
selected etch plasma or gas which reacts with the unprotected portion of 
metal film layer 30. The resulting metal hydrides or organometallic 
products are removed from chamber 84 through outlet 98. The type of 
organometallic product formed by the etching process depends upon the 
constituents in the metal film layer 30 and the plasma etch gas. 
For one embodiment of the present invention, metal film layer 30 is formed 
from indium. When hydrogen plasma enters chamber 94 through inlet 96, 
hydrogen radicals, formed with the aid of the RF energy, will combine with 
indium metal which has not been covered by photoresist layers 32 to form 
indium hydrides. By maintaining chamber 94 in a vacuum, the indium 
hydrides become volatile and are removed from the surface of focal plane 
array 60. Photoresist layers 32 protect the portions of metal film layer 
30 which will become metal strip conducts 34 following the dry etching 
process. The result is a plurality of strips of indium 34 extending from 
each storage gate 22 to the corresponding pad 84. Metal layer 30 may be 
formed from indium and various indium alloys including lead indium. 
The present invention may be used to form various types of metal 
interconnect patterns in addition to metal strip conductors 34 shown in 
FIG. 4a. For example, some hybrid solid state systems are formed by bump 
bonding component structures having corresponding bumps of indium metal. 
As shown in FIGS. 6 and 7, substrate 110 includes a plurality of indium 
bumps 112 formed on planar surface 114. Each indium bump 112 is preferably 
disposed on an associated contact pad 116 with barrier layer 118 
therebetween. Barrier layer 118 may be formed from various metals and 
alloys such as nickel, chrome or titanium-tungsten. The material used to 
form barrier 118 is preferably selected to provide mechanical bonding and 
electrical contact between indium bump 112 and the associated contact pad 
116 while at the same time minimizing potential corrosion between indium 
bump 112 and contact pad 116. 
As shown by dotted lines in FIG. 7, substrate 120 with indium bump 122 may 
be bonded with corresponding indium bump 112 on substrate 110. Indium 
bumps 112 and 122 may be formed on their respective substrates 110 and 120 
by forming a layer of indium metal on the surface of each substrate and 
dry etching the indium metal layer in accordance with the present 
invention. 
Examples of thermal isolation structures and bump bonds are shown in U.S. 
Pat. No. 5,047,644 entitled Polyamide Thermal Isolation Mesa for a Thermal 
Imaging System to Meissner, et al. The fabrication techniques and the 
materials used in U.S. Pat. No. 5,047,644 may be used in fabricating 
either substrate 110 or 120. U.S. Pat. No. 5,047,644 is incorporated by 
reference for all purposes in this patent application. 
Various types of thermal sensors and integrated circuit substrates may also 
be satisfactorily used with the present invention. U.S. Pat. No. 4,143,269 
entitled Ferroelectric Imaging System provides information concerning 
infrared detectors fabricated from ferroelectric materials and a silicon 
switching matrix or integrated circuit substrate. Substrate 120 may be 
formed with a plurality of ferroelectric thermal sensors and substrate 110 
may comprise an integrated circuit substrate as shown in U.S. Pat. No. 
4,143,269. U.S. Pat. No. 4,143,269 is incorporated by reference for all 
purposes in this patent application. 
FIGS. 8a and 8b are schematic representations showing the fabrication of 
metal interconnects 132 on the surface of integrated circuit substrate 130 
using the present invention. Integrated circuit substrate 130 preferably 
includes a plurality of contact pads 134 with polyamide bumps 136 formed 
on the surface of each contact pad 134. The configuration of polyamide 
bumps 136 may be selected to correspond with the desired metal 
interconnect pattern. 
As shown in FIG. 8a, a layer of interconnect metal 138 may be disposed over 
the surface of substrate 130 including polyamide bumps 136. Layers 140 of 
appropriate photoresist material are next placed on metal layer 138 to 
correspond with the desired metal interconnect pattern. Substrate 130 may 
then be placed in RF chamber 90 and dry etched in accordance with the 
present invention to form a plurality of metal interconnects 132 on the 
surface of substrate 130. For one embodiment of the present invention, 
metal film layer 138 is preferably formed from indium or alloys of indium. 
The resulting metal interconnects 132 may be used to bump bond a focal 
plane array with an integrated circuit substrate. 
The present invention allows forming metal bumps, solder patterns, metal 
strips, or any other geometric configuration as desired from a layer of 
metal film. The requirements for forming a metal interconnect pattern in 
accordance with the present invention are positioning a photoresist on a 
metal film layer to produce the desired configuration and selecting a dry 
etch gas which will react with the unprotected portions of the metal film 
layer. 
Although the present invention and its advantages have been described in 
detail, it should be understood that various changes, substitutions and 
alterations can be made therein without departing from the spirit and 
scope of the invention as defined by the appended claims.