Semiconductor apparatus and repair method thereof

A semiconductor apparatus includes a fuse array configured to store word line failure information, a redundancy latch section, and a redundancy control block configured to store, in the redundancy latch section, word line order information generated according to the word line failure information.

CROSS-REFERENCES TO RELATED APPLICATION

The present application claims priority under 35 U.S.C. §119(a) to Korean application number 10-2015-0109980 filed on Aug. 4, 2015, in the Korean Intellectual Property Office, which is incorporated herein by reference in its entirety.

BACKGROUND

1. Technical Field

Various embodiments generally relate to a semiconductor circuit, and more particularly to a semiconductor apparatus and a repair method thereof.

2. Related Art

A semiconductor repair is a process that replaces failed elements involving defective memory cells or defective data lines of the semiconductor chip with redundant memory cells and data lines included in the chip. A semiconductor apparatus may store failed addresses in fuses to map the failed addresses to addresses of the redundant memory cells and data lines.

Even after the semiconductor apparatus has been assembled in a package, the semiconductor repair may be performed by using e-fuses that allow fuse information to be updated through rupture operations.

SUMMARY

Various embodiments are directed to a semiconductor apparatus and a repair method thereof capable of reducing a circuit area and performing a stable repair operation.

In an embodiment, a semiconductor apparatus may include: a fuse array configured to store word line failure information; a redundancy latch section; and a redundancy control block configured to store word line sequence information generated according to the word line failure information, in the redundancy latch section.

In an embodiment, the fuse array may include a plurality of fuses which one-to-one match the plurality of word lines, and each of the plurality of fuses may store the word line fail information as a 1-bit signal.

In an embodiment, a method for repairing a semiconductor apparatus including a plurality of word lines may include: detecting whether each of the plurality of word lines has failed, in a test mode, and writing a detection result in a fuse array; generating a word line sequence information corresponding to a fuse in which occurrence of a fail is written, by scanning the fuse array; storing the word line sequence information; and performing a repair operation by using the word line sequence information.

In an embodiment, the writing of the detection result in the fuse array may include storing whether each of the plurality of word lines has failed, in each of a plurality of fuses of the fuse array, by a 1-bit signal.

DETAILED DESCRIPTION

Hereinafter, a semiconductor apparatus and a repair method thereof will be described below with reference to the accompanying drawings through various examples of embodiments.

As shown inFIG. 1, a semiconductor apparatus100in accordance with an embodiment may include a memory region200and a fuse array300.

The memory region200may include a normal section210, a redundancy section220, and a redundancy latch section230.

The normal section210may include a memory cell array and a plurality of word lines WL.

The memory cell array of the normal section210may consist of small unit memory blocks such as ‘mats’ or large unit memory blocks such as ‘banks.’

The redundancy section220may include a plurality of redundancy word lines RWL0to RWLn for replacing word lines corresponding to failed address. The word lines corresponding to failed address may include, among the plurality of word lines WL, word lines coupled to failed memory and failed word lines.

The redundancy latch section230may store failed addresses associated with failed memory cells and failed data lines.

The redundancy latch section230may include a plurality of latch sets LSET_0to LSET_n.

The plurality of latch sets LSET_0to LSET_n and the plurality of redundancy word lines RWL0to RWLn may be in one-to-one correspondence.

Each of the plurality of latch sets LSET_0to LSET_n may include a plurality of latches.

For example, provided that a failed address is an address signal that has thirteen bits, each latch set LSET_0to LSET_n may include thirteen latches.

The fuse array300may store failed addresses by rupturing fuses.

The fuse array300may include a counter310and a plurality of fuse sets FSET_0to FSET_n.

Each fuse sets FSET_0to FSET_n may include a plurality of e-fuses.

For example, provided that a failed address is an address signal that has thirteen bits, each fuse set FSET_0to FSET_n may include thirteen e-fuses.

A rupture operation is an operation that ruptures a gate insulation layer of an e-fuse formed of a transistor by applying a predetermined voltage thereto.

In an embodiment, the plurality of fuse sets FSET_0to FSET_n and the plurality of latch sets LSET_0to LSET_n may be in one-to-one correspondence.

The counter310may sequentially read out failed addresses written in the plurality of fuse sets FSET_0to FSET_n in response to a clock signal CLK.

The repair operation of the semiconductor apparatus100in accordance with an embodiment will be described below with reference toFIG. 2.

The repair operation of the semiconductor apparatus100may include a plurality of steps S11to S16. In the step S11, the semiconductor apparatus100enters a test mode.

In the test mode, a test is performed on the memory cell array of the normal section210, and failed addresses are detected in the step S12.

In the step S13, the failed addresses, which are detected in the step S12, are stored in a fuse set in a way that the fuses of the fuse array300are programmed in a predetermined order by using the rupture operation described above. In an embodiment, the fuses of the fuse array300may store order information regarding the failed word line (e.g., information showing that the failed word line is nth word line.)

For example, if a number is assigned to each fuse set FSET_0to FSET_n, the plurality of fuse sets FSET_0to FSET_n may be programmed in numerical order.

That is to say, the first fuse set FSET_0among the plurality of fuse sets FSET_0to FSET_n is ruptured to store a first failed address, and then the second fuse set FSET_1is ruptured to store a second failed address.

In the step S14, the failed addresses stored in the plurality of fuse sets FSET_0to FSET_n of the fuse array300are read and the plurality of corresponding latch sets LSET_0to LSET_n of the redundancy latch section230may store the failed addresses.

The step S14may be performed using the counter310of the fuse array300in a boot-up process of the semiconductor apparatus100.

In the step S15, in a normal operation mode, the semiconductor apparatus100determines whether an address provided from outside the semiconductor apparatus100(hereinafter, referred to as “external address”) corresponds to a failed address stored in the redundancy latch section230.

If it is determined that the external address corresponds to a failed address stored in the redundancy latch section230, a repair operation is performed in the step S16.

In the repair operation of the step S16, a redundancy word line of the redundancy section220may be activated in place of a word line of the normal section210corresponding to a failed address.

For example, if the failed address stored in the first latch set LSET_0of the redundancy latch section230corresponds to the external address, the first redundancy word line RWL0, which is in one-to-one correspondence with the latch set LSET_0may be activated.

For example, if the failed address stored in the fourth latch set LSET_3of the redundancy latch section230corresponds to the external address, the fourth redundancy word line RWL3, which is in one-to-one correspondence with the fourth latch set LSET_3may be activated.

Hereinbelow, a semiconductor apparatus101in accordance with another embodiment and a repair method thereof will be described with reference toFIGS. 3 to 5.

As shown inFIG. 3, a semiconductor apparatus101in accordance with another embodiment may include a memory region200, a fuse array301, and a redundancy control block400.

The memory region200may include a normal section210, a redundancy section220, and a redundancy latch section230.

The normal section210may include a memory cell array and a plurality of word lines WL.

The memory cell array of the normal section210may consist of small unit memory blocks such as ‘mats’ or large unit memory blocks such as ‘banks.’

If a failed memory cell exists in the memory cell array of the normal section210, a word line coupled to the failed memory cell may also be determined as a failed word line.

The redundancy section220may include a plurality of redundancy word lines RWL0to RWLn for replacing the failed word lines among the plurality of word lines WL.

The redundancy latch section230may store addresses of word lines determined to be failed.

The addresses of word lines determined to be failed may have the same values as the failed addresses described above with reference toFIGS. 1 and 2.

The redundancy latch section230may include a plurality of latch sets LSET_0to LSET_n.

The plurality of latch sets LSET_0to LSET_n and the plurality of redundancy word lines RWL0to RWLn may be in one-to-one correspondence.

Each of the plurality of latch sets LSET_0to LSET_n may include a plurality of latches.

For example, provided that a failed address is an address signal that has thirteen bits, each latch set LSET_0to LSET_n may include thirteen latches.

The fuse array301may store failed addresses with respect to the plurality of word lines WL of the normal section210by rupturing fuses.

The fuse array301may include a counter311and a plurality of fuses F0to F8k−1. In an embodiment, e-fuses may be used as the plurality of fuses F0to F8k−1.

A number of the plurality of fuses F0to F8k−1 may be determined based on a number of word lines WL0to WL8k−1 included in the normal section210.

The plurality of fuses F0to F8k−1 and the plurality of word lines WL0to WL8k−1 of the normal section210may be in one-to-one correspondence.

The fuse array301may store, in the plurality of fuses F0to F8k−1, word line failure information FD, which indicates whether respective word lines WL0to WL8k−1 have failed or not. The fuses corresponding to the failed word lines may store one or a logic high level and a logic low level as the word line failure information FD. In an embodiment, the word line failure information FD may have a single-bit.

For example, the fuses corresponding to the failed word lines may store the logic high level, and the fuses corresponding to normal word lines may store a logic low level.

The counter311may sequentially output signals by counting the logic high levels, which indicate failed addresses, from the word line failure information FD.

The redundancy control block400may store word line order information CNT2generated according to the word line failure information FD in a latch set of the redundancy latch section230in a predetermined order. For example, if a number is assigned to each latch set of the redundancy latch section230, a plurality of latch sets may store the word line order information CNT2in numerical order. In an embodiment, the word line order information CNT2may have order information regarding the failed word line (e.g., information showing that the failed word line is nth word line.)

The redundancy control block400may include an order information generation section420and a latch set selection section430.

The order information generation section420may generate pre word line order information CNT1according to the clock signal CLK and the word line failure information FD.

The order information generation section420may sequentially increase an internal count value according to the clock signal CLK, and output the pre word line order information CNT1by capturing an internal count value at the timing when the word line failure information FD has a value indicating a word line failure.

While the word line order information CNT2is generated by increasing an internal count value in the order information generation section420, counting may be performed based on the failed addresses of the embodiment described above with reference toFIGS. 1 and 2.

Therefore, word line order information CNT2may have the same values as the failed addresses described above with reference toFIGS. 1 and 2.

The order information generation section420may output the pre word line order information CNT1by capturing an internal count value in the case where the word line failure information FD is the logic high level.

The order information generation section420may include a counter.

The latch set selection section430may store the pre word line order information CNT1as the word line order information CNT2by selecting one among the plurality of latch sets LSET_0to LSET_n of the redundancy latch section230according to the clock signal CLK and the word line failure information FD.

The latch set selection section430may sequentially select the plurality of latch sets LSET_0to LSET_n of the redundancy latch section230based on the clock signal CLK each time word line failure information FD has the logic high level.

The latch set selection section430may store the pre word line order information CNT1as the word line order information CNT2in a latch set currently selected among the plurality of latch sets LSET_0to LSET_n of the redundancy latch section230.

The latch set selection section430may include a counter.

The operation of the redundancy control block400will be described below with reference toFIG. 4.

For example, when assuming that the word lines WL1and WL8k−1 among the plurality of word lines WL0to WL8k−1 have been determined to be failed, the logic high level may be stored in the fuses F1and F8k−1 among the plurality of fuses F0to F8k−1.

The word line failure information FD may have the logic high level at the timing of the second clock pulse.

While increasing a count value (e.g., thirteen bits) according to the clock signal CLK, the order information generation section420may output a count value ‘0000000000001’ as the pre word line order information CNT1.

The latch set selection section430may store, in the latch set LSET_0, ‘0000000000001’ as the word line order information CNT2as the word line failure information FD.

The word line failure information FD may have the logic high level at the timing of the last clock pulse among the clock pulses.

The order information generation section420may output a count value ‘1111111111111’ as the pre word line order information CNT1.

The latch set selection section430may store, in the latch set LSET_1which comes right after the latch set LSET_0, ‘1111111111111’ as the word line order information CNT2as the word line failure information FD.

The repair operation of the semiconductor apparatus101in accordance with an embodiment will be described below with reference toFIG. 5.

The repair operation of the semiconductor apparatus101may include a plurality of steps S31to S37. In the step S31, the semiconductor apparatus101enters a test mode.

In the test mode, a test is performed on the normal section210, and failed addresses are detected in the step S32.

In the step S33, the failed addresses, among the word lines WL0to WL8k−1, are stored in the plurality of fuses F0to F8k−1, which are in one-to-one correspondence with the word lines WL0to WL8k−1, through the rupture operation as described above.

In the step S34, a fuse array scan operation is performed (S34).

In the fuse array scan operation, the order information generation section420reads the fuse data sequentially outputted by the counter311of the fuse array301, that is, the word line failure information FD stored in the plurality of fuses F0to F8k−1.

In the step S35, the word line order information CNT2corresponding to fuses that have been programmed with respect to failed addresses is stored in the redundancy latch section230.

The step S35may be an operation that the latch set selection section430stores the word line order information CNT2by selecting one among the plurality of latch sets LSET_0to LSET_n according to the word line failure information FD having the logic high level.

The step S35may be performed in the boot-up process of the semiconductor apparatus101.

In the step S36, in a normal operation mode, the semiconductor apparatus101determines whether the external address corresponds to a failed address stored in the redundancy latch section230.

While the word line order information CNT2is generated by increasing an internal count value in the order information generation section420, counting may be performed based on the failed addresses of the embodiment described above with reference toFIGS. 1 and 2.

Therefore, the word line order information CNT2may have the same values as the failed addresses described above with reference toFIGS. 1 and 2.

If it is determined that the external address corresponds to a failed address stored in the redundancy latch section230, a repair operation is performed in the step S37.

In the repair operation of the step S37, a redundancy word line of the redundancy section220may be activated in place of a word line of the normal section210corresponding to a failed address.

For example, if the failed address stored in the first latch set LSET_0of the redundancy latch section230corresponds to the external address, the first redundancy word line RWL0, which is in one-to-one correspondence with the latch set LSET_0may be activated.

For example, if the failed address stored in the second latch set LSET_1of the redundancy latch section230corresponds to the external address, the second redundancy word line RWL1, which is in one-to-one correspondence with the second latch set LSET_1may be activated.

While various embodiments have been described above, it will be understood to those skilled in the art that the embodiments described are examples only. Accordingly, the semiconductor apparatus and the repair method thereof described herein should not be limited based on the described embodiments.