Resistive differential alignment monitor

A microelectronic device includes a resistive differential alignment monitor (RDAM), including a first variable-width resistor and a second variable-width resistor, which are members of a conductor level. Each of the resistors include a wide portion and a narrow portion. The RDAM further includes a vertical connector to each of the wide portion and the narrow portion of the first variable-width resistor, and to the wide portion and the narrow portion of the second variable-width resistor. The vertical connectors are members of a vertical connector level. Test terminals are coupled to the vertical connectors. The vertical connectors to the first variable-width resistor and the vertical connectors to the second variable-width resistor are separated by equal distances and are oriented anti-parallel to each other. The RDAM may be used to estimate a misalignment distance between the members of the vertical connector level and the members of the conductor level.

TECHNICAL FIELD

This disclosure relates to the field of microelectronic devices. More particularly, but not exclusively, this disclosure relates to test structures in microelectronic devices.

BACKGROUND

Microelectronic devices are formed in patterned layers, such as dielectric layers, metal layers, and semiconductor layers, which are patterned using photolithographic processes. Unwanted effects during fabrication of the microelectronic devices may cause some of the patterned layers to be misaligned with respect to each other. Misalignment may degrade device performance and reliability.

SUMMARY

The present disclosure introduces a microelectronic device including a resistive differential alignment monitor (RDAM), including a first variable-width resistor and a second variable-width resistor. The variable-width resistors are members of a conductor level of the microelectronic device. Each of the first variable-width resistor and the second variable-width resistor include a wide portion and a narrow portion. The RDAM further includes a vertical connector contacting each of the wide portion of the first variable-width resistor, the narrow portion of the first variable-width resistor, the wide portion of the second variable-width resistor, and the narrow portion of the second variable-width resistor. The vertical connectors are members of a vertical connector level of the microelectronic device. The vertical connectors to the first variable-width resistor and the vertical connectors to the second variable-width resistor are separated by equal distances. The first variable-width resistor and the second variable-width resistor are oriented anti-parallel to each other.

DETAILED DESCRIPTION

In addition, although some of the embodiments illustrated herein are shown in two dimensional views with various regions having depth and width, it should be clearly understood that these regions are illustrations of only a portion of a device that is actually a three dimensional structure. Accordingly, these regions will have three dimensions, including length, width, and depth, when fabricated on an actual device. Moreover, while the present invention is illustrated by embodiments directed to active devices, it is not intended that these illustrations be a limitation on the scope or applicability of the present invention. It is not intended that the active devices of the present invention be limited to the physical structures illustrated. These structures are included to demonstrate the utility and application of the present invention to presently preferred embodiments.

For the purposes of this disclosure, the term “conductive” is to be interpreted as “electrically conductive”. The term “conductive” refers to materials and structures capable of supporting a steady electrical current, that is, direct current (DC).

Features of elements, such as widths and lengths, described as being equal are considered equal within fabrication tolerances encountered during fabrication of the respective elements. The fabrication tolerances include tolerances due to unwanted variations in geometries of photomasks used in photolithographic processes to form the respective elements, as well as tolerances due to unwanted variations in deposition and etch processes.

For the purposes of this disclosure, the terms “vertical” and “vertically” refer to directions perpendicular to a face of a resistor in a resistive differential alignment monitor (RDAM). The terms “lateral” and “laterally” refer to directions parallel to the face of the resistor.

FIG.1Ais a perspective view andFIG.1Bis a top view of an example microelectronic device that includes an RDAM. The microelectronic device100may be manifested as an integrated circuit, a microelectrical mechanical system (MEMS) device, an electro-optical device, or a microfluidic device, by way of example. The RDAM101includes a first variable-width resistor102, hereinafter the “first resistor” and a second variable-width resistor103, hereinafter the “second resistor”, formed in a conductor level104. The conductor level104may be, for example, an interconnect level containing aluminum or copper interconnects, a gate level containing polycrystalline silicon and metal silicide gates, a diffused layer level in a semiconductor substrate, a resistor level in an interconnect region, a capacitor plate level, a bond pad level, redistribution layer (RDL) level, a buried layer level in a semiconductor substrate, or a two-dimensional electron gas (2DEG) level in a III-V semiconductor material. Other manifestations of the conductor level104are within the scope of this disclosure.

The first resistor102and the second resistor103have same sublayers with same compositions, as a result of being formed concurrently. The term “formed concurrently” includes elements formed using a scanning lithography process, in which a scanning exposure step exposes the pattern for one of the elements before exposing the pattern for another of the elements in the same scan. The term “formed concurrently” includes elements formed using etch processes used to define the elements, in which the etch process may complete one of the elements before completing another of the elements, due to variations in the etch process. The term “formed concurrently” includes elements formed by other processes, such as wet etch or clean processes, and deposition or growth process, in which the process may complete one of the elements before completing another of the elements, due to variations in the process.

The first resistor102has a first wide portion105and a first narrow portion107separate from the first wide portion105. The second resistor103has a second wide portion109and a second narrow portion111separate from the second wide portion109.

The RDAM101includes first wide portion vertical connectors113aand113bcontacting a first face114of the first resistor102in the first wide portion105. The RDAM101further includes a first narrow portion vertical connector115contacting the first face114of the first resistor102in the first narrow portion107. The first wide portion105has a first width106adjacent to the first wide portion vertical connectors113aand113b, on a side of the first wide portion vertical connectors113aand113bfacing the first narrow portion107. The first narrow portion107has a second width108adjacent to the first narrow portion vertical connector115, on a side of the first narrow portion vertical connector115facing the first wide portion105. The first width106is greater than the second width108. The first wide portion105may have a uniform width, equal to the first width106, along its length, as depicted inFIG.1B, which may advantageously provide more uniform current flow in the first wide portion105during operation of the RDAM101. Similarly, the first narrow portion107may have a uniform width, equal to the second width108, along its length, as depicted inFIG.1B, which may advantageously provide more uniform current flow in the first narrow portion107during operation of the RDAM101.

Similarly, the RDAM101includes second wide portion vertical connectors116aand116bcontacting a second face117of the second resistor103in the second wide portion109. The RDAM101further includes a second narrow portion vertical connector118contacting the second face117of the second resistor103in the second narrow portion111. The second wide portion109has a third width110adjacent to the second wide portion vertical connectors116aand116b, on a side of the second wide portion vertical connectors116aand116bfacing the second narrow portion111. The second narrow portion111has a fourth width112adjacent to the second narrow portion vertical connector118, on a side of the second narrow portion vertical connector118facing the second wide portion109. The third width110is greater than the fourth width112.

The first wide portion vertical connectors113aand113b, the first narrow portion vertical connector115, the second wide portion vertical connectors116aand116b, and the second narrow portion vertical connector118are members of a vertical connector level119of the microelectronic device100, such as a contact level to components of the microelectronic device100, a via level between interconnect levels, a bond pad via level, an RDL via level, a deep trench connector level, or source/drain contacts to a 2DEG level in a III-V semiconductor material, by way of example. Other manifestations of the vertical connector level119are within the scope of this disclosure. Members of a vertical connector level119are formed concurrently. In some versions of this example, the RDAM101may include only a single first wide portion vertical connector contacting the first wide portion105and a single second wide portion vertical connector contacting the second wide portion109. In other versions, the RDAM101may include three or more first wide portion vertical connectors contacting the first wide portion105and three or more second wide portion vertical connectors contacting the second wide portion109. In further versions, the RDAM101may include two or more first narrow portion vertical connectors contacting the first narrow portion107and two or more second narrow portion vertical connectors contacting the second narrow portion111.

The second face117of the second resistor103is coplanar with the first face114of the first resistor102, as a result of the first resistor102and the second resistor103being in the conductor level104. The first wide portion vertical connectors113aand113bare separated from the first narrow portion vertical connector115by a first resistor length120that extends in a first direction121from the first narrow portion vertical connector115to the first wide portion vertical connectors113aand113b. The second wide portion vertical connectors116aand116bare separated from the second narrow portion vertical connector118by a second resistor length122that extends in a second direction123from the second narrow portion vertical connector118to the second wide portion vertical connectors116aand116b. The first resistor length120and the second resistor length122are equal. The second direction123is anti-parallel to the first direction121, that is, the second direction123and the first direction121point in opposite directions on parallel lines, or on the same line.

The microelectronic device100includes first through fourth test terminals124a,124b,124c, and124d, respectively. The test terminals124athrough124dare sometimes referred to as probe pads, as the RDAM101may be tested by connecting test instruments to the test terminals124athrough124dby probes. The first test terminal124ais coupled to the first wide portion vertical connectors113aand113b. The second test terminal124bis coupled to the first narrow portion vertical connector115. The third test terminal124cis coupled to the second wide portion vertical connectors116aand116b. The fourth test terminal124dis coupled to the second narrow portion vertical connector118. The test terminals124a,124b,124c, and124dare electrically conductive, and may be in an interconnect level or bond pad level, suitable for probing. The test terminals124a,124b,124c, and124dmay be directly coupled to the vertical connectors113aand113b,115,116aand116b, and118, as depicted inFIG.1A, or may be coupled to the vertical connectors113aand113b,115,116aand116b, and118through intermediate conductive structures such as interconnects and vias. The test terminals124a,124b,124c, and124dare omitted fromFIG.1Bin order to show the placement of the vertical connectors113aand113b,115,116aand116b, and118more clearly.

The RDAM101enables estimation of a misalignment distance between members of the conductor level104and members of the vertical connector level119. The misalignment distance may be along the first direction121or the second direction123.

FIG.2is a top view of an example first resistor and second resistor of an RDAM. The first resistor202has a first wide portion205and a first narrow portion207adjacent to the first wide portion205. The RDAM201includes first wide portion vertical connectors213aand213bon a first face214of the first resistor202in the first wide portion205, and includes a first narrow portion vertical connector215contacting the first face214of the first resistor202in the first narrow portion207. The second resistor203has a second wide portion209and a second narrow portion211adjacent to the second wide portion209. The RDAM201includes second wide portion vertical connectors216aand216bon a second face217of the second resistor203in the second wide portion209, and includes a second narrow portion vertical connector218contacting the second face217of the second resistor203in the second narrow portion211.

The first wide portion205has a first width206adjacent to the first wide portion vertical connectors213aand213b, on a side of the first wide portion vertical connectors213aand213bfacing the first narrow portion207. The first narrow portion207has a second width208adjacent to the first narrow portion vertical connector215, on a side of the first narrow portion vertical connector215facing the first wide portion205. The first width206is greater than the second width208.

The second wide portion209has a third width210adjacent to the second wide portion vertical connectors216aand216b, on a side of the second wide portion vertical connectors216aand216bfacing the second narrow portion211. The second narrow portion211has a fourth width212adjacent to the second narrow portion vertical connector218, on a side of the second narrow portion vertical connector218facing the second wide portion209. The third width210is greater than the fourth width212.

The first resistor202and the second resistor203are designed so that the first width206of the first wide portion205is equal to the third width210of the second wide portion209, and both have a value Wwide, as noted inFIG.2. Similarly, the first resistor202and the second resistor203are designed so that the second width208of the first narrow portion207is equal to the fourth width212of the second narrow portion211, and both have a value Wnarr, as noted inFIG.2.

In this example, the vertical connectors213aand213b,215,216aand216b, and218are misaligned with respect to the first resistor202and the second resistor203. That is, locations of the first wide portion vertical connectors213aand213b, are shifted from first wide portion nominal positions225aand225bby a misalignment distance Δx in the x direction. The x direction extends from the first wide portion vertical connectors213aand213btoward the first narrow portion vertical connector215, as indicated by the coordinate system226. A location of the first narrow portion vertical connector215is shifted from a first narrow portion nominal position227in the x direction by the misalignment distance Δx. Locations of the second wide portion vertical connectors216aand216b, are shifted from second wide portion nominal positions228aand228bin the x direction by the misalignment distance Δx. A location of the second narrow portion vertical connector218is shifted from a second narrow portion nominal position229in the x direction by the misalignment distance Δx. The nominal positions225aand225b,227,228aand228b, and229are the positions the vertical connectors213aand213b,215,216aand216b, and218would have if no misalignment had occurred. The vertical connectors213aand213b,215,216aand216b, and218may also be misaligned in the y direction, as indicated inFIG.2.

The RDAM201enables estimation of a misalignment distance between members of a conductor level containing the first resistor202and the second resistor203and members of a vertical connector level containing the vertical connectors213a,213b,215,216a,216b, and218. During operation of the RDAM201, a first resistance R1of the first resistor202is measured, and a second resistance R2of the second resistor203is measured. The first resistance R1may include extraneous resistance contributions from the first wide portion vertical connectors213aand213band the first narrow portion vertical connector215, and may further include resistance contributions from test terminals coupled to the vertical connectors213aand213band215. Similarly, the second resistance R2may include extraneous resistance contributions from the second wide portion vertical connectors216aand216band the second narrow portion vertical connector218, and may further include resistance contributions from test terminals coupled to the vertical connectors216aand216band218.

Functionality of the RDAM201may be understood by examining components of the first resistance R1from portions of the first resistor202, and similarly for components of the second resistance R2from portions of the second resistor203. Considering the first resistor202, a first component R1Wconnof the first resistance R1is from an area of the first wide portion205under and around the first wide portion vertical connectors213aand213b. The first component R1Wconnis sometimes referred to as a head resistance at the first wide portion vertical connectors213aand213b. The first component R1Wconnmay be affected by the size and number of first wide portion vertical connectors213aand213band spacing between the first wide portion vertical connectors213aand213b.

A second component R1wideof the first resistance R1is from an area of the first wide portion205, extending a first wide length L1widefrom the first wide portion vertical connectors213aand213bto a first transition region230at a boundary between the first wide portion205and the first narrow portion207. The second component R1widehas a value of Rsheet×(L1wide/Wwide), where Rsheetis a sheet resistance of the first resistor202and the second resistor203. The first wide length L1widemay be expressed in terms of a wide nominal length Lwide,nom, which is a length from the first wide portion nominal positions225aand225bto the first transition region230, and the misalignment distance Δx: L1wide=Lwide,nom−Δx. Then, the second component R1widemay be expressed as Rsheet×((Lwide,nom−Δx)/Wwide).

A third component R1transof the first resistance R1is from the first transition region230. The third component R1transmay be affected by a shape of the first resistor202in the first transition region230. For example, a sharp transition, as depicted inFIG.2, may produce a third component R1transthat is different from a resistor having a gentle, distributed transition.

A fourth component R1narrof the first resistance R1is from an area of the first narrow portion207, extending a first narrow length L1narrfrom the first transition region230to the first narrow portion vertical connector215. The fourth component R1narrhas a value of Rsheet×(L1narr/Wnarr). The first narrow length L1narrmay be expressed in terms of a narrow nominal length Lnarr,nom, which is a length from the first transition region230to the first narrow portion nominal position227, and the misalignment distance Δx: L1narr=Lnarr,nom+Δx. Then, the fourth component R1narrmay be expressed as Rsheet×((Lnarr,nom+Δx)/Wnarr).

A fifth component R1Nconnof the first resistance R1is from an area of the first narrow portion207under and around the first narrow portion vertical connector215. The fifth component R1Nconnis sometimes referred to as a head resistance at the first narrow portion vertical connector215. The fifth component R1Nconnmay be affected by the size, number, and spacing of the first narrow portion vertical connectors215.

The first resistance R1may be expressed as a sum of the five components, in terms of the misalignment distance Δx.

The second resistance R2of the second resistor203may be examined in a similar manner, and components of the second resistance R2may be identified. A first component R2Wconnof the second resistance R2is from an area of the second wide portion209under and around the second wide portion vertical connectors216aand216b. The first resistor202and the second resistor203are designed to have similar layouts, reversed from each other along the x direction, so that the first component R2Wconnof the second resistance R2is equal to the first component R1wconnof the first resistance R1, within tolerances encountered in fabrication of the first resistor202and the second resistor203.

A second component R2wideof the second resistance R2is from an area of the second wide portion209, extending a second wide length L2widefrom the second wide portion vertical connectors216aand216bto a second transition region231at a boundary between the second wide portion209and the second narrow portion211. The second component R2widehas a value of Rsheet×(L2wide/Wwide). The second wide length L2widemay be expressed in terms of the wide nominal length Lwide,nom, which is a length from the second wide portion nominal positions228aand228bto the second transition region231, and the misalignment distance Δx: L2wide=Lwide,nom+Δx. Then, the second component R2widemay be expressed as Rsheet×((Lwide,nom+−Δx)/Wwide) The first resistor202and the second resistor203are designed to have the respective distances from the nominal positions225aand225b, and228aand228b, of the wide portion vertical connectors213aand213b, and216aand216b, to the transition regions230and231, to both be equal to Lwide,nom.

A third component R2transof the second resistance R2is from the second transition region231. The first resistor202and the second resistor203are designed to have the respective transition regions230and231with equal shapes, so that R2transequals R1rans.

A fourth component R2narrof the second resistance R2is from an area of the second narrow portion211, extending a second narrow length L2narrfrom the second transition region231to the second narrow portion vertical connector218. The fourth component R2narrhas a value of Rsheet×(L2narr/Wnarr). The second narrow length L2narrmay be expressed in terms of the narrow nominal length Lnarr,nom, which is a length from the second transition region231to the second narrow portion nominal position229, and the misalignment distance Δx: L2narr=Lnarr,nom−Δx. Then, the fourth component R2narrmay be expressed as Rsheet×((Lnarr,nom+Δx)/Wnarr). The first resistor202and the second resistor203are designed to have the respective distances from the transition regions230and231, to the nominal positions227, and229, of the narrow portion vertical connectors215, and218, to both be equal to Lnarr,nom.

A fifth component R2Nconnof the second resistance R2is from an area of the second narrow portion211under and around the second narrow portion vertical connector218. The first resistor202and the second resistor203are designed to have similar layouts, reversed from each other along the x direction, so that the fifth component R2Nconnof the second resistance R2is equal to the fifth component R1Nconnof the first resistance R1, within tolerances encountered in fabrication of the first resistor202and the second resistor203.

The second resistance R2may be expressed as a sum of the five components, in terms of the misalignment distance Δx.

A difference between the first resistance R1and the second resistance R2may be expressed by subtracting Equation 1 from Equation 2, noting that R2Wconnequals R1Wconn, that R2Nconnequals R1Nconn, and that R2transequals R1trans, as expressed in Equation 3.

The misalignment distance Δx may be estimated from Equation 3 by dividing both sides by 2 Rsheet(1/Wnarr−1/Wwide), as expressed in Equation 4.

The value of the sheet resistance Rsheetmay be obtained from process monitor measurements. The values of the first and third widths206and210of the wide portions205and209of the first resistor202and the second resistor203may be obtained from design data, and may be corrected using linewidth monitor measurements. The values of the second and fourth widths208and212of the narrow portions207and211of the first resistor202and the second resistor203may be obtained by similar means. Thus, the misalignment distance Δx may be estimated in absolute units using Equation 4, which may advantageously be used to monitor misalignment. Misalignment values may be used to correct photolithography processes used in forming conductor levels corresponding to the conductor level containing the resistors202and203, or may be used to correct photolithography processes used in forming vertical connector levels corresponding to the vertical connector level containing the vertical connectors213a,213b,215,216a,216b, and218.

FIG.3is a top view of another example RDAM including a reference resistor pair. The RDAM301includes a first resistor302, a second resistor303and a reference resistor pair332. The first resistor302and the second resistor303have the properties disclosed in reference to any of the examples herein, including wide portions and narrow portions. The reference resistor pair332includes a first duplicate resistor302aand a second duplicate resistor303a. The first resistor302and the first duplicate resistor302ahave equal dimensions and a same first orientation. The second resistor303and the second duplicate resistor303ahave equal dimensions and a same second orientation, anti-parallel to the first orientation. The RDAM301further includes vertical connectors313on the wide portions and the narrow portions of the first resistor302, the second resistor303, the first duplicate resistor302a, and the second duplicate resistor303a, as disclosed in reference to the RDAM101ofFIG.1AandFIG.1Band the RDAM201ofFIG.2. The first duplicate resistor302aand the second duplicate resistor303aare coupled in series through the vertical connectors313by a conductive link333. The conductive link333makes contact to ends of the vertical connectors313opposite from the first duplicate resistor302aand the second duplicate resistor303a. The first duplicate resistor302aand the second duplicate resistor303amay be coupled in series through the vertical connectors313on the narrow portions of the duplicate resistors302aand303a, as depicted inFIG.3. Alternatively, the first duplicate resistor302aand the second duplicate resistor303amay be coupled in series through the vertical connectors313on the wide portions of the duplicate resistors302aand303a. In a further version of this example, the first duplicate resistor302aand the second duplicate resistor303amay be coupled from wide portion to narrow portion.

Test terminals324are coupled to the vertical connectors313on the first resistor302and the second resistor303, as disclosed in reference to the RDAM101ofFIG.1A. Additional test terminals324aare coupled to the vertical connectors313on the portions of the first duplicate resistor302aand the second duplicate resistor303awhich are not coupled together in series. For the version of this example depicted inFIG.3, the additional test terminals324aare coupled to the vertical connectors313on the wide portions of the first duplicate resistor302aand the second duplicate resistor303a. The conductive link333may be located in a same conductive level as the test terminals324and the additional test terminals324a. The additional test terminals324aenable measurement of a resistance of the reference resistor pair332, which includes a resistance of the first duplicate resistor302aand a resistance of the second duplicate resistor303a.

The reference resistor pair332may enable a quantitative check on the estimate of the misalignment distance Δx, disclosed in reference toFIG.2. The resistance Rrefof the reference resistor pair332is expected to be equal to the sum of the resistances of the first resistor302and the second resistor303, R1+R2, due to the first duplicate resistor302aand the second duplicate resistor303ahaving equal dimensions and orientations to the first resistor302and the second resistor303. Any difference between the resistance of the reference resistor pair332and the sum of the resistances of the first resistor302and the second resistor303, that is |Rref−(R1+R2)|, may be attributed to unwanted variations in features of the reference resistor pair332, the first resistor302, and the second resistor303, causing extraneous contributions to the resistances. Instances of the RDAM301in which a magnitude of the difference between the resistance of the reference resistor pair332and the sum of the resistances of the first resistor302and the second resistor303is significantly less than a magnitude of the difference of the resistances of the first resistor302and the second resistor303, that is, |Rref−(R1+R2)|<<<|R1−R2|, may indicate the estimate of the misalignment distance Δx is accurate. Conversely, instances of the RDAM301in which the magnitude of the difference between the resistance of the reference resistor pair332and the sum of the resistances of the first resistor302and the second resistor303is comparable to the magnitude of the difference of the resistances of the first resistor302and the second resistor303, that is, |Rref−(R1+R2)|≥|R1−R2|, may indicate the estimate of the misalignment distance Δx is undependable.

FIG.4is a top view of an example RDAM configured to estimate misalignment in two orthogonal directions. The RDAM401includes a first horizontal resistor chain434with first horizontal resistors402aand a second horizontal resistor chain435with second horizontal resistors403a. The first horizontal resistors402aand the second horizontal resistors403ahave the properties disclosed in reference to any of the examples herein, including wide portions and narrow portions.

The first horizontal resistors402aare duplicates of each other. The first horizontal resistors402aare connected serially through conductive links433, wide portion to narrow portion, through vertical connectors413on the wide portions and the narrow portions of the first horizontal resistors402a. The first horizontal resistors402aare all oriented horizontally, that is, the vertical connectors413on the wide portions on each first horizontal resistor402aare separated from the vertical connectors413on the narrow portions along a first horizontal direction. Instances of the first horizontal resistors402aat ends of the first horizontal resistor chain434are coupled to test terminals424.

The second horizontal resistors403aare duplicates of each other. The second horizontal resistors403aare connected serially through the conductive links433, wide portion to narrow portion, through vertical connectors413on the wide portions and the narrow portions of the second horizontal resistors403a. The second horizontal resistors403aare all oriented horizontally, that is, the vertical connectors413on the wide portions on each second horizontal resistor403aare separated from the vertical connectors413on the narrow portions along a second horizontal direction, anti-parallel to the first horizontal direction. Instances of the second horizontal resistors403aat ends of the first horizontal resistor chain434are coupled to test terminals424. The conductive links433may be coplanar with the test terminals424.

The first horizontal resistor chain434and the second horizontal resistor chain435may be used to estimate a horizontal misalignment distance between members of a conductor level containing the first horizontal resistors402aand the second horizontal resistors403aand members of a vertical connector level containing the vertical connectors413. A first horizontal chain resistance, R1chain,horiz, may be measured using the test terminals424coupled to the first horizontal resistor chain434. An average first horizontal resistance, R1avg,horiz, of the first horizontal resistors402amay be obtained by dividing the first horizontal chain resistance, R1chain,horiz, by the number, N1horiz, of the first horizontal resistors402ain the first horizontal resistor chain434, as expressed in Equation 5. Equation 5:
R1avg,horiz=R1chain,horiz/N1horiz

A second horizontal chain resistance, R2chain,horiz, may be measured using the test terminals424coupled to the second horizontal resistor chain435. An average second horizontal resistance, R2avg,horiz, of the second horizontal resistors403amay be obtained by dividing the second horizontal chain resistance, R2chain,horiz, by the number, N2horiz, of the second horizontal resistors403ain the second horizontal resistor chain435, as expressed in Equation 6.
R2avg,horiz=R2chain,horiz/N2horizEquation 6:

The average first horizontal resistance, R1avg,horiz, and the average second horizontal resistance, R2avg,horiz, may then be subtracted to estimate the horizontal misalignment distance, as disclosed in reference toFIG.2. The first horizontal resistor chain434and the second horizontal resistor chain435may include a sufficient number of the first horizontal resistors402aand the second horizontal resistors403a, respectively, to provide values of the first horizontal chain resistance, R1chain,horiz, and the second horizontal chain resistance, R2chain,horiz, that are more easily measured than single resistors. For example, the values of the first horizontal chain resistance, R1chain,horiz, and the second horizontal chain resistance, R2chain,horiz, may be 10 ohms to 10 kilo-ohms (kohms). The resistor chains434and435may be particularly advantageous for instances of the resistors402aand403afabricated in conductive levels which have sheet resistance values less than 0.10 ohms/square, such as interconnect levels. Having multiple instances of the resistors402aand403ain the resistor chains434and435may provide more accurate estimates of the average horizontal resistances, R1avg,horiz, and R2avg,horiz, in the presence of parasitic resistances, such as in the test terminals424.

The RDAM401includes a first vertical resistor chain436with first vertical resistors402band a second vertical resistor chain437with second vertical resistors403b. The first vertical resistors402band the second vertical resistors403bhave the properties disclosed in reference to any of the examples herein, including wide portions and narrow portions. The first vertical resistors402bare duplicates of each other, and are oriented parallel to each other, and the second vertical resistors403bare duplicates of each other. The first vertical resistors402band the second vertical resistors403bare oriented perpendicularly to the horizontal resistors402aand403a. The first vertical resistors402band the second vertical resistors403bmay be duplicates of the first horizontal resistors402aand the second horizontal resistors403a.

The first vertical resistors402bare connected serially through the conductive links433through vertical connectors413, and instances of the first vertical resistors402bat ends of the first vertical resistor chain436are coupled to test terminals424, as disclosed for the first horizontal resistors402a. The second vertical resistors403bare similarly connected serially through the conductive links433through vertical connectors413, and coupled to test terminals424.

The first vertical resistor chain436and the second vertical resistor chain437may be used to estimate a vertical misalignment distance, following the procedure disclosed for estimating the horizontal misalignment distance. Using the first vertical resistor chain436and the second vertical resistor chain437, each having multiple instances of the first vertical resistors402band the second vertical resistors403b, respectively, may provide the advantages disclosed in reference to the first horizontal resistor chain434and the second horizontal resistor chain435.

FIG.5is a chart of measurements acquired using a calibration RDAM. The calibration RDAM, not shown, includes a first resistor chain of first resistors and a second resistor chain of second resistors, and vertical connectors, similar to the resistor chains434and435ofFIG.4. In the RDAM used in this example, the vertical connectors have a nominal length and width, parallel to a plane of the resistors, of 300 nanometers. The calibration RDAM further includes additional pairs of resistor chains in which the vertical connectors were intentionally displaced in positive and negative increments of 25 nanometers. The resistors were formed in a thin film resistor layer, and the vertical connectors were formed in a via level. Each pair of resistor chains was measured, and the corresponding misalignment distance was estimated. The estimated displacement of the vertical connectors was plotted against the intentional (calibrated) displacement of the vertical connectors in the chart ofFIG.5. A least-squares trendline of the data has a slope of 1.050, and an intercept of 26 nanometers, corresponding to the case of no intentional displacement. The estimated displacements have a correlation R2of 0.989 to the calibrated displacements. Deviations of the estimated displacements from the trendline are attributed to geometry errors in the photomask used to form the vertical connectors, as well as variations encountered in deposition of the thin film level, patterning the resistors, and etching via holes for the vertical connectors. The data shown in the chart ofFIG.5indicates the RDAM is capable of estimating misalignment distances for vias on thin film resistor layers within 6 nanometers to 7 nanometers, significantly less than the allowed displacement tolerance of 100 nanometers.

FIG.6is a top view of an example resistor of an RDAM, showing placement of vertical connectors. The RDAM601includes a first resistor602, and a second resistor, not shown inFIG.6, which is a mirror duplicate of the first resistor602. The first resistor602includes a wide portion605and a narrow portion607adjacent to the wide portion605. In this example, the wide portion605extends past the narrow portion607by a first width increment638aon a first side of the first resistor602, and by a second width increment638bon a second side of the first resistor602. The first width increment638aand the second width increment638bmay be equal. The RDAM601of this example includes a wide portion vertical connector613on a face614of the first resistor602in the wide portion605, and includes a narrow portion vertical connector615contacting the face614of the first resistor602in the narrow portion607. The wide portion vertical connector613is separated from the narrow portion vertical connector615by a resistor length620that extends in a first direction621from the narrow portion vertical connector615to the wide portion vertical connector613. The wide portion605has a first width606adjacent to the wide portion vertical connector613, on a side of the wide portion vertical connector613facing the narrow portion607. The narrow portion607has a second width608adjacent to the narrow portion vertical connector615, on a side of the narrow portion vertical connector615facing the wide portion605. The first width606is greater than the second width608.

The wide portion vertical connector613has a first inline dimension639aparallel to the first direction621and a first transverse dimension639bperpendicular to the first direction621. The first inline dimension639aand the first transverse dimension639bare lateral dimensions of the wide portion vertical connector613, that is, the first inline dimension639aand the first transverse dimension639bare parallel to the face614, and are taken at the face614. The first inline dimension639amay be equal to the first transverse dimension639b, as depicted inFIG.6. Alternatively, the first inline dimension639amay be greater than the first transverse dimension639b, or the first inline dimension639amay be less than the first transverse dimension639b.

The narrow portion vertical connector615has a second inline dimension640aparallel to the first direction621and a second transverse dimension640bperpendicular to the first direction621. The second inline dimension640aand the second transverse dimension640bare lateral dimensions, taken at the face614. The second inline dimension640aand the second transverse dimension640bmay be equal, as depicted inFIG.6, or may be unequal. The second inline dimension640aand the second transverse dimension640bmay be equal to the first inline dimension639aand the first transverse dimension639b, or may be different.

The vertical connectors613and615may have rounded corners or rounded shapes, due to image deformation in a photolithography process used to form the vertical connectors613and615. The inline dimensions639aand640aare taken as maximum dimensions of the vertical connectors613and615, respectively, parallel to the first direction621. The transverse dimensions639band640bare taken as maximum dimensions of the vertical connectors613and615, respectively, perpendicular to the first direction621.

Performance of the RDAM601, with regard to estimating a misalignment distance of the vertical connectors613and615with respect to the first resistor602, may be enhanced by forming the first resistor602to extend past the vertical connectors613and615so that the vertical connectors613and615are completely located on the face614of the first resistor602, that is, the vertical connectors613and615do not extend over an edge of the first resistor602. Specifically, the first resistor602extends past the wide portion vertical connector613to the first side of the first resistor602by a first width extension641a, extends past the wide portion vertical connector613to the second side of the first resistor602by a second width extension641b, and extends past the wide portion vertical connector613in a direction opposite from the narrow portion vertical connector615by a first length extension641c. The extensions641a,641b, and641cmay be equal, or may be different. Similarly, the first resistor602extends past the narrow portion vertical connector615to the first side of the first resistor602by a third width extension642a, extends past the narrow portion vertical connector615to the second side of the first resistor602by a fourth width extension642b, and extends past the narrow portion vertical connector615in a direction opposite from the wide portion vertical connector613by a second length extension642c. The extensions642a,642b, and642cmay be equal, or may be different. The width extensions641a,641b,642a, and642bmay advantageously be larger than an expected misalignment of the vertical connectors613and615perpendicular to the first direction621. This advantage may be attained by forming the first resistor602so that the width extensions641a,641b,642a, and642bare at least as large as a minimum of the lateral dimensions of the vertical connectors613and615at the face614, referred to herein as the minimum vertical connection dimension, which is a minimum of the inline dimensions639aand640aand the transverse dimensions639band640bof the vertical connectors613and615. Similarly, the first resistor602may be formed so that the length extensions641cand642care at least as large as the minimum vertical connection dimension.

During operation of the RDAM601, a resistance of the first resistor602is measured. As disclosed in reference toFIG.2, the resistance of the first resistor602may be divided into five components.

A first component is from an area of the wide portion605under and around the wide portion vertical connector613. As noted above, performance of the RDAM601may be enhanced when the first resistor602extends past the wide portion vertical connector613on all sides.

A second component is from an area of the wide portion605, extending a wide length643from the wide portion vertical connector613to a transition region630at a boundary between the wide portion605and the narrow portion607. The wide length643corresponds to the first wide length L1wideofFIG.2. Performance of the RDAM601may further be enhanced by forming the first resistor602so that the wide length643is 2 to 5 times the minimum vertical connection dimension. If the wide length643is less than 2 times the minimum vertical connection dimension, the RDAM601may provide an erroneous estimate of the misalignment distance due to reduced linearity in the relationship between the misalignment distance and the difference in resistances of the first resistor602and the second resistor. If the wide length643is greater than 5 times the minimum vertical connection dimension, extraneous contributions to the resistances, which are expected to increase as the wide length643is increased, may reduce accuracy of the estimate of the misalignment distance.

A third component of the first resistance is from the transition region630. The transition region630corresponds to changes in current density between the wide portion605and the narrow portion607. A transition width644of the transition region630may be taken as twice a maximum of the first width increment638aand the second width increment638b.

A fourth component of the resistance is from an area of the narrow portion607, extending a narrow length645from the transition region630to the narrow portion vertical connector615. The narrow length645corresponds to the first narrow length L1narrofFIG.2. Similarly to the wide length643, performance of the RDAM601may further be enhanced by forming the first resistor602so that the narrow length645is 2 to 5 times the minimum vertical connection dimension.

A fifth component of the resistance is from an area of the narrow portion607under and around the narrow portion vertical connector615. As noted above, performance of the RDAM601may be enhanced when the first resistor602extends past the narrow portion607on all sides.

In this example, the first resistor602may have a rectilinear profile in the transition region630between the wide portion605and the narrow portion607, in which an edge of the first resistor602has a straight segment at the transition from the wide portion605to the narrow portion607, on each side of the first resistor602; the straight segments are oriented at right angles to the edges of the first resistor602in the wide portion605and the narrow portion607. The rectilinear profile may advantageously facilitate automated layout of the RDAM601.

FIG.7is a top view of another example resistor of an RDAM, showing placement of vertical connectors. The RDAM701includes a first resistor702, and a second resistor, not shown inFIG.7. The first resistor702includes a wide portion705and a narrow portion707adjacent to the wide portion705.

The RDAM701of this example includes two wide portion vertical connectors713aand713b, arranged across a width of the first resistor702in the wide portion705. The wide portion vertical connectors713aand713bcontact a face714of the first resistor702. The two wide portion vertical connectors713aand713bmay provide a more consistent resistance of the first resistor702, which may advantageously provide a more accurate estimate of a misalignment distance by the RDAM701.

The wide portion705has a first width706adjacent to the wide portion vertical connectors713aand713b, on a side of the wide portion vertical connectors713aand713bfacing the narrow portion707. The narrow portion707has a second width708adjacent to the narrow portion vertical connector715, on a side of the narrow portion vertical connector715facing the wide portion705. The first width706is greater than the second width708.

The RDAM701of this example includes a single narrow portion vertical connector715contacting the face714of the first resistor702in the narrow portion707. The single narrow portion vertical connector715may enable a minimum width of the first resistor702, consistent with the first resistor702extending past the narrow portion vertical connector715on all sides, which may advantageously reduce a total area of the RDAM701.

In this example, the first resistor702may have a sloped edge profile in a transition region730between the wide portion705and the narrow portion707. The sloped profile may provide more consistent patterns by a photolithographic process used to form the first resistor702, advantageously providing more accurate estimates of misalignment distances by the instances of the RDAM701.

FIG.8is a top view of a further example of a resistor of an RDAM, showing placement of vertical connectors. The RDAM801includes a first resistor802, and a second resistor, not shown inFIG.8. The first resistor802includes a wide portion805and a narrow portion807adjacent to the wide portion805.

The RDAM801of this example includes a first wide portion vertical connector813aand a second wide portion vertical connector813b, contacting a face814of the first resistor802. The first wide portion vertical connector813aand the second wide portion vertical connector813bare arranged along a direction of current flow of the first resistor802in the wide portion805. The RDAM801of this example includes a first narrow portion vertical connector815aand a second narrow portion vertical connector815b, contacting the face814. The first narrow portion vertical connector815aand the second narrow portion vertical connector815bare arranged along a direction of current flow of the first resistor802in the narrow portion807.

The wide portion805has a first width806adjacent to the second wide portion vertical connector813b, on a side of the second wide portion vertical connector813bfacing the narrow portion807. The narrow portion807has a second width808adjacent to the second narrow portion vertical connector815b, on a side of the second narrow portion vertical connector815bfacing the wide portion805. The first width806is greater than the second width808.

During operation of the RDAM801, the first wide portion vertical connector813aand the first narrow portion vertical connector815amay be connected to a current source846, so that current flows through the first resistor802from the first narrow portion vertical connector815ato the first wide portion vertical connector813a, as indicated inFIG.8, or vice versa. The second wide portion vertical connector813band the second narrow portion vertical connector815bmay be connected to an electric potential measurement component847, such as a voltmeter or source-measurement unit (SMU). The electric potential measurement component847provides a measurement of the potential across the first resistor802from the second narrow portion vertical connector815bto the second wide portion vertical connector813bproduced by the current from the current source846. The resistance of the first resistor802is estimated by dividing the measurement of the potential from the electric potential measurement component847by the current from the current source846. The measurement technique ofFIG.8may advantageously reduce unwanted extraneous resistance contributions from test terminals and probe equipment, advantageously providing a more accurate estimate of a misalignment distance by the RDAM801. The measurement technique ofFIG.8is commonly referred to as a kelvin measurement.

In this example, the first resistor802may have a curved edge profile in a transition region830between the wide portion805and the narrow portion807. The curved profile may provide even more consistent patterns by a photolithographic process used to form the first resistor802, compared to rectilinear or diagonal profiles with sharp corners, advantageously providing more accurate estimates of misalignment distances by the instances of the RDAM801.

FIG.9is a top view of an example of an RDAM, showing stretched vertical connectors. The RDAM901includes a first resistor902, and a second resistor, not shown inFIG.9. The first resistor902includes a wide portion905and a narrow portion907adjacent to the wide portion905.

The RDAM901of this example includes a wide portion vertical connector913on a face914of the first resistor902in the wide portion905, and includes a narrow portion vertical connector915contacting the face914of the first resistor902in the narrow portion907. The wide portion vertical connector913is separated from the narrow portion vertical connector915by a resistor length920that extends in a first direction921from the narrow portion vertical connector915to the wide portion vertical connector913. The wide portion vertical connector913of this example is a stretched vertical connector having a first inline dimension939aparallel to the first direction921, and a first transverse dimension939bperpendicular to the first direction921, in which the first transverse dimension939bis at least 3 times the first inline dimension939a. The stretched aspect of the wide portion vertical connector913may advantageously reduce unwanted variations in measured resistance of the first resistor902during operation of the RDAM901. The narrow portion vertical connector915of this example is also a stretched vertical connector having a second inline dimension940aparallel to the first direction921, and a second transverse dimension940bperpendicular to the first direction921, in which the second transverse dimension940bis at least 1.5 times the second inline dimension940a. The stretched aspect of the narrow portion vertical connector915may further reduce unwanted variations in measured resistance of the first resistor902.

The wide portion905has a first width906adjacent to the wide portion vertical connector913, on a side of the wide portion vertical connector913facing the narrow portion907. The narrow portion907has a second width908adjacent to the narrow portion vertical connector915, on a side of the narrow portion vertical connector915facing the wide portion905. The first width906is greater than the second width908.

In this example, the first resistor902may have a stepped edge profile in a transition region930between the wide portion905and the narrow portion907. The stepped profile may provide more process latitude for a photolithographic process used to form the first resistor902, compared to rectilinear profiles with sharp corners, while being compatible with design rules that do not allow diagonal edges.

FIG.10is a top view of an example of a tapered resistor of an RDAM. The RDAM1001includes a first resistor1002, and a second resistor, not shown inFIG.10. The first resistor1002has a tapered shape, with a wide portion1005and a narrow portion1007adjacent to the wide portion1005.

The RDAM1001of this example includes wide portion vertical connectors1013a,1013b, and1013con a face1014of the first resistor1002in the wide portion1005, and includes narrow portion vertical connectors1015aand1015bcontacting the face1014of the first resistor1002in the narrow portion1007. The wide portion1005has a first width1006adjacent to the wide portion vertical connectors1013a,1013b, and1013c, on a side of the wide portion vertical connectors1013a,1013b, and1013cfacing the narrow portion1007. The narrow portion1007has a second width1008adjacent to the narrow portion vertical connectors1015aand1015b, on a side of the narrow portion vertical connectors1015aand1015bfacing the wide portion1005. The first width1006is greater than the second width1008.

In this example, the wide portion1005and the narrow portion1007may be taken to meet at a midpoint between the wide portion vertical connectors1013a,1013b, and1013cand the narrow portion vertical connectors1015aand1015b. The wide portion1005has a first width1006adjacent to the wide portion vertical connectors1013athrough1013c, on a side of the wide portion vertical connectors1013athrough1013cfacing the narrow portion1007. The narrow portion1007has a second width1008adjacent to the narrow portion vertical connectors1015aand1015b, on a side of the narrow portion vertical connectors1015aand1015bfacing the wide portion1005. The first width1006is greater than the second width1008.

The RDAM1001of this example may be used to provide an estimate of a misalignment distance as disclosed in reference toFIG.2. The tapered shape of first resistor1002may provide more uniform current density between the wide portion vertical connectors1013a,1013b, and1013cand the narrow portion vertical connectors1015aand1015b, which may advantageously provide a more accurate estimate of the misalignment distance, compared to resistors having abrupt transitions between their wide portions and narrow portions.

The multiple wide portion vertical connectors1013a,1013b, and1013cmay provide more uniform current density in the wide portion1005, and the multiple narrow portion vertical connectors1015aand1015bmay provide more uniform current density in the narrow portion1007, further improving the accuracy of the misalignment distance estimate.

FIG.11is a top view of an example of non-symmetric shaped resistors of an RDAM. The RDAM1101includes a first resistor1102and a second resistor1103. A first face1114of the first resistor1102is coplanar with a second face1117of the second resistor1103. The first resistor1102has a first wide portion1105and a first narrow portion1107adjacent to the first wide portion1105. The first resistor1102of this example has a straight side1148aand a staggered side1148bopposite from the straight side1148a. The staggered side1148bmay have a rectilinear form, composed of straight edges meeting at right angles, as depicted inFIG.11, may have a polygonal form, composed of straight edges meeting at acute and obtuse angles, or may have a curvilinear form, composed of straight and curved edges. Thus, first narrow portion1107is offset with regard to the first wide portion1105, so that the first resistor1102has a non-symmetric shape.

The RDAM1101of this example includes two first wide portion vertical connectors1113aand1113b, arranged across a width of the first resistor1102in the first wide portion1105. The first wide portion vertical connectors1113aand1113bcontact the first face1114of the first resistor1102. The RDAM1101of this example includes a single first narrow portion vertical connector1115contacting the first face1114of the first resistor1102in the first narrow portion1107. The first wide portion vertical connectors1113aand1113bhave a first inline dimension1139aalong a first direction1121that points from the first narrow portion vertical connector1115to the first wide portion vertical connectors1113aand1113b. The first wide portion vertical connectors1113aand1113bhave a first transverse dimension1139bperpendicular to the first direction1121. The first narrow portion vertical connector1115has a second inline dimension1140aalong the first direction1121and a second transverse dimension1140bperpendicular to the first direction1121. In this example, the first transverse dimension1139band the second transverse dimension1140bmay be equal, and may be determined by fabrication guidelines for a vertical connector level of which the first wide portion vertical connectors1113aand1113band the first narrow portion vertical connector1115are members. The second inline dimension1140amay be greater than the first inline dimension1139a, to provide a closer match between a head resistance at the first narrow portion vertical connector1115and a head resistance at the first wide portion vertical connectors1113aand1113b. The configuration of the first wide portion vertical connectors1113aand1113band the first narrow portion vertical connector1115may be particularly advantageous for instances of the first resistor1102having a sheet resistance less than 0.10 ohms/square.

The first wide portion1105has a first width1106adjacent to the first wide portion vertical connectors1113aand1113b, on a side of the first wide portion vertical connectors1113aand1113bfacing the first narrow portion1107. The first narrow portion1107has a second width1108adjacent to the first narrow portion vertical connector1115, on a side of the first narrow portion vertical connector1115facing the first wide portion1105. The first width1106is greater than the second width1108.

The second resistor1103is a duplicate of the first resistor1102having a second wide portion1109and a second narrow portion1111adjacent to, and offset from, the second wide portion1109. The second resistor1103has the same non-symmetric shape as the first resistor1102, reversed in direction. The RDAM1101of this example includes two second wide portion vertical connectors1116aand1116bcontacting the second face1117in the second wide portion1109, and a single second narrow portion vertical connector1118contacting the second face1117in the second narrow portion1111. The second wide portion vertical connectors1116aand1116bhave the same dimensions as the first wide portion vertical connectors1113aand1113b, and the second narrow portion vertical connector1118has the same dimensions as the first narrow portion vertical connector1115.

The second wide portion1109has a third width1110, equal to the first width1106, adjacent to the second wide portion vertical connectors1116aand1116b, on a side of the second wide portion vertical connectors1116aand1116bfacing the second narrow portion1111. The second narrow portion1111has a fourth width1112, equal to the second width1108, adjacent to the second narrow portion vertical connector1118, on a side of the second narrow portion vertical connector1118facing the second wide portion1109.

The second resistor1103is reversed in direction from the first resistor1102, that is, a second direction1123that points from the second narrow portion vertical connector1118to the second wide portion vertical connectors1116aand1116bis anti-parallel to the first direction1121. The non-symmetric shapes of the first resistor1102and the second resistor1103may enable a more compact layout of the RDAM1101compared to resistor having symmetric shapes.

FIG.12AthroughFIG.12Eare cross sections of a microelectronic device having two example RDAMs, depicted in stages of an example method of formation. Referring toFIG.12A, the microelectronic device1200may be manifested as any of the microelectronic device types disclosed in reference to the microelectronic device100ofFIG.1AandFIG.1B. The microelectronic device1200of this example is formed in and on a substrate1249. The substrate1249includes a first area for a first RDAM1201aand a second area for a second RDAM1201b.

The substrate1249include a semiconductor material1250having a first conductivity type. In this example, the first conductivity type may be p-type, as indicated inFIG.12A. A field relief dielectric layer1251, commonly referred to as field oxide, is formed in and on the substrate1249. The field relief dielectric layer1251may be formed by a shallow trench isolation (STI) process and have an STI structure in which the field relief dielectric layer1251is in a trench in the semiconductor material1250, as depicted inFIG.12A. Alternatively, the field relief dielectric layer1251may be formed by a local oxidation of silicon (LOCOS) process and have a LOCOS structure, in which the field relief dielectric layer1251would have tapered edges, and extend partway into the semiconductor material1250and extend partway above the semiconductor material1250.

The first area for the first RDAM1201ais free of the field relief dielectric layer1251in an area for a first resistor1202aand an area for a second resistor, not shown. The first resistor1202aand the second resistor are parts of the first RDAM1201a. A diffused layer1252having a second conductivity type, opposite from the first conductivity type, is formed in the semiconductor material1250where exposed by the field relief dielectric layer1251. In this example, the second conductivity type may be n-type, as indicated inFIG.12A. The diffused layer1252is a member of a diffused layer level which may have an average dopant density of 1×1018atoms/cm3to 1×1020atoms/cm3, by way of example. The diffused layer1252may have a depth less than 1 micron. The diffused layer level may provide source/drain contact regions for n-channel metal oxide semiconductor (NMOS) transistors and contact regions for n-type wells in the microelectronic device1200. In the first area for the first RDAM1201a, the diffused layer1252provides a portion of the first resistor1202aand a portion of the second resistor.

The field relief dielectric layer1251may extend over the semiconductor material1250in the second area for the second RDAM1201b, as depicted inFIG.12A. Alternatively, the second area for the second RDAM1201bmay be free of the field relief dielectric layer1251.

Referring toFIG.12B, a gate layer1253is formed over the substrate1249and the field relief dielectric layer1251. The gate layer1253is a member of a gate level whose members may provide gates for NMOS transistors or p-channel metal oxide semiconductor (PMOS) transistors in the microelectronic device1200. The gate level may provide resistors or capacitor plates in the microelectronic device1200. The gate layer1253may include polycrystalline silicon, commonly referred to as polysilicon. Alternatively, the gate layer1253may include titanium nitride, tantalum nitride, fully silicided polysilicon (FUSI), or other conductive material. Sidewall spacers1254may be formed on lateral surfaces of the gate layer1253. The sidewall spacers1254may include silicon nitride, silicon dioxide, or silicon oxynitride, by way of example.

In this example, the first area for the first RDAM1201ais free of the gate layer1253. In the second area for the second RDAM1201b, the gate layer1253provides a portion of a third resistor1202band a fourth resistor, not shown. The third resistor1202band the fourth resistor are parts of the second RDAM1201b.

A metal silicide layer1255is formed on exposed silicon of the substrate1249and exposed polysilicon in the gate layer1253. The metal silicide layer1255may include titanium silicide, cobalt silicide, or nickel silicide, by way of example. The metal silicide layer1255may be formed by forming a layer of metal on the microelectronic device1200, contacting the exposed silicon and polysilicon. Subsequently, the layer of metal is heated to react the layer of metal with the exposed silicon and polysilicon to form the metal silicide layer1255. Unreacted metal is removed from the microelectronic device1200, leaving the metal silicide layer1255in place. The metal silicide layer1255may provide electrical connections to the gate layer1253and the substrate1249.

In the first area for the first RDAM1201a, the metal silicide layer1255on the diffused layer1252provides another portion of the first resistor1202aand another portion of the second resistor. In the second area for the second RDAM1201b, the metal silicide layer1255on the gate layer1253provides another portion of the third resistor1202band another portion of the fourth resistor.

The first resistor1202aincludes a first wide portion1205aand a first narrow portion1207a, according to any of the examples disclosed in reference toFIG.1AandFIG.1B,FIG.2, andFIG.6throughFIG.11. The second resistor is a duplicate of the first resistor1202a, having a second wide portion and a second narrow portion, reversed in direction. The third resistor1202bincludes a third wide portion1205band a third narrow portion1207b, according to any of the examples disclosed in reference toFIG.1AandFIG.1B,FIG.2, andFIG.6throughFIG.11. The fourth resistor is a duplicate of the third resistor1202b, having a fourth wide portion and a fourth narrow portion, reversed in direction.

Referring toFIG.12C, a pre-metal dielectric (PMD) layer1256is formed over the existing layers of the microelectronic device1200, covering the metal silicide layer1255and the field relief dielectric layer1251. The PMD layer1256is electrically non-conductive, and may include one or more sublayers of dielectric material. By way of example, the PMD layer1256may include a PMD liner, not specifically shown, of silicon nitride, contacting the metal silicide layer1255and the field relief dielectric layer1251. The PMD layer1256may also include a planarized layer of silicon dioxide-based dielectric material, not specifically shown, of silicon dioxide, phosphosilicate glass (PSG), fluorinated silicate glass (FSG), or borophosphosilicate glass (BPSG), on the PMD liner. The PMD layer1256may further include a PMD cap layer, not specifically shown, of silicon nitride, silicon carbide, or silicon carbonitride, on the planarized layer. Other layer structures and compositions for the PMD layer1256are within the scope of this example.

A vertical connector level1219is formed in the PMD layer1256. The vertical connector level1219includes a first wide portion vertical connector1213aof the first RDAM1201aon the first resistor1202ain the first wide portion1205a, and a first narrow portion vertical connector1215aon the first resistor1202ain the first narrow portion1207a. The first wide portion vertical connector1213aand the first narrow portion vertical connector1215aare conductive and extend through the PMD layer1256to make electrical connections to the first resistor1202a. The vertical connector level1219also includes second wide and narrow vertical connectors, not shown, to the second resistor. The vertical connector level1219further includes a third wide portion vertical connector1213bof the second RDAM1201bon the third resistor1202bin the third wide portion1205b, and a third narrow portion vertical connector1215bon the third resistor1202bin the third narrow portion1207b. The third wide portion vertical connector1213band the third narrow portion vertical connector1215bare conductive and extend through the PMD layer1256to make electrical connections to the third resistor1202b. The vertical connector level1219also includes fourth wide and narrow vertical connectors, not shown, to the fourth resistor. The vertical connector level1219also includes other vertical connectors, not shown, that provide electrical connections to components such as NMOS transistors and PMOS transistors of the microelectronic device1200. The vertical connectors of the vertical connector level1219are commonly referred to as contacts. The vertical connectors of the vertical connector level1219may include a liner/barrier of titanium and titanium nitride and a core metal of tungsten, as indicated inFIG.12C. Other structures for the vertical connectors of the vertical connector level1219are within the scope of this example.

Referring toFIG.12D, a first interconnect level1258is formed on the PMD layer1256and the vertical connector level1219. The first interconnect level1258includes a first test terminal1224aconnected to the first wide portion vertical connector1213aof the first RDAM1201aand a second test terminal1224bconnected to the first narrow portion vertical connector1215aof the first RDAM1201a. The first interconnect level1258also includes third and fourth test terminals connected to the vertical connectors on the second resistor. The first interconnect level1258further includes a fifth test terminal1224cconnected to the third wide portion vertical connector1213bof the second RDAM1201band a sixth test terminal1224dconnected to the third narrow portion vertical connector1215bof the second RDAM1201b. The first interconnect level1258also includes seventh and eighth test terminals connected to the vertical connectors on the fourth resistor. Forming the test terminals1224athrough1224dand the test terminals on the second and fourth resistors enables the first RDAM1201aand the second RDAM1201bto be tested after the first interconnect level1258is formed, without having to wait for fabrication of the microelectronic device1200to be completed.

The first interconnect level1258also includes first interconnects, not shown, that provide electrical connections between components of the microelectronic device1200. The first interconnects of the first interconnect level1258are conductive and make electrical connections to the contacts of the vertical connector level1219. The first interconnects and test terminals of the first interconnect level1258may have an etched aluminum structure, with an adhesion layer, not specifically shown, of titanium nitride or titanium tungsten, on the PMD layer1256, an aluminum layer, not specifically shown, with a few atomic percent of silicon, titanium, or copper, on the adhesion layer, and a barrier layer, not specifically shown, of titanium nitride on the aluminum layer. In another version of this example, the first interconnects and test terminals may have a damascene structure, with a barrier liner of tantalum and tantalum nitride in an interconnect trench in an intra-metal dielectric (IMD) layer, not specifically shown, on the PMD layer1256, with a copper core metal in the interconnect trench on the barrier liner. Other structures for the first interconnects and test terminals of the first interconnect level1258are within the scope of this example

Referring toFIG.12E, an inter-layer dielectric (ILD) layer1259may be formed over the first interconnect level1258. The ILD layer1259may include an etch stop layer, not specifically shown, of silicon nitride or silicon carbonitride on the interconnects of the first interconnect level1258and the PMD layer1256. The ILD layer1259may also include a planarized layer of silicon dioxide-based dielectric material, not specifically shown, of silicon dioxide, PSG, FSG, BPSG, organosilicate glass (OSG), carbon-doped oxide (CDO), or other low-k dielectric material, on the etch stop layer. The ILD layer1259may further include a stop layer of silicon nitride or silicon carbonitride on the planarized layer of silicon dioxide-based dielectric material. The stop layer may provide an etch stop layer for subsequently-formed etch aluminum interconnects, or a chemical mechanical polish (CMP) stop layer for subsequently-formed etch copper damascene interconnects.

A via layer1260is formed in the ILD layer1259. The via layer1260includes vias1261through the ILD layer1259, that make electrical connections to the test terminals1224athrough1224d, as well as additional vias, not shown, that make electrical connections to the test terminals on the second and fourth resistors of the first and second RDAMs1201aand1201band the additional interconnects, not shown, of the first interconnect level1258. The vertical connectors of the via layer1260are commonly referred to as contacts. The vias1261may include a liner/barrier of titanium and titanium nitride and a core metal of tungsten. Alternatively, the vias1261may include a liner/barrier of tantalum and tantalum nitride and a core metal of copper. Other structures for the vias1261are within the scope of this example.

A second interconnect level1262is formed on the ILD layer1259and the via layer1260. The second interconnect level1262includes upper test terminals1263connected to the test terminals1224athrough1224dand the test terminals on the second and fourth resistors of the first and second RDAMs1201aand1201b, through the vias1261. The second interconnect level1262also includes second interconnects, not shown, coupled to components in the microelectronic device1200. The upper test terminals1263and the second interconnects may have an etched aluminum structure, a copper damascene structure, or other structure. In some versions of this example, the via layer1260and the second interconnect level1262may be formed by a copper dual damascene process, with a common liner of tantalum and tantalum nitride and a common copper core metal in the vias1261and the upper test terminals1263. Forming the upper test terminals1263enables the first RDAM1201aand the second RDAM1201bto be tested after the second interconnect level1262is formed, without having to wait for fabrication of the microelectronic device1200to be completed. Additional test terminals may be formed in successive interconnect levels and a bond pad layer, enabling the first RDAM1201aand the second RDAM1201bto be tested at various stages of the fabrication process.

The first RDAM1201aenables estimation of a misalignment distance between members of a conductor level containing the first resistor1202aand members of the vertical connector level1219. The second RDAM1201benables estimation of a misalignment distance between members of a conductor level containing the third resistor1202band members of the vertical connector level1219.

FIG.13depicts a microelectronic device having two example RDAMs which may be used to estimate misalignment between members of two successive conductor levels. The microelectronic device1300includes a first conductor level1304, a vertical connector level1319, and a second conductor level1364. The first conductor level1304includes first conductive elements, and may be manifested as any of the examples disclosed in reference to the conductor level104ofFIG.1A. The second conductor level1364includes second conductive elements, and is successive to the first conductor level1304, that is, the second conductor level1364is formed after the first conductor level1304. The vertical connector level1319includes conductive vertical connectors which extend from the first conductive elements to the second conductive elements.

The first RDAM1301aincludes a first resistor1302aand a second resistor1303a, both in the first conductor level1304. The second resistor1303ais a duplicate of the first resistor1302a, reversed in direction. The first resistor1302aand the second resistor1303amay have any of the shapes and properties disclosed in reference to the examples ofFIG.1AandFIG.1B,FIG.2, andFIG.6throughFIG.11. The first RDAM1301aincludes first vertical connectors1313aof the vertical connector level1319on upper faces1314aand1317aof the first resistor1302aand the second resistor1303a, respectively, as disclosed in reference to the examples ofFIG.1AandFIG.1B.FIG.13shows two instances of the first vertical connectors1313aon each of the first resistor1302aand the second resistor1303a; the first RDAM1301amay include additional instances of the first vertical connectors1313aon each of the first resistor1302aand the second resistor1303a. The microelectronic device1300includes first test terminals1324acoupled to the first vertical connectors1313a, as disclosed in reference toFIG.1A. The first test terminals1324amay be instances of the second conductive elements of the second conductor level1364, as indicated inFIG.13. Alternatively, the first test terminals1324amay be elements of another conductor level of the microelectronic device1300. The first RDAM1301amay be used to estimate a first misalignment distance between the first conductive elements of the first conductor level1304and the vertical connectors of the vertical connector level1319, as disclosed in reference toFIG.2.

The second RDAM1301bincludes a third resistor1302band a fourth resistor1303b, both in the second conductor level1364. The fourth resistor1303bis a duplicate of the third resistor1302b, reversed in direction. The third resistor1302band the fourth resistor1303bmay have any of the shapes and properties disclosed in reference to the examples ofFIG.1AandFIG.1B,FIG.2, andFIG.6throughFIG.11. The second RDAM1301bincludes second vertical connectors1313bof the vertical connector level1319contacting lower faces1314band1317bof the third resistor1302band the fourth resistor1303b, respectively.FIG.13shows two instances of the second vertical connectors1313bcontacting each of the third resistor1302band the fourth resistor1303b; the second RDAM1301bmay include additional instances of the second vertical connectors1313bcontacting each of the third resistor1302band the fourth resistor1303b. The lower faces1314band1317bof the third resistor1302band the fourth resistor1303bare parallel to, but not coplanar with, the upper faces1314aand1317aof the first resistor1302aand the second resistor1303a. The first vertical connectors1313aand the second vertical connectors1313bhave upper ends which are coplanar with the lower faces1314band1317bof the third resistor1302band the fourth resistor1303b, and have lower ends which are coplanar with the upper faces1314aand1317aof the first resistor1302aand the second resistor1303a. In this example, ends of vertical connectors are coplanar with faces of resistors when the ends of the vertical connectors contact the resistors at the faces, recognizing the vertical connectors may extend into the resistors as a result of fabrication processes used to form the vertical connectors and the resistors.

The second RDAM1301bof this example further includes lateral connectors1365, which may be members of the first conductor level1304. The second vertical connectors1313bcontact the lateral connectors1365. The lateral connectors1365extend laterally past the third resistor1302band the fourth resistor1303b. The second RDAM1301bof this example also includes third vertical connectors1366of the vertical connector level1319that contact the lateral connectors1365. The microelectronic device1300includes second test terminals1324bcoupled to the third vertical connectors1366, so that the second test terminals1324bare coupled to the third resistor1302band the fourth resistor1303bthrough the second vertical connectors1313b, the lateral connectors1365, and the third vertical connectors1366. The second test terminals1324bmay be instances of the second conductive elements of the second conductor level1364, as indicated inFIG.13. Alternatively, the second test terminals1324bmay be elements of another conductor level of the microelectronic device1300. The second RDAM1301bmay be used to estimate a second misalignment distance between the second conductive elements of the second conductor level1364and the vertical connectors of the vertical connector level1319. The estimate of the first misalignment distance and the estimate of the second misalignment distance may be combined to provide an estimate of misalignment between the second conductive elements of the second conductor level1364and the first conductive elements of the first conductor level1304, which may be useful with regard to components that include instances of both the second conductor level1364and the first conductor level1304, such as capacitors and inductors in an interconnect region of the microelectronic device1300.

FIG.14AthroughFIG.14Hare top views and cross sections of a microelectronic device with an RDAM for estimating a misalignment distance between vias and interconnects of a copper dual damascene structure, depicted in stages of an example method of formation. Referring toFIG.14A, a top view, andFIG.14B, a cross section, the microelectronic device1400includes a first dielectric layer1456. By way of example, the first dielectric layer1456may be manifested as a PMD layer or an ILD layer of the microelectronic device1400.

A first lateral connector1465aand a second lateral connector1465bof the RDAM1401are formed in or on the first dielectric layer1456. The lateral connectors1465aand1465bmay have a damascene structure, and may include a first barrier liner1467of tantalum and tantalum nitride in interconnect trenches1468in the first dielectric layer1456, with a first copper core metal1469in the interconnect trenches1468on the first barrier liner1467. Other structures for the lateral connectors1465aand1465b, such as etched aluminum structures, are within the scope of this example. The lateral connectors1465aand1465bare formed concurrently with other lateral conductors, such as interconnects, of the microelectronic device1400.

Referring toFIG.14C, a top view, andFIG.14D, a cross section, a second dielectric layer1459is formed over the first dielectric layer1456and the lateral connectors1465aand1465b. The second dielectric layer1459may be manifested as an ILD layer of the microelectronic device1400.

A via etch mask1470is formed over the second dielectric layer1459, exposing the second dielectric layer1459in areas over the lateral connectors1465aand1465bfor a first vertical connector1413, a second vertical connector1415, a first test terminal connector1466a, and a second test terminal connector1466bof the RDAM1401, as well as vias, not shown, of the microelectronic device1400. The vertical connectors1413and1415and the test terminal connectors1466aand1466bare shown inFIG.14GandFIG.14H. The via etch mask1470may include photoresist and may be formed by a photolithographic process. The via etch mask1470may include anti-reflection material such as bottom anti-reflection coat (BARC), and may include hard mask material such as amorphous carbon.

A partial via etch process is performed which removes dielectric material from the second dielectric layer1459where exposed by the via etch mask1470, to form via holes1471in the second dielectric layer1459for the vertical connectors1413and1415and the test terminal connectors1466aand1466b, as well as the vias of the microelectronic device1400. The via holes1471extend partway to the lateral connectors1465aand1465b. The partial via etch process may be implemented as a timed reactive ion etch (RIE) process using fluorine radicals.

After the partial via etch process is completed, the via etch mask1470is removed. Organic material and amorphous carbon in the via etch mask1470may be removed by an oxygen plasma process, followed by a wet clean process, by way of example.

Referring toFIG.14E, a top view, andFIG.14F, a cross section, a trench etch mask1472is formed over the second dielectric layer1459, exposing the second dielectric layer1459in an area over the lateral connectors1465aand1465bfor a first resistor1402, a first test terminal1424a, and a second test terminal1424bof the RDAM1401, as well as interconnects, not shown, of the microelectronic device1400. The first resistor1402and the test terminals1424aand1424bare shown inFIG.14GandFIG.14H. The trench etch mask1472may include photoresist, formed by a photolithographic process, and may include anti-reflection material and hard mask material.

A trench etch process is performed which removes dielectric material from the second dielectric layer1459where exposed by the trench etch mask1472, to form a resistor trench1473a, a first test terminal trench1473b, and a second test terminal trench1473cin the second dielectric layer1459for the first resistor1402, the first test terminal1424a, and the second test terminal1424b, respectively, shown inFIG.14GandFIG.14H, and to form interconnect trenches, not shown, for the interconnects of the microelectronic device1400. The trenches1473a,1473b, and1473cextend partway to the lateral connectors1465aand1465band the first dielectric layer1456.

The trench etch process also removes additional dielectric material from the second dielectric layer1459under the via holes1471, so that the via holes1471extend to the lateral connectors1465aand1465bwhen the trench etch process is completed. The trench etch process may include an etch stop removal operation to clear an etch stop layer in the second dielectric layer1459. The trench etch process may be implemented as a timed RIE process using fluorine radicals. After the trench etch process is completed, the trench etch mask1472is removed.

Referring toFIG.14G, a top view, andFIG.14H, a cross section, a second barrier liner1474is formed in the trenches1473a,1473b, and1473cand the via holes1471. The second barrier liner1474may include tantalum and tantalum nitride, and may be formed by sputtering tantalum onto the second dielectric layer1459, and onto the lateral connectors1465aand1465bwhere exposed by the via holes1471, followed by forming tantalum nitride by an atomic layer deposition (ALD) process on the tantalum. The second barrier liner1474extends onto a top surface of the second dielectric layer1459.

A second copper core metal1475is formed on the second barrier liner1474, filling the trenches1473a,1473b, and1473cand the via holes1471, and extending over the top surface of the second dielectric layer1459. The second copper core metal1475may be formed by sputtering a seed layer of copper on the second barrier liner1474, followed by electroplating copper on the seed layer. Additives such as inhibitors and levelers may be added to a plating bath used for electroplating the copper, to reduce voids in the via holes1471and to reduce an amount of the copper1475extending over the top surface of the second dielectric layer1459. Subsequently, the second copper core metal1475and the second barrier liner1474over the top surface of the second dielectric layer1459, outside of the trenches1473a,1473b, and1473c, are removed by a copper CMP process, leaving the second copper core metal1475and the second barrier liner1474in the trenches1473a,1473b, and1473cand the via holes1471, to provide the first resistor1402, the first test terminal1424a, the second test terminal1424b, the first vertical connector1413, the second vertical connector1415, the first test terminal connector1466a, and the second test terminal connector1466b. The first resistor1402, with the first vertical connector1413and the second vertical connector1415are referred to as a copper dual damascene structure. The first resistor1402has a first wide portion1405and a first narrow portion1407. The first vertical connector1413contacts the first resistor1402in the first wide portion1405, and the second vertical connector1415contacts the first resistor1402in the first narrow portion1407.

The test terminals1424aand1424bare coupled to the first resistor1402through the test terminal connectors1466aand1466b, the lateral connectors1465aand1465b, the vertical connectors1413and1415. Concurrently with these conductive elements, additional lateral connectors, a second resistor, additional vertical connectors, additional test terminals, and additional test terminal connectors, not shown, are formed as part of the RDAM1401. The second resistor is a duplicate of the first resistor1402, reversed in direction. The RDAM1401may be used to estimate a misalignment distance between an interconnect the first resistor1402and the vertical connectors1413and1415.

FIG.15AthroughFIG.15Dare cross sections of a microelectronic device that includes two additional example RDAMs involving a resistor and a capacitor, depicted in stages of an example method of formation. Referring toFIG.15A, the microelectronic device1500may be manifested as any of the microelectronic device types disclosed in reference to the microelectronic device100ofFIG.1AandFIG.1B. The microelectronic device1500of this example is formed in and on a substrate1549. The substrate1549includes a first area for a first RDAM1501aand a second area for a second RDAM1501b. In some versions of this example, the substrate1549may be implemented as a dielectric layer, such as a PMD layer or an ILD layer, in the first area for a first RDAM1501aand in the second area for a second RDAM1501b. In other versions of this example, the substrate1549may be implemented as a semiconductor material or a dielectric material in the first area for a first RDAM1501a, and may be implemented as the same material or a different semiconductor material or a dielectric material in the second area for a second RDAM1501b.

In the first area for a first RDAM1501a, a lower conductor1576is formed over the substrate1549, and a capacitor dielectric layer1577is formed over the lower conductor1576. A first upper plate resistor1502aof the first RDAM1501ais formed over the capacitor dielectric layer1577. The lower conductor1576may be an element of a first interconnect level of the microelectronic device1500. The capacitor dielectric layer1577may be part of an anti-reflection layer used to pattern the first interconnect level, including the lower conductor1576. The first upper plate resistor1502amay be an element of an upper capacitor plate level of the microelectronic device1500. The lower conductor1576, the capacitor dielectric layer1577, and the first upper plate resistor1502amay be formed by a process sequence that includes forming an interconnect metal layer for the first interconnect level on the substrate1549. The interconnect metal layer may include an adhesion layer, not specifically shown, of titanium nitride or titanium tungsten, on the substrate1549, an aluminum layer, not specifically shown, with a few atomic percent of silicon, titanium, or copper, on the adhesion layer, and a barrier layer, not specifically shown, of titanium nitride on the aluminum layer, similar to the first interconnect level1258disclosed in reference toFIG.12D. The process sequence is continued by forming an anti-reflection layer over the interconnect metal layer, before the interconnect metal layer is patterned. The anti-reflection layer may include a lower sub-layer, not specifically shown, of silicon dioxide immediately over the interconnect metal layer, a middle sub-layer, not specifically shown, of silicon nitride over the lower sub-layer, and an upper sub-layer, not specifically shown, of silicon dioxide over the middle sub-layer. The process sequence is continued by forming a capacitor upper plate layer over the anti-reflection layer, before the interconnect metal layer is patterned. The capacitor upper plate layer may include an adhesion sub-layer of titanium and a main sub-layer of titanium nitride. The capacitor upper plate layer is then patterned to form the first upper plate resistor1502aconcurrently with upper plates of capacitors of the microelectronic device1500, by an RIE process using halogen radicals. Patterning of the capacitor upper plate layer is performed so as to leave a sufficient thickness of the anti-reflection layer over the interconnect metal layer to provide an anti-reflection functionality. The interconnect metal layer is patterned, using a photolithographic process that is facilitated by the anti-reflection layer, and an RIE process using chlorine radicals, to form the lower conductor1576, lower capacitor plates for the capacitors, and interconnects of the first interconnect level. The anti-reflection layer may be left over the lower conductor1576, lower capacitor plates, and interconnects, as indicated inFIG.15A.

The first upper plate resistor1502aincludes a first wide portion1505aand a first narrow portion1507a. The first upper plate resistor1502amay have any of the configurations disclosed in reference toFIG.6throughFIG.11. A second upper plate resistor, not shown, of the first RDAM1501ais formed concurrently with the first upper plate resistor1502a. The second upper plate resistor is a duplicate of the first upper plate resistor1502a, reversed in direction.

In this example, the second area for a second RDAM1501bmay be left free of the interconnect metal layer, the anti-reflection layer, and the capacitor upper plate layer. Alternatively, one or more interconnects of the first interconnect level, with accompanying overlayers of the anti-reflection layer, may be formed in the second area for a second RDAM1501b.

Referring toFIG.15B, a first ILD sub-layer1559ais formed over the existing microelectronic device1500. The first ILD sub-layer1559amay include an etch stop layer, not specifically shown, of silicon nitride and a planarized main layer, not specifically shown, of a silicon dioxide-based dielectric material on the etch stop layer. The first ILD sub-layer1559amay include a cap layer, not specifically shown, of silicon nitride, over the planarized main layer.

A first thin film resistor1502bof the second RDAM1501bis formed over the first ILD sub-layer1559a. The first thin film resistor1502bmay be part of a resistor level that includes additional thin film resistors used in circuits of the microelectronic device1500. By way of example, the first thin film resistor1502bmay include alloys of nickel, chromium, titanium, tantalum, molybdenum, silicon, and any metals of the platinum group (ruthenium, rhodium, palladium, osmium, iridium, and platinum). The first thin film resistor1502bmay include other elements, such as aluminum, copper, oxygen, nitrogen, or carbon, to impart desired properties to the first thin film resistor1502b. Other compositions for the first thin film resistor1502bare within the scope of this example.

The first thin film resistor1502bincludes a second wide portion1505band a second narrow portion1507b. The first thin film resistor1502bmay have any of the configurations disclosed in reference toFIG.6throughFIG.11. A second thin film resistor, not shown, of the second RDAM1501bis formed concurrently with the first thin film resistor1502b. The second thin film resistor is a duplicate of the first thin film resistor1502b, reversed in direction.

Referring toFIG.15C, a second ILD sub-layer1559bis formed over the existing microelectronic device1500. The second ILD sub-layer1559bmay include an etch stop layer, not specifically shown, of silicon nitride and a planarized main layer, not specifically shown, of a silicon dioxide-based dielectric material on the etch stop layer. The second ILD sub-layer1559bmay include a CMP stop layer, not specifically shown, of silicon nitride or silicon carbonitride, over the planarized main layer.

A first deep vertical connector1513aand a second deep vertical connector1515aare formed through the second ILD sub-layer1559band the first ILD sub-layer1559ato make contact to the first upper plate resistor1502ain the first wide portion1505aand the first narrow portion1507a, respectively. Concurrently, a third deep vertical connector, not shown, and a fourth deep vertical connector, not shown, are formed through the second ILD sub-layer1559band the first ILD sub-layer1559ato make contact to the second upper plate resistor.

A first shallow vertical connector1513band a second shallow vertical connector1515bare formed through the second ILD sub-layer1559bto make contact to the first thin film resistor1502bin the second wide portion1505band the second narrow portion1507b, respectively. Concurrently, a third shallow vertical connector, not shown, and a fourth shallow vertical connector, not shown, are formed through the second ILD sub-layer1559bto make contact to the second thin film resistor.

The shallow vertical connectors1513band1515bmay be formed concurrently with the deep vertical connectors1513aand1515a, or may be formed separately. The deep vertical connectors1513aand1515amay be part of a deep via level of the microelectronic device1500, and may be formed by any of the processes disclosed in reference to vias herein. Similarly, the shallow vertical connectors1513band1515bmay be part of a shallow via level of the microelectronic device1500, and may be formed by any of the processes disclosed in reference to vias herein.

Referring toFIG.15D, a first wide portion test terminal1524ais formed on the second ILD sub-layer1559bto make contact to the first deep vertical connector1513a, and a first narrow portion test terminal1524bis formed on the second ILD sub-layer1559bto make contact to the second deep vertical connector1515a. A second wide portion test terminal1524cis formed on the second ILD sub-layer1559bto make contact to the first shallow vertical connector1513b, and a second narrow portion test terminal1524dis formed on the second ILD sub-layer1559bto make contact to the second shallow vertical connector1515b. Additional test terminals are formed on the second ILD sub-layer1559bto make contact to the vertical connectors on the second upper plate resistor and the second thin film resistor. The test terminals1524athrough1524dand the additional test terminals may be part of an interconnect level of the microelectronic device1500. The test terminals1524athrough1524dmay have an etched aluminum structure or may have a copper damascene structure. Other structures for the test terminals1524athrough1524dare within the scope of this example.

The first RDAM1501aenables estimation of a first misalignment distance between members of the deep via level with respect to members of the upper capacitor plate level of the microelectronic device1500. The second RDAM1501benables estimation of a second misalignment distance between members of the shallow via level with respect to members of the thin film resistive level of the microelectronic device1500.

FIG.16AthroughFIG.16Care cross sections of a microelectronic device with an example RDAM involving bond pads, depicted in stages of an example method of formation. Referring toFIG.16A, the microelectronic device1600may be manifested as any of the microelectronic device types disclosed in reference to the microelectronic device100ofFIG.1AandFIG.1B. The microelectronic device1600of this example includes a top dielectric layer1659. In one version of this example, the top dielectric layer1659may be implemented as an ILD layer, and may have the structure and composition disclosed in reference to the ILD layer1259ofFIG.12E, for example. In another version of this example, the top dielectric layer1659may be implemented as a cap layer over a top interconnect level, and may include silicon dioxide, silicon nitride, silicon oxynitride, or polyimide, by way of example. Other compositions and structures for the top dielectric layer1659are within the scope of this example.

A first lateral connector1665aand a second lateral connector1665bare formed on the top dielectric layer1659in an area for the RDAM1601. The lateral connectors1665aand1665bare electrically conductive, and are part of a conductor level of the microelectronic device1600. A third lateral connector, not shown, and a fourth lateral connector, not shown, of the RDAM1601are formed concurrently with the lateral connectors1665aand1665b. In one version of this example, the conductor level, including the lateral connectors1665aand1665b, may be part of a top interconnect level of the microelectronic device1600, and may have an etched aluminum structure, a copper damascene structure, or a plated structure, by way of example. Interconnects having a plated structure may include an adhesion layer, not shown, on the top dielectric layer1659, with copper interconnects on the adhesion layer. The plated interconnects may be formed by sputtering the adhesion layer, containing titanium, on the top dielectric layer1659, followed by sputtering a seed layer, not shown, of copper on the adhesion layer. A plating mask is formed on the seed layer that exposes areas for the interconnects and the lateral connectors1665aand1665b. The plated interconnects are formed by electroplating copper on the seed layer where exposed by the plating mask. The plating mask is removed, and the seed layer and the adhesion layer between the interconnects are removed by wet etching. In another version of this example, the conductor level, including the lateral connectors1665aand1665b, may be part of an input/output (I/O) pad level of the microelectronic device1600, to be connected to an RDL. The input/output pad level may have a plated structure.

Referring toFIG.16B, a protective overcoat (PO) layer1678is formed over the top dielectric layer1659and the lateral connectors1665aand1665b. The PO layer1678is non-conductive, and may include one or more layers of dielectric material, such as silicon dioxide, silicon nitride, silicon oxynitride, aluminum oxide, polyimide, benzocyclobutene (BCB), or polybenzoxazole (PBO), by way of example. I/O pad openings1679extend through the PO layer1678, exposing the lateral connectors1665aand1665b. The I/O pad openings1679may be formed by an etch process after the one or more layers of dielectric material of the PO layer1678are formed. Alternatively, the I/O pad openings1679may be formed as parts of the one or more layers of dielectric material, by a photolithographic process for photosensitive dielectric material, such as photosensitive polyimide.

Referring toFIG.16C, a top conductor level1604is formed on the existing microelectronic device1600, with top conductor metal extending over the PO layer1678and into the I/O pad openings1679to make connections to the conductor level, including the lateral connectors1665aand1665b. In one version of this example, the top conductor level1604may be implemented as a bond pad level, and may include an adhesion sublayer of titanium or titanium tungsten, may include a pad sublayer of nickel or palladium, and may include a bonding surface metal of aluminum, gold, or platinum, by way of example. In another version of this example, the top conductor level1604may be implemented as an RDL, and may have a plated structure.

The top conductor level1604includes a first resistor1602of the top conductor level1604. The first resistor1602has a first wide portion1605and a first narrow portion1607. The first wide portion1605extends around one of the I/O pad openings1679, and the top conductor level metal extending into that I/O pad opening1679provides a first vertical connector1613from the first wide portion1605to the first lateral connector1665a. The first narrow portion1607extends around another of the I/O pad openings1679, and the top conductor level metal extending into that I/O pad opening1679provides a second vertical connector1615from the first narrow portion1607to the second lateral connector1665b.

The top conductor level1604also includes a first test terminal1624aand a second test terminal1624bof the top conductor level1604. The first test terminal1624aextends around a third of the I/O pad openings1679, and the top conductor level metal extending into that I/O pad opening1679provides a first test terminal connector1666afrom the first test terminal1624ato the first lateral connector1665a. Thus, the first test terminal1624ais coupled to the first wide portion1605through the first test terminal connector1666a, the first lateral connector1665a, and the first vertical connector1613. Similarly, the second test terminal1624bextends around a fourth of the I/O pad openings1679, and the top conductor level metal extending into that I/O pad opening1679provides a second test terminal connector1666bfrom the second test terminal1624bto the second lateral connector1665b. Thus, the second test terminal1624bis coupled to the first narrow portion1607through the second test terminal connector1666b, the second lateral connector1665b, and the second vertical connector1615. The first vertical connector1613, the second vertical connector1615, the first test terminal connector1666a, and the second test terminal connector1666bare members of a vertical connector level1619of the microelectronic device1600that connects members of the top conductor level1604to members of the conductor level that includes the lateral connectors1665aand1665b. The vertical connector level1619may be a bond pad via level or an RDL via level, conforming to the implementations for the top conductor level1604disclosed in this example.

A second resistor, not shown, of the RDAM1601and additional test terminals, also not shown, of the RDAM1601are formed concurrently with the first resistor1602and the test terminals1624aand1624b, and are coupled to the third and fourth lateral connectors in a similar configuration. The second resistor is a duplicate of the first resistor1602, reversed in direction. The RDAM1601enables estimation of a misalignment distance between the I/O pad openings1679and the bond pads of the microelectronic device1600.

FIG.17is a cross section of a microelectronic device with an example RDAM involving a buried layer. The microelectronic device1700may be manifested as any of the microelectronic device types disclosed in reference to the microelectronic device100ofFIG.1AandFIG.1B. The microelectronic device1700of this example is formed in and on a substrate1749that includes a semiconductor material1750having a first conductivity type. In this example, the first conductivity type may be p-type, as indicated inFIG.17.

A first resistor1702of the RDAM1701is formed in a buried layer level1704of the substrate1749. The first resistor1702has semiconductor material with a second conductivity type, opposite from the first conductivity type. In this example, in which the first conductivity type may be p-type, the second conductivity type may be n-type, as indicated inFIG.17. The buried layer level1704may include buried layers, not shown, also having the second conductivity type, in the substrate1749. The buried layers may provide isolation for components, buried collector for bipolar junction transistors, and source regions for junction field effect transistors, by way of example. The semiconductor material1750having the first conductivity type extends above the first resistor1702, as depicted inFIG.17. The first resistor1702includes a first wide portion1705and a first narrow portion1707. A second resistor, not shown, of the RDAM1701is formed in the buried layer level1704. The second resistor is a duplicate of the first resistor1702, having a second wide portion and a second narrow portion, reversed in direction. A field relief dielectric layer1751may be formed in and on the substrate1749.

A first vertical connector1713is formed through the field relief dielectric layer1751and through the semiconductor material1750over the first resistor1702, making contact to the first wide portion1705. A second vertical connector1715is formed through the field relief dielectric layer1751and the semiconductor material1750over the first resistor1702, making contact to the first narrow portion1707. The vertical connectors1713and1715are parts of a buried layer connector level of the microelectronic device1700, and may be implemented as deep trenches, having conductive cores1780laterally surrounded by insulating liners1781. The conductive cores1780may include polysilicon having the second conductivity type. The insulating liners1781may include silicon dioxide formed by thermal oxidation of silicon. A third vertical connector, not shown, is formed through the field relief dielectric layer1751and through the semiconductor material1750over the second resistor, making contact to the second wide portion. A fourth vertical connector, not shown, is formed through the field relief dielectric layer1751and through the semiconductor material1750over the second resistor, making contact to the second narrow portion. Additional deep trenches, not shown, may be formed concurrently with the first and second vertical connectors1713and1715, and the third and fourth vertical connectors, to provide electrical connections to the buried layers in the substrate1749.

A PMD layer1756may be formed over existing microelectronic device1700. Contacts1766are formed through the PMD layer1756to make electrical connections to the first and second vertical connectors1713and1715, and the third and fourth vertical connectors. The contacts1766may be formed as disclosed in reference to the vertical connector level1219ofFIG.12C. The contacts1766are part of a vertical interconnect level that includes additional contacts, which make connections to components of the microelectronic device1700.

A first test terminal1724ais formed over the PMD layer1756to make an electrical connection to the first vertical connector1713through one of the contacts1766. A second test terminal1724bis formed over the PMD layer1756to make an electrical connection to the second vertical connector1715through another of the contacts1766. A third test terminal, not shown, is formed over the PMD layer1756to make an electrical connection to the third vertical connector through a third instance of the contacts, and a fourth test terminal, not shown, is formed over the PMD layer1756to make an electrical connection to the third vertical connector through a fourth instance of the contacts. The RDAM1701enables estimation of a misalignment distance between buried layer connectors of the buried layer connector level and the buried layers in the microelectronic device1700.

FIG.18is a cross section of a microelectronic device with an example RDAM involving a two-dimensional electron gas (2DEG) in a III-V semiconductor device. For the purposes of this description, the term “III-V” is understood to refer to semiconductor materials in which group III elements, that is, aluminum, gallium, and indium, and possibly boron, provide a portion of the atoms in the semiconductor material and group V elements, that is, nitrogen, phosphorus, arsenic, and antimony provide another portion of the atoms in the semiconductor material. Examples of III-V semiconductor materials are gallium nitride, gallium arsenide, aluminum nitride, aluminum gallium nitride, indium phosphide, and indium antimonide. Terms describing elemental formulas of III-V materials do not imply a particular stoichiometry of the elements.

The microelectronic device1800of this example includes a base layer1850of III-V semiconductor material. The base layer1850is commonly referred to as an unintentionally doped (UID) layer. For gallium nitride devices, the base layer1850may be essentially gallium nitride. A carrier layer1882of III-V semiconductor material is formed on the base layer1850. The carrier layer1882may have a stoichiometry that is similar to, or the same as, a stoichiometry of an upper sub-layer of the base layer1850. A barrier layer1883is formed over the carrier layer1882. The barrier layer has a higher bandgap energy than the carrier layer1882, and has different composition than the carrier layer1882. For gallium nitride devices, the barrier layer1883may include aluminum nitride or aluminum gallium nitride. By way of example. The barrier layer1883exerts stress on the carrier layer1882, resulting in a 2DEG1884being formed in the carrier layer1882under the barrier layer1883. The 2DEG1884is electrically conductive, and is present even when the microelectronic device1800is unpowered. The 2DEG1884is a member of a 2DEG level which provides 2DEGs in field effect transistors of the microelectronic device1800

The barrier layer1883is patterned, for example by an RIE process using chlorine radicals. The carrier layer1882may also be patterned with the barrier layer1883, as depicted inFIG.18, or may be left unpatterned. Patterning the barrier layer1883results in the 2DEG1884having the same shape as the patterned barrier layer1883. The barrier layer1883is patterned so that the 2DEG1884provides a first resistor1802of the RDAM1801. The first resistor1802has a first wide portion1805and a first narrow portion1807. The barrier layer1883is concurrently patterned in other areas of the microelectronic device1800to form components such as transistors. The 2DEG1884is thus a part of a conductor level of 2DEGs in the microelectronic device. A second resistor, not shown, of the RDAM1801is formed concurrently with the first resistor1802. The second resistor is a duplicate of the first resistor1802, reversed in direction.

A first vertical connector1813is formed through the barrier layer1883to make an electrical connection to the first resistor1802, that is, to the 2DEG1884, in the first wide portion1805. A second vertical connector1815is formed through the barrier layer1883to make an electrical connection to the first resistor1802in the first narrow portion1807. The vertical connectors1813and1815are parts of a vertical connector level of the microelectronic device1800that includes source/drain contacts to field effect transistors (FETs). A third vertical connector, not shown, is formed through the barrier layer1883over the second resistor, making contact to the second wide portion. A fourth vertical connector, not shown, is formed through the barrier layer1883over the second resistor, making contact to the second narrow portion. Additional contacts, not shown, may be formed concurrently with the first and second vertical connectors1813and1815, and the third and fourth vertical connectors, to provide electrical connections to the 2DEGs in the carrier layer1882.

Test terminals1824are formed to make electrical connections to the first and second vertical connectors1813and1815, and the third and fourth vertical connectors. The test terminals1824may be formed concurrently with interconnects to the source/drain contacts in the microelectronic device1800. The test terminals1824may include an adhesion layer containing titanium and a bonding layer containing aluminum, by way of example. The RDAM1801enables estimation of a misalignment distance between source/drain contacts of the vertical connector level and the barrier layers in the microelectronic device1800.

FIG.19is a top view of a cross bridge test structure used to estimate sheet resistance and to estimate a line width correction. The estimated sheet resistance and line width correction may be applied to the method disclosed in reference toFIG.2to obtain a more accurate estimate of the misalignment distance. A microelectronic device1900includes at least one RDAM, not shown, having a first resistor and a second resistor of a conductor level, with vertical connectors which are members of a vertical connector level. The microelectronic device1900of this example includes the cross bridge test structure1985formed on a substrate1949. The cross bridge test structure1985includes a cross resistor1986formed in the conductor level that contains the first resistor and the second resistor of the RDAM. The cross bridge test structure1985also includes six test terminal connectors1966a,1966b,1966c,1966d,1966e, and1966fthat make electrical connections to the cross resistor1986. Test terminal connectors1966athrough1966dcontact the cross resistor1986on four branches around an intersection1987of the cross resistor1986. Test terminal connectors1966d,1966e, and1966fcontact the cross resistor1986along a linear branch, in the order listed. Test terminal connectors1966dand1966eare separated by a bridge length Lbridge, as shown inFIG.19. The cross resistor1986has a design bridge width Wbridgealong the bridge length Lbridge, as shown inFIG.19. The bridge length Lbridgeis at least 4 times the design bridge length Lbridge, to obtain an accurate estimate of the line width of the cross resistor1986. Test terminals1924a,1924b,1924c,1924d,1924e, and1924fare coupled to the test terminal connectors1966athrough1966f, respectively.

The sheet resistance of the cross resistor1986may be estimated by forcing currents through adjacent pairs of the test terminals1924athrough1924dand measuring potential differences across remaining pairs of the test terminals1924athrough1924d, dividing the potential differences by the corresponding currents to obtain resistances, and averaging the resistances to obtain an average resistance Ravg. The sheet resistance Rsheetmay be estimated as Rsheet=π Ravg/ln(2), where π is approximately 3.14159, and ln(2) is the natural logarithm of 2, approximately 0.693147. More complex methods of estimating the sheet resistance using the potential differences and the corresponding currents are within the scope of this example. The sheet resistance Rsheetmay be used in the method disclosed in reference toFIG.2to obtain a more accurate estimate of the misalignment distance.

The line width of the cross resistor1986along the bridge length Lbridgemay be estimated by forcing a current through the test terminals1924cand1924fand measuring a potential difference across the test terminals1924dthrough1924e, dividing the potential difference by the current to obtain a bridge resistance Rbridge. A corrected line width Wcorrmay be estimated as Wcorr=[Lbridge(Rsheet/Rbridge)]. The values for Wwideand Wnarras used in the method disclosed in reference toFIG.2may be corrected by adding a line width correction ΔW=Wcorr−Wbridgeto obtain a more accurate estimate of the misalignment distance.

FIG.20is a top view of a three-resistor test structure used to estimate sheet resistance and to estimate a line width correction. The estimated sheet resistance and line width correction may be applied to the method disclosed in reference toFIG.2to obtain a more accurate estimate of the misalignment distance. A microelectronic device2000includes at least one RDAM, not shown, having a first resistor and a second resistor of a conductor level, with vertical connectors which are members of a vertical connector level. The microelectronic device2000of this example includes the three-resistor test structure2085formed on a substrate2049. The three-resistor test structure2085includes a first resistor2086a, a second resistor2086b, and a third resistor2086c. The three resistors2086a,2086b, and2086care formed in the conductor level that contains the first resistor and the second resistor of the RDAM.

The three-resistor test structure2085includes first test terminal connectors2066aon each end of the first resistor2086a. The first resistor2086ahas a first body length L1between the first test terminal connectors2066a, with a first design body width W1,des. The three-resistor test structure2085includes second test terminal connectors2066bon each end of the second resistor2086b. The second resistor2086bhas a second body length L2between the second test terminal connectors2066b, with a second design body width W2,des. The three-resistor test structure2085includes third test terminal connectors2066con each end of the third resistor2086c. The third resistor2086chas a third body length L3between the third test terminal connectors2066c, with a third design body width W3,des. The design body widths W1,des, W2,des, and W3,desare the designed widths of the three resistors2086a,2086b, and2086c. A line width correction ΔW to the design body widths W1,des, W2,des, and W3,desis defined as a difference between physical body widths of the three resistors2086a,2086b, and2086cand the design body widths W1,des, W2,des, and W3,des, and may be estimated using the three-resistor test structure2085. The body lengths L1, L2, and L3are not all equal, and the design body widths W1,des, W2,des, and W3,desare not all equal. No two of the three resistors2086a,2086b, and2086chave equal body lengths and equal design body widths, that is, no two of the three resistors2086a,2086b, and2086care duplicates of each other. In one version of this example, the first body length L1may equal the second body length L2, and the third body length L3may be 2 times the first body length L1. In the same version of this example, the first body length L1may equal the second body length L2, and the third body length L3may be 2 times the first body length L1.

First test terminals2024aare coupled to the test terminal connectors2066ato enable measuring a first total resistance R1,totof the first resistor2086aand the first test terminal connectors2066a. Second test terminals2024bare coupled to the test terminal connectors2066bto enable measuring a second total resistance R2,totof the second resistor2086band the second test terminal connectors2066b. Third test terminals2024care coupled to the test terminal connectors2066cto enable measuring a third total resistance R3,totof the third resistor2086cand the third test terminal connectors2066c. The total resistance Rn,totof each of the three resistors2086a,2086b, and2086cis a sum of a head resistance Rn,headand a body resistance Rn,body, where index n=1, 2, 3 corresponds to the three resistors2086a,2086b, and2086c.

The head resistance Rn,headincludes the resistance of the test terminal connectors2066a,2066b, and2066c, an interface resistance between the test terminal connectors2066a,2066b, and2066cand the corresponding resistors2086a,2086b, and2086c, and a resistance of the resistors2086a,2086b, and2086coutside of the body lengths L1, L2, and L3. The head resistance Rn,headis taken to be inversely proportional to the corresponding design body width Wn,des. The head resistance Rn,headmay be expressed as Rn,head=R′head/Wn,des, where R′headis a head resistivity, and is a constant that is characteristic of the head resistance Rn,head.

The body resistance Rn,bodyis proportional to the corresponding body length Lnand the sheet resistance Rsheetof the resistors2086a,2086b, and2086c, and inversely proportional to the corresponding corrected design body width Wn,des−ΔW. The body resistance Rn,bodymay be expressed as Rn,body=Ln×Rsheet/(Wn,des−ΔW).

Thus, the total resistance Rn,totof each of the three resistors2086a,2086b, and2086c, which may be measured using the corresponding test terminals2024athrough2024c, may be expressed in terms of three unknown variables: the head resistivity R′head, the sheet resistance Rsheet, and the line width correction ΔW, and known parameters: the body length Lnand the design body width Wn,des. That is, Rn,tot=(R′head/Wn,des) [Ln×Rsheet/(Wn,des−ΔW)]. Measuring the three resistors2086a,2086b, and2086cprovides three independent equations for Rn,tot, which may be solved for the three unknown variables. The sheet resistance Rsheet, may be used in the method disclosed in reference toFIG.2to obtain a more accurate estimate of the misalignment distance. The values for Wwideand Wnarras used in the method disclosed in reference toFIG.2may be corrected by subtracting the line width correction ΔW to obtain a more accurate estimate of the misalignment distance.

FIG.21AandFIG.21Bare top views of an example microelectronic device including RDAMs, depicted in stages of formation. Referring toFIG.21A, the microelectronic device2100is formed in and on a substrate2149concurrently with additional microelectronic devices2100a. The microelectronic device2100and the additional microelectronic devices2100amay be manifested as any of the microelectronic device types disclosed in reference to the microelectronic device100ofFIG.1AandFIG.1B. The substrate2149may be implemented as a semiconductor wafer, a glass, sapphire, or polymer substrate for MEMS or microfluidic devices, or a composite substrate including both semiconductor material and dielectric material, by way of example. The microelectronic device2100contains components, labeled “COMPONENTS” inFIG.21AandFIG.21B.

The microelectronic device2100and the additional microelectronic devices2100amay have scribe seals2188and2188a, respectively, surrounding the components. The scribe seals2188and2188amay include continuous interconnects and continuous vias or dense discrete vias, to reduce crack propagation and impurity infiltration into the components. Singulation lanes2189, commonly referred to as scribe lanes or streets, saw lanes or streets, dicing lanes or streets, extend between the microelectronic device2100and the additional microelectronic devices2100a. The singulation lanes2189may extend to the scribe seals2188and2188a, or may extend partway to the scribe seals2188and2188a.

The microelectronic device2100of this example includes an internal RDAM2101alocated inside the scribe seal2188. The internal RDAM2101aincludes a first internal resistor2102aand a second internal resistor2103a, and vertical connectors, not shown, formed according to any of the examples disclosed herein. The internal RDAM2101aincludes internal test terminals2124acoupled to the vertical connectors. The internal test terminals2124amay extend to probe pads at a top surface of the microelectronic device2100, to enable probing after fabrication of the microelectronic device2100is completed, or may extend to bond pads to enable wire bonding the internal test terminals2124aduring assembly of the microelectronic device2100to allow testing the internal RDAM2101aafter packaging the microelectronic device2100. The internal test terminals2124amay be coupled to the vertical connectors through a multiplexer, labeled “MUX” inFIG.21AandFIG.21B. The multiplexer may advantageously enable testing a plurality of test structures using a relatively small number of probe/bond pads. The internal RDAM2101amay be referred to as an on-chip parametric (OCP) test structure.

The microelectronic device2100of this example also includes external RDAMs2101blocated outside of the scribe seal2188, in corner regions. The external RDAMs2101bmay be located in areas of the microelectronic device2100that experience high stress, such as corners of the microelectronic device2100, and thus do not contain components. The external RDAMs2101bmay be formed according to any of the examples disclosed herein. The external RDAMs2101bmay also be referred to as OCP test structures.

The microelectronic device2100of this example further includes singulation lane RDAMs2101clocated outside the scribe seals2188and2188a, on sides of the microelectronic device2100. The singulation lane RDAMs2101cmay extend into the singulation lanes2189, as depicted inFIG.21AandFIG.21B. The singulation lane RDAMs2101cmay be formed according to any of the examples disclosed herein. The singulation lane RDAMs2101cmay be tested during and after fabrication of the microelectronic device2100, before the microelectronic device2100is singulated from the additional microelectronic devices2100a.

Referring toFIG.21B, at least a portion of the substrate2149is removed from the singulation lanes2189, singulating the microelectronic device2100from the additional microelectronic devices2100a. The internal RDAM2101aremains in place in the microelectronic device2100after the microelectronic device2100is singulated. Similarly, the external RDAMs2101bremain in place in the microelectronic device2100after the microelectronic device2100is singulated. One or more portions, or all, of one or more of the singulation lane RDAMs2101cmay remain in the singulated microelectronic device2100. The portions of the singulation lane RDAMs2101cmay be present in the microelectronic device2100after packaging, that is, connection to external leads and encapsulation, for example, is completed.

Various features of the examples disclosed herein may be combined in other manifestations of example microelectronic devices. For example, any of the RDAMs disclosed herein may have single resistors, as disclosed in reference toFIG.1A, or may have a plurality of resistors connected serially, as depicted disclosed in reference toFIG.4. Any of the RDAMs disclosed herein may include a reference resistor pair, as disclosed in reference toFIG.3. Any of the RDAMs disclosed herein may have resistors and vertical connectors configured as disclosed in reference toFIG.6throughFIG.11. Any of the RDAMs disclosed herein may have resistors formed in an interconnect level, a gate level, a diffused layer level in a semiconductor substrate, a resistor level, a capacitor plate level, a bond pad level, an RDL level, a buried layer level in a semiconductor substrate, or a 2DEG level in a III-V semiconductor material. Any of the microelectronic devices disclosed herein may include one or more RDAMs configured to measure a misalignment distance in one direction or in two orthogonal directions. Any of the microelectronic devices disclosed herein may include a cross bridge test structure, as disclosed in reference toFIG.19. Any of the microelectronic devices disclosed herein may include a three-resistor test structure, as disclosed in reference toFIG.20.