In one embodiment, transistor device includes a first source or drain material on a substrate, a semiconductor material on the first source or drain material, a second source or drain material on the semiconductor material, a dielectric layer on the substrate and adjacent the first source or drain material, a ferroelectric (FE) material on the dielectric layer and adjacent the semiconductor material, and a gate material on or adjacent to the FE material. The FE material may be a perovskite material and may have a lattice parameter that is less than a lattice parameter of the semiconductor material.

BACKGROUND

In current ferroelectric field-effect transistor (FeFET) devices, the ferroelectric (FE) material layers (e.g., perovskite materials, such as BaTiO3or BaFeO3) may be epitaxially deposited on a semiconductor template material with a larger lattice constant. The tensile strain caused by this can force the polarization of the FE material to be in-plane, i.e., in the same direction as the channel between the source/drain regions of the device, which is not ideal for FeFET devices.

DETAILED DESCRIPTION

Embodiments herein describe vertical FeFET devices in which the source/drain regions of the device are above and below a semiconductor channel layer (in a vertical stack), with a ferroelectric (FE) material layer adjacent to the semiconductor channel layer. For example, in certain embodiments, perovskite FE materials such as BaTiO3and BiFeO3may be epitaxially deposited together with an oxide semiconductor layer, such as (La—Ba)SnO3, which has a larger lattice constant/lattice parameter than the perovskite FE materials. As used herein, (A-B) (e.g., La—Ba) may refer to elements A and B in proportions AxB(1-x)(e.g., LaxBa(1-x)SnO3). The relative difference in the lattice constant/lattice parameters of the materials along with their positioning allows the polarization of the perovskite FE material to be perpendicular to the channel between the source/drain regions in which current flows, which can lead to more ideal FeFET device properties. For example, some embodiments may allow for decreased operating voltage of FeFET devices, increased density of transistors on an integrated circuit device, three-dimensional scalability, or ferroelectric non-volatile memory applications.

FIG.1illustrates an example conventional FeFET device100. The example device100includes a substrate102with an oxide semiconductor material104formed on the substrate102and source/drain regions105adjacent the oxide semiconductor material104on either side. The device100also includes an FE material106on the oxide semiconductor material104, and a gate contact108on the FE material106. As used herein, a “source/drain region” or “source/drain material” may refer to a region or material that may be implemented either as a source or drain of a transistor device, depending on the implementation of the device (e.g., voltages applied to the respective source/drain regions or source/drain materials). For example, in some implementations, the source/drain region105A may be implemented as a source of the device100and the source/drain region105B may be implemented as a drain of the device100, while in other implementations, the source/drain region105A may be implemented as a drain of the device100and the source/drain region105B may be implemented as a source of the device100.

FeFET devices may be used to store information based on the polarization of the FE material106, and the polarization of the FE material106may be based on application of a voltage to the gate contact108. In current FeFET designs, e.g., those using non-perovskite FE materials and Group III-V semiconductor materials, the polarization of the FE material106is in the vertical direction with respect toFIG.1, i.e., pointing either toward or away from the semiconductor material104and generally perpendicular to the direction of current in the channel within the semiconductor material104.

Certain materials, such as (La—Ba)SnO3, have emerged as a promising candidate for oxide semiconductor channels in FeFET devices (e.g., semiconductor material104of the device100) because of its high mobility and oxygen stability. FeFET devices using (La—Ba)SnO3and a perovskite FE material may lead to decreased operating voltages due to the small coercivity of perovskite ferroelectrics. However, (La—Ba)SnO3has the highest mobility when it is grown epitaxially on a lattice-matched substrate and the lattice parameter of (La—Ba)SnO3(4.116 A) is significantly larger than that of FE perovskites (e.g., in-plane lattice parameter of BaTiO3is 3.99 A, and the lattice parameter of BiFeO3is 3.96 A). When these perovskite FE materials are grown with such a large tensile strain, the polarization of the FE material points in-plane (e.g., as shown inFIG.1, generally in parallel with the direction of current in the semiconductor channel). This can limit the application to deplete channel of a (La—Ba)SnO3semiconductor material directly below it, which in turn limits three-dimensional (3D) scaling if FET architectures, such as the one shown inFIG.1, are used.

A vertical FeFET structure as described herein may overcome these or other issues, and could allow the in-plane polarization to be utilized to deplete a channel as well as allow 3D stacking of the device(s). This could also benefit the electrical properties of the (La—Ba)SnO3channel material as it could allow it to be grown in a superlattice structure with the source/drain regions having similar lattice constants/lattice parameter, such as metallic higher doped (La—Ba)SnO3, which can lead to fewer defects in the channel and therefore higher mobility. The example vertical FeFET devices described herein may be used as a transistor in an integrated circuit device (e.g., as a transistor840in the integrated circuit device800ofFIG.8).

FIG.2illustrates an example vertical FeFET device200in accordance with embodiments herein. The example device200includes a substrate/templating layer202(hereinafter referred to as just a substrate) with a channel stack201formed thereon. The channel stack201includes a first source/drain region205B formed on the substrate202, a semiconductor layer204formed on the source/drain region205B, and a second source/drain region205A formed on the semiconductor layer204. The device200also includes a gate stack211formed on the substrate202, which includes a first dielectric layer210A formed on the substrate202adjacent to the source/drain region205B, a FE material206formed on the dielectric layer210A and adjacent the semiconductor material204, a gate contact208formed on the dielectric layer210A and adjacent the FE material206, and a second dielectric layer210B formed on the FE material206and the gate contact208. In certain embodiments the channel stack201may be grown first, and the gate stack211grown thereafter. In other embodiments, the gate stack211may be grown first, and the channel stack201grown thereafter.

The FE material206may be a perovskite material, and the semiconductor material204may be selected such that the lattice parameter of the semiconductor material204is larger than the lattice parameter of the FE material206. The perovskite FE material206may accordingly grow with a large tensile strain that causes the polarization of the FE material206to point in-plane as shown inFIG.2, which causes the direction to be generally perpendicular with the direction of current in the semiconductor channel as shown. Example semiconductor materials for use in the semiconductor layer204include a doped BaSnO3(e.g., doped with La or other dopants such as neodymium (Nd)), doped SrTiO3(e.g., doped with La or other dopants such as Nd), IGZO (Indium Gallium Zinc Oxide), LaNiO3, SrSnO3, or (Ba—Sr)SnO3, and example perovskite FE materials for use in FE material layer206include BaTiO3, Ba(Zr—Ti)O3, (Ba—Ca)TiO3, (Ba—Sr)TiO3, (Ba—Ca)(Ti—Zr)O3, BiFeO3, (Bi—La)FeO3, Bi(Fe—Co)O3, LiNbO3, or KNbO3.

The substrate202may include a template material (e.g., an oxide template material), which may be lattice-matched to one or more of the materials grown thereon. The substrate202may be formed, for example, from SrTiO3, GdScO3, DyScO3, LaAlO3, BaHfO3, BaZrO3, SrZrO3, SrHfO3, LaInO3, LaScO3, LaLuO3, La(LuSc)O3, or MgO. In some embodiments, the substrate202may be a templating material layer that is formed on a conventional Silicon-based (e.g., SiO2) or similar type of substrate material (not shown).

FIG.3illustrates an example dual gate vertical FeFET device300in accordance with embodiments herein. The configuration of the example device300is similar to the device200ofFIG.2, but with gate stacks311A,311B on each side of the channel stack301. The channel stack301is the same as the channel stack201and includes a first source/drain region305B formed on the substrate302, a semiconductor layer304formed on the source/drain region305B, and a second source/drain region305A formed on the semiconductor layer304. Likewise, each gate stack311A/311B includes a first dielectric layer310A/310C formed on the substrate302and adjacent to the source/drain region305B, a FE material306A/B formed on the dielectric layer310A/310C and adjacent the semiconductor material304, a gate contact308A/308B formed on the dielectric layer310A/310C and adjacent the FE material306, and a second dielectric layer310B/310D formed on the FE material306A/306B and the gate contact308A/308B.

The top ofFIG.3illustrates top views of different example configurations for the side view shown in the bottom ofFIG.3. In the top configuration shown, the width of the semiconductor material304spans the entirety of the FE material306, while in the bottom configuration shown, the semiconductor material304is surrounded by the FE material306on all sides. In certain embodiments, the source/drain regions305may have a similar configuration to the FE material306as that of the semiconductor material304. For instance, in the bottom configuration shown, both the semiconductor material304and the source/drain regions305above and below the semiconductor material304may be surrounded by the FE material306.

Like the example shown inFIG.2, in certain embodiments, the channel stack301may be formed first before the gate stacks311are formed on either side, while in other embodiments, the gate stacks311may be formed first before the channel stack301. The gate stacks311A,311B may be formed at the same time as each other. The materials used for the source/drain regions305and the semiconductor layer304may be the same as those described above with respect to the same components (e.g., the FE materials306may use the same example materials described above with respect to the FE material206and the semiconductor material304may use the same example materials described above with respect to the semiconductor material204).

FIG.4Aillustrates an example stacked vertical FeFET device400in accordance with embodiments herein. The example device400is similar to the device200but has an additional semiconductor material layer and source/drain region within its channel stack401, and a corresponding additional FE material and gate contact portion in the gate stack411. Although one additional stack layer is shown in each of the channel stack401and gate stack411(i.e., one additional semiconductor layer and source/drain layer for the channel stack401, and one additional FE material in the gate stack adjacent the additional semiconductor layer and source/drain layer), other embodiments may include additional stack layers. For example, a device may include two, three, four, five, or more additional stack layers, repeating the same pattern as shown inFIG.4A.

The channel stack401includes a first source/drain region405C formed on the substrate402, a first semiconductor layer404B formed on the source/drain region405C, a second source/drain region405B formed on the first semiconductor layer404B, a second semiconductor layer404A formed on the source/drain region405B, and a third source/drain region405A formed on the second semiconductor layer404A. The gate stack411includes a respective FE material layer406A/406B adjacent each semiconductor layer404A/404B, and a gate contact408that is in contact with each of the FE material layers406A,406B with a dielectric410surrounding and isolating the FE material layers.

As in the previous examples, in certain embodiments, the channel stack401may be formed first before the gate stack411is formed, while in other embodiments, the gate stack411may be formed first before the channel stack401. The materials used for each of the various layers/portions of the device400may be the same as those described above with respect to the same components (e.g., the FE materials406may use the same example materials described above with respect to the FE material206and the semiconductor materials404may use the same example materials described above with respect to the semiconductor material204).

FIG.4Billustrates the example stacked vertical FeFET device400ofFIG.4A, but with a dielectric layer412between two middle source/drain regions405BA and405BB.

FIG.5Aillustrates an example stacked, dual-gate vertical FeFET device500in accordance with embodiments herein. The configuration of the example device500is similar to the device400ofFIGS.4A-4B, but with gate stacks511A,511B on each side of the channel stack501. The channel stack501is the same as the channel stack401and includes a first source/drain region505C formed on the substrate502, a first semiconductor layer504B formed on the source/drain region505C, a second source/drain region505B formed on the first semiconductor layer504B, a second semiconductor layer504A formed on the source/drain region505B, and a third source/drain region505A formed on the second semiconductor layer504A. The gate stacks511A/511B include a respective FE material layer adjacent each semiconductor layer (506A and506C adjacent504A, and506B and506D adjacent504B), and a gate contact508A/508B that is in contact with each of the FE material layers in the respective gate stack. Each gate stack511A/511B also includes a dielectric510A/510B surrounding and isolating the FE material layers in the respective gate stack.

Like the example shown inFIGS.4A-4B, in certain embodiments, the channel stack501may be formed first before the gate stacks511are formed on either side, while in other embodiments, the gate stacks511may be formed first before the channel stack501. The gate stacks511A,511B may be formed at the same time as each other. The materials used for the source/drain regions505and the semiconductor layer504may be the same as those described above with respect to the same components (e.g., the FE materials506may use the same example materials described above with respect to the FE material406and the semiconductor material504may use the same example materials described above with respect to the semiconductor material404).

FIG.5Billustrates the example FeFET device500ofFIG.5A, but with a dielectric layer512between two middle source/drain regions405BA and405BB.

FIG.6illustrates an example process600of manufacturing a vertical FeFET in accordance with embodiments herein. The example process shown may include additional, fewer, or different operations than those shown or described below. In some embodiments, one or more of the operations shown inFIG.6include multiple operations, sub-operations, etc.

At610, a channel stack (e.g.,201,301,401,501) of the vertical FeFET is formed. This may include forming, at612, a first source/drain region (e.g.,205B,305B,405C,505C) on a substrate (e.g.,202,302,402,502), forming, at614, a semiconductor material layer (e.g.,204,304,404B,504B) on the first source/drain region, and forming, at616, a second source/drain region (e.g.,205A,305A,405B,505B) on the semiconductor material. In certain embodiments, additional layers may be formed within the channel stack, e.g., forming an additional semiconductor material layer (e.g.,404A,504A) on the second source/drain region, and forming an additional source/drain region (e.g.,405A,505A) on the second semiconductor material layer, and so on for as many layers as designed. Each of the respective materials may be chosen from the examples of each type of material described above.

At620, one or more gate stacks (e.g.,211,311A.311B,411,511A,511B) of the vertical FeFET are formed adjacent the channel stack formed at610. This may include forming, at622, a first dielectric layer (e.g.,210A,310A,310C) on the substrate, forming, at624, an FE material (e.g.,206,306A,306B,406B,506B,506D) on the first dielectric layer and adjacent the semiconductor material, forming, at626, a gate contact (e.g.,208,308A,308B) on the first dielectric layer and adjacent the FE material (e.g., on an opposite side of the FE material from the semiconductor material), and forming, at628, a second dielectric layer (e.g.,210B,310B,310D) on the FE material and gate contact and adjacent the second source/drain region. In certain embodiments, additional layers may be formed within each gate stack, e.g., forming an additional FE material layer (e.g.,406A,506A) and gate contact on the second dielectric layer, and forming an additional dielectric layer above the additional FE material and gate contact, and so on for as many layers as designed. Each of the respective materials may be chosen from the examples of each type of material described above. In embodiments where multiple gate stacks are implemented, each gate stack may be formed simultaneously, e.g., each respective layer of the gate stack is formed at the same time, or each gate stack may be formed at different times.

FIG.7is a top view of a wafer700and dies702that may incorporate any of the embodiments disclosed herein. The wafer700may be composed of semiconductor material and may include one or more dies702having integrated circuit structures formed on a surface of the wafer700. The individual dies702may be a repeating unit of an integrated circuit product that includes any suitable integrated circuit. After the fabrication of the semiconductor product is complete, the wafer700may undergo a singulation process in which the dies702are separated from one another to provide discrete “chips” of the integrated circuit product. The die702may include one or more transistors (e.g., some of the transistors840ofFIG.8, discussed below), supporting circuitry to route electrical signals to the transistors, passive components (e.g., signal traces, resistors, capacitors, or inductors), and/or any other integrated circuit components. In some embodiments, the wafer700or the die702may include a memory device (e.g., a random access memory (RAM) device, such as a static RAM (SRAM) device, a magnetic RAM (MRAM) device, a resistive RAM (RRAM) device, a conductive-bridging RAM (CBRAM) device, etc.), a logic device (e.g., an AND, OR, NAND, or NOR gate), or any other suitable circuit element. Multiple ones of these devices may be combined on a single die702. For example, a memory array formed by multiple memory devices may be formed on a same die702as a processor unit (e.g., the processor unit1002ofFIG.10) or other logic that is configured to store information in the memory devices or execute instructions stored in the memory array.

FIG.8is a cross-sectional side view of an integrated circuit device800that may be included in any of the embodiments disclosed herein. One or more of the integrated circuit devices800may be included in one or more dies702(FIG.7). The integrated circuit device800may be formed on a die substrate802(e.g., the wafer700ofFIG.7) and may be included in a die (e.g., the die702ofFIG.7). The die substrate802may be a semiconductor substrate composed of semiconductor material systems including, for example, n-type or p-type materials systems (or a combination of both). The die substrate802may include, for example, a crystalline substrate formed using a bulk silicon or a silicon-on-insulator (SOI) substructure. In some embodiments, the die substrate802may be formed using alternative materials, which may or may not be combined with silicon, that include, but are not limited to, germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide. Further materials classified as group II-VI, III-V, or IV may also be used to form the die substrate802. Although a few examples of materials from which the die substrate802may be formed are described here, any material that may serve as a foundation for an integrated circuit device800may be used. The die substrate802may be part of a singulated die (e.g., the dies702ofFIG.7) or a wafer (e.g., the wafer700ofFIG.7).

The integrated circuit device800may include one or more device layers804disposed on the die substrate802. The device layer804may include features of one or more transistors840(e.g., metal oxide semiconductor field-effect transistors (MOSFETs) or ferroelectric field-effect transistors (FeFETs), e.g., those described herein) formed on the die substrate802. The transistors840may include, for example, one or more source and/or drain (S/D) regions820, a gate822to control current flow between the S/D regions820, and one or more S/D contacts824to route electrical signals to/from the S/D regions820. The transistors840may include additional features not depicted for the sake of clarity, such as device isolation regions, gate contacts, and the like. The transistors840are not limited to the type and configuration depicted inFIG.8and may include a wide variety of other types and configurations such as, for example, planar transistors, non-planar transistors, or a combination of both. Non-planar transistors may include FinFET transistors, such as double-gate transistors or tri-gate transistors, and wrap-around or all-around gate transistors, such as nanoribbon, nanosheet, or nanowire transistors.

Returning toFIG.8, the example transistor840may include a gate822formed of at least two layers, a gate dielectric and a gate electrode. The gate dielectric may include one layer or a stack of layers. The one or more layers may include silicon oxide, silicon dioxide, silicon carbide, and/or a high-k dielectric material. However, in other embodiments, the transistors840may be FeFETs that are formed as described in detail above.

The gate electrode may be formed on the gate dielectric and may include at least one p-type work function metal or n-type work function metal, depending on whether the transistor840is to be a p-type metal oxide semiconductor (PMOS) or an n-type metal oxide semiconductor (NMOS) transistor. In some implementations, the gate electrode may consist of a stack of two or more metal layers, where one or more metal layers are work function metal layers and at least one metal layer is a fill metal layer. Further metal layers may be included for other purposes, such as a barrier layer.

For a PMOS transistor, metals that may be used for the gate electrode include, but are not limited to, ruthenium, palladium, platinum, cobalt, nickel, conductive metal oxides (e.g., ruthenium oxide), and any of the metals discussed below with reference to an NMOS transistor (e.g., for work function tuning). For an NMOS transistor, metals that may be used for the gate electrode include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, carbides of these metals (e.g., hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide), and any of the metals discussed above with reference to a PMOS transistor (e.g., for work function tuning).

The S/D regions820may be formed within the die substrate802adjacent to the gate822of individual transistors840. The S/D regions820may be formed using an implantation/diffusion process or an etching/deposition process, for example. In the former process, dopants such as boron, aluminum, antimony, phosphorous, or arsenic may be ion-implanted into the die substrate802to form the S/D regions820. An annealing process that activates the dopants and causes them to diffuse farther into the die substrate802may follow the ion-implantation process. In the latter process, the die substrate802may first be etched to form recesses at the locations of the S/D regions820. An epitaxial deposition process may then be carried out to fill the recesses with material that is used to fabricate the S/D regions820. In some implementations, the S/D regions820may be fabricated using a silicon alloy such as silicon germanium or silicon carbide. In some embodiments, the epitaxially deposited silicon alloy may be doped in situ with dopants such as boron, arsenic, or phosphorous. In some embodiments, the S/D regions820may be formed using one or more alternate semiconductor materials such as germanium or a group III-V material or alloy. In further embodiments, one or more layers of metal and/or metal alloys may be used to form the S/D regions820.

Electrical signals, such as power and/or input/output (I/O) signals, may be routed to and/or from the devices (e.g., transistors840) of the device layer804through one or more interconnect layers disposed on the device layer804(illustrated inFIG.8as interconnect layers806-810). For example, electrically conductive features of the device layer804(e.g., the gate822and the S/D contacts824) may be electrically coupled with the interconnect structures828of the interconnect layers806-810. The one or more interconnect layers806-810may form a metallization stack (also referred to as an “ILD stack”)819of the integrated circuit device800.

The interconnect structures828may be arranged within the interconnect layers806-810to route electrical signals according to a wide variety of designs; in particular, the arrangement is not limited to the particular configuration of interconnect structures828depicted inFIG.8. Although a particular number of interconnect layers806-810is depicted inFIG.8, embodiments of the present disclosure include integrated circuit devices having more or fewer interconnect layers than depicted.

In some embodiments, the interconnect structures828may include lines828aand/or vias828bfilled with an electrically conductive material such as a metal. The lines828amay be arranged to route electrical signals in a direction of a plane that is substantially parallel with a surface of the die substrate802upon which the device layer804is formed. For example, the lines828amay route electrical signals in a direction in and out of the page and/or in a direction across the page from the perspective ofFIG.8. The vias828bmay be arranged to route electrical signals in a direction of a plane that is substantially perpendicular to the surface of the die substrate802upon which the device layer804is formed. In some embodiments, the vias828bmay electrically couple lines828aof different interconnect layers806-810together.

The interconnect layers806-810may include a dielectric material826disposed between the interconnect structures828, as shown inFIG.8. In some embodiments, dielectric material826disposed between the interconnect structures828in different ones of the interconnect layers806-810may have different compositions; in other embodiments, the composition of the dielectric material826between different interconnect layers806-810may be the same. The device layer804may include a dielectric material826disposed between the transistors840and a bottom layer of the metallization stack as well. The dielectric material826included in the device layer804may have a different composition than the dielectric material826included in the interconnect layers806-810; in other embodiments, the composition of the dielectric material826in the device layer804may be the same as a dielectric material826included in any one of the interconnect layers806-810.

A first interconnect layer806(referred to as Metal 1 or “M1”) may be formed directly on the device layer804. In some embodiments, the first interconnect layer806may include lines828aand/or vias828b, as shown. The lines828aof the first interconnect layer806may be coupled with contacts (e.g., the S/D contacts824) of the device layer804. The vias828bof the first interconnect layer806may be coupled with the lines828aof a second interconnect layer808.

The second interconnect layer808(referred to as Metal 2 or “M2”) may be formed directly on the first interconnect layer806. In some embodiments, the second interconnect layer808may include via828bto couple the lines828of the second interconnect layer808with the lines828aof a third interconnect layer810. Although the lines828aand the vias828bare structurally delineated with a line within individual interconnect layers for the sake of clarity, the lines828aand the vias828bmay be structurally and/or materially contiguous (e.g., simultaneously filled during a dual-damascene process) in some embodiments.

The third interconnect layer810(referred to as Metal 3 or “M3”) (and additional interconnect layers, as desired) may be formed in succession on the second interconnect layer808according to similar techniques and configurations described in connection with the second interconnect layer808or the first interconnect layer806. In some embodiments, the interconnect layers that are “higher up” in the metallization stack819in the integrated circuit device800(i.e., farther away from the device layer804) may be thicker that the interconnect layers that are lower in the metallization stack819, with lines828aand vias828bin the higher interconnect layers being thicker than those in the lower interconnect layers.

The integrated circuit device800may include a solder resist material834(e.g., polyimide or similar material) and one or more conductive contacts836formed on the interconnect layers806-810. InFIG.8, the conductive contacts836are illustrated as taking the form of bond pads. The conductive contacts836may be electrically coupled with the interconnect structures828and configured to route the electrical signals of the transistor(s)840to external devices. For example, solder bonds may be formed on the one or more conductive contacts836to mechanically and/or electrically couple an integrated circuit die including the integrated circuit device800with another component (e.g., a printed circuit board). The integrated circuit device800may include additional or alternate structures to route the electrical signals from the interconnect layers806-810; for example, the conductive contacts836may include other analogous features (e.g., posts) that route the electrical signals to external components.

In some embodiments in which the integrated circuit device800is a double-sided die, the integrated circuit device800may include another metallization stack (not shown) on the opposite side of the device layer(s)804. This metallization stack may include multiple interconnect layers as discussed above with reference to the interconnect layers806-810, to provide conductive pathways (e.g., including conductive lines and vias) between the device layer(s)804and additional conductive contacts (not shown) on the opposite side of the integrated circuit device800from the conductive contacts836.

In other embodiments in which the integrated circuit device800is a double-sided die, the integrated circuit device800may include one or more through silicon vias (TSVs) through the die substrate802; these TSVs may make contact with the device layer(s)804, and may provide conductive pathways between the device layer(s)804and additional conductive contacts (not shown) on the opposite side of the integrated circuit device800from the conductive contacts836. In some embodiments, TSVs extending through the substrate can be used for routing power and ground signals from conductive contacts on the opposite side of the integrated circuit device800from the conductive contacts836to the transistors840and any other components integrated into the die800, and the metallization stack819can be used to route I/O signals from the conductive contacts836to transistors840and any other components integrated into the die800.

Multiple integrated circuit devices800may be stacked with one or more TSVs in the individual stacked devices providing connection between one of the devices to any of the other devices in the stack. For example, one or more high-bandwidth memory (HBM) integrated circuit dies can be stacked on top of a base integrated circuit die and TSVs in the HBM dies can provide connection between the individual HBM and the base integrated circuit die. Conductive contacts can provide additional connections between adjacent integrated circuit dies in the stack. In some embodiments, the conductive contacts can be fine-pitch solder bumps (microbumps).

FIG.9is a cross-sectional side view of an integrated circuit device assembly900that may include any of the embodiments disclosed herein. The integrated circuit device assembly900includes a number of components disposed on a circuit board902(which may be a motherboard, system board, mainboard, etc.). The integrated circuit device assembly900includes components disposed on a first face940of the circuit board902and an opposing second face942of the circuit board902; generally, components may be disposed on one or both faces940and942.

In some embodiments, the circuit board902may be a printed circuit board (PCB) including multiple metal (or interconnect) layers separated from one another by layers of dielectric material and interconnected by electrically conductive vias. The individual metal layers comprise conductive traces. Any one or more of the metal layers may be formed in a desired circuit pattern to route electrical signals (optionally in conjunction with other metal layers) between the components coupled to the circuit board902. In other embodiments, the circuit board902may be a non-PCB substrate. The integrated circuit device assembly900illustrated inFIG.9includes a package-on-interposer structure936coupled to the first face940of the circuit board902by coupling components916. The coupling components916may electrically and mechanically couple the package-on-interposer structure936to the circuit board902, and may include solder balls (as shown inFIG.9), pins (e.g., as part of a pin grid array (PGA), contacts (e.g., as part of a land grid array (LGA)), male and female portions of a socket, an adhesive, an underfill material, and/or any other suitable electrical and/or mechanical coupling structure.

The package-on-interposer structure936may include an integrated circuit component920coupled to an interposer904by coupling components918. The coupling components918may take any suitable form for the application, such as the forms discussed above with reference to the coupling components916. Although a single integrated circuit component920is shown inFIG.9, multiple integrated circuit components may be coupled to the interposer904; indeed, additional interposers may be coupled to the interposer904. The interposer904may provide an intervening substrate used to bridge the circuit board902and the integrated circuit component920.

The integrated circuit component920may be a packaged or unpacked integrated circuit product that includes one or more integrated circuit dies (e.g., the die702ofFIG.7, the integrated circuit device800ofFIG.8) and/or one or more other suitable components. A packaged integrated circuit component comprises one or more integrated circuit dies mounted on a package substrate with the integrated circuit dies and package substrate encapsulated in a casing material, such as a metal, plastic, glass, or ceramic. In one example of an unpackaged integrated circuit component920, a single monolithic integrated circuit die comprises solder bumps attached to contacts on the die. The solder bumps allow the die to be directly attached to the interposer904. The integrated circuit component920can comprise one or more computing system components, such as one or more processor units (e.g., system-on-a-chip (SoC), processor core, graphics processor unit (GPU), accelerator, chipset processor), I/O controller, memory, or network interface controller. In some embodiments, the integrated circuit component920can comprise one or more additional active or passive devices such as capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, electrostatic discharge (ESD) devices, and memory devices.

In embodiments where the integrated circuit component920comprises multiple integrated circuit dies, they dies can be of the same type (a homogeneous multi-die integrated circuit component) or of two or more different types (a heterogeneous multi-die integrated circuit component). A multi-die integrated circuit component can be referred to as a multi-chip package (MCP) or multi-chip module (MCM).

In addition to comprising one or more processor units, the integrated circuit component920can comprise additional components, such as embedded DRAM, stacked high bandwidth memory (HBM), shared cache memories, input/output (I/O) controllers, or memory controllers. Any of these additional components can be located on the same integrated circuit die as a processor unit, or on one or more integrated circuit dies separate from the integrated circuit dies comprising the processor units. These separate integrated circuit dies can be referred to as “chiplets”. In embodiments where an integrated circuit component comprises multiple integrated circuit dies, interconnections between dies can be provided by the package substrate, one or more silicon interposers, one or more silicon bridges embedded in the package substrate (such as Intel® embedded multi-die interconnect bridges (EMIBs)), or combinations thereof.

Generally, the interposer904may spread connections to a wider pitch or reroute a connection to a different connection. For example, the interposer904may couple the integrated circuit component920to a set of ball grid array (BGA) conductive contacts of the coupling components916for coupling to the circuit board902. In the embodiment illustrated inFIG.9, the integrated circuit component920and the circuit board902are attached to opposing sides of the interposer904; in other embodiments, the integrated circuit component920and the circuit board902may be attached to a same side of the interposer904. In some embodiments, three or more components may be interconnected by way of the interposer904.

In some embodiments, the interposer904may be formed as a PCB, including multiple metal layers separated from one another by layers of dielectric material and interconnected by electrically conductive vias. In some embodiments, the interposer904may be formed of an epoxy resin, a fiberglass-reinforced epoxy resin, an epoxy resin with inorganic fillers, a ceramic material, or a polymer material such as polyimide. In some embodiments, the interposer904may be formed of alternate rigid or flexible materials that may include the same materials described above for use in a semiconductor substrate, such as silicon, germanium, and other group III-V and group IV materials. The interposer904may include metal interconnects908and vias910, including but not limited to through hole vias910-1(that extend from a first face950of the interposer904to a second face954of the interposer904), blind vias910-2(that extend from the first or second faces950or954of the interposer904to an internal metal layer), and buried vias910-3(that connect internal metal layers).

In some embodiments, the interposer904can comprise a silicon interposer. Through silicon vias (TSV) extending through the silicon interposer can connect connections on a first face of a silicon interposer to an opposing second face of the silicon interposer. In some embodiments, an interposer904comprising a silicon interposer can further comprise one or more routing layers to route connections on a first face of the interposer904to an opposing second face of the interposer904.

The interposer904may further include embedded devices914, including both passive and active devices. Such devices may include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, electrostatic discharge (ESD) devices, and memory devices. More complex devices such as radio frequency devices, power amplifiers, power management devices, antennas, arrays, sensors, and microelectromechanical systems (MEMS) devices may also be formed on the interposer904. The package-on-interposer structure936may take the form of any of the package-on-interposer structures known in the art. In embodiments where the interposer is a non-printed circuit board

The integrated circuit device assembly900may include an integrated circuit component924coupled to the first face940of the circuit board902by coupling components922. The coupling components922may take the form of any of the embodiments discussed above with reference to the coupling components916, and the integrated circuit component924may take the form of any of the embodiments discussed above with reference to the integrated circuit component920.

The integrated circuit device assembly900illustrated inFIG.9includes a package-on-package structure934coupled to the second face942of the circuit board902by coupling components928. The package-on-package structure934may include an integrated circuit component926and an integrated circuit component932coupled together by coupling components930such that the integrated circuit component926is disposed between the circuit board902and the integrated circuit component932. The coupling components928and930may take the form of any of the embodiments of the coupling components916discussed above, and the integrated circuit components926and932may take the form of any of the embodiments of the integrated circuit component920discussed above. The package-on-package structure934may be configured in accordance with any of the package-on-package structures known in the art.

FIG.10is a block diagram of an example electrical device1000that may include one or more of the embodiments disclosed herein. For example, any suitable ones of the components of the electrical device1000may include one or more of the integrated circuit device assemblies900, integrated circuit components920, integrated circuit devices800, or integrated circuit dies702disclosed herein. A number of components are illustrated inFIG.10as included in the electrical device1000, but any one or more of these components may be omitted or duplicated, as suitable for the application. In some embodiments, some or all of the components included in the electrical device1000may be attached to one or more motherboards mainboards, or system boards. In some embodiments, one or more of these components are fabricated onto a single system-on-a-chip (SoC) die.

Additionally, in various embodiments, the electrical device1000may not include one or more of the components illustrated inFIG.10, but the electrical device1000may include interface circuitry for coupling to the one or more components. For example, the electrical device1000may not include a display device1006, but may include display device interface circuitry (e.g., a connector and driver circuitry) to which a display device1006may be coupled. In another set of examples, the electrical device1000may not include an audio input device1024or an audio output device1008, but may include audio input or output device interface circuitry (e.g., connectors and supporting circuitry) to which an audio input device1024or audio output device1008may be coupled.

The electrical device1000may include a memory1004, which may itself include one or more memory devices such as volatile memory (e.g., dynamic random access memory (DRAM), static random-access memory (SRAM)), non-volatile memory (e.g., read-only memory (ROM), flash memory, chalcogenide-based phase-change non-voltage memories), solid state memory, and/or a hard drive. In some embodiments, the memory1004may include memory that is located on the same integrated circuit die as the processor unit1002. This memory may be used as cache memory (e.g., Level 1 (L1), Level 2 (L2), Level 3 (L3), Level 4 (L4), Last Level Cache (LLC)) and may include embedded dynamic random access memory (eDRAM) or spin transfer torque magnetic random access memory (STT-MRAM).

In some embodiments, the electrical device1000can comprise one or more processor units1002that are heterogeneous or asymmetric to another processor unit1002in the electrical device1000. There can be a variety of differences between the processing units1002in a system in terms of a spectrum of metrics of merit including architectural, microarchitectural, thermal, power consumption characteristics, and the like. These differences can effectively manifest themselves as asymmetry and heterogeneity among the processor units1002in the electrical device1000.

In some embodiments, the electrical device1000may include a communication component1012(e.g., one or more communication components). For example, the communication component1012can manage wireless communications for the transfer of data to and from the electrical device1000. The term “wireless” and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a nonsolid medium. The term “wireless” does not imply that the associated devices do not contain any wires, although in some embodiments they might not.

In some embodiments, the communication component1012may manage wired communications, such as electrical, optical, or any other suitable communication protocols (e.g., IEEE 802.3 Ethernet standards). As noted above, the communication component1012may include multiple communication components. For instance, a first communication component1012may be dedicated to shorter-range wireless communications such as Wi-Fi or Bluetooth, and a second communication component1012may be dedicated to longer-range wireless communications such as global positioning system (GPS), EDGE, GPRS, CDMA, WiMAX, LTE, EV-DO, or others. In some embodiments, a first communication component1012may be dedicated to wireless communications, and a second communication component1012may be dedicated to wired communications.

The electrical device1000may include battery/power circuitry1014. The battery/power circuitry1014may include one or more energy storage devices (e.g., batteries or capacitors) and/or circuitry for coupling components of the electrical device1000to an energy source separate from the electrical device1000(e.g., AC line power).

The electrical device1000may include a display device1006(or corresponding interface circuitry, as discussed above). The display device1006may include one or more embedded or wired or wirelessly connected external visual indicators, such as a heads-up display, a computer monitor, a projector, a touchscreen display, a liquid crystal display (LCD), a light-emitting diode display, or a flat panel display.

The electrical device1000may include an audio output device1008(or corresponding interface circuitry, as discussed above). The audio output device1008may include any embedded or wired or wirelessly connected external device that generates an audible indicator, such speakers, headsets, or earbuds.

The electrical device1000may include an audio input device1024(or corresponding interface circuitry, as discussed above). The audio input device1024may include any embedded or wired or wirelessly connected device that generates a signal representative of a sound, such as microphones, microphone arrays, or digital instruments (e.g., instruments having a musical instrument digital interface (MIDI) output). The electrical device1000may include a Global Navigation Satellite System (GNSS) device1018(or corresponding interface circuitry, as discussed above), such as a Global Positioning System (GPS) device. The GNSS device1018may be in communication with a satellite-based system and may determine a geolocation of the electrical device1000based on information received from one or more GNSS satellites, as known in the art.

The electrical device1000may include an other output device1010(or corresponding interface circuitry, as discussed above). Examples of the other output device1010may include an audio codec, a video codec, a printer, a wired or wireless transmitter for providing information to other devices, or an additional storage device.

The electrical device1000may have any desired form factor, such as a hand-held or mobile electrical device (e.g., a cell phone, a smart phone, a mobile internet device, a music player, a tablet computer, a laptop computer, a 2-in-1 convertible computer, a portable all-in-one computer, a netbook computer, an ultrabook computer, a personal digital assistant (PDA), an ultra mobile personal computer, a portable gaming console, etc.), a desktop electrical device, a server, a rack-level computing solution (e.g., blade, tray or sled computing systems), a workstation or other networked computing component, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a stationary gaming console, smart television, a vehicle control unit, a digital camera, a digital video recorder, a wearable electrical device or an embedded computing system (e.g., computing systems that are part of a vehicle, smart home appliance, consumer electronics product or equipment, manufacturing equipment). In some embodiments, the electrical device1000may be any other electronic device that processes data. In some embodiments, the electrical device1000may comprise multiple discrete physical components. Given the range of devices that the electrical device1000can be manifested as in various embodiments, in some embodiments, the electrical device1000can be referred to as a computing device or a computing system.

Illustrative examples of the technologies described throughout this disclosure are provided below. Embodiments of these technologies may include any one or more, and any combination of, the examples described below. In some embodiments, at least one of the systems or components set forth in one or more of the preceding figures may be configured to perform one or more operations, techniques, processes, and/or methods as set forth in the following examples.

Example 1 is a transistor device comprising: a substrate; a first source or drain material on the substrate; a semiconductor material on the first source or drain material; a second source or drain material on the semiconductor material; a first dielectric material on the substrate and adjacent the first source or drain material; a ferroelectric (FE) material on the first dielectric material and adjacent the semiconductor material; a gate material on the on the first dielectric material and adjacent the FE material; and a second dielectric material on the FE material and gate material, the second dielectric material adjacent the second source or drain material.

Example 2 includes the subject matter of Example 1, wherein a lattice parameter of the semiconductor material is higher than a lattice parameter of the FE material.

Example 3 includes the subject matter of Example 1 or 2, wherein the FE material is a perovskite material.

Example 4 includes the subject matter of any one of Examples 1-3, wherein the FE material includes one or more of Barium, Titanium, Zirconium, Calcium, Strontium, Lanthanum, Bismuth, Iron, Cobalt, Lithium, Niobium, Potassium, and Oxygen.

Example 5 includes the subject matter of any one of Examples 1-4, wherein the semiconductor material includes one or more of Barium, Tin, Lanthanum, Neodymium, Strontium, Titanium, Indium, Gallium, Zinc, Nickel, and Oxygen.

Example 6 includes the subject matter of any one of Examples 1-5, wherein the substrate comprises one or more of Strontium, Titanium, Gadolinium, Scandium, Dysprosium, Lanthanum, Aluminum, Barium, Hafnium, Zirconium, Indium, Lutetium, Magnesium, and Oxygen.

Example 7 includes the subject matter of any one of Examples 1-6, wherein the first source or drain material and the second source or drain material each comprise one or more of Strontium, Ruthenium, Barium, Lanthanum, Tin, Manganese, Cobalt, Nickel, Yttrium, Copper, Vanadium, Molybdenum, Platinum, Iridium, Palladium, Tungsten, and Oxygen.

Example 8 includes the subject matter of any one of Examples 1-7, wherein the gate material comprises one or more of Strontium, Ruthenium, Barium, Lanthanum, Tin, Manganese, Cobalt, Nickel, Yttrium, Copper, Vanadium, Molybdenum, Platinum, Iridium, Palladium, Tungsten, and Oxygen.

Example 9 includes the subject matter of any one of Examples 1-8, wherein the FE material is a first FE material and the gate material is a first gate material, and the device further comprises: a third dielectric material on the substrate and adjacent the first source or drain material; a second FE material on the third dielectric material and adjacent the semiconductor material; a second gate material on the on the third dielectric material and adjacent the second FE material; a fourth dielectric material on the second FE material and the second gate material, the fourth dielectric material adjacent the second source or drain material.

Example 10 includes the subject matter of any one of Examples 1-9, wherein the semiconductor material is a first semiconductor material, and the device further comprises: a third dielectric material on the second source or drain material; a third second source or drain material on the dielectric; a second semiconductor material on the third source or drain material; a fourth source or drain material on the second semiconductor material; a second FE material on the second dielectric material and adjacent the second semiconductor material, wherein the gate material is further adjacent the second FE material; and a fourth dielectric material on the second FE material and the gate material.

Example 11 is a transistor device comprising: a substrate; a first source or drain material on the substrate; a semiconductor material on the first source or drain material; a second source or drain material on the semiconductor material; a dielectric layer on the substrate and adjacent the first source or drain material; a ferroelectric (FE) material on the dielectric layer and adjacent the semiconductor material, wherein the FE material has a lattice parameter that is less than a lattice parameter of the semiconductor material; and a gate material on or adjacent to the FE material.

Example 12 includes the subject matter of Example 11, wherein the FE material is a perovskite material.

Example 13 includes the subject matter of Example 11 or 12, wherein the FE material includes one or more of Barium, Titanium, Zirconium, Calcium, Strontium, Lanthanum, Bismuth, Iron, Cobalt, Lithium, Niobium, Potassium, and Oxygen.

Example 14 includes the subject matter of any one of Examples 11-13, wherein the semiconductor material includes one or more of Barium, Tin, Lanthanum, Neodymium, Strontium, Titanium, Indium, Gallium, Zinc, Nickel, and Oxygen.

Example 15 includes the subject matter of any one of Examples 11-14, wherein the substrate comprises one or more of Strontium, Titanium, Gadolinium, Scandium, Dysprosium, Lanthanum, Aluminum, Barium, Hafnium, Zirconium, Indium, Lutetium, Magnesium, and Oxygen.

Example 16 includes the subject matter of any one of Examples 11-15, wherein the first source or drain material and the second source or drain material each comprise one or more of Strontium, Ruthenium, Barium, Lanthanum, Tin, Manganese, Cobalt, Nickel, Yttrium, Copper, Vanadium, Molybdenum, Platinum, Iridium, Palladium, Tungsten, and Oxygen.

Example 17 includes the subject matter of any one of Examples 11-16, wherein the gate material comprises one or more of Strontium, Ruthenium, Barium, Lanthanum, Tin, Manganese, Cobalt, Nickel, Yttrium, Copper, Vanadium, Molybdenum, Platinum, Iridium, Palladium, Tungsten, and Oxygen.

Example 18 includes the subject matter of any one of Examples 11-17, wherein the FE material is a first FE material, the gate material is a first gate material, and the dielectric layer is a first dielectric layer, and the device further comprises: a second dielectric layer on the substrate and adjacent the first source or drain material; a second FE material on the second dielectric material and adjacent the semiconductor material; and a second gate material on the on the third dielectric material and adjacent the second FE material.

Example 19 includes the subject matter of any one of Examples 11-18, wherein the semiconductor material is a first semiconductor material, and the device further comprises: a second dielectric material on the second source or drain material; a third second source or drain material on the dielectric; a second semiconductor material on the third source or drain material; a fourth source or drain material on the second semiconductor material; a second FE material adjacent the second semiconductor material, wherein the gate material is further adjacent the second FE material; and a third dielectric material between the first FE material and the second FE material.

Example 20 is a method of manufacturing a transistor device comprising: forming a first source or drain material on a substrate; forming a semiconductor material on the first source or drain material; forming a second source or drain material on the semiconductor material; forming a dielectric layer on the substrate adjacent the first source or drain material; forming a ferroelectric (FE) material on the dielectric layer adjacent the semiconductor material, wherein the FE material has a lattice parameter that is less than a lattice parameter of the semiconductor material; and forming a gate material on or adjacent to the FE material.

Example 21 includes the subject matter of Example 20, wherein the FE material is a perovskite material.

Example 22 includes the subject matter of Example 20 or 21, wherein the FE material includes one or more of Barium, Titanium, Zirconium, Calcium, Strontium, Lanthanum, Bismuth, Iron, Cobalt, Lithium, Niobium, Potassium, and Oxygen.

Example 23 includes the subject matter of any one of Examples 20-22, wherein the semiconductor material includes one or more of Barium, Tin, Lanthanum, Neodymium, Strontium, Titanium, Indium, Gallium, Zinc, Nickel, and Oxygen.

Example 24 includes the subject matter of any one of Examples 20-23, wherein the FE material is a first FE material, the gate material is a first gate material, and the dielectric layer is a first dielectric layer, and the method further comprises: forming a second dielectric layer on the substrate and adjacent the first source or drain material; forming a second FE material on the second dielectric material and adjacent the semiconductor material; and forming a second gate material on the on the third dielectric material and adjacent the second FE material.

Example 25 includes the subject matter of any one of Examples 20-24, wherein the semiconductor material is a first semiconductor material, and the method further comprises: a forming a second dielectric material on the second source or drain material; forming a third second source or drain material on the second dielectric material; forming a second semiconductor material on the third source or drain material; forming a fourth source or drain material on the second semiconductor material; forming a second FE material adjacent the second semiconductor material, wherein the gate material is further adjacent the second FE material; and forming a third dielectric material between the first FE material and the second FE material.

In the above description, various aspects of the illustrative implementations have been described using terms commonly employed by those skilled in the art to convey the substance of their work to others skilled in the art. However, it will be apparent to those skilled in the art that the present disclosure may be practiced with only some of the described aspects. For purposes of explanation, specific numbers, materials, and configurations have been set forth to provide a thorough understanding of the illustrative implementations. However, it will be apparent to one skilled in the art that the present disclosure may be practiced without all of the specific details. In other instances, well-known features have been omitted or simplified in order not to obscure the illustrative implementations.

In various embodiments, the phrase “a first feature formed, deposited, or otherwise disposed on a second feature” may mean that the first feature is formed, deposited, or disposed over the second feature, and at least a part of the first feature may be in direct contact (e.g., direct physical and/or electrical contact) or indirect contact (e.g., having one or more other features between the first feature and the second feature) with at least a part of the second feature.

In various embodiments, the phrase “located on” in the context of a first layer or component located on a second layer or component refers to the first layer or component being directly physically attached to the second part or component (no layers or components between the first and second layers or components) or physically attached to the second layer or component with one or more intervening layers or components.

In various embodiments, the term “adjacent” refers to layers or components that are in physical contact with each other. That is, there is no layer or component between the stated adjacent layers or components. For example, a layer X that is adjacent to a layer Y refers to a layer that is in physical contact with layer Y.