Semiconductor device and method for fabricating the same

A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate; forming a fin-shaped structure on the substrate; forming a shallow trench isolation (STI) around the fin-shaped structure; forming a gate structure on the fin-shaped structure and the STI and the fin-shaped structure directly under the gate structure includes a first epitaxial layer; forming a source region having first conductive type adjacent to one side of the gate structure; and forming a first drain region having a second conductive type adjacent to another side of the gate structure.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The invention relates to a method for fabricating semiconductor device, and more particularly, to a method of fabricating semiconductor device having source region and drain region with different conductive type.

2. Description of the Prior Art

With the trend in the industry being towards scaling down the size of the metal oxide semiconductor transistors (MOS), three-dimensional or non-planar transistor technology, such as fin field effect transistor technology (FinFET) has been developed to replace planar MOS transistors. Since the three-dimensional structure of a FinFET increases the overlapping area between the gate and the fin-shaped structure of the silicon substrate, the channel region can therefore be more effectively controlled. This way, the drain-induced barrier lowering (DIBL) effect and the short channel effect are reduced. The channel region is also longer for an equivalent gate length, thus the current between the source and the drain is increased. In addition, the threshold voltage of the fin FET can be controlled by adjusting the work function of the gate.

However, the overall architecture of fin-shaped structure still poses numerous problems in current FinFET fabrication, which not only affects the carrier mobility in the channel region but also influences overall performance of the device. Hence, how to improve the current FinFET process has become an important task in this field.

SUMMARY OF THE INVENTION

According to a preferred embodiment of the present invention, a method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate; forming a fin-shaped structure on the substrate; forming a shallow trench isolation (STI) around the fin-shaped structure; forming a gate structure on the fin-shaped structure and the STI, in which the fin-shaped structure directly under the gate structure includes a first epitaxial layer; forming a source region having first conductive type adjacent to one side of the gate structure; and forming a first drain region having a second conductive type adjacent to another side of the gate structure.

According to another aspect of the present invention, a semiconductor device is disclosed. The semiconductor device includes: a substrate; a fin-shaped structure on the substrate; a shallow trench isolation (STI) around the fin-shaped structure; a gate structure on the fin-shaped structure and the STI, in which the fin-shaped structure directly under the gate structure includes a first epitaxial layer; a source region having first conductive type adjacent to one side of the gate structure; and a drain region having second conductive type adjacent to another side of the gate structure.

DETAILED DESCRIPTION

Referring toFIGS. 1-2,FIGS. 1-2illustrate a method for fabricating a tunneling field effect transistor (TFET) according to an embodiment of the present invention. Preferably,FIG. 1illustrates a cross-section view for fabricating a TFET andFIG. 2illustrates a 3-dimensional view for fabricating the TFET followingFIG. 1. As shown inFIGS. 1-2, a substrate12, such as a silicon substrate or silicon-on-insulator (SOI) substrate is first provided, fin-shaped structures14are formed on the substrate12, and a shallow trench isolation (STI)16composed of material such as silicon oxide is formed around the fin-shaped structures.

In this embodiment, each of the fin-shaped structures14includes three portions18,20,22, in which the bottom portion18and the middle portion20are embedded under a top surface of the STI16while the top portion22is protruding from the top surface of the STI16. Preferably, the bottom portion18and the substrate12are made of same material such as silicon, the middle portion20is made of silicon containing n-type or p-type dopants injected through an anti-punch through (APT) process, and the top portion22is made of epitaxial material including but not limited to for example, germanium (Ge) and/or silicon germanium (SiGe). It should be noted that the top portion22protruding from the top surface of the STI16, in particular the part of top portion22covered by a gate structure in the later process will be serving as a channel region or channel region of the device.

According to an embodiment of the present invention, the fin-shaped structures14are obtained by a sidewall image transfer (SIT) process. For instance, a layout pattern is first input into a computer system and is modified through suitable calculation. The modified layout is then defined in a mask and further transferred to a layer of sacrificial layer on a substrate through a photolithographic and an etching process. In this way, several sacrificial layers distributed with a same spacing and of a same width are formed on a substrate. Each of the sacrificial layers may be stripe-shaped. Subsequently, a deposition process and an etching process are carried out such that spacers are formed on the sidewalls of the patterned sacrificial layers. In a next step, sacrificial layers can be removed completely by performing an etching process. Through the etching process, the pattern defined by the spacers can be transferred into the substrate underneath, and through additional fin cut processes, desirable pattern structures, such as stripe patterned fin-shaped structures could be obtained.

Alternatively, the fin-shaped structures14could also be obtained by first forming a patterned mask (not shown) on the substrate12, and through an etching process, the pattern of the patterned mask is transferred to the substrate12to form the fin-shaped structure14. Moreover, the formation of the fin-shaped structures14could also be accomplished by first forming a patterned hard mask (not shown) on the substrate12, and a semiconductor layer composed of silicon germanium is grown from the substrate12through exposed patterned hard mask via selective epitaxial growth process to form the corresponding fin-shaped structures14. These approaches for forming fin-shaped structures are all within the scope of the present invention.

Next, as shown inFIG. 2, at least agate structure24is formed on the substrate12and STI16and standing astride at least one of the fin-shaped structures14. It should be noted that only a single gate structure24disposed across a single fin-shaped structure14is shown inFIG. 2for emphasizing the formation of source region and drain region with respect to the gate structure24in the later process. The fabrication of the gate structure24could be accomplished by a gate first process, a high-k first approach from gate last process, or a high-k last approach from gate last process. Since this embodiment pertains to a high-k last approach, dummy gate or gate structure24composed of an interfacial layer (not shown) and a patterned polysilicon material layer26could be first formed on the fin-shaped structures14and the STI16, and a spacer (not shown) is formed on the sidewall of the gate structure24.

Next, a first ion implantation process is conducted to implant dopants of a first conductive type into the top portion22of fin-shaped structure14on one side of the gate structure24for forming a source region28. After that, a second ion implantation is conducted to implant dopants of a second conductive type into the top portion22of fin-shaped structure14on another side of the gate structure24for forming a drain region30. In this embodiment, the first conductive type is p-type and the source region28is implanted with p-type dopants while the second conductive type is n-type and the drain region30is implanted with n-type dopants. Nevertheless, it would also be desirable to reverse the order and/or conductive type of the first ion implantation process and second ion implantation process by first implanting n-type dopants for forming a source region and then implanting p-type dopants for forming a drain region, which is also within the scope of the present invention.

It should also be noted that after the source region28and the drain region30are formed, the source region28, a channel region32or top portion22of fin-shaped structure14directly under the gate structure24, and the drain region30are in a way made of three different materials. For instance, the source region28adjacent to one side of the gate structure24preferably includes Ge or SiGe with p-type dopants, the channel region32or top portion22of fin-shaped structure14directly under the gate structure24includes Ge or SiGe having no dopants, and the drain region30includes Ge or SiGe with n-type dopants.

Moreover, according to an embodiment of the present invention, the ratio of germanium to silicon (Ge/Si) could also be adjusted to form a gradient channel from the source region28, through the channel region32directly under the gate structure24, and to the drain region30. For instance, the Ge/Si ratio in this embodiment is preferably adjusted so that the Ge/Si ratio gradually decreases from the source region28to the drain region30. By doing so, the band gap would be increased from the source region28to the drain region30which would further in turn suppress ambipolar issue so that better driving current could be obtained.

Referring toFIG. 3,FIG. 3illustrates a structural view of a TFET according to an embodiment of the present invention. As shown inFIG. 3, after forming the source region28and drain region30having different conductive type as disclosed inFIG. 2, an etching process could be conducted to remove the drain region30made of Ge or SiGe on one side of the gate structure24and expose the middle portion20made of doped silicon underneath, and then grow another epitaxial layer34with in-situ n-type dopants through epitaxial growth process on the exposed middle portion20.

Preferably, the newly grown epitaxial layer34(or the new drain region) and the channel region32directly under the gate structure24are made of different material, and the new drain region34and the source region28are also made of different material. For instance, the new drain region34in this embodiment is preferably made of silicon or silicon carbide (SiC) with in-situ n-type dopants while the channel region32is made of Ge or SiGe and the source region28is made of Ge or SiGe with p-type dopants.

After forming the source region28and either the drain region30formed inFIG. 2or the drain region34formed inFIG. 3, a selective contact etch stop layer (CESL) (not shown) could be formed on source region28, the drain region30or drain region34, and the gate structure24, and an interlayer dielectric (ILD) layer made of material such as tetraethyl orthosilicate (TEOS) is formed on the CESL. Next, a replacement metal gate (RMG) process could be conducted to planarize part of the ILD layer and then transforming the gate structure24into metal gate. The RMG process could be accomplished by first performing a selective dry etching or wet etching process, such as using etchants including ammonium hydroxide (NH4OH) or tetramethylammonium hydroxide (TMAH) to remove the polysilicon material layer26for forming a recess (not shown) in the ILD layer. Next, a U-shaped high-k dielectric layer and a conductive layer including at least a U-shaped work function metal layer and a low resistance metal layer are formed in the recess, and a planarizing process is conducted thereafter so that the top surfaces of the U-shaped high-k dielectric layer, U-shaped work function metal layer and low resistance metal layer are even with the surface of the ILD layer.

Preferably, the work function metal layer is formed for tuning the work function of the later formed metal gates to be appropriate in an NMOS or a PMOS. For an NMOS transistor, the work function metal layer having a work function ranging between 3.9 eV and 4.3 eV may include titanium aluminide (TiAl), zirconium aluminide (ZrAl), tungsten aluminide (WA1), tantalum aluminide (TaAl), hafnium aluminide (HfAl), or titanium aluminum carbide (TiAlC), but it is not limited thereto. For a PMOS transistor, the work function metal layer having a work function ranging between 4.8 eV and 5.2 eV may include titanium nitride (TiN), tantalum nitride (TaN), tantalum carbide (TaC), but it is not limited thereto. An optional barrier layer (not shown) could be formed between the work function metal layer and the low resistance metal layer, in which the material of the barrier layer may include titanium (Ti), titanium nitride (TiN), tantalum (Ta) or tantalum nitride (TaN). Furthermore, the material of the low-resistance metal layer may include copper (Cu), aluminum (Al), titanium aluminum (TiAl), cobalt tungsten phosphide (CoWP) or any combination thereof. Since the process of using RMG process to transform dummy gate into metal gate is well known to those skilled in the art, the details of which are not explained herein for the sake of brevity.

Referring toFIGS. 4-5,FIGS. 4-5illustrate a method for fabricating a tunneling field effect transistor (TFET) according to an embodiment of the present invention. Preferably,FIG. 4illustrates a cross-section view for fabricating a TFET andFIG. 5illustrates a 3-dimensional view for fabricating the TFET followingFIG. 4. As shown inFIGS. 4-5, a substrate42, such as a silicon substrate or silicon-on-insulator (SOI) substrate is first provided, fin-shaped structures44are formed on the substrate42, and a shallow trench isolation (STI)46composed of material such as silicon oxide is formed around the fin-shaped structures44.

In this embodiment, each of the fin-shaped structures44includes three portions48,50,52, in which the bottom portion48and the middle portion50are embedded under a top surface of the STI46while the top portion52is protruding from the top surface of the STI46. Preferably, the bottom portion48and the substrate12are made of same material such as silicon, the middle portion50is made of dielectric material such as silicon oxide, and the top portion52is made of epitaxial material including but not limited to for example, germanium (Ge) and/or silicon germanium (SiGe). It should be noted that the top portion52protruding from the top surface of the STI46, in particular the part of top portion52covered by a gate structure in the later process will be serving as a channel region or channel layer of the device.

Next, as shown inFIG. 5, at least agate structure54is formed on the substrate12and STI46and standing astride at least one of the fin-shaped structures44. It should be noted that only a single gate structure54disposed across a single fin-shaped structure44is shown inFIG. 5for emphasizing the formation of source region and drain region with respect to the gate structure54in the later process. The fabrication of the gate structure54could be accomplished by a gate first process, a high-k first approach from gate last process, or a high-k last approach from gate last process. Since this embodiment pertains to a high-k last approach, dummy gate or gate structure54composed of an interfacial layer (not shown) and a patterned polysilicon material layer56could be first formed on the fin-shaped structure44and the STI46, and a spacer (not shown) is formed on the sidewall of the gate structure54.

Next, a first ion implantation process is conducted to implant dopants of a first conductive type into the top portion52of fin-shaped structure44on one side of the gate structure54for forming a source region58. After that, a second ion implantation is conducted to implant dopants of a second conductive type into the top portion52of fin-shaped structure44on another side of the gate structure54for forming a drain region60. In this embodiment, the first conductive type is p-type and the source region58is implanted with p-type dopants while the second conductive type is n-type and the drain region60is implanted with n-type dopants. Nevertheless, it would also be desirable to reverse the order and/or conductive type of the first ion implantation process and second ion implantation process, such as by first implanting n-type dopants for forming a source region and then implanting p-type dopants for forming a drain region, which is also within the scope of the present invention.

Similar to the aforementioned embodiment, the source region58, a channel region62or top portion52of fin-shaped structure44directly under the gate structure54, and the drain region60are in a way made of three different materials after the source region58and the drain region60are formed. For instance, the source region58adjacent to one side of the gate structure54preferably includes Ge or SiGe with p-type dopants, the channel region62or top portion52of fin-shaped structure44directly under the gate structure54includes Ge or SiGe having no dopants, and the drain region60includes Ge or SiGe with n-type dopants.

Moreover, according to an embodiment of the present invention, the ratio of germanium to silicon (Ge/Si) could be adjusted to form a gradient channel from the source region58, through the channel region62directly under the gate structure54, and to the drain region60. For instance, the Ge/Si ratio in this embodiment could be adjusted so that the Ge/Si ratio gradually decreases from the source region58to the drain region60. By doing so, the band gap would be increased from the source region58to the drain region60which would further in turn suppress ambipolar issue so that better driving current could be obtained.

Referring toFIG. 6,FIG. 6illustrates a structural view of a TFET according to an embodiment of the present invention. As shown inFIG. 6, after forming the source region58and drain region60having different conductive type as disclosed inFIG. 5, an etching process could be conducted to remove the drain region60made of Ge or SiGe on one side of the gate structure54and expose the middle portion50made of silicon oxide underneath, and then grow another epitaxial layer64with in-situ n-type dopants through epitaxial growth process on the exposed middle portion50.

Preferably, the newly grown epitaxial layer64(or the new drain region) and the channel region62directly under the gate structure54are made of different material, and the new drain region64and the source region58are also made of different material. For instance, the new drain region64in this embodiment is preferably made of silicon or silicon carbide (SiC) with in-situ n-type dopants while the channel region62is made of Ge or SiGe and the source region58is made of Ge or SiGe with p-type dopants.

After forming the source region58and the drain region60or drain region64, elements such as a CESL (not shown) and a ILD layer could be formed on source region58, the drain region64, and the gate structure54, and a RMG process similar to the aforementioned embodiment could be conducted to transform the gate structure54into metal gate.

Referring toFIGS. 7-8,FIGS. 7-8illustrate a method for fabricating a tunneling field effect transistor (TFET) according to an embodiment of the present invention. Preferably,FIG. 7illustrates a cross-section view for fabricating a TFET andFIG. 8illustrates a 3-dimensional view for fabricating the TFET followingFIG. 7. As shown inFIGS. 7-8, a substrate72, such as a silicon substrate or silicon-on-insulator (SOI) substrate is first provided, fin-shaped structures74are formed on the substrate72, and a shallow trench isolation (STI)76composed of material such as silicon oxide is formed around the fin-shaped structures74.

In this embodiment, each of the fin-shaped structures includes two portions78,80, in which the bottom portion78is embedded under a top surface of the STI76while the top portion80is protruding from the top surface of the STI76. A cladded layer82is formed on the sidewalls of the fin-shaped structures74as well as on the top surface of the substrate72, and an optional hard mask84is formed between the cladded layer82and the STI76. Preferably, the top portion80, the bottom portion78, and the substrate72are made of same material such as silicon, the cladded layer82is made of epitaxial material including but not limited to for example, germanium (Ge) and/or silicon germanium (SiGe), and the hard mask84could be selected from the group consisting of silicon oxide, silicon nitride, silicon oxynitride, and silicon carbon nitride. It should be noted that the top portion80and cladded layer82protruding from the top surface of the STI76will be covered by a gate structure in the later process and will be serving as a channel region or channel layer of the device.

Next, as shown inFIG. 8, at least agate structure86is formed on the substrate72and STI76and standing astride at least one of the fin-shaped structures74. Similarly, only a single gate structure86disposed across a single fin-shaped structure74is shown inFIG. 8for emphasizing the formation of source region and drain region with respect to the gate structure86in the later process. The fabrication of the gate structure86could be accomplished by a gate first process, a high-k first approach from gate last process, or a high-k last approach from gate last process. Since this embodiment pertains to a high-k last approach, dummy gate or gate structure86composed of an interfacial layer (not shown) and a patterned polysilicon material layer88could be first formed on the fin-shaped structure74and the STI76, and a spacer (not shown) is formed on the sidewall of the gate structure86.

Next, a first ion implantation process is conducted to implant dopants of a first conductive type into the top portion80of fin-shaped structure74on one side of the gate structure86for forming a source region90. After that, a second ion implantation is conducted to implant dopants of a second conductive type into the top portion74on another side of the gate structure86for forming a drain region92. In this embodiment, the first conductive type is p-type and the source region90is implanted with p-type dopants while the second conductive type is n-type and the drain region92is implanted with n-type dopants. Nevertheless, it would also be desirable to reverse the order and/or conductive type of the first ion implantation process and second ion implantation process, such as by first implanting n-type dopants for forming a source region and then implanting p-type dopants for forming a drain region, which is also within the scope of the present invention.

Similar to the aforementioned embodiment, the source region90, a channel region94including the top portion80of fin-shaped structure74and part of the cladded layer82directly under the gate structure86, and the drain region92are in a way made of three different materials after the source region90and the drain region92are formed. For instance, the source region90adjacent to one side of the gate structure86preferably includes Ge or SiGe with p-type dopants, the channel region94directly under the gate structure86includes a combination of silicon from the top portion80of fin-shaped structure74and Ge or SiGe having no dopants from the cladded layer82, and the drain region92includes Ge or SiGe with n-type dopants.

Moreover, according to an embodiment of the present invention, the ratio of germanium to silicon (Ge/Si) could be adjusted to form a gradient channel from the source region90, through the channel region94directly under the gate structure86, and to the drain region92. For instance, the Ge/Si ratio in this embodiment could be adjusted so that the Ge/Si ratio gradually decreases from the source region90to the drain region92.

Referring toFIG. 9,FIG. 9illustrates a structural view of a TFET according to an embodiment of the present invention. As shown inFIG. 9, after forming the source region90and drain region92having different conductive type as disclosed inFIG. 8, an etching process could be conducted to remove the drain region92made of Ge or SiGe on one side of the gate structure86and expose the cladded layer82and bottom portion78of fin-shaped structure74underneath, and then grow another epitaxial layer96with in-situ n-type dopants through epitaxial growth process on the exposed cladded layer82and bottom portion78.

Preferably, the newly grown epitaxial layer96(or the new drain region) and the channel region94directly under the gate structure86are made of different material, and the new drain region96and the source region90are also made of different material. For instance, the new drain region96in this embodiment is preferably made of silicon or silicon carbide (SiC) with in-situ n-type dopants while the channel region94is made of a combination of silicon from the top portion80of fin-shaped structure74and Ge or SiGe having no dopants from the cladded layer82, and the source region90is made of Ge or SiGe with p-type dopants.

After forming the source region90and the drain region92or drain region96, elements such as a CESL (not shown) and a ILD layer could be formed on source region90, the drain region96, and the gate structure86, and a RMG process similar to the aforementioned embodiment could be conducted to transform the gate structure86into metal gate.