Extended package air core inductor

An electronic device comprises an air core inductor including an electronic semiconductor package including a first portion of the air core inductor internal to the electronic semiconductor package; and an electrically conductive layer arranged on a first external surface of the electronic semiconductor package and electrically connected as a second portion of the air core inductor.

PRIORITY APPLICATION

This application claims the benefit of priority to Malaysian Application Serial Number PI 2018702566, filed Jul. 23, 2018, which is incorporated herein by reference in its entirety.

TECHNICAL FIELD

Embodiments pertain to packaging of integrated circuits (ICs). Some embodiments relate to including inductors in IC packages.

BACKGROUND

Electronic systems often include integrated circuits (ICs) that are connected to a subassembly such as a substrate or motherboard. The ICs can be packaged and inserted into an IC package that is mounted on the subassembly. As electronic system designs become more complex, it is a challenge to meet the desired size constraints of the system. One aspect that can influence the overall size of a design is the spacing required for inductive circuit elements that traditionally are relatively large. As the size of the electronic circuit assemblies are reduced and electronic packages become more complex, the packaged electronic assemblies can become less robust and the cost of meeting the spacing requirements can increase. Thus, there are general needs for devices, systems and methods that address the spacing challenges for contacts of ICs yet provide a robust and cost effective design.

DETAILED DESCRIPTION

A fully-integrated voltage regulator (FIVR) is a voltage regulator (e.g., voltage converter) included in the same integrated circuit (IC) device with other components (e.g., processing circuitry, memory circuitry, and other circuitry) of the IC device. A FIVR circuit can be used to produce a voltage domain for the IC device by increasing or decreasing the voltage of the power source. IC devices of the same design may have multiple voltage domains; and an IC device may include multiple FIVR circuits to establish multiple voltage domains.

FIG. 1is a block diagram of an FIVR circuit100. A FIVR often includes a pulse-width modulation (PWM) block105that provides a control loop to regulate the value of an output voltage provided by the voltage regulator. The PWM block controls switch circuit107to deliver electrical energy onto an inductor109from the power source.

Inductive circuit elements can adversely impact the size requirements of an electronic assembly. One approach is to fabricate air core inductors (ACIs) during the manufacturing of the electronic package and incorporate the ACIs into the electronic circuit using metal routing layers of the electronic packaging. Although referred to as “air core,” ACIs can include an insulating dielectric material in the ACI core. These inductors are still referred to as ACIs because the insulating dielectric material has the same, or nearly the same, relative magnetic permeability as air (equal to 1.0).

FIG. 2is an illustration of a side view or cross section view of an IC device200. The IC device includes an electronic semiconductor package202coupled to a printed circuit board204(e.g., a motherboard) by solder bumps or solder balls206. The IC device includes two ACIs208. The ACIs can be connected to other components of the electronic semiconductor package202by vias210. The ACIs in the example ofFIG. 2include four turns. The number of turns that can be formed can be limited by the limit imposed by the fabrication process on the thickness of the substrate. The IC device also includes passive components212(e.g., capacitors and discrete inductors) on the land side of the IC package.

A challenge with using ACIs is that the FIVR efficiency is impacted by the size of the ACI coil, with larger coils desired for higher inductance L and lower resistance R. This can increase the number of substrate layers needed to form a large number of turns to increase L or to form parallel turn routing to reduce R. The increased number of layers can increase height and cost of the IC design. Also, for multi-FIVR designs, the ACI spacing requirement can limit the size of the ACIs, which can limit the increase in L and reduction in R available in the electronic assembly.

To increase the FIVR efficiency, one or more electrically conductive layers can be added external to the IC package and electrically connected to the ACI internal to the IC package. The one or more conductive layers may be electrically connected as one or more additional turns to increase inductance of the ACI, or connected to reduce resistance of the ACI.

FIG. 3is an illustration of a side view of another IC device300. The IC device includes an electronic semiconductor package302coupled to a printed circuit board304or PCB. The IC device300includes multiple ACIs including a first ACI314. A first portion316of the ACI314is internal to the electronic semiconductor package302, and a second portion of the ACI is external to the electronic semiconductor package302. The external portion320is an electrically conductive layer arranged on the external surface of the electronic semiconductor package. The external portion320is electrically connected to the internal portion as an additional turn of the ACI. The electronic semiconductor package302includes pads (e.g., input-output pads or I/O pads) to connect the internal ACI portion and the external turn. A solder resist process can be used to create the openings318in the electronic semiconductor package302for the pads. The external portion320and passive components such as capacitors and discrete packaged inductors can be mounted to the landside surface of the IC package.

In some aspects, the external portion of the ACI can include more than one turn. For example, the external portion320can include multiple conductive layers alternating with insulating layers. The conducting layers can be connected as multiple turns. The example ofFIG. 3also shows a recess in motherboard (RIMB). This area between the electronic semiconductor package302and the PCB defines a space often under-utilized in IC device assemblies. The external portion320and the passive components can be arranged in the RIMB. The number of turns that can be included in the external portion may depend on the land side space (e.g., RIMB) available.

In some aspects, the external portion320can be a metal preform, or preformed element. The metal can include one or more of copper, aluminum, tungsten, etc. The process of preforming the metal can result in physically detectable features, such as evidence of work hardening from the preforming for example. The preformed element can be produced from a sheet or ribbon of metal using a stamping process. The stamping process may also result in physically detectable features, such as burrs on edges of the preformed element for example. The external portion320can be arranged on the external surface of the electronic semiconductor package302using an adhesive. In certain embodiments that external portion can be bonded with solder to the internal portion.

FIG. 4is an illustration of a metal preform418attached to a four turn ACI. The external package surface is not shown in the Figure and would be between the internal ACI416and the metal preform418.

Returning toFIG. 3, the IC device300in the example includes a second ACI322. Like the first ACI314, a first portion324of the second ACI322is internal to the electronic semiconductor package302, and a second portion of the ACI is external to the electronic semiconductor package302. The external portion326is an electrically conductive layer arranged on the external surface of the electronic semiconductor package. The external portion326is an electrically, conductive layer electrically connected to reduce electrical resistance of at least one turn of the ACI. In the example shown inFIG. 3, an opening328in the IC package is formed (e.g., by a solder resist process) to expose a turn of the internal portion322of the ACI. The external portion326is bonded in parallel to the exposed turn (e.g., using solder paste) or a portion of the turn. The parallel bonding increases the effective thickness of the exposed turn of the ACI to reduce the electrical resistance of the exposed turn. The bonding either in series or parallel can result in detectable features such as a seam or solder joint where the preform is attached.

The example ofFIG. 3shows the external portion326on the land side of the electronic semiconductor package302. If the ACI322extends to the land side surface and the opposite top surface, a second conductive layer can be bonded to a turn at the top surface to reduce a resistance of a turn at the top surface. The external portion326can be a metal preform.

The IC device300includes an IC die330arranged on the external surface opposite the landside surface. The IC die can include a FIVR circuit, and an ACI of the electronic semiconductor package302can be electrically connected to the FIVR circuit. The IC die330can include one or more processor circuits and one or more memory circuits. In some aspects, the IC die330includes multiple FIVR circuits that provide multiple voltage domains for the IC die330. An ACI of electronic semiconductor package302can be electrically connected to each of the FIVR circuits of the IC die330. The external portions of the ACIs can be used to reduce the overall size of the ACIs. This can result in a smaller electronic semiconductor package302for the same number of ACIs. Reducing the size of the ACIs can also allow for a larger power plane332internal to the electronic semiconductor package302.

FIGS. 5A-5Dis a flow diagram of a method500of forming an electronic device, such as the IC device of theFIG. 3. The process flow begins by fabricating an ACI within an electronic semiconductor package.FIG. 5Ais an illustration of a cross section view an electronic semiconductor package502. The electronic semiconductor package502inFIG. 5Ais inverted from the view inFIG. 3. The electronic semiconductor package502includes internal ACIs516and524. At least one opening is formed on an outer surface of the electronic semiconductor package. InFIG. 5A, openings520are formed to contact ACI516and opening528is formed to contact ACI524. Openings520will be used to connect an electrically conductive preform as an additional turn to ACI516, and opening528will be used to connect an electrically conductive preform to reduce resistance of ACI524. Although the flow diagram describes connecting conductive preforms to both increase inductance and reduce resistance, only one type of conductive preform may be connected and multiple preforms of the same type may be added to the electronic semiconductor package502.

The openings520and528can be formed using a solder resist exposure and development process. InFIG. 5B, solder paste is printed at the locations of the openings520and528.

InFIG. 5C, electrically conductive preform518and electrically conductive preform526are arranged on the outer surface of the electronic semiconductor package502. The electrically conductive preforms are electrically connecting the electrically conductive preform to the air core inductor using the openings520and528formed in the electronic semiconductor package. Electrically, conductive preform518is connected to ACI516as an added turn to the ACI coil to increase inductance of the internal ACI516. Electrically conductive preform526is connected to internal ACI524to increase an effective thickness and lower the resistance of at least one turn of internal ACI524. Passive electronic components512are also attached to the outer surface of the electronic semiconductor package502. InFIG. 5C, the electrically conductive preforms and passive electronic components are attached to the land side outer surface of the electronic semiconductor package. The preforms can be coated with a passivation material such as nickel or tin for example.

InFIG. 5D, the electronic semiconductor package502is inverted from the view inFIG. 5A. An IC die530is attached to the outer surface of the electronic semiconductor package that is opposite the surface (e.g., the land side surface) where the electrically conductive preforms were attached. Solder balls506or bumps may also be attached to the outer surface. The electronic semiconductor package502can be attached to a PCB using the solder balls as in the example ofFIG. 3.

FIGS. 6A-6Dis a flow diagram of another method600of forming an electronic device.FIG. 6Ais an illustration of a cross section view an electronic semiconductor package602. The electronic semiconductor package602includes openings620and628for connecting electrically conductive preforms to ACI. The electronic semiconductor package602may be produced by a supplier and may include passive electronic components612already surface mounted to the electronic semiconductor package602.

InFIG. 6B, an IC die630is attached to the outer surface of the electronic semiconductor package that is opposite to the surface having the openings620and628for attachment to the electrically conductive preforms. One difference from the flow diagram ofFIGS. 5A-5Dis that the IC die is attached prior to the attachment of an electrically conductive preform.

InFIG. 6C, the electronic semiconductor package602is inverted from the view inFIG. 6Aand flipped left to right. Solder paste is printed at the locations of the openings620and628.

InFIG. 6D, electrically conductive preform618and electrically conductive preform626are arranged on the outer surface (e.g., the land side surface) of the electronic semiconductor package602. Electrically conductive preform618is connected to internal ACI616as an added turn to the ACI coil to increase inductance of the internal ACI616. Electrically conductive preform626is connected to internal ACI624to increase an effective thickness and lower the resistance of at least one turn of internal ACI624. Solder balls606or bumps are attached to the land side outer surface.

An example of an electronic device using assemblies with system level packaging as described in the present disclosure is included to show an example of a higher level device application.

FIG. 7is a system level diagram, according to one embodiment of the invention. For instance,FIG. 7depicts an example of an electronic device (e.g., system) that can include one or more of the air core inductors as described in the present disclosure. In one embodiment, system700includes, but is not limited to, a desktop computer, a laptop computer, a netbook, a tablet, a notebook computer, a personal digital assistant (PDA), a server, a workstation, a cellular telephone, a mobile computing device, a smart phone, an Internet appliance or any other type of computing device. In some embodiments, system700is a system on a chip (SOC) system. In one example, two or more systems as shown inFIG. 7may be coupled together using one or more SWC cables as described in the present disclosure. In one specific example, one or more SWC interconnections as described in the present disclosure may implement a serial bus.

In one embodiment, processor710has one or more processing cores712and712N, where N is a positive integer and712N represents the Nth processor core inside processor710. In one embodiment, system700includes multiple processors including710and705, where processor705has logic similar or identical to the logic of processor710. In some embodiments, processing core712includes, but is not limited to, pre-fetch logic to fetch instructions, decode logic to decode the instructions, execution logic to execute instructions and the like. In some embodiments, processor710has a cache memory716to cache instructions and/or data for system700. Cache memory716may be organized into a hierarchal structure including one or more levels of cache memory.

In some embodiments, processor710includes a memory controller714, which is operable to perform functions that enable the processor710to access and communicate with memory730that includes a volatile memory732and/or a non-volatile memory734. In some embodiments, processor710is coupled with memory730and chipset720. Processor710may also be coupled to a wireless antenna778to communicate with any device configured to transmit and/or receive wireless signals. In one embodiment, the wireless antenna interface778operates in accordance with, but is not limited to, the IEEE 802.11 standard and its related family, Home Plug AV (HPAV), Ultra-Wide Band (UWB), Bluetooth, WiMax, or any form of wireless communication protocol.

Memory730stores information and instructions to be executed by processor710. In one embodiment, memory730may also store temporary variables or other intermediate information while processor710is executing instructions. In the illustrated embodiment, chipset720connects with processor710via Point-to-Point (PtP or P-P) interfaces717and722. Chipset720enables processor710to connect to other elements in system700. In some embodiments of the invention, interfaces717and722operate in accordance with a PtP communication protocol such as the Intel® QuickPath Interconnect (QPI) or the like. In other embodiments, a different interconnect may be used.

In some embodiments, chipset720is operable to communicate with processor710,705N, display device740, and other devices772,776,774,760,762,764,766,777, etc. Buses750and755may be interconnected together via a bus bridge772. Chipset720connects to one or more buses750and755that interconnect various elements774,760,762,764, and766. Chipset720may also be coupled to a wireless antenna778to communicate with any device configured to transmit and/or receive wireless signals. Chipset720connects to display device740via interface (I/F)726. Display740may be, for example, a liquid crystal display (LCD), a plasma display, cathode ray tube (CRT) display, or any other form of visual display device. In some embodiments of the invention, processor710and chipset720are merged into a single SOC. In one embodiment, chipset720couples with a non-volatile memory760, a mass storage medium762, a keyboard/mouse764, and a network interface766via I/F724and/or I/F726, I/O devices774, smart TV776, consumer electronics777(e.g., PDA, Smart Phone, Tablet, etc.).

While the modules shown inFIG. 7are depicted as separate blocks within the system700, the functions performed by some of these blocks may be integrated within a single semiconductor circuit or may be implemented using two or more separate integrated circuits. For example, although cache memory716is depicted as a separate block within processor710, cache memory716(or selected aspects of716) can be incorporated into processor core712.

The devices, systems, and methods described can provide an external means to increase the inductance and decrease the resistance of an ACI internal to an electronic package. If the ACI is included in an FIVR circuit, the improvement to the ACI can improve the efficiency of the FIVR circuit.

Additional Description and Examples

Example 1 includes subject matter (such as an electronic device) comprising an air core inductor. The air core inductor includes an electronic semiconductor package including a first portion of the air core inductor internal to the electronic semiconductor package; and an electrically conductive layer arranged on a first external surface of the electronic semiconductor package and electrically connected as a second portion of the air core inductor.

In Example 2, the subject matter of Example 1, optionally includes the electrically conductive layer electrically connected as at least one turn of the air core inductor.

In Example 3, the subject matter of one or both of Examples 1 and 2 optionally includes the electrically conductive layer connected to increase a thickness of at least one turn of the air core inductor.

In Example 4, the subject matter of one or any combination of Examples 1-3 optionally includes an integrated circuit (IC) die arranged on a second external surface opposite the first external surface, wherein the IC die includes a fully integrated voltage regulator (FIVR) circuit and the air core inductor is electrically connected to the FIVR circuit.

In Example 5, the subject matter of one or any combination of Examples 1-4 optionally includes an IC die including a processor circuit.

In Example 6, the subject matter of one or any combination of Examples 1-5 optionally includes the electrically conductive layer including a metal preform and the first external surface of the electronic semiconductor package is a land side surface of the electronic semiconductor package, and the electronic device includes the metal preform and a plurality of passive electronic components arranged on the land side surface.

In Example 7, the subject matter of Example 6 optionally includes the land side surface of the electronic semiconductor package coupled to a substrate using solder bumps, wherein the substrate includes a recess in motherboard (RIMB) and the electrically conductive layer and the passive electronic components are arranged in the RIMB.

In Example 8, the subject matter of Example 6 optionally includes metal preform including copper, and the plurality of passive electronic components including capacitors and discrete inductors.

Example 9 includes subject matter (such as a method of forming an electronic device), or can optionally be combined with one or any combination of Examples 1-8 to include such subject matter, comprising fabricating an air core inductor within an electronic semiconductor package; forming at least one opening on a first outer surface of the electronic semiconductor package; arranging a preformed electrically conductive element on the first outer surface of the electronic semiconductor package; and electrically connecting the preformed electrically conductive element to the air core inductor using the at least one opening in the electronic semiconductor package.

In Example 10, the subject matter of Example 9 optionally includes electrically connecting the preformed electrically conductive element to the air core inductor as at least one turn of the air core inductor via the at least one opening in the electronic semiconductor package.

In Example 11, the subject matter of one or both of Examples 9 and 10 optionally includes electrically connecting the preformed electrically conductive element, via the at least one opening in the electronic semiconductor package, to increase an effective thickness of at least one turn of the air core inductor.

In Example 12, the subject matter of one or any combination of Examples 9-11 optionally includes arranging the preformed electrically conductive element includes attaching the electrically conductive preform on a land side outer surface of the electronic semiconductor package, and attaching a plurality of passive electronic components on the land side surface.

In Example 13, the subject matter of one or any combination of Examples 9-12 optionally includes attaching an integrated circuit (IC) die to a second outer surface of the electronic semiconductor package opposite the first outer surface.

In Example 14, the subject matter of Example 13 optionally includes attaching the IC die prior to the arranging of the preformed electrically conductive element on the first outer surface of the electronic semiconductor package.

In Example 15, the subject matter of one or any combination of Examples 9-14 optionally includes forming at least one opening includes forming the at least one opening using solder resist exposure and development to form a solder resist opening in the first outer surface of the electronic semiconductor package.

In Example 16, the subject matter of one or any combination of Examples 9-15 optionally includes attaching the first outer surface of the electronic semiconductor package to a printed circuit board (PCB).

Example 17 includes subject matter (such as an electronic device), or can optionally be combined with one or any combination of Examples 1-16 to include such subject matter, comprising a plurality of air core inductors. The air core inductors include an electronic semiconductor package including a first portion of each of the air core inductors internal to the electronic semiconductor package, and a plurality of electrically conductive layers arranged on a first external surface of the electronic semiconductor package and each of the plurality of electrically conductive layers electrically connected as a second portion of each of the air core inductors.

In Example 18, the subject matter of Example 17 optionally includes an integrated circuit (IC) die arranged on a second external surface opposite the first external surface, wherein the IC die includes a plurality of fully integrated voltage regulator (FIVR) circuits configured to produce a plurality of voltage domains for the IC die, and each of the air core inductors is electrically connected to a FIVR circuit of the plurality of FIVR circuits.

In Example 19, the subject matter of one or both of Examples 17 and 18 optionally includes at least a portion of the plurality of electrically conductive layers are electrically connected as at least one turn of a corresponding air core inductor.

In Example 20, the subject matter of one or any combination of Examples 17-19 optionally includes at least a portion of the plurality of electrically conductive layers are electrically connected to reduce electrical resistance of at least one turn of a corresponding air core inductor.