Semiconductor package and method for fabricating the same

A semiconductor package includes a mounting board including a bonding pad, first and second semiconductor chips sequentially stacked on the mounting board, a first wire connecting a first region of the bonding pad to a chip pad of the first semiconductor chip, and a second wire connecting the first region of the bonding pad to a chip pad of the second semiconductor chip, the second wire having a reverse loop configuration.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims priority from Korean Patent Application No. 10-2012-0074540 filed on Jul. 9, 2012 in the Korean Intellectual Property Office, and all the benefits accruing therefrom under 35 U.S.C. 119, the contents of which in its entirety are herein incorporated by reference.

BACKGROUND

Example embodiments relate to a semiconductor package and to a method for fabricating the same.

2. Description of the Related Art

Pursuant to the request for implementation of high-performance devices, the size of a semiconductor chip is gradually decreasing. In order to meet requirements of multi-function, high-capacity semiconductor package, development of a multi-chip semiconductor package having multiple semiconductor chips stacked in a package is under way.

However, according to the trend toward slimness of an electronic device incorporating the semiconductor package, the semiconductor package tends to shrink. To cope with the trend toward slimness of the electronic device, various studies of methods for downsizing the semiconductor package are being conducted.

In order to integrate multiple semiconductor chips into a semiconductor package, it is necessary to establish electrical connections among the semiconductor chips and/or between the semiconductor chips and a mounting. In order to establish the electrical connections, various methods, e.g., wires, may be used.

SUMMARY

Example embodiments provide a semiconductor package, which is reduced in size by performing double bonding on connection pads when electrically connecting a plurality of chips to the connection pads on a mounding board using wires.

Example embodiments also provide a method for fabricating a semiconductor package, which is reduced in size.

According to an aspect of the example embodiments, there is provided a semiconductor package including a mounting board including a bonding pad, first and second semiconductor chips sequentially stacked on the mounting board, a first wire connecting a first region of the bonding pad to a chip pad of the first semiconductor chip, and a second wire connecting the first region bonded to the first wire and a chip pad of the second semiconductor chip and having a reverse loop configuration.

The first wire may be connected to the bonding pad in a stitch configuration, and the second wire is connected to the bonding pad in a ball bonding configuration.

The semiconductor package may further include a bump ball between the first wire and the second wire on the first region.

At least a portion of the second wire may overlap the first region.

The first semiconductor chip may include a first upper semiconductor chip and a first lower semiconductor chip, and the first wire connects a chip pad of the first lower semiconductor chip to the bonding pad.

The second semiconductor chip may include a second upper semiconductor chip and a second lower semiconductor chip, and the second wire connects a chip pad of the second lower semiconductor chip to the bonding pad.

The semiconductor package may further include a third wire connecting the chip pad of the first lower semiconductor chip to the chip pad of the first upper semiconductor chip, and a fourth wire connecting the chip pad of the second lower semiconductor chip to the chip pad of the second upper semiconductor chip.

The semiconductor package may further include third and fourth semiconductor chips sequentially stacked on the second semiconductor chip, and third and fourth wires connecting the bonding pad to chip pads of the third and fourth semiconductor chips, respectively, wherein the third wire is bonded to the bonding pad in a second region of the bonding pad, and the fourth wire is bonded to the second region having the third wire bonded thereto and has a reverse loop configuration.

The third semiconductor chip may include a third upper semiconductor chip and a third lower semiconductor chip, the third wire connecting the chip pad of the third lower semiconductor chip to the bonding pad.

The fourth semiconductor chip may include a fourth upper semiconductor chip and a fourth lower semiconductor chip, the fourth wire connecting the chip of the fourth lower semiconductor chip to the bonding pad.

The semiconductor package may further include a fifth wire connecting the chip pad of the third lower semiconductor chip to the chip pad of the third upper semiconductor chip, and a sixth wire connecting the chip pad of the fourth lower semiconductor chip to the chip pad of the fourth upper semiconductor chip.

According to another aspect of the example embodiments, there is provided a semiconductor package including a mounting board including a first bonding pad and a second bonding pad disposed to be spaced apart from each other, first to fourth semiconductor chips sequentially stacked between the first and second bonding pads and including first to fourth chip pads, respectively, a first wire connecting a first region of the first bonding pad to the first chip pad, and a second wire connecting a second region of the second bonding pad to the second chip pad, a third wire connecting the first region having the first wire bonded thereto to the third chip pad and having a reverse loop configuration, and a fourth wire connecting the second region having the second wire bonded thereto to the fourth chip pad and having a reverse loop configuration.

The semiconductor package may further include a bump ball on at least one of a portion between the first wire and the third wire on the first region, and a portion between the second wire and the fourth wire on the second region.

The first and second wires may be connected to the first and second bonding pads in a stitch configuration, respectively, the third and fourth wires being connected to the first and second bonding pads in a ball bonding configuration, respectively.

The semiconductor package may further include fifth to eighth semiconductor chips sequentially stacked on the fourth semiconductor chip and including fifth to eighth chip pads, wherein a third region of the first bonding pad is connected to the fifth chip pad by a fifth wire, a fourth region of the second bonding pad is connected to the sixth chip pad by a sixth wire, the third region having the fifth wire bonded thereto is connected to a seventh chip pad by a seventh wire having a reverse loop configuration, and the fourth region having the seventh wire bonded thereto is connected to an eighth chip pad by an eighth wire having a reverse loop configuration.

According to another aspect of the example embodiments, there is provided a semiconductor package including a mounting board including a bonding pad, first and second semiconductor chips sequentially stacked on the mounting board, a first wire connecting a first region of the bonding pad to a chip pad of the first semiconductor chip, and a second wire connecting the first region of the bonding pad to a chip pad of the second semiconductor chip, the second wire being connected to the first region through the first wire.

The first wire may define a first connection region in the first region of the bonding pad, and the second wire may define a second connection region in the first region of the bonding pad, the first and second connection regions at least partially overlap each other.

A portion of the second connection region may directly contact the bonding pad.

The entire second connection region may contact the bonding pad only through the first connection region.

Centers of the first and second connections regions may not overlap.

DETAILED DESCRIPTION

It will be understood that when an element or layer is referred to as being “connected to” or “coupled to” another element or layer, it can be directly connected to or coupled to another element or layer or intervening elements or layers may be present. In contrast, when an element is referred to as being “directly connected to” or “directly coupled to” another element or layer, there are no intervening elements or layers present. It will also be understood that when a layer is referred to as being “on” another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may also be present. In contrast, when an element is referred to as being “directly on” another element, there are no intervening elements present. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items.

Hereinafter, a semiconductor package according to an embodiment will be described with reference toFIGS. 1A to 3B.

FIGS. 1A and 1Bare side views of a semiconductor package according to an embodiment,FIG. 2is an enlarged side view of portion “I” ofFIG. 1A, andFIGS. 3A and 3Bare enlarged plan views of a top portion of a bonding pad in portion “I”.

First, referring toFIGS. 1A and 1B, a semiconductor package10may include a mounting board100, a first semiconductor chip200, a second semiconductor chip300, a first wire250, and a second wire350. The mounting board100may include a first bonding pad110on a surface on which the first semiconductor chip200and the second semiconductor chip300are disposed. The first semiconductor chip200and the second semiconductor chip300are sequentially mounted on the mounting board100and include a first chip pad202and a second chip pad302, respectively. The first wire250may electrically connect the first bonding pad110and the first chip pad202, and may be bonded to a first region (A1ofFIG. 3A) of the first bonding pad110. The second wire350may electrically connect the first bonding pad110to the second chip pad302, and may be bonded to the first region of the first bonding pad110. In other words, the first wire250and the second wire350are double bonded in the first region of the first bonding pad110, e.g., the first region may be a double bonded region having two bonding regions of two different wires at least partially overlap on the bonding pad110. The second wire350may be, e.g., a reverse loop wire.

In detail, the mounting board100may be a board for packaging, e.g., a printed circuit board (PCB) or a ceramic substrate. An external terminal (not shown) electrically connecting the semiconductor package to an external device may be formed on a bottom surface of the mounting board100, i.e., a mounting surface on which the semiconductor chips200and300are disposed. The first bonding pad110may be electrically connected to the external terminal connected to the external device, and may supply an electrical signal to the semiconductor chip200and300. Alternatively, the first bonding pad110may be, e.g., a ground pad, and may be electrically connected to a ground line (not shown) in the mounting board100. In the illustrated embodiment, the first bonding pad110is disposed on, e.g., a peripheral portion of the mounting board100, but aspects of the example embodiments are not limited thereto.

The first semiconductor chip200and the second semiconductor chip300may be, e.g., memory chips, logic chips, or the like. When the first semiconductor chip200and/or the second semiconductor chip300are logic chips, they may be designed in various manners in consideration of the operation to be executed. When the first semiconductor chip200and/or the second semiconductor chip300are memory chips, the memory chips may be, e.g., non-volatile memory chips. For example, the memory chip100may be a flash memory chip, e.g., a NAND flash memory chip or a NOR flash memory chip, but the example embodiments are not limited to the above. In some embodiments, the memory chip100may include at least one of a phase change random access memory (PRAM), a magneto-resistive random access memory (MRAM), a resistive random access memory (RRAM), and so on.

The first chip pad202of the first semiconductor chip200and the second chip pad302of the second semiconductor chip300are electrically connected to semiconductor devices incorporated in the first semiconductor chip200and the second semiconductor chip300, respectively. Therefore, since the first chip pad202and the second chip pad302are electrically connected to the first bonding pad110, they may perform a same function in the respective semiconductor devices.

The first semiconductor chip200and the mounting board100may be attached by a first adhesive film150, and the first semiconductor chip200and the second semiconductor chip300may be attached by a second adhesive film152. The first and second adhesive films150and152may be, e.g., die attach films (DAFs) or adhesive films into which a wire can penetrate. The first and second adhesive films150and152may have different thicknesses according to locations to which the first and second adhesive films150and152are attached. The adhesive films into which a wire can penetrate, e.g., the second adhesive film152into which the first wire250can penetrate, may be thicker than the first adhesive film150so as to protect the second wire350. Here, “the wire penetrating into an adhesive film” means that even if an adhesive film is provided, the wire is surrounded by the adhesive film and its shape is maintained without being changed.

The first wire250and the second wire350may be made of a metal material, e.g., gold, copper, or aluminum. The first wire250and the second wire350may be connected to the first bonding pad110by, e.g., a heat compression method, an ultrasonic method, etc., but not limited thereto.

When wire bonding starts from a chip pad of a semiconductor chip, the wire is formed by forward bonding and is a forward loop wire. On the contrary, when wire bonding terminates at a chip pad of a semiconductor chip, the wire is formed by forward bonding and is a reverse loop wire. In the following description of the semiconductor package according to the example embodiments, the first wire250may be, e.g., a forward or reverse loop wire. However, the second wire350may be, e.g., a reverse loop wire, which allows a clearance between the first wire250and the second wire350to be secured. In other words, when a plurality of wires, e.g., two wires, are overlapped with each other at the same region of the first bonding pad110to perform double bonding thereon, the later formed second wire350should have a reverse loop configuration to secure a clearance between the same and the earlier formed first wire250.

Referring toFIGS. 1A and 1B, exemplary methods of stacking the semiconductor package10according to an embodiment are illustrated. It is assumed that the first semiconductor chip200and the second semiconductor chip300have the same width. In the semiconductor package10shown inFIG. 1A, the second semiconductor chip300is disposed to overlap the first semiconductor chip200. Therefore, the semiconductor package10may have, e.g., a linear lateral profile. In addition, the first wire250may be configured to penetrate into the second adhesive film152in view of the lateral profile. In the semiconductor package10shown inFIG. 1B, the second semiconductor chip300is disposed to partially overlap the first semiconductor chip200. Therefore, the semiconductor package10may have, e.g., a stepwise lateral profile.

Referring toFIG. 2, the first wire250is bonded to the first bonding pad110. The second wire350is bonded to the bonded first wire250. The first wire250is bonded to the first bonding pad110in a stitch configuration, for example. However, the second wire350is bonded to the first wire250, i.e., to the first bonding pad110, in a ball bonding configuration, for example.

The first wire250connecting the first chip pad202and a first region (A1ofFIG. 3A) of the first bonding pad110may be formed by forward bonding. Here, the first wire250may have a stitch part252having a wedge shape and a first wire body254. The stitch part252is a part that is actually bonded to the first bonding pad110and has a thickness that gradually decreases as a horizontal distance from the first wire body254increases.

The second wire350connecting the second chip pad302and the first region of the first bonding pad110may be formed by reverse bonding. Here, the second wire350may have a ball part352having a ball shape and a second wire body354. For example, the ball part352disposed on the stitch part252may be a part formed by a capillary used in wire bonding. Since the second wire350starts from the stitch part252of the first bonding pad110, the ball part352may be formed in the second wire350.

Referring toFIG. 2, an angle formed by the first wire250and the mounting board100may be smaller than an angle formed by the second wire350and the mounting board100, which is for the purpose of securing a clearance between the first wire250and the second wire350. A distance between the first wire body254and the second wire body354may be indicated by d1, which increases as an angle formed by the first wire250and the second wire350increases. In addition, as a size of the ball part352of the second wire350increases, d1may increase. The clearance between the first wire250and the second wire350may be adjusted by controlling the processing condition.

Referring toFIGS. 3A and 3B, an upper surface110uof the first bonding pad110may be bonded to the first wire250at a region A1, and may be bonded to the second wire350at a region B1. Since the second wire350is formed after the first wire250is bonded to the first bonding pad110, the region B1may be a region formed on the region A1. In the illustrated embodiment, the regions A1and B1are circular, which is only for brevity of explanation, but aspects of the example embodiments are not limited thereto.

For example, referring toFIG. 3A, the region B1having the second wire350bonded thereto is positioned at the region A1having the first wire250bonded thereto, i.e., the region B1may be completely overlapped by the region A1. This means that the second wire350is only bonded, e.g., directly bonded, to the first wire250, i.e., the second wire350is not directly bonded to the first bonding pad110. That is to say, the second wire350is electrically connected to the first bonding pad110through the first wire250. Since it is necessary for the second wire350to be bonded on the stitch part252of the first wire250shown inFIG. 2, a center of the region B1having the second wire350bonded thereto is separated from the center of the region A1having the first wire250bonded thereto. In other words, while portions of the regions A1and B1may overlap, centers of the regions A1and B1may not overlap. However, the stitch part252of the first wire250may be configured in various manners according to the processing condition in bonding the first wire250to the first bonding pad110, but aspects of the example embodiments are not limited thereto.

In another example, referring toFIG. 3B, a portion of the region B1having the second wire350bonded thereto overlaps the region A1having the first wire250bonded thereto, i.e., only a portion of the second wire350overlaps the region A1having the first wire250bonded thereto. Therefore, region B1having the second wire350bonded thereto may include a first portion bonded to the first bonding pad110through the first wire250and a second portion directly bonded to the first bonding pad110. Here, even if the region B1having the second wire350bonded thereto only partially overlaps the region A1having the first wire250bonded thereto, the first wire250and the second wire350are double bonded on the first bonding pad110.

A modified example of the semiconductor package according to an embodiment will now be described with reference toFIG. 4. Since the modified example is substantially the same as the previous embodiment, except that the semiconductor package further includes a bump ball, the same functional components are denoted by the same reference numerals and the description thereof will be made briefly or omitted.

FIG. 4is an enlarged plan view of a bonding pad for explaining a modified example of the semiconductor package according to an embodiment.

Referring toFIG. 4, the first wire250is bonded on the first bonding pad110. The second wire350is bonded on the bonded first wire250. A bump ball130may be disposed between the first wire250and the second wire350. A plurality of bump balls130may be disposed between the first wire250and the second wire350. In the illustrated embodiment, only one bump ball130is shown, which is only for brevity of explanation, but aspects of the example embodiments are not limited thereto. For example, the first wire250is connected, e.g., directly, to the first bonding pad110in a stitch configuration, and the second wire350is connected to the first wire250, i.e., the second wire350is connected to the first bonding pad110through the bump ball130and first wire250in a ball bonding configuration. In other words, the bump ball130is disposed between the first wire stitch part252and the second wire ball part352of the second wire350.

For example, the bump ball130may be made of the same material as the second wire350. The bump ball130may be formed before forming the second wire350or may be formed by a capillary used in wire bonding. Referring toFIG. 4, the bump ball130may be used to adjust a clearance between the first wire250and the second wire350. When the bump ball130is provided, a distance between the first wire body254and the second wire body354may be d2, which may be different from d1ofFIG. 2in which the bump ball130is not provided. Assuming that processing conditions for forming the first wire250and the second wire350are the same, an angle formed by the first wire250and the second wire350with respect to the first wire stitch part252may be the same as the angle ofFIG. 2. The bump ball130is disposed on the stitch part252, and the second wire ball part352is disposed on the bump ball130. A distance between the second wire ball part352and the stitch part252may differ depending on the presence or absence of the bump ball130. Since a length of a chord increases away from the center of a fan-shaped sector, the distance d2with the bump ball130is greater than the distance d2without the bump ball130, which is because a starting point of the second wire350becomes farther from the first wire stitch part252by the bump ball130. The clearance between the first wire250and the second wire350can be easily obtained by adjusting the number of bump balls130disposed between the first wire250and the second wire350on the first bonding pad110.

Semiconductor packages according to other embodiments will be described with reference toFIGS. 5A to 6B.FIGS. 5A to 5Care side views of a semiconductor package according to another embodiment, andFIGS. 6A and 6Bare views illustrating exemplary stacks of semiconductor chips for implementing a semiconductor package ofFIG. 5B, except for wires.

Referring toFIG. 5A, a first semiconductor chip200may include a first upper semiconductor chip220and a first lower semiconductor chip210. In other words, the first semiconductor chip200may be a multi-chip having a plurality of chips, but the second semiconductor chip300may be a single chip. The first lower semiconductor chip210and the first upper semiconductor chip220may be sequentially stacked on the mounting board100, and the second semiconductor chip300may further be stacked thereon. A chip pad222of the first upper semiconductor chip220and a chip pad212of the first lower semiconductor chip210may be connected to each other by a first inter-chip wire260. The first wire250may connect a first region (A1ofFIG. 3) of the first bonding pad110to the chip pad212of the first lower semiconductor chip210. The second wire350electrically connects the first bonding pad110and the second chip pad302and is bonded to the first region of the first bonding pad110having the first wire250bonded thereto. The second wire350is a reverse loop wire.

Referring toFIG. 5B, the first semiconductor chip200may include the first upper semiconductor chip220and the first lower semiconductor chip210. The second semiconductor chip300may include a second upper semiconductor chip320and a second lower semiconductor chip310. That is to say, each of the first semiconductor chip200and the second semiconductor chip300may be a multi-chip having a plurality of chips. The first lower semiconductor chip210, the first upper semiconductor chip220, the second lower semiconductor chip310, and the second upper semiconductor chip320are sequentially stacked on the mounting board100. The chip pad222of the first upper semiconductor chip220and the chip pad212of the first lower semiconductor chip210may be connected to each other by the first inter-chip wire260. A chip pad322of the second upper semiconductor chip320and a chip pad312of the second lower semiconductor chip310may be connected to each other by a second inter-chip wire360. The first wire250connects a first region of the first bonding pad110to the chip pad212of the first lower semiconductor chip210. The second wire350having a reverse loop configuration connects the first region of the first bonding pad110having the first wire250bonded thereto to the chip pad312of the second lower semiconductor chip310, thereby establishing double bonding.

It is assumed that all of the first lower semiconductor chip210, the first upper semiconductor chip220, the second lower semiconductor chip310, and the second upper semiconductor chip320have the same width. As shown inFIG. 5B, the first semiconductor chip200and the second semiconductor chip300are stacked to have a zigzag lateral profile, in which projections and depressions are periodically formed, but aspects of the example embodiments are not limited thereto. That is to say, the stacked first and second semiconductor chips200and300may have, for example, a stepwise lateral profile. Here, even if the sequentially stacked semiconductor chips have different sizes, they may be stacked in a zigzag configuration.

In order to ensure wire bonding efficiency, the first wire250and the second wire350may connect chip pads212and312of semiconductor chips210and310protruding toward the first bonding pad110, among semiconductor chips included in the semiconductor package12, to the first bonding pad110, respectively.

Referring toFIG. 5C, a semiconductor package13may include the first semiconductor chip200and the second semiconductor chip300, each being a multi-chip including a plurality of semiconductor chips. The semiconductor package13is substantially the same as the semiconductor package12shown inFIG. 5B, except for the number of semiconductor chips forming each of the first semiconductor chip200and the second semiconductor chip300. A chip pad212of a first lower semiconductor chip closest to the first bonding pad110and the first bonding pad110may be connected by the first wire250, and a chip pad312of a second lower semiconductor chip closest to the first bonding pad110and the first bonding pad110may be connected by the second wire350. The plurality of semiconductor chips forming each of the first semiconductor chip200and the second semiconductor chip300may be stacked stepwise, but aspects of the example embodiments are not limited thereto.

FIGS. 6A and 6Billustrate exemplary stacked configurations of semiconductor chips for implementing the semiconductor package12ofFIG. 5B. The first lower semiconductor chip210, the first upper semiconductor chip220, the second lower semiconductor chip310, and the second upper semiconductor chip320are sequentially stacked on the mounting board100.

Referring toFIG. 6A, chip pads212,312, and322of semiconductor chips210,220,310, and320are arranged in a first direction x, and the first bonding pad110is also arranged in the first direction x. Assuming the semiconductor chips210,220,310, and320have a width, e.g., w1, edges of the semiconductor chips210,220,310, and320stacked on the mounting board100may be arranged in a staggered manner in a second direction y in a zigzag configuration. However, edges of the semiconductor chips210,220,310, and320not arranged in a staggered manner may be aligned toward a normal line of the mounting board100, but aspects of the example embodiments are not limited thereto. Edges of the semiconductor chips210,220,310, and320stacked on the mounting board100may be arranged in a staggered manner in at least two directions x and y.

Referring toFIG. 6B, each of the semiconductor chips210,220,310, and320may have, e.g., a rectangular plane shape. A length of one side of the rectangular plane may be w1and a length of the other side may be w2. The sequentially stacked semiconductor chips210,220,310, and320may be arranged in a rotated state of an angle of 90 degrees. Chip pads212and312of a first lower semiconductor chip210and a second lower semiconductor chip310may be arranged along one of edges of the rectangle having the length w1. On the contrary, the chip pads212and312of a first upper semiconductor chip220and a second upper semiconductor chip320may be arranged along one of edges of the rectangle having the length w2. However, the chip pads212,222,312, and322of the semiconductor chips210,220,310, and320are arranged in the first direction x and a first bonding pad110is also arranged in the first direction x.

A modified example of the semiconductor package according to another embodiment of the example embodiments will be described with reference toFIGS. 7Aand7B.FIG. 7Ais a side view illustrating a modified example ofFIG. 5B, andFIG. 7Bis a view illustrating an exemplary stacked configuration of semiconductor chips for implementing a semiconductor package ofFIG. 7A, except for wires.

Referring toFIG. 7A, the first lower semiconductor chip210and the second lower semiconductor chip310may have a width w2in the second direction y, and a first upper semiconductor chip220and a second upper semiconductor chip320may have a width w1in the second direction y. One of lateral surfaces of the stacked first and second semiconductor chips200and300, which is adjacent to a first bonding pad110, may have, e.g., a zigzag configuration. However, at least one lateral surfaces of the stacked first and second semiconductor chips200and300, which is not adjacent to a first bonding pad110, may be arranged in a line.

Referring toFIG. 7B, edges of the semiconductor chips210,220,310, and320having chip pads arranged in a line may have the same width. Alternatively, the edges of the semiconductor chips210,220,310, and320having chip pads arranged in a line may have different widths.

A semiconductor package according to still another embodiment will be described with reference toFIGS. 8 to 9B.FIG. 8is a side view of a semiconductor package according to still another embodiment, andFIGS. 9A and 9Bare enlarged plan views of a top portion of a bonding pad in portion “I” ofFIG. 1A.

Referring toFIG. 8, a semiconductor package15includes first to fourth semiconductor chips200,300,400, and500sequentially stacked on the mounting board100. The semiconductor package15may further include first to fourth wires250,350,450, and550connecting the first bonding pad110to first to fourth chip pads202,302,402,band502. The first wire250is bonded to a first region (A1ofFIG. 9A) of the first bonding pad110and connects the first bonding pad110to the first chip pad202. The second wire350is bonded to the first region having the first wire250bonded thereto and connects the first bonding pad110to the second chip pad302. The third wire450is bonded to a second region (A2ofFIG. 2) of the first bonding pad110and connects the first bonding pad110to the third chip pad402. The fourth wire550is bonded to the second region having the third wire450bonded thereto and connects the first bonding pad110to the fourth chip pad502. In other words, the first wire250and the second wire350are double bonded in the first region of the first bonding pad110, and the third wire450and the fourth wire550are double bonded in the second region of the first bonding pad110. The second wire350and the fourth wire550may be, e.g., a reverse loop wire.

Referring toFIG. 8, the first to fourth semiconductor chips200,300,400, and500may be stacked to have a zigzag lateral profile. The first to fourth semiconductor chips200,300,400, and500may have the same width, but aspects of the example embodiments are not limited thereto.

Referring toFIGS. 9A and 9B, the upper surface110uof the first bonding pad110is bonded to the first wire250at the first region A1, and the upper surface110uof the first bonding pad110is bonded to the second wire350at the region B1. The upper surface110uof the first bonding pad110is bonded to the third wire450at the second region A2, and the upper surface110uof the first bonding pad110is bonded to the fourth wire550at the region B2. The first region A1, having the first wire250bonded thereto, and the second region A2may be spaced apart from each other, and a distance therebetween may be “d”.

Referring toFIG. 9A, the region B1, where the first wire250and the second wire350are double bonded, and the region B2, where the third wire450and the fourth wire550are double bonded, may be positioned on a center line M of the bonding pad110. However, example embodiments are not limited thereto, e.g., the regions A1, A2, B1, and B2may have different orientations.

Referring toFIG. 9B, a potion of the second wire350may overlap the first region A1and a portion of the fourth wire550may overlap the second region A2. Here, the first region A1and the second region A2are spaced apart from each other by the distance d. However, a distance between the double bonded region between the first wire250and the second wire350and the double bonded region between the third wire450and the fourth wire550may be d′. Here, d′ and d may be different from each other, and in some cases, d′ may be 0. When d′ is 0, the first to fourth wires250,350,450, and550may be physically in contact with each other.

A semiconductor package according to still another embodiment will be described with reference toFIGS. 10A and 10B. In the following description, the semiconductor package shown inFIGS. 10A and 10Bwill be described assuming that the third semiconductor chip and the fourth semiconductor chip shown inFIG. 5Bare stacked.FIGS. 10A and 10Bare side views of a semiconductor package according to still another embodiment.

Referring toFIG. 10A, a third semiconductor chip400may be a multi-chip including a third upper semiconductor chip420and a third lower semiconductor chip410, and a fourth semiconductor chip500may be a single chip. The third lower semiconductor chip410, the third upper semiconductor chip420, and the fourth semiconductor chip500are sequentially stacked on the second upper semiconductor chip320. A chip pad422of the third upper semiconductor chip420and a chip pad412of the third lower semiconductor chip410may be connected by a third inter-chip wire460. A third wire450may connect a second region (A2ofFIG. 9A) of the first bonding pad110to the chip pad412of the third lower semiconductor chip410. A fourth wire550may electrically connect the first bonding pad110to a fourth chip pad502and may be bonded to the second region of the first bonding pad110having the third wire450bonded thereto. The second wire350may be a reverse loop wire.

Referring toFIG. 10B, the third semiconductor chip400may include a third upper semiconductor chip420and a third lower semiconductor chip410, and the fourth semiconductor chip500may include a fourth upper semiconductor chip520and a fourth lower semiconductor chip510. The chip pad422of the third upper semiconductor chip420and the chip pad412of the third lower semiconductor chip410may be connected by the third inter-chip wire460, and a chip pad522of the fourth upper semiconductor chip520and a chip pad512of the fourth lower semiconductor chip510may be connected by a fourth inter-chip wire560. The third wire450connects the second region of the first bonding pad110to the chip pad412of the third lower semiconductor chip410. The fourth wire550having a reverse loop configuration connects the second region of the first bonding pad110having the third wire450bonded thereto to the chip pad312of the second lower semiconductor chip310, thereby establishing double bonding.

The third lower semiconductor chip410, the third upper semiconductor chip420, the fourth lower semiconductor chip510, and the fourth upper semiconductor chip520sequentially stacked on the second upper semiconductor chip320may have the same widths. As shown inFIG. 10B, the first to fourth semiconductor chips200,300,400, and500are stacked to have a zigzag lateral profile in which projections and depressions are periodically formed, but aspects of the example embodiments are not limited thereto.

A semiconductor package according to still another embodiments will be described with reference toFIGS. 11 to 12B.

FIG. 11is a side view of a semiconductor package according to still another embodiment, andFIGS. 12A and 12Billustrate mounting boards to be used in the semiconductor package shown inFIG. 11.

Referring toFIG. 11, a semiconductor package18may include a mounting board100, first to fourth semiconductor chips200,300,400, and500, and first to fourth wires250,350,450, and550. In detail, the mounting board100may include the first bonding pad110and the second bonding pad120. The first bonding pad110and the second bonding pad120may be disposed to be spaced apart from each other. For example, the first bonding pad110and the second bonding pad120may be disposed at facing edges on the mounting board100, but aspects of the example embodiments are not limited thereto.

The sequentially stacked first to fourth semiconductor chips200,300,400, and500may be disposed between the first bonding pad110and the second bonding pad120. The first to fourth semiconductor chips200,300,400, and500may include first to fourth chip pads202,302,402, and502, respectively. For example, the first chip pad202and the third chip pad402included in the first and third semiconductor chips200and400may be disposed at edges adjacent to the first bonding pad110, and the second chip pad302and the fourth chip pad502included in the second and fourth semiconductor chips300and500may be disposed at edges adjacent to the second bonding pad120, which is, however, provided only for illustration of the semiconductor package according to the example embodiments, but aspects of the example embodiments are not limited thereto.

In the illustrated embodiment, the sequentially stacked first to fourth semiconductor chips200,300,400, and500have the same width and are stacked in a line, but aspects of the example embodiments are not limited thereto.

The first wire250electrically connects the first bonding pad110to the first chip pad202and is bonded to a first region (A1ofFIG. 14) of the first bonding pad110. The second wire350electrically connects the second bonding pad120to the second chip pad302and is bonded to a third region (A3ofFIG. 14) of the second bonding pad120. The third wire450may connect the first region having the first wire250bonded thereto to the third chip pad402, thereby electrically connecting the third chip pad402and the first bonding pad110. The fourth wire550may connect the third region having the second wire350bonded thereto to the fourth chip pad502, thereby electrically connecting the fourth chip pad502to the second bonding pad120. The third wire450bonded to the first region of the first bonding pad110and the fourth wire550bonded to the third region of the second bonding pad120may be, for example, a reverse loop wire. In addition, the first wire250and the third wire450may be double bonded in the first bonding pad110, and the second wire350and the fourth wire550may be double bonded in the second bonding pad120.

The semiconductor package18may further include the bump ball130, as shown inFIG. 4, disposed between the first wire250and the second wire350, which are double bonded in the first region of the first bonding pad110. In addition, the semiconductor package18may further include a bump ball disposed between the second wire350and the fourth wire550, which are double bonded in the third region of the second bonding pad120. That is to say, the semiconductor package18may further bump balls between the first wire250and the second wire350on the first region of the first bonding pad110and/or between the second wire350and the fourth wire550on the third region of the second bonding pad120.

Referring toFIGS. 2 and 1, the first wire250and the second wire350may be bonded to the first bonding pad110and the second bonding pad120in a stitch configuration, respectively, to be connected. The third wire450and the fourth wire550may be bonded to the first bonding pad110and the second bonding pad120in a ball bonding configuration, respectively, to be connected.

Referring toFIG. 12A, the first bonding pad110and the second bonding pad120may be disposed at facing edges on the mounting board100, but aspects of the example embodiments are not limited thereto. The first bonding pad110and the second bonding pad120may be arranged in the first direction x. The first to fourth chip pads202,302,402and502may also be arranged in the first direction x. The first chip pad202and the third chip pad402may be arranged at edges of the semiconductor chip, which is adjacent to the first bonding pad110, and the second chip pad302and the fourth chip pad502may be arranged at edges of the semiconductor chip, which is adjacent to the second bonding pad120.

Referring toFIG. 12B, the first bonding pad110disposed at one edge of the mounting board100may be arranged in the first direction x. The second bonding pad120disposed at the other edge of the mounting board100adjacent to the edge where the first bonding pad110is disposed may be arranged in the second direction y. The direction in which the first to fourth chip pads connected to the first bonding pad110and the second bonding pad120are arranged may be determined by the direction in which the first bonding pad110and the second bonding pad120are arranged.

A semiconductor package according to still another embodiment will be described with reference toFIGS. 13 and 14. In the following description, the semiconductor package shown inFIG. 13will be described assuming that the fifth to eighth semiconductor chips shown inFIG. 11are stacked.

FIG. 13is a side view of a semiconductor package according to still another embodiment.FIG. 14is an enlarged plan view illustrating top portions of bonding pads in “III” and “IV” portions ofFIG. 13.

Referring toFIG. 13, a semiconductor package19may include fifth to eighth semiconductor chips600,700,800, and900. The fifth to eighth semiconductor chips600,700,800, and900are sequentially stacked on a fourth semiconductor chip500and may be arranged in a line, but aspects of the example embodiments are not limited thereto. A fifth chip pad602and a seventh chip pad802may be disposed at edges of the semiconductor chip adjacent to the first bonding pad110, and a sixth chip pad702and an eighth chip pad902may be disposed at edges of the semiconductor chip adjacent to a second bonding pad120.

The fifth wire650connects a second region (A2ofFIG. 14) of the first bonding pad110to the first chip pad202, and the sixth wire750connects a fourth region (A4ofFIG. 14) of the second bonding pad to the sixth chip pad702. A seventh wire850having a reverse loop configuration connects the second region having the fifth wire650bonded thereto to the seventh chip pad802, and an eighth wire950having a reverse loop configuration connects the fourth region having the sixth wire750bonded thereto to the eighth chip pad902.

The first wire250and the third wire450, and the fifth wire650and the seventh wire850are double bonded, respectively, on the first bonding pad110. In addition, the second wire350and the fourth wire550, and the sixth wire750and the eighth wire950are double bonded, respectively, on the second bonding pad120.

Referring toFIG. 14, the first region A1where the first wire250is bonded to the first bonding pad110and the second region A2where the fifth wire650is bonded to the first bonding pad110may be spaced apart from each other. In addition, the third region A3where the second wire350is bonded to the second bonding pad120and the fourth region A4where the sixth wire650is bonded to the second bonding pad120may be spaced apart from each other.

Like two types of double bonding established in the first bonding pad110, the double bonded regions B1and B2may be positioned on the center line M of the first bonding pad110, respectively. However, like two types of double bonding established in the second bonding pad120, the double bonded regions B3and B4may be spaced apart from the center line M of the second bonding pad120, respectively.

In addition, like in the first bonding pad110, the third wire450and the seventh wire850may completely overlap the first region A1and the second region A2. However, like in the second bonding pad120, only one of the third wire450and the seventh wire850may completely overlap the first region A1and the second region A2, and the other may partially overlap the first region A1and the second region A2.

A package-on-package (POP) structure including a semiconductor packages according to embodiments will be described with reference toFIGS. 15A to 15D.FIGS. 15A to 15Dillustrate package-on-package (POP) structures using semiconductor packages according to embodiments.

Referring toFIG. 15A, an upper semiconductor package2may correspond to the semiconductor package12shown inFIG. 2, which is surrounded by an upper molding member140and a lower semiconductor package1may correspond to the semiconductor package18shown inFIG. 18, which is surrounded by a lower molding member140-1. The upper molding member140and the lower molding member140-1may be made of, e.g., an epoxy molding compound (EMC). A mounting board100of the upper semiconductor package2and a mounting board100-1of the lower semiconductor package1may be electrically connected by a conductive connecting part4. The conductive connecting part4may include, e.g., a solder material. An external terminal3that can be electrically connected to an external device may be attached to the other surface corresponding to one surface of the mounting board100-1of the lower semiconductor package1. The semiconductor package12shown inFIG. 5Bmay be included in the lower semiconductor package1and the semiconductor package18shown inFIG. 11may be included in the upper semiconductor package2.

Referring toFIG. 15B, the POP structure may be a package-on-package having the upper semiconductor package2and the lower semiconductor package1using the semiconductor package12shown inFIG. 5Bstacked vertically. The POP structure shown inFIG. 15Bis different from the POP structure shown inFIG. 15Ain that the same number of bonding pads are included in the semiconductor package used for the lower semiconductor package1and the upper semiconductor package2.

Referring toFIG. 15C, the POP structure may be a package-on-package having the upper semiconductor package2and the lower semiconductor package1using the semiconductor package12shown inFIG. 5Bstacked in a mirrored manner. The POP structure shown inFIG. 15Cis different from the POP structure shown inFIG. 15Bin that the upper and lower semiconductor packages are stacked in different directions.

Referring toFIG. 15D, the upper semiconductor package2using the semiconductor package12shown inFIG. 5Bmay be disposed on the lower semiconductor package1having the semiconductor chip5without double wire bonding. In the illustrated embodiment, the semiconductor chip5is connected to the mounting board of the lower semiconductor package by a solder ball6, but aspects of the example embodiments are not limited thereto.

FIG. 16is a perspective view of an electronic device including a semiconductor package according to embodiments.

Referring toFIG. 16, the semiconductor package according to embodiments may be applied to an electronic device1000, such as a cellular phone. Since the semiconductor package according to embodiments of the example embodiments is highly reliable, the operating reliability of the electronic device1000can be ensured even under harsh conditions. The electronic device1000is not limited to the cellular phone shown inFIG. 16, and examples thereof may include a variety of electronic devices, such as a mobile electronic device, a notebook computer, a portable multimedia player (PMP), an MP3 player, a camcorder, a memory stick, or a memory card.

A method for fabricating a semiconductor package according to an embodiment will be described with reference toFIGS. 17A to 17D. In the following description, the semiconductor package according to the example embodiments will be described with regard to the semiconductor package shown inFIG. 10B.

FIGS. 17A to 17Dillustrate a method for fabricating a semiconductor package according to an embodiment.

Referring toFIG. 17A, a first semiconductor chip200is disposed on a mounting board100including a first bonding pad110The first semiconductor chip200may be single chip, but may also include a plurality of chips. The first semiconductor chip200may include a first lower semiconductor chip210and a second upper semiconductor chip320. Here, the first lower semiconductor chip210and the first upper semiconductor chip220may be sequentially stacked on the mounting board100.

A chip pad of the first semiconductor chip200and the first bonding pad110may be wire bonded by a first wire250. The first wire250may be bonded to the first bonding pad110in a second region A2. Referring toFIG. 17A, a chip pad222of the first upper semiconductor chip220and a chip pad212of the first lower semiconductor chip210may be connected by a first inter-chip wire260, and the chip pad212of the first lower semiconductor chip210and a first region A1of the first bonding pad110may be connected by a first wire250. The first wire250and the first inter-chip wire260may be formed in any arbitrary order. For example, the chip pad222of the first upper semiconductor chip220and the chip pad212of the first lower semiconductor chip210may first be connected by the first inter-chip wire260, and the chip pad212of the first lower semiconductor chip210and the first region A1of the first bonding pad110may then by connected by the first wire250.

Referring toFIG. 17B, a second semiconductor chip300may be stacked on the first semiconductor chip200. In a case where the second semiconductor chip300includes a second lower semiconductor chip310and a second upper semiconductor chip320, the second lower semiconductor chip310and the second upper semiconductor chip320may be sequentially stacked on the first upper semiconductor chip220.

A chip pad of the second semiconductor chip300and the first region A1of the first bonding pad110may be wired by a second wire350. Since a reverse wiring method is used for wiring to form the second wire350, the second wire350is a reverse loop wire. Since the second wire350is boned to the first bonding pad110on the first region A1of the first bonding pad110, the first wire250and the second wire350establish double bonding on the first region A1. The second wire350is bonded to the first bonding pad110at a region B1.

Referring again toFIG. 17B, a chip pad322of the second upper semiconductor chip320and a chip pad312of the second lower semiconductor chip310are connected by a second inter-chip wire360, and the chip pad312of the second lower semiconductor chip310and the first region A1of the first bonding pad110are connected by the second wire350. In the illustrated embodiment, the second wire350connecting the chip pad312of the second lower semiconductor chip310and the first region A1of the first bonding pad110is formed by reverse wiring. However, the formation of the second inter-chip wire360may start at any location. In addition, the second inter-chip wire360and the second wire350may be formed in any arbitrary order. For example, the first region A1of the first bonding pad110and the chip pad312of the second lower semiconductor chip310may first be connected by the second wire350, and the chip pad312of the second lower semiconductor chip310and chip pad322of the second upper semiconductor chip320may then be connected by the second inter-chip wire360.

Referring toFIG. 17C, a third semiconductor chip400may be stacked on the second semiconductor chip300. In a case where the third semiconductor chip400includes a third lower semiconductor chip410and a third upper semiconductor chip420, the third lower semiconductor chip410and the third upper semiconductor chip420may be sequentially stacked on the second upper semiconductor chip320.

A chip pad of the third semiconductor chip400and the second region A2of the first bonding pad110may be wired by a third wire450. The third wire450may be bonded to the first bonding pad110at the second region A2. Referring toFIG. 17C, a chip pad422of the third upper semiconductor chip420and a chip pad412of the first lower semiconductor chip410may be connected by a third inter-chip wire460, and the chip pad412of the third lower semiconductor chip410and a second region A2of the first bonding pad110may be connected by a third wire450. The third wire450and the third inter-chip wire460may be formed in any arbitrary order. For example, the chip pad422of the third upper semiconductor chip420and the chip pad412of the third lower semiconductor chip410may first be connected by the third inter-chip wire460, and the chip pad412of the third lower semiconductor chip410and the second region A2of the first bonding pad110may then by connected by the third wire450.

Referring toFIG. 17D, a fourth semiconductor chip500may be stacked on the third semiconductor chip400. In a case where the fourth semiconductor chip500includes a fourth lower semiconductor chip510and a fourth upper semiconductor chip520, the fourth lower semiconductor chip510and the fourth upper semiconductor chip520may be sequentially stacked on the third upper semiconductor chip420.

A chip pad of the fourth semiconductor chip500and the second region A2of the first bonding pad110may be wired by a fourth wire550. Since a reverse wiring method is used for wiring to form the fourth wire550, the third wire450and the fourth wire550establish double bonding on the first region A1.

Referring again toFIG. 17D, a chip pad522of the fourth semiconductor chip500and a chip pad512of the fourth lower semiconductor chip510are connected by a fourth inter-chip wire560, and the chip pad512of the fourth lower semiconductor chip510and the second region A2of the first bonding pad110are connected by the fourth wire550. In the illustrated embodiment, the second wire350connecting the chip pad312of the second lower semiconductor chip310and the first region A1of the first bonding pad110is formed by reverse wiring. However, the formation of the second inter-chip wire360may start at any location. In addition, the second inter-chip wire360and the second wire350may be formed in any arbitrary order. For example, the fourth inter-chip wire560may be formed after forming the fourth wire550.

By way of summary and review, according to example embodiments, a semiconductor package may include a plurality of semiconductor chips electrically connected to a bonding pad, such that wires of different semiconductor chips may be double bonded to the bonding pad. In other words, connection regions of the different wires on the bonding pad may at least partially overlap. Therefore, the area of the bonding pad contacted by the wires is reduced, so that the size of the semiconductor package may be reduced as well. In contrast, when each semiconductor chip of a conventional semiconductor package is connected by a separate wire to a different region of a bonding pad, a width of bonding pad may increase, thereby increasing the size of the semiconductor package is also increased.