Semiconductor device comprising a semiconductor chip stack and method for producing the same

A semiconductor device includes a semiconductor chip stack having at least one lower semiconductor chip as a base of the semiconductor chip stack, and at least one upper semiconductor chip. An insulating intermediate plate is arranged between the semiconductor chips. Connecting elements wire the semiconductor chips, the intermediate plate and external terminals to one another.

CROSS REFERENCE TO RELATED APPLICATIONS

This application claims priority under 35 U.S.C. §119 to Application No. DE 102007018914.3 filed on Apr. 19, 2007, entitled “Semiconductor Device Comprising a Semiconductor Chip Stack and Method for Producing the Same,” the entire contents of which are hereby incorporated by reference.

BACKGROUND

The invention relates to a semiconductor device comprising a semiconductor chip stack and a method for producing the same. Semiconductor devices of this type have at least one lower semiconductor chip as base of the semiconductor chip stack and at least one upper semiconductor chip. In this case, the semiconductor chips are stacked directly one on top of another. In the case of conventional stacking of this type it must be ensured that the individual potentials of the semiconductor chips are effectively insulated from one another during the stacking.

Electrical insulation, however, is detrimental to the thermal conductivity. Thus, by way of example, when a logic chip is fixed onto a transistor by means of an insulating adhesive, thermal conductivity is adversely affected. This is because an increased thermal resistance forms on the top side of the lower semiconductor chip, which forms the base, as a result of an upper stacked semiconductor chip being applied by adhesive bonding. In addition, the size of the upper semiconductor chip is disadvantageously limited with regard to its areal extent since it cannot project beyond the edge of the lower semiconductor chip without increasing the risk of the semiconductor chip stack breaking.

Furthermore as a result of semiconductor chips being adhesively bonded onto one another to form a semiconductor chip stack, a redistribution wiring between the electrodes of the semiconductor chips that are adhesively bonded onto one another, namely those on the top side of the lower semiconductor chip and those on the rear side of the upper semiconductor chip, is not possible without considerable outlay in terms of costs. Power semiconductor chips having electrodes on the top side and the rear side cannot therefore be stacked satisfactorily by means of adhesive bonding technology. In the case of semiconductor chips of this type it is only possible for electrodes that are of identical type and equal in area, that is to say congruent, to be adhesively bonded onto one another by means of a conductor adhesive, such that in circuitry terms only restricted functions can be realized by means of a stacking.

Moreover, it is possible, in the context of “wafer level packaging technology” to electrically connect two composite plates with corresponding embedded semiconductor chips and with wiring structures on coplanar top sides via through contacts in such a way that a semiconductor device comprising a semiconductor chip stack arises, the semiconductor chips of which are electrically wired to one another via vertical through contacts and horizontal wiring structures. Such stacking of semiconductor chips is not advantageous for stacking power semiconductor chips on account of the thermal insulation of the semiconductor chip stack, even though the wiring possibilities are improved.

Furthermore, it is possible to create multilayered ceramic substrates which can be equipped with semiconductor chips on both sides, such that the heat-loss-generating top sides of the semiconductor chips are uncovered on both sides of the substrate plate and can dissipate heat. However, this requires a substrate technology having a high material outlay.

Finally, it is also possible to provide semiconductor chips with a sequence of metallization and insulation layers on the areas with which they are intended to be connected, and then to adhesively bond them onto one another. Although this affords the possibility of complex wiring, the thermal effects are serious and not advantageous for power semiconductor devices.

In light of the foregoing, there is a need for improved semiconductor chip stack configurations.

SUMMARY

The invention relates to a semiconductor device comprising a semiconductor chip stack and a method for producing the same. The semiconductor device has a semiconductor chip stack having at least one lower semiconductor chip as a base of the semiconductor chip stack, and at least one upper semiconductor chip. An insulating intermediate plate is arranged between the semiconductor chips. Furthermore, the connecting elements electrically connect the semiconductor chips, the intermediate plate and external terminals of the semiconductor device to one another. In this case, the semiconductor device has surface-mountable external contacts on its underside.

DETAILED DESCRIPTION

FIG. 1shows a schematic cross section through a semiconductor device10of one embodiment of the invention. The semiconductor device10has a semiconductor chip stack1having at least one lower semiconductor chip2and an upper semiconductor chip3stacked thereon. An intermediate plate4is arranged between the semiconductor chips2and3, the intermediate plate having an electrically conductive coating5on its top side9.

The intermediate plate4can be a ceramic plate. Ceramic plates have the advantage that their thermal conductivity can be greater than the thermal conductivity of the stacked semiconductor chips2and3, such that, by means of a ceramic intermediate plate4, a heat loss that arises in the lower semiconductor chip2can be dissipated via the intermediate plate4and the upper semiconductor chip3. It is also possible to make the intermediate plate4larger than is permitted by the areal extent of the lower semiconductor chip2.

Moreover, it is possible for the intermediate plate4to be a plastic plate. Such a plastic plate as intermediate plate4can have a substance from the group polyimides, high-temperature thermoplastics, polybenzocyclobutene or polybenzoxazoles or mixtures thereof. Plastic plates of this type can be provided with a plating on one side, the plating constituting the conductive coating. The plating can also be patterned in order to provide both contact pads13for connecting elements6and contact pads14for the upper semiconductor chip3, for example. The conductive coating5is patterned in such a way that it forms a wiring structure24on the top side9of the intermediate plate4.

In this schematic cross section of the semiconductor device10the connecting elements6are bonding wires and connect for example the contact pads13on the top side9of the intermediate plate4to a contact area27on the top side28of the upper semiconductor chip3, which is fixed by its rear side29on a contact pad14of the wiring structure24on the top side9of the intermediate plate4.

The materials of the contact area14on the intermediate plate4for semiconductor chips3and the coating34on the rear side29of the upper semiconductor chip3can be coordinated with one another in such a way that a diffusion solder connection is possible. In the case of a diffusion solder connection of this type, in the course of diffusion soldering, intermetallic phases form which have a higher melting point than the melting point of the components of the diffusion solder. A solderable coating16on the top side15of the lower semiconductor chip2for fixing the intermediate plate4can also have a diffusion solder layer18, which reacts with a plating8on the underside31of the intermediate plate. The diffusion solder layer18both for the solderable coating16and for the contact pad14has the advantage that the stack1composed of semiconductor chips2and3and an intermediate plate4arranged in between has a high thermostability and therefore withstands, without being damaged, subsequent process temperatures in the course of the production of a semiconductor device10of this type. Diffusion solder layers18are used in the areas in which firstly the semiconductor chip stack1is realized and is then intended to be fixed as semiconductor chip stack1for example on a semiconductor device carrier22.

However, if a sequence of method steps that differs from this is provided, then it may be advantageous to provide a diffusion solder connection between a chip island21of the semiconductor device carrier22and the rear side32of the lower semiconductor chip2and then to apply the intermediate plate4and finally to apply the upper semiconductor chip3of the semiconductor chip stack1. In this case it is advantageous to provide the first solder layer17as diffusion solder layer18and to realize the second fixing between intermediate plate4and lower semiconductor chip2by means of a soft solder layer, and finally to embody the topmost fixing layer between stacked semiconductor chip3and intermediate plate4by means of a conductive adhesive, such that in the manufacturing sequence a temperature grading results for the cohesive connections and it is ensured that the solder and adhesive connections do not mutually damage one another during the manufacturing sequence.

In one form of implementation for producing a semiconductor device, therefore, a patterned thin ceramic or polymer plate provided with a plurality of mutually electrically isolated metallic regions for chip fixing and for connecting element fixing is applied to the top side15of the lower semiconductor chip2. In order to cohesively connect such an intermediate plate4by means of diffusion soldering or soft soldering, a solderable surface metallization composed, for example, of Ag, Au, Pd or PdAu is applied as the topmost layer to the top side of the lower semiconductor chip, while the underside of the ceramic or polymer plate has a metallic plating composed, for example, of Cu, Ag, Ni, or NiPdAu.

One or a plurality of upper semiconductor chips3can then be applied to the electrically insulating intermediate plate4based on ceramic or a polymer by means of conductive or insulating adhesive or a solder. In the case of a metallic solder connection, the top side of the ceramic or polymer intermediate plate then also likewise has a metallic coating composed of Cu, Ag, Ni, Pd or NiPdAu, for example. As a result, power semiconductor chips with vertical current flow, the chip rear side of which constitutes a drain terminal, for example, can also be electrically insulated from one another and applied one above another, thus resulting in a “chip stacking” or a “chip-on-chip” structure.

In addition, between the upper semiconductor chip3and the metallized regions of the wiring structure24on the insulation intermediate plate4and/or the lower semiconductor chip, electrical connections can be realized by means of metal wires, for example. Moreover, it is possible to provide a linking area for further upper semiconductor chips3on the lower semiconductor chip2, the linking area being significantly larger than the lower semiconductor chip2. The mounting area which is available for fitting stacked semiconductor chips3is thereby enlarged.

Various cohesive connections are possible between a chip island21of a semiconductor device carrier22and the rear side electrode38of the lower semiconductor chip2and also between the top side15of the lower semiconductor chip2and the intermediate plate4and also between the intermediate plate4and the upper semiconductor chip3. The designer of the semiconductor device can choose between a solder layer, a diffusion solder layer, an insulating adhesive layer and an electronically conductive adhesive layer, in order to achieve an optimum cohesive connection between the individual components of the semiconductor chip stack1within the semiconductor device10.

Furthermore, the surface-mountable external contacts are arranged on the underside of the semiconductor device10and embedded in a plastic housing composition apart from external contact areas as external terminals7. For this purpose, the external contacts are constructed from leads25of a leadframe and have a chip island21for the lower semiconductor chip2, wherein the chip island21and the leads25can merge into external terminals7.

FIGS. 2 to 9show schematic views of components of the semiconductor device10in accordance withFIG. 1during the production thereof.

FIG. 2shows a schematic cross section through an upper semiconductor chip3for a semiconductor chip stack. A semiconductor chip3of this type can be a power semiconductor device or an integrated circuit having control functions or a logic component and also a memory component. A semiconductor chip3of this type is produced from a semiconductor wafer, wherein a multiplicity of semiconductor chip positions are arranged in rows and columns on the semiconductor wafer.

A semiconductor chip3of this type is produced from a monocrystalline semiconductor material and has differently doped semiconductor zones which enable the actual switching, control, logic or memory function. The semiconductor zones are connected to contact areas27which are arranged on the top side28of the semiconductor chip3or are arranged as rear side electrode33on the rear side29of the upper semiconductor chip3.

FIG. 3shows a schematic cross section through a lower semiconductor chip2for a semiconductor chip stack. In this production method, withFIG. 3a lower semiconductor chip2composed of silicon was provided, the top side15and the rear side32of which have a larger areal extent than that of the semiconductor chip3to be stacked, which is illustrated inFIG. 2. The thickness of the semiconductor chip2used as base semiconductor chip for the semiconductor chip stack is also greater than the thickness of the upper semiconductor chip3as shown byFIG. 2.

On the top side15of the lower semiconductor chip2, contact areas27are arranged in the edge regions, the contact areas enabling a connection both to the upper semiconductor chip and to the external terminals of the semiconductor device with the inclusion of connecting elements. Power semiconductor devices can also be used as lower semiconductor chips2and as upper semiconductor chips. In order to connect the lower semiconductor chip2to the upper semiconductor chip, a metallization is provided on the top side15of the lower semiconductor chip2, which metallization can have for example metals for a diffusion solder layer18. Diffusion solder layers of this type have the advantage of a higher thermostability compared with soft solder layers or adhesive layers. The production of a semiconductor device according to the invention comprising a semiconductor chip stack requires not just the two semiconductor chips2and3but, as then shown byFIG. 4, a further intermediate plate4.

FIG. 4shows a schematic cross section through a blank26of an intermediate plate4. A blank26of this type can be produced from ceramic, for example, for which purpose firstly a green body is formed, which subsequently contracts in a burning process to form a sintered ceramic. Moreover, it is customary to saw such ceramic plates as intermediate plates4from a sintered ceramic block in order to be able to produce precise top sides9and rear sides31of the blanks26. In this case, the thickness of such a ceramic blank is approximately 0.5 mm.

Moreover, it is possible to produce such a blank26from a plastic, wherein as plastics a substance from the group polyimides, high-temperature thermoplastics, polybenzocyclobutene or polybenzoxazoles or mixtures thereof is used as material for the blank26of an intermediate plate4. The blank26is subsequently provided with electrically conductive layers.

FIG. 5shows a schematic cross section through an intermediate plate4after coating of the blank26fromFIG. 4. A wiring structure24was applied on the top side9of the blank26, which wiring structure emerged from a patterned plating. For this purpose, firstly an electroless chemical or electrolytic metal deposition is carried out. In an electrolytic metal deposition it is necessary for the surface of the ceramic plate to become conductive. For this purpose, an electrically conductive seed layer is applied for example by means of a sputtering method and the seed layer is subsequently contact-connected. In an electrolytic bath, a closed coating is then deposited, for example on the top side9of the intermediate plate4.

The closed coating can subsequently be patterned by means of photolithography technology involving the formation of a photoresist mask. Various methods are used for patterning, preferably wet-chemical etching or dry etching by means of a plasma. The photoresist mask is subsequently removed, which can be done with the aid of a plasma ashing or with the aid of a solvent. This patterning gives rise to a wiring structure24on the top side9of the blank26, which can subsequently be used either for fixing or cohesive connection to an upper semiconductor chip or for fitting of connecting elements. For this purpose, the wiring structure24shown has a contact pad13for connecting elements and a contact pad14for a semiconductor chip.

FIG. 6shows a schematic cross section through a semiconductor chip stack1having semiconductor chips2and3in accordance withFIGS. 2 and 3and the intermediate plate4in accordance withFIG. 5. The cohesive connections between the three components of the semiconductor chip stack1can be carried out in various ways; it is thus possible, by means of a solderable coating16composed of a diffusion solder material, to produce a diffusion solder layer18in interaction with the plating8, such that the cohesive connection between the lower semiconductor chip2and the intermediate plate4has high temperature stability.

A chip island in the form of a contact pad14for the upper semiconductor chip3can likewise have a solderable coating, wherein the coating preferably comprises a soft solder, such that the fixing between intermediate plate4and lower semiconductor chip2is not jeopardized upon application of the stacked semiconductor device3. Instead of a soft solder layer, this cohesive connection can also be effected by an insulating or by an electrically conductive adhesive layer19.

In principle, it is possible firstly to produce a thermostable semiconductor chip stack1with an intermediate plate4or, in another exemplary implementation of the method, to provide a semiconductor chip carrier having a chip island on which, one after another, firstly the lower semiconductor chip1, then the intermediate plate4and finally the upper semiconductor chip3are applied and thus stacked.

FIG. 7shows a schematic cross section through a semiconductor device position35on a semiconductor device carrier22, wherein the semiconductor device carrier22can have a multiplicity of such semiconductor device positions35. A central chip island21as external terminal7is arranged in the semiconductor device position35, the chip island being surrounded by leads25as external terminals7.

FIG. 8shows a schematic cross section through the semiconductor device carrier22in accordance withFIG. 7after application of a semiconductor chip stack1in accordance withFIG. 6. In this case, the entire semiconductor chip stack1, such as can be seen inFIG. 6, is either adhesively bonded by means of a conductive adhesive or soldered by means of soft solder onto the chip island21in order not to jeopardize the cohesive connections between the components of the semiconductor chip stack1. On the other hand, it is possible for the components of the semiconductor chip stack1to be applied successively on the chip island21. In this case, the solder layer17can also be a diffusion solder layer in order to create a thermostable cohesive connection which extends, without being damaged, the further process steps such as soldering and adhesive bonding of the components to form a semiconductor chip stack1.

FIG. 9shows a schematic cross section through the semiconductor device carrier22in accordance withFIG. 8after fitting of connecting elements6. The arrangement of the connecting elements6is purely schematic and not restricted to the cross section shown. The connecting elements6shown are merely intended to demonstrate what possibilities for the electrical connections between the external terminals7and the individual levels of the semiconductor chip stack1are possible.

Thus, contact areas27on the top side28of the upper semiconductor chip3can be connected to the upper wiring structure24on the intermediate plate4and, furthermore, contact pads13of the wiring structure24of the intermediate plate4can be connected via corresponding connecting elements6to contact areas27in edge regions of the lower semiconductor chip2. It is also possible to connect the upper semiconductor chip3directly to external terminals7in the form of leads25and/or to electrically connect contact areas27of the lower semiconductor chip2to the corresponding leads25as external terminals7. The contact areas27of the upper semiconductor chip3and of the lower semiconductor chip2can also be connected to one another via connecting elements6.

After completion of the connections via connecting elements6, the semiconductor device carrier22with the semiconductor chip stack1and the connecting elements6can be embedded into a plastic housing composition, from which project, whilst leaving them free, the external terminals7as surface-mountable external contacts on the underside of the semiconductor device10, as shown byFIG. 1.

FIG. 10shows a schematic cross section through a semiconductor device20of a further embodiment of the invention. Components having the same functions as in the previous figures are identified by the same reference symbols and are not discussed separately.

In this embodiment of the invention in accordance withFIG. 10, adhesive connections are predominant as cohesive connection between the semiconductor device carrier and the semiconductor chip stack1and also within the semiconductor chip stack1. For this purpose, the upper semiconductor chip3is applied by means of a connecting paste, which can be electrically conductive or insulating, onto a ceramic plate metallized with copper on both sides as intermediate plate4, which can also be coated with nickel or with nickel alloys, wherein the intermediate plate4is in turn applied to the top side of the lower semiconductor chip2by means of a connecting paste.

The difference with respect to the embodiment shown inFIG. 1is that here power semiconductor chips are stacked one on top of another. A further difference consists in the fact that the intermediate plate4has a larger areal extent than that of the lower semiconductor chip2, such that also larger upper semiconductor chips3or semiconductor chips3of the same size can be stacked on the intermediate plate4. Moreover, the copper plate coated on both sides is not only formed as wiring structure24on the top side9, but is also patterned on the rear side31, such that it can be connected to correspondingly adapted electrodes of the lower semiconductor device2such as a source electrode S2and a gate electrode G2. The rear side32of the lower semiconductor chip2constitutes a drain electrode D2, which can be externally contact-connected via the chip island21of the semiconductor device carrier22as drain electrode D1. The stacked semiconductor chip3likewise has a drain electrode D3on its rear side29and a source electrode S3and a gate electrode G3on its top side28. The gate electrode G2of the lower semiconductor chip2and the gate electrode G3of the upper semiconductor chip3are electrically connected to one another via the intermediate plate4and its wiring structures24.

In this embodiment of the invention, the edge sides of the intermediate plate have conductor tracks, or through contacts are provided through the intermediate plate4. In this embodiment, the two gate electrodes G2and G3are driven by a common gate terminal G1of the semiconductor device. However, it is also possible for the two semiconductor chips to be driven separately if corresponding connecting elements6are provided. The two source electrodes S3and S2are also routed together to an outer source electrode S1of the semiconductor device20. Only the drain electrodes D2and D3can be accessed separately. For this purpose, the connecting lines between D3and an external terminal do not lie in the cross-sectional plane shown here.

FIG. 11shows a schematic cross section through a semiconductor chip stack1of a semiconductor device30of a further embodiment of the invention. Components having the same functions as in the previous figures are identified by the same reference symbols and are not discussed separately.

In this further embodiment of the invention, the semiconductor device30has two upper semiconductor chips11and12on the intermediate plate4, the semiconductor chips being fixed alongside one another and fulfilling various logic or memory functions.

For this purpose, the upper semiconductor chips11and12have a plurality of contact areas27on their top sides28, which contact areas can be wired variously via connecting elements. An intermediate plate4is arranged onto the top side of the lower semiconductor chip2by means of a solder layer, which presupposes a solderable metallization of the top side, such as e.g. a coating composed of AgAu or PdAu as topmost coating on the lower semiconductor chip in order to fix the thin intermediate plate having a thickness of less than 0.5 mm. In this case, the thin intermediate plate can comprise an insulating material which is coated on both sides with copper or with nickel or with alloys thereof, as is indicated for “DCB” plates (direct copper bonding). The two upper semiconductor chips11and12illustrated here are fixed thereon by means of a solder layer.

FIG. 12shows a schematic cross section through the semiconductor chip stack1in accordance withFIG. 11after fitting of connecting elements6. In this illustration, too, the connecting elements6depicted are merely intended to show what possibilities exist, in principle, for electrically connecting the individual levels of the semiconductor chip stack1among one another and/or to external terminals7or leads25. In this case, the semiconductor chip island21as external terminal7has a larger metal thickness than the leads25, provision being made for the leads25to project laterally from a plastic housing, while the underside36of the chip island21as cooling area and external terminal7projects from the plastic housing as surface-mountable external contact.

FIG. 13shows a schematic cross section through a semiconductor device40in accordance with a further embodiment of the invention. Components having the same functions as in the previous figures are identified by the same reference symbols and are not discussed separately.

In this case, in a manner similar to that in the case of the semiconductor device20in accordance withFIG. 10, power semiconductor chips are stacked one above another, wherein the intermediate plate4has a larger areal extent than that of the lower semiconductor chip2. Here as well the intermediate plate4is provided with wiring structures24on both sides. Two power semiconductor chips11and12are arranged on the top side9of the intermediate plate4, the power semiconductor chips in each case having a source electrode S3and a gate electrode G3on their top sides28.

The rear sides29of the upper semiconductor chips11and12are fixed on corresponding contact pads14of the wiring structure24of the intermediate plate4as drain electrodes D3. Once again two electrodes, namely a source electrode S2and a gate electrode G2, are arranged on the top side15of the lower semiconductor chip2, which electrodes are electrically connected to the electrodes of the upper semiconductor chips11and12via corresponding conductor tracks of the lower wiring structure24of the intermediate plate4. The high-current-carrying connecting elements37for the upper semiconductor chips11and12are embodied as bonding tapes which are bonded multiply on the source electrodes S3.