Semiconductor device having a diode type electrical fuse (e-fuse) cell array

A semiconductor device includes a first word line configured to perform a writing operation or a programing operation, a second word line configured to perform a read operation, a first switching device including a first gate electrode and a first node, a second switching device comprising a second gate electrode and a second node, an electrical fuse (e-fuse) disposed between the first node and the second node, and a diode coupled to the first node and the first word line, wherein the first gate electrode and the second gate electrode are coupled to the second word line.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims the benefit under 35 U.S.C. 119(a) of Korean Patent Application No. 10-2019-0135398 filed on Oct. 29, 2019 in the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference for all purposes.

BACKGROUND

The following description relates to an electrical-fuse (e-fuse) cell. The following description also relates to a nonvolatile memory device provided with such an e-fuse cell.

2. Description of Related Art

Typically, power integrated circuits (ICs) such as Power Management IC (PMIC) devices may require a small capacity of using nonvolatile One Time Programmable (OTP) memory to perform analog trimming functions. However, typical OTP memories, using an E-Memory or transistor as a nonvolatile memory, may present issues of a complicated driving method, a low reliability and a large area.

Therefore, for the nonvolatile OTP memory, an electrical-fuse One-Time Programmable (e-fuse OTP) memory having a simple driving method and a small area may be used in typical examples. Such an e-fuse type memory may be programmed by opening an e-fuse by blowing the e-fuse using an overcurrent of about 10 mA to 30 mA in a polysilicon fuse or a metal fuse, which are examples of fuses used as the e-fuse. The resistance before the program operation is about 50-100Ω, and as the program current flows through the e-fuse, e-fuse resistance after the program is more than such a few tens of Ωs of resistance.

In order to blow such an e-fuse, as noted above, a program current of 10 to 30 mA may be required, and a metal-oxide-semiconductor (MOS) transistor having a channel width of a predetermined value or more may be required to flow such a program current of a predetermined value or more, thereby increasing the area of the e-fuse memory cell.

Not being able to reduce the area of a memory device, as described above, means the size of the memory device may not readily be reduced, which may be an issue in designing a miniaturized memory device.

SUMMARY

In one general aspect, a semiconductor device, includes a first word line configured to perform a writing operation or a programing operation, a second word line configured to perform a read operation, a first switching device including a first gate electrode and a first node, a second switching device including a second gate electrode and a second node, an electrical fuse (e-fuse) disposed between the first node and the second node, and a diode coupled to the first node and the first word line, wherein the first gate electrode and the second gate electrode are coupled to the second word line.

The semiconductor device may further include a first bit line coupled to the second node and a third switching device, wherein the first switching device and the second switching device each may include an N-type metal-oxide-semiconductor (NMOS) transistor, and the third switching device may include a P-type metal-oxide-semiconductor (PMOS) transistor.

A program current may pass through the first bit line, the second node, the e-fuse, the first node, the diode and the first word line, in order.

A read current may pass through the first switching device, the first node, the e-fuse, the second node and the second switching device, in order.

A current path for the programing operation in the e-fuse may have a direction opposite to a direction for a current path for the read operation in the e-fuse.

The semiconductor device may further include a program current controller configured to provide a program voltage to a selected e-fuse cell for the program operation, a read current control controller configured to provide a read voltage to the selected e-fuse cell for the read operation, a reference voltage generator configured to generate a reference voltage, and a sensor, including a sense amplifier, configured to sense whether the selected e-fuse cell is programmed or not.

The read current controller may include a read current switching device and a read current resistor connected in series.

The reference voltage generator may include first, second and third reference switching devices, and first and second reference resistors, wherein each of the read current switching device and the first reference switching device may include a P-type metal-oxide-semiconductor (PMOS) transistor.

In another general aspect, a semiconductor device includes an e-fuse formed on an insulation layer, a first switching device formed on a first well region, a diode formed on a second well region having a opposite conductivity type to a conductivity type of the first well region, and a second switching device formed on a third well region having a same conductivity type as the conductivity type of the first well region.

The semiconductor device may further include a guard ring that may enclose the first switching device, the diode, the e-fuse and the second switching device.

The first switching device and the second switching device may be n-type metal-oxide-semiconductor (NMOS) transistors.

The semiconductor device may further include a first contact plug formed on the first switching device, a second contact plug formed on the diode, a third contact plug and a fourth contact plug formed on the e-fuse, and a fifth contact plug formed on the second switching device.

The semiconductor device may further include a first metal interconnection connecting the first contact plug, the second contact plug and the third contact plug, and a second metal interconnection connecting the fourth contact plug and the fifth contact plug.

In another general aspect, a semiconductor device includes an e-fuse formed on an insulation layer, a first switching device formed on a first well region, a diode formed on a second well region, and a second switching device formed on a third well region.

The second well region may have an opposite conductivity type to a conductivity type of the first well region.

The third well region may have a same conductivity type as a conductivity type of the first well region.

The semiconductor device may further include a guard ring that encloses the first switching device, the diode, the e-fuse and the second switching device.

The first switching device and the second switching device may be n-type metal-oxide-semiconductor (NMOS) transistors.

DETAILED DESCRIPTION

Expressions such as “first conductivity type” and “second conductivity type” as used herein may refer to opposite conductivity types such as N and P conductivity types, and examples described herein using such expressions encompass complementary examples as well. For example, an example in which a first conductivity type is N and a second conductivity type is P encompasses an example in which the first conductivity type is P and the second conductivity type is N.

One or more examples may provide an e-fuse cell capable of operating stably with a lower current, while reducing the area compared to the related art by improving the arrangement of circuit devices constituting the e-fuse cell, and a nonvolatile memory device provided with such an e-fuse cell.

Also, one or more examples may provide a nonvolatile memory device having an e-fuse cell that reduces the area of a memory device by arranging the devices of the e-fuse cell appropriately, and the nonvolatile memory device may have a different current flow used for a program mode and a read mode operation for storing and reading data, thereby allowing for stable operation with a lower current. The following description is described below based on examples illustrated in drawings.

Accordingly, the following examples may provide for an e-fuse cell that may reduce the area of a memory cell by more appropriately arranging the devices constituting the e-fuse cell, and a nonvolatile device having such an e-fuse cell.

Such one or more examples are made possible by using a diode as a program selection device instead of a typical transistor device, and thus, even if the junction area is small, it may be possible to flow a current of a predetermined magnitude or more while still being able to reduce the area of the e-fuse cell.

In another aspect, the following description may provide for a nonvolatile memory device that has a different current path in the program mode and read mode operation, so as to be able to operate stably with a lower voltage so as to be able to operate at a lower current, accordingly.

FIG. 1illustrates a block diagram of a nonvolatile memory device having an e-fuse cell array, according to an example.

As shown in the example ofFIG. 1, a semiconductor device according to an example may include a nonvolatile memory (NVM) device10. The nonvolatile memory (NVM) device may include a control logic20, a word line (WL) driver40, a programming driver50, an e-fuse cell array60, as a non-limiting example, though other elements may be present in addition to or instead of these enumerated elements. The control logic20may supply an internal control signal suitable for the program mode or the read mode, according to the control signal. The control logic20may supply a control signal into a word line (WL) driver40and a programming driver50. The control logic20may also supply a control signal into the sense amplifier70, which may also be a sensor70or be a part of a sensor70. The word line (WL) driver40may include the word line selector, and may activate a write or programming word line (WWL) or a read word line (RWL), accordingly. The programming driver50may include the bit line selector, and supplies a programming current that is controlled by WSEL pins. The e-fuse cell array60may include a plurality of e-fuse unit cells100. The sense amplifier (BL S/A)70may detect the digital data coming from the bit line (BL), and the data may be output through the OUTPUT (DOUT).

Further, RE, WREN and PEB ports denote Read Enable, Write Enable and Programming Enable, respectively. An ADD port may provide for address selection in the word line (WL) driver40to activate the write or programming word line (WWL) or the read word line (RWL). The WSEL port may provide for a programming current control in the programming driver50in order to supply the programming current. VDD and VSS ports may supply external supply power and ground voltage, respectively.

Although the cell array form or the capacity of the e-fuse cell array60may not be particularly limited to the particular one or more examples, one or more example are described with respect to an example of a predetermined capacity, arranged in 128 rows×16 columns. In such an example, the one row may correspond to one of write word lines (WWL) for a writing operation, and to one of read word lines (RWL) for a read operation. For example, there may be a one-to-one correspondence between the WWL and the RWL. For example, the e-fuse cell array60may include 128 word lines and 16 bit lines. Thus, a total of 2048 bits may be included in the e-fuse cell array60, such that a total of 2048 e-fuse unit cells may be arranged in the e-fuse cell array60. In such an example, the word line selector and the bit line selector are required to perform programming of the e-fuse unit cells. One of the 128 word lines and one of the 16 bit lines are serially selected through row decoding and column decoding. Thus, the e-fuse unit cell structure100is to be sequentially selected and operated.

FIG. 2illustrates an e-fuse unit cell layout disposed in the e-fuse cell array, according to an example.

As illustrated in the example ofFIG. 2, the e-fuse unit cell structure100may include a first switching device110, a diode120, a second switching device130and an e-fuse140, as a non-limiting example, though other elements may be present in addition to or instead of these enumerated elements. The e-fuse140may be disposed to be adjacent to the second switching device130rather than the first switching device110. The diode120may be located in a center region of the e-fuse unit cell structure100. The guard ring150may be formed so as to enclose the first switching device110, the diode120, the second switching device130and the e-fuse140. The two switching devices110and130may be n-type metal-oxide-semiconductor (NMOS) transistors or NMOS metal-oxide-semiconductor field effect transistors (MOSFETs). The cross-sections of each device are illustrated in the examples ofFIGS. 6-10. The e-fuse unit cell structure100may be disposed side-by-side repeatedly, to make total 2048 e-fuse unit cells to be arranged in the e-fuse cell array60.

FIG. 3is a circuit diagram illustrating a connection structure of devices disposed in the e-fuse unit cell structure100.

According to the example ofFIG. 3, the e-fuse unit cell structure100may include a first word line240A used for a writing operation or a programing operation, a second word line240B used for a read operation, a first switching device110having a first gate electrode and a first node N1, a second switching device130having a second gate electrode and a second node N2, an electrical fuse (e-fuse)140disposed between the first node N1and the second node N2, a diode120coupled to the first node N1and the first word line240A, and a first bit line220A coupled to the second node N2, as a non-limiting example, though other elements may be present in addition to or instead of these enumerated elements. The first gate electrode and the second gate electrode may be coupled to the second word line240B. The first bit line220A may be coupled to a third switching device210disposed in a program current control unit or program current controller200. The first switching device110and the second switching device130may be NMOS transistors and the third switching device210may be a p-type metal-oxide-semiconductor (PMOS) transistor, according to an example. The first node N1may be disposed between the first switching device110and the e-fuse140. The second node N2may be disposed between the second switching device130and the e-fuse140.

According to the example ofFIG. 3, the first switching device110and the second switching device130may be connected in series. The first switching device110may have a first source terminal, a first drain terminal and a first gate terminal, according to a non-limiting example. The first source terminal of the first switching device110near to the first node N1may be connected to a cathode of the e-fuse140.

The second switching device130may have a second source terminal, a second drain terminal and a second gate terminal, according to a non-limiting example. The second drain terminal near to the second node N2may be connected to an anode of the e-fuse140. A second source terminal may be connected to a ground terminal.

According to the example ofFIG. 3, the e-fuse140may have a cathode C and an anode A, and the e-fuse140may be configured to be programmed by applying a programming current. The e-fuse140is disposed between the first switching device110and the second switching device130, wherein the e-fuse comprises the anode or P terminal and the cathode or N terminal. The cathode or N terminal may be connected to the first source terminal of the first switching device110through the first node N1. The anode or P terminal of the e-fuse140may be connected to the second drain terminal of the second switching device130through the second node N2.

According to the example ofFIG. 3, the diode120may include an anode or P terminal and a cathode or N terminal. The diode120may be disposed between the first node N1and the first word line240A. The anode of the diode120may be connected to the first node N1. The cathode of the diode120may be connected to the first word line240A or write word line WWL, which is connected to the word line (WL) driver40, and finally to the control logic20.

As shown in the example ofFIG. 3, a dashed line may denote a program current path for the e-fuse unit cell structure100. The bit line220may supply the program current, and the e-fuse140may be programmed by the program current. The program current may thus flow out from the bit line and the e-fuse, through the diode120and write word line WWL. In such an example, the program current may flow from the anode of the e-fuse140into the cathode of the e-fuse140.

According to the example ofFIG. 3, a dash and dot line, including dashes separated by dots, may represent a read current path from the first switching transistor110to the second switching transistor130. Accordingly, such a read current path may pass through the first switching transistor110, the e-fuse140and the second switching transistor130, as shown in the example ofFIG. 3. In such an example, the read current may flow through the cathode of the e-fuse140into the anode of the e-fuse140, which has an opposite current flow compared to the program current path. No read current may pass through the diode120, so a high driving voltage may not be used. Therefore, using a read current with a low driving current may be possible. The read current may check whether the e-fuse is programmed or not. The voltage conditions are described in greater detail in another section of the present disclosure.

FIG. 4illustrates a circuit diagram illustrating a program operation of a nonvolatile memory device, according to an example.

According to the example ofFIG. 4, a programmable e-fuse cell array60may include a plurality of word lines240A,240B,240C,240D,240E and240F, and a plurality of bit lines220A and220B, as a non-limiting example. However, other examples may use a different number of word lines and/or bit lines. A first diode120may be coupled to the first word line240A, and a first e-fuse140may be coupled to the first bit line220A. A second diode120′ may also be coupled to the first word line240A, and a second e-fuse140′ is coupled to a second bit line220B. Another diode below the first diode120may also be coupled to second word line240C, and another e-fuse below the second e-fuse140′ may also be coupled to the second bit line220B. One of the write word lines240A,240C and240E may be selectively activated by the word line selector disposed in the WL driver40. One of the bit lines220A and220B may be selectively activated by the bit line selector disposed in the PD driver50.

According to the example ofFIG. 4, the e-fuse cell array60may further include a program current controller200having the third switching device210. The program current controller200may control a programming current used to program the e-fuse140. The programming current may be provided into the e-fuse by turning on the third switching device210. For example, a PMOS transistor may be used for the third switching device210. The third switching transistor210may include a third source terminal, a third drain terminal and a third gate terminal, according to a non-limiting example.

According to the example ofFIG. 4, the first e-fuse unit cell100may be electrically isolated from the neighboring second e-fuse unit cell100′ by an trench isolation region160or another field oxide, which may reduce a leakage current otherwise occurring between the e-fuse unit cells100and100′. The first e-fuse unit cell100and the second e-fuse unit cell100′ may be disposed in a first well region and a second well region, respectively, wherein the first well region may be isolated from the second well region by the trench isolation region160. The e-fuse140may be a polysilicon fuse, also referred to as poly fuse, including a silicide layer formed on the poly-Si layer, where the silicide layer is selected from one of cobalt silicide, nickel silicide or titanium silicide, as non-limiting examples. A resistance of the e-fuse may be changed by the programming current. For example, a resistance of the e-fuse may have a resistance value of approximately 300Ω or less before a writing or programming operation, and may have a resistance value of approximately 3 kΩ or more after the writing or programming operation. A silicide layer may be rearranged, such as to have a migration on the poly-Si layer due to the applied programming current, and then the poly-Si's resistance may increase up to 3 kΩ because the silicide layer is moved to a local area in the poly-Si layer.

FIG. 4shows a program operation of the nonvolatile memory device10. The first e-fuse unit cell100may be selected for programing operation through a selection signal provided from the control logic20. Then, the third switching device210may be turned on, and the first switching device110and the second switching device130may be turned off. As the third switching device210is turned on, a program voltage may be applied to the first bit line220A, the program voltage approximately ranging from 3V to 8V. The first bit line220A may be connected to the second node N2. During the program operation of the nonvolatile memory device10, a program voltage may be selectively provided to the e-fuse unit cell structure100through the first bit line220. The first bit line220may be selected through column decoding, in such an example. A program current may flow through the third switching device210, the first bit line220A, the first e-fuse140, and the first diode120. Accordingly, a high current may flow through the e-fuse140so that information is programmed. The programmed e-fuse140may have a high resistance of approximately 3 kΩ or more.

If the second e-fuse unit cell100′ is unselected during the programing operation, the second diode120′ in the unselected e-fuse unit cell100′ may serve as a protection device when the cell100′ is not being written. For example, a voltage of 5V may be applied to write the first bit line220A, and a voltage of 1V may be applied to write a second bit line220B. The second diode120′ in the second e-fuse unit cell100′ may block a current flowing from the shared first word line240A through the first e-fuse unit cell100. The unselected second e-fuse cell100′ may be therefore protected.

FIG. 5is a circuit diagram illustrating a read operation of the nonvolatile memory device10, according to an example.

According to the example ofFIG. 5, the sense amplifier70may compare a voltage applied to the e-fuse140with the reference voltage provided by the reference voltage generator400, and may output the difference. According to the output value of the difference, if the voltage through the e-fuse140is smaller than the reference voltage generated by the reference voltage generator400, it may be judged that the selected e-fuse140is not programmed, and in the opposite case, the selected e-fuse140may be judged as being programmed. Because the diode120is not used for the current path during the read operation of the present example, it is not illustrated in the example ofFIG. 5.

In greater detail, the control logic20may select the first e-fuse unit cell structure100to perform a read operation, and may provide a selection signal to the selected e-fuse unit cell structure100. Then, the first switching device110, the second switching device130and the read current switching device310may be turned on, accordingly. After that, the word line (WL) driver40may drive the read current control unit or read current controller300by providing a read voltage to generate a reference voltage. Accordingly, the switching devices310,410,420, and430may be turned on.

According to the example ofFIG. 5, a read current control unit300may provide a read voltage to the selected e-fuse unit cell100for a read operation. That is, during the read operation of the nonvolatile memory device10, a read voltage may be provided to the selected e-fuse unit cell100. The read current control unit300may include a read current switching device310and a read current resistor320formed by using a non-silicided poly-Si layer, according to a non-limiting example. In such an example, the read voltage may ranges from 1-6V. As the read current switching device310is turned on, the read current may flow through the read current switching device310, the read current resistor320, the first switching device110, the e-fuse140, and the second switching device130.

The read current may also flow through the first reference switching device410, the first reference resistor440, and the second reference switching device420, the second reference resistor450, and the third reference switching device430. In such an example, the first and second reference resistors440and450may correspond to the read current resistor320and the e-fuse140, respectively. The first, second and third reference switching devices410,420and430may correspond to the read current switching device310, the first switching device110and the second switching device130, respectively. The first reference switching device410and the corresponding read current switching device310may be PMOS devices, such as to minimize mismatching characteristics otherwise occurring during the reading operation. The second and third reference switching devices420and430and the corresponding first and second switching devices110and130may be NMOS transistors to minimize mismatching characteristics otherwise occurring during the reading operation. The reference voltage generator400may have the three switching devices410,420and430and two reference resistors440and450. The e-fuse unit cell100and the read current control unit300may also include the three switching devices110,130and310and two resistors140and320. As a result of using these approaches in examples, mismatching characteristics may be minimized during the reading operation.

Further, if the e-fuse140is un-programmed, the e-fuse140may show a lower resistance value than the first to second reference resistors440and450, so that a voltage measured at the e-fuse140may be lower than the reference voltage generated by the reference voltage generator400.

Conversely, if the e-fuse140is programmed, the e-fuse140may show a higher resistance value than a reference resistance, and thus a voltage measured at the e-fuse140may be higher than the reference voltage. Accordingly, the sense amplifier70may determine whether the e-fuse140is programmed by comparing the voltage of the e-fuse with the reference voltage.

According to the example ofFIG. 5, the read current switching device310may be a P-channel MOS transistor. The read current resistor320may have a predetermined first resistance value. In addition, one end of the read current resistor320may be connected to a fourth drain terminal of the read current switching device310. The other end of the read current resistor320may be commonly connected to each of the drain terminals of the first switching device110in the e-fuse unit cell structure100, through the bit line220A. The other end of the read current resistor320may also be connected to the bit line sense amplifier70. The first resistance value of the read current resistor320may have an intermediate value about 1600Ω between an un-programmed resistance value, that is, 300Ω or less, and a minimum resistance value, that is, 3000Ω when programmed.

According to the example ofFIG. 5, the reference voltage generator400may provide a reference voltage to the bit line sense amplifier70. The reference voltage generator400may include three switching devices410,420and430and two reference resistors440and450formed by using a non-silicided poly-Si layer. The reference voltage generator400may divide the read voltage using a plurality of resistors connected in series, and may generate the divided voltage as a reference voltage. The three switching devices410,420and430may be connected in series. The second reference resistor440may be connected between the first reference switching device410and the second reference switching device420, and the second reference resistor450may be connected between the second reference switching device420and the third reference switching device430.

According to the example ofFIG. 5, the first reference switching device410may be a PMOS device. With respect to the first reference switching device410, its source terminal may receive the read voltage, its gate terminal may receive the inverted read control signal and its drain terminal may be connected to one end of the first reference resistor440to selectively provide a read voltage to the first reference resistor440. The second reference switching device420may selectively connect the first reference resistor440and the second reference resistor450. That is, the second reference switching device420may be an NMOS having a drain terminal commonly connected to the first reference resistor440and the sense amplifier70, a gate terminal inputted with a read control signal, and a source terminal connected to a second reference resistor450. The third reference switching device430may be an NMOS whose drain terminal is connected to the second reference resistor450, a gate terminal receives a read control signal, and a source terminal is grounded, such that current flows through the first reference resistor440and the second reference resistor450due to the read voltage.

According to the example ofFIG. 5, two resistors provided in the reference voltage generator400, that is, the first reference resistor440and the second reference resistor450, may each have a predetermined resistance value, respectively. Each resistance value may have an intermediate value, for example, 1500 to 5000Ω between the resistance value as not programmed, for example, about 50-200Ω and the minimum resistance value when programmed, for example, about 3000-10000Ω, of the e-fuse140.

FIG. 6is a cross-sectional view of the first switching device110taken along line I-I′ in the e-fuse unit cell structure100illustrated in the example ofFIG. 2.

A P-type well region (PW)111may be formed in a semiconductor substrate. A first switching gate insulating layer101and a dummy gate insulating layer103may be formed on the semiconductor substrate The first switching gate electrode113and the dummy gate electrode112may be formed on the first switching gate insulating layer101and the dummy gate insulating layer103, respectively. The floating region115a, the dummy gate electrode112, and first switching N+ drain region114may be required for a read margin test. For the read margin test, a NMOS transistor may be further required to be in a reference voltage path. To match the NMOS transistor, the NMOS dummy gate electrode113with the floating region115amay be added to the first switching device110. In one or more non-limiting examples, such elements may be added in parallel or removed. The adding of the NMOS dummy gate electrode113with the floating region115amay be optional, in that one or more examples add the NMOS dummy gate electrode113with the floating region115a, but one or more other examples omit this element.

Spacers may be formed on the sidewalls of the first switching gate electrode113and the dummy gate electrode112. The dummy gate electrode112and the first switching gate electrode113may be doped by using N-type dopants. A first switching N+ drain region114may be formed in the P-type well region (PW)111between the dummy gate electrode112and the first switching gate electrode113. The floating region115aand the first switching N+ drain region114may be formed in the P-type well regions111at both sides of the dummy gate electrode112. The first switching N+ source region115b, the first switching N+ drain region114, and the floating region115amay all have the same conductivity type and the same doping concentration and the same depth as each other, because all of these regions may be formed in the same processing step with the same dopant condition. The first switching N+ drain region114may be connected to the sense amplifier70for performing a read operation. The floating region115amay not be connected to any potential, so the floating region115amay remain in a floating state. However, the first switching source region115bmay be connected to the first node N1. In such an example, the first switching N+ drain region114and the first switching gate electrode113may become parts that form a read current path during a read operation. In the present discussion, the use of “N+” refers to highly doped N-type dopants. “P+” refers to highly doped P-type dopants.

Further, a P+ guard ring150may be formed in the P-type well region111and may be spaced apart from the first switching N+ source region115aand the first switching N+ source region115bby a first isolation structure160. The P+ guard ring150may electrically isolate the first switching device110from the other devices. In addition, the trench-type first isolation structure160adjacent to the guard ring150may be formed, in one or more non-limiting examples. Further, there may be many contact plugs161,162,163and metal interconnections171,172,173. The guard ring150may be connected to the contact plug161and the metal line171. The N+ drain region114may be connected to the contact plug162and metal line172. The source region115bmay be connected to another contact plug163and another metal line173. In such an example, the metal line173may indicate the first node N1as shown in the example ofFIG. 3.

FIGS. 7A and 7Bare cross-sectional views of the diode structure120taken along the line II-II′ in the e-fuse cell illustrated inFIG. 2, according to an example.

As illustrated in the example ofFIG. 7A, an N-type well (NW) region121may be formed in a semiconductor substrate. An N+ cathode122and a P+ anode123may be formed in the N-type well region (NW)121. The NW121may be isolated from the P-type well region (PW)111by a trench isolation region160. The trench isolation region160may surround the N-type well region (NW)121. A P+ guard ring150may also be formed in the P-type well region (PW)111, in one or more examples. Further, silicide layers152may also be formed on the N+ cathode and the P+ anode. Contact plugs164,165may be formed on the silicide layers152, and metal interconnections174,175may be formed to couple the contact plugs164and165to each other. The N+ cathode122may be connected to the contact plug164and the metal line174. The P+ anode123may be connected to the contact plug165and metal line175.

FIG. 7Bis a cross-sectional view of a diode120of another example. A P+ anode123may be formed in an N-type well region121, and the first isolation structure160may enclose the P+ anode123. An N+ cathode122may be formed to be adjacent to the isolation structure160. Unlike the example ofFIG. 7A, the diode120of the example ofFIG. 7Bmay have an isolation structure160formed between the P+ anode123and the N+ cathode122. Because of the presence of the isolation structure16, the N+ cathode122and the P+ cathode region123may be effectively isolated from each other, thereby reducing the size of the overall device. If a diode is configured without the isolation structure160, as in the example ofFIG. 7A, the size of the overall device may be much larger, to improve the junction breakdown voltage as in the example ofFIG. 7B. In the same manner, as explained in the example ofFIG. 7A, there may also be silicide layers152, contact plugs, and metal lines, as shown in the example ofFIG. 7B.

FIG. 8is a cross-sectional view taken along line III-III′ of the second switching device130and the e-fuse140provided in the e-fuse unit cell structure100, as illustrated in the example ofFIG. 2.

According to the example ofFIG. 8, the second switching device130and the e-fuse140may be formed together in the P-type well region111. InFIG. 8, the left side of the drawing is the second switching device130and the right side is the e-fuse140. In the second switching device130, a second switching gate electrode131may be formed on a second gate insulating layer102. A second spacer may be formed on sidewalls of the second switching gate electrode131. The second switching N+ source region132and the second switching second switching N+ drain region133may formed in the P-type well region111, on both sides of the second switching gate electrode131. The second switching N+ source region132may be grounded, and the second switching second switching N+ drain region133may be connected to the anode of the e-fuse140. The second switching second switching N+ drain region133is connected to the third switching device210, together with the anode of the e-fuse140. The P+ guard ring150may be formed to be spaced apart from the second switching N+ source region132. The trench-type isolation structure160may be formed between the guard ring150and the second switching N+ source region132.

According to the example ofFIG. 8, the e-fuse140may use a poly-fuse including a silicide layer144, formed on the pol-Si material142. The silicide layer144may selected from one of cobalt silicide, nickel silicide or titanium silicide, as non-limiting examples, but other silicide materials may be used for the silicide layer144in other examples. The e-fuse140formed adjacent to the second switching device130may have an anode contact plug168and a cathode contact plug169. Each of the anode contact plug168and the cathode contact plug169may be formed by using a metal layer, such as tungsten metal, as a non-limiting example, which may be electrically coupled to both of the poly-Si layer142and the silicide layer144. Thus, the anode contact plug168and the cathode contact plug169may be connected to metal layers, or metal lines or metal interconnections,177and179, respectively, which may be selected from one of the materials of aluminum-copper (Al—Cu), tungsten (W), or copper (Cu), and so on, as non-limiting examples. The metal line177may connect between the anode contact plug168of the e-fuse140and second switching contact plug167of the second switching device130. Thus, the e-fuse140may be electrically connected to the second switching130by the metal line177. In such an example, the metal line177may indicate the second node N2, as shown in the example ofFIG. 3.

According to the example ofFIG. 8, a second isolation structure or e-fuse isolation structure170having a predetermined depth may be formed in the p-well region111located at the lower part of the poly-Si layer142. The e-fuse isolation structure170may have a length longer than a length of the e-fuse140and may have a depth deeper than a depth of the second switching N+ source region132or the second switching second switching N+ drain region133. A P-type guard ring150may be formed adjacent to the e-fuse isolation structure170.

Next, a current flow direction during a program operation and a read operation of a nonvolatile memory device, according to an example, is described in greater detail. The description of the current flow refers to the example ofFIG. 9, in which the first switching device110, the second switching device130, the diode120, and the e-fuse140may be connected to each other.

FIG. 9illustrates each device arranged in a vertical direction for convenience of description, but it should be noted that the devices are disposed on one semiconductor substrate as illustrated in the example ofFIG. 2or the example ofFIG. 3.

In such a configuration, during the program operation, the first and second switching devices110and130may be turned OFF. To program the e-fuse140, the program current may flow into the e-fuse140. Arrow {circle around (1)} indicates the program current path. The program current may flow into the e-fuse140and may flow out the diode120, according to arrow {circle around (1)}. Thus, the e-fuse140may be programed and then the resistance of e-fuse140may be increased because the silicide layer may be agglomerated on the poly-Si layer.

On the other hand, during the read operation, the first and second switching devices110and130may be turned ON. Arrow {circle around (2)} indicates a read current path. The read current may flow starting from the first switching device110and the read current may flow through the e-fuse, and may finally flows out of the second switching device130. In greater detail, the current flow may pass from the first switching N+ source region115bof the first switching device to the second switching N+ drain region133of the second switching device130, via the cathode and anode of the e-fuse140.

That is, it may be understood that the program operation of the nonvolatile memory device10of the example ofFIG. 9may flow through the diode120, while the read operation may not flow through the diode120, thereby providing different current flows for these differing operations. As described above, the current directions in the read and program operations may be opposite to each other, and thus the read operation, as indicated by arrow {circle around (2)}, may not need to flow through the diode120, thereby enabling operation at a low voltage.

FIG. 10is a cross-sectional view of the e-fuse unit cell structure100taken along line IV-IV′, in the example ofFIG. 2.

The second switching device130, at left, and the e-fuse140, at right, may be arranged side by side in the example ofFIG. 2. However, the positions of the second switching device130and the e-fuse140are changed inFIG. 10, that is, the e-fuse140, at left, and the second switching device130, at right, are positioned as shown. In order to sufficiently explain the longitudinal cross-sectional structure of the e-fuse unit cell structure100, the location of each device may be rearranged.

As illustrated in the example ofFIG. 10, the first switching device110, the diode120, the e-fuse140and the second switching device130may be sequentially connected from the left side of the drawing to configure the e-fuse unit cell structure100, as shown. In the present example, a plurality of e-fuse unit cells100may be provided in the row direction. The number of the e-fuse cells, for example, may be 128. The third switching device210in the program current control unit200may be connected to the anode of the e-fuse140of each cell100.

As illustrated in the example ofFIG. 10, a semiconductor device, according to a non-limiting example, may include a first contact plug163formed on first switching device110, a second contact plug165formed on the diode120, a third contact plug169formed on the e-fuse140, and a first metal interconnection173,179connecting the first contact plug163, the second contact plug165and the third contact plug169. The first metal interconnection173,179may indicates the first node N1, as shown in the example ofFIG. 3.

As illustrated in the example ofFIG. 10, a semiconductor device according to an example may further include a fourth contact plug168formed on anode of the e-fuse140, a fifth contact plug167formed on the N+ drain region133of the second switching device130, and a second metal interconnection177connecting the fourth contact plug168and the fifth contact plug167. The second metal interconnection177may refer to the second node N2, as shown in the example ofFIG. 3.

The first switching device110may be formed on a first well region, such as P-type well region, PW111aand the diode120may be formed on a second well region, such as N-type well region, NW121having a opposite conductivity type to that of the first well region111a, and the second switching device130may be formed on a third well region, such as P-type well region, PW111b, having a same conductivity type as that of the first well region111a. A guard ring150to enclose the first switching device110, the diode120, the e-fuse140and the second switching device130may be present, as well. The first switching device110and the second switching device130may be NMOS transistors.

As illustrated in the example ofFIG. 10, for the program operation, the third switching device210may be connected to the anode of e-fuse140. The program current may flow from the third switching device or PMOS transistor210into the anode of e-fuse140. Then, the e-fuse140may be programed and the program current may flows out through the diode120, including a P+ anode and an N+ cathode. During the program operation, the first switching device110and the second switching device130may be turned-off. The third switching device or PMOS transistor210may include a third switching P+ drain region191, a third switching P+ source region193, and a third switching gate electrode195between the P+ drain/source regions191,193. In such an example, the third switching P+ drain region191and the third switching P+ source region193may be formed in N-type well region121. Thus, the third switching P+ drain region191of the third switching device or PMOS transistor210may be electrically connected to the anode of the e-fuse.

For the read operation, the read current may flow into the first switching device110and through the e-fuse140and may finally flow out of the second switching device130. The metal lines173,179or N1, and177or N2, may be used for the read current path. Thus, the read current path, which may be left to right, may be opposite to that of the program current path, which may be right to left. As shown in the example ofFIG. 3, the read word line240B may turn on both the first switching device110and the second switching device130for the read operation.

As described above, it may be seen that the present disclosure performs the program and read operations using different current paths during the program operation and the read operation of the nonvolatile memory device10. In this example, the program voltage may require 5.5V for the path through the e-fuse and diode during the program operation, but the voltage level may be adjusted to 1.6-5.5V for the path through only the e-fuse and the first and second switching devices, during the read operation.

Also, when the nonvolatile memory device10is arranged to form a diode-type e-fuse cell as in the present examples, it may be possible to provide a design that may reduce the area of the nonvolatile memory device10. Such reduction of area may cause the nonvolatile memory device10to be suitable for other applications. That is, for example, when the area of an e-fuse cell based on a 2K bit transistor and that of an e-fuse cell based on a 2K bit diode as in the present disclosure are tested, the area of the present disclosure may be 2.8E7 μm2, while the transistor based e-fuse cell may be 5.0E7 μm2, which is a significant reduction in the size of the area.

As described above, the e-fuse cell of the present disclosure may be manufactured into a diode type employing a diode as a program selection device while appropriately disposing devices provided therein, thereby reducing the area of the existing e-fuse cell. Such an approach may also be expected to reduce the size of the memory device employing the e-fuse cell.

In addition, because the current paths of the program operation and the read operation of the e-fuse cell may be set differently, a stable operation with a lower current may be possible.