Methods of forming conductive contacts in the fabrication of integrated circuitry

A method of forming a conductive contact includes forming a structure comprising an upper surface joining with a sidewall surface. The sidewall surface contains elemental-form silicon. Silicon is epitaxially grown from the sidewall surface. Dielectric material is formed over the upper surface and the epitaxially-grown silicon. A conductive contact is formed through the dielectric material to conductively connect with the upper surface.

TECHNICAL FIELD

Embodiments disclosed herein pertain to methods of forming conductive contacts in the fabrication of integrated circuitry.

BACKGROUND

In the fabrication of integrated circuitry, components at different elevations may be electrically interconnected. For example, an insulating/dielectric material may be deposited over a lower component, and an opening etched therethrough to expose an area of the lower component to which electrical connection is to be made. The opening is filled with conductive material which may then be used in the fabrication of another conductive component or in making electrical connection with another conductive component.

It is desirable to precisely align the opening which is etched in the dielectric material to the contact area for the lower component. The individual circuit components continue to be fabricated to increasingly small lateral dimensions resulting in the contact areas for the smaller devices shrinking as well. If the opening in the dielectric material does not sufficiently overlie the contact area of the underlying component, no electrical connection may be made, and may result in inoperable circuitry.

While the invention was motivated in addressing the above-identified issues, it is no way so limited. Rather, the invention is limited by the accompanying claims as literally worded and as appropriately interpreted in accordance with the doctrine of equivalence.

DETAILED DESCRIPTION OF EXAMPLE EMBODIMENTS

Example first embodiments of methods of forming a conductive contact are described with respect to a substrate10inFIGS. 1-3. Referring toFIG. 1, substrate10comprises substrate material12and may comprise a semiconductor substrate. In the context of this document, the term “semiconductor substrate” or “semiconductive substrate” is defined to mean any construction comprising semiconductive material, including, but not limited to, bulk semiconductive materials such as a semiconductive wafer (either alone or in assemblies comprising other materials thereon), and semiconductive material layers (either alone or in assemblies comprising other materials). The term “substrate” refers to any supporting structure, including, but not limited to, the semiconductive substrates described above. Substrate material12may be homogenous or non-homogenous, and may comprise multiple different composition materials and/or layers. A structure14has been formed relative to substrate material12, and comprises an upper surface16joining with a sidewall surface18that joins with a surface20. Structure14is shown as a simple step wherein sidewall surface18and upper surface16are each straight and join at an angle of about 90°. Other structures, for example including other angles and curving surfaces, may be used.

Sidewall surface18comprises elemental-form silicon along some or all of its length. Example materials are monocrystalline or polycrystalline silicon. In one embodiment, some or all of upper surface16comprises elemental-form silicon. Similarly, some or all of surface20may comprise elemental-form silicon.

Upper surface16may comprise a contact area24to which conductive electrical connection is to be made. Accordingly, contact area24may be considered as a node location which, in this example, is a diffusion region22which has been formed within substrate material12. Contact area24may be of any size and shape, and is shown as having an example lateral expanse “A” inFIG. 1. Expanse or location A may be considered as a targeting area for making electrical connection relative to contact area24.

Referring toFIG. 2, silicon26has been epitaxially grown laterally from sidewall surface18. Such has also been grown elevationally from upper surface16. Such may be conductively doped with a suitable conductivity enhancing impurity during or subsequent to such growth, thereby rending material26electrically conductive. Targeting area A in this example has thereby been enlarged or laterally widened to dimension B. In one embodiment, the epitaxial growth is sufficiently great to increase contact area24by at least 50%. Silicon26may be epitaxially grown by any suitable existing or yet-to-be developed technique. For example, such can be grown by vapor-phase-epitaxy using SiCl4and H2as source precursors at about 1200° C. As alternate examples, such may be grown using silane, dichlorosilane, and/or trichlorosilane as source gases.

Referring toFIG. 3, dielectric material28has been formed over upper surface16and epitaxially-grown silicon26. Such may be homogenous or non-homogenous, with doped silicon dioxide (i.e., borosilicate glass, phosphosilicate glass, borophosphosilicate glass, etc) and silicon nitride being examples. A contact opening30has subsequently been etched through dielectric material28, for example being targeted to overlie the targeting area represented by enlarged dimension B. Such has been filled with one or more suitable conductive materials32, thereby forming a conductive contact34. Such provides but one example of forming a conductive contact through dielectric material to conductively connect with upper surface16, in this example through epitaxially-grown silicon26. In one embodiment and as shown, the conductive contact physically touches the epitaxially-grown silicon. In one embodiment, conductive contact34may be received entirely within the confines of lateral dimension A (not shown). Alternately as shown, such may extend beyond the borders of lateral dimension A and into expanse B received laterally outward thereof.

Processing relative to another embodiment substrate fragment10ais next described with reference toFIGS. 4-6. Like numerals from the above-described embodiments have been used where appropriate, with some construction differences being indicated with the suffix “a” or with different numerals. Referring toFIG. 4, substrate10adiffers from substrate10ofFIG. 1in having upper surface16masked with material36. Such may be homogenous or non-homogenous comprising multiple different compositions and/or layers. Silicon dioxide and/or silicon nitride are examples. Outermost surfaces of material36may comprise no or insufficient elemental-form silicon such that no epitaxial growth may occur there-from.

Referring toFIG. 5, silicon26ahas been epitaxially grown laterally from sidewall surface18. Material36masks upper surface24so that no silicon epitaxially grows there-from during the epitaxially growing of silicon laterally from sidewall surface18. In one embodiment, epitaxially-grown silicon26amay have an upper-most surface38which is higher than upper surface16. In one embodiment, epitaxially-grown silicon26ahas a laterally outermost surface40which is further from sidewall surface18than is upper-most surface38from upper surface16. Specifically, laterally outermost surface40is shown at a distance C from sidewall surface18and upper-most surface38is shown at a distance D from upper surface16, with C being greater than D. Regardless,FIG. 5depicts lateral expanse A of contact area24as having been increased to a lateral expanse E, thereby increasing the targeting area.

Referring toFIG. 6, processing has occurred analogous to that described above wherein a conductive contact34has been formed through dielectric material28to conductively connect with upper surface16. Such conductive contact may or may not overlie epitaxially-grown silicon26a, may or may not physically touch such if it does so overlie, and may or may not physically touch upper surface16.

Additional embodiments are next described with respect toFIGS. 7-14in a method of forming, in some embodiments, a pair of conductive contacts and, in some embodiments, of forming a conductive contact to a source/drain area in the fabrication of a transistor. Like numerals from the above-described embodiments have been used where appropriate, with some construction differences being indicated with different numerals. Referring toFIG. 7, a substrate40includes semiconductive material42. Such may be homogenous or non-homogenous, with polycrystalline silicon and monocrystalline silicon being examples. A hard-mask44has been formed over semiconductive material42, and comprises layers46and48. Each may be homogenous or non-homogenous, with an example material46being undoped silicon dioxide and an example material48being silicon nitride and/or carbon. One or more anti-reflective coatings (not shown) may also be used. Hard-mask44has been used as a mask in forming a trench50into semiconductive material42, for example by anisotropic dry etching. Trench50may be longitudinally elongated, for example extending into and out of the plane of the page upon whichFIG. 7lies. Trench50comprises opposing sidewall surfaces52which individually join with upper surfaces54on opposing sides of trench50. Sidewall surfaces52comprise elemental-form silicon along at least some portions of their respective lengths, including along upper portions thereof. In one embodiment, upper surfaces54comprise elemental-form silicon. Regardless, upper surfaces54comprise contact areas to which individual of the conductive contacts of the pair are to electrically connect as will apparent in the continuing discussion. In one embodiment, upper surfaces54will comprise respective source/drain areas of one or more transistors being fabricated.

Referring toFIG. 8, a gate dielectric56has been formed within trench50over sidewall surfaces52. Such may be homogenous or non-homogenous, with silicon dioxide and/or silicon nitride being examples.

Referring toFIG. 9, conductive gate material58has been formed within trench50to laterally cover upper sidewall portions of gate dielectric56. Conductive material58may be homogenous or non-homogenous, with conductively doped polysilicon and/or titanium nitride being examples.

Referring toFIG. 10, an upper portion of conductive gate material58has been removed to expose an upper sidewall portion of gate dielectric56within that portion of trench50which is within semiconductive material42. Any suitable timed dry anisotropic etch may be used. Such may also etch some of conductive gate material58from being received laterally over gate dielectric56at lowest-most sidewall portions thereof, for example as shown.

Referring toFIG. 11, a suitable dielectric60has been deposited and subsequently recessed within trench50. An example dielectric material60is silicon dioxide, for example in the form of a spin-on-dielectric. Gate dielectric56has also been removed from the upper portions of trench sidewalls52of material42to expose elemental-form silicon of trench sidewalls52where such join with upper surfaces54. Such may be conducted using any suitable wet or dry etching technique(s). Some of masking material44may be etched (not shown) previously or during such etching. The removing of outer portions of materials60and56as shown inFIG. 11may occur in the same step or in different steps. For example, where materials60and56are of the same composition or of different compositions capable of being etched with the same etching chemistry, such might be removed in the same etching step. Alternately if such are of different compositions, etching of materials60and56might occur in separate etching steps.

The above processing describes but one method of masking opposing lower portions of sidewall surfaces52and leaving opposing upper portions of sidewall surfaces52exposed. In one embodiment, such opposing upper portions of the sidewall surfaces are planar and parallel one another. In one embodiment, upper surfaces54are planar, in one embodiment are co-planar, and the opposing upper portions of sidewall surfaces52extend perpendicularly relative to such co-planar upper surfaces54. In one embodiment, lower portions of sidewall surfaces52are masked with insulative material, for example with material56as shown. In one embodiment, lower portions of sidewall surfaces52are masked with conductive material, for example with material58as shown. In one embodiment, the lower portions are masked with insulative material and with conductive material, and in one embodiment with the insulative material being received between the conductive material and the sidewall surfaces of the lower portions, for example as shown.

Upper surfaces54comprise contact areas62to which individual of the conductive contacts of the pair are to electrically connect. In one embodiment, such contact areas will comprise respective source/drain regions of a field effect transistor. Regardless, each is depicted as comprising a respective lateral expanse “A” which exemplifies a targeting area for forming electrical contact with contact area62.

Referring toFIG. 12, opposing silicon blocks64have been epitaxially grown toward one another from opposing exposed upper portions of sidewall surfaces52of material42above the masked lower portions of sidewall surfaces52to effectively increase upper surface area of contact areas62. In one embodiment, the epitaxial growth forms the opposing blocks of the pair to each be of the same size. In one embodiment, upper surfaces54are masked during such epitaxial growth such that no silicon epitaxially grows there-from where such comprises elemental-form silicon during the epitaxially growing of the silicon blocks from the exposed opposing upper portions of sidewall surfaces52. For example in the depicted embodiment, at least some of masking material44has remained over substrate40during such epitaxial growing of silicon blocks64.FIG. 12depicts an increase of the upper surface area for electrically connecting with contact areas62represented by increased lateral expanse B.

As with the first-described embodiments, such epitaxial growth may form the epitaxially-grown silicon to have an upper-most surface which is higher than upper surfaces54, for example as shown with respect to upper-most surfaces65of silicon blocks64relative to upper surfaces54of semiconductive material42. Further, analogously to the first-described embodiments, epitaxially-grown silicon blocks64may have a respective laterally outermost surface66which is further from sidewall surface52from which each is grown than are the respective upper-most surfaces65from upper surfaces54.

Referring toFIG. 13, isolation trenches70have been formed within semiconductive material42and filled with dielectric material72. Material48(not shown) has been removed, and dielectric material28has been formed over upper surface54and epitaxially-grown silicon block64. Alternate and/or additional processing may occur.

Referring toFIG. 14, contact openings30have been etched through dielectric material28and filled with conductive material32to form a pair of conductive contacts34. Such extend through dielectric material28and individually conductively connect to a respective one of contact areas62, which in one embodiment comprise upper surfaces of a respective source/drain region. At least one of the pair of conductive contacts34may overlie one of the epitaxially-grown silicon blocks, and if so may physically touch such epitaxially-grown silicon block, for example as shown. In one embodiment and in spite of the increase in contact area, the conductive contact may be received entirely within (not shown) lateral expanse A of contact area62.

Processing as described above, may provide greater area of contact between a conductive contact and an underlying node location, thereby reducing contact resistance. The above processing might be used in fabrication of memory circuitry, for example in DRAM circuitry of a cross-hair architecture.