Semiconductor device and method of forming stacked semiconductor die and conductive interconnect structure through an encapsulant

A semiconductor device has a first conductive layer formed over a first substrate. A second conductive layer is formed over a second substrate. A first semiconductor die is mounted to the first substrate and electrically connected to the first conductive layer. A second semiconductor die is mounted to the second substrate and electrically connected to the second conductive layer. The first semiconductor die is mounted over the second semiconductor die. An encapsulant is deposited over the first and second semiconductor die and the first and second substrates. A conductive interconnect structure is formed through the encapsulant to electrically connect the first and second semiconductor die to the second surface of the semiconductor device. Forming the conductive interconnect structure includes forming a plurality of conductive vias through the encapsulant and the first substrate outside a footprint of the first and second semiconductor die.

FIELD OF THE INVENTION

The present invention relates in general to semiconductor devices and, more particularly, to a semiconductor device and method of forming a stacked-die semiconductor package with an interconnect structure through an encapsulant to electrically connect the stacked die to a common surface of the package.

BACKGROUND OF THE INVENTION

Semiconductor devices are generally manufactured using two complex manufacturing processes, i.e., front-end manufacturing, and back-end manufacturing, each involving potentially hundreds of steps. Front-end manufacturing involves the formation of a plurality of die on the surface of a semiconductor wafer. Each semiconductor die is typically identical and contains circuits formed by electrically connecting active and passive components. Back-end manufacturing involves singulating individual semiconductor die from the finished wafer and packaging the die to provide structural support and environmental isolation. The term “semiconductor die” as used herein refers to both the singular and plural form of the words, and accordingly, can refer to both a single semiconductor device and multiple semiconductor devices.

One goal of semiconductor manufacturing is to produce smaller semiconductor devices. Smaller devices typically consume less power, have higher performance, and can be produced more efficiently. In addition, smaller semiconductor devices have a smaller footprint, which is desirable for smaller end products. A smaller semiconductor die size can be achieved by improvements in the front-end process resulting in semiconductor die with smaller, higher density active and passive components. Back-end processes may result in semiconductor device packages with a smaller footprint by improvements in electrical interconnection and packaging materials.

A conventional semiconductor device may contain stacked semiconductor die mounted to a substrate for high density and efficient integration of die. A plurality of first bond wires is formed to electrically connect a lower die to the substrate and a plurality of second bond wires is formed to electrically connect an upper die to the substrate. An encapsulant is formed over the die and the substrate. The bond wires formed between the upper and lower die and the substrate can cause an undesirable increase in the height of the package. An adhesive layer between the die must have sufficient thickness and headroom to enable the first bond wires to clear a footprint of the lower die without contacting the upper die. Additionally, the encapsulant must have sufficient thickness and headroom to enable the second bond wires to clear a footprint of the upper die without breaching a surface of the encapsulant. The process of forming bond wires greatly increases manufacturing time and expense, as well as increasing package profile.

SUMMARY OF THE INVENTION

A need exists for a simple, cost effective, and high-density semiconductor package with stacked semiconductor die and an interconnect structure to enable accessibility of input and output (I/O) signals of the stacked die from a single surface of the semiconductor package. Accordingly, in one embodiment, the present invention is a method of making a semiconductor device having first and second surfaces comprising the steps of providing a first substrate, forming a first conductive layer over the first substrate, mounting a first semiconductor die to the first substrate electrically connected to the first conductive layer, providing a second substrate, forming a second conductive layer over the second substrate, mounting a second semiconductor die to the second substrate electrically connected to the second conductive layer, mounting the first semiconductor die over the second semiconductor die, depositing an encapsulant over the first and second semiconductor die and the first and second substrates, and forming a first conductive interconnect structure through the encapsulant to electrically connect the first and second semiconductor die to the second surface of the semiconductor device.

In another embodiment, the present invention is a method of making a semiconductor device having first and second surfaces comprising the steps of providing a first substrate, mounting a first semiconductor die over the first substrate, providing a second substrate, mounting a second semiconductor die over the second substrate, mounting the second semiconductor die over the first semiconductor die, depositing a first encapsulant over the first and second semiconductor die, and forming a plurality of first interconnect structures through the first encapsulant to electrically connect the first and second semiconductor die to the second surface of the semiconductor device.

In another embodiment, the present invention is a method of making a semiconductor device comprising the steps of providing a first substrate, providing a second substrate, mounting a first semiconductor die to the first substrate, mounting a second semiconductor die to the second substrate, mounting the first semiconductor die over the second semiconductor die, and forming a first interconnect structure to electrically connect the first and second semiconductor die to a common surface of the semiconductor device.

In another embodiment, the present invention is a semiconductor device comprising a first substrate. A first semiconductor die is mounted to the first substrate. A second semiconductor die is mounted over the first semiconductor die. A second substrate is mounted to the second semiconductor die. An encapsulant is deposited over the first substrate, the second substrate, and the first and second semiconductor die. A conductive interconnect structure is formed through the encapsulant electrically connecting the first and second semiconductor die to a common surface of the semiconductor device.

DETAILED DESCRIPTION OF THE DRAWINGS

Patterning is the basic operation by which portions of the top layers on the semiconductor wafer surface are removed. Portions of the semiconductor wafer can be removed using photolithography, photomasking, masking, oxide or metal removal, photography and stenciling, and microlithography. Photolithography includes forming a pattern in reticles or a photomask and transferring the pattern into the surface layers of the semiconductor wafer. Photolithography forms the horizontal dimensions of active and passive components on the surface of the semiconductor wafer in a two-step process. First, the pattern on the reticle or masks is transferred into a layer of photoresist. Photoresist is a light-sensitive material that undergoes changes in structure and properties when exposed to light. The process of changing the structure and properties of the photoresist occurs as either negative-acting photo resist or positive-acting photo resist. Second, the photoresist layer is transferred into the wafer surface. The transfer occurs when etching removes the portion of the top layers of semiconductor wafer not covered by the photoresist. The chemistry of photoresists is such that the photoresist dissolves slowly and resists removal by chemical etching solutions while the portion of the top layers of the semiconductor wafer not covered by the photoresist is removed more rapidly. The process of forming, exposing, and removing the photoresist, as well as the process of removing a portion of the semiconductor wafer can be modified according to the particular resist used and the desired results.

In negative-acting photo resists, photoresist is exposed to light and is changed from a soluble condition to an insoluble condition in a process known as polymerization. In polymerization, unpolymerized material is exposed to a light or energy source and polymers form a cross-linked material that is etch-resistant. In most negative resists, the polymers are polyisopremes. Removing the soluble portions (i.e. the portions not exposed to light) with chemical solvents or developers leaves a hole in the resist layer that corresponds to the opaque pattern on the reticle. A mask whose pattern exists in the opaque regions is called a clear-field mask.

In positive-acting photo resists, photoresist is exposed to light and is changed from relatively nonsoluble condition to a much more soluble condition in a process known as photosolubilization. In photosolubilization, the relatively insoluble resist is exposed to the proper light energy and is converted to a more soluble state. The photosolubilized part of the resist can be removed by a solvent in the development process. The basic positive photoresist polymer is the phenol-formaldehyde polymer, also called the phenol-formaldehyde novolak resin. Removing the soluble portions (i.e. the portions exposed to light) with chemical solvents or developers leaves a hole in the resist layer that corresponds to the transparent pattern on the reticle. A mask whose pattern exists in the transparent regions is called a dark-field mask.

After removal of the top portion of the semiconductor wafer not covered by the photoresist, the remainder of the photoresist is removed, leaving behind a patterned layer. Alternatively, some types of materials are patterned by directly depositing the material into the areas or voids formed by a previous deposition/etch process using techniques such as electroless and electrolytic plating.

FIG. 1illustrates electronic device50having a chip carrier substrate or PCB52with a plurality of semiconductor packages mounted on its surface. Electronic device50can have one type of semiconductor package, or multiple types of semiconductor packages, depending on the application. The different types of semiconductor packages are shown inFIG. 1for purposes of illustration.

Electronic device50can be a stand-alone system that uses the semiconductor packages to perform one or more electrical functions. Alternatively, electronic device50can be a subcomponent of a larger system. For example, electronic device50can be part of a cellular phone, personal digital assistant (PDA), digital video camera (DVC), or other electronic communication device. Alternatively, electronic device50can be a graphics card, network interface card, or other signal processing card that can be inserted into a computer. The semiconductor package can include microprocessors, memories, application specific integrated circuits (ASIC), logic circuits, analog circuits, RF circuits, discrete devices, or other semiconductor die or electrical components. Miniaturization and weight reduction are essential for these products to be accepted by the market. The distance between semiconductor devices must be decreased to achieve higher density.

For the purpose of illustration, several types of first level packaging, including bond wire package56and flipchip58, are shown on PCB52. Additionally, several types of second level packaging, including ball grid array (BGA)60, bump chip carrier (BCC)62, dual in-line package (DIP)64, land grid array (LGA)66, multi-chip module (MCM)68, quad flat non-leaded package (QFN)70, and quad flat package72, are shown mounted on PCB52. Depending upon the system requirements, any combination of semiconductor packages, configured with any combination of first and second level packaging styles, as well as other electronic components, can be connected to PCB52. In some embodiments, electronic device50includes a single attached semiconductor package, while other embodiments call for multiple interconnected packages. By combining one or more semiconductor packages over a single substrate, manufacturers can incorporate pre-made components into electronic devices and systems. Because the semiconductor packages include sophisticated functionality, electronic devices can be manufactured using less expensive components and a streamlined manufacturing process. The resulting devices are less likely to fail and less expensive to manufacture resulting in a lower cost for consumers.

FIGS. 2a-2cshow exemplary semiconductor packages.FIG. 2aillustrates further detail of DIP64mounted on PCB52. Semiconductor die74includes an active region containing analog or digital circuits implemented as active devices, passive devices, conductive layers, and dielectric layers formed within the die and are electrically interconnected according to the electrical design of the die. For example, the circuit can include one or more transistors, diodes, inductors, capacitors, resistors, and other circuit elements formed within the active region of semiconductor die74. Contact pads76are one or more layers of conductive material, such as aluminum (Al), copper (Cu), tin (Sn), nickel (Ni), gold (Au), or silver (Ag), and are electrically connected to the circuit elements formed within semiconductor die74. During assembly of DIP64, semiconductor die74is mounted to an intermediate carrier78using a gold-silicon eutectic layer or adhesive material such as thermal epoxy or epoxy resin. The package body includes an insulative packaging material such as polymer or ceramic. Conductor leads80and bond wires82provide electrical interconnect between semiconductor die74and PCB52. Encapsulant84is deposited over the package for environmental protection by preventing moisture and particles from entering the package and contaminating semiconductor die74or bond wires82.

FIG. 2billustrates further detail of BCC62mounted on PCB52. Semiconductor die88is mounted over carrier90using an underfill or epoxy-resin adhesive material92. Bond wires94provide first level packaging interconnect between contact pads96and98. Molding compound or encapsulant100is deposited over semiconductor die88and bond wires94to provide physical support and electrical isolation for the device. Contact pads102are formed over a surface of PCB52using a suitable metal deposition process such as electrolytic plating or electroless plating to prevent oxidation. Contact pads102are electrically connected to one or more conductive signal traces54in PCB52. Bumps104are formed between contact pads98of BCC62and contact pads102of PCB52.

InFIG. 2c, semiconductor die58is mounted face down to intermediate carrier106with a flipchip style first level packaging. Active region108of semiconductor die58contains analog or digital circuits implemented as active devices, passive devices, conductive layers, and dielectric layers formed according to the electrical design of the die. For example, the circuit can include one or more transistors, diodes, inductors, capacitors, resistors, and other circuit elements within active region108. Semiconductor die58is electrically and mechanically connected to carrier106through bumps110.

BGA60is electrically and mechanically connected to PCB52with a BGA style second level packaging using bumps112. Semiconductor die58is electrically connected to conductive signal traces54in PCB52through bumps110, signal lines114, and bumps112. A molding compound or encapsulant116is deposited over semiconductor die58and carrier106to provide physical support and electrical isolation for the device. The flipchip semiconductor device provides a short electrical conduction path from the active devices on semiconductor die58to conduction tracks on PCB52in order to reduce signal propagation distance, lower capacitance, and improve overall circuit performance. In another embodiment, the semiconductor die58can be mechanically and electrically connected directly to PCB52using flipchip style first level packaging without intermediate carrier106.

FIG. 3ashows a semiconductor wafer120with a base substrate material122, such as silicon, germanium, gallium arsenide, indium phosphide, or silicon carbide, for structural support. A plurality of semiconductor die or components124is formed on semiconductor wafer120separated by a non-active, inter-die wafer area or saw street126as described above. Saw street126provides cutting areas to singulate semiconductor wafer120into individual semiconductor die124.

FIG. 3bshows a cross-sectional view of a portion of semiconductor wafer120. Each semiconductor die124has a back surface128and active surface130containing analog or digital circuits implemented as active devices, passive devices, conductive layers, and dielectric layers formed within the die and electrically interconnected according to the electrical design and function of the die. For example, the circuit may include one or more transistors, diodes, and other circuit elements formed within active surface130to implement analog circuits or digital circuits, such as digital signal processor (DSP), ASIC, memory, or other signal processing circuit. Semiconductor die124may also contain integrated passive devices (IPDs), such as inductors, capacitors, and resistors, for RF signal processing.

An electrically conductive layer132is formed over active surface130using PVD, CVD, electrolytic plating, electroless plating process, or other suitable metal deposition process. Conductive layer132can be one or more layers of Al, Cu, Sn, Ni, Au, Ag, or other suitable electrically conductive material. Conductive layer132operates as contact pads electrically connected to the circuits on active surface130. Contact pads132can be disposed side-by-side a first distance from the edge of semiconductor die124, as shown inFIG. 3b. Alternatively, contact pads132can be offset in multiple rows such that a first row of contact pads is disposed a first distance from the edge of the die, and a second row of contact pads alternating with the first row is disposed a second distance from the edge of the die.

An electrically conductive bump material is deposited over conductive layer132using an evaporation, electrolytic plating, electroless plating, ball drop, or screen printing process. The bump material can be Al, Sn, Ni, Au, Ag, Pb, Bi, Cu, solder, and combinations thereof, with an optional flux solution. For example, the bump material can be eutectic Sn/Pb, high-lead solder, or lead-free solder. The bump material is bonded to conductive layer132using a suitable attachment or bonding process. In one embodiment, the bump material is reflowed by heating the material above its melting point to form balls or bumps134. In some applications, bumps134are reflowed a second time to improve electrical contact to conductive layer132. Bumps134can also be compression bonded to conductive layer132. Bumps134represent one type of interconnect structure that can be formed over conductive layer132. The interconnect structure can also use stud bump, micro bump, or other electrical interconnect.

InFIG. 3c, semiconductor wafer120is singulated through saw street126using a saw blade or laser cutting tool136into individual semiconductor die124.

FIGS. 4a-4tillustrate, in relation toFIGS. 1 and 2a-2c, a process of forming a stacked-die semiconductor package with an interconnect structure through an encapsulant to electrically connect the stacked die to a common surface of the package. InFIG. 4a, a temporary substrate or carrier140contains sacrificial base material such as silicon, polymer, beryllium oxide, glass, or other suitable low-cost, rigid material for structural support. An interface layer or double-sided tape142is formed over carrier140as a temporary adhesive bonding film, etch-stop layer, or release layer. A semiconductor wafer or substrate144contains base material, such as silicon, germanium, gallium arsenide, indium phosphide, or silicon carbide, for structural support. As a semiconductor wafer, substrate144can contain embedded integrated semiconductor die or discrete devices. Substrate144can also be a multi-layer flexible laminate, ceramic or leadframe. Substrate144is mounted to interface layer142over carrier140.

InFIG. 4b, a plurality of vias is formed through substrate144using laser drilling, mechanical drilling, or deep reactive ion etching (DRIE). The vias are filled with Al, Cu, Sn, Ni, Au, Ag, titanium (Ti), tungsten (W), poly-silicon, or other suitable electrically conductive material using electrolytic plating, electroless plating process, or other suitable metal deposition process to form z-direction vertical interconnect conductive vias146.

An insulating or passivation layer148is formed over a surface of substrate144and conductive vias146using PVD, CVD, printing, spin coating, spray coating, sintering or thermal oxidation. The insulating layer148contains one or more layers of silicon dioxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiOn), tantalum pentoxide (Ta2O5), aluminum oxide (Al2O3), or other material having similar insulating and structural properties. A portion of insulating layer148is removed by an etching process with a patterned photoresist layer to expose substrate144and conductive vias146.

An electrically conductive layer150is formed over the exposed substrate144and conductive vias146using a patterning and metal deposition process such as printing, PVD, CVD, sputtering, electrolytic plating, and electroless plating. Conductive layer150is one or more layers of Al, Cu, Sn, Ni, Au, Ag, or other suitable electrically conductive material. Conductive layer150is electrically connected to conductive vias146.

InFIG. 4c, a temporary substrate or carrier154contains sacrificial base material such as silicon, polymer, beryllium oxide, glass, or other suitable low-cost, rigid material for structural support. An interface layer or double-sided tape156is formed over carrier154as a temporary adhesive bonding film, etch-stop layer, or release layer. Leading with insulating layer148and conductive layer150, substrate144is mounted to interface layer156over carrier154. Carrier140and interface layer142are removed by chemical etching, mechanical peeling, CMP, mechanical grinding, thermal bake, UV light, laser scanning, or wet stripping to expose a surface of substrate144and conductive vias146opposite conductive layer150.

An insulating or passivation layer158is formed over substrate144and conductive vias146using PVD, CVD, printing, spin coating, spray coating, sintering or thermal oxidation. The insulating layer158contains one or more layers of SiO2, Si3N4, SiOn, Ta2O5, Al2O3, or other material having similar insulating and structural properties. A portion of insulating layer158is removed by an etching process with a patterned photoresist layer to expose substrate144and conductive vias146.

An electrically conductive layer160is formed over the exposed substrate144and conductive vias146using a patterning and metal deposition process such as printing, PVD, CVD, sputtering, electrolytic plating and electroless plating. Conductive layer160can be one or more layers of Al, Cu, Sn, Ni, Au, Ag, or other suitable electrically conductive material. Conductive layer160is electrically connected to conductive vias146and conductive layer150. In another embodiment, conductive vias146are formed through substrate144after forming conductive layers150and/or160. Conductive layers150and160can be formed prior to insulating layer148and158, respectively. The resulting wafer-form through silicon via (TSV) interposer or substrate162provides electrical interconnect vertically and laterally across the substrate.

InFIG. 4g, a substrate layer170contains a base material, such as silicon, germanium, gallium arsenide, indium phosphide, or silicon carbide, for structural support, similar toFIGS. 4a-4d. As a semiconductor wafer, substrate170can contain embedded integrated semiconductor die or discrete devices. Substrate170can also be a multi-layer flexible laminate, ceramic, or leadframe. A plurality of vias is formed through substrate170using laser drilling, mechanical drilling or DRIE. The vias are filled with Al, Cu, Sn, Ni, Au, Ag, Ti, W, poly-silicon, or other suitable metal deposition process to form a plurality of z-direction vertical interconnect conductive vias172.

An insulating layer174is formed over a surface of substrate170and conductive vias172using PVD, CVD, printing, spin coating, spray coating, sintering or thermal oxidation. The insulating layer174contains one or more layers of SiO2, Si3N4, SiON, Ta2O5, Al2O3, or other material having similar insulating and structural properties. A portion of insulating layer174is removed by an etching process with a patterned photoresist layer to expose substrate170and conductive vias172.

Conductive layer176is formed over the exposed substrate170and conductive vias172using a patterning and metal deposition process such as printing, PVD, CVD, sputtering, electrolytic plating, and electroless plating. Conductive layer176can be one or more layers of Al, Cu, Sn, Ni, Au, Ag, or other suitable electrically conductive material. Conductive layer176is electrically connected to conductive vias172.

A temporary substrate or carrier178contains sacrificial base material such as silicon, polymer, beryllium oxide, glass, or other suitable low-cost, rigid material for structural support. An interface layer180is formed over carrier178as a temporary adhesive bonding film, etch-stop layer, or release layer. Leading with insulating layer174and conductive layer176, substrate170is mounted to carrier178with interface layer180.

An insulating or passivation layer182is formed over substrate170and conductive vias172using PVD, CVD, printing, spin coating, spray coating, sintering or thermal oxidation. The insulating layer182contains one or more layers of SiO2, Si3N4, SiON, Ta2O5, Al2O3, or other material having similar insulating and structural properties. A portion of insulating layer182is removed by an etching process with a patterned photoresist layer to expose substrate170and conductive vias172.

An electrically conductive layer184is formed over the exposed substrate170and conductive vias172using a patterning and metal deposition process such as printing, PVD, CVD, sputtering, electrolytic plating, and electroless plating. Conductive layer184can be one or more layers of Al, Cu, Sn, Ni, Au, Ag, or other suitable electrically conductive material. Conductive layer184is electrically connected to conductive vias172. In another embodiment, conductive vias172are formed through substrate170after forming conductive layers176and/or184. Conductive layers176and184can be formed prior to insulating layer174and182, respectively. The resulting wafer-form TSV interposer or substrate186provides electrical interconnect vertically and laterally across the substrate.

InFIG. 4h, a plurality of semiconductor die188originating from a semiconductor wafer, similar toFIGS. 3a-3c, has a back surface190and an active surface192containing analog or digital circuits implemented as active devices, passive devices, conductive layers, and dielectric layers formed within the die and electrically interconnected according to the electrical design and function of the die. For example, the circuit may include one or more transistors, diodes, and other circuit elements formed within active surface192to implement analog circuits or digital circuits, such as DSP, ASIC, memory or other signal processing circuit. Semiconductor die188may also contain IPDs, such as inductors, capacitors, and resistors, for RF signal processing. A plurality of contact pads194is formed on active surface192and electrically connected to the circuits on the active surface. A plurality of bumps196is formed over contact pads194.

Each semiconductor die188is mounted to conductive layer184of TSV substrate186using a pick and place operation with active surface192oriented toward the substrate. Bumps196are reflowed to electrically connect conductive layer194of semiconductor die188to conductive layer184of TSV substrate186.FIG. 4ishows semiconductor die188mounted to TSV substrate186.

InFIG. 4j, a portion of TSV substrate186is removed using a saw blade or laser cutting tool198to create gap200between semiconductor die188and extending down to interface layer180. Carrier178provides structural support for TSV substrate186and semiconductor die188during formation of gap200.

InFIG. 4l, semiconductor die188is mounted to adhesive layer202, over semiconductor die124, with back surface190oriented toward back surface128. In another embodiment, adhesive layer202is formed over back surface190of semiconductor die188.

InFIG. 4n, the assembly fromFIG. 4m, containing semiconductor die124, semiconductor die188, TSV substrate162, and TSV substrate186, is placed in chase mold204. Chase mold204has an upper mold support206and lower mold support208, which are brought together to enclose semiconductor die124, semiconductor die188, TSV substrate162, and TSV substrate186with open space210. The lower mold support208includes a plurality of openings or gates212for injecting MUF material into open space210.

InFIG. 4r, a plurality of vias220is formed through MUF material214, extending to conductive layer160using laser drilling, mechanical drilling, or DRIE. The sidewalls of vias220can have a tapered, straight, or stepped profile.

An electrically conductive bump material is deposited over conductive layer176of TSV substrate186using an evaporation, electrolytic plating, electroless plating, ball drop, or screen printing process. The bump material can be Al, Sn, Ni, Au, Ag, Pb, Bi, Cu, solder, and combinations thereof, with an optional flux solution. For example, the bump material can be eutectic Sn/Pb, high-lead solder, or lead-free solder. The bump material is bonded to conductive layer176using a suitable attachment or bonding process. In one embodiment, the bump material is reflowed by heating the material above its melting point to form balls or bumps224. In some applications, bumps224are reflowed a second time to improve electrical contact to conductive layer176. An under bump metallization (UBM) layer can be formed under bumps224. Bumps224can also be compression bonded to conductive layer176. Bumps224represent one type of interconnect structure that can be formed over conductive layer176. The interconnect structure can also use stud bump, micro bump, or other electrical interconnect. In a similar process, an electrically conductive bump material is deposited over conductive vias222, substantially coplanar with bumps224, to form bumps226.

InFIG. 4t, the assembly fromFIG. 4sis singulated through MUF material214and TSV substrate162, outside a footprint of semiconductor die124and188, through gap200, with saw blade or laser cutting tool228into individual integrated dual flipchip semiconductor packages230.

FIG. 5shows semiconductor package230after singulation. Semiconductor die124is mounted over semiconductor die188with adhesive layer202, providing a high density of semiconductor die within a small footprint. Semiconductor die124is mechanically and electrically connected to TSV substrate162with bumps134. Conductive layers150and160, and conductive vias146, provide electrical connectivity vertically and horizontally across TSV substrate162. Semiconductor die188is mechanically and electrically connected to TSV substrate186with bumps196. Conductive layers176and184, and conductive vias172, provide electrical connectivity vertically and horizontally across TSV substrate186.

The length of TSV substrate186is less than the length of TSV substrate162to allow clearance for conductive vias222. Semiconductor die124and188, and TSV substrates162and186are disposed within a chase mold and MUF material214is deposited over the assembly. MUF material214is uniformly formed over semiconductor die124and188in a single manufacturing step, eliminating the need to deposit MUF material over each die individually. Conductive vias222are formed through MUF material214to electrically connect TSV substrate162to a common surface231of semiconductor package230. Bumps226are formed over an exposed surface of conductive vias222. Bumps224are formed over conductive layer176of TSV substrate186.

Semiconductor die124is electrically connected through contact pads132, bumps134, TSV substrate162, and conductive vias222to the common surface231of semiconductor package230. Semiconductor die188is electrically connected through bumps196, and TSV substrate186to the common surface231of semiconductor package230. Accordingly, TSV substrate162and186, conductive vias222, and bumps134and196form a conductive interconnect structure to provide electrical paths for I/O signals of semiconductor die124and188to a common surface231of semiconductor package230.

FIGS. 6a-6jillustrate, in relation toFIGS. 1 and 2a-2c, a process of forming a stacked-die semiconductor package with first and second substrates and an interconnect structure through an encapsulant to electrically connect the first and second substrates. Continuing fromFIG. 4i, an adhesive layer234is formed over back surface128of semiconductor die124, as shown inFIG. 6a. Adhesive layer234can be thermal epoxy, epoxy resin, B-stage epoxy laminating film, UV B-stage film adhesive layer, UV B-stage film adhesive layer including acrylic polymer, thermo-setting adhesive film layer, WIF encapsulant material, suitable wafer backside coating, epoxy resin with organic filler, silica filler, or polymer filler, acrylate based adhesive, epoxy-acrylate adhesive, a PI-based adhesive or other suitable adhesive material.

InFIG. 6b, semiconductor die188is mounted to adhesive layer234, over semiconductor die124, with back surface190oriented toward back surface128. In another embodiment, adhesive layer234is formed over back surface190of semiconductor die188.FIG. 6cshows semiconductor die188mounted over semiconductor die124to adhesive layer234.

InFIG. 6d, the assembly fromFIG. 6c, containing semiconductor die124, semiconductor die188, TSV substrate162, and TSV substrate186, is placed in chase mold236. Chase mold236has an upper mold support238and lower mold support240, which are brought together to enclose semiconductor die124, semiconductor die188, TSV substrate162, and TSV substrate186with open space242. The lower mold support240includes a plurality of openings or gates244for injecting MUF material into open space242.

InFIG. 6e, MUF material246in a liquid state is injected through gates244with nozzles248while an optional vacuum assist250draws pressure from the side of chase mold236to uniformly fill open space242over semiconductor die124, semiconductor die188, TSV substrate162and TSV substrate186with MUF material246. MUF material246can be an encapsulant, molding compound, polymer composite material, such as epoxy resin with filler, epoxy acrylate with filler, or polymer with proper filler.FIG. 6fshows MUF material246disposed around and between semiconductor die124, semiconductor die188, TSV substrate162, and TSV substrate186. InFIG. 6g, semiconductor die124, semiconductor die188, TSV substrate162and TSV substrate186are removed from chase mold236.

InFIG. 6h, a plurality of vias252is formed through MUF material246, TSV substrate162, and TSV substrate186, extending from conductive layer176to conductive layer150using laser drilling, mechanical drilling, or DRIE. The sidewalls of vias252can have a tapered, straight, or stepped profile.

An electrically conductive bump material is deposited over conductive layer150of TSV substrate162using an evaporation, electrolytic plating, electroless plating, ball drop, or screen printing process. The bump material can be Al, Sn, Ni, Au, Ag, Pb, Bi, Cu, solder, and combinations thereof, with an optional flux solution. For example, the bump material can be eutectic Sn/Pb, high-lead solder, or lead-free solder. The bump material is bonded to conductive layer150using a suitable attachment or bonding process. In one embodiment, the bump material is reflowed by heating the material above its melting point to form balls or bumps256. In some applications, bumps256are reflowed a second time to improve electrical contact to conductive layer150. An under bump metallization layer can be formed under bumps256. Bumps256can also be compression bonded to conductive layer150. Bumps256represent one type of interconnect structure that can be formed over conductive layer150. The interconnect structure can also use stud bump, micro bump, or other electrical interconnect. In a similar process, an electrically conductive bump material is deposited over conductive vias254, coplanar with bumps256, to form bumps258.

FIG. 7shows semiconductor package260after singulation. Semiconductor die124is mounted over semiconductor die188with adhesive layer234, providing a high density of semiconductor die within a small footprint. Semiconductor die124is mechanically and electrically connected to TSV substrate162with bumps134. Conductive layers150and160, and conductive vias146provide electrical connectivity vertically and horizontally across TSV substrate162. Semiconductor die188is mechanically and electrically connected to TSV substrate186with bumps196. Conductive layers176and184, and conductive vias172provide electrical connectivity vertically and horizontally across TSV substrate186.

Semiconductor die124and188, and TSV substrates162and186are disposed within a chase mold and MUF material246is deposited over the assembly. MUF material246is uniformly formed over semiconductor die124and188in a single manufacturing step, eliminating the need to deposit MUF material over each die individually. Conductive vias254are formed through MUF material246, TSV substrate162, and TSV substrate186to electrically connect TSV substrates162and186to common surface261. Bumps258are formed over an exposed surface of conductive vias254. Bumps224are formed over conductive layer176of TSV substrate186.

Semiconductor die124is electrically connected through contact pads132, bumps134, TSV substrate162, and conductive vias254to the common surface261of semiconductor package260. Semiconductor die188is electrically connected through bumps196, TSV substrate186, and conductive vias154to the common surface261of semiconductor package260. Accordingly, TSV substrate162and186, bumps134and196, and conductive vias254form a conductive interconnect structure to provide electrical paths for I/O signals of semiconductor die124and188to the entire common surface261of semiconductor package260.

FIGS. 8a-8hillustrate, in relation toFIGS. 1 and 2a-2c, a process of forming a stacked-die semiconductor package with wire bonds electrically connecting an upper semiconductor die to a first substrate. InFIG. 8a, continuing fromFIG. 4k, a temporary substrate or carrier262contains sacrificial base material such as silicon, polymer, beryllium oxide, glass, or other suitable low-cost, rigid material for structural support. An interface layer or double-sided tape264is formed over carrier262as a temporary adhesive bonding film. Semiconductor die188is mounted to interface layer264over carrier262with back surface190oriented toward carrier262. Carrier178and interface layer180are removed by chemical etching, mechanical peeling, CMP, mechanical grinding, thermal bake, UV light, laser scanning, or wet stripping to expose conductive layer176and insulating layer174.

InFIG. 8d, MUF material278in a liquid state is injected through gates276with nozzles280while an optional vacuum assist282draws pressure from the side of chase mold268to uniformly fill open space274around semiconductor die124, semiconductor die188, TSV substrate162, TSV substrate186, and bond wires266with MUF material278. MUF material278can be an encapsulant, molding compound, polymer composite material, such as epoxy resin with filler, epoxy acrylate with filler, or polymer with proper filler.FIG. 8eshows MUF material278disposed around and between semiconductor die124, semiconductor die188, TSV substrate162, TSV substrate186, and bond wires266. InFIG. 8f, semiconductor die124, semiconductor die188, TSV substrate162and TSV substrate186are removed from chase mold268. A plurality of vias284is formed through MUF material278extending to conductive layer160using laser drilling, mechanical drilling, or DRIE. The sidewalls of vias284can have a tapered, straight, or stepped profile.

An electrically conductive bump material is deposited over vias286using an evaporation, electrolytic plating, electroless plating, ball drop, or screen printing process. The bump material can be Al, Sn, Ni, Au, Ag, Pb, Bi, Cu, solder, and combinations thereof, with an optional flux solution. For example, the bump material can be eutectic Sn/Pb, high-lead solder, or lead-free solder. The bump material is bonded to conductive vias286using a suitable attachment or bonding process. In one embodiment, the bump material is reflowed by heating the material above its melting point to form balls or bumps288. In some applications, bumps288are reflowed a second time to improve electrical contact to conductive vias286. A UBM layer can be formed under bumps288. Bumps288can also be compression bonded to conductive vias286. Bumps288represent one type of interconnect structure that can be formed over conductive vias286. The interconnect structure can also use stud bump, micro bump, or other electrical interconnect.

InFIG. 8h, the assembly fromFIG. 8gis singulated through MUF material278and TSV substrate162, outside a footprint of semiconductor die124and188, with saw blade or laser cutting tool289into individual integrated dual flipchip semiconductor packages290.

FIG. 9shows semiconductor package290after singulation. Semiconductor die124is mounted over semiconductor die188with adhesive layer202, providing a high density of semiconductor die within a small footprint. Semiconductor die124is mechanically and electrically connected to TSV substrate162with bumps134. Conductive layers150and160, and conductive vias146, provide electrical connectivity vertically and horizontally across TSV substrate162. Semiconductor die188is mechanically and electrically connected to TSV substrate186with bumps196. Conductive layers176and184, and conductive vias172, provide electrical connectivity vertically and horizontally across TSV substrate186. Bond wires266electrically connect TSV substrate186to TSV substrate162.

The length of TSV substrate186is less than the length of TSV substrate162to allow clearance for conductive vias286and bond wires266. Semiconductor die124and188, and TSV substrates162and186are disposed within a chase mold and MUF material278is deposited over the assembly. MUF material278is uniformly formed over semiconductor die124and188in a single manufacturing step, eliminating the need to deposit MUF material over each die individually. Conductive vias286are formed through MUF material278to electrically connect TSV substrate162to a common surface291of semiconductor package290. Bumps288are formed over an exposed surface of conductive vias286.

Semiconductor die124is electrically connected through contact pads132, bumps134, TSV substrate162, and conductive vias286to the common surface291of semiconductor package290. Semiconductor die188is electrically connected through bumps196, TSV substrate186and bond wires266to TSV substrate162. Accordingly, TSV substrate162and186, bumps134and196, bond wires266, and conductive vias286form a conductive interconnect structure to provide electrical paths for I/O signals of semiconductor die124and188to the common surface291of semiconductor package290.

FIGS. 10a-10killustrate in relation toFIGS. 1 and 2a-2c, a process of forming a stacked-die semiconductor package with a first semiconductor die electrically connected to a first substrate with wirebonds. InFIG. 10a, continuing fromFIG. 4d, a plurality of semiconductor die298originating from a semiconductor wafer, similar toFIGS. 3a-3c, has a back surface300and an active surface302containing analog or digital circuits implemented as active devices, passive devices, conductive layers, and dielectric layers formed within the die and electrically interconnected according to the electrical design and function of the die. For example the circuit may include one or more transistors, diodes, and other circuit elements formed within active surface302to implement analog circuits or digital circuits, such as DSP, ASIC, memory or other signal processing circuit. Semiconductor die298may also contain IPDs, such as inductors, capacitors, and resistors, for RF signal processing. A plurality of contact pads304is formed on active surface302and electrically connected to the circuits on the active surface. Semiconductor die298is mounted to TSV substrate162, with back surface300oriented toward conductive layer160, using a suitable die attach adhesive.

InFIG. 10b, bond wires308are formed between contact pads304and conductive layer160, providing an electrical connection between contact pads304, bond wires308, conductive layers160and150, and conductive vias146.

InFIG. 10c, a TSV substrate is formed, similar toFIGS. 4a-4d, with substrate layer312and conductive vias314. Insulating layer316and conductive layer318are formed on one side of substrate312and mounted to temporary carrier320with interface layer322. Insulating layer324and conductive layer326are formed on substrate312, on the side opposite insulating layer316, to form TSV substrate328.

InFIG. 10d, a plurality of semiconductor die330originating from a semiconductor wafer, similar toFIGS. 3a-3c, has a back surface332and an active surface334containing analog or digital circuits implemented as active devices, passive devices, conductive layers, and dielectric layers formed within the die and electrically interconnected according to the electrical design and function of the die. For example the circuit may include one or more transistors, diodes, and other circuit elements formed within active surface334to implement analog circuits or digital circuits, such as DSP, ASIC, memory or other signal processing circuit. Semiconductor die330may also contain IPDs, such as inductors, capacitors, and resistors, for RF signal processing. A plurality of contact pads336is formed on active surface334and electrically connected to the circuits on the active surface. A plurality of bumps338is formed over contact pads336.

Each semiconductor die330is mounted to conductive layer326of TSV substrate328using a pick and place operation with active surface334oriented toward the substrate. Bumps338are reflowed to electrically connect conductive layer326of semiconductor die330to conductive layer326of TSV substrate328.FIG. 10eshows semiconductor die330mounted to TSV substrate328.

InFIG. 10f, a portion of TSV substrate328is removed using a saw blade or laser cutting tool340to create gap342between semiconductor die330and extending down to interface layer322. Carrier320provides structural support for TSV substrate328and semiconductor die330during formation of gap342.

InFIG. 10g, an adhesive layer344is formed over active surface302of semiconductor die298. Adhesive layer344can be thermal epoxy, epoxy resin, B-stage epoxy laminating film, UV B-stage film adhesive layer, UV B-stage film adhesive layer including acrylic polymer, thermo-setting adhesive film layer, WIF encapsulant material, suitable wafer backside coating, epoxy resin with organic filler, silica filler, or polymer filler, acrylate based adhesive, epoxy-acrylate adhesive, a PI-based adhesive or other suitable adhesive material. Leading with back surface332, semiconductor die330is mounted to semiconductor die298with adhesive layer344. Adhesive layer344has a sufficient thickness to enable clearance and headroom of bond wires308to electrically connect contact pads304with conductive layer160.

InFIG. 10h, carrier320and interface layer322are removed by chemical etching, mechanical peeling, CMP, mechanical grinding, thermal bake, UV light, laser scanning, or wet stripping to expose insulating layer316and conductive layer318. The assembly fromFIG. 10g, containing semiconductor die298, semiconductor die330, TSV substrate328, TSV substrate162, and bond wires308, is placed in chase mold346. Chase mold346has an upper support mold348and lower support mold350, which are brought together to enclose semiconductor die298, semiconductor die330, TSV substrate328, TSV substrate162, and bond wires308, with open space352. The lower support mold350includes a plurality of openings or gates354for injecting MUF material into open space352.

InFIG. 10i, MUF material356in a liquid state is injected through gates354with nozzles358while an optional vacuum assist360draws pressure from the side of chase mold346to uniformly fill open space352over semiconductor die298, semiconductor die330, TSV substrate328, TSV substrate162, bond wires308and gap342. MUF material356can be an encapsulant, molding compound, polymer composite material, such as epoxy resin with filler, epoxy acrylate with filler, or polymer with proper filler.

InFIG. 10j, semiconductor die298, semiconductor die330, TSV substrate328, TSV substrate162, and bond wires308are removed from chase mold346. A plurality of vias362is formed through MUF material356, outside a footprint of semiconductor die298and230, extending to conductive layer160using laser drilling, mechanical drilling, or DRIE. The sidewalls of vias362can have a tapered, straight, or stepped profile.

An electrically conductive bump material is deposited over conductive layer318of TSV substrate328using an evaporation, electrolytic plating, electroless plating, ball drop, or screen printing process. The bump material can be Al, Sn, Ni, Au, Ag, Pb, Bi, Cu, solder, and combinations thereof, with an optional flux solution. For example, the bump material can be eutectic Sn/Pb, high-lead solder, or lead-free solder. The bump material is bonded to conductive layer318using a suitable attachment or bonding process. In one embodiment, the bump material is reflowed by heating the material above its melting point to form balls or bumps366. In some applications, bumps366are reflowed a second time to improve electrical contact to conductive layer318. A UBM layer can be formed under bumps366. Bumps366can also be compression bonded to conductive layer318. Bumps366represent one type of interconnect structure that can be formed over conductive layer318. The interconnect structure can also use stud bump, micro bump, or other electrical interconnect. In a similar process, an electrically conductive bump material is deposited over conductive vias364, substantially coplanar with bumps366, to form bumps368. The assembly is singulated through gap342, MUF material356and TSV substrate162with saw blade or laser cutting tool370into individual semiconductor packages372.

FIG. 11shows semiconductor package372after singulation. Semiconductor die298is mounted over semiconductor die330with adhesive layer344, providing a high density of semiconductor die within a small footprint. Adhesive layer344has a sufficient thickness to enable clearance and headroom of bond wires308without breaching an upper surface of adhesive layer344contacting semiconductor die188as bond wires308curve to electrically connect contact pads304with conductive layer160. Semiconductor die330is mechanically and electrically connected to TSV substrate328with bumps338. Conductive layers318and326, and conductive vias314provide electrical connectivity vertically and horizontally across TSV substrate328. Semiconductor die298is mechanically connected to TSV substrate162and electrically connected to TSV substrate162with bond wires308. Conductive layers150and160, and conductive vias146, provide electrical connectivity vertically and horizontally across TSV substrate162.

The length of TSV substrate328is less than the length of TSV substrate162to allow clearance for conductive vias364and bond wires308. Semiconductor die330and298, and TSV substrates162and328are disposed within a chase mold and MUF material356is deposited over the assembly. MUF material356is uniformly formed over semiconductor die330and298in a single manufacturing step, eliminating the need to deposit MUF material over each die individually. Conductive vias364are formed through MUF material356to electrically connect TSV substrate162to a common surface374of semiconductor package372. Bumps368are formed over an exposed surface of conductive vias364. Bumps366are formed over conductive layer318of TSV substrate328.

Semiconductor die298is electrically connected through contact pads304, bond wires308, TSV substrate162, and conductive vias364to the common surface374of semiconductor package372. Semiconductor die330is electrically connected through bumps338, and TSV substrate328to the common surface374of semiconductor package372. Accordingly, TSV substrate162and328, bond wires308, bumps338, and conductive vias364form a conductive interconnect structure to provide electrical paths for I/O signals of semiconductor die330and298to the common surface374of semiconductor package372.

FIGS. 12a-12nillustrate, in relation toFIGS. 1and2a-2c, a process of forming a stacked-die semiconductor package with a first substrate having multiple interconnected conductive layers. InFIG. 12a, a temporary substrate or carrier384contains sacrificial base material such as silicon, polymer, beryllium oxide, glass, or other suitable low-cost, rigid material for structural support. An interface layer or double-sided tape386is formed over carrier384as a temporary adhesive bonding film, etch-stop layer, or release layer. A semiconductor wafer or substrate390contains base material, such as silicon, germanium, gallium arsenide, indium phosphide, or silicon carbide, for structural support. As a semiconductor wafer, substrate390can contain embedded integrated semiconductor die or discrete devices. Substrate390can also be a multi-layer flexible laminate, ceramic or leadframe. Substrate390is mounted to interface layer386over carrier384.

InFIG. 12b, a plurality of vias is formed through substrate390using laser drilling, mechanical drilling, DRIE. The vias are filled with Al, Cu, Sn, Ni, Au, Ag, Ti, tungsten W, poly-silicon, or other suitable electrically conductive material using electrolytic plating, electroless plating process, or other suitable metal deposition process to form z-direction vertical interconnect conductive vias392. Substrate390also includes redistribution layers for routing electrical signals horizontally. The resulting wafer-form TSV interposer or substrate396provides electrical interconnect vertically and laterally across the substrate.

InFIG. 12c, a plurality of semiconductor die398originating from a semiconductor wafer, similar toFIGS. 3a-3c, has a back surface400and an active surface402containing analog or digital circuits implemented as active devices, passive devices, conductive layers, and dielectric layers formed within the die and electrically interconnected according to the electrical design and function of the die. For example, the circuit may include one or more transistors, diodes, and other circuit elements formed within active surface402to implement analog circuits or digital circuits, such as DSP, ASIC, memory or other signal processing circuit. Semiconductor die398may also contain IPDs, such as inductors, capacitors, and resistors, for RF signal processing. A plurality of contact pads404is formed on active surface402and electrically connected to the circuits on active surface402. A plurality of bumps406is formed over contact pads404.

Each semiconductor die398is mounted to TSV substrate396using a pick and place operation with active surface402oriented toward the substrate. Bumps406are reflowed to electrically connect semiconductor die398to one or more redistribution layers of TSV substrate396and conductive vias392.FIG. 12dshows semiconductor die398mounted to TSV substrate396.

InFIG. 12e, a TSV substrate is formed, similar toFIGS. 4a-4d, with substrate layer410and conductive vias412. Insulating layer414and conductive layer416are formed on one side of substrate410and mounted to temporary carrier418with interface layer420. Insulating layer422and conductive layer424are formed on substrate410, on the side opposite insulating layer414. The resulting wafer-form TSV interposer or substrate426provides electrical interconnect vertically across the substrate.

InFIG. 12f, a plurality of semiconductor die428originating from a semiconductor wafer, similar toFIGS. 3a-3c, has a back surface430and an active surface432containing analog or digital circuits implemented as active devices, passive devices, conductive layers, and dielectric layers formed within the die and electrically interconnected according to the electrical design and function of the die. For example the circuit may include one or more transistors, diodes, and other circuit elements formed within active surface432to implement analog circuits or digital circuits, such as DSP, ASIC, memory or other signal processing circuit. Semiconductor die428may also contain IPDs, such as inductors, capacitors, and resistors, for RF signal processing. A plurality of contact pads434is formed on active surface432and electrically connected to the circuits on the active surface. A plurality of bumps436is formed over contact pads434.

Each semiconductor die428is mounted to conductive layer424of TSV substrate426using a pick and place operation with active surface432oriented toward the substrate. Bumps436are reflowed to electrically connect semiconductor die428to conductive layer424of TSV substrate426.FIG. 12gshows semiconductor die428mounted to TSV substrate426.

InFIG. 12h, a portion of TSV substrate426is removed using a saw blade or laser cutting tool440to create gap442between semiconductor die428and extending down to interface layer420. Carrier418provides structural support for TSV substrate426and semiconductor die428during formation of gap442.

Semiconductor die428is mounted to semiconductor die398, with adhesive layer444, with back surface430oriented toward back surface400. In another embodiment, adhesive layer444is formed over back surface430of semiconductor die428.

The assembly, containing semiconductor die428, semiconductor die398, TSV substrate396, and TSV substrate426, is placed in chase mold446. Chase mold446has an upper mold support448and lower mold support450, which are brought together to enclose semiconductor die428, semiconductor die398, TSV substrate396, and TSV substrate426with open space452. The lower mold support450includes a plurality of openings or gates454for injecting MUF material into open space452.

InFIG. 12k, MUF material456in a liquid state is injected through gates454with nozzles458while an optional vacuum assist460draws pressure from the side of chase mold446to uniformly fill open space452over semiconductor die398, semiconductor die428, TSV substrate396, TSV substrate426and gap442with MUF material. MUF material456can be an encapsulant, molding compound, polymer composite material, such as epoxy resin with filler, epoxy acrylate with filler, or polymer with proper filler.FIG. 12lshows MUF material456disposed over semiconductor die398, semiconductor die428, TSV substrate396, and TSV substrate426.

InFIG. 12m, semiconductor die398, semiconductor die428, TSV substrate396and TSV substrate426are removed from chase mold446. A plurality of vias462is formed through MUF material456extending to TSV substrate396using laser drilling, mechanical drilling, or DRIE. The sidewalls of vias462can have a tapered, straight, or stepped profile.

InFIG. 12n, vias462are filled with Al, Cu, Sn, Ni, Au, Ag, Ti, W, poly-silicon, or other suitable electrically conductive material using electrolytic plating, electroless plating process, or other suitable metal deposition process to form z-direction vertical interconnect conductive vias464. Conductive vias464electrically connect with one or more redistribution layers and conductive vias392of TSV substrate396.

An electrically conductive bump material is deposited over conductive layer416of TSV substrate426using an evaporation, electrolytic plating, electroless plating, ball drop, or screen printing process. The bump material can be Al, Sn, Ni, Au, Ag, Pb, Bi, Cu, solder, and combinations thereof, with an optional flux solution. For example, the bump material can be eutectic Sn/Pb, high-lead solder, or lead-free solder. The bump material is bonded to conductive layer416using a suitable attachment or bonding process. In one embodiment, the bump material is reflowed by heating the material above its melting point to form balls or bumps466. In some applications, bumps466are reflowed a second time to improve electrical contact to conductive layer416. An under bump metallization layer can be formed under bumps466. Bumps466can also be compression bonded to conductive layer416. Bumps466represent one type of interconnect structure that can be formed over conductive layer416. The interconnect structure can also use stud bump, micro bump, or other electrical interconnect. In a similar process, an electrically conductive bump material is deposited over conductive vias464, substantially coplanar with bumps466, to form bumps468.

The assembly is singulated through MUF material456, gap442, and TSV substrate396, outside a footprint of the periphery of semiconductor die398and428with saw blade or laser cutting tool469into individual integrated dual flipchip semiconductor packages470.

FIG. 13shows semiconductor package470after singulation. Semiconductor die398is mounted over semiconductor die428with adhesive layer444, providing a high density of semiconductor die within a small footprint. Semiconductor die398is mechanically and electrically connected to TSV substrate396with bumps406. TSV substrate396has a plurality of conductive vias390and multiple conductive redistribution layers, providing electrical connectivity vertically and horizontally across TSV substrate396. Semiconductor die428is mechanically and electrically connected to TSV substrate426with bumps436. Conductive layers424and416, and conductive vias412, provide electrical connectivity vertically and horizontally across TSV substrate426.

The length of TSV substrate426is less than the length of TSV substrate396to allow clearance for conductive vias464. Semiconductor die398and428, and TSV substrates426and396are disposed within a chase mold and MUF material456is deposited over the assembly. MUF material456is uniformly formed over semiconductor die398and428in a single manufacturing step, eliminating the need to deposit MUF material over each die individually. Conductive vias464are formed through MUF material456to electrically connect TSV substrate396to a common surface471of semiconductor package470. Bumps468are formed over an exposed surface of conductive vias464. Bumps466are formed over conductive layer416of TSV substrate426.

Semiconductor die398is electrically connected through contact pads404, bumps406, TSV substrate396, and conductive vias464to the common surface471of semiconductor package470. Semiconductor die428is electrically connected through bumps436, and TSV substrate426to the common surface471of semiconductor package470. Accordingly, TSV substrate396and426, bumps406and436, and conductive vias464form a conductive interconnect structure to provide electrical paths for I/O signals of semiconductor die398and428to the common surface471of semiconductor package470.

In another embodiment, shown inFIG. 14, TSV substrate472can contain a silicon substrate layer with z-direction vertical conductive vias480and one or more redistribution layers to provide electrical connections horizontally and vertically across TSV substrate472. TSV substrate482can contain a substrate layer490, vias492, with insulating layer500and conductive layer510opposite insulating layer520and conductive layer530. Conductive layers510and530, and conductive vias492provide electrical connectivity vertically and horizontally across TSV substrate482. Semiconductor die398is mounted over semiconductor die428with adhesive layer444, providing a high density of semiconductor die within a small footprint. Semiconductor die398is mechanically and electrically connected to TSV substrate482with bumps406.

The length of TSV substrate472is less than the length of TSV substrate482to allow clearance for conductive vias534. Semiconductor die398and428, and TSV substrates472and482are disposed within a chase mold and MUF material532is deposited over the assembly. MUF material532is uniformly formed over semiconductor die398and428in a single manufacturing step, eliminating the need to deposit MUF material over each die individually. Conductive vias534are formed through MUF material532to electrically connect TSV substrate482to a common surface540of semiconductor package539. Bumps536are formed over an exposed surface of conductive vias534. Bumps538are formed over conductive vias480of TSV substrate472.

Semiconductor die398is electrically connected through contact pads404, bumps406, TSV substrate482, and conductive vias534to the common surface540of semiconductor package539. Semiconductor die428is electrically connected through bumps436, and TSV substrate472to the common surface540of semiconductor package539. Accordingly, TSV substrate482and472, bumps406and436, and conductive vias534form a conductive interconnect structure to provide electrical paths for I/O signals of semiconductor die398and428to a common surface540of semiconductor package539.

FIGS. 15a-15jillustrate, in relation toFIGS. 1 and 2a-2c, a process of forming a stacked-die semiconductor package with multiple interconnect structures to electrically connect the stacked die to a top and bottom surface of the package. InFIG. 15a, continuing fromFIG. 4c, a plurality of semiconductor die542originating from a semiconductor wafer, similar toFIGS. 3a-3c, has a back surface544and an active surface546containing analog or digital circuits implemented as active devices, passive devices, conductive layers, and dielectric layers formed within the die and electrically interconnected according to the electrical design and function of the die. For example the circuit may include one or more transistors, diodes, and other circuit elements formed within active surface546to implement analog circuits or digital circuits, such as DSP, ASIC, memory or other signal processing circuit. Semiconductor die542may also contain IPDs, such as inductors, capacitors, and resistors, for RF signal processing. A plurality of contact pads548is formed on active surface546and electrically connected to the circuits on the active surface. A plurality of bumps550is formed over contact pads548.

Each semiconductor die542is mounted to conductive layer160of TSV substrate162using a pick and place operation with active surface546oriented toward the substrate. Bumps550are reflowed to electrically connect conductive layer548of semiconductor die542to conductive layer160of TSV substrate162.

InFIG. 15b, a portion of TSV substrate162is removed using a saw blade or laser cutting tool552to create gap554between semiconductor die542and extending down to interface layer156. Carrier154provides structural support for TSV substrate162and semiconductor die542during formation of gap554.

A plurality of semiconductor die558originating from a semiconductor wafer, similar toFIGS. 3a-3c, has a back surface560and an active surface562containing analog or digital circuits implemented as active devices, passive devices, conductive layers, and dielectric layers formed within the die and electrically interconnected according to the electrical design and function of the die. For example the circuit may include one or more transistors, diodes, and other circuit elements formed within active surface562to implement analog circuits or digital circuits, such as DSP, ASIC, memory or other signal processing circuit. Semiconductor die558may also contain IPDs, such as inductors, capacitors, and resistors, for RF signal processing. A plurality of contact pads564is formed on active surface562and electrically connected to the circuits on the active surface. A plurality of bumps566is formed over contact pads564.

The assembly, containing semiconductor die542, semiconductor die558, and TSV substrate162is placed in chase mold570. Chase mold570has an upper mold support572and lower mold support574, which are brought together to enclose semiconductor die542, semiconductor die558, and TSV substrate162with open space576. The lower mold support574includes a plurality of openings or gates578for injecting MUF material into open space576.

InFIG. 15e, MUF material580in a liquid state is injected through gates578with nozzles582while an optional vacuum assist584draws pressure from the side of chase mold570to uniformly fill open space576over semiconductor die558, semiconductor die542, TSV substrate162, and gap554with MUF material580. MUF material580can be an encapsulant, molding compound, polymer composite material, such as epoxy resin with filler, epoxy acrylate with filler, or polymer with proper filler.FIG. 15fshows MUF material580disposed around and between semiconductor die558, semiconductor die542, TSV substrate162, and gap554.

InFIG. 15g, semiconductor die542, semiconductor die558, and TSV substrate162are removed from chase mold570. A plurality of vias586is formed through MUF material580extending to conductive layer160using laser drilling, mechanical drilling, or DRIE. A plurality of second vias588is formed through MUF material580, extending through gap554and creating an opening on the opposite surface of MUF material580. The sidewalls of vias586and588can have a tapered, straight, or stepped profile.

InFIG. 15i, a TSV substrate is formed, similar toFIGS. 4a-4d, with substrate layer594and conductive vias596. Insulating layer598and conductive layer600are formed on one side of substrate594. Insulating layer602and conductive layer604are formed on substrate594, on the side opposite insulating layer598. The resulting wafer-form TSV interposer or substrate606provides electrical interconnect vertically across the substrate. Leading with conductive layer604, TSV substrate606is mounted over the assembly, using a suitable attachment or bonding process, and electrically connected to bumps566, and conductive vias590and592.

An electrically conductive bump material is deposited over conductive layer150of TSV substrate162using an evaporation, electrolytic plating, electroless plating, ball drop, or screen printing process. The bump material can be Al, Sn, Ni, Au, Ag, Pb, Bi, Cu, solder, and combinations thereof, with an optional flux solution. For example, the bump material can be eutectic Sn/Pb, high-lead solder, or lead-free solder. The bump material is bonded to conductive layer150using a suitable attachment or bonding process. In one embodiment, the bump material is reflowed by heating the material above its melting point to form balls or bumps610. In some applications, bumps610are reflowed a second time to improve electrical contact to conductive layer150. A UBM layer can be formed under bumps610. Bumps610can also be compression bonded to conductive layer150. Bumps610represent one type of interconnect structure that can be formed over conductive layer150. The interconnect structure can also use stud bump, micro bump, or other electrical interconnect. In a similar process, an electrically conductive bump material is deposited over conductive vias592, substantially coplanar with bumps610, to form bumps612.

InFIG. 15j, the assembly fromFIG. 15iis singulated through MUF material580, gap554, and TSV substrate606, outside a footprint of semiconductor die558and542, with saw blade or laser cutting tool614into individual integrated dual flipchip semiconductor packages616.

FIG. 16shows semiconductor package616after singulation. Semiconductor die558is mounted over semiconductor die542with adhesive layer556, providing a high density of semiconductor die within a small footprint. Semiconductor die558is mechanically and electrically connected to TSV substrate606with bumps566. Conductive layers604and600, and conductive vias596, provide electrical connectivity vertically and horizontally across TSV substrate606. Semiconductor die542is mechanically and electrically connected to TSV substrate162with bumps550. Conductive layers150and160, and conductive vias146, provide electrical connectivity vertically and horizontally across TSV substrate162.

The length of TSV substrate162is less than the length of TSV substrate606to allow clearance for conductive vias592. Semiconductor die542and558, and TSV substrate162are disposed within a chase mold and MUF material580is deposited over the assembly. MUF material580is uniformly formed over semiconductor die542and558in a single manufacturing step, eliminating the need to deposit MUF material over each die individually. Conductive vias590and592are formed through MUF material580. TSV substrate606is mechanically and electrically connected to conductive vias590and592. Conductive vias590electrically connect TSV substrate606to TSV substrate162. Conductive vias592extend from TSV substrate606to a common surface618of semiconductor package616. Bumps612are formed over an exposed surface of conductive vias592. Bumps610are formed over conductive layer150of TSV substrate162.

Semiconductor die558is electrically connected through contact pads564, bumps566, TSV substrate606, and conductive vias592to the common surface618of semiconductor package616. Semiconductor die542is electrically connected through bumps550, and TSV substrate162to the common surface618of semiconductor package616. Conductive vias590electrically connect TSV substrate606to TSV substrate162. Accordingly, TSV substrate162and606, bumps566and550, and conductive vias590and592form a conductive interconnect structure to provide electrical paths for I/O signals of semiconductor die558and542to a common surface618of semiconductor package616.

FIGS. 17a-17rillustrate, in relation toFIGS. 1 and 2a-2c, a process of forming a stacked-die semiconductor package with multiple interconnect structures through an encapsulant to provide electrical connectivity between the die and multiple substrates. InFIG. 17a, continuing fromFIG. 4j, an adhesive layer622is formed over back surface190of semiconductor die188. Adhesive layer622can be thermal epoxy, epoxy resin, B-stage epoxy laminating film, UV B-stage film adhesive layer, UV B-stage film adhesive layer including acrylic polymer, thermo-setting adhesive film layer, WIF encapsulant material, suitable wafer backside coating, epoxy resin with organic filler, silica filler, or polymer filler, acrylate based adhesive, epoxy-acrylate adhesive, a PI-based adhesive or other suitable adhesive material.

InFIG. 17b, carrier178and interface layer180are removed by chemical etching, mechanical peeling, CMP, mechanical grinding, thermal bake, UV light, laser scanning, or wet stripping to expose insulating layer174and conductive layer176. TSV substrate186and semiconductor die188are placed in chase mold630. Chase mold630has an upper mold support632and lower mold support634, which are brought together to enclose semiconductor die188and TSV substrate186with open space636. The lower mold support634includes a plurality of openings or gates638for injecting MUF material into open space636.

InFIG. 17c, MUF material640in a liquid state is injected through gates638with nozzles642while an optional vacuum assist644draws pressure from the side of chase mold630to uniformly fill open space636around semiconductor die188, TSV substrate186, and gap200with MUF material. MUF material640can be an encapsulant, molding compound, polymer composite material, such as epoxy resin with filler, epoxy acrylate with filler, or polymer with proper filler.FIG. 17dshows MUF material640disposed around and between semiconductor die188, TSV substrate186, and gap200.

InFIG. 17e, semiconductor die188, and TSV substrate186are removed from chase mold630. A plurality of vias646is formed through MUF material640extending to conductive layer184of TSV substrate186using laser drilling, mechanical drilling, or DRIE. The sidewalls of vias646can have a tapered, straight, or stepped profile.

InFIG. 17g, a TSV substrate is formed, similar toFIGS. 4a-4d, with substrate layer650and conductive vias652. Insulating layer654and conductive layer656are formed on one side of substrate650and mounted to temporary carrier658with interface layer660. Insulating layer662and conductive layer664are formed on substrate650, on the side opposite insulating layer654. The resulting wafer-form TSV interposer or substrate666provides electrical interconnect vertically across the substrate.

InFIG. 17h, a portion of TSV substrate666is removed using a saw blade or laser cutting tool668to create gap670extending down to interface layer660. Carrier658provides structural support for TSV substrate666during formation of gap670.

InFIG. 17k, a plurality of semiconductor die680originating from a semiconductor wafer, similar toFIGS. 3a-3c, has a back surface682and an active surface684containing analog or digital circuits implemented as active devices, passive devices, conductive layers, and dielectric layers formed within the die and electrically interconnected according to the electrical design and function of the die. For example, the circuit may include one or more transistors, diodes, and other circuit elements formed within active surface684to implement analog circuits or digital circuits, such as DSP, ASIC, memory or other signal processing circuit. Semiconductor die680may also contain IPDs, such as inductors, capacitors, and resistors, for RF signal processing. A plurality of contact pads686is formed on active surface684and electrically connected to the circuits on the active surface. A plurality of bumps688is formed over contact pads686.

An adhesive layer690is formed over back surface682of semiconductor die680. Adhesive layer690can be thermal epoxy, epoxy resin, B-stage epoxy laminating film, UV B-stage film adhesive layer, UV B-stage film adhesive layer including acrylic polymer, thermo-setting adhesive film layer, WIF encapsulant material, suitable wafer backside coating, epoxy resin with organic filler, silica filler, or polymer filler, acrylate based adhesive, epoxy-acrylate adhesive, a PI-based adhesive or other suitable adhesive material. Leading with back surface682, each semiconductor die680is mounted to TSV substrate666with adhesive layer690, on the side of TSV substrate666opposite semiconductor die188.

InFIG. 17l, the assembly, containing TSV substrate186and666, and semiconductor die680and188, is placed in chase mold694. Chase mold694has an upper mold support696and lower mold support698, which are brought together to enclose semiconductor die188, semiconductor die680, TSV substrate186, and TSV substrate666with open space700. The lower mold support698includes a plurality of openings or gates702for injecting MUF material into open space700.

InFIG. 17m, MUF material712in a liquid state is injected through gates702with nozzles714while an optional vacuum assist716draws pressure from the side of chase mold694to uniformly fill open space700over the assembly. MUF material712can be an encapsulant, molding compound, polymer composite material, such as epoxy resin with filler, epoxy acrylate with filler, or polymer with proper filler.FIG. 17nshows MUF material712disposed around semiconductor die188, TSV substrate186, and TSV substrate666.

InFIG. 17o, the assembly fromFIG. 17o, comprising semiconductor die188and680, TSV substrate186, and TSV substrate666, is removed from chase mold694. A plurality of vias718is formed through MUF material712extending to conductive layer656using laser drilling, mechanical drilling, or DRIE. Similarly, a plurality of vias720is formed through MUF material712and640, extending through gap670and gap200. Vias718and720can have a tapered, straight, or stepped profile.

An electrically conductive bump material is deposited over conductive layer176of TSV substrate186using an evaporation, electrolytic plating, electroless plating, ball drop, or screen printing process. The bump material can be Al, Sn, Ni, Au, Ag, Pb, Bi, Cu, solder, and combinations thereof, with an optional flux solution. For example, the bump material can be eutectic Sn/Pb, high-lead solder, or lead-free solder. The bump material is bonded to conductive layer176using a suitable attachment or bonding process. In one embodiment, the bump material is reflowed by heating the material above its melting point to form balls or bumps730. In some applications, bumps730are reflowed a second time to improve electrical contact to conductive layer176. A UBM layer can be formed under bumps730. Bumps730can also be compression bonded to conductive layer176. Bumps730represent one type of interconnect structure that can be formed over conductive layer176. The interconnect structure can also use stud bump, micro bump, or other electrical interconnect. In a similar process, an electrically conductive bump material is deposited over conductive vias724, coplanar with bumps730, to form bumps732.

InFIG. 17r, the assembly fromFIG. 17ris singulated through TSV substrate162, and gaps670and200, outside a footprint of semiconductor die680and188, with saw blade or laser cutting tool734into individual semiconductor packages736.

FIG. 18shows semiconductor package736after singulation. Semiconductor die680is mounted over TSV substrate666with adhesive layer690, and semiconductor die188is mounted over an opposing surface of TSV substrate666with adhesive layer622, providing a high density of semiconductor die within a small footprint. Semiconductor die680is mechanically and electrically connected to TSV substrate162with bumps688. Conductive layers150and160, and conductive vias146provide electrical connectivity vertically and horizontally across TSV substrate162. Semiconductor die188is mechanically and electrically connected to TSV substrate186with bumps196. Conductive layers176and184, and conductive vias172, provide electrical connectivity vertically and horizontally across TSV substrate186.

The length of TSV substrates186and666is less than the length of TSV substrate162to allow clearance for conductive vias724. MUF material640is deposited over semiconductor die188and TSV substrate186in a chase mold. In a separate process, MUF material712is deposited over semiconductor die680and188, and TSV substrates666and186. Conductive vias648are formed through MUF material640to electrically connect TSV substrate186to TSV substrate666. Conductive vias722are formed through MUF material712to electrically connect TSV substrate162to TSV substrate666. Conductive vias724are formed through MUF material712to electrically connect TSV substrate162to a common surface738of semiconductor package736. Bumps732are formed over an exposed surface of conductive vias724. Bumps730are formed over conductive layer176of TSV substrate186.