Spin transfer torque triad for non-volatile logic gates

A non-volatile logic gate, including a magnetic material having a shape induced magnetic anisotropy, wherein a shape of the magnetic material has a first vertex, a second vertex, and a third vertex and supports a single magnetic domain; regions of the magnetic material including a first input region adjacent the first vertex, a second input region adjacent the second vertex, and an output region adjacent a third vertex; the first input region for receiving a first logic input to the logic gate, the second input region for receiving a second logic input to the logic gate, and the output region for outputting at least one logic output of the logic gate; and the shape induced magnetic anisotropy determining at least part of a truth table for the logic gate, so that the logic gate produces the at least one logic output from the logic inputs using the shape.

BACKGROUND OF THE INVENTION

1. Field of the Invention

This invention relates to logic gates, digital electronics for signal processing, storage and computation, and methods of fabricating the same.

2. Description of the Related Art

(Note: This application references a number of different publications as indicated throughout the specification by one or more reference numbers within brackets, e.g., [x]. A list of these different publications ordered according to these reference numbers can be found below in the section entitled “References.” Each of these publications is incorporated by reference herein.)

Spin Transfer Torque (STT) devices and spin valves are well documented in the literature. A spin valve device comprises a first conductive magnetic layer (fixed layer) and a second conductive magnetic layer (free layer), separated by a spacer layer, wherein the fixed layer, free layer, and spacer layers produce a device that exhibits Giant Magneto Resistance (GMR). The orientation of the magnetic moments in the fixed layer are fixed or pinned while the orientation of the magnetic moments in the free layer are not fixed and are consequently free to rotate in response to magnetic fields.

According to the GMR effect, when the magnetic moments in the fixed layer and the free layer are aligned (or parallel and pointing in the same direction), the device exhibits much smaller resistance as compared to when the magnetic moments in the fixed layer and the free layer are not aligned (or are anti parallel and pointing in the opposite direction).

Accordingly, if the magnetization orientation in the free layer is initially aligned with the magnetization orientation in the fixed layer (due to the weak spin coupling provided by the spacer layer), a magnetic field passing near the free layer may re-orient the magnetization orientation of the free layer with respect to the magnetization orientation of the fixed layer, causing a large change in resistance of the spin valve due to the GMR effect, which is sensed by current passing between the fixed layer and the free layer. Such an implementation is used as a read head sensor for hard drives, for example [1].

The GMR effect is also exploited for Magnetic Random Access Memory (MRAM). In the early MRAM the free layer magnetization reorientation was performed by applying a magnetic field generated by current in a write line: the state of the memory element is read by sensing the resistance via the GMR effect. More recently the spin transfer torque (STT) effect is used to write the magnetization state of the free layer [2-4]. An STT device (STTD) is a three layer device comprising a first, fixed, ferromagnetic metallic layer and a free, second, metallic, ferromagnetic layer separated from the first by a thin conductor or an insulator thin enough to allow electron tunneling. A spin polarized current (a current comprising electrons having predominantly one spin orientation) will reorient the free layer to be parallel or anti parallel as the electrons flow from the fixed to the free layer or from the free to fixed layer, respectively. In this way the relative magnetization orientation of the two layers can be “written” and “read” by suitable current flow through the STT device. Large currents are used to write (STT effect); small currents to sense the resistance (GMR effect).

The first and second layers of the STT device do not require power to retain their relative magnetization orientations, and therefore such a memory implementation is non-volatile—i.e., the data or information remains stored when the power to the device is switched off.

However, conventional magnetic memories or devices (e.g., MRAM) that are used to replace solid state memories such as Dynamic Random Access Memory (DRAM), Static Random Access Memory (SRAM), and flash memory, are not capable of executing logic. Instead, conventional devices use the transistor (e.g., CMOS) to perform logic operations. Replacing some transistors in the logic device with a patterned magnetic material may reduce the device size and cause such a device to be faster and cheaper.

Thus, there is a need for magnetic devices to perform logic operation in addition to being able to store information in a non-volatile way. The present invention satisfies this need by extending the capability of magnetic devices and adding logic operation to magnetic memory elements.

SUMMARY OF THE INVENTION

One or more embodiments of the present invention comprise connecting STT-MRAM to a single domain nanoscale magnet in order to execute a logic function, and using the STT-MRAM to both read from and write to the single domain nanoscale magnet.

Thus, to overcome the limitations in the prior art, and to overcome other limitations that will become apparent upon reading and understanding the present specification, the present invention discloses a non-volatile logic gate, comprising a magnetic material having a shape induced magnetic anisotropy, wherein the shape of the magnetic material has a first vertex, a second vertex, and a third vertex and supports a single magnetic domain; regions of the magnetic material including a first input region adjacent the first vertex, a second input region adjacent the second vertex, and an output region adjacent a third vertex; the first input region for receiving a first logic input to the logic gate, the second input region for receiving a second logic input to the logic gate, and the output region for outputting at least one logic output of the logic gate; and the shape induced magnetic anisotropy determining at least part of a truth table for the logic gate, so that the logic gate produces the at least one logic output from the logic inputs using the shape.

The role of the shape is to induce the magnetic anisotropy which define the magnetic states of the shaped magnet. In the present invention, the triangular shape introduces the magnetic anisotropy which defines the spin-ice like magnetic ground states of the magnet. However, other shapes may be used that introduce the magnetic shape anisotropy.

The present invention is not limited to any particular dimension of the ferromagnet, so long as the ferromagnet supports a single magnetic domain.

The magnetic material may be a ferromagnet at a temperature of operation of the logic gate.

The shape induced magnetic anisotropy is such that the truth table defines the logic gate as a NAND gate or a NOR gate. For example, the shape may be a triangle (e.g., isosceles, scalene, or equilateral triangle). Alternatively, the shape may have curved sides (e.g., concave sides) connecting the vertices.

The shape, and shape induced magnetic anisotropy, impart bistability to the logic gate that enables the logic gate to be initialized as either a NAND gate or a NOR gate.

The shape, and shape induced magnetic anisotropy, may be such that local magnetization alignments at each of the vertices obey the spin ice rule [5-6].

The first input region, the second input region, and the output region may, may or may not, be electrically isolated from each other.

The first input region may have a first local magnetization alignment defined by the first logic input, the second input region may have a second local magnetization alignment defined by the second logic input, and the output region may have a third output magnetization alignment that defines the logic output and which is initialized to define the logic gate as the NAND gate or the NOR gate. The shape and shape induced magnetic anisotropy may be such that there are exactly six energy equivalent combinations for the directions of the first local magnetization alignment, the second magnetization alignment, and the output local magnetization alignment. The shape and shape induced magnetic anisotropy may be such that two of the local magnetizations are aligned to point away from their respective vertices and one of the local magnetizations is aligned to point towards its respective vertex, or one of the local magnetizations is aligned to point away from its respective vertex and two of the local magnetizations are aligned to point towards their respective vertices.

The logic gate may produce the at least one logic output from the logic inputs using the shape induced magnetic anisotropy when (1) the logic inputs include concurrent writing pulses that switch the first local magnetization and the second local magnetization, wherein a positive writing pulse represents logic state “1” and a negative writing pulse represents logic state “0”; and (2) the output region receives initialization pulses that align the third output magnetization (selecting one of the bistable ground states of the ferromagnet) to initialize the logic gate as a NOR gate or NAND gate, each time the logic gate receives the writing pulses. The initialization pulses begin either earlier or concurrently with the writing pulses, and the initialization pulse should end before the trailing edge of the writing pulses so that the logic gate is initialized by a trailing edge of the initialization pulse.

In one or more embodiments, the initialization pulses may be positive to achieve a NAND gate, or the initialization pulses may be negative to achieve a NOR gate.

The logic gate may further comprise a Spin Transfer Torque (STT) Triad including a first fixed layer, a second fixed layer, and a third fixed layer coupled by a single free layer, wherein the single free layer is the magnetic material; and one or more spacer layers separating the fixed layers from the free layer such that the fixed layers are electrically coupled to the free layer.

The logic gate may further comprise (a) the first fixed layer providing the first logic input that orients the first local magnetization so as to point the first local magnetization alignment in a direction towards or away from the first vertex, (b) the second fixed layer providing the second logic input that orients the second local magnetization alignment so as to point the second local magnetization alignment in a direction towards or away from the second vertex, and (c) the third fixed layer providing an initialization pulse that orients the third local magnetization alignment so as to point the third local magnetization alignment in a direction towards or away from the third vertex to define the truth table that defines the logic gate as a NAND gate or a NOR gate.

The third fixed layer may be positioned to read the logic output using the GMR effect.

However, in other embodiments, instead of the fixed layers, the magnetizations may be aligned by a multiferroic element.

The towards direction of the magnetization alignment may indicate a logical state “0,” the away direction may indicate a logical state “1,” and the logic output is typically bistable when one of the logic inputs is “1” and the other of the logic inputs is “0”. The third fixed layer then re-writes the logic output to “1” when the logic output is bistable, so that the logic inputs and logic output satisfy NAND gate logic, or the third fixed layer re-writes the logic output to “0” when the logic output is bistable, so that the logic inputs and logic output satisfy NOR gate logic.

The present invention further discloses a plurality of the logic gates. A bipolar transistor or a CMOS pair connected to the STT triad output provides a fan out of the output, where one STT triad output may drive any number of other STT triad inputs. The STT triad may comprise any NAND or NOR element based logic circuit (e.g. 1-bit full adder).

DETAILED DESCRIPTION OF THE INVENTION

Overview

One concept of the present invention is the separation of the read and write functions of the STT-MRAM, and connection of STT-MRAMs by a shared single domain magnet, thereby achieving non-volatile logic.

Strong shape induced magnetic anisotropy defines six different magnetization alignment ground states of a single domain ferromagnetic triangle. Local magnetization direction at the triangle vertices defines logical “0”, pointing inwards, and logical “1” pointing outwards, from the vertices of the triangle. The present invention defines one vertex as the output and the other two vertices as inputs.

By controlling local magnetization alignment of two inputs, one of the triangle magnetic ground states is defined, with corresponding magnetization alignment of the third vertex, which serves as an output.

Each of the triad inputs may be controlled by a spin transfer torque device (STTD), or multiferroic cell (MC) driven by 2 transistors, for example. For input states (1, 1) and (0, 0), the output is 0 and 1, respectively. (1, 0) and (0, 1) input states result in the bi-stable output of either 0 or 1.

Current (voltage) initialization pulses clocked through the STTD placed over the output vertex, before or simultaneously with writing the inputs, so that the initialization pulse ends before the trailing edge of the write pulses, define the output to be “1” for all input combinations except (1,1) (which results in “0”), and therefore the logic gate exhibits NAND logical operation. In another embodiment, the output may be defined to be “0” for all input combinations except (0,0) (which results in “1”), so that the logic gate exhibits NOR gate logical operation.

The magnetoresistance effect in the STTD is used to read the output state, and also used to drive the input of the next triad in the logic circuit. The magnetization states are stable in time, and therefore the triad has “write” and “store” phases of operation. The triad device acts as a logic gate during the “write” phase, and as a memory element during the “store” phase. While the write time is defined by the STTD, the “store” phase is not limited in time. The triad device does not consume energy during the “store” phase.

TECHNICAL DESCRIPTION

Integrating magnetic elements into electronic circuits significantly expands the device capabilities by making them non-volatile. Non-volatile logic does not lose information when the power is turned off, does not require energy to store the information, and continues operation when the circuit is powered on again without an initialization process.

Switching between the triad ground states has been demonstrated by micromagnetic simulations.

Ground States of the Single Domain Ferromagnet

FIG. 1(a) shows a triangular shaped nanoscale ferromagnet100, dominated by shape induced magnetic anisotropy, that may serve as a non-volatile NAND gate. Small enough to support a single domain, the local magnetizations of the isolated triangle may be found in six different configurations, one of which is shown inFIG. 1(a). Each magnetization alignment state is characterized by one of vertices102having the local magnetization104directed toward (or away from) that vertex102while the two other vertices106,108have their local magnetizations110,112directed away from (or towards) their respective vertices106,108. Inputs to the logic gate are at vertices A and B of the ferromagnet100, and the output from the logic gate is at vertex C of the ferromagnet100.

FIGS. 1(b)-(g) show all 6 possible magnetization alignment ground states for the triangle shaped nanoscale ferromagnet100, defined by the spin ice rule [5-6] wherein each ground state represents one of the possible logic states of the logic gate according to the present invention. The ferromagnet100has a triangular shape114having a side length116of less than 150 nm, or a size (e.g., area) that supports a single magnetic domain.

If the present invention defines a “1” as the local magnetization alignment110pointing away from a vertex106(inward), and “0” as the local magnetization alignment104pointing towards vertex102(outward), then the 6 magnetization alignment ground states enable NAND or NOR gate logic, as shown in Table 1 below.

Table 1 tabulates the 6 ground magnetization alignment ground states of the ferromagnet100when a first input to the logic gate defines a magnetization alignment at vertex A (hereinafter input A) and a second input to the logic gate defines a magnetization alignment at vertex B (hereinafter input B), wherein the magnetization alignment at vertex C (hereinafter output C) is determined from input A and B according to the spin ice rule and the logic output of the logic gate is also read from output C.

Table 1 shows that when input A is “0” and input B is “1”, or when input A is “1” and input B is “0”, the output at vertex C is bistable (i.e., “0” or “1”). This bistability allows the ferromagnet100to act as a NAND gate or a NOR gate. For NAND gate operation, the bistable ferromagnet output at vertex C is initialized or written to “1” when input A is “0” and input B is “1”, and when input A is “1” and input B is “0”. For NOR gate operation, the bistable ferromagnet output at vertex C is written or initialized to “0” when input A is “0” and input B is “1”, and when input A is “1” and input B is “0”.

FIG. 2(a) is a top view schematic of an STT triad200comprising three fixed layers202,204,206(in three STTDs or STT diodes) coupled by a single domain ferromagnet208(free layer). The STT triad200implements a scalable non-volatile logic gate and memory element. The ferromagnet208has a shape that is a triangle having three vertices A, B, and C. A first input to the logic gate is at vertex A (input A), a second input to the logic gate is at vertex B (input B), and an output of the logic gate is at vertex C (output C). The local magnetization alignment210,212at the inputs A, B, and the triangular shape, cause a local magnetization alignment214at the output C, thereby demonstrating triad operation.

The free layer208has two input regions216,218adjacent or in proximity to the vertices A, B, respectively, and an output region220adjacent or in proximity to the output vertex C, wherein the input regions216,218and output region220are electrically isolated from each other by one or more electrical gaps, spatial separation, or because the regions216-220do not overlap, for example. The input regions216,218and output region220have the local magnetization alignments210,212and214towards or away from the vertices A, B, C, respectively.

The first fixed layer202is positioned on or above input region216at vertex A, the second fixed layer204is positioned on or above input region218at vertex B, and the third fixed layer206is positioned on or above output region220at vertex C of the ferromagnet208, wherein (a) the first fixed layer202orients the first local magnetization alignment210so as to point the first local magnetization alignment210in a direction towards or away from the first vertex A, (b) the second fixed layer204orients the second local magnetization alignment212so as to point the second local magnetization alignment212in a direction towards or away from the second vertex B, and (c) the third fixed layer206orients a third local magnetization alignment214so as to point the third local magnetization alignment214in a direction towards or away from the third vertex C to initialize the logic gate as a NAND or NOR logic gate. The third fixed layer206also reads the logic output from the third local magnetization alignment214using the GMR effect.

Thus, the STT triad200may comprise three STTDs and a single domain magnet208, wherein each of the STTDs comprises a fixed layer (e.g.,202,204, or206) and a portion (e.g.,216,218, or220) under the fixed layer202,204,206. The three STTDs may be coupled by the single domain magnet208.

In one embodiment, each of the fixed layers202-206are synthetic antiferromagnets comprising two magnetically coupled ferromagnetic layers222,224having fixed and antiparallel magnetic orientations226and228, as shown inFIG. 2(b) [7]. One of the magnetically coupled layers222is a CoFe layer and the other magnetically coupled layer224is a CoFeB layer. The magnetically coupled layers222and224are separated and coupled by a Ruthenium (Ru) layer230.FIG. 2(b) also shows the free layer ferromagnet208that is a CoFeB layer. The CoFeB ferromagnet208is separated from the ferromagnetic layers222,224of the synthetic antiferromagnet by an MgO spacer layer232. The scale234inFIG. 2(b) is 1 nm. Thus,FIG. 2(b) is a cross-section of the STT triad200at the location of the fixed layers202-206.

The STTDs comprising fixed layers202-206may be about 100 nanometers (nm) in diameter or less. For example 10-20 nm diameter STT pillars comprising layers202-206may be positioned on the triangular free layer208, wherein the triangular free layer208may have a side that is 50 nm long. The size of the STTDs may scale with the triangular free layer's208dimensions. However, the present invention is not limited to any particular dimensions for the STTDs comprising fixed layers202-206, the free layer208, or the STTD triad200.

STT triads200may be connected together.FIG. 2(c) is a top view schematic of two single domain ferromagnets208,236integrated with a CMOS pair of transistors238. In the second ferromagnet236, inputs are at vertices A′ and B′ (input A′ and input B′), and the output is at vertex C′ of the triangle (output C′). The circuit connection (using transistors238) is between the output C of the first ferromagnet208and one of the inputs A′ of the second ferromagnet236, although other circuit connections are possible.

FIG. 2(d) is a side-view ofFIG. 2(c), showing the second STT triad240comprises fixed layers242and the STT triads200,240may have one or more electrical gaps244to electrically isolate the input regions216,218and output region220.

FIG. 2(c) andFIG. 2(d) also show clocking of the ferromagnet(s)208. Each vertex A,B,C, A′,B′,C′ of each STT triad208,240is clocked using clocking pulses through fixed layer (e.g.,202-206) deposited on input regions216-220at the vertices A-C. The logic state “0” or “1” is supplied or clocked by pulsed voltages VDD+and VSS−that produce a current through the STTD that reorients the magnetization alignments210,212and214of the free layer208with respect to the fixed layers202-206. Specifically, it is the direction of the current flow between each of the fixed layers202-206and the free layer208that fixes the magnetization alignment210,212,214of free layer208with respect to each of the fixed layers202-206. For example, a spin polarized current (a current comprising electrons having predominantly one spin orientation) reorients the free layer's208local magnetization alignment210to be parallel or anti parallel to the fixed layer's224magnetization228as the electrons in the spin polarized current flow from the fixed layer202to the input region216of free layer208, or from the input region216of free layer208to fixed layer202, respectively. Similarly, spin polarized current reorients local magnetization alignment212in input region218to be parallel or anti parallel to the fixed layer's224magnetization alignment228, as current flows between input region218and fixed layer204, and spin polarized current reorients or reads local magnetization alignment214in output region220as parallel or anti parallel to the fixed layer's224magnetization alignment228as current flows between output region220and fixed layer206.

Logic state “1” is represented by the local magnetization alignments210,212,214pointing away or outwards from vertices A, B, C, respectively, and logic state “0” is represented by the local magnetization210,212,214pointing inwards or towards vertices A, B, or C, respectively.

According to the ground states of the ferromagnet100,208, the output vertex C is “1” if (A,B)=(0,0) (as shown inFIG. 1(g)) and the vertex C is “0” if (A,B)=(1,1) (as shown inFIG. 1(b)). In both these cases ((A,B)=(0,0) or (1,1)), the internal fields (e.g., local magnetization alignment214) overcome the output clock pulses from the fixed layers212.

However, if (A,B)=(0,1) or (1,0), the output C appears ambiguous or bistable. Specifically, there are two ground states representing (A,B)=(0,1), one giving output “1” and the other output “0” (seeFIGS. 1(d) and1(c)), and two ground states representing (A,B)=(1,0), one giving output “1” and the other output “0” (seeFIGS. 1(f) and1(e)).

The bistability allows the present invention to achieve logic NAND or logic NOR by initializing the orientation of magnetization alignment214at the output vertex C. Specifically, this ambiguity or bistability is relieved during clocking of positive supply voltage VDD+and negative supply voltage VSS−to the output vertex C. For NAND gate operation, vertex C is clocked to “1” unless the inputs (A,B)=(1,1). For (A,B)=(1,1) or (0,0), the internal fields214is sufficient to overcome the reset pulse at the output vertex C and the output vertex is set to “0” or “1”, according toFIGS. 1(b) and1(g).

For a NOR gate implementation, the opposite initialization is used: vertex C is clocked to “0” unless the inputs (A,B)=(1,1).

In the quiescent state no power is drawn in the ferromagnet208. During a single clock cycle, the ferromagnet208,236is energized and the state of the ferromagnet208,236is switched. At the same time, a transistor238pair is clocked on, and the appropriate current is delivered to the next stage STTD242at input vertex A′ of ferromagnet236. The current to the next stage244is determined by the limiting resistor Rc, and fan-out is limited only by the current drive that can be delivered by the transistor238pair. When the resistance of the output spin torque device (comprising fixed layer206, free layer region220, and spacer (e.g.,232) between the free layer region220and fixed layer206) is greater than, or less than, the resistance of load resistor RL, the CMOS pair238draws current in the fixed layer of STTD242in the positive or negative direction respectively, reorienting the magnetization alignment246of the free layer236near the vertex A′ of the next triad STTD240, as shown inFIG. 2(d).

Timing Scheme

FIG. 3is a graph illustrating the timing of the clocking pulses300,302, and304to obtain the NAND gate of the present invention. The logic gate (ferromagnet100,208) produces at least one logic output from the logic inputs using the shape induced magnetic anisotropy when the logic inputs include concurrent writing pulses300,302(STT current pulses) to switch the magnetization alignments MAand MB(magnetization switching) in each of the input regions216and218, wherein a positive writing pulse306represents logic state “1” and a negative writing pulse308represents logic state “0”. The output region receives initialization pulses304to align the output magnetization Mout(selecting one of the bistable ground states illustrated inFIGS. 1(c),(d),(e) and (f)) in the output region220and initialize the logic gate as a NOR gate or NAND gate. The initialization pulses304are received by the output region each time the logic gate receives the writing pulses300-302. The initialization pulses304may begin at a same time as the writing pulses300-302, are shorter than the writing pulses300-302, and the magnetization alignment Moutin the output region220is initialized by a trailing edge of the initialization pulses304. Alternatively, the initialization pulses304can initialize the output before the writing pulses300-302are clocked—the triad then will stay initialized until the inputs are written.

When the initialization pulses304are positive, the logic gate is a NAND gate. However, when the initialization pulses304are negative, the logic gate is a NOR gate. The write phases310(shaded region) may comprise a short˜1 nanosecond (ns) long pulse300, and the triad relaxation is scalable with triad dimensions—for a 50 nm side triad, the relaxation time may be 150 picoseconds (ps). During the store phases312(white regions), the triad stores the input and output states with no time limit and with no energy consumption.

ADVANTAGES AND IMPROVEMENTS

The present invention adds non-volatility to the existing logic devices and logic operation capability to the memory capability of magnetic devices. This leads to lower power consumption, better scalability, and non volatility. Using STT to implement logic as well as store information, replaces and reduces the transistor count.

Features of this STTD triad and transistor238pair include:

1. Integrated logic and memory.

2. Easy implementation in existing technology, using e.g., sputter deposited magnetic films and lithography for patterning.

3. The triad is non-volatile and is energized from the power off state by pulsing VDDand VSS. There is no power dissipation in the quiescent state.

4. Micro-magnetic simulations indicate that the relaxation of the STT triad free layer to one of its ground states is faster than state-of-the-art STT junctions.

5. The power and/or energy per operation and time per operation of this nonvolatile logic is determined essentially by switching power of the STTD.

Possible Modifications and Variations

FIG. 4shows an embodiment wherein the shape does not have straight sides400connecting the vertices A, B, C.

Switching the input states of the ferromagnet208can also be performed by other means, for example, by using exchange bias coupling to multiferroic (MC) elements500on triad vertexes A-C, as shown inFIG. 5. The difference between the spin torque based and multiferroics based triad, is that the former uses current for switching, while the latter uses voltage V. A voltage V applied to the MC element500orients the magnetization502of the MC element which in turn orients the magnetization alignment210in the free layer208. While the latter (MC element) has a power advantage, the former (STTD) would probably have a performance advantage because of the faster triad200input switching time (1 ns).

Process Steps

FIG. 6is a flowchart illustrating a method of fabricating a non-volatile logic gate, comprising a magnetic material. The method may comprise the following steps (referring also toFIGS. 1(a)-(g),FIGS. 2(a)-(d)),FIGS. 3-4.

Block600represents selecting the magnetic material, and defining or shaping the magnetic material into a shape that induces magnetic anisotropy in the magnetic material, wherein the shape has a first vertex A, a second vertex B, and a third vertex C, and supports or provides a single magnetic domain.

The magnetic material may be a ferromagnet or ferrimagnet at a temperature of operation of the logic gate, for example. Materials for the ferromagnet include, but are not limited to, Iron/Cobalt, permalloy (Ni/Fe), or CoTaZr. The magnetic material is typically metallic/conducting.

The step may comprise defining a size of the magnetic material (e.g., dimensions116and/or area of the triangle) that supports the single magnetic domain.

The shape may be a triangle, e.g., an isosceles, equilateral, or scalene triangle, for example. In other embodiments, the shape may not have straight sides (e.g., may have curved sides400) connecting the vertices A, B, C. The curved sides may be concave, for example.

The shape induced magnetic anisotropy may determine at least part of a truth table for the logic gate, so that the logic gate produces the at least one logic output from the logic inputs using the shape. The shape may be such that the truth table describes NAND gate logic or NOR gate logic for the logic gate.

The shape may be such that local magnetization alignments210,212,214at each of the vertices obey the spin ice rule.

Bistability allows NAND or NOR operation depending on initialization or definition of the output of the logic gate. The shape geometrically frustrates the magnetic material so that a magnetization alignment214at the third vertex C is bistable when one of the logic inputs is “0” and the other of the logic inputs is “1”, enabling the logic gate to be initialized as either a NAND gate or a NOR gate.

Block602represents defining regions of the magnetic material including a first input region216adjacent or proximate to the first vertex A, a second input region218adjacent or proximate to the second vertex B, and an output region220adjacent or proximate to the third vertex C, wherein the first input region216is for receiving a first logic input (e.g., logical “0” or “1”) to the logic gate, the second input region218is for receiving a second logic input (e.g., logical “0” or “1”) to the logic gate, and the output region220is for outputting at least one logic output (e.g., logical “0” or “1”) of the logic gate.

The first input region216may completely cover the first vertex A, the second input region218may completely cover the second vertex B, and the output region220may completely cover the third vertex C, but the regions216-220typically do not overlap each other.

The first input region216, the second input region218, and the output region220may, or may not, be electrically isolated from each other. If the regions216-220are isolated, an electrical gap244may be between each of the regions216-220. Sizes of the input regions216-218and output region220may be such that current in one of the regions216-220does not affect current in another of the regions216-220.

The first input region216typically has a first local magnetization alignment210defined by the first logic input, the second input region218typically has a second local magnetization alignment212defined by the second logic input, and the output region220typically has a third output magnetization alignment214that defines the logic output.

The shape may be such that there are exactly six energy equivalent combinations (six stable configurations) for the directions of the first local magnetization alignment210, the second magnetization alignment212, and the output local magnetization alignment214. The six energy equivalent combinations may correspond to six energy equivalent energy states determined by a spin ice rule. The switching energy of the local magnetization alignments210-214is typically sufficiently stable to operate as non-volatile logic.

The shape may be such that two of the local magnetization alignments210-214point away from their respective vertices A, B, C and one of the local magnetization alignments210-214points towards its respective vertex A, B or C, or one of the local magnetization alignments points210-214away from its respective vertex A, B, or C, and two of the local magnetization alignments210-214point towards their respective vertices A, B, C.

Block604represents positioning fixed layers202-206to form an STT triad200including a first fixed layer202, a second fixed layer204, and a third fixed layer206coupled by a single free layer, wherein the single free layer is the magnetic material (e.g., ferromagnet208). The step may comprise depositing one or more spacer layers232to separate the fixed layers202-206from the free layer208such that the fixed layers202-206are electrically coupled to the free layer202. Each fixed layer202-206along with the portion (e.g.,216,218,220) of the free layer208under it forms an STTD or a STT diode.

Typically, there should not be a magnetic coupling between the fixed layers202-206and the free layer208, so the free layer's208magnetization alignment210-214can move freely; the free layer's208magnetization alignment210-214should not be pinned by the any magnetic fields associated with the fixed layers202-206. In the embodiment ofFIG. 2(b), to reduce the magnetic fields from the fixed layers202-206, the fixed layers202-206comprise of two antiferromagnetically aligned magnets222,224separated by layer230. The STTD is formed by the magnetic film224in close proximity to the free layer208. The magnetic film222nullifies the magnetic field from the magnetic film224without influencing the spin transfer torque (STT) caused by the current flow from layer224to the free layer208, as shown inFIG. 2(b). Thus, in the embodiment ofFIG. 2(b), only one of the magnetic films (layer224) in the antiferromagnetically coupled pair actually participates in the STT action, the transfer of magnetization by spin transfer. The film (layer222) not in proximity to the free layer208simply cancels out the fringing fields from the magnetic field used for the STT.

The first fixed layer202is positioned to provide the first logic input via writing pulse300that orients the first local magnetization alignment210so as to point the first local magnetization alignment210in a direction towards or away from the first vertex A.

The second fixed layer204is positioned to provide the second logic input via writing pulse302that orients the second local magnetization alignment212so as to point the second local magnetization alignment212in a direction towards or away from the second vertex B.

The third fixed layer206is positioned to provide an initialization pulse304that orients the third local magnetization alignment214so as to point the third local magnetization alignment214in a direction towards or away from the third vertex C, to define the truth table describing NAND or NOR logic. The third fixed layer206is also positioned to read the logic output using the GMR effect.

In one embodiment, the towards direction may be defined indicate a logical state “0,” the away direction may indicate a logical state “1,” and the logic output is bistable when one of the logic inputs is “1” and the other of the logic inputs is “0”. In this case, and when the logic output is bistable, the fixed layer206may re-write the logic output to “1” so that the logic inputs and logic output satisfy NAND gate logic. Alternatively, the fixed layer206may re-write the logic output to “0” when the logic output is bistable, so that the logic inputs and logic output satisfy NOR gate logic.

Block606represents the end result of the method, a logic gate. The logic gate may comprise a triad200of one or more fixed layers202-206coupled by a single domain ferromagnet208. The step may comprise connecting a plurality of the logic gates208, for example, wherein one or more transistors238electrically couple the output of one of the logic gates to one of the inputs of another of the logic gates.

The present invention may use transistors238to perform read-write functionality, while the magnetic material of the present invention performs the logic. The transistors238may form a CMOS pair, for example, that reads the triad output at vertex C and writes it to another triad input at input A′. The plurality of logic gates and the transistors may form a full adder, for example, as shown inFIG. 7.

FIG. 7(a) is top view of a full adder built up from several STT-triad unit cells700comprising the ferromagnet100and CMOS pair238. The full adder has inputs A, B and Carry In (Cin), and outputs Sum (S) and Carry Out (Co).FIG. 7(b) is a side view of the STT-triad unit cell700.

FIGS. 1-6also illustrate a method for implementing a non-volatile logic gate, comprising obtaining a magnetic material having a shape induced magnetic anisotropy, wherein a shape of the magnetic material has a first vertex, a second vertex, and a third vertex and supports a single magnetic domain and regions of the magnetic material include a first input region adjacent the first vertex, a second input region adjacent the second vertex, and an output region adjacent a third vertex; writing a first logic input to the first input region and a second logic input to the second input region, initializing the logic gate as a NAND gate or as a NOR gate; and outputting at least one logic output from the output region, wherein the shape induced magnetic anisotropy determines at least part of a truth table for the logic gate, so that the logic gate produces the at least one logic output from the logic inputs using the shape.

REFERENCES

CONCLUSION