Process and structure for a superjunction device

A superjunction device comprising a drain contact, a substrate layer above the drain contact, an epitaxial layer above the substrate layer, a P+ layer above the epitaxial layer formed by P-type implantation to a bottom of the superjunction device, a trench with a sloped angle formed by use of a hard mask layer. The trench is filled with an insulating material. A first vertical column is formed adjacent to the trench. A second vertical column is formed adjacent to the first vertical column. A source contact is coupled to the first vertical column and the second vertical column. A P-body region is coupled to the source contact. A gate oxide is formed above the source contact and the epitaxial layer, and a gate formed above the gate oxide.

BACKGROUND INFORMATION

Field of the Disclosure

The present invention relates generally to semiconductor devices, devices structures, and processes for fabricating high-voltage integrated circuits or power transistors devices.

Background

High-voltage applications such as motor drives, uninterruptible power supplies, and solar inverters may use power semiconductor devices. A variety of power semiconductor devices are available depending on the specific requirements of the application, such as power diodes, power metal-oxide-semiconductor field-effect transistors (MOSFET), bipolar-junction transistors (BJT), insulated gate bipolar transistors (IGBT), thyristors, etc.

Performance metrics of power semiconductor devices may include operating current and voltage, input and output impedance, switching speed, reverse-bias breakdown voltage, etc. The type of power semiconductor device utilized may be based in part on these performance metrics. Additional factors such as cost and device area may also contribute to the determination of the type of power semiconductor device utilized.

In order to increase the breakdown voltage of the vertical device, the thickness of an epitaxial layer of the vertical device also increases and the doping concentration in epitaxial layer decreases. However, this leads to a disproportional increase in the drain-source resistance (RDSON), which increases conduction losses when the vertical device is in the ON state. Another type of device known as a superjunction device can improve RDSONfor devices with high breakdown voltage by using charge compensation. For the same conduction losses (RDSON) superjunction devices require less area, which results in smaller output capacitance and smaller energy that is stored and lost during switching transitions.

DETAILED DESCRIPTION

A superjunction device can provide a lower specific ON resistance (RDSON) and lower output capacitance (COSS) performance in comparison to a vertical device with the same breakdown voltage. In one example, a vertical device can be a metal-oxide-semiconductor field effect transistor (MOSFET). The specific ON resistance is derived from the product's drain-source ON resistance and the area of the device. In one example, for a vertical device with a breakdown voltage of 400 volts, it can have an output capacitance of 360 picofarads (pf), an area of 13.8 mm{circumflex over ( )}2 and a 0.2 Ohm resistance. The specific ON resistance is calculated to be 2.76 Ohm/mm{circumflex over ( )}2.

The use of a superjunction device instead of a vertical device can provide numerous benefits. For a superjunction device with the same breakdown voltage as the vertical MOSFET mentioned above, the superjunction device can be built with less area, which in reduces the overall specific on resistance and decreases switching losses during each turn off event. In one example, the superjunction device can have an 8.0 mm2area and a 0.2 ohm resistance. The specific on resistance is calculated to be 1.6 ohm/mm2, which is a decrease in specific on resistance by forty two percent in comparison to the planar vertical device.

The superjunction device in the present disclosure can be formed in vertical columns of a trench etched into a silicon surface. The formation of vertical columns includes substantially equal doping concentrations of adjacent P and N columns in order to achieve charge balancing. The positive charges from the P column and negative charges from the N column provide a net charge of zero in the drift region. The charge balancing provided by the P and N column is critical to creating a constant electric field in order to maximize the breakdown voltage of the superjunction device. A high doping concentration in N column allows reduction of specific Ron for the targeted breakdown voltage.

In addition, the trench can be filled with a semi-insulating material such as semi-insulating polycrystalline silicon (SIPOS) or another equivalent insulating material to create a high voltage resistance between the source and drain to further assist in charge balancing. The insulated resistor can help provide a constant electric field throughout the superjunction device because the vertical electric field in semi-insulating resistor is expected to be approximately constant.

Superjunction devices include trenches filled with oxide. In one example, a superjunction device can be built with U-shaped trenches. However the performance and reliability of the superjunction device is reduced when voids are formed in the trench caused by the uneven filling of the trench with oxide. The voids can adversely affect device reliability due to presence of mobile charges that can move in high electric fields during the OFF state. As described below, a superjunction vertical transistor device can be formed that reduces the formation of voids when filling the trench with oxide when the trench is V-shaped instead of U-shape.

FIG. 1illustrates one example of a process for forming a superjunction device with a hard mask for implantation, in accordance with embodiments of the present disclosure. The superjunction device100comprises a substrate102, a N-type epitaxial layer108, a first type vertical column110, a second type vertical column111, a hard mask layer120for implantation, and optional screen oxide layer123.

To form the superjunction device structure100, an N-type substrate102can be used, on which an N-type epitaxial layer108is formed. Next, a hard mask layer120is formed over the epitaxial layer N-type layer. A trench is etched with a sloped angle in the N-type epitaxial layer108. In one example, the angle of the trench can be between 85-95 degrees. The angle of the trench less than 90 degrees can be formed for a V-trench. With implantation122and diffusion, a first type vertical column110is formed adjacent to the trench. Similarly by implantation122and diffusion, a second type vertical column111is formed adjacent to the first vertical column110. The first vertical column110can be a P-type semiconductor and the second vertical column111can be N-type semiconductor. It is appreciated in other examples, the first vertical column110can be an N-type semiconductor and the second vertical column111can be a P-type semiconductor. The implantation doses of the first vertical column and of the second vertical column are approximately equal to provide charge compensation. The implanting and diffusing can include boron and phosphate as part of the first type vertical column or the second type vertical column formation.

FIG. 2illustrates one example of a superjunction device with a V-trench, in accordance with embodiments of the present disclosure. It is appreciated that the elements mentioned inFIG. 2may be one example of elements ofFIG. 1, and that similarly named and numbered elements referenced below are coupled and function similar to as described above. The superjunction device200comprises a substrate layer202, a P+ layer204, an epitaxial layer208, a first vertical column210, a second vertical column211, a source contact214, a p-body region212, a gate oxide216, a gate contact218, and source electrode219. The substrate layer202can comprise of silicon material and is above the drain contact203. The epitaxial layer is formed above the substrate layer202. The P+ layer204is formed by P-type implantation to a bottom of the superjunction device200and is disposed above the epitaxial layer208. As mentioned previously, the first vertical column210and the second vertical column211are formed through implantation and diffusion. A trench is formed and is filled with an insulating material206. The insulating material206can use oxides such as tetrathoxysilane (TEOS), thermal oxide, borophosphosilicate glass (BPSG), nondoped silica glass (NSG). The angle of the trench can be between 85 to 95 degrees. InFIG. 2the V-shape trench is preferred, which allows the insulating material to be filled without voids and allows the first vertical column210and the second vertical column211regions to be formed by vertical (zero degree) implantation. The P-body region212is coupled to the source contact214. A gate oxide216is deposited above the epitaxial layer208. The gate218is formed above the gate oxide. In other examples, the gate218can be formed within the trench. The source electrode219is formed above source contact214. In addition, an insulation layer (not shown) can be formed above the gate218.

FIG. 3Aillustrates another example of a superjunction device with a trench and a DMOS gate, in accordance with embodiments of the present disclosure. It is appreciated that the elements mentioned inFIG. 3Amay be one example of elements of the previous figures, and that similarly named and numbered elements referenced below are coupled and function similar to as described above.FIGS. 3A-6Brepresent several embodiments of the superjunction device that use the vertical trench to allow the filling of the insulating material without voids. The superjunction300comprises similar elements as the previous figures. The difference is the channel under the gate318couples source contact314and first vertical column310.

FIG. 3Billustrates a top view of the superjunction device ofFIG. 2andFIG. 3A. The top view of the superjunction device shows the insulating material306, epitaxial layer308, second vertical column311, P-body312, N+ source314, and gate318. Channel under the gate318couples to N− epitaxial layer308(as shown onFIG. 2) and to N-type column (as shown onFIG. 3A)

FIG. 4Aillustrates another example of a superjunction device with a trench and an UMOS gate, in accordance with embodiments of the present disclosure. It is appreciated that the elements mentioned inFIG. 4Amay be one example of elements of the previous figures, and that similarly named and numbered elements referenced below are coupled and function similar to as described above. The superjunction device400comprises similar elements as the previous figures. The difference is the gate418is a UMOS gate.

FIG. 4Billustrates a top view of the superjunction device ofFIG. 4A. The top view of the superjunction device shows the insulating material406, epitaxial layer408, P-body412, N+ source414, and gate418. Dash filled areas show the channel that couples source contact414to first vertical column410.

FIG. 4Cillustrates a cross section through the channel of the superjunction device inFIG. 4A. The cross section through the channel of the superjunction device shows how electrons traverses the superjunction device from the source419to the N+ source414, then to first vertical column410(when a voltage is applied to the gate418), and then to the substrate402and the drain.

FIG. 5Aillustrates a superjunction device with a trench and a DMOS gate, in accordance with embodiments of the present disclosure. It is appreciated that the elements illustrated inFIG. 5Amay be one example of elements of the previous figures, and that similarly named and numbered elements referenced below are coupled and function similar to as described above.FIG. 5Billustrates a top view of the superjunction device inFIG. 5A, in accordance with embodiments of the present disclosure. It shows that channel under the gate518will couple the source contact514to the first vertical column510.

FIG. 6Aillustrates another example of a superjunction device with a UMOS gate, in accordance with embodiments of the present disclosure. It is appreciated that the elements illustrated inFIG. 6Amay be one example of elements of the previous figures, and that similarly named and numbered elements referenced below are coupled and function similar to as described above.FIG. 6Billustrates a top view of the superjunction device inFIG. 6A, in accordance with embodiments of the present disclosure.

FIG. 7Aillustrates another example of a superjunction device with an insulated resistor, in accordance with embodiments of the present disclosure. It is appreciated that the elements illustrated inFIG. 7Amay be one example of elements of the previous figures, and that similarly named and numbered elements referenced below are coupled and function similar to as described above. As mentioned previously, the vertical trench can be filled with a semi-insulating material734such as semi-insulating polycrystalline silicon (SIPOS) or another equivalent insulating material to create a high voltage resistance path between the source and drain to further assist in charge balancing. The superjunction device700comprises a substrate layer702, an epitaxial layer708, a first vertical column710, a second vertical column711, a source contact714, a P-body region712, a gate oxide716, a gate contact718, source electrode719, and a semi-insulating material734. The substrate layer702can comprise of silicon material and is above the drain contact703. The semi-insulating material734can be deposited into the trench in order to provide a nearly constant electric field, and can be coupled to the bottom of the epitaxial layer708, or the bottom of substrate layer702. The semi-insulating material734functions as an insulated resistor can help provide a nearly constant electric field throughout the superjunction device because the electric field expected to be approximately constant within insulated resistor. An additional benefit is to provide higher tolerance to charge misbalance. The epitaxial layer708is formed above the substrate layer702. As mentioned previously, the first vertical column710and the second vertical column711are formed through implantation and diffusion. A trench is filled with an insulating material706. The insulating material706can use oxides such as tetrathoxysilane (TEOS), thermal oxide, borophosphosilicate glass (BPSG), nondoped silica glass (NSG). The angle of the trench can be between 85 to 95 degrees. InFIG. 7A, the trench is substantially a V-shape, which allows the insulating material to be filled without voids and allows the first vertical column710and the second vertical column711regions to be formed by vertical (zero degree) implantation. A source contact714is coupled to the first vertical column710and the second vertical column711. The P-body region712is coupled to the source contact714. A gate oxide716is formed above the source contact714and the epitaxial layer708. The gate718is formed above the gate oxide. In other examples, the gate718can be formed within the trench. The source electrode719is formed above source contact714. In addition, a passivation layer (not shown) can be formed above the gate718.

FIG. 7Billustrates a top view of the superjunction device ofFIG. 7A. The top view of the superjunction device shows the insulating material706, epitaxial layer708, second vertical column711, P-body region712, N+ source714, gate718, and semi-insulating layer734.

FIG. 8Aillustrates another example of a superjunction device with a trench and a semi-insulating material, in accordance with embodiments of the present disclosure. It is appreciated that the elements mentioned inFIG. 8Amay be one example of elements of the previous figures, and that similarly named and numbered elements referenced below are coupled and function similar to as described above.FIGS. 7A-12Brepresent several embodiments of the superjunction device that use the vertical trench to allow the filling of the insulating material without voids and further comprises the semi-insulating material. The superjunction device800comprises similar elements as the previous figures. The difference is semi-insulating material is in a V-shape.

FIG. 8Billustrates a top view of the superjunction device ofFIG. 8A. The top view of the superjunction device shows the insulating material806, epitaxial layer808, second vertical column811, P-body region812, N+ source814, gate818, and semi-insulating layer834.

FIG. 9Aillustrates another example of a superjunction device with a trench and a semi-insulating material, in accordance with embodiments of the present disclosure. It is appreciated that the elements mentioned inFIG. 9Amay be one example of elements of the previous figures, and that similarly named and numbered elements referenced below are coupled and function similar to as described above. The superjunction device900comprises similar elements as the previous figures. The difference is semi-insulating material934is coupled to the epitaxial layer908.

FIG. 9Billustrates a top view of the superjunction device ofFIG. 9A. The top view of the superjunction device shows the insulating material906, epitaxial layer908, second vertical column911, P-body region912, N+ source914, gate918, and semi-insulating layer934.

FIG. 10Aillustrates another example of a superjunction device with a LIMOS gate and a semi-insulating material, in accordance with embodiments of the present disclosure. It is appreciated that the elements illustrated inFIG. 10Amay be one example of elements of the previous figures, and that similarly named and numbered elements referenced below are coupled and function similar to as described above. The superjunction device1000comprises similar elements as the previous figures. The difference is semi-insulating material1034is coupled to the P+ layer1004.

FIG. 10Billustrates top view of the superjunction device ofFIG. 10A. The top view of the superjunction device shows the insulating material1006, epitaxial layer1008, second vertical column1011, P-body region1012, N+ source1014, gate1018, and semi-insulating layer1034.

FIG. 11Aillustrates a superjunction device with a trench and a DMOS gate, and a semi-insulating material, in accordance with embodiments of the present disclosure. It is appreciated that the elements illustrated inFIG. 11Amay be one example of elements of the previous figures, and that similarly named and numbered elements referenced below are coupled and function similar to as described above.

FIG. 12Aillustrates another example of a superjunction device with a LIMOS gate, and a semi-insulating material in accordance with embodiments of the present disclosure. It is appreciated that the elements illustrated inFIG. 12Amay be one example of elements of the previous figures, and that similarly named and numbered elements referenced below are coupled and function similar to as described above.

FIG. 12Billustrates a top view of the superjunction device inFIG. 12A, in accordance with embodiments of the present disclosure

Although the present invention is defined in the claims, it should be understood that the present invention can alternatively be defined in accordance with the following examples:

Example 1: A method of forming a superjunction device structure, comprising: depositing an epitaxial N-type layer over an N-type substrate; depositing a hard mask layer over the epitaxial N-type layer; etching a trench with a sloped angle on the epitaxial N-type layer; forming a first vertical column adjacent to the trench by implantation and diffusion; forming a second vertical column adjacent to the first vertical column by implantation and diffusion; filling the trench with an insulating material such that a formation of key-holes is avoided; performing a chemical-mechanical planarization (CMP) to remove the insulating material over the first and second vertical column and the epitaxial N-type layer; depositing a gate oxide and a polysilicon layer; etching the gate oxide and the polysilicon layer with a gate mask above the polysilicon layer to form a gate; implanting a source contact below the gate oxide; implanting a P-body region below the source contact; forming a source electrode and a gate contacts; and forming a drain contact below the N-type substrate.

Example 2: The method of example 1, further comprising: depositing a semi-insulating material into the trench to provide a near constant electric field.

Example 3: The method of any of the previous examples, further comprising etching the trench to an angle between 85 to 95 degrees.

Example 4: The method of any of the previous examples, wherein the first vertical column is a P-type semiconductor and the second vertical column is an N-type semiconductor.

Example 5: The method of any of the previous examples, wherein implantation doses of the first vertical column and of the second vertical column are approximately equal.

Example 6: The method of any of the previous examples, wherein implantation doses of the first vertical column and of the second vertical column are approximately equal.

Example 7: The method of any of the previous examples, further comprising implanting and diffusing a phosphate as part of the first vertical column or the second vertical column.

Example 8: The method of any of the previous examples, further comprising depositing a channel mask and implanting in a top portion of the p-body region to adjust a threshold voltage.

Example 9: A superjunction device, comprising: a drain contact; a substrate layer above the drain contact; an epitaxial layer above the substrate layer; a P+ layer above the epitaxial layer formed by P-type implantation to a bottom of the superjunction device; a trench with a sloped angle formed by use of a hard mask layer, the trench filled with an insulating material; a first vertical column formed adjacent to the trench, a second vertical column formed adjacent to the first vertical column; a source contact coupled to the first vertical column and the second vertical column; a P-body region coupled to the source contact; a gate oxide formed above the source contact and the epitaxial layer; and a gate formed above the gate oxide.

Example 10: The superjunction device of example 9, wherein the trench extends to the substrate layer.

Example 11: The superjunction device of any of the previous examples, further comprising a semi-insulating material deposited into the trench, the semi-insulating material coupled to the source contact at a top of the epitaxial layer or to the substrate layer.

Example 12: The superjunction device of any of the previous examples, wherein the semi-insulating material forms a u-shape in the trench, the semi-insulating material coupled to the source contact at the top of the epitaxial layer or to the substrate layer.

Example 13: The superjunction device of any of the previous examples, further comprising an epitaxial buffer layer formed between the substrate layer and a bottom of the trench.

Example 14: The superjunction device of any of the previous examples, wherein the first vertical column is a P-type semiconductor and the second vertical column is an N-type semiconductor

Example 15: The superjunction device of any of the previous examples, wherein the first vertical column is an N-type semiconductor and the second vertical column is a P-type semiconductor.

Example 16: The superjunction device of any of the previous examples, wherein the gate is a DMOS gate.

Example 17: The superjunction device of any of the previous examples, wherein the gate is a LIMOS gate.

Example 18: The superjunction device of any of the previous examples, wherein the sloped angle of the trench is between 85 to 95 degrees.

Example 19: The superjunction device of any of the previous examples, further comprising: a passivation layer formed above the gate.

Example 20: The superjunction device of any of the previous examples, wherein the gate is formed within the trench.

Example 21: The superjunction device of any of the previous examples, wherein the trench is V-shaped to allow the trench to be filled with oxide without voids and to allow two column regions to be formed by vertical substantially zero degree implantation.