NANOMOLDING OF ELECTRICAL INTERCONNECTS

A method for forming semiconductor interconnects includes establishing a nanostructure in a substrate. The nanostructure may be embodied as a trench or other structure that extends from a first semiconductor device or structure to a second semiconductor device or structure. The method also includes establishing an electrically conductive material, such as a polycrystalline or single crystal copper material, on the substrate over the nanostructure to form a semiconductor assembly. The semiconductor assembly is then subjected to thermal process that causes the electrically conductive material to mold into the nanostructure established in the substrate to form an electrical interconnect that electrically connects the first semiconductor structure to the second semiconductor structure.

FIELD OF THE DISCLOSURE

The present disclosure relates generally to the formation of nanostructure and, more particularly, to the formation of nanostructure interconnects capable of electrically connecting semiconductor devices.

BACKGROUND

Interconnects are electrical structures that electrically connect two or more semiconductor devices or structures (e.g., transistors) in an electrical circuit or device such as an integrated circuit. The historical direction of the electrical device industry is for the production of smaller and more efficient electrical circuits and devices. However, as the overall footprint of electrical devices shrink, the corresponding size of interconnects included in such electrical devices likewise shrink. The shrinking of interconnects, however, offer challenges in the design and fabrication of electrical components because interconnects can be the limiting consideration in operational speed and efficiency of the resulting electrical component.

The reduction of the size of interconnects in electrical circuits is resulting in the need for nano-scale interconnects. However, while the ability to fabricate complex nanostructures is increasingly researched, a nanofabrication approach that enables simultaneous control over crystallinity, size, morphology, and material composition appears to remain elusive. For example, while bottom-up techniques such as molecular beam epitaxy and atomic layer deposition can fabricate high quality single crystalline films and coatings, those techniques are generally not useful in the fabrication of other more complex nanostructures. Additionally, those techniques do not readily translate to different material classes, require extensive optimization for each material composition of interest, and control of grain size and orientation is limited or dictated by the underlying substrate. Colloidal synthesis techniques can achieve acceptable size, shape, and composition control but are generally limited to 0D or 1D nanostructures, requires surface ligands to stabilize in solution, and cannot be easily integrated with other nanofabrication techniques or cleanroom processing. Micro-additive manufacturing, such as two-photon lithography or electrohydrodynamic redox 3D printing, enables arbitrary control of morphology and rapid optimization but is generally limited to a few material classes, cannot be performed over large areas due to the limitations of the rastering of a laser or a tip, and the final structures are nanoporous. Additionally, while top-down techniques, such as lithography, can enable control of morphology and size, those techniques are limited in material choice and lack control of crystallinity.

Thermomechanical nanomolding (TMNM) is a technique in which a bulk feedstock of a desired material is pressed through a nanoporous mold at elevated temperatures and pressures. TMNM has been shown to yield high aspect ratio single crystal nanowires over wafer-scale distances and to be rather material-agnostic. However, while TMNM can be used to form nanowires of a desired material, it is unclear whether TMNM techniques can be used to form more complex nanostructures, such as those required in an electrical circuit or device, which may have different boundary conditions and surface area to volume ratios, and if additional growth mechanisms are at play.

SUMMARY

According to an aspect of the present disclosure, a method for forming semiconductor interconnects may include establishing a nanostructure in a substrate and establishing an electrically conductive material on the substrate over the nanostructure to form a semiconductor assembly. The nanostructure may extend from a first semiconductor structure of the substrate to a second semiconductor structure of the substrate. The method may also include performing a thermal process on the semiconductor assembly that causes the electrically conductive material to mold into the nanostructure established in the substrate to form an electrical interconnect that electrically connects the first semiconductor structure to the second semiconductor structure.

In some embodiments, the nanostructure may be embodied as a trench formed in the substrate. In such embodiments, the trench may have at least one dimension that is less than 100 nanometers. Additionally, in some embodiments, the trench may have an aspect ratio of a height of the trench to a width of the trench of at least 10.

In some embodiments, establishing the nanostructure in the substrate may include establishing the nanostructure in a silicon substrate, an oxide layer, or a dielectric layer. Additionally, in some embodiments, the first semiconductor structure may be embodied as a first semiconductor transistor and the second semiconductor structure may be embodied as a second semiconductor transistor. In such embodiments, establishing the nanostructure in the substrate may include establishing the nanostructure to extend from the first semiconductor transistor to the second semiconductor transistor.

Additionally, in some embodiments, establishing the electrically conductive material on the substrate over the nanostructure may include establishing a single crystal copper layer on the substrate over the nanostructure. Alternatively, in other embodiments, establishing the electrically conductive material on the substrate over the nanostructure may include establishing a polycrystalline copper layer on the substrate over the nanostructure.

In some embodiments, the nanostructure may be embodied as a trench formed in the substrate, and the trench may include an inner wall. In such embodiments, establishing the electrically conductive material on the substrate may include aligning the electrically conductive material with the inner wall of the trench. For example, in some embodiments, aligning the electrically conductive material with the inner wall of the trench may include aligning a crystallographic plane of the electrically conductive material that has the lowest surface energy parallel to the inner wall of the trench. In some embodiments, the electrically conductive material may be embodied as a single crystal copper material and, in such embodiments, aligning the electrically conductive material with the inner wall of the trench may include aligning the (111) crystallographic plane of the single crystal copper material parallel to the inner wall of the trench. Alternatively, in other embodiments, the electrically conductive material may be embodied as a Body Centered Cubic (BCC) structured material and, in such embodiments, aligning the electrically conductive material with the inner wall of the trench may include aligning the (110) crystallographic plane of the BCC structured material parallel to the inner wall of the trench. Alternatively, in yet other embodiments, the electrically conductive material may be embodied as a Hexagonal Close Packed (HCP) structured material and, in such embodiments, aligning the electrically conductive material with the inner wall of the trench may include aligning the (001) crystallographic plane of the HCP structured material parallel to the inner wall of the trench.

Additionally, in some embodiments, performing the thermal process may include heating the semiconductor assembly to a melting temperature (Tm) of the electrically conductive material of in the range of 0.4 Tm to 0.7 Tm at a pressure in the range of 20 MegaPascals (MPa) to 100 MPa for a time period in the range of 1 hour to 2 hours. For example, in some embodiments, the electrically conductive material may be embodied as a nanocrystalline copper material and, in such embodiments, the performing the thermal process may include heating the semiconductor assembly to a temperature of 400 degrees Celsius at a pressure of 30 MPa for a time period of about 90 minutes. In other embodiments, the electrically conductive material may be embodied as a microcrystalline copper material and, in such embodiments, performing the thermal process may include heating the semiconductor assembly to a temperature of 400 degrees Celsius at a pressure of 60 MPa for a time period of about 90 minutes. In yet other embodiments, the electrically conductive material may include a single crystal copper material and, in such embodiments, performing the thermal process may include heating the semiconductor assembly to a temperature of 400 degrees Celsius at a pressure of 70 MPa for a time period of about 90 minutes.

In some embodiments, the method may also include lining the nanostructure with a barrier material prior to establishing the electrically conductive material on the substrate. In such embodiments, the barrier material may limit the interaction of the electrically conductive material and the substrate. For example, the barrier material may be a nitride material, such as tantalum nitride or other material that limits the interaction of the electrically conductive material and the substrate.

According to another aspect of the present disclosure, an electrical circuit may include a first semiconductor device established in a substrate and a second semiconductor device established in the substrate. The electrical circuit may also include a two-dimensional nanostructure interconnect that electrically connects the first semiconductor device to the second semiconductor device. In some embodiments, the two-dimensional nanostructure interconnect may be embodied as a single crystal copper interconnect formed in a trench of the substrate having a width less than 100 nanometers and an aspect ratio of a height of the trench to the width of the trench of at least 10.

According to a further aspect of the present disclosure, a method for forming semiconductor interconnects may include forming a nanostructure in a substrate and depositing an electrically conductive material onto the substrate over the nanostructure. The nanostructure may extend from a first semiconductor structure of the substrate to a second semiconductor structure of the substrate. The method may also include performing a thermal process on the substrate and electrically conductive material to cause the electrically conductive material to mold into the nanostructure formed in the substrate to form an interconnect electrically connecting the first semiconductor structure to the second semiconductor structure.

In some embodiments, the nanostructure may be embodied as a trench formed in the substrate. Alternatively, in other embodiments, the nanostructure may be embodied as a hole, via, or cavity formed in the substrate. In some embodiments, the nanostructure may have at least one dimension that is less than 100 nanometers. Additionally, the nanostructure may have a height-to-width aspect ratio of at least 10 and/or a length-to-width and/or a length-to-height aspect ratio of at least 1000.

Additionally, in some embodiments, the substrate may be embodied as a silicon substrate. Alternatively in other embodiments, the substrate may be embodied as an oxide layer or a dielectric layer. For example, in some embodiments, the substrate may be embodied as aluminum oxide layer or a silicon dioxide layer, and the nanostructure may be formed in the aluminum oxide layer or the silicon dioxide layer.

In some embodiments, the first and second semiconductor structures may be embodied as semiconductor devices. For example, the first and second semiconductor structures may be embodied as transistors. Alternatively, in other embodiments, the first and second semiconductor structures may be embodied as conductive contact pads formed on the substrate.

Additionally, in some embodiments, the electrically conductive material may be embodied a copper material, a cobalt material, or a ruthenium material. For example, the electrically conductive material may be embodied as a material selected from the group consisting of CoSn, Al2Cu, CoSi, and MoP.

In some embodiments, depositing the electrically conductive material onto the substrate may include growing a film of the electrically conductive material on the substrate over the nanostructure. Additionally, in some embodiments, the interconnect may be embodied as a single crystal. For example, the interconnect may consist of a single crystal. Alternatively, in other embodiments, the electrically conductive material may be embodied as a polycrystalline material. For example, the electrically conductive material may be embodied as polycrystalline copper.

In some embodiments, the nanostructure may be embodied as a trench formed in the substrate, and the trench may include an inner wall. In such embodiments, depositing the electrically conductive material onto the substrate may include aligning the electrically conductive material with the inner wall of the trench. For example, in such embodiments, aligning the electrically conductive material with the inner wall of the trench may include aligning a crystallographic plane of the electrically conductive material that has the lowest surface energy parallel to the inner wall of the trench.

In some embodiments, the electrically conductive material may be embodied as a Body Centered Cubic (BCC) structured material. In such embodiments, aligning the electrically conductive material with the inner wall of the trench may include aligning the (110) crystallographic plane of the BCC structured material parallel to the inner wall of the trench. In other embodiments, the electrically conductive material may be embodied as a Hexagonal Close Packed (HCP) structured material. In such embodiments, aligning the electrically conductive material with the inner wall of the trench may include aligning the (001) crystallographic plane of the HCP structured material parallel to the inner wall of the trench. Alternatively, in yet other embodiments, the electrically conductive material may be embodied as a single crystal copper material. In such embodiments, aligning the electrically conductive material with the inner wall of the trench comprises may include the (111) crystallographic plane of the single crystal copper material parallel to the inner wall of the trench.

Additionally, in some embodiments, performing the thermal process may include heating the substrate to a melting temperature (Tm) of the electrically conductive material of in the range of 0.4 Tm to 0.7 Tm at a pressure in the range of 20 MegaPascals (MPa) to 200 MPa for a time period in the range of 1 hour to 2 hours. For example, performing the thermal process may include heating the substrate to 0.5 Tm. In some embodiments, the electrically conductive material may be embodied as a copper material and, in such embodiments, performing the thermal process may include heating the substrate to about 450 degrees Celsius. In some embodiments, performing the thermal process may include exposing the substrate to a pressure in the range of about 30 MPa to 60 MPa. Additionally or alternatively, in some embodiments, performing the thermal process may include heating the substrate to a primer melting temperature (Tm) of the electrically conductive material of in the range of 0.4 Tm to 0.7 Tm. Additionally or alternatively, in some embodiments, performing the thermal process may include exposing the substrate to a pressure in the range of 20 MegaPascals (MPa) to 200 MPa.

In some embodiments, the method may further include lining the nanostructure with a barrier material prior to depositing the electrically conductive material onto the substrate. The barrier material may be selected so as to limit interaction of the electrically conductive material and the substrate. For example, the barrier material may be embodied as a metallic material. Additionally, the method may include forming one or more liner layers. In such embodiments, the one or more liner layers may be embodied as a first liner layer on the first semiconductor structure of the substrate and a second liner layer on the second semiconductor structure of the substrate. The one or more liner layers may be selected from materials, for example, comprising a nitride material (e.g., tantalum nitride), silicon dioxide, metallic materials (e.g. silver, lanthanum, titanium, ruthenium, iridium, tungsten, zirconium, antimony, calcium, any combination or alloy thereof), metal oxide materials, or metal nitride materials.

Additionally, in some embodiments, the substrate may be embodied as or otherwise include one or more dielectric materials. Additionally, in some embodiments, the method may include aligning a type of planes of a single crystal of the electrically conductive material to one or more walls of the mold. Alternatively or additionally, in some embodiments, the method may further include forming one or more interconnects each comprising a single crystal material.

According to yet a further aspect of the present disclosure, a semiconductor device may include a substrate, a first semiconductor structure formed on the substrate, a second semiconductor structure formed on the substrate, and a nanostructure formed in the substrate. The nanostructure may be embodied as a trench that extends from the first semiconductor structure to the second semiconductor structure. The semiconductor device may also include electrically conductive material molded into the nanostructure using any one of the methods described above such that the electrically conductive material electrically connects the first semiconductor structure to the second semiconductor structure.

Accordingly to still a further aspect of the present disclosure, a method for forming semiconductor interconnects may include forming a nanostructure in a substrate extending from a first surface of the substrate to a second surface of the substrate, depositing an electrically conductive material over the nanostructure to form a barrier layer over the nanostructure, and nanomolding an electrically conductive material into the nanostructure to cause the electrically conductive material to form a single crystal interconnect electrically connecting the first surface of the substrate to the second surface of the substrate.

In some embodiments, the nanostructure may be embodied as a trench, a hole, via or a cavity. Additionally, in some embodiments, the nanostructure may have at least one dimension that is less than 100 nanometers. For example, the nanostructure may have a height-to-width aspect ratio of at least 10 and/or a length-to-width and/or a length-to-height aspect ratio of at least 1000. Additionally, in some embodiments, the substrate may be embodied as a silicon substrate, a silicon dioxide substrate, or an aluminum oxide substrate.

In some embodiments, wherein the substrate includes a first semiconductor structure on the first surface of the substrate and a second semiconductor structure on the second surface of the substrate. In such embodiments, the single crystal interconnect may electrically connecting the first semiconductor structure to the second semiconductor structure. For example, the first semiconductor structure may be embodied as a transistor, contact pad, or conductive element, and the second semiconductor structure may be embodied as a transistor, contact pad, or conductive element. In some embodiments, the interconnect may be formed from copper, cobalt, ruthenium, CoSn, Al2Cu, CoSi, or MoP. For example, in some embodiments, the interconnect may consist of copper, cobalt, ruthenium, CoSn, Al2Cu, CoSi, or MoP.

In some embodiments, the nanostructure may be embodied as a trench defining an inner wall extending in a first direction. In such embodiments, nanomolding of the electrically conductive material into the nanostructure to form the single crystal interconnect may align an orientation of a crystallographic plane of the interconnect to the first direction of the trench wall. For example, in some embodiments, the crystallographic plane of the interconnect may be embodied as a (111) crystallographic plane, a (110) crystallographic plane, or a (001) crystallographic plane.

Additionally, in some embodiments, nanomolding the electrically conductive material may include heating the substrate to a melting temperature (Tm) of the electrically conductive material, in the range of 0.4 Tm to 0.7 Tm, at a pressure in the range of 20 MegaPascals (MPa) to 200 MPa, and for a time period between about 1 hour to about 2 hours. For example, heating the substrate may include heating the substrate to 0.5 Tm or about 450 degrees Celsius. Additionally, in some embodiments, the nanomolding may be performed at an elevated pressure between about 30 MPa to about 60 MPa. Additionally or alternatively, the nanomolding may include heating the substrate to a primer melting temperature (Tm) of the electrically conductive material in the range of 0.4 Tm to 0.7 Tm. Additionally or alternatively, the nanomolding may be performed at a pressure in the range of 20 MegaPascals (MPa) to 200 MPa. Furthermore, in some embodiments, the electrically conductive material into the nanostructure may cause the electrically conductive material to form a plurality of single crystal interconnects electrically connecting the first surface of the substrate to the second surface of the substrate.

According to yet another aspect of the present disclosure, a method for forming semiconductor interconnects may include forming a nanostructure in a substrate extending from a first surface of the substrate to a second surface of the substrate, depositing an electrically conductive material over the nanostructure to form a barrier layer over the nanostructure; and disposing within the nanostructure a nanomolded single crystal interconnect to electrically connect the first surface of the substrate to the second surface of the substrate. In some embodiments, the forming of the nanostructure in the substrate may include forming a plurality of nanostructures extending from the first surface of the substrate to the second surface of the substrate. In such embodiments, depositing of the electrically conductive material may include depositing of the electrically conductive material over the plurality of nanostructures to form a barrier layer over each of the plurality of nanostructures. Additionally, in such embodiments, disposing of the nanomolded single crystal may include disposing a nanomolded single crystal within each of the plurality of nanostructures to electrically connect the first surface of the substrate to the second surface of the substrate.

DETAILED DESCRIPTION

Referring now toFIG.1, in an illustrative embodiment, an electrical circuit100fabricated according to the technologies disclosed herein includes a first semiconductor structure102, a second semiconductor structure104, and a nanostructure interconnect110extending between the first and second semiconductor structures102,104. The nanostructure interconnect110is electrically connected to each of the first and second semiconductor structure102,104and electrically connects those structures to each other. Each of the semiconductor structures102,104may be embodied as any type of semiconductor structures including, but not limited to, semiconductor transistors, electrical circuit components, contact pads, other interconnects or conductive elements (e.g., metallization), and/or other semiconductor structures, devices, circuits, connections, or interconnects.

In the embodiment ofFIG.1, the nanostructure interconnect110is formed along a generally linear path between the semiconductor structures102,104. However, in other embodiments such as the embodiment ofFIG.2, the nanostructure interconnect110may be formed along a complex or otherwise non-linear path (e.g., to avoid other electrical components of the electrical circuit100). Additionally, although the illustrative electrical circuit100includes only a single nanostructure interconnect110in the embodiments ofFIGS.1and2, it should be appreciated that the electrical circuit100may include additional nanostructure interconnects110in other embodiments.

The illustrative nanostructure interconnect110includes an electrically conductive conductor (e.g., a copper conductor) formed in a corresponding nanostructure. For example, as shown inFIG.3, the illustrative nanostructure interconnect110includes an electrically conductive conductor112formed in a nanostructure114. The nanostructure114is illustratively embodied as a nanostructure trench (i.e., a “nanotrench”) defined or otherwise formed in a substrate300. However, in other embodiments, the nanostructure114may be embodied as other types of nanostructures formed in the substrate300including, but not limited to, a via, a hole, a cavity, or other area or volume of the substrate300.

Illustratively, the nanostructure interconnect110is embodied as a two-dimensional nanostructure in that the nanostructure interconnect110includes at least one dimension that is less than 100 nanometers. That is, unlike one-dimensional nanostructures in which two dimensions are on the nanoscale (e.g., less than 100 nanometers) and one is on the microscale or greater, the nanostructure interconnect110illustratively includes one dimension on the nanoscale (i.e., less than 100 nanometers) and two dimensions on the microscale or greater (i.e., greater than 100 nanometers). Accordingly, as used herein, a “one-dimensional nanostructure” means a nanostructure in which the size of two dimensions of the nanostructure are on the nanoscale (i.e., less than 100 nanometers) and the remaining one dimension is greater than the nanoscale (i.e., greater than 100 nanometers). Examples of one-dimensional (1D) nanostructures include nanowires, nanorods, nanobelts, and nanotubes-whose lateral dimensions fall anywhere in the range of 1 to 100 nm. Conversely, as used herein, a “two-dimensional nanostructure” means a nanostructure in which the size of one dimension (e.g., the width of a trench) is on the nanoscale (i.e., less than 100 nanometers) and the remaining two dimensions (e.g., the height and length of the trench) are greater than the nanoscale (i.e., each are greater than 100 nanometers). Examples of two-dimensional (2D) nanostructures include nanosheets and deep nanotrenches. In the illustrative embodiment, for example, the nanostructure interconnect110(i.e., the nanostructure114and the electrically conductive conductor112) has a width302of about 20-40 nanometers and a depth or height304of 500-1000 nanometers. As such, depending on the particular dimensions of the width302and height304, the nanostructure interconnect110may be fabricated using the technologies disclosed herein to have a height-to-width aspect ratio in the range of 1 to 1,000 or more, including any value therewithin and any subranges therebetween, preferably with a relatively high aspect ratio of at least 5, 10, 15, 20, 25, 30, 35, 40, 45, 50, 100, 150, 200, 250, 300, 350, 400, 450, 500, etc. The overall length of the nanostructure interconnect110may depend on various criteria such as the structure or size of the electrical circuit100, the size of the substrate300(e.g., the size of the substrate wafer), and/or other implementation criteria. As such, depending on the overall length of the nanostructure interconnect110, the nanostructure interconnect110may be fabricated using the technologies disclosed herein to have a length-to-width and/or a length-to-height aspect ratio in the range of 1 to 10,000 or more, including any value therewithin and any subranges therebetween, preferably with a relatively high aspect ratio of at least 10, 50, 100, 200, 300, 400, 500, 600, 700, 800, 900, 100, 1,500, 2,000, etc.

As discussed in more detail below, the electrically conductive conductor112may be formed from any electrically conductive material suitable to the fabrication techniques described herein. Typically, an electrically conductive material having low resistivity is selected. In the illustrative embodiment, the electrically conductive conductor112is embodied as a copper material. However, in other embodiments, the electrically conductive conductor112may be embodied as a cobalt or ruthenium material. For example, in some embodiments, the electrically conductive conductor112may be embodied as Cobalt Tin (CoSn), Copper Aluminide (AL2CU), Cobalt Silicide (CoSi), or Molybdenum Phosphide (MoP). Additionally, the electrically conductive conductor112may be embodied as a single or polycrystalline material. For example, in the illustrative embodiment, the electrically conductive conductor112is embodied as a single copper material or a polycrystalline material.

The substrate300may be embodied as any type of substrate in which the nanostructure114can be etched, formed, or otherwise established. Typically, a material having a relatively high melting point (i.e., higher than the electrically conductive material forming the electrically conductive conductor112), low diffusivity, and a high modulus is selected to form the substrate300. For example, in the illustrative embodiment, the substrate300is embodied as a silicon substrate, which may form a portion of a silicon wafer, for example. However, in other embodiments, other types of substrates may be used. For example, the substrate300may be embodied as an oxide layer or a dielectric layer, which may be established on another substrate (e.g., on a silicon substrate) using typical semiconductor fabrication techniques. In some embodiments, the substrate300may be embodied as MgO substrate, a NaCL substrate, an aluminum oxide (Al2O3) layer, or a silicon dioxide (SiO2) layer. Again, such layers may be formed on other substrates or layers.

In some embodiments, the electrical circuit100may also include a barrier layer120, which may be established (e.g., deposited or grown) over the nanostructure114of the nanostructure interconnect110and the surrounding substrate300. The barrier layer120may be embodied as any material capable of providing a barrier that limits or otherwise prevents interaction of the electrically conductive conductor112and the substrate300. For example, in embodiments in which the electrically conductive conductor112is a copper material, the barrier layer120may be formed from a nitride, such as tantalum nitride. However, in other embodiments, the barrier layer120may be embodied as, for example, a metallic material, such as silver, lanthanum, titanium, ruthenium iridium, tungsten, zirconium, animony, calcium, or any combination thereof. Alternatively, the barrier layer120may be embodied may be embodied as a metal oxide or a metal nitride material. In some embodiments, the barrier layer120is embodied as silicon dioxide deepening on, for example, the type of substrate300used. Although only a single barrier layer120is shown inFIG.3, it should be appreciated that the electrical circuit100may include additional barrier layers in other embodiments and such additional layers may cover common or different areas of the electrical circuit100(e.g., one layer may cover the semiconductor structure102and another layer may cover the semiconductor structure104).

Referring now toFIGS.4-6, in some embodiments, the electrical circuit100may be embodied as a vertical electrical circuit with semiconductor structures, devices, or components “buried” in the substrate300(e.g., a memory circuit). In such embodiments, the electrical circuit100may include multiple nanostructure interconnects110, each of which may be configured to electrically connect multiple semiconductor structures102,104established in the substrate300. For example, as shown inFIG.4, each nanostructure interconnect110extends over and electrically connects multiple semiconductor structures102,104, which have been previously deposited, grown, or otherwise established in the substrate300. As shown inFIG.5, each electrically conductive conductor112extends downwardly into the nanostructure114(illustratively embodied as a nanotrench) and is electrically connected to a semiconductor structure102buried in the substrate300. In this way, layers of semiconductor devices or circuits can be formed using the nanostructure interconnects110. As discussed above, the nanostructure interconnects110may form lateral or vertical interconnects (e.g., vias), which connect multiple layers of a vertical circuit, in some embodiments. As such, it should be appreciated that the electrical circuit100may include multiple levels of nanostructure interconnects110, which may electrically connect semiconductor structures102,104located on the same level and/or semiconductor structures102,104or other nanostructure interconnects110located on other levels (i.e., vertical connectivity) of the electrical circuit100.

FIG.6illustrates a cross-sectional Scanning Transmission Electron Microscopy (STEM) imaging of nanocrystalline copper interconnects formed in corresponding nanostructure (i.e., nanotrenches), which corresponds to the nanostructure interconnects110illustrated inFIGS.4and5. A scalebar 600 of 100 nanometers is included to identify the corresponding scale. As shown inFIG.6, the nanocrystalline copper material has fully or otherwise sufficiently filled the nanotrenches formed in the substrate of that illustrative embodiment.

Referring now toFIGS.7and8, a method700may be used to fabricate the electrical circuit100and associated nanostructure interconnects110described above. The method700begins with block702in which the substrate300is fabricated. As described above, the substrate may be formed from any suitable material such as an oxide or dielectric material (e.g., aluminum oxide (Al2O3) or silicon dioxide (SiO2)). In the illustrative embodiment in block704, the substrate300is fabricated from a silicon material. In such embodiments, the substrate300may be embodied as a single substrate as shown inFIG.9or may include additional materials, structures, or features depending on the fabrication technique used and the overall process entailed. For example, in some embodiments, multiple layers of silicon may be grown or deposited on each other (or other substrate material) to produce the substrate300.

Referring back toFIG.7, after the substrate300has been fabricated, the method700advances to block706in which one or more semiconductor structures102,104are fabricated in the or on the substrate300. For example, in block708, one or more semiconductor devices, such as a transistors, may be fabricated using typical semiconductor processing techniques. Additionally or alternatively, in block710, one or more semiconductor connectors, such as electrical connector pads or connections, may be fabricated on or in the substrate300. As shown inFIG.10, in the illustrative embodiment, a semiconductor structure102is formed in the substrate300. The semiconductor structure102may be so formed, for example, by ion implantation, deposition, or other fabrication technique. Additionally, in some embodiments, additional semiconductor layers may be formed over the semiconductor structure102such that the structure102becomes “buried” in the substrate300.

Referring again back toFIG.7, after the semiconductor structures102,104have been fabricated in the substrate300, the method700advances to block712. In block712, one or more nanostructures114are established in the substrate300. Depending on the particular type of nanostructure114to be used, different methodologies may be employed for establishing the nanostructures114in the substrate300. For example, the nanostructures114may be formed using an etching process. For example, in an illustrative embodiment, the nanostructure formation process included (1) thermal oxidation for hardmask formation with a 200 nm gap (1 μm pitch), (2) a photolithography process with a KrF scanner (ASML, PAS 5500/700D), (3) hardmask etching (Lam Research, EXELAN-HPT), (4) photoresist stripping (PSK. DAS-2000), (5) post cleaning, (6) silicon trench etching (Lam Research, TCP-9400DFM), (7) another round of post cleaning. (8) hard mask removal through hydrofluoric acid, and (9) low-pressure nitride deposition (Centrotherm, E1200) for gap shrinkage to a target gap of 20˜40 nm. The illustrative etching conditions included a mixture of CF4, Ar, and O2for the Bottom Anti-Reflective Coating (BARC) etching; C4F8, Ar, and O2for the oxide etching; and He, SF6, and O2gases for silicon trench etching.

In the illustrative embodiment in block714, the nanostructures114are formed as two-dimensional nanostructures. That is, as described above, the nanostructure114include at least one dimension less than 100 nanometers, while the other two dimensions may be greater than 100 nanometers. For example, in block716and as shown inFIG.11, the nanostructure114may be formed as a nanotrench, which illustrative has a width302of about 20-40 nanometers and a depth304of about 500-100 nanometers. Additionally, as shown inFIG.11and indicated in block718ofFIG.7, the nanostructure(s)114are established or formed in the substrate300so as to connect multiple semiconductor structures102,104. That is, the nanostructure114(e.g., a nanotrench) is exposed to the corresponding semiconductor structures102,104such that the electrically conductive conductor112that is subsequently molded into the nanostructure114can electrically contact the corresponding semiconductor structures102,104.

After the semiconductor structures102,104have been formed in the substrate300, the method700advances to block720in some embodiments. In block720, a barrier liner layer120is deposited or otherwise formed over the nanostructures114as illustrated inFIG.12. As discussed above, the barrier liner layer120may be embodied as any material capable of providing a barrier that limits or otherwise prevents interaction of the electrically conductive conductor112and the substrate300. For example, the barrier layer120may be embodied as silicon dioxide, a metal oxide, a metal nitride, or other metallic material. The barrier layer120may be formed in/over the nanostructure114(and surrounding substrate300in some embodiments) using any suitable fabrication techniques such as a deposition process (e.g., a chemical vapor deposition process) or growth process (e.g., an epitaxial growth process).

FIGS.13and14illustrate a cross-sectional Scanning Transmission Electron Microscopy (STEM) imaging of set of trench nanostructures114formed in a substrate300and including a barrier liner layer120formed over the nanostructures114. A scalebar 1300 of 1 micrometer (1 μm) is included inFIG.13, and a scalebar 1400 of 1 nanometer is included inFIG.14to identify the corresponding scales.

Referring now back toFIG.7, after the nanostructures114have been established in block712and the barrier layer120, if any, has been formed in block720, the method700advances to block722. In block722, an electrically conductive material is established over the nanostructures114. As shown inFIG.15, the electrically conductive material may be embodied as an electrically conductive material layer1550, which may be overlaid, deposited, grown, or otherwise formed over the nanostructures114(and surrounding substrate300) using any suitable methodology to form a semiconductor assembly1500. For example, in some embodiments, the electrically conductive material layer1550is embodied as a foil layer of electrically conductive material (e.g., copper), which is placed over the nanostructure114. In other embodiments, the electrically conductive material layer1550is grown as a thin film on the substrate300.

As discussed above, the electrically conductive material (which subsequently forms the electrically conductive conductor112) may be embodied as any electrically conductive material feedstock that is suitable to the fabrication techniques described herein such as, for example, copper, cobalt, ruthenium, CoSn, AL2CU, CoSi, or MoP. Additionally, as discussed above, the electrically conductive material may be polycrystalline or single crystal material. For example, in block724ofFIG.7, a nanocrystalline copper feedstock may be used as the electrically conductive material, which may have grain sizes from 50 nanometers to 7 micrometers. Alternatively, in block726, a micocrystalline copper feedstock may be used as the electrically conductive material, which may have gain sizes from 1 micrometer to 50 micrometers.

Furthermore, in the illustrative embodiment in block728, a single crystal copper feedstock is used as the electrically conductive material. In doing so, it has been determined that the success of nanomolding the single crystal copper feedstock is dependent on the orientation of the single crystal with respect to the inner walls of the nanotrench. If the single crystal copper feedstock is not properly orientated, substantially higher pressure may be required to achieve nanomolding, which can crack or damage the substrate300. As such, the single crystal copper feedstock may be aligned to a trench wall in block730to improve the nanomolding of the single crystal copper feedstock.

To align the feedstock to the nanotrench, a crystallographic plane of the electrically conductive material layer1550that has the lowest surface energy parallel is aligned to the inner wall of the nanotrench. For example, as shown inFIG.16, a single crystal copper foil layer1550is aligned such that the (111) crystallographic plane of the single crystal copper material is parallel to a longitudinal inner wall1600of the trench nanostructure114. It should be appreciated that once the foil layer1550is properly aligned to a single trench nanostructure114, that foil layer1550is also aligned with other trench nanostructures114parallel to that aligned trench nanostructure114. Proper alignment of the layer1550may be confirmed via Laue diffraction. It should be appreciated that the described alignment process is usable for other Face Centered Cubic (FCC) single crystal structures, in addition to copper. For Body Centered Cubic (BCC) single crystal structures, the (110) crystallographic plane may be aligned to the longitudinal inner wall1600of the trench nanostructure114. For Hexagonal Close Packed (HCP) single crystal structures, the (001) crystallographic plane may be aligned to the longitudinal inner wall1600of the trench nanostructure114. In embodiments, in which the electrically conductive material layer1550is grown on the substrate300, the electrically conductive material layer1550may be aligned with the inner wall1600of the trench nanostructure114via the growth process.

For polycrystalline layers1550, it has been determined that the crystal will slowly rotate toward an orientation in which the lowest surface energy parallel is aligned to the inner wall of the nanotrench. However, such rotation takes place over distances longer than the depth of the corresponding trench nanostructure114(e.g., >500 nanometers). As such, the resulting material located in the trench nanostructure114after thermal processing (see description of block732of method700below), will also be polycrystalline but with defects, such as twins. The use of a single crystal feedstock reduces grain rotation and increases the likelihood of single crystal formation along the length of the trench nanostructure114. For example,FIG.18illustrates a 4D-STEM grain orientation map of nanocrystalline copper interconnects formed in corresponding nanostructure trenches subsequent to a thermal process as described above. Conversely,FIG.19illustrates a single crystal copper interconnect formed in a corresponding nanostructure trench and having the (111) crystallographic plane of the single crystal copper interconnect aligned with an inner wall of the trench.

Referring back toFIG.7, after the electrically conductive material1550has been established over the corresponding nanostructure114in block722, the method700advances to block732ofFIG.8. In block732, a thermal process is performed on the semiconductor assembly1500(i.e., the substrate300and the electrically conductive material layer1550) to mold the electrically conductive material layer1550into the corresponding nanostructure114to form the electrically conductive conductor112therein as shown inFIG.17. To do so, in block734ofFIG.8, a thermal process having a pressure, temperature, and process time based on the type of electrical conductive material is performed. For example, the thermal process may include heating the semiconductor assembly1500to a melting temperature (Tm) of the electrically conductive material1550in the range of 0.4 Tm to 0.7 Tm at a pressure in the range of 20 MegaPascals (MPa) to 100 MPa for a time period in the range of 1 hour to 2 hours. More specifically, if the electrically conductive material1550is embodied as a nanocrystalline copper material, the thermal process may include heating the semiconductor assembly1500to a temperature of about 400 degrees Celsius at a pressure of about 30 MPa for a time period of about 90 minutes. Alternatively, if the electrically conductive material1550is embodied as a microcrystalline copper material, the thermal process may include heating the semiconductor assembly1500to a temperature of about 400 degrees Celsius at a pressure of about 60 MPa for a time period of about 90 minutes. Further, if the electrically conductive material1550is embodied as a microcrystalline copper material, the thermal process may include heating the semiconductor assembly1500to a temperature of about 400 degrees Celsius at a pressure of about 70 MPa for a time period of about 90 minutes. Higher temperatures and pressures may be used in some embodiments; however, high temperatures and pressures increase the risk heat damage and fracturing of the semiconductor assembly1500in other areas. The thermal process may be achieved using various heating equipment and processes. For example, in some embodiments a hot press, in which a press is encapsulated by a corresponding furnace, may be used. In other embodiments, the heating process may be achieved via heating the anvils that are apply pressure to the semiconductor assembly1500, which conducts heat to the electrically conductive material1550during loading. Alternatively, in other embodiments, a laser may be used to selectively heat the semiconductor assembly1500.

Referring back toFIG.8, after the thermal process has been performed on the semiconductor assembly1500, the method700advances to block736in which final or additional processing of the semiconductor assembly1500is performed. For example, in block738, any electrically conductive material1550remaining on top of the substrate300may be etched or otherwise removed. Additionally, in some embodiments, the substrate300may be further etched away to form freestanding nanostructures. For example,FIG.20illustrates a “false color” SEM image of a set of single crystal copper nanofins, which may be formed via the etching process of block738. A scalebar 2000 of 2 micrometers is included to identify the corresponding scale.

Referring now toFIGS.21-23, imaging illustrations of an electrical circuit100including nanocrystalline copper nanostructure interconnects110fabricated according to the method700described above are shown.FIG.21illustrates an illustrative Optical Bright Field Image of a set of nanocrystalline copper nanostructure interconnects110. A scalebar 2100 of 10 micrometers is included to identify the corresponding scale.FIG.22illustrates a cross-sectional SEM imaging of the nanocrystalline copper nanostructure interconnects110ofFIG.21. A scalebar 2200 of 1 micrometers is included to identify the corresponding scale.FIG.23illustrates a longitudinal cross-sectional SEM imaging of the nanocrystalline copper nanostructure interconnects110ofFIG.21. A scalebar 2300 of 1 micrometers is included to identify the corresponding scale. As shown in each ofFIGS.21-23, the nanocrystalline copper conductive material has substantially filled the corresponding nanotrenches.

Similarly,FIG.24illustrates a longitudinal cross-sectional SEM imaging of a microcrystalline copper nanostructure interconnect110formed in a corresponding nanotrench using the method700described above. A scalebar 2400 of 2 micrometers is included to identify the corresponding scale. Additionally,FIG.25illustrates a cross-sectional STEM imaging of a set of single crystal copper interconnects110formed in corresponding nanotrenches according to the method700described above. A scalebar 2500 of 1 micrometers is included to identify the corresponding scale. Again, as shown in each ofFIGS.24and26, the microcrystalline copper conductive material ofFIG.24and the single crystal copper material ofFIG.25have sustainably filled the corresponding nanotrenches.

While the disclosure has been illustrated and described in detail in the drawings and foregoing description, such an illustration and description is to be considered as illustrative and not restrictive in character, it being understood that only illustrative embodiments have been shown and described and that all changes and modifications that come within the spirit of the disclosure are desired to be protected.