Receiver circuit

A receiver circuit includes: first and second phase adjusters that generate first and second clock signals; first and second determinators that perform binary determination on input data in synchronization with the first and second clock signals; a phase detection circuit that detects a phase on the basis of determination values of the first and the second determinators; a filter that performs filtering on the detected phase and thereby outputs first phase information to the second phase adjuster; an adder that adds a shift amount to the first phase information and thereby outputs second phase information to the first phase adjuster; and a corrector that outputs third phase information for decreasing variation in phase difference of the first clock signal with respect to the second clock signal to the first phase adjuster.

CROSS-REFERENCE TO RELATED APPLICATION

This application is based upon and claims the benefit of priority of the prior Japanese Patent Application No. 2013-156804, filed on Jul. 29, 2013, the entire contents of which are incorporated herein by reference.

FIELD

The embodiments discussed herein are directed to a receiver circuit.

BACKGROUND

With improvement in performance of information processors such as apparatuses and servers intended for communication trunk, the data rate of signal transmitting/receiving inside and outside the apparatus needs to be increased. The receiver circuit performs reproduction (CDR: Clock and Data Recovery) of the clock and data from data of a high data rate in order to absorb the difference in clock frequency with respect to the transmitter circuit. As a CDR method in a transmitter/receiver circuit at such a high speed as exceeding 10 Gbps, there is known CDR in a two-times over sampling method of performing sampling two times in 1 unit interval (UI) section of data and setting one sampling to the center of data and the other sampling to the transition point of data.

Further, a closed loop clock correction method is known which includes a step of adjusting two or more input signals including at least one in-phase clock and at least one quadrature phase clock, and a step of applying the adjusted quadrature phase clock signal to a device capable of generating a 4-quadrant interpolated output clock phase (refer to, for example, Patent Document 1). First, an interpolated output clock phase is delayed so as to form a clock for measurement device, and two or more adjusted input signals to the measurement device are measured over a range of the interpolated output clock phase. Then, an error between the in-phase clock and the quadrature phase clock is decided using sample information from the measurement device, and the in-phase clock and the quadrature phase clock are adopted using the decided error information in a closed loop feedback configuration.[Patent Document 1] Japanese Laid-open Patent Publication No. 2011-10296

The receiver circuit can sample a center and a transition point of data using a first clock signal and a second clock signal. If the phase difference between the first clock signal and the second clock signal is constant, the center of data can be sampled at all times. However, if the receiver circuit has a function of shifting the phase of the first clock signal, there occurs variation in the phase difference between the first clock signal and the second clock signal. In this case, it is impossible to sample the center of data to cause a problem of increasing the occurrence rate of data error.

SUMMARY

A receiver circuit includes: a first phase adjuster that generates a first clock signal; a second phase adjuster that generates a second clock signal; a first determinator that performs binary determination on input data in synchronization with the first clock signal; a second determinator that performs binary determination on the input data in synchronization with the second clock signal; a phase detection circuit that detects a phase on the basis of determination values of the first determinator and the second determinator; a filter that performs filtering on the phase detected by the phase detection circuit and thereby outputs first phase information; an adder that adds a shift amount to the first phase information and thereby outputs second phase information; and a corrector that generates third phase information for decreasing variation in phase difference of the first clock signal with respect to the second clock signal, wherein the first phase adjuster adjusts a phase of the first clock signal on the basis of the second phase information and the third phase information, and wherein the second phase adjuster adjusts a phase of the second clock signal on the basis of the first phase information.

DESCRIPTION OF EMBODIMENTS

FIG. 1is a diagram illustrating a configuration example of a receiver circuit according to this embodiment. The receiver circuit receives, from a transmitter circuit, data Di with a high bit rate in an integrated circuit chip, between chips (in a device, between devices). A clock signal of the receiver circuit is asynchronous with a clock signal of the transmitter circuit.

A first phase interpolation circuit101agenerates a first clock signal CLKa using a reference clock signal CLKr. A second phase interpolation circuit101bgenerates a second clock signal CLKb using the reference clock signal CLKr. The first phase interpolation circuit101ais a first phase adjuster and adjusts the phase of the first clock signal CLKa on the basis of phase information MSBa and LSBa. The phase information MSBa is high-order bit phase information, and the phase information LSBa is low-order bit phase information. The second phase interpolation circuit101bis a second phase adjuster and adjusts the phase of the second clock signal CLKb on the basis of phase information MSBb and LSBb. The phase information MSBb is high-order bit phase information, and the phase information LSBb is low-order bit phase information. When a shift amount SD is “0,” the phase difference between the first clock signal CLKa and the second clock signal CLKb is 90 degrees.

FIG. 2Ais a diagram illustrating examples of input and output signals of the first phase interpolation circuit101a. The first phase interpolation circuit101areceives input of four-phase reference clock signals CLKra, CLKrb, CLKrax, CLKrbx, and outputs first clock signals CLKa and CLKax by performing phase interpolation on the four-phase reference clock signals CLKra, CLKrb, CLKrax, CLKrbx. The four-phase reference clock signals CLKra, CLKrb, CLKrax, CLKrbx are shifted in phase by 90 degrees each. The reference clock signal CLKra is a signal with a phase of 0 degrees, the reference clock signal CLKrb is a signal with a phase of 90 degrees, the reference clock signal CLKrax is a signal with a phase of 180 degrees, and the reference clock signal CLKrbx is a signal with a phase of 270 degrees. The first clock signals CLKa and CLKax are differential signals inverted in phase to each other.

FIG. 3is a diagram illustrating a configuration example of the first phase interpolation circuit101a. A current source301is connected between a power source potential node and a switch group303. A current source302is connected between the power source potential node and a switch group304. The current sources301and302supply currents different in magnitude from each other. The switch group303has four switches which connect the current source301to a gate of a transistor305, a gate of a transistor307, a gate of a transistor319, and a gate of a transistor317respectively. The switch group304has four switches which connect the current source302to the gate of the transistor305, the gate of the transistor307, the gate of the transistor319, and the gate of the transistor317respectively. The switch groups303and304are controlled according to the phase information MSBa and LSBa. The total current value of the variable current sources301and302are constant (for example, I0×256), and the current is allocated to the variable current sources301and302according to the phase information MSBa and LSBa. For example, when generating the clock signal CLKa to be interpolated between the clock signals CLKra and CLKrb at 1:3, the variable current source301is set to I0×64 and the variable current source302is set to I0×192.

An n-channel field effect transistor305has a source connected to a ground potential node, and the gate and a drain which are connected to a gate of a transistor306. The n-channel field effect transistor306has a source connected to the ground potential node, the gate connected to the gate of the transistor305, and a drain connected to gates of transistors309and310. The n-channel field effect transistor307has a source connected to the ground potential node, and the gate and a drain which are connected to a gate of a transistor308. The n-channel field effect transistor308has a source connected to the ground potential node, the gate connected to the gate of the transistor307, and a drain connected to sources of transistors311and312.

The n-channel field effect transistor309has the source connected to the drain of the transistor306, a gate connected to the node of the reference clock signal CLKrb, and a drain connected to the node of the first clock signal CLKa. The n-channel field effect transistor310has the source connected to the drain of the transistor306, the gate connected to the reference clock signal CLKrbx, and a drain connected to the node of the first clock signal CLKax. The n-channel field effect transistor311has the source connected to the drain of the transistor308, a gate connected to the node of the reference clock signal CLKrbx, and a drain connected to the node of the first clock signal CLKa. The n-channel field effect transistor312has the source connected to the drain of the transistor308, a gate connected to the node of the reference clock signal CLKrb, and a drain connected to the node of the first clock signal CLKax.

The n-channel field effect transistor317has a source connected to the ground potential node, the gate and a drain which are connected to a gate of the transistor318. The n-channel field effect transistor318has a source connected to the ground potential node, the gate connected to the gate of the transistor317, and a drain connected to sources of transistors313and314. The n-channel field effect transistor319has a source connected to the ground potential node, the gate and a drain which are connected to a gate of a transistor320. The n-channel field effect transistor320has a source connected to the ground potential node, the gate connected to the gate of the transistor319, and a drain connected to sources of transistors315and316.

The n-channel field effect transistor313has the source connected to the drain of the transistor318, a gate connected to the node of the reference clock signal CLKra, and a drain connected to the node of the first reference clock signal CLKa. The n-channel field effect transistor314has the source connected to the drain of the transistor318, a gate connected to the node of the reference clock signal CLKrax, and a drain connected to the node of the first reference clock signal CLKax. The n-channel field effect transistor315has the source connected to the drain of the transistor320, a gate connected to the node of the reference clock signal CLKrax, and a drain connected to the node of the first reference clock signal CLKa. The n-channel field effect transistor316has the source connected to the drain of the transistor320, a gate connected to the node of the reference clock signal CLKra, and a drain connected to the node of the first reference clock signal CLKax. A resistor321is connected between the power source potential node and the node of the first clock signal CLKa. A resistor322is connected between the power source potential node and the node of the first clock signal CLKax.

The first clock signals CLKa and CLKax are generated by weighing each of the four-phase reference clock signals CLKra, CLKrb, CLKrax, CLKrbx and adding them. The first phase interpolation circuit101acan adjust the phases of the first clock signals CLKa and CLKax in a range of 0 degrees to 360 degrees. The high-order bit phase information MSBa is phase information for performing rough adjustment, and the low-order bit phase information LSBa is phase information for performing fine adjustment.

FIG. 2Bis a diagram illustrating examples of input and output signals of the second phase interpolation circuit101b. The second phase interpolation circuit101bhas the same configuration as that of the first phase interpolation circuit101ainFIG. 3. However, the second phase interpolation circuit101breceives input of reference clock signals CLKrb, CLKrax, CLKrbx, CLKra in place of the reference clock signals CLKra, CLKrb, CLKrax, CLKrbx of the first phase interpolation circuit101a, and outputs second clock signals CLKb and CLKbx in place of the first clock signals CLKa and CLKax of the first phase interpolation circuit101a. When a shift amount SD is “0,” the second clock signals CLKb and CLKbx are signals delayed by 90 degrees with respect to the first clock signals CLKa and CLKax as illustrated inFIG. 5C.

InFIG. 1, a first determinator102asamples center data of the input data Di in synchronization with the edge of the first clock signal CLKa as illustrated inFIG. 5C, performs binary determination on the sampled center data, and outputs center data Do. Concretely, the first determinator102aoutputs the center data Do of “1” when the center data is larger than a threshold value, and outputs the center data Do of “0” when the center data is smaller than the threshold value. The phase of the edge of the first clock signal CLKa is adjusted by the first phase interpolation circuit101ato the center phase of the input data Di.

A second determinator102bsamples transition point data of the input data Di in synchronization with the edge of the second clock signal CLKb as illustrated inFIG. 5C, performs binary determination on the sampled transition point data, and outputs transition point data Bd. Concretely, the second determinator102boutputs the transition point data Bd of “1” when the transition point data is larger than a threshold value, and outputs the transition point data Bd of “0” when the transition point data is smaller than the threshold value. The phase of the edge of the second clock signal CLKb is adjusted by the second phase interpolation circuit101bto the transition point phase of the input data Di.

A phase detection circuit103detects the phase on the basis of the center data Do and the transition point data Bd, and outputs an up signal UP and a down signal DN.

FIG. 4Ais a diagram illustrating a configuration example of the phase detection circuit103inFIG. 1, andFIG. 4Bis a chart illustrating a truth table of input and output of the phase detection circuit103. Center data Do[n+1] is the center data Do of (n+1)th bit data. Transition point data Bd[n] is the transition point data Bd of nth bit data. Center data Do[n] is the center data Do of the nth bit data. An exclusive logical sum (XOR) circuit401outputs an exclusive logical sum of the center data Do[n+1] and the transition point data Bd[n] as the up signal UP. An exclusive logical sum (XOR) circuit402outputs an exclusive logical sum of the transition point data Bd[n] and the center data Do[n] as the down signal DN.

For example, in the case where the center data Do[n] is “1,” the transition point data Bd[n] is “1” and the center data Do[n+1] is “0” as illustrated inFIG. 4C, the actual phase of the transition point is delayed from the phase of the transition point data Bd[n], and therefore the down signal DN of “1” and the up signal UP of “0” are outputted in order to delay the phases of the clock signals CLKa and CLKb.

In the case where the center data Do[n] is “0,” the transition point data Bd[n] is “1” and the center data Do[n+1] is “1” as illustrated inFIG. 4D, the actual phase of the transition point is advanced from the phase of the transition point data Bd[n], and therefore the up signal UP of “1” and the down signal DN of “0” are outputted in order to advance the phases of the clock signals CLKa and CLKb.

A filter105inFIG. 1is a low-pass filter that performs low-pass filtering (integration) on the up signal UP and the down signals DN and thereby removes noise and outputs first phase information PH. An adder106adds the shift amount SD to the first phase information PH and thereby outputs the second phase information MSBa.

The first phase interpolation circuit101aroughly adjusts the phase of the first clock signal CLKa on the basis of the second phase information MSBa. The second phase interpolation circuit101breceives input of the first phase information PH as the high-order bit phase information MSBb and roughly adjusts the phase of the second clock signal CLKb on the basis of the high-order bit phase information MSBb. When the shift amount SD is 0, the phase information MSBa and the phase information MSBb are the same, and the phase difference between the first clock signal CLKa and the second clock signal CLKb is 90 degrees. In the case ofFIG. 4C, the phases of the clock signals CLKa and CLKb are corrected in a delay direction by the phase interpolation circuits101aand101b. In the case ofFIG. 4D, the phases of the clock signals CLKa and CLKb are corrected in an advance direction by the phase interpolation circuits101aand101b. This enables the first determinator102ato sample the center data and the second determinator102bto sample the transition point data.

Here, the phase difference between the first clock signal CLKa and the second clock signal CLKb sometimes shifts from 90 degrees due to the difference between the load or the wiring length of the first clock signal CLKa and the load or the wiring length of the second clock signal CLKb. In this case, to correct the phase difference between the first clock signal CLKa and the second clock signal CLKb to 90 degrees, the shift amount SD is inputted. Inputting the shift amount SD makes it possible to correct the phase difference between the first clock signal CLKa and the second clock signal CLKb to 90 degrees.

Ideally, the phase interpolation circuits101aand101bare circuits that interpolate between the four-phase reference clock signals ra, rb, rax, rbx at regular intervals. Actually, however, the first clock signal CLKa and the second clock signal CLKb have non-linearity to the phase information PH as illustrated inFIG. 5A. When the shift amount SD is 0, the phase interpolation circuits101aand101bhave the same circuit configuration inFIG. 3and have the same non-linearity. In this case, as illustrated inFIG. 5B, the phase difference between the first clock signal CLKa and the second clock signal CLKb can be kept at the same phase difference (90 degrees) to the phase information PH at all times. In this case, as illustrated inFIG. 5C, the phase difference between the first clock signal CLKa and the second clock signal CLKb is kept at 90 degrees, so that the edge of the first clock signal CLKa can keep the phase of the center data, and the edge of the second clock signal CLKb can keep the phase of the transition point data.

However, when the shift amount SD is not 0, the characteristics of the first clock signal CLKa inFIG. 5Amove in a conceptually oblique direction. Therefore, the non-linearity of the first clock signal CLKa and the non-linearity of the second clock signal CLKb are different from each other. In this case, as illustrated inFIG. 5D, the phase difference between the first clock signal CLKa and the second clock signal CLKb is not kept at the same phase difference (90 degrees) to the phase information PH but has a vibration width WD. In this case, as illustrated inFIG. 5E, the phase of the first clock signal CLKa with respect to the second clock signal CLKb vibrates at the vibration width WD having a minimum phase501and a maximum phase502. In this case, the edge of the first clock signal CLKa cannot keep the phase of the center data but increases in determination error rate (bit error rate) of the first determinator102a.

FIG. 6Ais a chart illustrating a bit error rate (BER)601with respect to the shift amount SD. A first clock signal CLKa indicated with a broken line is a clock signal when the shift amount SD is 0 and located in the phase of the center data, and thus has an extremely low bit error rate. In contrast, a first clock signal CLKa indicated with a solid line is a clock signal when the shift amount SD is d (for example, −4) and shifted from the phase of the center data, and thus has a relatively high bit error rate. When SD=d, a phase602of the first clock signal CLKa with respect to the second clock signal CLKb vibrates with respect to the phase information PH as described above. When the phase602vibrates, the bit error rate601corresponding to the phase602also vibrates. For example, the bit error rate601becomes a minimum bit error rate BERj when the phase information PH is j, and becomes a maximum bit error rate BERk when the phase information PH is k.

An average bit error rate BERave is an average value of all bit error rates corresponding to the vibrating phase602and is a bit error rate corresponding to the average value of the vibrating phase602. Since the bit error rate BERk is higher than the average bit error rate BERave, the absolute value of the phase (skew) of the first clock signal CLKa with respect to the second clock signal CLKb can be determined to be larger than the average value at the phase information PH=k. In this case, at the phase information PH=k, third phase information LSBa for delaying the phase of the first clock signal CLKa is generated so that the phase of the first clock signal CLKa becomes the average phase.

In contrast, since the bit error rate BERj is lower than the average bit error rate BERave, the absolute value of the phase (skew) of the first clock signal CLKa with respect to the second clock signal CLKb can be determined to be smaller than the average value at the phase information PH=j. In this case, at the phase information PH=j, third phase information LSBa for advancing the phase of the first clock signal CLKa is generated so that the phase of the first clock signal CLKa becomes the average phase.

The first phase interpolation circuit101afinely adjusts the phase of the first clock signal CLKa on the basis of the third phase information LSBa. This makes it possible to decrease the vibration of the phase602of the first clock signal CLKa with respect to the second clock signal CLKb and keep the phase602almost constant at the shift amount SD=d. When the shift amount SD=d, it is possible to decrease the vibration of the phase602and make the phase difference between the first clock signal CLKa and the second clock signal CLKb almost constant.

Here, when the shift amount SD is near 0, the bit error rate is extremely low. As a result, the bit error rate of each piece of phase information PH is almost the same, so that it is difficult to generate the phase information LSBa by the above-described method. In this case, the following method is used.

A case of using the receiver circuit at the shift amount SD=d+e (for example, −1) will be described as an example. First, the phase information LSBa at the shift amount SD=d (for example, −4) is calculated by the above-described method. Next, the phase information LSBa at the shift amount SD=e (for example, +3) is similarly calculated. Then, on the basis of the phase information LSBa at the shift amount SD=d and the phase information LSBa at the shift amount SD=e, the phase information LSBa at the shift amount SD=d+e is calculated. By inputting d+e as the shift amount SD and inputting the phase information LSBa at the shift amount SD=d+e into the first phase interpolation circuit101a, the phase difference between the first clock signal CLKa and the second clock signal CLKb is made almost constant, thereby decreasing the determination error rate of the first determinator102a.

FIG. 7is a chart illustrating the phases (delayed time) of the first clock signal CLKa and the second clock signal CLKb with respect to the phase information PH. The phase information PH periodically changes in a range, for example, 0 to 31. PH=32 is the same as PH=0, and the next to PH=31 is PH=0. Clock signals CLKa and CLKb indicated with broken lines are clock signals with ideal linear characteristics. Clock signals CLKa and CLKb indicated with solid lines are clock signals with actual non-linear characteristics. In this case, each piece of the high-order bit phase information MSBa and MSBb is 5 bits of 0 to 31, and, for example, each piece of the low-order bit phase information LSBa and LSBb is 2 bits.

Here, it is assumed that the phase of the first clock signal CLKa is Da and the phase of the second clock signal CLKb is Db. K is the phase in a range of 0 to 31. If k is a value outside the range, the remainder after division of k by 32 can be reread as k. It is assumed that the slope with respect to the phase information PH is 1 as illustrated inFIG. 7. The phase is 0 degrees when k=0, the phase is 360/32=11.25 degrees when k=1, . . . , the phase is 348.75 degrees when k=31. The phase difference between the first clock signal CLKa and the second clock signal CLKb is almost k=8 (90 degrees). A non-linearity E(k) is a difference between the clock signal of the solid line and the clock signal of the broken line. The non-linearity E(k) is mainly decided by the circuit structures and the characteristics such as band and so on of the phase interpolation circuits101aand101b, and is therefore the common value in the phase interpolation circuits101aand101bwhen the shift amount SD=0.

Therefore, the following expressions are established.
Da(k)=k+E(k)
Db(k)=8+k+E(k)

In this case, Db(k)−Da(k) is 8 irrespective of the phase information PH, so that the phase difference between the first clock signal CLKa and the second clock signal CLKb can be said to still keep 90 degrees even with the non-linearity E(k).

Here, a case where the shift amount SD is applied will be described. SD=d and SD=e are outside the center phase of the input data Di, and the bit error rate is relatively large. Here, it is assumed that the phase Da(k) when SD=d is applied is Dad(k). The phase Dad(k) is expressed by the following expression.
Dad(k)=Da(k+d)=k+d+E(k+d)

Thus, the following expression is established.
Db(k)−Dad(k)=8−d+{E(k)−E(k+d)}

Thus, an error of {E(k)−E(k+d)} occurs according to the phase information PH(=k), so that the first clock signal CLKa vibrates with respect to the second clock signal CLKb. To correct the error due to the vibration, a correction amount Cd(k) corresponding to the phase information PH(=k) and the shift amount SD (=d) is calculated by the following expression.
Cd(k)={E(k)−E(k+d)}

By rewriting the above expression, the following expression is established, so that the phase of the first clock signal CLKa with respect to the second clock signal CLKb after correction can keep a constant phase relation irrespective of the phase information PH(=k).
Db(k)={Dad(k)+Cd(k)}=8−d

Next, as in the following expression, Cd(k) is shifted by −d and then applied to the phase Db(k), and SD=e is applied to Da(k). Here, it is assumed that the phase Da(k) when SD=e is applied is Dae(k).
Db(k)+Cd(k−d)=8+k+E(k)+{E(k−d)−E(k)}
Dae(k)=Da(k+e)=k+e+E(k+e)

The phase difference between the two clock signals is expressed by the following expression.

Next, by the following expression, a correction amount Cde(k) at SD=d+e is calculated.
Cde(k)=E(k−d)−E(k+e)

Next, as in the following expression, the correction amount Cde(k) is shifted by d and then applied to the phase Da(d+e). In this event, it is set that SD=d+e. Then, the correction amount applied to Db(k) is canceled.

The difference between them is expressed by the following expression and has no relation with the phase information PH (=k).
Db(k)−{Da(d+e)+Cde(k+d)}=8−(d+e)

Accordingly, it can be said that the vibration of the first clock signal CLKa with respect to the second clock signal CLKb is eliminated with SD=d+e applied. If d and e are not found as the shift amount SD which enables measurement of the bit error rate, further division is performed and correction amounts are added by the same means using SD=d1+d2+d3 . . . to thereby enable calculation of the correction amount for an arbitrary shift amount SD.

A pattern checker104inFIG. 1detects an error signal ER of the center data Do being the determination value of the first determinator102a. As initiation processing after power-on of the receiver circuit, the receiver circuit receives input of the input data Di of a test pattern. The test pattern is time-series known data based on a generating polynomial. The pattern checker104determines whether or not the center data Do with respect to the input data Di of the test pattern coincides with an expected value, and outputs the error signal ER of “0” when they coincide, and outputs an error signal ER of “1” when they do not coincide.

A corrector107has a bit error rate comparison circuit108, adders109a,109b, and correction code registers REGa and REGb. The bit error rate comparison circuit108receives input of the error signal ER and the phase information PH and outputs correction amounts CUP and CDN.

FIG. 8is a diagram illustrating a configuration example of the bit error rate comparison circuit108inFIG. 1. A logical product (AND) circuit802outputs a logical product signal of the clock signal CLK and the output signal of a comparison circuit806. The clock signal CLK has a frequency corresponding to the bit rate of the input data Di. A pattern counter810counts the number of pulses of the output signal of the logical product circuit802. The comparison circuit806outputs 0 when the count value of the pattern counter810and a pattern maximum value PTN_MAX coincide, and outputs 1 when they do not coincide. The pattern maximum value PTN_MAX is the number of patterns (the number of pieces of data) necessary for generating the phase information (correction amount) LSBa and is, for example, one million. More specifically, the comparison circuit806outputs 1 until the number of patterns of the input data Di of the test pattern reaches PTN_MAX and outputs 0 when it reaches PTN_MAX.

A logical product circuit801outputs a logical product signal of the error signal ER and the output signal of the comparison circuit806. An error counter808counts the number of pulses of the output signal of the logical product circuit801. More specifically, the error counter808outputs the number of patterns having an error signal ER of 1 in the total number of patterns PTN_MAX of the test pattern, as the average bit error rate BERave.

A comparison circuit805outputs 1 when the phase information PH and a variable k coincide, and outputs 0 when the phase information PH and a variable k do not coincide. The frequency corresponding to the bit rate of the input data Di is the same as the frequency of the clock signal of the transmitter circuit. In contrast, the clock signals CLKa and CLKb are clock signals of the receiver circuit. The clock signal of the transmitter circuit and the clock signal of the receiver circuit are asynchronous. Therefore, the frequency corresponding to the bit rate of the input data Di is slightly different from the frequencies of the clock signals CLKa and CLKb. Accordingly, the phase information PH changes circulating in the range of 0 to 31 with time. The variable k is sequentially changed in the range of 0 to 31. For instance, first, by setting k=0, a bit error rate BER0 is detected. Then, by setting k=1, a bit error rate BER1 is detected. Similarly, bit error rates BER2 to BER31 can be detected.

A logical product circuit803outputs a logical product signal of the error signal ER and the output signal of the comparison circuit805. An error counter809counts the number of pulses of the output signal of the logical product circuit803. More specifically, the comparison circuit809counts the number of patterns of an error signal ER=1 at PH=k and outputs a bit error rate BERk when PH=k.

A logical product circuit804outputs a logical product signal of the clock signal CLK and the output signal of the comparison circuit805. A pattern counter811counts the number of pulses of the output signal of the logical product circuit804. More specifically, the pattern counter811counts the number of patterns of PH=k. A comparison circuit807outputs 0 when the count value of the pattern counter811and the pattern maximum value PTN_MAX coincide, and outputs 1 when they do not coincide. More specifically, the comparison circuit807outputs 0 until the number of patterns of PH=k in the input data Di of the test pattern reaches PTN_MAX and outputs 1 when it reaches PTN_MAX.

A comparison circuit812receives input of the output signal of the comparison circuit807as a trigger signal trig, and compares the average bit error rate BERave and the bit error rate BERk when the trigger signal trig becomes 1. Then, when the bit error rate BERk is smaller than the average bit error rate BERave, the comparison circuit812outputs a phase correction amount CUP corresponding to BERave−BERk so as to increase the bit error rate BERk up to the average bit error rate BERave. Further, when the bit error rate BERk is larger than the average bit error rate BERave, the comparison circuit812outputs a phase correction amount CDN corresponding to BERk−BERave so as to decrease the bit error rate BERk down to the average bit error rate BERave. Note that the counters808to811are reset when the output value of the comparison circuit807becomes 1.

By sequentially changing the variable k from 0 to 31 as described above, the increment signal CUP and the decrement signal CDN with a correction amount at each phase of 0 to 31 are outputted.

InFIG. 1, the correction amount Cd in each phase of 0 to 31 inputted from the bit error rate comparison circuit108is held in the correction code register REGa, so that the correction amount Cd is updated by the increment signal CUP and the decrement signal CDN. The adder109aadds the phase information PH and a phase SAa and outputs the resultant. The adder109badds the phase information PH and a phase SAb and outputs the resultant. The correction code register REGa outputs the correction amount corresponding to the phase outputted from the adder109a, as the phase information LSBa to the first phase interpolation circuit101a. The correction code register REGb outputs the correction amount corresponding to the phase outputted from the adder109b, as the phase information LSBb to the second phase interpolation circuit101b. Hereinafter, its details will be described.

FIG. 9is a flowchart illustrating the processing method of the receiver circuit inFIG. 1, andFIGS. 10A to 10Hare charts illustrating a phase adjustment method of the first clock signal CLKa and the second clock signal CLKb. First, in the initial state, SD=0, and the first clock signal CLKa and the second clock signal CLKb have the non-linearity E(k) with respect to the phase k of 0 to 31 as illustrated inFIG. 10A. The phase k indicates the phase of 0 to 31 as with the phase information PH. The non-linearity E(k) is the difference between the clock signal of the solid line and the clock signal of the broken line inFIG. 7.

First, at Step S901, the receiver circuit sets the shift amount SD=d and the variable k=0. The adder106outputs the phase made by adding the shift amount SD=d to the phase information PH as the phase information MSBa to the first phase interpolation circuit101a. Then, the first clock signal CLKa inFIG. 10Ais subjected to phase shift with the shift amount SD=d, whereby the first clock signal CLKa is adjusted in phase as illustrated inFIG. 10B.

Next, at Step S902, the receiver circuit calculates the correction amount Cd(k) by the following expression and writes the correction amount Cd(k) into the register REGa.
Cd(k)={E(k)−E(k+d)}

Next, at Step S903, the receiver circuit determines whether or not the variable k is the same as a phase maximum value PI_MAX. The phase maximum value PI_MAX is, for example, 31. The processing proceeds to Step S905if they are the same, and proceeds to Step S904if they are not the same.

At Step S904, the receiver circuit increments the variable k and returns to Step S902and repeats the above processing. Thus, each correction amount Cd(k) of k=0 to 31 is written into the register REGa. As a result, the first clock signal CLKa is adjusted in phase as illustrated inFIG. 10C.

At Step S905, the receiver circuit copies all correction amounts Cd(k) in the register REGa to the register REGb.

Next, at Step S906, the receiver circuit sets the phase SAb=d. The adder109badds the phase SAb=d to the phase information PH. Then, the second clock signal CLKb is adjusted in phase as illustrated inFIG. 10D.

Next, at Step S907, the receiver circuit sets the shift amount SD=e and the variable k=0. The adder106outputs the phase made by adding the shift amount SD=e to the phase information PH as the phase information MSBa to the first phase interpolation circuit101a. Then, the first clock signal CLKa inFIG. 10Dis subjected to phase shift with the shift amount SD=e, whereby the first clock signal CLKa is adjusted in phase as illustrated inFIG. 10E.

Next, at Step S908, the receiver circuit calculates the correction amount Cde(k) by the following expression and writes the correction amount Cde(k) into the register REGa.
Cde(k)=E(k−d)−E(k+e)

Next, at Step S909, the receiver circuit determines whether or not the variable k is the same as the phase maximum value PI_MAX. The phase maximum value PI_MAX is, for example, 31. The processing proceeds to Step S911if they are the same, and proceeds to Step S910if they are not the same.

At Step S910, the receiver circuit increments the variable k and returns to Step S908and repeats the above processing. Thus, each correction amount Cde(k) of k=0 to 31 is written into the register REGa. As a result, the first clock signal CLKa is adjusted in phase as illustrated inFIG. 10F.

At Step S911, the receiver circuit clears all phase correction amounts in the register REGb. Thus, the register REGb outputs the phase information LSBb of “0” at all times irrespective of the output value of the adder109b.

Next, at Step S912, the receiver circuit sets the phase SAa=d. The adder109aadds the phase SAa=d to the phase information PH. Then, the first clock signal CLKa is adjusted in phase as illustrated inFIG. 10G, and the second clock signal CLKb returns to the state inFIG. 10Aby clearing the register REGb.

Next, at Step S913, the receiver circuit sets the shift amount SD=d+e. The adder106outputs the phase made by adding the shift amount SD=d+e to the phase information PH as the phase information MSBa to the first phase interpolation circuit101a. Then, the first clock signal CLKa is adjusted in phase as illustrated inFIG. 10H.

This generates the first clock signal CLKa and the second clock signal CLKb at the shift amount SD=d+e. The register REGa outputs the correction amount Cde(k) according to the output value of the adder109aas the phase information LSBa. The register REGb outputs the phase information LSBb of “0” at all times. Since the first clock signal CLKa is corrected by the correction amount Cde(k) in the register ERGa, the phase difference between the first clock signal CLKa and the second clock signal CLKb becomes almost constant irrespective of the phase information PH. Since the vibration of the first clock signal CLKa with respect to the second clock signal CLKb is decreased, the first determinator102acan sample the center of the input data Di to decrease the determination error rate.

FIG. 11is a diagram illustrating a configuration example of a receiver circuit according to another embodiment. The receiver circuit inFIG. 11is made by adding a first delay circuit1101aand a second delay circuit1101bto the receiver circuit inFIG. 1. Hereinafter, the points of the receiver circuit inFIG. 11different from the receiver circuit inFIG. 1will be described.

A first phase interpolation circuit101aadjusts the phase of a first clock signal CLKa only using phase information MSBa. A second phase interpolation circuit101badjusts the phase of a second clock signal CLKb only using phase information MSBb. The first delay circuit1101adelays the output signal of the first phase interpolation circuit101aaccording to the phase information LSBa to thereby adjust the phase of the first clock signal CLKa, and outputs the first clock signal CLKa to a first determinator102a. The second delay circuit1101bdelays the output signal of the second phase interpolation circuit101baccording to the phase information LSBb to thereby adjust the phase of the second clock signal CLKb, and outputs the second clock signal CLKb to a second determinator102b. In this case, the first phase interpolation circuit101aand the first delay circuit1101aconstitute a first phase adjuster, and the second phase interpolation circuit101band the second delay circuit1101bconstitute a second phase adjuster.

A corrector107generates phase information LSBa for decreasing the variation in phase difference of the first clock signal CLKa with respect to the second clock signal CLKb. The first phase adjuster adjusts the phase of the first clock signal CLKa on the basis of the phase information MSBa and the phase information LSBa. The second phase adjuster adjusts the phase of the second clock signal CLKb on the basis of the phase information PH. Provision of the corrector107makes it possible to decrease the variation in phase difference between the first clock signal CLKa and the second clock signal CLKb and thereby decrease the occurrence rate of data error.

In the case ofFIG. 1, the first phase adjuster has the first phase interpolation circuit101athat generates the first clock signal CLKa by performing phase interpolation on the plurality of reference clock signals CLKra, CLKrb, CLKrax, CLKrbx on the basis of the phase information MSBb and the phase information LSBb. The second phase adjuster has the second phase interpolation circuit101bthat generates the second clock signal CLKb by performing phase interpolation on the plurality of reference clock signals CLKrb, CLKrax, CLKrbx, CLKra, on the basis of the phase information PH (=MSBb). Note that after the register REGb is cleared, the phase information LSBb becomes 0.

In the case ofFIG. 11, the first phase adjuster has the first phase interpolation circuit101athat generates the clock signal by performing phase interpolation on the plurality of reference clock signals CLKra, CLKrb, CLKrax, CLKrbx on the basis of the phase information MSBa, and the first delay circuit1101athat generates the first clock signal CLKa by delaying the clock signal generated by the first phase interpolation circuit101aon the basis of the phase information LSBa. The second phase adjuster has the second phase interpolation circuit101bthat generates the second clock signal CLKb by performing phase interpolation on the plurality of reference clock signals CLKrb, CLKrax, CLKrbx, CLKra on the basis of the phase information PH (=MSBb). Note that after the register REGb is cleared, the phase information LSBb=0, so that the second delay circuit1101bdoes not perform delay but the second phase interpolation circuit101bgenerates the second clock signal CLKb.

The corrector107generates the phase information LSBa for decreasing the variation in bit error rate BERk for each phase of the determination value of the first determinator102a. Concretely, the corrector107generates the phase information LSBa on the basis of the bit error rate BERk for each phase of the determination value of the first determinator102aand the average value BERave of the bit error rate for each phase. The corrector107further generates the phase information LSBa on the basis of the bit error rate BERk when the adder106adds a first shift amount d and the bit error rate BERk when the adder106adds a second shift amount e.

As described above, the phase difference of the first clock signal CLKa with respect to the second clock signal CLKb has a correlation with the bit error rate BERk corresponding thereto. Accordingly, the corrector107calculates the average value of the phase difference of the first clock signal CLKa with respect to the second clock signal CLKb and generates the phase information LSBa on the basis of the phase difference of the first clock signal CLKa with respect to the second clock signal CLKb and the average value.

Note that the above-described embodiments merely illustrate concrete examples of implementing the present invention, and the technical scope of the present invention is not to be construed in a restrictive manner by these embodiments. That is, the present invention may be implemented in various forms without departing from the technical spirit or main features thereof.

Provision of a corrector makes it possible to decrease the variation in phase difference between a first clock signal and a second clock signal and thereby decrease the occurrence rate of data error.