Adaptive dual-slope frequency controller for adjusting power conversion

This specification discloses a adaptive dual-slope frequency controller for adjusting power conversion of a power supply. The converter can adjust its operating frequency according to the status of a load device. A feedback voltage, representing the load status, is used to control two pairs of charging/discharging currents of a storage capacitor in the present controller, thereby controlling the period of the voltage waveform at the capacitor. This controller can especially lower the frequency of the gate pulse of power supply to improve the overall efficiency at light load and no load.

BACKGROUND OF THE INVENTION

1. Field of Invention

The invention relates to a frequency controller for adjusting power conversion and, in particular, to a adaptive dual-slope frequency controller for adjusting power conversion.

2. Related Art

In the circuit of the power supply2shown inFIG. 1, the power converter4is used to receive an external input voltage Vin and to provide an output voltage Vo to the load device6. The feedback control circuit8outputs an appropriate gate pulse to the power converter4according to the output voltage Vo in order to provide an appropriate power to the load device6. For example, when the load device6is at heavy load, the feedback control circuit8makes the power converter4to provide a larger power output to satisfy the system's needs. On the other hand, if the load device6is at light load, the feedback control circuit8makes the power converter4to provide a smaller power output to save energy. The power converter4can be a buck converter, a boost converter, a fly back converter, or a forward converter, depending upon different specification needs. The feedback control circuit8mostly adjusts the output power of the power converter4by pulse width modulation (PWM). From the above description, it is seen that the feedback control circuit8is the key role of affecting the efficiency of a power supply2.

FIG. 2is the block diagram of a conventional feedback control circuit8. It includes an error amplifier11, a reference voltage generator12, a comparator,13, an oscillator14, an SR inverter15, a gate drive16, and feedback compensation circuits17,18.

We useFIG. 3to describe the principle of the conventional feedback control circuit8. When an output voltage Vo enters the positive terminal of the error amplifier11via the feedback compensation circuit18, the error amplifier11compares it with a reference voltage Vref generated by the reference voltage generator12. It further feeds an amplified error voltage Ve to the positive terminals of the feedback compensation circuit17and the comparator13. The feedback compensation circuits17,18are circuits composed of resistors and capacitors. Their purpose is to stabilize the closed-loop feedback compensation of the power supply2.

The comparator13compares the error voltage Ve and the voltage on the switch current CS of the switch chip (not shown) in order to generate a reset signal to the SR flip-flop15. If the voltage is smaller than the voltage on the switch current CS of the switch chip, then the reset signal is a low voltage and so is the gate pulse. If the voltage is greater than the voltage on the switch current CS of the switch chip, then the reset signal is a high voltage and the voltage of the gate pulse is determined by the oscillation output signal CLKOUT of the oscillator14. On the other hand, the oscillation output signal CLKOUT generated by the oscillator14periodically restores the gate pulse to the high voltage.

Therefore, the pulse width of the gate pulse determines the output power of the power converter4. However, the frequency of the oscillation output signal CLKOUT is fixed. This in turn infers that the frequency of the gate pulse is also fixed. A fixed gate pulse will result in large power consumption in light load and no load conditions.

SUMMARY OF THE INVENTION

A primary objective of the invention is to provide a adaptive dual-slope frequency controller, which enables a power converter to adjust its operating frequency according to the load status of the load device.

The present controller accomplishes the frequency modulation by controlling the charge/discharge current of the capacitor by an error voltage Ve. The period of the voltage Vramp at the capacitor can thus be controlled to adjust the frequency of the gate pulse.

The disclosed adaptive dual-slope frequency controller contains a storage capacitor; a first charging current source coupled to the capacitor via a first switch; a first discharging current source coupled to the capacitor via a second switch; a second charging current source coupled to the capacitor via a third switch; a second discharging source coupled to the capacitor via a fourth switch; a conversion circuit to receive an error voltage Ve and output a corresponding conversion signal to the charging current sources; and a control circuit to receive the voltage at the capacitor, a high-level voltage reference, and a low-level voltage reference and output a control signal and an output pulse. The control signal controls the charge/discharge current on the first charging current source, the first discharging current source, the second charging current source, and the second discharging current source to control the period of the voltage waveform at the capacitor, thereby controlling the frequency of a gate pulse.

DETAILED DESCRIPTION OF THE INVENTION

As shown inFIG. 4, the disclosed adaptive dual-slope frequency controller40contains four sets of current sources: the first charging current source Ic141, the first discharging current source Id142, the second charging current source Ic243, and the second discharging current source Id244; four sets of current control switches: the first switch SW1411, the second switch SW2421, the third switch SW3431, and the fourth switch SW4441; a storage capacitor45, a control circuit46, a charge/discharge circuit47, and a conversion circuit48.

The storage capacitor45is used to perform charge/discharge. The first charging current source Ic141is coupled to the storage capacitor45via the first switch SW1411. The first discharging current source Id142is coupled to the storage capacitor45via the second switch SW2421. The second charging current source Ic243is coupled to the storage capacitor45via the third switch SW3431. The second discharging source Id244is coupled to the storage capacitor45via the fourth switch SW4441. The conversion circuit48refers to an error voltage Ve and outputs a corresponding conversion signal to the second charging current source Ic243, adjusting the charging current absorbed by the second charging current source Ic243. According to the voltage on the switch current CS, a reset signal is output to a corresponding switch SW1˜SW4. However, the conversion circuit48can be coupled to any of the current sources41˜44in a single or multiple means. It is not limited by the embodiment disclosed herein.

The control circuit46is used to receive a capacitor voltage Vramp, a high voltage reference VH, a low voltage reference VL, and to output a control signal (including a first and a second control signals) and an output pulse CLKOUT. A main feature of the invention is in that the control signal controls the charging/discharging current of the storage capacitor45via the first charging current source Ic141, the first discharging current source Id142, the second charging current source Ic243, and the second discharging source Id244. The period of the capacitor voltage Vramp is thus controlled to adjust the frequency of a gate pulse.

FIG. 5schematically shows the oscillation period and the operation of the four switches. The oscillation period T of the disclosed adaptive dual-slope frequency controller is equal to Tc1+Td1+Tc2+Td2. When the storage capacitor45is charged for the first time Tc1, the first switch411is is conductive while the second, third, and fourth switches421,431,441are turned off. When the storage capacitor45is discharged for the first time Td1, the second switch421is is conductive while the first, third, and fourth switches411,431,441are turned off. When the storage capacitor45is charged for the second time Tc2, the third switch431is is conductive while the first, second, and fourth switches411,421,441are turned off. When the storage capacitor45is discharged for the second time Td2, the fourth switch441is conductive while the first, second, and third switches411,421,431are turned off.

The control circuit46shown inFIG. 6contains: a comparator61, a T flip-flop62, a first inverter63, a second inverter64, and a pulse generator65. The comparator61uses two negative-terminal reference voltages VH, VL and a positive-terminal capacitor charge/discharge voltage signal Vramp to control its output. The switch between VH and VL is further controlled by a first control signal CSL output of the comparator61. When the first control signal is Hi, the negative-terminal reference voltage of the comparator61is switched from VH to VL. When the output signal CSL is LO, the negative terminal reference voltage of the comparator61is switched from VL to VH. OUTB is the control output signal of the first inverter63. The T flip-flop62receives the first control signal OUT and, after a negative-edge trigger, outputs a second control signal. The pulse generator65here is preferably to be a negative-edge trigger pulse generator65that outputs a pulse CLKOUT. However, it should not be taken to restrict the scope of the invention. The disclosed control circuit46makes use of the output control signals CK1, CK2, CK3, and CK4of two sets of logic control circuits. CK1and CK2determine the first capacitor charge/discharge period, and CK3and CK4determine the second capacitor charge/discharge period. CK1, CK2, CK3, and CK4are enabled by the T flip-flop62outputting a second control signal Q and the control signal QB of second inverter64.

In the following, we useFIG. 7to describe the action of the circuit.

When the storage capacitor45is charged for the first time Tc1: When the input capacitor voltage Vramp on the positive terminal of the comparator61exceeds the negative terminal input reference voltage VH, the output of the comparator61is turned to Hi. The output of the T flip-flop62is unchanged, remaining at Lo. CK1turns to Lo, and CK2turns to Hi. The storage capacitor45starts to discharge. At the same time, the negative terminal reference voltage of the comparator61is transited from VH to VL.

When the storage capacitor45is discharged for the first time Td1: After the end of the Tc1period, the negative terminal reference voltage of the comparator61is transited from VH to VL. When the positive terminal input capacitor voltage Vramp of the comparator61is lower than the negative terminal input reference voltage VL, the output OUT of the comparator61further is turned to Lo. The T flip-flop62is triggered so that its output Q changed to Hi. Therefore, CK2turns to Lo, and CK3turns to Hi. The storage capacitor45is further charged. At the same time, the negative terminal reference voltage of the comparator61is switched from VL to VH.

When the storage capacitor45is charged for the second time Tc2: When the positive terminal input capacitor voltage Vramp of the comparator61exceeds the negative terminal input reference voltage VH, the output OUT of the comparator61is turned to Hi. The output of the T flip-flop62is unchanged, remaining at Hi. CK3turns to LO, and CK4turns to Hi. The storage capacitor45starts to discharge. At the same time, the negative terminal reference voltage of the comparator61is switched from VH to VL.

When the storage capacitor45is discharged for the second time Td2: After the end of the Tc2period, the negative reference voltage of the comparator61is switched from VH to VL. When the positive terminal input capacitor voltage Vramp of the comparator61is lower than the negative terminal input reference voltage VL, the output of the comparator61further changes to Lo. The T flip-flop62is triggered so that its output Q changes to Lo. At the same time, the triggering negative edge triggers the pulse generator65to output a pulse CLKOUT, enabling the start of the next period. CK4turns to Lo, and CK turns to Hi. The storage capacitor45is charged again. The negative terminal reference voltage of the comparator61is switched from VL to VH.

To summarize, we useFIG. 8to show the timing chart of the operations of the disclosed adaptive dual-slope frequency control circuit. The error voltage Ve and the switch current CS determines when to generate a reset signal. Dual-slope voltage signal (Vramp) determines one period of enabling pulse wave, CLKOUT. The reset signal determines when to shut down the gate pulse, and the CLKOUT signal determines when to enable it.

Therefore, the invention uses the error voltage Ve that enters the conversion circuit48to control the charge/discharge current of the storage capacitor45, thereby controlling the period of the Vramp. In the end, the invention achieves the goal of controlling the frequency of the gate pulse.FIG. 9is a first embodiment circuit of the disclosed adaptive dual-slope frequency control circuit. The conversion circuit90is another embodiment of the conversion circuit48inFIG. 6. The conversion circuit90uses an adder to subtract a certain voltage Vc from the error voltage Ve, the result of which controls the voltage and outputs a corresponding conversion signal to the second charging current source Ic243, adjusting its charging current. Thus, the second charging current source Ic243and the error voltage Ve have a functional relation. It can be a first-order, second-order, or exponential function; however, the invention is not limited by these examples. With reference toFIGS. 9-1to9-3, when the power supply is at a heavy load, the second charging current source Ic243extracts a maximum current I2to charge the storage capacitor45. At this moment, the frequency of the oscillation output signal CLKOUT is the highest frequency F2and the charge period is the shortest Tc2,1. When the load reduces to its minimum, the second charging current source Ic243extracts a minimum current I1to charge the storage capacitor45. At this moment, the frequency of the oscillation output signal CLKOUT reaches its minimum frequency F1and the charge period reaches its maximum Tc2,2.

FIG. 10shows a second embodiment circuit diagram of the disclosed adaptive dual-slope frequency control circuit. The conversion circuit100is another embodiment of the conversion circuit48inFIG. 6. The conversion circuit100uses a comparator with a hysteresis. The hysteresis phenomenon of the amplifier is used to reduce the sensitivity of the comparator to the error voltage Ve. When the error voltage Ve is greater than a larger voltage V2or smaller than a smaller voltage V1, the output signal of the amplifier can enable the function of the second charging current Ic243. If the error voltage Ve is between the larger voltage V2and the smaller voltage V1, the output signal of the comparator is unchanged. With reference toFIGS. 10-1to10-3, when the power supply is at a heavy load, the second charging current source Ic243extracts a maximum current I2to charge the storage capacitor45. At this moment, the frequency of the oscillation output signal CLKOUT is the highest frequency F2and the charge period is the shortest Tc2,1. When the load reduces to its minimum, the second charging current source Ic243extracts a minimum current I1to charge the storage capacitor45. At this moment, the frequency of the oscillation output signal CLKOUT reaches its minimum frequency F1and the charge period reaches its maximum Tc2,2.

FIG. 11is a third embodiment circuit diagram of the disclosed adaptive dual-slope frequency control circuit. As a further embodiment of the conversion circuit48inFIG. 6, it is different from others in that the first charging current source Ic141, the first discharging current source Id142, the second charging current source Ic243, and the second discharging current source Id244are coupled to the first conversion circuit111, the second conversion circuit112, the third conversion circuit113, and the fourth conversion circuit114, respectively. Each of them uses its own conversion circuit111˜114to output a conversion signal corresponding to the error voltage Ve to the corresponding current source41˜44. The charge currents or discharge currents extracted by the current sources41˜44are thus adjusted. A reset signal is output according to the voltage of the switch current CS to the corresponding switch SW1˜SW4, achieving the same charge/discharge effects as described above.

The first conversion circuit111refers to the error voltage Ve and outputs a corresponding conversion signal to the first charging current source Ic141. The first charging current source Ic141couples the first switch411to the storage capacitor45. The first switch411determines the first charge period. The second conversion circuit112refers to the error voltage Ve and outputs a corresponding conversion signal to the first discharging current source Id142. The first discharging current source Id142couples the second switch421to the storage capacitor45. The second switch421determines the first discharge period. The third conversion circuit113refers to the error voltage Ve and outputs a corresponding conversion signal to the second charging current source Ic243. The third charging current source Ic243couples the third switch431to the storage capacitor45. The third switch431determines the second charge period. The fourth conversion circuit114refers to the error voltage Ve and outputs a corresponding conversion signal to the second discharging current source Id244. The second discharging current source Id244couples the fourth switch441to the storage capacitor45. The fourth switch441determines the second discharge period.

Certain variations would be apparent to those skilled in the art, which variations are considered within the spirit and scope of the claimed invention.