Method and apparatus for transferring data across a protocol bridge

A method and apparatus for transferring data across a network protocol bridge is disclosed. In one embodiment, a multi-processing engine configuration is used wherein processing engines are tasked with carrying out specific data transfer operations. In another embodiment, this multi-processing engine configuration is implemented in a protocol bridge in which data is being transferred between Fibre Channel and a network bus that is coupled to a host system. In one embodiment, the network bus is a PCI/PCI-X bus.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates in general to data networks and more particularly, to a method and apparatus for transferring data across a protocol bridge.

2. Background Information

Fibre Channel is a computer communications protocol designed to provide for higher performance information transfers. Fibre Channel allows various existing networking protocols to run over the same physical interface and media. In general, Fibre Channel attempts to combine the benefits of both channel and network technologies.

A channel is a closed, direct, structured, and predictable mechanism for transmitting data between relatively few entities. Channels are commonly used to connect peripheral devices such as a disk drive, printer, tape drive, etc. to a workstation. Common channel protocols are Small Computer System Interface (SCSI) and High Performance Parallel Interface (HIPPI).

Networks, however, are unstructured and unpredictable. Networks are able to automatically adjust to changing environments and can support a larger number of connected nodes. These factors require that much more decision making take place in order to successfully route data from one point to another. Much of this decision making is done in software, making networks inherently slower than channels.

Fibre Channel has made a dramatic impact in the storage arena by using SCSI as an upper layer protocol. Compared with traditional SCSI, the benefits of mapping the SCSI command set onto Fibre Channel include faster speed, connection of more devices together and larger distance allowed between devices. In addition to using SCSI, several companies are selling Fibre Channel devices that run Internet Protocol (IP).

Fibre Channel continues to expand into the storage markets, which will make use of its benefits over traditional channel technologies such as SCSI. Being able to access mass storage devices quicker and from greater distances is very attractive to such applications as multimedia, medical imaging, and scientific visualization. One of the issues with transferring data across a protocol bridge, such as a bridge between Fibre Channel and a peripheral component interconnect (PCI) bus operating in accordance with the PCI-X standard, which is commonly referred to in the art as a PCI-X bus, is the lack of available bandwidth afforded by prior art systems. Thus, there is a need for an improved system of data transfer in which bandwidth is maintained.

SUMMARY OF THE INVENTION

An apparatus and methods for bridging a first network to at least a second network are disclosed. One method comprises coupling a first network interface to a first network, where the first network has a first network protocol, and coupling a second network interface to a second network, where the second network has a second network protocol that is different from the first network protocol. The method further comprises servicing data transmission requests from the second network using a first processing engine, managing data flow from the second network to the first network using a second processing engine, managing data flow from the first network to the second network using a third processing engine, and providing bus command management using a fourth processing engine.

Other embodiments are disclosed and claimed herein.

DETAILED DESCRIPTION

One aspect of the invention is to provide an improved protocol bridge for transferring data. In one embodiment, the protocol bridge transfers data between a protocol-specific network (e.g., Fibre Channel) and a host system on a network bus. In one embodiment, the network bus is a bus compatible with both PCI and PCI-X standards, which is commonly referred to in the art as a PCI/PCI-X bus.

Another aspect of the invention involves the use a multi-processing engine configuration in which specific processing engines are tasked with carrying out specific data transfer operations. In one embodiment, data transfer operations are distributed among four on-chip processing engines. In one example, task distribution is set up as follows: a first processing engine may be dedicated to servicing data transmission requests from the host system. A second processing engine may then be dedicated to managing data flow from the host system to the fibre channel. A third processing engine may be used to manage data flow to the host system from the fibre channel. Finally, a fourth processing engine may be dedicated to bus command management.

Yet another aspect of the invention is to provide inter-processing engine communication using an inter-locked shared memory. In one embodiment, the shared memory may be comprised of firmware queues, while in another embodiment it may be comprised of SDRAM. However, it should further be appreciated that any other memory format capable of providing inter-processing engine communication functionality may similarly be used.

I. System Overview

In one embodiment, the invention may be implemented using an ASIC design. To that end,FIGS. 1A-1Billustrate a block diagram of one embodiment of an ASIC10capable of carrying out one or more aspects of the present invention. In the embodiment ofFIGS. 1A-1B, the ASIC10includes two Fibre Channel (FC) ports, F0Port and F1Port, with hardware associated with the F0Port residing on the F0function level and hardware associated with the F1Port residing on the F1function level. It should be appreciated, however, that there may be more or fewer FC ports and one or more of the hardware components for different FC functions may be integrated onto the same function level.

Ingress and Egress references inFIGS. 1A-1Bdescribe the data path direction between a Network Bus12(e.g., PCI/PCI-X bus) and one or more Fibre Channel(s)14, where the Ingress path refers to data supplied by the Fibre Channel(s)14to the Network Bus12and the Egress path refers to data supplied by the Network Bus12to the Fibre Channel(s)14. While in one embodiment the Network Bus12is a POI/PCI-X bus, it should equally be appreciated that the Network Bus12may be any other type of bus, such as those operated in accordance with PCI Express and InfiniBand standards. In another embodiment, the Network Bus12couples a host system to the ASIC10, where the host system may be a personal computer, a server, etc.

In the embodiment ofFIGS. 1A-1B, ASIC10is comprised of four major components—a Host Interface, a Fibre Channel Interface, a Payload Buffer and a Processor Subsystem, all of which will be described in detail below.

A. Host Interface

The Host Interface provides the interface and control between the ASIC10and a host system (not shown) coupled to the Network Bus12. In the embodiment ofFIGS. 1A-1B, the Host Interface is comprised of the Host Control Module16and the Network Interface18.

Where the Network Bus12is a PCI/PCI-X bus, the Host Interface may further house PCI/PCI-X input staging registers and output sub-phases registers (not shown). The Host Interface may also contain the PCI/PCI-X master and target state machines in order for the ASIC10to function as a bus master or a target device on a PCI/PCI-X bus. PCI Configuration Space registers may also be included to support various additional features.

The Host Control Module16is comprised of the Egress Host Control (EHC)20, the Ingress Host Control (IHC)22, and the Network Bus Control (PXC)24, according to one embodiment. In the embodiment ofFIG. 1, the Host Control Module16has the following DMA/queue controllers available to it from the Header Queue Memory (HQM)26:EHPQ0—Egress Host Pass-Through Queue0,EHPQ1—Egress Host Pass-Through Queue1,EHIQ—Egress Host Internal Queue,IHPQ0—Ingress Host Pass-Through Queue0,IHPQ1—Ingress Host Pass-Through Queue1,IHIQ0—Ingress Host Internal Queue, andIHIQ1—Ingress Host Internal Queue.

In another embodiment, most of these DMA controllers will also have separate scatter/gather fetch DMA controllers which assist in bringing in new scatter/gather lists and continuing scatter/gather element processing on its own without processor intervention.

The EHC module20may be used to provide read functionality as a bus master to transfer data from the Network Bus12(which may originate from the host system's memory) to the Egress Payload Buffer (EPB) module28or to the Egress Host Queue (EHQ) memories. In one embodiment, the Egress Host Pass-Thru Queue0(EHPQ0), Egress Host Pass-Thru Queue1(EHPQ1) and/or Egress Host Internal Queue (EHIQ) registers are programmed with data and control information prior to each read operation.

As shown in the embodiment ofFIGS. 1A-1B, the EHQ Memory may be divided into three separate queues (i.e., EHPQ0, EHPQ1and EHIQ). In one embodiment of a DMA operation, the EHQ memory is used as the common shared memory and the main communication bridge between processor40and the Host Control Module16.

The IHC module22may be used to provide the DMA write function as a bus master to transfer data to the Network Bus12host memory from the Ingress Payload Buffer (IPB) module30or the Ingress Host Queue (IHQ) memory. In one embodiment, the Ingress Host Pass-Thru Queue0/1(IHPQ0/1) or Ingress Host Internal Queue0/1(IHIQ0/1) registers are programmed with data and control information prior each DMA write operation. In another embodiment, the IHQ memory is used as the common shared memory and a communication bridge between the embedded processor40and the Host Control Module16.

As shown in the embodiment ofFIGS. 1A-1B, the IHQ memory may be divided into 4 sections, IHPQ0, IHPQ1, IHIQ0and IHIQ1.

B. Fibre Channel Block

The Fibre Channel block provides the interface and control between the Fibre Channel and the ASIC10. In the embodiment ofFIGS. 1A-1B, the Fibre Channel block consists of 4 major modules—the Egress Fibre Channel Control (EFC)32, Arbitrated Loop Control (ALC)34, Ingress Fibre Channel Control (IFC)36and Fibre Channel Interface (FCI)38modules.1. EFC Module

In one embodiment, the EFC module32provides the frame flow control mechanism of the FC transmitting port (i.e., F0or F1). Other operations which may be performed by the EFC module32include frame assembly, CRC generation, and retransmission of certain data from the ALC module34(e.g., L_Port data). In one embodiment, the EFC module32assembles and transmits frames to the FCI module38based on the data from Egress Fibre Channel Pass Through Queues (EFPQ0, EFPQ1), Egress Fibre Channel Internal Queues (EFIQ0, EFIQ1), Egress Payload Buffer (EPB), and data from the ALC module34.

When transmission of internally generated frames is required, the EFC module32may control the ALC34module's Loop Port State Machine (LPSM) to arbitrate, open and close the loop in order to complete the frame transmission. The EFC module32may also provide registers needed to control and to read the state of the status pins of external GBIC and SERDES devices.

In order to prevent memory access collision between the processor40and the EFC module32, a control bit may be defined in each queue element. For example, after power-on-reset, the control bit in each queue element may be initialized to zero before the EFPQ0/1and EFIQ0/1Queue Memory state machines are enabled. After a queue element has been programmed by the processor40with appropriate information for the EFC module32to transmit a frame or frames, control bit of the queue element may be set by the processor40to indicate that the ownership of the queue element has been released to the EFC module32, according to one embodiment.

Once the EFC module32has detected that the control bit is being set in this queue element, it may then copy data in the queue element into its own local registers to start the frame transmission process. After the frame transmission process is completed, the EFC module32may update the header fields and status in the same queue element location in the queue memory, and release the queue element back to the processor40by clearing the control bit. In one embodiment, once the processor40detects that the control bit has been cleared, it saves all necessary data from the queue element into its data RAM (e.g., DDR/SDRAM52). If an error has occurred during the processing of a queue element, the EFC32queue memory state machine may be halted on the queue of the given element. The processor40may then take appropriate error recovery actions and re-enable the queue process after the error recovery actions are complete.2. ALC Module

In the embodiment ofFIGS. 1A-1B, the ALC module34is located between the IFC module36and EFC modules32. This module consists primarily of a Loop Port State Machine (LPSM) whose main function is to continuously monitor data stream coming from the IFC module36. The LPSM may further be used to monitor commands from the processor40and the EFC32. In one embodiment, the EFC32may send a command to the LPSM which defines the function to be performed by the ALC34such as loop arbitration, open loop, close loop, etc. In another embodiment, the LPSM may be controlled by the processor40.

In one embodiment, the ALC module34is able to detect different primitive signals or sequences (e.g., LIP, LPE, LPB, MRK, NOS, OLS, LR and LRR) and respond accordingly. In the loop topology, data from the IFC module36may be either passed on to the EFC module32, or substituted with a primitive sequence depending on the function to be performed. The substitution may be either by the state machine itself or signaled from the EFC module32.3. IFC Module

The IFC module36receives a data stream from the Fibre Channel Interface (FCI) module38and provides functions that may include frame disassembling, frame header matching and routing, primitive signal and sequence detection, CRC checking and link interface integrity measurement. In one embodiment, the data received from the FCI module38is passed on to the ALC module34for retransmission during a private/public loop (L_Port) monitoring state. When not in the monitoring state, each frame received may be examined and routed to the appropriate destination modules. If external memory43(e.g., QDR SRAM) is available, each frame received may be stored, and at the same time, the data in the external memory43read in. In another embodiment, frame headers are routed to either the IFPQ0/1or IFIQ0/1/2memory. If there is a payload in the frame, the payload may be written into the next available buffer segment in the IPB module30, according to one embodiment. A certain amount of the payload can also be stored in the IFPQx or IFIQx memory along with the frame header for early and fast access of the payload by the processor40before the whole frame is received.

In another embodiment, in order to prevent memory access collision between the processor40and the IFC36, a control bit may be defined in each queue element as the queue element ownership token bit between the IFC36and the processor40. For example, when a queue element is released by the processor40to receive a frame, the control bit of the queue element is set by the processor40to indicate that the ownership of the queue element has been released. When a frame is received, the IFC36may check the control bit to make sure of the ownership of this queue element. The IFC36may then copy the header into its own local registers and into the queue element. The header may also be compared against the header of the last frame received in the same queue, according to another embodiment. After the frame reception is completed either with or without errors, the IFC36may then update the status in the same queue element, and release the queue element back to the processor40by clearing the control bit.

When a frame is received and routed into either the pass-thru or internal queue, it may be written into the queue element allocated for this frame. The header of the received frame may also be compared against the last frame received in the same queue to see if this frame is the continuation of the last frame. The result of the comparison may then be stored in one or more registers.

Once the processor40detects that the control bit is cleared, it may then check a status field in the queue element to determine if any additional processing of the frame is required. Moreover, any desired information in the queue element may be saved to its Data RAM. Finally, the control bit may be set by the processor40to complete the queue element process, after which the queue element would be ready for next the frame.

The Payload Buffer block is comprised of the Egress Payload Buffer (EPB)28and Ingress Payload Buffer (IPB)30modules which may be used to provide up to a certain amount of storage (e.g., 16 Kbytes) for payload data as it flows between the Fibre Channel link and the Network Bus12. To achieve constant streaming of data, the buffer may be implemented using a dual-ported RAM. The buffer can be segmented to reduce latency by allowing a segment to be filled by the write block, while another segment is being emptied by the read block.

The Processor Subsystem consists of processor40, Processor Bridge Controller (PBC)42, Head Queue Memory (HQM)44, Memory Port Interface (MPI) modules46, and Initialization and Configuration Control (ICC) module48.1. Processor

In the embodiment ofFIGS. 1A-1B, processor40includes embedded processing engines PE1, PE2, PE3and PE4. While in one embodiment, the embedded processing engines (PE1, PE2, PE3, and PE4) are little-endian, 5-stage pipeline, high-performance, 32-bit RISC cores, it should equally be appreciated that other processor/engine configurations may be employed. For example, the embedded processing engines may similarly be comprised of one or more MIPS processors. Moreover, while the embodiment ofFIGS. 1A-1Bdepicts four processing engines, it should similarly be appreciated that more or fewer processing engines may be used.

The PBC module42provides the interfaces that connects the embedded processing engines PE1-PE4to the rest of the ASIC10hardware. Each embedded processing engine PE1-PE4may have a bus (shown inFIG. 1Aas buses501-504) that is used to interface to the rest of the ASIC10through the PBC module42. In one embodiment, buses501-504are general purpose I/O buses that support burst reads and pipelined single-access writes. In another embodiment, the processing engines PE1-PE4can also use buses501-504to interface with external memory devices such as DDR/SDRAM52and NVRAM54attached to the ASIC10through the MPI module46, or SEEPROM56through the ICC module48. In yet another embodiment, the PBC module42may also provide bi-directional bridging between the F_LIO58and Host Local I/O (H_LIO) bus60. In one embodiment, F_LIO58may be used to provide access to registers in other hardware blocks through arbitration.

In addition to providing interfaces for various busses, the PBC module42may also provide one or more of the following functions: Host Delivery Queues are provided to allow external hosts to post PCI addresses of new commands in the host memory to be processed by the ASIC10; a plurality of “Done Queue” logics are provided to allow proper handshakes between processors and external hosts, and to control PCI interrupt generation; firmware queue registers are provided to allow processors to pass messages between them; different types of timers are provided for various purposes possibly including real time clocks and programmable timers; and message passing registers which allow processors to pass and receive messages to and from external hosts.

The HQM module44provides high-speed dual-port memory modules. Memory modules may serve a specific function and be grouped into a particular interface, such as Host, FC and MPI. Within each interface, the memory modules may further be divided into Egress or Ingress data flow direction, and also into pass-through and internal.

In one embodiment of an I/O operation, the processing engines PE1-PE4are running with the firmware to process incoming and outgoing frames. The HQM module44may serve as the common shared memory that is used as the main communication bridge between the embedded processing engines PE1-PE4and the hardware where both have direct random access.

The MPI module46may be used to provide arbitrated accesses to external memory (e.g., DDR/SDRAM52and/or NVRAM54) devices by the embedded processing engines PE1-PE4, as well as to every bus master on the internal H_LIO bus60. In one embodiment, the embedded processing engines PE1-PE4can access external memory via three mechanisms—the Context Cache Interface (CCIF)61, the Memory Control Interface (MCIF)62or the H_LIO bus60.4. Initialization and Configuration Control Module (ICC)

In one embodiment, the ICC48includes a Serial Memory Control (SMC) module, which can be used to initialize internal registers and provide read/write access to SEEPROM56. The ICC48may also include a Trace Control module to provide external visibility of the internal signals.

II. Processing Engine Implementation

As discussed above in Section I.D, processing engines PE1-P4may be connected to the rest of the ASIC10through the PBC module42. Referring now toFIG. 2, in which one embodiment of the processing engines PE1-PE4firmware flow is depicted. In particular, in the embodiment ofFIG. 2, PE1may be used to service I/O requests and control information from the host system to the ASIC10over Network Bus12. PE1may also initiate FC protocol commands (FCP_CMND) and other FC functions, such as Transfer Readys (FCP_XFER_RDY) and FCP Responses (FCP_FRSP). In one embodiment, PE1may also generate requests for PE2to send data on the Fibre Channel Egress. Moreover, PE1may also be used to pass host system resource contexts to PE4.

In the embodiment ofFIG. 2, PE1has access to EFIQ0and EHIQ, which may operate in lockstep for host system I/O request processing. Header queue pointers may be used to maintain the I/O request processing from the host. By way of example only, the queue pointer EHIQNewmay be used to point to the next EHIQ element that is available to receive an I/O request from the host, while the queue pointer EXIQPtrmay point to the EHIQ element that is awaiting host DMA completion and the next EFIQ0element available for egress Fibre Channel. In addition, a third queue pointer (e.g., EFIQ0Comp) may be used to point to the EFIQ0element that is possibly awaiting completion on egress Fibre Channel. A firmware flag in the header queue element may be used to provide control throughout these operations.

Continuing to refer toFIG. 2, PE2may be used to manage data flow from the host system (vis the Network Bus12) and transmit such data on fibre. In particular, PE2may service FCP_XFER_RDY frames on ingress Fibre Channel and generate egress Fibre Channel activity through the host DMA channel. In one embodiment, the sources of egress Fibre Channel requests may come from either FCP_XFER_RDY on IFIQ0or from the Firmware Queue from PE1. In one embodiment, PE2may load and lock the I/O context and generate a host system DMA transfer, which provides data to send out on the Fibre Channel. Once the data has been transmitted out on the Fibre Channel, the I/O context may then be saved to memory and unlocked, according to one embodiment.

In the embodiment ofFIG. 2, Ingress Fibre Channel processing uses a single header queue pointer for managing IFIQ0. This queue pointer (e.g., IFIQNew) may be used to point to the next IFIQ0element that contains a FCP_XFER_RDY frame received on the ingress Fibre Channel. After the frame has been validated, a request may be placed on a firmware queue for processing by the egress Fibre Channel section of PE2. This mechanism provides asynchronous operation between the ingress and egress sections of the PE2processing operations, according to one embodiment.

Egress processing requests may come from either the firmware queue from PE1or the internal firmware queue from PE2. For example, requests from PE1may be requests for FCP data (FCP_DATA), Common Transport data (CT_DATA), a Common Transport response (CT_RESPONSE), or IP data (IP_DATA). Similarly requests from PE2may include a FCP_XFER_RDY request.

In the embodiment ofFIG. 2, the EHPQ0/1and EFPQ0/1element indexes may operate in lockstep for each egress request processed. Header queue pointers may be used for processing egress requests. For example, queue pointers (e.g., EXPQ0New/EXPQ1New) may be used to point to the next EHPQ0/1element that is available for initiating a DMA transfer from the host and the next EFPQ0/1element available for the egress Fibre Channel. Similarly, queue pointers (e.g., EXPQ0Comp/EXPQ1Comp) may point to the EHPQ0/1element that is awaiting host DMA completion and the EFPQ0/1element that is awaiting completion on the egress Fibre Channel. A firmware flag may be maintained in the header queue element to provide control throughout these operations.

Continuing to refer toFIG. 2, PE3may be used to manage data flow to the host system for data that is received on the Fibre Channel. In particular, PE3may service FCP_DATA and FCP_RSP frames on the ingress Fibre Channel and generate DMA transfers to the host. In one embodiment, the serviceable events for PE3include: FCP data or FCP response events received on IFPQ0/1, host DMA completions on IHPQ0/1, and I/O Context fetching completions. In another embodiment, for FCP_DATA frames received, PE3may load and lock the I/O context and transfer the Fibre Channel data to the host system using a DMA operation. When all the data has been received on Fibre Channel, the I/O context may be saved to memory (e.g., SDRAM) and unlocked, according to one embodiment. For FCP_RSP frames received, PE3may load and lock the I/O context and send a ‘completion’ message to PE4using a firmware queue. Thereafter, the I/O context may be unlocked.

In one embodiment, the IFPQ0/1and IHPQ0/1element indexes may operate in lockstep for each ingress request processed. In another embodiment, the IHPQ0/1element may not used when a successful FCP_RSP is received. In such a case, the IHPQ0/1element may be skipped after processing of the IFPQ0/1element is complete.

Header queue pointers may be used in processing ingress requests. For example, queue pointers (e.g., IXPQ0New/IXPQ1New) may point to the next IFPQ0/1element available for the ingress Fibre Channel and the next IHPQ0/1element that is available for initiating a DMA transfer to the host. Similarly, queue pointers (e.g., IHPQ0Comp/IHPQ1Comp) may be used to point to the IHPQ0/1element that is awaiting host DMA completion.

PE4may be used to service the ‘completion’ firmware queue and provide management of the Fibre Channel link. The receipt of a ‘completion’ firmware queue message may produce an I/O request completion to the host system over the Network Bus12. The Fibre Channel link management functions provided by PE4may include Link Initialization and Link Service Frame Management. Link Initialization may include a set of software algorithms designed to make the link operational as either an N-Port (point-to-point and Fabric Fiber Channel topologies) or an L-Port. After successful link initialization, the Fibre Channel port may have the state of ‘Link-Up’ and port discovery may begin.

As shown inFIG. 2, PE4may use the IFIQ2and IHIQ0element indexes in lockstep for each ingress request processed. However, the IHIQ0element need not be used when a Link Initialization frame or Link Service frame is received. In such cases, the IHIQ0element may be skipped after processing of the IFIQ2element is complete. As with the other processing engines, header queue pointers may be used for processing ingress requests. A queue pointer (e.g., IXIQNew) may point to the next IFIQ2element that contains a Link Initialization frame, Link Service frame, CT_DATA, IP_DATA or FCP_CMND received on the ingress Fibre Channel. In one embodiment, after a frame has been validated, an IHIQ0element may be generated for CT_DATA, IP_DATA, and FCP_CMND. Similarly, an EFIQ1element may be generated for Link Service processing or Link Initialization. A queue pointer (e.g., IXIQNew) may also be used to point to the next IHIQ0element that is available for initiating a DMA transfer to the host. Moreover, a queue pointer (IHIQ0Comp) may also be used to point to the IHIQ element that is awaiting host DMA completion. In another embodiment, when the IHIQ0host transfer is complete, a queue entry may be generated for completion of CT_DATA, IP_DATA or FCP_CMND.

In one embodiment, egress processing requests are generated internally from Link Initialization, Link Service Processing, and Port Discovery. A queue pointer (e.g., EFIQ1New) may be used to point to the next EFIQ1element that is available for initiating the egress Fibre Channel requests. Another queue pointer (e.g., EFIQ1Comp) may also be used to point to the EFIQ1element that is awaiting completion on the egress Fibre Channel. In another embodiment, a firmware flag is maintained in the header queue element to provide control throughout these operations.

By way of providing an example of how processing engines PE1-PE4may be used to carry out data transfer operations, one embodiment of an Initiator FCP read/write operation and a Target read/write operation will now be described.

Referring now toFIG. 3, in which one embodiment of an Initiator FCP read/write operation300is described. In the embodiment ofFIG. 3, PE1-PE4are used to carry out the read/write operation. In particular, at block305the host system initiates operation300by writing the I/O request's address to a Delivery Queue. PE1may then transfers the I/O request from the host system using EHIQ (block310). Thereafter, at block315PE1may be used to send the FCP_CMND using EFIQ0. PE1may then generate a ‘Report I/O Handle’ message to PE4(block320). At block325, PE4may transfer the ‘Report I/O Handle’ data to the host system via Network Bus12.

If operation300is a ‘read’ operation, then after block330the process continues to block335where PE3receives FCP_DATA using IFPQ0/1. PE3may then transfer the data to the host system using IHPQ0/1(block340). At this point, in the embodiment ofFIG. 3, PE3may receive an FCP_RSP using IFPQ0/1(block345). At block350, PE3generates a ‘Completion’ message to PE4, after which PE4generates and transfers the ‘Done Queue’ entry to the host system using IHIQ1(block355).

If, on the other hand, the operation300is a ‘write’ operation then the process continues to block360rather than block335. In particular, at block360, PE2receives a FCP_XFER_RDY using IFIQ0. At block365, PE2generates a ‘Transfer Ready’ message to PE2, after which PE2reads the ‘Transfer Ready’ message from PE2(block370). At this point, PE2may transfer the data to the Fibre Channel using EHPQ0/1and EFPQ0/1(block375). If the data transfer operation is not complete, operation300returns to block360until the data transfer operation is complete (block380). Once the data transfer operation is complete, operation300continues to block345and continues in the same manner as if it were a ‘read’ operation.

Referring now toFIG. 4A-4B, in which a Target FCP read/write operation400is depicted. In the embodiment ofFIGS. 4A-4B, processing engines PE1-PE4are used to carry out the FCP read/write operations.

At block405, PE4receives an unsolicited FCP_CMND on IFIQ2, after which PE4is tasked with allocating an FCP_CMND_RESOURCE for the exchange (block410). PE4may then generate and transfer the ‘Done Queue’ entry to the host system using IHIQ1at block415. If operation400is a ‘read’ operation, the process will continue to block425where PE1transfers the I/O request from the host system using EHIQ. Thereafter, PE1may send the FCP_XFER_RDY using EFIQ0(block430). In the embodiment ofFIG. 4A, at block435PE3may then receive FCP_DATA using IFPQ0/1, after which PE3may transfer the data to the host system using IHPQ0/1(block440). Thereafter, at block445, PE3generates a ‘Completion’ message to PE4, which in turn may generate and transfer the ‘Done Queue’ entry to the host system using IHIQ1(block450).

At block455, a determination is made as to whether the data transfer is complete. If not, operation400returns to block425and repeats the operations of blocks430-450until all data has been transferred. If, on the other hand, the data transfer is complete, operation400will continue to block460where the I/O request's address is written to a Delivery Queue. PE1may then transfer the I/O request from the host system using EHIQ (block465). At block470, PE1may send the FCP_RSP using EFIQ0. PE1may also then generate a ‘Completion’ message to PE4(block475), followed by PE4generating and transferring a ‘Done Queue’ entry to the host system using IHIQ1(block480).

If, on the other hand, operation400was a ‘write’ operation, then after block420the process would continue to A ofFIG. 4B. Referring now toFIG. 4B, at block485PE1transfers the I/O request from the host system using EHIQ. Thereafter, PE1may send a ‘Transfer’ message to PE2(block490), and PE2may read the ‘Transfer’ message from PE1(block495). In addition, at block500PE2may also transfer the data to the Fibre Channel using EHPQ0/1and EFPQ0/1. Thereafter, PE2may generate a ‘Completion’ message to PE4, and PE4may generate and transfer the ‘Done Queue’ entry to the host system using IHIQ1(block510). The operations of blocks485-515are repeated until the data transfer is complete. At that point, operation400continues to block460and proceeds in the same manner that a ‘read’ operation would.