Filter tuner system and method

A system and method for a filter tuner is presented. The system comprises a sequential logic, a register, a comparator, a first and second counter, a synchronizing logic, a first and second oscillator, a control logic, and a first and second combinational logic. The method comprises the steps of executing a calibration cycle of a filter tuner, executing a measurement cycle of the filter tuner, and tuning a filter with the filter tuner dependent on a determined cutoff frequency variation.

FIELD OF THE INVENTION

The present invention generally relates to communications systems wherein signal information is processed in analog forms. More specifically, the invention relates to systems and methods for tuning resistance-capacitance (“RC”) continuous-time filters.

BACKGROUND OF THE INVENTION

RC continuous-time filters are utilized in various applications, such as in communications systems. As with other types of filters, RC continuous-time filters may be designed to selectively filter out the parts of a signal that have frequencies above or below a desired cutoff frequency. Typically, RC continuous-time filters are utilized in applications where the signals are expected to remain continuous in time and have analog levels. Since continuous-time filters can typically be utilized without the need for signal sampling, continuous-time filters provide a significant operating-speed advantage over the switched-capacitor filter counterparts.

One example of a popular application in which RC continuous-time filters are utilized is digital subscriber line (“DSL”) communications systems. DSL communications systems have been introduced and implemented by communications systems providers in recent years to provide customers with a wide variety of interactive multi-media communications signals over existing plain old telephone system (“POTS”) communications lines. As shown inFIG. 1, and known in the art, a typical DSL communications system100includes several basic components. It is noted thatFIG. 1merely presents a simplified representation of a typical DSL communications system that is sufficient for the purpose of this discussion.

As shown inFIG. 1, a typical DSL communications system100includes an analog front end (“AFE”)102, a hybrid104, a back-matching resistor106, a scaling transformer108, one or more DSL lines110, and one or more connecting communications system lines112. An AFE102is a primary interface component between a DSL communications system and other types of communications systems, such as T-carrier (e.g., T1, T3) or optical-carrier (e.g., OC-1, OC-48) communications systems. Although not shown inFIG. 1, a complete DSL communications system typically includes two or more of the DSL systems100interconnected via one or more DSL lines110.

Within an AFE of a DSL communications system, such as that depicted inFIG. 1, one or more RC continuous-time filters may be utilized. Typically, the components of a DSL system, with the exception of some portions of the communications lines, are contained in a common location. As a result of this practice, DSL system components, including RC continuous-time filters integrated within an AFE, may be subject to temperature variations affected by ambient temperature variations as well as by variations in operating conditions (e.g., signal strengths or operating durations). For example, in typical applications of DSL communications systems, operating temperatures of system components may vary from −40° C. to 125° C. due to ambient temperature and/or operating condition variations. It is noted that the preceding discussion, with respect to DSL communications systems, merely presents one example of the utilization of RC continuous-time filters, and there are many other applications in which RC continuous-time filters are or may be utilized and in which temperature variation may be a concern.

Although RC continuous-time filters offer an operating-speed advantage, as discussed above, these filters typically require some means of tuning in order to set and maintain a desired cutoff frequency. A major reason that tuning of RC continuous-time filters is necessary is because the cutoff frequency of the filter is dependent on the values of the resistance and capacitance elements of the filter, and these values will typically vary due to temperature variations. For example, in a filter built with “High-resitivity Poly0” resistors and “Interpoly” capacitors (note, these component types are known in the art and have certain temperature variation characteristics), the variation in cutoff frequency may vary by as much as 0.15%/° C. In contrast, an acceptable range of cutoff frequency variation, depending on the application, is typically less than 0.04%/° C. It is noted that in an RC continuous-time filter that is built with High-resitivity Poly0 resistors and Interpoly capacitors, the temperature variation of the RC component of the filter, and thus the cutoff frequency of the filter, is typically dominated by the temperature variation of the resistors which can be as large as 0.15%/° C.

Therefore, there is a need for a system and method for a filter tuner for tuning RC continuous-time filters in order to set and maintain cutoff frequencies within acceptable tolerances with regard to temperature variations.

SUMMARY OF THE INVENTION

Certain objects, advantages, and novel features of the invention will be set forth in part in the description that follows and in part will become apparent to those skilled in the art upon examination of the following or may be learned with the practice of the invention. The objects and advantages of the invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out in the appended claims.

To achieve various objects and advantages, the present invention is directed to a novel system and method for a filter tuner. In accordance with some embodiments of the present invention, a system for filter tuning is provided that includes a sequential logic, a register, a comparator, a first and second counter, a synchronizing logic, a first and second oscillator, a control logic, and a first and second combinational logic.

In accordance with other embodiments of the present invention, a method for a filter tuner is provided that includes the steps of executing a calibration cycle of a filter tuner, executing a measurement cycle of the filter tuner, and tuning the filter with the filter tuner dependent on a determined cutoff frequency variation.

The embodiments of the present invention provide at least the advantage of a system and method for a filter tuner that tunes RC continuous-time filters in order to set and maintain cutoff frequencies within acceptable tolerances with regard to temperature variations.

Other objects, features, and advantages of the present invention will become apparent to one skilled in the art upon examination of the following drawings and detailed description. It is intended that all such additional objects, features, and advantages be included herein within the scope of the present invention, as defined by the claims.

DETAILED DESCRIPTION OF THE EMBODIMENTS

Having summarized the invention above, reference is now made in detail to the description of the invention as illustrated in the drawings. While the invention will be described in connection with these drawings, there is no intent to limit it to the embodiment or embodiments disclosed therein. On the contrary, the intent is to cover all alternatives, modifications, and equivalents included within the spirit and scope of the invention as defined by the appended claims. Indeed, the present invention is believed to be applicable to a variety of systems, devices, and technologies.

Turning now to the drawings, wherein like referenced numerals designate corresponding parts throughout the drawings,FIG. 2Ashows a block diagram depicting the utilization of an embodiment of the present invention as it may be utilized in a filter tuning application. In such a filter tuning application, a filter tuner hardware300,400in accordance with an embodiment of the present invention, may be in electrical communications with controls204. Further, controls204may be in electrical communications with a filter208. The filter tuner hardware300,400is described in further detail below, but generally, the hardware300,400may operate to monitor the accuracy of the filter208and cause adjustments to the filter208to set or maintain its cutoff frequency accuracy. Controls204may include one or more processors, digital signal processors (“DSPs”), or other circuitry elements that may control the adjustment or accuracy of the filter208in response to signals communicated with the filter tuner hardware300. The filter208may be one or more of a variation of RC continuous-time filters such as, for example, a variation of a low-pass, high-pass, or band-pass filter.

As shown inFIG. 2A, controls204may include filter tuner firmware206, in accordance with an embodiment of the present invention. The filter tuner firmware206may include various forms of logic, software, executable code, or other forms within the scope of the embodiments of the present invention, as will be apparent to one skilled in the art. The filter tuner firmware206may reside in a memory (not shown) such as a read-only memory (“ROM”) or programmable read-only memory (“PROM”) located with the controls206(as depicted) or at some other location (not depicted) with the components of the filter tuning application. The firmware206is described in further detail below, but generally, the firmware206may communicate control or data signals with the filter tuner hardware300,400. The firmware206may also communicate control or data signals with controls204.

FIG. 2Bshows a block diagram depicting the utilization of another embodiment of the present invention as it may be utilized in a filter tuning application. Similar to the previous description, in such a filter tuning application, a filter tuner hardware300,400, in accordance with another embodiment of the present invention, may be in electrical communications with controls204. Further, controls204may be in electrical communications with a filter208. The filter tuner hardware300,400is described in further detail below, but generally, the hardware300,400may operate to monitor the accuracy of the filter208and cause adjustments to the filter208to set or maintain its accuracy. Controls204may include one or more processors, digital signal processors (“DSPs”), or other circuitry elements that may control the adjustment or accuracy of the filter208in response to signals communicated with the filter tuner hardware300,400. The filter208may be one or more of a variation of RC continuous-time filters such as, for example, a variation of a low-pass, or band-pass filter.

As shown in FIG.2B,in contrast to the application depicted inFIG.2A, the filter tuner hardware300,400may include logic210. Internal logic210may consist of one of various forms of logic circuitry such as microprocessors, programmable logic controllers (“PLCs”), or other forms of logic circuitry. Additionally, internal logic210may include memory (e.g., ROM or EPROM) that contains executable code, firmware, or other forms of software that is processed by internal logic210. Internal logic210may typically be located with filter tuner hardware300,400, but the logic210may alternatively be located at some other location (not depicted) with the components of the filter tuning application.

Focusing now onFIG. 3, there is shown a block diagram representing a filter tuner hardware300in accordance with embodiments of the present invention as presented inFIGS. 2A and 2B. The filter tuner hardware300may include several elements that are described in the following. It is noted that although single line connections are depicted between elements of the filter tuner hardware300to facilitate the description of the embodiments, a single-line may represent one or more connections and/or connecting circuits within the scope of the embodiments of the present invention.

The filter tuner hardware300may include a sequential logic302that has one or more inputs and outputs. The sequential logic302may transmit control and/or data signals (“signals”) to other elements that make up the filter tuner hardware300The sequential logic302may also transmit signals to controls204(FIG.2A). The transmitting of signals from the sequential logic302may occur in response to signals inputted to the sequential logic302from other elements of the filter tuner hardware300or from controls204. The signals inputted from controls204may be inputted in response to the execution of filter tuner firmware210(FIG.2A), in accordance with an embodiment of the present invention. Alternatively, the transmitting signals from the sequential logic302may occur in response to signals inputted to the sequential logic302from internal logic210(FIG.2B), in accordance with another embodiment of the present invention.

As shown inFIG. 3, the sequential logic302, in accordance with an embodiment of the present invention, may have inputs connected to one or more elements of the filter tuner hardware300including a comparator306and a synchronizing logic312. The sequential logic302, in accordance with an embodiment of the present invention, may also have outputs connected to one or more elements of the filter tuner hardware300including a register304, a first counter308, a second counter309, and a synchronizing logic312. Additionally, in accordance with an embodiment of the present invention, the sequential logic302may also transmit and receive signals from controls204(FIG.2A). Alternatively, in accordance with another embodiment of the present invention, the sequential logic302may transmit or receive signals from internal logic210(FIG. 2B) and also transmit signals to controls204.

The sequential logic302of the filter tuner hardware300may include one or more sequential logic circuits. For example, the sequential logic302may include one or more latches or flip-flops along with one or more combinational logic elements. As another example, the sequential logic302may include a state machine circuit. The sequential logic302may include other forms of sequential logic circuits within the scope of the embodiments of the present invention, as will be apparent to one skilled in the art.

Continuing with reference toFIG. 3, the filter tuner hardware300may also include a register304. The register304may store signals that are inputted from elements of the filter tuner hardware300and transmit the stored signals to other elements of the filter tuner hardware300. The inputting of signals to the register304for storage (i.e., loading the register) and the transmitting of stored signals from the register304may occur in response to signals inputted to the register304from other elements of the filter tuner hardware300or from controls204. The signals inputted from controls204may be inputted in response to the execution of filter tuner firmware206(FIG.2A), in accordance with an embodiment of the present invention. Alternatively, the inputting of signals to the register304for the storage and transmitting of stored signals from the register304may occur in response to signals inputted to the register304from internal logic210(FIG.2B), in accordance with another embodiment of the present invention.

The register304, in accordance with an embodiment of the present invention, may have inputs connected to one or more elements of the filter tuner hardware300including a sequential logic302and a first counter308. The register304, in accordance with an embodiment of the present invention, may also have outputs connected to one or more elements of the filter tuner hardware300including a comparator306.

The register304of the filter tuner hardware300may include one or more sequential logic circuits. For example, the register304may include one or more latches or flip-flops along with one or more combinational logic elements. The register304may include other forms of sequential logic circuits within the scope of the embodiments of the present invention, as will be apparent to one skilled in the art.

The filter tuner hardware300ofFIG. 3may also include a comparator306. The comparator306may generate an output signal in response to a comparison of the signals inputted to the comparator306. For example, if the all of the signals inputted to the comparator306are equivalent, the comparator306may generate a particular output signal that indicates that status.

The comparator306, in accordance with an embodiment of the present invention, may have inputs connected to one or more elements of the filter tuner hardware300including a register304and a first counter308. The comparator306, in accordance with an embodiment of the present invention, may also have one or more outputs connected to one or more elements of the filter tuner hardware300including a sequential logic302.

The comparator306of the filter tuner hardware300may include one or more combinational logic elements that form one or more combinational logic circuits. For example, the comparator306may include one or more logic OR, AND, or NOT gates. The comparator306may include other types of combinational logic elements within the scope of the embodiments of the present invention, as will be apparent to one skilled in the art.

The filter tuner hardware300may also include a first counter308and a second counter309. The first and second counters308,309may output a one or more bit (i.e., multiple-bit) counting sequence (e.g., 000, 001, 010, . . . , 000, 001, 010, . . . in binary format) in response to signals inputted from other elements of the filter tuner hardware300. For example the counters308,309may count in response to one or more oscillating signal inputs. Also, the counters308,309may output a counting sequence that is established based on signals that are loaded to the counters from other elements of the filter tuner hardware300.

The counters308,309, in accordance with an embodiment of the present invention, may have inputs connected to one or more elements of the filter tuner hardware300including a sequential logic302, a synchronizing logic312, a second oscillator311, and a second combinational logic315. The counters308,309, in accordance with an embodiment of the present invention, may also have outputs connected to one or more elements of the filter tuner hardware300including a comparator306and a first combinational logic314. Additionally, in accordance with an embodiment of the present invention, the counters308,309may also transmit or receive signals from controls204(FIG.2A). Alternatively, in accordance with another embodiment of the present invention, the counters308,309may transmit or receive signals from internal logic210(FIG. 2B) and also transmit signals to controls204.

The counters308,309of the filter tuner hardware300may include one or more sequential logic circuits. For example, the counters308,309may include one or more latches or flip-flops along with one or more combinational logic elements. The counters308,309may include other forms of sequential logic circuits within the scope of the embodiments of the present invention, as will be apparent to one skilled in the art.

The filter tuner hardware300may also include a first oscillator310and a second oscillator311. The first and second oscillators310,311may generate an oscillating signal output that may be utilized for example to “clock” other sequential circuit elements of the filter tuner hardware300, such as the counters308,309. The oscillators310,311may generate output signals in response to input signals from controls204which may be inputted in response to the execution of filter tuner firmware206(FIG.2A), in accordance with an embodiment of the present invention. Alternatively, the oscillators310,311may generate output signals in response to input signals from internal logic210(FIG.2B), in accordance with another embodiment of the present invention.

The oscillators310,311, in accordance with an embodiment of the present invention, may have outputs connected to one or more elements of the filter tuner hardware300including a first counter308and a second combinational logic315. Additionally, in accordance with an embodiment of the present invention, the oscillators310,311may also receive signals from controls204(FIG.2A). Alternatively, in accordance with another embodiment of the present invention, the oscillators310,311may receive signals from internal logic210(FIG.2B).

The oscillators310,311may include one or more circuit elements. For example, the oscillators310,311may include one or more resistance or capacitance elements. As another example, the oscillators310,311may include a quartz crystal that generates an oscillating signal at one or more frequencies. Additionally, the oscillators310,311may include one or more analog-to-digital (“A/D”) conversion circuitries that may convert an analog oscillating signal generated, for example, from a quartz crystal to a digital oscillating signal (e.g., a square wave). The oscillators310,311may include other forms of circuitry within the scope of the embodiments of the present invention, as will be apparent to one skilled in the art.

In further reference toFIG. 3, the filter tuner hardware300may also include a synchronizing logic312. The synchronizing logic312may synchronize signals that are inputted from elements of the filter tuner hardware300so that the outputted signals are in synchronism with signals from other elements of the filter tuner hardware300. In performing such a synchronizing function, the synchronizing logic312may utilize one or more synchronous signals generated by elements of the filter tuner hardware300such as, for example, the oscillating signals that may be generated by the first and second oscillators310,311.

The synchronizing logic312, in accordance with an embodiment of the present invention, may have inputs connected to one or more elements of the filter tuner hardware300including a sequential logic302, a second counter309, and a second combinational logic315. The synchronizing logic312, in accordance with an embodiment of the present invention, may also have outputs connected to one or more elements of the filter tuner hardware300including a sequential logic302and a first and second counter308,309.

The synchronizing logic312, of the filter tuner hardware300may include one or more sequential logic circuits. For example, the synchronizing logic312, may include one or more latches or flip-flops along with one or more combinational logic elements. The synchronizing logic312may include other forms of sequential logic circuits within the scope of the embodiments of the present invention, as will be apparent to one skilled in the art.

The filter tuner hardware300may also include a first combinational logic314and a second combinational logic315. The first and second combinational logic314,315may process signals such that certain output signals are provided in response to certain input signals. For example, the combinational logic314,315may provide logic functions such as OR, AND, NOT, or combinations of these logic functions upon inputted signals. The combinational logical314,315may also provide certain output signals in further response to signals inputted to the combinational logic314,315from controls204(FIG. 2A) that may respond to the execution of filter tuner firmware206(FIG.2A), in accordance with an embodiment of the present invention. Alternatively, the combinational logical314,315may also provide certain output signals in further response to signals inputted to the combinational logic314,315from internal logic210(FIG.2B), in accordance with another embodiment of the present invention.

The combinational logic314,315, in accordance with an embodiment of the present invention, may have inputs connected to one or more elements of the filter tuner hardware300including a first counter309and a first oscillator310. Additionally, the combinational logic314,315may have inputs connected to one or more external clock sources which may be used to provide reference clock signals for the purpose of testing the operation of the filter tuner hardware300. The combinational logic314,315, in accordance with an embodiment of the present invention, may also have outputs connected to one or more elements of the filter tuner hardware300including a first counter309and a synchronizing logic312. Additionally, in accordance with an embodiment of the present invention, the combinational logic314,315may also transmit and receive signals from controls204(FIG.2A). Alternatively, in accordance with another embodiment of the present invention, the combinational logic314,315may transmit or receive signals from internal logic210(FIG. 2B) and also transmit signals to controls204.

The combinational logic314,315of the filter tuner hardware300may include one or more combinational logic elements that form one or more combinational logic circuits. For example, the combinational logic314,315may include one or more logic OR, AND, or NOT gates. The combinational logic314,315may include other types of combinational logic elements within the scope of the embodiments of the present invention, as will be apparent to one skilled in the art.

As discussed above with respect to elements of the filter tuner hardware300depicted inFIG. 3, several of these elements may receive and/or transmit signals to controls204(FIG.2A), in accordance with an embodiment of the present invention. Further, signals received from and/or transmitted to controls206may be responsive to the execution of filter tuner firmware206(FIG.2A). For example, as depicted inFIG. 3, the sequential logic302may receive control signals from controls204in response to execution of filter tuner firmware206. Further, the sequential logic302may transmit status signals to controls204. As another example, the first and second oscillators310,311may receive enable inputs from controls204and the second combinational logic315may receive a select input from controls204also. As another example, the second counter309may transmit a count output to controls204and the first combinational logic314may transmit a counter status output to controls204.

Alternatively, in accordance with another embodiment of the present invention, several elements of the filter tuner hardware300may receive and/or transmit signals to internal logic210(FIG. 2B) and/or transmit signals to controls204(FIG. 2A) which may be responsive to the execution of filter tuner firmware206(FIG.2A). For example, as depicted inFIG. 3, the sequential logic302may receive control signals from internal logic210. Further, the sequential logic302may transmit status signals to controls204. As another example, the first and second oscillators310,311may receive enable inputs from internal logic210and the second combinational logic315may receive a select input from internal logic210also. As another example, the second counter309may transmit a count output to controls204and the first combinational logic314may transmit a counter status to internal logic210.

Focusing now onFIG. 4, there is shown a block diagram representing a filter tuner hardware400in accordance with other embodiments of the present invention as presented inFIGS. 2A and 2B. The filter tuner hardware400may include several elements that are described in the following. It is noted that although single line connections are depicted between elements of the filter tuner hardware400to facilitate the description of the embodiments, a single-line may represent one or more connections and/or connecting circuits within the scope of the embodiments of the present invention.

The filter tuner hardware400may include a finite state machine402, that has one or more inputs and outputs. The finite state machine402may transmit signals to other elements that make up the filter tuner hardware400The finite state machine402may also transmit signals to controls204(FIG.2A). The transmitting of signals from the finite state machine402may occur in response to signals inputted to the finite state machine402from other elements of the filter tuner hardware400or from controls204. The signals inputted from controls204may be inputted in response to the execution of filter tuner firmware206(FIG.2A), in accordance with an embodiment of the present invention. Alternatively, the transmitting of signals from the finite state machine402may occur in response to signals inputted to the finite state machine402from internal logic210(FIG.2B), in accordance with another embodiment of the present invention.

As shown inFIG. 4, the finite state machine402, in accordance with an embodiment of the present invention, may have inputs connected to one or more elements of the filter tuner hardware400including a comparator306and a synchronizer412. The finite state machine402, in accordance with an embodiment of the present invention, may also have outputs connected to one or more elements of the filter tuner hardware400including a 14-bit register404, a 14-bit counter408, an 11-bit counter409, and a synchronizer412. Additionally, in accordance with an embodiment of the present invention, the finite state machine402may also transmit and receive signals from controls204(FIG.2A). Alternatively, in accordance with another embodiment of the present invention, the finite state machine402may transmit or receive signals from internal logic210(FIG. 2B) and also transmit signals to controls204.

The finite state machine402of the filter tuner hardware400may include one or more sequential logic elements and one or more combinational logic elements. For example, the finite state machine402may include one or more latches or flip-flops and one or more logic function elements such as OR, AND, or NOT gates. The finite state machine402may include other forms of sequential logic elements and combinational logic elements within the scope of the embodiments of the present invention, as will be apparent to one skilled in the art.

Continuing with reference toFIG. 4, the filter tuner hardware400may also include a 14-bit register404. The 14-bit register404may store signals of up to 14-bit lengths that are inputted from elements of the filter tuner hardware400and transmit the stored signals to other elements of the filter tuner hardware400. The inputting of signals to the 14-bit register404for storage (i.e., loading the register) and the transmitting of stored signals from the 14-bit register404may occur in response to signals inputted to the 14-bit register404from other elements of the filter tuner hardware400or from controls204. The signals inputted from controls204may be inputted in response to the execution of filter tuner firmware206(FIG.2A), in accordance with an embodiment of the present invention. Alternatively, the inputting of signals to the 14-bit register404for the storage and transmitting of stored signals from the 14-bit register404may occur in response to signals inputted to the 14-bit register404from internal logic210(FIG.2B), in accordance with another embodiment of the present invention.

The 14-bit register404, in accordance with an embodiment of the present invention, may have inputs connected to one or more elements of the filter tuner hardware400including a finite state machine402and a 14-bit counter408. The 14-bit register404, in accordance with an embodiment of the present invention, may also have outputs connected to one or more elements of the filter tuner hardware400including a comparator306.

The 14-bit register404of the filter tuner hardware400may include one or more sequential logic circuits. For example, the 14-bit register404may include a cascaded circuit of 14 latches or flip-flops electrically coupled to one or more combinational logic elements. The 14-bit register404may include other forms of sequential logic circuits within the scope of the embodiments of the present invention, as will be apparent to one skilled in the art.

The filter tuner hardware400ofFIG. 4may also include a comparator306. The comparator306may generate an output signal in response to a comparison of the signals inputted to the comparator306. For example, if the all of the signals inputted to the comparator306are equivalent, the comparator306may generate a particular output signal that indicates that status.

The comparator306, in accordance with an embodiment of the present invention, may have inputs connected to one or more elements of the filter tuner hardware400including a 14-bit register404and a 14-bit counter408. The comparator306, in accordance with an embodiment of the present invention, may also have one or more outputs connected to one or more elements of the filter tuner hardware400including a finite state machine402.

The comparator306of the filter tuner hardware400may include one or more combinational logic elements that form one or more combinational logic circuits. For example, the comparator306may include one or more logic OR, AND, or NOT gates. The comparator306may include other types of combinational logic elements within the scope of the embodiments of the present invention, as will be apparent to one skilled in the art.

The filter tuner hardware400may also include a 14-bit counter408and an 11-bit counter409. The 14-bit counter408may output up to a 14-bit counting sequence in response to signals inputted from other elements of the filter tuner hardware400. Similarly, the 11-bit counter409may output up to an 11-bit counting sequence in response to signals inputted from other elements of the filter tuner hardware400. For example either of the counters408,409may count in response to one or more oscillating signal inputs. Also, both counters408,409may output a counting sequence that is established based on multiple-bit signals that are loaded to the counters from other elements of the filter tuner hardware400.

The counters408,409, in accordance with an embodiment of the present invention, may have inputs connected to one or more elements of the filter tuner hardware400including a finite state machine402, a synchronizer412, a crystal oscillator411, and a multiplexer415. The counters408,409, in accordance with an embodiment of the present invention, may also have outputs connected to one or more elements of the filter tuner hardware400including a comparator306and a combinational logic414. Additionally, in accordance with an embodiment of the present invention, the counters408,409may also transmit or receive signals from controls204(FIG.2A). Alternatively, in accordance with another embodiment of the present invention, the counters408,409may transmit or receive signals from internal logic210(FIG. 2B) and also transmit signals to controls204.

The counters408,409of the filter tuner hardware400may include one or more sequential logic circuits. For example, the 14-bit counter408may include a cascaded circuit of 14 latches or flip-flops electrically coupled to one or more combinational logic elements. Similarly, for example, the 11-bit counter409may include a cascaded circuit of 11 latches or flip-flops electrically coupled to one or more combinational logic elements. The counters408,409may include other forms of sequential logic circuits within the scope of the embodiments of the present invention, as will be apparent to one skilled in the art.

The filter tuner hardware400may also include an RC oscillator410and a crystal oscillator411. Both oscillators410,411may generate an oscillating signal output that may be utilized for example to “clock” other sequential circuit elements of the filter tuner hardware400, such as the counters408,409. The oscillators410,411may generate output signals in response to input signals from controls204which may be inputted in response to the execution of filter tuner firmware206(FIG.2A), in accordance with an embodiment of the present invention. Alternatively, the oscillators410,411may generate output signals in response to input signals from internal logic210(FIG.2B), in accordance with another embodiment of the present invention.

The oscillators410,411, in accordance with an embodiment of the present invention, may have outputs connected to one or more elements of the filter tuner hardware400including a 14-bit counter408and a multiplexer415. Additionally, in accordance with an embodiment of the present invention, the oscillators410,411may also receive signals from controls204(FIG.2A). Alternatively, in accordance with another embodiment of the present invention, the oscillators410,411may receive signals from internal logic210(FIG.2B).

The RC oscillator may include one or more resistance elements and one or more capacitance elements electrically coupled to provide a circuit that may generate an oscillating signal output. The crystal oscillator411may include one or more crystals, for example quartz crystals, coupled to other circuit elements (e.g., resistance or capacitance elements) to provide a circuit that may generate an oscillating signal output. Additionally, the oscillators410,411may include one or more analog-to-digital (“A/D”) conversion circuitries that may convert a generated analog oscillating signal to a digital oscillating signal (e.g., a square wave). The oscillators410,411may also include other forms of circuitry within the scope of the embodiments of the present invention, as will be apparent to one skilled in the art.

In further reference toFIG. 4, the filter tuner hardware400may also include a synchronizer412. The synchronizer412may synchronize signals that are inputted from elements of the filter tuner hardware400so that the outputted signals are in synchronism with signals from other elements of the filter tuner hardware400. In performing such a synchronizing function, the synchronizer412may utilize one or more synchronous signals generated by elements of the filter tuner hardware400such as, for example, the oscillating signals that may be generated by the oscillators410,411.

The synchronizer412, in accordance with an embodiment of the present invention, may have inputs connected to one or more elements of the filter tuner hardware400including a finite state machine402, an 11-bit counter409, and a multiplexer415. The synchronizer412, in accordance with an embodiment of the present invention, may also have outputs connected to one or more elements of the filter tuner hardware400including a finite state machine402, a 14-bit counter408, and an 11-bit counter409.

The synchronizer412, of the filter tuner hardware400may include one or more sequential logic circuits. For example, the synchronizer412, may include one or more latches or flip-flops electrically coupled to one or more combinational logic elements. The synchronizer412may include other forms of sequential logic circuits within the scope of the embodiments of the present invention, as will be apparent to one skilled in the art.

The filter tuner hardware400may also include a combinational logic414. The combinational logic414may provide counter overflow and underflow status signals in response to input signals from the 11-bit counter409.

The combinational logic414, in accordance with an embodiment of the present invention, may have inputs connected to one or more elements of the filter tuner hardware400including an 11-bit counter409. Additionally, in accordance with an embodiment of the present invention, the combinational logic414may also transmit signals to controls204(FIG.2A). Alternatively, in accordance with another embodiment of the present invention, the combinational logic414may transmit to internal logic210(FIG. 2B) and to controls204.

The combinational logic414, in accordance with an embodiment of the present invention, may include a logic AND gate420and a logic NOR gate422that are electrically coupled. The combinational logic414may alternatively include other types of combinational logic elements configured to provide counter overflow and underflow status signals within the scope of the embodiments of the present invention, as will be apparent to one skilled in the art.

The filter tuner hardware400may also include a multiplexer415. The multiplexer415may selectively output one of a plurality of signals inputted to the multiplexer415. The multiplexer415may selectively output one of a plurality of input signals in response to signals inputted to the multiplexer415from controls204(FIG. 2A) that may respond to the execution of filter tuner firmware206(FIG.2A), in accordance with an embodiment of the present invention. Alternatively, the multiplexer415may selectively output one of a plurality of input signals in response to signals inputted to the multiplexer415from internal logic210(FIG.2B), in accordance with another embodiment of the present invention.

The multiplexer415, in accordance with an embodiment of the present invention, may have inputs connected to one or more elements of the filter tuner hardware400including an RC oscillator410. Additionally, the multiplexer415may have inputs connected to one or more external clock sources which may be used to provide reference clock signals for the purpose of testing the operation of the filter tuner hardware400. The multiplexer415, in accordance with an embodiment of the present invention, may also have outputs connected to one or more elements of the filter tuner hardware400including an 11-bit counter409and a synchronizer412. Additionally, in accordance with an embodiment of the present invention, the multiplexer415may also receive signals from controls204(FIG.2A). Alternatively, in accordance with another embodiment of the present invention, the multiplexer415may receive signals from internal logic210(FIG. 2B) and also transmit signals to controls204.

The multiplexer415of the filter tuner hardware400may include one or more combinational logic elements that form one or more combinational logic circuits to provide multiplexing functionality. For example, the multiplexer415may include one or more logic OR, AND, or NOT gates. The multiplexer415may include other types of combinational logic elements within the scope of the embodiments of the present invention, as will be apparent to one skilled in the art.

As discussed above with respect to elements of the filter tuner hardware400depicted inFIG. 4, several of these elements may receive and/or transmit signals to controls204(FIG.2A), in accordance with an embodiment of the present invention. Further, signals received from and/or transmitted to controls206may be responsive to the execution of filter tuner firmware206(FIG.2A). For example, as depicted inFIG. 4, the finite state machine402may receive control signals to execute a calibration cycle (i.e., “CALIBRATE”) or a measurement cycle (i.e., “MEASURE”) from controls204in response to execution of filter tuner firmware206. Further, the finite state machine402may transmit status signals indicating that a calibration or measurement cycle is done (i.e., “DONE”) to controls204. As another example, the RC oscillator410and the crystal oscillator411may receive enable inputs from controls204and the multiplexer415may receive a select input from controls204also. As another example, the 11-bit counter409may transmit a count output to controls204and the combinational logic414may transmit a counter overflow status output or counter underflow status output to controls204.

Alternatively, in accordance with another embodiment of the present invention, several elements of the filter tuner hardware400may receive and/or transmit signals to internal logic210(FIG. 2B) and/or transmit signals to controls204(FIG. 2A) which may be responsive to the execution of filter tuner firmware206(FIG.2A). For example, as depicted inFIG. 4, the finite state machine402may receive control signals to execute a calibration cycle (i.e., “CALIBRATE”) or a measurement cycle (i.e., “MEASURE”) from internal logic210. Further, the finite state machine402may transmit status signals indicating that a calibration or measurement cycle is done (i.e., “DONE”) to internal logic210. As another example, the RC oscillator410and the crystal oscillator411may receive enable inputs from internal logic210and the multiplexer415may receive a select input from internal logic210also. As another example, the 11-bit counter409may transmit a count output to controls204and the combinational logic414may transmit a counter overflow status output or counter underflow status output to internal logic210.

As discussed above with respect to elements of the filter tuner hardware300,400depicted inFIGS. 3 and 4, several of these elements may receive and/or transmit signals to controls204(FIG.2A), in accordance with an embodiment of the present invention. Additionally, signals received from and/or transmitted to controls206may be responsive to the execution of filter tuner firmware206(FIG.2A). Further, as discussed above with respect to elements of the filter tuner hardware300,400depicted inFIGS. 3 and 4, several of these elements may receive and/or transmit signals to internal logic210(FIG. 2B) and/or transmit signals to controls204which may be responsive to the execution of filter tuner firmware206, in accordance with another embodiment of the present invention. In this regard, the following descriptions will present methods, in accordance with embodiments of the present invention, that may be executed by filter tuner firmware206and/or internal logic210in conjunction with the filter tuner hardware300,400, controls204, and filter208in, for example, applications such as those depicted inFIGS. 2A and 2B. It is noted, though, that references made to elements ofFIGS. 2A,2B,3, and4in describing the following methods are made merely to facilitate the description of the embodiments of the present invention, and the utilization of the methods is not limited to applications with these elements.

Focusing now onFIG. 5, a flowchart diagram is shown representing a method500for a filter tuner in accordance with embodiments of the present invention. The method500begins at start step502. Following start step502, in step504, a filter208is tuned to a nominally optimal setting. A nominally optimal setting may be, for example, a setting at which the filter will have −1.0 dB loss at the nominal filter cutoff frequency. The determination of a nominally optimal initial setting for the filter may be made by execution of filter tuner firmware206, in accordance with an embodiment of the present invention. In accordance with another embodiment of the present invention, the setting determination may be made by internal logic210. The filter setting may be represented by one or more coarse tuning bits and by one or more fine tuning bits. For example, the filter setting may be represented by 6-bits for coarse-tuning and 6-bits for fine-tuning (i.e., a 12-bit setting).

In further regard to step504of the method500, the setting of the filter208may be made using control words transmitted to controls204from filter tuner firmware206, in accordance with an embodiment of the present invention, or from internal logic210, in accordance with another embodiment of the present invention. For example, a low-pass cutoff control word may be designated “TXF” and a high-pass cutoff control word may be designated “RXF.” Each control word (TXF, RXF) may be monotonic with higher frequency cutoffs being indicated by higher binary numbers. In response to the control words, the controls204may cause adjustments to the appropriate components of the filter208to occur which results in the tuning of the filter208to a nominally optimal setting.

Following step504, in step506, the enable input to the RC oscillator410is asserted in order to generate a temperature dependent reference frequency to drive the 11-bit counter409. The enable input of the RC oscillator may be asserted by signals from controls204in response to execution of filter tuner firmware206, in accordance with an embodiment of the present invention, or by signals from internal logic210, in accordance with another embodiment of the present invention. When enabled, the RC oscillator may operate at some nominal frequency such as, for example, 10 MHz. Although not shown in step506, as discussed above, an enable input may also be transmitted to the crystal oscillator411to enable it to provide oscillating signals.

Following step506, in step508, the “CALIBRATE” control word is asserted to initiate a calibration cycle by the filter tuner hardware400. The assertion of “CALIBRATE” may be made by filter tuner firmware206, in accordance with an embodiment of the present invention, or by internal logic210, in accordance with another embodiment of the present invention. Following step508, in step510, a calibration cycle is executed by the filter tuner hardware400. The steps involved in this execution step510are described below with regard to FIG.6.

Following step510, in step512, the “MEASURE” control word is asserted to initiate a measurement cycle by the filter tuner hardware400. The assertion of “MEASURE” may be made by filter tuner firmware206, in accordance with an embodiment of the present invention, or by internal logic210, in accordance with another embodiment of the present invention. Following step512, in step514, a measurement cycle is executed by the filter tuner hardware400. The steps involved in this execution step514are described below with regard to FIG.7.

Following step514, in step516, the filter208is tuned to correct the accuracy of the filter cutoff frequency. The steps involved in this execution step516are described below with regard to FIG.8. Following step516is the stop step518at which the method500is complete.

Focusing now onFIG. 6, a flowchart diagram is shown further representing a method510for a filter tuner in accordance with embodiments of the present invention as presented in FIG.5. Specifically a method510for execution of the calibration cycle of the method500(FIG. 5) is represented in accordance with embodiments of the present invention. The method510begins at start step602. Following start step602, in step604, 14-bit counter408is reset and 11-bit counter409is reset, for example, to zero. The input signals to the counters408,409to execute the reset may be transmitted from the finite state machine402.

Following step604, in step606, the counters408,409are started. The counters408,409may be started simultaneously, in accordance with embodiments of the present invention. The input signals to the counters408,409to initiate counting may be transmitted from the synchronizer412. When initiated, the 14-bit counter408may count at a fixed frequency generated by the crystal oscillator411, which inputs an oscillating signal to the counter408. The fixed frequency of the crystal oscillator411may be, for example, approximately 35 MHz, dependent on the characteristics of the crystal. When the 11-bit counter409is initiated to count, it may count at the temperature dependent reference frequency generated by the RC oscillator410.

A brief reference toFIG. 4shows that the RC oscillator410inputs an oscillating signal to the 11-bit counter409via the multiplexer415, which also receives an input from an external clock source. As discussed above in the description of the filter tuner hardware400, the multiplexer415may receive a select signal from either filter tuner firmware206(via controls204) or from internal logic210, in accordance with embodiments of the present invention. Thus, an oscillating signal may be transmitted to the 11-bit counter409from either the RC oscillator, under normal operation, or from an external clock source, under testing operation.

Continuing now with reference toFIG. 6, following step606, in step608the counters408,409are stopped when the 11-bit counter409reaches a predetermined count limit which may be, for example, 1024 counts. The counters408,409may be stopped simultaneously, in accordance with embodiments of the present invention. The determination that the counter409has reached the count limit may be made based on the count status signals transmitted from the counter409to either controls204or to internal logic210, in accordance with embodiments of the present invention. Once counter409has been determined to reach the count limit, signals from either controls204or internal logic210are transmitted to the filter tuner hardware400to stop the counting. The input signals to the counters408,409to stop counting may be transmitted from the synchronizer412.

Following step608, in step610, the count reached by the 14-bit counter408, when it was stopped in step608, is loaded to the 14-bit register404. The load signal to the register404may be transmitted form the finite state machine402in response to input signals to the finite state machine402indicating that the 11-bit counter409has reached the predetermined count limit.

Following step610, in step612, the “DONE” control word is asserted to indicate that the calibration cycle is complete. The asserted “DONE” signal is transmitted from the finite state machine402to either controls204or internal logic210, in accordance with embodiments of the present invention. Following step612is the stop step614at which the method510is complete.

Focusing now onFIG. 7, a flowchart diagram is shown further representing a method514for a filter tuner in accordance with embodiments of the present invention as presented in FIG.5. Specifically a method514for execution of the measurement cycle of the method500(FIG. 5) is represented in accordance with embodiments of the present invention. The method514begins at start step702. Following start step702, in step704, 14-bit counter408is reset and 11-bit counter409is reset, for example, to zero. The input signals to the counters408,409to execute the reset may be transmitted from the finite state machine402.

Following step704, in step706, the counters408,409are started. The counters408,409may be started simultaneously, in accordance with embodiments of the present invention. The input signals to the counters408,409to initiate counting may be transmitted from the synchronizer412. When initiated, the 14-bit counter408may count at a fixed frequency generated by the crystal oscillator411, which inputs an oscillating signal to the counter408. The fixed frequency of the crystal oscillator411may be, for example, approximately 35 MHz, dependent on the characteristics of the crystal. When the 11-bit counter409is initiated to count, it may count at the temperature dependent reference frequency generated by the RC oscillator410.

Following step706, in step708, the counters408,409are stopped when the 14-bit counter408reaches a count equivalent to the count that is stored in the 14-bit register404. The determination that the counter408has reached a count that is equivalent to the count stored in the register404may be based on the output signals from the comparator306. As is shown, for example, inFIG. 4, the output of the register404and the counter408are both transmitted to the inputs of the comparator306, and when these inputs to the comparator306are equivalent, an indicating signal may be transmitted from the comparator306to the finite state machine402. In response, signals may be transmitted from the state machine402to the synchronizer412, and the input signals to the counters408,409to stop counting may subsequently be transmitted from the synchronizer412.

Following step708, in step710, the “DONE” control word is asserted to indicate that the measurement cycle is complete. The asserted “DONE” signal is transmitted from the finite state machine402to either controls204or internal logic210, in accordance with embodiments of the present invention. Following step710is the stop step712at which the method514is complete.

Focusing finally onFIG. 8, a flowchart diagram is shown further representing a method516for a filter tuner in accordance with embodiments of the present invention as presented in FIG.5. Specifically a method516for tuning the filter208to correct the accuracy of the filter cutoff frequency in accordance with the method500(FIG. 5) is represented, in accordance with embodiments of the present invention. The method516begins at start step802.

Following start step802, in step804, the variation of the resistance-capacitance (“RC”) components of the filter208is determined. Since the temperature variation of the RC is dominated by the resistor in a filter208designed with, for example, High-resitivity Poly0 resistors and Interpoly capacitors, the determination of the variation of the RC is made by determining the variation of the resistance (“R”). Specifically, a percentage variation of R is determined by finding the difference of the count of counter409, that is reached at step708(FIG. 7) of the measurement cycle, to the predetermined count referenced in step608(FIG.6). The following equation may represent this determination:
RDIFF=CNTCNTR 409−CNTPRE-DET(Eq. 1)
The least significant bit (“LSB”) of RDIFF from Eq. 1 approximately represents a 0.1% temperature variation in the RC of the RC oscillator410, and the percentage change in the RC of the filter208is typically less than ±5%. Therefore, a percentage variation in the frequency of the RC oscillator410is approximately equal to a percentage change in the RC of the filter208, particularly for small percentage variations.

Following step804, in step806, the RC variation determined in step804is mapped to the filter tuning control words TXF (low-pass control) and RXF (high-pass control). The following equations may represent this mapping:
TXFNEW=TXFINIT+RDIFF*KTX(Eq. 2)
RXFNEW=RXFINIT+RDIFF*KRX(Eq. 3)
In Eq. 2 and Eq. 3 above, the constants KTXand KRXmay be values that are provided or determined for each nominal filter cutoff and these constants can have positive or negative values. To prevent changing the values of KTXand KRXtoo quickly, a certain amount of hysteresis may be introduced.

Following step806, in step808, the filter208is tuned. This tuning of the filter208may be made using the control words TXF and RXF transmitted to controls204from filter tuner firmware206or from internal logic210, in accordance with embodiments of the present invention. In response to the control words, the controls204may cause adjustments to the appropriate components of the filter208to occur which results in the tuning of the filter208to correct cutoff frequency accuracy affected by temperature variation.

It is emphasized that references made to elements ofFIGS. 2A,2B,3, and4in describing the preceding methods are made merely to facilitate the description of the embodiments of the present invention, and the utilization of the methods is not limited to applications with these elements. Further, the flowchart diagrams of the filter tuning methods500,510,514, and516described above and shown inFIGS. 5,6,7, and8show the architecture, functionality, and operation of possible implementations of the embodiments of the present invention. In this regard, each block may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). It should also be noted that in some alternative implementations, the functions noted in the blocks may occur in an order different from that shown in the figures.

It is further emphasized that the above-described embodiments of the present invention, particularly any “preferred” embodiments, are merely possible examples of the implementations that are merely set forth for a clear understanding of the principles of the invention. It will be apparent to those skilled in the art that many modifications and variations may be made to the above-disclosed embodiments of the present invention without departing substantially from the spirit and principles of the invention. All such modifications and variations are intended to be included herein within the scope of the disclosure and present invention and protected by the following claims.