Semiconductor light emitting device

According to one embodiment, a semiconductor light emitting device includes a metal substrate, a first semiconductor layer, a first semiconductor layer, a second semiconductor layer, a light emitting layer, a first intermediate layer and a second intermediate layer. The substrate has a coefficient of thermal expansion not more than 10×10−6 m/K. The first and second semiconductor layer include a nitride semiconductor. The second semiconductor layer is provided between the substrate and the first semiconductor layer. The emitting layer is provided between the first semiconductor layer and the second semiconductor layer. The first intermediate layer is provided between the substrate and the second semiconductor layer. The second intermediate layer is provided between the first intermediate layer and the second semiconductor layer. a surface roughness of a first surface of the substrate contacting the first intermediate layer is less than a thickness of the first intermediate layer.

CROSS-REFERENCE TO RELATED APPLICATION

This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2012-179800, filed on Aug. 14, 2012; the entire contents of which are incorporated herein by reference.

FIELD

Embodiments described herein relate generally to a semiconductor light emitting device.

BACKGROUND

One method for manufacturing a semiconductor light emitting device includes bonding a substrate that has excellent heat dissipation to a growth substrate on which a stacked body including a nitride semiconductor is provided, and subsequently removing the growth substrate. It is desirable to increase the reliability of the semiconductor light emitting device.

DETAILED DESCRIPTION

In general, according to one embodiment, a semiconductor light emitting device includes a metal substrate, a first semiconductor layer, a first semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type, a light emitting layer, a first intermediate layer and a second intermediate layer. The metal substrate has a coefficient of thermal expansion not more than 10×10−6m/K. The first semiconductor includes a nitride semiconductor. The second semiconductor layer is provided between the metal substrate and the first semiconductor layer. The second semiconductor layer includes a nitride semiconductor. The light emitting layer is provided between the first semiconductor layer and the second semiconductor layer. The light emitting layer includes a nitride semiconductor. The first intermediate layer is provided between the metal substrate and the second semiconductor layer to contact the metal substrate. The second intermediate layer is provided between the first intermediate layer and the second semiconductor layer. a surface roughness of a first surface of the metal substrate contacting the first intermediate layer is less than a thickness of the first intermediate layer.

The drawings are schematic or conceptual; and the relationships between the thicknesses and the widths of portions, the proportions of sizes between portions, etc., are not necessarily the same as the actual values thereof. Further, the dimensions and/or the proportions may be illustrated differently between the drawings, even for identical portions.

In the drawings and the specification of the application, components similar to those described in regard to a drawing thereinabove are marked with like reference numerals, and a detailed description is omitted as appropriate.

First Embodiment

FIG. 1is a schematic view showing a semiconductor light emitting device according to a first embodiment.

FIG. 2is a cross-sectional view in which portion A ofFIG. 1is enlarged.

The semiconductor light emitting device110of the embodiment includes a metal substrate10, a stacked body60, a first intermediate layer20, and a second intermediate layer30. The stacked body60includes a first semiconductor layer66, a light emitting layer64, and a second semiconductor layer62.

The semiconductor light emitting device110is formed by bonding between the stacked body60and the metal substrate (hereinbelow, called substrate bonding). A growth substrate18used to form the stacked body60is removed.

The metal substrate10supports the stacked body60. The metal substrate10has a first surface10a, and a second surface10bon the side opposite to the first surface10a. The first surface10ais the surface that contacts the first intermediate layer20described below.

Herein, an axis perpendicular to the first surface10aof the metal substrate10is taken as a Z axis. One axis perpendicular to the Z axis is taken as an X-axis direction. A direction perpendicular to the Z axis and the X axis is taken as a Y axis. Hereinbelow, “stacking” includes not only the case of being overlaid in contact with each other but also the case of being overlaid with another layer inserted therebetween. Further, being “provided on” includes not only the case of being provided in direct contact but also the case of being provided with another layer inserted therebetween.

It is favorable for the coefficient of thermal expansion of the metal substrate10to be near the coefficient of thermal expansion of the growth substrate18. The growth substrate18is, for example, one selected from a silicon (Si) substrate, a sapphire substrate, and a silicon carbide (SiC) substrate. The coefficient of thermal expansion of the Si substrate is 2.5×10−6m/K. The coefficient of thermal expansion of the sapphire substrate is 5.2×10−6m/K. The coefficient of thermal expansion of the SiC substrate is 3.7×10−6m/K. For example, the coefficient of thermal expansion of the metal substrate10is not more than 10×10−6m/K. Thereby, peeling in the substrate bonding is suppressed.

The thermal conductivity of the metal substrate10is higher than the thermal conductivity of the growth substrate18. For example, the thermal conductivity of the metal substrate10is not less than 160 W/m·K. Thereby, the heat from the stacked body60is emitted.

The metal substrate10includes, for example, a sintered impregnated metal. The metal substrate10includes a first metal portion including a first metal, and a second metal portion including a second metal dispersed in the first metal portion. The first metal portion is formed by sintering a powder of the first metal. The second metal portion is formed by causing the first metal portion to be impregnated with the second metal. An elution prevention agent of the second metal may be used in the impregnation. By using the sintered impregnated metal as the metal substrate10, the adhesion with the first intermediate layer20described below is better.

For example, one selected from the first metal portion and the second metal portion includes one selected from molybdenum (Mo) and tungsten (W); and the other selected from the first metal portion and the second metal portion includes copper (Cu).

FIG. 3is a graph showing the coefficient of thermal expansion and the thermal conductivity.

FIG. 3shows the coefficient of thermal expansion (CTE: 10−6m/K) and the thermal conductivity (TC: W/m·K) for various substrates.

FIG. 3shows laminated metals (LM) and sintered impregnated metals (SIM). The laminated metals LM shown inFIG. 3are metals in which Cu, Mo, and Cu are laminated and bonded by hot pressing. The proportion of Mo in the entirety is illustrated. Cu0.5Mo0.5, Cu0.35Mo0.65, and CuW are illustrated for the sintered impregnated metals SIM.

As shown inFIG. 3, the thermal conductivities of the laminated metals LM are higher than that of Si. However, as described below, there is a possibility that the lamination interface may peel in the substrate bonding.

Conversely, for the sintered impregnated metals SIM, the coefficient of thermal expansion CTE and the thermal conductivity TC change linearly with the composition ratio of Cu and Mo. The sintered metal does not peel at the interface with the contained metal. Accordingly, for example, it is favorable for the metal substrate10to include one selected from Cu0.5Mo0.5, Cu0.35Mo0.65, and CuW. In such a case, the coefficient of thermal expansion of the metal substrate10satisfies being not more than 10×10−6m/K. Also, the thermal conductivity of the metal substrate10satisfies being not less than 160 W/m·K by the metal substrate10including Cu. There is a tendency for the peeling of the metal to be suppressed even when the composition ratio of Mo in the metal substrate10is high.

The thickness of the metal substrate10is, for example, not more than 200 micrometers (μm). In the case where the thickness of the metal substrate10is thicker than 200 μm, there is a possibility that the growth substrate18and the stacked body60may peel due to the stress that occurs when cooling after the substrate bonding. On the other hand, when the thickness of the metal substrate10is not more than 200 μm, the peeling of the growth substrate18is suppressed.

Here, the first surface10aof the metal substrate10is polished by, for example, CMP (Chemical Mechanical Polishing). The surface roughness of the first surface10aof the metal substrate10is less than the thickness of the first intermediate layer20described below. In other words, the value of the surface roughness of the first surface10ais less than the value of the roughness of the first intermediate layer20. The first surface10ais covered with the first intermediate layer20along the recesses and protrusions of the first surface10a. Thereby, in the substrate bonding, diffusion of the metal (e.g., the Cu) included in the metal substrate10into the second intermediate layer30or diffusion of the metal (e.g., the Au and the Sn) included in the second intermediate layer30into the metal substrate10(the mutual diffusion of the metals) is suppressed.

The surface roughness of the metal substrate10is measured by, for example, AFM (Atomic Force Microscopy) or a surface roughness meter (Surfcorder). While “surface roughness” is not particularly limited, for example, “surface roughness” may be the arithmetic average surface roughness Ra specified by ES-B-0601.

The surface roughness of the first surface10aof the metal substrate10is, for example, not more than 100 nm, and more favorably not more than 50 nm. The diffusion of the metal recited above is markedly suppressed by the surface roughness of the first surface10abeing not more than 50 nm.

The stacked body60is provided on the first surface10aside of the metal substrate10. As described above, the stacked body60includes the first semiconductor layer66of the first conductivity type, the light emitting layer64, and the second semiconductor layer62of the second conductivity type.

The first conductivity type is, for example, an n type. The second conductivity type that is opposite to the first conductivity type is, for example, a p type. The first conductivity type may be the p type; and the second conductivity type may be the n type. The case where the first conductivity type is the n type and the second conductivity type is the p type is described as an example in the embodiment.

The first semiconductor layer66includes a nitride semiconductor. The conductivity type of the first semiconductor layer66is, for example, the n type. The first semiconductor layer66includes, for example, silicon (Si) as a dopant. The Si concentration of the first semiconductor layer66is not less than 1×1018cm−3. Thereby, the current spread length of the first semiconductor layer66lengthens; and the luminous efficiency increases.

The first semiconductor layer66includes a third surface66aon the side opposite to the metal substrate10. The third surface66ais the surface from which the light emitted from the light emitting layer64is mainly emitted to the outside.

The third surface66aof the first semiconductor layer66includes multiple recess/protrusion portions66s. The length between the adjacent protrusions of the recess/protrusion portions66sis longer than the peak wavelength inside the first semiconductor layer66of the emitted light that is radiated from the light emitting layer64. Thereby, the light extraction efficiency increases.

The second semiconductor layer62is provided between the metal substrate10and the first semiconductor layer66. The second semiconductor layer62includes a nitride semiconductor. The conductivity type of the second semiconductor layer62is, for example, the p type. The second semiconductor layer62includes, for example, magnesium (Mg) as a dopant. It is favorable for the concentration of Mg in the second semiconductor layer62to be, for example, 1×1021cm−3. Thereby, the second semiconductor layer62has an ohmic contact to a second electrode50.

Because the resistivity of the p-type nitride semiconductor is high, it is desirable for the thickness of the second semiconductor layer62to be not more than 100 nm. For example, the second semiconductor layer62includes an 80 nm GaN layer that contacts the light emitting layer64, and a 5 nm GaN layer that contacts the second electrode50.

The light emitting layer64is provided between the first semiconductor layer66and the second semiconductor layer62. The light emitting layer64includes a nitride semiconductor. The light emitting layer64includes, for example, AlxGayIn1-x-yN (0≦x≦1 and 0≦y≦1). The light emitting layer64includes, for example, a multiple quantum well structure (MQW) in which N periods of an AlGaN barrier layer and an InGaN well layer are alternately stacked. N is an integer of 2 or more. The thickness of each layer of the MQW structure is, for example, not less than 1 nm and not more than 10 nm.

The InGaN/GaN superlattice structure may be provided between the MQW structure and the first semiconductor layer66. Thereby, the difference of the lattice constants between the MQW structure and the first semiconductor layer66is relaxed.

The first semiconductor layer66is provided between a first electrode80and the light emitting layer64. The first electrode80may include titanium (Ti), an alloy of Ti and aluminum (Al), or a transparent oxide (e.g., ITO).

The first electrode80has, for example, a stacked structure. The first electrode80includes an Al layer contacting the first semiconductor layer66, a Ni layer provided on the Al layer, and a Au layer provided on the Ni layer. The thickness of the Al layer is not less than 100 nm and not more than 200 nm. The thickness of the Au layer is not less than 1 μm.

Other configurations of the first electrode80may include a four-layer structure of Ti/Al/Ni/Au or a five-layer structure of Ti/Al/Ta/Pt/Au. The configuration of the first electrode80is selected according to the thermal processes before and after the first electrode formation process.

A dielectric layer72is provided between the second semiconductor layer62and a third intermediate layer40. The dielectric layer72contacts the second semiconductor layer62and a protective layer76described below. The dielectric layer72also contacts the third intermediate layer40. The dielectric layer72is provided around the second semiconductor layer62as viewed from the Z-axis direction. The dielectric layer72includes, for example, silicon oxide (SiO2), silicon nitride (SiN), or silicon oxynitride (SiON).

The second electrode50is provided between the second semiconductor layer62and the second intermediate layer30described below. The second electrode50contacts the second semiconductor layer62. The second electrode50may include, for example, one selected from Ni and Ag. The second electrode50may include one platinum group metal selected from Pt, Ru, Os, Rh, Ir, and Pd.

The stacked body60has, for example, a truncated pyramid configuration.

The protective layer76is provided at least on the side surface of the light emitting layer64. For example, at least one selected from SiO2, SiN, and SiON is used as the protective layer76. Thereby, current leakage between the layers of the stacked body60is suppressed. The protective layer76covers a portion of the third surface66a.

The first intermediate layer20, the second intermediate layer30, and the third intermediate layer40will now be described.

The stacked body60and the metal substrate10are bonded via the first intermediate layer20, the second intermediate layer30, and the third intermediate layer40.

The first intermediate layer20is provided between the metal substrate10and the second semiconductor layer62.

The first intermediate layer20contacts the metal substrate10. The first intermediate layer20functions as a barrier layer that suppresses the diffusion of the metal. The first intermediate layer20is pre-provided on the first surface10aof the metal substrate10in the substrate bonding. The first intermediate layer20suppresses the mutual diffusion of the metals between the metal substrate10and the second intermediate layer30. Also, the first intermediate layer20strengthens the adhesion between the metal substrate10and the second intermediate layer30.

The first intermediate layer20includes Ti. Thereby, the mutual diffusion of the metals between the metal substrate10and the second intermediate layer30is suppressed.

The thickness of the first intermediate layer20is not less than 50 nm and not more than 1000 nm, and more favorably not less than 50 nm and not more than 200 nm. The first surface10ais covered with the first intermediate layer20by the thickness of the first intermediate layer20being not less than 50 nm. On the other hand, it is favorable for the thickness of the first intermediate layer20to be not more than 200 nm to improve the thermal conduction from the stacked body.

The first intermediate layer20may have a stacked structure. The details are described below.

The second intermediate layer30is provided between the first intermediate layer20and the second semiconductor layer62. The second intermediate layer30bonds the stacked body60to the metal substrate10.

The melting point of the material of the second intermediate layer30is lower than the melting point of the material of the first intermediate layer20. The melting point of the material of the second intermediate layer30is lower than the melting point of the material of the third intermediate layer40described below. The material of the second intermediate layer30is, for example, low melting-point solder. The second intermediate layer30includes, for example, gold (Au). For example, the material of the second intermediate layer30may include one selected from gold-tin (AuSn) and gold-indium (AuIn). The material of the second intermediate layer30may be Sn.

The thickness of the second intermediate layer30is not less than 1000 nm and not more than 10 μm, and more favorably not less than 1 μm and not more than 5 μm.

The third intermediate layer40is provided between the second electrode50and the second intermediate layer30. The third intermediate layer40includes Ti. The third intermediate layer40may have a stacked structure. The third intermediate layer40is, for example, TiW/Pt/TiW/Pt/Ti/Au. Thereby, the diffusion of the metal due to the third intermediate layer40is suppressed. The material of the third intermediate layer40may be the same as the material of the second intermediate layer30.

The thickness of the third intermediate layer40is, for example, not less than 50 nm and not more than 1000 nm, and more favorably not less than 50 nm and not more than 200 nm.

A back surface electrode90contacts the second surface10bof the metal substrate10. The back surface electrode90may include, for example, Au.

Processing of the second surface10bof the metal substrate10such as polishing, etc., is not performed. The surface roughness of the second surface10bof the metal substrate10is greater than the surface roughness of the first surface10a. The surface roughness of the second surface10bof the metal substrate10is, for example, not less than 200 nm. Thereby, the back surface electrode90closely adheres to the metal substrate10due to an anchor effect.

The bonding portion of the semiconductor light emitting device110(portion A ofFIG. 1) will now be described in detail usingFIG. 2.

The first intermediate layer20may have a stacked structure. The first intermediate layer20includes a first layer22, a second layer24, and a third layer26. The first layer22is provided between the metal substrate10and the second intermediate layer30to contact the metal substrate10. The first layer22includes Ti. The first layer22may include Ni. The thickness of the first layer22is not less than 10 nm and not more than 200 nm. The thickness of the first layer22is, for example, 50 nm. The first layer22suppresses the diffusion of the metal included in the metal substrate10toward the second intermediate layer30.

The second layer24is provided between the first layer22and the second intermediate layer30. The second layer24includes a metal different from the material of the first layer22. The second layer24includes, for example, Pt. The second layer24may include one selected from Ti and Au. The thickness of the second layer24is not less than 10 nm and not more than 200 nm. The thickness of the second layer24is, for example, 50 nm.

The third layer26is provided between the second layer24and the second intermediate layer30. The third layer26includes Ti. Thereby, the adhesion between the second layer24and the second intermediate layer30is increased. Further, the diffusion of the metal included in the second intermediate layer30toward the metal substrate10is suppressed. The third layer26may include Au.

The state of the substrate bonding will now be described in comparison to a reference example.

In a semiconductor light emitting device of a first reference example, the metal substrate is a substrate of a laminated metal. The metal substrate includes, for example, a first metal layer including Cu, a second metal layer including Cu, and a third metal layer including Mo provided between the first metal layer and the second metal layer. The first intermediate layer20is provided between the first metal layer and the second intermediate layer. The stacked body contacts a growth substrate. The stacked body is bonded to the metal substrate via the second intermediate layer.

In the substrate bonding of the first reference example, strong stress occurs at the interface between the first metal layer and the second metal layer and the interface between the second metal layer and the third metal layer. Therefore, there is a possibility that mechanical damage such as peeling, etc., may occur at the interfaces recited above.

A semiconductor light emitting device of a second reference example differs from the semiconductor light emitting device of the first reference example in that the disposition of the metal layers is reversed. In the second reference example, the metal substrate includes, for example, a fourth metal layer including Cu, a fifth metal layer including Cu, and a sixth metal layer including Mo provided between the fourth metal layer and the fifth metal layer.

In the substrate bonding of the second reference example as well, there is a possibility that the mechanical damage such as peeling, etc., may occur at the interface between the fourth metal layer and the fifth metal layer and the interface between the fifth metal layer and the sixth metal layer. Also, there is a possibility that the mutual diffusion of the metals between the Cu of the fourth metal layer and the second intermediate layer may occur.

In a semiconductor light emitting device of a third reference example, the metal substrate is a substrate of a sintered impregnated metal. The surface roughness of the surface of the metal substrate is, for example, greater than the thickness of the first intermediate layer. The surface roughness of the surface of the metal substrate is, for example, not less than 200 nm. Otherwise, the configuration of the third reference example is similar to the configuration of the first embodiment.

Here,FIG. 4AandFIG. 4Bare cross section SEM images of the state of the substrate bonding. The first intermediate layer20has, for example, a three-layer structure and includes the first layer22, the second layer24, and the third layer26.

FIG. 4Ashows the state of the substrate bonding in the manufacturing process of the semiconductor light emitting device193of the third reference example.

FIG. 4Bshows the state of the substrate bonding in the manufacturing process of the semiconductor light emitting device110of the embodiment.

The surface of a first surface13aof the third reference example as shown inFIG. 4Ais rougher than the surface of the first surface10aof the metal substrate10of the first embodiment. The first intermediate layer20is discontinuous in portion B. Therefore, the metal (e.g., the Cu) included in the metal substrate13diffuses from the metal substrate13toward the second intermediate layer30. EDX (Energy Dispersive X-ray spectrometry) analysis shows that Cu is detected at the second intermediate layer30of portion B. In the case where, for example, Au is used as the second intermediate layer30, the composition of the AuCu occurring due to the mutual diffusion is unstable. By such mutual diffusion, peeling of the metal substrate13occurs easily in the semiconductor light emitting device of the third reference example.

Conversely, in the semiconductor light emitting device110of the first embodiment as shown inFIG. 4A, the first surface10aof the metal substrate10is polished by, for example, CMP. The surface roughness of the first surface10aof the metal substrate10is less than the thickness of the first intermediate layer20. In this example, the surface roughness of the first surface10aof the metal substrate10is not more than 50 nm. The surface roughness of the first surface10aof the metal substrate10is 25 nm.

In the first embodiment, the first surface10ais covered with the first intermediate layer20along the recesses and protrusions of the first surface10a. Thereby, in the substrate bonding, the mutual diffusion of the metals between the metal substrate10and the second intermediate layer30is suppressed. In the semiconductor light emitting device110, the peeling of the metal substrate10is suppressed. In the semiconductor light emitting device110, the heat dissipation due to the metal substrate10is maintained for a long period of time. Therefore, a long life is realized for the semiconductor light emitting device110.

Thus, according to the embodiment, various defects that may occur in the substrate bonding are suppressed.

Second Embodiment

FIG. 5is a flowchart showing a method for manufacturing a semiconductor light emitting device according to a second embodiment.

FIG. 6AtoFIG. 8are schematic cross-sectional views showing the method for manufacturing the semiconductor light emitting device.

As shown inFIG. 5, the method for manufacturing the semiconductor light emitting device according to the second embodiment includes substrate bonding (step S101) and removing the growth substrate (step S102).

In the substrate bonding (step S101), the metal substrate10and the stacked body60which is provided on the growth substrate18are disposed such that the second semiconductor layer62opposes the first intermediate layer20and are bonded via the second intermediate layer30.

In the removal of the growth substrate (step S102), the growth substrate18is removed from the stacked body60.

The details will now be described.

As shown inFIG. 6A, the substrate bonding (step S101) includes, for example, a process of preparing the growth substrate18on which the stacked body60is provided. The process of preparing the growth substrate18includes, for example, the following processes.

InFIG. 6A, an axis perpendicular to the growth substrate18is taken as a Z1 axis. One axis perpendicular to the Z1 axis is taken as an X1-axis direction. A direction perpendicular to the Z1 axis and the X1 axis is taken as a Y1 axis. In this drawing, being “formed on A” means being formed on A in the Z1-axis direction. InFIG. 6A, the Z1-axis direction is a direction that is opposite to the Z-axis direction of the other drawings.

The growth substrate18is, for example, one selected from a Si substrate, a sapphire substrate, and a SiC substrate. The n-type first semiconductor layer66is formed on the growth substrate18. The first semiconductor layer66may include a buffer layer. Then, the light emitting layer64is formed on the first semiconductor layer66. For example, the light emitting layer64has the MQW structure recited above. It is favorable for the growth temperature of the light emitting layer64to be not less than 900° C. and not more than 950° C. The p-type second semiconductor layer62is formed on the light emitting layer64.

The dielectric layer72is formed on the second semiconductor layer62. A portion of the dielectric layer72is selectively removed. The second electrode50is formed on the second semiconductor layer62to contact the second semiconductor layer62.

The third intermediate layer40is formed on the second electrode50and the dielectric layer72. The third intermediate layer40has a stacked structure. For example, TiW/Pt/TiW/Pt is formed on the stacked body60by sputtering. Then, Ti/Au is formed by vacuum vapor deposition.

As shown inFIG. 6B, the substrate bonding (step S101) may include, for example, a process of preparing the metal substrate10in parallel with the process of preparing the growth substrate18. The process of preparing the metal substrate10includes, for example, the following processes.

A powder of the first metal (e.g., Mo) is sintered. Thereby, the first metal portion, which is a sintered body that includes the first metal, is formed. An elution prevention agent of the second metal is coated onto the first metal portion. Then, the first metal portion is impregnated with the second metal. At this time, the elution prevention agent is removed. The coefficient of thermal expansion of the metal substrate10thus formed is not more than 10×10−6m/K.

Then, the first surface10aof the metal substrate10is polished by CMP. The surface roughness of the first surface10aprior to the polishing is, for example, 200 nm or more. The surface roughness of the first surface10aafter the polishing is, for example, not more than 50 nm.

Continuing, the first intermediate layer20is formed on the first surface10aof the metal substrate10. The first intermediate layer20has, for example, a stacked structure. For example, the first layer22including Ti, the second layer24including Pt, and the third layer26including Ti are formed on the first surface10aby vacuum vapor deposition.

Then, the second intermediate layer30is formed on the first intermediate layer20. The second intermediate layer30may include, for example, low melting-point solder. For example, one selected from AuSn, AuIn, and Sn is formed as the second intermediate layer30on the first intermediate layer20by vacuum vapor deposition. The material of the second intermediate layer30is selected according to the bonding method recited below.

Continuing as shown inFIG. 7A, the metal substrate10and the stacked body60which is provided on the growth substrate18are disposed such that the second semiconductor layer62opposes the first intermediate layer20. The disposition is such that the +Z direction of the metal substrate10opposes the +Z1 direction of the growth substrate18. The stacked body60and the metal substrate10are bonded via the second intermediate layer30by heating in this state. For example, eutectic fusion or liquid phase diffusion bonding is used as the bonding method.

At this time, the surface roughness of the first surface10aof the metal substrate10is less than the thickness of the first intermediate layer20. Thereby, in the substrate bonding, the mutual diffusion of the metals between the metal substrate10and the second intermediate layer30is suppressed.

Then, as shown inFIG. 7B, the removal of the growth substrate (step S102) is performed. The growth substrate18is removed from the stacked body60. Thereby, the third surface66aof the first semiconductor layer66is exposed. For example, laser lift-off, substrate polishing, wet etching, or dry etching may be used to remove the growth substrate18.

In the case where the growth substrate18is the sapphire substrate, for example, laser lift-off is used. The laser beam is irradiated in the direction (the −Z direction) from the growth substrate18toward the stacked body60. The irradiation power density of the laser is, for example, not less than 0.65 J/cm2and not more than 0.80 J/cm2. Thereby, the sapphire substrate is peeled.

As shown inFIG. 8, the method for manufacturing the semiconductor light emitting device may include, for example, the following processes.

The stacked body60is selectively removed by dry etching. Thereby, the stacked body60is patterned into a truncated pyramid configuration.

Then, the multiple recess/protrusion portions66sare formed in the third surface66aof the first semiconductor layer66. For example, anisotropic etching of the first semiconductor layer66is performed using a strongly alkaline aqueous solution of potassium hydroxide and/or sodium hydroxide. The etching temperature is, for example, not less than 60° C. and not more than 80° C.

Continuing, the first electrode80is formed on the first semiconductor layer66by vacuum vapor deposition, etc.

Third Embodiment

FIG. 9is a schematic cross-sectional view showing a semiconductor light emitting device according to a third embodiment.

The aspects of the semiconductor light emitting device120according to the third embodiment that differ from those of the semiconductor light emitting device110according to the first embodiment will now be described.

As shown inFIG. 9, a portion of the stacked body60is removed, for example, by dry etching. The first semiconductor layer66includes the third surface66aon the side opposite to the metal substrate10, and a fourth surface66bon the side opposite to the third surface66a.

The fourth surface66bis provided at a position where a portion of the stacked body60is removed.

A first dielectric layer721is provided in contact with the fourth surface66bof the first semiconductor layer66, the side surface of the light emitting layer64, and the side surface of the second semiconductor layer62. The first dielectric layer721also functions as a protective layer of the light emitting layer64.

The first electrode80contacts the fourth surface66bof the first semiconductor layer66. The first electrode80includes, for example, a contact portion81and a draw-out portion82. The contact portion81contacts the fourth surface66bof the first semiconductor layer66. The draw-out portion82contacts the contact portion81. The first dielectric layer721is provided between the first semiconductor layer66and the draw-out portion82. The draw-out portion82extends outward (e.g., in the X direction) from the stacked body60as viewed from the Z direction. A pad85is provided on a portion of the draw-out portion82extending outward from the stacked body60.

A second dielectric layer722is provided between the first electrode80and the third intermediate layer40. The first electrode80and the second electrode50are electrically insulated by the second dielectric layer722. Thereby, electrical shorts between the first electrode80and the second electrode50in the substrate bonding are suppressed.

The second electrode50is provided between the third intermediate layer40and the second semiconductor layer62. The second electrode50contacts the second semiconductor layer62.

The second electrode50has an ohmic contact with the second semiconductor layer62. The second electrode50includes, for example, an ohmic contact layer that includes one selected from Ag and Al, a highly reflective layer, and a cap layer that prevents migration.

In the semiconductor light emitting device110, light is absorbed by the first electrode80. Conversely, in the semiconductor light emitting device120, the light is not shielded by the first electrode80. In the semiconductor light emitting device120, the pad85is disposed outward from the stacked body60. A bonding wire connected to the pad85does not shield the light emitting surface (the third surface66a). In the embodiment, the light extraction efficiency increases. In the embodiment, for example, metal-organic chemical vapor deposition (MOCVD), metal-organic vapor phase epitaxy (MOVPE), molecular beam epitaxy (MBE), and hydride vapor phase epitaxy (HVPE) may be used to grow the semiconductor layer.

For example, in the case where MOCVD or MOVPE is used, the following source materials may be used when forming the semiconductor layers. For example, TMGa (trimethylgallium) and TEGa (triethylgallium) may be used as the source material of Ga. For example, TMIn (trimethylindium), TEIn (triethylindium), etc., may be used as the source material of In. For example, TMAl (trimethylaluminum), etc., may be used as the source material of Al. For example, NH3(ammonia), MMHy (monomethylhydrazine), DMHy (dimethylhydrazine), etc., may be used as the source material of N. SiH4(monosilane), Si2H6(disilane), etc., may be used as the source material of Si.

According to the embodiment recited above, a semiconductor light emitting device having high reliability can be provided.

In the specification, “nitride semiconductor” includes all compositions of semiconductors of the chemical formula BxInyAlzGa1-x-y-zN (0≦x≦1, 0≦y≦1, 0≦z≦1, and x+y+z≦1) for which the composition ratios x, y, and z are changed within the ranges respectively. “Nitride semiconductor” further includes group V elements other than N (nitrogen) in the chemical formula recited above, various elements added to control various properties such as the conductivity type and the like, and various elements included unintentionally.

Hereinabove, exemplary embodiments of the invention are described with reference to specific examples. However, the invention is not limited to these specific examples. One skilled in the art may similarly practice the invention by appropriately selecting specific configurations of components from known art; and such practice is included in the scope of the invention to the extent that similar effects are obtained.