Semiconductor integrated circuit device

First, second, and third power wirings and plurality of first signal wirings are formed on the upper layer of a semiconductor substrate, and at least one second signal wiring is formed on the upper layer of the plurality of first signal wirings. First and second power wirings are mutually separated in the cell height direction and extended in the cell width direction. Third power wiring extends between the first and second power wirings in the cell width direction. The plurality of first signal wirings are separated from first, second, and third power wirings, and electrically connected to at least one of the plurality of circuit elements. At least one second signal wiring extends in the cell width direction, and electrically connected to at least one of the plurality of circuit elements and the plurality of first signal wirings.

BACKGROUND

1. Technical Field

The present invention relates to a semiconductor integrated circuit device, and, in particular, to a semiconductor integrated circuit device which is provided with a standard logic cell having a multi-height structure.

2. Background Art

As a method of forming a semiconductor integrated-circuit on a semiconductor substrate, a standard logic cell method has been known. The standard logic cell method is a method of designing a Large-Scale Integration (LSI) chip by providing a basic unit (for example, an inverter, a latch, a flip-flop, a full adder, or the like) having a specific logical function as a standard logic cell in advance, disposing a plurality of standard logic cells on a semiconductor substrate and connecting between the standard logic cells using metal wirings.

Recently, with accelerated demands for high-speed and small area in a semiconductor integrated-circuit, a method of applying a double height structure to a standard logic cell (for example, refer to Japanese Patent Unexamined Publication No. 7-249747) has been known as a method of enabling a transistor disposition region, which occupies the interior of a cell, to be effectively enlarged.FIG. 12illustrates the schematic layout of a semiconductor integrated circuit device disclosed in Japanese Patent Unexamined Publication No. 7-249747. The semiconductor integrated circuit device includes standard logic cell901which has a single height structure (hereinafter, denoted by “single height cell”), and standard logic cell902which has a double height structure (hereinafter, denoted by “double height cell”). The cell height of single height cell901is uniform, and the cell width of single height cell901can be enlarged. Double height cell902has a cell height which is twice as high as the cell height of single height cell901. Since double height cell902can enlarge the channel width of a transistor, which occupies the interior of a cell, by commoditizing a P-well region (or an N-well region), the drive capability of the transistor can be improved without enlarging the cell width, unlike single height cell901.

Since a region where wiring is possible can be enlarged by changing the structure of the standard logic cell from a single height structure to the double height structure, the degree of the freedom of the disposition of contacts or wirings can be increased. As a result, M1 wiring which extends in the X-axis direction (cell width direction) can be disposed. A wiring path can be also circumvented using M2 wiring. M1 wiring is a wiring which is formed on a first metal wiring layer (that is, a metal wiring layer which is the nearest to a semiconductor substrate) disposed on the upper layer of the semiconductor substrate, and M2 wiring is a wiring which is formed on a second metal wiring layer (that is, a metal wiring layer which is the second nearest to the semiconductor substrate) disposed on the upper layer of the first metal wiring layer. M2 wiring extends in the Y-axis direction (cell height direction).

The circumvention of the wiring path using M2 wiring, which extends in the Y-axis direction, will be described with reference toFIG. 13.FIG. 13is an example of the layout of cell region903surrounded by the dotted-line of double height cell902shown inFIG. 12. Double height cell902includes three power wirings which extend in parallel with X-axis direction, and the cell height of double height cell902corresponds to 18 tracks. Cell region903corresponds to a part of the cell region between any one of power wiring WP81of the power wirings of both ends and center power wiring WP82, and the separation distance between power wirings WP81and WP82corresponds to 9 tracks (that is, half of the cell height). Generally, the cell height of the standard logic cell is expressed using the number of wirings (that is, the number of wiring tracks) which can be added in the standard logic cell and which extend in the X-axis direction.

As shown inFIG. 13, when M1 wiring W800which extends in the X-axis direction is disposed between PMOS transistor PM9and NMOS transistor NM9, it is difficult to electrically connect each of the drain regions of PMOS transistor PM9and NMOS transistor NM9using M1 wiring. The drain region of PMOS transistor PM9is electrically connected to M1 wiring W801through contact C801, the drain region of NMOS transistor NM9is electrically connected to M1 wiring W802through contact C802, and each of M1 wirings W801and W802is electrically connected to M2 wiring W901through vias V901and V902.

In double height cell, M2 wiring which extends in the Y-axis direction is used in order to circumvent the wiring path. Not only in the double height cell but also in a standard logic cell which includes a multi-height structure, M2 wiring which extends in the Y-axis direction (cell height direction) is used in order to circumvent the wiring path. The standard logic cell which includes the multi-height structure is the standard logic cell which has a cell height n times (n is an integer number which is equal to or greater than 2) higher than the cell height of a single height cell.

SUMMARY

However, since a region where wiring is possible is narrowed by reducing the cell height of the standard logic cell, the degree of freedom of wiring of M1 wiring is lowered. Therefore, there is a case where it is difficult to dispose M1 wiring which extends in the cell width direction (that is, a case where it is difficult to extend M1 wiring in the cell width direction). Even when M2 wiring which extends in the cell height direction is used, it may be difficult to circumvent a wiring path, so that it may be difficult to electrically connect between circuit elements (that is, it is difficult to configure a circuit which has a desired logic function). Therefore, it is difficult to reduce the cell height of the standard logic cell. It is also difficult to reduce the cell height of a standard logic cell which has a multi-height structure as well as the double height structure.

The present invention enables the cell height of a standard logic cell to be reduced while the electrical connection relationship between the circuit elements of the standard logic cell is maintained in a semiconductor integrated circuit device which is provided with the standard logic cell having a multi-height structure.

According to a first aspect of the invention, a semiconductor integrated circuit device is a semiconductor integrated circuit device which includes a standard logic cell. The standard logic cell includes a plurality of circuit elements which are formed on a semiconductor substrate, and first and second power wirings which are respectively formed on the upper layer of the semiconductor substrate, which are separated from each other in the cell height direction in a planar view and extend in the cell width direction which is perpendicular to the cell height direction, and which supply a first reference voltage. The standard logic cell further includes a third power wiring which is formed on the upper layer of the semiconductor substrate, which extends in the cell width direction between the first and second power wirings in the planar view, and which supplies a second reference voltage which is different from the first reference voltage. The standard logic cell further includes a plurality of first signal wirings which are respectively formed on the upper layer of the semiconductor substrate, which are separated from the first, second, and third power wirings in the planar view, and which are electrically connected to at least one of the plurality of circuit elements, and includes at least one second signal wiring which is formed on the upper layer of the plurality of first signal wirings, which extends in the cell width direction in the planar view, and which is electrically connected to at least one of the plurality of circuit elements and the plurality of first signal wirings. In the semiconductor integrated circuit device, even when it is difficult to dispose the first signal wirings which extend in the cell width direction, a wiring path can be circumvented using the second signal wiring which extends in the cell width direction, so that the cell height of the standard logic cell can be reduced while the electrical connection relationship between the circuit elements is maintained.

A plurality of second signal wirings may be included in the standard logic cell, and the standard logic cell may further include a first auxiliary wiring which is formed on the same layer with the plurality of second signal wirings, which extends in the cell height direction in the planar view, and which connects two second signal wirings from among the plurality of second signal wirings. With this configuration, even when it is difficult to dispose the first signal wirings which extend in the cell width direction and the first signal wiring which extends in the cell height direction, the wiring path can be circumvented using the first auxiliary wiring and a bent wiring which includes two second signal wirings, so that the cell height of the standard logic cell can be reduced while the electrical connection relationship between the circuit elements is maintained.

The first auxiliary wiring may extend in the cell height direction across the third power wiring in the planar view, and may connect the second signal wiring, which is disposed between the first and third power wirings, with the second signal wiring, which is disposed between the second and third power wirings, from among the plurality of second signal wirings. With this configuration, the circuit elements can be electrically connected across the third power wiring. Therefore, a wiring (for example, a gate wiring) may not be additionally formed in order to circumvent the third power wiring, so that the cell area of the standard logic cell can be prevented from increasing.

The first auxiliary wiring may extend in the cell height direction across the third power wiring in the planar view, and may connect two adjacent second signal wirings, which interpose the third power wiring therebetween, from among the plurality of second signal wirings. With this configuration, the deterioration of the degree of freedom of disposition of another second signal wiring can be suppressed.

The standard logic cell may further include a second auxiliary wiring which is integrally formed with a single second signal wiring from among the plurality of second signal wirings on the same layer with the plurality of second signal wirings, which extends in the cell height direction in the planar view, and which electrically connects the corresponding second signal wiring to at least one of the plurality of circuit elements and the plurality of first signal wirings. With this configuration, even when it is difficult to dispose the first signal wiring which extends in the cell width direction and the first signal wiring which extends in the cell height direction, the wiring path can be circumvented using the second auxiliary wiring and a bent wiring having the second signal wiring, so that the cell height of the standard logic cell can be reduced while the electrical connection relationship between the circuit elements is maintained.

A single second signal wiring may be included in the standard logic cell, and the standard logic cell may further include an auxiliary wiring which is integrally formed with the second signal wiring on the same layer with the second signal wiring, which extends in the cell height direction in the planar view, and which electrically connects the second signal wiring to at least one of the plurality of circuit elements and the plurality of first signal wirings.

As described above, the cell height of the standard logic cell can be reduced while the electrical connection relationship between the circuit elements of the standard logic cell is maintained.

DESCRIPTION OF EMBODIMENTS

Embodiments will be described in detail with reference to the accompanying drawings. The same reference numerals are used to indicate the same or equivalent parts throughout the drawings, and the description thereof will not be repeated.

First Exemplary Embodiment

FIG. 1illustrates an example of the layout of a standard logic cell which is provided in a semiconductor integrated circuit device according to a first embodiment. The standard logic cell includes a flip-flop as shown inFIG. 2. The standard logic cell includes a plurality of circuit elements (here, diffusion layer DF and gate wiring GW which are the components of a MOS transistor), power wirings WP1, WP2, and WP3(first, second, and third power wirings), a plurality of first signal wirings WS1, and a plurality of second signal wirings WS2.

The plurality of circuit elements are formed on semiconductor substrate SUB. Power wirings WP1, WP2, and WP3and the plurality of first signal wirings WS1are formed on the upper layer of semiconductor substrate SUB. The plurality of second signal wirings WS2are formed on the upper layers of the plurality of first signal wirings WS1. For example, power wirings WP1, WP2, and WP3and the plurality of first signal wirings WS1are formed on the first wiring layer (for example, a first metal wiring layer which is the nearest to semiconductor substrate SUB) which is disposed on the upper layer of semiconductor substrate SUB, and the plurality of second signal wirings WS2are formed on the second wiring layer (for example, a second metal wiring layer which is the second nearest to semiconductor substrate SUB) which is disposed on the upper layer of the first wiring layer. Here, power wirings WP1, WP2, and WP3and the plurality of first signal wirings WS1are configured by M1 wiring (wiring formed on the first metal wiring layer), and the plurality of second signal wiring WS2are configured by M2 wiring (wiring formed on the second metal wiring layer). Only a circumferential line is illustrated to indicate M2 wiring in the drawing.

In planar view, power wirings WP1and WP2are separated from each other in the Y-axis direction and are extended in the X-axis direction (direction which is perpendicular to the Y-axis direction). Here, the planar view corresponds to a case where the standard logic cell is viewed from the normal line direction of the principal surface of semiconductor substrate SUB, the X-axis direction corresponds to the cell width direction of the standard logic cell, and the Y-axis direction corresponds to the cell height direction of the standard logic cell. Power wiring WP3extends in the X-axis direction between power wirings WP1and WP2. In planar view, each of the plurality of first signal wirings WS1is separated from the first, second, and third power wirings and each of the plurality of second signal wirings WS2extends in the X-axis direction. Here, first signal wiring WS1corresponds to M1 wiring excluding power wirings WP1, WP2, and WP3from among the plurality of M1 wirings which are formed on the first metal wiring layer in the standard logic cell, second signal wiring WS2corresponds to M2 wirings which are formed on the second metal wiring layer in the standard logic cell.

Power wirings WP1and WP2supply power voltage (first reference voltage), and power wiring WP3supplies ground voltage (second reference voltage). Each of the plurality of first signal wirings WS1is electrically connected to at least one of the plurality of circuit elements (diffusion layer DF and gate wiring GW) via a contact, and each of the plurality of second signal wirings WS2is electrically connected to at least one of the plurality of circuit elements and the plurality of first signal wirings WS1through a via.

Here, the contact is a connection region where diffusion layer DF (or gate wiring GW) electrically connects to M1 wiring, and the via is a connection region where M1 wiring electrically connects to M2 wiring.

The cell height of the standard logic cell shown inFIG. 1corresponds to 12 tracks. 1 track is a unit which is determined based on a minimum wiring width and a minimum wiring interval, and corresponds to the interproximal interval of the center line of a wiring track. The wiring track corresponds to the reference line, such as a grid line, of the wiring disposition, and the center line of the plurality of wiring tracks performs division in the Y-axis direction at equal intervals and extends in the X-axis direction. Here, power wirings WP1, WP2, and WP3are formed to overlap with 0-th wiring track T0, sixth wiring track T6, twelfth wiring track T12, respectively, in planar view. The separation distance between power wirings WP1and WP3corresponds to 6 tracks, and the separation distance between power wirings WP2and WP3corresponds to 6 tracks. The separation distance between power wirings WP1and WP3is equal to the separation distance between power wirings WP2and WP3. Each of the plurality of second signal wirings WS2is disposed to overlap with any one wiring track of wiring tracks T0to T12in the planar view. That is, each of the plurality of second signal wirings WS2is formed to be separated at a regular interval in the Y-axis direction in the planar view.

(Part of Circuit Configuration of Standard Logic Cell)

FIG. 3illustrates circuit region100, which is surrounded by a dotted-line, of the circuit configuration of the standard logic cell shown inFIG. 2. Circuit region100includes inverter11, transfer gate12, two-input NAND circuit13, and tri-state inverter14. Two input NAND circuits13and tri-state inverter14are included in a slave latch. Inverter11includes PMOS transistor PM11and NMOS transistor NM11, transfer gate12includes PMOS transistor PM12and NMOS transistor NM12. Two input NAND circuits13includes PMOS transistors PM13and PM14and NMOS transistors NM13and NM14, and tri-state inverter14includes PMOS transistors PM15and PM16and NMOS transistors NM15and NM16. Connection wiring W1electrically connects the output of inverter11(the drains of PMOS transistor PM11and NMOS transistor NM11) to the input of transfer gate12(the sources of PMOS transistor PM12and NMOS transistor NM12). Connection wiring W2electrically connects to transfer gate12(the gate of NMOS transistor NM12) and to tri-state inverter14(the gate of PMOS transistor PM15). Connection wiring W3electrically connects the output of transfer gate12(the drains of PMOS transistor PM12and NMOS transistor NM12), the input of two-input NAND circuit (the gates of PMOS transistor PM13and NMOS transistor NM14), and the output of tri-state inverter14(the drains of PMOS transistor PM16and NMOS transistor NM15). Connection wiring W4electrically connects the output of two-input NAND circuit (the drains of PMOS transistors PM13and PM14and NMOS transistor NM13) to the input of tri-state inverter14(the gates of PMOS transistor PM16and NMOS transistor NM15).

(Part of Example of Layout of Standard Logic Cell)

FIG. 4illustrates a part of an example of the layout of the standard logic cell corresponding to the part (circuit region100) of the circuit configuration of the standard logic cell shown inFIG. 3. First signal wirings WS101, WS102, and WS103correspond to connection wirings W1, W2, and W3shown inFIG. 3, respectively, and the combination of first signal wirings WS104and WS105and second signal wiring WS201corresponds to connection wiring W4shown inFIG. 3.

The gates of PMOS transistor PM16and NMOS transistor NM15(the input of tri-state inverter14) are electrically connected to first signal wiring WS104through a contact, and the drains of PMOS transistor PM13and PM14and NMOS transistor NM13(the output of two-input NAND circuit13) are electrically connected to first signal wiring WS105through a contact. In this case, since first signal wiring WS104is surrounded by three first signal wirings WS101, WS102, and WS103, it is difficult to extend first signal wiring WS104in the X-axis direction (cell width direction). Since power wiring WP3is proximally disposed to the circumference of first signal wiring WS101, an area, in which new first signal wiring (M1 wiring) can be formed, is not secured between first signal wiring WS101and power wiring WP3. Since power wiring WP2is proximally disposed to the circumference of first signal wiring WS103, an area, in which new first signal wiring (M1 wiring) can be formed, is not secured between first signal wiring WS103and power wiring WP2. Thus, it is difficult to dispose new M1 wiring which connects first signal wirings WS104and WS105. When first signal wirings WS104and WS105are electrically connected to second signal wiring WS201(M2 wiring) through vias V201and V202, respectively, first signal wirings WS104and WS105can be circumvented with second signal wiring WS201which extends in the X-axis direction.

As described above, even when it is difficult to dispose first signal wiring (M1 wiring) which extends in the X-axis direction, a wiring path can be circumvented with second signal wiring (M2 wiring) which extends in the X-axis direction, so that the cell height of the standard logic cell can be reduced while the electrical connection relationship between circuit elements is maintained. Thus, the cell area of the standard logic cell can be reduced.

Second Exemplary Embodiment

FIG. 5illustrates an example of the layout of a standard logic cell which is provided in a semiconductor integrated circuit device according to a second embodiment. The standard logic cell includes a flip-flop as shown inFIG. 6. The standard logic cell includes bent wiring W22in addition to the configuration of the standard logic cell shown inFIG. 1. Bent wiring W22is formed on the same layer on which the plurality of second signal wirings WS2are formed. Here, bent wiring W22is formed on a second metal wiring layer. Bent wiring W22will be described later.

Part of Circuit Configuration of Standard Logic Cell

FIG. 7illustrates circuit region200, which is surrounded by the dotted line, of the circuit configuration of the standard logic cell shown inFIG. 6. Circuit region200includes inverter21, two-input NAND circuit22, and transfer gate23. Inverter21and two-input NAND circuit22are included in a master latch. Inverter21includes PMOS transistor PM21and NMOS transistor NM21. Two-input NAND circuit22includes PMOS transistors PM22, PM23, and PM24and NMOS transistors NM22, NM23, and NM24. Transfer gate23includes PMOS transistor PM25and NMOS transistor NM25. Connection wiring W5electrically connects the drains of PMOS transistors PM22and PM23, which are included in two-input NAND circuit22, with the source of PMOS transistor PM24. Connection wiring W6is electrically connected to the input of transfer gate23(the sources of PMOS transistor PM25and NMOS transistor NM25). Connection wiring W7electrically connects the output of inverter21(the drains of PMOS transistor PM21and NMOS transistor NM21) to the input of two-input NAND circuit22(the gates of PMOS transistor PM23and NMOS transistor NM23).

(Part of Example of Layout of Standard Logic Cell)

FIG. 8illustrates a part of an example of the layout of the standard logic cell which corresponds to the part (circuit region200) of the circuit configuration of the standard logic cell shown inFIG. 7. First signal wirings WS106and WS107correspond to respective connection wirings W5and W6shown inFIG. 7. The combination of first signal wirings WS108and WS109and bent wiring W22corresponds to connection wiring W7shown inFIG. 7.

The drains of PMOS transistor PM21and NMOS transistor NM21(the output of inverter21) are electrically connected to first signal wiring WS109through a contact, and the gates of PMOS transistor PM23and NMOS transistor NM23(the input of two-input NAND circuit22) are electrically connected to first signal wiring WS108through a contact. In this case, since first signal wiring WS108is surrounded by power wiring WP3and two first signal wirings WS106and WS107, it is difficult to dispose new first signal wiring (M1 wiring) which connects first signal wirings WS108and WS109. When each of first signal wirings WS108and WS109is electrically connected to bent wiring W22(M2 wiring) through via V203or V204, first signal wirings WS108and WS109can be circumvented using connection wiring WS22.

Bent wiring W22, which is shown inFIGS. 5 and 8, will be described in detail with reference toFIG. 9. Bent wiring W22includes second signal wirings WS22aand WS22band auxiliary wiring WS22c. Auxiliary wiring WS22cis formed on the same layer on which second signal wirings WS22aand WS22bare formed. In planar view, second signal wirings WS22aand WS22bextend in the X-axis direction (cell width direction), and auxiliary wiring WS22cextends in the Y-axis direction (cell height direction). Auxiliary wiring WS22cconnects second signal wirings WS22aand WS22b. Here, auxiliary wiring WS22cis formed on the second metal wiring layer. Second signal wiring WS22ais disposed between power wirings WP1and WP3, second signal wiring WS22bis disposed between power wirings WP2and WP3, and auxiliary wiring WS22cextends in the Y-axis direction across power wiring WP3in planar view in order to connect second signal wirings WS22aand WS22b. Here, second signal wirings WS22aand WS22bare adjacent to each other while power wiring WP3is interposed therebetween in planar view.

As described above, even when it is difficult to dispose the first signal wiring (M1 wiring) which extends in the X-axis direction and the first signal wiring (M1 wiring) which extends in the Y-axis direction, a wiring path can be circumvented using bent wiring (M2 wiring), so that the cell height of the standard logic cell can be reduced while the electrical relationship between circuit elements are maintained. Therefore, the cell area of the standard logic cell can be reduced.

When the circuit elements, which are formed in the cell area between power wirings WP1and WP3, are electrically connected to the circuit elements which are formed in the cell region between power wirings WP2and WP3(that is, when circuit elements are electrically connected across power wiring WP3), a method of using gate wiring GW (poly-silicon wiring) which extends in the Y-axis direction across power wiring WP3may be considered. However, since such a gate wiring GW is additionally formed, the cell area of the standard logic cell increases. On the other hand, in the standard logic cell shown inFIG. 5, auxiliary wiring WS22cwhich is included in bent wiring W22extends in the Y-axis direction across power wiring WP3, so that the circuit elements can be electrically connected across power wiring WP3. Therefore, since gate wiring GW may not be additionally formed, the cell area of the standard logic cell can be prevented from increasing. Auxiliary wiring WS22cmay not be across power wiring WP3in planar view.

Since second signal wirings WS22aand WS22b, which are included in bent wiring W22, are adjacent to each other while power wiring WP3is interposed therebetween, the deterioration of the degree of freedom of disposition of another second signal wiring (M2 wiring) can be suppressed. It is preferable that the separation distance between second signal wirings WS22aand WS22b, which are included in bent wiring W22, be 2 tracks. With this configuration, the deterioration of the degree of freedom of disposition of another second signal wiring (M2 wiring) can be minimized. Second signal wirings WS22aand WS22b, which are included in bent wiring W22, may be adjacent to each other while power wiring WP3is not interposed therebetween. It is preferable that the separation distance between second signal wirings WS22aand WS22b(the length of auxiliary wiring WS22c) be an interval which does not affect to the disposition of first signal wiring WS1(M1 wiring).

Modification of Second Embodiment

As shown inFIG. 10, the standard logic cell which is provided in the semiconductor integrated circuit device according to the second embodiment may include bent wiring W23instead of bent wiring W22shown inFIG. 5. Other configurations may be the same as those of the standard logic cell shown inFIG. 5.

As shown inFIG. 11, bent wiring W23includes second signal wiring WS23aand auxiliary wiring WS23d. Auxiliary wiring WS23dis integrally formed with second signal wiring WS23aon the same layer of second signal wiring WS23a. In planar view, second signal wiring WS23aextends in the X-axis direction (cell width direction), and auxiliary wiring WS23dextends in the Y-axis direction (cell height direction). Here, auxiliary wiring WS23delectrically connect second signal wiring WS22ato at least one of the plurality of circuit elements (diffusion layer DF and gate wiring GW) and the plurality of first signal wirings WS1. Here, auxiliary wiring WS23dis formed on the second metal wiring layer. Auxiliary wiring WS23dextends in the Y-axis direction across power wiring WP3in planar view. Second signal wiring WS23ais adjacent to power wiring WP3in planar view.

Even in both the case where configuration is made as described above and the case where it is difficult to dispose the first signal wiring (M1 wiring) which extends in the X-axis direction and the first signal wiring (M1 wiring) which extends in the Y-axis direction, the wiring path can be circumvented using the bent wiring (M2 wiring), so that the cell height of the standard logic cell can be reduced while the electrical connection relationship between the circuit elements are maintained. Therefore, the cell area of the standard logic cell can be reduced.

Since auxiliary wiring WS23d, which is included in bent wiring W23, extends in the Y-axis direction across power wiring WP3, the circuit elements can be electrically connected across power wiring WP3. Therefore, since gate wiring GW may not be additionally formed, the cell area of the standard logic cell can be prevented from increasing. Auxiliary wiring WS23dmay not be across power wiring WP3in planar view.

Since second signal wiring WS23a, which is included in bent wiring W23, is adjacent to power wiring WP3, the deterioration of the degree of freedom of disposition of another second signal wiring (M2 wiring) can be suppressed. Second signal wiring WS23a, which is included in bent wiring W23, may not be adjacent to power wiring WP3. The length of auxiliary wiring WS23dmay be an interval which does not affect to the disposition of first signal wiring WS1(M1 wiring).

The standard logic cell, which is provided in the semiconductor integrated-circuit according to the second embodiment, may include both bent wiring W22shown inFIG. 5and bent wiring W23shown inFIG. 10.

Other Embodiment

Although the case where the cell height of the standard logic cell corresponds to 12 tracks has been described as an example in the above-described embodiments for convenience of explanation, the cell height of the standard logic cell may be greater or less than 12 tracks. Although the standard logic cell which has the double height structure has been described as an example, the semiconductor integrated circuit device may be provided with a standard logic cell which has a multi-height structure. The standard logic cell which has the multi-height structure is a standard logic cell which has a cell height n times higher (n is integral number which is equal to or greater than 2) than the cell height of the single height cell. Although the case where a flip-flop is formed in the standard logic cell has been described as an example, the standard logic cell may include another circuit (for example, a latch, a full adder, or the like) other than the flip-flop.

Although description has been made such that power wirings WP1and WP2supply power voltage and power wiring WP3supplies ground voltage, power wirings WP1and WP2may supply ground voltage and power wiring WP3may supply power voltage. Although description has been made such that the separation distance between power wirings WP1and WP3is equal to the separation distance between power wirings WP2and WP3, the separation distance between power wirings WP1and WP3may be different from the separation distance between power wirings WP2and WP3. Although description has been made such that power wirings WP1, WP2, and WP3are formed on the first metal wiring layer, power wirings WP1, WP2, and WP3may be formed on another wiring layer (for example, the second metal wiring layer).

Although description has been made such that each of the plurality of second signal wirings WS2is disposed to overlap with anyone of the wiring tracks in planar view (that is, each of the plurality of second signal wiring WS2is formed to be separated at a regular interval in the Y-axis direction in planar view), each of the plurality of second signal wiring WS2may not be separated at a regular interval in the Y-axis direction in planar view. A plurality of second signal wirings WS2may be included in the standard logic cell, and a single second signal wiring WS2may be included in the standard logic cell.

As described above, the above-described semiconductor integrated circuit device can reduce the cell height of the standard logic cell, so that the semiconductor integrated circuit device can be used as a semiconductor integrated circuit device which includes a standard logic cell, such as a flip-flop.