Semiconductor structure and manufacturing method thereof

A semiconductor structure includes a substrate; an interconnect structure formed over the substrate and including a dielectric layer over the substrate, a first conductive member formed within the dielectric layer and a second conductive member formed within the dielectric layer; a waveguide formed between the first conductive member and the second conductive member; a first die disposed over the interconnect structure and electrically connected to the first conductive member; and a second die disposed over the interconnect structure and electrically connected to the second conductive member, wherein the waveguide is coupled with the first conductive member and the second conductive member.

BACKGROUND

Electronic equipments using semiconductor devices are essential for many modern applications. With the advancement of electronic technology, the semiconductor devices are becoming increasingly smaller in size while having greater functionality and greater amounts of integrated circuitry. Due to the miniaturized scale of the semiconductor device, a chip on wafer on substrate (CoWoS) is widely used to integrate several chips into a single semiconductor device by through substrate via (TSV). During the CoWoS operation, a number of chips are assembled on a single semiconductor device. Furthermore, numerous manufacturing operations are implemented within such a small semiconductor device.

However, the manufacturing operations of the semiconductor device involve many steps and operations on such a small and thin semiconductor device. The manufacturing of the semiconductor device in a miniaturized scale becomes more complicated. An increase in a complexity of manufacturing the semiconductor device may cause deficiencies such as poor structural configuration, delamination of components, or other issues, resulting in a high yield loss of the semiconductor device and increase of manufacturing cost. As such, there are many challenges for modifying a structure of the semiconductor devices and improving the manufacturing operations.

DETAILED DESCRIPTION OF THE DISCLOSURE

In this document, the term “coupled” may also be termed as “electrically coupled”, and the term “connected” may be termed as “electrically connected”. “Coupled” and “connected” may also be used to indicate that two or more elements cooperate or interact with each other.

An electronic device including various semiconductor chips is manufactured by a number of operations. During the manufacturing process, the semiconductor chips with different functionalities and dimensions are integrated into a single module. Circuitries of the semiconductor chips are integrated and connected through conductive traces. The semiconductor chips communicate with each other by transmitting an electrical signal from one device to another device through the conductive traces. However, such transmission between the semiconductor chips may not satisfy a high demand of communication between the semiconductor chips. As a result, performance of the electronic device may not be at a desired level.

In the present disclosure, a semiconductor structure is disclosed. The semiconductor structure includes a substrate, an interconnect structure disposed or deposited over the substrate and including a dielectric layer over the substrate, a first conductive member disposed within the dielectric layer and a second conductive member disposed or formed within the dielectric layer, a waveguide disposed or fabricated within the dielectric layer, a first die disposed over the interconnect structure and electrically connected to the first conductive member, a second die disposed over the interconnect structure and electrically connected to the second conductive member, wherein the waveguide is coupled with the first conductive member and the second conductive member.

An electrical signal is transmitted from the first die to the first conductive member, and the electrical signal is converted to an electromagnetic signal. The electromagnetic signal is transmitted from the first conductive member to the second conductive member within the waveguide. When the electromagnetic signal is received by the second conductive member, the electromagnetic signal is converted to an electrical signal. The electrical signal is then transmitted from the second conductive member to the second die. The electromagnetic signal is in non-visible (e.g. radio wave, microwave, etc.) spectrum and transmitted in a high frequency (e.g. substantially greater than 10 GHz) along the waveguide, an energy loss of transmission of the electromagnetic signal by the waveguide can be minimized.

FIG. 1is a schematic cross sectional view of a semiconductor structure100in accordance with various embodiments of the present disclosure. In some embodiments, the semiconductor structure100includes a substrate101, an interconnect structure102, a waveguide103, a first die104and a second die105.

In some embodiments, the semiconductor structure100is a semiconductor package. In some embodiments, the semiconductor structure100is an integrated fan out (InFO) package, where I/O terminals of the first die104or the second die105are fanned out and redistributed over a surface of the first die104or the second die105in a greater area. In some embodiments, the semiconductor structure100is a chip on wafer on substrate (CoWoS) packaging structure. In some embodiments, the semiconductor structure100is a three dimensional integrated circuit (3D IC). In some embodiments, the semiconductor structure100is configured to perform an ultra-high speed signal transmission (e.g. transmission speed substantially greater than 10 Gigabyte per second (Gb/s)) within the semiconductor structure100in a high frequency (e.g. a frequency substantially greater than about 10 Giga Hertz (GHz)).

In some embodiments, the substrate101is a semiconductive substrate. In some embodiments, the substrate101includes semiconductive material such as silicon, germanium, gallium, arsenic, or combinations thereof. In some embodiments, the substrate101is an interposer or the like. In some embodiments, the substrate101is a silicon substrate or silicon interposer. In some embodiments, the substrate101includes material such as ceramic, glass, polymer or the like. In some embodiments, the substrate101includes organic material. In some embodiments, the substrate101has a quadrilateral, rectangular, square, polygonal or any other suitable shape.

In some embodiments, the substrate101includes a first surface101aand a second surface101bopposite to the first surface101a. In some embodiments, there is a via101cin the substrate101extended through at least a portion of the substrate101. In some embodiments, the via101cis extended between the first surface101aand the second surface101b. In some embodiments, the via101cincludes a conductive material such as copper, silver, gold, aluminum, etc. In some embodiments, the via101cis a through silicon via (TSV).

In some embodiments, a first pad101dis disposed over and electrically connected to the via101c. In some embodiments, the first pad101dis disposed over the second surface101bof the substrate101. In some embodiments, the first pad101dincludes metal or metal alloy. In some embodiments, the first pad101dincludes chromium, copper, gold, titanium, silver, nickel, palladium or tungsten, etc. In some embodiments, the first pad101dis a solderable surface and serves as a platform for receiving a solder material and for electrically connecting a circuitry of the substrate101with an external component or external circuitry.

In some embodiments, a first conductive bump101eis disposed or fabricated over the substrate101. In some embodiments, the first conductive bump101eis fabricated over the second surface101bof the substrate101. In some embodiments, the first conductive bump101eis fabricated over and electrically connected to the first pad101d. In some embodiments, the first conductive bump101eis electrically connected to the via101c. In some embodiments, the first conductive bump101eis in a cylindrical, spherical or hemispherical shape. In some embodiments, the first conductive bump101eis a solder joint, a solder bump, a solder ball, a ball grid array (BGA) ball, a controlled collapse chip connection (C4) bump or the like. In some embodiments, the first conductive bump101eis a conductive pillar or post. In some embodiments, the first conductive bump101eincludes metals such as lead, tin, copper, gold, nickel, etc.

In some embodiments, the interconnect structure102is disposed or deposited over the substrate101. In some embodiments, the interconnect structure102is deposited over the first surface101aof the substrate101. In some embodiments, the interconnect structure102includes a dielectric layer102adeposited over the substrate101, several conductive members102bdisposed or formed within the dielectric layer102a, and several conductive vias102cdisposed or formed within the dielectric layer102a.

In some embodiments, the dielectric layer102aincludes one or more dielectric layers. In some embodiments, the dielectric layer102aincludes silicon dioxide, fluorine-doped silicon dioxide, carbon-doped silicon dioxide, porous silicon dioxide, a dielectric material having a low dielectric constant (Low K), a dielectric material having an ultra-low dielectric constant (ULK), a dielectric material having a dielectric constant substantially less than a dielectric constant of silicon dioxide, a dielectric material having a dielectric constant substantially less than 4.

In some embodiments, the conductive members102band the conductive vias102care configured to electrically connect to the via101cor the first conductive bump101e. In some embodiments, the conductive members102band the conductive vias102care electrically connected to a circuitry disposed over or within the substrate101. In some embodiments, the conductive member102bis electrically coupled with the conductive via102c. In some embodiments, the conductive members102bare laterally extended within the dielectric layer102a, and the conductive vias102care vertically extended within the dielectric layer102a. In some embodiments, the conductive members102band the conductive vias102cinclude conductive material such as gold, silver, copper, nickel, tungsten, aluminum, tin and/or alloys thereof.

In some embodiments, the conductive members102bincludes a first conductive member102b-1and a second conductive member102b-2. In some embodiments, the first conductive member102b-1and the second conductive member102b-2are formed or disposed within the dielectric layer102a. In some embodiments, the first conductive member102b-1and the second conductive member102b-2are formed adjacent to each other. In some embodiments, a dielectric is between the first conductive member102b-1and the second conductive member102b-2. In some embodiments, the first conductive member102b-1is horizontally aligned with the second conductive member102b-2. In some embodiments, the first conductive member102b-1and the second conductive member102b-2are electrically connected to corresponding conductive vias102c. In some embodiments, the via101cis electrically connected to the first conductive member102b-1, the second conductive member102b-2, the third conducive member102b-3or the fourth conductive member102b-4.

In some embodiments, the first conductive member102b-1is configured to convert an electrical signal to an electromagnetic signal. In some embodiments, the first conductive member102b-1is configured to transmit the electromagnetic signal to the second conductive member102b-2. In some embodiments, the second conductive member102b-2is configured to receive the electromagnetic signal from the first conductive member102b-1. In some embodiments, the second conductive member102b-2is configured to convert the electromagnetic signal to an electrical signal. In some embodiments, the first conductive member102b-1is a first transmission electrode, and the second conductive member102b-2is a first receiving electrode. In some embodiments, the electromagnetic signal is non-visible radiation such as microwave, radio wave, etc. In some embodiments, the electromagnetic signal is not a visible light.

In some embodiments, the conductive members102bincludes a third conductive member102b-3and a fourth conductive member102b-4. In some embodiments, the third conductive member102b-3and the fourth conductive member102b-4are disposed or formed within the dielectric layer102a. In some embodiments, the third conductive member102b-3and the fourth conductive member102b-4are formed adjacent to each other. In some embodiments, the third conductive member102b-3is horizontally aligned with the fourth conductive member102b-4. In some embodiments, the third conductive member102b-3and the fourth conductive member102b-4are electrically connected to corresponding conductive vias102c.

In some embodiments, the third conductive member102b-3is disposed opposite to the first conductive member102b-1, and the fourth conductive member102b-4is disposed opposite to the second conductive member102b-2. In some embodiments, the first conductive member102b-1and the third conductive member102b-3are operable in pairs, and the second conductive member102b-2and the fourth conductive member102b-4are operable in pairs.

In some embodiments, the third conductive member102b-3is configured to convert an electrical signal to an electromagnetic signal and transmit the electromagnetic signal to the second conductive member102b-2or the fourth conductive member102b-4. In some embodiments, the fourth conductive member102b-4is configured to receive the electromagnetic signal from the first conductive member102b-1or the third conductive member102b-3and convert the electromagnetic signal to an electrical signal. In some embodiments, the third conductive member102b-3is a second transmission electrode, and, the fourth conductive member102b-4is a second receiving electrode. In some embodiments, the second transmission electrode is disposed opposite to the first transmission electrode, and the second receiving electrode is disposed opposite to the first receiving electrode. In some embodiments, the first conductive member102b-1has configuration similar to the third conductive member102b-3, and the second conductive member102b-2has configuration similar to the fourth conductive member102b-4.

In some embodiments, the waveguide103is disposed within the dielectric layer102aof the interconnect structure102. In some embodiments, the waveguide103is disposed between two of the conductive members102b. In some embodiments, the waveguide103is disposed between the first conductive member102b-1and the second conductive member102b-2or between the third conductive member102b-3and the fourth conductive member102b-4. In some embodiments, the waveguide103is coupled with the first conductive member102b-1and the second conductive member102b-2. In some embodiments, the waveguide103is coupled with the third conductive member102b-3and the fourth conductive member102b-4. In some embodiments, the waveguide103is laterally extended within the dielectric layer102a. In some embodiments, a height of the waveguide103is about 1 μm. In some embodiments, a width of the waveguide103is about 1 μm. In some embodiments, the width of the waveguide103is about 10 times of the height of the waveguide103.

In some embodiments, the waveguide103includes a first end103aand a second end103bopposite to the first end103a. In some embodiments, the first end103ais coupled with the first conductive member102b-1or the third conductive member102b-3, and the second end103bis coupled with the second conductive member102b-2or the fourth conductive member102b-4. In some embodiments, the first end103ais surrounded by the first conductive member102b-1and the third conductive member102b-3, and the second end103bis surrounded by the second conductive member102b-2and the fourth conductive member102b-4.

In some embodiments, the waveguide103is dielectric and configured to transmit an electromagnetic signal from one of the conductive members102bto another one of the conductive members102b. In some embodiments, the electromagnetic signal is transmitted within the waveguide103. In some embodiments, the waveguide103is configured to transmit an electromagnetic signal from the first conductive member102b-1to the second conductive member102b-2within the waveguide103or from the third conductive member102b-3to the fourth conductive member102b-4. In some embodiments, the electromagnetic signal is non-visible radiation such as microwave, radio wave, etc. In some embodiments, the electromagnetic signal is not a visible light.

In some embodiments, an electrical signal from the first conductive member102b-1is converted to an electromagnetic signal, and the electromagnetic signal is transmitted within the waveguide103from the first conductive member102b-1to the second conductive member102b-2, and the electromagnetic signal is converted to an electrical signal at the second conductive member102b-2. As such the electrical signal is transmitted from the first conductive member102b-1to the second conductive member102b-2through the waveguide103. In some embodiments, the waveguide103is configured to transmit the electromagnetic signal in a frequency of greater than 10 Giga Hertz (GHz). In some embodiments, a transmission speed of the electromagnetic signal is substantially greater than 10 Gigabytes per second (Gb/s).

In some embodiments, a dielectric constant of the waveguide103is substantially greater than the dielectric constant of the dielectric layer102a. Since the dielectric constant of the waveguide103is substantially greater than the dielectric constant of the dielectric layer102a, the waveguide103causes the electromagnetic signal entered into the waveguide103to be reflected within the waveguide103by total internal reflection, such that the electromagnetic signal can be transmitted from the first end103ato the second end of the waveguide103or from the first conductive member102b-1to the second conductive member102b-2.

In some embodiments, the dielectric constant of the waveguide103is substantially greater than a dielectric constant of silicon dioxide. In some embodiments, the dielectric constant of the waveguide103is substantially greater than 4. In some embodiments, the dielectric constant of the waveguide103is substantially greater than 7. In some embodiments, the dielectric constant of the waveguide103is substantially greater than 13. In some embodiments, the dielectric constant of the waveguide103is substantially greater than 100. In some embodiments, the dielectric constant of the waveguide103is substantially greater than 200. In some embodiments, the dielectric constant of the waveguide103is substantially greater than 500.

In some embodiments, the waveguide103includes silicon nitride or silicon carbide. In some other embodiments, the waveguide103includes low-temperature (e.g., 180° C.) silicon dioxide (CVD-SiO2), silicon nitride (SiNx) or silicon oxynitride (SiOxNy) deposited by any suitable depositions such as chemical vapor deposition (CVD), plasma enhanced CVD (PECVD), sub-atmospheric CVD (SACVD), atmospheric pressure CVD (APCVD), metal organic CVD (MOCVD), laser CVD (LCVD), etc. In some embodiments, the waveguide103includes low-temperature (e.g., <240° C.) titanium dioxide (TiO2) deposited by LCVD, electron beam (e.g. electronic gun) evaporation or etc. In some embodiments, the waveguide103includes low-temperature (e.g., 210° C.) high-k dielectric material such as zirconium dioxide (ZrO2), aluminum oxide (Al2O3), hafnium oxide (HfOx), Hafnium silicate (HfSiOx), zirconium titanate (ZrTiOx), tantalum oxide (TaOx), etc. In some embodiments, the waveguide103includes strontium titanate (SrTiO3 having dielectric constant (k) of about 83 to about 100) or barium titanate (BaTiO3 having dielectric constant (k) of about 500).

In some embodiments, the first die104is disposed over the interconnect structure102. In some embodiments, the first die104is disposed over the first conductive member102b-1or the third conductive member102b-3. In some embodiments, the first die104is fabricated with a predetermined functional circuit within the first die104. In some embodiments, the first die104is singulated from a semiconductive wafer by a mechanical or laser blade. In some embodiments, the first die104comprises a variety of electrical circuits suitable for a particular application. In some embodiments, the electrical circuits include various devices such as transistors, capacitors, resistors, diodes and/or the like. In some embodiments, the first die104is a logic device die, central processing unit (CPU) die, graphics processing unit (GPU) die, mobile phone application processing (AP) die or the like. In some embodiments, the first die104is a system on chip (SoC) that integrates all electronic components into a single die. In some embodiments, the first die104is a die, a chip or a package. In some embodiments, the first die104has a top cross section (a cross section from the top view of the semiconductor structure100as shown inFIG. 1) in a quadrilateral, a rectangular or a square shape.

In some embodiments, the first die104is a transmission die or a driver die. In some embodiments, the first die104includes a transmission circuit or a transmitter. In some embodiments, the transmission circuit of the first die104is configured to generate an electrical signal. In some embodiments, the first die104is electrically connected to the first conductive member102b-1or the third conductive member102b-3. In some embodiments, the electrical signal is transmitted from the first die104to the first conductive member102b-1or the third conductive member102b-3.

In some embodiments, the first die104is electrically connected to the first conductive member102b-1or the third conductive member102b-3through a redistribution layer (RDL)106and a second conductive bump107. In some embodiments, the RDL106is disposed or formed over the interconnect structure102. In some embodiments, the RDL106is configured to re-route a path of circuitry from the first die104to the conductive members102, so as to redistribute I/O terminals of the first die104.

In some embodiments, the RDL106includes a second dielectric layer106aand a second pad106b. In some embodiments, the second dielectric layer106ais disposed or deposited over the dielectric layer102a. In some embodiments, the second pad106bis partially exposed from the second dielectric layer106a. In some embodiments, the second pad106bis electrically connected to the conductive via102cor the conductive member102b. In some embodiments, the second pad106bis extended into the dielectric layer102a. In some embodiments, a portion of the second pad106bis surrounded by the dielectric layer102a. In some embodiments, the second dielectric layer106aincludes dielectric material such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride or the like. In some embodiments, the second pad106bincludes conductive material such as gold, silver, copper, nickel, tungsten, aluminum, palladium and/or alloys thereof.

In some embodiments, the second conductive bump107is disposed or fabricated between the interconnect structure102and the first die104. In some embodiments, the second conductive bump107is disposed between the RDL106and the first die104. In some embodiments, the first die104is electrically connected to the conductive member102or the second pad106bby the second conductive bump107. In some embodiments, the second conductive bump107is in a cylindrical, spherical or hemispherical shape. In some embodiments, the second conductive bump107is a solder joint, a solder bump, a solder ball, a ball grid array (BGA) ball, a controlled collapse chip connection (C4) bump or the like. In some embodiments, the second conductive bump107is a conductive pillar or post. In some embodiments, the second conductive bump107includes metals such as lead, tin, copper, gold, nickel, etc.

In some embodiments, the second die105is disposed over the interconnect structure102. In some embodiments, the second die105is disposed adjacent to the first die104. In some embodiments, the second die105is disposed over the second conductive member102b-2or the fourth conductive member102b-4. In some embodiments, the second die105is fabricated with a predetermined functional circuit within the second die105. In some embodiments, the second die105is singulated from a semiconductive wafer by a mechanical or laser blade. In some embodiments, the second die105comprises a variety of electrical circuits suitable for a particular application. In some embodiments, the electrical circuits include various devices such as transistors, capacitors, resistors, diodes and/or the like. In some embodiments, the second die105is a high bandwidth memory (HBM) die. In some embodiments, the second die105is a die, a chip or a package. In some embodiments, the second die105has a top cross section (a cross section from the top view of the semiconductor structure100as shown inFIG. 1) in a quadrilateral, a rectangular or a square shape.

In some embodiments, the second die105is a receiving die or a receiver die. In some embodiments, the second die105includes a receiving circuit or a receiver. In some embodiments, the receiving circuit of the second die105is configured to receive the electrical signal. In some embodiments, the second die105is electrically connected to the second conductive member102b-2or the fourth conductive member102b-4. In some embodiments, the electrical signal generated from the first die104is converted to an electromagnetic signal, and the electromagnetic signal is transmitted from the first die104within the waveguide103to the second conductive member102b-2or the fourth conductive member102b-4, and the electromagnetic signal is converted to an electrical signal received by the second die105, such that the electrical signal from the first die104is transmitted to the second die105through the waveguide103.

In some embodiments, the second die105is electrically connected to the second conductive member102b-2or the fourth conductive member102b-4through the redistribution layer (RDL)106and the second conductive bump107. In some embodiments, the second die105is electrically connected to the second pad106bof the RDL106through the second conductive bump107. In some embodiments, the second conductive bump107is disposed between the interconnect structure102and the second die105. In some embodiments, the second conductive bump107is disposed between the RDL106and the second die105. In some embodiments, the second die105is disposed over the second conductive member102b-2.

In some embodiments, an underfill material108is disposed or dispensed over the RDL106, the interconnect structure102and the substrate101. In some embodiments, the underfill material108surrounds the second conductive bump107. In some embodiments, the underfill material108fills spacing between two adjacent second conductive bumps107. In some embodiments, a sidewall of the first die104or a sidewall of the second die105is in contact with the underfill material108. In some embodiments, the underfill material108is an electrically insulated adhesive for protecting the second conductive bump107or securing a bonding between the first die104and the RDL106or the second die105and the RDL106. In some embodiments, the underfill material108includes epoxy, resin, epoxy molding compounds or etc.

In some embodiments, a molding109is disposed over the RDL106, the interconnect structure102and the substrate101. In some embodiments, the molding109surrounds the first die104and the second die105. In some embodiments, the molding109covers the underfill material108. In some embodiments, a portion of the molding109is disposed between the first die104and the second die105. In some embodiments, the portion of the molding109is disposed over the waveguide103. In some embodiments, a surface of the first die104or a surface of the second die105is exposed from the molding109. In some embodiments, the molding109is in contact with the sidewall of the first die104or the sidewall of the second die105. In some embodiments, the molding109can be a single layer film or a composite stack. In some embodiments, the molding109includes various materials, such as molding compound, molding underfill, epoxy, resin, or the like. In some embodiments, the molding109has a high thermal conductivity, a low moisture absorption rate and a high flexural strength.

FIG. 2is a schematic cross sectional view of semiconductor structure200in accordance with various embodiments of the present disclosure. In some embodiments, the semiconductor structure200includes a substrate101, an interconnect structure102, a waveguide103, a first die104and a second die105, which have similar configurations as those described above or illustrated inFIG. 1. In some embodiments, the via101cis surrounded by the dielectric layer102a. In some embodiments, the dielectric layer102ais disposed or deposited between the via101cand the substrate101.

In some embodiments, the semiconductor structure200includes a second substrate201and a bond pad201adisposed or formed over the second substrate201. In some embodiments, the substrate101is disposed over the second substrate201. In some embodiments, the first conductive bump101eis disposed or fabricated over the bond pad201a. In some embodiments, the bond pad201ais electrically coupled with the first conductive bump101e. In some embodiments, the first die104and the second die105are electrically connected to the second substrate201through the first conductive bump101e.

In some embodiments, the second substrate201is fabricated with a predetermined functional circuit thereon. In some embodiments, the second substrate201includes several conductive traces and several electrical components such as transistor, diode, etc. disposed within the second substrate201. In some embodiments, the second substrate201includes semiconductive materials such as silicon. In some embodiments, the second substrate201is a silicon substrate. In some embodiments, the second substrate201is a printed circuit board (PCB). In some embodiments, the bond pad201aincludes conductive material such as gold, silver, copper, nickel, tungsten, aluminum, palladium and/or alloys thereof.

FIG. 3is a schematic diagram of the semiconductor structure100in accordance with some embodiments of the present disclosure. In some embodiments, the semiconductor structure100includes a transmission circuit301and a receiving circuit305. In some embodiments, the transmission circuit301is disposed in the first die104, and the receiving circuit305is disposed in the second die105.

In some embodiments, the transmission circuit301is a driver circuit. In some embodiments, the transmission circuit301includes a first source S1, a first drain al and a first gate G1. In some embodiments, the first source S1is electrically grounded. In some embodiments, the transmission circuit301is configured to receive an input signal IN to the first gate G1, output an electrical signal from the first drain D1to a transmission coupling element303athrough a transmission line302. In some embodiments, the transmission coupling element303ais disposed over or in the first conductive member102b-1or the third conductive member102b-3. In some embodiments, the transmission coupling element303aincludes a first transmission coupling element303a-1and a second transmission coupling element303a-2. In some embodiments, the transmission coupling element303aincludes conductive material such as gold, silver, copper, nickel, tungsten, aluminum, palladium and/or alloys thereof. In some embodiments, the first transmission coupling element303a-1and the second transmission coupling element303a-2are disposed opposite to each other. In some embodiments, the second transmission coupling element303a-2is electrically grounded. In some embodiments, the first end103aof the waveguide103is surrounded by the transmission coupling element303a. In some embodiments, the electrical signal from the transmission line302to the first transmission coupling element303a-1generates an electromagnetic signal corresponding to the electrical signal, and the electromagnetic signal is transmitted from the first end103ato the second end103bof the waveguide103.

In some embodiments, the receiving circuit305is a receiver circuit. In some embodiments, the receiving circuit305includes a second source S2, a second drain D2and a second gate G2. In some embodiments, the second source S2is electrically grounded. In some embodiments, the receiving circuit305is configured to receive the electrical signal from a receiving coupling element303bto the second gate G2and output an output signal OUT from the second drain D2. In some embodiments, the receiving coupling element303ais disposed over or in the second conductive member102b-2or the fourth conductive member102b-4. In some embodiments, the receiving coupling element303bincludes a first receiving coupling element303b-1and a second receiving coupling element303b-2. In some embodiments, the receiving coupling element303bincludes conductive material such as gold, silver, copper, nickel, tungsten, aluminum, palladium and/or alloys thereof. In some embodiments, the first receiving coupling element303b-1and the second receiving coupling element303b-2are disposed opposite to each other. In some embodiments, the second receiving coupling element303b-2is electrically grounded. In some embodiments, the second end103bof the waveguide103is surrounded by the receiving coupling element303b. In some embodiments, the electromagnetic signal from the waveguide103is converted to an electrical signal at the receiving coupling element303b, and the electrical signal is transmitted through the receiving line304to the second gate G2.

In the present disclosure, a method of manufacturing a semiconductor structure (100or200) is also disclosed. In some embodiments, the semiconductor structure (100or200) is formed by a method400. The method400includes a number of operations and the description and illustration are not deemed as a limitation as the sequence of the operations.FIG. 4is an embodiment of the method400of manufacturing the semiconductor structure (100or200). The method400includes a number of operations (401,402,403,404,405,406and407).

In operation401, a substrate101is provided or received as shown inFIGS. 4A and 4B. In some embodiments, the substrate101is a semiconductive substrate. In some embodiments, the substrate101is a silicon substrate or silicon interposer. In some embodiments, the substrate101includes a first surface101aand a second surface101bopposite to the first surface101a. In some embodiments, the substrate101has configuration similar to the one described above or illustrated inFIG. 1 or 2.

In some embodiments, a via101cextended through at least a portion of the substrate101is formed. In some embodiments, the via101cis extended between the first surface101aand the second surface101b. In some embodiments, the via101cis a through silicon via (TSV). In some embodiments, the via101cis formed by removing a portion of the substrate101to form a first recess110as shown inFIG. 4Aand forming a conductive material into the first recess110to form the via101cas shown inFIG. 4B. In some embodiments, the removal of the portion of the substrate101includes photolithography, etching or any other suitable operations. In some embodiments, the formation of the conductive material includes sputtering, electroplating or any other suitable operations. In some embodiments, the via101chas configuration similar to the one described above or illustrated inFIG. 1 or 2. In some embodiments, a dielectric material is deposited over the substrate101and along a sidewall of the first recess110before the formation of the conductive material into the first recess110. In some embodiments, the dielectric material surrounds the via101c. In some embodiments, the dielectric material is deposited between the via101cand the substrate101.

In operation402, a first layer of a dielectric layer102ais deposited over the substrate101as shown inFIG. 4C. In some embodiments, the first layer of the dielectric layer102ais a low dielectric constant electrical isolation layer. In some embodiments, the first layer of the dielectric layer102aincludes silicon dioxide, fluorine-doped silicon dioxide, carbon-doped silicon dioxide, porous silicon dioxide, a dielectric material having a low dielectric constant (Low K), a dielectric material having an ultra-low dielectric constant (ULK), a dielectric material having a dielectric constant substantially less than a dielectric constant of silicon dioxide, a dielectric material having a dielectric constant substantially less than 4. In some embodiments, the dielectric layer102ais deposited by spin coating, chemical vapor deposition (CVD), plasma-enhanced CVD (PECVD), high-density plasma CVD (HDPCVD) or any other suitable operations.

In some embodiments, some conductive members102band some conductive vias102care formed after the deposition of the first layer of the dielectric layer102a. In some embodiment, some conductive members102band some conductive vias102care formed within the first layer of the dielectric layer102a. In some embodiments, some conductive members102bincluding a third conductive member102b-3and a fourth conductive member102b-4are formed. In some embodiments, some conductive members102bare formed by removing a portion of the first layer of the dielectric layer102aand disposing a conductive material. In some embodiments, the removal of the portion of the dielectric layer102aincludes photolithography, etching or any other suitable operations. In some embodiments, the formation of the conductive material includes sputtering, electroplating or any other suitable operations. In some embodiments, the conductive member102bhas configuration similar to the one described above or illustrated inFIG. 1 or 2.

In some embodiments, some conductive vias102care formed within the first layer of the dielectric layer102a. In some embodiments, the conductive via102cis formed removing a portion of the dielectric layer102aand forming a conductive material. In some embodiments, the removal of the first layer of the portion of the dielectric layer102aincludes photolithography, etching or any other suitable operations. In some embodiments, the forming of the conductive material includes sputtering, electroplating or any other suitable operations. In some embodiments, the conductive via102chas configuration similar to the one described above or illustrated inFIG. 1 or 2. In some embodiments, some conductive members102band some conductive vias102care formed separately or simultaneously.

In operation403, a waveguide103is formed within the dielectric layer102aas shown inFIGS. 4D-4H. In some embodiments, the waveguide103is formed over some conductive members102bor some conductive vias102c. In some embodiments, the waveguide103is deposited over the third conductive member102b-3and the fourth conductive member102b-4. In some embodiments, the waveguide103is formed between the third conductive member102b-3and the fourth conductive member102b-4. In some embodiments, the waveguide103is coupled with the third conductive member102b-3and the fourth conductive member102b-4.

In some embodiments, the waveguide103is formed by depositing a waveguide material103cover the first layer of the dielectric layer102aas shown inFIG. 4D, coating and pattern defining photoresist103dover the waveguide material103cas shown inFIG. 4E, and removing a portion of the waveguide material103cexposed from the photoresist103dto form the waveguide103as shown inFIG. 4F. In some embodiments, the photoresist103dis removed after the formation of the waveguide103as shown inFIG. 4G. In some embodiments, the portion of the waveguide material103cexposed from the photoresist103dis removed by wet etching, plasma etching or any other suitable operations. In some embodiments, the waveguide material103chas a dielectric constant substantially greater than a dielectric constant of the dielectric layer102a. In some embodiments, the disposing of the waveguide material103cincludes spin coating, chemical vapor deposition (CVD), plasma-enhanced CVD (PECVD), high-density plasma CVD (HDPCVD), sub-atmospheric CVD (SACVD), atmospheric pressure CVD (APCVD), metal organic CVD (MOCVD), laser CVD (LCVD), electron beam (e.g. electronic gun) evaporation or any other suitable operations. In some embodiments, the photoresist103dis removed by etching, stripping or any other suitable operations. In some embodiments, a second layer of the dielectric layer102ais deposited over the substrate101to surround the waveguide103as shown inFIG. 4H. In some embodiments, the second layer of the dielectric layer102ais deposited to cover the waveguide103, and then thinning down to expose the waveguide103by planarization, chemical mechanical polish (CMP) or any other suitable operations. In some embodiments, the second layer of the dielectric layer102ais similar to the first layer of the dielectric layer102a. In some embodiments, the waveguide103has configuration similar to the one described above or illustrated inFIG. 1, 2 or 3.

In operation404, a first conductive member102b-1or a second conductive member102b-2is formed within the dielectric layer102aas shown inFIG. 4I. In some embodiments, some conductive members102bincluding a first conductive member102b-1and a second conductive member102b-2are formed. In some embodiments, the waveguide103is formed after the formation of the third conductive member102b-3and the fourth conductive member102b-4but before the formation of a first conductive member102b-1and a second conductive member102b-2. In some embodiments, the waveguide103is formed between the first conductive member102b-1and the second conductive member102b-2. In some embodiments, the waveguide103is coupled with the first conductive member102b-1and the second conductive member102b-2.

In some embodiments, the first conductive member102b-1or the second conductive member102b-2is formed by removing a portion of the second layer of the dielectric layer102aand forming a conductive material. In some embodiments, the removal of the portion of the second layer of the dielectric layer102aincludes photolithography, etching or any other suitable operations. In some embodiments, the disposing of the conductive material includes sputtering, electroplating or any other suitable operations. In some embodiments, the first conductive member102b-1and the second conductive member102b-2have configuration similar to the one described above or illustrated inFIG. 1 or 2. In some embodiments, an interconnect structure102including the dielectric layer102a, the conductive member102band the conductive via102cis formed over the substrate101. In some embodiments, the waveguide103is disposed within the interconnect structure102. In some embodiments, some conductive members102bor some conductive vias102care formed after the formation of the waveguide103.

In some embodiments, a RDL106is formed over the interconnect structure102as shown inFIG. 4Jafter the formation of the waveguide103. In some embodiments, the RDL106including a second dielectric layer106aand a second pad106bis formed. In some embodiments, the second pad106bis formed over and electrically connected to the conductive member102b. In some embodiments, the second pad106bis formed by disposing a conductive material over the dielectric layer102aand the conductive member102b. In some embodiments, the second pad106bis formed by sputtering, electroplating or any other suitable operations.

In some embodiments, the second dielectric layer106ais disposed over the dielectric layer102a. In some embodiments, the second dielectric layer106ais deposited by spin coating, chemical vapor deposition (CVD), plasma-enhanced CVD (PECVD), high-density plasma CVD (HDPCVD) or any other suitable operations. In some embodiments, some portions of the second dielectric layer106aare removed to at least partially expose the second pad106b. In some embodiments, some portions of the second dielectric layer106aare removed by photolithography, etching or any other suitable operations. In some embodiments, the second dielectric layer106aand the second pad106bhave configuration similar to the one described above or illustrated inFIG. 1 or 2.

In some embodiments, a second conductive bump107is fabricated over the second pad106bas shown inFIG. 4J. In some embodiments, the second conductive bump107is bonded with the second pad106. In some embodiments, the second conductive bump107is fabricated by ball dropping, solder pasting, stencil printing or any other suitable operations. In some embodiments, the second conductive bump107is reflowed after the formation.

In operation405, a first die104is disposed over the dielectric layer102aas shown inFIG. 4K. In some embodiments, the first die104is bonded over the substrate101. In some embodiments, the first die104is a logic device die, central processing unit (CPU) die, graphics processing unit (GPU) die, mobile phone application processing (AP) die or the like. In some embodiments, the first die104is a system on chip (SoC) that integrates all electronic components into a single die. In some embodiments, the first die104is a transmission die or a driver die. In some embodiments, the first die104includes a transmission circuit or a transmitter. In some embodiments, the transmission circuit of the first die104is configured to generate an electrical signal. In some embodiments, the first die104is electrically connected to the first conductive member102b-1or the third conductive member102b-3. In some embodiments, the electrical signal is transmitted from the first die104to the first conductive member102b-1or the third conductive member102b-3. In some embodiments, the first die104has configuration similar to the one described above or illustrated inFIG. 1 or 2.

In some embodiments, the first die104is electrically connected to the conductive member102bor the conductive via102cthrough the second conductive bump107. In some embodiments, the second conductive bump107is disposed between the first die104and the dielectric layer102ato electrically connect the first die104to the first conductive member102b-1or the third conductive member102b-3. In some embodiments, the second conductive bump107is bonded with the second pad106b, such that the first die104is electrically connected to the via101c, the conductive member102bor the conductive via102c. In some embodiments, the electrical signal from the first die104is transmitted to the first conductive member102b-1or the third conductive member102b-3through the second conductive bump107.

In operation406, a second die105is disposed over the dielectric layer102aas shown inFIG. 4K. In some embodiments, the second die105is disposed adjacent to the first die104. In some embodiments, the second die105is bonded over the substrate101. In some embodiments, the second die105is a high bandwidth memory (HBM) die. In some embodiments, the second die105is a receiving die or a receiver die. In some embodiments, the second die105includes a receiving circuit or a receiver. In some embodiments, the receiving circuit of the second die105is configured to receive the electrical signal. In some embodiments, the second die105is electrically connected to the second conductive member102b-2or the fourth conductive member102b-4. In some embodiments, the electrical signal generated from the first die104is converted to an electromagnetic signal, and the electromagnetic signal is transmitted from the first die104within the waveguide103to the second conductive member102b-2or the fourth conductive member102b-4, and the electromagnetic signal is converted to an electrical signal received by the second die105, such that the electrical signal from the first die104is transmitted to the second die105through the waveguide103. In some embodiments, the second die105has configuration similar to the one described above or illustrated inFIG. 1 or 2.

In some embodiments, the second die105is electrically connected to the conductive member102bor the conductive via102cthrough the second conductive bump107. In some embodiments, the second conductive bump107is disposed between the second die105and the dielectric layer102ato electrically connect the second die105to the second conductive member102b-2or the fourth conductive member102b-4. In some embodiments, the second conductive bump107is bonded with the second pad106b, such that the second die105is electrically connected to the via101c, the conductive member102bor the conductive via102c. In some embodiments, the electrical signal transmitted through the waveguide103, the third conductive member102b-3or the fourth conductive member102b-4is received by the second die105through the second conductive bump107.

In some embodiments, an underfill material108is disposed to surround the second conductive bump107as shown inFIG. 4Lafter the disposing of the first die104and the second die105. In some embodiments, the underfill material108surrounds the first die104and the second die105and fills gap between the adjacent second conductive bumps107. In some embodiments, the underfill material108is disposed by flowing, injection or any other suitable operations. In some embodiments, the underfill material108has configuration similar to the one described above or illustrated inFIG. 1 or 2.

In operation407, a molding109is formed as shown inFIG. 4M. In some embodiments, the molding109is formed over the RDL106, the interconnect structure102and the substrate101. In some embodiments, the molding109surrounds the first die104, the second die105, the underfill material108and the second conductive bump107. In some embodiments, the molding109is formed by transfer molding, injection molding, over molding or any other suitable operations. In some embodiments, the molding109is ground to expose a surface of the first die104or the second die105. In some embodiments, the molding109is ground by grinding, planarization, chemical mechanical polish (CMP) or any other suitable operations. In some embodiments, the molding109has configuration similar to the one described above or illustrated inFIG. 1 or 2.

In some embodiments, the substrate101is ground from the second surface101bto expose the via101cas shown inFIG. 4N. In some embodiments, the second surface101bis ground to become a new second surface101b′. In some embodiments, a carrier is temporarily attached to the first die104, the second die105and the molding109by an adhesive, and then the substrate101is ground from the second surface101b. In some embodiments, the carrier includes silicon or glass. In some embodiments, the adhesive is a light to heat conversion (LTHC) release film or the like. In some embodiments, the substrate101is ground by backside grinding, CMP or any other suitable operations.

In some embodiments, a first pad101dis formed over the substrate101as shown inFIG. 4O. In some embodiments, the first pad101dis formed over the second surface101b′ of the substrate101. In some embodiments, the first pad101dis formed over and electrically connected to the via101c. In some embodiments, the first pad101dis formed by disposing a conductive material over the substrate101. In some embodiments, the forming of the conductive material includes sputtering, electroplating or any other suitable operations. In some embodiments, the first pad101dhas configuration similar to the one described above or illustrated inFIG. 1 or 2.

In some embodiments, a first conductive bump101eis fabricated over the substrate101. In some embodiments, the first conductive bump101eis electrically connected to the conductive member102bthrough the via101c. In some embodiments, the first conductive bump101eis electrically connected to the first conductive member102b-1, the second conductive member102b-2, the third conductive member102b-3or the fourth conductive member102b-4through the via101c. In some embodiments, the first conductive bump101eis disposed over the first pad101d. In some embodiments, the first conductive bump101eis disposed before or after the formation of the waveguide103. In some embodiments, the first conductive bump101eis disposed before the disposing of the first die104and the second die105. In some embodiments, the first conductive bump101eis fabricated by ball dropping, solder pasting, stencil printing or any other suitable operations. In some embodiments, the first conductive bump101eis reflowed after the fabrication. In some embodiments, the first conductive bump101ehas configuration similar to the one described above or illustrated inFIG. 1 or 2. In some embodiments, a semiconductor structure100is formed, which has configuration similar to the one described above or illustrated inFIG. 1.

In the present disclosure, a semiconductor structure is disclosed. The semiconductor structure includes a waveguide disposed or formed between two conductive members in an interconnect structure. An electrical signal from a transmission die is converted to an electromagnetic signal at one conductive member, the electromagnetic signal is then transmitted through the waveguide to another conductive member, the electromagnetic signal is converted to an electrical signal at another conductive member, and the electrical signal is transmitted to a receiving die. Such signal transmission can minimize or prevent energy loss, and transmission speed is improved or increased.

In some embodiments, a semiconductor structure includes a substrate; an interconnect structure disposed or deposited over the substrate and including a dielectric layer over the substrate, a first conductive member disposed or formed within the dielectric layer and a second conductive member disposed or formed within the dielectric layer; a waveguide disposed between the first conductive member and the second conductive member; a first die disposed over the interconnect structure and electrically connected to the first conductive member; and a second die disposed over the interconnect structure and electrically connected to the second conductive member, wherein the waveguide is coupled with the first conductive member and the second conductive member.

In some embodiments, the first die and the second die are disposed adjacent to each other. In some embodiments, the waveguide is configured to transmit an electromagnetic signal from the first conductive member to the second conductive member within the waveguide. In some embodiments, the waveguide is configured to transmit an electromagnetic signal in a frequency of greater than 10 GHz. In some embodiments, a dielectric constant of the waveguide is substantially greater than a dielectric constant of the dielectric layer. In some embodiments, the first die is disposed over the first conductive member, and the second die is disposed over the second conductive member. In some embodiments, the first conductive member and the second conductive member are laterally extended within the dielectric layer. In some embodiments, the waveguide includes silicon nitride, silicon carbide or a dielectric material with a dielectric constant substantially greater than 4. In some embodiments, the semiconductor structure further includes a molding surrounding the first die and the second die. In some embodiments, a portion of the molding is disposed or formed over the waveguide. In some embodiments, the semiconductor structure further includes a via extended through at least a portion of the substrate and electrically connected to the first conductive member or the second conductive member; a first conductive bump disposed or fabricated over the substrate and the via and electrically connected to the via; a second conductive bump disposed or fabricated between the first die and the interconnect structure or between the second die and the interconnect structure; an underfill material surrounding the second conductive bump.

In some embodiments, a semiconductor structure includes a substrate; a via extended through at least a portion of the substrate; an interconnect structure disposed or deposited over the substrate and including a dielectric layer, a first transmission electrode disposed or formed within the dielectric layer and a first receiving electrode formed or disposed within the dielectric layer; a waveguide formed or disposed within the dielectric layer; a transmission die disposed over the interconnect structure and including a transmission circuit electrically connected to the first transmission electrode; and a receiving die disposed over the interconnect structure and including a receiving circuit electrically connected to the first receiving electrode, wherein the via is electrically connected to the first transmission electrode or the first receiving electrode, the transmission circuit is configured to generate an electrical signal, the receiving circuit is configured to receive the electrical signal, the electrical signal is convertible to an electromagnetic signal transmittable from the first transmission electrode to the first receiving electrode within the waveguide.

In some embodiments, the semiconductor structure further includes a second transmission electrode formed or disposed within the dielectric layer and disposed or disposed opposite to the first transmission electrode; a second receiving electrode formed or disposed within the dielectric layer and disposed or disposed opposite to the first receiving electrode. In some embodiments, a first end of the waveguide is surrounded by the first transmission electrode and the second transmission electrode, and a second end of the waveguide opposite to the first end is surrounded by the first receiving electrode and the second receiving electrode. In some embodiments, a height of the waveguide is about 1 μm to about 10 μm, or a width of the waveguide is about 10 μm to about 100 μm. In some embodiments, the transmission die includes a system on chip (SoC), central processing unit (CPU) die, graphics processing unit (GPU) die or mobile phone application processing (AP) die, and the receiving die includes high bandwidth memory (HBM) die. In some embodiments, a transmission speed of the electromagnetic signal is substantially greater than 10 Gigabytes per second (Gb/s).

In some embodiments, a method of manufacturing a semiconductor structure includes providing a substrate; depositing a dielectric layer over the substrate; forming a waveguide within the dielectric layer; forming a first conductive member and a second conductive member within the dielectric layer; disposing a first die over the dielectric layer; disposing a second die over the dielectric layer and adjacent to the first die; and forming a molding to surround the first die and the second die, wherein the waveguide is formed between the first conductive member and the second conductive member.

In some embodiments, the forming of the waveguide includes depositing a waveguide material over the dielectric layer, coating a photoresist over the dielectric layer, and removing a portion of the waveguide material exposed from the photoresist. In some embodiments, the method further includes forming a via extended through at least a portion of the substrate; fabricating a first conductive bump over the substrate to electrically connect to the first conductive member or the second conductive member by the via; fabricating a second conductive bump between the first die and the dielectric layer or between the second die and the dielectric layer to electrically connect the first die to the first conductive member or the second die to the second conductive member; dispensing an underfill material to surround the second conductive bump.