Voltage fluctuation detection circuit

The present disclosure provides a voltage fluctuation detection circuit, which includes a voltage adjustment circuit and a comparator. The voltage adjustment circuit includes an adjustment circuit input terminal to receive the operating voltage, a first adjustment circuit output terminal to output a first voltage, and a second adjustment circuit output terminal to output a second voltage that is step-shaped, the second voltage differs from the first voltage by a bias voltage at the beginning of a preset clock period and falls within a first amplitude within the preset clock period, the magnitude of the bias voltage is related to the first voltage. The comparator includes: a first comparator input terminal to receive the first voltage, a second comparator input terminal to receive the second voltage, and a comparator output terminal to output a comparison result of the first voltage and the second voltage.

RELATED APPLICATION

The present application claims the benefit of priority to the Chinese patent application No. 202110690539.4, filed on Jun. 22, 2021, and entitled “Voltage Fluctuation Detection Circuit,” the entire content of which is incorporated herein by reference.

TECHNICAL FIELD

The present disclosure relates to the technical field of integrated circuits (ICs), and in particular to a voltage fluctuation detection circuit.

BACKGROUND

In some cases, a specially designed circuit is required in an integrated circuit (IC) to detect the fluctuation of an electrical signal. For example, in some applications, it is necessary to detect the voltage of an input signal so as to determine whether the input signal is an alternating current (AC) signal or a direct current (DC) signal. The circuit needs to have high detection accuracy to ensure the performance of the IC, and it cannot be too complicated in order to reduce the cost and volume of the IC.

BRIEF SUMMARY

In order to solve the above-mentioned problems, the present disclosure provides a voltage fluctuation detection circuit. The voltage fluctuation detection circuit can detect the fluctuation of an electrical signal, and achieve a balance between circuit complexity, detection accuracy and sufficiently fast detection speed, thereby achieving a balance between the optimal performance and cost of an integrated circuit (IC).

The AC/DC voltage detection circuit includes:

DETAILED DESCRIPTION

The terms used herein are merely intended to describe specific examples or embodiments, rather than to limit the present disclosure. For example, unless contexts explicitly state otherwise, the singular forms “a”, “an” and “the” used herein may also include plural forms. In this disclosure, the terms “include” and/or “comprise” refer to the existence of an associated integer, step, operation, element, component and/or group, without excluding the existence of one or more other features, integers, steps, operations, elements, components and/or groups. In other words, other features, integers, steps, operations, elements, components and/or groups may be added to the system/method. In this disclosure, the term “A is on B” may mean that A is directly adjacent to B (above or below), or that A and B are indirectly adjacent (that is, A and B are separated by an object). The term “A is in B” may mean that A is completely in B or A is partially in B.

In the following description of the present disclosure, the economical efficiency of the features, the operation and function of related elements of the structure, as well as the combination and manufacturing of the components can be significantly improved. All of these aspects form part of the present disclosure with reference to the drawings. However, it should be understood that the drawings are merely intended for illustration purposes, rather than to limit the scope of the present disclosure.

In some cases, IC needs a specially designed circuit(s) to detect the fluctuation of electrical signal.

The present disclosure provides a voltage fluctuation detection circuit. The voltage fluctuation detection circuit can detect the fluctuation of the electrical signal. The voltage fluctuation detection circuit provided by the present disclosure can achieve a balance between circuit complexity and detection speed, and achieve the balance between optimal performance and IC cost. The voltage fluctuation detection circuit provided in this disclosure can be applied to all ICs for detecting the characteristics of electrical signals.

As an example,FIG.1illustrates a structure of a voltage fluctuation detection circuit001according to some exemplary embodiments of the present disclosure. As an example,FIG.2illustrates a timing diagram of various signals of the fluctuation voltage detection circuit in operation according to some exemplary embodiments of the present disclosure. Specifically, the voltage fluctuation detection circuit001may include a voltage adjustment circuit100and a comparator200. In some exemplary embodiments, the voltage fluctuation detection circuit001may further include a voltage divider circuit400, a peak latch circuit800and/or a detection and output circuit700.

The voltage divider circuit400may include any circuit for dividing a voltage signal VHVinput through a high voltage (HV) pin into an operating voltage signal V0. For example, as shown inFIG.1, the voltage divider circuit400may include a first resistor R1and a second resistor R2connected in series. An output terminal (e.g., output port)420of the voltage divider circuit400may be connected between the first resistor R1and the second resistor R2. One terminal (e.g., port) of the voltage divider circuit400may be connected to the voltage input HV pin, and the other terminal thereof may be connected to a ground wire GND. In this way, by reasonably designing the resistance of the first resistor R1and the second resistor R2, the voltage divider circuit400may divide the input voltage signal VHVinto the operating voltage signal V0at the output terminal420.

The operating voltage signal V0may be an AC signal or a DC signal. For ease of description, in the following description of the present disclosure, the working mechanism of the voltage fluctuation detection circuit001will be described by taking an AC voltage signal as the operating voltage signal. Referring toFIG.2, the operating voltage signal V0includes multiple periods, where the operating voltage signal in each period includes one rising edge and one falling edge.

The comparator200includes a first comparator input terminal210, a second comparator input terminal220and a comparator output terminal230. One of the first comparator input terminal210and the second comparator input terminal220may be a positive terminal (an input terminal marked with “+”) of the comparator200, and the other may be a negative terminal (an input terminal marked with “−”) of the comparator200. When the voltage of the positive terminal is higher than that of the negative terminal, the comparator output terminal comparator output terminal230of the comparator200outputs a high level. When the voltage of the negative terminal is higher than that of the positive terminal, the comparator output terminal comparator output terminal230of the comparator200outputs a low level. TakingFIG.1as an example, the first comparator input terminal210of the comparator may be electrically connected to a first output terminal102of the voltage adjustment circuit to receive a first voltage V1. The second comparator input terminal220of the comparator may be electrically connected to a second output terminal103of the voltage adjustment circuit to receive a second voltage V2. The comparator200may compare the magnitudes of the first voltage signal V1and the second voltage signal V2, and output a high level or a low level via the comparator output terminal230according to a comparison result, that is, to output the comparison result between the first voltage V1and the second voltage V2. When the first voltage signal V1is higher than the second voltage signal V2, the comparator outputs a high level. When the first voltage signal V1is lower than the second voltage signal V2, the comparator outputs a low level.

The detection and output circuit700is connected to the comparator output terminal230. The detection and output circuit700detects the comparison result output by the comparator output terminal230, and outputs a control signal based on the comparison result. The control signal may be used to control the start or stop of an integrated circuit (IC). The detection and output circuit700may also output a characteristic of the input signal based on the comparison result, for example, to indicate whether the type of the input signal is AC or DC. As an example, the detection and output circuit700may include at least one counting circuit. As an example, the counting circuit may include one or more counters for determining whether the type of the input signal is AC or DC by counting the number of flips of the output of the comparator between high and low levels.

One terminal of the peak latch circuit800may be connected to the comparator output terminal230of the comparator200and the other terminal thereof is connected to a voltage bias circuit110. The peak latch circuit800records and latches peak data of the VHVaccording to the output signal of the comparator output terminal230of the comparator, and transfers the peak data to the voltage bias circuit110. The voltage bias circuit110automatically adjusts the magnitude of a bias voltage according to the peak data.

The voltage adjustment circuit100may include an input terminal101, the first output terminal102and the second output terminal103. The input terminal101of the voltage adjustment circuit receives the operating voltage V0. The first output terminal102of the voltage adjustment circuit outputs the first voltage V1. The second output terminal103of the voltage adjustment circuit outputs the second voltage V2that is a step-shaped voltage. As an example, the second voltage V2is different from the first voltage V1by a bias voltage, i.e., ΔV, at the beginning of a preset clock period Tsample, and the second voltage does not drop by more than a first amplitude in the clock period Tsample. For example, the first amplitude may be 1%, 2%, 3%, 4%, 5%, 6%, 7%, 8%, 9% or 10%, or an interval between any two of the foregoing numbers, of ΔV. The magnitude of the bias voltage ΔV is related to the first voltage V1.

Specifically, the voltage adjustment circuit100may include a voltage bias circuit110and a step voltage generating circuit500.

The voltage bias circuit110may add the bias voltage ΔV to an input voltage Vinof the voltage bias circuit110and output a voltage Vout. As an example, the voltage bias circuit110may include at least one of a voltage-controlled voltage source, or a voltage-controlled current source. For example, the voltage bias circuit110may be a voltage-controlled current source.

As an example, the bias may be a positive bias (the bias voltage ΔV is a positive voltage), for example, the output voltage Voutis higher than the input voltage Vin by ΔV, that is, Vout=Vin+ΔV. The bias may also be a negative bias (the bias voltage ΔV is a negative voltage), for example, the output voltage Voutis lower than the input voltage Vinby ΔV, that is, Vout=Vin−ΔV. For ease of description, in the following description of the present disclosure, Vout=Vin+ΔV is taken as an example to illustrate the working mechanism of the rising edge detection circuit. As an example,FIG.3Aillustrates a comparison between the input voltage Vinand the output voltage Voutof the voltage bias circuit110according to some exemplary embodiments of the present disclosure. Referring toFIG.3A, the input voltage Vinrises along the rising edge, and the voltage bias circuit110adds the bias voltage ΔV to Vinto generate Vout.

It should be noted thatFIG.3Aexemplarily describes the working process of the voltage bias circuit110by taking the rising edge as an example, and the mechanism is the same for the falling edge.

Referring toFIG.1, the step voltage generating circuit500may convert a voltage input to the step voltage generating circuit into a step voltage. For example, the step voltage generating circuit500may include a switch circuit120, a clock circuit300and a voltage holding circuit130. As an example, the switch circuit120may include at least one field-effect transistor (FET). As an example, the FET may include, but is not limited to, a metal oxide semiconductor field-effect transistor (MOSFET), a bipolar junction transistor (BJT), a silicon controlled rectifier (SCR), a gate turn-off thyristor (GTO), an insulated gate bipolar transistor (IGBT), a MOS-controlled thyristor (MCT), or a static induction transistor (SIT). The clock circuit300is connected to the switch circuit120and controls the switch circuit120to be disconnected and connected according to the clock period Tsampleto generate the second voltage V2. The voltage holding circuit130is connected to the switch circuit120and holds the second voltage V2after the switch circuit120is disconnected, such that the second voltage does not drop by more than the first amplitude in the clock period Tsample. In this way, the second voltage V2applied to the second comparator input terminal220remains substantially constant during the clock period Tsample. As an example, the voltage holding circuit130may include at least one capacitor circuit.

As mentioned above, the first voltage V1is different from the second voltage V2by the bias voltage ΔV at the beginning of the preset clock period Tsample, and the second voltage does not drop by more than the first amplitude in the clock period Tsample.

The working mechanism of the voltage fluctuation detection circuit001will be described below.

For ease of description, in the following description of the present disclosure, a “first circuit S1” denotes a circuit connecting the input terminal101and the first output terminal102of the voltage adjustment circuit, and a “second circuit S2” denotes a circuit connecting the input terminal101and the second output terminal103of the voltage adjustment circuit. The operating voltage signal V0may be transmitted to the first comparator input terminal210and the second comparator input terminal220via the first circuit S1and the second circuit S2, respectively. Referring toFIG.1, an input terminal of the first circuit S1is electrically connected to the operating voltage V0, and an output terminal thereof is the first output terminal102of the voltage adjustment circuit. The first circuit S1may convert the operating voltage V0into the first voltage V1. An input terminal of the second circuit S2is electrically connected to the operating voltage V0, and an output terminal thereof is the second output terminal103of the voltage adjustment circuit. The second circuit S1may convert the operating voltage V0into the second voltage V2.

Referring toFIG.1, the voltage divider circuit400divides the input signal VHVinto the operating voltage V0. The operating voltage V0is then input to the adjustment circuit100from the input terminal101of the adjustment circuit. The adjustment circuit100adjusts the operating voltage V0to the first voltage V1and the second voltage V2, which are respectively output from the first output terminal102and the second output terminal103of the adjustment circuit. The first comparator input terminal210is a positive terminal, and the second comparator input terminal220is a negative terminal. The first comparator input terminal210of the comparator is connected to the first output terminal102of the adjustment circuit and receives the first voltage V1, and the second comparator input terminal220of the comparator is connected to the second output terminal103of the adjustment circuit and receives the second voltage V2.

The first output terminal102of the voltage adjustment circuit100is electrically connected to the input terminal101thereof. For example, as shown inFIG.1, two ends of the first circuit S1may be directly connected to the output terminal420of the voltage divider circuit400and the first comparator input terminal210of the comparator. Therefore, the first voltage V1delivered to the first comparator input terminal210of the comparator via the first circuit S1is equivalent to the operating voltage V0output from the output terminal of the voltage divider circuit400, that is, V1=V0.

The voltage bias circuit110is connected in series with the step voltage generating circuit500, and the circuits in series are respectively connected to the input terminal101and the second output terminal103of the voltage adjustment circuit. For example, as shown inFIG.1, the voltage bias circuit110and the step voltage generating circuit500may be connected in series and arranged on the second circuit S2. The input terminal of the voltage bias circuit110may be electrically connected to the output terminal420of the voltage divider circuit400. The voltage bias circuit110may add the bias voltage to the operating voltage V0. The voltage bias circuit110is configured to bias the operating voltage V0by ΔV. In other words, the voltage bias circuit110may add the bias voltage ΔV to the operating voltage V0. The bias voltage shown inFIG.1is a positive voltage.

The clock circuit300is connected to the switch circuit120. The clock circuit300sends out a clock pulse based on the preset clock period Tsampleto control the on and off of the switch circuit120.

One terminal of the switch circuit120is connected to the output terminal of the voltage bias circuit110, and the other terminal thereof is used as the output terminal of the voltage adjustment circuit100and connected to the second comparator input terminal220. When the switch circuit120is turned on, the second voltage V2output from the output terminal of the voltage bias circuit110may be connected to the second comparator input terminal220. When the switch circuit120is turned off, the second voltage V2cannot be connected to the second comparator input terminal220. As an example, the switch circuit120may include at least one FET or other circuit that may be controlled to turn on and off a power supply.

One terminal of the voltage holding circuit130is grounded (GND), and the other terminal thereof is connected to the second circuit S2between the switch circuit120and the second comparator input terminal220. The voltage holding circuit130is used to stabilize the second voltage V2, which is previously applied to the second comparator input terminal220when the switch circuit120is connected, within a preset range in the preset clock period after the switch circuit120is disconnected. As an example, the voltage holding circuit130includes at least one capacitor circuit. For example, inFIG.1, the voltage holding circuit130includes a capacitor Chold. When the switch circuit120is in a connected state, the second circuit S2is connected to apply the second voltage V2to the second comparator input terminal220, and the capacitor Choldis charged to the second voltage V2. When the switch circuit is in a disconnected state, the voltage V2of the capacitor Choldis applied to the second comparator input terminal220as an input signal of the second comparator input terminal220, such that the input signal of the second comparator input terminal220may be stabilized at the second voltage V2.

As an example,FIG.3Billustrates a comparison between the voltage Voutof the output terminal of the voltage bias circuit and the second voltage V2applied to the second comparator input terminal220of the comparator according to some exemplary embodiments of the present disclosure (ΔV>0).FIG.3Balso shows a timing diagram of the voltage Vinat the input terminal of the voltage bias circuit with a dotted line.

A pulse signal m1occurs at time t1. At this time, the voltage at the first comparator input terminal210is V1(t1). When the pulse signal m1arrives, the switch circuit120is connected, and the voltage at the second comparator input terminal220is V2(t1)=V1(t1)+ΔV. When the switch circuit120is connected, the capacitor Choldis charged, such that the voltage across positive and negative terminals of the capacitor Choldbecomes V2(t1). After the pulse signal m1ends, the switch circuit120is disconnected. The voltage stabilizing effect of the capacitor Choldcauses the second voltage at the second comparator input terminal220to basically stabilize at V2(t1). The stabilization time is a clock period Tsampleof the pulse signal, which is indicated by a horizontal line L1inFIG.4. As mentioned above, the “basically stabilize” means that the voltage stabilizing effect of the capacitor Choldallows the second voltage at the second comparator input terminal220to slightly drop on the basis of V2(t1). Such a drop does not exceed the first amplitude, for example, the first amplitude may be 1%, 2%, 3%, 4%, 5%, 6%, 7%, 8%, 9% or 10% of ΔV(t1), or it may be in an interval between any two of these numbers.

A pulse signal m2occurs at time t2. When the pulse signal m2arrives, the voltage at the first comparator input terminal210is V1(t2). The switch circuit120is connected again, and the voltage at the second comparator input terminal220increases instantaneously from V2(t1) to the voltage at the output terminal of the voltage bias circuit, that is, V2(t2)=V1(t2)+ΔV(t2). When the switch circuit120is connected, the capacitor Choldis charged, such that the voltage across positive and negative terminals of the capacitor Choldbecomes V2(t2). After the pulse signal m2ends, the switch circuit120is disconnected. The voltage stabilizing effect of the capacitor Choldcauses the second voltage at the second comparator input terminal220of the comparator to basically stabilize at V2(t2). The stabilization time is a clock period Tsampleof the pulse signal, which is indicated by the horizontal line L2inFIG.4. As mentioned above, the “basically stabilize” means that the voltage stabilizing effect of the capacitor Choldallows the second voltage at the second comparator input terminal220of the comparator to slightly drop on the basis of V2(t2). Such a drop does not exceed the first amplitude, for example, the first amplitude may be 1%, 2%, 3%, 4%, 5%, 6%, 7%, 8%, 9% or 10% of ΔV(t2), or it may be in an interval between any two of these numbers.

The timing of the voltage V2applied to the second comparator input terminal220of the comparator is shown inFIG.3B. Since the magnitude of the first voltage V1is equivalent to that of Vin, the relationship between the first voltage V1and the second voltage V2can be obtained. As an example,FIG.3Balso shows the timing of the first voltage V1applied to the first input terminal220of the comparator and the second voltage V2applied to the second comparator input terminal220of the comparator according to some exemplary embodiments of the present disclosure.

Referring toFIG.3B, the switch circuit120receives the pulse signal m2of the clock circuit300at time t2. The pulse signal m2causes the second voltage to increase from V2(t1) to V2(t2), which is indicated by a vertical line L3inFIG.3B. V2and V1cross at a cross point X1. The time corresponding to X1is t2. Before time t2, the first voltage is above the second voltage, that is, the first voltage is higher than the second voltage. After time t2, the first voltage is below the second voltage, that is, the first voltage is lower than the second voltage. The first voltage V1is applied to the first input terminal of the comparator, and the second voltage V2is applied to the second input terminal of the comparator. Therefore, before the clock signal m2arrives, the first voltage is higher than the second voltage, and the comparator output terminal230of the comparator200outputs a high level. After the clock signal m2ends, the first voltage is lower than the second voltage, and the comparator output terminal230of the comparator200outputs a low level. That is, when the clock signal m2arrives, the comparator flips from a high level to a low level. Therefore, the clock signal m2can cause the comparator to flip once.

Referring toFIG.3B, as described above, the second voltage V2is maintained at V2(t2) (indicated by the horizontal line L2) in a duration from the end of the pulse signal m2to the arrival of a pulse signal m3(that is, a t2−t3interval inFIG.3B). In this duration, the first voltage V1continuously climbs from the cross point X1. The first voltage and the second voltage cross again at point X2. The time corresponding to the cross point X2is tx2. That is, at tx2, the comparator flips again. As described above, at the time corresponding to the cross point X1, the output of the comparator flips from high to low (that is, a falling edge occurs). At the time corresponding to the cross point X2, the output of the comparator is flipped from low to high (that is, a rising edge occurs). At the time t3when the next pulse signal m3arrives, the output of the comparator is flipped from high to low again (that is, a falling edge occurs again).

The second voltage V2is lower than the first voltage V1at the beginning of the clock period Tsample. In a clock period Tsample, when the rising amplitude of the operating voltage V0exceeds the bias voltage, the output of the comparator200undergoes at least one flip between the high and low levels.

It should be noted that the premise of the above-mentioned flip is that at the beginning of the clock period Tsample, ΔV causes the step voltage V2to be higher than the voltage V1that naturally fluctuates with V0. The fluctuation interval of the voltage V1in one clock period Tsampleis higher than ΔV, such that V1crosses with V2. Under this condition, every time a pulse signal arrives, the output of the comparator is flipped from high to low (that is, a falling edge occurs). The output of the comparator between two pulse signals is flipped from low to high (that is, a rising edge occurs). When the next pulse signal arrives, the output of the comparator is flipped from high to low again (that is, a falling edge occurs again).

As described above, when the input signal VHVshown inFIG.2is an AC signal and VHVis at the falling edge, the first voltage V1drops with time, and it is lower than the second voltage V2at the beginning of the V1clock period. Therefore, the second voltage V2is always higher than the first voltage V1, and the output terminal of the comparator200always outputs a low level, and thus no flip occurs.

In summary, when VHVis at the rising edge, the output of the comparator will be flipped, that is, the comparator may output a pulse. When VHVis at the falling edge, the output of the comparator is not flipped, that is, the comparator does not output a pulse.

Therefore, by detecting whether the comparator can output a pulse by the detection and output circuit700, it can be known whether the VHVis currently at a rising edge or a falling edge.

The voltage fluctuation detection circuit provided by the present disclosure may detect the voltage of the AC line.

Firstly, the circuit has a simple structure and a small number of components, which can reduce the cost and volume of the IC.

In addition, the circuit has high accuracy and can achieve a balance between the circuit complexity, detection accuracy, detection speed and low cost, so as to achieve a balance between the optimal performance and the cost of the IC. For example, the frequency of the pulse output by the comparator may be controlled by simply setting the value of ΔV and the frequency of the sampling clock Tsample.

Further, for an analog IC (including, but not limited to, a switching power supply controller, an audio/video amplifier or a signal converter), if a digital circuit is used to sample and detect the characteristic of the electrical signal, the addition of a digital design to the analog IC will increase the cost of the IC. In the detection circuit provided by the present disclosure, the input signal VHVmay be an analog signal. When the detection circuit is applied to the analog IC, it can greatly reduce the complexity of the analog IC, and can achieve a balance between the circuit complexity, detection accuracy, sufficiently fast detection speed and low cost, so as to achieve a balance between the optimal performance and the cost of the IC.

The AC-DC controller can convert Alternating Current (AC) into Direct Current (DC) to implement the work of electronic circuits. On the one hand, the input signal of current AC-DC controller may only be AC, but not DC. On the other hand, for IC operation, the characteristics of input signals are important sensing information. Therefore, for IC operation, the control of an AC-DC power supply module(s) needs the information regarding the characteristics of the input signal of AC line, that is, whether the input voltage is DC or AC. At the same time, because the stability of some input voltages is not ideal, even DC voltage may have some fluctuations and noises. These disturbance and noises may affect the judgment on input signal characteristics.

In some exemplary embodiments, the operating current of the AC-DC controller can be expanded from DC to DC and AC to expand the operating conditions of the controller so as to enable the controller work in various environments. A detection circuit to detect whether the input signal is AC signal or DC signal is needed for designing a controller meeting both DC input and AC input requirements.

Regarding the voltage fluctuation detection circuit provided by the present disclosure, in the case where the input signal VHVis a DC signal, if noise and disturbance are not considered, or although VHVfluctuates, the fluctuation range is not large enough to require surpassing V1over V2in one clock period Tsample, the output terminal of the comparator200does not flip.

For example, referring toFIG.1, when the input signal VHVis DC, if noise and disturbance are not considered, the first voltage V1does not change in the clock period Tsample, and V1=V0. The voltage at the input terminal of the voltage bias circuit is Vin=V0=V1, and the voltage at the output terminal of the voltage bias circuit110is Vout=V0+ΔV=V1+ΔV. In the clock period Tsample, Voutremains unchanged. When the switch circuit120is connected, V2=Vout=V0+ΔV=V1+ΔV. When the switch circuit is disconnected, V2=VC=Vout=V0+ΔV=V1+ΔV. That is, in the entire clock period, V2is always higher than V1by ΔV, that is, V2=V1+ΔV. V2and V1do not cross, so the output terminal of the comparator always outputs a low level.

Therefore, if the value of ΔV can be properly selected, the voltage fluctuation detection circuit001can detect whether the operating voltage V0is AC or DC. The voltage adjusting circuit100is for the operating voltage V0, and outputs a first voltage V1through the first voltage adjusting circuit output terminal102and a second voltage V2through the second voltage adjusting circuit output terminal103. The second voltage V2differs from the first voltage V1by a bias voltage ΔV at the beginning of a preset clock period Tsample, and the second voltage V2falls within a first amplitude within the clock period Tsample.

At the beginning of the clock period Tsample, the bias voltage ΔV is added to the first voltage V1by the voltage bias circuit110to make the second voltage V2generate a step. Before the step, the second voltage is less than the first voltage, and the comparator outputs a high level. After the step, the second voltage is greater than the first voltage, and the comparator outputs a low level. That is, this step makes the output of the comparator change from high level to low level. In other words, at the beginning of clock period Tsample, the second voltage V2is stepped by a bias voltage ΔV, which makes the second voltage V2and the first voltage V1cross once and the comparator flip once.

In other words, the voltage fluctuation detection circuit provided in this disclosure can be used for AC-DC controllers. The voltage fluctuation detection circuit can detect whether the operating current of the AC-DC controller is AC or DC, thereby facilitating the expansion of the operating current of the AC-DC controller from DC to DC and AC.

In summary, in the voltage fluctuation detection circuit provided by the present disclosure, the voltage bias circuit110in the voltage adjustment circuit100adds a bias to the operating voltage V0. The bias is stored in the capacitor Choldwhen the switch is turned on. The bias signal is sampled and held by the switch downstream of the voltage bias circuit110, the clock signal and the capacitor Chold. Slopes of the first voltage signal (direct sample) applied to the first input terminal of the comparator and the second voltage applied to the second input terminal of the comparator are different, such that a crossing occurs in the clock period. The output of the comparator is flipped every time a crossing occurs. By determining whether the comparator outputs a pulse signal, the characteristic of the input electrical signal may be determined, for example, whether the input signal fluctuates, whether the input signal is at a rising edge or a falling edge.

In some exemplary embodiments, the magnitude of ΔV is constant, regardless of the characteristic of the input voltage Vin.

As an example,FIG.4Aillustrates a comparison of outputs corresponding to two different inputs VHV1and VHV2under a constant ΔV according to some exemplary embodiments of the present disclosure.

FIG.4Ashows three diagrams in sequence from left to right. In the three diagrams, the sampling clock period is Tsample. In the left diagram ofFIG.4A, a corresponding input signal is VHV1, and a corresponding bias voltage is ΔV. In the middle diagram ofFIG.4A, a corresponding input signal is VHV2, and a corresponding bias voltage is ΔV. In the right diagram ofFIG.4A, a corresponding input signal is VHV2, and a corresponding bias voltage is ΔV′. InFIG.4A, the peak of the signal VHV2is higher than that of the signal VHV1, and ΔV′ is higher than ΔV.

Referring to the left diagram inFIG.4A, when the input signal is VHV1, in a clock period T(1), V1and V2cross (cross point X1), and the comparator outputs a pulse. In a clock period T(2), V1and V2cross (cross point X2), and the comparator outputs a pulse. In a clock period T(3), V1and V2do not cross (cross point X2), and the comparator stops outputting a pulse. According to the above description, the detection and output circuit700determines whether the input signal VHVis currently at a rising edge or a falling edge by determining whether the comparator can output a pulse. If the detection and output circuit700is configured to output a signal indicating a falling edge when a next clock pulse (corresponding to a pulse m4at t4in the left diagram ofFIG.4A) arrives after the comparator stops outputting a pulse, then, as shown in the left diagram ofFIG.4A, the detection and output circuit700outputs a signal at t4to indicate that the VHVchanges from a rising edge to a falling edge. In some embodiments, a second target circuit may be provided in the detection and output circuit700to monitor the output of the comparator. For example, if the second target circuit is configured to detect the output of the comparator, when the pulse m4at time t4arrives, the output of the second target circuit undergoes a flip. As an example, the second target circuit may be a monitoring circuit. As an example, the monitoring circuit may include a power-on prohibition unit or a switch signal prohibition unit. In some exemplary embodiments, the power-on prohibition unit may include a hardware-based power-on prohibition circuit, and the switch signal prohibition unit may include a hardware-based switch signal prohibition circuit. In some exemplary embodiments, the monitoring circuit may also be implemented by a software-controlled general-purpose circuit, for example, the general-purpose circuit may be controlled by a power-on prohibition program or a switch signal prohibition program to complete the function of the power-on prohibition circuit or the switch signal prohibition circuit.

Referring to the middle diagram ofFIG.4A, when the input signal is VHV2, V1and V2cross (cross point Y1) in the clock period T(1), and the comparator outputs a pulse. Since the clock period T(2), V1and V2do not cross, and the comparator stops outputting a pulse. According to the above description, the detection and output circuit700determines whether the input signal VHVis currently at a rising edge or a falling edge by determining whether the comparator may output a pulse. Similarly, if the detection and output circuit700is configured to output a signal indicating a falling edge when a next clock pulse (corresponding to a pulse m3at t3in the middle diagram ofFIG.4A) arrives after the comparator stops outputting a pulse, then, as shown in the middle diagram ofFIG.4A, the detection and output circuit700outputs a signal at t3to indicate that the VHVchanges from a rising edge to a falling edge. As an example, if the second target circuit is configured to detect the output of the comparator, when the pulse m3at time t3arrives, the output of the second target circuit undergoes a flip.

The left diagram ofFIG.4Ais compared with the middle diagram ofFIG.4A. When the input signal is VHV2with a small peak, if the same bias voltage ΔV is used, compared with the left diagram ofFIG.4A, the middle diagram ofFIG.4Ashows that the time when the second target circuit undergoes a flip has a long wavelength band from a peak901of VHV2. That is, when the second target circuit undergoes a flip, VHV2actually has a long wavelength band before it changes from a rising edge to a falling edge. This is because when the peak of the input signal VHV2is small, its initial slope is also small. In this case, if it is determined directly according to the output result of the comparator that the rising edge is ended and the falling edge is started, the detection accuracy of the circuit is not very high.

In some exemplary embodiments, the magnitude of ΔV may be related to Vin.

As an example, the magnitude of ΔV may be positively correlated with the peak of Vin. That is, if the peak of VHV2is lower than that of VHV1, then the value of ΔV2is lower than that of ΔV1. As an example,FIG.4Billustrates a relationship between ΔV and the peak of Vinaccording to some exemplary embodiments of the present disclosure. In the exemplary embodiments shown inFIG.4B, ΔV=K·(peak of Vin), where K is a constant value, that is, ΔV has a linear positive correlation with the peak of VHV. It should be noted thatFIG.4Bis only an example to describe the positive correlation between ΔV and the peak of VHV. The positive correlation between ΔV and the peak of VHVmay also be non-linear without affecting the core spirit of the present disclosure. For example,FIG.4Cillustrates another relationship between ΔV and the peak of Vinaccording to some exemplary embodiments of the present disclosure. InFIG.4C, ΔV is positively, but not linearly correlated with the peak of VHV. Of course, in some exemplary embodiments, the magnitude of ΔV may also change in real time with Vin. For example, ΔV(t)=K·Vin(t).

Referring toFIG.4A, as shown in the right diagram ofFIG.4A, when the input signal is VHV2with a small peak, if a small bias voltage ΔV′ is used, in a clock period T(1), V1and V2cross (cross point Z1), and the comparator outputs a pulse. In a clock period T(2), V1and V2cross (cross point Z2), and the comparator outputs a pulse. Since a clock period T(3), V1and V2do not cross, and the comparator stops outputting a pulse. According to the above description, the detection and output circuit700determines whether the input signal VHVis currently at a rising edge or a falling edge by determining whether the comparator outputs a pulse. Similarly, if the detection and output circuit700is configured to output a signal indicating a falling edge when a next clock pulse (corresponding to a pulse m4at t4in the right diagram ofFIG.4A) arrives after the comparator stops outputting a pulse, then, as shown in the right diagram ofFIG.4A, the detection and output circuit700outputs a signal at t4to indicate that the VHVchanges from a rising edge to a falling edge. As an example, if the second target circuit is configured to detect the output of the comparator, when the pulse m4at time t4arrives, the output of the second target circuit undergoes a flip.

The middle diagram ofFIG.4Ais compared with the right diagram ofFIG.4A. When the input signal is VHV2with a small peak, if a small bias voltage ΔV′ is used, compared with the middle diagram ofFIG.4A, the right diagram ofFIG.4Ashows that the time when the output signal of the second target circuit is flipped is delayed backward by one clock period Tsample. Compared with the middle diagram ofFIG.4A, in the right diagram, the input signal VHVcorresponding to the time when the output signal of the second target circuit is flipped is closer to the peak901, which improves the detection accuracy of the circuit.

It should be noted that, in the above description, the principle of the voltage fluctuation detection circuit provided in this disclosure is introduced by taking the rising edge as an example. The voltage fluctuation detection circuit provided by the present disclosure may also detect the falling edge so as to detect the input signal. In the case where the input signal is at the falling edge, if the circuit is so constructed that the first voltage is higher than the second voltage at the beginning of the clock period Tsample, and the falling amplitude of the first voltage V1exceeds the bias voltage value within one clock period, the output of the comparator is flipped at least once.

For example, the bias voltage inFIG.1may be set as −ΔV. In this case, the first voltage is higher than the second voltage at the beginning of the clock period Tsample, and in one clock period the falling amplitude of the first voltage V1exceeds the bias voltage amplitude ΔV, the output of the comparator200is flipped at least once.

FIG.5illustrates a structure of another voltage fluctuation detection circuit002according to some exemplary embodiments of the present disclosure.

Referring toFIG.5, the voltage bias circuit110is provided on the first circuit S1. The voltage bias circuit110is connected in series with the first output terminal102and the input terminal101of the adjustment circuit. That is, two ends of the voltage bias circuit110are respectively connected to the output terminal101and the first output terminal102of the adjustment circuit.

The step voltage generating circuit500is provided on the second circuit S2. The step voltage generating circuit500is connected in series with the input terminal101and the second output terminal103of the adjustment circuit. That is, two ends of the step voltage generating circuit500are respectively connected to the output terminal101and the second output terminal103of the adjustment circuit. Referring toFIG.5, the first comparator input terminal210of the comparator is a positive terminal, the second comparator input terminal220of the comparator is a negative terminal, and the bias voltage is a negative voltage −ΔV.

As an example,FIG.6illustrates a comparison between the operating voltage V0, the first voltage V1and the second voltage V2in the structure of the circuit shown inFIG.5.

The voltage bias circuit110adds a bias voltage to the operating voltage V0to generate the first voltage V1. The bias voltage is negative, and its absolute value is equal to ΔV, that is, the bias voltage is −ΔV. Therefore, V1=V0−ΔV. The timing of the first voltage V1is indicated by V1inFIG.6.

The step voltage generating circuit500acts on the operating voltage signal V0to cause the operating voltage signal V0to step so as to generate a step-shaped second voltage V2.

Referring toFIGS.5and6, a switch Q1is turned on when the clock pulse m1arrives. The second voltage V2is equal to the operating voltage V0, which is V2(t1). When the switch Q1is turned on, the capacitor Choldis charged to V2(t1). After the clock pulse m1ends, the switch Q1is turned off. The capacitor Choldkeeps the voltage on the negative terminal of the comparator basically at V2(t1) (indicated by the horizontal line L1inFIG.6), and the holding time is one clock period Tsampleof the clock pulse. The ‘basically stabilize” means that the voltage stabilizing effect of the capacitor Choldallows the second voltage at the second comparator input terminal220of the comparator to slightly drop on the basis of V2(t1). Such a drop does not exceed the first amplitude, for example, the first amplitude may be 1%, 2%, 3%, 4%, 5%, 6%, 7%, 8%, 9% or 10% of ΔV(t1), or may be in an interval between any two of these numbers. It can be seen fromFIG.6that the first voltage V1is lower than the second voltage V2at the beginning of the corresponding clock period Tsampleindicated by the horizontal line L1. In the clock period Tsample, the operating voltage V0rises along the rising edge, the first voltage V1also rises along the rising edge, but the second voltage V2remains substantially constant under the action of the capacitor Chold. In this clock period, as the first voltage V1rises, the first voltage V1and the second voltage V2cross (cross point X1), and the comparator undergoes a flip.

When the clock pulse m2arrives, the switch Q1is connected, and the second voltage V2instantaneously increases to the operating voltage V0, that is, V2(t2). Before the clock pulse m2arrives, the magnitude of the second voltage V2is V2(t1). The arrival of the clock pulse m2causes the second voltage V2to instantaneously rise from V2(t1) to V2(t2). Before the rise, the magnitude of the second voltage, i.e. V2(t1), is lower than that of the first voltage V1, that is, the voltage on the positive terminal of the comparator is higher than that on the negative terminal, and the comparator outputs a high level. After the rise, the magnitude of the second voltage V2(t2) is higher than that of V1, that is, the voltage on the positive terminal of the comparator is lower than that on the negative terminal, and the comparator outputs a low level. That is, the arrival of the clock pulse m2causes the first voltage V1and the second voltage V2to cross once (cross point X2), and the comparator flips once.

Meanwhile, when the clock pulse m2arrives and the switch Q1is turned on, the capacitor Choldis charged, such that the voltage across the positive and negative terminals of the capacitor Choldbecomes V2(t2). After the clock pulse m2ends, the switch Q2is turned off. The capacitor Choldkeeps the second voltage V2applied to the negative terminal of the comparator at V2(t2) (indicated by the horizontal line L2inFIG.6), and the holding time is one clock period Tsampleof the clock pulse.

In summary, a negative bias voltage can also be used to make the first voltage and the second voltage cross in the clock period and make the comparator flip. Thus, it can also be determined whether the input signal is a DC signal or an AC signal by determining the output of the comparator (for example, whether the comparator can output a pulse and the number of output pulses).

It should be noted that, for ease of description, in the above description, the principle of the AC/DC voltage detection circuit is described with the first input terminal of the comparator as a positive terminal and the second input terminal of the comparator as a negative terminal. The first input terminal of the comparator may also be a negative terminal and the second input terminal of the comparator may also be a positive terminal without affecting the core principle of the present disclosure.

In addition, the bias voltage inFIG.5can also be set to +ΔV for detecting the falling edge of the operating voltage V0. In this case, the first voltage is higher than the second voltage at the beginning of the clock period Tsampleand the falling amplitude of the first voltage V1exceeds the bias voltage value amplitude ΔV within one clock period, the output of the comparator200is flipped at least once.

FIG.7illustrates a structure of a voltage fluctuation detection circuit003according to some exemplary embodiments of the present disclosure. The circuit structure shown inFIG.7is similar to that shown inFIG.1, except that inFIG.7, the first output terminal of the voltage adjustment circuit is connected to the first input terminal of the comparator, and the first input of the comparator is a negative terminal of the comparator. In addition, inFIG.7, the second output terminal of the voltage adjustment circuit is connected to the second input terminal of the comparator, and the second input terminal of the comparator is a positive terminal of the comparator. That is, the voltage bias circuit110is connected in series with the step voltage generating circuit500and is provided on the first circuit S1. Therefore, the first voltage is applied to the negative terminal of the comparator, and the second voltage is applied to the positive terminal of the comparator.

The comparison between the first voltage and the second voltage illustrated inFIG.3Bis applicable to the circuit structure shown inFIG.7. Referring toFIG.3B, in the circuit structure shown inFIG.7, for every clock period that comes, the comparator flips once at the arrival of the clock period and flips again during the clock period. In the circuit structure shown inFIG.7, taking the clock signal m2as an example, before the clock signal m2arrives, the second voltage V2(t1) is lower than the first voltage V1, that is, the voltage on the positive terminal of the comparator is lower than that on the negative terminal, and the comparator outputs a low level. The arrival of the clock pulse m2causes the second voltage to rise instantaneously from V2(t1) to V2(t2). After the rise, the second voltage V2(t2) is higher than the first voltage V1, that is, the voltage on the positive terminal of the comparator is higher than that on the negative terminal of the comparator, and the comparator outputs a high level. That is, the arrival of the pulse signal m2causes the comparator to flip from a low level to a high level. After the pulse signal m2ends, the second voltage is maintained at V2(t2) under the action of the capacitor Chold. As the first voltage rises along the rising edge, the second voltage and the first voltage cross again (cross point X2). Before the cross point X2, the second voltage is higher than the first voltage, that is, the voltage on the positive terminal of the comparator is higher than that on the negative terminal of the comparator, and the comparator outputs a high level. After the cross point X2, the second voltage is lower than the first voltage, that is, the voltage on the positive terminal of the comparator is lower than that on the negative terminal of the comparator, and the comparator outputs a low level. That is, in the clock period Tsample, the comparator flips from a high level to a low level.

When the clock pulse arrives, the comparator flips from a low level to a high level, and before the next clock pulse arrives, the comparator flips from a high level to a low level. Therefore, it can also be determined whether the input signal is a DC signal or an AC signal by determining the output of the comparator (for example, whether the comparator can output a pulse and the number of output pulses).

In addition, the bias voltage inFIG.7can also be set to −ΔV for detecting the falling edge of the operating voltage V0. In this case, the first voltage is higher than the second voltage at the beginning of the clock period Tsample and the falling amplitude of the first voltage V1exceeds the bias voltage value amplitude ΔV within one clock period, the output of the comparator200is flipped at least once.

FIG.8illustrates a structure of a voltage fluctuation detection circuit004according to some exemplary embodiments of the present disclosure. The circuit structure shown inFIG.8is similar to that shown inFIG.5, except that inFIG.8, the first output terminal of the voltage adjustment circuit is connected to the first input terminal of the comparator, and the first input of the comparator is a negative terminal of the comparator. In addition, inFIG.8, the second output terminal of the voltage adjustment circuit is connected to the second input terminal of the comparator, and the second input terminal of the comparator is a positive terminal of the comparator. In other words, the first voltage is applied to the negative terminal of the comparator, and the second voltage is applied to the positive terminal of the comparator. The analysis ofFIG.8may be referred to that ofFIG.5, which will not be repeated herein for the sake of brevity.

In summary, the voltage fluctuation detection circuit provided by the present disclosure adds a bias to the operating voltage V0through the voltage bias circuit110in the voltage adjustment circuit100. The bias is stored in the capacitor Choldwhen the switch is turned on. The bias signal is sampled and held by the switch downstream of the voltage bias circuit110, the clock signal and the capacitor Chold. Slopes of the first voltage signal (direct sample) applied to the first input terminal of the comparator and the second voltage applied to the second input terminal of the comparator are different, such that a crossing occurs in the clock period. The output of the comparator is flipped every time a crossing occurs. By determining whether the comparator can output a pulse signal, the fluctuation of the electrical signal can be determined, for example, whether the electrical signal fluctuates, or whether the electrical signal is at a rising edge or a falling edge.

The voltage fluctuation detection circuit provided by the present disclosure can detect the voltage of an AC line. The circuit has a simple structure and a small number of components, which can reduce the cost and volume of the IC. The circuit has high accuracy and can achieve a balance between the circuit complexity, detection accuracy, sufficiently fast detection speed and low cost, so as to achieve a balance between the optimal performance and the cost of the IC. For example, the frequency of the pulse output by the comparator can be controlled only by reasonably setting the value of ΔV and the frequency of the sampling clock Tsample.

For an analog IC (including, but not limited to, a switching power supply controller, an audio/video amplifier or a signal converter), if a digital circuit is used to sample and detect the characteristic of the electrical signal, the addition of a digital design to the analog IC will increase the cost of the IC. In the detection circuit provided by the present disclosure, the input signal VHVmay be an analog signal. When the detection circuit is applied to the analog IC, it can greatly reduce the complexity of the analog IC, and can achieve a balance between the circuit complexity, detection accuracy, sufficiently fast detection speed and low cost, so as to achieve a balance between the optimal performance and the cost of the IC.

The voltage fluctuation rising edge detection circuit provided by the present disclosure can be used in an AC-DC controller. The voltage fluctuation rising edge detection circuit can detect whether the operating current of the AC-DC controller is AC or DC, thereby expanding the operating current of the AC-DC controller from DC to DC and AC.

The basic concepts are described above, and those skilled in the art may better understand, after reading this detailed disclosure, that the above detailed disclosure is intended to be presented by way of example only and not limitation. Although it is not explicitly stated herein, those skilled in the art may make various changes, improvements and modifications to the present disclosure. For example, the steps in the method of the present disclosure may not necessarily be performed in exactly the order described. These steps may also be performed in part and/or in other combinations as reasonably expected by those of ordinary skill in the art. These changes, improvements and modifications are intended to be included in the present disclosure, and fall within the scope of the embodiments of the present disclosure.

In addition, some terms are used to describe the embodiments of the present disclosure. For example, the terms “an embodiment”, “one embodiment” and/or “some exemplary embodiments” mean that a particular feature, structure or characteristic described in the embodiment(s) is included in at least one embodiment of the present disclosure. Therefore, it should be emphasized and understood that two or more references to “an embodiment”, “one embodiment” or “an alternative embodiment” in various parts of this disclosure may not necessarily all refer to the same embodiment. In addition, the specific features, structures or characteristics may be appropriately combined in one or more embodiments of the present disclosure.

In addition, those skilled in the art should understand that the aspects of the present disclosure may be described herein in either form of many patentable categories or contexts. These categories and contexts include any new and useful processes, machines, manufacturing or composition issues, or any new and useful improvements. Correspondingly, various aspects of the present disclosure may be fully implemented in hardware or software (including firmware, resident software, microcode, etc.). Alternatively, the software and hardware implementations may be combined, and all of them are generally referred to herein as “blocks”, “modules”, “engines”, “units”, “components” or “systems”. In addition, the aspects of the present disclosure may take the form of a computer program product embodied in one or more computer-readable media on which computer-readable program codes are present.

Further, the stated order of processing elements or sequences, and the numbers, letters or other names used accordingly, are not intended to limit the claimed processes and methods to any order, unless it is defined in the claims. Although various embodiments have been discussed above through various embodiments that are currently considered to be useful embodiments of the present disclosure, it should be understood that such details are only for such a purpose. The appended claims are not limited to the disclosed embodiments, and on the contrary, they are intended to cover modifications and equivalent arrangements made within the scope of the disclosed embodiments. For example, although the implementation of the various components described above can be embodied in a hardware device, it can also be implemented as a software-only solution, for example, an installation on an existing server or mobile device.

Similarly, it should be understood that in the above description of the exemplary embodiments of the present disclosure, various features are sometimes combined in a single embodiment, drawing or description thereof to simplify the present disclosure and make one or more of the various creative embodiments better understood. However, the method of the present disclosure should not be interpreted as reflecting an intention that the claimed subject matter requires more features than those explicitly recited in each claim. In contrast, an inventive embodiment may have fewer features than all the features of a single previously disclosed exemplary embodiment.