Liquid crystal display device and fabrication method thereof

Disclosed is a liquid crystal display device and a fabrication method thereof comprises a data PCB substrate having a data pad block and a gate PCB substrate having a gate pad block; a data dummy pad and a gate dummy pad formed on the data PCB substrate and on the gate PCB substrate, respectively; and a repair redundancy line formed on the gate pad block and the data pad block to form a redundancy line path between them.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The preferred embodiment of the present invention will be described in detail with reference to accompanying drawings. FIG. 2 is a drawing for showing a PCB having a repair redundancy line thereon, according to the present invention. FIG. 3 is a detailed drawing of A part in FIG. 2 according to the present invention. FIG. 4 is a detailed drawing of B part in FIG. 2 according to the present invention. FIG. 5 is a flow chart for showing a fabrication method of array substrate of liquid crystal display device according to the present invention. Referring to FIG. 2 , according to the present invention, a repair redundancy line 35 is formed differently from the repair redundancy line 15 according to a conventional method as shown in FIG. 1 . Referring to FIG. 3, a drawing number 17 is a current path of repair redundancy line according to a conventional method and a drawing number 37 is that according to the present invention. Referring to FIG. 4, a repair redundancy line 35 is formed on a part wherein capacitor is not generated with a ground in a PCB substrate. On the other hand, according to the present invention, an array substrate is fabricated by forming an address wiring on an array substrate and at the same time forming a repair line to form a redundancy line path with a data dummy pad on a gate dummy pad. Then, an insulating layer is formed on the array substrate and a-Si layer is formed as a channel layer of thin film transistor. Subsequently, in forming signal line wiring, a repair line to form the redundancy line path with the gate dummy pad is formed on the data dummy pad. And, a protective layer made of SiNx is formed on the thin film transistor in order to protect the thin film transistor. And then, a pixel electrode made of ITO and additional capacitor are formed at the same time and a current path is formed to interconnect the repair lines. The liquid crystal display device having the above array substrate has a thin film display device on one substrate and a color filter on the other substrate. And, in order to solve problems from signal line disconnection, the repair redundancy line 35 is formed on the edge of active area in the panel. And, the number of the repair redundancy line 35 formed on the edge of the active area 41 in the panel is one or more to be connected into the PCB through TCP 80 . Additionally, the current path 37 of the repair redundancy line 35 is connected to that of a dummy pad of the gate pad through a dummy pad of the data pad and the repair redundancy line 35 is formed on the edge of PCB to eliminate capacitor with ground. And, in the repair redundancy line 35 , the current path 37 is formed through the data dummy pad bonded to data PCB and through the gate dummy pad 50 bonded to gate PCB unlike the conventional method in that the current path 17 is formed on the gate PCB by FPC 90 . Referring to FIGS. 2 and 3 , repair redundancy lines 35 are formed on a gate dummy pad 50 b of the closest gate pad block 31 a transferring from the data PCB substrate 21 to the gate PCB substrate 31 and on a data dummy pad 50 a of the data pad 21 . Here, the gate pad 31 and the data pad 21 has different metal formation process. Therefore, via hole is formed and a current path 37 is formed by connecting each other in formation of ITO. If the data PCB substrate and the gate PCB are interconnected by a FPC 90 as in a conventional method, capacitor is formed between ground and repair line, thereby causing repair line delay. And, if the repair current path 37 is formed in order to prevent generation of capacitor, the structures of X and Y PCBs become complicated. Accordingly, as shown in FIG. 4 , instead of ground, a plurality of repair redundancy lines are formed on the edge of PCB pad of PCB substrate. If a ground pattern is formed on the part wherein the repair redundancy line may be formed, capacitor is formed, thereby causing repair line delay. Therefore, it is essential not to form the ground pattern in the process of forming PCB. As described above, according to the present invention, the repair redundancy line is formed on the edge of PCB, wherein the ground pattern is not formed. Therefore, capacitor is not generated between the ground and the repair redundancy line and thereby repair line delay is prevented. Moreover, a circuit diagram of PCB substrate is simplified since the current path is formed in a cell, not in the FPC.