Semiconductor device

Provided is a semiconductor device having an RC-IGBT structure, the semiconductor device comprising an FWD (Free Wheel Diode) region and an IGBT (Insulated Gate Bipolar Transistor) region. Provided is a semiconductor device comprising:a semiconductor substrate; a transistor section formed on the semiconductor substrate; a diode section formed on the semiconductor substrate and including a lifetime killer at a front surface side of the semiconductor substrate;a gate runner provided between the transistor section and the diode section and electrically connected to a gate of the transistor section.

The contents of the following Japanese patent application(s) are incorporated herein by reference:NO. 2016-027035 filed in JP on Feb. 16, 2016, andNO. 2016-224025 filed in JP on Nov. 17, 2016.

BACKGROUND

1. Technical Field

The present invention relates to a semiconductor device.

2. Related Art

Conventionally, a semiconductor device having an RC-IGBT structure is known, the structure including an FWD region and an IGBT region formed to be adjacent to each other (for example, Japanese Patent Application Publication No. 2004-363328).

However, in the conventional semiconductor device, a lifetime killer to be injected into the FWD region is also injected into the IGBT region, which may hamper electric properties of the IGBT.

SUMMARY

In a first aspect of the present invention, provided is a semiconductor device comprising: a semiconductor substrate; a transistor section formed on the semiconductor substrate; a diode section formed on the semiconductor substrate and including a lifetime killer at a front surface side of the semiconductor substrate; a gate runner provided between the transistor section and the diode section and electrically connected to a gate of the transistor section.

The semiconductor substrate may include a lifetime killer in at least some regions at the front surface side of the semiconductor substrate and below the gate runner.

The semiconductor substrate may include a lifetime killer in an entire region at the front surface side of the semiconductor substrate and below the gate runner.

The semiconductor substrate may include a lifetime killer in at least a portion at the front surface side of the semiconductor substrate and closer to the transistor section than to the gate runner.

A collector region of the transistor section may be formed in at least a portion below the gate runner.

A collector region of the transistor section may be formed in an entire region below the gate runner.

A collector region of the transistor section may be formed at least a portion closer to the diode section than to the gate runner.

A cathode region of the diode section may not be formed below the gate runner.

The semiconductor device may further comprise a well region having a conductivity type different from that of the semiconductor substrate and formed below the gate runner.

The transistor section may include a gate trench section formed on the front surface of the semiconductor substrate, and at least a portion of the gate trench section may be formed below the gate runner.

The diode section may be arranged at an end portion of an active region of the semiconductor device.

The diode section may be arranged at a corner portion of an active region of the semiconductor device.

The diode section may surround the transistor section in a planar view.

The transistor section may surround the diode section in a planar view.

The semiconductor device may further comprise: a temperature sensor provided adjacent to the transistor section to detect signals in response to a temperature of the transistor section; and a temperature sensor terminal electrically connected to the temperature sensor through a wiring for sensors, to which the signals detected by the temperature sensor are input.

The diode section may include an isolation region to allow at least one of the gate runner and the wiring for sensors to traverse the diode section.

The temperature sensor may be arranged above a well region.

The temperature sensor may be surrounded by the transistor section.

The diode section may include: a first diode region formed at one end of an active region of the semiconductor device; and a second diode region formed at the other end of the active region opposing to the one end.

The temperature sensor may be provided between the first diode region and the second diode region.

The semiconductor device may further comprise: an emitter region of a first conductivity type formed on the front surface of the semiconductor substrate; a base region of a second conductivity type which is different from the first conductivity type formed on the front surface of the semiconductor substrate;

an accumulating layer of the first conductivity type formed at the front surface side of the semiconductor substrate and having a higher concentration than an impurity concentration of the semiconductor substrate; and an interlayer insulating film formed on the front surface of the semiconductor substrate. Also, the interlayer insulating film may include a contact hole corresponding to at least some regions of the emitter region and the base region and formed to penetrate the interlayer insulating film. The accumulating layer may be formed inside a region in which the contact hole is formed in an extending direction of a trench section included in the transistor section.

The accumulating layer may be formed inside a region in which the contact hole is formed in an extending direction of a trench section included in the diode section.

The accumulating layer may be formed in a region in which the transistor section, the diode section and the gate runner are formed.

At least a portion of the accumulating layer may be formed within a well region.

The contact hole at the diode section side may be formed to be apart from a well region in a planar view.

At least a portion of an end portion of a trench section of the transistor section may be formed within a well region.

DESCRIPTION OF THE EMBODIMENTS

Hereinafter, the present invention will be described through the embodiments of the invention. However, the embodiments described below are not to limit the claimed inventions. Also, all of all of combinations of features described in the embodiments are not necessarily essential for means for solving the problem of the invention.

FIG. 1is a plan view illustrating an exemplary semiconductor device100in accordance with Example 1. The semiconductor device100is a semiconductor chip including a semiconductor substrate on which an active region102and an outer region105are formed. The semiconductor substrate has a first conductivity type. In the present example, the first conductivity type is described as N type while the second conductivity type as P type. However, the first conductivity type may be P type while the second conductivity type may be N type.

The active region102is a region which an electric current flows when the semiconductor device100is driven. The active region102is provided with a plurality of transistor sections70and a diode section80. Also, the active region102may include a temperature sensor90adjacent to the transistor section70or the diode section80.

The transistor section70includes a transistor such as an IGBT (Insulated Gate Bipolar Transistor). In an example, the transistor section70includes a plurality of transistors arranged in a rectangular shape. The plurality of transistors included in the transistor section70are connected to one another in electrically parallel. The transistor section70has a gate terminal, an emitter terminal and a collector terminal, and the predetermined potential is applied to each terminal, respectively. The transistor section70of the present example is formed to cover a surrounding area of the diode section80.

The diode section80includes a diode such as an FWD (Free Wheel Diode). In an example, the diode section80includes a plurality of diodes arranged in a rectangular shape. The plurality of diodes included in the diode section80are provided in electrically parallel to one another. The diode section80has an emitter (or anode) terminal and a cathode terminal, and the predetermined potential is applied to each terminal, respectively.

The temperature sensor90is formed above a front surface of semiconductor substrate10and detects signals in response to the temperature of the semiconductor device100. In an example, the temperature sensor90includes a PN diode. Preferably, the temperature sensor90is provided in the vicinity of the transistor section70to detect the temperature of the transistor section70. However, the temperature sensor90may also be provided in the vicinity of the diode section80.

The outer region105is provided outside of the active region102. Outside of the active region102refers to a region which is not surrounded by the active region102and is closer to an end portion of the semiconductor substrate10than to the center of the active region102. The outer region105may surround the active region102. The outer region105of the present example includes a gate pad106, a sensing unit107and a temperature detecting section108. Also, a region such as an edge termination region109may be provided more outside of the outer region105.

The gate pad106is connected to the transistor section70via the gate runner46. The gate pad106sets a gate of the transistor section70to a gate potential. The gate of the transistor section70refers to, for example, a gate conductive section within the gate trench section40.

The gate runner46is formed to surround an area of the transistor section70. In particular, the gate runner46is formed in a boundary region between the transistor section70and the diode section80, preferably. The gate runner46is formed from a conductive material such as polysilicon. The gate runner46is connected to the plurality of transistor sections70as well as the gate pad106.

The sensing unit107detects an electric current flowing the transistor section70. In an example, an electric current flowing the sensing unit107is in proportion to a main current flowing the transistor section70and is smaller than the main current. For example, the sensing unit107is connected to the transistor section70in parallel and the same gate potential is input to the sensing unit107as the transistor section70. Note that the sensing unit107may be connected to a resistor having a greater resistivity than a resistor connected to the transistor section70.

The temperature detecting section108is an exemplary temperature sensor terminal wired to the temperature sensor90. Signals are input to the temperature detecting section108which are detected by the temperature sensor90and indicating the temperature of the semiconductor device100. The temperature detecting section108may output the input signals to outside. Also, the semiconductor device100may be controlled to be driven based on the temperature detected by the temperature sensor90. Note that the wiring of the temperature sensor90of the present example partially intersects the gate runner46in some regions. In such a case, in an example, the gate runner46is formed on an insulating film such as a thermally oxidized film on a front surface of the semiconductor substrate while the wiring of the temperature sensor90is formed via an insulating film such as an interlayer insulating film above the gate runner46such that wiring of the gate runner46and the temperature sensor90stereoscopically intersects.

The edge termination region109reduces concentration of the electric field at the front surface side of the semiconductor substrate. The edge termination region109has, for example, a guard ring, a field plate, an RESURF (reduced surface field) and a structure of a combination thereof.

FIG. 2is an exemplary plan view illustrating the semiconductor device100in accordance with Example 1 in more detail. The semiconductor device100of the present example includes, at a front surface side of the chip, a gate runner46, an emitter electrode52, a gate trench section40, a dummy trench section30, an emitter trench section60, a well region17, an emitter region12, a base region14, a contact region15and contact holes54,55,56,57.

The gate trench section40, the dummy trench section30, the emitter trench section60, the well region17, the emitter region12, the base region14and the contact region15are formed inside of the semiconductor substrate at the front surface side. Also, the emitter electrode52and the gate runner46are provided above the front surface of the semiconductor substrate. Note that although an interlayer insulating film is formed between the emitter electrode52and the gate runner46, and the front surface of the semiconductor substrate, it is omitted inFIG. 1.

The contact holes54,55,56,57are formed to penetrate the interlayer insulating film formed above the semiconductor substrate. Positioning of the contact holes54,55,56,57are not limited to the present example.

The emitter electrode52contacts the semiconductor substrate through the contact holes54,56,57. The emitter electrode52is formed from a metal-containing material. In an example, at least some regions of the emitter electrode52are formed from aluminum-containing metal. The emitter electrode52may include a region formed of a tungsten-containing material. The emitter electrode52of the present example is provided to correspond to the transistor section70and the diode section80, respectively.

The transistor section70refers to a region performing transistor operations.

In the present drawing, although the end of the transistor section70is shown as an end of the emitter electrode52formed on the region performing the transistor operations for convenience, it can be changed as appropriate.

The diode section80refers to a region such as an FWD performing diode operations. In the present drawing, although the end of the diode section80is shown as an end of the emitter electrode52formed on the region performing the diode operations for convenience, it can be changed as appropriate.

The gate runner46is electrically connected to a polysilicon layer45underlying the gate runner46through the contact hole55. The gate runner46of the present example is connected to the semiconductor substrate via the polysilicon layer45. The gate runner46is formed from a metal-containing material, as is the case with the emitter electrode52.

The dummy trench section30is formed to extend in a predetermined extending direction on the front surface of the semiconductor substrate. One or more dummy trench sections30are arranged in a region of the transistor section70along a predetermined arrangement direction at a predetermined interval against the gate trench section40. The shape of the dummy trench section30of the present example is a loop type shape having a curved shape at both end portions.

The gate trench section40includes an opposing section41and a protruding section43. The opposing section41is formed to extend in the extending direction described above in an area in which it is opposing to the dummy trench section30. That is, the opposing section41is formed to be parallel to the dummy trench section30. The protruding section43is formed to further extend from the opposing section41in an area in which it is not opposing to the dummy trench section30. In the present example, two opposing sections41provided on both sides of the dummy trench section30are connected via one protruding section43. At least a portion of the protruding section43may have a curved shape. The gate trench section40of the present example has a loop type shape having the protruding section43formed at both ends thereof.

A polysilicon layer45is formed to connect the protruding section43and the gate runner46. The protruding section43of the present example includes a portion extending in a direction orthogonal to the opposing section41in a region most distant from the opposing section41. At the extending portion of the protruding section43, a polysilicon layer within the gate trench section40and the polysilicon layer45are connected. The polysilicon layer45is connected to the gate runner46via the contact hole55. The gate runner46is connected to the gate pad106. This allows a gate potential applied to the gate pad106from an external circuit or the like to be applied to the polysilicon layer within the gate trench section40via the gate runner46and the polysilicon layer45.

The gate trench sections40and the dummy trench sections30of the present example are arranged alternately in a predetermined arrangement direction. Also, each trench section may be arranged at a constant interval. However, the arrangement of each trench section is not limited to the example above. A plurality of gate trench sections40may be arranged between two dummy trench sections30. Also, the number of the gate trench sections40provided between respective dummy trench sections30may not be constant.

The contact hole55is formed in an interlayer insulating film of a lower portion of the gate runner46.

The emitter trench section60is provided in a region in which the diode section80is formed. The emitter trench section60may have both a loop type shape and a linear shape. Also, the emitter trench section60of the present example is provided to have a trench width corresponding to those of the dummy trench section30and the gate trench section40. However, the shape of the emitter trench section60may be changed as appropriate depending on the layout of the transistor section70and the diode section80.

The well region17is formed within a predetermined area from the region in which the gate runner46is provided. Also, the well region17is formed below the gate runner46. The well region17of the present example is formed to extend toward the transistor section70side and the diode section80side from the gate runner46. The well region17has a second conductivity type, unlike the semiconductor substrate, if the semiconductor substrate has the first conductivity type.

The contact region15on a front surface of the base region14is a region of the second conductivity type, having a higher impurity concentration than the base region14. The contact region15of the present example is of P+ type.

The emitter region12is selectively formed in the transistor section70at a portion of a front surface of the contact region15as a region of the first conductivity type having a higher impurity concentration than the semiconductor substrate. The emitter region12of the present example is of N+ type. Each of the contact region15and the emitter region12is formed to extend from one of the adjacent trench sections to the other. One or more contact regions15and one or more emitter regions12of the transistor section70are formed, in a region sandwiched by respective trench sections, to alternately expose along the extending direction of the trench section.

The contact hole54is formed above the emitter region12and the contact region15in the transistor section70. The contact hole54of the present example is formed across the emitter region12and the contact region15. The contact hole54may be formed to expose the entire front surface of the emitter regions12. Also, the contact hole54may be formed to also expose the entire front surface of the contact region15. However, the contact hole54is not formed in a region which corresponds to the base region14or the well region17.

Also, the contact hole54is formed above the base region14and the contact region15in the diode section80. In an example, the contact hole54of the transistor section70and the contact hole54of the diode section80have the same length in the extending direction of each trench section.

Note that in the diode section80the base region14may only include the base region14and omit the contact region15formed on the front surface thereof. This can inhibit, in the diode section80, an excessive injection of minority carriers into the drift region18.

The contact hole56is formed above the dummy trench section30in the transistor section70. The contact hole56connects the emitter electrode52to a dummy conductive section formed within the dummy trench section30.

The contact hole57is formed above the emitter trench section60in the diode section80. The contact hole57connects the emitter electrode52to a dummy conductive section formed within the emitter trench section60.

FIG. 3illustrates an exemplary cross section taken along a-a′ of the semiconductor device100in accordance with Example 1. The semiconductor device100of the present example includes a lifetime killer47and a lifetime killer48in a drift region18of a semiconductor substrate10. Note that in the present example an interlayer insulating film26is illustrated between a gate runner46and an emitter electrode52, and the semiconductor substrate10.

The lifetime killer47is formed at a front surface side of the semiconductor substrate10and used to adjust the lifetime of carriers. Forming the lifetime killer47can shorten the lifetime of carriers. The lifetime killer47is formed by irradiating ion or the like from the front surface side or the back surface side of the semiconductor substrate10. In an example, the lifetime killer47is formed by irradiating helium onto the semiconductor substrate10. The lifetime killer47of the present example is, for example, formed at the anode region side of the diode section80to reduce the lifetime of carriers at the anode region side. This results in the semiconductor device100reducing a tail current, which can reduce a reverse recovery loss Err.

The lifetime killer48is formed at the back surface side of the semiconductor substrate10to shorten the lifetime of carriers. The lifetime killer48is, for example, irradiated from the back surface side of the semiconductor substrate10. In an example, the lifetime killer48is formed by irradiating helium. For example, if a rated reverse voltage of the semiconductor device100is applied, the lifetime killer48is formed in a position not in contact with a depletion layer spreading from a boundary between the anode region and the n-type region of the semiconductor substrate10.

The semiconductor substrate10of the present example includes the lifetime killer47in at least some regions at the front surface side of the semiconductor substrate10and below the gate runner46. As used herein, below the gate runner46refers to a region, in a planar view, in which the gate runner46is formed and which is closer to the back surface of the semiconductor substrate10than the gate runner46is. Note that, as used herein, the planar view refers to a view from the front surface side to the back surface side of the semiconductor substrate10.

Also, the semiconductor substrate10may also include the lifetime killer47in at least some regions at the front surface side of the semiconductor substrate10and below the well region17. This can inhibit an excessive injection of minority carriers from the well region17of a high impurity concentration to the drift region18. As used herein, below the well region17refers to a region, in a planar view, in which the well region17is formed and which is closer to the back surface of the semiconductor substrate10than the well region17is. Also, the region in which the well region17is formed may refer to a region in the front surface of the semiconductor substrate10to which dopants are injected to form the well region17.

The collector region22is provided in at least some regions below the gate runner46. The collector region22may be provided in at least some regions below the well region17. The collector region22of the present example is provided in at least some regions below the gate runner46, which can isolate the transistor section70and the cathode region28. Therefore, the semiconductor device100can inhibit a malfunction of the transistor section70affected by the cathode region28.

Comparative Example 1

FIG. 4is a plan view illustrating a configuration of the semiconductor device500in accordance with Comparative Example 1. The semiconductor device500of the present example comprises transistor sections570and diode sections580arranged alternately. Configurations shown by labels in common with the semiconductor device100have features similar to those of the semiconductor device100. The semiconductor device500comprises a gate runner546to connect the gate terminal103and the transistor section570.

The gate runner546is wired to surround the transistor sections570and the diode sections580arranged alternately. The gate runner546of the present example is provided between the transistor sections570and between the diode sections580. Also, the gate runner546is formed to surround the transistor section570and the diode section580collectively. That is, the gate runner546of the present example is not provided in a boundary region between the transistor section570and the diode section580.

FIG. 5illustrates a helium irradiation region of the semiconductor device500in accordance with Comparative Example 1. Regions shown by dashed lines are irradiated with helium ion at the front surface side of the semiconductor substrate. Helium is irradiated mainly to the diode section580and to the surrounding region of the diode section580. Also, although the front surface side of the transistor section570needs not to be irradiated with helium, a boundary region between the transistor section570and the diode section580may be irradiated with helium to prevent the semiconductor device500from malfunction. Therefore, in the semiconductor device500of the present example, the transistor section570is also irradiated with helium.

FIG. 6is a plan view illustrating the semiconductor device500in accordance with Comparative Example 1 in more detail. The semiconductor device500of the present example comprises, at a front surface side of a chip, a gate runner546, an emitter electrode552, a gate trench section540, a dummy trench section530, an emitter trench section560, a well region517, an emitter region512, a base region514, a contact region515and contact holes554,555,556,557.

The semiconductor device500includes a transistor section570and a diode section580arranged in an arrangement direction. Therefore, a boundary between the diode section580and the transistor section570is not provided with the gate runner546. As the gate runner546is not provided between the transistor section570and the diode section580, the transistor section570and the diode section580are formed to be adjacent to each other.

FIG. 7illustrates an exemplary cross section taken along b-b′ of the semiconductor device500in accordance with Comparative Example 1. The semiconductor device500comprises a dummy trench section530, a gate trench section540, an emitter trench section560, a collector region522, a cathode region582formed in a semiconductor substrate510. Also, the semiconductor device500includes a collector electrode524formed below the semiconductor substrate510and an interlayer insulating film526and an emitter electrode552formed above the semiconductor substrate510. Note that the gate trench section540is connected to a gate terminal551while the dummy trench section530and the emitter trench section560are connected to an emitter terminal553.

The semiconductor device500includes a lifetime killer547and a lifetime killer548formed in a drift region518of the semiconductor substrate510. The lifetime killer547is provided at the front surface side of the semiconductor substrate510to correspond to the diode section580. The lifetime killer548is provided at the back surface side of the semiconductor substrate510to correspond to the transistor section570and the diode section580.

The semiconductor device500of the present example does not include the gate runner546between the transistor section570and the diode section580. The semiconductor device500also includes the lifetime killer547provided at the front surface side of the semiconductor substrate510and at the transistor section570side to prevent malfunction. The lifetime killer547provided at the transistor section570side of semiconductor device500may deteriorate properties.

FIG. 8illustrates an exemplary configuration of a semiconductor device100in accordance with Example 2. A semiconductor device100of the present example comprises two diode sections80a,80bprovided at an end portion of an active region102. The semiconductor device100of the present example shows an exemplary arrangement of a transistor section70, a diode section80and a temperature sensor90, of which an area or the like of each region may be changed as appropriate depending on required properties or the like. For example, the sizes of the transistor section70and the diode section80are determined to have a predetermined area ratio.

The diode section80ais provided at one end of the active region102. The diode section80bis provided at the other end different from the one end of the active region102at which the diode section80ais provided. The diode section80bof the present example is provided at an end portion of the active region102opposing to the one end at which the diode section80ais provided. In this way, the diode section80is arranged at the end portion of the active region102not to contact the transistor section70around the one end of the active region102. Therefore, the transistor section70is less affected by helium with which the diode section80is irradiated.

The transistor section70is formed in a region in which the diode sections80a,80bare not formed in the active region102. In an example, the transistor section70is arranged to be divided into five regions. The transistor section70is provided to be surrounded by the gate runner46, respectively. Therefore, the gate runner46is necessarily formed at the boundary between the transistor section70and the diode section80. This can inhibit deterioration of the properties of the transistor section70.

The temperature sensor90is formed to be surrounded by the transistor section70. More specifically, the temperature sensor90is provided in the vicinity of the center of the active region102inside the transistor section70. This results in the temperature sensor90measuring the temperature in a region of the transistor section70which is most likely subject to a high temperature. However, the temperature sensor90may be provided in a region other than the center of the active region102and in the vicinity of the transistor section70. Also, the temperature sensor90may be provided in the vicinity of the diode section80. The temperature sensor90of the present example is arranged between the diode section80aand the diode section80b.

FIG. 9illustrates an exemplary configuration of a semiconductor device100in accordance with Example 3. The semiconductor device100of the present example shows an exemplary arrangement of a transistor section70, a diode section80and a temperature sensor90, of which an area or the like of each region may be changed as appropriate depending on required properties or the like.

The diode section80is formed at an end portion of an active region102. In particular, the diode section80of the present example is formed at a corner portion of the active region102. That is, the diode section80is arranged to have more regions contact the end portion of the active region102to reduce the boundary region between the diode section80and the transistor section70. Therefore, the transistor section70is less affected by helium with which the diode section80is irradiated.

The transistor section70is formed in a region in which the diode section80is not formed in the active region102. The transistor section70is provided to be surrounded by the gate runner46, respectively. Therefore, the gate runner46is necessarily formed at the boundary between the transistor section70and the diode section80. This can inhibit deterioration of the properties of the transistor section70. In particular, as the diode section80of the present example is provided at the corner portion of the active region102, the boundary region includes only two sides which contact the transistor section70. Therefore, the transistor section70is less affected by irradiation of helium.

The temperature sensor90is arranged depending on the position of the diode section80. In an example, the temperature sensor90is provided such that its wiring is positioned between the transistor section70and the diode section80. This results in the transistor section70having a larger area. Also, in the temperature sensor90of the present example, wiring connecting the temperature sensor90and a temperature detecting section108is provided to be adjacent to one side of the diode section80. In this way, an invalid region is arranged in a surrounding area of the diode section80which does originally not operate as the transistor section70such that the transistor section70is further less affected by helium with which the diode section80is irradiated.

FIG. 10illustrates an exemplary configuration of a semiconductor device100in accordance with Example 4. The semiconductor device100of the present example shows an exemplary arrangement of a transistor section70, a diode section80and a temperature sensor90, of which an area or the like of each region may be changed as appropriate depending on required properties or the like.

The transistor section70is formed at the center of the active region102. The center of the active region102may not exactly be a center of the active region102, but the arrangement may include the transistor section70around which other regions such as the diode section80are formed. Also, the transistor section70in which the temperature sensor90is arranged at the center includes a concave portion through which wiring is provided to connect the temperature sensor90and a temperature detecting section108. The transistor section70of the present example includes a gate runner46at the boundary between the temperature sensor90and the wiring. That is, the gate runner46is arranged along the concave portion of the transistor section70.

The diode section80is formed to surround the transistor section70. Although the diode section80of the present example is formed to have a uniform width, it may also have each side of varied widths. For example, the width of the diode section80is adjusted such that the transistor section70and the diode section80have a particular area ratio. Also, the diode section80includes an isolation region S to provide wiring for the temperature sensor90.

FIG. 11illustrates an exemplary cross section of the semiconductor device100. In particular, the figure shows a cross section of a region in which the temperature sensor90is formed.

The temperature sensor90includes a PN diode. The temperature sensor90utilizes the current-voltage properties of the PN diode varied depending on the temperature to detect the temperature of the semiconductor device100. The temperature sensor90is arranged, for example, above the semiconductor substrate10via a gate insulating film49. More specifically, the temperature sensor90is formed above the well region17. In this way, the temperature sensor90is formed above the well region17which is an invalid region not to operate as the transistor section70, which allows an arrangement without narrowing the region of the transistor section70. The temperature sensor90of the present example includes a first conductivity type region91, a second conductivity type region92, a first connection portion93, a second connection portion94and an insulating film95.

The first conductivity type region91and the second conductivity type region92configure the PN diode. For example, the first conductivity type region91is formed of N type semiconductor while the second conductivity type region92is formed of P type semiconductor.

The first connection portion93and the second connection portion94are electrically connected to the first conductivity type region91and the second conductivity type region92, respectively. Also, the first connection portion93and the second connection portion94are electrically connected to the temperature detecting section108through wiring.

The insulating film95insulates the first connection portion93and the second connection portion94to prevent them from being electrically connected to a region other than the first conductivity type region91and the second conductivity type region92, which needs not to be connected.

FIG. 12illustrates an exemplary cross section taken along a-a′ of a semiconductor device100in accordance with Example 5. The semiconductor device100of the present example shows an exemplary arrangement of a lifetime killer47and a collector region22. Also, the semiconductor device100of the present example illustrates the cross section taken along a-a′ ofFIG. 2.

In an example, the lifetime killer47is provided in the entire region below a gate runner46at a front surface side of the semiconductor substrate10. The semiconductor device100of the present example includes the lifetime killer47formed in the entire region below the gate runner46, but not formed in a region at the transistor section70side, which inhibits deterioration of properties of the transistor section70. Also, the lifetime killer47may be formed in the entire region below the well region17. Also in this case, the lifetime killer47may not be formed in a region at the transistor section70side.

The collector region22is provided in the entire region below the gate runner46. The collector region22of the present example is formed in the entire region below the gate runner46, but is not provided in a region at the diode section80side. That is, the transistor section70and the cathode region28can be isolated without affecting the region of the diode section80. Also, the semiconductor device100can inhibit a malfunction of the transistor section70affected by the cathode region28.

The collector region22may also be provided in the entire region below the well region17. Also in this case, the collector region22may not be provided in a region at the diode section80side.

The collector region22may be formed beyond a position on the back surface side corresponding to the end of the emitter electrode52formed in the diode section80. This can inhibit influences of carriers of the diode section80which interrupt the transistor section70side.

FIG. 13illustrates an exemplary cross section taken along a-a′ of a semiconductor device100in accordance with Example 6. The semiconductor device100of the present example shows an exemplary arrangement of a lifetime killer47and a collector region22. Also, the semiconductor device100of the present example illustrates the cross section taken along a-a′ ofFIG. 2.

In an example, the lifetime killer47is provided in at least a portion at the transistor section70side. The lifetime killer47of the present example is also provided in the entire region below the gate runner46at a front surface side of the semiconductor substrate10. That is, the lifetime killer47of the present example is formed to extend from the diode section80side to the transistor section70. The semiconductor device100of the present example is provided with the lifetime killer47extending to the transistor section70side, which can inhibit a malfunction of the transistor section70affected by the cathode region28.

The collector region22is provided in at least a portion of the diode section80side. Also, the collector region22is provided in the entire region below the gate runner46. The cathode region28is not formed below the gate runner46. That is, the cathode region28of the present example is formed more apart from the transistor section70side than in the semiconductor device100in accordance with Example 5. This further facilitates the semiconductor device100of the present example to inhibit a malfunction of the transistor section70affected by the cathode region28. Also, the collector region22may be provided in at least a portion of the diode section80side and in the entire region below the well region17.

Note that a position of an end of the lifetime killer47at the transistor section70side and a position of an end of the collector region22at the diode section80side can be arranged as appropriate in relation to the configuration in the foregoing. For example, the lifetime killer47may be formed such that its end at the transistor section70side is positioned in a portion below the gate runner46or the well region17, as shown inFIG. 3. In addition, the collector region22may extend such that its end at the diode section80side is positioned in at least a portion of the diode section80side, as shown inFIG. 13. This results in the lifetime killer47sufficiently less affecting properties of the transistor section70.

In addition, for example, the lifetime killer47may be formed to extend beyond from below the gate runner46or the well region17such that its end at the transistor section70side is positioned in a portion of the transistor section70, as shown inFIG. 13. In addition, the collector region22may be formed such that its end at the diode section80side is positioned in a portion below the gate runner46or the well region17, as shown inFIG. 3. This can inhibit minority carriers accumulated in a lower portion of the gate runner46or a lower portion of the well region17from the diode section80from affecting the transistor section70side.

FIG. 14is a plan view illustrating an exemplary semiconductor device100in accordance with Example 7. The semiconductor device100of the present example has a structure in which a polysilicon layer embedded inside a gate trench section40via a gate insulating film is directly connected to the gate runner46.

The transistor section70includes a dummy trench section30having a loop type shape and the gate trench section40having a linear shape. However, whether the dummy trench section30and the gate trench section40have a loop type shape or a linear shape, respectively, may be changed as appropriate.

The diode section80includes, as is the case with Example 1, an emitter trench section60having a loop type shape and a linear shape to correspond to a trench width of the dummy trench section30and the gate trench section40. However, the shape of the emitter trench section60may be changed as appropriate depending on the layout of the transistor section70and the diode section80.

The gate runner46is provided between the transistor section70and the diode section80. The gate runner46of the present example is formed to have a linear shape.

The gate trench section40includes a region formed in parallel to an extending direction of gate runner46and a region formed in parallel to an extending direction of the dummy trench section30. At least a portion of the gate trench section40is formed to be connected to the gate runner46via a contact hole55. At least a portion of the gate trench section40may be formed below the gate runner46.

FIG. 15illustrates an exemplary cross section taken along c-c′ of the semiconductor device100in accordance with Example 7. The semiconductor device100of the present example includes the gate runner46between the transistor section70and the diode section80, which can inhibit a malfunction of the transistor section70affected by the cathode region28.

In an example, the lifetime killer47is provided in at least a portion at the transistor section70side. The lifetime killer47of the present example is also provided in the entire region below the gate runner46at a front surface side of the semiconductor substrate10. That is, the lifetime killer47of the present example is formed to extend from the diode section80side to the transistor section70. The semiconductor device100of the present example is provided with the lifetime killer47extending to the transistor section70side, which can inhibit a malfunction of the transistor section70affected by the cathode region28.

Note that even if the gate trench section40is directly connected to the gate runner46as in the present example, the relationship of the lifetime killer47and the gate runner46may be set as appropriate, as shown in other Examples.

The collector region22may be formed beyond a position on the back surface side corresponding to the end of the emitter electrode52formed in the diode section80. This can inhibit influences of carriers of the diode section80which interrupt the transistor section70side.

FIG. 16is a plan view illustrating an exemplary semiconductor device100in accordance with Example 8.FIG. 17illustrates an exemplary cross section taken along d-d′ of the semiconductor device100in accordance with Example 8. The semiconductor device100of the present example further comprises an accumulating layer16, in addition to the configuration of the semiconductor device100in accordance with Example 1.

The accumulating layer16is formed at the back surface side of the base region14. The accumulating layer16is formed to have a higher concentration than an impurity concentration of the semiconductor substrate10. More specifically, the accumulating layer16has a higher impurity concentration than an impurity concentration of the drift region18. The accumulating layer16is formed between the adjacent trenches. In an example, the accumulating layer16has an impurity concentration of equal to or greater than 1E16 cm−3, and equal to or less than 1E18 cm−3. Note that E means a power of 10, and for example, 1E16 cm−3means 1×1016cm−3. For example, the accumulating layer16is formed by injecting N type impurities such as phosphorous from the front surface side of the semiconductor substrate10. Providing the accumulating layer16inhibits holes injected from the collector region22to the drift region18in an ON state from flowing into the base region14, which enhances the injection facilitation effect of electrons from the emitter region12to the base region14. This results in the semiconductor device100having a reduced ON voltage.

Although the accumulating layer16of the present example is formed in the transistor section70, it is not formed in the diode section80. Also, the accumulating layer16is formed, in a planar view, to correspond to the region in which the contact hole54is formed. The accumulating layer16of the present example is formed inside the region in which the contact hole54is formed in the extending direction of the trench section included in the transistor section70. This results in the semiconductor device100of the present example enhancing the carrier draw out effect of the accumulating layer16, which inhibits decreases in capability. Also, preferably, at least a portion of an end portion of a trench section of the transistor section70is formed in the well region17. This enhances the breakdown voltage of the semiconductor device100.

FIG. 18is a plan view illustrating an exemplary semiconductor device100in accordance with Example 9.FIG. 19illustrates an exemplary cross section taken along d-d′ of the semiconductor device100in accordance with Example 9. The semiconductor device100of the present example further comprises an accumulating layer16, in addition to the configuration of the semiconductor device100in accordance with Example 1.

The accumulating layer16of the present example is formed in both of the transistor section70and the diode section80. However, the accumulating layer16is not formed in the well region17. That is, the accumulating layer16is not formed in the region in which the gate runner46is formed. Also, the accumulating layer16is formed, in a planar view, to correspond to the region in which the contact hole54is formed. The contact hole54at the transistor section70side is formed, in a planar view, to be apart from the well region17. Also, the contact hole54at the diode section80side is formed, in a planar view, to be apart from the well region17.

The accumulating layer16of the present example is formed inside the region in which the contact hole54is formed in the extending direction of the trench section included in the transistor section70. Also, similarly in the diode section80, the accumulating layer16is formed inside the region in which the contact hole54is formed in the extending direction of the trench section included in the diode section80. This results in the semiconductor device100of the present example enhancing the carrier draw out effect of the accumulating layer16, which inhibits decreases in resistance. Note that the lifetime killer47at the front surface side may be omitted if the accumulating layer16is formed in the diode section80.

FIG. 20is a plan view illustrating an exemplary semiconductor device100in accordance with Example 10.FIG. 21illustrates an exemplary cross section taken along d-d′ of the semiconductor device100in accordance with Example 10. The semiconductor device100of the present example further comprises an accumulating layer16, in addition to the configuration of the semiconductor device100in accordance with Example 1.

The accumulating layer16of the present example is formed in both of the transistor section70and the diode section80. Furthermore, at least a portion of the accumulating layer16of the present example is formed in the well region17. That is, the accumulating layer16is also formed in the region in which the gate runner46is formed. Therefore, the accumulating layer16of the present example is formed in the region in which the transistor section70, the diode section80and the gate runner46are formed. Referring now to the cross section view, the accumulating layer formed in the well region17is indicated as an accumulating layer16awhile the accumulating layer formed in a region other than the well region17is indicated as an accumulating layer16b. The accumulating layer16bis formed in the base region14. The accumulating layer16bis, as is the case with the accumulating layer16of Examples 8 and 9, a high concentration layer of N type. The accumulating layer16amay not be of N type, unlike the accumulating layer16b. That is, although the accumulating layer16amay be formed through the same processes as the accumulating layer16b, it is formed in the well region17and thus it may remain P type. Also, the accumulating layer16aof the well region17may include an impurity of N type. The chemical concentration of N type impurities in the well region17is lower than the chemical concentration of P type impurities in the well region17. This results in the semiconductor device100inhibiting decreases in the breakdown voltage and resistance. Note that the lifetime killer47at the front surface side may be omitted if the accumulating layer16is formed in the diode section80.

FIG. 22illustrates the relationship between an ON voltage Von (V) and a turn off loss Eoff (mJ). In the semiconductor device100in accordance with Example 1, the turn off loss Eoff (mJ) is reduced compared to the semiconductor device500in accordance with Comparative Example 1. This results from the diode section80provided at the center, which reduces a region for introducing the lifetime killer at the front surface of the transistor section70, thereby improving the tradeoff between the ON voltage Von (V) and the turn off loss Eoff (mJ).

EXPLANATION OF REFERENCES