Method of making a capacitor with standard self-aligned gate process

A method of manufacturing a semiconductor device is disclosed wherein a matched capacitor having a relatively high capacitance is formed in the structure of a linear MOS device. The method utilizes the standard procedure for manufacturing MOS devices which includes two separate mask steps for forming contact openings to a field effect transistor. During the first mask step, the opening for the upper plate contact of the capacitor is fully etched while the opening for the lower plate contact is only partially etched. During the second mask step, the opening for the lower plate contact of the capacitor is fully etched to the lower plate. In this manner the existing standard procedure may be used without the addition of nonstandard mask and diffusion steps.

The present invention relates to MOS integrated circuit devices having 
integrally formed capacitors. 
BACKGROUND OF THE INVENTION 
One of the standard fabrication processes for making MOS integrated circuit 
devices utilizes a self-aligning gate process when forming the associated 
source and drain regions. This process, which is disclosed in U.S. Pat. 
No. 3,472,712 which issued Oct. 14, 1969 to Bower, includes the formation 
of a thin layer of electrically insulating gate oxide on the planar 
surface of a semiconductor body, the formation of a gate on the insulating 
material, and the selective implanting of a doping impurity thereby 
informing the source and drain regions using the gate itself as a mask. 
After forming the source and drain regions and adding a layer of nitride 
and a layer of borophosphosilicate glass (BPSG), a two step masking 
opeation is performed to form the contact openings. The first masking step 
forms openings through the BPSG. The second masking step extends the 
openings through the nitride and gate oxide layers so that the surface of 
the semiconductor body is exposed. The two step masking process is a 
standard one for many manufacturers because it greatly reduces the chance 
occurrence of a short due to the presence of foreign matter on the 
photolithographic plate during the masking process. 
In self-aligning gate processes, there is no heavy doping under the gate. 
Therefore, a capacitor having a dielectric formed of this material is 
necessarily non-linear. In such processes where a capacitor is formed 
along with a transistor, the capacitor typically includes a lightly doped 
substrate electrode and an upper polysilicon electrode. Because the 
lightly doped substrate electrode can be depleted by the voltage on the 
upper polysilicon electrode, the capacitor is highly nonlinear and the 
effective electrical separation between the electrodes is not constant. 
This renders the capacitor unsuitable for precision measurement 
applications such as analog to digital converters. 
When including a matched capacitor in the structure of a linear CMOS device 
of either the silicon on insulator(SOI) type, or bulk silicon type, the 
standard fabrication process must be modified to include an extra mask 
step and an extra diffusion. That is, the substrate electrode, or 
capacitor plate, must be heavily doped prior to forming the upper 
polysilicon electrode which is formed at the same time the gate is formed. 
On the other hand, when dealing with a CMOS device of the bulk silicon 
type, the standard fabrication process may be modified somewhat 
differently. In this case the two plates of the capacitor are formed of 
polysilicon and have a thin layer of oxide interposed between them. The 
structure is arranged on an area of isoplanar silicon dioxide. In this 
case the standard fabrication process must include an additional step to 
form a second layer of polysilicon and the associated photoresist mask. 
What is needed is a method of forming a linear capacitor having high 
capacitance per unit area utilizing the standard fabrication process 
without the need for additional process steps. The present invention 
achieves this by taking advantage of the existing procedure whereby two 
separate mask steps are used to form the contact openings of the 
transistor. 
SUMMARY OF THE INVENTION 
According to the present invention a method of making a semiconductor 
capacitor device is provided comprising the following steps. A 
semiconducting region of one conductivity type is formed having a planar 
surface and a layer of dielectric material is formed on the planar 
surface. First and second spaced apart openings are formed partially 
through the layer of dielectric material over the semiconducting region. 
Then the second opening is extended completely through the remainder of 
the layer of dielectric material to expose a portion of the semiconducting 
region. An electrically conductive first electrode is formed in the first 
opening and an electrically conductive second electrode is formed in the 
second opening in ohmic contact with the exposed portion of the 
semiconducting region.

DESCRIPTION OF THE PREFERRED EMBODIMENT 
In the following description and as shown in FIGS. 1 through 8, specific P 
and N type conductivity materials are indicated. These indications are by 
way of example and shall not be deemed to limit the teachings of the 
present invention. It will be understood that devices having opposite P 
and N arrangements are considered equivalent in all pertinent respects to 
the devices described herein. 
There is shown in FIGS. 1 through 6 an integrated circuit device 2 having a 
semiconductor body 4 of P type conductivity material. A pair of regions, 
indicated at 6 and 8 in FIG. 1, define the sites for forming a linear MOS 
transistor 10 and a matched capacitor 12 respectively. A relatively thin 
layer 30 of electrically insulating material, such as silicon oxide, is 
formed on a planar surface 22 of the body 4 as shown in FIG. 2. A gate 24 
is then formed on the layer 20 and associated source and drain regions 26 
and 28 respectively are formed utilizing the self aligning gate process 
referred to above. The forming of the layer 20, gate 24, source region 26, 
and drain region 28 is accomplished using processes that are well known by 
those skilled in the art and therefore will not be described here. 
Typically, the source and drain regions 26 and 28 are formed by ion 
implantation of suitable doping impurities to form the desired type 
conductivity material, which in the present case is N type conductivity. 
During the formation of the source and drain regions 26 and 28, a 
capacitor plate region 30 is also formed having N type conductivity. A 
layer 34 of silicon nitride is then formed on the entire device 2, as 
shown in FIG. 3. The combined thickness of the oxide layer 20 and nitride 
layer 34 is about 1800 angstroms, about 700 angstroms being the thickness 
of the oxide layer. A relatively thick layer 36, about 7000 angstroms, of 
BPSG is then formed over the nitride layer 34 in a manner that is well 
known in the art. 
A first layer 38 of photoresist is formed over the layer 36 of BPSG and 
four openings 40, 42, 44, and 46 are formed in the layer 38 over the 
regions 26, 28, and 30 as shown in FIG. 4. The process for forming of the 
layer 38 and the openings 40, 42, 44 and 46 is well known in the art and, 
therefore, will not be described here. The device 2 is then subjected to 
reactive ion etching so that the portions of the layer 36 of BPSG that are 
exposed through the openings 40, 42, 44, and 46 are etched down to the 
surface 30 of the layer 34 of nitride, thereby leaving openings 52, 54, 
56, and 58 in the layer 36 as indicated by dashed lines in FIG. 4. The 
layer 38 is removed in a manner that is well known in the art. The BPSG is 
then reflowed by subjecting it to about 900.degree. C. in a nitrogen 
environment for about one half hour. This causes the BPSG layer 36 to take 
the form shown in FIG. 5. 
A second layer 60 of photoresist is then formed over the layer 36 and the 
three openings 62, 64, and 66 are formed in the layer 60 within the 
openings 54, 56, and 58 respectively as shown in FIG. 5. The device 2 is 
again subjected to reactive ion etching so that the portions of the layers 
34 and 20 that lie directly below the openings 62, 64, and 66 are etched 
down to the planar surface 22 as indicated by the dashed lines in FIG. 5. 
The second layer 60 of photoresist is then removed and the metal contacts 
70, 72, 74, and 76 are formed in a manner well known in the art. 
The metal contact 72 is in ohmic contact with the surface of the heavily 
doped region 30 which forms one plate of the capacitor 12. The metal 
contact 70, being in intimate contact with the nitride layer 34, forms the 
other plate of the capacitor 12. The layers 20 and 34 of oxide and nitride 
disposed between these two plates and having a combined thickness of about 
1800 angstroms, form the dielectric of the capacitor 12. This structure 
yields a linear capacitor having a relatively high capacitance per unit 
area. 
The above description pertains to forming a linear capacitor in the 
structure of the linear MOS device 2 wherein the substrate in bulk 
silicon. However, the same teachings may be applied to MOS devices of the 
silicon-on-insulator (SOI) type as well. Such as SOI structure 78 is 
depicted in FIGS. 7 and 8 where an insulator 80 is shown having two 
epitaxial layers 82 and 84 formed thereon which define the sites for 
forming a linear MOS transistor and a matching capacitor. The layers 82 
and 84 are of P type conductivity material. A layer 86 of silicon oxide is 
formed over each of the layers 82 and 84 are shown in FIG. 8. A gate 88 is 
then formed on the layer 86 and associated source and drain regions 90 and 
92 of N type conductivity are implanted or diffused in a manner similar to 
those of the bulk silicon device described above. During the formation of 
the source and drain regions 90 and 92, a capacitor plate region 94 is 
also formed having N type conductivity. A layer 34 of nitride and a layer 
36 of BPSG are then formed over the entire device 78 in a manner similar 
to that described above for the bulk silicon device 2 and as depicted in 
FIGS. 3, 4, 5, and 6. Similarly, contact openings and contacts 70, 72, 74, 
and 76 are then formed. It will be understood that the manufacturing 
methods inherent in the structures shown in FIGS. 3, 4, 5, and 6 and 
described in relation to the device 2 may be applied to SOI devices as 
well as bulk silicon devices. 
One of the very important advantages realized by practicing the teachings 
of the present invention is that a matched capacitor having a relatively 
high capacitance may be made in the structure of a linear MOS device using 
the standard fabrication process without the addition of nonstandard mask 
and diffusion steps.