Data memory access collision manager, device and method

A non-volatile memory receives a data read request from a processing core of a plurality of processing cores. The read request is directed to a data partition of a non-volatile memory. The non-volatile memory determines whether to process the read request using read-while-write collision management. When it is determined to process the read request using read-while-write collision management, an address associated with the read request is stored in an address register of a set of registers associated with the processing core. Write operations directed to the data partition are suspended. A read operation associated with the read request is executed while the write operations are suspended and data responsive to the read operation is stored in one or more data registers of the set of registers. The data stored in the one or more data registers of the set of registers is provided to the processing core.

BACKGROUND

Technical Field

The present disclosure generally relates to managing data access collisions, such as collisions between a read request and a write request to a memory partition of a non-volatile memory array.

Description of the Related Art

A system on a chip (SoC) may typically have multiple processing cores accessing a non-volatile memory (NVM). The NVM may typically be divided into partitions, such as one or more partitions to store code for execution by the various processing cores, and one or more partitions to store data for use by the various processing cores. Collisions between memory accesses to data, such as read and write accesses to the NVM by different processing cores, may occur. In addition, the processing cores may include standard processing cores, which may share data with other processing cores, for example, through software data exchanges using a shared NVM, and secure processing cores which typically do not share data with other processing cores through software data exchanges using shared NVM.

BRIEF SUMMARY

In an embodiment, a device comprises a plurality of sets of registers, which, in operation, store addresses and data associated with data read requests received from respective processing cores of a plurality of processing cores, the data read requests being directed to a data partition of a non-volatile memory. The device includes control circuitry coupled to the plurality of sets of registers. The control circuitry, in a read-while-write collision management mode of operation, responds to a data read request received from one processing core of the plurality of processing cores and directed to the data partition by: storing an address associated with the data read request in an address register of one of the plurality of sets of registers associated with the one processing core; requesting suspension of write operations directed to the data partition and execution of a read operation associated with the read request while the write operations are suspended; storing data responsive to the read operation in one or more data registers of the one of the plurality of sets of registers; and providing the data stored in the one or more data registers of the one of the plurality of sets of registers to the one processing core.

In an embodiment, a system comprises a plurality of processing cores and a non-volatile memory coupled to the plurality of processing cores. The non-volatile memory has a data partition, a plurality of sets of registers, which, in operation, store addresses and data associated with data read requests received from respective processing cores of the plurality of processing cores, the data read requests being directed to a data partition of a non-volatile memory, and control circuitry coupled to the plurality of sets of registers and to the data partition. The control circuitry, in a read-while-write collision management mode of operation, responds to a data read request received from one processing core of the plurality of processing cores and directed to the data partition by: storing an address associated with the data read request in an address register of one of the plurality of sets of registers associated with the one processing core; suspending write operations directed to the data partition; executing a read operation associated with the read request while the write operations are suspended; storing data responsive to the read operation in one or more data registers of the one of the plurality of sets of registers; and providing the data stored in the one or more data registers of the one of the plurality of sets of registers to the one processing core. In an embodiment, the control circuitry, when the read-while-write collision management mode of operation is not enabled, responds to the data read request received from the one processing core of the plurality of processing cores and directed to the data partition by bypassing the one of the plurality of set of registers associated with the one processing core during processing of the read request.

In an embodiment, a method comprises receiving a data read request from a processing core of a plurality of processing cores, the data read request being directed to a data partition of a non-volatile memory; determining whether to process the data read request using read-while-write collision management: and responding to a determination to process the data read request using read-while-write collision management by: storing an address associated with the data read request in an address register of a set of registers associated with the processing core; suspending write operations directed to the data partition; executing a read operation associated with the read request while the write operations are suspended; storing data responsive to the read operation in one or more data registers of the set of registers; and providing the data stored in the one or more data registers of the set of registers to the processing core.

In an embodiment, a non-transitory computer-readable medium's contents cause a non-volatile memory controller to perform a method, the method comprising: receiving a data read request from a processing core of a plurality of processing cores, the data read request being directed to a data partition of a non-volatile memory; determining whether to process the data read request using read-while-write collision management: and responding to a determination to process the data read request using read-while-write collision management by: storing an address associated with the data read request in an address register of a set of registers associated with the processing core; suspending write operations directed to the data partition; executing a read operation associated with the read request while the write operations are suspended; storing data responsive to the read operation in one or more data registers of the set of registers; and providing the data stored in the one or more data registers of the set of registers to the processing core.

DETAILED DESCRIPTION

FIG.1is a functional block diagram of an embodiment of an electronic device or system100of the type to which the embodiments, which will be described, may apply. The system100comprises one or more processing cores or circuits102,104. As illustrated, the processing cores include one or more standard or host processing (or non-secure) cores102, and one or more secure processing cores104. The host processing cores102may perform software data swaps in shared non-volatile memory (NVM) with other processing cores, and the secure processing cores104typically do not perform software data swaps in shared NVM with other processing cores. The processing cores102,104may comprise, for example, one or more processors, a state machine, a microprocessor, a programmable logic circuit, discrete circuitry, logic gates, registers, etc., and various combinations thereof. The processing cores102,104may control overall operation of the system100, execution of application programs by the system100, secure operations performed by the system100, etc.

The system100includes one or more memories, such as one or more volatile memories106and one or more NVMs108, which may store, for example, all or part of instructions and data related to control of the system100, applications and operations performed by the system100, etc. One or more of the memories106,108may include a memory array (not shown), all or part of which may, in operation, selectively be shared by one or more processes executed by the system100, such as one or more processes executed by a host processor102and one or more processes executed by a secure processor104.

As illustrated, the non-volatile memories108are organized into one or more memory partitions110, which may comprise, for example, regions of a memory array, individual memory arrays, etc., of a non-volatile memory. The memory partitions110may be organized into code storage partitions110cproviding code storage and data storage partitions110dproviding data storage. The volatile memories106also may be organized into one or more partitions (not shown). As illustrated, the system100includes one or more volatile memory controllers112to control accesses to the volatile memories106by the processing cores102,104, and one or more non-volatile memory controllers114to control access to the non-volatile memories108by the processing cores102,104.

Conventionally, to avoid collisions between read and write data accesses of standard processing cores and secure processing cores to data storage partitions of a non-volatile memory (e.g., a read-while-write collision in a data storage partition110dbetween a write access by a secure processing core104and a read access by a host processing core102), separate data partitions of the non-volatile memory are assigned to the host processing cores and to the secure processing cores, which increases the cost in terms of non-volatile memory area, power consumption, etc.

The non-volatile memory controllers or circuits114, as illustrated, include one or more collision managers or circuits120, to manage collisions between data accesses to a partition110dby different processing cores, which facilitates the sharing of one or more data partitions110dby a host processing core102and a secure processing core104. As discussed in more detail below, the collusion managers120may, for example, manage a collision between a write request from one processing core (e.g., a host processing core102or a secure processing core104) to access one or more addresses in a data partition110d, and a read request from a second processing core (e.g., a host processing core102or a secure processing core104) to access one or more addresses in the data partition110d.

The system100may include one or more interfaces150(e.g., wireless communication interfaces, wired communication interfaces, controller interfaces, etc.), and other functional circuits160, which may include antennas, power supplies, sensors (e.g., image sensors, audio sensors, accelerometers, pressure sensors, temperature sensors, encoders, traction motor controllers, etc.), and a main bus system170. The main bus system170may include one or more data, address, power and/or control buses coupled to the various components of the system100. The system100also may include additional bus systems such as bus system172, which communicatively couples the volatile memories106and the volatile memory controllers112, and bus system174, which communicatively couples the non-volatile memories108and the non-volatile memory controllers114.

FIG.2is a functional block diagram of a system200illustrating an embodiment of a collision manager or circuitry220, which may be employed in the system100ofFIG.1. The system200includes a non-volatile memory208, a non-volatile memory controller214, and registers240, which may be included in the non-volatile memory controller214. As illustrated, the non-volatile memory208includes a read-while-write data partition RWW3210d, which, in operation, stores data (data inFIG.2) of a standard processing core (see processing core102ofFIG.1) and stores secure data (HSM data inFIG.2) of a secure processing core (see processing core104ofFIG.1). The non-volatile memory208may typically comprise additional memory partitions, as shown inFIG.3. The non-volatile memory208also includes a register interface282, a finite state machine284, and logic circuitry286coupled to the register interface282and the finite state machine284.

As illustrated, the non-volatile memory controller214includes write control circuitry288and read-control circuitry290. The read-control circuitry includes a register interface292, a finite state machine294, a plurality of transaction control circuits or transactors296, sequencing circuitry or a sequencer298and a security circuit299. The registers240, together with the register interface282, the finite state machine284, the logic circuitry286, the write control circuitry288and the read-control circuitry290, form the collision manager220.

The register interface292controls storage and retrieval of addresses, data, and control information (e.g., control flags) in the registers240. The finite state machines284,294control the timing of read operations performed using read-while-write collision management. The transactors296convert read request addresses to logical addresses of the non-volatile memory. The sequencer298sequences requests received from multiple transactors296. The security circuit299verifies that read access to the requested address is granted to the processing core from which the read request originated.

The write control circuitry288is coupled to a write memory interface of the non-volatile memory208, the read control circuitry290is coupled to a read memory interface of the non-volatile memory208, and the finite state machine294is coupled to the logic circuitry286. The write control circuitry288receives write requests though an interface, as illustrated inFIG.2, an Advanced eXtensible Interface (AXI). Similarly, the transactors296of the read control circuitry290receive read requests through interfaces, as illustrated, AXI interfaces. A read-intercept interface295intercepts read requests when read-while-write collision management is enabled. In general, when read-while-write collision management is enabled, reads are performed using the register interfaces282,292, with polling employed to indicate when the data is ready to be read from the registers. Examples of operation of the collision manager220when collision management is enabled are described in more detail below.

Embodiments of the system100ofFIG.1and of the system200ofFIG.2may include more components than illustrated, may include fewer components than illustrated, may combine illustrated components or split illustrated components, and various combinations thereof. For example, instead of having a separate non-volatile memory108and non-volatile memory controller114, the non-volatile memory108of system100may be modified to include a non-volatile memory controller114, which may be split into non-volatile memory write control circuitry (seeFIG.2) and non-volatile memory read control circuitry (seeFIG.2). In another example, the registers240may be incorporated into the non-volatile memory controller214. In another example, the read-intercept interface295may be omitted in some embodiments, and the transactors296configured provide the read requests to the registers240when read-while-write collision management is to be performed. The system100or the system200may comprise a system on a chip (SoC), discrete chips coupled together, etc., or various combinations thereof.

FIG.3is a conceptual diagram illustrating partitioning of a non-volatile memory308into partitions, such as the non-volatile memory108ofFIG.1, the non-volatile memory208ofFIG.2. As illustrated inFIG.3, the non-volatile memory308is partitioned into five memory partitions.

A first partition, RWW Partition 0, is a read-while-write partition having three 16 KB blocks reserved for special purposes, and a 32 KB block and two 64 KB blocks for accesses by secure processing cores (see secure processing core104ofFIG.1). A second partition, RWR Partition 1, is a read-while-read partition, details of the blocks of which are not shown inFIG.3. A third partition, RWW Partition 1, is a read-while-write partition having a low-address space with three 64 KB blocks and a 256K address space having three 256 KB blocks for shared accesses by standard processing cores (see processing core102ofFIG.1). A fourth partition, RWW Partition 2, also is a read-while-write partition having a low-address space with three 64 KB blocks and a 246K address space with three 256 KB blocks for shared accesses by standard processing cores (see processing core102ofFIG.1). Standard processing cores (e.g., processing cores102ofFIG.1) may perform software data swaps between the third partition RWW partition 1 and the fourth partition RWW partition 2.

A fifth partition, RWW partition 3 (e.g., RWW3210dofFIG.2), is a read-while-write partition shared by standard processing cores (see standard processing cores102ofFIG.1) and secure processing cores (see secure processing cores104ofFIG.1). The high address space of RWW partition 3 as illustrated includes four 16 KB blocks allocated to unsecure data, data 0, data 1, data 2 and data 3 (e.g., data accessible by a standard processor102), and two 16 KB blocks allocated to secure data HSM data 0 and HSM data 1. RWW partition 3 is designed as a data partition memory to be shared between the two groups of cores: secured data (HSM Data in theFIG.3) of secure cores (see cores104ofFIG.1) and non-secured data (data in theFIG.3) of non-secure cores (see cores102ofFIG.1). In an embodiment, content access for each group of cores is independent with respect to operations performed by a core of the other group. In other words, a core submitting a read request is unaware when the shared RWW partition 3 is already being subjected to a modify or write operation submitted by another core.

FIG.4is a conceptual diagram illustrating organization of a plurality of registers440that may be employed, for example, as the registers240of the collision manager220ofFIG.2. The plurality of registers440includes a first set of registers442aassociated with read requests of a standard processing core (e.g., a processing core102ofFIG.1, a second set of registers442bassociated with read requests of a secure processing core (e.g., a secure processing core104ofFIG.1), and one or more registers444to store control information associated with managing read-while-write data collisions, as illustrated flags F1 and F2, which may be used to control polling mechanisms and interrupts.

FIG.5illustrates an embodiment of a method500of determining whether to perform collision management processing of a read request or standard processing of a read in response to a read request received from a processing core and directed to a read-while-write data partition of a non-volatile memory, and will be described for convenience with reference toFIGS.1through4. The method500may be performed, for example, under control of the collision management circuitry120ofFIG.1or the collision management circuitry220ofFIG.2using a RWW partition, such as RWW3 partition210dofFIG.2.

The method500starts at502and proceeds to504. At504, the method500receives a request to read data stored at an address of a partition of a non-volatile memory. For example, a transactor296of read control circuitry290ofFIG.2may receive a read request from a processor, such as a standard processing core102or a secure processing core104ofFIG.1, via a bus system, such as the bus system170ofFIG.1, via an interface, such as an AXI interface, a read-intercept interface295, or various combinations thereof. In response to receiving a read request, the method500proceeds from504to506.

At506, the method500determines whether read-while-write collision management is enabled. This may be done, for example, by checking a flag or control signal indicating whether read-while-write collision management is enabled, by determining whether the data partition to which the read request is directed is shared by a standard processing core (e.g., a processing core102ofFIG.1) and a secure processing core (e.g., a secure processing core104ofFIG.1). When read-while-write collusion management is not enabled, the method500proceeds from506to510, where processing of the read request is performed without implementing read-while-write collision management. The method500proceeds from510to514, where the method500may terminate or may perform other processing, such as returning to504to wait for another read request.

When read-while-write collision management is enabled, the method proceeds from506to508. At508, the method500determines whether a write operation is in process. With reference toFIG.2, this may be done, for example, by checking a status of the non-volatile memory208, or a status of the write control circuitry288.

When the method500determines at508that a write operation is in process, the method500proceeds from508to512, where processing of the read request is performed using read-while-write collision management. The method500proceeds from512to514, where the method500may terminate or may perform other processing, such as returning to504to wait for another read request.

When the method500determines at508that a write operation is not in process, the method500proceeds from508to510, where processing of the read request is performed without implementing the read request using read-while-write collision management. The method500proceeds from510to514, where the method500may terminate or may perform other processing, such as returning to504to wait for another read request.

Embodiments of the method500ofFIG.5may not include all of the illustrated acts, may include additional acts, may combine acts, may split acts, and may perform acts in various orders. For example, acts506and508may be performed in various orders, or combined, act506may be omitted, for example, when collision management is enabled by default for a partition, etc. In another example, acts506,508and510may be omitted in some embodiments, or in some operational modes, and all read requests to a memory partition shared by secure and non-secure processing cores may be handled using collision management processing of the read request. In another example, additional collision management acts may be performed by the method500, such as acts related to read-while-read or write-while-write collusion management.

FIG.6illustrates an embodiment of a method600of processing a read request when read-while-write collision management is not enabled, or, in some embodiments, when read-while-write collision management is enabled, but a write operation is not in process when the read request is received. The method600will be described for convenience with reference toFIGS.1through5, and may be employed to perform the processing of act510inFIG.5. The method600may be performed, for example, under control of the read control circuitry290ofFIG.2using a RWW partition, such as RWW3 partition210dofFIG.2.

The method600starts at622and proceeds to624. At624, the method600receives a request to read data stored at an address of a partition of a non-volatile memory. For example, a transactor296of read control circuitry290ofFIG.2may receive a read request from a processor, such as a standard processing core102or a secure processing core104ofFIG.1, via a bus system, such as the bus system170ofFIG.1, via an interface, such as an AXI interface, a read-intercept interface, or various combinations thereof. In response to receiving a read request, the method600proceeds from624to226.

At626, the method600translates the read request in accordance with a read access protocol. For example, a read request received as an AXI transaction request may be translated into a non-volatile memory read request, for example, by a transactor296. The system address provided with the AXI transaction burst request may be translated into a logical address. The translation at626may be performed in a conventional manner. The method600proceeds from626to628.

At628, translated read requests are sequenced for processing by the non-volatile memory, for example, the sequencer298may sequence a burst request received from a transactor296for processing by the non-volatile memory208. The sequencing at628may be performed in a conventional manner. The method600proceeds from628to630.

At630, the method600determines whether the sequenced request is from a processing core authorized to access the requested data. For example, the security circuit299may verify the requested access is authorized. The determining whether a request is authorized at630may be performed in a conventional manner. When it is determined at630that the requested access is not authorized, the method600proceeds from630to631, where error or unauthorized access processing may be performed. When it is determined at630that the requested access is authorized, the method600proceeds from630to632.

At632, the method600asserts a read-enable signal and provides the translated request to the non-volatile memory, for example, via a read memory interface, which may be performed in a conventional manner. The method600proceeds from632to634.

At634, the method600waits for the data to be ready, for example, by waiting a programmed number of wait states. The waiting at634may be performed in a conventional manner. The method600proceeds from634to636.

At636, the method600provides the requested data to the processing core, for example, via an AXI interface, which may be performed in a conventional manner. The method600proceeds from636to638, where the method600may terminate or may perform other processing, such as returning to624to wait for another read request.

Embodiments of the method600ofFIG.6may not include all of the illustrated acts, may include additional acts, may combine acts, may split acts, and may perform acts in various orders. For example, act632may be split into multiple acts.

FIG.7illustrates an embodiment of a method700of processing a read request when read-while-write collision management is enabled. The method700will be described for convenience with reference toFIGS.1through6, and may be employed to perform the processing of act512inFIG.5. The method700may be performed, for example, under control of the read control circuitry290ofFIG.2using a RWW partition, such as RWW3 partition210dofFIG.2.

The method700starts at742and proceeds to744. At744, the method700intercepts a read request to read data stored in a partition of a non-volatile memory while a write request to the partition is being processed, and stores a memory address associated with the read request in a memory register. For example, a read intercept interface295or a transactor296of read control circuitry290ofFIG.2, may intercept a read request from a processor, such as a standard processing core102or a secure processing core104ofFIG.1, via a bus system, such as the bus system170ofFIG.1, via an interface, such as an AXI interface, a read-intercept interface, or various combinations thereof, and store an address associated with the read request in an address register of a set of registers, for example, with reference toFIG.4, the address register of the set of registers442a(e.g., in the case where the read request is from a standard processing core102) or the address register of the set of registers442b(e.g., in the case where the request is from a secure processing core104). The method700proceeds from744to746. In some embodiments, a processing core (e.g., processing core102or processing core104ofFIG.1), may write the address in the address register of the set of registers. For example, when all read requests directed to a partition are processed using read-while-write collision management.

At746, the method700requests suspension of the write operation to the partition, and proceeds to748to wait for an acknowledgment that the write operation has been suspended. For example, a read-intercept interface295or a transactor296may relay a suspend request to the finite state machine294, which generates a suspend signal provided to the non-volatile memory and to the logic circuitry286. When the write operation has been suspended, the non-volatile memory provides a suspend acknowledgement signal to the finite state machine294. Once the suspend acknowledgement signal is received, the method700proceeds from748to750.

At750, the method700provides an address associated with the read request for translation. For example, with reference toFIG.4, an address associated with the request stored in an address register of a set of registers442a(e.g., in the case where the request is from a standard processing core102) or442b(e.g., in the case where the request is from a secure processing core104) may be provided to a transactor296for translation. For example, a system address provided with the AXI transaction burst request may be translated in a logical address. The translation at750may be performed in a conventional manner. The method700proceeds from750to752.

At752, the translated read request is sequenced for processing by the non-volatile memory, for example, the sequencer298may sequence a burst request received from a transactor296. The sequencing at752may be performed in a conventional manner. The method700proceeds from752to754.

At754, the method700determines whether the sequenced request is from a processing core authorized to access the requested data. For example, the security circuit299may verify the requested access is authorized. The determining whether a request is authorized at754may be performed in a conventional manner. When it is determined at754that the requested access is not authorized, the method700proceeds from754to755, where error or unauthorized access processing may be performed. When it is determined at754that the requested access is authorized, the method700proceeds from754to756.

At756, the method700asserts a read-enable signal and provides the translated request to the non-volatile memory, for example, via a read memory interface, which may be performed in a conventional manner. The method700proceeds from756to758.

At758, the method700waits for the data to be ready, for example, by waiting a programmed number of wait states. The waiting at758may be performed in a conventional manner. The method700proceeds from758to760.

At760, the method700stores the requested data in the register interface. For example, a data register of a set of registers442a(e.g., in the case where the request is from a standard processing core102) or442b(e.g., in the case where the request is from a secure processing core104). For example, the non-volatile memory208may provide the data to a transactor296, which stores the data in the data register. The method700proceeds from760to762.

At762, the method700provides the requested data to the requesting processing core (e.g., a standard processing core102or secure processing core104). For example, the processing core may read the requested data from the data register. The method700proceeds from762to764.

At764, the method700resumes the suspended write operation to the partition. The method700proceeds from764to766, where the method700may terminate or may perform other processing, such as returning to744to wait for another read request.

Embodiments of the method700ofFIG.7may not include all of the illustrated acts, may include additional acts, may combine acts, may split acts, and may perform acts in various orders. For example, acts760,762and764may be performed in various orders, acts760and764may be performed in parallel, etc. In another example, the method700may be modified to include acts of responding to additional read requests received during processing of a current read request using read-while-write collision management by sending a decode error.

FIG.8is a flow diagram illustrating an embodiment of a method800of processing a read request when read-while-write collision management is enabled. The method800will be described for convenience with reference toFIGS.1through5, and may be employed to perform the processing of act512inFIG.5. The method800may be performed, for example, under control of the read control circuitry290ofFIG.2using a RWW partition, such as RWW3 partition210dofFIG.2.

The method800starts at802, where an address of a read request received from a processing core (e.g., processing core102or processing core104ofFIG.1) is written into an address register of a set of registers, for example, with reference toFIG.4, the address register of the set of registers442a(e.g., in the case where the read request is from a standard processing core102) or the address register of the set of registers442b(e.g., in the case where the request is from a secure processing core104). The address may be written into the address register by, for example, the requesting processing core, by a read-intercept interface, or by a transactor. The method800waits at802for an indication that the requested data has been loaded into one or more data registers of a set of registers associated with the data request, such as data registers of the set of registers442a(e.g., in the case where the read request is from a standard processing core102) or data registers of the set of registers442b(e.g., in the case where the request is from a secure processing core104). For example, the processing core may read the status of a polling mechanism or wait for an interrupt to provide the indication that the requested data is ready to be read (has been loaded into the registers.

In parallel with the waiting at802, the method800requests at810suspension of hardware write operations to the partition and waits for an acknowledgement that hardware write operations to the partition have been suspended. For example, with reference toFIG.2, the non-volatile memory controller214may request suspension of hardware write operations to the partition by the non-volatile memory208. When the acknowledgement of suspension of hardware write operations is received, the method800proceeds from810to812.

At812, the read operation is executed. For example, with reference toFIG.2, a transactor296may execute the read operation when a memory bus is free (e.g., based on arbitration logic of the non-volatile memory controller). The method proceeds from812to814.

At814, the requested data is received and stored into the one of the address registers associated with the memory read request. For example, with reference toFIG.2, a transactor296may receive the requested data from the non-volatile memory208after N wait states (e.g., a programmable number of wait states), and store the data in one or more data registers of a set of registers associated with the data request, such as data registers of the set of registers442a(e.g., in the case where the read request is from a standard processing core102) or data registers of the set of registers442b(e.g., in the case where the request is from a secure processing core104). With reference toFIG.2, the non-volatile memory, after providing the data, masks the done flag and the read-while-write error flag, and clears the suspension of hardware write operations to the partition. The done flag and the read-while write error flags are masked because the write operation is suspended, then resumed, so indicating a write operation is finished, or that a read-while-write error has occurred would be inaccurate. The non-volatile memory controller generates an interrupt, or sets the polling flag, to let the processor know the data is ready.

In response to the indication the data is ready, the method800proceeds from802to820, where the data is read from the one or more registers in the set of registers associated with the read request, and an interrupt status bit is cleared to indicate the data is ready to be read.

Embodiments of the method800ofFIG.8may not include all of the illustrated acts, may include additional acts, may combine acts, may split acts, and may perform acts in various orders. For example, act810may be split into multiple acts. In another example, the method800may be modified to include acts of responding to additional read requests received during processing of a current read request by sending a decode error.

Embodiments may facilitate allowing processors with different security attributes (e.g., a host processor102and a secure processor104) to share a data partition allowing read-while-write access to the shared data partition. For example, a host processor102may be executing code independent of the operation of a secure processor104, and thus be unaware that a write operation is about to start or is underway by the secure processor. In the absence of read-while-write collision management, the host processor would receive an invalid data reading the shared partition. When the read-while-write collision management is enabled, the host processor may assert the read request through the register interfaces while the hardware write operation is suspended, and the hardware write operation may be resumed after the data responsive to the read request is stored in the registers. The signaling to control the read and suspend/resume operations may be handled by the non-volatile memory controller and the non-volatile memory. Thus, read-while-write operations may take place without either processor being aware of the accesses by the other processor. The process of executing the read request (e.g., translation, serializing, and security checks) may be unchanged between accesses where read-while-write collision management is enable and when read-while-write collision management is disabled, and thus security and other aspects of the processing of read requests may be preserved.

In an embodiment, a device comprises: a plurality of sets of registers, which, in operation, store addresses and data associated with data read requests received from respective processing cores of a plurality of processing cores, the data read requests being directed to a data partition of a non-volatile memory; and control circuitry coupled to the plurality of sets of registers, wherein the control circuitry, in a read-while-write collision management mode of operation, responds to a data read request received from one processing core of the plurality of processing cores and directed to the data partition by: storing an address associated with the data read request in an address register of one of the plurality of sets of registers associated with the one processing core; requesting suspension of write operations directed to the data partition and execution of a read operation associated with the read request while the write operations are suspended; storing data responsive to the read operation in one or more data registers of the one of the plurality of sets of registers; and providing the data stored in the one or more data registers of the one of the plurality of sets of registers to the one processing core. In an embodiment, the control circuitry, in operation: responds to a determination that a write operation directed to the data partition is being executed when the read request is received by enabling the read-while-write collision management mode of operation. In an embodiment, the requesting suspension of write operations directed to the data partition and execution of a read operation associated with the read request while the write operations are suspended comprises: waiting for an acknowledgement of suspension of the write operations before requesting execution of the read operation. In an embodiment, the control circuitry, in operation, responds to receipt of the data responsive to the read operation by clearing the suspension of write operations directed to the data partition. In an embodiment, the requesting execution of the read operation comprises responding to the suspension of the write operations by: translating the address stored in the address register of one of the plurality of sets of registers into a logical address of the data partition; sequencing the read request; verifying the read request is authorized; asserting a read-enable signal and providing the translated address to the non-volatile memory. In an embodiment, the device comprises the non-volatile memory. In an embodiment, the plurality of processing cores comprises a host processing core and a secure processing core. In an embodiment, the control circuitry, when the read-while-write collision management mode of operation is not enabled, responds to the data read request received from the one processing core of the plurality of processing cores and directed to the data partition by: translating the address associated with the read request into a logical address of the data partition; sequencing the read request; verifying the read request is authorized; asserting a read-enable signal and providing the translated address to the non-volatile memory. In an embodiment, the control circuitry, when the read-while-write collision management mode of operation is not enabled, responds to the data read request received from the one processing core of the plurality of processing cores and directed to the data partition by bypassing the one of the plurality of set of registers associated with the one processing core during processing of the read request.

In an embodiment, a system comprises: a plurality of processing cores; and a non-volatile memory coupled to the plurality of processing cores, the non-volatile memory having: a data partition; a plurality of sets of registers, which, in operation, store addresses and data associated with data read requests received from respective processing cores of the plurality of processing cores, the data read requests being directed to a data partition of a non-volatile memory; and control circuitry coupled to the plurality of sets of registers and to the data partition, wherein the control circuitry, in a read-while-write collision management mode of operation, responds to a data read request received from one processing core of the plurality of processing cores and directed to the data partition by: storing an address associated with the data read request in an address register of one of the plurality of sets of registers associated with the one processing core; suspending write operations directed to the data partition; executing a read operation associated with the read request while the write operations are suspended; storing data responsive to the read operation in one or more data registers of the one of the plurality of sets of registers; and providing the data stored in the one or more data registers of the one of the plurality of sets of registers to the one processing core. In an embodiment, the control circuitry, in operation: responds to a determination that a write operation directed to the data partition is being executed when the read request is received by enabling the read-while-write collision management mode of operation. In an embodiment, the executing of the read operation associated with the read request while the write operations are suspended comprises: waiting for an acknowledgement of suspension of the write operations before executing the read operation. In an embodiment, the executing of the read operation comprises: translating the address stored in the address register of one of the plurality of sets of registers into a logical address of the data partition; sequencing the read request; and verifying the read request is authorized. In an embodiment, the plurality of processing cores comprises a host processing core and a secure processing core. In an embodiment, the control circuitry, when the read-while-write collision management mode of operation is not enabled, responds to the data read request received from the one processing core of the plurality of processing cores and directed to the data partition by: translating the address associated with the read request into a logical address of the data partition; sequencing the read request; and verifying the read request is authorized. In an embodiment, the control circuitry, when the read-while-write collision management mode of operation is not enabled, responds to the data read request received from the one processing core of the plurality of processing cores and directed to the data partition by bypassing the one of the plurality of set of registers associated with the one processing core during processing of the read request.

In an embodiment, a method comprises: receiving a data read request from a processing core of a plurality of processing cores, the data read request being directed to a data partition of a non-volatile memory; determining whether to process the data read request using read-while-write collision management: and responding to a determination to process the data read request using read-while-write collision management by: storing an address associated with the data read request in an address register of a set of registers associated with the processing core; suspending write operations directed to the data partition; executing a read operation associated with the read request while the write operations are suspended; storing data responsive to the read operation in one or more data registers of the set of registers; and providing the data stored in the one or more data registers of the set of registers to the processing core. In an embodiment, the determining whether to process the data read request using read-while-write collision management control circuitry comprises determining whether a write operation directed to the data partition is being executed when the read request is received. In an embodiment, the method comprises using data polling to provide the data stored in the one or more data registers to the processing core. In an embodiment, the executing of the read operation comprises: translating the address stored in the address register into a logical address of the data partition; sequencing the read request; and verifying the read request is authorized. In an embodiment, the plurality of processing cores comprises a host processing core and a secure processing core. In an embodiment, the method comprises responding to a determination to process the read request without using read-while-write collision management by bypassing the set of registers associated with the processing core during processing of the read request. In an embodiment, the method comprises: receiving a second data read request from a second processing core of a plurality of processing cores, the second data read request being directed to the data partition of the non-volatile memory; determining whether to process the second data read request using read-while-write collision management: responding to a determination to process the second data read request using read-while-write collision management by: storing an address associated with the second data read request in an address register of a second set of registers associated with the second processing core; suspending write operations directed to the data partition; executing a second read operation associated with the second read request while the write operations are suspended; storing data responsive to the second read operation in one or more data registers of the second set of registers; and providing the data stored in the one or more data registers of the second set of registers to the second processing core.

In an embodiment, a non-transitory computer-readable medium's contents cause a non-volatile memory controller to perform a method, the method comprising: receiving a data read request from a processing core of a plurality of processing cores, the data read request being directed to a data partition of a non-volatile memory; determining whether to process the data read request using read-while-write collision management: and responding to a determination to process the data read request using read-while-write collision management by: storing an address associated with the data read request in an address register of a set of registers associated with the processing core; suspending write operations directed to the data partition; executing a read operation associated with the read request while the write operations are suspended; storing data responsive to the read operation in one or more data registers of the set of registers; and providing the data stored in the one or more data registers of the set of registers to the processing core. In an embodiment, the method comprises responding to a determination to process the read request without using read-while-write collision management by bypassing the set of registers associated with the processing core during processing of the read request. In an embodiment, the contents comprise instructions executed by the non-volatile memory controller.