Oscillator for pulse communication with reduced startup latency

An oscillator for use in pulse communication of pulse signals with a startup latency and a pulse oscillation signal (such as for use in a transmitter for OOK pulse communication with pulse modulation). The oscillator includes an LC resonator having a tank impedance, and including a high-side node (Vp), and a low-side node Vn, and having a tank voltage corresponding to [Vp-Vn]. A pulse startup circuit, includes a PMOS transistor with a source connected to a supply voltage VDD, and a drain connected through a resistance R to the Vp node (where R is significantly larger than the tank impedance), and connected to an attenuation capacitance, in parallel with the resistance R. The PMOS control terminal is coupled to receive a kick start pulse to initiate a pulse signal. the oscillator can include high-side and low-side pulse startup circuits.

BACKGROUND

A digital isolator can use an oscillator for digital pulse communication with pulse (oscillation) signals across an isolation barrier.FIG. 1illustrates a digital isolator10with a TX oscillator11and RX receiver (tank)12, coupled capacitively or inductively over an isolation barrier15. Data signals are encoded17, and transmitted11as pulse signals that are sensed by the receiver, and decoded18back to digital.

Communication is based on pulse modulation, for example, pulse code, pulse amplitude, pulse width, and pulse position. For example, pulse communication can be based on on-off keying (OOK), with edge encoding (such as one pulse for a rising edge, and two pulses for a falling edge).

While this Background information references digital isolators, this Disclosure is more generally directed to oscillator designs for pulse communication.

BRIEF SUMMARY

This Brief Summary is provided as a general introduction to the Disclosure provided by the Detailed Description and Drawings, summarizing aspects and features of the Disclosure. It is not a complete overview of the Disclosure, and should not be interpreted as identifying key elements or features of, or otherwise characterizing or delimiting the scope of, the disclosed invention.

The Disclosure describes apparatus and methods for an oscillator for pulse communication with active kick start for reduced startup latency.

According to aspects of the Disclosure, an oscillator for use in pulse communication of pulse signals with a startup latency and a pulse oscillation signal, includes an LC resonator including an inductance L, and a capacitance C, and having a tank impedance. The LC resonator including a high-side node (Vp), and a low-side node Vn, and having a tank voltage corresponding to [Vp-Vn]. A pulse startup circuit includes a PMOS transistor with a source connected to a supply voltage VDD, and a drain connected through a resistance R to the Vp node, where R is significantly larger than the tank impedance, and an attenuation capacitance connected to the drain, in parallel with the resistance R. The PMOS transistor including a control terminal coupled to receive a kick start pulse to initiate a pulse signal.

According to other aspects of the Disclosure, a circuit for transmitting pulse signals with a startup latency and a pulse oscillation signal, includes transmitter circuitry including an oscillator configured to generate pulse signals. The oscillator includes an LC resonator including an inductance L, and a capacitance C, and having a tank impedance, the LC resonator including a high-side node (Vp), and a low-side node Vn, and having a tank voltage corresponding to [Vp-Vn]. Pulse startup circuitry, includes a PMOS transistor with a source connected to a supply voltage VDD, and a drain connected through a resistance R to the Vp node, where R is significantly larger than the tank impedance, and an attenuation capacitance connected to the drain, in parallel with the resistance R. The PMOS transistor including a control terminal coupled to receive a kick start pulse to initiate a pulse signal.

According to other aspects of the Disclosure, a method of pulse communication of pulse signals with a startup latency and a pulse oscillation signal, for use in a system with a transmitter oscillator including an LC resonator including an inductance L, and a capacitance C, and having a tank impedance, the LC resonator including a high-side node (Vp), and a low-side node Vn, and having a tank voltage corresponding to [Vp-Vn]. The method includes: initiating a pulse signal from the oscillator with a kick start pulse; and generating the kick start pulse with a pulse startup circuit, including a PMOS transistor with a source connected to a supply voltage VDD, and a drain connected through a resistance R to the Vp node, where R is significantly larger than the tank impedance, and an attenuation capacitance connected to the drain, in parallel with the resistance R, the PMOS transistor including a control terminal coupled to receive the kick start pulse to initiate a pulse signal.

Other aspects and features of the invention claimed in this Patent Document will be apparent to those skilled in the art from the following Disclosure.

DETAILED DESCRIPTION

This Description and the Drawings constitute a Disclosure, including design examples and implementations, and including illustrating various technical features and advantages for: an oscillator for pulse communication with active kick start for reduced startup latency.

An example application is digital isolation based on a transmitter oscillator for pulse (oscillation) communication, capacitively (or inductively) coupled to a receiver across an isolation barrier. An example alternate application is a transmitter oscillator for pulse communication, coupled to an antenna for wireless communication to a remote receiver. An example pulse modulation is OOK (on-off keying), with edge encoding.

This Disclosure uses the following nomenclature: A pulse signal or pulse oscillation signal includes a startup swing period (startup latency), followed by a specified steady state swing period (pulse oscillation period), with pulse width determined by startup latency and the pulse oscillation period (at steady state swing). The startup latency, can also be referred to as the wakeup or settling time. For pulse communication, including the example OOK modulation, startup latency is an important aspect of pulse width, and therefore an important determinant of system power, delay and speed.

In brief overview, an oscillator for use in pulse communication of pulse signals with a startup latency and a pulse oscillation signal, includes an LC resonator having a tank impedance, and including a high-side node (Vp), and a low-side node Vn, and having a tank voltage corresponding to [Vp-Vn]. A pulse startup circuit, includes a PMOS transistor with a source connected to a supply voltage VDD, and a drain connected through a resistance R to the Vp node (where R is significantly larger than the tank impedance), and connected to an attenuation capacitance, in parallel with the resistance R. The PMOS control terminal is coupled to receive a kick start pulse (for example, 1 ns) to initiate a pulse signal. the oscillator can include high-side and low-side pulse startup circuits. An example application is a transmitter oscillator for OOK pulse communication with pulse modulation.

FIG. 2Aillustrates an oscillator21, for pulse communication, including generation of a pulse (oscillation) signal.FIG. 2Billustrates an example pulse signal with a pulse width based on a startup latency, followed by a pulse oscillation (steady state oscillation with a defined swing).

Oscillator21is configured for a digital isolation application, the oscillator configured as a transmitter for pulse communication (OOK) across an isolation barrier.

Oscillator21includes an oscillator core23with an LC resonator (tank)25, and a two stage feedback generator27. LC resonator25includes coupled inductors L1and L2with a center tap to ground. The tank inductors L1/L2are connected between a high-side node Vp and a low-side node Vn. The voltage difference between the Vp and Vn nodes is the tank voltage [Vp-Vn], which defines the (voltage) swing of the oscillator (each of the nodes Vp/Vn sees one-half of the tank voltage swing). Parasitic capacitance (which can be tuned by the tank inductors L1/L2) is not shown.

Oscillator21includes high-side and low-side startup circuits29A and29B coupled to respective nodes Vp and Vn. Startup circuits29A and29B include respective startup capacitors CA and CB to provide initial energy in the LC resonator tank25at the transition of VIN. VIN is an input to the startup circuits29A/29B (and provides an enable signal to the feedback generator). For higher levels of VIN, the startup capacitors CA and CB become part of the LC resonator tank, which can limit swing, and reduce oscillation frequency. Energy pumped is proportional to the capacitor ratios for the startup capacitors and tank capacitors, and VDD (for example, 1.8V), so CA,CB should be lower capacitance for higher swing, and higher for faster startup.

Referring toFIG. 2B, an example pulse signal is initiated by the VIN current pulse input to the resonator tank25through the startup capacitors CA/CB. An example startup latency after initiation is 5 ns before pulse oscillation (steady state swing) is achieved.

Pulse width and pulse oscillation period (effective energy transfer) are determined by receiver pulse signal sensing requirements. The example pulse signal is 7 ns of pulse oscillation (steady state swing)29SS, after the startup latency29SU of 5 ns, for a total pulse width of 12 ns, with a pulse swing29SW (tank voltage) of 1.8V.

FIGS. 3A and 3Billustrate an example oscillator31with an active kick start circuit for pulse communication with reduced startup latency, according to the Disclosure. The example oscillator31can be implemented in an example digital isolator, using capacitive isolation, with advantages in low power and isolation voltage specification.

FIG. 3Aillustrates the example oscillator31with example high-side and low-side active kick start circuits39A and39B.FIG. 3Billustrates example pulse signal waveforms, including an example pulse signal with a defined startup latency after pulse initiation, followed by pulse oscillation (steady state swing).

As illustrated inFIG. 3B, the active kick start circuit according to the Disclosure can provide a pulse oscillation signal in which startup latency39SU is reduced to 2 ns (from 5 ns), enabling a pulse oscillation period (steady state swing)39SS of 9 ns (increased from 7 ns). The resulting pulse width is 11 ns pulse width (decreased from 12 ns).

The example oscillator31includes an example oscillator core33, and the example active kick start circuits39A and39B. Example oscillator core33uses the oscillator core configuration inFIG. 2A. The active kick start circuits39A and39B function to reduce startup latency according to the Disclosure, replacing the (passive) capacitive startup circuits29A/29B inFIG. 1(eliminating the startup capacitors CA/CB).

The oscillator core can include any suitable structure for an LC resonator. In an example implementation, the oscillator core33includes, in addition to the LC resonator35, a two stage feedback generator37.

LC resonator35includes coupled inductors L1and L2with a center tap to ground (although the inductor center tap could be tied to a different voltage). If the inductor center tap is ground, the low-side active kick start circuit39B is not required (if the inductor center tap is a voltage different than ground, the low-side active kick start circuit is recommended). Parasitic capacitance (which can be tuned by the tank inductors L1/L2) is not shown

The resonator tank coupled inductors L1/L2are connected between a high-side node Vp and a low-side node Vn. The voltage difference between the Vp and Vn nodes is the tank voltage [Vp-Vn], which defines the (voltage) swing of the oscillator (each of the nodes Vp/Vn sees one-half of the tank voltage swing).

The example active kick start circuits39A and39B are coupled to respective LC resonator tank nodes Vp and Vn. The input VIN is used to enable the feedback generator37, but is not input to the active kick start circuits39A/39B.

Active kick start circuit39A includes a PMOS M1with a source coupled to VDD, and a drain coupled through resistor R to the resonator tank Vp node. A CATT capacitor is connected to the PMOS drain in parallel with R, forming a low pass filter for attenuating oscillation frequencies. Optional low-side active kick start circuit39B includes an NMOS M2with a source coupled to ground, and a drain coupled through resistor R to the resonator tank Vn node. A CATT capacitor is connected to the NMOS drain in parallel with R, forming a low pass filter.

For both example kick start circuits, R is chosen to be significantly larger than the tank impedance, for example 5-10×, so that the kick startup circuit(s) does(do) not impact steady state swing. For an example tank parallel resonance impedance of 1K, an example kick start circuit can be configured with R=10K, and a CATT of 100 fF.

Active kick start circuit39A receives a kick startup voltage pulse at the M1control terminal, generating a kick start current pulse through the resonator inductors L1/L2, and initiating a pulse signal. The initial startup current for both active kick start circuits39A/39B is VDD/R, and energy is input to the resonator tank35for only the duration of the kick start pulse (for example, 1 ns).

Pulse width is selected based on receiver pulse sensing requirements for pulse oscillation (effective energy transfer). Referring toFIG. 3B, the example pulse signal is 9 ns of pulse oscillation (steady state swing)39SS, for a total pulse width of 11 ns, with a pulse swing (tank voltage)39SW of 1.8V.

The CATT capacitors attenuate oscillation frequency, which doesn't impact startup DC current, and provide protection of the M1/M2GOI by holding the M1/M2drains low. When the kick start pulse is off, M1and M2float, but are off and present a high impedance.

The Disclosure provided by this Description and the Figures sets forth example designs and applications illustrating aspects and features of the invention, and does not limit the scope of the invention, which is defined by the claims. Known circuits, connections, functions and operations are not described in detail to avoid obscuring the principles and features of the Disclosed example designs and applications. This Disclosure can be used by ordinarily skilled artisans as a basis for modifications, substitutions and alternatives, including adaptations for other applications.