Integrated circuit provided with a protection against electrostatic discharges

An integrated circuit protected against electrostatic discharges, having output pads coupled to amplification stages, each stage including, between first and second power supply rails, a P-channel MOS power transistor in series with an N-channel MOS power transistor, this integrated circuit further including protection circuitry for simultaneously turning on the two transistors when a positive overvoltage occurs between the first and second power supply rails.

CROSS REFERENCE TO RELATED APPLICATIONS

This application claims the priority benefit of French patent application number 10/50860, filed on Feb. 8, 2010, entitled “Integrated Circuit Provided with a Protection Against Electrostatic Discharges,” which is hereby incorporated by reference to the maximum extent allowable by law.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to the protection of integrated circuits against electrostatic discharges.

2. Discussion of the Related Art

An integrated circuit comprises metal pads intended to provide connections to the outside. Some of the pads are capable of receiving power supply voltages. The other pads are capable of receiving and/or of providing input/output signals. Power supply rails, connected to the supply pads, are generally provided all around the circuit to power its different components. Generally, an insulating layer covers the circuit, only leaving access to the metal pads.

Such a circuit generally receives and/or delivers signals of low voltage level (for example, from 1 to 5 V) and of low current intensity (for example, from 1 μA to 10 mA), and may be damaged when overvoltages or overintensities occur between pads of the circuit.

It is thus provided to associate a protection structure with each pad. The protection structure should be able to rapidly drain off significant currents, that appear when an electrostatic discharge occurs on an input/output pad (“pad”, for simplification) or on a pad connected to a power supply rail (“rail”, for simplification).

FIG. 1shows an example of a protection structure1associated with an integrated circuit input/output pad3. A diode5is forward connected between pad3and a high power supply rail VDD. A diode7is reverse-connected between pad3and a low power supply rail VSS. A MOS transistor9, used as a switch, is connected between high and low power supply rails VDDand VSS. An overvoltage detection circuit11, connected in parallel with MOS transistor9, provides a trigger signal to this transistor. MOS transistor9comprises a parasitic diode10, forward connected between rail VSSand rail VDD.

In normal operation, when the chip is powered, the signals on pad3and rails VDDand VSSare such that diodes5and7conduct no current and detection circuit11makes MOS transistor9non-conductive.

In case of a positive overvoltage between rails VDDand VSS, circuit11turns on transistor9, which enables to remove the overvoltage.

In case of a negative overvoltage between rails VDDand VSS, parasitic diode10of transistor9becomes conductive and the overvoltage is removed.

In case of a positive overvoltage between pad3and high power supply rail VDD, diode5becomes conductive and the overvoltage is removed.

In case of a negative overvoltage between pad3and rail VDD, circuit11turns on transistor9and the overvoltage is removed through transistor9and diode7.

In case of a positive overvoltage between pad3and rail VSS, diode5becomes conductive and the positive overvoltage is transferred onto rail VDD, which corresponds to the above case of a positive overvoltage between rails VDDand VSS.

In case of a negative overvoltage between pad3and rail VSS, diode7becomes conductive and the overvoltage is removed.

In case of a positive or negative overvoltage between two input/output pads3, diodes5or7associated with the concerned pads become conductive, and the overvoltage is transferred onto high and low power supply rails VDDand VSS. This corresponds to one of the above overvoltage cases.

FIG. 2partly shows the diagram ofFIG. 1and shows in further detail an example of a possible embodiment of a circuit11for detecting a positive overvoltage between rails VDDand VSS, and for controlling protection transistor9. An edge detector, formed of a resistor21in series with a capacitor23, is connected between power supply rails VDDand VSS. Node M between resistor21and capacitor23is connected to the gate of a P-channel MOS transistor25having its source connected to rail VDDand having its drain connected to rail VSSvia a resistor27. Node N between the drain of transistor25and resistor27is connected to the gate of transistor9. An assembly29of diodes in series is forward-connected between node M and rail VSS. In this example, assembly29comprises four diodes in series.

In normal operation, when the circuit is powered, node M is in a high state. P-channel MOS transistor25thus conducts no current. Thus, gate node N of transistor9is in a low state, and protection transistor9is maintained off. When the potential difference between rails VDDand VSSincreases, the voltage of node M also increases. When the voltage of node M reaches a given threshold, diode assembly29becomes conductive. In this example, if each diode has a 0.6-V threshold voltage, assembly29becomes conductive when the voltage of node M exceeds 2.4 V. This results in a voltage drop at node M, which turns on P-channel MOS transistor25. Thus, gate node N of protection transistor9switches to a high state, that is, substantially to the same positive voltage as rail VDD. Transistor9thus becomes conductive and the overvoltage is removed.

When the integrated circuit is not powered, node M is in a low state. Since transistor25is not powered, drain node N of this transistor is in an undetermined state. If an abrupt positive overvoltage (fast voltage rise) occurs between rails VDDand VSS, node M remains in a low state. Transistor25thus becomes conductive and node N switches to a high state. Thus, protection transistor9is made conductive and the overvoltage is removed.

A disadvantage of the protection structure ofFIGS. 1 and 2lies in the fact that, to be able to drain off the currents induced by electrostatic discharges, diodes5and7and transistor9should have a large surface area (for example, a 200-μm junction perimeter per diode and a channel width of several tens of millimeters for the transistor). As a result, a significant silicon surface area is exclusively dedicated to the protection against electrostatic discharges, to the detriment of the other circuit components. Further, due to its large size, MOS transistor9, in the off state, is crossed by significant leakage currents, which increases the circuit power consumption and the stray capacitance between rails VDDand VSS.

SUMMARY OF THE INVENTION

An object at least one embodiment of the present invention is to provide an integrated circuit provided with a protection against electrostatic discharges, where this protection does not increase the silicon surface area taken up by the same circuit when unprotected or only slightly does so.

An object of an embodiment of the present invention is to provide such a protection which does not disturb the proper operation of the circuit in normal conditions of use.

An object of an embodiment of the present invention is to provide such a protection which is easy to implement.

An embodiment of the present invention provides using, in case of an overvoltage, MOS power transistors, existing in the output amplification stages of the integrated circuit, as an overvoltage removal path.

Thus, an embodiment of the present invention provides an integrated circuit protected against electrostatic discharges, having output pads coupled to amplification stages, each stage comprising, between first and second power supply rails, a P-channel MOS power transistor in series with an N-channel MOS power transistor, this integrated circuit further comprising protection means for simultaneously turning on the two transistors when a positive overvoltage occurs between the first and second power supply rails.

According to an embodiment of the present invention, in each amplification stage, the sources of the P- and N-channel transistors are respectively connected to the first and second power supply rails, and the drains of the transistors are connected to the output pad.

According to an embodiment of the present invention, the integrated circuit comprises a control circuit for each amplification stage to control, in normal operation, the turning off and the turning on of the transistors, this control circuit comprising at least one output connected to the gates of the P-channel and N-channel transistors, and the protection means comprise: first and second resistors respectively connected between the output of the control circuit and the respective gates of the P-channel and N-channel transistors; and a detection and trigger circuit comprising first and second outputs respectively connected to the gates of the P-channel and N-channel transistors, capable of simultaneously turning on the two transistors when a positive overvoltage occurs between the first and second power supply rails.

According to an embodiment of the present invention, the amplification stage control circuit is connected to the first and second power supply rails via P-channel and N-channel MOS transistors, having their respective gates connected to edge detectors capable of controlling the turning off of these transistors when a positive overvoltage occurs between the first and second power supply rails.

According to an embodiment of the present invention, the detection and trigger circuit comprises: a first zener diode forward-connected between its second output and the first rail; and a second zener diode forward-connected between the second rail and its first output.

According to an embodiment of the present invention, the detection and trigger circuit comprises: a first edge detector comprising a resistor in series with a capacitor, connected between the first and second rails; a second edge detector comprising a resistor in series with a capacitor, connected between the second and first rails; a P-channel MOS transistor having its source and its drain respectively connected to the first rail and to the first output, and having its gate connected between the resistor and the capacitor of the first edge detector; an N-channel MOS transistor having its source and its drain respectively connected to the second rail and to the second output, and having its gate connected between the resistor and the capacitor of the second edge detector; and first and second zener diodes respectively forward-connected between the second rail and the gate of the P-channel transistor, and between the gate of the N-channel transistor and the first rail.

DETAILED DESCRIPTION

For clarity, the same elements have been designated with the same reference numerals in the different drawings.

In an integrated circuit, an output amplification stage is associated with each output pad, to adapt the (low) power of the internal signals of the circuit, to a (higher) level exploitable outside of the circuit.

FIG. 3shows the diagram ofFIG. 1of a protection structure associated with a pad3of an integrated circuit, in the case where this pad is an output pad. In this case, an output amplification stage is associated with pad3.

The output amplification stage comprises a P-channel MOS power transistor31, in series with an N-channel MOS power transistor33. The sources of transistors31and33are respectively connected to high and low power supply rails VDDand VSS. The drains of transistors31and33are interconnected at a node connected to output pad3of the circuit. A control circuit35of the amplification stage is provided to control the gates of transistors31and33. In this example, circuit35comprises two inputs IN and LOW-Z, and two outputs, respectively connected to the gates of transistors31and33, to control the flowing of the current in one or the other of transistors31and33according to the state of inputs IN and LOW-Z. Signal IN corresponds to the signal which should be amplified by the amplification stage. Signal LOW-Z controls the setting of the output pad to high impedance, that is, the simultaneous turning off of transistors31and33. For its power supply, circuit35is connected to rails VDDand VSS.

FIG. 4shows in further detail a possible embodiment of circuit35for controlling output amplification stage31,33. Circuit35comprises a three-input NAND gate41and a three-input NOR gate43. The outputs of NAND gate41and NOR gate43are respectively connected to the gates of transistors31and33. NAND gate41receives signal IN, signal LOW-Z, and the output signal of NOR gate43inverted by an inverter45. NOR gate43receives signal IN, signal LOW-Z inverted by an inverter46, and the output signal of NAND gate41inverted by an inverter47. For their power supply, logic gates41,43,45,46, and47are connected to power supply rails VDDand VSS.

When signal LOW-Z is in a low state, to set output pad3to high impedance, the gate nodes of transistors31and33are respectively in high and low states. Thus, transistors31and33are both off, and pad3is at high impedance.

When signal LOW-Z is in a low state, the state of the gate nodes of transistors31and33is determined by signal IN.

Control circuit35is provided to control the turning-on of one or the other of transistors31and33(amplification of input signal IN) or the simultaneous turning-off of transistors31and33(setting to high impedance of the output pad), but never the simultaneous turning-on of two transistors, which would short-circuit the integrated circuit power supply. The return of the output signal of NAND gate41to the input of NOR gate43, via inverter47, and the return of the output signal of NOR gate43to the input of NAND gate41, via inverter45, enable to ascertain that power transistors31and33are not simultaneously on, even for a short time, for example, in switchings of signal IN.

It is here provided to use the MOS power transistors of the output amplification stage of an integrated circuit as an electrostatic discharge removal path. It is especially provided, in case of a positive overvoltage between power supply rails VDDand VSS, to simultaneously turn on transistors31and33to enable to remove the overvoltage.

FIG. 5schematically shows an embodiment of a protection structure associated with an output pad of an integrated circuit, using the transistors of the output amplification stage associated with the pad as elements of protection against electrostatic discharges.

A control circuit51, connected between power supply rails VDDand VSS, is provided to control the gates of transistors31and33of the output amplification stage associated with pad3. Parasitic diodes32and34of transistors31and33have been shown in the drawing. Diodes32and34are respectively forward-connected between pad3and rail VDDand reverse-connected between pad3and rail VSS. Like control circuit35described in relation withFIGS. 3 and 4, circuit51comprises two inputs IN and LOW-Z, and two outputs, respectively connected to the gates of transistors31and33, to control the flowing of the current in one or the other of the transistors according to the state of inputs IN and LOW-Z. Circuit51further comprises protection means for controlling the simultaneous turning-on of transistors31and33in case of a positive overvoltage between rails VDDand VSS.

In case of a positive overvoltage between rails VDDand VSS, circuit51controls the turning-on of transistors31and33, which enables to remove the overvoltage.

In case of a negative overvoltage between rails VDDand VSS, diodes34and32become conductive and the overvoltage is removed.

In case of a positive overvoltage between pad3and high power supply rail VDD, diode32becomes conductive and the overvoltage is removed.

In case of a negative overvoltage between pad3and rail VDD, circuit51controls the turning-on of transistors31and33and the overvoltage is removed through transistor31.

In case of a positive overvoltage between pad3and rail VSS, diode32becomes conductive and the positive overvoltage is transferred onto rail VDD. Circuit51controls the turning-on of transistors31and33and the overvoltage is removed through transistor33.

In case of a negative overvoltage between pad3and rail VSS, diode34becomes conductive and the overvoltage is removed.

In case of a positive or negative overvoltage between two input/output pads3, diode32associated with the most positive pad becomes conductive. Circuit51then controls the turning-on of transistors31and33, and the overvoltage is removed via transistor33associated with the most positive pad and via diode34associated with the least positive pad and, in parallel, via diode32associated with the most positive pad and via transistor31associated with the least positive pad.

Thus, transistors31and33enable removing any type of overvoltage capable of occurring between two (output) pads or rails of the circuit. Due to their normal power amplification function, transistors31and33have significant dimensions, and can advantageously replace the protection elements of conventional structures of the type described in relation withFIGS. 1 and 2(transistor9and diodes5and7). It should be noted that, to provide a full protection of the circuit, it may be provided to associate a protection adapted to the input pads of the circuit, for example, diodes of the type of diodes5and7ofFIG. 1, capable of transferring onto their power supply rails the overvoltages likely to occur on the input pads. The overvoltages can then be removed via the output stages of the output pads.FIG. 6shows the diagram ofFIG. 5, and shows in further detail an embodiment of the circuit for controlling the transistors of the output amplification stage (circuit51ofFIG. 5).

Like circuit35described in relation withFIG. 4the circuit ofFIG. 6comprises a logic block comprising a NAND gate41, a NOR gate43, and inverters45,46, and47, to control, in normal operation, the gates of transistors31and33according to the state of input signals IN and LOW-Z.

Resistors73and75are respectively added between the output of NAND gate41and the gate of transistor31and between the output of NOR gate43and the gate of transistor33.

Further, a detection and trigger circuit77is connected between power supply rails VDDand VSS. Circuit77comprises outputs CDP and CDN, respectively connected to the gates of transistors31and33.

An edge detector, formed of a capacitor63in series with a resistor65, is connected between rails VDDand VSS. NAND gate41is connected to power supply rail VDDvia a P-channel MOS transistor61having its gate connected to node A between capacitance63and resistor65. The source and the drain of transistor61are respectively connected to rail VDDand to the high power supply terminal of NAND gate41. The low power supply terminal of NAND gate41is connected to rail VSS.

Similarly, the power supply of NOR gate43is coupled with an edge detector, formed of a capacitor69in series with a resistor71, connected between rails VSSand VDD. NOR gate43is connected to power supply rail VSSvia an N-channel MOS transistor67having its gate connected to a node B between capacitor69and resistor71. The source and the drain of transistor67are respectively connected to rail VSSand to the low power supply terminal of NOR gate43. The high power supply terminal of NOR gate43is connected to rail VDD.

In normal operation, signals CDP and CDN are at high impedance and do not disturb the operation of the amplification stage control circuit. Further, nodes A and B respectively are in low and high states, maintaining transistors61and67on. Thus, the circuit for controlling the amplification stage is powered normally.

In case of a positive overvoltage between rails VDDand VSS, signals CDP and CDN respectively switch to low and high states. Thus, due to the presence of resistors73and75, whatever the output state of NAND gate41and NOR gate43, the voltage on the gate of P-channel MOS transistor31is smaller than the voltage of rail VDD, and the voltage on the gate of N-channel MOS transistor33is greater than the voltage of rail VSS. This causes the simultaneous turning-on of transistors31and33and the removal of the overvoltage.

The coupling of the power supplies of NAND gate41and NOR gate43with edge detectors is an additional way of ascertain the turning-on of transistors31and33, when a fast positive overvoltage occurs between rails VDDand VSS, while the integrated circuit is not powered. When the integrated circuit is not powered, node A between resistor65and capacitor63is in a low state. When a fast overvoltage occurs between rails VDDand VSS, node A immediately switches to a high state, that is, substantially to the same voltage as rail VDD, which causes the turning-off of transistor61. Thus, despite the presence of a positive voltage between rails VDDand VSS, NAND gate41is not powered and its output remains floating, in an undetermined state. Output signal CDP of circuit77can thus freely control the turning-on of transistor31to enable to remove the overvoltage. A substantially symmetrical line of argument applies to NOR gate43and to transistor33.

FIG. 7shows an embodiment of detection and trigger circuit77of the protection structure ofFIG. 6. This circuit comprises zener diodes81and83, respectively forward-connected between output CDN of the circuit and rail VDD, and reverse-connected between output CDP of the circuit and rail VSS.

In normal operation, when the circuit is powered, diodes81and83are non-conductive, and outputs CDN and CDP of the circuit are at high impedance.

When the potential difference between rails VDDand VSSexceeds a given threshold, diodes81and83become conductive in reverse mode, by avalanche effect. Thus, output CDN switches to a high state, that is, substantially at the same voltage as rail VDDminus a value VZcorresponding to the threshold voltage of diode81. Further, output CDP switches to a low state, that is, substantially to voltage VZcorresponding to the threshold voltage of diode83.

FIG. 8shows a preferred alternative embodiment of detection and trigger circuit77of the protection structure ofFIG. 6. An edge detector, formed of a resistor91in series with a capacitor93, is connected between power supply rails VDDand VSS. Node D between resistor91and capacitor93is connected to the gate of a P-channel MOS transistor95having its source connected to rail VDDand having its drain node E connected to output CDN of the circuit. A zener diode99is forward-connected between rail VSSand node D. Another edge detector, formed of a resistor101in series with a capacitor103, is connected between power supply rails VSSand VDD. Node G between resistor101and capacitor103is connected to the gate of an N-channel MOS transistor105having its source connected to rail VSSand having its drain node H connected to output CDP of the circuit. A zener diode109is reverse connected between rail VDDand node G.

In normal operation, when the circuit is powered, nodes D and G are respectively at high and low voltages, and transistors95and105are thus off. Thus, outputs CDN and CDP of the circuit are at high impedance.

When the potential difference between rails VDDand VSSexceeds a given threshold, diodes99and109become conductive in reverse mode by avalanche effect. This results in limiting the voltage of node D and causes a rise of the voltage at node G. Transistors95and105thus turn on. Thus, outputs CDN and CDP of the circuit respectively switch to high and low states, that is, substantially to the voltages of rails VDDand VSS.

When the integrated circuit is not powered, nodes D and G are at low states. If a fast positive overvoltage occurs between rails VDDand VSS, node D remains in a low state, and node G rapidly switches to a high state, substantially corresponding to the voltage of rail VDD. Transistors95and105thus turn on and outputs CDN and CDP respectively switch to high and low states.

An advantage of the detection and trigger circuit ofFIG. 8over the circuit ofFIG. 7is that in the circuit ofFIG. 8, in case of an overvoltage, outputs CDP and CDN are at voltages which are respectively lower and higher than in the case of the circuit ofFIG. 7. This results in a better conduction of transistors31and33and thus in a better efficiency of the protection.

FIG. 9shows another alternative embodiment of the protection structure ofFIG. 5. The circuit ofFIG. 9is similar by many points to the circuit ofFIG. 6, and the features which are not necessary to highlight the advantages of this circuit will not be described again hereafter.

In the circuit ofFIG. 9, detection and trigger circuit77ofFIG. 6is replaced with a detection and trigger circuit117comprising, in addition to outputs CDP and CDN respectively connected to the gates of transistors31and33, outputs CDP2and CDN2.

As in the circuit ofFIG. 6, NAND gate41is connected to power supply rail VDDvia a P-channel MOS transistor61. An edge detector comprising a capacitor63in series with a resistor65is connected between rails VDDand VSS. The node between capacitor63and resistor65is connected to the gate of transistor61. Similarly, NOR gate43is connected to power supply rail VSSvia an N-channel MOS transistor67. Another edge detector comprising a capacitor69in series with a resistor71is connected between rails VSSand VDD. The node between capacitor69and resistor71is connected to the gate of transistor67.

The circuit ofFIG. 9further comprises a P-channel MOS transistor111having its source connected to rail VDDand having its drain connected to the gate of transistor61. The gate of transistor111is connected to output CDP2of detection and trigger circuit117. The circuit ofFIG. 9also comprises an N-channel MOS transistor113having its source connected to rail VSSand having its drain connected to the gate of transistor67. The gate of transistor113is connected to output CDN2of circuit117.

In normal operation, signals CDP and CDN are at high impedance, and signals CDP2and CDN2respectively are at high and low states, maintaining transistors111and113off. Nodes A and B respectively are at low and high states, maintaining transistors61and67on. Thus, the amplification stage control circuit is powered and, due to the high impedance of outputs CDP and CDN, its normal operation is not disturbed.

In case of a positive overvoltage between rails VDDand VSS, signals CDP and CDN respectively switch to low and high states, which causes the simultaneous turning-on of transistors31and33and the removal of the overvoltage.

As in the circuit ofFIG. 6, the coupling of the power supplies of NAND gate41and NOR gate43with edge detectors is an additional way of ascertaining the turning-on of transistors31and33when a fast positive overvoltage occurs between rails VDDand VSSwhile the integrated circuit is not powered.

The provision of transistors111and113also enables to ascertain the cutting-off of the power supply of gates41and43when a slow positive overvoltage occurs between rails VDDand VSS. When a positive overvoltage occurs between rails VDDand VSS, outputs CDP2and CDN2of circuit117respectively switch to low and high states, which turns on transistors111and113. This results in a rise of the gate voltage of transistor61and a drop of the gate voltage of transistor67, which turns off transistors61and67. NAND gate41and NOR gate43are thus not powered and their respective outputs are floating, at undetermined states. Detection and trigger circuit117can thus freely control the turning-on of protection transistors31and33via its outputs CDP and CDN.

FIG. 10shows an embodiment of detection and trigger circuit117of the protection structure ofFIG. 9. The circuit ofFIG. 10comprises all the elements of the circuit ofFIG. 7and further comprises zener diodes121and123respectively forward-connected between output CDN2and rail VDD, and reverse-connected between output CDP2of the circuit and rail VSS, as well as resistors125and127respectively connected between output CDN2and rail VSSand between output CDP2and rail VDD.

In normal operation, when the circuit is powered, diodes81,83,121, and123are non-conductive. Thus, outputs CDN and CDP are at high impedance and outputs CDN2and CDP2respectively are at low and high states.

When the voltage difference between rails VDDand VSSexceeds a given threshold, diodes81,83,121, and123become conductive in reverse mode, by avalanche effect. Thus, outputs CDN and CDN2switch to a high state, that is, substantially to the same voltage as rail VDDminus a value VZcorresponding to the threshold voltage of the diodes. Further, outputs CDP and CDP2switch to a low state, that is, substantially to voltage VZcorresponding to the threshold voltage of the diodes.

FIG. 11shows a preferred alternative embodiment of detection and trigger circuit117of the protection structure ofFIG. 9. The circuit ofFIG. 11shows all the elements of the circuit ofFIG. 8. Only the additional elements will be described herein. Node D is connected to the gate of a P-channel MOS transistor131having its source connected to rail VDDand having its drain node connected to output CDN2of the circuit. A resistor133is connected between output CDN2and rail VSS. Further, node G is connected to the gate of an N-channel MOS transistor135having its source connected to rail VSSand having its drain node connected to output CDP2of the circuit. A resistor137is connected between output CDP2and rail VDD.

In normal operation, when the circuit is powered, nodes D and G are respectively at high and low voltages, maintaining transistors95,131,105, and135off. Thus, outputs CDN and CDP of the circuit are at high impedance and outputs CDN2and CDP2respectively are at low and high states.

When the potential difference between rails VDDand VSSexceeds a given threshold, diodes99and109become conductive in reverse mode, by avalanche effect. This limits the voltage of node D and causes a rise of the voltage at node G. Transistors95,131,105, and135thus become conductive. Thus, outputs CDN and CDN2switch to a high state, that is, substantially to the voltage of rail VDD, and outputs CDP and CDP2switch to a low state, that is, substantially to the voltage of rail VSS.

When the integrated circuit is not powered, nodes D and G are at low states. If a fast positive overvoltage occurs between rails VDDand VSS, node D remains in a low state, and node G rapidly rises to a high state, substantially corresponding to the voltage of rail VDD. Transistors95,131,105, and135thus turn on. Outputs CDN and CDN2switch to a high state and outputs CDP and CDP2switch to a low state.

An advantage of the provided embodiments is that they enable, in an integrated circuit, to decrease the silicon surface area specifically dedicated to the protection against electrostatic discharges.

Eliminating the MOS transistors specifically dedicated to the protection enables to decrease the electric overconsumption linked to leakage currents through these transistors.

Specific embodiments of the present invention have been described. Different variations and modifications will occur to those skilled in the art. In particular, embodiments of detection and trigger circuits have been described in relation withFIGS. 7 and 8. The present invention is not limited to these specific cases. It will be within the abilities of those skilled in the art to use any other circuit capable of detecting positive overvoltages between rails VDDand VSSand to accordingly control the gates of the transistors of the output amplification stage.

Further, the present invention is not limited to the use of the circuit described in relation withFIG. 4, to control, in normal operation, the turning-off and the turning-on of the MOS transistors of the output amplification stage.

Similarly, other logic blocks than those described in relation withFIGS. 6 and 9may be provided to interrupt, in case of an overvoltage, the normal power supply of the circuit for controlling the transistors of the output amplification stage.