Pixel set

A pixel set including two scan lines parallel to each other, a data line intersected with the scan lines, and two pixels located between the scan lines is provided. The pixels are at two sides of the data line, respectively. Each pixel includes an active device disposed adjacent to the data line, a pixel electrode, a storage capacitance electrode partially overlapped with the pixel electrode, and a drain compensating pattern including a branch. The branch is located at a side of the pixel electrode away from the data line, and has a concavity located at a side of the branch adjacent to the data line. The drain compensating pattern is connected to a drain of the active device. A portion of the drain compensating pattern is located inside the concavity. The branch is not overlapped with the drain compensating pattern at a side of the concavity away from the gate.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims the priority benefit of Taiwan application serial no. 98121147, filed Jun. 24, 2009. The entirety of the above-mentioned patent application is hereby incorporated by reference herein and made a part of specification.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention is related to a pixel set, and in particular, to a pixel set having a design of capacitance compensation.

2. Description of Related Art

Generally, an active matrix liquid crystal display (AM-LCD) mainly includes an active device array, a color filter and a liquid crystal layer.FIG. 1is a schematic top view of a conventional active device array. Referring toFIG. 1, an active device array100mainly includes a plurality of pixels110arranged to form an array. Each of pixels110comprises a scan line112, a data line114, an active device116and a pixel electrode118corresponding to the active device116.

It is noted that two adjacent pixels110share one data line114in the active device array100for saving the amount of the data lines114so as to reduce the loading of the driving chips or the amount of the driving chips. That is to say, the pixels110of the active device array100are configured in pairs. Simultaneously, a storage capacitance electrode120is further disposed in the pixel110for stabilizing the display frame of the liquid crystal display. Moreover, the active device116can be directly disposed on the scan line112for enlarging the disposition area of the pixel electrode118, that is to say, the scan line112and the active device116share the same space.

FIG. 2is an equivalent circuit diagram of a liquid crystal display (LCD) applying the active device array ofFIG. 1. Referring toFIG. 2, the pixel of a conventional active matrix LCD generally comprises an active device116, a liquid crystal capacitance CLCand a storage capacitance Cst.

Referring toFIGS. 1 and 2, the liquid crystal capacitance CLCis formed by coupling the pixel electrode118on the active device array100and a common electrode on the color filter (not shown). The storage capacitance Cstis formed by coupling the pixel electrode118and the storage capacitance electrode120, and the storage capacitance Cstis parallel to the liquid crystal capacitance CLC. In addition, the gate G, the source S and the drain D of the active device116are electrically connected to the scan line112, the data line114and the pixel electrode118of the liquid crystal capacitor CLC, respectively. An overlapping region is formed between the gate G and the drain D of the active device116, i.e. the area with oblique lines illustrated inFIG. 1. Therefore, a gate-drain parasitic capacitance Cgdis formed between the gate G and the drain D.

Referring toFIG. 1andFIG. 2again, the voltage applied to the liquid crystal capacitance CLCcommonly keeps a certain relationship with the light transmissive rate of the liquid crystals. Accordingly, a desired frame is displayed by a display if only the voltage applied to the liquid crystal capacitance CLCis modulated according to the desired frame. Nevertheless, the gate-drain parasitic capacitance Cgdis formed, and thus the voltage maintained in the liquid crystal capacitance CLCis varied with the signal change of the data line114. Such a voltage variation is called feed-through voltage ΔVpand is expressed as formula (1):

Δ⁢⁢Vp=CgdCgd+Cst+CLC⁢Δ⁢⁢Vg(1)
wherein ΔVg indicates an amplitude of a pulse voltage applied on the scan line112.

In the current manufacturing process of the active device array, the displacement error during movements of the machine would cause nonconformity among the positions of each element. Particularly, when the area of the overlapping region between the gate G and the drain D of the active device116such as the area with oblique lines shown inFIG. 1varies, the gate-drain parasitic capacitance Cgdis changed. Accordingly, the feed-through voltage ΔVpof each pixel100in a pair is different from each other, and uneven display brightness during display is generated.

SUMMARY OF THE INVENTION

The present invention is directed to a pixel set having a design for compensating the variations of the gate-drain parasitic capacitance caused by the displacement error of the manufacturing process.

The present invention provides a pixel set including two scan lines, a data line and two pixels. Two scan lines are parallel to each other, and the data line intersects with the two scan lines. The two pixels are located between the two scan lines and at two sides of the data line, respectively. The two pixels are respectively electrically connected to the two scan lines, wherein each of the pixels includes an active device, a pixel electrode, a storage capacitance electrode and a drain compensating pattern. The active device is disposed adjacent to the data line, and the active device includes a gate, a drain and a source. The gate is electrically connected to a corresponding one of the two scan lines. The source is electrically connected to the data line. The source and the drain are located at two opposite sides of the gate, respectively. The pixel electrode is electrically connected to the drain. The storage capacitance electrode is at least partially overlapped with the pixel electrode and the storage capacitance electrode includes a branch. The branch is located at a side of the pixel electrode away from the data line and has a concavity. The concavity is located at a side of the branch adjacent to the data line. The drain compensating pattern is connected to the drain, and at least a portion of the drain compensating pattern is located inside the concavity. A portion of the branch at a side of the concavity away from the gate is not overlapped with the drain compensating pattern.

In an embodiment of the present invention, the branch is substantially aligned with the edge of the drain compensating pattern at a side of the concavity adjacent to the gate.

In an embodiment of the present invention, the branch of one pixel is partially overlapped with the edge of the drain compensating pattern at a side of the concavity adjacent to the gate, while the branch of the other pixel is not overlapped with the drain compensating pattern.

In an embodiment of the present invention, a first distance between the branch and the drain compensating pattern of each pixel at the side of the concavity away from the gate is, for example, larger than a second distance between the branch and the drain compensating pattern at a side of the concavity adjacent to the gate.

In an embodiment of the present invention, the storage capacitance electrode of each of the pixels is in a U-shape, and the storage capacitance electrode substantially surrounds the edge of the pixel electrode.

In an embodiment of the present invention, the active device of each of the pixels further includes a semi-conductor pattern located between the gate, the source, and the drain.

In an embodiment of the present invention, each of the gates is located inside a corresponding one of the scan lines.

In an embodiment of the present invention, the pixel set further includes a connecting pattern to electrically connect the two storage capacitance electrodes of the two pixels. For example, the connecting pattern and the two storage capacitance electrodes of the two pixels are formed integrally.

In an embodiment of the present invention, the drain compensating pattern and the drain in each of the pixels are formed integrally.

In an embodiment of the present invention, in each of the pixels, a width of the branch at a portion on which the concavity is located is smaller than that of the branch at the other portion.

In view of the above, a concavity is formed in the storage capacitance electrode of the pixel set according to the present invention, and the drain compensating pattern is extended into the concavity so as to compensate the variation of the gate-drain parasitic capacitance between the gate and the drain. Accordingly, the pixel set of the present invention can improve the display evenness of a display when the pixel set is applied to the display. In addition, the pixel set of the present invention needs no additional element so that the manufacturing cost is not increased.

In order to make the aforementioned and other features and advantages of the present invention more comprehensible, several embodiments accompanied with figures are described in detail below.

DESCRIPTION OF EMBODIMENTS

FIG. 3is a schematic top view of a pixel set according to an embodiment of the present invention. Referring toFIG. 3, a pixel set200includes two scan lines210A and210B, a data line220, and two pixels230A and230B. The two scan lines210A and210B are parallel to each other, and the data line220intersects with the two scan lines210A and210B. The two pixels230A and230B are located between the two scan lines210A and210B, and respectively at two opposite sides of the data line220. The two pixels230A and230B are respectively electrically connected to the two scan lines210A and210B.

The pixel230A includes an active device232A, a pixel electrode234A, a storage capacitance electrode236A and a drain compensating pattern238A. Similarly, the pixel230B also includes an active device232B, a pixel electrode234B, a storage capacitance electrode236B and a drain compensating pattern238B. In the present embodiment, the disposition relationship between every element of the pixel230A and the data line220and the disposition relationship between every element of the pixel230B and the data line220correspond to each other. Therefore, only the pixel230A is specifically described in the following.

The active device232A of the pixel230A is disposed adjacent to the data line220, and the active device232A includes a gate G, a drain D, and a source S. The gate G is electrically connected to a corresponding one of the scan lines210A. In addition, the active device232A further includes a semi-conductor pattern C located between the gate G, the source S and the drain D. In the present embodiment, the active device232A is located on the scan line210A. That is to say, the gate G of the pixel230A is located inside the scan line210A, and formed integrally with the scan line210A. The source S is electrically connected to the data line220. The source S and the drain D are located at the two sides of the gate G, respectively. The pixel electrode234A is electrically connected to the drain D.

The storage capacitance electrode236A is at least partially overlapped with the pixel electrode234A and the storage capacitance electrode236A includes a branch240A. The branch240A is located at a side of the pixel electrode234A away from the data line220, and has a concavity242A. The concavity242A is located at a side of the branch240A adjacent to the data line220, wherein a width of the branch240A at a portion on which the concavity242A is located is smaller than that of the branch240A at the other portion.

The drain compensating pattern238A is connected to the drain D, and at least a portion of the drain compensating pattern238A is located inside the concavity242A. A portion of the branch240A at a side of the concavity242A away from the gate G is not overlapped with the drain compensating pattern238A. In the present embodiment, the drain compensating pattern238A is, for example, formed integrally with the drain D. That is to say, the drain compensating pattern238A is extended away the data line220from the drain D, and bended along with the edge of the branch240A so as to be partially extended into the concavity242A.

In the present embodiment, the storage capacitance electrodes236A and236B of the pixels230A and230B respectively are in a U-shape, and the storage capacitance electrodes236A and236B substantially respectively surround the edges of the pixel electrodes234A and234B. The branch240A and the branch240B are substantially respectively one branch of the U-shaped storage capacitance electrode236A away from the data line220and one branch of the U-shaped storage capacitance electrode236B away from the data line220. In addition, the pixel set200further includes a connecting pattern250to electrically connect the two storage capacitance electrodes236A and236B. For example, the connecting pattern250and the two storage capacitance electrodes236A and236B are formed integrally. The U-shaped storage capacitance electrodes236A and236B are merely taken as examples in the present embodiment, and the present invention is not limited thereto.

According to formula (1) described in the description of related art, the gate-drain parasitic capacitance Cgdbetween the gate G and the drain D may have influence on the display quality of the display applying the pixel set200, while the area of the overlapping region between the gate G and the drain D is critical to the gate-drain parasitic capacitance Cgd. Therefore, the design of the pixel set200is preferable to make the area of the overlapping region between the gate G and the drain D in the pixel230A to be consistent to that in the pixel230B as shown inFIG. 3. At this moment, the branch240A is aligned with the edge of the drain compensating pattern238A at a side of the concavity242A adjacent to the gate G. In the other pixel230B, the branch240B is also aligned with the edge of the drain compensating pattern238B at a side of the concavity242B adjacent to the gate G

Certainly, the present invention is not limited to this embodiment. In other embodiments, the branch240A can be partially overlapped with the drain compensating pattern238A at a side of the concavity242A adjacent to the gate G. Meanwhile, the branch240B is also partially overlapped with the edge of the drain compensating pattern238B at a side of the concavity242B adjacent to the gate G. It is worthy to note that the area of the overlapping region between the branch240A and the drain compensating pattern238A is preferably equal to that between the branch240B and the drain compensating pattern238B.

The structure of the active device232A and that of the active device232B are substantially point asymmetric. If any displacement error is generated during the manufacturing process, the area of the overlapping region between the gate G and the drain D of the active device232A is different from those of the active device232B. At this time, the capacitance values of the gate-drain parasitic capacitances Cgdin the pixels230A and230B are different such that the display effect of the pixels230A and230B are influenced. In another word, the displacement error causes the uneven display effect of the display applying the pixel set200.

For compensating the negative influence of the displacement error, the pixel230A and the pixel230B of the present embodiment are disposed with the drain compensating patterns238A and238B. Moreover, the storage capacitance electrodes236A and236B of the pixel230A and the pixel230B in the present embodiment are configured with the concavity242A and the concavity242B, respectively. Once the position of the drains D are shifted due to the displacement error during the manufacturing process, the position of the drain compensating patterns238A and the position of the drain compensating pattern238B are changed correspondingly. At this moment, the areas of the overlapping regions between the gate G and the drain D in the pixel230A and in the pixel230B respectively are different. In addition, the area of the overlapping region between the drain compensating pattern238A and the branch240A is different from the area of the overlapping region between the drain compensating pattern238B and the branch240B. Accordingly, the variation of the gate-drain parasitic capacitance Cgdcaused by the displacement error can be compensated.

FIG. 4is a schematic top view of a pixel set according to another embodiment of the present invention. Referring toFIG. 4, the pixel set200′ is substantially the same to the above pixel set200, and the main differences therebetween are that the positions of the drain D, the source S, and the data line220in the pixel set200′ are shifted toward the direction of the arrow A corresponding to the scan lines210A and210B. That is to say, the elements of pixel200′ are the same as the elements of the pixel set200, but the dispositions of the corresponding elements in the pixel set200′ are different from those in the pixel set200.

Specifically, the scan line210A, the scan line210B, the storage capacitance electrode236A, and the storage capacitance electrode236B are formed by the same film layer when the pixel set200′ is manufactured, and thus they are patterned in the same process. Similarly, the drain D, the source S, the drain compensating pattern238A, the drain compensating pattern238B, and the data line220are formed by the same film layer, so that they are patterned in the same process. Therefore, if a displacement error along the direction of the arrow A is generated in one process, the patterns of the two film layers may be shifted to opposite directions, and then a structure such as the pixel set200′ is made. It is noted that the dispositions of the elements in the pixel set200′ are taken as examples, but the present invention is not limited thereto. If other displacement error is generated during the manufacturing process, the dispositions or the layout of the elements in the pixel200′ may be changed.

If no displacement error is generated during the manufacturing process, the area of the overlapping region between the gate G and the drain D in the pixel230A and that in the pixel230B are the same as that shown inFIG. 3. However, when the film layer of the drain D is shifted toward the direction of the arrow A corresponding to the scan line210A, the area of the overlapping region of the gate G and the drain D in the pixel230A is relatively reduced. Simultaneously, the area of the overlapping region between the gate G and the drain D in the pixel230B is relatively enlarged. Therefore, the gate-drain parasitic capacitance Cgdbetween the gate G and the drain D in the pixel230A is different from the gate-drain parasitic capacitance Cgdbetween the gate G and the drain D in the pixel230B accordingly so that the negative influence of the uneven displaying is caused.

In the present embodiment, the drain compensating pattern238A and the drain compensating pattern238B are also shifted toward the direction of the arrow A corresponding to the storage capacitance electrode236A and the storage capacitance electrode236B due to the displacement error during the manufacturing process. Therefore, in the pixel230B, the branch240B is partially overlapped with the drain compensating pattern238B at a side244B of the concavity242B adjacent to the gate G. Simultaneously, in the pixel230A, the branch240A is not overlapped with the drain compensating pattern238A. Specifically, in the pixel230A, a first distance d1between the branch240A and the drain compensating pattern238A at a side246A of the concavity242A away from the gate G is, for example, larger than a second distance d2between the branch240A and the drain compensating pattern238A at a side244A of the concavity242A adjacent to the gate G. Nevertheless, the present invention is not limited thereto, and the relationships between the first distance d1and the second distance d2are varied with the degree of the displacement error.

The displacements of the drain compensating pattern238A and the drain compensating pattern238B compensates the variations of the gate-drain parasitic capacitance Cgdbetween the gate G and the drain D in the two pixels230A and230B. In detail, the gate-drain parasitic capacitance Cgdin the pixel230A is smaller than a desired value, and the gate-drain parasitic capacitance Cgdin the pixel230B is larger than the desired value. Hence, according to formula (1) disclosed in the description of the related art, the feed-through voltage ΔVp of the pixel230B may be higher than that of the pixel230A without disposing the drain compensating pattern238A, the drain compensating pattern238B, the concavity242A, and the concavity242B in the pixel set200′. In the present embodiment, the capacitance coupling effect caused by partially overlapping the branch240B and the drain compensating pattern238B is conducive to enhance the storage capacitance Cst, and thus the feed-through voltage ΔVp of the pixel230B is reduced. Accordingly, the variations between the feed through voltages ΔVp of the pixel230A and the pixel230B are eliminated, and therefore, the display evenness of the pixel set200′ is improved.

Under the compensation of the drain compensating pattern238A, the drain compensating pattern238B, the concavity242A, and the concavity242B, the feed through voltages ΔVp of the pixel230A and the pixel230B are substantially the same. That is to say, the design of the present embodiment can efficiently compensate the negative influence on the display effect of the pixel set200′ caused by the displacement error. More specifically, in the pixel set200′ of the present embodiment, the drain compensating pattern238A, the drain compensating pattern238B, and the drains D are formed integrally, and are formed in the same manufacturing process. Therefore, any additional element is not needed. That is to say, the pixel set200′ of the present embodiment can compensate the negative influence due to the displacement error without increasing the cost.

In summary, the drain compensating pattern and the concavity of the branch in the storage capacitance electrode provide the compensation effect in the pixel set of the present invention so as to reduce the negative effect of the displacement error during the manufacturing process. Particularly, the displacement error during the manufacturing process makes the drains and the drain compensating patterns of the two pixels in the pixel set be shifted simultaneously, such that the capacitance values of the gate-drain parasitic capacitances and the storage capacitances of the two pixels are varied. Therefore, the feed through voltages of the two pixels are compensated and the pixel set of the present invention applied in a display has good display evenness. In addition, the drain compensating pattern in the present invention is extended from the drain and the branch is a part of the storage capacitance electrode, so the pixel set of the present invention is formed without adding any additional element. In other words, in addition to compensating the displacement error during the manufacturing process, the manufacturing method of the pixel set of the present invention is able to be compatible with the conventional manufacturing method of the pixel set without complicating the manufacturing process.