Image forming apparatus, method of controlling image forming apparatus and storage medium

An image forming apparatus includes a print head, a main control unit, a head control unit, and a head unit power supply to generate a voltage to be supplied to the head control unit. The main control unit checks whether the main control unit is normally started up. The head control unit includes an operation checker to check whether the head control unit normally operates if the main control unit is normally started up and the head control unit is supplied with a check voltage, a head power supply generator to generate a voltage to be supplied to the print head if the head control unit normally operates, and a status detector to detect a status of the print head based on the voltage supplied to the print head, and control the voltage to be supplied to the head control unit depending on the status detected by the status detector.

BACKGROUND OF THE INVENTION

Field of the Invention

The present invention relates to an image forming apparatus and a method and program of controlling an image forming apparatus.

Description of the Related Art

Heretofore, as for image forming apparatuses, there has been known a technique of detecting a breakdown by checking electric conditions in an image forming apparatus. Japanese Patent Laid-open No. 2012-050202 discloses a technique of checking whether a breakdown occurs in an image forming apparatus in the process of starting up a power supply circuit and a power supply device for supplying a voltage to a printing head (for example, a DC/DC converter, a pre-CHG circuit, or the like).

SUMMARY OF THE INVENTION

In recent years, the importance of the technique of detecting an apparatus status has been increasing and there has been a need for safer detection technique.

The present invention has an object to provide a safer detection technique.

The present invention provides an image forming apparatus including a print head, a first control unit configured to control the image forming apparatus; a second control unit configured to control the print head; and a first voltage generator circuit configured to generate a voltage to be supplied to the second control unit under control of the first control unit. The first control unit includes a startup check unit configured to check whether the first control unit is normally started up. The second control unit includes an operation checker configured to check whether the second control unit normally operates in a case where the startup check unit confirms that the first control unit is normally started up and the second control unit is supplied with a check voltage that is lower than a voltage for normal operation, a second voltage generator circuit configured to generate a voltage to be supplied to the print head from the check voltage in a case where it is confirmed that the second control unit normally operates, and a status detector configured to detect a status of the print head based on the voltage supplied to the print head. The first control unit controls the voltage to be supplied to the second control unit based on the status detected by the status detector.

DESCRIPTION OF THE EMBODIMENTS

Hereinafter, with reference to the attached drawings, the present invention is explained in detail in accordance with preferred embodiments. Configurations shown in the following embodiments are merely exemplary and the present invention is not limited to the configurations shown schematically.

In addition, as a supplement, the same configurations are described with the same reference numerals.

FIG. 1is a block diagram illustrating a configuration of an image forming apparatus according to the present embodiment. This block diagram illustrates a control configuration in the image forming apparatus. The image forming apparatus includes a main control unit10, a head control unit20, a head print unit30, a host device40, a display unit41, a regular power supply51, and a head unit power supply52. In addition, the host device40and the main control unit10are coupled to each other and the host device40and the head control unit20are coupled to each other via a network60through which they mutually transmit and receive control data.

The main control unit10mainly controls entire printing operations. As illustrated inFIG. 1, the main control unit10includes a power supply generator11, a main controller12, a RAM113, a ROM114, an external IF circuit15, an image processor16, and a communication IF117. The power supply generator11is fed with a logic power supply (+12 V) from the regular power supply51. The power supply generator11generates a voltage (for example, +5V/+3.3 V/+2.5 V/+1.0 V and the like) required in each of blocks in the main control unit10by using an ON/OFF switchable DC/DC converter, a regulator, and the like, and supplies the voltage to the corresponding block. Here, a power supply for the main controller12and a power supply for peripheral blocks are provided separately and power is supplied to the peripheral blocks under the control of the main controller12.

The main controller12includes a CPU, a LAN controller, a serial input/output (SIO) bus, an inter-integrated circuit (I2C) bus, and a port. The main controller12controls the entire image forming apparatus in accordance with a program and various parameters stored in the ROM114by using the RAM113as a work area.

For example, when a print process is ordered (executed) by an operation on a touch panel of the display unit41, the host device40outputs a print job to the main control unit10via the network60. In response to input of the print job from the host device40via the communication IF117, the main controller12controls the image processor16so that the image processor16performs predetermined image processing on the received image data. Then, the main controller12transmits the image data after the image processing by the image processor16to a print data generator24of the head control unit20by using a high-speed serial communication data IF61.

The image processor16is composed of, for example, an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), or the like. The image processor16divides the image data after the image processing by the host device40into data sets for respective colors for printing in the head print unit30, and transmits (transfers) the data set for each color to the corresponding head control unit20. Note that only one head control unit20is illustrated in the present embodiment for convenience of explanation, but in fact multiple head control units20are provided for the respective colors for use. In addition, as a data transfer method, the high-speed serial communication data IF61may use any of methods including, but not limited to, a universal serial bus (USB), PCI express, and the like, for example.

The main controller12checks the status of the power supply generator11, the internal state of the RAM113, and the status of the image processor16. When the main controller12confirms that the main control unit10is normally started up, the main controller12subsequently causes the head unit power supply52to start to output a power supply by controlling a circuit inside the external IF circuit15in order to start up the head control unit20. The head unit power supply52is an output-variable power supply (voltage generator circuit), which receives an analog signal (0 V to 5 V) from the external IF circuit15and linearly changes an output voltage up to 0 V to 32 V. Such a linear change (gradual change) of the voltage intends to avoid application of a high voltage and prevent a breakdown in the apparatus. The specifications in the present embodiment are set such that +5.5 V is supplied at the time of startup, but the voltage value is not particularly limited as long as the voltage can be confirmed to be safe.

The head control unit20performs printing control based on the received image data. The head control unit20includes a head unit controller21, a RAM222, a ROM223, the print data generator24, a head power supply generator25, and a head IF26. The head unit controller21prints the image data by controlling the entire head control unit20and the head print unit30in accordance with a program and various parameters stored in the ROM223while using the RAM222as a work area.

The print data generator24converts INDEX data transmitted from the image processor16into Bitmap data printable by the head. The head power supply generator25receives power for initial check and power for normal operation outputted from the head unit power supply52, and supplies the power to each of blocks (for example, a logic control circuit and the like) and the head print unit30.

The head IF26includes a head current detector that detects a head current to be supplied to the head print unit30. The head IF26controls input and output of head logic control signals62in order that a logic section (logic circuit)32may generate a timing signal33to be used to eject ink at a predetermined timing in the head print unit30. In addition, the head IF26controls provision of a head heater power supply63to a heater31. The processing in the head IF26is described later by usingFIG. 3.

The head print unit30includes the heater31that causes ink to be ejected by heating the ink and the logic section32that controls the timing of the ink ejection by the heater31. In the head print unit30, the logic section32outputs the timing signal33to the heater31in order that the head print unit30may eject ink at a predetermined timing. The specifications concerning the timing signal33are of a publicly known technique, and therefore the explanation thereof is omitted herein.

The display unit41is coupled to the host device40and displays conditions in the image forming apparatus. In addition, the display unit41is capable of receiving various commands (operations) for image processing by way of the touch panel or the like. Moreover, at the occurrence of a failure, the display unit41displays the name and the location of a portion having the failure, as described later.

Next, a configuration of the external IF circuit15is described usingFIG. 2.FIG. 2is a block diagram illustrating the configuration of the external IF circuit15. As illustrated inFIG. 2, the external IF circuit15includes a digital-to-analog converter (DAC)110, a watchdog timer (WDT)111, an AND circuit112, and a GATE circuit113.

The DAC110changes a power supply voltage for the head unit power supply52under the control of the main controller12(for example, by way of the I2C or SIO bus or the like). In the present embodiment, using +5 V, the DAC110changes the output (power supply voltage) between 0 V and 5 V.

After the main controller12is started up, the main controller12accesses the WDT111to clear the timer at predetermined timings (for example, every 5 ms, every 10 ms, or the like). Meanwhile, when the WDT111is not accessed for a certain period, a counter is not cleared and the WDT111reverses the output upon lapse of a set period. In the present embodiment, the initial value of the WDT111is ‘H’ and the WDT111outputs ‘L’ in a case where an anomaly occurs.

The AND circuit112is a circuit for operation check, which calculates the logical product of the signal from the WDT111, a power good (PGOOD) signal from the power supply generator11, and a Status signal from the image processor16, and outputs the calculation result (hereinafter, referred to as a startup check signal) to the main controller12. Then, if the calculation result is ‘H’ (in other words, if all the signals are ‘H’), the main controller12determines that the main control unit10is normally started up and starts processing of causing the head unit power supply52to output a voltage for initial check.

In order for the head unit power supply52to output the voltage for initial check, the main controller12performs port control when detecting that the aforementioned startup check signal outputted to the main controller12is ‘H’. Specifically, the main controller12first outputs a GATE release signal to the GATE circuit113and then outputs a power supply ON signal to the GATE circuit113. Under the port control of the main controller12, the GATE circuit113outputs a power supply ON-OUT signal so that the head unit power supply52is enabled to output power. After that, the main controller12writes output data to the DAC110by using the I2C bus mounted on the main controller12.

The DAC110has a resolution of 8 bits using +5 V, and performs output control of about 20 mV by 1 bit. The head unit power supply52outputs a voltage based on the voltage outputted from the DAC110. The head unit power supply52changes the output voltage linearly with respect to the voltage outputted from the DAC110. Here, as the head unit power supply, a usual one may be used, and for example, a power supply in HWS series manufactured by TDK-Lambda Corporation or the like may be used.

Next, the configurations of the head power supply generator25and the head IF26are described usingFIG. 3.FIG. 3is a block diagram illustrating the configurations of the head power supply generator25and the head IF26. As illustrated inFIG. 3, the head power supply generator25includes a head control logic section DC/DC converter251, a heater control logic DC/DC converter252, a head power supply DC/DC converter253, a head power supply relay254, a power supply control IC255, and a feedback (FB) resistor256.

The head control logic section DC/DC converter251generates logic power supplies for controlling the entire head control unit20from a VH power supply at a VH voltage of 0 V to 32 V outputted from the head unit power supply52. Specifically, the head control logic section DC/DC converter251generates +3.3 V_HL, +1.0 V, and +2.5 V power supplies for operating the head unit controller21.

The heater control logic DC/DC converter252generates, from the VH power supply, a power supply (+3.3 V_HB) to be fed to the logic section32of the head print unit30and a power supply (VHT)63for controlling the heater31.

The head power supply DC/DC converter253generates a head heater power supply63from the VH power supply and feeds the head power supply63to the heater31of the head print unit30. Here, the VH power supply to be fed to the head power supply DC/DC converter253is switchable between ON and OFF under control of the head unit controller21. Then, each of the DC/DC converters used in this block is composed of a known FET, inductor, diode, and capacitor, adjusts the voltage according to features of the head print unit30under control of the power supply control IC255, and outputs the adjusted voltage. Here, FET is an abbreviation for a field effect transistor.

The power supply control IC255is a power system manager (PSM). The power supply control IC255is equipped with multiple DACs and analog-to-digital converters (ADCs). As illustrated inFIG. 3, the power supply control IC255adjusts and monitors the voltage rising timing and the voltage of each of the power supplies including +3.3 V_HL, the head power supply, VHT, and +3.3 V_HB outputted from the DC/DC converters. In addition, the power supply control IC255manages faults, generates fault logs, and automatically stores the logs in an internal EEPROM.

Here, as the power supply control IC255, used is an IC capable of power supply management without addition of software. In other words, the power supply control IC255adjusts and monitors the above kinds of voltages by hardware control. For this reason, even if the head unit controller21becomes out of control, the power supply control IC255can perform fault control and stop the power supply in a case where, in spite of the control, any of the setting values of the above kinds of power supply voltages which are set inside the power supply control IC255is exceeded.

The FB resistor256adjusts the output voltage of the head power supply DC/DC converter253. Specifically, the voltage outputted from the head power supply DC/DC converter253toward the head print unit30is adjusted by applying a predetermined voltage to the FB resistor256by a FB_CNT signal outputted from a DAC of the power supply control IC255and thereby controlling the current flowing into the FB resistor256.

A VH_SNS resistance voltage-dividing circuit257divides the voltage (VH power supply) outputted from the head unit power supply52. The head unit controller21reads the voltage (VH_SNS) divided by the VH_SNS resistance voltage-dividing circuit257, and changes (adjusts) the head power supply to be fed to the head print unit30by way of the power supply control IC255based on the read voltage. Specifically, the power supply control IC255is controlled to adjust the voltage of the FB_CNT signal, thereby changing the head power supply.

The VH voltage is set to 32 V in the specifications, but the maximum output as a rated power supply may be set to 36 V. In this case, in the VH_SNS resistance voltage-dividing circuit257, a constant (a resistance ratio) is set such that the output of the VH_SNS signal to the head unit controller21may not exceed 3.3 V. In this regard, the resistance ratio in the case of supplying a voltage of 36 V is 9.9:1. Then, in the case of supplying a voltage of 32 V as the VH voltage, the voltage of the VH_SNS is 2.9 V. In the case of supplying a voltage of 5.5 V as the VH voltage, the voltage of the VH_SNS is 0.5 V.

Subsequently, the head IF26is described. As illustrated inFIG. 3, the head IF26is provided between the head power supply generator25and the head print unit30. The head IF26includes the head power supply current detector and a switch circuit265. The head power supply current detector functions as an example of a status detector that detects the status of the printing head, and includes a low resistance261, a current detector circuit262, an amplifier263, and an ADC264for A/D conversion of an output from the amplifier263. Meanwhile, the switch circuit265switches a signal outputted from the print data generator24and a signal to be inputted to the print data generator24(in other words, a leak voltage from the logic section32). Note that the head logic control signals62outputted from the switch circuit265include, for example, a DATA signal, a CLK signal, an LT signal, and the like, and cover all the signals for controlling the logic section32.

Description is given herein of an operation of detecting a head current by the above described configurations. As illustrated inFIG. 3, when a current (head current) flows into the low resistance261, a voltage difference occurs between the input and the output of the low resistance261. For example, in a case where a current at 1 A flows into the low resistance261under the conditions where the resistance value of the low resistance261is 0.1Ω and the input voltage is 10 V, the voltage is decreased by 0.1 V to an output voltage of 9.9 V due to the occurrence of a voltage difference between the input and the output of the low resistance261.

The current detector circuit262is a current sensor amplifier for monitoring the current from the voltage between the input and the output of the low resistance261. Here, the current detector circuit262may be formed by using a known detector circuit, and the explanation of the detailed operation of the current detector circuit262is omitted herein. The amplifier263adjusts a gain such that the output of the current detector circuit262can be within an input range of the ADC264. The ADC264performs A/D conversion of the output from the amplifier263.

The head unit controller21monitors the current value of the head power supply by accessing the ADC264by way of an SIO IF. After the startup, the head unit controller21controls the print data generator24to switch Head control signal input/output ports to the input mode. Then, in order to detect a leak voltage from the logic section32of the head print unit30, the switch circuit265is controlled such that an input/output port of the switch circuit265is switched to the input mode to enable the leak voltage from the logic section32to be inputted to the print data generator24.

When confirming (detecting) that there is no voltage leakage, the print data generator24switches the IF_CNT signal and switches the input/output port of the switch circuit265to the output mode (in other words, sets the input/output port to enable a signal to be outputted to the logic section32of the head print unit30). Moreover, the head unit controller21switches the Head control signal input/output ports of the print data generator24to the output mode. In this regard, an input circuit of the switch circuit265has a power down protection function, and an IF capable of receiving an input voltage up to +5.5 V is used for a logic power supply of +3.3 V.

Next, a processing procedure executed by the main control unit10of the image forming apparatus is described by using a flowchart inFIGS. 4A and 4B. In the explanation of the flowchart, sign “S” represents step. This also applies in explanation for the following flowchart.

At S101, the main controller12executes boot processing and develops parameters on the RAM113based on the data in the ROM114. Along with this, the main controller12initializes the input/output of the internal port, a transfer rate and a transfer scheme of the SIO for accessing the DAC110of the external IF circuit15, a LAN IF, and an internal timer circuit.

When detecting the completion of all the initialization of them, the main controller12enables the peripheral IF and controls the port to turn on a DC/DC converter in the power supply generator11at S102in order to feed the power supplies to the peripheral blocks.

At S103, the main controller12enables the internal timer circuit and accesses the WDT111periodically at intervals of 5 ms to clear the timer of the WDT111. At S104, the main controller12enables the block that executes image processing. The image processor16is composed of the ASIC, FPGA, or the like as described above. For example, when the image processor16is composed of an FPGA, the main controller12preforms data transfer processing for making internal data available. The image processor16outputs a signal indicating the completion of the initialization as the Status signal.

At S105, the main controller12determines whether the hardware of the main control unit10is normally started up by monitoring the output result (the startup check signal) of the WDT111, the power supply generator11, and the image processor16as described above. When the startup check signal is ‘L’ at S105, the main controller12advances the processing to S115. At S115, the main controller12notifies the host device40of an initialization error of the main control unit10or records error information to the RAM113and the ROM114, and then advances the processing to wait processing in an error status. The ROM114used herein is assumed to be a flash ROM and is capable of recording the error information. This also applies to the ROM described below.

When the startup check signal is ‘H’ at S105, the main controller12determines that the system is normally started up, and sets the head unit power supply52to an output-enabled status in order to start up the head control unit20. In this case, the main controller12transmits data ‘0’ to the DAC110via the SIO and sets the power supply voltage output to the head unit power supply52to 0 V (in other words, initializes the power supply voltage output).

At S106, the main controller12controls the port to switch the output of the GATE release signal from ‘L’ to ‘H’. Thus, the GATE circuit113is enabled to output a power supply ON signal as a power supply ON-OUT signal to the head unit power supply52.

At S107, the main controller12controls the port such that the power supply ON signal may be outputted to the GATE circuit113, and thereby sets the head unit power supply52to a voltage output (application) enabled status by way of the GATE circuit113. At S108, the main controller12transmits predetermined data to the DAC110, and thereby sets the head unit power supply52to output +5.5 V. In this step, 2C (hex) is written as the predetermined data to the DAC110and the DAC110linearly outputs 0.86 V. Here, when the processing at S108is completed, processing at S201inFIG. 5Adescribed later is started.

At S109, the main controller12reads a power supply Error signal as an input signal. When the power supply Error signal is ‘L’, the main controller12determines that the head unit power supply52has an anomaly and advances the processing to S116. At S116, the main controller12notifies the host device40that the head unit power supply52has the anomaly, records the error information to the RAM113and the ROM114, and advances to the wait processing in the error status.

When the main controller12does not detect an error (anomaly) in the head unit power supply52at S109, the main controller12advances the processing to S110. At S110, the main controller12checks whether a head unit initial check completion notification transmitted from the head unit controller21of the head control unit20via the communication IF117is received. Note that the processing at S110is executed in response to completion of processing at S404inFIG. 7A.

At S111, the main controller12checks whether there is an error from initial check information concerning the head unit initial check completion notification. Specifically, the main controller12checks whether the head unit initial check completion notification is received from the head unit controller21within a predetermined period or whether an error is reported in the head unit initial check completion notification.

When the head unit initial check completion notification is not received within the predetermined period or the error is reported in the head unit initial check completion notification as a result of checking the initial check information at S111, the main controller12advances the processing to S117. At S117, the main controller12sets ‘L’ in the port of the power supply ON signal in order to turn off the power supply output of the head unit power supply52, thereby suspends the power supply output of the head unit power supply52, and then advances to the wait processing in the error status. In this regard, even when the error status is reported by the head unit controller21, the power supply does not have to be turned off in some cases depending on the error. In such a case, the main controller12may perform control without turning off the power supply.

Meanwhile, when the notification that the initialization of the head control unit20is completed and the head control unit20and the head print unit30are normally started up is received from the head unit controller21at S111, the main controller12advances the processing to S112. At S112, the main controller12executes output processing of the head power supply voltage for normal operation. In this processing, the main controller12controls the SIO of the main controller12to output E0(hex) to the DAC110in order to cause the head unit power supply52to output 28 V. Thus, the DAC110outputs 4.375 V, and the head unit power supply52outputs 28 V to the head control unit20.

At S113, the main controller12checks (determines) whether a notification that the normal voltage of 28 V is outputted is received from the head unit controller21. Then, when determining that the notification is received, the main controller12advances to stand-by processing at S114, and waits for transmission of print data from the host device40. In this processing, the processing of feeding the normal head power supply may be started after the print data is received.

Next, a processing procedure executed by the head control unit20of the image forming apparatus is described by using a flowchart inFIGS. 5A, 5B, 6, 7A and 7B. At S201, the head unit controller21executes boot processing and develops parameters on the RAM222based on the data in the ROM223. Along with this, the head unit controller21initializes the input/output of an internal port and an ADC internally provided to monitor a voltage of an inputted VH power supply (VH_SNS). In addition, the head unit controller21initializes a transfer rate and a transfer scheme of an I2C bus for accessing the print data generator24and the power supply control IC255of the head power supply generator25, and initializes an internal LAN IF and a communication IF227.

After completion of the boot processing, the head unit controller21reads the voltage of the ADC and checks the voltage of the inputted VH power supply (more exactly, VH_SNS) at S202. At S203, the head unit controller21determines whether the head unit power supply52normally supplies the voltage for initial check. Specifically, the head unit controller21determines whether the read value of the ADC is within a range of 5.5 V±5%. When the read voltage of the ADC is not within the range of 5.5 V±5%, the head unit controller21determines that the voltage outputted from the head unit power supply52is not the voltage for initial check, and advances the processing to S211.

Since the outputted voltage is determined not to be the voltage for initial check at S210, the head unit controller21notifies the host device40of the determination result and records the error information to the RAM222and ROM223at S211. At S212, the head unit controller21terminates the head unit initial check, and advances to the wait processing in the error status.

On the other hand, when the read voltage of the ADC is within the range of 5.5 V±5%, the head unit controller21determines that the voltage outputted from the head unit power supply52is the voltage for initial check of +5.5 V at S203. At S204, the head unit controller21checks a status of the power supply control IC255(I2C_IF0signal) to check whether the power supply control IC255normally operates.

At S205, the head unit controller21determines whether the power supply control IC255is in a normally operating status. When detecting at S205an anomaly as the status of the power supply control IC255, the head unit controller21advances the processing to S213. Since the power supply control IC255is determined not to be in the normally operating status at S204, the head unit controller21notifies the host device40of the determination result and records the error information to the RAM222and ROM223at S213. At S214, the head unit controller21terminates the head unit initial check, and advances to the wait processing in the error status. The host device40causes the display unit41to display, as indicating the detection of the power control IC error, the error of the board on which the power supply control IC255is mounted in the head control unit20, and prompts replacement of the board on which the head power supply generator25is mounted.

Meanwhile, when the head unit controller21confirms at S205that the power supply control IC255normally operates and an operation of monitoring the voltages and the like normally runs, the head unit controller21advances the processing to S206. At S206, the head unit controller21starts a head check sequence and causes the heater control logic DC/DC converter252to output a voltage of +3.3 V_HB by controlling an internal register of the power supply control IC255. After that, the head unit controller21similarly causes the heater control logic DC/DC converter252to output a voltage of VHT by controlling the internal register of the power supply control IC255. Moreover, the head unit controller21controls an IF_CNT signal by accessing the print data generator24via the I2C bus, and thereby performs control to switch the switch circuit265to a mode for outputting signals to the print data generator24.

At S207, the head unit controller21monitors the power supply control IC255and checks whether the power supply voltage of +3.3 V_HB is normally outputted (applied). When determining (detecting) at S207that the power supply voltage of +3.3 V_HB is not normally outputted, the head unit controller21advances the processing to S215.

Since it is detected at S207that the head logic power supply is not normally outputted, the head unit controller21executes head logic power supply error notification processing at S215. Specifically, the head unit controller21notifies the host device40of the head logic power supply error, and records the error information to the RAM222and the ROM223. At S216, the head unit controller21terminates the head unit initial check, and advances to the wait processing in the error status. The host device40causes the display unit41to display, as indicating the detection of the +3.3 V_HB error, the error of the board on which the heater control logic DC/DC converter252is mounted in the head control unit20, and prompts replacement of the board on which the head power supply generator25is mounted.

Meanwhile, when detecting that the power supply at +3.3 V_HB (power supply to be fed to the logic section32) is normally outputted at S207, the head unit controller21advances the processing to S208. At S208, the head unit controller21monitors the power supply control IC255and checks whether the outputted VHT (power supply for controlling the heater31) is normally outputted.

When detecting at S209that the VHT is not normally outputted, the head unit controller21advances the processing to S217. Since it is detected that the heater control logic power supply is not normally outputted, the head unit controller21executes heater control logic error notification processing at S217. Specifically, the head unit controller21notifies the host device40of the error and records the error information to the RAM222and the ROM223. At S218, the head unit controller21terminates the head unit initial check, and advances to the wait processing in the error status. The host device40causes the display unit41to display, as indicating the detection of the VHT power supply error, the error of the board on which the heater control logic DC/DC converter252is mounted in the head control unit20, and prompts replacement of the board on which the head power supply generator25is mounted.

Meanwhile, when detecting at S209that the VHT is normally outputted, the head unit controller21advances the processing to S210in order to check whether the head power supply DC/DC converter253can normally operate. At S210, the head unit controller21controls the port of the head unit controller21to turn on the head power supply relay254, and starts check processing for supplying the head power supply DC/DC converter253with +5.5 V.

Proceeding toFIG. 6, before the head power supply relay254is controlled to turn on (before the VH power supply starts to be fed to the head power supply DC/DC converter253), the head unit controller21checks an SNS signal terminal of the power supply control IC255and determines whether a voltage leaks to the head power supply at S301. Here, the SNS signal terminal is a signal terminal for +3.3 V_HL, the head power supply, VHT, and +3.3 V_HB, which are to be inputted to the power supply control IC255. When there is a voltage leakage of several V, which is not supposed to be outputted to the head power supply, the head unit controller21determines that the voltage leakage occurs in the head print unit30at S301and advances the processing to S305.

At S305, the head unit controller21notifies that the heater31is anomalous. Further, at S306, the head unit controller21sets, in the RAM222, a flag that indicates that an anomaly occurs in the heater31. Also when the anomaly of the heater31is detected, the head unit controller21subsequently controls the head power supply DC/DC converter253in order to detect details of the error and thereby confirms the details of the error. To this end, the processing is advanced to S302.

Meanwhile, when no voltage leaks to the head power supply (no voltage is detected) at S301, the processing is also advanced to S302. In sum, when the head logic power supply (+3.3 V_HB) and the heater control logic power supply (VHT) are normally outputted, the processing is advanced to S302.

At S302, the head unit controller21controls the port to turn on the head power supply relay254and supplies the head power supply DC/DC converter253with +5.5 V in order to check whether the head power supply DC/DC converter253can normally operate.

At S303, the head unit controller21monitors the head power supply outputted from the head power supply DC/DC converter253via the power supply control IC255, and checks whether the head power supply is fed only by turning on the head power supply relay254. When detecting at S303that the head power supply is fed with only the head power supply relay254turned on, the head unit controller21determines that the head power supply DC/DC converter253is short-circuited, and turns off the head power supply relay254at S307.

At S308, the head unit controller21executes anomaly error notification processing for the head power supply DC/DC converter253. Specifically, the head unit controller21notifies the host device40of the anomaly error for the head power supply DC/DC converter253, and records the error information to the RAM222and the ROM223. At S309, the head unit controller21terminates the head unit initial check, and advances to the wait processing in the error status.

The host device40causes the display unit41to display, as indicating the detection of the head power supply error, the error of the board on which the head power supply DC/DC converter253is mounted in the head control unit20, and prompts replacement of the board on which the head power supply generator25is mounted. In addition, along with this, when previously notified of an anomaly of the heater31, the host device40makes a notification of the anomaly of the head print unit30to prompt head replacement.

Meanwhile, when detecting at S303that the head power supply is not fed under the condition where only the head power supply relay254is turned on, the head unit controller21controls the register of the power supply control IC255to cause the head power supply DC/DC converter253to output a predetermined voltage at S304. In this operation, the power supply control IC255outputs the FB_CNT signal by controlling the internal DAC while monitoring the output of the head power supply, thereby changes the current of the FB resistor256configured to adjust the output voltage of the head power supply DC/DC converter253, and thus adjusts the output voltage to +5 V.

When +5 V is outputted as the head power supply, the head unit controller21controls the internal I2C IF to read the voltage of the ADC264of the head IF26. When the head power supply is not fed to the heater31of the head print unit30(in other words, when no current flows into the low resistance261), the voltage value of the ADC264is substantially 0 V. Meanwhile, when the head power supply is fed to the heater31of the head print unit30(in other words, when a current flows into the low resistance261), the voltage of the ADC264is a predetermined voltage or above.

Proceeding toFIG. 7A, when determining at S401that the voltage of the ADC264is substantially 0 V and the head power supply is not fed to the heater31of the head print unit30, the head unit controller21advances the processing to S402. At S402, the head unit controller21checks statuses of signals inputted as the Head control signals to the print data generator24, and thereby detects whether a voltage leaks to the logic section32. At S402, the head unit controller21determines that no voltage leaks from the heater31to the logic section32when all the Head control signals inputted to the print data generator24are substantially 0 V.

At S403, the head unit controller21recognizes completion of the initial check with the VH power supply set to +5.5 V, controls the register of the power supply control IC255to thereby switch the VH_ON signal to be inputted to the head power supply DC/DC converter253to ‘L’, and thus turns off the head power supply output. At S404, the head unit controller21issues a head unit initial check completion notification to the main controller12via the communication IF227. When the processing at S404is completed, the processing at S110inFIG. 4Bis executed as above described.

At S405, the head unit controller21monitors the value of VH_SNS and thereby checks whether the main controller12of the main control unit10has changed (controlled) the output of the head unit power supply52from +5.5 V to +32 V. When the head unit controller21confirms (determines) at S406that the output of the head unit power supply52has been changed to +32 V, the head unit controller21advances the processing to S407.

At S407, the head unit controller21controls the DAC of the power supply control IC255to adjust the voltage output of the FB_CNT, thereby setting the voltage to be outputted from the head power supply DC/DC converter253to +24 V. At S408, the head unit controller21waits for a print command from the main controller12.

Meanwhile, when determining at S401that the voltage of the ADC264is the predetermined voltage or above and the head power supply is fed to the heater31of the head print unit30, the head unit controller21advances the processing to S409. Here, the predetermined voltage is a voltage not reachable even if a subtle voltage such as noise is added to 0 V.

Proceeding toFIG. 7B, at S409, the head unit controller21detects the input statuses of the Head control signals inputted to the print data generator24and thereby detects whether a voltage leaks from the heater31to the logic section32. When determining that the voltage leaks from the heater31to the logic section32as a result of the detection, the head unit controller21advances the processing to S410. Specifically, the head unit controller21reads the input statuses of the Head control signals inputted to the print data generator24, determines that the voltage leaks (in other words, there is a failure) when any one of the ports is ‘H’, and advances the processing to S410.

At S410, for safety, the head unit controller21controls the register of the power supply control IC255to set the VH_ON signal to be inputted to the head power supply DC/DC converter253to ‘L’, thereby turning off the head power supply output. Moreover, since it is determined that the voltage leaks from the heater31to the logic section32, the head unit controller21determines at S411that the heater31and the board logic section have an anomaly. Then, the head unit controller21executes head and head control board error notification processing. Specifically, the head unit controller21notifies the host device40of a head and head control board error, prompts replacement of the head print unit30and the board (head control unit20), and records the error information to the RAM222and the ROM223. At S412, the head unit controller21terminates the head unit initial check, and advances to the wait processing in the error status.

When determining at S409that no voltage leaks from the heater31to the logic section32as a result of the detection, the head unit controller21advances the processing to S413. Specifically, the head unit controller21reads the values of the Head control signals inputted to the print data generator24, determines that no voltage leaks from the heater31to the logic section32when all the read values are substantially 0 V, and advances the processing to S413.

At S413, the head unit controller21determines that only the head has a failure, and for safety, controls the register of the power supply control IC255to set the VH_ON signal to be inputted to the head power supply DC/DC converter253to ‘L’, thereby turning off the head power supply output for safety. Then, at S414, the head unit controller21determines that an anomaly occurs in the heater31of the head print unit30, and executes head heater error notification processing. Specifically, the head unit controller21notifies the host device40of the head heater error, causes the display unit41to display a prompt to replace the head print unit30, and records the error information to the RAM222and the ROM223. At S415, the head unit controller21terminates the head unit initial check, and advances to the wait processing in the error status.

Meanwhile, at S402, the head unit controller21determines that a voltage leaks from the heater31to the logic section32when any of the Head control signals inputted to the print data generator24is ‘H’. At S416, the head unit controller21controls the power supply control IC255to stop the output of the head power supply DC/DC converter253. At S417, by controlling the power supply control IC255, the head unit controller21individually stops each of VHT and +3.3 V_HB from being outputted from the heater control logic DC/DC converter252to check whether there is a leakage from each of the power supply outputs. The head unit controller21checks the levels of the Head control signals at S418and advances the processing to S419when confirming a voltage leakage under the condition where each of the outputs of the heater control logic DC/DC converter252is off.

At S419, the head unit controller21determines that the board (head control unit20) itself is broken. Then, the head unit controller21notifies the host device40and the main controller12via the communication IF227that the board anomaly occurs, causes the display unit41to display a prompt to replace the board on which the switch circuit265is mounted, and records the error information to the RAM222and the ROM223. At S420, the head unit controller21terminates the head unit initial check, and advances to the wait processing in the error status. At the time of the above notification, if the head unit controller21detects the flag that indicates the heater anomaly in the RAM222, the head unit controller21also makes a notification of information concerning a warning indicating that the head print unit30possibly has the anomaly. It is also easily conceivable to repeat the check processing again in response to this information concerning the warning.

Meanwhile, the head unit controller21checks the levels of the Head control signals at S418and advances the processing to S421when confirming no voltage leakage under the condition where each of the outputs of the heater control logic DC/DC converter252is off. At S421, the head unit controller21determines that the logic section32of the head print unit30is broken. Then, the head unit controller21notifies the host device40and the main controller12via the communication IF227of the occurrence of the head anomaly and information on the concerned power supply block (VHT or +3.3 V_HB), and causes the display unit41to display a prompt to replace the head print unit30. In addition, along with this, the head unit controller21records the error information to the RAM222and the ROM223. At S420, the head unit controller21terminates the head unit initial check, and advances to the wait processing in the error status.

Other Embodiments

According to the present invention, it is possible to safely start up the entire circuits in the image forming apparatus.

This application claims the benefit of Japanese Patent Application No. 2019-146237, filed Aug. 8, 2019 which is hereby incorporated by reference wherein in its entirety.