Method of fabricating an integrated circuit device

A method for fabricating an integrated device is disclosed. A protective layer is formed over a gate structure when forming epitaxial (epi) features adjacent to another gate structure uncovered by the protective layer. The protective layer is thereafter removed after forming the epitaxial (epi) features. The disclosed method provides an improved method for removing the protective layer without substantial defects resulting. In an embodiment, the improved formation method is achieved by providing a protector over an oxide-base material, and then removing the protective layer using a chemical comprising hydrofluoric acid.

BACKGROUND

The present disclosure relates generally to an integrated circuit (IC) device and, more particularly, to a method for forming a complementary metal oxide semiconductor (CMOS) structure.

As technology nodes shrink, in some IC designs, there has been a desire to incorporate strained engineering, including a SiGe, a SiC, a SiP and/or a Si epitaxial (epi) process, in the formation process of CMOS devices to overcome Moore's law.

There are challenges to implementing such epi features and processes in CMOS fabrication. As technology nodes continue to decrease in size, particularly to the 22 nanometer (nm) technology node and below, the defect issue is one of the key challenges for forming the epi film. The defects may result from a removal process for removing a protective layer after the formation of epi lightly doped source/drain (LDD) features and/or epi source/drain (S/D) features. The defects which result in the CMOS device may impact the yield of device.

DETAILED DESCRIPTION

The present disclosure relates generally to manufacturing integrated circuit devices and, more particularly, to protective layers used during the manufacturing processes for the integrated circuit devices.

With reference to FIGS.1and2-15, a method100and a semiconductor device200are collectively described below. The semiconductor device200illustrates an integrated circuit, or a portion thereof, that can comprise memory cells and/or logic circuits. The semiconductor device200can include passive components such as resistors, capacitors, inductors, and/or fuses; and active components, such as P-channel field effect transistors (PFETs), N-channel field effect transistors (NFETs), metal-oxide-semiconductor field effect transistors (MOSFETs), complementary metal-oxide-semiconductor transistors (CMOSs), high voltage transistors, and/or high frequency transistors, other suitable components, and/or combinations thereof. It is understood that additional steps can be provided before, during, and/or after methods disclosed, and some of the steps described below can be replaced or eliminated, for additional embodiments of the method. It is further understood that additional features can be added in the semiconductor devices disclosed, and some of the features described below can be replaced or eliminated, to disclose additional embodiments.

Referring toFIGS. 1 and 2, the method100begins at step102wherein a substrate210is provided. In the depicted embodiment, the substrate210is a semiconductor substrate including silicon. The substrate210may be a p-type or n-type substrate. Alternatively, the substrate210comprises another elementary semiconductor, such as germanium; a compound semiconductor including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and/or indium antimonide; an alloy semiconductor including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and/or GaInAsP; or combinations thereof. In yet another alternative, the substrate210is a semiconductor on insulator (SOI). In other alternatives, semiconductor substrate210may include a doped epi layer, a gradient semiconductor layer, and/or a semiconductor layer overlying another semiconductor layer of a different type, such as a silicon layer on a silicon germanium layer.

The substrate210may include various doped regions depending on design requirements (e.g., p-type wells or n-type wells). The doped regions may be doped with p-type dopants, such as boron or BF2; n-type dopants, such as phosphorus or arsenic; or a combination thereof. The doped regions may be formed directly on the substrate210, in a P-well structure, in an N-well structure, in a dual-well structure, or using a raised structure. The substrate210may further include various active regions, such as regions configured for an N-type metal-oxide-semiconductor transistor device (referred to as an NMOS) and regions configured for a P-type metal-oxide-semiconductor transistor device (referred to as a PMOS). It is understood that the semiconductor device200may be formed by CMOS, NFET, and/or PFET technology processing, and thus some processes are not described in detail herein.

An exemplary isolation feature212is formed in the substrate210to isolate various regions of the substrate210, and in the present embodiment, to isolate the NMOS and PMOS device regions. The isolation feature212also isolates the device regions from other devices (not shown). The isolation feature212utilizes isolation technology, such as local oxidation of silicon (LOCOS) and/or shallow trench isolation (STI), to define and electrically isolate the various regions. In the present embodiment, the isolation feature212includes an STI. The isolation feature212comprises silicon oxide, silicon nitride, silicon oxynitride, other suitable materials, or combinations thereof. The isolation feature212is formed by any suitable process. As one example, forming an STI includes a photolithography process, etching a trench in the substrate (for example, by using a dry etching and/or wet etching), and filling the trench (for example, by using a chemical vapor deposition process) with one or more dielectric materials. In some examples, the filled trench may have a multi-layer structure, such as a thermal oxide liner layer filled with silicon nitride or silicon oxide.

A material layer is formed over the substrate. The material layer includes one or more material layers comprising any suitable material and thickness. The material layer can include interfacial layers, capping layers, diffusion/barrier layers, adhesion layers, other suitable layers, and/or combinations thereof. The material layer is formed by any suitable process including chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), high density plasma CVD (HDPCVD), metal organic CVD (MOCVD), remote plasma CVD (RPCVD), low-pressure CVD (LPCVD), plasma enhanced CVD (PECVD), plating, other suitable methods, and/or combinations thereof. The semiconductor device200may include one or more antireflective coating layers, such as a top antireflective coating layer and/or a bottom antireflective coating layer.

In one embodiment, the material layer includes a gate dielectric layer214, a gate electrode layer216, and a hard mask layer218. The gate dielectric layer214is formed over the substrate210by any suitable process to any suitable thickness. The gate dielectric layer214includes a dielectric material, such as silicon oxide, silicon oxynitride, silicon nitride, a high-k dielectric material, other suitable dielectric material, or combinations thereof. Exemplary high-k dielectric materials include HfO2, HfSiO, HfSiON, HfTaO, HfSiO, HfZrO, other suitable materials, or combinations thereof. The gate dielectric layer214may include a multilayer structure. For example, the gate dielectric layer214may include an interfacial layer, and a high-k dielectric material layer formed on the interfacial layer. An exemplary interfacial layer may be a grown silicon oxide layer formed by a thermal process or ALD process.

The gate electrode layer216is formed over the gate dielectric layer214by any suitable process to any suitable thickness. In the present embodiment, the gate electrode layer216is a polycrystalline silicon (polysilicon) layer. The polysilicon layer may be doped for proper conductivity. Alternatively, the polysilicon is not necessarily doped if a dummy gate is to be formed and replaced in a subsequent gate replacement process. Alternatively, the gate electrode layer216could include a conductive layer having a proper work function; therefore, the gate electrode layer216can also be referred to as a work function layer. The work function layer comprises any suitable material, such that the layer can be tuned to have a proper work function for enhanced performance of the associated device. For example, if a p-type work function metal (p-metal) for the PFET device is desired, TiN or TaN may be used. On the other hand, if an n-type work function metal (n-metal) for the NFET device is desired, Ta, TiAl, TiAlN, or TaCN, may be used. The work function layer may include doped conducting oxide materials. The gate electrode layer216may include other conductive materials, such as aluminum, copper, tungsten, metal alloys, metal silicide, other suitable materials, or combinations thereof. For example, where the gate electrode layer216includes a work function layer, another conductive layer can be formed over the work function layer.

The hard mask layer218is formed over the gate electrode layer216by any suitable process to any suitable thickness. The hard mask layer218, in one embodiment, includes silicon oxide. The hard mask layer218, in another embodiment, may include silicon nitride (SiN), silicon oxynitride (SiON), silicon carbide (SiC), SiOC, spin-on glass (SOG), a low-k material, tetraethylorthosilicate (TEOS), plasma enhanced CVD oxide (PE-oxide), high-aspect-ratio-process (HARP) formed oxide, amorphous carbon material, other suitable materials, and/or combinations thereof. The silicon oxide layer may be formed using methods such as CVD, PVD, or ALD and may have a thickness ranging from about 300 Angstroms to about 800 Angstroms.

Referring toFIGS. 1 and 3, the method100proceeds to step104in which a patterning process is applied to the hard mask layer218, the gate electrode layer216, and the gate dielectric layer214to form a gate structure for a PMOS device200A and a gate structure for a NMOS device200B. Each gate structure comprises, in order, a gate dielectric214, a gate electrode216, and a hard mask218. The patterning process, for example, includes forming a layer of photoresist (not shown) over the hard mask layer218by a suitable process, such as spin-on coating, and then exposing and developing the layer of photoresist to form a photoresist feature. Then, pattern of the photoresist feature can be transferred to the underlying gate dielectric layer214, the gate electrode layer216, and the hard mask layer218to form the gate structures by a dry etching process. Additionally, an anti-reflective coating (ARC) layer (not shown) may be formed on the hard mask layer218and under the layer of photoresist to enhance a subsequent patterning process. The photoresist feature may be stripped thereafter. It is understood that the above examples do not limit the processing steps that may be utilized to form the gate structures.

Referring toFIGS. 1 and 4, the method100proceeds to step106in which a first protective layer220is formed over the substrate210, the gate structures of the PMOS device200A and the NMOS200B. The first protective layer220may comprise a top protective layer220aand a bottom protective layer220b. The top protective layer220amay function as a protector to prevent or decrease epi, polycrystalline, or amorphous film from being formed thereon during a subsequent epi growth process. The bottom protective layer220bmay function as a buffer layer to provide an etching selectivity between the top protective layer220aand the hard mask218.

In some embodiments, the top protective layer220ais a nitrogen-containing and silicon-containing layer. In the present embodiment, the top protective layer220ais silicon nitride. The top protective layer220amay be formed by a process comprising an LPCVD process, a PECVD process, an ALD process, or combinations thereof. In the depicted embodiment, the top protective layer220ahas a thickness ranging between about 50 Angstroms and about 500 Angstroms. In some embodiments, the bottom protective layer220bincludes a material different from the top protective layer220aor the hard mask218. The bottom protective layer220b, for example, is silicon oxide and/or oxynitride, formed by LPCVD, PECVD, ALD, or the like. The bottom protective layer220bhas a thickness ranging between about 10 Angstroms and about 100 Angstroms.

Referring toFIG. 5, the portion of first protective layer220which is over the NMOS device200B is removed by a removing process to expose the substrate210around the gate structure of NMOS device200B. The removing process, for example, is an etching process. In some embodiments, the etching process is a two-step dry etching process, including a first step for removing a portion of the top protective layer220aand a second step for removing an underlying portion of the bottom protective layer220b. The first step of etching, for example, is performed using an etching gas of Cl2, HBr, CH2F2, CHF3, CF4, or combinations thereof. The second step of etching, for example, is performed using an etching gas of CH2F2, CHF3, CF4, or combinations thereof. Meanwhile, another portion of the first protective layer220which is over the PMOS device200A is not removed by the etching process because of a protector222thereon. The protector222, for example, is a photoresist pattern. In some embodiments, the protector222is removed by a stripping process after removing the first protective layer220over the NMOS device200B.

Referring toFIGS. 1 and 6, the method100proceeds to step108in which lightly doped source/drain (LDD) features224are formed in the NMOS device200B. In the depicted embodiment, the LDD features224are adjacent to the gate structure for the NMOS device200B. In the depicted embodiment, the LDD features224are on the substrate210referred as raised epi features with a top surface higher than the surface of the substrate210. In one embodiment, the LDD features224include a semiconductor material that is the same as the substrate210. In another embodiment, the LDD features224include silicon (Si). In the depicted embodiment, the LDD features224are formed by an epi growth process. The epi growth process may include a selective epitaxial growth (SEG) process, CVD deposition techniques (e.g., vapor-phase epitaxy (VPE) and/or ultra-high vacuum CVD (UHV-CVD)), molecular beam epitaxy (MBE), other suitable epi processes, or combinations thereof. The epi process may use gaseous and/or liquid precursors, which may interact with the composition of the substrate210.

Referring toFIGS. 1 and 7, the method100proceeds to step110in which the first protective layer220over the PMOS device200A is removed by an etching process. In the depicted embodiment, the etching process is a three-step process. The three-step process, for example, comprises a first step referred to as a passivating step, a second step referred to as a stripping step, and a third step referred to as a cleaning step. In some embodiments, the three-step process is performed in the equipment designed for single-wafer processing. In alternative embodiments, the three-step process is performed in equipment used for bench-type processes. The three-step process may be performed in three separated tanks/chambers or performed within a single tank/chamber.

The first step of the etching process for removing the first protective layer220over the PMOS device200A, in some embodiments, is performed using a chemical to form a passivation layer (not shown) over the isolation feature212and/or the hard mask218in the NMOS device200B. In some embodiments, the chemical trends to react with hydroxyl groups on the surface of oxide-based materials, such as the isolation feature212and/or the hard mask218in the NMOS device200B, therefore to form the passivation layer. In the depicted embodiment, the chemical comprises hexamethyldisilazane (HMDS), trimethylsilyl chloride (TMSC), or the like. In the depicted embodiment, the chemical is introduced in the processing tank/chamber for a period of time ranging from about 30 seconds to about 120 seconds. In some embodiments, a portion of the chemical is left (or absorbed) on the surfaces of oxide-based materials to form the passivation layer thereon. In some embodiments, the passivation layer has a thickness ranging from about 5 Angstroms and about 50 Angstroms. The passivation layer may prevent the isolation feature212and/or the hard mask218from being damaged in a subsequent stripping process. In some embodiments, the first step process is performed at a temperature ranging from about 23° C. to about 80° C.

The second step of an etching process is subsequently carried out. In some embodiments, the second step of the etching process is performed using a chemical comprising hydrofluoric acid (HF). In some embodiments, a diluted hydrofluoric acid (DHF) vapor is applied to the surface of substrate210. In some embodiments, the DHF vapor comprises a HF vapor and a carrier gas (e.g., N2). In the depicted embodiment, the concentration of HF vapor in the DHF vapor ranges between about 30% and about 50%. In some embodiments, the second step process is performed at a temperature less than about 100° C. In the depicted embodiment, the second step process is performed at a temperature ranging from about 23° C. to about 80° C. The second step process may last for a period of time ranging from about 30 seconds to about 120 seconds. In some embodiments, the DHF vapor further comprises isopropyl alcohol (IPA) with a designed concentration (e.g., less than about 10 wt %) to change the absorbability of DHF vapor on the surface of substrate210, therefore, to change the etching rate of the DHF vapor. In alternative embodiments, the DHF vapor is replaced by a DHF solution for the second step of etching process. The DHF solution, for example, is prepared by mixing a liquid HF with de-ionized water (DIW).

In embodiments, the DHF vapor/solution used in the second step provides a high etching rate to the first protective layer220, e.g., greater than about 100 Angstrom/min. In embodiments, the DHF vapor/solution used in the second step has a low etching rate (e.g., less than about 1 Angstrom/min.) to the epi features, such as LDD features224. Therefore, the DHF vapor/solution may provide a high etching selectivity (e.g., greater than about 100) between the first protective layer220and the LDD features224in the second step, which can remove the first protective layer220without substantially damaging the LDD features224. In addition, the isolation feature212and/or the hard mask218is not substantially removed in the second step of etching process because of the protection of the passivation layer formed in the first step of etching process as mentioned above.

In some embodiments, the third step of etching process is provided for removing particles resulted in the prior two steps of etching process after removing the first protective layer220over the PMOS device200A. In some embodiments, the third step is performed using a chemical comprising ammonia-peroxide mixture (APM) with a designed concentration, e.g., NH4OH:H2O2:H2O=1:1:50. In some embodiments, the third step is performed at a temperature ranging from about 23° C. to about 60° C. and lasting for a period of time from about 30 seconds to about 120 seconds.

Still referring toFIG. 7, the method100proceeds to step112in which spacers226are formed adjoining sidewalls of the gate structures of the PMOS device200A and the NMOS device200B. In some embodiments, spacers226are formed over at least a portion of the LDD features224adjacent to the sidewalls of the gate structures of the NMOS device200B. In the depicted embodiment, spacers226may be formed by blanket depositing a dielectric spacer layer (not shown), such as a silicon nitride layer, over the PMOS device200A and the NMOS device200B, and then the dielectric layer is anisotropically etched to form the spacers226. Alternatively, liners (not shown) may be included under the spacers226by forming a dielectric liner layer, e.g., a silicon oxide layer, under the spacer layer, and then the spacer layer and the liner layer are etched in sequence to form the spacers226and the underlying liners. In still another embodiment, the spacers226may include other dielectric materials, such as silicon oxide, silicon oxynitride, or combinations thereof.

Referring toFIGS. 1,8, and9, the method100proceeds to step114in which a second protective layer228is formed over the NMOS device200B. Referring to FIG.8, the second protective layer228is formed over the substrate210, the gate structures of the PMOS device200A and the NMOS200B. The second protective layer228may comprise a top protective layer228aand a bottom protective layer228b. The top protective layer228aand the bottom protective layer228bmay have functions the same as the top protective layer220aand the bottom protective layer220bas mentioned above. In some embodiments, the top protective layer228aand the bottom protective layer228bare formed by processes the same as the processes for forming the top protective layer220aand the bottom protective layer220bas mentioned above.

Referring toFIG. 9, the portion of the second protective layer228which is over the PMOS device200A is removed by a removing process to expose the underlying substrate210around the gate structure of PMOS device200A. The removing process, for example, is an etching process. In some embodiments, the etching process is a two-step dry etching process, including a first step for removing the portion of the top protective layer228aand a second step for removing the underlying bottom protective layer228b. The first and second etching steps may be the same as the process for removing the portion of the first protective layer220over the NMOS device200B as mentioned above. Another portion of the second protective layer228over the NMOS device200B is not removed in the etching process because of being covered by a protector230. The protector230, for example, is a photoresist pattern. In some embodiments, the protector230is removed by a stripping process after removing the second protective layer228over the PMOS device200A.

Referring toFIGS. 1,10, and11, the method100proceeds to step116in which source/drain engineering is performed to configure the source/drain regions of the PMOS device region200A. InFIG. 10, the exposed portions of the substrate210, particularly in the source and drain regions of the PMOS device200A, are then removed by an etching process to form recesses232in the substrate210. In some embodiments, the etching process includes a dry etching process, wet etching process, or combination thereof. In the depicted embodiment, the etching process utilizes a combination of dry and wet etching processes. The dry etching process, for example, includes an etching gas of NF3, Cl2, SF6, He, Ar, CF4, or combinations thereof. The wet etching solution may include NH4OH, HF, TMAH (tetramethylammonium hydroxide), other suitable wet etching solutions, or combinations thereof. After the etching process, a pre-cleaning process may be performed to clean the recesses232with a HF solution or other suitable solution.

InFIG. 11, a semiconductor material is formed in the recesses232to form source and drain features (S/D) (strained structures)234of the PMOS device200A. The source and drain features234may alternatively be referred to as raised source and drain regions. In the depicted embodiment, an epi process is provided to form the semiconductor material in the recesses232. In some embodiments, the source and drain features234are formed from a material different from the substrate210. Accordingly, the channel region of the PMOS device200A is strained or stressed to enable carrier mobility of the device and enhance device performance. In the depicted embodiment, silicon germanium (SiGe) is formed in the recesses232by an epi process to form SiGe source and drain features234in a crystalline state on the silicon substrate210. The SiGe source and drain features234may alternatively be referred to as raised source and drain regions. The source and drain features234associated with the gate structure of the PMOS device200A may be in-situ doped or undoped during the epi process. When the source and drain features are undoped, it is understood that they may be doped in a subsequent process. The doping may be achieved by an ion implantation process, plasma immersion ion implantation (PIII) process, gas and/or solid source diffusion process, other suitable process, or combinations thereof. The source and drain features234may further be exposed to annealing processes, such as a rapid thermal annealing process.

Still referring toFIGS. 1 and 11, the method100proceeds to step118in which the portion of the second protective layer228over the NMOS device200B is thereafter removed by an etching process. In the depicted embodiment, the etching process is a three-step process. The three-step process, for example, comprises a first step referred to as a passivating step, a second step referred to as a stripping step, and a third step referred to as a cleaning step. The three-step process may be performed in the equipment for single-wafer processes, or alternatively can be performed in the equipment for bench-type processes. The three-step process may be performed in three separated tanks/chambers, or alternatively can be performed within one tank/chamber.

The three-step process for removing the second protective layer228over the NMOS device200B may be the same as the three-step process for removing the first protective layer220over the PMOS device200A as mentioned above. For example, the first step of etching process may form a passivation layer (not shown) over the isolation feature212and/or the hard mask218in the PMOS device200A to prevent them from being damaged in a subsequent stripping process. For example, the second step of etching process removes the portion of the second protective layer228over the NMOS device200B using a DHF vapor or DHF solution. In the depicted embodiment, the DHF vapor or DHF solution has a low etching rate to the epi features, such as the source and drain features234. Therefore, the DHF vapor or DHF solution may provide a high etching selectivity between the second protective layer228and the source and drain features234(e.g., greater than about 100). In addition, the DHF vapor or DHF solution may remove the second protective layer228without substantially attacking the isolation feature212and/or the hard mask218in the PMOS device200A because of the protection of the passivation layer formed in the first step of the etching process as mentioned above. After the portion of the first protective layer220over the NMOS device200B has been removed, the third step of etching process is provided for cleaning the semiconductor device200.

Referring toFIGS. 1,12, and13, the method100proceeds to step120in which a third protective layer236is formed over the PMOS device200A. Referring toFIG. 12, the third protective layer236is formed over the substrate210, the gate structures of the PMOS device200A and the NMOS200B. The third protective layer236may comprise a top protective layer236aand a bottom protective layer236b. The top protective layer236aand the bottom protective layer236bmay have functions that are the same as the functions of top protective layer220aand bottom protective layer220bas mentioned above. The top protective layer236aand the bottom protective layer236bmay be provided by the same processes as the processes for forming the top protective layer220aand the bottom protective layer220bas mentioned above.

Referring toFIG. 13, the portion of the third protective layer236over the NMOS device200B is removed by a removing process to expose the underlying substrate210around the gate structure of NMOS device200B. The removing process, for example, is an etching process. In some embodiments, the etching process is a two-step dry etching process, including a first step for removing the portion of the top protective layer236aand a second step for removing the underlying portion of the bottom protective layer236b. The first and second etching steps may be performed by the same process as the process for removing the portion of the first protective layer220over the NMOS device200B as mentioned above. Another portion of the third protective layer236over the PMOS device200A is not removed in the etching process because of being covered by a protector238. The protector238, for example, is a photoresist pattern. In some embodiments, the protector238is thereafter removed by a stripping process.

Referring toFIGS. 1,14, and15, the method100proceeds to step122in which source/drain engineering is performed to configure the source/drain regions of the NMOS device region200B. InFIG. 14, the exposed portions of the substrate210, particularly in the source and drain regions of the NMOS device200B, are then removed by an etching process to form recesses240in the substrate210. In some embodiments, the etching process includes a dry etching process, wet etching process, or combination thereof. In the depicted embodiment, the etching process utilizes a combination of dry and wet etching processes. The dry etching process, for example, includes an etching gas of NF3, Cl2, SF6, He, Ar, CF4, or combinations thereof. The wet etching solution may include NH4OH, HF, TMAH (tetramethylammonium hydroxide), other suitable wet etching solutions, or combinations thereof. After the etching process, a pre-cleaning process may be performed to clean the recesses240with a HF solution or other suitable solution.

InFIG. 15, a semiconductor material is formed in the recesses240to form source and drain features (strained structures)242of the NMOS device200B. In the depicted embodiment, the source and drain features242include epitaxially grown silicon (epi Si). The epi Si source and drain features242associated with the gate structure of the NMOS device200B may be in-situ doped or undoped during the epi process. For example, the epi Si source and drain features242may be doped with phosphorous to form Si:P source and drain features or doped with carbon to form Si:C source and drain features. When the source and drain features are undoped, it is understood that they may be doped in a subsequent process. The doping may be achieved by an ion implantation process, plasma immersion ion implantation (PIII) process, gas and/or solid source diffusion process, other suitable process, or combinations thereof. The source and drain features242may alternatively be referred to as raised source and drain regions. The source and drain features242may further be exposed to annealing processes, such as a rapid thermal annealing process.

Still referring toFIGS. 1 and 15, the method100proceeds to step124in which the portion of the third protective layer236over the PMOS device200A is removed by an etching process. In the depicted embodiment, the etching process is a three-step process. The three-step process, for example, comprises a first step referred to as a passivating step, a second step referred to as a stripping step, and a third step referred to as a cleaning step. The three-step process may be performed by a single-wafer process or a bench-type process. The three-step process may be performed in three separated tanks/chambers or performed in one tank/chamber.

The three-step process for removing the third protective layer236over the PMOS device200A may be the same as the three-step process for removing the first protective layer220over the PMOS device200A as mentioned above. For example, the first step of etching process may form a passivation layer (not shown) over the isolation feature212and/or the hard mask218in the NMOS device200B to prevent them from being damaged in a subsequent stripping step. For example, the second step of etching process removes the portion of the third protective layer236over the PMOS device200A using a vapor or DHF solution. The vapor or DHF solution has a low etching rate to the epi features, such as the source and drain features242. Therefore, the vapor or DHF solution may remove the third protective layer236without substantially attacking the source and drain features242. In addition, the isolation feature212and/or the hard mask218in the NMOS device200B are not substantially removed by covering the passivation layer formed in the first step. As mentioned above, the third step of etching process may be thereafter provide for cleaning the semiconductor device200.

Subsequent processing may implement a gate replacement process. For example, metal gates may replace the gate electrode (i.e., polysilicon gate layer) of the gate structures of the PMOS/NMOS devices. A first metal gate having a first work function may be formed in the gate structure of the NMOS devices and a second gate structure having a second work function may be formed in the gate structure of the PMOS devices. The metal gates may comprise any suitable material including aluminum, copper, tungsten, titanium, tantalum, tantalum aluminum, tantalum aluminum nitride, titanium nitride, tantalum nitride, nickel silicide, cobalt silicide, silver, TaC, TaSiN, TaCN, TiAl, TiAlN, WN, metal alloys, other suitable materials, and/or combinations thereof.

Subsequent processing may form various contacts/vias/lines and multilayer interconnect features (e.g., metal layers and interlayer dielectrics) on the substrate, configured to connect the various features or structures of the semiconductor device. The additional features may provide electrical interconnection to the device. For example, a multilayer interconnection includes vertical interconnects, such as conventional vias or contacts, and horizontal interconnects, such as metal lines. The various interconnection features may implement various conductive materials including copper, tungsten, and/or silicide. In one example, a damascene and/or dual damascene process is used to form a copper related multilayer interconnection structure.

The various embodiments of the present disclosure discussed above offer advantage over other methods known to the inventors, it being understood that no particular advantage is required for all embodiments, and that different embodiments may offer different advantages. One of the advantages is that the defects or particles resulted from the etching process for removing the protective layers may be improved (reduced). Another advantage is that the etching selectivity between the protective layer and epi features may be enhanced, therefore, the etching process may remove the protective layer without substantially attacking the epi features. Therefore, loss of epi features can be controlled. Another advantage is that the hard mask of the gate structure and STI can be protected by a passivation layer, therefore preventing damage in the etching process for removing the protective layer.

One form of the present disclosure involves a method of fabricating an integrated circuit device. The method includes: providing a substrate having a first region and a second region; forming a first gate structure in the first region and a second gate structure in the second region; forming a protective layer over the first gate structure; forming features adjacent to opposite portions of the second gate structure by an epitaxial (epi) growth process; and removing the protective layer, wherein the step of removing comprises: forming a protector over the second gate structure; and performing an etching process using a chemical comprising hydrofluoric acid (HF).

Another form of the present disclosure involves a method of fabricating a CMOS device. The method includes: providing a semiconductor substrate with a shallow trench isolation (STI) feature; forming a first gate structure and a second gate structure overlying the semiconductor substrate and separated by the STI feature; forming spacers adjoining opposite sidewalls of the first and the second gate structures; forming a protective layer overlying the first and the second gate structures; removing a portion of the protective layer over the second gate structure, but leaving another portion of the protective layer over the first gate structure; forming epi features in the semiconductor substrate adjacent to edges of the opposite spacers of the second gate structure; thereafter introducing a chemical to react with surface of the STI feature; and thereafter removing the portion of the protective layer over the first gate structure.

Another form of the present disclosure involves a method of fabricating a CMOS device. The method includes: providing a semiconductor substrate with an isolation feature therein; forming a first and a second gate structures over the semiconductor substrate; forming raised features on the semiconductor substrate at either side of the second gate structure; forming spacers adjoining sidewalls of the first and second gate structures and over at least a portion of the raised features; forming a protective layer over the first and the second gate structures; removing a portion of the protective layer over the first gate structure, but leaving another portion of the protective layer over the second gate structure; forming recesses in the semiconductor substrate at either side of the first gate structure; epitaxially (epi) growing a semiconductor material to fill the recesses; forming protectors over the first gate structure and the isolation feature; removing the portion of the protective layer over the second gate structure using a chemical comprising hydrofluoric acid (HF); and performing a cleaning process.