Method for adjusting signal generator and signal generator

Monitoring a spectrum of an inter-leaved signal by a signal generator which inter-leaves two DAC outputs with the same sampling rate, while adjusting the output offset level of each DAC, the output amplitude level of each DAC, the output selection timing of each DAC, and the output renewal timing of each DAC.

FIELD OF THE INVENTION

The present invention pertains to digital-to-analog conversion technology and in particular, to inter-leaved digital-to-analog conversion technology.

DISCUSSION OF THE BACKGROUND ART

A high-speed digital-to-analog converter is needed for the high-speed generation of waveforms as necessary. The digital-to-analog converters with the fastest conversion rate made by an available art are difficult to obtain because they are not on the general market and they are very expensive when compared to commercial products. Therefore, digital-to-analog conversion devices are inter-leaved in order to avoid such problems (for instance, refer to U.S. Pat. No. 6,356,224). This inter-leaving has an advantage in that a commercial digital-to-analog converter that has a relatively low conversion rate and is inexpensive can be used. Conventional converters are also set forth in the following: JP Unexamined Patent Application (Kokai) 5-276,036, JP Unexamined Patent Application (Kokai) 11-195,988, JP Unexamined Patent Application (Kokai) 2002-217,732, and JP Unexamined Patent Application (Kokai) 2002-246,910.

On the other hand, the following problems can occur with inter-leaving. For instance, there are cases wherein, although it is small, there is a difference in performance between inter-leaved digital-to-analog converters. Moreover, even though inter-leaved digital-to-analog converters momentarily have exactly the same properties, it is difficult to always maintain this state. Furthermore, there are cases wherein the output signals of digital-to-analog converters cannot be switched at uniform intervals. That is, by means of conventional inter-leaving, signal precision is sacrificed for high-speed conversion. Therefore, an object of the present invention is to provide technology for generating signals with less distortion than in the past.

SUMMARY OF THE INVENTION

Therefore, by means of the present invention, the signal spectrum after inter-leaving in a signal generator is monitored while adjusting the output offset level of each DAC, the output amplitude level of each DAC, the output selection timing of each DAC, and the output renewal timing of each DAC. The present invention is a method for the adjustment of a signal generator for inter-leaving a first digital-to-analog converter and a second digital-to-analog converter operated under the same sampling rate and outputting signals obtained by synthesizing the output signals of the first and the second digital-to-analog converters, characterized in that it comprises a first step for adjusting the output offset of these first and second digital-to-analog converters such that when a direct current of the same level has been output from the first and second digital-to-analog converters, or when signals that do not contain a frequency component of this sampling rate have been output as these synthesized signals, the level in the spectrum of these synthesized signals of the frequency component that is the same as this sampling rate becomes lower than a first predetermined level or becomes the minimum, and a second step for adjusting the output level of these first and second digital-to-analog converters such that when signals of a first predetermined frequency have been output as these synthesized signals, the level in the spectrum of these synthesized signals becomes the same for two frequency components separated by this first predetermined frequency from the frequency that is the same as this sampling rate; the difference between these two levels becomes less than a second predetermined value or becomes the minimum; or the sum of these two levels becomes less than a third predetermined value or becomes the minimum, wherein the second step is repeated until the signal integrity value, when signals of the second predetermined frequency have been output as synthesized signals, satisfies a predetermined condition, e.g., less than a fourth predetermined level or becomes the minimum.

The method of the present invention may further comprise a third step for adjusting timing by which the output signals of said first digital-to-analog converter are renewed such that when signals of a third predetermined frequency have been output from this first digital-to-analog converter and a direct current has been output from this second digital-to-analog converter, the level of this third frequency component becomes the maximum in the spectrum of these synthesized signals, and a fourth step for adjusting timing by which the output signals of this second digital-to-analog converter are renewed such that when a direct current has been output from this first digital-to-analog converter and signals of a fourth predetermined frequency are output from this second digital-to-analog converter, the level of this fourth predetermined frequency component in the spectrum of these synthesized signals becomes the maximum, wherein these second, third, and fourth steps are repeated until the signal integrity value, when signals of this second predetermined frequency have been output as synthesized signals, satisfies a predetermined condition, e.g., less than this fourth predetermined value or becomes the minimum.

Preferably, the third step comprises adjusting the phase of clock signals applied to this first digital-to-analog converter in order to adjust this timing, and this fourth step comprises adjusting the phase of clock signals applied to this second digital-to-analog converter in order to adjust this timing.

This method may further comprise a fifth step for adjusting timing by which are selected the output signals of these first and second digital-to-analog converters such that when signals of a fifth predetermined frequency have been output as these synthesized signals, the level in the spectrum of these synthesized signals becomes less than a fifth predetermined level or becomes the minimum for two frequency components that are separated by this fifth predetermined frequency from the frequency component that is the same as this sampling rate, wherein these second, third, fourth, and fifth steps are repeated until this signal integrity satisfies a predetermined condition, e.g., less than this fourth predetermined value or becomes the minimum.

Preferably, the signal generator has a selector for selecting the output signals of these first and second digital-to-analog converters, and the fifth step comprises changing the duty ratio of the signals applied to this selector for this selecting.

Preferably, the first step is also repeated until the signal integrity value, when signals of a second predetermined frequency have been output as these synthesized signals, satisfies a predetermined condition, e.g., less than a fourth predetermined value or becomes the minimum.

Another embodiment according to the present invention includes a method for the adjustment of a signal generator for inter-leaving a first and a second digital-to-analog converter that operate under the same sampling frequency and outputting signals obtained by synthesizing output signals of these first and second digital-to-analog converters, characterized in that it comprises a step for adjusting the output offset of these first and second digital-to-analog converters such that when a direct current of the same level is output from these first and second digital-to-analog converters, or when signals that do not contain a frequency component of this sampling rate are output as these synthesized signals, the level in the spectrum of these synthesized signals of the frequency component that is the same as this sampling rate becomes less than a predetermined value or becomes the minimum.

Still yet another embodiment according to the present invention is a method for the adjustment of a signal generator for inter-leaving a first and a second digital-to-analog converter that operate under the same sampling rate and outputting signals obtained by synthesizing the output signals of these first and second digital-to-analog converters, characterized in that it comprises a step for adjusting the output level of these first and second digital-to-analog converters such that when signals of a predetermined frequency have been output as these synthesized signals, the level in the spectrum of the synthesized signals becomes the same for two frequency components separated by this predetermined frequency from the frequency that is the same as this sampling rate; the difference between these two levels becomes less than a first predetermined value or becomes the minimum; or the sum of these two levels becomes less than a second predetermined value or becomes the minimum.

Another embodiment includes a method for the adjustment of a signal generator for inter-leaving a first and a second digital-to-analog converter that operate under the same sampling rate and outputting signals obtained by synthesizing the output signals of these first and second digital-to-analog converters, characterized in that it comprises a step for adjusting the timing with which are selected the output signals of these first and second digital-to-analog converters such that when signals of a predetermined frequency have been output as synthesized signals, the level in the spectrum of these synthesized signals of two frequency components separated by this predetermined frequency from the frequency that is the same as this sampling rate becomes less than a predetermined value or becomes the minimum.

A further embodiment includes a method for the adjustment of a signal generator for inter-leaving a first and a second digital-to-analog converter that operate under the same sampling rate and outputting signals obtained by synthesizing the output signals of these first and second digital-to-analog converters, characterized in that it comprises a third step for adjusting timing by which the output signals of the first digital-to-analog converter are renewed such that when signals of a first predetermined frequency have been output from this first digital-to-analog converter and a direct current has been output from this second digital-to-analog converter, the level of this first predetermined frequency component in the spectrum of these synthesized signals becomes the maximum; and a fourth step for adjusting the timing by which the output signals of this second digital-to-analog converter are renewed such that when a direct current has been output from this first digital-to-analog converter and signals of a second predetermined frequency have been output from this second digital-to-analog converter, the level of this second predetermined frequency component in the spectrum of these synthesized signals becomes the maximum.

The present invention also includes a device that is a signal generator for inter-leaving a first and a second digital-to-analog converter that operate under the same sampling rate and outputting signals obtained by synthesizing the output signals of these first and second digital-to-analog converters, characterized in that it has a control device that executes a first step for adjusting the output offset of these first and second digital-to-analog converters such that when a direct current of the same level has been output from these first and second digital-to-analog converters, or signals that do not contain a frequency component of this sampling rate have been output as synthesized signals, the level in the spectrum of these synthesized signals of the frequency component that is the same as this sampling rate becomes lower than a first predetermined value or becomes the minimum, and a second step for adjusting the output level of these first and second digital-to-analog converters such that when signals of a first predetermined frequency have been output as these synthesized signals, the level in the spectrum of the synthesized signals is the same for two frequency components separated by this predetermined frequency from the frequency that is the same as this sampling rate; the difference between these two levels becomes less than the first predetermined value or becomes the minimum; or the sum of these two levels becomes less than a second predetermined value or becomes the minimum, wherein this second step is repeated until the signal integrity value, when signals of a second predetermined frequency have been output as these synthesized signals, satisfies a predetermined condition, e.g., less than a fourth predetermined value or becomes the minimum.

The control device of the present invention may also execute a third step for adjusting the timing by which output signals of this first digital-to-analog converter are renewed such that when signals of a third predetermined frequency have been output from this first digital-to-analog converter and a direct current has been output from this second digital-to-analog converter, the level of this third predetermined frequency in the spectrum of these synthesized signals becomes the maximum and a fourth step for adjusting the timing by which output signals of this second digital-to-analog converter are renewed such that when a direct current has been output from this first digital-to-analog converter and signals of a fourth predetermined frequency have been output from this second digital-to-analog converter, the level of this fourth predetermined frequency component in the spectrum of these synthesized signals becomes the maximum, wherein these second, third, and fourth steps are repeated until the signal integrity value, when signals of this second predetermined frequency have been output as these synthesized signals, satisfies a predetermined condition, e.g., less than this fourth predetermined value or becomes the minimum.

The third step typically comprises adjusting the phase of clock signals applied to this first digital-to-analog converter in order to adjust this timing, and this fourth step comprises adjusting the phase of clock signals applied to this second digital-to-analog converter in order to adjust this timing.

The control device further executes a fifth step for adjusting timing by which are selected the output signals of these first and second digital-to-analog converters such that when signals of a fifth predetermined frequency have been output as these synthesized signals, the level in the spectrum of these synthesized signals becomes lower than a fifth predetermined level or becomes the minimum for two frequency components that are separated by this fifth predetermined frequency from the frequency component that is the same as this sampling rate, wherein these second, third, fourth, and fifth steps are repeated until this signal integrity value satisfies a predetermined condition, e.g., less than this fourth predetermined value or becomes the minimum.

The signal generator has a selector for selecting the output signals of these first and second digital-to-analog converters, and this fifth step comprises changing the duty ratio of the signals applied to this selector for this selecting.

Optionally, the first step is repeated until the signal integrity when signals of a second predetermined frequency have been output as these synthesized signals satisfies a predetermined condition, e.g., less than a fourth predetermined value or becomes the minimum.

The present invention also pertains to a signal generator for inter-leaving a first and a second digital-to-analog converter that operate under the same sampling frequency and outputting signals obtained by synthesizing output signals of these first and second digital-to-analog converters, characterized in that it comprises a control device for adjusting the output offset of these first and second digital-to-analog converters such that when a direct current of the same level is output from these first and second digital-to-analog converters, or when signals that do not contain a frequency component of this sampling rate are output as these synthesized signals, the level in the spectrum of these synthesized signals of the frequency component that is the same as this sampling rate becomes lower than a predetermined value or becomes the minimum.

Another embodiment of the present invention includes a signal generator for inter-leaving a first and a second digital-to-analog converter that operate under the same sampling rate and outputting signals obtained by synthesizing the output signals of these first and second digital-to-analog converters, characterized in that it comprises a control device for adjusting the output level of these first and second digital-to-analog converters such that when signals of a predetermined frequency have been output as these synthesized signals, the level in the spectrum of the synthesized signals becomes the same for two frequency components separated by this predetermined frequency from the frequency that is the same as this sampling rate; the difference between these two levels becomes less than a first predetermined value or becomes the minimum; or the sum of these two levels becomes less than a second predetermined value or becomes the minimum.

Still yet a further embodiment includes a signal generator for inter-leaving a first and a second digital-to-analog converter that operate under the same sampling rate and outputting signals obtained by synthesizing the output signals of these first and second digital-to-analog converters, characterized in that it comprises a control device for adjusting the timing with which are selected the output signals of these first and second digital-to-analog converters such that when signals of a predetermined frequency have been output as synthesized signals, the level in the spectrum of these synthesized signals of two frequency components separated by this predetermined frequency from the frequency that is the same as this sampling rate becomes lower than a predetermined value or becomes the minimum.

A further embodiment includes a signal generator for inter-leaving a first and a second digital-to-analog converter that operate under the same sampling rate and outputting signals obtained by synthesizing the output signals of these first and second digital-to-analog converters, characterized in that it comprises a control device that executes a step for adjusting timing by which the output signals of this first digital-to-analog converter are renewed such that when signals of a first predetermined frequency have been output from this first digital-to-analog converter and a direct current has been output from this second digital-to-analog converter, the level of this first predetermined frequency component in the spectrum of these synthesized signals becomes the maximum; and a fourth step for adjusting the timing by which the output signals of this second digital-to-analog converter are renewed such that when a direct current has been output from this first digital-to-analog converter and signals of a second predetermined frequency have been output from this second digital-to-analog converter, the level of this second predetermined frequency component in the spectrum of these synthesized signals becomes the maximum.

By means of the present invention, it is possible to generate signals with less distortion that in the past by inter-leaved digital-to-analog conversion.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

Embodiments of the present invention will now be described while referring to the attached drawings. The first embodiment of the present invention is a signal generator100. Refer toFIG. 1.FIG. 1is a block drawing showing the internal structure of signal generator100. Signal generator100comprises a digital-to-analog converter110, a digital-to-analog converter120, a phase converter130, a phase converter140, a clock signal source150, a selector160, a device170for changing the duty ratio, and a compensator180. The digital-to-analog converter in the drawing is indicated by DAC. The clock signal source is shown by the clock block.

Clock signal source150is a device for generating clock signals C1having a frequency of 5 GHz. Clock signals C1are applied to DAC110via phase converter130; DAC120via phase converter140; and selector160via a device170for changing the duty ratio. Phase converters130and140are devices for converting the phase of the input signals by a specific angle and outputting the conversion results. Phase converters130and140change the amount of phase conversion in response to outside control. Device170for changing the duty ratio is a device for adjusting the duty ratio of input signals and outputting the adjustment results C2. Output signal Saof DAC110and output signal Sbof DAC120are applied to selector160. DAC110and DAC120adjust the level and offset of output signals Saand Sbunder outside control. Adjustment of the level here means that the amplitude level of the output signals is adjusted without adjusting the digital data or the digital data stream that will be given to the DAC. Selector160is the device for selecting either output signal Saor Sbin accordance with the output signal level of device170for changing the duty ratio and outputting the selected signals. By means of the present embodiment, selector160outputs output signal Sawhen the logic level of clock signal C2is L and outputs output signal Sbwhen the logic level of clock signal C2is H. As a result, synthesized signals Sxthat include either output signal Saor Sbare generated based upon the output of selector160. Compensator180is the device that monitors output signals Sxof the selector and controls other devices based on these results. Compensator180comprises a measuring part181for analyzing the spectrum of output signals Sxof the selector and a control part182for controlling the outside devices based on the analysis results of measuring part181. The spectrum analysis system of measuring part181can be a Fourier transform system such as used in an FFT analyzer, or a sweep system such as used in a spectrum analyzer. Control part182controls DAC110, DAC120, phase converter130, phase converter140, and device170for changing the duty ratio.

Next, the procedure for adjusting signal generator100and increasing the signal integrity of synthesized signals Sxwill be described. Degradation of signal integrity of synthesized signals Sxoccurs as a result of mismatching of the amplitude level between DACs, mismatching of the offset level between the DACs, or mistiming of selection of the output signals of a DAC by selector160. Consequently, the present invention adjusts each structural unit and each signal inside signal generator100while monitoring the spectrum of synthesized signals Sx. Refer toFIG. 2as well asFIG. 1.FIG. 2is a flow chart showing the procedure by which the signal integrity of synthesized signals Sxis improved.

First, in step S10, control part182adjusts the output offset levels of DAC110and DAC120such that the frequency component that is the same 5 GHz that is the sampling rate of DAC110and DAC120becomes less than the predetermined value TH1or becomes the minimum in the spectrum of synthesized signals Sxanalyzed by measuring part181. DAC110and DAC120at this time output a direct current of the same level or alternating current signals wherein synthesized signals Sxdo not contain a 5 GHz component. Refer toFIG. 3.FIG. 3is the spectrum of synthesized signals Sxwhen the offset level is mismatched between DAC110and DAC120. It is clear fromFIG. 3that 5 GHz is an unnecessary component. By means of this step, the level of the component of this 5 GHz is lower than the predetermined value TH1.

Next, in step S11, a sine wave of 1 GHz is output to signal generator100as synthesized signal Sx. Moreover, control part182adjusts the output amplitude levels of DAC110and DAC120such that the level in the spectrum of synthesized signals Sxanalyzed by measuring part181is the same for two frequency components (4 GHz, 6 GHz) separated by 1 GHz (frequency of synthesized signal Sx) from 5 GHz (sampling rate); the difference between these two levels becomes less than predetermined value TH2or becomes the minimum; or the sum of these two levels becomes less than predetermined value TH3or becomes the minimum. Refer toFIG. 4.FIG. 4is the spectrum of synthesized signal Sxin the case where the amplitude levels are mismatched between DAC110and DAC120when 1 GHz has been output as synthesized signal Sx. It is clear fromFIG. 4that 4 GHz and 6 GHz are unnecessary components. By means of this step, the levels of these two components are adjusted so that they are the same.

Next, in step S12, control part182adjusts the timing by which output signals Saand Sbare selected so that, in the spectrum of the synthesized signals Sxanalyzed by measuring part181, the level of the two frequency components (4 GHz, 6 GHz) separated by 1 GHz (frequency of synthesized signal Sx) from 5 GHz (sampling rate) becomes less than predetermined value TH4or becomes the minimum. In continuation with step S11, signal generator100at this time outputs sine waves of 1 GHz. Specifically, the duty ratio of clock signal C1is adjusted. Selector160must switch between output signal Saand output signal Sbat equal time intervals. For instance, when selector160is operating under ideal conditions, the duty ratio of the clock signals applied to selector160must be 50%. However, there are cases in which the duty ratio of the clock signals change by the time they reach selector160. Therefore, by means of this step, the duty ratio of clock signals C1is adjusted by device170for changing the duty ratio such that the duty ratio of clock signals becomes 50% when they reach selector160. Refer toFIG. 5.FIG. 5is the spectrum of synthesized signals Sxin the case where the switching interval between the output signals of DAC110and the output signals of DAC120was not uniform when 1 GHz was output as synthesized signal Sx. It is clear fromFIG. 5that 4 GHz and 6 GHz are unnecessary components. By means of this step, the level of these frequency components is less than predetermined value TH4.

Next, window adjustment is performed in step S13. Window means the time when input signals are selected by selector160. By means of this step, the operation of the DAC selected by selector160is adjusted such that the selected DAC outputs a level as close as possible to a setting level that is the analog output level indicated by the digital input data, within a predetermined window. When adjusting DAC110, control part182adjusts the timing by which the output signals of DAC110are renewed such that the level of 2.5 GHz becomes the maximum in the spectrum of synthesized signals Sxanalyzed by measuring part181, with rectangular waves of 2.5 GHz having been output from DAC110and direct current having been output from DAC120. Phase converter130adjusts the timing by adjusting the phase of the clock signals C11that are given to DAC110.

The adjustment of DAC110will be described again while referring toFIG. 6.FIG. 6is a drawing showing signals Sathat are output from DAC110and input to selector160, synthesized signals Sxthat are output from selector160, and the time when selector160selects output signals Sa. Signal Sboutput from DAC120and input to selector160at this time is direct current having a mean level of the amplitude range of signal Sa. Signal Sbcan be another level, as long as it is a direct current. Digital data are input to DAC110such that rectangular waves of 2.5 GHz are output. However, there are cases in which the signals that are actually output from DAC110are not perfectly rectangular waves because of performance limitations with DAC110. As previously described, when the timing by which the output signals of DAC110are renewed is adjusted such that the level of 2.5 GHz becomes the maximum in the spectrum of synthesized signals Sx, the portion as close as possible to the maximum level of output signal Sais manifested within window Wa1, and the portion as close as possible to the minimum level of output signal Sais manifested within window Wa2, as shown inFIG. 6.

The adjustment of DAC120is the same as the adjustment of DAC110. That is, control part182adjusts the timing by which the output signals of DAC120are renewed such that the level of 2.5 GHz is the maximum in the spectrum of synthesized signals Sxanalyzed by measuring part181, with direct current having been output from DAC110and a rectangular wave of 2.5 GHz output from DAC120. Phase converter140adjusts the timing by adjusting the phase of clock signals C12given to DAC120.

Moreover, if the signal integrity of synthesized signals Sxanalyzed by measuring part181satisfies a predetermined condition, e.g., a predetermined value of TH5or greater, the system will return to step S11and continue processing (Step S14). The system can return to step S10rather than step S11. The result of the above-mentioned series of processing is an optimal adjustment of signal generator100such that synthesized signals Sxof a high signal integrity are obtained as shown inFIG. 7.

However, the frequency of synthesized signal Sxin step S11and the frequency of synthesized signal Sxin step12can be a frequency other than 1 GHz, and the two are not necessarily the same. Moreover, the frequency of signal Sawhen adjusting DAC110and the frequency of signal Sbwhen adjusting DAC120can be frequencies other than 2.5 GHz and the two are not necessarily the same. Of course, there is probably an advantage to making the frequencies the same because the time needed to set up the DAC is reduced.

A second embodiment of the present invention will now be described. This second embodiment is a signal generator200. Signal generator200is different from signal generator100in that there is a frequency divider inside a selector260. This frequency divider plays a role in adjusting the duty ratio for feeding clock signals to the DAC. Refer toFIG. 8.FIG. 8is a block diagram showing the internal structure of signal generator200. The same reference numbers as inFIG. 1have been used inFIG. 8for the same structural parts as inFIG. 1and a detailed description has therefore been omitted. Signal generator200comprises a DAC110, a DAC120, a phase converter130, a phase converter140, a clock signal source250, a selector260, and a compensator280.

Clock signal source250is the device for generating clock signal C3having a frequency of 10 GHz. Clock signal C3is divided in two by a frequency divider261housed inside selector260and these frequencies are then applied to DAC110via phase converter130and DAC120via phase converter140, respectively. Frequency divider261comprises, for instance, a T flip-flop, or similar component. Selector260is a device for selecting either output signal Saor output signal Sbin accordance with the level of clock signal C4output by frequency divider261, and outputting the selected signal. By means of the present embodiment, selector260outputs output signal Sawhen the logic level of clock signal C4is L and outputs output signal Sbwhen the logic level of clock signal C4is H. As a result, synthesized signals Sxthat include output signals Saand/or Sbare generated. Compensator280is the device for monitoring output signals Sxof the selector and controlling outside devices based on the observation results. Compensator280comprises a measuring part181for analyzing the spectrum of output signals Sxof the selector and a control part282for controlling outside devices based on the analysis results of measuring part181. Control part282controls DAC110, DAC120, phase converter130, and phase converter140.

Next, the procedure for adjusting signal generator200and increasing the signal integrity of synthesized signals Sxwill be described. Degradation of the signal integrity of synthesized signals Sxoccurs as a result of mismatching of the amplitude level between DACs, mismatching of the offset level between the DACs, or mistiming of selection of the output signals of a DAC by selector160. Consequently, the present invention adjusts each structural unit and each signal inside signal generator200while monitoring the spectrum of synthesized signals Sx. Refer toFIG. 9in conjunction withFIG. 8.FIG. 9is a flow chart showing the procedure by which the signal integrity of synthesized signals Sxis improved.

First, in step S20the offset level is adjusted as in step S10. The description of the processing in step S20is the same as the description of the processing in step S10with control part182rewritten as control part282.

Next, the amplitude level is adjusted in step S21as in step S11. The description of the processing in step S21is the same as the description of the processing in step S11with control part182rewritten as control part282. By means of the second embodiment, the clock signal C3is divided in two by frequency divider261and the processing corresponding to step S12is therefore unnecessary.

Next, window adjustment is performed in step S23as in step S13. The description of the processing in step S23is the same as the description of the processing in step S13with control part182rewritten as control part282.

Moreover, if the signal integrity value of synthesized signals Sxanalyzed by measuring part181is predetermined value TH5or greater, they system will return to step S21and continue processing (Step S24). The system can return to step S20rather than step S21. The result of the above-mentioned series of processing is an optimal adjustment of signal generator200such that synthesized signals Sxof a high signal integrity are obtained as shown inFIG. 7.

By means of the second embodiment, frequency divider261can also be positioned outside of selector260as long as it is at a distance such that the duty ratio of clock signals C4that are output does not become irregular. It should be noted that it is necessary to feed clock signals from frequency divider261to selector260, DAC110, and DAC120because the initial phase of clock signal C4is not confirmed.

A third embodiment of the present invention will now be described. The third embodiment is a signal generator300. Signal generator300differs from signal generator200in that selector160comprises a through-output. Refer toFIG. 10.FIG. 10is a block diagram showing the internal structure of signal generator300. The same reference numbers as inFIG. 8have been used inFIG. 10for the same structural parts as inFIG. 8and a detailed description has therefore been omitted. Signal generator300comprises a DAC110, a DAC120, a phase converter130, a phase converter140, a clock signal source350, a selector160, and a compensator380.

Clock signal source350is the device for generating a clock signal C5having a frequency of 10 GHz and clock signal C6having a frequency of 5 GHz. When switch SW1selects the x side and switch SW2is turned ON, clock signal C5is divided in two by a frequency divider361housed inside selector360and these frequencies are then applied to DAC110via phase converter130and DAC120via phase converter140, respectively. On the other hand, when switch SW1selects the y side and switch SW2is turned OFF, clock signals C6is directly applied to DAC110via phase converter130and DAC120via phase converter140, respectively. Frequency divider261comprises, for instance, a T flip-flop, or a similar component. Selector360is a device for selecting either output signal Saor output signal Sbin accordance with the level of clock signal C4output by frequency divider361and outputting the selected signal. By means of the present embodiment, selector360outputs output signal Sawhen the logic level of clock signal C4is L and outputs output signal Sbwhen the logic level of clock signal C2is H. As a result, synthesized signals Sxthat include output signal Saand/or Sbare generated. Moreover, selector360outputs through-output, that is, outputs signals Saand Sbthat are to be input without further processing when SW2is turned OFF and clock signal C5is not introduced. Compensator380is the device for monitoring output signals Sxof the selector and controlling outside devices based on the observation results. Compensator380comprises a measuring part181for analyzing the spectrum of output signals Sxof the selector and control part382for controlling outside devices based on the analysis results of measuring part181. Control part382controls DAC110, DAC120, switch SW1, and switch SW2.

Next, the procedure for adjusting signal generator300and increasing the signal integrity of synthesized signals Sxwill be described. Degradation of signal integrity of synthesized signals Sxoccurs as a result of mismatching of the amplitude level between DACs, mismatching of the offset level between the DACs, or mistiming of switching between the output signals of the DACs. Consequently, the present invention adjusts each structural unit and each signal inside signal generator300while monitoring the spectrum of synthesized signals Sx. Refer toFIG. 11as well asFIG. 10.FIG. 11is a flow chart showing the procedure by which the signal integrity of synthesized signals Sxis improved. Switch SW1selects the y side and switch SW2is turned ON by the control implemented by control part382for inter-leave operation.

First, in step S30the offset level is adjusted as in step S20. The description of the processing in step S30is the same as the description of the processing in step S20with control part182rewritten as control part382.

Next, the amplitude level is adjusted in step S31as in step S21. The description of the processing in step S31is the same as the description of the processing in step S21with control part182rewritten as control part382. By means of the third embodiment, the clock signal C5is divided in two by frequency divider361and the processing corresponding to step S22is therefore unnecessary.

Next, window adjustment is performed in step S33as in step S23. The description of the processing in step S33is the same as the description of the processing in step S23with control part182rewritten as control part382.

Moreover, if the signal integrity value of synthesized signals Sxanalyzed by measuring part181is the predetermined value TH5or greater, the system will return to step S31and continue processing (Step S34). The system can return to step S30rather than step S31. The result of the above-mentioned series of processing is an optimal adjustment of signal generator300such that synthesized signals Sxof a high signal integrity are obtained as shown inFIG. 7.

When synthesized signals Sxare such low-frequency signals that inter-leaving of DAC110and DAC120is not necessary (when signals of 2.5 GHz or lower are output), control part382moves switch SW1to the y side and turns switch SW2OFF. In this case, selector360outputs signals Saand Sbto be input without further processing. As a result, it is possible to control the generation of unnecessary frequency components that are produced by an inter-leaving operation. Moreover, signals of different types can be output from DAC110and DAC120. Furthermore, when switch SW2is OFF, one of signals Saand Sbcan be fixed such that the other can be output to the output terminal of synthesized signals Sx.

By means of the third embodiment, frequency divider361can also be positioned outside of selector360as long as it is at a distance such that the duty ratio of clock signals C7that are output does not become irregular. It should be noted that it is necessary to feed clock signals from frequency divider361to selector360, DAC110, and DAC120because the initial phase of clock signal C4is not confirmed.

However, the first, second and third embodiments can be modified as follows. By means of the first, second, and third embodiments, control part182, control part282and control part382can be individually housed in devices that are to be controlled. For instance, by means of the first embodiment, control part182can be housed decentralized between DAC110, DAC120, and device170for changing the duty ratio. Of course, a partial housing of the control part is also possible, whereby, for instance, the control mechanism relating to device170for changing the duty ratio is separated from control part182and housed inside device170for changing the duty ratio. In such a case, it is necessary for each device that is to be controlled to individually receive the results of spectrum analysis and the measurement results are naturally output from measuring part181to device170for changing the duty ratio.

The first, second, and third embodiments have described a structure wherein two DACs are inter-leaved. However, the present invention is a signal generator having 2nDACs and can be easily applied to a signal generator wherein the signal path from the output of each DAC to the output of the signal generator has a two-branch structure and there is a selector at the part that corresponds to the joint between two branches. In such a case, the signal generating circuit that inter-leaves two DACs is regarded as one DAC and the procedure described for the first, second, and third embodiments is applied. That is, a signal generating circuit obtained by inter-leaving two signal generating circuits having two DACs is adjusted. Then, the signal generating circuit comprising four DACs is regarded as one DAC and similarly adjusted. By adjusting the circuits in steps in this way, the adjustment of the present invention can be accomplished, even with a structure wherein 2nDACs have been inter-leaved.