Digital-to-analog conversion with combined pulse modulators

A digital-to-analog converter includes first and second pulse modulators to generate first and second pulse modulated signals in response to first and second digital values, a third pulse modulator to generate a third pulse modulated signal in response to a third digital value, and a switch/filter circuit to generate an analog signal by combining the first and second pulse modulated signals in response to the third pulse modulated signal. The first and second pulse modulated signals may be low-pass filtered before being combined. In some embodiments, the third digital value may be incremented in a single direction between transitions of the first and second digital values. In some other embodiments, the third digital value may be incremented in opposite directions between alternating transitions of the first and second digital values.

BACKGROUND

A pulse width modulation (PWM) circuit can be used to perform as a digital-to-analog converter (DAC) by applying the PWM output signal to a low-pass filter having a corner frequency that is low enough to eliminate the high-frequency components of the PWM signal. PWM DAC circuits are especially useful for generating voltage references with microcontrollers because they can fairly easily generate linear analog outputs by applying appropriate low-pass filters to the PWM outputs that are available on many microcontrollers. These simplistic PWM DAC circuits, however, tend to be inaccurate and require difficult trade offs between resolution and response time. Obtaining higher resolution requires a longer PWM count chain which produces a lower fundamental frequency.

FIG. 1illustrates a prior art PWM DAC circuit in which the outputs from two separate 8-bit PWMs10and12are combined through an analog summing/filter circuit14to provide a higher resolution DAC. Although this type of circuit may provide higher resolution, it may require highly accurate divider resistors and complex active circuitry to provide an accurate output. Additional problems may include the need to provide heavy filtering to extract the DC component from the PWM ripple which reduces the operating speed, and the need to compensate for internal component resistances in the active analog circuitry.

FIG. 2illustrates another prior art PWM DAC circuit in which a PWM clock signal is used to dither between two adjacent output values of an 8-bit DAC. The DAC 16 outputs a value of N when the clock input is low and a value of N+1 when the clock input is high. Thus, by using a PWM signal as the clock input and filtering the DAC output with a low-pass filter18, the circuit provides additional discrete analog output levels between the DAC output levels.

The technique illustrated inFIG. 2, however, reduces the operating speed substantially because the DAC output must be allowed to settle repeatedly at the different values of N and N+1 as the clock input transitions in response to the PWM input. Moreover, the circuit ofFIG. 2requires complex, dedicated and custom digital circuitry in the DAC to implement.

DETAILED DESCRIPTION

FIG. 3illustrates an embodiment of a digital-to-analog converter according to some inventive principles of this patent disclosure. The embodiment ofFIG. 3includes a first pulse modulator20to generate a first pulse modulated signal P1in response to a first digital value D1, a second pulse modulator22to generate a second pulse modulated signal P2in response to a second digital value D2, and a third pulse modulator24to generate a third pulse modulated signal P3in response to a third digital value D3. A switch/filter circuit26generates an analog output signal A1by combining the first and second pulse modulated signals P1and P2in response to the third pulse modulated signal P3as described in more detail below.

The pulse modulators20,22and24may implement any suitable modulation technique such as pulse width modulation (PWM), pulse frequency modulation (PFM), etc., or any combination of techniques, at any desired resolution, i.e., 8-bit, 10-bit, etc. The switch/filter circuit26may include any suitable combination of analog and/or digital switches, multiplexers, active and/or passive filters, etc.

FIG. 4is a block diagram of a first exemplary embodiment of a digital-to-analog converter illustrating some possible implementation details according to some inventive principles of this patent disclosure. In the embodiment ofFIG. 4, the pulse modulators are realized as pulse width modulators (PWMs)28,30and32(PWM1, PWM2, PWM3) which generate pulse width modulated signals PW1, PW2and PW3in response to digital values D1, D2and D3, respectively. The switch/filter circuit is implemented with an analog or digital switch34which selectively couples the first and second pulse modulated signals PW1and PW2in a time-multiplexed manner to a low pass filter36in response to the third pulse width modulated signal PW3.

Sequencing logic38controls the overall operation of the converter by generating the digital values D1, D2and D3in an appropriate sequence to generate the desired analog output waveform. For example, the values of D1and D2may be selected as N and N+1, respectively, which bracket a desired output between N and N+1. The value of D3may then be set to provide a duty factor DF between zero and one such that the value of the filtered analog output is N+DF.

Thus, the embodiment ofFIG. 4may generate a range of values between N and N+1, thereby providing greater resolution than would be available from either of the individual PWMs28and30. The number of discrete steps between N and N+1 is determined by the resolution of PWM3. For example, if PWM3is implemented with 8-bit resolution, there may be 256 steps between N and N+1. Thus, if all three PWMs are implemented with 8-bit resolution, the equivalent resolution of the resulting system may be as high as 16-bits depending on the implementation details such as the offset voltages of the low pass filter36, analog switch34, etc.

Moreover, the embodiment ofFIG. 4may provide faster operation than a single PWM DAC having the equivalent resolution because the sum of the settling time of PWM1and PWM2, combined with the delay through the analog switch34and low pass filter36may be substantially less than the delay time of the count chain in the single PWM DAC.

The inventive principles are not limited to the details illustrated with respect toFIG. 4. For example, the resolutions of each of PWM1, PWM2and PWM3may be set to different values depending on the desired overall resolution, and the number of counts between PWM1and PWM2may be some number other than zero. The low pass filter may be implemented with active and/or passive circuitry, with any suitable number of poles, etc. Likewise, the sequencing logic be implemented with analog and/or digital hardware, software, firmware, etc., or any suitable combination thereof.

With the embodiment ofFIG. 4, it may be beneficial to implement some or all of the PWMs with clock sources that are unsynchronized to prevent correlation between the PWMs from cancelling the respective contributions of the PWMs which may occur if the PWM signals are synchronous and have the same count length. This may prevent, for example, a situation in which PWM3is not capable of passing pulses from PWM1and PWM2under circumstances in which the PWM modulus is identical for all three.

FIG. 5is a block diagram of a second exemplary embodiment of a digital-to-analog converter illustrating some possible implementation details according to some inventive principles of this patent disclosure. In the embodiment ofFIG. 5, the pulse modulators are again realized as pulse width modulators (PWMs)28,30and32(PWM1, PWM2, PWM3) which generate pulse width modulated signals PW1, PW2and PW3in response to digital values D1, D2and D3, respectively. However, the outputs of PWM1and PWM2are filtered before switching. A first low-pass filter42provides a first filtered signal F1in response to the first pulse width modulated signal PW1, while a second low-pass filter44provides a second filtered signal F2in response to the second pulse modulated signal PW2. An analog switch46is arranged to provide a multiplexed analog signal A2by selecting the first and second filtered signals in response to the third pulse width modulated signal PW3. A third low-pass filter48removes the modulation ripple to provide the final analog output signal A3. Sequencing logic40controls the overall operation of the converter by generating the digital values D1, D2and D3in an appropriate sequence to generate the desired analog output waveform.

Some additional implementation details will be described in the context of the embodiment ofFIG. 5, but the inventive principles are not limited to these details. Moreover, the embodiment ofFIG. 5may be operated in different modes by implementing different algorithms with the sequencing logic40.

For purposes of illustration, and in a first mode of operation, PW1, PW2and PW3are each assumed to have 8-bit resolution. Sequencing logic40sets the digital values of D1and D2to generate the two filtered analog signals F1and F2with values of N and N+1, respectively, using PWM1and PWM2independently. The filters42and44may be implemented, for example, with two-pole active filters to remove virtually all of the induced ripple. The two filtered analog signals F1and F2are then modulated by analog switch46and filtered to produce the final analog output having a value N+DF where DF is the duty factor of the third pulse width modulated signal PW3. The third filter48may have a more gradual roll-off because the values of N and N+1 are relatively close.

To obtain an arbitrary 16-bit output voltage V, sequencing logic40may load PWM1with a value D1that provides a filtered analog signal F1=V/256, and load PWM2with a value D2that provides a filtered analog signal F2=1+V/256. PWM3is then loaded with a value D3that corresponds to V modulo256.

FIG. 6illustrates the operation of the embodiment ofFIG. 5in the first mode of operation. Increasing values of the analog output voltage V are shown progressing from left to right. One portion of the full-scale range begins at the left side ofFIG. 6where PWM1=N, PWM2=N+1 and PWM3=0. Moving to the right, the filtered value of the final analog output signal increases as the value of PWM3(shown in hexadecimal values) increases towards the maximum value FFh. For simplicity, only a few intermediate values of 40h, 80h, C0h and E0h are shown.

The system then enters a second portion of the full scale range as PWM3is reset by transitioning from FFh back to 00h, PWM1is incremented to N+1, and PWM2is incremented to N+2. The value of PWM3then increases again towards the maximum value FFh as the analog output voltage V continues to increase.

FIG. 7illustrates the operation of the embodiment ofFIG. 5in a second mode of operation. Here, the first portion of the full-scale range again begins at the left side ofFIG. 7where PWM1=N, PWM2=N+1 and PWM3=0. Moving to the right, the filtered value of the final analog output signal increases as the value of PWM3(shown in hexadecimal values) increases towards the maximum value FFh.

In the second mode, however, the value of PWM3is not reset after reaching the maximum value FFh. Instead, in the second portion of the full-scale range, PWM3is decremented (incremented in the opposite direction) back towards the minimum value of 00h. Also, rather than incrementing both of PWM1and PWM2as in the first mode, PWM2remains at N+1 and PWM1is double incremented to N+2. The analog output voltage V continues to increase as the value of PWM3decreases.

The system reaches a third portion of the full-scale range (not shown) when PWM3reaches 00h. At this transition, PWM1remains at N+2, and PWM2is double incremented to N+3. The filtered value of the final analog output signal then continues to increase as the value of PWM3once again increases towards the maximum value FFh.

Thus, in the second mode of operation, the values of PWM1and PWM2are incremented in an alternating manner while the value of PWM3is incremented in opposite directions between alternating transitions of PWM1and PWM2.

A potential advantage of the second mode of operation is that it may provide monotonic operation even when the offsets of the first and second filters are controlled to a tolerance as loose as one 8-bit LSB. This is in contrast to the first mode of operation where the offsets may need to be as tight as one 16-bit LSB to provide monotonic operation. With the second mode, even a worst case in which the offset is only kept within 1/256 of full-scale amplitude, a sequence of 256 steps through one portion of the range would simply show no change in amplitude, but never reverse and become non-monotonic.

FIGS. 8 and 9show another way to illustrate the operation of the embodiment ofFIG. 5in the first and second modes of operation, respectively.

Referring toFIG. 8, at V=0 in the first mode of operation, PWM1is set to 0 and PWM2is set to 1. PWM3begins at zero, then increments to FFh as the analog output voltage V continues to increase towards the right. After reaching FFh, PWM3is then reset to 00h, and PWM1and PWM2are incremented to 1 and 2, respectively at the transition. PWM3is again incremented towards FFh until the next transition where PWM1and PWM2are incremented again and PWM3is reset. Thus, PWM3may be described as having a single slope direction (or polarity) with respect to the digital value D3that drives it.

Referring toFIG. 9, the operation in the second mode is the same as for the first mode during the first portion of the full scale range. However, at the first transition where PWM3reaches FFh, PWM1is double incremented, PWM2is left unchanged, and PWM3is not reset, but rather begins to decrement towards 00h. Thus, fromFIG. 9PWM3may be described as having two slope directions (or polarities) with respect to the digital value D3that drives it, and each of PWM1and PWM2are alternately held constant or double incremented when the slope of PWM3changes direction.

FIGS. 10 and 11show yet another way to illustrate the operation of the embodiment ofFIG. 5in the first and second modes of operation, respectively. In the embodiments ofFIGS. 10 and 11, the third PWM is implemented as a 2-bit PWM to simplify the illustrations. The values of PWM1, PWM2and PWM3are shown for increasing values of the analog output voltage V moving toward the bottom of the tables.

Referring to the table ofFIG. 10, which illustrates the first mode, V begins at zero at the top of the table where PWM1=1, PWM2=1 and PWM3=0. PWM3is then incremented to 1, 2 and 3 as PWM1and PWM2remain constant. As PWM3is reset to 0, PWM1and PWM2are incremented to 1 and 2, respectively. PWM3is then incremented to 1, 2 and 3 again as PWM1and PWM2remain constant. This pattern continues through the rest of the full scale range with PWM1and PWM2being incremented simultaneously each time PWM3is reset to 0 in the first mode of operation.

Referring to the table ofFIG. 11, which illustrates the second mode, V begins at zero at the top of the table where PWM1=1, PWM2=1 and PWM3=0. PWM3is then incremented to 1, 2 and 3 as PWM1and PWM2remain constant. At the next step, PWM1is double incremented to 2, PWM2remains constant at 1, and PWM3remains at 3. PWM3is then decremented in a downward slope to 2, 1 and 0 as PWM1and PWM2remain constant. This pattern continues through the rest of the full scale range with PWM1and PWM2being alternately double incremented each time PWM3transitions from a positive to a negative slope.

FIG. 12illustrates an alternative embodiment of the second mode, again with PWM3implemented as a 2-bit PWM, in which one of the steps in each downward sloping portion is eliminated to prevent a situation in which there may be no change in the analog output voltage if PWM3remains at 3 for two steps.

FIG. 13illustrates another alternative embodiment of the second mode, again with PWM3implemented as a 2-bit PWM, in which one of the steps in each downward and upward sloping portion is eliminated to prevent a situation in which there may be no change in the analog output voltage if PWM3remains at 0 or 3 for two steps.

The various embodiments ofFIGS. 10,11,12and13may be useful, for example, to accommodate PWMs in which one or both of the minimum or maximum values of PWM3provide either a constant output or a narrow spike that is one clock cycle long.

A potential advantage of the embodiment ofFIG. 5, regardless of the mode of operation, is that it may not be affected by synchronization of the clocks for the various PWMs.

Any of the logic described above may be implemented as analog and/or digital hardware, software, firmware, etc., or any suitable combination thereof.

In any of the embodiments described above, the sequencing logic may be implemented with program code running on a processing core in a microcontroller on which PWM1, PWM2and PWM3reside. This may be particularly beneficial with currently available microcontrollers which may have six channels of 8-bit PWM outputs, and thus may provide two complete channels of 16-bit PWM DACs.

Some potential benefits of the inventive principles described herein include the ability to implement higher resolution DACs utilizing existing, low-cost, debugged circuitry commonly available in microcontrollers, while placing lower demands on the analog circuitry.

As used herein, the term increment may refer to incrementing a value in either the positive direction or the negative direction (decrementing).

The inventive principles of this patent disclosure have been described above with reference to some specific example embodiments, but these embodiments can be modified in arrangement and detail without departing from the inventive concepts. For example, the embodiment ofFIG. 3may be modified to include additional PWMs that the switch/filter circuit may switch between. Such changes and modifications are considered to fall within the scope of the claims following the Appendices.