FPGA integrated circuit having embedded sram memory blocks with registered address and data input sections

A field-programmable gate array device (FPGA) having plural rows and columns of logic function units (VGB's) further includes a plurality of embedded memory blocks, where each memory block is embedded in a corresponding row of logic function units. Each embedded memory block has a registered address port for capturing received address signals in response to further-received, address-validating clock signals. Interconnect resources are provided for conveying the address-validating clock signals to address-changing circuitry so that a next address can be generated safely in conjunction with the capturing by the registered address port of a previous address signal.

CROSS REFERENCE TO RELATED APPLICATIONS

The following copending U.S. patent applications are owned by the owner of the present application, and their disclosures are incorporated herein by reference:(A) Ser. No. 08/948,306 filed Oct. 9, 1997 by Om P. Agrawal et al. and originally entitled, “VARIABLE GRAIN ARCHITECTURE FOR FPGA INTEGRATED CIRCUITS”;(B) (A) Ser. No. 08/996,049 filed Dec. 22, 1997 by Om P. Agrawal et al and originally entitled, DUAL PORT SRAM MEMORY FOR RUN-TIME USE IN FPGA INTEGRATED CIRCUITS;(C) Ser. No. 08/996,361 filed Dec. 22, 1997, by Om Agrawal et al. and originally entitled, “SYMMETRICAL, EXTENDED AND FAST DIRECT CONNECTIONS BETWEEN VARIABLE GRAIN BLOCKS IN FPGA INTEGRATED CIRCUITS”;(D) Ser. No. 08/995,615 filed Dec. 22, 1997, by Om Agrawal et al. and originally entitled, “A PROGRAMMABLE INPUT/OUTPUT BLOCK (IOB) IN FPGA INTEGRATED CIRCUITS”;(E) Ser. No. 08/995,614 filed Dec. 22, 1997, by Om Agrawal et al. and originally entitled, “INPUT/OUTPUT BLOCK (IOB) CONNECTIONS TO MAXL LINES, NOR LINES AND DENDRITES IN FPGA INTEGRATED CIRCUITS”;(F) Ser. No. 08/995,612 filed Dec. 22, 1997, by Om Agrawal et al. and originally entitled, “FLEXIBLE DIRECT CONNECTIONS BETWEEN INPUT/OUTPUT BLOCKs (IOBS) AND VARIABLE GRAIN BLOCKs (VGBS) IN FPGA INTEGRATED CIRCUITS”;(G) Ser. No. 08/997,221 filed Dec. 22, 1997, by Om Agrawal et al. and originally entitled, “PROGRAMMABLE CONTROL MULTIPLEXING FOR INPUT/OUTPUT BLOCKs (IOBs) IN FPGA INTEGRATED CIRCUITS”;(H) Ser. No. 09/191,444 filed Nov. 12, 1998 by inventors Bai Nguyen et al and originally entitled, MULTI-PORT SRAM CELL ARRAY HAVING ISOLATION BUFFER IN EACH SRAM CELL FOR PROTECTING SRAM CELL FROM READ NOISE;(I) Ser. No. 09/235,536 filed concurrently herewith by inventors Bai Nguyen et al and entitled, MULTI-PORT SRAM CELL ARRAY HAVING PLURAL WRITE PATHS INCLUDING FOR WRITING THROUGH ADDRESSABLE PORT AND THROUGH SERIAL BOUNDARY SCAN; and(J) Ser. No. 09/008,762 filed Jan. 19, 1998 by inventors Om Agrawal et al and entitled, SYNTHESIS-FRIENDLY FPGA ARCHITECTURE WITH VARIABLE LENGTH AND VARIABLE TIMING INTERCONNECT.

CROSS REFERENCE TO RELATED PATENTS

BACKGROUND

1. Field of the Invention

The invention is generally directed to integrated circuits, more specifically to on-chip memory provided for run-time use with on-chip logic circuits. The invention is yet more specifically directed to on-chip memory provided for run-time use within Programmable Logic Devices (PLD's), and even more specifically to a subclass of PLD's known as Field Programmable Gate Arrays (FPGA's).

2. Description of Related Art

Field-Programmable Logic Devices (FPLD's) have continuously evolved to better serve the unique needs of different end-users. From the time of introduction of simple PLD's such as the Advanced Micro Devices 22V10™ Programmable Array Logic device (PAL), the art has branched out in several different directions.

One evolutionary branch of FPLD's has grown along a paradigm known as Complex PLD's or CPLD's. This paradigm is characterized by devices such as the Advanced Micro Devices MACH™ family. Examples of CPLD circuitry are seen in U.S. Pat. Nos. 5,015,884 (issued May 14, 1991 to Om P. Agrawal et al.) and 5,151,623 (issued Sep. 29, 1992 to Om P. Agrawal et al.).

Another evolutionary chain in the art of field programmable logic has branched out along a paradigm known as Field Programmable Gate Arrays or FPGA's. Examples of such devices include the XC2000™ and XC3000™ families of FPGA devices introduced by Xilinx, Inc. of San Jose, Calif. The architectures of these devices are exemplified in U.S. Pat. Nos. 4,642,487; 4,706,216; 4,713,557; and 4,758,985; each of which is originally assigned to Xilinx, Inc.

An FPGA device can be characterized as an integrated circuit that has four major features as follows.(1) A user-accessible, configuration-defining memory means, such as SRAM, EPROM, EEPROM, anti-fused, fused, or other, is provided in the FPGA device so as to be at least once-programmable by device users for defining user-provided configuration instructions. Static Random Access Memory or SRAM is of course, a form of reprogrammable memory that can be differently programmed many times. Electrically Erasable and reprogrammable ROM or EEPROM is an example of nonvolatile reprogrammable memory. The configuration-defining memory of an FPGA device can be formed of mixture of different kinds of memory elements if desired (e.g., SRAM and EEPROM).(2) Input/Output Blocks (IOB's) are provided for interconnecting other internal circuit components of the FPGA device with external circuitry. The IOB's may have fixed configurations or they may be configurable in accordance with user-provided configuration instructions stored in the configuration-defining memory means.(3) Configurable Logic Blocks (CLB's) are provided for carrying out user-programmed logic functions as defined by user-provided configuration instructions stored in the configuration-defining memory means. Typically, each of the many CLB's of an FPGA has at least one lookup table (LUT) that is user-configurable to define any desired truth table, —to the extent allowed by the address space of the LUT. Each CLB may have other resources such as LUT input signal pre-processing resources and LUT output signal post-processing resources. Although the term ‘CLB’ was adopted by early pioneers of FPGA technology, it is not uncommon to see other names being given to the repeated portion of the FPGA that carries out user-programmed logic functions. The term, ‘LAB’ is used for example in U.S. Pat. No. 5,260,611 to refer to a repeated unit having a 4-input LUT.(4) An interconnect network is provided for carrying signal traffic within the FPGA device between various CLB's and/or between various IOB's and/or between various IOB's and CLB's. At least part of the interconnect network is typically configurable so as to allow for programmably-defined routing of signals between various CLB's and/or IOB's in accordance with user-defined routing instructions stored in the configuration-defining memory means. Another part of the interconnect network may be hard wired or nonconfigurable such that it does not allow for programmed definition of the path to be taken by respective signals traveling along such hard wired interconnect. A version of hard wired interconnect wherein a given conductor is dedicatedly connected to be always driven by a particular output driver, is sometimes referred to as ‘direct connect’.

In addition to the above-mentioned basic components, it is sometimes desirable to include on-chip reprogrammable memory that is embedded between CLB's and available for run-time use by the CLB's and/or resources of the FPGA for temporarily holding storage data. This embedded run-time memory is to be distinguished from the configuration memory because the latter configuration memory is generally not reprogrammed while the FPGA device is operating in a run-time mode. The embedded run-time memory may be used in speed-critical paths of the implemented design to implement, for example, FIFO or LIFO elements that buffer data words on a first-in/first-out or last-in/first-out basis. Read/write speed, data validating speed, and appropriate interconnecting of such on-chip embedded memory to other resources of the FPGA can limit the ability of a given FPGA architecture to implement certain speed-critical designs.

Modern FPGA's tend to be fairly complex. They typically offer a large spectrum of user-configurable options with respect to how each of many CLB's should be configured, how each of many interconnect resources should be configured, and how each of many IOB's should be configured. Rather than determining with pencil and paper how each of the configurable resources of an FPGA device should be programmed, it is common practice to employ a computer and appropriate FPGA-configuring software to automatically generate the configuration instruction signals that will be supplied to, and that will cause an unprogrammed FPGA to implement a specific design.

FPGA-configuring software typically cycles through a series of phases, referred to commonly as ‘partitioning’, ‘placement’, and ‘routing’. This software is sometimes referred to as a ‘place and route’ program. Alternate names may include, ‘synthesis, mapping and optimization tools’.

In the partitioning phase, an original circuit design (which is usually relatively large and complex) is divided into smaller chunks, where each chunk is made sufficiently small to be implemented by a single CLB, the single CLB being a yet-unspecified one of the many CLB's that are available in the yet-unprogrammed FPGA device. Differently designed FPGA's can have differently designed CLB's with respective logic-implementing resources. As such, the maximum size of a partitioned chunk can vary in accordance with the specific FPGA device that is designated to implement the original circuit design. The original circuit design can be specified in terms of a gate level description, or in Hardware Descriptor Language (HDL) form or in other suitable form.

After the partitioning phase is carried out, each resulting chunk is virtually positioned into a specific, chunk-implementing CLB of the designated FPGA during a subsequent placement phase.

In the ensuing routing phase, an attempt is made to algorithmically establish connections between the various chunk-implementing CLB's of the FPGA device, using the interconnect resources of the designated FPGA device. The goal is to reconstruct the original circuit design by reconnecting all the partitioned and placed chunks.

If all goes well in the partitioning, placement, and routing phases, the FPGA configuring software will find a workable ‘solution’ comprised of a specific partitioning of the original circuit, a specific set of CLB placements and a specific set of interconnect usage decisions (routings). It can then deem its mission to be complete and it can use the placement and routing results to generate the configuring code that will be used to correspondingly configure the designated FPGA.

In various instances, however, the FPGA configuring software may find that it cannot complete its mission successfully on a first try. It may find, for example that the initially-chosen placement strategy prevents the routing phase from completing successfully. This might occur because signal routing resources have been exhausted in one or more congested parts of the designated FPGA device. Some necessary interconnections may have not been completed through those congested parts. Alternatively, all necessary interconnections may have been completed, but the FPGA configuring software may find that simulation-predicted performance of the resulting circuit (the so-configured FPGA) is below an acceptable threshold. For example, signal propagation time may be too large in a speed-critical part of the FPGA-implemented circuit. More specifically, certain synchronization signals may need to propagate from one section of the FPGA to another according to a particular sequence and architectural constraints of the FPGA device may impede this from happening in an efficient manner in so far as resource utilization is concerned.

Given this, if the initial partitioning, placement and routing phases do not provide an acceptable solution, the FPGA configuring software will try to modify its initial place and route choices so as to remedy the problem. Typically, the software will make iterative modifications to its initial choices until at least a functional place-and-route strategy is found (one where all necessary connections are completed), and more preferably until a place-and-route strategy is found that brings performance of the FPGA-implemented circuit to a near-optimum point. The latter step is at times referred to as ‘optimization’. Modifications attempted by the software may include re-partitionings of the original circuit design as well as repeated iterations of the place and route phases.

There are usually a very large number of possible choices in each of the partitioning, placement, and routing phases. FPGA configuring programs typically try to explore a multitude of promising avenues within a finite amount of time to see what effects each partitioning, placement, and routing move may have on the ultimate outcome. This in a way is analogous to how chess-playing machines explore ramifications of each move to each chess piece on the end-game. Even when relatively powerful, high-speed computers are used, it may take the FPGA configuring software a significant amount of time to find a workable solution. Turn around time can take more than 8 hours.

In some instances, even after having spent a large amount of time trying to find a solution for a given FPGA-implementation problem, the FPGA configuring software may fail to come up with a workable solution and the time spent becomes lost turn-around time. It may be that, because of packing inefficiencies, the user has chosen too small an FPGA device for implementing too large of an original circuit.

Another possibility is that the internal architecture of the designated FPGA device does not mesh well with the organization and/or timing requirements of the original circuit design.

Organizations of original circuit designs can include portions that may be described as ‘random logic’ (because they have no generally repeating pattern). The organizations can additionally or alternatively include portions that may be described as ‘bus oriented’ (because they carry out nibble-wide, byte-wide, or word-wide, parallel operations). The organizations can yet further include portions that may be described as ‘matrix oriented’ (because they carry out matrix-like operations such as multiplying two, multidimensional vectors). These are just examples of taxonomical descriptions that may be applied to various design organizations. Another example is ‘control logic’ which is less random than fully ‘random logic’ but less regular than ‘bus oriented’ designs. There may be many more taxonomical descriptions. The point being made here is that some FPGA structures may be better suited for implementing random logic while others may be better suited for implementing bus oriented designs or other kinds of designs. In cases where embedded memory is present, the architecture of the embedded memory can play an important role in determining how well a given taxonomically-distinct design is accommodated. Compatibility between the embedded memory architecture and the architecture of intertwined CLB's and interconnect can also play an important role in determining how well a given taxonomically-distinct design is accommodated.

If after a number of tries, the FPGA configuring software fails to find a workable solution, the user may choose to try again with a differently-structured FPGA device. The user may alternatively choose to spread the problem out over a larger number of FPGA devices, or even to switch to another circuit implementing strategy such as CPLD or ASIC (where the latter is an Application Specific hardwired design of an IC). Each of these options invariably consumes extra time and can incur more costs than originally planned for.

FPGA device users usually do not want to suffer through such problems. Instead, they typically want to see a fast turnaround time of no more than, say 4 hours, between the time they complete their original circuit design and the time a first-run FPGA is available to implement and physically test that design. More preferably, they would want to see a fast turnaround time of no more than, say 30 minutes, for successful completion of the FPGA configuring software when executing on a 80486-80686 PC platform (that is, a socommercially specified, IBM compatible personal computer) and implementing a 25000 gate or less, design in a target FPGA device.

FPGA users also usually want the circuit implemented by the FPGA to provide an optimal emulation of the original design in terms of function packing density, cost, speed, power usage, and so forth irrespective of whether the original design is taxonomically describable generally as ‘random logic’, or as ‘bus oriented’, ‘memory oriented’, or as a combination of these, or otherwise.

When multiple FPGA's are required to implement a very large original design, high function packing density and efficient use of FPGA internal resources are desired so that implementation costs can be minimized in terms of both the number of FPGA's that will have to be purchased and the amount of printed circuit board space that will be consumed.

Even when only one FPGA is needed to implement a given design, a relatively high function packing density is still desirable because it usually means that performance speed is being optimized due to reduced wire length. It also usually means that a lower cost member of a family of differently sized FPGA's can be selected or that unused resources of the one FPGA can be reserved for future expansion needs.

In summary, end users want the FPGA configuring software to complete its task quickly and to provide an efficiently-packed, high-speed compilation of the functionalities provided by an original circuit design irrespective of the taxonomic organization of the original design.

In the past, it was thought that attainment of these goals was primarily the responsibility of the computer programmers who designed the FPGA configuring software. It has been shown however, that the architecture or topology of the unprogrammed FPGA can play a significant role in determining how well and how quickly the FPGA configuring software completes the partitioning, placement, and routing tasks.

As indicated above, the architectural layout, implementation, and use of on-chip embedded memory can also play a role in how well the FPGA configuring software is able to complete the partitioning, placement and routing tasks with respect to using embedded memory; and also how well the FPGA-implemented circuit performs in terms of propagating signals into, through and out of the on-chip embedded memory.

SUMMARY OF THE INVENTION

An improved FPGA device in accordance with the invention includes one or more columns of multi-ported SRAM blocks for holding run-time storage data.

In each such SRAM block, at least a first of the multiple ports is a read/write port (Port_1) which can receive first address signals and respond by directing the writing of further-received first data to an address-defined first area of the SRAM block and which can alternatively respond by directing the reading of stored data from an address-defined area of the SRAM block. A second of the multiple ports (Port_2) has at least an independent read-capability such that the second port can receive respective second address signals and can respond independently of the first port by reading stored second data from a respective address-defined area of the SRAM block.

The address signals that drive the multiple ports of each SRAM block generally come from respective signal sources that have changing output states. In accordance with the invention, one or more address-capturing registers are provided for a respective one or more of the multiple ports of each SRAM block for capturing a respective address signal for that port in response to an address-validating strobe signal. The address-validating strobe signal is routable to the respective signal source of the address signal so that the address-validating strobe signal may be used to enable a changing of the output state of the signal source once the respective address signal has been captured by the address-capturing register.

In one embodiment, an address-validating strobe signal of each SRAM block may be coupled by userconfiguration from a special SRAM control bus (SVIC) to crossing bidirectional interconnect lines (e.g., tri-stated horizontal longlines) for providing timingsynchronization to the respective signal source of the address signal so that the address-validating strobe signal may be used to enable a changing of the output state of the signal source once the respective address signal has been captured by the address-capturing register.

Further in accordance with the invention, one or more data-capturing registers are provided for a respective one or more of the multiple ports of each SRAM block for capturing a respective data signal for that port in response to a data-validating strobe signal.

When data writing is taking place, the data-validating strobe signal is routable to the respective signal source of the data signal so that the data-validating strobe signal may be used to enable a changing of the output state of the signal source once the respective data write signal has been captured by the data-capturing register.

When data reading is taking place, the data-validating strobe signal is routable to respective logic of the data signal destination so that the data-validating strobe signal may be used to indicate to that logic that a valid data output state is present for the respective to-be read data signal which has now been captured by the data-capturing register.

In one embodiment, special, vertical interconnect channels are provided adjacent to embedded SRAM columns for supplying the address-validating strobe signals and data-validating strobe signals to the SRAM blocks as well as additional control signals. The control signals (which include the address-validating and data-validating strobe signals) may be broadcast via special longlines (SMaxL lines) to all SRAM blocks of a given column or localized to groups of SRAM blocks in a given column by using shorter special vertical lines (S4xL lines).

One of the features of embodiments that include the address-capturing registers is that read operations can be performed simultaneously at the multiple ports of each SRAM block using respective, and typically different, address signals for each such port, as well as different interconnect lines for transferring the output data. The data output (data reading) bandwidth of the embedded memory can be thereby maximized, if such maximize bandwidth is desired. Logic circuits can engage in generating a next, new address signals even while the SRAM blocks are busy responding to register-captured, old address signals. Such pipelining of operations can help to increase overall system bandwidth.

Another of the features of embodiments that include the data-capturing registers is that the SRAM blocks can begin responding to new address signals even while the destination logic blocks of old data are busy responding to register-captured, old data signals. Such pipelining of operations can help to increase overall system bandwidth.

Other aspects of the invention will become apparent from the below detailed description.

DETAILED DESCRIPTION

FIG. 1shows a macroscopic view of an FPGA device100in accordance with the invention. The illustrated structure is preferably formed as a monolithic integrated circuit.

The macroscopic view ofFIG. 1is to be understood as being taken at a magnification level that is lower than later-provided, microscopic views. The more microscopic views may reveal greater levels of detail which may not be seen in more macroscopic views. And in counter to that, the more macroscopic views may reveal gross architectural features which may not be seen in more microscopic views. It is to be understood that for each more macroscopic view, there can be many alternate microscopic views and that the illustration herein of a sample microscopic view does not limit the possible embodiments of the macroscopically viewed entity. Similarly, the illustration herein of a sample macroscopic view does not limit the possible embodiments into which a microscopically viewed embodiment might be included.

FPGA device100comprises a regular matrix of super structures defined herein as super-VGB's (SVGB's). In the illustrated embodiment, a dashed box(upper left corner) circumscribes one such super-VGB structure which is referenced as101. There are four super-VGB's shown in each super row of FIG.1and also four super-VGB's shown in each super column. Each super row or column contains plural rows or columns of VGB's. One super column is identified as an example by the braces at111. Larger matrices with more super-VGB's per super column and/or super row are of course contemplated.FIG. 1is merely an example.

There is a hierarchy of user-configurable resources within each super-VGB. At a next lower level, each super-VGB is seen to contain four VGB's. In the illustrated embodiment, identifier102points to one such VGB within SVGB101.

A VGB is a Variable Grain Block that includes its own hierarchy of user configurable resources. At a next lower level, each VGB is seen to contain four Configurable Building Blocks or CBB's arranged in a L-shaped configuration. In the illustrated embodiment, identifier103points to one such CBB within VGB102.

At a next lower level, each CBB has its own hierarchy of user configurable resources. Some of these (e.g., a CSE) will be shown in later figures. A more detailed description of the hierarchal resources of the super-VGB's, VGB's, CBB's, and so forth, may be found in the above-cited Ser. No. 08/948,306filed Oct. 9, 1997 by Om P. Agrawal et al. and originally entitled, VARIABLE GRAIN ARCHITECTURE FOR FPGA INTEGRATED CIRCUITS, whose disclosure is incorporated herein by reference.

It is sufficient for the present to appreciate that each CBB includes a clocked flip flop and that each CBB is capable of producing at least one bit of result data and/or storing one bit of data in its flip flop and/or of outputting the stored and/or result data to adjacent interconnect lines. Each VGB (102) is in turn, therefore capable of producing and outputting at least 4 such result bits at a time to adjacent interconnect lines. This is referred to as nibble-wide processing. Nibble-wide processing may also be carried out by the four CBB's that line the side of each SVGB (e.g.,101).

With respect to the adjacent interconnect lines (AIL's), each SVGB is bounded by two horizontal and two vertical interconnect channels (HIC's and VIC's). An example of a HIC is shown at150. A sample VIC is shown at160. Each such interconnect channel contains a diverse set of interconnect lines as will be seen later.

The combination of each SVGB (e.g.,101) and its surrounding interconnect resources (of which resources, not all are shown inFIG. 1) is referred to as a matrix tile. Matrix tiles are tiled one to the next as seen, with an exception occurring about the vertical sides of the two central, super columns,115. Columns114(LMC) and116(RMC) of embedded memory are provided along the vertical sides of the central pair115of super columns. These columns114,116will be examined in closer detail shortly.

From a more generalized perspective, the tiling of the plural tiles creates pairs of adjacent interconnect channels within the core of the device100. An example of a pair of adjacent interconnect channels is seen at HIC's1and2. The peripheral channels (HIC0, HIC7, VIC0, VIC7) are not so paired. Switch matrix boxes (not shown, seeFIG. 2) are provided at the intersections of the respective vertical and horizontal interconnect channels. The switch matrix boxes form part of each matrix tile construct that includes a super-VGB at its center. See area465of FIG.3.

The left memory column (LMC)114is embedded as shown to the left of central columns pair115. The right memory column (RMC)116is further embedded as shown to the right of the central columns pair115. It is contemplated to have alternate embodiments with greater numbers of such embedded memory columns symmetrically distributed in the FPGA device and connected in accordance with the teachings provided herein for the illustrative pair of columns,114and116. It is also possible to additionally have embedded rows of such embedded memory extending horizontally.

Within the illustrated LMC114, a first, special, vertical interconnect channel (SVIC)164is provided adjacent to respective, left memory blocks MLO through ML7. Within the illustrated RMC164, a second, special, vertical interconnect channel (SVIC)166is provided adjacent to respective, right memory blocks MRO through MR7.

As seen, the memory blocks, ML0-ML7and MR0-MR7are numbered in accordance with the VGB row they sit in (or the HIC they are closest to) and are further designated as left or right (L or R) depending on whether they are respectively situated in LMC114or RMC116. In one embodiment, each of memory blocks, ML0-ML7and MR0-MR7is organized to store and retrieve an addressable plurality of nibbles, where a nibble contains 4 data bits. More specifically, in one embodiment, each of memory blocks, ML0-ML7and MR0-MR7has an internal SRAM array organized as a group of 32 nibbles (32×4=128 bits) where each nibble is individually addressable by five address bits. The nibble-wise organization of the memory blocks, ML0-ML7and MR0-MR7corresponds to the nibble-wise organization of each VGB (102) and/or to the nibble-wise organization of each group of four CBB's that line the side of each SVGB (101). Thus, there is a data-width match between each embedded memory block and each group of four CBB's or VGB. As will be seen a similar kind of data-width matching also occurs within the diversified resources of the general interconnect mesh.

At the periphery of the FPGA device100, there are three input/output blocks (IOB's) for each row of VGB's and for each column of VGB's. One such IOB is denoted at140. The IOB's in the illustrated embodiment are shown numbered from1to96. In one embodiment, there are no IOB's directly above and below the LMC114and the RMC116. In an alternate embodiment, special IOB's such as shown in phantom at113are provided at the end of each memory column for driving address and control signals into the corresponding memory column.

Each trio of regular IOB's at the left side (1-24) and the right side (49-72) of the illustrated device100may be user-configured to couple data signals to the nearest HIC. Similarly, each trio of regular IOB's on the bottom side (25-48) and top side (73-96) may be user-configured for exchanging input and/or output data signals with lines inside the nearest corresponding VIC. The SIOB's (e.g.,113), if present, may be userconfigured to exchange signals with the nearest SVIC (e.g.,164). Irrespective of whether the SIOB's (e.g.,113) are present, data may be input and/or output from points external of the device100to/from the embedded memory columns114,116by way of the left side IOB's (1-24) and the right side IOB's (49-72) using longline coupling, as will be seen below. The longline coupling allows signals to move with essentially same speed and connectivity options from/to either of the left or right side IOB's (1-24,49-72) respectively to/from either of the left or right side memory columns.

It is sufficient for the present to appreciate that each IOB includes one or more clocked flip flops and that each IOB is capable of receiving at least one bit of external input data from a point outside the FPGA device, and/or outputting at least one bit of external output data to a point outside the FPGA device, and/or storing one bit of input or output data in respective ones of its one or more flip flops, and/or of transferring such external input or output data respectively to or from adjacent interconnect lines. Each set of 24 IOB's that lie adjacent to a corresponding one of the peripheral HIC's and VIC's may therefore transfer in parallel, as many as 24 I/O bits at a time. Such transference may couple to the adjacent one of the peripheral HIC's and VIC's and/or to neighboring VGB's.

Data and/or address and/or control signals may be generated within the FPGA device100by its internal VGB's and transmitted to the embedded memory114,116by way of the peripheral and inner HIC's, as will be seen below.

The VGB's are numbered according to their column and row positions. Accordingly, VGB(0,0) is in the top left corner of the device100, VGB(7,7) is in the bottom right corner of the device100; and VGB(1,1) is in the bottom right corner of SVGB101.

Each SVGB (101) may have centrally-shared resources. Such centrally-shared resources are represented inFIG. 1by the diamond-shaped hollow at the center of each illustrated super-VGB (e.g.,101). Longline driving amplifiers (seeFIG. 5) correspond with these diamond-shaped hollows and have their respective outputs coupling vertically and horizontally to the adjacent HIC's and VIC's of their respective superVGB's.

As indicated above, each super-VGB inFIG. 1has four CBB's along each of its four sides. The four CBB's of each such interconnect-adjacent side of each super-VGB can store a corresponding four bits of result data internally so as to define a nibble of data for output onto the adjacent interconnect lines. At the same time, each VGB contains four CBB's of the L-shaped configuration which can acquire and process a nibble's worth of data. One of these processes is nibble-wide addition within each VGB as will be described below. Another of these processes is implementation of a 4:1 dynamic multiplexer within each CBB. The presentation of CBB's in groups of same number (e.g., 4 per side of a super-VGB and 4 within each VGB) provides for a balanced handling of multi-bit data packets along rows and columns of the FPGA matrix. For example, nibbles may be processed in parallel by one column of CBB's and the results may be efficiently transferred in parallel to an adjacent column of CBB's for further processing. Such nibble-wide handling of data also applies to the embedded memory columns114/116. As will be seen, nibble-wide data may be transferred between one or more groups of four CBB's each to a corresponding one or more blocks of embedded memory (MLx or MRx) by way of set of 4 equally-long lines in a nearby HIC. Each such set of 4 equally-long lines may be constituted by so-called, double-length lines (2xL lines), quad-length lines (4xL lines), octal-length lines (8xL lines) or maximum length longlines (MaxL lines).

In one particular embodiment of the FPGA device, the basic matrix is 10-by-10 SVGB's, with embedded memory columns114/116positioned around the central two super columns115. (SeeFIG. 2.) In that particular embodiment, the integrated circuit may be formed on a semiconductor die having an area of about 100,000 mils2or less. The integrated circuit may include four metal layers for forming interconnect. So-called ‘direct connect’ lines and ‘longlines’ of the interconnect are preferably implemented entirely by the metal layers so as to provide for low resistance pathways and thus relatively small RC time constants on such interconnect lines. Logic-implementing transistors of the integrated circuit have drawn channel lengths of 0.35 microns or 0.25 microns or less. Amplifier output transistors and transistors used for interfacing the device to external signals may be larger, however.

As indicated above, the general interconnect channels (e.g., HIC150, VIC160ofFIG. 1) contain a diverse set of interconnect lines.FIG. 2shows a distribution200of different-length horizontal interconnect lines (2xL, 4xL, 8xL) and associated switch boxes of a single horizontal interconnect channel (HIC)201, as aligned relative to vertical interconnect channels in an FPGA of the invention. This particular FPGA has a 10×10 matrix of super-VGB's (or a 20×20 matrix of VGB's). The embedded memory columns (114/116) are not fully shown, but are understood to be respectively embedded in one embodiment, between VIC's7-8and11-12, as indicated by zig-zag symbols214and216.

For an alternate embodiment, symbol214may be placed between VIC's6and7while symbol216is placed between VIC's12and13to indicate the alternate placement of the embedded memory columns114/116between said VIC's in the alternate embodiment. For yet another alternate embodiment, zig-zag symbol214may be placed between VIC's8and9while zig-zag symbol216is placed between VIC's10and11to represent corresponding placement of the embedded memory columns114/116in the corresponding locations. Of course, asymmetrical placement of the embedded memory columns114/116relative to the central pair of SVGB columns (115) is also contemplated. In view of these varying placement possibilities, the below descriptions of which 2xL, 4xL, or 8xL line intersects with corresponding columns214/216should, of course, be read as corresponding to the illustrated placement of symbols214and216respectively between VIC's7-8and VIC's11-12with corresponding adjustments being made if one of the alternate placements of214/216is chosen instead.

By way of a general introduction to the subject of interconnect resources, it should be noted that the interconnect mesh of FPGA100includes lines having different lengths. It may be said that, without taking into account any length changes created by the imposition of the embedded memory columns114/116, the horizontally-extending general interconnect channels (HIC's) and vertically-extending general interconnect channels (VIC's) of the FPGA device100are provided with essentially same and symmetrically balanced interconnect resources for their respective horizontal (x) and vertical (y) directions. These interconnect resources include a diversified and granulated assortment of MaxL lines, 2xL lines, 4xL lines and 8xL lines as well as corresponding 2xL switch boxes, 4xL switch boxes, and 8xL boxes.

In one embodiment, each general channel, such as the illustrated example inFIG. 2of HIC201(the horizontal interconnect channel), contains at least the following resources: eight double-length (2xL) lines, four quad-length (4xL) lines, four octal-length (8xL) lines, sixteen full-length (MaxL) lines, sixteen directconnect (DC) lines, eight feedback (FB) lines and two dedicated clock (CLK) lines. Vertical ones of the general interconnect channels (VIC's) may contain an additional global reset (GR) longline. Parts of this total of 58/59 lines may be seen inFIGS. 4 and 5as having corresponding designations AILO through AIL57/58for respective interconnect lines that are adjacent to corresponding VGB's. Not all of the different kinds of lines are shown in FIG.2. Note that each of the 2xL, 4xL, 8xL and MaxL line sets includes at least four lines of its own kind for carrying a corresponding nibble's worth of data or address or control signals.

InFIG. 2, core channels1through18are laid out as adjacent pairs of odd and even channels. Peripheral channels0and19run alone along side the IOB's (see FIG.1). Although not shown inFIG. 2, it should be understood that each switch box has both horizontally-directed and vertically-directed ones of the respective 2xL, 4xL, and 8xL lines entering into that respective switch box. (See region465ofFIG. 3.) A given switchbox (XxSw) may be user-configured to continue a signal along to the next XxL line (e.g., 2xL line) of a same direction and/or to couple the signal to a corresponding same kind of XxL line of an orthogonal direction. A more detailed description of switchboxes for one embodiment may be found in the above-cited, U.S. Ser. No. 09/008,762, filed Jan. 19, 1998 by inventors Om Agrawal et al whose disclosure is incorporated herein by reference.

Group202represents the 2xL lines of HIC201and their corresponding switch boxes. For all of the 2xL lines, each such line spans the distance of essentially two adjacent VGB's (or one super-VGB). Most 2xL lines terminate at both ends into corresponding 2x switch boxes (2xSw's). The terminating 2xSw boxes are either both in even-numbered channels or both in odd-numbered channels. Exceptions occur at the periphery where either an odd or even-numbered channel is nonexistent. As seen in the illustrated embodiment200, interconnections can be made via switch boxes from the 2xL lines of HIC201to any of the odd and even-numbered vertical interconnect channels (VIC's)0-19.

With respect to the illustrated placement214/216of embedded memory columns114/116, note in particular that 2xL line223and/or its like (other, similarly oriented 2xL lines) may be used to provide a short-haul, configurable connection from SVGB253(the one positioned to the right of VIC #6) to LMC214. Similarly, line224and its like may be used to provide a short-haul connection from SVGB254(the one positioned to the right of VIC #8) to LMC214. Line225and/or its like may be used to provide a short-haul connection from SVGB255to RMC216. Line226and/or its like may be used to provide a short-haul connection from SVGB256to RMC216. Such short-haul connections may be useful for quickly transmitting speed-critical signals such as address signals and/or data signals between a nearby SVGB (253-256) and the corresponding embedded memory column114or116.

Group204represents the 4xL lines of HIC201and their corresponding switch boxes. Most 4xL lines each span the distance of essentially four, linearly-adjacent VGB's and terminate at both ends into corresponding 4x switch boxes (4xSw's). The terminating 4xSw boxes are either both in even-numbered channels or both in odd-numbered channels. As seen in the illustrated embodiment200, interconnections can be made via switch boxes from the 4xL lines of HIC201to any of the odd and evennumbered vertical interconnect channels (VIC's)0-19.

With respect to the illustrated placement214/216of embedded memory columns114/116, note in particular that 4xL line242and/or its like (other, similarly oriented 4xL lines that can provide generally similar coupling) may be used to provide a medium-haul configurable connection between LMC214and either one or both of SVGB252and SVGB253. Line243and/or its like may be used to provide a configurable connection of medium-length between LMC214and either one or both of SVGB's253and254. Similarly, line245and/or its like may be used to provide medium-length coupling between RMC216and either one or both of SVGB's255and256. Moreover, line247and/or its like may be used to configurably provide medium-haul interconnection between RMC216and either one or both of SVGB's257and256. Such medium-haul interconnections may be useful for quickly propagating address signals and/or data signals in comparatively medium-speed applications.

Group208represents the 8xL lines of HIC201and their corresponding switch boxes. Most 8xL lines (7 out of 12) each spans the distance of essentially eight, linearly-adjacent VGB's. A fair number of other 8xL lines (5 out of 12) each spans distances less than that of eight, linearly-adjacent VGB's. Each 8xL line terminates at least one end into a corresponding 8x switch box (8xSw). The terminating 8xSw boxes are available in this embodiment only in the core oddnumbered channels (1,3,5,7,9,11,13,15and17). Thus, in embodiment200, interconnections can be made via switch boxes from the 8xL lines of HIC201to any of the nonperipheral, odd-numbered vertical interconnect channels (VIC's). It is within the contemplation of the invention to have the 8xSw boxes distributed symmetrically in other fashions such that even-numbered channels are also covered.

With respect to the illustrated placement214/216of embedded memory columns114/116, note in particular that 8xL line281or its like may be used to provide even longer-haul, configurable connection from between LMC214and any one or more of SVGB's251-254. (In one embodiment where 214 places to the left of VIC7, 8xL line280provides configurable interconnection between LMC214and any one or more of SVGB's250-253.) In the illustrated embodiment, 8xL line282may be used to provide 8xL coupling between any two or more of: LMC214and SVGB's252-255. Line283may be used to provide 8xL coupling between any two or more of: LMC214, RMC216, and SVGB's253-256. Line284may be used to provide 8xL coupling between any two or more of: LMC214, RMC216, and SVGB's254-257. Line285may be used to provide 8xL coupling between any two or more of: RMC216and SVGB's255-258. Line286may be similarly used to provide 8xL coupling between any two or more of: RMC216and SVGB's256-259. Although the largest of the limited-length lines is 8xL in the embodiment ofFIG. 2, it is within the contemplation of the invention to further have 16xL lines, 32xL lines and so forth in arrays with larger numbers of VGB's.

In addition to providing configurable coupling between the intersecting memory channel214and/or216, each of the corresponding 2xL, 4xL, 8xL and so forth lines may be additionally used for conveying such signals between their respective switchboxes and corresponding components of the intersecting memory channel.

Referring briefly back toFIG. 1, it should be noted that the two central super columns115are ideally situated for generating address and control signals and broadcasting the same by way of short-haul connections to the adjacent memory columns114and116. High-speed data may be similarly conveyed from the memory columns114/116to the SVGB's of central columns115.

Before exploring more details of the architecture of FPGA device100, it will be useful to briefly define various symbols that may be used within the drawings. Unless otherwise stated, a single line going into a trapezoidal multiplexer symbol is understood to represent an input bus of one or more wires. Each open square box (MIP) along such a bus represents a point for user-configurable acquisition of a signal from a crossing line to the multiplexer input bus. In one embodiment, a PIP (programmable interconnect point) is placed at each MIP occupied intersection of a crossing line and the multiplexer input bus. Each of PIP (which may be represented herein as a hollow circle) is understood to have a single configuration memory bit controlling its state. In the active state the PIP creates a connection between its crossing lines. In the inactive state the PIP leaves an open between the illustrated crossing lines. Each of the crossing lines remains continuous however in its respective direction (e.g., x or y).

PIP's (each of which may be represented herein by a hollow circle covering a crossing of two continuous lines) may be implemented in a variety of manners as is well known in the art. In one embodiment pass transistors such as MOSFET's may be used with their source and drain respectively coupled to the two crossing lines while the transistor gate is controlled by a configuration memory bit. In an alternate embodiment, nonvolatilely-programmable floating gate transistors may be used with their source and drain respectively coupled to the crossing lines. The charge on the floating gate of such transistors may represent the configuration memory bit. A dynamic signal or a static turn-on voltage may be applied to the control gate of such a transistor as desired. In yet another alternate embodiment, nonvolatilely-programmable fuses or anti-fuses may be provided as PIP's with their respective ends being connected to the crossing lines. One may have bidirectional PIP's for which signal flow between the crossing lines (e.g.,0and1) can move in either direction. Where desirable, PIP's can also be implemented with unidirectional signal coupling means such as AND gates, tri-state drivers, and so forth.

An alternate symbol for a group of PIP's is constituted herein by a hollow and tilted ellipse covering a bus such as is seen in FIG.10.

Another symbol that may be used herein is a hollow circle with an ‘X’ inside. This represents a POP. POP stands for ‘Programmable Opening Point’. Unless otherwise stated, each POP is understood to have a single configuration memory bit controlling its state. In the active state the POP creates an opening between the colinear lines entering it from opposing sides. In the inactive state the POP leaves closed an implied connection between the colinear lines entering it. Possible implementations of POP's include pass transistors and tri-state drivers. Many other alternatives will be apparent to those skilled in the art.

Referring now toFIG. 3, this figure provides a mid-scopic view of some components within an exemplary matrix tile400that lays adjacent to embedded memory column, RMC416. Of course, other implementations are possible for the more macroscopic view of FIG.1.

The mid-scopic view ofFIG. 3shows four VGB's brought tightly together in mirror opposition to one another. The four, so-wedged together VGB's are respectively designated as (0,0), (0,1), (1,0) and (1,1). The four VGB's are also respectively and alternately designated herein as VGB_A, VGB_B, VGB_C, and VGB_D.

Reference number430points to VGB_A which is located at relative VGB row and VGB column position (0,0). Some VGB internal structures such as CBB's Y, W, Z, and X are visible in the mid-scopic view of FIG.3. An example of a Configurable Building Block (CBB) is indicated by410. As seen, the CBB's410of each VGB430are arranged in an L-shaped organization and placed near adjacent interconnect lines. Further VGB internal structures such as each VGB's common controls developing (Ctrl) section, each VGB's wide-gating supporting section, each VGB's carry-chaining (Fast Carry) section, and each VGB's coupling to a shared circuit450of a corresponding super-structure (super-VGB) are also visible in the mid-scopic view of FIG.3. VGB local feedback buses such as the L-shaped structure shown at435inFIG. 3allow for high-speed transmission from one CBB to a next within a same VGB, of result signals produced by each CBB.

The mid-scopic view ofFIG. 3additionally shows four interconnect channels surrounding VGB's (0,0) through (1,1). The top and bottom, horizontally extending, interconnect channels (HIC's) are respectively identified as451and452. The left and right, vertically extending, interconnect channels (VIC's) are respectively identified as461and462.

Two other interconnect channels that belong to other tiles are partially shown at453(HIC2) and463(VIC2) so as to better illuminate the contents of switch boxes area465. Switch boxes area465contains an assortment of 2xL switch boxes, 4x switch boxes and 8x switch boxes, which may be provided in accordance with FIG.2.

In addition, a memory-control multiplexer area467is provided along each HIC as shown for configurably coupling control signals from the horizontal bus (e.g., HIC452) to special vertical interconnect channel (SVIC)466. The illustrated placement of multiplexer area467to the right of the switch boxes (SwBoxes) of VIC's462and463is just one possibility. Multiplexer area467may be alternatively placed between or to the left of the respective switch boxes of VIC's462and463.

In one embodiment (see FIG.8), SVIC466has sixteen, special maximum length lines (16 SMaxL lines), thirty-two, special quad length lines (32 S4xL lines), and four special clock lines (SCLK0-3). SVIC466carries and couples control signals to respective control input buses such as471,481of corresponding memory blocks such as470,480.

A memory-I/O multiplexer area468is further provided along each HIC for configurably coupling memory data signals from and to the horizontal bus (e.g., HIC452) by way of data I/O buses such as472,482of corresponding memory blocks such as470,480. Again, the illustrated placement of multiplexer area468to the right of the switch boxes (SwBoxes) of VIC's462and463is just one possibility. Multiplexer area468may be alternatively placed between or to the left of the respective switch boxes of VIC's462and463.

Memory control multiplexer area477and memory I/O multiplexer area478are the counterparts for the upper HIC451of areas467and468of lower HIC452. Although not specifically shown, it is understood that the counterpart, left memory channel (LMC) is preferably arranged in mirror symmetry to the RMC416so as to border the left side of its corresponding matrix tile.

As seen broadly inFIG. 3, the group of four VGB's (0,0) through (1,1) are organized in mirror image relationship to one another relative to corresponding vertical and horizontal centerlines (not shown) of the group and even to some extent relative to diagonals (not shown) of the same group. Vertical and horizontal interconnect channels (VIC's and HIC's) do not cut through this mirror-wise opposed congregation of VGB's. As such, the VGB's may be wedged-together tightly.

Similarly, each pair of embedded memory blocks (e.g.,470and480), and their respective memory-control multiplexer areas (477and467), and their respective memory-I/O multiplexer areas (478and468) are organized in mirror image relationship to one another as shown. Horizontal interconnect channels (HIC's) do not cut through this mirror-wise opposed congregation of embedded memory constructs. As such, the respective embedded memory constructs of blocks MRx0(in an even row,470being an example) and MRx1(in an odd row,480being an example) may be wedged-together tightly. A compact layout may be thereby achieved.

With respect to mirror symmetry among variable grain blocks, VGB (0,1) may be generally formed by flipping a copy of VGB (0,0) horizontally. VGB (1,1) may be similarly formed by flipping a copy of VGB (0,1) vertically. VGB (1,0) may be formed by flipping a copy of VGB (1,1) horizontally, or alternatively, by flipping a copy of VGB (0,0) vertically. The mirror-wise symmetrical packing-together of the four VGB's (0,0through1,1) is referred to herein as a ‘Super Variable Grain Block’ or a super-VGB440.

In a preferred embodiment, the mirror symmetry about the diagonals of the super-VGB is not perfect. For example, there is a Fast Carry section in each VGB that allows VGB's to be chained together to form multi-nibble adders, subtractors or counters. (A nibble is a group of 4 data bus. A byte is two nibbles or 8 data bits. A counter generally stores and feeds back its result so as to provide cumulative addition or subtraction.) The propagation of rippled-through carry bits for these Fast Carry sections is not mirror wise symmetrical about the diagonals of each super-VGB440. Instead it is generally unidirectional along columns of VGB's. Thus, CBB's X, Z, W, and Y are not interchangeable for all purposes.

The unidirectional propagation of carry bits is indicated for example by special direct connect lines421a,421b and421c which propagate carry bits upwardly through the Fast Carry portions of VGB's (0,0) and (1,0). The unidirectional propagation is further indicated by special direct connect lines422a,422b and422c which propagate carry bits upwardly through the Fast Carry portions of VGB's (0,1) and (1,1).

Such unidirectional ripple-through of carry bits may continue across the entire FPGA device so as to allow addition, subtraction or count up/down results to form in bit aligned fashion along respective columns of the FPGA device. Bit aligned results from a first set of one or more columns can be submitted to other columns (or even resubmitted to one or more columns of the first set) for further bit aligned processing. In one embodiment, the X CBB generally produces the relatively least significant bit (LSB) of result data within the corresponding VGB, the Z CBB generally produces the relatively next-more significant bit, the W CBB generally produces the relatively next-more significant bit, and the Y CBB generally produces the relatively most significant bit (MSB) of result data within the corresponding VGB.

In an alternate embodiment, propagation of rippledthrough carry bits may be zig-zagged first up and then down through successive columns of VGB's. In such an alternate zig-zagged design, the significance of bits for adder/subtractor circuits would depend on whether the bits are being produced in an odd or even column of VGB's.

The local feedback lines435of each VGB may be used to feedback its registered adder outputs to one of the adder inputs and thereby define a counter. The counter outputs can be coupled by way of the adjacent HIC to either an intersecting SVIC (e.g.,466, so as to provide address sequencing) or to an adjacent data port (e.g.,472,482, so as to store counter results in the embedded memory at designated time points).

FIGS. 4-7Dare provided to facilitate the understanding of the coupling that is provided by way of the HIC's (e.g.,451and452) between the embedded memory blocks (470) and corresponding inputs and outputs of the super-VGB's (440) and/or IOB's. It is helpful to study the I/O structure of selected components within each super-VGB and IOB to some extent so that the data and control input/output interplay between the embedded memory columns114/116and the SVGB's and the IOB's can be appreciated. At the same time, it is to be understood that the description given here for the SVGB's and IOB's may be less extensive than that given in the above-cited Ser. Nos. 08/948,306 and 08/995,615. The description given here for the SVGB's and IOB's are intended to provide no more than a basic understanding of the cooperative structuring of the embedded memory blocks (470/480) and corresponding inputs and outputs of the super-VGB's (440) and IOB's (see FIG.7A).

Referring toFIG. 6A, each of the X, Z, W, and Y Configurable Building Blocks of each VGB has six 19:1, input-terms acquiring multiplexers (shown as a single set with an x6 wide input bus) for acquiring a corresponding six input term signals of the CBB from adjacent interconnect lines (AIL's). The CBB can process its respectively acquired signals in accordance with user-configuration instructions to produce result signals. The Yz_A signal548output by the Y CBB540ofFIG. 6Ais an example of such a result signal.

Each of the X, Z, W, and Y CBB's further has a result-signal storing register (e.g.,667ofFIG. 6B) and a 2/4/8xL drive amplifier (e.g.,630of FIG.6B). A configurable bypass multiplexer (e.g.,668ofFIG. 6B) allows the CBB to be configured to output either a register-stored version of a CBB result signal or a nonstored (unregistered) result signal of the CBB onto adjacent ones of the 2xL lines, 4xL lines and 8xL lines. Various, dynamic control signals may be used by the CBB for controlling its internal, result-signal storing register (e.g.,667). These control signals are acquired by way of respective, controls input multiplexers (14:1 Ctrl, shown inFIG. 6A) of the respective CBB's X,Z,W,Y. There are two such controls input multiplexers (14:1 Ctrl) provided for each CBB.

In addition to its 2/4/8xL drive amplifier, each of the X, Z, W, and Y CBB's further has a dedicated directconnect (DC) drive amplifier (shown as DC Drive in FIG.6A and as610inFIG. 6B) which can configurably output either a register-stored version of a CBB result signal or an non-stored (unregistered) result signal of the CBB onto adjacent ones of so-called, direct connect lines. Moreover, each CBB has means for outputting its registered or unregistered result-signals onto feedback lines (FBL's608and671) of the VGB. The DCL's (direct connect lines) and FBL's are not immediately pertinent to operation of the embedded memory blocks (470) but are mentioned here for better understanding of next-described FIG.4.

FIG. 4looks at the 2/4/8xL driver output connections for each super-VGB. InFIG. 4, each CBB has four respective output lines for driving nearby 2xL interconnect lines, 4xL interconnect lines and 8xL interconnect lines that surround the encompassing super VGB. The four respective output lines of each CBB may all come form one internal 2/4/8xL line driving amplifier (e.g.,630ofFIG. 6B) or from different drive amplifiers.

The layout ofFIG. 4is essentially symmetrical diagonally as well as horizontally and vertically. The octal length (8xL) lines are positioned in this embodiment further away from the VGB's401-404than are the 4xL and 2xL lines of the respective vertical and horizontal interconnect channels. AIL line0of each of the illustrated VIC's and HIC's is at the outer periphery and AIL numbers run generally from low to high as one moves inwardly. The quad length (4xL) lines are positioned in this embodiment further away from the VGB's than are the double length (2xL) lines of the respective VIC's and HIC's. It, is within the contemplation of the invention to alternatively position the octal length (8xL) lines closest to VGB's401-404, the quad length (4xL) lines next closest, and the double length (2xL) lines of the respective VIC's and HIC's furthest away from surrounded VGB's401-404. The same pattern of course repeats in each super-VGB of the FPGA core matrix.

VGB_A (401) can couple to same AIL's in the northern octals (Octals(N)) as can VGB_D (404) in the southern octals (Octals(S)). A similar, diagonal symmetry relation exists between VGB_B (402) and VGB_C (403). Symmetry for the eastern and western octal connections is indicated by PIP's431,432,433and434moving southwardly along the west side of the tile and by counterposed PIP's441,442,443and444moving northwardly along the east side.

Note that the non-adjacent 2xL connections of this embodiment (e.g., the PIP connection of the Y CBB in VGB401to vertical AIL #40) allow for coupling of a full nibble of data from any VGB to the 2xL lines in either or both of the adjacent VIC's and HIC's. Thus, busoriented operation may be efficiently supported by the L-organized CBB's of each VGB in either the horizontal or vertical direction. Each CBB of this embodiment has essentially equivalent access to output result signals to immediately adjacent 2xL, 4xL and 8xL lines as well as to nonadjacent 2xL lines (in the AIL40-43sets). Each pair of VGB's of a same row of column can output4independent result signals to a corresponding 4 lines in any one of the following 4-line buses, (a) the immediately adjacent 2xL0group (AIL's16-19), (b) the immediately adjacent 4xL group (AIL's48-51), (c) the immediately adjacent 8xL group (AIL's0-3), and (d) the not immediately adjacent 2xL1group (AIL's40-43).

Aside from having dedicated 2/4/8xL drivers in each CBB, there are shared big drivers (tristateable MaxL drivers) at the center of each super-VGB for driving the MaxL lines of the surrounding horizontal and vertical interconnect channels (HIC's and VIC's). Referring toFIG. 5, a scheme for connecting the shared big drivers (MaxL drivers) to the adjacent MaxL interconnect lines is shown for the case of super-VGB (0,0). This super-VGB (also shown as101inFIG. 1) is surrounded by horizontal interconnect channels (HIC's)0and1and by vertical interconnect channels (VIC's)0and1. The encompassed VGB's are enumerated as A=(0,O), B=(0,1), C=(1,0) and D=(1,1). A shared big logic portion of the SVGB is shown at580. Shared big logic portion580receives input/control signals501,502,503,504and responsively sends corresponding data and control signals to sixteen, three-state (tristate) longline driving amplifiers that are distributed symmetrically relative to the north, east, south and west sides of the SVGB. The sixteen, tristate drivers are respectfully denoted as: N1through N4, E1through E4, S1through S4, and W1through W4. Angled line501represents the supplying of generically-identified signals: DyOE, Yz, Wz, Xz, Zz, FTY(1,2) and FTX(1,2) to block580from VGB_A. DyOE is a dynamic output enable control. Yz, Wz, Xz; Zz are respective result signals from the Y, W, X, Z CBB's of VGB_A. FTY(1,2) and FTX(1,2) are feedthrough signals passed respectively through the Y and X CBB's of VGB_A. Angled lines502,503and504similarly and respectively represent the supplying of the above generically-identified signals to block580respectively from VGB_B, VGB_C and VGB_D.

Note that the tristate (3-state) nature of the shared big drivers means that signals may be output in time multiplexed fashion onto the MaxL lines at respective time slots from respective, bus-mastering ones of the SVGB's along a given interconnect channel.

The adjacent MaxL interconnect lines are subdivided in each HIC or VIC into four groups of 4 MaxL lines each. These groups are respectively named MaxL0, MaxL1, MaxL2and MaxL3as one moves radially out from the core of the super-VGB. MaxL drivers N1through N4respectively connect to the closest to the core, lines of respective groups MaxL0, MaxL1, MaxL2and MaxL3of the adjacent north HIC.

MaxL drivers E1through E4similarly and respectively connect to the closest to the core ones of MaxL lines in respective groups MaxL0-MaxL3of the adjacent east VIC. MaxL drivers S1through S4similarly and respectively connect to the closest to the core ones of MaxL lines in respective groups MaxL0-MaxL3of the adjacent south HIC. MaxL drivers W1through W4similarly and respectively connect to the closest to the core ones of MaxL lines in respective groups MaxL0-MaxL3of the adjacent west vertical interconnect channel (VIC(0)).

As one steps right to a next super-VGB (not shown), the N1-N4connections move up by one line in each of the respective groups MaxL0-MaxL3, until the top most line is reached in each group, and then the connections wrap around to the bottom most line for the next super-VGB to the right and the scheme repeats.

A similarly changing pattern applies for the southern drives. As one steps right to a next super-VGB (not shown), the S1-S4connections move down by one line in each of the respective groups MaxL0-MaxL3, until the bottom most line is reached in each group, and then the connections wrap around to the top most line for the next super-VGB to the right and the scheme repeats.

A similarly changing pattern applies for the eastern and western drives. As one steps down to a next super-VGB (not shown), the E1-E4and W1-W4connections move outwardly by one line in each of the respective groups MaxL0-MaxL3, until the outer most line is reached in each group, and then the connections wrap around to the inner most line of each group for the next super-VGB down and the scheme repeats. Thus, on each MaxL line, there are multiple tristate drivers that can inject a signal into that given MaxL line.

The group of MaxL lines in each channel that are driven by tristate drivers ofFIG. 5are referred to herein as the ‘TOP’ set. This TOP set comprises AIL's #8, #24, #32and #12of respective groups MaxL0, MaxL1, MaxL2and MaxL3. (The designation of this set as being TOP is arbitrary and coincides with the label TOP in the right bottom corner ofFIG. 5as applied to the bottom MaxL0group.)

In similar fashion, the group of MaxL lines in each channel that are driven by tristate drivers of the next to the right SVGB are referred to herein as the ‘2ND’ set. This 2ND set comprises AIL's #9, #25, #33and #13. The group of MaxL lines in each channel that are driven by tristate drivers of the twice over to the right SVGB are referred to herein as the ‘3RD’ set. This 3RD set comprises AIL's #10, #26, #34and #14. The group of MaxL lines in each channel that are driven by tristate drivers of the thrice over to the right SVGB are referred to herein as the ‘BOT’ set. This BOT set comprises AIL's #11, #27, #35and #15.

FIG. 7Aillustrates how IOB's interface with the MaxL lines, and in particular the TOP set of AIL's #8, #24, #32and #12; and the 3RD set of AIL's #10, #26, #34and #14.

Internal details of each IOB are not germane to the immediate discussion and are thus not fully shown in FIG.7A. However, as shown inFIG. 7A, each IOB such as IOB_LO (at the top, left) includes two longline driving tristate drivers790and791for driving a respective pair of MaxL lines. The illustrated tristate drivers790and791for example, respectively drive TOP AIL #8and 2ND AIL #9. Input signals of the respective two longline driving tristate drivers,790and791, may be configurably derived from a number of sources including external I/O pin792of the corresponding FPGA device (e.g.,100of FIG.1). Other sources include one or both of two bypassable and serially-coupled registers within each IOB as will be seen in FIG.7B.

Each IOB ofFIG. 7A, such as IOB_LO; further includes a pin-driving tristate driver (with configurably-variable slew rate) such as shown at794. Input signals of the pin-driving tristate driver794may be configurably derived from a number of sources including from user-configurable multiplexer795. Two of the selectable inputs of multiplexer795are coupled to the same two longlines driven by that same IOB. In the case of IOB_LO for example, that would be TOP AIL #8and 2ND AIL #9.

The remaining IOB's shown inFIG. 7Ahave similar internal structures. As seen, at the left side of the FPGA device, between even-numbered HIC(0) and oddnumbered HIC(1), there are provided six IOB's respectively identified as IOB_LO through IOB_L5. At the right side of the FPGA device there are further provided six more IOB's respectively identified as IOB_RO through IOB_R5. The external I/O pins are similarly identified as PIN_RO through PIN_R5on the right side and as PIN_LO through PIN_L5on the left side. The same connection pattern repeats between every successive set of even and odd-numbered HIC's.FIG. 7Amay be rotated ninety degrees to thereby illustrate the IOB-to-MaxL lines connectivity pattern for the VIC's as well. (References to horizontal lines will of course be changed to vertical and references to left and right IOB's will of course be changed to top and bottom.)

On the left side, IOB_L0, IOB_L1and IOB_L2collectively provide bidirectional coupling at least to 3 TOP longlines (AIL's #8, #24, #32) and 1 3RD longline (AIL #14) in the adjacent even-numbered HIC(0). On the right side, IOB_R0, IOB_R1and IOB_R2collectively provide bidirectional coupling at least to 3 3RD longlines (AIL's #10, #26, #34) and 1 TOP longline (AIL #12) in the adjacent and same even-numbered HIC(0). The combination of the six IOB's of HIC(0) therefore allow for bidirectional coupling of nibble-wide data either to the TOP set ((AIL's #8, #24, #32and #12) and/or to the 3RD set (AIL's #10, #26, #34and #14).

As seen in the bottom half ofFIG. 7A, on the left side, IOB_L5, IOB_L4and IOB_L3collectively provide bidirectional coupling at least to 3 3RD longlines (AIL's #10, #26, #34) and 1 TOP longline (AIL #12) in the adjacent odd-numbered HIC(1). On the right side, IOB_R5, IOB_R4and IOB_R3collectively provide bidirectional coupling at least to 3 TOP longlines (AIL's #8, #24, #32) and 1 3RD longline (AIL #14) in the same odd-numbered HIC(1). The combination of the six IOB's of HIC(1) therefore allow for bidirectional coupling of nibble-wide data either to the TOP set (AIL's #8, #24, #32and #12) and/or to the 3RD set (AIL's #10, #26, #34and #14) of the odd-numbered, adjacent HIC.

In addition to the above-described couplings between the IOB's and the MaxL lines of the interconnect mesh, IOB's also couple by way of direct connect wires to peripheral ones of the SVGB's for both input and output. More specifically, there are direct connect wires connecting the left-side IOB's (IOB_L0through IOB_LS) to adjacent SVGB's of super column number0. Two such wires are represented as DC1and DC2coupling IOB_L2to the illustrated column-0SVGB.FIG. 7Aindicates that the super column0SVGB's can drive the same TOP set of longlines (AIL's #8, #24, #32and #12) that may be driven by the IOB's, and as will later be seen, by the embedded memory.

There are further direct connect wires connecting the right-side IOB's (IOB_R0through IOB_R5) to adjacent SVGB's of the rightmost super column. The column number of the rightmost super column is preferably (but not necessarily) equal to an even integer that is not a multiple of four. In other words, it is equal to 4m+2 where m=1, 2, 3, etc. and the leftmost super column is numbered0. That means there are a total of 4m+3 SVGB's per row. The latter implies that square SVGB matrices will be organized for example as 11×11, 13×13, 19×19, 23×23 SVGB's and so on. (If the same organizations are given in terms of VGB's, they become 22×22, 26×26, 38×38, 46×46 VGB's and so on.) The rightmost SVGB number (4m+2) connects by way of direct connect wires to the right-side IOB's.FIG. 7Aindicates that these super column number 4m+2 SVGB's can drive the same 3RD set of longlines (AIL's #10, #26, #34and #14) that may be driven by the IOB's, and as will later be seen, by the embedded memory.

In alternate embodiments, the extent of direct connect between IOB's to adjacent columns of SVGB's is increased from extending to just the most adjacent super column to extending to at least the first two or three nearest super columns. This allows the right-side IOB's to reach the SVGB's that drive the 3RD longline set with direct connections.

Aside from direct connect wires, IOB's may be further coupled to the SVGB's of the device by 2xL, 4xL, 8xL lines of the adjacent HIC's. Coupling between the IOB's and the 2xL, 4xL, 8xL lines of adjacent HIC's may be provided through a configurable dendrite structure that extends to the multiplexer795of each IOB from pairs of adjacent HIC's. The specific structure of such configurable dendrite structures (not shown) is not germane to the present disclosure. It is sufficient to understand that configurable coupling means are provided for providing coupling between the 2xL, 4xL, 8xL of the adjacent HIC's and the corresponding IOB's. A more detailed disclosure of dendrite structures may be found in the above-cited, US application Ser. No. 08/995,615.

FIG. 7Bmay now be referred to while keeping in mind the input/output structures of the surrounding SVGB's and IOB's as described above for respectiveFIGS. 1-5and7A. InFIG. 7B, control signals for synchronizing various I/O flows are shown in combination with elements that direct the I/O flows.

However, before describing these more complex structures of the IOB's, it will be beneficial to briefly refer to FIG.6B and to describe data flow structures that can direct various dynamic signals to the D (645), clock (663), clock-enable (664), reset (651) and set (652) input terminals of CSE flip flop667. It will be beneficial to also briefly describe data flow structures that can direct the Q output (669) of the CSE flip flop and/or register-bypassing alternate signals to various interconnect lines (2xL lines through MaxL lines).

Referring to6B, an example is shown of a specific CSE60Y that may be included within each Y CBB of each VGB. CSE60Y is representative of like CSE's (Configurable Sequential Elements) that may be included in the respective others of the X, W and Z CBB's of each VGB. The signal processing results of the given CBB (e.g., the Y one) may respectively appear on lines675and672as signals fa(3T) and fb(3T). Here, the notation fm(nT) indicates any Boolean function of up to n independent input bits as produced by a user-programmable LUT (lookup table, not shown) identified as LUT m. The output of a synthesized 4-input LUT may appear on line675as signal fY(4T). The output of a synthesized 6-input LUT may appear on line635as signal fD(6T). Alternatively, line635may receive a wide-gated signal denoted as fWO(p) which can represent a limited subset of functions having up to p independent input bits. In one embodiment, p is 16. A result signal (SB3) produced by an in-CBB adder/subtractor logic (570ofFIG. 6A) appears on line638. Configuration memory bits639are user-programmable so that multiplexer640can be instructed to route the result signal of a selected one of lines675,635and638to its output line645. As such, multiplexer640defines an example of a user-programmable, result-signal directing circuit that may be found in each CSE of the VGB500A shown in FIG.6A. Other result-signal directing circuits may be used as desired.

Each CSE includes at least one data storing flip-flop such as that illustrated at667. Flip-flop667receives reset (RST) and set control signals651and652in addition to clock signal663and clock enable signal664. A locally-derived control signal CTL1is presented at line655while a VGB common enable is presented on line654. Multiplexer604is programmably configurable to select one or the other of lines654,655for presentation of the selected input signal onto output line664. As explained above, lines672,675,635and638carry logic block (CBB) result signals. The control signals of lines651through655are derived from common controls section550of FIG.6A. The common controls section550acquires a subset of neighboring signals from AIL's by way of the 14:1 Ctrl multiplexers and defines a further subset or derivative of these as VGBcommon control signals. The signals of lines653,654and655may be used to control the timing of when states change at the outputs of respective line drivers610(DCL driver),620(to-tristate driver),630(2/8xL driver),668(FBL driver) and670(FBL driver). A more detailed explanation of such CBB-result signals may be found in at least one of the above-cited, copending applications.

With the three bits of configuration memory shown at639inFIG. 6B, a user can control multiplexer640to select an appropriate data signal645for supply to the D input of flip-flop667. The selected signal may bypass the flipflop by routing through a user-programmable multiplexer668to line608. Multiplexer668may be programmed to alternatively apply the Q output of flip-flop667to line608. Buffer610drives a direct-connect line612. Buffer630drives one or more of CBB-adjacent 2xL, 4xL or 8xL lines. Connection636is to a non-adjacent 2xL line (see FIG.4). Items632,633,634and638′ represent PIP-like, programmable connections for progra mably interconnecting their respective co-linear lines. A more detailed explanation of the CSE structure and its other components may be found in at least one of the above-cited, copending applications. For purposes of the present application, it is to be understood that elements620,670,632,634,638′ and633define examples of user-programmable, stored-signal directing circuits that may be found in each CSE of the VGB500A shown in FIG.6A and may be used for directing the Q output of flip flop667to one or more interconnect resources such adjacent 2xL-8xL lines or MaxL lines. Other stored-signal directing circuits may be used as desired.

Referring to the IOB structure700shown inFIG. 7B, this IOB700may be used to provide a configurable interconnection between the input/output pin/pad709and neighboring, internal interconnect resources. The chip-internal interconnect resources may supply signals for output by IOB700to external circuits, where the external circuits (not shown) connect to I/O pin or pad709. In particular, the internal interconnect resources that can supply such signals to an IOB first multiplexer710include a first plurality711of 8 direct connect lines (DCL's), a second plurality712of 6 MaxL lines, and a third plurality713of 6 dendrite lines (Dend's). The signal selected for output on line715of the multiplexer may be transmitted by way of register-bypass multiplexer725and pad-driving amplifier730for output through I/O pin/pad709.

External signals may also be brought in by way of I/O pin/pad709for transfer by the IOB700to one or more of a fourth plurality714a,b of two MaxL lines, and to one dendrite line715, and NOR line716, and one direct connect line717. Lines714a and714b are each connected to a respective MaxL line. Line716operates in open-collector mode such that it can be resistively urged to a normally-high state and can be pulled low by one or more open-collector drivers such as driver766. The illustrated INPUT_ENd line couples to a gate of one of plural, in series pull-down MOSFET transistors (not shown) in766that can sink current from the NOR line716.

IOB700includes a first register/latch720for storing a respective first output signal. This first output signal is supplied to a D input of unit720by line715. A plurality719of 20 configuration memory cells determines which interconnect resource will supply the signal to line715. In an alternate embodiment, a combination (not shown) of a decoder and a fewer number of configuration memory cells may be used to select a signal on one of lines711-713for output on line715.

IOB700includes a second register/latch750for storing an input signal supplied to a D input thereof by a dynamic multiplexer745. Input signals may flow from pad709, through input buffer740, through user-programmable delay742and/or through delay-bypass multiplexer744to one input terminal of dynamic multiplexer745. A second input terminal of dynamic multiplexer745couples to the Q output of the second register/latch750. The selection made by multiplexer745is dynamically controlled by an IOB INPUT_CLKEN signal supplied on line746.

A plurality of control signals may be input to IOB700for controlling its internal operations. These include input enable signals, INPUT_ENa, INPUT_ENb, INPUT_ENc, and INPUT_ENd. Input enable signals, INPUT_ENa, INPUT_ENb, and INPUT_ENC respectively drive the output enable terminals of respective tristate drivers761,762and765. The INPUT_ENd signal selectively enables the pull-down function of open-collector (open-drain) driver766as explained above. A respective plurality of four deactivating multiplexers771,772,775and one more (not shown) for766are provided for user-programmable deactivation of one or more of the respective tristate drivers761,762and765, and of driver766. In one embodiment, all of input enable signals, INPUT_ENa, INPUT_ENb, INPUT_ENc, and INPUT_ENd are tied together and designated simply as a common INPUT_EN signal. In an alternate embodiment, just the INPUT_ENa and INPUT_ENb enable signals are tied together and designated as a common and dynamically changeable, INPUT_EN signal while each of the INPUT_ENc and INPUT_ENd lines are tied to Vcc (set to logic ‘1’).

Further control signals that may be supplied to IOB700include an INPUT CLOCK signal (INPUT_CLK) on line747, the INPUT_CLKEN signal on line746, an OUTPUT_EN signal that couples to the QE terminal732of tristate driver730, an OUTPUT_CLOCK signal on line727, an OUTPUT_CLKEN signal on line726, and a COMMON SET/RST signal on lines705and705′. These control signals may be acquired from adjacent interconnect lines by one or more IOB control multiplexers such as the one illustrated in FIG.7C.

As illustrated inFIG. 7B, programmable memory bits in the FPGA configuration memory may be used to control static multiplexers such as728,748, etc. to provide programmable polarity selection and other respective functions. Static single-pole double-throw electronic switches706and708are further controlled by respective configuration memory bits (m) so that the COMMON SET/RST signal of lines705,705′ can be used to simultaneously reset both of register/latches720and750, or simultaneously set both of them, or set one while resetting the other.

An output of register by-pass multiplexer725is coupled to pad driving amplifier730. The amplifier730is controllable by a user-programmable, slew rate control circuit735. The slew rate control circuit735allows the output of pad driving amplifier730to either have a predefined, relatively fast or comparatively slow rise time subject to the state of the memory bit (m) controlling that function. The OUTPUT_EN signal supplied to terminal732of the pad driving amplifier730may be used switch the output of amplifier730into a high-impedance state so that other tristate drivers (external to the FPGA chip) can drive pad709without contention from driver730.

External signals may be input to IOB700as explained above via pin709and input buffer740. In one embodiment, the user-programmable delay element742comprises a chain of inverters each having pull-down transistors with relatively large channel lengths as compared to logic inverters of the same chip. The longer channel lengths provide a higher resistance for current sinking and thus increase the RC response time of the inverter. A plurality of user-programmable, internal multiplexers (not shown) of delay unit742define the number of inverters that a delayed signal passes through. The user-programmable delay element742may be used to delay incoming signals for the purpose of deskewing data signals or providing a near-zero hold time for register/latch750. A global clock signal (GK) of the FPGA array may be used for example as a source for the INPUT_CLOCK signal of line746. Due to clock skew, the global clock signal may not reach register/latch750before a data signal is provided to the D input of register/latch750. In such a situation, the variable delay function of element742may be used to delay incoming data signals acquired by buffer740so they can align more closely with clock edges provided on clock input terminal749of register742.

Each of configurable input register/latches720and750can be configured to operate either as a latch or as a register, in response to a respective memory bit setting (721,751) in the configuration memory. When the respective register/latch (720or740) operates as a register, data at its D input terminal is captured for storage and transferred to the its Q output terminal on the rising edge of the register's CLOCK signal (729or749). When the register/latch operates as a latch, any data change at D is captured and seen at Q while the signal on the corresponding CLOCK line (729or749) is at logic ‘1’ (high). When the signal on the CLOCK line returns to the logic ‘0’ state (e.g., low), the output state of Q is frozen in the present state, and any further change on D will not affect the condition of Q while CLOCK remains at logic ‘0’.

A COMMON SET/RST signal may be generated from a VGB to all IOBs or to a subset of IOBs in order to set or reset the respective latches (720,750) in the affected IOB's. The COMMON SET/RST signal may also be generated by peripheral device that is coupled to the FPGA array by way of a particular IOB.

The Q output of register/latch750couples to respective first input terminals of a plurality of user-programmable, register-bypassing multiplexers755and757. Multiplexer757drives direct connect amplifier760while multiplexer755drives amplifiers761,762,765and766. Respective second input terminals of register-bypassing multiplexers755and757receive a register-bypassing signal from the output of delay-enabling multiplexer744.

Referring to briefly back toFIG. 7A, for one subspecies of this embodiment, element790and791respectively correspond to elements761and762ofFIG. 7Bwhile element794corresponds to element730and element795corresponds to element710. While the specific embodiment ofFIG. 7Buses plural flip flops respectively for storing input and output signals, it is also within the contemplation of the invention to use a single flip flop for at different times storing either an input or output signal and for directing respective clock and clock enable control signals to that one flip flop in accordance with its usage at those different times.

Referring toFIG. 7C, the control signals that are used for a plurality of neighboring IOB's (which plurality is at least equal to 3 in one embodiment) may be derived from interconnect channels that extend perpendicular to the array edge on which the corresponding IOB's reside. In the example ofFIG. 7C, a plurality of 6 co-controlled IOB's reside on a left edge and are neighbored by an immediately above or upper HIC and by an immediately below or lower HIC. The 6 co-controlled IOB's are divided into two nonoverlapping subsets of 3 immediately adjacent IOB's. Each subset of 3 immediately adjacent IOB's has its own ‘common’ control signals which are shown above dashed line781and ‘individual’ controls which are shown below dashed line781. For each such subset of 3 immediately adjacent IOB's there is a first stage multiplexer (not shown) which selects whether the immediately upper or immediately lower channel will supply the control signals. The successive second stage multiplexer is illustrated as780in FIG.7C. This second stage multiplexer780determines which specific signals from the elected channel will be used.

The illustrated, ‘left side’, IOB control multiplexer780comprises a plurality of eleven multiplexer input lines designated as MILs #1-11. A partially-populating set of PIP's is distributed as shown over the crosspoints of MILs #1-11and illustrated lines of the elected HIC (upper or lower) for transferring a signal from a desired HIC line to the respective MIL line. Each AIL has 8 PIP's along it for the embodiment ofFIG. 7Cwhile each MIL also has 8 PIP's along it. This allows for symmetric loading of lines.

MIL #1for example, may be used to transfer to multiplexer748a control signal from AIL numbers15,39,42and52of the upper HIC when the upper HIC is elected or from AIL numbers17,41,44and49of the lower HIC when the lower HIC is elected. The other four PIP's of MIL #1are coupled to the four global clock lines, CLK0-CLK3of the FPGA array. Polarity-selecting multiplexer748is essentially the same as that shown inFIG. 7Aexcept that for embodiments that followFIG. 7C, clock line749′ connects directly to the clock inputs of each corresponding register750of the 3 IOB's in the controls-sharing group.

Similarly, for MIL #3, polarity-selecting multiplexer728is essentially the same as that shown inFIG. 7Aexcept that for embodiments that followFIG. 7C, clock line729′ connects directly to the clock inputs of each corresponding register720of the 3 IOB's in the controls-sharing group.

MIL #5can provide a local set or reset signal which is logically ORred in OR gate788with the FPGA array's global SET/RST signal. Output785′ of the OR gate connects directly to the common SET/RST lines705,705′ of each corresponding IOB in the controls-sharing group of IOB's. If a local set or reset signal is not being used, MIL #5should be programmably coupled to ground by the PIP crossing with the GND line.

MIL #6,7, and8may be used to define individual IOB control signals OUTPUT ENO, OUTPUT ENI, OUTPUT EN2respectively to the OUTPUT EN terminal of each of a first, second, third IOB of the control-sharing group. MILs #9,10,11may be used to define individual IOB control signals INPUT EN0, INPUT EN1, INPUT EN2respectively to the INPUT EN terminal of each of the first, second, and third IOB of the control-sharing group. Other means are of course possible for acquiring a subset of signals from the AIL's of each IOB and defining therefrom the control signals of the IOB. The connection between these aspects of the IOB's and the control signals that are used for controlling the embedded memory blocks of the same FPGA array will become apparent below.

Referring now toFIG. 8, a right memory channel (RMC) is broadly shown at816. The RMC816includes a special vertical interconnect channel (SVIC) as shown under the braces of860and a memory block as shown at870.

A horizontal interconnect channel (HIC) that belongs to the general interconnect of the FPGA array is shown passing through at850. Darkened squares such as at855are used to indicate general areas of possible interconnection (e.g., PIP connections) to various portions of the passing-through HIC. Memory I/O multiplexer area878(first dashed box) corresponds to area478of FIG.3. Memory control multiplexer area877(second dashed box) corresponds to area477of FIG.3. Memory control acquisition area871(third dashed box) corresponds to symbol471of FIG.3.

Memory block870contains a multi-ported SRAM array organized as 32-by-4 bits (for a total of 128 bits). One of the ports is of a read-only type as indicated at882. Another port is bidirectional and provides for both reading of nibble-wide data out of memory block870and for writing of nibble-wide data into memory block870as indicated at884. Output enable terminal883cooperates with the read/write data port884, as will be explained shortly. For sake of convenience, the read/write port884is also be referred to herein as the first port, or Port_1. The read-only data port882is referred to as the second port, or Port_2.

Two different address signals may be simultaneously applied to memory block870for respectively defining the target nibble (4 data bits) that are to pass through each of first and second data ports,884and882. As such, a 5-bit wide first address-receiving port874is provided in block870for receiving address signals for the read/write data port884(Port_1). A second 5-bit wide address-input port872is provided for receiving independent address signals for association with the read-only data port882(Port_2). Additionally, a 6-bit wide controls-input port873is provided in block870for receiving various control signals from the adjacent SVIC860as will be detailed shortly. The respective combination of 5, 6, and 5 (address, control, address) lines adds up to a total of 16 such lines.

SVIC860contains a diversified set of special-function interconnect lines. A first set of four longlines are dedicated to carrying the CLK0-CLK3clock signals of the FPGA array. This set of four clock lines is denoted as SCLK bus861.

Another set of sixteen longlines is illustrated at862and identified as special maximum length lines (SMaxL). Like the other longlines of integrated circuit100, the SMaxL lines862extend continuously and fully over a corresponding working dimension of the FPGA matrix. The SMaxL lines862are subdivided into respective groups of 5, 6 and 5 lines each as denoted by identifiers862a,862c and862b. Configurable interconnections of these respective components862a-c with crossing buses872-874are denoted by darkened squares such as at865. It is seen from the darkened square icons ofFIG. 8that either of the 5-bit wide longline components862a or862b can supply a 5-bit wide address signal to either one or both of address-input ports874and872. Similarly, the 6-bit wide vertical longline component862c may be used for supplying all six of the control signals supplied to 6-bit wide port873.

SVIC860further includes two sets of special, quad-length lines respectively denoted as S4×L0and S4×L1. These sets of quad-lines are respectively illustrated at864and866as being each sixteen lines wide. In each set of quad lines, the set is further subdivided into respective components of five, six and five lines (5/6/5) in the same manner that wires-group862was. Again, darkened squares are used to indicate the provision of configurable interconnections to the respective ports872,873and874of memory block870. Unlike the staggered organization of the general quad-length lines (4×L lines) shown inFIG. 2, in one embodiment of the FPGA device100the special, quad-length lines in the two sets, S4×L0(864) and S4×L1(866) are not staggered and are not joined one to the next by switch boxes. This non-staggered organization allows for simultaneous broadcast to a group of as many as 4 adjacent SRAM blocks (4×4×32 bits of memory) of five bits of address signals for each respective address port (874,872) and/or six bits of control signals for each respective control port (873). Omission of switch boxes in the two special quad-length sets, S4×L0(864) and S4×L1(866), helps to reduce capacitive loading and thereby helps to speed the transmission of address and/or control signals to ports872,873,874by way of S4×L0(864) and S4×L1(866).

Memory control acquisition area871(dashed box) is defined by the darkened square connections of SVIC860to ports872,873,874of block870. The memory control acquisition area871may be configured by the FPGA user such that the five bits of the read-only address input port872may be acquired from the five-bit wide components of any one of line sets862,864and866. Similarly, the five-bit address signal of the read/write input port874may be acquired from any one of these vertical line subsets. The six control signals of input controls port873may be acquired partially from the SCLK bus861and/or fully from any one of the six-bit wide components of vertical line sets862,864and866.

FPGA-wide address or control signals that are common to a given embedded memory column114/116may be broadcast as such over longlines such as that of SVIC components861and862. More localized address or control signals that are common to a given section of an embedded memory column114/116may be broadcast as such over S4×L components864and866of the SVIC.

HIC850crosses with SVIC860in the region of memory control multiplexer area877. As seen inFIG. 8, HIC850also has a set of subcomponents. More specifically, there are sixteen longlines denoted at859as the MaxL set. There are four octal-length lines denoted at858as the 8×L set. There are four quad-length lines denoted at854as the 4×L set. There are eight double-length lines denoted at852as the 2×L set. Furthermore, there are sixteen direct-connect lines denoted at851as the DCL set. Moreover, there are eight feedback lines denoted at857as the FBL set. Nibble-wide data transmission is facilitated by the presentation of each of these diversified interconnect resources (851,852,854,857-859) as a number of wires, where the number is an integer multiple of 4.

Within the dashed box ofFIG. 8that is designated as memory I/O multiplexer area878, darkened sources are provided to show the general interconnections that may be formed (in accordance with one embodiment) between HIC850and the buses extending from ports882,883and884of the memory block870. As seen, in this embodiment, the read/write data port884(Port_1) is restricted to configurable connections only with the MaxL set859. This restriction allows for run-time switching between read and write modes. It should be recalled fromFIGS. 7A-7Bthat the longlines of the MaxL set859can be driven by tristate drivers of the adjacent SVGB's and/or IOB's. As will be seen inFIG. 9, the read/write data port884(Port_1) also has tristate drive capability. Data can thus be output onto the tristateable MaxL set859by a given bus master (SVGB or IOB) that wants to write data into the read/write data port884(Port_1) or output onto the tristateable MaxL set859by Port_1itself when Port_1(884) is in a read mode.

The read-only data port882(Port_2) can output data signals, in accordance with the illustrated interconnect possibilities, to any one or more of the MaxL set859, the 8×L set858, the 4×L set854and the 2×L set852.

Output enable signals may be acquired by port883in accordance with the illustrated interconnect possibilities, from one of sets859,858,854and852.

It is within the contemplation of the invention to have other patterns of interconnect coupling possibilities in multiplexer area878. However, for one embodiment of SRAM block870, the particular intercoupling possibilities shown in878is preferred for the following reasons. The read-only data port882(Port_2) tends to output read data at a faster rate than does the read/write data port884(Port_1). As such, it is particularly useful to be able to output this more-quickly accessed data (from Port_2) by way of the shorter-length (and thus faster) 2×L lines852. A user-configurable multiplexer coupling is therefore provided from the read-only data port882to the 2×L lines set852. Additional user-configurable multiplexer couplings are further provided to line sets854,858and859.

The writing of data into port884or the reading of data from port884tends to be a relatively slower process as compared to the reading of data from port882. At the same time, it is desirable to be able to source data into port884from any column of the FPGA device100(FIG. 1) and/or from any column of IOB's (1-24,49-72). User-configurable multiplexer connections855are therefore provided for bi-directional and tristateable transfer of data between the read/write data port884and the MaxL lines set859. However, it is not desirable to have further user-configurable interconnections between read/write data port884and the other, not-tristateable line sets858,854,852,851and857of HIC850. Converting the other line sets858,854,852,851and857of HIC850into tristateable lines would consume additional space in the integrated circuit100because the 2/4/8×L outputs (FIG. 4) of the CBB's would have to be converted into tristate drivers for this one purpose without providing substantial improvement in speed and performance. As such, in a preferred embodiment, the read/write data port884(Port_1) is couplable only to the adjacent MaxL lines set859.

It will be seen later (in the embodiment of FIG.9), that the OE port883may be used to time the outputting of time-multiplexed data from port884. The output data may be pre-stored in a Port_1read-register (not shown in FIG.8). As such, high-speed coupling of control signals to port883may be desirable even if the Port_1data portion884couples only to longlines859. Data may be time-multiplexed onto longlines859at relatively high switching speed by using the high-speed enabling function of the OE port883. Accordingly, as seen inFIG. 8, user-configurable multiplexer options are provided for coupling control signals to OE port883from the shorter (faster) line sets852,854and858as well as from longer line set859.

FIG. 9shows a next level of details within an SRAM block such as870of FIG.8. The internal structure of such an SRAM block is generally designated as900and includes a shared SRAM array901. Repeated, dual-port memory cells are provided within array901. Each such dual-port memory cell is referenced as902.

In one embodiment of FPGA device100(FIG.1), there are 128 dual-ported memory cells902within SRAM array901. The data of these cells902may be simultaneously accessed by way of respective, bidirectional couplings903and904. Couplings903and904carry both address and data signals for the correspondingly accessed cells.

A first configuration memory bit905of the FPGA device100is dedicated to a respective SRAM block900for allowing users to disable transition-sensitive inputs of block900in cases where block900is not being used. A logic ‘0’ is stored in configuration memory bit905when block900is not used. A logic ‘1’ signal in configuration memory bit905becomes an active RAM enabling signal906(RAMEN) that permits block900to be used.

A first port control unit910(Port_1Unit) is provided for controlling operations of the read/write data port884and its corresponding address input port874.

The supplied five-bit address signal874for Port_1may be stored within a first address-holding register911of block900and/or it may be transmitted through bypass path912to a first data input of address multiplexer914. A second data input of multiplexer914receives the Q output of the first address-storing register911. Configuration memory bit915controls multiplexer914to select as the current address signal (A1in) of Port_1, either the signal present at the first input (912) or at the second input (Q) of address-selecting multiplexer914. The selected address signal918is then applied to the address input A1inof the Port_1unit910.

An address-strobing signal958may be applied to a clock input of address-storing register911for causing register911to latch onto the signal presented on line874. The address-strobing signal958is produced by passing a rising edge of an address-validating clock signal (ADRCLK) through control-input terminal933and through an address-strobe enabling AND gate908. The second input of AND gate908is connected to the RAMEN signal906so that the output of gate908is pulled low (to logic ‘0’) when RAMEN is at logic ‘0’.

In addition to address-input port918, the Port_1unit910has a D1outport (971) from which data may be read out and a D1inport (977) into which data may be written Port_1unit910further includes a write-enable terminal978(WE1) onto which a logic ‘1’ signal must be placed in order to move write data from the D1inport977into SRAM array901by way of coupling903. Unit910further has a read-enable terminal979(RE1) onto which a logic ‘1’ signal must be placed in order to move read data from array901to the D1outport971by way of coupling903.

The D1outport971is 4-bits wide and is coupled to the D input port of a 4-bit wide, read-register972. The Q output of register972couples to one selectable input of a synch controlling multiplexer973. The D1outport971additionally couples to a second 4-bit wide selectable input of multiplexer973. An RS/A control signal (Read Synch or Asynch control) is applied to the selection control terminal of the synch controlling multiplexer973for selecting one of its inputs as a signal to be output to tri-state output driver974. The RS/A signal comes from a control output953of an R/W control unit950. Another output terminal952of the R/W control unit produces the WE1signal which couples to terminal978. Yet another output terminal951produces the RE1signal which couples to terminal979.

The output enabling terminal of tri-state driver974is coupled to output943of a Port_1read-enabling AND gate941. AND gate941includes three input terminals respectively coupled to receive the RAMEN signal906, the OE signal from line883, and an R/WEN signal as provided on line934.

Line934(R/WEN) is one of the six lines that form control port873(FIG.8). The other five lines are respectively931for receiving an RWCLK (read/write clock) signal,932for receiving the already-mentioned ADRCLK signal,935for receiving an RMODE signal, and936for receiving an ROEN (read-only enable) signal.

The RWCLK (read/write clock) signal on line931passes through AND gate907when RAMEN is true to provide access-enabling strobes on line917for Port_1. Line917couples to a rising-edge sensitive, clock input of the read register972of Port_1. Register972acquires the D1outsignal at its D input for storage upon the rising edge of each pulse presented on line917.

The Port_1access-enabling line917also connects to a rising-edge sensitive, clock input of a write-data storing register976. Register976receives four bits of write-data at its D input port from write buffer (high input impedance amplifier)975. The input of buffer975connects to the 4-bit wide read/write data port884. The output (Q) of register976couples to the 4-bit wide D1ininput of the Port_1unit910.

It is seen, therefore, that acquisition of memory write data through port884occurs in synchronism with the RWCLK signal931. For writing to occur, an active write-enable signal WEN must further be applied to terminal954of the read/write control unit950. WEN954is the binary inverse of the R/WEN signal on control line934. The combination of R/WEN control line934and OE control line883is provided so that the read/write port (Port_1) may have at least three separate states, namely, high-impedance output (Hi-Z), active bistable output (reading), and data inputting (writing).

In an alternate embodiment, the dashed, alternate connection and dashed line cut indicated by947is made and the responsiveness of registers911and972is modified such that one of these registers (e.g.,911) latches on the rising edge of passed-through RWCLK pulses and the other of these registers (e.g.,972) latches on the opposed falling edge of passed-through RWCLK pulses. The pulse width of the passed-through RWCLK pulses (917) would be adjusted in such an alternate embodiment to be at least equal to or greater than the address-strobe to read-valid latency of Port_1. Register976may latch on either edge of the passed-through RWCLK pulses (917). If write-register976is made to latch on the pulse edge opposite to that of read-register972, write and read-back operations may be carried out in close time proximity to one another.

In yet another alternate embodiment, the dashed, alternate connection and dashed line cut indicated by948is made and the responsiveness of register921is modified such that register921latches on a predetermined one of the rising and falling edges of passed-through ROCLK pulses (927). If both of modifications947and948are made, then the ADRCLK control signal933and its associated hardware (e.g.,908ofFIG. 9) may be eliminated to thereby provide a more compact device.

In yet another alternate embodiment, line933, gate907and line958are replicated so as to define two separate, RAMEN-enabled, address-validating strobes where one is dedicated to the address-storing register911and the other is dedicated to the address-storing register921. Such an alternative embodiment is represented in next-described,FIG. 10by a dashed line denoted as carrying an ADRCLK2 signal.

FIG. 10provides a view of a combined, monolithic system1000in accordance with the invention which shows both a multi-ported SRAM array1010and logic circuitry, generally designated as1020for supplying address signals to SRAM array1010.

More specifically, SRAM array1010includes a respective first access port (PORT#1) and a second access port (PORT#2) having respective address inputs1013and1014. PORT#1address signals may be received at the first address input1013either from a respective PORT#1address-capturing register1011or by way of a programmably-activatable register-bypass path1017. PORT#2address signals may be received at the second address input1014either from a respective PORT#2address-capturing register1012or by way of a programmably-activatable register-bypass path1018.

In one embodiment, clock line1015supplies address-strobing signal ADRCLK1to the clock inputs of both of registers1011and1012. In an alternate embodiment, clock line1015supplies the address-strobing signal ADRCLK1only to the clock input of first register1011while a separate clock line1016supplies an independent address-strobing signal ADRCLK2to the clock input of second register1012. In the latter embodiment, break1016a is made. The former embodiment where break1016a is not made and clock line1015services both of registers1011and1012is preferred for cases where it is desirable to minimize consumption of interconnect resources.

Tilted-ellipse symbol1065represents a user-programmable, selective coupling of line1015to one of the vertical lines of special vertical interconnect channel (SVIC)1060. In one embodiment, SVIC1060corresponds to860ofFIG. 8 and 1065corresponds to a controls-acquisition coupling made by bus873to SVIC860. If line1016is used, then dashed symbol1066similarly represents a user-programmable, selective coupling of line1016to one of the vertical lines of SVIC1060. If line1016is not present and used, the internal PIP elements (not shown) of symbol1066are similarly not present and used.

SVIC1060can supply the ADRCLK1address-strobing signal to selection element1065from a plurality of source points located along SVIC1060. Tilted-ellipse symbol1067is representative of such user-identified and user-programmable, source points. In one embodiment, element1067corresponds to a controls-transfer coupling such as would be made inFIG. 8within the Mem Ct1Mux Control Area877, wherein control signals are selectively transferred from a given HIC850to SVIC860. Line1057is representative of a HIC line that transmits a respective ADRCLK0signal to control-transfer coupling1067. When picked up at control-acquisition coupling1065and transferred onto line1015, the signal is renamed as ADRCLK1. When picked up at yet another control-acquisition coupling1063and transferred onto a corresponding HIC line of a general routing path identified as (H/V)IC1001, the signal is renamed as ADRCLK3. The ADRCLK3control-acquisition coupling1062can overlap with the ADRCLK0control-transfer coupling1067or it can be located elsewhere along SVIC1060. FPGA configuration by the user can create either scenario. In one variation, line1057is a global clock line (CLK0-CLK3) that extends throughout the FPGA array for selective acquisition by generally all CBB's and IOB's and which further extend into each SVIC1060(see861ofFIG. 8) for selective acquisition by generally all SRAM blocks of that SVIC. Under this one variation, line1057effectively merges with lines1015and1001while control-transfer coupling1067effectively merges with1065and1063.

The ADRCLK0signal on HIC line1057originates from one or more ADRCLK sourcing circuits1055. These ADRCLK sourcing circuits1055can be in the form of VGB's or IOB's and can link to HIC line1057either directly or by way of VGB-implemented, dynamic multiplexers (whose creation is described in at least one of the above-cited and incorporated, U.S. applications) and/or general interconnect. In the case where independent control-acquisition coupling1066is present with optional line1016, control-transfer coupling1067may be seen as providing the respective ADRCLK source signals from a bus designated as1057instead of a single line1057. In the same case, ADRCLK sourcing circuits1055would provide the one or more signals that eventually become ADRCLK1and ADRCLK2.

Referring to the time versus signal amplitude plot at1005inFIG. 10, one or both of the rising edge1006and falling edge1008of a register-strobing pulse may be used to latch onto data presented at the D input of the register so that the same can be stored in the register and maintained at the Q output of the register until a next register-strobing event. The register may alternatively operate in a ‘latch mode’ where the Q output of the register can change while the clock pulse is at the high level1007. The present disclosure contemplates the use of any combinations of these possibilities, including having registers that are either user-programmable or fixed to operate in one or more of the latch mode, the single-edge responsive mode (rising or falling) and the dual-edge responsive mode (where Q changes on each of rising and falling edges). For purpose of simplicity, each event that causes a register to store and maintain a given output state is referred to herein as a register-strobing event.

Accordingly, when one of ADRCLK sourcing circuits1055produces a register-strobing event, the event is presented in the ADRCLK0signal HIC line1057, transferred onto SVIC1060by way of control-transfer coupling1067, and then further transferred by way of control-acquisition coupling1065onto line1015for presentation to a clock input of the first address-capturing register1011as the ADRCLK1signal. In response, the first address-capturing register1011captures a respective ADR_SV1signal that is presented on line1019to its D input. The ADR_SV1signal is acquired from the SVIC1060by a respective control-acquisition coupling1064.

Reference numeral1062points to two control-transfer couplings from which the ADR_SV1signal may be derived. A first of these control-transfer couplings is situated for selectively acquiring (or not) an ADR—2×L signal from a HIC line identified as1051and transferring the ADR—2×L signal to a programmably-selectable one of lines in SVIC1060. HIC line1051corresponds in one embodiment to a horizontal line found in one of the respective 2×L, 4×L, 8×L buses852,854and858of FIG.8. The HIC of line1051does not need to be immediately adjacent to SRAM array1010. It can be any HIC that crosses operatively with SVIC1060.

A second of control-transfer couplings1062is situated for selectively acquiring (or not) an ADR_MaxL signal from a HIC line identified as1052and transferring the ADR_MaxL signal to a programmably-selectable one of lines in SVIC1060. HIC line1052corresponds in one embodiment to a horizontal line found in the MaxL bus859of FIG.8. The HIC of line1052does not need to be immediately adjacent to SRAM array1010or the same as that of line1051. It can be any HIC that crosses operatively with SVIC1060. For purpose of convenient illustration however, both of lines1051and1052are shown as residing in a single HIC that is identified as1050.

For a first example, it is assumed that the ADR_SV1signal (1019) is derived from the ADR—2×L signal (1051). In its turn, the ADR—2×L signal (1051) is obtained from a Q output of a register1022within a CSE of logic circuitry1020. The CSE register1022corresponds in one embodiment to667of FIG.6B. CSE register1022has a clock input1022a that is clocked by logic circuit portion1021, where the latter portion1021typically includes a VGB common controls section such as550ofFIG. 6A and apolarity-selecting multiplexer such as603of FIG.6B. Logic circuit portion1021is responsive to the ADRCLK3signal that is routed to it by (H/V)IC interconnect resources1001. Logic circuit portion1021may be further responsive to one or more other input signals represented by input path1021a such that the ADRCLK3signal is blocked from evoking a register-strobing event on line1022a until an enabling signal is supplied on input path1021a. The logic circuit portion1021may include variable grain, configurable logic corresponding to one or more of the CBB's510,520,530and540of FIG.6A. The input path1021a may correspond to parts664,604ofFIG. 6Bas well as common controls section550of FIG.6A.

CSE register1022maintains its old Q output state until logic circuit portion1021provides a new register-strobing event to clock input1022a. The Q output state of CSE register1022is passed by way of a CSEQ portion1023to CSE output line1024so as to define a current or OLD ADDR1signal. In one embodiment, CSEQ portion1023corresponds to multiplexers668,620and driver630of FIG.6B. PIP1025is representative of any user-programmable routing means that may be used to couple the signal of line1024onto HIC line1051. In one embodiment, PIP1025includes at least one of the programmable coupling elements632,633,634and638of FIG.6B.

CSED portion1026ofFIG. 10presents a next or NEW ADDR1signal (1027) to the D input of CSE register1022. In one embodiment, CSED portion1026corresponds to multiplexer640of FIG.6B. The NEW ADDR1signal1027may be generated by configurable logic that feeds into CSED portion1026and may correspond for example to one inputs675,635and638of FIG.6B. By way of example, such a NEW ADDR1feeding logic may comprise an address counter (not shown) that is implemented by a plurality of CBB's. In such a case, the carry-propagating logic section570ofFIG. 6Amay cooperate with its respective in-VGB Configurable Building Blocks510-540to produce each successive NEW ADDR1signal. The NEW ADDR1signal may be alternatively computed by other logic means such as for example that which utilizes the wide-gating logic section560of FIG.6A. As yet another alternative, the NEW ADDR1signal may be generated outside the FPGA array and may be brought into the FPGA array by way of one or more IOB's.

When logic circuit portion1021provides a new register-strobing event to clock input1022a, the CSE register1022captures the NEW ADDR1signal1027then presented to it and CSEQ1023forwards this newly stored signal1027onto CSE output line1024. The new address signal then flows through routing means1025, line1051, the upper of control-transfer couplings1062, the SVIC1060and control-acquisition coupling1064to define the ADR_SV1signal (1019) at the D input of first address-capturing register1011. When the ADR_SV1signal (1019) stabilizes into a valid state at the D input of1011, the ADRCLK1signal (1015) may present a strobing-event to first address-capturing register1011for causing register1011to capture the stabilized ADR_SV1signal (1019).

The flow of the ADRCLK1signal (1015) follows the path already described above, namely, from one of the ADRCLK sourcing circuits1055, to HIC line1057, to control-transfer coupling1067, through SVIC1060, then through control-acquisition coupling1065to line1015. The CSE register-strobing signal of line1022a may follow an overlapping and similar path at the same time. More specifically, the address-strobing signal that travels on line1057for strobing first address-capturing register1011may also continue from control-transfer coupling1067, and through SVIC1060to exit from control-transfer coupling1063onto the (H/V)IC interconnect resources as the ADRCLK3signal. If or when further enabled by enabling signal1021a (if such further enabling is needed), the so-produced ADRCLK3signal can invoke logic circuit portion1021to strobe CSE register1022and thereby create a new (next) address signal on CSE output line1024. The enabling signal1021a, if used may be used to indicate when the NEW ADDR1signal1027is valid.

The signal propagation delay from the ADRCLK0line1057to the ADRCLK1line1015should be at least approximately equal to and more preferably shorter than the signal propagation delay from the same ADRCLKO line1057to the clock input1022a of CSE register1022. This helps to assure that the first address-capturing register1011has safely captured and stored the old address signal previously presented on CSE output line1024before the new state change of CSE register1022propagates to the D input1019of the first address-capturing register and presents itself as a new ADR_SV1signal.

Given that the first address-capturing register1011can safely capture and maintain the OLD ADDR1value for subsequent processing by SRPM array1010, the memory cell addressing operations and the responsive data fetching operations of SRAM array1010can overlap in time with the production by logic circuitry1020of a next or NEW ADDR1signal (1027) and the forwarding of this NEW ADDR1signal to the D input1019of the first address-capturing register1011. System response time may be advantageously minimized by such temporal overlapping of operations. Moreover, the interconnect resources of the SVIC1060may be advantageously used to serve the double-duty of transferring a register-strobing event (ADRCLK0) simultaneously to the clock input1015of the first address-capturing register1011and to the clock input1022a of the CSE register1022. Such double-duty use of interconnect resources within the FPGA array helps to improve resource utilization efficiency and frees other parts of the finite interconnect resources within the FPGA array for other uses.

There is more than one way to transfer a new address signal into the first address-capturing register1011. For purposes of a second example, it is assumed that the ADR_SV1signal (1019) is instead derived from the ADRrMaxL signal (1052). The signal flow for this second example is from MaxL line1052, through the lower of the control-transfer couplings1062, then through control-acquisition coupling1064onto line1019.

For its part, the ADR_MaxL signal (1052) is obtained from a tristate output of a line-mastering one of plural tristate drivers such as1031and1032. MaxL tristate driver1031has an input terminal1033, an output terminal coupled to HIC line1052, and output enabling terminal1035for switching the state of the driver's output terminal between a high-impedance (Hi-z) state and an active state. Similarly, MaxL tristate driver1032has an input terminal1034, an output terminal coupled to HIC line1052, and output enabling (OE) terminal1036for switching the state of the driver's output terminal between a Hi-z state and an active state. The input and OE terminals,1033and1035of first MaxL driver1031are driven by a ‘shared’, tristate-drivers controlling block (3S_CTL)1037. In one embodiment, the3S_CTL block1037corresponds to shared block580of FIG.6A. Controlling block1037can however take other forms such as ones where it is not shared by plural VGB's and/or plural CBB's.

A to-tristate signal1041may be fed from CSEQ1023to the3S_CTL block1037for presentation onto input terminal1033of first MaxL driver1031. The to-tristate signal1041may be one that is also stored in CSE register1022or not. In one embodiment, the line of signal1041corresponds to line548of FIGS.6A and/or6B. If OE terminal1035is set for the active output mode, the signal presented on input terminal1033will be output to MaxL line1052. If OE terminal1035is instead reset for effecting Hi-z output mode, the signal presented on input terminal1033will not be output to MaxL line1052and another MaxL driver (e.g.,1032) may instead drive line1052. The state of OE terminal1035may be controlled by dynamically-variable signal1045. In one embodiment, the line of signal1045corresponds to line558(DYOE) of FIG.6A.

The input and OE terminals,1034and1036of second MaxL driver1032are driven by a respective second ‘shared’, tristate-drivers controlling block (3S_CTL)1038. In one embodiment, the second3S_CTL block1038corresponds to shared block580(FIG. 6A) of an SVGB other than the SVGB that contains the first3S_CTL block1037. Second controlling block1038can however take other forms such as ones where it is not shared by plural VGB's and/or plural CBB's.

A second to-tristate signal1042may be fed from an appropriate source (e.g., a counterpart of CSEQ1023) to the second3S_CTL block1038for presentation onto input terminal1034of second MaxL driver1032. The second to-tristate signal1042may be one that is also stored in a CSE register or not. If OE terminal1036is set for the active output mode, the signal (NEW_ADDR_M2) presented on input terminal1034will be output to MaxL line1052. If OE terminal1036is instead reset for effecting Hi-z output mode, the signal presented on input terminal1034will not be output to MaxL line1052and another MaxL driver (e.g.,1031) may instead drive line1052. The state of OE terminal1036may be controlled by dynamically-variable signal1046. In one embodiment, the line of signal1046corresponds to a DyOE line (558) of an SVGB other than the SVGB that contains the first3S_CTL block1037.

Configurable logic block1040may be used to coordinate the switching of mastery over MaxL line1052as between tristate drivers1031,1032and others if applicable. A change-over to a new address bit on MaxL line1052may be carried out by switching the mastery over MaxL line1052between tristate drivers such as1031and1032. The full address word that is presented to first address input1013will of course be defined on a plurality of parallel lines, which lines can be comprised of one or both of MaxL lines and 2×L, 4×L, and/or 8×L lines.FIG. 5for example illustrates how a nibble's-worth of data may be transferred from any side of block580to adjacent MaxL lines. As such, the change-over to a new address that is discussed here for tristate drivers1031and1032may apply in parallel to a bus wide group of such tristate drivers. Alternatively, if the bit on line1052represents a significant address bit, the changeover of such a single bit can have uses.

The ADRCLK3signal may be used to coordinate switchover of mastery over MaxL line1052as follows. Instead of, or in addition to being routed to logic circuit portion1021, the ADRCLK3signal may be routed via (H/V)IC resources1001to terminal1043of configurable logic block1040. Block1040(which block can be a CBB, or VGB or other variable grain component) will respond by cycling the mastery over MaxL line1052through tristate drivers1031,1032and others if applicable. The changed state on line1052then propagates to define the ADR_SV1signal (1019) as explained above. In other words, the signal on terminal1043may be used as an address-changing control signal that deactivates the output enabling terminal1035of tristate driver1031and thereby allows another tristate drive (e.g.,1032or that of an IOB) to take over mastery of line1052.

Alternatively, while first MaxL driver1031has mastery over MaxL line1052, changes in the to-tristate signal1041may be propagated through elements1037,1031and line1052to thereby define the ADR_SV1signal (1019) as explained above. The change of state of the to-tristate signal1041may be made to occur in response to a change of state of the ADRCLK3signal. In view of the above, it is seen that a variety of mechanisms can be made to respond to the ADRCLK0and/or the ADRCLK3signals or derivations thereof such that the first address-capturing register1011safely captures a first address value for presentation to first address input1013while at approximately the same time or shortly thereafter, a new second address value can begin to propagate towards the D input (1019) of the first address-capturing register.

The above descriptions for how a first address value is safely captured in address-capturing register1011while at approximately the same time or shortly thereafter, a new second address value can begin to propagate towards the D input of that address-capturing register can equally apply to the second or PORT#2address-capturing register1012with the exception that the signal presented to the D input of the latter register1012is denoted in the illustration as ADR_SV2and its control-acquisition coupling is denoted as106C. In the embodiment wherein line1015services the clock inputs of both of registers1011and1012, both address-capturing operations will of course occur in response to the ADRCLK1signal. In the embodiment wherein line1015services the clock input of register1011while separate line1016and control-acquisition coupling1066services the clock input of register1012, each respective address-capturing operation will of course occur in response to the respective ADRCLK1or ADRCLK2signal. Separate sources1055may then be used respectively for each of the ADRCLK1and ADRCLK2signals and separate versions of the ADRCLK3and its associated circuits may also then be used respectively for each of the first and second address-capturing registers,1011and1012.

On the data transfer side of SRAM array1010, data-capturing registers such as the illustrated10R1,10R2and10R3may be similarly used to synchronize the transfer of data from and/or to the SRAM array1010during respective read and write operations.

More specifically, during write operations to Port#1, data may pass through respective ones of user-programmable interconnect points1075to write buffer10B1from either horizontal MaxL lines such as the one designated as10A2inFIG. 10, and/or from further lines that are horizontal 2×L, 4×L, and/or 8×L lines and are represented by the one designated as10A1in FIG.10. Actuation of read/write clock signal, RWCLK1causes data-capturing register10R1to capture and store the data then presented to its D input. The captured data is then presented by the Q output of register10R1to the Dindata-input section of Port#1for writing into a correspondingly addressed part of the SRAM array1010.

With the write data safely captured in data-capturing register10R1, the logic circuitry1070which supplies the write data may begin to generate next write data even while SRAM array1010is busy receiving the data stored in data-capturing register10R1. It should be apparent fromFIG. 10that the various parts of logic circuitry1070are referenced with numbers that are 50 greater than counterpart elements of circuitry1020and therefore a detailed repetition of their operations will not be repeated here. Configurable logic1071may be made responsive to the signal designated as RWCLK3and which is transmitted by the configurable interconnect resources designated as (H/V)IC1002. The RWCLK3signal may originate as a RWCLK0signal that is placed on HIC line1058and is sourced by one or more of RWCLK sourcing circuits1054. Control-transfer coupling1068selectively transfers the RWCLK0signal onto a line of SVIC1060. Control-acquisition coupling1061selectively transfers the there-received version of the RWCLK0signal to the clock input of data-capturing register10R1. The there-received version is referenced as the RWCLK1signal. Control-transfer coupling106A selectively transfers the there-received version of the RWCLK0signal to (H/V)IC resources1002. The latter there-received version is referenced as the RWCLK3signal. Due to inherent time delays, CSE register1072will not cause a new write-data signal to be output onto CSE output line1074until the previous write data signal is safely captured in data-capturing register10R1. Similarly, configurable logic block1090will not cause a switching of mastery over Max line10A2, if that mechanism is being used, until the previous write data signal is safely captured in data-capturing register10R1.

Synchronization for the transfer of read data from SRAM array1010to other parts of the FPGA array may follow a similar scheme. The RE1section of SRAM array1010corresponds to line979of FIG.9. The RE2section of SRAM array1010corresponds to line969of FIG.9. The RWCLK1signal strobes the read-data capturing register10R2first before a RWCLK3′ signal enables RE1to allow a next read operation by Port#1.

The RWCLK3′ signal can be either the same as the RWCLK3signal or a further delayed version thereof.

For the Port#2side, the corresponding The ROCLK1signal strobes the read-data capturing register10R3first before a ROCLK3′ signal enables RE2to allow a next read operation by Port#2. The ROCLK3′ signal can be either the same as the ROCLK3signal obtained by control-transfer coupling106B or a further delayed version thereof.

The respective tristate output drivers,10B2and10B3of Port#1and Port#2should not be enabled until after the respective RWCLK1and ROCLK1signal strobes the respective read-data capturing register,10R2and10R3, and the respective Q output of that register stabilizes into a valid state. As such, the respective RWCLK3″ and ROCLK3″ signals are accordingly timed to provide such a delayed action as they pass through optional logic sections10D1,10D2into respective OE control sections10E1,10E2. The respective RWCLK3″ and ROCLK3″ signals may the same as the RWCLK3and ROCLK3signals or may be other derivatives of the RWCLK0and ROCLK0signals that originate from circuits1054,1053and pass through control-transfer couplings1068and1069for distribution by SVIC1060to control-acquisition couplings such as106A and106B.

AlthoughFIG. 10shows various couplings for transferring address and data signals between CSE's (e.g.,1022,1072) and SRAM array1010, it should now be apparent that similar types of synchronizing arrangements may be made for transferring one or both of address and data signals between IOB's and the SRAM array1010. More specifically, inFIG. 7Bit was shown that clocked registers720and750are provided for sending data out of and into the FPGA array. InFIG. 7Cit will shown that the count signals for registers720and750may be acquired from adjacent interconnect lines and that the output of register750and input of register720may be programmably coupled to further interconnect lines of the FPGA array. Accordingly, IOB registers720and750may be used in the essentially the same ways as the CSE registers1022and1072inFIG. 10for synchronizing transfer of address and data between the SRAM array1010and the IOB's. Also, because the IOB's ofFIG. 7Bhave tristate drivers such as761and762, the latter tristate drivers may be used in the essentially the same ways as are drivers1031,1032, etc. inFIG. 10for synchronizing transfer of address and data between the SRAM array1010and the IOB's.

Referring inFIGS. 11A-11B, shown there are an FPGA configuring process and a flow chart of a software process for causing one or more of the operations ofFIG. 10to occur when a Variable Grain Architecture FPGA array of the invention is configured.

More specifically,FIG. 11Ais a schematic diagram of an FPGA configuring process1100wherein a predefined design definition1101is supplied to an FPGA compiling software module1102. Module1102processes the supplied information1101and produces an FPGA-configuring bitstream1103. Bitstream1103is supplied to an FPGA such as100or1000of respectiveFIGS. 1 and 11for accordingly configuring the FPGA.

The design definition1101may include a SRAM module1110, an address-source module1120and a data-I/O module1170.

Although it may appear from the drawing that modules1110,1120and1170are pre-ordained to respectively correspond to elements1010,1020and1070ofFIG. 10, that is not inherently true. The design definition1101may be expressed in a variety of ways which do not pre-ordain such an outcome. Modern circuit designs typically start with a Very High-level Descriptor Language (VHDL) or the like for defining the behavior of a to-be-implemented design at a level that is significantly higher than a gate-level or transistor level description. High level design definitions are often entered by designers into computer-implemented program that are commonly referred to by names such as VHDL synthesis tools. The output of the VHDL synthesis tools may be in the form of one or more computer files that constitute VHDL descriptions of the to-be-implemented design. VHDL description files may include one or more different kinds of constructs including VHDL Boolean constructs that define part or all of the design. The complexity of the Boolean functions can span a spectrum having very simple ones (e.g., those having 1-3 input terms) at one end to very complex ones at the other end. The high level definitions generally do not specify implementational details. That job, if an FPGA is to be used for implementation, is left to the FPGA compiler software module1102.

In the illustrated design definition1101, there is a specification for the address-source module1120to supply a valid address signal to an address input section (Ain) of the SRAM module1110at some general first time point t1. This presentation of a valid address is symbolically represented inFIG. 11Aby presentation step symbol1121.

Further in the illustrated design definition1101, there is a specification for the data I/O module1170to supply or receive a valid data signal respectively to or from a data input/output (Din/out) part of the SRAM module1110at some second general time point, t2. This presentation of valid data is symbolically represented inFIG. 11Aby data presentation step symbol1171. The second time point, t2can be before, after or coincident with the first time point, t1.FIG. 11Ashows t2following t1merely for sake of example.

Yet further in the illustrated design definition1101, there is a specification for a memory read or memory write operation to occur at some third general time point, t3based on the presentation of valid address and data signals in respective steps1121and1171. This execution of a memory read or memory write operation is symbolically represented inFIG. 11Aby execution step symbol1180.

It should be apparent from the way the elements in area1101were drawn that, ultimately, the address-source module1120will present address signals onto HIC bus1152and that these will then be transferred onto SVIC bus1160for presentation to the address input section (Ain) of the SRAM module1110at a first time point corresponding to t1. Also, when the design1101is ultimately implemented, the data I/O module1170will exchange data signals with the data input/output (Din/out) part of the SRAM module1110by way of HIC bus1150at time points corresponding to t2and t3. However the road to this ultimate goal is not embarked upon until the FPGA compiling software module1102inputs the design definition1101and processes it as will now be described.

FIG. 11Billustrates a flow chart1105of a process that attempts to realize the above-described efficiencies ofFIG. 10. Adesign definition such as1101is input at step1107into the FPGA compiler software module1102. Numerous processing steps may take place within software module1102.

Step1107is one of those steps in which the software module1102searches through the input design definition (e.g.,1101) for the presence of design components like1110,1120&1170that will perform memory read and/or write operations. The search criteria may optionally require the searched-for design components to operate in a nibble-wide or word-wide parallel mode so that they may share one synchronizing clock for plural address or data bits.

At step1108, if two or more design components like1110,1120&1170are found to satisfy the search criteria, the place-and-route definitions of those design components are repacked so as to urge those definitions toward ultimately ending up using an SRAM array like1010ofFIG. 10in combination with a controls-transferring bus like1060of FIG.10and in further combination with exchange synchronizing registers like1011,1012,10R1,10R2,10R3of FIG.10.

It is understood by those skilled in the art of FPGA configuration that many design factors may pull the design components like1110,1120&1170away from or into operative placement next to shared buses corresponding with HIC's1150and1152, where HIC1150is operatively adjacent to the data input/output (Din/out) part of the SRAM module1110. Some overriding design considerations may push them apart from such an optimal arrangement. The urging factor produced in step1108may therefore be just one of numerous place and route weighting factors that pull one way or another to position the placed components in such cooperative alignment.

Dashed path1190represents many other processes within the software module1102wherein the original design definition1101is transformed by steps such as design-partitioning, partition-placements and inter-placement routings to create a configuration file for the target FPGA100or1000. Step1109assumes that at least one set of design components like1110,1120&1170were found and were ultimately partitioned and placed together with minimal-time routing resources such as1150and1152so as to allow for the optimized use of a controls-transferring bus like1060ofFIG. 10in further combination with one or more exchange synchronizing registers like1011,1012,10R1,10R2,10R3of FIG.10. In that case, at step1109the target FPGA100(0) is configured to use a controls-transferring bus like1060ofFIG. 10in further combination with one or more exchange synchronizing registers like1011,1012,10R1,10R2,10R3ofFIG. 10for providing the specified address and data transfers that take place between design components like1110,1120&1170.

The above disclosure is to be taken as illustrative of the invention, not as limiting its scope or spirit. Numerous modifications and variations will become apparent to those skilled in the art after studying the above disclosure.

By way of example, instead of having only two columns of embedded memory respectively designated for the TOP longline set and the 3RD longline set, it is also within the contemplation of the invention to provide four columns of embedded memory respectively designated for the TOP through 3RD longline sets. Different numbers of columns of embedded memory may also be provided.

Given the above disclosure of general concepts, principles and specific embodiments, the scope of protection sought is to be defined by the claims appended hereto.