Apparatuses, systems, and methods for determining extremum numerical values

Embodiments of the disclosure are drawn to apparatuses and methods for determining extremum numerical values. Numerical values may be stored in files of a stack, with each bit of the numerical value stored in a content addressable memory (CAM) cell of the file. Each file may be associated with an accumulator circuit, which provides an accumulator signal. An extremum search operation may be performed where a sequence of comparison bits are compared in a bit-by-bit fashion to each bit of the numerical values. The accumulator circuits each provide an accumulator signal which indicates if the numerical value in the associated file is an extremum value or not. Examples of extremum search operations include finding a maximum of the numerical values and a minimum of the numerical values.

BACKGROUND

This disclosure relates generally to semiconductor devices, and more specifically to semiconductor components used for storing bits. Semiconductor logic devices may generally operate with a binary logic, where signals and information are stored as one or more bits, each of which may be at a high logical level or a low logical level. There may be a number of applications where it is useful to store a number of numerical values, encoded as binary numbers with each digit of the binary number stored as bit. For example, a memory device may store numerical values which are counts of the access operations to wordlines of a memory. In many applications it may further be desirable to determine a maximum (and or minimum) value of the store numerical values. For example, to identify which wordline(s) have been accessed the most.

DETAILED DESCRIPTION

Information in a semiconductor device may generally be represented by one or more binary bits, with each bit being at a high logical level (e.g., 1) or a low logical level (e.g., 0). Each bit may be stored in a memory cell such as a latch circuit. The memory cell may store a particular bit of information, which may later be retrieved and/or overwritten by a new bit of information to be stored. A group of memory cells may be organized together to form a file (or register), which stores information (e.g., data) including a number of bits. A number of files (e.g., a register) may be organized into a stack (e.g., a data storage unit), to store multiple pieces of information (e.g., each file may have N latch circuits to store information including N bits, and there may be M files in the stack). The number of files in a stack may generally be referred to as a depth of the stack. The number of latch circuits in a register may generally be referred to as a width of the stack.

A stack may include numerical values stored in the different registers. The numerical values may be represented as binary numbers, where each bit of the binary number is stored in a different memory cells. It may be desirable to search the stack to determine which of the stored numerical values has an extremum value, such as a maximum value and/or a minimum value. However, it may be a time consuming and/or power intensive process to read out all of the numerical values to a circuit which interprets the numerical value and searches for the maximum/minimum in the register stack. It may be desirable to search the stack for an extremum value by searching the numerical values on a bit-by-bit basis.

The present disclosure is drawn to apparatuses, systems, and methods for determining maximum and minimum numerical values stored in content addressable memory (CAM) cells. A stack may contain a number of files, each of which is made of a number of CAM cells. A numerical value (represented as a binary number) may be stored in one or more of the files, with each bit of the numerical value in one of the CAM cells of the file. Each CAM cell may have a latch portion to store a bit and a comparator portion which returns a match signal based on a comparison between the stored bit and an external bit. Each file may be coupled to an accumulator circuit which stores an accumulator signal. During an extremum search operation, a comparison bit may be compared to each bit in each of the files, the comparison bits may be provided starting with the most significant bit and working to the least significant. For example, a comparison bit may be compared to each of the most significant bits in each of the files, then the next most significant bit in each of the files etc. In some embodiments, the comparison bit may be compared to each of the most significant bits in all of the files simultaneously. The accumulator circuits may change the state of the accumulator signal based on the match signals from the files in the stack as the comparison bits are provided. An extremum numerical value (e.g., a maximum or minimum) stored in the stack may be identified based on the states of the accumulator signals.

FIG. 1is a block diagram of a stack according to an embodiment of the present disclosure. The stack100includes a number of files102, each of which includes a number of content addressable memory (CAM) cells104. The CAM cells104in file102are coupled in common to a signal line which carries a respective match signal Match based on a comparison of the stored bits Q in the CAM cells104to an external signal Compare. Each file102is coupled to an accumulator circuit106which stores and determines a state of an accumulator signal MaxMin. The stack100also includes a control logic circuit110which may provide signals to perform comparison operations as part of an extremum search operation to determine the file(s)102which contain extremum numerical values. Various actions may be performed based on the extremum search operation. For example, the control logic may provide a signal YMaxMin which indicates the index/indices of one or more of the files102which contain an extremum numerical value (e.g., the maximum or minimum value).

The stack100includes a number of files102, which may store data in one or more fields of the file102. Each field may include a number of CAM cells104, each of which stores a bit of the data in that field. For the sake of brevity and clarity, the files102ofFIG. 1are shown to include only a single field, which contains a numerical value. Other example embodiments may contain multiple fields per file102, some of which may numerical values (e.g., count values) and some of which may be non-numerical data (e.g., row addresses, flags). In general, the CAM cells104of each field are coupled in common to a different signal line which carries a match signal for that field. Since the example ofFIG. 1includes only a single field, only a single match signal line is shown and discussed.

The stack100may have a number of files102, which is generally referred to as a depth of the stack100. The example stack100ofFIG. 1includes n files102, which may generally be referenced by the index Y. Thus, a given file102may be referred to as File(Y), where Y is any value between 0 and n (inclusive). Each file102of the stack100may include a number of CAM cells104, which is generally referred to as a width of the stack100. The example stack100ofFIG. 1includes indifferent CAM cells104, which may generally be referenced by the index X. Thus, a given CAM cell104within a specified file102may be referred to as Cell(X), where X is any value between 0 and m (inclusive). Each CAM cell104may store a bit of information, which may generally be referred to as stored bit Q(X), where X is any value between 0 and m (inclusive). Accordingly, the stack100may have a total of n×m CAM cells104.

All of the CAM cells104in a given file102may be coupled in common to a signal line which provides a match signal Match. Since there are as many signals Match as there are files102, the match signals may generally be referred to as Match(Y), where Y is any number between 0 and n (inclusive). Each file102may receive external information, which may be compared to one or more specified bits Q stored in the CAM cells104of that file102. Each of the CAM cells104within a given File(Y)102may be capable of changing the state of the corresponding signal Match(Y) based on the comparison between the stored bit(s) Q and the provided external information.

In some embodiments, the CAM cells104may use dynamic logic to determine a state of the associated signal Match(Y). For example, all of the signals Match(Y) may be precharged to a first logical level which indicates a match between the stored bit Q and the provided external bit. The signals Match(Y) may be precharged by one or more driver circuits (not shown). In some embodiments, the accumulator circuit106coupled to the signal line Match(Y) may include the driver circuit and may pre-charge the signal line responsive to a control signal from the control logic110. If a CAM cell104determines there is not a match, it may change the state of the associated signal Match(Y) to a second logical level which indicates there is not a match. The operation of an example CAM cell104is described in more detail inFIG. 3.

Each of the signals Match(Y) is coupled to an accumulator circuit106. There may be a number of accumulator circuits, n, which matches a depth of the stack100. Each accumulator circuit106has an accumulator latch108which stores an accumulator signal MaxMin(Y). At the beginning of an extremum search operation, all of the accumulator signals MaxMin may be set to a first level (e.g., a high logic level). As the comparison signals Compare(X) are provided, the states of the accumulator signals MaxMin may change to a second level to indicate that the associated file102has been disqualified and does not include an extremum value. After the control logic circuit110performs an extremum search operation the states of the accumulator signals MaxMin(Y) indicate if the associated file102is an extremum value or not. The structure and operation of an example accumulator circuit is described in more detail inFIG. 4.

The control logic circuit110may perform an extremum search operation by performing a sequence of comparison operations. During one of these comparison operations, the control logic110may provide a comparison signal Compare(X). The signal Compare(X) may be signal provided to all of the CAM cells104with a particular index X, in all of the files102. The states of the match signals Match may be used to determine if the state of the stored bit Q(X) in any of the files102matches the state of the comparison signal Compare(X). For example, Compare(X) may be provided at a high logical level. Accordingly, the match signal Match(Y) may be at a high logical level if the bit Q(X) in the given File(Y) is at a high logical level, and may be at a low logical level otherwise. The state of the signal Compare(X) may determine the type of extremum search operation. If the signal Compare(X) is provided at a high logic level, the extremum search operation may be a maximum search operation. If the signal Compare(X) is provided at a low logic level, the extremum search operation may be a minimum search operation.

In some embodiments, during an extremum search operation, the control logic circuit110may perform comparison operations (e.g., provide Compare(X)) from a most significant bit Q(m) to a least significant bit Q(0) in the files102. The accumulator circuits106may be set up such that during an extremum search operation, the state of all of the accumulator signals MaxMin(Y) may start the extremum search operation at a first state, and change to a second state if Match(Y) indicates that there is not a match during the current comparison operation, unless all of the signals Match indicate that there is no match in the given comparison operation in which case the accumulator signal MaxMin(Y) may remain at the same state, regardless of the state of the associated match signal Match(Y).

The accumulator circuit106may be coupled in common to a signal AnyMatchF which indicates whether any of the match signals Match(Y) indicated a match after each of the comparison signals Compare(X) were provided. The signal AnyMatchF may indicate if there was a match for any of the accumulator circuits where the accumulator signal MaxMin(Y) is still at an initial state (e.g., a high logical level). Accumulator circuits106where the accumulator signal MaxMin(Y) has already changed to a second state (e.g., a low logical level) may not be used to determine the state of the signal AnyMatchF.

The signal AnyMatchF may be used by the accumulator circuits106to determine, in pan, whether to change the state of the accumulator signal MaxMin(Y) or not. In some example embodiments, the control logic circuit110may receive all of the match signals Match, and may provide the signal AnyMatchF based on the states of the signals Match(Y) and their associated accumulator signals MaxMin(Y). In some example embodiments, the accumulator circuits106may be coupled in common to a signal line carrying AnyMatchF, and each of the accumulator circuits106may change a state of the signal AnyMatchF on the signal line based on the state of the match signal Match(Y) coupled to that accumulator circuit106and the state of the accumulator signal MaxMin(Y) stored in that accumulator circuit106. During a given extremum search operation, once an accumulator signal MaxMin(Y) has changed to a second state, it may not change back to the first logical level until after the extremum search operation has finished. The process of performing an extremum search operation is described in more detail inFIG. 2.

In some embodiments, after all of the comparison operations as part of the extremum search operation, the control logic circuit110and/or the accumulator circuits106may resolve any ties. For example, if the extremum search operation is searching for a maximum numerical value, it may happen that more than one of the files102contains the same numerical value which is the maximum numerical value. The stack100may resolve the tie by, for example, keeping the accumulator signal MaxMin(Y) associated with the file102with the lowest index (e.g., the File(Y) for the lowest value of Y of the files102containing the tied maximum values) at a high level, and setting the accumulator signals MaxMin of the other accumulator circuits106to a low level.

In some embodiments, the accumulator circuits106may be coupled together in a ‘daisy-chain’ fashion such that a given Accumulato(Y) receives the accumulator signal MaxMin(Y−1) from a previous Accumulator(Y−1) and provides its accumulator signal MaxMin(Y) to a next Accumulator(Y+1). Additional control signals (not shown) may also be coupled between the accumulator circuits106in a ‘daisy-chain’ fashion. These daisy chained signals may allow the accumulator circuits106to resolve tics such that only a single one of the accumulator signals MaxMin(Y) remains at a high level after an extremum search operation.

In some embodiments, the control logic110may determine if no extremum value is found, and may provide one or more signals (not shown) which indicate that the extremum search operation did not return a value. For example, if all of the files102contain a numerical value which is 0. then the extremum search operation may not return a result. In some embodiments, the control logic110may still indicate a particular file (e.g., with the signal YMaxMin) in addition to (or instead of) the signal indicating that no extremum value was found.

As well as providing the comparison signals Compare(X) and the signal AnyMatchF, the control logic110may also provide other control signals, which are represented inFIG. 1as the signal Control. The control signals Control may be used to operate the accumulator circuits106during an extremum search operation. The control logic circuit110may be a state machine, which provides a sequence of different control signals to operate the accumulator circuits106. For example, one of the control signals may be used to indicate that an extremum search operation is about to begin and that the states of all of the accumulator signals MaxMin(Y) should be set to a first state. The control signals Control may generally be provided in common to the accumulator circuits106. Different example control signals and their operation are discussed in more detail inFIG. 4.

For the sake of clarity, the stack100ofFIG. 1is only shown coupled to a control logic circuit110and the signals used in an extremum search operation. The stack100may also be coupled to input data and to write signals, which may be used to overwrite one or more of the bits Q in the file102with associated bits of the input data. The stack100may also provide one or more of the stored bits Q from one or more of the files102. For example, a given file102may provide its stored numerical value (e.g., bits Q(0to m)) to a counter circuit, which may update the numerical value (e.g., increment it) and then provide a write signal such that the updated value is written back to the file102into the CAM cells104. In some embodiments, the state of the write signal, which determines if new data may be written to the file102may be determined, in part, by the accumulator circuit106based on the state of the accumulator signal MaxMin.

FIG. 2is a flow chart of a method of performing an extremum search operation according to an embodiment of the present disclosure. The method200may be implemented by the stack100ofFIG. 1. in sonic embodiments.

The method200may generally begin with block205, which describes setting accumulator signals to a first state. The accumulator signals (e.g., MaxMin(Y) ofFIG. 1) may be stored in accumulator latches in accumulator circuits (e.g., accumulator latches108in accumulator circuits106ofFIG. 1). In some embodiments all of the accumulator signals may be set to a first state. In some embodiments, the accumulator signal may be a one bit signal (e.g., an accumulator bit) and the first state may be a high logic level. In some embodiments, a control logic circuit (e.g.,110ofFIG. 1) may send an initialization signal. Responsive to receiving the initialization signal the accumulator circuits may store a high logical level in their accumulator latches as the accumulator signal. In some embodiments, block205may also include setting various other signals to an initial state. For example, the prior match signal (described in more detail inFIG. 4) may also be set to an initial inactive level.

Block205may generally be followed by block210, which describes providing a first comparison bit from a sequence of comparison bits. Each comparison bit (e.g., Compare(X) ofFIG. 1) may be provided to all of the bits in a given position in each of the files (e.g., files102ofFIG. 1) of a stack. For example, if the given comparison bit in the sequence is the Xth bit, then the comparison bit may be provided in common to the bits Q(X) in all of the files. In some embodiments, the sequence may begin with a most significant bit (e.g., Q(m)) and then count down bit-by-bit to a least significant bit (e.g., Q(0)). Accordingly at the block210, a first comparison bit may be provided to the bits Q(i) and then the next comparison bit may be provided to the bits Q(i−1) etc.

The state of the comparison bits may determine the type of extremum search operation that is being performed. For example, if the extremum search operation is searching for a maximum numerical value in the stack, then the comparison bits may be provided at a high logical level. If the extremum search operation is searching for a minimum numerical value in the stack, then the comparison bits may be provided at a low logical level.

Block210may generally be followed by block215, which describes pre-charging the match signals to a first state. The signal lines carrying the match signals (e.g., Match(Y) ofFIG. 1) may each be charged to a voltage level which represents a high logical level. The control logic may send a pre-charge signal to driver circuits (which may be located in the accumulator circuits). The pre-charge signal may activate the driver circuits, pre-charging the signal lines.

Block215may generally be followed by block220, which describes comparing the comparison bit to the corresponding stored bit in each file. As previously discussed, a comparison bit Compare(X) may be provided in common to all of the bits Q(X) with a given index X in all of the files. Each CAM cell storing the bits Q(X) may compare the state of the stored bit Q(X) to the comparison bit Compare(X). If there is a match (e.g., the bits have the same stale) then the match signal Match(Y) for that file may remain at a first state (e.g., a high logical level). If there is not a match, the CAM cell may change the state of the match signal Match(Y) to a second state (e.g., a low logical level).

Block220may generally be followed by block225, which describes determining if there w as a match for any of the files where the accumulator signal is at a high level. The determination may be made based on the status of the match signals after the comparison operation described in block220. There may be a signal (e.g., AnyMatchF ofFIG. 1) which indicates whether any of the match signals indicate a match or not in the files with accumulator signals at a high logical level. The files associated with accumulator signals at the low logical level may be disqualified from this determination. For example, each of the accumulator circuits may be coupled in common to a signal line carrying AnyMatchF, which is pre-charged to a first level as part of the block225. Any of the accumulator circuits may change a state of the signal line (and thus AnyMatchF) based on their associated match signal as long as the accumulator signal stored in that accumulator circuit is at a high logical level. If the accumulator signal is at a low level, then it may not affect the status of the signal AnyMatchF whether there is a match or not. The state of the signal line may thus indicate if there was at least one match or not in the files associated accumulator signals which are at a high logical level. If there is not at least one match (e.g., the signal AnyMatchF is high), then block225may generally be followed by block240, as described in more detail herein.

If there w as at least one match (e.g., the signal AnyMatchF is low), then block225may generally be followed by block230, which describes setting the prior match signal to an active level. The control logic may contain a prior match signal which has an active level which indicates that there was at least one match between a stored bit and a comparison bit at least once during the current extremum search operation. In some embodiments, the prior match signal may be a single bit signal (e.g., a flag) with the active level being a high logical level.

Block230may generally be followed by block235, which describes changing the states of accumulator signals based on the match between their associated stored bit and the comparison bit. The accumulator signal for each file may be changed based on if the bit Q(X) in that file matches the comparison bit Compare(X). If there is not a match, the accumulator signal may be changed from a first state to a second state. If there is a match, the accumulator signal may be kept at its current state. Note that once an accumulator signal is in a second state, it is generally not reset to the first state until a new extremum search operation is performed. In some embodiments, the state of the Match signal may be written to the accumulator latch to change the state of the accumulator signal, and logic (e.g., feedback) may be used to prevent the accumulator signal from going back to the first state if it is currently in the second state. Block235may generally be followed by block250. as described in more detail herein.

Returning to block225, if there is not a match between the comparison bit and the stored bit Q(X) in any of the files, then block225may generally be followed by block240, which describes keeping all accumulator signals at their current levels. When there is not a match in any of the files (e.g., as indicated by the state of the any match signal), all of the accumulator signals may be kept at their current state, even if there is not a match between the match signal Match(Y) and the associated accumulator signal MaxMin(Y).

Block240may generally be followed by block250. Block235may also generally be followed by block250. Block250describes determining if the final comparison bit from the sequence of comparison bits has been provided. For example, in block250it may be determined if the most recently provided comparison bit was the least significant bit Compare(0) or not. If the final comparison bit has been provided, then it may indicate that the method200is done with providing comparison bits, and block250may generally be followed by block270.

If the final comparison bit has not been provided, then block250may generally be followed by block255, which describes providing a next comparison bit in the sequence. For example, if the sequence is counting down from a most significant bit Q(m) to a least significant bit Q(0), and the previous comparison bit was Compare(X), then at block255. a comparison bit Compare(X−1) may be provided. Block255is generally followed by block215. The loop from blocks215to block255may generally continue until the method200is done providing comparison bits.

Once the method200is done providing comparison bits the method200may proceed to block270, which describes determining if the prior match signal is at an active level. If the prior march signal is not at an active level, it may indicate that there was not an operation where there was at least one match for the comparison bit in one of the files. For example, if all of the files contain a number which is 0 (e.g., and therefore ail of their bits are at a low level), and the extremum search operation is looking for a maximum, then no bit will ever match the comparison bit.

If the prior match signal is at an active level (e.g., there was at least one match), block270may generally be followed by optional block260or if optional block260is not performed, may be followed by block265. Block260describes resolving any ties if more than one accumulator signal is in the first state. Accumulator signals which are in the first state may indicate that the associated file contains an extremum value. In some applications it may be desirable to identify only a single file as containing an extremum value. Accordingly, if multiple accumulator signals arc at the first state, during block260the control logic circuit and/or accumulator circuits may select one of them and may change the other accumulator signals to the second state. In one example criteria for selecting a single accumulator signal (e.g., for breaking the tie) the file with the highest index (e.g., the File(Y) where Y is closest to the maximum value Y=m) may be chosen. Other criteria may be used in other examples.

Block260may generally be followed by block265, which describes determining the file with the extremum numerical value based on the state of the extremum signals. The control logic circuit may identify the file containing the extremum value based on which one (or more if block260was not performed) of the accumulator signals is in a first slate. In some embodiments, the control logic circuit may provide a signal (e.g., YMaxMin ofFIG. 1) which indicates an index of which file contains the extremum value. In some embodiments, various actions may be performed on the file containing the extremum value (or on the files not containing an extremum value). For example, after a minimum numerical value in the stack is found, the stack may receive new data and a write signal. Only the accumulator circuit where the accumulator signal is still high (e.g., the minimum value) may pass the write signal on to the CAM cells of the file, and thus only the minimum numerical value may be overwritten.

Returning to block270. if the prior match signal is not at an active level (e.g., there were no matches), then block270may generally be followed by block275which describes indicating that no extremum value was determined. For example, block275may involve determining that there is no extremum value because all of the count values are equal. In some embodiments, block275may involve providing a signal which indicates that the extremum search operation was unsuccessfully concluded (e.g., because all files store an equal count value). In some embodiments, a file may still be indicated as a placeholder, for example by following a procedure similar to the one described in block260.

FIG. 3is a schematic diagram of a CAM cell according to an embodiment of the present disclosure. The CAM cell300may, in some embodiments, implement the CAM cells104ofFIG. 1. The CAM cell300includes a latch portion312and a comparator portion314. The CAM cell300may generally use voltages to represent the values of various bits. The CAM cell300may include conductive elements (e.g., nodes, conductive lines) which carry a voltage representing a logical value of that bit. For example, a high logical level may be represented by a first voltage (e.g., a system voltage such as VPERI), while a low logical level may be represented by a second voltage (e.g., a ground voltage, such as VSS).

The latch portion of the CAM cell300may store signals Q and QF which represents the state of a stored bit (e.g., Q(X) ofFIG. 1). When the CAM cell300receives a bit of input data represented by signals D and DF, and a write signal Write, the value of the input data may overwrite the stored bit and become the new stored bit. The CAM cell300may receive an external bit (e.g., Compare(X) ofFIG. 1) represented by signals X_Compare and XF_Compare and may compare the external bit to the stored bit. Based on that comparison, the CAM cell may change a state of a match signal BitMatch (e.g., Match(Y) ofFIG. 1), which may be shared in common with one or more other CAM cells in the same field of a file.

The latch portion312includes a first transistor316which has a source coupled to a node which provides a voltage VPERI. which may represent a high logical level. The first transistor316has a drain coupled to a node327having a voltage which represents the value of the signal Q and a gate coupled to a node329having a voltage which represents a value of the complementary signal QF. The signal Q represents the logical level of a bit stored in the latch portion312. The first transistor316may be a p-type transistor. The latch portion312also includes a second transistor317which has a source coupled to the node which provides VPERI, a gate coupled to the node327and a drain coupled to the node329. The second transistor317may be a p-type transistor.

The latch portion312includes a third transistor318which has a drain coupled to the node327, a gate coupled to the node329, and a source coupled to a node providing a ground voltage VSS. which may represent a low logical level. The third transistor318may be an n-type transistor. The latch portion312includes a fourth transistor319which has a drain coupled to the node329, a gate coupled to the node327, and a source coupled to the node providing the ground voltage VSS. The fourth transistor319may be an n-type transistor. The transistors316and318may form an inverter circuit and the transistors317and319may form another inverter circuit, and the two inverter circuits are cross-coupled to one another.

In operation, the first, second, third, and fourth transistors316-319may work to store the value of the stored signals Q and QF. The transistors316-319may work together to couple the node327carrying Q and the node329carrying QF to a node providing the system voltage (e.g., VPERI or VSS) associated with the value of the signals Q and QF. For example, if the stored signal Q is at a high logical level, then the inverse signal QF is at a low logical level. The first transistor316may be active, and VPFRI may be coupled to the node327. The second transistor317and the third transistor318may be inactive. The fourth transistor319may be active and may couple VSS to the node329, This may keep the node327at a voltage of VPERI, which represents a high logical level, and the node329at a voltage of VSS, which represents a low logical level. In another example, if the stored signal Q is at a low logical level, then the inverse signal QF may be at a high logical level. The first transistor316and the fourth transistor319may both be inactive. The second transistor317may be active and may couple VPFRI to the node329. The third transistor318may also be active and may couple VSS to the node327. In this manner, the stored signal Q and QF may be coupled to a respective system voltage corresponding to their current logical levels, which may maintain the current logical value of the stored bit.

The latch portion312also includes a fifth transistor320and a sixth transistor321. The transistors320and321may act as switches which may couple a signal line which carries input data D and a signal line carrying inverse input data DF to the nodes327and329carrying Q and QF respectively when a write signal Write is active. Tire fifth transistor320has a gate coupled to a line carrying the Write signal, a drain coupled to the signal D, and a source coupled to the node329. Hie sixth transistor321has a gate coupled to the W rite signal, a drain coupled to the signal DF, and a source coupled to the node329. Accordingly, when the Write signal is at a high level (e.g., at a voltage such as VPERI), the transistors320and321may be active, and the voltages of the signals D and DF may be coupled to the nodes327and329carrying Q and QF respectively.

In some embodiments, the first through sixth transistors316-321may generally all be the same size as each other. For example, the transistors316-321may have a gate width of about 300 nm. Other sizes of transistor316-321may be used in other examples. The CAM cell300also includes a comparator portion314The comparator portion314may compare the signals Q and QF to the signals X_Compare and XF_Compare. The signal X_Compare may represent a logical level of an external bit provided to the comparator portion314. If there is not a match between the signals Q and X_Compare (and therefore between QF and XF_Compare), then the comparator portion314may change a state of from the BitMatch signal from a first logical level (e.g., a high logical level) to a second logical level (e.g., a low logical level). For example, if the stored and external bits do not match, the comparator portion314may couple the ground voltage VSS to a signal line carrying the signal BitMatch. In some embodiments, if there is a match between the stored and external bits, then the comparator portion314may do nothing. In some embodiments, the signal BitMatch may be precharged to a voltage associated with a high logical level (e.g., VPERI) before a comparison operation. During the precharge operation (e.g. block225ofFIG. 2), both X_Compare and XF_Compare may be held at a low logical level.

The comparator portion includes a seventh transistor322, an eighth transistors323, a ninth transistor324, and a tenth transistor325. The seventh transistor322and the ninth transistor324may implement the first portion101ofFIG. 1. The eighth transistor323and the tenth transistor325may implement the second portion103ofFIG. 1. The seventh transistor322includes a drain coupled to the signal BitMatch, a gate coupled to the node327(e.g., the signal Q), and a source coupled to a drain of the ninth transistor324. The ninth transistor324also has a gate coupled to the signal XF Compare and a source coupled to a signal line providing the ground voltage VSS.

The eighth transistor323has a drain coupled to the signal BitMatch, a gate coupled to the node329(e.g, the signal QF), and a source coupled to a drain of the tenth transistor325. The tenth transistor has a gate coupled to the signal X_Compare and a source coupled to the ground voltage VSS.

Since the signal Q is complementary to the signal QF, the comparator portion312may operate by comparing the external signal X_Compare to the signal QF to see if they match, and the inverse external signal XF Compare to the stored signal Q to see if they match. If they do match, it may indicate that the signal X_Compare does not match live signal Q and that the signal XF_Compare does not match the signal QF, and thus that the external bits do not match the associated stored bits.

The comparator portion314may use relatively few components, since it changes the signal BitMatch from a known state (e.g., a precharged high logical level) to a low logical level. Thus, it may not be necessary to include additional components (e.g., additional transistors) to change the logical level of the signal BitMatch from low to high, or from an unknown level to either low or high. The comparator portion314may take advantage of this to provide dynamic logic. For example, the comparator portion314has two portions (e.g., transistors322/324and transistors324/325) either of which may couple the signal BitLine to the voltage VSS if there is not a match between the stored and external bit. Since only one of the portions is active at a time, only the state of the signal Q or QF needs to be checked by the active portion. Either of the portions is equally capable of changing the signal BitMatch to a low logical level.

In an example operation, if the stored signal Q is at a high logical level (and thus the signal QF is low) and the external signal X_Compare is also high (and the signal XF_Compare is low), then the external signals may match the stored signals, and the transistors322and325may be active while the transistors324and323are inactive. This may prevent the ground voltage VSS from being coupled to the signal BitMatch. If the signal X_Compare is low (e.g., if there is not a match), then the external signals may not match the stored signals, and the transistors322and324may be active wile transistors323and325are inactive. The transistors322and324being active at the same time may couple the ground voltage VSS to the signal BitMatch.

In another example operation if the stored signal Q is low (and thus the signal QF is high) then the transistor322may be inactive while the transistor323is active. If the external signal X_Compare is low (and XF_Compare is high) then the external signal may match the stored bits, and the transistor324is active while transistor325is inactive. If the signal X_Compare is high (and the signal XF_Compare is low) then the external signal may not match the stored signal and the transistor324may be inactive while the transistor325is active. Accordingly, the signal BitMatch may be coupled to ground voltage VSS through active transistors323and325.

In some embodiments, the transistors322-325of the comparator portion314may generally all have the same size to each other. In some embodiments, the transistors322-325of the comparator portion314may be a different size than the transistors316-321of the latch portions312. For example, the transistors322-325may have a gate width of about 400 nm and a gate length of about 45 nm. Other sizes for the transistors322-325may be used in other examples.

FIG. 4is a schematic diagram of an accumulator circuit according to an embodiment of the present disclosure. The accumulator circuit400may implement the accumulator circuits106ofFIG. 1, in some embodiments. The accumulator circuit400includes a latch circuit408(e.g., accumulator latch108ofFIG. 1) which stores an accumulator signal MaxMinY which in the case of the example accumulator circuit400ofFIG. 4is an accumulator bit. The latch circuit408may provide a signal MaxMinY (e.g., accumulator signal MaxMin(Y) ofFIG. 1) based on rite stored accumulator bit. The accumulator circuit400may receive a variety of inputs and control signals which be used to determine the state of the accumulator signal stored in the latch circuit408during an extremum search operation.

The accumulator circuit400receives a control signal BitxCompPre from a control logic circuit (e.g., control logic circuit110ofFIG. 1) in common with all the other accumulator circuits. The signal BitxCompPre may be used as part of a pre-charge operation (e.g., block215ofFIG. 2) to pre-charge a node carrying a match signal BitxMatch_Y to a high voltage level before each comparison. The match signal BitxMatch_Y may implement the match signal Match(Y) ofFIG. 1and/or BitMatch ofFIG. 3in some embodiments. Accordingly, the control logic circuit may provide the signal BitxCompPre at a high logic level (e.g., a high voltage) each time a comparison operation is performed (e.g., each time a comparison bit is provided to the files of the stack). The signal BitxCompPre may be ‘pulsed’ by the control logic (e.g., briefly provided at a high level and then returned to a low level) in order to pre-charge the node carrying the match signal BitxMatch_Y.

It may also be desirable to prevent the node carrying the signal BitxMatch_Y from floating between operations. The control signal Standby may be used to indicate that a comparison operation is not currently being performed. The signal Standby may be provided in common to all of the accumulator circuits of the stack. Accordingly the control logic circuit may provide a pulse of the signal BitxCompPre when a comparison operation is about to be performed, and the signal Standby when a comparison operation is not being performed. During the comparison operation the state of the node carrying the signal BitxMatch_Y may be allowed to change (e.g., neither BitxCompPre or Standby is active).

A node carrying the signal Standby is coupled to the gate of a transistor433, which has a source coupled to a ground voltage (e.g., VSS) and a drain coupled to the node carrying the match signal BitxMatch_Y. The transistor433may be an n-type transistor. Accordingly, when the signal Standby is provided, the transistor433is active, and the node carrying the signal BitxMatch_Y is coupled to ground to prevent it from floating.

In one embodiment, not shown inFIG. 4. the signal BitxCompPre may be coupled through an inverter circuit to the gate of a transistor432. The source of the transistor432is coupled to a system voltage (e.g., VPERI) higher than the ground voltage VSS, and the drain of the transistor432is coupled to the node carrying the match signal BitxMatch_Y. The transistor432may be a p-type transistor. Accordingly, in this embodiment, when the signal BitxCompPre is provided at a high level, the transistor432may be active and may couple the node carrying BitxMatch_Y to the system voltage, pre-charging it.

In some embodiments, such as the one shown inFIG. 4. it may be desirable to allow only the file which contains the extremum to be pre-charged for a comparison operation. For example, after an extremum value is found, it may be useful to compare an external numerical value only to the file containing the extremum value. In order to achieve this functionality, the signal BitxCompPre is coupled to one of the input terminals of a NAND gate431. The other input terminal of the NAND gate431may be coupled to the output terminal of an OR gate430. which has an input terminal coupled to a control signal FindMaxMinOp and the accumulator signal MaxMinY, The control signal FindMaxMinOp may be provided in common to all of the accumulator circuits in the stack. The accumulator signal MaxMinY is the value stored in the latch circuit408of the particular accumulator circuit400. and thus the value of the accumulator signal MaxMinY may be different in different accumulator circuits.

When it is desirable to pre-charge all of the match signals BitxMatch_Y across the depth of the stack, the signal FindMaxMinOp may be pulsed at the same time that the signal BitxCompPre is pulsed. Accordingly, the OR gate430may provide a high logic output, and thus both the inputs of the NAND gate431may be at a high level, causing it to return a low logic level signal to activate the transistor432.

If it is desirable to only pre-charge the node carrying the match signal in the file(s) which have an extremum value, the signal FindMaxMinOp may be kept at a low level (e.g., not provided) when the signal BitxCompPre is pulsed. The state of the accumulator signal MaxMinY may determine if the accumulator circuit400for a particular file charges the signal line carrying the match signal BitxMatch_Y or not. If the accumulator signal MaxMinY is at a high level (e.g., indicating that the accumulator circuit is associated with a file containing an extremum numerical value) then the match signal BitxMatchY may be pre-charged when the signal BitxCompPre is pulsed. If the accumulator signal is at a low level (e.g., indicating that the accumulator circuit is not associated with an extremum value) then the match signal BitxMatch_Y is not pre-charged. In some embodiments, the signal FindMaxMinOp may be omitted, and since the signal MaxMinY is initially set to a high level, the signal MaxMinY may function (along with BitxCompPre) to activate the transistor432.

As discussed inFIGS. 1-3, after the signal line carrying the match signal BitxMatch_Y is pre-charged, a comparison operation may be performed where a comparison bit is provided and compared to one of the hits in the file coupled to the accumulator circuit400. After the comparison operation the node carrying the match signal BitxMatch_Y may have a voltage indicating the result of the comparison, either a high voltage (e.g., VPHRI) if the comparison bit matched the stored bit, or a low voltage (e.g, VSS) if there was not a match. The node carrying the match signal BitxMatch_Y is coupled to the input terminal D of the latch circuit408. The value of the match signal BitxMatch_Y may be saved as the value of the accumulator signal stored in the latch circuit408. when the latch terminals LAT and LATf of the latch circuit408are triggered.

The accumulator circuit400receives a control signal BitxMatchAccumSample in common with the other accumulator circuits. The control logic circuit may pulse the signal BitxMatchAccumSample after each of the comparison operations (e.g., a delay time after pulsing the signal BitxCompPre). The control signal BitxMatchAccumSample may determine, in part, if and when the latch circuit408captures the value of the match signal BitxMatch_Y and saves it as the value of the accumulator signal MaxMinY.

The signal BitxMatchAccumSample is coupled to an input terminal of a NAND gate436. The other input terminal of the NAND gate436is coupled to a node carrying the accumulator signal MaxMinY stored in the latch. When the signal BitxMatchAccumSample is pulsed, the current value of the match signal BitxMatch_Y may only be captured in the latch circuit408if the current value of the accumulator signal MaxMinY is still at a high level. If the accumulator signal MaxMinY has been changed to a low level (e.g., due to a previous comparison operation resulting in a non-match) then the latch circuit408will be prevented front capturing future values of the match signal BitxMatch_Y. The NAND gate436has an output terminal coupled to the latch input LAT of the latch circuit408and also coupled to the inverting latch input LATf through an inverter circuit437.

The latch circuit408has a set input Sf coupled to a control signal FindMaxMinOp_InitF. The signal FindMaxMinOp_InitF may be coupled in common to all of the accumulator circuits of the stack. The signal FindMaxMinOp_InitF may be used to set all of the latch circuits408in the different accumulator circuits to store a high level as the accumulator signal MaxMinY before an extremum search operation (e.g., as part of block205ofFIG. 2). The signal FindMaxMinOp_InitF may be pulsed from a high level to a low level, and then back to a high level. This may cause all of the latch circuits408to be set to store a high level before beginning the extremum search operation. Since all latch circuits408are initialized to storing a high level as the accumulator signal, all of the latch circuits408may initially be responsive to the signal BitxMatchAccumSample until the latch is disqualified by the match signal BitxMatch_Y being at a low level after a comparison operation.

All of the accumulator circuits may be coupled in common to a signal line carrying the signal AnyYbitMatchF, which may be the signal AnyMatchF ofFIG. 1in some embodiments. The signal AnyYbitMatchF may indicate if any of the match signals BitxMatch_Y were at a high logical level after the comparison operation. In some embodiments, the state of the signal AnyYbitMatchF may be determined using dynamic logic (e.g., similar to the match signal BitMatch ofFIG. 2). For example, after each comparison operation, the signal AnyYbitMatchF may be pre-changed to a high level (e.g., a system voltage such as VPER1) and each of the accumulator circuits400may be capable of changing the state of the signals AnyYbitMatchF to a low level if the match signal BitxMatch_Y of that file is at a high level (e.g., indicating a match) after the comparison operation.

The signal line carrying the signal AnyYbitMatchF may be coupled to a driver circuit (not shown) which may pre-charge the signal line before a comparison operation. The driver circuit may pre-charge the signal line responsive to a control signal CrossRegCompPreF provided by the control logic. The signal CrossRegCompPreF may be pulsed to a low level to pre-charge the signal line carrying AnyYbitMatchF. In some embodiments, the driver circuit may include a transistor with a gate coupled to CrossRegCompPreF, a source coupled to a system voltage such as VPERI, and a drain coupled to the signal line carrying AnyYbitMatchF. The transistor may be a p-type transistor such that when the signal CrossRegCompPreF is pulsed low, the transistor is active and couples the signal line to VPERI to pre-charge it.

Each of the accumulator circuits400has a transistor434with a source coupled to the signal line carrying AnyYbitMatchF and a drain coupled to the source of a transistor443. The drain of the transistor443is coupled to a source of a transistor435. The drain of the transistor435is coupled to a ground voltage (e.g., VSS). The transistors434,435, and443may be n-type transistors. The gate of the transistor434is coupled to a control signal CrossRegComp, which may be provided in common to all of the accumulator circuits. The signal CrossRegComp may be pulsed to a high level by the control logic to determine if any of the match signals BitxMatchY are at a high level after the comparison operations (e.g., as part of block225ofFIG. 2). The gate of the transistor443is coupled to the signal MaxMinY. The gate of the transistor435is coupled to the node carrying the match signal BitxMatch_Y. Accordingly, when the signal CrossRegComp is pulsed, the transistor434is activated. If the match signal BitxMatch_Y is high, the transistor435is activated. If the accumulator signal MaxMinY is at a high level, then the transistor443is active. If all of the transistors434,435, and443are activated, the signal line carrying AnyYbitMatchF is coupled to the ground voltage VSS. Accordingly, the state of the signal AnyYbitMatchF may only be changed if the accumulator signal MaxMinY is at a high level, the match signal BitxMatch_Y is at a high level, and the command signal CrossRegComp is provided.

For each comparison operation during an extremum search operation, the signal line AnyYbitMatchF may be pro-charged to a high level, and may be pulled to a low level if any of the match signals BitxMatch_Y is at a high level (e.g., indicating a match). The control logic circuit may use the state of the signal Any YbitMatchF to determine if the state(s) of the accumulator signals should be changed (e.g., as described in blocks225-245ofFIG. 2). For example, responsive to the signal AnyYbitMatchF being at a low level (e.g., indicating at least one match), the control logic may provide a pulse of the signal BitXMatchAccumSample. Responsive to the signal AnyYbitMatchF being at a high level (e.g., indicating no matches) the control logic may skip providing the signal BitXMatchAccumSample for the given comparison operation.

In some embodiments, the different accumulator circuits400may be connected together in a ‘daisy chain’ fashion. This may allow the accumulator circuits400and the control logic circuit to work together to resolve any ties so that only one accumulator latch408in one of the accumulator circuits400holds a high value. For example, the accumulator circuits400may receive in common a control signal ClrLessSigAccums which indicates that ties should be resolved. Each accumulator circuit400may also receive signals AccumYp1_Clr and MaxMinYp1from a previous accumulator circuit400. The signal MaxMinYp1may be the accumulator signal MaxMinY of the previous accumulator circuit. The signal AccumYp1_Clr may be a signal AccumsLessThanY_Clr (which will be described herein) from a previous accumulator circuit.

The accumulator circuit includes an OR gate438with an input terminal coupled to the signal AccumYp1_Clr and an input terminal coupled to the signal MaxMinYp1. The output terminal of the OR gate438is coupled to one of the input terminals of a NAND gate439. The other input terminal of NAND gate439is coupled to the control signal ClrLessSigAccums. A first accumulator circuit in the daisy chain may have the inputs AccumYp1_Clr and MaxMinYp1coupled to a ground voltage to initialize the signal. When the control signal ClrLessSigAccums is pulsed, if either AccumYp1_Clr or MaxMinYp1is at a high level, the inverting reset terminal Rf of the latch circuit408may receive a low signal (e.g., a ground voltage) from the NAND gate439and may reset the value stored in the latch circuit408(e.g., the signal MaxMinY to a low level). The output terminal of the NAND gate439is passed through an inverter circuit440to become the signal AccumsLessThanY_Clr which is provided to the next accumulator circuit in the daisy chain (e.g., to become the signal AccumYp1_Clr).

The direction the accumulator circuits400are coupled together may determine the criteria used to break the tie. For example, an accumulator circuit associated with File(Y) may receive the signals AccumYp1_Clr and MaxMinYp1from an accumulator circuit associated with File(Y+1) and so on. This may cause any tie to broken in favor of the accumulator circuit with the highest index. Note that in some embodiments, the accumulator circuits may be daisy chained in the opposite direction (e.g., File(0) may provide signals to File(1)) and it only changes the direction in which ties are broken (e.g., from lowest numbered register to highest numbered register).

In an example operation, after alt the comparison bits have been provided (e.g., at block260ofFIG. 2), there may be 3 accumulator circuits which are each storing a respective accumulator signal: MaxMin2is high; MaxMin1is low; MaxMin0is high. In this example the accumulator circuits are daisy chained from highest to lowest index. When the signal ClrLessSigAccums is pulsed, the first accumulator circuit may receive low logical inputs on both AccumYp1_Clr and MaxMinYp1(since that is how those signals are initialized). Accordingly the accumulator signal MaxMin2is not reset, and remains at a high value. The second accumulator receives the signals AccumYp1_Clr at a low logical level (since the previous accumulator circuit was not reset) and receives MaxMinYp1at a high level since MaxMinYp1=MaxMin2. Accordingly, the second accumulator circuit receives a reset signal (e.g., the output of the NAND gate439is at a low level) however the accumulator signal MaxMin1was already at a low level, and remains at a low level. The third accumulator circuit receives the signal AccumYp1_Clr at a high level (since the previous circuit did receive a reset signal even if it didn't change anything) and MaxMinYp1at a low level (e.g., since MaxMin1is low). Accordingly, the third accumulator circuit may reset (since at least one of AccumYp1_Clr and MaxMinYp1is high) and the third accumulator signal MaxMin0may change to a low level. Thus, after the signal ClrLessSigAccums is pulsed, MaxMin2is high, MaxMin1is low and MaxMin0is low.

In some embodiments, the accumulator circuit400may control whether data can be written to the associated file based on the state of the accumulator signal. Each of the accumulator circuits400may receive in common a signal CountWriteEn which may be coupled to the input terminal of a NAND gate441. The other input terminal of the NAND gate441may be coupled to the output terminal Q of the latch circuit408which provides the accumulator signal MaxMinY. The NAND gate441may provide a signal through an inverter circuit442which is CountWriteY. The signal CountWriteY may be a write signal (e.g., the signal Write ofFIG. 3) which indicates that the values in the register may be overwritten. Due to the NAND gate441and inverter442. when the signal CountWriteEn is provided, the signal CountWriteY may only be at a high level for accumulator circuits which are storing an accumulator signal that is at a high logical level (e.g., indicating an extremum value).

An example environment where it may be useful to store numerical values and identify extremum values are semiconductor memory devices. Memory devices may be used to store one or more bits of information in a memory cell array, which contains a plurality of memory cells each of which includes one or more bits of information. The memory cells may be organized at the intersection of rows (word lines) and columns (bit lines). During various operations, the memory1device may access one or more memory cells along specified word lines or bit lines by providing a row and/or column address which specifies the word line(s) and bit line(s).

An example application for the stacks, accumulator circuits, and control logic circuit of the present disclosure are refresh operations in a memory device. Information in the memory cells may decay over time, and may need to be periodically refreshed (e.g., by rewriting the original value of the information to the memory cell). Repeated access to a particular row of memory (e.g., an aggressor row) may cause an increased rate of decay in neighboring rows (e.g., victim rows) due. for example, to electromagnetic coupling between the rows. This may generally be referred to as ‘hammering’ the row, or a row hammer event. In order to prevent information from being lost due to row hammering, it may be necessary to identify aggressor row s so that the corresponding victim rows can be refreshed (a ‘row hammer refresh’ or RHR). The row addresses of accessed rows may be stored and may be compared to new row addresses to determine if one or more rows requires an RHR operation.

Access counts to different rows of the memory may be stored in a stack, such as the stack100described inFIG. 1. A row address may be stored in one field of each file, while a count value associated with that row address may be stored in another field of that file. Each time the row address is accessed, its count value may be updated (e.g., incremented). Based on the count value, victim rows associated with the stored row address may be refreshed. For example, a maximum count value may be selected by performing an extremum search operation (e.g., as described inFIG. 2) for a maximum value. The victim rows associated with the aggressor row associated with the maximum value may then be refreshed. In another example, in some situations, a row address in the stack may need to be replaced, and an extremum search operation to find a minimum value in the stack may be performed, and the row address associated with that minimum value may be overwritten. The functionality described inFIG. 4where a write signal is only supplied to the file associated with the extremum value may be useful in this example.

FIG. 5is a block diagram showing an overall configuration of a semiconductor device according to at least one embodiment of the disclosure. The semiconductor device500may be a semiconductor memory device, such as a DRAM device integrated on a single semiconductor chip.

The semiconductor device500includes a memory array568. The memory array568is shown as including a plurality of memory banks. In the embodiment ofFIG. 1, the memory array568is shown as including eight memory banks BANK0-BANK7. More or fewer banks may be included in the memory array568of other embodiments. Each memory bank includes a plurality of word lines WL, a plurality of bit lines BL and BL, and a plurality of memory cells MC arranged at intersections of the plurality of word lines WL and the plurality of bit lines BL and /BL. The selection of the word line WL is performed by a row decoder558and the selection of the bit lines BL and /BL is performed by a column decoder560. In the embodiment ofFIG. 1, the row decoder558includes a respective row decoder for each memory bank and the column decoder560includes a respective column decoder for each memory bank. The bit lines BL and /BL are coupled to a respective sense amplifier (SAMP). Read data from the bit line BL or /BL is amplified by the sense amplifier SAMP, and transferred to read write amplifiers570over complementary local data lines (LIOT/B). transfer gate (TG), and complementary main data lines (MIOT/B). Conversely, write data outputted from the read/write amplifiers570is transferred to the sense amplifier SAMP over the complementary main data lines MIOT/B, the transfer gate TG, and the complementary local data lines LIOT/B, and written in the memory cell MC coupled to the bit line BL or /BL.

The semiconductor device500may employ a plurality of external terminals that include command and address (C/A) terminals coupled to a command and address bus to receive commands and addresses, and a CS signal, clock terminals to receive clocks CK and /CK, data terminals DQ to provide data, and power supply terminals to receive power supply potentials VDD, VSS, VDDQ, and VSSQ.

The clock terminals are supplied with external clocks CK and /CK that arc provided to an input circuit562. The external clocks may be complementary. The input circuit562generates an internal clock ICLK based on the CK and /CK clocks. The ICLK clock is provided to the command decoder560and to an internal clock generator564. The internal clock generator564provides various internal clocks LCLK based on the ICLK clock. The LCLK clocks may be used for timing operation of various internal circuits. The internal data clocks LCLK are provided to the input/output circuit572to time operation of circuits included in the input/output circuit572, for example, to data receivers to time the receipt of write data.

The C/A terminals may be supplied with memory addresses. The memory addresses supplied to the C/A terminals are transferred, via a command/address input circuit552, to an address decoder554. The address decoder554receives the address and supplies a decoded row address XADD to the row decoder558and supplies a decoded column address YADD to the column decoder560. The address decoder554may also supply a decoded bank address BADD, which may indicate the bank of the memory array568containing the decoded row address XADD and column address YADD. The C/A terminals may be supplied with commands. Examples of commands include timing commands for controlling the timing of various operations, access commands for accessing the memory, such as read commands for performing read operations and write commands for performing write operations, as well as other commands and operations. The access commands may be associated with one or more row address XADD, column address YADD, and bank address BADD to indicate the memory cell(s) to be accessed.

The commands may be provided as internal command signals to a command decoder556via the command/address input circuit552. The command decoder556includes circuits to decode the internal command signals to generate various internal signals and commands for performing operations. For example, the command decoder556may provide a row command signal to select a word line and a column command signal to select a bit line.

The device500may receive an access command which is a read command. When a read command is received, and a bank address, a row address and a column address are timely supplied with the read command, read data is read from memory cells in the memory array568corresponding to the row address and column address. The read command is received by the command decoder556, which provides internal commands so that read data from the memory array568is provided to the read/write amplifiers570. The read data is output to outside from the data terminals DQ via the input/output circuit572.

The device500may receive an access command which is a write command. When the write command is received, and a bank address, a row address and a column address are timely supplied with the write command, write data supplied to the data terminals DQ is written to a memory cells in the memory array568corresponding to the row address and column address. The write command is received by the command decoder556, which provides internal commands so that the write data is received by data receivers in the input/output circuit572. Write clocks may also be provided to the external clock terminals for timing the receipt of the write data by the data receivers of the input/output circuit572. The write data is supplied via the input/output circuit572to the read/write amplifiers570. and by the read/write amplifiers570to the memory array568to be written into the memory cell MC.

The device500may also receive commands causing it to carry out refresh operations. The refresh signal AREF may be a pulse signal which is activated when the command decoder556receives a signal which indicates an auto-refresh command. In some embodiments, the auto-refresh command may be externally issued to the memory device500. In some embodiments, the auto-refresh command may be periodically generated by a component of the device. In some embodiments, when an external signal indicates a self-refresh entry command, the refresh signal AREF may also be activated. The refresh signal AREF may be activated once immediately after command input, and thereafter may be cyclically activated at desired internal timing. Thus, refresh operations may continue automatically. A self-refresh exit command may cause the automatic activation of the refresh signal AREF to stop and return to an IDLE state.

The refresh signal AREF is supplied to the refresh address control circuit566. The refresh address control circuit566supplies a refresh row address RXADD to the row decoder558, which may refresh a wordline WL indicated by the refresh row address RXADD. The refresh address control circuit566may control a timing of the refresh operation, and may generate and provide the refresh address RXADD. The refresh address control circuit566may be controlled to change details of the refreshing address RXADD (e.g., how the refresh address is calculated, the timing of the refresh addresses), or may operate based on internal logic.

The refresh address control circuit566may selectively output a targeted refresh address (e.g., a victim address) or an automatic refresh address (auto-refresh address) as the refreshing address RXADD. The automatic refresh addresses may be a sequence of addresses which are provided based on activations of the auto-refresh signal AREF. The refresh address control circuit566may cycle through the sequence of auto-refresh addresses at a rate determined by AREF.

The refresh address control circuit566may also determine targeted refresh addresses which are addresses that require refreshing (e.g., victim addresses corresponding to victim rows) based on the access pattern of nearby addresses (e.g., aggressor addresses corresponding to aggressor rows) in the memory array568. The refresh address control circuit566may selectively use one or more signals of the device500to calculate the targeted refresh address RXADD. For example, the refresh address RXADD may be calculated based on the row addresses XADD provided by the address decoder. The refresh address control circuit566may sample the current value of the row address XADD provided by the address decoder554and determine a targeted refresh address based on one or more of the sampled addresses.

The refresh address RXADD may be provided with a timing based on a timing of the refresh signal AREF. The refresh address control circuit566may have time slots corresponding to the timing of AREF, and may provide one or more refresh addresses RXADD during each time slot. In some embodiments, the targeted refresh address may be issued in (e.g., “steal”) a time slot which would otherwise have been assigned to an auto-refresh address. In some embodiments, certain time slots may be reserved for targeted refresh addresses, and the refresh address control circuit566may determine whether to provide a targeted refresh address, not provide an address during that time slot, or provide an auto-refresh address instead during the time slot.

The targeted refresh address may be based on characteristics over time of the row addresses XADD received from the address decoder554. The refresh address control circuit566may sample the current row address XADD to determine its characteristics over time. The sampling may occur intermittently, with each sample acquired based on a random or semi-random timing. Access counts associated with the received row addresses XADD may be stored in a stack (e.g., the stack100ofFIG. 1). In some embodiments, access counts which exceed a threshold may have their victim addresses calculated and refreshed. In some embodiments, an extremum search operation (e.g., as described inFIG. 2) may be performed and an address with a maximum access count may be identified as an aggressor.

The refresh address control circuit566may use different methods to calculate a targeted refresh address based on the sampled row address XADD. For example, the refresh address control circuit566may determine if a given row is an aggressor address, and then calculate and provide addresses corresponding to victim addresses of the aggressor address as the targeted refresh address. In some embodiments, more than one victim address may correspond to a given aggressor address. In this case the refresh address control circuit may queue up multiple targeted refresh addresses, and provide them sequentially when it determines that a targeted refresh address should be provided. The refresh address control circuit566may provide the targeted refresh address right away, or may queue up the targeted refresh address to be provided at a later time (e.g., in the next time slot available for a targeted refresh).

The power supply terminals are supplied with power supply potentials VDD and VSS. The power supply potentials VDD and VSS are supplied to an internal voltage generator circuit574. The internal voltage generator circuit574generates various internal potentials VPP, VOD, VARY, VPERI, and the like based on the power supply potentials VDD and VSS supplied to the power supply terminals. The internal potential VPP is mainly used in the row decoder558, the internal potentials VOD and VARY are mainly used in the sense amplifiers SAMP included in the memory array568, and the internal potential VPERI is used in many peripheral circuit blocks.

The power supply terminals are also supplied with power supply potentials VDDQ and VSSQ. The power supply potentials VDDQ and VSSQ are supplied to the input/output circuit572. The power supply potentials VDDQ and VSSQ supplied to the power supply terminals may be the same potentials as the power supply potentials VDD and VSS supplied to the power supply terminals in an embodiment of the disclosure. The power supply potentials VDDQ and VSSQ supplied to the power supply terminals may be different potentials from the power supply potentials VDD and VSS supplied to the power supply terminals in another embodiment of the disclosure. The power supply potentials VDDQ and VSSQ supplied to the power supply terminals are used for the input/output circuit572so that power supply noise generated by the input/output circuit572does not propagate to the other circuit blocks.

FIG. 6is a block diagram of a refresh address control circuit according to an embodiment of the present disclosure. The dotted line is shown to represent that in certain embodiments, each of the components (e.g., the refresh address control circuit666and row decoder658) may correspond to a particular bank668of memory, and that these components may be repeated for each of the banks of memory. In some embodiments, the components shown within the dotted line may be positioned in each of the memory banks668. Thus, there may be multiple refresh address control circuits666and row decoders658. For the sake of brevity, only components for a single bank will be described.

A DRAM interface676may provide one or more signals to an address refresh control circuit676and row decoder658. The refresh address control circuit666may include a sample timing generator680, an aggressor detector circuit682, a row hammer refresh (RHR) state control686and a refresh address generator684. Tire DRAM interface676may provide one or more control signals, such as an auto-refresh signal AREF, and a row address XADD. The optional sample timing generator680generates a sampling signal ArmSample.

In some embodiments, the aggressor detector circuit682may receive each row address XADD associated with each access operation. In some embodiments, the aggressor detector circuit682may sample the current row address XADD responsive to an activation of ArmSample.

The aggressor detector circuit682may store the received row address XADD and determine if the current row address XADD is an aggressor address based on one or more previously stored addresses. The aggressor detector circuit682may include a stack (e.g., such as the stack100ofFIG. 1) which stores the row addresses and also access counts (e.g., numerical values) associated with those row addresses. The aggressor detector circuit682may provide one or more of the stored addresses to the refresh address generator684as the match address HitXADD based on their associated count values.

The RHR state control686may control the timing of targeted refresh operations. Hie RHR state control686may provide the signal RHR to indicate that a row hammer refresh (e.g., a refresh of the victim rows corresponding to an identified aggressor row) should occur. The RHR state control686may also provide an internal refresh signal IREF, to indicate that an auto-refresh should occur. Responsive to an activation of RHR. the refresh address generator684may provide a refresh address RXADD, which may be an auto-refresh address or may be one or more victim addresses corresponding to victim rows of the aggressor row corresponding to the match address HitXADD. The row decoder658may perform a targeted refresh operation responsive to the refresh address RXADD and the row hammer refresh signal RHR. The row decoder658may perform an auto-refresh operation based on the refresh address RXADD and the internal refresh signal IREF. In some embodiments, the row decoder658may be coupled to the auto-refresh signal AREF provided by the DRAM interface676, and the internal refresh signal IREF may not be used.

The DRAM interface676may represent one or more components which provides signals to components of the bank668. In some embodiments, the DRAM interlace676may represent a memory controller coupled to the semiconductor memory device (e.g., device600ofFIG. 1). In some embodiments, the DRAM interlace676may represent components such as the command address input circuit652, the address decoder654, and/or the command decoder656ofFIG. 1. The DRAM interface676may provide a row address XADD, the auto-refresh signal AREF, an activation signal ACT, and a precharge signal Pre. The auto-refresh signal AREF may be a periodic signal which may indicate when an auto-refresh operation is to occur. The activation signal ACT may be provided to activate a given bank668of the memory. The row address XADD may be a signal including multiple bits (which may be transmitted in series or in parallel) and may correspond to a specific row of a memory bank (e.g., the memory bank activated by ACT/Pre).

In the example embodiment ofFIG. 6, the aggressor detector circuit600uses a sampling signal ArmSample to determine when the aggressor detector circuit682should check a value of the row address XADD. The sample timing generator680provides the sampling signal ArmSample which may alternate between a low logic level and a high logic level. An activation of ArmSample may be a ‘pulse’, where ArmSample is raised to a high logic level and then returns to a low logic level. The sample timing generator680may provide a sequence of pulses of ArmSample. Each pulse may be separated from a next pulse by a time interval. The sample timing generator680may randomly (and/or semi-randomly and/or pseudo-randomly) vary the time interval.

The aggressor detector circuit682may receive the row address XADD from live DRAM interface676and ArmSample from the sample timing generator680. The row address XADD may change as the DRAM interface676directs access operations (e.g., read and write operations) to different rows of the memory cell array (e.g., memory cell array118ofFIG. 1), Each time the aggressor detector circuit682receives an activation (e.g., a pulse) of ArmSample, the aggressor detector circuit682may sample the current value of XADD.

Responsive to an activation of ArmSample, the aggressor detector circuit682may determine if one or more rows is an aggressor row based on the sampled row address XADD. and may provide identified aggressor rows as the match address HitXADD. As part of this determination, the aggressor detector circuit682may record (e.g., by latching and/or storing in a stack) the current value of XADD responsive to the activation of ArmSample. The current value of XADD may be compared to previously stored addresses in the aggressor detector circuit682(e.g., the addresses stored in the stack), to determine access patterns over time of the sampled addresses. If the aggressor detector circuit682determines that the current row address XADD is being repeatedly accessed (e.g., is an aggressor row), the activation of ArmSample may also cause the aggressor detector circuit682to provide the address of the aggressor row as a match address HitXADD. fat some embodiments, the match address (e.g., aggressor address) HitXADD may be stored in a latch circuit for later retrieval by the refresh address generator684.

For example, the aggressor detector circuit682may store the value of sampled addresses in a stack, and may have a counter associated with each of the stored addresses. When ArmSample is activated, if the current row address XADD matches one of the stored addresses, the value of the counter may be updated (e.g., incremented). Responsive to the activation of ArmSample. the aggressor detector circuit682may provide the address associated with the maximum value counter as the match address HitXADD. An extremum search operation (e.g., as described inFIG. 2) may be used to identify the maximum value. Other methods of identifying aggressor addresses may be used in other examples.

The RHR state control686may receive the auto-refresh signal AREF and provide the row hammer refresh signal RHR. The auto-refresh signal AREF may be periodically generated and may be used to control the timing of refresh operations. The memory device may carry out a sequence of auto-refresh operations in order to periodically refresh the rows of the memory device. The RHR signal may be generated in order to indicate that the device should refresh a particular targeted row (e.g., a victim row) instead of an address from the sequence of auto-refresh addresses. The RHR state control686may use internal logic to provide the RHR signal. In some embodiments, the RHR state control686may provide the RHR signal based on certain number of activations of AREF (e.g., every 4thactivation of AREF). The RHR state control686may also provide an internal refresh signal IREF, which may indicate that an auto-refresh operation should take place. In some embodiments, the signals RHR and IREF may be generated such that they are not active at the same time (e.g., are not both at a high logic level at the same rime).

The refresh address generator684may receive the row hammer refresh signal RHR and the match address HitXADD. The match address HitXADD may represent an aggressor row. The refresh address generator684may determine the locations of one or more victim rows based on the match address HitXADD and provide them as the refresh address RXADD. In some embodiments, the victim rows may include rows which are physically adjacent to the aggressor row (e.g., HitXADD+1 and HitXADD−1). In some embodiments, the victim rows may also include rows which are physically adjacent to the physically adjacent rows of the aggressor row (e.g., HitXADD+2 and HitXADD−2). Other relationships between victim rows and the identified aggressor rows may be used in other examples.

The refresh address generator684may determine the value of the refresh address RXADD based on the row hammer refresh signal RHR. In some embodiments, when the signal RHR is not active, the refresh address generator684may provide one of a sequence of auto refresh addresses. When the signal RHR is active, the refresh address generator684may provide a targeted refresh address, such as a victim address, as the refresh address RXADD.

The row decoder658may perform one or more operations on the memory array (not shown) based on the received signals and addresses. For example, responsive to the activation signal ACT and the row address XADD (and1REF and RHR being at a low logic level), the row decoder658may direct one or more access operations (for example, a read operation) on the specified row address XADD. Responsive to the RHR signal being active, the row decoder658may refresh the refresh address RXADD.

FIG. 7is a block diagram of an aggressor detector circuit according to the present disclosure. The aggressor detector circuit700may implement the aggressor detector circuit682in some embodiments. The aggressor detector circuit700includes a stack790and stack control logic792. The stack790may implement the stack100ofFIG. 1in some embodiments.

The stack790includes a number of files702each of which includes a row address field788which stores a row address XADD(Y) and an associated count value field789which stores a count value Count(Y). Each file702is associated with an accumulator circuit706. The files702and accumulator circuits706are coupled to control logic710which may be used to perform an extremum search operation (e.g., as described inFIG. 2). Although not shown for clarity inFIG. 7, the stack790may generally use similar signals (e.g., Match(Y), Compare(X), etc.) as those discussed regarding the stack100ofFIG. 1.

The stack790is coupled to a stack logic circuit792which may be used to provide signals and control the operation of the stack790. The control logic circuit710which manages the extremum search operation may be included as part of the stack logic circuit792m some embodiments. The row address field788may include a number of bits (e.g., a number of CAM cells) based on the number of bits in a row address. For example, the row address field788may be 16 bits wide in some embodiments. The count value field789may have a number of bits based on a maximum possible value of the count values it is desired to track. For example, the count value field789may be 11 bits wide in some embodiments. In some embodiments, the stack790may have a depth (e.g., a number of files702) of100. Other widths and depths for the stack790may be used in other embodiments.

In some embodiments, the slack790may include additional fields in the files702which may be used to store additional information associated with the stored row address. For example, each file702may include an empty flag, which may be used to indicate if the data in the file702is ready to be overwritten or not. The empty flag may be a single bit, with a first state which indicates that the file is ‘full’ and a second state which indicates the file is empty (e.g., the information in the file is ready to be overwritten). When a row address and count are removed from the stack790(e.g., after their victims are refreshed) rather than delete the data in that file702, the empty flag may be set to the second state instead.

When a row address XADD is received by the aggressor detector circuit700, it may be stored in an address latch793. In some embodiments, the stack logic circuit792may save a current value of the row address XADD in the address latch793when the signal ArmSample is provided. The address latch793may include a number of bits equal to the number of bits of a row address XADD. Thus, the address latch793may have a same width as the row address field788of the slack790. The address latch793may include a number of latch circuits to store the bits of the row address. In some embodiments, the address latch793may include CAM cells (e.g., CAM cells300ofFIG. 3) and may be structurally similar to the files702of the stack790.

An address comparator794may compare the row address XADD stored in the address latch793to the addresses in the stack790. The stack logic circuit792may perform a comparison operation based on the CAM cells of the stack790. For example, as discussed in regards toFIG. 1, each CAM cell of each row address field788may be coupled in common to a signal line carrying a match signal. When an address is compared to the row address fields788, the match signal lines may be pre-charged (e.g., by providing signals BitxCompPre and FindMaxMinOp ofFIG. 2). The stack logic circuit792may then provide the address as a comparison signal in common to all of the row address fields788. A first bit in each of the row address fields788may receive a first bit of the row address XADD for comparison, a second bit of each of the row address fields788may receive a second bit of the row address XADD and so forth. After the CAM cells perform the comparison operation, the match signal may only remain at the pre-charged level (e.g., a high logical level) if every bit of the comparison address matched every bit of the stored address XADD(Y). The address comparator794may determine if there were any matches in the files where the accumulator signal is at a high level, based on the states of the match signals (e.g., the voltages on the match signal lines) and the accumulator signals.

If there is a match between the received address XADD and one of the stored addresses XADD(Y), the count value Count(Y) associated with that stored address XADD(Y) which matched may be updated. The count value Count(Y) may be read out to a working counter795, which may update the numerical value of the count value Count(Y) and then write it back to the same file702associated with the matched stored address XADD(Y). For example, the working counter795may increment the count value Count(Y).

In some embodiments, the components of the accumulator circuit706may be used to provide additional functionality. For example, in the accumulator circuits706(e.g., as described in detail in the accumulator circuit400ofFIG. 4) may also be used to serially read out the contents of a Count Value CAM for further operations, such as loading it into the working counter795and incrementing its value. For example when the address comparator indicates a match between the row address XADD and one of the stored addresses788, that result may be coupled onto the corresponding match signal (e.g., Bitx Match) to the associated accumulator circuit706, and then the signal BitxMatchAccumSample may be pulsed. Therefore only that file's accumulator signal MaxMinY would be high, thereafter allowing its corresponding match signal BixMatch_Y to be precharged high when the global BitxCompPre was asserted. Then only the comparison signal X_Compare for the selected bit of the Count Value CAM array would be asserted, (e.g., at a high logical level for example). The signals CrossRegCompPreF and CrossRegContp would then be used by the control logic710as previously described (e.g., inFIG. 4) to determine the contents of the selected count value789bit back to the control circuit710where it would be loaded into the Working Counter795. This process would then be repeated for each bit. After the Working Counter795was incremented, the updated count would then be parallel-written back into the selected file's count value789(e.g., by providing the write signal CountWriteY).

If there is not a match between the received address XADD and one of the stored addresses XADD(Y), then the address XADD may be added to the stack790. This may be done by providing a write signal along with the bits of XADD to one of the files of the stack790. If there is room in the stack790, then the received row address XADD may be stored in an empty file702, and the working counter may set the associated count value in that file702to an initial value (e.g., 0, 1).

If there is not a match between the received address XADD and one of the stored addresses XADD(Y) and the stack790is full, the stack logic circuit792may replace one of the stored addresses currently in the stack790with the received address. In some embodiments, the control logic710may be used to perform an extremum search operation for a minimum of the stored count values Count(Y). The stack logic circuit792may then provide the new address XADD in common to all of the row address fields788along with a master write signal (e.g., CountWriteEn ofFIG. 4) in common to all of the accumulator circuits706. The accumulator circuits706may only provide the write signal to the files702which are associated with a minimum count value. Since in some embodiments, the accumulator circuits706may also break ties, this means that the write signal will only be provided to one file702and so the address XADD may be written to the file702which contains the minimum value. The identified minimum count value may then be reset to an initial value.

The stack logic circuit792may identify and provide a match address HitXADD based011the count values Count(Y) stored in the stack. In general, when one of the stored addresses XADD(Y) is provided as the match address HitXADD, the stored address XADD(Y) may be removed from stack790(or an empty flag of that file702may be set) and the count value Count(Y) may be reset to an initial value.

In some embodiments, the stack logic circuit792may include a threshold comparator circuit797which may compare the updated count value (e.g., after the count value is updated by the working counter795) to a threshold value. If the updated count value is greater than the threshold value, then the stored address XADD(Y) associated with the updated count value may be provided as the match address HitXADD.

In some embodiments, the stack logic circuit792may provide the stored row address XADD(Y) associated with a maximum count value as the match address HitXADD. For example, the control logic710may perform an extremum search operation to locate a maximum value, and then may provide an index of the file702containing that maximum value and also the associated row address.

In some embodiments, the locations of the current maximum and or minimum values may be indicated by pointers, which may be operated by a pointer logic circuit796. For example, the control logic710may perform an extremum search to locate an maximum value and then may return an index of the file702containing that maximum value. The pointer logic circuit796may direct a maximum pointer to indicate the file702containing the maximum value. New extremum search operations may be performed to update the maximum as count values change. When a match address needs to be provided, the maximum pointer may be used to quickly supply the address associated with the current maximum value.