Flash memory with integrated ROM memory cells

Memory array for storing a plurality of data bits. The memory array has flash memory cells, ROM memory cells addressing circuitry. The addressing circuitry is operatively coupled to both the plurality of flash memory cells and the plurality of ROM memory cells, the addressing circuitry being configured to address both the plurality of flash memory cells and the plurality of ROM memory cells.

FIELD

The present invention relates generally to memory arrays and, in particular, to memory modules incorporating both flash memory and ROM memory cells with common addressing circuitry.

BACKGROUND

Memory arrays for storage, both short-term and long-term, of digital data are well known in the art. Various configurations and implementations of random access memory, known in the art as RAM, provide data storage in relatively small, efficient spaces in comparison to other memory technologies. RAM cells, however, utilize active electronic components, including transistors, to store digital data, resulting in an effectively immediate loss of the stored data in the event of a loss of power to the RAM cells. Hence, RAM memory is referred to as volatile memory.

Non-volatile memory cells, by contrast, maintain stored digital data for some extended period of time without need to maintain power to the memory cell. Such non-volatile memory cells include read-only memory cells, made from various semiconductor devices and known in the art as ROM, and flash memory cells, traditionally made from floating-gate transistors. Such non-volatile memory cells are electrically addressed and thus are faster to access than, for instance, mechanically addressed data storage systems such as magnetic storage (for instance, hard disks) and optical storage (for instance, CD-ROMs). However, non-volatile memory cells have historically contrasted unfavorably with volatile memory and mechanically addressed data storage in terms of cost, efficiency and utility. While both volatile and mechanically addressed storage is relatively cheap, densely packed and freely writeable and rewriteable, non-volatile memory has historically been expensive, large and with limitations on how many times the cell may be written to, as with a flash memory cell, or not subject to being rewritten at all, as with ROM memory cells.

On that basis, non-volatile, electronically addressed memory cells have historically been used sparingly in contrast with volatile memory and mechanically addressed non-volatile data storage. However, recent process improvements in non-volatile memory have made the use of non-volatile memory more viable. In particular, flash memory applications have become increasingly common, while new non-volatile memory techniques are in development.

The proliferation of flash memory has, however, created new challenges. In particular, while contemporary flash memory relatively reliable in comparison with historic flash memory, contemporary flash memory remains relatively unreliable in contrast with many other forms of memory, both volatile and non-volatile. While the relative unreliability of flash memory may be acceptable in consumer electronics, for instance, in life-critical applications, such as in medical devices, data unreliability may create challenges in using and implementing flash memory arrays.

SUMMARY

Historically, the fact that flash memory cells and ROM memory cells utilize differing architecture has provided strong incentives to designers of individual memory arrays to make an array from one of flash memory and ROM memory, but not both. Differences in the physical dimensions of flash memory cells, made from floating-gate transistors, and ROM memory cells, made, for instance, from complimentary metal-oxide semiconductors, mean that flash and ROM memory cells cannot be formed into space-efficient lines of equivalent length and size. Differing power requirements to read and, in the case of flash memory cells, write to the cells creates comparatively large overhead and support electronics for a memory array with both flash and ROM memory cells. In addition, because of the above described differences in size and layout, flash and ROM memory arrays have historically incorporated varying addressing and sensing schemes, meaning that electronics configured to access individual cells have not been cross-compatible between flash and ROM memory arrays.

Owing to these above-detailed factors which tend to provide significant incentives not to combine flash and ROM, flash and ROM memory cells have not been incorporated within a single memory array incorporating common overhead circuitry. However, methodologies have been developed to permit the efficient combination of flash and ROM memory cells with a single array and incorporating at least some common overhead circuitry. Common overhead circuitry may include, but not be limited to, addressing circuitry, read circuitry, power supply, error detection and correction, data caching and timing structures. In applications in which the reliability and data integrity of flash memory cells may be inadequate, the benefits provided by rewriteable, non-volatile memory may nevertheless be attained when supplemented by relatively more reliable ROM memory.

In an embodiment, a memory array configured to store a plurality of data bits comprises a plurality of flash memory cells, a plurality of ROM memory cells and addressing circuitry operatively coupled to both the plurality of flash memory cells and the plurality of ROM memory cells, the addressing circuitry being configured to address both the plurality of flash memory cells and the plurality of ROM memory cells.

In an embodiment, the plurality of data are arranged in bitlines, the plurality of flash memory cells have a flash bitline address spacing, the plurality of ROM memory cells have a ROM bitline address spacing, and the flash bitline address spacing of the plurality of flash memory cells are approximately equal to the ROM bitline address spacing of the plurality of ROM memory cells.

In an embodiment, the memory array further comprises read circuitry operatively coupled to both the plurality of flash memory cells and the plurality of ROM memory cells, the read circuitry being configured to read both the plurality of flash memory cells and the plurality of ROM memory cells.

In an embodiment, the memory array is comprised of a single memory array and wherein the single memory array comprises both the plurality of flash memory cells and the plurality of ROM memory cells.

In an embodiment, the memory array further comprises overhead circuitry including at least one of a power source, a voltage generator and an addressing block, the overhead circuitry being shared by both the plurality of flash memory cells and the plurality of ROM memory cells.

In an embodiment, a method of providing a memory array configured to store a plurality of data bits comprises the steps of providing, in a single array, a plurality of flash memory cells and a plurality of ROM memory cells and providing addressing circuitry, operatively coupled to both the plurality of flash memory cells and the plurality of ROM memory cells, configured to address both the plurality of flash memory cells and the plurality of ROM memory cells.

In an embodiment, the method further comprises the step of providing read circuitry, operatively coupled to both the plurality of flash memory cells and the plurality of ROM memory cells, the read circuitry being configured to read both the plurality of flash memory cells and the plurality of ROM memory cells.

In an embodiment, the method further comprises the step of providing overhead circuitry including at least one of a power source, a voltage generator and an addressing block, the overhead circuitry being shared by both the plurality of flash memory cells and the plurality of ROM memory cells.

In an embodiment, a method of using a memory array configured to store a plurality of data bits having, in a single array, a plurality of flash memory cells and a plurality of ROM memory cells comprises the steps of addressing both the plurality of flash memory cells and the plurality of ROM memory cells with addressing circuitry common to both the plurality of flash memory cells and the plurality of ROM memory cells and reading both the plurality of flash memory cells and the plurality of ROM memory cells with reading circuitry common to both the plurality of flash memory cells and the plurality of ROM memory cells.

DESCRIPTION

FIG. 1ais a simplified depiction of a typical flash data bit or flash memory cell10known in the art. Throughout this description, flash data bit and flash memory cell are used interchangeably. An adaptation of a conventional metal-oxide substrate field effect transistor (MOSFET), a channel may be created in p-substrate12between n-source14and n-drain16by inducing a charge on gate18. Unlike in a conventional MOSFET transistor, however, floating gate20is incorporated between dielectric layers22between gate18and p-substrate12. The creation of a voltage on gate18causes floating gate20to store electrons which, owing to the presence of dielectric layers22, do not readily escape floating gate20. The presence of the charge in floating gate20causes a predictable variance in the voltage threshold of flash memory cell10which may be conventionally detected as part of a read operation. The ability of flash memory cell10to store digital information long term may, by consequence, be dependent on the ability of floating gate20to maintain an applied charge without substantial degradation over time.

The various components of flash memory cell10may be sized according to contemporary processes. In an embodiment, flash memory cell10is formed according to the 0.25 micrometer process. In such an embodiment, flash memory cell10has 0.9 micrometer by 1.20 micrometer dimensions.

FIG. 1bis a depiction of an exemplary physical embodiment of flash memory cell10. In an exemplary embodiment, flash memory cell10is read by placing gate18at two (2) Volts, drain16at 1.4 Volts and n-source14at zero (0) Volts, and the resultant current from drain16to source measured; if the drain-to-source current is less than approximately one (1) microampere then a logical “0” is stored in cell10, while if the drain-to-source current is greater than approximately ten (10) microamperes then a logical “1” is stored in cell10. In an embodiment, flash memory cell10may be programmed by placing gate18at 1.7 Volts, n-drain16at 0.6 Volts and n-source14at 9.5 Volts. In an embodiment, flash memory cell10may be erased by placing gate18at thirteen (13) Volts, n-drain16at zero (0) Volts and n-source14at zero (0) Volts.

FIG. 2is an exemplary application of multiple flash memory cells10being incorporated within line24to provide multi-bit data storage. N-sources14are shorted to a source line (YY) and N-drains16are coupled to bitlines26. Gates18are coupled to wordlines (XX). In so doing, a particular bit of each of multiple data words (for instance, bit0of each of words0and1) may be accessed on bitline26and the wordline through a read operation. By repeating this structure on multiple additional lines24, additional bits of the words of illustrated line24(for instance, bit0of words2and3) may be accessed for reading and writing. In an embodiment, each line24has two thousand ninety six (2,096) cells10, providing a flash bitline address spacing of two thousand ninety six (2,096) per line24. In an embodiment, each bitline26connects to two hundred fifty-six (256) flash data bits10.

FIG. 3ais a simplified depiction of a typical electrically programmable read-only memory (EPROM) data bit or memory cell30known in the art. Throughout this document, the terms read-only memory cell, read-only data bit, ROM or EPROM data bit, ROM or EPROM memory cell are used interchangeably. While the electrically programmable read-only memory cell30is shown for illustrative purposes, read-only memory cells which are not electrically programmable may also be utilized, as illustrated inFIG. 3b. In various embodiments, ROM data bit30is not electrically programmable. Like flash memory cell10, ROM data bit30is also an adaptation of a conventional MOSFET, with a channel being created in p-substrate32between n-source34and n-drain36by inducing a charge on gate38.

In contrast with floating gate20of flash memory cell10, which is commonly comprised of conventional polycrystalline silicon as used in MOSFET, floating gate40of EPROM data bit30is doped so as to resist changes in floating gate's40electric potential after placing floating gate40in a particular logical state. For instance, while floating gate40may be switched so that ROM data bit30stores a logical “1” to a logical “0”, the doping of floating gate40may prevent switching from a logical “0” to a logical “1”. In various embodiments, floating gate40is doped with phosphorous. While dielectric layers42may be incorporated as in flash memory cell10, dielectric layers42may not be required to maintain the electric potential of floating gate40. In embodiments which are not electrically programmable, and thus do not incorporate floating gate40, a contact or lack of contact may set the state of ROM memory cell30as known in the art.

The various components of ROM data bit30may be sized according to contemporary processes known in the art. In an embodiment, cell30is formed according to the 0.25 micrometer process. In such an embodiment, cell30has 1.375 micrometer by 0.9 micrometer dimensions.

FIGS. 4aand4bare exemplary applications of multiple ROM data bits30being incorporated within line44to provide multi-word data storage. InFIG. 4a, N-drain34and n-source36of adjacent ROM data bits30are coupled to bitlines26and ground respectively while gates38are coupled to wordlines XX). In so doing, a particular bit of each of multiple data words (for instance, bit0of each of words0-1) may be accessed on bitline26through a read operation on a word selected by the wordline. By repeating this structure on multiple additional lines44, additional bits of the words of illustrated line44(for instance, bit0of words2-3) may be accessed for reading and writing. In an embodiment, each line44includes two thousand ninety six (2,096) cells30, providing a ROM bitline address spacing of two thousand ninety six (2,096) per line44. In an embodiment, each bitline26corresponds to two hundred fifty-six (256) ROM data bits30.

The various embodiments described above are merely exemplary, as various additional types of flash data bits10are known in the art and myriad ROM data bits30are also known in the art. Similarly, flash data bits10and ROM data bits30are commonly organized into lines and columns according to various techniques dependent on the circumstances of the data bits themselves and the circumstances of their use. However, incorporating flash data bits10according to a common addressing scheme, i.e., common schemes by which bitlines26and wordlines44are assigned between and among flash data bits10and ROM data bits30, due to the differing characteristics of flash data bits10and ROM data bits30, may make the resultant memory relatively inefficient. In particular, because flash data bits10and ROM data bits30have differing dimensions, common addressing schemes may tend to create wasted space on a chip. Similarly, because flash data bits10and ROM data bits30have different performance characteristics, such as the amount of time needed to read data from one or the other, utilizing non-alike data bits within a common addressing scheme may, unless particularly addressed, create unreliabilities.

As illustrated, line44has shared N-sources36coupled to ground. In various embodiments, ROM memory cells30are programmed by either including or not including a drain connection for each ROM memory cell30. If there is a drain connection, the ROM memory cell may conduct current when selected. If there is no drain connection, the ROM memory cell may conduct no current when selected. The drain connection can be made with many semiconductor materials. In one embodiment, the connection is a contact. In other embodiments, for example, the connection is a via, metal or diffusion layer.

FIG. 5is a block diagram of memory array or module50which is a single memory array incorporating both flash data bits10(not shown with particularity) and ROM data bits30(not shown with particularity) according to a common addressing scheme. Flash data bits10are organized into lines24and ROM data bits are organized into lines44, as discussed above. Multiple bitlines26extend from rows24,44to column multiplexor52as known in the art. Sensing circuits54are read circuitry utilized to detect information placed on bitlines26and thus determine what the contents of a particular data bit are, irrespective of whether the data bit is a flash data bit10or a ROM data bit30.

Column decode block56, similar to that of column decoders known in the art, is overhead circuitry that controls a particular column multiplexor52′ to select each bitline26based on the column address as input into column decode block56. It is noted that in the illustrated embodiment, memory module50is divided into halves57, each with its own addressing circuitry such as multiplexors52,52′ and read circuitry such as sensing circuits54, to promote simplicity in such circuitry. In various alternative embodiments, memory module50may not be divided at all and thereby not multiple blocks of, for instance, multiplexors52,52′ and sensing circuitry54, or may be divided into more than two blocks with an accompanying multiplexors52,52′ and sensing circuitry54for each block.

Line electronics58is overhead circuitry which includes a row decoder, wordline driver and sourceline driver. The row decoder, as is familiar in the art, is configured to select a particular row or line24,44based on the input address. The wordline driver and the sourceline driver combine to create a voltage differential between wordline60and sourceline62, respectively. Wordline60and sourceline62provide a voltage differential over flash memory cells10in order to read or write the flash memory cell, as known in the art. As ROM memory cells30cannot be written to, only the wordline driver is coupled to a wordline60ROM memory cells30. The presence of a high voltage, such as a reference voltage, or a low voltage, such as a ground voltage, selects each row24,44for the purposes of reading the data from the cells10,30of the particular row24,44. In combination with the applied voltage on bitlines26from sensing circuitry or sensing circuit54, individual cells10,30may be selectively activated for reading and, in the case of flash memory cells10, writing.

High voltage generator64is overhead circuitry configured to supply voltages for programming and erasing flash memory cells10. In an embodiment, nine and one half (9.5) Volts is used for programming flash memory cells10and thirteen (13) Volts is used for erasing flash memory cells10. In an embodiment, high voltage generator64comprises at least one 2.0 Volt supply coupled to a Dickson charge pump to provide the programming and erasing voltages as appropriate.

Reference bitline66is structurally similar to bitlines26. However, reference bitline66is physically positioned at the far end of each row24,44relative to line electronics58. As will be discussed further below, the positional distance of reference bitline66may provide a deliberate delay in the operation of sensing circuit54in reading data following a selection of a particular memory cell10,30for reading by column decode block56and the wordline driver. Because of the physical differences between flash memory cells10and ROM memory cells30, the timing of activation of such cells10,30may vary with respect to one another.

In certain circumstances, because ROM memory cells30are physically larger than flash memory cells10, it may take longer for signals to propagate down wordlines60on ROM rows44than on flash rows24. Alternatively, ROM memory cells30may access faster than flash memory cells10owing to a shorter effective channel length on ROM memory cells30compared with flash memory cells10. This causes the read current to be higher and the sense amp triggers faster as does the circuit that times the read. As a result, the timing by which a selected flash memory cell10may place data on its bitline26during a read operation may occur later in time than the same read operation on a corresponding ROM memory cell30. Thus, the twelfth flash memory cell10in row24may place its data on its corresponding bitline26slower than the twelfth ROM memory cell30in row44. Because the twelfth flash memory cell10and the twelfth ROM memory cell30of each row24,44utilize the same bitline26, sensing circuits54may not, without an additional indication, be able to predict when the signal on the twelfth bitline26will be accurate.

When a signal propagates from the wordline driver, because the memory cell10,30is located physically closer to the wordline driver than reference bitline66, it may inherently be the case that the particular memory cell10,30is activated before reference bitline cell68, a reference memory cell10or30, as appropriate to the row24,44in which it is located. In certain embodiments, reference bitline cell68may be physically sized differently than flash memory cells10and ROM memory cells30so as to trigger more slowly than flash memory cells10and ROM memory cells30. In an embodiment, reference bitline cell68is a dummy memory cell not configured to store data.

It is known that once reference bitline66is activated, whatever the selected memory cell10,30may be, the selected memory cell10,30should have been activated, allowing sensing circuits54to read the data on the bitline26corresponding to the selected memory cell10,30. Consequently, activation of reference bitline66provides an indication to sensing circuit54that the data on the selected bitline26may be accurately read. As a result, reference bitline66provides the same sensing circuit54to read both flash memory cells10and ROM memory cells30.

FIG. 6is a block diagram illustrating detail of memory module50, illustrating individual flash memory cells10and ROM memory cells30. Row decoder70includes selection circuitry to select lines24,44for wordline driver72and sourceline driver74. Bitlines26are selected by way of column decode block56and column multiplexors52,52′. Individual cells10,30are positioned physically closer to row decoder70than is reference bitline cell68. As a result, flash memory cells10and ROM memory cells30may utilize a common addressing and sensing scheme, while flash memory cells10may utilize a common writing scheme.

FIG. 7ais a simplified block diagram of an embodiment of sensing circuit54and illustrative memory cells10,30coupled to sensing circuit54by way of bitline26. It is noted that for simplicity only a single bitline26is illustrated, though in the actual implementation there would be as many rows24,44as are present in memory module50(FIG. 5) and as many bitlines26as there are columns in rows24,44. Switch76may be utilized to select a particular bitline26for reading while switches78,80may be utilized to select a particular cell10,30on the particular bitline26for reading. Switches76,78and80are detail of column multiplexors52and52′.

Reference bitline cells68are coupled to reference bitline66and are selectable via switches82,84,86in a manner similar to that of bitline26. Reference bitline66is coupled to inverter88and from there to logic and delay block90and latch92. Latch92is configured to store the result of sensing the voltage on bitline26by way of inverter94. Logic and delay block90operates latch92based on the change in reference bitline66.

As is known in the art, in order to read cells10,30, an electronic stimulus is applied to cells10,30and the effect of cells10,30on the input electronic stimulus is measured. In an embodiment, cells10and30are variably biased with current, resistance or both and when wordline24or44is selected the voltage on bitline26is measured by way of inverter94and stored in latch92. If the charge stored in cell10,30is such that cell10,30conducts current and functions as a closed circuit, the voltage on bitline26may be low, that is reflected digitally by inverter94. Likewise, if the charge stored in cell10,30is such that cell10,30conducts little current, the voltage on bitline26may be high, which may be reflected digitally by inverter94. In an embodiment, the voltage on bitline26has a maximum of approximately two (2) Volts and a minimum of approximately zero (0) Volts, while inverter94has a threshold of between approximately 0.7 Volts to one (1) Volt.

Consequently, if the voltage on bitline26is less than approximately one (1) Volt inverter94may register that a logical “1” is in the cell10,30influencing bitline26by outputting a high voltage to latch92. If the voltage on bitline26is greater than approximately one (1) Volt inverter may register that a logical “0” is in the cell10,30influencing bitline26by outputting a low voltage to latch92.

Particularly regarding flash memory cells10, though also in certain instances with respect to ROM memory cells30, certain cells10may lose their ability to store charge on floating gate20, effectively rendering cell10inoperative and losing the data stored in cell10. To manage the reliability of cells10, margin bias circuit96provides variable bias current to test a reliability of cells10,30.

Margin bias circuit96, in the illustrated embodiment a hold circuit based on P-channel transistors (below) is configurable to provide testing to assess not merely the ability of cell10to store a logical “0” and a logical “1”, but rather whether cell10only barely has the ability to store a logical “0” or logical “1”, or if cell10has some margin in its ability to store a logical “0” or a logical “1”. In particular, if cell10can store a logical “0” or logical “1”, but cannot demonstrate margin in the ability to store logical “0” or logical “1”, data stored in cell10may be preserved by being transferred to another cell10while the cell10which failed the margin test may be deemed unreliable and, in an embodiment, not utilized for further data storage.

Pull-up circuit98forces bitline26in a known, charged state, in an embodiment two (2) Volts. Consequently, a read operation on cell10may be conducted such that the state on bitline26changes when floating gate20is charged. Thus, the charge on floating gate20must be strong enough to permit the flow of current over cell10to change the state of bitline26in order to store a logical “1”.

Margin bias circuit96is configurable to provide current to keep bitline26high after pull-up circuit98is switched off. In a conventional read operation to determine what is stored in cell10, in an embodiment, margin circuit96contains two P transistors YY and XX. P transistor YY and P transistor XX provide a base amount of current to keep bitline96high. In an embodiment, P transistor YY provides approximately four (4) microamperes of current to bias bitline26. In an embodiment, P transistor XX provides approximately five (5) microamperes of current to bias bitline26. Consequently, in such an embodiment, to store a logical “1”, cell10must be able to pass or “sink” at least nine (9) microamperes of current to change the voltage state of bitline26sufficient to be recorded by inverter94. If cell10passes or sinks less than nine (9) microamperes of current, a logical “0” will be stored.

In an embodiment, margin bias circuit96is configured to conduct a test on cell10to determine if cell10has margin in its ability to store a logical “0”. In an embodiment, margin bias circuit96is configured to provide four (4) microamperes of current to conduct a test of cell's10ability to store a logical “0”. If the charge stored in floating gate20is not strong enough to permit cell10to sink four (4) microamperes in total four (4) microamperes from P transistor YY and zero (0) microamperes from P transistor XX, then cell10may be deemed to have sufficient margin to reliably continue to store a logical “0”

In various alternative embodiments, margin bias circuit96is configured to provide different amounts of current dependent on the characteristics of cell10and the degree of margin that is desired for a cell10to qualify as reliable. In the above embodiment, margin bias circuit96is configured to provide four (4) microamperes to test cell's10ability to store a logical “0”; as cell10would need to sink less than four (4) microamperes to qualify as being reliable. The above principles apply to demonstrate greater or lesser amounts of margin.

The ability of cell10to store a logical “1” operates on a related principle. To store a logical “1”, floating gate20must store enough charge that cell10can sink more current than the amount being forced onto bitline26and thereby allow the voltage on bitline26to drop beyond that which registers as a low voltage for inverter94.

In a conventional read mode, then, when margin bias circuit96provides, in the above embodiment, four (4) microamperes on P transistor YY and five (5) microamperes on P transistor XX, cell10must sink more current than the combined nine (9) microamperes and therefore force bitline26low. In order to test for the reliability of cell10to store a logical “1”, margin bias circuit96provides an additional five (5) microamperes of current into bitline26. Therefore, cell10must now pass or sink a combined fourteen (14) microamperes. The additional five (5) microamperes is forced into bitline26by P transistor ZZ. If cell10can sink the original nine (9) microamperes plus the additional current provided by P transistor ZZ, the cell is tested as having sufficient margin to be considered reliable.

In various alternative embodiments, margin bias circuit96provides different amounts of current, resulting in different amounts of margin for logical “0” and logical “1”.

In further alternative embodiments, the amount of current margin bias circuit96provides is selectable in percentage terms. For instance, a margin “0” test may be conducted to provide a selectable percentage margin over a normal read operation. In the above embodiment, a margin “0” test of) four (4) microamperes provides an indication of approximately fifty (50) percent of margin over the nine (9) microamperes of a normal read operation. Similarly, a margin “1” test may be conducted to provide a selectable percentage. In an embodiment, margin bias circuit96may be configurable to provide current in order to indicate variable percentage of margin.

In various embodiments, pull-up circuit98is not provided, and margin bias circuit96provides all intended current biasing on bitline26. In such embodiments, margin bias circuit96simply provides a variable amount of bias current on bitline26, in the above embodiment four (4) microamperes, nine (9) microamperes and fourteen (14) microamperes for margin “0” testing, normal read operations and margin “1” testing, respectively.

In certain embodiments, a current which induces a voltage may also be referenced in terms of the resistance which is utilized to induce the current. Thus, margin bias circuit96and pull-up circuit98may be understood to impart a bias resistance rather than, or in addition to the bias current described herein. The resistance would be determined by the size of the transistors in each circuit.

Reference hold circuit100and reference pull-up circuit102provide related testing of reference bitline cells68as margin bias circuit96and pull-up circuit98provide for cells10. In an alternative embodiment illustrated inFIG. 7b, reference hold circuit100is not included and pull-up circuit102provides pro-charging of reference bitline66. As, in various embodiments, reference bitline cells68are electrically similar or identical to those of cells10, pull-up circuit102is configured to force reference bitline high and reference hold circuit100may variably provide five (5) eighth (8) and thirteen (13) microamperes for margin “0” testing, normal reading and margin “1” testing, respectively. Margin bias circuit96and reference hold circuit100may be selectable from any electronic circuitry known in the art which can reliably be configured to provide a predetermined and selectable amount of current.

FIGS. 8a,8band8care exemplary block diagrams of a portion ofFIGS. 7aand7billustrating margin “1” testing, a normal read operation and margin “0” testing, respectively. In all ofFIGS. 8a,8band8c, pull-up circuit98precharges bitline26to VDD. InFIG. 8a, margin bias circuit96is configured for a margin “1” test of cell10and produces fourteen (14) microamperes of current. Cell10may be determined to have adequate margin for reading a logical “1” if the voltage input to inverter94remains below the transition threshold of inverter94.

InFIG. 8b, margin bias circuit96is configured for a normal read operation and produces nine (9) microamperes of current. Cell10may be expected to have accurately displayed the digital bit stored therein and the inverter may be deemed to have accurately reported the nature of the digital bit stored therein based on the voltage on bitline26being above or below the transition threshold of inverter94, as the case may be.

InFIG. 8c, margin bias circuit96is configured for a margin “0” test of cell10and produces four (4) microampere of current. Cell10may be determined to have adequate margin for reading a logical “0” if the voltage input to inverter94remains above the transition threshold of inverter94.

FIG. 9is a schematic diagram of margin bias circuit96and pull-up circuit98. Margin bias circuit96includes P-channel metal oxide semiconductor transistors104,106(or “PMOS” transistors, as known in the art) sized to mirror five (5) microamperes of current from current source107. In an embodiment, transistors104and106are approximately one (1) micrometers by two hundred eighty (280) nanometers and approximately five (5) micrometer by two hundred eighty (280) nanometers, respectively. In an embodiment, when performing margin “0” testing, a 2.0 Volt supply is increased to approximately 2.1 Volts to increase potential leakage current into sensing circuit54(FIG. 5). In an embodiment, current source107is provided for margin “1” testing.

Margin bias circuit96further includes PMOS transistors110and112sized to provide four (4) microamperes and five (5) microamperes of current, respectively. In an embodiment, transistors108and109are provided to turn off currents in transistors110and112after the data is latched in latch92(FIGS. 7a&7b) to save power. In the illustrated embodiment, transistors110and112control the delivery of current via transistors108and109, respectively. In an embodiment, transistors110,112,108and109provide current for normal read, transistor110and108provide current for margin “0” read, and transistors110,108,112,109,104,106and current source107provide current for margin “1” read. It is emphasized that transistors104,106,108,109,110,112merely provide an illustrative embodiment of one way to provide a bias current on bitline26, and that the sizes of transistors104,106,108,109,110,112are selectable based on the circumstances in which they are applied.

FIG. 10is a block diagram of sensing circuit54. Sense amplifiers114are connected to selected bitlines26through multiplexing provided by column multiplexors52and52′ (not shown inFIG. 10), i.e., one sense amp connected to each selected cell10,30in line24,44, respectively. In an embodiment, twenty-two cells10or30in each line24or44, respectively, results in twenty-two sense amplifiers114selected by column decode block56and multiplexors52and52′. Lines116provide control signals and bias current for margin bias circuit96(FIGS. 7a&7b) and pull-up circuit98(FIGS. 7a&7b) to pre-charge each bitline26, provide read operations and margin testing. In an embodiment, latch92, inverter94, margin bias circuit96and pull-up circuit98are components of sensing circuit54.

Under certain circumstances, transients on bitlines26may show up as noise on other bitlines26. Such noise may interfere with the ability of sense amplifier114to detect the data stored in a cell10,30selected for reading. Sense amplifiers may incorporate pre-discharge circuitry to address such an issue. Upon a particular cell10,30having been selected to be read, bitlines26not corresponding to the particular cell10,30to be read may be driven to a predetermined state. In an embodiment, circuitry of sensing circuit54and column multiplexors52and52′ provide pre-discharge of unselected bitlines26. Pre-discharge circuits of sense amplifiers114and multiplexors52and52′ may be configured to drive bitlines26not related to the particular cell10,30to be read to ground before reading the selected cell10,30. In so doing, transients on the bitlines26not corresponding to the selected cell10,30may be avoided and, as a result, noise on the bitline26of the selected cell10,30may be reduced.

FIG. 11is a flowchart for providing a memory array such as memory module50. A plurality of flash memory cells10and ROM memory cells30are provided (1100) on memory module50. In an embodiment, flash memory cells10and ROM memory cells30are fabricated on one or more silicon dies as known in the art. In an embodiment, at least some of flash memory cells10and at least some ROM memory cells30are fabricated on the same silicon die. Addressing circuitry, including at least column decode block56and row decoder70, are provided (1102). In an embodiment, at least some of the addressing circuitry is provided on the same silicon die as the at least some flash memory cells10and ROM memory cells30.

FIG. 12is a flowchart for using a memory array such as memory module50. Addressing circuitry as described above is utilized to address (1200) both flash memory cells10and ROM memory cells30. Reading circuitry, including at least sensing circuit54, reads (1202) both flash memory cells10and ROM memory cells30.

FIG. 13ais a flowchart for operating a memory module such as memory module50. Individual data bits such as memory cells10,30are selectively coupled (1300) to a voltage sensing circuit such as sensing circuits54. Individual ones of the data bits are selective biased (1302) by at least margin bias circuit96and pull-up circuit98. The data state of the data bit is read (1304) based, at least in part, on a voltage of or imparted by the individual one of the plurality of data bits. If the reading (1304) is a margin test, it is determined (1306) whether the voltage corresponds to a correct data state. The margin test may be a margin high test, i.e., a margin “1” test, or a margin low test, i.e., a margin “0” test as detailed above. Margin bias circuit96is utilized to selectively bias (1308) the selected data bit. Bitline26not corresponding to the data bit may be pre-discharged (1310) prior to reading (1304) the data bit and, in an embodiment, each bitline26not corresponding to the data bit is pre-discharged prior to reading (1304) the data bit.

FIG. 13bis an alternative flowchart utilizing essentially the same steps as illustrated inFIG. 13abut which specifies a particular order for the steps ofFIG. 13a, as well as the additional step of pre-charging (1312) selected bitlines26.

Thus, embodiments of the memory array with flash memory cells and ROM memory cells and methods are disclosed. One skilled in the art will appreciate that the present invention can be practiced with embodiments other than those disclosed. The disclosed embodiments are presented for purposes of illustration and not limitation, and the present invention is limited only by the claims that follow.