Device having clock generating capabilities and a method for generating a clock signal

A method for generating a clock signal and a device having clock generating capabilities, the device includes: (i) a first divider, adapted to receive an input clock signal and divide the input clock signal to provide a first clock signal; (ii) a second divider, adapted to receive an input clock signal and divide the input clock signal to provide a second clock signal; wherein the first clock signal is phase shifted in relation to the second clock signal by half an input clock cycle; wherein a delay period of the first divider substantially equals a delay period of the second divider over a large range of delay affecting parameter values; (iii) a reconstruction circuit, connected to the first and second divider circuits, adapted to receive the first and second clock signals and apply a logical operation on the first and second clock signals to provide a reconstructed clock signal; and (iv) a selection circuit, connected to the first divider, second divider and reconstruction circuit, adapted to output an output clock signal in response to a selection signal that indicates whether to output the first clock signal, the second clock signal or the reconstructed clock signal.

FIELD OF THE INVENTION

The present invention relates to methods for generating a clock signal and a device that has clock generating capabilities.

BACKGROUND OF THE INVENTION

Modern integrated circuits include many modules that may require different clock signals. Many clock signals can be generated by dividing an input clock signal by a clock divider in order to provide a lower frequency clock signal. Some clock dividers should also be adapted to provide a non-divided version of an input clock signal.

In order to simplify the design of modules that are connected to the clock divider the provision of the non-divided version of the input clock and any divided version of the input clock signal should be characterized by the same delay period.

FIG. 1illustrates prior art clock divider10. Prior art clock divider10includes clock divider20, bypass path30and selection circuit40. Bypass path30includes a sequence of delay units such as inverters32. Clock divider20includes a sequence of flip-flops22and combinational logic24that form a counter.

Clock divider20and bypass path30receive an input clock signal clkin200. Clock divider20divides clkin200by a division ratio that differs from one. Bypass path30provides a delayed version of clkin200.

Selection logic40outputs an output clock signal (either the delayed version of clkin200or a divided clock signal) to module50.

Bypass path30and clock divider20can introduce the same delay over a very narrow temperature range, a very narrow voltage supply range and over a narrow process variation window.

In most cases bypass path30and clock divider20introduce different delays and the difference between these delays can be hard to predict. The delay difference can affect the manner in which module50operates.

SUMMARY OF THE PRESENT INVENTION

The present invention provides a method and a device as described in the accompanying claims. Specific embodiments of the invention are set forth in the dependent claims. These and other aspects of the invention will be apparent from and elucidated with reference to the embodiments described hereinafter.

DETAILED DESCRIPTION OF THE DRAWINGS

In the following specification, the invention will be described with reference to specific examples of embodiments of the invention. It will, however, be evident that various modifications and changes may be made therein without departing from the broader spirit and scope of the invention as set forth in the appended claims.

It has been found that a bypass path and a clock dividing path can be implemented by using similar components, thus guaranteeing substantially the same delay over a large range or delay affecting parameters such as temperature, supply voltage and process variations.

FIG. 2schematically shows an example of an embodiment of device100that has clock signal generating capabilities.

Device100can have information (data and/or media) processing capabilities. Device100can be a mobile device, such as, but not limited to, a laptop computer, a mobile phone, a media player, a mobile game console and the like. Device100can also be a stationary apparatus such as a desktop computer, a plasma screen, a television, a media entertainment system, a monitoring system, a stationary game console, a network node, a router, a switch, and the like. Device100can include one or more displays, processors, memory units, loudspeakers, microphones, DMA controllers, and the like. Device100can include multiple integrated circuits.

In the example ofFIG. 1, device100includes input clock generator90, first divider110, second divider120, reconstruction circuit130, first delay circuit140, second delay circuit150and selection circuit160.

Selection circuit140can receive a selection signal S208from controller180. Controller180can also determine the division ratios of first and second dividers110and120and program first and second dividers110and120accordingly.

First divider110is adapted to receive input clock signal clkin200and divides it to provide first clock signal clk1201.

Second divider120is adapted to receive input clock signal clkin200and divides it to provide second clock signal clk2202.

First clock signal clk1201is phase-shifted in relation to second clock signal clk2202by half an input clock cycle. This phase shift is denoted Phi207inFIG. 3.

A delay period of first divider110substantially equals a delay period of second divider120over a large range of delay affecting parameter values. The delay affecting parameter can be temperature, supply voltage and any process variation. The large range can include an expected temperature range, an expected supply voltage range and expected process variation ranges or a substantial portion (for example, at least 80%) of each of these ranges.

In the example ofFIG. 1, first divider110includes a positive edge triggered shift register112, first multiplexer116and first control logic114. Second divider120includes negative edge triggered shift register122, second multiplexer118and second control logic116. It is noted that both first and second control logics can be unified to provide a single control unit.

Input ports of first multiplexer116are connected to the output ports of positive edge triggered flip-flops111(1)-111(j) of positive edge triggered shift register112. The output port of first multiplexer116is connected to the input port of first positive edge triggered flip-flop111(1). Positive edge triggered flip-flops111(1)-111(j) are connected in a sequential manner to each other. The output of first divider110can be the output port of first positive edge triggered flip-flop111(1) (as illustrated in the example ofFIG. 1) or the output port of any other flip-flop.

Control logic114can determine, at any given time and in response to the requested division factor, which flip-flop output signal to provide to the input port of first positive edge triggered flip-flop111(1).

Input ports of second multiplexer126are connected to the output ports of negative edge triggered flip-flops121(1)-121(j) of negative edge triggered shift register122. The output port of second multiplexer126is connected to the input port of first negative edge triggered flip-flop121(1). Negative edge triggered flip-flops121(1)-121(j) are connected in a sequential manner to each other. The output of second divider120can be the output port of first negative edge triggered flip-flop121(1) (as illustrated in the example ofFIG. 1) or the output port of any other flip-flop.

Control logic124can determine, at any given time and in response to the requested division factor, which flip-flop output signal to provide to the input port of first negative edge triggered flip-flop121(1).

The generation of reconstructed clock signal clkr203requires both dividers110and120to be active but only one divider can be active or another clock signal (clk1201or clk2202) is required.

Reconstruction circuit130is connected to first and second divider circuits110and120, and is adapted to receive first and second clock signals clk1201and clk2202and to apply a logical operation on these clock signals to provide a reconstructed clock signal clkr203. In the example ofFIG. 2reconstruction circuit130includes XOR gate131. It receives as inputs first and second clock signals clk1201and clk2202and applies a XOR operation on them to provide reconstructed clock signal clkr203.

The output port of first divider110is connected to an input of first delay circuit140. An output port of first delay circuit140is connected to a first input port of selection circuit160to provide a delayed version of first clock signal clk1201.

The output port of second divider120is connected to an input of second delay circuit150. An output port of second delay circuit150is connected to a second input port of selection circuit160to provide a delayed version of second clock signal clk2202.

The delay period of first delay circuit140, second delay circuit150and reconstruction circuit130substantially equal each other over the large range of delay affecting parameter values.

Conveniently, these circuits include the same components—such as the same logic gates. For example, each circuit can include a XOR gate. Wherein first delay circuit140applies a XOR operation on first clock signal clk1201and “0” while second delay circuit150applies a XOR operation on second clock signal clk2202and “0”.

Selection circuit160is connected to first and second delay circuits140and150, reconstruction unit130. It receives selection signal S208from controller180and can select, in response to the value of that selection signal, which clock signal to output. Selection unit160can be a multiplexer.

Device10generates an output clock signal regardless of the division ratio (1 or not) by passing the input clock signal through flip-flops, thus the same delay is expected despite changes in the temperature, supply voltage level of process variations.

The clock signals generated by different paths (first divider110, second divider120) are responsive to edges of the input clock signal and thus are relatively balanced.

Because each clock divider out of clock dividers110and120includes multiple flip-flops but only a single combinational cell (a single multiplexer per clock divider) then high frequency clock signals can be generated.

FIG. 4schematically shows an example of an embodiment of method200for generating a clock signal.

Method200starts by stages210and220. Stage210includes receiving an input clock signal. Stage220includes determining whether to generate a reconstructed clock signal, a first clock signal or a second clock signal and generating a selection signal that is indicative of the selection.

Stage230includes dividing an input clock signal by a first divider to provide a first clock signal. Stage240includes dividing the input clock signal by a second divider to provide a second clock signal. The first clock signal is phase shifted in relation to the second clock signal by half an input clock cycle. A delay period of the first divider substantially equals a delay period of the second divider over a large range of delay affecting parameter values. The delay affecting parameter can be temperature, voltage supply level and process variations.

Stage230can include stage232of dividing the input clock signal by a first divider that includes a positive edge triggered shift register. The positive edge triggered shift register is connected to a control circuit

Stage240can include stage242of dividing the input clock signal by a second divider that includes a negative edge triggered shift register. The negative edge triggered shift register is connected to a control circuit.

Stages230and240are followed by stage250of generating the reconstructed clock signal by applying a logical operation on the first and second clock signals. The reconstructed clock signal has a cycle that equals the input clock cycle.

Conveniently, the reconstructed clock signal is phase shifted in relation to the input clock signal by an insignificant fraction of an input clock cycle.

Stage250can include stage252of generating the reconstructed clock signal by applying a XOR operation on the first and second clock signals.

Stage250is followed by stage260of outputting an output clock signal in response to a selection signal that indicates whether to output the first clock signal, the second clock signal or the reconstructed clock signal.

FIG. 5schematically shows an example of an embodiment of method300for generating a clock signal.

Stage273includes delaying the first clock signal by a first delay circuit that has an output that is connected to an input of the selection unit.

Stage274includes delaying the second clock signal by a second delay circuit that has an output that is connected to an input of the selection unit. A delay period of the first delay circuit substantially equals a delay period of the reconstruction circuit and a delay of the second delay circuit over a large range of delay affecting parameter values.

Stages273and274can be implemented by using delay circuits that are similar to the reconstruction unit and especially can include the same logic gates included in the reconstruction unit.

Stage273can include delaying the first clock signal by a XOR gate that applies a XOR operation on the first clock signal and a constant.

Stage274can include delaying the second clock signal by a XOR gate that applies a XOR operation on the second clock signal and a constant.

The conductors as discussed herein may be illustrated or described in reference to being a single conductor, a plurality of conductors, unidirectional conductors, or bidirectional conductors. However, different embodiments may vary the implementation of the conductors. For example, separate unidirectional conductors may be used rather than bidirectional conductors and vice versa. In addition, plurality of conductors may be replaced with a single conductor that transfers multiple signals serially or in a time-multiplexed manner. Likewise, single conductors carrying multiple signals may be separated out into various different conductors carrying subsets of these signals. Therefore, many options exist for transferring signals.

In addition, the invention is not limited to physical devices or units implemented in non-programmable hardware but can also be applied in programmable devices or units able to perform the desired device functions by operating in accordance with suitable program code. Furthermore, the devices may be physically distributed over a number of apparatuses, while functionally operating as a single device.

The word ‘comprising’ does not exclude the presence of other elements or steps then those listed in a claim. Moreover, the terms “front,” “back,” “top,” “bottom,” “over,” “under” and the like in the description and in the claims, if any, are used for descriptive purposes and not necessarily for describing permanent relative positions. It is understood that the terms so used are interchangeable under appropriate circumstances such that the embodiments of the invention described herein are, for example, capable of operation in other orientations than those illustrated or otherwise described herein.