Precharge switch-capacitor circuit and method

An input sampling stage circuit includes, a precharge buffer, a precharge switch-capacitor circuit, and an input sampling capacitor. The precharge buffer is configured to buffer an input voltage. The precharge switch-capacitor circuit includes a plurality of switches, a first capacitor, and a second capacitor configured such that the first and second capacitors are connected in series during a coarse sampling time and in parallel during a fine sampling time and charge transfer time. The input sampling capacitor is configured to sample the input voltage through the precharge switch-capacitor circuit during the coarse sampling time and sample the input voltage directly during the fine sampling time.

BACKGROUND

A switched-capacitor circuit is an electrical circuit that moves charge into and out of capacitors when switches are closed and opened. An increasing number of modern analog and mixed-signal integrated circuits, such as analog-to-digital converters, amplifiers, and analog filters, use switched-capacitor circuits as basic building blocks. The continued demand for improved performance of such analog and mixed-signal circuits has resulted in more stringent requirements for the switched-capacitor circuits.

SUMMARY

The problems noted above are solved in large part by systems and methods of sampling voltage in a switch-capacitor circuit. In some embodiments, a switch-capacitor circuit includes an input sampling stage circuit and an output stage circuit. The input sampling stage circuit includes a precharge buffer, a precharge switch-capacitor circuit, and an input sampling capacitor. The precharge buffer is configured to buffer an input voltage. The precharge switch-capacitor circuit includes a plurality of switches, a first capacitor, and a second capacitor configured such that the first and second capacitors are connected in series during a coarse sampling time and in parallel during a fine sampling time and charge transfer time. The input sampling capacitor is configured to sample the input voltage through the precharge switch-capacitor circuit during the coarse sampling time and sample the input voltage directly during the fine sampling time.

Another illustrative embodiment is a switch-capacitor circuit that includes an input sampling stage circuit and an output stage circuit. The input stage sampling circuit includes, a precharge buffer, a precharge switch-capacitor circuit, and an input sampling capacitor. The precharge buffer is configured to buffer an input voltage. The precharge switch-capacitor circuit includes a plurality of switches, a first capacitor, and a second capacitor configured such that the first and second capacitors are connected in parallel during a first portion of a coarse sampling time, in series during a second portion of the coarse sampling time, and in parallel during a fine sampling time and charge transfer time. The input sampling capacitor is configured to sample the input voltage through the precharge switch-capacitor circuit during the coarse sampling time and sample the input voltage directly during the fine sampling time.

Yet another illustrative embodiment is an input sampling stage circuit that includes a precharge buffer and a precharge switch-capacitor circuit. The precharge buffer is configured to buffer an input voltage and settle during a fine sampling time and a charge transfer time. The precharge switch-capacitor circuit includes a plurality of switches, a first capacitor, and a second capacitor configured such that an input sampling capacitor samples the input voltage through the precharge switch-capacitor circuit during the coarse sampling time. The plurality of switches, first capacitor, and second capacitor are also configured such that the input sampling capacitor samples the input voltage directly during the fine sample time. The plurality of switches, first capacitor, and second capacitor are also configured such that the input sampling capacitor discharges stored charge to an output stage circuit during the charge transfer time.

NOTATION AND NOMENCLATURE

DETAILED DESCRIPTION

The fundamental problem which often limits precision in switched-capacitor circuits is the effect of loading from the input circuitry. Faster sampling frequency and/or a larger input sampling capacitor in the input stage of some conventional switched-capacitor circuits results in lower input impedance. Ideally, the no load voltage produced by the input circuitry and the voltage at the input of the switched-capacitor circuit is equal. However, due to the input circuitry impedance and the switched-capacitor circuit input impedance the voltages are not equal. Instead an error term causes the no-load voltage to not equal the voltage at the input of the switched-capacitor circuit. This error term limits the accuracy of three important performance metrics: 1) gain error, 2) gain error temperature drift, and 3) non-linearity.

To improve input impedance of the switched-capacitor circuit and thereby improve the above listed performance metrics, some conventional switched-capacitor circuits include a precharge buffer. In these circuits, the input voltage is first “coarse” sampled during a first phase on a sampling capacitor through the precharge buffer and a coarse sampling switch. Immediately following this first phase, the input voltage is directly “fine” sampled during a second phase on the sampling capacitor through a second fine sampling switch. The charge stored on the sampling capacitor during the coarse and fine sampling phases is then transferred during a third phase to an output stage circuit. This process repeats itself over a sampling period. In a typical conventional switched-capacitor circuit, approximately 50% of the sampling period is allotted to the sampling phases (the first and second phases) while 50% of the sampling period is allotted to the charge transfer phase (the third phase). Furthermore, the fine sampling phase (the second phase) is approximately three times longer than the coarse sampling phase (the first phase) in the typical conventional switched-capacitor circuit so that the fine sampling process has sufficient time to settle to the required accuracy. Because these circuits utilize a precharge buffer to coarse charge the sampling capacitor to a precharge buffer output approximately equal in value to the input voltage, these circuits provide higher input impedance. However, these circuits have a much higher power dissipation arising from the need to quickly settle the precharge buffer output during the short duration of the coarse sampling phase. In fact, there is a direct relationship between the precharge buffer power dissipation and the fraction of the sampling period allotted to precharge buffer settling. The higher the percentage (fraction) of the sampling period allotted to the precharge buffer settling, the lower the precharge buffer power dissipation. Therefore, it is desirable to develop a switched-capacitor circuit that has a longer percentage of the sampling period allotted to precharge buffer settling while maintaining a high input impedance.

FIG. 1shows an illustrative block diagram of analog-to-digital system100that includes a switch-capacitor circuit104in accordance with various embodiments. The analog-to-digital system100includes the analog-to-digital converter (ADC)102which includes the switch-capacitor circuit104. In some embodiments, ADC102is configured to receive an analog input signal122and convert the analog input signal122into digital output signal124. ADC converter102may be any type of ADC including a direct-conversion ADC, a ramp-compare ADC, an integrating ADC, a pipeline ADC, a delta-sigma ADC, a successive-approximation ADC, and/or a time-interleaved ADC. The ADC102may include switch-capacitor circuit104. Switch-capacitor circuit104is configured to sample the analog input signal122and then transfer the resulting charge to a subsequent stage so that the analog signal may be converted into a digital signal. While switch-capacitor circuit104is shown as being included in ADC102, in other embodiments, switch-capacitor circuit104may be included in other analog and/or mixed-signal integrated circuits such as an amplifier and/or an analog filter.

FIG. 2Ashows an illustrative circuit diagram of switch-capacitor circuit104in accordance with various embodiments. InFIG. 2A, the switch-capacitor circuit104is in a single-ended configuration. Switch-capacitor circuit104may include a single-ended switch capacitor input sampling stage circuit202and a single-ended switch capacitor output stage circuit204. The output stage circuit204is representative of the internal discharging process within a larger circuit block such as an integrator, amplifier, or filter. The actual circuitry inside output stage circuit204may be different, but the net effect may be the same as shown inFIG. 2A.

The single-ended switch capacitor input sampling stage circuit202may include a precharge buffer206, a precharge switch-capacitor circuit208a fine sampling switch226, and an input sampling capacitor210. The precharge buffer206may include a buffer amplifier configured to buffer an input voltage Vi. In other words, the precharge buffer206is configured to provide electrical impedance transformation of the signal Vi and output the voltage Vib. The precharge switch-capacitor circuit208may include the switches212-216, the capacitor connecting switch218, the coarse sampling switch224, and capacitors220and222.

The single-ended configuration shown inFIG. 2Afirst samples the precharge buffer output Vib on the switch-capacitor circuit208capacitors220and222through switches212,214, and216for the duration of phase P3(the time that the input sampling capacitor210is not coarse sampling; i.e., during the fine sampling time and charge transfer time). Thus, during the duration of P3, switches212-216are closed. A portion of the charge stored on capacitors220and222is then transferred to input sampling capacitor210through coarse sampling switch224and capacitor connecting switch218during a coarse sampling time (“phase P1c”). Thus, during P1c, coarse sampling switch224and capacitor connecting switch218are closed while switches212-216, fine sampling switch226, and modeling switch228of the output stage circuit204are open. Hence, the capacitors220and222are connected in series during P1c. The input voltage Vi is then fine sampled during fine sampling time (“phase P1f”) on the input sampling capacitor210through fine sampling switch226for the duration of phase P1f. Thus, during P1f, the fine sampling switch226and switches212-216are closed while coarse sampling switch224, capacitor connecting switch218, and modeling switch228of the output stage circuit204are open. Hence, the capacitors220and222are connected in parallel during P1f. The charge stored on input sampling capacitor210during the coarse and fine sampling process is then transferred during charge transfer time (“phase P2”) to the output stage modeled by switch228. Thus, during phase P2, the modeling switch228of the output stage circuit204and switches212-216are closed while the fine sampling switch226, coarse sampling switch224, and capacitor connecting switch218are open. This coarse/fine sampling and charge transfer process repeats with sampling period (ts).

FIG. 2Bshows an illustrative circuit diagram of switch-capacitor circuit104in accordance with various embodiments. InFIG. 2B, the switch-capacitor circuit104is in a differential mode configuration. Switch-capacitor circuit104may include a differential switch capacitor input sampling stage circuit252and a differential switch capacitor output stage circuit254. The output stage circuit254is representative of the internal discharging process within a larger circuit block such as an integrator, amplifier, or filter. The actual circuitry inside output stage circuit254may be different, but the net effect may be the same as shown inFIG. 2B.

The differential switch capacitor input sampling stage circuit252may include a precharge buffer256, a precharge switch-capacitor circuit258, fine sampling switches276and284, input sampling capacitors260and290, and switches280,282, and283. The precharge buffer256may include two buffer amplifiers. One of the buffer amplifiers is configured to buffer an input voltage Vip. In other words, one of the buffer amplifiers of precharge buffer256is configured to provide electrical impedance transformation of the signal Vip and output the voltage Vibp. The second of the buffer amplifiers is configured to buffer an input voltage Vin. In other words, the second of the buffer amplifiers of precharge buffer256is configured to provide electrical impedance transformation of the signal Vin and output the voltage Vibn. The voltages Vip and Vin may be differential voltages. Hence, the voltages Vip and Vin may be a pair of the same voltage signal, except that the differential pair of signals are 180 degrees out of phase with each other. Thus, the amplitude of the two signals Vip and Vin that make up the differential voltage is the same; however, the phase of the two signals is different. Therefore, the voltage Vip may be referred to as a positive input voltage and the voltage Vin may be referred to as a negative input voltage. Similarly, the buffer amplifier output voltages Vibp and Vibn may be differential voltages. The precharge switch-capacitor circuit258may include the switches262-266and286, the capacitor connecting switch268, the coarse sampling switches274and288, and capacitors270and272.

The differential configuration shown inFIG. 2Bfirst samples the precharge buffer output (Vibp and Vibn) on precharge switch-capacitor circuit258capacitors270and272through switches262,264,266, and286for the duration of phase P3. Thus, during the duration of P3, switches262-266and286are closed. A portion of the charge stored on capacitors270and272is then transferred to input sampling capacitors260and290through coarse sampling switches274and288, capacitor connecting switch268, and switches280and282during the coarse sampling time (phase P1c). Thus, during P1c, coarse sampling switches274and288, capacitor connecting switch268, and switches280and282are closed while switches262-266,286, and283, fine sampling switches276and284, and modeling switches278and298of the output stage circuit254are open. Hence, the capacitors270and272are connected in series during P1c. The input (Vip and Vin) is then fine sampled during the fine sampling time (phase P1f) on the input sampling capacitors260and290through fine sampling switches276and284and switches280and282for the duration of phase P1f. Thus, during P1f, the fine sampling switches276and284and switches262-266,286,280, and282are closed while coarse sampling switches274and288, capacitor connecting switch268, switch283, and modeling switches278and298of the output stage circuit254are open. Hence, the capacitors270and272are connected in parallel during P1f. The charge stored on input sampling capacitors260and290during the coarse and fine sampling process is then transferred during the charge transfer time (phase P2) to the output stage circuit254modeled by switches283,278, and298. Thus, during phase P2, the modeling switches278and298of the output stage circuit254and switches262-266,286, and283are closed while the fine sampling switches276and284, coarse sampling switches274and288, capacitor connecting switch268, and switches280and282are open. This coarse/fine sampling and charge transfer process repeats with sampling period (ts).

FIG. 3shows an illustrative timing diagram300of switch timing for switches in switch-capacitor circuit104in accordance with various embodiments. More particularly, the timing diagram300shows the timing of when the various phases discussed above occur. A HIGH signal in timing diagram300indicates that the corresponding phase is occurring and, thus, the switches are closed or open as discussed above. As shown in timing diagram300, the switch-capacitor circuit104goes through three cycles (cycles1,2, and3). The three cycles correspond with times when the switches may open or close. For example, cycle1corresponds to phase2(the charge transfer time when charge stored on the input sampling capacitor210fromFIG. 2Aand/or input sampling capacitors260and290fromFIG. 2Bis transferred to the output stage circuit). In addition to corresponding to phase2, cycle1also corresponds with phase3(the time the precharge buffer206fromFIG. 2A and 256fromFIG. 2Bsettles) because phase3occurs at all times except during the coarse sampling time. Cycle1lasts for a duration that may be defined by (m−n)·ts where ts is sampling period, m is the percent of the sampling period that a precharge buffer is settling (i.e., the percent of the sampling period that includes phase3), and n is the percent of the sampling period that includes the fine sampling time (i.e., the percent of the sampling period that includes P1f).

Cycle2corresponds with P1c(the coarse sampling time). In addition to corresponding to P1c, cycle2also corresponds with phase1(the time that voltage is being sampled onto the input sampling capacitor210fromFIG. 2Aor input sampling capacitors260and290fromFIG. 2B). Cycle2lasts for a duration that may be defined by (1−m)·ts. Cycle3corresponds with P1f(the fine sampling time). In addition to corresponding to P1f, cycle3also corresponds with phase1and phase3. Cycle3lasts for a duration that may be defined by n·ts. By providing suitable switch timing which allows for the precharge buffer to settle its output for much larger fraction of sampling period (m), switch-capacitor circuit104provides the benefit of increasing the input impedance of the switched-capacitor circuit while at the same time minimizing the power dissipation of the precharge buffer.

FIG. 4shows an illustrative block diagram of time events402-408and associated states of capacitor voltages and charges in a switch-capacitor circuit104described inFIGS. 2A and 2Bin accordance with various embodiments. For proper operation of the switch-capacitor circuit104, it is necessary to size the capacitors220-222correctly relative to the input sampling capacitor210fromFIG. 2Aand the capacitors270-272correctly relative to input sampling capacitors260and290fromFIG. 2B. There are four separate time events402-408and associated states of all capacitor voltages and charges. For simplification, the following substitutions are used throughout the discussion ofFIG. 4which focuses on the differential design shown inFIG. 2B: C270(capacitance of capacitor270)=C272(capacitance of capacitor272)=Cs and C260(capacitance of capacitor260)=C290(capacitance of capacitor290)=Ci.

First event402is at the end of cycle1during which equivalent capacitor 2·Cs (as capacitors270and272are in parallel) has sampled precharge buffer output voltage Vib and equivalent capacitor 0.5·Ci (as the capacitors260and290are in series) has been discharged by the output stage circuit to 0V. The charges on the capacitors are:
Q1=2·Cs·Vib(1)
Q2=0  (2)
where Q1 is the charge on the equivalent capacitor 2·Cs and Q2 is the charge on the equivalent capacitor 0.5·Ci at the end of cycle1.

Second event404is at the beginning of cycle2during which capacitors270and272have been connected in series due to the switching discussed above and the resulting equivalent capacitor 0.5·Cs has voltage of 2·Vib across its terminals and has a charge of:
Q3=Cs·Vib(3)

Third event406is at the end of cycle2during which equivalent capacitors 0.5·Cs and 0.5·Ci have been connected in parallel and the desired voltage Vib is assumed across them. The charges on the capacitors are:
Q4=0.5·Cs·Vib(4)
Q5=0.5·Ci·Vib(5)
where Q4 is the charge on the equivalent capacitor 0.5·Cs and Q5 is the charge on the equivalent capacitor 0.5·Ci at the end of cycle2. From the charge conservation principle:
Q3+Q2=Q4+Q5  (6)
Substituting Equations 2-5 in Equation 6 and simplifying results in:
Cs=Ci(7)
Thus, the capacitors270and272are equal in capacitance to input sampling capacitors260and290. Hence, C270=C272=C260=C290.

Fourth event408is at the end of cycle3during which the equivalent input-sampling capacitor 0.5·Ci has finished the fine sampling process. At this time the equivalent 2·Cs capacitor is still settling from Vib/2 to Vib.

Applying the above analysis (Equations 1-6) to the single-ended configuration ofFIG. 2Aresults in the same relative capacitances of the capacitors220-222and half the input sampling capacitor210. Thus, because there is only a single input sampling capacitor, C220=C222=0.5·C210

Since the coarse sampling phase P1conly involves capacitor charge re-distribution (i.e., it only involves capacitors and switches), coarse sampling can be done in very short amount of time, in some embodiments in about 0.05·ts. This leaves a much longer time, in some embodiments about 0.95·ts, for precharge buffer settling during phase3. Since the precharge buffer settling time is increased in comparison to the precharge buffer settling time of the conventional switch-capacitor circuit (typically about 0.125·ts), precharge buffer power dissipation can be reduced by a factor of approximately 14. Furthermore, the fine sampling phase is also lengthened, in some embodiments to approximately 0.45·ts from the conventional switch-capacitor circuit fine sampling time (typically about 0.375·ts) providing a 20% increase in fine sampling time.

Peak voltage (VPEAK) of 2·Vib across series-connected capacitors220-222fromFIG. 2Aand capacitors270-272fromFIG. 2Bis used at the beginning of cycle2. VPEAK=2·Vib has been used to simplify the calculations in Equations 3-7. In a real switch-capacitor circuit104, VPEAK=2·Vib represents an upper limit value of the voltage. One technique to minimize VPEAKis to sequence the timing of switching (shown inFIG. 3) such that the rising edge of phase P1coccurs after the rising edge of phase P1. A second technique to minimize VPEAKis to design the switches such that the RON (S274+S288+S280+S282)≈RON (S268), where RON refers to switch on-resistance. Even with both of these techniques applied, practical implementation of switch-capacitor circuit104shown inFIGS. 2A-2Bmay not be able to the reduce VPEAKfactor by more than about 0.75 and consequently VPEAK≈0.75·2·Vib. Practical implementations of the switch-capacitor circuits104ofFIGS. 2A and 2Btherefore have VPEAK≈1.5·Vib. Peak voltages which are more than diode turn-on voltage above VDDwill turn on the normally reverse-biased diodes found in PMOS devices that may form the switches which are exposed to VPEAK≈1.5·Vib. These turned-on diodes will then leak some of the charge stored on capacitors220-222fromFIG. 2Aand capacitors270-272fromFIG. 2Bto VDDrail and thus degrade the circuit performance.

FIG. 5Ashows an illustrative circuit diagram of switch-capacitor circuit104in accordance with various embodiments. InFIG. 5A, the switch-capacitor circuit104is in a single-ended configuration. Switch-capacitor circuit104may include a single-ended switch capacitor input sampling stage circuit502and a single-ended switch capacitor output stage circuit504. The output stage circuit504is representative of the internal discharging process within a larger circuit block such as an integrator, amplifier, or filter. The actual circuitry inside output stage circuit504may be different, but the net effect may be the same as shown inFIG. 5A.

The single-ended switch capacitor input sampling stage circuit502may include a precharge buffer506, a precharge switch-capacitor circuit508a fine sampling switch526, and an input sampling capacitor510. The precharge buffer506may include a buffer amplifier configured to buffer an input voltage Vi. In other words, the precharge buffer506is configured to provide electrical impedance transformation of the signal Vi and output the voltage Vib. The precharge switch-capacitor circuit508may include the switches512-516, the capacitor connecting switch518, the coarse sampling switch524, switches530and534, and capacitors520and522.

In contrast to circuit ofFIG. 2A, which transfers the required charge from capacitor220and222to input sampling capacitor210in a single step during phase P1c, the single-ended precharge switch-capacitor circuit508ofFIG. 5Atransfers the required charge from capacitors520and522to input sampling capacitor510in two separate steps. The first step, which occurs during a subset of the coarse sampling time (phase P1ca), transfers the first portion of the charge from parallel-connected capacitors520and522to input sampling capacitor510through coarse sampling switch524and switches530and534. The second step, which occurs during a second subset of the coarse sampling time (phase P1cb), transfers the second portion of the charge from series-connected capacitors520and522to input sampling capacitor510through coarse sampling switch524and capacitor connecting switch518.

The single-ended configuration shown inFIG. 5Afirst samples the precharge buffer output Vib on the switch-capacitor circuit508capacitors520and522through switches512,514, and516for the duration of phase P3(the time that the input sampling capacitor510is not coarse sampling; i.e., during the fine sampling time and charge transfer time). Thus, during the duration of P3, switches512-516are closed. A first portion of the charge stored on capacitors520and522is then transferred to input sampling capacitor510through coarse sampling switch524and switches530and534during a phase P1ca. Thus, during P1ca, coarse sampling switch524and switches530and534are closed while switches512-516, capacitor connecting switch518, fine sampling switch526, and modeling switch528of the output stage circuit504are open. Hence, the capacitors520and522are connected in parallel during P1ca. A second portion of the charge from capacitors520and522is then transferred to input sampling capacitor510through coarse sampling switch524and capacitor connecting switch518during phase P1cb. Thus, during P1cb, coarse sampling switch524and connecting capacitor switch518are closed while switches512-516,530, and534, fine sampling switch526, and modeling switch528of the output stage circuit504are open. Hence, the capacitors520and522are connected in series during P1cb. The input voltage Vi is then fine sampled during fine sampling time (“phase P1f”) on the input sampling capacitor510through fine sampling switch526for the duration of phase P1f. Thus, during P1f, the fine sampling switch526and switches512-516are closed while coarse sampling switch524, capacitor connecting switch518, switches530and534, and modeling switch528of the output stage circuit504are open. Hence, the capacitors520and522are connected in parallel during P1f. The charge stored on input sampling capacitor510during the coarse and fine sampling process is then transferred during charge transfer time (“phase P2”) to the output stage modeled by switch528. Thus, during phase P2, the modeling switch528of the output stage circuit504and switches512-516are closed while the fine sampling switch526, coarse sampling switch524, capacitor connecting switch518, and switches530and534are open. This coarse/fine sampling and charge transfer process repeats with sampling period (ts).

FIG. 5Bshows an illustrative circuit diagram of switch-capacitor circuit104in accordance with various embodiments. InFIG. 5B, the switch-capacitor circuit104is in a differential mode configuration. Switch-capacitor circuit104may include a differential switch capacitor input sampling stage circuit552and a differential switch capacitor output stage circuit554. The output stage circuit554is representative of the internal discharging process within a larger circuit block such as an integrator, amplifier, or filter. The actual circuitry inside output stage circuit554may be different, but the net effect may be the same as shown inFIG. 5B.

The differential switch capacitor input sampling stage circuit552may include a precharge buffer556, a precharge switch-capacitor circuit558, fine sampling switches576and584, input sampling capacitors560and590, and switches580,582, and583. The precharge buffer556may include two buffer amplifiers. One of the buffer amplifiers is configured to buffer an input voltage Vip. In other words, one of the buffer amplifiers of precharge buffer556is configured to provide electrical impedance transformation of the signal Vip and output the voltage Vibp. The second of the buffer amplifiers is configured to buffer an input voltage Vin. In other words, the second of the buffer amplifiers of precharge buffer556is configured to provide electrical impedance transformation of the signal Vin and output the voltage Vibn. The voltages Vip and Vin may be differential voltages. Hence, the voltages Vip and Vin may be a pair of the same voltage signal, except that the differential pair of signals are 180 degrees out of phase with each other. Thus, the amplitude of the two signals Vip and Vin that make up the differential voltage is the same; however, the phase of the two signals is different. Therefore, the voltage Vip may be referred to as a positive input voltage and the voltage Vin may be referred to as a negative input voltage. Similarly, the buffer amplifier output voltages Vibp and Vibn may be differential voltages. The precharge switch-capacitor circuit558may include the switches562-566,586,588, and594, the capacitor connecting switch568, the coarse sampling switches574and592, and capacitors570and572.

In contrast to circuit ofFIG. 2B, which transfers the required charge from capacitor270and272to input sampling capacitors260and290in a single step during phase P1c, the differential precharge switch-capacitor circuit558ofFIG. 5Btransfers the required charge from capacitors570and572to input sampling capacitors560and590in two separate steps. The first step, which occurs during a subset of the coarse sampling time (phase P1ca), transfers the first portion of the charge from parallel-connected capacitors570and572to input sampling capacitors560and590through coarse sampling switches574and592and switches588,594,580, and582. The second step, which occurs during a second subset of the coarse sampling time (phase P1cb), transfers the second portion of the charge from series-connected capacitors570and572to input sampling capacitors560and590through coarse sampling switches574and592, capacitor connecting switch568, and switches580and582.

The differential configuration shown inFIG. 5Bfirst samples the precharge buffer output (Vibp and Vibn) on precharge switch-capacitor circuit558capacitors570and572through switches562,564,566, and586for the duration of phase P3. Thus, during the duration of P3, switches562-566and586are closed. A first portion of the charge stored on capacitors570and572is then transferred to input sampling capacitors560and590through coarse sampling switches574and592and switches588,594,580, and582during P1ca. Thus, during P1ca, coarse sampling switches574and592and switches588,594,580, and582are closed while switches562-566,586, and583, fine sampling switches576and584, capacitor connecting switch568, and modeling switches578and598of the output stage circuit554are open. Hence, the capacitors570and572are connected in parallel during P1ca. A second portion of the charge from capacitors570and572is then transferred to input sampling capacitors560and590through coarse sampling switches574and592, capacitor connecting switch568, and switches580and582during phase P1cb. Thus, during P1cb, coarse sampling switches574and592capacitor connecting switch568, and switches580and582are closed while switches562-566,586,583,588and594, fine sampling switches576and584, and modeling switches578and598of the output stage circuit554are open. Hence, the capacitors570and572are connected in series during P1cb. The input (Vip and Vin) is then fine sampled during the fine sampling time (phase P1f) on the input sampling capacitors560and590through fine sampling switches576and584and switches580and582for the duration of phase P1f. Thus, during P1f, the fine sampling switches576and584and switches562-566,586,580, and582are closed while coarse sampling switches574and592, capacitor connecting switch568, switches583,588, and594, and modeling switches578and598of the output stage circuit554are open. Hence, the capacitors570and572are connected in parallel during P1f. The charge stored on input sampling capacitors560and590during the coarse and fine sampling process is then transferred during the charge transfer time (phase P2) to the output stage circuit554modeled by switches583,578, and598. Thus, during phase P2, the modeling switches578and598of the output stage circuit554and switches562-566,586, and583are closed while the fine sampling switches576and584, coarse sampling switches574and592, capacitor connecting switch568, and switches580,582,588, and594are open. This coarse/fine sampling and charge transfer process repeats with sampling period (ts).

FIG. 6shows an illustrative timing diagram600of switch timing for switches in switch-capacitor circuit104in accordance with various embodiments. More particularly, the timing diagram600shows the timing of when the various phases discussed above occur. A HIGH signal in timing diagram600indicates that the corresponding phase is occurring and, thus, the switches are closed or open as discussed above. As shown in timing diagram600, the switch-capacitor circuit104goes through three cycles (cycles1,2, and3). The three cycles correspond with times when the switches may open or close. For example, cycle1corresponds to phase2(the charge transfer time when charge stored on the input sampling capacitor510fromFIG. 5Aand/or input sampling capacitors560and590fromFIG. 5Bis transferred to the output stage circuit). In addition to corresponding to phase2, cycle1also corresponds with phase3(the time the precharge buffer506fromFIG. 5A and 556fromFIG. 5Bsettles) because phase3occurs at all times except during the coarse sampling time. Cycle1lasts for a duration that may be defined by (m−n)·ts where ts is sampling period, m is the percent of the sampling period that a precharge buffer is settling (i.e., the percent of the sampling period that includes phase3), and n is the percent of the sampling period that includes the fine sampling time (i.e., the percent of the sampling period that includes P1f).

Cycle2includes two subset cycles,2aand2b. Cycle2acorresponds with P1ca(the first step of the coarse sampling time). In addition to corresponding to P1ca, cycle2aalso corresponds with phase1(the time that voltage is being sampled onto the input sampling capacitor510fromFIG. 5Aor input sampling capacitors560and590fromFIG. 5B) and P1c. Cycle2bcorresponds with P1cb(the second step of the coarse sampling time). In addition to corresponding to P1cb, cycle2balso corresponds with phase1and P1c. Cycle2lasts for a duration that may be defined by (1−m)·ts. Cycle3corresponds with P1f(the fine sampling time). In addition to corresponding to P1f, cycle3also corresponds with phase1and phase3. Cycle3lasts for a duration that may be defined by n·ts. By providing suitable switch timing which allows for the precharge buffer to settle its output for much larger fraction of sampling period (m), switch-capacitor circuit104provides the benefit of increasing the input impedance of the switched-capacitor circuit while at the same time minimizing the power dissipation of the precharge buffer.

FIG. 7shows an illustrative block diagram of time events702-710and associated states of capacitor voltages and charges in a switch-capacitor circuit104described inFIGS. 5A and 5Bin accordance with various embodiments. For proper operation of the switch-capacitor circuit104, it is necessary to size the capacitors520-522correctly relative to the input sampling capacitor510fromFIG. 5Aand the capacitors570-572correctly relative to input sampling capacitors560and590fromFIG. 5B. There are five separate time events702-710and associated states of all capacitor voltages and charges. For simplification, the following substitutions are used throughout the discussion ofFIG. 7which focuses on the differential design shown inFIG. 5B: C570(capacitance of capacitor570)=C572(capacitance of capacitor572)=Cs and C560(capacitance of capacitor560)=C590(capacitance of capacitor590)=Ci.

First event702is at the end of cycle1during which equivalent capacitor 2·Cs (as capacitors570and572are in parallel) has sampled precharge buffer output voltage Vib and equivalent capacitor 0.5·Ci (as the capacitors560and590are in series) has been discharged by the output stage circuit to 0V. The charges on the capacitors are:
Q1=2·Cs·Vib(8)
Q2=0  (9)
where Q1 is the charge on the equivalent capacitor 2·Cs and Q2 is the charge on the equivalent capacitor 0.5·Ci at the end of cycle1.

Second event704is at the end of cycle2aduring which a portion of the charge from the parallel-connected capacitors570and572, with an equivalent value of 2·Cs, has been transferred to equivalent capacitor 0.5·Ci (as the capacitors560and590are in series). This results in an intermediate voltage Vx across equivalent capacitors 2·Cs and 0.5·Ci. The resulting charges are:
Q3=2·Cs·Vx(10)
Q4=0.5·Ci·Vx(11)
where Q3 is the charge on the equivalent capacitor 2·Cs and Q4 is the charge on the equivalent capacitor 0.5·Ci at the end of cycle2a. From the charge conservation principle:
Q1+Q2=Q3+Q4  (12)
Substituting Equations 8-11 in Equation 12 and solving for Vx results in:
Vx=2·Cs/2·Cs+0.5·Ci·Vib(13)

Third event706is at the beginning of cycle2bduring which capacitors570and572have been connected in series with an equivalent capacitor value of 0.5·Cs. The voltage across the equivalent capacitor 0.5·Cs is 2·Vx with a resulting charge of:
Q5=Cs·Vx(14)

Fourth event708is at the end of cycle2bduring which equivalent capacitors 0.5·Cs and 0.5·Ci have been connected in parallel and the desired voltage Vib is assumed across them. The charges on the capacitors are:
Q6=0.5·Cs·Vib(15)
Q7=0.5·Ci·Vib(16)
where Q6 is the charge on the equivalent capacitor 0.5·Cs and Q7 is the charge on the equivalent capacitor 0.5·Ci at the end of cycle2b. From the charge conservation principle:
Q5+Q4=Q6+Q7  (17)
Substituting Equations 11, 13-16 in Equation 17 and solving for Cs results in:
Cs=0.6404·Ci(18)
Thus, the capacitors570and572are equal in capacitance to each other and approximately 0.6404 times the capacitance of input sampling capacitors560and590. In other words, the capacitors570and572are approximately 64% the capacitance of capacitors560and590. Substituting Equation 18 in Equation 13 and solving for Vx results in:
Vx=0.7192·Vib(19)

Fifth event710is at the end of cycle3during which the equivalent input-sampling capacitor 0.5·Ci has finished the fine sampling process. At this time the equivalent 2·Cs capacitor is still settling from Vib/2 to Vib.

Applying the above analysis (Equations 8-17) to the single-ended configuration ofFIG. 5Aresults in the same relative capacitances of the capacitors520-522and half the input sampling capacitor510. Thus, because there is only a single input sampling capacitor, C520=C522=0.5·0.6404·C510.

Peak voltage (VPEAK) of 2·Vx across series-connected capacitors520-522fromFIG. 5Aand capacitors570-572fromFIG. 5Bis used at the beginning of cycle2b. VPEAK=2·Vx has been used to simplify the calculations in Equations 14-19. In a real switch-capacitor circuit104, as shown inFIG. 5B, VPEAK=2·Vx represents an upper limit value of the voltage which would be approached when RON (S574+S592+S580+S582)>>RON (S568), where RON refers to switch on-resistance. However, since it is desirable to minimize VPEAK, the circuit ofFIG. 5Bis normally designed such that RON (S574+S592+S580+S582)≈RON (S568). Practical implementation ofFIG. 5Bdesign may, in an embodiment, result in VPEAKreduction factor of about 0.75 and therefore VPEAK≈0.75·2·Vx, where Vx≈0.72·Vib (Equation 19). Practical implementations of switch-capacitor circuit104ofFIGS. 5A and 5B, therefore, have VPEAK≈1.08·Vib. As discussed above, for a system requiring full-scale input Vi to be close to, equal to, or slightly above VDD, potential charge leakage is prevented. Even though VPEAKis still slightly above Vib, it is not sufficiently high to cause charge leakage. For example, consider a system which requires full-scale input Vi=VDD=5V. In this system VPEAK≈1.08·5V≈5.4V, VPEAKexceeds VDDby about 0.4V which is not sufficient to cause charge leakage from PMOS switch diodes with typical turn-on voltage in 0.6V to 0.7V range.

Similar to the switch-capacitor circuit104shown inFIGS. 2A and 2B, the switch-capacitor circuit104inFIGS. 5A and 5Bprovides a much longer time, in some embodiments about 0.95·ts, for precharge buffer settling during phase3. Since the precharge buffer settling time is increased in comparison to the precharge buffer settling time of the conventional switch-capacitor circuit (typically about 0.125·ts), precharge buffer power dissipation can be reduced by a factor of approximately 14. Furthermore, the fine sampling phase is also lengthened, in some embodiments to approximately 0.45·ts from the conventional switch-capacitor circuit fine sampling time (typically about 0.375·ts) providing a 20% increase in fine sampling time. Additionally, because the capacitors520-522may be smaller than 0.5 times the input sampling capacitor510fromFIG. 5Aand capacitors570-572fromFIG. 5Bmay be smaller than the input sampling capacitors560and590, a smaller silicon area, in some embodiments, approximately 36%, may be achieved in comparison to the switch-capacitor circuit104inFIGS. 2A and 2B.