Semiconductor device and inverter

In an embodiment, a semiconductor device is provided that includes a lateral transistor device having a source, a drain and a gate, and a monolithically integrated capacitor coupled between the gate and the drain.

BACKGROUND

To date, transistors used in power electronic applications have typically been fabricated with silicon (Si) semiconductor materials. Common transistor devices for power applications include Si CoolMOS®, Si Power MOSFETs, and Si Insulated Gate Bipolar Transistors (IGBTs). Group III nitride-based semiconductor devices, such as gallium nitride (GaN) devices, are now emerging as attractive candidates to carry large currents, support high voltages and to provide very low on-resistance and fast switching times.

In some applications, such as inverters, it would be useful to be able to control the turn on/turn off speed, that is the dv/dt or slew rate, to a target value. For silicon transistors, a gate resistor is typically used to control the switching speed. Active gate control has also been used in silicon devices to control and slow down dv/dt. It would also be desirable to be able to control the slew rate in other types of semiconductor devices, such as Group III nitride-based transistor devices.

SUMMARY

According to the invention, a semiconductor device is provided that comprises a lateral transistor device having a source, a drain and a gate, and a monolithically integrated capacitor coupled between the gate and the drain. The semiconductor device comprises a reverse transfer capacitance Crss, wherein Crss(Vds=0V)/Crss(Vds=400V)<50

In some embodiments, the lateral transistor device is a III-V semiconductor transistor device, such as a Group III nitride-based transistor device, for example a Group III nitride-based High Electron Mobility Transistor.

In some embodiments, the semiconductor device comprises a semiconductor body having a first surface, the lateral transistor device comprises a source finger electrode, a drain finger electrode and a gate finger electrode arranged on the first surface of the semiconductor body, the gate finger electrode being arranged laterally between the source finger electrode and the drain finger electrode, and a metallization structure arranged on the first surface, and the capacitor is integrated into the metallization structure and coupled between the gate finger electrode and the drain finger electrode.

In some embodiments, the capacitor is formed on the first surface and comprises a first plate formed from a first conductive layer of the metallization structure, a second plate formed from a second conductive layer of the metallization structure, the first and second conductive layers being spaced apart from another by a first insulation layer of the metallization structure.

In some embodiments, the lateral transistor device comprises an active area that contributes to current switching and the capacitor is positioned laterally adjacent to the active area.

In some embodiments, the capacitor is arranged on the first surface laterally adjacent the source finger electrode, the drain finger electrode and the gate finger electrode.

In some embodiments, the first plate of the capacitor extends from a gate runner formed from the first conductive layer, the gate runner being electrically coupled to the gate finger electrodes or the first plate extends from a gate pad formed from the first conductive layer, the gate pad being electrically coupled to the gate finger electrode, and the second plate of the capacitor extends from a drain bus formed from the second conductive layer, the drain bus being electrically coupled to the drain finger electrode.

In some embodiments, the lateral transistor device comprises an active area that contributes to current switching and the capacitor is positioned above the active area.

In some embodiments, the capacitor is arranged at least partially above the source finger electrode.

In some embodiments, the metallization structure further comprises a third conductive layer, the third conductive layer comprising a source finger arranged on the source finger electrode, a drain finger arranged on the drain finger electrode, and a gate runner that is positioned laterally adjacent the gate finger electrode, the source finger electrode and the drain finger electrode. The first conductive layer is arranged above the source finger and is insulated from the source finger by a second insulation layer.

In some embodiments, the second conductive layer comprises alternate drain and source buses that are arranged vertically above the source finger and the drain finger and extend substantially perpendicularly to the source finger and the drain finger. The source finger is coupled to the source bus by a first conductive via extending through the first insulation layer, and the drain finger is coupled to the drain bus by a second conductive via extending through the first insulation layer.

In some embodiments, the semiconductor device further comprises a third insulation layer that is positioned between the source finger and the drain finger of the third conductive layer and a fourth insulation layer arranged on the first surface that extends between the source finger electrode and the drain finger electrode and covers the gate finger electrode, wherein the third insulation layer is arranged on the fourth insulation layer.

In some embodiments, the first conductive layer is coupled to the gate runner by a third conductive via that extends through the third and fourth insulation layers.

In an embodiment, an inverter is provided that comprises one or more half bridge circuits, each comprising a first switch coupled in series with a second switch. At least one of the first switch and the second switch comprises a semiconductor device comprising a lateral transistor device having a source, a drain and a gate, and a monolithically integrated capacitor coupled between the gate and the drain.

In some embodiments, the inverter is a voltage source inverter for a motor drive.

In some embodiments, the inverter further comprises gate driver circuitry for actively controlling gate current of at least one of the first switch and the second switch.

In some embodiments, the gate driver circuitry is multilevel current controlling gate driver circuitry in which a first current level is used at start on and a second current level is used to maintain the current.

DETAILED DESCRIPTION

A number of exemplary embodiments will be explained below. In this case, identical structural features are identified by identical or similar reference symbols in the figures. In the context of the present description, “lateral” or “lateral direction” should be understood to mean a direction or extent that runs generally parallel to the lateral extent of a semiconductor material or semiconductor carrier. The lateral direction thus extends generally parallel to these surfaces or sides. In contrast thereto, the term “vertical” or “vertical direction” is understood to mean a direction that runs generally perpendicular to these surfaces or sides and thus to the lateral direction. The vertical direction therefore runs in the thickness direction of the semiconductor material or semiconductor carrier.

As employed in this specification, when an element such as a layer, region or substrate is referred to as being “on” or extending “onto” another element, it can be directly on or extend directly onto the other element or intervening elements may also be present. In contrast, when an element is referred to as being “directly on” or extending “directly onto” another element, there are no intervening elements present.

A depletion-mode device, such as a high-voltage depletion-mode transistor, has a negative threshold voltage which means that it can conduct current at zero gate voltage. These devices are normally on. An enhancement-mode device, such as a low-voltage enhancement-mode transistor, has a positive threshold voltage which means that it cannot conduct current at zero gate voltage and is normally off. An enhancement-mode device is not limited to low voltages and may also be a high-voltage device.

As used herein, a “high-voltage device”, such as a high-voltage depletion-mode transistor, is an electronic device which is optimized for high-voltage switching applications. That is, when the transistor is off, it is capable of blocking high voltages, such as about 300 V or higher, about 600 V or higher, or about 1200 V or higher, and when the transistor is on, it has a sufficiently low on-resistance (RON) for the application in which it is used, i.e., it experiences sufficiently low conduction loss when a substantial current passes through the device. A high-voltage device can at least be capable of blocking a voltage equal to the high-voltage supply or the maximum voltage in the circuit for which it is used. A high-voltage device may be capable of blocking 300 V, 600 V, 1200 V, or other suitable blocking voltage required by the application.

As used herein, a “low-voltage device”, such as a low-voltage enhancement-mode transistor, is an electronic device which is capable of blocking low voltages, such as between 0 V and Vlow, but is not capable of blocking voltages higher than Vlow. Vlowmay be about 10 V, about 20 V, about 30 V, about 40 V, or between about 5 V and 50 V, such as between about 10 V and 30 V.

As used herein, the phrase “Group III-Nitride” refers to a compound semiconductor that includes nitrogen (N) and at least one Group III element, including aluminum (Al), gallium (Ga), indium (In), and boron (B), and including but not limited to any of its alloys, such as aluminum gallium nitride (AlxGa(1-x)N), indium gallium nitride (InyGa(1-y)N), aluminum indium gallium nitride (AlxInyGa(1-x-y)N), gallium arsenide phosphide nitride (GaAsaPbN(1-a-b)), and aluminum indium gallium arsenide phosphide nitride (AlxInyGa(1-x-y)AsaPbN(1-a-b)), for example. Aluminum gallium nitride and AlGaN refers to an alloy described by the formula AlxGa(1-x)N, where 0<x<1.

For applications in which it is desirable to control the slew rate or dv/dt of a silicon transistor device, various approaches can be used. For example, a gate resistor may be used. This gate resistor acts against the inherent gate drain capacitance, CGD, or Miller capacitance to provide slew rate control. However, for other types of semiconductor devices, such as III-V semiconductor device and Group III nitride-based transistor devices, a gate resistor leads to high losses. This is a result of CGD being nonlinear for Group III nitride-based devices which leads to the slew rate being non-linear. Therefore, if the fastest portion of the switching speed is limited to a certain value, the overall switching speed becomes slower than desirable and to higher losses. Additionally, the slew rate is dependent on the load current.

One approach for controlling the slew rate in III-V semiconductor devices and Group III nitride-based devices, such as Group III nitride based HEMTs is to control the gate drive current to compensate for the nonlinearity in CGD and achieve a slew rate that is more linear.

A further approach for controlling the slew rate in III-V semiconductor devices and Group III nitride-based devices, such as Group III nitride based HEMTs is to include an additional capacitance that is coupled in parallel with the inherent gate drain capacitance Ca). The additional capacitance is linear so that the characteristic of the combined parallel capacitance is dominated by the additional linear capacitor and dv/dt is thus linearized. Whilst this approach may result in an increase in the total gate charge, the gate charge for Group III nitride-based transistor devices is low so that any increase in gate charge is acceptable as the total gate charge is still low in comparison with other types of semiconductor devices, such as silicon-based transistor devices.

The additional capacitance may be provided by an external capacitor. An external capacitor may lead to an increase in size and also in a requirement for additional pins in the package of the transistor device for connecting the external capacitor to the transistor device.

According to embodiments described herein, an additional capacitor that is coupled between drain and gate of the III-V transistor device, e.g. Group III nitride-based transistor device, is integrated into the semiconductor device. The additional capacitor may be integrated into the metallization structure arranged on a major surface of the semiconductor device including the transistor device and may be monolithically integrated into the metallization structure. Thus, a linearizing capacitor can be added to the equivalent circuit without requiring extra pins or significantly increasing the size occupied so that the slew rate is linearized and more accurately controllable.

A transistor device comprises a reverse transfer capacitance Crss, which is a dynamic characteristic of the transistor device that is dependent on the drain-source voltage Vds. By including an additional capacitor coupled between gate and drain, the value of Crssat a particular value of Vas is increased due to the linearizing effect of the additional capacitor. In some embodiments, the ratio between Crssat a drain source voltage of 0 V, i.e. Crss(Vds=0V), and Crssat a drain source voltage of 400 V, i.e. Crss(Vds=400V), is less than 50, or less than 20. In some embodiments, the ratio between Crssat a drain source voltage of 0 V, i.e. Crss(Vds=0V), and Crssat a drain source voltage of 200 V, i.e. Crss(Vds=200V)is less than 20.

For a comparison transistor device without the additional capacitor coupled between gate and drain, the ratio between Crssat a drain source voltage of 0 V, i.e. Crss(Vds=0V), and Crssat a drain source voltage of 400 V, i.e. Crss(Vds=400V), is greater than 100. For a comparison gallium nitride based HEMT without the additional capacitor coupled between gate and drain, Crss(Vds=0V)/Crss(Vds=400V), may be greater than 500.

FIG.1illustrates an equivalent circuit diagram10of a transistor device11with a controllable slew rate or dv/dt. The transistor device11may be a lateral transistor device, for example a III-V semiconductor device and in some embodiments is lateral a Group III nitride-based transistor device such as a Group III nitride-based HEMT (High Electron Mobility Transistor).

The transistor device11has a source connected to a low voltage bus12, which may be ground, and a drain connected to high-voltage bus13. The transistor device11includes an inherent drain source capacitance CDs' an inherent gate source capacitance, CGS, and an inherent gate drain capacitance CGD. An additional capacitor14is coupled between the drain and gate of the transistor device11and is also is coupled in parallel with the inherent gate drain capacitance CGD of the transistor device11. The additional capacitor14has a capacitance CMwhich is greater than the capacitance CGD. For example, the capacitance CMof the additional capacitor14can be at least 10 times larger than CGD.

In this circuit, the discharging and charging time of the additional capacitor14is variable and dv/dt is controllable and can be slowed down to provide a desired value. The capacitance of the additional capacitor14can be selected so as to linearize dv/dt. The additional capacitor14coupled between the drain and the gate and is coupled in parallel with the inherent gate drain capacitance CGD. This has the effect of linearizing the dv/dt slope which enables dv/dt to be controlled more accurately and the switching speed of the transistor11to be set at a desired value.

As used herein, a transistor device will be described as having a source, a drain and gate. These terms also encompass the functionally equivalent terminals of other types of devices, such as an insulated gate bipolar transistor. For example, as used herein, the term “source” encompasses not only a source of a MOSFET device but also an emitter of an insulator gate bipolar transistor (IGBT) device and an emitter of a BJT device, the term “drain” encompasses not only a drain of a MOSFET device but also a collector of an insulator gate bipolar transistor (IGBT) device and a collector of a BJT device, and the term “gate” encompasses not only a gate of the MOSFET device but also a gate of an insulator gate bipolar transistor (IGBT) device and a base of a BJT device.

According to embodiments described herein, the additional capacitor14is integrated into the semiconductor device which includes the transistor device11as is indicated by the dashed line15inFIG.1. The additional capacitor14may be monolithically integrated into the semiconductor device which includes the transistor device11. In some embodiments, the capacitor14is monolithically integrated into the metallization structure of the semiconductor device and/or transistor device11. In some embodiments, the transistor device is a lateral transistor device.

This semiconductor device may be used in applications such as inverters which include one or more half bridge circuits, each half bridge circuit comprising a first switch coupled in series with a second switch. The first switch may be the low side switch and the second switch the high side switch of the half bridge circuit. At least one of the first switch and the second switch may be provided by the transistor device15with the additional capacitor14coupled between drain and gate so that the overall gate-drain capacitance and, consequently, slew rate or dv/dt of the transistor device15is linearized and the switching speed is more accurately controllable.

In a half bridge circuit, the source of the low side switch or first transistor device, is coupled to low-voltage bus, for example ground, the drain of the low side switch is coupled to the source of the high side switch via an output node which may be coupled to a load which is to be driven by the half bridge circuit and the drain of the high side switch is coupled to high-voltage bus.

The inverter may be a voltage source inverter for a motor drive, for example. In some embodiments, the inverter further comprises gate driver circuitry. In some embodiments, the gate driver circuitry is configured to actively control the gate current. In some embodiments, the gate driver circuitry is multilevel current controlling gate driver circuitry in which a first current level is used at start on and a second current level is used to maintain the current.

FIG.2illustrates a schematic view of a semiconductor device20. The semiconductor device20may provide the equivalent circuit of the device15schematically indicated inFIG.1.

The semiconductor device20comprises a semiconductor body21having a first surface22, a lateral transistor device23formed in the semiconductor body21and metallisation structure24arranged on the first surface22. A capacitor25is integrated into the semiconductor device20, for example into the metallisation structure24.

The lateral transistor device23includes a source electrode26, a drain electrode27and a gate electrode28arranged on the first surface22. The gate electrode28is arranged laterally between the source electrode26and the drain electrode27. The capacitor25is electrically coupled between the drain electrode27and the gate electrode28.

The lateral transistor device23may be a III-V semiconductor device so that the semiconductor body21comprises one or more III-V semiconductor materials. In some embodiments, the lateral transistor device23is a Group III nitride-based semiconductor device so that the semiconductor body21comprises one or more Group III nitride materials.

Typically, the lateral transistor device23includes a plurality of source electrodes26, drain electrodes27and gate electrodes28and the capacitor25is electrically coupled between the drain electrodes27and the gate electrodes28. In some embodiments, the lateral transistor device23comprises source finger electrodes, drain finger electrodes and gate finger electrodes arranged on the first surface22of the semiconductor body21. In these embodiments, the capacitor25is integrated into the metallisation structure24and electrically coupled between the gate finger electrodes and the drain finger electrodes.

An additional linear capacitor25is used which is coupled between gate and drain electrodes of the transistor device23and in parallel with the inherent gate drain capacitance Ca) of the transistor device23in order to linearize dv/dt without occupying additional space external to the semiconductor device20. Since the transistor device23is a lateral device, all three electrodes, that is source, drain and gate, are conveniently positioned on a common first surface22, thus simplifying integration of the capacitor25into the metallisation structure24and into the portions of the metallization structure24that are coupled to the drain and gate electrodes.

The additional linearizing capacitor25may be integrated into the metallization structure24in different ways. Various embodiments will be now described with reference toFIGS.3A through5B.

FIGS.3A to3Fillustrate a semiconductor device30including a lateral transistor device31according to an embodiment.

In some embodiments, the semiconductor device30is a III-V semiconductor device and in some embodiments, such as that illustrated inFIG.2, the semiconductor device30is a Group III nitride-based semiconductor device. The transistor device31may be a Group III nitride-based HEMT (High Electron Mobility Transistor) device. The transistor device31may be a high voltage device having a blocking voltage of 600V or more and may be an enhancement mode device or a depletion mode device.

The semiconductor device30has a semiconductor body45with a first or top surface46. In the plan view ofFIG.3A, it can be seen that the transistor device31includes an active area or cell field38. A plurality of source fingers32alternately arranged with a plurality of drain fingers33are positioned on the first surface46of the semiconductor device30. Each of the source fingers32and drain fingers33are elongate and extend substantially parallel to one another. The source fingers32are electrically coupled to a common source pad34arranged adjacent a first lateral side of the cell field38and the drain fingers33are electrically coupled to a common drain pad35arranged on the opposing side of the cell field38by a drain bus44. This arrangement of the source and drain fingers32,33is also referred to as an interdigitated arrangement.

A gate electrode finger, which cannot be seen in the plan view ofFIG.3A, is positioned laterally between a source finger32and drain finger33and is electrically coupled to a gate pad36by a gate runner39. The gate runner39extends along the first lateral side of the cell field38to connect the gate finger electrodes to the gate pad36. The gate pad36is arranged laterally adjacent to and spaced apart from the cell field38.

In the embodiment illustrated inFIGS.3A through3F, the semiconductor device30also includes a diode37for ESD protection which is positioned adjacent one lateral side of the cell field38and the transistor device31.

An additional linearizing capacitor40is arranged on the first surface46that is electrically coupled between the drain fingers32and the gate runner39. In this embodiment, the additional linearizing capacitor40is positioned laterally adjacent the cell field38and laterally adjacent to the outermost finger, in this case a source finger of the cell field38. In this embodiment, the additional linearizing capacitor40is positioned laterally between the cell field38and the diode37and on the first surface46. In this embodiment, the capacitor40has an elongate shape in plan view. However, the shape of the capacitor40and its position on the first surface of the semiconductor device30may vary depending on the space available on the top surface46of the semiconductor device30.

As can be more clearly seen in the enlarged plan views ofFIGS.3B and3C, the capacitor40includes a first or bottom plate41, a second or top plate42arranged vertically above the first plate41and a dielectric43arranged between the first plate41and the second plate42. The first plate41comprises a conductive material which is connected to the gate pad36of the transistor device31. In some embodiments, the first plate41may be formed by an extension45of the gate runner39. In the design ofFIGS.3A through3F, the extension45may be substantially perpendicular to the gate runner39. The gate pad36is positioned on top of the gate runner39.

As can be seen in the enlarged plan view ofFIG.3C, the second plate42of the capacitor40is formed by a portion of a conductive layer forming the drain bus44. The drain bus44extends substantially perpendicularly to the drain fingers33laterally adjacent the cell field38and electrically couples the drain fingers33to one another. In this embodiment, the second plate42of the capacitor40is formed by an extension of the drain bus44on the first surface46that extends substantially perpendicularly to the drain bus44and substantially parallel to the drain fingers33. In some embodiments, the drain bus44and the second plate42are formed from a titanium nitride layer. The drain pad35is formed on the drain bus44and may include a metal, for example copper.

The vertically overlapping region between the first plate41provided by the extension45of the gate runner39and the second plate42provided by the extension of the drain bus44can be adjusted to provide the desired value of the capacitance of the linearizing capacitor40.

The semiconductor device30includes a metallization structure on the first surface46that includes a first conductive layer that is structured to form the gate runner39, the first plate41of the capacitor40and the source and drain fingers32,33positioned on the underlying source and drain finger electrodes. The metallization structure also includes a dielectric layer43that is positioned on the first conductive layer and a second conductive layer that is positioned on the dielectric layer43. The second conductive layer is structured to form the drain bus44and the second plate42of the capacitor40. The metallization structure also includes a further conductive layer on the second conductive layer that provides the source pad34, drain pad35and gate pad36.

Therefore, the additional capacitor40is monolithically integrated into the metallisation structure arranged on the first surface46of the semiconductor device30by appropriately structuring the masks using to fabricate the metallisation structure. In this embodiment, the capacitor40is monolithically integrated into the metallization structure without including any extra layers exclusively for the capacitor40.

FIG.3Dillustrates a cross-sectional view along the line A-A ofFIG.3Aand illustrates a cross-sectional view of a central region of the capacitor40. InFIG.3D, it can be seen that the semiconductor device30includes the semiconductor body45including the first or top surface46. The semiconductor device30is a Group III nitride-based device and includes a multilayer Group III nitride structure in which a transition layer47is arranged on a non-illustrated substrate, a channel layer48is positioned on the transition layer47and a barrier layer49is positioned on the channel layer48to from a heterojunction50. The channel layer48may comprise gallium nitride and the barrier layer49may comprise aluminium gallium nitride so that a heterojunction50is formed between the channel layer48and the barrier layer49that is capable of supporting a two-dimensional carrier gas.

The dielectric layer43of the capacitor40is positioned on the first plate41and the second plate42, which is connected to the drain bus44and the drain pad35, is positioned on the dielectric layer43. The conductive layer, which provides the first plate41of the capacitor40and the gate runner39, is electrically insulated from the barrier layer49of the semiconductor body45by an insulating layer51which may be formed of silicon nitride, for example. The first conductive layer and, therefore, the first plate41and the gate runner39may include a metal, such as copper. The dielectric layer43may include be formed of silicon nitride and/or silicon dioxide. The second plate42and drain bus44may include titanium nitride or a metal.

Also illustrated inFIG.3Dis a passivation layer52which is positioned on the second plate42. The passivation layer52may include two or more sublayers. In the example illustrated inFIG.3D, the passivation layer52includes a silicon nitride sublayer53positioned on the second plate42and a silicon dioxide sublayer54positioned on the silicon nitride sublayer53.

FIG.3Eillustrates a cross-sectional view along line B-B ofFIG.3Aand a cross-sectional view along the length of a portion of the capacitor40and the connection between the second plate42of the capacitor40and the drain pad35.

FIG.3Eillustrates that the bottom first plate41of the capacitor40that is coupled to the gate pad36has a distal end55which is laterally spaced apart from the drain pad35. The conductive layer forming the second plate42has a connection region56that extends laterally beyond the distal end55of the first plate41and under the drain pad35. The connection region56is in direct contact with the drain pad35to electrically connect the second plate42to the drain pad35. Vertically underneath the drain pad35and the connection region56of the second plate42, the semiconductor body45includes only insulating material in the space between the connection region56and the top surface46of the semiconductor body. The area of the capacitor40and, therefore, the capacitance provided, is limited at this end of the capacitor40by the lateral extent of the first plate41.

FIG.3Fillustrates a cross-sectional view along the line C-CFIG.3Aand illustrates a cross-sectional view at the opposing end of the capacitor40.FIG.3Fillustrates that the second plate42has a distal end56that is spaced apart from the gate pad36. The conductive layer providing the first plate41includes a connection region58that extends under the gate pad36and is spaced apart from the gate pad36by the dielectric layer43. A conductive via57is provided that vertically extends between the connection region58of the first plate41and the gate pad36and electrically couple the first plate41to the gate pad36and to the gate fingers of the transistor device. The area of the capacitor40is, therefore, limited by the lateral extent of the second plate42at this end of the capacitor40.

FIGS.4A and4Billustrate a plan view and a cross-sectional view, respectively, of a semiconductor device60including a lateral transistor device61according to an embodiment. The transistor device61includes a capacitor62which is integrated into a metallisation structure64positioned on a first surface65of semiconductor body66of the semiconductor device60. In this embodiment, the capacitor62is positioned on the active area63of the transistor device61and above the cell field.

Referring to the cross-sectional view ofFIG.4B, the semiconductor body66is a Group III nitride-based semiconductor body which includes a transition structure67arranged on a non-illustrated substrate, a channel layer68arranged on the transition layer67and a barrier layer69arranged on the channel layer68such that a heterojunction70is formed at the interface between the channel layer68and the barrier layer69. The channel layer68may comprise gallium nitride and the barrier layer69may comprise aluminium gallium nitride and the heterojunction70formed between the channel layer68and the barrier layer69is capable of supporting a two-dimensional charge gas, such as a two-dimensional electron gas (2 DEG).

The transistor device61includes source finger electrodes71drain finger electrodes72and gate finger electrodes73which are arranged on the first surface65of the semiconductor body66. The transistor device61is, therefore, a lateral transistor device with a conductive channel which extends substantially parallel to the first surface65.

The source finger electrodes71, the drain finger electrodes72and the gate finger electrodes73each have an elongate form which extends into the plane of the drawing ofFIG.4Ain the cross-sectional view ofFIG.4B. Using a Cartesian coordinate system with the plane of the drawing ofFIG.4Ain the x-y plane, the source finger electrode71, the drain finger electrode72and the gate finger electrode73each have a length extending in the y direction, a width extending in the x direction and a thickness extending in the z direction.

In the view illustrated inFIGS.4A and4B, a single source electrode71is illustrated with a gate finger electrode65positioned adjacent two opposing sides of the source finger electrode71and a drain electrode72is positioned adjacent each gate finger electrode73such that the gate finger electrode73is laterally positioned between the source finger electrode71and one of the drain finger electrodes72.

The source finger electrode71, drain finger electrode72and gate finger electrode73are not illustrated in the plan view ofFIG.4Awhich illustrates on the structure of the metallisation layer64arranged on the first surface65of the semiconductor body66and on the source finger electrode71, the drain finger electrode72and the gate finger electrode73.

The capacitor62is positioned above the source finger electrode71and includes a first plate74formed from a first conductive layer75of the metallisation structure64and a second plate76which is formed from a second conductive layer77of the metallisation structure64. The first and second conductive layers75,77are spaced apart from one another by a first insulating layer78of the metallisation structure64which also forms the dielectric of the capacitor62.

The metallisation structure64further includes a third conductive layer79which is positioned between the first conductive layer75and the first surface65of the semiconductor body66. The third conductive layer79comprises a source finger80which is arranged on the source finger electrode71and a drain finger81which is positioned on the drain finger electrode72. The third conductive layer79also includes a gate runner82, which can be seen in the plan view ofFIG.4A, which is positioned laterally adjacent the gate finger electrodes73, source finger electrodes71and drain finger electrodes81. In particular, the gate runner82extends substantially perpendicularly to the long length of the source finger71, drain finger72and gate finger73and in the x direction and is spaced apart from a distal end of the source finger71and drain fingers72. The gate finger electrodes73extend to and are connected with the gate runner82so that the gate runner82electrically couples the gate finger electrodes73to one another.

The first conductive layer75and, in particular, the first plate74of the capacitor62is positioned above the third conductive layer79and vertically above the source finger80. The first plate74is electrically insulated from the underlying source finger80and from source finger electrode71by a second insulating layer83. In some embodiments, the second insulating layer83may comprise silicon nitride and may be much thinner than the first insulating layer78which is positioned between the conductive plates74,76of the capacitor62.

The source finger80has a width which is greater than the width of the source finger electrode71and may have a width such that it is positioned above the gate finger electrodes73. The metallisation structure64further includes a third insulating layer84which is positioned between the source fingers80and gate fingers81and a fourth insulating layer85which is positioned on the first surface65and extends between the source fingers80and the drain fingers81and also covers the gate finger electrodes73so as to electrically insulate the gate finger electrodes73from the overlying source finger80.

As can be seen in the plan view ofFIG.4A, the source fingers80also have an elongate shape and are spaced apart from the drain fingers81which also have an elongate shape. The source fingers80and the drain fingers81have a long direction extending in the y direction and a width extending in the x direction.

The metallisation structure64includes a second conductive layer77which is used to electrically couple the source fingers80to one another and the drain fingers81to one another. Referring toFIG.4A, the second conductive layer77is structured to provide at least one source bus86and at least one drain bus87which are laterally spaced apart from one another and which have a long direction extending in the x direction and perpendicularly to the long directions of the source fingers80and drain fingers81. The source and drain buses86,87are arranged alternately in the y direction.

The source bus86and the drain bus87are elongate and extend substantially perpendicular to the source fingers80and drain fingers81and have a lateral extent such that they extend over at least two if not more source fingers80and drain fingers81. The drain bus87extends over the source finger80and is electrically coupled to the drain fingers81positioned on opposing sides of the source finger80by conductive vias88which extend through the first insulating layer78. The drain bus87is electrically insulated from the source finger by the first insulating layer78. Similarly, the source bus86extends over the drain fingers81and is electrically insulated from the drain fingers81by the first insulating layer78. The source bus86is electrically coupled to the source finger80by a conductive via89which extends from the source bus to the source finger80through the first insulating layer78. The conductive vias88,89have an off-set arrangement. The conductive via89from the source finger80is positioned laterally adjacent and spaced apart in the y direction from the first plate74of the capacitor62which is also positioned on the source finger80, but spaced apart and insulated from the source finger80by the second insulation layer83.

Using the Cartesian coordinate system, the plan view ofFIG.4Amay be considered to be in the x-y plane, whereby the source electrode fingers71, drain electrode fingers72, gate electrode finger73, the source fingers80and the drain fingers81of the third conductive layer79extend in the y direction and the source bus86, drain bus87of the second conductive layer77and the gate bus82of the third conductive layer79extend in the x direction. The z direction extends substantially perpendicularly to the first major surface65of the semiconductor body66such that the conductive vias88,89and90extend in the z direction.

The first conductive layer75has a lateral extent which corresponds to the lateral extent of the width of the first plate74of the capacitor62. As can be seen in the plan view ofFIG.4A, the first conductive layer75extends beyond the distal end of the source finger80and is positioned above the gate runner82which is formed in the underlying third conductive layer79. The first conductive layer75and the first plate74of the capacitor74is electrically coupled to the gate bus82by a conductive via90which extends through the first insulating layer78that is positioned between the first conductive layer75and the gate runner82.

The capacitor62is formed within the active area of the transistor device61since it is positioned above the source finger80of the third conductive layer and the drain bus87of the second conductive layer77. A capacitor having a form corresponding to that of the capacitor62may be positioned above some or all of the source fingers80of the transistor device61.

In the embodiment illustrated inFIGS.4A and4B, the width of the first plate of the capacitor62in the x direction is slightly less than the width in the x direction of the underlying source finger80such that the top edges of the source finger80are surrounded by the first insulating layer78, the second insulating layer83and the third insulating layer84.

The capacitor62includes a first plate74which is formed from the first conductive layer75and a second plate76which is formed from a portion of the second conductive layer77that also forms the drain bus87. The dielectric of the capacitor62is formed by a portion of the first insulating layer78that also serves as an interlayer dielectric of the metallization structure64that electrically insulates the second conductive layer77from the underlying third conductive layer79and, in particular, the drain bus87from the underlying source fingers80and the source bus86from the underlying drain fingers81.

In this embodiment, an additional conductive layer75is included in the metallization structure for the transistor device61to form the first plate74which does not form any part of the redistribution structure between one of the electrodes of the transistor device61and outer contact pads. The first conductive layer75forming the first plate may be used exclusively for the purpose of monolithically integrating the capacitor62into the metallization structure64at a positioned above the cell field and active area63of the transistor device61.

The first plate74is coupled to the gate electrode fingers by means of an extension of the first plate74in the y direction to above the gate runner82and the conductive via90. The second plate76is formed from the portion of the drain bus87overlying the first plate74and is coupled to the drain fingers electrodes72by way of the conductive via89and drain fingers81. The capacitor62provides a linear capacitance that is coupled in parallel with the inherent gate drain capacitance of the transistor device61so that the combined gate drain capacitance is linearized and dv/dt is linearized, thus enabling accurate control of the slew rate.

The source buses86are spaced apart from one another by laterally intervening drain buses87. The source buses86can be electrically coupled together by further source bus which may extend perpendicularly to the source buses86and parallel to the source fingers80which is positioned adjacent and spaced apart from a distal end of the drain buses87. Similarly, the drain buses87may be electrically coupled together by a further drain bus which extends perpendicularly to the drain buses86and parallel to the drain fingers81and which is positioned at the opposing side of the active area form the additional source bus. A source contact and a drain contact may be positioned on these additional buses.

FIGS.5A and5Billustrate a plan view and a cross-sectional view, respectively, of a semiconductor device100including a lateral transistor device61and a linearizing capacitor101according to an embodiment.

The lateral transistor device61corresponds to the lateral transistor device61of the semiconductor device60illustrated inFIGS.3A through3F. The linearizing capacitor101comprises a first plate74′ formed of the first conductive layer75which is positioned on the second insulating layer83which is in turn positioned on the source finger80as in the embodiment illustrated inFIGS.4A and4B. The linearizing capacitor101also includes the second plate76which is formed from the second conductive layer77of the metallisation structure64as in the embodiment illustrated inFIGS.4A and4B. The first plate74is spaced apart from the second plate76by the first insulating layer78to form the structure of the linearizing capacitor101. The first insulating layer78also forms the first interlayer dielectric of the metallisation structure64.

The linearizing capacitor101of the embodiment illustrated inFIGS.5A and5Bdiffers from the linearizing capacitor62of the embodiment illustrated inFIGS.4A and4Bin the value of the capacitance provided and in the width of the first plate74′ and also the width of the first plate74′ with respect to the width of the underlying source finger80.

In the embodiment illustrated inFIGS.5A and5B, the first plate74′ has a width in the x direction which is greater than the width in the x direction of the source finger80so that the opposing peripheral edges103,104of the first plate74′ are positioned vertically above the third insulating layer84which extends between the source fingers80and drain fingers81. The larger overall size of the first plate74′ compared to the first plate74in the embodiment illustrated inFIGS.4A and4B, leads to an increase in the capacitance of the capacitor101compared to the capacitor62illustrated inFIGS.4A and4B. The position of the peripheral edges103,104above the third insulating layer84provides an increased gate source capacitance Ccs compared to the embodiment illustrated inFIGS.4A and4B.

As in the embodiment illustrated inFIGS.4A and4B, the first plate74′ is electrically coupled to the gate bus82by a conductive via90which extends between the first plate74′ and the gate bus82at a position laterally adjacent to and spaced apart from the distal end of the source finger80and the drain fingers81. The second plate76is formed by a portion of the second conductive layer77that forms a drain bus87. As in the embodiment illustrated inFIGS.4A and4B, a capacitor101may be positioned above some or all of the source fingers80of the transistor device61.

The first plate74,74′ may include titanium nitride and/or tungsten. The materials of the second insulating layer83positioned between the first plate74,74′ and the underlying source finger80and its thickness as well as the material and thickness of the third insulating layer84may be selected such that the desired voltage rating of the transistor device is maintained.

For the transistor device61of the semiconductor devices60and100, starting from the first surface65of the semiconductor body66, the metallisation structure64has a structure formed of the fourth insulating layer85, the third conductive layer79and third insulating layer84, which are substantially coplanar, the second insulating layer83, the first conductive layer75, the first insulating layer78, and the second conductive layer77. In some embodiments, the second conductive layer77may include two or more sublayers, for example a titanium nitride layer which is positioned on the first insulating layer78and a metal layer, for example copper or a copper alloy, which is positioned on the titanium nitride layer. Similarly, the first insulating layer78may include two or more sublayers. In some embodiments, first sublayer may comprise silicon oxide and silicon nitride layer may be positioned on the silicon oxide layer.

The first insulating layer78and the third insulating layer84may be referred to as interlayer dielectrics. The third conductive layer79is commonly referred to as the M1of first metal layer and the second conductive layer77is commonly referred to as the second metallic layer M2the metallisation structure64. The third insulating layer84is the first interlayer dielectric ILD1and the first insulating layer78is the second interlayer dielectric ILD2. In this nomenclature, the first plate74,74′ may be thought of as third metal layer M3.

Whilst the first plate of the capacitor that is coupled to the gate of the transistor device may be positioned below the second plate that is coupled to the drain of the transistor device in the z direction, the opposite orientation is also possible so that the plate of the capacitor that is coupled to drain is positioned below the plate of the capacitor that is coupled to gate.

To summarise, by monolithically integrating an additional linear capacitor in the metallisation structure applied to the semiconductor device including a lateral transistor device, for example a Group III nitride-based transistor device, and electrically coupling this additional linear capacitor between gate and drain of the lateral transistor device, the combined gate drain capacitance of the transistor device is linearized so that the slew rate of dv/dt is linear allowing the switching speed to be adjusted, for example slowed, to a desired value. The capacitance of the capacitor can be well controlled as the geometry of the capacitor structure can be accurately controlled using photolithographic manufacturing processes used to fabricate the metallisation structure, in particular, the metal layers providing the plates of the capacitor. Additional chip area is not required for the additional capacitor and also no further pins of the package in which the semiconductor device is packaged are required, since the linearizing capacitor is positioned on and electrically coupled with the gate and drain of the transistor structure by the metallization structure itself. Consequently, external high-voltage capacitors can be avoided which avoids parasitic interconnect impedances, reduces the risk of high frequency oscillation and avoids additional variation of dv/dt due to parasitic capacitance.