Phase locked loop that includes D. C. modulation

A D.C. modulated phase locked oscillator (220 or 264) is usable separately to provide an output that is both phase locked and D.C. modulated or is usable in a radio frequency receiver (200). The D.C. modulated phase locked oscillator (220or 264) includes a phase locking oscillator (222 or 266) and a D.C. modulator (224 or 268). Both a forward path (14) and a feedback path (16) are D.C. modulated. In one embodiment. D.C. modulation of the feedback path (16) includes using a modulation oscillator (64) and two flip-flops (228 and 164) to develop quadrature square waves, and using a quadrature phase shift keying (QPSK) mixer (234) to subtract a frequency of one of the square waves from the frequency in the feedback path (16). In another embodiment, D.C. modulation of the feedback path (16) includes a dual modulus divider (34) being interposed into the feedback path (16), frequencies from a modulation oscillator (64) being used to control a parallel adder (272), and the parallel adder (272) being used to change one of the inputs of a modulus controller (50) that includes both "A" and "N" inputs, and that controls the number of times that the dual modulus divider (34) divides by lower and higher dividing ratios in accordance with the "A" and "N" inputs, whereby D.C. modulation of the feedback path (16) is achieved by a change in one of the inputs, "A" or "N".

BACKGROUND OF THE INVENTION 
1. Field of the Invention 
The present invention relates generally to phase locked oscillators and 
voltage controlled crystal oscillators. More particularly, the present 
invention relates to a phase locked loop with D.C. modulation, and uses of 
the D.C. modulated phase locked loop in such electrical devices as single 
frequency transmitters and receivers, and channelized transmitters and 
receivers. 
2. Description of the Related Art 
The frequency of radio frequency voltage controlled oscillators (RF VCO) 
has been closely controlled by phase locking a feedback signal from the RF 
VCO to a crystal controlled reference oscillator (XO). A phase detector 
has been used to determine the phase difference between the feedback 
signal and a crystal controlled reference frequency; and an integrator has 
been used to summate the phase difference and to control the frequency of 
the RF VCO oscillator in accordance with the summated phase difference. 
Improvements taught by the prior art over the basic phase locked oscillator 
include the use of prescalers to provide a feedback signal having a lower 
frequency than the RF VCO, thereby lowering the required frequency of the 
controlling circuitry. Prior art improvements over the basic circuitry 
also include the use of a dual modulus divider to channelize the output 
frequency by dividing the feedback by higher and lower dividing ratios in 
a technique known as pulse swallowing. That is, channelizing is 
accomplished by swallowing, or removing, pulses in the feedback path. 
While phase locked oscillators have provided a frequency output that drifts 
very little, a significant problem has been in trying to frequency 
modulate the output on a D.C. basis. 
One attempt at D.C. modulating the frequency output of a phase locked 
oscillator has been to use a voltage controlled crystal oscillator (VCXO) 
in place of a crystal controlled reference oscillator (XO), and to 
simultaneously modulate the RF VCO as well as the VCXO. The problems with 
this approach have been non-linearities in the VCXO, limited frequency 
deviation, limited frequency response of modulation, and significantly 
increased frequency drift as a function of both time and temperature. 
In stark contrast to the limitations of the prior art, the present 
invention provides highly linear D.C. modulation of a RF VCO together with 
very little frequency drift as well as almost unlimited deviation and 
frequency response. 
More particularly, the present invention provides both single frequency and 
channelized phase locked loops that are capable of D.C. modulation. 
SUMMARY OF THE INVENTION 
In the present invention, a D.C. modulated phase locked RF VCO includes a 
phase locked loop with a forward path, an RF VCO in the forward path that 
produces an output, a feedback path that is connected to the output, a 
crystal controlled reference oscillator, a phase detector that is 
connected to the crystal controlled reference oscillator and that is 
connected to both the feedback path and the forward path, and an 
integrator in the forward path that controls the frequency of the voltage 
controlled oscillator in response to integrated differences in the phase 
between said reference oscillator and the frequency in the feedback path. 
The means for D.C. modulating the RF VCO includes a dual modulus divider 
that is interposed into the feedback path, and a modulation oscillator 
that is connected to the dual modulus divider and that causes the dual 
modulus divider to divide by a higher dividing ratio for each cycle of the 
audio oscillator. Preferably, the modulation oscillator is a voltage 
controlled audio oscillator (AF VCO). 
Therefore, the dual modulus divider cooperates with the voltage controlled 
audio oscillator to remove one pulse from the feedback path for each cycle 
of the audio oscillator. The RF VCO is then caused by the loop to increase 
its output frequency to exactly compensate for these removed pulses. The 
result is that the frequency of the audio frequency oscillator is added to 
the frequency of the oscillator. D.C. modulation of the output is 
therefore achieved by D.C. modulating the voltage input to the voltage 
controlled audio frequency oscillator. 
Optionally, RF VCO is D.C. modulated substantially simultaneously with 
modulating of the feedback path in order to increase the frequency 
response of the loop. 
Further, the present invention includes means for synchronizing the 
changing of dividing ratios in accordance with completion of dividing at 
one of the ratios. In one embodiment, this means for synchronizing 
includes first and second flip-flops, and an OR gate. In another 
embodiment, this means for synchronizing includes a shift register, an OR 
gate, an AND gate, and an inverter. 
In the embodiment using the shift register, the combination of the shift 
register with the voltage controlled audio oscillator and the dual modulus 
divider provides a system in which a plurality of pulses are removed from 
the feedback path for each cycle of the audio oscillator. 
Optionally, a prescaling divider is used in the feedback path to reduce the 
frequency of the feedback signal prior to dividing the feedback signal by 
the dual modulus divider. This addition allows a higher frequency 
oscillator to be similarly controlled without exceeding the frequency 
limitations of the dual modulus divider. 
Further, the use of a prescaling divider reduces the required frequency of 
the audio oscillator for any given desired range of frequency modulation. 
In another embodiment, suitable primarily for lower frequencies, the dual 
modulus divider is omitted, and a pair of bistable multivibrators, or 
flip-flops, are used to synchronize the modulation oscillator with the 
pulses in the feedback path, and a resistor and a diode are used to remove 
one pulse from the feedback path for each cycle of the modulation 
oscillator, or even to effectively remove as many as hundreds of pulses 
from the feedback path for each cycle of the modulation oscillator. 
In still another embodiment, the means for D.C. modulating a phase locked 
loop includes a modulation oscillator, a pair of flip-flops, or bistable 
multivibrators, that are connected to the modulation oscillator and that 
produce two square-wave outputs that are phase shifted 90 degrees, one to 
the other, to produce quadrature outputs, and a quadrature phase shift 
keying (QPSK) mixer that is interposed into the feedback path of the phase 
locked loop, and that is connected to both quadrature outputs. 
The QPSK mixer produces both sidebands as mixed with the frequencies in the 
feedback path, but attenuates the one which is higher than the frequencies 
in the feedback path, thereby lowering the frequencies in the feedback 
path as a function of the frequencies of the modulation oscillator. 
Then, to keep the loop phase locked, the phase detector and the integrator 
cooperate to increase the voltage applied to the voltage controlled 
oscillator in the feedback loop, and thereby increase the output frequency 
of the voltage controlled oscillator. 
In this embodiment also, the RF VCO is D.C. modulated substantially 
simultaneously with modulating of the feedback path in order to increase 
the frequency response of the loop. 
In a final embodiment of the present invention, a dual modulus divider, 
having lower and higher dividing ratios, is interposed into the feedback 
path; a modulus controller, having "A" and "N" inputs which control the 
number of times that the dual modulus divider divides at each of the two 
dividing ratios, is connected to the dual modulus divider; a modulation 
oscillator, which produces modulation frequencies, is connected to a 
parallel adder by a synchronizer; and the parallel adder increases the "A" 
count of the modulus controller as a function of the frequencies of the 
modulation oscillator. 
As the "A" count of the modulus controller is increased, an additional 
division is performed on the frequency in the feedback path, lowering the 
frequency in the feedback path, and thereby requiring that the output 
frequency in the forward path increase to maintain the loop in phase 
locked condition. 
Optionally, the forward path is D.C. modulated substantially simultaneously 
with modulation of the feedback path, as described for the other 
embodiments. 
In embodiments using a dual modulus divider, by changing the normal state 
of the dual modulus divider to divide at the higher dividing ratio, pulses 
are added to the feedback path rather than being removed. 
The exceptionally low frequency drift of the present invention is 
attributable to the inherent stability of the crystal controlled reference 
oscillator, and the low frequency drift of the modulation oscillator 
which, preferably, is in the audio frequency range. 
The proliferation of uses for various frequency bands has resulted in 
crowding of the bands, and in an accompanying need to increase the number 
of channels in a given band. However, the limitation in the number of 
channels that can be accomplished depends to some measure upon the band 
width that must be allocated to expected frequency drift over time and 
temperature. 
Until recently, for military communication bands, a frequency drift of 
.+-.0.003 percent was allowed, but now specifications have been tightened 
to allow only .+-.0.002 percent. 
Assuming a frequency drift of .+-.0.003 percent in the 2200 to 2400 MHz 
band, and assuming the mid point of the band, this allowable frequency 
drift could result in a drift of .+-.69 KHz or a total drift of 138 KHz. 
The present invention provides both transmitters and receivers in which not 
only are drift specifications of .+-.0.002 percent readily attainable, but 
also the transmitters and receivers of the present invention can be 
manufactured to hold the frequency drift within .+-.0.001 percent should 
this specification be further tightened. 
Since the frequency drift of voltage controlled oscillators is a smaller 
percentage with lower frequency designs, the frequency drift of the RF VCO 
is reduced by dividing the feedback frequency by a larger dividing ratio 
and using a lower modulation frequency, even though the effect of each 
cycle of the modulation frequency, and the drift of the modulation 
oscillator, is multiplied by the dividing ratio. 
However, a reduced frequency in the feedback path results in a lower 
frequency response of the system. The use of a shift register also reduces 
the required frequency of the audio oscillator; but it does not 
deteriorate the frequency response, as does the use of a prescaling 
divider. 
Without regard to frequency response, in preferred embodiments the present 
invention provides almost instantaneous modulation of the output in 
response to a modulation signal, since the forward path is modulated as 
well as the feedback path. Therefore, while the time to phase lock is 
dependent upon the frequency in the feedback path, the time to D.C. 
modulate the output is almost instantaneous without regard to the 
frequency in the feedback path. 
Optionally, the present invention utilizes two separate means for 
controlling the dual modulus divider. One of these controlling means is 
the D.C. modulating means of the audio frequency voltage controlled 
oscillator; and the other controlling means provides means for 
channelizing the output. 
That is, the dual modulus divider is controlled to remove pulses in the 
feedback path to provide D.C. modulation of the output; and the dual 
modulus divider is separately controlled to remove pulses in the feedback 
path at a rate in which the output is shifted to a given frequency 
channel. 
The synchronizer of the present invention prevents interruption of the 
control of the dividing ratios of the dual modulus divider by one of the 
controlling means while the other controlling means is controlling the 
dual modulus divider. 
The D.C. modulated oscillator of the present invention is usable in, and is 
a subcombination of, a radio frequency receiver of the present invention. 
The radio frequency receiver includes an input stage for receiving a 
frequency modulated input signal; an oscillator for producing a phase 
locked output signal; a demodulator, including the oscillator, and being 
operatively connected to the input stage, for producing the D.C. component 
of the frequency modulated input signal; and a modulator, being 
operatively connected to the demodulator and to the oscillator, for D.C. 
modulating the phase locked output in response to the D.C. component. 
The radio frequency receiver of the present invention is channelized and/or 
includes any or all of the features of the D.C. modulated oscillator of 
the present invention. 
The apparatus and methods of the present invention are further described in 
the following aspects of the invention. 
In a first aspect of the present invention, an electrical device is 
provided which comprises reference frequency oscillator means for 
supplying a reference frequency; phase locking oscillator means including 
a loop with a forward path that includes a comparator being connected to 
the reference frequency oscillator means, and a variable frequency 
oscillator that is operatively connected to the comparator, and with a 
feedback path that feeds a feedback signal, related to an output from the 
variable frequency oscillator to an input of the comparator, for phase 
locking the loop to the reference frequency; quadrature signal generating 
means, being operatively connected to a source of modulation frequencies, 
for generating first and second quadrature frequencies from the modulation 
frequencies; and mixing means, having first and second quadrature input 
terminals that are operatively connected to respective ones of the 
quadrature frequencies, and being interposed into the feedback path with a 
third input terminal that is operatively connected to the feedback path 
proximal to the variable frequency oscillator, and with an output terminal 
that is operatively connected to the feedback path distal from the 
variable frequency oscillator, for mixing the quadrature frequencies with 
a signal derived from the output of the variable frequency oscillator. 
In a second aspect of the present invention, an electrical device is 
provided which comprises reference frequency oscillator means for 
supplying a reference frequency; phase locking oscillator means including 
a loop with a forward path that includes a comparator being connected to 
the reference frequency oscillator means, and a variable frequency 
oscillator that is operatively connected to the comparator, and with a 
feedback path that feeds a feedback signal, related to an output from the 
variable frequency oscillator back to an input of the comparator, for 
phase locking the loop to the reference frequency; dual modulus divider 
means, being interposed into the feedback path, for dividing a signal 
derived from the output of the variable frequency oscillator by lower and 
higher dividing ratios; modulus controller means, being connected to the 
dual modulus divider means, and including "A" and "N" inputs, for making 
the dual modulus divider means divide at one of the ratios "A" times and 
divide at the other of the ratios "N" times; a source of modulation 
frequencies; means, being operatively connected to the source of 
modulation frequencies and to one of the inputs of the modulus controller 
means, for changing, as a function of the modulation frequencies, the 
number of times that the dual modulus divider means divides at one of the 
dividing ratios; and the operative connection of the changing means to the 
source of modulation frequencies and to the one input of the modulus 
controller means comprises synchronizer means for synchronizing the 
changing of dividing ratios with completion of a division at one of the 
dividing ratios. 
In a third aspect of the present invention, a method is provided for D.C. 
modulating the output frequency of a loop with a forward path that 
includes a comparator receiving an input frequency and a variable 
frequency oscillator that is operatively connected to the comparator, and 
with a feedback path that feeds a feedback signal, related to an output of 
the variable frequency oscillator, to an input of the comparator, and that 
is phase locked to the input frequency, which method comprises accessing 
modulation frequencies; using the modulation frequencies to generate 
quadrature frequencies; and mixing the quadrature frequencies with a 
signal in the feedback path derived from the output of the variable 
frequency oscillator. 
In a fourth aspect of the present invention, a method is provided for D.C. 
modulating the output frequency of a loop with a forward path that 
includes a comparator receiving an input frequency and a variable 
frequency oscillator that is operatively connected to the comparator, and 
with a feedback path that feeds a feedback signal, related to an output of 
the variable frequency oscillator, to an input of the comparator, and that 
is phase locked to the input frequency, which method comprises dividing a 
frequency in the feedback path, derived from the output of the variable 
frequency oscillator, by lower and higher dividing ratios; controlling the 
number of times that the dividing step is performed at the lower and 
higher dividing ratios; accessing modulation frequencies; using the 
modulation frequencies to change the number of times the dividing step is 
performed at one of the ratios; and synchronizing the changing of the 
number of times the dividing step is performed at one of the ratios with 
completion of a division at one of the ratios. 
The QPSK mixer produces both sideband frequencies, attenuates one of the 
sideband frequencies, and delivers a frequency to the feedback path that 
is lower than the frequency received by the QPSK mixer by a function of 
the modulation frequencies, thereby providing D.C. modulation of the 
feedback path and D.C. modulation of the output of the electrical device. 
In a twelfth aspect of the invention, a method is provided for controlling 
the output frequency of a loop that includes both a forward path and a 
feedback path, and that is phase locked to a reference frequency, which 
method includes accessing modulation frequencies, using the modulation 
frequencies to develop quadrature frequencies, and mixing the quadrature 
frequencies with the frequencies in the feedback path. 
In a thirteenth aspect of the invention, an electrical device includes a 
reference frequency oscillator for supplying a reference frequency; a 
phase locking oscillator, being connected to the reference frequency 
oscillator, and including a loop with a forward path and a feedback path, 
for phase locking the loop to the reference frequency; a dual modulus 
divider, being interposed into the feedback path, for dividing the 
frequency in the feedback path by lower and higher dividing ratios; a 
modulus controller, being connected to the dual modulus divider, and 
having "A" and "N" inputs, for making the dual modulus divider divide at 
one of the ratios "A" times and divide at the other of the ratios "N" 
times; and an adding device, being operatively connected to a source of 
modulation frequencies and to one of the inputs, for changing the number 
of times that the dual modulus divider divides at one of the dividing 
ratios. 
In a fourteenth aspect of the invention, a method is provided for 
controlling the output frequency of a loop that includes both a forward 
path and a feedback path, and that is phase locked to a reference 
frequency, which method includes dividing the frequency in the feedback 
path by lower and higher dividing ratios; controlling the number of times 
that the dividing step is performed at the lower and higher ratios; 
accessing modulation frequencies; and using the modulation frequencies to 
change the number of times that the dividing step is performed at one of 
the ratios. 
In various other aspects of the invention, the frequency of the pulses in 
the feedback path are changed as a function of the frequency of a 
modulation oscillator: by reducing the frequency in the feedback path, by 
increasing the frequency in the feedback path, by preventing a change in a 
signal level in the feedback path for the duration of one of the pulses 
therein, by preventing a high from occurring during one pulse in the 
feedback path, by preventing a low from occurring between two pulses in 
the feedback path, or by changing the frequency of the pulses in the 
feedback path by a number that is larger or smaller than the frequency of 
the modulation amplifier, whether by means of a shift register, a dual 
modulus divider, a parallel adder, a quadrature frequency generator, a 
quadrature phase shift keying mixer, and/or a prescaling divider.

DESCRIPTION OF THE PREFERRED EMBODIMENTS 
Referring now to FIG. 1, in the most basic configuration of the prior art, 
a phase locked oscillator 10 includes a phase locked loop 12 with both a 
forward path 14 and a feedback path 16. The forward path 14 includes a 
forward path conductor 18, and both an integrator 20 and a variable 
frequency oscillator, or voltage controlled oscillator, 22 that are 
interposed into the conductor 18. The voltage controlled oscillator 22 
includes both a control input 21 and an output 23; and connections in the 
forward path 14 include the control input 21 of the voltage controlled 
oscillator 22 being connected to the integrator 20 by the forward path 
conductor 18. 
Also, the phase locked oscillator 10 includes a crystal controlled 
reference oscillator, or reference frequency oscillator, 24 and a phase 
detector, or comparator, 26. An input 25 of the phase detector 26 is 
connected to the crystal controlled reference oscillator 24, an output 27 
of the phase detector 26 is connected to the forward path 14, and an input 
29 of the phase detector 26 is connected to the feedback path 16 by a 
feedback conductor 28. 
The output 23 of the variable frequency oscillator 22 is connected to an 
output conductor 30; and the output conductor 30 is connected to the 
feedback conductor 28. Thus, the output conductor 30, feeds back the 
output frequency of the variable frequency oscillator 22 as a feedback 
signal through the feedback conductor 28 to the input 29 of the phase 
detector 26. The phase detector 26 performs a time comparison between the 
leading edge of the phase of the feedback signal and the leading edge of 
the reference frequency that is supplied by the crystal controlled 
reference oscillator 24, and supplies this difference to the integrator 
20. 
The integrator 20 then controls the frequency of the voltage controlled 
oscillator 22 by supplying voltages thereto that are in accordance with 
integrated time differences between the leading edges of the phases of the 
feedback signal and the reference frequency. The effect is that the 
frequency of the output is phase locked to the frequency of the crystal 
controlled reference oscillator 24. 
Referring now to FIG. 2, a phase locked oscillator 32 includes like-named 
and like-numbered components as recited for FIG. 1, and in addition, the 
FIG. 2 embodiment includes a dual modulus divider 34 and a prescaling 
divider 36. 
When the prescaling divider 36 is included in the circuitry of FIG. 2, but 
the dual modulus divider 34 is omitted, the output is divided by some 
number, perhaps sixteen, so that a feedback signal, having generally the 
form of a square wave, is produced whose frequency is lower than that of 
the output. This reduction in the frequency of the feedback signal allows 
the use of a crystal controlled reference oscillator 24 having a frequency 
that is less, in this example one-sixteenth, of the output. 
In operation, assuming a dividing ratio of sixteen to one, a reduction in 
frequency of one cycle in the feedback path 16 requires an increase in 
frequency of sixteen Hertz in the output conductor 30 to phase lock the 
feedback path 16 to the crystal controlled reference frequency. 
When the prescaling divider 36 is omitted from the schematic of FIG. 2, but 
the dual modulus divider 34 is included, the output frequency is divided, 
selectively, by two different dividing ratios, such as 40 and 41. 
The dividing ratios of the dual modulus divider 34 are controlled by a 
signal in a modulus control conductor 38 by a modulus controller which 
will be shown and described in more detail in conjunction with another 
drawing. 
By using the dual modulus divider 34, the frequency of the output can be 
channelized, and yet the frequency of the output will be closely 
controlled by the crystal controlled reference frequency, thereby avoiding 
frequency drift in the output, except for the small drift of the crystal 
(not shown) in the crystal controlled reference oscillator 24. An example 
of the use of the dual modulus divider to achieve channelization is 
included with the discussion of FIG. 3. 
Referring now to FIG. 3, in a phase locked oscillator 40 the prior art 
embodiment of FIG. 2 is constructed using an integrated chip 42. 
Preferably, the integrated chip 42 is of the type built by Motorola which 
is numbered 45152 by the manufacturer, and which is shown in FIG. 11. 
The integrated chip 42 includes a reference oscillator 44 that cooperates 
with a crystal 46 to form the crystal controlled reference oscillator 24 
of FIG. 2; and the chip 42 includes the phase detector 26 of FIG. 2. 
The integrated chip 42 further includes a variable modulus divider 48 that 
controls the number of times that the dual modulus divider 34 divides by 
the lower dividing ratio, and divides by the higher dividing ratio; and 
the integrated chip 42 includes a modulus controller 50 that controls the 
change from the lower dividing ratio to the higher dividing ratio to 
correspond to completion of any given dividing step. 
In the FIG. 3 embodiment, the integrator 20 of FIG. 2 consists, in 
simplified form, of an operational amplifier 52 and a capacitor 54. 
While the prescaling divider 36 of FIG. 2 is not included in FIG. 3, it 
could be included if desired, and the operation of the circuitry would be 
as described for FIG. 2. 
Channelization of the output of the voltage controlled oscillator 22 by the 
dual modulus divider 34 is accomplished as shown in the following example. 
To channelize a transmitter starting at 400 MHz with channel steps of 100 
KHz: the dual modulus divider 34, with dividing ratios of 40 and 41, 
divides the 400 MHz output by 40 for 100 times; and a frequency of 100 KHz 
is fed back to the phase detector 26. With a reference oscillator 44 
having a reference frequency of 100 KHz, the frequency of the voltage 
controlled oscillator 22 will be adjusted until the output frequency in 
the output conductor 30 is equal to the product of 40 times 100, times the 
reference frequency of the reference oscillator 24, or 
40.times.100.times.100 KHz=400 MHz. 
To achieve the first channelized frequency above 400 MHz, the N counter of 
the integrated chip 42 of FIG. 3 is set to 99 so that the dual modulus 
divider 34 divides by 40 for 99 times; and the A counter is set to divide 
by 41 once. 
When the dual modulus divider 34 divides the 400 MHz by 40 for 99 times, 
and by 41 for one time, for the loop 12 to phase lock, the phase detector 
26 and the integrator 20 must increase the frequency of the voltage 
controlled oscillator 22 to be equal to 
[(40.times.99)+(41.times.1)].times.100 KHz, or 400.1 MHz. 
Therefore, reducing the number of times that the dual modulus divider 34 
divides by 40, and equally increasing the number of times that the dual 
modulus divider 34 divides by 41, results in channelization in steps of 
100 KHz. 
While a reference frequency of 100 KHz has been used in the above examples 
for ease of computation, in a preferred embodiment a reference frequency 
of 31,250 Hertz is used. 
Referring now to FIG. 4, in a first embodiment of the present invention, an 
electrical device, or D.C. modulated phase locked oscillator 60, includes 
like-named and like-numbered components as described in conjunction with 
FIG. 2, except that the prescaling divider 36 is omitted, and except for 
additional components that will be described. 
In addition to like-named and like-numbered components of FIG. 2, the 
electrical device 60 of FIG. 4 includes a synchronizer 62 and a variable 
frequency oscillator, or voltage controlled oscillator, 64 which will be 
referred to herein as a modulation oscillator, and which preferably is an 
audio oscillator. 
In operation, the modulation oscillator 64 and the synchronizer 62 
cooperate to control the dual modulus divider 34, such that for each cycle 
of the modulation oscillator 64, the dual modulus divider 34 divides by 
the higher dividing ratio. 
If the dual modulus divider 34 has dividing ratios of 40 and 41, and if the 
modulation oscillator 64 has an output frequency of 100 Hertz, then the 
dual modulus divider 34 will divide the feedback signal in the feedback 
conductor 28 by 40, except for 100 times in any given second; and the dual 
modulus divider 34 will divide the feedback signal by 41 for 100 times 
each second. 
Each time the dual modulus divider 34 divides by the higher dividing ratio, 
one pulse will be removed from the feedback path 16, and the phase 
detector 26 will cooperate with the integrator 20 and the voltage 
controlled oscillator 22 to increase the output frequency by one cycle. 
Or, as in the example of a modulation oscillator 64 operating at one 
hundred Hertz, one hundred pulses will be removed from the feedback path 
16 each second; and the output frequency in the output conductor 30 will 
be increased by one hundred Hertz. 
Since the modulation oscillator 64 is of the voltage controlled type and is 
D.C. modulated, and since the phase detector 26 and the integrator 20 
cooperate to phase lock the feedback signal to the crystal controlled 
reference frequency, the output frequency must increase to keep the loop 
12 phase locked, and the result is that the output frequency is D.C. 
modulated. 
Since the output frequency is not only D.C. modulated, but also is crystal 
referenced, the present invention provides means for producing a crystal 
referenced output that is D.C. frequency modulated. 
The D.C. frequency modulated output, being now crystal referenced, has the 
inherent frequency stability of a crystal; and, since the frequency of the 
modulation oscillator 64 is quite low, the frequency drift of the 
modulation oscillator 64, being a function of frequency, is also quite 
low. Therefore, the combined frequency drift of the crystal controlled 
reference oscillator 24 and the modulation oscillator 64 is extremely low. 
Continuing to refer to FIG. 4, the synchronizer 62 holds a cycle received 
from the modulation oscillator 64 until it receives a division completion 
signal from a conductor 66 that connects the dual modulus divider 34 to 
the synchronizer 62. Then the synchronizer 62 delivers a modulus control 
signal to a modulus control conductor 68 that changes the dividing ratio 
of the dual modulus divider 34 from the lower dividing ratio to the higher 
dividing ratio. 
It should be understood that a phase locking oscillator 70 of the FIG. 4 
embodiment includes the phase locked loop 12 with both the forward path 14 
and the feedback path 16, the voltage controlled oscillator 22 and the 
integrator 20 in the forward path 14, the crystal controlled reference 
oscillator 24, and the phase detector 26 that is connected to the 
reference oscillator 24 and to both the forward path 14 and the feedback 
path 16. 
Further, it should be understood that a D.C. modulator 72 of the FIG. 4 
embodiment includes the dual modulus divider 34, the synchronizer 62, and 
the modulation oscillator 64, all of which are operatively connected to 
the feedback path 16. 
Referring now to FIG. 5, in a second embodiment of the present invention, 
an electrical device, or D.C. modulated phase locked oscillator, 80 
includes like-named and like-numbered components as described in 
conjunction with FIG. 4. In addition, the embodiment of FIG. 5 includes 
the prescaling divider 36 of FIG. 2, a summing resistor 82, a summing 
resistor 84, a modulation conductor 86, and a modulation conductor 88. 
The operation of the FIG. 5 embodiment is similar to that described for 
FIG. 4. The primary difference is that both the forward path 14 and the 
feedback path 16 are modulated. That is, both the modulation oscillator 64 
and the voltage controlled oscillator 22 are D.C. modulated. 
The modulation conductor 86 conducts a D.C. modulation signal to the 
modulation oscillator 64; and the modulation conductor 88 conducts the 
modulation signal to the summing resistor 84. 
The difference in the phase of the frequency of the feedback signal in the 
feedback path 16 and the phase of the reference frequency of the crystal 
controlled reference oscillator 24 produces an error signal that is fed to 
the integrator 20, the integrator 20 feeds an integrated error signal to 
the summing resistor 82, a modulation signal is fed to the summing 
resistor 84, and the signals to the summing resistors 82 and 84 are 
algebraically added to control the frequency of the voltage controlled 
oscillator 22. 
If the feedback path 16 were not modulated so that only the modulation 
signal of the modulation conductor 88 were connected to the voltage 
controlled oscillator 22, the phase locking of the loop 12 would cancel 
the frequency modulation of the output. Therefore, the frequency of the 
output could be A.C. modulated only, and then only if the modulation 
frequency were higher than the natural frequency of the loop 12. 
If only the feedback path 16 is modulated, as in FIG. 4, D.C. frequency 
modulation of the output is achieved, but the frequency response is 
limited by the natural frequency of the loop 12. 
Then, to achieve frequency modulation of the output, the phase detector 26 
must sense the difference in the frequency between the feedback path 16 
and the frequency of the crystal controlled reference oscillator 24, the 
integrator 20 must integrate the phase differences, the frequency of the 
voltage controlled oscillator 22 must be changed in accordance with the 
integrated phase differences, and the phase detector 26 must phase lock 
the feedback path 16 to the reference frequency of the crystal controlled 
reference oscillator 24. 
However, in the FIG. 5 embodiment, both the forward path 14 and the 
feedback path 16 are modulated substantially simultaneously, thereby 
achieving not only D.C. modulation of the output, but also essentially 
unlimited frequency response. 
Referring again to FIG. 5, the inclusion of both the prescaling divider 36 
and the dual modulus divider 34 decreases the required frequency of the 
crystal controlled reference oscillator 24, and decreases the required 
frequency of the modulation oscillator 64. While reducing the required 
frequency of the modulation oscillator 64 is advantageous in that the 
frequency of the modulation oscillator 64 is lowered, and the frequency 
drift thereof is reduced, the phase locking time is increased as the 
feedback frequency is decreased. 
It should be understood that a phase locking oscillator 90 of the FIG. 5 
embodiment includes the phase locked loop 12 with both the forward path 14 
and the feedback path 16, the voltage controlled oscillator 22 and the 
integrator 20 in the forward path 14, the prescaling divider 36 in the 
feedback path 16, the crystal controlled reference oscillator 24, and the 
phase detector 26 that is connected to the reference oscillator 24 and to 
both the forward path 14 and the feedback path 16. 
Further, it should be understood that a D.C. modulator 92 of the FIG. 5 
embodiment includes the dual modulus divider 34, the synchronizer 62, and 
the modulation oscillator 64, all of which are operatively connected to 
the feedback path 16; and the modulator 92 further includes the summing 
resistors, 82 and 84, and the modulation conductors, 86 and 88. 
Referring now to FIG. 6, in a third embodiment of the present invention, an 
electrical device, or D.C. modulated phase locked oscillator, 100 includes 
like-named and like-numbered components as described in conjunction with 
FIGS. 1-4. 
The electrical device 100 of FIG. 6 produces a crystal referenced output 
that is D.C. modulated, as has been described for the FIG. 5 embodiment, 
and the device 100 provides substantially simultaneous modulation of both 
the forward path 14 and the feedback path 16, also as described for the 
FIG. 5 embodiment. 
In addition, the electrical device 100 of FIG. 6 provides channelization of 
the output frequency as well as D.C. modulation of the output frequency. 
Both D.C. modulation and channelization of the output frequency are 
achieved by controlling the dual modulus divider 34 by two separate means. 
More particularly, channelization is achieved by controlling the dual 
modulus divider 34 by the variable modulus divider 48 and the modulus 
controller 50 in the integrated chip 42; and D.C. modulation is achieved 
by controlling the dual modulus divider 34 by the modulation oscillator 
64. 
The function of the synchronizer 62 of FIG. 4 is achieved in FIG. 6 by a 
synchronizer 101 which consists of first and second flip-flops, 102 and 
104, and by an OR gate 106. 
When a cycle, or pulse removing signal, is delivered to a clock terminal 
108 of the flip-flop 102 by the modulation oscillator 64, an output 
terminal, or Q terminal, 110 is energized, thereby energizing an input 
terminal, or D terminal, 112 of the flip-flop 104. The pulse removing 
signal from the modulation oscillator 64 is held by the flip-flop 102 
until the flip-flop 102 is reset by a signal to a reset terminal 114. 
Assuming that the dual modulus divider 34 has been dividing the feedback 
signal in the feedback path 16 by one or the other of the dividing ratios, 
when the dual modulus divider 34 has finished performing a dividing 
operation which is done to achieve channelization, a pulse in a conductor 
116 is directed to a clock terminal 118 of the flip-flop 104 and to the 
modulus controller 50 of the integrated chip 42. 
With energizing of the clock terminal 118, a modulus control signal is sent 
from a Q terminal, or output terminal, 120 of the flip-flop 104 to the 
dual modulus divider 34 via the OR gate 106 and a conductor 122, thereby 
changing the dividing ratio of the dual modulus divider 34 from the lower 
dividing ratio to the higher dividing ratio for one dividing cycle, and 
thereby removing one pulse from the feedback path 16. 
Completion of the next dividing cycle sends a signal in the conductor 116 
to the modulus controller 50; and the modulus controller 50 sends a reset 
signal to a reset terminal 124 of the flip-flop 104 via a conductor 126, 
and sends a modulus control signal to the dual modulus divider 34 via the 
conductor 126, the OR gate 106, and the conductor 122. 
Also, as a signal is sent from the Q terminal 120 of the flip-flop 104 to 
the OR gate 106 and to the dual modulus divider 34, a reset signal is sent 
from the Q terminal 120 of the flip-flop 104 to the reset terminal 114 of 
the flip-flop 102, thereby resetting the flip-flop 102. 
Thus, it can be seen that a synchronizer 62, consisting of the flip-flops, 
102 and 104, and the OR gate 106, cooperates with the modulus controller 
50 to prevent simultaneous control of the dual modulus divider 34 by the 
variable modulus divider 48, which provides channelization of the output 
frequency, and simultaneous control of the dual modulus divider 34 by the 
modulation oscillator 64 which provides D.C. modulation of the output 
frequency of the electrical device 100. 
It should be understood that, in the FIG. 6 embodiment, the electrical 
device, or D.C. modulated phase locked oscillator, 100 includes a phase 
locking oscillator 128 for producing a phase locked output, and a D.C. 
modulator 130 for D.C. modulating the output frequency of the phase 
locking oscillator 128. 
Also, it should be understood that the phase locking oscillator 128 of the 
FIG. 6 embodiment includes the phase locked loop 12 with both the forward 
path 14 and the feedback path 16, the voltage controlled oscillator 22, 
the operational amplifier 52 and the capacitor 54 which cooperate to 
provide the integrator 20, the prescaling divider 36, the crystal 46, and 
the integrated chip 42. 
The portions of the integrated chip 42 that are included in the phase 
locking oscillator 128 are: the reference oscillator 44 which cooperates 
with the crystal 46 to provide the crystal controlled reference oscillator 
24, the phase detector 26, the variable modulus divider 48, and the 
modulus controller 50. 
Finally, it should be understood that the modulator 130 of the FIG. 6 
embodiment includes the dual modulus divider 34, the flip-flops, 102 and 
104, which cooperate with the OR gate 106 to function as the synchronizer 
62 of FIGS. 4 and 5, and the modulation oscillator 64, all of which are 
operatively connected to the feedback path 16. The modulator 130 of FIG. 6 
also includes the summing resistors, 82 and 84, and the modulation 
conductors, 86 and 88. 
As stated above, the dual modulus divider 34 is a part of the modulator 
130; but also, the dual modulus divider 34 is a part of the phase locking 
oscillator 128 as the dual modulus divider 34 cooperates with the variable 
modulus divider 48 and the modulus controller 50 to provide channelization 
of the phase locking oscillator 128. 
Referring now to FIG. 7, in a fourth embodiment of the present invention, 
an electrical device, or D.C. modulated phase locked oscillator, 140 
includes a shift register 142 in a synchronizer 143 in addition to the 
flip-flops, 102 and 104. Further, the synchronizer 143 of the embodiment 
includes the OR gate 106, and AND gate 144, and an inverter 146. 
More specifically, the shift register 142 includes the flip-flops, 102 and 
104, for achieving the synchronizing functions, and any desired number of 
flip-flops 148 which cooperate with each other to remove more than one 
pulse from the feedback path 16 for each cycle of the modulation 
oscillator 64. 
Thus, the shift register 142 provides means for removing a plurality of 
pulses from the feedback path 16 for each cycle of the modulation 
oscillator 64. Therefore, the shift register 142 allows the frequency of 
the modulation oscillator 64 to be relatively low for a given range of 
frequency modulation of the output, and yet allows the frequency of the 
crystal controlled reference oscillator 24 to remain relatively high, 
thereby assuring rapid phase locking together with an adequate range of 
frequency modulation. 
Further, the shift register 142, in allowing the frequency of the 
modulation amplifier to be quite low, keeps the frequency drift of the 
modulation oscillator 64 extremely low, so that the combined drift of the 
modulation oscillator 64 and the crystal controlled reference oscillator 
24 are only a fraction of prior art designs. 
The operation of the electrical device, or D.C. modulated phase locked 
oscillator, 140 of FIG. 7 differs from the operation of the FIG. 6 
embodiment primarily in the multiple pulse removing of the shift register 
142, and in circuitry that is added to inhibit a clock terminal 150 of the 
shift register 142 when there is conflict between control of the dual 
modulus divider 34 by the modulus controller 50, and control of the dual 
modulus divider 34 by the shift register 142. 
More particularly, the clock terminal 150 of the shift register 142 is 
inhibited by the AND gate 144 and the inverter 146 from receiving a signal 
from the conductor 116, except when a signal provided by the inverter 146 
in a conductor 152 is applied to the AND gate 144 simultaneously with a 
signal in the conductor 116 from the dual modulus divider 34. 
It should be understood that, in the FIG. 7 embodiment, the D.C. modulated 
oscillator 140 includes a phase locking oscillator 154 for producing a 
phase locked output, and a D.C. modulator 156 for D.C. modulating the 
output frequency of the phase locking oscillator 154. 
Also, it should be understood that the phase locking oscillator 154 of the 
FIG. 7 embodiment includes the phase locked loop 12 with both the forward 
path 14 and the feedback path 16, the voltage controlled oscillator 22, 
the operational amplifier 52 and the capacitor 54 which cooperate to 
provide the integrator 20, the crystal 46, and the integrated chip 42. 
Portions of the integrated chip 42 that are included in the phase locking 
oscillator 154 are the reference oscillator 44 which cooperates with the 
crystal 46 to provide the crystal controlled reference oscillator 24, the 
phase detector 26, the variable modulus divider 48, and the modulus 
controller 50. 
Further, it should be understood that the modulator 156 of the FIG. 7 
embodiment includes the dual modulus divider 34, the shift register 142 
which cooperates with the OR gate 106, the AND gate 144, and the inverter 
146 to function as the synchronizer 62 of FIGS. 4 and 5, and the 
modulation oscillator 64, all of which are operatively connected to the 
feedback path 16. The modulator 156 of FIG. 7 also includes the summing 
resistors, 82 and 84, and the modulation conductors, 86 and 88. 
The dual modulus divider 34 functions as a part of the modulator 156 to 
achieve D.C. modulation of the output frequency, and also functions as a 
part of the phase locking oscillator 154 to provide channelization of the 
phase locking oscillator 154. 
Referring now to FIG. 8, an electrical device, or D.C. modulated phase 
locked oscillator, 160 includes components generally as named, numbered, 
and described in conjunction with the embodiment of FIG. 6. 
However, the electrical device 160 of FIG. 8 does not include the 
prescaling divider 36, the dual modulus divider 34, the flip-flop 104, the 
integrated chip 42, or the OR gate 106 of the FIG. 6 embodiment. 
Instead, the electrical device 160 of FIG. 8 includes an integrated chip 
162, a flip-flop 164, a resistor 166, and a diode 168. The integrated chip 
162 is of the type manufactured by Motorola under the number 45151 which 
is shown in FIG. 12. The integrated chip 162 includes the reference 
oscillator 44, the phase detector 26, and the variable modulus divider 48, 
all of which function as described for the integrated chip 42. The 
flip-flop 164 includes a D input terminal 170, a Q output terminal 172, a 
NOT-Q output terminal 174, and a clock terminal 176. 
In operation, when the flip-flop 164 is in the unclocked state, the NOT-Q 
output terminal 174 is high, and the diode 168 prevents this high from 
reaching a feedback conductor 178, so that all pulses from the output 
conductor 30 are fed back to the integrated chip 162. 
However, when the modulation oscillator 64 produces a pulse, the flip-flop 
102 is clocked, thereby producing a high at the output terminal 110 which 
is delivered to the input terminal 170 of the flip-flop 164. When the next 
pulse from the output conductor 30 and the feedback conductor 28 is 
applied to the clock terminal 176 of the flip-flop 164, the flip-flop 164 
is clocked to the state wherein the Q output terminal 172 is high and the 
NOT-Q output terminal 174 is low. With the NOT-Q output terminal 174 low, 
the pulse delivered to the feedback conductor 28 is pulled down by the 
resistor 166 and the connection of the conductor 178 to the low of the 
NOT-Q output terminal 174 via the diode 168. 
At substantially the same time, the flip-flop 164, being clocked by the 
output pulse at the clock terminal 176, delivers a high from the output 
terminal 172 to the reset terminal 114 of the flip-flop 102, thereby 
resetting the flip-flop 102 for receiving the next pulse from the 
modulation oscillator 64. 
Therefore, for each pulse of the modulation oscillator 64, one pulse is 
removed from the feedback path 16. That is, one pulse is dissipated, or 
prevented from reaching, the integrated chip 162; and the phase detector 
26 cooperates with the integrator 20 to increase the output frequency of 
the voltage controlled oscillator 22 to increase the output frequency by 
one Hertz. 
It should be understood that the electrical device 160 includes a phase 
locking oscillator 180 and a D.C. modulator 182. The phase locking 
oscillator 180 includes the voltage controlled oscillator 22, the crystal 
controlled reference oscillator 24, the phase detector 26, and the 
variable modulus divider 48. The D.C. modulator 182 includes the 
modulation oscillator 64, the flip-flops 102 and 164, the resistor 166, 
the diode 168, and the resistors 82 and 84. Further, the flip-flops, 102 
and 164, cooperate with the diode 168 and the resistor 166 to provide a 
synchronizer 184. 
Referring now to FIG. 9, an electrical device, or D.C. modulated phase 
locked oscillator, 190 includes components generally as named, numbered, 
and described in conjunction with the embodiment of FIG. 6. 
However, the electrical device 190 of FIG. 9 does not include the OR gate 
106 of the FIG. 6 embodiment. Instead, the electrical device 190 of FIG. 9 
includes the resistor 166 and the diode 168 of FIG. 8. 
In operation, when the flip-flop 104 is in the unclocked state, the diode 
168 blocks current flow to the output terminal 120; and the circuitry 
functions as described for FIG. 6. 
However, when the modulation oscillator 64 produces a pulse, the flip-flop 
102 is clocked, producing a high at the output terminal 110 and energizing 
the input terminal 112 of the flip-flop 104. Then, when the dual modulus 
divider 34 finishes a division by one of the dual dividing ratios, it 
delivers a pulse to the conductor 116, clocking the flip-flop 104. 
With the flip-flop 104 clocked, a high is produced at the output terminal 
120 of the flip-flop 104; and this high at the output terminal 120 is used 
to reset flip-flop 102 in preparation for another pulse from the 
modulation oscillator 64. 
In addition, this high from the output terminal 120 is delivered to the 
conductor 178, making the conductor 178 high. With the output terminal 120 
connected to the conductor 178 through the diode 168, and with the 
resistor 166 being interposed between the conductors 178 and 116, the 
conductor 178 is kept high as the conductor 116 goes low between pulses. 
The result is, by preventing a low in the conductor 178 between two pulses 
delivered to the conductor 116 by the dual modulus divider 34, two pulses 
are combined into one; and in effect, one pulse is removed from the 
feedback path 16 in the conductor 178. 
Removing one pulse from the conductor 178 effectively removes a number of 
pulses from the feedback path 16 that is equal to the dividing ratio of 
the prescaling divider 36 times the lower dividing ratio of the dual 
modulus divider 34. 
For instance, if the prescaling divider 36 has a dividing ratio of 16, and 
if the lower dividing ratio of the dual modulus divider 34 is 20, then 
each pulse of the modulation oscillator 64 removes 16 times 20, or 320 
pulses from the feedback path 16. Therefore, to increase the output of the 
voltage controlled oscillator 22 by 10 MHz, the required frequency of the 
modulation oscillator 64 would be 31,250 Hertz. 
Notice that in this manner extremely wide frequency deviations can be 
achieved. This is, of course, at the expense of increased drift since the 
modulation oscillator drift is multiplied by the ratio shown above, that 
is, 320. In the example shown, a typical drift of 30 KHz at the output 
could be caused by the drift of the modulation oscillator 64 when 
multiplied by 320. This drift is still well within the drift allowed from 
transmitters which would use this wider deviation capability. 
The electrical device 190 of FIG. 9 provides a much greater frequency 
deviation for a given frequency of the modulation oscillator 64 than does 
the electrical device 140 of FIG. 7, since a counter or a shift register, 
such as the shift register 142, removes only a small number of plurality 
of pulses from the feedback path 16 for each pulse of the modulation 
oscillator 64. More specifically, if the shift register 142 removes 10 
pulses from the feedback path 16 for each cycle of the modulation 
oscillator 64, the electrical device 190, in removing 320 pulses from the 
feedback path 16 for each cycle of the modulation oscillator 64, removes 
32 times as many pulses from the feedback path 16 for each cycle of the 
modulation oscillator 64. 
Further, as previously noted, since the frequency drift of a voltage 
controlled oscillator, such as the modulation oscillator 64, is smaller, 
as a percentage of output frequency, for lower frequencies, the total 
drift of the D.C. modulated oscillator 190 as described herein is less 
when a plurality of pulses are removed from the feedback path 16 for each 
cycle of the modulation oscillator 64, and the frequency of the modulation 
oscillator 64 is reduced. 
The pulse removal, or pulse combining, as described in conjunction with 
FIG. 9, must be prohibited when the dual modulus divider 34 is in the 
higher mode to prevent an incorrect output frequency. To prevent the pulse 
removing function from removing a pulse resulting from division at the 
higher dividing ratio, the conductor 126 is connected to the flip-flop 104 
in addition to being connected to the dual modulus divider 34. This 
connection of the conductor 126 to the flip-flop 104 provides 
synchronization of the modulating and dividing functions as described 
previously. 
It should be understood that the electrical device 190 of FIG. 9 includes a 
phase locking oscillator 192 and a D.C. modulator 194. The phase locking 
oscillator 192 includes the voltage controlled oscillator 22, the crystal 
controlled reference oscillator 24, the phase detector 26, the variable 
modulus divider 48, and the modulus controller 50. The D.C. modulator 194 
includes the modulation oscillator 64, the flip-flops 102 and 104, the 
resistor 166, the diode 168, and the resistors 82 and 84. A synchronizer 
196 of the FIG. 9 embodiment includes the flip-flops, 102 and 104, the 
resistor 166, and the diode 168. The synchronizer 196 cooperates with the 
modulus control conductor 126 to provide the synchronizing function, as 
described previously. 
Referring again to FIG. 6, if the dual modulus divider 34 were set so that 
the normal state were to divide at the higher dividing ratio, rather than 
normally to divide at the lower dividing ratio, then, in effect, one pulse 
would be added to the feedback path 16, rather than removed therefrom. 
That is, if the dual modulus divider 34 were dividing by a dividing ratio 
of 21, and then dividing at the ratio of 20 once per second, the frequency 
in the feedback path 16, as supplied to the phase detector 26, would be 
increased by one pulse per second; and the phase detector 26 and the 
integrator 20 would cooperate with the voltage controlled oscillator 22 to 
reduce the output frequency by one Hertz. 
Of course, to obtain an increase in the output frequency as a function of 
the frequency of the modulation oscillator 64, with the dividing ratios 
inverted as noted above, would require providing an inverted D.C. 
modulation voltage to the modulation oscillator 64, while continuing to 
supply an uninverted D.C. modulation voltage to the resistor 84. 
It is important to notice that D.C. modulation of a phase locked loop is 
achieved in the present invention by either removing pulses from the 
feedback path 16 or adding pulses to the feedback path 16. 
Removal of pulses is achieved by increasing the dividing ratio of the dual 
modulus divider 34 once for each cycle of the modulation oscillator 64 as 
shown in FIG. 6, by increasing the dividing ratio a plurality of times for 
each cycle of the modulation oscillator 64 as shown in FIG. 7, by removing 
a very large number of pulses from the feedback path 16 when both the 
prescaling divider 36 is included and one output pulse is eliminated, as 
shown in FIG. 9, or by removing many pulses from the feedback path 16 by 
eliminating one output pulse from a circuit in which either the dual 
modulus divider 34 or the prescaling divider 36 is included. 
Removal of pulses, or elimination of pulses, is achieved by preventing a 
high from passing though the resistor 166 of FIG. 8, thereby removing a 
pulse by dissipating it through the resistor 166 to a low of the NOT-Q 
output terminal 174. 
Also, removal of pulses is achieved by preventing a low from appearing in 
the conductor 178 of FIG. 9 by placing a high in the conductor 178 from 
the output terminal 120, through the diode 168, and into the conductor 
178, while isolating the high in the conductor 178 from a low in the 
conductor 116 by the resistor 166 for one cycle. 
Or, stated more broadly, the use of the resistor 166 and the diode 168 
prevents a change in the signal level in the feedback path 16. 
In FIGS. 4 and 5, the synchronizer 62 is shown symbolically. In the FIG. 6 
embodiment, the synchronizer 62 includes the flip-flops 102 and 104, the 
OR gate 106, and the modulus controller 50 of the integrated chip 42. In 
the FIG. 7 embodiment, the synchronizer 62 includes the flip-flops 102 and 
104, the OR gate 106, the AND gate 144, the inverter 146, and the modulus 
controller 50. In the FIG. 8 embodiment, the synchronizer 62 includes the 
flip-flops 102 and 164. And, in the FIG. 9 embodiment, the synchronizer 62 
includes the flip-flops 102 and 104, and the modulus controller 50. 
Referring now to FIG. 10, a radio frequency receiver, or signal processing 
apparatus, 200 comprises an input stage 202, an I.F. stage 203, a 
demodulator 204 that includes the I.F. stage 203, an rf mixer 210, the 
phase locking oscillator 128 of FIG. 6, and the modulator 130 of FIG. 6. 
The input stage 202 includes an rf preselector 206 and an rf amplifier 208; 
and the I.F. stage 203 includes an I.F. amplifier/filter 212, a local 
mixer 214, and a local oscillator 216. 
More particularly, the input stage 202 is connected to a first input 213 of 
the rf mixer 210, the phase locking oscillator 128 is connected to a 
second input 215 of the rf mixer 210, and the I.F. amplifier/filter 212 of 
the I.F. stage 203 is connected to an output 217 of the rf mixer 210. 
In operation, the input stage 202 receives and amplifies an rf input signal 
that is frequency modulated; the phase locking oscillator 128 generates a 
phase locked signal, that is, a signal that is phase locked to a crystal 
controlled reference frequency; the amplified rf signal is mixed with the 
phase locked signal in the rf mixer 210, and demodulated in the I.F. stage 
203 to produce a demodulated output signal in an output conductor 218; and 
the modulator 130 uses the demodulated output signal to D.C. modulate the 
phase locked signal, thereby modulating the output signal of the conductor 
218. 
The rf input signal may be in the 2200 to 2400 MHz range, the D.C. 
modulated phase locked oscillator 100 may have an output frequency in the 
range of 1700-1900 MHz, and the local oscillator 216 may have a frequency 
of 500 Mhz. However, these frequencies are given merely as an example. In 
actual practice, the input frequencies may be in any range of rf 
frequencies, or even in frequencies that are below the rf range, and that 
are connected to the receiver 200 by other means, such as electrical 
connection or light waves. 
For purposes of understanding the claims, it should be recognized that the 
signal processing apparatus 200 of FIG. 10 includes the electrical device 
100 of FIG. 6. 
More particularly, it should be recognized that the circuitry of the radio 
frequency receiver 200 includes the phase locking oscillator 128 and the 
D.C. modulator 130, both of FIG. 6. 
Referring again to FIG. 4, for purposes of understanding the claims, the 
following should be observed: The output 27 of the phase detector 26 
controls the integrator 20, the integrator 20 controls the VCO 22, and the 
VCO 22 produces the output frequency in the output conductor 30. Because 
of this forward progression of control, as opposed to feedback of the 
output signal from the output conductor 30 to the input 29 of the phase 
detector 26, as used in the appended claims, the forward path 14 of the 
phase locked loop 12 includes: the phase detector 26, the integrator 20, 
the forward path conductor 18, the VCO 22, and the output conductor 30. 
In like manner, since the output signal feeds back from the output 
conductor 30 to the input 29 of the phase detector 26 as a feedback 
signal, as used in the appended claims, the feedback path 16 includes the 
feedback conductor 28 and the dual modulus divider 34. 
Since the phase detector 26 provides an output which is a function of the 
difference between the phase angles of the feedback signal to the input 29 
and the reference frequency in the input 25, the phase detector 26 is a 
part of the forward path 14. 
It follows that the electrical components of the other embodiments of the 
present invention can be understood to be a part of the forward path 14, 
to be a part of the feedback path 16, or to be a part of neither one, in 
accordance with the flow of signal from the phase detector 26 toward the 
output conductor 30, or the flow of signal from the output conductor 30 
back to the phase detector 26. 
For instance, it is evident that the prescaling divider 36 of FIG. 5 is in 
the feedback path 16. In like manner, referring to FIG. 6, the output 
conductor 30, the prescaling divider 36, the dual modulus divider 34, and 
the A and N counters of the variable modulus divider 48 of the integrated 
chip 42 are a part of the feedback path 16. However, it is obvious that 
the reference oscillator 44 of the integrated chip 42 is not a part of the 
forward path 14, nor a part of the feedback path 16; because it is outside 
the loop 12. 
Further, it should be recognized that each of the electrical devices 60, 
80, 140, 160, and 190 of FIGS. 4, 5, 7, 8, and 9 includes a phase locking 
oscillator 70, 90, 154, 180, or 192, respectively, for producing a phase 
locked output; and each of the electrical devices 60, 80, 140, 160, and 
190 of FIGS. 4, 5, 7, 8, and 9 includes a modulator 72, 92, 156, 182, or 
194, respectively, for D.C. modulating the output of the phase locking 
oscillator 70, 90, 154, 180, or 192, respectively. 
Therefore, any of the oscillators and modulators of FIGS. 4, 5, 7, 8, or 9, 
or any other components that provide the same functions, can be 
substituted for the phase locking oscillator 128 and the modulator 130 
which are shown in FIG. 10. 
Referring now to FIG. 13, an electrical device, or D.C. modulated phase 
locked oscillator, 220 includes a phase locking oscillator 222 and a D.C. 
modulator 224. The phase locking oscillator 222 includes components 
generally as named, numbered, and described in conjunction with the 
embodiment of FIG. 8. 
The D.C. modulator 224 includes the variable modulus divider 48 of the 
integrated chip 162, the modulation oscillator 64, a quadrature signal 
generator 226 that includes the flip-flop 164 of FIG. 8 and a flip-flop 
228, filters 230 and 232, and a quadrature phase shift keying mixer (QPSK) 
234 which preferably is part number PMQPW-250, manufactured by 
Mini-Circuits of Brooklyn N.Y., and which is shown in schematic form in 
FIG. 16. 
For the purposes of describing the operation of the flip-flops 164 and 228, 
initial conditions are assumed as follows: a low at three terminals, 
namely a Q terminal, or output terminal, 236 of the flip-flop 228, the D 
input terminal 170 of the flip-flop 164, and the Q output terminal 172; 
and a high at the NOT-Q output terminal 174 of the flip-flop 164, and a D 
terminal, or input terminal, 238 of the flip-flop 228 which is connected 
to the NOT-Q terminal 174 by a conductor 240. 
The operation of the flip-flops 164 and 228 can best be understood by 
considering the states of the various ones of the terminals, 170, 172, 
174, 236, and 238 of the flip-flops 164 and 228 prior to, and immediately 
following the rising edge of, each cycle from the modulation oscillator 
64. 
Assuming the initial states of the terminals 170, 172, 174, 236, and 238 as 
noted above, where "0" is a low and "1" is a high, then the leading edge 
of a particular cycle from the modulation oscillator 64, applied to clock 
terminals 176 and 242, results in the original states being changed, or 
remaining the same, as follows: 
TABLE 1 
______________________________________ 
Prior to and Subsequent to 1st Cycle 
______________________________________ 
Flip-flop 228 
D terminal 238 . . . "1" .fwdarw. "1" 
Q terminal 236 . . . "0" .fwdarw. "1" 
Flip-flop 164 
D terminal 170 . . . "0" .fwdarw. "1" 
Q terminal 172 . . . "0" .fwdarw. "0" 
NOT-Q terminal 174 . "1" .fwdarw. "1" 
______________________________________ 
TABLE 2 
______________________________________ 
Prior to and Subsequent to 2nd Cycle 
______________________________________ 
Flip-flop 228 
D terminal 238 . . . "1" .fwdarw. "0" 
Q terminal 236 . . . "0" .fwdarw. "1" 
Flip-flop 164 
D terminal 170 . . . "1" .fwdarw. "1" 
Q terminal 172 . . . "0" .fwdarw. "1" 
NOT-Q terminal 174 . "1" .fwdarw. "0" 
______________________________________ 
TABLE 3 
______________________________________ 
Prior to and Subsequent to 3rd Cycle 
______________________________________ 
Flip-flop 228 
D terminal 238 . . . "0" .fwdarw. "0" 
Q terminal 236 . . . "1" .fwdarw. "0" 
Flip-flop 164 
D terminal 170 . . . "1" .fwdarw. "0" 
Q terminal 172 . . . "1" .fwdarw. "1" 
NOT-Q terminal 174 . "0 " .fwdarw. "0" 
______________________________________ 
TABLE 4 
______________________________________ 
Prior to and Subsequent to 4th Cycle 
______________________________________ 
Flip-flop 228 
D terminal 238 . . . "0" .fwdarw. "1" 
Q terminal 236 . . . "0" .fwdarw. "0" 
Flip-flop 164 
D terminal 170 . . . "0" .fwdarw. "0" 
Q terminal 172 . . . "1" .fwdarw. "0" 
NOT-Q terminal 174 . "0" .fwdarw. "1" 
______________________________________ 
From a study of the tables shown above, taken together with the schematic 
drawing of FIG. 13, it can be seen that one pulse is supplied to the 
filter 230, and to a first quadrature input terminal 244 of the QPSK mixer 
234, when the leading edge of the first cycle is received from the 
modulation oscillator 64. 
Also, from the tables shown above, it can be seen that a second pulse is 
supplied to the filter 232 and to a second quadrature input terminal 246 
of the QPSK mixer 234 when the leading edge of the second cycle is 
received from the modulation oscillator 64. 
Further, it can be seen from the tables shown above that these pulses are 
supplied to the filters 230 and 232, and to the QPSK mixer 234, only once 
for each four cycles of the modulation oscillator 64, and that these two 
pulses are one cycle apart, the first occurring at the first cycle of the 
modulation oscillator 64, and the second occurring at the second cycle of 
the modulation oscillator 64. 
Thus, the flip-flops, 228 and 164, cooperate to divide the frequency of the 
modulation oscillator 64 by four. Further, since the two pulses from the 
flip-flops, 228 and 164, are separated by one cycle of the modulation 
oscillator 64, they are phase shifted by 90 degrees, and the flip-flops, 
228 and 164, serve as the quadrature signal generator 226. 
Referring now to FIGS. 14a-14c, and to the preceding description that 
follows Tables 1-4: FIG. 14a is a graph of a modulation frequency 248 of 
the modulation oscillator 64 that has a period 250; FIG. 14b is a graph of 
a first square wave 252 that is developed at the Q terminal 236 of the 
flip-flop 228 in response to the modulation frequency, that has a period 
254, and that is delivered to the filter 230 and to the input terminal 244 
of the QPSK mixer 234; and FIG. 14c is a graph of a second square wave 256 
that is developed at the Q terminal 172 of the flip-flop 164 in response 
to the modulation frequency, that has a period of 258, that is phase 
shifted from the first square wave 252, and that is delivered to the 
filter 232 and to the input terminal 246 of the QPSK mixer 234. 
Thus, as seen in FIGS. 14a-14c, the flip-flops, 228 and 164, of the 
quadrature signal generator 226 provide square waves, 252 and 256, whose 
periods, 254 and 258, extend for four of the periods 250 of the modulation 
frequency 248; and the square wave 256 is shifted in time by one of the 
periods 250. Further, the frequencies of the square waves, 252 and 256, 
are one-fourth of the frequency of the modulation frequency 248, and the 
square waves, 252 and 256 are phase shifted 90 degrees from one another to 
provide quadrature frequencies. 
Therefore, with the QPSK mixer 234 interposed into the feedback conductor 
28, with a feedback input terminal 260 and a feedback output terminal 262 
connected to the feedback conductor 28, when mixed with frequencies in the 
feedback path 16, the lower sideband frequency is lower than the feedback 
frequency by one-fourth of the frequency of the modulation oscillator 64; 
and, to maintain phase locking, the voltage controlled oscillator 22 
increases its frequency by one-fourth of the frequency of the modulation 
oscillator 64. 
Referring now to FIG. 15, an electrical device, or D.C. modulated phase 
locked oscillator, 264 includes a phase locking oscillator 266 and a D.C. 
modulator 268. The phase locking oscillator 266 includes components 
generally as named, numbered, and described in conjunction with the 
embodiment of FIG. 6. 
The D.C. modulator 268 includes the dual modulus divider 34, the variable 
modulus divider 48, the modulus controller 50, and the modulation 
oscillator 64, all as described in conjunction with the embodiment of FIG. 
6. In addition, the D.C. modulator 268 includes a synchronizer 270 and a 
parallel adder 272, the parallel adder 272 being shown in schematic form 
in FIG. 17. The synchronizer 270 includes both the flip-flop 102 of FIG. 6 
and a flip-flop 274. 
In operation, a D terminal, or an input terminal, 276 of the flip-flop 102 
is held high by an applied voltage, as shown, so that, when the modulation 
oscillator 64 delivers a pulse to the clock terminal 108 of the flip-flop 
102, the Q terminal 110 of the flip-flop 102 is high and delivers a high 
to a D terminal, or input terminal, 278 of the flip-flop 274, thereby 
holding the pulse from the modulation oscillator 64 until the completion 
of a dividing cycle by the dual modulus divider 34. 
Upon completion of a dividing cycle, the modulus controller 50 clocks the 
flip-flop 274 by delivering the clocking pulse to a clock terminal 280 of 
the flip-flop 274 via the modulus control conductor 38, thereby producing 
a high at a Q terminal, or output terminal, 282. 
The high at the Q terminal 282 is transmitted to a control terminal 284 of 
the parallel adder 272 via a conductor 286; and the high at the Q terminal 
282 is also transmitted to the reset terminal 114 of the flip-flop 102 via 
the conductor 286. 
With the "A" count of the modulus controller 50 increased by the parallel 
adder 272, an additional division is performed on the frequency in the 
feedback path 16, thereby causing the phase detector 26 and the integrator 
20 to increase the frequency of the voltage controlled oscillator 22. 
Referring now to FIGS. 10, 13, and 15, either of the electrical devices, 
220 and 264, of FIGS. 13 and 15, can be utilized in the signal processing 
apparatus 200 of FIG. 10 in the same manner as the electrical device 100 
of FIG. 6 which is shown in the signal processing apparatus 200 of FIG. 
10. 
That is, the signal processing apparatus 200 of FIG. 10 can use the phase 
locking oscillator 222 and the D.C. modulator 224 of FIG. 13, or the phase 
locking oscillator 266 and the D.C. modulator 268 of FIG. 15, in place of 
the phase locking oscillator 128 and the D.C. modulator 130 of FIG. 6. 
While the present invention has been described with particular components, 
it should be understood that the scope of the present invention is to be 
determined by the terminology used in the claims, and by the functions 
recited therein, without regard to more specifically described components 
in the detailed description. 
Further, while examples have been given for frequencies, it should be 
understood that the present invention will function as described, and is 
useful in the gigahertz range, in the megahertz range, in the kilohertz 
range, and below the kilohertz range. For this reason, frequency limiting 
terms, such as radio frequency, are not needed, nor included, in the 
claims. 
While specific apparatus and method have been disclosed in the preceding 
description, and while part numbers have been inserted parenthetically 
into the claims to facilitate understanding of the claims, it should be 
understood that these specifics have been given for the purpose of 
disclosing the principles of the present invention and that many 
variations thereof will become apparent to those who are versed in the 
art. Therefore, the scope of the present invention is to be determined by 
the appended claims, and without any limitation by the part numbers 
inserted parenthetically in the claims. 
INDUSTRIAL APPLICABILITY 
The present invention is applicable to phase locked oscillators, voltage 
controlled crystal oscillators, single frequency transmitters and 
receivers, channelized transmitters and receivers, telemetry and video 
transmitters such as are used for commercial, consumer, and military 
products, and to all such electrical devices in which low frequency drift, 
inclusion of a maximum number of channels within a limited frequency 
range, large frequency deviations, and/or rapid synchronization to 
modulation frequencies are/is required, whether the output frequencies be 
in the gigahertz range, in the megahertz range, in the kilohertz range, or 
even lower than the kilohertz range.