Methods of forming integrated circuit capacitors having U-shaped electrodes

Methods of forming integrated circuit capacitors include the steps of forming a first electrically insulating layer having a conductive plug therein, on a semiconductor substrate, and then forming second and third electrically insulating layers of different materials on the first electrically insulating layer. A contact hole is then formed to extend through the second and third electrically insulating layers and expose the conductive plug. Next, a conductive layer is formed in the contact hole and on the third electrically insulating layer. A step is then performed to planarize the conductive layer to define a U-shaped electrode in the contact hole. The third electrically insulating layer is then etched-back to expose upper portions of outer sidewalls of the U-shaped electrode, using the second electrically insulating layer as an etch stop layer. However, the second electrically insulating layer is not removed but is left to act as a supporting layer for the U-shaped electrode. This second electrically insulating layer preferably comprises a composite of a nitride layer and an oxide layer. To increase the effective surface area of the U-shaped electrode, an HSG layer may also be formed on the inner and outer sidewalls of the U-shaped electrode.

RELATED APPLICATION
 This application is related to Korean Appn. No. 98-12563, filed Apr. 9,
 1998, the disclosure of which is hereby incorporated herein by reference.
 1. Field of the Invention
 The present invention relates to methods of forming integrated circuit
 devices and, more particularly, to methods of forming integrated circuit
 capacitors.
 2. Background of the Invention
 As DRAMs increase in memory cell density, there is a continuous challenge
 to maintain sufficiently high storage capacitance within memory cells
 despite decreasing cell area. Additionally there is a continuing goal to
 further decrease cell area. Many methods have been proposed to keep the
 capacitance of such storage capacitors at acceptable levels. One approach
 is to increase the height of the storage node (electrode of the
 capacitor). Another approach is to use high dielectric materials such as
 Ta.sub.2 O.sub.5, or BST.
 However, there are some problems with the approach to increasing the height
 of the storage node. For example, if the required height of the storage
 node is more than 10,000 .ANG., it becomes very difficult to pattern
 conductive layers as storage nodes. There are also some problems with
 using high dielectric materials, such as Ta.sub.2 O.sub.5 and BST, as
 dielectric films. These problems include the complexity of the fabrication
 process and reduced reliability.
 Attempts have been made to address these problems. For example, FIG. 1A
 shows, in cross-section, a "one cylinder stack" (OCS) structure of a
 capacitor storage node according to the prior art. As can be seen in FIG.
 1A, the cup-shaped storage node has a capacitance of about two times
 larger than that of a simple stack capacitor structure because both outer
 and inner surfaces of the node can be utilized as an effective capacitor
 area. FIG. 1B shows, in cross-section, a simple stacked capacitor with an
 HSG layer on its surface according to the prior art. The simple stacked
 capacitor with an HSG layer has a capacitance about two times larger than
 that of a simple stacked capacitor without an HSG layer. One cylinder
 stack capacitors with HSG layers on both inner and outer surface also can
 be formed.
 FIGS. 2A-2D are cross-sectional diagrams which illustrate a method of
 fabricating an OCS capacitor with an HSG layer thereon. Referring now to
 FIG. 2A, a device isolating layer 12 is formed on a predetermined region
 of a semiconductor substrate 10 to define active and inactive regions. A
 gate electrode structure 14 is formed over the semiconductor substrate 10.
 A gate oxide layer also is disposed between the gate electrode structure
 14 and the substrate 10. Source/drain regions 16 are formed in the active
 region adjacent to the gate electrode layer. An interlayer insulating
 layer 18 is formed over the semiconductor substrate 10 and the gate
 electrode structure 14. A contact hole 19 is opened in the interlayer
 insulating layer 18 to expose one of the source/drain regions 16. A
 polysilicon layer 20 is used as a storage node. This layer is deposited in
 the contact hole 19 and over the insulating layer 18. A photoresist layer
 pattern 22 is formed over the polysilicon layer 20 to define a storage
 node region. A low temperature oxide layer 24 is deposited over the
 polysilicon layer 20 (including the photoresist pattern 22) to a thickness
 of about 2,500 .ANG..
 Referring to FIG. 2B, the low temperature oxide layer 24 is then dry etched
 to form sidewall spacers 24a on the lateral edges of the photoresist
 pattern 22. Using the photoresist pattern 22 and the sidewall spacers 24a
 as a mask, a timed etching step is performed on the insulating layer 20 to
 remove more than half of the original thickness thereof.
 The formation of the storage node structure is next addressed and
 illustrated in FIGS. 2C-2D. After removing the photoresist pattern 22, the
 polysilicon layer 20 is etched back, using the sidewall spacers 24a as a
 mask, to form the storage node structure 20a, as shown in FIG. 2D.
 Subsequently, an HSG layer (not shown) is formed on the surfaces of the
 storage node 20a. A dielectric film and top plate are then formed on the
 storage node 20a using conventional techniques.
 The above-described method has some drawbacks. For example, the timed etch
 conducted on the insulating layer may not provide process reliability, and
 the polymer resulting from the etch back may contaminate the storage node
 which affects the dielectric characteristics. The etch back using the
 sidewall spacers as a mask also may cause a variation in storage node
 thickness. Moreover, since the thickness of the top portion of the storage
 node is less than 1,000 .ANG., the storage node may fall down during a
 cleaning process and the HSG formation thereon may totally consume the
 storage node and cause it to break off.
 SUMMARY OF THE INVENTION
 It is therefore an object of the present invention to provide improved
 methods of forming integrated circuit capacitors and capacitors formed
 thereby.
 It is another object of the present invention to provide methods of forming
 integrated circuit capacitors having high capacitance and capacitors
 formed thereby.
 These and other objects, features and advantages of the present invention
 are provided by methods of forming integrated circuit capacitors that
 include the steps of forming a first electrically insulating layer having
 a conductive plug therein, on a semiconductor substrate, and then forming
 second and third electrically insulating layers of different materials on
 the first electrically insulating layer. A contact hole is then formed to
 extend through the second and third electrically insulating layers and
 expose the conductive plug. Next, a conductive layer is formed in the
 contact hole and on the third electrically insulating layer. A step is
 then performed to planarize the conductive layer to define a U-shaped
 electrode in the contact hole. The third electrically insulating layer is
 then etched-back to expose upper portions of outer sidewalls of the
 U-shaped electrode, using the second electrically insulating layer as an
 etch stop layer. However, the second electrically insulating layer is not
 removed but is left to act as a supporting layer for the U-shaped
 electrode. This second electrically insulating layer preferably comprises
 a composite of a nitride layer and an oxide layer. To increase the
 effective surface area of the U-shaped electrode, an HSG layer may also be
 formed on the inner and outer sidewalls of the U-shaped electrode.
 According to another aspect of the present invention, the planarization
 step may be preceded by the step of forming a fourth electrically
 insulating layer on the conductive layer. In this case, the planarization
 step will include the step of planarizing the fourth electrically
 insulating layer and the conductive layer to define a U-shaped electrode
 in the contact hole. To complete the capacitor, steps may also be
 performed to form a capacitor dielectric layer on the U-shaped electrode
 and on the second electrically insulating layer and then form an upper
 capacitor electrode on the capacitor dielectric layer.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
 The present invention now will be described more fully hereinafter with
 reference to the accompanying drawings, in which preferred embodiments of
 the invention are shown. This invention may, however, be embodied in many
 different forms and should not be construed as limited to the embodiments
 set forth herein; rather, these embodiments are provided so that this
 disclosure will be thorough and complete, and will fully convey the scope
 of the invention to those skilled in the art. In the drawings, the
 thickness of layers and regions are exaggerated for clarity. Like numbers
 refer to like elements throughout. It will be understood that when an
 element such as a layer, region or substrate is referred to as being "on"
 another element, it can be directly on the other element or intervening
 elements may also be present. In contrast, when an element is referred to
 as being "directly on" another element, there are no intervening elements
 present.
 Referring now to FIG. 3A, a cross-sectional view of a semiconductor
 substrate 100 with a gate electrode structure 104 on its surface is
 provided. A device isolation layer 102 (e.g., a field oxide layer) is
 formed on a predetermined area of the semiconductor substrate 100 to
 define active and inactive regions therein. The gate electrode structure
 104 is formed on the active region and a gate oxide layer extends
 therebetween. Source/drain regions 106 are formed adjacent to the gate
 electrode structure 104 by implanting impurities into the substrate 100.
 A first insulating layer 108 (e.g., an oxide layer) is formed over the
 semiconductor substrate 100 and over the gate electrode structure 104. The
 first insulating layer 108 is then etched to form a contact hole 110
 therein. This contact hole 110 exposes one of the source/drain regions
 106. A first conductive material (e.g., a polysilicon layer 112) is
 deposited in the contact hole 110 and over the first insulating layer 108
 using a chemical vapor deposition (CVD) method. In order to provide a good
 ohmic contact to the source/drain regions 106, the conductive material may
 be heavily doped. The doping method may include depositing an in-situ
 doped polysilicon layer, such as by LPCVD and adding phosphine(PH.sub.3)
 to the CVD reactant gas (e.g., SiH.sub.4). Alternatively, the polysilicon
 layer 112 can be deposited undoped and then impurities can be implanted.
 Referring to FIG. 3B, a planarization process is performed on the
 polysilicon layer 112 to form a contact plug 112a in the contact hole 110.
 The planarization process may be a CMP or plasma etch-back process. The
 plasma etch-back may use a CF-based etch gas using CF.sub.4, C.sub.2
 F.sub.6, C.sub.3 F.sub.8, CH.sub.2 F.sub.2, CHF.sub.3, or SF.sub.6, or
 combinations thereof.
 Referring now to FIG. 3C, a second insulating layer 114, comprising a
 silicon nitride layer 114a and an HTO layer 114b, is deposited over the
 first insulating layer 108 and contact plug 112a. A third insulating layer
 116, comprising a first PECVD oxide layer 116, is then deposited over the
 HTO layer 114b. The silicon nitride layer 114a is deposited to a thickness
 of about 70 .ANG. and serves as an etch stop layer during the subsequent
 step of etching the first PECVD oxide 116. The HTO layer 114b is deposited
 to a thickness of about 500 .ANG. to 1,500 .ANG.. This HTO layer 114b is
 provided to serve as an etch stop layer during the step of removing the
 first PECVD layer 116. As described hereinbelow, the HTO layer 114b can
 also be used to support a storage electrode of a capacitor. The first
 PECVD oxide layer 116 may have a thickness of about 5,000 .ANG..
 Referring to FIG. 3D, a photoresist layer pattern (not shown) is deposited
 over the first PECVD oxide layer 116. The first PECVD oxide layer 116, the
 HTO layer 114b, and the nitride layer 114a are then selectively etched to
 form an opening 118. The opening 118 exposes the contact plug 112a and
 surrounding portions of the first insulating layer 108. Here, the nitride
 layer 114a serves as an etch stop layer during this etching step.
 Referring now to FIG. 3E, a second conductive layer 120 (used as storage
 node) is deposited in the opening 118 and over the first PECVD oxide layer
 116. The second conductive layer 120 is preferably made of polysilicon and
 is deposited to a thickness less than half of the opening width and
 preferably to a thickness of about 200 .ANG. to 2000 .ANG..
 Referring to FIG. 3F, a fourth insulating layer 122 (such as a photoresist
 layer or an SOG layer) is deposited in the remaining space in the opening
 118 and over the polysilicon layer 120 to a thickness of about 100 .ANG.
 to 10,000 .ANG.. This fourth insulating layer 122 serves a dual purpose of
 preventing particle impaction (such as polymer) within the opening during
 the step of removing the polysilicon layer outside of the opening 118 and
 protecting the polysilicon layer 120 within the opening.
 Referring to FIG. 3G, the fourth insulating layer 122 and the polysilicon
 layer 120 are then etched back (at an etch ratio of about 1:1) until a top
 surface of the first PECVD oxide layer 116 is exposed. This etch-back step
 results in the formation of a cup-shaped storage node 120a.
 The fourth insulating layer 122a remaining in the opening 118 and the first
 PECVD oxide layer 116 outside of the opening then are removed, as shown in
 FIG. 3H. If the fourth insulating layer 122a is a photoresist layer, the
 first PECVD oxide layer 116 is removed following the removal of the
 photoresist layer 112a from the opening. In this case, the photoresist
 layer is removed by ashing and the first PECVD oxide layer 116 is removed
 by wet etching in a BOE solution. On the other hand, if the fourth
 insulating layer 122a is an SOG layer, the SOG layer remaining in the
 cup-shaped storage-node 120a and the first PECVD oxide layer 116 are
 removed at the same time by wet etching in a BOE solution or dry etching.
 During these etching steps, the HTO layer 114b serves as an etch stop
 layer since the first PECVD oxide layer 116 has a high etch selectivity
 (the etch ratio of the first PECVD oxide layer and HTO layer is about
 4:1). The remaining HTO layer 114b and the remaining nitride layer 114a
 also serve the purpose of supporting the cup-shaped storage node 120a
 during back-end processing.
 To increase the surface area of the capacitor, a rough conductive layer
 such as an HSG layer 124 then is formed on the surface of the capacitor by
 wellknown conventional methods as shown in FIG. 3I. Next, conventional
 processes for forming a dielectric film and an upper capacitor electrode
 are carried out to form a complete capacitor structure.
 In the drawings and specification, there have been disclosed typical
 preferred embodiments of the invention and, although specific terms are
 employed, they are used in a generic and descriptive sense only and not
 for purposes of limitation, the scope of the invention being set forth in
 the following claims.