Grating couplers integrated with one or more airgaps

The present disclosure relates to semiconductor structures and, more particularly, to grating couplers integrated with one or more airgap and methods of manufacture. The structure includes: a substrate material comprising one or more airgaps; and a grating coupler disposed over the substrate material and the one or more airgaps.

FIELD OF THE INVENTION

The present disclosure relates to semiconductor structures and, more particularly, to grating couplers integrated with one or more airgaps and methods of manufacture.

BACKGROUND

An optical coupler is a component that couples light from an optical fiber to a waveguide structure. For example, an optical coupler can be a grating coupler used in silicon photonics to provide efficient coupling to silicon waveguides. But, the coupling efficiency of grating couplers are limited due to the light leakage into the underlying substrate.

To improve coupling efficiency, a reflector can be provided under the grating coupler to reflect light back into the waveguide structure so that the reflected light can be absorbed by the waveguide structure. For example, metallic mirrors made of noble metals, e.g., Au, or a distributed Bragg reflector (DBR) composed of vertically stacked multilayers of metal-oxides or polymer material, can be used to enhance grating coupler efficiency. However, such configurations are either incompatible with CMOS processes or require complicated fabrication steps. Hence, they cannot be easily and cost efficiently implemented on Si photonics platforms.

SUMMARY

In an aspect of the disclosure, a structure comprises: a substrate material comprising one or more airgaps; and a grating coupler disposed over the substrate material and the one or more airgaps.

In an aspect of the disclosure, a structure comprises: a bulk substrate material comprising one or more sealed airgaps within the bulk substrate material; a waveguide structure over the bulk substrate material; and a grating coupler optically coupled to the waveguide structure and disposed over the one or more airgaps.

In an aspect of the disclosure, a method comprises: forming one or more sealed airgaps in a bulk substrate material; and forming a grating coupler over the bulk substrate material and the one or more airgaps.

DETAILED DESCRIPTION

The present disclosure relates to semiconductor structures and, more particularly, to grating couplers integrated with one or more airgaps and methods of manufacture. More specifically, the present disclosure includes grating couplers with an embedded airgap or array of airgaps formed in a bulk substrate or semiconductor on insulator (SOI) technologies. Advantageously, the present disclosure provides enhancement to the coupling efficiency of grating couplers.

In embodiments, the grating couplers can be fabricated using bulk Si wafers or SOI technologies. The grating couplers can be patterned polysilicon material or SiN material with integrated airgap(s) in the substrate under the grating couplers. The integrated airgap(s) can be a single, merged airgap or an array of airgaps. With the help of the airgap or array of airgaps, the peak wavelength can be shifted to a shorter wavelength, which helps relax fabrication constraints. In this way, there is no need to pattern small features that are below ground rules such as reflectors, etc. The airgaps can also be tuned to different shapes depending on the performance requirements of the grating couplers.

FIGS. 1A-1Eshow cross-sectional views of trenches and cavity structures formed in a substrate, amongst other features, and respective fabrication processes in accordance with aspects of the present disclosure. More specifically,FIG. 1Ashows an incoming structure10comprising a bulk substrate12composed of any suitable semiconductor materials such as, e.g., Si. One or more pad films14, e.g., dielectric materials, is deposited on the substrate12. For example, the pad films14can be oxide or nitride films or combinations of these or other dielectric materials. In embodiments, the pad film(s)14can be deposited by a conventional deposition process, e.g., chemical vapor deposition (CVD). By way of example, nitride can be deposited to a thickness of about 100 nm to 200 nm; whereas, oxide can be deposited to a thickness of about to 10 nm. In the case of Si substrates, the oxide can be formed from Si in furnace oxidizations of the Si material.

Still referring toFIG. 1A, openings or trenches16are patterned on the pad film(s)14, followed by trench formation into the substrate12. The trenches16can include “holes” and/or “bars”. In embodiments, the trenches16can be formed by conventional lithography and etching processes. For example, a resist formed over the pad dielectric film(s)14is exposed to energy (light) to form a pattern (opening). An etching process with a selective chemistry, e.g., reactive ion etching (RIE), will be used to form one or more trenches16through the openings of the resist, through the pad film(s)14, and into the substrate12. The resist can then be removed by a conventional oxygen ashing process or other known stripants. The width of the trenches14can be determined by the lithography resolution. In one illustrative non-limiting example, the trenches14can be 120 nm wide and 0.7 micron deep into the substrate12.

Referring toFIG. 1B, a sidewall liner (also referred to as a spacer)18can be formed on the sidewalls of the trenches16by depositing a dielectric material and anisotropic etching the dielectric material from the bottom of the trenches16and top planar features of the structure. In embodiments, the sidewall liner18can be an oxide or nitride, combinations thereof or other dielectric materials, as examples. The sidewall liner18can be formed using any known deposition method, e.g., CVD, thermal oxidization of the silicon substrate, atomic layer deposition (ALD) or any of these combinations.

The sidewall liner18should robustly coat the sidewalls of the trenches16in order to protect the underlying substrate material12from subsequent removal (e.g., etching) processes (for cavity formation). To achieve this robust sidewall coverage, the dielectric material should be thick enough to leave a thick film on the sidewalls of the trenches16, but not too thick that it pinches off the top opening of the trenches16which would prevent cavity formation. For example, 40 nm of nitride can be deposited on a 100 nm wide trench. In other embodiments, the sidewall of the trenches16can be thermally oxidized to form a SiO2layer which extends under the pad film(s)14. Following this thermal oxidization or other deposition process, the sidewall liner18can undergo an anisotropic etch. In embodiments, the top surface of the pad film14is exposed to the spacer etch and is thinned but not fully removed.

In an example, the anisotropic etch comprises a RIE using a perfluorocarbon-based chemistry which removes material from planar surfaces but leaves dielectric material on the sidewall of the trenches16as is known in the art. An optional vapor or liquid HF treatment, hydrogen plasma, anneal, basic or acidic chemical clean, or any process known to remove thin or native dielectrics or residual spacer etch polymer from the substrate12(e.g., silicon) can be used to remove any excessive dielectric material at a bottom of the trenches16. The post sidewall liner etch cleans (e.g., anisotropic etch) should leave a robust dielectric liner18on the top corner and sidewall of the trenches16to prevent etching of the substrate12through the sidewall of the trenches16during cavity formation. If a thermal oxide formed in a furnace for the sidewall liner18is used, then the substrate12under the pad film(s)14can be oxidized, which may provide a better protective barrier to prevent unintentional substrate etching during the cavity formation.

As shown inFIG. 1C, an array of cavity structures20can be selectively formed in the substrate12by a substrate removal, e.g., etching, process through the bottom of the trenches16. Alternatively, as shown inFIG. 1D, the array of cavity structures can be over-etched to form a single, merged cavity structure20a. In either scenario, the pad film(s)14on the surface of the substrate12and the sidewall liner18on the sidewall of the trenches16will protect the substrate12from being unintentionally etched during the cavity formation.

To form the cavity structures20,20a, the exposed substrate material12within the trenches16can be removed by a wet etching process or dry etching process. For example, dry etchants include plasma-based CF4, plasma-based SF6, or gas XeF4silicon etch, etc., and wet etching processes include KOH and NH4OH. In embodiments, the upper surface of cavity structure20can be about 0.4 μm to 0.7 μm in depth below the top surface of the substrate12; although the depth can be modulated to increase optimization for different wavelengths. In addition, the cavity structures20can have a diameter of about 200 nm to 1.0 μm as an example; although other dimensions are contemplated herein.

InFIG. 1E, the sidewall liner and pad films are removed, exposing the upper surface of the substrate12and the sidewalls of the trenches16. The sidewall liner and pad films can be removed by a conventional etching process selective to such materials. For example, the sidewall liner and pad films can be removed by using only or a combination of hot phosphorous followed by a HF chemistry or vice-versa depending on the single dielectric layer or stack of different dielectric layers used for the sidewall liner. Following the removal of the sidewall liner and pad films, the trenches22can be subjected to an optional annealing process to soften or round (curve) the edges of the trenches as is known in the art such that no further explanation is required for a complete understanding of the present disclosure, e.g., a temperature range of about 800° C. to about 1100° C., for up to about 60 seconds in an H2atmosphere

FIGS. 2A and 2Bshow formation of an array of airgap(s) integrated into the substrate12, amongst other features. InFIG. 2A, a material22can be formed, e.g., deposited, on the surface of the substrate12including, e.g., the optional surface of the curvature, sidewalls of the trenches16and sidewalls of the cavity structures20. In embodiments, the material22can be epitaxial SiGe deposited using ultra high vacuum CVD (UHVCVD); although other semiconductor materials, polysilicon or epitaxial films, and deposition processes are contemplated herein.

By way of example, SiGe material can be deposited at a temperature of about 600° C. to 750° C., resulting in a thickness of about 5 nm to about 50 nm. It should be understood that other thicknesses of the material22can be applied, depending on the critical dimension of the trenches16. For example, in general, as the width of the trenches16increases, the thickness of material22increases in order to ensure that the top of the trench16is filled or sealed during the subsequent reflow anneal.

As shown inFIG. 2B, the substrate, e.g., material22, can be heated to equal to or greater than the reflow temperature of the material22. This reflow temperature reflows the material22to fill in the top of trenches16. Since SiGe has a lower reflow temperature than Si, for example, the material22can be reflowed into the opening of the trenches16to plug or fill the top of the trenches16without filling in the cavity structures20. In embodiments, the reflow temperature can be about 800° C. to 1050° C. and the reflow time can be anywhere up to about 600 seconds. By providing the reflow process, the top of the trench16is fully sealed with the material22, thereby forming, e.g., airgaps20′. In embodiments, the airgaps20′ can be circular (spheres), oval, cylindrical, a single, merged airgap (FIG. 1D), etc. Moreover, the array of airgaps20′ can have a constant pitch (e.g., periodic) or non-periodic pitch (e.g. apodized).

In optional embodiments, a silicon layer can be deposited to a thickness of about 150 nm in a deposition chamber having a temperature of about 850° C. to about 1050° C. for about 60 seconds. At this temperature, the SiGe material22continues to reflow, continuing to gravitate or migrate into the upper portion of the trenches16(e.g., typically at the smallest critical dimension). The semiconductor material may also reflow during the bake, filling in the increased volume at the top of the trench and resulting in a planar or nearly planar surface. This reflow also assists in sealing the trenches16, thereby forming the airgaps20′.

FIG. 3shows a grating coupler formed over the airgap(s)20′, amongst other features. More specifically, a dielectric material24can be formed, e.g., deposited, over the sealed airgaps20′. The dielectric material24can be, e.g., an oxide material, deposited by a conventional deposition method, e.g., CVD process. A waveguide material26can be formed e.g., deposited, on the dielectric material24. In embodiments, the waveguide material26can be, e.g., SiN, deposited by a CVD process. In embodiments, the material thickness of the waveguide material26can be, e.g., 200 nm to 500 nm.

The waveguide material26can be patterned using conventional lithography and etching processes to form a waveguide structure28and a grating coupler30. The pattern of the grating coupler30comprises a plurality of openings26awhich can be aligned with the airgaps20′, offset from the airgaps20′ or combinations thereof, depending on the desired performance parameters of the waveguide structure28. The openings26acan also be of different shapes, e.g., rectangular, square, etc. In any scenario, the plurality of openings26aare positioned such that light can pass through the grating coupler30, reach to the airgaps20′, and reflect back to the waveguide structure28to optimize coupling efficiency of the waveguide structure28.

FIG. 4shows a structure10acomprising a grating coupler30with a single airgap20a′ integrated into the substrate12. The single airgap20a′ can be formed by merging the cavity structures described inFIG. 1D, followed by the remaining processes described inFIGS. 1E-2B. In this embodiment, the airgap20a′ is below the waveguide structure28and the grating coupler30. Also, through modeling, it has been shown that coupling efficiency of the structure10aincreases significantly over a process of record, e.g., a structure which does not include any airgaps features over the grating coupler of the waveguide structure.

FIG. 5shows a structure10bcomprising a polysilicon grating coupler30integrated with an array of airgaps20′ as shown inFIG. 3. In this embodiment, the waveguide structure28can be composed of Si material33and the grating coupler30includes polysilicon material34patterned over the Si material33. In the fabrication process, as an example, the Si material33and polysilicon material34can be deposited by any conventional deposition method such as, CVD, with the polysilicon material34deposited over the Si material33. The polysilicon material34can be patterned using conventional lithography and etching processes as already described herein. As in the any of the embodiments, the grating coupler30(e.g., patterned poly material) can comprise any number of different patterns, e.g., shapes or openings34a.

FIG. 6shows a structure10ccomprising a grating coupler30with a single airgap20a′ integrated into the substrate12. The single airgap20a′ can be formed by merging the cavity structures described inFIG. 1D, followed by the remaining processes described inFIGS. 1E-2B. In this embodiment, the grating coupler30includes polysilicon material34patterned over Si material33as described with respect toFIG. 5, with the waveguide structure28comprising the Si material33. However, in this embodiment, only a single airgap20a′ can be formed in the underlying substrate12, such as by merging the cavities described inFIG. 1D.

FIG. 7shows a grating coupler formed using SOI technology, amongst other features, and respective fabrication processes. More specifically, the structure10dofFIG. 7shows a grating coupler30and waveguide structure28formed from semiconductor material12cof the SOI technology12. As should be understood by those of skill in the art, the SOI technology12comprises a substrate (wafer)12a, an insulator layer12b(e.g., buried oxide layer) over the substrate12a, and a semiconductor material12cover the insulator material12b. The semiconductor material12ccan be any appropriate semiconductor material such as Si or SiN; although other semiconductor materials are contemplated herein.

Still referring toFIG. 7, the grating coupler30and waveguide structure28can be formed by a patterning process, e.g., lithography and etching (RIE) of the semiconductor material12c, as already described herein such that no further explanation is required for an understanding of the present disclosure. In alternative processes, the grating coupler30can be formed by using a polysilicon material patterned over the semiconductor material12c, as discussed with reference toFIG. 5, for example. In even further alternative embodiments, the grating coupler30and waveguide structure28can be formed by deposited and patterning a separate semiconductor material (e.g., SiN) over a dielectric material deposited on the semiconductor material12c. In any scenario, a cladding layer36is deposited on the grating coupler30and waveguide structure28. In embodiments, the cladding layer36is Undoped Silicate Glass (USG).

FIG. 8Ashows a cross-sectional view of trenches38formed on sides of the grating coupler30and extending into the semiconductor material12cof the SOI technology.FIG. 8Bis a top down view ofFIG. 8A. More specifically, trenches38can be formed on both sides of the grating coupler30and extend into the semiconductor material12c. The trenches38can be formed by conventional lithography and etching processes using selective chemistries for the different materials, e.g., cladding material38, insulator material12band substrate12a.

FIG. 9Ashows a cross-sectional view of cavity structures20formed underneath the grating coupler30, within the substrate12a.FIG. 9Bis a top down view ofFIG. 9A. More specifically, using an etching process on the exposed and substrate12a, cavity structures20are formed within the substrate12a, underneath the grating coupler30. The cavity structures20can be formed with a selective chemistry to the substrate12a, i.e., the remaining materials block etching processes from occurring at other locations. In embodiments, the substrate12acan be over-etched to merge the cavity structures20into a single cavity structure. As already described herein, the etching process can be a wet etching process or dry etching process.

FIG. 10shows an array of airgaps20′ formed under the grating coupler30, amongst other features. In embodiments, the array of airgaps20′ can be formed by depositing material44into the trenches38in order to seal the trenches38. Prior to sealing the airgaps20′, an optional cleaning process of the cavity structures can be performed as already described herein. In embodiments, the material44can be a dielectric material deposited by a conventional CVD process. As should be understood by those of skill in the art, the dielectric material will result in a pinch off phenomena.

In optional embodiments, prior to cavity formation, a sidewall liner (also referred to as a spacer) can be formed on the sidewalls of the trenches, preferably on the exposed substrate material12a, followed by an anisotropic etching process to expose a bottom surface of the trenches, as already described herein. After the airgap formation described inFIG. 10, the sidewall liner can be removed by a conventional etching process selective to such materials.

FIG. 11shows a structure10ecomprising a CMOS device42fully integrated with the grating coupler30and waveguide structure28, using SOI technology, amongst other features. In embodiments, the CMOS device42can be an active or passive device. For example, the active device can be a transistor with a nitride liner43; whereas, the passive device can be a resistor or capacitor, amongst other types of device.

The grating couplers with airgaps can be utilized in system on chip (SoC) technology. It should be understood by those of skill in the art that SoC is an integrated circuit (also known as a “chip”) that integrates all components of an electronic system on a single chip or substrate. As the components are integrated on a single substrate, SoCs consume much less power and take up much less area than multi-chip designs with equivalent functionality. Because of this, SoCs are becoming the dominant force in the mobile computing (such as in Smartphones) and edge computing markets. SoC is also commonly used in embedded systems and the Internet of Things.