Assemblies having conductive interconnects which are laterally and vertically offset relative to one another

Some embodiments include an integrated assembly having a base which includes first circuitry. Memory decks are over the base. Each of the memory decks has a sense/access line coupled with the first circuitry. The memory decks and base are vertically spaced from one another by gaps. The gaps alternate in a vertical direction between first gaps and second gaps. Overlapping conductive paths extend from the sense/access lines to the first circuitry. The conductive paths include first conductive interconnects within the first gaps and second conductive interconnects within the second gaps. The first and second conductive interconnects are laterally offset relative to one another.

TECHNICAL FIELD

Integrated assemblies (e.g., integrated memory). Integrated assemblies having multiple levels (decks, tiers), and having conductive interconnects extending between the levels.

BACKGROUND

In some applications, it can be desired to couple circuitry from one level to another.FIGS. 1-4illustrate an example prior art process for electrically coupling circuitry across levels.

FIG. 1shows an assembly1000having a conductive structure1002at a first elevational level, and having a conductive interconnect1004extending upwardly from the structure1002. In some applications, the structure1002may be coupled with logic circuitry (e.g., complementary metal-oxide-semiconductor (CMOS)).

In the shown embodiment, an insulative liner1006is along an outer edge of the conductive interconnect, and an insulative material1008is along the liner1006and over the structure1002. The insulative material1008and the liner1006may comprise the same composition as one another, or may comprise different compositions relative to one another.

A planarized surface1009extends along the insulative material1008and the liner1006. The conductive interconnect1004projects upwardly to above the planarized surface1009. In some applications, it is desired for the planarized surface1009to extend across the conductive material of the interconnect1004, as well as across the insulative material1008and the liner1006. However, processing limitations may result in the upper surface of the conductive interconnect1004projecting above the planarized surface1009. In the illustrated application, the interconnect1004has a projection (step)1007which extends above the planarized surface1009.

Referring toFIG. 2, conductive material1010is provided over the upper surface1009and the interconnect1004, and is patterned into conductive structures1012. The conductive structures1012may be lines extending into and out of the page relative to the cross-sectional view ofFIG. 2. In some applications, the conductive structures1012may be sense/access lines (wordlines or bitlines).

The upward projection of the interconnect1004may problematically influence the patterning of the conductive structures1012. For instance,FIG. 3shows a problem which may result during such patterning, and shows the central structure1012having a different shape (a contorted shape) relative to the structures formed on the planarized surface1009.

The contorted shape of the central structure1012may complicate further processing. For instance,FIG. 4shows a conductive structure1014formed over the conductive structure1012. The conductive structure1014is poorly supported by the structure1012due to the contorted shape of the structure1012. Thus, the structure1014may shift from a desired location leading to problematic impairment of device performance, and even to device inoperability.

In some applications, the structure1014may be a conductive interconnect which is utilized for coupling sense/access lines from an upper level (upper deck) of memory to logic circuitry through the structure1002, and the structure1004may be a conductive interconnect which is utilized for coupling sense/access lines (1012) from a lower level (lower deck) of memory to the logic circuitry through the structure1002. The problematic coupling of the structure1014to the contorted structure1012may problematically impact the coupling of the sense/access lines from the upper level to the logic circuitry.

FIG. 5diagrammatically illustrates an example prior art arrangement for a series of the conductive interconnects1004at a process stage A. Specifically, the interconnects are in a staggered arrangement along a supporting base1016.

A series of sense/access lines1012is formed over the interconnects1004at a process stage B. The interconnects1004are shown in dashed-line (phantom) view at the process stage B to indicate that they are under the sense/access lines1012.

The second interconnects1014are formed on the sense/access lines1012, and directly over the first interconnects1004, at a process stage C.

FIG. 6shows a cross-sectional view along one of the sense/access lines1012ofFIG. 5, and shows the conductive interconnect1014being formed directly over the conductive interconnect1004. In the illustrated application, the conductive interconnect1004penetrates into the sense/access line1012due to the conductive interconnect1004having the problematic upward projection (step)1007described above with reference toFIG. 1.

Although the interconnect1014is shown to be aligned with the interconnect1004, in practice the projection1007may alter the shape of the conductive line1012to render it difficult, if not impossible, to appropriately land the interconnect1014on the conductive line1012. The interconnect1014may miss the line1012entirely (i.e., may be shifted in or out of the page relative to the cross-sectional view ofFIG. 6), or may only catch an edge of the line1012, as is diagrammatically illustrated inFIG. 4.

It is desired to develop assemblies which alleviate the problems associated with attempting to land the upper interconnects1014on the conductive structures1012. Specifically, it is desired to avoid landing the upper interconnects1014on surfaces which may be shifted by the projecting regions1007.

DETAILED DESCRIPTION OF THE ILLUSTRATED EMBODIMENTS

Some embodiments include multilevel (multitier, multideck) arrangements having vertically-extending interconnects within gaps between the various levels. The interconnects alternate between first interconnects and second interconnects in a vertical direction. The second interconnects are laterally offset relative to the first interconnects. In some embodiments, the first and second interconnects may be incorporated into conductive paths which electrically couple sense/access lines with logic circuitry (e.g., CMOS). Example embodiments are described with reference toFIGS. 7-14.

It is useful to describe example memory arrays before describing the interconnect arrangements of example embodiments. A region of an example memory array10is shown inFIG. 7. The array comprises memory devices20. First sense/access lines14are over the memory devices, and second sense/access lines16are under the memory devices. The first sense/access lines14extend along an illustrated y-axis direction, and the second sense/access lines16extend along the illustrated x-axis direction. In some embodiments, the first sense/access lines14may be considered to extend along a first direction, and the second sense/access lines16may be considered to extend along a second direction which crosses the first direction. The second direction may be substantially orthogonal to the first direction (as shown), or not. The term “substantially orthogonal” means orthogonal to within reasonable tolerances of fabrication and measurement.

The term “sense/access line” (or alternatively, the term “access/sense line”) is generic for wordlines (access lines) and bitlines (sense lines). In some embodiments, the conductive lines14may be wordlines while the conductive lines16are bitlines, and in other embodiments the conductive lines16may be the wordlines while the conductive lines14are the bitlines.

The conductive lines14may be considered to form a first set12of the sense/access lines, and the conductive lines16may be considered to form a second set18of the sense/access lines.

The memory devices20are at cross-points where the first sense/access lines14overlap the second sense/access lines16. In some embodiments, the illustrated assembly ofFIG. 7may be considered to be an example of a three-dimensional cross-point memory configuration. Each of the memory devices20comprises a memory cell22over an access device (select device)24.

The memory cells22may comprise any suitable configurations, and may comprise programmable material having two or more selectable resistive states to enable storing of information. Examples of such memory cells are resistive RAM (RRAM) cells, phase change RAM (PCRAM) cells (or, more generally, phase change memory (PCM) cells), and programmable metallization cells (PMCs)—which may be alternatively referred to as a conductive bridging RAM (CBRAM) cells, nanobridge memory cells, or electrolyte memory cells. The memory cell types are not mutually exclusive. For example, RRAM may be considered to encompass PCRAM and PMCs. Additional example memory includes ferroelectric memory, magnetic RAM (MRAM) and spin-torque RAM.

The access devices24may comprise any suitable configurations. For instance, the access devices may comprise diodes, ovonic threshold switches (OTSs), etc.

The memory array10may be considered to be configured as a memory deck11.

FIG. 8shows another example memory array30. The memory array30comprises three sets12,18and26of the sense/access lines: with the first set12comprising the sense/access lines14, the second set18comprising the sense/access lines16, and the third set26comprising sense/access lines28. The sense/access lines16may be considered to be first sense/access lines, and the sense/access lines14and28may be considered to be second sense/access lines. The first sense/access lines16may correspond to either bitlines or wordlines, and the second sense/access lines14and28may correspond to the other of bitlines and wordlines. In other words, in some embodiments the first sense/access lines16may be bitlines while the sense/access lines14and28are wordlines, or vice versa.

The set18of the first sense/access lines may be considered to be vertically sandwiched between the sets12and26of the second sense/access lines. The memory devices20between the sets18and26of sense/access lines may be referred to as a first set of memory devices (with an example memory device of the first set being labeled20a), and the memory devices20between the sets18and12of the sense/access lines may be referred to as a second set of memory devices (with an example memory device of the second set being labeled20b).

The memory devices20aand20bofFIG. 8may be identical to the devices20ofFIG. 7, and may each comprise an access device (i.e., the device24ofFIG. 7) in combination with a memory cell (i.e., the memory cell22ofFIG. 7). The structures22and24are not shown inFIG. 8in order to simplify the drawing. In some embodiments, the illustrated assembly ofFIG. 8may be considered to be another example of a three-dimensional cross-point memory configuration.

The memory array30may be considered to be configured as a memory deck31.

Each of the memory cells ofFIGS. 7 and 8is uniquely addressed by a pair of the sense/access lines. For instance, each of the memory devices20ofFIG. 7is uniquely addressed by one of the sense/access lines14in combination with one of the sense/access lines16. Similarly, each of the memory devices20ofFIG. 8is uniquely addressed by one of the sense/access lines16in combination with one of the sense/access lines14or one of the sense/access lines28. In some applications, the sense/access lines16may be considered to be shared sense/access lines in that they are shared between pairs of memory cells (and associated memory devices). For instance, one of the sense/access lines16ofFIG. 8is labeled as16a, and such is shared between the memory devices labeled20aand20b.

FIG. 9shows an integrated assembly40comprising a base32, and comprising a pair of the memory decks31over the base. The decks are labeled as31aand31bso that they may be distinguished from one another.

The base32comprises logic circuitry, with such logic circuitry being shown to be subdivided between two regions34and36. The logic circuitry may comprise any suitable configuration(s), and in some embodiments may comprise CMOS. One of the regions34and36may comprise bitline decoder circuitry and/or sensing circuitry (e.g., sense amplifier circuitry), and the other may comprise wordline decoder circuitry and/or wordline driver circuitry.

The sense/access lines16of the upper and lower decks31aand31bare electrically coupled with the circuitry region36through interconnects42and44, respectively; and through a shared interconnect46. The sense/access line16of the upper deck31bmay be considered to have a conductive path to the region36which overlaps a conductive path from the sense/access line16of the lower deck31ato the region36, with the coupling of the conductive paths being diagrammatically illustrated with a box (junction)46. Similarly, the sense/access lines28of the upper and lower decks31aand31bhave conductive paths to the circuitry region34which include interconnects48and50, and the sense/access lines14of the upper and lower decks have conductive paths to the circuitry region34which include interconnects52and54. Boxes (junctions)46are provided to diagrammatically illustrate coupling of the conductive interconnects48and50along an overlapping conductive path, and coupling of the conductive interconnects52and54along an overlapping conductive path.

It is desired to develop architectures suitable for achieving the coupling between the overlapping conductive paths ofFIG. 9while avoiding the problems described above with reference to the prior art of the Background section. Example architectures are described with reference to the remaining figures (FIGS. 10-14). The architectures may be suitable for coupling sense/access lines of multiple memory decks to achieve overlapping conductive paths, and/or may be suitable for other applications in which it is desired to achieve overlapping conductive paths.

Referring toFIG. 10, a portion of the base32is illustrated at a process stage A. The portion comprises the circuitry region36. The conductive interconnects46are shown to be distributed across the region36. The conductive interconnects46are arranged in a pair of rows56and58, with such rows extending along an illustrated direction of an x-axis. The rows56and58may be referred to as a first row and a second row, respectively. The first and second rows56and58are offset from one another along an illustrated y-axis direction. In some embodiments, one of the x-axis and y-axis directions may be referred to as a first direction and the other may be referred to as a second direction.

The conductive interconnects46are numbered consecutively 1 through 5 along the direction of the x-axis. Some of the conductive interconnects46are oddly numbered (i.e., are numbered 1, 3 and 5), and some are evenly numbered (i.e., are numbered 2 and 4). The oddly numbered interconnects are within the first row56and the evenly numbered interconnects are within the second row58.

A process stage B ofFIG. 10shows regions of the sense/access lines16extending over the interconnects46. The sense/access lines extend along the y-axis direction, and are spaced from one another by intervening spaces60. In some embodiments, the sense/access lines16may be considered to be generically representative of conductive lines or conductive structures.

A process stage C ofFIG. 10shows the second conductive contacts44formed over the conductive lines16. The second conductive interconnects are numbered consecutively 1 through 5 along the direction of the x-axis. Some of the conductive interconnects44are oddly numbered (i.e., are numbered 1, 3 and 5), and some are evenly numbered (i.e., are numbered 2 and 4). In the shown embodiment, the second conductive interconnects44are arranged in the pair of rows56and58, with the evenly numbered interconnects44being in the first row56and the oddly numbered interconnects44being in the second row58.

FIGS. 11 and 12show cross-sectional side views along a pair of the conductive lines16at the process stage C ofFIG. 10. Specifically, two of the lines16at the process stage C are labeled as16aand16b, andFIGS. 11 and 12show cross-sections along the lines16aand16b, respectively.

Referring toFIG. 11, the base32comprises a conductive structure62which is electrically coupled with logic circuitry64. The circuitry64may comprise the decoder circuitries, driver circuitries, sensing circuitries, etc., described above with reference to the circuitries34and36ofFIG. 9.

The interconnect46is coupled with the structure32, and extends upwardly to the conductive line16a. In the illustrated embodiment, the interconnect46penetrates into the conductive line16ain a manner analogous to that described above with reference to the prior art structure ofFIG. 6. However, the upper interconnect44is laterally offset relative to the lower interconnect46so that any problems associated with a region of the conductive line16adirectly over the conductive interconnect46will not adversely impact fabrication of the interconnect44. Thus, the problems described above in the Background section may be avoided.

The configuration ofFIG. 11has the lower interconnect46corresponding to the oddly numbered lower interconnect “1” (from the process stage A ofFIG. 10) and has the upper interconnect44corresponding to the oddly numbered upper interconnect “1” (from the process stage C ofFIG. 10).

FIG. 12shows a structure similar to that ofFIG. 11, but shows the upper interconnect44laterally shifted in an opposite direction relative to the lower interconnect46as compared to the configuration ofFIG. 11. Also, the configuration ofFIG. 12has the lower interconnect46corresponding to the evenly numbered lower interconnect “2” (from the process stage A ofFIG. 10) and has the upper interconnect44corresponding to the evenly numbered upper interconnect “2” (from the process stage C ofFIG. 10).

The structures62,46,16and44ofFIGS. 11 and 12may be compositionally the same as one another, or at least one of such structures may be compositionally different relative to at least one other of such structures. In some embodiments, the interconnects46may be compositionally different from the conductive lines16(i.e.,16aofFIGS. 11 and 16bofFIG. 12). For instance, the conductive interconnects46may comprise a different metal and/or metal-containing composition than the conductive lines16.

The configurations ofFIGS. 10-12pertain to the sense/access lines16ofFIG. 9. It is to be understood that similar configurations may pertain to the sense/access lines14and28ofFIG. 9.

The configurations ofFIGS. 10-12may be considered to show regions of the sense/access lines16which are laterally outward of the memory arrays30aand30bof the upper and lower decks31aand31bofFIG. 9.

FIGS. 13 and 14show diagrammatic views of an integrated assembly70comprising multiple vertically-stacked decks (levels, tiers)31a-dover a base32. Only the sense/access lines16are shown within the decks31a-dto simplify the drawing, but it is to be understood that the other sense/access lines14and28may also be within the decks. Although the integrated assembly is shown comprising at least four decks (actually more than four decks forFIG. 13as only one set of the sense/access lines (e.g., bitlines16) are shown, and as the illustrated sense/access line (e.g., bitline) may be shared between two vertically adjacent other sense/access lines (e.g., wordlines14and28ofFIG. 9) so that two memory cell sets are along each of the illustrated sense/access lines16), it is to be understood that the integrated assembly may extend upwardly beyond the shown region to comprise more than the illustrated decks (as is diagrammatically illustrated with dots provided above the top deck31dto indicate that more decks may be above the top deck). Alternatively, the integrated assembly may comprise fewer than illustrated decks.

The base32comprises the circuitry64(e.g., logic circuitry which may include one or more of decoder circuitry, sensing circuitry, wordline driver circuitry, etc.). In some embodiments, the circuitry64may be referred to as first circuitry.

The decks31a-dcomprise memory arrays30a-d, respectively. In some embodiments, each of the memory arrays may be considered to have a first side71and an opposing second side73(with the sides71and73being shown relative to the memory array30d). The sense/access lines16may extend laterally outward beyond the first and second sites71and73of the memory arrays, as shown. Each of the sense/access lines may include a coupling region72(only some of which are labeled) which electrically couples the sense/access line with the circuitry64of the base32. In some embodiments, the coupling regions72along the first sides71of the memory arrays30may be referred to as first coupling regions72a, and the coupling regions72along the second sites73of the memory arrays30may be referred to as second coupling regions72b.

In some embodiments, the decks31a,31b,31cand31dmay correspond to a first, second, fourth and sixth deck, respectively. In some embodiments, they may correspond to as a first, second, fourth and sixth memory deck, respectively, and may be considered to each comprise memory circuitry. The illustrated conductive lines16within the decks31a,31b,31cand31dmay be referred to as first, second, third and fourth conductive lines, respectively; or as first, second, third and fourth conductive structures, respectively.

In the illustrated embodiment, the decks (levels, tiers)31a-dare vertically spaced from one another by intervening gaps66b,66cand66d, and the base32is spaced from the bottom deck31aby an intervening gap66a. In some embodiments, the gaps66may be considered to alternate between first gaps and second gaps, with the gaps66aand66cbeing representative of the first gaps, and the gaps66band66dbeing representative of the second gaps.

Conductive interconnects46extend upwardly from the base and are electrically coupled with the circuitry64. Only some of the interconnects46are labeled. One of the interconnects46is labeled as46aso that it may be distinguished from the other interconnects. The interconnect46amay be referred to as a first conductive interconnect. The first conductive interconnect46aextends between the base32and the sense/access line (first conductive line, first conductive structure)16aof the deck31a. The first conductive line16ais coupled with logic circuitry64within the base32through at least the first conductive interconnect46a.

A second conductive interconnect44aextends between the sense/access line16aof the deck31aand the sense/access line (second conductive line, second conductive structure)16bof the deck31b. The second conductive line16bwithin the deck31bis electrically coupled with the logic circuitry64through a conductive path which includes the first and second conductive interconnects44aand46a, and a region74of the first conductive line16a. In the illustrated embodiment, the first conductive interconnect46ais laterally offset from the second conductive interconnect44aalong the illustrated y-axis, and is offset by a distance which includes the entirety of the memory array30a. In other embodiments, the conductive interconnects44aand46amay be laterally offset from one another, but may be on the same side of the memory array30aas one another.

Referring toFIG. 14, the first conductive structure16amay be considered to have a first region76directly over the conductive interconnect46a, a second region78laterally offset from the first region, and the region74as a third region between the first and second regions. The second conductive interconnect44aextends upwardly from the second region78to the second conductive structure16b. The first conductive structure16ais electrically coupled to the CMOS circuitry (e.g., the circuitry64) through a first conductive path which includes at least the first interconnect46a, and the second conductive structure is electrically coupled to the CMOS circuitry (e.g., the circuitry64) through a second conductive path which includes at least the second conductive interconnect44a, the third region74of the first conductive structure16a, and the first conductive interconnect46a.

The structures16a-dmay be considered to have overlapping conductive paths which extend to the CMOS circuitry (e.g., the circuitry64) within the base32, with such conductive paths extending across the gaps66a-d. The conductive paths may be considered to comprise first interconnects46aand86awithin the first gaps66aand66c, and to comprise second conductive interconnects44aand84awithin the second gaps66band66d. The first interconnects (i.e.,46aand86a) are laterally offset relative to the second interconnects44(i.e.,44aand84a).

In some embodiments, the structures16a,16b,16c,16d,44a,46a,84aand86amay all be compositionally the same as one another (e.g., may all comprise the same metal, metal-containing compositions, etc.). In other embodiments, at least one of the structures16a,16b,16c,16d,44a,46a,84aand86amay be compositionally different from at least one other of the structures16a,16b,16c,16d,44a,46a,84aand86a. For instance, in some embodiments the interconnects44a,46a,84aand86aare compositionally the same as one another, and are compositionally different from the conductive structures16a-d. For instance, the interconnects44a,46a,84aand86amay comprise different metals and/or metal-containing compositions relative to the conductive structures16a-d.

The embodiments described herein may be utilized relative to integrated memory and/or may be utilized relative to other integrated assemblies. Generally, the embodiments may be considered to be broadly applicable to any semiconductor industry application.

The assemblies and structures discussed above may be utilized within integrated circuits (with the term “integrated circuit” meaning an electronic circuit supported by a semiconductor substrate); and may be incorporated into electronic systems. Such electronic systems may be used in, for example, memory modules, device drivers, power modules, communication modems, processor modules, and application-specific modules, and may include multilayer, multichip modules. The electronic systems may be any of a broad range of systems, such as, for example, cameras, wireless devices, displays, chip sets, set top boxes, games, lighting, vehicles, clocks, televisions, cell phones, personal computers, automobiles, industrial control systems, aircraft, etc.

The terms “dielectric” and “insulative” may be utilized to describe materials having insulative electrical properties. The terms are considered synonymous in this disclosure. The utilization of the term “dielectric” in some instances, and the term “insulative” (or “electrically insulative”) in other instances, may be to provide language variation within this disclosure to simplify antecedent basis within the claims that follow, and is not utilized to indicate any significant chemical or electrical differences.

The terms “electrically connected” and “electrically coupled” may both be utilized in this disclosure. The terms are considered synonymous. The utilization of one term in some instances and the other in other instances may be to provide language variation within this disclosure to simplify antecedent basis within the claims that follow.

The cross-sectional views of the accompanying illustrations only show features within the planes of the cross-sections, and do not show materials behind the planes of the cross-sections, unless indicated otherwise, in order to simplify the drawings.

When a structure is referred to above as being “on”, “adjacent” or “against” another structure, it can be directly on the other structure or intervening structures may also be present. In contrast, when a structure is referred to as being “directly on”, “directly adjacent” or “directly against” another structure, there are no intervening structures present. The terms “directly under”, “directly over”, etc., do not indicate direct physical contact (unless expressly stated otherwise), but instead indicate upright alignment.

Structures (e.g., layers, materials, etc.) may be referred to as “extending vertically” to indicate that the structures generally extend upwardly from an underlying base (e.g., substrate). The vertically-extending structures may extend substantially orthogonally relative to an upper surface of the base, or not.

Some embodiments include an integrated assembly having a base which includes circuitry. A first conductive interconnect extends upwardly from the base. A first level is over the base and includes a first conductive structure. The first conductive structure is coupled with the circuitry through at least the first conductive interconnect. The first conductive structure has a first region directly over the first conductive interconnect, a second region laterally offset from the first region, and a third region between the first and second regions. A second conductive interconnect extends upwardly from the second region of the first conductive structure. A second level is over the first level and includes a second conductive structure. The second conductive structure is coupled with the circuitry through at least the first conductive interconnect, the third region of the first conductive structure and the second conductive interconnect.

Some embodiments include an integrated assembly having a base which includes logic circuitry. A first deck is over the base. The first deck includes first memory circuitry and a first conductive line associated with the first memory circuitry. A second deck is over the first deck. The second deck includes second memory circuitry and a second conductive line associated with the second memory circuitry. A first conductive interconnect extends between the base and the first deck. The first conductive line is coupled with the logic circuitry through at least the first conductive interconnect. A second conductive interconnect extends between the first deck and the second deck. The second conductive line is coupled with the logic circuitry through a path which includes the first and second conductive interconnects, and a region of the first conductive line. The first conductive interconnect is laterally offset from the second conductive interconnect.

Some embodiments include an integrated assembly having a base which includes first circuitry. Memory decks are over the base. Each of the memory decks has a sense/access line coupled with the first circuitry. The memory decks are vertically spaced from one another by gaps. The gaps alternate in a vertical direction between first gaps and second gaps. A gap between the base and a bottommost of the memory decks is one of the first gaps. Overlapping conductive paths extend from the sense/access lines to the first circuitry. The conductive paths include first conductive interconnects within the first gaps and second conductive interconnects within the second gaps. The first and second conductive interconnects are laterally offset relative to one another.