Detecting problematic voltage signals from charge pumps

Techniques and apparatuses are provided for testing a charge pump. A test circuit detects voltage drop-offs in a voltage signal provided by a charge pump in a test period. A comparator is used to compare the voltage signal to a divided down, delayed version of the signal. A counting circuit is connected to an output of the comparator to determine a number of the drop-offs in the test period. A control circuit such as an on-chip state machine compares the number of drop-offs to a maximum allowable number of drop-offs to set a pass/fail status of the charge pump. The control circuit can configure various parameters of the test, including a ratio of a voltage divider, and the maximum allowable number of drop-offs based on the charge pump being tested.

BACKGROUND

The present technology relates to charge pumps.

Electronic devices often require regulated voltages in order to operate properly. Typically, a supply voltage of the device is provided to a voltage regulator which can translate the voltage to an output voltage at different levels. Various types of voltage regulators can be used. For example, a charge pump, or voltage converter, provides an output voltage which is different from the supply voltage. A charge pump typically uses capacitors as energy storage elements to provide an output voltage which is higher or lower than the input voltage. Moreover, a charge pump can include voltage regulation circuitry to maintain the output voltage at a constant level.

DETAILED DESCRIPTION

Apparatus and techniques are provided for detecting problematic voltage signals from charge pumps on an integrated circuit or chip.

Charge pumps are used in integrated circuits to provide voltages at specified levels to components of the circuit. A charge pump generally refers to a switching voltage converter that converts an input voltage to a different output voltage. A charge pump includes a storage element such as a capacitor to repeatedly transfer charge from an input node to an output node according to a clock signal. The clock signal is used to control the timing of the opening and closing of switches which transfer the charge. A feedback mechanism may be used to regulate the output voltage at a specified level by alternately blocking the clock signal from reaching the charge pump and allowing the clock signal to reach the charge pump.

Charge pumps play an important role in integrated circuits. For example, in a memory device, charge pumps can be used to provide voltage signals for erase, program and read operations. Moreover, the voltage signals may be at a relatively high level such as 10-25 V or more. A test can be performed to detect a faulty output in a charge pump. One approach is to determine if a charge pump can complete an operation such as an erase operation in a specified amount of time. However, this approach may not identify marginal charge pumps which have a small current leak caused by a weak short circuit path, since a charge pump may initially pass such a test when the charge pump is new. However, the leaks can worsen over time when the integrated circuit is used by an end user. For example, in a memory device, a leak can worsen as the device undergoes program-erase cycles.

Techniques and apparatuses provided herein address the above and other issues. In one approach, a test circuit is provided which detects voltage drop-offs in a voltage signal provided by a charge pump in a test period. Referring toFIG. 3A, for example, a comparator is used to compare the voltage signal to a divided down, delayed version of the signal. A counting circuit is connected to an output of the comparator to count a number of the drop-offs in the test period. A control circuit such as an on-chip state machine manages the test, and compares the number of drop-offs to a maximum allowable number of drop-offs to set a pass/fail status of the charge pump. The control circuit can configure various parameters of the test, including a ratio of a voltage divider, and the maximum allowable number of drop-offs based on the charge pump being tested.

Generally, the techniques can be used to effectively determine problematic voltage signals of charge pumps. Potentially defective chips can be proactively screened for small current leaks at the time of manufacture as well as when the chips are in the field, in the hands of the end users.

These and other benefits are further discussed below.

FIG. 1Adepicts an example voltage signal output by a charge pump, before and after a voltage divider, where the voltage signal includes voltage drop-offs. The vertical axis depicts voltage and the horizontal axis depicts time. In this example, the charge pump is requested to output a fixed voltage, Vtarget, in a time period t0-tp. The voltage signal of plot100initially increases to the desired level, as depicted by plot101, and is maintained at the desired level until a drop-off (plot102). The voltage signal quickly recovers to the desired level but a number of additional drop-offs occur, as depicted by plots103,104and105. Each drop-off represents a sudden down spike in the voltage and can be caused by a defect in the charge pump.

A minimum voltage, Vmin, can be defined as the minimum acceptable level of the voltage signal when the requested output is Vtarget. Vtarget−Vmin=ΔV1 represents an allowable margin in the charge pump output, such as to account for variations in the fabrication process. This margin may be referred to as a guard band voltage and may be determined as a ratio of Vtarget using a voltage divider or as a fixed value. The performance of the charge pump is considered to be acceptable if the voltage remains above Vmin. For example, the drop-off of plot102does not fall below Vmin so that this drop-off does not disqualify the charge pump. However, the drop-offs of plots103-105do fall below Vmin. These drop-offs can potentially disqualify the charge pump from use. In one approach, a charge pump is allowed to have no more than a maximum allowable number of drop-offs in a specified test period (tp). If it has more than the maximum allowable number of drop-offs, a fail status is set for the charge pump and it is disqualified from use. The entire chip in which the charge pump is located may also be disqualified.

One approach to detecting drop-offs is to use a comparator to compare the voltage signal100at the level of Vtarget to another voltage signal (plot106) at the level of Vmin. However, these voltage signals can be at a relatively high level, so that the comparator has to be relatively large to withstand the voltages. Another approach it to divide down the voltage signals using a voltage divider. The voltage of each signal is reduced according to a ratio of the voltage divider. In this example, the voltage signals of plots100and106are divided down to provide the voltage signals of plots110and116, respectively. Vtarget is divided down to Vtarget_div, and Vmin is divided down to Vmin_div, where Vtarget_div−Vmin_div=ΔV2 and ΔV2ΔV1.

The voltage signal of plot110initially increases to the desired level, Vtarget_div, as depicted by plot111. The drop-off of plot112does not fall below Vmin_div, while the drop-offs of plots113,114and115do fall below Vmin_div. Vmin_div is the minimum acceptable level of the voltage signal when the requested output is Vtarget. Vtarget-Vmin=ΔV2 represents an allowable margin or guard band voltage. The performance of the charge pump is considered to be acceptable if the voltage remains above Vmin_div.

A comparator can be used which is reduced in size in accordance with the reduction in voltage to compare the voltage signal110at the level of Vtarget_div to another voltage signal (plot116) at the level of Vmin_div. The comparator can detect each drop-off which falls below Vmin_div.

FIG. 1Bdepicts the voltage signal of plot110ofFIG. 1Aand a divided down version of the voltage signal (plot120). A divided down version of a voltage signal refers to one signal which is derived by reducing the voltage of another signal such as by using a voltage divider. Plot120is the same as plot110but is divided down, e.g., reduced in magnitude by an amount ΔV2. Plot120represents plot100divided down twice. The voltage signal of plot120initially increases to Vmin_div as depicted by plot121. The drop-offs of plots122,123,124and125correspond to the drop-offs of plots112,113,114and115, respectively.

FIG. 1Cdepicts the voltage signal of plot110ofFIG. 1Band a delayed version of the voltage signal of plot120as plot130. For example, a delay d is depicted between the corresponding drop-offs of plots115and135. The voltage signal of plot130initially increases to Vmin_div as depicted by plot131. The drop-offs of plots132,133,134and135correspond to delayed versions of the drop-offs of plots112,113,114and115, respectively.

The drop-off of plot112does not fall below Vmin_div, while the drop-offs of plots113,114and115do fall below Vmin_div. In this approach, there is no need for a separate voltage generator to provide a voltage signal at the level of Vmin_div. This approach also could be used without dividing down the voltage signal of the charge pump. In this case, the voltage signal of plot100can be compared to a delayed version of the voltage signal of plot100.

By comparing an original voltage signal (e.g., plot110) to a delayed and divided down version of the original voltage signal (e.g., plot130), a desired guard band voltage (Vtarget_div−Vmin_div=ΔV2) can be defined for testing the performance of a charge pump. Further, the delay ensures that the drop-offs do not align in the two signals, so that the drop-off in plot110is measured against Vmin_div and not a lower level. Generally, it is highly unlikely that drop-offs align in the two signals. If a drop-off in the non-delayed signal110did align with a drop off in the delayed signal of plot130, it is possible that the drop-off in the signal110is not detected. The techniques provided herein can allow for testing using multiple delay levels to address this unlikely case.

FIG. 1Ddepicts a signal145comprising pulses which identify drop-offs in the voltage signal110ofFIG. 1C. The pulses141,142and143represent a voltage increase from a low level to a high level followed by a decrease back to the low level for each of the drop-offs of plots113,114and115, respectively. The drop off of the plot112is not large enough to trigger a pulse. In one approach, the signal is a voltage signal output by the comparator318ofFIG. 3A.

FIG. 2depicts a cross-sectional view of a capacitor in a charge pump, showing a defect which can cause voltage drop-offs as depicted inFIG. 1A-1C. A leaky path200, or weak short circuit, is depicted in an oxide203between parallel plates201and202of the capacitor. One of the plates is at a high voltage and the other plate is grounded. Such a defect is caused during fabrication and can worsen over time. This is one example of a defect in a charge pump which can lead to an unstable output including voltage drop-offs. The capacitor in this example has a finger structure, where the plates are formed by metal lines in a metal-oxide-metal MOM configuration.

FIG. 3Adepicts a test circuit300for testing for drop-offs in voltage signals of different charge pumps. Generally, testing can occur for one or more charge pumps on a chip. Efficiencies are achieved by using the same testing circuit for multiple charge pumps. In this example, there are three charge pumps, charge pump A301, charge pump B302and charge pump C303, which provide a respective output voltage signal on a respective output path304,305and306. In other cases, such as inFIG. 6A, additional charge pumps can be connected to the test circuit for testing. Each charge pump can be in a charge pump circuit such as inFIG. 4.

The output paths are provided as inputs to a multiplexer307. The multiplexer is thus connected to output paths of a plurality of charge pumps, and a control circuit such as the state machine is configured to provide a signal to the multiplexer selecting a charge pump from among a plurality of charge pumps.

For a given test, one of the charge pumps is selected and its output is passed by the multiplexer to a path308as a voltage Vout. Vout can be divided down by a second voltage divider309to provide a divided down voltage signal Vpath1at a path310. The path310is connected between resistors Ra and Rb of the voltage divider so that Vpath1=Vout×Rb/(Ra+Rb). The ratio could be one half or less, for example. For example, Vout may correspond to the plot100ofFIG. 1Ahaving a nominal voltage of Vtarget, and Vpath1may correspond to the plot110ofFIG. 1Ahaving a nominal voltage of Vtarget_div, where Vtarget_div=Vtarget×Rb/(Ra+Rb). The nominal voltage of a voltage signal refers to the voltage when a drop-off does not occur. This is the requested or target output voltage of a charge pump.

A set of first voltage dividers312is connected to the path310by a path311. The set of first voltage dividers may be configured, e.g., as depicted inFIGS. 3B and 3C. One voltage divider is selected in the set to divide down Vpath1based on a desired guard band voltage. For example, Vpath1may correspond to the plot110ofFIG. 1Bhaving a nominal voltage of Vtarget_div, and the voltage signal on the path313, Vpath1_div, may correspond to the plot120ofFIG. 1Bhaving a nominal voltage of Vmin_div.

The divided down signal is output on the path313to a delay circuit314. The delay circuit can be configured to provide one or more specified delays to the voltage signal on the path313and provide a corresponding delayed signal on the path315as Vpath2. The delay circuit may be configured, e.g., as depicted inFIG. 3D. For example, the non-delayed voltage signal on the path313may correspond to the plot120ofFIG. 1Bhaving the nominal voltage of Vmin_div, and the delayed voltage signal on the path315may correspond to the plot130ofFIG. 1Chaving the nominal voltage of Vmin_div. The delay circuit can optionally be provided before the voltage dividers.

The voltage signal on the path310(a first input path) has the voltage Vpath1and is provided to a first input, e.g., a non-inverting input316, of a comparator318. The voltage signal on the path315(a second input path) has the voltage Vpath2and is provided to a second input317, e.g., an inverting input, of the comparator. The comparator is an example of an op-amp comparator circuit. When Vpath1<Vpath2, the voltage Vcomp at an output path319of the comparator is high. When Vpath1>Vpath2, Vcomp is low. See alsoFIG. 1Dfor an example voltage signal, including pulses141-143, of the path319. A counting circuit320receives the voltage signal on the path319and counts a number of times the voltage signal transitions from low to high, for example. Each transition corresponds to a downward transition or drop-off in a voltage (Vpath1) on the first input path310, where the downward transition is below Vpath2and therefore more than a guard band voltage set by a voltage divider in the set of voltage dividers312.

Essentially, the counting circuit320counts a number of pulses in the voltage signal on path319. An example counting circuit is depicted inFIG. 3E.

A state machine812or other control circuit can be provided on the chip to communicate with the various components and manage the test. The state machine is one example of a control circuit. Other embodiments for a control circuit include, e.g., a microprocessor, microcontroller, FPGA, a hardware only circuit, a hardware with software circuit and so forth.

For example, the state machine may send a request to activate one of the charge pumps301-303for a test. The state machine may send a request to the multiplexer307to connect the output path of the selected charge pump to the path308. The state machine may send a request to the set of voltage dividers312to select one of the voltage dividers, e.g., using a corresponding switch as depicted inFIGS. 3B and 3C. The state machine may send a request to the set of delay circuits314to select one of the delay circuits, e.g., using a corresponding switch as depicted inFIG. 3D.

In this example, the test circuit300is separate from the state machine, which may be a pre-existing component on a chip. In this way, the functionality of the test circuit can easily be added to a chip which has a state machine. The state machine can be configured with firmware for performing the functions described herein.

FIG. 3Bdepicts an example implementation of the set of voltage dividers312ofFIG. 3A. Vpath1is input on the path311and a divided down voltage Vpath1_div is output on the path313. In this example, five separate voltage dividers with different respective ratios are provided. A set of resistors R1-R5are connected to switches SW1-SW5, respectively. A resistor Rr is connected between the path313and ground. One of the switches can be selected, e.g., switched on or made conductive, to select a corresponding ratio. The remaining switches are switched off or non-conductive. For example, if SW1, SW2, SW3, SW4and SW5is selected, the ratio is Rr/(R1+Rr), Rr/(R2+Rr), Rr/(R3+Rr), Rr/(R4+Rr) or Rr/(R5+Rr), respectively. R1-R5are the top resistors and Rr is the bottom resistor. A larger value of the top resistor results in a lower ratio, a lower output voltage and a larger guard band. The output voltage, Vpath1_div, is equal to Vpath1×ratio. This approach is efficient since there is a single bottom resistor.

As an alternative, more than one switch can be switched on to obtain other ratios.

FIG. 3Cdepicts another example implementation of the set of voltage dividers312ofFIG. 3A. This approach provides greater flexibility thanFIG. 3Bsince the top and bottom resistors can differ in each voltage divider. In this example, five separate voltage dividers321-325(first voltage dividers) with different respective ratios are provided. The set of top resistors R1-R5are connected to switches SW1-SW5, respectively, as inFIG. 3B. However, a different bottom resistor R6-R10is connected in series with each top resistor R1-R5, respectively. One of the switches can be selected, e.g., switched on or made conductive, to select a corresponding ratio, while the remaining switches are switched off or non-conductive. For example, if SW1, SW2, SW3, SW4or SW5is selected, the ratio is R6/(R1+R6), R7/(R2+R7), R8/(R3+R8), R9/(R4+R9) or R10/(R5+R10), respectively.

FIG. 3Ddepicts an example implementation of the delay circuit314ofFIG. 3A. This example provides a set of two delay circuits. Vpath1_div is input on the path313and Vpath2is output on the path315. The set of delay circuits includes a resistor R in series with the paths313and315. A first delay circuit326comprises the resistor R and the capacitor C1, and a second delay circuit327comprises the resistor R and the capacitor C2. C1and C2are connected to the resistor R by switches SW6and SW7, respectively. To select the delay of C1, SW6is switched on and SW7is switched off. To select the delay of C2, SW7is switched on and SW6is switched off. As an alternative, more than one switch can be switched on to obtain other delays.

The delay circuit provides a delay which is proportional to the time constant RC. Thus, a larger capacitance and a larger resistance corresponds to a larger delay. The resistor reduces the amount of current flowing into the capacitor when a voltage transition occurs such as a drop-off. When the drop-off occurs in Vpath1_div, the capacitor will take some time to discharge before the drop-off is provided in Vpath2. The discharge time will be larger when the drop-off is greater. After the drop-off, the capacitor will charge back up to the nominal voltage of Vmin_div (FIG. 1C).

FIG. 3Edepicts an example implementation of the counting circuit320ofFIG. 3A. The counting circuit can comprise a number of flip-flops FF0-FF3. The example depicts a four bit asynchronous up counter which comprises four positive edge triggered D type flip-flops connected in toggle mode. Each flip flop has a clock (CK) input. Data from an output Q bar is fed back to a data input (D), and an output Q is connected to a bit node. For example, FF0-FF3have bit nodes330-333, respectively. The bit nodes provide respective bits Q0-Q3of a four bit word, e.g., a digital count, which indicates the number of pulses which have been counted. Up to 16 pulses can be counted. Q0is the least significant bit and Q3is the most significant bit, so that the four bit word provide a decimal value based on: Q0×1+Q1×2+Q2×4+Q3×8.

FIG. 3Fdepicts waveforms for a counting process in the circuit ifFIG. 3E. The waveform340includes sixteen example pulses P1-P16and is input to the CK input of FF0. The pulses, which represent voltage drop-offs, are spaced equally in time in this example although in practice they can be unequally spaced. The waveforms350,360,370and380depict Q0, Q1, Q2and Q3, respectively. A low or high level of the waveform depicts a logical 0 or 1, respectively. Generally, the rising edge of the Q output of each flip-flop triggers the CK input of the next flip-flop at half the frequency of the CK pulses applied to its input.

Assuming that the four Q outputs are initially at 0000, the rising edge of the first pulse P1applied will cause Q0to transition to logic 1, and the rising edge of second pulse P2will cause Q0to return to logic 0. The process continues with each pulse such that the rising edge of the odd-numbered pulses cause Q0to transition to logic 1, and the rising edge of the even-numbered pulses cause Q0to return to logic 0. In a similar way, the rising edge of P2, P6, P10and P14will cause Q1to transition to logic 1, and the rising edge of P4, P8, P12and P16cause Q1to return to logic 0. The rising edge of P4and P12will cause Q2to transition to logic 1, and the rising edge of P8and P16cause Q2to return to logic 0. The rising edge of P8will cause Q3to transition to logic 1, and the rising edge of P16will cause Q3to return to logic 0.

FIG. 4depicts an example of a charge pump circuit400comprising the charge pump A301ofFIG. 3A. A similar charge pump circuit can be provided for each of the other charge pumps. The charge pump301has an input node415and an output node406. The output node is connected to a load such as a capacitive load407. For example, in a memory system, the load can represent a word line, bit line, source line or substrate. The load can represent a component in a circuit which operates using the voltage output of the charge pump.

A clamp transistor403can be used to clamp an input voltage at the input node415to Vin, due to potential variations in the supply voltage Vcc from a power supply419. This ensures that the input voltage is fixed even if Vcc varies. The clamp transistor may be an nMOSFET in which the source voltage, Vin, is equal to the control gate voltage minus the threshold voltage (Vth) of the transistor.

A clock source416provides a clock signal constantly or alternatingly to the charge pump301. The clock source, which is a circuit, includes a clock generator405which outputs a constant clock signal at a specified frequency to a clock control circuit404. SeeFIG. 7A. The clock control circuit provides a gating function to either block the signal from reaching the charge pump, or passing the clock signal to the charge pump. For example, the clock signal may be passed when the voltage output of the charge pump is below a desired voltage and blocked when the voltage output of the charge pump is above the desired voltage. The desired voltage can be a fixed level or an increasing level such as a ramp.

The clock signal is responsive to a feedback circuit418which includes a feedback path417, a comparator410and a voltage divider409. The voltage divider409divides the output voltage Vout using resistors Rc and Rd to provide a comparison voltage Vcomp at a node408. Rd can be adjustable to provide voltage trimming Vcomp is compared to a reference voltage Vref at the comparator to set a flag FLG. FLG=0 if Vcomp>Vref and FLG=1 if Vcomp<=Vref. Note that Vcomp is a known fraction Rd/(Rc+Rd) of Vout, so that a comparison of Vcomp to Vref by the comparator is equivalent to a comparison of Vout to a specified output voltage.

When FLG=1, the clock control circuit passes the clock signal to the charge pump to operate the charge pump in a pumping mode, where charge is transferred from the input node415of the charge pump at an input voltage Vin to the output node406. When FLG=0, the clock control circuit does not pass the clock signal to the charge pump, so that the charge pump operates in a non-pumping mode, where charge is not transferred from the input node to the output node. Vout will tend to decay in the non-pumping mode as the load is driven.

FIG. 5Adepicts a flowchart of an example process for testing the voltage output of a charge pump for drop-offs. Step500includes comparing first and second voltage signals from a charge pump, where the second voltage signal (e.g., Vpath2inFIG. 3A) is a divided down, delayed version of the first voltage signal (e.g., Vpath1inFIG. 3A). Step501includes counting a number of times the first voltage signal drops below the second voltage signal (e.g., counting a number of drop-offs in the first voltage signal) in a test period. For example, as mentioned, the drop-offs can be counted by counting the pulses (FIG. 1D) at the output of a comparator. Step502includes comparing the number of drop-offs to a maximum allowable number of drop-offs to set a pass/fail status for the charge pump. Step503notes that test parameters such as a voltage divider ratio (e.g., for the voltage dividers ofFIGS. 3B and 3C), a delay (e.g., for the delay circuits ofFIG. 3D) and maximum allowable number of drop-offs can be customized for the charge pump. See alsoFIG. 6A-6D.

FIG. 5Bdepicts a flowchart of another example process for testing the voltage output of a charge pump for drop-offs, consistent withFIG. 5A. Step510includes entering a test mode at a control circuit. For example, this can be a built in self-test (BIST) mode of a state machine. Various test modes may be possible. Moreover, the control circuit may enter a mode, issue requests and perform other actions by issuing commands using firmware. Further details regarding commands are provided below.

Step511includes entering a voltage drop-off detection mode. Step513includes configuring a selected charge pump to output a voltage signal. For example,FIG. 3Ashows how a state machine812can communicate with charge pumps301-303to instruct one of the charge pumps to begin outputting a voltage signal. In one approach, the selected charge pump outputs a fixed voltage at its highest output level, as this stresses the charge pump to the highest degree and is most likely to reveal drop-offs caused by defects such as weak short circuit paths. Alternatively, the control circuit can specify a particular voltage output in a range of available outputs of the charge pump.

Step514includes configuring a multiplexer (e.g., the multiplexer307inFIG. 3A) to pass the voltage signal from the selected charge pump, e.g., from one of the paths304-306to the path308. Step515includes selecting a guard band voltage, e.g., ΔV2 inFIG. 1C. Step516includes selecting a voltage divider based on the selected guard band voltage. For example,FIG. 3Ashow how a state machine812can communicate with the set of voltage dividers312, andFIGS. 3B and 3Cshow how switches can be configured to select one voltage divider (or ratio) among multiple voltage dividers (or ratios). The control circuit can also access a table for steps514and515such as depicted inFIG. 6B.

Step517includes setting a maximum allowable number of drop-offs. The control circuit can set this internally by accessing a table using a command and address. For example, seeFIG. 6C. Step518includes entering an operation mode and beginning a test period. During the test period, the number of drop-offs is counted, as discussed. These are drop-offs whose magnitude exceeds the guard band voltage. Step519includes waiting until the test period is over. Step520includes reading a count of the number of drop-offs from the counting circuit. For example, the control circuit may communicate with the counting circuit320inFIG. 3Ato obtain a digital count which indicates the number of pulses which have been counted in the output of the comparator318. See alsoFIGS. 3E and 3F.

A decision step521determines whether the count exceeds the maximum (max.) allowable count. If the decision step521is true (T), step522sets a fail status for the charge pump. The die may have to be disabled in this case. In some cases, an alternative or backup die is available in a device. Or, an alternative or backup charge pump may be available on the same die as the failed charge pump. If the decision step521is false (F), step523sets a pass status for the charge pump. Assuming there are no other faults, the die can therefore be delivered to the end user. Step524issues a reset sequence indicating that the test is completed.

Various commands can be issued by a control circuit such as the on-chip state machine to carry out the test, as depicted below.

CMD xx; //This command can be issued at step511to enter the drop-off detection mode.

CMD 55, Addr 0xh, DATA xx; //This command can be issued at step512to select a charge pump, consistent withFIG. 6A.

CMD 55, Addr xxh, DATA yy; //This command can be issued at step515to select a guard band voltage, consistent withFIG. 6B.

CMD 55, Addr yyh, DATA zz; //This command can be issued at step517to set a maximum allowable number of drop-offs, consistent withFIG. 6C.

CMD 1E; //This command is used for unselecting blocks.

CMD 80h; ADDR*5; CMD yyh; //This command can be issued at step518. A pre-determined consistent voltage output can be set by the command CMD yyh.

Delay “X”; //This command can be issued at step519to set the duration of the test in milliseconds.

CMD 70h; RD; // This command can be issued at step520to read (RD) the count of drop-offs and check the pass/fail status.

FIG. 6Ais a table for use in connection with step512ofFIG. 5Bwhich cross-references different charge pumps to different addresses. The tables ofFIG. 6A-6Cmay be provided as part of the state machine812, for example. The state machine may have the ability to test multiple charge pumps on a chip, one charge pump at a time. In this example, there are eight charge pumps labelled as A-H. Charge pumps A-C were depicted inFIG. 3A. The state machine can issue an address 0xh which corresponds to a particular charge pump to select that charge pump for testing. The binary values 000, 001, 010, 011, 100, 101, 110 and 111 correspond to the charge pumps A-H, respectively.

Example voltage signals which are provided by the different charge pumps in a memory device can include a program voltage, erase voltage, read voltage, bit line voltage and unselected word line voltage.

FIG. 6Bis a table for use in connection with step515ofFIG. 5Bwhich cross-references different guard bands to different addresses. The state machine may have the ability to set different guard bands when testing a charge pump. Recall fromFIG. 3A-3Cthat one voltage divider can be selected from among the set of voltage dividers312. In one approach, the guard band is defined by a ratio of a voltage divider. The ratio defines the guard band in terms of the amount by which a voltage is decreased by a voltage divider. Thus, guard band=input voltage×(1−ratio). For example, inFIG. 3C, the ratio of the voltage diver321is R6/(R1+R6). Thus, the guard band voltage is Vpath1×(1−R6/(R1+R6)). If the ratio is 0.90, for example, the guard band is Vpath1×0.1. If Vpath1=10 V, the guard band is 1 V. Recall that Vpath1is a divided down signal obtained from Vout inFIG. 3Ausing the second voltage divider309. As an example, Vpath1=10 V when Vout=20 V and when the ratio of the second voltage divider309is 0.5.

In this example, there are five voltage guard bands, consistent withFIGS. 3B and 3C. The state machine can issue an address xxh which corresponds to a particular guard band and voltage divider. In this example, the binary values 000, 001, 010, 011 and 100 correspond to ratios of 0.98, 0.96, 0.94, 0.92 and 0.90, respectively. If Vpath1=10 V, the binary values 000, 001, 010, 011 and 100 correspond to guard band voltages of 0.2, 0.4, 0.6, 0.8 and 1.0, respectively.

FIG. 6Cis a table for use in connection with step517ofFIG. 5Bwhich cross-references different maximum allowable numbers of drop-offs to different addresses. The state machine may have the ability to set different maximum allowable numbers of drop-offs in a test. The number can be based on various factors such as the duration of the test, and the number of drop-offs which can be tolerated by a circuit connected to the charge pump being tested.

In this example, there are five values of the number. The state machine can issue an address yyh which corresponds to a number. In this example, the binary values 000, 001, 010, 011 and 100 correspond to the values of 1, 2, 4, 6 and 8 drop-offs, respectively.

Other test parameters which could be customized for a test include the delay time d. For example, a table can be provided which cross-references different addresses to different delays, such as 1, 5, 10, or 100 microseconds.

Note that a test can be repeated with different parameters to provide a pass/fail determination for a charge pump. For example, a test can be repeated with different levels of guard band and/or maximum allowable number of drop-offs. In one approach, the test is repeated with larger guard band but a smaller maximum allowable number of drop-offs. The final result of pass or fail can be based on an interim result from each test. It is also possible to classify a charge pump a designation other than pass or fail. For example, a charge pump can be given a score, e.g., from one to ten, in terms of the likelihood of failure over the life of the chip. In another approach, the test is repeated at different times over the life of the chip. If there is a downtrend in the scores, an action can be taken such as repeating the test more frequently or switching to an alternative or backup charge pump.

FIG. 7AtoFIG. 7Dprovide example configurations of a charge pump. A charge pump can use a capacitor to transfer charge from an input node to an output node. In one approach, a MOS (metal oxide semiconductor) capacitor is used. A capacitor can be formed by depositing a layer of metallic conductive material onto a layer of oxide that has been deposited or grown on a layer of semiconductor material, such as a semiconductor wafer, referred to as the body. The semiconductor material may be p-type or n-type, based on the polarity of the body, in which case the capacitor is referred to as being p-type or n-type, respectively. The top conducting layer may be considered to be a gate terminal, while the bottom conducting layer is a source, drain or bulk terminal. In one approach, a capacitor can be formed from a MOSFET by tying its drain, source and bulk terminal together and using the resulting device as a two-terminal device.

To be used as flying capacitor, the technology should provide an opportunity to connect the bulk terminal of the capacitor to a voltage different from that of a substrate. For standard digital technology (p-type substrate, no triple-well) an nMOS capacitor can be used, while for an n-type substrate, a pMOS capacitor can be used. For triple-well technology, any type can be used. For the follower configuration, one terminal is always grounded, so a pMOS or nMOS capacitor can be used. The capacitor can be a metal-oxide-metal (MOM) capacitor typically having a finger structure, or a metal-insulator-metal (MIM) capacitor typically having a plate structure, for example.

FIG. 6Dis a table for use in connection with step517ofFIG. 5Bwhich cross-references charge pumps to a different guard band ratios and maximum allowable numbers of drop-offs. As mentioned in connection with step503, test parameters such as a voltage divider ratio, a delay and a maximum allowable number of drop-offs can be customized for a charge pump. In this example, each charge pump identifier is cross-reference to a guard band ratio (voltage divider ratio) and a maximum allowable number of drop-offs. For example, charge pumps A, B and C are cross-referenced to ratios of 0.98, 0.92 and 0.96, respectively, and to maximum allowable number of drop-offs of 1, 4 and 2, respectively. This is just one example, as each charge pump can be cross-referenced to any ratio and to any maximum allowable number of drop-offs.

For instance, for a charge pump where it is highly important to have a steady output with no or few drop-offs, the ratio can be relatively large, defining a relatively small guard band, and the maximum allowable number of drop-offs can be relatively small.

FIG. 7Adepicts an example implementation of the charge pump301ofFIG. 3Aconfigured as a single-stage charge pump301a. A charge pump generally refers to a switching voltage converter that employs an intermediate capacitive storage element which is sometimes referred to as a flying capacitor or a charge transfer capacitor. One or more flying capacitors can be used. Moreover, a charge pump can include multiple stages connected in series to obtain special features such as a high output voltage and a greater range of output voltages. A charge pump can be constructed or configured for providing voltage conversion for applications including: multiplier, divider, inverter and follower. The principles discussed herein can be applied to one or more stages, and to one or more capacitors in a stage. The charge pump301ais a generalized embodiment which can be controlled for multiplier, divider, inverter and follower applications. The charge pump301aincludes an input node415at which a voltage Vin is applied. For example, Vin may be a fixed power supply voltage sometimes referred to as Vdd or Vcc in a semiconductor chip. Charge from the voltage is maintained in an input capacitor Cin604which is connected to a ground node624.

A first set of switches610and a second set of switches612are controlled by regulation and control circuitry616to transfer charge from the input node415to a flying capacitor Cf606, and from Cf606to an output node406. Vout is a resulting voltage at the output node406, and can be greater than or less than Vin. The output node is coupled to an output capacitor Cout618, which is connected to a ground node622. The first set of switches610includes switches S1, S2and S3which are star-connected to one terminal (such as the top conductor) of Cf. The switches may be MOSFETs, bipolar junction transistors, relay switches, or the like. S1connects the top conductor of Cf to the input node415to receive a charge from Vin. S2connects the top conductor of Cf to the output node406to transfer its charge to the output node. S3connects the top conductor of Cf to a ground node608. Similarly, the second set of switches612includes switches S4, S5and S6which are star-connected to another terminal (such as the bottom conductor) of Cf. S4connects the bottom conductor of Cf to the input node415to receive a charge from Vin. S5connects the bottom conductor of Cf to the output node406to transfer its charge to the output node. S6connects the bottom conductor of Cf to a ground node614.

Generally, the charge pump operation includes two main phases: charging Cf from the input node, and discharging Cf into the output node. During each phase, one of the switches in each set of switches is closed, connecting Cf to either the input node, the output node, or a ground node. Further, the regulation and control circuitry616provides the switches with appropriate control signals, including frequency, phases, amplitudes, delays, etc., depending on the particular application. The regulation and control circuitry616may communicate with the output node406as well such as to detect its level. Note that the circuits shown are examples only, as various modifications can be made.

FIG. 7Bdepicts an example implementation of the charge pump301ofFIG. 3Aconfigured as a voltage multiplier. A voltage multiplier, or step-up charge pump, in general, provides Vout>Vin. The charge pump301bprovides 2×Vin>Vout>Vin, and the switches S3and S5ofFIG. 7Aare not needed. In a charging phase, the regulation and control circuitry616provides the switches with appropriate control signals so that S1is closed, e.g., conductive, and S2is open, e.g., non-conductive, so that Cf is charged via S1. Further, S4is open and S6is closed so that the bottom conductor of Cf is connected to the ground node614. In a discharging phase, S1is open and S2is closed, so that Cf is discharged, at least in part, to the output node406via S2. Further, S4is closed and S6is open.

FIG. 7Cdepicts an example implementation of the charge pump301ofFIG. 3Aconfigured as a single-stage, multi-capacitor charge pump. In the charge pump301c, multiple flying capacitors are provided in a single stage. While two capacitors are provided as an example, more than two may be used. There are many possible charge pump configurations with multiple flying capacitors. The charge pump301cis configured as a voltage multiplier in which Vout≈3×Vin. Capacitors Cf1642and Cf2644are provided. A set of switches641includes switches S1to S7. S2and S5are connected to ground nodes646and648, respectively. During a charging phase, switches S2, S3, S5, and S6are closed, while S1, S4and S7are open, so that both flying capacitors Cf1and Cf2are connected in parallel and charged to the input voltage. During a discharging phase, switches S1, S4and S7are closed, and S2, S3, S5and S6are open, so that the flying capacitors are connected in series between the input node415and the output node406. This effectively creates an output voltage of approximately three times the input voltage.

The use of multiple flying capacitors in a single stage can provide a ratio between Vout and Vin, e.g., Vout=1.5×Vin, 3×Vin, etc., or Vout=½×Vin, ⅓×Vin, etc. For greater flexibility, a multi-stage charge pump, such as described below, can be used.

FIG. 7Ddepicts an example implementation of the charge pump301ofFIG. 3Aconfigured as a multi-stage charge pump. Vin is provided at input node415so that Vout is obtained at an output node406. As an example, three stages658,666and674are provided. Two or more stages may be used in a multi-stage charge pump. Each stage can include switches and one or more flying capacitors as discussed previously, for example. At the input, a capacitor Cin654is connected at one of its conductive layers to a ground node656. At a node660which is between the first stage658and the second stage666, a capacitor Ca662is connected at one of its conductive layers to a ground node664. At a node668which is between the second stage666and the third stage674, a capacitor Cb670is connected at one of its conductive layers to a ground node672. Finally, at the output node406, an output capacitor Cout678is connected at one of its conductive layers to a ground node430. A multi-stage charge pump can provide greater flexibility in terms of providing a greater range of output voltages. Further, each stage can include one or more capacitors to provide even greater flexibility.

The multi-stage charge pump301dis operated under the control of regulation and control circuitry667which controls switching in each stage. Note that it is also possible to provide regulation and control circuitry in each stage, additionally or alternatively. Charge is transferred from the input node415of the first stage to a flying capacitor (not shown) in the first stage658, and from the flying capacitor of the first stage to the node660. Charge is then transferred from the node660of the second stage to a flying capacitor (not shown) in the second stage, and from the flying capacitor of the second stage to the node668. Charge is then transferred from the node668to a flying capacitor (not shown) in the third stage, and from the flying capacitor of the third stage to the output node406, assuming there are no further stages.

FIG. 8Adepicts an example clock signal of a charge pump. A voltage of the signal is plotted versus time. As mentioned, regulation and control circuitry is used to provide switches in a charge pump with appropriate control signals, including frequency, phases, amplitudes, delays, etc., depending on the particular configuration. The control signals are set so that the one or more capacitors in the charge pump operate at desired operating points. Generally, the capacitor undergoes repeated cycles of charging and discharging in order to transfer charge from the input node to the output node. Thus, the applied voltage across the capacitor varies during charging and discharging. Note that Vin may be substantially constant during the charging and discharging.

The waveform700represents a clock pulse in a clock period tCLK, and includes a high level and a low level. These levels can be of equal or different durations. The duration of the clock pulse relative to tCLK is the duty cycle, as mentioned.

FIG. 8Bdepicts an example plot705of a voltage of a flying capacitor in a charge pump during charging and discharging. The voltage is plotted versus time and is time-aligned with the clock signal ofFIG. 8A. The waveform700represent one clock period and includes a high level and a low level. In this example, charging of the capacitor occurs when the clock signal is high and discharging of the capacitor occurs when the clock signal is low.

FIG. 9is a block diagram of an example memory system800including the test circuit300ofFIG. 3Aand the charge pump circuit400ofFIG. 4. The memory system may include many blocks of storage elements. See, e.g.,FIG. 10. The memory system800has read/write circuits for reading and programming a page of storage elements in parallel, and may include one or more memory die802. Memory die802includes an array900of storage elements, which may include several of the blocks901ofFIG. 10, control circuitry810, and read/write circuits865. In some embodiments, the array of storage elements can be three dimensional. The memory array is addressable by word lines via a row decoder830and by bit lines via a column decoder860. The read/write circuits865include multiple sense blocks801and allow a page of storage elements to be read or programmed in parallel. Typically an off-chip controller850is included in the same memory device (e.g., a removable storage card) as the one or more memory die802. Commands and data are transferred between the host899and controller850via lines820and between the controller and the one or more memory die802via lines821.

The control circuitry810cooperates with the read/write circuits865to perform operations on the memory array. The control circuitry810includes a state machine812, an on-chip address decoder814, the test circuit300ofFIG. 3A, the charge pump circuit400ofFIG. 4(which includes the charge pump A), and additional charge pump circuits401and402which include the charge pumps B and C, respectively.

The state machine812provides chip-level control of memory operations. For example, the state machine may be configured to test charge pumps as described herein. The state machine may also be configured to perform operations on the memory cells such as read and verify processes. The on-chip address decoder814provides an address (ADDR) interface between that used by the host or a memory controller to the hardware address used by the decoders830and860. The charge pump circuits control the power and voltages supplied to the word lines and bit lines during memory operations.

In some implementations, some of the components ofFIG. 9can be combined. In various designs, one or more of the components (alone or in combination), other than memory array900, can be thought of as a managing or control circuit. For example, one or more managing or control circuits may include any one of, or a combination of, control circuitry810, state machine812, decoders814and860, charge pump circuit100, sense blocks801, read/write circuits865, controller850, host899, and so forth.

The data stored in the memory array is read out by the column decoder860and output to external I/O lines via the data I/O line and a data input/output buffer. Program data to be stored in the memory array is input to the data input/output buffer via the external I/O lines. Command data for controlling the memory device are input to the controller850. The command data informs the flash memory of what operation is requested. The input command is transferred to the control circuitry810. The state machine812can output a status of the memory device such as READY/BUSY or PASS/FAIL. When the memory device is busy, it cannot receive new read or write commands.

In another possible configuration, a non-volatile memory system can use dual row/column decoders and read/write circuits. In this case, access to the memory array by the various peripheral circuits is implemented in a symmetric fashion, on opposite sides of the array, so that the densities of access lines and circuitry on each side are reduced by half.

FIG. 10depicts a block of memory cells in an example configuration of the memory array900ofFIG. 9. The memory cells may represent a plurality of non-volatile memory cells. A charge pump provides an output voltage which is different from a supply or input voltage. In one example application, the charge pump circuit100is used to provide voltages at different levels during erase, program or read operations in a non-volatile memory device such as a NAND flash EEPROM. In such a device, a block901of memory cells includes a number of storage elements which communicate with respective word lines WL0-WL15, respective bit lines BL0-BL13, and a common source line905. An example storage element902is depicted. In the example provided, sixteen storage elements are connected in series to form a NAND string (see example NAND string915), and there are sixteen data word lines WL0through WL15. Moreover, one terminal of each NAND string is connected to a corresponding bit line via a drain select gate (connected to select gate drain line SGD), and another terminal is connected to a common source905via a source select gate (connected to select gate source line SGS). Thus, the common source905is coupled to each NAND string. The block901is typically one of many such blocks in a memory array.

In an erase operation, a high voltage such as 20 V is applied to a substrate on which the NAND string is formed to remove charge from the storage elements. During a programming operation, a voltage in the range of 15-25 V is applied to a selected word line. In one approach, step-wise increasing program pulses are applied until a storage element is verified to have reached an intended state. Moreover, pass voltages at a lower level may be applied concurrently to the unselected word lines. In read and verify operations, the select gates (SGD and SGS) are connected to a voltage in a range of 2.5 to 4.5 V and the unselected word lines are raised to a read pass voltage, Vread, (typically a voltage in the range of 4.5 to 6 V) to make the transistors operate as pass gates. The selected word line is connected to a voltage, a level of which is specified for each read and verify operation, to determine whether a Vth of the concerned storage element is above or below such level.

In practice, the output of a charge pump may be used to provide different voltages concurrently to different word lines or groups of word lines. It is also possible to use multiple charge pumps to supply different word line voltages. Similarly, the output from a charge pump can be provided to a bit line or other location as needed in the memory system.

Accordingly, in one embodiment, an apparatus comprises: a comparator comprising a first input path and a second input path, the first input path is connected to a charge pump and the second input path is connected to the first input path; a first voltage divider and a delay circuit in the second input path; a counting circuit connected to an output path of the comparator and configured to count a number of transitions in the output path of the comparator during a test period; and a control circuit connected to the counting circuit and configured to receive the count from the counting circuit and compare the count to a maximum allowable number of transitions.

In another embodiment, a method comprises: comparing a first voltage signal on a first path to a second voltage signal on a second path in a test period, the second voltage signal comprises a delayed and divided down version of the first voltage signal, the first path is connected to a charge pump and the comparing detects a number of drop-offs in a voltage output of the charge pump while the charge pump is requested to output a fixed voltage; and based on the number of drop-offs, setting a pass/fail status for the charge pump.

In another embodiment, an apparatus comprises: a memory die comprising a plurality of non-volatile memory cells; a plurality of charge pumps on the memory die; a multiplexer on the memory die, the multiplexer is connected to the plurality of charge pumps;

a comparator on the memory die, the comparator comprising a first input path and a second input path, the first input path is connected to the multiplexer and the second input path is connected to the first input path, the second input path comprising a voltage divider and a delay circuit; and a control circuit, the control circuit is configured to select a charge pump of the plurality of the charge pumps, and to control the multiplexer to pass a voltage signal from the selected charge pump to the first input path.