Test system

A test system is a test system for conducting a test including a static characteristic test of a device under test, the test system comprising: a plurality of static characteristic units used for measurement of the static characteristic test; and a replacement unit configured to be able to attach and detach specific units among the plurality of static characteristic units, the specific units selectively used according to a measurement item.

TECHNICAL FIELD

The present disclosure relates to a test system.

BACKGROUND ART

Conventionally, there is a test apparatus for inspecting a power semiconductor module such as an insulated gate bipolar transistor (IGBT). For example, a semiconductor test apparatus that determines quality of a device under test (DUT) is described in PTL 1.

CITATION LIST

Patent Literature

SUMMARY OF INVENTION

Technical Problem

Test items and test content of the DUT may vary according to requested specifications of a user. For example, there are measurement requiring supply of a voltage, measurement requiring supply of a current, and measurement requiring supply of a voltage and a current in a static characteristic test. The semiconductor test apparatus described in Patent Literature 1 cannot flexibly handle the requested specifications. More specifically, since the semiconductor test apparatus described in Patent Literature 1 needs to be separately designed to form a configuration necessary and sufficient for the test items and the test content of the DUT included in the requested specifications, the time required for providing the semiconductor test apparatus becomes long.

In the present technical field, a test system capable of flexibly handling a case in which test items requested by each user are different is desired.

Solution to Problem

A test system according to an aspect of the present disclosure is a test system for conducting a test including a static characteristic test of a device under test. The test system comprises: a plurality of static characteristic units used for measurement of the static characteristic test; and a replacement unit configured to be able to attach and detach specific units among the plurality of static characteristic units, the specific units selectively used according to a measurement item of the static characteristic test.

In the test system, the specific units selectively used according to the measurement item of the static characteristic test can be attached and detached. Therefore, for example, necessary specific units can be mounted on the replacement unit, and unnecessary specific units can be removed from the replacement unit according to a requested measurement item of the static characteristic test. As a result, even when a test item requested by each user varies, the test system does not have to be separately designed, and the test system that can handle requested specifications by simple work of just attaching and detaching the specific units can be provided.

In an embodiment, the specific units may include: a first voltage unit configured to apply a first voltage to the device under test; a second voltage unit configured to apply a second voltage smaller than the first voltage to the device under test; and a current source unit configured to supply a current to the device under test. The first voltage unit, the second voltage unit, and the current source unit may be mounted on the replacement unit according to a requested measurement item. In the static characteristic test, there are measurement requiring supply of a voltage, measurement requiring supply of a current, and measurement requiring supply of a voltage and a current. Therefore, necessary units among the first voltage unit, the second voltage unit, and the current source unit can be mounted on the replacement unit, and unnecessary specific units can be removed from the replacement unit according to the requested measurement item of the static characteristic test. As a result, even when a test item requested by each user varies, the test system does not have to be separately designed, and the test system that can handle the requested specifications by simple work of just attaching and detaching the first voltage unit, the second voltage unit, and the current source unit can be provided.

In one embodiment, the current source unit may include a plurality of current source subunits configured to supply a current of a first amount of current to the device under test. When the measurement item is a measurement item requiring the current source unit, a necessary number of current source subunits among the plurality of current source subunits may be mounted on the replacement unit according to an amount of current necessary for the measurement item. The magnitude of necessary current may vary according to the measurement item of the static characteristic test. Therefore, when the measurement item is a measurement item requiring the current source unit, the current source unit does not have to be separately designed according to the amount of current necessary for the requested measurement, and the test system that can handle the requested specifications by simple work of just mounting the necessary number of current source subunits can be provided.

In one embodiment, the test system may further comprise a plurality of dynamic characteristic units for performing a dynamic characteristic test of the device under test. In this case, the dynamic characteristic test can be performed in addition to the static characteristic test.

In one embodiment, each unit of the plurality of static characteristic units and the plurality of dynamic characteristic units may be arranged at a position closer to the device under test when a degree of influence, on a measurement accuracy of the device under test, of a signal transmitted and received by the unit is larger. In this case, because the unit that transmits and receives a signal with a large degree of influence on the measurement accuracy of the device under test is arranged close to the device under test, the length of wiring between the unit and the device under test can be short. Therefore, inductance components of the wiring for transmitting the signal with a large degree of influence on the measurement accuracy of the device under test can be suppressed, and the measurement accuracy of the device under test can be improved.

In one embodiment, the test system may further comprise a first housing, a second housing, and a third housing. The first housing, the second housing, and the third housing may be arranged in such a way that a distance from the device under test increases in order of the first housing, the second housing, and the third housing. The each unit may be housed in one of the first housing, the second housing, and the third housing according to the degree of influence. For example, when all units are housed in a housing arranged near the device under test, the housing is enlarged, and the arrangement in using the test system is limited. On the other hand, the units can be distributed and housed in the first housing, the second housing, and the third housing according to the degrees of influence, on the measurement accuracy of the device under test, of the signals transmitted and received by the units to thereby downsize the first housing arranged near the device under test while suppressing the reduction in the measurement accuracy of the device under test. As a result, a degree of freedom of arrangement in using the test system can be improved.

In one embodiment, the plurality of static characteristic units may be housed in the second housing. Because the static characteristic test is less likely to be affected by the inductance components compared to the dynamic characteristic test, the static characteristic units may be arranged at a position somewhat away from the device under test. In this way, the number of units housed in the first housing can be decreased. As a result, the first housing can be downsized without reducing the measurement accuracy.

In one embodiment, the plurality of dynamic characteristic units may comprise: a dynamic characteristic measurement circuit for performing the dynamic characteristic test; a dynamic characteristic controller configured to control the dynamic characteristic measurement circuit and the device under test according to a preset measurement pattern of the dynamic characteristic test; and an interceptor configured to control the dynamic characteristic measurement circuit and the device under test when an abnormal state is detected in the dynamic characteristic test. The interceptor may be arranged at a position closer to the device under test than the dynamic characteristic controller. In this case, the wiring between the interceptor and the device under test can be short, and the control in the abnormal state can be performed faster than the control of a normal state.

In one embodiment, the test system may further comprise an interface substrate for absorbing a physical difference according to a type of the device under test. The interface substrate may comprise probes electrically connected to electrodes of the device under test, and the number and arrangement of the probes may be set according to the type of the device under test. According to the configuration, because the interface substrate according to the type of the device under test to be tested is used, it is unnecessary to design the test system for each of different types of device under test. That is, the part of the test system except the interface substrate can be shared regardless of the type of the device under test.

In one embodiment, the device under test may be a power semiconductor module. In this case, even when a test item requested by each user varies, the test system of a power semiconductor module does not have to be separately designed, and the test system of the power semiconductor module that can handle requested specifications by simple work of just attaching and detaching the specific units can be provided.

Advantageous Effects of Invention

According to each aspect and each embodiment of the present disclosure, a power semiconductor test system capable of flexibly handling a case in which test items requested by each user are different can be provided.

DESCRIPTION OF EMBODIMENTS

Hereinafter, embodiments of the present disclosure will be described with reference to the drawings. Note that in the description of the drawings, the same reference signs are provided to the same or equivalent elements, and overlapping description will be omitted.

FIG. 1is an external view schematically showing a power semiconductor test system according to an embodiment.FIG. 2is a configuration diagram schematically showing the power semiconductor test system ofFIG. 1. A power semiconductor test system1shown inFIGS. 1 and 2is a test system for conducting various tests including a static characteristic (DC: Direct Current) test and a dynamic characteristic (AC: Alternating Current) test of a DUT2. The DUT2is a device under test and is, for example, a power semiconductor module including a set of two semiconductor elements electrically connected in series. The DUT2is, for example, a power semiconductor module of a 2 in 1 type, a 4 in 1 type, a 6 in 1 type, an 8 in 1 type, or the like. An example of the semiconductor element included in the DUT2includes an IGBT. The DUT2includes a P terminal, an N terminal, an O terminal, and a control terminal (electrode).

In the static characteristic test, characteristics, such as a collector breaking current Ices, a gate-emitter threshold voltage Vge (th), a gate-emitter leakage current Iges, and a collector-emitter saturation voltage Vce (sat), can be measured. In the dynamic characteristic test, switching measurement, short circuit capability measurement (SC measurement), and the like are performed. Specifically, characteristics, such as an entire gate charge Qg, a turn-on delay time td (on), a turn-on rise time tr, a turn-off delay time td (off), a turn-off fall time tf, a reverse recovery time trr, a reverse recovery charge Qrr, and an emitter-collector voltage Vec, can be measured. These measurement items are appropriately selected according to requested specifications of a user.

The power semiconductor test system1includes a plurality of static characteristic units used for the measurement in the static characteristic test and a plurality of dynamic characteristic units used for the measurement in the dynamic characteristic test. The plurality of static characteristic units include a static characteristic measurement circuit21, a gate servo22, a large-current measurement circuit23, a trigger matrix25, high voltage units71, low voltage units72, and a large-current source unit73described later. The plurality of dynamic characteristic units include a dynamic characteristic measurement circuit14, a capacitor bank15, a driving driver16, current sensors17, voltage sensors18, an interceptor26, a digitizer27, a charge power supply32, and a dynamic characteristic controller33described later.

Each unit of the plurality of static characteristic units and the plurality of dynamic characteristic units is arranged according to a degree of influence, on measurement accuracy of the DUT2, of a signal transmitted and received by the unit. Each unit is, for example, arranged at a position farther from the DUT2when the degree of influence, on the measurement accuracy of the DUT2, of the signal transmitted and received by the unit is smaller and is arranged at a position closer to the DUT2when the degree of influence, on the measurement accuracy of the DUT2, of the signal transmitted and received by the unit is larger. The power semiconductor test system1includes a first apparatus10, a second apparatus20, and a third apparatus30. In the power semiconductor test system1, the units shown inFIG. 2are distributed to the first apparatus10, the second apparatus20, and the third apparatus30according to a management level. The first apparatus10, the second apparatus20, and the third apparatus30are arranged in such a way that the distance from the DUT2increases in order of the first apparatus10, the second apparatus20, and the third apparatus30. Units of a management level Lv1are arranged in the first apparatus10. Units of a management level Lv2are arranged in the second apparatus20. Units of a management level Lv3are arranged in the third apparatus30.

The management level is a standard indicating the accuracy required for the signal transmitted and received by each unit and is set according to the degree of influence of the signal on the measurement accuracy of the DUT2. The management level Lv1is an inductance management level. Specifically, high speed and high accuracy are required for the signals transmitted and received by the units of the management level Lv1. The management level Lv2is a noise management level. Specifically, the accuracy required for the signals transmitted and received by the units of the management level Lv2is lower than the accuracy required for the signals transmitted and received by the units of the management level Lv1and is higher than the accuracy required for the signals transmitted and received by the units of the management level Lv3. An example of the signals transmitted and received by the units of the management level Lv2includes a small analog signal. The management level Lv3is a normal management level. Specifically, the accuracy required for the signals transmitted and received by the units of the management level Lv3is lower than the accuracy required for the signals transmitted and received by the units of the management level Lv1and the management level Lv2, and accuracy in a degree not causing a communication error is required. Examples of the signals transmitted and received by the units of the management level Lv3include a digital signal and a signal not requiring accuracy. Therefore, the required accuracy increases in order of the management level Lv3, the management level Lv2, and the management level Lv1.

The first apparatus10will be described in detail with reference toFIGS. 3 to 5in addition toFIGS. 1 and 2.FIG. 3is a diagram showing an example of configuration of the first apparatus10.FIG. 4is a diagram for describing functions of a DIB included in the first apparatus10, wherein (a) ofFIG. 4is a diagram for describing a function of the DIB when the DUT2is a power semiconductor module of the 2 in 1 type, and (b) ofFIG. 4is a diagram for describing a function of the DIB when the DUT2is a power semiconductor module of the 6 in 1 type.FIG. 5is an example of a circuit diagram of a dynamic characteristic measurement circuit and a capacitor bank included in the first apparatus10. As shown inFIGS. 1 to 3, the first apparatus10includes a DIB (Device Interface board)11(interface substrate) and a test head12.

The DIB11is a unit for absorbing a physical difference according to the type of the DUT2. The DIB11provides an interface between the DUT2and the test head12. The DM11is prepared for each type of the DUT2. The DIB11is disposed on the test head12through support members13. The DIB11includes a substrate61, probes62, and contact portions63. The number and arrangement of the probes62are set according to the type of the DUT2. In this example, the probes62are electrically connected to the P terminal, the N terminal, the O terminal, and the control terminal of the DUT2. The contact portions63are electrically connected to terminals of the test head12. The contact portions63are the same regardless of the type of the DUT2. Note that although the power semiconductor module is described as the DUT2here, the power semiconductor test system1can be a test system for a semiconductor element when the DIB11and the dynamic characteristic measurement circuit14ofFIG. 2correspond to a single semiconductor element. In other words, the power semiconductor test system1can also be applied to a test system configured to conduct tests (static characteristic and dynamic characteristic tests) of the semiconductor element.

InFIG. 3and (a) ofFIG. 4, the DIB11when the DUT2is a power semiconductor module of the 2 in 1 type is illustrated. In this case, the DUT2includes transistors Qdp and Qdn and diodes Ddp and Ddn. The transistors Qdp and Qdn are IGBTs. An emitter of the transistor Qdp and a collector of the transistor Qdn are electrically connected to each other. Cathodes of the diodes Ddp and Ddn are electrically connected to collectors of the transistors Qdp and Qdn, respectively, and anodes of the diodes Ddp and Ddn are electrically connected to emitters of the transistors Qdp and Qdn, respectively. That is, the transistors Qdp and Qdn are electrically connected in series in the same direction, the diode Ddp is a free wheel diode electrically connected in parallel with the transistor Qdp, and the diode Ddn is a free wheel diode electrically connected in parallel with the transistor Qdn. The DUT2includes the P terminal, the O terminal, and the N terminal. The P terminal is electrically connected to the collector of the transistor Qdp and the cathode of the diode Ddp, the N terminal is electrically connected to the emitter of the transistor Qdn and the anode of the diode Ddn, and the O terminal is electrically connected to the emitter of the transistor Qdp, the collector of the transistor Qdn, the anode of the diode Ddp, and the cathode of the diode Ddn. That is, the O terminal is electrically connected to a connection portion Cd (seeFIG. 5) for electrically connecting the transistors Qdp and Qdn.

The probes62include a probe62p, a probe62n, a probe62o, and probes62g. The probes62ginclude a probe62gpand a probe62gn. A leading end of the probe62pis in contact with the P terminal of the DUT2such that the probe62pis electrically connected to the P terminal of the DUT2. A leading end of the probe62nis in contact with the N terminal of the DUT2such that the probe62nis electrically connected to the N terminal of the DUT2. A leading end of the probe62ois in contact with the O terminal of the DUT2such that the probe62ois electrically connected to the O terminal of the DUT2. A leading end of the probe62gpis in contact with a control terminal for the transistor Qdp of the DUT2such that the probe62gpis electrically connected to the control terminal for the transistor Qdp of the DUT2. A leading end of the probe62gnis in contact with a control terminal for the transistor Qdn of the DUT2such that the probe62gnis electrically connected to a control terminal for the transistor Qdn of the DUT2.

The contact portions63include a contact portion63p, a contact portion63n, a contact portion63o, and contact portions63g. The contact portions63ginclude a contact portion63gpand a contact portion63gn. The contact portion63pis in contact with a P output terminal Tp of the test head12. The contact portion63nis in contact with an N output terminal Tn of the test head12. The contact portion63ois in contact with an O output terminal To of the test head12. The contact portions63gcome into contact with control output terminals Tg of the test head12.

The substrate61is a plate-like member and includes a main surface61aand a back surface61bthat is a surface on the opposite side of the main surface61a. The DUT2is disposed on the main surface61a. On the main surface61a, the probes62p,62n,62o,62gp, and62gnare provided to protrude in a normal axis direction of the main surface61a. The probes62p,62n,62o,62gp, and62gnare arranged at positions coming into contact with the P terminal, the N terminal, the O terminal, the control terminal for the transistor Qdp, and the control terminal for the transistor Qdn of the DUT2, respectively, when the DUT2is disposed on the main surface61a. The contact portions63p,63n,63o, and63gare provided on the back surface61b. The contact portions63p,63n,63o, and63gare arranged at positions coming into contact with the P output terminal Tp, the N output terminal Tn, the O output terminal To, and the control output terminals of the test head12, respectively, when the DIB11is disposed at a predetermined position on the test head12.

The substrate61includes a selection circuit64and wiring for electrically connecting terminals of semiconductor elements included in the DUT2to the output terminals of the test head12. Specifically, the substrate61includes wiring for electrically connecting the probe62pand the contact portion63pand wiring for electrically connecting the probe62nand the contact portion63n. The selection circuit64is a circuit for selecting a set of semiconductor elements to be tested among the plurality of sets of semiconductor elements included in the DUT2. Specifically, the selection circuit64selects O terminals and control terminals of the set of the semiconductor elements to be tested in the DUT2. The selection circuit64includes, for example, a switch such as a relay.

As shown in (a) ofFIG. 4, since a set of semiconductor elements does not have to be selected when the DUT2is a power semiconductor module of the 2 in 1 type, the selection circuit64electrically connects the probe62oand the contact portion63o, electrically connects the probe62gpand the contact portion63gp, and electrically connects the probe62gnand the contact portion63gn.

In (b) ofFIG. 4, the DIB11when the DUT2is a power semiconductor module of the 6 in 1 type is illustrated. In this case, the DUT2includes sets of the transistors Qdp and Qdn and the diodes Ddp and Ddn of the 2 in 1 type, in parallel for three phases (U, V, and W phases). More specifically, the DUT2includes transistors Qdpu and Qdnu and diodes Ddpu and Ddnu for the U phase, includes transistors Qdpv and Qdnv and diodes Ddpv and Ddnv for the V phase, and includes transistors Qdpw and Qdnw and diodes Ddpw and Ddnw for the W phase. The DUT2includes a P terminal, a U terminal, a V terminal, a W terminal, and an N terminal. The P terminal is electrically connected to collectors of the transistors Qdpu, Qdpv, and Qdpw, and the N terminal is electrically connected to emitters of the transistors Qdnu, Qdnv, and Qdnw. The U terminal is electrically connected to an emitter of the transistor Qdpu and a collector of the transistor Qdnu, the V terminal is electrically connected to an emitter of the transistor Qdpv and a collector of the transistor Qdnv, and the W terminal is electrically connected to an emitter of the transistor Qdpw and a collector of the transistor Qdnw.

In the DIB11for the power semiconductor module of the 6 in 1 type, the arrangement and the number of probes62are different, as compared to the DIB11for the power semiconductor module of the 2 in 1 type. Specifically, it is different that the probes62oinclude a probe62ou, a probe62ov, and a probe62owand that the probes62ginclude a probe62gpu, a probe62gnu, a probe62gpv, a probe62gnv, a probe62gpw, and a probe62gnw.

A leading end of the probe62ouis in contact with the U terminal of the DUT2such that the probe62ouis electrically connected to the U terminal of the DUT2. A leading end of the probe62ovis in contact with the V terminal of the DUT2such that the probe62ovis electrically connected to the V terminal of the DUT2. A leading end of the probe62owis in contact with the W terminal of the DUT2such that the probe62owis electrically connected to the W terminal of the DUT2. A leading end of the probe62gpuis in contact with a control terminal for the transistor Qdpu of the DUT2such that the probe62gpuis electrically connected to the control terminal for the transistor Qdpu of the DUT2. A leading end of the probe62gnuis in contact with a control terminal for the transistor Qdnu of the DUT2such that the probe62gnuis electrically connected to the control terminal for the transistor Qdnu of the DUT2. A leading end of the probe62gpvis in contact with a control terminal for the transistor Qdpv of the DUT2such that the probe62gpvis electrically connected to the control terminal for the transistor Qdpv of the DUT2. A leading end of the probe62gnvis in contact with a control terminal for the transistor Qdnv of the DUT2such that the probe62gnvis electrically connected to the control terminal for the transistor Qdnv of the DUT2. A leading end of the probe62gpwis in contact with a control terminal for the transistor Qdpw of the DUT2such that the probe62gpwis electrically connected to the control terminal for the transistor Qdpw of the DUT2. A leading end of the probe62gnwis in contact with a control terminal for the transistor Qdnw of the DUT2such that the probe62gnwis electrically connected to the control terminal for the transistor Qdnw of the DUT2.

The probes62ou,62ov,62ow,62gpu,62gnu,62gpv,62gnv,62gpw, and62gnware arranged at positions coming into contact with the U terminal, the V terminal, the W terminal, the control terminal for the transistor Qdpu, the control terminal for the transistor Qdnu, the control terminal for the transistor Qdpv, the control terminal for the transistor Qdnv, the control terminal for the transistor Qdpw, and the control terminal for the transistor Qdnw of the DUT2, respectively, when the DUT2is disposed on the main surface61a.

When the DUT2is a power semiconductor module of the 6 in 1 type, one set of semiconductor elements needs to be selected from the three sets of semiconductor elements. Therefore, the selection circuit64electrically connects one of the probes62ou,62ov, and62owand the contact portion63o, electrically connects one of the probes62gpu,62gpv, and62gpwand the contact portion63gp, and electrically connects one of the probes62gnu,62gnv, and62gnwand the contact portion63gn. Specifically, when the selection circuit64selects the U phase, the selection circuit64electrically connects the probe62ouand the contact portion63o, electrically connects the probe62gpuand the contact portion63gp, and electrically connects the probe62gnuand the contact portion63gn. When the selection circuit64selects the V phase, the selection circuit64electrically connects the probe62ovand the contact portion63o, electrically connects the probe62gpvand the contact portion63gp, and electrically connects the probe62gnvand the contact portion63gn, When the selection circuit64selects the W phase, the selection circuit64electrically connects the probe62owand the contact portion63o, electrically connects the probe62gpwand the contact portion63gp, and electrically connects the probe62gnwand the contact portion63gn.

As described above, changing the number and the arrangement of the probes62according to the type of the DUT2in the DIB11makes it unnecessary to change parts except the DIB11of the power semiconductor test system1. That is, since the DIB11absorbs the difference in the physical shape of the DUT2depending on the type of the DUT2, the test head12, the second apparatus20, and the third apparatus30basically have common configurations regardless of the type of the DUT2. In the following description, the power semiconductor module of the 2 in 1 type will be used as the DUT2.

Although not illustrated in the description above, the probes62include a probe62p, a probe62n, and a probe62ofor the dynamic characteristic test and a probe62p, a probe62n, and a probe62ofor the static characteristic test, and the probes come into contact with the terminals of the DUT2, respectively. Furthermore, the DIB11includes a separation circuit not shown. The separation circuit is a circuit for electrically separating the probe62p, the probe62n, and the probe62ofor the static characteristic test and the static characteristic measurement circuit21. When the measurement of the static characteristic test is to be performed, the separation circuit electrically connects the probe62p, the probe62n, and the probe62ofor the static characteristic test and the static characteristic measurement circuit21, and when the measurement of the dynamic characteristic test is to be performed, the separation circuit electrically separates the probe62p, the probe62n, and the probe62ofor the static characteristic test and the static characteristic measurement circuit21. Note that the probes62gare commonly used in the dynamic characteristic test and the static characteristic test.

The test head12includes the dynamic characteristic measurement circuit14, the capacitor bank15, the driving driver16, the current sensors17, the voltage sensors18, and a housing19(first housing). In the test head12, the dynamic characteristic measurement circuit14, the capacitor bank15, the driving driver16, the current sensors17, and the voltage sensors18are housed in the housing19. The housing19is box-shaped and the P output terminal Tp, the N output terminal Tn, the O output terminal To, and the control output terminal Tg are provided so as to protrude upward from an upper surface of the housing19.

The dynamic characteristic measurement circuit14is a circuit for performing the dynamic characteristic test of the DUT2. The capacitor bank15is a power supply configured to supply a current for the dynamic characteristic test to the dynamic characteristic measurement circuit14.FIG. 5shows the dynamic characteristic measurement circuit14and the capacitor bank.15when the DUT2is a power semiconductor module of the 2 in 1 type. As shown inFIG. 5, the dynamic characteristic measurement circuit14includes a selection circuit41, an overcurrent preventing circuit42, a high-speed breaking circuit43, a selection circuit44, and a reactor L. The capacitor bank15includes a capacitor51and a main switch portion52.

A film capacitor with excellent frequency characteristics is used as the capacitor51, for example. When stored energy (charge) decreases, the capacitor51is connected to the charge power supply32and charged by the charge power supply32.

The main switch portion52is a circuit configured to switch supply and block of current from the capacitor51to the DUT2(the transistor Qdp or the transistor Qdn). The main switch portion52includes a transistor Qp and a diode Dp. The transistor Qp is an IGBT. A cathode of the diode Dp is electrically connected to a collector of the transistor Qp, and an anode of the diode Dp is electrically connected to an emitter of the transistor Qp. Therefore, the diode Dp is a free wheel diode electrically connected in parallel with the transistor Qp. The collector of the transistor Qp is electrically connected to a + terminal (positive terminal) of the capacitor51, and the emitter of the transistor Qp is electrically connected to a collector of a transistor Qhp, a cathode of a diode Dhp, one end of a switch SWp, and the P terminal of the DUT2described later.

The selection circuit41is a circuit for selecting one of the transistors Qdp and Qdn included in the DUT2as a target of switching measurement. The selection circuit41includes transistors Qhp and Qhn and diodes Dhp and Dhn. The transistors Qhp and Qhn are IGBTs. Cathodes of the diodes Dhp and Dhn are electrically connected to collectors of the transistors Qhp and Qhn, respectively, and anodes of the diodes Dhp and Dhn are electrically connected to emitters of the transistors Qhp and Qhn, respectively. Therefore, the diode Dhp is a free wheel diode electrically connected in parallel with the transistor Qhp, and the diode Dhn is a free wheel diode electrically connected in parallel with the transistor Qhn. The emitter of the transistor Qhp and the collector of the transistor Qhn are electrically connected to each other and are electrically connected to a collector of a transistor Qcf and a cathode of a diode Dcf described later. That is, the transistors Qhp and Qhn are electrically connected in series in the same direction, and a connection portion Cs electrically connecting the transistors Qhp and Qhn is electrically connected to the O terminal of the DUT2through the high-speed breaking circuit43and the reactor L. The collector of the transistor Qhp is electrically connected to the emitter of the transistor Qp, the anode of the diode Dp, the one end of the switch SWp, and the P terminal of the DUT2. The emitter of the transistor Qhn is electrically connected to a − terminal (negative terminal) of the capacitor51, another end of the switch SWn, and the N terminal of the DUT2.

The overcurrent preventing circuit42is a circuit for consuming energy stored in the reactor L. The overcurrent preventing circuit42is provided electrically in parallel with the reactor L. The overcurrent preventing circuit42includes transistors Qif and Qir and diodes Dif and Dir. The transistors Qif and Qir are IGBTs. Cathodes of the diodes Dif and Dir are electrically connected to collectors of the transistors Qif and Qir, respectively, and anodes of the diodes Dif and Dir are electrically connected to emitters of the transistors Qif and Qir, respectively. Therefore, the diode Dif is a free wheel diode electrically connected in parallel with the transistor Qif, and the diode Dir is a free wheel diode electrically connected in parallel with the transistor Qir. The emitter of the transistor Qif and the emitter of the transistor Qir are electrically connected to each other. That is, the transistors Qif and Qir are electrically connected in series in opposite directions. The collector of the transistor Qif is electrically connected to a collector of a transistor Qcr, a cathode of a diode Dcr, and one end of the reactor L described later. The collector of the transistor Qir is electrically connected to another end of the reactor L, the other end of the switch SWp, one end of a switch SWn, and the O terminal of the DUT2.

The high-speed breaking circuit43is a circuit for causing the overcurrent preventing circuit42to consume the energy stored in the reactor L at a high speed. The high-speed breaking circuit43is provided electrically in series with the reactor L. The high-speed breaking circuit43includes the transistors Qcf and Qcr and the diodes Dcf and Der. The transistors Qcf and Qcr are IGBTs. The cathodes of the diodes Dcf and Dcr are electrically connected to the collectors of the transistors Qcf and Qcr, respectively, and anodes of the diodes Dcf and Dcr are electrically connected to emitters of the transistors Qcf and Qcr, respectively. Therefore, the diode Dcf is a free wheel diode electrically connected in parallel with the transistor Qcf, and the diode Dcr is a free wheel diode electrically connected in parallel with the transistor Qcr. The emitter of the transistor Qcf and the emitter of the transistor Qcr are electrically connected to each other. That is, the transistors Qcf and Qcr are electrically connected in series in opposite directions. The collector of the transistor Qcf is electrically connected to the emitter of the transistor Qhp, the collector of the transistor Qhn, the anode of the diode Dhp, and the cathode of the diode Dhn. The collector of the transistor Qcr is electrically connected to the collector of the transistor Qif, the cathode of the diode Dif, and the one end of the reactor L.

The selection circuit44is a circuit for selecting one of the transistors Qdp and Qdn included in the DUT2as a target of short circuit capability measurement. The selection circuit44includes the switches SWp and SWn. The switches SWp and SWn are relays. The one end of the switch SWp is electrically connected to the emitter of the transistor Qp, the anode of the diode Dp, the collector of the transistor Qhp, the cathode of the diode Dhp, and the P terminal of the DUT2. The other end of the switch SWp and the one end of the switch SWn are electrically connected to each other and are electrically connected to the other end of the reactor L, the collector of the transistor Qir, the cathode of the diode Dir, and the O terminal of the DUT2. The other end of the switch SWn is electrically connected to the − terminal of the capacitor51, the emitter of the transistor Qhn, the anode of the diode Dhn, and the N terminal of the DUT2.

The reactor L is a load of the dynamic characteristic test. That is, the reactor L is a load of the transistors Qdp and Qdn. The one end of the reactor L is electrically connected to the collector of the transistor Qcr and the cathode of the diode Dcr, and the other end of the reactor L is electrically connected to the O terminal of the DUT2.

The driving driver16switches an on-state (conductive state) and an off-state (cutoff state) of the transistors Qp, Qhp, Qhn, Qif, Qir, Qcf, Qcr, Qdp, and Qdn and the switches SWp and SWn. The driving driver16outputs a gate signal to each of the transistors Qp, Qhp, Qhn, Qif, Qir, Qcf, Qcr, Qdp, and Qdn according to an instruction from the interceptor26or the dynamic characteristic controller33to thereby switch the on-state and the off-state of each transistor. The driving driver16outputs a relay signal to each of the switches SWp and SWn according to an instruction from the interceptor26or the dynamic characteristic controller33to thereby switch the on-state and the off-state of each switch. Note that the on-state of the transistor denotes that the collector and the emitter are in an electrically conductive state, and the off-state of the transistor denotes that the collector and the emitter are in an electrically cutoff state. When the transistor is an IGBT, the on-state and the off-state are switched by a gate-emitter voltage.

The current sensors17are sensors configured to detect current values of currents flowing in the P terminal and the N terminal of the DUT2. The current sensors17are provided on the P output terminal Tp and the N output terminal Tn. The current sensors17output the detected current values to the interceptor26and the digitizer27. The voltage sensors18are sensors configured to detect voltage values of voltages of the P terminal and the N terminal of the DUT2. The voltage sensors18are provided on the P output terminal Tp and the N output terminal Tn. The voltage sensors18output the detected voltage values to the interceptor26and the digitizer27. The current sensors17and the voltage sensors18communicate with the interceptors26and the digitizers27through analog voltages.

Next, the second apparatus20will be described in detail with reference toFIGS. 1 and 2. The second apparatus20includes the static characteristic measurement circuit21, the gate servo22, the large-current measurement circuit23, a replacement unit24, the trigger matrix25, the interceptor26, the digitizer27, and a housing28(second housing). In the second apparatus20, the static characteristic measurement circuit21, the gate servo22, the large-current measurement circuit23, the replacement unit24, the trigger matrix25, the interceptor26, and the digitizer27are housed in the housing28. The housing28is box-shaped.

The static characteristic measurement circuit21is a circuit for performing the static characteristic test of the DUT2. The static characteristic measurement circuit21includes, for example, a relay matrix circuit and a circuit including passive elements, such as a resistance element, a capacitor, and a reactor. The relay matrix circuit is a circuit for determining how to connect each unit of the high voltage units71and the low voltage units72and each terminal of the DUT2. The circuit including the passive elements is a circuit for clamping a gate and stabilizing static characteristic measurement.

The gate servo22is a unit used for measurement of a gate-emitter threshold voltage Vge (th) in the static characteristic test. The gate servo22includes, for example, an operational amplifier and a plurality of resistance elements. The gate servo22adjusts a gate voltage of the element to be measured of the transistors Qdp and Qdn of the DUT2to thereby perform control in such a way that a collector current of the element to be measured becomes a predetermined current. The gate servo22is mounted as a substrate that can be attached to and detached from the static characteristic measurement circuit21.

The large-current measurement circuit23is a circuit for performing measurement that requires a large current (for example, about 800 A) in the static characteristic test. The large-current measurement circuit23is used for measurement of, for example, a collector-emitter saturation voltage Vce (sat) of the static characteristic test and an emitter-collector voltage Vec of the dynamic characteristic test. The large-current measurement circuit23has, for example, a circuit configuration similar to the static characteristic measurement circuit21and includes a relay matrix circuit and a circuit including passive elements, such as a resistance element, a capacitor, and a reactor. In the large-current measurement circuit23, the relay matrix circuit is a circuit for determining how to connect the large-current source unit73and each terminal of the DUT2. The large-current measurement circuit23includes, for example, a plurality of switches, and the large-current measurement circuit23switches the on-state and the off-state of the switches to thereby select one of the transistors Qdn and Qdp of the DUT2as a measurement target.

The replacement unit24is configured to be able to attach and detach specific units selectively used according to a measurement item among a plurality of static characteristic units. Examples of the specific units that can be attached and detached include the high voltage units71(first voltage units), the low voltage units72(second voltage units), and the large-current source unit73(current source unit). That is, the high voltage units71, the low voltage units72, and the large-current source unit73are mounted on the replacement unit24according to a requested measurement item. The high voltage units71apply a first voltage to the measurement target of the DUT2. The first voltage is, for example, a high voltage of about 1500V. The low voltage units72apply a second voltage smaller than the first voltage to the measurement target of the DUT2. The second voltage is, for example, a low voltage of about 150V. Note that the high voltage units71and the low voltage units72supply a current of about 0.1 A to the measurement target of the DUT2. The large-current source unit73supplies a current to the measurement target of the DUT2. The large-current source unit73supplies, for example, a current of about 500 A and a voltage of about 10V. A specific configuration of the replacement unit24will be described later.

The trigger matrix25is configured to receive a trigger emitted by a unit and control an output destination of the received trigger. The trigger matrix25is connected to and capable of communicating with the dynamic characteristic measurement circuit14, the static characteristic measurement circuit21, the large-current measurement circuit23, the charge power supply32, the dynamic characteristic controller33, the high voltage units71, the low voltage units72, and the large-current source unit73through, for example, optical fibers. The trigger matrix25receives a trigger from these units and outputs the trigger to units of the output destination. The trigger matrix25determines the units of the output destination according to a matrix set in advance by an integrated controller31and outputs the trigger to the units of the output destination. The trigger matrix25distributes a synchronization pulse for synchronizing the units to all units connected to and capable of communicating with the trigger matrix25.

When the interceptor26detects an abnormal state in the dynamic characteristic test, the interceptor26controls the dynamic characteristic measurement circuit14, the capacitor bank15, and the DUT2. The interceptor26instructs the driving driver16to switch the on-state and the off-state of the transistors included in the dynamic characteristic measurement circuit14, the capacitor bank15, and the DUT2. The interceptor26determines, for example, whether the current value detected by the current sensor17exceeds an overcurrent threshold, and the interceptor26detects an overcurrent (abnormal state) when the current value detected by the current sensor17exceeds the overcurrent threshold. The overcurrent threshold is a preset value for detecting the overcurrent. When the interceptor26detects the overcurrent, the interceptor26instructs the driving driver16to execute an overcurrent prevention process. The interceptor26operates the overcurrent preventing circuit42in the overcurrent prevention process. The overcurrent prevention process will be described later.

The digitizer27is used in the dynamic characteristic test, and the digitizer27is configured to sample the current value detected by the current sensor17and the voltage value detected by the voltage sensor18to convert the current value and the voltage value to digital values. The digitizer27outputs the current value and the voltage value converted to the digital values to the integrated controller31. The digitizer27and the integrated controller31are connected by, for example, an optical fiber, and the digitizer27and the integrated controller31transmit and receive data through optical communication.

Next, the third apparatus30will be described in detail with reference toFIGS. 1 and 2. The third apparatus30includes the integrated controller31, the charge power supply32, the dynamic characteristic controller33, and housings34(third housings). The housings34include a housing34aand a housing34b. In the third apparatus30, the charge power supply32is housed in the housing34a, and the integrated controller31and the dynamic characteristic controller33are housed in the housing34b. The housing34aand the housing34bare box-shaped. The housing34aand the housing34bmay be integrated.

The integrated controller31is a control apparatus for controlling the entire power semiconductor test system1. The integrated controller31outputs, to each unit, a command or the like for controlling each unit. The integrated controller31is realized by, for example, installing a control program (software) of the power semiconductor test system1on a general-purpose personal computer. The integrated controller31is connected to and capable of communicating with each of the dynamic characteristic measurement circuit14, the static characteristic measurement circuit21, the trigger matrix25, the charge power supply32, the dynamic characteristic controller33, the high voltage units71, the low voltage units72, and the large-current source unit73through, for example, a LAN (Local Area Network). Note that inFIG. 2, illustration of the connection between the integrated controller31and the dynamic characteristic measurement circuit14and between the integrated controller31and the static characteristic measurement circuit21is omitted. In this case, a unit definition file is set in the integrated controller31according to the unit connected to the LAN. The unit definition file is a file defining an IP (Internet Protocol) address, a function, a command, and the like of the unit. In this way, the integrated controller31recognizes the unit connected to the LAN.

The charge power supply32is a power supply for charging and discharging the capacitor51of the capacitor bank15. The charge power supply32is, for example, a high voltage power supply. The charge power supply32charges the capacitor51to conduct the dynamic characteristic test. The charge power supply32discharges the capacitor51after the end of the dynamic characteristic test.

The dynamic characteristic controller33is configured to control the dynamic characteristic measurement circuit14, the capacitor bank15, and the DUT2according to a preset measurement pattern of the dynamic characteristic test. The dynamic characteristic controller33instructs the driving driver16to switch the on-state and the off-state of the transistors Qp, Qhp, Qhn, Qif, Qir, Qcf, Qcr, Qdp, and Qdn and the switches SWp and SWn according to the preset measurement pattern of the dynamic characteristic test. Note that the dynamic characteristic controller33is connected to the driving driver16by an optical signal through the interceptor26.

Next, an example of the overcurrent prevention process by the interceptor26will be described with reference toFIG. 5. For example, the interceptor26instructs the driving driver16to operate the overcurrent preventing circuit42in response to detection of an overcurrent in the N output terminal Tn caused by the fact that the transistor Qdn of the DUT2does not enter the off-state in the switching measurement of the transistor Qdn (will be called “N-side switching measurement” in some cases). More specifically, the interceptor26instructs the driving driver16to put the transistors Qcf, Qcr, Qir, and Qdn into the on-state and put the other transistors into the off-state. In this case, a current path is formed which goes round through the transistor Qcf, the transistor Qcr, the reactor L, the transistor Qdn, and the diode Dhn in this order, and a current path is formed which goes round through the reactor L, the transistor Qir, and the diode Dif in this order. In this way, the energy stored in the reactor L when the overcurrent occurs flows in each current path. In each current path, the energy is consumed by the resistance components and the like, such as transistors and diodes, and the amount of current becomes 0. In this way, the overcurrent preventing circuit42consumes the energy stored in the reactor L when the overcurrent occurs, and further flow of overcurrent in the DUT2is prevented in the N-side switching measurement.

Similarly, the interceptor26instructs the driving driver16to operate the overcurrent preventing circuit42in response to detection of an overcurrent in the P output terminal Tp caused by the fact that the transistor Qdp of the DUT2does not enter the off-state in the switching measurement of the transistor Qdp (will be called “P-side switching measurement” in some cases). More specifically, the interceptor26instructs the driving driver16to put the transistors Qcf, Qcr, Qif, and Qdp into the on-state and put the other transistors into the off-state. In this case, a current path is formed which goes round through the reactor L, the transistor Qcr, the transistor Qcf, the diode Dhp, and the transistor Qdp in this order, and a current path is formed which goes round through the reactor L, the transistor Qif, and the diode Dir in this order. In this way, the energy stored in the reactor L when the overcurrent occurs flows in each current path. In each current path, the energy is consumed by the resistance components and the like, such as transistors and diodes, and the amount of current becomes 0. In this way, the overcurrent preventing circuit42consumes the energy stored in the reactor L when the overcurrent occurs, and further flow of overcurrent in the DUT2is prevented in the P-side switching measurement.

When faster breaking of the overcurrent is required in the N-side switching measurement, the interceptor26may also instruct the driving driver16to operate the high-speed breaking circuit43in addition to the overcurrent preventing circuit42in response to the detection of the overcurrent in the N output terminal Tn. More specifically, the interceptor26may instruct the driving driver16to put the transistors Qir and Qdn into the on-state and put the other transistors into the off-state. In this case, only the current path is formed which goes round through the reactor L, the transistor Qir, and the diode Dif in this order. In this way, the energy stored in the reactor L when the overcurrent occurs flows in the current path. In the current path, the energy is consumed by the resistance components and the like, such as transistors and diodes, and the amount of current becomes 0. In this way, the overcurrent preventing circuit42consumes the energy stored in the reactor L when the overcurrent occurs, and further flow of overcurrent in the DUT2is prevented in the N-side switching measurement.

Similarly, when faster breaking of the overcurrent is required in the P-side switching measurement, the interceptor26may instruct the driving driver16to operate the high-speed breaking circuit43in addition to the overcurrent preventing circuit42in response to the detection of the overcurrent in the P output terminal Tp. More specifically, the interceptor26may instruct the driving driver16to put the transistors Qif and Qdp into the on-state and put the other transistors into the off-state. In this case, only the current path is formed which goes round through the reactor L, the transistor Qif, and the diode Dir in this order. In this way, the energy stored in the reactor L when the overcurrent occurs flows in the current path. In the current path, the energy is consumed by the resistance components and the like, such as transistors and diodes, and the amount of current becomes 0. In this way, the overcurrent preventing circuit42consumes the energy stored in the reactor L when the overcurrent occurs, and further flow of overcurrent in the DUT2is prevented in the P-side switching measurement.

Note that compared to when the high-speed breaking circuit43is not operated, the resistance value contributing to the consumption of the overcurrent is large when the high-speed breaking circuit43is operated. Therefore, the energy stored in the reactor L is consumed in a short time. Therefore, further flow of overcurrent in the DUT2is more surely prevented in the switching measurement.

Next, a specific configuration of the replacement unit24will be described with reference toFIGS. 6 to 10.FIG. 6is a schematic configuration diagram of the replacement unit24.FIG. 7is a schematic configuration diagram of a motherboard for voltage included in the replacement unit24.FIG. 8is a schematic configuration diagram of a motherboard for current included in the replacement unit24.FIG. 9is a schematic configuration diagram of specific units that can be attached to and detached from the replacement unit24, wherein (a) ofFIG. 9is a plan view of the specific units, and (b) ofFIG. 9is a side view of the specific units.FIG. 10is a diagram for describing connection of the motherboard ofFIG. 8and the specific units ofFIG. 9.

As shown inFIG. 6, the replacement unit24includes a motherboard MB1and a motherboard MB2. The motherboard MB1is a motherboard for voltage. The motherboard MB2is a motherboard for current. The motherboard MB1and the motherboard MB2extend in a direction X and are arranged parallel to each other in a direction Y intersecting with the direction X. The high voltage units71, the low voltage units72, and an intermediate voltage unit74can be attached to and detached from the motherboard MB1. The intermediate voltage unit74is a unit for supplying a voltage of about 1500V to the high voltage units71and supplying a voltage of about 150V to the low voltage units72. The intermediate voltage unit74is not a unit directly related to the measurement and is used in subordination to the high voltage units71and the low voltage units72.

The large-current source unit73can be attached to and detached from the motherboard MB2. The large-current source unit73includes one large-current master75and a plurality of large-current boosters76(a plurality of current source subunits). The large-current master75is configured to control measurement of the DUT2requiring the large-current source unit73. The large-current master75can supply a current of, for example, about 1 A. The large-current boosters76are appropriately used according to the amount of current necessary for the measurement and can supply a current of a first amount of current. The first amount of current is, for example, about 125 A. The large-current master75transmits a current instruction to each large-current booster76at, for example, a timing designated by the integrated controller31. Each large-current booster76receives the current instruction transmitted from the large-current master75and supplies a current according to the current instruction. The large-current master75also measures the voltage and the current at a timing designated by the integrated controller31.

When the measurement item is a measurement item that requires the large-current source unit73, one large-current master75and one large-current booster76are always mounted on the replacement unit24. A necessary number of (for example, one to four) large current boosters76among the plurality of large-current boosters76are mounted on the replacement unit24according to the amount of current necessary for the measurement. Note that when the amount of current necessary for the measurement exceeds the amount of current that can be supplied by one large-current master75and four large-current boosters76(about 500 A in this example), another motherboard MB2may be further added to the replacement unit24. By mounting a necessary number of large-current boosters76on the added motherboard MB2, the large-current source unit73can supply the amount of current necessary for the measurement.

As shown inFIG. 7, the motherboard MB1includes: a connector CN1electrically connected to the power supply of the second apparatus20; a plurality of connectors CN2electrically connected to the static characteristic measurement circuit21; and a plurality of connectors CN3for electrical connection with each specific unit. The connector CN1, the connectors CN2, and the connectors CN3are provided on a surface MB1aon one side of the motherboard MB1. The connector CN1and the connectors CN2are arranged in the direction Y at one end of the motherboard MB1in the direction X. A power supply voltage for control is supplied to the high voltage units71, the low voltage units72, and the intermediate voltage unit74mounted on the motherboard MB1through the connector CN1. The high voltage units71and the low voltage units72mounted on the motherboard MB1are electrically connected to the static characteristic measurement circuit21through the connectors CN2. The connectors CN3for connection with each specific unit and guide mechanisms G (seeFIG. 10) form slots. Specifically, the motherboard MB1includes slots SL1to SL5that allow attaching and detaching the specific units. The slots SL1to SL5are sequentially arranged in the direction X. The slots SL1and SL2are slots for the high voltage units71. The slot SL3is a slot for the intermediate voltage unit74. The slots SL4and SL5are slots for the low voltage units72.

The connectors CN3include connectors CN31, connectors CN32, connectors CN33, connectors CN34, and connectors CN35. The connectors CN31are connectors for supplying each specific unit with the power supply voltage supplied through the connector CN1. The connectors CN32are connectors for supplying the voltage from the intermediate voltage unit74to the high voltage units71. The connectors CN33are connectors for supplying the voltage from the intermediate voltage unit74to the low voltage units72. The connectors CN34are connectors for electrically connecting the static characteristic measurement circuit21and the high voltage units71through the connectors CN2. The connectors CN35are connectors for electrically connecting the static characteristic measurement circuit21and the low voltage units72through the connectors CN2. The slots SL1and SL2are formed by the connectors CN31, CN32, and CN34, the slot SL3is formed by the connectors CN31, CN32, and CN33, and the slots SL4and SL5are formed by the connectors CN31, CN33, and CN35.

As shown inFIG. 8, the motherboard MB2includes: a connector CN4electrically connected to the power supply of the second apparatus20; a connector CN5electrically connected to the static characteristic measurement circuit21; and a plurality of connectors CN6for connecting each specific unit. The connector CN4, the connector CN5, and the connectors CN6are provided on a surface MB2aon one side of the motherboard MB2. The connector CN4and the connector CN5are arranged in the direction Y at one end of the motherboard MB2in the direction X. The power supply voltage for control is supplied to the large-current master75and the large-current boosters76mounted on the motherboard MB2through the connector CN4. The large-current master75and the large-current boosters76mounted on the motherboard MB2are electrically connected to the large-current measurement circuit23through the connector CN5. The connectors CN6for connecting each specific unit and the guide mechanisms G (seeFIG. 10) form slots. Specifically, the motherboard MB2includes slots SL6to SL10that allow attaching and detaching the specific units. The slots SL6to SL10are sequentially arranged in the direction X. The slot SL6is a slot for the large-current master75. The slots SL7to SL10are slots for the large-current boosters76.

The connectors CN6include a connector CN61, a connector CN62, connectors CN63, connectors CN64, and connectors CN65. The connector CN61is a connector for supplying the large-current master75with the power supply voltage supplied through the connector CN4. The connector CN62is a connector for electrically connecting the large-current measurement circuit23and the large-current master75through the connector CN5. The connectors CN63are connectors for supplying the large-current boosters76with the power supply voltage supplied through the connector CN4and for electrically connecting the large-current measurement circuit23and the large-current boosters76through the connector CN5. The connectors CN64and the connectors CN65are connectors for the current output from the large-current boosters76. The connectors CN64are + output connectors, and the connectors CN65are − output connectors. The slot SL6is formed by the connectors CN61and CN62, and the slots SL7to10are formed by the connectors CN63, CN64, and CN65. Note that on a surface on the opposite side of the surface MB2aon one side, the motherboard MB2includes a connector not shown connected to an external low voltage power supply.

The high voltage units71, the low voltage units72, the intermediate voltage unit74, the large-current master75, and the large-current boosters76all have similar configurations. Here, an example of the large-current master75will be used to describe the configuration of the specific units and the connection of the specific units and the motherboards with reference toFIGS. 9 and 10. As shown inFIG. 9, the large-current master75includes a control substrate81, a power substrate82, a connector83, a connector84, and connectors85. The control substrate81is a substrate for controlling the power substrate82to obtain desirable voltage and current. Note that on an end portion of the control substrate81on the opposite side of the motherboard MB2, the control substrate81includes a connector (for example, a LAN connector) for connection and communication with the integrated controller31and a connector (for example, a connector for optical communication) for connection and communication with the trigger matrix25. The control substrate81is commonly used by the high voltage units71, the low voltage units72, the intermediate voltage unit74, the large-current master75, and the large-current boosters76. The power substrate82varies for each of the high voltage units71, the low voltage units72, the intermediate voltage unit74, the large-current master75, and the large-current boosters76. The power substrate82of the high voltage units71and the low voltage units72performs power conversion for converting the constant voltage generated by the intermediate voltage unit74to desirable voltage and current. The power substrate82of the large-current source unit73performs power conversion for converting the power supply voltage of the second apparatus20to desirable voltage and current.

The connector83is a connector for connecting the large-current master75to the connector CN61of the motherboard MB2. The connector84is a connector for connecting the large-current master75to the connector CN62of the motherboard MB2. The connector83and the connector84are provided on one end82aof the power substrate82and are arranged along an edge of the one end82aof the power substrate82. The connectors85are connectors for electrically connecting the control substrate81and the power substrate82. A main surface on one side of the control substrate81and a main surface on one side of the power substrate82face each other through the connector85, and the control substrate81and the power substrate82are arranged in such a way that the control substrate81and the power substrate82overlap.

As shown inFIG. 10, the replacement unit24includes the guide mechanisms G. The guide mechanisms G are a pair of members extending in a direction Z intersecting with the surface MB2aon one side of the motherboard MB2. The guide mechanisms G hold both ends of the power substrate82of the large-current master75in the extending direction in such a way that the both ends can slide. Work of mounting the large-current master75on the motherboard MB2is performed by inserting the large-current master75into the slot SL6along the guide mechanisms G. In this case, the large-current master75is inserted into the slot SL6in a state that the one end82aof the power substrate82faces the surface MB2aon one side of the motherboard MB2. The large-current master75is inserted along the guide mechanisms G until the connector83and the connector84are fitted to the connector CN61and the connector CN62of the motherboard MB2, respectively. On the other hand, work of removing the large-current master75from the motherboard MB2is performed by pulling out the large-current master75from the slot SL6along the guide mechanisms G.

FIG. 11is a diagram showing the units used for each measurement.FIG. 11illustrates part of the static characteristic test and the dynamic characteristic test that can be conducted by the power semiconductor test system1. As shown inFIG. 11, the integrated controller31and the trigger matrix25are used for all measurements. In each measurement of the dynamic characteristic test, the test head12, the dynamic characteristic measurement circuit14, the capacitor bank15, the driving driver16, the current sensors17, the voltage sensors18, the interceptor26, the digitizer27, the charge power supply32, and the dynamic characteristic controller33are used in addition to the integrated controller31and the trigger matrix25. The large-current measurement circuit23is further used for the measurement of the emitter-collector voltage Vec.

On the other hand, the units used for each measurement vary in the static characteristic test. For example, the static characteristic measurement circuit21and the high voltage units71are used in addition to the integrated controller31and the trigger matrix25for the measurement of the collector breaking current Ices. For the measurement of the gate-emitter threshold voltage Vge (th), the static characteristic measurement circuit21, the gate servo22, the low voltage units72, and the large-current source unit73are used in addition to the integrated controller31and the trigger matrix25. For the measurement of the gate-emitter leakage current Iges, the static characteristic measurement circuit21and the low voltage units72are used in addition to the integrated controller31and the trigger matrix25. For the measurement of the collector-emitter saturation voltage Vce (sat), the static characteristic measurement circuit21, the large-current measurement circuit23, the low voltage units72, and the large-current source unit73are used in addition to the integrated controller31and the trigger matrix25.

In the power semiconductor test system1, the specific units (the high voltage units71, the low voltage units72, and the large-current source unit73) selectively used according to the measurement item of the static characteristic test can be attached to and detached from the replacement unit24. Therefore, necessary specific units can be mounted on the replacement unit24, and unnecessary specific units can be removed from the replacement unit24according to the requested measurement item of the static characteristic test. The gate servo22can be attached to and detached from the static characteristic measurement circuit21. Therefore, the gate servo22is mounted on the static characteristic measurement circuit21, or the gate servo22is removed from the static characteristic measurement circuit21according to the requested measurement item of the static characteristic test. As a result, even when the test item (measurement item) requested by each user varies, the power semiconductor test system1does not have to be separately designed, and the power semiconductor test system1that can handle requested specifications by simple work of just attaching and detaching the specific units and the gate servo22can be provided.

Furthermore, the magnitude of necessary current may vary according to the measurement item of the static characteristic test and the requested specifications of the user. When the measurement item is a measurement item requiring the large-current source unit73, one large-current master75and one large-current booster76are mounted on the replacement unit24. When the first amount of current that can be supplied by the one large-current booster76is smaller than the amount of current necessary for the measurement, a necessary number of large-current boosters76are further mounted on the replacement unit24. In this way, the large-current source unit73does not have to be separately designed according to the amount of current necessary for the requested measurement, and the power semiconductor test system1that can handle the requested specifications by simple work of just mounting the necessary number of large-current boosters76can be provided.

Furthermore, the magnitude of necessary voltage may vary according to the measurement item of the static characteristic test and the requested specifications of the user. When the measurement item is a measurement item requiring the high voltage units71, a necessary number of high voltage units71are mounted on the replacement unit24according to the voltage value necessary for the measurement. Similarly, when the measurement item is a measurement item requiring the low voltage units72, a necessary number of low voltage units72are mounted on the replacement unit24according to the voltage value necessary for the measurement. In this way, the high voltage units71and the low voltage units72do not have to be separately designed according to the voltage value necessary for the requested measurement, and the power semiconductor test system1that can handle the requested specifications by simple work of just mounting the necessary numbers of high voltage units71and low voltage units72can be provided.

In this way, necessary units are mounted on the replacement unit24, and unnecessary units are removed from the replacement unit24according to the requested specifications. In this case, the unit definition file is added and deleted in the integrated controller31according to the units attached to and detached from the replacement unit24. The integrated controller31detects a system configuration error when the unit designated by the unit definition file does not exist in the IP address included in the unit definition file. In this way, the integrated controller31can recognize the unit mounted on the replacement unit24. Note that in the large-current source unit73, the IP address may be allocated to the large-current master75, and the IP address may not be allocated to the large-current boosters76. That is, one IP address may be allocated for the entire large-current source unit73.

Each unit of the plurality of static characteristic units and the plurality of dynamic characteristic units is arranged at a position closer to the DUT2when the degree of influence, on the measurement accuracy of the DUT2, of the signal transmitted and received by the unit is larger. In this case, the unit that transmits and receives a signal with a large degree of influence on the measurement accuracy of the DUT2is arranged close to the DUT2, and the length of the wiring between the unit and the DUT2can be short. In other words, each unit is arranged in such a way that the larger the degree of influence, the shorter the length of the wiring between the unit and the DUT2. Therefore, inductance components of the wiring for transmitting a signal with a large degree of influence on the measurement accuracy of the DUT2can be reduced, and the measurement accuracy of the DUT2can be improved.

In the power semiconductor test system1of the embodiments, the units of the plurality of static characteristic units and the plurality of dynamic characteristic units are distributed to the first apparatus10, the second apparatus20, and the third apparatus30according to the management level Lv. That is, each unit is housed in one of the housing19, the housing28, and the housings34. The distance from the DUT2(wiring length from the DUT2) is, for example, about 10 to 100 mm for the units of the management level Lv1, the distance from the DUT2(wiring length from the DUT2) is, for example, about 10 to 100 cm for the units of the management level Lv2, and the distance from the DUT2(wiring length from the DUT2) is, for example, about 10 to 100 m for the units of the management level Lv3. Therefore, the first apparatus10, the second apparatus20, and the third apparatus30are arranged in such a way that the distance from the DUT2increases in order of the first apparatus10, the second apparatus20, and the third apparatus30. In other words, the second apparatus20is arranged at a position farther from the DUT2than the first apparatus10. The third apparatus30is arranged at a position farther from the DUT2than the second apparatus20. Therefore, the housing19, the housing28, and the housings34are arranged in such a way that the distance from the DUT2increases in order of the housing19, the housing28, and the housings34.

For example, when all of the units are housed in the housing19arranged near the DUT2, the housing19is enlarged, and the arrangement in using the power semiconductor test system1is limited. On the other hand, each unit can be distributed and housed in the housing19, the housing28, and the housings34according to the degrees of influence, on the measurement accuracy of the DUT2, of the signals transmitted and received by the unit to thereby downsize the housing19arranged near the DUT2while suppressing the reduction in the measurement accuracy of the DUT2.

For example, as shown inFIG. 12, the housing19(first apparatus10) can be arranged between a pair of conveyors3for conveying the DUT2, the housing28(second apparatus20) can be arranged near a conveyance line formed by the pair of conveyors3and the first apparatus10, and the housings34(third apparatus30) can be arranged at a position away from the conveyance line. In this way, by arranging the downsized first apparatus10on the conveyance line of the DUT2, it becomes possible to shorten the movement distance of the DUT2in the supply of the DUT2from the conveyor3positioned on the upstream of the conveyance line to the power semiconductor test system1and in the ejection of the DUT2from the power semiconductor test system1to the conveyor3positioned on the downstream of the conveyance line. That is, if the first apparatus10is enlarged, the conveyance interval of the DUT2needs to be increased, and the conveyance line becomes large. However, the conveyance interval of the DUT2can be reduced by downsizing the first apparatus10, and the conveyance line can be downsized. Therefore, it is unnecessary to provide a robot for transfer or the like in order to prevent the enlargement of the conveyance line. As a result, the test of the DUT2can be efficient. In this way, the degree of freedom of the arrangement in using the power semiconductor test system1can be improved.

Furthermore, by arranging the interceptor26near the current sensors17and the voltage sensors18, the wiring between the current sensors17and the interceptor26and between the voltage sensors18and the interceptor26can be short, and the detection accuracy of an abnormal state can be improved. Since the dynamic characteristic controller33and the driving driver16are connected by an optical signal through the interceptor26, high speed control is possible even if the dynamic characteristic controller33is arranged farther from the driving driver16than the interceptor26. Furthermore, by arranging the digitizer27near the current sensors17and the voltage sensors18, the wiring between the current sensors17and the digitizer27and between the voltage sensors18and the digitizer27can be short, and the measurement accuracy can be improved.

The plurality of static characteristic units (the static characteristic measurement circuit21, the gate servo22, the large-current measurement circuit23, the trigger matrix25, the high voltage units71, the low voltage units72, and the large-current source unit73) are housed in the housing28. Since the static characteristic test is less likely to be affected by the inductance components compared to the dynamic characteristic test, the static characteristic units can be arranged at positions somewhat away from the DUT2. In this way, the number of units housed in the housing19can be decreased. As a result, the housing19can be downsized without reducing the measurement accuracy of the DUT2.

By using the DIB11according to the type of the DUT2to be tested, it is unnecessary to design the power semiconductor test system1for each of the different types of DUTs2. That is, the part of the power semiconductor test system1except the DIB11can be shared regardless of the type of the DUT2.

Note that the power semiconductor test system according to the present invention is not limited to the embodiments. For example, the semiconductor elements included in the DUT2are not limited to the IGBTs. The semiconductor elements included in the DUT2may be field effect transistors (FETs), diodes, or the like. Even in such a DUT2, since the number and the arrangement of the probes62of the DIB11are appropriately designed according to the terminals of the DUT2, the design of the power semiconductor test system1does not have to be changed except for the DIB11.

The design of the static characteristic measurement circuit21may be changed according to the measurement item of the static characteristic test included in the requested specifications. Since the large-current measurement circuit23needs to select the measurement target included in the DUT2, the circuit configuration of the large-current measurement circuit23may be changed according to the number of elements to be measured included in the DUT2or the like when the difference in the number of elements to be measured included in the DUT2and the like according to the type of the DUT2cannot be absorbed by the DIB11. According to the configuration mentioned above, the customer's need can be met by appropriately changing the specific units mounted on the replacement unit24when supplying the test system to the customer, and by changing the design of the static characteristic measurement circuit21and the large-current measurement circuit23. In other words, the customer's need can be met by mainly changing the second apparatus20. Parts other than the second apparatus20can be dealt with by making minor adjustments to the software of the integrated controller31or the like, for example. In this way, the test system can be quickly supplied to customers with various requests, and the cost can be reduced.

The units mounted on the replacement unit24may be recognized by Plug and Play. In this case, the integrated controller31may detect the system configuration error when the units recognized by the system definition file and the units recognized by Plug and Play are different.

The P output terminal Tp and the N output terminal Tn may be parallel. For example, as shown inFIG. 13, each of the P output terminal Tp and the N output terminal Tn includes a cylinder portion91and a flat plate portion92. The cylinder portion91is a metallic bus bar and is inserted into the annular current sensor17. An outside diameter of the cylinder portion91is the same as an inside diameter of the current sensor17or is slightly smaller than the inside diameter of the current sensor17. Such a shape improves the current measurement accuracy while reducing the current density. The cylinder portion91includes an end portion91aand an end portion91b. The end portion91ais positioned at one end of the cylinder portion91and is semi-cylindrical. A surface91cof the end portion91aalong an axial center of the cylinder portion91is in contact with a surface on one side of a substrate53of the capacitor bank15. The surface91cof the P output terminal. Tp is in contact with a surface53aof the substrate53. The surface91cof the N output terminal Tn is in contact with a surface53bthat is a surface opposite the surface53aof the substrate53.

The end portion91bis positioned at the other end of the cylinder portion91. The flat plate portion92is electrically connected to the end portion91b. The flat plate portion92of the P output terminal Tp and the flat plate portion92of the N output terminal Tn are constituted as parallel flat plates formed by flat braided conductors across an insulator. The insulator is, for example, insulating paper or an insulating heat-shrinkable tube. In this case, since the flat plate portion92of the P output terminal Tp and the flat plate portion92of the N output terminal Tn are parallel, and currents in opposite directions flow in the flat plate portion92of the P output terminal Tp and the flat plate portion92of the N output terminal Tn, the inductance of the P output terminal Tp and the N output terminal Tn can be reduced. As a result, the measurement accuracy of the dynamic characteristic test can be improved. Furthermore, flexibility of the flat plate portions92can also be realized.

Furthermore, the connection pattern of the P output terminal Tp and the capacitor bank15and the connection pattern of the N output terminal Tn and the capacitor bank15may be parallel.FIG. 14is a diagram schematically showing an example of the capacitor bank15, wherein (a) ofFIG. 14is a cross-sectional view of the capacitor bank15, and (b) ofFIG. 14is an end view along a line XIVb-XIVb of (a) ofFIG. 14. As shown inFIG. 14, the capacitor bank15includes a plurality of capacitors51, the main switch portion52, and the substrate53. The substrate53is a multi-layer printed circuit board. In the example shown inFIG. 14, the substrate53is a four-layer printed circuit board. The substrate53includes the surface53aand the surface53bthat is a surface on the opposite side of the surface53a. The substrate53includes a base54that is a plate-like insulator and includes a first layer55, a second layer56, a third layer57, and a fourth layer58as wiring layers. The first layer55, the second layer56, the third layer57, and the fourth layer58are constituted by a conductive material such as copper foil. A wiring pattern is formed on each of the first layer55, the second layer56, the third layer57, and the fourth layer58.

The base54includes a surface54aand a surface54bthat is a surface on the opposite side of the surface54a. The first layer55is provided on the surface54a. The second layer56and the third layer57are provided inside of the base54. The + terminals of the capacitor51, the main switch portion52, and the P output terminal Tp are electrically connected to the second layer56, and the wiring of the second layer56forms P output wiring. The − terminals of the capacitors51and the N output terminal Tn are electrically connected to the third layer57, and the wiring of the third layer57forms N output wiring. The fourth layer58is provided on the surface54b. The surface53ais equivalent to the surface54aprovided with the first layer55, and the surface53bis equivalent to the surface54bprovided with the fourth layer58.

At the end portion53cof the substrate53, the end portion91aof the P output terminal Tp and the end portion91aof the N output terminal Tn are arranged in such a way as to sandwich the substrate53. The first layer55has a connection pattern55afor electrically connecting the end portion91aof the P output terminal Tp at the end portion53c. The fourth layer58has a connection pattern58afor electrically connecting the end portion91aof the N output terminal Tn at the end portion53c. The connection pattern55aand the connection pattern58aare arranged in parallel.

IVHs (Interstitial Via Holes)59are provided on the base54. The IVHs59are structures for electrically connecting the layers of the substrate53by providing a conductive material on wall surfaces of holes not penetrating through the base54. The IVHs59include IVHs59aand IVHs59b. The IVHs59aextend from the surface54atoward the inside of the base54and electrically connect the connection pattern55aof the first layer55and the second layer56. The IVHs59bextend from the surface54btoward the inside of the base54and electrically connect the third layer57and the connection pattern58aof the fourth layer58.

As shown inFIG. 15, when normal through hole vias159are used instead of the IVHs, holes penetrating through the base54are provided on the end portion53c. Since the potential difference is large around the through hole vias159, the wiring pattern needs to be provided at an insulation interval from the through hole vias159. Therefore, since the wiring pattern cannot be provided around the through hole vias159, the connection pattern55aand the connection pattern58acannot be sufficiently parallel at the end portion53cof the substrate53, and the inductance increases accordingly.

In this way, the connection pattern55aand the connection pattern58acan be arranged in parallel at the end portion53cof the substrate53by using the IVHs59. Therefore, the inductance of the P output wiring including the connection pattern55aand the N output wiring including the connection pattern58acan be further reduced. As a result, the measurement accuracy of the dynamic characteristic test can be further improved.

The thickness of the second layer56and the third layer57may be larger than the thickness of the first layer55and the fourth layer58. In this case, the current flowing through the second layer56and the third layer57can be increased. The interval between the second layer56and the third layer57may be smaller than the interval between the first layer55and the second layer56and the interval between the third layer57and the fourth layer58. In this case, the inductance of the P output wiring and the N output wiring can be further reduced, and the measurement accuracy of the dynamic characteristic test can be further improved.

REFERENCE SIGNS LIST