Semiconductor circuit apparatus with power save mode

A semiconductor circuit apparatus comprises a substrate and a circuit block including a memory formed on the substrate. The circuit block performs regular operations at a first power supply voltage in an active mode, and a part of the circuit block is stopped and the memory keeps stored data at a second power supply voltage smaller than the first power supply voltage in a power save mode. The memory holds the stored data during the power save mode, resulting in higher speed return to a regular active mode, as well as power consumption reduction.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The invention relates to a semiconductor circuit apparatus, more particularly, a semiconductor circuit apparatus having a power save mode and an active mode.

2. Description of Related Art

Semiconductor technological advances and more multifaceted and sophisticated products have given rise to demand for faster, more sophisticated, larger scale and less power consumption semiconductor circuits. In order to meet such demand, semiconductor chips with system on chip structure, in which multiple circuit blocks of different functions are formed, are widely used. Further, semiconductor circuit chips which have multiple operation modes are proposed to reduce the power consumption. Such electrical products have a standby mode, which is a power save mode, in which a part of the circuit is deactivated so that the standby power consumption is reduced.

One typical example of electric device with the standby mode is a handheld mobile device, such as a cellular phone and PDA (Personal Digital Assistance). Since the mobile devices use a battery as a power supply and there is a demand for long continuous use, the reduction of power consumption of semiconductor circuit chips is highly demanded. Furthermore, as more sophisticated cellular phones are introduced, more sophisticated and higher operation speed semiconductor circuit chips are significantly required.

Though a cellular phone needs to operate constantly in preparation for incoming calls, not all the circuit needs to operate constantly. Power consumption reduction is accomplished by activating only the necessary circuits during the standby period. An increase of the drive voltage results in higher speed circuit, but an increase in the drive voltage can lead to increased power consumption. Therefore, a technique is proposed which reduces the drive voltage and the thickness of gate insulating film of a device to accomplish reduced power consumption, as well as achieving high speed operation with increased on-current.

FIG. 10is a schematic block diagram of a related semiconductor circuit apparatus having multiple circuit blocks and a standby mode as an operation mode. A semiconductor circuit apparatus comprises the first circuit block1001, the second circuit block1002and I/O circuit part1003. The first and second circuit blocks1001,1002have a processor, a memory, an analog circuit portion part and a digital circuit part, respectively. Each of circuit blocks1001-1003has an interface control circuit.

FIG. 11shows the power supply voltage levels in an active mode and a standby mode. Vdd1, Vdd2and Vdd3correspond to the voltage levels of the first circuit block1001, the second circuit block1002and I/O circuit part1003, respectively. When entering the standby mode from the regular active mode, power supply to the second circuit block1002is stopped and only the first circuit block1001and I/O circuit part1003operate. The first circuit block1001contains a circuit which controls switching to the active mode and a memory for storing data necessary to return to the active mode.

In the above semiconductor circuit apparatus, the thicknesses of gate insulating films of respective circuit blocks may be set to different values. Specifically, it follows: I/O circuit part1003>first circuit block1001>second circuit block1002. Thinner gate insulating films of the second circuit block1002which operates in the active mode allow high speed operation of the circuit block. Furthermore, thicker gate insulating films of the first circuit block1001and I/O circuit part1003which operate in the standby mode afford a reduction in leak current and reduction in power consumption in the standby mode. A semiconductor circuit apparatus configured as above is disclosed in Japanese Published Unexamined Patent Application No. 2003-188351. Besides, Japanese Published Unexamined Patent Application No. 2001-156260, for example, discloses a technique varying the gate insulating film thickness from circuit block to circuit block.

The above mentioned circuit configuration can reduce the power consumption by using the standby mode. It has now been discovered that in the transition to the standby mode in the above semiconductor circuit apparatus, it is needed to fix input signals from the second circuit block1002to other circuit blocks, and also needed to clamp to ground or separate output signals from other circuit blocks to the second circuit block1002in order to stop the power supply to the second circuit block1002. Thus, the sequence to stop power supply to the second circuit block1002is necessary, as well as an interface control circuit.

Also, a regular power-on sequence is needed to return from the standby mode to the active mode and resume the power supply to the second circuit block since each node level is undefined. The circuit configuration and sequence for mode switching is thus complicated, and it takes long time to go into the active mode from the standby mode. And, the leak current control by changing only the thickness of a gate oxide film can not meet the requirements of both the operation performance during the active mode and leak current reduction during the standby mode.

SUMMARY OF THE INVENTION

According to an aspect of the invention, there is provided a semiconductor circuit apparatus comprising a circuit block including a memory, a power supply control circuit providing a reduced power supply voltage to the circuit block in a power save mode at which a part of the circuit block is stopped and the memory is capable of keeping stored data.

According to an aspect of the invention, there is provided a semiconductor circuit apparatus comprising a substrate and a circuit block including a memory formed on the substrate. The circuit block performs regular operations at a first power supply voltage in an active mode, and a part of the circuit block is stopped and the memory keeps stored data at a second power supply voltage smaller than the first power supply voltage in a power save mode.

The memory holds the stored data during the power save mode, resulting in higher speed return to a regular active mode, as well as power consumption reduction.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

FIG. 1is a schematic diagram illustrating a semiconductor circuit apparatus100according to this embodiment. Referring toFIG. 1, a voltage regulator102provides a semiconductor circuit chip101with power supply voltages, including a higher voltage Vdd and lower voltage Vss. A control processor103controls the semiconductor circuit chip101and the voltage regulator102. In this embodiment, the voltage regulator102and control processor103are formed outside of the semiconductor circuit chip101, namely formed in a different chip than the semiconductor circuit chip101.

The semiconductor circuit chip101comprises a first circuit block110, second circuit block120, and I/O circuit130which is a interface circuit performs date input/output with external circuits. The first and the second circuit blocks communicate data with external circuits through the I/O circuit130. Furthermore, the first circuit block110comprises a memory111, processor112, a logic circuit portion113and an analog circuit portion114. Similarly, the second circuit block120comprises a memory121, processor122, a logic circuit portion123and a analog circuit portion124.

In the semiconductor circuit chip101, the firs circuit block110, the second circuit block120and the I/O circuit130belong to different power supply systems, respectively and provided via separated individual power supply routs. Each of the circuit blocks110,120,130is provided powers supply potentials controlled individually. Each power supply potential may be the same or different. Typically, the I/O circuit130operates with a higher voltage than other circuit blocks.

The semiconductor circuit apparatus100have a standby mode, which is a power save mode, and an active mode as operation modes. The standby mode and active mode are switched in accordance with predetermined conditions, as appropriate. The standby mode stops predetermined circuit operations, allowing a reduction in the power consumption. One of typical semiconductor circuit apparatus with the standby mode and active mode is used in mobile electronics such as a cellular phone and PDA (Personal Digital Assistance).

For example, if the semiconductor circuit apparatus100constitutes a part of a cellular phone, it operates in the active mode during transmitting and receiving. The semiconductor circuit apparatus100is placed into the standby mode during other states and stops unnecessary circuit operations to reduce the power consumption. On the other hand, receiving an incoming call during the standby mode, the semiconductor circuit apparatus100enters the active mode from the standby mode immediately in response to the incoming call. Apparently, the invention may be applied to various types of circuit apparatus as well as mobile electronics.

The semiconductor circuit apparatus100according the present embodiment provides power supply voltage at such a level that a memory is capable of keeping stored data, allowing high speed switching from the standby mode to the active mode. Specifically, when the semiconductor circuit apparatus100goes into the standby mode from the active mode, the power supply voltages to the first circuit block110and the second circuit block120are lowered in the semiconductor circuit chip101in the standby mode. The power supply voltage to the I/O circuit130can be designed as appropriate. For example, the I/O circuit130may be driven constantly regardless of operations modes. Alternatively, the power supply may be stopped to reduce the power consumption.

The higher power supply potentials provided to the first circuit block110and the second circuit block120are kept at such a level that the memories111and112can hold data. The higher power supply potentials are preferably reduced to the lowest levels which enable the memories111and112to keep stored data, in terms of power consumption reduction. Preferably SRAMs are used for the memories111and121in terms of high operation speed and low power consumption. During the standby mode, circuit blocks other than the memories111and112are stopped in the first circuit block110and the second circuit block120. Specifically the processors112and122, the logic circuit portions113and123, and the analog circuit portions114and124are operationally stopped, respectively.

FIG. 2depicts a timing chart showing power supply potentials change in the active mode and the standby mode. Referring toFIG. 2, a switching operation of the operations modes will be described. In this example, the I/O circuit130operates constantly in both the active mode and the standby mode. Besides, the power supply potential Vdd1to the first circuit block110is higher than the power supply potential Vdd2to the second circuit block120inFIG. 2, as an example. Vdd2<Vdd1<Vdd3is established.

During the active mode, the voltage regulator102provides the first circuit block110, the second circuit block120and the I/O circuit130with power supply potentials Vdd1, Vdd2and Vdd3, respectively. If the predetermined conditions are satisfied to switch to the standby mode, the control processor103presents control signals to the semiconductor circuit chip101and the voltage regulator102to switch to the standby mode.

The control processor103has preset data to define each power potential in the standby mode and the active mode. The control signals to the voltage regulator102include reference levels to identify the power potentials. The voltage regulator102generates and provides each power supply potential in accordance with the reference levels set by the control processor103. The voltage regulator102reduces the power supply potential Vdd1and Vdd2for the standby mode. The power supply potential Vdd3to the I/O circuit130is maintained at the same level. Vdd1<Vdd1is established during the standby mode.

If predetermined conditions for transition to the active mode are satisfied, such as a cellular phone that receives an incoming call, the control processor103put out control signals to the semiconductor circuit chip101and the voltage regulator102to change to the active mode from the standby mode. The voltage regulator102raises the power supply potentials Vdd1and Vdd2for the first circuit block110and the second circuit block120to potentials for regular operations in accordance with the reference levels set by the control processor103.

As depicted inFIG. 2, the power supply potentials Vdd1and Vdd2for the first circuit block110and the second circuit block120never become zero (supply stop) and constant potentials are supplied (1.2 V in the active mode and 0.6 V in the standby mode, for example). These power supply potentials ensure that data in the memories111and121are kept. Node potentials of each circuit portion are thus defined as HIGH or LOW, dispensing with an interface circuit to determine input/output data between circuit blocks for switching between the active mode and the standby mode. Thus, a reduction in circuit scale is achieved.

Further, node potentials in each circuit block are defined as HIGH or LOW. Therefore, a sequence is not needed for determining node potentials required in a conventional circuit that stops power supply, affording a high speed transition from the standby mode to the active mode. Specifically, the operation mode control according to the embodiment reduces the mode switching time from conventional several tens of micro-seconds to several tens of nano-seconds.

While the voltage regulator102is formed outside the semiconductor circuit chip101(in a different chip) in the above example, the voltage regulator102, as shown inFIG. 3, may be formed within the semiconductor circuit chip101. In switching between the standby mode and the active mode, the voltage regulator102generates power supply potentials for circuit blocks according to the reference the control processor103to change supply potentials.

In mode switching, it is important to reduce leakage current during the standby mode to reduce the power consumption, as well as high speed switching. Sub-threshold leakage current and gate leakage current are known as the leak current. A MOS transistor with low threshold voltage can not turns off completely, leading to a large amount of sub-threshold leakage current. In a MOS transistor with a thin gate oxide film, tunnel leakage current flows through the thin gate oxide film. The tunnel leakage current flows from a gate to source/drain of from the source/drain to the gate.

Proper design for gate oxide film thickness is important to allow high speed operation and reduce leakage current. A thinner gate oxide film improves the operation performance, but it increases leakage current. On the other hand, thicker gate oxide film reduces leakage current, but it lowers the operation performance. Therefore, relatively thin gate oxide films are used in a circuit block which is required to operate at relatively high speed, and relatively thick gate oxide films are used in a circuit block which is not required to operate at high speed as another circuit. Design of proper different thicknesses of gate oxide films for different circuit blocks can keep the operation performance and reduce leakage current.

In the semiconductor circuit apparatus100illustrated inFIG. 1, transistors in each circuit block110,120and130have different thickness of gate oxide films. Specifically, the relation between the thicknesses of the circuit block110,120and130is as follows: I/O circuit130>first circuit block110>second circuit block120.

When this thickness relation is established, the relation between the leakage currents of the circuit block110,120and130is as follows: I/O circuit130<first circuit block110<second circuit block120. The power supply potential of each circuit block is the same as described referring toFIG. 2, and the relation between them is described by: Vdd2<Vdd1<Vdd3. The second circuit block120which has thinner gate oxide films is provided with power supply potential lower than other circuit blocks during both active mode and standby mode. The semiconductor circuit apparatus100lowers the power supply potential Vdd1and Vdd2to the predetermined levels, specifically, to the lowest levels at which the memories can hold data in the standby mode. As the power supply potential is decreased, the leakage current decreases exponentially. Sub-threshold leakage current decreases approximately in proportion to the power supply potential.

Therefore, the first circuit block110may, for example, have thinner gate oxide films to increase the ON-current of transistors to improve the operation performance in the active mode. It is possible to design a proper relation between an improvement (preservation) of the operation performance and a reduction in the power consumption by reduced leakage current with the standby mode and the gate oxide film thickness design according to desired circuit block characteristics.

In the above example, the first circuit block110and the second circuit block120belong to different power systems and they are provided with the power via different power supply routs. Alternatively, these two circuit blocks110,120may have a common power supply rout for common power supply control of the first circuit block110and the second circuit block120. In this case, the power supply potential Vdd1and Vdd2are the same value, as a timing chart inFIG. 4depicts. Other points are the same as Embodiment 1. This configuration simplifies power supply structure of a circuit and power supply control for each circuit block.

It is preferable to control a substrate potential to decrease leakage current during the standby mode.FIG. 5is a schematic diagram illustrating a semiconductor circuit apparatus according to the present embodiment. A substrate bias circuit501provides a substrate bias potential. The substrate bias circuit501is formed outside the semiconductor circuit chip101, and it is formed on the same chip as the voltage regulator102inFIG. 5. Other configuration is substantially the same asFIG. 1and details are omitted.

In a P type substrate, for example, the substrate potential during operation is generally set to ground. Reduction of the substrate potential (deviation in a negative direction) results in an increase in the threshold voltages of transistors. On the other hand, increase of the substrate potential (deviation in a positive direction) results in a decrease in the threshold voltages of transistors. An increase in the threshold voltage of a transistor results in a decrease in the sub-threshold leakage current. On the other hand, reduction of the power supply voltage along with the decrease of the threshold voltage of a transistor allows a decrease in the gate leakage current.

Therefore, the threshold voltage is preferably controlled to minimize the total leakage current of the sub-threshold leakage current and the gate leakage current. The substrate potential for the standby mode is reduced in the minus direction in a semiconductor circuit apparatus in which the sub-threshold leakage current is dominant. The leakage current during the standby mode is thus effectively reduced. On the contrary, the substrate potential for the standby mode is increased in the plus direction in a semiconductor circuit apparatus in which the gate leakage current is dominant. It allows a reduction in the leakage current during the standby mode.

In the active mode, the substrate potential is set to a proper value, not affecting adversely the operation performance of the circuit blocks110and120. Combination of the low voltage operation of the standby mode and the substrate potential control reduces effectively the power consumption (including leakage current) without performance degradation of a circuit block.

FIG. 6is a timing chart depicting the varying power supply potentials in the active mode and the standby mode. Referring toFIG. 6, switching operation of the operation modes will be described. In the example shown inFIG. 6, the I/O circuit130operates constantly regardless of the operation modes, namely operates during both the active mode and the standby mode. Further, the first circuit block110and the second circuit block120receive power supply potentials through a common path and the power potential Vdd1and Vdd2are the same value. Also, Vdd2=Vdd1<Vdd3is established.

In the active mode, the voltage regulator provides the first circuit block110, the second circuit block120and the I/O circuit130with Vdd1, Vdd2and Vdd3respectively. Further, the substrate bias circuit501sets the substrate potential to ground. If the predetermined conditions are satisfied for going into the standby mode, the control processor103provides control signals to the voltage regulator102and the substrate bias circuit501to enter the standby mode.

The control processor103has obtained data for identifying the power supply potential and substrate potential in advance, and the control signals to the voltage regulator102and the substrate bias circuit501include reference levels that identify each potential. The voltage regulator102produces the power supply potentials in accordance with the reference levels set by the control processor103and supply them.

Further, the substrate bias circuit501produces and provides the substrate potential in accordance with the reference level set by the control processor103. The voltage regulator102reduces the power supply potential Vdd1and Vdd2for the standby mode. The power supply potential to the I/O circuit130Vdd3is kept at the same level. The power supply potentials Vdd1and Vdd2are preferably set to the lowest potential respectively which enables a memory to keep the stored data, as described in Embodiment 1. The substrate bias circuit501reduces the substrate potential for the standby mode. Thus, the substrate potential is reduced or increased for the standby mode.

If the predetermined conditions are satisfied to go into the standby mode, the control processor103signals the semiconductor circuit chip101, the voltage regulator102and the substrate bias circuit501to enter the standby mode. The voltage regulator102raises the power supply potentials Vdd1and Vdd2for the first and second circuit blocks110and120to the potentials for the regular operations in accordance with the reference levels set by the control processor103. The substrate bias circuit501also returns the substrate potential to ground in accordance with the reference level set by the control processor103.

While the substrate bias circuit501is formed outside the semiconductor circuit chip101in the above mentioned example, it may be formed inside the semiconductor circuit chip101as illustrated inFIG. 7A, or both the voltage regulator102and the substrate bias circuit501may be formed inside the semiconductor circuit chip101as shown inFIG. 7B.

While, in the above embodiments, the control processor103provides the stored preset reference levels to the voltage regulator102and the substrate bias circuit501to control the power supply potential and the substrate potential, the present embodiment determines the potential level to keep data in a memory and controls the power supply potential in accordance with it.

FIG. 8is a simplified schematic block diagram of a semiconductor circuit apparatus800according to the present embodiment. A memory cell level determination circuit801is formed in the semiconductor circuit chip101to determine the power supply potential levels required so as for each of the memories111and112in the semiconductor circuit chip101to keep stored data. The voltage regulator102supplies the power supply potential in the standby mode based on the determination of the memory cell level determination circuit801. Since other configuration is substantially the same as Embodiment 1, the details are omitted.

FIG. 9is a detailed block diagram of a portion of the memory cell level determination circuit801.FIG. 9shows the configuration in the memory cell level determination circuit801to determine the potential level for the memory111contained in the first circuit block110. The memory cell level determination circuit801comprises a replica cell901, a reference circuit902and a comparison circuit903.

The replica cell901has the same circuit configuration as a cell in the memory111. If the memory111is SRAM, the cell includes flip-flops. Further, the replica cell901preferably has slightly worse characteristics than the cell in the memory111. Thus, it ensures that the power supply potential level required for keeping data stored in a cell in the memory111is determined reliably.

The reference circuit902puts out the reference level (potential level) which is compared to the output of the replica cell901. The reference level is smaller than HIGH output of the replica cell with the normal power supply potential. Specific values may be preset with proper design. The replica cell901is supplied with the same power supply potential as the memory110and changes its output according to the power supply potential. Comparing the output of the replica cell901with the reference level from the reference circuit902, HIGH/LOW of the output of replica cell901is determined, namely it is determined whether the power supply potential is at the level capable of kept stored data.

The comparison circuit903compares the replica cell output with the reference level from the reference circuit902to put out a determination signal. If HIGH output of the replica cell901is greater than the reference level from the reference circuit902, then the comparison circuit903can determine HIGH/LOW of the replica cell901output, so it determines that the power supply potential is large enough for the memory110to hold data and puts out the determination signal representing it.

If HIGH output of the replica cell901is smaller than the reference level, then the comparison circuit903cannot determine HIGH/LOW of the replica cell901output, so it determines that the power supply potential is not large enough for the memory110to hold data and puts out the determination signal representing it. The voltage regulator102controls the power supply potential in the standby mode according to the determination signal from the memory cell level determination circuit801.

Switching operation from the active mode to the standby mode will be described. For entering the standby mode, the voltage regulator102reduces the output power supply potential based on the control signals from the control processor103. The memory cell level determination circuit801carries out the determination process in response to the varying (decreasing) power supply potential level. The determination process compares the output of the replica cell901and the output of the reference circuit902at each power supply potential level.

If the output of the replica cell901is reduced smaller than the output of the reference circuit902and the determination signal changes to the signal indicating determination impossible, the voltage regulator102set the output potential to the power supply potential for the standby mode and keep the power supply potential at the output potential level during the standby mode. The memories110and120hold data at the power supply potentials determined by the memory cell level determination circuit. The voltage regulator102raises the power supply potential to the regular operation potential in accordance with the control signals from the control processor for going into the active mode from the standby mode.

The memory cell level determination circuit801comprises a circuit configured the same asFIG. 9for determining the memory potential in the second circuit block120, or if the memories111and121are controlled with a common power supply potential, the circuit configuration shown inFIG. 9may be used to determine the standby mode potential of the two memories.

In the present embodiment, the memory cell level determination circuit801formed in the semiconductor determines the power supply potential of the standby mode, thus affording the optimal power supply potential for each circuit block or chip. The above configuration of the memory cell level determination circuit is a preferred example and the memory cell level determination circuit according to the invention is not limited to this configuration.

It is apparent that the present invention is not limited to the above embodiment and it may be modified and changed without departing from the scope and spirit of the invention.