Semiconductor device and method of manufacturing the same

A semiconductor device and a method of manufacturing the same are disclosed. The semiconductor device includes a first insulation layer on or over a semiconductor substrate, metal patterns on or over the first insulation layer, a thin film resistor pattern disposed on or over the metal patterns, and an anti-reflection layer between the thin film resistor pattern and the metal patterns.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims under 35 U.S.C. §119 the benefit of Korean Patent Application No. 10-2011-0105469, filed Oct. 14, 2011, which is hereby incorporated by reference in its entirety.

BACKGROUND

Passive devices perform important functions in an electronic system. Recently, the making of miniaturized, multi-functional, and economical electronic appliances has become popular, and is giving rise to requirements for passive devices to be fabricated in the form of an array, a network, and a built-in passive device. Such passive devices sense, monitor, transmit, reduce, and control voltage.

Resistors as passive devices suppress a flow of electric charge or current, thereby controlling the amount of current. Such passive devices may be classified as a thin film resistor, in which a metal layer is thinly deposited to form a pattern, and an active layer resistor in an active area. Thin film resistors are generally disposed between metal lines in a semiconductor device.

FIG. 1is a cross-sectional view of a conventional semiconductor device including metal patterns and a thin film resistance pattern. The semiconductor device ofFIG. 1includes a semiconductor substrate10, a first dielectric20on the substrate10, a lower metal line30on the first dielectric20, and metal patterns40. Also, a second dielectric50, a thin film resistor pattern60, and a third dielectric70may be formed over the metal patterns40, and an upper metal line80, and a via90may be successively formed over the lower metal line30and over or adjacent to the metal patterns40.

As described above, in the process of manufacturing the semiconductor device, the thin film resistor pattern60may have a nonuniform profile, width, or shape due to the presence of the metal patterns40under some portions of the thin film resistor pattern60, and the absence of the metal patterns40under other portions of the thin film resistor pattern60. That is, in an exposure process performed on a photoresist material for patterning a thin film resistor material and forming the thin film resistor pattern60, a portion of the light may be transmitted through the thin film resistor material due to a thinness of the thin film resistor. The transmitted light is reflected by the metal patterns40located under the thin film resistor back to the photoresist over the thin film resistor material during the exposure process, and thus forming a photoresist pattern that has some relatively wide portions. The photoresist pattern is then used to pattern the thin film resistor material and form the thin film resistor pattern60. As a result, a profile of the thin film resistor pattern60may be deformed.

FIG. 2is an overhead photograph of a thin film resistor pattern formed according to the conventional manufacturing method described above. The photograph shows that a portion of the thin film resistor pattern formed in an area that contains underlying metal patterns has a uniform width, but the thin film resistor pattern disposed in an area that does not contain underlying metal patterns is reduced in width.

That is, referring toFIGS. 1 and 2, in the conventional method of manufacturing the semiconductor device including the metal patterns and the thin film resistor pattern, it may be difficult to form a thin film resistor pattern having a uniform profile. As a result, a resistance of the thin film resistor may be different from that desired by a designer.

SUMMARY OF THE INVENTION

Embodiments provide a semiconductor device having a desired resistance by providing a thin film resistor pattern having a regular and/or uniform profile.

In one embodiment, a semiconductor device includes: a first insulation layer on or over a semiconductor substrate; metal patterns on or over the first insulation layer; a thin film resistor pattern on or over the metal patterns; and an anti-reflection layer between the thin film resistor pattern and the metal patterns.

In another embodiment, a method of manufacturing a semiconductor device includes: forming a first insulation layer on a semiconductor substrate; depositing a metal layer on or over the first insulation layer; patterning the metal layer to form metal patterns; forming a second insulation layer on or over the first insulation layer and the metal patterns; forming an anti-reflection layer on or over the second insulation layer; forming a third insulation layer on or over the anti-reflection layer; and forming a thin film resistor layer on or over the third insulation layer and patterning the thin film resistor layer to form a thin film resistor pattern.

Details of various embodiments of the present invention are set forth in the accompanying drawings and the description below. However, the following description of the invention does not limit the scope of the invention as defined in the appended claims. It will be understood by those skilled in the art that various changes, equivalents, and modifications may be made without departing from the scope of the present invention as defined in the claims. Other features will be apparent from the description and drawings, and from the claims.

DETAILED DESCRIPTION OF THE EMBODIMENTS

Hereinafter, embodiments of a semiconductor device and a method of manufacturing the same in accordance with the present invention will be described with reference to the accompanying drawings.

FIG. 3is a cross-sectional view of a semiconductor device according to a first embodiment.FIGS. 4 to 9are cross-sectional views illustrating a process of manufacturing the semiconductor device according to the first embodiment.

Referring toFIG. 3, a semiconductor device according to the first embodiment includes a first insulation layer200on or over a semiconductor substrate100, metal patterns300on or over the first insulation layer200, a thin film resistor pattern700over the metal patterns300, and an anti-reflection layer500between the thin film resistor pattern700and the metal patterns300. In addition, the semiconductor device according to the first embodiment may further include a second insulation layer400on or over the metal patterns300and a third insulation layer600on or over the anti-reflection layer500.

Referring toFIG. 4, a first insulation layer200is formed on a semiconductor substrate100. The semiconductor substrate100may be a single-crystal silicon wafer, or a single-crystal silicon wafer with one or more layers of epitaxial silicon grown thereon. The first insulation layer200may comprise an oxide layer (e.g., a silicon oxide, formed by chemical vapor deposition [CVD] of a silicon source such as tetraethyl-orthosilicate (TEOS) or silane and an oxygen source such as dioxygen [O2] and/or ozone [O3], etc.).

Also, the first insulation layer200may be formed as a single layer or a plurality of layers. For example, the first insulation layer200may include a first insulation sublayer201and a second insulation sublayer202on or over the semiconductor substrate100. Here, the first insulation sublayer201may be a pre-metal-dielectric (PMD; e.g., a silicon oxide, formed by CVD of a silicon source such as tetraethyl-orthosilicate (TEOS) or silane and an oxygen source such as dioxygen [O2] and/or ozone [O3], a spin on glass [SOG], a borophosphosilicate glass [BPSG], a phosphosilicate glass [PSG], etc.), and the second insulation sublayer202may be an inter-metal dielectric (IMD; e.g., a silicon oxide, formed by CVD of a silicon source such as tetraethyl-orthosilicate (TEOS) or silane and an oxygen source such as dioxygen [O2] and/or ozone [O3], a SOG, a BPSG, a PSG, a low k dielectric such as fluorosilicate glass [FSG], polyimide, HSG, etc.).

Referring toFIGS. 5 and 6, metal patterns300are formed on or over the first insulation layer200. A metal layer310(e.g., comprising aluminum deposited on a Ti/TiN bilayer, capped with a TiN-on-Ti bilayer, etc.) may be deposited on the first insulation layer200, and a photoresist pattern (PR) may be formed on the metal layer310. Then, a photolithography process and an etching process may be performed to form the metal patterns300. After the metal patterns300are formed, the photoresist pattern (PR) is removed by an asking or stripping process.

Referring toFIG. 6, the metal patterns300may be formed at regular intervals (e.g., with a consistent spacing between adjacent metal patterns), but the present embodiments are not limited thereto. That is, the metal patterns300may alternatively be spaced at irregular or varying distances.

Referring toFIG. 7, a second insulation layer400and an anti-reflection layer500may be sequentially formed on or over the metal patterns300. The anti-reflection layer500may comprise an inorganic-based material, but is not limited thereto. For example, the anti-reflection layer500may comprise a silicon oxynitride (SiON) layer. A chemical vapor deposition process may be performed using SiH4, N2O, and He as source gases to form the SiON anti-reflection layer500.

The anti-reflection layer500may be uniformly distributed on or over the second insulation layer400. For example, the anti-reflection layer500may be formed on an entire top surface of the second insulation layer400. The anti-reflection layer500may have a thickness of about 50 Å to about 500 Å (e.g., about 100 Å to about 400 Å, about 150 Å to about 350 Å, or any value or range of values therein). The anti-reflection layer500will be described below in detail together with a thin film resistor pattern700.

Referring toFIG. 8, a third insulation layer600and a thin film resistor layer410are formed on or over the anti-reflection layer500. For example, the third insulation layer600may be an oxide layer (e.g., a silicon oxide, formed by CVD of a silicon source such as tetraethyl-orthosilicate (TEOS) or silane and an oxygen source such as dioxygen [O2] and/or ozone [O3], SOG, etc.), but is not limited thereto. The third insulation layer600may have a thickness of about 1000 Å to about 5000 Å (e.g., about 1500 Å to about 4000 Å, about 2000 Å to about 3000 Å, or any value or range of values therein).

A resistor material may be used to form the thin film resistor layer410without specific limitations. For example, the thin film resistor layer410may comprise at least one compound selected from the group consisting of CrSi, NiCr, TaN, CrSi2, CrSiN, CrSiO, and combinations thereof, but is not limited thereto.

For example, the thin film resistor layer410may be manufactured by depositing SiCr or NiCr on or over the third insulation layer600at a thickness of about 10 Å to about 500 Å through by PVD (e.g., a sputtering process).

Thereafter, referring toFIG. 9, a photoresist pattern (PR) may be formed on or over the thin film resistor layer410. The photoresist pattern may be formed by depositing a photoresist material (e.g., positive photoresist) over the thin film resistor layer410and then patterning the photoresist material in a photolithography process. The photoresist pattern may define the thin film resist pattern700. Subsequently, an etching process may be performed using the photoresist pattern as a mask to form the thin film resistor pattern700.

The thin film resistor pattern700, when viewed from overhead, may have a substantially rectangular profile (e.g., similar to the profile shown inFIG. 2). For instance, the profile of the thin film resistor pattern700may have parallel sides that extend longer (i.e., are longer) than the other sides of the profile running perpendicular thereto. The length W1inFIG. 9may represent the longer sides of the profile of the thin film resistor pattern700, which extend in a first direction. However, the thin film resistor pattern700is not limited to such a shape. For example, the thin film resistor pattern700may have a square or another alternative shape. The term ‘extend’ used herein may denote that a ratio of a long axis of the thin film transistor pattern700to a short axis thereof is 5:1 or greater (e.g., about 5:1 to about 100:1, or any value or range of values therein). However, the ratio of the sides of the thin film transistor pattern700is not limited to such ratios.

The thin film resistor pattern700may be formed as a thin film. For example, the thin film resistor pattern700may have a thickness ranging from about 10 Å to about 500 Å (e.g., about 25 Å to about 400 Å, about 50 Å to about 300 Å, about 100 Å to about 250 Å, or any value or range of values therein). Thus, in the exposure process for manufacturing the thin film resistor pattern700, a portion of the light used in the exposure process to form a photoresist pattern may be transmitted through the thin film resistor layer700, and may reach the metal patterns300, where it may be reflected back to the photoresist material. In the absence of the anti-reflection layer (e.g., as in a conventional semiconductor device) the reflected light may alter the pattern of the photoresist material during the exposure process and thereby cause deformation of the thin film resistor pattern (see, e.g., the Background discussion above). To solve the above-described limitation, the current embodiment includes the anti-reflection layer500under the thin film resistor pattern700. The anti-reflection layer500is intended to prevent the reflection of light that passes through the thin film resistor pattern from underlying metal patterns back to the photoresist material during the photoresist exposure process, where the reflected light can distort the photoresist pattern.

The anti-reflection layer500is disposed between the thin film resistor pattern700and the meal patterns300. For example, the anti-reflection layer500may be between the second insulation layer400and the third insulation layer600.

Here, the anti-reflection layer500may overlap the thin film resistor pattern700and the metal patterns300. For example, from an overhead perspective, the two dimensional area of the thin film resistor pattern700may completely overlap with the anti-reflection layer500directly underlying it. Stated another way, the two-dimensional area (e.g., footprint) of the thin film resistor pattern700may be completely included within the periphery of the two-dimensional area of the underlying anti-reflection layer500and/or overlap the anti-reflection layer500. In one embodiment, the anti-reflection layer500may have a width W2greater than that W1of the thin film resistor pattern700, but is not limited thereto.

Referring toFIGS. 3 and 9, the anti-reflection layer500may be formed on or over an entire top surface of the second insulation layer400, but the present embodiments are not limited thereto. In one embodiment, the anti-reflection layer500of the semiconductor device may be formed on or over only a portion of the second insulation layer400.

FIGS. 10 and 11are cross-sectional views illustrating a semiconductor device according to a second embodiment. Referring toFIG. 10, an anti-reflection layer510may be formed on only a portion of a top surface of the second insulation layer400. That is, the anti-reflection layer510may be patterned to be on a portion of the top surface of the second insulation layer400.

Referring toFIG. 10, the anti-reflection pattern510may be formed to correspond to the periphery of the overlying thin film resistor pattern700. In detail, the anti-reflection pattern510may be formed to correspond to the two-dimensional surface area (e.g., footprint) of the overlying thin film resistor pattern700. For example, the thin film resistor pattern700may be within the periphery of the directly underlying anti-reflection pattern510, and thus be completely overlapped by the anti-reflection pattern510. The anti-reflection pattern510may have a width W2greater than that W1of the thin film resistor pattern700, but the present embodiments are not limited thereto. Here, the anti-reflection pattern510may completely overlap both the length and width dimensions of the thin film resistor pattern700from an overhead perspective. Thus, the anti-reflection pattern510blocks light from passing to the underlying metal patterns300during a photoresist exposure process (e.g., a forming a photoresist pattern to define the anti-reflection pattern510), and thereby prevents the reflection of light from the metal pattern300to the perimeter of the photoresist pattern where it may distort the photoresist pattern.

Referring toFIG. 11, the anti-reflection pattern520may be formed to correspond to only the periphery of the thin film resistor pattern700on the anti-reflection pattern520, but the present embodiments are not limited thereto. In this embodiment, the anti-reflection layer520underlies the periphery or outline of the overlying thin film resistor pattern700in order to prevent the reflection of light to the periphery of the photoresist pattern (e.g., which defines the thin film resistor pattern700) during an photoresist exposure and/or patterning process. That is, the anti-reflection pattern520may have an annular shape and be formed to correspond to only the periphery of the thin film resistor pattern700, but may not be under a center region of the thin film resistor pattern700.

That is, the anti-reflection pattern520according to the second embodiment may be formed to correspond to the inside (e.g., center area) and periphery of the overlying thin film resistor pattern700may correspond only to the periphery of the overlying thin film resistor pattern700in order to prevent the reflection of light from the metal patterns300to the periphery of the photoresist pattern defining the thin film resistor pattern700during the photoresist exposure process. Thus, in the semiconductor device according to the second embodiment, the thin film resistor pattern700having a regular, uniform, and controllable profile may be manufactured.

FIG. 12is a cross-sectional view of a semiconductor device according to a third embodiment. Referring toFIG. 12, the anti-reflection layer includes a plurality of anti-reflection patterns530. Each of the anti-reflection patterns530may correspond to one of the underlying metal patterns300. For example, one of the plurality of anti-reflection pattern530may correspond to each of the metal patterns300in a one-to-one arrangement. Here, each of the anti-reflection patterns530may have a width W2greater than a width W3of the underlying metal pattern. Thus, each anti-reflection pattern may completely overlap the underlying metal pattern from an overhead perspective. Also, a portion of the plurality of anti-reflection patterns530may be disposed to correspond to the periphery of the thin film resistor pattern700.

The anti-reflection patterns530according to the third embodiment may correspond to the metal patterns300and the periphery of the thin film resistor pattern700. Specifically, the anti-reflection patterns530may overlap with the periphery of the overlying thin film resistor pattern700and completely overlap the underlying metal patterns300. Thus, in accordance with the third embodiment, a semiconductor device having a thin film resistor pattern700with a regular, uniform, and controllable profile may be manufactured.

In the semiconductor device according to the embodiments of the present invention, the anti-reflection layer located between the thin film resistor pattern and the metal patterns allows for the formation of a thin film resistor pattern having a regular, uniform, and controllable profile. Accordingly, the semiconductor device may have stable resistance characteristics, and any mismatch thereof may be reduced or eliminated.

Any reference in this specification to “one embodiment,” “an embodiment,” “example embodiment,” etc., means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the invention. The appearances of such phrases in various places in the specification are not necessarily all referring to the same embodiment. When a particular feature, structure, or characteristic is described in connection with any one embodiment, one skilled in the art will understand that such feature, structure, or characteristic may be included in other embodiments with which the feature, structure, or characteristic is compatible.