Wafer carrier having provisions for improving heating uniformity in chemical vapor deposition systems

A wafer carrier and methods of making the same for use in a system for growing epitaxial layers on one or more wafers by chemical vapor deposition. The wafer carrier includes wafer retention pockets recessed in its body. A thermally-insulating spacer is situated at least partially in the at least one wafer retention pocket and arranged to maintain a spacing between the peripheral wall surface and the wafer, the spacer being constructed from a material having a thermal conductivity less than a thermal conductivity of the wafer carrier such that the spacer limits heat conduction from portions of the wafer carrier body to the wafer. The wafer carrier further includes a spacer retention feature that engages with the spacer and includes a surface oriented to prevent centrifugal movement of the spacer when subjected to rotation about the central axis.

FIELD OF THE INVENTION

The invention relates generally to semiconductor fabrication technology and, more particularly, to chemical vapor deposition (CVD) processing and associated apparatus for reducing temperature non-uniformities on semiconductor wafer surfaces.

BACKGROUND OF THE INVENTION

In the fabrication of light-emitting diodes (LEDs) and other high-performance devices such as laser diodes, optical detectors, and field effect transistors, a chemical vapor deposition (CVD) process is typically used to grow a thin film stack structure using materials such as gallium nitride over a sapphire or silicon substrate. A CVD tool includes a process chamber, which is a sealed environment that allows infused gases to be deposited upon the substrate (typically in the form of wafers) to grow the thin film layers. An example of a current product line of such manufacturing equipment is the TurboDisc® family of MOCVD systems, manufactured by Veeco Instruments Inc. of Plainview, N.Y.

A number of process parameters are controlled, such as temperature, pressure and gas flow rate, to achieve a desired crystal growth. Different layers are grown using varying materials and process parameters. For example, devices formed from compound semiconductors such as III-V semiconductors typically are formed by growing successive layers of the compound semiconductor using metal organic chemical vapor deposition (MOCVD). In this process, the wafers are exposed to a combination of gases, typically including a metal organic compound as a source of a group III metal, and also including a source of a group V element which flow over the surface of the wafer while the wafer is maintained at an elevated temperature. Typically, the metal organic compound and group V source are combined with a carrier gas which does not participate appreciably in the reaction as, for example, nitrogen. One example of a III-V semiconductor is gallium nitride, which can be formed by reaction of an organo-gallium compound and ammonia on a substrate having a suitable crystal lattice spacing, as for example, a sapphire wafer. Typically, the wafer is maintained at a temperature on the order of 1000-1100° C. during deposition of gallium nitride and related compounds.

In a MOCVD process, where the growth of crystals occurs by chemical reaction on the surface of the substrate, the process parameters must be controlled with particular care to ensure that the chemical reaction proceeds under the required conditions. Even small variations in process conditions can adversely affect device quality and production yield. For instance, if a gallium and indium nitride layer is deposited, variations in wafer surface temperature will cause variations in the composition and bandgap of the deposited layer. Because indium has a relatively high vapor pressure, the deposited layer will have a lower proportion of indium and a greater bandgap in those regions of the wafer where the surface temperature is higher. If the deposited layer is an active, light-emitting layer of an LED structure, the emission wavelength of the LEDs formed from the wafer will also vary to an unacceptable degree.

In a MOCVD process chamber, semiconductor wafers on which layers of thin film are to be grown are placed on rapidly-rotating carousels, referred to as wafer carriers, to provide a uniform exposure of their surfaces to the atmosphere within the reactor chamber for the deposition of the semiconductor materials. Rotation speed is on the order of 1,000 RPM. The wafer carriers are typically machined out of a highly thermally conductive material such as graphite, and are often coated with a protective layer of a material such as silicon carbide. Each wafer carrier has a set of circular indentations, or pockets, in its top surface in which individual wafers are placed. Typically, the wafers are supported in spaced relationship to the bottom surface of each of the pockets to permit the flow of gas around the edges of the wafer. Some examples of pertinent technology are described in U.S. Patent Application Publication No. 2012/0040097, U.S. Pat. No. 8,092,599, U.S. Pat. No. 8,021,487, U.S. Patent Application Publication No. 2007/0186853, U.S. Pat. No. 6,902,623, U.S. Pat. No. 6,506,252, and U.S. Pat. No. 6,492,625, the disclosures of which are incorporated by reference herein.

The wafer carrier is supported on a spindle within the reaction chamber so that the top surface of the wafer carrier having the exposed surfaces of the wafers faces upwardly toward a gas distribution device. While the spindle is rotated, the gas is directed downwardly onto the top surface of the wafer carrier and flows across the top surface toward the periphery of the wafer carrier. The used gas is evacuated from the reaction chamber through ports disposed below the wafer carrier. The wafer carrier is maintained at the desired elevated temperature by heating elements, typically electrical resistive heating elements disposed below the bottom surface of the wafer carrier. These heating elements are maintained at a temperature above the desired temperature of the wafer surfaces, whereas the gas distribution device typically is maintained at a temperature well below the desired reaction temperature so as to prevent premature reaction of the gases. Therefore, heat is transferred from the heating elements to the bottom surface of the wafer carrier and flows upwardly through the wafer carrier to the individual wafers. Also, the heat transferred upwards through the carrier material is radiated from the top surface of the wafer carrier. The degree of radiative emission from the wafer carrier is determined by the emissivity of the carrier and the surrounding components.

A great deal of effort has been devoted to system design features to minimize temperature variations during processing; however, the problem continues to present many challenges. For instance, wafers are significantly less thermally conductive than the wafer carrier. Introducing a sapphire wafer in a pocket of the wafer carrier creates a heat-trapping, or “blanketing” effect. This phenomenon results in a generally radial thermal profile at the pocket floor which is hotter in the center and lower temperature towards the outer radius of the pocket, where the heat can be emitted by radiation and convection into the environment.

Another effect that impacts thermal uniformity of the wafers in-process is the thermal gradient across the thickness of the wafer, which causes a concave bow, resulting in a non-uniform gap distance between the wafer bottom and pocket floor. This is because the hotter bottom of the wafer tends to expand more in relation to the colder top surface, thereby assuming a classical concave shape. The concave bow will generally add to the thermal non-uniformity that already exists on the wafer due to thermal blanketing effects. Due to the very small thermal conductance of the gas gap compared to the carrier material, the wafer surface temperature is extremely sensitive to changes in the gap magnitude. In the case of a concave bow, the center of the wafer will be closer to the pocket floor, and consequently hotter compared to the outer edges. This effect is more pronounced in larger-diameter wafers, which are typically made from silicon. Also, with silicon wafers in particular, the bowing is further aggravated by film stresses from a crystal lattice mismatch between the silicon substrate and the deposited layers used to fabricate the devices on the substrate.

A related thermal conduction transfer process also occurs in the lateral direction from wafer carrier pocket edge to the wafer edge, depending upon this distance. In CVD tools utilizing a high-speed rotating wafer carrier, the wafers are typically driven towards the outer edge of the pockets due to high centrifugal forces. Thus, these wafers are in typically in contact with the outer pocket edge. The non-concentric position of a wafer in the pocket creates a non-uniform gap from the pocket edge that is zero at the point of contact, and increases circumferentially away from the contact point. The smaller gap between the wafer and carrier in regions close to the point of contact increases the conductive heat transfer from the carrier to the wafer. This “close proximity” effect results in much higher edge temperatures in the region of contact. Co-pending U.S. patent application Ser. No. 13/450,062, the disclosure of which is incorporated by reference herein, describes approaches for reducing the proximity effect utilizing “bumpers” to center the wafer at a prescribed distance from the pocket edge. These bumpers have been shown to be successful in virtually eliminating the high temperature crescent generated by the proximity effect. However, several practical challenges remain, particularly

Another challenge in maintaining temperature uniformity over the wafers relates to the wafers, which are typically circular, flat discs, having one or more straight portions of their edge commonly referred to as “flats.” Flats are generally used to indicate the doping type of the wafer, as well as the crystallographic orientation of the wafer, and are typically found on wafers smaller than 200 mm. In CVD processing, however, the flats present a non-uniformity for heat transfer to the wafer. In particular, the heat transfer to the portion of the wafer near the flat tends to be reduced due to the separation between the edge of the wafer flat and the wafer carrier. Also, the flat introduces a variation in gas flow that also affects the temperature in the vicinity of the flat.

A further concern relates to multi-wafer pocket geometries with non-concentric pocket locations. Here, the thermal profile becomes more complicated as the convective cooling is dependent upon the historical gas streamline path passing over both the wafer carrier and wafer regions. For high-speed rotating disc reactors, the gas streamlines spiral outward from inner to outer radius in a generally tangential direction. In this case, when the gas streamline is passing over the exposed portion of the wafer carrier (such as the regions of “webs” between the wafers), it is heated up relative to the regions where it is passing over the wafers. In general, these webs are quite hot relative to the other regions of the carrier where the wafers are situated, as the heat flux streamlines due to the blanketing effect have channeled the streamlines into this region. Thus, the gas paths passing over the webs create a tangential gradient in temperature due to the convective cooling, which is hotter at the leading edge (entry of the fluid streamline to the wafer) relative to the trailing edge (exit of the fluid streamline over the wafer).

These effects contribute to a reduced product yield since devices fabricated from portions of the wafer near the flat tend to exhibit increased photoluminescence relative to the target value for the rest of the wafer. Solutions are needed that addresses one or more of these, and related, challenges in improving wafer heating uniformity in CVD reactors.

SUMMARY OF THE INVENTION

Aspects of the invention are directed to a chemical vapor deposition (CVD) system in which thermal non-uniformities along the edges of the wafers are significantly reduced. In one aspect, a wafer carrier has a body formed symmetrically about a central axis, and including a generally planar top surface that is situated perpendicularly to the central axis. At least one wafer retention pocket is recessed in the wafer carrier body from the top surface. Each one wafer retention pocket includes a floor surface and a peripheral wall surface that surrounds the floor surface and defines a periphery of that wafer retention pocket, the wafer retention pocket is adapted to retain a wafer within the periphery when subjected to rotation about the central axis. A thermally-insulating spacer is situated at least partially in the at least one wafer retention pocket and arranged to maintain a spacing between the peripheral wall surface and the wafer. The spacer is constructed from a material having a thermal conductivity less than a thermal conductivity of the wafer carrier body such that the spacer limits heat conduction from portions of the wafer carrier body to the wafer. A spacer retention feature is formed in the wafer carrier body that engages with the spacer and includes a surface oriented to prevent centrifugal movement of the spacer when subjected to rotation about the central axis.

In another aspect of the invention, a method is provided for forming the wafer carrier. In the method, a wafer carrier body is formed that is symmetric about a central axis. A generally planar top surface is formed in the body that is situated perpendicularly to the central axis. A plurality of wafer retention pockets are formed, with each of the pockets being recessed in the body from the top surface. In the pockets there is a floor surface and a peripheral wall surface that surrounds the floor surface and defines a periphery of that wafer retention pocket. The wafer retention pocket is adapted to retain a wafer within the periphery when subjected to rotation about the central axis.

The method further comprises situating a thermally-insulating spacer at least partially in the at least one wafer retention pocket to maintain a spacing between the peripheral wall surface and the wafer. The spacer is constructed from a material having a thermal conductivity less than a thermal conductivity of the wafer carrier body such that the spacer limits heat conduction from portions of the wafer carrier body to the wafer. A spacer retention feature is formed in the wafer carrier body such that the spacer retention feature engages with the spacer and provides a surface oriented to prevent centrifugal movement of the spacer when subjected to rotation about the central axis.

In related aspects of the invention, the wafer carrier is part of an apparatus for growing epitaxial layers on one or more wafers by chemical vapor deposition that includes a reaction chamber, a rotatable spindle having an upper end disposed inside the reaction chamber, where the wafer carrier is centrally and detachably mounted on an upper end of the spindle and is in contact therewith at least in the course of a CVD process.

DETAILED DESCRIPTION

FIG. 1illustrates a chemical vapor deposition apparatus in accordance with one embodiment of the invention. A reaction chamber8defines a process environment space. A gas distribution device12is arranged at one end of the chamber. The end having the gas distribution device12is referred to herein as the “top” end of the chamber8. This end of the chamber typically, but not necessarily, is disposed at the top of the chamber in the normal gravitational frame of reference. Thus, the downward direction as used herein refers to the direction away from the gas distribution device12; whereas the upward direction refers to the direction within the chamber, toward the gas distribution device12, regardless of whether these directions are aligned with the gravitational upward and downward directions. Similarly, the “top” and “bottom” surfaces of elements are described herein with reference to the frame of reference of chamber8and gas distribution device12.

Gas distribution device12is connected to sources14a,14b,14cfor supplying process gases to be used in the wafer treatment process, such as a carrier gas and reactant gases such as a metalorganic compound and a source of a group V metal. The gas distribution device12is arranged to receive the various gases and direct a flow of process gasses generally in the downward direction. The gas distribution device12desirably is also connected to a coolant system16arranged to circulate a liquid through the gas distribution device so as to maintain the temperature of the gas distribution device at a desired temperature during operation. A similar coolant arrangement (not shown) can be provided for cooling the walls of chamber8. Chamber8is also equipped with an exhaust system18arranged to remove spent gases from the interior of the chamber through ports (not shown) at or near the bottom of the chamber so as to permit continuous flow of gas in the downward direction from the gas distribution device.

A spindle20is arranged within the chamber so that the central axis22of the spindle extends in the upward and downward directions. The spindle is mounted to the chamber by a conventional rotary pass-through device25incorporating bearings and seals (not shown) so that the spindle can rotate about axis22, while maintaining a seal between the spindle and the wall of chamber8. The spindle has a fitting24at its top end, i.e., at the end of the spindle closest to the gas distribution device12. As further discussed below, fitting24is an example of a wafer carrier retention mechanism adapted to releasably engage a wafer carrier. In the particular embodiment depicted, the fitting24is a generally frustoconical element tapering toward the top end of the spindle and terminating at a flat top surface. A frustoconical element is an element having the shape of a frustum of a cone. Spindle20is connected to a rotary drive mechanism26such as an electric motor drive, which is arranged to rotate the spindle about axis22.

A heating element70is mounted within the chamber and surrounds spindle20below fitting24. The chamber is also provided with an entry opening72leading to an antechamber76, and a door74for closing and opening the entry opening. Door74is depicted only schematically inFIG. 1. and is shown as movable between the closed position shown in solid lines, in which the door isolates the interior of chamber8from antechamber76, and an open position shown in broken lines at74′. The door74is equipped with an appropriate control and actuation mechanism for moving it between the open position and closed positions. In practice, the door may include a shutter movable in the upward and downward directions as disclosed, for example, in U.S. Pat. No. 7,276,124, the disclosure of which is hereby incorporated by reference herein. The apparatus depicted inFIG. 1may further include a loading mechanism (not shown) capable of moving a wafer carrier from the antechamber76into the chamber and engaging the wafer carrier with the spindle in the operative condition, and also capable of moving a wafer carrier off of the spindle and into antechamber76.

The apparatus also includes a plurality of wafer carriers80. In the operating condition shown inFIG. 1, a first wafer carrier80is disposed inside chamber8in an operative position, whereas a second wafer carrier80is disposed within antechamber76. Each wafer carrier80includes a body82which is substantially in the form of a circular disc having a central axis84(FIG. 2). The body82is formed symmetrically about central axis84. In the operative position the central axis84of the wafer carrier body is coincident with the axis22of the spindle. The body82may be formed as a single piece or as a composite of plural pieces. For example, as disclosed in U.S. Patent Application Pub. No. 20090155028, the disclosure of which is hereby incorporated by reference herein, the wafer carrier body may include a hub defining a small region of the body surrounding the central axis84and a larger portion defining the remainder of the disc-like body. The body desirably is formed from materials which do not contaminate the process and which can withstand the temperatures encountered in the process. For example, the larger portion of the disc may be formed largely or entirely from materials such as graphite, silicon carbide, or other refractory materials. The body has a generally planar top surface88and a bottom surface90extending generally parallel to one another and generally perpendicular to the central axis84of the disc. The body also has one, or a plurality, of wafer-holding features adapted to hold a plurality of wafers.

In operation, a wafer124, such as a disc-like wafer formed from sapphire, silicon carbide, or other crystalline substrate, is disposed within each pocket90of each wafer carrier80. Typically, the wafer124has a thickness which is small in comparison to the dimensions of its major surfaces. For example, a circular wafer of about 2 inches (50 mm) in diameter may be about 430 μm thick or less. As illustrated inFIG. 1, the wafer is disposed with a top surface126facing upwardly, so that the top surface is exposed at the top of the wafer carrier. It should be noted that in various embodiments, wafer carrier80carries different quantities of wafers. For instance, in one example embodiment, the wafer carrier is adapted to hold six wafers. In another example embodiment, as shown inFIG. 2, wafer carrier80holds 12 wafers.

In a typical MOCVD process, a wafer carrier80with wafers loaded thereon is loaded from antechamber76into chamber8and placed in the operative position shown inFIG. 1. In this condition, the top surfaces of the wafers face upwardly, towards the gas inlet structure12. Heater70is actuated, and the rotary drive mechanism26operates to turn spindle20and hence wafer carrier80around axis22. Typically, the spindle is rotated at a rotational speed from about 50-1500 revolutions per minute. Process gas supply units14a,14b, and14care actuated to supply gases through the gas distribution device12. The gases pass downwardly toward the wafer carrier80, over the top surface88of the wafer carrier and the top surfaces126of the wafers, and downwardly around the periphery of the wafer carrier to the outlet and to exhaust system18. Thus, the top surface of the wafer carrier and the top surfaces of the wafer are exposed to a process gas including a mixture of the various gases supplied by the various process gas supply units. Most typically, the process gas at the top surface is predominantly composed of the carrier gas supplied by carrier gas supply unit14b. In a typical chemical vapor deposition process, the carrier gas may be nitrogen, and hence the process gas at the top surface of the wafer carrier is predominantly composed of nitrogen with some amount of the reactive gas components.

Heaters70transfer heat to the bottom surface90of the wafer carrier, principally by radiant heat transfer. The heat applied to the bottom surface of the wafer carrier flows upwardly through the body82of the wafer carrier to the top surface88of the wafer carrier. Heat passing upwardly through the body also passes upwardly through gaps to the bottom surface of each wafer, and upwardly through the wafer to the top surface126of the wafer. Heat is radiated from the top surface88of the wafer carrier and from the top surfaces126of the wafer to the colder elements of the process chamber as, for example, to the walls of the process chamber and to the gas distribution device12. Heat is also transferred from the top surface88of the wafer carrier and the top surfaces126of the wafers to the process gas passing over these surfaces.

In the embodiment depicted, the system includes a number of features designed to determine uniformity of heating of the surfaces126of each wafer124. In this embodiment, temperature profiling system130receives temperature information122that can include a temperature and temperature monitoring positional information from temperature monitor120. In addition, temperature profiling system130receives wafer carrier positional information, which in one embodiment can come from rotary drive mechanism26. With this information, temperature profiling system130constructs a temperature profile of the wafers124on wafer carrier80. The temperature profile represents a thermal distribution on the surface126of each of the wafers124.

FIGS. 2 and 3illustrate wafer carrier80in greater detail. Each wafer retention site is in the form of a generally circular recess, or pocket92extending downwardly into the body from the top surface88. The generally circular shape is made to correspond to the shape of the wafers. Each pocket92has a floor surface94disposed below the surrounding portions of the top surface88. Floor surface94can be flat (as shown), or it can be concave, convex, textured, etc. Each pocket also has a peripheral wall surface96surrounding the floor surface and defining the periphery of the pocket. The peripheral wall surface96extends downwardly from the top surface88of the body toward the floor surface. In various embodiments, the peripheral wall surface96can have an undercut where the wall slopes inwards, i.e., towards the center of the pocket, over at least a portion of the periphery. Thus, such a sloped the peripheral wall surface96would form an acute angle relative to floor surface94. In one example embodiment, the angle formed between peripheral wall surface96and floor surface94is 80 degrees.

One aspect of the invention is directed to the addition of a thermally-insulating spacer, as partially illustrated inFIG. 3at100. Thermally-insulating spacer100can have a variety of structural arrangements according to various embodiments, several of which are detailed below. An important feature of spacer100, in one type of embodiment, is that spacer100is constructed and situated so that it maintains a separation between the wafer which sits in pocket92, and peripheral wall surface94. In a related type of embodiment, spacer100also creates a space between the wafer and floor surface94by supporting the wafer at its edges at a height that is elevated relative to floor surface94. Various structures of spacer100are contemplated to provide these functions, several of which are detailed below. In related embodiments, spacer100has features that help to retain wafers in their pockets during processing. For instance, one embodiment uses lateral extensions referred to herein as lips, which extend over parts of the top surface of the wafer, thereby preventing the wafer from lifting off its bottom support and being ejected from the pocket due to the massive centrifugal forces at high rotatational velocities.

Another feature of spacer100is its heat-insulating characteristic. Since heat transfer to the wafer occurs primarily from heat flowing though the body of wafer carrier80, the thermally-insulating characteristic in the present context means that the thermal conductivity of spacer100is less than the thermal conductivity of wafer carrier80. Thus, spacer100not only provides separation between the wafer and the peripheral (and, optionally, the floor) surfaces of the wafer carrier, but also spacer100limits the conductive heat transfer between the wafer carrier surface(s) and the outer edge of the wafer.

In one type of embodiment, when wafer carrier80is made primarily from graphite, spacer100is made from a ceramic material such as sapphire, quartz, aluminum nitride, silicon nitride, silicon carbide, silicon, gallium nitride, gallium arsenide, or other suitable material that can withstand applicable process temperatures, that has a suitable thermal expansion coefficient, and that has a thermal conductivity less than graphite.

In a related embodiment, wafer carrier80has one or more spacer retention features that are adapted to engage with each spacer100. The spacer retention features according to various embodiments can have a variety of structures, though in an important aspect, certain embodiments of the spacer retention features are specifically constructed to retain the spacers100while subjected to process conditions involving lateral forces due to the rotation of wafer carrier80. Notably, significant centrifugal forces are exerted by the wafer being forced in an outward radial direction from the central axis84against one or more of the spacers100. This force, in turn, is opposed by the spacer and the spacer retention features of wafer carrier80. According to one embodiment, the spacer and the spacer retention feature cooperate to form a bracing arrangement that locks the spacer in place in response to an applied centrifugal force along an outward radial direction from the central axis.

In another related embodiment, the spacer has an upper portion that laterally extends along the top surface of the wafer carrier in a direction away from the center of the pocket. This configuration advantageously provides heat insulating properties for the top surface of the wafer carrier that is not beneath a wafer, thereby improving heat flux uniformity within the wafer carrier body and, ultimately, the in-process heating uniformity of the wafers.

FIG. 4is a schematic plan-view diagram that illustrates wafer24situated inside wafer retention pocket92a, and further retained by spacers100a, which are separate spacer structures according to one embodiment. In this example, each of spacers100ais situated partially in wafer retention pocket (particularly, along the outer periphery of each pocket92). Each spacer100aincludes a wafer interface surface106a. Also depicted schematically are spacer retention features200athat are formed in body82aof the wafer carrier as spacer retention recesses (defined by the surrounding material of body82a), and in each of which at least a portion a spacers100aresides. In various embodiments, the spacer retention recesses are recessed into the top surface88aof the wafer carrier, into the floor surface94aof the wafer retention pocket, or both.

FIG. 5is a schematic cross-sectional view diagram illustrating another exemplary arrangement in which spacer100bis retained by spacer retention feature200b. In this example, spacer retention feature200bprotrudes upwards from top surface88bof the example wafer carrier, in which wafer retention pocket92bis defined having floor surface94b, as depicted. Spacer100bhas a first portion102bthat extends downwards toward floor surface94b, and a second portion that is situated over the top surface88b.

FIGS. 6A and 6Brespectively depict another exemplary spacer,100cthat includes a post structure102c, and a head structure104c. Post structure102cis designed to fit almost entirely within a spacer retention feature. Head structure104cis designed such that a portion thereof is inside the periphery of the wafer retention pocket, and includes a wafer edge interface surface106c, and a wafer bottom support tab108c. In one embodiment, as depicted, wafer edge interface surface106cis undercut (i.e., sloped inwards toward the wafer retention pocket center) in order to help lock the wafer in place when the wafer carrier is being used in-process. Wafer bottom support tab108chas a top surface that is situated higher than floor surface94cwhen spacer100cis installed. This arrangement permits wafer bottom support surface108cto retain the wafer in a spaced relationship relative to floor surface94. In particular, in a process, gas may flow between the bottom of the wafer and floor surface94. Head structure104cfurther includes a spacer bracing portion110cthat serves to reinforce, or lock the spacer in place with the spacer retention feature.

FIG. 7is a cross-sectional view diagram of a wafer carrier having a wafer retention pocket92c. Spacer retention feature200cincludes bore sections202cand204c. Bore section202cextends into body82cof the wafer carrier well below the bottom surface94cof wafer retention pocket92c. Bore section202cis designed to engage post structure102c. Likewise, a larger upper bore section204cis formed to engage head structure104c. Upper bore section204calso extends down below the floor surface94c. A portion of upper bore section204calso protrudes into wafer retention pocket92c. This is the portion that includes wafer edge interface surface106cand wafer bottom support tab108c. In this embodiment, spacer retention feature200calso includes spacer bracing cutout210cdefined by the body82cof the wafer carrier, and situated along a radial axis from the center of wafer retention pocket92con the distal end of spacer retention feature200c. In an assembled wafer carrier, spacer bracing cutout210cengages with spacer bracing portion110c.

FIG. 8is a top-view diagram illustrating an exemplary arrangement of a wafer carrier according to a related embodiment in which wafer retention pocket92cand a plurality of spacer retention features200c, are shown. Spacer retention features200c, are positioned around the periphery of pocket92cin a non-uniform fashion, with a higher density of spacer retention features positioned at a distal end of pocket92crelative to the central axis of the wafer carrier.

FIG. 9is a top-view schematic diagram illustrating another type of geometry for spacer100according to one embodiment. As depicted, spacer100dis a continuous, ring-shaped structure that is situated along a circumference of wafer retention pocket92d.FIG. 10is a cross-sectional view of section10-10, in which spacer retention feature200dis an upward protrusion similar to the embodiment ofFIG. 5. As depicted in this embodiment, the profile of spacer100dis generally Z-shaped. In a related embodiment, the interior surface of spacer retention feature200dwhich engages with spacer100dmay be undercut (i.e., inwardly sloping) to help better retain the ring-shaped spacer100d.

In other embodiments, any suitable profile may be used. Also, in other embodiments, the protrusion200dmay be omitted. In this latter case, the peripheral wall surface surrounding the floor surface of pocket92dcan function as a spacer retention feature.

FIG. 11is a schematic diagram depicting a variation of the embodiment ofFIG. 10. In this example, spacer100eis ring-shaped, and follows the contour of the wafer retention pocket as in the previous embodiment, but spacer100ediffers in that it has a C-shaped profile. A first portion102eof the C-shaped spacer ring extends down into, or down past (as depicted) wafer retention pocket floor surface94e. A second portion of the C-shaped profile103eextends into trench200e, which serves as a spacer retention feature in this embodiment.

In a variation of this embodiment, as depicted schematically inFIG. 12, spacer103fhas a lateral extension portion103fthat extends along the top surface88fof the wafer carrier to provide thermal insulating over portions of the top surface beyond the periphery of the wafer retention pocket92f. This top-side insulation can be beneficial in avoiding temperature non-uniformities due to the blanketing effect. Essentially, extending the thermal insulation over the “web” areas of the wafer carrier creates a uniform blanket, thereby avoiding non-heat-insulating surfaces from which heat can be more easily emitted by radiation or transferred out by conduction or convection, resulting in cooler spots and hotter spots on the wafer during CVD processing. In a related embodiment, as depicted, spacer100fincludes a ledge portion108f, which protrudes radially towards the center of the pocket92falong pocket floor surface94f. In this example the spacer retention feature200fis embodied by the trench into which the deep portion of the spacer extends downward.

FIG. 13Ais an exploded-view diagram illustrating another type of embodiment, where the spacer100is realized as a compound structure comprising an upper ring spacer100g1, and a lower ring spacer100g2. When assembled, the upper and lower ring spacers fit together in a nested fashion, as shown in more detail in the cross-sectional view diagram of a portion of the assembly inFIG. 13B. In this embodiment, each ring spacer100g1,100g2has a generally L-shaped profile. The upper spacer100g1fits over the corner of the lower spacer100g2as depicted. The assembled rings are inserted into trench200g, which has a depth substantially below that of wafer retention pocket floor surface94g. In the assembly, lower spacer100g2provides a ledge108gthat extends around the circumference of the wafer retention pocket92g. Upper ring spacer100g1provides a wafer edge interface surface106g. The nested assembly of the upper and lower ring spacers is retained reliably in trench200gthanks to the undercut of peripheral wall96g. Likewise, the wafer is reliably retained by virtue of an undercut in wafer edge interface surface106g.

As a variation to the embodiments described with reference toFIGS. 13A and 13B,FIG. 14is an exploded-view diagram that illustrates a compound spacer composed of upper ring spacer100h1and lower ring spacer100h2. Lower ring spacer100h2is similar to lower ring spacer100g2described above, except that lower ring spacer100h2has a plurality of tabs108hsituated along its interior wall. Tabs108hprotrude inwards, i.e., towards the center of the pocket, and serve to raise the wafer by its bottom surface (at its edges) off of the wafer retention pocket floor. This is an analogous function to ledge108g, except that the group of tabs do not constitute a continuous ledge. Advantageously, for some applications, there is an opportunity for process gasses to flow beneath the wafer to some extent. Tabs108hare arranged with increasing density (i.e., closer together) at the distal end of the pocket (i.e., farthest from the central axis on with the wafer carrier rotates in-process) since the distal end of the wafer is subjected to the greatest stresses due to the centrifugal force from high-speed rotation of the wafer carrier. In order to align the tabs108hproperly with respect to the wafer carrier's central axis, a set of keys,112hand114h, implemented in one embodiment as protrusions, engage with a notch in the wafer carrier's body (not shown). Since ring spacers100h1and100h2engage with one another, upper ring spacer100h1has a key112hthat fits over and engages with the key114hof lower ring spacer.

FIG. 15is a cross-sectional view diagram illustrating another variation of the embodiment described above with reference toFIGS. 13A and 13B. In the embodiment depicted inFIG. 15, lower ring spacer100i2is similar to lower ring spacer100g2. It likewise provides a ledge108i(or tabs), and is locked in place in nesting fashion by upper ring spacer100i1. The primary difference lies in upper ring spacer100i1. In particular, wafer edge interface surface106iis not necessarily undercut (although it may be). Instead of relying on the undercut to retain the wafer reliably, a lip115iextends towards the center of the pocket. With a wafer present in the pocket, lip115iwould reach over the top edge of the wafer. In this embodiment, the lip115iis continuous along the entire circumference of upper ring spacer1001. In a related embodiment, the lip115iis in the form of tabs at various locations around the circumference; i.e., there is no continuous lip. Lip115iprevents the wafer from being ejected from the wafer retention pocket by opposing upward movement of the wafer edge.

In a related aspect of the invention, provisions are made for improving wafer edge-to-edge heating uniformity for wafers that have one or more flat edges, or flats.FIG. 16is a diagram illustrating an approach according to one type of embodiment. Wafer carrier380has a wafer retention pocket392recessed from the top surface like a conventional wafer carrier; however, the floor surface394is specially modified to increase heat transfer to the flat edge of the wafer. In particular, flat compensation portion350of the pocket floor is sloped downward from the pocket's periphery towards the center of the pocket for some distance corresponding to the size of the flats of the wafers for which wafer carrier380is designed.

FIGS. 17A and 17Bare cross-sectional view diagrams of section17-17fromFIG. 16.FIG. 17Aillustrates an interior peripheral pocket wall396, adjacent to which is a flat compensation portion350athat includes a raised flat pocket floor portion652a, which after some distance takes the form of a concave downward curved profile. In one embodiment, the transition point between the flat and concave parts is based on the position of the flat edge of wafer380. For example, in one embodiment, the transition is situated directly below the flat edge of the wafer.

FIG. 17Billustrates a similar embodiment, though with three sections of the floor portions: flat section352b, linearly-sloping section353, and concave-sloping section354b. The relative positions of each of the sections can be optimized based on empirical data from process runs, and the photoluminescence variability produced in each run.

FIG. 18is a schematic diagram illustrating, in top view, a wafer retention pocket designed to accommodate a wafer with two flats. Here, there are two flat compensation portions aligned according to the wafer flat alignment on the wafer.

FIG. 19illustrates another approach, namely, use of a non-round pocket. In this example, a generally flat peripheral wall portion450is designed to coincide with the wafer flat. This approach maintains essentially the same distance between the wafer flat and the peripheral wall of the pocket as every other point along the wafer's edges. In a related approach, the generally flat wall portion450is not actually perfectly flat. Instead, there is a slight convex curvature of a very large radius. This creates a protrusion of the peripheral wall towards the center of the pocket. The geometry facilitates removal of the wafer from the pocket following processing, since it avoids binding of the wafer's edges against the peripheral wall, which can happen if the wafer becomes forced into the corner at the transition between the curved peripheral wall and the generally flat wall portion450.

FIG. 20is a top-view schematic diagram illustrating another type of geometry for a spacer100according to one embodiment in which the spacer100is used to accommodate wafer flats. As depicted, spacer100jis a continuous, ring-shaped structure that has a flat interior portion101jthat is meant to coincide with the wafer flat of wafer124j. Spacer100jis situated along a circumference of round wafer retention pocket92j. Since the outer circumference of ring-shaped spacer100jis round, spacer100jcan be placed in any orientation according to one embodiment. In a related embodiment, a key-and notch feature is utilized to require a certain orientation of the wafer flat. In this embodiment, the thermally-insulating properties of spacer100jobviate any non-uniformities experienced at the flat edge of wafer124jdue to spacing between wafer edge and pocket periphery. This approach is not mutually exclusive of the embodiments ofFIGS. 16-18. Thus, it can be combined with flat compensation portion350of the pocket floor in some embodiments.

The embodiments above are intended to be illustrative and not limiting. Other variations are contemplated to fall within the claims. In addition, although aspects of the present invention have been described with reference to particular embodiments, those skilled in the art will recognize that changes can be made in form and detail without departing from the scope of the invention, as defined by the claims.

Persons of ordinary skill in the relevant arts will recognize that the invention may comprise fewer features than illustrated in any individual embodiment described above. The embodiments described herein are not meant to be an exhaustive presentation of the ways in which the various features of the invention may be combined. Accordingly, the embodiments are not mutually exclusive combinations of features; rather, the invention may comprise a combination of different individual features selected from different individual embodiments, as will be understood by persons of ordinary skill in the art.

Any incorporation by reference of documents above is limited such that no subject matter is incorporated that is contrary to the explicit disclosure herein. Any incorporation by reference of documents above is further limited such that no claims that are included in the documents are incorporated by reference into the claims of the present application. The claims of any of the documents are, however, incorporated as part of the disclosure herein, unless specifically excluded. Any incorporation by reference of documents above is yet further limited such that any definitions provided in the documents are not incorporated by reference herein unless expressly included herein.