Paralleling of switching devices for high power circuits

A circuit includes first and second half bridges, a first inductor, a second inductor, and a main inductor. The half bridges each include a high side switch, a low side switch, and a gate driver configured to apply switching signals to the high side switch and the low side switch. The first inductor has one side electrically connected to an output node of the first half bridge between the high side switch and the low side switch. The second inductor has one side electrically connected to an output node of the second half bridge between the high side switch and the low side switch. The main inductor is coupled to a node between the other sides of the first and second inductors. The main inductor has a greater inductance than each of the first and second inductors, and the first and second inductors are inversely coupled to one another.

TECHNICAL FIELD

This specification relates to circuit configurations and methods that allow for operation of high-speed power circuits at very high current and power levels.

BACKGROUND

Using high-speed III-N power switches involves balancing requirements for heat transfer, ease of assembly, and high-speed, low-inductance electrical interconnection. Conventional leaded power packages, such as any of the variations of the TO-220 package100, which is illustrated inFIG. 1, can be used with III-N power switches. The combination of a metal mounting tab102and flexible copper leads104,106, and108permits attachment of the package to effective heat sinks in a variety of configurations. Connection to a PCB with conventional soldering techniques permits ease of manufacture.

Nonetheless, the package leads typically introduce undesirable inductance. Reduction in switching speed caused by this inductance may be an acceptable design compromise, but instability may still present a problem. Since a power switch can be a high-gain device, if allowed to operate in a linear mode, care should be taken that any oscillations due to parasitic resonances do not couple to a node where positive feedback may sustain or amplify the oscillations.

FIG. 2is a circuit diagram of a half bridge circuit comprising a gate driver202, a high side III-N transistor204coupled to a high voltage node206, and a low side III-N transistor208coupled to a ground node210. Two terminals231and233of the gate driver202are coupled to respective gates of the transistors204and208, and two terminals232and234of the gate driver202are coupled to respective sources of the transistors204and208, such that the gate driver is able to apply voltage signals to the gates of each of transistors204and208relative to their respective sources. An inductor214is coupled to the half bridge circuit at an output node212.

In operation, the gate driver202can operate the transistors204and208in a constant-current mode (CCM), switching rated current at rated voltage. For example, the high voltage node206can provide a voltage of 400V or 600V or greater, and the III-N transistors can be configured with a rating to withstand the resulting high currents. Due to the inductance of the inductor214, current flowing through the inductor214cannot change instantaneously.

To illustrate the operation of the half bridge, consider an example scenario where the gate driver202turns the high side transistor204on and turns the low side transistor208off. Current flows from the high voltage node206, through the high side transistor204, and through the output node212to the inductor214. When the gate driver202turns the high side transistor204off, the inductance of inductor214drives the voltage at node212negative, which allows current to flow up through the low side transistor208even though it is off. If the half bridge is implemented using a conventional package, the undesirable inductance introduced by the package leads can cause significant ringing and oscillation related to transient current flowing through the circuit, which can interfere with a stable, efficient switching function.

SUMMARY

In a first aspect, a circuit includes a first half bridge, a second half bridge, a first inductor, a second inductor, and a main inductor. The first half bridge includes a first high side switch, a first low side switch, and a first gate driver, the first gate driver being configured to apply switching signals to the first high side switch and the first low side switch. The second half bridge includes a second high side switch, a second low side switch, and a second gate driver, the second gate driver being configured to apply switching signals to the second high side switch and the second low side switch. The first inductor has a first side electrically connected to an output node of the first half bridge, the output node of the first half bridge being between the first high side switch and the first low side switch. The second inductor has a first side electrically connected to an output node of the second half bridge, the output node of the second half bridge being between the second high side switch and the second low side switch. The main inductor is coupled to a node which is between a second side of the first inductor and a second side of the second inductor. An inductance of the main inductor is greater than an inductance of each of the first and second inductors, and the first and second inductors are inversely coupled to one another.

In a second aspect, a method of operating a circuit configured to provide an output current to a load is described. The method includes applying, by a first gate driver of a first half bridge of the circuit, switching signals to a first high side switch and a first low side switch of the first half bridge, and responsive to the applied switching signals, providing a first output current through an output of the first half bridge; applying, by a second gate driver of a second half bridge of the circuit, switching signals to a second high side switch and a second low side switch of the second half bridge, and responsive to the applied switching signals, providing a second output current through an output of the second half bridge; during a first time period, while providing to the load the output current of the circuit at a first current level, operating both the first and second half bridges to provide the first and second output currents through their respective outputs, such that during the first time period the total output current provided to the load is a sum of the first and second output currents; and during a second time period, while providing to the load the output current of the circuit at a second current level smaller than the first current level, operating the first half bridge to provide the first output current through its output while maintaining the second half bridge in an OFF state, such that during the second time period the total output current provided to the load is equal to the first output current.

The methods and devices described herein may each include one or more of the following. A coupling coefficient of the first and second inductors is in a range of about −0.9 to −1.0. The first and second high side switches are configured to receive common timing signals from a first PWM source, and the first and second low side switches are configured to receive common timing signals from a second PWM source. The first and second half bridges are connected in parallel and are configured to operate as a single half bridge circuit, the single half bridge circuit having a higher maximum output current than either of the first and second half bridges.

The first PWM source is coupled to a first input of the first gate driver and to a first input of the second gate driver, and the second PWM source is coupled to a second input of the first gate driver and to a second input of the second gate driver. The first and second high side switches and the first and second low side switches each comprise two or more switches connected in parallel. The first and second high side switches are both connected to a high voltage node, and the first and second low side switches are both connected to a low voltage or ground node.

The voltage at the high voltage node relative to the low voltage or ground node is about 400V or higher. The first and second gate drivers are configured to apply the switching signals at a frequency between 30 kHz and 10 MHz. The first and second high side switches and the first and second low side switches comprise III-Nitride devices. The III-Nitride devices can be III-Nitride enhancement mode transistors. The III-Nitride devices can be hybrid devices, each hybrid device comprising a depletion mode III-Nitride transistor and an enhancement mode silicon transistor. The main inductor can be part of a load that is driven or controlled by the half bridges of the circuit. The load can comprise an electric motor.

As used herein, the terms III-Nitride or III-N materials, layers, devices, etc., refer to a material or device comprised of a compound semiconductor material according to the stoichiometric formula BwAlxInyGazN, where w+x+y+z is about 1 with 0≤w≤1, 0≤x≤1, 0≤y≤1, and 0≤z≤1. III-N materials, layers, or devices, can be formed or prepared by either directly growing on a suitable substrate (e.g., by metal organic chemical vapor deposition), or growing on a suitable substrate, detaching from the originally substrate, and bonding to other substrates.

As used herein, two or more contacts or other items such as conductive channels or components are said to be “electrically connected” if they are connected by a material which is sufficiently conducting to ensure that the electric potential at each of the contacts or other items is intended to be the same, e.g., is about the same, at all times under any bias conditions.

As used herein, “blocking a voltage” refers to the ability of a transistor, device, or component to prevent significant current, such as current that is greater than 0.001 times the operating current during regular conduction, from flowing through the transistor, device, or component when a voltage is applied across the transistor, device, or component. In other words, while a transistor, device, or component is blocking a voltage that is applied across it, the total current passing through the transistor, device, or component will not be greater than 0.001 times the operating current during regular conduction. Devices with off-state currents which are larger than this value exhibit high loss and low efficiency, and are typically not suitable for many applications.

As used herein, a “high-voltage device”, e.g., a high-voltage switching transistor, is an electronic device which is optimized for high-voltage switching applications. That is, when the transistor is off, it is capable of blocking high voltages, such as about 300V or higher, about 600V or higher, or about 1200V or higher, and when the transistor is on, it has a sufficiently low on-resistance (RON) for the application in which it is used, e.g., it experiences sufficiently low conduction loss when a substantial current passes through the device. A high-voltage device can at least be capable of blocking a voltage equal to the high-voltage supply or the maximum voltage in the circuit for which it is used. A high-voltage device may be capable of blocking 300V, 600V, 1200V, or other suitable blocking voltage required by the application. In other words, a high-voltage device can block all voltages between 0V and at least Vmax, where Vmaxis the maximum voltage that can be supplied by the circuit or power supply, and Vmaxcan for example be 300V, 600V, 1200V, or other suitable blocking voltage required by the application.

As used herein, a “III-Nitride” or “III-N device” is a device based on III-N materials. The III-N device can be designed to operate as an enhancement-mode (E-mode) transistor device, such that the threshold voltage of the device (i.e., the minimum voltage that must be applied to the gate relative to the source in order to turn the device on) is positive. Alternatively, the III-N device can be a depletion-mode (D-mode) device, having a negative threshold voltage. The III-N device can be a high-voltage device suitable for high voltage applications. In such a high-voltage device, when the device is biased off (e.g., the voltage on the gate relative to the source is less than the device threshold voltage), it is at least capable of supporting all source-drain voltages less than or equal to the high-voltage in the application in which the device is used, which for example may be 100V, 300V, 600V, 1200V, 1700V, or higher. When the high voltage device is biased on (e.g., the voltage on the gate relative to the source is greater than the device threshold voltage), it is able to conduct substantial current with a low on-voltage. The maximum allowable on-voltage is the maximum voltage that can be sustained in the application in which the device is used.

DETAILED DESCRIPTION

Many power switching applications require very high output currents, and thus the associated power switching circuits require switches which are capable of conducting large currents with minimal conduction losses and are also capable of switching large voltages with minimal switching losses. In applications in which very high output current levels are needed, one way to achieve the required current levels is to connect multiple switches in parallel and operate the parallel-connected switches as a single switch.

FIG. 3is a circuit diagram of an example switching circuit300, e.g., a half bridge, in which the high side switch304includes two switches322and324connected in parallel, and the low side switch308includes two switches326and328connected in parallel. Output node331of the gate driver302is coupled to the gates of switches322and324, and thereby switches both of these switches approximately simultaneously. Output node332of the gate driver is coupled to the sources of switches322and324, such that voltage signal applied by the gate driver302to the gates of switches322and324is referenced relative to their respective sources. Output node333of the gate driver302is coupled to the gates of switches326and328, and thereby switches both of these switches approximately simultaneously. Output node334of the gate driver is coupled to the sources of switches326and328, such that voltage signal applied by the gate driver302to the gates of switches326and328is referenced relative to their respective sources.

Output node331can be directly connected to the gates of switches322and324(not shown), or alternatively a resistive component321can be coupled between output node331and the gate of switch322, and resistive component323can be coupled between output node331and the gate of switch324. Output node333can be directly connected to the gates of switches326and328(not shown), or alternatively a resistive component325can be coupled between output node333and the gate of switch326and resistive component327can be coupled between output node333and the gate of switch328. Resistive components321,323,325, and327can, for example, be resistors or ferrite beads, which may help improve circuit stability.

A first pulse-width modulated (PWM) source354connected to a first input364of the gate driver302provides the timing for the on/off signals applied at output node331, and a second PWM source358connected to a second input368of the gate driver302provides the timing for the on/off signals applied at output node333. Inductor314is coupled (e.g., electrically connected) to the circuit at output node312. The entire circuit can be formed on a circuit board with printed wiring connections that electrically couple the components of the circuit.

Switches322,324,326, and328are capable of being operated at higher switching frequencies than some switches used in conventional high-voltage power switching circuits, such as switches implemented as silicon-based transistors (e.g., silicon-based MOSFETs or IGBTs). For example, switches322,324,326, and328can be III-N transistors, such as the III-N transistor shown inFIG. 4, which may be capable of being switched at higher frequencies than silicon-based MOSFETs or IGBTs without exhibiting substantial additional power loss or other instabilities during operation. As seen inFIG. 4, a III-Nitride high electron mobility transistor (HEMT) can include a substrate400(e.g., a silicon substrate), a III-N buffer layer402formed of a III-N semiconductor material such as AlN or AlGaN, a III-N channel layer406formed of a III-N semiconductor material such as GaN, a III-N barrier layer408formed of a III-N semiconductor material (e.g., AlGaN or AlN) having a larger bandgap than that of the III-N channel layer406, and a two-dimensional electron gas (2DEG) channel416formed in the III-N channel layer406adjacent to the III-N barrier layer408, the 2DEG channel416serving as the conductive channel of the transistor. The III-N HEMT further includes source and drain contacts410and412, respectively, which contact the 2DEG channel416. A gate electrode414, which is deposited between the source and drain contacts410and412, respectively, is used to modulate the conductivity of the channel in the region directly below the gate electrode414. Optionally, a gate insulator420is included between the gate electrode414and the underlying III-N semiconductor materials.

Referring back toFIG. 3, in many applications, it is preferable that switches304and308be provided as enhancement-mode devices, thereby requiring that switches322,324,326, and328each be provided as enhancement-mode devices. However, switching devices formed of single high-voltage enhancement-mode transistors can be difficult to fabricate reliably. For example, due at least partially to tight process tolerances, it can be difficult to design a III-N HEMT such as the device shown inFIG. 4such that it consistently and reliably operates as an enhancement-mode device with a positive threshold voltage. That is, even when a design is implemented for a III-N HEMT for which the resulting HEMT should be an enhancement-mode device, small variations in layer thicknesses, feature dimensions, etc., that typically occur can result in many of the devices either being depletion-mode devices or otherwise not exhibiting a high enough threshold voltage for reliable operation.

As an alternative to a single high-voltage enhancement-mode transistor, when enhancement-mode switches which can be operated at high switching frequencies are desired for switches322,324,326, and328, the switches can each be implemented as a hybrid device that includes a high-voltage depletion-mode (D-mode) transistor504and a low-voltage enhancement-mode (E-mode) transistor502, configured as shown inFIG. 5. The resulting hybrid device ofFIG. 5can be operated in the same way as a single high-voltage E-mode transistor, and in many cases achieves the same or similar output characteristics as a single high-voltage E-mode transistor. The source electrode506of the low-voltage E-mode transistor502and the gate electrode508of the high-voltage D-mode transistor504are both electrically connected together, for example with wire bonds, and together form the source510of the hybrid device. The gate electrode512of the low-voltage E-mode transistor502forms the gate514of the hybrid device. The drain electrode516of the high-voltage D-mode transistor504forms the drain518of the hybrid device. The source electrode520of the high-voltage D-mode transistor504is electrically connected to the drain electrode522of the low-voltage E-mode transistor502.

In particular implementations of the hybrid device ofFIG. 5, the hybrid device is implemented as a III-N device. In this case, the D-mode transistor504is a high-voltage III-N D-mode transistor (e.g., capable of blocking at least 200V while biased in the OFF state), and the E-mode transistor502is a low-voltage silicon-based E-mode transistor (e.g., cannot reliably block voltages greater than 100V while biased in the OFF state). Although such an implementation of a III-N switch utilizes a silicon-based transistor in the switch, because the silicon-based transistor is a low-voltage device, the switch can still be capable of being operated at the higher switching frequencies.

Referring back toFIG. 3, due to the use of III-N transistors (as inFIG. 4) or hybrid devices (as inFIG. 5), e.g., III-N hybrid devices, for switches322,324,326, and328, the switching circuit300illustrated inFIG. 3can be operated at higher switching frequencies than some conventional switching circuits implemented using silicon transistors. For example, the switching circuit300can be operated at a switching frequency of 30 kHz or higher, 50 kHz or higher, 80 kHz or higher, or up to 1 MHz or higher (i.e., during operation of the circuit, the switches can be switches at a frequency of 30 kHz or higher, 50 kHz or higher, 80 kHz or higher, or up to 1 MHz or higher). The high switching frequencies that can be utilized result at least partially because the switches322,324,326, and328can be switched at much higher switching speeds or slew rates than conventional switches. For example, when switches322,324,326, and328are switched on or off, the rate of change of voltage across the switches (typically referred to as the voltage switching rate or just the switching rate) can be greater than 40 Volts/nanosecond, e.g. in the range of 50-200 Volts/nanosecond, and the rate of change of current (typically referred to as the current switching rate) can be greater than 2 Amps/nanosecond, e.g. in the range of 3-10 Amps/nanosecond.

In the circuit300ofFIG. 3, when the switches322,324,326, and328are each encased in an individual package, such as the package shown inFIG. 1, and are switched at high frequencies and/or high switching rates, parasitic inductances introduced by the package leads along with intrinsic delays in each of the switches can lead to circuit instability. For example, although the gates of switches322and324are both electrically connected (or electrically coupled) to the same output node331of the gate driver302, parasitics and delays in the switches typically cause one of the switches to be switched a short time before the other (the same also being true for switches326and328). This can cause current from one of switching devices322or324to be coupled into the other switch rather than into inductor314immediately after switching, as indicated by the circulating current lines344and348shown inFIG. 3. This may lead to voltage overshoots and oscillations as well as circuit instability in the circuit300, and typically results in circuit failure. Hence, although the configuration ofFIG. 3allows for much larger output currents through inductor314than in a bridge circuit in which each switch304and308is formed of a single switch (rather than multiple switches connected in parallel), it can be very difficult to achieve stable circuit operation in the circuit300ofFIG. 3. Furthermore, although additional switches may be added in parallel with each of the parallel-connected switches in order to further increase the current output capabilities of the circuit, doing so further increases circuit parasitics and thereby further increases the voltage oscillations and instabilities in the circuit.

FIG. 6is a circuit diagram of an example switching circuit600in which two half bridge circuits660and670are connected in parallel to operate as a single half bridge circuit with a maximum output current that can be as high as two times the maximum output current of each of the individual half bridge circuits660and670. Each of the half bridge circuits660and670has an inductor664and674at its respective output, with output ends of inductors664and674each connected to the output612of the circuit600. The switches of half bridge circuit660are each driven by a first gate driver602, and the switches of half bridge circuit670are each driven by a second gate driver603. The outputs684and685of the gate drivers602and603which send control signals to the gates of high side switches604(in half bridge circuit660) and605(in half bridge circuit670) each receive their timing signals from a first common PWM source654which is connected to a first input694of the first gate driver602and to a first input695of the second gate driver603. The outputs688and689of the gate drivers602and603which send control signals to the gates of low side switches608(in half bridge circuit660) and609(in half bridge circuit670) each receive their timing signals from a second common PWM source658which is connected to a second input696of the first gate driver602and to a second input697of the second gate driver603.

In the circuit600ofFIG. 6, switches604and605are switched approximately simultaneously, and switches608and609are switched approximately simultaneously. Hence, half bridges660and670output approximately the same current at all times (other than short times before and after switching due to parasitics/delays, as previously described), and so the total maximum output current of circuit600can be as much as about two times that of each of half bridges660and670. However, the currents output by each of switches604and605are decoupled from one another by inductors664and674, as are the currents output by each of switches608and609(the total inductance between nodes680and690is the sum of the inductances of inductors664and674). As such, even if there exists a relative delay between the switching of the high side switches604and605or between the switching of the low side switches608and609, the increased voltage oscillations and instabilities that were described with respect to the circuit ofFIG. 3are not present or are substantially mitigated in circuit600. Thus, circuit600is capable of providing much higher output current than a conventional half bridge circuit while still allowing for reliable, stable circuit operation.

While the configuration of circuit600allows for a stable operation of a power switching circuit with very high current capabilities, it requires two output inductors664and674, as compared to a single inductor214/314in the circuits ofFIGS. 2 and 3. Inductors214,314,664, and674are quite large, for example in the range of about 20-200 μH or larger. Including two such inductors can substantially increase the size and cost of the circuit.

FIG. 7is a schematic diagram of a circuit700which is similar to that ofFIG. 6, except that the large output inductors664and674are replaced by a single large main output inductor714and a pair of smaller inversely coupled inductors762and772, connected as shown. The main output inductor714has a substantially larger inductance than each of the inversely coupled inductors762and772. For example, the inductance of main output inductor714can be at least two times, at least three times, at least five times, or at least ten times that of each of the inversely coupled inductors762and772.

Similar to circuit600inFIG. 6, circuit700inFIG. 7is capable of providing much higher output current than a conventional half bridge circuit while still allowing for reliable, stable circuit operation. However, circuit700has the added benefit of having one of the two large output inductors in the circuit ofFIG. 6replaced by a pair of substantially smaller inductors, thereby reducing the size and cost of the entire circuit.

Inductors762and772have approximately the same self inductance (e.g., the self inductance of inductor762can be within 2%, 5%, or 10% of that of inductor772) and are configured to be inversely coupled to one another, such that their coupling coefficient k is equal or close to −1, for example in the range of −0.9 to −1.0. As such, during circuit operation, the total inductance Lloopbetween nodes780and790(self inductance of each of inductors762and772, plus their respective mutual inductances) is approximately equal to four times the self inductance of each of inductors762and772. Simulations have shown that in many applications, inductors762and772can each have a self inductance that is less than 20% or less than 10% of that of main output inductor714and still substantially limit current flowing between nodes780and790during circuit operation.

FIG. 8illustrates a possible configuration for inductors762,772, and714. The main output inductor714is formed of a wire coiled around a first ferromagnetic core816. The inversely coupled inductors762and772are formed of a pair of wires wrapped in opposite directions around a second ferromagnetic core826. Because inductors762and772each have much smaller self inductance than that of inductor714, the second ferromagnetic core826may be smaller than the first ferromagnetic core816. As seen inFIG. 8, the ferromagnetic cores816and826may be toroid cores.

FIG. 9, which is a schematic diagram of a circuit900, illustrates how 2×N half bridges, where N is an integer, can be combined to operate as a single half bridge with an even larger maximum output current.FIG. 9illustrates the case where N=2, such that the outputs of 4 half bridge circuits are combined. The entire circuit900includes a single large main output inductor914. Each of the 4 half bridges includes a smaller inductor962/972/982/992at their respective outputs. Inductors962,972,982, and992are each inversely coupled to one another, such that their respective coupling coefficients are close to −1 (e.g., in the range of −0.9 to −1.0). As with the circuit700ofFIG. 7, circuit900inFIG. 9is capable of providing much higher output current than a conventional half bridge circuit while still allowing for reliable, stable circuit operation.

FIG. 10illustrates a possible configuration for the inversely coupled inductors962,972,982, and992ofFIG. 9. The inductors962,972,982, and992are all formed from a single ferromagnetic core1026. Core1026includes a first end portion1030, a second end portion1040, and 2×N segments1032,1034,1036, and1038extending from the first end portion1030to the second end portion1040. Inductor962is formed by coiling a first wire around the first segment1032, inductor972is formed by coiling a second wire around the second segment1034, inductor982is formed by coiling a third wire around the third segment1036, and inductor992is formed by coiling a fourth wire around the fourth segment1038.

FIG. 11is a schematic diagram of a circuit1100in which features of the circuits ofFIGS. 3 and 7are combined into a single circuit. As inFIG. 7, the circuit1100includes a pair of half bridges1160and1170, connected in parallel to operate as a single half bridge circuit with a maximum output current that can be as high as two times the maximum output current of each of the individual half bridge circuits1160and1170. The switches of the half bridges are each formed by paralleling two switches in order to increase the maximum output current of each switch, as inFIG. 3. The entire circuit1100includes a single large main output inductor1114, and each half bridge1160and1170includes a smaller inductor1162and1172at its respective output, where inductors1162and1172are inversely coupled to one another.

A method for operating the circuits ofFIGS. 6, 7, and 11which can further improve their efficiencies is as follows. During times where the output currents of the circuits are large, the half bridges operate in parallel, as previously described. During these high current time periods, losses are dominated by conduction loss through the switches, and so simultaneously operating two half bridges in parallel minimizes these losses. However, during times where the output currents of the circuits are small, conduction losses are small, and the total circuit loss is dominated by switching losses. During these low current time periods, one of the half bridges is turned off while the other is still operated. While this may slightly increase conduction losses during the low current time periods, switching losses, which are the dominant loss mechanisms during the low current time periods, are reduced by approximately a factor of two.

Similar methods can be applied to the circuit ofFIG. 9. For example, all 4 half bridges can be operated during time periods of very high current, 3 half bridges can be operated during periods of slightly lower current, 2 half bridges can be operated during times of even lower output current, and 1 half bridge can be operated during times when the output current is very low.

FIG. 12shows examples of the input and output voltage waveforms associated with the operation of the circuit700shown inFIG. 7. The horizontal axis is time, the vertical access is voltage, and the various voltages plotted inFIG. 12are each superimposed over one another and vertically offset with respect to each other. The gate driver input signal754(represented by waveform1202inFIG. 12) is applied to the first half bridge gate driver702at input node794and to the second half bridge gate driver703at input node795. There exists a first delay between application at the first gate driver702of an input voltage signal754(waveform1202) and issuance by the first gate driver at node784of a first gate driver output signal (waveform1204). There also exists a second delay between application at the second gate driver703of the input voltage signal754(waveform1202) and issuance by the second gate driver at node785of a second gate driver output signal (waveform1206). The first delay may be different than the second delay, where the difference is represented inFIG. 12by Δtp. Hence, the output signal timing of the first gate driver702at node784can be slightly different than the output signal timing of the second gate driver at node785. Waveforms1208and1210represent the resulting output voltages at output nodes780and790, respectively, as a function of time, and the difference between these output voltages as a function of time is represented by waveform1212. The difference (represented by waveform1212) between the voltage Vds1at the output node780of the first half bridge circuit760and the voltage Vds2at the output node790of the second half bridge circuit770due to the Δtpcan cause a circulating current between output780of the first half bridge circuit and output790of the second half bridge circuit, where the relative magnitude of the circulating current as a function of time is given by waveform1214. The small inductors762and772act to limit this circulating current. The magnitude of the circulating current is given by icirculating=Vdc*Δtpwhere Lloopis described previously, and Vdcis the input voltage at node706. For a typical circuit operation of 400Vdc, with Δtpbeing less than 10 ns, the circulating current is limited to less than 1 A. For this configuration, the total inductance of the inversely coupled inductors762and772can be about 4 μH. The large inductor714acts to control the output current ripple. Typically, the current ripple is 20% to 30% of the rated output current.

FIG. 13shows a plot1300of output waveforms during operation of the circuits inFIGS. 6, 7, and 11described above. Waveform I(L1) shows time dependence of a first output current through the first small inductor664,762or1162. Waveform I(L2) shows time dependence of a second output current through the second small inductor674,772or1172. Waveform I(L1)−I(L2) shows time dependence of a difference between the first and second output currents. Waveform I(Lf) shows time dependence of an output current at the node612or an output current through the large inductor714or1114.

In general, each of the first and second half bridge circuits of the circuits inFIGS. 6, 7, and 11can be in either an ON state or an OFF state. In the example illustrated inFIG. 13, during a first time period tP1(before 2.5 ms), both the first and second half bridge circuits are operating (i.e., are being maintained in their respective ON states) to share the total output current having a first current level (e.g., of 17 amps). The small inductors help to balance the current and keep the circulating current small. At 2.5 ms the output current drops to second current level (e.g., of 8.5 amps). In response to the foregoing drop in output current, the second half bridge is turned off (and, thus, the second half bridge transitions from its ON state to its OFF state). As such, during a second time period tP2(after 2.5 ms), only the first half bridge is operated, and the second half bridge is maintained in its OFF state. Since the current during the second time period is small compared to the current during the first time period, the switching loss becomes dominant. To minimize switching losses, the second half bridge is kept off, and the total current is output by the first half bridge. There remains a small current charging and discharging the output capacitance of the GaN HEMTs of the second half bridge. However, since the second half bridge remains off, this will not result in switching losses in the second half bridge. Thus, the method of operating the circuit as described above improves the efficiency of the circuits inFIGS. 6, 7, and 11during low power conditions.

A number of implementations have been described. Nevertheless, it will be understood that various modifications may be made without departing from the spirit and scope of the techniques and devices described herein. For example, in each of the circuits described herein, when the circuit is connected to and used to control or drive a load which has a large inductance, for example when the load is an electric motor, a separate main output inductor (such as inductors314,664,674,714,914, and1114) may not be needed. Instead, the load inductance functions as the output inductance of the circuit. Additionally, the switches of any of the circuits described herein can be formed of III-Nitride devices, and can be switched at high frequencies and/or high current and voltage switching rates, similar to switches322,324,326, and328ofFIG. 3. That is, the same devices used for switches322,324,326, and328inFIG. 3can be used for the switches of any of the other circuits described herein. Furthermore, circuit nodes referred to as “output nodes” may also be input nodes for the circuit. For example, when the circuit is used in applications where the output current is bidirectional, the output node will function as both an input node and an output node during operation of the circuit. Accordingly, other implementations are within the scope of the following claims.