Active clamp flyback converter capable of switching operation modes

A power converter using an active-clamp flyback topology has a low-side switch, a high-side switch and a control circuit. The low-side switch connects a primary winding of a transformer to an input ground line, and the high-side switch is connected in series with a capacitor to form an active-clamp circuit connected in parallel with the primary winding. The control circuit provides high-side and low-side signals to the high-side and the low-side switches respectively, in response to a current-sense signal and a compensation signal. The control circuit is configured to operate the power converter in one of operation modes including a complementary mode and a non-complementary mode. When operated in the complementary mode, the high-side signal and the low-side signal are substantially complementary to each other, and the control circuit exits the complementary mode in response to the current-sense signal to enter the non-complementary mode.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims priority to and the benefit of Taiwan Application Series Number 107132836 filed on Sep. 18, 2018, which is incorporated by reference in its entirety.

BACKGROUND

The present disclosure relates generally to power converters using an active-clamp flyback topology and control methods thereof, and, more particularly, to control methods that operates a power converter using an active-clamp flyback topology in one of several operation modes.

Flyback power converters have been widely adopted in the power supplies of home appliances, computers, battery chargers for example. To further improve the efficiency of a flyback power converter, an active-clamp topology has been introduced, using an active-clamp circuit to replace a snubber, which is commonly used to consume the energy stored by the leakage inductance of a primary winding of a transformer in the flyback power converter. A power converter using an active-clamp flyback topology is named an ACF power converter in short. ACF power converter is well known to have outstanding power efficiency when a load of the ACF power converter is heavy. However, the power efficiency deteriorates seriously when the load is light, substantially due to the significant circulated current continuously going back and forth through a primary winding of the ACF power converter.

Texas Instruments introduces UCC28780, a controller used in an ACF power converter. UCC28780 is capable of operating in one of four operation modes, basically in response to the state of the load of the ACF power converter. The circuit application datasheet of USCC28780, however, still shows a bleeder resistor connected in parallel with a capacitor of an active-clamp circuit, to slowly release the energy accumulated on the capacitor. Obviously, as the bleeder resistor acts as an energy eater, USCC28780 does completely employ the benefit of the active-clamp circuit.

Furthermore, system designers of conventional ACF power converters usually confront the difficulties in dealing with electromagnetic interference (EMI) and audible noise.

DETAILED DESCRIPTION

FIG. 1shows ACF power converter10according embodiments of the invention. Bridge rectifier BD performs full-wave rectification for alternating-current voltage VACfrom a power grid, to provide input power lines IN and GNDI. Input voltage VINat input power line IN is positive in reference to the voltage at input power line GNDI, which is referred to as input ground GNDI hereinafter. Transformer TF includes primary winding LP, secondary winding LS and auxiliary winding LA, inductively coupled to each other. Primary wilding LP, low-side switch LSS, and current-sense resistor RCS are connected in series between input power line IN and input ground GNDI. Low-side switch LSS and current-sense resistor connect primary wilding LP to input ground GNDI. Current-sense resistor RCS provides current-sense signal VCSto power controller14, via current-sense pin CS. High-side switch HSS connects in series with capacitor CAC to form active-clamp circuit ACC, which connects in parallel with primary winding LP. When low-side switch LSS is turned ON, current-sense signal VCSis representative of inductor current IMflowing through primary winding LP.

Power controller14, an integrated circuit in an embodiment, controls driver DVR, which could be another integrated circuit in one embodiment of the invention, to provide to high-side switch HSS and low-side switch LSS high-side signal DRVHSand low-side signal DRVLSrespectively. High-side switch HSS and low-side switch LSS could be high-voltage GaN transistors or MOS transistors in some embodiments of the invention. In some embodiments of the invention, driver DVR, high-side switch HSS and low-side switch, individually manufactured, are all integrated into one integrated-circuit package. Power controller14and driver DVR, in combination, could act as a control circuit to provide high-side signal DRVHSand low-side signal DRVHS, controlling high-side switch HSS and low-side switch LSS respectively.

By turning ON and OFF high-side switch HSS and low-side switch LSS, power controller14causes inductor current IMto vary, so that secondary winding LS reflectively generates alternating-current voltage, which is then rectified to provide output power lines OUT and GNDO. Output voltage VOUTat output power line OUT is positive in reference to the voltage at output power line GNDO, which is referred to as output ground GNDO hereinafter. Output voltage VOUTprovides output current IOto charge or power load13, a rechargeable battery for instance.

To regulate output voltage VOUT, power controller14acquires negative feedback control from the combination of error amplifier EA, optical coupler OPT and compensation capacitor CCOMP. At the secondary side, error amplifier EA compares output voltage VOUTwith target voltage VREF-TAR, to control compensation signal VCOMPon compensation capacitor CCOMP at the primary side, via optical coupler OPT that provides DC isolation between the primary and secondary sides. For example, when output voltage VOUTexceeds target voltage VREF-TAR, compensation signal VCOMPgoes down and the power that ACF power converter10converts to load13reduces, so as to regulate output voltage VOUTabout at target voltage VREF-TAR.

AC voltage is induced across auxiliary winding LA at the primary side, and rectified to generate operating voltage VCCat power input pin VCC of power controller14, where operating voltage VCCsubstantially supplies the power needed for the operation of power controller14. Resisters RA and RB, connected in series, form a voltage-dividing circuit, and the joint between resisters RA and RB is connected to feedback pin FB of power controller14. Feedback voltage VFBis at feedback pin FB.

In one embodiment of the invention, power controller14adaptively switches to operate in one of two operation modes, but the invention is not limited to, however. In another embodiment of the invention, power controller14adaptively switches to operate in one of three operation modes.FIG. 2demonstrates two operation modes, one called hereinafter the ACF mode and the other the flyback mode. Generally speaking, the ACF mode is used when load13is in a heavy state, and the flyback mode is used when load13is in a light state or there is no load.

As demonstrated inFIG. 2, when operated in the ACF mode, power controller14is configured to perform: 1) making high-side signal DRVHSand low-side signal DRVLSsubstantially complementary to each other, and high-side switch HSS and low-side switch LSS perform ZVS; 2) fixing but jittering switching frequency fCYC; and 3) modulating signal peak VCS-PEAKin response to compensation signal VCOMP, where signal peak VCS-PEAKis a local maximum of current-sense signal VCSand will be detailed later. Power controller14, when operated in the ACF mode, checks whether positive-current duration TON-Pand negative-current duration TON-Nfit a predetermined relationship to exit the ACF mode and enter the flyback mode. Positive-current duration TON-Pand negative-current duration TON-Nrepresent durations when current-sense signal VCSis positive and negative respectively, especially when low-side switch LSS is turned ON.

In comparison with compensation signal VCOMP, a predetermined relationship between positive-current duration TON-Pand negative-current duration TON-Ncould be more suitable to indicate the state of load13when power controller14is operated in the ACF mode, and could be used as an indicator to switch operation modes.

When operated in the flyback mode, power controller14is configured to perform: 1) keeping high-side switch HSS substantially turned OFF; 2) making signal peak VCS-PEAKabout a constant; and 3) modulating and jittering switching frequency fCYCin response to compensation VCOMPMeanwhile, power controller14monitors whether the compensation signal VCOMPexceeds a reference voltage VCOMP-REF, to exit the flyback mode and enter the ACF mode.

Please refer toFIGS. 2 and 3A, whereFIG. 3Ashows some signal waveforms when ACF power converter10is operated in the ACF mode. From top to bottom, signal waveforms inFIG. 3Aare clock signal CLK internally generated by power controller14, high-side signal DRVHS, low-side signal DRVLS, current-sense signal VCS, terminal voltage VSWat the joint between high-side switch HSS and low-side switch LSS, and winding voltage VAUXacross auxiliary winding LA.

Power controller14has in itself a clock generator to provide clock signal CLK, capable of defining switching cycle TCYC, the reciprocal of which is switching frequency fCYCof low-side signal DRVLS.

When power controller14is operated in the ACF mode, switching frequency fCYCis about a constant independent from compensation signal VCOMP, and might optionally be jittered. For example, during the time when power controller14is operated in the ACF mode, switching frequency fCYCis independent from compensation signal VCOMP, centers at 200 kHz and varies periodically between 190 kHz and 210 kHz with a jittering frequency of 400 Hz, capable of solving electromagnetic interference (EMI) issues.

When operated in the ACF mode, power controller14makes high-side signal DRVHSand low-side signal DRVLSsubstantially complementary, as demonstrated by the waveforms inFIG. 3A. The ACF mode is a complementary mode, therefore. When high-side signal DRVHSturns from logic “1” to logic “0”, dead time TDFfollows and then low-side signal DRVLScomplementarily turns from logic “0” to logic “1”. Similarly, when low-side signal DRVLSturns from logic “1” to logic “0”, dead time TDRfollows and then high-side signal DRVHScomplementarily turns from logic “0” to logic “1”.

Dead times TDFand TDRare short but necessary. Their existence prevents the short through happening when both high-side switch HSS and low-side switch LSS are turned ON at the same time, and also helps high-side switch HSS and low-side switch LSS both to perform zero-voltage switching (ZVS). It is known in the art that low-side signal DRVLSand high-side signal DRVHSare substantially complementary to each other even though they both are “0” in logic briefly during dead times TDFand TDR. For example, when low-side signal DRVLSturns from logic “1” into logic “0”, winding voltage VAUXraises from a negative voltage VNand approaches to a positive voltage VP, while terminal voltage VSWraises from 0V to approach voltage VCP, as shown inFIG. 3A. Voltage VCPis the voltage at the joint between high-side switch HSS and capacitor CAC. Power controller14senses winding voltage VAUXby detecting feedback voltage VFB. Once it is found that winding voltage VAUXis about the positive voltage VP, it can be determined that terminal voltage VSWis about voltage VCP, and accordingly power controller14changes high-side signal DRVHSfrom “0” into “1” in logic, performing ZVS at high-side switch HSS. Similarly, when high-side signal DRVHSturns from logic “1” into logic “0”, power controller14could detect winding voltage VAUXto know whether terminal voltage VSWdrops to be about 0V, and when it is determined that the terminal voltage VSWis about 0V, changes low-side signal DRVLSfrom “0” into “1” in logic, performing ZVS at low-side switch LSS.

Low-side ON time TON-Lrefers to the period of time when low-side signal DRVLSis “1” in logic, or the period of time when low-side switch LSS conducts current. Analogously, high-side ON time TON-His the period of time when high-side signal DRVHSis “1” in logic, or the period of time when high-side switch HSS conducts current.

FIG. 3Aalso shows how power controller14modulates signal peak VCS-PEAK. InFIG. 3Aattenuated compensation signal VCOMP-SCis in a linear correlation with compensation signal VCOMP. For example, VCOMP-SC=K*VCOMP, where K is a constant between 0 and 1. A voltage divider comprising resistors connected in series, for example, divides compensation signal VCOMPto generate attenuated compensation signal VCOMP-SC. Attenuated compensation signal VCOMP-SCcontrols signal peak VCS-PEAK. During low-side ON time TON-L, current-sense signal VCSincreases over time, and when determining that current-sense signal VCSexceeds attenuated compensation signal VCOMP-SC, power controller14ends low-side ON time TON-Land, further after a delay of dead time TDR, starts high-side ON time TON-H. During dead time TDR, current-sense signal VCSdrops, and the local maximum of current-sense signal VCSbecomes signal peak VCS-PEAK, which is about attenuated compensation signal VCOMP-SC, as shown inFIG. 3A. Accordingly, power controller14modulates signal peak VCS-PEAKin response to compensation signal VCOMP. In comparison with the switching cycle at the left portion ofFIG. 3A, the one at the right portion orFIG. 3Ahas a larger attenuated compensation VCOMP-SC, so signal peak VCS-PEAKis larger in the right portion orFIG. 3A. In other words, power controller14makes signal peak VCS-PEAKin a linear correlation with compensation signal VCOMP.

A switching cycle TCYCshown inFIG. 3Aconsists of dead time TDF, low-side ON time TON-L, dead time TDRand high-side ON time TON-H. A pulse of clock signal CLK ends high-side ON time TON-Hand starts dead time TDF, which ends at about the moment when terminal voltage VSWis 0V. Low-side ON time TON-Lfollows dead time TDF, and ends when current-sense signal VCSexceeds attenuated compensation signal VCOMP-SCDead time TDRfollows low-side ON time TON-L, and ends when terminal voltage VSWis about voltage VCP fto start high-side ON time TON-HA next pulse of clock signal CLK ends high-side ON time TON-Hand also concludes a switching cycle TCYC.

When operated at the ACF mode, inductor current IMflowing through primary winding LP does not stop at 0 A, always changing.

Please refer toFIGS. 2 and 3B, whereFIG. 3Bshows some signal waveforms when ACF power converter10is operated in the flyback mode. From top to bottom, signal waveforms inFIG. 3Bare clock signal CLK, high-side signal DRVHS, low-side signal DRVHS, current-sense signal VCS, terminal voltage VSW, and winding voltage VAUX.

As shown inFIG. 3B, when operated in the flyback mode, high-side signal DRVHSis substantially kept as “0” in logic to turn high-side switch HSS OFF, and low-side signal DRVLSperiodically switches low-side switch LSS. The flyback mode is a non-complementary mode because high-side signal DRVLSand low-side signal DRVLSare not complementary to each other, obviously.

Shown inFIG. 3B, a pulse of clock signal CLK starts a switching cycle TCYCand low-side ON time TON-Las well. When current-sense signal VCSexceeds a constant reference voltage VCS-REF, low-side ON time TON-Lends and demagnetization time TDMGstarts. Reference voltage VCS-REFis independent to compensation signal VCOMPDuring demagnetization time TDMG, secondary winding LS releases energy to build up output voltage VOUT. Demagnetization time TDMGcomes to an end when secondary winding LS completely depletes the energy it carries, so terminal voltage VSWstarts oscillating, and oscillation time TOSCbegins, as shown inFIG. 3B. A next pulse of clock signal CLK concludes both oscillation time TOSCand a switching cycle TCYC. When operated in the flyback cycle, a switching cycle time TCYCconsists of low-side ON time TON-L, demagnetization time TDMGand oscillation time TOSC.

InFIG. 3B, when operated in the flyback mode, peak signal VCS-PEAKis independent to the variation of attenuated compensation signal VCOMP-SCor compensation signal VCOMP, and is about a constant substantially equal to reference voltage VCS-REF.

When operated in the flyback mode, the clock generator providing clock signal CLK is controlled by compensation signal VCOMP. By comparing the left and the right portions ofFIG. 3B, it can be found that the lower attenuated compensation signal VCOMP-SCthe longer switching cycle TCYC.

When power controller14is operated in the flyback mode, switching frequency fCYC, the reciprocal of switching cycle TCYC, depends on compensation signal VCOMP, and might optionally be jittered to solve EMI issues. For example, during the time when power controller14is operated in the flyback mode, switching frequency fCYCcenters at an average frequency and varies periodically between upper and lower frequencies, where the average frequency is a function of compensation signal VCOMP.

Even thoughFIG. 3Bshows that high-side switch HSS is constantly turned OFF, the invention is not limited to however. In another embodiment of the invention, when power controller14is operated in the flyback mode, high-side switch HSS is not turned ON during low-side ON time TON-Land demagnetization time TDMG, but is briefly turned ON in a period of time within oscillation time TOSC, to release some electric energy stored in capacitor CAC.

The flyback mode is a discontinuous conduction mode (DCM), because inductor current IMflowing through primary winding LP stays at 0 A sometimes.

When operated in the flyback mode, if power controller14determines that compensation signal VCOMPexceeds a reference voltage VCOMP-REFpower controller14exits the flyback mode and enters the ACF mode.

FIG. 4enlarges the waveform of current-sense signal VCSduring low-side ON time TON-L. When operated in the ACF mode, inductor current IMthrough primary winding LP might be negative at the beginning of low-side ON time TON-L, so current-sense signal VCSis negative in that beginning. During low-side ON time TON-L, as input voltage VINconstantly increases the magnetic energy stored by primary winding LP, current-sense signal VCSincreases linearly over time until current-sense signal VCSexceeds attenuated compensation signal VCOMP-SCShown inFIG. 4, negative-current duration TON-Nrefers to the period of time when current-sense signal VCSis negative, and positive-current duration TON-Pthe period of time when it is positive. Only if positive-current duration TON-Pis longer than negative-current duration TON-N, ACF power converter10is transferring and supplying energy to output voltage VOUT. From another perspective of view, if positive-current duration TON-Pis very close to negative-current duration TON-Nand the compensation signal VCOMPstays unchanged, it implies that load13is not heavy anymore, and should be a middle load or a light load.

It can be found fromFIG. 4that compensation signal VCOMPor attenuated compensation signal VCOMP-SC, which are usually used to indicate the status of load13, cannot represent the status of load13anymore, basically due to the existence of negative-current duration TON-N. Therefore, it is a better choice to select positive-current duration TON-Pand negative-current duration TON-Nas indicators, instead of compensation signal VCOMP, for determining whether to exit the ACF mode.

As shown inFIG. 2, in one embodiment of the invention, power controller14checks whether positive-current duration TON-Pand negative-current duration TON-Nhave a predetermined relationship therebetween, to exit the ACF mode and enter the flyback mode. For example, when TON-P<TON-N+KT, power controller14exits the ACF mode and enters the flyback mode, where KTis a positive constant. The predetermined relationship is not limited to the comparison between positive-current duration TON-Pand negative-current duration TON-N. In another embodiment of the invention, for example, power controller14checks energization duty cycle DON-P, referring to TON-P/(TON-P+TON-N), to see if it is smaller than a predetermined value, so as to exit the ACF mode and enter the flyback mode.

In one embodiment of the invention, power controller14exits the ACF mode and enters the flyback mode right after the switching cycle in which positive-current duration TON-Pand negative-current duration TON-Nare found to have the predetermined relationship, but this invention is not limited to. In another embodiment of the invention, power controller14delays to exit the ACF mode and enter the flyback mode until positive-current duration TON-Pand negative-current duration TON-Nhave continuously been found to have the predetermined relationship for a predetermined time period, 1 ms for example. This delay is especially beneficial during the test of load transient response. Supposedly this delay is 1 ms, and, under a test of load transient response, the status when load13is a light load does not last more than 1 ms before load13switches to become a heavy load. Under this test of load transient response, power controller14will continue to be operated in the ACF mode when load13briefly changes into a light load, and ACF power converter10expectedly has better transient response and more stable output voltage VOUT.

FIG. 5Ashows the relationship between switching frequency fCYCand compensation signal VCOMPfor ACF power converter10. When operated in the ACF mode and in the flyback back, the relationship is demonstrated by curves CfCYC-ACFand CfCYC-FLY, respectively. Curve CfCYC-ACFclearly shows that switching frequency fCYCis a constant fHwhen operated in the ACF mode, and is independent from compensation signal VCOMPCurve CfCYC-FLYshows that when compensation signal VCOMPis between 4.3V and 0.7V switching frequency fCYCand compensation signal VCOMPhave a positive linear correlation with each other, meaning switching frequency fCYCincreases linearly as compensation signal VCOMPincreases. In case the embodiment inFIG. 1has a function of frequency jittering, curves CfCYC-ACFand CfCYC-FLYrepresent averages of switching frequency fCYCwhen it is jittered during the ACF mode and the flyback mode respectively.

It is also shown inFIG. 5Athat power controller14is operated in a burst mode when compensation signal VCOMPis around 0.5V, no matter which operation mode it was operated in previously. The burst mode can reduce the switching loss of high-side switch HSS and low-side switch LSS, and possibly increases the power conversion efficiency when supplying power to a light load or no load. If output current IOis positive but very little, compensation signal VCOMPcould go below 0.5V, causing power controller14to constantly turn OFF high-side switch HSS and low-side switch LSS and resulting in switching frequency fCYCequal to 0, no power conversion at all. As power conversion pauses while output current IOcontinues, output voltage VOUTdecreases and compensation signal VCOMPwill go upward over time. Once compensation signal VCOMPexceeds 0.7V, power controller14resumes to operate in the flyback mode or the ACF mode that it was operated in before the power conversion paused, supplying power to output voltage VOUT. If output current IOis still so little that the energy the ACF power converter10supplies to output voltage VOUTexceeds the energy that load13consumes, output voltage VOUTwill go upward and compensation signal VCOMPeventually will go below 0.5V again, causing power conversion to pause once again. Therefore, if load13is always little, switching frequency fCYCwill alternate between being 0 Hz for a period of time and being non-zero Hz for another period of time. This kind of operation mode is known as a burst mode.

FIG. 5Bdemonstrates the relationship between signal peak VCS-PEAKand compensation signal VCOMPregarding to the embodiment ofFIG. 1. When operated in the ACF mode, signal peak VCS-PEAKand compensation signal VCOMPhave a relationship shown by curve CVCS-P-ACF; when operated in the flyback mode, they have a relationship shown by curve CVCS-P-FLY, Curve CVCS-P-ACFindicates a positive, linear correlation between signal peak VCS-PEAKand compensation signal VCOMP, the higher compensation signal VCOMPthe higher signal peak VCS-PEAKCurve CVCS-P-FLYindicates signal peak VCS-PEAKas a constant VCS-REFindependent from compensation signal VCOMP.

FIG. 5Cdemonstrates the graph of current IOvs compensation signal VCOMPwhen the embodiment ofFIG. 1stays on a steady state, and the mode switching between the ACF mode and the flyback mode as well. When operated in the ACF mode, the relationship between output current IOand compensation signal VCOMPis represented by curve CIO-ACF; when operated in the flyback mode, it is represented by curve CIO-FLY. It is supposed that output current IOof ACF power converter10is initially below reference current IO-2, and, according toFIG. 5C, power controller14should be operated in the flyback mode. When output current IOvaries, compensation signal VCOMPchanges accordingly, following curve CIO-FLY. In case that output current IOsteadily increases to exceed reference current IO-1, power controller14determines that compensation signal VCOMPis larger than reference voltage VCOMP-REF, so it exits the flyback mode and enters the ACF mode. Once it enters the ACF mode, compensation signal VCOMPincreases dramatically to approach to the value corresponding to reference current IO-1on curve CIO-ACF. Now when output current IOvaries, compensation signal VCOMPchanges accordingly, following curve CIO-ACFIn case that power controller14determines that positive-current duration TON-Pand negative-current duration TON-Nhave reached the predetermined relationship, output current IOis about reference current IO-2, and power controller14exits the ACF mode to enter the flyback mode. Due to the operation mode switching from the ACF mode to the flyback mode, compensation signal VCOMPdecreases dramatically to approach to the value corresponding to reference current IO-2on curve CIO-FLY.

FIG. 6demonstrates consecutive switching cycles TCYCwhen ACF power converter10inFIG. 1is operated in the flyback mode. As shown inFIG. 6, low-side signal DRVLSswitches low-side switch LSS to continuously and periodically generate N switching cycles TCYC, where N is 8 for example, an integer bigger than 1.

The waveforms inFIG. 6from top to bottom are clock signal CLK, high-side signal DRVHS, low-side signal DRVLS, current-sense signal VCS, terminal voltage VSW, blank signal SBLAN, and count CNT.

Blank signal SBLANgenerated internally in power controller14defines blanking time TBLAN, which represents the minimum cycle time of the present switching cycle TCYC. Only when blanking time TBLANelapses, the current switching cycle TCYCcan conclude and a next switching cycle TCYCcan start. Blanking time TBLANis determined by load13for example. In one embodiment, blanking time TBLANis generated in response to compensation signal VCOMP, and the relationship of maximum frequency fBLAN, the reciprocal of blanking time TBLAN, versus compensation signal VCOMPcould be represented by curve CFCYC-FLYinFIG. 5A.

Power controller14could have a counter to record count CNT of the switching cycles TCYC. When it is determined that N switching cycles TCYChave appeared, the counter is reset to make count CNT1, as shown inFIG. 6, to restart count CNT.

FIG. 7demonstrates control method60in use of power controller14. When count CNT is smaller than N, meaning the current switching cycle must be one of the first N−1 switching cycles, step62of control method60, which checks whether the count CNT is N, will generate a negative result, and control method60proceeds to steps for a normal flyback cycle. In other words, each of the first N−1 switching cycles is deemed as a normal flyback cycle. When the count CNT is N, meaning the current switching cycle must be the Nth switching cycle, step62of control method60will generate a positive result, and control method60proceeds to steps for a modified flyback cycle. The Nth switching cycle is deemed as a modified flyback cycle. The count CNT is reset to be 1 in the end of the Nth switching cycle.

FIGS. 6 and 7show that only one of N consecutive switching cycles TCYCis a modified flyback cycle, and the rest are normal flyback cycles, but the invention is not limited to. According to embodiments of the invention, several consecutive ones of N consecutive switching cycles are modified flyback cycles and the rest are normal flyback cycles.

Taking the demonstration inFIG. 6as an example, a difference between a normal flyback cycle and a modified flyback cycle can be found by scrutinizing the waveform of high-side signal DRVHSWithin a normal flyback cycle, high-side signal DRVHSis always “0” in logic, keeping high-side switch HSS constantly turned OFF. Nevertheless, within a modified flyback cycle, even though high-side signal DRVHSstays most of time at “0” in logic, it becomes “1” in logic shortly about at the end of the modified flyback cycle, turning ON high-side switch HSS for a short period of time. Accordingly, a switching cycle TCYCfor a modified flyback cycle includes high-side ON time TON-H, as shown by the Nth switching cycle inFIG. 6.

Since high-side switch HSS is always turned OFF within a normal flyback cycle, the energy that the leakage inductance of primary winding LP is energized during low-side ON time TON-Lwill accumulate on capacitor CAC, so voltage VCPincreases switching cycle by switching cycle. Each modified flyback cycle, due to the brief high-side ON time TON-H, could release a portion of the energy to output voltage VOUT, to increase the conversion efficiency. At the same time, voltage VCPcould accordingly reduce, avoiding low-side switch LSS from being damaged by an over-high voltage VCPthat stresses low-side switch LSS when low-side switch LSS is turned OFF.

According to embodiments of the invention, an active-clamp circuit needs a bleeder resistor no more, because voltage VCPcould decrease within a modified flyback cycle, so power conversion could be improved and manufacturing cost reduced. As demonstrated by ACF power converter10inFIG. 1, active-clamp circuit ACC is a no-loss active-clamp circuit because it includes no bleeder resistor.

Referring toFIG. 7, for a normal flyback cycle, step64a, using low-side signal DRVLS, turns ON low-side switch LSS to generate low-side ON time TON-Lwhile making signal peak VCS-PEAKa constant. Most of the signal waveforms during the 1stswitching cycle TCYCinFIG. 6, for example, are self-explanatory in light ofFIG. 3Band the related teaching. Blanking time TBLANstarts at the same time when low-side ON time TON-Lstarts, and has a length in response to load13. For example, the lighter load13the longer blanking time TBLAN. Within the 1stswitching cycle TCYC, blanking time TBLANcovers low-side ON time TON-L, demagnetization time TDMG, and a portion of oscillation time TOSCTerminal voltage VSWoscillates during oscillation time TOSCwithin the 1stswitching cycle TCYC, producing peaks PK1, PK2and valleys VY1, VY2and VY3.

Step66ainFIG. 7waits until the end of blanking time TBLANFIG. 6illustrates in the 1stswitching cycle TCYCthat blanking time TBLANends about after the occurrence of peak PK2.

Step68inFIG. 7flows step66a, detecting whether a valley of terminal voltage VSWhappens. Step70, following when it is determined that a valley happens, increases count CNT by 1 and concludes the current normal flyback cycle. Within the 1stswitching cycle TCYCinFIG. 1, for example, valley VY3appears at moment tDET, so clock signal CLK concludes the 1stswitching cycle TCYC, count CNT increases by 1, and the 2ndswitching cycle TCYCstarts.

Shown inFIG. 7, steps64band66bfor a modified flyback cycle are the same with steps64aand66arespectively, and are not detailed for brevity. The Nth switching cycle TCYCshown inFIG. 6is a modified flyback cycle, where blanking time TBLANcovers low-side ON time TON-L, demagnetization time TDMG, and portion of oscillation time TOSC. Terminal voltage VSWoscillates during oscillation time TOSCwithin the Nth switching cycle TCYC, producing peaks PK1, PK2, PK3and valleys VY1, VY2and VY3

Step72inFIG. 7follows step66b, detecting whether a peak of terminal voltage VSWhappens. Step74, following when it is determined that a peak happens, turns ON high-side switch HSS, starting high-side ON time TON-H. As shown by the Nth switching cycle TCYCinFIG. 6, peak PK3is the 1stpeak after the end of blanking time TBLAN, so high-side ON time TON-Hstarts at about the moment when peak PK3appears. During high-side ON time TON-H, voltage VCPat the joint between high-side switch HSS and capacitor CAC might decrease slightly because voltage VCPenergizes primary winding LP.

According to some embodiments of the invention, one modified flyback cycle has only one high-side ON time TON-H, and it appears only after the end of blanking time TBLAN, as exemplified byFIG. 6. This invention is not limited to however. Some embodiments of the invention might have more than one high-side ON time TON-Hwithin one modified flyback cycle.

The duration of high-side ON time TON-Hin each modified flyback cycle might be a predetermined constant according to embodiments of the invention. But this invention is not limited to. Some embodiments of the invention may have the duration of high-side ON time TON-Hdetermined in response to voltage VCPat the joint between high-side switch HSS and capacitor CAC, while power controller14detects winding voltage VAUXvia feedback pin FB to indirectly detect voltage VCP. For example, if power controller14, during high-side ON time TON-H, finds voltage VCPis below a reference value, then power controller14ends high-side ON time TON-Hin a modified flyback cycle.

Step76inFIG. 7, following step74after the end of high-side ON time TON-H, generates dead time TDFand then makes low-side signal DRVLSto turn into “1” in logic from “0” at the moment when terminal voltage VSWis about 0V. In other words, step76makes low-side switch LSS perform ZVS. Step78follows step76, concluding the Nth switching cycle TCYC, and resetting count CNT to be 1, so as to let the next switching cycle TCYCstart.

From the embodiment shown byFIGS. 6 and 7, ACF power converter10acts like a quasi-resonant power converter when it is operated in a flyback mode, because a normal flyback cycle and a modified flyback cycle each ends at about the moment when a valley of terminal voltage VSWappears, performing valley switching that is capable of reducing switching loss. This invention is not limited to however. It is not necessary for ACF power converter10to perform valley switching when operated in a flyback mode. For example, some embodiments of the invention might skip step68inFIG. 7, and start a next switching cycle right after the end of blanking time TBLAN.

Even thoughFIGS. 6 and 7show that high-side ON time TON-Hin a modified flyback cycle starts at about the moment when a peak appears, but this invention is not limited to. Some embodiments of the invention might have step72inFIG. 7skipped or modified. Some embodiments of the invention have step72modified to detect a next valley after the end of blanking time TBLANand start high-side ON time TON-Hat about the moment when the next valley appears, for example. Other embodiments of the invention nevertheless have step72skipped, to start high-side ON time TON-Hright after the end of blanking time TBLAN.

N is a constant integer according to embodiments of the invention, but this invention is not limited to. N might be adaptively changed in some embodiments of the invention. For example, power controller14could detect voltage VCP, via the help of feedback pin FB and auxiliary winding LA, during high-side ON time TON-H. Voltage VCPis the voltage at an end of primary winding LP when high-side switch HSS is turned ON. If voltage VCPis higher than a top boundary of a predetermined acceptable range, N seems too large and is going to decrease by 1 at the end of the Nth switching cycle, implying the increased frequency for a modified flyback cycle to appear. On the other hand, if voltage VCPis lower than a bottom boundary of the predetermined acceptable range, N seems too small and is going to increase by 1 at the end of the Nth switching cycle. Accordingly, voltage VCPis adaptively controlled to substantially stay within the acceptable range.