Switch circuit

To provide a switch circuit which is capable of reliably controlling transmission of a voltage from GND to VDD to an internal circuit or shut-off thereof even when a positive or negative voltage is inputted to an input terminal, and thereby reduces the risk of latch-up. A switch circuit is comprised of NMOS transistors, and the gates of the NMOS transistors are controlled by an output voltage of a boosting circuit, thereby making it possible to reliably control transmission or shut-off of a voltage from GND to VDD.

RELATED APPLICATIONS

This application claims priority under 35 U.S.C. §119 to Japanese Patent Application No. 2015-011546 filed on Jan. 23, 2015, the entire content of which is hereby incorporated by reference.

BACKGROUND OF THE INVENTION

Field of the Invention

The present invention relates to a switch circuit provided at a terminal at which a positive or negative voltage is inputted to an internal circuit of a semiconductor device.

Background Art

FIG. 4is a circuit diagram showing a related art switch circuit. The switch circuit controls whether to transmit a positive or negative voltage inputted to an input terminal IN to an internal circuit15or shut off the positive or negative voltage, according to a signal of a switch control terminal EN.

Consider where the positive voltage VIN+ inputted from the input terminal IN is caused to be transmitted to a node B which is an input terminal of the internal circuit15. The signal of the switch control terminal EN is made to be a VDD voltage in an active state to turn ON NMOS transistors11and12. Here, the VDD voltage is a power supply voltage of the internal circuit15. Further, a level shifter circuit18is configured to convert the signal of the input terminal LI into a voltage by the voltage of a power supply terminal LV and output the voltage from an output terminal LO and thereby to reverse the logic of the input and output. When the signal of the input terminal LI is of the VDD voltage, the level shifter circuit18outputs a signal of a GND voltage from the output terminal LO.

When the signal of the input terminal LI is of the GND voltage, the level shifter circuit18outputs a signal of the voltage of the power supply terminal LV from the output terminal LO. Thus, the level shifter circuit18outputs the GND voltage. When the voltage VIN+ is a voltage less than or equal to (|VGSP1|+|VOVP1|), the level shifter circuit18turns OFF a PMOS transistor16. When the voltage VIN+ is a voltage greater than or equal to (|VGSP1|+|VOVP1|), the level shifter circuit18turns ON the PMOS transistor16. Here, VGSP1 is a threshold voltage (VGSP1<0V) of each of the PMOS transistors16and a PMOS transistor17. VOVP1 is an overdrive voltage (VOVP1<0V) necessary to reliably turn ON the PMOS transistors16and17. Further, since the signal of the switch control terminal EN becomes the GND voltage through an inverter14, the PMOS transistor17is turned ON. Thus, the positive voltage VIN+ inputted from the input terminal IN is transmitted to the node B which is the input terminal of the internal circuit15. At this time, since an NMOS transistor13is being turned OFF, it does not affect the voltage of the node B.

Further, since the voltage at which the voltage VIN+ is greater than or equal to the GND voltage and less than or equal to (|VGSP1|+|VOVP1|) can be transmitted to the node B through the NMOS transistors11and12, the voltage at which the voltage VIN+ is greater than or equal to (|VGSP1|+|VOVP1|) and less than or equal to (VDD-VGSN1-VOVN1) can be transmitted to the node B through either the NMOS transistors11and12or the PMOS transistors16and17, and the voltage at which the voltage VIN+ is greater than or equal to (VDD-VGSN1-VOVN1) and less than or equal to VDD can be transmitted to the node B through the PMOS transistors16and17, the positive voltage VIN+ inputted from the input terminal IN can be transmitted to the node B between the GND voltage at minimum and the VDD voltage at maximum.

Here, VDD is a power supply voltage, VGSN1 is a threshold voltage (VGSN1>0V) of each of the NMOS transistors11and12, and VOVN1 is an overdrive voltage (VOVN>0V) necessary to reliably turn ON the NMOS transistors11and12.

Next, consider where the positive voltage VIN+ inputted from the input terminal IN is not caused to be transmitted to the node B taken as the input of the internal circuit15. The signal of the switch control terminal EN is made to be a GND voltage in an inactive state. Since the GND voltage is inputted to the input terminal LI, the level shifter circuit18outputs the same voltage as VIN+ connected to the power supply terminal LV from the output terminal LO. Since a gate of the NMOS transistor13is at the VDD voltage and a source thereof is at the GND voltage, the NMOS transistor13is turned ON to bring a node A to the GND voltage. Since a gate and a source (node A) of the NMOS transistor11are at the GND voltage, the NMOS transistor11is turned OFF. Since a gate and a drain (node A) of the NMOS transistor12are at the GND voltage, the NMOS transistor12is turned OFF. Since a gate and a source (input terminal IN) of the PMOS transistor16are at the voltage VIN+, the PMOS transistor16is turned OFF. Since a gate of the PMOS transistor17is at the VDD voltage and a drain (node B) thereof is less than or equal to the VDD voltage, the PMOS transistor17is turned OFF. Thus, the positive voltage VIN+ inputted from the input terminal IN is not transmitted to the node B taken as the input of the internal circuit15.

Next, consider where the negative voltage VIN− inputted from the input terminal IN is not caused to be transmitted to the node B taken as the input of the internal circuit15. The signal of the switch control terminal EN is made to be the GND voltage in the inactive state. Since, however, the negative voltage VIN− lower than the GND voltage is applied to the input terminal IN, the NMOS transistor11is brought into an ON state in a weak inversion region. Here, since the NMOS transistor13is turned ON, the node A is not brought to the input negative voltage VIN−, but to the GND voltage. Since the gate and source of the NMOS transistor12are at the GND voltage, the NMOS transistor12is turned OFF. Since VIN− is applied to the gate, source and backgate of the PMOS transistor16, the PMOS transistor16is turned OFF. Since the gate of the PMOS transistor17is at the VDD voltage and the node B is at less than or equal to the VDD voltage, the PMOS transistor17is turned OFF. Thus, the negative voltage VIN− inputted from the input terminal IN is not transmitted to the node B taken as the input of the internal circuit15.

Thus, the related art switch circuit is capable of preventing the negative voltage from being transmitted to the input of the internal circuit15even if the negative voltage is inputted from the input terminal IN, and preventing the malfunction of the internal circuit.

SUMMARY OF THE INVENTION

In the related art switch circuit, however, there is a possibility that the risk of causing latch-up will exist since the PMOS transistor16the source and backgate of which are connected to the input terminal IN, and the NMOS transistor13the source and backgate of which are connected to the GND terminal exist in close proximity to each other on a circuit basis, and that a large current is made to flow to thereby break down the circuit. Further, when a countermeasure is taken against the latch-up in layout design, a circuit scale is increased, thus leading to the cost-up of a product.

A switch circuit of the present invention has been made to solve the above problems. The switch circuit is configured such that it is equipped with a first NMOS transistor having a drain connected to an input terminal of a semiconductor device, a source connected to a first node, and a gate connected to a second node, a second NMOS transistor having a drain connected to the first node, a source connected to a third node, and a gate connected to the second node, a third NMOS transistor having a drain connected to the first node, and a gate connected to a switch control terminal via an inverter, and a boosting circuit having a boosting circuit control terminal connected to the switch control terminal, a voltage input terminal connected to a power supply, and a voltage output terminal connected to the second node, and the third node is connected to an internal circuit.

According to the switch circuit of the present invention, it is possible to prevent the transmission of a negative voltage inputted from an input terminal to an input terminal of an internal circuit even if the negative voltage is inputted therefrom and transmit a voltage up to a VDD voltage as a positive voltage to the input of the internal circuit, and to reduce a risk caused by latch-up.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Embodiments of a switch circuit of the present invention will hereinafter be described with reference to the accompanying drawings. The switch circuit controls whether to transmit a positive or negative voltage inputted to an input terminal IN to an internal circuit15or shut off the positive or negative voltage, according to a signal of a switch control terminal EN.

First Embodiment

FIG. 1is a circuit diagram illustrating a switch circuit according to a first embodiment.

The switch circuit according to the first embodiment is equipped with NMOS transistors11,12and13, an inverter14, and a boosting circuit19.

The NMOS transistor11has a drain connected to the input terminal IN, a gate connected to a voltage output terminal RO (node D) of the boosting circuit19, and a source connected to a drain of the NMOS transistor12and a drain of the NMOS transistor13. The NMOS transistor12has a gate connected to the voltage output terminal RO (node D) of the boosting circuit19, and a source connected to an input terminal (node B) of the internal circuit15. The NMOS transistor13has the drain connected to the source of the NMOS transistor11and the drain of the NMOS transistor12, a gate connected to an output terminal (node C) of the inverter14, and a source grounded to GND. The inverter14has an input terminal connected to the switch control terminal EN. The boosting circuit19has a boosting circuit control terminal RE connected to the switch control terminal EN, and a voltage input terminal RI connected to a power supply voltage26.

The boosting circuit19is controlled to be ON/OFF according to the signal of the switch control terminal EN. In an ON state, the boosting circuit19outputs a voltage obtained by boosting a signal inputted to the voltage input terminal RI from the voltage output terminal RO. In an OFF state, the boosting circuit19outputs a GND voltage from the voltage output terminal RO. The NMOS transistors11and12are controlled to be ON/OFF by the signal of the voltage output terminal RO of the boosting circuit19. The inverter14inverts a signal of a VDD/GND voltage inputted thereto and outputs the inverted signal. The NMOS transistor13is controlled to be ON when the NMOS transistors11and12are turned OFF.

The operation of the switch circuit according to the first embodiment will next be described.

(1) When a positive voltage VIN+ inputted from the input terminal IN is not caused to be transmitted to the node B:

The switch control terminal EN is inputted with a signal of a GND voltage in an inactive state. Since the gate of the NMOS transistor13is at the VDD voltage and the source thereof is at the GND voltage, the NMOS transistor13is turned ON to bring a node A to the GND voltage. Since the gate and source (node A) of the NMOS transistor11are at the GND voltage, the NMOS transistor11is turned OFF. Since the gate and drain (node A) of the NMOS transistor12are at the GND voltage, the NMOS transistor12is turned OFF. Thus, the positive voltage VIN+ inputted from the input terminal IN is not transmitted to the node B.

(2) When a negative voltage VIN− inputted from the input terminal IN is not caused to be transmitted to the node B:

The switch control terminal EN is inputted with the signal of the GND voltage in the inactive state. The boosting circuit19is brought into an OFF state and thereby outputs the GND voltage. Since the drain of the NMOS transistor11is at the negative voltage VIN− and the gate thereof is at the GND voltage, the NMOS transistor11is brought into an ON state in a weak inversion region. Since, however, the gate of the NMOS transistor13is at the VDD voltage, the NMOS transistor13is turned ON to bring the node A to the GND voltage. Since the drain and gate of the NMOS transistor12are at the GND voltage, the NMOS transistor12is turned OFF. Thus, the negative voltage VIN− inputted from the input terminal IN is not transmitted to the node B.

(3) When the positive voltage VIN+ (less than or equal to VDD voltage) inputted from the input terminal IN is caused to be transmitted to the node B:

The switch control terminal EN is inputted with a signal of a VDD voltage in an active state. The boosting circuit19is brought into an ON state and thereby outputs a boosted voltage greater than or equal to (VDD+VGSN1+VOVN1). Since the gate of the NMOS transistor11is at the voltage greater than or equal to (VDD+VGSN1+VOVN1), the NMOS transistor11transmits the voltage VIN+ to the source (node A). The NMOS transistor12also similarly propagates the voltage VIN+ to the node B.

As describe above, the switch circuit according to the present embodiment is capable of transmitting the input voltage which ranges from the GND voltage to the VDD voltage.

Further, the switch circuit according to the present embodiment has no risk of latch-up because there are not provided PMOS transistors each having a source and a backgate connected to a power supply or a node such as an input/output terminal into which a large current is made to flow.

FIG. 2is one example of the configuration of the boosting circuit19employed in the first embodiment. A diode21has an anode connected to the voltage input terminal RI (power supply26) and a cathode connected to one end (node E) of a capacitor24. A PMOS transistor22has a drain connected to the voltage output terminal RO (node D) of the boosting circuit19, a gate connected to the output terminal (node C) of the inverter14, and a source connected to one end (node E) of the capacitor24. An NMOS transistor23has a drain connected to the voltage output terminal RO (node D) of the boosting circuit19, a gate connected the output terminal (node C) of the inverter14, and a source connected to GND. The capacitor24has the other end connected to the boosting circuit control terminal RE (switch control terminal EN).

The operation of the configuration example of the boosting circuit shown inFIG. 2will next be described.

(1) When the boosting circuit19outputs a GND voltage:

The switch control terminal EN is inputted with a signal of a GND voltage in an inactive state. Further, a power supply voltage VDD of the internal circuit15is inputted to the power supply26. Since the gate of the NMOS transistor23is at the VDD voltage and the source thereof is at the GND voltage, the NMOS transistor23is turned ON to bring the voltage output terminal RO (node D) of the boosting circuit19to GND. When the node E is at a voltage less than or equal to (VDD+|VGSP2|), the PMOS transistor22is turned OFF because the gate of the PMOS transistor22is at the VDD voltage and the source thereof is at less than or equal to (VDD+|VGSP2|). Here, VGSP2 is a threshold voltage of the PMOS transistor22(VGSP2<0). When the node E is at a voltage greater or equal to (VDD+|VGSP2|), the PMOS transistor22is turned ON until the source (node E) reaches the voltage of (VDD+|VGSP2|), to thereby discharge the capacitor24. Since the anode of the diode21is at the VDD voltage when the node E is at a voltage less than or equal to (VDD−VBE), the diode21charges the capacitor24until the cathode (node E) thereof reaches the voltage of (VDD−VBE). Here, VBE is a threshold voltage of the diode21(VBE>0). When the node E is at a voltage greater than or equal to (VDD−VBE), the diode21does not allow current to flow. The capacitor24is charged/discharged according to the state of one end (node E) as described above and becomes a voltage at which the voltage of one end is greater than or equal to (VDD−VBE) and less than or equal to (VDD+VGSP2).

(2) When the boosting circuit19outputs a boosted voltage:

The switch control terminal EN is inputted with a signal of a VDD voltage in an active state. Since the gate of the NMOS transistor23is at the GND voltage, the NMOS transistor23is turned OFF. Since the capacitor24is inputted with the signal of the GND voltage at the other end thereof while the switch control terminal EN is in an inactive state, an electrical charge at which the inter-terminal voltage of the capacitor24assumes a voltage greater than or equal to (VDD−VBE) and less than or equal to (VDD+|VGSP2|) is accumulated between the terminals of the capacitor24. Since the voltage of the other end becomes the VDD voltage when the switch control terminal EN reaches the VDD voltage, the voltage of one end (node E) is boosted to greater than or equal to (2VDD−VBE) and less than or equal to (2VDD+|VGSP2|). Since the gate of the PMOS transistor22is at the GND voltage, the PMOS transistor22is turned ON. The electrical charge accumulated in the capacitor24is distributed to gate capacitances of the NMOS transistors11and12through the PMOS transistor22. Thus, a voltage of the voltage output terminal RO (node D) is greater than or equal to (2VDD−VBE)*C1/(C1+CG) and less than or equal to (2VDD+|VGSP2|)*C1/(C1+CG). Here, C1 indicates the capacitance value of the capacitor24, and CG indicates the sum of the capacitance values of the gate capacitances of the NMOS transistors11and12. Now, when C1 is designed to be greater than or equal to CG*(VDD+VGSN1+VOVN1)/(VDD−VGSN1−VOVN1−VBE), the boosting circuit is capable of outputting a voltage greater than or equal to (VDD+VGSN1+VOVN1). Further, when C1 is designed to be less than or equal to CG*VBD1/(VDD−VGSN1−VOVN1−VBE), the NMOS transistors11and12are not broken down. Here, VBD1 is the gate breakdown voltage of the NMOS transistors11and12.

Since a PMOS the source and backgate of which are connected to a power supply or a node such as an input/output terminal into which a large current is made to flow does not exist if the boosting circuit described above is provided, the risk of latch-up is low. Further, a circuit scale is also small and the cost is low as well.

Second Embodiment

FIG. 3is a circuit diagram illustrating a switch circuit according to a second embodiment.

The switch circuit according to the second embodiment is equipped with a voltage limiting circuit20in addition to the switch circuit according to the first embodiment. The voltage limiting circuit20has one end connected to the voltage output terminal RO (node D) of the boosting circuit19, and the other end connected to GND.

The voltage limiting circuit20allows current to flow into GND when the voltage output terminal RO of the boosting circuit19is at greater than equal to a voltage VBD2, to thereby maintain the voltage at less than or equal to VBD2. Here, VBD2 is a voltage greater than or equal to (VDD+VGSN1+VOVN1) and a voltage lower than the gate breakdown voltage of the NMOS transistors11and12.

Thus, in the switch circuit according to the second embodiment, even when the output voltage of the boosting circuit19becomes the voltage greater than or equal to the gate breakdown voltage of the NMOS transistors11and12for some reason, the NMOS transistors11and12can be prevented from being broken down, and other circuit operations are similar to the circuit operation described in the first embodiment.