Flash memory device and program method thereof

A nonvolatile memory device that includes first and second storage areas, and a control logic configured to control the first and second storage areas, wherein when a program operation of the first storage area is passed before a program operation of the second storage area is passed, the control logic completes the program operation of the first storage area and continues the program operation of the second storage area is provided.

BACKGROUND

The present disclosure relates to a flash memory device and, more particularly, to a flash memory device and a program method capable of reducing program disturbance.

A non-volatile memory device may retain stored data in memory cells even when the power is turned off. As an example of such a non-volatile memory device, a flash memory device may have a function of electrically erasing data of memory cells collectively, so that it is widely used for applications such as computers, memory cards, and the like.

A flash memory device may be classified into a NOR type and a NAND type based upon the interconnection between memory cells and bit lines. In general, the NOR-type flash memory device is unfavorable for high integration, although it has an advantage that it can easily cope with high speed. The NAND-type flash memory device is favorable for high integration, because it consumes less current than the NOR-type flash memory device.

The NAND-type flash memory device may include a memory cell array as a region for storing information. The memory cell array may consist of a plurality of blocks, each of which has a plurality of cell strings (referred to as NAND strings). The NAND-type flash memory device may further include a page buffer circuit that is configured to store or read data in or from the memory cell array. As is known in the art, in the case of the NAND-type flash memory device, memory cells may be programmed or erased by use of the Fowler-Nordheim (FN) tunneling current. Erase and program methods of the NAND-type flash memory device are disclosed in greater detail in U.S. Pat. No. 5,473,563 entitled “Nonvolatile Semiconductor Memory” and in U.S. Pat. No. 5,696,717 entitled “Nonvolatile Integrated Circuit Memory Devices Having Adjustable Erase/Program Threshold Voltage Verification Capability”, the entire contents of which are hereby incorporated by reference.

The NAND-type flash memory device may be classified into a Single Level Cell (SLC) NAND-type flash memory device and a Multi Level Cell (MLC) NAND-type flash memory device.

The SLC NAND-type flash memory device can store 1-bit data per memory cell, while the MLC NAND-type flash memory device can store multi-bit data per memory cell.

FIG. 1is a diagram showing threshold voltage distributions of a conventional MLC NAND-type flash memory device. The distribution figure indicates the case that 2-bit data is stored in each memory cell of the MLC NAND-type flash memory device. It will be understood by one of ordinary skill in the art, however, that the MLC NAND-type flash memory device is configured to store N-bit data (N is an integer of 3 or more) per memory cell.

Referring toFIG. 1, when erased, a memory cell may have an erase state ST0. Further, each memory cell may be programmed to have one of program states (or, data states) ST1, ST2and ST3. Although not illustrated, in a case where 3-bit data is stored in each memory cell, each memory cell may have one of an erase state (ST0) and seven program states (ST1˜ST7).

A conventional NAND-type flash memory device may include a plurality of planes, each of which has a separate memory cell array. A memory cell array may include memory cells arranged in rows and columns. During a multi-plane program operation, the NAND-type flash memory device may perform a program operation with respect to all or selected planes at the same time. In this case, the NAND-type flash memory device may perform a verification operation for confirming whether a program operation of each plane is made in the normal fashion. A program operation is passed when data is programmed normally and is failed when data is not programmed normally. As is known in the art, the NAND-type flash memory device may repeat a program operation until the program operations all of the selected planes are passed.

Although a program-passed plane exists, the NAND-type flash memory device may perform a program operation with respect to all selected planes when at least one plane is judged to be program-failed. During the repeated program operation, a program voltage and a pass voltage are applied to all selected planes that consist of program-passed planes and program-failed planes. Accordingly, if the NAND-type flash memory device has at least one program-failed plane, the program and pass voltages may be applied to all selected planes that include program-passed planes.

In this case, memory cells in a program-passed plane may be unnecessarily supplied with the program and pass voltages. That is, memory cells in a program-passed plane may be unduly stressed. Memory cells thus stressed may be soft programmed, as illustrated by the broken lines inFIG. 1. This means that threshold voltages of the memory cells in the program-passed plane are increased, which is illustrated by the broken lines inFIG. 1. In other words, the memory cells in the program-passed plane may suffer from program disturbance.

A NAND-type flash memory device may read data from selected memory cells to output the read data externally. During a read operation, read voltages R0, R1, and R2defined between ST0and ST1, between ST2and ST3, and between ST2and ST3, respectively, may be used to read 2-bit data. If threshold voltage distributions of respective states are increased over the read voltages R0, R1, and R2, it is impossible to read data from memory cells having the states ST0, ST1, ST2, and ST3accurately. That is, a read error may arise.

As a result, during a multi-plane program operation, if at least one plane is judged to be program-failed, the program and pass voltages may be continuously applied to memory cells of the program-passed planes. This may cause a read error due to program disturbance.

SUMMARY OF THE INVENTION

Exemplary embodiments of the present invention are directed to provide a flash memory device and a program method thereof capable of reducing program disturbance.

One exemplary embodiment of the present invention provides a nonvolatile memory device that comprises first and second storage areas, and a control logic configured to control the first and second storage areas, wherein when a program operation of the first storage area is passed before a program operation of the second storage area is passed, the control logic completes the program operation of the first storage area and continues the program operation of the second storage area.

An exemplary embodiment of the present invention provides a method of programming a nonvolatile memory device. The method of programming a nonvolatile memory device comprises executing program operations of first and second storage areas simultaneously; completing the program operation of a program-passed area of the first and second storage areas; and continuing the program operation of a program-failed area of the first and second storage areas.

An exemplary embodiment of the present invention provides a memory system that comprises a nonvolatile memory device, and a controller configured to control the nonvolatile memory device. The nonvolatile memory device comprises first and second storage areas, and a control logic configured to control the first and second storage areas, wherein when a program operation of the first storage area is passed before a program operation of the second storage area is passed, the control logic completes the program operation of the first storage area and continues the program operation of the second storage area.

DETAILED DESCRIPTION OF EXEMPLARY EMBODIMENTS

Exemplary embodiments of the present invention will be described below in more detail with reference to the accompanying drawings, showing a flash memory device as an example for illustrating structural and operational features provided by the present invention. The present invention may, however, be embodied in different forms and should not be construed as limited to the exemplary embodiments set forth herein. Rather, these exemplary embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the present invention to those of ordinary skill in the art. Like reference numerals refer to like elements throughout the accompanying figures.

As will be described below, a flash memory device according to an exemplary embodiment of the present invention may include a voltage generator circuit configured to generate a program voltage, a pass voltage, and a high voltage; a plurality of planes configured to perform a program operation in response to the program, pass, and high voltages and to verify whether a program operation has passed or failed; and control logic configured to control the planes in response to verification results of the planes. More specifically, the control logic may control the planes so as to prevent the program and pass voltages or the high voltage from being supplied to program-passed planes. Accordingly, the flash memory device of an exemplary embodiment of the present invention is capable of reducing the stress to program-passed planes, that is, reducing a program disturbance.

FIG. 2is a block diagram showing a flash memory device according to an exemplary embodiment of the present invention.

Referring toFIG. 2, a flash memory device1000according to an exemplary embodiment of the present invention may include a plurality of planes100_1to100—y−1, a control logic unit200, and a voltage generator circuit300. The flash memory device1000according to this exemplary embodiment of the present invention may be an SLC NAND-type flash memory device or an MLC NAND-type flash memory device.

Each of the planes100_0to100—y−1 may be configured to store data information at a multi-plane program operation and to verify whether the data information is stored normally. Verification results of the planes100_0˜100—y−1 may be transferred to the control logic200.

The control logic200may be configured to generate control signals P/F_FLAG0˜P/F_FLAGy−1 each corresponding respectively to the planes100_0˜100—y−1 in response to the verification results from the planes100_0˜100—y−1. Further, the control logic200may be configured to control an entire operation of the flash memory device1000.

The voltage generator circuit300may be configured to generate a program voltage Vpgm, a pass voltage Vpass, and a high voltage Vpp under the control of the control logic200. The respective program, pass, and high voltages Vpgm, Vpass and Vpp may be supplied to the respective planes100_0˜100—y−1.

In a case where a multi-plane program operation is carried out, the flash memory device1000may perform a program operation in which the data information is stored in all or selected ones of the planes. The program operation may be repeated until the data information is stored normally in all or selected ones of the planes. When a program operation of a plane is passed, the plane may output a pass signal. On the other hand, when a program operation of a plane is failed, the plane may output a fail signal. Hereinafter, such a plane that a program operation is passed is referred to as a ‘program-passed plane’, and such a plane that a program operation is failed is referred to as a ‘program-failed plane’.

For example, assuming that a plane100_0is program-passed and a plane100—y−1 is program-failed, the plane100_0outputs a pass signal and the plane100—y−1 outputs a fail signal. The pass and fail signals are supplied to the control logic200as verification results. The control logic200may activate a control signal P/F_FLAG0in response to the pass signal from the plane100_0, and may inactivate a control signal P/F_FLAGy−1 in response to the fail signal from the plane100—y−1. The control signals P/F_FLAG0and P/F_FLAGy−1 are fed to the planes100_0and100—y−1, respectively.

The program-passed plane100_0may be configured to prevent the program and pass voltages Vpgm and Vpass from being received in response to the activated control signal P/F_FLAG0. Accordingly, no program operation may be made with respect to the program-passed plane100_0that receives the activated control signal P/F_FLAG0. On the other hand, the program-failed plane100—y−1 may receive the program voltage Vpgm and pass voltage Vpass from the voltage generator300in response to the inactivated control signal P/F_FLAGy−1. This means that a program operation is repeatedly made with respect to the program-failed plane100—y−1 that receives the inactivated control signal P/F_FLAGy−1.

As a result, the flash memory device1000may be configured to prevent a program operation from being performed with respect to program-passed planes, even though certain planes are not program-passed.

FIG. 3is a block diagram showing a plane illustrated inFIG. 2. Respective planes100_0˜100—j−1 may be configured to have the same structure as that illustrated inFIG. 3.

Referring toFIG. 3, the plane100_0according to an exemplary embodiment of the present invention may include a memory cell array110having a plurality of memory blocks BLK0˜BLKn−1, a row selector circuit120, a page buffer circuit130, a column selector circuit140, and a pass/fail check circuit150. Each of the memory blocks BLK0˜BLKn−1 may include a plurality of memory cells arranged in rows (or word lines) and columns (or bit lines). The memory cell array110may store data information.

The row selector circuit120can select a memory block in response to an externally input block address (not shown) and select a word line in the selected memory block in response to a row address (not shown). The row selector circuit120may receive a program voltage Vpgm, a pass voltage Vpass, and a high voltage Vpp from the voltage generator circuit300shown inFIG. 2and a control signal P/F_FLAG0from the control logic200ofFIG. 2. At a program operation, the row selector circuit120may apply the program voltage Vpgm to a selected word line and the pass voltage Vpass to respective unselected word lines. More specifically, the row selector circuit120may be configured to prevent the voltages Vpgm, Vpass, and Vpp from being applied to corresponding signal lines based upon activation of the control signal P/F_FLAG0.

The page buffer circuit130may include page buffers that are electrically connected respectively to bit lines shared by all memory blocks. Each of the page buffers may operate as a sense amplifier or a write driver based on a mode of operation.

For example, in a program operation, the page buffer circuit130may store data provided via the column selector circuit140and drive bit lines of the memory cell array110with a predetermined voltage, for example, a power-supply voltage, or a ground voltage, based on the stored data, respectively. In a read or verity operation, the page buffer circuit130may sense data bits stored in memory cells of a selected word line. In a read operation, the sensed data bits may be output externally via the column selector circuit140. In a verify operation, the sensed data bits may be transferred to the pass/fail check circuit150via the column selector circuit140.

The pass/fail check circuit150may check whether all data bits transferred via the column selector circuit140have a pass data value and provide a pass or fail signal to the control logic200ofFIG. 2as a verification result.

The control logic200may generate the control signal P/F_FLAG0in response to the verification result from the pass/fail check circuit150to output the control signal P/F_FLAG0to the row selector circuit120.

During a multi-plane program operation, all or selected ones of the planes may perform a program operation separately. More specifically, during a verification interval, the pass/fail check circuit150of each plane may check whether the memory cells are normally programmed. If a plane, for example,100_0, is judged to be program-passed, a program operation may be made as follows.

The pass/fail check circuit150of the program-passed plane provides a pass signal to the control logic200as a verification result. The control logic200activates the control signal P/F_FLAG0in response to the pass signal from the pass/fail check circuit150. The row selector circuit120of the program-passed plane interrupts the program and pass voltages Vpgm and Vpass or the high voltage Vpp supplied from the voltage generator circuit300in response to the activated control signal P/F_FLAG0. Accordingly, it is possible to prevent memory cells of a selected memory block in the program-passed plane100_0from being subjected to undue stress.

If a plane, for example,100_0, is judged to be program-failed, a program operation may be performed as follows.

The pass/fail check circuit150of the program-failed plane may provide a fail signal to the control logic120as a verification result. The control logic200may inactivate the control signal P/F_FLAG0in response to the fail signal from the pass/fail check circuit150. The row selector circuit120may receive the voltages Vpgm, Vpass, and Vpp in response to the inactivated control signal P/F_FLAG0, so that a program operation is again performed with respect to the program-failed plane.

FIG. 4is a block diagram showing a row selector circuit illustrated inFIG. 3according to an exemplary embodiment of the present invention.

Referring toFIG. 4, a memory block BLK0may include a plurality of transistor strings111, each of which has a string select transistor SST, a ground select transistor GST, and a plurality of memory cell transistors MC0˜MCm−1 connected in series between the select transistors SST and GST. The strings111are electrically connected to corresponding bit lines BL0˜BLk−1, respectively. Although not illustrated in the figures, the bit lines BL0˜BLk−1 may be arranged so as to be shared by all memory blocks BLK0˜BLKn−1 of the plane100_0. In each string111, the string select transistor SST is connected to a string select line SSL, the ground select transistor GST is connected to a ground select line GSL, and the memory cell transistors MC0˜MCm−1 are respectively connected to corresponding word lines WL0˜WLm−1.

The row selector circuit120may include a block decoder121and a row decoder122. The row decoder122may include select transistors STR0˜STRi−1. The lines SSL, WL0˜WLm−1, and GSL are respectively connected to corresponding select lines S0˜Si−1 through the select transistors STR0˜STRi−1.

The row decoder122may further comprise a decoder1221that is configured to transfer corresponding voltages, supplied from the voltage generator circuit shown inFIG. 2, to the select lines S0˜Si−1 in response to row address information and the control signal P/F_FLAG0. The decoder1221operates as a word line driver circuit. The decoder1221interrupts the program and pass voltages Vpgm and Vpass supplied from the voltage generator circuit300shown inFIG. 2in response to an activated control signal P/F_FLAG0. At this time, the decoder1221drives the select lines S1˜Si−2 with either a predetermined voltage or a ground voltage and drives the select lines S0and Si−1 with a power-supply voltage and a ground voltage, so that the word lines WL0˜WLm−1 are driven with a ground voltage or the predetermined voltage. In this exemplary embodiment, the predetermined voltage may be a voltage identical to or lower than a power supply voltage.

Gates of the select transistors STR0˜STRi−1 are commonly connected to a block select line BSC, which is output from the block decoder121. The block decoder121may select a memory block in response to externally input block address information. That is, the block decoder121may activate or inactivate the block select line BSC in response to the block address information. The page buffer circuit130may include page buffers PB connected to the bit lines BL0˜BLk−1, respectively. In a program verify operation, each of the page buffers PB may output read data to the pass/fail check circuit150via the column selector circuit140. Data transferred to the pass/fail check circuit150may be used to check whether a program operation of selected memory cells is normally performed. Exemplary page buffer and pass/fail check circuits are disclosed in U.S. Pat. No. 5,299,162 entitled ‘Nonvolatile Semiconductor Memory Device And An Optimizing Programming Method Thereof’, the entire contents of which are hereby incorporated by reference.

FIG. 5is a timing diagram for describing a multi-plane program operation of a flash memory device including a row selector circuit illustrated inFIG. 4. Below, a multi-plane program operation of the flash memory device according to an exemplary embodiment of the present invention will be more fully described with reference toFIGS. 4 and 5. For convenience of description, a multi-plane program operation will be described using plane,100_0, however, it will be seen by one of ordinary skill in the art that the present invention can be applied to other planes.

Once a multi-plane program operation commences, the block decoder121ofFIG. 2may drive a block select line BSC with a high voltage Vpp from a voltage generator circuit300shown inFIG. 2, so that select transistors STR0˜STRi−1 shown inFIG. 4are turned on. More specifically, the block decoder121may include a high-voltage driver1211and a block word line driver1212, which are illustrated inFIG. 6. The high-voltage driver1211may provide the high voltage Vpp from the voltage generator circuit300to the block word line driver1212as a block word line voltage Vppi. The block word line driver1212of the block decoder121may drive the block select line BSC with the block word line voltage Vppi being the high voltage Vpp.

In the case where the plane100_0is judged to be program-passed after a program verify operation, control logic200ofFIG. 2may activate a control signal P/F_FLAG0to go high in response to a verification result of the pass/fail check circuit150. The decoder1221in the row decoder122may prevent the program and pass voltages Vpgm and Vpass from being transferred to select lines S1˜Si−2 in response to the activated control signal P/F_FLAG0. At the same time, the decoder1221may drive the select line S1˜Si−2 with a predetermined voltage or a ground voltage Gnd. Accordingly, a ground voltage or a predetermined voltage may be applied to all word lines in a selected memory block via the turned-on select transistors STR1˜STRi−2. In this exemplary embodiment, the predetermined voltage may be a power-supply voltage Vdd or a voltage lower than the power-supply voltage. Because programmed memory cells in the program-passed plane are supplied with the predetermined voltage or the ground voltage during a program operation, it is possible to prevent program stress (or disturbance) of the programmed memory cells due to a program operation for program-failed planes.

In the case that the plane100_0is judged to be program-failed, as illustrated inFIG. 5, the control logic200may inactivate the control signal P/F_FLAG0to a low level in response to a verification result of the pass/fail check circuit150. The decoder1221in the row decoder122shown inFIG. 4may drive select lines corresponding to the word lines WL0˜WLm−1 with corresponding program and pass voltages Vpgm and Vpass, respectively, in response to the inactivated control signal P/F_FLAG0. That is, a selected word line is driven with the program voltage Vpgm and unselected word lines are driven with the pass voltage Vpass. Accordingly, a program operation may be made with respect to the program-failed plane.

FIG. 6is a block diagram showing a row selector circuit120illustrated inFIG. 3according to an exemplary embodiment of the present invention. InFIG. 6, constituent elements that are substantially identical to those inFIG. 4are marked by the same numerals, and a description thereof is thus omitted.

Referring toFIG. 6, the block decoder121may include the high-voltage driver1211and the block word line driver1212. The high-voltage driver1211transfers a high voltage Vpp from the voltage generator circuit300shown inFIG. 2to the block word line driver1212as the block word line voltage Vppi. The block word line driver1212may respond to a control signal P/F_FLAG0from control logic200to determine whether to apply the block word line voltage Vppi to the block word line BSC.

FIG. 7is a timing diagram for describing a multi-plane program operation of a flash memory device including a row selector circuit120illustrated inFIG. 6. Hereinafter, a multi-plane program operation according to the flash memory device will be more fully described with reference toFIGS. 6 and 7.

Basically, a program operation may be performed identically to that described above. After the program operation, a verify operation may be made. A plane may be judged to be program-passed or program-failed as a verification result.

In the case that the plane is judged to be program-passed, as illustrated inFIG. 7, control logic200may activate a control signal P/F_FLAG0in response to a verification result from the program-passed plane100_0. The block word line driver1212may interrupt transferring the block word line voltage Vppi as the high voltage Vpp in response to the activated control signal P/F_FLAG0. At this time, the block word line driver1212may output a predetermined voltage, for example, identical or lower than a power-supply voltage, as the block word line voltage Vppi in response to the activated control signal P/F_FLAG0. This means that the block word line BSC is driven with the predetermined voltage via the block word line driver1212. Alternatively, a ground voltage may be applied to the block word line BSC instead of the predetermined voltage. As a result, the select transistors STR0˜STRi−1 may be slightly tamed on by the block word line BSC that is driven with the predetermined voltage. This makes it possible to limit the predetermined voltage of the respective program and pass voltages Vpgm and Vpass to be applied to the word lines WL0˜WLm−1.

As a result, it is possible to prevent the respective program and pass voltages Vpgm and Vpass from being applied to selected memory cells in the program-passed plane. That is, program disturbance may be reduced with respect to the program-passed plane.

In the case where the plane100_0is judged to be program-failed, as illustrated inFIG. 7, the control logic200may inactivate the control signal P/F_FLAG0in response to a verification result from the program-failed plane. As the control signal P/F_FLAG0is inactivated, that is, set to a low-level, the block word line BSC may be driven with the high voltage Vpp, that is, the block word line voltage Vppi. This enables the select transistors STR0˜STRi−1 to be turned on so as to transfer the respective program and pass voltages Vpgm and Vpass to corresponding word lines of the program-failed plane. This means that a program operation is again made with respect to the program-failed plane.

As will be understood from the above description, the flash memory device1000according to an exemplary embodiment of the present invention may be configured to prevent the respective program and pass voltages Vpgm and Vpass from being applied to memory cells of a program-passed plane, with at least one plane being program-failed. Thus, the flash memory device1000is capable of reducing program disturbance.

FIG. 8is a block diagram showing a row selector circuit120illustrated inFIG. 3according to an exemplary embodiment of the present invention.

The row selector circuit120illustrated inFIG. 8is substantially identical to that inFIG. 6except that the control signal P/F_FLAG0is applied to the high-voltage driver1211instead of to the block word line driver1212. For convenience of description, constituent elements that are identical to those inFIG. 6are marked by the same numerals, and description thereof is thus omitted. The high-voltage driver1211may respond to the control signal P/F_FLAG0from control logic200to determine an output of a high voltage Vppi.

FIG. 9is a timing diagram for describing a multi-plane program operation of a flash memory device including a row selector circuit illustrated inFIG. 8. Hereinafter, a multi-plane program operation according to the flash memory device will be more fully described with reference toFIGS. 8 and 9.

Basically, a program operation may be performed identically to that described above. After the program operation, a verify operation may be performed. A plane may be judged to be program-passed or program-failed as a verification result.

In the case that the plane is judged to be program-passed, as illustrated inFIG. 9, the control logic200shown inFIG. 2may activate a control signal P/F_FLAG0in response to a verification result from the program-passed plane100_0. The activated control signal P/F_FLAG0may be applied to a high-voltage driver1211.

The high-voltage driver1211may interrupt the high voltage Vpp from the voltage generator circuit300shown inFIG. 2in response to the activated control signal P/F_FLAG0. At this time, the high-voltage driver1211may output a predetermined voltage, for example, a voltage identical to or lower than a power supply voltage, as a block word line voltage Vppi. As illustrated inFIG. 9, the predetermined voltage may be applied to a block word line BSC via a block word line driver1212. Afterwards, an operation will be performed in the same manner as described above. That is, a program operation may be prevented with respect to the program-passed plane.

If a plane is judged to be program-failed, as illustrated inFIG. 9, the control logic200may inactivate the control signal P/F_FLAG0by setting it to a low level in response to a verification result from the program-failed plane. The control logic200may apply the inactivated control signal P/F_FLAG0to the high-voltage driver1211. As the control signal P/F_FLAG0is inactivated, the high-voltage driver1211may output the high voltage Vpp as the block word line voltage Vppi to the block word line driver1212. This means that the block word line BSC is driven with the high voltage Vpp being the block word line voltage Vppi. Afterwards, an operation will be performed in the same manner as described above.

As a result, it is possible to prevent the respective program and pass voltages Vpgm and Vpass from being applied to selected memory cells in the program-passed plane. That is, program disturbance may be reduced with respect to the program-passed plane.

FIG. 10is a flow diagram for describing a multi-plane program operation of a flash memory device according to an exemplary embodiment of the present invention.

Referring toFIG. 10, a multi-plane program method of a flash memory device according to an exemplary embodiment of the present invention may include performing a multi-plane program operation (S100); performing a program verify operation with respect to all or selected planes (S200); checking whether all or selected planes are program-passed (S300); if at least one plane is judged to be program-failed, repeating the steps S100to S300with the program and pass voltages/the high voltage being interrupted with respect to program-passed planes (S400).

As described above, when one or more planes of the multi-planes are program-passed before other planes of the multi-planes are program-passed, during the multi-plane operation, the flash memory device1000according to exemplary embodiments of the present invention interrupts supplying the program voltage to the program-passed plane(s). For example, when one or more planes of the multi-planes are program-passed before other planes of the multi-planes are program-passed, the flash memory device1000according to exemplary embodiments of the present invention interrupts supplying the pass voltage to the program-passed plane(s). Alternatively, in this case, the flash memory device1000according to exemplary embodiments of the present invention interrupts supplying the high voltage to the program-passed plane(s). According to exemplary embodiments of the present invention, a program disturbance is reduced. Thus, reliability of the flash memory device1000is advanced.

It will be understood that the flash memory device1000described above may be configured to store at least one bit per memory cell.

In the above-described exemplary embodiments, the technical spirit of the present invention is described referring to the flash memory device1000. The technical spirit of the present invention, however, is not limited to the flash memory device1000. For example, it will be understood that the technical spirit of the present invention may be applied to a nonvolatile memory device, such as a read only memory (ROM), a programmable ROM (PROM), an electrically programmable ROM (EPROM), an electrically erasable PROM (EEPROM), a flash memory, a phase change random access memory (PRAM), a magnetic RAM (MRAM), a resistive RAM (RAM), a ferroelectric RAM (FRAM), and the like.

FIG. 11is a block diagram of a memory system10including the flash memory device1000shown inFIG. 2. Referring toFIG. 11, the memory system10according to an exemplary embodiment of the present invention includes the flash memory device1000and a controller2000.

The flash memory device1000may be configured to operate in the same manner as described referring toFIGS. 1 to 10. For example, when a program operation of a first storage area is passed before a program operation of a second storage area is passed, the program operation of the first storage area is completed and the program operation of the second storage area is continued.

The controller2000is connected with a host (not shown) and the flash memory device1000.

The controller2000is configured to access the flash memory device1000in response to a request from the host. For example, the controller2000is configured to control read, program and erase operations of the flash memory device1000. In another example, the controller2000is configured to provide an interface between the flash memory device1000and the host. In yet another example, the controller2000is configured to drive firmware for controlling the flash memory device1000.

The controller2000may include elements (not shown) that are well known to one having ordinary skill in the related art, such as a RAM, a processing unit, a host interface, a memory interface, and the like. The RAM may be used as a work memory of the processing unit. The processing unit may control various operations of the controller2000.

The host interface may include a protocol for exchanging data between the host and the controller2000. In an exemplary embodiment, the controller2000may be configured to communicate with an exterior, that is the host, using one of various protocols, such as a universal serial bus (USB) protocol, a multimedia card (MMC) protocol, a peripheral component interconnection (PCI) protocol, a PCI-express (PCI-E) protocol, an advanced technology attachment (ATA) protocol, a serial ATA (SATA) protocol, a parallel ATA (PATA) protocol, a small computer small interface (SCSI) protocol an enhanced small disk interface (ESDI) protocol, an integrated drive electronics (IDE) protocol, an enhanced IDE (EIDE) protocol, and the like. The memory interface may be configured to interface with the flash memory device1000.

The memory system10may further include an error correcting block (not shown). The error correcting block may be configured to detect errors of data read from the flash memory device1000and correct the detected errors. In an example, the error correcting block may be provided as an element of the controller2000. In another example, the error correcting block may be provided as an element of the flash memory device1000.

The flash memory device1000and the controller2000may be integrated into a single semiconductor device. In an example, the flash memory device1000and the controller2000may be integrated into a semiconductor device to form a memory card (not shown). For example, the flash memory device1000and the controller2000may be integrated into a semiconductor device to form a memory card, such as a personal computer memory card international association card (PCMCIA card or PC card), a compact flash card (CF card), a smart media card (SM or SMC), a memory stick, a multimedia card (MMC), a reduced size MMC (RS-MMC), a MMC micro, a secure digital card (SD card), a mini SD card, a micro SD card, a SD high capacity (SDHC) card, an universal flash storage card (UFS card), and the like.

In another example, the flash memory device1000and the controller2000may be integrated into a semiconductor memory device to form a single semiconductor device, such as a solid state drive (SSD). For example, the SSD includes a storage device configured to store data into a semiconductor memory. When the memory system10is used as the SSD, the operation speed of the host connected with the memory system may be extremely advanced.

In another example, the memory system10may be applied as one of various elements of an electronic device, such as a computer, a mobile computer, an ultra mobile PC (UMPC), a workstation, a net-book, a personal digital assistants (PDA), a portable computer, a web tablet, a wireless phone, a mobile phone, a smart phone, a digital camera, a digital audio recorder, a digital audio player, a digital picture recorder, a digital picture player, a digital video recorder, a digital video player, a device that is able to transmit and receive information in a wireless circumstance, one of various devices composing a home network, one of various devices composing a computer network, one of various devices composing a telematics network, a radio frequency identifier (RFID) or one of various devices, that is, a SSD, a memory card, and the like, composing a computing system

In another example, the flash memory1000or the memory system10may be packaged as one of various types to be subsequently embedded. For example, the flash memory device1000or the memory system10may be packaged by one of PoP (Package on Package), Ball grid arrays (BGAs), Chip scale packages (CSPs), Plastic Leaded Chip Carrier (PLCC), Plastic Dual In-Line Package (PDIP), Die in Waffle Pack, Die in Wafer Form, Chip On Board (COB), Ceramic Dual In-Line Package (CERDIP), Plastic Metric Quad Flat Pack (MQFP), Thin Quad Flatpack (TQFP), Small Outline (SOIC), Shrink Small Outline Package (SSOP), Thin Small Outline (TSOP), Thin Quad Flatpack (TQFP), System In Package (SIP), Multi Chip Package (MCP), Wafer-level Fabricated Package (WFP), and Wafer-Level Processed Stack Package (WSP).

FIG. 12is a block diagram illustrating a flash memory device3000that is an exemplary embodiment of the flash memory device1000inFIG. 11. Referring toFIG. 12, the flash memory device3000includes a first plane3100a, a second plane3100b, a first pass/fail register3300, a second pass/fail register3400and a control logic3200.

The first and second planes3100aand3100binclude memory cells configured to store data, respectively. The first and second planes3100aand3100bmay be configured to store at least a bit per memory cell. The first and second planes3100aand3100bmay be configured to execute program and read operations independently. The first and second planes3100aand3100bmay be configured identically to each other. The first and second planes3100aand3100bare described more particularly referring toFIG. 12toFIG. 15

Referring toFIG. 12, first plane3100ais configured to receive a first selection signal P1SEL from the control logic3200. The first plane3100amay be activated in response to the first selection signal P1SEL. For example, the first plane3100amay be configured to execute a read/program operation when the first selection signal P1SEL is activated.

The first plane3100ais configured to output a first pass/fail signal PF1. The first pass/fail signal PF1indicates whether the first plane3100ais program-passed during a program operation of the first plane3100a. For example, when the first plane3100ais program-passed, the first pass/fail signal PF1may be activated.

The second plane3100bis configured to receive a second selection signal P2SEL from the control logic3200. The second plane3100bmay be activated in response to the second selection signal P2SEL. For example, the second plane3100bmay be configured to execute a read/program operation when the second selection signal P2SEL is activated.

The second plane3100bis configured to output a second pass/fail signal PF2. The second pass/fail signal PF2indicates whether the second plane3100bis program-passed during a program operation of the second plane3100b. For example, when the second plane3100bis program-passed, the second pass/fail signal PF2may be activated.

The first pass/fail register3300is configured to receive the first pass/fail signal PF1from the first plane3100a. The first pass/fail register3300is configured to store the first pass/fail signal PF1. The first pass/fail signal PF1stored in the first pass/fail register3300may be transferred to the control logic3200.

The second pass/fail register3400is configured to receive the second pass/fail signal PF2from the second plane3100b. The second pass/fail register3400is configured to store the second pass/fail signal PF2. The second pass/fail signal PF2stored in the second pass/fail register3400may be transferred to the control logic3200.

The control logic3200is configured to control various operations of the flash memory device3000. The control logic3200is configured to receive the first pass/fail signal PF1from the first pass/fail register3300. The control logic3200is configured to output the first selection signal P1SEL. In an example, the control logic3200is configured to activate the first selection signal P1SEL when a read or program operation of the first plane3100ais executed. For example, the control logic3200may activate the first selection signal P1SEL using a plane address. That is, when the first plane3100ais selected by the plane address, the first selection signal P1SEL may be activated. In an example, the control logic3200is configured to deactivate the first selection signal P1SEL when the first pass/fail signal PF1is activated. For example, when the first pass/fail signal PF1is activated, the control logic3200may deactivate the first selection signal PF1regardless of other conditions, that is, regardless of the plane address. That is, when the first plane3100ais program-passed, the first plane3100amay be deactivated.

The control logic3200is configured to receive the second pass/fail signal PF2from the second pass/fail register3400. The control logic3200is configured to output the second selection signal P2SEL. In an example, the control logic3200is configured to activate the second selection signal P2SEL when a read or program operation of the second plane3100bis executed. For example, the control logic3200may activate the second selection signal P2SEL using the plane address. That is, when the second plane3100bis selected by the plane address, the second selection signal P2SEL may be activated. In an example, the control logic3200is configured to deactivate the second selection signal P2SEL when the second pass/fail signal PF2is activated. For example, when the second pass/fail signal PF2is activated, the control logic3200may deactivate the second selection signal PF2regardless of other conditions, that is, regardless of the plane address. That is, when the second plane3100bis program-passed, the second plane3100bmay be deactivated.

FIG. 13is a flow chart showing a program operation of the flash memory device3000shown inFIG. 12. Referring toFIGS. 12 and 13, in a step S510, a multi-plane program operation is started. For example, addresses and data may be received from the controller2000shown inFIG. 11. The received addresses may include addresses of the first plane3100aand addresses of the second plane3100b, because the multi-plane program operation has started. The received data may also include data to be programmed into the first plane3100aand data to be programmed into the second plane3100b.

The control logic3200may activate the first selection signal P1SEL based on the received addresses of the first plane3100a. The control logic3200may activate the second selection signal P2SEL based on the received addresses of the second plane3100b.

In a step S520, a program operation is executed. The program operation of the first plane3100aand the program operation of the second plane3100bmay be executed at the same time, because the first and second selection signals P1SEL and P2SEL are activated.

For example, bit lines of the first plane3100amay be set up based on the received data of the first plane3100a. At least one word line of the first plane3100amay be selected based on the received addresses of the first plane3100a. A program voltage may be applied to the selected word line of the first plane3100a, and a pass voltage may be applied to unselected word lines of the first plane3100a. Likewise, bit lines of the second plane3100bmay be set up based on the received data of the second plane3100b. At least one word line of the second plane3100bmay be selected based on the received addresses of the second plane3100b. A program voltage may be applied to the selected word line of the second plane3100b, and a pass voltage may be applied to unselected word lines of the second plane3100b. The program operations of the first and second planes3100aand3100bmay be executed simultaneously, because the multi-plane program operation is started.

In a step S530, a verify operation is executed. For example, the bit lines of the first plane3100amay be set up by a predetermined positive voltage, that is, a power supply voltage. A verify voltage may be applied to the word lines of the first plane3100a. Whether the first plane3100ais program-passed or program-failed is determined according to changes of voltages of the bit lines of the first plane3100a. The bit lines of the second plane3100bmay be set up by a predetermined positive voltage, that is, a power supply voltage. A verify voltage may be applied to the word lines of the second plane3100b. Whether the second plane3100bis program-passed or program-failed is determined according to changes of voltages of the bit lines of the second plane3100b. In an example, the verify operation of the first plane3100aand the verify operation of the second plane3100bmay be executed simultaneously, because the multi-plane program operation is started.

In a step S540, it is determined whether one of the multi-planes, that is, the first and the second planes3100aand3100b, is program-passed. When there is no program-passed plane, the program operations of the first and the second planes3100aand3100bmay be executed once again in the step S520. The steps S520to S540may be repeated until one of the first and second planes3100aand3100bis program-passed.

When one of the first and second planes3100aand3100bis program-passed, a step S550is executed. As an example, it is assumed that the first plane3100ais program-passed and, further, it is assumed that the first plane3100ais program-passed before the second plane3100bis program-passed. That is, it is assumed that the first plane3100ais program-passed and the second plane3100bis program-failed. At this time, the first plane3100amay activate the first pass/fail signal PF1. The activated first pass/fail signal PF1may be stored into the first pass/fail register3300.

In the step S550, the program operation of the program-passed plane is completed. The program operation of the first plane3100amay be completed, because it is assumed that the first plane3100ais program-passed. That is, the program operation of the first plane3100amay not be executed any more.

For example, the control logic3200may operate in response to the first pass/fail signal PF1stored in the first pass/fail register3300. The control logic3200may deactivate the first selection signal P1SEL in response to the activation of the first pass/fail signal PF1. When the first pass/fail signal PF1is activated, the control logic3200may deactivate the first selection signal P1SEL regardless of other conditions, that is, the plane addresses. Thus, the first plane3100amay be deactivated. When the first plane3100ais deactivated, the program operation of the first plane3100amay not be executed.

The first pass/fail signal PF1is being stored in the first pass/fail register3300. When the first plane3100ais program-passed, the activated first pass/fail signal PF1is being stored in the first pass/fail register3300. The control logic3200subsequently deactivates the first selection signal P1SEL in response to the activated first pass/fail signal PF1stored in the first pass/fail register3300. Thus, the program operation of the first plane3100awill not be executed any more. That is, the program operation of the first plane is completed.

In a step S560, the program operation of the program-failed plane is executed. The program operation of the second plane3100bmay be executed because it is assumed that the second plane3100bis program-failed. For example, the bit lines of the second plane3100bmay be set up and may be set up based on the verification result of the step S530. As described above, the program voltage may be applied to the selected word line of the second plane3100b, and the pass voltage may be applied to the unselected word lines of the second plane3100b. That is, the program operation of the second plane3100bmay be continued, even though the program operation of the first plane3100ais completed.

In a step S570, it is determined whether all planes are program-passed. For example, it is determined whether both the first and the second planes3100aand3100bare program-passed. It is assumed that the first plane3100ais program-passed in the step S540. Thus, if the second plane3100bis program-passed, the multi-plane program operation may be completed. If the second plane3100bis program-failed, the program operation of the second plane3100bmay be executed once again in the step S560. The steps S560and S570may be repeated until the second plane3100bis found to be program-passed. That is, the program operation of the second plane3100bmay be executed repeatedly until the second plane3100bis found to be program-passed. That is, the program operation of the second plane3100bmay be continuously repeated.

When the second plane3100bis program-passed, the second plane3100bwill activate the second pass/fail signal PF2. The activated second pass/fail signal PF2is stored into the second pass/fail register3400. When the first and second pass/fail signals PF1and PF2are activated, the control logic3200can complete the multi-plane program operation.

As described above, the flash memory device3000according to an exemplary embodiment of the present invention executes the multi-plane program operation of the first and second planes3100aand3100b. When the first plane3100ais program-passed prior to the second plane3100b, the first plane3100ais deactivated. The program operation of the second plane3100bis repeated until the second plane3100bis program-passed. That is, the first plane3100ais deactivated while the second plane3100bis programmed. Thus, disturbances due to a program voltage and a pass voltage are prevented in the program-passed first plane3100a, while the program operation is executed in the second plane3100b. Thus, reliabilities of the flash memory device3000are advanced.

In the exemplary embodiments described above, it is assumed that the first plane3100ais program-passed before the second plane3100bis program-passed. It will be understood, however, that the first and second planes3100aand3100bcan be program-passed simultaneously. In this case, the program operations of the first and second planes3100aand3100bmay be completed simultaneously.

FIG. 14is a flow chart showing an erase operation of the flash memory device3000shown inFIG. 12. Referring toFIGS. 12 and 14, in a step S610, a multi-plane erase operation is started. As an example, addresses may be received from the controller2000shown inFIG. 11. The received addresses may include addresses of the first plane3100aand addresses of the second plane3100b, because the multi-plane erase operation is started. The control logic3200can activate the first selection signal P1SEL based on the received addresses of the first plane3100a. The control logic3200can activate the second selection signal P2SEL based on the received addresses of the second plane3100b.

In a step S620, an erase operation is executed. The erase operation of the first plane3100aand the erase operation of the second plane3100bmay be executed at the same time, because the first and second selection signals P1SEL and P2SEL are activated.

As an example, bit lines of the first plane3100amay be floated. An erase voltage, that is, a ground voltage, may be applied to word lines of the first plane3100a. A bulk voltage, that is, a high voltage, may be supplied to a bulk area of the first plane3100a. Bit lines of the second plane3100bmay be floated. An erase voltage, that is, a ground voltage, may be applied to word lines of the second plane3100b. A bulk voltage, that is, a high voltage, may be supplied to a bulk area of the second plane3100b. The erase operations of the first and second planes3100aand3100bmay be executed simultaneously, because the multi-plane erase operation is started.

In a step S630, a verify operation is executed. For example, the bit lines of the first plane3100amay be set up by a predetermined voltage, that is, a power supply voltage. A verify voltage, that is, a ground voltage, may be applied to the word lines of the first plane3100a. Whether the first plane3100ais erase-passed or erase-failed is determined according to changes of voltages of the bit lines of the first plane3100a. The bit lines of the second plane3100bmay be set up by a predetermined voltage, that is, a power supply voltage. A verify voltage, that is, a ground voltage, may be applied to the word lines of the second plane3100b. Whether the second plane3100bis erase-passed or erase-failed is determined according to changes of voltages of the bit lines of the second plane3100b. In an example, the verify operation of the first plane3100aand the verify operation of the second plane3100bmay be executed simultaneously, because the multi-plane erase operation is started.

In a step S640, it is determined whether one of the multi-planes, that is, the first and the second planes3100aand3100b, is erase-passed. When there is no erase-passed plane, the erase operations of the first and the second planes3100aand3100bmay be executed in the step S620. The steps S620to S640may be repeated until one of the first and second planes3100aand3100bis erase-passed.

When one of the first and second planes3100aand3100bis erase-passed, a step S650is executed. As an example, it is assumed that the first plane3100ais erase-passed and it is assumed that the first plane3100ais erase-passed before the second plane3100bis erase-passed. That is, it is assumed that the first plane3100ais erase-passed and the second plane3100bis erase-failed. At this time, the first plane3100amay activate the first pass/fail signal PF1. The activated first pass/fail signal PF1may be stored into the first pass/fail register3300.

In the step S650, the erase operation of the erase-passed plane is completed. The erase operation of the first plane3100amay be completed because it is assumed that the first plane3100ais erase-passed. That is, the erase operation of the first plane3100awill not be executed any more.

As an example, the control logic3200can operate in response to the first pass/fail signal PF1stored in the first pass/fail register3300. The control logic3200can deactivate the first selection signal P1SEL in response to the activation of the first pass/fail signal PF1. When the first pass/fail signal PF1is activated, the control logic3200can deactivate the first selection signal P1SEL regardless of other conditions, that is, the plane addresses. Thus, the first plane3100amay be deactivated. When the first plane3100ais deactivated, the erase operation of the first plane3100awill not be executed.

The first pass/fail signal PF1is stored in the first pass/fail register3300. When the first plane3100ais erase-passed, the activated first pass/fail signal PF1is stored in the first pass/fail register3300. The control logic3200subsequently deactivates the first selection signal P1SEL in response to the activated first pass/fail signal PF1stored in the first pass/fail register3300. Thus, the erase operation of the first plane3100awill not be executed any more. That is, the erase operation of the first plane may be deemed to be completed.

In a step S660, the erase operation of the erase-failed plane is executed. The erase operation of the second plane3100bmay be executed because it is assumed that the second plane3100bis erase-failed. For example, the bit lines of the second plane3100bmay be floated. An erase voltage, that is, a ground voltage may be applied to the word lines of the second plane3100b. A bulk voltage, that is, a high voltage may be supplied to a bulk area of the second plane3100b. That is, the erase operation of the second plane3100bwill be continued, even though the erase operation of the first plane3100ais completed.

In a step S670, it is determined whether all planes are erase-passed. For example, it is determined whether both the first and the second planes3100aand3100bare erase-passed. It is assumed that the first plane3100ais erase-passed in the step S640. Thus, if the second plane3100bis erase-passed, the multi-plane erase operation may be deemed to be completed. If the second plane3100bis erase-failed, the erase operation of the second plane3100bcan be executed in the step S660. The steps S660and S670may be repeated until the second plane3100bis erase-passed. That is, the erase operation of the second plane3100bwill be executed repeatedly until the second plane3100bwill be erase-passed. That is, the erase operation of the second plane3100bmay be continued.

when the second plane3100bis erase-passed, the second plane3100bcan activate the second pass/fail signal PF2. The activated second pass/fail signal PF2is stored into the second pass/fail register3400. When the first and second pass/fail signals PF1and PF2are activated, the control logic3200can complete the multi-plane erase operation.

As described above, the flash memory device3000according to an exemplary embodiment of the present invention executes the multi-plane erase operation of the first and second planes3100aand3100b. When the first plane3100ais erase-passed prior to the second plane3100b, the first plane3100ais deactivated. The erase operation of the second plane3100bis repeated until the second plane3100bis deemed to be erase-passed. That is, the first plane3100ais deactivated while the second plane3100bis erased. Thus, disturbances due to an erase voltage and a bulk voltage are prevented in the erase-passed first plane3100a, while the erase operation is executed in the second plane3100b. Thus, reliabilities of the flash memory device3000are advanced.

In the exemplary embodiments described above, it is assumed that the first plane3100ais erase-passed before the second plane3100bis erase-passed. It may be understood, however, that the first and second planes3100aand3100bcan be erase-passed simultaneously. In this case, the erase operations of the first and second planes3100aand3100bcan be completed simultaneously.

The program operation and the erase operation of the flash memory device3000inFIG. 12are now described referring toFIGS. 13 and 14. Operations of the flash memory device3000according to the exemplary embodiments of the present invention, however, are not limited by the terms “program operation” and “erase operation”. For example, the erase operation may indicate an operation in which memory cells of the first and second planes3100aand3100bare adjusted to an erase state. That is, it will be understood that the program operation can include the erase operation.

For example, it may be understood that the flash memory device1000described referring toFIGS. 1 to 10can be configured to interrupt an erase voltage and/or a bulk voltage during the erase operation.

The flash memory device3000including the first and second planes3100aand3100bis described referring toFIGS. 12 to 14. The flash memory device3000, however, is not limited to a device including just two planes. For example, the flash memory device3000may include two or more planes as described referring toFIGS. 1 to 10.

FIG. 15is a flow chart describing a program operation of the flash memory device1000or3000, which includes a plurality of planes. Referring toFIG. 15, in a step S710, the multi-plane program operation is started. For example, as described referring to the step S510inFIG. 13, addresses and data may be provided to selected planes for the multi-plane program operation. In another example, as described referring to the step S610inFIG. 14, addresses are received for selected planes for the multi-plane erase operation.

In a step S720, the program operation is executed. The program operation executed in the step S720may include the erase operation.

In a step S730, it is determined whether a program-passed plane exists. If a program-passed plane does not exist, the program operation is executed once again in the step S720. That is, the program operation is repeated until at least one program-passed plane exists. If the program-passed plane exists, a step S740is executed.

In the step S740, it is determined whether all planes are program-passed. If all planes are program-passed, the multi-plane program operation is completed. If at least one plane is program-failed, a step S750is executed.

In the step S750, the program operation of the program-passed plane is completed. For example, as described referring toFIGS. 13 and 14, the program-passed plane may be deactivated. In another example, as described referring toFIGS. 1 to 10, the provision of a program, pass, or high voltage to the program-passed plane may be interrupted. Then, in the step S720, the program operation is executed.

The program operation of the program-passed plane is completed in the step S750. Thus, the program operation of the program-passed planes need not be executed once again in step S720. The program operation of the program-failed plane may not be completed is the step S750. Thus, the program operation of the program-failed plane may be executed once again in the step S720. That is, the program operation of the program-passed plane is completed, and the program operation of the program-failed plane is continued. The steps S720to S750may be repeated until all planes will be determined to be program-passed. That is, the program operation of the program-failed plane is repeated until all planes will be program-passed.

As described above, the flash memory device1000or3000according to exemplary embodiments of the present invention executes the multi-plane program operation. The program operation of the program-passed plane is completed, and the program operation of the program-failed plane is continued. Thus, disturbances in the program-passed plane are prevented. Thus, reliabilities of the flash memory device1000or3000are advanced.

FIG. 16is a block diagram illustrating the first plane3100ashown inFIG. 12. The second plane3100binFIG. 12has a structure identical to the first plane3100a. Thus, descriptions of the second plane3100bare omitted in the interest of brevity.

Referring toFIG. 16, the first plane3100aincludes a memory cell array3110, a row selector circuit3120, a page buffer circuit3130, a column selector circuit3140and a pass/fail check circuit3150.

The memory cell array3110is divided into a plurality of memory blocks BLK1, BLK2, . . . BLKm. Each memory block includes a plurality of pages. For example, inFIG. 16, there is illustrated the first memory block BLK1that includes first to n-th pages PAGE1, PAGE2, . . . PAGEn. All of the memory blocks BLK1to BLAB may have the same structure. Furthermore, both the i-th memory block BLKi (not shown) of the first plane3100aand the i-th memory block BLKi (not shown) of the second plane3100b, for example, may be programmed simultaneously in the multi-plane program operation. Furthermore, both the j-th page PAGEj (not shown) of the i-th memory block BLKi of the first plane3100aand the j-th page PAGEj of the i-th memory block BLKi (not shown) of the second plane3100b, for example, may be programmed simultaneously in the multi-plane program operation.

The row selector circuit3120, the page buffer circuit3130, the column selector circuit3140, and the pass/fail check circuit3150may be configured to operate the same as the row selector circuit120, the page buffer circuit130, the column selector circuit140and the pass/fail check circuit150described hereinabove relative toFIGS. 1 to 10.

The row selector circuit3120, the page buffer circuit3130, the column selector circuit3140, and the pass/fail check circuit3150may be configured to operate in response to a control of the control logic3200. The row selector circuit3120, the page buffer circuit3130, the column selector circuit3140, and the pass/fail check circuit3150may be configured to operate in response to the first selection signal P1SEL described hereinabove relative toFIGS. 11 to 15.

In an example, the row selector circuit3120, the page buffer circuit3130, the column selector circuit3140, and the pass/fail check circuit3150are configured to receive control signals (not shown) and the first selection signal P1SEL from the control logic3200. When the first selection signal P1SEL is active, the row selector circuit3120, the page buffer circuit3130, the column selector circuit3140, and the pass/fail check circuit3150operate normally in response to the control signals. When the first selection signal P1SEL is inactive, the row selector circuit3120, the page buffer circuit3130, the column selector circuit3140, and the pass/fail check circuit3150may be inactive, regardless of the other control signals from the control logic3200.

For example, the control logic3200may provide a control signal for controlling the row selector circuit3120, and the control signal may be inputted to an AND logic circuit (not shown) with the first selection signal P1SEL. An output of the AND logic circuit may be used as a control signal for controlling the row selector circuit3120. That is, when the first selection signal P1SEL is activated, a control signal from the control logic3200may be transferred to the row selector circuit3120. When the first selection signal P1SEL is deactivated, a control signal will not be transferred to the row selector circuit from the control logic3200.

Similarly, the control logic3200may provide control signals for controlling the page buffer circuit3130, the column selector circuit3140and the pass/fail check circuit3150, and the control signals may be respectively inputted to AND logic circuits with the first selection signal P1SEL. Outputs from the AND logic circuit may be used as control signals for controlling the page buffer circuit3130, the column selector circuit3140, and the pass/fail check circuit3150respectively.

FIG. 17is a block diagram illustrating a memory system30that is another embodiment of the memory system10shown inFIG. 11. Referring to theFIG. 16, the memory system30includes the flash memory device1000or3000and the controller2000.

The flash memory device1000or3000includes a plurality of flash memory chips. The plurality of flash memory chips is divided into a plurality of chip groups, each of which comprises a channel used to communicate with the controller2000. InFIG. 17, there is illustrated the plurality of flash memory chips that comprises first to k-th channels CHI to CHk, respectively. The flash memory device1000or3000may be configured to operate the same as described hereinabove relative toFIGS. 1 to 16.

The controller2000is configured to communicate with the flash memory device1000or3000via the first to k-th channels CHI to CHk. The controller2000may be configured to operate the same as described hereinabove relative toFIG. 11. The controller2000is described more particularly referring toFIG. 19.

For example, as described hereinabove relative toFIG. 11, it will be understood that the flash memory device1000or3000and the controller2000can comprise a memory card or an SSD. It also will be understood that the flash memory device1000or3000and the controller2000can be an element of one of various electronic devices.

FIG. 18is a flow chart for describing the memory systems10and30inFIGS. 11 and 17, respectively. Referring toFIG. 18, in a step S810, the controller2000issues the multi-plane program operation. For example, the controller2000may issue the multi-plane program operation in response to a request from a host (not shown).

In a step S820, the controller2000transmits addresses and data. For example, the addresses and data may be received from a host (not shown). The addresses and data may correspond to planes to be selected at the multi-plane program operation. For example, when p planes are selected for the multi-plane program operation, the controller2000can transmit the addresses and data that correspond to the p planes, respectively.

In a step S830, the flash memory device1000or3000receives the addresses and data from the controller2000. In a step S840, the flash memory device1000or3000starts the multi-plane program operation.

In a step S850, the flash memory device1000or3000completes the program operation of the program-passed plane, while the program operation of the program-failed plane is continued. For example, the flash memory device1000or3000may execute the program operation as described hereinabove relative toFIGS. 1 to 17. When all planes are program-passed, the multi-plane program operation is completed.

In a step S850, the flash memory device1000or3000transmits to the controller2000a response signal indicating that the multi-plane program operation is completed. For example, the flash memory device1000or3000transmits the response signal by activating or deactivating a ready/busy signal.

In a step S870, the controller2000receives the response signal generated in a step S860from the flash memory device1000or3000. Then, the controller2000can access the flash memory device1000or3000.

As described referring toFIGS. 1 to 18, during the multi-plane program operation, the program-passed plane is deactivated or the provision of power to the program-passed plane is interrupted. Thus, power consumption of the flash memory device1000or3000may be reduced.

In an example, power for operating the flash memory device1000or3000is supplied from the controller2000. Thus, it may be understood that power consumption of the memory systems10and30is reduced.

FIG. 19is a block diagram of the controller2000shown inFIGS. 11 and 17. Referring toFIG. 19, the controller2000includes a system bus2100, a processor2200, a RAM2300, a host interface2400, an error correcting block2500, and a memory interface2600.

The system bus2100provides communication channels between the various elements of the controller2000. The processor2200is configured to control various operations of the controller2000. More specifically, the processor2200is configured to control operations of the flash memory device1000or3000. The processor2200is configured to drive firmware for controlling the controller2000and the flash memory device1000or3000. For example, the processor2200is configured to drive a flash translation layer (FTL), a host driver, and the like.

The RAM2300is used as a work, or operating, memory of the controller2000. For example, the processor2200is configured to drive the firmware using the RAM2300. In another example, the RAM2300may be used as a buffer memory between the host (not shown) and the flash memory device1000or3000.

The host interface2400includes a protocol for communicating with the host. For example, the host interface2400is configured to communicate with the host using one of various protocols such as a USB, a MMC, a PCI, a PCI-E, an ATA, a SATA, a PATA, a SCSI, an ESDI, an IDE, an EIDE, and the like.

The error correcting block2500is configured to generate parities of data to be transmitted to the host or the flash memory device1000or3000. The generated parities are transferred to the flash memory device1000or3000with corresponding data. When data is received from the flash memory device1000or3000, corresponding parities are received together. The error correcting block2500is configured to detect and correct errors of the received data using the received parities.

The error correcting block2500includes an error control code (ECC) for detecting and correcting errors. For example, the ECC includes a cyclic redundancy check code (CRC code), a Bose, Chaudhuri, and Hocquenghem code (BCH code), a Reed-Solomon code (RS code), and the like.

The memory interface2600includes a protocol for communicating with the flash memory device1000or3000. For example, the memory interface2600may include a NAND protocol.

FIG. 20is a block diagram illustrating a computing system500including the memory system10or30inFIG. 11or17, respectively. Referring toFIG. 20, the computing system500according to an exemplary embodiment of the present invention includes a central processing unit4100(CPU), a RAM4200, a user interface4300, a power supply4400, and the memory system10or30.

The memory system10or30is electrically connected with the CPU4100, the RAM4200, the user interface4300, and the power supply4400via the system bus4500. Data provided through the user interface4300or processed by the CPU4100is stored into the memory system10or30. The memory system10or30includes the controller2000and the flash memory device1000or3000.

When the memory system10or30is embedded as an SSD, a booting speed of the computing system4000can be advanced extremely. Even though not shown inFIG. 20, it may be understood to one having ordinary skill in the related art that the memory system10or30may further include elements, such as an application chipset, camera image processor, and the like.

As described above, according to exemplary embodiments of the present invention, the program operation of the program-passed plane is completed. That is, disturbances due to a program voltage, for example, a program voltage, a pass voltage, a high voltage, an erase voltage, and the like, to the program-passed plane are prevented. If disturbances are prevented, distributions of the threshold voltages of the memory cells may be reduced. Thus, according to the exemplary embodiments of the present invention, errors are reduced at a read operation. That is, it will be understood that an error correcting capability of the flash memory device1000or3000is advanced.

When a cell-per-bit number increases, margins between logic states programmed into the memory cells decrease. That is, when the number of bits stored per memory cell increases, disturbances may be increased. According to exemplary embodiments of the present invention, disturbances in the program-passed plane are prevented. Thus, it will be understood that the effects of the exemplary embodiments of the present invention increase when the number of bits stored per memory cell increases.

According to exemplary embodiments of the present invention, the program operation of the program-passed plane is completed. That is, a program voltage, for example, a program voltage, a pass voltage, a high voltage, an erase voltage, and the like, is not supplied to the program-passed plane. Thus, power consumption is reduced during the program operation.