Three capacitor stack and associated methods

A three capacitor stack and associated methods are shown. An exemplary capacitor device may include a first capacitor stack that includes a first plurality of layers of reference electrodes interleaved with first capacitor electrodes, a second capacitor stack on the first capacitor stack that includes a second plurality of layers of reference electrodes interleaved with second capacitor electrodes, and a third capacitor stack on the second capacitor stack that includes a reference electrode and a third capacitor electrode. A respective layer of dielectric material is formed between the reference electrodes and the first capacitor electrodes, the second capacitor electrodes, and the third capacitor electrode.

BACKGROUND

In power delivery network design, various resonant frequency capacitors may be applied at various locations to provide a full system-om-chip (SoC) load requirement. Miniaturization of an overall solution sizes, particularly for small computing device designs having a large processing core, a system-in-device approach is becoming more prevalent. To support the miniaturization of solution sizes, a reduction in size and/or quantity of devices/components may be desirable.

DESCRIPTION OF EMBODIMENTS

Although the present disclosure uses elements of semiconductor chip devices, and their method of manufacture as an example, the disclosure is not so limited. Examples of the present disclosure may be used in any technology where formation of a solder ball in a solder resist layer is controlled.

FIG. 1shows an example of a power delivery network100having a three-in-one capacitor according to some embodiments of the disclosure. The PDN may include a system in package (SiP)110that includes a voltage regulator120. The SiP110may include circuitry112to provide power to a voltage regulator120. The circuitry112may include resistors, inductors, capacitors, etc., to provide the power, meet load requirements, and filter out frequencies.

The voltage regulator120may include circuitry122and a capacitor device130to provide a regulated voltage VOUT and a reference voltage VSS. The circuitry122may include transistors, diodes, inductors, etc., to provide the VOUT and VSS voltages with proper loading.

The capacitor device130may include a first capacitor132, a second capacitor134, and a third capacitor136to filter out frequencies in the in the VOUT and VSS voltages. IN some examples, multiple resonant frequencies may need to be filtered out. In some examples, the first capacitor132, the second capacitor134, and the third capacitor136may each be targeted to a different frequency. For example, each of the first capacitor132, the second capacitor134, and the third capacitor136may have different capacitances, with the individual capacitances targeted to filtering a specific frequency. In some examples, rather than including the first capacitor132, the second capacitor134, and the third capacitor136in two or more separate devices, the first capacitor132, the second capacitor134, and the third capacitor136may be included in a single capacitor device130. In some examples, the capacitor device130may included in a chipset. In some examples, the capacitor device130may be attached to a board as part of the chipset.

FIGS. 2A and 2Bdepict schematic views of a capacitor device200that includes three capacitors according to an embodiment of the disclosure.FIG. 2Adepicts a top-down schematic view of the capacitor device200.FIG. 2Bdepicts a cross-sectional view of the capacitor device200along cross-section line A. The capacitor device200ofFIGS. 2A and 2B, respectively, may include some of the same materials/layers/components. Those materials/layers/components that are common among each of the views of the capacitor device200ofFIGS. 2A and 2Buse common reference numbers. In the interests of brevity and clarity, description of the formation of these common layers/materials/components will not be repeated for each figure.

Turning now toFIGS. 2A and 2B, the capacitor device200may include a stack of alternating reference electrode layers214and capacitor electrode layers224,234, and244separated by a dielectric layer dielectric layer204to form a first capacitor220, a second capacitor230, and a third capacitor240. In some examples, the capacitor device200is a multi-layer ceramic chip capacitor (MLCC) device. The common conductors210may include the reference electrodes214connected to a reference contact214on a first side of the capacitor device200. The reference contact212may be coupled to a reference voltage VSS. The first capacitor220may include first capacitor electrodes224connected a second contact222on a second side of the capacitor device200. The second contact222may be coupled to a first voltage VCC0. The second capacitor230may include second capacitor electrodes234connected to a third contact232on a third side of the capacitor device200. The third contact232may be coupled to a second voltage VCC1. The third capacitor240may include third capacitor electrodes244connected to a fourth contact242. The fourth contact242may be coupled to a third voltage VCC2on a fourth side of the capacitor device200.

The following discussion of layers of electrodes references focuses on the capacitor electrodes224,234, and244associated with each of the first capacitor220, the second capacitor220, and the third capacitor240, respectively. It is understood that each of the first capacitor220, the second capacitor220, and the third capacitor240also include alternating or interleaved layers of the reference electrodes214to form the first capacitor220, the second capacitor220, and the third capacitor240. A count of layers of the capacitor electrodes224,234, and244, along with a material of the capacitor electrodes224,234, and244, a thickness of the dielectric layer204between adjacent reference/capacitor electrodes214,224,234, and244, and an active area where the adjacent reference/capacitor electrodes overlap with each other in the “A” direction, may set the capacitance of each of the first capacitor220, the second capacitor230, and the third capacitor240, respectively. For example, the first capacitor220may have a capacitance associated with 9 electrodes224of a first conductive material, the second capacitor230may have a capacitance associated with 3 electrodes234of a second conductive material, and the third capacitor240may have a capacitance associated with 2 electrodes244of a third conductive material.

The reference electrodes214may include a fourth conductive material. In some examples, the first, second, third, and fourth conductive materials may all be the same conductive material. In other examples, the first, second, third, and fourth conductive materials may each be a different material. In other examples, the first, second, third, and fourth may be any combination of the same or different materials. In some examples, respective one of the electrodes of the reference electrodes214may match include a material that is the same as a material of electrodes of the associated one of the first capacitor220, the second capacitor230, or the third capacitor240. For example, the individual ones of the reference electrodes214that are interleaved with the capacitor electrodes224of the first capacitor220may have a same material as the capacitor electrodes224, the individual ones of the reference electrodes214that are interleaved with the capacitor electrodes234of the second capacitor230may have a same material as the capacitor electrodes234, and the individual ones of the reference electrodes214that are interleaved with the capacitor electrodes244of the third capacitor240may have a same material as the capacitor electrodes244.

The first, second, third, and fourth conductive materials may include a metal material, such as palladium alloys, silver alloys, nickel alloys, copper alloys, or combinations thereof. Other conductive materials may be used for the first, second, third, and fourth conductive materials, such as copper or copper alloys, aluminum or aluminum alloys, etc. The contacts212,222,232, and242may also include metal materials. In some examples, each of the contacts212,222,232, and242may include the same material as the material of the reference/capacitor electrode214,224,234, and244to which it is connected. In another example, the212,222,232, and242may each include a same material, regardless of a material the associated reference/capacitor electrodes214,224,234, or244. In some examples, the contacts212,222,232, and242may include silver, copper, nickel, aluminum, etc. In some examples, the dielectric layer204may include a ceramic material. For example, the dielectric layer204may include a paraelectric material, such as Titanium dioxide (TiO), a ferroelectric material, such as barium titanate (BaTiO). The dielectric layer204may further include additives, such as aluminum silicate, magnesium silicate, aluminum oxide, Zinc, Zirconium, Niobium, Magnesium, Tantalum. Cobalt or Strontium. A dielectric thickness between a gap of a reference electrode214and an adjacent ones of the electrodes224,234, or244may be less than 0.5 μm.

The count of the capacitor electrodes224,234, and244associated with each of the first capacitor220, the second capacitor230, and the third capacitor240, respectively, depicted inFIG. 2Bare exemplary. The capacitor device200may include more or fewer capacitor electrodes224,234, and244(and a corresponding more or fewer count of the reference electrodes214) associated with each of the first capacitor220, the second capacitor230, and the third capacitor240, respectively, based on a desired capacitance of each of the first capacitor220, the second capacitor230, and the third capacitor240. In some examples, a count of capacitor electrodes224,234, and244associated with at least one of the first capacitor220, the second capacitor230, and the third capacitor240, respectively, may include 10 or more electrodes, 100 or more electrodes, etc. A total count of reference/capacitor electrodes214,224,234, and244in the capacitor device200may be limited by a height restriction associated with the capacitor device200.

As depicted inFIG. 2B, a count of the capacitor electrodes224associated with the first capacitor220may be different than a count of the capacitor electrodes234associated with the second capacitor230or a count of the capacitor electrodes244associated with the third capacitor240. In some examples, the first capacitor220, the second capacitor230, or the third capacitor240may have a same count of capacitor electrodes224,234, and244, respectively, as another of the first capacitor220, the second capacitor230, or the third capacitor240. In some examples, each of the capacitors220,230, and240may have an order of magnitude fewer number of electrodes than a next smallest size electrode. For example, the first capacitor220may include 100 electrodes, the second capacitor230may include 10 electrodes, and the third capacitor240may include 1 electrode. In one example, the capacitance associated with the first capacitor220may be 47 μF, capacitance associated with the second capacitor230may be 4.7 μF, and capacitance associated with the third capacitor240may be 0.47 μF. In another example, the capacitance associated with the first capacitor220may be 22 μF, capacitance associated with the second capacitor230may be 2.2 μF, and capacitance associated with the third capacitor240may be 0.22 μF.

FIGS. 3A-3Dshow a cross-section schematic view of formation of a device including three capacitors in accordance with embodiments of the disclosure. The device300), device301, device302, and device303ofFIGS. 3A-3D, respectively, may include some of the same materials/layers/components. Those materials/layers/components that are common among all or a subset of the device300, device301, device302, and device303ofFIGS. 3A-3Duse common reference numbers. In the interests of brevity and clarity, description of the formation of these common layers/materials/components will not be repeated for each figure.

Turning now toFIG. 3A, the device300may include a reference electrode stackable unit382and a first capacitor electrode stackable unit384that are stacked in alternating fashion to form a first capacitor stack392. While the first capacitor stack392shows 9 pairs of the reference electrode stackable unit382and the first capacitor electrode stackable unit384, the first capacitor stack392may include more or fewer pairs of the reference electrode stackable unit382and the first capacitor electrode stackable unit384. The reference electrode stackable unit382may include a reference electrode314and a dielectric layer304. The reference electrode314may be offset from the one edge of the dielectric layer304for form a first offset372. The first capacitor electrode stackable unit384may include a second contact322and a dielectric layer304. The first capacitor electrode324may be offset from the one edge of the dielectric layer304for form a second offset374. A length of the first offset372may be equal in length to the second offset374. The reference electrode314and the first capacitor electrode324may include conductive materials. In some examples, the reference electrode314and the first capacitor electrode324may include the same material. In some examples, the reference electrode314and the first capacitor electrode324may include different materials. In some examples, the reference electrode314and/or the first capacitor electrode324may include at least one of palladium or palladium alloys, silver or silver alloys, nickel or nickel alloys, copper or copper alloys, or combinations thereof. In some examples, the dielectric layer304may include a ceramic material. For example, the dielectric layer304may include a paraelectric material, such as Titanium dioxide (TiO), a ferroelectric material, such as barium titanate (BaTiO). The dielectric layer304may further include additives, such as aluminum silicate, magnesium silicate, aluminum oxide, Zinc, Zirconium, Niobium, Magnesium, Tantalum, Cobalt or Strontium. The dielectric may have a thickness of less than 0.5 μm.

Turning now toFIG. 3B, the device301may include a reference electrode stackable unit382and a second capacitor electrode stackable unit386that are stacked in alternating fashion to form a second capacitor stack394. While the second capacitor stack394shows 3 pairs of the reference electrode stackable unit382and the second capacitor electrode stackable unit386, the second capacitor stack394may include more or fewer pairs of the reference electrode stackable unit382and the second capacitor electrode stackable unit386. The second capacitor electrode stackable unit386may include a second capacitor electrode334and a dielectric layer304. The second capacitor electrode334may be offset from the one edge of the dielectric layer304for form the second offset374. The second capacitor electrode334may include a conductive material. In some examples, the second capacitor electrode334may include the same material of the reference electrode314or the first capacitor electrode324. In some examples, the second capacitor electrode334may include different materials than the reference electrode314or the first capacitor electrode324. In some examples, the second capacitor electrode334may include at least one of palladium or palladium alloys, silver or silver alloys, nickel or nickel alloys, copper or copper alloys, or combinations thereof.

Turning now toFIG. 3C, the device302may include a reference electrode stackable unit382and a third capacitor electrode stackable unit388that are stacked in alternating fashion to form a third capacitor stack396. While the third capacitor stack396shows 2 pairs of the reference electrode stackable unit382and the third capacitor electrode stackable unit388, the third capacitor stack396may include more or fewer pairs of the reference electrode stackable unit382and the third capacitor electrode stackable unit388. The third capacitor electrode stackable unit388may include a third capacitor electrode344and a dielectric layer304. The third capacitor electrode344may be offset from the one edge of the dielectric layer304for form the second offset374. The third capacitor electrode344may include a conductive material. In some examples, the third capacitor electrode344may include the same material as one or more of the reference electrode314, the first capacitor electrode324, or the second capacitor electrode334. In some examples, the third capacitor electrode344may include different materials than one or more of the reference electrode314, the first capacitor electrode324, or the second capacitor electrode334. In some examples, the third capacitor electrode344may include at least one of palladium or palladium alloys, silver or silver alloys, nickel or nickel alloys, copper or copper alloys, or combinations thereof.

Turning now toFIG. 3D, the device303may include attachment of a first contact312, a second contact322, a third contact332, and a fourth contact342to the reference electrode314, the first capacitor electrode324, the second capacitor electrode334, and the third capacitor electrode344, respectively. WhileFIG. 3Ddepicts the third contact332only being coupled to one of the second capacitor electrode334, the third contact332is coupled to each of the second capacitor electrode334. Further, whileFIG. 3Ddepicts the fourth contact342only being coupled to one of the third capacitor electrode344, the fourth contact342is coupled to each of the third capacitor electrode344. The first contact312, second contact322, third contact332, and fourth contact342may also include metal materials. In some examples, each of the first contact312, second contact322, third contact332, and fourth contact342may include the same material as the material of the reference electrode314, first capacitor electrode324, second capacitor electrode334, and third capacitor electrode344to which it is connected. In another example, the first contact312, second contact322, third contact332, and fourth contact342may each include a same material, regardless of a material the associated reference electrode314, first capacitor electrode324, second capacitor electrode334, or third capacitor electrode344. In some examples, the first contact312, second contact322, third contact332, and fourth contact342may include silver, copper, nickel, aluminum, etc.

The dielectric layer304may be formed by mixing ceramic powder with binder and solvents to create the slurry. The slurry may be poured onto conveyor belt inside a drying oven, resulting in the dry ceramic tape. This may then cut into square pieces called sheets. The thickness of the sheet may determine a voltage rating of an associated capacitor. For each of the reference electrode314, the first capacitor electrode324, the second capacitor electrode334, and the third capacitor electrode344, an electrode ink is made from a metal powder that is mixed with solvents and ceramic material to make the electrode ink. The reference electrode314, the first capacitor electrode324, the second capacitor electrode334, and the third capacitor electrode344may each be printed onto the ceramic sheets (e.g., the dielectric layer304) using a screen printing process. The ceramic sheets with the printed electrodes may be stacked to form a combined stack of the first capacitor stack392, the second capacitor stack394, and the third capacitor stack396, as depicted and described with reference to the device302ofFIG. 3C. Once stacked, pressure is applied to the combined stack to fuse all the separate layers and create a monolithic structure (e.g., a bar). The bar may be cut into all the separate devices, such as the device302. The separate devices may be fired in kilns. The temperature profile may be very important to the characteristics of the capacitors of the separate devices. The first contact312, the second contact322, the third contact332, and the fourth contact342may be attached to the device302to form the device303. The device303may be included in the capacitor device200ofFIGS. 2A and 2B.

FIG. 4illustrates a method400for forming a three capacitor stack in accordance with some embodiments. The method400may be implemented the capacitor device130ofFIG. 1, the capacitor device200ofFIGS. 2A and 2B, the devices300-303ofFIGS. 3A-DD, or combinations thereof.

The method400may include forming a first capacitor stack that includes a first plurality of layers of reference electrodes interleaved with first capacitor electrodes, at410. The method400may include forming a second capacitor stack on the first capacitor stack that includes a second plurality of layers of reference electrodes interleaved with second capacitor electrodes, at420. The method400may include forming a third capacitor stack on the second capacitor stack that includes a third plurality of layers of reference electrodes interleaved with third capacitor electrodes, at430. A respective layer of dielectric material may be formed between each the reference electrodes and the first electrodes of the first capacitor stack, the second electrodes of the second capacitor stack, and the third electrodes of the third capacitor stack. The first capacitor stack may include the first capacitor stack392ofFIGS. 3A-3C, the second capacitor stack may include the second capacitor stack394ofFIGS. 3B and 3C, and the third capacitor stack may include the first capacitor stack392ofFIG. 3C. The reference electrodes may include the electrodes214ofFIGS. 2A and 2B, the reference electrode314ofFIGS. 3A-3D, or combinations thereof. The first capacitor electrodes may include the first capacitor electrodes224ofFIGS. 2A and 2B, the first capacitor electrode324ofFIGS. 3A-3D, or combinations thereof. The second capacitor electrodes may include the second capacitor electrodes234ofFIGS. 2A and 2B, the second capacitor electrode334ofFIGS. 3B-3D, or combinations thereof. The third capacitor electrodes may include the third capacitor electrodes244ofFIGS. 2A and 2B, the third capacitor electrode344ofFIGS. 3C and 3D, or combinations thereof. The layers of dielectric material may include the dielectric layer dielectric layer204ofFIGS. 2A and 2B, the dielectric layer304ofFIGS. 3A-3D, or combinations thereof.

In some examples, a count of the first plurality of layers is different than a count of the second plurality of layers. In some examples, a count of the second plurality of layers of the second electrode stack is two orders of magnitude greater than a count of the third plurality of layers of the third capacitor stack, and the count of the second plurality of layers of the second electrode stack is two orders of magnitude greater than a count of the first plurality of layers of the first capacitor stack. The method400may further include forming a first contact connected to the first capacitor electrodes of the first electrode stack, forming a second contact connected to the second capacitor electrodes of the second electrode stack, forming a third contact connected to the third electrodes of the third electrode stack, and forming a fourth contact connected to the reference electrodes of the first electrode stack, the second electrode stack, and the third electrode stack. The first, second, third, and fourth contacts may include the first contact224, the second contact234, the third contact244, and the reference contact244, respectively, ofFIGS. 2A and 2B; the first capacitor electrode324, the second capacitor electrode334, the third capacitor electrode344, and the reference contact reference electrode314, respectively, ofFIGS. 3A-3D, or combinations thereof. Forming the first or second layer of the dielectric material may include rolling a slurry of ceramic material into a sheet. In some examples, the layer of the dielectric material may be less than 0.5 μm.

Forming a capacitor stack (e.g., the first, second, or third capacitor stack) may include forming a first stackable unit, forming a second stackable unit, and layering the first stackable unit over the second stackable unit. Forming the first stackable unit may include forming a first layer of the dielectric material and forming a conductive material over the first layer of dielectric material. Forming the second stackable unit may include forming a second layer of dielectric material, and forming a conductive material over the layer of dielectric material. The stackable units may include the reference electrode stackable unit382or the first capacitor electrode stackable unit384ofFIG. 3A, the second capacitor electrode stackable unit386ofFIG. 3B, the third capacitor electrode stackable unit388ofFIG. 3C, or combinations thereof.

Forming the electrodes (e.g., the first, second, or third capacitor electrodes, or the reference electrodes) may include printing a material on a layer of the dielectric material. The material may be the same for the first, second, and third capacitor electrodes, and the reference electrodes, in some examples. In other examples, the material may be different for at least two of the first, second, or third capacitor electrodes, or the reference electrodes. In some examples, the first, second, and third capacitor electrodes, and the reference electrodes may include one of a silver alloy, a palladium alloy, a nickel alloy or a copper alloy.

The method400may further include after forming the third capacitor stack, firing the first capacitor stack, the second capacitor stack, and the third capacitor stack in a kiln. The method400may further include forming a single device having three capacitors using the first electrode stack, the second electrode stack, and the third electrode stack. The single device may include the capacitor device200ofFIGS. 2A and 2B, the device303ofFIG. 3D, or combinations thereof.

FIG. 5illustrates a system level diagram, according to one embodiment of the invention. For instance,FIG. 5depicts an example of an electronic device (e.g., system) including a capacitor device as described in the present disclosure, such as the capacitor device130ofFIG. 1, the capacitor device200ofFIG. 2. The capacitor device303ofFIG. 3D, or combinations thereof.FIG. 5is included to show an example of a higher level device application for the present invention. In one embodiment, system500includes, but is not limited to, a desktop computer, a laptop computer, a netbook, a tablet, a notebook computer, a personal digital assistant (PDA), a server, a workstation, a cellular telephone, a mobile computing device, a smart phone, an Internet appliance or any other type of computing device. In some embodiments, system500is a system on a chip (SOC) system.

In one embodiment, processor510has one or more processing cores512and512N, where512N represents the Nth processor core inside processor510where N is a positive integer. In one embodiment, system500includes multiple processors including510and505, where processor505has logic similar or identical to the logic of processor510. In some embodiments, processing core512includes, but is not limited to, pre-fetch logic to fetch instructions, decode logic to decode the instructions, execution logic to execute instructions and the like. In some embodiments, processor510has a cache memory516to cache instructions and/or data for system500. Cache memory516may be organized into a hierarchal structure including one or more levels of cache memory.

In some embodiments, processor510includes a memory controller514, which is operable to perform functions that enable the processor510to access and communicate with memory530that includes a volatile memory532and/or a non-volatile memory534. In some embodiments, processor510is coupled with memory530and chipset520. Processor510may also be coupled to a wireless antenna578to communicate with any device configured to transmit and/or receive wireless signals. In one embodiment, the wireless antenna interface578operates in accordance with, but is not limited to, the IEEE 802.11 standard and its related family, Home Plug AV (HPAV), Ultra Wide Band (UWB), Bluetooth, WiMax, or any form of wireless communication protocol.

Memory530stores information and instructions to be executed by processor510. In one embodiment, memory530may also store temporary variables or other intermediate information while processor510is executing instructions. In the illustrated embodiment, chipset520connects with processor510via Point-to-Point (PtP or P-P) interfaces517and522. Chipset520enables processor510to connect to other elements in system500. In some embodiments of the invention, interfaces517and522operate in accordance with a PtP communication protocol such as the Intel® QuickPath Interconnect (QPI) or the like. In other embodiments, a different interconnect may be used.

In some embodiments, chipset520is operable to communicate with processor510,505N, display device540, and other devices572,576,574,560,562,564,566,577, etc. Chipset520may also be coupled to a wireless antenna578to communicate with any device configured to transmit and/or receive wireless signals.

Chipset520connects to display device540via interface526. Display540may be, for example, a liquid crystal display (LCD), a plasma display, cathode ray tube (CRT) display, or any other form of visual display device. In some embodiments of the invention, processor510and chipset520are merged into a single SOC. In addition, chipset520connects to one or more buses550and555that interconnect various elements574,560,562,564, and566. Buses550and555may be interconnected together via a bus bridge572. In one embodiment, chipset520couples with a non-volatile memory560, a mass storage device(s)562, a keyboard/mouse564, and a network interface566via interface524and/or504, smart TV576, consumer electronics577, etc.

While the modules shown inFIG. 5are depicted as separate blocks within the system500, the functions performed by some of these blocks may be integrated within a single semiconductor circuit or may be implemented using two or more separate integrated circuits. For example, although cache memory516is depicted as a separate block within processor510, cache memory516(or selected aspects of516) can be incorporated into processor core512.

To better illustrate the methods and device disclosed herein, a non-limiting list of embodiments is provided here:

Example 1 is an apparatus, comprising: a capacitor device comprising: a first capacitor stack, the first capacitor stack including a first plurality of layers of reference electrodes interleaved with first capacitor electrodes, wherein, a respective layer of dielectric material is included in between each of the reference electrodes and the first capacitor electrodes; and a second capacitor stack, the second capacitor stack including a reference electrode layered over a second capacitor electrode, wherein, a respective layer of dielectric material is included in between the reference electrode and the second capacitor electrode.

In Example 2, the subject matter of Example 1 optionally includes a third capacitor stack, the third capacitor stack including a third plurality of layers of reference electrodes interleaved with third capacitor electrodes, wherein, a respective dielectric layer is included in between each of the reference electrodes and the third capacitor electrodes.

In Example 3, the subject matter of Example 2 optionally includes wherein a count of the first plurality of layers is different than a count of the third plurality of layers.

In Example 4, the subject matter of any one or more of Examples 1-3 optionally include a first contact connected to the first capacitor electrodes of the first capacitor stack; a second contact connected to the second capacitor electrode of the second capacitor stack; and a third contact connected to the reference electrodes of the first capacitor stack and the second capacitor stack.

In Example 5, the subject matter of Example 4 optionally includes wherein a first capacitor electrode of the first capacitor electrodes of the first capacitor stack is offset from a first edge of a contacting layer of the dielectric material to provide a gap between the first capacitor electrode and the second contact, and wherein a particular reference electrode of the reference electrodes of the first capacitor is offset from a second edge of the contacting layer of the dielectric material to provide a gap between the particular reference electrode and the first contact.

In Example 6, the subject matter of any one or more of Examples 1-5 optionally include wherein the first capacitor electrodes of the first capacitor stack include a first material, wherein the second capacitor electrode of the second capacitor stack includes a second material; and wherein the reference electrodes of the first capacitor and the second capacitor include a third material.

In Example 7, the subject matter of Example 6 optionally includes wherein the first material is different than the second material.

In Example 8, the subject matter of any one or more of Examples 6-7 optionally include wherein the first material, the second material, and the third material include a same material.

In Example 9, the subject matter of any one or more of Examples 6-8 optionally include wherein the first material and the third material each include one of a silver alloy, a palladium alloy, a nickel alloy or a copper alloy.

In Example 10, the subject matter of any one or more of Examples 1-9 optionally include wherein the dielectric material includes a ceramic material.

In Example 11, the subject matter of any one or more of Examples 1-10 optionally include wherein the device is a multi-layer ceramic chip capacitor.

In Example 12, the subject matter of any one or more of Examples 1-11 optionally include wherein the layer of the dielectric material of the first capacitor electrode is less than 0.5 μm.

In Example 13, the subject matter of any one or more of Examples 1-12 optionally include a voltage regulator that includes the capacitor device.

In Example 14, the subject matter of any one or more of Examples 1-13 optionally include wherein the first capacitor stack has a capacitance value of 47 μF, and wherein the second capacitor stack has a capacitance value of 4.7 μF.

In Example 15, the subject matter of any one or more of Examples 1-14 optionally include wherein a count of the first plurality of layers of the first capacitor stack is an order of magnitude greater than a count of layers of the second capacitor stack.

In Example 16, the subject matter of any one or more of Examples 1-15 optionally include a chipset, wherein the chipset includes the capacitor device.

Example 17 is a capacitor device, the capacitor device comprising: a first capacitor stack that includes a first plurality of layers of reference electrodes interleaved with first capacitor electrodes; a second capacitor stack on the first capacitor stack that includes a second plurality of layers of reference electrodes interleaved with second capacitor electrodes; and a third capacitor stack on the second capacitor stack that includes a reference electrode and a third capacitor electrode, wherein a respective layer of dielectric material is formed between the reference electrodes and the first capacitor electrodes, the second capacitor electrodes, and the third capacitor electrode.

In Example 18, the subject matter of Example 17 optionally includes wherein a count of the first plurality of layers is different than a count of the second plurality of layers.

In Example 19, the subject matter of any one or more of Examples 17-18 optionally include a first contact connected to the first capacitor electrodes of the first capacitor stack; a second contact connected to the second capacitor electrode of the second capacitor stack; a third contact connected to the third capacitor electrode; and a fourth contact connected to the reference electrodes of the first capacitor stack and the second capacitor stack.

In Example 20, the subject matter of Example 19 optionally includes wherein a first capacitor electrode of the first capacitor electrodes of the first capacitor stack is offset from a first edge of a contacting layer of the dielectric material to provide a gap between the first capacitor electrode and the second contact, and wherein a particular reference electrode of the reference electrodes of the first capacitor is offset from a second edge of the contacting layer of the dielectric material to provide a gap between the particular reference electrode and the first contact.

In Example 21, the subject matter of any one or more of Examples 17-20 optionally include wherein the first capacitor electrodes of the first capacitor stack include a first material, wherein the second capacitor electrode of the second capacitor stack includes a second material; and wherein the reference electrodes of the first capacitor and the second capacitor include a third material.

In Example 22, the subject matter of Example 21 optionally includes wherein the first material is different than at least one of the second material or the third material.

In Example 23, the subject matter of any one or more of Examples 21-22 optionally include wherein the first material, the second material, and the third material include a same material.

In Example 24, the subject matter of any one or more of Examples 21-23 optionally include wherein the first material, the second material, and the third material each include at least one of a silver alloy, a palladium alloy, a nickel alloy or a copper alloy.

In Example 25, the subject matter of any one or more of Examples 17-24 optionally include wherein the dielectric material includes a ceramic material.

In Example 26, the subject matter of any one or more of Examples 17-25 optionally include wherein the capacitor device is a multi-layer ceramic chip capacitor.

In Example 27, the subject matter of any one or more of Examples 17-26 optionally include wherein the layer of the dielectric material of the first capacitor electrode is less than 0.5 μm.

In Example 28, the subject matter of any one or more of Examples 17-27 optionally include wherein the first capacitor stack has a capacitance value of 47 μF or 22 μF, wherein the second capacitor stack has a capacitance value of 4.7 μF or 2.2 μF, wherein the third capacitor stack has a capacitance value of 0.47 μF or 0.22 μF.

In Example 29, the subject matter of any one or more of Examples 17-28 optionally include wherein a count of the first plurality of layers of the first capacitor electrode is an order of magnitude greater than a count of the second plurality of layers of the second capacitor.

Example 30 is a method, comprising: forming a first capacitor stack that includes a first plurality of layers of reference electrodes interleaved with first capacitor electrodes; forming a second capacitor stack on the first capacitor stack that includes a second plurality of layers of reference electrodes interleaved with second capacitor electrodes; and forming a third capacitor stack on the second capacitor stack that includes a reference electrode and a third capacitor electrode, wherein a respective layer of dielectric material is formed between the reference electrodes and the first capacitor electrodes, the second capacitor electrodes, and the third capacitor electrode.

In Example 31, the subject matter of Example 30 optionally includes after forming the third capacitor stack, firing the first capacitor stack, the second capacitor stack, and the third capacitor stack in a kiln.

In Example 32, the subject matter of any one or more of Examples 30-31 optionally include wherein a count of the first plurality of layers is different than a count of the second plurality of layers.

In Example 33, the subject matter of any one or more of Examples 30-32 optionally include forming a first contact connected to the first capacitor electrodes of the first capacitor stack; forming a second contact connected to the second capacitor electrodes of the second capacitor stack; and forming a third contact connected to the third capacitor electrode of the third capacitor stack; and forming a fourth contact connected to the reference electrodes of the first capacitor stack, the second capacitor stack, and the third capacitor stack.

In Example 34, the subject matter of Example 33 optionally includes wherein forming the first capacitor stack includes: forming a first stackable unit by: forming a layer of dielectric material; and forming a conductive material over the layer of dielectric material; forming a second stackable unit by: forming a layer of dielectric material; and forming a conductive material over the layer of dielectric material.

In Example 35, the subject matter of any one or more of Examples 30-34 optionally include forming the first capacitor electrodes of the first capacitor stack by printing a first material on a first layer of the dielectric material; forming the second capacitor electrodes of the second capacitor stack by printing a second material on a second layer of the dielectric material; forming the third capacitor electrode of the third capacitor stack by printing a third material on a third layer of the dielectric material; and forming the reference electrodes of the first capacitor stack, the second capacitor stack, and the third capacitor stack by printing a fourth material on a fourth layer of the dielectric material.

In Example 36, the subject matter of Example 35 optionally includes forming the layer of the dielectric material includes rolling a slurry of ceramic material into a sheet.

In Example 37, the subject matter of Example 36 optionally includes wherein the first material is different than the second material.

In Example 38, the subject matter of any one or more of Examples 36-37 optionally include wherein the first material, the second material, and the third material include a same material.

In Example 39, the subject matter of any one or more of Examples 36-38 optionally include wherein the first material, the second material, and the third material each include one of a silver alloy, a palladium alloy, a nickel alloy or a copper alloy.

In Example 40, the subject matter of any one or more of Examples 30-39 optionally include wherein forming a single device having three capacitors using the first capacitor stack, the second capacitor stack, and the third capacitor stack.

In Example 41, the subject matter of any one or more of Examples 30-40 optionally include wherein the layer of the dielectric material of the first capacitor electrode is less than 0.5 μm.

In Example 42, the subject matter of any one or more of Examples 30-41 optionally include wherein a count of the second plurality of layers of the second capacitor stack is two orders of magnitude greater than a count of layers of the third capacitor stack, and wherein the count of the second plurality of layers of the second capacitor stack is two orders of magnitude greater than a count of the first plurality of layers of the first capacitor stack.

Example 43 is a apparatus, comprising: means for forming a first capacitor stack that includes a first plurality of layers of reference electrodes interleaved with first capacitor electrodes; means for forming a second capacitor stack on the first capacitor stack that includes a second plurality of layers of reference electrodes interleaved with second capacitor electrodes; and means for forming a third capacitor stack on the second capacitor stack that includes a reference electrode and a third capacitor electrode, wherein a respective layer of dielectric material is formed between the reference electrodes and the first capacitor electrodes, the second capacitor electrodes, and the third capacitor electrode.

In Example 44, the subject matter of Example 43 optionally includes after the third capacitor stack has been formed, means for firing the first capacitor stack, the second capacitor stack, and the third capacitor stack in a kiln.

In Example 45, the subject matter of any one or more of Examples 43-44 optionally include wherein a count of the first plurality of layers is different than a count of the second plurality of layers.

In Example 46, the subject matter of any one or more of Examples 43-45 optionally include means for forming a first contact connected to the first capacitor electrodes of the first capacitor stack; means for forming a second contact connected to the second capacitor electrodes of the second capacitor stack; and means for forming a third contact connected to the third capacitor electrode of the third capacitor stack; and means for forming a fourth contact connected to the reference electrodes of the first capacitor stack, the second capacitor stack, and the third capacitor stack.

In Example 47, the subject matter of Example 46 optionally includes wherein means for forming the first capacitor stack includes: means for forming a first stackable unit including: means for forming a layer of dielectric material; and means for forming a conductive material over the layer of dielectric material; means for forming a second stackable unit including: means for forming a layer of dielectric material; and means for forming a conductive material over the layer of dielectric material.

In Example 48, the subject matter of any one or more of Examples 43-47 optionally include means for forming the first capacitor electrodes of the first capacitor stack by printing a first material on a first layer of the dielectric material; means for forming the second capacitor electrodes of the second capacitor stack by printing a second material on a second layer of the dielectric material; means for forming the third capacitor electrode of the third capacitor stack by printing a third material on a third layer of the dielectric material; and means for forming the reference electrodes of the first capacitor stack, the second capacitor stack, and the third capacitor stack by printing a fourth material on a fourth layer of the dielectric material.

In Example 49, the subject matter of Example 48 optionally includes means for forming the layer of the dielectric material includes rolling a slurry of ceramic material into a sheet.

In Example 50, the subject matter of Example 49 optionally includes wherein the first material is different than the second material.

In Example 51, the subject matter of any one or more of Examples 49-50 optionally include wherein the first material, the second material, and the third material include a same material.

In Example 52, the subject matter of any one or more of Examples 49-51 optionally include wherein the first material, the second material, and the third material each include one of a silver alloy, a palladium alloy, a nickel alloy or a copper alloy.

In Example 53, the subject matter of any one or more of Examples 43-52 optionally include wherein means for forming a single device having three capacitors using the first capacitor stack, the second capacitor stack, and the third capacitor stack.

In Example 54, the subject matter of any one or more of Examples 43-53 optionally include wherein the layer of the dielectric material of the first capacitor electrode is less than 0.5 μm.

In Example 55, the subject matter of any one or more of Examples 43-54 optionally include wherein a count of the second plurality of layers of the second capacitor stack is two orders of magnitude greater than a count of layers of the third capacitor stack, and wherein the count of the second plurality of layers of the second capacitor stack is two orders of magnitude greater than a count of the first plurality of layers of the first capacitor stack.

These examples are intended to provide non-limiting examples of the present subject matter—they are not intended to provide an exclusive or exhaustive explanation. The detailed description above is included to provide further information about the present devices, and methods.