Memory system and operating method thereof

A memory system includes one or more memory chips, and a repair information storage chip including a nonvolatile memory configured to store a repair information of the one or more memory chips, wherein during an initial operation of the memory system, the repair information stored in the repair information storage chip is transmitted to the one or more memory chips.

BACKGROUND

Exemplary embodiments of the present invention relate to a memory system, and more particularly, to a technology for storing and transmitting repair information in a memory system.

2. Description of the Related Art

FIG. 1is a diagram for illustrating a repair operation of a conventional memory device.

Referring toFIG. 1, the conventional memory device includes a cell array110, a row circuit120, and a column circuit130. The cell array110includes a plurality of memory cells. The row circuit120is configured to enable a word line selected by a row address R_ADD. The column circuit130is configured to access (read or write) data of a bit line selected by a column address C_ADD.

A row fuse circuit140is configured to store a row address, corresponding to a memory cell having a defect in the cell array110, and generate a repair row address REPAIR_R_ADD. A row comparison unit150is configured to compare the repair row address REPAIR_R_ADD stored in the row fuse circuit140to the row address R_ADD inputted from an external source. When the repair row address REPAIR_R_ADD coincides with the row address R_ADD, the row comparison unit150controls the row circuit120to enable a redundant word line instead of the word line designated by the row address R_ADD.

A column fuse circuit160is configured to store a column address, corresponding to a memory cell having a defect in the cell array110, and generate a repair column address REPAIR_C_ADD. A column comparison unit170is configured to compare the repair column address REPAIR_C_ADD from the column fuse circuit160to the column address C_ADD inputted from an external source. When the repair column address REPAIR_C_ADD coincides with the column address C_ADD, the column comparison unit170controls the column circuit130to access a redundant bit line, instead of the bit line designated by the column address C_ADD.

The row fuse circuit140and the column fuse circuit160(hereinafter referred to as the fuse circuits) ofFIG. 1use laser fuses. The laser fuse stores high or low data depending on whether the fuse is cut or not. The laser fuse may be programmed in a wafer state, but may not be programmed after the wafer is mounted in a package. To overcome such a concern, an E-fuse may be used. The E-fuse may include a transistor. When the E-fuse includes a transistor, the E-fuse stores data by changing resistance between a gate and a drain/source.

FIG. 2is a diagram illustrating that the E-fuse including a transistor operates as a resistor or capacitor.

Referring toFIG. 2, the E-fuse includes a transistor T. When a normal power supply voltage which the transistor T may tolerate is supplied to a gate G, the E-fuse operates as a capacitor C. Therefore, there is no current flowing between the gate G and a drain D or source S (hereinafter referred to as a drain-source D-S). However, when a high voltage, which the transistor T may not stand, is applied to the gate G, gate oxide of the transistor T may become inoperable and short the gate G and the drain-source D-S. In this case, the E-fuse operates as a resistor R. Therefore, a current flows between the gate G and the drain-source D-S.

Such a characteristic may be used to recognize the data of the E-fuse through a resistance value between the gate G and the drain-source D-S of the E-fuse. To recognize the data of the E-fuse, (1) the size of the transistor T may be increased to directly recognize the data without a separate sensing operation, or (2) an amplifier may be used to sense a current flowing in the transistor T without increasing the size of the transistor T. In the above-described two methods, however, the transistor T forming the E-fuse must be enlarged, or the amplifier for amplifying data must be provided for each E-fuse. Therefore, both methods have limitations and concerns over the size and space.

Because of the above-described concerns related to the size and space, it may not be easy to apply the E-fuse to the fuse circuits140and160ofFIG. 1. Therefore, as disclosed in U.S. Pat. Nos. 6,904,751, 6,777,757, 6,667,902, 7,173,851, and 7,269,047, researches have been conducted on a method for performing a repair operation using data stored in an E-fuse array including a plurality of E-fuses (in this case, the entire area may be reduced because an amplifier is shared).

SUMMARY

Exemplary embodiments of the present invention are directed to a technology for storing repair information in a memory chip including nonvolatile memories such as an E-fuse array and transmitting the repair information to memory chips to repair a memory chip, in a system including a plurality of memory chips, such as a multi-chip package.

In accordance with an embodiment of the present invention, a memory system includes one or more memory chips, and a repair information storage chip including a nonvolatile memory configured to store repair information of the one or more memory chips, wherein during an initial operation of the memory system, the repair information stored in the repair information storage chip is transmitted to the one or more memory chips.

In accordance with another embodiment of the present invention, there is provided an operating method of a memory system which includes one or more memory chips and a repair information storage chip. The operation method includes powering up the memory system, transmitting, by the repair information storage chip, a repair information to the one or more memory chips, and replacing failed cells in the one or more memory chips with redundant cells using the repair information, during read and write operations of the one or more memory chips.

DETAILED DESCRIPTION

FIG. 3is a diagram illustrating a memory system in accordance with an embodiment of the present invention.

The memory system in accordance with the embodiment of the present invention may refer to a system including a plurality of memory chips and a repair information storage chip, which are stacked in one semiconductor package. Furthermore, the memory system in accordance with the embodiment of the present invention may refer to a system including a plurality of memory chips and a repair information storage chip, which exist over the same substrate or module.FIG. 3illustrates a memory system in which memory chips320and330and a repair information storage chip310are stacked.

Referring toFIG. 3, the memory system includes a repair information storage chip310and one or more memory chips320and330.

The repair information storage chip310is configured to store repair information. In the conventional memory device ofFIG. 1, the repair information is stored in the fuse circuits140and160. The repair information storage chip310may store the repair information of all memory chips320and330within the memory system. The repair information storage chip310may include various nonvolatile memories such as an E-fuse array, a flash memory array, and Electrically Erasable Programmable Read-Only Memory (EEPROM). The repair information of the memory chips320and330in the memory system is stored in the repair information storage chip310. Therefore, unlike the conventional memory device requiring an operation of programming fuse circuits in memory chips to store repair information, the memory system does not require the programming operation. That is, the memory system in accordance with the embodiment of the present invention simply programs only the repair information storage chip310after conducting defect analysis on the memory chips320and330. The memory system includes a plurality of data transmission channels301to transmit the repair information between the repair information storage chip and the respective memory chips. In this embodiment of the present invention, the memory system includes eight data transmission channels301. Furthermore, the memory system includes a first clock channel302formed between the repair information storage chip310and the memory chip320. In addition, the memory system includes a second clock channel303formed between the memory chip320and the memory chip330. During an initial operation period of the memory system, that is, before a normal operation, such as a read or write operation, is performed and after a power-up of the memory system, the repair information storage chip310outputs repair information to the data transmission channel301. Furthermore, the repair information storage chip310outputs a clock signal synchronized with the repair information to the first clock channel302.

The memory chips320and330receive the repair information from the repair information storage chip310during the initial operation period of the memory system, and repair their failed memory cells with redundant memory cells. Here, repairing is to access a redundant memory cell to instead of a failed memory cell, when the failed memory cell is selected by an address during a read or write operation. The memory chips320and330include a plurality of latch sets. The memory chips320and330store the repair information received from the repair information storage chip310in the latch sets, and repair their failed memory cells by using the repair information stored in the latch sets. The process in which the memory chips320and330store the repair information, which is transmitted to the data transmission channel301in the internal latch sets, using clock signals transmitted through the clock channels302and303, will be described in detail with reference to the accompanying drawings.

For reference, when the chips310to330are stacked as illustrated inFIG. 3, the channels301to303may be formed as through-silicon vias (TSVs). When the chips310to330exist over a module or substrate (for example, a PCB substrate), the channels may be formed as interconnections over the substrate or module.

FIG. 4is a configuration diagram of the memory chip320ofFIG. 3.

FIG. 4illustrates the process in which the memory chip320stores repair information D<0:7>, which is transmitted to the data transmission channel301, using first clock signals CLK1—0 to CLK1—3 transmitted to the first clock channel302.

Referring toFIG. 4, the memory chip320includes a plurality of memory banks BK0 to BK7, a select signal generation circuit including a plurality of select signal generation units420_01,420_23,420_45, and420_67each provided for every two banks, a plurality of latch sets430_0to430_7provided for the banks BK0 to BK7, respectively, and a clock transmission circuit including a plurality of clock transmission units450_0to450_3.

The select signal generation unit420_01is configured to generate select signals SEL0<0:255> by using the inputted first clock signal CLK1—0. Specifically, the select signal generation unit420_01sequentially activates each of the select signals SEL0<0:255> whenever the first clock signal CLK1—0 toggles. For example, when the first clock signal CLK1—0 toggles for the first time, the select signal SEL0<0> is activated, and when the first clock signal CLK1—0 toggles for the second time, the select signal SEL0<1> is activated. After the last select signal SEL0<255> is activated, the select signal generation unit420_01is disabled. The other select signal generation units420_23,420_45, and420_67also sequentially activate each of select signals SEL1<0:255>, SEL2<0:255>, and SEL3<0:255>, respectively, whenever the first clock signals CLK1—1 to CLK1—3 received by the respective select signal generation units420_23,420_45, and420_67toggle.

The latch sets430_0to430_7are enabled by the corresponding select signals SEL0<0:255>, SEL1<0:255>, SEL2<0:255>, and SEL3<0:255>. The enabled latch set receives and stores the repair information D<0:7> transmitted through the data transmission channel301. For example, when the select signal SEL1<0> is activated, a first latch set among the latch sets430_0corresponding to the bank BK0 receives and stores the repair information D<0:7> transmitted through the data transmission channel301. Similarly, when the select signal SEL1<1> is activated, a second latch set among the latch sets430_0receives and stores the repair information D<0:7> transmitted through the data transmission channel301.

The clock transmission units450_0to450_3are configured to transmit input clock signals as output clock signals, after all of the select signals SEL0<0:255>, SEL1<0:255>, SEL2<0:255>, and SEL3<0:255> generated by the select signal generation units420_01,420_23,420_45, and420_67corresponding to the respective clock transmission units among the clock transmission units450_0to450_3are activated. For example, when the first clock signal CLK1—1 is activated for 256 times, the select signal generation unit420_23activates all of the select signals SEL1<0:255>, and the clock transmission unit450_1transmits the first clock signal CLK1—1 as the first clock signal CLK1—2. In particular, the last clock transmission unit450_3transmits the first clock signal CLK1—3 as a second clock signal CLK2—0 to the second clock channel303after the first clock signal CLK1—3 is activated for 256 times. The second clock signal CLK2—0 transmitted to the second clock channel303is transmitted to the memory chip330.

The memory banks BK0 to BK7 perform their repair operations by using the repair data stored in the corresponding latch sets430_0to430_7. Here, repairing is to access a redundant memory cell instead of a failed memory cell, when the failed memory cell is selected by an address during a read or write operation.

In the memory chip320, while the first clock signal CLK1—0 inputted through the first clock channel302toggles 1,024 times, the repair information inputted through the data transmission channel301is sequentially stored in the latch sets430_0to430_7. After the repair information is stored in latch sets430_0to430_7, the first clock signal CLK1—0 is transmitted as the second clock signal CLK2—0 to the memory chip330through the second clock channel303. Here, since the memory chip320includes the latch sets430_0to430_7, which collectively include 1,024 latch sets, 1,024 clock cycles are used to store the repair information in all of the latch sets430_0to430_7. However, the time required for storing the repair information in all latch sets may be changed depending on the number of latch sets.

FIG. 4illustrates the select signal generation circuit is divided into the plurality of select signal generation units420_01,420_23,420_45, and420_67to generate the select signals SEL0<0:255>, SEL1<0:255>, SEL2<0:255>, and SEL3<0:255> used in the memory chip. In another exemplary embodiment, the select signal generation circuit may include one select signal generation unit to generate the select signals SEL0<0:255>, SEL1<0:255>, SEL2<0:255>, and SEL3<0:255> corresponding to the latch sets430_0to430_7in the memory chip320.

FIG. 5is a configuration diagram of the memory chip330ofFIG. 3.

Referring toFIG. 5, the memory chip330includes a plurality of memory banks BK0 to BK7, a select signal generation circuit including a plurality of select signal generation units520_01,520_23,520_45, and520_67each provided for every two banks, a plurality of latch sets530_0to530_7provided for the banks BK0 to BK7, respectively, and a clock transmission circuit including a plurality of clock transmission units550_0to550_3.

As illustrated inFIG. 5, the memory chip330may be configured in the same manner as the memory chip320. However, the memory chip330is different from the memory chip320in that the memory chip330uses second clock signals CLK2—0 to CLK2—3 inputted through the second clock channel303. Furthermore, since another memory chip does not exist at the rear stage of the memory chip330, the last clock transmission unit550_3of the memory chip330may be omitted or disabled. However, when another memory chip (for example, memory chip340) exists, the last clock transmission unit550_3may be enabled.

In the memory chip330, while the second clock signal CLK2—0 inputted through the second clock channel303is togged for 1,024 times, the repair information inputted through the data transmission channel301is sequentially stored in the latch sets530_0to530_7, which collectively include 1,024 latch sets.

FIG. 6is a detailed diagram of the latch sets430_0and430_1, the select signal generation unit420_01, and the clock transmission unit450_0ofFIG. 4.

Referring toFIG. 6, each of the latch sets430_0_0to430_0_127and430_1_128to430_1_255includes the same number of latches as a bit number of the data channel301. For example, the exemplary embodiment shown inFIG. 6includes eight latches and the data channel301has eight bits. The respective latch sets are enabled by the corresponding select signals SEL0<0:255>, and the enabled latch sets receive and store the repair information D<0:7> transmitted to the data channel301. For example, when the select signal SEL0<2> is activated, eight latches forming the latch set430_0_2receive and store the repair information D<0:7>, and when the select signal SEL0<255> is activated, eight latches forming the latch set430_1_255receive and store the repair information.

The clock transmission unit450_0is configured to transmit the first clock signal CLK1—0 as the first clock signal CLK1—1, after all of the select signals 0<0:255> are activated, that is, after the repair information D<0:7> is stored in all latch sets. The clock transmission unit450_0receives the select signal SEL0<255>, which is activated lastly among the select signals SEL0<0:255>, and the select signal SEL0<255> informs the clock transmission unit450_0that all of the select signals SEL0<0:255> were activated. Until the last select signal SEL0<255> is activated, the clock transmission unit450_0fixes the level of the first clock signal CLK1—1 to a low level.

FIG. 7is a configuration diagram of the select signal generation unit420_01ofFIG. 6.

Referring toFIG. 7, the select signal generation unit420_01includes an address generation section710and a decoding section720.

The address generation section710is configured to count the inputted first clock signal CLK1—0 and generate an address ADD<0:7>.FIG. 6illustrates a case in which the number of select signals SEL0<0:255> is set to 256. Therefore, the address ADD<0:7> is configured as an eight-bit binary code. The address generation section710may be designed by using a counter.

The decoding section720is configured to decode the address ADD<0:7> and generate the select signals SEL0<0:255>. As described above, the address ADD<0:7> includes an eight-bit binary code. Therefore, the address ADD<0:7> may be decoded to activate one of the select signals SEL0<0:255>.

When the last select signal SEL0<255> is activated, data are stored in all of the latch sets430_0_0to430_0_127and430_1_128to430_1_255corresponding to the select signal generation unit420_01. Therefore, the select signal no longer needs to be activated. Accordingly, when the last select signal SEL0<255> is activated, the address generation section710and the decoding section720are deactivated. As a result, all of the select signals SEL0<0:255> continuously maintain a deactivated state.

FIG. 8is a diagram illustrating the first clock signals CLK1—0 to CLK1—3 used in the memory chip320ofFIG. 4and the second dock signals CLK2—0 to CLK2—3 used in the memory chip330ofFIG. 5.

Referring toFIG. 8, the first clock signal CLK1—0 starts to toggle at the same time when the repair information is outputted from the repair information storage chip310. After the first clock CLK1—0 toggles, the repair information is stored in the latch sets430_0and430_1in the memory chip320during a first 256-clock cycle period801.

After the period801, clock transmission of the clock transmission unit450_0is started, and the first clock signal CLK1—1 starts to toggle. After the first clock CLK1—1 toggles, the repair information is stored in the latch sets430_2and430_3in the memory chip320during a second 256-clock cycle period802.

After the period802, clock transmission of the clock transmission unit450_1is started, and the first clock signal CLK1—2 starts to toggle. After the first clock CLK1—2 toggles, the repair information is stored in the latch sets430_4and430_5in the memory chip320during a third 256-clock cycle period803.

After the period803, clock transmission of the clock transmission unit450_2is started, and the first clock signal CLK1—3 starts to toggles. After the first clock CLK1—3 toggles, the repair information is stored in the latch sets430_6and430_7in the memory chip320during a fourth256clock-cycle period804.

After the period804, the clock transmission unit450_3starts to transmit the first clock signal CLK1—3 as the second clock signal CLK2—0 to the memory chip330through the second clock signal303. After the second clock signal CLK2—0 starts to toggle, the repair information is stored in the latch sets530_0and530_1in the memory chip330during a fifth 256-clock cycle period805.

After the period805, clock transmission of the clock transmission unit550_0is started, and the second clock signal CLK2_1starts to toggle. After the second clock signal CLK2—1 toggles, the repair information is stored in the latch sets530_2and530_3in the memory chip330during a sixth 256-clock cycle period806.

After the period806, clock transmission of the clock transmission unit550_1is started, and the second clock signal CLK2—2 starts to toggles. After the second clock signal CLK2—2 toggles, the repair information is stored in the latch sets530_4and530_5in the memory chip330during a seventh 256-clock cycle period807.

After the period807, clock transmission of the clock transmission unit550_2is started, and the second clock signal CLK2—3 starts to toggles. After the second clock signal CLK2—3 toggles, the repair information is stored in the latch sets530_6and530_7in the memory chip330during an eighth 256-clock cycle period808.

In this way, the operation of transmitting the repair information from the repair information storage chip310to the memory chip320and the memory chip330is competed.

In accordance with the embodiments of the present invention, the repair information of the memory chips is stored in the repair information storage chip, which is separate from the memory chips, in the memory system. As a result, the memory chips may be repaired by using the repair information stored in the repair information storage chip.

Therefore, the repair information may be collectively stored in the repair information storage chip without recording the repair information in the respective memory chips after defect analysis, and new repair information may be added at any time.

In this embodiment of the present invention, it has been described that the memory system includes two memory chips. However, the memory system may include a greater or smaller number of memory chips, and the repair information storage chip may store repair information of the memory chips.