Liquid crystal display panel and method for testing the same

The present invention relates to a liquid crystal display panel and a method for testing the same. The liquid crystal display panel includes at least one testing signal supply line having first and second horizontal portions spaced from each other for applying a testing signal to the liquid crystal display panel, first and second electrolytic corrosion blocking patterns connected to ends of the first and second horizontal lines respectively on a substrate and isolated from each other for prevention of transmission of the electrolytic corrosion from the first horizontal portion to the second horizontal portion, and a connection pattern formed of a material resistant to the electrolytic corrosion for connecting the first horizontal portion to the second horizontal portion, electrically.

CROSS REFERENCE TO RELATED APPLICATION

This application claims the benefit of the Korean Patent Application No. 10-2008-0091748, filed on Sep. 18, 2008, which is hereby incorporated by reference as if fully set forth herein.

BACKGROUND OF THE DISCLOSURE

1. Field of the Disclosure

The present invention relates to a liquid crystal display panel, and, more particularly, to a liquid crystal display panel which can prevent electrolytic corrosion from transmitting to the liquid crystal display panel from an outer portion of the panel which is a testing line, and a method for testing the same.

2. Discussion of the Related Art

In general, a liquid crystal display device is provided with the liquid crystal display panel for displaying a picture by utilizing electric and optical properties of liquid crystals, and a driver for applying a driving signal to the liquid crystal display panel.

The liquid crystal display panel has first and second substrates bonded with a gap therebetween, and a liquid crystal layer formed between the first and second substrates. The liquid crystal display panel is fabricated by a process having a thin film transistor array step for forming thin film transistors on the first substrate, and a color filter array step for forming a color filter on the second substrate. Fabrication of the liquid crystal display panel is finished by bonding the first substrate having the thin film transistor array formed thereon and the second substrate having the color filter array formed thereon together through a cell step, with the liquid crystal layer disposed therebetween.

The liquid crystal display panel finished thus is tested to determine if the liquid crystal display panel has defects or not, and the liquid crystal display panel which is determined to have no defects has a polarization plate attached to an outer side of the liquid crystal display panel, and a driving circuit connected thereto, thereby finishing fabrication of the liquid crystal display device.

Referring toFIG. 1A, in the testing process, after determining existence of defects by using testing signal supply lines12and14which apply signals to the liquid crystal display panel10, a portion having the testing signal supply lines12and14formed thereon is scribed SCR, to cut off the portion. However, if electrolytic corrosion takes place at a cut surface due to chemical or substrate contamination, the electrolytic corrosion transmits to an inside of the liquid crystal display panel10in a direction of the arrows through the testing signal supply lines12and14like the electrolytic corrosion portions shown inFIG. 1B, to cause a crack which leads to a defect of seal breakage.

SUMMARY OF THE DISCLOSURE

Accordingly, the present invention is directed to a liquid crystal display panel and a method for testing the same.

An object of the present invention is to provide a liquid crystal display panel which can prevent electrolytic corrosion from transmitting to the liquid crystal display panel from an outer portion of the panel which is a testing line, and a method for testing the same.

To achieve these objects and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, a liquid crystal display panel includes at least one testing signal supply line having first and second horizontal portions spaced from each other for applying a testing signal to the liquid crystal display panel, first and second electrolytic corrosion blocking patterns connected to ends of the first and second horizontal lines respectively on a substrate and isolated from each other for prevention of transmission of the electrolytic corrosion from the first horizontal portion to the second horizontal portion, and a connection pattern formed of a material resistant to the electrolytic corrosion for connecting the first horizontal portion to the second horizontal portion, electrically.

In another aspect of the present invention, a method for testing a liquid crystal display panel includes the steps of forming gate lines and at least one testing signal supply line having first and second horizontal portions spaced from each other for applying a testing signal to the liquid crystal display panel, and first and second electrolytic corrosion blocking patterns connected to ends of the first and second horizontal lines respectively on a substrate, testing shorts of the gate lines, forming a gate insulating film on the testing line and the first and second electrolytic corrosion blocking patterns, forming first and second contact holes which expose the first and second horizontal portions and a third contact hole which exposes the electrolytic corrosion blocking pattern, dividing a connection pattern formed of a material resistant to the electrolytic corrosion for connecting the first horizontal portion to the second horizontal portion through the first and second contact holes, and the first and second electrolytic corrosion blocking patterns by the third contact hole, inspecting defects in an array by applying a test signal to the at least one testing line, and removing the at least one testing line by scribing.

DESCRIPTION OF SPECIFIC EMBODIMENTS

FIG. 2illustrates a plan view of a testing portion for a liquid crystal display panel in accordance with a preferred embodiment of the present invention, andFIG. 3illustrates sections across lines I-I′ to III-III′ inFIG. 2, respectively.

Referring toFIGS. 2 and 3, the testing portion for a liquid crystal display panel includes a testing signal supply line at a periphery of a substrate for testing existence of defects at the liquid crystal display panel, a testing line140connected to the testing signal supply line for applying a signal to the liquid crystal display panel, and an electrolytic corrosion blocking pattern180for preventing the electrolytic corrosion from transmitting from the testing signal supply line.

As a testing method for detecting an electric characteristic defects at a thin film transistor liquid crystal display panel, in general, there are an array test and a GGS (Gate Gate Short) test. The array test is a final test after finishing fabrication of the thin film transistor substrate, wherein a testing instrument having a liquid crystal layer, i.e., a modulator, is placed on the thin film transistor substrate, and a test signal is supplied to the thin film transistor substrate to display a test picture for inspecting existence of defective pixels and defective lines. If the liquid crystal display panel has defects, an electric field is changed by a voltage applied to the liquid crystal display panel and the modulator to change a light quantity transmitting through the modulator, thereby notice the defects by a difference of voltages at a portion having a difference of pixels, to detect the defects of the liquid crystal display panel.

The GGS test is a test of shorts, caused by foreign matters during deposition of gate metal layers or a photo process, of all connection portions of gate patterns after finishing formation of gate patterns of the gate metal layers.

After finishing the testing, the testing signal lines are cut off by scribing SCR. In this instance, if the electrolytic corrosion takes place at the cut surface due to chemical or substrate contamination, the electrolytic corrosion transmits to an inside of the liquid crystal display panel through the testing signal supply line. In other words, currently, at the time of a 0° C. low temperature driving assessment after −10° C. low temperature conservation, a minute electrolytic corrosion defect transmission to the inside of the liquid crystal display panel caused by the substrate contamination and infiltration of external contamination causes a panel crack, resulting in a seal breakage defect as shown inFIG. 4.

The testing signal supply line includes a first testing signal line150grounded to the inside of the liquid crystal display panel for applying a ground voltage, and a second testing signal line162for applying the common voltage Vcom to the common electrode (not shown). The second signal supply line162includes a vertical portion158formed in parallel to the first testing signal supply line150, and a horizontal portion160a,160bbranched from the vertical portion158for applying the signal to the liquid crystal display panel.

The horizontal portion includes a first horizontal portion160abranched from the vertical portion158, and a second horizontal portion160bspaced from the first horizontal portion160aand connected to the testing line140for applying the signal to the liquid crystal display panel. The first and second horizontal portions160aand160bare connected to a connection pattern125through at least one first and second contact holes120and122which are passed through the a gate insulating film104and a protective film130, electrically. Since the electrolytic corrosion transmits following the gate metal layer, in order to prevent the electrolytic corrosion from transmitting, the first and second horizontal portions160aand160bare formed to be spaced apart from each other, and the first and second horizontal portions160aand160bspaced apart from each other thus are electrically connected by jumping with the connection pattern125of a transparent conductive layer which is resistant to the electrolytic corrosion and corrosion. The spaced distance between the first and second horizontal portions160aand160bare 20 μm˜50 μm.

In this instance, though a plurality of the first and second contact holes120and122respectively in the first and second horizontal portions160aand160bmay be formed singular, it is preferable that the plurality of contact holes are formed for preventing defective contact and enlarging a contact area.

The electrolytic corrosion blocking pattern180is connected to ends of the first and second horizontal portions160aand160brespectively, and formed of the gate metal layer (not shown) identical to the first and second horizontal portions160aand160b. After formation of the gate pattern of the gate metal layer (not shown), the GGS (Gate Gate Short) test is performed for testing whether shorts are taken place at the gate lines (not shown) or not. In this instance, the signal is applied to the liquid crystal display panel through a signal path of the vertical portion158of the second testing signal supply line162for applying the common voltage, the first horizontal portion160a, the electrolytic corrosion blocking pattern180, and the second horizontal portion160b.

After the GGS test, the electrolytic corrosion blocking pattern180is disconnected by a third contact hole111which penetrates through the protective film130, the gate insulating film104, and the electrolytic corrosion blocking pattern180, dividing the electrolytic corrosion blocking pattern180into a first electrolytic corrosion blocking pattern180aconnected to the first horizontal portion160aand a second electrolytic corrosion blocking pattern180bconnected to the second horizontal portion160b. Since the electrolytic corrosion blocking pattern180is divided into the first electrolytic corrosion blocking pattern180aand the second electrolytic corrosion blocking pattern180bthus, a signal and electrolytic corrosion transmission path from the first horizontal portion160ato the second horizontal portion160bis blocked. In this instance, the signal is applied to the inside of the liquid crystal display panel through a signal path of the vertical portion158of the second testing signal supply line162, the first horizontal portion160a, the connection pattern125, and the second horizontal portion160b.

Referring toFIG. 5, the electrolytic corrosion blocking pattern180may be formed to be circular, elliptical, polygonal, or zigzag for making the electrolytic corrosion transmission path longer.

At the time of the array test, the signal is applied to the liquid crystal display panel through the testing line140until the region of the testing signal line is cut off, and the testing line140is floated on an underside of a seal pattern after the region is cut off. Formed on the testing line140, there is a testing pattern142having the gate insulating film104, the protective film130, and the transparent conductive line. The testing pattern142is in contact with the testing line140so as to be connected electrically thereto for applying the common voltage applied to the testing line140to a common electrode (not shown) on the color filter substrate (not shown) through a conductive ball at the seal pattern.

FIG. 6illustrates sections across lines I-I′ to II-II′ inFIG. 2respectively and a thin film transistor.

Referring toFIG. 6, the testing signal supply line, the thin film transistor TFT and the electrolytic corrosion blocking pattern180are formed on the substrate100.

The thin film transistor TFT includes a gate electrode102branched from the gate line (not shown), a gate insulating film104formed on an entire surface of the substrate100having the gate electrode formed thereon, a semiconductor layer formed on the gate insulating film104overlapped with the gate electrode102, a source electrode110aformed on the semiconductor layer108branched from the data line (not shown), and a drain electrode110bformed on the semiconductor layer108opposite to the source electrode110a.

The semiconductor layer108includes an active layer108band an ohmic contact layer108aformed by patterning an amorphous silicon a-Si layer and an impurity n+doped amorphous silicon layer.

The thin film transistor TFT has the protective film130formed thereon having a pixel contact hole112which exposes the drain electrode110bformed therein, and is connected to the pixel electrode115and the drain electrode110bthrough the pixel contact hole112, electrically.

The first and second testing signal supply lines150and162are formed of a gate metal layer at the same layer with the gate electrode102of the thin film transistor TFT, the gate insulating film104and the protective film130are formed in succession on the first and second horizontal portions160aand160bof the second testing signal supply line162shown inFIG. 6, the first and second horizontal portions160aand160bare exposed by the first and second contact holes120and122respectively which passes through the gate insulating film104and the protective film130, and the connection pattern125connects the first and second horizontal portions160aand160bto each other through the first and second contact holes120and122, respectively.

The gate metal layer includes single layer or plural layers of a metal selected from molybdenum Mo, aluminum Al, aluminum-neodymium Al—Nd, copper Cu, chromium Cr, and titanium Ti or an alloy thereof.

The connection pattern125is formed of a transparent conductive material resistant to the electrolytic corrosion and corrosion identical to the pixel electrode115at the same layer with the pixel electrode115. The transparent conductive material may be one selected from indium tin oxide ITO, tin oxide TO, indium zinc oxide IZO, and indium tin zinc oxide ITZO.

The electrolytic corrosion blocking pattern180is connected to the first and second horizontal portions160aand160b, and has the gate insulating film104and the protective film130formed thereon in succession, is divided into the first electrolytic corrosion blocking pattern180aconnected to the first horizontal portion160aand the second electrolytic corrosion blocking pattern180bconnected to the second horizontal portion160bby a third contact hole111which passes through the protective film130, the gate insulating film104, and the electrolytic corrosion blocking pattern180.

FIGS. 7A to 7Dillustrate sections showing the steps of a method for fabricating the thin film transistor substrate inFIG. 6.

Referring toFIG. 7A, a gate pattern is formed on a substrate100, having a gate line (not shown), a gate electrode102, testing signal supply lines150and162, and an electrolytic corrosion blocking pattern180.

In detail, a gate metal layer is formed on the substrate100by deposition such as sputtering, and subjected to patterning with a mask by photolithography and etching, to form first and second horizontal portions160aand160bof a second testing signal supply line162spaced from each other for applying a common voltage, an electrolytic corrosion blocking pattern180connected to an end of each of the first and second horizontal portions160aand160b, and a gate electrode102. The first and second horizontal portions160aand160bare 20 μm˜50 μm spaced from each other.

The gate metal layer includes single layer or plural layers of a metal selected from molybdenum Mo, aluminum Al, aluminum-neodymium Al—Nd, copper Cu, chromium Cr, and titanium Ti or an alloy thereof.

After formation of the gate pattern of the gate metal layer, GGS test is performed for inspection of shorts between the gate patterns. In this instance, the signal is applied to an inside of the liquid crystal display panel through a signal path of the vertical portion158of the second testing signal supply line162for applying the common voltage to the liquid crystal display panel, the first horizontal portion160a, the electrolytic corrosion blocking pattern180, and the second horizontal portion160b.

Then, referring toFIG. 7B, a gate insulating film104, an amorphous silicon a-Si layer, and an impurity n+doped amorphous silicon layer are formed on an entire surface of the thin film transistor substrate100including the gate pattern by deposition, such as PECVD (Plasma Enhanced Chemical Deposition), or the like. Then, a source/drain metal layer is formed by deposition, such as sputtering, and subjected to patterning with a mask by photolithography and etching to overlap with the gate electrode102, to form a semiconductor layer108having an active layer108band an ohmic contact layer108a, and a thin film transistor having source and drain electrodes110aand110b. In this instance, for electrical isolation of the source electrode110aand the drain electrode110band the ohmic contact layer108a, diffractive exposure or a half-tone mask is used.

The gate insulating film104is formed of an inorganic insulating material, such as silicon oxide SiOx and silicon nitride. The source and drain metal layers are single layer or plural layers of a metal selected from molybdenum Mo, aluminum Al, aluminum-neodymium Al—Nd, copper Cu, chromium Cr, titanium Ti, an alloy of molybdenum Mo and titanium Ti MoTi, an alloy of titanium and neodymium TiNb or an alloy thereof.

Referring toFIG. 7C, a protective film130having first to third contact holes120,122, and111, and a pixel contact hole112is formed on an entire surface of the substrate including the thin film transistor TFT, and subjected to patterning with a mask by photolithography, and etching, to form first and second contact holes120and122which expose the first and second horizontal portions160aand160brespectively, a third contact hole111which exposes the electrolytic corrosion blocking pattern180, and a pixel contact hole112which exposes the drain electrode110bof the thin film transistor TFT.

The protective film130is formed of an inorganic insulating material, such as the gate insulating film104, by deposition, such as PECVD, or of an acryl group organic compound, or of organic insulating material, such as BCB (Benzocyclobuten), PFCB (Perfluorocyclobutane), Teflon, Cytop, and so on, by spin or spinless coating.

Referring toFIG. 7D, the connection pattern125and the pixel electrode115are formed on the protective film130, and the electrolytic corrosion blocking pattern180is divided into the first and second electrolytic corrosion blocking patterns180aand180b.

In detail, a transparent conductive material is deposited on the protective film130, and subjected to patterning with a mask by photolithography and etching to form the connection pattern connecting the first and second horizontal portions160aand160belectrically through the first and second contact holes120and122, and the pixel electrode115electrically connected to the drain electrode110bthrough the pixel contact hole112.

In this instance, since the third contact hole111exposes the electrolytic corrosion blocking pattern180, the electrolytic corrosion blocking pattern180exposed thus at the same time with patterning of the connection pattern125and the pixel electrode115is removed by the etching, to divide the electrolytic corrosion blocking pattern180into the first and second electrolytic corrosion blocking patterns180aand180b.

The transparent conductive material may be one selected from indium tin oxide ITO, tin oxide TO, indium zinc oxide IZO, and indium tin zinc oxide ITZO.

After finishing formation of the thin film transistor substrate thus, the array test is performed. That is, the testing instrument having a liquid crystal layer, i.e., a modulator, is placed on the thin film transistor substrate, and a test signal is supplied to the thin film transistor substrate to display a test picture for inspecting existence of defective pixels and defective lines. If the liquid crystal display panel has defects, an electric field is changed by a voltage applied to the liquid crystal display panel and the modulator to change a light quantity transmitting through the modulator, thereby notice the defects by a difference of voltages at a portion having a difference of pixels, to detect the defects at the liquid crystal display panel.

After finishing the test, edge regions of the substrate is scribed, to cut of the testing signal supply lines150and162.

In this instance, if electrolytic corrosion takes place at a cut surface due to chemical or substrate contamination, since the electrolytic corrosion transmits to an inside of the liquid crystal display panel through the testing signal supply lines, to cause a crack which leads to a defect of seal breakage, the electrolytic corrosion blocking pattern180is divided to block the signal and electrolytic corrosion transmission path. In this instance, the signal is applied to the inside of the liquid crystal display panel through a signal path of the vertical portion158, the first horizontal portion160a, the connection pattern125, and the second horizontal portion160b. This permits immediate application of the present invention to mass production without occupying large space.

As has been described, the liquid crystal display panel and the method for testing the same of the present invention have the following advantages.

The connection of the first and second horizontal portions of the testing signal supply line spaced from each other with the connection pattern of an electrolytic corrosion resistant material permits to block transmission of the electrolytic corrosion to the liquid crystal display panel when the testing signal supply line is cut off.

By forming the electrolytic corrosion blocking pattern connected to the first and second horizontal portions of the testing signal supply line to be isolated, a transmission pattern of the electrolytic corrosion can be blocked, and the seal breakage defect caused by panel crack coming from the electrolytic corrosion can be prevented.