Discontinuous patterned bonds for semiconductor devices and associated systems and methods

Discontinuous bonds for semiconductor devices are disclosed herein. A device in accordance with a particular embodiment includes a first substrate and a second substrate, with at least one of the first substrate and the second substrate having a plurality of solid-state transducers. The second substrate can include a plurality of projections and a plurality of intermediate regions and can be bonded to the first substrate with a discontinuous bond. Individual solid-state transducers can be disposed at least partially within corresponding intermediate regions and the discontinuous bond can include bonding material bonding the individual solid-state transducers to blind ends of corresponding intermediate regions. Associated methods and systems of discontinuous bonds for semiconductor devices are disclosed herein.

TECHNICAL FIELD

The present technology is directed generally to discontinuous bonds for semiconductor devices, and associated systems and methods. Discontinuous bonds in accordance with the present technology are suitable for solid-state transducers, including light-emitting diodes.

BACKGROUND

Solid state transducer devices include light-emitting diodes (“LEDs”), organic light emitting diodes (“OLEDs”), and polymer light-emitting diodes (“PLEDS”). The energy efficiency and small size of solid state transducer devices has led to the proliferation of these devices in a multitude of products. Televisions, computer monitors, mobile phones, digital cameras, and other electronic devices utilize LEDs for image generation, object illumination (e.g., camera flashes) and/or backlighting. LEDs are also used for signage, indoor and outdoor lighting, traffic lights, and other types of illumination. Improved fabrication techniques for these semiconductor devices have both lowered device cost and increased device efficiency.

Manufacturing processes for solid-state transducer devices and other semiconductor devices often include the use of multiple substrates. In one conventional method, semiconductor fabrication techniques are used to construct LEDs on a device substrate. A bonding material is then used to bond the device substrate to a carrier substrate, with the LEDs sandwiched therebetween. The device substrate can then be removed and the carrier substrate with the attached LEDs can be further processed to singulate individual LEDs.

Although this fabrication method can yield reasonable results, the bonding process can produce significant stresses on the substrates and the attached LEDs. These stresses can flex and bow the substrates causing, warping, delamination or other separations, and/or can lead to misalignments during the singulation process. Additionally, singulating the LEDs through both the bonding material and the substrate can create significant stresses and complicate the singulation process. Accordingly, there is a need for a solid-state transducer device and a method of fabrication that can avoid these limitations.

DETAILED DESCRIPTION

Specific details of several embodiments of wafer-level assemblies for semiconductor devices and associated systems and methods are described below. The embodiments below include solid-state transducers (“SSTs”). However, other embodiments of the presently disclosed technology may include other semiconductor devices, such as photocells, diodes, transistors, integrated circuits, etc. The term “SST” generally refers to solid-state devices that include a semiconductor material as the active medium to convert electrical energy into electromagnetic radiation in the visible, ultraviolet, infrared, and/or other spectra. For example, SST devices include solid-state light emitters (e.g., LEDs, laser diodes, etc.) and/or other sources of emission other than electrical filaments, plasmas, or gases. The term SST can also include solid-state devices that convert electromagnetic radiation into electricity. Additionally, depending upon the context in which it is used, the term “substrate” can refer to a wafer-level substrate or to a singulated device-level substrate. A person skilled in the relevant art will also understand that the technology may have additional embodiments, and that the technology may be practiced without several of the details of the embodiments described below with reference toFIGS. 1-13.

FIG. 1is a partially schematic, cross-sectional diagram of a portion of a wafer-level assembly, or device assembly100having a device substrate102, a transducer structure104and a first bond metal106in accordance with an embodiment of the present technology.FIG. 2is a partially schematic, cross-sectional diagram of a portion of a wafer-level assembly, or carrier assembly200, having a carrier substrate208and a second bond metal206in accordance with an embodiment of the present technology. The wafer-level assemblies ofFIGS. 1 and 2may be constructed using various semiconductor fabrication techniques. The device substrate102and the carrier substrate208, for example, can be made from silicon, polycrystalline aluminum nitride, sapphire, and/or other suitable materials including both metals and non-metals. Additionally, the device substrate102and/or the carrier substrate208may be a composite substrate or an engineered substrate. In such embodiments, the engineered substrate may include two or more materials bonded together, and/or materials chosen or engineered to improve fabrication or assembly of the device assembly100or carrier assembly200. The transducer structure104can be formed via a variety of processes, including metal organic chemical vapor deposition (“MOCVD”), molecular beam epitaxy (“MBE”), liquid phase epitaxy (“LPE”), and/or hydride vapor phase epitaxy (“HVPE”). In other embodiments, at least a portion of the transducer structure104may be formed using other suitable techniques, e.g., epitaxial growth techniques. The first bond metal106and the second bond metal206ofFIGS. 1 and 2may be composed of any of a variety of suitable metals including copper, aluminum, gold, tin, nickel, palladium, indium, and/or various alloys including combinations of these and/or other metals. In some embodiments, the first bond metal106and the second bond metal206may be composed of the same metal or alloy. In other embodiments, the first bond metal106and the second bond metal206may be composed of different metals or alloys. Furthermore, in yet other embodiments, a bonding material other than a metal may be used in place of the bond metals106and206. Various semiconductor adhesives, for example, may be used as a bonding material.

FIG. 3is a partially schematic, cross-sectional diagram of the device assembly100ofFIG. 1after having been patterned in accordance with an embodiment of the present technology. In the illustrated embodiment, the pattern formed in the device assembly100includes a plurality of trenches310formed by removing sections of the first bond metal106and the transducer structure104.FIG. 4is a partially schematic, top plan view of the device assembly100ofFIG. 3. Referring toFIGS. 3 and 4together, the trenches310can form a grid that separates the transducer structure104into a plurality of solid-state transducers (“SSTs”)312. The pattern of the trenches310and the SSTs312is shaped similarly to an inverted waffle shape, with sections or segments of the trenches310surrounding each of the SSTs312. The trenches310can be formed by positioning a mask (not shown) over the areas above the SSTs312and etching (e.g., wet etching, dry etching, etc.) the exposed sections of the first bond metal106and the transducer structure104. In other embodiments, the trenches310can be formed using other suitable semiconductor fabrication techniques.

FIG. 5is a partially schematic, cross-sectional diagram of a patterned carrier assembly500having a pattern in accordance with an embodiment of the present technology. In the illustrated embodiment, the pattern in the carrier assembly500includes a plurality of intermediate regions (e.g. recesses514) separated by raised portions or projections516.FIG. 6is a partially schematic, top plan view of the carrier assembly500ofFIG. 5. Referring toFIGS. 5 and 6together, the recesses514and the projections516form a waffle pattern with the projections516surrounding individual recesses514on all sides. As will be described in further detail below, the projections516can form dicing streets617that can be used to singulate the SSTs312. In some embodiments, the recesses514can be configured to have a depth of from about 5 to about 15 microns. In other embodiments, the depth of the recesses514may be smaller or larger than depths included in this range. The recesses514can be formed in a manner similar to that used to form the trenches310in the device assembly100. A mask (not shown), for example, can be used to cover the projections516of the carrier substrate208, and exposed sections of the carrier substrate208can be etched to form the recesses514. The recesses514can include blind ends515at least partially defined by the remaining carrier substrate208and/or the second bond metal206disposed in the recesses514to facilitate bonding with the device assembly100.

FIG. 7is a partially schematic, cross-sectional diagram of the device assembly100ofFIGS. 3 and 4and the carrier assembly500ofFIGS. 5 and 6in alignment prior to bonding. In the illustrated embodiment, the inverted waffle pattern of the device assembly100is aligned with the waffle pattern of the carrier assembly500, prior to bonding. In particular, the projections516of the carrier assembly500are aligned to be inserted into the trenches310, while the SSTs312with attached sections of the first bond metal106are aligned to be inserted into the recesses514. Optical alignment techniques and/or other semiconductor fabrication techniques can be used to align the device assembly100to the carrier assembly500in two orthogonal directions, and can be used to position the device assembly100and the carrier assembly500in parallel planes to facilitate consistent bonds between these assemblies. Additionally, the patterns of the assemblies described herein are created with suitable fabrication tolerances to allow for the assemblies to be mated. For example, the projections516may be slightly narrower than the trenches310to avoid an interference between these components.

FIG. 8is a partially schematic, cross-sectional diagram of a bonded assembly800, including the device assembly100and the carrier assembly500ofFIG. 7, configured in accordance with an embodiment of the present technology. Referring toFIGS. 7 and 8together, the bonded assembly800can be formed by bringing the device assembly100and the carrier assembly500together after alignment. When the device assembly100and the carrier assembly500are brought fully together to create the bonded assembly800, the individual SSTs312of the device assembly100are contained at least partially within the individual recesses514of the carrier assembly500. The first bond metal106of the device assembly100and the second bond metal206of the carrier assembly500combine to form a bond metal structure818, which bonds the SST's312to the recesses514. The bond metal structure818may be formed in a high temperature and pressure environment to facilitate bonding. The resulting bonded assembly800includes a discontinuous bond820composed of individual bond sections or segments821between the SSTs312and the bond metal structure818in the recesses514. In particular embodiments, the projections516of the carrier assembly500that separate the recesses514are not bonded to the device assembly100, and each individual projection516represents a discontinuity between the segments821of the discontinuous bond820.

FIG. 9is a partially schematic, cross-sectional diagram of the bonded assembly800shown inFIG. 8after the device substrate102(not shown inFIG. 9) has been removed in accordance with an embodiment of the present technology. The device substrate102may be removed by various semiconductor fabrication techniques including backgrinding, etching, chemical-mechanical planarization and/or other suitable removal methods. After the device substrate102has been removed, the bonded assembly800includes individual SSTs312separated by projections516. The projections516run across the bonded assembly800, as shown in the overhead view of the carrier assembly500inFIG. 6, to form the dicing streets617. A dicing saw or other singulation tool (not shown inFIG. 9) is then used to cut through the carrier substrate208along the dicing streets617to singulate the SSTs312. Dicing the bonded assembly along the streets617does not require the saw to singulate through more than one material, e.g., the saw need only cut through the carrier substrate208. Dicing through a single material can reduce the stresses on the bonded assembly800and can limit the potential for misalignments and defects caused by the singulation process. Additionally, the present technology further reduce stresses on the bonded assembly800by reducing or eliminating the need to singulate through a high stress bonding material.

FIG. 10is a partially schematic, cross-sectional diagram of the device assembly100ofFIG. 1and a carrier assembly1000in alignment prior to bonding in accordance with an embodiment of the present technology. Similar to the carrier assembly500ofFIGS. 5 and 6, the carrier assembly1000includes a plurality of recesses1014separated by streets or projections1016. The recesses1014and the projections1016form a waffle pattern with the projections1016surrounding individual recesses1014on all sides. In the illustrated embodiment, the recesses1014in the carrier assembly1000may be substantially filled with the second bond metal206to facilitate bonding with the device assembly100.

FIG. 11is a partially schematic, cross-sectional diagram of a bonded assembly1100including the device assembly100and the carrier assembly1000ofFIG. 10configured in accordance with an embodiment of the present technology. Referring toFIGS. 10 and 11together, after alignment, the device assembly100is brought together with and bonded to the carrier assembly1000. The resulting bonded assembly1100includes a bond metal structure1018that is formed from the first bond metal106of the device assembly100and the second bond metal206of the carrier assembly1000. The bond metal structure1018bonds the transducer structure104of the device assembly100to the carrier substrate208with a discontinuous bond1120. The discontinuous bond1120includes bond segments1121between the transducer structure104and the recesses1014. The projections1016of the carrier assembly1000are not bonded to the device assembly100. Accordingly, each individual projection1016represents a discontinuity between the bond segments1121of the discontinuous bond1120.

FIG. 12is a partially schematic, cross-sectional diagram of the device assembly100ofFIGS. 3 and 4and the carrier assembly200ofFIG. 2in alignment prior to bonding. As previously discussed, the trenches310, and the SSTs312define an inverted waffle shape, with sections of the trenches310surrounding each of the SSTs312.

FIG. 13is a partially schematic, cross-sectional diagram of a bonded assembly1300including the device assembly100and the carrier assembly200ofFIG. 12configured in accordance with an embodiment of the present technology. As shown inFIG. 13, the device assembly100and the carrier assembly200can be aligned and brought together to form the bonded assembly1300. Bonding the device assembly100with the carrier assembly200combines the first bond metal106with the second bond metal206to form a bond metal structure1318. Accordingly, the SSTs312of the device assembly100are bonded to the carrier assembly200with the bond metal structure1318. In the illustrated bonded assembly1300, the trenches310(or at least portions of the trenches310) remain open, forming a void or gap. The bonded assembly1300thereby includes a discontinuous bond1320composed of bond segments1321between the SSTs312and the carrier assembly200. The trenches310that separate the SSTs312represent a discontinuity between the bond segments1321of the discontinuous bond1320.

Conventional semiconductor fabrication techniques typically produce significant stresses across wafers that can cause the wafers to bow or warp. This in turn can cause the wafer components to separate and/or become misaligned, potentially creating immediate or delayed defects in the components. These negative effects can be especially pronounced in larger wafers in which stresses can build up over larger distances. In contrast to the foregoing conventional techniques, the discontinuous bonds of the present disclosure decrease the mechanical stress across the bonded assemblies. As discussed above, in the bonded assembly800, for example, the projections516of the carrier assembly500are not bonded to the device assembly100, and the projections516represent discontinuities in the discontinuous bond820. The discontinuities can decrease stress across the bonded assembly800and reduce or eliminate bowing and warping. The bonded assemblies1100and1300include similar stress reducing discontinuous bonds. Accordingly, the bonded assemblies of the present disclosure can be constructed on larger substrates because the lower stresses produce smaller amounts of bowing and warping for a given size substrate. In one embodiment, for example, the bonded assemblies can be constructed on eight inch diameter substrates. These larger wafers produce economies of scale not available with smaller wafers. Although the advantages of the systems and methods of the present technology may be more pronounced with larger diameter substrates, the advantages may also be present in smaller substrates. Accordingly, in other embodiments, the bonded assemblies may be constructed on smaller diameter substrates as well as larger diameter substrates.

A further advantage of embodiments of the present technology is that the second bond metal206can be contained during the fabrication process. The recesses514, for example, can contain the second bond metal206within the projections516. By containing the second bond metal206within the recesses514, the distribution of the second bond metal206can be limited to only areas where it is needed for bonding. Accordingly, the second bond metal206can be prevented from migrating to other areas of the carrier assembly500, and either interfering with other components (which can cause defects, such as short circuits), or creating waste by migrating to areas not used for bonding. By reducing defects and waste, systems and methods in accordance with embodiments of the present disclosure increase the efficiency and throughput with which SSTs and/or other semiconductor devices are manufactured.

From the foregoing it will be appreciated that specific embodiments of the disclosed technology have been described herein for purposes of illustration, but that various modifications may be made without deviating from the disclosure. For example, carrier assemblies, device assemblies and bonded assemblies disclosed herein can include trenches, patterned recesses, and/or projections with different sizes and/or shapes. Rectangular recesses and SSTs, for example, may be used in some embodiments. Additionally, different materials may be used in place of those described herein, or additional components may be added or removed. For example, a bonding material may be applied to only one of either the carrier assembly or the device assembly prior to bonding. In particular embodiments the trenches surround a single SST. In other embodiments, the smallest region enclosed by the trenches can include multiple SSTs. Such a technique can be used, for example, in instances for which grouping multiple SSTs together without a bond discontinuity does not create an unacceptable warping and/or other effects, and/or instances for which the SSTs remain together as a functional unit after dicing. Moreover, while various advantages and features associated with certain embodiments have been described above in the context of those embodiments, other embodiments may also exhibit such advantages and/or features, and not all embodiments need necessarily exhibit such advantages and/or features to fall within the scope of the technology. Accordingly, the disclosure and associated technology can encompass other embodiments not expressly shown or described herein.