Semiconductor device

According to one embodiment, a semiconductor device includes first and second electrodes, first, second, and third semiconductor regions, a gate electrode, first, and second conductive parts. The first semiconductor region includes a first region and a second region. The second semiconductor region is provided on the first region. The third semiconductor region is provided on the second semiconductor region. The second electrode is provided on the third semiconductor region. The gate electrode opposes the second semiconductor region in a second direction. The first conductive part is provided on the second region and is provided in a plurality in a third direction. The first conductive parts are arranged with the gate electrode in the second direction. The second conductive part is provided on the second region, and arranged with the gate electrode and the first conductive parts in the third direction.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is based upon and claims the benefit of priority from Japanese Patent Application No. 2018-024047, filed on Feb. 14, 2018; the entire contents of which are incorporated herein by reference.

FIELD

BACKGROUND

A semiconductor device such as MOSFET (Metal Oxide Semiconductor Field Effect Transistor) is used as a switching device. MOSFET includes a parasitic bipolar transistor. If this parasitic transistor operates, there is a possibility that the semiconductor device is destroyed. Therefore, it is desired that the parasitic transistor is difficult to operate.

DETAILED DESCRIPTION

According to one embodiment, a semiconductor device includes a first electrode, a first semiconductor region, a second semiconductor region, a third semiconductor region, a second electrode, a gate electrode, a first conductive part, and a second conductive part. The first semiconductor region is provided on the first electrode. The first semiconductor region includes a first region and a second region surrounding the first region. The first semiconductor region is of a first conductivity type. The second semiconductor region is provided on the first region. The second semiconductor region is of a second conductivity type. The third semiconductor region is provided on the second semiconductor region. The third semiconductor region is of the first conductivity type. The second electrode is provided on the third semiconductor region. The second electrode is electrically connected to the second semiconductor region and the third semiconductor region. The gate electrode opposes the second semiconductor region via a gate insulating part in a second direction perpendicular to a first direction from the first region toward the second semiconductor region. The first conductive part is provided on the second region via a first insulating part and electrically connected to the second electrode or the gate electrode. The first conductive part is provided in a plurality in a third direction perpendicular to the first direction and the second direction. The plurality of first conductive parts are separated one another. The first conductive parts are arranged with the gate electrode in the second direction. The second conductive part is electrically connected to the second electrode or the gate electrode. The second conductive part is provided on the second region via a second insulating part. The second conductive part is arranged with the gate electrode and the first conductive parts in the third direction.

The drawings are schematic or conceptual; and the relationships between the thicknesses and widths of portions, the proportions of sizes between portions, etc., are not necessarily the same as the actual values thereof. The dimensions and/or the proportions may be illustrated differently between the drawings, even in the case where the same portion is illustrated.

In the drawings and the specification of the application, components similar to those described thereinabove are marked with like reference numerals, and a detailed description is omitted as appropriate.

In the following descriptions and drawings, notations of n+, n, n−and p+, p, p−represent relative height of an impurity concentration in conductive types. That is, the notation with “+” shows a relatively higher impurity concentration than an impurity concentration for the notation without any of “+” and “−”. The notation with “−” shows a relatively lower impurity concentration than the impurity concentration for the notation without any of them.

The embodiments described below may be implemented by reversing the p-type and the n-type of the semiconductor regions.

First Embodiment

FIG. 1is a plan view showing a semiconductor device according to a first embodiment.

FIG. 1shows a cut plane at a position of a D-D′ line ofFIG. 2. The respective semiconductor regions are omitted inFIG. 1.

A semiconductor device100is, for example, MOSFET. As shown inFIG. 1toFIG. 3B, the semiconductor device100includes an n−-type (first conductivity type) semiconductor region1(first semiconductor region), a p-type (second conductivity type) base region2(second semiconductor region), an n−-type source region3(third semiconductor region), a p+-type contact region4(fourth semiconductor region), an n+-type drain region5(fifth semiconductor region), a field plate electrode (hereinafter, referred to as FP electrode)10a gate electrode14, a first conductive part21, a second conductive part22, a drain electrode41(first electrode), a source electrode42(second electrode), and a gate pad43(third electrode).

An XYZ orthogonal coordinate system is used in the description of the embodiment. A direction from a first region1aof the n−-type semiconductor region1toward the p-type base region2is taken as a Z-direction (first direction). Two directions perpendicular to the Z-direction and orthogonal each other are taken as an X-direction (second direction) and a Y-direction (third direction). For description, a direction from the first region1atoward the p-type base region2is referred to as “upward”, and the opposite direction is referred to as “downward”. These directions are based on a positional relationship between the first region1aand the p-type base region2, and are unrelated to a direction of gravity.

FIG. 1shows the source electrode42and the gate pad43by broken lines. As shown inFIG. 1, the source electrode42and the gate pad43are provided on an upper surface of the semiconductor device100, and separated each other. The FP electrode10, the gate electrode14, the first conductive part21, and the second conductive part22are provided under the source electrode42.

As shown inFIG. 2, the drain electrode41is provided on a lower surface of the semiconductor device100. The n+-type drain region5is provided on the drain electrode41and electrically connected to the drain electrode41. The n−-type semiconductor region1is provided on the n+-type drain region5. The n−-type semiconductor region1includes the first region1aand a second region1bsurrounding the first region1a. A direction from the first region1atoward the second region1bis perpendicular to the Z-direction. The p-type base region2is provided on the first region1a. The n−-type source region3and the p+-type contact region4are provided on the p-type base region2.

The FP electrode10is provided on the first region1avia an insulating part11. The gate electrode14is provided on the FP electrode10via an insulating part12. The gate electrode14opposes at least a portion of the n−-type semiconductor region1, the p-type base region2, or the n+-type source region3via a gate insulating part15in the X-direction. An insulating part35is provided on the gate electrode14. The gate electrode14is electrically connected to the gate pad43.

A portion of the source electrode42is provided in the insulating part35and is electrically connected to the n+-type source region3and the p+-type contact region4. In the example shown inFIG. 2, the p+-type contact region4is positioned below the n+-type source region3. The n+-type source region3is arranged with a portion of the source electrode42in the X-direction. A potential of the source electrode42is, for example, set to a ground. The gate electrode14and the source electrode42are electrically isolated by the insulating part35. The FP electrode10is electrically connected to the source electrode42or the gate electrode14(gate pad43).

Each of the p-type base region2, the n+-type source region3, the p+-type contact region4, the FP electrode10, and the gate electrode14is provided multiply in the X-direction on the first region1a, and extends in the Y-direction.

As shown inFIG. 1, the first conductive part21is provided multiply in the Y-direction. The multiple first conductive parts21are separated one another. The multiple first conductive parts21are arranged with the gate electrodes14in the X-direction. In the example ofFIG. 1, the first conductive part21is further provided multiply in the X-direction. The multiple gate electrodes14are positioned between a portion of the multiple first conductive parts21and another portion of the multiple first conductive parts21in the X-direction.

The second conductive part22extends in the X-direction. The second conductive part22is arranged with the multiple gate electrodes14and the multiple first conductive parts21. In the example ofFIG. 1, the second conductive part22is provided multiply in the Y-direction. The multiple gate electrodes14and the multiple first conductive parts21are positioned between the second conductive part22and the other second conductive part22.

The multiple first conductive parts21and the multiple second conductive parts22are provided only under the source electrode42in order not to be positioned under the gate pad43, for example.

As shown inFIG. 2, the first conductive part21is provided on the second region1bvia the first insulating part31. The first conductive part21opposes a portion of the n−-type semiconductor region1via the first insulating part31in the X-direction and the Y-direction. The first conductive part21is, for example, electrically connected to the source electrode42. Alternatively, the first conductive part21may be electrically connected to the gate electrode14and the gate pad43.

For example, a fourth conductive part24is provided in the first insulating part31between the first conductive part21and the p-type base region2. The fourth conductive part24is separated from the first conductive part21in the X-direction. For example, a length in the X-direction of the fourth conductive part24is shorter than a length in the X-direction of the first conductive part21. A length in the Z-direction of the fourth conductive part24is shorter than a length in the Z-direction of the first conductive part21. A potential of the fourth conductive part24is, for example, floating. Alternatively, the fourth conductive part24may be electrically connected to the source electrode42.

As shown inFIG. 3AandFIG. 3B, the second conductive part22is provided on the second region1bvia a second insulating part32. The second conductive part22opposes a portion of the n−-type semiconductor region1via the second insulating part32in the X-direction and the Y-direction. The second conductive part22is, for example, electrically connected to the source electrode42. Alternatively, the second conductive part22may be electrically connected to the gate electrode14and the gate pad43.

For example, as shown inFIG. 3AandFIG. 3B, the first conductive part21and the second conductive part22are continuously connected. The first insulating part31and the second insulating part32are continuously connected.

On example of materials of constituent components of the semiconductor device100will be described.

The n+-type semiconductor region1, the p-type base region2, the n+-type source region3, the p+-type contact region4, and the n+-type drain region5include silicon, silicon carbide, gallium nitride, or gallium arsenide as a semiconductor material. In the case where silicon is used as the semiconductor material, arsenic, phosphorous, or antimony can be used as an n-type impurity. Boron can be used as a p-type impurity.

The FP electrode10, the gate electrode14, the first conductive part21, and the second conductive part22include a conductive material such as polysilicon.

The insulating part11, the insulating part12, the gate insulating part15, the first insulating part31, and the second insulating part32include an insulating material such as silicon oxide.

The drain electrode41, the source electrode42, and the gate pad43include a metal such as aluminum.

The operation of the semiconductor device100will be described.

If a voltage not less than a threshold value is applied to the gate electrode14in a state in which a positive voltage to the source electrode42is applied to the drain electrode41, a channel (inversion layer) is formed at the gate insulating part15vicinity of the p-type base region2, and the semiconductor device100turned into an ON state. Electrons flow from the source electrode42to the drain electrode41through this channel. After that, when the voltage applied to the gate electrode14becomes lower than the threshold value, the channel in the p-type base region2disappears, and the semiconductor device100turns into an OFF state.

On example of a method for manufacturing the semiconductor device100will be described.

FIG. 4AtoFIG. 6Dare process cross-sectional views showing a manufacturing process of the semiconductor device according to the first embodiment.

FIG. 4AtoFIG. 6Dshow the manufacturing process of a portion corresponding to A-A′ cross section ofFIG. 1.

Firstly, a semiconductor substrate S including an n+-type semiconductor region5mand an n−-type semiconductor region1mis prepared. The n−-type semiconductor region1mis provided on the n+-type semiconductor region5m. Trenches T1and T2are formed on an upper surface of the n−-type semiconductor region1mby using a photolithography method and an RIE (Reactive Ion Etching) method as shown inFIG. 4A. The trench T1is formed multiply in the X-direction. The respective trenches T1extend in the Y-direction. The trench T2is formed multiply in the Y-direction. A dimension in the X-direction of the trench T2is longer than a dimension in the X-direction of the trench T1. The trench T1is a trench for forming the FP electrode10and the gate electrode14. The trench T2is a trench for forming the first conductive part21. In addition, in this process, a not-shown trench for forming the second conductive part22is formed.

The semiconductor substrate S is thermally oxidized, and an insulating layer11mis formed along a surface of the n−-type semiconductor region1m. As shown inFIG. 4B, a conductive layer10mwith which the trenches T1and T2are filled is formed on the insulating layer11mby using a CVD (Chemical Vapor Deposition) method.

As shown inFIG. 4C, a portion of the conductive layer10mis removed and thus multiple conductive layers10nseparated one another are formed. The conductive layer10nformed in the trench T2is covered with a not shown mask. As shown inFIG. 4D, a portion of the conductive layer10nformed in the trench T1is removed. The conductive layer10nremained in the trench T1corresponds to the FP electrode10. The conductive layer10nremained in the trench T2corresponds to the first conductive part21.

Outer circumference including the trench T2of the semiconductor substrate S is covered with a not shown mask. As shown inFIG. 5A, a portion of the insulating layer11mis removed by wet etching. Thereby, a portion of an inner surface of the trench T1and a portion of an inner surface of the trench T2are exposed. The semiconductor substrate S is thermally oxidized, and an insulating part15mis formed on the inner surface of the trench T1, the inner surface of the trench T2, and a surface of the first conductive part21. The insulating part15mis thinner than the insulating layer11m. An insulating layer12mis formed on an upper surface of the FP electrode10.

As shown inFIG. 5B, a conductive layer14mwith which the trenches T1and T2are filled is formed on the insulating part15m. A portion of the conductive layer14mis removed by using a CDE (Chemical Dry Etching) method or the RIE method. Thereby, as shown inFIG. 5C, multiple conductive layers are formed to be provided in the trench T1and the trench T2, respectively. The conductive layer formed in the trench T1corresponds to the gate electrode14. The conductive layer formed in the trench T2corresponds to the fourth conductive part24.

The p-type impurity is ion-implanted between the trenches T1and between the trenches T1and T2, and a p-type semiconductor region2mis formed. The n-type impurity is ion-implanted onto a surface of the p-type semiconductor region2mbetween the trenches T1, and an n′−-type semiconductor region3mis formed. As shown inFIG. 5D, an insulating layer35mcovering the gate electrode14and the fourth conductive part24is formed.

A photoresist PR is formed on the insulating layer35m. As shown inFIG. 6A, multiple openings OP1and an opening OP2are formed in the photoresist PR. A portion of the insulating layer35mis exposed through the multiple openings OP1and the opening OP2. The multiple openings OP1are positioned immediately above the multiple p-type semiconductor region2m, respectively. The opening OP2is positioned immediately above the first conductive part21.

Multiple openings OP3and an opening OP4are formed by using the photoresist PR as a mask. The respective openings OP3pierce the insulating layer35m, the insulating part15m, and the n+-type semiconductor region3m, and reach the p-type semiconductor region2m. The opening OP4pierces the insulating layer35mand the insulating part15m. The photoresist PR is removed, and the p-type impurity is ion-implanted to a bottom of the opening OP3. Thereby, as shown inFIG. 6B, the p+-type contact4is formed. The p-type semiconductor region2mother than the p+-type contact region4corresponds to the p-type base region2. The n+-type semiconductor region3mcorresponds to the n+-type source region3.

As shown inFIG. 6C, a metal layer is formed on the insulating layer35by using a sputtering method. The multiple openings OP3and the opening OP4are filled with this metal layer. The source electrode42and the gate pad43are formed by patterning this metal layer. A lower surface of the n+-type semiconductor region5mis ground until the n+-type semiconductor region5mhas a predetermined thickness. As shown inFIG. 6D, a metal material is deposited on the ground lower surface of the n+-type semiconductor region5mby using the sputtering method to form the drain electrode41. Through the above processes, the semiconductor device100shown inFIG. 1toFIG. 3Bis manufactured.

With respect to the trenches T1and T2formed by the process shown inFIG. 4A, a dimension in the X-direction of the trench T2is longer than a dimension in the X-direction of the trench T1. Thereby, as shown inFIG. 6A, a first distance in the X-direction between a step st1and the p-type semiconductor region2mcan be long. The step st1is formed between an upper surface of the insulating layer11mand an upper surface of the first conductive part21. When the first distance becomes long, a second distance in the X-direction between a step st2formed on an upper surface of the insulating layer35mand p-type semiconductor region2mbecomes longer. When the step st2is present, a step st3is generated on a surface of the photoresist PR. When the second distance becomes long, a position of the step st3can be shifted to the outer circumference side of the semiconductor substrate S from a position where the opening OP2is formed.

A thickness of a portion where the step st3of the photoresist PR is present is larger than a thickness of other portion of the photoresist PR such as on the gate electrode14. Therefore, if the position of the step st3overlaps the position of the opening OP2, the photoresist PR is not removed sufficiently when forming the opening OP2, and there is a possibility that the insulating layer35mis not exposed. In the case where the insulating layer35mis not exposed through the opening OP2, the opening OP4is not formed adequately. As a result, there is a possibility that the first conductive part21is not connected to the source electrode42. As described above, the opening OP4can be formed adequately by shifting the position of the step st3from the position where the opening OP2is formed.

The effect of the first embodiment will be described with reference toFIG. 7AtoFIG. 9.

FIGS. 7A to 7Care circuit diagrams illustrating electric circuits in which the semiconductor device according to the first embodiment is connected.

FIG. 8is a graph showing a current and a voltage in the semiconductor device in the electric circuit shown inFIG. 7.

FIG. 9is a plan view schematically showing a flow of a hole in the semiconductor device according to the first embodiment.

Semiconductor regions other than the n−-type semiconductor region1and the p-type base region2are omitted inFIG. 9.

In the examples shown inFIG. 7AtoFIG. 7C, two semiconductor devices100-1and100-2according to the embodiment are used, and a half bridge circuit is formed.FIG. 7Ashows an aspect in which the semiconductor device100-1is in an ON state and the semiconductor device100-2is in an OFF state. In the semiconductor device100-1, an ON current IONflows.

When the semiconductor device100-1is turned off in a state shown inFIG. 7A, an induced electro motive force due to an inductance L is generated. Thereby, as shown inFIG. 7B, a forward current IFflows in a diode composed of the n−-type semiconductor region1and the p-type base region2of the semiconductor device100-2. At this time, a hole is injected from the source electrode42to the n−-type semiconductor region1, and an electron is injected from the drain electrode14to the n−-type semiconductor region1.

When the forward current runs out in the diode of the semiconductor device100-2, a carrier stored inside the semiconductor device100-2is discharged. At this time, the hole stored in the n−-type semiconductor region1is discharged to the source electrode42. The electron is discharged to the drain electrode41. The carrier is discharged from the semiconductor device100-2, and thus as shown inFIG. 7C, a reverse recovery current IRflows in the semiconductor device100-2. The reverse recovery current IRflows from the drain electrode41toward the source electrode42.

InFIG. 8, a solid line represents a current flowing in the semiconductor device100-2. A broken line represents a voltage of the drain electrode41to the source electrode42. The horizontal axis represents a time, and the vertical axis represents a current value. The current value is represented by taking a direction from the drain electrode41toward the source electrode42as positive.

As shown inFIG. 8, if the forward current runs out at a timing t1, thereafter, the reverse recovery current starts to flow. The voltage of the drain electrode41to the source electrode42of the semiconductor device100-2starts to increase. At this time, a serge voltage Vs is generated in the voltage V depending on dIR/dt of a slope of the reverse recovery current decrease. If the dIR/dt is large, the serge voltage Vs also increases. If the serge voltage Vs is large, a parasitic NPN transistor composed of the n+-type source region3, the p-type base region3, and the n−-type semiconductor region1is easy to operate. If the parasitic NPN transistor operates, a large current flows in the semiconductor device, and there is a possibility that the semiconductor device is destroyed. Therefore, the dIR/dt is desired to be small.

A portion of the injected carrier at the diode operation is stored in the outer circumference of the type semiconductor region1as well. The hole stored in the outer circumference of the n−-type semiconductor region1moves to the near p-type base region2at the reverse recovery operation and is discharged to the source electrode42. Therefore, more holes than holes in other portion flow in the p-type base region2provided on the outer circumference. Therefore, the potential of the p-type base region2is easy to rise, and the parasitic NPN transistor is more easily operated.

With respect to this problem, in the semiconductor device100, the multiple first conductive parts21are provided on the second region1bof the n−-type semiconductor region1. The multiple first conductive parts21are separated one another. The multiple first conductive parts21are electrically connected to the source electrode42or the gate electrode14(gate pad43). That is, when the semiconductor device100is in the OFF state, the potential of the first conductive part21is negative to the hole.

According to this configuration, a portion of the holes h stored in the outer circumference of the n−-type semiconductor region1passes between the first conductive parts21and flows to the p-base base region2as shown by a broken line arrow ofFIG. 9. Another portion of the holes h is trapped in the vicinity of the first insulating part31as shown by a dotted line arrow. The trapped holes h flow to the p-type base region2with taking a long time in comparison with the non-trapped holes h.

In this way, the multiple first conductive parts21separated one another are provided, and thus variations in time until the holes h arrive at the p-type base region2can be large. As a result, the dIR/dt shown inFIG. 8can be small, and the possibility that the semiconductor device is destroyed by the operation of the parasitic NPN transistor can be reduced.

As shown inFIG. 9, a length L1in the X-direction of the first conductive part21is desired to be longer than a length L2in the X-direction of the gate electrode14. The length L1is long, and thus the holes h are easily trapped in the vicinity of the first insulating part31, and the dIR/dt can be further small.

A distance D1in the X-direction between the first insulating parts31is desired to be the same as a distance D2in the X-direction between the gate insulating parts15or to be shorter than the distance D2. The distance D1is, for example, the same as a length in the Y-direction of a portion between the first insulating parts31of the n−-type semiconductor region1. The distance D2is, for example, the same as a length in the X-direction of a portion between the gate insulating parts15of the n−-type semiconductor region1. The distance D2is, for example, the same as a length in the X-direction of the p-type base region2between the gate insulating parts15.

For example, a thickness of the first insulating part31is larger than a thickness of the gate insulating part15. In such a case, when the semiconductor device100is turned off, in the n−-type semiconductor region1in the vicinity of the first insulating part31, a depletion layer is hard to broaden more than in the n−-type semiconductor region1in the vicinity of the gate electrode14and the FP electrode10. If the distance D1is long in the configuration of the multiple first conductive parts21separated one another, the n−-type semiconductor region1between the first insulating parts31is hard to be depleted. As a result, there is a possibility that a breakdown voltage of the semiconductor device100is decreased.

In order to facilitate depletion of the n−-type semiconductor region1between the first insulating parts31and to suppress the breakdown voltage of the semiconductor device100from decreasing, the distance D1is desired to be not more than the distance D2. The distance D1is more preferably to be less than the distance D2. Thereby, the n−-type semiconductor region1between the first insulating parts31is more easily depleted, and the breakdown voltage of the semiconductor device100can be suppressed from decreasing.

A distance D3in the Y-direction between the first insulating part31and the second insulating part32is desired to be the same as the distance D2or to be shorter than the distance D2. The distance D3is, for example, the same as a length in the Y-direction of a portion between the first insulating part31and the second insulating part32of the n−-type semiconductor region1. According to this configuration, the breakdown voltage of the semiconductor device100can be suppressed from decreasing as well as the above.

FIG. 10is a plan view showing a semiconductor device according to a variation of the first embodiment.

The plan view ofFIG. 10shows a cross section at a B-B′ line ofFIG. 11.

As shown inFIG. 10, a semiconductor device110according to the variation of the first embodiment further includes multiple third conductive parts23. The multiple conductive parts23are separated in the Y-direction one another. The respective third conductive parts23extend in the X-direction. A portion of the respective third conductive parts23is positioned under the gate pad43.

A portion of the gate electrode14is positioned in the X-direction between the multiple first conductive parts21and the multiple third conductive parts23. A portion of the second conductive parts22is provided under the gate pad43. The multiple third conductive parts23are positioned in the Y-direction between the first conductive parts21and the portion of the second conductive parts22and between the multiple gate electrodes14and another portion of the second conductive parts22. A length in the X-direction of the third conductive parts23is longer than lengths in the X-direction of the respective gate electrodes14and the first conductive parts21.

As shown inFIG. 11, the third conductive part23is provided on the second region1bvia the third insulating part33. The third conductive part23opposes a portion of the n−-type semiconductor region1via the third insulating part33in the X-direction and the Y-direction. The gate pad43is provided on the third conductive part23via an insulating part36. The third conductive part23is electrically connected to the source electrode42. The third conductive part23may be electrically connected to the gate electrode14and the gate pad43.

When a current flows in the diode of the semiconductor device100, carriers are also stored in the n−-type semiconductor region1under the gate pad43. Holes stored under the gate pad43flow to the p-type base region2close to the gate pad43. Therefore, in the p-type base region2close to the gate pad43, the potential is easy to rise, and the parasitic NPN transistor is more easily to operate.

As shown inFIG. 10, the multiple third conductive parts23are provided, and thus similar to the multiple first conductive parts21, a portion of the holes h can be trapped when the holes h are discharged to the source electrode42. Thereby, the operation of the parasitic NPN transistor near the gate pad43can be suppressed, and the possibility that the semiconductor device is destroyed can be further reduced.

Second Embodiment

FIG. 12is a plan view showing a semiconductor device according to a second embodiment.

The plan view ofFIG. 12shows a cross section at a D-D′ line ofFIG. 13A.

In a semiconductor device200according to a second embodiment, as shown inFIG. 12, the multiple first conductive parts21are separated one another in the X-direction. The multiple first conductive parts21are arranged with the multiple gate electrodes14in the Y-direction. The second conductive parts22are arranged with the gate electrodes14and the first conductive parts21in the X-direction.

In the example shown inFIG. 12, the multiple gate electrodes14are positioned in the Y-direction between a portion of the multiple first conductive parts21and another portion of the multiple first conductive parts21. At least a portion of the respective gate electrodes14is positioned between the second conductive part22and the other second conductive part22.

As shown inFIG. 13A, for example, a distance D5in the X-direction between the gate insulating part15and the second insulating part32is the same as a distance D6between the gate insulating parts15. For example, as shown inFIG. 13B, a distance D7in the X-direction between the first insulating part31and the second insulating part32is the same as a distance D8between the first insulating parts31. Alternatively, the distance D8is shorter than the distance D6. A length L3(shown inFIG. 14) in the Y-direction of the first conductive part21is longer than a length L4(shown inFIG. 13A) in the X-direction of the gate electrode14.

Also in the embodiment, the multiple first conductive parts21are provided, and thus similar to the first embodiment, it is possible to increase variations in time until the holes h reach the p-type base region2. Thereby, the dIR/dt in the reverse recovery operation can be small, and the possibility that the semiconductor device is destroyed by the operation of the parasitic NPN transistor can be reduced.

In the semiconductor device according to the second embodiment, similar to the semiconductor device110, the multiple third conductive parts23may be provided under the gate pad43. In such a case, the multiple third conductive parts23are separated one another in the X-direction. The multiple third conductive parts23are provided, and thus the operation of the parasitic NPN transistor near the gate pad43can be suppressed, and the possibility that the semiconductor device is destroyed can be further reduced.

In order to improve the breakdown voltage, the multiple first conductive parts21are desired to be arranged in the Y-direction such as the semiconductor device100. This point will be described with reference toFIGS. 15A to 15D.

FIGS. 15A to 15Dare plan views showing a portion of the semiconductor device according to the first embodiment and a portion of the semiconductor device according to the second embodiment.

In the examples shown inFIGS. 15A to 15D, a distance between the insulating parts11, a distance between the first insulating parts31, a distance between the insulating part11and the first insulating part31, a distance between the insulating part11and the second insulating part32, and a distance between the first insulating part31and the second insulating part32are the same one another.

FIG. 15Ashows the vicinity of an end portion of the semiconductor device200in the Y-direction.FIG. 15Bshows the vicinity of an end portion in the X-direction of the semiconductor device200. As shown inFIG. 15A, a distance D11is 1/√2 times of the distance D. The distance D11is a distance between the respective insulating parts and a center point C1among one pair of first insulating parts31and one pair of insulating parts11. The distance D is a distance between the insulating parts11.

On the other hand, as shown inFIG. 15B, a distance D12is 1/√3 times of the distance D. The distance D12is a distance between the respective insulating parts and a center point C2among the insulating part11, the first insulating part31, and the second insulating part32.

That is, the distance D11is different from the distance D12, and longer than the distance D12. A difference between the distance D11and the distance D is larger than a difference between the distance D12and the distance D. If differences of these distances are large, variations are generated in spreading of the depletion layer, and the breakdown voltage of the semiconductor device may decrease.

FIG. 15Cshows the vicinity of an end portion of the semiconductor device100in the Y-direction.FIG. 15Dshows the vicinity of an end portion of the semiconductor device100in the X-direction. As shown inFIG. 15C, a distance D13is 1/√3 times of the distance D. The distance D13is a distance between the respective insulating parts and a center point C3among one pair of first insulating parts11and the second insulating part32.

As shown inFIG. 15D, a distance D14is 1/√3 times of the distance D between the insulating parts11. The distance D14is a distance between the respective insulating parts and a center point C4among the gate insulating layer15and one pair of first insulating parts31.

That is, the distance D13is the same as the distance D14. In comparison with the semiconductor device200, a difference between the distance D and each of the distance D13and the distance D14is smaller than the difference between the distance D11and the distance D.

Because of this, in the semiconductor device100, a difference between spreading of the depletion layer in the vicinity of the first insulating part31and spreading of the depletion layer in the vicinity of the second insulating part32can be small. Therefore, even if the multiple first conductive parts21are separated one another, the breakdown voltage can be suppressed from decreasing.

Third Embodiment

FIG. 16is a plan view showing a semiconductor device according to a third embodiment.

In a semiconductor device300according to a third embodiment, the multiple first conductive parts21are arranged with the gate electrodes14in the X-direction. The multiple first conductive parts21are separated in the Y-direction one another. The multiple second conductive parts22are arranged with the multiple gate electrodes14in the Y-direction. The multiple second conductive parts22are separated in the X-direction one another.

In the example shown inFIG. 16, the multiple gate electrodes14are positioned in the X-direction between a portion of the multiple first conductive parts21and another portion of the multiple first conductive parts21. The multiple gate electrodes14are positioned in the Y-direction between a portion of the multiple second conductive parts22and another portion of the multiple second conductive parts22.

The multiple first conductive parts21and the multiple second conductive parts22are provided, and thus it is possible to increase variations in time until the holes h arrives at the p-type base region2in a broader range of the outer circumferential part of the n−-type semiconductor region1. Thereby, the possibility that the semiconductor device is destroyed by the operation of the parasitic NPN transistor can be further reduced.

In the embodiments described above, relative high and low concentrations of impurities between the respective semiconductor regions are possible to be confirmed by using SCM (Scanning Electrostatic Capacitance Microscopy). Carrier concentrations in the respective semiconductor regions can be regarded to be equal to the activated impurity concentrations in the respective semiconductor regions. Therefore, relative high and low concentrations of carriers between the respective semiconductor regions are also possible to be confirmed by using SCM (Scanning Electrostatic Capacitance Microscopy).

Impurity concentrations in the respective semiconductor regions are possible to be measured, for example, by SIMS (Secondary Ion Mass Spectroscopy).