Physically unclonable circuit having a programmable input for improved dark bit mask accuracy

An apparatus is described. The apparatus includes a physically unclonable (PUF) circuit having a programmable input. The programmable input is to receive a value that caused the PUF circuit to strengthen its stability or strengthen its instability.

FIELD OF INVENTION

The field of invention pertains generally to the semiconductor arts, and, more specifically, to a physically unclonable circuit having a programmable input for improved dark bit mask accuracy.

BACKGROUND

With the increased miniaturization of circuits and the dimensions of their constituent structures (e.g., transistors), reliability problems may become more prevalent particularly for circuits exposed to extreme environmental conditions (e.g., performance, temperature, etc.). As such, it behooves system designers to include embedded functions that detect the presence of a reliability issue before a catastrophic failure event occurs.

DETAILED DESCRIPTION

Circuits are generally designed to be insensitive (as much as practicable) to manufacturing tolerances. However, a class of circuits may be designed that are purposefully sensitive to manufacturing tolerances (so called, “physically unclonable circuits” or PUFs). For instance, a circuit that is implemented on a semiconductor chip may be designed to have a measurable or determinable property that is highly sensitive to the threshold and/or the gain of its constituent transistors.

With significant sensitivity to certain parameters, and with the underlying manufacturing process having inherent variation with respect to these same parameters, identically designed instances of the circuit can exhibit different properties even if manufactured on the same semiconductor chip.FIG. 1shows an example of a PUF circuit100that if implemented on a semiconductor chip will have properties that are sensitive to the threshold and gain of its constituent transistors.

As observed inFIG. 1, the PUF circuit100includes a pair of inverters101,102with the respective output of both inverters being coupled to the respective input of the other inverter. Those of ordinary skill will recognize cross coupled inverters101,102implement a latch circuit that is inherently stable by itself (a 0 at the input of a first inverter provides a 1 at the input of the second inverter which re-enforces the 0 applied at the first inverter). Here, the circuit100operates according this stable mode when both of transistors Q1and Q2are off which occurs when the control node103is set to a logic 0.

However, when the control node103transitions to a logic 1, the circuit100attempts to turn on both of transistors Q1and Q2, which initially places the circuit into an unstable state. The unstable state will quickly return to a stable state if there is sufficient manufacturing variation amongst the different transistors of the inverters101,102, transistors Q1and Q2and/or the interconnect resistances between them. That is, although the circuit100as designed is symmetrical or balanced, owing to manufacturing tolerances, it may not actually be symmetrical or balanced as actually manufactured. If the circuit100is sufficiently imbalanced, the circuit will naturally “snap” to a stable state that is induced by the imbalance shortly after transistors Q1and Q2turn on.

For example, if transistors Q1and Q2have different response times, after the control node transitions to a logic 1, whichever of latch nodes104,105is coupled to the faster one of transistors Q1and Q2will be pulled to a logic high before the latch node that is coupled to the slower one if transistor Q1and Q2. As such, the circuit will naturally snap to a stable state in which the latch node that is coupled to the faster of transistors Q1and Q2will be held at a logic 1 and the latch node that is coupled to the slower of transistors Q1and Q2will be held at a logic 0. The value that is held at node105is ultimately latched into flip-flop106which essentially stores which specific one of two possible states the node105snapped to.

Even if transistors Q1and Q2are manufactured identically, however, the circuit100can still snap to a stable state if there exists sufficient manufacturing differences associated with the inverters101,102themselves. As is known in the art, transistor gain variation and/or transistor threshold voltage variation can affect the time at which an inverter will cause a receiving inverter to flip its output bit. Specifically, a lower driving inverter gain and a higher receiving inverter threshold will cause the receiving inverter to flip its output bit later in time. By contrast, a higher driving inverter gain and a lower receiving inverter threshold will cause the receiving inverter to flip its output bit sooner in time. For simplicity only transistor gain and threshold have been mentioned. But other manufacturing related properties can affect the timing of an inverter loop as described above (e.g., interconnect resistance(s), contact resistance(s), variation in transistor dimension(s), random dopant fluctuation etc.).

Here, even if both of the latch nodes104,105are simultaneously pulled to a logic 1 when the control node transitions to a logic 1 (because transistors Q1and Q2are identical), one of latch nodes104,105will start to be driven to a logic 0 before the other of the latch nodes104,105(again, owing to, e.g., manufacturing differences in the transistors within the inverters101,102). Once one of the latch nodes104,105starts to be driven to a logic 0 before the other of the latch nodes104,105, the circuit100will quickly snap to a stable state that holds the latch node that was first driven to logic 0 to a logic 0 and holds the other latch node to a logic 1. Again, whichever value node105snaps to is stored in flip-flop106.

FIG. 2shows a circuit having N instances201_1through201_N of a circuit, such as the PUF circuit described just above, that sets itself to a 1 or a 0 depending on its specific combination of manufacturing variation(s). In an embodiment, the circuits201_1through201_N are integrated on a same semiconductor chip (whereas in other embodiments the circuits may be integrated on a same printed circuit board). For convenience, a semiconductor die will be mostly referred to as an example.

In an embodiment that, e.g., uses the aforementioned PUF circuit100ofFIG. 1for each of PUF circuits201_1through201_N, during the final product testing of the manufactured semiconductor die, the control node103transitions to a 1 to cause each of the N circuits to snap to their respective stable bit value which is then stored in each circuit's respective flip-flop202_1through202_N. Each of the respective stable bit values kept in the flip flops202_1through202_N are then stored, in a separate nonvolatile memory203as a unique word or signature of the semiconductor chip. That is, with the storage of the N individual snapped-to stable bits into the non volatile memory203, the nonvolatile memory circuit203is essentially storing a signature of the specific distribution of the associated fabrication induced variation properties at the time of manufacture of the semiconductor chip.

As is known in the art, over the course of time and use, electronic circuitry will degrade such that at least one of its manufacturing related properties will change. As a consequence, the N PUF circuits201_1through201_N may begin to demonstrate a change in their behavior. As such, the respective N bit signature may change over time. In the case of a reliability problem or manufacturing defect that corresponds to a serious degradation problem, the signature will change some significant amount which can subsequently be flagged as an early detection warning that the electronic chip or board is prone to imminent failure. As such, corrective action can be taken before a more serious fatal hard failure occurs. As such, readouts of the signature are made from time to time during the lifetime of the chip and compared by a comparator205to the original signature that was captured at manufacture and stored in the non volatile memory203. Upon detection of a significant difference between the current signature and the original signature, an error flag206is raised.

The discussion above with respect toFIGS. 1 and 2assumed that each of the PUF circuits201_1through201_N will snap to a stable value. There can be instances, however, where a PUF circuit as manufactured is symmetrical or balanced such that it does not snap to a stable state when the control node transistions to a logic 1. For example, if transistors Q1and Q2are manufactured identically and both invertors are manufactured identically, the aforementioned mechanisms that snap the PUF circuit to a stable state may not arise. As such, the PUF circuit does not immediately snap to a stable state and instead remains in an unstable state for an extended period of time and/or, the PUF circuit will snap to a state based on temporal conditions like thermal noise, voltage droop, coupling from other circuits etc. Hence there is a high chance it will resolve to different states when evaluated multiple times.

Recognizing that the flip-flop106is designed to capture the value of node105a short time after the control value is set to a logic 1 (e.g., upon the control node103transitioning back to a logic 0 a short time after the control node103transitioned to a logic 1), the flip-flop106will latch either a 1 or 0 because the PUF circuit100did not snap to a stable state before the flip-flop106latched in its input value.

Circuits that behave in this manner (do not consistently resolve to one state) are unstable. In an embodiment, referring toFIG. 2, unstable PUF circuits are identified and their corresponding latched bit as read from their respective flip-flop are ideally not used for the signature code of the circuit that is used to detect chip degradation problems. As such, the signature word that is actually used is less than N bits. Here, the bits from unstable PUF circuits are marked as “dark bits”. A dark bit mask vector (hereinafter, “dark bit mask”) is also stored in the non volatile memory203that identifies which ones of the N bits from N PUF circuits emanate from an unstable PUF circuit. The dark bit mask is used to ignore the bits generated from the unstable PUF circuits whenever the signature for the circuit is being determined. The same positioned bits are also ignored by the comparator205when performing its comparison.

FIG. 3shows an improved PUF circuit300that can reduce or minimize its propensity to be deemed unstable. Here, as observed inFIG. 3, a counter307is coupled to receive the specific bit value that is latched into the flip flop306. Rather than take only one sample (i.e., transition the control value103to a value of 1 once per read of the PUF circuit100as described above with respect toFIG. 1), instead, multiple samples of the circuit300are taken and fed to a counter307. Here, multiple samples are taken by driving the control node303with a clock signal (CLK). Each time the clock transitions to a logic high, the circuit300will re-attempt to snap to a stable value. Upon each sample (i.e., each clock transition to a logic 1), the value latched by the flip-flop306is provided to the counter307. In an embodiment, if the flip-flop306has latched a 1 the counter307will increment, or, if the flip-flop306has latched a 0 the counter307will not increment.

If after a number of clock transitions (samples) a vast majority of the latched values correspond to a 1, the counter value307will have surpassed some threshold (Y) deemed sufficient to deem the circuit300stable at a value of 1. By contrast, if after a sufficient number of clock transitions (samples) the vast majority of the latched values correspond to a 0, the counter307will stay beneath some lower threshold (X) (e.g., a value just above 0) and the circuit300will be deemed stable at a value of 0. Here, although the circuit300may be unstable in the context of only one sample, it is possible that there exist latent mechanisms that will cause the circuit300to snap to one of the values much more frequently than the other of the values. In such cases, with enough samples taken, the circuit300can be deemed stable rather than unstable.

As such, with the improvement of taking a number of samples rather than just one sample, a number of the PUF circuits201ofFIG. 2may be deemed stable rather than unstable, which, in turn, reduces the size of the dark bit mask and instead expands the size of the unique signature of the semiconductor chip. With a larger size signature, degradation of the semiconductor chip will be more readily identified in advance of a hard failure than is possible with a smaller size signature.

Still yet another problem is the dependency that PUF circuit can have on existing conditions such as temperature and voltage. For example, a specific one of the PUF circuits201ofFIG. 2may be stable at a first set of conditions yet be unstable at a second set of conditions. Likewise, another specific one of the PUF circuits201ofFIG. 2may be unstable at the first set of conditions yet be stable at the second set of conditions.

Here, the inability to precisely characterize which PUF circuits201are stable and which circuits are unstable threatens the viability of the overall technique in that the dark bit mask may be accurate for one set of conditions but is not accurate for a different set of conditions. Storing different dark bit masks for different conditions is possible, but a more robust approach includes the ability to initially deem each of the PUF circuits201as stable or unstable at manufacturing and then have those characterizations remain accurate over the lifetime of the circuit irrespective of the conditions that the semiconductor chip is subject to.

Thus, in order to enhance the ability to permanently characterize a PUF circuit as stable or unstable,FIG. 3also shows the existence of a multiplexer309that is used to program a value into the PUF circuit300that causes the circuit300to drive itself towards being stable or unstable during a burn-in sequence.

A burn-in sequence is a special stress test that is applied to circuits as part of their standard manufacturing process. Here, elevated temperatures and/or voltages are applied to the manufactured chip or board to age the transistors and other manufactured features to their more permanent state. That is, early in the life of a circuit, various parameters of its constituent transistors and other manufactured features will drift (e.g., logarithmically) toward a respective more permanent, “settled in” state. The burn-in is designed to cause these parameters to reach this state before the manufactured circuit is actually shipped.

In the PUF circuit300ofFIG. 3, if the circuit300is deemed stable because it consistently snaps to a same logic value as reflected from the counter output (count value is greater than Y or less than X), and if the opposite of that value is presented to the second multiplexer input311during a burn-in, the presentation of the opposite value to the multiplexer309during the burn-in will have the effect of strengthening the circuit's stability.

Here, the circuit ofFIG. 3is programmed by a user (e.g., a burn-in test program executed on a manufacturing facility) placing a logic value at the second input311of the multiplexer309. During the burn-in, the BURN-IN input312is a logic high which disables the clock input303. The second input311of the multiplexer309is selected which causes the flip-flop306to latch the user provided value. In the case of a stable circuit, as discussed above, the opposite value that the circuit snaps to at node305is latched into the flip-flop306which has the effect of driving node305harder to its stable value thus strengthening the stability of the circuit through accelerated ageing.

In the case of an unstable circuit, the same value that the circuit tends to snap to is programmed at the second input311of the multiplexer309and latched by the flip-flop306which has the effect of driving node305harder to an opposite value than the value that the circuit tends to snap to, which, in turn, destabilizes the circuit even further. In an embodiment, delay buffering (e.g., a pair of inverters in series (not shown)) is placed at the front of the gate nodes of both of transistors Q1and Q2to inject a differential delay bias for the burn-in (when the CLK is disabled) that enhances the stability strengthening/weakening process for the circuit during the burn-in.

Thus, if the PUF circuit300consistently snaps to a 1 and then a 0 is presented to the second multiplexer input311during a burn-in, the circuit300will work harder to drive itself to a 1 at latch node305which causes the circuit to settle/mature with an even greater propensity to snap to a 1. Likewise, if a PUF circuit300consistently snaps to a 0 and then a 1 is presented to the second multiplexer input310during a burn-in, the circuit300will work harder to drive itself to a 0 at latch node305which causes the circuit300to settle/mature with an even greater propensity to snap to a 0.

The opposite is also true. That is, if the circuit300is deemed stable because it consistently snaps to a same logic value, and if the same value is presented to the second multiplexer input311during a burn-in, the presentation of the same value during the burn-in will have the effect of weakening the circuit's stability.

For example, if the PUF circuit300consistently snaps to a 1 and then a 1 is presented to the second multiplexer input311during a burn-in, the circuit300will work harder to drive itself to a 0 at latch node305which causes the circuit to settle/mature with less of a propensity to snap to a 1 than it did before the burn in. As such, the circuit is more unstable after the burn-in than before the burn-in. Likewise, if the PUF circuit300consistently snaps to a 0 and then a 0 is presented to the second multiplexer input311during a burn-in, the circuit300will work harder to drive itself to a 1 at latch node305which causes the circuit300to settle/mature with less of a propensity to snap to a 0 than it did prior to the burn in. Again, the circuit300is more unstable after the burn-in than before the burn-in.

Thus, programming the PUF circuit300with the opposite of the value it naturally stabilizes to has the effect of strengthening that stability. By contrast, programming the PUF circuit300with the same value that it naturally stabilizes to has the effect of unstabilizing the circuit300.

When not in a burn-in mode, the BURN_IN input312is low which enables the clock input303and effectively disables the feedback path from the flip-flop to transistors Q1and Q2. The first input310of the multiplexer309is selected which causes the circuit to operate normally as described above.

Recall the above discussion with respect toFIG. 2that being able to permanently declare each of the PUF circuits201_1through201_N as stable or unstable is important if a dark bit vector is to be generated that is accurate over multiple, different conditions. Thus, in an embodiment, those of the PUF circuits201_1through201_N that are deemed stable after a number of samples are taken are given an opposite value during burn-in to further strengthen their stability. By contrast, those of the PUF circuits201_1through201_N that are deemed unstable after a number of samples are taken are given a same value during burn-in to further strengthen their instability.

Note that the PUF circuits ofFIGS. 1 and 3can be implemented as hardware circuitry disposed on a semiconductor chip or printed circuit board. With respect to the PUF circuit ofFIG. 3, the counter circuitry307and/or threshold detection circuitry308can be implemented as a custom hardwired circuit, a programmable circuit (e.g., a programmable logic device (PLD), programmable logic array (PLA) or field programmable gate array (FPGA)) or a circuit that executes some form of program code such as a controller (e.g., a microcontroller) or processer (e.g., an embedded processor) or any combination of these. The signature checking circuit ofFIG. 2can also be implemented on a semiconductor chip or printed circuit board. Here, the comparison checking circuitry205can be implemented as a custom hardwired circuit, a programmable circuit (e.g., a programmable logic device (PLD), programmable logic array (PLA) or field programmable gate array (FPGA)) or a circuit that executes some form of program code such as a controller (e.g., a microcontroller) or processer (e.g., an embedded processor) or any combination of these.

FIG. 4shows a testing methodology that operates as described above. Here, a plurality of PUF circuits are tested for stability401, e.g., by taking a number of samples such as driving a control node with a clock signal as described above with respect toFIG. 3. Those of the PUF circuits that are deemed stable (e.g., because their respective counter reached a certain high threshold or stayed below a certain low threshold) are programmed with a value (e.g., the opposite value they stabilized to) for burn-in that strengthens their stability402.

By contrast, circuits that are deemed unstable (e.g., because the counter did not reach a certain high threshold and rose above a certain low threshold) are identified as unstable and programmed with a value (e.g., the same value they showed some stabilization toward) for burn-in that strengthens their instability403. The circuits are then burned-in, a dark bit mask vector is created (e.g., that identifies the unstable PUF circuits) and signature vector is created (e.g., that records the respective values from the stable PUF circuits)404.

FIG. 5shows a depiction of an exemplary computing system500such as a personal computing system (e.g., desktop or laptop) or a mobile or handheld computing system such as a tablet device or smartphone, or, a larger computing system such as a server computing system. As observed inFIG. 5, the basic computing system may include a central processing unit501(which may include, e.g., a plurality of general purpose processing cores and a main memory controller disposed on an applications processor or multi-core processor), system memory502, a display503(e.g., touchscreen, flat-panel), a local wired point-to-point link (e.g., USB) interface504, various network I/O functions505(such as an Ethernet interface and/or cellular modem subsystem), a wireless local area network (e.g., WiFi) interface506, a wireless point-to-point link (e.g., Bluetooth) interface507and a Global Positioning System interface508, various sensors509_1through509_N (e.g., one or more of a gyroscope, an accelerometer, a magnetometer, a temperature sensor, a pressure sensor, a humidity sensor, etc.), a camera510, a battery511, a power management control unit512, a speaker and microphone513and an audio coder/decoder514.

An applications processor or multi-core processor550may include one or more general purpose processing cores515within its CPU501, one or more graphical processing units516, a memory management function517(e.g., a memory controller) and an I/O control function518. The general purpose processing cores515typically execute the operating system and application software of the computing system. The graphics processing units516typically execute graphics intensive functions to, e.g., generate graphics information that is presented on the display503. The memory control function517interfaces with the system memory502.

Each of the touchscreen display503, the communication interfaces504-507, the GPS interface508, the sensors509, the camera510, and the speaker/microphone codec513,514all can be viewed as various forms of I/O (input and/or output) relative to the overall computing system including, where appropriate, an integrated peripheral device as well (e.g., the camera510). Depending on implementation, various ones of these I/O components may be integrated on the applications processor/multi-core processor550or may be located off the die or outside the package of the applications processor/multi-core processor550.

The computing system500may include (e.g., on a printed circuit board of the computing system and/or within a semiconductor chip of the computing system) that PUF circuits as described above where the PUF circuits can be sampled multiple times to further access stability and/or were burned-in such that initially stable circuits were burned in to strengthen their stability and initially unstable circuits were burned in to weaken their stability.

Embodiments of the invention may include various processes as set forth above. The processes may be embodied in machine-executable instructions. The instructions can be used to cause a general-purpose or special-purpose processor to perform certain processes. Alternatively, these processes may be performed by specific hardware components that contain hardwired logic for performing the processes, or by any combination of software or instruction programmed computer components or custom hardware components, such as application specific integrated circuits (ASIC), programmable logic devices (PLD), digital signal processors (DSP), or field programmable gate array (FPGA).