Power on reset apparatus

A power on reset (POR) circuit is provided. For the POR circuit, a PMOS transistor is coupled to a first voltage rail at its source. A drive circuit is coupled to the drain of the PMOS transistor and is configured to output a POR signal. A voltage divider is coupled between the drain of the PMOS transistor and the second voltage rail. A switch network is provided as well, which has first and second switches. The first switch is coupled between the gate of the PMOS transistor and the voltage divider, and the second switch is coupled between the gate of the PMOS transistor and the voltage divider. A controller is also coupled to control the first and second switches, wherein the first and second switches are complementary driven.

TECHNICAL FIELD

The invention relates generally to a power on reset (POR) circuit.

BACKGROUND

Turning toFIGS. 1 and 2, an example of a conventional POR circuit100and its desired performance can be seen. Typically, the POR circuit100is intended to provide a reset or reset signal during times of applied ramp up of the voltage on rail VDD. This can allow logic and other circuitry within a system in which the POR circuit100is employed to be reset to a default state during ramp up of the voltage on rail VDD or to restore the default state during a “brownout” event. To do this, the POR circuit100has two characteristic voltages: high threshold PORH and a low threshold PORL. The high threshold PORH is the “release threshold,” where the POR circuit100releases the reset signal as the voltage on rail VDD is increasing or ramping up to the nominal voltage VDDN, and the low threshold PORL is the “activate threshold,” where the reset signal is asserted as the voltage on rail VDD is decreasing or ramping down. The low threshold PORL is a lower voltage than high threshold PORH so as to provide a hysteresis to prevent “bouncing” of the reset signal POROUT if the voltage on rail VDD is near the threshold.

When the voltage on voltage rail VDD is rising or ramping up (i.e., between times T1and T2and between times T7and T8), the POR signal POROUT (which is an active low reset signal) transitions from logic low (or “0”) to logic high (or “1”) once the voltage on rail VDD becomes greater than high threshold PORH (and which eventually reaches a nominal voltage VDDN). Typically, this ramping up or increase in the voltage occurs during power-up (i.e., between times T1to T2) or following a “brownout” event (i.e., between times T12and T13). In the structure shown inFIG. 1, this high threshold PORH is set by the characteristics of transistors Q1and Q4and resistor R1. Looking first to transistor Q1(which, as shown is a PMOS transistor), the drain current ID, in saturation, for transistor Q1is:

ID=12⁢(WL·μ⁢⁢COX)⁢(VGS-VTP)2=k2⁢(VGS-VTP)2,(1)
where VGSis the gate-source voltage of transistor Q1, VTPis the threshold voltage for transistor Q1, W/L is the aspect ratio (channel width to length) of transistor Q1, μ is the charge-carrier mobility, and COXis the gate oxide unit capacitance. So, as a result of configuration of POR circuit100, the POR circuit100is released when:
R1·ID≧VTN,  (2)
where VTNis the threshold voltage of transistor Q4(which, as shown, is an NMOS transistor). Substituting equation (1) into equation (2) and solving for the gate-source voltage VGSof transistor Q1(which is the high threshold PORH), the high threshold PORH is:

VGS=PORH=VTP+2⁢VTNR⁢⁢1·K.(3)
From equation (3), it can be seen that the high threshold PORH is a function of the relationship between resistor R1and transistor Q1, namely the relative strength between resistor R1and transistor Q1. By relative strength, this refers to how “strong” or “weak” the transistor Q1and resistor R1are with respect to one another. For example, if resistor R1is large (i.e., up to 10's of MΩ), transistor Q1would be a correspondingly “weak” transistor (i.e., having a low aspect ratio relative to resistor R1) to achieve the desired high threshold PORH. As an example, if the resistor R1is on the order of 10's of MΩ, then the aspect ratio for transistor Q1would be in the neighborhood of 1/10 for a 0.5 μm process node. A “strong” transistor for this example might have an aspect ratio of 10/1. Typically, R1is on the order of 10's of MΩ to reduce power consumption, causing transistor Q1to have a low aspect ratio (i.e., about 1/10) in order to achieve the desired high threshold PORH. Also, transistor Q4of inverter102is usually set to be a “strong” transistor, while transistor Q3of inverter102is set to be a “weak” transistor (i.e., having a low aspect ratio relative to transistor Q4). Because the resistance of resistor R1can vary with process and temperature and because transistor Q1is usually a “weak” transistor (which is highly susceptible to process and temperature variation independent of the variations in resistor R1), the relative strength (and, thus, the threshold PORH) can vary substantially due to process variations. This means that, for the POR circuit100, the high threshold PORH is poorly controlled.

Once the voltage on rail VDD is greater than the high threshold PORH, transistor Q2is able to turn “on,” providing a hysteresis. The POR circuit100can then reassert the POR signal POROUT as the voltage on rail VDD begins to fall or ramp down during, for example, power down or a “brownout” event (i.e., at times T4and T10). The low threshold PORL is typically set by the characteristics of transistor Q2. Typically, transistor Q2is a “strong” transistor (i.e., having a high aspect ratio relative to resistor R1). For example, transistor Q2may have an aspect ratio of 10/1 for 0.5 μm process node when resistor R1is on the order of 10's of MΩ. As a result, the low threshold PORL is approximately equal to the threshold voltage VTPof transistor Q2. Additionally, there can be a threshold voltage mismatch between transistors Q1and Q2that can create an extra variation in the hysteresis voltage (which is generally the difference between the high threshold PORH and the low threshold PORL). As a result, the “brownout” performance may suffer due to the poor control of the hysteresis voltage.

Thus, there is a need for an improved POR circuit.

SUMMARY

An embodiment of the present invention, accordingly, provides an apparatus. The apparatus comprises a first voltage rail; a second voltage rail; a PMOS transistor that is coupled to the first voltage rail at its source; a drive circuit that is coupled to the drain of the PMOS transistor and that is configured to output a power on reset (POR) signal; a voltage divider that is coupled between the drain of the PMOS transistor and the second voltage rail; a switch network having: a first switch that is coupled between the gate of the PMOS transistor and the voltage divider; and a second switch that is coupled between the gate of the PMOS transistor and the voltage divider; and a controller that is coupled to control the first and second switches, wherein the first and second switches are complementary driven.

In accordance with an embodiment of the present invention, the drive circuit further comprises an inverter string.

In accordance with an embodiment of the present invention, the voltage divider further comprises a plurality of impedance elements coupled in series with one another between the drain of the PMOS transistor and the second voltage rail, and wherein the first switch is coupled to a first node within the voltage divider, and wherein the second switch is coupled to a second node within the voltage divider.

In accordance with an embodiment of the present invention, the plurality of impedance elements further comprises a plurality of resistors.

In accordance with an embodiment of the present invention, wherein the first switch further comprises a first NMOS transistor that is coupled to the first node of the voltage divider at its source and the gate of the first PMOS transistor at its drain, and wherein the second switch further comprises a second NMOS transistor that is coupled to the second node of the voltage divider at its source and the gate of the first PMOS transistor at its drain.

In accordance with an embodiment of the present invention, the controller further comprises: an output node of the inverter string that is coupled to apply the POR signal to the gate of the second NMOS transistor; and an internal node of the inverter string that is coupled to apply an inverse of the POR signal to the gate of the first NMOS transistor.

In accordance with an embodiment of the present invention, the controller further comprises a break-before-make circuit.

In accordance with an embodiment of the present invention, the controller further comprises: an output node of the inverter string that is coupled to apply the POR signal to the gate of the second NMOS transistor; and an inverter that is coupled to the output node and the gate of the first NMOS transistor.

In accordance with an embodiment of the present invention, the second node of the voltage divider is coupled to the second voltage rail.

DETAILED DESCRIPTION

Turning toFIG. 3, an example of a POR circuit200can be seen. In this example, high and low threshold voltages PORH and PORL are set by the characteristics of switch network204, the threshold voltage VTPof transistor Q1, the threshold voltage VTNof transistor Q4, and voltage divider202. The drain of transistor Q1is then able to provide a signal to the drive circuit208so as to generate the POR signal POROUT. In this example, an inverter string using inverters102and104is employed, but other configurations may be used as well (which can, for example, have fewer or more inverters or may employ one or more Schmitt triggers). A controller206then generates the controls signal(s) for the switch network204based at least in part on the POR signal POROUT.

InFIG. 4, a more detailed example of the POR circuit200(which is labeled200-1) can be seen. In this example, the voltage divider202-1is generally comprised of resistors R2and R3(other types of impedance elements, such as transistors operated in their linear region, can, however, be employed) coupled in series with one another between the drain of transistor Q1and rail VSS. The switch network204-1in this example is generally comprised of NMOS transistors Q5and Q6(which operate as switches) that are coupled to the gate of transistor Q1and to nodes within voltage divider202-1(which as shown in this example are the node between resistors R2and R3and the node coupled to rail VSS). These switches or transistors Q5and Q6, in this example, are also controlled by the inverter210(namely the input and output terminals or nodes of inverter210).

With POR circuit200-1and as the voltage on rail VDD is ramping up or rising (i.e., between times T1and T2ofFIG. 2) during, for example, power up or following a “brownout” event (i.e., between times T12and T13ofFIG. 2), the POR signal POROUT (which, again, is an active low signal) is initially logic low, meaning that transistor Q5is “off” and that transistor Q6is “on,”, coupling the gate of transistor Q1to the node between resistors R2and R3. For the example shown inFIG. 4, transistor Q1is deliberately chosen to be a “strong” transistor (i.e., high aspect ratio relative to divider202-1) to reduce the effects of process variation on the high threshold PORH. Once the voltage on rail VDD has ramped up to the high threshold PORH, the POR signal POROUT transitions from logic low to logic high. In contrast to the POR circuit100(where the threshold PORH is set by characteristics of transistors Q1and Q4and resistor R1), this high threshold PORH is set by the characteristics of transistors Q1and Q4and the voltage divider202-1. Looking first to transistor Q1, the POR circuit200-1is released when:
VD≧VTN,  (4)
where VDis the drain voltage of transistor Q1, where VTNis the threshold voltage of transistor Q4, and where it is assumed that transistor Q4is “stronger” than transistor Q3. For equation (4), this means that the gate voltage VGof transistor Q1is:

VG=VTN⁢R⁢⁢3R⁢⁢2+R⁢⁢3.(5)
Since the transistor Q1is “strong” relative to the resistors R2and R3, the gate-source voltage VGSto turn on transistor Q1is approximately equal to the threshold voltage VTPof transistor Q1, so the high threshold PORH is:

PORH=VTP+VTN⁢R⁢⁢3R⁢⁢2+R⁢⁢3.(6)
Thus, the high threshold PORH is now set by the threshold voltage of Q1/Q4and the resistor ratio, making it less susceptible to process variation compared to the POR circuit100.

As stated above, once the voltage on rail VDD reaches high threshold PORH (i.e., between times T2and T4), the POR circuit200-1is released. When the POR circuit200-1is released, transistor Q6is switched “off,” and transistor Q5is switched “on,” coupling the gate of transistor Q1to rail VSS. By coupling the gate of transistor Q1to rail VSS (which is usually coupled to ground), the low threshold PORL is the threshold voltage VTPof transistor Q1. So, as the voltage on rail VDD decreases or ramps down (i.e., between times T4to T5and T10to T11inFIG. 2) during, for example, power down or a “brownout” event, the POR circuit200-1is reasserted when the low threshold PORL is reached. Because transistor Q2is omitted, the threshold voltage mismatch can be eliminated, better controlling the hysteresis voltage.

Alternatively, the POR circuit200-2(as shown inFIG. 5), the low threshold PORL can be adjusted to a higher level. To accomplish this, voltage divider202-2is employed. As shown, there are multiple resistors R2to RN that are coupled in series with one another. The switches Q5and Q6can then be coupled to various nodes within the voltage divider202-2to achieve the desired thresholds. To preserve functionality of the POR circuit200-2, however, the voltage applied to the source of transistor Q6should be larger than the voltage applied to the source of transistor Q5.

The controller, too, may have multiple configurations. Controller206may also be configured to be nodes within drive circuit208(such as the output node of drive circuit208and the node between inverters102and104). Other configuration may also be employed where transistors Q5and Q6are driven by non-overlapping signals (such as a break-before-make logic circuit which can provide complementary signal).