Semiconductor packages including heat diffusion vias and interconnection vias

A semiconductor package includes a lower package including a lower semiconductor chip on a lower package substrate, an upper package on the lower package, and a heat interface material between the lower package and the upper package. The upper package includes an upper semiconductor chip on an upper package substrate including a center portion adjacent to the lower semiconductor chip and an edge portion. The heat interface material is in contact with a top surface of the lower semiconductor chip and the upper package substrate. The upper package substrate includes a heat diffusion via penetrating the center portion and an interconnection via penetrating the edge portion. The interconnection via is spaced apart from the heat diffusion via.

CROSS-REFERENCE TO RELATED APPLICATION

This U.S. non-provisional patent application claims priority under 35 U.S.C. §119 to Korean Patent Application No. 10-2013-0069754, filed on Jun. 18, 2013, in the Korean Intellectual Property Office, the disclosure of which is hereby incorporated by reference in its entirety.

BACKGROUND

The inventive concepts relate to semiconductor packages and, more particularly, to semiconductor packages that can provide improved heat exhaust characteristics.

As performance of electronic products has been improved, heat energies generated from devices used in electronic products have increased. In order to reduce heat generation problems of the devices, performance of the devices may be limited to control temperatures of the devices when the temperatures of the devices become equal or greater than a specific temperature. However, as generated heat energies increase, temperatures of the devices may rapidly increase such that performances of the devices may be reduced.

SUMMARY

Embodiments of the inventive concepts may provide semiconductor packages that can provide excellent heat exhaust efficiency.

The features of the inventive concept are not limited to the aforesaid, but other features not described herein will be clearly understood by those skilled in the art from descriptions below.

According to example embodiments of the inventive concepts, a semiconductor package may include a lower package including a lower semiconductor chip on a lower package substrate, an upper package on the lower package, the upper package including an upper semiconductor chip on an upper package substrate including a center portion adjacent to the lower semiconductor chip and an edge portion, and a heat interface material between the lower package and the upper package. The heat interface material contacts a top surface of the lower semiconductor chip and the upper package substrate. The upper package substrate may comprise a heat diffusion via penetrating the center portion of the upper package substrate, and an interconnection via penetrating the edge portion of the upper package substrate. The interconnection via may be spaced apart from the heat diffusion via.

In example embodiments, the lower package may further comprise a lower package molding layer exposing the heat interface material and extending on the lower semiconductor chip on the lower package substrate, and an electrical interconnection part penetrating the lower package molding layer on the lower package substrate, the electrical interconnection part contacting the interconnection via.

In example embodiments, the heat diffusion via may comprise a vertical heat diffusion via and a horizontal heat diffusion via. The vertical heat diffusion via penetrates the upper package substrate in a vertical direction to a bottom surface of the upper package substrate. The horizontal heat diffusion via may extend from a sidewall of the vertical heat diffusion via in a direction parallel to the bottom surface of the upper package substrate and further extend to penetrate a top surface of the upper package substrate.

In example embodiments, the vertical heat diffusion via may transfer heat generated from the lower semiconductor chip to the upper package substrate in the vertical direction, and the horizontal heat diffusion via may transfer the heat in the direction parallel to the bottom surface of the upper package substrate.

In example embodiments, the semiconductor package may further comprise a heat diffusion metal pad disposed between the bottom surface of the upper package substrate and a top surface of the heat interface material, and a heat exhaust pad disposed on the top surface of the upper package substrate. The heat exhaust pad may be in contact with the horizontal heat diffusion via.

In example embodiments, the heat diffusion via and the interconnection via may comprise a same metal material, the upper package substrate except the heat diffusion via and the interconnection via may comprise a porous insulation material having pores.

In example embodiments, the metal material may comprise aluminum (Al).

In example embodiments, the porous insulation material may comprise aluminum oxide (Al2O3), and the pores may contain therein a polymer material.

In example embodiments, the heat interface material may be spaced apart from an upper portion of the electrical interconnection part exposed by the lower package molding layer.

In example embodiments, the heat interface material may spaced apart from an upper portion of the electrical interconnection part exposed by the lower package molding layer.

In example embodiments, the heat interface material may be in contact with an upper portion of the electrical interconnection part exposed by the lower package molding layer.

According to example embodiments of the inventive concepts, a semiconductor package may include a lower package including a lower semiconductor chip on a lower package substrate, an upper package on the lower package, the upper package including an upper semiconductor chip on an upper package substrate including a center portion adjacent to the lower semiconductor chip and an edge portion, and a heat interface material between the lower package and the upper package, the heat interface material contacting a top surface of the lower semiconductor ship and the upper package substrate. First internal insulation patterns and second insulation patterns may be disposed within the center portion of the upper package substrate. The first internal insulation patterns may be in contact with a top surface of the upper package substrate and may be spaced part from each other. The second internal insulation patterns may be in contact with a bottom surface of the upper package substrate and correspond to the first internal insulation patterns, respectively.

In example embodiments, the upper package substrate may comprise horizontal heat diffusion vias and vertical heat diffusion vias. A respective one of the horizontal heat diffusion vias may be disposed between a respective one of the first internal insulation patterns and a respective one of the second internal insulation patterns. A respective one of the vertical heat diffusion vias may include a first vertical heat diffusion via disposed in the edge portion of the upper package substrate, and a second vertical heat diffusion via disposed between the horizontal heat diffusion vias in the center portion of the upper package substrate.

In example embodiments, a height of the vertical heat diffusion vias may be equal to a height of the upper package substrate.

In example embodiments, the horizontal heat diffusion vias and the vertical heat diffusion vias may comprise aluminum (Al).

In example embodiments, the first internal insulation patterns and the second internal insulation patterns may comprise a porous insulation material having pores, the porous insulation material may be aluminum oxide (Al2O3), and the pores may include therein a polymer material.

According to other example embodiments, a semiconductor package comprises a substrate having opposing faces, an edge portion and a center portion. A heat diffusion via extends to the opposing faces in the center portion, the heat diffusion via being electrically conductive but not configured to electrically connect to a semiconductor chip. An interconnection via extends to the opposing faces in the edge portion, the interconnection via being electrically conductive and configured to electrically connect to a semiconductor chip. A heat diffusion extension includes a buried portion that extends laterally from the heat diffusion via beneath the opposing faces and a penetrating portion that extends from the buried portion, remote from the heat diffusion via, to at least one of the opposing faces. The heat diffusion extension is electrically conductive but not configured to electrically connect to a semiconductor chip.

In example embodiments, the semiconductor package further comprises a semiconductor chip on the center portion of the substrate. The semiconductor chip is thermally connected but not electrically connected to the heat diffusion via and is electrically connected to the interconnection via. The penetrating portion of the heat diffusion extension is laterally offset from the semiconductor chip.

In example embodiments, the buried portion extends laterally from and at least partially surrounds the heat diffusion via and the penetrating portion extends from the buried portion and at least partially surrounds the heat diffusion via.

In example embodiments, the penetrating portion further extends away from the heat diffusion via beyond the interconnection via. In example embodiments, the penetrating portion extends to only one of the opposing faces that is adjacent the semiconductor chip.

DETAILED DESCRIPTION OF THE EMBODIMENTS

The inventive concepts will now be described more fully hereinafter with reference to the accompanying drawings, in which example embodiments of the inventive concepts are shown. Advantages and features of the inventive concepts and methods of achieving them will be apparent from the following example embodiments that will be described in more detail with reference to the accompanying drawings. It should be noted, however, that the inventive concepts are not limited to the following example embodiments, and may be implemented in various forms. Accordingly, the example embodiments are provided only to disclose the inventive concepts and let those skilled in the art know the category of the inventive concepts. In the drawings, embodiments of the inventive concepts are not limited to the specific examples provided herein and may be exaggerated for clarity.

Additionally, the embodiment in the detailed description will be described with sectional views as ideal example views of the inventive concepts. Accordingly, shapes of the example views may be modified according to manufacturing techniques and/or allowable errors. Therefore, the embodiments of the inventive concepts are not limited to the specific shape illustrated in the example views, but may include other shapes that may be created according to manufacturing processes. Areas exemplified in the drawings have general properties, and are used to illustrate specific shapes of elements. Thus, this should not be construed as limited to the scope of the inventive concepts.

FIG. 1is a cross-sectional view illustrating a semiconductor package according to a first embodiment of the inventive concepts.FIG. 2is a cross-sectional view illustrating a semiconductor package according to a second embodiment of the inventive concepts.FIG. 3is a cross-sectional view illustrating a semiconductor package according to a third embodiment of the inventive concepts.

Referring toFIG. 1, a semiconductor package1100includes a lower package100and an upper package300stacked on the lower package100. The semiconductor package1100is a package-on-package (POP) device.

The lower package100may include a lower package substrate11, a lower semiconductor chip23disposed on the lower package substrate11, and chip bumps21electrically connecting the lower package substrate11to the lower semiconductor chip23.

The lower package substrate11may be a multi-layered printed circuit board (PCB). Even though not shown in the drawings, the lower package substrate11may include a plurality of insulating layers (not shown) and internal wires (not shown) disposed between the insulating layers. Chip pads13may be provided on a top surface of the lower package substrate11, and external terminals15may be provided on a bottom surface of the lower package substrate11. The external terminals15may electrically connect the semiconductor package1100to an external device.

The lower semiconductor chip23is disposed on the chip pads13. The chip bumps21may be bonded to a bottom surface of the lower semiconductor chip23. The chip bumps21may be in contact with the chip pads13, so that the lower package substrate11may be electrically connected to the lower semiconductor chip23. For example, the lower semiconductor chip23may be a logic device (e.g., a micro-processor) or a memory device. Alternatively, a portion of the lower semiconductor chip23may be a memory device, and another portion of the lower semiconductor chip23may be a logic device and/or other device.

A lower package molding layer27may be disposed on the lower package substrate11having the semiconductor chip23. The lower package molding layer27may be on, and in some embodiments may cover, a sidewall of the lower semiconductor chip23and may completely fill a space between the chip bumps21. The lower package molding layer27may expose a top surface of the lower semiconductor chip23. One or more electrical interconnection parts25penetrating the lower package molding layer27may be disposed on the lower package substrate11. The electrical interconnection parts25may be disposed to be spaced apart from the lower semiconductor chip23at both sides of the lower semiconductor chip23. The electrical interconnection parts25may electrically connect the lower package substrate11to an upper package substrate31. A height of the electrical interconnection part25is higher than a height of the lower package molding layer27. Thus, an upper portion of the electrical interconnection part25may protrude from a top surface of the lower package molding layer27.

The upper package300includes the upper package substrate31, an upper semiconductor chip41disposed on the upper package substrate31, and bonding wires45electrically connecting the upper semiconductor chip41to the upper package substrate31.

The upper package substrate31includes a center portion A and an edge portion B. The upper package substrate31is on the electrical interconnection parts25. The upper package substrate31may include interconnection vias32and a heat diffusion via33. The interconnection vias32may penetrate a portion of the edge portion B of the upper package substrate31and may be disposed to face the electrical interconnection parts25. The heat diffusion via33may penetrate a portion of the center portion A of the upper package substrate31. The heat diffusion via33may be disposed to be adjacent to the lower semiconductor chip23. The heat diffusion via33may include a vertical heat diffusion via33aand a horizontal heat diffusion via33b. In some embodiments, the vertical heat diffusion via33amay penetrate the upper package substrate31in a vertical direction to a bottom surface of the upper package substrate31. The horizontal heat diffusion via33bmay extend from a sidewall of the vertical heat diffusion via33ain a parallel direction to the bottom surface of the upper package substrate31and may further extend to a top surface of the upper package substrate31. Alternatively, the upper package substrate31may not include the horizontal heat diffusion via33bin a semiconductor package1200ofFIG. 2according to a second embodiment of the inventive concepts.

Embodiments ofFIG. 1also describe a semiconductor package1100that comprises a substrate31having opposing faces, an edge portion B and a center portion A. A heat diffusion via33aextends to the opposing faces in the center portion A. The heat diffusion via33ais electrically conductive, but not configured to electrically connect to a semiconductor chip23or41. An interconnection via32extends to the opposing faces in the edge portion B. The interconnection via32is electrically conductive and is configured to electrically connect to a semiconductor chip23and/or41. A heat diffusion extension35includes a buried portion35athat extends laterally from the heat diffusion via33abeneath the opposing faces, and a penetrating portion35bthat extends from the buried portion35aremote from the heat diffusion via33a, to at least one of the opposing faces. The heat diffusion extension35is electrically conductive, but is not configured to electrically connect to a semiconductor chip.

Moreover,FIG. 1also illustrates various embodiments wherein a semiconductor chip41is provided on the center portion A of the substrate31. The semiconductor chip41is thermally connected but not electrically connected to the heat diffusion via33a, and is electrically connected to the interconnection via32. Moreover, the penetrating portion35bof the heat diffusion extension35is laterally offset from the semiconductor chip41.FIG. 1also illustrates various embodiments wherein the buried portion35aextends laterally from and at least partially surrounds the heat diffusion via33a, and the penetrating portion35bextends from the buried portion35aand at least partially surrounds the heat diffusion via33a. Finally,FIG. 1also illustrates various embodiments wherein the penetrating portion35bextends to only one of the opposing faces that is adjacent the semiconductor chip41.

The interconnection vias32and the heat diffusion via33may comprise a metal material. For example, the metal material may comprise aluminum (Al). The upper package substrate31except the interconnection via32and the heat diffusion via33may comprise a porous insulation material. In more detail, the porous insulation material may comprise aluminum oxide (Al2O3). The porous insulation material includes pores. A polymer material may be included in, and in some embodiments may fill, the pores.

One or more interconnection metal pads34aand a heat diffusion metal pad34bmay be disposed on the bottom surface of the upper package substrate31. The interconnection metal pad34amay be in contact with the interconnection via32, and the heat diffusion metal pad34bmay be in contact with the heat diffusion via33. The interconnection metal pad34amay be disposed between the electrical interconnection part25and the interconnection via32and may be in contact with the electrical interconnection part25. The interconnection and heat diffusion metal pads34aand34bmay include copper (Cu).

A separation space may exist between the top surface of the lower semiconductor chip23and the bottom surface of the upper package substrate31on which the interconnection and heat diffusion metal pads34aand34bare disposed. The separation space may contain, and in some embodiments may be filled with, a heat transfer layer29. In more detail, the heat transfer layer29may be disposed on the top surface of the lower semiconductor chip23and may be in contact with the heat diffusion metal pad34b. The heat transfer layer29may include a thermal interface material (TIM). A first solder resist layer36amay be conformally formed on the bottom surface of the upper package substrate31.

According to a third embodiment of the inventive concepts, the heat transfer layer29may completely fill a separation space between the lower package100and the upper package300in a semiconductor package1300illustrated inFIG. 3. In more detail, the heat transfer layer29may be disposed on the top surface of the lower semiconductor chip23and the lower package molding layer27exposing the top surface of the lower semiconductor chip23. The heat transfer layer29may be in contact with the electrical connection parts25protruding from the top surface of the lower package molding layer27.

Wire pads37and a heat exhaust pad39may be disposed on a top surface of the upper package substrate31. The wire pad37may be in contact with the interconnection via32, and the heat exhaust pad39may be in contact with the horizontal heat diffusion via33b. The wire and heat exhaust pads37and39may include copper (Cu).

The upper semiconductor chip41may be disposed on the upper package substrate31. In more detail, the upper semiconductor chip41may be disposed on the vertical heat diffusion via33a. For example, the upper semiconductor chip41may be a logic device (e.g., a micro-processor) or a memory device. Alternatively, a portion of the upper semiconductor chip41may be a memory device and another portion of the upper semiconductor chip41may be a logic device and/or another device. The upper semiconductor chip41may be joined to the upper package substrate31by a chip contact film43on a bottom surface of the upper semiconductor chip41.

Bonding pads47disposed on the upper semiconductor chip41may be electrically connected to the wire pads37through the bonding wires45. A second solder resist layer36bmay be further formed to conformally cover the wire and heat exhaust pads37and39on the top surface of the upper package substrate31. An upper package molding layer49may be disposed on the upper package substrate31on which the upper semiconductor chip41is mounted. The upper package molding layer49may be formed to extend on, and in some embodiments completely cover, the bonding wires45and the upper semiconductor chip41.

Heat generated from the lower semiconductor chip23is transferred to the upper package substrate31through the heat transfer layer29. A PCB used as a conventional upper package substrate may comprise bismaleimidetriazine (BT), and a heat conductivity of the bismaleimidetriazine (BT) is about 0.5 W/mK. Thus, heat generated from a lower semiconductor chip may not be easily exhausted to the outside such that the lower semiconductor chip may be damaged.

According to some embodiments of the inventive concepts, the heat diffusion via33is formed in the upper package substrate31so as to be adjacent to the lower semiconductor chip23. The heat diffusion via33includes the metal material so that a heat conductivity of the heat diffusion via33is excellent. For example, the heat diffusion via33includes aluminum (Al). A heat conductivity of the aluminum (Al) is about 210 W/mK. Thus, the heat generated from the lower semiconductor chip23may be smoothly exhausted through the heat diffusion via33. In more detail, the vertical heat diffusion via33aof the heat diffusion via33transfers the heat in a vertical direction from the lower semiconductor chip23to the upper package substrate31, and the horizontal heat diffusion via33bmay diffuse the heat in a horizontal direction. In other words, the horizontal heat diffusion via33bmay disperse a temperature distribution to prevent a hot spot which may occur in the upper package substrate31from being formed. Thus, a heat exhaust characteristic of the semiconductor package1100may be improved.

Additionally, since the interconnection via32of the upper package substrate31is a metal material, a coupling phenomenon between electrical signals may be improved.

FIG. 4is a cross-sectional view illustrating a semiconductor package according to a fourth embodiment of the inventive concepts. In the present embodiment illustrated inFIG. 4, for the purpose of ease and convenience in explanation, the same elements as described above will be indicated by the same reference numerals or the same reference designators and the descriptions to the same elements as described above will be omitted or mentioned briefly.

Referring toFIG. 4, a semiconductor package1400may include a pair of first internal insulation patterns51and a pair of second internal insulation patterns53which are disposed within the center portion A of the upper package substrate31. The pair of first internal insulation patterns51may be in contact with the top surface of the upper package substrate31and may be disposed to be spaced apart from each other. The pair of second internal insulation patterns53may be in contact with the bottom surface of the upper package substrate31and may be disposed to face the first internal insulation patterns51, respectively. The vertical heat diffusion via33aand horizontal heat diffusion vias33bmay be disposed within the center portion A of the upper package substrate31. In more detail, a respective one of the horizontal heat diffusion vias33bmay be disposed between a respective one of the first internal insulation patterns51and a respective one of the second internal insulation patterns53facing each other. The vertical heat diffusion via33amay be disposed between the horizontal heat diffusion vias33b. The first and second internal insulation patterns51and53may comprise the porous insulation material having the pores. The pores may include, and in some embodiments be filled with, the polymer material.

The semiconductor package1400may further include a vertical heat diffusion via33adisposed within the edge portion B of the upper package substrate31. The vertical heat diffusion via33awithin the edge portion B may be in contact with the heat exhaust pad39. As illustrated inFIG. 4, the horizontal heat diffusion via33bmay be connected to both the vertical heat diffusion via33awithin the center portion A and the vertical heat diffusion via33awithin the edge portion B. A height of the vertical heat diffusion via33amay be equal to a height of the upper package substrate31. One or more through-vias57may be disposed in the edge portion B of the upper package substrate31. The through-via57may penetrate the vertical heat diffusion via33ain the edge portion B. The through-via57may be in contact with the wire pad37and the interconnection metal pad34a. An insulating layer55may be disposed between the through-via53and the vertical heat diffusion via33ain the edge portion B. Accordingly,FIG. 4also illustrates embodiments wherein the penetrating portion35bfurther extends away from the heat diffusion via33abeyond the interconnection via57.

FIGS. 5A to 5Fare cross-sectional views illustrating a method of fabricating an upper package substrate according to some embodiments of the inventive concepts.

Referring toFIG. 5A, photoresist patterns3are formed on a top surface and a bottom surface of a substrate1. The substrate1may be an aluminum substrate.

FIG. 5Cis an enlarged view of a portion ‘A’ ofFIG. 5B. Referring toFIGS. 5B and 5C, the substrate1exposed by the photoresist patterns3is selectively oxidized. For example, the substrate1may be oxidized by an electrical chemical etching method. In more detail, the electrical chemical etching method may include placing the substrate1into an electrolytic solution, and applying a current to the substrate1. The electrolytic solution may be hydrochloric acid, sulfuric acid, phosphoric acid, chromic acid and/or oxalic acid. The current may be a direct current (DC) and/or an alternating current (AC). By the electrical chemical etching method, a region of the substrate1may be formed into a porous insulation material having pores4, as illustrated inFIG. 5C. The porous insulation material may comprise aluminum oxide (Al2O3).

Other regions of the substrate1protected by the photoresist patterns3may be formed into a vertical heat diffusion via33aand interconnection vias34. In detail, the vertical heat diffusion via33amay be formed in a center portion A of the substrate1, and the interconnection vias34may be formed in an edge portion B of the substrate1.

FIG. 5Eis an enlarged view of a portion ‘B’ ofFIG. 5D. Referring toFIGS. 5D and 5E, the photoresist patterns3are removed. The photoresist patterns3may be removed by performing an ashing process. The pores4may be filled with a polymer material6. The substrate1may be used as an upper package substrate31.

Referring toFIG. 5F, metal pads may be formed on a top surface and a bottom surface of the upper package substrate31. In more detail, wire pads37may be formed on the top surface of the upper package substrate31. The wire pads37may be in contact with the interconnection vias34. Interconnection metal pads34aand a heat diffusion metal pad34bmay be disposed on the bottom surface of the upper package substrate31. The interconnection metal pads34amay be in contact with the interconnection vias34, and the heat diffusion metal pad34bmay be in contact with the vertical heat diffusion via33a. The metal pads34aand34bmay include copper (Cu).

A first solder resist layer36ais formed on the bottom surface of the upper package substrate31. The first solder resist layer36amay be conformally formed on the bottom surface of the upper package substrate31to expose surfaces of the interconnection metal pads34aand the heat diffusion metal pad34b. A second solder resist layer36bis formed on the top surface of the upper package substrate31. The second solder resist layer36bmay be formed to expose a surface of the vertical heat diffusion via33aand to partially cover a surface of the wire pad37. An exposed portion of the surface of the wire pad37by the second solder resist layer36bmay be in contact with a bonding wire45in a subsequent process.

Referring toFIG. 2again, an upper semiconductor chip41is bonded to the top surface of the upper package substrate31. The upper semiconductor chip41may be bonded to be adjacent to the vertical heat diffusion via33a. The upper semiconductor chip41may be bonded by a chip contact film43. Bonding pads47may be formed on a top surface of the upper semiconductor chip41.

Bonding wires45may be used to connect the bonding pads47to the wire pads37. Thereafter, an upper package molding layer49may be used to cover the upper semiconductor chip41and the bonding wires45, thereby completing an upper package300. The electrical interconnection parts25of the lower package100may become in contact with the interconnection metal pads34adisposed on the bottom surface of the upper package substrate31. Thus, the upper package300may be stacked on the lower package100.

FIG. 6is a schematic block diagram illustrating an example of electronic systems including semiconductor package according to embodiments of the inventive concepts.FIG. 7is a schematic block diagram illustrating an example of memory systems including semiconductor packages according to embodiments of the inventive concepts.

Referring toFIG. 6, an electronic system2000may include a controller2100, an input/output (I/O) device2200, and a memory device2300. The controller2100, the I/O device2200, and the memory device2300may communicate with each other through a data bus2500. The data bus2500may correspond to a path through which data are transmitted. For example, the controller2100may include at least one of a microprocessor, a digital signal processor, a microcontroller and/or other logic devices having a similar function to any one of the microprocessor, the digital signal processor and the microcontroller. The controller2100, the I/O device2200, the memory device2300and/or the interface2400may include at least one of the semiconductor packages1100,1200,1300, and1400according to embodiments of the inventive concepts. The I/O device2200may include a keypad, a keyboard and/or a display device. The memory device2300stores data. For example, the memory device2300may store data and/or commands executed by the controller2100. The memory device2300may include a volatile memory device and/or a non-volatile memory device. In other embodiments, the memory device2300may include a flash memory device. For example, the flash memory device applied with technical features of the inventive concepts may be installed in an information processing system such as a mobile device or a desk top computer. The flash memory device of the memory device2300may be realized as a solid state disk (SSD). In this case, the electronic system200may stably store massive data in the memory device2300. The electronic system2000may further include an interface unit2400for transmitting electrical data to a communication network or for receiving electrical data from a communication network. The interface unit2400may operate by wireless or cable. For example, the interface unit2400may include an antenna for wireless communication or a transceiver for cable communication. Even though not shown in the drawings, the electronic system2000may further include an application chipset and/or a camera image processor (CIS).

The electronic system2000may be realized as a mobile system, a personal computer, an industrial computer and/or a logic system for performing various functions. For example, the mobile system may be one of a personal digital assistant (PDA), a portable computer, a web tablet, a mobile phone, a wireless phone, a laptop computer, a memory card, a digital music player, and/or an information transmitting/receiving system. If the electronic system2000performs wireless communication, the electronic system2000may be used in a communication interface protocol such as a third generation communication system (e.g., CDMA, GSM, NADC, E-TDMA, WCDAM, and/or CDMA2000).

Referring toFIG. 7, a memory card2400may include a non-volatile memory device2410and a memory controller2420. The non-volatile memory device2410and the memory controller2420may store data or read stored data. The non-volatile memory device2410, the memory controller2420and/or the host2430may include at least one of the semiconductor packages1100,1200,1300, and1400according to embodiments of the inventive concepts. The memory controller2420may read or write data from/into the non-volatile memory device2410in response to read/write request of a host2430.

According to embodiments of the inventive concepts, the semiconductor package includes the lower package and the upper package on the lower package. The upper package substrate on the lower package including the lower semiconductor chip includes the heat diffusion via. The heat diffusion via is disposed to be adjacent to the lower semiconductor chip. Thus, the heat generated from the lower semiconductor chip may be vertically and/or horizontally diffused through the heat diffusion vias to be exhausted. As a result, the heat exhaust characteristic of the semiconductor package may be improved.