Variable resistive memory device

A variable resistive memory device capable of reducing contact resistance by including a contact layer having low contact resistance, the variable resistive memory device including a substrate comprising an active region; a gate line on the substrate; a first contact layer electrically connected to the active region; a memory cell contact plug electrically connected to the first contact layer; and a variable resistive memory cell electrically connected to the memory cell contact plug, wherein the first contact layer has less contact resistance with respect to the active region than the memory cell contact plug.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims the benefit of Korean Patent Application No. 10-2012-0020401, filed on Feb. 28, 2012, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference.

BACKGROUND

Example embodiments of inventive concepts relate to semiconductor devices, and more particularly, to a variable resistive memory device.

A semiconductor product requires high-capacity data processing ability even while the volume is gradually decreased. There is demand to increase an operation speed and a degree of integration of a memory device used for the semiconductor product. As existing flash memory reaches the limit of scaling, non-volatile memory devices using a variable resistive material gain attention as a replacement memory.

SUMMARY

According to some example embodiments of inventive concepts, there is provided a variable resistive memory device comprising: a substrate comprising an active region; a gate line on the substrate; a first contact layer electrically connected to the active region; a memory cell contact plug electrically connected to the first contact layer; and a variable resistive memory cell electrically connected to the memory cell contact plug, wherein the first contact layer has less contact resistance with respect to the active region than the memory cell contact plug.

In some example embodiments of inventive concepts, the first contact layer may be buried in the substrate.

In some example embodiments of inventive concepts, a top surface of the first contact layer may be level with a top surface of the gate line.

In some example embodiments of inventive concepts, a bottom surface of the first contact layer may be level with the top surface of the gate line.

In some example embodiments of inventive concepts, the first contact layer may be between the gate lines.

In some example embodiments of inventive concepts, the first contact layer may be on an area between the gate lines.

In some example embodiments of inventive concepts, the first contact layer may include a metal silicide material.

In some example embodiments of inventive concepts, the variable resistive memory device may further include: a second contact layer electrically connected to the active region; a source line contact plug electrically connected to the second contact layer; and a source line electrically connected to the source line contact plug, wherein the second contact layer has less contact resistance with respect to the active region than the source line contact plug.

In some example embodiments of inventive concepts, the second contact layer may be buried in the substrate.

In some example embodiments of inventive concepts, the first contact layer and the second contact layer may include the same material.

In some example embodiments of inventive concepts, the gate line may be buried in the substrate.

In some example embodiments of inventive concepts, the gate line may be on the substrate.

In some example embodiments of inventive concepts, the first contact layer may include at least one of titanium (Ti), cobalt (Co), nickel (Ni), tantalum (Ta), platinum (Pt), vanadium (V), erbium (Er), zirconium (Zr), hafnium (Hf), molybdenum (Mo), and ytterbium (Yb).

In some example embodiments of inventive concepts, the second contact layer may include at least one of titanium (Ti), cobalt (Co), nickel (Ni), tantalum (Ta), platinum (Pt), vanadium (V), erbium (Er), zirconium (Zr), hafnium (Hf), molybdenum (Mo), and ytterbium (Yb).

According to other example embodiments of inventive concepts, there is provided a variable resistive memory device comprising: a substrate; a contact plug on the substrate; and a contact layer interposed between the substrate and the contact plug and having less contact resistance with respect to the substrate than the contact plug.

DETAILED DESCRIPTION OF EXAMPLE EMBODIMENTS

Reference will now be made in detail to example embodiments, examples of which are illustrated in the accompanying drawings. However, example embodiments are not limited to the example embodiments illustrated hereinafter, and the example embodiments herein are rather introduced to provide easy and complete understanding of the scope and spirit of example embodiments. In the drawings, the thicknesses of layers and regions are exaggerated for clarity.

It will be understood that when an element, such as a layer, a region, or a substrate, is referred to as being “on,” “connected to” or “coupled to” another element, it may be directly on, connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being “directly on,” “directly connected to” or “directly coupled to” another element or layer, there are no intervening elements or layers present. Like reference numerals refer to like elements throughout. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items. Expressions such as “at least one of,” when preceding a list of elements, modify the entire list of elements and do not modify the individual elements of the list.

Example embodiments are described herein with reference to cross-sectional illustrations that are schematic illustrations of example embodiments (and intermediate structures). As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, example embodiments should not be construed as limited to the particular shapes of regions illustrated herein but may be to include deviations in shapes that result, for example, from manufacturing. For example, an implanted region illustrated as a rectangle may, typically, have rounded or curved features and/or a gradient of implant concentration at its edges rather than a binary change from implanted to non-implanted region. Likewise, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation takes place. Thus, the regions illustrated in the figures are schematic in nature and their shapes may be not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of example embodiments.

A magnetic random access memory (MRAM) will now be illustrated as a variable resistive memory. However, example embodiments of inventive concepts are not limited thereto, and the variable resistive memory may be a phase change RAM (PCRAM), a resistive RAM (RRAM), or the like.

FIG. 1is a circuit diagram of a variable resistive memory array100according to some example embodiments of inventive concepts.

Referring toFIG. 1, the variable resistive memory array100may include a plurality of unit cells U of a plurality of variable resistive memory devices arranged in a matrix form. Each of the unit cells U of the variable resistive memory device may include an access portion C and a memory portion M. Each of the unit cells U of the variable resistive memory device may be electrically connected to a word line WL and a bit line BL. When the access portion C is a transistor as illustrated inFIG. 1, the unit cell U of the variable resistive memory device may further include a source line SL that is electrically connected to a source region of the access portion C. The word line WL and the bit line BL may be arranged at a certain angle, for example, at a right angle, in two dimensions. Furthermore, the word line WL and the bit line BL may be arranged at a certain angle or arranged to be parallel to each other. The source line SL may be a common source line for the unit cells U of the variable resistive memory device.

The access portion C may control supply of current to the memory portion M according to a voltage of the word line WL. The access portion C may be a MOS transistor, a bipolar transistor, or a diode.

The memory portion M may include a variable resistive material, for example, a magnetic material, or a magnetic tunnel junction (MTJ). The memory portion M may perform a memory function by using a resistance variation due to a spin transfer torque (STT) phenomenon in which a magnetization direction of a magnetic body is changed according to an input current.

FIG. 2is a top view of the variable resistive memory array100, according to some example embodiments of inventive concepts.FIG. 2shows a region II ofFIG. 1.

Referring toFIG. 2, the variable resistive memory array100may include a bit line BL extending in a first direction and a source line SL and a gate line GL extending in a second direction that forms a predetermined angle with the first direction. The predetermined angle may be a right angle or any other angle. The first direction may be an x direction, for example, and the second direction may be a y direction, for example.

The source line SL may be in the center and may overlap at least a part of the bit line BL. However, the source line SL does not physically contact the bit line BL. In an area where the source line SL overlaps the bit line BL, there may be a source line contact plug SP that electrically connects a substrate10(seeFIG. 3) to the source line SL. The position of the source line contact plug SP is not limited thereto, and only a part of the source line contact plug SP may overlap the bit line BL or the source line SL may not overlap the bit line BL.

Gate lines GL may be on both sides of the source line SL, respectively. A variable resistive memory cell MC may be on a side of the gate line GL that is opposite to the source line SL. The variable resistive memory cell MC may overlap the bit line BL. The position of the variable resistive memory cell MC is not limited thereto, and only a part of the variable resistive memory cell MC may overlap the bit line BL or the variable resistive memory cell MC may not overlap the bit line BL. The variable resistive memory cell MC may overlap a memory cell contact plug MP located below the variable resistive memory cell MC.

The variable resistive memory cell MC is electrically connected to the bit line BL. The source line SL does not physically contact the gate line GL. A memory cell contact plug MP may be below the variable resistive memory cell MC. The source line SL may be a common source line that is shared by variable resistive memory cells MC on both sides of the source line SL.

The gate lines GL may correspond to the word lines WL ofFIG. 1, and the variable resistive memory cells MC may correspond to the memory portions M ofFIG. 1. An insulation layer ISO formed of an insulation material may be located between two adjacent gate lines GL.

FIG. 3is a cross-sectional view of a variable resistive memory device1taken along line III-III ofFIG. 2, according to some example embodiments of inventive concepts.

Referring toFIG. 3, the variable resistive memory device1may include a substrate10, a gate line GL, a variable resistive memory cell60, a source line SL, and a bit line BL. The variable resistive memory cell60may correspond to the variable resistive memory cell MC ofFIG. 2.

The gate line GL may be electrically connected to the variable resistive memory cell60, and the gate line GL may be electrically connected to the source line SL.

The variable resistive memory device1may further include a source line contact plug SP electrically connecting the source line SL to an active region11of the substrate10, and a memory cell contact plug MP electrically connecting the variable resistive memory cell60to the active region11of the substrate10.

The variable resistive memory device1may further include a first contact layer30. The first contact layer30may be between the memory cell contact plug MP and the active region11of the substrate10, and may have less contact resistance with respect to the active region11of the substrate10than the memory cell contact plug MP.

The variable resistive memory device1may further include a second contact layer32. The second contact layer32may be between the source line contact plug SP and the active region11of the substrate10, and may have less contact resistance with respect to the active region11of the substrate10than the source line contact plug SP.

The substrate10may include a semiconductor layer including silicon (Si), silicon-germanium (SiGe), and/or silicon carbide (SiC). Also, the substrate10may include an epitaxial layer, a silicon-on-insulator (SOI) layer, and/or a semiconductor-on-insulator (SEOI) layer. Also, although it is not illustrated, the substrate10may further include a conductive line such as word line or a bit line or other semiconductor devices. The substrate10may further include a conductive layer including titanium (Ti), titanium nitride (TiN), aluminum (Al), tantalum (Ta), tantalum nitride (TaN), and/or tantalum aluminum nitride (TaAlN), or a dielectric layer including silicon oxide, titanium oxide, aluminum oxide, zirconium oxide, or hafnium oxide.

The substrate10may include an isolation layer12for defining the active region11. The isolation layer12may be formed using a typical shallow trench isolation (STI) method. The active region11may include impurities, and thus may function as a source region and a drain region. The active region11may provide a channel region of the gate line GL.

The gate line GL may be buried in a trench16formed in the substrate10. According to an example embodiment, the gate line GL may constitute a buried transistor. The gate line GL may include a gate insulation layer21formed on the bottom and side walls of the trench16, a gate electrode layer22formed in the gate insulation layer21, and a capping layer23formed on the gate electrode layer22. The active region11may contact the bottom and side walls of the gate line GL. The gate electrode layer22may be the word line WL ofFIG. 1. The gate line GL and source and drain regions (not shown) may constitute a MOS transistor to function as an access device. The source and drain regions may be formed in a part of the active region11located between adjacent gate lines GL. Alternatively, the first contact layer30and/or the second contact layer32may function as the source and drain regions.

The first contact layer30and the second contact layer32may be outside of the gate line GL. The first contact layer30and the second contact layer32may be buried in the substrate10. For example, top surfaces of the first contact layer30and the second contact layer32may be level with a top surface of the capping layer23of the gate line GL or may have a height lower than the top surface of the capping layer23. Here, “height” denotes a distance from the substrate10.

The first contact layer30may be electrically connected to the active region11of the substrate10. The first contact layer30may have less contact resistance with respect to the active region11of the substrate10than the memory cell contact plug MP. The second contact layer32may be electrically connected to the active region11of the substrate10. The second contact layer32may have less contact resistance with respect to the active region11of the substrate10than the source line contact plug SP. The first contact layer30and the second contact layer32may include a silicide material, for example, metal silicide. The metal may include one of titanium (Ti), cobalt (Co), nickel (Ni), tantalum (Ta), platinum (Pt), vanadium (V), erbium (Er), zirconium (Zr), hafnium (Hf), molybdenum (Mo), and ytterbium (Yb). The first contact layer30and the second contact layer32may include the same material or different materials.

A first interlayer insulation layer40and a second interlayer insulation layer42may be sequentially on the gate line GL. The first and second interlayer insulation layers40and42may include oxide, nitride, and oxynitride, for example, at least one of silicon oxide, silicon nitride, and silicon oxynitride. The first and second interlayer insulation layers40and42may include the same material or different materials. The first and second interlayer insulation layers40and42may be formed by using a method such as sputtering, chemical vapor deposition (CVD), plasma enhanced CVD (PECVD), or atomic layer deposition (ALD). The first and second interlayer insulation layers40and42may be planarized by performing a planarization process using a chemical mechanical polishing (CMP) method or a dry etch method.

InFIG. 3, although the first and second interlayer insulation layers40and42are illustrated to be separated from each other, example embodiments of the inventive concepts are not limited thereto. For example, the first and second interlayer insulation layers40and42may be one layer.

The first and second interlayer insulation layers40and42may expose the first contact layer30. The first interlayer insulation layers40may expose the second contact layer32. The memory cell contact plug MP may be on the exposed first contact layer30. The source line contact plug SP may be on the exposed second contact layer32.

The memory cell contact plug MP and the source line contact plug SP may include, for example, at least one of titanium (Ti), titanium nitride (TiN), tungsten (W), and tungsten nitride (WN), or a stacked structure of the above materials. The memory cell contact plug MP and the source line contact plug SP may be formed by using a method such as sputtering, CVD, PECVD, or ALD. The memory cell contact plug MP and the source line contact plug SP may be formed by forming contact holes by using a typical photolithography method and/or an etch method, filling the contact holes with a conductive material, and performing a planarization process using a CMP method or a dry etch method.

The source line SL may be on the first interlayer insulation layer40and electrically connected to the source line contact plug SP. Accordingly, the active region11of the substrate10and the source line SL may be electrically connected to each other via the second contact layer32and the source line contact plug SP. The source line SL may include a conductive material, for example, metal such as aluminum (Al), copper (Cu), tungsten (W), titanium (Ti), or tantalum (Ta), or an alloy such as titanium tungsten (TiW) or titanium aluminum (TiAl), or carbon (C). The source line SL may include titanium nitride (TiN), titanium aluminum nitride (TiAlN), tantalum nitride (TaN), tungsten nitride (WN), molybdenum nitride (MoN), niobium nitride (NbN), titanium silicon nitride (TiSiN), titanium boron nitride (TiBN), zirconium silicon nitride (ZrSiN), tungsten silicon nitride (WSiN), tungsten boron nitride (WBN), zirconium aluminum nitride (ZrAlN), molybdenum aluminum nitride (MoAlN), tantalum silicon nitride (TaSiN), tantalum aluminum nitride (TaAlN), titanium oxynitride (TiON), titanium aluminum oxynitride (TiAlON), tungsten oxynitride (WON), tantalum oxynitride (TaON), titanium carbonitride (TiCN), or tantalum carbonitride (TaCN). Also, the source line SL may have a stacked structure of the above-described materials.

The memory cell contact plug MP may be within the first and second interlayer insulation layers40and42and electrically connected to the first contact layer30. The variable resistive memory cell60may be on the memory cell contact plug MP. Accordingly, the active region11of the substrate10and the variable resistive memory cell60may be electrically connected to each other via the first contact layer30and the memory cell contact plug MP.

The variable resistive memory cell60may perform a memory function by using a resistance variation such as magnetoresistance by an electrical signal due to the gate line GL.

The variable resistive memory cell60may include a lower electrode61, a lower magnetic layer62, an upper magnetic layer64, a tunnel barrier layer66, and an upper electrode68. The lower magnetic layer62, the upper magnetic layer64, and the tunnel barrier layer66may be interposed between the lower and upper electrodes61and68. The lower magnetic layer62, the upper magnetic layer64, and the tunnel barrier layer66may constitute a magnetic tunnel junction (MTJ) or a spin valve. For example, when the tunnel barrier layer66is insulative, the lower magnetic layer62, the upper magnetic layer64, and the tunnel barrier layer66may constitute an MTJ. For example, when the tunnel barrier layer66is conductive, the lower magnetic layer62, the upper magnetic layer64, and the tunnel barrier layer66may constitute a spin valve.

The lower electrode61may be on the second interlayer insulation layer42and electrically connected to the memory cell contact plug MP. The lower electrode61may be formed using a typical etch method, a damascene method, or a dual damascene method. The lower electrode61may include a metal such as aluminum (Al), copper (Cu), tungsten (W), titanium (Ti), or tantalum (Ta), or an alloy such as titanium tungsten (TiW) or titanium aluminum (TiAl), or carbon (C). The lower electrode61may include titanium nitride (TiN), titanium aluminum nitride (TiAlN), tantalum nitride (TaN), tungsten nitride (WN), molybdenum nitride (MoN), niobium nitride (NbN), titanium silicon nitride (TiSiN), titanium boron nitride (TiBN), zirconium silicon nitride (ZrSiN), tungsten silicon nitride (WSiN), tungsten boron nitride (WBN), zirconium aluminum nitride (ZrAlN), molybdenum aluminum nitride (MoAlN), tantalum silicon nitride (TaSiN), tantalum aluminum nitride (TaAlN), titanium oxynitride (TiON), titanium aluminum oxynitride (TiAlON), tungsten oxynitride (WON), tantalum oxynitride (TaON), titanium carbonitride (TiCN), or tantalum carbonitride (TaCN). Also, the lower electrode61may have a stacked structure of the above-described materials.

The lower magnetic layer62, the tunnel barrier layer66, and the upper magnetic layer64may be sequentially stacked on the lower electrode61. The lower electrode61may be electrically connected to the lower magnetic layer62. The tunnel barrier layer66may be interposed between the upper and lower magnetic layers62and64. The lower magnetic layer62, the upper magnetic layer64, and the tunnel barrier layer66may constitute an MTJ or a spin valve. For example, when the tunnel barrier layer66is insulative, the lower magnetic layer62, the upper magnetic layer64, and the tunnel barrier layer66may constitute an MTJ. For example, when the tunnel barrier layer66is conductive, the lower magnetic layer62, the upper magnetic layer64, and the tunnel barrier layer66may constitute a spin valve.

The lower magnetic layer62and the upper magnetic layer64each may have a perpendicular magnetization direction. For example, the perpendicular magnetization direction may be perpendicular to the surface of the substrate10. A memory operating method of the variable resistive memory cell60using the perpendicular magnetization direction is described below with reference toFIGS. 4 to 7. However, example embodiments of inventive concepts are not limited thereto and a case in which the lower and upper magnetic layer62and64each have a horizontal magnetization direction is included in the technical scope of example embodiments of the inventive concepts.

The tunnel barrier layer66performs a function to change the magnetization direction of the lower magnetic layer62or the upper magnetic layer64as electrons tunnel through the tunnel barrier layer66. Thus, the tunnel barrier layer66may have a thin thickness so that electrons may tunnel. The tunnel barrier layer66may be insulative and include, for example, oxide, nitride, or oxynitride. The tunnel barrier layer66may include, for example, at least one of magnesium oxide, magnesium nitride, magnesium oxynitride, silicon oxide, silicon nitride, silicon oxynitride, silicon carbonate, aluminum oxide, aluminum nitride, aluminum oxynitride, calcium oxide, nickel oxide, hafnium oxide, tantalum oxide, zirconium oxide, and manganese oxide. Also, the tunnel barrier layer66may be conductive and include, for example, non-magnetic transition metal, and for example, at least one of copper (Cu), gold (Au), tantalum (Ta), silver (Ag), copper-platinum (CuPt), and copper-manganese (CuMn).

The upper electrode68may be on the upper magnetic layer64and may be electrically connected to the upper magnetic layer64. The upper electrode68may include a metal such as aluminum (Al), copper (Cu), tungsten (W), titanium (Ti), or tantalum (Ta), or an alloy such as titanium tungsten (TiW) or titanium aluminum (TiAl), or carbon (C). The upper electrode68may include titanium nitride (TiN), titanium aluminum nitride (TiAlN), tantalum nitride (TaN), tungsten nitride (WN), molybdenum nitride (MoN), niobium nitride (NbN), titanium silicon nitride (TiSiN), titanium boron nitride (TiBN), zirconium silicon nitride (ZrSiN), tungsten silicon nitride (WSiN), tungsten boron nitride (WBN), zirconium aluminum nitride (ZrAlN), molybdenum aluminum nitride (MoAlN), tantalum silicon nitride (TaSiN), tantalum aluminum nitride (TaAlN), titanium oxynitride (TiON), titanium aluminum oxynitride (TiAlON), tungsten oxynitride (WON), tantalum oxynitride (TaON), titanium carbonitride (TiCN), or tantalum carbonitride (TaCN). Also, the upper electrode68may have a stacked structure of the above-described materials. The lower electrode61and the upper electrode68may be formed of the same material or different materials. The source line SL may be formed of the same material as or a different material than the lower electrode61and/or the upper electrode68.

As described above, when the first and second interlayer insulation layers40and42are one layer, the source line SL and the lower electrode61may be not have a step. For example, the source line SL and the lower electrode61may be on the same interlayer insulation layer.

A bit line contact plug70may be on the upper electrode68and may be electrically connected to the upper electrode68. The bit line contact plug70may include, for example, at least one of titanium (Ti), titanium nitride (TiN), tungsten (W), and tungsten nitride (WN), or a stacked structure of the above materials.

The variable resistive memory cell60and the bit line contact plug70may be surrounded by a third interlayer insulation layer80. The third interlayer insulation layer80may include oxide, nitride, and oxynitride, for example, at least one of silicon oxide, silicon nitride, and silicon oxynitride.

The bit line BL may be on the bit line contact plug70. The bit line contact plug70may be electrically connected to the bit line BL.

FIGS. 4 to 7are views for explaining a method of storing data using a magnetization direction of the variable resistive memory cell60ofFIG. 3. InFIGS. 4 to 7, the lower electrode61and the upper electrode68are not illustrated.

Referring toFIG. 3, when the gate line GL is turned on, the source line SL and the bit line BL are electrically connected to each other via the variable resistive memory cell60. When the direction of current flowing in the variable resistive memory cell60is changed, a magnetoresistance value of at least one of the lower magnetic layer62and the upper magnetic layer64included in the variable resistive memory cell60changes, and thus the magnetic memory layer60may store data “0” or “1”. For example, as the magnetization directions of the lower and upper magnetic layers62and64are parallel or anti-parallel to each other, data may be stored.

InFIGS. 4 and 5, it is assumed that the lower magnetic layer62is a pinned layer in which the magnetization direction is pinned and the upper magnetic layer64is a free layer in which the magnetization direction is changed. It is also assumed that the magnetization direction of the lower magnetic layer62is pinned in an upward direction. Although it is not illustrated, a pinning layer for pinning the magnetization direction of the pinned layer may be further provided above or under the pinned layer and the pinning layer may include an anti-ferromagnetic material.

Referring toFIGS. 3 and 4, when the gate line GL is turned on and current flows from the source line SL to the bit line BL, the magnetization tends to be in the upward direction along a magnetization easy axis. Accordingly, the lower and upper magnetic layers62and64have an upward, parallel magnetization direction, which indicates a low resistance state. Data “0” may be stored in the low resistance state.

Referring toFIGS. 3 and 5, when the gate line GL is turned on and current flows from the bit line BL to the source line SL, the magnetization tends to be in the downward direction contrary to the magnetization easy axis. Since the upper magnetic layer64is a free layer, the magnetization direction is changed to the downward direction. However, the lower magnetic layer62that is a pinned layer has the upward magnetization direction without change. Accordingly, the lower and upper magnetic layers62and64have an anti-parallel magnetization direction, which indicates a high resistance state. Data “1” may be stored in the high resistance state.

In the meantime, when the magnetization direction of the lower magnetic layer62is pinned in the downward direction, data may be stored in the opposite manner. For example, when current flows from the source line SL to the bit line BL, data “1” may be stored and, when current flows from the bit line BL to the source line SL, data “0” may be stored.

InFIGS. 6 and 7, it is assumed that the lower magnetic layer62is a free layer in which the magnetization direction is changed and the upper magnetic layer64is a pinned layer in which the magnetization direction is pinned. It is also assumed that the magnetization direction of the upper magnetic layer64is pinned in a downward direction.

Referring toFIGS. 3 and 6, when the gate line GL is turned on and current flows from the source line SL to the bit line BL, the magnetization tends to be in the upward direction along a magnetization easy axis. Since the lower magnetic layer62is a free layer, the magnetization direction is changed to the upward direction. However, the upper magnetic layer64that is a pinned layer has the downward magnetization direction without change. Accordingly, the lower and upper magnetic layers62and64have an anti-parallel magnetization direction, which indicates a high resistance state. Data “1” may be stored in the high resistance state.

Referring toFIGS. 3 and 7, when the gate line GL is turned on and current flows from the bit line BL to the source line SL, the magnetization tends to be in the downward direction contrary to the magnetization easy axis. Accordingly, the lower and upper magnetic layers62and64have a downward, parallel magnetization direction, which indicates a low resistance state. Data “0” may be stored in the low resistance state.

If the magnetization direction of the upper magnetic layer64is pinned in the upward direction, data may be stored in the opposite manner. For example, when current flows from the source line SL to the bit line BL, data “0” may be stored and, when current flows from the bit line BL to the source line SL, data “1” may be stored.

As illustrated inFIGS. 4 to 7, when the lower and upper magnetic layers62and64store data according to the magnetization direction, a value of the current flowing in the variable resistive memory cell60is changed. The stored data may be read out by sensing a difference in the current value.

AlthoughFIGS. 4 to 7illustrate a case in which the lower and upper magnetic layers62and64each have a perpendicular magnetization direction, this is an example and a case in which the lower and upper magnetic layers62and64each have a horizontal magnetization direction is included in the technical scope of example embodiments of inventive concepts.

FIGS. 8 to 13are cross-sectional views illustrating a method of manufacturing the variable resistive semiconductor device1ofFIG. 3, according to some example embodiments of inventive concepts.FIGS. 8 to 13illustrate cross-sections taken along line III-III ofFIG. 2and cross-sections taken along line IV-IV ofFIG. 2.

Referring toFIG. 8, a substrate10is provided. Isolation layers12for defining the active region11are formed within the substrate10. Gate lines GL each including an insulation layer21, a gate electrode layer22, and a capping layer23are formed between the isolation layers12of the substrate10. Although the gate lines GL constitute buried transistors in the present example embodiment, this is only an example, and the gate lines GL may constitute planar transistors.

Referring toFIG. 9, openings OP1are formed in the substrate10by recessing portions of the substrate10between the gate lines GL. The openings OP1may be formed by lithography or etch back.

Referring toFIG. 10, a sacrificial layer39is formed on the gate lines GL. The sacrificial layer39may fill the openings OP1. The sacrificial layer39may include a conductive material, for example, metal. The sacrificial layer39may include one of titanium (Ti), cobalt (Co), nickel (Ni), tantalum (Ta), platinum (Pt), vanadium (V), erbium (Er), zirconium (Zr), hafnium (Hf), molybdenum (Mo), and ytterbium (Yb). The sacrificial layer39may be formed by using a method such as sputtering, CVD, PECVD, or ALD.

Referring toFIG. 11, the first and second contact layers30and32are formed by thermally treating the sacrificial layer39. The first contact layer30and the second contact layer32may be between the gate lines GL. The first contact layer30and the second contact layer32may be formed by a reaction between the materials of the sacrificial layer39and the substrate10, and may include, for example, a silicide material. In other words, the first contact layer30and the second contact layer32may include a metal silicide material formed by a reaction of the metal material of the sacrificial layer39with the silicon material of the substrate10. The first contact layer30and the second contact layer32may be formed in the same process or different processes.

Referring toFIG. 12, the first and second contact layers30and32are exposed by removing the sacrificial layer39. The removing process may be performed using a planarization process such as CMP or etchback. The first contact layer30and the second contact layer32may be buried in the substrate10. For example, top surfaces of the first contact layer30and the second contact layer32may be level with top surfaces of the capping layers23of the gate lines GL or may have a height lower than the top surfaces of the capping layers23.

A metal silicide material forming the first contact layer30and the second contact layer32may be deposited to be higher than the gate lines GL by the thermal treatment ofFIG. 11. However, the metal silicide material forming the first contact layer30and the second contact layer32may be deposited to be level with or lower than the gate lines GL by the planarization process ofFIG. 12.

Referring toFIG. 13, the memory cell contact plug MP formed on the first contact layer30is electrically connected to the first contact layer30. The source line contact plug SP formed on the second contact layer32is electrically connected to the second contact layer32. The memory cell contact plug MP may be surrounded by the first and second interlayer insulation layers40and42. The source line contact plug SP may be surrounded by the first interlayer insulation layer40.

The variable resistive memory cell60, the source line SL, and the bit line BL are formed to complete the variable resistive memory device1ofFIG. 3.

FIG. 14is a cross-sectional view of a variable resistive memory device2according to some example embodiments of inventive concepts. The variable resistive memory device2according to the present example embodiments is a modification of the variable resistive memory device1described above with reference toFIGS. 2 to 13, so a description of duplicate matters will be omitted.

Referring toFIG. 14, the variable resistive memory device2may include a substrate10, a gate line GL, a variable resistive memory cell60, a source line SL, and a bit line BL.

The variable resistive memory device2may further include a source line contact plug SP electrically connecting the source line SL to an active region11of the substrate10, and a memory cell contact plug MP electrically connecting the variable resistive memory cell60to the active region11of the substrate10.

The variable resistive memory device2may further include a first contact layer30abetween the source line contact plug SP and the active region11of the substrate10that has less contact resistance with respect to the active region11of the substrate10than the source line contact plug SP. The variable resistive memory device2may further include a second contact layer32abetween the memory cell contact plug MP and the active region11of the substrate10that has less contact resistance with respect to the active region11of the substrate10than the memory cell contact plug MP.

The gate line GL may be on the active region11of the substrate10. According to an example embodiment, the gate line GL may constitute a buried transistor. The gate line GL may include an insulation layer21, a gate electrode layer22, and a capping layer23. The gate electrode layer22may correspond to the word line WL ofFIG. 1. The gate line GL and source and drain regions (not shown) may constitute a MOS transistor to function as an access device.

The first contact layer30aand the second contact layer32amay be outside the gate line GL. The first contact layer30aand the second contact layer32amay be within an auxiliary insulation layer44. A first interlayer insulation layer40and a second interlayer insulation layer42may be on the auxiliary insulation layer44.

Top surfaces of the first contact layer30aand the second contact layer32amay have a height higher than the top surface of the capping layer23of the gate line GL. The top surfaces of the first contact layer30aand the second contact layer32amay be level with the top surface of the capping layer23of the gate line GL or may have a height lower than the top surface of the capping layer23.

The first contact layer30amay have less contact resistance with respect to the active region11of the substrate10than the memory cell contact plug MP. The second contact layer32amay have less contact resistance with respect to the active region11of the substrate10than the source line contact plug SP. The first contact layer30aand the second contact layer32amay include a silicide material, for example, metal silicide. The metal may include one of titanium (Ti), cobalt (Co), nickel (Ni), tantalum (Ta), platinum (Pt), vanadium (V), erbium (Er), zirconium (Zr), hafnium (Hf), molybdenum (Mo), and ytterbium (Yb). The first contact layer30aand the second contact layer32amay include the same material or different materials.

The memory cell contact plug MP may be on the first contact layer30aexposed through the first and second interlayer insulation layers40and42. The source line contact plug SP may be on the second contact layer32aexposed through the first interlayer insulation layer40.

The source line SL may be on the first interlayer insulation layer40to be electrically connected to the source line contact plug SP. Accordingly, the active region11of the substrate10and the source line SL may be electrically connected to each other via the second contact layer32aand the source line contact plug SP.

The memory cell contact plug MP, which is electrically connected to the first contact layer30a, may be within the first and second interlayer insulation layers40and42. The variable resistive memory cell60may be on the memory cell contact plug MP. Accordingly, the active region11of the substrate10and the variable resistive memory cell60may be electrically connected to each other via the first contact layer30aand the memory cell contact plug MP.

FIGS. 15 to 20are cross-sectional views illustrating a method of manufacturing the variable resistive semiconductor device2ofFIG. 14, according to some example embodiments of inventive concepts.FIGS. 15 to 20illustrate cross-sections taken along line III-III ofFIG. 2and cross-sections taken along line IV-IV ofFIG. 2.

Referring toFIG. 15, a substrate10is provided. Isolation layers12for defining the active region11are formed within the substrate10. Gate lines GL, each including an insulation layer21, a gate electrode layer22, and a capping layer23are formed between the isolation layers12of the substrate10. Although the gate lines GL constitute buried transistors in the present example embodiment, this is only an example, and the gate lines GL may constitute planar transistors. An auxiliary insulation layer44covering the gate lines GL is formed on the substrate10.

Referring toFIG. 16, openings OP2exposing portions of the substrate10between the gate lines GL are formed by recessing the portions of the substrate10between the gate lines GL. The openings OP2may be formed by lithography or etch back.

Referring toFIG. 17, a sacrificial layer39is formed on the gate lines GL. The sacrificial layer39may fill the openings OP2. The sacrificial layer39may include a conductive material, for example, metal. The sacrificial layer39may include one of titanium (Ti), cobalt (Co), nickel (Ni), tantalum (Ta), platinum (Pt), vanadium (V), erbium (Er), zirconium (Zr), hafnium (Hf), molybdenum (Mo), and ytterbium (Yb). The sacrificial layer39may be formed by using a method such as sputtering, CVD, PECVD, or ALD.

Referring toFIG. 18, the first and second contact layers30aand32aare formed by thermally treating the sacrificial layer39. The first contact layer30aand the second contact layer32amay be between the gate lines GL. The first contact layer30aand the second contact layer32amay be buried in the substrate10. The first contact layer30aand the second contact layer32amay be formed by a reaction between the materials of the sacrificial layer39and the substrate10, and may include, for example, a silicide material. In other words, the first contact layer30aand the second contact layer32amay include a metal silicide material formed by a reaction of the metal material of the sacrificial layer39with the silicon material of the substrate10. The first contact layer30aand the second contact layer32amay be formed in the same process or different processes.

Referring toFIG. 19, the first and second contact layers30aand32aare exposed by removing the sacrificial layer39. The removing process may be performed by CMP or etchback. The first contact layer30aand the second contact layer32amay protrude more than the gate lines GL. Top surfaces of the first contact layer30aand the second contact layer32amay have a height higher than the top surfaces of the capping layers23of the gate lines GL. The top surfaces of the first contact layer30aand the second contact layer32amay be level with the top surfaces of the capping layers23of the gate lines GL or may have a height lower than the top surfaces of the capping layers23.

A metal silicide material forming the first contact layer30aand the second contact layer32amay be deposited to be higher than the gate lines GL by the thermal treatment ofFIG. 18. However, the metal silicide material forming the first contact layer30aand the second contact layer32amay be deposited to be level with or lower than the gate lines GL by the planarization process ofFIG. 19.

Referring toFIG. 20, the memory cell contact plug MP is formed on the first contact layer30ato be is electrically connected to the first contact layer30a. The source line contact plug SP is formed on the second contact layer32ato be electrically connected to the second contact layer32a. The memory cell contact plug MP may be surrounded by the first and second interlayer insulation layers40and42. The source line contact plug SP may be surrounded by the first interlayer insulation layer40.

The variable resistive memory cell60, the source line SL, and the bit line BL are formed to complete the variable resistive memory device2ofFIG. 14.

FIG. 21is a cross-sectional view of a variable resistive memory device3according to some example embodiments of inventive concepts. The variable resistive memory device3according to the present example embodiments is a modification of the variable resistive memory devices1and2described above with reference toFIGS. 1 to 20, so a description of duplicate matters will be omitted. According to the present example embodiment, a gate line GL constitutes a planar transistor.

Referring toFIG. 21, the variable resistive memory device3may include a substrate10, a gate line GL, a variable resistive memory cell60, a source line SL, and a bit line BL.

The variable resistive memory device3may further include a source line contact plug SP electrically connecting the source line SL to an active region11of the substrate10, and a memory cell contact plug MP electrically connecting the variable resistive memory cell60to the active region11of the substrate10.

The variable resistive memory device3may further include a first contact layer30bbetween the source line contact plug SP and the active region11of the substrate10that has less contact resistance with respect to the active region11of the substrate10than the source line contact plug SP. The variable resistive memory device3may further include a second contact layer32bbetween the memory cell contact plug MP and the active region11of the substrate10that has less contact resistance with respect to the active region11of the substrate10than the memory cell contact plug MP.

The gate line GL may be on the active region11of the substrate10. According to an example embodiment, the gate line GL may constitute a planar transistor. The gate line GL may include an insulation layer25, a gate electrode layer26, a capping layer27, and a spacer28. The gate electrode layer26may correspond to the word line WL ofFIG. 1. The gate line GL and a source/drain region13may constitute a MOS transistor to function as an access device.

The first contact layer30band the second contact layer32bmay be outside the gate line GL. Top surfaces of the first contact layer30band the second contact layer32bmay be level with the top surface of the capping layer27of the gate line GL or may have a height lower than the top surface of the capping layer27.

The first contact layer30bmay have less contact resistance with respect to the active region11of the substrate10than the memory cell contact plug MP. The second contact layer32bmay have less contact resistance with respect to the active region11of the substrate10than the source line contact plug SP. The first contact layer30band the second contact layer32bmay include a silicide material, for example, metal silicide. The metal may include one of titanium (Ti), cobalt (Co), nickel (Ni), tantalum (Ta), platinum (Pt), vanadium (V), erbium (Er), zirconium (Zr), hafnium (Hf), molybdenum (Mo), and ytterbium (Yb). The first contact layer30band the second contact layer32bmay include the same material or different materials.

The memory cell contact plug MP may be on the first contact layer30bexposed through the first and second interlayer insulation layers40and42. The source line contact plug SP may be on the second contact layer32bexposed through the first interlayer insulation layer40.

The source line SL may be on the first interlayer insulation layer40to be electrically connected to the source line contact plug SP. Accordingly, the active region11of the substrate10and the source line SL may be electrically connected to each other via the second contact layer32band the source line contact plug SP.

The memory cell contact plug MP, which is electrically connected to the first contact layer30b, may be within the first and second interlayer insulation layers40and42. The variable resistive memory cell60may be on the memory cell contact plug MP. Accordingly, the active region11of the substrate10and the variable resistive memory cell60may be electrically connected to each other via the first contact layer30band the memory cell contact plug MP.

FIG. 22is a schematic view illustrating an example embodiment of a memory card5000according to an example embodiment of inventive concepts.

Referring toFIG. 22, a controller5100and a memory5200are configured to send/receive electric signals to/from each other. For example, when the controller5100gives a command to the memory5200, the memory5200can send data. The memory5200can include the non-volatile memory device100, according to an example embodiment of inventive concepts. The non-volatile memory devices according to the various example embodiments of inventive concepts can be in NAND or NOR architecture arrays in correspondence to the logic gate design. Such NAND and NOR arrays are generally known in the art. The memory arrays in a plurality of rows and columns can have one or more memory array bank (not shown). The memory5200can include the memory array (not shown) or the memory array bank (not shown), all of which are known in the art. The memory card5000can further include conventional members, such as a conventional row decoder (not shown), a column decoder (not shown), input/output (I/O) buffers (now shown), and/or a control resistor (not shown) in order to drive the memory array bank (not shown), all of which are known in the art. The memory card5000can be used in memory devices as a memory card, for example, such as a memory stick card, a smart media (SM) card, a secure digital (SD) card, a mini SD card, or a multi media card (MMC).

FIG. 23is a schematic diagram of a system6000according to an example embodiment of inventive concepts.

Referring toFIG. 23, the system6000may include a controller6100, an input/output device6200, a memory6300, and an interface6400. The system6000may be a mobile system or a system that transmits or receives data. The mobile system may be a personal digital assistant (PDA), a portable computer, a web tablet, a wireless phone, a mobile phone, a digital music player, or a memory card. The controller6100executes a software program and controls the system6000. The controller6100may be a microprocessor, a digital signal processor, a microcontroller, or the like. The input/output device6300can be used to input or output data of the system6000. The system6000is connected to an external apparatus, for example, a personal computer or a network, using the input/output device6200, to send/receive data to/from the external apparatus. The input/output device6200may be a keypad, a keyboard, or a display. The memory6300may store codes and/or data for operating the controller6100and/or may store data processed by the controller6100. The memory6300may include a non-volatile memory device according to an example embodiment of inventive concepts. The interface6400may be a data transmission path between the system6000and an external apparatus. The controller6100, the input/output device6200, the memory6300, and the interface6400may communicate with one another by a bus6500. For example, the system6000can be used for a mobile phone, an MP3 player, a navigation system, a portable multimedia player (PMP), a solid state disk (SSD), or a household appliance.

FIG. 24is a perspective view of an electronic device7000to which a semiconductor device according to an example embodiment of inventive concepts is applicable.

Referring toFIG. 24, the electronic system7000is a case in which the electronic system5000(seeFIG. 22),6000(seeFIG. 23) is applied to a mobile phone. Besides the mobile phone, the electronic system5000(seeFIG. 22),6000(seeFIG. 23) may also be applicable to an MP3 player, a navigation device, a portable multimedia player (PMP), a solid state disk (SSD), a vehicle, or household appliances.

The foregoing is illustrative of example embodiments and is not to be construed as limiting thereof. Although example embodiments have been described, those of ordinary skill in the art will readily appreciate that many modifications are possible in the example embodiments without materially departing from the novel teachings and advantages of the example embodiments. Accordingly, all such modifications are intended to be included within the scope of the claims. Example embodiments are defined by the following claims, with equivalents of the claims to be included therein.