Fabrication of Schottky barrier diode using lateral epitaxial overgrowth

A diode is disclosed. The diode includes a semiconductor substrate, a hard mask formed above the substrate, vertically oriented components of a first material adjacent sides of the hard mask, and laterally oriented components of the first material on top of the hard mask. The laterally oriented components are oriented in a first direction and a second direction. The diode also includes a second material on top of the first material. The second material forms a Schottky barrier.

TECHNICAL FIELD

Embodiments of the disclosure pertain to fabricating Schottky diodes and, in particular, fabricating Schottky diodes using lateral epitaxial overgrowth.

BACKGROUND

Some conventional radio frequency (RF) systems use on-chip electrostatic discharge (ESD) protection circuits to provide ESD protection for system circuitry. The design of ESD protection circuits for such systems can be challenging. ESD protection circuits need to have current density and leakage current characteristics that enable them to provide effective protection. In particular, the ESD protection circuit needs to have the capacity to handle significant amounts of current in response to an ESD event and to exhibit low reverse leakage current during normal operation.

GaN transistors are promising candidates for use in future RF products such as 5G products. In order to enable a fully integrated GaN RF frontend for such products, there is a need for ESD protection circuits that use high performance Schottky diodes. However, Schottky diodes can exhibit higher leakage current than some other types of diodes. Conventional approaches to ESD protection circuit design do not adequately address current density and reverse leakage current challenges.

DESCRIPTION OF THE EMBODIMENTS

Approaches for fabricating Schottky diodes using lateral epitaxial overgrowth are described. In the following description, numerous specific details are set forth, such as specific integration and material regimes, in order to provide a thorough understanding of embodiments of the present disclosure. It will be apparent to one skilled in the art that embodiments of the present disclosure may be practiced without these specific details. In other instances, well-known features, such as integrated circuit design layouts, are not described in detail in order to not unnecessarily obscure embodiments of the present disclosure. Furthermore, it is to be appreciated that the various embodiments shown in the Figures are illustrative representations and are not necessarily drawn to scale.

In an embodiment, a co-integration of GaN transistors and Schottky diodes in the same die is done using single operation regrowth of epitaxial material to form Schottky diode components and transistor source and drain components of a co-integrated semiconductor structure. Embodiments, as part of the fabrication of a Schottky diode, utilize the regrowth of highly doped material to form a layer of material over which a Schottky barrier is formed. The highly doped layer of material is formed during source-drain epitaxial regrowth operations for a co-integrated transistor. Embodiments utilize lateral overgrowth of the highly doped material to form a highly doped material layer that has low defect density underneath the Schottky barrier. These material characteristics are used to fabricate Schottky diodes that can deliver high current density. In addition, the low defect density reduces reverse bias vertical leakage current. In embodiments, the highly doped material is formed in a single operation without extra regrowth.

FIG. 1is an illustration of a cross-section of an integrated MOSHEMT and GaN Schottky diode semiconductor structure according to an embodiment. In an embodiment, single operation epitaxial regrowth is used to form thin films as part of the structuring of transistor source and drain regions and Schottky diode cathode components of the co-integrated semiconductor structure. The process results in a Schottky diode that delivers high current density and exhibits low reverse bias leakage current.

Referring toFIG. 1, the Schottky diode100A includes the semiconductor material115which is highly doped and has low defect density. The low defect density of the semiconductor material115enables the Schottky diode100A to deliver current of higher density than could be delivered using materials that have a higher defect density. In an embodiment, the semiconductor material115is formed from highly doped GaN. In an embodiment, semiconductor material115is formed during the formation of the source133, the drain145, the first cathode region105and the second cathode region107. The material that is grown in the first cathode region105and the second cathode region107of the semiconductor structure100accumulates in those regions and vertically rises along the sidewalls of the stack of materials of the semiconductor structure100that includes the semiconductor layer109, the polarization layer111, the hard mask layer113and parts of the epitaxial layer103. In an embodiment, the semiconductor material115eventually extends above the hard mask113. Thereafter, in an embodiment, process conditions are adjusted to promote lateral growth of the semiconductor material. The accumulating material then moves laterally from the sides of the hard mask113until the top surface of the hard mask113is covered. The manner in which the lateral regrowth of epitaxial material is used to form the highly doped and low defect density semiconductor material115is discussed herein with reference toFIGS. 2A-2E.

The hard mask layer113isolates the material layers that are located above the hard mask layer113from the defects of the substrate101that is located below the hard mask layer113. For example, defects of the substrate101are projected upwards from the substrate101through the GaN epitaxial layer103, the semiconductor layer109and the polarization layer111. However, the hard mask layer113has a physical structure that is impenetrable by the defects. Thus, the upward projection of the defects is stopped by the hard mask layer113. It should be appreciated that in an embodiment the material that is located above the hard mask layer113, such as the low defect density and highly doped semiconductor115, unintentionally doped layer117and the Schottky barrier layer119, are protected by the defect blocking utility of the hard mask layer113.

In operation, upon the occurrence of an ESD event, the Schottky diode100A becomes forward biased and routes the ESD current to ground. In this manner, the current is prevented from damaging circuitry such as RF device frontend circuitry that can include transistors such as the transistor100B (which can be located at the front end of an associated RF device). In an embodiment, because the material that is formed underneath the Schottky barrier is highly doped, the current density of the current that flows in the Schottky diode100A is high, which provides Schottky diode100A with a robust current handling capacity. In addition, when the Schottky diode100A is reversed biased, because the material that is formed underneath the Schottky barrier is low in defects, reverse current leakage is low, and reverse voltage protection is maximal.

In an embodiment, the substrate101can be formed from silicon. In other embodiments, the substrate101can be formed from other materials. In an embodiment, the epitaxial layer103can be formed from GaN. In other embodiments, the epitaxial layer103can be formed from other materials. In an embodiment, the first cathode105and the second cathode107can be formed from InGaN. In other embodiments, the first cathode105and the second cathode107can be formed from other materials. In an embodiment, the semiconductor109can be formed from an AlN. In other embodiments, semiconductor109can be formed from other materials. In an embodiment, the polarization layer111can be formed from AlInN. In other embodiments, the polarization layer111can be formed from other materials. In an embodiment, the hard mask layer113can be formed from a nitride. In other embodiments, the hard mask layer113can be formed from other materials. In an embodiment, the highly doped and low defect density semiconductor layer115can be formed from InGaN. In other embodiments, the highly doped and low defect density semiconductor layer115can be formed from other materials. In an embodiment, the unintentionally doped semiconductor117can be formed from GaN. In other embodiments, the unintentionally doped semiconductor117can be formed from other materials. In an embodiment, the Schottky barrier layer119can be formed from AlGaN or AlInN. In other embodiments, the Schottky barrier layer119can be formed from other materials. In an embodiment, the insulator121can be formed from an oxide. In other embodiments, the insulator121can be formed from other materials. In an embodiment, the first cathode contact123can be formed from Ti, Al or W. In other embodiments, the first cathode contact123can be formed from other materials. In an embodiment, the second cathode contact125can be formed from Ti, Al or W. In other embodiments, the second cathode contact125can be formed from other materials. In an embodiment, the Schottky metal127can be formed from nickel, platinum or titanium nitride. In other embodiments, the Schottky metal127can be formed from other materials. In an embodiment, the insulator129can be formed from an oxide. In other embodiments, the insulator129can be formed from other materials. In an embodiment, the source133can be formed from InGaN. In other embodiments, the source133can be formed from other materials. In an embodiment, the source contact131can be formed from Ti, Al or W. In other embodiments, the source contact131can be formed from other materials. In an embodiment, the drain145can be formed from InGaN. In other embodiments, the drain145can be formed from other materials. In an embodiment, the drain contact143can be formed from Ti, Al or W. In other embodiments, the drain contact143can be formed from other material. In one embodiment, the gate139can be formed from nickel, platinum or titanium nitride. In other embodiments, the gate139can be formed from other materials. In an embodiment, the gate contact137can be formed from Ti, Al or W. In other embodiments, the gate contact137can be formed from other material. In an embodiment, high-k material135can include but is not limited to hafnium oxide. In other embodiments, high-k material can include other materials. In an embodiment, the tall hard mask141can be formed from polysilicon or silicon dioxide. In other embodiments, the tall hard mask141can be formed from other materials.

Advantages of embodiments include the formation of both a highly doped and low defect density semiconductor layer115underneath a Schottky barrier layer119and the Schottky barrier layer119itself during an operation for forming the source and the drain of a co-integrated transistor100B. Thus, multiple operations for forming these structures are avoided. As discussed above, in an embodiment, the formation of the highly doped and low defect density semiconductor layer115can be accomplished using lateral overgrowth techniques. In an embodiment, the highly doped and low defect density semiconductor layer115is formed from high quality material that has a low defect density. In addition, in an embodiment, the orientation of the lateral overgrowth contributes to the low defect density of the highly doped and low defect density semiconductor layer115. Moreover, as described above, the hard mask113protects the highly doped and low defect density semiconductor layer115from defects that are projected from the substrate103. The highly doped and low defect density semiconductor layer115with low defect density results in a Schottky diode that delivers high current density and exhibits low reverse bias leakage current.

FIGS. 2A-2Fare illustrations of cross-sectional views of a semiconductor structure200during a fabrication process for a Schottky barrier diode that uses lateral overgrowth. Referring toFIG. 2A, after a plurality of operations, a cross-section of semiconductor structure200is formed that includes substrate201, epitaxial layer203, semiconductor layer205, polarization layer207short hard mask209, tall hard mask211, oxide213, semiconductor215, polarization layer217and short hard mask219. In an embodiment, the cross-section ofFIG. 2Ais an illustration of the appearance of the semiconductor structure200before source/drain epitaxial regrowth operations. In an embodiment, unlike conventional masking approaches which use source/drain epitaxial regrowth processes based on an epitaxial region etch out and undercut, a tall hard mask211is used for epitaxial regrowth. In an embodiment, a tall (e.g., greater than 150 nm) hard mask211is formed for source-drain epitaxial regrowth in the transistor region. Moreover, a short (e.g., approximately 20-30 nm) hard mask209is formed for epitaxial regrowth in the Schottky diode region. In other embodiments, hard masks of other heights can be used. In an embodiment, the depth of the epitaxial undercut (EUC) can be the same in both the transistor and the Schottky diode region.

Referring toFIG. 2B, after one or more operations that result in the cross-section of the semiconductor structure200that is shown inFIG. 2A, a source-drain epitaxial growth operation is performed. In an embodiment, the source-drain epitaxial growth operation can be performed by loading the wafer into an epitaxial reactor for the source-drain epitaxial growth operation. In other embodiments, the epitaxial growth operation can be performed in any other suitable manner of performing the epitaxial growth operation. In an embodiment, the first thin film that is grown is a highly doped n+ InGaN film221. In an embodiment, the highly doped n+ InGaN film221is doped with Si. In other embodiments, the n+ InGaN film221can be doped with other materials. Because the hard mask209for the Schottky region is shallow, initially, the n+ InGaN film221grows vertically along the sidewalls of the hard mask209and eventually extends vertically above the top of hard mask209. The n+ InGaN film221then grows laterally223along the top surface of the hard mask209from both sides and eventually completely covers the top surface of the hard mask209. The InGaN crystal that grows along the sidewalls of the hard mask209is high quality InGaN crystal that has a low defect density. This same high quality InGaN crystal with low defect density laterally overgrows the shallow hard mask region209. The epitaxial growth operation helps to decouple the defects of the substrate from critical regions of the Schottky diode200A as the overgrowth above the shallow hard mask209is protected from the defects that are projected from the substrate201by the shallow hard mask209. Thus, in embodiments, because Schottky diode reverse leakage current is directly proportional to defect density, the Schottky diode200A is able to provide low reverse leakage current. In this manner the challenge of achieving low defect density that is described herein is addressed.

Referring toFIG. 2C, after one or more operations that result in the cross-section shown inFIG. 2B, the n+ InGaN film223that is grown laterally along the top surface of the hard mask209is grown longer by configuring process conditions to foster lateral overgrowth of the top surface of the hard mask209as opposed to vertical growth. In an embodiment, this process results in the merger of the n+ InGaN film223overgrowth on the top surface of the hard mask209in the Schottky diode region200A.

Referring toFIG. 2D, after one or more operations that result in the cross-section of the semiconductor structure200shown inFIG. 2C, a thin layer of undoped GaN225is grown. In an embodiment, the thin layer of undoped GaN225can have a thickness of approximately 20-30 nm. In other embodiments, the thin layer of undoped GaN225can have other thicknesses. Referring toFIG. 2E, after one or more operations that result in the cross-section of the semiconductor structure200shown inFIG. 2D, a material227that is chosen for setting the Schottky barrier for the Schottky diode is grown above the thin layer of undoped GaN225. In an embodiment, the material227that is chosen for setting the Schottky barrier can include a thin layer of AlGaN (30%)˜1 eV barrier, of 10 nm thickness. In other embodiments, other materials that have other thicknesses can be used for the material for setting the Schottky barrier.

Referring toFIG. 2F, after one or more operations that result in a cross-section of the semiconductor structure200such as is shown inFIG. 2E(after the epitaxial growth has been completed) the different height areas of the semiconductor structure200are planarized. Thereafter, a gate for the MOS HEMT device229, a Schottky contact231for the diode, and ohmic metal contacts233and236to the source235and the drain237regions of the MOS HEMT device200B are formed. In an embodiment, a dry etch is used to etch out the undoped GaN225and the AlGaN 227 layers to form a space for ohmic metal contacts in the Schottky diode region before the deposition of ohmic metals.

A plurality of transistors, such as metal-oxide-semiconductor field-effect transistors (MOSFET or simply MOS transistors), may be fabricated on the substrate. In various implementations of the invention, the MOS transistors may be planar transistors, nonplanar transistors, or a combination of both. Nonplanar transistors include FinFET transistors such as double-gate transistors and tri-gate transistors, and wrap-around or all-around gate transistors such as nanoribbon and nanowire transistors. Although the implementations described herein may illustrate only planar transistors, it should be noted that the invention may also be carried out using nonplanar transistors.

The gate electrode layer is formed on the gate dielectric layer and may consist of at least one P-type workfunction metal or N-type workfunction metal, depending on whether the transistor is to be a PMOS or an NMOS transistor. In some implementations, the gate electrode layer may consist of a stack of two or more metal layers, where one or more metal layers are workfunction metal layers and at least one metal layer is a fill metal layer.

In some implementations of the invention, a pair of sidewall spacers may be formed on opposing sides of the gate stack that bracket the gate stack. The sidewall spacers may be formed from a material such as silicon nitride, silicon oxide, silicon carbide, silicon nitride doped with carbon, and silicon oxynitride. Processes for forming sidewall spacers are well known in the art and generally include deposition and etching process steps. In an alternate implementation, a plurality of spacer pairs may be used, for instance, two pairs, three pairs, or four pairs of sidewall spacers may be formed on opposing sides of the gate stack.

As is well known in the art, source and drain regions are formed within the substrate adjacent to the gate stack of each MOS transistor. The source and drain regions are generally formed using either an implantation/diffusion process or an etching/deposition process. In the former process, dopants such as boron, aluminum, antimony, phosphorous, or arsenic may be ion-implanted into the substrate to form the source and drain regions. An annealing process that activates the dopants and causes them to diffuse further into the substrate typically follows the ion implantation process. In the latter process, the substrate may first be etched to form recesses at the locations of the source and drain regions. An epitaxial deposition process may then be carried out to fill the recesses with material that is used to fabricate the source and drain regions. In some implementations, the source and drain regions may be fabricated using a silicon alloy such as silicon germanium or silicon carbide. In some implementations the epitaxially deposited silicon alloy may be doped in situ with dopants such as boron, arsenic, or phosphorous. In further embodiments, the source and drain regions may be formed using one or more alternate semiconductor materials such as germanium or a group III-V material or alloy. And in further embodiments, one or more layers of metal and/or metal alloys may be used to form the source and drain regions.

One or more interlayer dielectrics (ILD) are deposited over the MOS transistors. The ILD layers may be formed using dielectric materials known for their applicability in integrated circuit structures, such as low-k dielectric materials. Examples of dielectric materials that may be used include, but are not limited to, silicon dioxide (SiO2), carbon doped oxide (CDO), silicon nitride, organic polymers such as perfluorocyclobutane or polytetrafluoroethylene, fluorosilicate glass (FSG), and organosilicates such as silsesquioxane, siloxane, or organosilicate glass. The ILD layers may include pores or air gaps to further reduce their dielectric constant.

FIG. 3illustrates a computing device300in accordance with one implementation of the invention. The computing device300houses a board302. The board302may include a number of components, including but not limited to a processor304and at least one communication chip306. The processor304is physically and electrically coupled to the board302. In some implementations the at least one communication chip306is also physically and electrically coupled to the board302. In further implementations, the communication chip306is part of the processor304.

The processor304of the computing device300includes an integrated circuit die packaged within the processor304. In some implementations of the invention, the integrated circuit die of the processor includes one or more devices, such as MOS-FET transistors built in accordance with implementations of the invention. The term “processor” may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory.

The communication chip306also includes an integrated circuit die packaged within the communication chip306. In accordance with another implementation of the invention, the integrated circuit die of the communication chip includes one or more devices, such as MOS-FET transistors built in accordance with implementations of the invention.

In further implementations, another component housed within the computing device300may contain an integrated circuit die that includes one or more devices, such as MOS-FET transistors built in accordance with implementations of the invention.

FIG. 4illustrates an interposer400that includes one or more embodiments of the invention. The interposer400is an intervening substrate used to bridge a first substrate402to a second substrate404. The first substrate402may be, for instance, an integrated circuit die. The second substrate404may be, for instance, a memory module, a computer motherboard, or another integrated circuit die. Generally, the purpose of an interposer400is to spread a connection to a wider pitch or to reroute a connection to a different connection. For example, an interposer400may couple an integrated circuit die to a ball grid array (BGA)406that can subsequently be coupled to the second substrate404. In some embodiments, the first and second substrates402/404are attached to opposing sides of the interposer400. In other embodiments, the first and second substrates402/404are attached to the same side of the interposer400. And in further embodiments, three or more substrates are interconnected by way of the interposer400.

The interposer may include metal interconnects408and vias410, including but not limited to through-silicon vias (TSVs)412. The interposer400may further include embedded devices414, including both passive and active devices. Such devices include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, and electrostatic discharge (ESD) devices. More complex devices such as radio-frequency (RF) devices, power amplifiers, power management devices, antennas, arrays, sensors, and MEMS devices may also be formed on the interposer400. In accordance with embodiments of the invention, apparatuses or processes disclosed herein may be used in the fabrication of interposer400.

The following examples pertain to further embodiments. The various features of the different embodiments may be variously combined with some features included and others excluded to suit a variety of different applications.

A diode comprises a semiconductor substrate, a hard mask formed above the substrate, vertically oriented components of a first material adjacent sides of the hard mask, and laterally oriented components of the first material on top of the hard mask. The laterally oriented components are oriented in a first direction and a second direction. A second material is on top of the first material. The second material forms a Schottky barrier.

The diode of example embodiment 1, wherein the laterally oriented components are directed from a first side of the hard mask and a second side of the hard mask.

The diode of example embodiment 1, wherein the hard mask prevents defects from the substrate from reaching the first material.

The diode of example embodiment 1, wherein the hard mask includes a nitride material.

The diode of example embodiment 1, wherein a layer of gallium nitride is on the substrate and under the hard mask.

The diode of example embodiment 1, wherein a Schottky metal is formed above the Schottky barrier.

The diode of example embodiment 1, 2, 3, 4, 5 or 6 wherein the diode is a Schottky diode.

A semiconductor device comprises a transistor and a diode. The diode comprises a semiconductor substrate, a hard mask formed above the substrate, vertically oriented components of a first material adjacent sides of the hard mask, and laterally oriented components of the first material on top of the hard mask. The laterally oriented components are oriented in a first direction and a second direction. A second material is formed above the first material. The second material forms a Schottky barrier.

The semiconductor device of example embodiment 8, wherein the laterally oriented components are directed from a first side of the hard mask and a second side of the hard mask.

The semiconductor device of example embodiment 8, wherein the hard mask prevents defects from the substrate from reaching the first material.

The semiconductor device of example embodiment 8, wherein the hard mask includes a nitride material.

The semiconductor device of example embodiment 8, 9, 10 or 11 wherein a layer of gallium nitride is on the substrate and under the hard mask.

The semiconductor device of claim1, wherein a Schottky metal is formed above the Schottky barrier.

The semiconductor device of claim13, wherein the diode is a Schottky diode.

A method comprises forming a semiconductor substrate, forming a hard mask formed above the substrate, forming vertically oriented components of a first material adjacent sides of the hard mask, and forming laterally oriented components of the first material on top of the hard mask. The laterally oriented components are oriented in a first direction and a second direction. A second material is formed above the first material, the second material forming a Schottky barrier.

The method of example embodiment 15, wherein the laterally oriented components are directed from a first side of the hard mask and a second side of the hard mask.

The method of example embodiment 15, wherein the hard mask prevents defects from the substrate from reaching the first material.

The method of example embodiment 15, wherein the hard mask includes HSON.

The method of example embodiment 15, wherein a layer of GaN is on the substrate and under the hard mask.

The method of example embodiment 15, wherein a Schottky metal is formed above the Schottky barrier.