Locality aware load balancing of IO paths in multipathing software

An apparatus comprises a host device configured to communicate over a network with a storage system. The host device comprises a plurality of nodes each comprising a plurality of processing devices and at least one communication adapter. The host device comprises a multi-path input-output (MPIO) driver that is configured to obtain an input-output (IO) operation that targets a given logical volume. The MPIO driver identifies a source node and a plurality of paths between the source node and the given logical volume. The MPIO driver determines a load factor and a distance for each identified path. The MPIO driver determines a weight associated with each identified path based at least in part on the determined load factor and distance and selects a target path based at least in part on the determined weight. The MPIO driver delivers the obtained IO operation to the given logical volume via the selected target path.

FIELD

BACKGROUND

Storage arrays and other types of storage systems are often shared by multiple host devices over a network. A given host device may comprise a multi-path input-output (MPIO) driver that is configured to process input-output (IO) operations for delivery from the given host device to the storage system. In some cases, the host devices may implement a non-uniform memory access (NUMA) architecture, combining groups of processing devices, memory and hardware bus adapters (HBAs) into separate nodes which enhances processing and latency within a given node. Utilizing existing multi-pathing techniques with host devices implementing a NUMA architecture may result in various inefficiencies in the storage system.

SUMMARY

Illustrative embodiments of the present invention provide techniques for what is referred to herein as “locality aware pathing.” For example, some embodiments provide locality aware load balancing of IO paths in multi-pathing software. Other types of locality aware pathing can be implemented in other embodiments.

In one embodiment, an apparatus comprises a host device configured to communicate over a network with a storage system comprising a plurality of storage devices. The host device comprises a plurality of nodes each comprising a plurality of processing devices, memory coupled to the plurality of processing devices, and at least one communication adapter. Each node is connected to at least one adjacent node by an interconnect communication pathway. The host device further comprises an MPIO driver that is configured to deliver input-output operations from the host device to the storage system over the network. The MPIO driver is further configured to obtain an input-output operation that targets a given logical volume of the storage system. The MPIO driver identifies a source node among the plurality of nodes for the input-output operation based at least in part on information associated with the input-output operation and identifies a plurality of paths between the source node and the given logical volume via the communication adapters of the plurality of nodes. The MPIO driver determines a load factor for each identified path based at least in part on input-output operations pending for each identified path and determines a distance for each identified path between the source node and a corresponding communication adapter for each identified path. The MPIO driver determines a weight associated with each identified path based at least in part on the determined load factor and the determined distance and selects a target path from the identified paths based at least in part on the determined weight. The MPIO driver delivers the obtained input-output operation to the given logical volume via the selected target path.

DETAILED DESCRIPTION

Illustrative embodiments will be described herein with reference to exemplary information processing systems and associated computers, servers, storage devices and other processing devices. It is to be appreciated, however, that embodiments of the present disclosure are not restricted to use with the particular illustrative system and device configurations shown. Accordingly, the term “information processing system” as used herein is intended to be broadly construed, so as to encompass, for example, processing systems comprising cloud computing and storage systems, as well as other types of processing systems comprising various combinations of physical and virtual processing resources. An information processing system may therefore comprise, for example, at least one data center that includes one or more clouds hosting multiple tenants that share cloud resources. Numerous other types of enterprise and cloud-based computing and storage systems are also encompassed by the term “information processing system” as that term is broadly used herein.

FIG. 1shows an information processing system100configured in accordance with an illustrative embodiment. The information processing system100comprises a plurality of host devices102-1,102-2, . . .102-N. The host devices102communicate over a storage area network (SAN)104with at least one storage array105. The storage array105comprises a plurality of storage devices106-1, . . .106-M each storing data utilized by one or more applications running on one or more of the host devices102. The storage devices106are illustratively arranged in one or more storage pools. The storage array105and its associated storage devices106is an example of what is more generally referred to herein as a “storage system.” This storage system in the present embodiment is shared by the host devices102, and is therefore also referred to herein as a “shared storage system.”

The host devices102illustratively comprise respective computers, servers or other types of processing devices capable of communicating with the storage array105of the SAN104. For example, at least a subset of the host devices102may be implemented as respective virtual machines of a compute services platform or other type of processing platform. The host devices102in such an arrangement illustratively provide compute services such as execution of one or more applications on behalf of each of one or more users associated with respective ones of the host devices102. The term “user” herein is intended to be broadly construed so as to encompass numerous arrangements of human, hardware, software or firmware entities, as well as combinations of such entities. Compute services may be provided for users under a Platform-as-a-Service (PaaS) model, although it is to be appreciated that numerous other cloud infrastructure arrangements could be used.

The storage devices106of the storage array105of SAN104implement logical units or volumes (LUNs) configured to store objects for users associated with the host devices102. These objects can comprise files, blocks or other types of objects. In illustrative embodiments, the storage devices106may comprise one or more clusters of storage devices106. The host devices102interact with the storage array105utilizing read and write commands as well as other types of commands that are transmitted over the SAN104. Such commands in some embodiments more particularly comprise small computer system interface (SCSI) commands or non-volatile memory express (NVMe) commands, depending on the type of storage device, although other types of commands can be used in other embodiments. A given IO operation as that term is broadly used herein illustratively comprises one or more such commands. References herein to terms such as “input-output” and “IO” should be understood to refer to input and/or output. Thus, an IO operation relates to at least one of input and output.

Also, the term “storage device” as used herein is intended to be broadly construed, so as to encompass, for example, a logical storage device such as a LUN or other logical storage volume. A logical storage device can be defined in the storage array105to include different portions of one or more physical storage devices. Storage devices106may therefore be viewed as comprising respective LUNs or other logical storage volumes.

Each of the host devices102illustratively has multiple IO paths to the storage array105, with at least one of the storage devices106of the storage array105being visible to that host device on a given one of the paths. A given one of the storage devices106may be accessible to the given host device over multiple IO paths.

Different ones of the storage devices106of the storage array105illustratively exhibit different latencies in processing of IO operations. In some cases, the same storage device may exhibit different latencies for different ones of multiple IO paths over which that storage device can be accessed from a given one of the host devices102.

The host devices102and the storage array105may be implemented on respective distinct processing platforms, although numerous other arrangements are possible. For example, in some embodiments at least portions of the host devices102and the storage array105are implemented on the same processing platform. The storage array105can therefore be implemented at least in part within at least one processing platform that implements at least a subset of the host devices102.

The SAN104may be implemented using multiple networks of different types to interconnect storage system components. For example, the SAN104may comprise a portion of a global computer network such as the Internet, although other types of networks can be part of the SAN104, including a wide area network (WAN), a local area network (LAN), a satellite network, a telephone or cable network, a cellular network, a wireless network such as a WiFi or WiMAX network, or various portions or combinations of these and other types of networks. The SAN104in some embodiments therefore comprises combinations of multiple different types of networks each comprising processing devices configured to communicate using Internet Protocol (IP) or other related communication protocols.

The host devices102comprise respective sets of IO queues110-1,110-2, . . .110-N, respective MPIO drivers112-1,112-2, . . .112-N, and respective sets of nodes116-1,116-2, . . .116-N. The MPIO drivers112collectively comprise a multi-path layer of the host devices102. The multi-path layer provides functionality for locality aware pathing logic114-1,114-2, . . .114-N implemented within the MPIO drivers112.

With reference now toFIG. 2, an example set of nodes116for a given host device102illustratively comprises a plurality of nodes202, e.g., nodes202-1and202-2in the illustrated example. While illustrated as having two nodes202in the example ofFIG. 2, the set of nodes116for a given host device102may alternatively comprise any other number of nodes. In some embodiments, the set of nodes116may implement a NUMA architecture where each node202is a NUMA node of the NUMA architecture.

The nodes202of a given host device102each comprise at least one central processing units (CPU)204, memory206and at least one communication adapter208. For example, in the embodiment illustrated inFIG. 2, node202-1comprises CPUs204-1and204-2, memory206-1, and communication adapter208-1and node202-2comprises CPUs204-3and204-4, memory206-2, and communication adapter208-2. While each node202in the example embodiment shown inFIG. 2is illustrated as having two CPUs204, a memory206, and a communication adapter208, a given node202in alternative embodiments may have any other number of CPUs204, memory206, and communication adapters208. In some embodiments, a given node202may not comprise a communication adapter208at all where, for example, such a given node202may rely on the communication adapters208of the other nodes202for communicating with the storage array105.

The CPUs204may comprise microprocessors, microcontrollers, application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), graphics processing units (GPUs) or other type of processing circuitry, as well as portions or combinations of such circuitry elements.

The memory206may comprise random access memory (RAM), read-only memory (ROM), flash memory or other types of memory, in any combination.

The communication adapters208may comprise, for example, HBAs or any other communication or network adapter that may be used to connect to a network such as, e.g., network fabric212, and allow communication between nodes202and storage array105vis the network fabric.

Each communication adapter208comprises a port210that is connected to network fabric212. For example, communication adapter208-1comprises a port210-1and communication adapter208-2comprises a port210-2. In some embodiments, the communication adapters208or ports210may comprise a PCI slot that is used to communication with the network fabric212.

In illustrative embodiments each node202may comprise at least one communication pathway, referred to herein as an interconnect214, to an adjacent node202. For example, in the embodiment illustrated inFIG. 2, node202-1may be connected directly to node202-2via an interconnect214. Interconnect214facilitates the transfer of information or other data directly between nodes202-1and202-2without relying on the bandwidth of the network fabric212or other communication pathways of information processing system100. In some embodiments, each node202may connected to each other node202via an interconnect214.

In an illustrative embodiment, each node202is connected to one or more adjacent nodes202via a respective interconnect214. For example, for data to be transferred from a given node202to another node202that is not connected directly to the given node202via an interconnect214, one or more intermediary nodes202and their respective associated interconnects214may be used.

In some embodiments, a distance map may be generated and stored in a given host device102that comprises information on the various communication pathways of the architecture of the set of nodes116of a given host device102. For example, the distance map may comprise information that indicates a relative distance of a communication pathway between each pair of nodes202in the set of nodes116based on how many interconnects214need to be utilized to communicate between the pair of nodes202.

In one example, with reference again toFIG. 2, the communication pathway between node202-1and adjacent node202-2may only use a single interconnect214. In such a case, a value may be assigned to the communication pathway between node202-1and node202-2in the distance map which indicates the relative distance. For example, the value may indicate that a single interconnect214is used in the communication pathway. For example, the distance map may include information indicating a value of 2 for this communication pathway.

In another example, where a given node202and a target node202are not connected directly by an interconnect214, the communication pathway between the given node202and the target node202may comprise one or more intermediary nodes202and corresponding interconnects214. In such a case, the distance map may indicate, for example, how many interconnects214need to be traversed to reach the target node202. For example, if there is only one intermediary node202, the communication pathway between the given node202and the target node202may comprise two interconnects214. In such a case, a value may be assigned to the communication pathway between the given node202and the target node202in the distance map which indicates the relative distance. For example, the value assigned to the communication pathway may indicate that two interconnects214are used. For example, the distance map may include information indicating a value of 3 for the communication pathway in this example.

In some embodiments, the distance map may also assign a value of 1 for each communication pathway which indicates that no interconnects214are used, e.g., where a given node202transmits an IO operation to the storage array105using its own communication adapter208instead of the communication adapter208of another node202.

In some embodiments, for example, the value in the distance map for each communication pathway may be the number of interconnects214included in that communication pathway plus 1. For example, a communication pathway between adjacent nodes202which only uses a single interconnect214may have a value of 2 in the distance map.

While particular values such as 1, 2 and 3 are used in the above examples, any other value or other indication may be included in the distance map that indicates a relative distance of a communication pathway in the set of nodes116. In some embodiments, the locality of a given node202may be defined by the distance map. For example, the values found in the distance map for the paths associated with each node202may define the locality of that node202.

MPIO drivers typically group all paths from a host device to a LUN into a single logical device known as a multi-path logical device. The individual block devices representing each path are known as native devices. Applications use a multi-path logical device for IO operations so that the IO operations may be distributed across all available paths. When paths fail, the MPIO driver will typically redirect the IO operations to other alive paths in the multi-path logical device.

In an illustrative embodiment, for example as seen inFIG. 2, storage array105comprises a plurality of logical volumes216-1,216-2, . . .216-P, e.g., residing on storage devices106-1. . .106-M (FIG. 1). Each communication adapter208communicates with a given logical volume216via one or more paths218through different portions220, e.g., network infrastructure, of the network fabric212. In some embodiments, a communication adapter208and corresponding portion220may together may be referred to as an initiator-target (IT) nexus for a path, where I represents an initiator (e.g., communication adapter208) and T represents a target (e.g., the portion220of the network fabric220) for the path. As illustrated inFIG. 2, for example, communication adapter208-1(designated as C1) may communicate with a target storage volume216-1(designated as D1) via portion220-1(designated as T1) of network fabric212forming a path218-1(C1T1D1). Communication adapter208-1(C1) may also communicate with storage volume216-1(D1) via portion220-2(designated as T2) of network fabric212forming a path218-2(C1T2D1). Communication adapter208-2(designated as C2) may communicate with storage volume216-1(D1) via portion220-1(T1) of network fabric212forming a path218-3(C2T1D1). Communication adapter208-2(C2) may also communicate with storage volume216-1(D1) via portion220-2(T2) of network fabric212forming a path218-4(C2T2D1). Thus, in the example ofFIG. 2, there are four paths,218-1(C1T1D1),218-2(C1T2D1),218-3(C2T1D1) and218-4(C2T2D1), between the set of nodes116of the host device102and the target logical volume216-1, two for each of communication adapters208-1and208-2.

Paths may be added or deleted between the host devices102and the storage array105in the system100. For example, the addition of one or more new paths from host device102-1to the storage array105or the deletion of one or more existing paths from the host device102-1to the storage array105may result from the respective addition or deletion of at least a portion of the storage devices106of the storage array105.

Addition or deletion of paths can also occur as a result of zoning and masking changes or other types of storage system reconfigurations performed by a storage administrator or other user.

In some embodiments, paths are added or deleted in conjunction with the addition of a new storage array or the deletion of an existing storage array from a storage system that includes multiple storage arrays, possibly in conjunction with configuration of the storage system for at least one of a migration operation and a replication operation.

For example, a storage system may include first and second storage arrays, with data being migrated from the first storage array to the second storage array prior to removing the first storage array from the storage system.

As another example, a storage system may include a production storage array and a recovery storage array, with data being replicated from the production storage array to the recovery storage array so as to be available for data recovery in the event of a failure involving the production storage array.

In these and other situations, path discovery scans may be performed by the MPIO drivers of the multi-path layer as needed in order to discover the addition of new paths or the deletion of existing paths.

A given path discovery scan can be performed utilizing known functionality of conventional MPIO drivers, such as PowerPath® drivers.

The path discovery scan in some embodiments may be further configured to identify one or more new LUNs or other logical storage volumes associated with the one or more new paths identified in the path discovery scan. The path discovery scan may comprise, for example, one or more bus scans which are configured to discover the appearance of any new LUNs that have been added to the storage array105as well to discover the disappearance of any existing LUNs that have been deleted from the storage array105.

For each of one or more new paths identified in a path discovery scan of the type described above, the corresponding one of the host devices102is configured to execute a host registration operation for that path. The host registration operation for a given new path illustratively provides notification to the storage array105that the corresponding one of the host devices102has discovered the new path.

The MPIO drivers utilize the multiple paths described above to send IO operations from the host devices102to the storage array105.

For example, an MPIO driver112-1is configured to select IO operations from its corresponding set of IO queues110-1for delivery to the storage array105over the SAN104. The sources of the IO operations stored in the set of IO queues110-1illustratively include respective processes of one or more applications executing on the host device102-1. Other types of sources of IO operations may be present in a given implementation of system100.

The MPIO drivers described herein may comprise, for example, otherwise conventional MPIO drivers, such as PowerPath® drivers from Dell EMC of Hopkinton, Mass., suitably modified in the manner disclosed herein to implement functionality for locality aware pathing. Other types of MPIO drivers from other driver vendors may be suitably modified to incorporate functionality for locality aware pathing as disclosed herein.

In some embodiments, migration involves synchronizing the target storage device or LUN to the source storage device or LUN, i.e., achieving an operating state in which the target storage device or LUN stores the same data as the source storage device or LUN, and then a path flip operation is performed so that subsequent accesses of the data are directed to the target storage device or LUN instead of the source storage device or LUN. Once the path flip operation is successfully accomplished, the source storage device or LUN can be taken out of service or put to some other use.

A number of data migration technologies are available to migrate data from a source LUN to a target LUN. One such data migration tool is Dell EMC PowerPath® Migration Enabler (PPME). PowerPath®, of which PPME is one component, is available on common operating systems such as Linux, Windows, AIX and VMware ESX. PPME uses multiple data transfer technologies for data migration including, for example, host copy, open replicator, and other similar technologies.

The storage array105in the present embodiment is assumed to comprise a persistent memory that is implemented using a flash memory or other types of non-volatile memory of the storage array105. More particular examples include NAND-based flash memory or other types of non-volatile memory such as resistive RAM, phase change memory, spin torque transfer magneto-resistive RAM (STT-MRAM) and Intel Optane™ devices based on 3D XPoint™ memory. The persistent memory is further assumed to be separate from the storage devices106of the storage array105, although in other embodiments the persistent memory may be implemented as a designated portion or portions of one or more of the storage devices106. For example, in some embodiments the storage devices106may comprise flash-based storage devices, as in embodiments involving all-flash storage arrays.

The storage array105in the present embodiment further comprises additional components such as response time control module120and IO operation priority queues122, illustratively configured to make use of the above-described persistent memory. For example, the response time control module120may be used to implement storage array-based adjustments in response time for particular IO operations based at least in part on service level objective (SLO) information stored by the storage array105in its persistent memory. The response time control module120operates in conjunction with the IO operation priority queues122.

The storage array105utilizes its IO operation priority queues122to provide different levels of performance for IO operations. For example, the IO operation priority queues122may have respective different priority levels. The storage array105may be configured to provide different priority levels for different ones of the IO operations by assigning different ones of the IO operations to different ones of the IO operation priority queues122. The IO operation priority queues122are illustratively associated with respective SLOs for processing of IO operations in the storage array105.

Process tags may be used in assigning different ones of the IO operations to different ones of the IO operation priority queues122, as disclosed in U.S. patent application Ser. No. 15/849,828, filed Dec. 21, 2017, and entitled “Storage System with Input-Output Performance Control Utilizing Application Process Detection,” which is incorporated by reference herein.

As mentioned above, communications between the host devices102and the storage array105may utilize PCIe connections or other types of connections implemented over one or more networks. For example, illustrative embodiments can use interfaces such as Serial Attached SCSI (SAS) and Serial ATA (SATA). Numerous other interfaces and associated communication protocols can be used in other embodiments.

The storage array105in some embodiments may be implemented as part of cloud infrastructure in the form of a cloud-based system such as an Amazon Web Services (AWS) system. Other examples of cloud-based systems that can be used to provide at least portions of the storage array105and possibly other portions of system100include Google Cloud Platform (GCP) and Microsoft Azure.

The storage array105may additionally or alternatively be configured to implement multiple distinct storage tiers of a multi-tier storage system. By way of example, a given multi-tier storage system may comprise a fast tier or performance tier implemented using flash storage devices, and a capacity tier implemented using hard disk drive devices. A wide variety of other types of server-based flash storage devices and multi-tier storage systems can be used in other embodiments, as will be apparent to those skilled in the art. The particular storage devices used in a given storage tier may be varied depending on the particular needs of a given embodiment, and multiple distinct storage device types may be used within a single storage tier. As indicated previously, the term “storage device” as used herein is intended to be broadly construed, and so may encompass, for example, disk drives, flash drives, solid-state drives, hybrid drives or other types of storage products and devices, or portions thereof, and illustratively include logical storage devices such as LUNs.

As another example, the storage array105may be used to implement one or more storage nodes in a cluster storage system comprising a plurality of storage nodes interconnected by one or more networks.

It should therefore be apparent that the term “storage array” as used herein is intended to be broadly construed, and may encompass multiple distinct instances of a commercially-available storage array suitably reconfigured to support node locality aware pathing of IO operations as disclosed herein.

For example, the storage array105may comprise one or more storage arrays such as VNX®, Symmetrix VMAX® and Unity™ storage arrays, commercially available from Dell EMC. Other types of storage products that can be used in implementing a given storage system in illustrative embodiments include software-defined storage products such as ScaleIO™, cloud storage products such as Elastic Cloud Storage (ECS), object-based storage products such as Atmos, scale-out all-flash storage arrays such as XtremIO™, and scale-out NAS clusters comprising Isilon® platform nodes and associated accelerators, all from Dell EMC. Combinations of multiple ones of these and other storage products can also be used in implementing a given storage system in an illustrative embodiment.

These and other storage systems can be part of what is more generally referred to herein as a processing platform comprising one or more processing devices each comprising a processor coupled to a memory. A given such processing device may correspond to one or more virtual machines or other types of virtualization infrastructure such as Docker containers or other types of LXCs. As indicated above, communications between such elements of system100may take place over one or more networks.

The term “processing platform” as used herein is intended to be broadly construed so as to encompass, by way of illustration and without limitation, multiple sets of processing devices and associated storage systems that are configured to communicate over one or more networks. For example, distributed implementations of the host devices102are possible, in which certain ones of the host devices102reside in one data center in a first geographic location while other ones of the host devices102reside in one or more other data centers in one or more other geographic locations that are potentially remote from the first geographic location. Thus, it is possible in some implementations of the system100for different ones of the host devices102to reside in different data centers than the storage array105.

Numerous other distributed implementations of the host devices102and/or the storage array105are possible. Accordingly, the storage array105can also be implemented in a distributed manner across multiple data centers.

In illustrative embodiments, the MPIO drivers112provide functionality for locality aware pathing of IO operations from the nodes202of a host device102to the storage array105using respective locality aware pathing logic114implemented within the MPIO drivers112.

In some systems, a NUMA node may comprise processors, memory, and communication adapters. A NUMA node is an example of a node202as described above with reference toFIG. 2. NUMA affinity is a metric or indication of the relative efficiency of utilizing particular resources where, for example, the resources found within a particular NUMA node will have a high NUMA affinity for each other. For example, a processor within a particular NUMA node will have a high NUMA affinity to other resources within that NUMA node and a lower NUMA affinity to resources within another NUMA node. In some embodiments, the values found in the distance map mentioned above may comprise NUMA affinity information.

NUMA affinity may be utilized when attempting to balance IO load within an information processing system. For example, NUMA affinity may be utilized by MPIO software on top of typical load balancing techniques such as, e.g., a round robin algorithm, to drive the balancing of IO operations. For example, IO operations may be pushed to particular PCI slots based on the NUMA affinity of the processor that is handling the IO operation to those PCI slots, e.g., since they are all in the same NUMA node. However, inefficiencies and imbalances in the IO load balancing of the storage system may result where, for example, the PCI slot or slots of that NUMA node are over-loaded.

In NVMe technology, where the hardware is capable of dispatching IO operations on multiple queues simultaneously, effective and optimal load balancing becomes even more important. MPIO drivers which support multi-queue architectures may be aware of the NUMA affinity of the components of the NUMA nodes in a NUMA based architecture. Because of this, if an IO operation uses a particular processor of the NUMA node, then the memory and PCI slot of that NUMA node will typically be chosen for servicing that IO operation based on their NUMA affinity. Ideally such a technique will reduce cache misses. In cases where the PCI slot of that NUMA node is overloaded with other IO operations, however, blind reliance on NUMA affinity may result in increased latency and other inefficiencies within the system.

In illustrative embodiments, the IO load for IO operations may be optimized by considering both locality, e.g., the distance values from the distance map (NUMA affinity in some embodiments), and load factor, which is based at least in part on pending IO operations for the communication adapters within the system.

In some embodiments, IO operations may be routed to a non-node aligned hardware queue, e.g., to a communication adapter that is not part of a node202, if the IO load on the communication adapter208located in a node202is too high.

In illustrative embodiments, a given MPIO driver112obtains a node topology of the set of nodes116of the host device102. For example, MPIO diver112may determine the topology of each node202including, e.g., which CPUs204, memory206, and communication adapters208belong to each node202. The MPIO driver112may also obtain the distance map, described above, for the set of nodes116. The distance map may, for example, comprise distance values for each path from the CPUs204of each node202to each of the logical volumes216of the storage array105, as described above. In some embodiments, values of the distance map may comprise the NUMA affinity values for the set of nodes116. For example, the value in the distance map for each path may comprise the NUMA affinity.

The MPIO driver112may also determine the nodes202and corresponding communication adapters208of the set of nodes116that may be utilized to service an IO operation. For example, the MPIO driver112may generate or obtain the available paths for routing IO operations from each CPU204to each of the logical volumes216of the storage array105via the communication adapters208of each of the nodes202. The MPIO driver112may generate a mapping or other data structure that maps each CPU204to each communication adapter208as part of the available paths that may be utilized to dispatch IO operations to the logical volumes216of the storage array105. In some embodiments, the mapping may also comprise the distance values of the distance map associated with each communication pathway that corresponds to the CPUs204and communication adapters208.

In some embodiments, if the available communication adapters208for dispatching IO operations to the logical volumes216of the storage array105are not spread across the plurality of nodes202, e.g., only the communication adapters208on a single node202or subset of nodes202are available for routing IO operations, an alert or other alarm may be issued by the MPIO driver112. For example, the alert may indicate that there is a communication or other failure between one or more of the nodes202in the set of nodes116that is reducing the availability of the communication adapters208of at least some of those nodes202for use in routing IO operations to the logical volumes216of the storage array105.

In an illustrative embodiment, when an MPIO driver112obtains an IO operation that targets a given logical volume216from an IO queue110, the MPIO driver determines which path will be used to dispatch the IO operation to the storage array105. In illustrative embodiments, the MPIO driver112utilizes locality aware pathing logic114to determine which path will be used for that IO operation.

In illustrative embodiments, locality aware pathing logic114may determine the source CPU204and node202from which the IO operation has originated or that will be servicing the IO operation for the host device102. For example, the IO operation, or information associated with the IO operation, may comprise an indication of the source CPU204. In some embodiments, for example, the IO operation, or information associated with the IO operation, may comprise a CPU identifier (ID) that may be used to identify the source CPU204and thus the node202containing the source CPU204.

With the source CPU204identified, locality aware pathing logic114determines each path that may be used to dispatch the IO operation from the source CPU204to the target logical volume216. For example, with reference again toFIG. 2, an example set of the available paths to a given logical volume216-1that originate at a given CPU204-1(and thus node202-1) may comprise a first path218-1(C1T1D1) which utilizes communication adapter208-1of node202-1and portion220-1of the network fabric212, a second path218-2(C1T2D1) which utilizes communication adapter208-1of node202-1and portion220-2of the network fabric212, a third path218-3(C2T1D1) which utilizes communication adapter208-2of node202-2, e.g., via interconnect214, and portion220-1of the network fabric212and a fourth path218-4(C2T2D1) which utilizes communication adapter208-2of node202-2, e.g., via interconnect214, and portion220-2of the network fabric212. Any other number of paths may also or alternatively be available that utilize the communication adapters208of any other nodes202.

In some embodiments, locality aware pathing logic114may generate a vector based at least in part on the available paths that may be used to dispatch the IO operation from the source CPU204to the target logical volume216. For example, in some embodiments, the vector may comprise an entry for each available path and each entry may comprise a respective distance value for that path. In illustrative embodiments, for example, the distance value in the vector for each available path may be obtained based at least in part on the above described distance map. For example, the communication pathways between the nodes that each path utilizes may be compared to the distance map to identify the relevant communication pathway in the distance map and the value for that communication pathway may be obtained for use as the distance value for that path in the vector.

An example vector for the example set of available paths described above may comprise Di=(1, 1, 2, 2). For example, the first entry of 1 in vector Direpresents the distance associated with path218-1, i.e., no interconnects are utilized for this path since the path originates at CPU204-1and utilizes communication adapter208-1which is in the same node202-1, the second entry of 1 in vector Direpresents the distance associated with path218-2, i.e., no interconnects are utilized for this path since the path originates at CPU204-1and utilizes communication adapter208-1which is in the same node202-1, the third entry of 2 in vector Direpresents the distance associated with path218-3, i.e., the interconnect214between node202-1and node202-2is utilized for this path since the path originates at CPU204-1of node202-1and utilizes communication adapter208-2which is in node202-2, a different node, and the fourth entry of 2 in vector Direpresents the distance associated with path218-4, i.e., the interconnect214between node202-1and node202-2is utilized for this path since the path originates at CPU204-1of node202-1and utilizes communication adapter208-2which is in node202-2.

In illustrative embodiments, locality aware pathing logic114may also determine the IO load, e.g., number of read and write IO blocks, pending at each communication adapter208of each node202. In some embodiments, the IO load may also or alternatively be determined for each portion220of network fabric source212. For example, the pending IO load may be obtained from the MPIO driver212or another component of the host device102or information processing system100.

In illustrative embodiments, a load factor for each available path may be determined based at least in part on the determined IO loads. For example, a load factor vector Wimay be generated that comprises the load factor for each available path. In illustrative embodiments, the load factor for each available path may comprise a value based at least in part on the IO load for the communication adapter208utilized in that path. In some embodiments, the load factor for each available path may comprise a value based at least in part on the IO load for the portion220of the network fabric212utilized in that path. In some embodiments, the load factor for each available path may comprise a value based at least in part on the IO load for both the communication adapter208and the portion220of the network fabric212that are utilized in that path. In some embodiments, the load factor for each available path may comprise a value based at least in part on the IO load on any portion of the path including, for example, the IO load on the communication adapter208, the IO load on the portion220of the network fabric212, and the IO load on any other portion of the path including the interface with the storage array105. In illustrative embodiments, the larger the number of IO blocks pending along the path, the greater the value of the load factor for the path.

In an example embodiment, the determined IO loads may be normalized to a particular range to generate the load factor. In an example embodiment, the range of the load factor may comprise 0 to 100 and the IO loads may be normalized to fit in this range. As an example, path218-1may have 85010 blocks pending which may be normalized to a load factor value of 85 (850×0.1), path218-2may have 350 IO blocks pending which may be normalized to a load factor value of 35 (350×0.1), path218-3may have 500 blocks pending which may be normalized to a load factor value of 50 (500×0.1), and path218-4may have 150 IO blocks pending which may be normalized to a load factor value of 15 (150×0.1). In such an example, the load factor vector Wifor paths218-1,218-2,218-3and218-4may comprise Wi=(85, 35, 50, 15). Any other range of values and normalization may be utilized depending on the specific attributes of the system. In alternative embodiments no normalization may be used and the IO load of each component may be used as is in the load factor vector.

In illustrative embodiments, locality aware pathing logic114calculates a weight for each path based on a function f(Di, Wi) of the distance vector Diand the load factor vector Wiwhere the distance vector Direpresents the latency added by using communication adapters of different nodes, and the load factor represents the load on the communication adapters and portions of the network fabric of each IT nexus. For example, in some embodiments, the function f(Di, Wi) may comprise a multiplication operation that multiplies the distance value in the distance vector Dito the corresponding load factor value in the load factor vector Wifor each path to determine that path's weight. In the example scenario above, the function f(Di, Wi)=(85*1), (35*1), (50*2), (15*2)=85, 35, 100, 30. Thus path218-1has a weight of 85, path218-2has a weight of 35, path218-3has a weight of 100 and path218-4has a weight of 30 in this example. In some embodiments, for example, modifier weights may be applied to the values of each of the distance vector and load factor components to tailor the function as desired. For example, the distance values and load factor values may be separately weighted to increase or decrease their respective contribution to the final weight value of the function for each path.

In illustrative embodiments, the locality aware pathing logic114selects the path218having the minimum calculated weight, for example, Path=Min [f(Di, Wi)]. For example, where the function f(Di, Wi)=85 (path218-1), 35 (path218-2), 100 (path218-3), 30 (path218-4), locality aware pathing logic114selects path218-4for delivery of the IO operation to the target logical volume216-1since path218-4has the minimum weight. In other embodiments, a path other than the path with the minimum weight may be selected based on the function f(Di, Wi).

In illustrative embodiments, if the host device102does not implement a node-based architecture, such as a NUMA architecture, the distance values in the distance vector may be set to 1 such that load balancing across the paths may be performed according to conventional techniques.

While locality aware pathing logic114is described above with respect to the nodes of a single host device, in some embodiments, the nodes of any number of host devices may be used where, for example, a given path from a given CPU204to a given logical volume216may utilize a communication adapter208associated with a node202of a host device102that is different than the host device102that contains the given CPU204.

It is to be appreciated that these and other features of illustrative embodiments are presented by way of example only, and should not be construed as limiting in any way. Accordingly, different numbers, types and arrangements of system components such as host devices102, SAN104, storage array105, storage devices106, sets of IO queues110, MPIO drivers112, locality aware pathing logic114and sets of nodes116can be used in other embodiments.

It should also be understood that the particular sets of modules and other components implemented in the system100as illustrated inFIG. 1are presented by way of example only. In other embodiments, only subsets of these components, or additional or alternative sets of components, may be used, and such components may exhibit alternative functionality and configurations.

Illustrative embodiments of the techniques and functionality of locality aware pathing logic114will now be described in more detail with reference to the flow diagram ofFIG. 3.FIG. 3provides an example process that is implemented by locality aware pathing logic114to select a path for delivering an IO operation to a given logical volume that takes into account both IO load and locality of the communication adapter used by that path to the CPU processing the IO operation.

The process as shown inFIG. 3includes steps300through314, and is suitable for use in the system100but is more generally applicable to other types of systems comprising multiple host devices and a shared storage system.

At300, the MPIO driver112obtains an IO operation from the IO queue110of its host device102. The IO operation targets a given logical volume of the storage array105, e.g., logical volume216-1.

At302, locality aware pathing logic114identifies the source node202for the IO operation. For example, the locality aware pathing logic114may obtain a CPU ID associated with the IO operation to determine a CPU204that is processing the IO operation. The identified source node202will be the source node202containing the CPU204corresponding to the CPU ID.

At304, locality aware pathing logic114identifies the available paths between the source node202and the given logical volume, e.g., one or more of the paths218in the example ofFIG. 2.

At306, locality aware pathing logic114determines the load factor associated with each path. For example, locality aware pathing logic114may determine the load factor associated with a path based at least in part on the number of IO blocks pending at one or more of a communication adapter208utilized by the path, a portion220of the network fabric212utilized by the path, or any other portion of the information processing system100that is utilized by that path or in another manner as described above.

At308, locality aware pathing logic114determines the distance for each path. For example, locality aware pathing logic114may determine the distance based on the values found in the distance map as described above.

At310, locality aware pathing logic114determines a weight for each path as a function of the load factor and the distance for that path, for example, as described above.

At312, locality aware pathing logic114selects a target path based at least in part on the determined weights. For example, locality aware pathing logic114may select the path that has the minimum weight among the available paths. In some embodiments, another path may be selected based at least in part on the determined weights other than the path having the minimum weight. For example, the path having the second lowest weight, or any other path may be selected.

At314, locality aware pathing logic114delivers the IO operation to the given logical volume via the selected target path.

Separate instances of the process ofFIG. 3may be performed in respective additional host devices that share the storage array.

The particular processing operations and other system functionality described in conjunction with the flow diagram ofFIG. 3is presented by way of illustrative example only, and should not be construed as limiting the scope of the disclosure in any way. Alternative embodiments can use other types of processing operations involving host devices, storage systems and locality aware pathing logic. For example, the ordering of the process steps may be varied in other embodiments, or certain steps may be performed at least in part concurrently with one another rather than serially. Also, one or more of the process steps may be repeated periodically, or multiple instances of the process can be performed in parallel with one another in order to implement a plurality of different locality aware pathing logic arrangements within a given information processing system.

Functionality such as that described in conjunction with the flow diagram ofFIG. 3can be implemented at least in part in the form of one or more software programs stored in memory and executed by a processor of a processing device such as a computer or server. As will be described herein, a memory or other storage device having executable program code of one or more software programs embodied therein is an example of what is more generally referred to herein as a “processor-readable storage medium.”

The above-described functions associated with functionality for locality aware pathing are carried out at least in part under the control of its locality aware pathing logic114. For example, locality aware pathing logic114is illustratively configured to control performance of portions of the process shown in the flow diagram described above in conjunction withFIG. 3.

It is assumed that each of the other MPIO drivers112are configured in a manner similar to that described above and elsewhere herein for the first MPIO driver112-1. The other host devices102of the system100are therefore also configured to communicate over the SAN104with the storage array105, and the MPIO drivers112of such other host devices102are each similarly configured to select IO operations from a corresponding one of the sets of IO queues110for delivery to the storage array105over the SAN104, and to perform the disclosed functionality for locality aware pathing. Accordingly, functionality described above in the context of the first MPIO driver112-1is assumed to be similarly performed by each of the other MPIO drivers112-2through112-N.

The MPIO drivers112may be otherwise configured utilizing well-known MPIO functionality such as that described in K. Piepho, “Dell EMC SC Series Storage: Microsoft Multipath I/O,” Dell EMC Engineering, June 2017, which is incorporated by reference herein. Such conventional MPIO functionality is suitably modified in illustrative embodiments disclosed herein to support locality aware pathing.

Although in some embodiments certain commands used by the host devices102to communicate with the storage array105illustratively comprise SCSI commands, other types of commands and command formats can be used in other embodiments. For example, some embodiments can implement IO operations utilizing command features and functionality associated with NVMe, as described in the NVMe Specification, Revision 1.3, May 2017, which is incorporated by reference herein. Other storage protocols of this type that may be utilized in illustrative embodiments disclosed herein include NVMe over Fabric, also referred to as NVMeoF.

As indicated previously, absent use of functionality for locality aware pathing as disclosed herein, IO load balancing in node-based architectures such as, e.g., a NUMA architecture, may be inefficient since the loads will typically be sent to those communication adapters with the highest affinity to the source CPU, i.e., the communication adapters found in the same node.

Such drawbacks are advantageously overcome in illustrative embodiments herein by utilization of locality aware pathing logic114to implement functionality for locality aware pathing as described above. For example, by selecting the target path as a function of a load factor on each communication adapter and distance to the communication adapter, the path having the best combination of available throughput and latency may be utilized to maximize efficiency in the system. This allows an underutilized communication adapter to be taken advantage of by the MPIO driver even when the latency to that underutilized communication adapter may be greater than the latency to a local communication adapter since the difference in latency may be offset by the additional time that the IO blocks of the IO operation would wait in the queue for the local communication adapter, which results in better IO throughput and lower latency overall in the system.

It was noted above that portions of an information processing system as disclosed herein may be implemented using one or more processing platforms. Illustrative embodiments of such platforms will now be described in greater detail. These and other processing platforms may be used to implement at least portions of other information processing systems in other embodiments. A given such processing platform comprises at least one processing device comprising a processor coupled to a memory.

Cloud infrastructure as disclosed herein can include cloud-based systems such as Amazon Web Services, Google Cloud Platform and Microsoft Azure. Virtual machines provided in such systems can be used to implement a fast tier or other front-end tier of a multi-tier storage system in illustrative embodiments. A capacity tier or other back-end tier of such a multi-tier storage system can be implemented using one or more object stores such as Amazon S3, Google Cloud Platform Cloud Storage, and Microsoft Azure Blob Storage.

Another illustrative embodiment of a processing platform that may be used to implement at least a portion of an information processing system comprises a plurality of processing devices which communicate with one another over at least one network. The network may comprise any type of network, including by way of example a global computer network such as the Internet, a WAN, a LAN, a satellite network, a telephone or cable network, a cellular network, a wireless network such as a WiFi or WiMAX network, or various portions or combinations of these and other types of networks.

Each processing device of the processing platform comprises a processor coupled to a memory. The processor may comprise a microprocessor, a microcontroller, an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), a graphics processing unit (GPU) or other type of processing circuitry, as well as portions or combinations of such circuitry elements. The memory may comprise random access memory (RAM), read-only memory (ROM), flash memory or other types of memory, in any combination. The memory and other memories disclosed herein should be viewed as illustrative examples of what are more generally referred to as “processor-readable storage media” storing executable program code of one or more software programs.

Also included in the processing device is network interface circuitry, which is used to interface the processing device with the network and other system components, and may comprise conventional transceivers.

As another example, portions of a given processing platform in some embodiments can comprise converged infrastructure such as VxRail™, VxRack™, VxRack™ FLEX, VxBlock™, or Vblock® converged infrastructure from Dell EMC.

Again, these particular processing platforms are presented by way of example only, and other embodiments may include additional or alternative processing platforms, as well as numerous distinct processing platforms in any combination, with each such platform comprising one or more computers, servers, storage devices or other processing devices.

Also, numerous other arrangements of computers, servers, storage devices or other components are possible in an information processing system as disclosed herein. Such components can communicate with other elements of the information processing system over any type of network or other communication media.

It should again be emphasized that the above-described embodiments are presented for purposes of illustration only. Many variations and other alternative embodiments may be used. For example, the disclosed techniques are applicable to a wide variety of other types of information processing systems, utilizing other arrangements of host devices, networks, storage systems, storage arrays, storage devices, processors, memories, IO queues, MPIO drivers, locality aware pathing logic, sets of nodes and additional or alternative components. Also, the particular configurations of system and device elements and associated processing operations illustratively shown in the drawings can be varied in other embodiments. For example, a wide variety of different MPIO driver configurations and associated locality aware pathing logic arrangements can be used in other embodiments. Moreover, the various assumptions made above in the course of describing the illustrative embodiments should also be viewed as exemplary rather than as requirements or limitations. Numerous other alternative embodiments within the scope of the appended claims will be readily apparent to those skilled in the art.