Method to improve metal defects in semiconductor device fabrication

The invention, in one aspect, provides a method of manufacturing a semiconductor device. This method includes providing a semiconductor substrate and depositing a metal layer over the semiconductor substrate that has an overall thickness of about 1 micron or greater. The metal layer is formed by depositing a first portion of the thickness of the metal layer, which has a compressive or tensile stress associated therewith over the semiconductor substrate. A stress-compensating layer is deposited over the first portion, such that the stress-compensating layer imparts a stress to the first portion that is opposite to the compressive or tensile stress associated with the first portion. A second portion of the thickness of the metal layer is then deposited over the stress-compensating layer.

TECHNICAL FIELD OF THE INVENTION

The invention is directed, in general, to a method of manufacturing a semiconductor device and, more specifically, to a method that improves metal defects in a thick deposited metal.

BACKGROUND OF THE INVENTION

Optimization of semiconductor devices continues to be an important goal for the semiconductor industry. Such optimization schemes often include incorporating large scale components, such as inductors, onto the same chip on which the transistors are made. Typically, these large scale devices require the deposition of thicker metals than those used to form other components, such as interconnects, in the semiconductor device. For example, in forming inductors, metal thickness can reach thicknesses of about 1 to 3 microns.

Unfortunately, during the deposition of these thick metal layers, metal defects can occur. Due to the thickness that must be achieved, the wafer is exposed to plasma for a longer period of time that results in higher and up-trend wafer temperatures. When the wafer is finally cooled down at the end of the deposition process, the thick metal will often contract and the resulting force will cause metal defects. These metal defects are very undesirable in that they can affect yield and cause reliability issues.

To address these problems, the semiconductor industry has attempted to adjust the thermal budgets used during the deposition of thick metal layers by breaking the deposition process into two or three separate steps. For example, the metal deposition is conducted for a period of 10 minutes and then discontinued to allow the substrate to cool down. Then, the metal deposition is continued for another 10 minutes with a cool down period at the end of that deposition cycle. This is continued until the full thickness of the metal layer is achieved. While these processes have reduced the number of defects to some degree, they have not fully addressed the issue in that metal defects are still observed.

Accordingly, there is a need to provide a process by which thick layers may be deposited while avoiding the problems associated with the conventional processes discussed above.

SUMMARY OF THE INVENTION

To address the above-discussed deficiencies, the invention provides, in one embodiment, a method of manufacturing a semiconductor device. This embodiment comprises providing a semiconductor substrate and depositing a metal layer over the semiconductor substrate. The metal layer has an overall thickness of about 1 micron or greater. The method of depositing this metal layer includes depositing a first portion the metal layer, which has a compressive or tensile stress associated therewith over the semiconductor substrate. A stress-compensating layer is deposited over the first portion, such that the stress-compensating layer has a stress associated with it that is opposite to the compressive or tensile stress associated with the first portion. A second portion of the metal layer is then deposited over the stress-compensating layer. In one embodiment, this method may be used to manufacture an integrated circuit (IC) that has an inductor incorporated therein.

DETAILED DESCRIPTION

Referring initially toFIG. 1, there is illustrated a general, partial view of a semiconductor device100as provided by the invention. In this embodiment, the semiconductor device100includes a transistor region105that may be of conventional design and manufactured with conventional processes and materials. As such, the transistor region includes conventional transistors106, interconnects107, and dielectric layers108. Also included is a semiconductor component110, such as an inductor. The invention's application is not limited to an inductor, however, and it should be noted that any semiconductor component that requires a thick metal deposition of about 1 micron or more is also within the scope of the invention. Additionally, the semiconductor component110may be located at any level of the semiconductor device100. In the illustrated embodiment, the semiconductor component110is located at or near the outermost dielectric layer110, and just prior to the final interconnect level within the device.

In the illustrated embodiment, the inductor component110includes a segmented metal layer115that has an intervening stress-compensating layer120located between segmented portions115aof the metal layer115. Thus, the overall stress is compensated throughout the deposition by inserting this stress-compensating layer120or layers at different stages. In most embodiments, the portions115awill have the same metallic composition, which includes alloys thereof. However, in other embodiments, the portions115amay be comprised of different metals or alloys, but whatever the composition of the metal or alloy, it is preferably different from the metal or alloy composition of the stress-compensating layer120. As seen in this embodiment, the metal layer115contains first, second and third portions115awith a stress-compensating layer120located between the first and second portions115aand the second and third portions115aof the metal layer115.

The invention recognizes that controlling the thermal budget as discussed above is not sufficient to adequately reduce the number of metal defects that occur in metal layers having a thickness of about 1 micron or more. The invention also recognizes that a cause of the metal defects may be attributable to the compressive or tensile stress associated with the thick metal layer upon its deposition. It is further recognized that significant reduction in metal defects in such metal layers can be achieved by segmenting the metal layer into separate layer portions and placing a stress-compensating layer between those portions. The stress-compensating layer120is deposited in a way such that it has an associated stress opposite to that of the metal layer115. The stress-compensating layer120will in effect counter the inherent stress within the metal and lessen or eliminate the occurrence of metal defects.

FIG. 2Aillustrates an enlarged view of one embodiment of the upper portion of a semiconductor device200that may be employed in the semiconductor device100ofFIG. 1at one stage of manufacture. InFIG. 2A, a first portion205aof a metal layer205is deposited over a dielectric layer210. The total thickness of the metal layer205at the end of the deposition cycle should be about 1 micron or more. At this stage, a conventional barrier layer (not shown), such as titanium/titanium nitride (Ti/TiN) or tantalum/tantalum (Ta/TaN) may be located between the dielectric layer210and the first portion205a. The barrier layer may have a thickness of about 60 nm.

The first portion205aof the metal layer205may be deposited using conventional deposition processes, such as physical vapor deposition (PVD). In one embodiment, the deposition parameters may include using an aluminum target and sputtering in an inert gas, such as argon, that has a flow ranging from about 10 sccm to about 30 sccm, at a pressure ranging from about 2500 mTorr to about 8500 mTorr, and at a power ranging from about 4000 to about 12000 watts. The depositional conditions of the first portion205acauses a stress215to be incorporated into the first portion205a. Here the stress215is shown to be tensile, but the stress may also be compressive. In certain embodiments, the stress of the first portion205amay range from about 1E8 to 5E9 Pascals. The metal layer205may be comprised of any conductive metal, alloy, or any other conductive material that is suitable for making a semiconductor device. For example, the metal layer205may be aluminum, or in other embodiments, it may be copper, gold, silver platinum, or palladium, to name just a few.

The thickness of the first portion205awill depend on the overall, final thickness of the metal layer205and the number of portions into which the metal layer205is ultimately divided. For example, the thickness of each portion of the metal layer205may range from about 0.3 microns to 1.5 microns. In the embodiment illustrated inFIG. 2A, the metal layer205is to be divided into two portions having a total thickness of about 1.4 microns. Thus, the thickness of the first portion205awill be about 0.70 microns.

As seen inFIG. 2B, following the deposition of the first portion205a, a stress-compensating layer220is deposited over the first portion205a. In an advantageous embodiment, the stress-compensating layer220is a single layer, however, it may also be a stack of layers; this may be the case for all embodiments of the invention. The stress-compensating layer220is deposited in a way to cause it to have a stress225that is opposite the stress of the underlying first portion205a. For instance, if the first portion205ahas a tensile stress, then the stress-compensating layer220will be deposited to have a compressive stress. On the other hand, if the first portion205ahas a compressive stress, then the stress-compensating layer220will be deposited to have a tensile stress. Conventional processes may be used to deposit the stress-compensating layer220. In one advantageous embodiment, a sputtering process is used to deposit this layer. For example, a titanium target may be used, and an inert gas, such as Argon, may be flowed with nitrogen to form a TiN layer. An example of a flow rate for the Argon may range from about 5 sccm to about 30 sccm. The flow rates for the nitrogen may also be from about 5 sccm to about 30 sccm. Further examples of one embodiment include conducting the sputter process at a pressure ranging from about 2500 mTorr to about 8500 mTorr and at a power ranging from about 2000 watts to about 8000 watts. These deposition parameters can result in a stress-compensating film where the stress ranges from about 1E10 Pascals to about 3E10 Pascals. Moreover, those who are skilled in the art will understand how to vary the deposition parameters to achieve a film having either a compressive stress or tensile stress associated with it.

The presence of the stress-compensating layer220provides advantages over prior art processes and devices. For example, it has been found with the invention that the counter stress provided by the stress-compensating layer220significantly reduces the number of metal defects that can form when a single thick metal layer is deposited. As such, with implementation of the invention, product reliability and yield can be increased. In addition, because the semiconductor device100is moved from the chamber used to deposit the metal layer205to the chamber used to deposit the stress-compensating layer220, the first portion205ahas an opportunity to inherently cool down, which also aides in the reduction of metal defect formation.

InFIG. 2C, a second portion205bof the metal layer205is deposited over the stress-compensating layer220. In an advantageous embodiment, the second portion205bhas the same metallic or metallic alloy composition as the first portion205aand the same processes may also be used to deposit the second portion205b. In such instances, the second portion205bmay also have the same type of stress215associated with it as is associated with the first portion205a, or alternatively, it may have an opposite stress associated with it. Due to the presence of the underlying stress-compensating layer220, it is believed that the stress225that is imparted to the first portion205amay also be imparted to the second portion205b. Regarding the materials, other embodiments do not preclude the use of different materials in forming the second portion205b.

In the embodiment shown inFIG. 2C, the deposition of the second portion205bcompletes the total thickness of the metal layer205, and in an advantageous embodiment, the thickness of the second portion205bwill be approximately the same as the first portion205a. For example, if the targeted metal thickness is of the metal layer205is 1.4 microns, the first and second portions205aand205bwill each have a thickness of approximately 0.70 microns. It should be understood, however, that the thicknesses of the first and second portions205aand205bneed not be the same; one may be thicker than the other and still be within the scope of the invention. However, their individual thicknesses will total the targeted thickness of the metal layer205.

Upon the completion of the deposition of metal layer205and the stress-compensating layer220, a photoresist layer230is deposited and patterned as shown inFIG. 2D, and a conventional etch may be conducted to form the semiconductor component235as shown inFIG. 2E. As mentioned above, in one embodiment, the semiconductor component235may be an inductor.

FIG. 3Aillustrates another embodiment of the semiconductor component300, as provided by the invention, that may be employed in the semiconductor device ofFIG. 1. In this embodiment, additional layers of metal and stress-compensating layers are deposited as described below. In achieving the structure shown inFIG. 3A, the same processes and materials used to construct the device shown inFIG. 2Cmay be used to build the structure illustrated inFIG. 3A. As such, the same reference numbers are used.

Following the deposition of the second portion205b, and unlike the embodiment ofFIG. 2C, the total thickness of the metal layer205has not yet been achieved. Thus, in the embodiment illustrated inFIG. 3B, another stress-compensating layer310is deposited over the second portion205b. This stress-compensating layer310may have the same composition as the stress-compensating layer220, and it may also have a thickness of about 50 nm. As such, the same processes and materials as those described above may be used to form the stress-compensating layer310. In an advantageous embodiment, the stress-compensating layer310will have a stress315associated with it that is opposite to the stress215as described above regarding the embodiment shown inFIG. 2C. This counter stress further reduces the formation of metal defects in the second portion205b.

Following the deposition of the stress-compensating layer310, a third portion205cof the metal layer205is deposited over the stress-compensating layer310. In this embodiment, the deposition of the third portion205ccompletes the total thickness of metal layer205. In an advantageous embodiment, the third portion205chas the same metallic or metallic alloy composition as the first and second portions205aand205band the same processes may also be used to deposit the third portion205c. In such instances, the third portion205cmay also have the same type of stress215associated with it as is associated with the first and second portions205aand205b. Due to the presence of the underlying stress-compensating layer310, it is believed that the stress315that is imparted to the second portion205bmay also be imparted to the third portion205c. Regarding the materials, other embodiments do not preclude the use of different materials in forming the third portion205c.

In the embodiment shown inFIG. 3C, the deposition of the third portion205ccompletes the total thickness of the metal layer205, and in an advantageous embodiment, the thickness of the third portion205cwill be approximately the same as the thicknesses of the first and second portions205aand205b. For example, if the targeted metal thickness of the metal layer205is 1.45 microns, the first, second and third portions205a,205b, and205cwill each have a thickness of approximately 0.45 microns. It should be understood, however, that the thicknesses of the first, second, and third portions205a,205b, and205cneed not be the same; one may be thicker than the others or they may all have different thicknesses and still be within the scope of the invention. However, their individual thicknesses will total the targeted thickness of the metal layer205. Furthermore, in this as well as other embodiments, the various portions of the metal layer205may all have the same type of stress associated with each one, or the portions may be deposited in such a way such that the type of stress in each portion alternates with the other. Likewise, the stress-compenstating layer310located between each portion may also alternate with other stress-compensating layers. Thus, in certain embodiments, the overall stack may comprise layers that have alternating types of stress associated with them. Given the teachings herein, one who is skilled in the art would understand how to alternate the deposition parameters to achieve this type of alternating stress pattern.

Upon the completion of the deposition of metal layer205and the stress-compensating layers220and310, a photoresist layer315is deposited and patterned as shown inFIG. 3D, and a conventional etch may be conducted to form the semiconductor component320as shown inFIG. 3E. As mentioned above, in one embodiment, the semiconductor component320may be an inductor. While the above embodiments have described the metal layer being segmented into only two or three layers with intervening stress-compensating layers located between them, it is readily recognized that the invention may be used to segment the metal layer into any number of segments with a stress-compensating layer being located between each pair of segments.

Turning briefly toFIG. 4, there is illustrated a partial view of an IC400that comprises a semiconductor component410, which may be any of the above-discussed embodiment, and a conventional transistor structure415as the one discussed above regardingFIG. 1. The semiconductor component may be any of the embodiments as discussed above and as illustrated inFIG. 1,2F, or3F. The semiconductor component410is electrically connected to the underlying transistor structure415by conventional structures, the details of which are not shown. It should also be understood that those who are skilled in the art would understand how to complete the IC400to form an operative IC.

By segmenting a thick metal layer and placing stress-reducing layers between those segments, the invention provides both a process and device that incurs fewer metal defects in the thick metal layer than the conventional processes and devices that are discussed above. As a result, product yields and product reliability are increased.