Display device

According to one embodiment, a display device including an insulating substrate, a first gate driver, a first gate line and a conductive material layer is provided. The first gate line has a first end connected to the first gate driver and a second end opposite to the first end, and extends in a first direction. The conductive material layer is located between the insulating substrate and the first gate line, overlaps the first gate line, and extends in the first direction. In the display device, the second end of the first gate line is electrically connected to the conductive material layer.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is based upon and claims the benefit of priority from Japanese Patent Application No. 2017-008619, filed Jan. 20, 2017, the entire contents of which are incorporated herein by reference.

FIELD

BACKGROUND

In liquid crystal display devices used in smartphones, tablet computers, etc., there has been demand for narrower frames. Therefore, if circuits such as a gate driver are built in a display panel, the built-in circuits usually adopt a one-side drive/one-side power supply method.

In a transmissive liquid crystal display device, to prevent deterioration of a switching element and leak current, a light-shielding layer serving as a shield against light from a backlight is provided in some cases. It is known that, to prevent the light-shielding layer from becoming electrically floating, the light-shielding layer is electrically connected to a gate electrode of the switching element, for example.

DETAILED DESCRIPTION

In general, according to one embodiment, a display device including an insulating substrate, a first gate driver, a first gate line and a conductive material layer is provided. The first gate line has a first end connected to the first gate driver and a second end opposite to the first end, and extends in a first direction. The conductive material layer is located between the insulating substrate and the first gate line, overlaps the first gate line, and extends in the first direction. In the display device, the second end of the first gate line is electrically connected to the conductive material layer.

Embodiments will be described hereinafter with reference to the accompanying drawings. Incidentally, the disclosure is merely an example, and proper changes within the spirit of the invention, which are easily conceivable by a skilled person, are included in the scope of the invention as a matter of course. In addition, in some cases, in order to make the description clearer, the widths, thicknesses, shapes, etc., of the respective parts are schematically illustrated in the drawings, compared to the actual modes. However, the schematic illustration is merely an example, and adds no restrictions to the interpretation of the invention. Besides, in the specification and drawings, the structural elements having functions, which are identical or similar to the functions of the structural elements described in connection with preceding drawings, are denoted by like reference numerals, and an overlapping detailed description is omitted unless otherwise necessary.

FIG. 1shows the structure of a display device DSP of the present embodiment. A first direction X and a second direction Y shown in the drawing cross each other. For example, the first direction X and the second direction Y orthogonally cross each other, but the first direction X and the second direction Y may cross each other at an angle other than an angle of 90 degrees.

In the present embodiment, a liquid crystal display device will be described as an example of the display device. The main structure disclosed in the present embodiment is also applicable to various display devices such as a self-luminous display device having an organic electroluminescent display element, etc., an electronic paper-type display device having an electrophoretic element, etc., a display device adopting a micro-electromechanical system (MEMS), and an electrochromic display device.

The display device DSP includes a display panel PNL, a driver IC chip1which drives the display panel PNL, etc. The display panel PNL is a liquid crystal display panel, for example, and includes a first substrate SUB1, a second substrate SUB2, a sealant SE, a peripheral light-shielding layer BMA and a liquid crystal layer (liquid crystal layer LC which will be described later). The second substrate SUB2is opposed to the first substrate SUB1. The sealant SE is provided in a region shown by rising diagonal lines, and attaches the first substrate SUB1and the second substrate SUB2to each other. The peripheral light-shielding layer BMA is provided in a region shown by falling diagonal lines, and is formed of the same material as that of a light-shielding layer BM which will be described later. The display panel PNL includes a display area DA which displays an image, and a non-display area NDA which has the shape of a frame and surrounds the display area DA. In the present embodiment, the display area DA is a region enclosed in the peripheral light-shielding layer BMA, and the non-display area NDA is a region in which the peripheral light-shielding layer MBA is provided.

The driver IC chip1is located in the non-display area NDA. In the example illustrated, the driver IC chip1is provided in a mounting portion MT of the first substrate SUB1which extends beyond the second substrate SUB2. For example, a display driver which outputs a signal necessary for image display is incorporated in the driver IC chip1. The display driver here includes at least part of a source driver SD, a gate driver GD and a common electrode driver circuit CD which will be described later. The driver IC chip1is not limited to the example illustrated but may be provided on a flexible printed circuit board which is separately connected to the display panel PNL.

The display panel PNL of the present embodiment may be any one of a transmissive display panel having a transmissive display function of displaying an image by selectively transmitting light from a back surface side of the first substrate SUB1, a reflective display panel having a reflective display function of displaying an image by selectively reflecting light from a front surface side of the second substrate SUB2, and a transflective display panel having the transmissive display function and the reflective display function.

Further, although detailed description of the structure of the display panel PNL will be omitted here, the display panel PNL may have a structure conforming to any one of a display mode using a lateral electric field along an X-Y plane or a main surface of a substrate, a display mode using a longitudinal electric field along a normal of the X-Y plane, and a display mode using an oblique electric field which is oblique with the X-Y plane. Still further, the display panel PNL may have a structure conforming to a display mode using an arbitrary combination of the longitudinal electric field, the lateral electric field and the oblique electric field.

FIG. 2is a diagram showing the basic structure and the equivalent circuit of the display panel PNL shown inFIG. 1. The display panel PNL includes a plurality of pixels PX in the display area DA. The pixels PX are arranged in a matrix. Further, the display panel PNL includes a plurality of gate lines G (G1to Gn), a plurality of source lines S (S1to Sm), a common electrode CE, etc., in the display area DA. The gate lines G extend in the first direction X and are arranged in the second direction Y. The source lines S extend in the second direction Y and are arranged in the first direction X. The gate lines G and the source lines S are not necessarily extended linearly but may be partially bent. The common electrode CE is provided over the pixels PX.

The display panel PNL includes gate drivers GD1and GD2, and a source driver SD in the non-display area NDA. The gate driver (first gate driver) GD1and the gate driver (second gate driver) GD2face each other across the display area DA in the first direction X. The gate lines G are connected to one of the gate drivers GD1and GD2. In the example illustrated, the odd-numbered gate lines G1, G3, . . . are connected to the gate driver GD1. The even-numbered gate lines G2, G4, . . . are connected to the gate driver GD2. The source lines S are connected to the source driver SD. The common electrode CE is connected to the common electrode driver circuit CD. The source driver SD, the gate driver GD1and GD2and the common electrode driver CD may be formed on the first substrate SUB1or may be partially or entirely incorporated in the driver IC chip1shown inFIG. 1, in the non-display area NDA.

Each pixel PX includes a switching element SW, a pixel electrode PE, the common electrode CE, a liquid crystal layer LC, etc. The switching element SW is formed of a thin-film transistor (TFT), for example, and is electrically connected to the gate line G and the source line S. The gate line G is connected to the respective switching elements SW of the pixels PX arranged in the first direction X. The source line S is connected to the respective switching elements SW of the pixels PX arranged in the second direction Y. The pixel electrode PE is electrically connected to the switching element SW. Each pixel electrode PE is opposed to the common electrode CE and drives the liquid crystal layer LC by an electric field formed between the pixel electrode PE and the common electrode CE. Storage capacitance CS is formed between an electrode having the same potential as that of the common electrode CE and an electrode having the same potential as that of the pixel electrode PE, for example. The gate line G, the source line S, the switching element SW, the pixel electrode PE, the common electrode CE, etc., are provided in the first substrate SUB1shown inFIG. 1.

FIG. 3is a plan view of a structural example of the first substrate SUB1. The first substrate SUB1is one of the substrates which constitute the display panel PNL. The example illustrated corresponds to an example adopting a fringe field switching (FFS) mode, which is one of the display modes using the lateral electric field.

The first substrate SUB1is located over the display area DA and the non-display area NDA. The first substrate SUB1includes light-shielding layers LS (LS1, LS2and LS3), relay electrodes PE1, relay electrodes RE2(RE21, RE22and RE23), etc., in addition to the gate drivers GD1and GD2, the gate lines G (G1, G2and G3), the source lines S (S1, S2, Sm−1 and Sm), the switching elements SW and the pixel electrodes PE.

The gate drivers GD1and GD2are arranged in the non-display area NDA of the first substrate SUB1. In the example illustrated, the non-display area NDA has a first non-display area NDA1adjacent to the left side of the display area DA and a second non-display area NDA2adjacent to the right side of the display area DA. The gate driver GD1is located in the first non-display area NDA1, and the gate driver GD2is located in the second non-display area NDA2. That is, the gate driver GD1and the gate driver GD2face each other across the display area DA in the first direction X. In the example illustrated, the gate driver GD1and the gate driver GD2are arranged in regions which have length in the second direction Y and width in the first direction X.

The source lines S are formed in a strip shape having a substantially constant width, and cross the gate lines G, respectively, in the display area DA. All the source lines S are located between the gate driver GD1and the gate driver GD2. The source line S1corresponds to the source line closest to the first non-display area NDA1in the display area DA, and is located at the left edge of the display area DA in the drawing. The source line Sm corresponds to the source line closest to the second non-display area NDA2in the display area DA, and is located at the right edge of the display area DA in the drawing.

The switching elements SW are formed between the adjacent source lines S. For example, the switching element SW is arranged in the vicinity of the gate line G1between the source line Sm−1 and the source line Sm. The switching element SW is connected to the source line Sm, and is also electrically connected to the pixel electrode PE via the relay electrode RE1. The structure of the pixel PX including the switching element SW will be described later.

The gate lines G are formed in a strip shape having a substantially constant width, and are drawn to the first non-display area NDA1and the second non-display area NDA2. That is, both ends of the gate lines G in the first direction X are located in the non-display area NDA. More specifically, one ends EG11and EG31of the gate lines G1and G3are connected to the gate driver GD1in the first non-display area NDA1. The other ends EG12and EG32of the gate lines G1and G3are located in the second non-display area NDA2and are spaced apart from the gate driver GD2. In the example illustrated, the other ends EG12and EG32are located between the source line Sm and the gate driver GD2. On the other hand, one end EG21of the gate line G2is located in the first non-display area NDA1and is spaced apart from the gate driver GD1. In the example illustrated, one end EG21is located between the source line S1and the gate driver GD1. The other end EG22of the gate line G2is connected to the gate driver GD2in the second non-display area NDA2.

Conductive material layers, for example, the light-shielding layers LS extend in the first direction X and overlap the gate lines G. The light-shielding layers LS, except ends thereof, are formed in a strip shape having a substantially constant width. The width here corresponds to width in the second direction Y. In the present embodiment, a length LLS of the light-shielding layer LS1in the first direction X is greater than a length LDA of the display area DA in the first direction X. For example, the length LLS is substantially equal to a length LG1of the gate line G1in the first direction X. Further, both ends of the light-shielding layers LS are located in the non-display area NDA. In the non-display area NDA, the light-shielding layer LS is connected to the gate driver connected to the corresponding gate line G and is electrically connected to the gate line G at the end opposite to the gate driver.

More specifically, one end EL11of the light-shielding layer LS1is connected to the gate driver GD1in the first non-display area NDA1. The other end EL12of the light-shielding layer LS1is located in the second non-display area NDA2and overlaps the end EG12. That is, the other end EL12is located between the source line Sm and the gate driver GD2and is spaced apart from the gate driver GD2. The light-shielding layer LS1is electrically connected to the other end EG12via the relay electrode RE21which overlaps the other end EL12and the other end EG12. Accordingly, the gate line C1and the light-shielding layer LS1are electrically connected to each other in the second non-display area NDA2.

On the other hand, one end EL21of the light-shielding layer LS2is located in the first non-display area NDA1and overlaps one end EG21. That is, one end EL21is located between the gate driver GD1and the source line S1and is spaced apart from the gate driver GD1. The other end EL22of the light-shielding layer LS2is connected to the gate driver GD2in the second non-display area NDA2. The light-shielding layer LS2is electrically connected to the gate line G2via the relay electrode RE22which overlaps one end EL21and one end EG21. The structure of the light-shielding layer LS3is the same as that of the light-shielding layer LS1, and thus detailed description thereof will be omitted.

In the present embodiment, one end EG11corresponds to the first end of the first gate line, and the other end EG12corresponds to the second end of the first gate line. One end EL11corresponds to the third end of the light-shielding layer, and the other end EL12corresponds to the fourth end of the light-shielding layer. One end EG21corresponds to the sixth end of the second gate line, and the other end EL22corresponds to the fifth end of the second gate line. Further, the relay electrode RE21corresponds to the first relay electrode, and the relay electrode RE22corresponds to the third relay electrode.

FIG. 4is a plan view of the structure of the pixel PX. This is a plan view of the first substrate SUB1.FIG. 4is an enlarged view of the vicinity of the pixel PX which is most distant from the gate driver GD1in the first direction X. The first substrate SUB1includes the common electrode, for example, but the illustration of the common electrode is omitted here.

The first substrate SUB1includes the gate line G1, the light-shielding layer LS1, the source lines Sm−1 and Sm, the switching element SW, the pixel electrode PE, the relay electrodes RE1and RE21, etc.

The gate line G1has a width WG1less than a width WLS of the light-shielding layer LS1and entirely overlaps the light-shielding layer LS1. In the example illustrated, the gate line G1is located in a substantially center of the light-shielding layer LS1.

The switching element SW is formed between the source line Sm−1 and the source line Sm. For example, the switching element SW is a single-gate thin-film transistor which is electrically connected to the source line Sm and the pixel electrode PE. The switching element SW includes a semiconductor layer SC, a gate electrode GE, the relay electrode RE1, etc.

The semiconductor layer SC is substantially L-shaped and has a first portion SC1and a second portion SC2. The first portion SC1extends in the second direction Y between the source line Sm−1 and the source line Sm, and crosses the gate line G1and the light-shielding layer SL1. The gate electrode GE corresponds to a portion of the gate line G1crossing the first portion SC1. One end of the first portion SC1overlaps the pixel electrode PE and the relay electrode RE1. The relay electrode RE1is electrically connected to the first portion SC1in a contact hole CH1formed in a region overlapping the first portion SC1. The second portion SC2extends from the other end of the first portion SC1to the source line Sm in the first direction X and crosses the source line Sm. The second portion SC2is electrically connected to the source line Sm in a contact hole CH2formed in a region overlapping the source line Sm. The first portion SC1and the second portion SC2are linearly formed in the example illustrated but may be partially bent.

The pixel electrode PE is located between the source line Sm−1 and the source line Sm. The pixel electrode PE includes an electrode portion PA and a contact portion PB. The electrode portion PA and the contact portion PB are integrally or continuously formed with each other and are electrically connected to each other. The contact portion PB is closer to the gate line G1than the electrode portion PA. That is, the contact portion PB is arranged in a location overlapping the relay electrode RE1and is electrically connected to the relay electrode RE1. Accordingly, the pixel electrode PE is electrically connected to the switching element SW. The electrode portion PA extends from the contact portion PB in the second direction Y. In the example illustrated, the pixel electrode PE has three electrode portions PA. The three electrode portions PA are arranged in the first direction X at intervals and are formed in a strip shape having a substantially constant width in the first direction X. The shape of the pixel electrode PE is not limited to the example illustrated but may be appropriately changed in accordance with the shape of the pixel PX, etc. For example, the pixel electrode PE may extend in an oblique direction crossing the first direction X and the second direction Y, and the electrode portion PA may extend in the oblique direction.

Next, the other end EL12of the light-shielding layer LS1and the other end EG12of the gate line G1will be described.

In the present embodiment, the other end EL12corresponds to a region of the light-shielding layer LS1which nearly overlaps the relay electrode RE21. Further, the other end EG12corresponds to a region of the gate line G1which nearly overlaps the relay electrode RE21. In the example illustrated, the other end EL12has the shape of a rectangle, and the sides of the rectangle in the second direction Y are longer than the sides of the rectangle in the first direction X. For example, a width (first width) WEL of the other end EL12is about twice the width (second width) WLS. The width here corresponds to width in the second direction Y.

The relay electrode RE21overlaps the other end EL12and the other end EG12. More specifically, the relay electrode RE21has a region which overlaps both the other end EL12and the other end EG12, and a region which overlaps the other end EL12but does not overlap the other end EG12. In the example illustrated, the relay electrode RE21has the same shape as that of the other end EL12, and the entire relay electrode RE21is located within the region of the other end EL12. A contact hole CH3and a contact hole CH4are formed in a region in which the relay electrode RE21is provided. The contact holes CH3and CH4are arranged in the second direction Y. The contact hole CH3is located in a region in which the relay electrode RE21and the gate line G1overlap each other. Within the region in which the relay electrode RE21and the other end EL12overlap each other, the contact hole CH4is located in a region which does not overlap the gate line G1.

The relay electrode21is connected to the gate line G1in the contact hole CH3. Further, the relay electrode RE21is connected to the light-shielding layer LS1in the contact hole CH4. In this way, the light-shielding layer LS1and the gate line G1are electrically connected to each other via the relay electrode RE21in the non-display area NDA. In the example illustrated, the contact holes CH3and CH4have rectangular shapes having substantially equal sizes. That is, the area of a region in which the relay electrode RE21and the gate line G1contact each other is substantially equal to the area of a region in which the relay electrode RE21and the light-shielding layer LS1contact each other. However, the sizes and shapes of the contact holes CH3and CH4may be appropriately changed. Further, the contact hole CH3and the contact hole CH4may be arranged in a direction crossing the second direction Y.

FIG. 5is a sectional view of part of the display panel PNL taken along line A-B shown inFIG. 4. InFIG. 5, a direction from the first substrate SUB1to the second substrate SUB2is defined as a third direction Z. Further, the third direction Z is referred to as up or above, and the opposite direction to the third direction Z is referred to as down or below.

The first substrate SUB1includes a first insulating substrate10, an insulating film11, an insulating film12, an insulating film13, an insulating film14, an insulating film15, an insulating film16, the light-shielding layer LS1, the semiconductor layer SC, metal protection films M1and M2, the gate electrode GE (gate line G1), the source line Sm, the relay electrode RE1, the common electrode CE, the pixel electrode PE, a first alignment film AL1, etc.

The first insulating substrate10is a light transmissive substrate such as a glass substrate or a resin substrate. The insulating film11is formed on the first insulating substrate10. The light-shielding layer LS1is located on the insulating film11. The light shielding layer LS1serves as a shield against light transmitted to the semiconductor layer SC from a backlight unit BL which will be described later. The light-shielding layer LS1is formed of a metal material such as titanium (Ti), for example. The insulating film12covers the light-shielding layer LS1and is also formed on the insulating film11. The semiconductor layer SC is located on the insulating film12and partially overlaps the light-shielding layer LS1. The semiconductor layer SC is formed of a transparent amorphous oxide semiconductor (TAOS), for example, but the semiconductor layer SC may be formed of polycrystalline silicon or amorphous silicon. The metal protection films M1and M2are spaced apart from each other and contact on an upper surface SA of the semiconductor layer SC. The insulating film13covers the semiconductor layer SC and the metal protection films M1and M2.

The gate electrode GE, which is part of the gate line G1, is located on the insulating film13and is covered with the insulating film14. The gate electrode GE is located directly above a region of the semiconductor layer SC which is opposed to the light-shielding layer LS1. The gate line G1and the metal protection films M1and M2are formed of a metal material such as aluminum (Al), titanium (Ti), silver (Ag), molybdenum (Mo), tungsten (W), copper (Cu) or chromium (Cr), an alloy of these metal materials, etc., and may have a single layer structure or a multi-layer structure.

The source line Sm and the relay electrode RE1are located on the insulating film14and are covered with the insulating film15. The source line Sm and the relay electrode RE1are formed of the same material and may be formed of the above-described metal material. The source line Sm contacts the metal protection film M1in the contact hole CH2which penetrates the insulating film13and the insulating film14. The relay electrode RE1contacts the metal protection film M2in the contact hole CH1which penetrates the insulating film13and the insulating film14. That is, the metal protection film M1is located between the semiconductor layer SC and the source line Sm, and the metal protection film M2is located between the semiconductor layer SC and the relay electrode RE1.

The common electrode CE is located on the insulating film15and is covered with the insulating film16. The pixel electrode PE is located on the insulating film16and is covered with the first alignment film AL1. Part of the pixel electrode PE is opposed to the common electrode CE via the insulating film16. The common electrode CE and the pixel electrode PE are formed of a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO). In a location overlapping an opening of the common electrode CE, the pixel electrode PE contacts the relay electrode RE1in a contact hole CH6which penetrates the insulating film15and the insulating film16. In the example illustrated, the contact hole CH6is formed directly above the contact hole CH1. The insulating film11, the insulating film12, the insulating film13, the insulating film14and the insulating film16are an inorganic insulating film of silicon oxide, silicon nitride, silicon oxynitride, etc., and may have a single layer structure or a multi-layer structure. The insulating film15is an organic insulating film such as acrylic resin.

The second substrate SUB2includes a second substrate20, a light-shielding layer BM, a color filter CF, an overcoat layer OC, a second alignment film AL2, etc.

The light-shielding layer BM and the color filter CF are located on a side of the second insulating substrate20which is opposed to the first substrate SUB1. The light-shielding layer BM is formed of a black colored resin material, for example, and the pixels are partitioned by the light-shielding layer BM. For example, the light-shielding layer BM is arranged in a location opposed to the wires such as the source line Sm, the gate line G1, and the switching element SW. The color filter CF is arranged in a location opposed to the pixel electrode PE and partially overlaps the light-shielding layer BM. The overcoat layer OC covers the color filter CF. The second alignment film AL2covers the overcoat layer OC.

The color filter CF may be arranged in the first substrate SUB1. The light-shielding layer BM may be arranged between the color filter CF and the overcoat layer OC or between the overcoat layer OC and the second alignment film AL2. Further, a pixel which displays white may be added, and in this case, a white color filter may be arranged or an uncolored resin material may be arranged in the white pixel, or the overcoat layer OC may be arranged without any color filter.

The first substrate SUB1and the second substrate SUB2are arranged such that the first alignment film AL1and the second alignment film AL2are opposed to each other. A predetermined cell gap is formed between the first alignment film AL1and the second alignment film AL2. The cell gap is 2 to 5 μm, for example. The first substrate SUB1and the second substrate SUB2are attached to each other by a sealant with the predetermined cell gap formed.

The liquid crystal layer LC is located between the first substrate SUB1and the second substrate SUB2and is held between the first alignment film AL1and the second alignment film AL2. The liquid crystal layer LC includes liquid crystal molecules. The liquid crystal layer LC is formed of a liquid crystal material having positive dielectric anisotropy or a liquid crystal material having negative dielectric anisotropy.

With respect to the display panel PNL having the above-described structure, a first optical element OD1including a first polarizer PL1is arranged below the first substrate SUB1. Further, a second optical element OD2including a second polarizer PL2is arranged above the second substrate SUB2. For example, the first polarizer PL1and the second polarizer PL2are arranged such that absorption axes thereof orthogonally cross each other in an X-Y plane. The first optical element OD1and the second optical element OD2may include a retardation film such as a quarter-wave plate or a half-wave plate, a scattering layer, an antireflective layer, etc., as needed.

In this structural example, the liquid crystal molecules included in the liquid crystal layer LC are initially aligned in a predetermined direction between the first alignment direction AL1and the second alignment film AL2in an off state in which an electric field is not formed between the pixel electrode PE and the common electrode CE. In the off state, the light emitted from the backlight unit BL toward the display panel PNL is absorbed by the first optical element OD1and the second optical element OD2, and the display becomes dark. On the other hand, in an on state in which an electric field is formed between the pixel electrode PE and the common electrode CE, the liquid crystal molecules are aligned in a direction different from the initial alignment direction, and the alignment direction is controlled by the electric field. In the on state, part of the light from the backlight unit BL is transmitted through the first optical element OD1and the second optical element OD2, and the display becomes bright.

FIG. 6is a sectional view of part of the display panel PNL taken along line C-D shown inFIG. 4.FIG. 6only shows the main portions of the first substrate SUB1.

The other end EL12has a region A extending beyond the other end EG12in the second direction Y. The relay electrode RE21is located on the insulating film14and overlaps the region A and the other end EG12. In other words, the gate line G1is located between the relay electrode RE21and the light-shielding layer LS1but is not interposed between the region A and the relay electrode RE21. The relay electrode RE21can be formed of the same material in the same manufacturing process together with the source line Sm and the relay electrode RE1shown inFIG. 5.

The contact hole CH3is formed directly above the other end EG12and penetrates the insulating film14. The contact hole CH4is formed directly above the region A and penetrates the insulating film14, the insulating film13and the insulating film12. The relay electrode RE21contacts an upper surface EGT of the other end EG12in the contact hole CH3and contacts an upper surface ELT of the other end EL12in the contact hole CH4. In this way, the light-shielding layer LS1and the gate line G1are electrically connected to each other. In the example illustrated, a first contact portion C1in which the relay electrode RE21and the light-shielding layer LS1contact each other and a second contact portion C2in which the relay electrode RE21and the gate line G1contact each other are arranged in the second direction Y.

In the present embodiment, the insulating film12corresponds to the first insulating film, the insulating film13corresponds to the second insulating film, and the insulating film14corresponds to the third insulating film. The contact hole CH4corresponds to the first through hole which penetrates the third insulating film, the second insulating film and the first insulating film, and the contact hole CH3corresponds to the second through hole which penetrates the third insulating film.

According to the present embodiment, the light-shielding layer LS overlapping the gate line G is provided. Therefore, it is possible to prevent the property deterioration and improve the reliability of the switching element SW including the semiconductor layer SC formed of an oxide semiconductor layer.

The light-shielding layer LS and the gate line G are electrically connected to each other. Therefore, it is possible to prevent the light-shielding layer LS from becoming electrically floating. Further, the light-shielding layer LS and the gate line G are connected to each other in the non-display area NDA. Therefore, as compared to a case where the light-shielding layer LS and the gate line G are electrically connected to each other in each pixel PX, for example, the floating of the light-shielding layer LS can be prevented without reducing the aperture ratio.

Further, the light-shielding layer LS is electrically connected to the gate line G at both ends. Therefore, as compared to a case where the light-shielding layer LS is connected to the gate line G at only one end, the time taken for the potential of the light-shielding layer LS to become the same as that of the gate line G can be shortened. That is, even if the light-shielding layer LS and the gate line G have different time constants due to differences in material, width, film thickness, etc., the influence of the time constant difference can be suppressed. Accordingly, degradation in display quality can be prevented.

Still further, the contact holes CH3and CH4which overlap the relay electrode RE21are arranged in the second direction Y. Therefore, the width of the non-display area NDA in the first direction X can be reduced as compared to a case where the contact holes CH3and CH4are arranged in the first direction X, for example. Still further, as shown inFIG. 3, for example, when the gate lines G arranged in the second direction Y are connected to the gate driver GD1and the gate driver GD2, alternately, the width of the first non-display area NDA1and the width of the second non-display area NDA2can be uniformed, and this is suitable for narrowing the frame.

Next, another structural example will be described.

A structural example shown inFIG. 7differs from the structural example shown inFIG. 3in that both ends of the light-shielding layer LS is connected to the gate line G via the relay electrode RE2.

One end EL11of the light-shielding layer LS1is located in the first non-display area NDA1but is spaced apart from the first driver GD1. In the example illustrated, one end EL11is located between the gate driver GD1and the source line S1. The light-shielding layer LS1is connected to the gate line G1via the relay electrode RE21aoverlapping one end EL11and the relay electrode RE21boverlapping the other end EL12.

Further, the other end EL22of the light-shielding layer LS2is located in the second non-display area NDA2but is spaced apart from the gate driver GD2. In the example illustrated, the other end EL22is located between the source line Sm and the gate driver GD2. The light-shielding layer LS2is connected to the gate line G2via the relay electrode RE22aoverlapping one end EL21and the relay electrode RE22boverlapping the other end EL22.

The structures of one end EL11and the other end EL22are the same as those of the other end EL12and one end EL21. In the present embodiment, the relay electrode RE21bcorresponds to the first relay electrode, and the relay electrode RE21acorresponds to the second relay electrode. The structure of the light-shielding layer LS3is the same as that of the light-shielding layer LS1, and thus detailed description thereof will be omitted. The same advantages as those of the structural example shown inFIG. 3can be obtained also in the present structural example.

A structural example shown inFIG. 8differs from the structural example shown inFIG. 3in that the first substrate SUB1has one gate driver GD.

In the example illustrated, the gate driver GD is provided in the first non-display area NDA1. One ends EG11, EG21and EG31and one ends EL11, EL21and EL31are connected to the gate driver GD in the first non-display area NDA1. The other ends EG12, EG22and EG32and the other ends EL12, EL22and EL32are located in the second non-display area NDA2. The light-shielding layers LS1, LS2and LS3are connected to the gate lines G1, G2and G3via the relay electrodes RE21, RE22and RE23overlapping the other ends EG12, EG22and EG32and the other ends EL12, EL22and EL32, respectively. One ends EL11, EL21and EL31may be connected to the gate lines G1, G2and G3via the relay electrodes RE21a, RE22aand RE23aas shown inFIG. 7.

The same advantages as those of the structural example shown inFIG. 3can be obtained also in the present structural example.

A structural example shown inFIG. 9differs from the structural example shown inFIG. 4in that the other end EG12and the other end EL12are connected to each other in one contact hole CH5(through hole).

The contact hole CH5is located within a region in which the relay electrode RE21is provided, and overlaps the other end EG12and the other end EL12. In the example illustrated, the contact hole CH5is located in a substantially center of the relay electrode RE21. In the contact hole CH5, the area of a region overlapping the other end EG12is substantially equal to the area of a region overlapping the other end EL12. The contact hole CH5has a rectangular shape in the example illustrated but may have another shape. Further, a width WEL′ of the other end EL12may be less than the width WEL shown inFIG. 4.

FIG. 10is a sectional view of part of the display panel PNL taken along line E-F shown inFIG. 9. The contact hole CH5penetrates the insulating film14, the insulating film13and the insulating film12. In the contact hole CH5, the relay electrode RE21contacts the insulating film14, the insulating film13and the insulating film12and also contacts the upper surface ELT. Further, the relay electrode RE21contacts the upper surface EGT and also contacts a side surface EGS of the other end EG12.

The same advantages as those of the structural example shown inFIG. 3can be obtained also in the present structural example. Further, according to the present structural example, the area of the relay electrode RE21can be reduced.

As described above, according to the present embodiment, a display device which can prevent degradation in display quality can be provided.