Semiconductor device

A semiconductor device includes a first gate line, a second gate line and a first bar-shaped contact structure. The first gate line has a first long axis extending along a first direction. The second gate line is parallel to the first gate line. The first bar-shaped contact structure has a second axis forming an angle substantially greater than 0° and less than 90° with the first long axis.

This application claims the benefit of People's Republic of China application Serial No. 201711047374.9, filed Oct. 31, 2017, the subject matter of which is incorporated herein by reference.

BACKGROUND

Technical Field

The disclosure relates in generally to a semiconductor device and more particularly to a semiconductor device having a gate contact structure.

Description of the Related Art

As the evolution of semiconductor process, a semiconductor integrated circuit (IC) with higher driving current and reaction speed as well as smaller critical size is required. In order to shrink the critical dimension (CD) of the semiconductor device and increase its reaction speed. A fin field effect transistor (fin field effect transistor, FinFET) technology has been applied to provide a semiconductor device with higher functional density, lower power consumption and improved gate control over the channel potential.

However, as the CD of the semiconductor device continue to shrink; the landing area of a contact structure that is used to provide an inter-layer connection in the semiconductor device is also shrank. The difference between an after-development-inspection (ADI) CD and an after-etching-inspection (AEI) CD during the process for fabrication the contact structure may be thus increased, and critical dimension uniformity (CDU) thereof can be deteriorated. This may cause connection failure between the gate of the FinFET and the contact structure; and the yield of the FinFET may be decreased significantly.

Therefore, there is a need of providing an improved semiconductor device to obviate the drawbacks encountered from the prior art.

SUMMARY

One aspect of the present disclosure is to provide a semiconductor device, wherein the semiconductor device includes a first gate line, a second gate line and a bar-shaped contact structure. The first gate line has a first long axis extending along a first direction. The second gate line is parallel to the first gate line. The bar-shaped contact structure has a second axis forming an angle substantially greater than 0° and less than 90° with the first long axis.

Another aspect of the present disclosure is to provide a semiconductor device, wherein the semiconductor device includes a semiconductor substrate, a first gate line, a second gate line and a bar-shaped contact structure. The first gate line is disposed on the substrate and has a first long axis extending along a first direction. The second gate line is disposed on the substrate and parallel to the first gate line. The bar-shaped contact structure is disposed on and electrically contacting with the first gate line and the second gate line, wherein the bar-shaped contact structure has a second axis forming an angle substantially greater than 0° and less than 90° with the first axis.

In accordance with the aforementioned embodiments of the present disclosure, a semiconductor device is provided in which a bar-shaped contact structure is applied electrically contacting to two parallel gate lines underlying thereof, wherein the bar-shaped contact structure has a long axis forming an angle greater than 0° and less than 90° with the long axis of the two parallel gate lines respectively. By this arrangement, the contacting area of the contact structure landing on the top surfaces of these two gate lines can be enlarged without increasing the pitch (width) of these two gate lines. As a result, the connection reliability between the bar-shaped contact structure and these two gate lines can be improved and the yield of the semiconductor device can be also increased.

DETAILED DESCRIPTION

The embodiments as illustrated below provide a semiconductor device to improve the reliability and the yield thereof which may be deteriorated by critical dimension shrinkage in prior art. The present disclosure will now be described more specifically with reference to the following embodiments illustrating the structure and arrangements thereof.

It is to be noted that the following descriptions of preferred embodiments of this disclosure are presented herein for purpose of illustration and description only. It is not intended to be exhaustive or to be limited to the precise form disclosed. Also, it is also important to point out that there may be other features, elements, steps and parameters for implementing the embodiments of the present disclosure which are not specifically illustrated. Thus, the specification and the drawings are to be regard as an illustrative sense rather than a restrictive sense. Various modifications and similar arrangements may be provided by the persons skilled in the art within the spirit and scope of the present disclosure. In addition, the illustrations may not be necessarily drawn to scale, and the identical elements of the embodiments are designated with the same reference numerals.

FIG. 1is a top view illustrating a partial layout of a semiconductor device100in accordance with one embodiment of the present disclosure. The semiconductor device100includes a plurality of semiconductor fins (such as the semiconductor fins101A and101B), a plurality of gate lines (such as the gate lines102A,102B,102C and102D) and a plurality of bar-shaped contact structures103.

In some embodiments of the present disclosure, the gate lines102A,102B,102C and102D are parallel to each other and intersect with the semiconductor fins101A and101B respectively. In the present embodiment, each of the gate lines102A,102B,102C and102D (e.g. the gate line102A) has a long axis K1extending along a first direction (e.g. along the extending direction of Y axis). The semiconductor fin101A (or101B) has a long axis K2extending along the extending direction of X axis (i.e. a direction perpendicular to the first direction). In other words, each of the gate lines102A,102B,102C or102D vertically comes across over the semiconductor fins101A and101B, and extends beyond the two sides101A1and101A2of the semiconductor fin101A and the two sides101B1and101B2of the semiconductor fins101B parallel to the long axis K2thereof.

However, it should be appreciated that, although the long axis K1of the gate lines102A,102B,102C and102D (e.g. the gate line102A) and the long axis K2of the semiconductor fins101A and101B (e.g. the semiconductor fin101A) as depicted inFIG. 1are perpendicular with each other; the arrangement of the gate lines102A,102B,102C and102D and the semiconductor fins101A and101B may not limited as this regard. In some other embodiments of the present disclosure, the long axis K1of the gate lines102A,102B,102C and102D (e.g. the gate line102A) and the long axis K2of the semiconductor fins101A and101B (e.g. the semiconductor fin101A) may rather form an angle greater than 0° and less than 90° (not shown).

The bar-shaped contact structures103are respectively disposed adjacent to the two sides101A1and101A2of the semiconductor fin101A and the two sides101B1and101B2of the semiconductor fins101B parallel to the long axis K2of the semiconductor fin101A, but not overlapped with the semiconductor fin101A and the semiconductor fins101B. Each of the bar-shaped contact structures103is disposed between two adjacent gate lines (such as the adjacent two gate lines102A and102B), and arranged corresponding two adjacent gate lines (102A and102B). In some embodiments of the preset disclosure, each of the bar-shaped contact structures103also has a long axis K3forms an angle θ less than 0° and less than 90° with the long axis K1of the two corresponding gate lines102A and102B. In the present embodiment, the angle θ formed by the long axis K3of each bar-shaped contact structures103and the long axis K1of the two corresponding gate lines102A and102B can be about 60°.

Although the long axis K3of the bar-shaped contact structures103, in the present embodiment, are parallel with each other, but the arrangement of the bar-shaped contact structures103may not be limited to this regard. In some embodiments of the present disclosure, one of the bar-shaped contact structures103may have a long axis forming an non-straight angle (which is not equal to 180° and 0°) with the long axis of another one of the bar-shaped contact structures103(not shown).

In some embodiments of the present disclosure, each of the bar-shaped contact structures103may at least partially cover on the two corresponding gate lines102A and102B. In the present embodiment, each of the bar-shaped contact structures103can thoroughly come across the two corresponding gate lines102A and102B. For example, the portion of the bar-shaped contact structures103overlapping with the gate line102A may have a lateral width W11measured along a direction perpendicular to the first direction (parallel to the extending direction of X axis) substantially equal to the length of a short axis S11of the gate line102A measured along the direction perpendicular to the first direction.

However, the overlapping of the bar-shaped contact structures103and the two corresponding gate lines102A and102B may not limited to this regard.FIG. 2Ais a top view illustrating a partial layout of a semiconductor device200in accordance with another embodiment of the present disclosure; andFIG. 2Bis a cross-sectional view illustrating the structure of the semiconductor device200taken along the section line2B-2B′ depicted inFIG. 2A. The layout of the semiconductor device200is similar to that of the semiconductor device100except the arrangement of the bar-shaped contact structures203and the two corresponding gate lines102A and102B.

In the present embodiment, the portion of the bar-shaped contact structures203overlapping with the gate line102A may have a lateral width W21measured along a direction perpendicular to the first direction (parallel to the extending direction of X axis) substantially greater than half of the length of the short axis S11of the gate line102A measured along the direction perpendicular to the first direction; and the portion of the bar-shaped contact structures203overlapping with the gate line102B may have a lateral width W22measured along a direction perpendicular to the first direction (parallel to the extending direction of X axis) substantially greater than half of the length of the short axis S12of the gate line102B measured along the direction perpendicular to the first direction.

The method for fabricating the semiconductor device100may include steps as follows: A substrate10is firstly provided, and a plurality of semiconductor fins, such as the semiconductor fins101A and101B, are formed on the substrate10.FIG. 3Ais a top view illustrating the structure of a substrate10with a plurality of semiconductor fins101A and101B in accordance with one embodiment of the present disclosure;FIG. 3Bis a cross-sectional view illustrating the structure of the substrate10taken along the section line3B-3B′ depicted inFIG. 3A; andFIG. 3Cis a cross-sectional view illustrating the structure of the substrate taken along the section line3C-3C′ depicted inFIG. 3A.

In the present embodiment, the substrate10can be a silicon-containing substrate, such as a silicon wafer. Each of the semiconductor fins101A and101B can be mesa-stripes protruding form the top surface of the substrate10formed by an etching process. Each of the semiconductor fins101A and101B (e.g. the semiconductor fin101A) has a long axis K2extending along the extending direction of X axis (perpendicular to the first direction).

Next, a plurality of gate lines102A and102B are formed coming across over the semiconductor fins101A and101B.FIG. 4Ais a top view illustrating the results after a plurality of gate lines (such as the gate lines102aand102B) are formed on the structure depicted on theFIG. 3A;FIG. 4Bis a cross-sectional view illustrating the structure taken along the section line4B-4B′ depicted inFIG. 4A; andFIG. 4Cis a cross-sectional view illustrating the structure taken along the section line4C-4C′ depicted inFIG. 4A. In the present embodiment, the gate lines102aand102B may conformally come across over the semiconductor fins101A and101B; and each of the gate lines102aand102B (e.g. the gate line102a) has a long axis K1extending along the extending direction of Y axis (parallel to the first direction). In some embodiments of the present embodiments, the gate lines102aand102B may include metal material. For example, in the present embodiment, each of the gate lines102aand102B may include a high-k/metal gate. In detail, each of the gate lines102aand102B may include a gate spacer102s, a high dielectric constant material (high-k) layer102h, a work function layer102fand a metal gate102m. An insulation structure104, such as a shallow trench isolation (STI), may be formed between the two adjacent gate lines102aand102B.

A plurality of bar-shaped contact structures103are then provided.FIG. 5Ais a top view illustrating the results after a plurality of bar-shaped contact structures103are formed on the structure depicted on theFIG. 4A;FIG. 5Bis a cross-sectional view illustrating the structure taken along the section line5B-5B′ depicted inFIG. 5A; andFIG. 5Cis a cross-sectional view illustrating the structure of the taken along the section line5C-5C′ depicted inFIG. 5A. In some embodiments of the present disclosure, each of the bar-shaped contact structures103is formed on the insulation structure104disposed between the two adjacent gate lines102aand102B, extending beyond the insulation structure104to cover on a portion of the gate lines102aand102B, and electrically contacting with the gate lines102aand102B respectively. Each of the bar-shaped contact structures103has a long axis K3forming an angle θ less than 0° and less than 90° with the long axis K1of the two corresponding gate lines102A and102B. In the present embodiment, each of the bar-shaped contact structures103may at least partially cover on the two corresponding gate lines102A and102B.

Because the long axis K3of the bar-shaped contact structures103and the long axis K1of the two corresponding gate lines102A and102B form an angle θ less than 0° and less than 90° instead of a right angle. The overlapping area defined by the bar-shaped contact structures103and the two corresponding gate lines102A and102B can be enlarged to provide more space for forming an electrical contact respectively between the bar-shaped contact structures103and the two corresponding gate lines102A and102B, so as to expend the process window for forming the semiconductor device100without increase the pitch (width) of these two gate lines102A and102B. As a result, the yield and reliability of the semiconductor device100can be significantly improved.

In accordance with the aforementioned embodiments of the present disclosure, a semiconductor device is provided in which a bar-shaped contact structure is applied electrically contacting to two parallel gate lines underlying thereof, wherein the bar-shaped contact structure has a long axis forming an angle greater than 0° and less than 90° with the long axis of the two parallel gate lines respectively. By this arrangement, the contacting area of the contact structure landing on the top surfaces of these two gate lines can be enlarged without increasing the pitch (width) of these two gate lines. As a result, the connection reliability between the bar-shaped contact structure and these two gate lines can be improved and the yield of the semiconductor device can be also increased.