Semiconductor device

A power diode is disclosed wherein it is possible to lower on-voltage by expanding a conducting region at an on time. By applying negative voltage to a plate electrode when turning on a power diode, an inversion layer is formed in a front surface layer of an n drift region sandwiched between a p guard ring region and a p anode region, and the p guard ring region and p anode region are connected by the inversion layer, thereby causing one portion or all of the p guard ring region to function as an active region together with the anode region, and expanding an energization region, thus lowering on-voltage.

CROSS REFERENCE TO RELATED APPLICATION

The entire disclosure of the inventor's corresponding Japanese patent application, Serial No. JP PA 2013-015971, filed Jan. 30, 2013, is hereby incorporated by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a semiconductor device such as a power diode.

2. Description of the Background Art

FIGS. 8A and 8Bare configuration diagrams of a heretofore known power diode500, whereinFIG. 8Ais a main portion plan view, andFIG. 8Bis a main portion sectional view taken along the line X-X ofFIG. 8A. The power diode (hereafter, simply called the diode) is a vertical diode.

The diode500includes an active region11formed of a p anode region2, a p guard ring region3configuring a breakdown voltage structure16surrounding the active region11, and an insulating film4(for example, an oxide film) which is a protection film on the p guard ring region3. To describe in further detail, the diode500includes the p anode region2disposed in the front surface of an n semiconductor substrate1, the p guard ring region3disposed so as to surround the p anode region2, the insulating film4disposed on the p guard ring region3, an n cathode region6disposed on the rear surface of the n semiconductor substrate1, an anode electrode7disposed on the p anode region2, and a cathode electrode8on the n cathode region6. The p guard ring region3is configured of ring-shaped p+regions3a, and a region of the n semiconductor substrate1in which no diffusion regions are formed forms an n drift region1a. Herein, the diffusion regions refer to regions, such as the p anode region2, p+regions3a, and n cathode region6, which are formed by diffusing or injecting impurities from or into the surface of the n semiconductor substrate1.

When the diode500is put into an on state, holes are injected into the n drift region1afrom the p anode region2, and electrons are injected into the n drift region1afrom the n cathode region6so as to neutralize the holes. Conductivity modulation thus occurs in the n drift region1a, the on-resistance of the diode decreases, and on-voltage reaches a low value. Herein, a forward voltage drop of the diode is called on-voltage.

Also, when reverse current for cancelling forward current is caused to flow in order to put the diode500into an off state, the holes and electrons accumulated in the n drift region1aare swept to the outside, reverse recovery current flows, reverse voltage is applied to the diode500, and the diode500attains the off state.

Owing to the reverse voltage, a depletion layer expands from the pn junction of the p anode region2and n drift region1ato the n drift region1a. The depletion layer expanding laterally, on reaching the p guard ring region3, further expands while leaping over the p+regions3aconfiguring the p guard ring region3, one p+region3aafter another. The width of the depletion layer expanding laterally increases in this way, meaning that field intensity on the surface decreases, and breakdown voltage on the surface is stably maintained.

Also, in JP-A-6-77506, in a power pin diode wherein an anode region is formed of a Schottky barrier junction and a pn junction, a p floating region is provided in an active region so as to be adjacent to the p anode region, and a MOS gate structure is provided between the p anode region and p floating region. At an on time, negative voltage is applied to a MOS gate, thus forming a p channel region, and the p anode region and p floating region are connected to expand an energization region, thus lowering on-voltage. When turning off the power pin diode, the MOS gate is turned off prior thereto, the p floating region is separated from the p anode region, and subsequently, reverse current for cancelling forward current is caused to flow, thus turning off the diode. The forward current decreases owing to the reverse current, excess holes and electrons are swept to the outside, and thus decrease. By further causing reverse current to flow, reverse recovery current flows through the pn junction and Schottky barrier junction, and excess holes and electrons are extinguished, thus attaining an off state. As the reverse recovery current in the Schottky barrier junction is low, reverse recovery current and reverse recovery loss decrease as compared with a power pin diode wherein the whole of an active region is formed of a pn junction. In this way, JP-A-6-77506 discloses measures whereby it is possible to lower both on-voltage and reverse recovery loss in the power pin diode.

However, in the heretofore known diode500ofFIGS. 8A and 8B, in particular, when it is a high-voltage diode, the proportion of the p guard ring region3in a semiconductor chip increases, and when the area of the chip is the same, the active region11decreases in the same proportion, and the on-voltage rises.

Also, in JP-A-6-77506, as the floating region is provided in the active region, anode current flows to the floating region, which is not connected to an anode electrode, via the anode region. As the current flowing to the floating region flows to a conductivity modulation layer while flowing laterally through the floating region, the on-voltage rises as compared with when the whole of the active region is formed as the anode region. That is, with the structure of JP-A-6-77506, a conducting area decreases equivalently, as compared with when the whole of the active region is formed as the anode region.

Also, it is not described in JP-A-6-77506 that a guard ring provided in the outer peripheral portion of the active region is connected to the anode region, thus lowering the on-voltage.

SUMMARY OF THE INVENTION

An object of the invention is to solve the heretofore described problems, and thus provide a semiconductor device wherein it is possible to lower on-voltage by expanding a conducting region at an on time.

In order to achieve the object, according to a first aspect of the invention, a semiconductor device is configured including a second conductivity type first semiconductor region disposed in a front surface layer of a first conductivity type semiconductor substrate; a second conductivity type guard ring region which is a breakdown voltage structure disposed surrounding the first semiconductor region; an insulating film extending from on the end portion of the first semiconductor region to the guard ring region; a conductive film disposed on the semiconductor substrate sandwiched between the end portion of the first semiconductor region and the guard ring region, and on the guard ring region, via the insulating film; and a main electrode, disposed on the first semiconductor region, which is spaced away from the conductive film.

Also, according to a second aspect of the invention, in the semiconductor device of the first aspect of the invention, it is preferable to adopt a configuration wherein the guard ring region is formed of a plurality of second conductivity type second semiconductor regions of high concentration, the conductive film is divided into ring shapes, and the divided ring-shaped conductive films are disposed, via the insulating film, on the semiconductor substrate sandwiched between the first semiconductor region and guard ring region and on the semiconductor substrate sandwiched between the adjacent second semiconductor regions.

Also, according to a third aspect of the invention, in the semiconductor device of the first aspect or the second aspect of the invention, it is preferable that one portion of the semiconductor substrate forms the main electrode and a Schottky barrier junction.

Also, according to a fourth aspect of the invention, in the semiconductor device of any one of the first aspect to the third aspect of the invention, it is preferable that the first conductivity type semiconductor substrate is an n-type semiconductor substrate, the second conductivity type first semiconductor region is a p-type anode region, the second conductivity type guard ring region is a p-type guard ring region, the second conductivity type second semiconductor regions are p-type regions of high concentration, and the conductive film is a plate electrode.

Also, according to a fifth aspect of the invention, in the semiconductor device of any one of the first aspect to the fourth aspect of the invention, it is preferable that voltage at which inversion layers are formed in the front surface layer of the semiconductor substrate is applied to the conductive film at an on time, and voltage at which the inversion layers are extinguished is applied to the conductive film at an off time.

According to the invention, the guard ring region and anode region are connected by the inversion layers when turning on the semiconductor device, thereby expanding the conducting region, and it is thus possible to lower the on-voltage.

DETAILED DESCRIPTION OF THE INVENTION

Hereafter, a description will be given, referring to the attached drawings, of a preferred embodiment of a semiconductor device according to the invention. In the following description, a first conductivity type is an n type, and a second conductivity type is a p type. Also, a first semiconductor region is a p anode region, and a second semiconductor region is a p region of high concentration. Also, p denotes that the conductivity type is the p type, while n denotes that the conductivity type is the n type, and + superscripted to each of p and n denotes that the impurity concentration is high. Also, portions the same as heretofore known are given the same reference signs.

FIGS. 1A, 1B, and 2are configuration diagrams of a semiconductor device100according to Embodiment 1 of the invention, whereinFIG. 1Ais a main portion plan view,FIG. 1Bis a main portion sectional view taken along the line X-X ofFIG. 1A, andFIG. 2is an enlarged view of the F portion ofFIG. 1B. The semiconductor device100is a power diode and a vertical diode100a.

The diode100aincludes an active region11formed of a p anode region2, a p guard ring region3configuring a breakdown voltage structure16surrounding the active region11, and a plate electrode5disposed on the p guard ring region3via an insulating film4(for example, an oxide film). The plate electrode5is formed from, for example, polysilicon. Next, to describe in further detail, the diode100aincludes the p anode region2disposed in the front surface of an n semiconductor substrate1, the p guard ring region3disposed so as to surround the p anode region2, the plate electrode5disposed on the p guard ring region3via the insulating film4extending from on the end portion of the p anode region2, an n cathode region6disposed on the rear surface of the n semiconductor substrate1, an anode electrode7disposed on the p anode region2, and a cathode electrode8on the n cathode region6. The p guard ring region3is configured of ring-shaped p+regions3a, and a region of the n semiconductor substrate1in which no diffusion regions are formed forms an n drift region1a. The insulating film4and plate electrode5act respectively like the gate oxide film and gate electrode of a MOS gate structure.

Also, the diffusion depths of the p anode region2and p guard ring region3may be the same or may be different. The diffusion depth is determined by the optimal design of each of the p anode region2and p guard ring region3.

FIGS. 3A to 3C and 4are diagrams illustrating an operation of the diode100aofFIGS. 1A and 1B, whereinFIG. 3Ais a diagram when in an on state,FIG. 3Bis a diagram when in transition to an off state, andFIG. 3Cis a diagram when in the off state, whileFIG. 4is an operation waveform diagram of the diode100aofFIG. 1. The operation will be described usingFIGS. 3A to 3B and 4.

InFIGS. 3A and 4, when in the on state, at a point t1, negative voltage is applied to a cathode terminal K with an anode terminal A of the diode100aset at a reference potential (GND (a ground potential) or 0V), thereby forward biasing the diode100a, and negative voltage is applied to the plate electrode5with the potential of the anode terminal A as the reference. A point at which the diode100ais forward biased and a point at which the negative voltage is applied to the plate electrode5do not always have to be caused to coincide with each other. By applying the negative voltage to the plate electrode5, inversion layers12(p channel layers) are formed in front surface layers of the n drift region1asandwiched, one between the p anode region2and p guard ring region3, and the others between the adjacent p+regions3aconfiguring the p guard ring region3. The p anode region2and p guard ring region3are connected by the formation of the inversion layers12. Holes13are injected into the n drift region1afrom the p anode region2and p guard ring region3, and electrons14are injected into the n drift region1afrom the n cathode region6so as to neutralize the holes13. Conductivity modulation thus occurs in the n drift region1a, and on-voltage reaches a low value. In particular, as anode current IAflows through the p guard ring region3too, an energization region15expands, and the on-voltage drops significantly. The expanse of the energization region15leads to an equivalent expanse of the active region11. Some holes13are injected from the inversion layers12(p channel layers) too.

Next, inFIGS. 3B and 4, when in transition to the off state, at a point t2, the negative voltage being applied to the plate electrode5is changed to 0V or positive voltage, and the inversion layers12are extinguished, thus separating the p guard ring region3from the p anode region2. The p guard ring region3, by being separated from the p anode region2, acts as the original breakdown voltage structure16. Also, in this condition, as the energization region15is reduced to the same size as the active region11, the on-voltage rises to some extent. At a point t3, when reverse current IARfor cancelling forward current IAFflowing through the diode100ais caused to flow, the holes13and electrons14accumulated in the n drift region1aare swept to the outside, and the anode current IA(=IAF−IFR) decreases. When reverse recovery current IRRflows at a point t4, the accumulated holes13and electrons14flow to the p anode region2and n cathode region6respectively, and decrease. At a point at which the reverse recovery current IRRreaches a peak, reverse voltage VR(a cathode electrode K has positive voltage with the potential of an anode electrode A as the reference) is applied to the diode100a. Owing to the reverse voltage VR, a depletion layer17expands in the n drift region1a, and residual holes13and electrons14are swept out to the p anode region2and n cathode region6respectively, and thus extinguished. As a matter of course, recombination is also added to this.

Next, inFIGS. 3C and 4, the steady off state is reached at a point t5, and the expanse of the depletion layer17stops.

By applying the reverse voltage VR, the depletion layer17expands vertically and laterally from the pn junction of the p anode region2and n drift region1ainto the n drift region1a. A depletion layer17aexpanding laterally, on reaching the p+regions3aconfiguring the p guard ring region3, further expands laterally while leaping over one p+region3aafter another. The width of the depletion layer17aexpanding laterally increases in this way, meaning that field intensity on the surface decreases, and breakdown voltage on the surface is maintained stabilized.

By connecting the p guard ring region3to the p anode region2at an on time and separating the p guard ring region3from the p anode region2at an off time in this way, it is possible to lower the on-voltage without affecting the breakdown voltage.

Also, the voltage applied to the plate electrode5is switched to 0V or the positive voltage via a plate terminal G prior to a transition to the off state, and subsequently, a transition is made to the off state, thereby enabling the on-voltage to have the same level as the reverse recovery current IRRwhen the anode current IAis caused to flow through only the active region11. Because of this, with the diode100aof the invention, as it is possible to reduce the on-voltage without increasing the reverse recovery current IRR, it is possible to improve the trade-off between the on-voltage and reverse recovery current (reverse recovery loss).

In a high-voltage diode, there is high voltage in the vicinity of the lateral end portion of the depletion layer17(in the vicinity of the end portion of a chip) shown inFIG. 3C. Because of this, high voltage is applied to the insulating film4between the plate electrode5and the vicinity of the end portion (not shown) of the depletion layer17, meaning that there occurs a case in which the insulating film4is dielectrically broken down. In order to prevent this, it is often the case that the plate electrode5is not formed on the p+regions3ain the vicinity of the end portion of the depletion layer17. For example, it is good that the outer peripheral side end portion of the plate electrode5is positioned on the second and third p+regions3afrom the anode electrode7side, thus preventing the plate electrode5from being formed on the p+regions3ain the outer peripheral portion away from the second and third p+regions3a.

Also, the diode100aconfigures an inverter circuit or the like. For example, it is often the case that the diode100ais used as a free wheel diode combined with insulated gate bipolar transistors (IGBTs) or the like.

Working Example 1

Working Example 1 is an example wherein Embodiment 1 is applied to a diode with a breakdown voltage of 600V.FIG. 5shows a main portion sectional view of a semiconductor device200according to Working Example 1 of the invention. The semiconductor device200is a power diode which is formed of the active region11, formed of the p anode region2, and the breakdown voltage structure16surrounding the active region11.

The breakdown voltage structure16is formed of the p guard ring region3, formed of, for example, seven p+regions3a, a p-type channel stopper region9disposed in the outermost periphery away from the p guard ring region3, the insulating film4formed from an oxide film on the p guard ring region3and channel stopper region9, and the plate electrode5disposed via the insulating film4.

Herein, as high voltage is applied to the outer peripheral side insulating film4close to the channel stopper region9, as heretofore described, the outer peripheral side end portion of the plate electrode5is set to be on the third p+region3afrom the active region11. Also, the channel stopper region9is set to be of p type this time, but may be set to be of n type. Also, it is also possible to provide a field plate on the channel stopper region. Also, when raising the breakdown voltage, it is possible to respond thereto by increasing the number of p+regions3aand thus increasing the width of the p guard ring region3.

With this diode, it is confirmed that the diode is put into the on state by applying negative voltage to the cathode terminal K with the anode terminal A set at 0V, and furthermore, the on-voltage of the diode drops by applying negative voltage to the plate terminal G. Also, it can be confirmed that when switching the negative voltage of the cathode terminal K to positive voltage and thus putting the diode into the off state, the voltage applied to the plate terminal G is switched to positive voltage prior thereto, as a result of which the reverse recovery current IRRis of the same level as when the anode current IAis caused to flow through only the active region11.

Working Example 2

FIG. 6is a main portion sectional view of a semiconductor device300according to Working Example 2 of the invention. The difference of the semiconductor device300from the semiconductor device200ofFIG. 5is that the outer peripheral side of the insulating film4starting from the third p+region3afrom the active region11is increased in thickness. By adopting this kind of structure, it is possible to relax an electric field applied to the outer peripheral side insulating film4when the n drift region1a, when reverse biasing, rises in potential toward the outer peripheral side, and there occurs a possibility that the insulating film4may be broken down on the outer peripheral side of the plate electrode5. Also, the plate electrode5is extended from the active region11to the fifth p+region3a.

In Working Example 2, it can be confirmed that when voltage such that an inversion layer is formed in only a region in which the insulating film4is thin is applied to the plate terminal G, there are the same advantageous effects as in Working Example 1. Herein, the number of plate terminals G does not always have to be one, and it is also possible to divide the plate electrode5into a plurality of regions corresponding to the thickness of the insulating film4, and provide a plurality of plate terminals G, one in each of the plurality regions.

Working Example 3

FIG. 7is a main portion sectional view of a semiconductor device400according to Working Example 3 of the invention. The difference of the semiconductor device400from the semiconductor device200inFIG. 5is that the n drift region1aand anode region7in the active region11form a Schottky barrier junction18, and the Schottky barrier junction18is connected in parallel to a pn junction formed of the p anode region2and n drift region1a. In this case, there are the same advantageous effects as in Working Example 1, and it is possible to lower the reverse recovery current IRRby providing the Schottky barrier junction18. It is a matter of course that this structure can be applied to the semiconductor device300too.