Transistor structure having buried island regions

A semiconductor device such as a transistor includes a source region, a drain region, a semiconductor region, at least one island region and at least one gate region. The semiconductor region is located between the source region and the drain region. The island region is located in the semiconductor region. Each of the island regions differs from the semiconductor region in one or more characteristics selected from the group including resistivity, doping type, doping concentration, strain and material composition. The gate region is located between the source region and the drain region covering at least a portion of the island regions.

BACKGROUND

The ability to modify the threshold voltage in a transistor is highly desirable to design complex circuits. In Silicon MOSFETs, threshold voltage is commonly tuned by the doping density in the channel. However, the change in threshold voltage in unipolar transistors is not easy. For example, the threshold voltage of unipolar n-type transistors of III-V and III-Nitride semiconductors is typically negative. Therefore these transistors are depletion-mode or normally-on devices. Although enhancement-mode or normally-off transistors are highly desirable in many applications, it can be difficult to change the threshold voltage of these transistors to positive values.

This invention describes a new structure with island regions in the gate region of a transistor. This new structure is useful for tuning the threshold voltage.

SUMMARY

In accordance with one aspect of the disclosed subject matter, a transistor is provided that includes a source region, a drain region, a semiconductor region, at least one island region and at least one gate region. The semiconductor region is located between the source region and the drain region. The island region is located in the semiconductor region. Each of the island regions differs from the semiconductor region in one or more characteristics selected from the group including resistivity, doping type, doping concentration, strain and material composition. The gate region is located between the source region and the drain region covering at least a portion of the island regions.

In accordance with another aspect of the disclosed subject matter, a diode is provided that includes a cathode region, a semiconductor region, at least one island region and an anode region. The island region is located in the semiconductor region. Each of the island regions differs from the semiconductor region in one or more characteristics selected from the group including resistivity, doping type, doping concentration, strain and material composition. The anode region covers at least a portion of the island regions.

In accordance with yet another aspect of the disclosed subject matter, a method is provided for forming a transistor having a tailored threshold voltage. In accordance with the method, at least one island region is formed in a semiconductor region. The island region is formed so that it has at least one structural and/or compositional characteristic that differs from the at least one structural and/or compositional characteristic of the semiconductor region so that the transistor has the tailored threshold voltage. A conductive electrode is formed which covers at least a portion of the island regions.

DETAILED DESCRIPTION

In the following description, numerous specific details are set forth in order to provide a thorough understanding of exemplary embodiments or other examples described herein. However, it will be understood that these embodiments and examples may be practiced without the specific details. In other instances, well-known methods and procedures have not been described in detail, so as not to obscure the following description. Further, the embodiments disclosed are for exemplary purposes only and other embodiments may be employed in lieu of, or in combination with, the embodiments disclosed.

FIG. 1shows a plan view of one embodiment of a semiconductor device100constructed in accordance with the teachings presented herein.FIGS. 2 and 3show cross-sectional views of semiconductor device100taken along lines A-A′ and B-B′, respectively. InFIGS. 1-3and the FIGs. that follow like elements are denoted by like reference numerals. The semiconductor device100in this illustrative embodiment is depicted as a transistor that is operational in an enhancement mode or a depletion-mode. However, the teachings presented herein are equally applicable to other semiconductor devices such as diodes and various power and RF devices and is not limited to the particular devices described below.

Source and drain contacts140and150, respectively, are disposed in a recess extending through the barrier layer120and dielectric layer130and into the semiconductor layer110. In this way the source and drain contacts140and150contact the semiconductor layer110. A gate electrode160is disposed over the dielectric layer130and is located between the source and drain contacts140and150.

In some embodiments semiconductor layer110may be an epitaxial layer that is formed on the substrate105. In other embodiments the semiconductor layer110is bulk-like and need not be epitaxial. In these latter embodiments the semiconductor layer110may itself act as the substrate. As used herein, the term “substrate” refers to a free-standing, self-supporting structure and is not to be construed as a thin film layer that is formed on a free-standing, self-supporting structure.

A series of n (n≥1) island regions170are located in the semiconductor layer110between the source contact140and drain contact150. At least a portion of each island region170extends underneath or below the gate electrode160. More specifically, if the gate electrode160extends in the lateral direction (e.g., the x-direction inFIGS. 1-3), then in some embodiments each island region170extends in a direction perpendicular to the lateral direction (e.g., the z-direction inFIGS. 1-3). In some embodiments, the gate region (including the gate electrode160, dielectric layer130and possibly barrier layer120) covers the entirety of island regions170. In the embodiment shown inFIG. 2the island regions170extend through the barrier layer120and may contact the dielectric layer130.

The island regions170will have any suitable cross-section shape such as square, rectangular, hexagonal, circular and elliptical, for example. The width of each island region170in the lateral direction (e.g., along the x-direction inFIGS. 1-3) may vary, for instance, from 10 nm to the maximum width of the source and drain contacts140and150. The island regions170may all have the same or different widths. The distance between each island region170may vary from 0 to 100 μm, for example. Likewise, the length of each island region170may vary from 10 nm to the full distance between the source and drain contacts140and150. The island regions170may all have the same or different lengths. The depth of each “island region170may vary from 1 nm to 500 μm in some embodiments.

The semiconductor device100may be fabricated from many different material systems, including but not limited to Si-based systems and group III-V materials, in particular group III-nitride based material systems. Group-III nitrides include the semiconductor compounds formed between nitrogen and the elements in Group-III of the periodic table, usually aluminum (Al), gallium (Ga), and indium (In). This group also includes ternary and tertiary compounds such as AlGaN and AlInGaN. Some particular materials that may be suitable include, by way of example, Si, GaAs, Ga2O3, ZnO2, AlN, SiC, AlN, InN, GaN and diamond-based power and RF devices.

As previously mentioned, the semiconductor layer110may be a bulk semiconductor layer or it may comprise one or more sublayers formed on a substrate. By way of illustration, in some embodiments semiconductor layer110may be composed of InxAlyGazN (0≤x≤1, 0≤y≤1, 0≤z≤1, x+y+z=1), SiC, InxAlyGazAs (0≤x≤1, 0≤y≤1, 0≤z≤1, x+y+z=1), diamond, Si and/or oxide semiconductors such as Ga2O3, ZnO2, either by themselves or in combination with other materials and/or heterostructures.

Barrier layer120, which may comprise two or more sublayers, may comprise in some embodiments one or more layers of InxAlyGazN (0≤x≤1, 0≤y≤1, 0≤z≤1, x+y+z=1), SiC, InxAlyGazAs (0≤x≤1, 0≤y≤1, 0≤z≤1, x+y+z=1), diamond, SixNy, SiO2, Ga2O3, ZnO2and/or etch-stop layers formed by a combination of these materials. Dielectric layer130in some embodiments may comprise Al2O3, SixOy, SixNy, SixOyNz, Teflon, HfO2, or any other dielectric with a dielectric constant below 200.

The gate electrode160may include conductive material including, for instance, amorphous, poly-crystalline, or crystalline semiconductors, metals or conductive oxides or dielectrics or a combination of these materials.

The island regions170differs from the surrounding semiconductor layer110and the barrier layer120in any one or more ways. For example, the island regions may differ from semiconductor layer110and the barrier layer120by having different doping types, doping levels, resistivity or material compositions including crystalline, poly-crystalline, amorphous semiconductors or dielectric material or any combination of different doping types, doping levels, resistivity and material compositions. The island regions170may be formed by ion implantation or by etching into the semiconductor layer and re-deposition of materials or by any combination of these and other methods. In some embodiments the island regions170may contain voids, without solid phase materials. For instance, as will be shown below in connection withFIG. 4(b)the island regions170may each incorporate a portion of a trench that is lined with various layers that define the individual island regions170.

FIGS. 4a-4dshow alternative embodiments of the invention along the lateral direction taken along lines A-A′ inFIG. 1. While in the embodiment ofFIG. 2the top of the island regions170and the barrier layer120are in the same plane, in some embodiments such as shown inFIGS. 4aand 4bthey may be in different planes (i.e., different depths).

In the embodiment shown inFIG. 4(a), each island region170is formed at the bottom of a trench172located in the semiconductor layer110. The trenches172may be lined or filled first with the dielectric layer130followed by the gate electrode160. The barrier layer120may be located below the dielectric layer130between adjacent trenches172or between a trench and the source or drain contacts140and150.FIG. 5shows the embodiment ofFIG. 4(a)taken along lines B-B′ inFIG. 1. The gate electrode160may or may not fill the trench172.

In the embodiment shown inFIG. 4(b), each island region170, which is shown within the rectangle defined by the dashed lines, contains two layers175each lining a sidewall of trench172formed in the semiconductor layer110. The layers175are different from the surrounding semiconductor layer110and barrier layer120by having different doping types, doping levels, resistivity or material compositions including crystalline, poly-crystalline, amorphous semiconductors or dielectric material or any combination of the different doping types, doping levels, resistivity and material compositions.

In some embodiments such as shown inFIGS. 4(c) and 4(d), each of the island regions170includes multiple sub-layers176and178, where the sub-layer176and sub-layer178are different from the surrounding semiconductor layer and barrier layer in any one or more ways by having, for example, different doping types, doping levels, resistivity or material compositions including crystalline, poly-crystalline, amorphous semiconductors or dielectric material or any combination of the different doping types, doping levels, resistivity and material compositions. Similar toFIG. 4(b), island regions170inFIGS. 4(c) and 4(d)are shown within the rectangles defined by the dashed lines.

The interface between the sub-layer176and sub-layer178is along the horizontal direction as shown inFIG. 4(c)or along the vertical direction as shown inFIG. 4(d). In some embodiments, the interface between the sub-layers of island regions170is at an angle different from 0 and 90 degrees. In some embodiments, each of the sub-layers176and178may include additional sub-layers.

In some embodiments, a portion of the barrier layer120in the gate region may be recessed and the dielectric layer130covers the recessed barrier layer120region. The gate electrode160disposed over the dielectric layer130may include conductive material including amorphous, poly-crystalline, or crystalline semiconductors, metals or conductive oxides or dielectrics or a combination of these material. In the embodiments described above the source and drain contacts140and150and the gate electrode160are all formed on the same side of the semiconductor layer (i.e., the top side as seen most easily inFIG. 3) to define a lateral device. In other embodiments, at least one of the drain or source contacts140and150is formed on the opposite side of the semiconductor layer110from the gate electrode160to define a vertical device.

FIGS. 6(a)-6(c)show cross-sectional views of other alternative embodiments of the invention taken along line A-A′ inFIG. 1. The island regions170inFIGS. 6(a)-6(c)are similar to those discussed above in connection withFIGS. 2, 4(c) and4(d), respectively. The embodiments ofFIGS. 6(a)-6(c), however, include an additional semiconductor layer185over or on semiconductor layer110and below barrier layer120. The semiconductor layer185may or may not be located in whole or in part in the gate region shown inFIG. 1. Island regions170are located in the semiconductor layer110between the source contact140and drain contact150and are buried underneath the semiconductor layer185.

The semiconductor layer185, which is located over the island regions170and the semiconductor layer110, may be formed by epitaxial growth or any other suitable method. The semiconductor layer185may be a single semiconductor layer or it may include two or more sub-layers. For example, in some embodiments the semiconductor layer185comprises InxAlyGazN (0≤x≤1, 0≤y≤1, 0≤z≤1, x+y+z=1), SiC, InxAlyGazAs (0≤x≤1, 0≤y≤1, 0≤z≤1, x+y+z=1), diamond, Si and/or oxide semiconductors such as Ga2O3, ZnO2, either by themselves or in combination with other materials and/or heterostructures.

Due to the different compositional and/or structural differences (e.g., different doping types, doping densities, conductivities or material composition) between the island regions170and the surrounding layers in the various embodiments, the built-in potential or mechanical strain between the island regions170and the surrounding semiconductor layers shifts the Fermi-level of the semiconductor layers where the conduction channel is located. As a result, the threshold voltage of the transistor containing the island structure in the gate region is modulated. For example, if the semiconductor layer110is n-type, the island regions may be differ from the semiconductor layer110in being p-type, which will affect the Fermi-level and change the device threshold voltage. This structure can be applied to unipolar semiconductors to make normally-off/enhancement-mode transistors.

The semiconductor devices described herein may be fabricated using a wide variety of different fabrication techniques. For instance, low cost deposition techniques such as chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), and reactive or conventional sputtering methods may be employed. The island regions may be structured, for example, using a SixOyNz-based hard mask combined with dry/wet etching. As a further alternative, other growth methods, such as molecular beam epitaxy (MBE) or atomic layer epitaxy may be used. Yet additional techniques that may be employed include, without limitation, Flow Modulation Organometallic Vapor Phase Epitaxy (FM-OMVPE), Organometallic Vapor-Phase Epitaxy (OMVPE), Hydride Vapor-Phase Epitaxy (HYPE), Atomic Layer Deposition (ALD), and Physical Vapor Deposition (PVD). Standard metallization techniques, as known in the art of semiconductor fabrication, can be used to form the electrodes.

FIGS. 7(a)-7(d)shows a simplified example of the processing steps that may be employed to fabricate the embodiment of the invention shown inFIGS. 2-3. First, in step310ofFIG. 7(a)barrier layer120is deposited on semiconductor layer110, which, as previously mentioned, may be an epitaxial layer formed on a substrate (not shown) or it may itself serve as the substrate. Next, in step320ofFIG. 7(b)an implantation step is performed using suitable masks and the like to form the island regions170that extend through the barrier layer120. Of course, island regions170may be formed by alternative techniques as well. For instance, trenches may be formed in the semiconductor110using an etching process, followed by deposition into the trenches of the material(s) that define the island regions170. Dielectric layer130is then formed in step330ofFIG. 7(c)over the barrier layer120and the exposed surface of the island regions170, followed by deposition of the gate electrode160in step340ofFIG. 7(d). Finally, although not shown, source and drain regions and optional passivation layers may be formed in a conventional manner to complete the fabrication of the semiconductor device100.

FIGS. 8(a)-8(e)shows a simplified example of the processing steps that may be employed to fabricate the embodiment of the invention shown inFIG. 4(a)in which the island regions170are formed at the bottom of trenches172. First, in step410ofFIG. 8(a)barrier layer120is deposited on semiconductor layer110, which, as previously mentioned, may be an epitaxial layer formed on a substrate (not shown) or it may itself serve as the substrate. Next, in step420ofFIG. 8(b)trenches172are formed through the barrier layer120and into the semiconductor layer110by etching methods using suitable masks and the like. An implantation or deposition step is then performed to deposit island regions170through the bottom of the trenches172in step430ofFIG. 8(c). Dielectric layer130is then formed in step440ofFIG. 8(d)over the barrier layer120and in the trenches172over the island regions170, followed by deposition of the gate electrode160in step450ofFIG. 8(e). Finally, although not shown, source and drain regions and optional passivation layers may be formed in a conventional manner to complete the fabrication of the semiconductor device100.

As previously mentioned, the structures described herein may be employed in a number of different semiconductor devices. For instance, in addition to transistors, it may be incorporated into diodes. Similar to the transistor structures shown above, the anode (or in some cases the cathode) of such a diode will cover at least a portion of the island regions. The island regions themselves may be as described above. The anode will make electrical contact with the semiconductor layer underneath it. The different compositional and/or structural differences between the island regions and the surrounding semiconductor layers changes the diode junction capacitance and reverse leakage current.