Chip package module including flip-chip ground pads and power pads, and wire-bonding ground pads and power pads

A chip package module is provided. The chip package module includes a package substrate, a chip, and a conductive connector assembly. The chip having a first surface and a second surface opposite thereto is disposed on the package substrate. The first surface is divided into a first region, a second region, and a third region, and the second region is located between the first and third regions. The chip includes a flip-chip pad group disposed in the first region, a wire-bonding pad group disposed in the third region, and a signal pad group disposed in the second region. The conductive connector assembly is electrically connected between the chip and the package substrate. One of the flip-chip pad group and the wire-bonding pad group is electrically and physically connected to the conductive connector assembly, and the other one is not physically connected to the conductive connector assembly.

CROSS-REFERENCE TO RELATED PATENT APPLICATION

This application claims the benefit of priority to Taiwan Patent Application No. 108136004, filed on Oct. 4, 2019. The entire content of the above identified application is incorporated herein by reference.

FIELD OF THE DISCLOSURE

The present disclosure relates to a chip package module, and more particularly to a chip package module that can be packaged by flip-chip packaging technology or wire-bonding packaging technology according to particular implementations.

BACKGROUND OF THE DISCLOSURE

Recently, flip-chip and wire-bonding packaging technologies have been widely used to package an integrated circuit chip (IC chip) so as to form an electronic component packaged structure.

Despite the cost of the electronic component packaged structure that is fabricated by using the wire-bonding packaging technology being relatively lower, the size of the electronic component packaged structure thus fabricated is relatively larger. Furthermore, it is easier to generate crosstalk and noise in the electronic component packaged structure during signal transmission due to bonding wires being too close together.

Compared to the wire-bonding packaging technology, although the cost of the electronic component packaged structure fabricated by using the flip-chip packaging technology is relatively higher, the electronic component packaged structure has smaller size. Furthermore, better signal transmission quality and lower noise in the electronic component packaged structure fabricated by using the flip-chip packaging technology can be easily achieved since a transmission distance between the IC chip and the circuit board is shorter. Accordingly, the flip-chip packaging technology is usually used for fabricating high-end products, while the wire-bonding packaging technology is usually used for fabricating middle-end products or low-end products.

While IC chips used in high-end, middle-end and low-end products may have the same specification, the arrangements of the pads of the IC chips are different for different packaging technologies, i.e., the flip-chip packaging technology and the wire-bonding packaging technology. To be more specific, in the arrangement of the pads for the flip-chip packaging technology, a plurality of power pads and a plurality of ground pads are usually arranged in a central region of the IC chip. In comparison to the aforementioned arrangement, in another arrangement of the pads for the wire-bonding packaging technology, a plurality of power pads and a plurality of ground pads are usually arranged in a peripheral region of the IC chip.

That is to say, the arrangement of the pads of the IC chip for the flip-chip packaging technology is incompatible with another arrangement of the pads of the IC chip for the wire-bonding packaging technology, and vice versa. As such, in practical application, the flexibility of the IC chip would be limited.

SUMMARY OF THE DISCLOSURE

In response to the above-referenced technical inadequacies, the present disclosure provides a chip package module, and the chip package module includes a chip that can be packaged by using any of a flip-chip packaging technology and a wire-bonding packaging technology according to a practical implementation.

In one aspect, the present disclosure provides a chip package module that includes a package substrate, a chip, and a conductive connector assembly. The chip having a first surface and a second surface opposite to the first surface is disposed on the package substrate. The first surface is divided into a first region, a second region, and a third region, in which the second region is located between the first region and the third region. The chip includes a flip-chip pad group disposed in the first region, a wire-bonding pad group disposed in the third region, and a signal pad group disposed in the second region. The conductive connector assembly is electrically connected between the chip and the package substrate. One of the flip-chip pad group and the wire-bonding pad group is electrically and physically connected to the conductive connector assembly, and the other one of the flip-chip pad group and the wire-bonding pad group is not physically connected to the conductive connector assembly.

Therefore, one of the advantages of the present disclosure is that in the chip package module provided herein, by the technical features of “the chip including the flip-chip pad group, the wire-bonding pad group, and the signal pad group” and “one of the flip-chip pad group and the wire-bonding pad group is electrically and physically connected to the conductive connector assembly, and the other one is not physically connected to the conductive connector assembly,” the chip package module can be fabricated by using any one of the flip-chip and wire-bonding packaging technologies according to a field of application thereof, thereby improving application flexibility of the chip. These and other aspects of the present disclosure will become apparent from the following description of the embodiment taken in conjunction with the following drawings and their captions, although variations and modifications therein may be affected without departing from the spirit and scope of the novel concepts of the disclosure.

DETAILED DESCRIPTION OF THE EXEMPLARY EMBODIMENTS

Reference is made toFIG. 1toFIG. 3.FIG. 1is a schematic top view of a chip according to an embodiment of the present disclosure.FIG. 2shows an enlarged view of the chip taken on part II ofFIG. 1.FIG. 3is a partial schematic side view of the chip shown inFIG. 1.

As shown inFIG. 1andFIG. 3, a chip1of the embodiment of the present disclosure has a first surface1aand a second surface1bopposite to the first surface1a. Furthermore, as shown inFIG. 1, the first surface1aof the chip1can be divided into a first region A1, a second region A2and a third region A3from a center to an edge of the chip1along a radial direction.

As shown inFIG. 1, the first region A1is a central region of the first surface1a, the second region A2surrounds the first region A1, and the third region A3surrounds the second region A2(and the first region A1). That is to say, the second region A2is located between the first region A1and the third region A3.

Reference is made toFIG. 2. The chip1includes a flip-chip pad group10, a signal pad group11, and a wire-bonding pad group12. The flip-chip pad group10is disposed in the first region A1and includes a plurality of pads. To be more specific, the flip-chip pad group includes a plurality of flip-chip power pads P1and a plurality of flip-chip ground pads G1, which are jointly arranged in an array.

Specifically, the flip-chip power pads P1are arranged in at least one column (two columns are shown inFIG. 2) in a first direction D1, and the flip-chip ground pads G1are arranged in another column in the first direction D1. In one embodiment, a plurality of columns of the flip-chip power pads P1and a plurality of columns of the flip-chip ground pads G1are alternately arranged in the first region A1.

In the instant embodiment, each of the columns of the flip-chip ground pads G1is interposed between two adjacent columns of the flip-chip power pads P1. That is to say, in a second direction D2, one of the flip-chip ground pads G1is disposed between two adjacent ones of the flip-chip power pads P1. It should be noted that the flip-chip pad group10illustrated inFIG. 2is only exemplified for description, but not intended to limit the scope of the present disclosure. The numbers and arrangements of the flip-chip power pads P1and the flip-chip ground pads G1can be adjusted according to actual implementations.

Reference is made toFIG. 4, which shows an enlarged view of a chip according to another embodiment of the present disclosure. In the flip-chip pad group10of the instant embodiment, the arrangements of the flip-chip power pads P1and the flip-chip ground pads G1are different from those shown inFIG. 2. Specifically, as shown inFIG. 4, in the flip-chip pad group10, at least two columns of the flip-chip power pads P1are adjacent to each other. In another embodiment, in the flip-chip pad group10, at least two columns of the flip-chip ground pads G1can be adjacent to each other.

Accordingly, as long as the flip-chip power pads P1and the flip-chip ground pads G1can be arranged to comply with the flip-chip packaging technology, the arrangements of the flip-chip power pads P1and the flip-chip ground pads G1are not limited to the examples provided herein.

Reference is made toFIG. 2. The signal pad group11is disposed in the second region A2and includes a plurality of signal pads S. The signal pads S are arranged to surround the first region A1. In the embodiment shown inFIG. 2, the signal pads S are arranged in three columns (or three rows) near to one side of the first region A1, but the present disclosure is not limited thereto. In another embodiment, the number and arrangement of the signal pads S can be adjusted based on the functions and size of the chip1.

For example, the signal pads S can be respectively defined as different signal terminals, such as a VCC pad, a VDD pad, a VSS pad, a power supply pad, a clock-signal pad, an address signal pad, and so on.

It should be noted that the signal pads S of the signal pad group11can be arranged to comply with both of the flip-chip and wire-bonding packaging technologies. Generally, a pitch between any two adjacent pads required in the wire-bonding packaging technology would be larger than that required in the flip-chip packaging technology. Accordingly, in order to comply with both of the requirements of the wire-bonding and flip-chip packaging technologies, a pitch d2between two adjacent ones of the signal pads S in the same column would primarily meet the requirements of the wire-bonding packaging technology.

Therefore, the pitch d2between any two adjacent ones of the signal pads S in the same column is larger than a pitch d1between any two adjacent ones of the flip-chip ground pads G1(or the flip-chip power pads P1) in the same column. The aforementioned pitch can be defined as the shortest distance between two geometric centers of two adjacent pads at the same column, such as two adjacent signal pads S. Furthermore, a column pitch L2between two adjacent columns of the signal pads S in the second region A2is larger than a column pitch L1between two adjacent columns of the flip-chip power pads P1(or the flip-chip ground pads G1) in the first region A1.

Reference is made toFIG. 2. The wire-bonding pad group12includes a plurality of wire-bonding power pads P2and a plurality of wire-bonding ground pads G2. The wire-bonding ground pads G2are arranged in a first column along an edge of the chip1. Furthermore, the wire-bonding power pads P2are arranged in a second column along the edge of the chip1, and the second column is located at the inner side of the first column. That is, the second column is farther away from the edge of the chip1than the first column.

In another embodiment, the two positions of the first and second columns can be switched with each other. In other words, the wire-bonding ground pads G2are farther away from the edge of the chip1, and the wire-bonding power pads P2are closer to the edge of the chip1.

It should be noted that, only a part of the chip1is illustrated to elaborate the present disclosure. In practice, the wire-bonding ground pads G2and the wire-bonding power pads P2are arranged along the entire edge of the chip1and surround the second region A2.

In the instant embodiment, any two adjacent wire-bonding power pad P2and wire-bonding ground pad G2are offset from each other in the second direction D2. As shown inFIG. 2, an imaginary connecting line between two geometric centers of two adjacent wire-bonding power pad P2and wire-bonding ground pad G2is not parallel to the second direction D2.

A pitch d3between two adjacent ones of the wire-bonding ground pads G2in the first column is substantially the same as a pitch between two adjacent ones of the wire-bonding power pads P2in the second column. It should be noted that since the wire-bonding pad group12is arranged to comply with the requirements of the wire-bonding packaging technology, the pitch d3between two adjacent ones of the wire-bonding ground pads G2is greater that the pitch d1between two adjacent ones of the flip-chip ground pads G1in the same column.

In addition, a column pitch L3between two adjacent columns (the first and second columns) in the third region A3is greater than the column pitch L1between two adjacent columns in the first region A1.

Accordingly, the chip1provided in the embodiments of the present disclosure can be packaged by any one of the flip-chip or wire-bonding packaging technologies. Reference is made toFIG. 5, which is a partial schematic side view of a chip package module M1that is fabricated by packaging the chip1with the flip-chip packaging technology. The chip package module M1includes a chip1, a package substrate2, a conductive connector assembly3and a molding layer4. The package substrate2has a supporting surface2aand a bottom surface2bopposite to the supporting surface2a.

The package substrate2can be a circuit board, a ceramic board, a metal board, or a board made of composite material. In the instant embodiment, the package substrate2is a circuit board and includes a plurality of interconnecting wires (not shown) configured therein, a plurality of solder pads20G,20P,20S disposed on the supporting surface2a, and a plurality of solder balls21disposed on the bottom surface2b. Specifically, the solder pads20G,20P,20S and the solder balls21can be electrically connected one another through the interconnecting wires configured in the package substrate2.

The solder pads20G,20P,20S can include a plurality of power solder pads20P, a plurality of ground solder pads20G, and a plurality of signal pads20S. In the instant embodiment, the interconnecting wires, the solder pads20G,20P,20S, and the solder balls21of the package substrate2are arranged to comply with the requirements of the flip-chip packaging technology.

To be more specific, as shown inFIG. 5, the supporting surface2aof the package substrate2is defined with a predetermined chip mounting area20a, and the solder pads20G,20P,20S are arranged in the predetermined chip mounting area20a. When the chip1is disposed on the package substrate2, the first surface1aof the chip1faces toward the package substrate2, i.e., the chip1is disposed on the package substrate2in a flip chip manner. The power solder pads20P, the ground solder pads20G, and the signal solder pads20S are disposed under the chip1.

Furthermore, in the instant embodiment, the power solder pads20P and the ground solder pads20G are arranged in an array. To be more specific, the power solder pads20P are arranged to respectively correspond to the flip-chip power pads P1, and the ground solder pads20G are arranged to respectively correspond to the flip-chip ground pads G1. Similarly, the signal solder pads20S are arranged under the second region A2and correspond to the signal pads S, respectively.

When the chip1is disposed on the package substrate2, the chip1can be electrically connected to the package substrate2through the conductive connector assembly3. In the instant embodiment, the electrical connector assembly3is electrically and physically connected to the flip-chip pad group10, but is not physically connected to the wire-bonding pad group12. That is to say, when the chip1is packaged by using the flip-chip packaging technology, all of the wire-bonding power pads P2and the wire-bonding ground pads G2of the chip1are dummy pads.

Furthermore, according to the packaging technology of the chip1is the flip-chip or wire-bonding packaging technology, the conductive connector assembly3of the instant embodiment can include either a plurality of (conductive) bumps or a plurality of bonding wires. In the embodiment shown inFIG. 5, the conductive connector assembly3includes a plurality of power bumps30P, a plurality of ground bumps30G, and a plurality of signal bumps30S.

Each of the power bumps30P is connected between the corresponding one of the power solder pads20P and the corresponding one of the flip-chip power pads P1. Each of the ground bumps30G is connected between the corresponding one of the ground solder pads20G and the corresponding one of the flip-chip ground pads G1. Each of the signal bumps30S is connected between the corresponding one of the signal pads20S and the corresponding one of the signal pads S. As such, the chip1can be mounted on and electrically connected to the package substrate2through the conductive connector assembly3. The molding layer4covers the chip1and the supporting surface2aof the package substrate2so as to protect the chip1.

Reference is made toFIG. 6, which is a partial schematic side view of a chip package module M2that is fabricated by packaging the chip1with the wire-bonding packaging technology.

The chip package module M2includes the chip1, a package substrate2, a conductive connector assembly3′, and a molding layer4. In the instant embodiment, the solder pads20G,20P,20S, the interconnecting wires, and the solder balls21are arranged to comply with the requirements of the wire-bonding packaging technology. Therefore, the solder pads (including the power solder pads20P, the ground solder pads20G, the signal solder pads20S) are located at the outside of the predetermined chip mounting area20a, and surround the predetermined chip mounting area20a.

In one embodiment, in the solder balls21disposed on the bottom surface2bof the package substrate2, some of the solder balls21are electrically connected to the power solder pads20P and the ground solder pads20G, and are arranged in a region overlapping with the predetermined chip mounting area20ain a thickness direction of the package substrate2(i.e., some of the solder balls21are arranged under the predetermined chip mounting area20a). Accordingly, compared to the signal solder pads20S, any one of the power solder pads20P and the ground solder pads20G is located at a position closer to the predetermined chip mounting area20a.

The chip1is disposed on the package substrate2with the second surface1bthereof facing toward the package substrate2. That is to say, the arrangement direction of the chip1in the instant embodiment, in which the first surface1aof the chip1faces upward, is opposite to that in the embodiment shown inFIG. 5. Furthermore, the chip package module M2further includes an adhesive layer5interposed between the chip1and the package substrate2, such that the chip1can be fixed on the package substrate2.

Furthermore, as shown inFIG. 6, a shortest distance between any one of the signal solder pads20S and the chip1is greater than that between any one of the power solder pads20P and the chip1. Additionally, the shortest distance between any one of the signal solder pads20S and the chip1is greater than that between any one of the ground solder pads20G and the chip1. As long as the aforementioned conditions are satisfied, the positions of the plurality of the power solder pads20P and the plurality of ground solder pads20G can be switched with each other, and the present disclosure is not limited thereto.

When the chip1is disposed on the package substrate2, the chip1can be electrically connected to the package substrate2through the conductive connector assembly3′. One of the differences between the instant embodiment and the embodiment shown inFIG. 5is that the conductive connector assembly3′ is electrically and physically connected to the wire-bonding pad group12in the instant embodiment, rather than the flip-chip pad group10. That is to say, when the chip1is packaged by using the wire-bonding packaging technology, all of the flip-chip power pads P1and the flip-chip ground pads G1are dummy pads.

Furthermore, in the embodiment shown inFIG. 6, the conductive connector assembly3′ includes a plurality of power bonding wires30P′, a plurality of ground bonding wires30G′, and a plurality of signal bonding wires30S′. Each of the power bonding wires30P′ is connected between the corresponding one of the power solder pads20P and the corresponding one of the wire-bonding power pads P2, and each of the ground bonding wires30G′ is connected between the corresponding one of the ground solder pads20G and the corresponding one of the wire-bonding ground pads G2. Each of the signal bonding wires30S′ is connected between the corresponding one of the signal solder pads20S and the corresponding one of the signal pads S. Therefore, the chip1can be electrically connected to the package substrate2through the conductive connector assembly3′ and electrically connected to an external control circuit through the solder balls21of the package substrate2.

It should be noted that whether the chip1is packaged by the flip-chip or wire-bonding packaging technology, the signal pad group11of the chip1are electrically connected to the conductive connector assembly3(3′). That is to say, when the chip1is mounted on the package substrate2in the flip-chip manner, the signal pads S are respectively connected to the signal bumps30S so as to be electrically connected to the signal solder pads20S, respectively. When the chip1is connected to the package substrate2in the wire-bonding manner, the signal pads S are respectively connected to the signal bonding wires30S′ so as to be electrically connected to the signal solder pads20S, respectively.

In conclusion, one of the advantages of the present disclosure is that in the chip package module M1(M2) provided herein, by the technical features of “the chip1including the flip-chip pad group10, the wire-bonding pad group12, and the signal pad group11” and “one of the flip-chip pad group10and the wire-bonding pad group12is electrically and physically connected to the conductive connector assembly3(3′), and the other one is not physically connected to the conductive connector assembly3(3′),” the chip package module M1(M2) can be fabricated by packaging the chip1with the flip-chip or wire-bonding packaging technology, thereby improving application flexibility of the chip1. That is to say, the chip1, which includes the flip-chip pad group10, the wire-bonding pad group12, and the signal pad group11and is provided in the embodiments of the present disclosure, can be packaged by any one of the flip-chip and wire-bonding packaging technologies.

For example, according to particular implementations, the chip1can be packaged by the flip-chip packaging technology to fabricate the chip package module M1that can be used in high-end electronic products. Furthermore, the chip1can also be packaged by the wire-bonding packaging technology to fabricate the chip package module M2that can be used in middle-end or low-end electronic products.