Memory diodes

A memory cell (32C), including a first non-insulator (34C) and a second non-insulator (40C), different from the first non-insulator. The second non-insulator forms a junction (46C) with the first non-insulator. The cell further includes a first electrode (48C) which is connected to the first non-insulator and a second electrode (50C) which is connected to the second non-insulator. At least one of the first and second non-insulators is chosen from a group consisting of a solid electrolyte and a mixed ionic electronic conductor and has an ionic transference number less than 1 and greater than or equal to 0.5.

FIELD OF THE INVENTION

The present invention relates generally to memory devices, and particularly to memory devices formed from non-insulating materials.

BACKGROUND OF THE INVENTION

A number of different memory systems are known in the art. However, known technological and scaling limitations of the memories based on existing technologies, such as flash memories, generate problems for the microelectronics industry. The problems are compounded for the memory industries.

Documents incorporated by reference in the present patent application are to be considered an integral part of the application except that to the extent any terms are defined in these incorporated documents in a manner that conflicts with the definitions made explicitly or implicitly in the present specification, only the definitions in the present specification should be considered.

SUMMARY OF THE INVENTION

An embodiment of the present invention provides a memory cell, including:

a first non-insulator;

a second non-insulator, different from the first non-insulator, forming a junction with the first non-insulator;

a first electrode connected to the first non-insulator; and

a second electrode connected to the second non-insulator, wherein at least one of the first and second non-insulators is chosen from a group consisting of a solid electrolyte and a mixed ionic electronic conductor and has an ionic transference number less than 1 and greater than or equal to 0.5.

Typically, the first non-insulator and the second non-insulator are selected so that the junction acts as a diode.

Typically, at least one of the first and the second non-insulators is selected from a group including a p-type material having a preponderance of holes, an n-type material having a preponderance of electrons, and an i-type, intrinsic material. One of the first and the second non-insulators may include a metal.

Typically, the cell is configurable into one of two different stable states. The cell may be configured into one of the two different states in response to applying one of a forward and a reverse current to the cell. The cell may have a hysteresis, so that the states include a low-current high-resistance state and a high-current low-resistance state. The hysteresis may be configured by applying one of a preset voltage and a voltage changing at a preset rate to the cell. The one of the two different stable states may be ascertained by measuring a current generated on application of a read voltage between the first and second electrodes.

Alternatively or additionally, the two stable states may have differing open circuit voltages between the first and the second electrodes. In one embodiment one of the two stable states has a zero open circuit voltage. Typically, the one of the two stable states is determined by measuring a potential between the first and the second electrodes.

In a disclosed embodiment the cell is configurable to store energy.

There is further provided, according to an embodiment of the present invention, a memory cell, including:

a first non-insulator;

a second non-insulator;

a first electrode connected to the first non-insulator;

a second electrode connected to the second non-insulator; and

n third non-insulators, where n is an integer greater than or equal to 1, connected sequentially between the first and second non-insulators to form (n+1) junctions,

wherein at least one of the first, second and n third non-insulators is chosen from a group consisting of a solid electrolyte and a mixed ionic electronic conductor and has an ionic transference number less than 1 and greater than or equal to 0.5, so that the cell is configurable into one of 2(n+1)stable states, and wherein at least two of the stable states are different.

In a disclosed embodiment the cell has a hysteresis, and the 2(n+1)stable states are defined by respective hysteresis states of the cell.

In a further disclosed embodiment the 2(n+1)stable states have respective 2(n+1)open circuit voltages. A first open circuit voltage of the 2(n+1)open circuit voltages may be zero, and a second open circuit voltage may be different from zero.

In a yet further disclosed embodiment, the 2(n+1)stable states include up to 2(n+1)different stable states.

There is further provided, according to an embodiment of the present invention, a memory array, including:

a first non-insulator layer;

a second non-insulator layer, different from the first non-insulator layer, forming a junction layer with the first non-insulator layer;

a first electrode layer connected to the first non-insulator layer; and

a second electrode layer connected to the second non-insulator and configured to define a plurality of memory cells within the array, wherein at least one of the first and second non-insulator layers is chosen from a group consisting of a solid electrolyte and a mixed ionic electronic conductor and has an ionic transference number less than 1 and greater than or equal to 0.5.

Typically, the second electrode layer includes a multiplicity of isolated electrodes corresponding to the plurality of memory cells.

In an alternative embodiment the first electrode layer is configured as a first multiplicity of parallel conductors, and the second electrode layer is configured as a second multiplicity of parallel conductors not parallel to the first multiplicity. Typically, each of the plurality of memory cells is defined by a respective different intersection between the first and the second multiplicities.

There is further provided, according to an embodiment of the present invention, apparatus, including:

a first non-insulator; and

a second non-insulator, different from the first non-insulator, forming a junction with the first non-insulator, at least one of the first and second non-insulators being chosen from a group consisting of a solid electrolyte and a mixed ionic electronic conductor and having an ionic transference number less than 1 and greater than or equal to 0.5.

Typically, the first non-insulator and the second non-insulator are selected so that the junction acts as a diode. In a disclosed embodiment the diode has a hysteresis.

In an alternative embodiment at least one of the first and the second non-insulators is selected from a group including a p-type material having a preponderance of holes, an n-type material having a preponderance of electrons, and an i-type, intrinsic material. In a further alternative embodiment one of the first and the second non-insulators includes a metal. Typically, the first and the second non-insulators are configurable to store energy.

There is further provided, according to an embodiment of the present invention, a method for forming a memory cell, including:

providing a first non-insulator;

forming with a second non-insulator, different from the first non-insulator, a junction with the first non-insulator;

connecting a first electrode to the first non-insulator; and

connecting a second electrode to the second non-insulator, wherein at least one of the first and second non-insulators is chosen from a group consisting of a solid electrolyte and a mixed ionic electronic conductor and has an ionic transference number less than 1 and greater than or equal to 0.5.

There is further provided, according to an embodiment of the present invention, a method for forming a memory cell, including:

providing a first non-insulator;

providing a second non-insulator;

connecting a first electrode to the first non-insulator;

connecting a second electrode to the second non-insulator; and

connecting n third non-insulators, where n is an integer greater than or equal to 1, sequentially between the first and second non-insulators to form (n+1) junctions,

wherein at least one of the first, second and n third non-insulators is chosen from a group consisting of a solid electrolyte and a mixed ionic electronic conductor and has an ionic transference number less than 1 and greater than or equal to 0.5, so that the cell is configurable into one of 2(n+1)stable states, and wherein at least two of the stable states are different.

There is further provided, according to an embodiment of the present invention, a method for forming a memory array, including:

providing a first non-insulator layer;

connecting a second non-insulator layer, different from the first non-insulator layer, to form a junction layer with the first non-insulator layer;

connecting a first electrode layer to the first non-insulator layer; and

connecting a second electrode layer to the second non-insulator, wherein the second electrode layer is configured to define a plurality of memory cells within the array, wherein at least one of the first and second non-insulator layers is chosen from a group consisting of a solid electrolyte and a mixed ionic electronic conductor and has an ionic transference number less than 1 and greater than or equal to 0.5.

There is further provided, according to an embodiment of the present invention, a method, including:

providing a first non-insulator; and

connecting a second non-insulator, different from the first non-insulator, to form a junction with the first non-insulator, at least one of the first and second non-insulators being chosen from a group consisting of a solid electrolyte and a mixed ionic electronic conductor and having an ionic transference number less than 1 and greater than or equal to 0.5.

DETAILED DESCRIPTION OF EMBODIMENTS

Overview

An embodiment of the present invention provides a memory cell, which is typically configured within an array of substantially similar memory cells. Each cell in the array has at least one junction, each junction being formed between two non-insulator materials. The two non-insulators are typically configured as layers of the array. At least one of the first and second non-insulators is chosen from a group consisting of a solid electrolyte and a mixed ionic electronic conductor and has an ionic transference number which is less than 1 and greater than or equal to 0.5. Typically, the non-insulator materials are selected so that the junction formed by the materials acts as a diode, having rectifying properties.

The inventor has found that a cell formed as described above has a hysteresis characteristic, and the hysteresis enables the cell to exist in different numbers of stable states. Thus, a cell having one junction can exist in two different stable states. Which state a cell is in may be determined by applying a read voltage to the cell, and measuring which of different possible currents the cell delivers.

The inventor has also found that in addition to the hysteresis characteristic exhibited by a cell, the cell is also able to store energy in at least one of its states, and the stored energy is manifested as a non-zero open circuit voltage. Thus, a single junction cell may exist in a first state having zero open circuit voltage, and a second state having a non-zero open circuit voltage, so that the state of a cell may be measured by determining the open circuit voltage.

When formed in arrays, memory cells of the present invention have considerably smaller cross-talk to adjacent cells than cells based on other junctions, such those of metal-insulator-metal devices.

System Description

Embodiments of the present invention provide cells which are typically formed as arrays comprising more than one such cell. For clarity, except where otherwise stated, the following description assumes such arrays, and those having ordinary skill in the art will be able to adapt the description,mutatis mutandis, for the case of a single cell.

Reference is now made toFIG. 1, which is a schematic illustration of an array30of cells, according to an embodiment of the present invention. As is explained in more detail below, each cell of array30acts, inter alia, as a memory diode, and may also be referred to herein as a memory diode cell. A memory diode cell is assumed to function as a diode that has electrical rectifying characteristics and that is also able to act as a memory device, storing information. Typically the information stored comprises binary information, wherein a given memory diode cell may be in one of two possible stable states. In some embodiments the information may be “multi-nary,” wherein the cell may be in one of more than two states. The state of a memory diode cell may be read and/or changed by an entity, such as a potential sensor, a current sensor, or a charge sensor, external to the memory diode cell. In addition to storing information, a memory diode cell is also able to store energy, and supply the stored energy to an external device.

In the following description, array30is assumed to have a generally box-like shape, with edges defining an orthogonal set of xyz axes, wherein the z axis is a vertical axis. However, it will be understood that the assumption of the shape and orientation of array30is purely by way of example and for clarity, so that in practice array30may have substantially any suitable shape and substantially any orientation. It will also be understood that designations herein such as “upper,” “lower,” “above,” or “below” in describing the relations between elements of array30are for simplicity and clarity, and are not limiting.

In array30a substrate layer34, assumed to be a generally rectangular sheet and to be lying generally parallel to an xy plane, is used as a mount for the array of cells. In array30, the properties, described below, of substrate layer34are selected so that the substrate layer also acts as a functional component of the array. (Embodiments wherein the substrate layer does not act as a functional component of a memory diode cell array are described below.) Substrate layer34has an upper surface36and a lower surface38, and comprises a first solid material which is a non-insulator. Substrate layer34may herein also be referred to as first non-insulator layer34.

A second non-insulator layer40, having different properties to those of the first non-insulator layer, is a generally rectangular sheet. Layer40, by way of example, may have generally the same xy dimensions as the first non-insulator layer, and also lies generally parallel to the xy plane. Second non-insulator layer40is a solid having properties causing it to also act as a functional component of the array. The second non-insulator layer has an upper surface42and a lower surface44, and it is mounted so that its lower surface44is in contact with upper surface36of the first non-insulator layer. A region of contact37of the two non-insulator layers, shown for surface36by hatching, thus forms a junction layer46.

A conducting layer, typically an inert metal such as platinum or gold, is connected to lower surface38of first non-insulator layer34, and acts as a first electrode layer48for the array. In array30, first electrode layer48may comprise a conducting sheet of material having, by way of example, generally the same xy dimensions as the non-insulator layers.

A plurality of discrete, isolated, electrodes50A,50B, . . . , herein by way of example assumed to comprise generally similar discs, are connected to upper surface42of second non-insulator layer40. Electrodes50A,50B, . . . are herein generically also referred to as electrodes50, and are assumed to form a second electrode layer53. Each electrode50in layer53forms a section of the layer and is typically formed from inert metal, such as that used for layer48. Electrodes50are typically arranged in a two-dimensional repeating pattern that may be defined vectorially, as is known in the art. In array30there may be any convenient number of electrodes50in layer53, and the electrodes are typically arranged symmetrically on a rectangular xy grid. By way of example,FIG. 1illustrates nine electrodes50A,50B, . . .50I of layer53.

Typically, although not necessarily, first electrode layer48comprises a metallic bonding layer49which bonds the first electrode layer to lower surface38of the first non-insulator. A metallic bonding layer may be formed from a non-inert metal, such as Ti, Al, or Cr. In addition, electrodes50A,50B, . . . may also comprise respective metallic bonding layers51A,51B, . . . which bond the respective electrodes to upper surface42of the second non-insulator.

As stated above, electrodes50A,50B, . . .50I are isolated from each other, and each electrode defines a respective memory diode cell32A, . . .32C . . . , generically referred to herein as cells32, in array30. For clarity, in the following description, at least some of the components of a given cell32formed by layers of array30may be differentiated from each other by appending a corresponding letter to the identifying numeral of the layer, or layer sections, of the array, where the components comprise all or part of second electrode layer53, first non-insulator layer34, second non-insulator layer40, and first electrode layer48.

Thus, as illustrated by a diagram52, the components of cell32C, defined by electrode50C, comprise the electrode, a non-insulator section40C of second non-insulator layer40, a non-insulator section34C of first non-insulator layer34, a junction section46C of junction layer46, and an electrode section48C of first electrode layer48, the sections lying generally beneath electrode50C. Electrode50C may also comprise bonding layer section51C, and section48C may also comprise a section of bonding layer49.

Typically, although not necessarily, at least some of sections40C,34C,46C, and48C have generally the same shape as electrode50C, but may differ in size. For example, since first electrode layer48is a conducting sheet, section48C may be substantially larger than electrode50C, depending on the resistivity of the sheet. All cells32in array30have substantially the same structures, and it will be understood that the isolation of individual electrodes50from each other allows cells32to be individually addressed, typically by individual conductors (not shown in the figure) attached to the electrodes.

Properties of the different layers of array30are described below.

FIG. 2is a schematic illustration of an array130of memory diode cells, according to an alternative embodiment of the present invention. Apart from the differences described below, the operation of array130is generally similar to that of array30(FIG. 1), and elements indicated by the same reference numerals in both arrays30and130are generally similar in construction and in operation. For clarity, elements that are similar in the two arrays are differentiated by appending an apostrophe to the reference numerals in elements in array130. Thus, array130comprises a second electrode layer53′, a first non-insulator layer34′, a second non-insulator layer40′, a junction layer46′, and a first electrode layer48′.

In contrast to array30, in array130first non-insulator layer34′ does not act as a substrate for the array. Thus, while by way of example in array130first non-insulator layer34′ is assumed to have similar x and y dimensions to layer34in array30, it typically may have a smaller z dimension than the z dimension of first insulator layer34of array30. To support its elements, array130comprises a separate, insulating substrate layer132. First non-insulator layer34′ is mounted on substrate layer132, so that lower surface38′ of the first insulator layer contacts the substrate.

Second non-insulator layer40′ is assumed by way of example to have similar y and z dimensions to layer40of array30, but to have a smaller x dimension. Lower surface44′ of layer40′ contacts upper surface36′ of layer34′ to form junction46′. Because of the smaller x dimension of layer40′, there is a region134on upper surface36′ that does not form junction46′, and first electrode layer48′ is dimensioned to suit this region. In contrast to array30, in array130first electrode layer48′ is mounted on upper surface36′ in region134.

In array130second electrode layer53′ has, by way of example, six disc electrodes50A′,50B′, . . .50F′ (referred to herein together as electrodes50′), mounted to contact surface42′. As for array30, electrodes50′ in array130may comprise a bonding layer51′ to bond the electrodes to mating surface42′, and electrode layer48′ may comprise a bonding layer49′ for bonding the layer to surface36′ of non-insulator layer34′. As for array30, in array130each disc electrode50′ defines a separate memory diode cell32′, so that in the example embodiment illustrated byFIG. 2, there are six memory diode cells.

A diagram136illustrates the structure of one of memory cells32′,32C′, in more detail. Cell32C′ comprises a non-insulator section40C′ of second non-insulator layer40′, a non-insulator section34C′ of first non-insulator layer34′, a junction section46C′ of junction layer46′, and an electrode section48C′ of electrode layer48′. However, in contrast to the cells of array30, cells32′ use a portion134C′ of region134to form a conducting path to electrode layer48′.

In the description herein, arrays such as array130comprise two non-insulator layers which are typically thin. These arrays are also referred to as dual film arrays, and the cells of dual film arrays are referred to as dual film cells. In contrast, arrays such as array30comprise two non-insulator layers, one of which is thin, the other being thick. These arrays are also referred to herein as single film arrays, and their cells as single film cells.

It will be understood that there are configurations of arrays of memory diode cells other than those described above with reference toFIGS. 1 and 2. For example, rather than first electrode layer48of array30being in the general form of a single continuous sheet, the electrode layer may be in the form of two or more separate sheets, and/or may have apertures. Examples of other configurations of arrays of memory diode cells are described below.

FIGS. 3A and 3Bare schematic diagrams illustrating alternative configurations of arrays of memory diode cells, according to an embodiment of the present invention. A diagram150illustrates a top view of an array152, which functions generally as array30, and except for the differences described below is assumed to be configured generally as array30(FIG. 1). Thus array152comprises memory diode cells153, formed from a second electrode layer154having separate electrode discs156, a first non-insulator layer158acting as a substrate, a second non-insulator layer160, and a first electrode layer162, the layers being stacked parallel to the z axis, as in array30. Layers158and160form a junction layer159. Second electrode layer154, discs156, first non-insulator layer158, junction layer159, and second non-insulator layer160are respectively substantially similar to second electrode layer53, discs50, first non-insulator layer34, junction layer46, and second non-insulator layer40.

However, unlike first electrode layer48, which is a continuous sheet, first electrode layer162is in the form of a mesh in an xy plane, having apertures164therein. The mesh is sized to correspond with the positions of electrode discs in second electrode layer154, so that junctions166of the first electrode layer mesh are positioned in line with discs156. If, as is typically the case, discs156are arranged in a two-dimensional repeating pattern that may be defined vectorially, the positions of junctions166may be defined using the same vector definitions, so that junctions166align vertically with discs156.

As for array30, each memory diode cell153in array152is defined by a respective electrode disc156. Thus a given cell153includes sections of non-insulator layers158and160below a specific disc, and sections of mesh layer162including and surrounding the mesh junction166below the specific disc.

A diagram180illustrates a top view of an array182of memory diode cells184. Apart from the differences described below, the operation of array182is generally similar to that of array152, and elements indicated by the same reference numerals in both arrays152and182are generally similar in construction and in operation.

As for array152, in array182discs156of second electrode layer154are typically arranged in a two-dimensional repeating pattern that may be defined vectorially. However, in array182, positions of junctions166of mesh layer162may use the same vector definition to define the repetitions of the junctions, but with centers of apertures164aligned with discs156.

In array182, each memory diode cell184is defined by a respective electrode disc156. Thus a given cell184includes sections of non-insulator layers158and160below a specific disc, and sections of mesh layer162framing the aperture164below the specific disc.

FIG. 4is a schematic top view of a further alternative configuration of an array200of memory diode cells, according to an embodiment of the present invention. Apart from the differences described below, the operation of array200is generally similar to that of array30(FIG. 1), and elements indicated by the same reference numerals in both arrays30and200are generally similar in construction and in operation. Thus, array200comprises first non-insulator layer34, second non-insulator layer40, and junction layer46formed at the region of contact of the two non-insulator layers. In contrast to the configuration of first electrode layer48in array30, in array200first electrode layer48comprises a first plurality of substantially similar parallel, separated, electrodes202A,202B,202C, . . . , also referred to herein as electrodes202. Electrodes202are connected to lower surface38of first non-insulator layer34, and are typically, but not necessarily, separated from each other by equal distances. Herein, by way of example, electrodes202are assumed to be configured as linear conductors parallel to the x-axis.

Also in contrast to the configuration of second electrode layer53of array30, in array200second electrode layer53comprises a second plurality of substantially similar, parallel, separated, electrodes204A,204B,204C, also referred to herein as electrodes204. Electrodes204are connected to upper surface42of second non-insulator layer40, and as for electrodes202are typically, but not necessarily, separated from each other by equal distances. Herein, by way of example, electrodes204are assumed to be configured as linear conductors that are not parallel to electrodes202, so that the two pluralities of electrodes, as viewed along to the z-axis, cross. By way of example, electrodes204are assumed to be parallel to the y-axis, so that the two pluralities of electrodes are orthogonal to each other.

The crossing of the two electrode layers defines different cells of array200. For example, a cell206is defined by the crossing of electrode202A and electrode204B. Cell206comprises portions of electrode202A, electrode204B, non-insulator layer34, non-insulator layer40, and junction layer46in the region of the crossing point of the two electrodes. In array200there are other cells, all similar to cell206, each of the cells being defined uniquely by one of electrodes202and one of electrodes204. Eight such cells are illustrated inFIG. 4.

The arrays described above with reference toFIGS. 1-4are examples of arrays of memory diode cells, wherein each cell has a single junction between two non-insulator layers. As is explained below, each cell of a single junction array is capable of assuming two stable states, so that each cell is able to store information in a binary format.

Embodiments of the present invention are not limited to cells with a single junction, so that embodiments of the present invention include arrays of memory cells having two or more junctions.

FIGS. 5A and 5Bshow schematic side views of arrays230and330, each array having two junctions, according to embodiments of the present invention. Apart from the differences described below, the operation of arrays230and330are respectively generally similar to those of a arrays30and130(FIGS. 1 and 2), and elements indicated by the same reference numerals in pairs of arrays30and230, and in pairs of arrays130and330, are generally similar in construction and in operation.

Array230(FIG. 5A) comprises first electrode layer48, first non-insulator layer34which acts as a substrate, second non-insulator layer40, and junction layer46, herein also referred to as first junction layer46, formed by the contact between layers34and40. Between electrode layer53, comprising disc electrodes50, and second non-insulator layer40there is a third non-insulator layer232. By way of example discs50A,50B of disc electrodes50are shown inFIG. 5A. A lower surface234of the third non-insulator layer contacts upper surface42of the second non-insulator layer, so forming a second junction layer236between the upper two non-insulator layers. Disc electrodes50are mounted on an upper surface238of third non-insulator layer232.

As for array30all cells of array230are substantially similar in configuration and operation, and each cell of array230is defined by a particular disc electrode50. Thus, a cell240defined by disc electrode50B comprises the electrode, and sections of third non-insulator layer232, second junction layer236, second non-insulator layer40, first junction layer46, first non-insulator layer34, and first electrode layer48, the sections lying below the electrode.

Array330(FIG. 5B) is formed on insulating substrate132, upon which is mounted first non-insulator layer34′. As for array130first electrode layer48′ is mounted on upper surface36′ of layer34′ in region134. However, in array330first electrode layer48′ comprises, by way of example, two separate conducting sheets mounted on two separate sub-regions comprising region134. In addition to first electrode layer48′ and first non-insulator layer34′, array330comprises second non-insulator layer40′, and junction layer46′, herein also referred to as first junction layer46′, formed by the contact between layers34′ and40′.

Between electrode layer53′, comprising disc electrodes50′, and second non-insulator layer40′ there is a third non-insulator layer332. By way of example discs50A′,50B′ of disc electrodes50′ are shown inFIG. 5B. A lower surface334of the third non-insulator layer contacts upper surface42′ of the second non-insulator layer, so forming a second junction layer336between the upper two non-insulator layers. Disc electrodes50′ are mounted on an upper surface338of third non-insulator layer332.

As for array130all cells of array330are substantially similar in configuration and operation, and each cell of array330is defined by a particular disc electrode50′. Thus, a cell340defined by disc electrode50B′ comprises the electrode, and sections of third non-insulator layer332, second junction layer336, second non-insulator layer40′, first junction layer46′, and first non-insulator layer34, the sections lying below the electrode. As for array130, cells in array330use portions of region134to form a conducting path to electrode layer48′.

Cells of a multiple junction array, such as those exemplified above with reference toFIGS. 5A and 5Bare capable of assuming more than two stable states, so that each cell is able to store information in a “multi-nary” format. As is explained below, a cell in an array having j junctions, where n is a positive integer, can have up to 2jdifferent stable states, and such a cell is able to store information in a “2j-nary” format. For example, a cell with 3 junctions may be configured to have eight different stable states, so being able to store information in an octal, i.e., base eight, format.

Referring toFIGS. 1-5B, memory diode cells in arrays of such cells comprise a first and second electrode layer, and two or more non-insulator layers. In each array, at least one non-insulator layer has a sufficiently high ionic conductivity to enable migration of ions across the layer, i.e., in the z-direction, at an operating temperature of the cells of the array, the ionic migration typically occurring during polarization of the layer. The operating temperature of the cells is typically in the range of approximately 20° C.—approximately 30° C., although operating temperatures below and above this range are possible, depending on the mobility of the ions in the non-insulator layers.

A non-insulator layer may be thick (≧1 μm), such as in the case where the layer also acts as a substrate. Alternatively, the layer may be thin (<1 μm), and so does not typically act as a substrate. For an array wherein all layers are thin, the array may typically be formed on an insulator substrate.

A non-insulator layer with the sufficiently high ionic conductivity referred to above is herein termed an operational non-insulator layer, or just an operational layer. Thus, there is at least one operational layer in an array of memory diode cells. An operational layer also has some electronic conductivity, or is able to conduct electrons or holes injected to the layer, so that the layer is not completely insulating. In other words, an operational non-insulator layer may be an ionic conductor or solid electrolyte (SE) with a small electronic conductivity, or a mixed ionic electronic conductor (MIEC) with a relatively high ionic conductivity, comparable or even larger than the electronic conductivity. Typically, the operational layer has an ionic transference number equal to or greater than 0.5 and is less than 1. While the ionic transference number is less than one, it may be only slightly less than one. For example, the ionic transference number may be approximately 0.999,999, corresponding to a deviation from one of 1 part per million (ppm), or approximately 0.999,999,999, corresponding to a deviation of 1 part per billion (ppb), or it may be even closer to 1 than the 1 ppb deviation.

In the claims and in the description, the ionic transference number of a material is assumed to be the fraction of the total current carried by mobile ions of the material. For example, an ionic transference number of 0.5 means that 50% or ½ of the total current in a material is carried by mobile ions of the material.

Non-insulator layers which do not correspond to the operational definition given above, herein termed non-operational layers, typically comprise semiconductors. In some embodiments, a non-operational layer may comprise a metal. Non-operational layers have electronic conductivity with substantially no ionic conductivity, so that their ionic transference number is equal to, or approaches, 0.

Operational and non-metallic, i.e., semiconductor, non-operational layers may have their respective electronic conductivity configured to be p-type, where the material of the layer has a preponderance of holes, n-type, where the material has a preponderance of electrons, or the material may be intrinsic, i-type, where the electrons and holes have approximately equal concentrations.

Layer Formation

The layers of the arrays, i.e., the non-insulator layers and the two electrode layers, may be formed by any suitable method known in the art. Such methods include, but are not limited to, physical vapor deposition (PVD), chemical vapor deposition (CVD), sputtering, pulsed laser deposition (PLD), ion or e-beam deposition, thermal evaporation, molecular beam epitaxy (MBE), and metal-organic chemical vapor deposition (MOCVD). Alternatively, the layers may be deposited by wet or dry chemical routes including sol-gel processing methods, spin coating, dip-coating, and atomic layer deposition (ALD).

The different layers may be patterned according to a required device layout structure using conventional micro- or nanofabrication processes such as photolithography, e-beam lithography, wet or dry etching, imprint lithography, or any other suitable patterning system known in the art. As exemplified above, array layers may be deposited on an insulating substrate. Alternatively, one of the array layers may be configured as a substrate. Unlike other memory devices, which require application of an external electric field to one or more layers of the device after deposition of the layers so as to render the devices operable, layers of devices of the present invention do not require application of any external electric field, after layer deposition, for rendering the devices operable.

Junctions

Junctions of memory diode cells, such as junctions formed in junction layers46,46′,159,236, and336are electrified junctions that are formed between two non-insulator layers, so that a space charge is formed in the region of the junction. For non-metallic non-insulator layers, the layers may be configured to be p-type, n-type, or i-type, provided that the junction formed is one of a p-n, i-p, or i-n junction. In addition, at least one of the non-insulator layers is an operational layer. If one of the non-insulator layers is metallic, the other non-insulator layer is an operational layer, and may be p-type, n-type, or i-type.

In the case wherein the junction is formed of two operational layers, the space charge formed at the junction may reside on both sides of the junction in both layers. In the case wherein the junction is formed of one operational layer and one non-operational layer, more of the space charge typically resides in the more insulating layer, which is usually the operational layer.

Layers

Possible materials for operational non-insulator layers comprise (but are not limited to) materials with the compositions given in Listing I:

Possible materials for the non-operational non-insulator layers comprise (but are not limited to) materials with the compositions given in Listing II:

The electrodes, including their bonding layers, may comprise any suitable conducting material. Possible materials for the electrodes comprise (but are not limited to) materials with the compositions given in Listing III:

Possible materials for an insulating substrate comprise (but are not limited to) materials with the compositions given in Listing IV

EXAMPLES

Single cells having p-n junctions were prepared as follows. A first cell corresponded to a cell of single film array30, a second cell corresponded to a cell of dual film array130(FIG. 1andFIG. 2).

SrTiO3thin layers (˜80 nm or ˜160 nm thick), doped with Fe or Nb, were deposited on polished 1.4% Nb-doped (single film configuration,FIG. 1) and undoped (dual film configuration,FIG. 2) SrTiO3(100) single crystals, 1×1 cm2in area and 0.5 mm thick, purchased from Crystal Gmbh, of Berlin, Germany. The layers were deposited by pulsed laser deposition (PLD) using commercial 0.1% Fe or Nb-doped SrTiO3ceramic targets purchased from SCI Engineering Inc. of St. Charles, Mo. The layers were grown in oxygen at a pressure of 55 mTorr (single film configuration) or in high vacuum at ˜10−6Torr (dual film configuration), and at a substrate temperature of 700° C.

6000 or 3000 pulses of a KrF excimer laser (λ=248 nm) with an energy flux of 1 J/cm2and a repetition rate of 3 Hz were shot at the targets for the single and dual film junction configurations, respectively. The deposition rate was approximately 0.27 Å per pulse, respectively, giving ˜160 or ˜80 nm thick layers in the single and dual film junction configurations.

Thus, first and second non-insulator layers34,40(FIG. 1) of the single film array respectively comprised 1.4% Nb-doped SrTiO3(0.5 mm thick) acting as a substrate, and 0.1% Fe-doped SrTiO3epitaxial film (˜160 nm thick). The Nb-doped SrTiO3was n-type, the Fe-doped SrTiO3was a mixed ionic electronic conductor at ambient temperatures, wherein the ionic conductivity was by negatively charged oxygen ions, and the electronic conductivity was predominantly by holes, i.e., was p-type.

For each of the cells, electrode layers were formed by first sputtering a Ti bonding layer, (˜20 nm thick) on the non-insulator surface to which the layer was to be attached, and then sputtering Pt contacts with a thickness of ˜100 nm onto the Ti bonding layer.

Thus, for the single cell corresponding to the single film array, second electrode layer53comprised a given disc electrode50having a bonding layer51that was formed as a 1 mm diameter contact, and consisted of ˜100 nm Pt on ˜20 nm Ti. Second electrode layer53was formed on the upper surface of the 0.1% Fe-doped SrTiO3epitaxial film, corresponding to upper surface42of second non-insulator layer40. First electrode layer48and bonding layer49comprised a large contact consisting of ˜100 nm Pt on ˜20 nm Ti. The first electrode layer, i.e., the large contact, was formed on the lower surface of the 1.4% Nb-doped SrTiO3(0.5 mm thick) substrate corresponding to lower surface38of first non-insulator layer34.

For the single cell corresponding to the dual film array, second electrode layer53′ and first electrode layer48′ were both formed as 1 mm diameter contacts consisting of ˜100 nm Pt on ˜20 nm Ti, the titanium acting as bonding layers51′ and49′. Second electrode layer53′ was formed on the upper surface of the 0.1% Fe-doped SrTiO3epitaxial film, corresponding to upper surface42′ of second non-insulator layer40′. First electrode layer48′ was formed on the upper surface of the 0.1% Nb-doped SrTiO3epitaxial film, corresponding to region134of upper surface36′ of first non-insulator layer34′.

FIG. 6shows schematic X-ray diffraction diffractograms of the non-insulator layers of the single cells, according to an embodiment of the present invention. The diffractograms were prepared before the electrode layers were attached to the cells. The non-insulator layers grew epitaxially on the substrates, as demonstrated by high resolution X-ray diffraction (HRXRD) diffractograms210and212. As shown by diffractogram210, the only diffraction peaks observed are from reflections from crystallographic planes parallel to the substrate (100) planes, i.e. the (100), (200) reflections. Regions of other crystallographic orientations or additional crystal phases are not detected, confirming that the Fe-doped SrTiO3layer grew epitaxially on the (100) Nb-doped SrTiO3(100) substrate.

The high resolution scan in the vicinity of the (200) reflection, presented in diffractogram212, was analyzed using extended kinematic approximation approach. The intense and narrow signal indicates high structural perfection of the grown layer with d-spacing homogeneity across the layer. The dispersion parameter of d-spacing fluctuations was obtained from the HRXRD, σ=0.005 Å. The intensity fringes observed in the high resolution scan indicate high structural quality and an atomically-smooth interface with the substrate. A film thickness of 164 nm was calculated from the intensity fringes.

FIGS. 7A and 7Bshow schematic current vs. voltage graphs for a memory diode cell, according to an embodiment of the present invention. The graphs were generated by measuring the single cell of the single film configuration, described above. The inventor found similar results to those of the single film configuration for the dual film configuration.

The current-voltage (I-V) characteristics of the junction of the cell were measured using a Keithley 2635 source-meter. The voltage was applied in sweep or alternate modes. In the sweep mode the voltage may start from −3 volts and may increment in a stepwise fashion every 0.01 volt to +3 volts; once it reaches +3 volts it may start to sweep back to ˜3 volts. In the alternate mode, the voltage alternates between +X and −X volts, the value of X starting at 3 and changing by 0.01 volt until it reaches zero. After each voltage change (in both the sweep and the alternate modes) the new voltage was held constant for 600 ms. All I-V measurements were carried out at ambient conditions.

A graph300illustrates the measurements on a linear scale. A graph302illustrates the measurements on a semi-logarithmic scale. In graph302, current values to the left of minimum current cusps304,306, and308are negative, and current values to the right of the cusps are positive. For clarity, in the following explanation, the single film cell is assumed to be similar to a cell in array30(FIG. 1), and the explanation uses reference numerals from this array.

The voltage measurements assume that first electrode layer48, i.e. the electrode layer connected to the n-type Nb-doped SrTiO3layer, is at a potential of 0 volts, and that the potential on second electrode layer53, i.e., the electrode layer connected to the p-type Fe-doped SrTiO3layer, varies between +3 volts and −3 volts. When the second electrode layer has a positive voltage, the cell is forward biased; when the second electrode has a negative voltage, the cell is reverse biased.

Curves310and312illustrate measurements made on the cell in the alternate mode. The curves illustrate that in the alternate mode, the cell rectifies, with negative polarity (reverse bias) currents on the order of −1 to −10 nA between −0.5 and −3 volt, and positive polarity (forward bias) currents of up to +0.2 mA at +3 volt. The onset voltage for the current increase in forward bias is about +2 volt. In the alternate mode the current goes through a zero crossing point, i.e., I=0 when V=0 and vice versa, and there is no hysteresis displayed.

In contrast, the I-V measurements in the sweep mode display a prominent hysteresis between forward (from −3 to +3 volts) and reverse (from +3 to −3 volts) scans. The hysteresis is visible in the differences between forward scanned curves314,316, and reverse scanned curves318,320. The hysteresis is large; for example, at a voltage of approximately +0.8 V the ratio between the forward and reverse scan currents is approximately 5,000.

The hysteresis in the cell may be used for memory operations, as described hereinbelow. The inventor believes that the following explanation of the hysteresis applies.

If second electrode layer53is set negative, e.g., to −3 volts, junction layer46, in this case a p-n junction, is negatively polarized. I.e., mobile ionic carriers such as oxygen vacancies in the p-type layer shift away from the p-n junction and towards the second electrode layer. As a result, a space charge and a built-in voltage (Vbi) across the junction increase. Consequently, a reverse saturation current (IS) decreases because it depends exponentially on the built-in voltage, according to equation (1):

where k is the Boltzmann constant, and

T is the absolute temperature.

The current (I) that flows through the junction also decreases since, according to the Shockley diode equation (2):

where VDis a voltage across the junction,

n is an ideality factor of the junction (typically between 1 and 2), and

k and T are as defined for equation (1).

In this situation, the junction is in a low current—high resistance state, corresponding to forward curves314,316.

In contrast, if second electrode layer53is set positive, e.g., to +3 volts, junction layer46is positively polarized. I.e., mobile ionic carriers shift towards the p-n junction. As a result, the space charge and built-in voltage across the junction decrease, the reverse saturation current increases, and the current flowing through the junction (at a given voltage) increases. In this situation the junction is in a high current—low resistance state, corresponding to reverse curves318,320.

The two states of the junction are stable, and may be used to store binary information.

FIG. 8Ais a schematic diagram illustrating a computing system400using an array of memory diode cells, andFIG. 8Bis a flowchart420of steps used by computing system400in addressing a cell in the array, according to embodiments of the present invention.

Computing system400comprises a processing unit (PU)402, which may be any processing unit known in the art. PU402is assumed to be coupled to an array of memory diode cells configured as described herein. By way of example the array in system400is assumed to comprise array30(FIG. 1).

For simplicity, the steps in flowchart420refer to a given cell32in array30constructed according to the single film configuration example described above, and first electrode layer48is assumed to be at a potential of 0 volts. Those of ordinary skill in the art will be able to adapt the explanation herein,mutatis mutandis, for cells of other embodiments of the present invention, and wherein the potential of first electrode layer48differs from zero.

By way of example, the low current—high resistance state described above is assumed to represent a “1” or “set” state, and the high current—low resistance state is assumed to represent a “0” or “reset” state.

In a write step422PU402writes a 1 to the cell by polarizing junction46negatively, for example by applying −3 volts to second electrode layer53. Alternatively, PU402writes a 0 to the cell by polarizing junction46positively, for example by applying +3 volts to second electrode layer53. The voltages applied to second electrode layer53, −3 or +3 volts, are termed the write voltages of the cell.

In a state step424, the cell is in one of its two possible states, according to the polarization applied in write step422. If the cell is in its 1 state, reverse curves318,320apply. If the cell is in its 0 state, forward curves314,316apply.

In a read step426, PU402applies a voltage, smaller in magnitude than the write voltages, to first electrode layer48. The voltage applied is herein termed the read voltage, and is used to determine if the forward or reverse curves apply to the cell. On application of the read voltage, PU402measures the current generated by the cell, and the measured current provides an indication to the processing unit as to which of the two possible curves apply to the cell, so determining the state of the cell. Thus, PU402ascertains the state, 0 or 1, stored in the cell. In some embodiments, after reading the stored state, write step422may be repeated to re-write the cell to its state in step424.

As a first example, assume the read voltage is approximately +0.8 V, and that the write voltages are as given above. Referring to graph302, if the current measured is approximately 10−11A, then forward curve316applies, and the cell is in its low current—high resistance, or 1, state. If the current measured is approximately 10−8A, then reverse curve320applies, and the cell is in its high current—low resistance, or 1 state.

As a second example, the read voltage may be approximately −1.5 V, with the write voltages given above. In this case the current measured may be approximately 10−11A, wherein forward curve316applies, and the cell is in its 1 state, or the current measured may be 10−10A, wherein reverse curve320applies, and the cell is in its 0 state.

Typically, for a given memory diode cell there is an optimal read voltage, which gives a maximum ratio between the currents measured in the two states of the cell. The optimal read voltage is a function of the hysteresis of the cell. For the single film example described above, the optimal read voltage was approximately +0.8 V.

FIGS. 9A and 9Bshow further schematic current vs. voltage (I-V) graphs for a memory diode cell, according to an embodiment of the present invention. The graphs were generated by measuring the single cell of the single film configuration example described above. The methods of measurement used the sweep mode, explained above with reference toFIGS. 7A and 7B. As explained herein, the inventor has found that the hysteresis of a given cell may be altered by applying differing preset voltages to the cell, and thus to the cell's junction, prior to measuring the hysteresis.

A graph500illustrates the I-V measurements on a linear scale. A graph502illustrates the measurements on a semi-logarithmic scale. In graph502, current values to the left of minimum current cusps are negative, and current values to the right of the cusps are positive.

For each set of measurements, a different negative preset voltage was applied to the cell for a preset time period of 20 s, prior to measuring the hysteresis of the cell. The different voltages were −1.0V, −1.5V, −2.0V, −2.5V, and −4.0V. The three curves of graph500, for the voltage values of −2.0V, −2.5V, and −4.0V, and the five curves of graph502, for the five different voltages applied, show that the hysteresis of the cell increased with increasing negative preset voltage applied to the cell.

FIG. 10shows a yet further schematic current vs. voltage (I-V) graph550for a memory diode cell, according to an embodiment of the present invention. The curves of graph550were generated by measuring the single cell of the single film configuration example described above. The methods of measurement used a sweep mode, explained above with reference toFIGS. 7A and 7B, with the difference that instead of sweeping the voltages applied to the cell in a stepwise fashion, the swept voltages were changed at differing constant rates. The inventor has found that the hysteresis of a given cell changes according to the rate at which the cell is swept.

As illustrated in the three I-V curves of graph550, for sweep rates of 20 mV/s, 50 mV/s, and 500 mV/s, as the sweep rate increases, the hysteresis of the cell increases.

The effects on the hysteresis of a memory diode cell, described above with respect toFIGS. 7,9A,9B, and10, enable memory diode cells, implemented according to embodiments of the present invention, to be tuned to have different characteristics. For example, the hysteresis of a given cell may be configured, by having differing preset voltages and/or differing sweep rates, so as to change the optimal read voltage (referred to in the description of flowchart400) for the cell.

Referring back to graph302and graph502(FIGS. 7B and 9B), the curves of the graphs illustrate another characteristic of memory diode cells, apart from their hysteresis, that has been found by the inventor: there is a shift in an open circuit voltage (OCV) value, VOC, between the forward and reverse scans. VOCis the voltage that occurs for each scan at the minimum current point of the curves, i.e., at the cusps of each curve. For example, as illustrated in graph302, the forward scan gives an OCV value at cusp308of approximately −1 V, and the reverse scan gives an OCV value at cusp304of approximately 0 V. Graph502illustrates the same effect for all preset voltages applied prior to measuring the hysteresis. For example, the curve for a preset voltage of −1.0 V has OCVs, at the cusps of the curves, of approximately 0 V and −0.1 V; the curve for a preset voltage of −4.0 V has OCVs of approximately 0 V and approximately −0.3 V.

The shift in OCV, and the fact that at least one of the OCVs for a given curve is non-zero, is in complete contrast to other memory devices known in the art, such as those known as memristors. Other memory devices have a zero crossing point, i.e., I=0 when V=0, and vice versa, for both forward and reverse scans of the devices.

The fact that memory diode cells configured as described herein have non-zero OCVs indicates that such memory diode cells are able to store energy, unlike memory devices known in the art. An explanation for this behavior is provided below.

FIG. 11is a graph600of voltage vs. time for a memory diode cell, according to an embodiment of the present invention. Graph600was produced using measurements on the single film configuration cell example described above. As is described above with reference toFIGS. 7A and 7B, the voltage measurements assume that the first electrode layer (layer48inFIG. 1) connected to the n-type Nb-doped SrTiO3layer is at a potential of 0 volts, and the voltage is measured at the second electrode layer (layer53) connected to the p-type Fe-doped SrTiO3layer.

A battery switchably applied a voltage of −1.5 V to the second electrode layer of the cell (reverse bias configuration). With the switch closed, the battery and cell were in parallel, and the battery “charged” the cell. With the switch closed, an electrometer read the potential across the battery. With the switch open, when the cell “discharged,” the battery was not accessible to the electrometer, and the electrometer read the potential across the cell. With the switch open, the cell was in an OCV configuration. The switching was cycled on and off, so that the electrometer measured the charging and OCV potentials cyclically. Referring to graph302(FIG. 7B) the cycling corresponds to following the left side of curve316from its cusp to −1.5 V, and then from −1.5 V to its cusp.

Graph600demonstrates that repeatedly recycling the memory diode cell continuously returns a repeatable, stable OCV of approximately −0.8 V that is constant over a substantial period of time, many minutes. Similarly, cyclically applying an opposite voltage of +1.5 V to the cell also produces a repeatable, stable OCV that is substantially different from the −0.8 V found above, and is typically approximately 0 V.

The description above with regard to the different values of OCV for a memory diode cell can be applied to a different method for reading the state of the cell, as is exemplified by the description of flowchart700below.

FIG. 12is a flowchart700of steps used by computing system400(FIG. 8A) in addressing a cell in a memory diode cell array, according to an alternative embodiment of the present invention. Except as described below, flowchart700assumes substantially the same conditions as flowchart420(FIG. 8B) so that steps702and704are respectively substantially the same as steps422and424.

In a read step706, which replaces read step426of flowchart400, PU402measures the OCV of the cell, the value of the OCV indicating the state of the cell. For example, referring to graph302(FIG. 7B), if the OCV is approximately −1 V, the cell is in its low current—high resistance, or 1 state; if the OCV is approximately 0 V, the cell is in its high current—low resistance, or 0 state. As for read step426, in some embodiments write step702may be repeated to re-write the cell to its state in step704.

It will be understood that the reading of the OCV by PU402involves negligible current flow through the cell and the reading therefore consumes negligible power and has negligible influence on the information stored in the cell.

FIG. 13is a schematic equivalent circuit diagram of a memory diode cell, according to an embodiment of the present invention. The inventor believes that the following description explains observed properties of a memory diode cell, and the equivalent circuit is based on this explanation.

The energy storage capacity of a cell is connected with its chemical capacitance, which arises from field-induced stoichiometry modifications in one or more of layers that form the junction of the cell. When a voltage is applied to the cell, mobile ionic defects such as oxygen vacancies redistribute according to the field direction and as a result the cell becomes polarized. In the single film example described above the energy storage is assumed to come from the chemical capacitance of the p-type Fe-doped SrTiO3layer, and the property of chemical capacitance applies to all operational layers, as defined herein. Thus, cells having junctions with at least one operational layer are able to store energy by becoming polarized, so changing the chemical capacitance of the layer. The chemical capacitance change may be accomplished by applying a voltage to, or passing a current through, the layer.

In an equivalent circuit800, a memory diode cell is assumed to comprise an ionic rail802and a parallel electronic rail804. The ionic rail comprises a resistor806in series with a chemical capacitor808. The electronic rail comprises a resistor810in series with a diode812. One side of the parallel combination of rails is connected to a first terminal814of the cell, and a second side of the parallel combination is connected, via a series resistor816to a second terminal818of the cell. The first and second terminals correspond to the first and second electrodes of the cell.

The OCV shifts described above result from the polarization effect occurring in the cell. When an external power source applies a negative voltage to the cell, i.e., if terminal814is set negative, assuming terminal818is zero, diode812behaves as an open circuit allowing only a very small current (the reverse current) to pass through the electronic rail. As a result, some current goes into the ionic rail and charges capacitor808, i.e., ionic current is stored as charge in capacitor808. If the cell is disconnected from the external power source immediately after charging the chemical capacitor, the capacitor remains charged—giving rise to a negative OCV as observed in the forward I-V scans presented in graphs302and502(FIGS. 7 and 9B). When positive voltage is applied to the cell the diode behaves as a closed circuit and (electronic) current passes through the electronic rail, the ionic rail becoming inactive. This explains the zero OCV in the reverse I-V scans in graphs302and502.

Consideration of the description above shows that a memory diode cell having a single junction can be in one of two different stable states. The states are defined by a hysteresis characteristic of the cell, and which of the two states the cell is in may be determined by measuring where on a hysteresis curve the cell is, for example by measuring the current generated for a given read voltage, or by measuring an open circuit voltage of the cell.

In general, a memory diode cell having j junctions, where j is an integer greater than or equal to 1, can be in one of 2jstable states, each of the states being defined by respective hysteresis characteristics generated by the j junctions. As explained above, the hysteresis may be configured to be different, so that each of the 2jstable states may be configured to be different. The different 2jstable states may be determined by measuring which of the 2jdifferent currents is generated by a given read voltage, or by measuring which of the 2jdifferent open circuit voltages is generated.

Memory diode cells of the present invention comprise junctions, such as p-n junctions, as is explained above. Cells based on such junctions have considerably smaller cross-talk to adjacent cells in an array of such cells than cells based on other junctions, such those of metal-insulator-metal devices.