Impedance-matched write driver circuit and system using same

Embodiments of the present invention relate to an impedance-matched write driver circuit which comprises a voltage source, a write driver circuit electrically coupled to the voltage source, a signal input coupled so as to effect the output of the write driver circuit, and an impedance matching circuit electrically coupled to the write driver circuit, wherein the impedance matching circuit is enabled to damp the output oscillations in the output of the write driver circuit. Importantly, the impedance of the impedance-matched write driver circuit is selectable by component selection or by logic. Another embodiment of the present invention is directed to a system, e.g., a magnetic disk storage unit that makes use of the write driver as described herein.

RELATED U.S. APPLICATIONS

This application claims priority to the commonly-owned co-pending provisional patent application, U.S. Ser. No. 60/434,868, entitled “IMPEDANCE-MATCHED WRITE DRIVER,” filed Dec. 19, 2002, and assigned to the assignee of the present invention and this application is hereby incorporated by reference.

FIELD OF THE INVENTION

The present invention relates to the field of hard disk memory storage devices.

BACKGROUND OF THE INVENTION

Magnetic hard disk drives continue to provide ever more storage space and faster access, as well as data transfer and retrieval times. Where once 100 kilobytes of stored data occupied a ten inch diameter footprint, 2.5 inch diameter disks now exceed 100 Gigabytes and information transfer and access times have undergone similar order-of-magnitude improvements.

One of the reasons for the continuing improvement is higher disk rotation speeds. Another reason is the continuing shrinkage of the size of a data bit recordable on the magnetic medium that coats the surface of a typical hard disk platter. The shrinking data bit footprint can be attributed to the ability to accurately position the reading and writing head close to the recording medium. The closer the head, the smaller the magnetic signal needed to define a recorded bit.

While there are mechanical and aerodynamic achievements behind the ability to get the read/write head to within microns of a recording surface, the electrical challenges have been no less daunting. Very precise control of write currents, for example, is necessary to write (record) a bit of uniform size to the medium. The uniform size of a bit is necessary in order to fit the highest possible number of bits onto a given platter surface size.

Access times, the time required to find a particular set of data bytes on the recorded surface, depend on the speed of disk rotation and on the speed with which the read/write head, mounted on the head arm, can be moved to a particular track on the platter. That head motion is easiest to attain with the lightest possible head and arm weights.

Conventional artFIG. 1Aillustrates a typical hard disk drive. The recordable medium is coated on the surface of platters101where head arm102controls the position of read/write head105. Read/write head105records and reads data written to the recordable medium. Write current, sufficient to magnetize the appropriate bit of recordable medium, is sent to the head from pre-amp/write driver106. The position of head arm102is driven by arm actuator103under control logic from logic board104. It is noted here that there are many existing configurations of hard disk drives with varying numbers of platters on a common spindle and an accompanying number of head arms, one for each recordable medium surface. It is also noted that, as the numbers of platters increases, the numbers of arms also increases, and the inertial load on the moving arm actuator increases.

Transfer time, the time required to read or write a given amount of data, depends on many elements, of which disk rotation speed is a significant part. Another significant contributor to transfer time in data writing is the speed with which write current to the write head can be switched on and off.

While higher power electronics in the head arm and read/write head can contribute to higher rates of data writing, higher powers typically entail larger and heavier components. A larger and heavier pre-amp/write driver (106inFIG. 1) of which there is one for each head on each arm, would force an increase in the inertia of head arms102, necessarily slowing access times.

It is noted here that write driver106is, in this illustration, mounted on head arm102. The mounting location of Write driver106is the result of tradeoffs made in the design process. The farther the write driver is located from the write head, the more effect the impedance of the wires connecting the two will have on the write signal, thereby reducing its operational frequency. In general, shorter wires result in theoretically faster signals. However, the mass of the pre-amp/write driver contributes to the moment of inertia of the head arm. Generally, locating the pre-amp/write driver closer to the write head means locating it farther from the arm spindle107and vice versa. With more mass located farther from the spindle, the stronger, and heavier, the arm must be. The heavier the arm and the farther the pre-amp/write driver is from the arm spindle107, or the heavier the pre-amp/write driver, the more the actuator energy required to move the arm from disk track to disk track rapidly and the higher demand on the arm actuator for precision control of the head arm.

Conventional artFIG. 1Billustrates a write driver circuit, in this case an “H-bridge” model of a typical write driver. An “X” logic signal or a “Y” logic signal, representing logic level commands for a logical “1” or “0” in the recorded medium, are sent to the driver from upstream logic. Amplifying transistors111,112,113and114are switched on or off as appropriate to control power supply voltage Vcc,108, in the appropriate direction through the write head, represented inFIG. 1Bby load resistances115and116and also load inductance117. It is noted that the output load is approximated in this illustration. There are any number of different load models associated with existing write heads.

As demand for speed of writing to the recordable medium seeks ever faster write speeds, impedance in write drivers, connecting wires and in write heads limits switch-on, switch-off rates. A mismatch of impedances between the write driver and the write head, and associated wiring, often results in signal reflections and jitter which slows the attainment of the proper signal level to the write head. The proper write signal level is necessary to achieve a subsequently readable written bit that is also contained fully within the allowable bit footprint in the recorded medium.

Impedance mismatches occur because, when the one of the bottom transistors in the H-bridge, illustrated inFIG. 1B, is turned on by the appropriate logic input, the output impedance of the transistor becomes high and the signal is reflected at the output terminal. The output current thus has a large overshoot and ringing, or oscillation, and the overshoot and ringing, as discussed above, decrease the achievable data rate.

In order to match impedances as well as possible, drive designers choose from a selection of available pre-amp/write drivers, trading off between signal speed and quality and pre-amp/write driver location on the head arm. The design process can be iterative and slow and can result in compromises in component selection that result in non-optimum hard disk drive performance. Furthermore, maintaining a selection of components in order to accommodate differences between designs can be costly to the drive manufacturer.

SUMMARY OF THE INVENTION

Accordingly, an impedance matching write driver circuit and system for use are presented herein. Embodiments of the present invention provide a circuit that can enable the hard disk designer to select the proper impedance to match the characteristics of the write head in order to reduce reflections and ringing in the write current output by the write driver.

Embodiments of the present invention relate to an impedance-matched write driver circuit which comprises a voltage source, a write driver circuit electrically coupled to the voltage source, a signal input coupled so as to effect the output of the write driver circuit, and an impedance matching circuit electrically coupled to the write driver circuit, wherein the impedance matching circuit is enabled to damp the output oscillations in the output of the write driver circuit. Importantly, the impedance of the impedance-matched write driver circuit is selectable by component selection or by logic. Another embodiment of the present invention is directed to a system, e.g., a magnetic disk storage unit that makes use of the write driver as described herein.

These and other objects and advantages of the present invention will become obvious to those of ordinary skill in the art after having read the following detailed description of the preferred embodiments which are illustrated in the various drawing figures.

DETAILED DESCRIPTION

FIG. 2illustrates an impedance-matched write driver circuit in accordance with one embodiment of the present invention. InFIG. 2, voltage source208supplies voltage to current driver transistors211,212,213and214which control direction of current through the output load, modeled by resistances215and216and inductance217. It is noted here that the output load is a function of the magnetic read head being driven by the write driver as well as the magnetic recording medium being written to. Voltage source208also provides voltage to an impedance matching circuit here illustrated by transistors201,202,203and204. Voltage source208is connected to the base connections of transistors201and202as well as their collector connections.

The emitter connections of transistors201and202are connected, in this embodiment, through resistors221and222, to the output load. Transistors203and204are collector connected to the output load and their base connections are connected to an “X” and a “Y” input, respectively, the same inputs are connected to the base connections of current driver transistors213and214. The emitter connections of transistors203and204are connected to ground through band gap reference219. It is noted here that “X” and “Y” inputs, as used in this illustration, are meant to refer to the points where logical “0” and logical “1” inputs are input. The logical “0” and logical “1” inputs are the relative high and low voltages of digital signals. In this embodiment of the present invention, “X” and “Y” are the input of the digital logical signal that controls what is written to the magnetic recording medium of the storage device.

The bridge constructed from transistors201,202,203and204forms an impedance matching circuit. Excessive signal reflection and ringing are the result of mismatched impedance between the write driver and the load. In order to reduce the effects of mismatched impedance during the period when the current driving transistors in the H-bridge,211and214or212and213, are turned on, the output impedance matching circuit drives the impedance to less than 100 ohms. This embodiment of the present invention employs one technique for accomplishing this but it is noted that there are other techniques employed by other embodiments.

When the signal input to X is high and the signal input to Y is low, transistor211and transistor214are turned on. The write current flows from IWxto IWy. Transistor204is also turned on. The output impedance, Ro, is given in this embodiment of the present invention by the relationship:
Ro=(R2+1/gm(Q9)),

and where 1/gm (Q9) refers to the instantaneous transconductance of transistor202.

An illustration of another embodiment of the present invention is found inFIG. 3. Here, impedance matching is achieved by the cascading of transistors301and302,303and304,305and306, and307and308. Here, too, the “H-bridge ” write driver comprises cascaded transistors301and302, and303and304, with transistors309and310. IWx, the write current for “X”, is supplied when the X inputs,331and351, are high, turning on cascaded transistors301and302, as well as transistor310. IWy, the write current for “Y” is supplied when “Y” inputs,332and352, are high, turning on cascaded transistors303and304and transistor309.

In the embodiment illustrated inFIG. 3, impedance matching is accomplished in the damping current circuit implemented with transistors305through308in conjunction with resistors311and312. When the write signal is high at “X”,331and351, IWXis damped by damping current I2, at322. When the write signal is high at “Y”,331and352, IWYis damped by damping current I1, at321.

In order to maintain precise control over the recorded data bit footprint, the write driver maintains write current (Iw) accuracy within the desired current range of the write head in its application. Damping circuit current I2, at321, is given by:
I2={1.1Ro/Ra−Rb/(40Ra)}Iw/(1+Ro/Ra)(=DcIw).  (1)

In the circuit illustrated in this implementation, Rb refers to the resistance of resistor341, and Ra refers to the resistance of damping resistors311and312. The damping coefficient, Dcis set, in this implementation, to 0.1. The actual write current, IWXor IWY−, is equal to the Iw, which is the reference current, times 40.

The voltage drop from point331to point328is, in this embodiment, equal to the voltage drop from point “C” to point328as shown in the following relationships.
Vbe(301)+Vbe(302)+(I1+I3)Ro=Vbe(333)+Iw Rb/40−Vbe(339)+Vbe(307)+Vbe(308)+Ra I2  (2)

Then relationship (2) is written in the form:
(I3+I1)Ro=Iw Rb/40+Ra12  (3)

From the Kirhhoff's current law at point328,
1.1Iw=I1+I2+I3  (4)

Relationship (4) is written in the form:
I1+I3=1.1Iw−I2  (5)

The voltage drop from point331to point329is equal to the voltage drop from point “C” to point329
Vbe(Q3)+Vbe(Q2)=Vbe(Q33)+Iw Rb/40−Vbe(P9)+Vbe(Q22)+Vbe(Q21)+Ra I1  (6)

The effective size of the impedance matching transistors, in this illustration is determined by the transistor size ratio which is, in this embodiment:
Q3,301:Q22, 305=Q2, 302:Q21, 306=10:1.

Assuming Vbe(333)=Vbe(339), relationship (6) thus is written in the form:
I1=2Vt{1n(I3/10I1)}/Ra−Iw Rb/40Ra(7)

It is noted that one possible requirement for write driver/preamplifiers is a write speed on the order of 800 Mbps (million bits per second). It is also noted that a desirable feature of a write driver is a favorable power supply rejection ration (PSRR). Embodiments of the present invention achieve both of these attributes.

FIG. 4illustrates a circuit implementation of an impedance matching circuit to dampen an output for a write driver such as illustrated inFIG. 3. In this illustration, there are shown three different impedance matching circuits which are selectable based on the signal levels of impedance control inputs Z1at401, Z2at402and Z3at403. Impedance matching circuits411,412and413provide the same impedance balancing and signal damping as the impedance matching circuit illustrated inFIG. 3. It is noted here that the four transistors illustrated in each impedance matching circuit corresponds and is analogous to transistors305,306,307and308inFIG. 3. However, selection of resistance values for resistors421,422,423,431,432and433result in different impedance values for each of the impedance matching circuits. It is noted that, by designing an appropriate value for the resistors in manufacture of the semiconductor device which comprises some embodiments of the present invention, the same semiconductor device can be employed in a wide variety of hard disk drives. The resultant advantages of this can be a reduced parts inventory and a speedier design process.

InFIG. 4, input Z1,401, selects impedance matching circuit411; Z2,402, selects impedance matching circuit412; and Z3,403, selects impedance matching circuit413. As discussed above, resistor value selection determines the actual impedance balance of each circuit. However, in the embodiment of the present invention discussed here, values are chosen which result in available impedances of 50 ohms, 74 ohms, and 100 ohms. The balancing impedance is provided at IWX,451, and IWY,452, which correspond with points329and328, respectively, inFIG. 3.

FIG. 5illustrates an implementation of an impedance selection circuit in accordance with an embodiment of the present invention. The illustration here can either be of a portion of the semiconductor device which comprises the write driver or it may be of a discrete component of the write driver system. Impedance control bit “0” (ZCONT0),501, and impedance control bit “1” (ZCONT1),502, are, in this embodiment, the controlling inputs which control the matching impedance discussed above.

By selection of a high signal on both ZCONT0and ZCONT1, a high on one and a low on the other, or a low signal on both, four impedance levels can be selected: Z0at510, Z1at401, Z2at402and Z3at403. It is noted that Z1, Z2and Z3are the same impedance selection inputs as shown inFIG. 4. In this embodiment, the selectable impedances are open (zero), 50 ohms, 74 ohms and 100 ohms.

Impedance selection, in this embodiment, is made by switching on or off selections circuits520through523. Each circuit is identical and serve to implement the “two to four” translation required to make the selection with two available input bits. It is noted that impedances can be selected by component selection in manufacture that results in the desired ZCONT0and ZCONT1states, or can be selected by logic in implementations where the desired impedance matching changes within a manufactured hard disk device.

In the embodiment of the present invention discussed herein, there are four selectable impedances The following table illustrates the balancing impedances to a write driver that result from the input states of ZCONT0and ZCONT1.

FIG. 6illustrates a modeled resultant output of a write driver employing embodiments of the present invention.FIG. 6is a graph in which ordinate601measures current in amps and abscissa602is time measured in nanoseconds. The write head model used to generate the performance curves illustrated is a typical resistance/inductance (RL) write head circuit. Output signal603illustrates the behavior of a write driver without impedance matching. It is noted that initial pulse onset is seeking a signal strength of 40 mA for a period of approximately ten nanoseconds. It is noted that an overshoot to a higher signal strength can result in an adverse performance of the write head. Here signal curve603initially overshoots to 60 mA then undershoots by ten mA,607, taking nearly the entire pulse period to recover and never fully damping out at the desired signal strength. This undamped performance repeats with every change of write signal, such as at608.

Curve604illustrates the performance of a write driver incorporating an embodiment of the present invention. The impedance matching balances the write driver output with an impedance of 100 ohms. With the same signal input as was used for curve603, curve604overshoots by a smaller amount, in this illustration four mA, and damps to within two mA within two nanoseconds. Curves605and606illustrate the output signal behavior of the impedance-matched write driver with a balancing impedance of 74 ohms and 50 ohms, respectively.

It is noted that the modeled curves presented inFIG. 6are only for illustration and embodiments of the present invention provide different behaviors in different applications. In each case, however, the addition of impedance matching results in a much improved write head performance with a smaller signal overshoot and a shortened damping time to desired signal strength. These combine to provide more rapid and more accurate data bit writing to the recordable medium of the hard disk device.

A typical application for a hard disk employing an embodiment of the present invention is in a computer system. A configuration typical to a generic computer system is illustrated, in block diagram form, inFIG. 7. Generic computer700is characterized by a processor701, connected electronically by a bus750to a volatile memory702, a non-volatile memory703, possibly some form of data storage device704and a display device705. It is noted that display device705can be implemented in different forms. While a video CRT or LCD screen is common, this embodiment can be implemented with other devices or possibly none. Bus710also connects a possible alpha-numeric input device706, cursor control707, and communication I/O device708. An alpha-numeric input device706may be implemented as any number of possible devices, but is commonly implemented as a keyboard.

It is noted here that permanent data storage device704is, in implementations pertinent to embodiments of the present invention, a hard disk memory device employing an impedance-matched write driver. However, embodiments of the present invention can operate in systems such as autonomous servers, dedicated MP3 players and other stand alone systems, obviating the need for a directly connected display device and for an alpha-numeric input device. Similarly, the employment of cursor control707is predicated on the use of a graphic display device,705.