Limiter circuit for limiting pulsive noises

A limiter circuit comprises a low-pass filter which passes only a modulation signal out of the modulation signal having pulsive noises superimposed thereon and circuit means for supplying the modulation signal extracted by the filter to current source circuits for a limiter differential amplifier to control the current source circuit for the limiter differential amplifier in accordance with a waveform of the input modulation signal applied thereto.

BACKGROUND OF THE INVENTION 
1. Field of the Invention 
The present invention relates to a limiter circuit suitable for use in a 
vehicle mounted receiver such as car radio or vehicle mounted CB 
transceiver, and more particularly to a limiter circuit for limiting 
pulsive noises superimposed on a modulation signal. 
2. Description of the Prior Art 
A vehicle mounted receiver such as an AM/FM radio receiver or CB 
transceiver is apt to be influenced by pulsive noises generated from an 
internal combustion engine of the vehicle. 
Accordingly, the vehicle mounted receiver usually incorporates in a 
demodulator a limiter circuit for limiting the pulsive noises. 
A limiter circuit as shown in FIG. 1 has been known as the limiter circuit 
for that purpose. In FIG. 1, there are connected between an anode of a 
detecting diode 11 of a detector circuit, that is, a detection signal 
input terminal T.sub.1 and a detection signal output terminal T.sub.2 a 
limiting diode 21, dividing resistors 22 and 23 for dividing a modulation 
signal (demodulation signal) which is developed at the input terminal 
T.sub.1 of the detection by the detecting diode 11 and a D.C. voltage to 
supply the divided signal and voltage to an anode of the limiting diode 21 
and a filter circuit 30 which comprises resistors 31 and 32 and a large 
capacitance capacitor 33 for extracting only the D.C. voltage from the 
modulation signal and the D.C. voltage applied to an input terminal 
thereof to supply the D.C. voltage to a cathode of the limiting diode 21. 
During normal reception state, the limiting diode 21 is biased to be 
conductive, and it is cut off only when the pulsive noise is superimposed 
on the modulation signal and it exceeds an AM 100% modulation level so 
that the potential at the anode of the limiting diode 21 falls below the 
potential at the cathode thereof by the noise. In this manner, the noise 
is limited. One example of such prior art limiter circuit is disclosed in 
Japanese Patent Publication No. 15224/67 published Aug. 23, 1967 which was 
also assigned to the assignee of the present invention. 
FIGS. 2A and 2B show waveforms for illustrating the operation of the 
limiter circuit. In FIGS. 2A and 2B, numeral 1 denotes a ground potential, 
2 denotes a D.C. bias potential at the cathode of the limiting diode 21, 3 
denotes a D.C. bias potential at the anode of the limiting diode, 4 
denotes a modulation signal at AM carrier 100% modulation, 5 and 6 denote 
pulsive noises superimposed on the modulation signal 4, 4' denotes a 
modulation signal when AM carrier modulation does not reach 100%, and 5' 
and 6' denote pulsive noises superimposed on the modulation signal 4'. 
In the limiter circuit shown in FIG. 1, a limiting level is determined by 
the A.C. voltage (AGC voltage) which depends on the level of the carrier. 
As a result, when the limiting level is set to the modulation signal 
amplitude at the AM 100% modulation as shown in FIG. 2A, the noise can be 
fully limited at the high modulation as shown in FIG. 2A but at the low 
modulation as shown in FIG. 2B the pulsive noise output is large relative 
to the modulation signal and the limiting effect is materially decreased. 
If the limiting level is lowered in order to overcome the above difficulty, 
the modulation signal at the high modulation is limited and the waveform 
of the modulation signal is distorted. Accordingly, the limiting level has 
to have been compromised at an appropriate level. 
Furthermore, as the demand for implementing electronic circuits by IC 
structures increases recently, it may also be desired to implement the 
circuit of FIG. 1 by an IC structure. In this case, the terminals T.sub.1, 
T.sub.2 and T.sub.3 must be provided as terminal pins of the IC. This is 
contrary to the object of the IC of permitting inclusion of as many 
functions as possible with a limited number of IC pins. In addition, 
relatively large capacitance capacitors designated by 13, 24 and 33 must 
be off-chip mounted. 
SUMMARY OF THE INVENTION 
It is an object of the present invention to provide a limiter circuit which 
is easy to implement by an IC structure and a limiting level of which 
changes in accordance with a waveform of a modulation input signal. 
In order to achieve the above object, in accordance with the present 
invention, there is provided circuit means for supplying biasing currents 
for a differential transistor pair of a differential amplifier by separate 
constant current sources and controlling the current sources in accordance 
with the waveform of the modulation input signal.

DESCRIPTION OF THE PREFERRED EMBODIMENTS 
The present invention is now explained in detail with reference to the 
accompanying drawings. FIG. 3 is a circuit diagram of one embodiment of 
the present invention. In FIG. 3, numeral 50 denotes a modulation signal 
source, T.sub.1 denotes a modulation signal input terminal to which a 
modulation signal e.sub.i is applied, and numeral 100 denotes an amplitude 
limiting amplifier circuit which comprises a pair of limiting differential 
transistors 111 and 112, a pair of constant current source differential 
transistors 113 and 114 connected in series with the differential 
transistor pair 111 and 112 to supply bias currents to those transistors, 
and a plurality of resistors 121-126. The base of the transistor 111 is 
connected to the input terminal T.sub.1 and also connected to an operating 
power supply 411 through a biasing resistor 122. The collector of the 
transistor 111 is connected to an operating power supply 412 and the 
emitter thereof is connected to a collector of the transistor 113. The 
base of the transistor 112 is connected to the operating power supply 411. 
The collector of the transistor 112 is connected to the operating power 
supply 412 through a load resistor 125, and also connected to an output 
terminal T.sub.2, and the emitter thereof is connected to the collector of 
the transistor 114. Those emitters of the transistors 111 and 112 are 
connected together through a resistor 121. The base of the transistor 113 
is connected to an operating power supply 413 and the base of the 
transistor 114 is connected to the operating power supply 413 through a 
control terminal T.sub.c1 and a resistor 126. Those emitters of the 
transistors 113 and 114 are connected to a constant current source 
transistor 410 through resistors 123 and 124, respectively. The base of 
the transistor 410 is connected to an operating power supply 414 and the 
emitter thereof in grounded through a resistor 415. Since the transistors 
113 and 114 serve as a constant current source, an input signal current at 
the input terminal T.sub.1 flows through the circuit including the 
transistor 111, the resistor 121 and the transistor 112. Thus, by varying 
bias currents to the transistors 111 and 112, more appropriate limiting 
level can be obtained. 
Numeral 200 denotes a low-pass filter which is connected between the 
modulation signal input terminal T.sub.1 and the control terminal T.sub.c1 
and conducts the modulation signal input e.sub.i to the control terminal 
T.sub.c1 while eliminating the pulsive noises superimposed on the 
modulation signal. The filter 200 may be a conventional one. 
Numeral 300 denotes a bias compensation circuit which compensates for the 
change of bias at the output terminal T.sub.2 when the base potentials of 
the pair of current source differential transistors 113 and 114 in the 
amplifier circuit 100 are controlled by the control signal (modulation 
signal) at the control terminal T.sub.c1 to control the bias currents of 
the pair of limiting differential transistors 111 and 112, that is, 
compensates for the biases to prevent the change of control signal 
V.sub.c1 from appearing at the output terminal T.sub.2. The circuit 300 
comprises differential transistor pairs 311, 312 and 313, 314 which are 
connected in parallel with the differential transistor pairs 111, 112 and 
113, 114, respectively, of the amplifier circuit and of the same circuit 
configuration as those transistor pairs. The bases of the transistors 311 
and 312 are both connected to the operating power supply 411 and these 
emitters thereof are connected together through a resistor 321. The 
collector of the transistor 311 is connected to the collector of the 
transistor 111 and the collector of the transistor 312 is connected to the 
collector of the transistor 112. The base of the transistor 313 is 
connected to the control terminal T.sub.c1 and the collector thereof is 
connected to the emitter of the transistor 311. The base of the transistor 
314 is connected to the operating power supply 413 and the collector 
thereof is connected to the emitter of the transistor 312. The emitters of 
the transistors 313 and 314 are connected to the collector of the constant 
current source transistor 410 through resistors 323 and 324, respectively. 
The resistances of the resistors 123, 124, 323 and 324 are selected to be 
equal so that the current flowing through the transistors 114, 313 and 
113, 314 are equal, and the resistances of the resistors 121 and 321 are 
selected to be equal so that the currents flowing through the transistors 
112, 311 and 111, 312 are equal, whereby a constant bias current 
continuously flows through the load resistor 125. 
In the circuit arrangement described above, the limiting characteristic 
described above is attained by applying the input signal having the 
pulsive noises eliminated by the low-pass filter 200 to the control 
terminal T.sub.c1 as the control signal V.sub.c1. 
Referring to FIGS. 4 and 5, a principle of operation of the present circuit 
is explained. A circuit of FIG. 4A is obtained by eliminating the bias 
compensation circuit 300 from the circuit shown in FIG. 3. When a signal 
51 as shown in FIG. 5A is applied to the control terminal T.sub.c1 through 
the low-pass filter 200, the control signal V.sub.c1 at the control 
terminal T.sub.c1 and the input signal e.sub.i at the input terminal 
T.sub.1 are zero at a time t.sub.1 of the input waveform. Thus, a current 
of I.sub.o /4 flows through each of the transistors 123 and 124, where 
I.sub.o is the constant current from the constant current transistor 410. 
The limiter circuit under this condition can be expressed by an equivalent 
circuit shown in FIG. 4B. Thus, the current of I.sub.o /4 flows through 
each of the pair of limiting differential transistors 111 and 112 and an 
input-output characteristic exhibits symmetric limiting levels 52 and 53 
with respect to zero axis as shown by a curve (ii) in FIG. 5C. A limiting 
level at a time t.sub.1 of an output waveform 51' shown in FIG. 5B is 
determined thereby. At a time t.sub.2 of the input waveform 51, the 
control signal V.sub.c1 and the input signal e.sub.i are at a positive 
maximum value and a current of I.sub.o /2 flows through the transistor 114 
while no current flows through the transistor 113. The limiter circuit 
under this condition is expressed by an equivalent circuit shown in FIG. 
4C. Thus, current of approximately I.sub.o /2 flows through the transistor 
112 of the pair of limiting differential transistors 111 and 112 while 
only small current flows through the other transistor 111. As a result, an 
input-output characteristic is such that an input current which is 
approximately twice as high as that at the time t.sub.1 flows in the 
positive direction while small input current flows in the negative 
direction, as shown by a curve (i) in FIG. 5C. Thus, the limiting level at 
the time t.sub.2 of the output waveform 51' increases by the factor of 
approximately 2 in the positive direction while the limiting level in the 
negative direction is approximately zero. Similarly, at a time t.sub.3 of 
the input waveform 51, the limiter circuit is expressed by an equivalent 
circuit shown in FIG. 4B and an input-output characteristic exhibits a 
curve (ii) in FIG. 5C. At a time 4 of the input waveform 51, the control 
signal V.sub.c1 and the modulation circuit e.sub.i are at negative maximum 
and a current of I.sub.o /2 flows through the transistor 113 while no 
current flows through the transistor 114. The limiter circuit under this 
condition is expressed by an equivalent circuit shown in FIG. 4D. Thus, an 
input-output characteristic exhibits a curve (iii) in FIG. 5C. In this 
manner, for the sine wave input 51 shown in FIG. 5A, the sine wave output 
51' shown in FIG. 5B and the limiting levels 52 and 53 shown by dotted 
curves which vary in accordance with sine wave are obtained. 
In the present circuit, since the limiter levels are set by changing the 
bias levels of the pair of differential transistors 111 and 112, the 
positive and negative limiting level waveforms in FIG. 5B cannot be 
changed beyond the bias voltage. However, it has been proved that the 
present circuit can attain the improvement of approximately 6 dB over the 
conventional circuit. 
As described above, although the limiting levels 52 and 53 change by the 
control signal V.sub.c1 applied to the control terminal T.sub.c1, those 
changes do not influence the output current at the output terminal T.sub.2 
by the function of the bias compensation circuit 300. Accordingly, no 
matter what waveform is applied to the control terminal T.sub.c1, it is 
not material so long as it does not clip the output signal 51'. In an 
extreme case, it may be a square wave, in which case a noise limiting 
effect is substantially same. Accordingly, even if the low-pass filter 200 
is of so simple configuration that it cannot fully eliminate the pulsive 
noises, the limiter circuit of the present invention can fully eliminate 
the noises. 
More specifically, as shown in FIG. 6, by selecting the amplitude of the 
control signal 56 (V.sub.c1) applied to the control terminal T.sub.c1 from 
the low-pass filter 200 to be larger enough than a level V.sub.th at which 
the pair of differential transistors 113 and 114 switch, the signal for 
causing the change of the limiting level is a square wave as shown by a 
curve A B C D E I J. Assuming that the low-pass filter 200 is of so simple 
configuration and the characteristics thereof is so poor that a pulsive 
noise 57 superimposed on the control signal 56 cannot be fully eliminated 
but can only be attenuated to the extent shown by a waveform 57', the 
waveform of the signal for causing the change of the limiting level now 
change to a curve A B C D E F G H I J. That is, the changes of the 
limiting levels 52 and 53 shown in FIG. 5B are shown by the curve A B C D 
E F G H I J in FIG. 6. 
This is illustrated in FIG. 7. By the waveform shown by the curve A-J in 
FIG. 6, the upper limiting level 58 changes as shown by a curve A'-J', and 
the lower limiting level 59 similarly changes as shown by a curve A"-J". 
Thus, the pulsive noise 57 superimposed on the control signal 56 in FIG. 6 
is limited between the levels 58 and 59 so that it is compressed to a 
noise 57" having an amplitude of 2.DELTA.I. Accordingly, even with the 
low-pass filter 200 of simple configuration, the circuit can fully attain 
the noise limiting effect. 
The bias compensation operation is now explained. In the circuit of FIG. 3, 
when the signal is absent, that is, when the input signal e.sub.i at the 
input terminal T.sub.1 and the control signal V.sub.c1 at the control 
terminal T.sub.c1 are zero, the current of I.sub.o /4 flows through the 
transistors 111, 112, 113, 114 and 311, 312, 313, 314, respectively, where 
I.sub.o is the constant current supplied from the constant current source 
transistor 410, and the sum current I.sub.o /2 of the currents through the 
transistors 112 and 312 flows through the load resistor 125 and hence the 
output terminal T.sub.2. 
As the input signal e.sub.i is applied to the input terminal T.sub.1 and 
the control signal V.sub.c1 is applied to the control terminal T.sub.c1 
and the latter increases from zero, for example, the currents in the 
transistor 114 of the amplifier circuit 100 and the current in the 
transistor 313 of the bias compensation circuit 300 increase accordingly. 
On the other hand, the current in the transistor 113 of the amplifier 
circuit 100 and the current in the transistor 314 of the bias compensation 
circuit 300 decrease by the amounts corresponding to the increments of the 
currents in the transistors 114 and 313. As a result, the current in the 
transistor 112 of the amplifier circuit 100 and the current in the 
transistor 311 of the bias compensation circuit also increase while the 
current in the transistor 111 of the amplifier circuit 100 and the current 
in the transistor 312 of the bias compensation circuit 300 decrease. By 
selecting the resistances of the resistors 121 and 321 connected between 
the emitters of the transistors 111 and 112 and between the emitters of 
the transistors 311 and 312, respectively, to be equal to each other, 
equal current flows through the transistors 112, 311 and 111, 312, 
respectively. Therefore, the current flowing through the output terminal 
T.sub.2 does not change. For example, if the current flowing through the 
transistors 114 and 313 increased by .DELTA.I.sub.o to reach (I.sub.o 
/4+.DELTA.I.sub.o), the same magnitude of current (I.sub.o 
/4+.DELTA.I.sub.o) flows through the transistors 112 and 311 and a current 
of (I.sub.o /4-.DELTA.I.sub.o) flows through the transistors 113, 314 and 
111, 312. Accordingly, the current flowing through the output terminal 
T.sub.2 is equal to (I.sub.o /4+.DELTA.I.sub.o)+(I.sub.o 
/4-.DELTA.I.sub.o)=I.sub.o /2. Thus, the bias current is kept constant for 
the change of the control signal V.sub.c1. 
FIG. 8 shows a limiter circuit in accordance with another embodiment of the 
present invention which improves the limiting effect at the low 
modulation. In FIG. 8, the like parts to those shown in FIG. 3 are 
designated by the like numerals and they are not explained here. In FIG. 
8, numeral 500 denotes a circuit for improving the limiting effect at the 
low modulation and it comprises transistors 511, 512, 513 and 514 which 
constitute the circuit for improving the limiting effect at the low 
modulation. The bases of the pair of differential transistors 511 and 512 
are connected to the operating power supply 411 and the emitters thereof 
are connected together. The collector of the transistor 511 is connected 
to the collectors of the transistors 111 and 311 and the collector of the 
transistor 512 is connected to the collectors of the transistors 112 and 
312. The base of the transistor 513 of the pair of differential 
transistors 513 and 514 is connected to a control terminal T.sub.c2 and 
also connected to an operating power supply 416 through a resistor 526 and 
an offset power supply 531 (V.sub.c). The collector thereof is connected 
to the emitters of the pair of differential transistors 113 and 114 of the 
amplifier circuit 100 and the emitters of the pair of differential 
transistors 313 and 314 of the bias compensation circuit 300 through the 
emitter resistors 123, 124 and 323, 324, respectively, and the emitter of 
the transistor 513 is connected to the collector of the constant current 
source transistor 410 through a resistor 523. The base of the transistor 
514 is connected to the operating power supply 416, the collector thereof 
is connected to the emitters of the transistors 511 and 512 and the 
emitter thereof is connected to the collector of the constant current 
source transistor 410 through a resistor 524. 
Numeral 600 denotes a full-wave rectifier circuit which is connected 
between the low-pass filter 200 and the control terminal T.sub.c2 and 
full-wave rectifies the input signal (modulation signal) from the filter 
200 and supplies the resulting pulsating voltage to the control terminal 
T.sub.c2 as a control signal V.sub.c2. The pulsating voltage derived from 
the full-wave rectifier circuit 600 changes in proportion to the magnitude 
of the modulation signal e.sub.i applied to the input terminal T.sub.1, 
that is, a percentage modulation. This pulsating voltage acts as the 
control voltage V.sub.c2 which controls an operating current flowing 
through the transistor 513 of the limiting effect improving circuit 500 in 
accordance with a level of the pulsating voltage and controls the 
input-output characteristic of the amplifier circuit 100, that is, the 
limiting level. 
The operation of the circuit of FIG. 8 is now explained. In FIG. 8, 
assuming that the constant current source transistor 410 supplies a 
constant current of I.sub.o when the control signals V.sub.c1 and V.sub.c2 
are zero, a current of I.sub.o /2 flows through the transistors 513 and 
514 respectively and a current of I.sub.o /8 flows through the transistors 
113, 114, 313 and 314, respectively. Those currents flow into the 
transistors 111, 112, 311 and 312 as they are if the input voltage Vi at 
the input terminal T.sub.1 is zero. A current of I.sub.o /4 flows into the 
transistors 511 and 512, respectively. A sum current of the currents from 
the transistors 112, 314 and 514, that is, I.sub.o /8+I.sub.o /8+I.sub.o 
/4= I.sub.o /2 flows through the resistor 125 and hence the output 
terminal T.sub.2. 
When the control signal V.sub.c1 at the control terminal T.sub.c1 increases 
from zero, the currents in the transistors 114, 313 and 112, 311 increase 
while the currents in the transistors 113, 314 and 111, 312 decrease by 
the amounts corresponding to the increments, like in the circuit shown in 
FIG. 3. 
When the control signal V.sub.c2 at the control terminal T.sub.c2 increases 
from zero, the current in the transistor 513 increases in accordance with 
the level of the control signal V.sub.c2 and the currents in the 
respective transistors of the amplifier circuit 100 and the bias 
compensation circuit 300 also increase. The current in the transistor 514 
decreases by the amount corresponding to the current increment in the 
transistor 513 and the currents in the transistors 511 and 512 also 
decrease accordingly. For example, if the current in the transistor 513 
increases by .DELTA.I.sub.o to reach (I.sub.o /2+.DELTA.I.sub.o), a 
current of (I.sub.o /8+.DELTA.I.sub.o /4) flows into the transistors 113, 
114, 313, 314 and 111, 112, 311, 312, respectively, a current of (I.sub.o 
/2-.DELTA.I.sub.o) flows into the transistor 514, and a current of 
(I.sub.o /4-.DELTA.I.sub.o /2) flows into the transistors 511 and 512, 
respectively. Accordingly, a current of (I.sub.o /8+.DELTA.I.sub.o 
/4)+(I.sub.o /8+.DELTA.I.sub.o /4)+(I.sub. o /4-.DELTA.I.sub.o /2)=I.sub.o 
/2 flows into the output terminal T.sub.2 and hence there occurs no change 
in the output current. 
Thus, even if the control signals V.sub.c1 and V.sub.c2 change, this change 
does not appear at the output terminal T.sub.2. 
The limiting operation to the input voltage V.sub.i of the input signal 
e.sub.i under the above condition is now explained. 
When the input voltage Vi of the input signal e.sub.i and the control 
signals V.sub.c1 and V.sub.c2 are zero, the current of I.sub.o /8 flows 
into the pair of limiting differential transistors 111 and 112 as 
described above, and no current flows through the resistor 121. 
When the input voltage V.sub.i of the input signal e.sub.i changes in the 
positive direction from zero, that is, during a positive half cycle of the 
input signal e.sub.i, the current in the transistor 111 increases while 
the current in the transistor 112 decreases. However, since the control 
signal V.sub.c1 does not change, the transistors 113 and 114 each supplies 
the current of I.sub.o /8 as the constant current source. Thus, the 
current increment beyond I.sub.o /8 in the current of the transistor 111 
flows into the transistor 114 through the resistor 121 and the current in 
the transistor 112 decreases by the amount corresponding to that 
increment. When the current in the transistor 111 reaches I.sub.o /4 from 
I.sub.o /8, the current flowing into the transistor 114 from the resistor 
121 reaches I.sub.o /8 while the current in the transistor 112 reaches 
zero and the transistor 112 is cut off. 
Similarly, when the input voltage V.sub.i of the input signal e.sub.i 
changes in a negative direction from zero, that is, during a negative half 
cycle of the input signal e.sub.i, the current in the transistor 111 
decreases this time while the current in the transistor 112 increases. 
When the current flowing into the resistor 121 from the transistor 112 
reaches I.sub.o /4, the transistor 111 is cut off. 
In this manner, when one of the transistors 111 and 112 are cut off, the 
current in the other transistor ceases to increase even if the input 
voltage V.sub.i further increases. That is, the currents in the 
transistors 111 and 112 can change only .+-.I.sub.o /8 from the initial 
current I.sub.o /8 no matter how the input voltage V.sub.i changes, and 
the current at the output terminal T.sub.2 can change only .+-.I.sub.o /8 
from the initial current I.sub.o /2. 
When the control signal (voltage) V.sub.c2 at the control terminal T.sub.c2 
changes, the operation is the same as that described in connection with 
the embodiment of FIG. 3, and hence the description thereof is omitted. 
FIG. 9 is a characteristic chart of an input-output characteristic of the 
transistors 111 and 112 to the control signal V.sub.c1, in which an 
abscissa represents the input voltage V.sub.i at the input terminal 
T.sub.1 and an ordinate represents an output current I from the pair of 
limiting differential transistors 111 and 112. In FIG. 9, characteristic 
curves 61, 62 and 63 represent characteristics when the control signal 
V.sub.c1 is zero, positive and negative, respectively. It is seen from the 
characteristic curves 61, 62 and 63 in FIG. 9 that the limiting level 
changes depending on whether the control signal V.sub.c1 is zero, positive 
or negative. Thus, by controlling the control signal V.sub.c1, the 
input-output characteristic of the transistors 111 and 112 can be 
controlled to control the limiting level. 
The case where the control signal (voltage) V.sub.c2 at the control 
terminal T.sub.c2 increases from zero is explained. As the control signal 
V.sub.c2 increases, the current in the transistor 513 increases from 
I.sub.o /2 accordingly, while the current in the transistor 514 decreases 
accordingly. As stated above, the current at the output terminal T.sub.2 
does not change from I.sub.o /2. Assuming that the increment of the 
current in the transistor 513 is equal to .DELTA.I.sub.o, the current in 
the transistor 513 reaches I.sub.o /2+.DELTA.I.sub.o while the currents in 
the transistors 113, 114 and 111, 112 reach I.sub.o /8+.DELTA.I.sub.o /2, 
respectively. Accordingly, the currents in the transistors 111 and 112 
change within the range between (I.sub.o /8+.DELTA.I.sub.o /2) and 
.+-.(I.sub.o /8+.DELTA.I.sub.o /2) in accordance with the input signal 
V.sub.i, and the current at the output terminal T.sub.2 changes within the 
range between I.sub.o /2 and .+-.(I.sub.o /8+.DELTA.I.sub.o /2 ). The 
current .DELTA.I.sub.o changes in accordance with the level of the control 
signal V.sub.c2, i.e., the magnitude (percentage modulation) of the input 
signal at the input terminal T.sub.1. Accordingly, the limiting levels of 
the transistors 111 and 112 can be changed in accordance with the 
magnitude of the input signal. 
FIG. 10 shows a characteristic chart showing input-output characteristics 
of the transistors 111 and 112 to the control signal V.sub.c2, in which an 
abscissa represents the input voltage V.sub.i at the input terminal 
T.sub.1 and an ordinate represents the output current I of the pair of 
limiting differential transistors 111 and 112. In FIG. 10, characteristic 
curves 71, 72 and 73 represent the characteristics when the control signal 
V.sub.c2 is zero, small and large, respectively. 
It is seen from the characteristic curves 71, 72 and 73 shown in FIG. 10 
that as the magnitude of the control signal V.sub.c2 increases, a 
saturation level of the output current rises. Thus, by controlling the 
control signal V.sub.c2, the input-output characteristics of the 
transistor 111 and 112 can be controlled to control the limiting levels. 
In the circuit arrangement shown in FIG. 8, when a modulation signal 81 
(e.sub.i) on which pulsive noises 91 and 92 are superimposed as shown in 
FIG. 11A is applied to the input terminal T.sub.1, a control signal 
V.sub.c2 of a waveform as shown in FIG. 11B appears at the control 
terminal T.sub.c2. By this control signal V.sub.c2, a current I.sub.513 
flowing in the transistor 113 assumes a waveform as shown in FIG. 11C. A 
current .DELTA.I represents an initial current supplied by the offset 
power supply 531 (V.sub.c). The current shown in FIG. 11C is distributed 
to the transistors 111 and 112 which constitute the limiting differential 
amplifier by the transistors 113 and 114 which are driven by the control 
voltage V.sub.c1 applied to the control terminal T.sub.c1. In order to 
simplify the explanation, it is assumed that the transistors 113 and 114 
are switching by the control voltage V.sub.c1. Then, current waveforms 
I.sub.111 and I.sub.112 of the transistors 111 and 112 assume the 
waveforms as shown in FIGS. 11D and 11E, respectively. The currents in the 
transistors 111 and 112 do not decrease to completely zero for the 
following reason. For example, when the transistor 114 is conductive, most 
parts of the current flow into the transistor 112 and that portion of the 
current in the transistor 114 which corresponds to the base-emitter 
voltage V.sub.BE of the transistor 112 flows into the transistor 111 
through the resistor 121. However, the current portion is very small. 
Since the limiting level 75 to the positive half cycle of the signal 
e.sub.i applied to the pair of limiting differential transistors 111 and 
112 corresponds to the bias current of the transistor 112 and the limiting 
level 76 to the negative half cycle corresponds to the bias current of the 
transistor 111 as described above, the limiting levels are established as 
shown in FIG. 11F and the signal 82 (e.sub.o) is produced at the output 
terminal T.sub.2 while it is limited between those levels without 
distortion. 
As described above, since the limiting levels substantially coincide with 
the signal level, the signal is not deteriorated even if the signal level 
is low. 
The magnitude of the current .DELTA.I in the transistors 113 and 114 
establishes the limiting level to the pulsive noise 92 which is 
superimposed on a peak of the signal 82, and it can be arbitrarily 
determined by the voltage V.sub.c of the offset power supply 531, and 
theoretically it does not provide a signal distortion with the signal 92 
no matter how it is small. Thus, the pulsive noise 92 can be fully 
suppressed. 
Since the limiting levels 75 and 76 changes to substantially follow the 
level of the input signal, that is, since the control signal V.sub.c2 is 
changed in accordance with the modulation level of the input signal, as 
the signal level lowers, the limiting levels lower accordingly and hence 
the limiting levels to the pulsive noise 91 also lower, that is, they 
approach to the level of I.sub.o /2. Therefore, the S/N ratio is not 
deteriorated when the signal level is low. 
In general, an AM receiver includes a so-called AGC circuit which filters a 
detected signal by a low-pass filter to produce a D.C. control voltage and 
feed it back to an amplifier stage in a preceding stage of the detector 
circuit to control the gain of the amplifier stage. However, since the 
effect of AGC decreases as an input electric field is lowered, the level 
of the detected signal is lowered at a low electric field. This is true in 
an FM receiver. 
However, according to the present embodiment, since the limiting level 
changes in accordance with the level of the demodulated signal, the S/N 
ratio is not deteriorated even at a low electric field. 
Alternatively, the AGC control voltage may be superimposed on the voltage 
V.sub.c of the offset power supply 531. In this case, the S/N ratio is 
also not deteriorated even at a low electric field. 
Furthermore, the application of the signal to the control terminal T.sub.c1 
may be stopped and instead a D.C. control signal derived by rectifying and 
filtering the signal may be applied to the voltage V.sub.c of the offset 
power supply 531 to change the limiting level in accordance with the 
signal level so that a high S/N ratio is obtained. 
By changing the current I.sub.o of the constant current source 410, too, by 
utilizing the AGC control signal of the receiver, a greater noise limiting 
effect can be attained. In this case, the influence of the change of the 
current I.sub.o to the output can be readily prevented by providing an 
additional differential amplifier, in the same manner as in the embodiment 
of FIG. 8. 
While the pairs of differential transistors 311, 312 and 313, 314 are 
configured completely symmetrically to the pairs of differential 
transistors 111, 112 and 113, 114 in order to prevent the output from 
changing by the input at the control terminal T.sub.c1, the transistors 
311 and 312 may be eliminated and the outputs of the transistors 313 and 
314 may be directly connected to the collectors of the transistors 111 and 
112. In this case, also, the control signal at the control terminal 
T.sub.c1 does not appear at the output although the distortion of the 
signal at the output slightly increases. Therefore, the configuration can 
be simplified by eliminating the pair of differential transistors 311 and 
312. 
As described hereinabove, according to the present invention, a sufficient 
noise limiting effect can be attained without distorting the signal. 
Further, since there is no need to use a number of large capacitance 
capacitors, it is very easy to implement the circuit in an IC structure. 
Thus, an inexpensive noise limiter circuit which can fully suppress the 
noise to produce a high S/N signal even at a low electric field can be 
provided.