Localized stress regions for three-dimension chiplet formation

Aspects of the present disclosure provide a method for forming a chiplet onto a semiconductor structure. The method can include providing a first semiconductor structure having a first circuit and a first wiring structure formed on a first side thereof, and attaching the first side to a carrier substrate. The method can further include forming a composite of a first stress film and a second stress film on a second side of the first semiconductor structure, and separating the carrier substrate from the first semiconductor structure. The method can further include cutting the composite of the first stress film and the second stress film and the first semiconductor structure to define at least one chiplet, and bonding the at least one chiplet to a second semiconductor structure that has a second circuit and a second wiring structure such that the second wiring structure is connected to the first wiring structure.

FIELD OF THE PRESENT DISCLOSURE

The present disclosure relates generally to microelectronic devices including semiconductor devices, transistors, and integrated circuits, including methods of microfabrication.

BACKGROUND

In the manufacture of a semiconductor device (especially on the microscopic scale), various fabrication processes are executed such as film-forming depositions, etch mask creation, patterning, material etching and removal, and doping treatments. These processes are performed repeatedly to form desired semiconductor device elements on a substrate. Historically, with microfabrication, transistors have been created in one plane, with wiring/metallization formed above the active device plane, and have thus been characterized as two-dimensional (2D) circuits or 2D fabrication. Scaling efforts have greatly increased the number of transistors per unit area in 2D circuits, yet scaling efforts are running into greater challenges as scaling enters single digit nanometer semiconductor device fabrication nodes. Semiconductor device fabricators have expressed a desire for three-dimensional (3D) semiconductor circuits in which transistors are stacked on top of each other.

SUMMARY

Aspects of the present disclosure provide a method for forming a chiplet onto a semiconductor structure. For example, the method can include providing a first semiconductor structure having a first circuit and a first wiring structure formed on a first side thereof, and attaching the first side of the first semiconductor structure to a carrier substrate. The method can further include forming a composite of a first stress film and a second stress film on a second side of the first semiconductor structure, and separating the carrier substrate from the first semiconductor structure. The method can further include cutting the composite of the first stress film and the second stress film and the first semiconductor structure to define at least one chiplet, and bonding the at least one chiplet to a second semiconductor structure that has a second circuit and a second wiring structure such that the second wiring structure is connected to the first wiring structure. In an embodiment, the method can further include removing the composite of the first stress film and the second stress film after the at least one chiplet is bonded to the second semiconductor structure.

In an embodiment, the first semiconductor structure can further have a first dielectric layer formed on the second side thereof, and forming a composite of a first stress film and a second stress film on a second side of the first semiconductor structure can include forming a composite of a first stress film and a second stress film on the first dielectric layer of the first semiconductor structure. For example, the first semiconductor structure can further have a first substrate formed on the first dielectric layer, and the method can further include, prior to forming a composite of a first stress film and the second stress film on the first dielectric layer of the first semiconductor structure, removing the first substrate to uncover the first dielectric layer.

In an embodiment, the first side of the first semiconductor structure can be attached to the carrier substrate using an attachment material, and separating the carrier substrate from the first semiconductor structure can include heating the attachment material such that the carrier substrate is separated from the first semiconductor structure.

In an embodiment, the method can further include patterning the first stress film to form a first patterned stress film, and cutting the composite of the first stress film and the second stress film and the first semiconductor structure to define at least one chiplet can include cutting the composite of the first patterned stress film and the second stress film and the first semiconductor structure to define at least one chiplet. For example, the first patterned stress film can be formed with at least one stress region, and the second stress film can be formed within the at least one stress region. As another example, the second stress film can be further formed on the first patterned stress film. In an embodiment, the first patterned stress film can be formed via a mask-based lithography tool, ultraviolet (UV) cross-linking, or a direct-write lithography tool. For example, the first patterned stress film can be formed via the direct-write lithography tool using a digital light processing (DLP) chip, a grating light valve or a laser galvanometer. In an embodiment, the method can further include removing the composite of the first patterned stress film and the second stress film after the at least one chiplet is bonded to the second semiconductor structure.

Aspects of the present disclosure further provide another method for forming a chiplet onto a semiconductor structure. For example, the method can include providing a first semiconductor structure having a first circuit and a first wiring structure formed on a first side thereof, and attaching the first side of the first semiconductor structure to a carrier substrate. The method can further include forming a composite of a first stress film and a second stress film on a second side of the first semiconductor structure, and cutting the composite of the first stress film and the second stress film and the first semiconductor structure to define at least one chiplet. The method can further include separating the carrier substrate from the at least one chiplet, and bonding the at least one chiplet to a second semiconductor structure that has a second circuit and a second wiring structure such that the second wiring structure is connected to the first wiring structure.

In an embodiment, the method can further include patterning the first stress film to form a first patterned stress film, and cutting the composite of the first stress film and the second stress film and the first semiconductor structure to define at least one chiplet can include cutting the composite of the first patterned stress film and the second stress film and the first semiconductor structure to define at least one chiplet. For example, the first patterned stress film can be formed with at least one stress region, and the second stress film can be formed within the at least one stress region. As another example, the second stress film can be further formed on the first patterned stress film. In an embodiment, the first patterned stress film can be formed via a mask-based lithography tool, UV cross-linking or a direct-write lithography tool.

In an embodiment, the first semiconductor structure can further have a first dielectric layer formed on the second side thereof, and forming a composite of a first stress film and a second stress film on a second side of the first semiconductor structure can include forming a composite of a first stress film and a second stress film on the first dielectric layer of the first semiconductor structure. For example, the first semiconductor structure can further have a first substrate formed on the first dielectric layer, and the method can further include, prior to forming a composite of a first stress film and the second stress film on the first dielectric layer of the first semiconductor structure, removing the first substrate to uncover the first dielectric layer.

In an embodiment, the first side of the first semiconductor structure can be attached to the carrier substrate using an attachment material, and cutting the stress film and the first semiconductor structure to define at least one chiplet can include cutting the stress film, the first semiconductor structure and the attachment material to define at least one chiplet. For example, cutting the stress film, the first semiconductor structure and the attachment material to define at least one chiplet can include cutting the stress film, the first semiconductor structure, the attachment material and a portion of the carrier substrate to define at least one chiplet.

DETAILED DESCRIPTION

3D integration, i.e., the vertical stacking of multiple devices, aims to overcome scaling limitations experienced in planar devices by increasing transistor density in volume rather than area. Although device stacking has been successfully demonstrated and implemented by the flash memory industry with the adoption of 3D NAND, application to random logic designs is substantially more difficult. 3D integration for logic chips (CPU (central processing unit), GPU (graphics processing unit), FPGA (field programmable gate array) and SoC (System on a chip)) is being pursued.

As microelectronic devices are fabricated on wafers, the wafer itself is subject to various stresses from the different materials added, removed, as well as treatment steps such as annealing. Such stresses can cause overlay problems from wafer bow, warpage and curvature. These problems can increase with wafers stacked on wafers. Techniques herein include systems and methods to mitigate wafer stress complications from stacked wafers and chiplets.

Techniques herein can include selective stress (or stressor) film technology and creating relatively thin chiplets to attach or bond to a semiconductor structure, e.g., a wafer or a die. One or more stress films can be deposited on a surface (e.g., a back, second or inactive side, or opposite to a front, second, active or working side) of the chiplets. In an embodiment, a direct-write lithographic exposure tool can be used to write a corrected stress pattern on the back side of chiplets before being cut and placed on or bonded to a wafer. Chiplets can receive identical or different stress films and identical or different stress-correction patterns for localized stress regions. This enables higher density of 3D chiplets to be stacked because the thickness of the chiplet may be greatly reduced. These techniques also enable higher die yield per wafer because the wafer has less bow or curvature which enables higher precision photolithography.

The order of discussion of the different steps as described herein has been presented for clarity sake. In general, these steps can be performed in any suitable order. Additionally, although each of the different features, techniques, configurations, etc. herein may be discussed in different places of the present disclosure, it is intended that each of the concepts can be executed independently of each other or in combination with each other. Accordingly, the present invention can be embodied and viewed in many different ways.

FIGS.1-9are cross-sectional views illustrating a first exemplary method for forming a chiplet onto a semiconductor structure according to some embodiments of the present disclosure. As shown inFIG.1, a first semiconductor structure100can be provided. In an embodiment, the first semiconductor structure100can have a first circuit (or a first active circuit)110and a first wiring structure120formed on a first side100A (or a front side, an active side or a working side) of the first semiconductor structure100. For example, the first circuit110can be formed in bulk silicon105of the first semiconductor structure100. As another example, the first wiring structure120can include vias and copper layers. In an embodiment, the first circuit110and the first wiring structure120can be used as chiplets. A chiplet herein can be a component device or integrated circuit or a portion thereof that is a component of a larger module, assembly, package, or an integrated circuit. A chiplet can be cut from a larger device or wafer, e.g., the first semiconductor structure100. A dashed line shown inFIG.1can identify an example chiplet.

In an embodiment, the first semiconductor structure100can further have a first dielectric layer130and a first substrate140formed on a second side (or a back side or an inactive side)100B of the first semiconductor structure100. For example, the first substrate140can be a silicon substrate. In the fabrication of the first semiconductor structure100, a silicon-on-insulator (SOI) substrate, which is composed of the first substrate140, the first dielectric layer130and the bulk silicon105, can be provided, the first circuit110can be formed in the bulk silicon105via photolithography, and the first wiring structure120can be formed to connect the first circuit110.

FIG.1further shows a carrier substrate150for the first semiconductor structure100to be attached thereto. For example, the carrier substrate150can be a silicon wafer.

As shown inFIG.2, the first side100A of the first semiconductor structure100can be attached to the carrier wafer150using an attachment material210. For example, the attachment material210can be specified as a glue layer, a bonding layer, a method to bonding wafers that can be removed later, semiconductor to semiconductor with native oxide for dielectric interface, metal to metal, metal with oxide coating, metal with SiC coating, metal with SiCN coating, metal with an attachment film comprising semiconductor with a coating consisting of one or more elements, or a combination thereof.

As shown inFIG.3, the first substrate140can be removed to uncover the first dielectric layer130. For example, the first semiconductor structure100can be planarized via chemical-mechanical planarization (or called chemical-mechanical polishing) (CMP), which stops at the first dielectric layer130, to remove the first substrate140and uncover the first dielectric layer130.

As shown inFIG.4, a first stress film410can be formed on the first dielectric layer130. Any type of stress (i.e., compressive or tensile) may be induced in the bulk silicon105by attaching or forming the first stress film410on the first dielectric layer130. For example, a photoresist layer can be applied to or deposited on the first dielectric layer130via spin coating to act as the first stress film410. As another example, the first stress film410can include silicon nitride, silicon oxide, etc, e.g., Si3N4, SiOxNy, Si and SiO2. The first stress film410can also be an ultraviolet (UV) cross-linking stress film that includes a spin-on material, e.g., benzocyclobutene (BCB) and other materials with cross-linking properties. For example, the spin-on material can be exposed with a direct write exposure and then baked to complete processing to establish a desired stress pattern and be used for any one of the exemplary methods.

As shown inFIG.5, optionally, the first stress film410can be patterned to form a first patterned stress film510with stress regions510A. For example, the stress regions510A can be openings in the first patterned stress film510. In an embodiment, the first stress film410can be patterned, exposed and developed to remove the reacted (e.g., positive) photoresist layer and form the first patterned stress film510. For example, a photomask can be used for forming the first patterned stress film510. As another example, the first stress film410, e.g., the photoresist layer, can be patterned with a direct-write (or maskless) lithography tool, which projects simultaneously or uses a scanning motion to project a stress-modification pattern on the photoresist layer or a layer with photo-reactive agents. The patterned photoresist layer can be then developed to create a relief pattern. This relief pattern can serve as a stress film, or be transferred into an underlying layer to become the first patterned stress film510. For example, a digital light processing (DLP) chip can be used. As another example, a grating light valve or laser galvanometer can be used. Direct-write systems are able to use a processing engine to control amount/intensity of light at any given point on a substrate or film to be exposed Any of various convention light wavelengths can be used based on a photo-reactive agent of a corresponding film (or the film composition can be selected based on light wavelengths available). For stress mitigation, a lower resolution exposure is sufficient to create desired stress modifications (or the first patterned stress film510). Stress-modification patterns (or the first patterned stress film510) herein can make regions of stress induced by stress film (or patterned stress film) vs regions of reduced stress or no stress where the first-write tool has removed at least a portion of the stress film that will make the substrate more planar for optimum photolithography precision. Though the pattern is shown as only partially extending through the first stress film410/the first patterned stress film510, it should be appreciated that the pattern may extend completely through in order to further modify the stress characteristics.

FIG.5further shows that a second stress film520can be deposited and formed within the stress regions510A of the first patterned stress film510. For example, the stress regions510A can be openings in the first patterned stress film510, and the second stress film520can fill the openings and be adjacent to the first patterned stress film510. Therefore, a composite of the first patterned stress film510and the second stress film520can be formed on the first dielectric layer130. After the second stress film520is deposited and formed within the stress regions510A of the first patterned stress film510, CMP can be performed to planarize the second stress film520. In an embodiment, the second stress film520can be formed only within the stress regions510A of the first patterned stress film510, as shown inFIG.5. In another embodiment, the second stress film520can be further formed on the first patterned stress film510. In yet another embodiment, the first stress film410is not patterned, and the second stress film520can be deposited and formed on the first stress film410, to form a composite of the first stress film410and the second stress film520. The second stress film520can be used to add or reduce stress in specific regions of the first semiconductor structure100and chiplets, which will be formed in subsequent process steps. For example, the second stress film520can be either different from or the same as the first stress film410(and the first patterned stress film510) to keep the first semiconductor structure100and the chiplets at balanced stress over the entire area.

As shown inFIG.6, the attachment material210can be removed to separate the first semiconductor structure100from the carrier substrate150. For example, the attachment material210can be heated and vaporized such that the first semiconductor structure100can be separated from the carrier substrate150.FIG.6further shows a second semiconductor structure600that can be bonded to the first semiconductor structure100. For example, the second semiconductor structure600can have a second circuit610and a second wiring structure620that corresponds to the first wiring structure120of the first semiconductor structure100.

As shown inFIG.7, the first semiconductor structure100along with the composite of the first patterned stress film510and the second stress film520(or the composite of the first stress film410and the second stress film520) can be cut via etching, for example, to define a plurality of chiplets750. As the composite of the first patterned stress film510and the second stress film520(or the composite of the first stress film410and the second stress film520) is formed on the first semiconductor structure100, which can allow the first semiconductor structure100(and the chiplets750) to receive identical or different stress films and identical or different stress-correction patterns for localized stress regions and have less complicated wafer stress, the first semiconductor100(and the chiplets750) can have reduced thickness, and higher density of 3D chiplets can be stacked. One or more than one of the chiplets750can be bonded to another semiconductor structure. For example, the chiplet750can be bonded to the second semiconductor structure600, which has the second circuit610and the second wiring structure620that corresponds to the first wiring structure120of the first semiconductor structure100.

As shown inFIG.8, the chiplet750can be bonded to the second semiconductor structure600, with the first wiring structure120of the chiplet750being connected to the second wiring structure620of the second semiconductor structure600.

As shown inFIG.9, the composite of the first patterned stress film510and the second stress film520(or the composite of the first stress film410and the second stress film520) can be removed to uncover the first dielectric layer130. For example, the composite of the first patterned stress film510and the second stress film520(or the composite of the first stress film410and the second stress film520) can be removed via CMP, which stops at the first dielectric layer130, to uncover the first dielectric layer130.FIG.9further shows that the first dielectric layer130can be removed. For example, the first dielectric layer130can be removed via CMP. In an embodiment, the composite of the first patterned stress film510and the second stress film520(or the composite of the first stress film410and the second stress film520) and the first dielectric layer130can be removed in a single CMP process. Therefore, the chiplet750, which is bonded to the second semiconductor structure600, can be very thin.

FIGS.10-14are cross-sectional views illustrating a second exemplary method for forming a chiplet onto a semiconductor structure according to some embodiments of the present disclosure. The second exemplary method differs from the first exemplary method in that in the second exemplary method, prior to forming the first stress film410, both the first substrate140and the first dielectric layer130are removed, which can enable optimum stress transfer. As shown inFIG.10, which followsFIG.2, the first substrate140and the first dielectric layer130are removed. For example, the first substrate140and the first dielectric layer130can be removed in a single CMP process, or be removed in two respective CMP processes, to uncover the second side (or the back side or the inactive side)100B of the first semiconductor structure100.

As shown inFIG.11, the first stress film410can be formed on the second side100B of the first semiconductor structure100and be in direct contact with the bulk silicon105. For example, a photoresist layer can be deposited on the second side100B to act as the first stress film410.

As shown inFIG.12, the first stress film410can be patterned to form the first patterned stress film510with the stress regions510A. For example, a photomask can be used for forming the first patterned stress film510. As another example, the first stress film410, e.g., the photoresist layer, can be patterned with a direct-write lithography tool. The patterned photoresist layer can be then developed to create a relief pattern. This relief pattern can serve as a stress film, or be transferred into an underlying layer to become the first patterned stress film510. For example, a DLP chip can be used. As another example, a grating light valve or laser galvanometer can be used.FIG.12further shows that the second stress film520can be deposited and formed within the stress regions510A of the first patterned stress film510and on the first patterned stress film510. Therefore, a composite of the first patterned stress film510and the second stress film520can be formed on the first dielectric layer130. After the second stress film520is deposited and formed within the stress regions510A of the first patterned stress film510and on the first patterned stress film510, CMP can be performed to planarize the second stress film520. In an embodiment, the second stress film520can be formed within the stress regions510A of the first patterned stress film510and on the first patterned stress film510, as shown inFIG.12. In another embodiment, the second stress film520can be formed only within the stress regions510A of the first patterned stress film510. In yet another embodiment, the first stress film410is not patterned, and the second stress film520can be deposited and formed on the first stress film410, to form a composite of the first stress film410and the second stress film520.

As shown inFIG.13, the attachment material210can be removed to separate the first semiconductor structure100from the carrier substrate150. For example, the attachment material210can be heated and vaporized such that the first semiconductor structure100can be separated from the carrier substrate150.FIG.13further shows that the first semiconductor structure100along with the composite of the first patterned stress film510and the second stress film520(or the composite of the first stress film410and the second stress film520) can be cut via etching, for example, to define a plurality of chiplets1350. One or more than one of the chiplets1350can be bonded to another semiconductor structure. For example, the chiplet1350can be bonded to the second semiconductor structure600, which has the second circuit610and the second wiring structure620that corresponds to the first wiring structure120of the first semiconductor structure100.FIG.13further shows that the chiplet1350can be bonded to the second semiconductor structure600, with the first wiring structure120of the chiplet1350being connected to the second wiring structure620of the second semiconductor structure600.

As shown inFIG.14, the composite of the first patterned stress film510and the second stress film520(or the composite of the first stress film410and the second stress film520) can be removed. For example, the composite of the first patterned stress film510and the second stress film520(or the composite of the first stress film410and the second stress film520) can be removed via CMP, which stops at the bulk silicon105of the first semiconductor structure100where the first circuit110is formed. Therefore, the chiplet1350, which is bonded to the second semiconductor structure600, can be very thin.

FIGS.15-17are cross-sectional views illustrating a third exemplary method for forming a chiplet onto a semiconductor structure according to some embodiments of the present disclosure. The third exemplary method differs from the first and second exemplary methods in that in the third exemplary method the first semiconductor structure100along with the composite of the first patterned stress film510and the second stress film520(or the composite of the first stress film410and the second stress film520) are cut to define the chiplets750/1350with the carrier substrate150and the attachment material210being kept in place and the chiplets750/1550being separated from the carrier substrate150at a future step at a chiplet level. The third exemplary method can enable control of cutting the chiplets with a thicker underlying substrate. As shown inFIG.15, which followsFIG.12, the composite of the first patterned stress film510and the second stress film520(or the composite of the first stress film410and the second stress film520) and the first semiconductor structure100, which includes the first dielectric layer130and the first circuit110(and the attachment material210) can be cut sequentially via etching, for example, to define the chiplets1350. In an embodiment, the cutting process can stop at the carrier substrate150, as shown inFIG.15. In another embodiment, the carrier substrate150can be etched partially in the cutting process.FIG.15can also followFIG.5, and the composite of the first patterned stress film510and the second stress film520(or the composite of the first stress film410and the second stress film520) and the first semiconductor structure100, which includes the first circuit110, the first wiring structure120and the first dielectric layer130(and the attachment material210) (and, optionally, a top portion of the carrier substrate150) can be etched sequentially, to define the chiplets750.

As shown inFIG.16, optionally, chiplet supporters1610can be optionally formed on the composite of the first patterned stress film510and the second stress film520(or the composite of the first stress film410and the second stress film520) for each of the chiplets1350(or chiplets750), and the attachment material210can be removed via heating, for example, to separate the carrier substrate150from the chiplets1350(or chiplets750). For example, the chiplet supporters1610can be formed on the first patterned stress film510(or the first stress film410) and/or the second stress film520for each of the chiplets1350(or chiplets750).FIG.16further shows that one or more than one of the chiplets1350(or chiplets750) can be bonded to another semiconductor structure. For example, the chiplet1350(or chiplet750) can be bonded to the second semiconductor structure600, which has the second circuit610and the second wiring structure620, the second wiring structure620corresponding to the first wiring structure120of the first semiconductor structure100. In an embodiment, the chiplet supporters1610can be used for holding the chiplets750(or chiplets1350) in place during subsequent process steps, e.g., the cutting process step. For example, the chiplet supporters1610can be an adhesive. As another example, the chiplet supporters1610can be formed on the surface of the composite of the first patterned stress film510and the second stress film520(or the composite of the first stress film410and the second stress film520) in a random location for each of the chiplets750(or chiplets1350). The chiplet supporters1610can be formed in any shape, e.g., a block, as shown inFIG.16.

As shown inFIG.17, the chiplet1350(or chiplet750) can be bonded to the second semiconductor structure600, with the first wiring structure120of the chiplet1350(or chiplet750) being connected to the second wiring structure620of the second semiconductor structure600. Then, the chiplet supporter1810and the composite of the first patterned stress film510and the second stress film520(or the composite of the first stress film410and the second stress film520) (and the first dielectric layer130for the chiplet750) can be removed. For example, the chiplet supporter1810, the composite of the first patterned stress film510and the second stress film520(or the composite of the first stress film410and the second stress film520) and the first dielectric layer130can be removed via CMP in a single process or multiple processes.

FIGS.18-22are cross-sectional views illustrating a fourth exemplary method for forming a chiplet onto a semiconductor structure according to some embodiments of the present disclosure. The fourth exemplary method differs from the first and second exemplary methods in that in the fourth exemplary method a dual stress film stack of two or more layers can be deposited on the second side100B of the first semiconductor structure100, omitting the CMP process performed on the second stress film520. In an embodiment, as shown inFIG.18, which followsFIG.10, a dual stress film stack of two or more layers, e.g., a composite of a first stress film1810and a second stress film1820, can be deposited and formed on the second side100B of the first semiconductor structure100. In another embodiment, which followsFIG.3, the composite of the first stress film1810and the second stress film1820can be deposited and formed on the first dielectric layer130. For example, a photoresist layer can be applied to or deposited on the first dielectric layer130via spin coating to act as the first stress film1810(or the second stress film1820). As another example, the first stress film1810(or the second stress film1820) can include silicon nitride, silicon oxide, etc. The first stress film1810(or the second stress film1820) can also be an UV cross linking stress film that includes a spin-on material.

As shown inFIG.19, optionally, the dual stress film stack can be patterned. For example, the first stress film1810can be patterned to form a first patterned stress film1910with stress regions1910A. For example, a photomask can be used for forming the first patterned stress film1910. As another example, the first stress film1810, e.g., the photoresist layer, can be patterned with a direct-write lithography tool. The patterned photoresist layer can be then developed to create a relief pattern. This relief pattern can serve as a stress film, or be transferred into an underlying layer to become the first patterned stress film1910. For example, a DLP chip can be used. As another example, a grating light valve or laser galvanometer can be used. Therefore, a composite of the first patterned stress film1910and the second stress film1820can be formed on the second side100B of the first semiconductor structure100.

As shown inFIG.20, the attachment material210can be removed to separate the first semiconductor structure100from the carrier substrate150. For example, the attachment material210can be heated and vaporized such that the first semiconductor structure100can be separated from the carrier substrate150.FIG.20further shows that the first semiconductor structure100along with the composite of the first patterned stress film1910and the second stress film1820(or the composite of the first stress film1810and the second stress film1820) can be cut via etching, for example, to define a plurality of chiplets2050. One or more than one of the chiplets2050can be bonded to another semiconductor structure. For example, the chiplet2050can be bonded to the second semiconductor structure600, which has the second circuit610and the second wiring structure620that corresponds to the first wiring structure120of the first semiconductor structure100.

Alternatively, the first semiconductor structure100along with the composite of the first patterned stress film1910and the second stress film1820(or the composite of the first stress film1810and the second stress film1820) can be cut to define the chiplets2050, and then the attachment material210can be removed to separate the carrier substrate150from the chiplets2050.

As shown inFIG.21, the chiplet2050can be bonded to the second semiconductor structure600, with the first wiring structure120of the chiplet2050being connected to the second wiring structure620of the second semiconductor structure600.

As shown inFIG.22, the composite of the first patterned stress film1910and the second stress film1820(or the composite of the first stress film1810and the second stress film1820) can be removed. For example, the composite of the first patterned stress film1910and the second stress film1820(or the composite of the first stress film1810and the second stress film1820) can be removed via CMP, which stops at the bulk silicon105of the first semiconductor structure100where the first circuit110is formed.

FIG.23is a flow chart illustrating a fifth exemplary method2300for forming a chiplet onto a semiconductor structure according to some embodiments of the present disclosure. In an embodiment, some of the steps of the fifth exemplary method2300shown can be performed concurrently or in a different order than shown, can be substituted by other method steps, or can be omitted. Additional method steps can also be performed as desired. In another embodiment, the fifth exemplary method2300can correspond to the first, second and fourth exemplary methods shown inFIGS.1-14and18-22.

At step S2310, a first semiconductor structure can be provided. In an embodiment, the first semiconductor structure (e.g., the first semiconductor structure100) can include a first circuit (e.g., the first circuit110) and a first wiring structure (e.g., the first wiring structure120) that are formed on a first side of the first semiconductor structure (e.g., the first side100A) and a first dielectric layer (e.g., the first dielectric layer130) and a first substrate (e.g., the first substrate140) that are formed on a second side of the first semiconductor structure (e.g., the second side100B).

At step S2320, the first side of the first semiconductor structure can be attached to a carrier substrate. For example, the first side100A of the first semiconductor100can be attached to the carrier substrate150using the attachment material210.

At step S2330, the first substrate (and the first dielectric layer) can be removed. For example, the first substrate140(and the first dielectric layer130) can be removed via CMP.

At step S2340, a composite of a first stress film and a second stress film can be formed on the second side (or the first dielectric layer) of the first semiconductor structure. For example, the composite of the first stress film1810and the second stress film1820can be formed on the second side100B of the first semiconductor structure100, as shown inFIG.18. As another example, the composite of the first stress film1810and the second stress film1820can be formed on the first dielectric layer130of the first semiconductor structure100.

At step S2350, the first stress film can be patterned to form a first patterned stress film. For example, the first stress film can be patterned with the direct-write to form the composite of the first patterned stress film510and the second stress film520, as shown inFIG.5. As another example, the first stress film can be patterned to form the composite of the first patterned stress film1910and the second stress film1820, as shown inFIG.19

At step S2360, the first semiconductor structure can be separated from the carrier substrate. For example, the attachment layer210can be heated and vaporized such that the first semiconductor structure100can be separated from the carrier substrate150.

At step S2370, the first semiconductor structure along with the composite of the first patterned stress film and the second stress film (or the composite of the first stress film and the second stress film) can be cut to define a plurality of chiplets. For example, the first semiconductor structure100along with the composite of the first patterned stress film1910/510and the second stress film1820/520(or the composite of the first stress film1810/410and the second stress film1820/520) can be cut via etching, for example, to define the chiplets750/1350/2050.

At step S2380, one or more than one of the chiplets can be bonded to another semiconductor structure. For example, the chiplet750/1350/2050can be bonded to the second semiconductor structure600, which has the second circuit610and the second wiring structure620, with the first wiring structure120of the chiplet750/1350/2050being connected to the second wiring structure620of the second semiconductor structure600.

At step S2390, the composite of the first patterned stress film and the second stress film (or the composite of the first stress film and the second stress film) (and the first dielectric layer) can be removed. For example, the composite of the first patterned stress film1910/510and the second stress film1820/520(or the composite of the first stress film1810/410and the second stress film1820/520) (and the first dielectric layer130) can be removed via CMP.

FIG.24is a flow chart illustrating a sixth exemplary method2400for forming a chiplet onto a semiconductor structure according to some embodiments of the present disclosure. In an embodiment, some of the steps of the sixth exemplary method2400shown can be performed concurrently or in a different order than shown, can be substituted by other method steps, or can be omitted. Additional method steps can also be performed as desired. In another embodiment, the sixth exemplary method2400can correspond to the third exemplary method shown inFIGS.15-17. The sixth exemplary method2400can also include steps S2310-S2350.

At step S2460, the first semiconductor structure along with the composite of the first patterned stress film and the second stress film (or the composite of the first stress film and the second stress film) can be cut to define a plurality of chiplets. For example, the first semiconductor structure100along with the composite of the first patterned stress film510and the second stress film520can be cut via etching, for example, to define the chiplets750, with the carrier substrate150and the attachment material210being kept in place and the chiplets750being separated from the carrier substrate150at a future step at a chiplet level.

At step S2465, optionally, chiplet supporters are formed on the composite of the first patterned stress film and the second stress film (or the composite of the first stress film and the second stress film) for each of the chiplets. For example, the chiplet supporters1610can be formed on the composite of the first patterned stress film510and the second stress film520for each of the chiplets750.

At step S2470, the chiplets can be separated from the carrier substrate. For example, the attachment layer210can be heated and vaporized such that the chiplets750can be separated from the carrier substrate150.

At step S2480, one or more than one of the chiplets can be bonded to another semiconductor structure. For example, the chiplet750can be bonded to the second semiconductor structure600, which has the second circuit610and the second wiring structure620, with the first wiring structure120of the chiplet750being connected to the second wiring structure620of the second semiconductor structure600.

At step S2490, the chiplet supporters and the composite of the first patterned stress film and the second stress film (or the composite of the first stress film and the second stress film) (and the first dielectric layer) can be removed. For example, the chiplet supporters1610and the composite of the first patterned stress film510and the second stress film520(and the first dielectric layer130) can be removed via CMP.

According to some embodiments of the present disclosure, any stress combination is possible. Stress films can be compressive, tensile, or neutral in different regions on a semiconductor device, a die or a wafer. Embodiments herein include two or more compressive or tensile of the same stress type but different stress values (or alternatively they may be different stress regions on the same wafer, i.e., compressive and tensile). Examples herein show two stress films, but more than two stress films can also be used. Multiple types of stress films on a back side of chiplets can provide another degree of freedom in enhancing photolithography.