Semiconductor package and methods of manufacturing a semiconductor package

In an embodiment, a semiconductor package includes a first transistor device having first and second opposing surfaces, a first power electrode and a control electrode arranged on the first surface and a second power electrode arranged on the second surface. A first metallization structure arranged on the first surface includes a plurality of outer contact pads which includes a protective layer of solder, Ag or Sn. A second metallization structure is arranged on the second surface. A conductive connection extending from the first surface to the second surface electrically connects the second power electrode to an outer contact pad of the first metallization structure. A first epoxy layer arranged on side faces and on the first surface of the transistor device includes openings which define a lateral size of the plurality of outer contact pads and a package footprint.

BACKGROUND

In some circuits, such as power conversion, the circuit requires two or more semiconductor devices which are electrically coupled together to provide the corresponding circuit or part of the corresponding circuit. For example, in motor drivers, DC/DC converters and rectifiers, the circuit may require a combination of transistor devices which are used as a switch in a half bridge configuration that includes a low side switch and a high side switch. In a half bridge configuration, the drain of the transistor device providing the low side switch is electrically coupled to the source of the transistor providing the high side switch.

In some cases, each semiconductor device, for example, a transistor device, is accommodated within a package and the packages are electrically coupled together by means of a conductive redistribution structure positioned external to the packages. For example, the packages may be mounted on a circuit board including a conductive redistribution structure which electrically couples the packages to form the circuit or part of the circuit. Such an arrangement may, however, occupy an undesirably large lateral area for some applications.

US 2013/0140673 A1 discloses a semiconductor device including one semiconductor die in which a first field effect transistor and a second field effect transistor are monolithically integrated and form a half bridge configuration.

Semiconductor devices for power conversion circuits which occupy a smaller lateral area and methods for fabricating such semiconductor devices are desirable.

SUMMARY

In an embodiment, a semiconductor package comprises a first transistor device comprising a first surface and a second surface opposing the first surface, a first power electrode and a control electrode arranged on the first surface and a second power electrode arranged on the second surface, a first metallization structure arranged on the first surface, the first metallization structure comprising a plurality of outer contact pads, the outer contact pads comprising a protective layer of solder, Ag or Sn, a second metallization structure arranged on the second surface, a conductive connection extending from the first surface to the second surface and electrically connecting the second power electrode to an outer contact pad of the first metallization structure, and a first epoxy layer arranged on side faces and on the first surface of the transistor device. The first epoxy layer comprises openings defining the lateral size of the outer contact pads and a package footprint.

In an embodiment, a method comprises forming at least one first trench in a first surface of the semiconductor wafer in a device region, wherein the semiconductor wafer comprises separation regions arranged between component positions of the semiconductor wafer, the component positions comprising the device region comprising an electronic device, forming a first metallization structure arranged on the first surface in the component position, the first metallization structure comprising a plurality of outer contact pads forming a package footprint, and inserting conductive material into the first trench, forming at least one second trench in the first surface of the semiconductor wafer in the separation regions, applying a first epoxy layer to the first surface of a semiconductor wafer such that the second trenches and edge regions of the component positions are covered with the first epoxy layer, removing portions of a second surface of the semiconductor wafer, the second surface opposing the first surface, and revealing portions of the first epoxy layer in the separation regions and the conductive material in the first trenches and producing a worked second surface, applying a second metallization layer to the worked second surface and operably coupling the second metallization layer to the conductive material and an outer contact pad on the first major surface and cutting through the first epoxy layer in the separation regions to form a plurality of separate semiconductor packages.

In an embodiment, a method comprises forming a first metallization structure on a first surface of a semiconductor wafer, wherein the semiconductor wafer comprises separation regions arranged between component positions, the component positions comprising a device region comprising an electronic device, the first metallization structure being arranged on the component positions and comprising a plurality of outer contacts forming a package footprint, forming at least one second trench in the first surface of the semiconductor wafer in the separation regions, applying a first epoxy layer to the first surface of a semiconductor wafer such that the second trenches, and edge regions of the component positions are covered with the first epoxy layer, removing portions of a second surface of the semiconductor wafer, the second surface opposing the first surface, and revealing portions of the first epoxy layer in the separation regions, forming at least one first trench in the worked second surface of the semiconductor wafer in the device region of the component position, inserting conductive material into the first trench, applying a second metallization layer to the worked second surface and operably coupling the second metallization layer to the conductive material and an outer contact pad on the first major surface, and cutting through the first epoxy layer in the separation regions to form a plurality of separate semiconductor packages.

In an embodiment, a module comprises a first electronic device in a first device region and a second electronic device in a second device region, wherein the first electronic device is operably coupled to the second electronic device to form a circuit. The module further comprises a first major surface comprising at least one contact pad, a second major surface comprising at least one contact pad, the second major surface opposing the first major surface, a first epoxy layer arranged on the first major surface that leaves at least portions of the first contact pad exposed. Side faces of the first electronic device and of the second electronic device are embedded in, and in direct contact with, the first epoxy layer. The module further comprises a conductive redistribution structure that electrically couples the first electronic device with the second electronic device to form the circuit. The conductive redistribution structure comprises a conductive via extending from the first major surface to the second major surface and a conductive layer that is arranged on the conductive via and on at least one of the first device region and on the second device region.

In an embodiment, an electronic component comprises a module according to any one of the embodiments described herein, a plurality of leads and a plastic housing composition. The first contact pad of the module is coupled to a first lead and the second contact pad of the module is coupled to a second lead of the plurality of leads. The plastic housing composition covers the first epoxy layer.

In an embodiment, a method for manufacturing a semiconductor module comprises forming at least one trench in non-device regions of a first surface of a semiconductor wafer and forming at least one trench in non-circuit regions the first surface of the semiconductor wafer. The non-device regions are arranged between component positions and the component positions comprising at least two semiconductor devices for forming a circuit. A non-circuit region is arranged between a first device region comprising a first electronic device and a second device region comprising a second electronic device, a first metallization layer being arranged on the first surface in the first device region and in the second device region. The method further comprises applying a first polymer layer to the first surface of a semiconductor wafer such that the trenches, edge regions of the component positions, edge regions of the first device regions and edge regions of the second device regions are covered with the first polymer layer, removing portions of a second surface of the semiconductor wafer, the second surface opposing the first surface, revealing portions of the first polymer layer in the non-device regions and in the non-circuit regions and producing a worked second surface. The method further comprises applying a second metallization layer to the worked second surface and operably coupling the first electronic device to the second electronic device to form the circuit and inserting a separation line through the first polymer layer in the non-device regions to form a plurality of separate semiconductor dies comprising the circuit.

DETAILED DESCRIPTION

A number of exemplary embodiments will be explained below. In this case, identical structural features are identified by identical or similar reference symbols in the figures. In the context of the present description, “lateral” or “lateral direction” should be understood to mean a direction or extent that runs generally parallel to the lateral extent of a semiconductor material or semiconductor carrier. The lateral direction thus extends generally parallel to these surfaces or sides. In contrast thereto, the term “vertical” or “vertical direction” is understood to mean a direction that runs generally perpendicular to these surfaces or sides and thus to the lateral direction. The vertical direction therefore runs in the thickness direction of the semiconductor material or semiconductor carrier.

As employed in this specification, when an element such as a layer, region or substrate is referred to as being “on” or extending “onto” another element, it can be directly on or extend directly onto the other element or intervening elements may also be present. In contrast, when an element is referred to as being “directly on” or extending “directly onto” another element, there are no intervening elements present.

In power conversion applications, the corresponding circuits commonly require a combination of transistors, such as Field Effect Transistors (FETs), to form, for example the high- and low-side of a buck converter, to be positioned as close as possible. The individual placing of chips requires minimum spacing distances which limits the possible shrink of the package. Wider spacings may also increase stray inductivities which impact the performance of the package.

Some embodiments described herein provide a semiconductor package with a single semiconductor die that includes a single semiconductor device, in particular a single semiconductor device for power conversion. In some embodiments, the single semiconductor device is a transistor device such as a vertical MOSFET (Metal Oxide Semiconductor Field Effect Transistor) or vertical IGBT (Insulated Gate Bipolar Transistor). The semiconductor package has a smaller package footprint and occupies a smaller lateral area as the drain outer contact as well as the source outer contact and gate outer contact of the package are positioned on, and within the lateral area of, the semiconductor die providing the transistor device.

Some embodiments described provide include a multi-chip or multi-device single die module that enables closer spacing of chips within the module and simultaneously allows a direct electrical connection between source and drain of two devices, e.g. vertical transistor devices, by means of a via, for example a through silicon via (TSV). The module can be packaged in standard plastic packages or is ready for chip embedding or may be used as a final package without further packaging.

FIG. 1illustrates a flow diagram20of a method for fabricating a semiconductor module which includes a first electronic device and a second electronic device which are coupled to form a circuit. In block21, at least one trench is formed in separation regions of a first surface of a semiconductor wafer. In block22, at least one trench is formed in non-device regions of the first surface of the semiconductor wafer. The separation regions are arranged between component positions of the semiconductor wafer. The component positions may each comprise at least two electronic devices for forming a circuit and a non-device region arranged between a first device region comprising a first electronic device and a second device region comprising a second electronic device. A first metallization structure is arranged on the first surface of the semiconductor wafer in the first device region and in the second device region.

In block23, a first polymer layer is applied to the first surface of the semiconductor wafer such that the trenches in both the separation regions and the non-device regions, edge regions of the component positions, edge regions of the first device regions and edge regions of the second device regions are covered with the first polymer layer. The polymer layer may include a curable polymer composition, such as a thermosetting polymer resin and may include epoxy.

In block24, portions of a second surface of the semiconductor wafer, the second surface opposing the first surface, are removed and portions of the first polymer layer positioned in the separation regions and in the non-device regions are exposed and a worked second surface is produced.

The thickness of the semiconductor wafer is reduced and may be reduced to a predetermined thickness. In these embodiments, the depth of the trenches in the separation regions and in the non-device regions may be selected to be greater than the desired final thickness of the semiconductor wafer, such that portions of the first polymer layer arranged in the trenches formed in the separation regions and in the non-device regions are exposed after the thickness of the semiconductor wafer has been reduced to the predetermined desired thickness.

In block25, a second metallization layer is applied to the worked second surface. The first electronic device is operably coupled to the second electronic device to form the desired circuit.

In block26, a separation line is inserted through the first polymer layer positioned in the separation regions to form a plurality of separate semiconductor modules, each semiconductor module comprising the circuit. Each semiconductor module includes the first electronic device and the second electronic device which are operably coupled to form the circuit. The separation line may be inserted by mechanical sawing or laser cutting, for example.

The semiconductor module includes two device regions comprising semiconductor material. The semiconductor material may be silicon, for example. Each semiconductor module includes two or more electronic devices which are laterally separated from one another by the portion of the first polymer layer arranged in the non-device region which is laterally positioned between the first device region comprising the first electronic device and the second device region comprising the second electronic device. The sidewalls of the module and edges formed between the sidewalls and the first surface and the second surface of the device regions may be covered and in direct contact with the first polymer layer. The first polymer layer may be used to protect the side faces and edges. This arrangement may be used to simplify handling of the module using automated equipment.

The module may be subsequently packaged and the exposed portions of the first and second metallization layers provide contact pads which may be electrically coupled to the external contact pads of the package by an internal conductive redistribution structure. In some embodiments, the module may be used in a circuit or application without being further packaged.

As an example, the first electronic device may include a transistor device, for example a field effect transistor device such as a MOSFET or insulated gate bipolar transistor (IGBT). The second electronic device may also comprise a transistor device, for example a field effect transistor device such as a MOSFET or insulated gate bipolar transistor (IGBT), or may include a driver device, such as a gate driver device, or part of a gate driver device, such as a pull-down FET (Field Effect Transistor), or may include a passive device, such as an inductor, a capacitor, or a resistor. If two transistor devices are provided, the module may provide a half bridge circuit with appropriate electrical connections between the two transistor devices.

In some embodiments, each component position may comprise more than two electronic devices for forming a particular circuit. As an example, the circuit may be half bridge configuration in the case of both the first electronic device and the second electronic device being a transistor and the component position may further include a driver device, or part of a driver device, such as a pull-down FET, that is coupled to the gates of the two transistor devices.

The non-device regions do not include any device structures and may laterally surround the first device region and the second device region. The separation regions which are positioned between immediately adjacent component positions are typically also free of device structures. In some embodiments, the component positions are arranged in a regular array of rows and columns such that the trenches formed in the separation regions have the form of a square or rectangular grid in plan view.

The device regions in each component position may have different lateral arrangements. In some embodiments, the device regions within each electronic component position are arranged laterally adjacent one another, such that the trenches formed in the non-device regions extend substantially parallel to one another. In some embodiments, the device regions within each electronic component position are arranged laterally such that one device region is separated from the other device region by two substantially perpendicular non-device regions and such that the trenches formed in the non-device regions extend substantially perpendicular to one another. For example, one device region may be arranged in a corner of a laterally square or rectangular component position such that it is bounded by two substantially perpendicular separation regions and by two substantially perpendicular non-device regions. The other device region may have an L-shape. In some embodiments, one device region is laterally surrounded in all sides by a further device region such that a non-device region having a continuous ring-form surrounds the inner device region. For example, an inner device region may be substantially square or rectangular and be laterally surrounded by a substantially square or rectangular continuous non-device region which in turn is laterally surrounded by a square or rectangular ring-shaped further device region. The inner device region and the outer device region may be concentric or non-concentrically arranged with respect to one another.

In some embodiments, in block25, the second metallization layer is applied such that it operably couples, for example electrically connects, the first electronic device to the second electronic device to form the circuit. In other embodiments, the first electronic device and the second electronic device may be electrically connected by the first metallization structure and the removal of portions of the second surface of the semiconductor wafer results in the semiconductor body of the two electronic devices being electrically insulated from one another. The second metallization layer may provide a ground plane in these embodiments.

In some embodiments, the method further comprises forming a vertical conductive connection that extends between the first and second surfaces of the wafer. The vertical conductive connection may be used to electrically couple the first and second electronic devices. A vertical conductive connection may be used if one or more of the electronic devices is a vertical device having a vertical drift path, for example.

In some embodiments, the method further comprises inserting one or more vias or through-holes into the first device region or the second device region, inserting conductive material into the via and electrically coupling the conductive material within the via to the first electronic device and to the second electronic device. In some embodiments, a via may be inserted into both the first device region and the second device region. In some embodiments, two or more vias may be inserted into at least one of the first device region and the second device region. The number and position of the vias may be selected depending on the circuit which is to be formed, the structure of the first and second electronic devices and on the current carrying capacity required by the via structure.

The via may be inserted into the first surface of the semiconductor wafer and, afterwards, the first metallization structure and the first polymer layer is applied to the first surface and subsequently, portions of the second surface of the semiconductor wafer are removed to form the worked second surface. Alternatively the via may be inserted into the first surface of the semiconductor wafer before the first metallization structure is applied.

An insulating material may be inserted into the one or more vias or through-holes formed in the first device region or the second device region before the conductive material is inserted into the via. The insulating material may line the side walls of the via or through-hole and contain insulation to the surrounding device body.

In some embodiments, a further conductive layer is applied to the first metallization structure, for example, to increase the thickness of the regions which are to provide the contact pads. The conductive material may be inserted into the via before the further conductive layer is applied such that this further conductive layer electrically couples the conductive material within the via to the first metallization structure. Alternatively, the conductive material can be inserted into the via and a further conductive layer applied to one or both of the major surfaces in the same deposition process.

In some embodiments, the via is inserted into the worked second surface of the semiconductor wafer. In these embodiments, the via may be inserted such that the base of the via is formed by a portion of the first metallization structure or further conductive layer positioned on the first surface of the semiconductor wafer. The conductive material is inserted into the via such that it makes contact with and is electrically connected to the first metallization structure. The conductive material may be electrically insulated from the surrounding device body by insulation material that lines the side walls of the via.

The second metallization layer may be applied to the worked second surface and to the conductive material within the via in order to electrically couple the first electronic device arranged in the first device region to the conductive via and to the second electronic device positioned in the second device region. The second metallization layer may extend from the first device region over the non-device region including the first polymer layer which is exposed in the worked second surface, onto the second device region and onto the conductive material positioned within the via. The second metallization layer may also be structured in order to form one or more contact areas on the worked second surface of the semiconductor wafer that are electrically separated from a further conductive area, for example, the conductive area electrically coupling the first electronic device to the conductive via.

In these embodiments, a vertical portion of the redistribution structure of the module is formed which is positioned within the semiconductor material of the semiconductor wafer, either within the first device region or within the second device region.

In other embodiments, this vertical portion of the redistribution structure may be positioned between the first and second device regions and be positioned in the non-device region. In some embodiments, the method further includes inserting conductive material into the trench formed in the non-device region and electrically coupling the conductive material positioned within this trench to the first electronic device and to the second electronic device. The conductive material within the via may be electrically coupled to the first electronic device and to the second electronic device by portions of the first metallization layer arranged on the first surface and by portions of the second metallization layer arranged on the second surface.

The conductive material arranged in the trench in the non-device region may be electrically insulated from the semiconductor material of the first and second device regions by applying one or more insulating layers to the sidewalls of the trench. In some embodiments, after the first polymer layer is inserted into the trench formed in the non-device region, a via is formed in the first polymer layer in the non-device regions. The via may have a width which is less than the width of the trench such that side faces of the first device region and of the second device region bounding the via are covered with the first polymer layer. The conductive material is applied to the first polymer layer in the via. The first polymer layer is, therefore, used to electrically insulate the conductive material from the side faces of the first and second device regions.

In some embodiments, the portions of the second surface of the wafer are subsequently removed exposing not only the first polymer layer arranged in the non-device regions but also the conductive material arranged within the non-device region in the worked second surface such that the conductive material extends from the first metallization surface structure arranged on the first surface of the second device region to the worked second surface.

The second metallization layer may be applied to the conductive material within the via arranged in the non-device region to electrically couple the first electronic device to the second electronic device. The second metallization layer may be applied such that it extends from the first device region over the non-device region to the second device region. In the case of via being positioned in the non-device region, the lateral extension of the second metallization layer onto both the first and the second device regions may be used to assist mechanical stability of the structure.

In some embodiments, a conductive via from the first surface of the semiconductor wafer to the worked second surface of the semiconductor wafer is formed by a conductive portion of the first device region or of the second device region. The conductive portion extends from the first surface of the semiconductor wafer to the worked second surface of the semiconductor wafer. The conductive portion may be insulated from the remainder of the semiconductor material of the first device region and second device region by an insulation layer, for example an oxide or nitride and/or by the first polymer layer. The conductive portion may be coupled to the first electronic device and second electronic device by a portion of the first and second metallization layers in order to electrically couple the first and second electronic devices and form the circuit.

The first polymer layer may be applied to the first surface of the semiconductor wafer such that at least a portion of the first metallization structure is uncovered by the first polymer layer. In some embodiments, the first polymer layer may be selectively applied such that it is applied to the trenches, edge regions of the component positions and edge regions of the first device regions and of the second device regions or may be applied as a closed layer, and portions of the first polymer layer removed to expose at least portion of the first metallization structure.

In some embodiments, the first polymer layer is laterally arranged such that peripheral portions of the first metallization structure are covered by the first polymer layer and bound exposed portions of the first metallization structure, for example bound and define one or more contact pads. In these embodiments, the first polymer layer may act to control the lateral extent of solder applied to the contact pads.

In some embodiments, the method further comprises applying a carrier to the first polymer layer arranged on the first surface, the first polymer layer being structured such that a least first portion of the first metallization structure is exposed by the first polymer layer. Cavities may be formed between the carrier and the first metallization structure which are bounded by the first polymer layer. The portions of the second surface of the semiconductor wafer are then removed and portions of the first polymer layer in the separation regions and in the non-device regions revealed whilst the carrier is applied to the first polymer layer. The carrier is not in direct contact with the first metallization structure of the semiconductor wafer.

The separation line, for example sawing line, may have a width that is less than the width of the trench in the separation regions. The separation line may then be inserted into the separation region such that at least portions of the side faces of the plurality of separate semiconductor modules comprise a portion of the first polymer layer.

In some embodiments, a second polymer layer is applied to the worked second surface in the separation regions and non-device regions, the side faces of the separate semiconductor modules may also comprise of a portion of the second polymer layer as well as the first polymer layer. The entire side faces as well as edges of the component positions may be covered by the first and second polymer layers.

The second polymer layer may also comprise a curable polymer composition, for example a thermosetting resin, for example, for example a second epoxy layer. The second polymer layer may be applied to the worked second surface such that it covers at least the first polymer layer arranged on the separation regions. The second polymer layer may also cover at least portions of the second metallization layer. In some embodiments, the second polymer layer covers peripheral regions of discrete portions of the second metallization layer and defines one or more contact pads which may be connected to a further conductive surface by solder.

In some embodiments, the second metallization layer includes a portion which extends from the first device region to the second device region and which extends over the non-device region which may comprise the first polymer layer. In some embodiments, the second polymer layer may abut this device connection portion of the second metallization layer or may cover peripheral edge regions of this portion of the second metallization layer and define a contact pad which is exposed from the second polymer layer. In other embodiments, this device connection portion of the second metallization layer may be entirely covered by the second polymer layer which provides electrical insulation of this portion of the metallization layer. This arrangement may be used if an electrical contact directly to this portion of the second metallization layer is not required or in embodiments in which electrical insulation of this portion of the layer and circuit is desirable or required.

In some embodiments, the second metallization layer may be applied by applying a conductive seed layer to the worked second surface, applying a second polymer layer to the seed layer such that at least portions of the seed layer are exposed from the second polymer layer, and applying a conductive layer to the exposed portions of the seed layer. The seed layer may be applied using vacuum deposition techniques, such as sputtering or chemical vapour deposition. The conductive layer may be applied to the seed layer using electrodeposition techniques, such as electroless deposition or galvanic deposition.

The conductive seed layer may be applied to the worked second surface such that the first polymer layer arranged in the separation regions and in the non-device regions and semiconductor material of the first and second device regions are covered by the seed layer. The second epoxy layer may be applied to the seed layer such that the separation regions are covered by the second polymer layer and such that regions of the worked second surface comprising semiconductor material and the first polymer layer arranged in the non-device regions are uncovered by the second polymer layer. The conductive layer is than applied to the seed layer in the portions uncovered by the second polymer layer in order to form the second metallization layer.

At least two devices are fabricated on the wafer so that the distances between chips can be reduced and are limited only by separation processes, for example 10-50 μm for mechanical half-cut dicing or plasma half-cut dicing. The multi-chip die is encapsulated in epoxy and only the corresponding connections are open metallic surfaces, for example copper surfaces. With the help of a via, direct connection between front side 1 (source1) and back-side 2 (drain2) of different chips are possible. Due to the encapsulated nature of the multi-chip die it can be directly picked and placed in standard packages like QFN or in chip embedding approaches.

Different types of devices may be processed next to each other on a silicon wafer. Once the processing of the front-side of the chips has been completed, a half-cut process step is performed. Here, the individual chips or devices are isolated from each other. At the same time the lines for separation between the individual multi-chip dies or multi-device modules are also half-cut. Following a dice-before-grind-with-epoxy process, the chips and half-cut lines (depth of half-cut˜wafer target thickness+10 um) are covered and filled with epoxy. The copper pads on the front side are then opened in a lithography step making use of the corresponding epoxy properties. After mounting the wafer on a glass carrier, the wafer is thinned to its desired thickness, for example 15-20 μm. In the thinning process the epoxy filled half-cuts are exposed on the backside. Now a Copper back-side is deposited. This may be achieved by a sputtered Ti/Cu seed layer that is brought to a final thickness via electrodeposition of copper. Depending on the thickness also only sputtering is possible. Afterwards, the copper backside is structured in a manner that the multi-chip dies are connected to form the intended circuit.

The silicon through via can thereby be formed from the front-side before the half-cut dicing or from the back-side before the seed layer deposition. After the Cu backside structuring the complete backside is covered with epoxy again and the intended copper pads are opened in a lithography step making use of the corresponding epoxy properties. After the curing of the epoxy, the wafer is frame-demounted and the multi-chip dies are separated by a laser cut through the epoxy. Now the multi-chip dies can be picked in a standard manner from a dicing foil to be placed in standard packages.

Alternatively, both the copper front-side and copper-backside contacts and the silicon through via can be formed by using the corresponding front- and backside epoxy as a pattern plating mask on the pre-structured seed layer. This is achieved with the help of electroless plating. In this way the silicon through via can be integrated in a preexisting process flow.

The concept can be applied straight forwardly to integrate passive components like capacitors or inductors if they are formed on part of the wafer next to the corresponding connection chips. These passive components are treated like additional chips or as a part of one of the multi-chip system. Integration of these passive components may be of interest in integrated solutions since it allows the minimization of loop inductances and stray passive component contributions. This directly improves the performance of the solution and allows better control of overshoot behavior.

FIG. 2illustrates a schematic cross-sectional view of a semiconductor module30. The semiconductor module30includes a first electronic device31in a first device region32and a second electronic device33in a second device region34. The first electronic device31is operably connected to the second electronic device33to form a circuit. In the illustrated embodiment, the first electronic device31is a transistor device, in particular a vertical transistor device, having a gate pad35and source pad36on a first surface37and a drain pad38on a second surface39which opposes the first surface37. The second electronic device33is also a transistor device, in particular a vertical transistor device having a gate pad40and source pad41on a first surface42and a drain pad43on a second surface44that opposes the first surface42. The first surface42of the second electronic component33is substantially coplanar with the first surface37of the first electronic component31and the second surface44of the second electronic component33is substantially coplanar with the second surface39of the first electronic component31.

The module30has a first major surface45which includes at least one contact pad. In the embodiment illustrated inFIG. 2, the first major surface45includes four contact pads which are coupled to the source pad36and gate pad35of the first electronic device31and to the gate pad40and source pad41of the second electronic device33. The semiconductor module30also includes a second major surface46that opposes the first major surface45. The semiconductor module30includes a first polymer layer47, in particular, a first epoxy layer, that is arranged on the first major surface45and which leaves at least portions of the contact pads35,36,40,41exposed.

The first polymer layer47may be arranged on peripheral regions of the contact pads35,36,40,41. The first polymer layer47covers side faces48of the first electronic device31and the second electronic device33such that the first electronic device and the second electronic device33can be considered to be embedded in the first polymer layer47. The semiconductor module30also includes a conductive redistribution structure49that electrically couples the first electronic device31to the second electronic device33.

In this embodiment, the conductive redistribution structure49includes a conductive via50which extends from the first major surface45to the second major surface46of the semiconductor module30. The conductive via50may be positioned in with the first device area32or in the second device area34and may be called a through silicon via. The conductive via50may be electrically insulated from the semiconductor material of the electronic device by an insulation layer55. The via50provides an electrically conductive connection from the first major surface45to the second major surface46of the module and from the first surface42of the second electronic device33to the second surface39of the first electronic device32. The redistribution structure49further includes a conductive layer51that extends laterally on the second major surface46of the module and is arranged on the via50formed in the second electronic device33.

The conductive layer51is arranged on the conductive via50and on a portion of the first polymer layer47which forms part of the second major surface46. The conductive layer51extends from the drain pad38of the first electronic device31to the conductive via50and is positioned not only on the first electronic device31and a portion of the first polymer layer47but also on a portion of the second major surface44of the second electronic component33.

The conductive via50may extend between the source pad41and the second surface44of the second electronic component33and be electrically coupled to the source pad41. The conductive layer51in combination with the conductive via50provides a redistribution structure49from the source pad41of the second electronic device33to the drain pad38of the first electronic device31. In this particular embodiment, this arrangement can be used to form a half bridge configuration in which the first electronic component31is the low side switch of the half bridge configuration and the second electronic device33is the high side switch of the half bridge configuration.

A further conductive layer56may be arranged on the drain pad43of the second electronic device33such that the outer surfaces of the further conductive layers51,56are substantially coplanar.

The conductive layer51that extends from the second surface39of the first electronic device31onto the second surface44of the second electronic device33is electrically insulated from further conductive portions arranged on the second surface44of the second electronic device33, such as the contact pad56, and from the body of the second electronic device33by the insulating layer55. The insulating layer55lines the side walls of the via50and extends over and is arranged directly on the second surface44of the second electronic device33in regions adjacent the via50. The insulating layer55has a lateral extent such that it is positioned between the second surface44and the conductive layer51and electrically insulates the conductive layer51from the second surface44and the second surface44of the second electronic device33from the second surface39of the first electronic device31.

The module30may be fabricated using the method illustrated inFIG. 1whereby the first electronic component31is formed from the first device region and the second electronic component33is formed from the second device region of the semiconductor wafer. The region between adjoining side faces48of the first and second electronic components31,33is the non-device region of the component position of the semiconductor wafer. The outermost surface53of the semiconductor module30is formed by portions of the first polymer layer47which are formed by insertion of the separation line in the separation regions of the semiconductor wafer.

The semiconductor module30is formed from a semiconductor wafer by insertion of trenches and filling of the trenches with a first polymer layer which is arranged so as to embed at least the side faces of the electronic devices31,33in the first polymer layer47. The first polymer layer47provides a mechanical matrix holding the electronic devices31,33together. The conductive connection between the electronic devices31,33to form the desired circuit, in the embodiment illustrated inFIG. 2, a half bridge configuration can be formed by deposition of conductive layers on the first and second major surfaces45,46and in the case of one or more vertical devices, by the provision of one or more conductive vias50extending between the major surfaces45,46of the semiconductor module30.

The via50may be arranged in a device region. In the embodiment illustrated inFIG. 2, the via50is arranged in the second electronic component33and extends between the first surface42and second surface44of the second electronic component33.

FIGS. 3A and 3Billustrate a cross-sectional view of a semiconductor module30′ which in addition to the features illustrated inFIG. 2further includes a second polymer layer54arranged on the second major surface46of the semiconductor module30′. The second polymer layer54may also be a curable polymer, such as a thermosetting polymer composition and in some embodiments includes an epoxy resin.

In some embodiments, such as that illustrated inFIG. 3A, the second polymer layer54may be arranged at the peripheral edges of the semiconductor module30′ and be arranged in contact with portions of the first polymer layer47arranged adjacent the side faces48of the first electronic component31and of the second electronic component33. The second polymer layer54may also be arranged between conductive regions of the second major surface46of the semiconductor module30′. For example, in the embodiment illustrated inFIG. 3A, the second polymer layer is arranged between the further layer51and the drain pad43. In some embodiments, the second epoxy layer54may cover the peripheral regions of the drain pad43and the conductive layer51.

In some embodiments such as that illustrated inFIG. 3B, the conductive layer51is covered entirely by the second polymer layer54and at least a portion of the drain pad43remains uncovered by the second polymer layer54.

In the embodiments illustrated inFIGS. 2 and 3, the first electronic device31and the second electronic device33is a transistor device and the circuit formed is a half bridge circuit. However, the types of electronic devices arranged in the first and second device regions of the semiconductor module are not limited to transistor devices. For example, one of the electronic devices may be a transistor device and the other of the electronic devices may be a driver device, for example a gate driver device, or part of a gate driver device such as a pull-down FET, for driving the gate of the transistor device, or a diode or passive device such as an inductor, a capacitor or a resistor. Furthermore, the module is not limited to including just two electronic devices and may include three or more electronic devices. For example, the module may include two transistor devices coupled to form half bridge circuit, and also a driver device, or part of a gate driver device such as a pull-down FET, for driving the gates of the two transistor devices.

As mentioned above, in embodiments in which the module includes a redistribution structure having a vertical portion extending between the first major surface and the second major surface of the module, the vertical portion may be provided by one or more conductive vias which are positioned in one or more of the electronic devices. In these embodiments, the sidewalls of the via are formed by the semiconductor material, for example silicon, of the electronic device. In other embodiments, the vertical portion of the redistribution structure may be positioned laterally adjacent the electronic devices.

FIG. 4illustrates a module60which includes a first electronic device61and a second electronic device62arranged laterally adjacent each other and embedded in a first polymer layer63which covers at least portions of the side faces64of both the first electronic device61and second electronic device62. In some embodiments, the first polymer layer63may cover peripheral regions and edges of a first major surface65of the first electronic device61and a first major surface66of the second electronic device62which is positioned laterally adjacent the first major surface65of the first electronic component61and may be substantially coplanar with the first major surface65of the first electronic component61. The portion of the first polymer layer63arranged between the first electronic device61and second electronic device62may be described as a non-device region67with the first electronic device61being arranged in a first device region68and the second electronic device62being arranged in a second device region69.

In this embodiment, a conductive via70is arranged in the non-device region67. The conductive via70has sidewalls71formed by the material of the first polymer layer63. The conductive via may have an elongate shape in plan view. The conductive via70may include conductive material, such as a metal, for example copper. In some embodiments, the side walls71defining the via72in the first polymer layer63may be lined with one or more metal layers which may be used to improve the adhesion to the material of the first polymer layer63as well as one or more conductive layers having a thickness suitable for carrying the current required by the particular application. In some embodiments, the via72may be substantially filled with conductive material.

The semiconductor module60also includes a first metallization structure73arranged at the first major surface74of the module60. The first metallization layer73may include two or more conductive portions with one or more conductive portions being arranged on the first major surfaces65,66of the first and second semiconductor devices61,62. Similarly, the semiconductor module60may include a second metallization layer75arranged at the second major surface76of the module60which is structured to provide one or more portions on the second surfaces77,78of the first and second electronic devices61,62respectively. The conductive via70may be electrically coupled to a portion of the first metallization structure73, which extends from one of the electronic devices, for example, the second electronic device62, to the conductive via70. The conductive via70may be coupled to the other one of the electronic devices, for example the first electronic device61, by a portion of the second metallization layer75arranged on the opposing side of the module76which extends between the first electronic device61and the conductive via70.

In the case of the first and second electronic devices61,62being transistor devices and the desired circuit being half bridge configurations, a portion of the second metallization structure75may extend from a drain pad positioned at the second surface77of the first electronic device61to the conductive via70and a portion of the first metallization layer73may extend from the conductive via70to a source pad arranged at the first major surface66of the second electronic device62.

The portion of the second metallization structure75that extends from the second surface77of the first electronic device61onto the second surface78of the second electronic device62is electrically insulated from further portions of the second metallization structure75arranged on the second surface78of the second electronic device62, such as the contact pad82. This electrical insulation may be provided by an insulating layer63that lines the side walls of the via70and extends over and is arranged directly on the second surface78of the second electronic component62in regions adjacent the via70. The portion of the second metallization structure75that is positioned on the second surface78of the second electronic device62is arranged on this insulation layer63. The insulation layer55also serves to electrically insulate the second surface78of the second electronic device62from the second surface77of the first electronic device61.

In other embodiments, the conductive layer75has a lateral extent such that it does not extend onto the semiconductor body of the first electronic device61and extends only to the conductive material in the via70.

FIG. 5illustrates an enlarged top view and enlarged side view of the conductive via70in the semiconductor module60. The first electronic component61includes a contact pad79on its first major surface65which, may be a source pad if the first electronic component is a transistor device for example, and a second contact pad80on its second major surface77which may be a drain pad for example. The second electronic component62also includes a contact pad81on its first major surface66and contact pad82on its second major surface78. The contact pad81may be a source pad and the contact pad82may be a drain pad if the second electronic component is a transistor device. Each transistor device may also include a gate pad which cannot be seen in the views ofFIG. 5. Edge regions83of the first electronic device61that are formed between the first major surface65and the side face64are covered by a portion84of the first polymer layer63. The entire side face64of the first electronic component61may be covered by the first polymer layer63. Similarly, the edge region85of the second electronic device62formed between the first major surface66and side face64may be covered by the first polymer layer63. The first polymer layer63may abut the contact pads79,81arranged on the first major surfaces65,66of the first and second electronic devices61,62, respectively.

The redistribution structure86used to couple the contact pad80with the contact pad81arranged on the opposing sides of the module60may be formed by a conductive path which extends from the contact pad80through the via72to the contact pad81to electrically couple the drain of the first electronic device61to the source of the second electronic device62. The redistribution structure86includes a via72formed in the first polymer layer64which extends substantially parallel to side faces64of the first and second electronic devices61,62. The via72may have sidewalls71which are roughened to improve the adhesion to the conductive material positioned within the via72. The sidewalls71of the via72may also be a lined with one or more adhesion layers. The redistribution structure86may be formed using several portions. For example, the conductive via72extending through the first polymer layer63may be filled with conductive material and a lateral layer87applied to the upper surface of the via70which extends from the via70to the contact pad81. A second lateral layer88may be applied to the opposing rear side of the module60which extends from the contact pad80to the lower surface of the conductive via70. In other embodiments, a conductive layer may be applied which extends from the contact pad81into the via72and by a layer which extends from the contact pad80into the via71such that the two conductive layers join at a position in the via72adjacent the side faces64and a continuous conductive path is produced.

The semiconductor module according to any one of the embodiments described herein may be used to form a circuit by mounting the module onto a higher level substrate including a redistribution structure, for example a circuit board such as a printed circuit board. In other embodiments, the semiconductor module may be packaged. Packaging the semiconductor module enables the module to be provided in the form of a package with a standard footprint and standard outline which may assist in simplifying use of the module in particular application.

FIG. 6illustrates a schematic view top view of the semiconductor module30′ ofFIG. 3Baccommodated within a package90. In the illustrated embodiment, the package90includes a die pad91, five leads92to96and a plastic housing97. The die pad91and inner portions of the leads92to96are positioned within the plastic housing97. Portions of the leads92to96extend outside of plastic housing97and provide the external contact contacts to the package90. In this embodiment, the leads92to96are positioned adjacent a single side of the die pad91with the central one of the five leads, lead94, being integral with the die pad91. The module30′ is mounted on the upper surface98of the die pad91.

Since the drain pad43of the second electronic device33is exposed at the second major surface46of the semiconductor module30′ and the drain pad38of the electronic device61, the further conductive layer51and conductive via50are covered by the second polymer layer54, by mounting the second major surface46of the module30′ to the upper surface98of the die pad90, the drain pad43of the second electronic device33may be electrically coupled to the die pad91and therefore the central lead94. The pads35,36,40,41arranged at the first major surface45of the module30′ face upwardly and may be electrically coupled to the leads92,93,95,96, which are spaced apart from the die pad91, by conductive connections such as one or more bond wires, conductive ribbons or contact clips. The source pad36may be coupled to the first lead92, the gate pad35may be coupled to the lead93, the source pad41and the gate pad40of the second electronic device33may be coupled to the leads95,96respectively.

Also illustrated in the top view ofFIG. 6is the non-device area100of the module30′. The device areas32,34are indicated by dashed lines. The conductive via50is positioned underneath the source pad41and is also indicated by a dashed line.

The package is not limited to one having the arrangement of die pad, leads, connections and housing illustrated inFIG. 6. For example, the package may be a Surface Mount Device, such as a Super SO8 package or QFN (Quad Flat No Lead) package. A contact clip may be used in place of bond wires for power connections, e.g. connections other than a connection to the gates, for example.

A method for fabricating a semiconductor module according some embodiments will now be described with reference toFIGS. 7A to 7I.

FIG. 7Aillustrates a cross-sectional view of a semiconductor wafer110including a first major surface111and a second major surface112which opposes the first major surface111. The semiconductor wafer110includes a plurality of component positions of which two component positions113,113′ are illustrated inFIGS. 7A to 7I. Adjacent component positions are spaced apart from one another by a separation region114. The semiconductor wafer110may comprise silicon and may be a silicon single crystal wafer or a silicon single crystal wafer comprising an epitaxial silicon layer on top in which semiconductor devices are formed, whereby the epitaxial layer provides the first major surface111and the silicon single crystal wafer provides the second major surface112.

The component positions113are typically arranged in rows and columns to form a regular grid such that the separation regions114provide have the form of substantially orthogonal stripes in plan view. Each component position113includes two or more device regions115,116which are separated by a non-device region117which does not include any device structures. The wafer110also includes a first metallization structure118on its first major surface111. The first metallization structure118may be structured so that it is positioned in only the device regions115,116and such that the non-device region117is free from first metallization structure118.

One of the device positions of the component position113, for example the device regions116, includes one or more conductive vias134which extends from the first metallization structure118into the wafer110to a depth. The conductive via134may have the form of a blind via135having a base positioned at a depth from the first major surface111which is greater than the predetermined final thickness of the electronic components as is illustrated inFIG. 7B. The blind via135may include insulation material (not seen in the figures) that covers at least the side walls of the blind via135and conductive material arranged on the insulation material. The conductive material may include one or more liner layers lining the side walls of the blind via and one or more further conductive materials on the liner layers. The conductive material may fill the remainder of the blind via135. The conductive material may include one or more metals or alloys and/or polysilicon.

FIG. 7Billustrates the wafer110after the formation of first trenches119which have been inserted into the first major surface111in the separation regions114and after the formation of second trenches120which have been inserted into the first major surface111in the non-device regions117. The trenches119,120may have a depth d which is slightly larger than the predetermined final thickness tfof the electronic components and which is less than the initial thickness tiof the wafer110.

FIG. 7Cillustrates the wafer110after a first polymer layer121, which in this embodiment comprises epoxy, has been inserted into the first trenches119and second trenches120. In this embodiment, the first polymer layer121also extends over the peripheral regions of the discrete portions of the first metallization layer118and therefore has an uppermost outer surface122which is positioned in a plane above the outer surface123of the first metallization structure118. In other embodiments, the first polymer layer may abut the portions of the first metallization layer and form a substantially coplanar surface.

FIG. 7Dillustrates the wafer110after a carrier124has been applied to the outer surface122of the first polymer layer121. Since the outer surface122of the first polymer layer121is arranged at a plane above the outer surface123of the first metallization layer118, cavities125are formed between the carrier124and the first metallization structure118.

FIG. 7Eillustrates the removal of portions of the second major surface112of the semiconductor wafer110so that the initial thickness tiof the wafer110is reduced to the final desired thickness tfand such that portions of the first polymer layer121arranged in the separation region114and in the non-device regions117are exposed in the worked second surface126and the conductive material arranged in the blind vias134in the second device positions116is exposed at the worked second surface to produce a through contact or through-silicon-via (TSV). The removal of portions of the wafer110is indicated schematically inFIG. 7Eby the arrows127. The portions of the second surface112of the semiconductor wafer110may be removed by grinding and/or chemical mechanical polishing, for example.

FIG. 7Fillustrates the application of a second metallization structure128to the worked second surface126. In some embodiments, one or more insulation layers, for example an oxide layer, may be applied to the worked second surface126and structured before application of the second metallization structure128to the worked second surface. The second metallization layer128may include a seed layer129and further conductive layer130applied to the seed layer129. The second metallization layer128may be applied such that it forms a closed layer extending over the exposed portions of the first polymer layer121, the worked second surface131of the device regions115,116and portions of the conductive material in the vias134which are exposed at the worked second surface126.

The conductive layer130may be structured as illustrated inFIG. 7Gso that the separation114regions are free of the conductive layer. The structure of the second metallization layer128may be carried out such that an electrical connection between the first device area115and the second device area116within each component position113is formed. One or more further discrete conductive areas may also be formed within one or both of the component positions113depending on the desired electrical connections for the circuit.

The conductive via134may be electrically coupled to a structured portion136of the second metallization layer128that extends over the non-device region117onto the other device, for example from the second device area116to the first device area115in the embodiment illustrated inFIG. 7G. One or more further discrete structured portions137that are separate from the structured portion136may be formed on the first device area115and/or second device area116. The device area including a via may include a discrete portion and a portion that extends onto a neighbouring device area.

In some embodiments, a second polymer layer131may be applied to the separation regions114and non-device regions117at the worked second surface126. In some embodiments, such as that illustrated inFIG. 7Hthe second metallization layer128may be structured such that both the conductive layer130and the seed layer129and some portions of the first polymer layer121arranged at the worked second surface126in the separation regions114are removed. The second polymer layer131may be applied in the separation regions114as shown inFIG. 7Isuch that it is in contact with the first polymer layer121and overlaps peripheral regions of the second metallization layer128formed in the component positions113. The interface between the first polymer layer and the second polymer layer131may be positioned adjacent sidewalls of the device regions115,116. The semiconductor modules132may then be singulated from the wafer by inserting a separation line133, for example by sawing, along the separation regions114. The width of the separation line may be less than the width of the separation region114such that the outermost side faces of the individual modules132are covered by the first and second epoxy layers121,131.

In some embodiments, the semiconductor module132includes a redistribution structure including a vertical portion which extends substantially perpendicular to the first and second lateral major surfaces. As discussed above, this vertical portion may be provided by a conductive via134which may be positioned within one or more of the device regions115,116and consequently have sidewalls formed by semiconductor material of the electronic device. Sidewalls of the via may be lined with an insulating material so as to electrically insulate the conductive material within the via from the semiconductor material of the electronic device. The conductive material may include one or more metals.

In other embodiments, the conductive via may be positioned in the non-device region117and formed by inserting a further trench in the polymer material in the non-device region117. Such a conductive via extends substantially parallel to side faces of the adjacent device regions115,116. The conductive material within the via is electrically insulated from the semiconductor material of the device regions115,116by the polymer material. The sidewalls of the conductive via are formed by polymer material. This embodiment may be used to manufacture the semiconductor module60illustrated inFIGS. 4 and 5.

In some embodiments, the vertical portion of the redistribution structure may be formed by semiconductor material and may be formed by a portion or island of semiconductor material positioned within the device region.

FIG. 8illustrates a cross-sectional view of a module140including the first electronic device31arranged in a first device region32and second electronic device33formed in a second device region34as in the embodiment illustrated inFIG. 2. The semiconductor module140differs in the form of the vertical portion of the redistribution structure between the drain pad38on the second surface39of the first electronic device31and the source pad41arranged on the first surface42of the second electronic device33. In this embodiment, the second device region34comprises an island141of semiconductor material which is electrically insulated from the further semiconductor material142of the second electronic device33by insulating material143. The insulation layer143extends form the first surface42to the second surface44to isolate the island141from the remainder of the second electronic device33.

In the embodiment illustrated inFIG. 8, the island141is formed at the periphery of the second electronic component33and is bounded on at least one side by a portion of the polymer material first polymer layer47which is arranged between the side faces48of the first and second electronic devices31,33.

The island141may include a semiconductor material having a conductivity which is higher than the conductivity of the semiconductor material142of the electronic device. The island141may be more highly doped that the semiconductor material of the electronic device. In embodiments in which the electronic devices31,33are formed from a semiconductor wafer including an epitaxial layer on a substrate, the epitaxial layer may be processed to form the transistor device structures at the first surface37,42. The substrate may be highly doped and have a sufficient conductivity for forming the drain region and a portion of the redistribution structure. In these embodiments, the upper epitaxial layer may be removed from the substrate at the upper portion of the island141and replaced by material having a higher conductivity in order to form a vertical conductive connection from the first surface42to the opposing second surface44. Alternatively, the conductivity of the epitaxial layer may be locally increased in the island141by increasing the doping level, for example, by implantation, a contact extending through the upper epitaxial layer to the underlying substrate or the combination of a contact extending through the upper epitaxial layer and a locally increased doping level may be used.

The conductive island141may be electrically coupled to the source pad41arranged on the first surface42of the second electronic component33by a conductive layer144which extends between the island141and the source pad41. The conductive island141may be electrically coupled to the drain pad38arranged on the second surface39of the first electronic component31by the conductive layer51on the opposite side of the island141which extends from the drain pad38to the island141. The conductive layer51has a lateral extent such that its periphery is arranged on the insulating material143and stops short of the semiconductor body of the second electronic device33so that it is not arranged on the rear side44of the electronic device33.

In other embodiments, the island may be formed within the semiconductor material of the device region such that it is surrounded on all side faces by the insulating material143.

A second polymer layer54may be arranged on the second surface39of the first electronic device31and second surface44of the second electronic device33between the further conductive layer51and drain pad38and at the periphery of the module. The second polymer layer54may also entirely cover the further conductive layer51.

FIG. 9illustrates a semiconductor module150which includes a first electronic device31arranged in a first device region32and second electronic device33formed in a second device region34as in the embodiment illustrated inFIG. 2. The semiconductor module150further includes a redistribution structure between the drain pad38on the second surface39of the first electronic device31and the source pad41arranged on the first surface42of the second electronic device33in the form of a conductive island141of semiconductor material as in the embodiment illustrated inFIG. 8. The conductive island141is electrically insulated from the further semiconductor material142of the second electronic device33by insulating material143.

The semiconductor module150differs from the semiconductor module140ofFIG. 8in that the separation regions151formed between the outermost facing side faces48of the device regions32,34of the module150and the non-device regions152extending between side faces48include insulating material153which is separate from the first and second polymer layers47,54. The insulating material153may be the same as or different from the insulating material143which electrically insulates the conducive island141providing the vertical redistribution structure from the body of the second semiconductor device33. The insulating material153may comprise an oxide or a nitride, such as SiO2for example.

The insulating material153has a thickness which corresponds to the thickness of the first electronic device31and the second electronic device33and extends from the first surface37to the second surface of the first electronic device31and from the first surface42to the second surface44of the second electronic device33. The first polymer layer47is arranged on the insulating material153in the separation regions151and in the non-device regions152. The second polymer layer54is arranged on the insulating material153in the separation regions151.

The conductive layer51extends from the drain pad38over the second major surface37of the first electronic device31and over the insulating material153in the non-device region151. The conductive layer51has a lateral extent such that its periphery is arranged on the insulating material143which insulates the island141from the semiconductor body of the second electronic device33and stops short of the semiconductor body of the second electronic device33so that it is not arranged on or electrically coupled with the rear side44of the electronic device33.

As in the embodiment illustrated inFIG. 3B, the further conductive layer51may be entirely covered by the second polymer layer54, as illustrated inFIG. 9, or abut the further conductive layer51, as in the embodiment illustrated inFIG. 8.

To summarize, embodiments described herein, combine advantages of multi-chip dies such as closer chip distances, single picking of multi-chip die, and front-side contacting of gate and sense-pads and can be used to provide a module and electronic component with a desired circuit cost-effectively and efficiently.

In some embodiments, such as those illustrated inFIGS. 2, 3A-3B and 7A-7I, at least one of the semiconductor devices33of the semiconductor module30,30′;132includes a conductive via50;134that includes conductive material positioned in a via or through-hole which extends from the front surface to the rear surface of the semiconductor body of the semiconductor device. The conductive via50;134may be manufactured by inserting the via into the front surface111of the semiconductor wafer110, as in the embodiment illustrated inFIG. 7A. In other embodiments, the conductive via50;134may be formed by inserting the via into the opposing rear surface112of the semiconductor wafer110.

Embodiments for forming a conducive via will now be described with reference toFIGS. 10A to 15for a semiconductor package that includes a single semiconductor device. These embodiments can, however, also be used for fabricating a conductive via in a semiconductor module including two or more semiconductor devices, for example the module described with reference toFIGS. 1 to 9, whereby one, both or all of the semiconductor devices of the module may include a conductive via.

FIG. 10Aillustrates a cross-sectional view of a semiconductor wafer160including a first major surface161and a second major surface162which opposes the first major surface161. The semiconductor wafer160may comprise silicon and may be a silicon single crystal wafer or a silicon single crystal wafer comprising an epitaxial silicon layer on top in which semiconductor devices are formed, whereby the epitaxial layer provides the first major surface161and the silicon single crystal wafer provides the second major surface162.

The semiconductor wafer160includes a plurality of component positions163of which two are illustrated inFIG. 10. The method will be described with reference to a single component position163. However, in practice, the method is carried out on all of the component positions in the wafer160. Adjacent component positions163are spaced apart from one another by a separation region164. The component positions163are typically arranged in rows and columns to form a regular grid such that the separation regions164provide have the form of substantially orthogonal stripes in plan view. Each component position163includes a single device region165that in this embodiment includes a single semiconductor device167. The device region165may include a power device167such as a transistor device, in particular a transistor device with a vertical drift path which is commonly referred to as a vertical transistor device. The vertical transistor device may be a MOSFET device or an IGBT, for example.

A vertical transistor device may have a first power electrode and a control electrode positioned on the first surface and a second power electrode positioned on the opposing second surface. The first power electrode may be a source of a MOSFET device or an emitter of an IGBT device, the second power electrode may be a drain of a MOSFET device or a collector of an IGBT device and the control electrode may be a gate of a MOSFET device or a gate of an IGBT device.

At least one first trench166is formed in the first surface161of the semiconductor wafer160in the device region165of the component position163. The first trench166may have an elongate form in plan view or may have a substantially circular or square form in plan view. In some embodiments, a plurality of first trenches may be formed in each component position163. The first trench166has a base171and sidewalls170and may have a depth which is less than the thickness of the semiconductor wafer160. The depth of the first trench166may also be slightly greater than the intended final thickness of the semiconductor die, for example around 10% deeper than the intended final thickness. The first trench166may be formed by etching.

In some embodiments, the first trench166has a ratio of width to depth of 0.5:1.0 to 1.5:1.0, for example around 1:1. This ratio may be used to assist in the reliable deposition of conductive material into the first trench166, for example by electrodeposition.

Referring toFIG. 10B, a first metallisation structure168is formed on the major first surface161and conductive material169is inserted into the first trench166. The conductive material169may include one or more sublayers and may fill the first trench166. In non-illustrated embodiments, the conductive material169lines the sidewalls170and base171of the first trench leaving a gap in the centre. The conductive material169may include a plurality of sublayers.

The first metallisation layer168may include a plurality of sublayers.FIG. 12illustrates an enlarged view of a structure which may be used for the first metallization structure168and illustrates the sublayers. The conductive material169which is positioned in the first trench166may include the same structure as the first metallization layer.

The structure of the sublayers illustrated inFIG. 12may also be used to form the first metallization layer of a semiconductor module including two or more devices that are electrically connected together to form a circuit, such as a half-bridge configuration. The structure of the sublayers illustrated inFIG. 12may also be used to form the first metallization layer of a semiconductor module as illustrated inFIGS. 1 to 9.

The structure of the sublayers positioned in the first trench166illustrated inFIG. 12may also be used for a conductive via in a semiconductor module, whereby the conductive via may be positioned in the semiconductor die, as in the embodiments illustrated inFIGS. 2, 3 and 7or between semiconductor dies, as in the embodiments illustrated inFIGS. 4 and 5.

In the embodiment illustrated inFIG. 12, the first metallization layer168includes sublayers of titanium (Ti), titanium nitride (TiN), tungsten (W), an aluminium copper alloy (AlCu) and copper (Cu) arranged in this order on the first surface161. In other embodiments, the structure of the first metallisation layer168may include sublayers of a titanium silicon alloy (TiSi), whereby the silicon is deposited with the titanium onto the first surface161, titanium nitride (TiN), tungsten (W), an aluminium copper alloy (AlCu) and copper (Cu). The copper layer may be deposited by a combination of physical vapour deposition (PVD) techniques and galvanic techniques, such as electroplating or electroless plating. InFIG. 10B, two copper layers172,173of the first metallisation structure168are indicated. The copper layer172, which is deposited by PVD, may have a thickness of around 5 μm and the copper layer173, which is deposited by galvanic techniques, may have a thickness of around 10 μm.

In some embodiments, the conductive material169in the first trench166may include sublayers of titanium (Ti), titanium tungsten (TiW) and copper (Cu) arranged in this in this order on the sidewalls170and base171of the first trench166, or titanium (Ti) and copper (Cu) arranged in this order on the sidewalls170and base171of the first trench166. The conductive material169may be inserted into the first trench166using two or more different processes. For example, the titanium and titanium tungsten sublayers may be deposited by physical vapour deposition (PVD) such as sputtering and the copper may be deposited using galvanic techniques. The copper layer may be deposited by a combination of physical vapour deposition techniques and galvanic techniques. The first trench166may also be lined with an insulating layer before deposition of the conductive material169.

The first metallisation layer168provides the outer contacts174of the final semiconductor package which form a package footprint175. In some embodiments, a further protective layer176is positioned on the outermost surface of the copper of the first metallization layer168.

The protective layer176may include a material to protect the underlying first metallization layer168from oxidation or corrosion, since the metallization layer168provides the outer contacts of the final semiconductor package. The protective layer176may include a metal or alloy, for example, Sn or Ag in the case of a copper outer layer of the first metallization layer168, and may also be present in the solder connection formed between the outer contact of the final semiconductor package and a higher level circuit board. The protective layer176may also be formed by a soft solder.

As illustrated inFIG. 10C, a second trench177is inserted into the first surface161of the semiconductor wafer160in the separation regions164. The second trench177has a base positioned within and formed by the semiconductor material of the semiconductor wafer160. The second trench177may have a depth that is slightly greater than the desired thickness of the semiconductor die. The second trench177may have approximately the same depth as the first trench166.

A first polymer layer178is applied is applied to the first major surface161, as illustrated inFIG. 10D, such that the second trench177and edge regions of the component positions163adjoining the separation regions164are covered with the first polymer layer178. The first polymer layer178may include an epoxy resin. In some embodiments, edge regions of the first metallisation layer168are also covered with the first polymer layer178such that central regions of the protection layer176remain exposed from the first polymer layer178. In these embodiments, the first polymer178is used to define the outer contacts174and the package footprint175.

The method then continues by removing portions of the second surface162of the semiconductor wafer160as indicated by schematically inFIG. 10dby the arrows179to reveal portions of the first polymer layer178in the separation regions164and the conductive material169in the first trenches166and produce a second worked surface162′. The first side161of the semiconductor wafer160may be mounted onto a carrier such as glass and the second surface162removed by grinding and/or chemical mechanical polishing to reduce the thickness of the semiconductor wafer160to the desired thickness. The desired final thickness may be in the range of 5 μm to 60 μm, for example, 15 to 30 μm.

A second metallisation layer180is applied to the second worked surface162′ as illustrated inFIG. 10e. Since the second metallisation layer180is in direct contact with the conductive material169in the first trenches166, the second metallisation layer180is operably coupled to the conductive material169in the first trench166and to an outer contact pad174on the first major surface161. The second metallisation layer180may also include a plurality of sublayers, such as titanium, and copper. The copper may be deposited using two different techniques, for example a physical vapour deposition technique may be used to deposit a first copper layer which may act as a seed layer and the further copper layer deposited onto the first copper layer by galvanic techniques. A protective layer may also be positioned on the copper layer. The protective layer may be silver or tin for example. In some embodiments, the protection layer applied to the second metallization layer180may be electrically insulating as the second metallization layer180does not provide an outer contact in the final semiconductor package.

In embodiments in which the device167is a vertical transistor device, the second metallisation layer180is coupled to the drain region of the transistor device and the conductive material169within the first trench166provides a vertical conductive path or via182from the drain region to the contact pad174which provides the drain outer contact186of the semiconductor package.

The semiconductor packages183are separated from the wafer160by cutting through the first polymer layer178positioned on separation regions164and, in particular, through the first polymer layer178positioned in the second trenches177. Side faces184of the final second semiconductor packages183may be coated by the first remaining portions of the first polymer layer178in embodiments in which the width of the cut inserted into the second trench177is less than the width of the second trench177. The resulting semiconductor package183is illustrated inFIG. 10f.

InFIGS. 10E and 10F, a cross-sectional view of the semiconductor wafer160is illustrated in which the drain outer contact186, a gate outer contact187and a source outer contact188of the semiconductor package183can be seen. The source electrode193and gate electrode194arranged on the first surface161of the component position163and transistor device167and the drain electrode195arranged on the second surface of the component position163and transistor device167are also illustrated in the cross-sectional view ofFIGS. 10E and 10F.

In some embodiments, a second insulating layer which may include a polymer such as an epoxy resin is applied to the worked second surface162′ after the formation of the second metallization layer180and before singulation of the packages183from the wafer160as is described in connection with the fabrication of the semiconductor module with reference toFIG. 7I.

In some embodiments, solder185is applied to the outer surfaces of the outer contacts174. The solder185may be applied before separation of the semiconductor packages183from the semiconductor wafer160. In some embodiments, the protective layer176of the first metallisation layer168may be omitted and the solder185may act as the protective layer.

The semiconductor packages183may be singulated or separated from the wafer160by laser cutting through the first polymer layer178and then removed from the dicing tape by a pick and place machine and placed into a carrier real for delivery to the customer. Electrical testing of the packages183may be carried out before singulation.

In some embodiments, a semiconductor package183is, therefore, formed that comprises a first transistor device167. The first semiconductor device163comprises a first surface161and a second surface162′ opposing the first surface161, a first power electrode, for example a source electrode, and a control electrode, for example a gate electrode, arranged on the first surface161and a second power electrode, for example a drain electrode, arranged on the second surface162′. The semiconductor package183includes a first metallization structure168arranged on the first surface, the first metallization structure168comprising a plurality of outer contact pads186,187,188, the outer contact pads186,187,188comprising a protective layer176of solder, Ag or Sn. The semiconductor package183further comprises a second metallization structure180arranged on the second surface162′, a conductive connection169extending from the first surface161to the second surface162′ and electrically connecting the second power electrode to an outer contact pad186of the first metallization structure168. A first epoxy layer178is arranged on side faces184and on the first surface161of the transistor device163, the first epoxy layer178comprising openings defining the lateral size of the outer contact pads186,187,188and the package footprint175.

In some embodiments, the semiconductor package further comprising a second epoxy layer on the second surface162′, wherein the second epoxy layer covers edge regions of the second surface162′ and leaves a region of the second metallization layer180exposed, or the second epoxy layer entirely covers the second metallization layer180.

In the method illustrated with reference toFIGS. 10A-10F, the first trenches166used for fabricating the conductive via182and the second trenches177used for separating the semiconductor packages183from the wafer160are both introduced into the wafer160from the first side161. In an alternative embodiment, the second trenches177are inserted into the first major surface161of the semiconductor wafer160and the first trenches166are introduced into the semiconductor wafer160from the second side162of the semiconductor wafer160. The first trenches166are introduced into the semiconductor wafer160after processing of the first side is completed and after the semiconductor wafer160has been thinned, the worked second surface162′ has been formed and the polymer layer178positioned in the second trenches177has been exposed in the worked second surface162′. This embodiment will be described with reference toFIGS. 11A-11D.

FIG. 11Aillustrates the semiconductor wafer160including the first major surface161and the second major surface162opposing first major surface161. The wafer160includes the component positions163separated by separation regions164with the semiconductor device167being positioned in the device region165of the component position163.

The first metallisation structure168is formed on the first surface163of the semiconductor wafer160on the component positions163and is structured to produce a plurality of outer contacts174forming package footprint175. The first metallization structure168may have the structure illustrated inFIG. 12. The second trench177is then formed in the first surface161of the semiconductor wafer160in the separation regions164and the first insulating layer178, which includes an epoxy, is applied to the first surface161such that it fills the second trenches177. The first polymer layer178may further extend over the peripheral edge regions of the component positions163and, in some embodiments, may also extend over peripheral regions of the first metallisation layer168and, therefore, peripheral regions of the outer contacts174of the package footprint175provided by the first metallisation layer168.

As illustrated inFIG. 11B, portions of the second surface162of the semiconductor wafer are then removed, revealing portions of the first polymer layer178positioned in the second trenches177of the separation regions164. The first surface including the first polymer layer178may be mounted on a carrier, such as a glass carrier and the second surface162is removed by grinding and/or chemical mechanical polishing to reduce the thickness of the semiconductor wafer160to the desired final thickness, which may lie in the region of 5 to 60 μm, and produce the second worked surface162′.

As illustrated inFIG. 11C, the first trench166is inserted into the worked second surface162′ in the device regions165of the component positions163. This first trench166is used for forming the vertical conductive connection between the worked second surface162′ and the first surface161of the semiconductor wafer160. The first trench166has a depth such that it has a base170formed by the first metallization layer168. The first trench166extends throughout the entire thickness of the thinned semiconductor after160.

Conductive material169is inserted into the first trenches166from the worked second surface162′ as illustrated inFIG. 11D. The conductive material169may include two or more sublayers. An embodiment is illustrated inFIG. 12, in which the conductive material169includes sublayers of titanium, titanium tungsten and copper in this order on the side walls171or titanium and copper in this order of the side wall171. The copper may be deposited using a two or more different methods, for example, physical vapour deposition, such as sputtering, to deposit a first copper layer and galvanic deposition to deposit further copper layer and increase the thickness filling the second trenches166.

The first trenches166may be inserted into the worked second surface162′ by etching the worked second surface162′. A sublayer of the first metallisation layer may be used as an etch stop. In some embodiments, for example for a first metallization layer168having the structure illustrated inFIG. 12, a tungsten sublayer may be used as an etch stop. The titanium sublayer of the conductive material169may be in direct contact with the tungsten layer of the first metallization layer168.

The second metallisation layer180is then applied to the worked second surface162′, as illustrated inFIG. 11d, such that it is in contact with the conductive material169positioned in the first trench166and such that it is operably connected to an outer contact174on the first surface161of the semiconductor wafer160. The semiconductor packages183are then singulated from the wafer160by cutting through the separation regions164and in particular, through the first polymer layer178positioned in the second trenches177, as indicated schematically inFIG. 11dby arrows189, to produce the semiconductor package183as illustrated inFIG. 10f.

As discussed above, the first metallisation structure168on the first major surface161of the semiconductor wafer160provides the outer contacts174for the semiconductor package183. The semiconductor package183is mounted onto a higher level circuit board by way of the outer contacts174, which are arranged on the first surface161of the semiconductor package183. A solder connection can be used, which may be applied to the outer contacts174as illustrated inFIG. 10F.

The outer contacts174each have a lateral size and an arrangement within the outer contour of the lower surface of the semiconductor package183which is called the package footprint175. The outer contacts174may have different arrangements and provide different package footprints.

FIGS. 13A and 13Billustrate two examples of a package footprint which may be provided by the first metallisation layer168of the package183. The package183includes a power transistor device167, such as a vertical MOSFET device or vertical IGBT device and includes a footprint175including a drain outer contact186, a gate outer contact187and a source outer contact188.

In the embodiment illustrated inFIG. 13A, the drain outer contact186has a U-shape and extends along three sides of the package footprint183. The source contact188and the gate contact187are positioned between the arms of the U with the gate contact187being positioned opposite the base of the U-shaped drain contact186. The outer contacts186,187,188are spaced apart from one another by regions of the first polymer layer178which includes an epoxy.

FIG. 13Billustrates a perspective view of a package footprint190for the semiconductor package183according to another embodiment. The package183includes a power transistor device167, such as a vertical MOSFET device or vertical IGBT device and includes a footprint200including a drain outer contact186, a gate outer contact187and a source outer contact188. In the package footprint190, the source outer contact188has a general rectangular shape as in the package footprint175. The drain outer contact186includes plurality of drain contact pads191which are arranged in two rows. The rows are arranged on two opposing sides of the first surface161of the semiconductor package183with the source pad188being arranged between the two rows. The gate outer contact187includes two gate contact pads192that are positioned adjacent the source pad188and between the two rows of four drain contact pads191. The drain contact pads191and the gate contact pads192may each have a circular form. However, other forms, such as elongate of square may be used.

FIG. 14illustrates a flow chart200of a method for fabricating a semiconductor package. In block201, at least one first trench is formed in a first surface of the semiconductor wafer in a device region, wherein the semiconductor wafer comprises separation regions arranged between component positions of the semiconductor wafer, the component positions comprising the device region comprising an electronic device. In block202, a first metallization structure is formed on the first surface in the component position, the first metallization structure comprising a plurality of outer contact pads forming a package footprint, and conductive material is inserted into the first trench. In block203, at least one second trench is formed in the first surface of the semiconductor wafer in the separation regions. In block204, a first epoxy layer is applied to the first surface of a semiconductor wafer such that the second trenches and edge regions of the component positions are covered with the first epoxy layer. In block205, portions of a second surface of the semiconductor wafer are removed, the second surface opposing the first surface, and revealing portions of the first epoxy layer in the separation regions and the conductive material in the first trenches and producing a worked second surface. In block206, a second metallization layer is applied to the worked second surface and operably coupling the second metallization layer to the conductive material and an outer contact pad on the first major surface. In block207, the first epoxy layer is cut through in the separation regions to form a plurality of separate semiconductor packages.

In this embodiment, the via in the from of the first trench is inserted into the first surface of the wafer and conductive material is inserted from the first surface into the via. The first trench may be a blind via and the conductive material in the blind via is exposed at the rear surface by removing portions of the second surface.

FIG. 15illustrates a flow chart210of a method for fabricating a semiconductor package. In block211, a first metallization structure is formed on a first surface of a semiconductor wafer, wherein the semiconductor wafer comprises separation regions arranged between component positions, the component positions comprising a device region comprising an electronic device, the first metallization structure being arranged on the component positions and comprising a plurality of outer contacts forming a package footprint. In block212, at least one second trench is formed in the first surface of the semiconductor wafer in the separation regions. In block213a first epoxy layer is applied to the first surface of a semiconductor wafer such that the second trenches, and edge regions of the component positions are covered with the first epoxy layer. In block214portions of a second surface of the semiconductor wafer are removed, the second surface opposing the first surface, and revealing portions of the first epoxy layer in the separation regions. In block215at least one first trench is formed in the worked second surface of the semiconductor wafer in the device region of the component position. In block216conductive material is inserted into the first trench. In block217a second metallization layer is applied to the worked second surface and operably coupling the second metallization layer to the conductive material and an outer contact pad on the first major surface. In block218the first epoxy layer is cut through in the separation regions to form a plurality of separate semiconductor packages.

In this embodiment, the via in the from of the first trench is inserted into the worked second surface of the wafer and conductive material is inserted from the worked second surface into the via. The via is inserted into the worked second surface such that it extends through the entire thickness of the semiconductor wafer and such that the base of the first trench is formed by a portion of the first metallization structure. The conductive material in the first trench is deposited directly onto the portion of the first metallization layer exposed at the base of the first trench. The second metallization layer is applied to the conductive material in the first trench that is arranged at the worked second surface.

The semiconductor package includes outer contacts that are formed above the semiconductor material providing the semiconductor device. For example, for a vertical transistor device, the drain, source and gate outer contacts forming the package footprint are arranged on the first major surface of the semiconductor device with the drain region on the opposing second major surface of the semiconductor device being electrically coupled to the drain outer contact disposed on the opposing first major surface by use of the conductive via (or through silicon via) that is positioned in the semiconductor device. The side faces and portions of the first major surface arranged between the outer contacts are covered with a insulating layer, which is typically a polymer layer such as an epoxy resin. These structures are formed at the wafer level so that a separate packaging step, for example a molding step or the mounting of the semiconductor device in a metal can is not used.

EXAMPLES

A method, comprising: forming at least one first trench in a first surface of a semiconductor wafer in a device region, wherein the semiconductor wafer comprises separation regions arranged between component positions of the semiconductor wafer, the component positions comprising the device region comprising an electronic device; forming a first metallization structure arranged on the first surface in the component position, the first metallization structure comprising a plurality of outer contact pads forming a package footprint, and inserting conductive material into the first trench; forming at least one second trench in the first surface of the semiconductor wafer in the separation regions; applying a first epoxy layer to the first surface of a semiconductor wafer such that the second trenches and edge regions of the component positions are covered with the first epoxy layer; removing portions of a second surface of the semiconductor wafer, the second surface opposing the first surface, and revealing portions of the first epoxy layer in the separation regions and the conductive material in the first trenches and producing a worked second surface; applying a second metallization layer to the worked second surface and operably coupling the second metallization layer to the conductive material and an outer contact pad on the first major surface; and cutting through the first epoxy layer in the separation regions to form a plurality of separate semiconductor packages.

A method, comprising: forming a first metallization structure on a first surface of a semiconductor wafer, wherein the semiconductor wafer comprises separation regions arranged between component positions, the component positions comprising a device region comprising an electronic device, the first metallization structure being arranged on the component positions and comprising a plurality of outer contacts forming a package footprint; forming at least one second trench in the first surface of the semiconductor wafer in the separation regions; applying a first epoxy layer to the first surface of a semiconductor wafer such that the second trenches, and edge regions of the component positions are covered with the first epoxy layer; removing portions of a second surface of the semiconductor wafer, the second surface opposing the first surface, and revealing portions of the first epoxy layer in the separation regions; forming at least one first trench in the worked second surface of the semiconductor wafer in the device region of the component position; inserting conductive material into the first trench; applying a second metallization layer to the worked second surface and operably coupling the second metallization layer to the conductive material and an outer contact pad on the first major surface; and cutting through the first epoxy layer in the separation regions to form a plurality of separate semiconductor packages.

The method of Example 1 or Example 2, wherein the cutting through the first epoxy comprises forming a cut having a width that is less than the width of the second trench so that at least portions of side faces of the plurality of separate semiconductor packages comprise a portion of the first epoxy layer.

The method of any one of Examples 1 to 3, wherein the first epoxy layer further covers edge regions of the first metallization structure.

The method of Examples 4, wherein openings in the first epoxy layer define the lateral size of the outer contact pads and the package footprint.

The method of any one of Examples 1 to 5, further comprising applying a protective layer to the outer contact pads, wherein the protective layer comprises solder or Ag or Sn.

The method of any one of Examples 1 to 6, wherein the first trench has a ratio of width to depth of 1:1 and the conductive material is inserted by electrodeposition.

The method of any one of Examples 1 to 7, wherein the first metallization layer is formed by applying a Ti-containing layer, a W layer, a Al-containing layer and a Cu layer in this order.

The method of Example 8, further comprising applying a TiN layer between the Ti-containing layer and the W layer.

The method of any one of Examples 1 to 9, wherein the second metallization layer is formed by applying a Ti-containing layer and a Cu layer.

The method according to Example 10, further comprising applying a TiW layer between the Ti-containing layer and the Cu layer.

The method according to one of Examples 2 to 11, wherein the first trench is inserted into the worked second surface of the semiconductor wafer by etching and a W layer of the first metallization structure arranged on the first surface of the semiconductor wafer acts as an etch stop.

The method of any one of Examples 1 to 12, further comprising applying a second epoxy layer to the worked second surface such that the second epoxy layer covers edge regions of the component positions and, optionally, edge regions of the second metallization layer, or such that the second epoxy layer entirely covers the second metallization layer.

The method of any one of Examples 1 to 12, wherein the component positions of the semiconductor wafer further comprise a further electronic device, the further device region being laterally separated from the device region by a non-device region.

The method of Example 14, wherein the first trench is positioned in the non-device region.

The method of Example 14 or Example 15, wherein the second metallization layer is further applied to the further electronic device and operable couples the further electronic device to the conductive material and the outer contact pad on the first major surface and the electronic device.

A semiconductor package, comprising: a first transistor device comprising: a first surface and a second surface opposing the first surface, a first power electrode and a control electrode arranged on the first surface and a second power electrode arranged on the second surface; a first metallization structure arranged on the first surface, the first metallization structure comprising a plurality of outer contact pads, the outer contact pads comprising a protective layer of solder, Ag or Sn; a second metallization structure arranged on the second surface; a conductive connection extending from the first surface to the second surface and electrically connecting the second power electrode to an outer contact pad of the first metallization structure; and a first epoxy layer arranged on side faces and on the first surface of the transistor device, the first epoxy layer comprising openings defining the lateral size of the outer contact pads and a package footprint.

The semiconductor package of Example 17, further comprising a second epoxy layer on the second surface, wherein the second epoxy layer covers edge regions of the second surface and leaves a region of the second metallization layer exposed, or the second epoxy layer entirely covers the second metallization layer.

The semiconductor package of Example 17 or Example 18, further comprising a second device, wherein the first conductive connection forms part of a conductive redistribution structure that electrically couples the first transistor device with the second device to form a circuit, wherein the conductive redistribution structure further comprises a conductive layer that is arranged on the conductive connection and on at least one of the second surface of the first transistor device and the second device.

The semiconductor package of claim19, wherein the second electronic device is a transistor device and the circuit is a half-bridge circuit, or the second electronic device is a driver device, or the second electronic device is an inductor or a capacitor or a resistor.

A method, comprising: forming at least one trench in separation regions of a first surface of a semiconductor wafer; forming at least one trench in non-device regions of the first surface of the semiconductor wafer, wherein the separation regions are arranged between component positions of the semiconductor wafer, the component positions comprising at least two electronic devices for forming a circuit, a non-device region arranged between a first device region comprising a first electronic device and a second device region comprising a second electronic device, and a first metallization structure arranged on the first surface in the first device region and in the second device region; applying a first epoxy layer to the first surface of a semiconductor wafer such that the trenches, edge regions of the component positions, edge regions of the first device regions and edge regions of the second device regions are covered with the first epoxy layer; removing portions of a second surface of the semiconductor wafer, the second surface opposing the first surface, revealing portions of the first epoxy layer in the separation regions and in the non-device regions and producing a worked second surface; applying a second metallization layer to the worked second surface and operably coupling the first electronic device to the second electronic device to form the circuit; and inserting a separation line through the first epoxy layer in the separation regions to form a plurality of separate semiconductor modules comprising the circuit.

The method of Example 21, further comprising: inserting a via into the second device region; inserting conductive material into the via; and electrically coupling the conductive material to the first electronic device and to the second electronic device.

The method of Example 22, wherein the via is inserted into the first surface of the semiconductor wafer and afterwards, the first metallization structure and the first epoxy layer is applied to the first surface and portions of the second surface of the semiconductor wafer are removed, or the via is inserted into the worked second surface of the semiconductor wafer.

The method of Example 21, further comprising: inserting conductive material into the trench formed in the non-device region; and electrically coupling the conductive material to the first electronic device and to the second electronic device.

The method of Example 24, wherein the first epoxy layer is inserted into the trench formed in the non-device region, a via is formed in the first epoxy layer in the non-device regions such that side faces of the first device region and of the second device region bounding the via are covered with the first epoxy layer and the conductive material is applied to the first epoxy layer in the via, the conductive material extending from the first metallization structure in the second device region to the worked second surface.

The method of Example 21, wherein a conductive via from the first surface of the semiconductor wafer to the worked second surface of the semiconductor wafer is formed by a conductive portion of the first device region or of the second device region, the conductive portion extending from the first surface of the semiconductor wafer to the worked second surface of the semiconductor wafer.

The method of any one of Examples 21 to 26, wherein the second metallization layer is applied to the conductive material within the via to operably couple the first electronic device to the second electronic device.

The method of any one of Examples 21 to 27, wherein the second metallization layer is applied such that it extends from the first device region over the non-device region to the second device region.

The method of any one of Examples 21 to 28, wherein the separation line has a width that is less than the width of the trench in the separation region such that at least portions of side faces of the plurality of separate semiconductor modules comprise a portion of the first epoxy layer.

The method of any one of Examples 21 to 29, wherein the first epoxy layer further covers edge regions of the first metallization structure.

The method of any one of Examples 21 to 30, further comprising applying a second epoxy layer to the worked second surface that covers at least the first epoxy layer arranged in the separation regions.

The method of Example 21, wherein the second epoxy layer covers the second metallization layer arranged on the first device region and exposes the second metallization layer arranged on the second device region.

A module, comprising: a first electronic device in a first device region; a second electronic device in a second device region, wherein the first electronic device is operably coupled to the second electronic device to form a circuit; a first major surface comprising at least one contact pad; a second major surface comprising at least one contact pad, the second major surface opposing the first major surface; a first epoxy layer arranged on the first major surface that leaves at least portions of the first contact pad exposed, wherein side faces of the first electronic device and of the second electronic device are embedded in, and in direct contact with, the first epoxy layer; and a conductive redistribution structure that electrically couples the first electronic device with the second electronic device to form the circuit, wherein the conductive redistribution structure comprises a conductive via extending from the first major surface to the second major surface and a conductive layer that is arranged on the conductive via and on at least one of the first device region and the second device region.

The module of Example 33, wherein the first electronic device is a transistor device, the second electronic device is a transistor device and the circuit is a half-bridge circuit, or the first electronic device is a transistor device and the second electronic device is a driver device, or the first electronic device is a transistor device and the second electronic device is an inductor or a capacitor or a resistor.

An electronic component, comprising: the module of Example 33 or Example 34; a plurality of leads, wherein the first contact pad is coupled to a first lead of the plurality of leads and the second contact pad is coupled to a second lead of the plurality of leads; and a plastic housing composition, wherein the plastic housing composition covers the first epoxy layer, the second epoxy layer and portions of the plurality of leads.