Laser diode driver circuit

A laser diode drive circuit includes a laser diode (LD), a modulation-current differential drive circuit, a bias-current differential drive circuit, a first inductance connected between an anode of the LD and a positive power source, a second inductance connected between a cathode of the LD and a negative-phase output terminal of the bias-current differential drive circuit, a first resistor connected to a connection point of the anode of the LD and the first inductance and connected to a negative-phase output terminal of the modulation-current differential drive circuit, and a second resistor connected to a connection point of the cathode of the LD and the second inductance and connected to a positive-phase output terminal of the modulation-current differential drive circuit, and a positive-phase output terminal of the bias-current differential drive circuit is connected to the connection point.

FIELD

The present invention relates to a laser diode driver circuit that is provided in a transmission unit of a subscriber terminal apparatus (ONU: Optical Network Unit) of a PON (Passive Optical Network) system that is one of access optical communication systems.

BACKGROUND

A point-to-multipoint access optical communication system referred to as “PON system” has been widely used as a method for implementing a public line network that employs optical fibers.

The PON system is constituted by an OLT (Optical Line Terminal) as a station-side apparatus and a plurality of ONUs that serve as a plurality of subscriber terminal apparatuses connected to the OLT via an optical star coupler. Because a number of ONUs can share the OLT and most part of the optical fibers configuring transmission paths, reduction of the operation cost can be expected, and because the optical star coupler, which is a passive component, does not need a power supply and can be easily installed outside, there is another advantage of high reliability. Accordingly, the PON system has been recently actively introduced as a key technology for implementing broadband networks.

For example, in a GE-PON (Gigabit Ethernet®-Passive Optical Network) having a transmission speed of 1.25 Gbit/s, which is standardized compliant with the IEEE802.3ah, a downstream from an OLT to ONUs employs a broadcast communication system using an optical wavelength band of 1.49 micrometers and each of the ONUs retrieves only the data addressed to itself in an allocated time slot. On the other hand, an upstream from each of the ONUs to the OLT uses an optical wavelength band of 1.31 micrometers and employs a time-division multiplex communication system for controlling transmission timing such that data from the ONUs do not collide with each other.

In the upstream communication of the PON system described above, an optical transmission unit in each of the ONUs generates an upstream burst optical data signal according to each transmission timing. In order to generate the burst optical data signal at a high speed, differential driving of a semiconductor laser diode (LD) is effective. For example, Patent Literature 1 proposes a technique related to differential driving of an LD.

CITATION LIST

Patent Literature

SUMMARY

Technical Problem

However, in the technique disclosed in Patent Literature 1 mentioned above, when a bias current is supplied to an LD in a burst manner, a reverse voltage is generated due to an inductance connected between a positive power source and the anode of the LD for implementing the differential driving of the LD. This decreases an output potential of a bias-current drive circuit to close to a negative power source, generating a time for which an output transistor in the bias-current drive circuit is switched OFF. Due to this operation, because a predetermined time is required from the time at which the bias current is started to flow until a set current is supplied, there has been a problem that a burst emission is delayed and the transmission efficiency is degraded.

The present invention has been achieved in view of the above problems, and an object of the present invention is to provide a laser diode driver circuit (hereinafter, “LD drive circuit”) that can improve the transmission efficiency of a PON system.

Solution to Problem

To solve the problems and achieve the object according to an aspect of the present invention, a laser diode driver circuit includes: a laser diode that converts a current signal into an optical signal; a bias-current drive circuit that supplies a bias current to the laser diode; a modulation-current drive circuit that supplies a modulation current to the laser diode; a first inductance connected between the anode of the laser diode and a positive power source; a second inductance connected between the cathode of the laser diode and a negative-phase output terminal of the bias-current drive circuit; a first resistor with one end connected to a connection point of the anode of the laser diode and the first inductance and the other end connected to a negative-phase output terminal of the modulation-current drive circuit; and a second resistor including one end connected to a connection point of the cathode of the laser diode and the second inductance and the other end connected to a positive-phase output terminal of the modulation-current drive circuit. A positive-phase output terminal of the bias-current drive circuit is connected to the connection point of the anode of the laser diode and the first inductance.

Advantageous Effects of Invention

According to the present invention, because a positive-phase output terminal of a bias-current drive circuit is connected to a connection point between the anode of an LD and a first inductance, the transmission efficiency of a PON system can be improved.

DESCRIPTION OF EMBODIMENTS

Exemplary embodiments of an LD drive circuit according to the present invention will be explained below in detail with reference to the accompanying drawings. The present invention is not limited to the embodiments.

First Embodiment

FIG. 1depicts a configuration of a general PON system. The PON system includes an OLT as s station-side apparatus and a plurality of subscriber terminal apparatuses ONU1to ONUn connected to the OLT via an optical star coupler. In the PON system, because an access method in an upstream channel from the ONU1to ONUn to the OLT is defined as a time-division multiplex method, packets1-1to1-nare intermittently transmitted from the ONU1to ONUn to the OLT. Timings at which the ONU1to ONUn respectively transmit the packets1-1to1-nare adjusted such that the packets1-1to1-nare not overlapped in an optical receiver (not shown) of the OLT. Furthermore, because each of the distances from the OLT to the ONU1to ONUn is different from each other, as shown in the uppermost part ofFIG. 1, optical intensities of the packets1-1to1-nreceived by the optical receiver of the OLT are different from each other. An LD drive circuit according to a first embodiment is applied to the ONU1to ONUn, and the configuration and operations thereof are explained below in detail.

FIG. 2depicts a configuration of the LD drive circuit according to the first embodiment of the present invention, andFIG. 3depicts a reference example of a modulation-current differential drive circuit (hereinafter, “modulation-current drive circuit”)40and a bias-current differential drive circuit (hereinafter, “bias-current drive circuit”)41shown inFIG. 2.

InFIG. 2, the LD drive circuit according to the first embodiment includes, as a main configuration, an LD1that converts a current signal into an optical signal, the bias-current drive circuit41that supplies a burst-like bias current to the LD1, the modulation-current drive circuit40that supplies a modulation current to the LD1by superimposing the modulation current on the bias current, a first inductance2connected between the anode side of the LD1and a positive power source30, a second inductance3connected between the cathode side of the LD1and a negative-phase output terminal24bof the bias-current drive circuit41, a first resistor4with one end connected to a connection point N1between the anode of the LD1and the first inductance2(hereinafter, simply “connection point N1”) and the other end connected to a negative-phase output terminal21bof the modulation-current drive circuit40, and a second resistor5with one end connected to a connection point between the cathode of the LD1and the second inductance3and the other end connected to a positive-phase output terminal21aof the modulation-current drive circuit40.

Furthermore, in the LD drive circuit according to the first embodiment, a positive-phase output terminal24aof the bias-current drive circuit41is connected to the connection point N1.

The modulation-current drive circuit40includes the positive-phase output terminal21aand the negative-phase output terminal21b, and further includes modulation-voltage-signal input terminals20aand20band a modulation-current setting terminal22. The positive-phase output terminal21aand the negative-phase output terminal21bfunction as differential-current-signal output terminals of the modulation-current drive circuit40. Two complementary input signals (burst signals) are respectively input to the modulation-voltage-signal input terminals20aand20b.

The bias-current drive circuit41includes the positive-phase output terminal24aand the negative-phase output terminal24b, and further includes differential-voltage-signal input terminals23aand23band a bias-current setting terminal25. Two complementary input signals are respectively input to the differential-voltage-signal input terminals23aand23b. The positive-phase output terminal24aand the negative-phase output terminal24bfunction as differential-current-signal output terminals of the bias-current drive circuit41.

The first resistor4and the second resistor5operate as damping resistors for relaxing impedance mismatch between the impedance of the LD1and the output impedance of the modulation-current drive circuit40. The first inductance2becomes high impedance when the modulation current is output from the modulation-current drive circuit40, thus isolating the positive power source30in a high-frequency component isolating manner to drive the LD1. The second inductance3is configured to increase an output impedance of the bias-current drive circuit41to prevent the modulation current from the modulation-current drive circuit40from flowing into the bias-current drive circuit41.

As shown inFIG. 3, the modulation-current drive circuit40includes a first MOS transistor6, a second MOS transistor7, and a current source8that is provided between a connection point of the source of the first MOS transistor6and the source of the second MOS transistor7and a negative power source33and supplies a current determined by a set value from the modulation-current setting terminal22.

The first MOS transistor6and the second MOS transistor7constitute a differential circuit driven by the two complementary input signals. The modulation-voltage-signal input terminal20ais connected to the gate of the first MOS transistor6, and the negative-phase output terminal21bis connected to the drain of the first MOS transistor6. The modulation-voltage-signal input terminal20bis connected to the gate of the second MOS transistor7, and the positive-phase output terminal21ais connected to the drain of the second MOS transistor7. In this manner, the modulation-current drive circuit40is configured such that the drains of the first MOS transistor6and the second MOS transistor7respectively output a positive-phase output and a negative-phase output of the modulation-current drive circuit40.

The bias-current drive circuit41includes a third MOS transistor9, a fourth MOS transistor10, and a current source11that is provided between a connection point of the source of the third MOS transistor9and the source of the fourth MOS transistor10and the negative power source33and supplies a current determined by a set value from the bias-current setting terminal25.

The third MOS transistor9and the fourth MOS transistor10constitute a differential circuit driven by the two complementary input signals. The differential-voltage-signal input terminal23ais connected to the gate of the third MOS transistor9, and the negative-phase output terminal24bis connected to the drain of the third MOS transistor9. The differential-voltage-signal input terminal23bis connected to the gate of the fourth MOS transistor10, and the positive-phase output terminal24ais connected to the drain of the fourth MOS transistor10. In this manner, the bias-current drive circuit41is configured such that the drains of the third MOS transistor9and the fourth MOS transistor10respectively output a positive-phase output and a negative-phase output of the bias-current drive circuit41. The reference sign “Vds50” shown inFIG. 3indicates a drain-source voltage of the third MOS transistor9included in the bias-current drive circuit41according to the first embodiment.

Operations of the LD drive circuit according to the first embodiment of the present invention are explained below.

FIG. 4is a conceptual diagram of a waveform of an LD drive current input to the LD1and a waveform of output light from the LD1, andFIG. 5depicts a relationship between a modulation signal, a bias signal, an LD drive current, and LD output light.

InFIG. 4, the horizontal axis represents an LD drive current (ILD), the vertical axis represents an optical power (Po) of the LD output light, and the curve line represents a characteristic curve of the LD1. A bias current indicates a current output from the positive-phase output terminal24aor the negative-phase output terminal24bof the bias-current drive circuit41, and a modulation current indicates a current output from the positive-phase output terminal21aor the negative-phase output terminal21bof the modulation-current drive circuit40. The waveform of the LD drive current represents a waveform of the current in which the bias current is superimposed on the modulation current.

Because the modulation current in response to a baseband signal (burst signal) is supplied to the LD1by the modulation-current drive circuit40together with the bias current, the LD output light as shown inFIG. 4is output from the LD1in response to the both currents. A bias current with which the modulation current is not distorted is required for the emission of the LD1.

The modulation signal shown inFIG. 5is a signal input to the modulation-voltage-signal input terminal20aor the modulation-voltage-signal input terminal20b, which is converted into the modulation current shown inFIG. 4by the first MOS transistor6and the second MOS transistor7that constitute a differential pair. The bias signal shown inFIG. 5is a signal input to the differential-voltage-signal input terminal23aor the differential-voltage-signal input terminal23bof the bias-current drive circuit41, which is converted into the bias current shown inFIG. 4by the third MOS transistor9and the fourth MOS transistor10that constitute a differential pair.

In the ONU of the PON system, because the light needs to be emitted in a burst manner, the LD drive current (the modulation current and the bias current) shown inFIG. 5is applied to the LD1in a burst manner, by which the LD output light (burst light) as shown inFIG. 5is generated from the LD1.

In the LD drive circuit according to the present embodiment, as shown inFIG. 3, a current flowing through the first inductance2is not changed by connecting the positive-phase output terminal24aof the bias-current drive circuit41to the connection point N1, and hence a reverse voltage caused by the first inductance2is suppressed. Furthermore, a back electromotive force caused by the second inductance3is reduced by setting values of the first inductance2and the second inductance3to satisfy a relationship of the first inductance2>>the second inductance3.

The effect of the LD drive circuit according to the first embodiment is explained below based on a comparison with a conventional technique.

FIG. 6depicts a configuration of a conventional LD drive circuit,FIG. 7depicts a simulation result obtained by using the LD drive circuit shown inFIG. 6, andFIG. 8depicts a stabilization time and transmission efficiency of the LD output light by the LD drive circuit shown inFIG. 6.

The LD drive circuit shown inFIG. 6is a circuit described in Patent Literature 1 mentioned above. Parts of the LD circuit that are identical to those of the LD drive circuit according to the first embodiment are denoted by same reference signs, explanations thereof will be omitted, and only different features are explained below.

The conventional drive circuit shown inFIG. 6is different from the LD drive circuit according to the first embodiment in the following points. That is, the conventional drive circuit shown inFIG. 6includes a fifth resistor12having one end connected to the first MOS transistor6and the other end connected to a positive power source31and a sixth resistor13having one end connected to the second MOS transistor7and the other end connected to the positive power source31. Furthermore, in the conventional LD drive circuit shown inFIG. 6, the drain of the fourth MOS transistor10is connected to a positive power source32. The reference sign “Vds1” shown inFIG. 6indicates a drain-source voltage of the third MOS transistor9included in a conventional bias-current drive circuit41.

A waveform of an input voltage (bias signal) to the differential-voltage-signal input terminal23a(positive-phase input terminal) shown inFIG. 6is shown in the uppermost chart ofFIG. 7. An output current (bias current) output from the negative-phase output terminal24bshown inFIG. 6is shown in the middle chart ofFIG. 7, and a waveform of the Vds1shown inFIG. 6is shown in the lowermost chart ofFIG. 7.

When the input voltage shown in the uppermost chart ofFIG. 7is input to the differential-voltage-signal input terminal23a, the output current as shown in the middle chart ofFIG. 7appears at the negative-phase output terminal24b. The reason why a rise of the waveform of the output current shown in the middle chart ofFIG. 7is lagged is because, as shown in the lowermost chart ofFIG. 7, the value of the Vds1is greatly inversed to Vds=3.8 volts due to the back electromotive force from the first inductance2and the third MOS transistor9cannot operate during the time for which the Vds1is inversed. The time for which the Vds1is inversed is a time until the third MOS transistor9that is switched OFF by the back electromotive force becomes switched ON.

As explained above with referenced toFIGS. 4 and 5, because the bias current to the LD1is converted into the light waveform, a time of about 110 nanoseconds is required for the output light of the LD1to be stabilized, as the waveform shown in the middle chart ofFIG. 7.

FIG. 8depicts a relationship between a time for which the Vds1is inversed and the transmission efficiency. The horizontal axis represents an On/Off time of the LD1, and the vertical axis represents the transmission efficiency. The transmission efficiency when the time for which the Vds1is inversed is 110 nanoseconds is 96.7%. That is, it is found that about 3.3% is wasted. Therefore, a reduction of a rise time of the LD1is effective in improving the transmission efficiency.

FIG. 9depicts a simulation result obtained by using the LD drive circuit according to the first embodiment of the present invention. A waveform of the input voltage to the differential-voltage-signal input terminal23a(positive-phase input terminal) shown inFIGS. 2 and 3is shown in the uppermost chart ofFIG. 9, a waveform of the output current from the negative-phase output terminal24bshown inFIGS. 2 and 3is shown in the middle chart ofFIG. 9, and a waveform of the Vds50is shown in the lowermost chart ofFIG. 9.

With the LD drive circuit according to the first embodiment, it is found that a convergence time of the waveform of the output current shown in the middle chart ofFIG. 9is about 8 nanoseconds, which is a value sufficiently shorter than the rise time shown inFIG. 7. As explained above with reference toFIGS. 4 and 5, because the bias current to the LD1is converted into the light waveform, the time required for the output light of the LD1to be stabilized is reduced from about 110 nanoseconds to about 8 nanoseconds, improving the transmission efficiency accordingly. Furthermore, although the rise time of the waveform shown in the uppermost chart ofFIG. 9is shorter than the rise time of the waveform shown in the uppermost chart ofFIG. 7, even when such an input voltage is input, the rise time of the LD1can be reduced with the configuration according to the first embodiment as compared to a conventional technique.

As described above, the LD drive circuit according to the first embodiment includes the LD1, the bias-current drive circuit41, the modulation-current drive circuit40, the first inductance2connected between the anode side of the LD1and the positive power source30, the second inductance3connected between the cathode side of the LD1and the negative-phase output terminal24bof the bias-current drive circuit41, the first resistor4with one end connected to the connection point N1and the other end connected to the negative-phase output terminal21bof the modulation-current drive circuit40, and the second resistor5with one end connected to the connection point between the cathode of the LD1and the second inductance3and the other end connected to the positive-phase output terminal21aof the modulation-current drive circuit40, and the positive-phase output terminal24aof the bias-current drive circuit41is connected to the connection point N1. Therefore, the inversion time of the Vds50caused by the reverse voltage of the first inductance2, that is, the time required to the output light of the LD1to be stabilized, is reduced as compared to the conventional one, and as a result, a highly-efficient transmission can be achieved in the PON system.

Second Embodiment

FIG. 10depicts a configuration of an LD drive circuit according to a second embodiment of the present invention, andFIG. 11depicts a reference example of the modulation-current drive circuit40and the bias-current differential drive circuit41shown inFIG. 10. The LD drive circuit shown inFIGS. 10 and 11includes an impedance element17connected between the positive-phase output terminal24aof the bias-current drive circuit41and the connection point N1, and having an impedance characteristic in a broad frequency range from a low frequency to a high frequency, in addition to the constituent elements having same reference signs and identical functions as those in the LD drive circuit according to the first embodiment. That is, the LD drive circuit according to the second embodiment is configured to improve the high frequency characteristic, while the LD drive circuit according to the first embodiment is configured such that the positive-phase output terminal24aof the bias-current drive circuit41is electrically connected to the connection point N1.

More specifically, similarly to the second inductance3, the impedance element17is configured to increase the output impedance of the bias-current drive circuit41to suppress the flow of the modulation current from the modulation-current drive circuit40into the bias-current drive circuit41. In this manner, by arranging the second inductance3and the impedance element17, the high frequency characteristic is even more improved than the LD drive circuit according to the first embodiment The operation of the LD drive circuit according to the second embodiment is explained below. The bias signal input to the differential-voltage-signal input terminals23aand23bis taken in the bias-current drive circuit41as the bias current, and the bias current from the bias-current drive circuit41is supplied to the LD1via the second inductance3and the impedance element17.

As described above, the LD drive circuit according to the second embodiment includes the LD1, the bias-current drive circuit41, the modulation-current drive circuit40, the first inductance2connected between the anode side of the LD1and the positive power source30, the second inductance3connected between the cathode side of the LD1and the negative-phase output terminal24bof the bias-current drive circuit41, the first resistor4with one end connected to the connection point N1and the other end connected to the negative-phase output terminal21bof the modulation-current drive circuit40, the second resistor5with one end connected to the connection point between the cathode of the LD1and the second inductance3and the other end connected to the positive-phase output terminal21aof the modulation-current drive circuit40, and the impedance element17connected between the connection point N1and the positive-phase output terminal24aof the bias-current drive circuit41. Therefore, the LD drive circuit according to the second embodiment has the effect of further improving the high frequency characteristic, in addition to the effects of the LD drive circuit according to the first embodiment.

Third Embodiment

FIG. 12is a configuration example of an LD drive circuit according to a third embodiment of the present invention, andFIG. 13is another example of the LD drive circuit according to the third embodiment of the present invention. With the recent advancement in the downsizing of the semiconductor process the withstand voltage of the transistor has been decreased in recent years, and when the output potential of the bias-current drive circuit41is decreased from the positive power source30to close to the negative power source33, the output potential may exceed the withstand voltage of the transistor, causing a problem that the reliability in the withstand voltage of the transistor can be hardly secured. The LD drive circuit according to the third embodiment is configured to solve such a problem, in addition to having effects as those of the first embodiment. Parts of the LD circuit that are identical to those of the LD drive circuit according to the first embodiment are denoted by same reference signs, explanations thereof will be omitted, and only different features are explained below.

The LD drive circuit shown inFIG. 12is explained first. The LD drive circuit shown inFIG. 12includes a tr/tf control circuit14that controls a tr/tf (rise/fall) characteristic of the bias current, as well as the constituent elements having same reference signs and identical functions as those in the LD drive circuit according to the first embodiment. More specifically, in the bias-current drive circuit41shown inFIG. 12, the tr/tf control circuit14is connected between the positive-phase output terminal24aand the negative-phase output terminal24bof the bias-current drive circuit41and the drains of the third MOS transistor9and the fourth MOS transistor10.

The operation of the LD drive circuit shown inFIG. 12is explained below. The bias signal input to the differential-voltage-signal input terminals23aand23bis taken in the tr/tf control circuit14as the bias current, and the tr/tf characteristic of the bias current is relaxed by the tr/tf control circuit14. The bias current from the third MOS transistor9is supplied to the LD1via the second inductance3. In this manner, the LD drive circuit shown inFIG. 12is configured such that the magnitude of the reverse voltage caused by the first inductance2is reduced by relaxing the rise and the fall of the bias current by using the tr/tf control circuit14.

The LD drive circuit shown inFIG. 13is explained next. The LD drive circuit shown inFIG. 13includes the tr/tf control circuit14that controls a tr/tf characteristic of the input voltage (bias signal) and a third resistor15and a fourth resistor16for broadening a linear operating area of the differential circuit, in addition to the constituent elements having like reference signs and identical functions as those in the LD drive circuit according to the first embodiment. More specifically, in the bias-current drive circuit41shown inFIG. 13, the tr/tf control circuit14is connected between the differential-voltage-signal input terminals23aand23bof the bias-current drive circuit41and the gates of the third MOS transistor9and the fourth MOS transistor10, and the third resistor15and the fourth resistor16are connected in series to form a series resistance with one end connected to the source of the third MOS transistor9and the other end connected to the source of the fourth MOS transistor10. Furthermore, the current source11that supplies the current determined by the set value from the bias-current setting terminal25is provided between a connection point of the series resistance and the negative power source33.

The operation of the LD drive circuit shown inFIG. 13is explained below. The bias signal input to the differential-voltage-signal input terminals23aand23bis taken in the tr/tf control circuit14, the tr/tf characteristic of the bias signal is relaxed by the tr/tf control circuit14, and then the bias signal is input to the third MOS transistor9and the fourth MOS transistor10. Further, the linear operating area of the differential circuit is broadened due to the third resistor15and the fourth resistor16, thus the input/output characteristics of the third MOS transistor9and the fourth MOS transistor10are relieved. The bias current from the third MOS transistor9is supplied to the LD1via the second inductance3. In this manner, the LD drive circuit shown inFIG. 13is configured such that the magnitude of the back electromotive force caused by the first inductance2is reduced by relieving the rise and the fall of the bias signal by using the tr/tf control circuit14, the third resistor15, and the fourth resistor16.

FIG. 14depicts a simulation result obtained by using the LD drive circuit according to the third embodiment of the present invention. A waveform of the input voltage to the differential-voltage-signal input terminal23a(positive-phase input terminal) shown inFIGS. 12 and 11is shown in the uppermost chart ofFIG. 14, a waveform of the output current from the negative-phase output terminal24bshown inFIGS. 12 and 11is shown in the middle chart ofFIG. 14, and a waveform of the Vds50of the third MOS transistor9is shown in the lowermost chart ofFIG. 14.

With the LD drive circuit according to the third embodiment, it is found that a convergence time of the waveform of the output current shown in the middle chart ofFIG. 14is about 8 nanoseconds, similarly to the LD drive circuit according to the first embodiment, and the value of the Vds50shown in the lowermost chart ofFIG. 14is improved from 3.8 volts to 3.3 volts. Although the recent advancement in the downsizing of the semiconductor process has been remarkable, because the downsizing of the semiconductor process and the decrease of the withstand voltage have a tradeoff relationship, the reduction of the value of the Vds50to a value lower than 3.8 volts can improve the reliability on the withstand voltage. In this manner, the third embodiment is capable of not only achieving the LD drive circuit with which the reliability of the withstand voltage of the transistor can be easily secured but also increasing the lifetime of the transistor.

Fourth embodiment

FIG. 15is a configuration example of an LD drive circuit according to a fourth embodiment of the present invention, andFIG. 16is another configuration example of the LD drive circuit according to the fourth embodiment of the present invention. The LD drive circuits shown inFIGS. 15 and 16include the impedance element17connected between the positive-phase output terminal24aof the bias-current drive circuit41and the connection point N1, as well as the constituent elements having same reference signs and identical functions as those in the LD drive circuit according to the third embodiment. That is, the LD drive circuit according to the fourth embodiment is configured to improve the high frequency characteristic, while the LD drive circuit according to the third embodiment is configured such that the positive-phase output terminal24aof the bias-current drive circuit41is electrically connected to the connection point N1.

More specifically, similarly to the second inductance3, the impedance element17is configured to increase the output impedance of the bias-current drive circuit41to suppress the flow of the modulation current from the modulation-current drive circuit40into the bias-current drive circuit41. In this manner, by arranging the second inductance3and the impedance element17, the high frequency characteristic is even more improved than the LD drive circuit according to the third embodiment. The operation of the LD drive circuit according to the fourth embodiment is explained below. The bias signal input to the differential-voltage-signal input terminals23aand23bis taken in the bias-current drive circuit41as the bias current, and the bias current from the bias-current drive circuit41is supplied to the LD1via the second inductance3and the impedance element17.

As explained above, the LD drive circuit according to the fourth embodiment includes the LD1, the bias-current drive circuit41similarly to the bias-current drive circuit41according to the third embodiment, the modulation-current drive circuit40, the first inductance2connected between the anode side of the LD1and the positive power source30, the second inductance3connected between the cathode side of the LD1and the negative-phase output terminal24bof the bias-current drive circuit41, the first resistor4with one end connected to the connection point N1and the other end connected to the negative-phase output terminal21bof the modulation-current drive circuit40, the second resistor5with one end connected to the connection point between the cathode of the LD1and the second inductance3and the other end connected to the positive-phase output terminal21aof the modulation-current drive circuit40, and the impedance element17connected between the connection point N1and the positive-phase output terminal24aof the bias-current drive circuit41. Therefore, the LD drive circuit according to the fourth embodiment has the effect of further improving the high frequency characteristic, in addition to the effects of the LD drive circuit according to the third embodiment.

The LD drive circuit according to the first to fourth embodiments may be configured as explained below. Parts of the LD circuit explained below that are identical to those of the LD drive circuit according to the first to fourth embodiments are denoted by same reference signs, explanations thereof will be omitted, and only different features are explained below.

FIG. 17is another configuration example of the modulation-current drive circuit40described in the first and third embodiments of the present invention,FIG. 18is another configuration example of the modulation-current drive circuit40described in the second and fourth embodiments of the present invention. The modulation-current drive circuits40shown inFIGS. 17 and 18include the first MOS transistor6, the second MOS transistor7, the current source8, the fifth resistor12with one end connected to the first MOS transistor6and the other end connected to the positive power source30, and the sixth resistor13with one end connected to the second MOS transistor7and the other end connected to the positive power source30. The fifth resistor12and the sixth resistor13function as bias resistors.

Even with the arrangement of the fifth resistor12and the sixth resistor13between the drains of the first MOS transistor6and the second MOS transistor7and the power source30in the above manner, operations and effects are identical to those of the LD drive circuits according to the first to fourth embodiments.

The same power source as the positive power source30connected to the other end of the first inductance2is supplied to the modulation-current drive circuits40shown inFIGS. 17 and 18. It is assumed that the positive power source30of the modulation-current drive circuit40is connected to the positive power source30for the first inductance2with a low impedance. By commonly connecting the positive power source30supplied to the modulation-current drive circuit40and the positive power source30connected to the first inductance2in the above manner, the high frequency characteristic can be improved.

The transistor that is applicable to the LD drive circuits according to the first to fourth embodiments of the present invention is not limited to the MOS transistor, but a bipolar transistor can be used instead. In this case, the source described in the first to fourth embodiments can be read as an emitter, and similarly, the gate can be read as a base, and the drain can be read as a collector.

FIG. 19is an example of a case where the impedance element17described in the second and fourth embodiments is configured as an inductance17a,FIG. 20is an example of a case where the impedance element17described in the second and fourth embodiments is configured as a resistor17b, andFIG. 21is an example of a case where the impedance element17described in the second and fourth embodiments is configured as a series circuit17cof an inductance and a resistor. All the inductance17a, the resistor17b, and the series circuit17chave an impedance characteristic in a broad frequency range from a low frequency to a high frequency. Therefore, by configuring the impedance element17with any one of the inductance17a, the resistor17b, and the series circuit17c, the output impedance of the bias-current drive circuit41can be increased. As a result, the modulation current from the modulation-current drive circuit40is suppressed from flowing into the bias-current drive circuit41, and the high frequency characteristic is even more improved.

The LD drive circuits according to the first to fourth embodiments are only examples of the contents of the present invention and can be combined with other well-known techniques. It is needless to mention that the present invention can be configured while modifying it without departing from the scope of the invention, such as omitting a part the configuration.

INDUSTRIAL APPLICABILITY

As described above, the present invention is applicable to an ONU of a PON system, and particularly useful as an invention that can improve the transmission efficiency of the PON system.

REFERENCE SIGNS LIST

14tr/tf control circuit

20a,20bmodulation-voltage-signal input terminal

21a,24apositive-phase output terminal

21b,24bnegative-phase output terminal

22modulation-current setting terminal

23a,23bdifferential-voltage-signal input terminal

25differential-voltage-signal input terminal

30,31,32positive power source

33negative power source

1-1to1-npacket from ONU

N1connection point of anode of LD and first inductance