VIRTUAL POWER SUPPLY THROUGH WAFER BACKSIDE

Embodiments of the present invention are directed to processing methods and resulting structures for providing a virtual power supply through a wafer backside. In a non-limiting embodiment of the invention, a front end of line structure having a gate is formed and a back end of line structure is formed on a first surface of the front end of line structure. A backside power delivery network is formed on a second surface of the front end of line structure opposite the first surface. Source and drain regions on a first side of the gate are connected to the backside power delivery network and source and drain regions on a second side of the gate are connected to the back end of line structure.

BACKGROUND

The present invention generally relates to fabrication methods and resulting structures for semiconductor devices, and more specifically, to processing methods and resulting structures for providing a virtual power supply through a wafer backside.

The development of an integrated circuit (i.e., chip) involves several stages from design through fabrication. Many aspects of the development are performed iteratively to ensure that the chip ultimately manufactured meets all design requirements. Defining the chip architecture is one of the earliest phases of integrated circuit development. The power (e.g., power requirement), performance (e.g., timing), and area (i.e., space needed) for the resulting chip, collectively PPA, is one of the primary metrics by which integrated circuits are evaluated. PPA is largely a consequence of the chip architecture.

Semiconductor fabrication continues to evolve towards improving one or more aspects of PPA. For example, a higher number of active devices (mainly transistors) of ever decreasing device dimensions are placed on a given surface of semiconductor material. Density scaling has put a strain on the design and fabrication of the interconnects between the front end of line of the integrated circuit, consisting mainly of the active devices, and the contact terminals of the integrated circuit. In many chip architectures, all of these interconnects are incorporated in the back end of line (BEOL) structure of the integrated circuit, which includes a stack of metallization layers and vertical via connections built on top of the front end of line (FEOL) structure.

A key component of the BEOL structure is the power delivery network (PDN). The PDN of an integrated circuit is defined by the conductors and vias connected to the power supply (VDD) and ground (VSS) terminals of the chip. The PDN is responsible for delivering power to the individual devices in the front end. The integration of the PDN in the BEOL has become particularly challenging as device densities continue to scale. Backside power delivery is one known solution to this problem, and involves moving some (or most, or all) layers of the PDN from the front side of the integrated circuit to the back side. In a backside-style architecture, the repositioned layers are not formed on top of the FEOL, but are instead formed on the opposite side of the chip (i.e., on the backside of the semiconductor substrate onto which the active devices have been built).

SUMMARY

Embodiments of the invention are directed to a method for providing a virtual power supply through a wafer backside. A non-limiting example of the method includes forming a front end of line structure having a gate and forming a back end of line structure on a first surface of the front end of line structure. A backside power delivery network is formed on a second surface of the front end of line structure opposite the first surface. Source and drain regions on a first side of the gate are connected to the backside power delivery network and source and drain regions on a second side of the gate are connected to the back end of line structure.

Embodiments of the invention are directed to a semiconductor structure. A non-limiting example of the semiconductor structure includes a front end of line structure having a gate and a back end of line structure on a first surface of the front end of line structure. A backside power delivery network is positioned on a second surface of the front end of line structure opposite the first surface. Source and drain regions on a first side of the gate are connected to the backside power delivery network and source and drain regions on a second side of the gate are connected to the back end of line structure.

Embodiments of the invention are directed to a semiconductor structure. A non-limiting example of the semiconductor structure includes a front end of line structure having a gate and a back end of line structure on a first surface of the front end of line structure. A backside power delivery network is positioned on a second surface of the front end of line structure opposite the first surface. Source and drain regions on a first side of the gate are connected to a power supply in the backside power delivery network and source and drain regions on a second side of the gate are connected to a virtual power supply in the backside power delivery network.

The diagrams depicted herein are illustrative. There can be many variations to the diagram or the operations described therein without departing from the spirit of the invention. For instance, the actions can be performed in a differing order or actions can be added, deleted or modified.

In the accompanying figures and following detailed description of the described embodiments of the invention, the various elements illustrated in the figures are provided with two or three-digit reference numbers. With minor exceptions, the leftmost digit(s) of each reference number correspond to the figure in which its element is first illustrated.

DETAILED DESCRIPTION

It is understood in advance that although example embodiments of the invention are described in connection with a particular transistor architecture, embodiments of the invention are not limited to the particular transistor architectures or materials described in this specification. Rather, embodiments of the present invention are capable of being implemented in conjunction with any other type of transistor architecture or materials now known or later developed.

Turning now to an overview of technologies that are more specifically relevant to aspects of the present invention, ICs are fabricated in a series of stages, including a front-end-of-line (FEOL) stage, a middle-of-line (MOL) stage, and a back-end-of-line (BEOL) stage. The process flows for fabricating modern ICs are often identified based on whether the process flows fall in the FEOL stage, the MOL stage, or the BEOL stage. Generally, the FEOL stage is where device elements (e.g., transistors, capacitors, resistors, etc.) are patterned in the semiconductor substrate/wafer. The FEOL stage processes include wafer preparation, isolation, gate patterning, and the formation of wells, source/drain (S/D) regions, extension junctions, silicide regions, and liners. The MOL stage typically includes process flows for forming the contacts (e.g., CA) and other structures that communicatively couple to active regions (e.g., gate, source, and drain) of the device element. For example, the silicidation of source/drain regions, as well as the deposition of metal contacts, can occur during the MOL stage to connect the elements patterned during the FEOL stage. Layers of interconnections (e.g., metallization layers) are formed above these logical and functional layers during the BEOL stage to complete the IC. Most ICs need more than one layer of wires to form all the necessary connections, and as many as 5-12 layers are added in the BEOL process. The various BEOL layers are interconnected by vias that couple from one layer to another. Insulating dielectric materials are used throughout the layers of an IC to perform a variety of functions, including stabilizing the IC structure and providing electrical isolation of the IC elements. For example, the metal interconnecting wires in the BEOL region of the IC are isolated by dielectric layers to prevent the wires from creating a short circuit with other metal layers.

As discussed previously, a key component of the BEOL structure is the power delivery network (PDN). Backside power delivery (also referred to as a backside power delivery network) is a chip architecture that involves repositioning layers of the PDN from the top of the FEOL to the opposite side of the chip. In other words, in a backside-style architecture the PDN layers are placed on the backside of the semiconductor substrate onto which the active devices have been built. Challenges remain, however, in fully leveraging backside power delivery chip architectures.

One such challenge is the difficulty in co-integrating backside power delivery with a virtual power supply (sometimes referred to as boost). “Virtual” power supplies, as the name suggests, are not connected to the actual device power supply (e.g., a common supply voltage, often denoted VDD), but instead serve as separate, supplemental supplies of power (boost) to specific regions of a substrate (i.e., some transistor(s)). Device boosting is an attractive technology offering that exploits on-chip capacitive coupling (e.g., between interconnect lines in SOI finFETs) to enable dynamically boosted power delivery. Boosting can improve device functionality and performance by allowing, for example, increases in individual transistor voltages (e.g., from 0.3 v to 0.7 v, etc.). Virtual power supplies are not easily co-integrated with backside power delivery chip architectures as both platforms require dedicated metallization systems (interconnects).

Turning now to an overview of aspects of the present invention, one or more embodiments of the invention address the above-described shortcomings by providing fabrication methods and resulting structures for providing a virtual power supply through a wafer backside (sometimes referred to as the backside virtual power supply). As used herein, a “backside virtual power supply” refers to a structural feature of one or more embodiments of this disclosure where virtual power is interdigitated with boost signal lines at the backside of a wafer, thereby reducing a number of metallization levels over the FEOL devices (e.g., transistor arrays).

Boosted devices (e.g., transistors) can be connected to the backside virtual power supply in a variety of ways. In some embodiments, one side of the source/drain regions of a boosted device is connected to a frontside power supply (VDD) in the BEOL metallization (Mx layer), while the other side of the source/drain is connected to a virtual power supply at the backside of the wafer. A gate can be connected to a boost signal on the frontside and a backside boost signal line can run in parallel to the virtual power supply lines connected to the gate.

While generally described with respect to a backside virtual power supply, in some embodiments, the virtual power supply and true power supply can backside-frontside swapped. For example, in some embodiments, one side of the source/drain regions of a boosted device is connected to a backside power deliver network (BS-PDN), while the other side of the source/drain is connected to a virtual power supply at the frontside of the wafer. The gate of the boosted device can be connected to a boost signal on the frontside.

In yet other embodiments, the virtual power supply and true power supply can run in parallel on the backside (or frontside). For example, one side of the source/drain regions of a boosted device is connected to a backside power deliver network (BS-PDN) and the other side of the source/drain is connected to a virtual power supply at the backside side of the wafer. The gate can be connected to a boost signal on the frontside and a backside boost signal line can run in parallel to the virtual power supply lines connected to the gate.

Turning now to a more detailed description of fabrication operations and resulting structures according to aspects of the invention,FIG.1Adepicts a cross-sectional view taken along the line X (across gate in channel of logic region) inFIG.1Fof a semiconductor wafer100after an initial set of fabrication operations have been applied as part of a method of fabricating a final semiconductor device according to one or more embodiments of the invention.FIG.1Bdepicts a cross-sectional view taken along the line Y1(along gate in source/drain of logic region) inFIG.1F.FIG.1Cdepicts a cross-sectional view taken along the line Y2(along gate in first source/drain of boost region) inFIG.1F.FIG.1Ddepicts a cross-sectional view taken along the line Y3(along gate in channel of boost region) inFIG.1F.FIG.1Edepicts a cross-sectional view taken along the line Y4(along gate in second source/drain of boost region) inFIG.1F.FIG.1Fdepicts a top-down reference view of the semiconductor wafer100.

As shown inFIGS.1A-1F, various FEOL102and MOL104structures have been built in the semiconductor wafer100. The specific examples of the FEOL102and MOL104are provided for ease of discussion only and are not meant to be particularly limited. For example, the FEOL102illustrates a nanosheet-style transistor architecture. It should be understood, however, that the nanosheet-style transistor architecture of the FEOL102is provided for ease of discussion only and that other transistor architectures (e.g., vertical tunneling transistors, planar transistors, finFETs, etc.) are included in the contemplated scope of this disclosure. Similarly, other MOL structures can be fabricated depending on the needs of a given application, and all such configurations are within the contemplated scope of this disclosure.

In some embodiments, the semiconductor wafer100includes one or more nanosheets110(collectively, a nanosheet stack(s)) and a gate112formed over channel regions of the one or more nanosheets110. As used herein, a “channel region” refers to the portion of a nanosheet of the one or more nanosheets110over which the gate112is formed, and through which current passes from source to drain in the final device.

In some embodiments, the gate112includes a gate extension112a. As discussed in further detail with respect toFIG.5D, the gate extension112aextends into the STI region118to enable a backside signal connection.

In some embodiments, the semiconductor wafer100includes a substrate138having an etch stop layer136(e.g., a buried oxide layer or a SiGe epi layer) and an additional semiconductor layer134(e.g., Si) over the etch stop layer136, although other substrate configurations are within the contemplated scope of this disclosure. In some embodiments, the substrate (e.g., substrate134/136/138) includes a silicon-on-insulator (an) structure and the substrate138is a bottommost substrate layer.

FIGS.2A,2B,2C,2D, and2Edepict cross-sectional views of the semiconductor wafer100taken along the lines X, Y1, Y2, Y3, and Y4, respectively, ofFIG.2Fafter a processing operation according to one or more embodiments. In some embodiments, BEOL structures are built on the semiconductor wafer100. The specific examples of the BEOL structures are provided for ease of discussion only and are not meant to be particularly limited. For example, the BEOL structure shown inFIG.2Acan include one or more first vias202(“V0”), a first metal layer204(“M1”), any number of intermediate interconnects206(metal levels/vias between Mx and M1 which connects a power supply (“VDD”) at Mx to M1), one or more last vias208(“Vx−1”), a last metal layer210(“Mx”), and one or more dielectric layers212. In some embodiments, one or more additional BEOL levels214are formed above the last metal layer210.

As shown inFIG.2D, the gate112is connected to the one or more first vias202by way of the gate contact130. In some embodiments, the gate contact130is configured as a boost signal in boost regions of the semiconductor wafer100(refer toFIG.2F). Boost circuit regions refer to regions of the semiconductor wafer100where the power supply (“VDD”) in Mx is converted to a virtual VDD at the wafer backside according to one or more embodiments.

FIGS.3A,3B,3C,3D, and3Edepict cross-sectional views of the semiconductor wafer100taken along the lines X, Y1, Y2, Y3, and Y4, respectively, ofFIG.3Fafter a processing operation according to one or more embodiments. In some embodiments, a carrier wafer302is formed over the last metal layer210(e.g., on the one or more additional BEOL levels214, if present).

In some embodiments, the semiconductor wafer100is flipped and the bottommost substrate layer138is removed. The bottommost substrate layer138can be removed using any suitable process, such as, for example, combination of wafer grinding, CMP, dry etch and a wet etch stopping on the etch stop layer136.

FIGS.4A,4B,4C,4D, and4Edepict cross-sectional views of the semiconductor wafer100taken along the lines X, Y1, Y2, Y3, and Y4, respectively, ofFIG.4Fafter a processing operation according to one or more embodiments. In some embodiments, the etch stop layer136is removed and the additional semiconductor layer134is recessed to expose a top surface of the STI region118(FIGS.4B,4C,4D,4E), the gate extension112a(FIG.4D), and the VBPRs132(FIGS.4B,4E).

The etch stop layer136can be removed and the additional semiconductor layer134can be recessed using any suitable technique, such as, for example, using a wet etch, a dry etch, or a combination of sequential wet and/or dry etches. In some embodiments, the additional semiconductor layer134can be recessed below the top surface of the STI region118, the gate extension112a, and/or the VBPRs132.

FIGS.5A,5B,5C,5D, and5Edepict cross-sectional views of the semiconductor wafer100taken along the lines X, Y1, Y2, Y3, and Y4, respectively, ofFIG.5Fafter a processing operation according to one or more embodiments. In some embodiments, a backside dielectric502is formed on the semiconductor wafer100. In some embodiments, the backside dielectric502is deposited or otherwise formed on the recessed surface of the additional semiconductor layer134.

In some embodiments, the backside dielectric502is a high-k dielectric. As used herein, a “high-k” dielectric refers to a material having a dielectric constant greater than 3.0 (i.e., a higher dielectric constant than conventional BEOL low-k dielectrics). Examples of high-k materials include, but are not limited to, SiO2, SiN, SiC, SiOC, or combination of above materials.

In some embodiments, conductive materials are deposited in the backside dielectric502to define one or more backside metallization layers (here, the backside metal layer504). The backside metal layer504can also be referred to as the backside M1. This process can be referred to as a backside M1 metallization (or, as a first backside metallization layer). The backside metal layer504can include various lines and vias depending on the requirements of a given application. In some embodiments, the backside metal layer504is configured as a backside virtual power supply including a “virtual VDD”, a “virtual VSS”, and a “boost signal” (as shown). In some embodiments, the frontside metallization layers (e.g., the last metal layer210) are configured as a frontside power supply include a “VDD” (as shown) and “VSS” (not separately shown).

In some embodiments, a backside power delivery network (BS-PDN)506is formed over the backside metal layer504. The BS-PDN506can include any number of metal layers, lines, and vias, and can be formed in a similar manner as the BEOL structures discussed previously with respect toFIGS.2A,2B,2C,2D, and2E, except that the BS-PDN506is formed on an opposite side of the semiconductor wafer100.

After backside M1 metallization is complete, the semiconductor wafer100can be finalized using known processes (e.g., additional BEOL, far back end of line (FBEOL), packaging, etc., processes used to define a final device, including the incorporation of additional frontside or backside metallization layers).

FIGS.6A,6B,6C,6D, and6Edepict cross-sectional views of the semiconductor wafer100taken along the lines X, Y1, Y2, Y3, and Y4, respectively, ofFIG.6Fafter a processing operation according to one or more embodiments.FIGS.6A,6B,6C,6D, and6Edepict an alternative embodiment from that shown inFIGS.5A,5B,5C,5D, and5E. InFIGS.5A,5B,5C,5D, and5E, the backside power delivery is fully virtual, while the frontside power delivery is the true power supply. In contrast, inFIGS.6A,6B,6C,6D, and6Ethe backside power delivery is the true power supply, while the frontside power delivery is virtual. The semiconductor wafer100is otherwise configured in a similar manner as shown inFIGS.5A,5B,5C,5D, and5E.

FIGS.7A,7B,7C,7D, and7Edepict cross-sectional views of the semiconductor wafer100taken along the lines X, Y1, Y2, Y3, and Y4, respectively, ofFIG.7Fafter a processing operation according to one or more embodiments.FIGS.7A,7B,7C,7D, and7Edepict an alternative embodiment from that shown inFIGS.5A,5B,5C,5D, and5E. InFIGS.5A,5B,5C,5D, and5E, the backside power delivery is fully virtual, while the frontside power delivery is the true power supply. In contrast, inFIGS.7A,7B,7C,7D, and7Ethe backside power delivery offers both the true power supply and virtual power (i.e., a hybrid backside power delivery system).

In some embodiments, additional VBPRs132are provided for backside power delivery (seeFIG.7C). In some embodiments, one or more first vias202are removed (or their fabrication is entirely skipped), preventing a frontside-to-backside short due to the presence of the additional VBPRs132. The semiconductor wafer100is otherwise configured in a similar manner as shown inFIGS.5A,5B,5C,5D, and5E.

FIG.8depicts a flow diagram illustrating a method800for providing a virtual power supply through a wafer backside according to one or more embodiments of the invention. As shown at block802, a front end of line structure including a gate is formed. At block804, a back end of line structure is formed on a first surface of the front end of line structure. At block806, a backside power delivery network is formed on a second surface of the front end of line structure opposite the first surface.

In some embodiments, source and drain regions on a first side of the gate are connected to the backside power delivery network and source and drain regions on a second side of the gate are connected to the back end of line structure.

In some embodiments, the back end of line structure includes a power supply. In some embodiments, a virtual power supply is formed between the front end of line structure and the backside power delivery network. In some embodiments, the power supply is connected to the source and drain regions on the second side of the gate and the virtual power supply is connected to the source and drain regions on the first side of the gate.

In some embodiments, the back end of line structure includes a virtual power supply. In some embodiments, a power supply is formed between the front end of line structure and the backside power delivery network. In some embodiments, the power supply is connected to the source and drain regions on the first side of the gate and the virtual power supply is connected to the source and drain regions on the second side of the gate.

In some embodiments, the gate is connected to a boost signal on the back end of line structure and a backside boost signal line between the backside power delivery network and the front end of line structure. In some embodiments, the gate includes a gate extension that extends through a shallow trench isolation region of the front end of line structure. In some embodiments, the gate extension is directly connected to the backside boost signal line.

Various embodiments of the present invention are described herein with reference to the related drawings. Alternative embodiments can be devised without departing from the scope of this invention. Although various connections and positional relationships (e.g., over, below, adjacent, etc.) are set forth between elements in the following description and in the drawings, persons skilled in the art will recognize that many of the positional relationships described herein are orientation-independent when the described functionality is maintained even though the orientation is changed. These connections and/or positional relationships, unless specified otherwise, can be direct or indirect, and the present invention is not intended to be limiting in this respect. Similarly, the term “coupled” and variations thereof describes having a communications path between two elements and does not imply a direct connection between the elements with no intervening elements/connections between them. All of these variations are considered a part of the specification. Accordingly, a coupling of entities can refer to either a direct or an indirect coupling, and a positional relationship between entities can be a direct or indirect positional relationship. As an example of an indirect positional relationship, references in the present description to forming layer “A” over layer “B” include situations in which one or more intermediate layers (e.g., layer “C”) is between layer “A” and layer “B” as long as the relevant characteristics and functionalities of layer “A” and layer “B” are not substantially changed by the intermediate layer(s).

The term “conformal” (e.g., a conformal layer or a conformal deposition) means that the thickness of the layer is substantially the same on all surfaces, or that the thickness variation is less than 15% of the nominal thickness of the layer.

As used herein, “p-type” refers to the addition of impurities to an intrinsic semiconductor that creates deficiencies of valence electrons. In a silicon-containing substrate, examples of p-type dopants, i.e., impurities, include but are not limited to, boron, aluminum, gallium, and indium.

As used herein, “n-type” refers to the addition of impurities that contributes free electrons to an intrinsic semiconductor. In a silicon containing substrate examples of n-type dopants, i.e., impurities, include but are not limited to antimony, arsenic and phosphorous.