Semiconductor device

A method of forming a semiconductor device comprises forming a base wafer comprising a first chip package portion, a second chip package portion, and a third chip package portion. The method also comprises forming a capping wafer comprising a plurality of isolation trenches, each of the plurality of isolation trenches being configured to substantially align with one of the first chip package portion, the second chip package portion or the third chip package portion. The method further comprises eutectic bonding the capping wafer and the base wafer to form a wafer package. The method additionally comprises dicing the wafer package into a first chip package, a second chip package, and a third chip package. The method also comprises placing the first chip package, the second chip package, and the third chip package onto a substrate.

BACKGROUND

Device manufacturers are continually challenged to deliver value and convenience to consumers by, for example, providing integrated circuits that provide quality performance. Some integrated circuits include multiple microelectromechanical systems or chip packages formed by different processes. These types of integrated circuits often fail because the chip packages are not formed under common conditions, and/or one chip package's operational performance is unknown compared to another chip package's operational performance.

DETAILED DESCRIPTION

The following disclosure provides many different embodiments, or examples, for implementing different features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These are examples and are not intended to be limiting.

Some semiconductor devices combine multiple chip packages into an integrated circuit. These semiconductor devices often fail because of difficulty in determining whether a chip package is capable of performing an intended operation or the chip package is defective. As such, some devices that are capable of performing an intended operation are joined with defective devices causing the integrated circuit to fail. Using devices that are known to be capable of performing an intended operation reduces the likelihood that a final semiconductor device will be defective. Controlling the source of all of the chip packages used in a semiconductor device increases the likelihood that all of the chip packages used in the semiconductor device are known to be able to perform an intended operation.

FIG. 1is a cross sectional view of a semiconductor device100, in accordance with one or more embodiments. The semiconductor device100comprises a CMOS chip package101, a first chip package103, a second chip package105, and a third chip package107bonded together by a molding compound109. Each of the first chip package103, second chip package105, and third chip package107include isolation trenches111a-111ctherein.

The semiconductor device100also comprises a plurality of conductive elements113a-113dthat are over and in contact with a series of under bump layers115a-115c. The under bump layers115a-115care over and in contact with a redistribution layer117. Each of the conductive elements113and the under bump layers115are formed within a plurality of openings in an insulation layer119. The insulation layer119, in some embodiments, comprises an epoxy or low outgas sing material. Conductive pads121a-121c(collectively referred to as conductive pad121) are over the chip packages103,105and107and in contact with a series of pairs of dielectric plugs123a-123f(collectively referred to as dielectric layer123).

The first chip package103, second chip package105, and third chip package107each comprise a chip package portion125of a series of corresponding chip package portions125a-125c(collectively referred to as chip package portion125) that are each derived from a same base wafer. The first chip package103, second chip package105, and third chip package107also each comprise a capping wafer portion127of a series of corresponding capping wafer portions127a-127c(collectively referred to as capping wafer portion127). The capping wafer portions127a-127care eutectic bonded by a eutectic bond129to the chip package portions125. The capping wafer portions127a-127care each derived from a same capping wafer. In some embodiments, at least one of the conductive pads121substantially align with at least one pad or location of eutectic bond129.

The capping wafer and the base wafer are eutectic bonded before being separated into capping wafer portions127and chip package portions125by eutectic bond129to form a wafer package and then diced to separate the wafer package into the first chip package103, second chip package105, and third chip package107.

In some embodiments, the first chip package103, second chip package105and third chip package107are configured to perform specific operations. For example, in some embodiments, the first chip package103is an accelerometer, the second chip package105is a gyroscope, and the third chip package107is a pressure sensor. In some embodiments, the semiconductor device100comprises one or more types of chip packages that are one or more of application specific integrated circuits (ASIC), a high vacuum pressure devices (such as devices having 3 ATM pressure), or low vacuum pressure devices.

FIG. 2is a cross sectional view of a wafer package200, in accordance with one or more embodiments. The wafer package200includes a capping wafer201eutectic bonded to a base wafer203. The capping wafer201includes capping wafer portions127and chip package portions125before being separated by a die cutting process along lines202aand202b. The eutectic bonds129are formed between the capping wafer201and the base wafer203before the die cutting process. Accordingly, each of the resulting chip packages103,105and107are formed from the same capping wafer201, the same base wafer203, and are subjected to the same eutectic bonding process that forms eutectic bonds129.

In some embodiments, the eutectic bonds129comprise aluminum, germanium, indium, gold, tin, silicon, tungsten, carbon, other suitable materials, or a combination thereof. In some embodiments, one or more materials that are part of eutectic bonds129are deposited on one or more of the capping wafer201or the base wafer203before the eutectic bonds129are formed.

The wafer package200comprises the dielectric layer123that includes dielectric plugs123a-123f. The dielectric plugs123a-123fare formed in openings within the capping wafer201after the capping wafer201and the base wafer203are eutectic bonded or before the capping wafer201and the base wafer203are eutectic bonded. Additionally, the wafer package200includes conductive pads121a-121c. In some embodiments, the conductive pads121comprise aluminum, copper, gold, tin, other suitable materials, or a combination thereof.

The isolation trenches111a-111cof the capping wafer201align with corresponding trenches205a-205cof the chip package portions125. The isolation trenches111a-111care formed by any process capable of removing material from a substrate such as, but not limited to, an etching process, in the capping wafer201before the capping wafer201is eutectic bonded to the base wafer203.

FIG. 3is a cross sectional view of a wafer package300, in accordance with one or more embodiments. The wafer package300includes many of the features discussed with respect to wafer package200illustrated inFIG. 2. The wafer package300; however, includes a capping wafer301that includes dielectric layer123that comprises an alternative dielectric layer123. For example, the dielectric layer123is formed in a plurality of openings303a-303f. The openings303a-303fare, in some embodiments, formed by an isotropic etching process performed before or after the capping wafer301is eutectic bonded to the base wafer203. The capping wafer301is subjected to an oxidation process to form an oxide layer307at least covering the sidewalls of the openings303a-303fand optionally over the capping wafer301. The openings303a-303fthen have a dielectric material such as, but not limited to, a polysilicon material deposited therein.

FIG. 4is a flowchart of a process400for making a semiconductor device such as semiconductor device100, in accordance with one or more embodiments. The process begins with step401in which an adhesive material402is placed on a carrier404. Then, in step403, chip packages103,105and107are placed on the carrier404. Next, in step405, the molding compound109is deposited over the first chip package103, the second chip package105and the third chip package107. The molding compound109is also cured. In step407, the molding compound109is optionally leveled by, for example, a grinding or CMP process, exposing one or more portions of one or more of the chip package103,105,107.

Then, in step409, a reconstructed wafer is formed by optionally forming the redistribution layer117over the chip packages103,105and107, and optionally forming the insulation layer119over the first chip package103, the second chip package105, and the third chip package107. The insulation layer119is optionally cured if the insulation layer119comprises a material that requires curing. The insulation layer119is also optionally leveled by a grinding or CMP process. A plurality of openings408are formed in the insulation layer119exposing the redistribution layer117, for example, by an etching process or other suitable process for removing material.

In step411, a plurality of conductive elements such as solder balls are deposited in the plurality of openings408. In some embodiments, the plurality of conductive elements alternatively comprise a plurality of conductive pillars. The semiconductor device100is then tested for one or more functions associated with the semiconductor device100and/or any operations associated with each of the chip packages103,105, or107. In some embodiments, the under bumper layers115are optionally deposited in the openings408before depositing the conductive elements in the openings408. Then, in step413, the carrier404is optionally removed from the semiconductor device100by, for example, de-bonding the adhesive402.

FIG. 5is a flow chart of a method500of making a semiconductor device100, in accordance with one or more embodiments. Method500begins with step501in which a base wafer comprising a first chip package portion, a second chip package portion, and a third chip package portion is formed by a combination of deposition, etching, photolithographic processes, or other suitable process in or on a substrate.

Then, in step503, a capping wafer is formed comprising a plurality of isolation trenches, each of the plurality of isolation trenches being configured to substantially align with one of the first chip package portion, the second chip package portion or the third chip package portion. The capping wafer is formed by a combination of deposition, etching, photolithographic processes, or other suitable process in or on a substrate.

In some embodiments, a plurality of communication openings are formed in the capping wafer by an etching process, or other suitable process for removing material from one or more layers of the capping wafer. The plurality of communication openings comprise a first pair of communication openings substantially aligned with the first chip package portion, a second pair of communication openings substantially aligned with the second chip package portion, and a third pair of communication openings substantially aligned with the third chip package portion. The openings are filled with a dielectric material forming a dielectric layer, and a plurality of conductive pads are deposited over the dielectric layer.

In some embodiments, the capping wafer is subjected to an oxidization process to form an oxidation layer at least in the plurality of communication openings, and a dielectric material is deposited in the plurality of communication openings. In some embodiments, the plurality of isolation trenches is formed by an etching process, for example, between the pairs of communication openings either before the communication openings are formed, or after.

In step505, the capping wafer is eutectic bonded to the base wafer to form a wafer package. In some embodiments, the communication openings are formed in the capping wafer before the capping wafer is eutectic bonded to the base wafer. In other embodiments, the communication openings are formed after the capping wafer is eutectic bonded to the base wafer.

In step507, wafer package is die cut to separate the wafer package into a first chip package configured to perform a first operation, the first chip package comprising the first chip package portion, a second chip package configured to perform a second operation, the second chip package comprising the second chip package portion, and a third chip package configured to perform a third operation, the third chip package comprising the third chip package portion. In some embodiments, the plurality of communication openings are formed in the capping wafer before the wafer package is die cut. In other embodiments, the plurality of communication openings is formed in the capping wafer and any portions thereof after the diecutting process.

In step509, the process continues to process400, discussed with respect toFIG. 4. In some embodiments, a CMOS chip package portion is placed on the carrier404(FIG. 4) before bonding the first chip package, the second chip package and third chip package. Accordingly, the CMOS chip package, the first chip package, the second chip package and the third chip package are bonded together using the molding compound. Additionally, the redistribution layer117(FIG. 1) is also formed over the CMOS chip package.

One aspect of this description relates to a method of forming a semiconductor device, the method comprising forming a base wafer comprising a first chip package portion, a second chip package portion, and a third chip package portion. The method also comprises forming a capping wafer comprising a plurality of isolation trenches, each of the plurality of isolation trenches being configured to substantially align with one of the first chip package portion, the second chip package portion or the third chip package portion. The method further comprises eutectic bonding the capping wafer and the base wafer to form a wafer package. The method additionally comprises dicing the wafer package to separate the wafer package into a first chip package configured to perform a first operation, a second chip package configured to perform a second operation, and a third chip package configured to perform a third operation. The first chip package comprises the first chip package portion, the second chip package comprises the second chip package portion, and the third chip package comprises the third chip package portion. The method also comprises placing the first chip package, the second chip package, and the third chip package onto a substrate.

Another aspect of this description relates to a semiconductor device comprising a first chip package configured to perform a first operation, the first chip package comprising a first chip package portion comprising a first base wafer portion of a base wafer and a first capping wafer portion of a capping wafer eutectic bonded to the first base wafer portion. The semiconductor device also comprises a second chip package configured to perform a second operation, the second chip package comprising a second chip package portion comprising a second base wafer portion of the base wafer and a second capping wafer portion of the capping wafer eutectic bonded to the second base wafer portion. The semiconductor device further comprises a third chip package configured to perform a third operation, the third chip package comprising a third chip package portion comprising a third base wafer portion of the base wafer and a third capping wafer portion of the capping wafer eutectic bonded to the third base wafer portion. The semiconductor device additionally comprises a CMOS chip package. The CMOS chip package, the first chip package, the second chip package and the third chip package are bonded together by a molding compound. The first chip package, the second chip package and the third chip package are separate components derived from the capping wafer and the base wafer.

Still another aspect of this description relates to a semiconductor device comprising a first chip package configured to perform a first operation, the first chip package comprising a first chip package portion comprising a first base wafer portion of a base wafer and a first capping wafer portion of a capping wafer eutectic bonded to the first base wafer portion. The semiconductor device also comprises a second chip package configured to perform a second operation, the second chip package comprising a second chip package portion comprising a second base wafer portion of the base wafer and a second capping wafer portion of the capping wafer eutectic bonded to the second base wafer portion. The semiconductor device further comprises a third chip package configured to perform a third operation, the third chip package comprising a third chip package portion comprising a third base wafer portion of the base wafer and a third capping wafer portion of the capping wafer eutectic bonded to the third base wafer portion. The semiconductor device additionally comprises a CMOS chip package.

The semiconductor device also comprises a plurality of communication openings in the capping wafer, the plurality of communication openings comprising a first pair of communication openings configured to substantially align with the first chip package portion, a second pair of communication openings configured to substantially align with the second chip package portion, and a third pair of communication openings configured to substantially align with the third chip package portion. The semiconductor device further comprises an oxidation layer in the plurality of communication openings. The semiconductor device additionally comprises a dielectric material in the plurality of communication openings. The semiconductor device also comprises a plurality of isolation trenches between the pairs of communication openings. The CMOS chip package, the first chip package, the second chip package and the third chip package are bonded together by a molding compound. The first chip package, the second chip package and the third chip package are separate components derived from the capping wafer and the base wafer.

It will be readily seen by one of ordinary skill in the art that the disclosed embodiments fulfill one or more of the advantages set forth above. After reading the foregoing specification, one of ordinary skill will be able to affect various changes, substitutions of equivalents and various other embodiments as broadly disclosed herein. Although features of various embodiments are expressed in certain combinations among the claims, it is contemplated that these features can be arranged in any combination and order. It is therefore intended that the protection granted hereon be limited only by the definition contained in the appended claims and equivalents thereof.