Semiconductor device having a metal gate electrode stack

A semiconductor device includes a substrate, a gate dielectric layer on the substrate, and a gate electrode stack on the gate dielectric layer. The gate electrode stack includes a metal filling line, a wetting layer, a metal diffusion blocking layer, and a work function layer. The wetting layer is in contact with a sidewall and a bottom surface of the metal filling line. The metal diffusion blocking layer is in contact with the wetting layer and covers the sidewall and the bottom surface of the metal filling line with the wetting layer therebetween. The work function layer covers the sidewall and the bottom surface of the metal filling line with the wetting layer and the metal diffusion blocking layer therebetween.

TECHNICAL FIELD

The disclosure relates to semiconductor devices and methods of manufacturing the same.

BACKGROUND

In a semiconductor device such as metal-oxide-semiconductor field-effect transistors (MOSFETs), metals have been introduced as gate electrode materials in order to avoid the polysilicon depletion effect in a doped polysilicon gate electrode. A replacement-gate (RPG) process has been introduced for fabricating a metal gate electrode. As device dimensions shrink and the gate length is scaled down, it is difficult to form a void-free metal gate structure in the RPG process.

DETAILED DESCRIPTION

It is to be understood that the following disclosure provides many different embodiments or examples, for implementing different features of various embodiments. Specific examples of components and arrangements are described below to simplify the present disclosure. The present disclosure may, however, be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein; rather, these embodiments are provided so that this description will be thorough and complete, and will fully convey the present disclosure to those of ordinary skill in the art. It will be apparent, however, that one or more embodiments may be practiced without these specific details.

In the drawings, the thickness and width of layers and regions are exaggerated for clarity. Like reference numerals in the drawings denote like elements. The elements and regions illustrated in the figures are schematic in nature, and thus relative sizes or intervals illustrated in the figures are not intended to limit the scope of the present disclosure.

FIG. 1is a cross-sectional view of a semiconductor device100according to an embodiment of the present disclosure. The semiconductor device100comprises a substrate110having an active area112. Lightly doped drain (LDD) regions114and source/drain regions116are formed in the active area112of the substrate110. An inter-layer dielectric pattern120is formed on the active area112of the substrate110. The inter-layer dielectric pattern120includes insulating spacers124and insulating patterns126. The inter-layer dielectric pattern120defines a gate trench128formed through the inter-layer dielectric pattern120on the active area112of the substrate110. In some embodiments, the insulating spacers124include an oxide layer, a nitride layer, or a combination thereof. In some embodiments, the insulating patterns126include a silicon oxide layer or an insulating layer having low dielectric constant (low-k) dielectric characteristics.

A gate dielectric layer130is formed on and contacting a top surface of the active area112and sidewalls of the inter-layer dielectric pattern120. In one or more embodiments, the gate dielectric layer130is formed of at least one of high-k dielectric materials, silicon oxide, silicon nitride, or silicon oxynitride. The high-k dielectric materials include materials having a dielectric constant greater than silicon dioxide. The high-k dielectric materials suitable for the gate dielectric layer130include hafnium oxide, hafnium oxide doped with Zr, aluminum oxide, titanium oxide, zirconium oxide, indium oxide, lanthanum oxide, yttrium oxide, hafnium silicon oxide, hafnium aluminum oxide, aluminum silicon oxide, titanium silicon oxide, zirconium silicon oxide, strontium oxide, strontium titanium oxide, yttrium silicon oxide, and combinations thereof, but are not limited by the above-mentioned materials. In some embodiments, the gate dielectric layer130has a stack structure of two or more dielectric layers. In one or more embodiments, the gate dielectric layer130has a stack structure of an interfacial dielectric layer, such as a silicon oxide layer, and a high-k material layer overlying the interfacial dielectric layer. In some embodiments, the gate dielectric layer130has a thickness in the range of about 1 to 4 nanometers (nm).

A capping layer132and a barrier layer140are sequentially formed on the gate dielectric layer130. In one or more embodiments, the capping layer132and the barrier layer140are optional. A metal gate electrode stack150fills the remainder of the gate trench128on the barrier layer140. The metal gate electrode stack150includes a work function layer152, a metal diffusion blocking layer154, a wetting layer156, and a metal filling line158sequentially formed on the barrier layer140.

The metal filling line158is composed of a line-shaped metal layer extending along and within the gate trench128. The metal filling line158has sidewalls158SW facing the sidewalls of the inter-layer dielectric pattern120and a bottom surface158BT facing the active area112. The wetting layer156is in contact with at least a portion of the sidewalls158SW and at least a portion of the bottom surface158BT of the metal filling line158. The metal diffusion blocking layer154is in contact with at least a portion of the wetting layer156and covers at least a portion of the sidewalls158SW and at least a portion of the bottom surface158BT of the metal filling line158with the wetting layer156therebetween. The work function layer152covers the sidewalls158SW and the bottom surface158BT of the metal filling line158with the wetting layer156and the metal diffusion blocking layer154therebetween.

In one or more embodiments, the wetting layer156extends to continuously or intermittently cover the metal filling line158along the sidewalls158SW and the bottom surface158BT thereof. In some embodiments, the metal diffusion blocking layer154extends to continuously or intermittently cover the wetting layer156along the sidewalls158SW and the bottom surface158BT of the metal filling line158. In some embodiments, a top portion of the sidewalls158SW or the immediate vicinity of a top surface of the metal filling line158is covered by the metal diffusion blocking layer154and/or the wetting layer156.

The metal filling line158is positioned in the middle with regard to distance from the sidewalls of the inter-layer dielectric pattern120at the entrance of the gate trench128. In some embodiments, the metal filling line158comprises at least one of aluminum (Al), copper (Cu), AlCu, or tungsten (W), but is not limited by the above-mentioned materials.

As device dimensions shrink and the gate length becomes scaled down, the phenomenon of electromigration in the metal filling line158can cause voids in the vicinity of the metal filling line158within the gate trench128. The voids generated in a gate electrode may deteriorate an electrical characteristic and reliability of the gate electrode, increase the resistance of the gate electrode, and/or weaken the structural integrity of the gate electrode. Electromigration is the movement or diffusion of atoms in a metal line, for example, caused by current flow through the metal line. Diffusion of metal ions from the sidewalls158SW and the bottom surface158BT of the metal filling line158may lead to voids in the metal gate electrode stack150. The wetting layer156and the metal diffusion blocking layer154are formed to cover the sidewalls158SW and the bottom surface158BT of the metal filling line158. Therefore, the wetting layer156and the metal diffusion blocking layer154inhibit diffusion of metal ions from the metal filling line158to adjacent layers, thereby inhibiting the formation of the undesirable voids in the vicinity of the metal filling line158of the metal gate electrode stack150.

Further, the wetting layer156contacts with the sidewalls158SW and the bottom surface158BT of the metal filling line158between the metal filling line158and the metal diffusion blocking layer154as depicted inFIG. 1. In one or more embodiments, the wetting layer156is a metal layer which forms bonds to the metal filling line158. The wetting layer156enables the metal filling line158to have improved filling characteristics in the gate trench128, and therefore results in a continuous void-free metal gate electrode stack by facilitating filling of the gate trench128with the metal such as Al, Cu, or alloys thereof for forming the metal filling line158without leaving unfilled voids therein. The wetting layer156includes at least one of cobalt (Co), Ti, or Ta. In some embodiments, the wetting layer156has a thickness in the range of about 1 to 5 nm.

The metal diffusion blocking layer154is in contact with the wetting layer156between the wetting layer156and the work function layer152. The metal diffusion blocking layer154includes a metal nitride. For example, the metal diffusion blocking layer154includes at least one of a Ti-rich TiN layer, a TaN layer, or a TiN layer. The Ti-rich TiN layer has a relatively large content of Ti in comparison with a stoichiometric TiN layer consisting of a 1:1 mixture of Ti and N atoms. That is, the Ti-rich TiN layer has more than 50 atomic percent Ti content therein. The metal diffusion blocking layer154has a stack structure of a first metal nitride layer154A and a second metal nitride layer154B. The first metal nitride layer154A and the second metal nitride layer154B comprise different compositions of metal nitride from each other. For example, the metal diffusion blocking layer154has the first metal nitride layer154A comprising TiN, and the second metal nitride layer154B comprising Ti-rich TiN. Alternatively, the metal diffusion blocking layer154has the first metal nitride layer154A comprising TiN, and the second metal nitride layer154B comprising TaN. The first metal nitride layer154A of the metal diffusion blocking layer154contacts with the work function layer152. The second metal nitride layer154B of the metal diffusion blocking layer154contacts with the wetting layer156. In some embodiments, the first metal nitride layer154A and the second metal nitride layer154B of the metal diffusion blocking layer154have thicknesses in the range of about 1 to 5 nm.

The work function layer152is interposed between the barrier layer140and the metal diffusion blocking layer154, and faces the sidewalls158SW and the bottom surface158BT of the metal filling line158within the gate trench128. In one or more embodiments, the work function layer152comprises at least one of Ti, Al, TiAl, TiN, Co, WN, or TaC. For example, the work function layer152comprises at least one of Ti, Al, or TiAl when the metal gate electrode stack150is part of an N-channel MOS (NMOS) transistor of a complementary MOS (CMOS) device. Alternatively, the work function layer152comprises at least one of TiN, Co, WN, or TaC when the metal gate electrode stack150is part of a P-channel MOS (PMOS) transistor of the CMOS device. In some embodiments, the work function layer152has a thickness in the range of about 1 to 10 nm.

The work function layer152is in contact with the barrier layer140. In some embodiments, additional one or more metallic layers (not shown) are interposed between the work function layer152and the barrier layer140such that the work function layer152and the barrier layer140are not in direct contact.

The capping layer132conformally covers the gate dielectric layer130while contacting with a top surface of the gate dielectric layer130. In some embodiments, the capping layer132includes at least one of metal nitrides such as titanium nitride (TiN) and tantalum nitride (TaN), metal carbides such as tantalum carbide (TaC), and combinations thereof. In one or more embodiments, the capping layer132has a thickness in the range of about 1 to 5 nm.

The barrier layer140is interposed between the capping layer132and the work function layer152. In some embodiments, the barrier layer140comprises at least one conductive barrier material selected from metals, metal nitrides, or metal alloys. For example, the barrier layer140may include at least one conductive barrier material selected from TiN, TaN, TaC, or WN, but is not limited by the above-mentioned materials. In some embodiments, the barrier layer140has a thickness in the range of about 1 to 5 nm.

FIG. 2is a cross-sectional view of a semiconductor device200according to another embodiment of the present disclosure. In some embodiments, the semiconductor device200can be part of CMOS transistors included in a logic device. InFIG. 2, the features are the same as or similar to like-numbered features described with respect toFIG. 1. For example, an element “2xx” inFIG. 2is the same as or similar to an element “1xx” inFIG. 1. Therefore, the descriptions thereof will be omitted to avoid repetition.

The semiconductor device200comprises a substrate210having a first region I and a second region II as divided by dotted lines inFIG. 2. A first MOS transistor TR1is formed in the first region I, and a second MOS transistor TR2is formed in the second region II. In some embodiments, a first active area212A of the first region I and a second active area212B of the second region II are divided by an isolation layer (not shown) formed in the substrate210.

First LDD regions214A and first source/drain regions216A are formed in the first active area212A of the first region I. In one or more embodiments, the first region I is an NMOS region in which an NMOS transistor is formed as the first MOS transistor TR1. Additionally, N-type LDD regions and N-type source/drain regions are formed in the first active area212A as the first LDD regions214A and first source/drain regions216A, respectively.

Second LDD regions214B and second source/drain regions216B are formed in the second active area212B of the second region II. In one or more embodiments, the second region II is a PMOS region in which a PMOS transistor is formed as the second MOS transistor TR2. Also, P-type LDD regions and P-type source/drain regions are formed in the second active area212B as the second LDD regions214B and second source/drain regions216B, respectively.

An inter-layer dielectric pattern220is formed on the first active area212A of the first region I and on the second active area212B of the second region II. The inter-layer dielectric pattern220includes insulating spacers224and insulating patterns226. A first gate trench228A and a second gate trench228B are formed through the inter-layer dielectric pattern220on the first active area212A and the second active area212B, respectively.

A gate dielectric layer230is formed on the first active area212A and the second active area212B. Within the first gate trench228A, the gate dielectric layer230is formed to cover and contact a top surface of the first active area212A and sidewalls of the inter-layer dielectric pattern220defining the first gate trench228A. Within the second gate trench228B, the gate dielectric layer230is formed to cover and contact a top surface of the second active area212B and sidewalls of the inter-layer dielectric pattern220defining the second gate trench228B.

The first gate trench228A is filled with a first metal gate electrode stack250A over the gate dielectric layer230to form the first MOS transistor TR1. The first metal gate electrode stack250A includes a first work function layer252A, a metal diffusion blocking layer254, a wetting layer256, and a metal filling line258sequentially formed over the gate dielectric layer230. The metal filling line258formed in the first region I has sidewalls258SW facing the sidewalls of the inter-layer dielectric pattern220and bottom surface258BT facing the first active area212A. The metal diffusion blocking layer254has a stack structure of a first metal nitride layer254A and a second metal nitride layer254B. When the first MOS transistor TR1is an NMOS transistor, the first work function layer252A comprises one or more metals needed for a work function suitable for the NMOS transistor. In some embodiments, the first work function layer252A comprises at least one of Ti, Al, or TiAl.

The second gate trench228B is filled with a second metal gate electrode stack250B over the gate dielectric layer230to form the second MOS transistor TR2. The second metal gate electrode stack250B includes a second work function layer252B, the metal diffusion blocking layer254, the wetting layer256, and the metal filling line258sequentially formed over the gate dielectric layer230. The metal filling line258formed in the second region II has sidewalls258SW facing the sidewalls of the inter-layer dielectric pattern220and bottom surface258BT facing the second active area212B. When the second MOS transistor TR2is a PMOS transistor, the second work function layer252B comprises one or more metals needed for a work function suitable for the PMOS transistor. In some embodiments, the second work function layer252B comprises at least one of TiN, Co, WN, or TaC.

A capping layer232is interposed between the gate dielectric layer230and the first work function layer252A in the first region I, and between the gate dielectric layer230and the second work function layer252B in the second region II. A barrier layer240is formed between the capping layer232and the first work function layer252A in the first region I, and between the capping layer232and the second work function layer252B in the second region II.

In various embodiments of the semiconductor device100or200according to the present disclosure, the metal gate electrode stack150,250A, or250B includes the metal filling line158or258, the wetting layer156or256being in contact with the sidewalls158SW or258SW and the bottom surface158BT or258BT of the metal filling line158or258, and the metal diffusion blocking layer154or254being in contact with the wetting layer156or256and covering the sidewalls158SW or258SW and the bottom surface158BT or258BT of the metal filling line158or258with the wetting layer156or256therebetween. The wetting layer156or256includes at least one of Co, Ti, or Ta. The metal diffusion blocking layer154or254has at least one metal nitride layer including at least one of Ti-rich TiN, TaN, or TiN. The stack structure of the metal diffusion blocking layer154or254and the wetting layer156or256covering the sidewalls158SW or258SW and the bottom surfaces158BT or258BT of the metal filling line158or258can inhibit diffusion of metal ions from the metal filling line158or258, thereby inhibiting the formation of the undesirable voids in the metal gate electrode stack150,250A, or250B.

FIGS. 3A through 3Iare cross-sectional views for a method of manufacturing a semiconductor device, according to an embodiment of the present disclosure.

In the embodiments described with reference toFIGS. 3A through 3I, the method of manufacturing the semiconductor device according to the present disclosure is applied to a process for manufacturing a CMOS transistors of a logic device, in particular, to a process for manufacturing the semiconductor device200depicted inFIG. 2.

Referring toFIG. 3A, an isolation layer (not shown) is formed in the substrate210having the first region I and the second region II so as to define a plurality of active areas including the first active area212A and the second active area212B. Then, dummy gate patterns222are formed on the substrate210in the first region I and the second region II. In some embodiments, the first region I and the second region II are divided by the isolation layer (not shown) formed of any one selected from an oxide layer, a nitride layer, or a combination thereof. In some embodiments, the first region I is the NMOS region, and the second region II is the PMOS region. In one or more embodiments, the substrate210is formed of silicon, and the dummy gate patterns222are formed of polysilicon, although neither of the substrate210and the dummy gate patterns222is particularly limited thereto.

The insulating spacers224are formed to cover sidewalls of each of the dummy gate patterns222. In some embodiments, the insulating spacers224are formed of an oxide layer, a nitride layer, or a combination thereof.

In some embodiments, before the insulating spacers224are formed, first ion implantation processes are performed to form the first LDD regions214A and the second LDD regions214B in the first active area212A and the second active area212B, respectively, by using the dummy gate patterns222as first ion implantation masks. After the insulating spacers224are formed, second ion implantation processes are performed on the first active area212A and the second active area212B, respectively, by using the dummy gate patterns222and the insulating spacers224as second ion implantation masks. Additionally, an annealing process is performed to form the first source/drain regions216A and the second source/drain regions216B in the first active area212A and the second active area212B, respectively. During the first and second ion implantation processes, N-type dopant ions are implanted in the first region I in order to form N-type LDD regions and N-type source/drain regions as the first LDD regions214A and the first source/drain regions216A, respectively. Additionally, during the first and second ion implantation processes, P-type dopant ions are implanted in the second region II, in order to form P-type LDD regions and P-type source/drain regions as the second LDD regions214B and the second source/drain regions216B, respectively.

Then, the insulating patterns226are formed in each of a plurality of spaces defined by the insulating spacers224between each of the dummy gate patterns222. In some embodiments, the insulating patterns226are formed of silicon oxide or insulating material having a low dielectric constant. In order to form the insulating patterns226, an insulating material is deposited on the substrate210so as to have a thickness sufficient to fill the plurality of spaces defined by the insulating spacers224between each of the dummy gate patterns222, and then a planarization process, such as chemical mechanical polishing (CMP), may be performed thereon until top surfaces of the dummy gate patterns222are exposed.

Referring toFIG. 3B, the dummy gate patterns222are removed from the first region I and the second region II, so that the first active area212A and the second active area212B of the substrate210are exposed through the first gate trench228A and the second gate trench228B, respectively. In some embodiments, the dummy gate patterns222are removed by using a wet etching process.

Referring toFIG. 3C, the gate dielectric layer230is formed to conformally cover the top surfaces of the first and second active areas212A and212B and the sidewalls of the inter-layer dielectric pattern220exposed through the first and second gate trenches228A and228B, respectively. Then, the capping layer232and the barrier layer240are sequentially formed on the gate dielectric layer230.

In one or more embodiments, the gate dielectric layer230is formed to have a stack structure of an interfacial dielectric layer, such as a SiO2layer, and a high-k material layer overlying the interfacial dielectric layer. In some embodiments, the gate dielectric layer230is formed by a thermal oxidation process, an atomic layer deposition (ALD) process, a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, or combinations thereof. In some embodiments, the gate dielectric layer230is formed to have a thickness in the range of about 1 to 4 nm.

In one or more embodiments, the capping layer232is formed to include at least one of metal nitrides such as TiN and TaN, metal carbides such as TaC, and combinations thereof. In some embodiments, the capping layer232is formed by an ALD process, a CVD process, a PVD process, or combinations thereof. In some embodiments, the capping layer232is formed to have a thickness in the range of about 1 to 5 nm.

In one or more embodiments, the barrier layer240is formed to comprise at least one conductive barrier material selected from metals or metal nitrides. In some embodiments, the barrier layer240includes at least one conductive barrier material selected from TiN, TaN, TaC, or WN, but is not limited by the above-mentioned materials. In some embodiments, the barrier layer240is formed by an ALD process, a CVD process, a PVD process, or combinations thereof. In some embodiments, the barrier layer240is formed to have a thickness in the range of about 1 to 5 nm.

Referring toFIG. 3D, the first work function layer252A is formed on the barrier layer240in the first region I. In the case of forming an NMOS transistor in the first region I, the first work function layer252A is formed to comprise at least one of Ti, Al, or TiAl. In some embodiments for forming the first work function layer252A in the first region I, blanket deposition of metallic material for forming a first metallic layer is performed on the entire exposed top surface of the resultant structure on which the barrier layer240is formed. Then, an unnecessary portion of the first metallic layer is removed from the substrate210by using a suitable etch mask layer (not shown) covering a portion of the first metallic layer to leave the first work function layer252A resulting from the portion of the first metallic layer in the first region I. In some embodiments, the first work function layer252A is formed by an ALD process, a CVD process, a PVD process, or combinations thereof. In some embodiments, the first work function layer252A is formed to have a thickness in the range of about 1 to 10 nm.

Referring toFIG. 3E, the second work function layer252B is formed on the barrier layer240in the second region II. In the case of forming a PMOS transistor in the second region II, the second work function layer252B is formed to comprise at least one of TiN, Co, WN, or TaC. In some embodiments for forming the second work function layer252B in the second region II, blanket deposition for forming a second metallic layer is performed on the entire exposed top surface of the resultant structure on which the first work function layer252A and the barrier layer240are exposed in the first region I and the second region II, respectively. Then, an unnecessary portion of the second metallic layer is removed from the substrate210by using a suitable etch mask layer (not shown) covering a portion of the second metallic layer to leave the second work function layer252B resulting from the portion of the second metallic layer in the second region II. In some embodiments, the second work function layer252B is formed by an ALD process, a CVD process, a PVD process, or combinations thereof. In some embodiments, the second work function layer252B is formed to have a thickness in the range of about 1 to 10 nm.

In the exemplified embodiment described above with reference toFIGS. 3D and 3E, the first work function layer252A is formed before the formation of the second work function layer252B. However, the first work function layer252A may be formed after the formation of the second work function layer252B, in accordance with the spirit and scope of embodiment of the disclosure.

Referring toFIG. 3F, the metal diffusion blocking layer254is formed on the first work function layer252A and the second work function layer252B in the first region I and the second region II. The metal diffusion blocking layer254is formed to have the stack structure of the first metal nitride layer254A and the second metal nitride layer254B. In some embodiments, the metal diffusion blocking layer254is formed to have a stack structure of a TiN layer and a Ti-rich TiN layer as the stack structure of the first metal nitride layer254A and the second metal nitride layer254B. Alternatively, the metal diffusion blocking layer254is formed to have a stack structure of a TiN layer and a TaN layer as the stack structure of the first metal nitride layer254A and the second metal nitride layer254B. In some embodiments, each of the first metal nitride layer254A and the second metal nitride layer254B of the metal diffusion blocking layer254is formed by an ALD process, a CVD process, a PVD process, or combinations thereof. In some embodiments, each of the first metal nitride layer254A and the second metal nitride layer254B of the metal diffusion blocking layer254is formed to have thicknesses in the range of about 1 to 5 nm.

Referring toFIG. 3G, the wetting layer256is formed on the metal diffusion blocking layer254in the first region I and the second region II. The wetting layer256is formed to include at least one of Co, Ti, or Ta. In one or more embodiments, the wetting layer256is formed by a CVD process, although not particularly limited thereto. In some embodiments, the wetting layer256is formed to have a thickness in the range of about 1 to 5 nm.

Referring toFIG. 3H, a metal filling layer258P is formed to have a thickness sufficient to fill the first gate trench228A and the second gate trench228B on the wetting layer256in the first region I and the second region II. In some embodiments, the metal filling layer258P is formed to comprise at least one of Al, Cu, or AlCu, but is not limited by the above-mentioned materials. In some embodiments, the metal filling layer258P is formed by a PVD process, although not particularly limited thereto. After the remainder of the first gate trench228A and the second gate trench228B is filled with the metal filling layer258P on the wetting layer256, the resultant structure having the metal filling layer258P is thermally treated at a temperature sufficiently high enough to cause reflow of the metal filling layer258P, for example at a temperature of about 300-600° C. By the reflow process as described above, materials of the metal filling layer258P can flow within the first gate trench228A and the second gate trench228B, thereby promoting complete filling of the first gate trench228A and the second gate trench228B without voids.

Referring toFIG. 3I, the resultant structure ofFIG. 3His planarized by using a CMP process until a top surface of the inter-layer dielectric pattern220is exposed in the first region I and the second region II, to form the metal filling lines258resulting from portions of the metal filling layer258P within the first gate trench228A and the second gate trench228B, respectively.

According to one or more embodiments described with reference toFIGS. 3A through 3I, in forming the first and second metal gate electrode stacks250A and250B, the metal diffusion blocking layer254, the wetting layer256, and the metal filling line258are sequentially formed over the gate dielectric layer230within the first and second gate trenches228A and228B, respectively. The stack structure of the metal diffusion blocking layer254and the wetting layer256formed to cover the sidewalls258SW and the bottom surfaces258BT of the metal filling line258can inhibit diffusion of metal ions from the metal filling line258, thereby inhibiting the formation of the undesirable voids in the first and second metal gate electrode stacks250A and250B.

According to some embodiments, a semiconductor device comprises a substrate, a gate dielectric layer on the substrate, and a gate electrode stack on the gate dielectric layer. The gate electrode stack includes a metal filling line, a wetting layer, a metal diffusion blocking layer, and a work function layer. The wetting layer is in contact with a sidewall and a bottom surface of the metal filling line. The metal diffusion blocking layer is in contact with the wetting layer and covers the sidewall and the bottom surface of the metal filling line with the wetting layer therebetween. The work function layer covers the sidewall and the bottom surface of the metal filling line with the wetting layer and the metal diffusion blocking layer therebetween.

According to some embodiments, a semiconductor device comprises a substrate having a first active area and a second active area, an inter-layer dielectric pattern defining a first gate trench on the first active area and a second gate trench on the second active area, and a first MOS transistor including a first gate electrode stack within the first gate trench. The first gate electrode stack includes a first metal filling line, a first wetting layer, a first metal diffusion blocking layer, and a first work function layer. The first wetting layer is in contact with a sidewall and a bottom surface of the first metal filling line. The first metal diffusion blocking layer is in contact with the first wetting layer and covers the sidewall and the bottom surface of the first metal filling line with the first wetting layer therebetween. The first work function layer covers the sidewall and the bottom surface of the first metal filling line with the first wetting layer and the first metal diffusion blocking layer therebetween.

According to some embodiments, a method of manufacturing a semiconductor device comprises forming an inter-layer dielectric pattern on a substrate having a first active area and a second active area. The inter-layer dielectric pattern is formed to define gate trenches through which the first active area or the second active area is exposed. A gate dielectric layer is formed on the first and second active areas and on surfaces of the inter-layer dielectric pattern within the gate trenches. Gate electrode stacks are formed to fill the gate trenches on the gate dielectric layer. In order to form the gate electrode stacks, a first work function layer is formed over the gate dielectric layer formed on the first active area. A metal diffusion blocking layer is formed on the first work function layer. A wetting layer is formed on the metal diffusion blocking layer. A metal filling layer is formed on the wetting layer.

While the present disclosure has been particularly shown and described with reference to example embodiments thereof, a skilled person in the art will appreciate that there can be many embodiment variations of this disclosure. Although the embodiments and their features have been described in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the embodiments.

The above method embodiment shows exemplary steps, but they are not necessarily required to be performed in the order shown. Steps may be added, replaced, changed order, and/or eliminated as appropriate, in accordance with the spirit and scope of embodiment of the disclosure. Embodiments that combine different claims and/or different embodiments are within scope of the disclosure and will be apparent to those skilled in the art after reviewing this disclosure.