Stacked amplifier with diode-based biasing

Techniques for improving linearity of amplifiers are described. In an exemplary design, an amplifier (e.g., a power amplifier) may include a plurality of transistors coupled in a stack and at least one diode. The plurality of transistors may receive and amplify an input signal and provide an output signal. The at least one diode may be operatively coupled to at least one transistor in the stack. Each diode may provide a variable bias voltage to an associated transistor in the stack. Each diode may have a lower voltage drop across the diode at high input power and may provide a higher bias voltage to the associated transistor at high input power. The at least one transistor may have higher gain at high input power due to the higher bias voltage from the at least one diode. The higher gain may improve the linearity of the amplifier.

BACKGROUND

The present disclosure relates generally to electronics, and more specifically to amplifiers.

Amplifiers are commonly used in various electronic devices to provide signal amplification. Different types of amplifiers are available for different uses. For example, a wireless communication device such as a cellular phone may include a transmitter and a receiver for bi-directional communication. The transmitter may include a driver amplifier (DA) and a power amplifier (PA), the receiver may include a low noise amplifier (LNA), and the transmitter and receiver may include variable gain amplifiers (VGAs).

Linearity is an important design goal for a power amplifier. The power amplifier may be designed to meet linearity requirements by using sufficiently large transistors and applying appropriate biasing. The power amplifier may have extra margin in linearity, which may then be used to boost efficiency of the power amplifier and reduce current consumption. Extra linearity margin may also be used to reduce transistor size and may lead to saving of chip area as well as cost. A power amplifier with good linearity may thus be highly desirable.

DETAILED DESCRIPTION

The detailed description set forth below is intended as a description of exemplary designs of the present disclosure and is not intended to represent the only designs in which the present disclosure can be practiced. The term “exemplary” is used herein to mean “serving as an example, instance, or illustration.” Any design described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other designs. The detailed description includes specific details for the purpose of providing a thorough understanding of the exemplary designs of the present disclosure. It will be apparent to those skilled in the art that the exemplary designs described herein may be practiced without these specific details. In some instances, well-known structures and devices are shown in block diagram form in order to avoid obscuring the novelty of the exemplary designs presented herein.

Techniques for improving the linearity of amplifiers are described herein. The techniques may be used for various types of amplifiers such as power amplifiers, driver amplifiers, LNAs, VGAs, etc. The techniques may also be used for amplifiers in various electronic devices such as wireless communication devices, cellular phones, personal digital assistants (PDAs), handheld devices, wireless modems, laptop computers, cordless phones, Bluetooth devices, consumer electronic devices, etc. For clarity, the use of the techniques for amplifiers in a wireless communication device is described below.

FIG. 1shows a block diagram of an exemplary design of a wireless communication device100. In this exemplary design, wireless device100includes a data processor110and a transceiver120. Transceiver120includes a transmitter130and a receiver150that support bi-directional wireless communication. In general, wireless device100may include any number of transmitters and any number of receivers for any number of communication systems and any number of frequency bands.

In the transmit path, data processor110processes data to be transmitted and provides an analog output signal to transmitter130. Within transmitter130, the analog output signal is amplified by an amplifier (Amp)132, filtered by a lowpass filter134to remove images caused by digital-to-analog conversion, amplified by a VGA136, and upconverted from baseband to radio frequency (RF) by a mixer138. The upconverted signal is filtered by a filter140, further amplified by a driver amplifier142and a power amplifier144, routed through switches/duplexers146, and transmitted via an antenna148.

In the receive path, antenna148receives signals from base stations and/or other transmitter stations and provides a received signal, which is routed through switches/duplexers146and provided to receiver150. Within receiver150, the received signal is amplified by an LNA152, filtered by a bandpass filter154, and downconverted from RF to baseband by a mixer156. The downconverted signal is amplified by a VGA158, filtered by a lowpass filter160, and amplified by an amplifier162to obtain an analog input signal, which is provided to data processor110.

FIG. 1shows transmitter130and receiver150implementing a direct-conversion architecture, which frequency converts a signal between RF and baseband in one stage. Transmitter130and/or receiver150may also implement a super-heterodyne architecture, which frequency converts a signal between RF and baseband in multiple stages. A local oscillator (LO) generator170generates and provides transmit and receive LO signals to mixers138and156, respectively. A phase locked loop (PLL)172receives control information from data processor110and provides control signals to LO generator170to generate the transmit and receive LO signals at the proper frequencies.

FIG. 1shows an exemplary transceiver design. In general, the conditioning of the signals in transmitter130and receiver150may be performed by one or more stages of amplifier, filter, mixer, etc. These circuits may be arranged differently from the configuration shown inFIG. 1. Furthermore, other circuits not shown inFIG. 1may also be used in the transmitter and receiver. For example, matching circuits may be used to match various active circuits inFIG. 1. Some circuits inFIG. 1may also be omitted. All or a portion of transceiver120may be implemented on one or more analog integrated circuits (ICs), RF ICs (RFICs), mixed-signal ICs, etc. For example, amplifier132through power amplifier144in transmitter130may be implemented on an RFIC. Driver amplifier142and power amplifier144may also be implemented on another IC external to the RFIC.

Data processor110may perform various functions for wireless device100, e.g., processing for transmitted and received data. A memory112may store program codes and data for data processor110. Data processor110may be implemented on one or more application specific integrated circuits (ASICs) and/or other ICs.

The techniques for improving the linearity of amplifiers described herein may be used for various types of amplifiers, such as the amplifiers shown inFIG. 1. For clarity, much of the description below covers improving the linearity of a power amplifier, e.g., power amplifier144inFIG. 1. The techniques can vary the biasing of the power amplifier to improve linearity when needed at high input RF power.

FIG. 2shows a schematic diagram of an exemplary design of a power amplifier200implemented with stacked transistors. In the exemplary design shown inFIG. 2, power amplifier200is implemented with three N-channel metal oxide semiconductor (NMOS) transistors212,214and216coupled in a stack. NMOS transistor212has its gate coupled to one end of a resistor232and its source coupled to circuit ground. NMOS transistor214has its gate coupled to one end of a resistor234and its source coupled to the drain of NMOS transistor212. NMOS transistor216has its gate coupled to one end of a resistor236, its source coupled to the drain of NMOS transistor214, and its drain providing an output RF signal (RFout). The other end of resistors232,234and236are coupled to nodes A, B and C, respectively. A capacitor224is coupled between the gate of NMOS transistor214and circuit ground. A capacitor226is coupled between the gate of NMOS transistor216and circuit ground. A load218is coupled between a power supply (Vdd) and the drain of NMOS transistor216. Load218may include an inductor, a capacitor, an MOS transistor, and/or other circuits. An AC-coupling capacitor222has one end receiving an input RF signal (RFin) and the other end coupled to the gate of NMOS transistor212.

A bias circuit250generates bias voltages for NMOS transistors212,214and216. In the exemplary design shown inFIG. 2, bias circuit250includes a resistor ladder formed by four resistors252,254,256and258coupled in series and between Vdd and circuit ground. The top end of resistor252is coupled to node A and provides a first bias voltage (Vbias1). The top end of resistor254is coupled to node B and provides a second bias voltage (Vbias2). The top end of resistor256is coupled to node C and provides a third bias voltage (Vbias3). Capacitors262,264and266have one end coupled to nodes A, B and C, respectively, and the other end coupled to circuit ground.

NMOS transistor212is a gain transistor that provides signal amplification for the RFin signal. NMOS transistors214and216provide signal amplification as well as signal drive for the RFout signal. Improved reliability may be achieved by using multiple NMOS transistors coupled in a stack. The RFout signal may have a large voltage swing, which may exceed a breakdown voltage of each NMOS transistor. The voltage swing of the RFout signal may be split or distributed approximately equally across NMOS transistors212,214and216. Each NMOS transistor may then observe only a fraction of the voltage swing, which should be less than the breakdown voltage of the NMOS transistor in order to achieve good reliability. The use of stacked transistors is especially desirable for high frequency amplifiers implemented with transistors fabricated with deep sub-micron IC processes and having low breakdown voltages. The stacked transistors can essentially multiply the breakdown voltage to improve reliability.

Resistors232,234and236provide isolation for NMOS transistors212,214and216, respectively. Resistors232,234and236prevent too much RF signal from leaking from NMOS transistors212,214and216to bias circuit250, which may then cause a drop in the gain of power amplifier200. Resistors232,234and236may have fixed values (as shown inFIG. 2) or may have adjustable values (not shown inFIG. 2). In either case, the values of resistors232,234and236may be selected to provide the desired amount of isolation between NMOS transistors212,214and216and bias circuit250. Capacitors224and226provide the proper RF signal strength at the gates of NMOS transistors214and216, respectively.

Bias circuit250generates appropriate bias voltages for NMOS transistors212,214and216. Resistors252,254,256and258may be selected to obtain the desired Vbias1, Vbias2and Vbias3voltages for NMOS transistors212,214and216, respectively, e.g., to obtain the desired gain for the NMOS transistors and to achieve the desired voltage splitting across the NMOS transistors. Capacitors262,264and266provide low RF impedance looking into bias circuit250from the gates of NMOS transistors212,214and216, respectively. The sizes of capacitors262,264and266may be selected to provide the desired impedance for the leaked RF signals from NMOS transistors212,214and216.

FIG. 2shows an exemplary design of bias circuit250implementing a resistor ladder to generate bias voltages for the NMOS transistors in power amplifier200. A bias circuit may also be implemented with other exemplary designs that can generate the desired bias voltages for a power amplifier.

FIG. 2shows an exemplary design of power amplifier200with three NMOS transistors coupled in a stack. In general, a power amplifier may be implemented with any number of NMOS transistors coupled in a stack. The number of NMOS transistors to couple in a stack may be determined based on the expected maximum voltage swing of the RFout signal, the breakdown voltage of each NMOS transistor, and/or other factors.

Power amplifier200may be able to handle a large RFout signal using NMOS transistors having a small breakdown voltage. However, power amplifier200may have relatively poor linearity performance under certain operating scenarios. The gain of NMOS transistor212typically decreases at high input RF power. The lower gain of NMOS transistor212may result in worse linearity for power amplifier200at high input RF power, which may be undesirable.

FIG. 3shows a schematic diagram of an exemplary design of a power amplifier202implemented with stacked transistors and having diode-based biasing for the gain transistor. Power amplifier202includes NMOS transistors212,214and216, load218, capacitors222,224and226, resistors232,234and236, and bias circuit250, which are coupled as described above for power amplifier200inFIG. 2. Power amplifier202further includes an NMOS transistor242coupled in a diode configuration. NMOS transistor242has its gate coupled to its drain and its drain coupled to node A. Resistor232has one end coupled to the gate of NMOS transistor212and the other end coupled to the source of NMOS transistor242. NMOS transistor242may be implemented with a symmetric structure, and the source and drain of NMOS242transistor may be interchangeable.

Diode-connected NMOS transistor242has a gate-to-source voltage of Vgs_diode1. The voltage drop across resistor232may be negligible. A gate voltage (Vg1) of NMOS transistor212may then be expressed as:
Vg1=Vbias1−Vgs—diode1.  Eq (1)

The Vgs_diode1voltage of diode-connected NMOS transistor242is dependent on input RF power. The amount of RF current that leaks from NMOS transistor212to bias circuit250is dependent on (e.g., is proportional to) the input RF power. When the input RF power is high, diode-connected NMOS transistor242rectifies the RF current that leaks from NMOS transistor212to bias circuit250. The rectified RF current results in a smaller Vgs_diode1voltage as the input RF power is increased. The Vbias1voltage may be a fixed voltage. In this case, a decrease in the Vgs_diode1voltage would result in an increase in the Vg1voltage. Since the Vg1voltage is equal to a gate-to-source (Vgs) voltage of NMOS transistor212, the higher Vg1voltage increases the Vgs voltage and hence the gain of NMOS transistor212at high input RF power. The higher gain may improve the linearity of power amplifier202.

FIG. 4shows a schematic diagram of an exemplary design of a power amplifier204implemented with stacked transistors and having diode-based biasing for each transistor in the stack. Power amplifier204includes all of the circuit components in power amplifier202inFIG. 3. Power amplifier204further includes NMOS transistors244and246, each of which is coupled in a diode configuration. NMOS transistor244has its gate coupled to its drain and its drain coupled to node B. Resistor234has one end coupled to the gate of NMOS transistor214and the other end coupled to the source of NMOS transistor244. Similarly, NMOS transistor246has its gate coupled to its drain and its drain coupled to node C. Resistor236has one end coupled to the gate of NMOS transistor216and the other end coupled to the source of NMOS transistor246.

Bias circuit250may provide fixed Vbias1, Vbias2and Vbias3voltages. Diode-connected NMOS transistors242,244and246may have Vgs voltages of Vgs_diode1, Vgs_diode2and Vgs_diode3, respectively, which may be variable and dependent on the input RF power. NMOS transistors212,214and216have gate voltages of Vg1, Vg2and Vg3, respectively, which may be variable and dependent on (i) the Vbias1, Vbias2and Vbias3voltages from bias circuit250and (ii) the Vgs_diode1, Vgs_diode2and Vgs_diode3voltages of diode-connected NMOS transistors242,244and246. The Vg voltage of each NMOS transistor may be determined based on the Vbias voltage and the Vgs_diode voltage applicable for that NMOS transistor, as shown in equation (1). The Vg voltage of each NMOS transistor may increase at high input RF power, which may improve the gain of that NMOS transistor. The higher gains for NMOS transistors212,214and216may improve the linearity of power amplifier204.

The improvement in linearity of power amplifiers202and204with the use of diode-based biasing may be quantified by various metrics such as adjacent channel power ratio (ACPR). Computer simulation indicates that ACPR improves for a Code Division Multiple Access (CDMA) signal when diode-based biasing is employed, as shown inFIG. 7.

FIG. 5Ashows plots of the Vgs voltage of NMOS transistor212with and without diode-based biasing. The effect of diode-based biasing is stronger when applied to three NMOS transistors inFIG. 4instead of only one NMOS transistor inFIG. 3. InFIG. 5A, the horizontal axis denotes input RF power of the RFin signal and is given in units of dBm. The vertical axis denotes the Vgs voltage of NMOS transistor212and is given in units of Volts (V). A plot510shows the Vgs voltage of NMOS transistor212inFIG. 2without diode-based biasing. A plot512shows the Vgs voltage of NMOS transistor212inFIG. 4with diode-based biasing provided by diode-connected NMOS transistor242. As shown inFIG. 5A, the Vgs voltage of NMOS transistor212is relatively constant without diode-based biasing and increases with input RF power when diode-based biasing is used.

FIG. 5Bshows plots of the gain of NMOS transistor212with and without diode-based biasing. InFIG. 5B, the horizontal axis denotes input RF power and is given in units of dBm. The vertical axis denotes the gain of NMOS transistor212and is given in units of decibel (dB). A plot520shows the gain of NMOS transistor212inFIG. 2without diode-based biasing. A plot522shows the gain of NMOS transistor212inFIG. 4with diode-based biasing provided by diode-connected NMOS transistor242. As shown inFIG. 5B, the gain of NMOS transistor212drops off at high input RF power without diode-based biasing and peaks slightly at high input RF power with diode-based biasing.

Diode-connected NMOS transistor242can increase the Vgs voltage of NMOS transistor212at high input RF power, as shown inFIG. 5A. The size of NMOS transistor242may be smaller than the size of NMOS transistor212and may be selected to obtain the desired increase in the Vgs voltage of NMOS transistor212at high input RF power. The smaller size of NMOS transistor242may prevent the Vgs voltage of NMOS transistor242from increasing and the Vgs voltage of NMOS transistor212from decreasing at low input RF power. For a given amount of change in RF current, the change in the Vgs voltage of NMOS transistor242may be much larger than that of NMOS transistor212. Multiple diode-connected NMOS transistors may also be coupled in series to further increase the Vgs voltage of NMOS transistor212at high input RF power.

The size of capacitor262and the size of diode-connected NMOS transistors242may be selected together. In general, a larger capacitor262may be selected for a smaller NMOS transistor242, and vice versa.

FIG. 6shows a schematic diagram of an exemplary design of a power amplifier206implemented with stacked transistors and having diode-based biasing. Power amplifier206includes all of the circuit components in power amplifier204inFIG. 4, with the following differences. Power amplifier206includes variable resistors632,634and636in place of fixed resistors232,234and236inFIG. 4. Power amplifier206further includes variable resistors652,654,656and658in place of fixed resistors252,254,256and258in bias circuit250inFIG. 4.

Variable resistors652,654,656and658may be adjusted to obtain the desired bias voltages for NMOS transistors212,214and216, e.g., to account for variations in IC process, temperature, power supply voltage, etc. Variable resistors632,634and636may be adjusted (e.g., individually) to vary the extent of gain improvement of each NMOS transistor due to the associated diode-connected NMOS transistor. This may improve the overall gain and linearity of power amplifier206.

FIGS. 3,4and6show exemplary designs of power amplifiers with three NMOS transistors coupled in a stack. In general, the techniques described herein may be used for amplifiers with any number of transistors (e.g., two, three, four, or more transistors) coupled in a stack. Diode-based biasing may be used for at least one transistor in the stack. For example, diode-based biasing may be used for only the gain transistor in the stack (e.g., as shown inFIG. 3) or for each transistor in the stack (e.g., as shown inFIG. 4).

FIGS. 3,4and6show exemplary designs in which diode-connected NMOS transistors are used for diode-based biasing. In other exemplary designs, diode-connected P-channel metal oxide semiconductor (PMOS) transistors may be used for diode-based biasing. For example, inFIG. 3, diode-connected NMOS transistor242may be replaced with a diode-connected PMOS transistor having its source coupled to node A and its gate and drain coupled to resistor232. In some other exemplary designs, pin diodes may be used for diode-based biasing. For example, inFIG. 3, diode-connected NMOS transistor242may be replaced with a pin diode having its anode coupled to node A and its cathode coupled to resistor232. Diode-based biasing may also be implemented with other circuit components.

FIGS. 3,4and6show exemplary designs of power amplifiers implemented with NMOS transistors. In general, the techniques described herein may be used for amplifiers implemented with transistors of various types. For example, diode-based biasing may be used for amplifiers implemented with PMOS transistors, bipolar junction transistors (BJTs), heterojunction bipolar transistors (HBTs), high electron mobility transistors (HEMTs), gallium arsenide (GaAs) transistors, etc. The techniques may also be used for amplifiers fabricated with various IC process technologies such as complementary metal oxide semiconductor (CMOS), silicon-on-insulator (SOI), etc.

Amplifiers implemented with stacked transistors and having diode-based biasing (e.g., as shown inFIGS. 3,4and6) may have certain advantages over other amplifiers. Diode-based biasing can provide linearization based on an analog circuit that is simple and useful. Diode-based biasing can increase the DC bias voltage and increase the RF gain at high input RF power for each transistor in the stack having a diode in its DC biasing path. Diode-based biasing may significantly improve linearity of the amplifiers, which may provide other benefits described above.

Diode-based biasing may improve linearity while reducing current consumption. An amplifier may be biased with more current to obtain higher gain and better linearity. However, the amplifier would consume more bias current all the time, even when higher gain is not needed, e.g., at low input RF power. Diode-based biasing allows the gain to be increased dynamically with high input RF power, so that more bias current is used only when needed for high input RF power.

FIG. 7shows plots of linearity performance of a power amplifier with and without diode-based biasing. InFIG. 7, the horizontal axis denotes output power level (Pout), which is given in units of dBm. The vertical axis denotes ACPR, which is given in units of dBc/30 kHz. A plot710shows ACPR of the power amplifier without diode-based biasing. A plot720shows ACPR of the power amplifier with diode-based biasing. As shown inFIG. 7, ACPR may be improved across all output power levels by use of diode-based biasing.

A power amplifier with diode-based biasing may be advantageously used under several scenarios. First, the power amplifier may be used to improve ACPR or linearity without sacrificing efficiency. For example, at an output power level of 23 dBm inFIG. 7, ACPR may be about −50 dBc/30 kHz without diode-based biasing and about −52 dBc/30 kHz with diode-based biasing. Efficiency may be about the same for both cases since the output power level is the same. However, better ACPR may be obtained with diode-based biasing. Second, the power amplifier may be used to achieve the same ACPR or linearity with better efficiency. For example, at an ACPR level of −50 dBc/30 kHz inFIG. 7, the output power level may be about 23 dBm without diode-based biasing and about 23.5 dBm with diode-based biasing. Efficiency is typically higher for higher output power level. The power amplifier may be designed based on a tradeoff between linearity and efficiency. Once the power amplifier is designed, it may be operated to obtain the desired output power level. Linearity and efficiency of the power amplifier at this output power level may then be dependent on the design of the power amplifier.

In an exemplary design, an apparatus (e.g., a wireless device, an integrated circuit, etc.) may comprise an amplifier (e.g., a power amplifier). The amplifier may comprise a plurality of transistors (e.g., NMOS transistors212,214and216inFIG. 3or4) coupled in a stack and at least one diode (e.g., diode-connected NMOS transistor242inFIG. 3or diode-connected NMOS transistors242,244and246inFIG. 4). The plurality of transistors may receive and amplify an input signal and provide an output signal. The at least one diode may be operatively (e.g., indirectly) coupled to at least one transistor in the stack. Each diode may provide a variable bias voltage (e.g., Vg1inFIG. 3) to an associated transistor in the stack.

In an exemplary design, a single diode may be operatively coupled to a single transistor in the stack, e.g., as shown inFIG. 3. The single transistor may be a gain transistor that receives the input signal and provides signal gain for the input signal. In another exemplary design, one diode may be operatively coupled to each transistor in the stack, e.g., as shown inFIG. 4. In general, one or more diodes may be operatively coupled to all or a subset of the transistors in the stack. In any case, each diode may have a lower voltage drop across the diode at high input power and may provide a higher bias voltage to the associated transistor at high input power. The at least one transistor operatively coupled to the at least one diode may have higher gain at high input power due to the higher bias voltage from the at least one diode.

The amplifier may further comprise at least one resistor (e.g., resistors232,234and236) coupled between the at least one transistor in the stack and the at least one diode. Each resistor may be a fixed resistor (e.g., as shown inFIGS. 3 and 4) or a variable resistor (e.g., as shown inFIG. 6).

The amplifier may further comprise a plurality of resistors (e.g., resistors252to258inFIGS. 3 and 4) coupled in a ladder. The plurality of resistors may provide a plurality of bias voltages (e.g., Vbias1, Vbias2and Vbias3) for the plurality of transistors in the stack. The at least one diode may be coupled to at least one resistor in the ladder. The plurality of resistors may comprise at least one variable resistor to provide adjustable bias voltages, e.g., to account for variations in IC process, temperature, power supply, etc. The amplifier may further comprise a plurality of capacitors (e.g., capacitors262,264and266inFIGS. 3 and 4) coupled to the plurality of resistors in the ladder. Each capacitor may provide low impedance looking from the gate of an associated transistor in the stack.

In an exemplary design, the plurality of transistors may comprise MOS transistors, e.g., NMOS transistors as shown inFIGS. 3 and 4or PMOS transistors. The a plurality of transistors may also be implemented with transistors of other types. In an exemplary design, the at least one diode may comprise at least one NMOS transistor, each coupled as a diode. The at least one diode may also be implemented with diodes of other types.

In an exemplary design, an integrated circuit may comprise an amplifier (e.g., a power amplifier). The amplifier may comprise a plurality of MOS transistors coupled in a stack and at least one diode-connected MOS transistor. The plurality of MOS transistors may receive and amplify an input signal and provide an output signal. The at least one diode-connected MOS transistor may be operatively coupled to at least one MOS transistor in the stack. Each diode-connected MOS transistor may provide a variable bias voltage to an associated MOS transistor in the stack. In an exemplary design, a single diode-connected MOS transistor may be operatively coupled to a single MOS transistor (e.g., the gain MOS transistor) in the stack, e.g., as shown inFIG. 3. In another exemplary design, one diode-connected MOS transistor may be operatively coupled to each MOS transistor in the stack, e.g., as shown inFIG. 4. The amplifier may further comprise at least one resistor coupled between the at least one diode-connected MOS transistor and the at least one MOS transistor in the stack.

FIG. 8shows an exemplary design of a process800for amplifying a signal. An input signal may be amplified with a plurality of transistors coupled in a stack to obtain an output signal (block812). A plurality of bias voltages for the plurality of transistors in the stack may be generated, e.g., with a plurality of resistors coupled in a ladder (block814). At least one variable bias voltage for at least one transistor in the stack may be generated based on at least one diode (block816). In an exemplary design, a single variable bias voltage for a single transistor in the stack may be generated based on a single diode and a fixed bias voltage from the resistor ladder. In another exemplary design, a plurality of variable bias voltages for the plurality of transistors in the stack may be generated based on a plurality of diodes, one variable bias voltage for each transistor in the stack. Leakage from the at least one transistor in the stack may be controlled (e.g., reduced) with at least one resistor coupled between the at least one transistor and the at least one diode (block818).

The amplifiers described herein may be implemented on an IC, an analog IC, an RFIC, a mixed-signal IC, an ASIC, a printed circuit board (PCB), an electronic device, etc. The amplifiers may also be fabricated with various IC process technologies such as CMOS, NMOS, PMOS, BJT, bipolar-CMOS (BiCMOS), silicon germanium (SiGe), GaAs, etc.

An apparatus implementing the amplifiers described herein may be a stand-alone device or may be part of a larger device. A device may be (i) a stand-alone IC, (ii) a set of one or more ICs that may include memory ICs for storing data and/or instructions, (iii) an RFIC such as an RF receiver (RFR) or an RF transmitter/receiver (RTR), (iv) an ASIC such as a mobile station modem (MSM), (v) a module that may be embedded within other devices, (vi) a receiver, cellular phone, wireless device, handset, or mobile unit, (vii) etc.