Semiconductor device

A semiconductor device is disclosed. The semiconductor device includes: a substrate; a metal-oxide semiconductor (MOS) transistor disposed in the substrate; and a shallow trench isolation (STI) disposed in the substrate and around the MOS transistor, in which the STI comprises a stress material.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The invention relates to a semiconductor device, and more particularly, to a semiconductor device with stress-induced STI or contact plugs.

2. Description of the Prior Art

A conventional MOS transistor generally includes a semiconductor substrate, such as silicon, a source region, a drain region, a channel positioned between the source region and the drain region, and a gate located above the channel. The gate is composed of a gate dielectric layer, a gate conductive layer positioned on the gate dielectric layer, and a plurality of spacers positioned on the sidewalls of the gate conductive layer. Generally, for a given electric field across the channel of a MOS transistor, the amount of current that flows through the channel is directly proportional to a mobility of the carriers in the channel. Therefore, how to improve the carrier mobility so as to increase the speed performance of MOS transistors has become a major topic for study in the semiconductor field.

The formation of SiGe source/drain regions is commonly achieved by epitaxially growing a SiGe layer adjacent to the spacers within the semiconductor substrate after forming the spacer. In this type of MOS transistor, a biaxial tensile strain occurs in the epitaxial silicon layer due to the silicon germanium, which has a larger lattice constant than silicon, and, as a result, the band structure alters, and the carrier mobility increases. This enhances the speed performance of the MOS transistor.

In addition to the application of epitaxial layer, as the semiconductor processes advance, how to increase the driving current for metal oxide semiconductor (MOS) transistors for fabrication processes under 65 nanometer has become an important topic. According to this trend, the utilization of high stress films for increasing the driving current of MOS transistors has become increasingly popular. Currently, the utilization of high stress films to increase the driving current of MOS transistors is divided into two categories: one being a poly stressor formed before the formation of nickel silicides and the other being a contact etch stop layer (CESL) formed after the formation of the nickel silicides.

However, as current approach of either using epitaxial layer or stress films to increase the mobility of carrier in the channel regions of transistor has reached a bottleneck, how to further improve the performance of current device has become an important task.

SUMMARY OF THE INVENTION

It is an objective of the present invention to provide a semiconductor device, which preferably increases the mobility of carriers in the channel region of the MOS transistor through utilization of stress-induced STI structures and contact plugs.

A semiconductor device is disclosed. The semiconductor device includes: a substrate; a metal-oxide semiconductor (MOS) transistor disposed in the substrate; and a shallow trench isolation (STI) disposed in the substrate and around the MOS transistor, in which the STI comprises a stress material.

Another aspect of the present invention provides a semiconductor device, which includes: a substrate; a metal-oxide semiconductor (MOS) transistor disposed in the substrate; a dielectric layer disposed on the substrate to cover the MOS transistor; and at least one stress plug disposed in the dielectric layer and around the MOS transistor, wherein the stress plug comprises a stress material.

Another aspect of the present invention provides a method for fabricating semiconductor device. The method includes the steps of: providing a substrate; forming a metal-oxide semiconductor (MOS) transistor in the substrate; forming a dielectric layer on the substrate to cover the MOS transistor; forming at least a contact hole in the dielectric layer and around the MOS transistor; and filling the contact hole with a stress material.

DETAILED DESCRIPTION

Referring toFIG. 1,FIG. 1illustrates a perspective view of a semiconductor device according to a preferred embodiment of the present invention. As shown inFIG. 1, a substrate10, such as a silicon substrate or a silicon-on-insulator (SOI) substrate is provided. A shallow trench isolation (STI) fabrication is then performed by first using one or more photo-etching process to form a trench12dividing or surrounding each active region, and forming a stress material14on the surface of the substrate10to fill the trench12. A planarizing process, such as a chemical mechanical polishing (CMP) process is then performed to partially remove the stress material14on the surface of the substrate10so that the surface of the stress material14in the trench12is even with the surface of the substrate10. As a result, a STI16structure filled with stress material14is formed.

According to a preferred embodiment of the present invention, the stress material14is selected from a material consisting of silicon nitride, boron nitride, silicon oxide, silicon carbide, and silicon oxynitride, in which the stress material14filled into the STI16could be a single material layer or multiple layers composed of same or different material, which are all within the scope of the present invention. Preferably, the stress of silicon nitride is between −3.5 GPa to 2.0 GPa and the stress of boron nitride is between −1 GPa to −2 GPa. As boron nitride is stable in air, vacuum, and inert gases and also being a suitable insulator with pronounced heat dissipating ability, the trench12is preferably filled with stress material such as boron nitride.

A MOS transistor fabrication is then carried out by first forming a gate structure18in the substrate10adjacent to two sides of the STI16shown inFIG. 1. The gate structure18could include a gate dielectric layer20and a gate electrode22. An offset spacer24and a main spacer26are formed on the sidewall of each gate structure18, and a lightly doped drain28and source/drain30with corresponding conductive type are formed in the substrate10adjacent to two sides of the offset spacer24and main spacer26.

Next, a selective epitaxial growth process is performed to form an epitaxial layer (not shown) in the substrate10adjacent to two sides of the main spacer26, in which the material of the epitaxial layer could be selected according to the nature of the transistor being fabricated. For instance, if the transistor being fabricated is a NMOS transistor, the epitaxial layer preferably includes SiC; if the transistor being fabricating is a PMOS transistor, the epitaxial layer preferably includes SiGe.

Next, a salicide process is performed by first forming a metal selected from a group consisting of cobalt, titanium, nickel, platinum, palladium, and molybdenum on the substrate10to cover the source/drain30and epitaxial layer, and then using at least one rapid thermal anneal process to react the metal with source/drain30and epitaxial layer for forming a silicide layer32in the substrate10adjacent to two sides of the main spacer26. The un-reacted metal is removed thereafter.

Next, a stress layer34is covered on the surface of the substrate10and gate structure18, in which the material of the stress layer34could be adjusted according to the conductivity of the transistor. For instance, if the transistor being fabricated is a NMOS transistor, the stress layer is a tensile stress layer; if the transistor being fabricated is a PMOS transistor, the stress layer is a compressive stress layer.

Next, an interlayer dielectric layer36is formed on the substrate10to cover the stress layer34, and a plurality of contact holes are formed in the interlayer dielectric layer36and the stress layer34. After the contact hole is filled with metal such as tungsten, a plurality of contact plugs38connecting the source/drain30is formed. This completes the fabrication of a semiconductor device according to a preferred embodiment of the present invention.

In this embodiment, the MOS transistors formed adjacent to two sides of the STI are preferably transistors of same conductive type, such as all NMOS transistors or all PMOS transistors. By doing so, the stress material14filled into the STI16could be utilized to provide a tensile strain for NMOS transistors disposed on two sides of the STI16or to provide a compressive strain for PMOS transistors disposed on two sides of the STI16.

Referring toFIGS. 2-3,FIG. 2illustrates a top view of a semiconductor device according to another embodiment of the present invention andFIG. 3illustrates a cross-sectional view ofFIG. 2along the sectional line AA′. As shown in the figures, a substrate60, such as silicon substrate or a SOI substrate is provided. At least an active region92is defined on the substrate60and a plurality of STIs94are disposed around the active region92, in which the STIs94could be the STI structure having stress as disclosed inFIG. 1.

Next, at least a gate structure68is formed on the substrate60, in which the gate structure68includes a gate dielectric layer70and a gate electrode72. An offset spacer74and a main spacer76are formed on the sidewall of each gate structure68, and a lightly doped drain78and source/drain70with corresponding conductive type are formed in the substrate60adjacent to two sides of the offset spacer74and main spacer76.

Next, a selective epitaxial growth process is performed to form an epitaxial layer (not shown) in the substrate60adjacent to two sides of the main spacer76, in which the material of the epitaxial layer could be selected according to the nature of the transistor being fabricated. For instance, if the transistor being fabricated is a NMOS transistor, the epitaxial layer preferably includes SiC; if the transistor being fabricating is a PMOS transistor, the epitaxial layer preferably includes SiGe.

Next, a salicide process is performed by first forming a metal selected from a group consisting of cobalt, titanium, nickel, platinum, palladium, and molybdenum on the substrate60to cover the source/drain80and epitaxial layer, and then using at least one rapid thermal anneal process to react the metal with source/drain80and epitaxial layer for forming a silicide layer82in the substrate60adjacent to two sides of the main spacer86. The un-reacted metal is removed thereafter.

Next, a stress layer84is selectively covered on the surface of the substrate60and gate structure68, in which the material of the stress layer84could be adjusted according to the conductivity of the transistor. For instance, if the transistor being fabricated is a NMOS transistor, the stress layer is a tensile stress layer; if the transistor being fabricated is a PMOS transistor, the stress layer is a compressive stress layer.

Next, an interlayer dielectric layer86is formed on the substrate60to cover the stress layer84, and one ore more etching process is conducted to form a plurality of contact holes88in the interlayer dielectric layer86and the stress layer84. After filling the contact holes88with a stress material, a plurality of stress plugs90is formed in the contact holes88. In contrast to typical contact plugs contacting the source/drain80, the stress plugs90of this embodiment are situated around the entire MOS transistor while not electrically connected to the source/drain80. As the stress plugs90are primarily used to provide stress to the channel region of the MOS transistor, the stress plugs90are extended parallel to the gate structures68, such as parallel to the width of the channel. Moreover, the MOS transistors adjacent to two sides of the stress plugs90are preferably transistors of the same conductive type, such as both being NMOS transistors or PMOS transistors. By following this design, the stress plugs90could provide a tensile stress to two adjacent NMOS transistors simultaneously or provide a compressive stress to adjacent PMOS transistors simultaneously.

According to a preferred embodiment of the present invention, the stress material filled into the contact hole88is selected from a material consisting of silicon nitride, boron nitride, silicon oxide, silicon carbide, and silicon oxynitride. In addition, the stress of silicon nitride is between −3.5 GPa to 2.0 GPa and the stress of boron nitride is between −1 GPa to −2 GPa. As boron nitride is stable in air, vacuum, and inert gases and also being a suitable insulator with pronounced heat dissipating ability, the contact holes88are preferably filled with stress material such as boron nitride.

One or more etching processes are then conducted to form a plurality of contact holes (not shown) in the interlayer dielectric layer86and stress layer84, and a conductive material is provided to fill the contact holes for forming a plurality of conductive plugs (not shown) in the contact holes. It should be noted that these conductive plugs could be disposed anywhere in the active region92for electrically connecting the source/drain80. For instance, these conductive plugs could be disposed between the gate structures68and the stress plugs90, or the stress plugs90could be disposed between the gate structures68and the conductive plugs, or even the conductive plugs be formed in the stress plugs90and penetrating the stress plug90to electrically connect to the source/drain80. Referring now toFIG. 4, which illustrates a top view of a semiconductor device having both contact plugs and stress plugs. As shown inFIG. 4, a plurality of contact plugs96could be disposed between the stress plugs90and the gate structure68. It should be noted that the position of the contact plugs96is not limited to the ones shown in the figure, but could also be placed anywhere in the active region92, such as adjacent to the ends of the stress plugs90, which are all within the scope of the present invention.

Overall, the present invention preferably fills the STI in the substrate and contact holes in the interlayer dielectric layer with stress material to form STI structures and contact plugs with capable of applying stress. By doing so, the present invention could improve the carrier mobility in the channel region of the entire MOS transistor on top of epitaxial layer and stress layer. Also, the aforementioned approach for forming STI and contact plugs with stress material could also be applied to other fabrication and devices, such as memory devices or high voltage devices. Moreover, the transistor of the present invention could include transistors with polysilicon gate or metal gate, in which the metal gate transistors could be fabricated from gate first, gate last, high-k first, or high-k last processes.