Wireless communication device

A wireless communication device including an integrated processing circuit and a first memory is provided. The integrated processing circuit includes a processing unit capable of processing a wireless communication signal and a radio frequency (RF) unit capable of performing a conversion between a radio frequency (RF) signal and a baseband signal, wherein the wireless communication signal is one or more of the RF signal and the baseband signal. The first memory is coupled to the integrated processing circuit. The first memory is capable of storing data used by the processing unit, wherein the RF unit and the first memory are packaged in a single semiconductor device.

BACKGROUND

The present invention relates to a wireless communication device, and more particularly to a wireless communication device having an integrated processing circuit and a memory embedded in a same semiconductor package and a wireless communication device having a radio frequency unit and a memory embedded in a same semiconductor device.

In a wireless communication module, a memory package is always installed external to the baseband processing package arranged for processing a baseband operation of the wireless communication module. In this arrangement, however, a large amount of package pins are required for signal transmission between the memory package and the baseband processing package. Furthermore, a plurality of PCB (Printed circuit board) conducting paths should also be required for signal transmission between the package pins of the memory package and the baseband processing package. This interface installed between the memory package and the baseband processing package may occupy a large area on the wireless communication module that can cause difficulties when designing the modern wireless communication system. Besides, the PCB conducting paths may bring lower signal quality and limited operation speed. Therefore, how to reduce the package pin count of the wireless communication module and thus reduce using PCB conducting paths to subsequently reduce the cost is a serious problem in the field of wireless communication system.

SUMMARY

One of the objectives of the present invention is to provide a wireless communication device having an integrated processing circuit and a memory embedded in a same semiconductor package and a wireless communication device having a radio frequency unit and a memory embedded in a same semiconductor device.

According to a first embodiment of the present invention, a wireless communication device is provided. The wireless communication device comprises an integrated processing circuit and a first memory. The integrated processing circuit comprises a processing unit and a radio frequency (RF) unit. The processing unit is capable of processing a wireless communication signal. The radio frequency (RF) unit is capable of performing a conversion between a radio frequency (RF) signal and a baseband signal, wherein the wireless communication signal is one or more of the RF signal and the baseband signal. The first memory is coupled to the integrated processing circuit. The first memory is capable of storing data used by the processing unit, wherein the integrated processing circuit and the first memory are packaged in a single semiconductor package.

According to a second embodiment of the present invention, a wireless communication device is provided. The wireless communication device comprises an integrated processing circuit, a radio frequency (RF) unit, and a first memory. The integrated processing circuit comprises a processing unit, capable of processing a wireless communication signal. The radio frequency (RF) unit is capable of performing a conversion between a radio frequency (RF) signal and a baseband signal. The first memory is coupled to the integrated processing circuit, the first memory is capable of storing data used by the processing unit, wherein the wireless communication signal is one or more of the RF signal and the baseband signal, and the integrated processing circuit, the radio frequency unit, and the first memory are packaged in a single semiconductor package.

According to a third embodiment of the present invention, a wireless communication device is provided. The wireless communication device comprises an integrated processing circuit and a first memory. The integrated processing circuit comprises a processing unit and a radio frequency (RF) unit. The processing unit is capable of processing a wireless communication signal. The radio frequency (RF) unit is capable of performing a conversion between a radio frequency (RF) signal and a baseband signal, wherein the wireless communication signal is one or more of the RF signal and the baseband signal. The first memory is coupled to the integrated processing circuit. The first memory is capable of storing data used by the processing unit. The RF unit is put at one package, the first memory is put at another package, and the two packages are packaged in a single device

According to a fourth embodiment of the present invention, a wireless communication device is provided. The wireless communication device comprises an integrated processing circuit, a radio frequency (RF) unit, and a first memory. The integrated processing circuit comprises a processing unit, capable of processing a wireless communication signal. The radio frequency (RF) unit is capable of performing a conversion between a radio frequency (RF) signal and a baseband signal, wherein the wireless communication signal is one or more of the RF signal and the baseband signal. The first memory is coupled to the integrated processing circuit and the first memory is capable of storing data used by the processing unit. The radio frequency (RF) unit is put at one package, the first memory is put at another package, and the two packages are packaged in a single device.

DETAILED DESCRIPTION

Please refer toFIG. 1.FIG. 1is a diagram illustrating a wireless communication device100according to a first embodiment of the present invention. The wireless communication device100includes an integrated processing circuit102, a first memory104, and a second memory106. The integrated processing circuit102and the first memory104are packaged in a single semiconductor package108, and the second memory106is packaged in another semiconductor package110. The second memory106can be externally coupled to the semiconductor package108via at least one printed circuit board (PCB) conducting path112or any other conducting path suitable for signal transmission between the semiconductor package108and the semiconductor package110. The integrated processing circuit102includes a processing unit capable of processing a wireless communication signal. The first memory104is coupled to the integrated processing circuit102and is capable of storing data used by the processing unit in processing the wireless communication signal or any other signals. The second memory106may be a non-volatile memory (e.g., serial flash, parallel flash, etc.). In addition, the second memory106may be utilized to store data that is used by the processing unit. For example, when the wireless communication device100is powered on, the data stored in the second memory106may first be transferred to the first memory104, and the processing unit then reads the data to perform the initialization process of the wireless communication device100. Furthermore, the data of the second memory106may be stored in the form of compressed data. It should be noted that, in addition to processing the wireless communication signal, the processing unit may also be utilized to perform other functions of the wireless communication device100. For example, the processing unit may be applied to execute application software, process data for a telephone directory or a to-do list of the wireless communication device100.

In this preferred embodiment, the first memory104, which may be a volatile memory (e.g., DRAM, pseudo SRAM, etc.) or a non-volatile memory (e.g., serial flash, parallel flash, etc.), and is conventionally placed externally to the integrated processing circuit102, is now included in the semiconductor package108. In other words, the integrated processing circuit102and the first memory104are arranged to be a system-in-package (SIP). Accordingly, no package pin is required for the interface between the integrated processing circuit102and the first memory104. More specifically, the integrated processing circuit102and the first memory104are two dies in the same semiconductor package108, and thus the interface between the integrated processing circuit102and the first memory104can be implemented by bonding wire(s) rather than the PCB conducting path.

Since the signal transferring between the integrated processing circuit102and the first memory104is within the semiconductor package108, there is no need to build up package pins between the integrated processing circuit102and the first memory104. Furthermore, the total number of PCB conducting paths112arranged to connect the semiconductor package108and the semiconductor package110, thus to connect the integrated processing circuit102and the second memory106, can be reduced. For example, if the second memory106is a serial flash memory, the SPI (Serial Peripheral Interface) bus interface can be used to connect the semiconductor package110with the semiconductor package108, wherein the SPI bus interface needs only 4 to 6 pins. Therefore, the total number of pins of the semiconductor package108and the semiconductor package110is also reduced accordingly. Consequently, the size of the semiconductor package108including the integrated processing circuit102and the first memory104is smaller than the total size of the conventional counterpart having the integrated processing circuit and the first memory separately, and the total size of the semiconductor package108, the PCB conducting paths112, and the semiconductor package110is also smaller than the total size of the conventional counterpart having the integrated processing circuit, the first memory, and the second memory separately.

Since the integrated processing circuit102and the first memory104are packaged in the same semiconductor package108, the signal quality (e.g., the signal eye diagram) of signal transmitting between the integrated processing circuit102and the first memory104may improve in comparison with the conventional counterpart connected by the PCB conducting paths. Moreover, in this preferred embodiment, the first memory104can be upgraded to have a higher operation speed for increasing the data rate transmitted between the integrated processing circuit102and the first memory104due to the absence of PCB conducting paths between the integrated processing circuit102and the first memory104. It should be noted that another benefit of installing the integrated processing circuit102and the first memory104into the same semiconductor package108is that the driving power of the integrated processing circuit102and the first memory104can be set lower than the conventional counterpart, thus power consumption is reduced, since the loading between two dies is lower than the loading between two packages.

In this preferred embodiment, the wireless communication device100may further include a radio frequency (RF) unit and a power management unit (PMU). The RF unit is capable of performing a conversion between a radio frequency (RF) signal and a baseband signal, wherein the wireless communication signal processed by the integrated processing circuit102can be one or more of the RF signal and the baseband signal. The power management unit is capable of managing power consumption of at least one of the integrated processing circuit102and the first memory104. It should be noted that the RF unit and/or the power management unit can be included in the integrated processing circuit102, placed inside the semiconductor package108or external to the semiconductor package108. For example, in one embodiment, the RF unit and/or the power management unit are/is installed within the integrated processing circuit102. In another embodiment, the RF unit and/or the power management unit are/is installed within the semiconductor package108but not within the integrated processing circuit102. In another embodiment, the RF unit and/or the power management unit are/is placed externally to the semiconductor package108.

Please refer toFIG. 2.FIG. 2is a diagram illustrating a wireless communication device200according to a second embodiment of the present invention. The wireless communication device200includes an integrated processing circuit202, a first memory204, and a second memory206. Compared to the above-mentioned first embodiment, the integrated processing circuit202, the first memory204, and the second memory206are all packaged in a single semiconductor package208. The integrated processing circuit202includes a processing unit capable of processing a wireless communication signal. The first memory204is coupled to the integrated processing circuit202and capable of storing data used by the processing unit in processing the wireless communication signal or any other signals. The second memory206is coupled to the integrated processing circuit202. In addition, the second memory206may be utilized to store data that is used by the processing unit. For example, when the wireless communication device200is powered on, the data stored in the second memory206may first be transferred to the first memory204, and the processing unit then reads the data to perform the initialization process of the wireless communication device200. Furthermore, the data of the second memory206may be stored in the form of compressed data. It should be noted that, in addition to processing the wireless communication signal, the processing unit may also be utilized to perform other functions of the wireless communication device200. For example, the processing unit may be applied to execute application software, process data for a telephone directory or a to-do list of the wireless communication device200.

In this preferred embodiment, the first memory204and the second memory206, which may be a volatile memory (e.g., DRAM, pseudo SRAM, etc.) and a non-volatile memory (e.g., serial flash, parallel flash, etc.) respectively, and conventionally would be placed externally to the integrated processing circuit202, are now included in the semiconductor package208. The first memory204can also be a non-volatile memory (e.g., serial flash, parallel flash, etc.). In other words, the integrated processing circuit202, the first memory204, and the second memory206are arranged to be a system-in-package (SIP). Accordingly, no package pin is required for the interface between the integrated processing circuit202and the first memory204, and the interface between the integrated processing circuit202and the second memory206. More specifically, the integrated processing circuit202, the first memory204, and the second memory206are three dies in same the semiconductor package208, thus the interfaces between the integrated processing circuit202and the first memory204, and between the integrated processing circuit202and the second memory206can be implemented by bonding wire(s) rather than the PCB conducting path.

Since the signal transferring between the integrated processing circuit202and the first and second integrated memories204,206is within the semiconductor package208, there is no need to build up package pins between the integrated processing circuit202and the first and second integrated memories204,206. Therefore, the total number of pins of the semiconductor package208is reduced. Consequently, the size of the semiconductor package208including the integrated processing circuit202and the first and second integrated memories204,206is smaller than the total size of the conventional counterpart having the integrated processing circuit and the first and second integrated memories separately.

Similar to the above-mentioned embodiment, the signal quality (e.g., the signal eye diagram) of signal transmitting between the integrated processing circuit202and the first and second integrated memories204,206may become better in comparison with the conventional counterpart connected by the PCB conducting paths. The first and second integrated memories204,206can be upgraded to have higher operation speeds to increase the data rate transmitted between the integrated processing circuit202and the first and second integrated memories204,206due to the absence of PCB conducting paths between the integrated processing circuit202and the first and second integrated memories204,206. In addition, the driving power of the integrated processing circuit202and the first and second integrated memories204,206can be set to be lower than the conventional counterpart.

The wireless communication device200may further include a RF unit and a power management unit. The arrangement of the RF unit and the power management unit can be similar to those arrangements illustrated for the wireless communication device100, thus a detailed description is omitted here for brevity.

Regarding the embodiment shown inFIG. 1, the integrated processing circuit102and the first memory104may be two dies packaged in the same semiconductor package108. However, this is for illustrative purposes only, and is not meant to be a limitation of the present invention.FIG. 3is a diagram illustrating a semiconductor device according to an embodiment of the present invention. The semiconductor device30may include a plurality of semiconductor packages301and302, where an RF unit303may be put at one semiconductor package301, and a memory304may be put at another semiconductor package302. By way of example, but not limitation, multiple semiconductor packages (e.g.,301and302) may be packaged in a single device (e.g., semiconductor device30) by using a two-dimensional (2D) packaging manner or a three-dimensional (3D) packaging manner. For example, package stacking technology, such as Package-on-Package (PoP) or Package-in-Package (PiP), may be employed to package the semiconductor packages301and302in the semiconductor device30. It should be noted that the present invention has no limitations on the packaging method actually used for integrating multiple semiconductor packages in a single device. That is, a single device with one semiconductor package having an RF unit included therein and another semiconductor package having a memory included therein falls within the scope of the present invention.

In accordance with the proposed semiconductor device design shown inFIG. 3, the present invention further proposes alterations of the semiconductor package108shown inFIG. 1.FIG. 4is a diagram illustrating a first alternative integration design of the integrated processing circuit102and the first memory104shown inFIG. 1according to an embodiment of the present invention.FIG. 5is a diagram illustrating a second alternative integration design of the integrated processing circuit102and the first memory104shown inFIG. 1according to an embodiment of the present invention. A wireless communication device (e.g.,100) may be modified to have a semiconductor package (e.g.,108) replaced by the semiconductor device40or the semiconductor device50, depending upon actual design consideration. The major difference between the semiconductor devices40and50is the location of an RF unit1032. The RF unit1032may be configured to perform a conversion between an RF signal and a baseband signal. The processing unit1031may be configured to process a wireless communication signal, where the wireless communication signal may be one or more of the RF signal and the baseband signal. Regarding the embodiment shown inFIG. 4, the RF unit1032and the processing unit1031may be both included in the integrated processing circuit102, the integrated processing circuit102may be put at the semiconductor package401, and the first memory104may be put at another semiconductor package402. Regarding the embodiment shown inFIG. 5, the RF unit1032may be external to the integrated processing circuit102, the integrated processing circuit102and the RF unit1032may be put at the semiconductor package501, and the first memory104may be put at another semiconductor package402.

In the embodiments shown inFIG. 4andFIG. 5, the RF unit1032and the processing unit1031may be put at the same semiconductor package401/501. However, this is for illustrative purposes only, and is not meant to be a limitation of the present invention. Alternatively, the processing unit1031may be configured to be placed outside the semiconductor package401in which the RF unit1032is located. To put it simply, any integration design of the integrated processing circuit102and the first memory104that employs the proposed semiconductor device design shown inFIG. 3falls within the scope of the present invention.

In the above-mentioned embodiments, two issues may emerge from installing the memory (e.g., the first memory104and/or the second memory206) into the semiconductor package/semiconductor device including the integrated processing circuit. The first issue can be how to determine if the memory installed into the semiconductor package/semiconductor device is an effective memory. The second issue can be how to reduce the interference caused by the memory when the memory is installed into the semiconductor package/semiconductor device.

Regarding the first issue, please refer toFIG. 6, which is a flowchart illustrating how to determine if the memory installed into the semiconductor package/semiconductor device is an effective memory. For the example of the wireless communication device100, before the first memory104is ready to be installed in the semiconductor package108(or semiconductor device40/50), a testing procedure (e.g., a chip probe, CP) may be performed by such as the manufacturer of the first memory or the wireless communication device100to determine if the first memory104is an effective memory. When the first memory104fails the testing procedure, the first memory104can be discarded. When the first memory104passes the testing procedure, the first memory104can be signed or marked by an identification, wherein the identification is capable of indicating that the first memory104is an effective memory. In other words, the identification can be regarded as a good ID for the first memory104as shown inFIG. 6.

When the first memory104is identified as an effective memory, the first memory104can then be included into the semiconductor package108(or semiconductor device40/50) with the integrated processing circuit102via a packaging process to form at least a portion of the wireless communication device100. When the packaging process is completed, another test may be performed upon the semiconductor package108(or semiconductor device40/50). At this stage, a tester (not shown) may be utilized for reading the identification (i.e., the good ID1042) of the first memory104, wherein the tester may externally couple to the semiconductor package108(or semiconductor device40/50). When the tester determines that the good ID1042exists in the first memory104, at least the first memory104can be confirmed not the discarded memory. In other words, utilizing the tester to test the existence of good ID1042can help confirm that the first memory104packaged in the semiconductor package108(or semiconductor device40/50) is an effective memory.

Another method to check whether the first memory104packaged in the semiconductor package108(or semiconductor device40/50) is effective is testing the function of the first memory104by a testing circuit1022to see if the first memory104functions well. It should be noted that, in some embodiments, the testing circuit1022can be embedded in the integrated processing circuit102as shown inFIG. 6. More specifically, the testing circuit1022can be a built-in self-test (BIST) circuit embedded in the integrated processing circuit102. Accordingly, the above-mentioned first issue can be solved.

It should be noted that the purpose of signing or marking the good ID1042is to exclude the failed memory from the semiconductor package108(or semiconductor device40/50), and installing the testing circuit1022into the semiconductor package108(or semiconductor device40/50) is to check whether the first memory104is an effective memory. Furthermore, both the good ID1042and the testing circuit1022, or only one of the good ID1042and the testing circuit1022, can be applied to the semiconductor package108(or semiconductor device40/50). In the embodiment that both the good ID1042and the testing circuit1022are applied, when the good ID1042does not work, or when the good ID1042is wrong, the testing circuit1022can be utilized to test the effectivity of the first memory104.

Regarding the second issue, which is how to reduce the interference caused by the first memory104when the first memory104is installed into the semiconductor package108(or semiconductor device40/50), at least three methods are developed to solve this. The first method is to adjust, such as lower, the driving power of a driving signal transmitted between the first memory104and the integrated processing circuit102. In one embodiment, the driving power can be adjusted to a minimum driving power acceptable for transmitting the driving signal between the first memory104and the integrated processing circuit102to make the memory read/write operation performed under the minimum driving power.FIG. 7is a diagram illustrating the wireless communication device400utilizing the first method to reduce the interference caused by the first memory104according to the embodiment of the present invention. In this embodiment, a driving control circuit1024and a boundary circuit1026can be further included in the integrated processing circuit102, and a boundary circuit1044can be further included in the first memory104, wherein at least one bonding wire114is capable of connecting the boundary circuit1026and the boundary circuit1044. The driving control circuit1024is capable of adjusting a driving power of a driving signal Sd generated by the boundary circuit1026and/or the boundary circuit1044. In one embodiment, the driving control circuit1024is capable of adjusting the driving power to a minimum driving power acceptable for transmitting the driving signal Sd between the first memory104and the integrated processing circuit102. When the driving signal Sd transmitted between the first memory104and the integrated processing circuit102is decreased, the interference caused by the first memory104can be reduced. Accordingly, this arrangement is capable of reducing the interference made to the sensitive circuit(s) such as RF unit1032of the wireless communication device400. More specifically, in the wireless communication device400, the sensitive circuit may be utilized to process an analog signal that is more sensitive than the digital circuit. For example, the RF unit1032is utilized to perform the conversion between a radio frequency (RF) signal and a baseband signal of the wireless communication device400. In this embodiment, the RF unit1032is externally coupled (i.e., different die, or different package, or same package) to the integrated processing circuit102, however the RF unit1032and the integrated processing circuit102are installed in the same package (or the same device).

The wireless communication device400further comprises a power management unit (PMU)1034. The power management unit1034is capable of managing power consumption of the integrated processing circuit102and/or the first memory104. In this embodiment, the PMU1034is internally coupled to the integrated processing circuit102. In other words, the PMU1034and the integrated processing circuit102are installed in the same die, however this is not the limitation of the present invention.

It should be noted that, inFIG. 7, though only the testing circuit1022is applied, a good ID can also be applied in the first memory104by using the above-mentioned method. Therefore, both the good ID and the testing circuit1022, or only one of the good ID and the testing circuit1022, can be applied to the semiconductor package108(or semiconductor device50).

The second method is using a frequency hopping scheme to avoid the operating frequency band of sensitive circuit(s) such as the RF unit1032as shown inFIG. 8.FIG. 8is a diagram illustrating a wireless communication device500utilizing the second method to reduce the interference caused by the first memory104according to the embodiment of the present invention. In this embodiment, a frequency control circuit1028can be further included in the integrated processing circuit102. The frequency control circuit1028is capable of controlling an operating frequency of component(s) other than sensitive circuit(s) to be different from the operating frequency band of the sensitive circuit(s). One example of the component(s) other than sensitive circuit(s) is the first memory104. One example of the sensitive circuit(s) is the RF unit1032. In this embodiment, the frequency control circuit1028can be a frequency hopping control circuit. Please refer toFIG. 9.FIG. 9is a flowchart illustrating a frequency hopping control method600performed by the frequency control circuit1028according to an embodiment of the present invention. Provided that substantially the same result is achieved, the steps of the flowchart shown inFIG. 9need not be in the exact order shown and need not be contiguous, that is, other steps can be intermediate. Besides, step602can be omitted. The frequency hopping control method600can include the steps of:

Step602: Identify an operating frequency F1 of the sensitive circuit, e.g., the RF unit1032; and

Step604: Control an operating frequency of the circuit (e.g. the first memory104) other than the sensitive circuit to be away from the operating frequency F1.

In step602, the frequency control circuit1028can identify the operating frequency F1 of the sensitive circuit. More specifically, when/before the wireless communication device500receives an RF signal having an oscillating frequency F1, the frequency control circuit1028is capable of determining the oscillating frequency (i.e., F1) of the RF signal. In step604, when the RF unit1032processes the RF signal, the frequency control circuit1028is capable of controlling the operating frequency F2 of the first memory104to be different from the oscillating frequency (i.e., F1) of RF signal. The operating frequency of the first memory104can be controlled by the frequency control circuit1028to hop to various frequencies to avoid the oscillating frequency F1 when the oscillating frequency F1 is changed as shown inFIG. 10.FIG. 10is a spectrum diagram illustrating the oscillating frequency F1 of the RF signal and various operating frequencies (i.e., F2, F3, F4) of the first memory104according to an embodiment of the present invention. When the oscillating frequency F1 of the RF signal varies, the operating frequency of the first memory104can vary as well to be away from the oscillating frequency F1. Since the operating frequency F1 of the sensitive circuit is now different from the operating frequency F2 of the first memory104, the interference made to the power and signal of the integrated processing circuit102can be reduced. More specifically, in the wireless communication device500, the sensitive circuit may be utilized to process an analog signal that is more sensitive than the digital circuit. For example, the RF unit1032can be utilized to perform the conversion between a radio frequency (RF) signal and a baseband signal of the wireless communication device500. In the wireless communication device500, the RF unit1032is internally coupled (i.e., same die, or same package, or different package) to the integrated processing circuit102.

It should be noted that, inFIG. 8, though only the good ID1042is applied, a testing circuit can also be installed in the semiconductor package108(or semiconductor device40) by using the above-mentioned method. Therefore, both the good ID1042and the testing circuit, or only one of the good ID1042and the testing circuit, can be applied to the semiconductor package108(or semiconductor device40).

The third method is using a spread spectrum scheme to reduce radiation power from at least one circuit other than the sensitive circuit (e.g. RF unit1032) as shown inFIG. 11.FIG. 11is a diagram illustrating the wireless communication device800utilizing the third method to reduce the interference caused by the first memory104according to the embodiment of the present invention. In this embodiment, a frequency control circuit1030can be further included in the integrated processing circuit102. The frequency control circuit1030is capable of spreading an operating frequency of component(s) other than sensitive circuit(s) into a specific frequency band Fss as shown inFIG. 12. One example of the component(s) other than sensitive circuit(s) is the first memory104. One example of the sensitive circuit(s) is the RF unit1032.FIG. 12is a timing diagram illustrating the operating frequency of the first memory104according to an embodiment of the present invention. It should be noted that, for brevity, the operating frequency of the first memory104in this preferred embodiment is also marked as F2. Furthermore, in this embodiment, the frequency control circuit1030can be a spread spectrum control circuit. When the RF unit1032processes a received RF signal for example, the frequency control circuit1030can slowly adjust the operating frequency F2 of the first memory104to change from the lower bound frequency Fssl to the upper bound frequency Fssu of the specific frequency band Fss as shown inFIG. 12. By doing this, the energy of the operating frequency F2 of the first memory104is averagely distributed into the specific frequency band Fss, therefore the interference caused by the operating frequency F2 of the first memory104made to the power and signal of the integrated processing circuit102can be reduced.

In addition, trying to physically place the first memory104away from the sensitive circuit (e.g. RF unit1032) also helps reduce the interference caused by first memory104to the sensitive circuit. More specifically, in the wireless communication device800, the sensitive circuit may be utilized to process an analog signal that is more sensitive than the digital circuit. For example, the RF unit1032is utilized to perform the conversion between a radio frequency (RF) signal and a baseband signal of the wireless communication device800. In the wireless communication device800, the RF unit1032is internally coupled (i.e., same die) to the integrated processing circuit102.

Furthermore, inFIG. 11, though only the good ID1042is applied, a testing circuit can also be installed in the semiconductor package108(or semiconductor device40) by using the above-mentioned method. Therefore, both the good ID1042and the testing circuit, or only one of the good ID1042and the testing circuit, can be applied to the semiconductor package108(or semiconductor device40).

It should be noted that, even though the above-mentioned methods utilized for solving the issue of how to determine if the memory installed into the semiconductor package (or semiconductor device) is an effective memory and the issue of how to reduce the interference caused by the memory are described in conjunction with the wireless communication device100,400,500and800, those skilled in the art will appreciate that the above-mentioned methods may also be applied to the wireless communication device200or any other wireless communication devices having RF unit and memory in the same package (or semiconductor device) for solving similar issues. Examples of wireless communication device may include, but not limited to, mobile phone, tablet and wearable device. Furthermore, the present invention is not limited to using all the above-mentioned methods together in the wireless communication device100,400,500and800. Applying one or more of the above-mentioned methods in the wireless communication device100,200,400,500,800or any other wireless communication devices having integrated processing circuit and memory in the same package (or having the RF unit and memory in the same device) also belongs to the scope of the present invention. Moreover, the arrangement of the above-mentioned good IDs, testing circuits, driving control circuits, frequency control circuits, RF units, first memories, second memories, and PMUs are not limited to the arrangement shown inFIGS. 1-8and11. Those skilled in the art will appreciate that the arrangement may also be re-arranged/modified according to the practical designing requirement of the wireless communication device. Besides, inFIG. 8andFIG. 11, though the frequency control circuits1028,1030, the driving control circuit1024, and the RF unit1032are installed in the integrated processing circuit102, the frequency control circuits1028,1030, the driving control circuit1024, and/or the RF unit1032may be arranged to externally couple to integrated processing circuit102and still in the same semiconductor package108(or semiconductor device40/50), or be selectively omitted. The frequency control circuits1028,1030, the driving control circuit1024, and/or the RF unit1032may also be arranged to externally couple to the semiconductor package108(or semiconductor device40/50).

Briefly, the present invention includes at least one memory into the semiconductor package (or semiconductor device) having an integrated processing circuit for processing the wireless communication signal to reduce the cost of the wireless communication device and improve signal quality and operation speed. Furthermore, the present invention also discloses at least three methods to solve the issue of how to determine if the memory installed into the semiconductor package (or semiconductor device) is an effective memory, and the issue of how to reduce the interference caused by the memory when the memory is installed into the semiconductor package (or semiconductor device).