Package with windowed heat spreader

A semiconductor device has a substrate and a first semiconductor die disposed over the substrate. A subpackage is also disposed over the substrate. A stiffener is disposed over the substrate around the first semiconductor die and subpackage. A heat spreader is disposed over the stiffener. The heat spreader is thermally coupled to the first semiconductor die. The heat spreader has an opening over the subpackage.

FIELD OF THE INVENTION

The present invention relates in general to semiconductor devices and, more particularly, to a semiconductor device and method of forming a semiconductor device with a windowed heat spreader.

BACKGROUND OF THE INVENTION

Semiconductor devices are commonly found in modern electronic products. Semiconductor devices perform a wide range of functions such as signal processing, high-speed calculations, transmitting and receiving electromagnetic signals, controlling electronic devices, transforming sunlight to electricity, and creating visual images for television displays. Semiconductor devices are found in the fields of communications, power conversion, networks, computers, entertainment, and consumer products. Semiconductor devices are also found in military applications, aviation, automotive, industrial controllers, and office equipment.

As devices are reduced in size, and operate at higher frequencies, heat generation of the semiconductor components becomes more of a design consideration. Many semiconductor packages include heat spreaders connected to semiconductor die. The heat spreaders help dissipate heat from the semiconductor die by spreading out the thermal energy over a larger surface area. The heat spreaders also improve thermal handling capacity by allowing an external heat sink to be attached via the heat spreader.

Heat spreaders are typically a separate component disposed over a semiconductor die or package. The heat spreaders commonly form part of an enclosure that extends around and over components of the semiconductor package. One problem with prior art heat spreaders is that the enclosure can trap thermal energy within the package and cause problems with thermal management of other enclosed components. Therefore, a need exists for an improved heat spreader for semiconductor packages.

DETAILED DESCRIPTION OF THE DRAWINGS

The present invention is described in one or more embodiments in the following description with reference to the figures, in which like numerals represent the same or similar elements. While the invention is described in terms of the best mode for achieving the invention's objectives, it will be appreciated by those skilled in the art that it is intended to cover alternatives, modifications, and equivalents as may be included within the spirit and scope of the invention as defined by the appended claims and their equivalents as supported by the following disclosure and drawings. The term “semiconductor die” as used herein refers to both the singular and plural form of the words, and accordingly, can refer to both a single semiconductor device and multiple semiconductor devices.

Back-end manufacturing refers to cutting or singulating the finished wafer into the individual semiconductor die and packaging the semiconductor die for structural support, electrical interconnect, and environmental isolation. To singulate the semiconductor die, the wafer is scored and broken along non-functional regions of the wafer called saw streets or scribes. The wafer is singulated using a laser cutting tool or saw blade. After singulation, the individual semiconductor die are mounted to a package substrate that includes pins or contact pads for interconnection with other system components. Contact pads formed over the semiconductor die are then connected to contact pads within the package. The electrical connections can be made with conductive layers, bumps, stud bumps, conductive paste, bond wires, or other suitable interconnect structure. An encapsulant or other molding compound is deposited over the package to provide physical support and electrical isolation. The finished package is then inserted into an electrical system and the functionality of the semiconductor device is made available to the other system components.

FIG.1ashows a semiconductor wafer100with a base substrate material102, such as silicon, germanium, aluminum phosphide, aluminum arsenide, gallium arsenide, gallium nitride, indium phosphide, silicon carbide, or other bulk semiconductor material. A plurality of semiconductor die or components104is formed on wafer100separated by a non-active, inter-die wafer area or saw street106as described above. Saw street106provides cutting areas to singulate semiconductor wafer100into individual semiconductor die104. In one embodiment, semiconductor wafer100has a width or diameter of 100-450 millimeters (mm).

FIG.1bshows a cross-sectional view of a portion of semiconductor wafer100. Each semiconductor die104has a back or non-active surface108and an active surface110containing analog or digital circuits implemented as active devices, passive devices, conductive layers, and dielectric layers formed within or over the die and electrically interconnected according to the electrical design and function of the die. For example, the circuit may include one or more transistors, diodes, and other circuit elements formed within active surface110to implement analog circuits or digital circuits, such as digital signal processor (DSP), ASIC, MEMS, memory, or other signal processing circuit. Semiconductor die104may also contain integrated passive devices (IPDs), such as inductors, capacitors, and resistors, for RF signal processing. Back surface108of semiconductor wafer100may undergo an optional backgrinding operation with a mechanical grinding or etching process to remove a portion of base material102and reduce the thickness of semiconductor wafer100and semiconductor die104.

An electrically conductive layer112is formed over active surface110using PVD, CVD, electrolytic plating, electroless plating process, or other suitable metal deposition process. Conductive layer112include one or more layers of aluminum (Al), copper (Cu), tin (Sn), nickel (Ni), gold (Au), silver (Ag), or other suitable electrically conductive material. Conductive layer112operates as contact pads electrically connected to the circuits on active surface110.

Conductive layer112can be formed as contact pads disposed side-by-side a first distance from the edge of semiconductor die104, as shown inFIG.1B. Alternatively, conductive layer112can be formed as contact pads that are offset in multiple rows such that a first row of contact pads is disposed a first distance from the edge of the die, and a second row of contact pads alternating with the first row disposed a second distance from the edge of the die. Conductive layer112represents the last conductive layer formed over semiconductor die104with contact pads for subsequent electrical interconnect to a larger system. However, there may be one or more intermediate conductive and insulating layers formed between the actual semiconductor devices on active surface110and contact pads112for signal routing.

An electrically conductive bump material is deposited over conductive layer112using an evaporation, electrolytic plating, electroless plating, ball drop, or screen printing process. The bump material can be Al, Sn, Ni, Au, Ag, Pb, Bi, Cu, solder, and combinations thereof, with an optional flux solution. For example, the bump material can be eutectic Sn/Pb, high-lead solder, or lead-free solder. The bump material is bonded to conductive layer112using a suitable attachment or bonding process. In one embodiment, the bump material is reflowed by heating the material above its melting point to form conductive balls or bumps114. In one embodiment, conductive bumps114are formed over an under bump metallization (UBM) having a wetting layer, barrier layer, and adhesion layer. Conductive bumps114can also be compression bonded or thermocompression bonded to conductive layer112. Conductive bumps114represent one type of interconnect structure that can be formed over conductive layer112for electrical connection to a substrate. The interconnect structure can also use bond wires, conductive paste, stud bump, micro bump, or other electrical interconnect.

InFIG.1c, semiconductor wafer100is singulated through saw street106using a saw blade or laser cutting tool118into individual semiconductor die104. The individual semiconductor die104can be inspected and electrically tested for identification of KGD post-singulation.

FIGS.2a-2hillustrate forming semiconductor packages150with semiconductor die104and a windowed heat spreader.FIG.2ais a partial cross-sectional view of a substrate152used as a base for manufacturing packages150. Substrate152can be a unit substrate singulated from a larger panel or remain as part of a larger substrate panel. Hundreds or thousands of packages are commonly formed in a single substrate panel or on separate unit substrates on a single carrier using the same steps described herein.

Substrate152includes one or more insulating layers154interleaved with one or more conductive layers156. Insulating layer154is a core insulating board in one embodiment, with conductive layers156patterned over the top and bottom surfaces, e.g., a copper-clad laminate substrate. Conductive layers156also include conductive vias electrically coupled vertically through insulating layers154. Substrate152can include any number of conductive and insulating layers interleaved over each other. A solder mask or passivation layer can be formed over either side of substrate152. Any suitable type of substrate or leadframe is used for substrate152in other embodiments.

Any components desired to implement the intended functionality of packages150are mounted to or disposed over substrate152and electrically connected to conductive layers156. Substrate152has two major surfaces: top surface157and bottom surface159. Components can be mounted onto top surface157and bottom surface159in any suitable configuration. InFIG.2b, manufacturing of package150on substrate152commences with surface mounting of semiconductor die104, discrete component164, and subpackage170on top surface157using, e.g., any suitable pick and place method or device.

Semiconductor die104represents any one or more electrical components that are to be thermally connected or coupled to an overlying heat spreader in subsequent manufacturing steps for thermal management. Subpackage170and discrete components164represent components that do not need to be directly coupled to a heat spreader. Subpackage170can be any suitable package of any suitable type or configuration. Subpackage170can also be a bare die similar to semiconductor die104, or only discrete components164can be used without a separate subpackage170.

The illustrated subpackage170includes a substrate172similar to substrate152, a die174similar to die104, an encapsulant176, and solder bumps178similar to bumps114. Additional die, subpackages, or discrete components can be mounted on top surface157or159as desired to implement the intended functionality of package150. Discrete components164, e.g., resistors, capacitors, inductors, transistors, or diodes, are mounted on top surface157using solder paste or another suitable attachment and connection mechanism. Solder paste is reflowed between terminals of discrete components164and contact pads of conductive layers156on top surface157. Bumps114and178are reflowed, typically in the same process step, to physically and electrically connect die104and subpackage170, respectively, to substrate152.

InFIG.2c, an adhesive layer200is disposed on top surface157. Adhesive200is dispensed in a ring completely around the perimeter of substrate152using a nozzle in one embodiment. In other embodiments, adhesive200is discontinuous around the perimeter of substrate152.

Adhesive200is used to attach a stiffener ring202to substrate152inFIGS.2dand2e. Stiffener ring202forms a ring around semiconductor die104, subpackage170, and discrete component168. In the illustrated embodiment, stiffener ring202extends completely to all edges of substrate152and continuously around the perimeter of the substrate. In other embodiments, substrate152may extend outside the boundary of stiffener ring202and additional components may be disposed on the substrate outside of the stiffener ring boundary. Stiffener ring202sits directly on adhesive200and has approximately the same shape. In embodiments where stiffener ring202does not follow the perimeter of substrate152, adhesive200is modified to follow the shape of the stiffener ring accordingly. Adhesive200fixes stiffener ring202to substrate152. Stiffener ring202physically supports the final package to reduce warpage.

A thermal interface material (TIM)204is disposed on back surface108of semiconductor die104. TIM204facilitates thermal transfer from semiconductor die104to the overlying heat spreader to be placed in the following manufacturing steps. TIM204can be applied in any suitable pattern and may not completely cover back surface108.

FIG.2eshows a plan view of stiffener ring202on substrate152, revealing a plurality of discrete components164and a pair of subpackages170aand170b. Any suitable combination of components can be used. In one embodiment, subpackage170ais the subpackage illustrated in the cross section ofFIG.2dwhile subpackage170bis a bare die similar to die104. The plan view shows how stiffener ring202extends completely around the components on substrate152. Stiffener ring202may also be discontinuous.

InFIGS.2fand2g, heat spreader210is disposed on stiffener ring202. Heat spreader210is cut from a sheet of metal using mechanical or laser cutting or formed using any other suitable process. The material for heat spreader210is copper, steel, aluminum, titanium, carbon, mixtures thereof, alloys thereof, or any other suitable metal or nonmetal heat spreader material. Heat spreader210includes an outer perimeter that is approximately identical to the outer perimeter of ring202. An adhesive214is disposed on heat spreader210, stiffener ring202, or both prior to disposing the heat spreader on the stiffener ring. Adhesive214mechanically fixes heat spreader210to stiffener ring202. The height of stiffener ring202is selected such that a bottom surface of heat spreader210contacts and presses down on TIM204.

TIM204is pressed into a thin layer by heat spreader210. TIM204enhances thermal conductivity from semiconductor die104to heat spreader210. In general, heat spreader210will be pressed down until the heat spread physically contacts semiconductor die104. TIM204fills in tiny gaps between heat spreader210and back surface108of semiconductor die104that exist due to asperities and other imperfections in the surfaces. All below embodiments also typically include their respective heat spreaders in physical contact with their respective die or other electrical components being cooled.

Heat spreader210includes a window212formed as an opening completely through the heat spreader over subpackages170.FIG.2gshows a plan view with subpackages170aand170bcontained completely within the footprint of window212. Having subpackages170completely within the footprint of window212allows the subpackages to be taller than would be normally allowed if heat spreader210completely filled in the area within stiffener ring202. However, subpackages170can extend outside a footprint of window212, under heat spreader210, if the subpackages are shorter than stiffener ring202. Heat spreader210extends over discrete components168, but discrete components168could also be located within the footprint of window212. Window212is formed in any suitable shape based primarily on the layout of underlying components that do not need to be in direct thermal contact with heat spreader210.

Package150is completed inFIG.2hby applying solder bumps220to bottom surface159of substrate152in any suitable method, similar to the application of bumps114inFIG.1B. Bumps220are subsequently used to install package150into a larger electrical system. In some embodiments, a plurality of packages150are formed as a panel and then singulated from each other after completion.

Semiconductor die104is thermally connected to heat spreader210by TIM204, which allows thermal energy from the semiconductor die to be efficiently removed. A heatsink can later be attached to the top surface of heat spreader210opposite semiconductor die104to increase the exposed surface area and thereby the rate of thermal transfer to ambient. Opening212in heat spreader210allows thermal energy from subpackages170to escape package150to ambient. Subpackages170may not require thermal management via a heat spreader, but could still produce enough heat to cause malfunction if fully enclosed within a complete bubble formed between substrate152, stiffener ring202, and heat spreader210without window212. Window212allows heat within package150to escape quicker than if heat spreader210fully enclosed the package. Any components that require a heat sink or heat spreader are placed under heat spreader210while components that do not need a heat spreader are placed under or near window212to allow convection out of package150.

FIG.3shows a double-sided semiconductor package222. Semiconductor package222is similar to package150, with the primary difference being semiconductor die224and discrete component226disposed on bottom surface159. Any combination of components, including active or passive discrete components, integrated circuits, and subpackages, can be mounted on bottom surface159.

FIGS.4a-4cillustrate embodiments where the stiffener ring includes a bar through the package to compartmentalize the electrical components. Stiffener230inFIG.4aincludes a ring stiffener230aand compartment stiffener230bformed together as a single continuous block of material. Compartment stiffener230bcreates two different compartments for the electrical components on substrate152. Alternatively, a separate compartment stiffener240can be added in addition to ring stiffener210as shown inFIG.4b.

A compartment stiffener helps further brace the resultant semiconductor packages against warpage and reduces the amount of heat from semiconductor die104that reaches subpackages170via radiation or convection.FIG.4cshows a cross-section of a package250with a compartment stiffener. Both compartment stiffener240with ring stiffener210and stiffener230with compartment stiffener230bbuilt in have basically the same cross-sectional appearance other than in cross-sections where gaps exist between stiffeners210and240.FIG.4calso illustrates a taller subpackage170cextending into window212and over the top surface of heat spreader210as an example. Any embodiment can include the taller subpackage170c.

In some cases, a height of semiconductor die104is not suitable for a flat heat spreader disposed on a specific thickness of ring stiffener202that is available.FIGS.5a-5cillustrate various embodiments to accommodate different heights of semiconductor die104. InFIG.5a, package260includes a semiconductor die104athat is taller than ring stiffener202, and therefore heat spreader210would be unable to lie flat on the ring stiffener.

Accordingly, a heat spreader262with a cavity264formed into the bottom surface of the heat spreader is used. Cavity264has a depth into heat spreader262approximately equal to, or slightly larger than, the height differential between semiconductor die104aand ring stiffener202. When heat spreader262is laid down on ring stiffener202, there is a slight gap between the horizontal surface of cavity264and back surface108of semiconductor die104ato accommodate TIM266.

FIG.5bshows another cross-sectional view of the same package260. The cross-section ofFIG.5bonly extends through heat spreader262and not through window212. Two semiconductor die104aand104bare coupled to heat spreader262for cooling. As previously discussed, semiconductor die104ais taller than ring stiffener202and a cavity264is used to accommodate the excess height. Semiconductor die104b, on the other hand, is short enough that heat spreader210would be too far away to make a satisfactory thermal coupling. Heat spreader262is formed with a protrusion268to lower the bottom surface of the heat spreader above semiconductor die104b. Protrusion268brings the bottom surface of heat spreader262down so that the gap between the heat spreader and semiconductor die104bis appropriate for TIM266to thermally connect the two. Protrusion268has beveled edges, but the edges could also be vertical as with cavity264. Likewise, cavity264could have beveled edges instead of the pictured vertical edges.

FIG.5cshows package270with heat spreader272. Package270includes the same two semiconductor die104aand104bfrom package260, with die104abeing taller than ring stiffener202and die104bbeing shorter. Heat spreader272is stamped or otherwise bent, shaped, or formed to include areas274and280of different heights compared to the rest of the heat spreader that is approximately even with the top of ring stiffener202. Area274is stamped from the top to lower the bottom surface toward semiconductor die104b. Because heat spreader272begins with a uniform thickness and no material is removed in the stamping process, the thickness of the heat spreader within area274remains approximately equal to the thickness around area274. A concave surface276is formed on top of heat spreader272, and a convex surface278is formed on the bottom of the heat spreader by area274being moved downward.

Likewise, area280is stamped from the bottom to raise the surface of heat spreader272and form a convex surface282on top and a concave surface284on the bottom. Stamping is performed prior to installing heat spreader272onto package270. Stamping bends the metal of heat spreader272into the illustrated shape or other suitable shapes. Any number and height of semiconductor die, semiconductor packages, or other suitable devices can make thermal contact with a heat spreader via any of the methods disclosed inFIGS.5a-5c.

FIGS.6a-6cillustrate various embodiments where a mesh is formed through a heat spreader instead of a window. The mesh includes a plurality of smaller openings or holes formed through the heat spreader instead of one larger window. InFIG.6a, heat spreader290includes a mesh291formed over subpackages170aand170b. Mesh291includes a plurality of diamond shaped openings292. Heat spreader293inFIG.6bincludes a mesh294comprising a plurality of square openings295. Heat spreader296inFIG.6cincludes a mesh297with a plurality of circular openings298. Openings292,295, and298can be formed by mechanical drilling, mechanical punching, laser cutting, or another suitable process. Any shape of opening can be used to form a mesh. Forming a mesh over subpackages170aand170bhelps physically protect the tops of the subpackages from external contact while still allowing thermal convection out of the package. The heat spreader material remaining between the mesh holes provides physical protection while the mesh holes allow thermal convection out of the package.

FIGS.7aand7billustrate incorporating the above-described semiconductor packages, e.g., package150, into an electronic device300.FIG.7aillustrates a partial cross-section of package150mounted onto a printed circuit board (PCB) or other substrate302as part of electronic device300. Bumps220are reflowed onto conductive layer304of PCB302to physically attach and electrically connect package150to the PCB. In other embodiments, thermocompression or other suitable attachment and connection methods are used. In some embodiments, an adhesive or underfill layer is used between package150and PCB302. Semiconductor die104, discrete component168, and subpackage170are electrically coupled to each other and conductive layer304through substrate152and bumps220.

FIG.7billustrates electronic device300including PCB302with a plurality of semiconductor packages mounted on a surface of the PCB, including package150. Electronic device300can have one type of semiconductor package, or multiple types of semiconductor packages, depending on the application. Electronic device300can be a stand-alone system that uses the semiconductor packages to perform one or more electrical functions. Alternatively, electronic device300can be a subcomponent of a larger system. For example, electronic device300can be part of a tablet computer, cellular phone, digital camera, communication system, or other electronic device. Electronic device300can also be a graphics card, network interface card, or another signal processing card that is inserted into a computer. The semiconductor packages can include microprocessors, memories, ASICs, logic circuits, analog circuits, RF circuits, discrete active or passive devices, or other semiconductor die or electrical components.

InFIG.7b, PCB302provides a general substrate for structural support and electrical interconnection of the semiconductor packages mounted on the PCB. Conductive signal traces304are formed over a surface or within layers of PCB302using evaporation, electrolytic plating, electroless plating, screen printing, or other suitable metal deposition process. Signal traces304provide for electrical communication between the semiconductor packages, mounted components, and other external systems or components. Traces304also provide power and ground connections to the semiconductor packages as needed.

In some embodiments, a semiconductor device has two packaging levels. First level packaging is a technique for mechanically and electrically attaching the semiconductor die to an intermediate substrate. Second level packaging involves mechanically and electrically attaching the intermediate substrate to PCB302. In other embodiments, a semiconductor device may only have the first level packaging where the die is mechanically and electrically mounted directly to PCB302.

For the purpose of illustration, several types of first level packaging, including bond wire package346and flipchip348, are shown on PCB302. Additionally, several types of second level packaging, including ball grid array (BGA)350, bump chip carrier (BCC)352, land grid array (LGA)356, multi-chip module (MCM)358, quad flat non-leaded package (QFN)360, quad flat package362, and embedded wafer level ball grid array (eWLB)364are shown mounted on PCB302along with package150. Conductive traces304electrically couple the various packages and components disposed on PCB302to package150, giving use of the components within package150to other components on the PCB.

Depending upon the system requirements, any combination of semiconductor packages, configured with any combination of first and second level packaging styles, as well as other electronic components, can be connected to PCB302. In some embodiments, electronic device300includes a single attached semiconductor package, while other embodiments call for multiple interconnected packages. By combining one or more semiconductor packages over a single substrate, manufacturers can incorporate pre-made components into electronic devices and systems. Because the semiconductor packages include sophisticated functionality, electronic devices can be manufactured using less expensive components and a streamlined manufacturing process. The resulting devices are less likely to fail and less expensive to manufacture resulting in a lower cost for consumers.