Airgap spacers formed in conjunction with a late gate cut

Methods of forming a field-effect transistor and structures for a field effect-transistor. A sidewall spacer is formed adjacent to a sidewall of a gate structure of the field-effect transistor and a dielectric cap is formed over the gate structure and the sidewall spacer. A cut is formed that extends through the dielectric cap, the gate structure, and the sidewall spacer. After forming the cut, the sidewall spacer is removed from beneath the dielectric cap to define a cavity, and a dielectric material is deposited in the cut and in the cavity. The dielectric material encapsulates a portion of the cavity to define an airgap spacer.

BACKGROUND

The present invention relates to semiconductor device fabrication and integrated circuits and, more specifically, to methods of forming a field-effect transistor and structures for a field effect-transistor.

Complementary-metal-oxide-semiconductor (CMOS) processes may be used to build a combination of p-type and n-type field-effect transistors that are used to construct, for example, logic cells. Field-effect transistors generally include a body defining a channel region, a source, a drain, and a gate electrode. When a control voltage exceeding a characteristic threshold voltage is applied to the gate electrode, carrier flow occurs in the channel region between the source and drain to produce a device output current.

The gate electrode may be covered by a self-aligned contact cap that protects the gate electrode during the formation of source/drain contacts. Sidewall spacers are arranged adjacent to the sidewalls of the gate electrode. The sidewall spacers may be composed of a dielectric material having a low dielectric constant. In that regard, the sidewall spacers may incorporate airgaps to form airgap spacers. In conventional process flows, the airgap spacers are formed after forming the source/drain contacts and after removing the self-aligned contact caps from their positions over the gate electrodes. Specifically, the self-aligned contact caps and sacrificial sidewall spacers are removed to generate opened spaces, and the opened spaces are refilled with portions of a dielectric layer that is non-conformally deposited. The deposited dielectric layer pinches off in the narrow portions of the spaces formerly occupied by the sidewall spacers and thereby forms the airgap spacers. The deposited dielectric layer also re-forms the self-aligned contact caps over the gate electrodes. The locations of the airgap spacers are based on the profiles of the gate electrodes and source/drain contacts, which may introduce significant variations in the locations of the airgaps and elevate the risk that the airgaps may be opened and filled with metal during downstream processing steps.

Improved structures for a field-effect transistor and methods of forming a structure for a field-effect transistor are needed.

SUMMARY

In an embodiment of the invention, a method includes forming a gate structure, forming a sidewall spacer adjacent to a sidewall of the gate structure, forming a dielectric cap over the gate structure and the sidewall spacer, and forming a cut extending through the dielectric cap, the gate structure, and the sidewall spacer. After forming the cut, the sidewall spacer is removed from beneath the dielectric cap to define a cavity, and a dielectric material is deposited in the cut and in the cavity. The dielectric material encapsulates a portion of the cavity to define an airgap spacer.

In an embodiment of the invention, a structure includes a gate structure with a first lengthwise section and a second lengthwise section, and an airgap spacer adjacent to a sidewall of the first lengthwise section of the gate structure. The airgap spacer includes a first portion of a dielectric material and a cavity encapsulated within the first portion of the dielectric material. A dielectric pillar is arranged in a cut between the first lengthwise section of the gate structure and the second lengthwise section of the gate structure. The dielectric pillar includes a second portion of the dielectric material that is contiguous with the first portion of the dielectric material.

DETAILED DESCRIPTION

With reference toFIGS. 1 and 1A-1Cand in accordance with embodiments of the invention, fins10,12of an integrated circuit structure are formed that project from a substrate14. The fins10,12may be formed by patterning the single-crystal semiconductor material (e.g., single-crystal silicon) of the substrate14with lithography and etching processes, and cutting the patterning semiconductor material into given lengths in the layout associated with the specific device structures being formed and their arrangement. Trench isolation regions16are formed that operate to electrically isolate the fins10,12from each other. The trench isolation regions16may be formed by depositing a layer composed of a dielectric material, such as an oxide of silicon (e.g., silicon dioxide), by chemical vapor deposition (CVD), and recessing with an etching process. An upper section of each of the fins10,12is revealed by the recessing of the trench isolation regions16, and a lower section of each of the fins10,12is surrounded by the trench isolation regions16.

Gate structures18of the integrated circuit structure are formed that extend over the fins10,12, substrate14, and trench isolation regions16. Each gate structure18is arranged transverse to the fins10and overlaps with a section of each fin10. Each gate structure18is also arranged transverse to the fins12and overlaps with a section of each fin12. Each gate structure18may include a gate electrode20and a gate dielectric layer22arranged between the overlapped sections of the fins10,12and the gate electrode20. The gate electrode20may include one or more conformal barrier metal layers and/or work function metal layers, such as metal layers composed of titanium aluminum carbide and/or titanium nitride, and a metal gate fill layer composed of a conductor, such as tungsten. The gate dielectric layer22may be composed of a high-k dielectric material, such as hafnium oxide.

Each of the gate structures18includes a sidewall23and a sidewall24that is opposite from the sidewall23, as well as a top surface25that connects the sidewalls23,24. Sidewall spacers26are arranged on the opposite sidewalls23,24of the gate structures18. The sidewall spacers26may be composed of a sacrificial material, such as aluminum oxide or titanium oxide, that is deposited with atomic layer deposition (ALD) as a conformal layer on the gate structures18and etched with a directional etching process, such as reactive ion etching (RIE). The sidewall spacers26are placeholder structures that are subsequently removed to form air gap spacers.

Semiconductor layers28are epitaxially grown from the fins10,12. The semiconductor layers28may be formed by an epitaxial growth process in which semiconductor material nucleates for epitaxial growth from a semiconductor surface, such as the exposed surfaces of fins10,12, and grows in crystalline fashion. For example, the epitaxial semiconductor layers28may contain silicon-germanium doped during epitaxial growth with a p-type dopant (e.g., boron, aluminum, gallium, and/or indium) that provides p-type electrical conductivity. As another example, the epitaxial semiconductor layers28may contain silicon-germanium doped during epitaxial growth with an n-type dopant (e.g., phosphorus and/or arsenic) that provides n-type electrical conductivity. The epitaxial semiconductor layers28furnish source/drain regions for field-effect transistors formed using the fins10,12and gate structures18. As used herein, the term “source/drain region” means a doped region of semiconductor material that can function as either a source or a drain of a field-effect transistor.

With reference toFIGS. 2A-2Cin which like reference numerals refer to like features inFIGS. 1A-1Cand at a subsequent fabrication stage of the processing method, the gate electrode20and the gate dielectric layer22of the gate structures18are recessed relative to the sidewall spacers26, the CESL32, and the interlayer dielectric layer34using one or more selective etching processes to form cavities. As used herein, the term “selective” in reference to a material removal process (e.g., etching) denotes that, with an appropriate etchant choice, the material removal rate (i.e., etch rate) for the targeted material is greater than the removal rate for at least another material exposed to the material removal process. Portions of the sidewall spacers26are arranged above the top surface25of the recessed gate structures18.

The portions of the sidewall spacers26arranged above the top surface25of the recessed gate structures18are removed with an etching process that widens the cavities. The etching process may include, for example, a reactive ion etching process that removes the material of the sidewall spacers26selective to the materials of the gate structures18, the CESL32, and the interlayer dielectric layer34. The height of the sidewall spacers26is effectively shortened by the etching process, and the shortened sidewall spacers26may be coplanar with the gate structures18.

After the sidewall spacers26are etched, self-aligned contact caps38are formed in the widened cavities over the gate structures18and sidewall spacers26. The self-aligned contact caps38may be may be composed of a layer of a dielectric material, such as silicon nitride, that is deposited by chemical vapor deposition to fill the widened cavities over the gate structures18and sidewall spacers26and then planarized with chemical-mechanical polishing (CMP). Each self-aligned contact cap38has a bottom surface37that shares a boundary with the top surface25of the associated gate structure18and the adjacent top surfaces of the sidewall spacers26.

With reference toFIGS. 3A-3Cin which like reference numerals refer to like features inFIGS. 2A-2Cand at a subsequent fabrication stage of the processing method, the CESL32and the interlayer dielectric layer34are removed from their respective positions over the epitaxial semiconductor layers28, which exposes the epitaxial semiconductor layers28. The cavities opened by removal of the CESL32and interlayer dielectric layer34are filled with trench silicide (TS) contacts40. The TS contacts40are physically and electrically connected with the epitaxial semiconductor layers28. The TS contacts40, which are arranged in a vertical direction over the epitaxial semiconductor layers28, may include a metal silicide, such as tungsten silicide, titanium silicide, nickel silicide, or cobalt silicide, formed by silicidation. The TS contacts40may be deposited by, for example, chemical vapor deposition, planarized by chemical-mechanical polishing, and recessed with a selective etching process.

Dielectric caps42are formed in the portion of the cavities over the recessed TS contacts40. The dielectric caps42may be may be composed of a layer of dielectric material, such as silicon nitride, that is deposited to fill the portion of the opened spaces over the recessed TS contacts40by chemical vapor deposition and then planarized with chemical-mechanical polishing (CMP).

With reference toFIGS. 4A-4Cin which like reference numerals refer to like features inFIGS. 3A-3Cand at a subsequent fabrication stage of the processing method, an etch mask44is formed by applying a lithography stack and patterning the lithography stack to generate an opening46. The etch mask44may include a photoresist layer, an organic planarization layer (OPL) material, and an anti-reflection coating that are patterned with lithography and etching processes. The opening46in the etch mask44exposes portions of the self-aligned contact caps38over the gate structures18over an area arranged in a lateral direction between the fins10and the fins12. The opening46extends transverse to the length of the gate structures18.

The portions of the self-aligned contact caps38exposed by the opening46in the etch mask44are etched and removed with an etching process, such as a reactive ion etching process, to expose portions of the gate electrode20and the gate dielectric layer22of the gate structures18and the sidewall spacers26. The exposed portions of the gate electrode20and the gate dielectric layer22of the gate structures18and the sidewall spacers26are then etched and removed with one or more anisotropic etching processes, such as reactive ion etching processes, to expose portions of the trench isolation regions16. Each gate structure18and its sidewall spacers26are divided by the one or more etching processes into distinct disconnected lengthwise sections separated by a cut48. One of the lengthwise sections of each gate structure18is associated with the fins10, and the other of the lengthwise sections of each gate structure18is associated with the fins12. The etch mask44may be removed after forming the cut48.

With reference toFIGS. 5A-5Cin which like reference numerals refer to like features inFIGS. 4A-4Cand at a subsequent fabrication stage of the processing method, the sidewall spacers26are etched and removed by an etching process, such as a wet chemical etching process, that is isotropic with lateral and vertical components. Access for the ingress of the etching process is provided through the cut48, and the sidewall spacers26may be fully removed by the etching process. The lateral removal of the sidewall spacers26forms cavities50that are arranged beneath the self-aligned contact caps38and, in particular, below the bottom surfaces37of the self-aligned contact caps38. The etching process removes the sidewall spacers26selective to the self-aligned contact caps38such that the self-aligned contact caps38are undercut to form the cavities50. The etching process also removes the sidewall spacers26selective to the fins10,12, the trench isolation regions16, the gate structures18, the epitaxial semiconductor layers28, and the TS contacts40. The materials of the involved features are selected to provide the etch selectivity.

The cavities50are arranged in the spaces formerly occupied by the sidewall spacers26, and each cavity50may have dimensions equal or substantially equal to the dimensions of the removed sidewall spacer26. Each cavity50defines a covered channel or passageway extending laterally beneath the bottom surface of the overlying self-aligned contact cap38. In particular, a portion of each cavity50extends laterally from the cut48toward and over the fins10, and another portion of each cavity50also extends laterally in an opposite direction from the cut48toward and over the fins12. The cavities50are aligned parallel or substantially parallel to the length of the gate structures18and are self-aligned during the lateral etching process by the physical presence of the gate structures18, TS contacts40, and self-aligned contact caps38.

The overlying self-aligned contact caps38and the underlying trench isolation regions16and fins10,12provide vertical constraint during the etching process such that the height of the cavities50is uniform among the different cavities50. Each cavity50extends in a vertical direction from the trench isolation regions16to the bordering bottom surface37of the self-aligned contact caps38. The gate structures18and the stacked epitaxial semiconductor layers28and TS contacts40provide horizontal constraint during the etching process. The cavities50are formed without removing the self-aligned contact caps38as is done when performing conventional processes in order to remove the sidewall spacers. The dimensions (e.g., length, width, and height) of the cavities50may be equal or substantially equal to the dimensions of the removed sidewall spacers26.

With reference toFIGS. 6A-6Cin which like reference numerals refer to like features inFIGS. 5A-5Cand at a subsequent fabrication stage of the processing method, a dielectric layer52is concurrently deposited in the cut48and inside the cavities50. The dielectric layer52may be composed of silicon dioxide or a low-k dielectric material, such as SiC, SiOC, SiOCN, SiN, or SiBCN, deposited by atomic layer deposition or chemical vapor deposition.

The dielectric layer52deposits on the surfaces inside the cavities50and within the cut48, and pinches-off to prevent complete filling of the cavities50. Instead, portions of the cavities50remain unfilled and are surrounded by the dielectric material of the dielectric layer52. The portions of the cavities50are sealed in part by the portion of the dielectric material deposited inside the cut48and are encapsulated by the dielectric material of the dielectric layer52. The sealed portions of the cavities50define one or more airgaps that may be characterized by a permittivity or dielectric constant of near unity (i.e., vacuum permittivity). Each airgap may be filled by atmospheric air at or near atmospheric pressure, may be filled by another gas at or near atmospheric pressure, or may contain atmospheric air or another gas at a sub-atmospheric pressure (e.g., a partial vacuum). The sealed portions of the cavities50are arranged over and between the fins10,12, and generally between the bottom surface37of the self-aligned contact caps38and the trench isolation regions16. The combination of the cavities50and the dielectric material of the dielectric layer52defines airgap spacers that are arranged with precise placement between the gate structures18and the TS contacts40. The composite dielectric constant of the airgap spacers is less than the dielectric constant of the dielectric material of the dielectric layer52.

The portion of the dielectric material deposited inside the cut48provides a dielectric pillar furnishing electrical isolation between the lengthwise sections of the gate structures18associated with fins10and the lengthwise sections of the gate structures18associated with fins12. The portion of the dielectric material deposited inside the cut48is contiguous with the portions of the dielectric material deposited inside the cavities50that participate in forming the airgap spacers.