Memory module and memory system

A memory module is provided which includes a printed circuit board; first semiconductor packages provided on one surface of the printed circuit board; and second semiconductor packages provided on the other surface of the printed circuit board, the first semiconductor packages and the second semiconductor packages having semiconductor dies that form ranks. A number of the ranks formed by the first semiconductor packages being different from a number of the ranks formed by the second semiconductor packages. Semiconductor packages forming a same one of the ranks receive a chip selection signal in common and semiconductor packages forming other ranks receive a different chip selection signal.

BACKGROUND

The example embodiments described herein relate to a semiconductor memory, and more particularly, relate to a memory module and a memory system.

A semiconductor memory device is a memory device which is fabricated using semiconductors such as silicon (Si), germanium (Ge), gallium arsenide (GaAs), indium phosphide (InP), and so on. Semiconductor memory devices are classified into volatile memory devices and nonvolatile memory devices.

Volatile memory devices may lose stored contents at power-off. Volatile memory devices include a static RAM (SRAM), a dynamic RAM (DRAM), a synchronous DRAM (SDRAM), and the like. Nonvolatile memory devices may retain stored contents even at power-off. Nonvolatile memory devices include a read only memory (ROM), a programmable ROM (PROM), an electrically programmable ROM (EPROM), an electrically erasable and programmable ROM (EEPROM), a flash memory device, a phase-change RAM (PRAM), a magnetic RAM (MRAM), a resistive RAM (RRAM), a ferroelectric RAM (FRAM), and so on.

SUMMARY

One aspect of some example embodiments of the inventive concepts is directed to providing a memory module which includes a printed circuit board; first semiconductor packages provided on one surface of the printed circuit board; and second semiconductor packages provided on the other surface of the printed circuit board, wherein the first semiconductor packages and the second semiconductor packages have semiconductor dies that form ranks, a number of the ranks formed by the first semiconductor packages being different from a number of the ranks formed by the second semiconductor packages, and the semiconductor dies in a same rank receive a chip selection signal in common and the semiconductor dies in different ranks receive different chip selection signals.

In one example embodiment, the first semiconductor packages form two ranks and the second semiconductor packages form a single rank.

In one example embodiment, the first semiconductor packages are dual die packages and the second semiconductor packages are mono die packages.

In one example embodiment, the semiconductor dies at a first layer of the first semiconductor packages form a rank and the semiconductor dies at a second layer of the first semiconductor packages form another rank.

In one example embodiment, the first and second semiconductor packages have different structures.

In one example embodiment, a number of semiconductor dies provided at each of the first semiconductor packages is different from a number of semiconductor dies provided at each of the second semiconductor packages.

Another aspect of some example embodiments of the inventive concepts is directed to providing a memory module which includes a plurality of semiconductor dies connected with an external device through a common channel, the plurality of semiconductor dies configured to operate in response to control signals from the external device, wherein the plurality of semiconductor dies form ranks a number of which is not a power of 2, and wherein semiconductor dies in a same rank receive a chip selection signal in common and semiconductor dies in different ranks receive different chip selection signals.

In one example embodiment, the number of ranks formed by the plurality of semiconductor dies corresponds to one of 3, 5, 6, and 7.

In one example embodiment, the memory module further comprises a printed circuit board having a first surface and a second surface. First semiconductor dies of the plurality of semiconductor dies are provided on the first surface, second semiconductor dies of the plurality of semiconductor dies are provided on the second surface. A first number of ranks in the first semiconductor dies is different from a second number of ranks in the second semiconductor dies.

In one example embodiment, the first semiconductor dies are dual die packages provided on the first surface of the printed circuit board and the second semiconductor dies are mono die packages provided on the second surface of the printed circuit board.

Still another aspect of some example embodiments of the inventive concepts is directed to providing a memory system which includes a memory controller; and a plurality of first semiconductor dies connected with the memory controller through a common channel and configured to operate in response to control signals of the memory controller, wherein the plurality of first semiconductor dies form ranks a number of which is not a power of 2, and semiconductor dies in a same rank receive a chip selection signal in common and semiconductor dies in different ranks receive different chip selection signals.

In one example embodiment, the plurality of first semiconductor dies are packed together with the memory controller to form a multi-chip package.

In one example embodiment, the memory controller forms a first package, the plurality of first semiconductor dies form at least one second package, and the first package and the at least one second package form a package-on-package.

In one example embodiment, the memory system further includes a plurality of second semiconductor dies connected with the memory controller through a second common channel and configured to operate in response to control signals from the memory controller.

In one example embodiment, the plurality of first semiconductor dies and the plurality of second semiconductor dies are packed together with the memory controller to form a multi-chip package.

In one example embodiment, the memory controller forms a first package, the plurality of first semiconductor dies and the plurality of second semiconductor dies form at least one second package, and the first package and the at least one second package form a package-on-package.

Still another aspect of some example embodiments is directed to a memory module.

In one or more example embodiments, the memory module includes sets of semiconductor dies arranged in ranks on a printed circuit board, each set of semiconductor dies in a same rank configured to communicate with a controller over a common channel and a number of the ranks arranged on the printed circuit board not being a power of two.

In one example embodiment, the number of the ranks arranged on the printed circuit board corresponds to one of three, five, six, and seven.

In one example embodiment, the memory module is configured to communicate with a memory controller at an operating speeds of up to 1600 megabits per second (Mpbs).

In one example embodiment, the sets of semiconductor dies are packed together with a memory controller to form a multi-chip package.

With example embodiments of the inventive concepts, the number of ranks connected with one channel may be adjusted. Thus, an operating speed supported by semiconductor memories may be optimized. Also, it is possible to provide a memory module and a memory system with the improved operating speed.

DETAILED DESCRIPTION

FIG. 1is a block diagram schematically illustrating a memory system100according to an example embodiment of the inventive concepts.

Referring toFIG. 1, a memory system100may include a memory controller110, a first memory unit120, and a second memory unit130.

The memory controller110may be configured to control the first and second memory units120and130.

The first memory unit120may be configured to communicate with the memory controller110through a first channel CH1. The first memory unit120may perform operations (e.g., a read operation, a write operation, etc.) according to a control of the memory controller110.

The first memory unit120may include a plurality of ranks R1to R3, each of which includes one or more memory chips (or, memory dies). For example, each rank may include one or more DRAM memory chips (or, memory dies).

The ranks R1to R3may receive different chip selection signals CS1, CS2, and CS3from the memory controller110through the first channel CH1. For example, the first rank R1may receive the first chip selection signal CS1from the memory controller110through the first channel CH1. When the first chip selection signal CS1is activated, memory chips (or, memory dies) in the first rank R1may be activated. The second rank R2may receive the second chip selection signal CS2from the memory controller110through the first channel CH1. The third rank R3may receive the third chip selection signal CS3from the memory controller110through the first channel CH1. That is, in the first channel CH1, the chip selection signals CS1to CS3associated with the first to third ranks R1to R3may be transferred through lines which are electrically separated.

It is possible to exchange data in common with the memory controller110through the ranks R1to R3. For example, when the first chip selection signal CS1is activated, the first rank R1may receive data transmitted from the memory controller110through the first channel CH1or send data to the first channel CH1. When the second chip selection signal CS2is activated, the second rank R2may receive data transmitted from the memory controller110through the first channel CH1or send data to the first channel CH1. When the third chip selection signal CS3is activated, the third rank R3may receive data transmitted from the memory controller110through the first channel CH1or send data to the first channel CH1. That is, in the first channel CH1, data associated with the first to third ranks R1to R3may be transferred through common data lines.

In each rank, memory chips (or, memory dies) may share a chip selection signal. For example, when the first chip selection signal CS1is activated, memory chips (or, memory dies) of the first rank R1may be activated at the same time.

In each rank, memory chips (or, memory dies) may exchange data through the first channel CH1independently. For example, data lines of the first channel CH1may be divided into groups corresponding to memory chips (or, memory dies) in each rank, respectively. Each group may be assigned to each memory chip (or, each memory die) in each rank. For example, the first channel CH1may have 64 data lines, each rank may be formed of eight memory chips (or, memory dies), and each memory chip (or, each memory die) may have an 8-bit data channel.

The second memory unit130may have the same structure as the first memory unit120except that the second memory unit130communicates with the memory controller110through the second channel CH2and receives fourth to sixth chip selection signals CS4to CS6, and a description thereof is thus omitted for the sake of brevity.

The memory unit120and the memory unit130may communicate with the memory controller110through channel CH1or channel CH2, respectively. Each of the memory units120/130may include a plurality of ranks R1to R3. Each rank may include a plurality of memory chips (or, memory dies). The plurality of ranks R1to R3communicate with the memory controller110via a plurality of chip selection signals CS1to CS3, respectively.

The number of ranks connected with a channel CH1or channel CH2may not be a power of 2 (e.g. 2^n, where n is a positive integer). For example, the number of ranks connected with one channel CH1or CH2may be one of 3, 5, 6, 7, 9, 10, etc., but not 1, 2, 4, 8 etc.

In example embodiments, memory chips (or, memory dies) may be random access memories such as a DRAM, SRAM, PRAM, MRAM, FRAM, RRAM, and so on. The first and second memory units120and130may be used as a main memory in a computing device.

In example embodiments, each of the first and second memory units120and130may be a memory module. For example, each of the first and second memory units120and130may be one of memory modules such as DIMM (Dual In-line Memory Module), RDIMM (Registered DIMM), FBDIMM (Fully Buffered DIMM), and so on.

FIG. 2is a table illustrating operating speeds of a memory unit according to the number of ranks. Referring toFIGS. 1 and 2, when one memory unit (e.g., a memory module) includes one rank, it may support 1066 megabits per second (Mbps), 1333 Mbps, and 1600 Mbps.

When one memory unit (e.g., a memory module) includes two ranks, it may support 1066 Mbps, 1333 Mbps, and 1600 Mbps.

When one memory unit (e.g., a memory module) includes four ranks, it may support 1066 Mbps, while it may not support 1333 Mbps and 1600 Mbps.

Ranks connected with a channel CH1or CH2may act as a load. As the number of ranks connected with a channel CH1or CH2increases, a load of the channel CH1or CH2may increase. In this case, an operating speed (e.g., a clock frequency) supported at the channel CH1or CH2may decrease.

In a typical memory system, one channel CH1or CH2may be connected with ranks the number of which corresponds to a power of 2. For example, one memory module (DIMM, RDIMM, or FBDIMM) may provide ranks the number of which corresponds to a power of 2. As illustrated inFIG. 2, in the case that there are provided ranks the number of which corresponds to a power of 2, an operating speed may gradually decrease according to an increase in the number of ranks. Thus, in the case that there are provided ranks the number of which corresponds to a power of 2, optimization on the capacity and operating speed of a memory unit120or130connected with one channel may not be performed normally.

For example, in the case that the capacity of a memory unit120or130connected with one channel CH1or CH2increases, the number of ranks of the memory unit120or130may increase. In the case that the operating speed of the memory unit120or130increases, the number of ranks of the memory unit120or130may decrease. With the above description, the number of ranks may be adjusted to optimize the capacity and operating speed of the memory unit120or130.

Referring toFIG. 2, if there are provided ranks the number of which corresponds to a power of 2, it may be difficult to provide a memory unit120or130having an operating speed of 1333 Mbps. That is, although a processor accessing a memory system100supports an operating speed of 1333 Mbps, it may access the memory system10in an operating speed of only 1066 Mbps.

To solve the above-described problem, a memory unit (or, a memory module) according to an example embodiment of the inventive concepts may be configured to provide ranks the number of which corresponds to a number not being a power of 2 (e.g., 3. 5, 6, 7, 9, 10, etc.).

FIG. 3is a table illustrating relationships between channels and ranks according to first and second cases. The first case shows an example in which the number of ranks provided corresponds to power of two and the second case shows an example in which the number of ranks provided does not correspond to a power of two. It is assumed that a memory capacity achieved through an organization of channels and ranks is 48 GB. It is assumed that a capacity of memory chips (or, memory dies) in a rank is 8 GB.

Referring toFIGS. 1 to 3, in the first case, two ranks may be provided at the first channel CH1and four ranks may be provided at the second channel CH2. In the first case, memory chips (or, memory dies) within the ranks that are connected with the first and second channels CH1and CH2may support 1066 Mbps.

In the second case, three ranks may be provided at the first channel CH1and three ranks may be provided at the second channel CH2. In the second case, memory chips (or, memory dies) within the ranks that are connected with the first and second channels CH1and CH2may support 1033 Mbps.

As shown inFIG. 3, in case2where the number of ranks provided at the channels CH1and CH2may not be a power of 2, the memory chips (or, memory dies) may be optimized to run at higher operating speeds that are supported by the memory chips (or, memory dies).

FIG. 4is a diagram schematically illustrating the memory unit (or memory module)120according to an example embodiment of the inventive concepts. In example embodiments, the memory module120may be a DIMM, an RDIMM, or an FBDIMM.

Referring toFIG. 4, the memory module120may include a printed circuit board121, a plurality of dual die packages (DDPs), and a plurality of mono die packages (MDPs).

The dual die packages may be provided on one surface of the printed circuit board121. Each of the dual die packages may provide two ranks R1and R2. The mono die packages may be provided on the other surface of the printed circuit board121. Each of the mono die packages may provide a rank R3.

Each of the dual die packages may include a printed circuit board PCB1, memory dies D1and D2, bonding wires BW1and a molding M1. The memory dies D1and D2may be stacked on the printed circuit board PCB1. The memory dies D1and D2may be connected with the printed circuit board PCB1through the bonding wires BW1. The molding M1may surround and protect the printed circuit board PCB1, the memory dies D1and D2, and the bonding wires BW1. Solder balls SB1may be electrically connected with the memory dies D1and D2through the printed circuit board PCB1and the bonding wires BW1. The solder balls SB1may be electrically connected with the printed circuit board121.

In the dual die packages, the memory dies D1, placed at one layer, from among the memory dies D1and D2may form the rank R1, and the memory dies D2, placed at the other layer, from among the memory dies D1and D2may form the rank R2.

Each of the mono die packages may include a printed circuit board PCB2, a memory die D3, bonding wires BW2and a molding M2. The memory die D3may be stacked on the printed circuit board PCB2. The memory die D3may be connected with the printed circuit board PCB2through the bonding wires BW2. The molding M2may surround and protect the printed circuit board PCB2, the memory die D3, and the bonding wires BW2. Solder balls SB2may be electrically connected with the memory die D3through the printed circuit board PCB2and the bonding wires BW2. The solder balls SB2may be electrically connected with the printed circuit board121.

The memory dies D3of the mono die packages may constitute the rank R3.

As described above, the memory module120may be configured to include different types of memory packages (e.g., DDP and MDP), so that it is formed to include ranks the number of which is not a power of 2.

InFIG. 4, there are illustrated dual die packages and mono die packages. However, the inventive concepts are not limited thereto. While it is appropriate to form the dual die packages to include two memory dies D1and D2, modification and application on a detailed structure (e.g., location, a connection method, etc.) may be made using a well-known packaging method and packaging methods to be developed later. Likewise, while it is appropriate to form the mono die packages to include a memory die D3, modification and application on a detailed structure (e.g., location, a connection method, etc.) may be made using a well-known packaging method and packaging methods to be developed later. This may be applied to example embodiments to be described later.

FIG. 5is a table illustrating memory modules according to example embodiments of the inventive concepts.

Referring toFIG. 5, when the number of ranks is 3, a package including two dies stacked may be provided on one surface of the memory module120or130. In each package having two dies, one die may form the rank R1and the other die may form the rank R2. A package including one die may be provided on the other surface of the memory module. In each package having one die, the one die may form the rank R3. Example embodiment having this configuration may correspond to the memory module120illustrated inFIG. 4.

When the number of ranks is 5, a package including three dies stacked may be provided on one surface of a memory module. In each package having three dies, a first die may form a first rank, a second die may form a second rank, and a third die may form a third rank. A package including two dies stacked may be provided on the other surface of the memory module. In each package having two dies, one die may form a rank and the other die may form the other rank.

When the number of ranks is 6, a package including three dies stacked may be provided on one surface of a memory module. In each package having three dies, a first die may form a first rank, a second die may form a second rank, and a third die may form a third rank. A package including three dies stacked may be provided on the other surface of the memory module. In each package having three dies, a first die may form a first rank, a second die may form a second rank, and a third die may form a third rank.

When the number of ranks is 7, a package including four dies stacked may be provided on one surface of a memory module. In each package having four dies, a first die may form a first rank, a second die may form a second rank, a third die may form a third rank, and a fourth die may form a fourth rank. A package including three dies stacked may be provided on the other surface of the memory module. In each package having three dies, a first die may form a first rank, a second die may form a second rank, and a third die may form a third rank.

FIG. 6is a diagram schematically illustrating a memory system100aaccording to another example embodiment of the inventive concepts.

Referring toFIG. 6, a memory system100amay include first to seventh dies D1to D7.

The first die D1may be a memory controller. The second to seventh dies D2to D7may be memory dies. The first to seventh dies D1to D7may be electrically connected with a printed circuit board PCB through bonding wires BW. Solder balls SB may be electrically connected with the first to seventh dies D1to D7through the printed circuit board PCB and the bonding wires BW. The first to seventh dies D1to D7, the bonding wires BW, and the printed circuit board PCB may be protected by a molding M.

The first to seventh dies D1to D7may form a multi-chip package (MCP) including different types of dies (or, chips).

The second to seventh dies D2to D7may communicate with the first die D1through one channel. The second to seventh dies D2to D7may form ranks the number of which is not a power of 2. For example, the second and third dies D2and D3may form a first rank R1, the fourth and fifth dies D4and D5may form a second rank R2, and the sixth and seventh dies D6and D7may form a third rank R3.

If ranks the number of which is not a power of 2 are provided, it is possible to optimize the operating speed and capacity of the memory system100aformed of the multi-chip package.

FIG. 7is a diagram schematically illustrating a memory system100baccording to still another example embodiment of the inventive concepts.

The memory system100bmay have the same structure as a memory system100aofFIG. 6except that the number of memory dies increases and the memory dies communicate with a memory controller through a plurality of channels, and a description thereof is thus omitted for the sake of brevity.

The 1stdie D1may be a memory controller, and the 2ndto 13thdies D2to D13may be memory dies. The 2ndto 7thdies D2to D7may communicate with the 1stdie D1through a first channel CH1, and the 8thto 13thdies D8to D13may communicate with the 1stdie D1through a second channel CH2.

Memory dies connected with each channel may form ranks the number of which is not a power of 2. For example, in the first channel CH1, the 2ndand 3rddies D2and D3may form a first rank R1, the 4thand 5thdies D4and D5may form a second rank R2, and the 6thand 7thdies D6and D7may form a third rank R3. In the second channel CH2, the 8thand 9thdies D8and D9may form a first rank R1, the 10thand 11thdies D10and D11may form a second rank R2, and the 12thand 13thdies D12and D13may form a third rank R3.

If ranks the number of which is not a power of 2 are provided, it is possible to optimize the operating speed and capacity of the memory system100bformed of a multi-chip package.

FIG. 8is a diagram schematically illustrating a memory system100caccording to still another example embodiment of the inventive concepts.

Referring toFIG. 8, a memory system100cmay include a first package P1and a second package P2.

The first package P1may be a logic package. The first package P1may be a memory controller. The first package P1may include a printed circuit board PCB1, a die D1provided on the printed circuit board PCB1, bonding wires BW1connecting the printed circuit board PCB1and the die D1, a molding M1protecting the die D1and the bonding wires BW1, and solder balls SB1.

The second package P2may be a memory package. The second package P2may include a printed circuit board PCB2, a plurality of dies D2to D7stacked on the printed circuit board PCB2, bonding wires BW2connecting the printed circuit board PCB2and the dies D2to D7, a molding M2protecting the dies D2to D7and the bonding wires BW2, and solder balls SB2. The solder balls SB2may be connected with the printed circuit board PCB1of the first package P1. The solder balls SB1of the first package P1may be electrically connected with the die D1of the first package P1and the dies D2to D7of the second package P2.

The first and second packages P1and P2may constitute a package-on-package (PoP).

The dies D2and D7in the second package P2may form ranks the number of which is not a power of 2. For example, the 2ndand 3rddies D2and D3may form a first rank R1, the 4thand 5thdies D4and D5may form a second rank R2, and the 6thand 7thranks D6and D7may form a third rank R3.

If ranks the number of which is not a power of 2 are provided, it is possible to optimize the operating speed and capacity of the memory system100cformed of the package-on-package.

FIG. 9is a diagram schematically illustrating a memory system100daccording to still another example embodiment of the inventive concepts.

Referring toFIG. 9, a memory system100dmay include a first package P1and a second package P2.

The memory system100dmay have the same structure as a memory system100cofFIG. 8except that the number of memory dies of the second package P2increases and the memory dies communicate with a memory controller of the first package1through a plurality of channels, and a description thereof is thus omitted for the sake of brevity.

The first package P1may include a plurality of dies D2to D13. The 2ndto 7thdies D2to D7may communicate with the first package P1through a first channel CH1, and the 8thto 13thdies D8to D13may communicate with the first package P1through a second channel CH2.

Memory dies connected with each channel may form ranks the number of which is not a power of 2. For example, in the first channel CH1, the 2ndand 3rddies D2and D3may form a first rank R1, the 4thand 5thdies D4and D5may form a second rank R2, and the 6thand 7thdies D6and D7may form a third rank R3. In the second channel CH2, the 8thand 9thdies D8and D9may form a first rank R1, the 10thand 11thdies D10and D11may form a second rank R2, and the 12thand 13thdies D12and D13may form a third rank R3.

If ranks the number of which is not a power of 2 are provided, it is possible to optimize the operating speed and capacity of the memory system100dformed of a package-on-package.

FIG. 10is a block diagram schematically illustrating a computing device1000according to an example embodiment of the inventive concepts.

Referring toFIG. 10, a computing device1000may include a processor1110, a memory1120, storage1130, a modem1140, and a user interface1150.

The processor1110may control an overall operation of the computing device1000, and may perform logical operations. The processor1110may be formed of a system-on-chip (SoC).

The memory1120may communicate with the processor1110. The memory1120may be a working memory (or, a main memory) of the processor1110or the computing device1000. The memory1120may include a volatile memory such as a static RAM, a dynamic RAM, a synchronous DRAM, or the like or a nonvolatile memory such as a flash memory, a phase-change RAM, a magnetic RAM, a resistive RAM, a ferroelectric RAM, or the like.

As described with reference toFIGS. 1 to 9, the memory1120may provide ranks the number of which is not a power of 2 per channel. Thus, it is possible to optimize the operating speed and capacity of the computing device1000including the memory1120and the processor1110communicating with the memory1120.

The storage1130may store data which the computing device1000retains for a long time. The storage1130may include a hard disk drive or a nonvolatile memory such as a flash memory, a phase-change RAM, a magnetic RAM, a resistive RAM, a ferroelectric RAM, or the like.

In example embodiments, the memory1120and the storage1130may be formed of the same type of nonvolatile memories. In this case, the memory1120and the storage1130may be integrated to a semiconductor integrated circuit.

The modem1140may communicate with an external device according to a control of the processor1110. For example, the modem1140may communicate with the external device in a wire or wireless manner. The modem1140may communicate based on at least one of wireless communications manners such as LTE (Long Term Evolution), WiMax, GSM (Global System for Mobile communication), CDMA (Code Division Multiple Access), Bluetooth, NFC (Near Field Communication), WiFi, RFID (Radio Frequency Identification, and so on or wire communications manners such as USB (Universal Serial Bus), SATA (Serial AT Attachment), SCSI (Small Computer Small Interface), Firewire, PCI (Peripheral Component Interconnection), and so on.

The user interface1150may communicate with a user according to a control of the processor1110. For example, the user interface1150may include user input interfaces such as a keyboard, a keypad, a button, a touch panel, a touch screen, a touch pad, a touch ball, a camera, a microphone, a gyroscope sensor, a vibration sensor, and so on. The user interface1150may further include user output interfaces such as an LCD, an OLED (Organic Light Emitting Diode) display device, an AMOLED (Active Matrix OLED) display device, an LED, a speaker, a motor, and so on.

The computing device1000may include a variety of devices such as a computer, a notebook computer, a server, a smart television, and so on. The computing device1000may include a variety of mobile devices a smart phone, a smart pad, a smart camera, and so on.

FIG. 11is a flow chart schematically illustrating a semiconductor memory fabricating method according to an example embodiment of the inventive concepts. In example embodiments, the fabricating method ofFIG. 11may be a memory module fabricating method. However, the inventive concepts are not limited thereto.

Referring toFIG. 11, in operation S110, a plurality of semiconductor memory dies may be prepared.

In operation S120, the semiconductor memory dies may be grouped into a plurality of ranks. In this case, the semiconductor memory dies may be grouped into ranks the number of which is not a power of 2.

In operation S130, semiconductor memory dies in the same rank may be connected with a common chip selection signal. Also, a plurality of ranks may be connected in common with the same data lines. Data lines connected with each rank may be distributed and connected to semiconductor memory dies in a corresponding rank.

In example embodiments, if packaging is performed before operation S120, a memory module described with reference toFIG. 4may be fabricated. Alternatively, if packaging is performed after operation S130, a memory system having a multi-chip package as described with reference toFIG. 6or7or a memory system having a package-on-package design described with reference toFIG. 8or9may be fabricated.