Static source plane in stram

A memory array includes a plurality of magnetic tunnel junction cells arranged in an array. Each magnetic tunnel junction cell is electrically coupled between a bit line and a source line. The magnetic tunnel junction cell is configured to switch between a high resistance state and a low resistance state by passing a write current passing though the magnetic tunnel junction cell. A word line is electrically coupled to a gate of the transistor. The source line is a common source line for the plurality of magnetic tunnel junctions.

BACKGROUND

Fast growth of the pervasive computing and handheld/communication industry generates exploding demand for high capacity nonvolatile solid-state data storage devices. It is believed that nonvolatile memories, especially flash memory, will replace DRAM to occupy the biggest share of memory market by 2009. However, flash memory has several drawbacks such as slow access speed (˜ms write and ˜50-100 ns read), limited endurance (˜103-104programming cycles), and the integration difficulty in system-on-chip (SoC). Flash memory (NAND or NOR) also faces significant scaling problems at 32 nm node and beyond.

Magneto-resistive Random Access Memory (MRAM) is another promising candidate for future nonvolatile and universal memory. MRAM features non-volatility, fast writing/reading speed (<10 ns), almost unlimited programming endurance (>1015cycles) and zero standby power. The basic component of MRAM is a magnetic tunneling junction (MTJ). Data storage is realized by switching the resistance of MTJ between a high-resistance state and a low-resistance state. MRAM switches the MTJ resistance by using a current induced magnetic field to switch the magnetization of MTJ. As the MTJ size shrinks, the switching magnetic field amplitude increases and the switching variation becomes severer. Hence, the incurred high power consumption limits the scaling of conventional MRAM.

Recently, a new write mechanism, which is based upon spin polarization current induced magnetization switching, was introduced to the MRAM design. This new MRAM design, called Spin-Transfer Torque RAM (STRAM), uses a (bidirectional) current through the MTJ to realize the resistance switching. Therefore, the switching mechanism of STRAM is constrained locally and STRAM is believed to have a better scaling property than the conventional MRAM.

However, a number of yield-limiting factors must be overcome before STRAM enters the production stage. One concern is that in traditional STRAM design, two metal tracks are required in each column direction, one is for the source line and the other is for the bit line which sets the minimum width of each column. Also, the write current is asymmetric during writing the high and low resistance states in the STRAM cell. The forward current (current flowing from bit line to source line) is larger than the reverse current (current flowing from the source line to the bit line). The driving transistor size is thus determined by the reverse current requirements.

BRIEF SUMMARY

The present disclosure relates to present disclosure relates to a spin-transfer torque memory array having a single source line. In particular the present disclosure relates to a spin-transfer torque memory array having a single static source line that provides a constant voltage when writing the high resistance data state or the low resistance data state to the memory cell. This structure can reduce STRAM cell dimensions, improve array density, and/or balance the driving currents for the high resistance data state or the low resistance data state to the memory cell.

In an illustrative embodiment, a memory array including a plurality of magnetic tunnel junction cells arranged in an array. Each magnetic tunnel junction cell is electrically coupled between a bit line and a source line. The magnetic tunnel junction cell is configured to switch between a high resistance state and a low resistance state by passing a write current passing though the magnetic tunnel junction cell. A transistor is electrically between the magnetic tunnel junction cell and the source line. A word line is electrically coupled to a gate of the transistor. The source line is a common source line for the plurality of magnetic tunnel junction cells.

In another illustrative embodiment, a memory array includes a plurality of magnetic tunnel junction cells arranged in an array. Each magnetic tunnel junction cell is electrically coupled to a transistor. Each magnetic tunnel junction cell is configured to switch between a high resistance state and a low resistance state by passing a write current passing though the magnetic tunnel junction cell. A plurality of bit lines are arranged in columns. Each bit line column is electrically coupled at least selected magnetic tunnel junction cells along the column. A plurality of word lines are arranged in rows that are orthogonal to the word line rows. Each word line row is electrically coupled to at least selected transistors along the row. A source line electrically connects all the transistors in the array.

An illustrative method of writing to a magnetic tunnel junction cell includes applying a static source line voltage to a common source line. The common source line is electrically coupled to a plurality of magnetic tunnel junction cells forming a memory array. A transistor is electrically between each magnetic tunnel junction cell and the common source line. The method then includes passing a write current through a selected magnetic tunnel junction cell in a first direction by grounding a bit line in electrically connection to the selected magnetic tunnel junction cell, to write a first data state to the magnetic tunnel junction cell, or the method includes passing a write current through a selected magnetic tunnel junction cell in a second direction opposing the first direction by applying a write voltage being greater than the static source line voltage to a bit line in electrically connection to the selected magnetic tunnel junction cell, to write a second data state to the magnetic tunnel junction cell.

DETAILED DESCRIPTION

In the following description, reference is made to the accompanying set of drawings that form a part hereof and in which are shown by way of illustration several specific embodiments. It is to be understood that other embodiments are contemplated and may be made without departing from the scope or spirit of the present disclosure. The following detailed description, therefore, is not to be taken in a limiting sense. The definitions provided herein are to facilitate understanding of certain terms used frequently herein and are not meant to limit the scope of the present disclosure.

The present disclosure relates to a spin-transfer torque memory array having a single source line. In particular the present disclosure relates to a spin-transfer torque memory array having a single static source line that provides a constant voltage when writing the high resistance data state or the low resistance data state to the memory cell. This structure can reduce STRAM cell dimensions, improve array density, and/or balance the driving currents for the high resistance data state or the low resistance data state to the memory cell. While the present disclosure is not so limited, an appreciation of various aspects of the disclosure will be gained through a discussion of the examples provided below.

FIG. 1is a cross-sectional schematic diagram of an illustrative magnetic tunneling junction (MTJ) cell10in the low resistance state andFIG. 2is a cross-sectional schematic diagram of the illustrative MTJ cell10in the high resistance state. The MTJ cell can be any useful memory cell that can switch between a high resistance state and a low resistance state. In many embodiments, the variable resistive memory cell described herein is a spin-transfer torque memory cell.

The MTJ cell10includes a ferromagnetic free layer12and a ferromagnetic reference (i.e., pinned) layer14. The ferromagnetic free layer12and a ferromagnetic reference layer14are separated by an oxide barrier layer13or tunnel barrier. A first electrode15is in electrical contact with the ferromagnetic free layer12and a second electrode16is in electrical contact with the ferromagnetic reference layer14. The ferromagnetic layers12,14may be made of any useful ferromagnetic (FM) alloys such as, for example, Fe, Co, Ni and the insulating barrier layer13may be made of an electrically insulating material such as, for example an oxide material (e.g., Al2O3or MgO). Other suitable materials may also be used.

The electrodes15,16electrically connect the ferromagnetic layers12,14to a control circuit providing read and write currents through the ferromagnetic layers12,14. The resistance across the MTJ cell10is determined by the relative orientation of the magnetization vectors or magnetization orientations of the ferromagnetic layers12,14. The magnetization direction of the ferromagnetic reference layer14is pinned in a predetermined direction while the magnetization direction of the ferromagnetic free layer12is free to rotate under the influence of a spin torque. Pinning of the ferromagnetic reference layer14may be achieved through, e.g., the use of exchange bias with an antiferromagnetically ordered material such as PtMn, IrMn and others.

FIG. 1illustrates the MTJ cell10in the low resistance state where the magnetization orientation of the ferromagnetic free layer12is parallel and in the same direction of the magnetization orientation of the ferromagnetic reference layer14. This is termed the low resistance state or “0” data state.FIG. 2illustrates the MTJ cell10in the high resistance state where the magnetization orientation of the ferromagnetic free layer12is anti-parallel and in the opposite direction of the magnetization orientation of the ferromagnetic reference layer14. This is termed the high resistance state or “1” data state.

Switching the resistance state and hence the data state of the MTJ cell10via spin-transfer occurs when a current, passing through a magnetic layer of the MTJ cell10, becomes spin polarized and imparts a spin torque on the free layer12of the MTJ cell10. When a sufficient spin torque is applied to the free layer12, the magnetization orientation of the free layer12can be switched between two opposite directions and accordingly the MTJ cell10can be switched between the parallel state (i.e., low resistance state or “0” data state) and anti-parallel state (i.e., high resistance state or “1” data state) depending on the direction of the current.

The illustrative spin-transfer torque MTJ cell10may be used to construct a memory device that includes multiple variable resistive memory cells where a data bit is stored in magnetic tunnel junction cell by changing the relative magnetization state of the free magnetic layer12with respect to the pinned magnetic layer14. The stored data bit can be read out by measuring the resistance of the cell which changes with the magnetization direction of the free layer relative to the pinned magnetic layer. In order for the spin-transfer torque MTJ cell10to have the characteristics of a non-volatile random access memory, the free layer exhibits thermal stability against random fluctuations so that the orientation of the free layer is changed only when it is controlled to make such a change. This thermal stability can be achieved via the magnetic anisotropy using different methods, e.g., varying the bit size, shape, and crystalline anisotropy. Additional anisotropy can be obtained through magnetic coupling to other magnetic layers either through exchange or magnetic fields. Generally, the anisotropy causes a soft and hard axis to form in thin magnetic layers. The hard and soft axes are defined by the magnitude of the external energy, usually in the form of a magnetic field, needed to fully rotate (saturate) the direction of the magnetization in that direction, with the hard axis requiring a higher saturation magnetic field.

FIG. 3is a graph of a static R-V sweep curve of a MTJ cell. When applying a positive voltage on the second electrode16inFIG. 1or2, the MTJ cell10enters the positive applied voltage region inFIG. 3and switches from the high resistance state (FIG. 2) to the low resistance state (FIG. 1). When applying a positive voltage on the first electrode15inFIG. 1or2, the MTJ cell10enters the negative applied voltage region inFIG. 3. The resistance of the MTJ cell switches from the low resistance state (FIG. 1) to the high resistance state (FIG. 2).

Let RHand RLdenote the high and low magnet resistance, respectively. We define the Tunneling Magneto Resistance Ratio (TMR) as TMR=(RH−RL)/RL. Here RH, RLand TMR are determined by also the sensing current or voltage, as shown inFIG. 3. Generally, a large TMR makes it easier to distinguish the two resistance states of the MTJ cell.

FIG. 4is schematic circuit diagrams of a memory apparatus11. The memory apparatus11includes magnetic tunneling junction (MTJ) cell20electrically between a bit line BL and a source line SL. The magnetic tunneling junction (MTJ) cell20is configured to switch between a high resistance state and a low resistance state, as described above. The transistor21is electrically between the source line SL and the MTJ cell20. The transistor21is electrically coupled to a word line WL via a gate contact of the transistor21. The transistor21can be any useful transistor such as, for example, a NMOS or PMOS semiconductor device. In many embodiments, the transistor21can be electrically coupled to the MTJ cell20in any useful internal electrical connection such as with an electrode22.

FIG. 5is a top view schematic diagram of a traditional memory array50. A side view of in individual MTJ cell apparatus is shown inFIG. 4. The memory array50includes four MTJ cells MTJ1, MTJ2, MTJ3, MTJ4arranged in a 2×2 array. The memory array50includes two word lines WL1, WL2, two bit lines BL1, BL2, and two source lines SL1, SL2to operate the 2×2 memory array50. It is understood that while a 2×2 array is illustrated, the memory array50can includes any number of MTJ cells arranged in an array. As illustrated, each column (or row) of the memory array50requires a separate source line SL1and SL2to operate the 2×2 memory array50. The BL1and SL1operate MTJ1and MTJ2depending on whether WL1or WL2is activated. The BL2and SL2operate MTJ3and MTJ4depending on whether WL1or WL2is activated.

FIG. 6is a top view schematic diagram of an illustrative memory array60. A side view of in individual MTJ cell apparatus is shown inFIG. 4. The memory array60includes four MTJ cells MTJ1, MTJ2, MTJ3, MTJ4arranged in a 2×2 array. The memory array56includes two word lines WL1, WL2, two bit lines BL1, BL2, and a common source lines SL to operate the 2×2 memory array60. It is understood that while a 2×2 array is illustrated, the memory array60can includes any number of MTJ cells arranged in an array. As illustrated, the memory array60requires a single common source line SL to operate the 2×2 (or any size) memory array60. This configuration can reduce the size of a memory array by at least 10% or at least 20% or at least 30%, as shown in Table 1 below, as compared to the configuration illustrated inFIG. 5as compared to the traditional layout constriction. If considering the driving ability of the two write currents, this configuration can balance the write currents (for writing the high and low resistance states) to be within 30% of each other, or within 20% of each other, or within 10% of each other, as shown in Table 1 below. In many embodiments, both the size reduction and balancing the driving ability of the two write currents are taken into consideration.

While the source line is illustrated as a line, it is understood that the source line can be a described as a source plane where the source plane electrically connects all the transistors in the array at the same time. Activation of the particular word line allows current to flow through the particular MTJ cell for writing to the MTJ cell, as described above.

When writing to each MTJ cell a fixed static voltage (VDD/2) is provided so there is no charging/discharging on it. During writing “1” operation, the BL voltage is set to GND so that driving current flow from SL to BL. During writing “0” operation, the BL is connected to VDD and hence, driving current should flow from BL to SL. The reading scheme of this design could be as same as conventional STRAM—a small read current flow is provided to flow from BL to SL.

FIG. 7Ais schematic circuit diagram of a traditional STRAM in writing “0” mode.FIG. 7Bis schematic circuit diagram of a traditional STRAM in writing “1” mode. When writing the “0” mode, the traditional source line SL is set to ground and the bit line BL is set to the write voltage VDD. The write voltage VDD can be provided by a first voltage generator (not show). The first voltage generator can be provided on-chip. The word line WL is set to an activation voltage VDD to allow current to flow through the transistor. When writing the “1” mode, the traditional source line SL is set to the write voltage VDD and the bit line BL is set to ground. The word line WL is set to an activation voltage VDD to allow current to flow through the transistor.

FIG. 8Ais schematic circuit diagram of an illustrative STRAM in writing “0” mode.FIG. 8Bis schematic circuit diagram of an illustrative STRAM in writing “1” mode’. When writing the “0” mode, the source line SL is set to a voltage value between the write voltage and ground and is denoted as VDD/2 and the bit line BL is set to the write voltage VDD. The write voltage VDD can be provided by a first voltage generator (not show) and the source line static voltage can be provided by a second voltage generator (not shown). The first voltage generator and the second voltage generator can be provided on-chip. The word line WL is set to an activation voltage VDD to allow current to flow through the transistor. When writing the “1” mode, the source line SL remains set to a voltage value between the write voltage and ground and is denoted as VDD/2 and the bit line BL is set to ground. The word line WL is set to an activation voltage VDD to allow current to flow through the transistor. Thus, in both writing operations, the source line is set to a static voltage level that can be, in many embodiments, equal to VDD/2.

Table 1 compares the simulated writing current of conventional STRAM design and our Static Source design described herein. All the simulations were done at TSMC 130 nm technology node. In this table, the active current measures the current flowing through bit cell when bit cell is selected (WL=1). The active current is normalized to the minimal required writing current.

The simulation result shows that the forward current is 45% more than reverse current, which is the minimal required writing current, in a conventional STRAM bit cell. However, if using the same driving transistor size in our new design, forward and reverse currents are more balanced: both of them are around 30% more than the minimal required writing current. In other words, the driving transistor in the new design can be reduced to 75% of conventional design, while we can achieve the same driving ability.

The technique can be further improved by dynamically changing a body bias of the driving transistor: When a row is selected, we can dynamically increase its body bias in order to get higher driving current. Table 2 shows the simulation results if we apply dynamic body biasing on the proposed STRAM cells. The required transistor size can be further reduced to 65% of conventional design and it can still achieve the minimal driving ability required.

The tables above illustrate that the disclosed static source plane memory cell architecture improves the driving symmetry of the STRAM memory cell and can also reduce the physical footprint of the STRAM memory cell, allowing for an increase in memory density. The proposed STRAM memory array structure having a single source plane for the array balances the forward and reverse driving ability of the STRAM memory cell and can also reduce the driving transistor size, leading to additional scaling of the memory array.

FIG. 9is a flow diagram of an illustrative method of writing to a memory array100. The method includes applying a static source line voltage to a common source line at block101. The common source line is electrically coupled to a plurality of magnetic tunnel junction cells forming a memory array. A transistor is electrically between each magnetic tunnel junction cell and the common source line. If writing the “0” data state to the STRAM cell at block102, a write current is passed through a selected magnetic tunnel junction cell in a first direction by applying a write voltage being greater than the static source line voltage to a bit line in electrically connection to the selected magnetic tunnel junction cell. The MTJ is then in the “0” data state at block104. If writing the “1” data state to the STRAM cell at block103, a write current is passed through a selected magnetic tunnel junction cell in a second direction opposing the first direction by grounding the bit line in electrically connection to the selected magnetic tunnel junction cell. The MTJ is then in the “1” data state at block105.

Thus, embodiments of the STATIC SOURCE PLANE IN STRAM are disclosed. The implementations described above and other implementations are within the scope of the following claims. One skilled in the art will appreciate that the present disclosure can be practiced with embodiments other than those disclosed. The disclosed embodiments are presented for purposes of illustration and not limitation, and the present invention is limited only by the claims that follow.