Semiconductor packaging device

A semiconductor packaging device is provided. Semiconductor package groups, a side retainer wall, and a filling layer may be located on a base plate. The side retainer wall may be located around the semiconductor package groups. The filling layer may be located between the side retainer wall and the semiconductor package groups.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims the benefit of priority under 35 U.S.C. §119 from Korean Patent Application No. 10-2008-0104428, filed on Oct. 23, 2008, the contents of which are hereby incorporated herein by reference in their entirety.

BACKGROUND

1. Field of the Invention

Example embodiments relate to a semiconductor packaging device in which at least one side retainer wall is located around semiconductor package groups on a base plate.

2. Description of the Related Art

Recently, to accommodate the trend of having multi-function electronic devices, semiconductor packaging devices have been manufactured on a single base plate using semiconductor package groups. The base plate may have interconnections to connect the package groups to other groups or devices. The semiconductor package groups may be attached to the base plate using a filling layer. The filling layer may be injected through a dispenser nozzle in a semiconductor packaging assembly line. However, the filling layer has to be formed on the base plate to a sufficient thickness and for a sufficient period of time so that only the top surfaces of the semiconductor packaging groups are exposed. The filling layer may flow into a space between the semiconductor packaging groups and partially leak out through edges of the base plate.

SUMMARY

Example embodiments provide a semiconductor packaging device which is suitable to physically control the flow of the filling layer from the semiconductor package groups.

Example embodiments also provide a semiconductor packaging device having at least one side retainer wall which is located around semiconductor package groups on a base plate.

Features and/or utilities of the present general inventive concept may be realized by a semiconductor packaging device including a base plate, a plurality of first semiconductor package groups located on the base plate, a side retainer wall which extends upward from a main surface of the base plate and surrounds the first semiconductor package groups, and a filling layer which contacts the side retainer wall and is located between the first semiconductor package groups.

Each of the first semiconductor package groups may include semiconductor packages which are sequentially stacked, the side retainer wall may contact sides of the first semiconductor package groups, and the filling layer may be located between the semiconductor packages of each of the first semiconductor package groups.

The semiconductor packaging device may further include a plurality of second semiconductor package groups located on a surface opposite to the main surface of the base plate, and the second semiconductor package groups may either have the same structure as the first semiconductor package groups or a different structure from the first semiconductor package groups.

Other features and/or utilities of the present general inventive concept may be realized by a semiconductor packaging device including a base plate, a plurality of first semiconductor package groups located on the base plate, side retaining walls which extend upward from a main surface of the base plate and are located adjacent to the first semiconductor package groups, and a filling layer which contacts the side retainer walls and is located between the first semiconductor package groups.

Each of the first semiconductor package groups may include semiconductor packages which are sequentially stacked, the side retainer walls may be located between the first semiconductor package groups and at locations corresponding to the outermost semiconductor package groups among the first semiconductor package groups and may contact sides of the first semiconductor package groups, and the filling layer may be located between the semiconductor packages of each of the first semiconductor package groups.

The semiconductor packaging device may further include a plurality of second semiconductor package groups located on a surface opposite to the main surface of the base plate, and the second semiconductor package groups may have either the same structure as the first semiconductor package groups or a different structure than the first semiconductor package groups.

Additional features and/or utilities of the present general inventive concept may include a semiconductor packaging device including a base plate, a plurality of first semiconductor package groups located on the base plate, side retainer walls which extend upward from a main surface of the base plate and are located along a side of the first semiconductor package groups, and a filling layer which contacts the side retainer walls and is located between the first semiconductor package groups.

Each of the first semiconductor package groups may include semiconductor packages which are sequentially stacked, the side retainer walls may be located between the first semiconductor package groups and may contact sides of the first semiconductor package groups, and the filling layer may be located between the semiconductor packages of each of the first semiconductor package groups.

In example embodiments, the semiconductor packaging device may further include a plurality of second semiconductor package groups located on a surface opposite to the main surface of the base plate, and the second semiconductor package groups may have either the same structure as the first semiconductor package groups or a different structure than the first semiconductor package groups.

Other features and/or utilities of the present general inventive concept may be realized by a semiconductor packaging device including a substrate, a first plurality of stacked semiconductor devices on a first surface of the substrate, a first retainer wall adjacent to the first plurality of stacked semiconductor devices, and a first filling to fill spaces defined by the first retainer wall and the first plurality of stacked semiconductor devices.

The first retainer wall may be located along only a first side of the first plurality of semiconductor devices and a second side opposite the first side. Alternatively, the first retainer wall may entirely surround the first plurality of stacked semiconductor devices.

The first plurality of stacked semiconductor devices may be arranged in a row on the substrate, and the first retainer wall may include at least a first side portion on a first side of the first plurality of stacked semiconductor devices, at least a second side portion on a second side of the first plurality of stacked semiconductor devices, and at least one end portion at each end of the row of stacked semiconductor devices, and the first retainer wall may have at least one gap between two adjacent side portions, or between a side portion and an adjacent end portion.

The first retainer wall may contact a first side of each stacked semiconductor device on a first side of the row, a second side of each semiconductor device on a second side of the row opposite the first side, and a side of each stacked semiconductor device at each end of the row. Alternatively, the first retainer wall may contact only a first side of each stacked semiconductor device on a first side of the row and a second side of each semiconductor device on a second side of the row opposite the first side.

The first retainer wall may be shorter than an upper surface of an upper semiconductor device of each one of the first plurality of stacked semiconductor devices. Alternatively, the first retainer wall may be substantially the same height as an upper surface of an upper semiconductor device of at least one of the first plurality of stacked semiconductor devices. Alternatively, the first retainer wall may be higher than an upper surface of an upper semiconductor device of at least one of the first plurality of stacked semiconductor devices.

An upper surface of the first filling may be lower than an upper surface of an upper semiconductor device of each one of the first plurality of stacked semiconductor devices. Alternatively, an upper surface of the first filling may cover an upper surface of an upper semiconductor device of at least one of the first plurality of stacked semiconductor devices.

The first retainer wall may not contact any one of the first plurality of stacked semiconductor devices. The first filling may fill a space between the first retainer wall and the first plurality of stacked semiconductor devices.

The first retainer wall may contact at least a side part of at least one of the first plurality of stacked semiconductor devices.

The semiconductor packaging device may further include a second plurality of stacked semiconductor devices located on a second surface of the substrate opposite the main surface, a second retainer wall adjacent to the second plurality of stacked semiconductor devices, and a second filling to fill spaces defined by the second retainer wall and the second plurality of stacked semiconductor devices.

The second plurality of stacked semiconductor devices may be located at positions on the second surface of the substrate corresponding to locations of the first plurality of stacked semiconductor devices on the main surface of the substrate.

The first plurality of stacked semiconductor devices may be arranged in at least two adjacent rows. The first retainer wall may surround both of the two adjacent rows. Alternatively, the first retainer wall may surround a first row of the two adjacent rows. A second retainer wall may surround a second row of two adjacent rows.

The first retainer wall may include a first surface adjacent to the first plurality of stacked semiconductor devices and a second surface opposite the first surface, and each of the first and second surfaces of the first retainer wall may be perpendicular to the main surface of the substrate. Alternatively, the first surface of the first retainer wall may be perpendicular to the main surface of the substrate, and the second surface of the first retainer wall may be curved such that the first retainer wall is wider at a base adjacent to the substrate than at an end farthest from the substrate.

The material that makes up the first filling may have a higher viscosity than a material that makes up the first retainer wall.

The first retainer wall may include an insulation material, and the first filling may include an insulation material. The first filling may include a material to conduct heat.

Additional features and/or utilities of the present general inventive concept may be realized by a base plate of a semiconductor packaging device, the base plate including a substrate, a plurality of pads on a main surface of the substrate to receive a plurality of semiconductor devices, and a retainer wall area adjacent to the plurality of pads to form a retainer wall thereon.

The retainer wall area may have a rougher surface texture than the rest of the main surface of the substrate. The plurality of pads may include electrically conductive plates mounted on wiring on the substrate. The plurality of pads may include electrically conductive plates embedded in the substrate.

Additional features and/or utilities of the present general inventive concept may be realized by a computing device including a semiconductor packaging device and a controller. The semiconductor packaging device may include a substrate, a plurality of stacked semiconductor devices on the substrate, a retainer wall adjacent to the plurality of stacked semiconductor devices, and a filling to fill spaces defined by the retainer wall and the plurality of stacked semiconductor devices. The controller may control at least one semiconductor device of the plurality of stacked semiconductor devices.

At least one of the stacked semiconductor devices may be memory, and the controller may control a read operation from and a write operation to the memory.

DETAILED DESCRIPTION OF THE EMBODIMENTS

Various example embodiments will now be described more fully with reference to the accompanying drawings in which some example embodiments are shown, wherein like reference numerals refer to the like elements throughout. The embodiments are described below to explain the present general inventive concept by referring to the figures. In the drawings, the thicknesses of layers and regions may be exaggerated for clarity.

Detailed illustrative embodiments are disclosed herein. However, specific structural and functional details disclosed herein are merely representative for purposes of describing example embodiments. This general inventive concept, however, may be embodied in many alternate forms and should not be construed as limited to only example embodiments set forth herein.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of example embodiments. As used herein, the singular forms “a,” “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises,” “comprising,” “includes” and/or “including,” when used herein, specify the presence of stated features, integers, steps, operations, elements and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components and/or groups thereof. Spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or a relationship between a feature and another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as “below” or “beneath” other elements or features would then be oriented “above” the other elements or features. Thus, for example, the term “below” can encompass both an orientation which is above as well as below. For example, a term “filling layer” can be used to describe an “under-fill” in a semiconductor packaging line, and a term “side retainer wall” can be used to describe a “side fill” which aids a filling layer in a semiconductor packaging line. The device may be otherwise oriented (rotated 90 degrees or viewed or referenced at other orientations) and the spatially relative descriptors used herein should be interpreted accordingly.

To more specifically describe example embodiments, various aspects will be described in detail with reference to the attached drawings. However, the inventive concept is not limited to example embodiments described.

A semiconductor packaging device according to example embodiments will be described with reference toFIGS. 1A-Eand2A-B.

FIGS. 1A-1Eare plan views of a semiconductor packaging device according to example embodiments, andFIGS. 2A-2Bare schematic perspective views of a portion of the semiconductor packaging device ofFIG. 1A.

Referring toFIGS. 1A-1Eand2A-2B, a semiconductor packaging device80may include a plurality of semiconductor package groups SPG1to SPGn located on a main surface of a substrate or base plate10. The main surface is defined as a first surface upon which semiconductor package groups may be located. It may be substantially planar and of a sufficient size to accommodate a plurality of semiconductor package groups. Semiconductor package groups and other elements may also be located on a second surface opposite the main surface (as shown, for example, inFIG. 7E), although only the main surface is shown inFIGS. 1A-1E. The surface opposite the main surface is the surface on the other side of the base plate10as the main surface. The semiconductor package groups on the surface opposite the main surface may be of a same quantity as the semiconductor package groups SPG1to SPGn, for example. The base plate10may be a printed circuit board (PCB). Each of the semiconductor package groups SPG1to SPGn may include lower and upper semiconductor packages30and50which may be sequentially stacked as shown inFIGS. 1 and 2.

The lower and upper semiconductor packages30and50may include the same semiconductor chip or different semiconductor chips, respectively. Each of the semiconductor package groups SPG1to SPGn may include two or more semiconductor packages. The semiconductor package30or50of each of the semiconductor package groups SPG1to SPGn may include bumps24and44. The lower and upper semiconductor packages30and50may be electrically connected with the base plate10through the bumps24and44. The base plate10may have pads to electrically connect to the bumps24to transmit data, power, or heat to and from the semiconductor package groups SPG1to SPGn. The semiconductor package groups on the surface opposite the main surface of the base plate10may have the same elements as the semiconductor package groups SPG1to SPGn.

A side retainer wall66may be located on the base plate10as shown inFIGS. 1A-1E,2A, and2B. The side retainer wall66may be configured to surround the semiconductor package groups SPG1to SPGn along guide lines P1and P2shown inFIG. 1. The side retainer wall66may extend upward from the main surface of the base plate10as shown inFIGS. 2A and 2B. The side retainer wall66may contact sides of the semiconductor package groups SPG1to SPGn. The side retainer wall66may contact sides of the lower and upper semiconductor packages30and50of each of the semiconductor package groups SPG1to SPGn, as shown inFIGS. 1A-1D. Alternatively, the side retainer wall66may not contact sides of the semiconductor package groups SPG1to SPGn, as shown inFIG. 1E.

As shown inFIGS. 1A and 1C, the retainer wall66may have side portions to correspond to a length of a row of semiconductor package groups SPG1to SPGn to restrict the flow of a filling material70in a direction Y. As shown inFIGS. 1A and 1D, the retainer wall may also have end portions66cto restrict the flow of a material in a direction X. As shown inFIGS. 1A and 1B, the retainer wall66may entirely surround the semiconductor package groups SPG1to SPGn to restrict the flow of a filling material70in both the direction X and the direction Y.

The filling layer70as shown inFIG. 2BandFIGS. 8A to 8Fmay be contained by the side retainer wall66and may be formed on the base plate10. The filling layer70may fill in the area A between the semiconductor package groups SPG1to SPGn. The filling layer70may also fill in the areas between the lower and upper semiconductor packages30and50of each of the semiconductor package groups SPG1to SPGn. The filling layer70may be defined by the retainer wall66to fill an area surrounding the semiconductor package groups SPG1to SPGn. The filling layer70may be formed to expose top surfaces of the semiconductor package groups SPG1to SPGn. The base plate10may have structures of the same form as the side retainer wall66, the filling layer70, and the semiconductor package groups SPG1to SPGn on the surface opposite to the main surface of the base plate10.

As shown inFIG. 1B, the retainer wall66may entirely surround a series of semiconductor package groups SPG1-SPGn. As shown inFIG. 1C, the retainer wall66may include only side portions66ato leave the ends of the series of semiconductor package groups SPG1-SPGn exposed. As shown inFIG. 1D, the retainer wall66may include side portions66band end portions66cwith spaces located between side portions66band other side portions66band/or spaces between side portions66band the end portions66c.

Next, a method of manufacturing a semiconductor packaging device according to example embodiments will be described.

FIG. 3is a schematic perspective view of the semiconductor package groups of the semiconductor packaging device ofFIG. 1A.FIGS. 6A to 6Dare cross-sectional views taken along lines I-I′, II-II′, III-III′, and IV-IV′ ofFIG. 1A, illustrating an initial step in manufacturing a semiconductor packaging device according to example embodiments.

Referring toFIG. 3andFIGS. 6A to 6D, the base plate10may be prepared as shown inFIGS. 6A to 6D. The base plate10may include a printed circuit board. The base plate10may have interconnections including pads15as shown inFIGS. 6A to 6D. The base plate10may be made of a flexible material or a non-flexible material. The lower semiconductor packages30may be mounted on the base plate10as shown inFIG. 3andFIGS. 6A to 6D. The lower semiconductor packages30may include lower bumps24and lower pads28which protrude from the corresponding semiconductor packages30and are sequentially stacked in one or more rows as shown inFIGS. 6A to 6D.

The number of lower bumps24may correspond to the number of pads15. Likewise, the number of lower pads28may correspond to the number of lower bumps24. The lower bumps24may contact the pads15of the base plate10as shown inFIGS. 6A to 6D. Therefore, the pads15, the lower bumps24, and the lower pads28may electrically connect the base plate10to the lower semiconductor packages30. The pads15, the lower bumps24, and the lower pads28may be electrically conductive. The upper semiconductor packages50may be mounted above the lower semiconductor packages30, respectively, as shown inFIG. 3andFIGS. 6A to 6D.

The upper semiconductor package50may include upper bumps44and upper pads48which protrude from the upper semiconductor packages50and are sequentially stacked as shown inFIGS. 6A to 6D. The upper bumps44may come in contact with corresponding circuits (not shown) of the lower semiconductor packages30as shown inFIGS. 6A to 6D. The upper bumps44and the upper pads48may have electrical conductivity. Therefore, the upper semiconductor packages50may be electrically connected to the base plate10through the lower semiconductor packages30.

According to the example embodiments, the lower and upper semiconductor packages30and50may be included in each of the semiconductor package groups SPG1to SPGn located on the base plate10as shown inFIG. 3andFIGS. 6A to 6D.

Next, a method of manufacturing a semiconductor packaging device according to example embodiments will be described in further detail.

FIG. 4is a schematic perspective view of a portion of the semiconductor packaging device ofFIGS. 1A and 1Daccording to an embodiment of the present general inventive concept.FIGS. 7A to 7Dare cross-sectional views taken along lines I-I′, II-II′, III-III′, and IV-IV′ ofFIG. 1A, illustrating an intermediate step in manufacturing the semiconductor packaging device according to an embodiment of the present general inventive concept.

FIGS. 7E and 7Fare cross-sectional views taken along lines I-I′ and III-III′ ofFIG. 1A, illustrating a final step in manufacturing the semiconductor packaging device according to an embodiment of the present general inventive concept.

Referring toFIGS. 1A,1D,4, andFIGS. 7A to 7D, side retainer walls66band66cmay be formed on the base plate10. The side retainer walls66band66cmay be formed along guide lines P1and P2as shown inFIG. 1Ato be adjacent to the semiconductor package groups SPG1to SPGn. The side retainer walls66band66cmay extend upward from a main surface of the base plate10. The side retainer walls66band66cmay be formed with gaps between adjacent side portions66band/or between the side portions66band the end portions66c.

The side retainer walls66bmay be formed along sides of the semiconductor package groups SPG1to SPGn as shown inFIGS. 1A,1D,4, and7B. Retainer walls66cmay be formed at locations corresponding to the semiconductor package groups SPG1and SPGn at the ends of a row of semiconductor package groups SPG1to SPGn as shown inFIGS. 1A,1D,4,7C, and7D. The side retainer walls66band66cmay contact sides of the semiconductor package groups SPG1to SPGn as shown inFIGS. 4,7C, and7D. The side retainer walls66band66cmay include a viscous material having insulating properties.

The semiconductor package groups SPG1to SPGn and the side retainer walls66bmay define spaces A on the base plate10as shown inFIGS. 1A,1D, and4. A filling layer70may be formed on the base plate10as shown inFIGS. 7A to 7D. The filling layer70may be injected onto the base plate10through a dispenser nozzle in a semiconductor packaging assembly line. The filling layer70may fill the spaces A while contacting sidewalls of the side retainer walls66band66c. In this manner, the filling layer70may be formed between the lower and upper semiconductor packages30and50of each of the semiconductor package groups SPG1to SPGn.

The filling layer70may include a viscous material having insulating properties. The filling layer70may have greater viscosity than the side retainer walls66band66c. The side retainer walls66band66cmay control the flow of the filling layer70and confine the filling layer70within the spaces around the semiconductor package groups SPG1to SPGn. The side retainer walls66band66cmay help to attach the semiconductor package groups SPG1to SPGn to the base plate10by bonding with the filling layer70. The filling layer70may be formed to expose top surfaces of the semiconductor package groups SPG1to SPGn.

Referring toFIGS. 7E and 7F, the semiconductor package groups SPG1to SPGn ofFIGS. 7A to 7Dmay be formed on the base plate10. The semiconductor package groups SPG1to SPGn, the side retainer walls66band66c, and the filling layer70may together form an upper package group UPG located on the main surface of the base plate10as shown inFIGS. 7E and 7F. According to an embodiment, a plurality of upper package groups UPG may be mounted in a series on the base plate10. The upper package groups UPG may include the lower and upper semiconductor packages30and50. The upper package groups may also include additional semiconductor packages stacked on the top semiconductor package50.

The base plate10may have lower package groups LPG mounted onto a surface opposite the main surface of the base plate10as shown inFIGS. 7E and 7F. The lower package groups LPG may include a plurality of semiconductor package groups SPG11to SPGn1. The semiconductor package groups SPG11to SPGn1of the lower package group LPG may have the same elements as the semiconductor package groups SPG1to SPGn of the upper package group UPG. The lower package groups LPG may be mounted in a series on the base plate10. The lower package group LPG may include the lower and upper semiconductor packages30and50and may include additional semiconductor packages stacked on the upper semiconductor packages50.

The semiconductor package groups SPG11to SPGn1of the lower package group LPG may have a same quantity as the semiconductor package groups SPG1to SPGn of the upper package group UPG. Alternatively, the semiconductor package groups SPG11to SPGn1of the lower package group LPG may have a different quantity than the semiconductor package groups SPG1to SPGn of the upper package group UPG. In this manner, the lower package group LPG and the upper package group UPG may make up the semiconductor packaging device80together with the base plate10as shown inFIGS. 7E and 7F.

FIG. 5is a schematic perspective view of a portion of the semiconductor packaging device ofFIGS. 1A and 1Baccording to an embodiment of the present general inventive concept.FIGS. 8A to 8Dare cross-sectional views taken along lines I-I′, II-II′, III-III′, and IV-IV′ ofFIG. 1, illustrating an intermediate step in manufacturing the semiconductor packaging device according to an embodiment of the present general inventive concept.

FIGS. 8E and 8Fare cross-sectional views taken along lines I-I′ and III-III′ ofFIG. 1A, illustrating a final step in manufacturing the semiconductor packaging device according to an embodiment of the present general inventive concept.

Referring toFIG. 5andFIGS. 8A to 8D, a side retainer wall66may be formed on the base plate10. The side retainer wall66may be formed along guide lines P1and P2as shown inFIG. 1Ato entirely surround the semiconductor package groups SPG1to SPGn. The side retainer wall66may extend upward from the main surface of the base plate10. As such, the side retainer wall66may come in contact with sides of the semiconductor package groups SPG1to SPGn as shown inFIGS. 5,8A,8C, and8D. The side retainer wall66may include a viscous material having insulating properties.

The semiconductor package groups SPG1to SPGn and the retainer walls66may define spaces A as shown inFIGS. 1A and 5. A filling layer70may be formed on the base plate10as shown inFIGS. 8A to 8D. The filling layer70may fill the spaces A while contacting sidewalls of the side retainer walls66. As such, the filling layer70may be formed between the lower and upper semiconductor packages30and50of each of the semiconductor package groups SPG1to SPGn. The filling layer70may have greater viscosity than the side retainer walls66. The side retainer walls66may control the flow of the filling layer70and confine the filling layer70within the area around the semiconductor package groups SPG1to SPGn. The side retainer walls66may help to attach the semiconductor package groups SPG1to SPGn to the base plate10.

Referring toFIGS. 8E and 8F, the semiconductor package groups SPG1to SPGn ofFIGS. 8A to 8Dmay be formed on the base plate10. The semiconductor package groups SPG1to SPGn may be included together with the side retainer walls66and the filling layer70as an upper package group UPG located on the main surface of the base plate10as shown inFIGS. 8E and 8F. A plurality of upper package groups UPG may be mounted in series on the base plate10. The upper package groups UPG may include the lower and upper semiconductor packages30and50and may include additional semiconductor packages stacked on the upper semiconductor packages50.

The base plate10may include a lower package group LPG located on the surface opposite the main surface of the base plate10as shown inFIGS. 8E and 8F. The lower package groups LPG may include a plurality of semiconductor package groups SPG11to SPGn1. The semiconductor package groups SPG11to SPGn1of the lower package group LPG may have the same elements as the semiconductor package groups SPG1to SPGn of the upper package groups UPG. The lower package groups LPG may be mounted in series on the base plate10. The lower package groups LPG may include the lower and upper semiconductor packages30and50and may include additional semiconductor packages stacked on the upper semiconductor packages50.

FIGS. 9A to 9Dare cross-sectional views taken along lines I-I′, II-II′, III-III′, and IV-IV′ ofFIG. 1A, illustrating an intermediate step in manufacturing a semiconductor packaging device according to an embodiment of the present general inventive concept.

FIGS. 9E and 9Fare cross-sectional views taken along lines I-I′ and III-III′ ofFIG. 1A, illustrating a final step in manufacturing the semiconductor packaging device according to an embodiment of the present general inventive concept.

Referring toFIGS. 1A,1C, and9A to9D, side retainer walls66amay be formed on the base plate10as shown inFIGS. 1A,1C, and9B. The side retainer walls66cofFIGS. 1D and 4are not formed at the ends of the series of semiconductor package groups SPG1-SPGn. The side retainer walls66amay be formed along guide lines P1and P2as shown inFIG. 1Ato be adjacent to the semiconductor package groups SPG1to SPGn. The side retainer walls66amay extend upward from the main surface of the base plate10as shown inFIG. 9B. The side retainer walls66amay contact the sides of the semiconductor package groups SPG1to SPGn as shown inFIG. 4.

The side retainer walls66amay be formed along guide lines P1and P2on the sides of the semiconductor package groups SPG1to SPGn as shown inFIGS. 9A and 9B. The semiconductor package groups SPG1to SPGn and the side retainer walls66amay define spaces A as shown inFIGS. 1A,1C, and4. Subsequently, a filling layer70may be formed on the base plate10as shown inFIGS. 9A to 9D. The filling layer70may fill the spaces A while contacting sidewalls of the side retainer walls66a. The filling layer70may fill the spaces between the lower and upper semiconductor packages30and50of each of the semiconductor package groups SPG1to SPGn. The side retainer walls66amay control the flow of the filling layer70and confine the filling layer70to the area surrounding the semiconductor package groups SPG1to SPGn.

Referring toFIGS. 9E and 9F, the semiconductor package groups SPG1to SPGn ofFIGS. 9A to 9Dmay be formed on the base plate10. The semiconductor package groups SPG1to SPGn, the side retainer walls66a, and the filling layer70may together form an upper package group UPG located on the main surface of the base plate10as shown inFIGS. 9E and 9F. A plurality of upper package groups UPG may be formed in series on the base plate10. The upper package groups UPG may include the lower and upper semiconductor packages30and50and may also include additional semiconductor packages stacked on the upper semiconductor packages50.

The base plate10may include a lower package group LPG located on the surface opposite the main surface of the base plate10as shown inFIGS. 9E and 9F. The lower package groups LPG may include a plurality of semiconductor package groups SPG11to SPGn1. The semiconductor package groups SPG11to SPGn1of the lower package group LPG may have the same elements as the semiconductor package groups SPG1to SPGn of the upper package groups UPG. The lower package groups LPG may be formed in series on the base plate10. The lower package groups LPG may include the lower and upper semiconductor packages30and50and may also include additional semiconductor packages stacked on the upper semiconductor packages50.

The lower package group LPG, the upper package group UPG, and the base plate10may together form the semiconductor packaging device80, as shown inFIGS. 9E and 9F.

FIGS. 10A-10Dillustrate a method to manufacture a semiconductor packaging device80according to an embodiment of the present general inventive concept.

As shown inFIG. 10A, a substrate10may be provided. The substrate may be a printed circuit board, for example. The substrate may include pads15and a retainer wall area100. The pads15may be configured to receive a plurality of semiconductor packages or devices in a row or in series. The pads15may be further configured to receive semiconductor packages in a plurality of rows. The pads may be raised above a surface of the substrate10or they may have an upper surface flush, or substantially flush, with an upper surface of the substrate10. For example, substrate material may be removed from the surface of the substrate10and a pad15may be embedded therein.

As shown inFIG. 10B, semiconductor packages30,50may be mounted on the pads15via conductive bumps, electrodes, or leads24,44. Specifically, a semiconductor package30may be mounted directly on the pads15via bumps24, and a semiconductor package50may be mounted upon the semiconductor package30via bumps44. Although only two semiconductor packages are shown inFIG. 10B, and number of semiconductor packages may be stacked. In addition, the semiconductor packages30,50may be stacked together either before or after the semiconductor package30is mounted to the substrate10.

As shown inFIG. 10C, a retainer wall66may be formed on the retainer wall area100. The retainer wall area100may have a surface distinct from other areas of the substrate surface. For example, the retainer wall area100may be rougher than surrounding areas or may comprise a substance coated on the substrate10to facilitate bonding between the retainer wall area100and the material that makes up the retainer wall66. The retainer wall66may be formed to a height lower than or equal to an upper surface of the upper semiconductor package50. Alternatively, the retainer wall may be formed to a height above an upper surface of the upper semiconductor package50.

AlthoughFIG. 10Cillustrates a retainer wall66that is spaced from, or not directly adjacent to, the semiconductor packages,30,50, the retainer wall66may also be directly adjacent to the semiconductor packages30,50so that it may contact the semiconductor packages. If the semiconductor packages30,50are of different sizes, the retainer wall66may be directly adjacent to one semiconductor package and spaced a certain distance from the other.

As shown inFIGS. 11A-11C, respectively, the retainer wall66may be formed into any shape, including having a straight inside surface1100adjacent to the semiconductor devices30,50and a straight outside surface1102; having a straight inside surface1100and a curved outside surface1102, or having a curved inside surface1100and a curved outside surface1102.

After forming the retainer wall66, the space defined by the retainer wall66and the semiconductor packages30,50may be filled in with a filling70.FIG. 10Dillustrates a perspective view of a portion of the semiconductor packaging device80ofFIG. 1Awith portions of the retaining wall66and filling70cut away for clarity. The filling may fill the spaces A between semiconductor package groups, such as SPG1and SPG2, and between individual semiconductor packages30,50of the semiconductor package groups. When the retainer wall66is spaced a certain distance from the semiconductor packages30,50, the filling may also fill the space between the semiconductor packages30,50and the retainer wall66.

When the retainer wall66is shorter or of an equal height as an upper surface of the upper semiconductor package50, the filling leaves the upper surface of the upper semiconductor package50exposed. However, when the retainer66is taller than a height of the upper surface of the upper semiconductor package50, the filling may partially or entirely cover the upper surface of the upper semiconductor package50.

The filling material70may include an insulation material and/or a heat conductive material to dissipate heat from the semiconductor packages30,50. The insulation material may physically insulate the semiconductor packages30,50from physical shock or it may prevent electrical transmission through the filling material70. The filling material70may include a bonding agent such as cement to affix the semiconductor packages30,50to the substrate10and/or to the retaining wall66. The filling material70may have a viscosity greater than that of the retainer wall66. As such, the filling material70may form the LPG and UPG ofFIGS. 8E and 8Ftogether with the substrate10, the semiconductor packages30and50, and the retainer wall66. The LPG and UPG may be formed as the semiconductor packaging device80ofFIGS. 8E and 8F.

FIGS. 12A and 12Billustrate stacked semiconductor packages arranged in rows of the semiconductor packaging device80. As shown inFIG. 12A, a first row R1of stacked semiconductor packages is arranged adjacent to a second row R2of stacked semiconductor packages on the substrate10. A retainer wall66is adjacent to only one of the rows R2. Although the retainer wall66illustrated inFIG. 12Ais adjacent to only the sides of the row R2, the retainer wall66may have any configuration, as illustrated inFIGS. 1A-1E. As discussed previously, filler70may fill the spaces A between the stacked semiconductor packages.

FIG. 12Billustrates the rows R1and R2ofFIG. 12A, but the retainer wall66surrounds both the first row R1and the second row R2. When there are more than two rows, the retainer wall66may surround any of the rows and may exclude any of the rows. Specifically, the retainer wall66may be formed adjacent to any rows that are to receive filling70, and may not be formed adjacent to rows that are not to receive filling70. Alternatively, the retainer wall66may not be formed adjacent to rows that receive filling70.

Referring toFIGS. 1A and 13A,FIG. 13Aillustrates a computing device1300including a semiconductor packaging device80according to an embodiment of the present general inventive concept, a controller1302, and an interface1304. The controller1302may access an individual semiconductor device, such as the stacked semiconductor devices30,50discussed above, of the semiconductor packaging device. For example, the semiconductor devices30,50may be memory to store data or a semiconductor device to manipulate data, such as a multiplexing device or another controller. The controller1302may receive commands from an interface1304, which may include a user interface such as a display and keypad, or may include a port to receive commands from an external device, for example. The controller may be electrically connected to pads on the substrate10of the semiconductor packaging device80, or pads located on an exposed upper surface of one of the stacked semiconductor devices50, for example.

For example, if the computing device1300receives a command from an external device via the interface1304to access memory located in the semiconductor packaging device80, the interface1304may transmit the command to the controller1302which may access any of the stacked semiconductor devices30,50in the semiconductor packaging device80to read data and to transmit the data to the external device via the interface1304.

The computing device1300may be enclosed by a physical housing1312, or it may include a plurality of devices electrically connected together. For example, the interface1304may be integral with the computing device1300, or it may be externally connected to the computing device1300.

FIG. 13Billustrates a computing device1308connected to a semiconductor packaging device80according to an embodiment of the present general inventive concept. Similar to the computing device1300inFIG. 13A, the computing device1308may include a controller1302and an interface1304. The computing device1308may further include a memory device to receive data from the controller1302or another source. The computing device1308may include a terminal T1to connect to an external device, such as the semiconductor packaging device80. The semiconductor packaging device80may have a terminal T2directly formed on the device, or it may be connected to a terminal T2. Numeral1310represents a connection between terminals T1and T2, and may include a hard connection including a physical wire, or a wireless connection. For example, both the computing device1308and the semiconductor packaging device80may be connected to a wireless transceiver to transmit and/or receive data wirelessly.

Alternatively, the computing device1308may be connected to the semiconductor packaging device80via a physical wire. The wire may be directly connected to a terminal T2formed on the semiconductor packaging device to allow the computing device1308to access data on or otherwise control or access the semiconductor packages located on the semiconductor packaging device80.

Alternatively, the controller1302may be one of the stacked semiconductor devices30,50, and the interface may be connected directly to the semiconductor packaging device80.

As described above, example embodiments provide a semiconductor packaging device in which at least one side retainer wall is located adjacent to semiconductor package groups on the base plate. The at least one side retainer wall may confine a filling layer within the semiconductor package groups and may expose top surfaces of the semiconductor package groups. Therefore, the at least one side retainer wall may provide a better mounting environment for elements of electronic devices together with the base plate, the filling layer and the semiconductor package groups, compared to the conventional semiconductor packaging device.