Systems and methods of control for plasma processing

A plasma processing system includes a vacuum chamber, a first coupling electrode, a substrate holder disposed in the vacuum chamber, a second coupling electrode, and a controller. The substrate holder is configured to support a substrate. The first coupling electrode is configured to provide power for generation of a plasma in the vacuum chamber. The first coupling electrode is further configured to couple source power pulses to the plasma. The second coupling electrode is configured to couple bias power pulses to the substrate. The controller is configured to control a first offset duration between the source power pulses the bias power pulses.

TECHNICAL FIELD

The present invention relates generally to plasma processing, and, in particular embodiments, to systems and methods of control for plasma processing.

BACKGROUND

The manufacture of semiconductor devices involves a series of techniques including formation, patterning, and removal of a number of layers of material on a substrate. In order to achieve the physical and electrical specifications of current and next generation semiconductor devices, processing flows enabling reduction of feature size while maintaining structural integrity are desirable for various patterning processes. Historically, with microfabrication, transistors have been created in one plane, with wiring/metallization formed above, and have thus been characterized as two-dimensional (2D) circuits or 2D fabrication. Scaling efforts have greatly increased the number of transistors per unit area in 2D circuits, yet scaling efforts are running into greater challenges as scaling enters nanometer-scale semiconductor device fabrication nodes. Therefore, there is a desire for three-dimensional (3D) semiconductor devices in which transistors are stacked on top of each other.

As device structures densify and develop vertically, the desire for precision material processing becomes more compelling. Trade-offs between selectivity, profile control, film conformality, and uniformity in plasma processes can be difficult to manage. Thus, equipment and techniques that isolate, and control the process conditions that are optimal for etch and deposition regimes are desirable in order to precisely manipulate materials and meet advanced scaling challenges.

Plasma processes are commonly used in the manufacture of semiconductor devices. For example, plasma etching and plasma deposition are common process steps during semiconductor device fabrication. A combination of source power and bias power may be used to generate and direct plasma during plasma processing.FIG.16illustrates conventional timing diagrams for the application of source power and bias power during plasma processing. In the top diagram, there are no distinct pulses for the source power or the bias power. In the middle diagram, continuous bias power is applied with no pulses while 100 μs source pulses are applied. In the bottom diagram, continuous source power is applied with no pulses while 80 μs bias pulses are applied.

SUMMARY

In accordance with an embodiment, a plasma processing system includes a vacuum chamber, a first coupling electrode, a substrate holder disposed in the vacuum chamber, a second coupling electrode, and a controller. The substrate holder is configured to support a substrate. The first coupling electrode is configured to provide power for generation of a plasma in the vacuum chamber. The first coupling electrode is further configured to couple source power pulses to the plasma. The second coupling electrode is configured to couple bias power pulses to the substrate. The controller is configured to control a first offset duration between the source power pulses the bias power pulses.

In accordance with another embodiment, an apparatus includes a vacuum chamber, a coupling electrode, and a substrate holder. The coupling electrode is coupled to a source power supply node and configured to generate a plasma within the vacuum chamber using a first sequence of source power pulses. The substrate holder is coupled to a bias power supply node and disposed within the vacuum chamber. The substrate holder is configured to support a substrate to be processed by the plasma. A second sequence of bias power pulses is configured to accelerate ions of the plasma towards the substrate.

In accordance with still another embodiment, a method of plasma processing includes outputting a first signal to a first function generator using a first pulse modulation circuit, generating a first source power pulse using the first function generator in response to the outputting the first signal, providing the first source power pulse at a first coupling electrode of a vacuum chamber to generate a plasma, generating a bias power pulse by triggering a delay relative to the first source power pulse, providing the bias power pulse at a second coupling electrode of the vacuum chamber, and performing a plasma deposition or etch process on a substrate disposed in the vacuum chamber. Providing the bias power pulse accelerates ions from the plasma towards the substrate.

Corresponding numerals and symbols in the different figures generally refer to corresponding parts unless otherwise indicated. The figures are drawn to clearly illustrate the relevant aspects of the embodiments and are not necessarily drawn to scale. The edges of features drawn in the figures do not necessarily indicate the termination of the extent of the feature.

DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS

The making and using of various embodiments are discussed in detail below. It should be appreciated, however, that the various embodiments described herein are applicable in a wide variety of specific contexts. The specific embodiments discussed are merely illustrative of specific ways to make and use various embodiments, and should not be construed in a limited scope.

Various techniques, as described herein, pertain to device fabrication using precision plasma processing techniques, including etch and deposition processes. Several instances manifest in semiconductor manufacturing in both front end of line (FEOL, e.g., transistor fabrication) through to the back end of line (BEOL, e.g., interconnect fabrication), where materials are to be manipulated with a high degree of precision. Conventional plasma processing apparatus and methods may be lacking in control of plasma properties, including control of radical populations and compositions, control of ion populations, and control of electron populations, as well as reaction by-products, and thus, have been deficient in meeting advanced scaling requirements.

When using plasma to manipulate material at nanometer scales on a workpiece surface for advanced device topologies, it may be desirable to precisely control one or more plasma properties such as ion energy distributions (IEDF), ion temperature (Ti), ion angular distributions (IADF), electron energy distributions (EEDF), electron temperature (Te), for example. Traditional plasma process parameters, such as gas pressure, power, and more specifically, the manner in which electromagnetic fields are coupled to a gas environment in order to form plasma (e.g., capacitive coupling, inductive coupling, etc.) may impact these plasma properties. However, to meet the needs of present and future state-of-the-art device fabrication, relatively more complex methodologies may be beneficial so that plasma properties such as IEDF, Ti, IADF, and the like may be effectively manipulated to achieve differentiated target outcomes on the fabrication workpiece.

For example, it is widely accepted that no active control mechanism exists in the art to control the angle of ions incident on a topographical feature of a microelectronic device during plasma processing. It may be beneficial to deliver absolutely vertical or substantially vertical ions to the substrate surface. Additionally, it may also be beneficial to control the angle of ion beams delivered into structures while accounting for and/or correcting for scattering on sidewalls of patterned structures. For example, this control of ion distribution angle could be useful for high aspect ratio contact (HARC) type etches and patterning applications as well as other etch/deposition processes.

Various embodiments described herein provide systems and methods to control plasma properties for the delivery of ions for plasma processing such as in reactive ion etching or plasma deposition. The various embodiments may provide antiphased, antisynchronous, and/or out-of-phase source power and bias power pulsing for plasma processing. The pulsing may be controlled using plasma processing parameters including pulse width, frequency, and amplitude for both source power and bias power as well as one or more offsets between pulses. Using the plasma processing parameters, bias power pulses may be pulsed in a delayed manner from the source plasma or at the same time as the source plasma. Various plasma properties such as ion temperature Ti, electron temperature Te, electron density ne, sheath voltage drop Vsheath, plasma bulk potential VP, and the like may be modulated and controlled using the embodiment systems and methods as described herein.

Embodiments provided below describe various systems and methods of operating plasma processing systems, and in particular, methods of plasma processing that include source power pulses and bias power pulses. The following description describes the embodiments. An example schematic timing diagram and a qualitative graph of an embodiment method of control for plasma processing that includes source power pulses and bias power pulses are described usingFIG.1. An embodiment plasma processing system including a source pulse modulation circuit and a pulse modulation timing circuit is described usingFIG.2. Two embodiment methods of plasma processing including bias pulses with positive and negative leading offsets relative to source pulses are described usingFIG.3. Two embodiment methods of plasma processing including bias pulses with negative and positive trailing offsets relative to source pulses are described usingFIG.4. An embodiment method of plasma processing including bias pulses with dynamic offsets is described usingFIG.5. An embodiment method of plasma processing including bias power pulse trains is described usingFIG.6. An embodiment method of plasma processing including source pulse and bias pulse timing associated with particular gas flows is described usingFIG.7. Several embodiment plasma processing systems are described usingFIGS.8-11. Two embodiment plasma processing systems including a source pulse modulation circuit and a pulse modulation timing circuit are described usingFIGS.12and13. An embodiment helical resonator plasma processing system is described usingFIG.14. An embodiment method of plasma processing is described usingFIG.15.

FIG.1illustrates a schematic timing diagram of a pulse sequence and a corresponding qualitative graph of an example method of control for plasma processing that includes source power pulses and bias power pulses in accordance with an embodiment of the invention. The source power is coupled to a plasma processing chamber of a plasma processing system and is used to generate a plasma for processing of a microelectronic workpiece. The bias power is also coupled to the plasma processing chamber and may be used to accelerate ions toward a surface of the microelectronic workpiece in addition to other functions.

Referring toFIG.1, a timing diagram100includes a source power1and a bias power2which are pulsed to generate and deliver ions to a microelectronic workpiece (e.g., a semiconductor wafer). Specifically, timing diagram100includes a pulse sequence with one or more source power (SP) pulses11and bias power (BP) pulses12which are at least partially non-overlapping in time. For example, the source power1may be alternating current (AC) power which is switched between an on state and an off state to generate the SP pulses11(the frequency of the AC power is higher than the frequency of the SP pulses11). Similarly, the bias power2may also be AC power. Alternatively, one or both of the source power1and the bias power2may be DC power.

In various embodiments, the pulse sequence is periodic with a pulse modulation period5and includes multiple SP pulses11and BP pulses12. However, in some cases, a pulse sequence may refer to a single SP pulse and a single BP pulse. Further, although periodicity may be beneficial, there is no strict requirement that the pulse sequence be periodic or that the SP pulses have the same period as the BP pulses.

As shown in graph102, the temperature curve31and the density curve32of the generated plasma change in accordance with the applied source power1of timing diagram100. SP pulses11generate a plasma glow phase characterized by an increase in various plasma parameters such as the electron density ne, electron temperature Te, and the ion temperature Ti. Initial application of a SP pulse11may result in a spike21in plasma temperature (e.g., Teand Ti) which relaxes to a pseudo-equilibrium state23for the remainder of the SP pulse. After the SP pulse ends, the plasma enters an afterglow phase during which the ions and electrons may cool down resulting in decreases in Te, Ti. The electrons and ions diffuse to the walls by ambipolar diffusion resulting in decreases in ne. In various embodiments, during the afterglow phase, a BP pulse is applied to accelerate the generated ions towards a surface of a microelectronic workpiece.

As illustrated in graph102, Teand Timay decrease more rapidly than nein the afterglow phase. Since the electron density neis correlated with available ions, applications of a BP pulse during the afterglow phase may be particularly effective in order to accelerate low-temperature ions to the surface of the microelectronic workpiece. During the afterglow phase, the plasma current may also decrease. This current drop may allow for a large voltage difference Vpacross the plasma sheath and VDC(RF DC self-bias voltage) in the afterglow phase when bias power is applied (e.g., using a BP pulse). The increased voltage difference Vpand the time-average drop dc voltage drop VDCalong with the lower ion temperature may improve the directionality of the ion flux.

Therefore, the SP pulses and BP pulses are at least partially non-overlapping in time. In one embodiment, the SP pulses and BP pulses are completely out-of-phase as illustrated in the timing diagram100. In other embodiments, the SP pulses and BP pulses may partially overlap. Accordingly, embodiments of the method include both a nonzero interval of time during which the source power1is applied without the bias power2, as well as including a nonzero interval of time during which the bias power2is applied without the source power1.

Still referring toFIG.1, the pulse sequence of timing diagram100may be generated using pulse modulation process parameters. The pulse modulation process parameters may include SP pulse width3and SP pulse amplitude4corresponding to the source power1sequence as well as a leading edge bias offset6, BP pulse width7, BP pulse amplitude8, and a trailing edge bias offset9corresponding to the bias power2sequence. In particular, each SP pulse11includes a SP pulse width3and an SP pulse amplitude4while each BP pulse12includes a BP pulse width7and a BP pulse amplitude8. It should be mentioned that unless otherwise noted, amplitude as used herein refers to the average peak-to-peak amplitude of a given pulse.

For both the SP pulses11and BP pulses12, a specific pulse width may be implemented by choosing a duty cycle (%) for a given pulse modulation period5. For example, if the pulse modulation period is set to 150 μs, a 56% source power duty cycle (%) and a 28% bias power duty cycle (%) would result in an 84 μs SP pulse width and a 42 μs BP pulse width. In one embodiment, the source power1and the bias power2have the same pulse modulation period. Alternatively, source power1and bias power2may operate with separate pulse modulation period. In various embodiments, the duty cycle (%) of either of the SP pulses11and BP pulses12may range from about 3% to about 90%. In one embodiment, the duty cycle (%) of the SP pulses11is about 5%. In another embodiment, the duty cycle (%) of the SP pulses11is about 50%. In still another embodiment, the duty cycle (%) of both the SP pulses11and the BP pulses12is about 40%. Suitable duty cycles (%) for the SP pulses11and BP pulses12may be chosen according to specific properties of a given plasma process.

The duration of any of the pulse widths described herein may have any suitable value as chosen based on specific parameters of a given plasma process. For example, the SP pulse width3may range between about 10 μs and about 100 μs. Alternatively, the SP pulse width3may be larger or smaller. For example, the SP pulse width3may be on the order of milliseconds in some embodiments. Similarly, the BP pulse width7may range between 10 μs and about 100 μs, but can also be larger or smaller as with the SP pulse width3. Furthermore, the SP pulse width3and the BP pulse width7may be independently chosen according to a given plasma process.

As illustrated inFIG.1, a delay between SP pulses11and BP pulses12may be referred to as a leading edge bias offset6. The leading edge bias offset6may be implemented as a percentage of the pulse modulation period5. For example, the leading edge bias offset may vary between −10% to +10% of the pulse modulation period5. Alternatively, the leading edge bias offset6may set as a specific time value. For example, continuing the above case where the source power1and the bias power2have the same pulse modulation period set to 150 μs, a leading edge bias offset of 10% would result in a 15 μs delay between the trailing edge of a SP pulse and a BP pulse. In the foregoing example, the leading edge bias offset6is set to be positive. However, the leading edge bias offset6may also be zero or negative.

Similarly, a delay between BP pulses12and SP pulses11may be referred to as a trailing edge bias offset9and may be implemented through a combination of the SP pulse width3, the leading edge bias offset6, and the BP pulse width7. Continuing the above example, a 56% source power duty cycle (%), a leading edge bias offset of 10%, and a 28% bias power duty cycle (%) accounts for 94% of a complete pulse modulation period. Therefore, in this specific example, there is a delay equal to 6% of the pulse modulation period between the trailing edge of a BP pulse and the leading edge of a SP pulse. Since the pulse modulation period is 150 μs, this delay which is the trailing edge bias offset9is equal to 9 μs. Similar to the leading edge bias offset6, the trailing edge bias offset9is not required to be positive, but may also be zero or negative.

The duration of any of the offsets described herein may have any suitable value as chosen based on specific parameters of a given plasma process. For example, the leading edge bias offset6may range between about −50 μs and about 50 μs. In various embodiments, the leading edge bias offset6may be between about −15 μs and about 20 μs. In one embodiment, the leading edge bias offset6is about 20 μs. In another embodiment, the leading edge bias offset6is about to 10 μs. In still another embodiment, the leading edge bias offset6is about 1 μs.

The pulse amplitudes may have corresponding high and low amplitude states. For example, the high and low amplitudes may be voltage levels. Specifically, each of the SP pulses11may oscillate between a SP low amplitude state13and a SP high amplitude state14while each of the BP pulses12may oscillate between a BP low amplitude state17and a BP high amplitude state18. A positive or negative DC bias may be applied to one or both the source power1or the bias power2so that the respective high and low amplitudes are brought to desirable levels.

It should be mentioned that both the temperature curve31and density curve32are qualitative in nature. Therefore, while both may be indicative of important phenomena associated with the effect of a pulse sequence on plasma parameters such as Te, Ti, and ne, neither are intended to be drawn with a specific scale or be quantitatively accurate. Furthermore, simplifications may have been made for the sake of clarity. For example, the electron temperature Teand the ion temperature Tihave been represented as a single curve in graph102because the shape of the curves is similar even though Temay be at least an order of magnitude greater than Tiin a cold plasma.

FIG.2illustrates a block diagram of an example plasma processing system including a source pulse modulation circuit and a pulse modulation timing circuit in accordance with an embodiment of the invention. The plasma processing system ofFIG.2may be used to perform any of the embodiment methods as described herein, such as the method ofFIG.1, for example.

Referring toFIG.2, a plasma processing system200includes a SP coupling electrode15coupled to a plasma processing chamber210. For example, the plasma processing chamber210may include a vacuum chamber. The SP coupling electrode may allow application of source power to the plasma processing chamber210resulting in the generation of a plasma60. In various embodiments, the SP coupling electrode15is a conductive coil positioned around the plasma processing chamber210and is a quarter-wave helical resonator in one embodiment. In another embodiment, the SP coupling electrode15is a half-wave helical resonator. Alternatively, other SP coupling electrodes may be employed, such as an antenna, plate electrode, or a waveguide, as examples.

The plasma processing system200further includes a BP coupling electrode19coupled to the plasma processing chamber205. The BP coupling electrode19may enable application of bias power to a microelectronic workpiece being processed. In various embodiments, the BP coupling electrode19is a substrate holder and is an electrostatic chuck in one embodiment.

The source power may be coupled to the plasma processing chamber210using a SP control path201which includes a SP pulse modulation circuit51. The SP pulse modulation circuit51may modulate a source signal between a SP high amplitude state14and a SP low amplitude state13. For example, the modulated source signal may correspond with the SP pulses11as described in reference toFIG.1. The modulated source signal may be received by a SP function generator20which may superimpose a waveform onto the modulated source signal. As a person of skill in the art may recognize, a pulse modulation circuit, such as the SP pulse modulation circuit51, can be implemented, e.g., using a laser driver capable of generating high power pulses for laser diodes such as AVTECH AVOZ-D2-B pulse generator type circuits, for example.

The SP function generator20, which may be implemented using any function generator as would be known to a person skilled in the art, such as a 2235A HP function generator in one specific example, may also optionally include an amplification circuit such as an RF amplifier, configured to increase the amplitude of the modulated source signal. In various embodiments, the SP function generator20may be a signal generator, and may be a radio frequency (RF) signal generator in one embodiment. Alternatively, the SP function generator20may be a microwave function generator. In one embodiment, the SP function generator20may be an arbitrary waveform generator (AWG).

A function generator such as SP function generator20may be a circuit that includes an electronic oscillator. More than one electronic oscillator may be included in a function generator. Waveforms may be generated by a function generator using digital signal processing. The digital output may then be converted with a digital-to-analog converter to produce an analog waveform. A function generator may also include modulation functions such as amplitude modulation, frequency modulation, or phase modulation.

The frequency of the superimposed waveform may be higher than the pulse modulation frequency. In various embodiments, the frequency of the superimposed waveform may be an RF frequency and is about 13.56 MHz in one embodiment. As a result, each of the resulting SP pulses may include several cycles of the superimposed waveform. The waveform shape may include a periodic waveform such as a sinusoidal wave, a square wave, a sawtooth wave, and the like. Alternatively, the waveform shape may include an aperiodic wave such as a superposition of multiple sinusoidal waves of various frequencies to generate an arbitrary waveform shape.

The SP control path201may include an optional SP impedance matching network25. As a person of skill in the art may recognize, an impedance matching network, such as the SP impedance matching network25, can be implemented using feedback control circuits that phase shift compensation signals based on an impedance measurement such as, for example, described in US Patent Publication 2009/0000942. The matching circuits may be variations of L and T type networks. For example, an impedance matching network may include a network of inductors, capacitors, and/or variable capacitors. Frequency tuning, i.e., adjustment of the driving frequency to match the antenna-plasma resonance is another means of matching. Frequency tuning in pulsed mode may utilize feedback control to take advantage of power or voltage measurements that correlate with plasma impedance.

The SP pulses generated by the SP function generator20may pass through the optional SP impedance matching network25before being coupled to the plasma processing chamber210by the SP coupling electrode15. The optional SP impedance matching network25may be omitted in certain plasma processing systems such as when the SP coupling electrode15is a resonant structure inductively coupled to the plasma60. Conversely, the optional SP impedance matching network25may be included when the SP coupling electrode15is non-resonant. The optional SP impedance matching network25may be used to ensure that the source power is efficiently coupled to the plasma60by matching the impedance of the load to the impedance of the supply.

Still referring toFIG.2, the bias power may be coupled to the plasma processing chamber210using a BP control path202. The BP control path202may be coupled to the SP control path201through a pulse modulation timing circuit52. The pulse modulation timing circuit52may determine the timing of BP pulses relative to the timing of SP pulses generated by the SP control path201. The pulse modulation timing circuit52may receive a signal from the SP pulse modulation circuit51and introduce a delay triggered by either the leading edge or the trailing edge of a SP pulse. The signal from the SP pulse modulation circuit51to the pulse modulation timing circuit52may be the SP pulse or a clock signal indicative of the SP pulse, as examples. Alternatively, the SP pulses and BP pulses may be offset from one another based on a timing schedule which may be implemented using clock signaling. As an example, if the leading edge bias offset parameter is set to 8% of the pulse modulation period, the pulse modulation timing circuit52may introduce a delay equal to 8% of the pulse modulation period after being triggered by the trailing edge of a SP pulse. Alternatively, if the pulse modulation timing circuit52is configured to be triggered by the leading edge of a SP pulse, a delay of 8% of the pulse modulation period plus the source power duty cycle (%) may be introduced by the pulse modulation timing circuit52. As a further alternative, the pulse modulation timing circuit52may determine the timing of SP pulses relative to the timing of BP pulses generated by the BP control path202.

As a person of skill in the art may recognize, a timing circuit, such as the pulse modulation timing circuit52, can be implemented using any timing circuit. In one specific example, a Highland Technology T560 4-channel compact digital delay and pulse generator circuit may be used.

Similar to the SP control path201, the BP control path202may include an optional BP pulse modulation circuit53triggered by the pulse modulation timing circuit52. The optional BP pulse modulation circuit53may modulate a bias signal between a BP high amplitude state and a BP low amplitude state. For example, the modulated bias signal may correspond with the BP pulses12as described in reference toFIG.1. Alternatively, the optional BP pulse modulation circuit53may be omitted and a delayed modulated source signal may correspond with the BP pulses.

The modulated bias signal may be received by an optional BP function generator30. The optional BP function generator30may superimpose a waveform onto the modulated bias signal. The waveform may be similar or different than the waveform superimposed on the modulated source signal and may have any desired waveform shape as previously described. The optional BP function generator30may also optionally include an amplification circuit to increase the amplitude of the modulated bias signal. In one embodiment, the bias power delivered to the plasma processing chamber210is DC power. In this case, the optional BP function generator30may be omitted. In some cases where amplification is needed, but function generation is not, an amplification circuit may be included instead of the optional BP function generator30.

A BP impedance matching network35is also included in the BP control path202between the optional BP function generator30and the BP coupling electrode19. The BP impedance matching network may be used to ensure that the bias power is efficiently coupled to the plasma processing chamber210by matching the impedance of the load to the impedance of the supply.

The SP function generator20and the optional SP impedance matching network25may be included in a SP generator circuit240which receives source power and provides SP pulses to the SP coupling electrode15. Similarly, the optional BP function generator30and the BP impedance matching network35may be included in a BP generator circuit245which receives bias power and provides BP pulses to the BP coupling electrode19.

One or more of the elements described above may be included in a controller. For example, as shown inFIG.2, the SP pulse modulation circuit51, pulse modulation timing circuit52, and optional BP pulse modulation circuit53may be included in a controller250. The controller250may be locally located relative to the plasma processing chamber210. Alternatively, controller250may be located remotely relative to the plasma processing chamber210. The controller250may be capable of exchanging data with one or more of the elements included in the SP control path201and the BP control path202. Each of the impedance matching networks may be controlled by controller250or may include a separate controller.

The controller250may be configured to set, monitor, and/or control various control parameters associated with generating a plasma and delivering ions to the surface of a microelectronic workpiece. Control parameters may include, but are not limited to power level, frequency, and duty cycle (%) for both the source power and the bias power as well as bias offset percentage. Other control parameter sets may also be used. For example, pulse width of the SP pulses and BP pulses and the bias offset may be entered directly rather than being represented as a duty cycle (%) of the pulse modulation period.

FIG.3illustrates schematic timing diagrams of example methods of plasma processing including bias pulses with positive and negative leading offsets relative to source pulses in accordance with embodiments of the invention. The timing diagrams ofFIG.3may be specific implementations of other embodiment timing diagrams, such as timing diagram100ofFIG.1, for example. Similarly labeled elements may be as previously described.

Referring toFIG.3, a timing diagram300includes a positive leading edge (+LE) bias offset306between high amplitude states of SP pulses11and high amplitude states of non-overlapping BP pulses312which do not overlap in time with adjacent SP pulses11in the pulse sequence. The non-overlapping BP pulses312also include a non-overlapping BP pulse width307and are separated from subsequent SP pulses11by a trailing edge bias offset9.

In contrast, a timing diagram320is similar to timing diagram300except that timing diagram320includes a negative leading edge (−LE) bias offset326between high amplitude states of SP pulses11and high amplitude states of −LE BP pulses322which partially overlap in time with adjacent SP pulses11in the pulse sequence. For example, both the +LE bias offset306and the −LE bias offset326are measured relative to the trailing edge of a respective SP pulse11. Consequently, a negative offset such as −LE bias offset326results in −LE BP pulses322. The −LE BP pulses322also include an overlapping BP pulse width327and are separated from subsequent SP pulses11by a trailing edge bias offset9.

FIG.4illustrates schematic timing diagrams of example methods of plasma processing including bias pulses with negative and positive trailing offsets relative to source pulses in accordance with embodiments of the invention. The timing diagrams ofFIG.4may be specific implementations of other embodiment timing diagrams, such as timing diagram100ofFIG.1, for example. Similarly labeled elements may be as previously described.

Referring toFIG.4, a timing diagram400includes a negative trailing edge (−TE) bias offset409in addition to a +LE bias offset306. Each resulting −TE BP pulse412of the pulse sequence has a −TE BP pulse width407and is non-overlapping in time with the previous SP pulse11, but partially overlapping in time with the subsequent SP pulse11. According to the convention adopted in this illustration for offsets, a negative offset value indicates overlap with an adjacent pulse. Therefore, for trailing edge offsets of a given pulse, a negative offset results in overlap between the trailing edge of the pulse and the leading edge of the next pulse, as illustrated for −TE bias offset409in timing diagram400, for example.

Similarly, a timing diagram420includes a negative −TE bias offset409in addition to a −LE bias offset326between high amplitude states of SP pulses11and high amplitude states of overlapping BP pulses422which partially overlap with both the previous and subsequent SP pulses11of the pulse sequence. The overlapping BP pulses11include an overlapping BP pulse width427which is greater in duration than each SP pulse width3of the SP pulses11.

FIG.5illustrates a schematic timing diagram of an example method of plasma processing including bias pulses with dynamic offsets relative to source pulses in accordance with an embodiment of the invention. The timing diagram ofFIG.5may be a specific implementation of other embodiment timing diagrams, such as timing diagram100ofFIG.1, for example. Similarly labeled elements may be as previously described.

Referring toFIG.5, a timing diagram500includes SP pulses11with pulse modulation period5and BP pulses12with variable leading offset bias offsets (509,519,529) that may be dynamically varied. Specifically, the leading edge bias offset of each of the BP pulses12may change for each SP pulse11of the pulse sequence. Any combination of positive, zero, and negative leading or trailing offsets are possible. For example, the first BP pulse12is illustrated with a positive variable offset509, while the second and third BP pulses12are illustrated with a zero value variable offset519and a negative variable offset529respectively. It should be noted that while the offsets may change every pulse modulation period5, they may also stay the same for multiple pulse modulation periods at a time or change gradually. For example, a large positive offset may gradually be decreased in magnitude from period to period until it becomes zero and then negative.

FIG.6illustrates a schematic timing diagram of an example method of plasma processing include bias power pulse trains in accordance with an embodiment of the invention. The timing diagram ofFIG.6may be a specific implementation of other embodiment timing diagrams, such as timing diagram100ofFIG.1, for example. Similarly labeled elements may be as previously described.

Referring toFIG.6, a timing diagram600includes SP pulses11and BP pulse trains612with BP pulse train width607. The BP pulse trains612may be specific embodiments of BP pulses12as previously described. The BP pulse trains612include BP subpulses622and corresponding BP subpulse width617and BP subpulse separation619. Each of the BP subpulses622may be implemented similar to BP pulses12. In various embodiments, the BP subpulses622are AC pulses and are RF pulses in one embodiment. In another embodiment, the BP subpulses622are DC pulses.

FIG.7illustrates a schematic timing diagram of an example method of plasma processing including source pulse and bias pulse timing associated with particular gas flows in accordance with an embodiment of the invention. The timing diagram ofFIG.7may incorporate one or more specific implementations of other embodiment timing diagrams, such as timing diagram100ofFIG.1. For example, a given plasma process may utilize multiple types of gas, each of which may have a specific implementation of an embodiment timing diagram associated with it. Similarly labeled elements may be as previously described.

Referring toFIG.7, a timing diagram700includes a gas source701in addition to a source power1and a bias power2. The gas source701may include multiple gases and/or mixtures of gases. For example, as illustrated in timing diagram700, gas source701includes a first gas (G1) flow731with a G1 gas flow duration735and a second gas (G2) flow761with a G2 gas flow duration765. The G1 gas flow731and the G2 gas flow761are separated in time by a gas flow offset740. Alternatively, the second gas may be introduced during the G1 gas flow731and the G2 gas flow761may partially overlap with the G2 gas flow731.

Each of the gases may have a pulse sequence associated with the respective gas flow duration. Specifically, a set of plasma processing parameters may be chosen for each gas, for example, from prior embodiments such as inFIGS.1, and3-6, to generate a pulse sequence that is specifically tailored for a particular gas while it is being provided to the plasma processing chamber.

As illustrated in timing diagram700, the G1 pulse sequence71associated with the G1 gas flow731includes G1 SP pulses711with G1 SP pulse width703and G1 BP pulses712with G1 BP pulse width707and G1 BP pulse amplitude708. The G1 BP pulses712are temporally defined relative to the G1 SP pulses711by a G1 LE bias offset706and a G1 TE bias offset709. The G1 pulse sequence71has a G1 pulse modulation period705and may be offset from the leading edge of the G1 gas flow731by a G1 LE source offset736.

Similarly, the G2 gas flow761has an associated G2 pulse sequence72including G2 SP pulses751with G2 SP pulse width743and G2 BP pulses752with G2 BP pulse width747and G2 BP pulse amplitude758. The G2 BP pulses752are temporally defined relative to the G2 SP pulses751by a G2 LE bias offset746and a G2 TE bias offset749. The G2 pulse sequence72has a G2 pulse modulation period745and may be offset from the leading edge of the G2 gas flow761by a G2 LE source offset766. As illustrated, plasma processing parameters may be different between gas flows. For example, pulse width, pulse amplitude, frequency, offset, and others for both source power and bias power may be varied along with the gas flow.

The embodiments described herein, where SP pulses and BP pulses are coupled to plasma, can be implemented by various apparatus, such as those depicted inFIGS.8-11.FIG.8illustrates a schematic diagram of an example capacitively coupled plasma processing system,FIG.9illustrates a schematic diagram of an example inductively coupled plasma processing system, FIG. to illustrates a schematic diagram of an example surface wave plasma processing system, andFIG.11illustrates a schematic diagram of an example remote plasma processing system which may be used to perform methods of plasma processing in accordance with embodiments of the invention. The plasma processing systems ofFIGS.8-11may each be a specific implementation of other embodiment plasma processing systems, such as the plasma processing system200ofFIG.2, for example. Similarly labeled elements may be as previously described.

Referring toFIG.8, a capacitively coupled plasma (CCP) processing system800includes an AC source power supply881coupled to a SP generator circuit240that is coupled to an upper plate electrode (UEL)815and an AC bias power supply882coupled to a BP generator circuit245that is coupled to a lower plate electrode (LEL)819. The AC source power supply881and the AC bias power supply882may respectively generate source power and bias power in accordance with the embodiments described previously such as inFIGS.1,3-7. A CCP860is formed within a grounded plasma processing chamber810proximate a substrate16between the UEL815and the LEL819. The LEL819may also serve as an electrostatic chuck (ESC) to support and retain the substrate16. In various embodiments, plasma is formed by coupling RF power to at least one of the electrodes. The AC power coupled to the UEL815may have a different RF frequency than the AC power coupled to LEL819. Alternatively, multiple RF power sources may be coupled to the same electrode. Moreover, direct current (DC) power may be coupled to the upper electrode and/or the lower electrode.

Referring toFIG.9, an inductively coupled plasma (ICP) processing system goo includes AC source power supply881coupled to a SP generator circuit240that is coupled to an inductive electrode915and AC bias power supply882coupled to a BP generator circuit245that is coupled to an LEL819. Again, the AC source power supply881and the AC bias power supply882may respectively generate source power and bias power in accordance with the embodiments described previously such as inFIGS.1,3-7. An ICP960is formed proximate a substrate16between the inductive electrode915(e.g., a planar, or solenoidal/helical coil or antenna) and the LEL819. A dielectric material910separates the inductive electrode915from the ICP960. The dielectric material910may reduce and/or prevent capacitive coupling effects.

Referring to FIG. to, a surface wave plasma (SWP) processing system1000includes AC source power supply881coupled to a SP generator circuit240that is coupled to a microwave waveguide (μ-waveguide)1014and a slot antenna1015. Similarly, the AC source power supply881and the AC bias power supply882may respectively generate source power and bias power in accordance with the embodiments described previously such as inFIGS.1, and3-7. An SWP1060is formed proximate a substrate16between the slot antenna1015and a LEL819. The SWP1060is formed by coupling RF power at microwave frequencies through a coaxial line and the μ-waveguide1014to the slot antenna1015. (PV-perhaps a small detail onFIG.10but The slot antenna1015may be implemented as a plate with holes or other structures. In some embodiments, the slot antenna may be sandwiched between dielectric structures similar to dielectric material910ofFIG.9so that microwaves may pass from the waveguide (center) radially outward from the center (e.g., through a ceramic structure with a dielectric constant such that the wavelength is reduced, through the antenna structures, and/or through another dielectric material).

Referring toFIG.11, a remote plasma processing system1100is similar to the ICP processing system900ofFIG.9except that instead of a plasma being formed proximate a substrate, a remote plasma1160is formed in a region remote from a substrate16, for example, in a different plasma chamber or an isolated part of the plasma processing chamber810. The remote plasma1160is separated or isolated from the substrate16by a particle isolation structure1118. The particle isolation structure1118may be a filter, conduit, or orifice plate arranged to impede the transport of charged particles from the remote plasma source to the substrate16. In one embodiment, the remote plasma1160is an ICP. Alternatively, the remote plasma1160may be a CCP, an SWP, etc.

FIG.12illustrates a block diagram of an example plasma processing system including a non-resonant source power coupling electrode in accordance with an embodiment of the invention. The plasma processing system ofFIG.12may be used to perform any of the embodiment methods as described herein, such as the method ofFIG.1, for example.

Referring toFIG.12, a non-resonant plasma processing system1200includes a SP supply node81supplying source power1coupled to an non-resonant SP coupling electrode1215of a plasma processing chamber1210and a BP supply node82supplying bias power2coupled to a bias power coupling electrode19of the plasma processing chamber1210. The source power1is coupled to the non-resonant SP coupling electrode1215through a SP control path1201which includes a SP controller1226configured to control source power settings. For example, the SP controller1226may adjust gain settings for a SP RF function generator and amplifier1220and impedance matching settings for a SP impedance matching network1225. Similarly, the bias power2is coupled to BP coupling electrode19through a BP control path1202including a BP controller1236which controls bias settings of a BP RF function generator and amplifier1230and a BP impedance matching network1235.

Since the non-resonant plasma processing system1200couples source power1using a non-resonant structure, the SP impedance matching network1225is included in order to efficiently provide source power to a plasma. In order for maximum power to be transferred from the non-resonant SP coupling electrode1215to the plasma, the impedance of the load on the power supply should be the same as the impedance of the power supply itself. For example, the impedance of the load on the power supply may be influenced by the impedance of the plasma, which may depend on specific rapidly changing conditions such as chemistry, pressure, density, and others. Therefore, the SP impedance matching network1225may beneficially allow plasma conditions to vary while maintaining efficient power coupling of the source power1to the plasma60.

A SP pulse signal is generated using a SP pulse modulation circuit1251which may receive one or more plasma processing parameters as inputs. For example, as illustrated, the SP pulse modulation circuit1251receives a SP pulse frequency fSand a SP pulse width tp,S. The SP pulse modulation circuit1251then generates a SP pulse signal V(fS, tp,S) using fSand tp,S. In one embodiment, the SP pulse signal V(fS, tp,S) includes a high amplitude state of about 5 V and a low amplitude state of about 0 V. However, other voltage levels are also possible. The SP pulse frequency fScan range from about 0.1 Hz to about 10 kHz. Alternatively, the SP pulse frequency fScan range from about 1 kHz to about 5 kHz.

The SP RF function generator and amplifier1220receives the source power1from the SP supply node81and the SP pulse signal V(fS, tp,S) from the SP pulse modulation circuit1251and then generates SP pulses by amplifying and modulating the SP pulse signal V(fS, tp,S) with a function. The power amplification may range from a few watts (e.g., 1-2 W) to greater than 1000 kW. In one embodiment, the generated function may comprise an AC signal. The AC signal can be generated at a source frequency, which can fall within the RF range, very-high frequency (VHF) range, or microwave (MW) range of the electromagnetic spectrum. Alternatively, the generated function may comprise a DC signal such as a pulsed DC signal.

The SP pulses pass through the SP impedance matching network1225and to a SP directional coupler1227. Therefore, the SP directional coupler1227receives SP pulses with a time varying source voltage VS(t) and source current IS(t). The SP directional coupler1227is configured to pass the SP pulses to the non-resonant SP coupling electrode1215. The SP directional coupler1227is also coupled to the SP controller1226which may beneficially allow the SP controller1226to adjust source power settings based on a comparison of the forward source power Pf,Sand the reverse source power Pr,S, as illustrated. For example, the forward source power Pf,Smay be an indication of the magnitude of the power being transmitted in a forward direction (i.e., toward the SP coupling electrode) while the reverse source power Pr,Smay be an indication of the magnitude of the power being reflected in a reverse direction (i.e., away from the SP coupling electrode). Pf,Sand Pr,Smay be measured by the SP controller1226.

A similar feedback mechanism may be implemented between the BP controller1236and a BP directional coupler1237that receives time varying bias voltage VB(t) and bias current IB(t) so that bias power settings may be adjusted based on a comparison of the forward bias power Pf,Band the reverse bias power Pr,B. which may be an indication of the magnitudes of the power being transmitted in a forward direction (i.e., toward the BP coupling electrode) and the power being reflected in a reverse direction (i.e., away from the BP coupling electrode). Pf,Band Pr,Bmay be measured by the BP controller1236.

The SP RF function generator and amplifier1220, the SP impedance matching network1225, the SP controller1226, and the SP directional coupler1227are included in a non-resonant SP generator circuit1240which receives the source power1from the SP supply node81and provides SP pulses to the non-resonant SP coupling electrode1215. The non-resonant SP generator circuit1240may be a specific implementation of the SP generator circuit240ofFIG.2, for example. Similarly, the BP RF function generator and amplifier1230, the BP impedance matching network1235, the BP controller1236, and the BP directional coupler1237are included in a BP generator circuit1245which receives the bias power2from the BP supply node82and provides BP pulses to the BP coupling electrode19. The BP generator circuit1245may be a specific implementation of the BP generator circuit245ofFIG.2, for example.

A time delay tdelayis introduced between the SP pulses and BP pulses using a BP tdelaytiming circuit1252coupled to an output of the SP pulse modulation circuit1251. The SP pulse modulation circuit1251may transmit a signal to the BP tdelaytiming circuit1252, where the signal may be the SP pulse or a clock signal indicative of the SP pulse. The BP tdelaytiming circuit1252receives the time delay tdelayat an input and then sends a signal to the BP pulse modulation circuit1253. In one embodiment, the BP tdelaytiming circuit1252is triggered by the trailing edge of the SP pulse signal. Alternatively, the BP tdelaytiming circuit1252may be triggered by the leading edge of the SP pulse signal. The BP pulse modulation circuit1253generates a BP pulse signal using inputs (e.g., BP pulse frequency fBand BP pulse width tp,B) which is then sent to the BP RF function generator and amplifier1230.

When different gases are pulsed, an alternating time delay may be used. For example, a specific time delay may correspond to each gas or combination of gases during a given plasma process. Further, other plasma processing parameters may change for a particular gas or combination of gases such as the SP pulse frequency fSs, the SP pulse width tp,S, the BP pulse frequency fB, the BP pulse width tp,B, and others.

The function generated by the BP RF function generator and amplifier1230may comprise an AC signal. The AC signal can be generated at a bias frequency, which can also fall within the RF range, VHF range, or MW range. For example, the source frequency can exceed about 10 MHz, and the bias frequency can be less than about 15 MHz. Alternatively, for example, the source frequency can exceed about 50 MHz, and the bias frequency can be less than about 5 MHz. Alternatively yet, the source frequency can range from about 50 MHz to about 150 MHz, and the bias frequency can range from about 1 MHz to about 5 MHz.

FIG.13illustrates a block diagram of an example plasma processing system including a resonant source power coupling electrode in accordance with an embodiment of the invention. The plasma processing system ofFIG.13may be used to perform any of the embodiment methods as described herein, such as the method ofFIG.1, for example.

Referring toFIG.13, a resonant plasma processing system1300includes a SP control path1301which includes a resonant SP coupling electrode1315. The resonant plasma processing system1300is similar the non-resonant plasma processing system1200except that the SP impedance matching network1225is omitted in the SP control path1301because the resonant SP coupling electrode1315may provide the advantage of efficient source power coupling to a plasma60without impedance matching. Accordingly, a SP RF function generator and amplifier1220provides SP pulses directly to a SP directional coupler1227which may provide feedback to a SP controller1327. The SP RF function generator and amplifier1220, the SP controller1226, and the SP directional coupler1227are included in a resonant SP generator circuit1340which receives the source power1from the SP supply node81and provides SP pulses to the resonant SP coupling electrode1315. The resonant SP generator circuit1340may be a specific implementation of the SP generator circuit240ofFIG.2, for example.

The resonant plasma processing system1300may also advantageously enable agile pulsing of the source power. For example, impedance matching networks may be unable to respond as quickly as a matchless resonant structure such as the resonant SP coupling electrode1315. Therefore, at higher SP pulse frequencies, impedance matching networks may be limited to lower frequencies in order to provide efficient source power to the plasma. In various embodiments, the resonant SP coupling electrode1315comprises a helical resonator antenna1329.

FIG.14illustrates a schematic diagram of an example helical resonator plasma processing system in accordance with an embodiment of the invention. The helical resonator plasma processing system may be a specific implementation of other plasma processing systems such as the plasma processing system200ofFIG.2, the ICP processing system900ofFIG.9and/or the resonant plasma processing system1300ofFIG.13, as examples. Specifically, the source power coupling electrode is formed as a helical resonator antenna. Similarly labeled elements may be as previously described.

Referring toFIG.14, a helical resonator plasma processing system1400includes a grounded outer structure1410surrounding a resonant SP coupling electrode1315implemented as a helical resonator antenna1329which in turn surrounds a dielectric inner surface1411. The helical resonator antenna1329is grounded at one end and left free at the other. An AC source power supply881is coupled to a SP generator circuit240which is coupled to the helical resonator antenna1329at an appropriate distance from the grounded connection. The source power coupling location (also referred to as a tap position) may depend on operating frequency as well as other considerations. A helical resonator plasma1460is generated which is inductively coupled to the resonant SP coupling electrode1315. For example, the dielectric inner surface1411may be provided between the helical resonator plasma1460and the helical resonator antenna1329to facilitate inductive coupling. An AC bias power supply882may be coupled to a BP generator circuit245which is coupled to a lower plate electrode (LEL)819. The lower plate electrode (LEL)819serves as an electrostatic chuck (ESC) to support and retain a substrate16.

The helical resonator antenna1329may be a full-wave, half-wave, or quarter-wave antenna. For example, if the helical resonator antenna1329is driven at using RF power with a frequency of 13.56 MHz, a quarter-wave helical resonator antenna may be about 5.5 m in length. As the RF frequency increases, the length of the helical resonator antenna1329may decrease. For example, a quarter-wave helical resonator antenna driven at about 50 MHz may be about 1.5 m in length.

FIG.15illustrates an example method of plasma processing in accordance with an embodiment of the invention. The method ofFIG.15may be performed by any of the embodiment plasma processing systems as described herein, such as plasma processing system200ofFIG.2, for example. It is noted thatFIG.15is not intended to limit method steps to a particular order. Additionally, any of the steps as described inFIG.15may be performed concurrently in any combination as well as separately. Accordingly, variation of the ordering and/or timing of the below method steps is within the scope of the method as described as may be apparent to a person of skill in the art.

Step1501of a method1500of plasma processing includes outputting a signal to a function generator using a pulse modulation circuit. Step1502includes generating a SP pulse using the function generator in response to outputting the signal. Step1503includes providing the SP pulse at a SP coupling electrode of a plasma processing chamber to generate a plasma. Step1504includes generating a BP pulse by triggering a delay relative to the SP pulse. Step1505includes providing the BP pulse at a BP coupling electrode of the plasma processing chamber. Step1506includes performing a plasma deposition or etch process on a substrate disposed in the plasma processing chamber where providing the BP pulse accelerates ions from the plasma towards the substrate.

Example embodiments of the invention are summarized here. Other embodiments can also be understood from the entirety of the specification as well as the claims filed herein.

A plasma processing system including a vacuum chamber; a first coupling electrode configured to provide power for generation of a plasma in the vacuum chamber, the first coupling electrode being further configured to couple SP pulses to the plasma; a substrate holder disposed in the vacuum chamber, the substrate holder being configured to support a substrate; a second coupling electrode configured to couple BP pulses to the substrate; and a controller configured to control a first offset duration between the SP pulses the BP pulses.

The plasma processing system of example 1, wherein the first coupling electrode is capacitively coupled to the plasma, wherein the plasma processing system includes a capacitively coupled plasma processing system; or the first coupling electrode is inductively coupled to the plasma, wherein the plasma processing system includes a inductively coupled plasma processing system; or wherein the first coupling electrode is coupled to the plasma through a microwave waveguide and slot antenna, wherein the plasma processing system includes a surface wave plasma processing system.

The plasma processing system of one of examples 1 and 2, further including a first function generator configured to generate the SP pulse, wherein the controller includes a timing circuit configured to generate the first offset duration; and a first pulse modulation circuit including a first output coupled to an input of the first function generator and a second output coupled to the timing circuit.

The plasma processing system of example 3, further including a second pulse modulation circuit coupled to the timing circuit; and a second function generator coupled to the second pulse modulation circuit and configured to generate the BP pulses.

The plasma processing system of one of examples 3 and 4, wherein the timing circuit is further configured to control a second offset duration between the BP pulses and the SP pulses.

The plasma processing system of one of examples 3 to 5, wherein the first pulse modulation circuit includes a first input configured to receive a first pulse frequency, and a second input configured to receive a first pulse width, and wherein the first pulse modulation circuit is further configured to generate a SP pulse signal at an output based on the first pulse frequency and the first pulse width.

The plasma processing system of one of examples 3 to 6, wherein the timing circuit includes a timing circuit input configured to receive a time delay, and wherein the timing circuit is further configured to set the first offset duration based on the time delay.

The plasma processing system of one of examples 3 to 7, wherein the first function generator is configured to generate the SP pulses by modulating a SP pulse signal received from the first pulse modulation circuit with an alternating current (AC) signal generated at a first frequency.

The plasma processing system of example 8, further including a second pulse modulation circuit coupled to the timing circuit and configured to generate a BP pulse signal; and a second function generator coupled to the second pulse modulation circuit and configured to generate the BP pulses by modulating the BP pulse signal with an AC signal generated at a second frequency, wherein the second frequency is less than about 15 MHz, and wherein the first frequency is greater than about 10 MHz.

An apparatus including a vacuum chamber; a coupling electrode coupled to a source power (SP) supply node and configured to generate a plasma within the vacuum chamber using a first sequence of SP pulses; and a substrate holder coupled to a bias power (BP) supply node and disposed within the vacuum chamber, the substrate holder being configured to support a substrate to be processed by the plasma, wherein a second sequence of BP pulses is configured to accelerate ions of the plasma towards the substrate.

The apparatus of example to, wherein the first SP pulse and the BP pulse are at least partially non-overlapping in time.

The apparatus of one of examples 10 and 11, wherein the coupling electrode is a resonant coupling electrode.

The apparatus of example 12, further including a function generator; and a directional coupler including an output directly coupled to the resonant coupling electrode and an input directly coupled to the function generator.

The apparatus of one of examples 12 and 13, wherein the resonant coupling electrode is a helical resonator antenna.

The apparatus of example to, further including a function generator; an impedance matching network coupled to the function generator; and a directional coupler including an input coupled to the impedance matching network, wherein the coupling electrode is a non-resonant coupling electrode, and wherein the directional coupler further includes an output coupled to the non-resonant coupling electrode.

A method of plasma processing including using a first pulse modulation circuit, outputting a first signal to a first function generator; generating a first source power (SP) pulse using the first function generator in response to the outputting the first signal; providing the first SP pulse at a first coupling electrode of a vacuum chamber to generate a plasma; generating a bias power (BP) pulse by triggering a delay relative to the first SP pulse; providing the BP pulse at a second coupling electrode of the vacuum chamber; and performing a plasma deposition or etch process on a substrate disposed in the vacuum chamber, wherein providing the BP pulse accelerates ions from the plasma towards the substrate.

The method of example 16, wherein the delay includes an offset duration between about −15 μs and about 20 μs; and a leading edge of the BP pulse is separated from a trailing edge of the first SP pulse by the offset duration.

The method of one of examples 16 and 17, further including generating a second SP pulse using the first function generator, wherein a trailing edge of the BP pulse is separated from a leading edge of the second SP pulse by an offset duration that is greater than zero seconds.

The method of one of examples 16 to 18, further including generating a second SP pulse using the first function generator, wherein a trailing edge of the BP pulse overlaps with a leading edge of the second SP pulse by an offset duration that is greater than zero seconds.

The method of one of examples 16 to 19, further including generating a second SP pulse using the first function generator, wherein a leading edge of the first SP pulse is separated from a leading edge of the second SP pulse by a pulse modulation period that is between about 200 μs and about 1000 μs.

The power control techniques as described herein may be controlled by a controller. It is also noted that the controller may be implemented using one or more programmable integrated circuits that are programmed to provide the functionality described herein. For example, one or more processors (e.g., microprocessor, microcontroller, central processing unit, etc.), programmable logic devices (e.g., CPLD (complex programmable logic device), FPGA (field programmable gate array), etc.), and/or other programmable integrated circuits may be programmed with software or other programming instructions to implement any of the functionality described herein. It is further noted that the software or other programming instructions may be stored in one or more non-transitory computer-readable mediums (e.g., memory storage devices, FLASH memory, DRAM memory, reprogrammable storage devices, hard drives, floppy disks, DVDs, CD-ROMs, etc.), and the software or other programming instructions, when executed by the programmable integrated circuits, cause the programmable integrated circuits to perform the processes, functions, and/or capabilities described herein. Other variations of the above could also be implemented.

One or more deposition processes may be used to form material layers using the plasma process described herein. For a plasma deposition process, a precursor gas mixture may be used including but not limited to hydrocarbons, fluorocarbons, or nitrogen containing hydrocarbons in combination with one or more dilution gases (e.g., argon, nitrogen, etc.) at a variety of pressure, power, flow and temperature conditions. Similarly, one or more etch processes may be used to etch material layers using the plasma process described herein. For example, plasma etch processes may be implemented using plasma containing fluorocarbons, oxygen, nitrogen, hydrogen, argon, and/or other gases. In addition, operating variables for process steps, for example, the chamber temperature, chamber pressure, flowrates of gases, frequency and/or power applied to electrode assembly in the generation of plasma, and/or other operating variables for the processing steps may be controlled. Variations of the above may also be implemented while still taking advantage of the techniques described herein.

While this invention has been described with reference to illustrative embodiments, this description is not intended to be construed in a limiting sense. Various modifications and combinations of the illustrative embodiments, as well as other embodiments of the invention, will be apparent to persons skilled in the art upon reference to the description. For example, the embodiments ofFIGS.3-7may be combined in further embodiments. It is therefore intended that the appended claims encompass any such modifications or embodiments.