CLOCK SELECTION METHOD FOR MULTIPLYING DELAY LOCKED LOOP

There is provided a method for generating a select signal for a multiplexer of a Multiplying Delay Locked Loop (MDLL). The method includes determining that an output of a divider of the MDLL is a high level, determining that an output signal of a multiplexed voltage controlled oscillator (VCO) of the MDLL is a falling edge after the output of the divider is the high level and inserting a select signal as a select input to the multiplexer at the falling edge of the output signal of the multiplexed VCO in response to determining that the output of the divider has achieved the high level.

CROSS-REFERENCE TO RELATED APPLICATION

This application is based on and claims priority from Indian Patent Application No. 202241040410 filed on Jul. 14, 2022, in the Indian Intellectual Property Office, the disclosure of which is incorporated by reference herein in its entirety.

BACKGROUND

The disclosure relates to phase locked loops (PLLs), and more specifically is related to a method of clock selection for a Multiplying Delay Locked Loop (MDLL).

2. Description of Related Art

A Multiplying Delay Locked Loop (MDLL) is a type of electronic circuit for frequency multiplication of an input clock signal. Major components of the MDLL are a multiplexed voltage controlled ring oscillator, a divider, a phase detector and a loop filter.FIG.1shows a plurality of electronic components of a related art phase locked loops (PLLs).

In related art architectures, the internal components of the ring oscillator are accessed for MDLL multiplexer (Mux) selection signal (SEL) generation, and are generally designed for 5-stage ring oscillator, which may not work with a 3-stage ring oscillator. Also some of the related art architectures not only need internal components of ring oscillator but also, special conditions like, differential ring oscillator with skewed rise, fall times.

Using internal phases of the ring oscillator for Mux selection limits a coarse and fine control options for the ring oscillator.

Many of the related art architectures work only at Full-Rate, wherein an edge of an output signal of the voltage controlled oscillator (VCOOUT) is replaced at a rate of a Reference Frequency (FREF) or corresponding VCOOUT edge is replaced for every reference edge, wherein the reference edge indicates a reference input signal (REF)

However, to track and correct a time offset error between frequency of VCOOUT (FVCO) and FREF due to drift in the ring oscillator frequency (MDLL loop's long term stability/lock), the SEL signal is generated at half-rate or quarter rate such that the VCOOUT edge is replaced for every alternate REF edge or once for every ‘4’ REF edges.

Thus, there is a need to provide an efficient MDLL selection without accessing the internal components of the ring oscillator.

SUMMARY

An object of the disclosure is to provide a Multiplying Delay Locked Loop (MDLL) with a selection logic which does not access the internal components of the ring oscillator and generates SEL signal at either Full-rate or at half-rate or at quarter rate of FREF.

According to an aspect of the disclosure, there is provided a method for generating a select signal for a multiplexer of a Multiplying Delay Locked Loop (MDLL), the method including: determining that an output of a divider of the MDLL is a high level, determining that an output signal of a multiplexed voltage controlled oscillator (VCO) of the MDLL is a falling edge after the output of the divider is the high level and inserting a select signal as a select input to the multiplexer at the falling edge of the output signal of the multiplexed VCO in response to determining that the output of the divider has achieved the high level.

The select signal is generated based on the output signal of the multiplexed VCO, a reference signal and the output of the divider.

The select signal is generated using a select signal generation circuit, and wherein the select signal generation circuit includes: a plurality of D-flip flops, wherein the output signal of the multiplexed VCO and the output of the divider is input to the plurality of D-flip flops, and a plurality of logic gates.

The select signal is a high level at a second falling edge of the output signal of the multiplexed VCO when the output of the divider has achieved a rising edge.

The select signal is a high level at a third falling edge of the output signal of the multiplexed VCO when the output of the divider has achieved a rising edge.

The select signal is a low level at a first rising edge of the output signal of the multiplexed VCO, after the select signal is made a high level, when a reference signal is a high level.

The select signal is a low level at rising edge of a REF signal (600), when output signal of the multiplexed VCO has achieved first rising edge after select signal is made a high level.

The select signal as the select input to the multiplexer at the falling edge of the output signal of the multiplexed VCO includes: determining that the falling edge of the output signal of the multiplexed VCO is a second falling edge; and inserting the select signal at the second falling edge of the output signal of the multiplexed VCO.

The inserting the select signal as the select input to the multiplexer at the falling edge of the output signal of the multiplexed VCO includes: determining that the falling edge of the output signal of the multiplexed VCO is a third falling edge; and inserting the select signal at the third falling edge of the output signal of the multiplexed VCO.

The method further includes: determining that the select signal is a high level, determining that the output signal of the multiplexed VCO is a rising edge, determining that a reference signal is a high level and de-inserting the select signal as the select input to the multiplexer at the rising edge of the output signal of the multiplexed VCO and wherein the reference signal is a high level.

The de-inserting the select signal as the select input to the multiplexer at the rising edge of the output signal of the multiplexed VCO includes: determining that the rising edge of the output signal of the multiplexed VCO is a first rising edge, and de-inserting the select signal at the first rising edge of the output signal of the multiplexed VCO and the reference signal is a high level.

The de-inserting the select signal as the select input to the multiplexer at the rising edge of the output signal of the multiplexed VCO includes: determining that the rising edge of the output signal of the multiplexed VCO is a first rising edge after the select signal is a high level, determining that the reference signal is a low level at the first rising edge of the output signal of the multiplexed VCO and the reference signal has a rising edge after output signal of the multiplexed VCO first rising edge and de-inserting the select signal at the rising edge of the reference signal.

The select signal is selected as the select input to the multiplexer based on the output of the divider and output signal of the multiplexed VCO for insertion.

The select signal is selected as in as the select input to the multiplexer based on a reference signal and output signal of the multiplexed VCO for de-insertion.

According to another aspect of the disclosure, there is provided an apparatus including: a first circuit configured to determine that an output of a divider of a Multiplying Delay Locked Loop (MDLL) is a high level, a second circuit configured to determine that an output signal of a multiplexed voltage controlled oscillator (VCO) of the MDLL is a falling edge after the output of the divider is the high level and a third circuit configured to generate a select signal to be inserted as a select input to a multiplexer of the MDLL at the falling edge of the output signal of the multiplexed VCO based on a determination that the output of the divider has achieved the high level.

The select signal is generated based on the output signal of the multiplexed VCO, a reference signal and the output of the divider.

The third circuit is signal generation circuit includes: a plurality of D-flip flops, wherein the input to the plurality of D-flip flops is the output signal of the multiplexed VCO and the output of the divider; and a plurality of logic gates.

The third circuit is further configured to: determine that the falling edge of the output signal of the multiplexed VCO is a third falling edge; and generate the select signal at the third falling edge of the output signal of the multiplexed VCO.

DETAILED DESCRIPTION

Accordingly, embodiments herein provides a MDLL selection method without accessing internal components of a ring oscillator in the MDLL. According to an embodiment, the method and the MDLL uses a SEL input to a multiplexer of multiplexed ring oscillator, wherein the SEL input is based on a divider output, the ring oscillator output and a reference signal.

According to aspect of the disclosure, there is provided a method of generating the SEL signal. Unlike a related art method, the method of SEL selection according to an embodiment of the disclosure ensures that there is no dependency on the duty cycle of the divider signal (DIV).

Referring now to the drawings, and more particularly toFIGS.2,3A-3D,4A-4D,5,6A-6B, and7A-7Bwhere similar reference characters denote corresponding features consistently throughout the figures, there are shown preferred embodiments.

FIG.2is a block diagram of an MDLL (100), according to an embodiment of the disclosure.

In an embodiment, the MDLL (1000) includes a phase detector (100), a loop filter (200), a multiplexed voltage controlled oscillator (300), a divider (400), SEL signal (500), and a reference signal (REF) (600).

The phase detector (100) is for detecting a phase difference between an input and an output of a loop divider of the MDLL (1000). The input to the phase detector (100) is the REF signal (600) and an output (DIV) of the divider (400). An output of the phase detector (100) is provided as an input to the loop filter (200). An output (Vctr) of the loop filter is provided as an input to the multiplexed voltage controlled ring oscillator (300).

The multiplexed voltage controlled ring oscillator (300) includes a plurality of inverters (301-303) and a multiplexer (304). The output Vctr of the loop filter is provided as in input to each inverter (301-303) of the multiplexed voltage controlled ring oscillator (300).

There are multiple intermediate outputs of the multiplexed voltage controlled ring oscillator (300) from the plurality of inverters (301-304). A final output of the multiplexed voltage controlled ring oscillator (300) (VCOOUT) is an input to the multiplexer (304). Another input to the multiplexer (304) is the REF signal (600).

Accordingly, the method according to an embodiment of the disclosure ensures that there is no dependency on a DIV signal duty.

According to an embodiment, the DIV signal is loop divider output (o/p) and the duty cycle of the DIV signal varies based on divider implementation and can be as low as 1/Ndiv for a full rate operation, where Ndiv=Loop division factor.

According to an embodiment, for half rate and quarter rate operations, the divider (400) implementations give DIV signal with 50% duty cycle.

Since, the circuit has to work for all the cases, full-rate, half-rate and quarter-rate, and all types of divider implementations, it is ensured that the method for the MDLL according to an embodiment works independent of the duty cycle of the DIV signal.

Further, as the method according to an embodiment does not use any intermediate outputs from the plurality of inverters (301-303), the MDLL operates independent of the multiplexed voltage controller ring oscillator stages and type (single ended/differential).

In an embodiment, the SEL signal (500) is provided to the multiplexer (304) for selecting an input of the multiplexer (304). The output of the multiplexer (304) may be either the REF signal (600) or the final output (VCOOUT) of the voltage controlled ring oscillator (300) depending upon the SEL signal (500).

In an embodiment, the method further includes generating the SEL signal (500) based on the divider output (DIV), the REF signal (600) and the final VCOOUT.

In an embodiment, the SEL signal is inserted (a high level, 1) in the multiplexer (304) at a second falling edge of the VCOOUT, after the DIV is a high level.

In another embodiment, the SEL signal is inserted in or provided to the multiplexer (304) at a third falling edge of the VCOOUT, after the DIV is a high level.

In another embodiment, the SEL signal is de-inserted (a low level, 0) from the multiplexer (304) at first rising edge of the VCOOUT, after SEL is made A high level, when the REF signal is ‘1’.

In another embodiment, the SEL signal is de-inserted (a low level, 0) from the multiplexer (304) at rising edge of REF signal (600), when VCOOUT has achieved rising edge, after SEL is made a high level.

According to an embodiment, a logic circuitry for generation of the SEL signal may be implemented using an arrangement of logic gates, such as AND, OR, NOR, INV, MUX and set/reset Flip Flops.

According to an embodiment, using only the final output (VCOOUT) of voltage controlled ring oscillator (300), the output of divider (DIV) and the REF signal (600), and without internal signals of the voltage controlled ring oscillator (300), the SEL signal (logic) can achieve a maximum MDLL SEL signalhigh duration of 1/FVCO, where FVCO is the frequency of VCOOUT. Further, according to an embodiment, the method and the MDLL (1000) works for any FREF/n (‘n’ is an integer≥1) rate edge replacement.

FIG.3Ais a schematic diagram, illustrating a circuit (300A) generation of the SEL signal (500), according to an embodiment of the disclosure.

As seen inFIG.3A, the SEL signal (500) is generated using the DIV, the REF signal (600) and the VCOOUT. The circuit (300A) comprises a plurality of flip-flops, a plurality of AND gates, a plurality of OR gates, a NOT gate and a MUX.

In an embodiment, all ‘set’ flops will be in ‘set’ state (Q=1) and ‘reset’ flops will be in reset state (Q=0), wherein OPEN=0, CLOSE=1 and SEL=0.

At an instance the ENB is made 0 from 1, all the flip flops except for the FF21are out of ‘set’/‘reset’ state such that outputs are transparent to corresponding input and the clock.

The FF21is in ‘set’ state as RST_EN is still ‘1’, and CLOSE=1.

The DIV=0 and hence at 1stVCOOUT rising edge, an output of FF11goes to ‘0’. It will go to ‘1’, only on the 1strising edge of VCOOUT after DIV goes to ‘1’.

At the next falling edge of VCOOUT, OPEN=1 and hence SEL=1, as CLOSE is already ‘1’. The moment OPEN=‘1’, RST_EN=0 and FF21is out of ‘reset’ state; SEL=1 and the Mux output is transparent to Inv (REF).

The moment SEL becomes ‘1’, FF11goes to ‘set’ state and FF11o/output=1, irrespective of DIV and OPEN. That is, SEL no longer responds to DIV and SEL become ‘0’ only when CLOSE=0.

It is to be noted that DIV, for a minimum duty cycle case of 1/Ndiv, will have a high duration of just 1/FVCO. For instance, DIV goes to ‘0’ before next rising edge of VCOOUT. However, SEL=1 and hence FF11reaches ‘set’ state, before next VCOOUT rising edge and DIV becoming ‘0’ within 1/FVCO time, will not affect.

When the condition of REF=1 and the rising edge of VCOOUT after SEL=1 is met: CLOSE=0 (as FF21output (o/p)=0, Mux output=0, RST_EN=0) and hence SEL=0.

The moment SEL=0: FF11is out of ‘set’ state i.e. OPEN is again transparent to DIV and VCOOUT; output of Mux in CLOSE path is ‘0’ irrespective of REF.

OPEN goes to ‘0’ on 2ndfalling edge of VCOOUT after both SEL and DIV are ‘0’. Till then, OPEN=1 and so RST_EN=0 and CLOSE=0 and so SEL will remain ‘0’.

After OPEN goes to ‘0’, RST_EN=1 and hence CLOSE=1.

In another embodiment, the SEL (500) is generated using the components as listed above. In another embodiment, the SEL signal may be generated using other electronic components, however the logic remains the same.

The circuit inFIG.3Aensures that the SEL signal (500) is inserted in the multiplexer (304) at 2ndfalling edge of the VCOOUT signal after the DIV signal has achieved a high level. The high level and the low level in the current specification indicates a binary numeral “1” and “0” respectively.

FIG.3Bis a schematic diagram, illustrating a circuit (300B) for generation of the SEL signal (500) at a third falling edge of the VCOOUT, according to an embodiment of the disclosure.

As seen inFIG.3B, the SEL signal (500) is generated using the DIV, the REF signal (600) and the VCOOUT. The circuit (300B) comprises a plurality of flip-flops, a plurality of AND gates, a plurality of OR gates, a NOT gate and a MUX.

InFIG.3B, additional flip-flop is added which is clocked by falling edge of VCOOUT, in the OPEN path, to add one more falling edge to achieve OPEN and hence the SEL signal (500) insertion is on3rd falling edge instead of 2ndfalling edge of VCOOUT as seen inFIG.3A.

As seen inFIG.3B, a ‘set’ of FF11is generated from AND(CLOSE, O_IM) instead of the SEL signal (500), inFIG.3A. Timing of rising edge of O_IM inFIG.3Bis aligned with timing of rising edge of OPEN inFIG.3A: both become ‘1’ at the same VCOOUT falling edge after DIV=1. So AND (CLOSE, O_IM) inFIG.3Bwill have same timing as SEL=AND(CLOSE, OPEN) ofFIG.3Afor both rising and falling edges. Hence ‘set’ of FF11will have same timing for bothFIG.3AandFIG.3B.

FIG.3Cis a schematic diagram, illustrating a circuit (300C) for generation of the SEL signal (500) at a second falling edge of the VCOOUT, according to an embodiment of the disclosure.

As seen inFIG.3C, the SEL signal (500) is generated using the DIV, the REF signal (600) and the VCOOUT. The circuit (300C) comprises a plurality of flip-flops, a plurality of AND gates, a plurality of OR gates, a NOT gate and a MUX.

According to an embodiment, the operation ofFIG.3Cis same as that ofFIG.3A, but an additional flip-flop on ENB with CLK=REF and an AND gate is added.

FIG.3Dis a schematic diagram, illustrating a circuit (300D) for generation of the SEL signal (500) at a third falling edge of the VCOOUT, according to an embodiment of the disclosure.

As seen inFIG.3D, the SEL signal (500) is generated using the DIV, the REF signal (600) and the VCOOUT. The circuit (300D) comprises a plurality of flip-flops, a plurality of AND gates, a plurality of OR gates, a NOT gate and a MUX.

According to an embodiment, the operation ofFIG.3Dis same as that ofFIG.3B, but an additional flip-flop on ENB with CLK=REF and an AND gate is added.

It is to be noted that inFIG.3D, a start of the SEL generation block is delayed till falling edge of REF after ENB=0, to ensure the SEL generation block always start from a correct known state and hence works for all conditions.

FIG.4Ais a waveform diagram, illustrating generation of the SEL signal at a second falling edge of a VCOOUT, according to an embodiment of the disclosure;

As seen inFIG.4A, a first waveform (401) is of the final output VCOOUT of the multiplexed voltage controlled oscillator (300) with rising and falling edges. The first waveform includes a first falling edge (401a) and a second falling edge (401b) of VCOOUT after the DIV signal is a high level. A second waveform (402) is the DIV signal, which achieves a high level at (402a). A third waveform of reference signal REF signal (600) achieves a high level at (403a). A fourth waveform is of select signal SEL (500), which is generated using the circuit shown inFIG.3Aand based on the inputs, VCOOUT (401), the DIV signal (402) and the REF signal (600).

The SEL signal (500) inFIG.4Ais a high level at the second falling edge (401b) of the VCOOUT (401), where the DIV signal has already achieved a high level.

FIG.4Bis a waveform diagram, illustrating generation of the SEL signal at a third falling edge of a VCOOUT, after DIV=1, according to an embodiment of the disclosure.

As seen inFIG.4B, a first waveform (401) is of the final output VCOOUT of the multiplexed voltage controlled oscillator (300) with rising and falling edges. The first waveform401includes a first falling edge (401a), a second falling edge (401b) and a third falling edge (401c) after DIV signal is a high level. A second waveform (402) is the DIV signal, which achieves a high level at (402a). A third waveform of reference signal REF signal (600) achieves a high level at (403a). A fourth waveform is of select signal SEL (500), which is the SEL signal generated using the circuit shown inFIG.3Cand based on the inputs (401), the DIV signal (402) and the REF signal (600).

The SEL signal (500) inFIG.4Bis a high level at the third falling edge (401c) of the VCOOUT (401), where the DIV signal has already achieved a high level.

FIG.4Cis a waveform diagram, illustrating generation of the SEL signal for a half rate mode, according to an embodiment of the disclosure. For the half-rate mode, an edge replacement is done once for every ‘2’ REF edges. In line with this, SEL signal is generated for every alternate REF edge.

FIG.5is another schematic diagram, illustrating a circuit (501) for generating the SEL signal (500), according to an embodiment of the disclosure.

As seen inFIG.5, the SEL signal (500) is generated using the DIV signal, the REF signal (600) and the VCOOUT. The circuit (500) includes a plurality of flip-flops, a plurality of AND gates, a plurality of OR gates, a plurality of NOT gate and a MUX.

The SEL (500) is generated using the components as listed above. In another embodiment, the SEL signal (500) may be generated using other electronic components, however the logic remains the same.

The circuit inFIG.5ensures that the SEL signal (500) can be inserted in the multiplexer (304) at 2ndfalling edge of the VCOOUT signal after the DIV signal has achieved a high level. The high level and the low level in the current specification indicates a binary numeral “1” and “0” respectively.

Further, the circuit inFIG.5also ensures that the SEL signal (500) may be de-inserted from the multiplexer (304) at 1strising edge of the VCOOUT signal after the SEL signal is made a high level and the REF signal (600) is a high level. The high level and the low level in the current specification indicates a binary numeral “1” and “0” respectively.

In an embodiment, when the ENB=1, all ‘set’ flops will be in ‘set’ state (Q=1) and ‘reset’ flops will be in reset state (Q=0) and OPEN=0, CLOSE=1 and SEL=0. At the instance block enabled i.e. ENB=140, FF41is out of ‘set’ state and FF41will be transparent to ENB. After 1stfalling edge of REF: all flops in OPEN path (FF11to FF13) and FF22will be out of ‘set’/‘reset’ state such that the outputs are transparent to corresponding input and clock.

FF21will still be in ‘reset’ state and DF of FF21and DF_dly and FF22will continue to be at ‘0’. FF31will still be in ‘set’ state as RST_EN is still ‘1’ and CLOSE=1.

On 1strising edge of DIV, FF11, Dr=1 and FF21will be out of ‘reset’ state. At the next 2ndfalling edge of VCOOUT, after DIV rising edge, OPEN=1 and hence SEL=1, as CLOSE is already ‘1’.

The moment OPEN=‘1’, RST_EN=0 and FF31is out of ‘reset’ state; SEL=1 and the Mux output is transparent to Inv(REF). Moreover, FF11input is VDD and FF11output can go to ‘0’, only when it is ‘reset’. Also, FF11output=1, irrespective of DIV, until it is ‘reset’, OPEN no longer responds to DIV and SEL can/will become ‘0’ only when CLOSE=0. When the condition of REF=1 and a rising edge of VCOOUT after SEL=1 is met: CLOSE=0 (as FF31output=0, Mux output=0, RST_EN=0) and hence SEL=0.

When the condition of SEL=0 and a rising edge of VCOOUT after a falling edge of DIV is met: Inv(SEL)=1 and Df_dly=1, and FF11is ‘reset’. Here, SEL goes from 0 to 1, on 2ndfalling edge and 2ndrising edge of VCOOUT. DIV, for the minimum duty cycle case of 1/Ndiv, goes to ‘0’ b/w 1strising edge and 1stfalling edge of VCOOUT; To ensure that, FF11is not reset till SEL=1, Df_dly should become ‘1’, only after, 1 rising edge of VCOOUT after DIV falling edge. This is achieved with FF21and FF22.

Once FF11is reset: OPEN goes to ‘0’ on 2ndfalling edge of VCOOUT. Till then, OPEN=1 and so RST_EN=0 and CLOSE=0 and so SEL will remain ‘0’.

Once FF11is reset: Drb=1 and FF21is reset. After one rising edge of VCOOUT, Df_dly=0 and FF11is out of ‘reset’. For instance, OPEN is again transparent to DIV and VCOOUT. After OPEN goes to ‘0’, RST_EN=1 and hence CLOSE=1.

FIG.6Ais a flow diagram for generation of the SEL signal, according to an embodiment inFIG.3Cof the disclosure.

As seen inFIG.6A, at operation (601a), the flow determines that a signal ENB is 0. The ENB is a logical inversion of EN, which the enable signal for the block. According to an embodiment, the block is enabled when EN=1 or ENB=0.

Further, at operation (602a), the method includes determining that the DIV signal is a high level and the VCOOUT signal is rising from 0-1 (i.e., from a low level to a high level). At operation (603a), the method includes determining that the VCOOUT is at a falling edge after the rising edge at (602a) and the edge of the VCOOUT is the first falling edge. At operation (604a), after satisfying the conditions from (601a-603a), SEL signal is set a high level. Further, at operation (605a), the VCOOUT is again rising from 0-1, which is the first rising edge after the SEL is a high level, and the REF signal (600) is 1. Then at operation (606a), the SEL signal is set a low level due to the rising edge of the VCOOUT and REF is ‘1’.

FIG.6Bis a flow diagram for generation of the SEL signal, according to an embodiment inFIG.5of the disclosure.

As seen inFIG.6B, at operation (601b), the flow determines that a signal ENB is 0. Further, at operation (602b), the method includes determining that the DIV signal is becoming a high level from a low level (i.e., from 0 to 1). At operation (603b), the method includes determining that the VCOOUT is at a falling edge after the DIV rising edge at operation (602b) and the edge of the VCOOUT is the second falling edge. At operation (604b), after satisfying the conditions from operations (601b-603b), SEL signal is set a high level. Further, at operation (605b), the VCOOUT is again rising from 0-1, which is the first rising edge after SEL is a high level, and the REF signal (600) is 1. Then, at operation (606b), the SEL signal is set a low level due to the rising edge of the VCOOUT.

FIGS.7A and7Bare simulation waveforms for the MDLL selection, according to an embodiment of the disclosure.

As seen inFIG.7A, a first waveform (701a) is of a signal ENB.

A second waveform (702a) is of the final output VCOOUT of the multiplexed voltage controlled oscillator (300) with rising and falling edges. A third waveform (703) is the REF signal, which achieves a high level at (703a1,703b1and703c1). A fourth waveform (704a) is the DIV signal and a fifth waveform (705a) is the SEL signal generated using the circuit shown inFIGS.3A-3DandFIG.5and based on the inputs (701a), (702a), (703a) and (704a).

The SEL signal (705a) inFIG.7Ais a high level at the falling edge of the VCOOUT (702a), where the DIV (704a) signal has already achieved a high level for a full rate operation

As seen inFIGS.7B, a first waveform (701b) is of a signal ENB.

A second waveform (702b) is of the final output VCOOUT of the multiplexed voltage controlled oscillator (300) with rising and falling edges. A third waveform (703b) is the REF signal. A fourth waveform (704b) is the DIV signal and a fifth waveform (705b) is the SEL signal generated using the circuit shown inFIGS.3A-3DandFIG.5and based on the inputs (701b), (702b), (703b) and (704b).

The SEL signal (705b) inFIG.7Bis a high level at the falling edge of the VCOOUT (702b), where the DIV (704b) signal has already achieved a high level for a half rate operation.

The embodiments disclosed herein can be implemented using at least one software program running on at least one hardware device and performing network management functions to control the elements.