SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

A semiconductor device and a method for manufacturing the same are provided. The semiconductor device includes a channel layer, a gate element on the channel layer, and source/drain elements at least partly embedded in the channel layer. The source/drain elements are on opposite sides of the gate element. The source/drain elements include a metal element and a lower silicide element between the metal element and the channel layer. The lower silicide element has a hydrogen content less than 2 at %.

This application claims the benefit of People's Republic of China application Serial No. 202210378793.5, filed Apr. 12, 2022, the subject matter of which is incorporated herein by reference.

BACKGROUND

Technical Field

The disclosure relates to a semiconductor device and a method for manufacturing the same, and more particularly to a semiconductor device including a high electron mobility transistor (HEMT) structure and a method for manufacturing the same.

Description of the Related Art

High electron mobility transistors have been widely used in various applications in recent years. Specifically, the high electron mobility transistors include two-dimensional electron gas (2-DEG) with high electron mobility, making these transistors suitable for various high-speed and high-power electronic components.

However, there are still several important issues unaddressed in the development of high electron mobility transistors. For example, a large contact resistance at the junction of a source/drain element and a channel layer may decrease the electrical performance of the transistors.

It is desirable to provide technology for a semiconductor device with low contact resistance.

SUMMARY

The present disclosure relates to a semiconductor device and a method for manufacturing the same.

According to an embodiment of the present disclosure, a semiconductor device is provided. The semiconductor device includes a channel layer, a gate element on the channel layer, and source/drain elements at least partly embedded in the channel layer. The source/drain elements are on opposite sides of the gate element. The source/drain elements include a metal element and a lower silicide element between the metal element and the channel layer. The lower silicide element has a hydrogen content less than 2 at %.

According to an embodiment of the present disclosure, a semiconductor device is provided. The semiconductor device includes a channel layer, a gate element on the channel layer, and source/drain elements at least partly embedded in the channel layer. The source/drain elements are on opposite sides of the gate element. The source/drain elements include a metal element, an upper silicide element and a lower silicide element. The lower silicide element is between the metal element and the channel layer. The lower silicide element is below the upper silicide element and separated from the upper silicide element.

According to an embodiment of the present disclosure, a semiconductor device is provided. The semiconductor device includes a channel layer, a gate element on the channel layer, and source/drain elements at least partly embedded in the channel layer. The source/drain elements are on opposite sides of the gate element. The source/drain elements include a metal element and a lower silicide element between the metal element and the channel layer. The lower silicide element has a nitrogen content less than 5 at %.

According to an embodiment of the present disclosure, a method for manufacturing a semiconductor device is provided. The method includes: forming a channel layer on a substrate; forming a barrier layer on the channel layer; forming a gate element on the barrier layer; forming a hole through the barrier layer, wherein a bottom of the hole is below an upper surface of the channel layer; forming a source/drain element. The step of forming the source/drain element includes lining the hole with a silicon film having a hydrogen content less than 5 at %, and forming a first metal film and a second metal film on the silicon film. The first metal film and the second metal film include different materials.

The above and other embodiments of the disclosure will become better understood with regard to the following detailed description of the non-limiting embodiment(s). The following description is made with reference to the accompanying drawings.

DETAILED DESCRIPTION

The illustrations may not be necessarily drawn to scale, and there may be other embodiments of the present disclosure which are not specifically illustrated. Thus, the specification and the drawings are to be regard as an illustrative sense rather than a restrictive sense. Moreover, the descriptions disclosed in the embodiments of the disclosure such as detailed construction, manufacturing steps and material selections are for illustration only, not for limiting the scope of protection of the disclosure. The steps and elements in details of the embodiments could be modified or changed according to the actual needs of the practical applications. The disclosure is not limited to the descriptions of the embodiments. The illustration uses the same/similar symbols to indicate the same/similar elements.

FIG.1schematically illustrates a semiconductor device10according to an embodiment of the present disclosure. The semiconductor device10includes a substrate101, a transistor structure100disposed on the substrate101along a Z direction, and a buffer layer102between the substrate101and the transistor structure100. The Z direction may be, for example, a normal direction to an upper surface101uof the substrate101.

The transistor structure100includes a channel layer103, a barrier layer104, a gate element105, two source/drain elements106and a passivation layer107.

The channel layer103is on the buffer layer102. The gate element105is on the channel layer103. The barrier layer104is between the channel layer103and the gate element105. The gate element105may include a control layer112and a gate metal layer111on the control layer112. The passivation layer107may be on the channel layer103. The passivation layer107may cover an upper surface104uof the barrier layer104and the gate element105.

Two source/drain elements106are on opposite sides of the gate element105. The source/drain elements106are on the channel layer103. Specifically, part of the source/drain element106is above the passivation layer107; another part of the source/drain element106passes through the passivation layer107and is at least partly embedded in the channel layer103. In this embodiment, a lower surface106bof the source/drain element106is below an upper surface103uof the channel layer103.

The source/drain element106includes a metal element113, at least one upper silicide element114-1between the metal element113and the passivation layer107, and at least one lower silicide element114-2between the metal element113and the channel layer103. The lower silicide element114-2is separated from the upper silicide element114-1. The lower silicide element114-2is below the upper silicide element114-1. The upper silicide element114-1is above the passivation layer107. In this embodiment, the source/drain element106includes two upper silicide elements114-1and one lower silicide element114-2separated from each other. Two upper silicide elements114-1may be approximately at the same level. The metal element113has a sidewall113sbetween the upper silicide element114-1and the lower silicide element114-2. The sidewall113sof the metal element113may directly contact the passivation layer107.

The transistor structure100may further include a carrier channel103c(represented by lateral dashed lines inFIG.1). The carrier channel103cmay be formed near an interface between the channel layer103and the barrier layer104. The carrier channel103cmay be also known as two-dimensional electron gas (2-DEG). For example, the transistor structure100may be a high electron mobility transistor structure.

FIGS.2-4schematically illustrate a method for manufacturing a semiconductor device according to an embodiment of the present disclosure.

Referring toFIG.2, a substrate101is provided. The substrate101may be a semiconductor substrate, such as a doped or undoped silicon substrate. A buffer layer102, a channel layer103and a barrier layer104may be formed on the upper surface101uof the substrate101in sequence along the Z direction, for example, by a metal organic chemical vapor deposition (MOCVD) process or a molecular beam epitaxy (MBE) process. The buffer layer102may include AlN, AlGaN or GaN. For example, the buffer layer102may include undoped GaN or GaN that is not intentionally doped. The channel layer103may include AlN, GaN, InN, AlGaN, AlInN, GaInN or AlGaInN. For example, the channel layer103may include GaN. The barrier layer104may include AlN, GaN, InN, AlGaN, AlInN, GaInN or AlGaInN. For example, the barrier layer104may include AlGaN.

Then, a gate element105is formed on the upper surface104uof the barrier layer104. In an embodiment, the formation of the gate element105may include the following steps. A control layer112is formed on the upper surface104uof the barrier layer104by a metal organic chemical vapor deposition process or a molecular beam epitaxy process. A gate metal layer111is formed on an upper surface112uof the control layer112by a chemical vapor deposition (CVD) process or a physical vapor deposition (PVD) process. An etching process, such as a wet etching process or a dry etching process, is performed to the control layer112and the gate metal layer111so as to remove part of the control layer112and part of the gate metal layer111to form the gate element105shown inFIG.2and expose part of the upper surface104uof the barrier layer104. The control layer112may include GaN doped with p-type dopants. The gate metal layer111may include a conductive material, such as aluminum (Al), copper (Cu), nickel (Ni), platinum (Pt), palladium (Pd), Iridium (Ir), Molybdenum (Mo), gold (Au), titanium (Ti) or TiN.

After the formation of the gate element105, a passivation layer107is formed on the barrier layer104, for example, by a chemical vapor deposition process or a physical vapor deposition process. The passivation layer107may cover the exposed part of the upper surface104uof the barrier layer104and the gate element105. The passivation layer107may include SiN, SiO2, AlN, or Al2O3.

Two holes201are formed on opposite sides of the gate element105. In an embodiment, part of the channel layer103, part of the barrier layer104and part of the passivation layer107may be removed by a photo-etching process to form the holes201. The etching process may be performed downwardly along the Z direction. The etching process may be stopped as the etching process progresses beyond the upper surface103uof the channel layer103. The hole201may extend through the barrier layer104and the passivation layer107. A bottom201bof the hole201may be below the upper surface103uof the channel layer103. In an embodiment, a sidewall201sof the hole201may be inclined with respect to the Z direction. A width of an opening of the hole201may be greater than that of the bottom of the hole201.

Referring toFIGS.3-4, source/drain elements106are formed in the holes201. The formation of the source/drain element106may include the following steps. The hole201are lined with a silicon film321. A first metal film322and a second metal film323are formed on the silicon film321. In an embodiment, the silicon film321, the first metal film322and the second metal film323may be formed in the hole201in sequence, for example, by a chemical vapor deposition process or a physical vapor deposition process. The silicon film321may directly contact the channel layer103, the barrier layer104and the passivation layer107. A lower surface321bof the silicon film321may be below the upper surface103uof the channel layer103. The silicon film321may include a silicon-containing material with low hydrogen content, such as a silicon-containing material with a hydrogen content less than 5 at %. In an embodiment, the silicon film321includes amorphous silicon with a hydrogen content less than 5 at %. The first metal film322and the second metal film323may include different materials. The first metal film322may include metal, such as titanium, cobalt, nickel and tantalum. In an embodiment, the first metal film322may include titanium. The second metal film323may include metal, such as aluminum, copper, tungsten, titanium, nickel, molybdenum and tantalum. In an embodiment, the second metal film323may include aluminum or aluminum doped with copper. In an embodiment, the second metal film323may include aluminum or aluminum doped with copper and may be free of gold.

The formation of the source/drain element106may further include performing an annealing process to the structure ofFIG.3so as to form a metal element113, an upper silicide element114-1and a lower silicide element114-2from the silicon film321, the first metal film322and the second metal film323, as shown inFIG.4. Specifically, during the annealing process, the silicon film321, the first metal film322and the second metal film323react to form silicide, a portion of silicide moves upward, and another portion of silicide moves downward. The portion of silicide which moves upward can be defined as the upper silicide element114-1. The portion of silicide which moves downward can be defined as the lower silicide element114-2. The remainder of the second metal film323(or may be understood as the unreacted portion of the second metal film323) can be defined as the metal element113. After the annealing process, the upper silicide element114-1is on an upper surface107uof the passivation layer107. After the annealing process, the lower silicide element114-2is at the bottom201bof the hole201. A thickness T1of the lower silicide element114-2along the Z direction may be greater than a thickness T2of the barrier layer104along the Z direction. An upper surface114uof the lower silicide element114-2may be above an upper surface104uof the barrier layer104. The lower silicide element114-2may directly contact the channel layer103.

The upper silicide element114-1and the lower silicide element114-2may include the same material. The upper silicide element114-1and the lower silicide element114-2may include silicide with low hydrogen content, such as silicide with a hydrogen content less than 2 at %. In an embodiment, the upper silicide element114-1and the lower silicide element114-2may include titanium silicide (TiSi) and/or titanium aluminum silicide (TiAlSi) with a hydrogen content less than 2 at %. In an embodiment, the upper silicide element114-1and the lower silicide element114-2may include titanium silicide (TiSi) and/or titanium aluminum silicide (TiAlSi) with a hydrogen content less than 1.5 at %. In an embodiment, the upper silicide element114-1and the lower silicide element114-2may have a nitrogen content less than 5 at %. In an embodiment, the upper silicide element114-1and the lower silicide element114-2may include titanium silicide (TiSi) and/or titanium aluminum silicide (TiAlSi) with a hydrogen content less than 0.6 at %.

The second metal film323and the metal element113may include the same material, such as aluminum, copper, tungsten, titanium, nickel, molybdenum and tantalum. In an embodiment, the metal element113may include aluminum or aluminum doped with copper. In an embodiment, the metal element113may include aluminum or aluminum doped with copper and may be free of gold.

In an embodiment, a semiconductor device10ofFIG.1is provided through the method schematically illustrated inFIGS.2-4.

According to the above embodiments, the source/drain element of the transistor structure of the semiconductor device provided by the present disclosure include a silicide element with low hydrogen content or low nitrogen content, and the silicide element is between the metal element and the channel layer. With such configuration, the contact resistance at the junction of the source/drain element and the channel layer effectively reduced, and the electrical performance of the semiconductor device can be improved. Moreover, the silicide element with low hydrogen content or low nitrogen content can result in better Ohmic contact.