Low power bit switches and method for high-voltage input SAR ADC

A switched capacitor circuit, which may be an SAR ADC, includes a plurality of bit switching circuits (33) each including a high-voltage sampling switch circuit (18) having a first terminal (28) coupled to a first terminal of a corresponding capacitor (22) and a second terminal coupled to receive an analog input signal (VSIG). A third terminal of the sampling switch circuit is coupled to an intermediate conductor (19). Each switching circuit (33) also includes a low-voltage conversion switch circuit (30) coupled to the intermediate conductor (19) and a combinational logic circuit (12) applying low-voltage signals to the conversion switch circuit and a level-shifting circuit (16) that generates corresponding high-voltage signals (HV_SIG_DRV) which control coupling of the first terminal (28) to the analog input signal and the intermediate conductor.

BACKGROUND OF THE INVENTION

The present invention relates generally to reducing power in integrated circuits that include high-voltage switches, and more particularly to reducing power consumed in bit sampling switches in high-voltage SAR ADCs (successive approximation register analog-to-digital converters).

For example, in conventional high-voltage 16-bit SAR ADCs, each bit switching circuit includes three high-voltage switches, one for sampling a high-voltage analog input signal VSIG, one for switching the bottom plate of a corresponding CDAC (capacitor DAC) capacitor to a first reference voltage VREF, and one for switching the plate of a corresponding CDAC capacitor to a second reference voltage GND. The high power consumption is due to the high dynamic power associated with the level-shifting of various digital control signals during each switching event. Furthermore, the bit switches typically are very large, in order to achieve the low channel resistances required for fast signal settling.

“Prior Art”FIG. 1Ashows the basic part of a conventional 16-bit SAR ADC circuit, which is repeated for every capacitor of the CDAC array. The complete circuit includes 16 low-voltage (e.g., 5 volt) combinational logic circuits12which receive a sampling signal SMPL from a digital control circuit (e.g., circuit21inFIG. 2B), 16 signals BIT that are sequentially generated by SAR logic circuitry (e.g., SAR logic27inFIG. 2C) in response to the output of a SAR comparator25, and 16 “trim” signals e.g., (BIT_SAMP inFIG. 2A) that determine which of 16 CDAC capacitors are to be utilized for sampling the analog input signal VSIG. Each of the 16 combinational logic circuits12generates corresponding low-voltage drive signals SIG_DRV, REF_DRV, and GND_DRV which are applied to the inputs of three corresponding level shifter circuits, respectively, in each of 16 blocks14in order to generate the corresponding high corresponding voltage signals HV_SIG_DRV, HV_REF_DRV, and HV_GND_DRV, respectively.

Bit switching circuit17in each block14includes three high-voltage bit switching circuits, one for each bit of the SAR ADC. For convenience, each bit switching circuit is represented by a single pole, triple throw switch having its pole terminal coupled by conductor28to the bottom plate of a corresponding CDAC capacitor in a CDAC20. Each single pole, triple throw switch has one pole connected to high-voltage analog input signal VSIG, another pole connected to reference voltage VREF, and a third pole connected to the ground voltage GND (or VSS). The upper plate of each of the 16 CDAC capacitors in block20is connected by a conductor24to one input of a SAR comparator25, the output of which is connected to an input of the above mentioned SAR logic (not shown). The three level shifter circuits in each block14are powered by relatively high supply voltages HVDDand HVSS, which may be 15 volts and −15 volts, respectively. The foregoing conventional SAR ADC circuitry is included in the assignee's presently marketed ADS8556 product.

All of the VSIGsampling, VREFand GND switches are formed from high-voltage transistors because they share the same “pole node” with the high-voltage analog input signal VSIG, and consequently the digital control signals SIG_DRV, REF_DRV, and GND_DRV must be level-shifted to a high voltage range. Unfortunately, the level shifters consume a great deal of power.

The problem of high power consumption in bit switches of conventional high-voltage SAR ADCs sometimes has been dealt with by using a resistive divider circuit to attenuate the high-voltage analog input signal VSIGbefore it is sampled onto a selected CDAC bit capacitor (or capacitors) will, to avoid the use of high-voltage switches for sampling the high-voltage analog input signal VSIGduring sampling operation and switching between VREFand GND during successive approximation analog-to-digital conversion. This approach is shown in Prior ArtFIG. 1B, which is the same as FIG. 1 of U.S. Pat. No. 6,731,232 entitled “Programmable Input Range in SAR ADC” issued May 4, 2004 to Kearney. The resistive divider results in an undesirably low impedance input, and also results in high power consumption in circuitry required for driving the resistive divider. Another technique for dealing with the high power consumption has been to use a capacitive divider circuit to attenuate the high-voltage input signal between the capacitors of a separate sampling CDAC in series with the conversion CDAC involved in the successive approximation operation. The capacitive divider referred to is shown in Prior ArtFIG. 1C, which is the same asFIG. 6in the above mentioned Kearney patent. In Prior ArtFIG. 1C, the sampling switches used for sampling the high-voltage analog input signal onto the CDAC capacitors need to be high-voltage switches, but the VREFand GND switches used during the conversion operation can be low-voltage switches. However, this technique has the disadvantage of poor SNR (signal to noise ratio) due to the attenuation of the input signal caused by the additional sampling CDAC, as well as the disadvantage of requiring additional integrated circuit die area.

Thus, there is an unmet need for a high-voltage SAR ADC in which dynamic power consumption is substantially reduced compared to the dynamic power consumption in the closest prior art high-voltage SAR ADCs.

There also is an unmet need for a high-voltage SAR ADC having lower power consumption and requiring less integrated circuit chip area than the closest prior art high-voltage SAR ADCs.

There also is an unmet need for a high-voltage SAR ADC having reduced current spikes in the high-voltage supplies than is the case for the closest prior art high-voltage SAR ADCs.

There also is an unmet need for a high-voltage SAR ADC in which a high-voltage analog input signal can be coupled to the CDAC capacitors thereof with less signal distortion than in the closest prior art high-voltage SAR ADCs.

There also is an unmet need for a high-voltage SAR ADC having good signal-to-noise performance along with significantly lower dynamic power consumption compared to the closest prior art SAR ADCs.

SUMMARY OF THE INVENTION

It is an object of the invention to provide a high-voltage SAR ADC in which dynamic power consumption is substantially reduced compared to the dynamic power consumption in the closest prior art high-voltage SAR ADCs.

It is another object of the invention to provide a high-voltage SAR ADC having lower power consumption and requiring less integrated circuit chip area than the closest prior art high-voltage SAR ADCs.

It is another object of the invention to provide a high-voltage SAR ADC having reduced current spikes in the high-voltage supplies than is the case for the closest prior art high-voltage SAR ADCs.

It is another object of the invention to provide a high-voltage SAR ADC in which a high-voltage analog input signal can be coupled to the CDAC capacitors thereof with less signal distortion at lower power consumption levels than in the closest prior art high-voltage SAR ADCs.

It is another object of the invention to provide a high-voltage SAR ADC having good signal-to-noise performance along with significantly lower dynamic power consumption compared to the closest prior art SAR ADCs.

It is another object of the invention to provide a high-voltage SAR ADC in which gain error in the ADC transfer function is reduced without substantially increasing dynamic power consumption.

It is another object of the invention to provide a high-voltage SAR ADC in which the faster conversion cycle times are achieved.

Briefly described, and in accordance with one embodiment, the present invention provides a switched capacitor circuit, which may be a SAR ADC, that includes a plurality of bit switching circuits (33) each including a high-voltage sampling switch circuit (18) having a first terminal (28) coupled to a first terminal of a corresponding capacitor (22) and a second terminal coupled to receive an analog input signal (VSIG). A third terminal of the sampling switch circuit is coupled to an intermediate conductor (19). Each switching circuit (33) also includes a low-voltage conversion switch circuit (30) coupled to the intermediate conductor (19) and a combinational logic circuit (12) applying low-voltage signals to the conversion switch circuit and a level-shifting circuit (16) that generates corresponding high-voltage signals (HV_SIG_DRV) which control coupling of the first terminal (28) to the analog input signal and the intermediate conductor.

In one embodiment, the invention provides a high-voltage switched capacitor circuit (10) including a plurality of capacitors (22) each having a first terminal, a plurality of bit switching circuits (33) each including a high-voltage sampling switch circuit (18) having a first terminal (28) coupled to a second terminal of a corresponding capacitor (22) and a second terminal coupled to receive a high-voltage analog input signal (VSIG), and a third terminal coupled to an intermediate conductor (19). Each bit switching circuits (33) also includes a low-voltage conversion switch circuit (30) including a first terminal coupled to the intermediate conductor (19), a second terminal coupled to receive a first reference voltage (VREF), and a third terminal coupled to receive a second reference voltage (GND). A plurality of low-voltage combinational logic circuits (12) generate a plurality of low-voltage first signals (SIG_DRV), respectively, in response to a sampling level of a mode control signal (SMPL). Each low-voltage combinational logic circuit (12) also generates low-voltage second (REF_DRV) and third (GND_DRV) signals according to a corresponding one of a plurality of bit signals (BIT<1:16>), respectively, during a predetermined level of the mode control signal (SMPL). A plurality of level-shifting circuits (16) each has an input coupled to receive a corresponding low-voltage first signal (SIG_DRV). Each level-shifting circuit (16) generates a corresponding high-voltage second signal (HV_SIG_DRV) to control coupling of the first terminal (28) of a corresponding high-voltage sampling switch circuit (18) to the high-voltage analog input signal (VSIG) during the sampling level and to the intermediate conductor (19) during the pre-determined level.

In a described embodiment, the high-voltage switched capacitor circuit is a high-voltage SAR ADC, the capacitors are CDAC capacitors (22or C1p, C2p. . . C16p) each having a first terminal coupled to a first input (−) of a comparator (25), and the predetermined level is a conversion level, wherein the high-voltage SAR ADC includes a SAR logic circuit (27) having an input coupled to an output of the comparator (25), and performs a successive approximation procedure in response to the output of the comparator (25) to successively generate the corresponding bit signals (BIT<1:16>) to provide a digital representation of the high-voltage analog input signal (VSIG).

In a described embodiment, each level-shifting circuit (16) includes a low-voltage first latch circuit (16A) having an input coupled to a corresponding low-voltage first signal (SIG_DRV) and also includes a high-voltage second latch circuit (16B) having an input coupled to an output of the low-voltage first latch circuit (16A), wherein the high-voltage second latch circuit (16B) produces the high-voltage second signal (HV_SIG_DRV=HV_OUTp) and a high-voltage third signal (HV_OUTn) which is a logical complement of the high-voltage second signal (HV_SIG_DRV=HV_OUTp). The high-voltage second and third output signals are coupled to control a corresponding high-voltage sampling switch circuit (18).

In a described embodiment, each high-voltage sampling switch circuit (18) includes a high-voltage boosted switch circuit (18A inFIG. 5) including a boost transistor (54) and a boost capacitor (55) coupled between a gate and a first electrode of the boost transistor (54), wherein the first electrode of the boost transistor (54) is coupled to the second terminal (VSIG) of that high-voltage sampling switch circuit (18) to receive the high-voltage analog input signal (VSIG), and a second electrode of the boost transistor (54) is coupled to the first terminal (28) of that high-voltage sampling switch circuit (18).

In one embodiment, each high-voltage sampling switch circuit (18) also includes a high voltage transmission gate (18B) controlled by a corresponding level-shifting circuit (16) coupled in parallel with the high-voltage boosted switch circuit (18A) in that high-voltage sampling switch circuit (18). A precharging circuit (58) precharges the boost capacitor (55).

In one embodiment, the precharging circuitry (58) produces a boosted output voltage equal to a high-magnitude lower reference voltage level (HVSS) plus a boost voltage (Vboost), wherein the boost transistor (54) is an N-channel transistor. The high-voltage boosted switch circuit (18A) includes a first N-channel transistor (60) having a drain coupled to receive the boosted output voltage (HVSS+Vboost) and a source coupled to both a first terminal (61) of the boost capacitor (55) and a first terminal of a CMOS (complementary metal oxide semiconductor) transmission gate (64,65), a second N-channel transistor (63) having a source coupled to the high-magnitude lower voltage reference level (HVSS) and a drain (62) coupled to a second terminal of the boost capacitor (55) and to a source of a third N-channel transistor (66) having a drain coupled to the high-voltage analog input signal (VSIG) and a gate coupled to a second terminal of the CMOS transmission gate (64,65) and to a gate of the boost transistor (54), a fourth N-channel transistor (67) having a source coupled to the high-magnitude lower reference voltage level (HVSS) and a drain coupled to the gate of the boost transistor (54). The gate of the first N-channel transistor (60), a gate of the second N-channel transistor (63), a gate of the fourth N-channel transistor (67), and a first control terminal of the CMOS transmission gate (64,65) are coupled to receive a logical complement of the high-voltage second signal (HV_SIG_DRV), and a second control terminal of the CMOS transmission gate (64,65) is coupled to receive the high-voltage second signal (HV_SIG_DRV).

In a described embodiment, a digital controller (21) generates the mode control signal (SMPL) and a plurality of ADC gain control signals (BIT_SAMP<1:16>) to determine which of the plurality of CDAC capacitors (C1p, C2p. . . C16p) are to be utilized for sampling of the analog input signal (VSIG), wherein the plurality of low-voltage combinational logic circuits (12) generate the plurality of low-voltage first signals (SIG_DRV), respectively, according to predetermined levels of the ADC gain control signals (BIT_SAMP<1:16>).

In a described embodiment, the SAR ADC is a 16-bit SAR ADC, wherein the plurality of CDAC capacitors includes 16 CDAC capacitors (C1p, C2p. . . C16p) in a first CDAC (10p), the first CDAC (10p) including 16 of the bit switching circuits (33), 16 of the low-voltage combinational logic circuits (12), and 16 of the level shifting circuits (16). In one embodiment, the high-voltage SAR ADC also includes a second CDAC (10n) that is essentially similar to the first CDAC (10p), wherein the CDAC capacitors in the second CDAC (10n) each have a first terminal coupled to a second input (+) of the comparator (25).

In one embodiment, each low-voltage combinational logic circuit (12) includes a first inverter (40) having an input coupled to receive a corresponding bit signal (BIT<1:16>) and an output coupled to a first input of a first ORing circuit (41). The second inverter (43) has an input coupled to an output of the first ORing circuit (41) and an output coupled to a first input of a second ORing circuit (44), a third inverter (45) has an input coupled to the output of the first ORing circuit (41) and an output coupled to a first input of a third ORing circuit (46), and an ANDing circuit (42) has an output coupled to a second input of the second ORing circuit (44) and to a second input of the third ORing circuit (46). The mode control signal (SMPL) signal is applied to a second input of the first ORing circuit (41) and a first input of the ANDing circuit (42). A corresponding ADC gain control signal (BIT_SAMP<1:16>) is coupled to a second input of the ANDing circuit (42). The low-voltage first (SIG_DRV), second (REF_DRV), and third (GND_DRV) signals are produced at the outputs of the ANDing circuit (42), the third ORing circuit (46), and the second ORing circuit (44), respectively.

In one embodiment, a hold switch (38) is coupled between the second reference voltage (GND) and the first (−) input of the comparator (25), and the hold switch (30) is controlled in response to a hold signal (HOLD_CTRL) signal generated by the digital controller (21).

In one embodiment, each low-voltage combinational logic circuit (12) operates to cause a corresponding low-voltage conversion switch circuit (30) to couple a corresponding intermediate conductor (19) to one of the second (VREF) and third (GND) terminals of that corresponding low-voltage sampling switch circuit (30) during the sampling level of the mode control signal (SMPL) to protect the low-voltage conversion switch circuit (30) from high voltages on the corresponding intermediate conductor (19).

In one embodiment, the invention provides a method for providing reduced power consumption in a high-voltage SAR ADC including a plurality of CDAC capacitors (22or C1p, C2p. . . C16p) each having a first terminal coupled to a first input (−) of a comparator (25), a plurality of bit switching circuits (33) each including a high-voltage sampling switch circuit (18) having a first terminal (28) coupled to a second terminal of a corresponding CDAC capacitor (22) and a second terminal coupled to receive a high-voltage analog input signal (VSIG), a plurality of low-voltage combinational logic circuits (12) for generating a plurality of low-voltage first signals (SIG_DRV), respectively, in response to a sampling level of a mode control signal (SMPL), each low-voltage combinational logic circuit (12) also generating corresponding low-voltage second (REF_DRV) and third (GND_DRV) signals according to a corresponding bit signal (BIT<1:16>) during a conversion level of the mode control signal (SMPL), and a plurality of level-shifting circuits (16) each having an input coupled to receive a corresponding low-voltage first signal (SIG_DRV), each level-shifting circuit (16) generating a corresponding high-voltage first signal (HV_SIG_DRV) to control coupling of the first terminal (28) of a corresponding high-voltage sampling switch circuit (18) to the second terminal (VSIG) during the sampling level. The method includesproviding a low-voltage conversion switch circuit (30) and an intermediate conductor (19) in each bit switching circuit (33), wherein a first terminal of the low-voltage conversion switch circuit (30) is connected to the intermediate conductor (19);coupling the first terminal (28) of one of the high-voltage sampling switch circuits (18) to the second terminal (VSIG) of that high-voltage sampling circuit (18) in response to the corresponding high voltage second signal (HV_SIG_DRV) during the sampling level; andcoupling a third terminal of that high-voltage sampling switch circuit (18) to the intermediate conductor (19) in that bit switching circuit (33) during the conversion level, and, during the conversion level, coupling a second terminal of that low-voltage conversion switch circuit (30) to receive a first reference voltage (VREF) in response to the corresponding low-voltage second signal (REF_DRV) if the corresponding bit signal (BIT<1:16>) is at a first level, and coupling a third terminal of that low-voltage conversion switch circuit (30) to receive a second reference voltage (GND) in response to the corresponding low-voltage third signal (GND_DRV) if the corresponding bit signal (BIT<1:16>) is at a second level.

In one embodiment, the method includes operating a SAR logic circuit (27) having an input coupled to an output of the comparator (25) to perform a successive approximation procedure in response to the output of the comparator (25) to successively generate the corresponding bit signals (BIT<1:16>) to provide a digital representation of the high-voltage analog input signal (VSIG).

In one embodiment, the method includes operating each low-voltage combinational logic circuit (12) to cause a corresponding low-voltage conversion switch circuit (30) to couple a corresponding intermediate conductor (19) to one of the second (VREF) and third (GND) terminals of that corresponding low-voltage sampling switch circuit (30) during the sampling level of the mode control signal (SMPL) to protect the low-voltage conversion switch circuit (30) from high voltages on the corresponding intermediate conductor (19).

In one embodiment, the method includes operating each low-voltage combinational logic circuit (12) to cause the corresponding low-voltage conversion switch circuit (30) to couple the corresponding intermediate conductor (19) to the third terminal (GND) of that corresponding low-voltage sampling switch circuit (30) during the sampling level of the mode control signal (SMPL).

In one embodiment, the method includes providing in each bit switching circuit (33) a high-voltage boosted switch circuit (18A inFIG. 5) including a boost transistor (54) and a boost capacitor (55) coupled between a gate and a first electrode of the boost transistor (54) in each high-voltage sampling switch circuit (18), the first electrode of the boost transistor (54) being coupled to the second terminal (VSIG) of that high-voltage sampling switch circuit (18) to receive the high-voltage analog input signal (VSIG), a second electrode of the boost transistor (54) being coupled to the first terminal (28) of that high-voltage sampling switch circuit (18), the method including precharging the boost capacitor (55) to produce a low impedance of the boost transistor (54).

In one embodiment, the invention provides a high-voltage SAR ADC including a plurality of CDAC capacitors (22or C1p, C2p. . . C16p) each having a first terminal coupled to a first input (−) of a comparator (25); a plurality of bit switching circuits (33) each including a high-voltage sampling switch circuit (18) having a first terminal (28) coupled to a second terminal of a corresponding CDAC capacitor (22) and a second terminal coupled to receive a high-voltage analog input signal (VSIG); a plurality of low-voltage combinational logic circuits (12) for generating a plurality of low-voltage first signals (SIG_DRV), respectively, in response to a sampling level of a mode control signal (SMPL), each low-voltage combinational logic circuit (12) also generating corresponding low-voltage second (REF_DRV) and third (GND_DRV) signals according to a corresponding bit signal (BIT<1:16>) during a conversion level of the mode control signal (SMPL); a plurality of level-shifting circuits (16) each having an input coupled to receive a corresponding low-voltage first signal (SIG_DRV), each level-shifting circuit (16) generating a corresponding high-voltage first signal (HV_SIG_DRV) to control coupling of the first terminal (28) of a corresponding high-voltage sampling switch circuit (18) to the second terminal (VSIG) during the sampling level; a low-voltage conversion switch circuit (30) and an intermediate conductor (19) in each bit switching circuit (33), wherein a first terminal of the low-voltage conversion switch circuit (30) is connected to the intermediate conductor (19); means (12,16) for coupling the first terminal (28) of one of the high-voltage sampling switch circuits (18) to the second terminal (VSIG) of that high-voltage sampling circuit (18) in response to the corresponding high voltage second signal (HV_SIG_DRV) during the sampling level; and means (12,16,) for coupling a third terminal of that high-voltage sampling switch circuit (18) to the intermediate conductor (19) in that bit switching circuit (33) during the conversion level, and, during the conversion level, coupling a second terminal of that low-voltage conversion switch circuit (30) to receive a first reference voltage (VREF) in response to the corresponding low-voltage second signal (REF_DRV) if the corresponding bit signal (BIT<1:16>) is at a first level, and coupling a third terminal of that low-voltage conversion switch circuit (30) to receive a second reference voltage (GND) in response to the corresponding low-voltage third signal (GND_DRV) if the corresponding bit signal (BIT<1:16>) is at a second level.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

A detailed analysis of the power consumption of the 16-bit SAR ADC in Prior ArtFIG. 1Awas performed in an effort to substantially reduce the power consumption. The packet of charge consumed by each of the three level shifters every time it changes state results in a transient current peak in both the HVDDand HVSShigh-voltage power supplies every time each level shifter changes state. It was determined that an excessively large amount of the total power consumption of the 16-bit SAR ADC is due to dynamic power consumed by the switching of the three level shifters to provide the three high-voltage switch control signals HV_SIG_DRV, HV_REF_DRV, and HV_GND_DRV.

Referring now toFIG. 2A, to overcome the foregoing high dynamic power consumption problem of Prior ArtFIG. 1A, a 16-bit high-voltage SAR ADC10is provided which includes 16 “low-voltage” (e.g., analog supply voltage AVDD=5 volts) combinational logic circuits12that all receive an input sampling control signal SMPL from a digital control circuit (FIG. 2B), 16 bit data signals BIT generated by SAR logic27in response to the output of SAR comparator25, and 16 “bit sampling” signals BIT_SAMP<1:16> that determine which of the 16 corresponding binarily weighted CDAC capacitors represented by capacitor22are utilized for sampling high-voltage analog input signal VSIG. SAR logic27executes a well-known SAR algorithm for bit-by-bit testing of the output voltage of SAR comparator25to determine whether the present SAR ADC bit being generated should be a “1” or a “0”.

Each of the 16 combinational logic circuits12generates corresponding low-voltage drive signals SIG_DRV, REF_DRV, and GND_DRV. Each of low-voltage drive signals SIG_DRV is applied to the input of a single corresponding one of 16 level shifter circuits16in block15. Each level shifter circuit16generates a corresponding high-voltage sampling switch drive signal HV_SIG_DRV.

Bit switching circuitry33includes 16 bit switching circuits, one for each of the 16 bits of SAR ADC10. Each of the 16 bit switching circuits in block33includes a high-voltage sampling switch circuit18(hereinafter referred to simply as “sampling switch”18) represented by a high-voltage single pole, double throw switch having its pole terminal coupled by a corresponding conductor28to the bottom plate of a corresponding one of the 16 CDAC capacitors22in CDAC20. The pole terminal of each of the 16 high-voltage sampling switches18is controlled by a corresponding high-voltage signal HV_SIG_DRV. Bit switching circuitry33also includes 16 low-voltage single pole, double throw conversion switch circuits30(hereinafter, “conversion switches”30). Each of the 16 high-voltage sampling switches18has one terminal connected to a “high-voltage” analog input signal VSIGand another terminal connected by a corresponding intermediate conductor19to the pole terminal of a corresponding one of 16 low-voltage conversion switches30. Each of the 16 low-voltage conversion switches30also has one terminal connected to VREFand another terminal connected to GND.

The pole terminal28of each of the 16 high-voltage sampling switches18is controlled so as to connect that pole terminal28to VSIGin response to a HIGH level of a corresponding high-voltage HV_SIG_DRV drive signal and to connect the pole terminal28of that sampling switch18to the corresponding intermediate conductor19in response to a LOW level of that corresponding high-voltage HV_SIG_DRV drive signal. The pole terminal of each of the 16 conversion switches30is controlled so as to connect intermediate conductor19to VREFin response to a HIGH level of a corresponding low-voltage REF_DRV drive signal. The pole terminal of each of the 16 low-voltage conversion switches30also is controlled so as to connect the corresponding intermediate conductor19to GND in response to a HIGH level of a corresponding low-voltage GND_DRV drive signal.

The upper plate of each of the 16 capacitors22of a “pDAC” in block20is connected by a single conductor24to the (−) input of SAR comparator25, the output of which is connected to an input of SAR logic27. SAR logic27sequentially generates a decision bit on every conversion clock (CLK) cycle and thereby generates the 16 above mentioned bit signals BIT<1:16> (FIG. 2B) in response to “sampled-VSIG” voltage comparisons made by comparator25. The (+) input of SAR comparator25is connected to a low-voltage implementation of a “nDAC” in block31that is essentially similar to the “pDAC” in block20. The circuitry in block15is partly powered by “high” supply voltages HVDDand HVSS, which may be 15 volts and −15 volts, respectively, and also is partly powered by “low” supply voltages AVDDand AVSS, which may be 5 volts and zero (GND) volts, respectively.

FIG. 2Bshows more details of 16-bit SAR ADC10inFIG. 2A. InFIG. 2B, a digital control circuit21generates sample/convert control signal SMPL and the 16 control signals BIT SAMP<1:16>. SAR ADC10also includes a first CDAC10p(which is referred to as a “pDAC” because its output24pis connected to the negative (−) input of SAR comparator25and the input signal VSIGis inverted on the top plate conductor24p, so the final state of the capacitors in pDAC10pis equal to the final digital output produced by SAR ADC10). First CDAC10pincludes 16 binarily weighted CDAC capacitors C1p, C2p. . . C16pwhich correspond to the 16 CDAC capacitors22inFIG. 2A. Capacitors C1p, C2p. . . C16peach have an upper plate connected to conductor24p. First CDAC10palso includes 16 bit switching circuits33-1p,33-2p. . .33-16p, which are collectively referred to as “bit switching circuitry33”. Bit switching circuitry33includes bit switching circuitry33ofFIG. 2Aand, for convenience of illustration, also includes level shifter circuits16and combinational logic12ofFIG. 2A, as shown inFIG. 2C.

The lower plates of CDAC capacitors C1p, C2p. . . C16pinFIG. 2Bare connected by 16 corresponding conductors28-1p,28-2p. . .28-16pto corresponding pole terminals of the sampling switches18in the 16 bit switching circuits33-1p,33-2p. . .33-16p, respectively. An implementation of each of bit switching circuits33-1p,33-2p. . .33-16pis represented by bit switching circuit33shown inFIG. 2C.

Referring now toFIG. 2C, each bit switching circuit33includes a low-voltage combinational logic circuit12which receives the sample/convert signal SMPL, one of the 16 signals BIT<1:16>, and one of the 16 signals BIT_SAMP<1:16> indicated inFIG. 2B. (An implementation of combinational logic circuit12is shown in subsequently describedFIG. 3.) Each low-voltage combinational logic circuit12generates a drive signal SIG_DRV which is applied to the input of a high-voltage level shifter circuit16. (An implementation of level shifter circuit16is shown in subsequently describedFIG. 4.) Each level shifter circuit16generates a high-voltage output signal HV_SIG_DRV that is applied to control the corresponding high-voltage sampling switch18having its pole terminal connected by the corresponding conductor28(i.e., the corresponding one of conductors28-1p,2p. . .16pinFIG. 2B) to the lower plate of a corresponding CDAC capacitor22(i.e., a corresponding one of capacitors C1p, C2p. . . C16pinFIG. 2B).

During the sampling mode, the bottom plate of the corresponding CDAC capacitor22inFIG. 2C(i.e., the corresponding one of capacitors C1p, C2p. . . C16pinFIG. 2B) is connected to VSIGby the ON switch18, and conversion switch30is turned OFF. Intermediate node19is connected to GND by turning ON the GND switch. Since intermediate node19is connected to GND, the VREFand GND transistors can be low-voltage transistors.

Each combinational logic circuit12also generates corresponding low-voltage drive signals REF_DRV and GND_DRV, which control a corresponding conversion switch30by selectively coupling its pole terminal to VREFin response to the corresponding signal REF_DRV and by selectively coupling the pole terminal of that conversion switch30to GND in response to GND_DRV. The pole terminal of the corresponding low-voltage conversion switch30is connected by the corresponding intermediate conductor19to one terminal of high-voltage sampling switch18. The other terminal of sampling switch18is connected to receive the high-voltage analog input voltage VSIG, which is equal to VINPif bit switching circuit33is included in pDAC10pinFIG. 2B(and is equal to VINNif bit switching circuit33is included in nDAC10ninFIG. 2B). An implementation of high-voltage sampling switch18is indicated in subsequently describedFIGS. 5,5A and5B. (Of course, each of the illustrated single-pole, double throw switches shown inFIGS. 2B and 2Ccan be readily implemented by means of two single-pole, single throw switches having a common pole terminal.)

Depending on the resulting decision for a particular bit of SAR ADC10, the VREFswitching transistor or the GND switching transistor may be turned ON. Since the VREFand GND transistors are low-voltage transistors, the digital control signals REF_DRV and GND_DRV can be low-voltage signals, so no level shifter circuits are required to generate them.

Referring to bothFIGS. 2B and 2C, the 16 sample/convert signals BIT_SAMP<1:16> are connected to the BIT_SAMP inputs of the combinational logic circuit12of each of bit-switching circuits33-1p,33-2p. . .33-16p, respectively. The sample/convert signal SMPL is connected to the SMPL inputs of the combinational logic circuit12of each of bit-switching circuits33-1p,33-2p. . .33-16p. The 16 signals BITP<1:16> produced by SAR logic circuit27are connected to the BIT inputs of the combinational logic circuit12of each of bit switching circuits33-1p,33-2p. . .33-16p, respectively. The VSIG, VREF, and GND inputs of each of bit-switching circuits33-1p,33-2p. . .33-16pin CDAC10pare connected to VINP, VREF, and GND, respectively.

SAR ADC10includes a low-voltage second CDAC10n(which is referred to as a “nDAC” because its output24nis connected to the positive (+) input of SAR comparator25. Second CDAC10nincludes16binarily weighted CDAC capacitors C1n, C2n. . . C16neach having an “upper” plate connected to conductor24n. The “lower” plates of the 16 CDAC capacitors C1n, C2n. . . C16nare connected by 16 corresponding conductors28-1n,28-2n. . .28-16nto corresponding pole terminals of sampling switches18in the 16 bit switching circuits33-1n,33-2n. . .33-16n, respectively. Bit switching circuits33-1n,33-2n. . .33-16ncan be the same as bit switching circuits33-1p,33-2p. . .33-16p.

The 16 sample/convert signals BIT_SAMP<1:16> are connected to the BIT_SAMP inputs of the combinational logic circuit12of each of bit-switching circuits33-1n,33-2n. . .33-16n. Sampling signal SMPL is connected to the SMPL inputs of combinational logic circuit12of each of bit-switching circuits33-1n,33-2n. . .33-16n. The 16 signals BITN<1:16> signals produced by SAR logic circuit27are connected to the BIT inputs of the combinational logic circuits12of bit-switching circuits33-1n,33-2n. . .33-16n, respectively. The VSIG, VREF, and GND inputs of each of bit-switching circuits33-1n,33-2n. . .33-16nin CDAC10nare connected to VINN, VREF, and GND, respectively.

Digital control circuit21also generates a sample/hold signal HOLD_CTRL which is applied to control two sample/hold switches37and38. One terminal of each of sample/hold switches37and38is connected to GND. The other terminal of sample/hold switch38is connected by conductor24pto the (−) input of comparator25, and the other terminal of sample/hold switch37is connected by conductor24nto the (+) input of comparator25. The HOLD_CTRL signal is almost the same as the SMPL signal except for some digital timing differences. The signal HOLD_CTRL is HIGH during the sampling mode when switches37and38are turned ON. This connects the two “top plate” conductors24pand24nto GND, and the bottom plates28-1p,2p. . .16pand28-1n,2n. . .16nof the sampling capacitors to the appropriate high-voltage analog input signal VSIG(VSIGPor VSIGN) during this time. That is, all of the CDAC capacitors of pDAC10pare connected to VSIGP, and all of the CDAC capacitors of nDAC10nare connected to VSIGN(which is very close to GND). Consequently, a charge corresponding to the appropriate input voltage VSIGis stored in each CDAC. During the conversion mode, the HOLD_CTRL signal toggles and turns OFF switches37and38so that the top plate conductors can remain electrically floating during the conversion process.

FIG. 3shows one implementation of combinational logic circuit12ofFIG. 2C, wherein combinational logic circuit12includes an inverter40having its input coupled by conductor29to receive a corresponding one of bit signals BITP<1:16> generated by SAR logic27. For the case in which combinational logic circuit12is included in pDAC10p, conductor29is one of conductors29pinFIG. 2B, and for the case in which combinational logic circuit12is included in nDAC10n, conductor29is one of conductors29ninFIG. 2B. The output of inverter40is connected to one input of NOR gate41. The other input of NOR gate41is connected to receive sample/convert signal SMPL, which is also coupled to one input of two-input AND gate42. The other input of AND gate42is coupled to receive a corresponding one of the 16 ADC gain control signals BIT_SAMP<1:16> produced by digital control circuit21. (The gain of SAR ADC10depends on the number of CDAC capacitors being used for sampling analog input signal VSIG.) The output of NOR gate41is connected to the inputs of inverters43and45. The output of inverter43is connected to one input of OR gate44. The output of AND gate42is connected to the other input of OR gate44and to one input of NOR gate46. The other input of NOR gate46is connected to the output of inverter45. AND gate42generates the low-voltage drive signal SIG_DRV. NOR gate46generates the low-voltage drive signal REF_DRV, and OR gate44generates the low-voltage drive signal GND_DRV.

By way of definition, the term “ORing gate” as used herein is intended to encompass either an OR gate or a NOR gate, and the term “ANDing gate” used herein is intended to encompass either an AND gate or a NAND gate.

Sample/convert signal SMPL indicates whether SAR ADC10is to be in its VSIGsampling mode or its analog-to-digital conversion mode. Specifically, SMPL is at a logic HIGH level when the SAR ADC10is in its VSIGsampling mode and is at a logic LOW level when SAR ADC10is in its conversion mode. SMPL goes to a HIGH level when one conversion operation ends, and remains HIGH until a falling edge of an earlier external user-provided “start conversion” signal CONVST (not shown) initiates another conversion. The 16 bit signals BITP<1:16> and the 16 bit signals BITN<1:16> generated by SAR logic27are the results of bit decisions sequentially made by SAR logic27in response to the output of SAR comparator25during the successive approximation procedure performed by SAR logic27.

The 16 ADC gain control signals BIT_SAMP<1:16> received by the 16 bit switching circuits33from digital control circuit21determine, respectively, whether or not each particular CDAC bit capacitor is to be used for sampling analog input signal VSIG. ADC gain control signal BIT_SAMP is at a logic HIGH level if the corresponding CDAC capacitor22(i.e., the corresponding one of CDAC capacitors Cp1, Cp2. . . Cp16inFIG. 2B) is used to sample the analog input signal VSIG, and is at a logic LOW level if the corresponding CDAC capacitor22is not being used to sample the analog input signal VSIG. (This technique is disclosed in U.S. Pat. No. 6,922,165 entitled “Method and Circuit for Gain and/or Offset Correction in a Capacitor Digital-to-Analog Converter” issued Jul. 26, 2005 to present inventor Robert Seymour.)

The low-voltage drive signal SIG_DRV generated by each combinational logic circuit12drives the corresponding level shifter16, which in turn drives the corresponding high-voltage sampling switch18. High-voltage sampling switch18is turned ON in response to SIG_DRV being at a logic HIGH level. If the ADC gain control signal BIT_SAMP for a particular bit of SAR ADC10is at a LOW logic level, then the corresponding CDAC capacitor22is not used to sample the input signal VSIG, so in that case SIG_DRV stays at a LOW level permanently. However, if that ADC gain control signal BIT_SAMP is at a HIGH level, then the corresponding signal SIG_DRV in effect “follows” sample/convert signal SMPL. The low-voltage drive signal REF_DRV generated by each combinational logic circuit12drives the corresponding low-voltage VREFswitch, which is ON when REF_DRV is at a HIGH level. REF_DRV is always at a LOW level during a VSIGsampling operation.

During a conversion operation, REF_DRV goes HIGH if the corresponding signal BIT is HIGH, and vice-versa. The low-voltage drive signal GND_DRV generated by each combinational logic circuit12drives the low-voltage GND switch, which is turned ON when GND_DRV is at a HIGH level. During conversion operation, drive signal GND_DRV goes to a HIGH level when BIT is at a LOW level, and goes to a LOW level when BIT is at a HIGH level. Irrespective of whether the BIT_SAMP signal is HIGH or LOW, GND_DRV may be HIGH during sampling operation so as to connect intermediate conductor19to GND in order to protect the low-voltage transistors in conversion switch30from high voltages on intermediate conductor19.

FIG. 4shows one way each of the 16 level shifters16can be implemented. InFIG. 4, level shifter16includes a non-inverting buffer48and an inverter49each having its input connected to receive a corresponding low-voltage drive signal SIG_DRV. The output of buffer48is connected to the gate of a P-channel transistor MP25having its source connected to the low-voltage supply AVDDand its drain connected by conductor50to the drain of an N-channel transistor MN3, the gate of an N-channel transistor MN2, and the gate of an N-channel transistor MN4. Each of transistors MN3, MN2, and MN4has its source connected to the high-voltage supply HVSS. The output of inverter49is connected to the gate of a P-channel transistor MP24having its source connected to AVDDand its drain connected by conductor51to the gate of transistor MN3, the drain of transistor MN2and the gate of an N-channel transistor MN5. The source of transistor MN5is connected to HVSSand its drain is connected by conductor52to the drain of a P-channel transistor MP14and to the gate of a P-channel transistor MP2. The sources of transistors MP14and MP2are connected to high-voltage supply HVDD. The gate of transistor MP14is connected by conductor53to the drain of transistor MN4and the drain of transistor MP2.

Transistors MP25, MP24, MN3, and MN2form a first latch16A, and transistors MP14, MP2, MN5, and MN4form a second latch16B. A high-voltage output signal HV_OUTp=HV_SIG_DRV is produced on conductor53of the second latch, and a complementary high-voltage output signal HV_OUTn is produced on conductor52of the second latch. High-voltage output signal HV_OUTp is basically a level-shifted, high-voltage version of SIG_DRV inFIGS. 2A-C.

First latch circuit16A operates to latch the logic LOW level of the low-voltage input signal SIG_DRV to HVSSvolts and the second stage16B operates to latch the logic HIGH level to HVDDvolts. When SIG_DRV is at a HIGH level, i.e. AVDD, then high-voltage output signal HV_OUTp=HV_SIG_DRV is at a “high-magnitude” HIGH level, i.e. HVDDvolts and HV_OUTn is at a “high-magnitude” LOW level, i.e. HVSSvolts. Similarly, when SIG_DRV is at a LOW level, i.e. AVSSvolts, output signal HV_OUTp is at a LOW level (i.e. HVSSvolts) and HV_OUTn is at a HIGH level (i.e. HVDDvolts). More specifically, when SIG_DRV is at a HIGH level, the gate of transistor MP24is pulled LOW, so the gate of transistor MN5goes to a HIGH level, i.e. AVDDvolts. This turns on transistor MN5, causing it to pull down its drain voltage to HVSS. This makes HV_OUTn equal to HVSS, i.e. a logic LOW level. Since, HV_OUTn is at a LOW level equal to HVSS, transistor MP2is turned ON, causing it to pull HV_OUTp=HV_SIG_DRV to a HIGH level, i.e. to HVDD. The reverse happens when SIG_DRV is at LOW level.

Thus, the two outputs of level shifter16are complementary, out-of-phase high-voltage signals that swing between the upper high-voltage supply level HVDDand the lower high-voltage supply level HVSS. In one implementation of sampling switch18, both HV_OUTp and HV_OUTn are used to control the connections of the pole terminal of sampling switch18to both VSIGand intermediate conductor19.

FIG. 5shows a generalized implementation of a 16 bit sampling switch18. A high-voltage, capacitively boosted N-channel transistor18A is connected in parallel with a transmission gate18B. Sampling switch18includes an N-channel transistor54having its source connected to conductor23so as to receive high-voltage analog input signal VSIG. A boost capacitor55is coupled between the gate and source of transistor54. Transmission gate18B includes a first switch56and a second switch57coupled in parallel between conductor23and a conductor39. Conductor39is connected to one terminal of a resistor68having its other terminal connected to conductor28. Switch56may be an N-channel MOS transistor, the gate of which coupled to receive the signal HV_OUTp=HV_SIG_DRV shown inFIG. 4. Switch57may be a P-channel MOS transistor, the gate of which is coupled to receive the signal HV_OUTn (FIG. 4). Thus, sampling switch18includes two signal paths, one being through “gate-boosted” transistor54, which provides the low impedance needed for a fast VSIGsampling rate. The other signal path is through transmission gate18B.

Transmission gate18B provides a continuous signal sampling path in case the sampling of VSIGrequires so much time that the boost voltage across boost capacitor55decays to an unreasonable level. Resistor55increases the signal transit time through the path including transmission gate18B. During the conversion process, boost capacitor55is precharged to a fixed voltage Vboost and transistor54is turned OFF by connecting its gate to HVSS. During sampling, when N-channel transistor54needs to be turned ON, the high-voltage input signal VSIGis selectively coupled by transistor66and conductor62to the bottom plate of boost capacitor55and to the source of N-channel transistor54, while the top plate of capacitor55is connected to the gate of N-channel transistor54. In this way, transistor54is turned ON with an input-independent gate-source voltage equal to Vboost, thus providing a low switch impedance and reduced distortion from the input switching transistor54.

Transmission gate18B ofFIG. 5is shown inFIG. 5A, and includes a N-channel transistor56A and a P-channel transistor56B coupled in parallel between conductors23and39. A resistor68is connected between conductor39and conductor28.

A schematic diagram of one implementation of sampling switch18A ofFIG. 5is shown inFIG. 5B, wherein the sampling switch18A includes N-channel transistor60having its drain coupled by conductor59to the output of a buffer58. Buffer58generates a precharging bias voltage on conductor59equal to HVSS+Vboost=HVSS+10 volts, which is used to pre-charge boost capacitor55. The source of transistor60is coupled by conductor61to one plate of boost capacitor55, the source of an N-channel transmission gate transistor64, and the source of a P-channel transmission gate transistor65. The drains of transistors64and65are connected to the gate of an N-channel transistor66, the gate of N-channel transistor54, and the drain of an N-channel transistor67. The other plate of boost capacitor55is connected by conductor62to the drain of an N-channel transistor63and the source of transistor66. The drain of transistor66is connected by conductor23to VSIGand the source of transistor54. The drain of transistor54is connected to a corresponding CDAC capacitor by conductor28. The sources of transistors63and67are connected to high-magnitude low-voltage supply HVSS. The gates of transistors60,63,65, and67are connected to the logical complement of HV_SIG_DRV, and the gate of transistor64is connected to HV_SIG_DRV.

During the conversion mode of SAR ADC10, boost capacitor54is precharged by buffer58. The signal HV_SIG_DRVn (which is the same as HV_OUTn inFIG. 4) is at a HIGH level, which turns ON transistors60and63. This connects boost capacitor55between the output of buffer58and the HVSSsupply voltage, so a precharge voltage of Vboost=10 volts is stored on boost capacitor55. During the conversion mode, the transmission switch, including transistors64and65, is turned OFF so that transistor54is completely disconnected from boost capacitor55. The gate of transistor54is connected to HVSSby turning ON N-channel transistor switch67. Note that gate of transistor67is also controlled by the logical complement of HV_SIG_DRV (which is this the same as HV_OUTp inFIG. 4), which is at a HIGH level during the conversion mode.

During the sampling mode, HV_SIG_DRVn goes to a LOW level and HV_SIG_DRV goes to a HIGH level. This turns OFF transistors60,63, and67and also turns on the transmission gate transistor64and65and transistor66. Since transistor66is turned ON, the input signal VSIGis applied to the bottom plate of boost capacitor55, thus boosting its top-plate voltage to VSIG+10 volts. Also, since transmission gate transistors64and65are turned ON, this results in connecting the top plate of boost capacitor55to the gate of transistor54. Consequently, the gate-source voltage of transistor54is an essentially constant value of 10 volts (to which boost capacitor55is precharged by buffer58) that turns ON transistor54so that input signal VSIGis connected directly through the low channel resistance of transistor54and conductor28to the bottom plate of the corresponding CDAC capacitor22(FIG. 2C). Due to the high, essentially constant gate-source voltage of transistor54, it provides low impedance to achieve fast signal settling. Furthermore, the ON impedance of transistor54does not vary significantly with input signal VSIG. This results in minimal signal distortion by SAR ADC10.

The described embodiment of the invention provides a significant reduction in the dynamic power consumption of a high-voltage SAR ADC, by eliminating 2 of the 3 level-shifters in each prior art bit switching circuit and thereby providing substantial reduction in power consumed from the high-voltage power supply. The described embodiment invention also reduces the amount of integrated circuit chip area required for the SAR ADC. This is also achieved because 2 of the 3 switches in each bit switching circuit are formed using low-voltage transistors instead of the substantially larger high-voltage transistors.

A main advantage of the invention is the much lower dynamic power consumption of the described SAR ADC compared to the prior art. Another advantage is that substantially lower integrated circuit chip area is required for each bit switching circuit33because of the elimination of two level shifters for each bit-switching circuit33and because low-voltage transistors can be used for the conversion switches30. Another advantage is that the magnitudes of the current spikes in the high-voltage power supply have been significantly reduced. Another advantage is that new bit switching circuitry33allows the high-voltage analog input signal VSIGto be directly sampled through a very low, relatively constant impedance onto the CDAC capacitors22, which results in minimal signal distortion and good SNR performance along with the features of low power consumption and low die area. Yet another advantage of the described high-voltage SAR ADC is that it provides reduced gain error in the ADC transfer function along with reduced dynamic power consumption, because of the capability of selecting any value of capacitance in the CDAC onto which the high-voltage input signal is sampled. Furthermore, the faster conversion times are achieved because the “switched VREF” settling time and the “switched GND” signal settling times are reduced because of the lower channel resistances that are achieved in the low-voltage switch circuits30, and this is achieved without increasing integrated circuit chip size.

It should be understood that intermediate node19can be selectively coupled (by the corresponding low-voltage switch30) to VREFinstead of GND (as previously described) during the sampling mode, and this will also protect intermediate node19, and hence also protect low-voltage switch30, from damage due to high voltages.

It should also be understood that the described high-voltage switch architecture may be usable in high-voltage, switched-capacitor, programable gain amplifiers (PGAs), and possibly also in other high-voltage, switched-capacitor amplifiers (although there are other known solutions for such applications that are not applicable to SAR converters).

While the invention has been described with reference to several particular embodiments thereof, those skilled in the art will be able to make various modifications to the described embodiments of the invention without departing from its true spirit and scope. It is intended that all elements or steps which are insubstantially different from those recited in the claims but perform substantially the same functions, respectively, in substantially the same way to achieve the same result as what is claimed are within the scope of the invention.