ICT probe contact improvement

A method of testing a printed circuit board (PCB) with an in-circuit test (ICT) probe having an improved probe-to-via contact is provided. The ICT probe includes a tip attached to a spindle; a housing having a cavity, a portion of the spindle insertable into the cavity; and a heating element wrapped helically around the spindle, the heating element coupled to the housing. The probe is contacted with a surface of a flux layer of a test via of the PCB, said contact compressing the heating element and recessing the insertable portion of the spindle into the cavity. The tip of the probe is heated with the heating element to a temperature capable of at least partially melting the flux layer, the tip at least partially penetrating the flux layer to contact a surface of a solder plugging the test via.

BACKGROUND

The present invention relates in general to printed circuit board (PCB) in-circuit test (ICT) methods and structures. More specifically, the present invention relates to ICT probe structures having an improved probe-to-via contact and methods of using the same.

Circuit boards such as multilayer printed circuit boards (PCBs) are widely used in the electronics industry. PCBs typically include one or more layers having conductive traces etched onto them, the various layers separated by a dielectric material. Interconnections are possible between each layer, for example using through-holes or vias. PCB design and production is often subject to various, often conflicting, requirements, such as a demand for products which are compact, operate at high-speeds, have low costs, and have high reliability. Meeting these requirements presents an ongoing challenge for the industry.

In-circuit tests (ICTs) are widely used throughout the industry to improve PCB reliability and quality control. ICTs assess the electrical properties of electrical elements in PCBs and the quality of the electrical connections between the electrical elements. ICTs measure the resistances, capacities, and other characteristics of each electrical element to detect potential manufacturing defects and the reliability of each electrical element tested. For example, an ICT can identify open or short circuits. ICTs offer simple operation requirements and accurate defect positioning.

SUMMARY

According to embodiments of the present invention, a method of fabricating an ICT probe having an improved probe-to-via contact is provided. The method can include providing an ICT probe having a tip attached to a spindle; a housing having a cavity, a portion of the spindle insertable into the cavity; and a heating element wrapped helically around the spindle, the heating element coupled to the housing. The probe is contacted with a surface of a flux layer of a test via of the PCB, said contact compressing the heating element and recessing the insertable portion of the spindle into the cavity. The tip of the probe is heated with the heating element to a temperature capable of at least partially melting the flux layer, the tip at least partially penetrating the flux layer to contact a surface of a solder plugging the test via.

According to embodiments of the present invention, a PCB ICT probe having an improved probe-to-via contact is provided. The probe can include a tip attached to a spindle; a housing having a cavity, a portion of the spindle insertable into the cavity; and a heating element wrapped helically around the spindle, the heating element coupled to the housing. Contacting a surface of a flux layer of a test via of the PCB with the probe compresses the heating element and recesses the insertable portion of the spindle into the cavity. The heating element is capable of heating the tip of the probe to a temperature capable of at least partially melting the flux layer.

DETAILED DESCRIPTION

For purposes of the description hereinafter, the terms “upper,” “lower,” “right,” “left,” “vertical,” “horizontal,” “top,” “bottom,” and derivatives thereof shall relate to the described structures and methods, as oriented in the drawing figures. The terms “overlying,” “atop,” “on top,” “positioned on” or “positioned atop” mean that a first element, such as a first structure, is present on a second element, such as a second structure, wherein intervening elements such as an interface structure can be present between the first element and the second element. The term “about” is intended to include the degree of error associated with measurement of the particular quantity based upon the equipment available at the time of filing the application. For example, “about” can include a range of ±8% or 5%, or 2% of a given value.

For the sake of brevity, conventional techniques related to ICTs of PCBs may or may not be described in detail herein. Moreover, the various tasks and process steps described herein can be incorporated into a more comprehensive procedure or process having additional steps or functionality not described in detail herein. In particular, various steps in the manufacture of ICT probes and PCBs are well known and so, in the interest of brevity, many conventional steps will only be mentioned briefly herein or will be omitted entirely without providing the well-known process details.

Turning now to a more detailed description of technologies relevant to the present invention, as previously noted herein, there are challenges to providing PCBs which are compact, operate at high-speeds, have low costs, and have high reliability. ICTs provide PCB quality control by testing the reliability of the PCB electrical elements and connections. ICTs rely upon a plurality of ICT probes positioned over each element and connection to be tested. For example, an ICT probe can be positioned over a test via. An accurate reliability test of the test via requires a firm contact between the ICT probe and the test via. Providing a reliable contact can be problematic, especially for test vias on PCBs treated with organic solderability preservative (OSP). OSP is a water-based organic compound introduced during the PCB fabrication process to selectively bond with and protect the PCB copper until soldering is applied in a later fabrication step to plug the test via. Unfortunately, the elevated reflow soldering temperatures required in lead-free soldering processes cause oxidation on the OSP coating. Consequently, a thin flux layer forms over the solder plugging the test via. The flux layer typically cools to room temperature prior to the ICT, becoming hard and sticky. The cooled flux layer reduces the quality of the contact between the ICT probe and the test via. Moreover, continuous testing of OSP-treated PCBs causes a buildup of flux to accumulate on the ICT probe tips. The flux buildup can further impede the probe-to-via contact.

The flux layer formed over the test via and the flux buildup on the ICT probe causes a high no defect found (NDF) rate during ICTs. The NDF rate indicates the frequency that a re-test of a failed test element (e.g., an electrical element or connection having a suspected defect) does not confirm the defect. For example, a 50% NDF rate for test vias indicates that half of the test vias which initially fail an ICT reliability test will pass when re-tested. A high NDF rate can indicate a poor contact between an ICT probe and a test element and substantially reduces the ICT efficiency. Known solutions to these flux problems are somewhat limited. For example, special test probe tips having a high spring force can improve probe-to-via contact, the cleaning frequency of each ICT probe during maintenance can be increased to remove flux build up from the probe tips, and the number of times the ICT probe actuates each PCB element (e.g., a test via) can be increased. These solutions increase the ICT cost, do not adequately address the flux layer formed over the test via, or fail to sufficiently decrease the NDF rate. Thus, a method and structure are desired for an ICT probe having an improved probe-to-via contact and reduced NDF rate.

Turning now to an overview of aspects of the present invention, one or more embodiments provide methods of fabricating an ICT probe and ICT probe structures having an improved probe-to-via contact. The described methods and structures employ a spring-based heating element. The spring-based heating element serves a dual purpose: first, heating the tip of the ICT probe to a temperature hot enough to soften and penetrate a flux layer on a test via; and second, providing a flexible connection to the ICT probe tip to improve the quality of the probe contact to the test via. The temperature of the ICT probe tip is controlled to remain below the solder melt point. In this manner, an ICT probe having an improved probe-to-via contact, a reduced NDF rate, and a reduced tip maintenance requirement is provided. The improved ICT probe is easily integrated into existing ICT systems, increasing ICT efficiency. Methods for fabricating an ICT probe and the resulting structures therefrom in accordance with embodiments of the present invention are described in detail below by referring to the accompanying drawings inFIGS. 1-5.

FIG. 1illustrates a cross-sectional view of a PCB100having a solder102plugging a test via104(sometimes referred to as “filling” a test via) during an intermediate step of an ICT according to one or more embodiments. Any known composition and manner of forming the PCB100can be utilized. In some embodiments, the PCB100can be a multilayer PCB and can be fully assembled (e.g., with capacitors, resistors, and other board elements). A fully assembled PCB is commonly referred to as a PCB assembly (PCBA). In some embodiments, the PCB100can include an OSP coating (not illustrated). The solder102can be of any suitable PCB solder material, such as, for example, a lead free solder material including tin, copper, silver, bismuth, indium, zinc, antimony, traces of other metals, and alloys thereof. The solder102can have a melting point, for example, of about 217 degrees Celsius. In some embodiments, the solder102is a high temperature application solder having a melting point of greater than about 400 degrees Celsius. In some embodiments, a flux layer106is formed as a bi-product of the soldering process over the solder102and portions of the PCB100. Consequently, the composition of the flux layer106depends in part upon the chosen solder material. In some embodiments, the flux layer106can be succinic acid, glutaric acid, adipic acid, ethylenediaminetetraacetic acid (EDTA), abietic acid, pimaric acid, and leviopimaric acid. Tables 1A and 1B illustrate a variety of possible flux compositions, associated chemical formula and structure, and melting points.

An ICT probe108having a tip110attached to a spindle112, a spring-based heating element114wrapped helically around the spindle112, and a housing116having a cavity contacts a surface of the flux layer106. The spring-based heating element114is coupled to the housing116. The cavity is sized such that a portion of the spindle112is insertable into the cavity of the housing116. In some embodiments, the spindle112includes a first diameter. A diameter of the cavity is slightly larger than the first diameter of the spindle112. By applying a force to the tip110(i.e., by pressing the tip110against the surface of the flux layer106), the spring-based heating element114is compressed and a portion of the spindle112is recessed into the cavity of the housing116. In some embodiments, the tip110is a high string force tip. Any known high string force tip can be utilized.

The tip110is heated by the spring-based heating element114to a temperature capable of at least partially melting the flux layer106. Partially melting the flux layer106allows for the tip110to at least partially penetrate the surface of the flux layer106to contact a surface of the solder102plugging the test via104. In some embodiments, a current is passed through the spring-based heating element114to heat the tip110(as depicted inFIG. 4).

In some embodiments, a test pad118of the PCB100is contacted by a reference probe120. The reference probe120(sometimes referred to as a “ground” or “power” probe) is formed in a like manner as is the ICT probe108. Contacting the reference probe120to the test pad118completes a circuit including the ICT probe108and the PCB100during the ICT.

FIG. 2illustrates a cross-sectional view of a surface of a test via200having a probe mark202during an intermediate step of an ICT according to one or more embodiments. The probe mark202indicates that a probe (not illustrated) successfully contacted a surface of the test via200. The test via200is plugged with a solder204. In some embodiments, the solder204is tin. In some embodiments, the solder204is a lead free solder material including tin, copper, silver, bismuth, indium, zinc, antimony, traces of other metals, and alloys thereof. A flux layer206overlaps the test via200and the solder204. As discussed previously herein, the flux layer206is formed as a bi-product of the soldering process. In some embodiments, the flux layer206spreads and flows non-uniformly across the surface of the test via200and the solder204.

FIG. 3illustrates a side view of a plurality of test probe tips300A-300E. Each tip is covered by a non-uniform build-up of flux302. As discussed previously herein, continuous testing of OSP-treated PCBs causes a buildup of flux to accumulate on ICT probe tips. The flux buildup can impede the probe-to-via contact during an ICT.

FIG. 4illustrates a cross-sectional view of the PCB100during an intermediate step of an ICT according to one or more embodiments. The ICT probe108is coupled to a temperature sensor400. A temperature controller402is electrically coupled to the temperature sensor400and to the spring-based heating element114. In some embodiments, the temperature controller402is a proportional-integral-derivative (PID) controller. The temperature controller402regulates a current passing through the spring-based heating element114. The current can be increased to increase the temperature of the spring-based heating element114. Similarly, the current can be decreased to decrease the temperature of the spring-based heating element114. The tip110is conductively heated by the spring-based heating element114.

In this configuration, the temperature of the tip110can be indirectly controlled by the temperature controller402by regulating the current passing through the spring-based heating element114. The temperature controller402ensures that the temperature of the tip110is high enough to at least partially melt the flux layer106while simultaneously limiting the temperature of the tip110to a temperature lower than a melting point of the solder102. In this manner, the tip110can at least partially penetrate the flux layer106to contact a surface of the solder102without damaging or otherwise compromising the solder102. Consequently, the probe-to-via contact between the ICT probe108and the test via104(plugged by the solder102) is improved and the NDF rate is correspondingly decreased. In some embodiments, the temperature controller402is manually adjustable by a user. In some embodiments, the temperature controller402automatically adjusts the current passing through the spring-based heating element in real-time.

FIG. 5illustrates a block diagram of the temperature controller402according to one or more embodiments. The temperature controller402can be a known proportional-integral-derivative (PID) controller. A PID controller uses a feedback control loop to minimize a calculated error value defined as a difference between a desired set point (e.g., a desired probe tip temperature) and a measured process variable (e.g., the actual temperature as measured in real-time). An adder500processes a temperature set value502and a feedback signal504(e.g., the current temperature as measured by the temperature sensor400in real-time) to calculate an error value by determining the difference between the temperature set value502and the feedback signal504. The output signal of the adder500is received by the proportional processor506, the integral processor508, and the derivative processor510. In some embodiments, the proportional processor506accounts for present values of the error value, the integral processor508accounts for past values of the error value, and the derivative processor510accounts for an expected future value of the error value as a function of the current rate of change in the error value. The output signal from each of the processors506,508, and510are combined by an adder512and received by a current control processor514. The current control processor514attempts to minimize the calculated error value by adjusting the current passing through the spring-based heating element114via current control516.

The descriptions of the various embodiments of the present invention have been presented for purposes of illustration but are not intended to be exhaustive or limited to the embodiments described. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the invention. The terminology used herein was chosen to best explain the principles of the embodiment, the practical application or technical improvement over technologies found in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments described herein.