Semiconductor device and method of manufacturing thereof

A silicon nitride film having a thickness of 3 nm or less is formed on the surfaces of a P-well and N-well, as well as on the upper and side surfaces of a gate electrode, in which the silicon nitride film can be formed, for example, by exposing the surface of the P-well and N-well, and the upper and side surfaces of the gate electrode to a nitrogen-gas-containing plasma using a magnetron RIE apparatus. Then, pocket layers, extension layers and source/drain layers are formed while leaving the silicon nitride film unremoved.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2002-167637, filed on Jun. 7, 2002, the entire contents of which are incorporated herein by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a semiconductor device suitable for composing CMOS (complementary metal-oxide semiconductor) and a method of manufacturing thereof.

2. Description of the Related Art

General procedures for manufacturing conventional CMOS transistor are as follows.FIGS. 15A through 17Care schematic sectional views serially showing process steps of a conventional method of manufacturing a CMOS transistor.

First as shown inFIG. 15A, an element isolation region4is formed in the surficial portion of a P-type semiconductor substrate1, and wells are then formed in the device forming areas partitioned by the element isolation region4, where a P-well2is formed in an N-channel MOS (NMOS) area, and an N-well3is formed in a P-channel MOS (PMOS) area.

Next as shown inFIG. 15B, an insulating film and a polysilicon film are formed on the semiconductor substrate1, and then patterned to thereby form gate insulating films5and gate electrodes6, respectively, in the device forming areas.

Next as shown inFIG. 15C, a resist film21is formed so as to cover the PMOS area and to expose the NMOS area. Using the resist film21and gate electrode6together as a mask, arsenic is ion-implanted at a high concentration to thereby form extension layers11in the P-well2, and then boron or indium is ion-implanted to thereby form pocket layers9deeper in the P-well2. Ion implantation of boron or indium herein is carried out from a direction normal to or declined away from the surface of the semiconductor substrate1.

Next as shown inFIG. 16A, the resist film21is removed, and a resist film22is formed so as to cover the NMOS area and to expose the PMOS area. Using the resist film22and gate electrode6together as a mask, boron is ion-implanted at a high concentration to thereby form extension layers12in the N-well3, and then arsenic is ion-implanted to thereby form pocket layers10deeper in the N-well3. Ion implantation of arsenic herein is carried out from a direction normal to or declined away from the surface of the semiconductor substrate1.

Next as shown inFIG. 16B, the resist film22is removed, an insulating film is formed over the entire surface, and the film is then anisotropically etched so as to leave a portion of such film only on the side surfaces of the gate electrodes6, to thereby form side walls13.

Next as shown inFIG. 16C, a resist film25is formed on the semiconductor substrate1so as to cover the PMOS area and to expose the NMOS area. Using the resist film25, gate electrode6and side walls13together as a mask, arsenic is ion-implanted at a high concentration to thereby form deep source/drain diffusion regions14.

Next as shown inFIG. 17A, the resist film25is removed, and a resist film26is formed on the semiconductor substrate1so as to cover the NMOS area and to expose the PMOS area. Using the resist film26, gate electrode6and side walls13together as a mask, boron is ion-implanted at a high concentration to thereby form deep source/drain diffusion regions15.

Then as shown inFIG. 17B, the resist film26is removed, and a silicide layer, which is typically a cobalt silicide layer16, is then formed on the gate electrodes6and source/drain diffusion regions14and15.

This process successfully yields a CMOS transistor.

The foregoing process however suffers from a drawback such that the resist films21,22used as the masks when the pocket layers and extension layers are formed must be removed after these layers are formed, where ashing or wet treatment required for removing the resist films21,22inevitably oxidizes the silicon substrate. Oxidation of the silicon substrate results in loss of the implanted impurities, which fails in attaining an expected concentration and profile. Oxidation of the silicon substrate is also disadvantageous in that making the extension layers distant from the gate portion to thereby substantially deepen junction of the extension layers. This undesirably causes degradation of the characteristics, which is typified by short-channel effect.

Another disadvantage of the above-described manufacturing method relates to annealing which is necessary for activating impurities in the source/drain region15after the formation thereof, where the annealing undesirably promotes outward diffusion of impurities which reside in the channel to thereby cause depletion of the channel, or undesirably promotes outward diffusion of impurities which reside in the source/drain diffusion region15.

There is known a technique for suppressing the outward diffusion, which is an oxide film capping based on RTO (rapid thermal oxidation). Another known technique relates to formation of an outward diffusion preventive film, which is typified by a nitride film having a thickness of 100 nm or around formed by CVD process. The oxide film capping, however, suffers from a drawback such that profile of the source/drain diffusion layer becomes deeper due to accelerated diffusion induced by oxygen. On the other hand, formation of the nitride film having a thickness of 100 nm or around on the side surfaces of the gate electrode by the CVD process tends to result in increased stress and abnormal diffusion.

SUMMARY OF THE INVENTION

In consideration of the foregoing problems, it is therefore an object of the present invention to provide a semiconductor device and a method of manufacturing thereof, which are aimed at achieving excellent characteristics, such as low extension resistivity, by preventing oxidation of the semiconductor substrate possibly proceeds during removal of the resist film, and by preventing outward diffusion of the impurities during annealing.

After extensive investigations, the present inventors reached the several aspects of the invention described below.

A method of manufacturing a semiconductor device according to one aspect of the present invention characteristically comprises a step for forming on a semiconductor substrate having a first conductivity type a gate insulating film which comprises a material having a dielectric constant higher than that of silicon oxide film; a step for forming a gate electrode on the gate insulating film; a step for introducing nitrogen into the surface of the semiconductor substrate and the gate electrode; and a step for forming a pair of impurity layers having the opposite conductivity type from the first conductivity type, which are formed in the semiconductor substrate so as to fall on both sides of the gate electrode.

In the present invention, formation of the gate insulating film and gate electrode is followed by introduction of nitrogen into the surfaces of the semiconductor substrate and gate electrode, so that the areas introduced with nitrogen are successfully prevented from being oxidized even the resist film is formed and then removed thereon. The present invention is also advantageous in that the annealing is carried out in such a state that the surfaces of the semiconductor substrate and gate electrode are introduced with nitrogen, which successfully prevents outward diffusion of impurities already contained therein.

The present invention is thus successful in preventing depletion of the channel, which has been a problem in the conventional process, and as a consequence in obtaining a semiconductor device having excellent characteristics.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

The semiconductor device and the method of manufacturing thereof according to embodiments of the present invention will specifically be described below.FIGS. 1A through 5Care schematic sectional views serially showing the process steps of the method of manufacturing a semiconductor device according to the first embodiment of the present invention.

In the first embodiment, an element isolation region4is formed in the surficial portion of a P-type semiconductor substrate1as shown inFIG. 1A, and wells are then formed in the device forming areas partitioned by the element isolation region4, where a P-well (channel)2is formed in an N-channel MOS (NMOS) area, and an N-well (channel)3is formed in a P-channel MOS (PMOS) area.

Next as shown inFIG. 1B, an insulating film and a polysilicon film are formed on the semiconductor substrate1, and then patterned to thereby form gate insulating films5and gate electrodes6, respectively, in the device forming areas. The gate insulating film5is preferably composed of a silicon oxinitride film, where a silicon oxide film is also allowable.

Next as shown inFIG. 1C, a silicon nitride film (nitrogen-introduced layer)7having a thickness of 3 nm or less is formed on the surface of a P-well2and N-well3, and on the upper and side surfaces of a gate electrode6. The silicon nitride film7can be formed typically by exposing the surfaces of the P-well2and N-well3, and the upper and side surfaces of the gate electrode6to a nitrogen-gas-containing plasma using a magnetron RIE apparatus. Typical conditions for the exposure involves a gas pressure of 10 mTorr (approx. 1.33×10−1Pa), an RF power of 100 W, an N2flow rate of 50 sccm, a process time of 2 seconds, and a process temperature of 15° C. It is also allowable to form the silicon nitride film7by exposing the surfaces of the P-well2and N-well3, and the upper and side surfaces of the gate electrode6to a plasma of a mixed gas of nitrogen and argon using a magnetron RIE apparatus. Still another method of forming the silicon nitride film7can be such that exposing the surfaces of the P-well2and N-well3, and the upper and side surfaces of the gate electrode6to radicals generated from a nitrogen-containing gas (e.g., a mixed gas of nitrogen and helium) using a remote-plasma apparatus. Typical conditions for the exposure involves a process temperature of 550 to 800° C., a process time of 30 to 60 seconds, a power of 3 kW, and a mixing ratio of nitrogen and helium of 10:90 in percentage by volume.

Next as shown inFIG. 2A, a silicon oxide film8aand a silicon nitride film8bare successively formed over the entire surface.

Next as shown inFIG. 2B, the silicon nitride film8bis anisotropically etched to thereby leave the film only on the side portions of the gate electrode6.

The silicon oxide film8ais then subjected to wet processing. The process results in removal of the lower end portions of the stacked film which is composed of the silicon oxide film8aand silicon nitride film8b, to thereby form notches8thereat as shown inFIG. 2C.

Next as shown inFIG. 3A, a resist film21is formed on the semiconductor substrate1so as to cover the PMOS area and to expose the NMOS area. Using the resist film21and gate electrode6together as a mask, P-type impurities, which are typically indium and boron, are ion-implanted to thereby form P-type pocket layers9in the surficial portions of the P-well2. The ion implantation is typically carried out by inclined ion implantation from four directions orthogonal to each other in a plan view. As for the ion implantation of indium, an implantation energy is typically set to 60 to 90 keV and an amount of dose is set to 5×1012to 1.1×1013cm−2. As for the ion implantation of boron, an implantation energy is typically set to 8 to 12 keV and an amount of dose is set to 2×1012to 7×1012cm−2. The resist film21is removed after the ion implantation, and then annealing is carried out so as to activate the implanted impurities. It is also allowable to carry out the annealing by spike annealing under an N2atmosphere at 950 to 1,050° C. The removal of the resist film21can be accomplished by ashing or wet processing. Typical conditions for the ashing relate to use of a down-flow apparatus, an O2flow rate of 1,000 sccm, a CF4flow rate of 10 sccm, a flow rate of a forcing gas of 600 sccm, and a process temperature of 250° C. The wet processing can typically be accomplished by using a sulfuric acid-hydrogen peroxide mixed solution. Any other resist films described hereinafter can be removed in a similar manner.

Then as shown inFIG. 3B, a resist film22is formed on the semiconductor substrate1so as to cover the NMOS area and to expose the PMOS area. Using the resist film22and gate electrode6together as a mask, an N-type impurity, which is typically antimony, is ion-implanted to thereby form N-type pocket layers10in the surficial portions of the N-well3. The ion implantation is typically carried out by inclined ion implantation from four directions orthogonal to each other in a plan view, where an implantation energy is typically set to 50 to 70 keV and an amount of dose is set to 1.0×1013to 1.5×1013cm−2. The resist film22is removed after the ion implantation.

Next as shown inFIG. 3C, a resist film23is formed on the semiconductor substrate1so as to cover the PMOS area and to expose the NMOS area. Using the resist film23, gate electrode6, silicon oxide film8aand silicon nitride film8btogether as a mask, an N-type impurity, which is typically arsenic, is ion-implanted to thereby form N-type extension layers11in the surficial portions of the pocket layers9. The ion implantation is effected typically from the direction normal to the surface of the semiconductor substrate1, where an implantation energy is typically set to 2 to 4 keV and an amount of dose is set to 1.0×1015to 1.5×1015cm−2. The resist film23is removed after the ion implantation, and then annealing is carried out so as to activate the implanted impurity. It is also allowable to carry out the annealing by spike annealing under an N2atmosphere at 950 to 1,050° C.

Next as shown inFIG. 4A, a resist film24is formed on the semiconductor substrate1so as to cover the NMOS area and to expose the PMOS area. Using the resist film24, gate electrode6, silicon oxide film8aand silicon nitride film8btogether as a mask, a P-type impurity, which is typically boron, is ion-implanted to thereby form P-type extension layers12in the surficial portions of the pocket layers10. The ion implantation is effected typically from the direction normal to the surface of the semiconductor substrate1, where an implantation energy is typically set to 0.2 to 0.4 keV and an amount of dose is set to 1.0×1015to 1.5×1015cm−2. The resist film24is removed after the ion implantation.

An insulating film, which is typically a silicon oxide film, is formed over the entire surface, and the film is then anisotropically etched so as to leave a portion of such film only on the side portions of the gate electrodes6, to thereby form side walls13as shown inFIG. 4B. The silicon oxide film8aand silicon nitride film8bare buried for example in the side walls13.

Next as shown inFIG. 4C, a resist film25is formed on the semiconductor substrate1so as to cover the PMOS area and to expose the NMOS area. Using the resist film25, gate electrode6and side walls13together as a mask, an N-type impurity, which is typically phosphorus, is ion-implanted at a high concentration to thereby form deep N-type source/drain diffusion regions14in the surficial portion of the P-well2. The ion implantation is carried out typically from the direction normal to the surface of the semiconductor substrate1, where an implantation energy is set to 5 to 9 keV and an amount of dose is set to 5×1015to 8×1015cm−2. The resist film25is removed after the ion implantation.

Next as shown inFIG. 5A, a resist film26is formed on the semiconductor substrate1so as to cover the NMOS area and to expose the PMOS area. Using the resist film26, gate electrode6and side walls13together as a mask, a P-type impurity, which is typically boron, is ion-implanted at a high concentration to thereby form deep P-type source/drain diffusion regions15in the surficial portion of the N-well3. The ion implantation is carried out typically from the direction normal to the surface of the semiconductor substrate1, where an implantation energy is typically set to 2 to 5 keV and an amount of dose is set to 3×1015to 5×1015cm−2. The resist film26is removed after the ion implantation, and then annealing is carried out so as to activate the implanted impurity. It is also allowable to carry out the annealing by spike annealing under an N2atmosphere at 1,025 to 1,070° C.

Then as shown inFIG. 5B, an exposed portion of the silicon nitride film7is removed, and a silicide layer16, which is typically a cobalt silicide layer, is formed on the gate electrode6and source/drain diffusion layers14,15.

The process then advances to formation of an interlayer insulating film17, formation of contact holes18which penetrate the interlayer insulating film17to reach the source/drain diffusion regions14,15, filling of the contact holes18with a conductive material19, and formation of a wiring, which completes a CMOS transistor.

The semiconductor device thus manufactured has a constitution shown inFIG. 5C.

According to the first embodiment of the present invention, the silicon nitride layer7is formed at least on the side surfaces of the gate electrode6and on the surfaces of the P-well2and N-well3after the process step for forming the gate electrode6(FIG. 1B) and before the process step for annealing for activation of the impurities in the source/drain diffusion regions14,15, so that the outward diffusion of the impurities in the channel, and the outward diffusion of the impurities in the source/drain diffusion regions14,15can successfully be suppressed even when the annealing is carried out. This is successful in suppressing depletion which has been a problem in the previous process.

While the foregoing process includes the steps for forming and removing the resist films each time the pocket layers, extension layers and source/drain diffusion layers are formed, the surfaces of the P-well2and N-well3(surface of the semiconductor substrate1) are prevented from being oxidized during ashing or wet processing for removing the resist films since the silicon nitride film7is formed at least on the surface of the P-well2and N-well3. This successfully prevents decrease in the impurities and changes in the concentration and profile. The extension layers is not deepened, which is advantageous in that ensuring shallow junction.

Another advantage resides in that the pocket layers are formed by the ion implantation effected from a direction inclined away from the surface of the semiconductor substrate1after the notches are formed8, and that the extension layers are formed by the ion implantation effected from the direction normal to the surface of the semiconductor substrate1, so that overlap in the plan view of the extension layers with the gate electrode can be suppressed to a narrow level while ensuring a wide overlap of the pocket layers with the gate electrode.

Next paragraphs will deal with the second embodiment of the present invention. In the second embodiment, a double sidewall structure is applied to a CMOS transistor.FIGS. 6A through 6Care schematic sectional views serially showing process steps of a method of manufacturing a semiconductor device according to the second embodiment of the present invention, andFIG. 7is a schematic sectional view showing a CMOS transistor manufactured by the second embodiment of the present invention.

In the second embodiment, the process steps from formation of the element isolation region4(FIG. 1A) to formation of the silicon nitride layer7(FIG. 1C) are carried out similarly to those in the first embodiment.

Next as shown inFIG. 6A, a silicon oxide film31is formed over the entire surface.

Next as shown inFIG. 6B, the silicon oxide film31is anisotropically etched so as to leave a portion thereof only on the side portions of the gate electrodes6.

The process steps from formation of the resist film21(FIG. 3A) to formation of the extension layers12(FIG. 4A) are then carried out similarly to those in the first embodiment.

An insulating film, which is typically a silicon oxide film, is then formed on the entire surface, and the film is then anisotropically etched so as to leave a portion thereof only on the side portions of the gate electrodes6, to thereby form side walls13as shown inFIG. 6C. The silicon oxide film31is covered for example with the side walls13.

The process steps from formation of the resist film25(FIG. 4C) and thereafter are then carried out similarly to those in the first embodiment, which completes a CMOS transistor shown inFIG. 7.

The effects of preventing outward diffusion and oxidation of the semiconductor substrate1during the removal of the resist films can be obtained also in the second embodiment similarly to the first embodiment.

Next paragraphs will deal with the third embodiment of the present invention. In the third embodiment, a structure having a notched gate electrode is applied to a CMOS transistor.FIGS. 8A through 9Care schematic sectional views serially showing process steps of a method of manufacturing a semiconductor device according to the third embodiment of the present invention, andFIG. 10is a schematic sectional view showing a CMOS transistor manufactured by the third embodiment of the present invention.

In the third embodiment, the element isolation region4, P-well2and N-well3are formed (FIG. 1A) similarly to the first embodiment.

Next as shown inFIG. 8A, an insulating film32and a polysilicon film33are formed on the semiconductor substrate1, and further on the polysilicon film33in the device forming areas, resist films27are formed so as to cover the areas where the gate electrodes are to be formed.

Next using the resist films27as a mask and using a gas containing HBr and O2, the upper portion of the polysilicon film33is etched. The etching is carried out under a condition which allows the depositional matter generated in the etching to readily adhere on the side planes of the upper portion of the polysilicon film33which emerge as the etching proceeds. When the etching completes, a deposit34remains as shown inFIG. 8B.

The lower portion of the polysilicon film33is then etched using the resist film27as a mask. The etching is carried out under a condition which makes it difficult for the depositional matter generated in the etching to adhere on the side planes of the lower portion of the polysilicon film33which emerge as the etching proceeds. When the etching completes, a deposit34remains on the upper side planes of the etched polysilicon film33and side planes of the resist film27.

The polysilicon film33is then isotropically etched using the resist film27as a mask. In the isotropic etching, the upper portion of the polysilicon film33is hardly removed by virtue of protection by the thick deposit34, but the etching of the lower portion of the polysilicon film33can proceed since the portion has only a slight amount of deposit34adhered thereon which can readily be removed. When the etching completes, tapered notches35are formed along the edges of the gate insulating film5and the bottom ends of the gate electrode6as shown inFIG. 9A. The gate electrode6thus obtained comprises the residual portion of the polysilicon film33and deposit34.

Next a silicon nitride film7having a thickness of 3 nm or less is formed on the surface of the P-well2and N-well3, on the upper and side surfaces of the gate electrode6, and on the side surfaces of the notches35as shown inFIG. 9B. The silicon nitride film7can be formed similarly to the first embodiment.

The process steps from formation of the resist film21(FIG. 3A) to formation of the extension layers12(FIG. 4A) are carried out similarly to those in the first embodiment.

An insulating film, which is typically a silicon oxide film, is formed over the entire surface, and the film is then anisotropically etched so as to leave a portion thereof only on the side portions of the gate electrodes6, to thereby form side walls13as shown inFIG. 9C.

The process steps from formation of the resist film25(FIG. 4C) and thereafter are carried out similarly to those in the first embodiment, which completes a CMOS transistor shown inFIG. 10.

The effects of preventing outward diffusion and oxidation of the semiconductor substrate1during the removal of the resist films can be obtained also in the third embodiment similarly to the first embodiment.

Next paragraphs will deal with the fourth embodiment of the present invention. In the fourth embodiment, a so-called, single-drain structure is applied to a CMOS transistor.FIG. 11is a schematic sectional view showing a CMOS transistor manufactured by the fourth embodiment of the present invention.

The CMOS transistor shown inFIG. 11has neither the pocket layers nor extension layers in any of the source/drain regions of the N-channel transistor and P-channel transistor, unlike the CMOS transistor previously shown inFIG. 5C. Also the side walls13are not formed.

The CMOS transistor having such constitution can be manufactured by the process steps previously shown inFIGS. 1AthroughFIG. 5C, except that the process steps for forming the pocket layers or extension layers, and associate process steps for forming and removing the masks are omitted. It is to be noted now that the process step for forming the silicon nitride layer7shown inFIG. 1Cis, of course, an indispensable step.

The effects of preventing outward diffusion and oxidation of the semiconductor substrate1during the removal of the resist films can be obtained also in the fourth embodiment similarly to the first embodiment.

Next paragraphs will deal with the fifth embodiment of the present invention. In the fifth embodiment, a structure having neither notches8nor notches32is applied to a CMOS transistor.FIGS. 12A through 12Care schematic sectional views serially showing process steps of a method of manufacturing a semiconductor device according to the fifth embodiment of the present invention, andFIG. 13is a schematic sectional view showing a CMOS transistor manufactured by the fifth embodiment of the present invention.

In the fifth embodiment, the process steps from formation of the element isolation region4(FIG. 1A) to formation of the silicon nitride film7(FIG. 1C) are carried out similarly to those in the first embodiment.

Next as shown inFIG. 12A, the resist film21is formed while omitting the preceding steps shown inFIGS. 2A through 2C. Using the resist film21and gate electrode6together as a mask, the P-type pocket layers9and N-type extension layers11are formed.

Next as shown inFIG. 12B, the resist film21is removed, and then the resist film22is formed. Using the resist film22and gate electrode6together as a mask, the N-type pocket layers10and P-type extension layers12are formed.

The resist film22is then removed, and the process steps from formation of the side walls13(FIG. 4B) and thereafter are carried out similarly to those in the first embodiment, which completes a CMOS transistor shown inFIG. 13.

The effects of preventing outward diffusion and oxidation of the semiconductor substrate1during the removal of the resist films can be obtained also in the fifth embodiment similarly to the first embodiment.

In the present invention, the thickness of the nitride film is preferably 3 nm or less, and more preferably 2 nm or less.FIG. 14is a graph showing relation between the thickness of the nitride film and resistivity of the extension layer (extension resistivity). As is clear fromFIG. 14, the nitride film having a proper thickness can lower the resistivity of the extension layer, but too large thickness thereof tends to undesirably raise the resistivity of the extension layer. The nitride film has thus preferably has a thickness of 3 nm or less.

The CMOS transistors explained in the foregoing embodiments are applicable to inverter or so. It is to be noted now that the semiconductor device according to the present invention is by no means limited to those applied to the CMOS transistors.

While the ion implantation in the foregoing embodiments are carried out using the resist films as a mask, the present invention is also valid for the case where a stencil mask is used. The reason why resides in that it is no more necessary to carry out a step for removing the resist film for the case where the stencil mask is used, but the conventional method suffers from probability of depletion of the channel during the annealing.