Semiconductor package

A semiconductor package is provided. The semiconductor package includes: a mounting substrate including at least one bonding pad; a first semiconductor chip disposed on the mounting substrate, and including a first protrusion on one side of the first semiconductor chip; a first spacer ball electrically connected to the first semiconductor chip; a first bump ball electrically connected to the first spacer ball; and a first wire which electrically connects the first bump ball and the bonding pad without contacting the first protrusion, wherein the first wire includes a first portion extending in a direction away from the bonding pad, and a second portion extending in a direction approaching the bonding pad.

CROSS-REFERENCE TO THE RELATED APPLICATION

This application claims priority from Korean Patent Application No. 10-2018-0099332, filed on Aug. 24, 2018, the disclosure of which is incorporated herein by reference in its entirety.

BACKGROUND

Apparatuses and methods consistent with the exemplary embodiments of the inventive concept relate to a semiconductor package including a folded loop and a normal loop.

2. Description of the Related Art

Recently, the size of semiconductor chips has been increased while requiring implementation of high-performance elements. Further, in order to satisfy multi-functionalization and high capacity of a semiconductor package, a multi-chip semiconductor package in which a plurality of semiconductor chips are stacked in one package is developed.

However, with slimming-down of electronic devices in which semiconductor packages are used, the size of semiconductor packages tends to decrease. In order to satisfy such a tendency of downsizing of electronic devices, various researches on a method capable of reducing the size of a semiconductor package are being conducted.

SUMMARY

Various embodiments of the inventive concept provide a miniaturized semiconductor package with improved product reliability.

However, the inventive concept is not restricted to these embodiments described herein, and instead, various other embodiments will become apparent to one of ordinary skill in the art to which the inventive concept pertains by referencing the detailed description of these embodiments.

According to some embodiments of the inventive concept, there is provided a semiconductor package which may include: a mounting substrate including at least one bonding pad; a first semiconductor chip disposed on the mounting substrate, and including a first protrusion on one side of the first semiconductor chip; a first spacer ball electrically connected to the first semiconductor chip; a first bump ball electrically connected to the first spacer ball; and a first wire which electrically connects the first bump ball and the bonding pad without contacting the first protrusion, wherein the first wire includes a first portion extending in a direction away from the bonding pad, and a second portion extending in a direction approaching the bonding pad.

According to some embodiments of the inventive concept, there is provided a semiconductor package which may include: at least one bonding pad; a first semiconductor chip including a first chip pad connected to the bonding pad, and a first protrusion protruding from an upper surface of the first chip pad; a first spacer ball on the first chip pad; a first bump ball on the first spacer ball; a first wire which connects the first bump ball and the bonding pad without contacting the first protrusion; a second semiconductor chip disposed on the first semiconductor chip, and including a second chip pad connected to the bonding pad, and a second protrusion protruding from an upper surface of the second chip pad; a second bump ball directly connected to the second chip pad; and a second wire which connects the second bump ball and the bonding pad without contacting the second protrusion, wherein the first wire includes a first portion extending in a direction away from the bonding pad, and a second portion extending in a direction approaching the bonding pad, and the second wire does not extend in the direction away from the bonding pad.

According to some embodiments of the inventive concept, there is provided a semiconductor package which may include: a mounting substrate including at least one bonding pad; a first semiconductor chip disposed on the mounting substrate, and including a first chip pad and a first protrusion protruding from the first chip pad; a second semiconductor chip disposed on the first semiconductor chip, and including a second chip pad and a second protrusion protruding from the second chip pad; a third semiconductor chip disposed on the second semiconductor chip, and including a third chip pad and a third protrusion protruding from the third chip pad; and a first wire, a second wire and a third wire connecting of the first to third chip pads to the bonding pad, respectively, wherein the second wire is connected to the second chip pad by a second spacer ball disposed on the second chip pad and a second bump ball disposed on the second spacer ball, wherein the first chip pad and the third chip pad do not overlap the second semiconductor chip in a vertical direction, wherein the second chip pad overlaps the first semiconductor chip and the third semiconductor chip in the vertical direction, and wherein the second wire includes a first portion extending in a direction away from the bonding pad, and a second portion extending in a direction approaching the bonding pad.

DETAILED DESCRIPTION OF THE EXEMPLARY EMBODIMENTS

The embodiments presented herein are all exemplary which do not restrict the inventive concept. An embodiment provided in the following description is not excluded from being associated with one or more features of another example or another embodiment also provided herein or not provided herein but consistent with the inventive concept. For example, even if matters described in a specific example are not described in a different example thereto, the matters may be understood as being related to or combined with the different example, unless otherwise mentioned in descriptions thereof.

It will be understood that when an element or layer is referred to as being “over,” “above,” “on,” “connected to” or “coupled to” another element or layer, it can be directly over, above, on, connected or coupled to the other element or layer or intervening elements or layers may be present. In contrast, when an element is referred to as being “directly over,” “directly above,” “directly on,” “directly connected to” or “directly coupled to” another element or layer, there are no intervening elements or layers present. Like numerals refer to like elements throughout. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items.

FIG. 1is an exemplary diagram for illustrating a semiconductor package according to some embodiments.

Referring toFIG. 1, the semiconductor package may include a mounting substrate100, a first semiconductor chip120a, a first adhesive film121, a first spacer ball150a, a first bump ball160a, a first wire170a, and a first molding resin180.

The first semiconductor chip120amay be disposed on the mounting substrate100. The first adhesive film121may be disposed between the first semiconductor chip120aand the mounting substrate100. For example, the first semiconductor chip120amay be fixed to the mounting substrate100by the first adhesive film121. The first adhesive film121may be, for example, a Die Attach Film (DAF).

The mounting substrate100may include a first bonding pad110on a surface on which the first semiconductor chip120ais disposed. The first semiconductor chip120amay include a first chip pad130aon a surface opposite to a surface connected to the mounting substrate100.

The first spacer ball150amay be disposed on the first semiconductor chip120a. For example, the first spacer ball150amay be connected to the first chip pad130aof the first semiconductor chip120a. The first bump ball160amay be disposed on the first spacer ball150a. For example, the first bump ball160amay be connected to the first spacer ball150a.

The first wire170amay electrically connect the first semiconductor chip120aand the mounting substrate100. For example, the first wire170amay connect the first chip pad130aof the first semiconductor chip120aand the first bonding pad110aof the mounting substrate100, thereby electrically connecting the first semiconductor chip120aand the mounting substrate100.

The first molding resin180may be formed on the mounting substrate100to cover the first semiconductor chip120a, the first adhesive film121, the first bonding pad110a, the first spacer ball150a, the first bump ball160aand the first wire170a. The first molding resin180may protect the internal constituent elements of the semiconductor package. For example, the first molding resin180may prevent or reduce an external shock from being transmitted to the mounting substrate100, the first semiconductor chip120a, the first adhesive film121, the first bonding pad110a, the first spacer ball150a, the first bump ball160aand the first wire170a. The first molding resin180may be, for example, an epoxy molding compound (EMC), but the embodiments are not limited thereto.

According to some embodiments, the mounting substrate100may be a packaging substrate, and may be, for example, a printed circuit board (PCB), a ceramic substrate or the like. On a lower surface of the mounting substrate100, that is, on a surface opposite to the mounting surface on which the first semiconductor chip120ais disposed, an external terminal (for example, a solder ball or a lead frame) which electrically connects the semiconductor package to the external device may be formed. The first bonding pad110amay be electrically connected to an external terminal connected to the external device, and may supply an electrical signal to the first semiconductor chip120a. Alternatively, the first bonding pad110amay be, for example, a ground pad and may be electrically connected to a ground line in the mounting substrate100. The first bonding pad110ais illustrated, for example, as being disposed in an outer shell of the mounting substrate100, but the embodiments are not limited thereto.

According to some embodiments, the first semiconductor chip120amay be, for example, a memory chip, a logic chip, or the like. When the first semiconductor chip120ais a logic chip, various designs may be made in consideration of operations to be performed. When the first semiconductor chip120ais a memory chip, the memory chip may be, for example, a non-volatile memory chip. For example, the first semiconductor chip120amay be a flash memory chip. For example, the first semiconductor chip120amay be one of a NAND flash memory chip and a NOR flash memory chip. However, the form of the memory device according to the technical idea of the inventive concept is not limited thereto. In some embodiments, the first semiconductor chip120amay be one of a phase-change random access memory (PRAM), a magneto-resistive random access memory (MRAM), and a resistive random access memory (RRAM).

According to some embodiments, the first chip pad130aof the first semiconductor chip120amay be electrically connected to the semiconductor element inside the first semiconductor chip120a. Therefore, the electric signal received by the first bonding pad110amay be transmitted to the first chip pad130aof the first semiconductor chip120aby the first wire170a. The electric signal transmitted to the first chip pad130aof the first semiconductor chip120amay be transmitted to the semiconductor element inside the first semiconductor chip120a.

According to some embodiments, the first semiconductor chip120amay include a first protrusion140a. The first protrusion140amay include a portion protruding in a vertical direction z from an upper surface120a_usof the first semiconductor chip. In some drawings, the first protrusion140ais illustrated as being a rectangular portion protruding in the vertical direction z from the upper surface120a-usof the first semiconductor chip, but the embodiments are not limited thereto. For example, the first protrusion140amay have various shapes such as a triangular shape or a tilted triangular shape. The process of generating the first protrusion140aof the first semiconductor chip120awill be described with reference toFIGS. 2, 3a, and3b.

FIG. 2is an exemplary diagram for describing a wafer including the semiconductor chip region according to some embodiments.FIGS. 3A and 3Bare illustrative diagrams for explaining a process of forming protrusions of the semiconductor chip according to some embodiments.

Referring toFIG. 2, the wafer200may include a first semiconductor chip region20and a second semiconductor chip region21. For example, the first semiconductor chip region20and the second semiconductor chip region21may be arranged on the wafer200in planar directions x, y. A cutting region22may be disposed between the first semiconductor chip region20and the second semiconductor chip region21. Each of the first semiconductor chip region20and the second semiconductor chip region21may include an internal circuit required for driving the semiconductor chip.

Referring toFIGS. 3A and 3B, by separating the first semiconductor chip region20and the second semiconductor chip region21along the cutting region22, the respective semiconductor chips (20_chip,21_chip) may be generated. For example, the first semiconductor chip region20and the second semiconductor chip region21may be separated in the x direction and in the −x direction on the basis of the cutting region22. The semiconductor chips (20_chip,21_chip) formed by separating the first semiconductor chip region20and the second semiconductor chip region21may include protrusions20_pt,21_pt, respectively. At this time, the protrusions20_pt,21_ptmay be generated due to the characteristics of a material constituting the semiconductor chips (20_chip,21_chip). Alternatively, the protrusions20_pt,21_ptmay be generated due to an external stress generated when separating the first semiconductor chip region20and the second semiconductor chip region21along the cutting region22. However, the embodiments are not limited to these causes of generating the protrusions20_pt,21_pt. Each of the semiconductor chips (20_chip,21_chip) may include protrusions20_pt,21_ptdue to various causes, in addition to the above-described causes.

Referring again toFIG. 1, the first wire170amay include, for example, gold, copper, aluminum, or the like. The first wire170amay be formed by, for example, a capillary, but the embodiments are not limited thereto. An example of the process of forming the first wire170awill be described later.

According to some embodiments, the first wire170amay be formed as a folded loop having a hook shape. The hook shape means a shape including a portion extending in a direction away from the first bonding pad110aand a portion extending in a direction approaching the first bonding pad110a. The folded loop means that the wire adjacent to a portion in which the first wire170ais connected to the first bump ball160ahas a wrinkled shape. The description will be provided with reference toFIG. 4for illustrative explanation.

FIG. 4is an enlarged view illustrating a region A ofFIG. 1in an enlarged manner.

Referring toFIG. 4, the first wire170amay include a first portion170a1extending in a direction away from the first bonding pad110a, and a second portion170a2extending in a direction approaching the first bonding pad110a. In other words, the first wire170amay have a hook shape. Further, the first wire170amay have a shape in which a portion adjacent to the portion connected to the first bump ball160ais wrinkled downward. In other words, the first wire170amay be formed as a folded loop having a hook shape.

According to some embodiments, since the first wire170ais formed as a folded loop, a height H1of the first wire may be smaller than the height of a general bonding wire. In a case where another semiconductor chip is vertically stacked on the first semiconductor chip120a, since the height H1of the first wire is smaller than the height of the general bonding wire, more chips may be stacked in the same region. Therefore, by forming the first wire170aas a folded loop, the semiconductor package can be miniaturized.

According to some embodiments, the first wire170adoes not come into contact with the first protrusion140aof the first semiconductor chip120a. When the first wire170acomes into contact with the first protrusion140aof the first semiconductor chip120a, a defective operation of the first semiconductor chip120amay occur. Therefore, according to some embodiments, by inserting the first spacer ball150abetween the first bump ball160aand the first chip pad130aof the first semiconductor chip120a, it is possible to prevent short-circuit between the first wire170aand the first protrusion140aof the first semiconductor chip120a. The height of the first spacer ball150amay be changed on the basis of the height of the first protrusion140a.

According to some embodiments, since the first wire170ais not in contact with the first protrusion140aof the first semiconductor chip120a, reliability of the semiconductor package can be improved. In addition, since the height H1of the first wire is reduced and more semiconductor chips may be stacked, the degree of integration of the semiconductor package can be improved.

FIG. 5is an exemplary diagram illustrating a semiconductor package in which semiconductor chips according to some embodiments are stacked vertically.

Referring toFIG. 5, the semiconductor package according to some embodiments may include a mounting substrate100, a first semiconductor chip120a, a second semiconductor chip120b, a third semiconductor chip120c, a first spacer ball150a, a second spacer ball150b, a first bump ball160a, a second bump ball160b, a third bump ball160c, a first wire170a, a second wire170b, a third wire170c, a first adhesive film121, a second adhesive film122, a third adhesive film123, and a molding resin180.

Each of the constituent elements illustrated inFIG. 5may be similar to those ofFIG. 1described above. Therefore, repeated descriptions will be omitted or briefly explained. According to some embodiments, the first semiconductor chip120amay include a first chip pad130aand a first protrusion140aprotruding from the upper surface120aus of the first semiconductor chip. The second semiconductor chip120bmay include a second chip pad130band a second protrusion140bprotruding from the upper surface of the second semiconductor chip120b. The third semiconductor chip120cmay include a third chip pad130cand a third protrusion140cprotruding from the upper surface of the third semiconductor chip120c.

The first semiconductor chip120amay be disposed on the mounting substrate100. For example, the first semiconductor chip120amay be attached to the mounting substrate100via the first adhesive film121.

The first spacer ball150amay be connected to the first chip pad130aof the first semiconductor chip120a. The first bump ball160amay be connected to the first spacer ball150a. The first wire170amay be connected to the first bump ball160aand the first bonding pad110a. In other words, the first chip pad130aand the first bonding pad110amay be electrically connected by the first wire170a. That is, the first semiconductor chip120aand the mounting substrate100may be electrically connected to each other via the first wire170a. In some embodiments, the first wire170amay be formed as a folded loop having a hook shape.

According to some embodiments, the first wire170ais not in contact with the first protrusion140aof the first semiconductor chip120a. Also, the first wire170ais not in contact with the second semiconductor chip120b. When the first wire170ais in contact with the first protrusion140aof the first semiconductor chip120aand the second semiconductor chip120b, a defective operation may occur in the semiconductor package. Therefore, according to some embodiments, by inserting the first spacer ball150abetween the first bump ball160aand the first chip pad130aof the first semiconductor chip120awith forming the first wire170aas a folded loop having a hook shape, it is possible to prevent the first wire170afrom being short-circuited to the first protrusion140aof the first semiconductor chip120aand the second semiconductor chip120b. The height of the first spacer ball150amay be changed considering the height of the first protrusion140aand the distance between the first semiconductor chip120aand the second semiconductor chip120b.

According to some embodiments, since the first wire170ais not in contact with the first protrusion140aof the first semiconductor chip120aand the second semiconductor chip120b, reliability of the semiconductor package can be improved. In addition, since the height H1of the first wire is reduced and more semiconductor chips may be stacked, the degree of integration of the semiconductor package may be improved.

The second semiconductor chip120bmay be arranged on the first semiconductor chip120a. For example, the second semiconductor chip120bmay be attached to the first semiconductor chip120avia the second adhesive film122. In other words, the second adhesive film122may be disposed between the first semiconductor chip120aand the second semiconductor chip120b.

The first adhesive film121and the second adhesive film122may be, for example, a Die Attach Film (DAF), and may be a material into which the wire may penetrate. The thicknesses of the first adhesive film121and the second adhesive film122may be different depending on the positions to be attached. The adhesive film into which the wire penetrates, e.g., the second adhesive film122into which the first wire170apenetrates, may be, for example, thicker than the first adhesive film121so that the first wire170amay be protected. Here, the expression “the wire penetrates into the adhesive film” means that even if the adhesive film is disposed on the wire, since the adhesive film surrounds the wire, the shape of the wire is maintained unchanged.

The second spacer ball150bmay be connected to the second chip pad130bof the second semiconductor chip120b. The second bump ball160bmay be connected to the second spacer ball150b. The second wire170bmay be connected to the second bump ball160band the first bonding pad110a. In other words, the second chip pad130band the first bonding pad110amay be electrically connected to each other by the second wire170b. That is, the second semiconductor chip120band the mounting substrate100may be electrically connected to each other via the second wire170b. The second wire170bmay be formed as a folded loop having a hook shape. In the same way as described above, the second wire170bis not brought into contact with the second protrusion140bof the second semiconductor chip120band the third semiconductor chip120c.

The third semiconductor chip120cmay be disposed on the second semiconductor chip120b. For example, the third semiconductor chip120cmay be attached to the second semiconductor chip120bvia the third adhesive film123. In other words, the third adhesive film123may be disposed between the second semiconductor chip120band the third semiconductor chip120c. The third adhesive film123may also be a DAF.

The third bump ball160cmay be directly connected to the third chip pad130cof the third semiconductor chip120c. In other words, a spacer ball may not be arranged on the third semiconductor chip120c. The third wire170cmay be connected to the third bump ball160cand the first bonding pad110a. In other words, the third chip pad130cand the first bonding pad110amay be electrically connected to each other by the third wire170c. The third wire170cmay be formed as a normal loop. In some embodiments, the normal loop may be in a wrinkle-free form. In addition, when the third wire170cdoes not extend in a direction away from the first bonding pad110a, the third wire170cmay be referred to as a normal loop. The normal loop according to some embodiments may be a forward loop or a reverse loop. When a start point of the wire bonding is a chip pad of a semiconductor chip, the loop is referred to as a forward loop. On the other hand, when the start point of the wire bonding is a bonding pad of a mounting substrate, the loop is referred to as a reverse loop. According to some embodiments, the third wire170cis not in contact with the third protrusion140cof the third semiconductor chip120c.

According to some embodiments, in the case of the third semiconductor chip120c, another semiconductor chip may no longer be stacked on the top thereof. Therefore, the third semiconductor chip120cmay be connected to the first bonding pad110aby the third wire170chaving the form of the normal loop. In some embodiments, a height H2of the third wire may be higher than the height H1of the first wire. Therefore, even if a spacer ball is not formed on the third the chip pad130cof the third semiconductor chip120c, the third wire170cmay not be in contact with the third protrusion140c.

The first chip pad130aof the first semiconductor chip120a, the second chip pad130bof the second semiconductor chip120b, and the third chip pad130cof the third semiconductor chip120care electrically connected to semiconductor elements inside the first semiconductor chip120a, the second semiconductor chip120b, and the third semiconductor chip120c, respectively. Since the first chip pad130a, the second chip pad130band the third chip pad130care electrically connected to the first bonding pad110a, the first chip pad130a, the second chip pad130band the third chip pad130cneed to be pads that perform a same role in the respective semiconductor chips. Therefore, the first semiconductor chip120a, the second semiconductor chip120b, and the third semiconductor chip120caccording to some embodiments may be semiconductor chips having a same configuration.

According to some embodiments, the first semiconductor chip120ato the third semiconductor chip120cmay be evenly stacked. In other words, assuming that the first semiconductor chip120ato the third semiconductor chip120care a semiconductor chip of a same size, the first semiconductor chip120ato the third semiconductor chip120cmay be stacked in the vertical direction. In other words, the first chip pad130aof the first semiconductor chip120amay vertically overlap the second semiconductor chip120band the third semiconductor chip120c. In addition, the second chip pad130bof the second semiconductor chip120bmay vertically overlap the first semiconductor chip120aand the third semiconductor chip120c. Further, the third chip pad130cof the third semiconductor chip120cmay vertically overlap the first semiconductor chip120aand the second semiconductor chip120b.

FIG. 6is an exemplary diagram for illustrating a semiconductor package according to some embodiments.

Referring toFIG. 6, the semiconductor package according to some embodiments may include a mounting substrate100, a first semiconductor chip120a, a second semiconductor chip120b, a third semiconductor chip120c, a first spacer ball150a, a second spacer ball150b, a first bump ball160a, a second bump ball160b, a third bump ball160c, a first wire170a, a second wire170b, a third wire170c, a first adhesive film121, a second adhesive film122, a third adhesive film123, and a molding resin180.

Each constituent element illustrated inFIG. 6may be similar to those ofFIGS. 1 and 5described above. Therefore, repeated descriptions will be omitted or briefly explained.

According to some embodiments, the mounting substrate100may include a first bonding pad110aand a second bonding pad110b. The first bonding pad110aand the second bonding pad110bmay be electrically connected to external terminals connected to an external device, respectively. For example, the first bonding pad110ais electrically connected to a first solder ball (not illustrated), and the second bonding pad110bmay be electrically connected to a second solder ball (not illustrated). Alternatively, the first bonding pad110aand the second bonding pad110bmay be, for example, ground pads, and may be electrically connected to ground lines in the mounting substrate100. The first bonding pad110aand the second bonding pad110bare, for example, illustrated as being arranged in an outer shell of the mounting substrate100, but the embodiments are not limited thereto.

According to some embodiments, the first semiconductor chip120aand the second semiconductor chip120bmay be connected to the first bonding pad110a. Further, the third semiconductor chip120cmay be connected to the second bonding pad110b. According to some embodiments, the first semiconductor chip120aand the second semiconductor chip120bmay be semiconductor chips of a same configuration, and the first semiconductor chip120aand the third semiconductor chip120cmay be semiconductor chips of different configurations. However, the embodiments are not limited thereto.

FIG. 6illustrates a configuration in which the first semiconductor chip120aand the second semiconductor chip120bare connected to the first bonding pad110a, and the third semiconductor chip120cis connected to the second semiconductor chip120b, but the embodiments are not limited thereto. For example, the first semiconductor chip120ais connected to the first bonding pad110a, and the second semiconductor chip120band the third semiconductor chip120cmay be connected to the second bonding pad110b. Those having ordinary skill in the technical field of the inventive concept may implement a semiconductor package including semiconductor chips having various arrangements.

FIG. 7is an exemplary diagram for illustrating a semiconductor package according to some embodiments.

Referring toFIG. 7, the semiconductor package according to some embodiments may include a mounting substrate100, a first semiconductor chip120a, a second semiconductor chip120b, a third semiconductor chip120c, a fourth semiconductor chip120d, a fifth semiconductor chip120e, a second spacer ball150b, a fourth spacer ball150d, a first bump ball160a, a second bump ball160b, a third bump ball160c, a fourth bump ball160d, a fifth bump ball160e, a first wire170a, a second wire170b, a third wire170c, a fourth wire170d, a fifth wire170e, a first adhesive film121, a second adhesive film122, a third adhesive film123, a fourth adhesive film124, a fifth adhesive film125, and a molding resin180.

Each constituent element illustrated inFIG. 6may be similar to those ofFIGS. 1, 5, and 6described above. Therefore, repeated descriptions will be omitted or briefly explained.

According to some embodiments, the first semiconductor chip120amay be disposed on the mounting substrate100. The mounting substrate100and the first semiconductor chip120amay be attached to each other via the first adhesive film121. The second semiconductor chip120bmay be disposed on the first semiconductor chip120a. The first semiconductor chip120aand the second semiconductor chip120bmay be attached to each other via the second adhesive film122. The third semiconductor chip120cmay be disposed on the second semiconductor chip120b. The second semiconductor chip120band the third semiconductor chip120cmay be attached to each other via the third adhesive film123. The fourth semiconductor chip120dmay be disposed on the third semiconductor chip120c. The third semiconductor chip120cand the fourth semiconductor chip120dmay be attached to each other via the fourth adhesive film124. The fifth semiconductor chip120emay be disposed on the fourth semiconductor chip120d. The fourth semiconductor chip120dand the fifth semiconductor chip120emay be attached to each other via the fifth adhesive film125.

The first semiconductor chip120ato the fifth semiconductor chip120emay be stacked in a zigzag form. In other words, the first chip pad130aof the first semiconductor chip120aand the third chip pad130cof the third semiconductor chip120cmay not be in contact with the second adhesive film122and the fourth adhesive film124, respectively. However, the second chip pad130bof the second semiconductor chip120band the fourth chip pad130dof the fourth semiconductor chip120dmay be in contact with the third adhesive film123and the fifth adhesive film125, respectively.

In other words, the first chip pad130aof the first semiconductor chip120a, the third chip pad130cof the third semiconductor chip120c, and the fifth chip pad130eof the fifth semiconductor chip120emay not vertically overlap the second semiconductor chip120band the fourth semiconductor chip120d. Further, the second chip pad130bof the second semiconductor chip120band the fourth chip pad130dof the fourth semiconductor chip120dmay overlap the first semiconductor chip120a, the third semiconductor chip120c, and the fifth semiconductor chip120ein the vertical direction.

According to some embodiments, the first bump ball160a, the second bump ball160b, and the third bump ball160cmay be directly connected to the first chip pad120aof the first semiconductor chip130a, the third chip pad130cof the third semiconductor chip120c, and the fifth chip pad130eof the fifth semiconductor chip120e, respectively. In other words, a spacer ball may not be separately connected to the top of the first semiconductor chip120a, the third semiconductor chip120c, and the fifth semiconductor chip120e.

The first wire170a, the third wire170c, and the fifth wire170emay be connected to the first bump ball160a, the third bump ball160c, and the fifth bump ball160e, respectively. Since the first chip pad130aof the first semiconductor chip120aand the second semiconductor chip120bdo not overlap in the vertical direction, the first wire170amay be formed as a normal loop. In other words, since the first chip pad130aof the first semiconductor chip120ahas a sufficient height for forming a normal loop at the top thereof, the first wire170amay be formed as a normal loop. Likewise, the third wire170cand the fifth wire170emay be formed as a normal loop.

According to some embodiments, the second spacer ball150band the fourth spacer ball150dmay be arranged on the second chip pad130bof the second semiconductor chip120band the fourth chip pad130dof the fourth semiconductor chip120d, respectively. Further, the second spacer ball150band the fourth spacer ball150dmay be connected to the second bump ball160band the fourth bump ball160d, respectively.

The second wire170band the fourth wire170dmay be connected to the second bump ball160band the fourth bump ball160d, respectively. Since the second chip pad130bof the second semiconductor chip120band the third semiconductor chip120coverlap in the vertical direction, the second wire170bmay be formed as a folded loop having a hook shape. In other words, since the second chip pad130bof the second semiconductor chip120bdoes not have a sufficient height to form a normal loop at the top, the second wire170bmay be formed as a folded loop. Similarly, the fourth wire170dmay be formed as a folded loop having a hook shape.

Even thoughFIG. 7illustrates that both the first wire170ato the fifth wire170eare connected to the first bonding pad110a, the embodiments are not limited thereto. For example, at least one of the first wire170ato the fifth wire170emay be connected to a bonding pad different from the first bonding pad110a.

FIGS. 8 to 16are intermediate stage diagrams for explaining a method of fabricating a semiconductor package according to some embodiments. Repeated or similar descriptions in view of the above embodiments will be omitted or briefly explained.

Referring toFIG. 8, the first semiconductor chip120ais disposed on the mounting substrate100. The first semiconductor chip120amay be attached to the mounting substrate100by the first adhesive film121. Subsequently, the first spacer ball150ahaving an appropriate size (for example, so that a first wire170ato be formed on the first spacer ball150adoes not come into contact with the first protrusion140aof the first semiconductor chip120aand the second semiconductor chip120b) is formed on the first chip pad130aof the first semiconductor chip120a. A person having ordinary knowledge in the technical field of the inventive concept may change the size of the first spacer ball150aas necessary.

Referring toFIGS. 9 and 10, a capillary920may form a first free air ball (FAB)910. By moving the capillary920in a first direction1001to press the first free air ball910, the first bump ball160amay be formed on the first spacer ball150a.

Referring toFIGS. 11 and 12, by moving the capillary920in a second direction1101away from the first bonding pad110a, a first portion (170a1ofFIG. 4) of the first wire170amay be formed. Subsequently, by moving the capillary920in a third direction1102, a fourth direction1103and a fifth direction1104approaching the first bonding pad110a, a second portion (170a2ofFIG. 4) of the first wire170amay be formed. That is, a folded loop having a hook shape may be formed through the processes ofFIGS. 9 to 12.

Referring toFIG. 13, the second semiconductor chip120bis disposed on the first semiconductor chip120a. The second semiconductor chip120bmay be attached to the first semiconductor chip120aby the second adhesive film122. Subsequently, a second spacer ball150bhaving an appropriate size is formed on the second chip pad130bof the second semiconductor chip120b. A person having ordinary knowledge in the technical field of the inventive concept may change the size of the second spacer ball150bas necessary.

Referring toFIG. 14, a second bump ball160band a second wire170bare formed in a manner similar to the method described above. In some embodiments, the second wire170bmay be formed as a folded loop having a hook shape.

Referring toFIGS. 15 and 16, the third semiconductor chip120cis disposed on the second semiconductor chip120b. The third semiconductor chip120cmay be attached to the second semiconductor chip120bby the second adhesive film122. Unlike the first semiconductor chip120aand the second semiconductor chip120b, no spacer ball is formed on the third chip pad130cof the third semiconductor chip120c. After the capillary920forms the second free air ball1510and presses the second free air ball1510against the third chip pad130cof the third semiconductor chip120cto form the third bump ball160c, a wire is formed in a direction approaching the first bonding pad110ato form a third wire170c. In some embodiments, the third wire170cmay be formed as a normal loop. Even thoughFIGS. 15 and 16illustrate that the third wire170cwhich is the normal loop is formed as a forward loop, the embodiments are not limited thereto.

Thereafter, the semiconductor package ofFIG. 5is fabricated by filling the molding resin180on the mounting substrate10, and the first semiconductor chip120ato the third semiconductor chip120c.

Although the method of fabricating the semiconductor package ofFIG. 5has been described with reference toFIGS. 8 to 16, the embodiments are not limited thereto. Those having ordinary skill in the technical field of the inventive concept will be able to fabricate the semiconductor package including the technical idea of the inventive concept by adding, changing or deleting a specific procedure as necessary.

While the inventive concept has been particularly shown and described with reference to exemplary embodiments thereof, it will be understood by those of ordinary skill in the art that various changes in form and details may be made therein without departing from the spirit and scope of the inventive concept as defined by the following claims. It is therefore desired that the above-described embodiments be considered in all respects as illustrative and not restrictive, reference being made to the appended claims rather than the foregoing description to indicate the scope of the invention.