AMPLIFIER WITH CASCODE ARRANGEMENT

An amplifier device, such as an operational amplifier device or unity gain buffer, may include a first input terminal, an inverting input terminal, a non-inverting input terminal, a reference voltage supply terminal, a negative voltage supply terminal, and an output terminal. The amplifier device may include one or more cascode arrangements, such as a first cascode arrangement coupled between the negative voltage supply terminal and the output terminal. A first transistor of the first cascode stage may be configured to receive a variable bias voltage at its gate terminal. A second transistor of the first cascode stage may be configured to receive a fixed bias voltage at its gate terminal. The variable bias voltage may correspond to a first input voltage supplied at the first input terminal.

TECHNICAL FIELD

Embodiments of the subject matter described herein relate generally to amplifiers, including operational amplifiers having one or more cascode stages.

BACKGROUND

Semiconductor devices find application in a wide variety of electronic components and systems. For example, semiconductor transistor-based amplifier devices are commonly used to amplify power, current, or voltage of signals provided at one or more inputs of such amplifier devices. A unity gain buffer, sometimes referred to as a “buffer amplifier” or “buffer” is a type of amplifier device that provides a voltage gain or current gain of exactly or approximately 1 between its input and its output. Transistors used to implement such amplifier devices typically have defined voltage limits. If such voltage limits are exceeded, the corresponding transistor may be damaged, which may negatively impact the operability of the corresponding amplifier device.

SUMMARY

A brief summary of various exemplary embodiments is presented below. Some simplifications and omissions may be made in the following summary, which is intended to highlight and introduce some aspects of the various exemplary embodiments, without limiting the scope. Detailed descriptions of an exemplary embodiment adequate to allow those of ordinary skill in the art to make and use these concepts will follow in later sections.

In an example embodiment, an amplifier device includes a first input terminal, a first voltage supply terminal, an output terminal, and a first cascode arrangement. The first input terminal may be configured to receive a first input voltage. The output terminal may be configured to provide an output voltage. The first cascode arrangement may be electrically coupled between the first voltage supply terminal and the output terminal. The first cascode arrangement may include a first transistor and a second transistor. The first transistor may have a first drain terminal electrically coupled to the output terminal, a first source terminal electrically coupled to the first drain terminal, and a first gate terminal that is configured to receive a variable bias voltage and to control the flow of current from the first drain terminal to the first source terminal, where the variable bias voltage corresponds to the first input voltage. The second transistor may have a second drain terminal electrically coupled to the first source terminal of the first transistor, a second source terminal electrically coupled to the first voltage supply terminal and to the second drain terminal, and a second gate terminal that is configured to receive a fixed bias voltage and to control the flow of current from the second drain terminal to the second source terminal.

In one or more embodiments, the amplifier device includes a current supply terminal configured to receive an input current, a node coupled to the second gate terminal of the second transistor, and a resistance coupled between the current supply terminal and the node. The second gate terminal of the second transistor may be configured to receive the fixed bias voltage via the node.

In one or more embodiments, the amplifier device includes a second voltage supply terminal and a voltage divider coupled between the first voltage supply terminal and the second voltage supply terminal. The second gate terminal of the second transistor may be configured to receive the fixed bias voltage via a node of the voltage divider

In one or more embodiments, the amplifier device includes a second voltage supply terminal, a first bipolar junction transistor (BJT) having a first emitter terminal coupled to the second voltage supply terminal, a first collector terminal coupled to the output terminal, and a first base terminal, a second BJT having a second emitter terminal coupled to the second voltage supply terminal, a second collector terminal, and a second base terminal coupled to the first base terminal of the first BJT, and a second cascode arrangement coupled between the second collector terminal of the second BJT and the first voltage supply terminal. The second cascode arrangement may be configured to receive at least the fixed bias voltage.

In one or more embodiments, the amplifier device includes a non-inverting input terminal configured to receive a second input voltage, a third BJT having a third emitter terminal, a third collector terminal coupled to a first bias node, and a third base terminal coupled to the non-inverting input terminal, and a third cascode arrangement coupled between the third emitter terminal of the third BJT and the first voltage supply terminal. The third cascode arrangement may be configured to receive at least the fixed bias voltage and the variable bias voltage.

In one or more embodiments, the amplifier device includes an inverting input terminal configured to receive a third input voltage, a fourth BJT having a fourth emitter terminal, a fourth collector terminal coupled to the first bias node, and a fourth base terminal coupled to the inverting input terminal, and a fourth cascode arrangement coupled between the fourth emitter terminal of the fourth BJT and the first voltage supply terminal. The fourth cascode arrangement may be configured to receive at least the fixed bias voltage and the variable bias voltage

In one or more embodiments, the amplifier device includes a third transistor having a third drain terminal electrically coupled to the first bias node, a third source terminal electrically coupled to the third drain terminal, and a third gate terminal that is coupled to the first input terminal, and a fifth cascode arrangement coupled between the third source terminal of the third transistor and the first voltage supply terminal. The fifth cascode arrangement may be configured to receive at least the fixed bias voltage and the variable bias voltage

In one or more embodiments, the first input voltage, the third input voltage, and the output voltage are each within 10% of the second input voltage.

In one or more embodiments, the second voltage supply terminal is configured to receive a first voltage, the first voltage supply terminal is configured to receive a second voltage, and the first voltage is at least 8 volts higher than the second voltage.

In one or more embodiments, the first input voltage, the second input voltage, and the third input voltage, are each greater than the second voltage and less than the first voltage.

In one or more embodiments, the first input voltage is configured to track the second input voltage with an offset of between 0 volts to 2 volts.

In an example embodiment, a unity gain buffer includes a first input terminal, a non-inverting input terminal, a first voltage supply terminal, an output terminal, and a first cascode arrangement. The first input terminal may be configured to receive a first input voltage. The non-inverting input terminal may be configured to receive a second input voltage. The first input voltage may track the second input voltage. The first voltage supply terminal may be configured to receive a first supply voltage. The output terminal may be configured to provide an output voltage. The first cascode arrangement may be electrically coupled between the first voltage supply terminal and the output terminal. The first cascode arrangement may include a first transistor and a second transistor. The first transistor may be coupled to the output terminal and having a first gate terminal that is configured to receive a variable bias voltage. The variable bias voltage may correspond to the first input voltage. The second transistor may be coupled between the first transistor and the first voltage supply terminal and having a second gate terminal that is configured to receive a fixed bias voltage. The first transistor may be configured to prevent a voltage differential across the second transistor from exceeding a predefined voltage threshold.

In one or more embodiments, the unity gain buffer includes a current supply terminal configured to receive an input current, a node coupled to the second gate terminal of the second transistor, and resistance coupled between the current supply terminal and the node. The second gate terminal of the second transistor may be configured to receive the fixed bias voltage via the node.

In one or more embodiments, the unity gain buffer includes a second voltage supply terminal configured to receive a second supply voltage that is greater than the first supply voltage, and a voltage divider coupled between the first voltage supply terminal and the second voltage supply terminal. The second gate terminal of the second transistor may be configured to receive the fixed bias voltage via a node of the voltage divider

In one or more embodiments, the unity gain buffer includes a second voltage supply terminal configured to receive a second supply voltage that is greater than the first supply voltage, a first bipolar junction transistor (BJT) having a first emitter terminal coupled to the second voltage supply terminal, a first collector terminal coupled to the output terminal, and a first base terminal, a second BJT having a second emitter terminal coupled to the second voltage supply terminal, a second collector terminal, and a second base terminal coupled to the first base terminal of the first BJT, and a second cascode arrangement coupled between the second collector terminal of the second BJT and the first voltage supply terminal. The second cascode arrangement may be configured to receive at least the fixed bias voltage.

In one or more embodiments, the unity gain buffer includes a third BJT having a third emitter terminal, a third collector terminal coupled to a first bias node, and a third base terminal coupled to the non-inverting input terminal, and a third cascode arrangement coupled between the third emitter terminal of the third BJT and the first voltage supply terminal. The third cascode arrangement may be configured to receive at least the fixed bias voltage and the variable bias voltage.

In one or more embodiments, the unity gain buffer includes a third BJT having a third emitter terminal, a third collector terminal coupled to a first bias node, and a third base terminal coupled to the non-inverting input terminal, and a third cascode arrangement coupled between the third emitter terminal of the third BJT and the first voltage supply terminal. The third cascode arrangement may be configured to receive at least the fixed bias voltage and the variable bias voltage.

In one or more embodiments, the unity gain buffer includes an inverting input terminal configured to receive a third input voltage, a fourth BJT having a fourth emitter terminal, a fourth collector terminal coupled to the first bias node, and a fourth base terminal coupled to the inverting input terminal, and a fourth cascode arrangement coupled between the fourth emitter terminal of the fourth BJT and the first voltage supply terminal. The fourth cascode arrangement may be configured to receive at least the fixed bias voltage and the variable bias voltage.

In one or more embodiments, the unity gain buffer includes a third transistor coupled to the first bias node and having a third gate terminal that is coupled to the first input terminal, and a fifth cascode arrangement coupled between the third transistor and the first voltage supply terminal. The fifth cascode arrangement may be configured to receive at least the fixed bias voltage and the variable bias voltage.

In one or more embodiments, the first input voltage is configured to track the second input voltage with an offset of between 0 volts to 2 volts.

In an example embodiment, control circuitry includes an amplifier transistor, a reference transistor, a switch, and a unity gain buffer. The amplifier transistor may be configured to receive an RF input signal for amplification. The amplifier transistor and the reference transistor may be formed on the same semiconductor die. The switch may have an output coupled to a control terminal of the amplifier transistor. The unity gain buffer may include an input terminal, a non-inverting input terminal, a voltage supply terminal, an output terminal, and a cascode arrangement. The input terminal may be configured to receive a first input voltage. The non-inverting input terminal may be coupled to the reference transistor and configured to receive a second input voltage. The first input voltage may track the second input voltage. The voltage supply terminal may be configured to receive a supply voltage. The output terminal may be configured to provide an output voltage to the control terminal of the amplifier transistor via the switch. The cascode arrangement may be electrically coupled between the voltage supply terminal and the output terminal. The cascode arrangement may include a first transistor and a second transistor. The first transistor may be coupled to the output terminal and having a first gate terminal that is configured to receive a variable bias voltage. The variable bias voltage may correspond to the first input voltage. The second transistor may be coupled between the first transistor and the voltage supply terminal and having a second gate terminal that is configured to receive a fixed bias voltage. The first transistor may be configured to prevent a voltage differential across the second transistor from exceeding a predefined voltage threshold.

DETAILED DESCRIPTION

The following detailed description is merely illustrative in nature and is not intended to limit the embodiments of the subject matter or the application and uses of such embodiments. Furthermore, there is no intention to be bound by any expressed or implied theory presented in the preceding technical field, background, or the following detailed description.

For simplicity and clarity of illustration, the drawing figures illustrate the general manner of construction, and descriptions and details of well-known features and techniques may be omitted to avoid unnecessarily obscuring the invention. Additionally, elements in the drawing figures are not necessarily drawn to scale. For example, the dimensions of some of the elements or regions in the figures may be exaggerated relative to other elements or regions to help improve understanding of embodiments of the invention.

The terms “first,” “second,” “third,” “fourth” and the like in the description and the claims, if any, may be used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the terms so used are interchangeable under appropriate circumstances such that the embodiments of the invention described herein are, for example, capable of operation in sequences other than those illustrated or otherwise described herein. Furthermore, the terms “comprise,” “include,” “have” and any variations thereof, are intended to cover non-exclusive inclusions, such that a process, method, article, or apparatus that comprises a list of elements is not necessarily limited to those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. The term “coupled,” as used herein, is defined as directly or indirectly connected in an electrical or non-electrical manner. As used herein the terms “substantial” and “substantially” mean sufficient to accomplish the stated purpose in a practical manner and that minor imperfections, if any, are not significant for the stated purpose. As used herein, the words “exemplary” and “example” mean “serving as an example, instance, or illustration.” Any implementation described herein as exemplary or an example is not necessarily to be construed as preferred or advantageous over other implementations.

Directional references such as “top,” “bottom,” “left,” “right,” “above,” “below,” and so forth, unless otherwise stated, are not intended to require any preferred orientation and are made with reference to the orientation of the corresponding figure or figures for purposes of illustration.

For the sake of brevity, conventional semiconductor fabrication techniques may not be described in detail herein. In addition, certain terms may also be used herein for reference only, and thus are not intended to be limiting. For instance, the terms “first”, “second”, and other such numerical terms referring to structures do not imply a sequence or order unless clearly indicated by the context.

Various embodiments described herein relate to a semiconductor transistor-based amplifier device (i.e., “amplifier”) that includes a cascode arrangement configured to prevent or mitigate conditions in which one or more voltage limits of one or more transistors of the amplifier are exceeded. In one or more embodiments, the amplifier device may be an operational amplifier that is configurable as a unity gain buffer (e.g., having a voltage gain of around 1; having a voltage gain of around 0 dB). For a given amplifier, if the voltage difference between any two input terminals, output terminals, or supply terminals of the amplifier exceeds the inter-terminal voltage limits of one or more transistors of the amplifier, such transistors could be damaged. To address this problem, in one or more embodiments, an amplifier includes one or more cascode arrangements in which respective sets series-connected transistors (i.e., transistors that are coupled together source-to-drain along a single path) are coupled between terminals of the amplifier, where respective voltage differentials between such terminals may exceed one or more inter-terminal voltage limits of a single transistor of the series-connected transistors. In one or more embodiments, each of the series-connected transistors may be metal oxide semiconductor (MOS) transistors. Gate terminals of the transistors of these cascode arrangements may be coupled to respective control nodes configured to bias the gate terminals to respective cascode bias voltages. The cascode bias voltages at the control nodes may be set such that the voltage between terminals of any given transistor of the amplifier may be reduced to be within corresponding voltage limits of that transistor, including gate-to-source voltage (VGS), drain-to-source voltage (VDS), and the gate-to-drain voltage (VGD) voltage limits. Thus, by including such cascode arrangements in an amplifier, such as an operational amplifier, the likelihood of transistors of the amplifier being damaged due to over-voltage may be advantageously reduced. At least one of the cascode bias voltages may be a variable cascode bias voltage corresponding to a tracking voltage. The tracking voltage may be equal to a non-inverting input voltage of the amplifier device or offset from the non-inverting input voltage by a fixed amount (e.g., between around 0 V to around 2 V), in accordance with various embodiments. The tracking voltage may be equal to an output voltage of the amplifier device or offset from the output voltage by a fixed amount (e.g., between around 0 V to around 2 V), in accordance with various embodiments.

In one or more embodiments, the amplifier device includes a first cascode arrangement coupled between an output terminal of the amplifier device and a negative voltage supply terminal of the amplifier device. The first cascode arrangement may include two or more series-connected nMOS transistors (three, as a non-limiting example) where at least one of the series-connected nMOS transistors receives a variable bias voltage corresponding to the tracking voltage and at least one other of the series-connected nMOS transistors receives a fixed bias voltage (e.g., from a node of a voltage divider, as a non-limiting example).

In one or more embodiments, the amplifier device includes a one or more other cascode arrangements in addition to the first cascode arrangement, where each such cascode arrangement is coupled between the negative voltage supply terminal of the amplifier device and one or more other terminals or nodes of the amplifier device (e.g., a reference voltage supply terminal, a positive voltage supply terminal, a non-inverting input terminal, an inverting input terminal, and/or the like). Each cascode arrangement may be configured to protect one or more transistors or other devices of the amplifier device by limiting the voltage provided to such devices (e.g., provided to the drain terminals of such devices), thereby preventing corresponding inter-terminal voltage limits of such devices from being exceeded. Each cascode arrangement may be configured to receive at least one fixed bias voltage. At least a subset of the cascode arrangements may be configured to receive (e.g., in addition to the fixed bias voltage) a variable bias voltage corresponding to the tracking voltage.

FIG.1is a block diagram of control circuitry100that is configured to selectively provide a direct current (DC) bias to a gate terminal of an amplifier transistor118. As shown, the control circuitry100may include a sense amplifier102, an operational amplifier104, a first switch106, a second switch108, a capacitor110, a first digital-to-analog convertor (DAC)112, a second DAC114, and a sense resistor140. The control circuitry100may be configured to control a reference transistor116and the amplifier transistor118. For example, the control circuitry100may be configured as bias circuitry that selectively provides a direct current (DC) bias voltage to the gate of the amplifier transistor118based, at least in part, on a voltage detected by the sense amplifier102at a drain terminal of the reference transistor116. As will be described, various elements of the control circuitry100may be coupled to one or more of a positive voltage supply120configured to supply a positive voltage VCC, a negative voltage supply124configured to supply a negative voltage VEE, (sometimes referred to herein as a “supply voltage” VEE) one or more reference voltage supplies122configured to provide a reference voltage VGND, a first control signal source126configured to supply a variable control signal TX_EN_A, or a second control signal source128configured to supply a variable control signal TX_EN_B. In one or more embodiments, each reference voltage supply122corresponds to a ground node and the reference voltage VGNDis at or around 0 V. It should be understood that “ground nodes” herein may not necessarily correspond to “earth ground” but may instead correspond to “signal ground” or another suitable reference potential, in accordance with various embodiments. Herein, the “gate terminal” or “base terminal” of a transistor may sometimes be referred to as a “control terminal”, and the “drain terminal” and “source terminal” or “emitter terminal” and “collector terminal” of a transistor may sometimes be referred to as “current-carrying terminals.”

The sense amplifier102may be an operational amplifier having a positive voltage supply terminal coupled directly to the positive voltage supply120, a negative voltage supply terminal coupled directly to the negative voltage supply124, an inverting input coupled to an output of the first DAC112, a non-inverting input coupled to a node138disposed between the sense resistor140and the drain of the reference transistor116, and an output coupled to a node136that is coupled to an input of the second DAC114and the gate of the reference transistor116. In or more embodiments, the voltage VCCsupplied by the positive voltage supply120may be around 5 V. In one or more embodiments, the voltage VEEsupplied by the negative voltage supply124may be around −8 V.

The operational amplifier104may be configured as a unity gain buffer (sometimes referred to as a “voltage buffer”) with a gain of 1 or around 1 (e.g., a gain of 0 dB or around 0 dB). That is, the operational amplifier104may be configured such that the voltage at the non-inverting input of the operational amplifier104may be equal to or approximately equal to the voltage at the output of the operational amplifier104. The operational amplifier104may include a positive voltage supply terminal coupled directly to the positive voltage supply120, a negative voltage supply terminal coupled directly to the negative voltage supply124, a non-inverting input coupled to the output of the second DAC114, an output coupled to a node134, and an inverting input coupled to the output of the operational amplifier104via the node134.

The first DAC112may include an input terminal coupled to the positive voltage supply120, an output terminal coupled to the inverting input of the sense amplifier102, and a control input at which first digital control signals are received, where the first digital control signals determine the voltage output by the first DAC112relative to the voltage VCCreceived from the positive voltage supply120. For example, the voltage output by the first DAC112may be between equal to the positive supply voltage VCCminus around 0.2 V and around 1 V (depending on the values of the first digital control signals). Herein, an example amount that is said to be “around” or “approximately” a given value is considered to be within +/−10% of the given value unless otherwise indicated.

The second DAC114may include an input terminal coupled to each of the output of the sense amplifier102and the gate of the reference transistor116via the node136, an output terminal coupled to a non-inverting input of the operational amplifier104, and a control input at which second digital control signals are received, where the second digital control signals determine the voltage output by the second DAC114relative to the voltage at the node136(i.e., the voltage at the output of the sense amplifier102). For example, given a voltage of around −3 V to around −1.5 V output by the sense amplifier102, the voltage output by the second DAC114may be in a range of around −6.5 V to around −1 V or in a range of around −8 V to around 0 V (depending, at least in part, on the values of the second digital control signals).

The capacitor110may be coupled between the node134and the negative voltage supply124. According to various embodiments, the capacitor110may have a capacitance in a range of around 1 nF to around 1 μF. For example, the capacitor110may improve the transient response at the node134. The sense resistor140may be coupled between the node138and the positive voltage supply120.

The reference transistor116may include a drain terminal coupled to the node138, a source terminal coupled to the reference voltage supply122, and a gate terminal coupled to the node136. The amplifier transistor118may include a drain terminal coupled to an output130, a source terminal coupled to the reference voltage supply122, and a gate terminal coupled to the node132. The first switch106may include an input terminal coupled to the node134, an output terminal coupled to the node132, and a control terminal coupled to the first control signal source126and configured to receive the variable control signal TX_EN_A. The second switch108may include an input terminal coupled to the node132, an output terminal coupled to the negative voltage supply124, and a control terminal coupled to the second control signal source128and configured to receive the variable control signal TX_EN_B.

A radio frequency (RF) input signal RFIN may be supplied by an RF signal source142to the gate of the amplifier transistor118via the node132. The RF input signal RFIN may be amplified by the amplifier transistor118to produce an RF output signal RFOUT at the output130.

The sense amplifier102may be configured to compare a first voltage output by the first DAC112(e.g., in a range of around 4 V to around 5.2 V) to a second voltage at the node138(e.g., in a range of around 8 V to around 10 V), corresponding to the voltage at the drain terminal of the reference transistor116, then output a third voltage (e.g., in a range of around 2.8 V to around 5 V), based on this comparison, at the node136. For example, the third voltage output by the sense amplifier102may be equal to the difference between the first voltage and the second voltage received by the sense amplifier102. The second DAC114may apply a voltage offset to the third voltage output by the sense amplifier102to produce a fourth voltage at its output (e.g., in a range of around −6.5 V to around −1 V or in a range of around −8 V to around 0 V), which the DAC114may provide to the non-inverting input of the operational amplifier104. As indicated above, operational amplifier104may be a unity gain amplifier that is configured to output a voltage that is equal to or approximately equal to the voltage received at its non-inverting input. That is, the operational amplifier104may receive the fourth voltage at its non-inverting input and may output the fourth voltage (e.g., at the node134).

The output of the operational amplifier104may be selectively coupled to the gate of the amplifier transistor118via the first switch106and a node132disposed between the output of the first switch106and the gate of the amplifier transistor118. The first switch106may be selectively opened and closed based on the variable control signal TX_EN_A provided to the control terminal of the first switch106by the first control signal source126. The second switch108may be selectively opened and closed based on the variable control signal TX_EN_B provided to the control terminal of the second switch108by the second control signal source128. Herein, a switch or transistor is considered to be “closed”, “on”, or “activated” when a relatively low impedance path is provided between the input terminal of the switch and the output terminal of the switch, permitting electric current to flow between its input terminal and its output terminal. Herein, a switch or transistor is considered to be “open”, “off” or “deactivated” when a relatively high impedance path is provided between its input terminal and its output terminal, such that the flow of current is reduced or blocked therebetween. For example, herein, a bipolar junction transistor (BJT) is considered to be “on”, when operating in its saturation region, and is considered to be “off” when operating in its cutoff region.

In one or more embodiments, the first control signal source126and the second control signal source128may be configured such that the first control signal source126only closes the first switch106(e.g., by asserting the variable control signal TX_EN_A) after the second control signal source128has opened the second switch108(e.g., by deasserting the variable control signal TX_EN_B), and such that the second control signal source128only closes the second switch108(e.g., by asserting the variable control signal TX_EN_B) after the first control signal source126has opened the first switch106(e.g., by deasserting the variable control signal TX_EN_A). Such configuration of the first control signal source126and the second control signal source128may prevent the first switch106and the second switch108from being closed simultaneously and may thereby prevent undesirable shoot-through current through the first switch106and the second switch108. The variable control signals TX_EN_A and TX_EN_B may be at around 1.8 V when asserted and around 0 V when deasserted.

When the first switch106is open and the second switch108is closed, the gate of the amplifier transistor118is coupled to the negative voltage supply124and receives the negative voltage VEE(e.g., around −8 V), which causes the amplifier transistor118to be open (disabled). When the first switch106is closed and the second switch108is open, the gate of the amplifier transistor118is coupled to the output of the operational amplifier104(e.g., configured to provide a voltage in a range of around −6.5 V to around −1 V or in a range of around −8 V to around 0 V), where the voltage output by the operational amplifier104provides as a DC bias at the gate of the amplifier transistor118sufficient to activate the amplifier transistor118(e.g., when RFIN is also sufficiently high).

In one or more embodiments, the reference transistor116and the amplifier transistor118may each be formed on the same semiconductor die and in close proximity to one another, such that the reference transistor116exhibits process and temperature dependencies that are similar to those of the amplifier transistor118. As a non-limiting example, the reference transistor116and the amplifier transistor118may each be Gallium Nitride (GaN) field effect transistors (FETs) formed on the same GaN die or GaN-on-SiC die as non-limiting examples. Process and temperature dependencies exhibited by the reference transistor116affect the voltage at the node138, which causes corresponding changes in the voltage output by the sense amplifier102, observable at the node136, which causes corresponding changes in the voltage provided at the gate of the amplifier transistor118(i.e., the “bias voltage”) when the first switch106is closed. In this way, process and temperature dependencies of the amplifier transistor118may be accounted for by dynamically adjusting the bias voltage supplied to the gate of the amplifier transistor118based on the similar process and temperature dependencies of the reference transistor116.

In one or more embodiments, the non-inverting input of the operational amplifier104may receive a voltage in a range of around −6.5 V to around −1 V or in a range of around −8 V to around 0 V from the output of the second DAC114, while the positive voltage supply terminal of the operational amplifier104is configured to receive the positive voltage VCC, which may be at or around 5 V, the negative voltage supply terminal of the operational amplifier104is configured to receive the negative voltage VEE, which may be at or around −8 V, and a reference voltage supply terminal configured to receive a reference voltage VRTGND, which may be around 0 V. Thus, the voltage differential between any of the inverting input terminal, non-inverting input terminal or output terminal of the operational amplifier104and the voltage supply terminals of the operational amplifier104, or between the voltage supply terminals themselves, may be as high as 8 V or higher, in accordance with one or more embodiments. Conventional MOS transistor devices typically have gate-source, gate-drain, and drain-source breakdown voltages that are respectively lower than these values (e.g., such breakdown voltages may typically be around 2.5 V). In one or more embodiments, to prevent or mitigate damage to transistor devices of the operational amplifier104due to over-voltage, the operational amplifier104may include one or more cascode arrangements that are configured to limit the voltage drop across any two terminals of such transistor devices to be below corresponding, predefined breakdown voltage thresholds (sometimes referred to herein as “voltage limits”) of those transistor devices, as described below.

FIGS.2and3show block diagrams corresponding to respective first and second portions200-1,200-2of an amplifier device200(sometimes referred to herein as the “amplifier200”) having an extended voltage range due, at least in part, to one or more cascode arrangements coupled between terminals of the amplifier device200. In one or more embodiments, the amplifier device200may be implemented as the operation amplifier104of the control circuitry100ofFIG.1. It should be understood that, with reference to arrangements of components of the amplifier device200, the term “coupled” should be understood to mean at least “electrically coupled” unless otherwise indicated.

Referring simultaneously toFIG.2andFIG.3, the amplifier device200may include p-channel MOS (pMOS) transistors206,214,216, n-channel MOS (nMOS) transistors208,210,225,314,316,318,320,326,328,332,334,338,340,346,352,354,356,366,368,370,372,374,376,378,380,382,394,395,396,398,399, bipolar junction transistors (BJTs)204,212,218,222,224,344,348,358,360,362,364,386,388,390,392, and resistances312,322,330,336,342,350,384. Any of the resistances312,322,330,336,342,350,384may be implemented via a single resistor or other electrically resistive element or multiple resistors or electrically resistive elements in accordance with various embodiments. In one or more embodiments, each of the BJTs204,212,218,222,224,344,348,360,362,386,388,390,392may be PNP BJTs. In one or more embodiments, each of the BJTs358,364may be NPN BJTs. In one or more embodiments, the transistors206,208,210,214,216,225,314,316,318,320,326,328,332,334,338,340,346,352,354,356,366,368,370,372,374,376,378,380,382,394,395,396,398,399may each have VGS, VDS, and VGDvoltage limits of around 3 V, such that inter-terminal voltages above around 3 V may stress or damage such transistors.

As will be described, the amplifier device200may be coupled to a positive voltage supply configured to provide a positive voltage VCCvia a positive voltage supply terminal220, a reference voltage supply configured to provide a reference voltage VRTGNDvia a reference voltage supply terminal202, a negative voltage supply configured to supply a negative voltage VEEvia the negative voltage supply terminal324, and a current supply configured to provide a bias reference current ISINKvia a terminal302. In one or more embodiments, the bias reference current ISINKmay establish the bias current level for each of the nMOS transistors having gate terminals coupled to the nodes315,317(i.e., the nMOS transistors314,316,318,320,326,328,356,376,370,396). In one or more embodiments, the negative voltage VEEand the corresponding negative voltage supply may correspond to the negative voltage VEEand the corresponding negative voltage supply124ofFIG.1. In one or more embodiments, the positive voltage VCCand the corresponding positive voltage supply may correspond to the positive voltage VCCand the corresponding positive voltage supply120ofFIG.1. In one or more embodiments, the reference voltage VRTGNDand the corresponding reference voltage supply may correspond to the reference voltage VGNDand the corresponding reference voltage supply122ofFIG.1. In one or more embodiments, VEEmay be at or around −8 V, VCCmay be at or around 5 V, VRTGNDmay be at or around 0 V, and ISINKmay be at or around 20 μA.

The amplifier device200may include an inverting input terminal304configured to receive an inverting input voltage signal VINN. The amplifier device may include a non-inverting input terminal306configured to receive a non-inverting input voltage signal VINP. The amplifier device200may include an output configured to provide an output voltage signal VOUT. In one or more embodiments, the amplifier device200may be an operational amplifier. In one or more embodiments, the amplifier device200may be configured as a unity gain buffer, such that VOUTis equal to or approximately equal to VINP. In one or more embodiments in which the amplifier device200is configured as a unity gain buffer, the inverting input terminal304may be coupled directly to the output terminal310, such that VINNis equal to or approximately equal to VOUT.

The amplifier device200may include a tracking voltage input terminal308configured to receive a tracking voltage VTRK. In one or more embodiments, the tracking voltage VTRKmay track the non-inverting input voltage VINP, such that VTRKis maintained at a fixed or approximately fixed voltage level of between around 0 V to around 2 V offset from (e.g., above) VINP. For example, the tracking voltage input terminal308may be coupled to the non-inverting input terminal306in one or more such embodiments. In one or more other embodiments, the tracking voltage VTRKmay track the non-inverting output voltage VOUT, such that VTRKis maintained at a fixed or approximately fixed voltage level of between around 0 V to around 2 V offset from (e.g., above) VOUT. For example, the tracking input voltage terminal308may be coupled to the output terminal310in one or more such embodiments. Herein, a voltage or other value is considered to be “fixed” when that voltage or value has little (e.g., less than 10%) or no variation (e.g., during normal operation of a corresponding circuit or device).

As shown inFIG.2, the BJT204may include an emitter terminal coupled to the positive voltage supply terminal220, a base terminal coupled to the base terminal of the BJT212and to a node213, and a collector terminal coupled to the source terminal of the pMOS transistor206. The BJT212may include an emitter terminal coupled to the positive voltage supply terminal220, a base terminal coupled to the base terminal of the BJT204and to the node213, and a collector terminal coupled to the node213. The BJT218may include an emitter terminal coupled to a node217, a base terminal coupled to the reference voltage supply terminal202, and a collector terminal coupled to a node228(i.e., coupled to the second portion200-2of the amplifier device200, shown inFIG.3, via the node228), denoted here as “B”. The BJT222may include an emitter terminal coupled to the positive voltage supply terminal220, a base terminal coupled to the node213, and a collector terminal coupled to the node213. That is, the base terminal of the BJT222is connected to the collector terminal of the BJT222. The BJT224may include an emitter terminal coupled to the node213, a base terminal coupled to the reference voltage supply terminal202, and a collector terminal coupled to a node230(i.e., coupled to the second portion200-2of the amplifier device200, shown inFIG.3, via the node230), denoted here as “C”. The BJTs218,224may be arranged in respective common base configurations. The BJTs204,222may be arranged in respective common emitter configurations. The BJT212may be arranged in a diode-connected configuration (e.g., the base terminal of the BJT212is connected to its collector terminal). The BJTs204and222may each operate as respective current sources that supply currents at their respective collector terminals. For example, the respective magnitudes of these currents are scaled based on the current magnitude through the diode-connected BJT212and respective ratios of relative transistor areas, where such ratios may be respectively defined as the area of the BJT204divided by the area of the BJT212and the area of the BJT222divided by the area of the BJT212.

The pMOS transistor206may include a source terminal coupled to the collector terminal of the BJT204, a gate terminal coupled to a node207, and a drain terminal coupled to the node207. That is, the gate terminal of the pMOS transistor206may be coupled to the drain terminal of the pMOS transistor206, such that the pMOS transistor206is configured as a diode-connected transistor. Current flow between the source and drain terminals of the pMOS transistor206may be controlled by the voltage at the node207.

The pMOS transistor214may include a source terminal coupled to the node213, a gate terminal coupled to a node207, and a drain terminal coupled to the node215. Current flow between the source and drain terminals of the pMOS transistor214may be controlled by the voltage at the node207.

The pMOS transistor216may include a source terminal coupled to the node215, a gate terminal coupled to a node217, and a drain terminal coupled to the node217. That is, the gate terminal of the pMOS transistor216may be coupled to the drain terminal of the pMOS transistor216, such that the pMOS transistor216is configured as a diode-connected transistor. Current flow between the source and drain terminals of the pMOS transistor216may be controlled by the voltage at the node217.

The nMOS transistor208may include a drain terminal coupled to the node207, a gate terminal coupled to the node215, and a source terminal coupled to the drain terminal of the nMOS transistor210. Current flow between the source and drain terminals of the nMOS transistor208may be controlled by the voltage at the node215.

The nMOS transistor210may include a drain terminal coupled to the source terminal of the nMOS transistor208, a gate terminal coupled to the node217, and a source terminal coupled to the drain terminal of the nMOS transistor225. Current flow between the source and drain terminals of the nMOS transistor210may be controlled by the voltage at the node217.

The nMOS transistor225may include a drain terminal coupled to the source terminal of the nMOS transistor210, a gate terminal coupled to the reference voltage supply terminal202, and a source terminal coupled to the node226(i.e., coupled to the second portion200-2of the amplifier device200, shown inFIG.3, via the node226), denoted here as “A”. Current flow between the source and drain terminals of the nMOS transistor225may be controlled by the voltage at the reference voltage supply terminal202(i.e., by VRTGND) and may be at least partly dependent on the reference current ISINK. For example, the nMOS transistors314,316,318,328are arranged as a cascode current mirror, such that the reference current ISINKsupplied via the terminal302causes a corresponding current (equal to or approximately equal to the reference current ISINK) to flow from the terminal226to the terminal324via at least the transistors204,206,208,210,225,316,320,334,338.

As shown inFIG.3, the BJT344may include an emitter terminal coupled to the node228, a base terminal coupled to the node341, and a collector terminal coupled to the emitter terminal of the BJT348. The BJT348may include an emitter terminal coupled to the collector terminal of the BJT344, a base terminal coupled to the negative voltage supply terminal324, and a collector terminal coupled to the negative voltage supply terminal324. The BJT358may include an emitter terminal coupled to the node357, a base terminal coupled to the inverting input terminal304, and a collector terminal coupled to the node228. The BJT360may include an emitter terminal coupled to the node230, a base terminal coupled to the node357, and a collector terminal coupled to the node381. The BJT362may include an emitter terminal coupled to the node230, a base terminal coupled to the node361, and a collector terminal coupled to the drain terminal of the nMOS transistor378. The BJT364may include an emitter terminal coupled to the node361, a base terminal coupled to the non-inverting input terminal306, and a collector terminal coupled to the node228. The BJT386may include an emitter terminal coupled to the reference voltage supply terminal202, a base terminal coupled to the node391, and a collector terminal coupled to the node391. That is, the base terminal of the BJT386may be coupled to the collector terminal of the BJT386, such that the BJT386is configured as a diode-connected transistor. The BJT388may include an emitter terminal coupled to the reference voltage supply terminal202, a base terminal coupled to the node391, and a collector terminal coupled to the node367. The BJT390may include an emitter terminal coupled to the reference voltage supply terminal202, a base terminal coupled to the node391, and a collector terminal coupled to the output terminal310. The BJT392may include an emitter terminal coupled to the node391, a base terminal coupled to the node367, and a collector terminal coupled to the negative voltage supply terminal324.

The nMOS transistor314may include a drain terminal coupled to the node315, a gate terminal coupled to the node315, and a source terminal coupled to the node317. That is, the gate terminal of the nMOS transistor314may be coupled to the drain terminal of the nMOS transistor314, such that the nMOS transistor314is configured as a diode-connected transistor. Current flow between the source and drain terminals of the nMOS transistor314may be controlled by the voltage at the node315(e.g., which is dependent on the current ISINK). For example, the nMOS transistor314may have a VGSthat supports a drain-to-source current (IDS) that is equal to or approximately equal to the current ISINK(e.g., 20 μA).

The nMOS transistor316may include a drain terminal coupled to the source terminal of the nMOS transistor334, a gate terminal coupled to the node315, and a source terminal coupled to drain terminal of the nMOS transistor320. Current flow between the source and drain terminals of the nMOS transistor316may be controlled by the voltage at the node315(e.g., which is dependent on the current ISINK).

The nMOS transistor318may include a drain terminal coupled to the node317, a gate terminal coupled to the node317, and a source terminal coupled to negative voltage supply terminal324. That is, the gate terminal of the nMOS transistor318may be coupled to the drain terminal of the nMOS transistor318, such that the nMOS transistor318is configured as a diode-connected transistor. Current flow between the source and drain terminals of the nMOS transistor318may be controlled by the voltage at the node317. For example, the nMOS transistor318may have a VGSthat supports an IDSthat is equal to or approximately equal to the current ISINK(e.g., 20 μA).

The nMOS transistor320may include a drain terminal coupled to the source terminal of the nMOS transistor316, a gate terminal coupled to the node317, and a source terminal coupled to negative voltage supply terminal324. Current flow between the source and drain terminals of the nMOS transistor320may be controlled by the voltage at the node317.

The nMOS transistor326may include a drain terminal coupled to the source terminal of the nMOS transistor328, a gate terminal coupled to the node317, and a source terminal coupled to negative voltage supply terminal324. Current flow between the source and drain terminals of the nMOS transistor326may be controlled by the voltage at the node317.

The nMOS transistor328may include a drain terminal coupled to the source terminal of the nMOS transistor332, a gate terminal coupled to the node315, and a source terminal coupled to drain terminal of the nMOS transistor326. Current flow between the source and drain terminals of the nMOS transistor328may be controlled by the voltage at the node315.

The nMOS transistor332may include a drain terminal coupled to the source terminal of the nMOS transistor346, a gate terminal coupled to the node335, and a source terminal coupled to drain terminal of the nMOS transistor328. Current flow between the source and drain terminals of the nMOS transistor332may be controlled by the voltage at the node335.

The nMOS transistor334may include a drain terminal coupled to the source terminal of the nMOS transistor338, a gate terminal coupled to the node335, and a source terminal coupled to drain terminal of the nMOS transistor316. Current flow between the source and drain terminals of the nMOS transistor334may be controlled by the voltage at the node335.

The nMOS transistor338may include a drain terminal coupled to the node226, a gate terminal coupled to the node337, and a source terminal coupled to drain terminal of the nMOS transistor334. Current flow between the source and drain terminals of the nMOS transistor338may be controlled by the voltage at the node337.

The nMOS transistor340may include a drain terminal coupled to the node228, a gate terminal coupled to the tracking voltage input terminal308, and a source terminal coupled to the node341. Current flow between the source and drain terminals of the nMOS transistor340may be controlled by the voltage at the tracking voltage input terminal308(i.e., by VTRK).

The nMOS transistor346may include a drain terminal coupled to the node341, a gate terminal coupled to the node347, and a source terminal coupled to the drain terminal of the nMOS transistor332. The node347may be coupled to the node228. Current flow between the source and drain terminals of the nMOS transistor346may be controlled by the voltage at the node347.

The nMOS transistor352may include a drain terminal coupled to the node357, a gate terminal coupled to the node347, and a source terminal coupled to the drain terminal of the nMOS transistor354. Current flow between the source and drain terminals of the nMOS transistor352may be controlled by the voltage at the node347.

The nMOS transistor354may include a drain terminal coupled to the source terminal of the nMOS transistor352, a gate terminal coupled to the node335, and a source terminal coupled to drain terminal of the nMOS transistor356. Current flow between the source and drain terminals of the nMOS transistor354may be controlled by the voltage at the node335.

The nMOS transistor356may include a drain terminal coupled to the source terminal of the nMOS transistor354, a gate terminal coupled to the node315, and a source terminal coupled to the first terminal of the resistance350. Current flow between the source and drain terminals of the nMOS transistor356may be controlled by the voltage at the node315.

The nMOS transistor366may include a drain terminal coupled to the node367, a gate terminal coupled to the node337, and a source terminal coupled to the drain terminal of the nMOS transistor368. Current flow between the source and drain terminals of the nMOS transistor366may be controlled by the voltage at the node337.

The nMOS transistor368may include a drain terminal coupled to the source terminal of the nMOS transistor366, a gate terminal coupled to the node335, and a source terminal coupled to drain terminal of the nMOS transistor370. Current flow between the source and drain terminals of the nMOS transistor368may be controlled by the voltage at the node335.

The nMOS transistor370may include a drain terminal coupled to the source terminal of the nMOS transistor368, a gate terminal coupled to the node315, and a source terminal coupled to drain terminal of the nMOS transistor398. Current flow between the source and drain terminals of the nMOS transistor370may be controlled by the voltage at the node315.

The nMOS transistor372may include a drain terminal coupled to the node361, a gate terminal coupled to the node347, and a source terminal coupled to drain terminal of the nMOS transistor374. Current flow between the source and drain terminals of the nMOS transistor372may be controlled by the voltage at the node347.

The nMOS transistor374may include a drain terminal coupled to the source terminal of the nMOS transistor372, a gate terminal coupled to the node335, and a source terminal coupled to drain terminal of the nMOS transistor376. Current flow between the source and drain terminals of the nMOS transistor374may be controlled by the voltage at the node335.

The nMOS transistor376may include a drain terminal coupled to the source terminal of the nMOS transistor374, a gate terminal coupled to the node315, and a source terminal coupled to first terminal of the resistance384. Current flow between the source and drain terminals of the nMOS transistor376may be controlled by the voltage at the node315.

The nMOS transistor378may include a drain terminal coupled to the collector terminal of the BJT362, a gate terminal coupled to the node329, and a source terminal coupled to node379. Current flow between the source and drain terminals of the nMOS transistor378may be controlled by the voltage at the node329.

The nMOS transistor380may include a drain terminal coupled to the node379, a gate terminal coupled to the node381, and a source terminal coupled to negative voltage supply terminal324. Current flow between the source and drain terminals of the nMOS transistor380may be controlled by the voltage at the node381.

The nMOS transistor382may include a drain terminal coupled to the node381, a gate terminal coupled to the node381, and a source terminal coupled to the negative voltage supply terminal324. That is, the gate terminal of the nMOS transistor382may be coupled to the drain terminal of the nMOS transistor382, such that the nMOS transistor382is configured as a diode-connected transistor. Current flow between the source and drain terminals of the nMOS transistor382may be controlled by the voltage at the node381.

The nMOS transistor394may include a drain terminal coupled to the output terminal310, a gate terminal coupled to the node347, and a source terminal coupled to drain terminal of the nMOS transistor395. Current flow between the source and drain terminals of the nMOS transistor394may be controlled by the voltage at the node347.

The nMOS transistor395may include a drain terminal coupled to the source terminal of the nMOS transistor394, a gate terminal coupled to the335, and a source terminal coupled to the drain terminal of the nMOS transistor396. Current flow between the source and drain terminals of the nMOS transistor395may be controlled by the voltage at the node335.

The nMOS transistor396may include a drain terminal coupled to the source terminal of the nMOS transistor395, a gate terminal coupled to the node315, and a source terminal coupled to the node397. Current flow between the source and drain terminals of the nMOS transistor396may be controlled by the voltage at the node315.

The nMOS transistor398may include a drain terminal coupled to the source terminal of the nMOS transistor370, a gate terminal coupled to the node397, and a source terminal coupled to the negative voltage supply terminal324. Current flow between the source and drain terminals of the nMOS transistor398may be controlled by the voltage at the node397.

The nMOS transistor399may include a drain terminal coupled to the source terminal of the nMOS transistor396, a gate terminal coupled to the node379, and a source terminal coupled to negative voltage supply terminal324. Current flow between the source and drain terminals of the nMOS transistor399may be controlled by the voltage at the node379.

The resistance312may include a first terminal coupled to the current supply terminal302and a second terminal coupled to the node315. The resistance322may include a first terminal coupled to the node329and a second terminal coupled to the negative voltage supply terminal324. The resistance330may include a first terminal coupled to the node335and a second terminal coupled to the node329. The resistance336may include a first terminal coupled to the node337and a second terminal coupled to the node335. The resistance342may include a first terminal coupled to the reference voltage supply terminal202and a second terminal coupled to the node337. The resistance350may include a first terminal coupled to the source of the nMOS transistor356and a second terminal coupled to the negative voltage supply terminal324. The resistance384may include a first terminal coupled to the source of the nMOS transistor376and a second terminal coupled to the negative voltage supply terminal324. The resistances322,330,336,342may be arranged as a voltage divider that is coupled between the reference voltage supply terminal202and the negative voltage supply terminal324. In one or more embodiments, the resistances312,322,330,336,342,350,384may have respective resistance values in a range of around 10 kΩ to around 100 kΩ.

The amplifier device200may include multiple cascode arrangements, which may increase the operational voltage range of the amplifier device200. For example, each cascode arrangement may mitigate or prevent overvoltage conditions that might otherwise occur across transistors of the amplifier device200by distributing the voltage drop between two corresponding terminals or nodes of the amplifier device200across multiple series-connected transistors of that cascode arrangement. In one or more embodiments, the amplifier device200may include first, second, third, fourth, fifth, sixth, and seventh cascode arrangements. For example, the first cascode arrangement of the amplifier device200may include a first set of series-connected transistors (i.e., transistors connected in series, source-to-drain) coupled between the negative voltage supply terminal324and the output terminal310. The first set of series-connected transistors may include at least the nMOS transistors394,395,396, each corresponding to a respective cascode stage of the first cascode arrangement. The nMOS transistors395,396of the first cascode arrangement may be configured to receive respective fixed bias voltages (e.g., VC1, VC3) at their respective gate terminals, while the nMOS transistor394of the first cascode arrangement may be configured to receive a variable bias voltage (e.g., VC4) at its gate terminal to accommodate changes in VOUT.

For example, the second cascode arrangement of the amplifier device200may include a second set of series-connected transistors coupled between the node367(which is coupled to the reference voltage supply terminal202via the BJT388) and the negative voltage supply terminal324. The second set of series-connected transistors may include the nMOS transistors366,368,370, each corresponding to a respective cascode stage of the second cascode arrangement. Each transistor of the second cascode arrangement may be configured to receive a respective fixed bias voltage (e.g., VC1, VC3, VC5) at its gate terminal, at least because the voltage difference between the negative voltage supply terminal324and the reference voltage supply terminal202is fixed or substantially fixed.

For example, the third cascode arrangement of the amplifier device200may include a third set of series-connected transistors coupled between the node361and the negative voltage supply terminal324(e.g., via the resistance384). The third set of series-connected transistors may include the nMOS transistors372,374,376, each corresponding to a respective cascode stage of the third cascode arrangement. The node361may be coupled to the node228via the BJT364, which is controlled by the non-inverting input voltage VINPprovided at the non-inverting input terminal306. The voltage at the node228may be set, primarily, based on the voltage VTRKat the node308shifted down by the VGSof the nMOS transistor340, and based on the voltage at the node341shifted up by the base-emitter voltage (VBE) of the BJT344. In one or more embodiments, the VGSof the nMOS transistor340is equal to or approximately equal to the VBEof the BJT344, such that the shifts across the nMOS transistor340and the BJT344substantially cancel one another out, resulting in a voltage at the node228is equal to or approximately equal to VTRK. In one or more such embodiments, the current sourced by the collector terminal of the BJT218ofFIG.2at the node228is greater than the combined currents flowing into the collectors of the BJTs358,364(e.g., such that the remaining current flows into the emitter of the BJT334and biases the BJT344to operate in an emitter follower configuration).

The nMOS transistors374,376of the third cascode arrangement may be configured to receive respective fixed bias voltages (e.g., VC1, VC3) at their respective gate terminals, while the nMOS transistor372of the third cascode arrangement may be configured to receive a variable bias voltage (e.g., VC4) at its gate terminal to accommodate changes in the voltage at the node361caused by changes to the voltages VTRKand VINP. The third cascode arrangement, in combination with the resistance384, may act as a current source that provides bias current to the BJT364.

For example, the fourth cascode arrangement of the amplifier device200may include a fourth set of series-connected transistors coupled between the node357and the negative voltage supply terminal324(e.g., via the resistance350). The fourth set of series-connected transistors may include the nMOS transistors352,354,356, each corresponding to a respective cascode stage of the fourth cascode arrangement. The node357may be coupled to the node228via the BJT358, which is controlled by the inverting input voltage VINNprovided at the inverting input terminal304. The BJTs358,360may be in an up-down emitter follower arrangement and the BJTs362,364may be in an up-down emitter follower arrangement, such that the voltage at the node230is equal to or approximately equal to VINNand VINP. This means that the collector-base voltage (VCB) of each of the BJTs358,364is at or around 0 V. The nMOS transistors354,356of the fourth cascode arrangement may be configured to receive respective fixed bias voltages (e.g., VC1, VC3) at their respective gate terminals, while the nMOS transistor352of the fourth cascode arrangement may be configured to receive a variable bias voltage (e.g., VC4) at its gate terminal to accommodate changes in the voltage at the node361caused by changes to the voltages VTRKand VINP. The fourth cascode arrangement may act as a current source that provides bias current to the BJT358.

For example, the fifth cascode arrangement of the amplifier device200may include a fifth set of series-connected transistors coupled between the node341and the negative voltage supply terminal324. The fifth set of series-connected transistors may include the nMOS transistors326,328,332,346, each corresponding to a respective cascode stage of the fifth cascode arrangement. The node341may be coupled to the node via the nMOS transistor340, which is controlled by the tracking voltage VTRKprovided at the tracking voltage input terminal. The nMOS transistors326,328,332of the fifth cascode arrangement may be configured to receive respective fixed bias voltages (e.g., VC1, VC2, VC3) at their respective gate terminals, while the nMOS transistor346of the fifth cascode arrangement may be configured to receive a variable bias voltage (e.g., VC4) at its gate terminal to accommodate changes in the voltage at the node341caused by changes to the tracking voltage VTRK.

For example, the sixth cascode arrangement of the amplifier device200may include a sixth set of series-connected transistors coupled between the node226and the negative voltage supply terminal324. The sixth set of series-connected transistors may include the nMOS transistors316,320,334,338, each corresponding to a respective cascode stage of the sixth cascode arrangement. The node226may be biased to at or around VRTGNDminus the VGSof the nMOS transistor225. Each transistor of the sixth cascode arrangement may be configured to receive a respective fixed (or substantially fixed) bias voltage (e.g., VC1, VC2, VC3, VC5) at its gate terminal.

For example, the seventh cascode arrangement of the amplifier device200may include at least one transistor coupled between the collector of the BJT362and the node379. The at least one transistor of the seventh cascode arrangement may include the nMOS transistor378. The nMOS transistor378of the seventh cascode arrangement may be configured to receive a fixed bias voltage (e.g., VC6) at its gate terminal. The nMOS transistor378may be configured to prevent the voltage at the node379from exceeding the voltage at the node329(i.e., VC6).

Fixed or variable bias voltages may be provided to each cascode stage of the cascode arrangements via the nodes315,317,329,335,337,347(sometimes referred to herein as “cascode bias control nodes” or “bias nodes”). For example, a first cascode bias voltage VC1may be provided to gate terminals of the nMOS transistors316,328,356,376,370,396via the cascode bias control node315. A second cascode bias voltage VC2may be provided to gate terminals of the nMOS transistors320,326via the cascode bias control node317. In one or more embodiments, the first cascode bias voltage VC1may be around 0.7 V higher than the second cascode bias voltage VC2due to the voltage drop across the diode-connected nMOS transistor314. The cascode bias voltages VC1and VC2may be considered fixed at least because they depend on the current supplied via the terminal302, which is constant or substantially constant. A third cascode bias voltage VC3may be provided to the gate terminals of the nMOS transistors332,334,354,374,368,395via the cascode bias control node335. A fourth cascode bias voltage VC4may be provided to the gate terminals of the nMOS transistors346,352,372,394. In one or more embodiments, the fourth cascode bias voltage VC4may be equal to VTRKminus the VGSof the nMOS transistor340plus the VBEof the BJT344. Assuming the VGSof the nMOS transistor340is similar to the VBEof the BJT344(e.g., around 0.7 V to around 1 V), the value of the voltage VC4may be equal to or approximately equal to the tracking voltage VTRK(which, in turn, is equal to or approximately equal to the voltages VINP, VOUT). A fifth cascode bias voltage VC5may be provided to the gate terminals of the nMOS transistors338,366via the cascode bias control node337. A sixth cascode bias voltage VC6may be provided to the gate terminal of the nMOS transistor378via the cascode bias control node329.

In one or more embodiments, the cascode bias voltages VC1, VC2, VC3, VC5, and VC6may be a fixed voltages that are independent from the voltages VINN, VINP. In one or more embodiments, the cascode bias voltage VC4may be a variable voltage that is equal to or approximately equal to VTRK, VINP, and VOUT, such that the value of VC4changes as VTRK, VINP, and VOUTchange, as explained above. The cascode bias control nodes329,335,337may be nodes of a voltage divider that includes the resistances322,330,336,342coupled in series between the reference voltage supply terminal202and the negative voltage supply terminal324.

It should be understood that, in one or more other embodiments, more or fewer cascode stages than those shown in the present example may be included in the cascode arrangement (e.g., to accommodate higher or lower operating voltage ranges of the amplifier device200).

During operation of the amplifier device200, the BJTs360,362may form a differential input pair configure to receive the inverting input voltage VINNand the non-inverting input voltage VINP, respectively. The BJTs358,364may be arranged in respective emitter-follower configurations and may reduce bias currents at the inverting input terminal304and the non-inverting input terminal306, respectively. The nMOS transistors380,382may form an active load for the differential input pair and may provide the drive signal for the output stage (e.g., the nMOS transistors396,395,394) via the node379.

The amplifier device200may have an output voltage range of between around −8 V and around 0 V, as a non-limiting example, and the voltage VINN, VINP, and VOUTmay each be at or around the same value within the output voltage range during normal operation of the amplifier device200. For example, VOUTand VINN(and, in one or more embodiments, VTRK) may each be within 10% of the value of VINPduring normal operation of the amplifier device200. The BJT392may be configured to source current to the output terminal310and may have a sufficiently high collector-emitter voltage (VCE) limit, such that it can operate safely over the required output voltage range of the amplifier device200(e.g., having a VCElimit of around or above 8 V). The nMOS transistor399may be configured to sink current from the output terminal310. The nMOS transistor399may be limited to a maximum VDSof around 3 V or around 2.5 V according to various embodiments. Given such a VDSlimit, the output voltage range of the amplifier device200(e.g., up to an 8 V differential between VEEand VOUT) would exceed the maximum VDSlimit of the nMOS transistor399if the drain of the nMOS transistor399were connected directly to the output terminal310.

In a given cascode arrangement, each cascode stage protects either the transistor of an adjacent cascode stage or one or more devices to which that cascode stage is coupled by limiting the voltage provided to such transistors or devices. For example, considering the first cascode arrangement of the amplifier device200, the nMOS transistor396prevents the VDSlimit of the nMOS transistor399from being exceeded by limiting the voltage at the drain terminal of the nMOS transistor399. The nMOS transistor395prevents the VDSlimit of the nMOS transistor396from being exceeded by limiting the voltage at the drain terminal of the nMOS transistor396. The nMOS transistor394prevents the VDSlimit of the nMOS transistor395from being exceeded by limiting the voltage at the drain terminal of the nMOS transistor395. The values of the cascode bias voltages VC1, VC2, VC3, VC4, VC5, and VC6may be set such that the VGSand VGDlimits (e.g., each around 2.5 V to around 3 V) of the transistors of the cascode arrangements of the amplifier device200are not exceeded.

The values of the voltages VINN, VINP, VOUT, and VTRKmay vary within the output voltage range (e.g., a range of around −8 V to around 0 V) of the amplifier device200during its operation. To account for such variation in these voltages, at least one of the cascode bias voltages provide to one or more of the cascode arrangements of the amplifier device200may be a variable voltage, rather than a fixed voltage. For example, the fifth cascode bias voltage VC5at the fifth cascode bias control node347may vary depending on the value of VTRK(which, as noted above, tracks the voltage of VINPor VOUT, according to various embodiments). In this way, the voltage used to bias the nMOS transistors346,352,372,394may be dependent on the value of VTRK, which may accommodate changes in the drain terminal voltages of these transistors (which are, in turn, respectively equal to or dependent on VTRK, VINN, VINP, or VOUT).

As a non-limiting example, given VINP, VINN, VTRK, and VOUTvalues of around −1 V, a negative voltage VEEof −8 V, and a reference voltage VRTGNDof 0V, the first cascode bias voltage VC1is around −6.60 V, the second cascode bias voltage VC2is around −7.30 V, the third cascode bias voltage VC3is around −4.37 V, the fourth cascode bias voltage VC4is around −1.00 V (i.e., equal to or approximately equal to VTRKand VOUT), the fifth cascode bias voltage VC5is around −2.12 V, and the sixth cascode bias voltage VC6is at or around −4.86 V. Continuing the example, the drain voltage of the nMOS transistor395is around −1.70 V, the drain voltage of the nMOS transistor396is around −5.07 V, and the drain voltage of the nMOS transistor399is around −7.30 V. As illustrated this example, the inter-terminal voltage limits of the nMOS transistors394,395,396, and399are not exceeded given the condition in which VOUT, VINN, VINP, VTRKare each equal to or approximately equal to −1 V. It should be understood that the transistors included in or coupled to the other cascode arrangements of the amplifier device200are similarly protected against inter-terminal over-voltage conditions in this example.

As another non-limiting example, given VINP, VINN, VTRK, and VOUTvalues of around −4 V, a negative voltage VEEof −8 V, and a reference voltage VRTGNDof 0V, the first cascode bias voltage VC1is around −6.60 V, the second cascode bias voltage VC2is around −7.30 V, the third cascode bias voltage VC3is around −4.37 V, the fourth cascode bias voltage VC4is around −4.00 V (i.e., equal to or approximately equal to VTRKand VOUT), the fifth cascode bias voltage VC5is around −2.12 V, and the sixth cascode bias voltage VC6is at or around −4.86 V. Continuing the example, the drain voltage of the nMOS transistor395is around −4.70 V, the drain voltage of the nMOS transistor396is around −5.07 V, and the drain voltage of the nMOS transistor399is around −7.30 V. As illustrated this example, the inter-terminal voltage limits of the nMOS transistors394,395,396, and399are not exceeded given the condition in which VOUT, VINN, VINP, VTRKare each equal to or approximately equal to −4 V. It should be understood that the transistors included in or coupled to the other cascode arrangements of the amplifier device200are similarly protected against inter-terminal over-voltage conditions in this example.

The foregoing description refers to elements or nodes or features being “connected” or “coupled” together. As used herein, unless expressly stated otherwise, “connected” means that one element is directly joined to (or directly communicates with) another element, and not necessarily mechanically. Likewise, unless expressly stated otherwise, “coupled” means that one element is directly or indirectly joined to (or directly or indirectly communicates with) another element, and not necessarily mechanically. Thus, although the schematic shown in the figures depict one exemplary arrangement of elements, additional intervening elements, devices, features, or components may be present in one or more embodiments of the depicted subject matter. Furthermore, the term “amplifier” used herein should be understood to refer to a “power amplifier” unless noted otherwise.