Apparatus for and method of controlling AIVC through block selection information in semiconductor memory device

A method of controlling a bank voltage (AIVC) through memory block selection information, said method comprising the steps of detecting an array block selection signal of an array block disposed distantly from an AIVC driver in response to an activated memory array block selection signal; and supplying a second bank voltage to a memory bank by driving a normal size driver and an oversize driver when detecting the array block selection signal for the distantly disposed array block.

FIELD OF THE INVENTION

The present invention relates to a semiconductor memory device, and more particularly, to AIVC control apparatus and method to selectively supply a bank voltage.

DESCRIPTION OF THE RELATED ART

A semiconductor memory device generally includes numerous memory cells. According to U.S. Pat. No. 5,109,265 based on a conventional technology of the semiconductor memory device having such numerous cells, the plurality of memory cells are divided into four memory banks. To provide a supply voltage, different additional voltages are generated in the semiconductor memory device which are then supplied to memory cells.

For example, a substrate bias voltage is supplied to a substrate, a word line voltage is supplied to a word line of a memory bank, and a bit line voltage is supplied to a bit line.

A potential of the substrate is lower than an external voltage source supplied to a semiconductor chip, the word line voltage is externally supplied, and a potential of the bit line is lower than the external voltage source or at a level of the external voltage source.

The respective voltage generators which generate the additional voltages cause a power loss, in particular, the substrate bias voltage and the word line voltage.

According to U.S. Pat. No. 6,125,073 based on a conventional technology of a semiconductor memory device having four divided memory banks and a voltage generator per bank, four divided supply voltage sources are allocated to the four memory banks, and the supply voltage sources generate a word line voltage, a bit line voltage and a substrate voltage. The supply voltage source can supply one or numerous supply voltages in parallel. The supply voltage source transmits a high capacity drive potential if memory bank1among the four memory banks is activated. If memory bank1has a standby state and one of memory banks2,3,4is accessed, the supply voltage source supplies a low capacity drive potential.

FIGS. 1A and 1Billustrates block diagrams of a bank voltage supply control circuit of a conventional semiconductor memory device.

InFIGS. 1A and 1B, the bank voltage supply control circuit includes a bank voltage (AIVC) supply control signal generator10for generating an enable signal VINT EN for an AIVC supply in response to a block selection signal; 1st through 8th AIVC drivers21˜28for receiving the enable signal VINT EN for the AIVC supply outputted from the AIVC supply control signal generator10to supply a bank voltage (AIVC) to a memory bank30; and the memory bank30for respectively receiving the AIVCs supplied from the 1st through 8th AIVC drivers21˜28to write or read data.

The memory bank30includes sixteen blocks Block0˜Block15. The sixteen blocks Block0˜Block15are divided into two array blocks, a first array block31and a second array block32.

The AIVC supply control signal generator10generates an enable signal VINT EN for an AIVC supply when a block selection signal is applied. The 1st through 8th AIVC drivers21˜28receive the enable signal VINT EN for the AIVC supply outputted from the AIVC supply control signal generator10, and supply the AIVC to the memory bank30. That is, the 1st through 8th AIVC drivers21˜28are respectively constructed of PMOS transistors21˜28, and when the enable signal VINT EN for the AIVC supply is applied to a gate, the PMOS transistors21˜28are turned on to supply the AIVC to the memory bank30.

In the memory bank30, the same voltage should be supplied to the first array block31and the second array block32, but in order for normal operation of the second array block32, due to a length difference between the first array block31and the second array block32, a voltage higher than a normal operating voltage of the first array block31must be supplied. Thus, the AIVC from the 1st through 8th AIVC drivers21˜28at a voltage level to normally operate the second array block32of the memory bank30, is supplied to both the first array block31and the second array block32.

In the bank voltage control circuit10of such a conventional semiconductor memory device, the same voltage is supplied regardless of a position of an array block within a bank. Thus, a power overshoot is caused in the first array block31near to the 1st through 8th AIVC drivers21˜28and excess power consumption is caused due to a large capacity of the AIVC drivers.

SUMMARY OF THE INVENTION

Exemplary embodiments of the present invention provide a bank voltage control apparatus using block information, to prevent or reduce the possibility of a bank voltage from overshooting by supplying a voltage corresponding to a position of an array block of a bank.

In another exemplary embodiment, the present invention is directed to a bank voltage control apparatus using block information, to reduce power consumption by determining a driver size and a drive time of an over driver according to a block position through activated block information.

In an exemplary embodiment of the present invention, a bank voltage control apparatus using block information supplies bank voltages of different levels based on a position of array block.

In an exemplary embodiment of the present invention, the method of controlling a bank voltage (AIVC) through memory block selection information, comprises the steps of detecting an array block selection signal of an array block disposed distant from an AIVC driver in response to an activated memory array block selection signal; supplying a second bank voltage to a memory bank by driving a normal size driver and an oversize driver in detecting the array block selection signal of the distantly disposed array block; and supplying a first bank voltage to the memory bank by driving only the normal size driver when an array block selection signal disposed near to the AIVC driver is detected in response to the activated memory array block selection signal.

In another exemplary embodiment of the present invention, the apparatus for controlling an AIVC through memory block selection information, comprises an array block signal detector for detecting a second array block selection signal of a second array block disposed distantly from an AIVC driver in response to a block selection signal; an oversize driver controller for receiving the second array block selection signal detected from the array block signal detector to generate an enable signal for driving an oversize driver; an AIVC supply control signal generator for generating an enable signal for an AIVC supply in response to the block selection signal; and a plurality of AIVC drivers each having a normal size driver and the oversize driver, for receiving the enable signal for the AIVC supply and the enable signal for the drive of the oversize driver, the enable signal for the AIVC supply being outputted from the AIVC supply control signal generator and the enable signal for driving the oversize driver being outputted from the oversize driver controller, and for driving the normal size driver and the oversize driver so as to supply a second bank voltage to a memory bank.

The plurality of AIVC drivers each receive the enable signal for the AIVC supply outputted from the AIVC supply control signal generator when an array block selection signal disposed near to the AIVC driver is detected instead of the second array block selection signal of the distantly disposed array block, and drive only the normal size driver so as to supply the first bank voltage to the memory bank.

In an exemplary embodiment of the present invention, the apparatus for controlling an AIVC through memory block selection information, includes an array block signal detector for detecting a second array block selection signal of a second array block disposed distantly from an AIVC driver in response to a block selection signal; an oversize driver controller for receiving the second array block selection signal detected from the array block signal detector to generate an enable signal for driving an oversize driver; an over driver enable signal generator for receiving the second array block selection signal detected from the array block signal detector to output an over driver enable signal; an over driver pulse width controller for receiving the second array block selection signal detected from the array block signal detector to output an over driver pulse width control signal; an AIVC supply control signal generator for generating an enable signal for an AIVC supply in response to the block selection signal, and controlling and outputting a level of the enable signal for the AIVC supply in response to the over driver pulse width control signal outputted from the over driver pulse width controller when the over driver enable signal is applied from the over driver enable signal generator; and a plurality of AIVC drivers each having a normal size driver and the oversize driver, for receiving the enable signal for the AIVC supply outputted from the AIVC supply control signal generator and the enable signal for the drive of the oversize driver outputted from the oversize driver controller, so as to drive the normal size driver and the oversize driver, and for supplying a third bank voltage to a memory bank.

In another exemplary embodiment, the present invention is directed to a method of controlling a bank voltage comprising the steps of detecting an array block selection signal indicating an array block to which the bank voltage should be applied, varying the block voltage depending on a location of the array block in a memory bank, and supplying the bank voltage to the array block.

In another exemplary embodiment, the present invention is directed to a semiconductor memory device comprising at least one memory bank, including a plurality of array blocks and means for detecting an array block selection signal indicating the array block to which a bank voltage should be applied, varying the block voltage depending on a location of the array block in the memory bank, and supplying the bank voltage to the array block.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference toFIGS. 3trough5. In the inventive description, details of widely known functions of constructions will be omitted so as not to obscure the gist of the present invention.

FIGS. 3A AND 3Billustrate a block diagram of a bank voltage control apparatus using block information in accordance with an exemplary embodiment of the present invention.

Referring first toFIGS. 3A AND 3B, the bank voltage (AIVC) control apparatus includes an array block signal detector40, an oversize driver controller50, an over driver pulse width controller60, an over driver enable signal generator70, an AIVC supply control signal generator80, 1st through 8th AIVC drivers91˜98, and a memory bank100.

The array block signal detector40receives, inverts and logically sums block selection signals Bls8˜Bls15for blocks Block8˜Block15disposed distant from an AIVC driver, and then produces a second array block selection signal of the memory bank.

The oversize driver controller50includes an inverter51, a NOR gate52and an inverter53, and receives the second array block selection signal produced by the array block signal detector40to generate an enable signal.

The over driver pulse width controller60receives the second array block selection signal detected from the array block signal detector40, and outputs an over driver pulse width control signal OVER_DRV_PULSE CONTROL.

The over driver enable signal generator70includes an inverter71and receives the second array block selection signal detected from the array block signal detector40, to output an over driver enable signal OVER_DRV_EN.

The AIVC supply control signal generator80receives a block selection signal to generate an enable signal VINT EN for a supply of a bank voltage (AIVC). When the over driver enable signal OVER_DRV_EN is applied from the over driver enable signal generator70thereto, the AIVC supply control signal generator80controls and outputs a level of the enable signal VINT EN for the AIVC supply in response to the over driver pulse width control signal outputted from the over driver pulse width controller60.

The 1st through 8th AIVC drivers91˜98receive the enable signal VINT EN for the AIVC supply and the enable signal for a drive of the oversize driver, to supply the AIVC to the memory bank100, the enable signal for the AIVC supply being outputted from the AIVC supply control signal generator80and the enable signal for the drive of the oversize driver being outputted from the oversize driver controller50.

The memory bank100respectively receives the AIVCs supplied from the 1st through 8th AIVC drivers91˜98, to write or read data.

The memory bank100includes sixteen blocks Block0˜Block15. These sixteen blocks Block0˜Block15are divided into two array blocks, a first array block102and a second array block104.

InFIG. 4, the 1st through 8th AIVC drivers91˜98include each of PMOS transistors111˜118as normal size drivers and each of PMOS transistors119˜126as oversize drivers. The normal size drivers are the AIVC drivers for supplying the AIVC when the first array block102is selected, and the oversize drivers are the AIVC drivers for supplying the AIVC when the second array block104is selected.

FIG. 5is a waveform diagram illustrating a level state of the enable signal VINT EN for the AIVC supply in accordance with an exemplary embodiment of the present invention.

Operations related toFIGS. 3to5will be described as follows.

An Exemplary Embodiment

When a memory device is activated, a block selection signal (Blsi) (generated from a low address decoder (not shown), for example) is applied to the AIVC supply control signal generator80. The AIVC supply control signal generator80receives the block selection signal (Blsi), to generate the enable signal VINT EN for the AIVC supply having a level such as A of FIG.5and apply the signal to the 1st through 8th AIVC drivers91˜98. In the 1st through 8th AIVC drivers91˜98, the PMOS transistors111˜118as the normal size drivers are each turned on by the enable signal VINT EN, to apply the signal to the first and second array blocks102,104of the memory bank100.

When one of blocks Block0˜Block7in the first array block102of the memory bank100is selected, only the PMOS transistors111˜118are turned on so as to supply a first bank voltage AIVC1to the memory bank100.

When one of eight blocks Block8˜Block15in the second array block104of the memory bank100is selected, the array block signal detector40receives, inverts and logically sums the block selection signals Bls8˜Bls15, to produce a second array block selection signal of the memory bank100. The second array block selection signal detected from the array block signal detector40is inverted and outputted through the inverter51. The signal inverted through the inverter51is applied to one input terminal of the NOR gate52. Then the NOR gate52inverts, logically sums and outputs the signal inverted through the inverter51and the enable signal VINT EN for the AIVC supply generated from the AIVC supply control signal generator80. The inverted, logically summed up and outputted signal from the NOR gate52is inverted through the inverter53, and is applied to gates of the PMOS transistors119˜126as the oversize drivers of the 1st through 8th AIVC drivers91˜98. Thereby all of the PMOS transistors111˜118as the normal size drivers and the PMOS transistors119˜126as the oversize drivers are operated, to thus supply the AIVC.

Therefore, when the first array block102positioned near to the 1st through 8th AIVC drivers91˜98is selected, only the PMOS transistors111˜118as the normal size drivers are operated to supply the first bank voltage AIVC1so as to prevent or reduce the possibility of overshooting of the AIVC. Also, when the second array block104positioned distantly from the 1st through 8th AIVC drivers91˜98is selected, all of the PMOS transistors111˜118as the normal size drivers and the PMOS transistors119˜126as the oversize drivers are operated to supply a second bank voltage AIVC2so as to prevent or reduce the possibility the AIVC is undesirably reduced.

Another Exemplary Embodiment

Another exemplary embodiment of the present invention has the same operations as the previous exemplary embodiment and additionally has operations for the over driver.

In operation for the over driver, when one of eight blocks Block8˜Block15in the second array block104is selected, the array block signal detector40receives, inverts and logically sums up the block selection signals Bls8˜Bls15provided from the low address decoder, to thus detect the second array block selection signal of the memory bank. This second array block selection signal becomes a trigger pulse of a high state. The second array block selection signal is inverted through the inverter71, next is generated as the over driver enable signal OVER_DRV_EN, and is then applied to the AIVC supply control signal generator80. Thereby, the over driver of the AIVC supply control signal generator80is enabled.

Further, the over driver pulse width controller60receives the second array block selection signal detected from the array block signal detector40, and applies the over driver pulse width control signal OVER_DRV_PULSE CONTROL to the AIVC supply control signal generator80. The AIVC supply control signal generator80lowers like B ofFIG. 5a level of the enable signal VINT EN for the AIVC supply in response to the over driver pulse width control signal outputted from the over driver pulse width controller60, and then outputs the signal, when the over driver enable signal OVER_DRV_EN is applied from the over driver enable signal generator70.

When one of blocks of the second array block104is selected, a level of the enable signal VINT EN for the AIVC supply is lowered like B of FIG.5. Thus all of the normal size drivers and the oversize drivers of the 1st through 8th AIVC drivers91˜98are fully turned on so as to increase a level of voltage supplied to the memory bank100.

Accordingly, when the first array block102disposed near to the 1st through 8th AIVC drivers91˜98is selected, only the PMOS transistors111˜118as the normal size drivers are operated to supply the first bank voltage AIVC1. When the second array block104positioned distantly from the 1st through 8th AIVC drivers91˜98is selected, the PMOS transistors111˜118as the normal size drivers and the PMOS transistors119˜126as the oversize drivers are all operated to supply the second bank voltage AIVC2. Also, when the second array block104is selected, the over driver of the AIVC supply control signal generator80is driven lower like such as B ofFIG. 5a level of the enable signal VINT EN for the AIVC supply, so as to increase a level of the AIVC and then supply a third bank voltage AIVC3to the memory bank100.

Herewith, the level of the first to third bank voltages AIVC1, AIVC2, AIVC3has a size of AIVC1<AIVC2<AIVC3.

The first and second array blocks102,104divided from the memory bank100that is classified into two or more array blocks, can be discriminated with address signals. But, in case redundancy was used, it is difficult to decide the division only with corresponding addresses. In the exemplary embodiment of the present invention, therefore, even though redundancy was used, the AIVC can be accurately controlled, by using not only a corresponding address signal but also information of an actually activated block selection signal Blsi.

Though in the above-mentioned exemplary embodiments of the present invention, the memory bank100was divided into two blocks, first and second array blocks, and one oversize driver was used in one AIVC driver; in case a capacity of the memory bank100is increased, the present invention can be also embodied without deviating from a scope of the present invention, by dividing the memory bank into three or more array blocks and equipping oversize drivers of the number matched to the number of the divided array blocks with one AIVC driver.

As described above, in exemplary embodiments of the present invention, when an array block positioned near to an AIVC driver is selected, only a normal size driver is operated to supply an AIVC so as to prevent or reduce the possibility of overshooting the AIVC. Also, when an array block positioned distantly from the AIVC driver is selected, both of the normal size driver and the oversize driver are operated to supply the AIVC so as to prevent or reduce the possibility of the AIVC of the distantly positioned array block from being undesirably reduced.

In addition, a size of a driver and a drive time of an over driver can be determined according to a position of a memory array block through activated block information, to reduce power consumption.

Although the present invention was described in detail above in connection with the exemplary embodiments thereof, the scope of the invention is not so limited. Various changes and modifications may be made without departing from the spirit and scope of the invention as defined in the following claims.