Controlling output voltage for power converter

A method includes generating a first feedback signal in response to a tracking signal indicating an output signal of the power converter. The method further includes detecting an overshoot of the tracking signal or an undershoot of the tracking signal, generating a second feedback signal in response to the detection result and the first feedback signal, and generating a modulation signal in response to the second feedback signal. A circuit includes an overshoot-and-undershoot (OU) signal generator detecting an overshoot of a tracking signal or an undershoot of the tracking signal. The circuit further includes a feedback signal modulator receiving a first feedback signal and generating a second feedback signal in response to the detection result and the first feedback signal and a modulation controller generating a modulation signal in response to the second feedback signal.

BACKGROUND

This present disclosure relates to integrated circuit devices, and more particularly to a power converter.

A power converter converts an input voltage into an output voltage and provides the output voltage to a load. The power converter may regulate the output voltage at a substantially constant level using a feedback loop for power factor correction (PFC) control. However, under a load transient condition, a relatively narrow bandwidth of the feedback loop may lead to an overshoot or an undershoot of the output voltage.

DETAILED DESCRIPTION

Embodiments relate to power converters and controlling an output signal. In an embodiment, a power converter receives an input voltage and provides an output voltage to a load. A first feedback signal is generated in response to a tracking signal (e.g., a sampled signal), where the tracking signal indicates an output signal of the power converter. An overshoot of the sampled signal or an undershoot of the sampled signal is detected, and a second feedback signal is generated in response to the detection result and the first feedback signal. A modulation signal is generated in response to the second feedback signal.

FIG. 1illustrates a power converter100according to an embodiment. The power converter100receives an input voltage VINand provides an output voltage VOUTto a load160.

The power converter100inFIG. 1includes a primary side controller110. The primary side controller110inFIG. 1may be integrated in a semiconductor chip, and the semiconductor chip may be packaged by itself or together with one or more other semiconductor chips.

The load160inFIG. 1may include one or more integrated chips (ICs). In an embodiment, the output voltage Voutis used to supply power to a Central Processing Unit (CPU), a Graphics Processing Unit (GPU), an integrated memory circuit, a battery charger, a light emitting diode (LED), or other types of electrical load.

FIG. 2illustrates a power converter200suitable for use as the power converter100ofFIG. 1. The power converter200includes a primary side circuit202and a secondary side circuit204.

The primary side circuit202inFIG. 2includes a bridge rectifier206, a capacitor208, a primary winding212, a switching device226, a sense resistor230, and a primary side controller210. A power supply (not shown) provides an AC input signal ACINto the bridge rectifier206, which inverts the negative halves of the received AC signal to generate a rectified AC signal (or an input voltage) VIN. The input voltage VINis applied to the primary winding212of the power converter200inFIG. 2.

In an embodiment, the primary side controller210(e.g.,FIG. 2) includes an auxiliary winding230, first and second resistors242and244, a sample-and-hold (S/H) circuit228, an amplifier224, an overshoot-and-undershoot (OU) signal generator220, a feedback signal modulator232, a pulse width modulation (PWM) controller (or a modulation controller)234. The primary side controller210inFIG. 2generates a PWM signal (or a modulation signal) PWM to control (e.g., turn on or off) a switching device226.

When the switching device226inFIG. 2is turned on, a first current flowing through the switching device226increases from zero to a peak value and energy is stored in the primary winding212. When the switching device226is turned off, the stored energy causes a diode218in the secondary side circuit204to be turned on, resulting in a second current flowing through the diode218. During a diode conduction period, a sum of an output voltage VOUTand a diode forward-voltage drop is reflected to the auxiliary winding230inFIG. 2and a magnitude of the second current decreases. Because the diode forward-voltage drop decreases as the second current decreases, the reflected voltage VNAacross the auxiliary winding230at a time proximate to the end of the diode conduction period can be represented by Equation 1:

VNA≈VOUT×NANS.Equation⁢⁢1
In Equation 1, NAis a number of turns of the auxiliary winding230and NSis a number of turns of the secondary winding214.

The first and second resistors242and244inFIG. 2function as a voltage divider and generate a divided voltage VAat a node between the first and second resistors242and244. The S/H circuit228inFIG. 2samples the divided voltage VAat the time proximate to the end of the diode conduction period, and thus a tracking signal (e.g., a tracking voltage) VAOUTcorresponding to the sampled voltage has a level proportional to that of the output voltage VOUT. In an embodiment, the S/H circuit228samples the divided voltage VAat the time corresponding to 70%, 85%, or 90% of the diode conduction period at a previous switching cycle. Although the embodiment shown inFIG. 2includes the S/H circuit228to sample the divided voltage VAat a specific time to generate the sampled voltage VAOUT, embodiments of the present disclosure are not limited thereto. In an embodiment, the S/H circuit228may be omitted, and the divided voltage VAcan be used as the tracking signal VAOUTto continuously track the output voltage VOUT. In another embodiment, the auxiliary winding230may be further omitted, and a scaled version of the output voltage VOUTcan be used as the tracking signal VAOUT.

The amplifier224inFIG. 2generates a first feedback signal FB1in response to the sampled voltage VAOUTand a reference voltage VREF. In an embodiment, the amplifier224is a transconductance amplifier, which generates a current having a magnitude proportional to a difference between the sampled voltage VAOUTand the reference voltage VREF.

The OU signal generator220inFIG. 2receives the sampled voltage VAOUTand generates an overshoot signal DYNOVand an undershoot signal DYNUNin response to the sampled voltage VAOUT.

In an embodiment, the overshoot signal DYNOVtransitions from a first logic value (e.g., a logic low value) to a second logic value (e.g., a logic high value) when the sampled voltage VAOUTbecomes equal to or greater than an overshoot enable threshold voltage (e.g., an overshoot enable threshold voltage VOV_ENinFIG. 3), and transitions from the logic high value to the logic low value when the sampled voltage VAOUTbecomes less than an overshoot disable threshold voltage (e.g., an overshoot disable threshold voltage VOV_DISinFIG. 3). In another embodiment, the overshoot signal DYNOVtransitions from a logic low value to a logic high value at a first time (e.g., a first time t1inFIG. 9A) when the sampled voltage VAOUTbecomes equal to or greater than an overshoot enable threshold voltage, and transitions from the logic high value to the logic low value at a second time (e.g., a first time t2inFIG. 9A) corresponding to a sum of the first time and a predetermined time interval.

In an embodiment, the undershoot signal DYNUNtransitions from a first logic value (e.g., a logic low value) to a second logic value (e.g., a logic high value) when the sampled voltage VAOUTbecomes less than an undershoot enable threshold voltage (e.g., an undershoot enable threshold voltage VUN_ENinFIG. 3), and transitions from the logic high value to the logic low value when the sampled voltage VAOUTbecomes equal to or greater than an undershoot disable threshold voltage (e.g., an undershoot disable threshold voltage VUN_DISinFIG. 3). In another embodiment, the undershoot signal DYNUNtransitions from a logic low value to a logic high value at a first time (e.g., a first time t1inFIG. 9B) when the sampled voltage VAOUTbecomes less than an undershoot enable threshold voltage, and transitions from the logic high value to the logic low value at a second time (e.g., a second time t2inFIG. 9B) corresponding to a sum of the first time and a predetermined time interval.

The feedback signal modulator232inFIG. 2receives the first feedback signal FB1, the overshoot signal DYNOV, and the undershoot signal DYNUNto generate a second feedback signal FB2in response to the received signals FB1, DYNOV, and DYNUN. Although the embodiment shown inFIG. 2uses the first feedback signal FB1and the second feedback signal FB2, which are analog signals, embodiments of the present disclosure are not limited thereto. In an embodiment, an analog-to-digital converter (not shown) may be added to receive the sampled voltage VAOUTand provide a digital version of the first feedback signal FB1the feedback signal modulator232. In such an embodiment, the feedback signal modulator232generates a digital version of the second feedback signal FB2in response to the received signals FB1, DYNOV, and DYNUN.

When the overshoot signal DYNOVand the undershoot signal DYNUNhave logic low values, respectively, the feedback signal modulator232generates the second feedback signal FB2substantially the same as the first feedback signal FB1. When either the overshoot signal DYNOVor the undershoot signal DYNUNhas a logic high value, the feedback signal modulator232generates the second feedback signal FB2different from the first feedback signal FB1.

The PWM controller234inFIG. 2generates the PWM signal in response to the second feedback signal FB2. A duty cycle of the PWM signal varies with a value of the second feedback signal FB2.

In an embodiment, when the overshoot signal DYNOVhas a logic high value, the second feedback signal FB2decreases at a faster rate than the first feedback signal FB1to quickly reduce one or both of an on-time duration and a switching frequency of the PWM signal PWM. As a result, the primary side controller210inFIG. 2may prevent a severe overshoot of the output voltage VOUT.

In an embodiment, when the undershoot signal DYNUNhas a logic high value, the second feedback signal FB2increases at a faster rate than the first feedback signal FB1to quickly increase one or both of the on-time duration and the switching frequency of the PWM signal PWM. As a result, the primary side controller210inFIG. 2may prevent a severe undershoot of the output voltage VOUT.

FIG. 3illustrates an OU signal generator320suitable for use as the OU signal generator220ofFIG. 2according to an embodiment. The OU signal generator320inFIG. 3includes first and second comparators302and304, a first flip-flop306, third and fourth comparators308and310, and a second flip-flop312.

The first comparator302inFIG. 3compares a sampled voltage VAOUTto an overshoot enable threshold voltage VOV_EN, and generates a first set signal SET1having a first logic value (e.g., a logic high value) when the sampled voltage VAOUTis equal to or greater than the overshoot enable threshold voltage VOV_EN. The sampled voltage VAOUThas a magnitude proportional to an output voltage (e.g., the output voltage VOUTofFIG. 2) of a power converter (e.g., the power converter200ofFIG. 2).

The second comparator304inFIG. 3compares the sampled voltage VAOUTto an overshoot disable threshold voltage VOV_DIS, and generates a first reset signal RST1having a logic high value when the sampled voltage VAOUTis less than the overshoot disable threshold voltage VOV_DIS. The overshoot disable threshold voltage VOV_DIShas a level lower than that of the overshoot enable threshold voltage VOV_EN.

In an embodiment, the first flip-flop306inFIG. 3is a set/reset (RS) flip-flop. The RS flip-flop306generates an overshoot signal DYNOVhaving a first logic value (e.g., a logic high value) when the first set signal SET1has a logic high value, and generates the overshoot signal DYNOVhaving a second logic value (e.g., a logic low value) when the first reset signal RST1has a logic high value. Although the embodiment shown inFIG. 3includes the first and second comparators302and304and the first flip-flop306, embodiments of the present disclosure are not limited thereto. In an embodiment, a single comparator (not shown) having a given hysteresis can replace with the first and second comparators302and304and the first flip-flop306. For example, the given hysteresis makes the comparator generate an overshoot signal DYNOVhaving a first logic value (e.g., a logic high value) when the sampled voltage VAOUTis equal to or greater than the overshoot enable threshold voltage VOV_ENand generate the overshoot signal DYNOVhaving a second logic value (e.g., a logic low value) when the sampled voltage VAOUTis less than the overshoot disable threshold voltage VOV_DIS.

The third comparator308inFIG. 3compares the sampled voltage VAOUTto an undershoot enable threshold voltage VUN_EN, and generates a second set signal SET2having a logic high value when the sampled voltage VAOUTis less than the undershoot enable threshold voltage VUN_EN.

The fourth comparator310inFIG. 3compares the sampled voltage VAOUTto an undershoot disable threshold voltage VUN_DIS, and generates a second reset signal RST2having a logic high value when the sampled voltage VAOUTis equal to or greater than the undershoot disable threshold voltage VUN_DIS. The undershoot disable threshold voltage VUN_DIShas a level higher than that of the undershoot enable threshold voltage VUN_EN.

In an embodiment, the second flip-flop312inFIG. 3is a set/reset (RS) flip-flop. The RS flip-flop312generates an undershoot signal DYNUNhaving a first logic value (e.g., a logic high value) when the second set signal SET2has a logic high value, and generates the undershoot signal DYNUNhaving a second logic value (e.g., a logic low value) when the second reset signal RST2has a logic high value. Although the embodiment shown inFIG. 3includes the third and fourth comparators308and310and the second flip-flop312, embodiments of the present disclosure are not limited thereto. In an embodiment, a single comparator (not shown) having a given hysteresis can replace with the third and fourth comparators308and310and the second flip-flop312. For example, the given hysteresis makes the comparator generate an undershoot signal DYNUNhaving a first logic value (e.g., a logic high value) when the sampled voltage VAOUTis less than the undershoot enable threshold voltage VUN_ENand generate the undershoot signal DYNUNhaving a second logic value (e.g., a logic low value) when the sampled voltage VAOUTis equal to or greater than the undershoot disable threshold voltage VUN_DIS.

FIG. 4illustrates a feedback signal modulator432suitable for use as the feedback signal modulator232ofFIG. 2according to an embodiment. The feedback signal modulator432inFIG. 4includes first and second flip-flops402and422, first and second logic gates404and414, first and second current sources406and420, an inverter412, a comparator410, a capacitor418, first, second, and third switching devices408,416, and426, and a third logic gate424.

The feedback signal modulator432inFIG. 4receives a first feedback signal FB1through an input node I. The input node I is connected to a first end of the second switching device416and to a non-inverting input of the comparator410.

The comparator410inFIG. 4has an inverting input receiving a second feedback signal FB2a. The comparator410inFIG. 4compares the first feedback signal FB1to the second feedback signal FB2a, and generates a comparison signal DYNCOM.

The first flip-flop402inFIG. 4receives an inverted version of the comparison signal DYNCOMand an inverted version of an overshoot signal DYNOV. In an embodiment, the first flip-flop402is an RS flip-flop, and the RS flip-flop402generates an overshoot end signal OVENDhaving a first logic value (e.g., a logic high value) when the overshoot signal DYNOVhas a logic low value, and generates the overshoot end signal OVENDhaving a second logic value (e.g., a logic low value) when the comparison signal DYNCOMhas a logic low value.

The first logic gate404inFIG. 4receives the overshoot end signal OVENDand an undershoot signal DYNUN, and performs a logical operation on the received signals OVENDand DYNUN. In an embodiment, the first logic gate404is an OR gate and performs an OR logical operation on the overshoot end signal OVENDand the undershoot signal DYNUNto provide an output signal to the first switching device408.

The first switching device408inFIG. 4is turned on or off in response to the output signal from the first logic gate404. In an embodiment, the first switching device408is turned on when the output signal from the first logic gate404has a first logic value (e.g., a logic high value), and is turned off when the output signal from the first logic gate404has a second logic value (e.g., a logic low value).

The second flip-flop422inFIG. 4receives the comparison signal DYNCOMand an inverted version of the undershoot signal DYNUN. In an embodiment, the second flip-flop422is an RS flip-flop, and the RS flip-flop422generates an undershoot end signal UNENDhaving a first logic value (e.g., a logic high value) when the undershoot signal DYNUNhas a logic low value, and generates the undershoot end signal UNENDhaving a second logic value (e.g., a logic low value) when the comparison signal DYNCOMhas a logic high value.

The second logic gate414inFIG. 4receives the undershoot end signal UNENDand the overshoot signal DYNOV, and performs a logical operation on the received signals UNENDand DYNOV. In an embodiment, the second logic gate414is an OR gate and performs an OR logical operation on the undershoot end signal UNENDand the overshoot signal DYNOVto provide an output signal to the third switching device426.

The third switching device426inFIG. 4is turned on or off in response to the output signal from the second logic gate414. In an embodiment, the third switching device426is turned on when the output signal from the second logic gate414has a first logic value (e.g., a logic high value), and is turned off when the output signal from the second logic gate414has a second logic value (e.g., a logic low value).

The third logic gate424inFIG. 4receives the overshoot end signal OVEND, the undershoot end signal UNEND, the overshoot signal DYNOV, and the undershoot signal DYNUN. In an embodiment, the third logic gate424is an OR gate and performs an OR logical operation on the received signals OVEND, UNEND, DYNOV, and DYNUNto generate a dynamic control signal DYN.

The inverter412inFIG. 4receives the dynamic control signal DYN, and inverts the dynamic control signal DYN to turn on or off the second switching device416. In an embodiment, the second switching device416is turned on to couple the input node I to an output node O when the dynamic control signal DYN has a logic low value.

The capacitor418inFIG. 4has a first end connected to the output node O and a second end connected to a ground. The feedback signal modulator432inFIG. 4outputs the second feedback signal FB2athrough the output node O. Although the embodiment shown inFIG. 4includes the capacitor418, embodiments of the present disclosure are not limited thereto. In an embodiment using digital versions of the first feedback signal FB1and the second feedback signal FB2a, the capacitor418may be replaced with a digital circuit element (e.g., a digital counter).

An operation of a primary side controller (e.g., the primary side controller210inFIG. 2), which includes the OU signal generator320inFIG. 3and the feedback signal modulator432inFIG. 4, is explained below in more detail below with reference toFIGS. 5A and 5B.FIG. 5Aillustrates example waveforms of the first feedback signal FB1, the second feedback signal FB2a, the sampled voltage VAOUT, the overshoot signal DYNOV, and the overshoot end signal OVENDwhen an overshoot of an output voltage (e.g., the output voltage VOUTinFIG. 2) occurs under a load transient condition.

At a first time t1inFIG. 5A, the sampled voltage VAOUTbecomes equal to or greater than the overshoot enable threshold voltage VOV_EN, and the first flip-flop306inFIG. 3generates an overshoot signal DYNOVhaving a logic high value in response to the first set signal SET1having a logic high value. In an embodiment, the overshoot enable threshold voltage VOV_ENhas a level equal to or greater than 110% of a level of a predetermined reference voltage VREF. The second logic gate414inFIG. 4generates an output signal having a logic high value in response to the overshoot signal DYNOVhaving a logic high value to turn on the third switching device426inFIG. 4. The third logic gate424inFIG. 4generates the dynamic control signal DYN having a logic high value in response to the overshoot signal DYNOVhaving a logic high value to turn off the second switching device416inFIG. 4.

During a time interval between the first time t1and a second time t2, the second switching device416inFIG. 4is turned off and the third switching device426inFIG. 4is turned on. A current flowing through the second current source420inFIG. 4discharges the capacitor418inFIG. 4, and thus a value of the second feedback signal FB2ais decreased at a faster rate than the first feedback signal FB1until the value of the second feedback signal FB2areaches a minimum value (e.g., zero volt).

When the value of the second feedback signal FB2ais decreased, a PWM controller (e.g., the PWM controller234inFIG. 2) reduces one or both of an on-time duration and a switching frequency of a PWM signal (e.g., the PWM signal PWM inFIG. 2). As a result, the primary side controller including the OU signal generator320inFIG. 3and the feedback signal modulator432inFIG. 4may prevent a severe overshoot of an output voltage (e.g., the output voltage VOUTinFIG. 2).

At the second time t2, the sampled voltage VAOUTbecomes less than the overshoot disable threshold voltage VOV_DIS, and the first flip-flop306inFIG. 3generates the overshoot signal DYNOVhaving a logic low value in response to the first reset signal RET1having a logic high value. In an embodiment, the overshoot disable threshold voltage VOV_DIShas a level substantially equal to 105% of that of the reference voltage VREF. As a result, the flip-flop402inFIG. 4generates the overshoot end signal OVENDhaving a logic high value in response to the overshoot signal DYNOVhaving a logic low value, and the first logic gate404inFIG. 4generates an output signal having a logic high value to turn on the first switching device408inFIG. 4. The third logic gate424inFIG. 4generates the dynamic control signal DYN having a logic high value in response to the overshoot end signal OVENDhaving a logic high value to turn off the second switching device416inFIG. 4.

During a time interval between the second time t2and a third time t3, the second switching device416inFIG. 4is turned off and the first switching device408inFIG. 4is turned on. A current flowing through the first current source406inFIG. 4charges the capacitor418inFIG. 4, and thus a value of the second feedback signal FB2ais increased until the second feedback signal FB2areaches the first feedback signal FB1.

At the third time t3when the second feedback signal FB2areaches the first feedback signal FB1, the comparator410inFIG. 4generates the comparison signal DYNCOMhaving a logic low value in response to the second feedback signal FB2aand the first feedback signal FB1, and thus the flip-flop402inFIG. 4generates the overshoot end signal OVENDhaving a logic low value. The third logic gate424inFIG. 4generates the dynamic control signal DYN having a logic low value, and thus the inverter412inFIG. 4generates an output signal having a logic high value to turn on the second switching device416inFIG. 4. As a result, the second switching device416inFIG. 4couples the input node I inFIG. 4to the output node O inFIG. 4to generate the second feedback signal FB2a, which is substantially the same as the first feedback signal FB1.

FIG. 5Billustrates example waveforms of the first feedback signal FB1, the second feedback signal FB2a, the sampled voltage VAOUT, the undershoot signal DYNUN, and the undershoot end signal UNENDwhen an undershoot of the output voltage occurs under a load transient condition.

At a first time t1inFIG. 5B, the sampled voltage VAOUTbecomes less than the undershoot enable threshold voltage VUN_EN, and the second flip-flop312inFIG. 3generates an undershoot signal DYNUNhaving a logic high value in response to the second set signal SET2having a logic high value. In an embodiment, the undershoot enable threshold voltage VUN_ENhas a level substantially equal to or less than 90% of that of the predetermined reference voltage VREF. The first logic gate404inFIG. 4generates an output signal having a logic high value in response to the undershoot signal DYNUNhaving a logic high value to turn on the first switching device408inFIG. 4. The third logic gate424inFIG. 4generates the dynamic control signal DYN having a logic high value in response to the undershoot signal DYNUNhaving a logic high value to turn off the second switching device416inFIG. 4.

During a time interval between the first time t1and a second time t2, the second switching device416inFIG. 4is turned off and the first switching device408inFIG. 4is turned on. A current flowing through the first current source406inFIG. 4charges the capacitor418inFIG. 4, and thus a value of the second feedback signal FB2ais increased at a faster rate than the first feedback signal FB1until the second feedback signal FB2areaches a maximum value.

When the value of the second feedback signal FB2ais increased, the PWM controller increases one or both of the on-time duration and the switching frequency of the PWM signal. As a result, the primary side controller including the OU signal generator320inFIG. 3and the feedback signal modulator432inFIG. 4may prevent a severe undershoot of the output voltage.

At the second time t2, the sampled voltage VAOUTbecomes equal to or greater than the undershoot disable threshold voltage VUN_DIS, and the second flip-flop312inFIG. 3generates the undershoot signal DYNUNhaving a logic low value in response to the second reset signal RST2having a logic high value. In an embodiment, the undershoot disable threshold voltage VUN_DIShas a level substantially equal to 95% of that of the predetermined reference voltage VREF. As a result, the flip-flop422inFIG. 4generates the undershoot end signal UNENDhaving a logic high value in response to the undershoot signal DYNUNhaving a logic low value, and the second logic gate414inFIG. 4generates an output signal having a logic high value in response to the undershoot end signal UNENDhaving a logic high value to turn on the third switching device426inFIG. 4. The third logic gate424inFIG. 4generates the dynamic control signal DYN having a logic high value in response to the undershoot end signal UNENDhaving a logic high value to turn off the second switching device416inFIG. 4.

During a time interval between the second time t2and a third time t3, the second switching device416inFIG. 4is turned off and the third switching device426inFIG. 4is turned on. A current flowing through the second current source420inFIG. 4discharges the capacitor418inFIG. 4, and thus a value of the second feedback signal FB2ais decreased until the second feedback signal FB2areaches the first feedback signal FB1.

At the third time t3when the second feedback signal FB2areaches the first feedback signal FB1, the comparator410inFIG. 4generates the comparison signal DYNCOMhaving a logic high value in response to the second feedback signal FB2aand the first feedback signal FB1, and thus the flip-flop422inFIG. 4generates the undershoot end signal UNENDhaving a logic low value in response to the comparison signal DYNCOMhaving a logic high value. The third logic gate424inFIG. 4generates the dynamic control signal DYN having a logic low value, and thus the inverter412inFIG. 4generates an output signal having a logic high value to turn on the second switching device416. As a result, the second switching device416inFIG. 4couples the input node I inFIG. 4to the output node O inFIG. 4to generate the second feedback signal FB2a, which is substantially the same as the first feedback signal FB1.

FIG. 6illustrates a feedback signal modulator632suitable for use as the feedback signal modulator232ofFIG. 2according to another embodiment. The feedback signal modulator632inFIG. 6includes a logic gate602, an output node O, and first, second, and third switching devices606,604, and608.

The logic gate602inFIG. 6receives an overshoot signal DYNOVand an undershoot signal DYNUN. In an embodiment, the logic gate602is a NOR gate and performs a NOR logical operation on the overshoot signal DYNOVand the undershoot signal DYNUNto provide an output signal to the second switching device604.

The second switching device604inFIG. 6is turned on or off in response to the output signal from the logic gate602. In an embodiment, the second switching device604is turned on when the output signal from the logic gate602has a first logic value (e.g., a logic high value), and is turned off when the output signal from the logic gate602has a second logic value (e.g., a logic low value).

The first switching device606inFIG. 6is turned on or off in response to the undershoot signal DYNUN. In an embodiment, the first switching device606is turned on when the undershoot signal DYNUNhas a first logic value (e.g., a logic high value) to couple the output node O to a power supply VDD, and is turned off when the undershoot signal DYNUNhas a second logic value (e.g., a logic low value).

The third switching device608inFIG. 6is turned on or off in response to the overshoot signal DYNOV. In an embodiment, the third switching device608is turned on when the overshoot signal DYNOVhas a first logic value (e.g., a logic high value) to couple the output node O to a ground, and is turned off when the overshoot signal DYNOVhas a second logic value (e.g., a logic low value).

An operation of a primary side controller (e.g., the primary side controller210inFIG. 2), which includes the OU signal generator320inFIG. 3and the feedback signal modulator632inFIG. 6, is explained below in more detail below with reference toFIGS. 7A and 7B.FIG. 7Aillustrates example waveforms of the first feedback signal FB1, a second feedback signal FB2b, the sampled voltage VAOUT, and the overshoot signal DYNOVwhen an overshoot of an output voltage (e.g., the output voltage VOUTinFIG. 2) occurs under a load transient condition.

At a first time t1inFIG. 7A, the sampled voltage VAOUTbecomes greater than the overshoot enable threshold voltage VOV_EN, and the first flip-flop306inFIG. 3generates the overshoot signal DYNOVhaving a logic high value in response to the first set signal SET1having a logic high value. The logic gate602inFIG. 6generates an output signal having a logic low value in response to the overshoot signal DYNOVhaving a logic high value to turn off the second switching device604inFIG. 6. The third switching device608inFIG. 6is turned on in response to the overshoot signal DYNOVhaving a logic high value. As a result, the value of the second feedback signal FB2bis decreased to a minimum value (e.g., zero volt) at the first time t1, e.g., substantially instantaneously.

At a second time t2inFIG. 7A, the sampled voltage VAOUTbecomes less than the overshoot disable threshold voltage VOV_DIS, and the first flip-flop306inFIG. 3generates the overshoot signal DYNOVhaving a logic low value in response to the first reset signal RST1having a logic high value. The third switching device608inFIG. 6is turned off in response to the overshoot signal DYNOVhaving a logic low value. The logic gate602inFIG. 6generates the output signal having a logic high value in response to the overshoot signal DYNOVhaving a logic low value to turn on the second switching device604inFIG. 6. As a result, the second feedback signal FB2breaches the first feedback signal FB1at the second time t2, e.g., substantially instantaneously.

FIG. 7Billustrates example waveforms of the first feedback signal FB1, the second feedback signal FB2b, the sampled voltage VAOUT, and the undershoot signal DYNUNwhen an undershoot of the output voltage occurs under a load transient condition.

At a first time t1inFIG. 7B, the sampled voltage VAOUTbecomes less than the undershoot enable threshold voltage VUN_EN, and the second flip-flop312inFIG. 3generates an undershoot signal DYNUNhaving a logic high value in response to the second set signal SET2having a logic high value. The logic gate602inFIG. 6generates the output signal having a logic low value in response to the undershoot signal DYNUNhaving a logic high value to turn off the second switching device604inFIG. 6. The first switching device606inFIG. 6is turned on in response to the undershoot signal DYNUNhaving a logic high value. As a result, the value of the second feedback signal FB2bis increased to a maximum value (e.g., the power supply voltage VDD) at the first time t1, e.g., substantially instantaneously.

At a second time t2inFIG. 7B, the sampled voltage VAOUTbecomes equal to or greater than the undershoot disable threshold voltage VUN_DIS, and the second flip-flop312inFIG. 3generates the undershoot signal DYNUNhaving a logic low value in response to the second reset signal RST2having a logic high value. The first switching device606inFIG. 6is turned off in response to the undershoot signal DYNUNhaving a logic low value. The logic gate602inFIG. 6generates the output signal having a logic high value to turn on the second switching device604inFIG. 6. As a result, the second feedback signal FB2breaches the first feedback signal FB1at the second time t2, e.g., substantially instantaneously.

FIG. 8illustrates an OU signal generator820suitable for use as the OU signal generator220ofFIG. 2according to another embodiment. The OU signal generator820inFIG. 8includes a first comparator802, a first delay circuit806, a first flip-flop804, a second comparator808, a second delay circuit812, and a second flip-flop810.

The first comparator802inFIG. 8compares a sampled voltage VAOUTto an overshoot enable threshold voltage VOV_EN, and generates a first output signal OUT1having a logic high value when the sampled voltage VAOUTis equal to or greater than the overshoot enable threshold voltage VOV_EN. The first delay circuit806inFIG. 8delays the first output signal OUT1by a first delay amount to generate a delayed version of the first output signal OUT1.

In an embodiment, the first flip-flop804inFIG. 8is a set/reset (RS) flip-flop. The RS flip-flop804generates an overshoot signal DYNOVhaving a first logic value (e.g., a logic high value) when the first output signal OUT1has a logic high value, and generates the overshoot signal DYNOVhaving a second logic value (e.g., a logic low value) when the delayed version of the first output signal OUT1has a logic high value. As a result, the RS flip-flop804generates a pulse having a width that corresponds to the first delay amount of the first delay circuit806.

The second comparator808inFIG. 8compares the sampled voltage VAOUTto an undershoot enable threshold voltage VUN_EN, and generates a second output signal OUT2having a logic high value when the sampled voltage VAOUTis less than the undershoot enable threshold voltage VUN_EN. The second delay circuit808inFIG. 8delays the second output signal OUT2by a second delay amount to generate a delayed version of the second output signal OUT2.

In an embodiment, the second flip-flop810inFIG. 8is a set/reset (RS) flip-flop. The RS flip-flop810generates an undershoot signal DYNUNhaving a first logic value (e.g., a logic high value) when the second output signal OUT2has a logic high value, and generates the undershoot signal DYNUNhaving a second logic value (e.g., a logic low value) when the delayed version of the second output signal OUT2has a logic high value. As a result, the RS flip-flop810generates a pulse having a width that corresponds to the second delay amount of the second delay circuit810.

FIG. 9Aillustrates an operation of a primary side controller (e.g., the primary side controller210inFIG. 2), which includes the OU signal generator820inFIG. 8and the feedback signal modulator432inFIG. 4or includes the OU signal generator820inFIG. 8and the feedback signal modulator632inFIG. 6. Specifically,FIG. 9Aillustrates example waveforms of the first feedback signal FB1, the second feedback signals FB2aand FB2b, the sampled voltage VAOUT, the overshoot signal DYNOV, and the overshoot end signal OVENDwhen an overshoot of an output voltage (e.g., the output voltage VOUTinFIG. 2) occurs under a load transient condition.

Unlike the OU signal generator320inFIG. 3including the second comparator304, the OU signal generator820inFIG. 8includes the first delay circuit806. As a result, a time interval between a first time t1and a second time t2inFIG. 9Ais determined by the first delay amount of the first delay circuit806inFIG. 8, rather than by a comparison result of the second comparator304inFIG. 3. Other operations of the OU signal generator820inFIG. 8are similar to those of the OU signal generator320inFIG. 3, and thus detailed descriptions of these operations of the primary side controller including the OU signal generator820inFIG. 8will be omitted herein for the interest of brevity.

FIG. 9Billustrates an operation of the primary side controller, which includes the OU signal generator820inFIG. 8and the feedback signal modulator432inFIG. 4or includes the OU signal generator820inFIG. 8and the feedback signal modulator632inFIG. 6. Specifically,FIG. 9Billustrates example waveforms of the first feedback signal FB1, the second feedback signals FB2aand FB2b, the sampled voltage VAOUT, the undershoot signal DYNUN, and the undershoot end signal UNENDwhen an undershoot of an output voltage (e.g., the output voltage VOUTinFIG. 2) occurs under a load transient condition.

Unlike the OU signal generator320inFIG. 3including the fourth comparator312, the OU signal generator820inFIG. 8includes the second delay circuit812. As a result, a time interval between a first time t1and a second time t2inFIG. 9Bis determined by the second delay amount of the second delay circuit812inFIG. 8, rather than by a comparison result of the fourth comparator312inFIG. 3. Other operations of the OU signal generator820inFIG. 8are similar to those of the OU signal generator320inFIG. 3, and thus detailed descriptions of these operations of the primary side controller including the OU signal generator820inFIG. 8will be omitted herein for the interest of brevity.

FIG. 10illustrates a process1000performed by a controller (e.g., the primary side controller210ofFIG. 2) according to an embodiment. In an embodiment, the controller includes an OU signal generator (e.g., the OU signal generator circuit220ofFIG. 2), a feedback signal modulator (e.g., the feedback signal modulator232ofFIG. 2), and a modulation controller (e.g., the PWM controller234ofFIG. 2).

At S1020, the controller generates a first feedback signal (e.g., the first feedback signal FB1ofFIG. 2) in response to a sampled signal (e.g., the sampled signal VAOUTofFIG. 2), which indicates an output signal of a power converter (e.g., the power converter200ofFIG. 2). In an embodiment, the controller further includes an amplifier (e.g., the amplifier224ofFIG. 2) that generates the first feedback signal in response to the sampled signal and a reference voltage (e.g., the reference voltage VREFofFIG. 2).

At S1040, the OU signal generator detects an overshoot or an undershoot of the sampled signal. In an embodiment, the OU signal generator generates an overshoot signal having a first logic value (e.g., a logic high value) when the overshoot is detected, and generates an undershoot signal having a second logic value (e.g., a logic high value) when the undershoot is detected. In an embodiment, the first and second logic values are the same values, but may be different values in other embodiments.

At S1060, the feedback signal modulator generates a second feedback signal (e.g., the second feedback signal FB2ofFIG. 2) in response to the detection result and the first feedback signal. In an embodiment, the feedback signal modulator generates the second feedback signal that is different from the first feedback signal when the OU signal generator detects the overshoot of the sampled signal or the undershoot of the sampled signal.

At S1080, the modulation controller generates a modulation signal (e.g., the PWM signal PWM ofFIG. 2) in response to the second feedback signal. In an embodiment, the modulation controller adjusts one or both of an on-time duration and a switching frequency of the modulation signal in response to the second feedback signal.

Aspects of the present disclosure have been described in conjunction with the specific embodiments thereof that are proposed as examples. Numerous alternatives, modifications, and variations to the embodiments as set forth herein may be made without departing from the scope of the claims set forth below. Accordingly, embodiments as set forth herein are intended to be illustrative and not limiting.