PHOTONIC INTEGRATED CIRCUIT

A device includes a substrate, a dielectric layer on the substrate, a waveguide within the dielectric layer, and a photodetector optically coupled to the waveguide. The photodetector is disposed above the waveguide layer and is monolithically integrated with the substrate. The photodetector is configured to operate at low temperatures, such as below about 50 K or about 20 K. In some embodiments, the monolithic photonic device includes thermal isolation structures and optical isolation structures. Techniques for manufacturing the monolithic photonic device, including the thermal isolation structures and optical isolation structures, are also described.

BACKGROUND

Photonic integrated circuits, such as photonic integrated circuits in photonic quantum computing systems, may include various integrated optical components, such as waveguides, couplers, photon generators, filter, switches, detectors, interferometers, delay lines, and the like. Integrating different types of integrated optical components onto a single chip may be difficult due to the different processes and material used for fabricating these integrated optical components.

Integrating different types of integrated optical components onto a single chip may also negatively impact the performance of the photonic integrated circuits due to, for example, noises caused by stray lights or thermal dissipation from heat generating components to other components. For example, photodetectors with high sensitivity, such as single photon detectors, may be used in many photonic quantum technologies, such as quantum cryptography and quantum computing. Because of their high sensitivity, these photodetectors may be very susceptible to noise, such as undesired ambient light or stray light that may reach the photodetectors through direct or indirect paths. Certain thermo-optical components, such as thermal tuners for tuning filters, may use heaters. Heat generated by the heaters may dissipate to other regions of the photonic integrated circuit, which may reduce the efficiency of the thermo-optical components and/or may increase the temperature of other components that may need to operate at low temperatures, such as cryogenic temperatures.

SUMMARY

This disclosure relates generally to photonic integrated circuit. More specifically, this disclosure relates to techniques for integrating different types of components on a monolithic photonic integrated circuit. The monolithic photonic integrated circuit includes optical and/or thermal isolation structures. For example, the monolithic photonic integrated circuit may include optical isolation structures for preventing background light from reaching a highly sensitive photodetector (e.g., a superconducting nanowire single photon detector) in a photonic integrated circuit (PIC) in order to achieve the high sensitivity and high signal to noise ratio (SNR). The monolithic photonic integrated circuit may also include thermal isolation structures to reduce or prevent heat dissipation from some thermo-optic devices to other regions of the photonic integrated circuit. The monolithic photonic integrated circuit with optical and/or thermal isolation structures may be manufactured using a combination of semiconductor processing techniques. Various inventive embodiments are described herein, including methods, processes, systems, devices, and the like.

According to certain embodiments, the photonic integrated circuit may include a photonic integrated circuit for optical quantum computing. The photonic integrated circuit may include various combination of different types of integrated optical components, such as waveguides, couplers, photon generators, filters, switches, detectors, interferometers, delay lines, and the like. For example, the photonic integrated circuit may include single photon generators for generating individual photons, filters and switches that may be tuned or controlled by thermo-optic devices or other tuners, and single photon detectors to detect individual photons. The different types of integrated optical components may operate at different temperatures. For example, the single photon detector may include superconducting nanowire single photon detector that may operate at low temperature, while the thermo-optic device may operate at a much higher temperature.

According to certain embodiments, the photonic integrated circuit may include isolation structures fabricated using CMOS back end of line (BEOL) processes to prevent ambient light or stray light from reaching the photodetector directly or indirectly. The isolation structures may include, for example, metal layers, arrays of vias, air gaps, trenches filled with reflective or absorptive materials, and the like. The isolation structures may provide local and/or global isolations to photodetectors and/or waveguides at different locations including the input ports and output ports of the photonic integrated circuit and the photodetector, such that any scattered, reflected, diffused, or otherwise leaked light from either the light source or the photonic integrated circuit is partially or fully blocked and thereby prevented from reaching the photodetector.

Systems, devices, and methods disclosed herein can improve the signal to noise ratio of the photodetector by preventing undesired light from reaching the highly sensitive photodetector. As such, the photodetector may achieve a high sensitivity and may have a minimum amount of dead time. The isolation structures may be fabricated using standard CMOS back end of line (BEOL) processes or CMOS-compatible BEOL processes. Some isolations may be local isolations, and no additional global layers or materials may be needed in the stack-up, and hence no additional thermal loads may be added to the circuit and device.

According to certain embodiments, the photonic integrated circuit may include thermal isolation structures, such as trenches and large undercut regions adjacent to heat generating devices. The thermal isolation structures may also be fabricated using CMOS or other semiconductor processing techniques, such as photolithography and wet/dry etching. The thermal isolation structures may keep the heat in a localized region to both improve the efficiencies of the thermo-optic device and reduce the burden for cooling regions that may need to operate in low temperature.

DETAILED DESCRIPTION

Techniques disclosed herein relate generally to photonic integrated circuit. More specifically, this disclosure relates to techniques for integrating different types of components on a monolithic photonic integrated circuit. The monolithic photonic integrated circuit includes optical and/or thermal isolation structures. Various inventive embodiments are described herein, including methods, processes, systems, devices, and the like.

According to certain embodiments, the photonic integrated circuit may include various combination of different types of integrated optical components, such as waveguides, couplers, photon generators, filters, switches, detectors, interferometers, delay lines, and the like. For example, the photonic integrated circuit may include a photonic integrated circuit for optical quantum computing, and may include single photon generators for generating individual photons, filters and switches that may be tuned or controlled by thermo-optic devices or other tuners, and single photon detectors to detect individual photons. The different types of integrated optical components may operate at different temperatures. For example, the single photon detector may include superconducting nanowire single photon detector that may operate at low temperature, while the thermo-optic device may operate at a much higher temperature.

The monolithic photonic integrated circuit may include optical isolation structures for preventing background light from reaching a highly sensitive photodetector (e.g., a single photon detector) in a photonic integrated circuit (PIC) in order to achieve the high sensitivity and high signal to noise ratio (SNR). The monolithic photonic integrated circuit may also include thermal isolation structures to reduce or prevent heat dissipation from some thermo-optic devices to other regions of the photonic integrated circuit. The monolithic photonic integrated circuit with optical and/or thermal isolation structures may be manufactured using a combination of semiconductor processing techniques.

Photodetectors with high light sensitivity, such as single photon detectors (SPDs, e.g., superconducting nanowire SPDs (SNSPDs)) used in many photonic quantum technologies, may be very sensitive to many kinds of light radiation. In many cases, the highly sensitive photodetectors may not achieve the sensitivity or SNR that they can potentially achieve due to various noise sources, such as noise caused by background light including stray light in a system or ambient light entering the system. Techniques disclosed herein can reduce or prevent undesired background light (such as stray light or ambient light) from reaching a highly sensitive photodetector (e.g., superconducting nanowire single photon detector) in a photonic integrated circuit in order to achieve high sensitivity and high signal to noise ratio.

According to certain embodiments, in order to improve the sensitivity and the SNR of a photodetector, the photodetector (e.g., SNSPD) may be optically isolated from background radiation (e.g., ambient light or stray light) using reflective or absorptive structures surrounding the photodetector. In some embodiments, additional isolation structures may be added at any other location in the PIC where background light may otherwise propagate before reaching the photodetector, so as to reduce the number of stray photons that may reach the region of the photodetector. For example, because one main source of background or stray light in a photonic integrated circuit is the light reflected, scattered, or diffused at optical input and/or output ports (e.g., input or output waveguide couplers) of the PIC due to imperfect coupling of light into or out of the PIC (e.g., waveguides), isolation structures may be used at the optical input and/or output ports to prevent stray light from entering the interior of the PIC. As such, the probability that any stray light or ambient light may enter the waveguides or reach the region of the photodetector may be significantly reduced. Furthermore, even if any background light reaches the region where the photodetector is located, the local isolation structures surrounding the photodetector may block the background light to prevent it from being detected by the photodetector. In various embodiments, the light isolation structures may be fabricated using standard CMOS back end of line (BEOL) processes or other CMOS-compatible fabrication processes.

According to certain embodiments, the photonic integrated circuit may include heaters for tuning some integrated optical components, such as optical filters, optical switches, optical interferometers, and the like. The photonic integrated circuit may also include thermal isolation structures, such as trenches and large undercut regions adjacent to the heaters. The thermal isolation structures may keep the heat in a localized region to both improve the efficiencies of the thermo-optic device and reduce the burden for cooling regions including devices that may need to operate in low temperature, such as the SNSPDs. The thermal isolation structures may also be fabricated using CMOS or other semiconductor processing techniques, such as photolithography and wet/dry etching.

Several illustrative embodiments will now be described with respect to the accompanying drawings, which form a part hereof. The ensuing description provides embodiment(s) only and is not intended to limit the scope, applicability, or configuration of the disclosure. Rather, the ensuing description of the embodiment(s) will provide those skilled in the art with an enabling description for implementing one or more embodiments. It is understood that various changes may be made in the function and arrangement of elements without departing from the spirit and scope of this disclosure. In the following description, for the purposes of explanation, specific details are set forth in order to provide a thorough understanding of certain inventive embodiments. However, it will be apparent that various embodiments may be practiced without these specific details. The figures and description are not intended to be restrictive. The word “example” or “exemplary” is used herein to mean “serving as an example, instance, or illustration.” Any embodiment or design described herein as “exemplary” or “example” is not necessarily to be construed as preferred or advantageous over other embodiments or designs.

FIG.1is a simplified block diagram illustrating an example of an optical device100including a photonic integrated circuit (PIC)120and a highly sensitive photodetector130according to certain embodiments. PIC120may include photonic circuits formed by waveguides and other active or passive optical components, such as filters, resonators, splitters, optical amplifiers, and the like. The optical device may include a light source, such as a laser110, which may be an ultra-fast (e.g., picosecond or femtosecond) pulsed laser. In some embodiments, the light source may be an external source and may be connected to PIC120through, for example, one or more optical fibers. Light from the light source may be coupled into the waveguides in PIC120through a coupler, such as a grating coupler, an edge coupler, or the like. However, it may be difficult to achieve a very high coupling efficiency. For example, in many cases, the coupling efficiency may be less than 90%, less than 75%, less than 60%, or less than 50%. Therefore, a large amount of light from the light source may not enter the waveguides in PIC120, and may instead be reflected, scattered, or diffused and become stray light140. Stray light140may be reflected, refracted, diffracted, or otherwise deflected by structures or components in optical device100, such as metal layers, interfaces between different materials, and the like. Therefore, a portion of stray light140may eventually reach photodetector130. In addition, some portions of PIC120may also leak light from the desired path. For example, light may be coupled out of a waveguide, instead of being guided within the photonic circuit to reach photodetector130, for example, when the waveguide has a sharp turn or when there are defects in the waveguide or other photonic circuits. Light leaked out from the photonic circuits may become stray light150, which may also be deflected at least partially to photodetector130. In some embodiments, ambient light may also enter PIC120, for example, through the oxide layers and/or be reflected by metal layers.

Photodetector130may be a highly sensitive photodetector, such as a single photon detector. For example, in some embodiments, photodetector130may include a superconducting nanowire single photon detector that can detect individual photons. In one embodiment, photodetector130may include a waveguide coupled to a superconducting nanowire, such as a niobium-germanium nanowire, which may have a ultralow resistance in the superconducting state. The superconducting nanowire may be photosensitive or photoactive, such as absorptive for photons. For example, photons passing through the waveguide may be absorbed by the superconducting nanowire and cause the superconducting nanowire to become non-superconducting (i.e., changing resistance or impedance). The resistance or impedance change in the nanowire may be converted into an electrical detection signal (e.g., a current or voltage signal) that indicates one or more photons are detected.

When at least a portion of stray light140and150reaches photodetector130, it may cause the superconducting nanowire to change state, and photodetector130may generate a detection signal indicating that one or more photons are detected even through no photon reaches the superconducting nanowire from the waveguide, or the magnitude of the detection signal may not correctly indicate the number of photons reaching the photodetector from the waveguide. Thus, false detection signals or incorrect (e.g., noisy) detection signals may be generated by photodetector130, which may reduce the effective sensitivity or SNR of photodetector130.

According to certain embodiments, light isolation structures may be added at different locations of optical device100to block the stray light or ambient light from reaching photodetector130. For example, an isolation structure160may be added at the input port of PIC120, an isolation structure170may be fabricated to surround photodetector130, and an isolation structure180may be added anywhere in optical device100where background light may otherwise propagate. More details of some embodiments of the light isolation structures and their fabrication processes are described in the following examples.

FIG.2illustrates an example of stray light isolation at input and/or output ports of a photonic integrated circuit200according to certain embodiments.FIG.2shows a cross-section view of PIC200, which may include a waveguide210fabricated on a substrate205(e.g., a silicon handle wafer). PIC200may also include an input port220for waveguide210and an output port230for waveguide210. Waveguide210may carry light from input port220into the interior of PIC200, where some photosensitive components may be located, or may guide light out of PIC200through output port230.

As described above, light may not be perfectly coupled into or out of waveguide210at input port220or output port230. A significant portion of input light or output light may enter PIC200through paths other than waveguide210. In some cases, in each laser pulse, about 1012photons may enter PIC200as stray light. To prevent these photons from reaching the interior of PIC200, one or more light isolation structure may be fabricated at the input port and/or the output port. For example, as illustrated inFIG.2, PIC200may include one or more metal trenches240and one or more deep trenches260that may act as isolation structure160shown inFIG.1. Metal trenches240may include a metal layer that is sufficiently thick to block (e.g., reflect or absorb) incident photons. Metal trenches240may act as a mirror-like barrier and may extend from, for example, metal1(M1, which may be about 1 μm above waveguide210), down to substrate205(which may be about 2-3 μm below waveguide210) to block light that may propagate in the cladding of waveguide210from reaching the interior of PIC200. Deep trenches260may extend through substrate205of PIC200, and may be empty (i.e., air gaps) or may be filled with reflective or absorptive materials to at least partially reflect or absorb incident photons that may propagate in or may be scattered from substrate205, such that the photons may not enter the cladding of the waveguide.

Gaps250may exist between adjacent metal trenches240such that waveguide210may pass through the gaps between metal trenches240. Gaps270may exist between adjacent deep trenches260such that waveguide210may be supported by the substrate at gaps270. As shown inFIG.2, gaps250and gaps270may not be aligned and may be offset from each other by a certain distance, such that gaps250may not be in the line of sight of stray photons from input port220, and thus stray photons from input port220may not pass though gaps250and may instead be blocked by metal trenches240.

FIG.3illustrates an example of locally isolating a photodetector350using various isolation structures in a photonic integrated circuit300according to certain embodiments. PIC300may include a substrate305(e.g., a silicon handle wafer). A waveguide310may be formed on substrate305, where waveguide310may include multiple turns to change directions. Light isolation structures, such as a top metal cover320, metal trenches330, and deep trenches340, may be fabricated in PIC300to surround and isolate waveguide310and photodetector350. The light isolation structures shown inFIG.3may be a specific embodiment of isolations structure170ofFIG.1, and may form an isolation structure that may be compared to a castle-like structure.

As illustrated inFIG.3, waveguide310may carry signal light from photonic circuits in PIC300to photodetector350(e.g., an SNSPD), where the signal light may be detected. Similar to deep trenches260, deep trenches340may include an air gap that passes completely through substrate305or may be filled with reflective or absorptive materials. In some embodiments, deep trenches340may pass partially through substrate305. Deep trenches may isolate photodetector350from light that may propagate in or may be scattered from substrate305. Metal trenches330may be similar to metal trenches240and may create a mirror-like barrier that may extends from M1down to substrate305as described above with respect toFIG.2. In some embodiments, metal trenches330may include multiple nested rings centered around photodetector350, where an inner ring may be enclosed by one or more outer rings. Each ring may include an opening where waveguide310may pass through. The opening in each ring may be on a different side (e.g., an opposite side or an adjacent side) with respect to the opening in an adjacent ring. Metal trenches330may block light that may propagate in the cladding of waveguide310from reaching photodetector350. Top metal cover320may serve as a roof of the light isolation structure, which may be compared to a castle-like structure, and may prevent light from reaching photodetector350from the top of photodetector350and PIC300.

FIGS.4A-4Dillustrate another example of locally isolating a photodetector470using various isolation structures in an optical device400according to certain embodiments.FIG.4Ais a cross-sectional view of optical device400including photodetector470and light isolation structures surrounding photodetector470.FIG.4Bis a perspective view of optical device400shown inFIG.4A. Optical device400may include a substrate410(e.g., a silicon handle wafer), a barrier oxide (BOX) layer420(e.g., silicon dioxide), a waveguide440formed on top of BOX layer420, and a low temperature oxide (LTO) layer430covering waveguide440. Optical device400may also include an array of vias450and a top metal cover460that may be formed on metal1layer.

FIG.4Cis a top view of optical device400ofFIG.4A.FIG.4Cshows top metal cover460covering photodetector470from the top such that background light may not reach photodetector470from the top, where top metal cover460may be a part of the metal1layer.

FIG.4Dis a top view of a cross-section of optical device400ofFIG.4A.FIG.4Dshows the arrangement of the array of vias450and photodetector470. As illustrated, the array of vias450may be arranged in a two-dimensional array, where vias in one row (or column) may be offset from vias in adjacent rows (or columns) such that the array of vias may effectively form a wall. Photodetector470may include a photoactive nanowire480(e.g., a niobium-germanium nanowire) on waveguide440.

FIG.5is a flow chart500illustrating an example method of fabricating various light isolation structures in a photonic integrated circuit according to certain embodiments. Even thoughFIG.5describes the operations in a sequential flow, some of the operations may be performed in parallel or concurrently. Some operations may be performed in a different order. An operation may have additional steps not included in the figure. Some operations may be optional, and thus may be omitted in various embodiments. Some operations may be performed together with another operation.

Optionally, at block510, a waveguide layer may be formed on a barrier oxide layer of a PIC, such as BOX layer420shown inFIGS.4A and4B. The waveguide layer may be patterned and etched using, for example, photolithography techniques, to form the waveguide core and/or input/output couplers. At block520, a photoactive layer, such as a niobium-germanium layer, may be deposited on top of the waveguide layer. The photoactive layer may be patterned and etched to form a nanowire on an area of the waveguide core. Processing at block510and block520may be part of the front end of line processes in the CMOS processes.

FIG.6is a cross-sectional view of an example of a photonic integrated circuit600including a photodetector manufactured using the front end of line processes at blocks510and520according to certain embodiments. PIC600may include a substrate610(e.g., a silicon handle wafer), a BOX layer620formed on substrate610, various devices (e.g., optical input/output coupler640, waveguide650, and a photodetector including a waveguide660and a nanowire670including a photoactive material) on a device layer, and an oxide layer630covering the device layer. Optical input/output coupler640may include a grating coupler. Oxide layer630and BOX layer620may act as the cladding of waveguide650. In one example, oxide layer630may have a thickness of about 1 μm.

At block530, vias or trenches may be etched in the oxide layers down to the substrate. For example, a patterned mask layer may be formed on the oxide layers (e.g., the LTO layer and BOX layer), and wet or dry etching techniques may be used to etch vias (holes) or trenches in the oxide layers, which may have a total thickness of, for example, 3-4 μm.

FIG.7is a cross-sectional view of an example of a photonic integrated circuit700with vias or trenches710etched in oxide layers using back end of line (BEOL) processes at block530according to certain embodiments. PIC700may be made from PIC600. Vias or trenches710may be etched through oxide layer630and BOX layer620down to substrate610.

At block540, the vias or trenches may be filled with reflective or absorptive materials, such as metal materials. For example, metal layers may be deposited on the oxide layers and selectively etched in one or more cycles to form metal plugs in the vias or trenches.

FIG.8is a cross-sectional view of an example of a photonic integrated circuit800with the vias or trenches etched in the oxide layers filled with reflective or absorptive materials (e.g., metals such as copper, aluminum, cobalt, tungsten, etc.) using the BEOL process at block540according to certain embodiments. PIC800may be made from PIC700, where vias or trenches710may be filled with metal plugs810.

At block550, standard CMOS BEOL processing techniques may be used to deposit a metal1layer on the oxide layers and etch the metal1layer to leave a top metal cover in an area on top of the photodetector. The top metal cover may be aligned with the vias or trenches that are filled with reflective or absorptive materials, such as metals. Therefore, the top metal cover and the vias or trenches may block background light from at least 3 (e.g., top, left, and right) or 5 (e.g., top, left, right, front, and rear) directions.

FIG.9is a cross-sectional view of an example of a photonic integrated circuit900with a top metal cover910fabricated as part of a metal layer for locally isolating the photodetector using the BEOL process at block550according to certain embodiments. PIC900may be made from PIC800and may include the additional top metal cover910formed as part of the metal1layer. Top metal cover910may be positioned above (e.g., on top of) the photodetector that includes waveguide660and nanowire670. Top metal cover910may be in contact with metal plugs810in vias or trenches710to block light from top, left, and right directions in the 2-D cross-sectional view.

Optionally, at block560, other BEOL processes may be performed to form, for example, additional dielectric (e.g., oxide) layers and upper metal layers (e.g., metal2, metal3, etc.). The BEOL processes may include standard CMOS BEOL processes.

FIG.10is a cross-sectional view of an example of a photonic integrated circuit1000after the additional BEOL processes at block560according to certain embodiments. PIC1000may be made from PIC900and may include additional metal layers1010and upper level metal layers, such as metal layer1020.

At block570, the substrate may be etched from the backside to form deep trenches in the substrate from the backside. The deep trenches may reflect photons propagating within the substrate at interfaces between the substrate material and the air gap. For example, total internal reflection may occur when photons are incident at a certain angle on the interface from the substrate material to the air gap.

FIG.11is a cross-sectional view of an example of a photonic integrated circuit1100including deep trenches1110etched in a substrate of the photonic integrated circuit using the BEOL process at block570according to certain embodiments. PIC1100may be made from PIC1000and may include deep trenches1110in substrate610. Deep trenches1110may be offset from metal plugs810. For example, deep trenches1110may be slightly farther away from the photodetector than metal plugs810to prevent light from circumventing metal plugs810from substrate610and bottom side of BOX layer620and reaching the photodetector.

Optionally, at block580, the deep trenches may be filled with reflective or absorptive materials that may block light, such as metal materials.

FIG.12is a cross-sectional view of an example of a photonic integrated circuit1200including the deep trenches in the substrate filled with reflective or absorptive materials using the process at block580according to certain embodiments. PIC1200may be made from PIC1100, and may include reflective or absorptive materials1210, such as metal materials, filled in deep trenches1110.

FIG.13is a cross-sectional view of photonic integrated circuit1200illustrating light isolation by various isolation structures in the photonic integrated circuit according to certain embodiments. Light from a laser may be sent to PIC1200through an input fiber1310, which may include a collimator, such as a GRIN lens or a micro lens. Input light1320from input fiber1310may propagate through the oxide layers and may be partially coupled into the waveguides in PIC1200by optical input/output coupler640, which may include slanted gratings in some embodiments.

Light that is not coupled into the waveguides by optical input/output coupler640may be scattered in various directions. For example, a portion of input light1320may be reflected at the interface between substrate610and BOX layer620as light1330, which may be further reflected by metal layer1020as light1370that may be blocked by one of metal plugs810. A portion of input light1320may be scattered as light1335, which may propagate towards a metal plug810and blocked by the metal plug. A portion of input light1320may be scattered at the bottom surface of substrate610, where one portion of scattered light1350may be blocked by the reflective or absorptive material1210in a deep trench1110, and another portion of scattered light1340may be blocked by a metal plug810.

Light1360scattered or otherwise leaked from waveguide650may also be blocked by a metal plug810from reaching the photodetector. Ambient light1380that may enter the oxide layers from the top or stray light reflected by various metal layers may be blocked by top metal cover910on top of the photodetector, and thus may not reach the photodetector either. In this way, only photons guided in waveguide660may reach the photodetector, and thus background noises can be significantly reduced or substantially eliminated. As such, a high sensitivity and a high SNR may be achieved by the photodetector.

In various embodiments, other dielectric layers used in CMOS processing may be used to replace one or more oxide layers (e.g., silicon dioxide layers) described above. For example, the dielectric layers may include silicon nitride, alkali halides, barium titanate, lead titanate, tantalum oxide, tungsten oxide, zirconium oxide, and the like.

The highly sensitive photodetectors described above may be used to detect individual photons in quantum computing or quantum cryptography. For example, single photon sources may be used in many photonic quantum technologies. An ideal single photon source would generate single photons deterministically. One way to achieve a deterministic single photon source is to use cascaded (or multiplexed) heralded photon sources based on, for example, spontaneous four wave mixing (SFWM) or spontaneous parametric down-conversion (SPDC) in passive nonlinear optical media. In each heralded photon source (HPS), photons may be non-deterministically produced in pairs (which includes a signal photon and an idler photon), where one photon (e.g., signal photon) heralds the existence of the other photon (e.g., idler photon) in the pair. Thus, if a signal photon is detected by a highly sensitive photodetector (e.g., a single photon detector as described above) at one heralded photon source, the corresponding idler photon can be used as the output of the single photon source, while other heralded photon sources in the cascaded (or multiplexed) heralded photon sources of the single photon source can be bypassed or switched off.

FIG.14is a flow chart1400illustrating an example method of fabricating a photonic integrated circuit according to certain embodiments. More specifically,FIG.14shows one example of an integration flow for forming thermal isolation structures, scattered light mitigation structures, photodetectors, and metal contacts on and within a base photonic integrated circuit (PIC). Other combinations of elements are possible without departing from the scope of the present disclosure. For example, the method may not include the steps for forming the thermal isolations structures or other structures, such as additional photonic structures formed in one or more additional photonic layers.

In step1401, the base PIC is provided. This base PIC can be any integrated circuit structure, and thus the example shown here is not intended to limit the scope of the present disclosure. In some embodiments, the base PIC can be provided as an output of any earlier sequence of processing steps, for example, silicon photonics processing steps for processing a silicon on insulator (SOI) wafer, and the like.

An example of one type of base PIC that can be provided in step1401is shown inFIG.15. The base PIC may include a PIC stack1501. PIC stack1501includes a multi-layer photonic integrated circuit stack, including a substrate1524(e.g., a silicon handle wafer), a first oxide layer1520, a waveguide layer1521, and a spacer/protective cap layer1522. In some embodiments, a second oxide layer1518can be disposed between the waveguide layer1521and the spacer/protective capping layer1522. The waveguide layer1521can be patterned to include various photonic components, including one or more input coupler regions1503, waveguide regions1505, heater regions1507, thermal isolation trench regions1509, photonics switch regions1511, photon detector regions1513, photon detector contact regions1515, and/or scatter mitigation structure regions1517. One of ordinary skill in the art will appreciate that the number, ordering, and position of the various regions and components shown here are merely illustrative and any arrangement is possible without departing from the scope of the present disclosure.

In some embodiments, the input coupler region1503can include any type of photonic input/output structure(s), such as a grating coupler1519. The photonic input/output structure can be previously formed in a waveguide layer1521, such as in a Si layer, a SiN layer, or any other material suitable for integrated photonics. The waveguide region1505can include one or more waveguides1523that can be part of one or more photonic structures and/or photonic components. For example, within the waveguide layer1521, waveguide structures can be used to form input/output structures (such as grating couplers), light routing structures (such as straight linear waveguides and waveguide bends), light generation structures (such as coupled microring photon sources), switch structures (such as Mach-Zehnder interferometers (MZI)), coupling structures (such as directional couplers), optical filters (e.g., wavelength-division multiplexed (WDM) wavelength filters), photonic delay line structures, and the like.

In the example illustrated inFIG.15, the structures within the waveguide layer are arranged in a pictorial manner to facilitate the description of the manufacturing process. One of ordinary skill will appreciate that the precise arrangement of the components (and interconnection between the components) can vary widely depending on the application for which the PIC is designed. As such, the waveguide layer1521shown is intended to represent any possible combination of photonic components that can be designed using one or more waveguides as building blocks.

Heater region1507can also be part of one or more optical components, such as filters, microrings, and MZIs (not shown), and can be used to thermally tune these structures. In some embodiments, a heater1525(e.g., a strip heater) can be located in the heater region1507. In some embodiments, heater1525can be formed in the waveguide layer1521, and may include a doped silicon (n- or p-doped silicon) layer1525aand a capping layer1525bformed of silicide, such as cobalt silicide, nickel silicide, or any other silicide. While the heater region1507is shown to be adjacent to the waveguide1523inFIG.15, other embodiments can employ silicide and/or metal heaters that are fabricated on top of the waveguide1523and can employ doped Si with a silicide top layer, metal materials such as TiN, TaN, or any other suitable heater material.

In some embodiments, thermal isolation trench region1509is adjacent to heater region1507such that a trench and undercut (not shown) can be formed in silicon oxide and silicon regions in subsequent processes to provide thermal isolation around heater1525, as described in more detail below in reference toFIGS.19-20. Such a trench and undercut can not only lead to more power efficient operation of the heater1525(by causing a reduced heating of the adjacent oxide layer and substrate) but also can provide thermal isolation between the region of the PIC that includes the heater1525(which may have a local temperature of 150 K-200 K) and the region of the PIC that includes the photon detectors (which may be at cryogenic temperatures, e.g., have a local temperature of 3 K-20 K, e.g., 4 K, 10 K, etc.). In some embodiments, many heaters may be used to tune many photonic components (e.g., single photon sources, filters, MZIs, etc.) that are located in close proximity to one another, the thermal isolation regions can prevent cross-talk between the heating of the components, such that one heater for heating a respective component may only minimally heat an adjacent component due to the thermal isolation properties of the thermal isolation structures that are formed in the thermal isolation regions. In some embodiments, thermal tuning may not be necessary and thus the heaters and heater regions may not be present.

In some embodiments, the photonics switch region1511includes any suitable photonic switch1527, such as a p-n switch, a p-i-n switch, a DC Kerr switch, a Pockels effect switch, or any other type of optical switch.

In some embodiments, the photon detector region1513and photon detector contact region1515can employ any waveguide integrated photon detection technology. For example, shown here in cross-section is a superconducting nanowire single photon detector1529. The photon detector region1513and photon detector contact region1515may include, for example, an AlN layer1530, a NbN layer1532, an amorphous silicon layer1534, and a silicon oxide layer1536. Details of the photon detector region1513and photon detector contact region1515are described below.

Surrounding the photon detector region1513can be a scatter mitigation structure region1517that can include one or more scatter mitigation structures (not shown) fabricated therein, such as the scatter mitigation structures described above in reference toFIGS.1-13.

In accordance with some embodiments, the base PIC can be covered with a spacer/protective cap layer1522shown inFIG.15, such as a SiN layer. Spacer/protective cap layer1522can be previously conformally deposited on top of the base PIC wafer. In other embodiments, the base PIC can include a planarized capping layer or any other layer without departing from the scope of the present disclosure.

Referring back toFIG.14, in step1403, the base PIC is prepared for a first lithography process. While the lithography processes referred to herein employs tri-layer lithography, any lithographic technique can be used without departing from the scope of the present disclosure.FIG.16shows examples of additional layers that can be deposited for use in a tri-layer lithography process. For example, a planarization layer1603can be deposited on the previously formed spacer layer (e.g., spacer/protective cap layer1522). Examples of planarization layer1603include organic planarization layers, such as a spin-on hard mask (SOH), organic planarizing layer (OPL), or any other layer or material that can be used to planarize the topography of the top layer of the base PIC. An anti-reflective coating1605can be deposited on top of the planarizing layer. Examples of anti-reflective coating1605include silicon-based anti-reflective coating (SiARC), bottom anti-reflective coating (BARC), and the like. On top of anti-reflective coating1605is deposited a photoresist layer1607, which can be lithographically patterned according to known methods. In the example shown inFIG.16, the photoresist layer1607is patterned to protect certain portions of the spacer layer (e.g., nitride layer) that are located on top of the heater, switch, and photon detector contact regions, as shown inFIG.16.

In step1405, a first etch process is performed to pattern the spacer/protective cap layer1522(e.g., a nitride layer). For example, the anti-reflective coating1605and planarization layer1603are etched in the regions that do not contain the photoresist (acting as an etch mask), resulting in the etched PIC structure1701shown inFIG.17, where spacers/caps1705(e.g., silicon nitride) remain on the top portions of the heater contact regions, switch contact regions, and photon detector contact regions. More generally, the photoresist can be lithographically patterned in any way that preserves islands of the SiN layer. These islands can be used as, for example, etch stops during the subsequent contact formation etch process.

In step1407, an oxide deposition process (e.g., using middle of the line (MOL) SiO2deposition) is performed to form an oxide layer1803on the etched PIC as shown inFIG.18.

In steps1409, the patterned base PIC is prepared for a second lithography process. In this process, another layer deposition and lithographic patterning of the photoresist is performed as in step1403.

In step1411, a second etch process is performed to generate a deep trench1903in the thermal isolation region (e.g., thermal isolation trench region1509) as shown inFIG.19. The deep trench1903, referred to herein as a “deep trench,” is a trench in the PIC stack that can extend all the way to the substrate1524. Any suitable etch process can be used to etch the deep trench. Etching processes, such as oxide etching processes and the like, can be employed without departing from the scope of the present disclosure. In some embodiments, the etch can be a selective etch that etches the oxide but not the Si substrate. The etching process can be an anisotropic etching process to etch the deep trench1903.

At step1413, an undercut2003is etched in the substrate1524at the base of the deep trench1903, as shown inFIG.20. Such an undercut can be formed using a combination of dry and wet etch processes. The dry etch can be sulfur hexafluoride, a chlorine etch, or any other dry etch process that is a selective etch that will etch silicon but not oxide, such that only the silicon at the base of the deep trench1903is etched while the oxide layers above are preserved. A wet etch can then be performed using, for example, tetramethylammonium hydroxide (TMAH), KOH, or any other suitable etchants. In some embodiments, the etching of the silicon occurs along the 111 crystal plane (e.g., at about 54 degrees). Such an etch results in the undercut2003having angled walls resultant from etching the silicon.

FIG.21illustrates one example of a heater2103and a full undercut structure2105in accordance with some embodiments. Full undercut structure2105may be an example of undercut2003shown inFIG.20, and may be formed using etch processes described above with respect toFIG.20. In some embodiments, undercut structure2105can be positioned underneath any photonic device2109that employs a heater. Thermal isolation from deep trenches and undercut structure2105may reduce or prevent heat loss into the surrounding substrate2107. Examples of photonic devices2109include single photon sources, optical filters, Mach-Zehnder interferometers, micro ring resonators, or any other structures that may use thermal tuning and/or switching. InFIG.21, an example is shown where two deep trenches2105aand2105bare each formed on a respective side of the waveguide and heaters in order to thermally isolate the heater elements from the surrounding regions, including the substrate (referred to here as the silicon handle) and the oxide layers. In some embodiments, a cooling member can be in thermal contact with the substrate to provide a head sink to the PIC during operation. For circuits that operate at cryogenic temperatures, the cooling member can be part of a larger cryostat that is cryogenically cooled. In such scenarios, without a thermal undercut structure disposed between the heater and the cooling structure, much of the heat generated by the heater may be shunted directly to the cooling structure, thereby negatively impacting the heating efficiency of the heater, and/or unnecessarily increasing the heat load on the cryogenic cooling system.

In step1415, as illustrated inFIG.22, an oxide layer2210is deposited on the PIC stack that includes deep trenches and undercuts for thermal isolation formed therein. The oxide layer2210may be planarized, for example, via chemical mechanical polishing (CMP). In some embodiments, oxide layer2210is deposited without breaking vacuum and thus seals the deep trench undercut regions such that these regions are kept sealed under vacuum. Keeping the deep trench and undercut regions under vacuum can improve the thermal isolation capabilities of the deep trench undercut structures by eliminating the most effective heat transfer mechanisms within the voids. For example, heat transfer through the deep trench occurs mainly via radiative transfer and more efficient processes such as diffusion, convection, and the like, are minimized.

In steps1417, a patterned photoresist layer2301may be formed on the PIC stack for a third lithography process as shown inFIG.23. In this process, another layer deposition and lithographic patterning of the photoresist is performed as in step1403. For example, the patterned photoresist layer2301may be formed on a planarization layer2305and an antireflection coating layer2303. In this case, patterning is performed to form etch mask for etching silicide contact holes.

In step1419, an oxide etch process can be performed to etch oxide layer2210, followed by a SiN punch process to etch spacers/caps1705, thereby forming silicide contact holes2401for making contact with the silicide layer (e.g., capping layer1525b), as shown inFIG.24.

In step1421, a lithography preparation, lithography, and etch processes are performed in a manner similar to the above. For example, as shown inFIG.25, a patterned photoresist layer2501may be formed on a planarization layer2505and an antireflection coating layer2503. In this case, the photoresist layer2501is patterned to allow for etching of the photon detector contact holes, stopping at the appropriate layer of the photon detector, for example, at the amorphous silicon layer. As shown in FIG.26, the planarization layer2505(e.g., SOH or OPL layer) may be removed to open up silicide contact holes2401and photon detector contact holes2601.

In step1423, metal silicide contacts2701are formed as illustrated inFIG.27. For example, a liner layer2703can first be deposited in the contact holes (e.g., silicide contact holes2401and photon detector contact holes2601). In some embodiments, the liner layer2703can be formed from tungsten, tungsten carbide, tungsten nitride, or any other suitable liner. After the liner layer deposition, an anneal step can be performed to form silicide regions2705at the bottom of the metal silicide contacts2701for detector contact, such as the amorphous silicon layer1534. Following the silicide formation, a metallization process is performed to fill the contact holes with a suitable contact metal2707, such as, for example, tungsten, copper, aluminum, cobalt, and the like. In some embodiments, before the silicide formation, a cleaning step can be performed to clean the amorphous silicon. Any suitable cleaning step can be used, such as a chemical cleaning step, argon sputter, and the like.

In step1425, a scatter mitigation structure2801is formed using a lithography and etch process, as illustrated inFIG.28. In some embodiments, the scatter mitigation structure2801can be formed in a deep trench that lands on the substrate1524. In other embodiments, the scatter mitigation structure2801can be formed in a through silicon via (TSV)-like trench as shown inFIG.28. After the trench is etched, an oxide liner2803is formed to prevent the fill material (that subsequently fills the scatter mitigation structure2801) from reacting with the silicon. A metal liner layer2805, such as a Ti—Cu barrier and seed layer, may then be formed on oxide liner2803, before filling the scatter mitigation structure with a fill material2807(e.g., a metal, such as copper). The fill material2807may have a thermal expansion coefficient (CTE) similar to substrate1524and/or oxide. In some embodiments, the TSV-like scatter mitigation structure can be on the order of10of microns deep, e.g., 40-60 microns deep and thus, is much deeper than the thermal isolation trench (which can be a factor of 10 less deep).

In some implementations, operations or processing may involve physical manipulation of physical quantities. Typically, although not necessarily, such quantities may take the form of electrical or magnetic signals capable of being stored, transferred, combined, compared, or otherwise manipulated. It has proven convenient at times, principally for reasons of common usage, to refer to such signals as bits, data, values, elements, symbols, characters, terms, numbers, numerals, or the like. It should be understood, however, that all of these or similar terms are to be associated with appropriate physical quantities and are merely convenient labels. Unless specifically stated otherwise, as apparent from the discussion herein, it is appreciated that, throughout this specification, discussions utilizing terms such as “processing,” “computing,” “calculating,” “determining,” or the like refer to actions or processes of a specific apparatus, such as a special purpose computer, special purpose computing apparatus or a similar special purpose electronic computing device. In the context of this specification, therefore, a special purpose computer or a similar special purpose electronic computing device is capable of manipulating or transforming signals, typically represented as physical electronic or magnetic quantities within memories, registers, or other information storage devices, transmission devices, or display devices of the special purpose computer or similar special purpose electronic computing device.

In the preceding detailed description, numerous specific details have been set forth to provide a thorough understanding of claimed subject matter. However, it will be understood by those skilled in the art that claimed subject matter may be practiced without these specific details. In other instances, methods and apparatuses that would be known by one of ordinary skill have not been described in detail so as not to obscure claimed subject matter. Therefore, it is intended that claimed subject matter not be limited to the particular examples disclosed, but that such claimed subject matter may also include all aspects falling within the scope of appended claims, and equivalents thereof.