Marks for locating patterns in semiconductor fabrication

Embodiments of semiconductor fabrication methods are disclosed. In an example, a method for forming a mark for locating patterns in semiconductor fabrication is disclosed. A wafer is divided into a plurality of shots. Each of the plurality of shots includes a semiconductor chip die. Four quarters of a locking corner mark are subsequently patterned, respectively, at four corners of four adjacent shots of the plurality of shots. Each quarter of the locking corner mark is symmetric to adjacent quarters of the locking corner mark and is separated from the adjacent quarters of the locking corner mark by a nominally same distance. The locking corner mark is set as an origin for locating patterns in at least one of the four adjacent shots in semiconductor fabrication.

BACKGROUND

Embodiments of the present disclosure relate to semiconductor fabrication methods.

In semiconductor fabrication, various types of measurement need to be performed after lithography exposure, including measuring critical dimensions of patterns in the wafer shots using critical dimension scanning electron microscopes (CD-SEM) and measuring overlay offsets between different layers using overlay metrology systems. Thus, a mark with a distinguishable pattern at a specific position in each shot becomes necessary to define a coordinate system of the shot. After lithography exposure and development, the mark can be patterned on the wafer and used as the origin to build up the coordinate system for each shot for subsequent measurements, such as critical dimension measurements and overlay offset measurements.

SUMMARY

Embodiments of semiconductor fabrication methods are disclosed herein.

In one example, a method for forming a mark for locating patterns in semiconductor fabrication is disclosed. A wafer is divided into a plurality of shots. Each of the plurality of shots includes a semiconductor chip die. Four quarters of a locking corner mark are subsequently patterned, respectively, at four corners of four adjacent shots of the plurality of shots. Each quarter of the locking corner mark is symmetric to adjacent quarters of the locking corner mark and is separated from the adjacent quarters of the locking corner mark by a nominally same distance. The locking corner mark is set as an origin for locating patterns in at least one of the four adjacent shots in semiconductor fabrication.

In another example, a method for forming a locking corner mark in semiconductor fabrication is disclosed. A first quarter of the locking corner mark is patterned at a first corner of a first shot of a wafer. After patterning the first quarter of the locking corner mark, a second quarter of the locking corner mark is patterned at a second corner of a second shot of the wafer. The second corner is adjacent to the first corner. The first and second quarters of the locking corner mark are symmetric and separated. Each of the first and second quarters of the locking corner mark includes an array of repetitive patterns.

In still another example, a method for forming a mark for locating patterns in semiconductor fabrication is disclosed. A wafer is divided into a plurality of shots. Four quarters of a locking corner mark are subsequently patterned, respectively, at four corners of four adjacent shots of the plurality of shots. Each quarter of the locking corner mark has an “L” shape and is exposed by only one lithography process. The locking corner mark is set as an origin for locating patterns in at least one of the four adjacent shots in semiconductor fabrication.

DETAILED DESCRIPTION

As used herein, the term “3D memory device” refers to a semiconductor device with vertically oriented strings of memory cell transistors (referred to herein as “memory strings,” such as NAND memory strings) on a laterally-oriented substrate so that the memory strings extend in the vertical direction with respect to the substrate. As used herein, the term “vertical/vertically” means nominally perpendicular to the lateral surface of a substrate.

In fabricating some semiconductor device, such as 3D memory devices, four identical cross-shaped marks are normally patterned at the four corners, respectively, of each shot on a wafer. The mark at the lower-left corner is used as the origin of a coordinate system of the shot for locating and measuring patterns (e.g., device patterns, testing patterns, alignment marks, etc.) during the fabrication processes. For example,FIG. 1illustrates a plan view of four adjacent shots102-1,102-2,102-3, and102-4(collectively referred to as “shorts102” or individually referred to as “each shot102”) of a wafer each having marks104for locating patterns in semiconductor fabrication. For shots102-1,102-2,102-3, and102-4shown inFIG. 1, shot102-1has an adjacent shot102-2in a first direction (x-direction) and another adjacent shot102-3in a second direction (y-direction) perpendicular to the first direction. Each shot102has a rectangle shape, and each mark104has a cross shape. Four marks104are patterned at each of the four corners of each shot102. As patterns (including marks104) in different shots are patterned by different lithography processes, each mark104may be exposed to light by multiple lithography processes when adjacent shots are subsequently patterned. For example, mark104-1at the center of four adjacent shots102-1,102-2,102-3, and102-4may be exposed four times by four lithography processes.

However, the above-mentioned mark design encounters various deficiencies and limitations. For example, for shots having patterns with small feature sizes (e.g., 100 nm), a mark with line patterns (e.g., having a minimum width of 2 μm) is not allowed to be arranged on the same photomask (also known as “reticle”) due to limitations imposed by design rules. In particular, arranging line patterns on the same photomask as contact vias should be avoided because of their significant shape and size differences. Moreover, the repeated exposures to the same mark by multiple lithography processes also increase the merge risk of the patterns of the mark, which can potentially damage the mark, even the size of the patterns can be reduced. Using other patterns on the photomask as the origin for establishing the coordinate system of a shot may also increase the complexity of measurement steps because other patterns are usually less distinguishable than the cross-shaped marks at the corners.

Various embodiments in accordance with the present disclosure provide improved marks for locating and measuring patterns in semiconductor fabrication. In some embodiments, a locking corner mark is divided into four quarters, which are subsequently patterned at four corners of four adjacent shots, respectively, to avoid repeated exposures to any quarter of the locking corner mark by multiple lithography processes, thereby reducing the merge risk of small-sized patterns. Thus, each quarter of the locking corner mark can be further divided into an array of repetitive patterns with a feature size comparable to that of device patterns in the same shot. In some embodiments, the locking corner mark formed by the four separate quarters still has a distinguishable shape, such as the crossed-shape, which can be easily used as the origin for future measurement steps.

FIG. 2illustrates a plan view of an exemplary shot202of a wafer200having four quarter marks208for locating patterns in semiconductor fabrication, according to some embodiments of the present disclosure. As used herein, a “wafer” is a piece of a semiconductor material for semiconductor devices to build in and/or on it and that can undergo various fabrication processes before being separated into dies. Wafer200can include a plurality of shots202. During the lithography process, each shot202located in a grid pattern on wafer200is exposed in turn as wafer200is stepped back and forth under a lens of a stepper, according to some embodiments. For example, once wafer200coated with a photoresist layer and a photomask (not shown) with desired patterns are in place and aligned, the wafer stage of the stepper, which is moved in the x- and y-directions (front to back and left to right) by worm screws or linear motors, carries wafer200so that the first of shots202to be exposed on it is located below the lens, directly under the photomask. A process program (also known as a “recipe”) can determine the length of the exposure, the photomask used, as well as other factors that affect the exposure. Exposed wafer200can be eventually moved to a developer where the photoresist on its surface is exposed to developing chemicals that wash away areas of the photoresist, based on whether they were exposed to the light passing through the photomask.

As shown inFIG. 2, each shot202can include one or more semiconductor chip dies204. Each semiconductor chip die204is a small block of semiconductor material of wafer200on which a given functional circuit (e.g., a semiconductor device) is fabricated. The semiconductor device that can be fabricated on semiconductor chip die204can include any suitable logic devices (e.g., central processing unit (CPU), graphic processing unit (GPU), and application processor (AP)), volatile memory devices (e.g., dynamic random-access memory (DRAM) and static random-access memory (SRAM)), non-volatile memory devices (e.g., NAND Flash memory, NOR Flash memory), or any combinations thereof in a 2D, 2.5D, or 3D architecture. Various types of device patterns with different shapes and/or sizes can be formed on semiconductor chip die204during different fabrication stages including, but not limited to, implantation areas, interconnect lines, contact vias, channels, trenches, plates, etc.

In some embodiments, each shot202further includes process control and monitor (PCM) regions206surrounding semiconductor chip dies204, for example, close to the edges and corners of shot202. PCM regions206can locate in scribing lines210in the x- and y-directions along which shot202can be diced from wafer200. In PCM regions206, various non-functional patterns (in contrast to functional device patterns on semiconductor chip dies204) can be formed, such as pads for thickness and critical dimension inline monitor, alignment marks for lithography alignment and overlay measurement, test-keys for wafer acceptance test (WAT) and reliability test, etc. At wafer package stage, part or the entirety of PCM regions206can be cut off and no longer detectable.

As shown inFIG. 2, each shot202can have a rectangle shape with four corners at which four corner PCM regions206-1,206-2,206-3, and206-4are located. Four quarter marks208-1,208-2,208-3, and208-4are formed in respective corner PCM region206-1,206-2,206-3, and206-4at the four corners of shot202, respectively. As will be described below in detail, instead of having four identical full marks (e.g.,104inFIG. 1), each quarter mark is a quarter of a full mark for locating patterns in semiconductor fabrication. For example,FIG. 3illustrates a plan view of four adjacent shots202-1,202-2,202-3, and202-4each having four quarter marks208-1,208-2,208-3, and208-4(collectively referred to as “quarter marks208” or individually referred to as “each quarter mark208”) for locating patterns in semiconductor fabrication, according to some embodiments of the present disclosure. Four quarter marks208-4,208-3,208-2, and208-1in four adjacent shots202-1,202-2,202-3, and202-4, respectively, can constitute a full mark302at the center of four adjacent shots202-1,202-2,203-3, and202-4. Since each shot202is individually exposed once, each quarter mark208will not be over-exposed for multiple times, according to some embodiments. Full mark302can be set as the origin for defining a coordinate system (e.g., having x-axis and y-axis) for at least one of four adjacent shots202-1,202-2,202-3, and202-4(e.g., upper-right shot202-2) and locating patterns in corresponding shot202in semiconductor fabrication. In some embodiments, four adjacent shots202-1,202-2,202-3, and202-4are patterned in scribing lines (in the x-direction and y-direction) and thus, are removed when dicing wafer200along the scribing lines to separate four adjacent shots202-1,202-2,202-3, and202-4from wafer200.

FIG. 4Aillustrates a plan view of an exemplary quarter406of a locking corner mark (also referred to herein as a “locking corner mark quarter”) in a cell region400, according to some embodiments of the present disclosure. In semiconductor device design, cell regions400are the basic units of the layout for arranging patterns. Each cell region400can have the same shape and size determined based on the design rules of fabricating the semiconductor device. Locking corner mark quarter406is arranged within cell region400that is at one of the corners of a shot, according to some embodiments. For example, cell region400may have a square shape with each side A of 16.9 μm. As shown inFIG. 4A, cell region400can be divided into four sub-regions, each of which has a square shape with each side B of 8.45 μm (i.e., B=A/2), and locking corner mark quarter406can be patterned in one of the sub-regions that is at the corner of the shot. For example, for cell region400at the upper-right corner of the shot, locking corner mark quarter406may be patterned in the upper-right sub-region of cell region400, as shown inFIG. 4A. During lithography process for patterning locking corner mark quarter406, the upper-right sub-region in which locking corner mark quarter406is to be patterned is exposed to the light (and is referred to herein as an “exposure area404”), while the remaining sub-regions are prevented from exposure (and are referred to herein as a “non-exposure area402”). Exposure area404is one quarter of the size of cell region400, according to some embodiments. It is understood that in some embodiments, the side B of exposure area404is not half of the side A of cell region400, and exposure area404is not one quarter of the size of cell region400.

In some embodiments, locking corner mark quarter406has an “L” shape having two arms of the same size. It is understood that, locking corner mark quarter406can have two arms of different sizes or have other shapes. As will be described below, four “L”-shaped locking corner mark quarters406can constitute a cross-shaped locking corner mark when they are patterned in four adjacent shots, respectively. As shown inFIG. 4A, each arm of locking corner mark quarter406has a feature width C and a feature length D.

In some embodiments, locking corner mark quarter406is a single pattern (e.g., in a continuous, enclosed area). The feature size (e.g., the feature width C) of the single pattern (e.g., the “L”-shaped pattern) of locking corner mark quarter406is greater than about 1 μm, such as greater than 1 μm. In some embodiments, the feature size (e.g., the feature width C) of the single pattern is between about 1 μm and about 10 μm, such as between 1 μm and 10 μm (e.g., 1 μm, 2 μm, 3 μm, 4 μm, 5 μm, 6 μm, 7 μm, 8 μm, 9 μm, 10 μm, any range bounded by the lower end by any of these values, or in any range defined by any two of these values). In some embodiments, the feature size of locking corner mark quarter406(e.g., the feature width C) is determined based on the feature size of patterns (e.g., device patterns) in the corresponding semiconductor chip die (not shown) of the same shot. The feature size of locking corner mark quarter406(e.g., the feature width C) can be about the same as the feature size of the patterns in the corresponding semiconductor chip die. For example, for an implantation photomask, the implantation patterns may have a feature size of about 2 μm, and the feature size of locking corner mark quarter406(e.g., the feature width C) may be about 2 μm as well. The feature length D can be between the feature width C and the side B of exposure area404.

As shown inFIG. 4A, another dimension related to locking corner mark quarter406is the distance E from the edge of cell region400. In some embodiments, the distance E is greater than 0, meaning that there is a margin between locking corner mark quarter406and the edge of cell region400. The margin can prevent the formation of fine photoresist lines on the wafer when an overlay shift occurs between adjacent shots, which can cause photoresist peeling defect. For example,FIG. 4Billustrates a plan view of an exemplary locking corner mark408formed by four quarters406-1,406-2,406-3, and406-4(collectively referred to as “four quarters406” or individually referred to as “each locking corner mark quarter406”) of locking corner mark408in four adjacent shots, according to some embodiments of the present disclosure. Each locking corner mark quarter406is symmetric to adjacent locking corner mark quarters406and is separated from its adjacent locking corner mark quarters by a nominally same distance2E, according to some embodiments. The distance2E between two adjacent locking corner mark quarters (either in the x-direction or y-direction) can serve as the margin for preventing photoresist peeling defect due to overlay shift.

In some embodiments, first locking corner mark quarter406-1is first patterned at the lower-right corner of the upper-left shot, and second locking corner mark quarter406-2is then patterned at the lower-left corner of the upper-right shot. The lower-right corner at which first locking corner mark quarter406-1is patterned is adjacent to the lower-left corner at which second locking corner mark quarter406-2is patterned in the x-direction, according to some embodiments. In some embodiments, third locking corner mark quarter406-3is patterned at the upper-right corner of the lower-left shot, and fourth locking corner mark quarter406-4is then patterned at the upper-left corner of the lower-right shot. The lower-right corner at which first locking corner mark quarter406-1is patterned is adjacent to the upper-right corner at which third locking corner mark quarter406-3is patterned in the y-direction, according to some embodiments. The lower-left corner at which second locking corner mark quarter406-2is patterned is adjacent to the upper-left corner at which fourth locking corner mark quarter406-4is patterned in the y-direction, according to some embodiments. The upper-right corner at which third locking corner mark quarter406-3is patterned is adjacent to the upper-right corner at which fourth locking corner mark quarter406-4is patterned in the x-direction, according to some embodiments. For any locking corner mark quarter406, it is symmetric to one adjacent locking corner mark quarter406in the x-direction and another adjacent locking corner mark quarter406in the y-direction. It is understood that the order of forming four locking corner mark quarters406-1,406-2,406-3, and406-4is not limited by the embodiments described above and can be any other suitable order in other embodiments. Nevertheless, once four locking corner mark quarters406-1,406-2,406-3, and406-4are patterned, they can constitute locking corner mark408having a cross shape at the center of the four adjacent shots.

FIG. 5illustrates a plan view of an exemplary quarter500of a locking corner mark including an array of repetitive patterns502, according to some embodiments of the present disclosure. In some embodiments, instead of having a single pattern (e.g., as shown inFIGS. 4A and 4B), locking corner mark quarter500includes an array of repetitive patterns502to reduce the pattern feature size of locking corner mark quarter500. This design can match the pattern feature size of locking corner mark quarter500with smaller pattern feature sizes of certain semiconductor chip dies including, but not limited to, semiconductor chip dies on which interconnect lines and contact vias are patterned.

The feature size of each repetitive pattern502(e.g., a square-shaped pattern) of locking corner mark quarter500is not greater than about 200 nm, such as not greater than 200 nm. In some embodiments, the feature size of each repetitive pattern502is between about 20 nm and about 200 nm, such as between 20 nm and 200 nm (e.g., 20 nm, 30 nm, 40 nm, 50 nm, 60 nm, 70 nm, 80 nm, 90 nm, 100 nm, 110 nm, 120 nm, 130 nm, 140 nm, 150 nm, 160 nm, 170 nm, 180 nm, 190 nm, 200 nm, any range bounded by the lower end by any of these values, or in any range defined by any two of these values). In some embodiments, the feature size of each repetitive pattern502is determined based on the feature size of patterns (e.g., device patterns) in the corresponding semiconductor chip die (not shown) of the same shot. The feature size of each repetitive pattern502can be about the same as the feature size of the patterns in the corresponding semiconductor chip die. For example, for a contact via photomask, the contact via patterns may have a feature size of about 100 nm, and the feature size of each repetitive pattern502may be about 100 nm as well.

It is understood that the shape of repetitive patterns502is not limited to the square shape as shown inFIG. 5and can be any other shapes, such as a circle shape, a rectangle shape, etc. In some embodiments, the shape of repetitive patterns502is nominally the same as the shape of the device patterns (e.g., circle shape of contact via patterns) in the corresponding semiconductor chip die. By matching the sizes and shapes of repetitive patterns502in locking corner mark quarter500with the device patterns of the same shot, the same optical proximity correction (OPC) can be applied to repetitive patterns502and the device patterns, thereby ensuring the uniformity of pattern quality on the wafer.

FIG. 6illustrates an image of an exemplary locking corner mark formed by four quarters of a locking corner marks each including an array of repetitive patterns, according to some embodiments of the present disclosure. As shown inFIG. 6, a cross-shaped locking corner mark is patterned at the center of four adjacent shots, which is formed by four “L”-shaped locking corner mark quarters patterned in the respective shot. Each “L”-shaped locking corner mark quarter is symmetric to two adjacent “L”-shaped locking corner mark quarters in the x-direction and y-direction, respectively. Each “L”-shaped locking corner mark quarter is also separated from the two adjacent “L”-shaped locking corner mark quarters in the x-direction and y-direction, respectively, by the same margin. As each shot includes only a quarter of the full cross-shaped locking corner mark, repeated exposures can be avoided for any “L”-shaped locking corner mark quarter when patterning the full cross-shaped locking corner mark. Moreover, each “L”-shaped locking corner mark quarter includes an array of repetitive patterns to match the feature size and/or shape with the device patterns on the same wafer (not shown).

FIG. 7is a flowchart of an exemplary method700for forming a mark for locating patterns in semiconductor fabrication, according to some embodiments of the present disclosure. Examples of the mark depicted inFIG. 7include marks depicted inFIGS. 2, 3, 4A, 4B, and 5. It is understood that the operations shown in method700are not exhaustive and that other operations can be performed as well before, after, or between any of the illustrated operations. Further, some of the operations may be performed simultaneously, or in a different order than shown inFIG. 7.

Referring toFIG. 7, method700starts at operation702, in which a wafer is divided into a plurality of shots. Each of the plurality of shots can include a semiconductor chip die. It is understood that the wafer is “divided” with respect to the design layout, as opposed to being physically cut off at operation702. As illustrated inFIG. 2, wafer200is divided into multiple shots202, each of which includes one or more semiconductor chip dies204.

Method700proceeds to operation704, in which patterns are formed in a semiconductor chip die in each shot of the wafer. In some embodiments, the patterns in the semiconductor chip die include interconnect lines and contact vias.

Method700proceeds to operation706, in which four quarters of a locking corner mark are subsequently patterned at four corners of four adjacent shots, respectively. In some embodiments, each quarter of the locking corner mark has an “L” shape and is exposed by only one lithography process. In some embodiments, each quarter of the locking corner mark is symmetric to adjacent quarters of the locking corner mark and is separated from the adjacent quarters of the locking corner mark by a nominally same distance. As illustrated inFIG. 4B, each quarter406of locking corner mark408is symmetric to adjacent quarters406of locking corner mark408and is separated from adjacent quarters406of locking corner mark408by the same distance2E.

In some embodiments, each quarter of the locking corner mark is a single pattern having a feature size that is about the same as a feature size of patterns in the corresponding semiconductor chip die of the same shot. As illustrated inFIG. 4B, each quarter406of locking corner mark408is a single “L”-shaped pattern. In some embodiments, each quarter of the locking corner mark includes an array of repetitive patterns each having a feature size that is about the same as a feature size of patterns in the corresponding semiconductor chip die of the same shot. As illustrated inFIG. 5, each quarter500of the locking corner mark includes an array of repetitive patterns502.

In some embodiments, each quarter of the locking corner mark is patterned in an exposure area that is one quarter of a cell size of the corresponding shot. As illustrated inFIG. 4A, locking corner mark quarter406is patterned in exposure area404that is one quarter of the size of cell region400. To subsequently pattern the four quarters of the locking corner mark, respectively, each of four lithography processes is subsequently applied on a respective one of the four exposure areas, such that each quarter of the locking corner mark is exposed by only one of the four lithography processes.

In some embodiments, a first quarter of the locking corner mark is patterned at a first corner of a first shot of a wafer, and a second quarter of the locking corner mark is patterned at a second corner of a second shot of the wafer after patterning the first quarter of the locking corner mark. The second corner can be adjacent to the first corner. As illustrated inFIG. 4B, first locking corner mark quarter406-1is patterned at the lower-right corner of the upper-left shot, and after that, second locking corner mark quarter406-2is patterned at the lower-left corner of the upper-right shot. The lower-right corner at which first locking corner mark quarter406-1is patterned is adjacent to the lower-left corner at which second locking corner mark quarter406-2is patterned in the x-direction. In some embodiments, to pattern the first quarter of the locking corner mark, a first lithography process is applied only on the exposure area in the first shot. In some embodiments, to pattern the second quarter of the locking corner mark, after applying the first lithography process, a second lithography process is applied only on the exposure area in the second shot.

Method700proceeds to operation708, in which the locking corner mark is set as an origin for locating patterns in at least one of the four adjacent shots in semiconductor fabrication. As illustrated inFIG. 3, locking corner mark302is at the center of four adjacent shots202-1,202-2,202-3, and202-4and can be set as the origin for locating patterns in at least one of four adjacent shots202-1,202-2,202-3, and202-4, such as upper-right shot202-2, in semiconductor fabrication.

Method700proceeds to operation710, in which the wafer is diced along scribing lines in which the four quarters of the locking corner mark are patterned to separate the four adjacent shots from the wafer. The locking corner mark thus can be removed from the final semiconductor device. As illustrated inFIG. 2, wafer200can be diced along scribing lines210in the x-direction and y-direction in which four quarters208-1,208-2,208-3, and208-4of the locking corner mark are patterned to separate four adjacent shots202from wafer200.

According to one aspect of the present disclosure, a method for forming a mark for locating patterns in semiconductor fabrication is disclosed. A wafer is divided into a plurality of shots. Each of the plurality of shots includes a semiconductor chip die. Four quarters of a locking corner mark are subsequently patterned, respectively, at four corners of four adjacent shots of the plurality of shots. Each quarter of the locking corner mark is symmetric to adjacent quarters of the locking corner mark and is separated from the adjacent quarters of the locking corner mark by a nominally same distance. The locking corner mark is set as an origin for locating patterns in at least one of the four adjacent shots in semiconductor fabrication.

In some embodiments, each quarter of the locking corner mark has an “L” shape.

In some embodiments, each quarter of the locking corner mark is a single pattern having a feature size that is about the same as a feature size of patterns in the corresponding semiconductor chip die of the same shot. The feature size is greater than about 1 μm, according to some embodiments.

In some embodiments, each quarter of the locking corner mark includes an array of repetitive patterns each having a feature size that is about the same as a feature size of patterns in the corresponding semiconductor chip die of the same shot. The feature size is not greater than about 200 nm, according to some embodiments.

In some embodiments, each quarter of the locking corner mark is patterned in an exposure area that is one quarter of a cell size of the corresponding shot. In some embodiments, to subsequently pattern the four quarters of the locking corner mark, respectively, each of four lithography processes is subsequently applied on a respective one of the four exposure areas, such that each quarter of the locking corner mark is exposed by only one of the four lithography processes.

In some embodiments, the locking corner mark is at a center of the four adjacent shots.

In some embodiments, the wafer is diced along scribing lines in which the four quarters of the locking corner mark are patterned to separate the four adjacent shots from the wafer.

According to another aspect of the present disclosure, a method for forming a locking corner mark in semiconductor fabrication is disclosed. A first quarter of the locking corner mark is patterned at a first corner of a first shot of a wafer. After patterning the first quarter of the locking corner mark, a second quarter of the locking corner mark is patterned at a second corner of a second shot of the wafer. The second corner is adjacent to the first corner. The first and second quarters of the locking corner mark are symmetric and separated. Each of the first and second quarters of the locking corner mark includes an array of repetitive patterns.

In some embodiments, patterns are formed in a semiconductor chip die of the wafer. A feature size of each repetitive pattern in the first and second quarters of the locking corner mark is about the same as a features size of the patterns in the semiconductor chip die. The feature size is not greater than about 200 nm, according to some embodiments. The feature size can be about 100 nm. In some embodiments, the patterns in the semiconductor chip die include interconnect lines and contact vias.

In some embodiments, each of the first and second quarters of the locking corner mark has an “L” shape.

In some embodiments, each of the first and second quarters of the locking corner mark is patterned in an exposure area that is one quarter of a cell size of the corresponding shot. In some embodiments, to pattern the first quarter of the locking corner mark, a first lithography process is applied only on the exposure area in the first shot. In some embodiments, to pattern the second quarter of the locking corner mark, a second lithography process is applied only on the exposure area in the second shot.

In some embodiments, the wafer is diced along scribing lines in which the first and second quarters of the locking corner mark are patterned to separate the four adjacent shots from the wafer.

According to still another aspect of the present disclosure, a method for forming a mark for locating patterns in semiconductor fabrication is disclosed. A wafer is divided into a plurality of shots. Four quarters of a locking corner mark are subsequently patterned, respectively, at four corners of four adjacent shots of the plurality of shots. Each quarter of the locking corner mark has an “L” shape and is exposed by only one lithography process. The locking corner mark is set as an origin for locating patterns in at least one of the four adjacent shots in semiconductor fabrication.

In some embodiments, each quarter of the locking corner mark is symmetric to adjacent quarters of the locking corner mark and is separated from the adjacent quarters of the locking corner mark by a nominally same distance.

In some embodiments, each quarter of the locking corner mark is patterned in an exposure area that is one quarter of a cell size of the corresponding shot.

In some embodiments, the wafer is diced along scribing lines in which the four quarters of the locking corner mark are patterned to separate the four adjacent shots from the wafer.

In some embodiments, patterns are formed in a semiconductor chip die in each of the plurality of shots. In some embodiments, each quarter of the locking corner mark is a single pattern having a feature size that is about the same as a feature size of the patterns in the corresponding semiconductor chip die of the same shot. The feature size is greater than about 1 μm, according to some embodiments. In some embodiments, each quarter of the locking corner mark includes an array of repetitive patterns each having a feature size that is about the same as a feature size of the patterns in the corresponding semiconductor chip die of the same shot. The feature size is not greater than about 200 nm, according to some embodiments.

In some embodiments, the locking corner mark is at a center of the four adjacent shots.