Substrate module, display apparatus, and liquid crystal antenna

A substrate module, a display apparatus, and a liquid crystal antenna are provided in the present disclosure. The substrate module includes a first substrate. The first substrate includes a first sub-region and a second sub-region; the second sub-region includes a binding region; and the binding region includes first pins. The first sub-region includes first loads, and a first sub-pin is electrically connected to the first load. The second sub-region includes at least one second load, and a second sub-pin is electrically connected to the second load. The second load includes a capacitor including a first capacitor. The first substrate includes a first base substrate, a first electrode layer, a first insulating layer and a second electrode layer. Along a direction perpendicular to a plane of the base substrate, an overlapping portion of a first electrode portion and a second electrode portion forms the first capacitor.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims the priority of Chinese Patent Application No. 202210621782.5, filed on Jun. 1, 2022, the content of which is incorporated herein by reference in its entirety.

TECHNICAL FIELD

The present disclosure generally relates to the field of communication technology and, more particularly, relates to a substrate module, a display apparatus, and a liquid crystal antenna.

BACKGROUND

In the existing technology, in order to drive and control devices in a substrate through a drive chip, the pins in the drive chip need to be connected to the pins in the substrate, and such structure is widely used in various fields. When the number of pins in the drive chip is greater than the number of pins in the substrate, some pins in the drive chip may be in a floating state, thereby affecting drive chip performance.

SUMMARY

One aspect of the present disclosure provides a substrate module. The substrate module includes a first substrate. The first substrate includes a first sub-region and a second sub-region; the second sub-region is on a side of the first sub-region along a first direction; the second sub-region includes a binding region; the binding region includes a plurality of first pins arranged along a second direction; and the first direction intersects the second direction. The plurality of first pins includes at least one first sub-pin and at least one second sub-pin; the first sub-region includes a plurality of first loads, and a first sub-pin is electrically connected to a first load of the plurality of first loads; the second sub-region includes at least one second load, and a second sub-pin is electrically connected to a second load; the second load includes a capacitor including a first capacitor; the first substrate includes a first base substrate, and further includes a first electrode layer, a first insulating layer and a second electrode layer which are sequentially arranged on a side of the first base substrate; the first electrode layer includes a first electrode portion; the second electrode layer includes a second electrode portion; and the second electrode portion is electrically connected to the second sub-pin; and along a direction perpendicular to a plane of the base substrate, the first electrode portion is at least partially overlapped with the second electrode portion; and an overlapping portion of the first electrode portion and the second electrode portion forms the first capacitor.

Another aspect of the present disclosure provides a display apparatus including a substrate module. The substrate module includes a first substrate. The first substrate includes a first sub-region and a second sub-region; the second sub-region is on a side of the first sub-region along a first direction; the second sub-region includes a binding region; the binding region includes a plurality of first pins arranged along a second direction; and the first direction intersects the second direction. The plurality of first pins includes at least one first sub-pin and at least one second sub-pin; the first sub-region includes a plurality of first loads, and a first sub-pin is electrically connected to a first load of the plurality of first loads; the second sub-region includes at least one second load, and a second sub-pin is electrically connected to a second load; the second load includes a capacitor including a first capacitor; the first substrate includes a first base substrate, and further includes a first electrode layer, a first insulating layer and a second electrode layer which are sequentially arranged on a side of the first base substrate; the first electrode layer includes a first electrode portion; the second electrode layer includes a second electrode portion; and the second electrode portion is electrically connected to the second sub-pin; and along a direction perpendicular to a plane of the base substrate, the first electrode portion is at least partially overlapped with the second electrode portion; and an overlapping portion of the first electrode portion and the second electrode portion forms the first capacitor.

Another aspect of the present disclosure provides a liquid crystal antenna including a substrate module. The substrate module includes a first substrate. The first substrate includes a first sub-region and a second sub-region; the second sub-region is on a side of the first sub-region along a first direction; the second sub-region includes a binding region; the binding region includes a plurality of first pins arranged along a second direction; and the first direction intersects the second direction. The plurality of first pins includes at least one first sub-pin and at least one second sub-pin; the first sub-region includes a plurality of first loads, and a first sub-pin is electrically connected to a first load of the plurality of first loads; the second sub-region includes at least one second load, and a second sub-pin is electrically connected to a second load; the second load includes a capacitor including a first capacitor; the first substrate includes a first base substrate, and further includes a first electrode layer, a first insulating layer and a second electrode layer which are sequentially arranged on a side of the first base substrate; the first electrode layer includes a first electrode portion; the second electrode layer includes a second electrode portion; and the second electrode portion is electrically connected to the second sub-pin; and along a direction perpendicular to a plane of the base substrate, the first electrode portion is at least partially overlapped with the second electrode portion; and an overlapping portion of the first electrode portion and the second electrode portion forms the first capacitor.

DETAILED DESCRIPTION

Various exemplary embodiments of the present disclosure are be described in detail with reference to the accompanying drawings. It should be noted that unless specifically stated otherwise, relative arrangement of components and steps, numerical expressions and numerical values described in these embodiments may not limit the scope of the present disclosure.

The following description of at least one exemplary embodiment may be merely illustrative and may not be used to limit the present disclosure and its application or use.

The technologies, methods, and apparatuses known to those skilled in the art may not be discussed in detail, but where appropriate, the technologies, methods, and apparatuses should be regarded as a part of the present disclosure.

In all examples shown and discussed herein, any specific value should be interpreted as merely exemplary, rather than as a limitation. Therefore, other examples in exemplary embodiment may have different values.

It should be noted that similar reference numerals and letters indicate similar items in the following drawings. Therefore, once an item is defined in one drawing, it does not need to be further discussed in the subsequent drawings.

FIG.1illustrates a planar schematic of a substrate module according to various embodiments of the present disclosure;FIG.2illustrates a structural schematic of a second sub-region in the substrate module inFIG.1; andFIG.3illustrates a cross-sectional view of the substrate module along a B-B′ direction inFIG.2. Referring toFIGS.1-3, various embodiments may provide a substrate module. The substrate module may include a first substrate10; the first substrate10may include a first sub-region A1and a second sub-region A2; the second sub-region A2may be on a side of the first sub-region A1along the first direction X; the second sub-region A2may include a binding region A21; the binding region A21may include a plurality of first pins20arranged along the second direction Y; and the first pin20may be configured for electrical connection with the pin in the drive chip (not shown inFIGS.1-3), where the first direction X may intersect the second direction Y. Optionally, the first direction X may be perpendicular to the second direction Y.

Optionally, in the COG (Chip on Glass) process, the pins in the drive chip may be directly electrically connected to the first pins20in the substrate module. Optionally, in the COF (Chip on Flex) process, the pins in the drive chip may be electrically connected to the pins in the flexible circuit board (not shown inFIGS.1-3), and the pins in the flexible circuit board may be electrically connected to the first pins20in the substrate module, thereby realizing that the pins in the drive chip may be electrically connected to the first pins in the substrate module.

The plurality of first pins20in the first substrate10may include at least one first sub-pin21. The first sub-region A1may include a plurality of first loads30. The first sub-pin21may be electrically connected to the first load30. When the devices in the first sub-region A1need to be driven and controlled by the drive chip, the first sub-pins21may be electrically connected to the pins of the drive chip. Optionally, the second sub-region A2may further include a fan-out line40, and the first sub-pin21may be electrically connected to the first load30in the first sub-region A1through the fan-out line40.

The plurality of first pins20in the first substrate10may further include at least one second sub-pin22. The second sub-region A2may include at least one second load50; and the second sub-pin22may be electrically connected to the second load50. When the number of pins in the drive chip is greater than the number of the first sub-pins21in the first substrate10, the pins in the drive chip that are not electrically connected to the first sub-pin21may be extra pins. The extra pins in the drive chip have the function of outputting signals. The extra pins in the drive chip may be electrically connected to the second sub-pins22. The second loads50may be disposed in the second sub-region A2, and the second sub-pins22may be electrically connected to the second loads50, so that extra pins in the drive chip may be electrically connected to the second loads50. Therefore, certain pins in the drive chip may be avoided to be in a floating state, and the working performance of the drive chip may be effectively improved.

Meanwhile, since the pins in the drive chip that are not electrically connected to the first sub-pins21may be electrically connected to the second sub-pins22, that is, pins in the drive chip that are not electrically connected to the first sub-pins21may be electrically connected to the second loads50. Therefore, the number of pins in the drive chip may not need to be same as the number of the first sub-pins21in the first substrate10. In such way, it may avoid that one drive chip may only be applied to a substrate with a specific number of first sub-pins21, and the application scope of the drive chip may be effectively expanded; and there is no need to provide different drive chips for substrates with different numbers of the first sub-pins21, which may effectively reduce the fabrication cost.

For example, the second load50may include a capacitor C1; and the capacitor C1may include a first capacitor C11. The first substrate10may include a first base substrate11, and include a first electrode layer12, a first insulating layer13and a second electrode layer14which are sequentially arranged on a side of the first base substrate11. The first insulating layer13may be disposed between the first electrode layer12and the second electrode layer14, so that the first electrode layer12and the second electrode layer14may be insulated from each other. The first electrode layer12may include a first electrode portion121; the second electrode layer14may include a second electrode portion141; and the first electrode portion121and the second electrode portion141may be insulated from each other. Along the direction perpendicular to the plane where the base substrate11is located, the first electrode portion121and the second electrode portion141may be at least partially overlapped with each other. The overlapping portion of the first electrode portion121and the second electrode portion141may form the first capacitor C11. The first electrode portion121and the second electrode portion141may be both disposed in the second sub-region A2. Along the direction perpendicular to the plane of the base substrate11, the overlapping portion of the first electrode portion121and the second electrode portion141may form the first capacitor C11, so that the first capacitor C11may be disposed in the second sub-region A2. The second electrode portion141of the first capacitor C11may be electrically connected to the second sub-pin22, so that the second sub-pin22may be electrically connected to the first capacitor C11.

It should be noted that,FIGS.1-2exemplarily illustrate that the first substrate10includes eight first sub-pins21and sixteen second sub-pins22. In other embodiments of the present disclosure, the first substrate10may further include other numbers of first sub-pins21and second sub-pins22, which may not be limited in the present disclosure.

It should be noted that in the present disclosure, all first pins20(the first sub-pins21and the second sub-pins22) may be disposed in a same layer. The first sub-pin21and the second sub-pin22inFIGS.1-2use different patterns to mark the first sub-pin21and the second sub-pin22which may be only for the purpose of clearly illustrating the first sub-pin21and the second sub-pin22and may not indicate that the first sub-pin21and the second sub-pin22are disposed in different film layers. Related labeling manners are also applied in the drawings of other embodiments of the present disclosure, which may not be described in detail in the present disclosure.

FIG.4illustrates a planar schematic of another substrate module according to various embodiments of the present disclosure;FIG.5illustrates a structural schematic of the second sub-region in the substrate module inFIG.4; andFIG.6illustrates a cross-sectional view of the substrate module along a C-C′ direction inFIG.5. Referring toFIGS.4-6, in some optional embodiments, the plurality of first pins20in the first substrate10may further include at least one third sub-pin23. The first electrode portion121may be electrically connected to the third sub-pin23. The drive chip may transmit signals to the first electrode portion121through the third sub-pin23and transmit signals to the second electrode portion141through the second sub-pin22, so that different signals may be transmitted to the first electrode portion121and the second electrode portion141respectively. Therefore, along the direction perpendicular to the plane of the base substrate11, the overlapping portion of the first electrode portion121and the second electrode portion141may form the first capacitor C11.

Optionally, the drive chip may transmit a common voltage signal to the first electrode portion121through the third sub-pin23, that is, the first pin20configured for transmitting the common voltage signal in the first base10may be reused as the third sub-pin23, which may be beneficial for reducing the area of the second sub-region A2and reduce the fabrication cost.

Referring toFIGS.4-6, in some optional embodiments, the first capacitor C1may be between the first sub-region A1and the binding region A21.

For example, the region between the first sub-region A1and the binding region A21may be a wiring region. The fan-out line40electrically connected to the first sub-pin21may be located in the wiring region. The first capacitor C1may be located between the first sub-region A1and the binding region A21. That is, the first capacitor C1may be disposed in the wiring region of the first substrate10, thereby effectively reducing the area of the second sub-region A2.

FIG.7illustrates another structural schematic of the second sub-region in the substrate module inFIG.4;FIG.8illustrates a cross-sectional view of the substrate module along a D-D′ direction inFIG.7; andFIG.9illustrates a cross-sectional view of the substrate module along a E-E′ direction inFIG.7. Referring toFIGS.4and7-9, the structure of the third sub-pin23in the substrate module described inFIG.7refers toFIG.6. In some optional embodiments, the first pin20may include a first sub-portion201and a second sub-portion202which are electrically connected with each other, the first sub-portion201may be located at the second electrode layer14, and the second sub-portion202may be located at the first electrode layer12. That is, the first sub-portion201and the second sub-portion202in the first pin20may be connected in parallel, which may effectively improve the conductivity of the first pin20.

Each first pin20in the first substrate10may be designed in a same manner. For example, the first sub-pin21may include a first sub-portion201aand a second sub-portion202awhich are electrically connected with each other. In the first sub-pin21, the first sub-portion201amay be located in the second electrode layer14, and the second sub-portion202amay be located in the first electrode layer12. The second sub-pin22may include a first sub-portion201band a second sub-portion202bwhich are electrically connected with each other. In the second sub-pin22, the first sub-portion201bmay be located in the second electrode layer14, and the second sub-portion202bmay be located in the first electrode layer12. The third sub-pin23may include a first sub-portion201cand a second sub-portion202cwhich are electrically connected with each other. In the third sub-pin23, the first sub-portion201cmay be located in the second electrode layer14, and the second sub-portion202cmay be located in the first electrode layer12. The structures of the first sub-pin21, the second sub-pin22and the third sub-pin23may use a same design manner, which may be beneficial for improving the reliability of all first sub-pins20.

The second sub-portion202aof the first sub-pin21may be insulated from the first electrode portion121, thereby avoiding mutual signal interference between the first sub-pin21and the first electrode portion121.

Both the second sub-portion202band the first electrode portion121in the second sub-pin22may be located in the first electrode layer12; and both the second sub-portion202band the first electrode portion121in the second sub-pin22may be insulated from each other. Therefore, the signals of the first electrode portion121and the second electrode portion141may be prevented from being same; and along the direction perpendicular to the plane of the base substrate11, the overlapping portion of the first electrode portion121and the second electrode portion141may form the first capacitor C11.

Both the second sub-portion202cand the first electrode portion12in the third sub-pin23may be in the first electrode layer12; and the second sub-portion202cin the third sub-pin23may be connected to the first electrode portion12to realize the electrical connection between the second sub-portion202cand the first electrode portion12in the third sub-pin23.

FIG.10illustrates another structural schematic of the second sub-region in the substrate module inFIG.4; andFIG.11illustrates a cross-sectional view of the substrate module along a F-F′ direction inFIG.10. Referring toFIGS.4,10and11, the structure of the first sub-pin21in the substrate module shown inFIG.10refers toFIG.9; and in some optional embodiments, the capacitive load C1further may include a second capacitor C12.

For example, the first electrode layer12may further include a third electrode portion122. The third electrode portion122may be located in the binding region A21. The third electrode portion122may be located on the side of the second sub-portion201in the second sub-pin22away from the first electrode portion121. The second sub-portion202ain the first sub-pin21, the second sub-portion202bin the second sub-pin22, and the third electrode portion122may all be located in the first electrode layer12; and the second sub-portion202ain the first sub-pin21and the second sub-portion202bin the second sub-pin22may both be insulated from the third electrode portion122. Therefore, the signals on the first sub-pin21, the second sub-pin22and the third electrode portion122may be prevented from interfering with each other.

Along the direction perpendicular to the plane of the base substrate11, the first sub-portion201bin the second sub-pin22may be at least partially overlapped with the third electrode portion122, and the second sub-portion202bin the second sub-pin22may be insulated from the third electrode portion122. Therefore, along the direction perpendicular to the plane of the base substrate11, the overlapping portion of the first sub-portion201bin the second sub-pin22and the third electrode portion122may form the second capacitor C12.

In the first substrate10, by reusing the first sub-portion201bin the second sub-pin22as a side electrode of the second capacitor C12, the second capacitor C12may be formed in the binding region A21, which may satisfy total load requirement of the second load50and be beneficial for reducing the capacitance of the first capacitor C12. Therefore, it is beneficial for reducing the area of the overlapping portion of the first electrode portion121and the second electrode portion141along the direction perpendicular to the plane of the base substrate11and reduce the area of the second sub-region A2.

FIG.12illustrates a cross-sectional view of the substrate module along a G-G′ direction inFIG.10. Referring toFIGS.4, and10-12, in some optional embodiments, the third electrode portion122may be electrically connected to the third sub-pin23, the drive chip may transmit signals to the third electrode portion122through the third sub-pin23, and the signals on the first sub-portion201bin the second sub-pin22and the third electrode portion122may be different. Therefore, along the direction perpendicular to the plane of the base substrate11, the overlapping portion of the first sub-portion201band the third electrode portion122in the second sub-pin22may form the second capacitor C12.

In addition, the drive chip may transmit signals to both the first electrode portion121and the third electrode portion122through the third sub-pin23, and there is no need to additionally set the first pin20to transmit signals to the third electrode portion122, which may be beneficial for reducing the area of the binding region A21and reduce the production cost.

FIG.13illustrates another structural schematic of the second sub-region in the substrate module inFIG.4. Referring toFIGS.4and13, in some optional embodiments, the third electrode portions122, which may each form the second capacitor C12with the first sub-portion201bin each second sub-pin22, may be connected to each other to form an integral structure, which may be beneficial for improving the uniformity of the signals on the third electrode portion122.

FIG.14illustrates a cross-sectional view of the substrate module along a H-H′ direction inFIG.13. Referring toFIGS.4,13and14, in some optional embodiments, along the direction perpendicular to the plane of the base substrate11, the first sub-portion201aand the third electrode portion122in the first sub-pin21may not be overlapped with each other. Therefore, the formation of capacitance between the first sub-portion201aand the third electrode portion122in the first sub-pin21may be avoided, and the influence of the setting of the third electrode portion122to the signal on the first sub-pin21may be avoided, which may ensure normal operation of the devices in the first sub-region A1.

It should be noted that, referring toFIG.10, the first electrode portion121and the third electrode portion122may be electrically connected to the third sub-pin23respectively, and signals may be simultaneously transmitted to the first electrode portion121and the third electrode portion122through the third sub-pin23. In other embodiments of the present disclosure, referring toFIG.15,FIG.15illustrates another structural schematic of the second sub-region in the substrate module inFIG.4. Optionally, the first electrode portion121may be connected to the third electrode portion122, and the third electrode portion122may be electrically connected to the third sub-pin23. Therefore, signals may be simultaneously transmitted to the first electrode portion121and the third electrode portion122through the third sub-pin23. Obviously, in other embodiments of the present disclosure, the first electrode portion121may be connected to the third electrode portion122, and the first electrode portion121may be electrically connected to the third sub-pin23. Therefore, signals may be simultaneously transmitted to the first electrode portion121and the third electrode portion122through the third sub-pin23, which may not be described in detail herein.

FIG.16illustrates another structural schematic of the second sub-region in the substrate module inFIG.4. Referring toFIGS.4and16, in some optional embodiments, the second load50may further include a resistor R1. The second electrode layer14may further include a first wiring142. The first wiring142may be electrically connected to the second sub-pin22, and the first wiring142may form the resistor R1. The load capacity of the second load50may be flexibly adjusted through the settings of the resistor R1and the capacitor C1.

The second electrode portion141and the second sub-pin22may be electrically connected through the first wiring142, that is, the resistor R1and the first capacitor C1in the second load50may be connected in series.

It should be noted that the resistor R1in the second load50connected in series with the first capacitor C1may be exemplarily shown in one embodiment. In other embodiments of the present disclosure, the resistor R1in the second load50and the first capacitor C1may also use other connection manners according to actual production requirements, which may not be described in detail herein.

FIG.17illustrates another structural schematic of the second sub-region in the substrate module inFIG.4. Referring toFIGS.4and17, in some optional embodiments, the first trace142may be a serpentine wiring structure, which may be beneficial for reducing the length of the first trace142along the first direction X while the resistance of the resistor R1remains unchanged, thereby being beneficial for reducing the width of the second sub-region A2in the first direction X.

It should be noted that in one embodiment, it exemplarily shows that the first wiring142may be a serpentine wiring structure. In other embodiments of the present disclosure, the first wiring142may also use other bending settings, which may not be described in detail herein.

Referring toFIGS.4and17, in some optional embodiments, along the second direction Y, the first sub-pin21may not be disposed between at least two adjacent second sub-pins22, that is, only at least two second sub-pins22may be disposed in a partial region; the first electrode portions121electrically connected to the second sub-pins22in such region may be connected to each other to form an integral structure, which may facilitate the arrangement of the first electrode portions121, reduce the region that needs to be etched between the first electrode portions121and the fan-out lines40, thereby reducing the risk of connection between the first electrode portions121and the fan-out lines40.

Optionally, along the second direction Y, the second sub-pin22may not be disposed between any two adjacent first sub-pins21, that is, all first sub-pins21may be disposed together to form a first sub-pin group. Therefore, the second sub-pins22may be disposed on a side of the first sub-pin group along the second direction Y; and along the second direction Y, the first electrode portions121electrically connected to the second sub-pins22located on a same side of the first sub-pin group may be connected to each other to form an integral structure. In such way, the region that need to be etched between the first electrode portions121and the fan-out lines40may be further reduced, and the risk of connection between the first electrode portions121and the fan-out lines40may be further reduced.

FIG.18illustrates a planar schematic of another substrate module according to various embodiments of the present disclosure. In some optional embodiments, the substrate module may further include a chip on film60. The chip on film60may include a flexible circuit board70and a drive chip80fixed on the flexible circuit board70. The flexible circuit board70may be bent toward the side of the first substrate10away from the first pins20, which may be beneficial for reducing the area of the substrate module.

The flexible circuit board70may include a plurality of second pins71, the drive chip80may include a plurality of third pins81, and one third pin81may be electrically connected to one second pin71.

The plurality of second pins71in the flexible circuit board70may include at least one fourth sub-pin711and at least one fifth sub-pin712; one fourth sub-pin711may be electrically connected to one first sub-pin21; and one fifth sub-pin713may be electrically connected to the second sub-pin22.

For example, in the chip on film60, the third pin81in the drive chip80may be electrically connected to the second pin71in the flexible circuit board70; and the second pin71in the flexible circuit board70may be electrically connected to the first substrate10in the first pin20, so that the third pin81in the drive chip80may be electrically connected to the first pin20in the first substrate10. When the number of the third pins81in the drive chip80is greater than the number of the first sub-pins21in the first substrate10, correspondingly, the number of the second pins71in the flexible circuit board70may be greater than the number of the first sub-pins21in the first substrate10, and a part of the second pins71electrically connected to the third pins81may not be electrically connected to the first sub-pin21. That is, a part of the third pins81in the drive chip80may not be electrically connected to the first sub-pins21, the third pins81in the drive chip80that are not electrically connected to the first sub-pins21may have the function of outputting signals, and the third pins81in the drive chip80that are not electrically connected to the first sub-pins21may be electrically connected to the second sub-pins22. By disposing the second loads50in the second sub-region A2and electrically connecting the second sub-pins22to the second loads50, the third pins81in the drive chip80that are not electrically connected to the first sub-pins21may be electrically connected to the second loads50. In such way, the third pins81in the drive chip80that are not electrically connected to the first sub-pins21may be prevented from being in a floating state, thereby effectively improving the working performance of the drive chip80.

Meanwhile, the third pins81in the drive chip80that are not electrically connected to the first sub-pins21may be electrically connected to the second sub-pins22through the second pins71in the flexible circuit board70, that is, the third pins81of the drive chip80that are not electrically connected to the first sub-pins21may be electrically connected to the second loads50. Therefore, the number of the third pins81in the drive chip80may not need to be same as the number of the first sub-pins21in the first substrate10. In such way, it may avoid that one drive chip80can only be applied to the substrate with a specific number of first sub-pins21, which may effectively expand the scope of application of the drive chip80; and there is no need to provide different drive chips80for substrates with different numbers of first sub-pins21, which may effectively reduce the fabrication cost.

Optionally, in the chip on film60, the plurality of second pins71in the flexible circuit board70may further include at least one sixth sub-pin713; and the sixth sub-pin713may be configured for electrical connection with the third sub-pin23.

It should be noted that, in one embodiment, it exemplarily illustrates that in the COF process, the third pin81in the drive chip80may be electrically connected to the first pin in the first substrate10through the second pin71in the flexible circuit board70. In other embodiments of the present disclosure, the COG process may also be used, that is, the third pin81in the drive chip80may also be electrically connected to the first pin20in the first substrate directly, which may not be described in detail in the present disclosure.

In some optional embodiments, referring toFIG.19,FIG.19illustrates a planar schematic of a display apparatus according to various embodiments of the present disclosure. A display apparatus1000provided in one embodiment may include a substrate module100provided by above-mentioned embodiments of the present disclosure. In one embodiment, a mobile phone may be taken as an example to describe the display apparatus1000inFIG.19. It can be understood that the display apparatus1000provided in the embodiment of the present disclosure may also be another display apparatus1000having a display function including a computer, a television, a vehicle-mounted display apparatus and the like, which may not be described in detail in the present disclosure. The display apparatus1000provided by embodiments of the present disclosure has the beneficial effects of the substrate module100provided by embodiments of the present disclosure. Details refer to specific description of the substrate module100in above-mentioned embodiments, which may not be described in detail in the present disclosure.

FIG.20illustrates a structural schematic of another display apparatus according to various embodiments of the present disclosure. Referring toFIG.20, in some optional embodiments, the display apparatus may include a display region AA and a non-display region NA surrounding the display region AA. The display region AA may be configured for display; and the non-display region NA may not be configured for display and be configured to dispose structures such as circuits. The first sub-region A1may located in the display region AA, and the second sub-region A2may be located in the non-display region NA. Optionally, the first sub-region A1may be overlapped with the display region AA.

When the substrate module100is used in the display apparatus, the display region AA may include a plurality of sub-pixels P, and the first loads30may include the sub-pixels P. That is, the first sub-pins21in the substrate module100may be electrically connected to the sub-pixels P in the display region AA, and the second loads40may be disposed in the non-display region NA.

In the display apparatus, the first sub-pin21in the first substrate10may be electrically connected to the sub-pixel P. When the number of pins in the drive chip is greater than the number of the first sub-pins21in the first substrate10, the pins in the drive chip that are not electrically connected to the first sub-pins21may be extra pins. Extra pins in the drive chip may have the function of outputting signals and may be electrically connected to the second sub-pins22. By disposing the second loads50in the second sub-region A2and electrically connecting the second sub-pins22to the second loads50, extra pins in the drive chip may be electrically connected to the second loads50, which may avoid that some pins in the drive chip may be in a floating state and effectively improve the working performance of the drive chip.

Meanwhile, the pins in the drive chip that are not electrically connected to the first sub-pin21may be electrically connected to the second sub-pins22, that is, pins in the drive chip that are not electrically connected to the first sub-pin21may be electrically connected to the second loads50. Therefore, the number of pins in the drive chip may not need to be same as the number of the first sub-pins21in the first substrate10. In such way, it may avoid that one drive chip can only be applied to a display apparatus with a specific number of first sub-pins21, which may effectively expand the scope of application of the drive chip; and there is no need to provide different drive chips for display apparatuses with different numbers of the first sub-pins21, which may effectively reduce the fabrication cost.

It should be noted that, optionally, in the COG process, the pins in the drive chip may be directly electrically connected to the first pins20in the substrate module. Optionally, in the COF process, the pins in the drive chip may be electrically connected to the pins in the flexible circuit board, and the pins in the flexible circuit board may be electrically connected to the first pins20in the substrate module, thereby realizing that the pins in the drive chip may be electrically connected to the first pins in the substrate module.

FIG.21illustrates a cross-sectional view of the display apparatus along a J-J′ direction inFIG.20. Referring toFIGS.20-21and also referring toFIGS.2-3for the structure of the second load, in some optional embodiments, the display apparatus provided in one embodiment may be an organic light-emitting display apparatus. In the organic light-emitting display apparatus, a circuit layer15and a light-emitting layer16may be sequentially disposed on a side of the first base substrate11, the light-emitting layer16may include a plurality of light-emitting elements P1, the circuit layer15may include a plurality of metal layers151, the transistor TFT may be formed by the plurality of metal layers151in the circuit layer15, and the transistor TFT may be electrically connected to the light-emitting element P1.

A metal layer151may be reused as the first electrode layer12; and another metal layer151may be reused as the second electrode layer14. Different metal layers151that are insulated from each other may be reused as the first electrode layer12and the second electrode layer14. Exemplarily, the first metal layer1511may be reused as the first electrode layer12; the second metal layer1512may be reused as the second electrode layer14; and the second metal layer1512may be located on a side of the first metal layer1511away from the first base substrate11. Obviously, in other embodiments of the present disclosure, other metal layers151may be reused as the first electrode layer12and the second electrode layer14, which may not be described in detail in the present disclosure.

In the display apparatus, by reusing the plurality of metal layers151in the circuit layer15as the first electrode layer12and the second electrode layer14, the process of the display apparatus may be effectively simplified, and the production cost may be reduced, which may be beneficial for reducing the thickness of the display apparatus.

FIG.22illustrates another cross-sectional view of the display apparatus along a J-J′ direction inFIG.20. Referring toFIGS.20-22and referring toFIGS.2-3for the structure of the second load, in some optional embodiments, the display apparatus provided in one embodiment may be a liquid crystal display apparatus. The liquid crystal display apparatus may include the first substrate10and a color filter substrate CF which are disposed opposite to each other, and include a liquid crystal layer90located between the first substrate10and the color filter substrate CF. The first substrate10may be an array substrate. A common electrode layer17, a circuit layer15and a pixel electrode layer18may be disposed sequentially on a side of the first base substrate11. The pixel electrode layer18may include a plurality of pixel electrodes P2, and the circuit layer15may include a plurality of metal layers151. The transistor TFT may be formed through the plurality of metal layers151in the circuit layer15, and the transistor TFT may be electrically connected to the pixel electrode P2.

The common electrode layer17or the metal layer151may be reused as the first electrode layer12; and the metal layer151or the pixel electrode layer18may be reused as the second electrode layer14. Exemplarily, the common electrode layer17may be reused as the first electrode layer12; and the first metal layer1511may be reused as the second electrode layer14. Obviously, in other embodiments of the present disclosure, other film layers may be reused as the first electrode layer12and the second electrode layer14, which may not be described in detail in the present disclosure.

In the display apparatus, the common electrode layer17or the metal layer151may be reused as the first electrode layer12, and the metal layer151or the pixel electrode layer18may be reused as the second electrode layer14, which may effectively simplify the process of the display apparatus, reduce the production cost, and be beneficial for reducing the thickness of the display apparatus.

In some optional embodiments, the structure of the second load refers toFIGS.2-3. The material of the first electrode layer12may be at least one of molybdenum, aluminum, titanium-aluminum stack, molybdenum-aluminum stack, indium tin oxide, copper, and/or any suitable materials; and the material of the second electrode layer14may be at least one of molybdenum, aluminum, titanium-aluminum stack, molybdenum-aluminum stack, indium tin oxide, copper, and/or any suitable materials.

Molybdenum, aluminum, titanium-aluminum stack, molybdenum-aluminum stack, indium tin oxide, and copper may all be commonly used materials in display apparatuses. The first electrode layer12and the second electrode layer14may be made by at least one of molybdenum, aluminum, titanium-aluminum stack, molybdenum-aluminum stack, indium tin oxide, and copper, which may effectively reduce the fabrication cost of the first electrode layer12and the second electrode layer14.

It should be noted that in one embodiment, it exemplarily shows that the material of the first electrode layer12may be at least one of molybdenum, aluminum, titanium-aluminum stack, molybdenum-aluminum stack, indium tin oxide, copper, and/or any suitable materials; and the material of the second electrode layer14may be at least one of molybdenum, aluminum, titanium-aluminum stack, molybdenum-aluminum stack, indium tin oxide, copper and/or any suitable materials. In other embodiments of the present disclosure, the first electrode layer12and the second electrode layer14may also be made of other materials according to actual fabrication needs, which may not be described in detail herein.

In some optional embodiments, referring toFIG.23,FIG.23illustrates a structural schematic of a liquid crystal antenna according to various embodiments of the present disclosure. A liquid crystal antenna2000provided in one embodiment may include the substrate module200provided in above-mentioned embodiments of the present disclosure. The liquid crystal antenna2000provided by embodiments of the present disclosure may have the beneficial effects of the substrate module200provided by embodiments of the present disclosure. Details refer to specific description of the substrate module200in above-mentioned embodiments, which may not be described in detail in one embodiment.

FIG.24illustrates a planar schematic of the first substrate in the liquid crystal antenna inFIG.23. Referring toFIGS.23-24, in some optional embodiments, the liquid crystal antenna may include the first substrate10and the second substrate300which are disposed opposite to each other and include a liquid crystal layer400located between the first substrate10and the second substrate300.

The first substrate10may include a plurality of transmission electrodes31; and the transmission electrode31may be located on the side of the first base substrate11adjacent to the second substrate300. The transmission electrode31, located in the first sub-region A1, may be the first load30.

Exemplarily, in embodiments of the present disclosure, the transmission electrode31may be a planar transmission line. The planar transmission line may be a microstrip line. The shape of the transmission electrode31may not be limited in embodiments of the present disclosure, as long as the configuration of the transmission electrode31may realize microwave signal transmission. For example, the shape of the transmission electrode31may also be designed as a spiral shape as shown inFIG.24. Obviously, in other embodiments of the present disclosure, the transmission electrode31may also use other shapes, such as a serpentine line, a folded line, a straight arc, and/or the like, which may not be described in detail in the present disclosure.

In the liquid crystal antenna, the first sub-pin21in the first substrate10may be electrically connected to the transmission electrode31.

Optionally, the drive chip in the liquid crystal antenna may be a drive chip in a conventional display apparatus. At least a part of the pins on the drive chip in the conventional display apparatus may be configured for electrical connection with the sub-pixels in the conventional display apparatus. Since the number of transmission electrodes31in the liquid crystal antenna is much less than the number of sub-pixels in the conventional display apparatus, when the drive chip in the liquid crystal antenna uses the drive chip in the conventional display apparatus, some pins in the drive chip may not be electrically connected to the transmission electrode31, and these pins may be in a floating state.

When the number of pins in the drive chip is greater than the number of the first sub-pins21in the first substrate10, the pins in the drive chip that are not electrically connected to the first sub-pins21are extra pins. The extra pins in the drive chip may have the function of outputting signals. The extra pins in the drive chip may be electrically connected to the second sub-pins22. By disposing the second loads50in the second sub-region A2and electrically connecting the second sub-pins22to the second loads50, the extra pins in the drive chip may be electrically connected to the second loads50, thereby avoiding some pins in the drive chip being in a floating state and effectively improving the performance of the drive chip.

Meanwhile, the pins in the drive chip that are not electrically connected to the first sub-pins21may be electrically connected to the second sub-pins22, that is, the pins in the drive chip that are not electrically connected to the first sub-pins21may be electrically connected to the second loads50. Therefore, the number of pins in the drive chip may not need to be same as the number of the first sub-pins21in the first substrate10. In such way, it may avoid that one drive chip can only be applied to the liquid crystal antenna with a specific number of first sub-pins21, which may effectively expand the scope of application of the drive chip; and there is no need to set different drive chips for the liquid crystal antennas with different numbers of the first sub-pins21, which may effectively reduce the fabrication cost.

It should be noted that, optionally, in the COG process, the pins in the drive chip may be directly electrically connected to the first pins20in the substrate module. Optionally, in the COF process, the pins in the drive chip may be electrically connected to the pins in the flexible circuit board, and the pins in the flexible circuit board may be electrically connected to the first pins20in the substrate module, such that the pins in the drive chip may be electrically connected to the first pins in the substrate module.

Referring toFIGS.23-24and also referringFIGS.2-3for the structure of the second load, in some optional embodiments, a wiring layer210and a transmission electrode layer220may be sequentially disposed on the side of the first base substrate11adjacent to the second substrate300. The wiring layer210may include a plurality of first wirings51; the transmission electrode layer220may include a plurality of transmission electrodes31; and the transmission electrodes31and the first sub-pins21may be electrically connected through the first wirings51.

The wiring layer210may be reused as the first electrode layer12, and the transmission electrode layer220may be reused as the second electrode layer14. The wiring layer210may be reused as the first electrode layer12, and the transmission electrode layer220may be reused as the second electrode layer14, which may effectively simplify the process of the liquid crystal antenna, reduce the production cost, and be beneficial for reducing the thickness of the liquid crystal antenna.

In some optional embodiments, the structure of the second load refers toFIGS.2-3. The material of the first electrode layer12may be indium tin oxide or copper, and the material of the second electrode layer14may be indium tin oxide or copper.

Both indium tin oxide and copper are commonly used materials in liquid crystal antennas. The first electrode layer12and the second electrode layer14may be fabricated by indium tin oxide or copper, which may effectively reduce the fabrication cost of the first electrode layer12and the second electrode layer14.

It should be noted that in one embodiment, it exemplarily describes that the material of the first electrode layer12may be indium tin oxide or copper, and the material of the second electrode layer14may be indium tin oxide or copper. In other embodiments of the present disclosure, the first electrode layer12and the second electrode layer14may also be made of other materials according to actual fabrication needs, which may not be described in detail herein.

Referring toFIGS.23-24, in some optional embodiments, the second substrate300may include a second base substrate310, a ground electrode320, a radiator330and a feeder340. The ground electrode320may be located on the side of the second base substrate310adjacent to the first substrate10; and the radiator330and the feeder340may be located on the side of the second base substrate310away from the first substrate10.

The feeder340may be configured to receive microwave signals, and the radiator330may be configured to radiate phase-shifted microwave signals. During microwave signal transmission, under the action of the voltage difference between the transmission electrode31and the ground electrode320, the liquid crystal molecules in the liquid crystal layer400may be deflected to change the phase of the microwave signal, thereby realizing the phase shift function of the microwave signal. In embodiments of the present disclosure, the voltage difference between the transmission electrode31and the ground electrode320may be controlled by controlling the bias driving voltage on the transmission electrode31.

It should be noted thatFIG.23exemplarily illustrates that the transmission electrode31and the ground electrode320are respectively disposed on the first substrate10and the second substrate300. In an actual liquid crystal antenna, the transmission electrode31and the ground electrode320may also be configured according to other positional relationships. For example, the transmission electrode31and the ground electrode320may also be configured on a same substrate, which may not be described in the present disclosure.

FIG.25illustrates a planar schematic of a second substrate in the liquid crystal antenna inFIG.23. Referring toFIGS.23and25, the orthographic projection of a part of an opening321in the ground electrode320on the plane where the second base substrate310is located may be at least partially overlapped with the orthographic projection of the feeder340on the plane where the second base substrate310is located. Therefore, the microwave signal on the second base substrate310may be transmitted to the side of the second substrate300away from the feeder340through such part of the opening321. The orthographic projection of another part of the opening321in the ground electrode320on the plane where the second base substrate310is located may be at least partially overlapped with the orthographic projection of the radiator330on the plane where the second base substrate310is located. Through such arrangement, the phase-shifted microwave signal may be transmitted to the radiator330through such part of the opening321and radiated out through the radiator330.

Optionally, in embodiments of the present disclosure, an end of the feeder340may be connected to a radio frequency connector (not shown inFIGS.23and25). The RF connector may be used as the signal source to provide the microwave signal.

In embodiments of the present disclosure, the shape of the radiator330may be formed as a rectangle or a circle. The shape of the radiator330may be configured as a rectangle for illustration inFIG.25.

From above-mentioned embodiments, it may be seen that the substrate module, the display apparatus and the liquid crystal antenna provided by the present disclosure may achieve at least following beneficial effects.

In the substrate module provided by the present disclosure, the substrate module may include the first substrate; the first substrate may include the first sub-region and the second sub-region; the second sub-region may be on the side of the first sub-region along the first direction and include the binding region; the binding region may include the plurality of first pins arranged along the second direction; and the first pins may be configured for electrical connection with the pins in the drive chip. In the COG process, the pins in the drive chip may be directly electrically connected to the first pins in the substrate module. In the COF process, the pins in the drive chip may be electrically connected to the pins in the flexible circuit board, and the pins in the flexible circuit board may be electrically connected to the first pins in the substrate module, such that the pins in the drive chip may be electrically connected to the first pins in the substrate module. The plurality of first pins in the first substrate may include at least one second sub-pin. The second sub-region may include at least one second load, and the second sub-pin may be electrically connected to the second load. When the number of pins in the drive chip is greater than the number of the first sub-pins in the first substrate, the pins in the drive chip that are not electrically connected to the first sub-pins are extra pins. The extra pins in the drive chip may have the function of outputting signals. The extra pins in the drive chip may be electrically connected to the second sub-pins. By disposing the second loads in the second sub-region and electrically connecting the second sub-pins to the second loads, the extra pins in the drive chip may be electrically connected to the second loads, thereby avoiding some pins in the drive chip being in a floating state and effectively improving the performance of the drive chip. Meanwhile, the pins in the drive chip that are not electrically connected to the first sub-pins may be electrically connected to the second sub-pins, that is, the pins in the drive chip that are not electrically connected to the first sub-pins may be electrically connected to the second loads. Therefore, the number of pins in the drive chip may not need to be same as the number of the first sub-pins in the first substrate. It may avoid that one drive chip can only be applied to the first substrate with a specific number of first sub-pins, which may effectively expand the scope of application of the drive chip; and there is no need to set different drive chips for the first substrates with different numbers of the first sub-pins, which may effectively reduce the fabrication cost.

Although some embodiments of the present disclosure have been described in detail through examples, those skilled in the art should understand that above-mentioned examples are provided for illustration only and not for the purpose of limiting the scope of the disclosure. Those skilled in the art should understand that modifications may be made to above-mentioned embodiments without departing from the scope and spirit of the present disclosure. The scope of the present disclosure may be defined by appended claims.