Semiconductor device having signal line and reference potential planes separated by a vertical gap

A semiconductor device according to the one embodiment of the present invention comprises a signal line; and a reference potential plane which is separated from the signal line and opposed to the signal line, the reference potential plane being provided with a discontinuous region in a portion intersecting with the signal line, as a delay element to be added to the signal line.

CROSS REFERENCE TO RELATED APPLICATION

This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2004-356735, filed on Dec. 9, 2004, the entire contents of which are incorporated herein by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a semiconductor device supporting a signal line of a high speed input/output (I/O) such as GHz band and more particularly, to a disposition structure of a signal line formed on a wiring board constituting a semiconductor chip or package located in the vicinity of a reference potential plane such as a ground (GND) plane.

2. Related Background Art

In recent years, the number of specifications of high speed interfaces in which a high speed signal of some hundreds of MHz, the GHz band or 10 GHz passes through outside of a semiconductor chip such as a package, a board or the like-has increased. As the operation frequency becomes higher and rise time or fall time of the signal becomes shorter, it is necessary to design a pattern of a package which is conventionally handled as a lumped constant while taking, into consideration, impedance and transmission delay time as a transfer path.

Conventionally, the reference potential plane such as the ground (GND) plane disposed under such a high speed signal line is not usually provided with a large slit which causes impedance mismatch and blocks a feedback current path.

A large slit in view of electromagnetic interference (EMI) can not usually enter the GND plane provided directly below the transfer line on the board or package. Especially on the transfer line in which impedance is controlled, a reference GND plane is not provided with a notch. It is conventionally known that if the GND plane is provided with a slit, the speed of a propagating wave is reduced.

Japanese Patent Laid-Open Publication No. 2003-273620 described a portable electronic apparatus which comprises an antenna for sending and receiving radio wave, a circuit board which has the antenna and which is disposed in the longitudinal direction of the antenna, and a reactance component loading unit provided on the circuit board for securing a line length for an image current of one-quarter wavelength (λ/4) flowing through the ground of the circuit board in the longitudinal direction of the antenna, the reactance component loading unit comprises a slit. By providing the slit, a ground board length L4can be adjusted such that it becomes a λ/4 line length, and the ground board length L4is set such that the length L4corresponds to an ideal ground board length L2. With this, it is possible to prevent the frequency of the antenna from deviating and to prevent the voltage standing wave ratio (VSWR) characteristics from deteriorating.

On the other hand, when the opposed reference potential plane exists in the vicinity of the signal line, a semiconductor device capable of generating signal transfer delay without providing a delay element on the side of the signal line and capable of easily forming an equivalent delay element on a wiring board constituting the semiconductor chip or package is required.

SUMMARY OF THE INVENTION

According to an one embodiment of the present invention, there is provided a semiconductor device comprising a signal line; and a reference potential plane which is separated from the signal line and opposed to the signal line, the reference potential plane being provided with a discontinuous region in a portion intersecting with the signal line, as a delay element to be added to the signal line.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

In each of embodiments of the present invention, a gap (discontinuous region) having an appropriate size is formed in a reference potential plane located in the vicinity of a signal line, thereby forming a slit in the reference potential plane without providing a delay element on the side of the signal line to generate a signal transmission delay, and an equivalent delay element is easily formed.

Embodiments of the present invention will be explained with reference to illustrated concrete example.

First Embodiment

The first embodiment will be explained with reference toFIGS. 1 to 4and8.

FIGS. 1 and 2are perspective views showing disposition of a wiring pattern and a reference potential plane such as a ground (GND) plane or the like provided on a semiconductor chip or a wiring board in a semiconductor device of the first embodiment of the present invention.FIGS. 3A and 3Bare equivalent circuit diagrams which show generation of signal transfer delays of a gap or a slit formed in a reference potential plane.FIG. 4Ais a sectional view of a semiconductor device formed with a signal line and a reference potential plane used for explaining the first embodiment.FIG. 4Bis a partially perspective plan view of an interior of the semiconductor device formed with the signal line and the reference potential plane used for explaining the first embodiment.FIGS. 8A and 8Bare a perspective view of a wiring board and a diagram showing characteristics used for explaining the delay effect of a slit formed in a reference potential plane. A sectional view taken along the line A-B inFIG. 4Bcorresponds toFIG. 4A.

InFIG. 1, a semiconductor chip constituting a semiconductor device, a wiring board constituting the semiconductor device, or wiring pattern and reference potential plane such as GND plane (in this embodiment, this is explained using a ground (GND) plane) provided on a mounting board on which the semiconductor device is mounted are disposed. The GND plane comprises a first GND plane20and a second GND plane30in the same plane, and a gap11is provided between the first and second GND planes20and30. A signal line10is disposed above the GND planes20and30such as to cross at least the gap11in the vicinity of the GND planes20and30.

InFIG. 2, a semiconductor chip constituting the semiconductor device, the wiring board constituting the semiconductor device, or wiring pattern and GND plane70provided on the mounting board on which the semiconductor device is mounted are disposed. The GND plane70is formed with a slit6within the GND plane70. A signal line10is disposed above the GND plane70such as to cross at least the slit6in the vicinity of the GND plane70. The GND planes20and30are completely separated from each other with the gap11interposed therebetween (such as shown inFIG. 1), and a feedback current path is completely cut off. On the other hand, as shown inFIG. 2, the slit6formed in the GND plane70is not in the separated state unlike the GND planes20and30and is in a state where both ends are connected to each other.

The discontinuous region such as the gap or slit is formed on the GND plane located in the vicinity of the signal line. With this, a signal transmission delay can be generated on the side of the GND plane without providing a delay element on the side of the signal line, and an equivalent delay element can easily be formed.

If a case where the GND plane is separated by the gap and a case where both ends are connected as shown inFIG. 2are compared with each other, a value of the delay amount and variation in delay amount caused by the shape of the slit are added, and the delay amount when both ends are not connected is greater than that when both ends are connected, and variation in delay amount caused by variation in slit width (gap width) is great.

In this manner, the delay amount can be adjusted by the shape, and it is possible to form a delay element having a desired signal delay amount by a pattern of the GND plane of the package.

Next, with reference toFIGS. 4A and 4B, the signal line provided on the wiring board constituting the semiconductor device and a delay element formed by the GND plane will be explained.

The semiconductor device shown inFIGS. 4A and 4Bincludes a semiconductor chip1and a wiring board2having multi-wiring layers on which the semiconductor chip1is mounted. The semiconductor chip1formed with the semiconductor device is connected to the wiring board2with adhesive9as shown inFIG. 4A. Connection electrodes3and3awhich are wiring patterns exposed to the surface of the wiring board2are formed on the surface of the wiring board2. The semiconductor chip1and the connection electrodes3and3aare electrically connected to each other through a bonding wire4bonded to the connection electrode (not shown) on the surface of the semiconductor chip1. Wiring patterns including a signal line7and a GND plane5are formed in a multi-layered manner in the wiring board2. As shown inFIG. 4A, external connection terminals8and8asuch as soldering balls or the like are formed on the back surface of the wiring board2through a connection electrode (not shown).

External connection terminals8and8aare electrically connected to a semiconductor device formed in the semiconductor chip1through a wiring pattern in the wiring board2. For example, the GND terminal8ais connected to the semiconductor device of the semiconductor chip1through the connection electrode3aon the surface of the wiring board2and the bonding wire4aconnected to the connection electrode3avia a GND plane5formed in the wiring board2. The external connection terminal8is connected to the semiconductor device of the semiconductor chip1through the connection electrode3on the surface of the wiring board2and the bonding wire4connected to the connection electrode3via the signal line7constituting the wiring pattern in the wiring board2.

The GND plane5is formed into a toroidal shape over the entire region of the wiring board2except a region directly below the semiconductor chip1, and the slit6is formed in a portion of the GND plane5. The signal line7is closely opposed to the GND plane5such that at least a portion of the signal line7crosses the slit6. By forming the slit (discontinuous region) having an appropriate size in the GND plane located close to the signal line7, it is possible to generate a signal transmission delay on the side of the GND plane and to easily add an equivalent delay element to the signal line without providing the delay element itself on the side of the signal line. The semiconductor device of this embodiment is designed for transmitting short-wavelength signals, especially high speed signals within the range of the GHz band, the THz band or higher frequency bands.

FIGS. 3A and 3Bare equivalent circuits explaining the electric property of the structure shown inFIG. 1orFIG. 2. InFIG. 3Aa transmission line100represents the signal line10shown inFIG. 1orFIG. 2. InFIG. 3Ba LC circuit constituted by a coil600and a capacitor700represents the signal line10shown inFIG. 1orFIG. 2. InFIGS. 3A and 3Ba coil400represents the inductance of a reference potential plane (20,30,70) below the signal line10. Resistors500represent that the reference potential plane is isolated by a high resistance at the gap11or slit6. A coil200and capacitors300depicted inFIGS. 3A and 3Brepresent that the impedance of the signal line10inFIG. 1orFIG. 2varies due to the gap11or slit6. The delay amount of the equivalent delay circuit can easily be adjusted by the shape of the slit, such as the width of the slit, and it is possible to form a delay element having a desired signal delay amount by a pattern of the GND plane.

FIGS. 8A and 8Bare a perspective view of a wiring board and a diagram showing characteristics used for explaining the delay effect of a slit6formed in the GND plane5in the board2having the signal line10disposed in the vicinity of the GND plane5formed with the reference potential plane (GND plane). The wiring board shown inFIG. 8Ais the GND plane5formed at its one surface with the slit6, and formed at its other surface with the signal line10. The wiring board has a vertical length of 60 mm, a lateral length of 80 mm and a thickness of 0.4 mm. As shown inFIG. 8B, the voltage (V) of a signal on the signal line is shown as a function to time (ns). If a signal rises in the signal line, when the rise time is 80 ps, a delay of 200 ps is generated. A dotted curved line b shows a waveform of a signal flowing through the signal line when there is no slit. A solid curved line a shows a waveform of a signal flowing through the signal line when there is a slit as shown inFIG. 8A. The delay effect of the slit formed in the GND plane is sufficient for using like this as a delay element.

Second Embodiment

The second embodiment will be explained with reference toFIGS. 5A and 5B.

FIG. 5Ais a sectional view of a semiconductor device formed with a signal line and a reference potential plane for explaining the second embodiment of the present invention, andFIG. 5Bis a partial perspective plan view of the semiconductor device formed with the signal line and the reference potential plane for explaining the second embodiment of the present invention. A sectional view taken along the A-B line inFIG. 5Bcorresponds toFIG. 5A. Unlike the first embodiment, the second embodiment is characterized in that the GND plane is partially disposed on the wiring board, and the semiconductor chip is connected to the wiring board in a flip chip manner.

The semiconductor device shown inFIGS. 5A and 5Bincludes a semiconductor chip21and a wiring board22having multi-layered wiring layers on which the semiconductor chip21is mounted. The semiconductor chip21is formed with the semiconductor device. The semiconductor chip21is connected to the wiring board22through soldering balls (connecting terminals)24in a flip chip manner as shown inFIG. 5A. Connection electrodes23and23awhich wiring patterns are formed on the surface of the wiring board22such as to be exposed from the surface. The semiconductor chip21and the connection electrodes23and23aare electrically connected to each other through the connection electrodes (not shown) on the surface of the semiconductor chip21and the soldering balls24connected to the connection electrodes23and23aon the wiring board22. Wiring patterns including the signal line27and the GND plane25are formed in the wiring board22in the multi-layered manner.

As shown inFIG. 5A, the external connection terminals28and28asuch as soldering balls are formed on the back surface of the wiring board22via connection electrodes (not shown). The external connection terminals28and28aare electrically connected to the semiconductor device formed on the semiconductor chip21through the wiring pattern in the wiring board22. For example, the GND terminal28ais connected to the semiconductor device of the semiconductor chip21through the connection electrode23aon the surface of the wiring board22and the soldering balls24aconnected to the connection electrode23avia the GND plane25formed in the wiring board22. The external connection terminal28is connected to the semiconductor device of the semiconductor chip21through the connection electrode23on the surface of the wiring board22and the soldering balls24connected to the connection electrode23via the signal line27which constitutes the wiring pattern in the wiring board22.

Here, the GND plane25is formed on a portion of the wiring board22separated from a region directly below the semiconductor chip21. The GND plane25is formed at its portion with the slit26. The signal line27is closely opposed to the GND plane25such that at least a portion of the signal line27crosses the slit26. By forming the slit (discontinuous region) having appropriate size in the GND plane located close to the signal line27, it is possible to generate a signal transmission delay on the side of the GND plane and to easily add an equivalent delay element to the signal line without providing the delay element itself on the side of the signal line as explained with reference toFIGS. 8A and 8B. The semiconductor device of this embodiment is designed for transmitting short-wavelength signals, especially high speed signals within the range of the GHz band, the THz band or higher frequency bands.

FIG. 3Bshows the equivalent circuit of the delay element formed by the slit26. Its delay amount can easily be adjusted by the shape of the slit such as the width of the slit, and it is possible to form a delay element having a desired signal delay amount by a pattern of the GND plane.

Third Embodiment

The third embodiment will be explained with reference toFIGS. 6 and 7.

FIG. 6is a perspective view showing disposition of a wiring pattern and a reference potential plane such as a GND plane or the like provided on a semiconductor chip or a wiring board in a semiconductor device of the third embodiment of the present invention.FIG. 7is a sectional view of a semiconductor chip having a multi-layer wiring layer formed with a reference potential plane of the third embodiment of the present invention.

Unlike the first and second embodiments, the third embodiment is characterized in that two GND planes are formed in different layers of wiring layers so that an interlayer space between the layers functions as a gap forming the discontinuous region, and wiring layers formed on the semiconductor chip are formed with a GND plane having a discontinuous region and a signal line for a high speed signal and the like.

InFIG. 6, a wiring pattern including a signal line and a reference potential plane such as the GND plane provided on a semiconductor chip constituting a semiconductor device, a wiring board constituting a semiconductor device or a mounting board on which a semiconductor device is mounted are disposed. The GND plane comprises first and second GND planes50and60formed on different layers which are upper and lower layers. A gap12exists in the interlayer space between the first and second GND planes50and60. A signal line40is disposed above the GND planes50and60in the vicinity of thereof. The signal line40extends between the layers. The signal line40comprises an upper signal line40b, a lower signal line40cand a vertical signal line40aformed in a via connecting the signal lines40band40cwith each other. The vertical signal line40ais formed in the vicinity of the gap12formed in the interlayer space between the first and second GND planes50and60.

By forming the discontinuous region such as the gap on the GND plane located in the vicinity of the signal line, it is possible to generate a signal transmission delay on the side of the GND plane even if the delay element is not provided on the side of the signal line, and to easily add an equivalent delay element to the signal line. Since the delay amount can be varied by varying the shape such as a gap width, it is possible to form a delay element having a desired signal delay amount on the signal line.

Next, a case in which a delay element formed of the signal line and the GND plane of the third embodiment is formed on a semiconductor chip will be explained with reference toFIG. 7. A structure having the delay element (seeFIG. 6) may be incorporated in the wiring pattern of the wiring board constituting the semiconductor device.

A semiconductor substrate31constituting the semiconductor chip is formed with a transistor constituting an integrated circuit. On the surface of the semiconductor substrate31, a wiring pattern36which is electrically connected to the integrated circuit is formed in an insulation film35. The transistor is a MOS transistor for example, and includes a source/drain region32, a gate insulating film33formed on the source/drain region32and a gate electrode34formed on the gate insulating film33. The semiconductor substrate31is provided at its surface with an insulating film35such as a silicon oxide film, and a wiring pattern36made of multi-layered aluminum and the like is formed in the insulating film35. Further, the GND plane made of aluminum and the like is formed in the insulating film35.

As the GND planes, a first GND plane37is formed as a lower layer, a second GND plane38is formed as an upper layer, and an interlayer gap39is formed therebetween. The wiring pattern36is formed with a signal line above and along the GND plane. The signal line comprises a lower signal line36c, an upper signal line36band a vertical signal line36adisposed therebetween and formed in the via of the insulation film35. The first GND plane37is opposed to the lower signal line36cclosely, the second GND plane38is opposed to the upper signal line36bclosely, and the interlayer gap39between the layers of the GND planes is opposed to the signal line36aclosely.

In this manner, the discontinuous region is formed by the interlayer gap between the GND planes37and38located closer to the signal lines36a,36band36c. With this, it is possible to generate a signal transmission delay on the side of the GND plane even if the delay element is not provided on the side of the signal line, and to easily add an equivalent delay element to the signal line (seeFIG. 8B). Since the delay amount can be varied by varying the shape such as a gap width, it is possible to form a delay element having a desired signal delay amount on the signal line. The semiconductor device of this embodiment is designed for transmitting short-wavelength signals, especially high speed signals within the range of the GHz band, the THz band or higher frequency bands.

In the above embodiment, the signal line for a high speed signal and the like of the wiring pattern provided on the semiconductor chip or wiring board constituting the semiconductor device, and the GND plane opposed to the signal line closely are explained, but an equivalent delay element is formed also between the signal line for the high speed signal and the like of the wiring pattern provided on the board on which the semiconductor device is mounted and the GND plane opposed to the signal line closely, and the present invention is also applied to the latter case also of course.

As explained above, according to the embodiments of the present invention, by forming the gap (discontinuous region) having an appropriate size on the reference potential plane located in the vicinity of the wiring pattern formed on the semiconductor chip or package board constituting the semiconductor device, it is possible to easily add an equivalent delay element having desired characteristics by adding the shape on the side of the reference potential plane rather than on the side of the signal line of the wiring pattern.