Memory device including charge pump circuit

The non-volatile memory device includes a memory cell array including a plurality of memory cells and a voltage generator configured to supply a voltage to the memory cell array. The voltage generator includes a charge pump circuit, a switching circuit, and a stage controller. The charge pump circuit includes a plurality of pump units and is configured to output a pump voltage and a pump current in accordance with a number of pump units that have received an input voltage among the plurality of pump units. The switching circuit is configured to output the pump voltage. The stage controller is configured to receive an input signal corresponding to the pump current and perform a stage control operation of generating a stage control signal for controlling the number of pump units to be driven.

BACKGROUND

Some example embodiments of the inventive concepts relate to semiconductor devices, and more particularly, to memory devices including a charge pump circuit.

Recently, demands for highly integrated and large capacity non-volatile semiconductor memory devices are increasing. Flash memory mainly used in a portable electronic device is a representative example of such non-volatile semiconductor memory devices. In a program operation of the non-volatile memory device, a relatively high voltage is applied. In order to generate such a relatively high voltage, a voltage generator for raising an input voltage input to the non-volatile memory device to generate the relatively high voltage may be provided in the non-volatile memory device. The voltage generator may include a charge pump. The charge pump is a kind of a direct current (DC)-DC converter for generating a voltage higher than the input voltage or lower than a ground voltage.

SUMMARY

Some example embodiments of the inventive concepts provide non-volatile memory devices including a charge pump circuit, capable of mitigating or preventing a large amount of peak current from being generated and/or reducing power consumed by the charge pump circuit.

According to an example embodiment of the inventive concepts, a non-volatile memory device includes a memory cell array including a memory cell region including a first metal pad and a memory cell array including a plurality of memory cells, and a peripheral circuit region including a second metal pad and a voltage generator configured to supply a voltage to the memory cell array, and vertically connected to the memory cell region by the first metal pad and the second metal pad. The voltage generator may includes a charge pump circuit including n pump units and configured to output a pump voltage and a pump current in accordance with a number of pump units, among the n pump units, that have received an input voltage, n being a natural number equal to or greater than 2, a switching circuit configured to output the pump voltage, and a stage controller configured to receive an input signal corresponding to the pump current and perform a stage control operation, the stage control operation including generating a stage control signal, the stage control signal being a signal for controlling the number of pump units among the n pump units.

According to an example embodiment of the inventive concepts, a non-volatile memory device includes a memory cell region including a first metal pad, and a peripheral circuit region including a second metal pad and vertically connected to the memory cell region by the first metal pad and the second metal pad. The peripheral circuit region further includes a charge pump circuit including a plurality of pump units and configured to output a pump voltage and a pump current in accordance with a number of pump units that have received an input voltage among the plurality of pump units, a switching circuit configured to output the pump voltage and the pump current, and a stage controller configured to receive an input signal corresponding to the pump current from the switching circuit, and generate a stage control signal for controlling a stage of the charge pump circuit. The non-volatile memory device may be configured to increase the number of pump units as the stage of the charge pump circuit increases.

According to an example embodiment of the inventive concepts, a non-volatile memory device includes a memory cell region including a first metal pad, and a peripheral circuit region including a second metal pad and vertically connected to the memory cell region by the first metal pad and the second metal pad. The peripheral circuit region further includes a charge pump circuit including a plurality of pump units and configured to output a pump voltage and a pump current, and a stage controller configured to perform a stage control operation of controlling a number of pump units to be driven among the plurality of pump units. The stage controller may include a pump current copy circuit configured to receive an input signal corresponding to the pump current and generate a copy voltage corresponding to the pump current, a pump current detector configured to output a reference signal based on the copy voltage and a reference voltage, and a stage control signal generator configured to generate a stage control signal for controlling a stage of the charge pump circuit based on the reference signal.

DETAILED DESCRIPTION

Some example embodiments of the inventive concepts will be described in detail with reference to the accompanying drawings.

It will be understood that, although the terms first, second, third etc. may be used herein to describe various values, elements, components, regions, layers and/or sections, these values, elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one value, element, component, region, layer or section from another value, element component, region, layer or section. Thus, a first value, element, component, region, layer or section discussed below could be termed a second value, element, component, region, layer or section without departing from the teachings of example embodiments.

FIG. 1is a block diagram illustrating a memory device10including a charge pump circuit according to an example embodiment of the inventive concepts.

The memory device10may be, for example, a NAND flash memory device. However, example embodiments of the inventive concepts are not limited to a NAND flash memory device. For example, the memory device10may include a NOR flash memory device, a resistive random access memory (RRAM) device, a phase-change random access memory (PRAM) device, a magneto-resistive random access memory (MRAM) device, a ferroelectric random access memory (FRAM) device, a spin transfer torque random access memory (STT-RAM) device, or the like. Further, according to some example embodiments, the memory device10may be implemented to have a three-dimensional array structure. For example, the memory device10may include a vertical NAND flash memory device having a three-dimensional array structure. The inventive concepts may be applied to a charge trap flash (CTF) memory device in which a charge storage layer includes an insulating layer as well as a flash memory device in which a charge storage layer is formed of a conductive floating gate.

Referring toFIG. 1, the memory device10includes a voltage generator100, a row decoder200, a memory cell array300, a page buffer circuit400, and a control logic500. Although not shown inFIG. 1, the memory device10may further include a data input and output circuit or an input and output interface. Further, although not shown, the memory device10may further include various sub-circuits such as an error correction circuit for correcting an error of data read from the memory cell array300.

The voltage generator100may receive an external voltage EVC provided from an external device (for example, a memory controller or a host). The voltage generator100may generate various kinds of internal voltages IVC for performing program, read, and erase operations on the memory cell array300from the external voltage EVC based on a voltage control signal CTRL_vol. For example, the voltage generator100may generate a word line voltage, a program voltage, a read voltage, a pass voltage, an erase verification voltage, or a program verification voltage. In addition, the voltage generator100may further generate a string selection line voltage and a ground selection line voltage based on the voltage control signal CTRL_vol. Further, the voltage generator100may further generate a bit line voltage based on the voltage control signal CTRL_vol.

The voltage generator100may include a charge pump circuit110and a stage controller130. The charge pump circuit110may receive the external voltage EVC provided from the external device and may generate a pump voltage from the external voltage EVC. The charge pump circuit110may include first to nth pump units each receiving the external voltage EVC. According to a stage of the charge pump circuit110, the number of pump units that receive the external voltage EVC among the first to nth pump units may vary. For example, in a first stage, one pump unit may receive the external voltage EVC and, at a second stage, two pump units may receive the external voltage EVC. In other words, the term “stage” or “stage of the charge pump circuit” may refer to the number of pump unit to be driven among the first to nth pump units.

The stage controller130may control a stage of the charge pump circuit110based on a magnitude of a pump current generated by the charge pump circuit110. InFIG. 1, it is illustrated that the stage controller130is included in the voltage generator100. However, the memory devices10according to the inventive concepts are not limited thereto. For example, the stage controller130may be included in the control logic500.

The voltage generator100of the memory device10according to some example embodiments of the inventive concepts may include the charge pump circuit110and the stage controller130. Therefore, it is possible to prevent a large amount of peak current from being generated during an operation by controlling the stage of the charge pump circuit110. Further, the voltage generator100of the memory device10may control the stage of the charge pump circuit110by sensing the pump current output from the charge pump circuit110. Thus, power consumption may be reduced when the operation is performed and/or an operation speed may be increased.

The row decoder200may select one of memory blocks BLK1to BLKz in response to a row address X-ADDR. The row decoder200may select one of word lines WL of a selected memory block and may select one of a plurality of string selection lines SSL. Further, the row decoder200receives the internal voltage IVC from the voltage generator100and may transmit a voltage for performing a memory operation to the word lines WL of the selected memory block. For example, during an erase operation, the row decoder200may transmit an erase voltage and a verification voltage to the selected word line and may transmit a pass voltage to non-selected word lines.

The memory cell array300may include a plurality of memory cells. For example, the plurality of memory cells included in the memory cell array300may be non-volatile memory cells that maintain stored data although supplied power is blocked. The memory cell array300may be connected to the string selection lines SSL, the word lines WL, ground selection lines GSL, and bit lines BL. For example, the memory cell array300may be connected to the row decoder200through the string selection lines SSL, the word lines WL, and the ground selection lines GSL, and further may be connected to the page buffer circuit400through the bit lines BL.

The memory cell array300includes the plurality of memory blocks BLK1to BLKz. Each of the plurality of memory blocks BLK1to BLKz may have a planar structure or a three-dimensional structure. The memory cell array300may include at least one of a single level cell block including single level cells SLC, a multilevel cell block including multilevel cells MLC, a triple level cell block including triple level cells TLC, and a quad level cell block including quad level cells QLC. For example, some memory blocks of the plurality of memory blocks BLK1to BLKz may be single level cell blocks and the other memory blocks may be multilevel cell blocks, triple level cell blocks, or quad level cell blocks.

The page buffer circuit400may transmit data DATA to and receive data DATA from the outside of the memory device10. The page buffer circuit400may select some of the bit lines BL in response to a column address Y-ADDR. The page buffer circuit400may operate as a write driver or a sense amplifier.

The control logic500may output various control signals, for example, the voltage control signal CTRL_vol, the row address X-ADDR, and the column address Y-ADDR for programming the data DATA in the memory cell array300, reading the data DATA from the memory cell array300, or erasing the data DATA stored in the memory cell array300based on a command CMD, an address ADDR, and a control signal CTRL. For example, the control logic500may receive the command CMD, the address ADDR, and the control signal CTRL from the memory controller outside the memory device10. Therefore, the control logic500may entirely control various operations in the memory device10.

FIG. 2is a block diagram illustrating a voltage generator of a memory device according to an example embodiment of the inventive concepts.

Referring toFIG. 2, the voltage generator100may include the charge pump circuit110, a switching circuit120, and the stage controller130. The charge pump circuit110may include a plurality of pump units111.

An input voltage V_in and an input current I_in may be provided from the outside to the charge pump circuit110. At this time, the input voltage V_in may be the external voltage EVC ofFIG. 1. The charge pump circuit110may output a pump voltage V_pump by raising the input voltage V_in. At this time, the charge pump circuit110may generate a pump current I_pump to output the pump voltage V_pump.

In the charge pump circuit110, in accordance with a received stage control signal SCS, an operating stage may change. The input voltage V_in may be applied to each of the plurality of pump units111. In accordance with the stage of the charge pump circuit110, the number of pump units, to which the input voltage V_in is applied, among the plurality of pump units111may vary. That is, in accordance with the stage of the charge pump circuit110, the number of pump units that operate among the plurality of pump units111may vary. For example, in the first stage, one pump unit operates, and at the second stage, two pump units may operate.

The switching circuit120may output the pump voltage V_pump output from the charge pump circuit110to the outside as an output voltage V_out. For example, the switching circuit120may receive the control signal (for example, CTRL_vol ofFIG. 1) from the control logic (for example,500ofFIG. 1), and may output the pump voltage V_pump as the output voltage V_out. At this time, the switching circuit120may generate an output current I_out to output the output voltage V_out.

When the memory device starts one operation among the program operation, the read operation, and the erase operation, in order to charge cells included in the memory cell array300, the output voltage V_out and the output current I_out may be output to the outside of the voltage generator100. For example, the charged memory cells may be expressed as a capacitor. When a charging operation of the charge pump circuit110is completed. Accordingly, the charge pump circuit110reaches a stabilization process, the output voltage V_out may reach a target voltage, and thus the output current I_out may be reduced and stabilized to a certain value.

The stage controller130may receive a signal SIP corresponding to the pump current I_pump from the switching circuit120. The stage controller130may obtain information on a magnitude of the pump current I_pump from the signal SIP corresponding to the pump current I_pump. The stage controller130may control the stage of the charge pump circuit110based on the information on the magnitude of the pump current I_pump. The stage controller130may output the stage control signal SCS to the charge pump circuit110based on the information on the magnitude of the pump current I_pump. A configuration of the stage controller130will be described hereinafter with reference toFIG. 5.

FIG. 3is a block diagram illustrating a charge pump circuit110according to an example embodiment of the inventive concepts.

Referring toFIGS. 2 and 3, the charge pump circuit110may include first to nth pump units111_1to111_nand first to nth voltage switches112_1to112_n. At this time, n is a natural number equal to or greater than 3. The first to nth pump units111_1to111_nmay be continuously connected. An internal configuration of each of the first to nth pump units111_1to111_nwill be described inFIG. 4.

The first to nth voltage switches112_1to112_nmay be selectively switched on/off, and accordingly, the input voltage V_in may be applied to the pump units respectively according to switching operations of the first to nth voltage switches112_1to112_n. Corresponding switching signals SCSC1to SCSCn may be respectively applied to the first to nth voltage switches112_1to112_n, and accordingly on/off operations of the first to nth voltage switches112_1to112_nmay be controlled. At this time, in accordance with the stage control signal SCS received from the stage controller130, the switching signals SCSC1to SCSCn respectively provided to the first to nth voltage switches112_1to112_nmay change.

In an example embodiment, the stage control signal SCS may be formed of n-bit codes SCSC1to SCSCn, and the bits may correspond to different voltage switches among the first to nth voltage switches112_1to112_n, respectively. For example, in the stage control signal SCS, the first code SCSC1may be provided to the first voltage switch112_1, the second code SCSC2is provided to the second voltage switch112_2, and the nth code SCSCn may be provided to the nth voltage switch112_n.

In an example embodiment, the stage control signal SCS is not formed of the n-bit codes, and instead may include a stage up signal for increasing the stage of the charge pump circuit110and a stage down signal for reducing or decreasing the stage of the charge pump circuit110. The charge pump circuit110may increase the number of pump units that operate when the stage up signal is received, and may reduce the number of pump units that operate when the stage down signal is received.

In the charge pump circuit110, in accordance with the received stage control signal SCS, an operating stage may change. In accordance with the stage of the charge pump circuit110, the number of pump units, to which the input voltage V_in is applied, among the first to nth pump units111_1to111_n, may vary. For example, in the first stage, the input voltage V_in is applied to the first pump unit111_1, and accordingly one pump unit may be driven. At the second stage, the input voltage V_in is applied to the first pump unit111_1and the second pump unit111_2, and accordingly two pump units may be driven. In the nth stage, the input voltage V_in is applied to the first to nth pump units111_1to111_n, and accordingly n pump units may be driven.

As the number of driving pump units increases, the charge pump circuit110may generate a relatively higher voltage as a target level while outputting a large amount of pump current I_pump. Therefore, as the number of driving pump units increases, the time spent on the pump voltage V_pump for reaching the target level (for example, set up time) may be reduced.

On the other hand, as the number of driving pump units increases, power consumed by the charge pump circuit110may increase. Further, as the number of driving pump units increases, a peak value of the input current I_in input to the charge pump circuit110may increase. Therefore, an operation of a component that provides power to the memory device may become unstable and the input voltage V_in provided to the memory device may become unstable.

In the memory device according to some example embodiments of the inventive concepts, the number of driving pump units among the first to nth pump units111_1to111_nincluded in the charge pump circuit110may be controlled in accordance with the stage control signal SCS, Thus, an operation speed may be increased by reducing or preventing power consumption and/or the setup time from excessively increasing.

FIG. 4is a block diagram illustrating a pump unit according to an example embodiment of the inventive concepts.FIG. 4illustrates the first pump unit111_1ofFIG. 3in a case where the input voltage V_in is provided to the first pump unit111_1. The pump unit illustrated inFIG. 4is merely an example. The pump unit may be implemented in one of various forms different from the one illustrated inFIG. 4. InFIG. 4, the first pump unit111_1ofFIG. 3is illustrated. The same configuration may be applied to the second to nth pump units111_2to111_nofFIG. 3.

Referring toFIG. 4, the first pump unit111_1may include a plurality of transistors Q0to Q4and a plurality of capacitors C0to C4. The plurality of transistors Q0to Q4may include n-type metal-oxide-semiconductor (NMOS) transistors. Drain terminals of the transistors Q0to Q4and gate terminals of the transistors Q0to Q4are connected to each other, respectively, and may operate as diodes. InFIG. 4, it is illustrated that the first pump unit111_1includes the five transistors Q0to Q4and the five capacitors C0to C4. However, pump units according to the inventive concepts are not limited thereto. The number of transistors and capacitors may vary.

A first clock signal CLK1or a second clock signal CLK2may be input through the first to fourth capacitors C1to C4excluding the output capacitor C0connected to an output end. In an example embodiment, the first clock signal CLK1and the second clock signal CLK2may be complementary.

In a first half period, the first clock signal CLK1has a low level and the second clock signal CLK2may have a high level and the first capacitor C1may be charged by the input voltage V_in. In the next half period, the first clock signal CLK1has a high level and the second clock signal CLK2may have a low level and a voltage of the first capacitor C1may be increased (or boosted) to two times the input voltage V_in by the first clock signal CLK1. Further, the first transistor Q1is turned off and the second transistor Q2is turned on, and accordingly a voltage of the second capacitor C2may increase twice the input voltage V_in.

In the next half period, when it is set again that the first clock signal CLK1has a low level and the second clock signal CLK2has a high level, a voltage of a second capacitor C2is increased to three times the input voltage V_in by the second clock signal CLK2and a third capacitor C3may be charged by the voltage of the second capacitor C2. Through such an operation, a first pump voltage V_pump1may be generated by amplifying the input voltage V_in. That is, when the number of transistors included in the first pump unit111_1is i, the first pump voltage V_pump1may be amplified up to i times the input voltage V_in.

FIG. 5is a block diagram illustrating a stage controller130according to an example embodiment of the inventive concepts.

Referring toFIGS. 2 and 5, the stage controller130may include a pump current copy circuit131, a pump current detector132, and a stage control signal generator133.

The pump current copy circuit131may receive the signal SIP corresponding to the pump current I_pump from the switching circuit120. The pump current copy circuit131may generate a copy voltage VR, a magnitude of which corresponds to the magnitude of the pump current I_pump, based on the signal SIP that corresponds to the pump current I_pump. In an example embodiment, the pump current copy circuit131may include a current mirror circuit and a current-voltage conversion circuit. For example, the current-voltage conversion circuit of the pump current copy circuit131may include a variable resistor R and a magnitude of the copy voltage VR may be proportional to a magnitude of the variable resistor R.

The pump current detector132may receive the copy voltage VR output from the pump current copy circuit131. The pump current detector132may generate a reference signal CS based on the copy voltage VR with a reference voltage Vref. For example, the pump current detector132may compare the copy voltage VR with a reference voltage Vref, and generate a reference signal CS based on a comparison result. In such cases, the reference signal CS may be referred to as a comparison signal. In an example embodiment, the pump current detector132may be implemented by an analog-digital converter (ADC). At this time, the reference voltage Vref may be provided from outside or may be generated in the pump current detector132.

For example, the pump current detector132may output the reference signal CS at a first level (for example, a high level) when the copy voltage VR is greater than the reference voltage Vref, and may output the reference signal CS at a second level (for example, a low level) when the copy voltage VR is less than or equal to the reference voltage Vref. Operations of the pump current detector132according to the inventive concepts are not limited thereto. The reference signal CS at the low level may be output when the copy voltage VR is greater than the reference voltage Vref, and the reference signal CS at the high level may be output when the copy voltage VR is less than or equal to the reference voltage Vref.

In an example embodiment, the pump current detector132may generate the reference signal CS based on the copy voltage VR and a plurality of reference voltages (for example, Vref1and Vref2). For example, the pump current detector132may compare the copy voltage VR with a plurality of reference voltages (for example, Vref1and Vref2) and generate the reference signal CS based on results of the comparison. In such cases, the reference signal CS may be referred to as a comparison signal.

The stage control signal generator133may receive the reference signal CS from the pump current detector132, and may output the stage control signal SCS. At this time, an operation of the stage control signal generator133outputting the stage control signal SCS may vary in accordance with an operation period. A control operation of the stage controller130may be divided into an operation in a first period P1and an operation in a second period P2based on a previously designated first reference time tp1(seeFIG. 6). In an example embodiment, the charge pump circuit110performs an operation of charging memory cells in the first period, and may finish the charging operation in the second period.

In an example embodiment, after an operation of the memory device starts, in the first period in which the memory cells are charged, the stage control signal generator133may output the stage control signal SCS that increases a stage when the reference signal CS is transitioned from the first level (for example, the high level) to the second level (for example, the low level). On the other hand, in the second period after the first period (for example, after tp1ofFIG. 6), the stage control signal generator133may output the stage control signal SCS that reduces the stage when the reference signal CS is transitioned from the second level to the first level.

In an example embodiment, the stage control signal generator133may receive information on the first reference time tp1that is a point in time at which the second period starts from the outside. For example, data corresponding to the first reference time tp1may be stored in the stage control signal generator133, and based on the previously stored data on the first reference time tp1, the operation of the first period and the operation of the second period may be dividedly performed. In an example embodiment, the stage control signal generator133may detect the first reference time tp1that is a point in time at which the second period starts. For example, the stage control signal generator133may obtain the first reference time tp1by detecting a point in time at which the charge pump circuit (e.g., charge pump circuit110ofFIG. 3) reaches a maximum stage (e.g., an nth stage). Operations of the stage control signal generator133according to the inventive concepts may not be limited thereto.

According to the foregoing example embodiment, the memory device may change the stage of the charge pump circuit based on the magnitude of the pump current I_pump output from the charge pump circuit. Therefore, the memory device may increase the pump current I_pump by sensing the case in which the magnitude of the pump current I_pump is not large enough and increasing the stage. Further, the memory device may control the stage (e.g., the maximum number of stages) after checking the magnitude of the pump current I_pump so as not to operate at a undesirably high stage from a point in time at which an operation of the charge pump circuit generating the pump voltage V_pump starts. Thus, power consumption may be reduced. The memory device may reduce power consumption by reducing the stage (e.g., the maximum number of stages) of the charge pump circuit in the second period.

FIG. 6is a view illustrating an operation of a stage controller according to an example embodiment of the inventive concepts.FIG. 6is a view illustrating a change in stage in accordance with the magnitude of the pump current and includes a graph illustrating a change in pump current over time. The charge pump circuit according to a comparative example operates at a (K+2)th stage without a change in stage. The operation of the stage controller illustrated inFIG. 6is merely an example, and operations of the stage controller according to the inventive concepts are not limited thereto.

Referring toFIGS. 2, 5, and 6, when the charge pump circuit110according to an example embodiment of the inventive concepts starts to operate, the charge pump circuit110may operate at a previously determined K stage. At this time, K may be an arbitrary number, which is a natural number equal to or greater than 1 as.

The stage controller130may control the stage of the charge pump circuit110. An operation of controlling the stage controller130may be divided into an operation in the first period P1and an operation in the second period P2based on the first reference time tp1. The charge pump circuit110may perform an operation of charging memory cells in the first period P1, and may finish the charging operation in the second period P2.

Data corresponding to the first reference time tp1may be previously stored in the stage controller130. In some example embodiments, the stage controller130may detect the first reference time tp1. The stage controller130may output the stage control signal SCS based on the first reference time tp1. In an example embodiment, the stage control signal SCS may include a stage up signal SCS_UP and a stage down signal SCS_DOWN, and the stage controller130may output the stage up signal SCS_UP in the first period P1, and may output the stage down signal SCS_DOWN in the second period P2.

When the charge pump circuit110starts to operate, the magnitude of the pump current I_pump may increase to a magnitude of a peak current I_peak. In the charge pump circuit110according to an example embodiment, K pump units may operate, and in a charge pump circuit according to the comparative example, (K+2) pump units may operate. Thus, the magnitude of the peak current I_peak of the charge pump circuit110according to the example embodiment may be less than a magnitude of a peak current Ic_peak of the charge pump circuit according to the comparative example. Therefore, according to the example embodiment, it is possible to prevent a device outside the memory device from being damaged due to the undesirably high peak current generated in the memory device according to the comparative example, thereby stably providing the input voltage to the memory device.

The magnitude of the pump current I_pump is gradually reduced after the magnitude of the pump current I_pump reaches the magnitude of the peak current I_peak, and may reach a magnitude of a reference current at a first time t1. At the first time t1, the pump current copy circuit131may generate the copy voltage VR corresponding to the magnitude of the pump current I_pump based on the signal SIP that corresponds to the pump current I_pump. At this time, the magnitude of the copy voltage VR may be equal to a magnitude of the reference voltage Vref. Because the copy voltage VR is gradually reduced and reaches the reference voltage Vref, the pump current detector132may output the reference signal CS transitioning from the high level to the low level. The stage control signal generator133may receive the reference signal CS transitioning from the high level to the low level, and may output the stage up signal SCS_UP for increasing the stage. The charge pump circuit110may receive the stage up signal SCS_UP, and may operate at a (K+1)th stage. As the stage of the charge pump circuit110increases, the magnitude of the pump current I_pump may increase again to a certain magnitude.

The magnitude of the pump current I_pump may be reduced again, and reach the magnitude of the reference current at a second time t2. The pump current copy circuit131may generate the copy voltage VR corresponding to the magnitude of the pump current I_pump based on the signal SIP that corresponds to the pump current I_pump. At the second time t2, the magnitude of the copy voltage VR may be equal to the magnitude of the reference voltage Vref. Because the copy voltage VR is gradually reduced and reaches the reference voltage Vref, the pump current detector132may output the reference signal CS transitioning from the high level to the low level. The stage control signal generator133may receive the reference signal CS, and may output the stage up signal SCS_UP for increasing the stage. The charge pump circuit110may receive the stage up signal SCS_UP, and may operate at the (K+2)th stage. As the stage of the charge pump circuit110increases, the magnitude of the pump current I_pump may increase again to a certain magnitude. Because the charge pump circuit110performs the charging operation in the first period P1, the stage controller130may control a magnitude of the pump current I_pump to be equal to or larger than a magnitude of the reference current, and may reduce a setup time spent on the pump voltage V_pump reaching a target voltage.

At a third time t3in the second period P2, the magnitude of the pump current I_pump is reduced again, and may reach the magnitude of the reference current. The pump current copy circuit131may generate the copy voltage VR, a magnitude of which corresponds to the magnitude of the pump current I_pump based on the signal SIP that corresponds to the pump current I_pump. At the third time t3, the magnitude of the copy voltage VR may be equal to the magnitude of the reference voltage Vref. Because the copy voltage VR is gradually reduced and reaches the reference voltage Vref, the pump current detector132may output the reference signal CS transitioning from the low level to the high level. The stage control signal generator133may receive the reference signal CS, and may output the stage down signal SCS_DOWN for reducing the stage. The charge pump circuit110may receive the stage down signal SCS_DOWN, and may operate at the (K+1)th stage. Because the charging operation of the charge pump circuit110is finished in the second period, the number of driving pump units engaging the charging operation may be reduced, thereby reducing power consumption.

FIG. 7is a circuit diagram illustrating a switching circuit, a pump current copy circuit, and a pump current detector that are included in a voltage generator according to an example embodiment of the inventive concepts. The circuit diagram ofFIG. 7is an example configuration corresponding to the operation of the stage controller inFIG. 6. Therefore, voltage generators according to the inventive concepts are not limited thereto, and various circuit configurations are available.

Referring toFIGS. 5 and 7, the switching circuit120may include a plurality of transistors. For example, the switching circuit120may include M transistors. At this time, M may be a natural number equal to or greater than 2.

The pump current copy circuit131may include a current mirror circuit131_1and a current-voltage conversion circuit131_2. The current mirror circuit131_1may receive the signal SIP that corresponds to the pump current I_pump, decrease the pump current I_pump by M times, and copy the pump current I_pump decreased by M times. The current-voltage conversion circuit131_2may convert the copied current I/M·I_pump into the copy voltage VR.

The current mirror circuit131_1may be connected to both ends of the switching circuit120, and may receive a voltage between the both ends of the switching circuit120as the signal SIP corresponding to the pump current I_pump. In an example embodiment, the current mirror circuit131_1may include two transistors and one operation amplifier. A configuration of the current mirror circuit is not limited thereto. The current mirror circuit131_1may have one of various circuit configurations in which the pump current I_pump is decreased by M times, and the current I/M·I_pump may be output.

In an example embodiment, the current-voltage conversion circuit131_2may be implemented by the variable resistor R connected to a ground power source. A magnitude of the variable resistor R may vary in accordance with control of the control logic (e.g., control logic500ofFIG. 1). For example, the magnitude of the variable resistor R may be controlled in order to compensate for an offset of the current mirror circuit131_1. In some example embodiments, for example, as illustrated inFIG. 10, the magnitude of the variable resistor R may be controlled in order to detect a defective memory cell included in the memory cell array (e.g., memory cell array300ofFIG. 1).

In an example embodiment, the pump current detector132may be implemented by an ADC. For example, the pump current detector132may include two comparators COMP1and COMP2and an S-R latch.

The copy voltage VR and the first reference voltage Vref1may be input to the first comparator COMP1and the copy voltage VR and the second reference voltage Vref2may be input to the second comparator COMP2. At this time, one of the first reference voltage Vref1and the second reference voltage Vref2may be greater than the reference voltage Vref ofFIG. 5by the offset, and the other of the first reference voltage Vref1and the second reference voltage Vref2may be less than the reference voltage Vref ofFIG. 5by the offset. For example, the first reference voltage Vref1may be greater than the reference voltage Vref by the offset and the second reference voltage Vref2may be less than the reference voltage Vref by the offset.

The first comparator COMP1may output a high-level signal when the copy voltage VR is greater than the first reference voltage Vref1, and may output a low-level signal when the copy voltage VR is less than the first reference voltage Vref1. The second comparator COMP2may output a low-level signal when the copy voltage VR is greater than the second reference voltage Vref2, and may output a high-level signal when the copy voltage VR is less than the second reference voltage Vref2.

The S-R latch may receive the signals output from the first comparator COMP1and the second comparator COMP2, and may output the reference signal CS. For example, when the S-R latch receives the low-level signal from the first comparator COMP1and receives the high-level signal from the second comparator COMP2, that is, when the copy voltage VR is less than the second reference voltage Vref2, the S-R latch may output the low-level reference signal CS. When the S-R latch receives the high-level signal from the first comparator COMP1and receives the low-level signal from the second comparator COMP2, that is, when the copy voltage VR is greater than the first reference voltage Vref1, the S-R latch may output the high-level reference signal CS. When the S-R latch receives the low-level signal from the first comparator COMP1and receives the low-level signal from the second comparator COMP2, that is, when the copy voltage VR is less than the first reference voltage Vref1and is greater than the second reference voltage Vref2, the S-R latch may output the reference signal CS at the same level as a level of the previously output reference signal CS.

Therefore, the pump current detector132may output the low-level reference signal CS when the copy voltage VR is less than the second reference voltage Vref2, may output the high-level reference signal CS when the copy voltage VR is greater than the first reference voltage Vref1, and may output the reference signal CS at the same level as the level of the previously output reference signal CS when the copy voltage VR has a value between the first reference voltage Vref1and the second reference voltage Vref2. In an example embodiment, the stage control signal generator133may output the stage control signal SCS when the reference signal CS transitions from the high level to the low level.

The pump current detector132illustrated inFIG. 7includes the two comparators COMP1and COMP2, and accordingly a change by a certain offset from the reference voltage Vref may not be sensed. The pump current detector132according to an example embodiment may include one comparator. The copy voltage VR and the reference voltage Vref may be inputted to the comparator. Thus, when the copy voltage VR is greater than the reference voltage Vref, the reference signal CS may have the high level, and when the copy voltage VR is less than the reference voltage Vref, the reference signal CS may have the low level.

FIG. 8is a view illustrating an operation of a stage controller according to an example embodiment of the inventive concepts.

Referring toFIGS. 5 and 8, the pump current detector132may receive the copy voltage VR as an analog signal, and may generate the reference signal CS based on the copy voltage VR and the plurality of reference voltages Vref1and Vref2. InFIG. 8, the two reference voltages are illustrated. However, pump current detectors according to an example embodiment of the inventive concepts may compare the copy voltage VR with three or more reference voltages.

For example, the pump current detector132may receive the copy voltage VR, and may output the 2-bit reference signal CS. When the copy voltage VR is greater than the first reference voltage Vref1, the pump current detector132may output the reference signal CS of 11. When the copy voltage VR is less than the second reference voltage Vref2, the pump current detector132may output the reference signal CS of 01. When the copy voltage VR has a value between the first reference voltage Vref1and the second reference voltage Vref2, the pump current detector132may output the reference signal CS of 10.

In the first period before the first reference time tp1, the stage control signal generator133may generate the stage control signal SCS, and accordingly the charge pump circuit (e.g., charge pump circuit110ofFIG. 2) may operate at the first stage when the reference signal CS of 11 is received. In the first period, the stage control signal generator133may generate the stage control signal SCS, and accordingly the charge pump circuit110may operate at the second stage when the reference signal CS of 10 is received. Further, in the first period, the stage control signal generator133may generate the stage control signal SCS, and accordingly the charge pump circuit110may operate at a third stage when the reference signal CS of 01 is received. That is, the stage corresponding to the magnitude of the copy voltage VR in the first period may be previously determined.

The stage controller130according to an example embodiment of the inventive concepts may control the stage by one of various methods other than the configuration illustrated inFIGS. 7 and 8in accordance with the magnitude of the copy voltage VR corresponding to the pump current.

FIG. 9is a block diagram illustrating a voltage generator100aof a memory device according to an example embodiment of the inventive concepts. InFIG. 9, description of the same components as those ofFIG. 2will not be repeated.

Referring toFIG. 9, the voltage generator100amay include the charge pump circuit110, the switching circuit120, and a stage controller130a. The charge pump circuit110may include a plurality of pump units111(e.g.,111_1to111_n). The number of driving pump units may vary in accordance with the stage.

The stage controller130amay terminate a stage control operation in response to a stage controller control signal CSC received from the outside. In an example embodiment, when an operation (e.g., one of a program operation, a read operation, and an erase operation) for the memory cells is completed, the stage controller130amay receive the stage controller control signal CSC, the stage control operation on the charge pump circuit may be terminated, thereby reducing power consumption.

In an example embodiment, in response to the stage controller control signal CSC received from the outside, the stage controller130amay terminate the stage control operation, and may perform an error detection operation with regard to one of the memory cell array and the voltage generator. The stage control operation of the stage controller130amay be the same as the stage control operation of the stage controller130ofFIG. 2. In an example embodiment, when the operation is performed on the memory cells, the stage controller control signal CSC may be received, and the stage controller130amay perform the error detection operation. The stage controller control signal CSC may be included in the voltage control signal CTRL_vol ofFIG. 1. The stage controller130amay receive the signal SIP corresponding to the pump current I_pump from the switching circuit120. The stage controller130amay obtain information on the magnitude of the pump current I_pump from the signal SIP corresponding to the pump current I_pump.

The stage controller130amay determine that an error is generated when the magnitude of the pump current I_pump is greater than the magnitude of the reference current. For example, when a fail memory cell is included in the memory cells on which the one operation among the program operation, the read operation, and the erase operation is performed, the magnitude of the pump current I_pump may be greater than the magnitude of the reference current, and the stage controller130amay determine that the error is generated. Further, for example, when a loss current is generated by a defective transistor included in the charge pump circuit110or the switching circuit120, the magnitude of the pump current I_pump may be greater than the magnitude of the reference current, and the stage controller130amay determine that the error is generated.

When the error is detected, the stage controller130amay output an error detection signal EDS to the control logic (e.g., control logic500ofFIG. 1). In an example embodiment, the control logic500may receive the error detection signal EDS, may determine that the fail memory cell is included in the operating memory cells, and may process a memory block including the fail memory cell as a bad block. A configuration of the stage controller130awill be described inFIG. 10.

FIG. 10is a block diagram illustrating a stage controller according to an example embodiment of the inventive concepts.FIG. 11is a view illustrating an operation of a stage controller according to an example embodiment of the inventive concepts.FIG. 10is a view illustrating that the stage controller performs the error detection operation in a third period P3.FIG. 11is a graph illustrating a change in pump current over time when the program operation is performed on normal memory cells and is the same as the graph ofFIG. 6, which illustrates a change in pump current over time when the stage is controlled in accordance with the magnitude of the pump current. InFIG. 11, the case in which the memory device performs the program operation is described as an example. However, the same description may be applied when the read operation or the erase operation is performed.

Referring toFIGS. 9 to 11, the stage controller130amay include a pump current copy circuit131a, a pump current detector132a, and a stage control signal generator133a. When the program operation is performed on the memory cells, at a second reference time tp2, the stage controller130amay receive the stage controller control signal CSC. In response to the stage controller control signal CSC, the stage controller130amay perform the error detection operation in the third period P3after the second reference time tp2.

When the error is not detected, the magnitude of the pump current I_pump in the third period P3may be less than the magnitude of the pump current I_pump in another period, and may be stabilized. For example, when the fail memory cell is not included in the programmed memory cells, the magnitude of the pump current I_pump may be reduced, and may be stabilized. On the other hand, when the fail memory cell is included in the programmed memory cells, the leakage current may be generated, and accordingly the magnitude of the pump current I_pump may be greater than in the case in which the error is not detected. InFIG. 11, only the case in which the fail memory cell is included is illustrated. However, the inventive concepts are not limited thereto. For example, when a defective transistor is included in the switching circuit, the loss current is generated, and accordingly the magnitude of the pump current I_pump may be greater than in the case in which the error is not detected. The pump current copy circuit131amay receive the signal SIP corresponding to the pump current I_pump from the switching circuit120. The pump current copy circuit131amay generate a copy voltage VR_f, a magnitude of which corresponds to the magnitude of the pump current I_pump based on the signal SIP corresponding to the pump current I_pump.

In an example embodiment, the pump current copy circuit131amay include the current mirror circuit and the current-voltage conversion circuit, and the current-voltage conversion circuit may be implemented by a variable resistor R_f connected to the ground power source. After the stage control operation, when the error detection operation starts, a magnitude of the variable resistor R_f of the pump current copy circuit131amay increase. That is, in response to the stage controller control signal CSC, a magnitude of the variable resistor R_f included in the pump current copy circuit131amay increase.

The magnitude of the pump current I_pump when the stage controller130aperforms the error detection operation (e.g., in the third period P3) may be less than the magnitude of the pump current I_pump when the stage controller130aperforms the stage control operation (e.g., in the first period P1and the second period P2). Therefore, when the stage controller130aperforms the error detection operation, the magnitude of the variable resistor of the pump current copy circuit131amay increase, and accordingly the pump current detector132amay easily detect the copy voltage VR_f.

The pump current detector132amay receive the copy voltage VR_f output from the pump current copy circuit131a. The pump current detector132amay generate a reference signal CS_f based on the copy voltage VR_f with the reference voltage Vref_f. For example, the pump current detector132amay compare the copy voltage VR_f with the reference voltage Vref_f, and may generate a reference signal CS_f based on a comparison result. Because the magnitude of the pump current I_pump when the stage controller130aperforms the error detection operation (e.g., in the third period P3) is less than the magnitude of the pump current I_pump when the stage controller130aperforms the stage control operation (e.g., in the first period P1and the second period P2), the reference voltage Vref_f when the error detection operation is performed may be lower than the reference voltage when the stage control operation is performed. Accordingly, the copy voltage VR_f may be easily detected. At this time, a value of the reference voltage Vref_f may be a voltage value corresponding to a maximum value of the magnitude of the pump current I_pump after the normal memory cells are programmed. The reference voltage Vref_f may be provided from the outside or may be generated in the pump current detector132a.

For example, the pump current detector132amay output the high-level reference signal CS_f when the copy voltage VR_f is higher than the reference voltage Vref_f, and may output the low-level reference signal CS_f when the copy voltage VR_f is equal to or lower than the reference voltage Vref_f. Operations of the pump current detector132aaccording to the inventive concepts are not limited thereto. When the copy voltage VR_f is higher than the reference voltage Vref_f, the low-level reference signal CS_f may be output and, when the copy voltage VR_f is equal to or lower than the reference voltage Vref_f, the high-level reference signal CS_f may be output.

The stage control signal generator133amay receive the reference signal CS_f from the pump current detector132a, and may output the error detection signal EDS. For example, when the copy voltage VR_f is higher than the reference voltage Vref_f, the stage control signal generator133amay receive the high-level reference signal CS_f, and may output the error detection signal EDS to the control logic (e.g., control logic500ofFIG. 1).

InFIG. 10, as the stage controller130aperforms the error detection operation, the magnitude of the variable resistor R_f included in the pump current copy circuit131aincreases and a magnitude of the reference voltage Vref_f in the pump current detector132ais reduced. However, the inventive concepts are not limited thereto. In some example embodiments, as the stage controller130aperforms the error detection operation, the magnitude of the variable resistor R_f included in the pump current copy circuit131areduces and the magnitude of the reference voltage Vref_f in the pump current detector132amay be increased.

FIG. 12is a block diagram illustrating a voltage generator100bof a memory device according to an example embodiment of the inventive concepts. InFIG. 12, description of the same components as those ofFIG. 2will not be repeated.

Referring toFIG. 12, the voltage generator100bmay include the charge pump circuit110b, the switching circuit120, a stage controller130b, and a pump clock generator140b. The charge pump circuit110bmay include the plurality of pump units111. The inventive concepts are not limited toFIG. 12. The stage controller130band the pump clock generator140bmay be components of the memory device and the voltage generator100b.

The stage controller130bmay receive the signal SIP corresponding to the pump current I_pump from the switching circuit120. The stage controller130bmay obtain the information on the magnitude of the pump current I_pump from the signal SIP corresponding to the pump current I_pump.

The stage controller130bmay control the stage of the charge pump circuit110bbased on the information on the magnitude of the pump current I_pump. The stage controller130bmay output the stage control signal SCS to the charge pump circuit110bbased on the information on the magnitude of the pump current I_pump. Further, the stage controller130bmay control a frequency of a pump clock signal PCLK provided to the charge pump circuit110bbased on the information on the magnitude of the pump current I_pump. The stage controller130bmay output a clock control signal CCLK to the pump clock generator140bbased on the information on the magnitude of the pump current I_pump. In an example embodiment, a stage control signal generator (not shown) included in the stage controller130bmay output the clock control signal CCLK to the pump clock generator140bbased on the information on the magnitude of the pump current I_pump.

The pump clock generator140bmay generate the pump clock signal PCLK, and may provide the pump clock signal PCLK to the charge pump circuit110b. For example, the pump clock signal PCLK may include the first clock signal CLK1and the second clock signal CLK2ofFIG. 4.

In an example embodiment, the pump clock generator140bmay be an oscillator. The pump clock generator140bmay receive the clock control signal CCLK from the stage controller130b, and generate the frequency of the pump clock signal PCLK in accordance with the clock control signal CCLK. For example, the pump clock generator140bmay generate the pump clock signal PCLK having the frequency increased or reduced integer number times from a basic frequency in accordance with the clock control signal CCLK.

As the frequency of the pump clock signal PCLK increases, the charge pump circuit110bmay generate the high voltage at the target level while outputting the large amount of pump current I_pump. Therefore, as the number of driving pump units increases, the setup time spent on the pump voltage V_pump reaching the target level may be reduced. On the other hand, as the frequency of the pump clock signal PCLK increases, power consumption of the charge pump circuit110bmay increase.

According to the example embodiments, the memory device may control the stage of the charge pump circuit110band the pump clock signal PCLK provided to the charge pump circuit110bby sensing the pump current I_pump. Thus, it is possible to mitigate or prevent power consumption or the setup time from excessively increasing. Thus, an operation speed may increase.

FIG. 13is a block diagram illustrating an example, in which a memory device to which a charge pump circuit is adopted according to an example embodiment of the inventive concepts is applied to a solid state drive (SSD) system1000.

Referring toFIG. 13, the SSD system1000may include a host1100and an SSD1200. The SSD1200may transmit and receive a signal to and from the host1100through a signal connector SIG and may receive power through a power connector PWR. The SSD1200may include an SSD controller1210, an auxiliary power supply1220, and memory devices1230,1240, and1250. At this time, the SSD1200may be implemented by using the above-described example embodiments with reference toFIGS. 1 to 12. Each of the memory devices1230,1240, and1250may include a charge pump circuit1232and a stage controller for controlling a stage of the charge pump circuit1232. Therefore, the SSD system1000may reduce power consumption and/or may increase an operation speed in accordance with the magnitude of the pump current when the operation (e.g., one of the program operation, the read operation, and the erase operation) is performed.

FIG. 14illustrates a memory device900having a chip-to-chip structure, according to exemplary embodiments of the inventive concept.

Referring toFIG. 14, a memory device900may have a chip-to-chip (C2C) structure. The C2C structure may refer to a structure formed by manufacturing an upper chip including a cell region CELL on a first wafer, manufacturing a lower chip including a peripheral circuit region PERI on a second wafer, different from the first wafer, and then connecting the upper chip and the lower chip in a bonding manner. For example, the bonding manner may include a method of electrically connecting a bonding metal formed on an uppermost metal layer of the upper chip and a bonding metal formed on an uppermost metal layer of the lower chip. For example, when the bonding metals may be formed of copper (Cu), the bonding manner may be a Cu-Cu bonding, and the bonding metals may also be formed of aluminum or tungsten. Each memory device of the above embodiments may be implemented as the memory device900.

Each of the peripheral circuit region PERI and the cell region CELL of the memory device900may include an external pad bonding area PA, a word line bonding area WLBA, and a bit line bonding area BLBA.

The peripheral circuit region PERI may include a first substrate710, an interlayer insulating layer715, a plurality of circuit elements720a,720b, and720cformed on the first substrate710, first metal layers730a,730b, and730crespectively connected to the plurality of circuit elements720a,720b, and720c, and second metal layers740a,740b, and740cformed on the first metal layers730a,730b, and730c. In an example embodiment, the first metal layers730a,730b, and730cmay be formed of tungsten having relatively high resistance, and the second metal layers740a,740b, and740cmay be formed of copper having relatively low resistance.

In an example embodiment illustrate inFIG. 14, although the first metal layers730a,730b, and730cand the second metal layers740a,740b, and740care shown and described, they are not limited thereto, and one or more metal layers may be further formed on the second metal layers740a,740b, and740c. At least a portion of the one or more metal layers formed on the second metal layers740a,740b, and740cmay be formed of aluminum or the like having a lower resistance than those of copper forming the second metal layers740a,740b, and740c.

The interlayer insulating layer715may be disposed on the first substrate710and cover the plurality of circuit elements720a,720b, and720c, the first metal layers730a,730b, and730c, and the second metal layers740a,740b, and740c. The interlayer insulating layer715may include an insulating material such as silicon oxide, silicon nitride, or the like.

Lower bonding metals771band772bmay be formed on the second metal layer740bin the word line bonding area WLBA. In the word line bonding area WLBA, the lower bonding metals771band772bin the peripheral circuit region PERI may be electrically connected to c in a bonding manner, and the lower bonding metals771band772band the upper bonding metals871band872bmay be formed of aluminum, copper, tungsten, or the like. Further, the upper bonding metals871band872bin the cell region CELL may be referred as first metal pads and the lower bonding metals771band772bin the peripheral circuit region PERI may be referred as second metal pads.

The cell region CELL may include at least one memory block. The cell region CELL may include a second substrate810and a common source line820. On the second substrate810, a plurality of word lines831to838(i.e.,830) may be stacked in a direction (a Z-axis direction), perpendicular to an upper surface of the second substrate810. At least one string select line and at least one ground select line may be arranged on and below the plurality of word lines830, respectively, and the plurality of word lines830may be disposed between the at least one string select line and the at least one ground select line.

In the bit line bonding area BLBA, a channel structure CH may extend in a direction, perpendicular to the upper surface of the second substrate810, and pass through the plurality of word lines830, the at least one string select line, and the at least one ground select line. The channel structure CH may include a data storage layer, a channel layer, a buried insulating layer, and the like, and the channel layer may be electrically connected to a first metal layer850cand a second metal layer860c. For example, the first metal layer850cmay be a bit line contact, and the second metal layer860cmay be a bit line. In an example embodiment, the bit line860cmay extend in a first direction (a Y-axis direction), parallel to the upper surface of the second substrate810.

In an example embodiment illustrated inFIG. 14, an area in which the channel structure CH, the bit line860c, and the like are disposed may be defined as the bit line bonding area BLBA. In the bit line bonding area BLBA, the bit line860cmay be electrically connected to the circuit elements720cproviding a page buffer893in the peripheral circuit region PERI. For example, the bit line860cmay be connected to upper bonding metals871cand872cin the cell region CELL, and the upper bonding metals871cand872cmay be connected to lower bonding metals771cand772cconnected to the circuit elements720cof the page buffer893.

In the word line bonding area WLBA, the plurality of word lines830may extend in a second direction (an X-axis direction), parallel to the upper surface of the second substrate810, and may be connected to a plurality of cell contact plugs841to847(i.e.,840). The plurality of word lines830and the plurality of cell contact plugs840may be connected to each other in pads provided by at least a portion of the plurality of word lines830extending in different lengths in the second direction. A first metal layer850band a second metal layer860bmay be connected to an upper portion of the plurality of cell contact plugs840connected to the plurality of word lines830, sequentially. The plurality of cell contact plugs840may be connected to the circuit region PERI by the upper bonding metals871band872bof the cell region CELL and the lower bonding metals771band772bof the peripheral circuit region PERI in the word line bonding area WLBA.

The plurality of cell contact plugs840may be electrically connected to the circuit elements720bproviding a row decoder894in the peripheral circuit region PERI. In an example embodiment, operating voltages of the circuit elements720bproviding the row decoder894may be different than operating voltages of the circuit elements720cproviding the page buffer893. For example, operating voltages of the circuit elements720cproviding the page buffer893may be greater than operating voltages of the circuit elements720bproviding the row decoder894. In an example embodiment, each voltage generator of the above embodiments may be disposed in the peripheral circuit region PERI.

A common source line contact plug880may be disposed in the external pad bonding area PA. The common source line contact plug880may be formed of a conductive material such as a metal, a metal compound, polysilicon, or the like, and may be electrically connected to the common source line820. A first metal layer850aand a second metal layer860amay be stacked on an upper portion of the common source line contact plug880, sequentially. For example, an area in which the common source line contact plug880, the first metal layer850a, and the second metal layer860aare disposed may be defined as the external pad bonding area PA.

Input-output pads705and805may be disposed in the external pad bonding area PA. Referring toFIG. 14, a lower insulating film701covering a lower surface of the first substrate710may be formed below the first substrate710, and a first input-output pad705may be formed on the lower insulating film701. The first input-output pad705may be connected to at least one of the plurality of circuit elements720a,720b, and720cdisposed in the peripheral circuit region PERI through a first input-output contact plug703, and may be separated from the first substrate710by the lower insulating film701. In addition, a side insulating film may be disposed between the first input-output contact plug703and the first substrate710to electrically separate the first input-output contact plug703and the first substrate710.

Referring toFIG. 14, an upper insulating film801covering the upper surface of the second substrate810may be formed on the second substrate810, and a second input-output pad805may be disposed on the upper insulating layer801. The second input-output pad805may be connected to at least one of the plurality of circuit elements720a,720b, and720cdisposed in the peripheral circuit region PERI through a second input-output contact plug803.

According to embodiments, the second substrate810and the common source line820may not be disposed in an area in which the second input-output contact plug803is disposed. Also, the second input-output pad805may not overlap the word lines830in the third direction (the Z-axis direction). Referring toFIG. 14, the second input-output contact plug803may be separated from the second substrate810in a direction, parallel to the upper surface of the second substrate810, and may pass through the interlayer insulating layer815of the cell region CELL to be connected to the second input-output pad805.

According to embodiments, the first input-output pad705and the second input-output pad805may be selectively formed. For example, the memory device900may include only the first input-output pad705disposed on the first substrate710or the second input-output pad805disposed on the second substrate810. Alternatively, the memory device900may include both the first input-output pad705and the second input-output pad805.

A metal pattern in an uppermost metal layer may be provided as a dummy pattern or the uppermost metal layer may be absent, in each of the external pad bonding area PA and the bit line bonding area BLBA, respectively included in the cell region CELL and the peripheral circuit region PERI.

In the external pad bonding area PA, the memory device900may include a lower metal pattern773a, corresponding to an upper metal pattern872aformed in an uppermost metal layer of the cell region CELL, and having the same shape as the upper metal pattern872aof the cell region CELL, in an uppermost metal layer of the peripheral circuit region PERI. In the peripheral circuit region PERI, the lower metal pattern773aformed in the uppermost metal layer of the peripheral circuit region PERI may not be connected to a contact. Similarly, in the external pad bonding area PA, an upper metal pattern, corresponding to the lower metal pattern formed in an uppermost metal layer of the peripheral circuit region PERI, and having the same shape as a lower metal pattern of the peripheral circuit region PERI, may be formed in an uppermost metal layer of the cell region CELL.

The lower bonding metals771band772bmay be formed on the second metal layer740bin the word line bonding area WLBA. In the word line bonding area WLBA, the lower bonding metals771band772bof the peripheral circuit region PERI may be electrically connected to the upper bonding metals871band872bof the cell region CELL by a Cu-Cu bonding.

Further, the bit line bonding area BLBA, an upper metal pattern892, corresponding to a lower metal pattern752formed in the uppermost metal layer of the peripheral circuit region PERI, and having the same shape as the lower metal pattern752of the peripheral circuit region PERI, may be formed in an uppermost metal layer of the cell region CELL. A contact may not be formed on the upper metal pattern892formed in the uppermost metal layer of the cell region CELL.

In an example embodiment, corresponding to a metal pattern formed in an uppermost metal layer in one of the cell region CELL and the peripheral circuit region PERI, a reinforcement metal pattern having the same shape as the metal pattern may be formed in an uppermost metal layer in another one of the cell region CELL and the peripheral circuit region PERI, and a contact may not be formed on the reinforcement metal pattern.