Clock network analysis using harmonic balance

A method and system to perform clock network analysis of a clock network of an integrated circuit that includes a grid obtains parameters for each transmission line of the clock network that carries a clock signal between a source of the clock signal and the grid. The method also includes obtaining models of nonlinear components of the clock network, and numerically solving a frequency domain nonlinear Harmonic Balance equation to obtain voltage values at an input and an output of each of the nonlinear components. The number of the voltage values obtained is proportional to the number of the nonlinear components. A physical implementation of the integrated circuit is obtained based on the clock network analysis.

BACKGROUND

The present invention relates to integrated circuit design, and more specifically, to clock network analysis using harmonic balance.

Integrated circuit design or chip design, as it is commonly known, involves multiple tasks that are performed at different phases to develop a logical design into a physical implementation of the chip. One of the tasks is analysis of the on-chip clock network which examines how and when a clock signal reaches each location or node in the chip. The analysis yields a clock signal waveform at each node. The clock signal waveforms provide values of interest in clock network analysis such as, for example, timing, overshoot, and undershoot. Two different clock network architectures are clock trees and clock grids. In a clock tree, the branches are unrelated such that leaves of different branches experience different clock delays. In a clock grid, metal wires connect the endpoints of each of the clock signal paths. As such, the clock skew, or the maximum difference among delays at the endpoints, is small. The coupling among the different clock paths in a clock grid makes clock network analysis different for the clock grid architecture than for the clock tree architecture.

SUMMARY

According to embodiments of the present invention, a computer-implemented method of performing clock network analysis of a clock network of an integrated circuit that includes a grid includes obtaining parameters for each transmission line of the clock network that carries a clock signal between a source of the clock signal and the grid, and obtaining models of nonlinear components of the clock network. A frequency domain nonlinear Harmonic Balance equation is numerically solved to obtain voltage values at an input and an output of each of the nonlinear components. The number of the voltage values obtained is proportional to the number of the nonlinear components. A physical implementation of the integrated circuit is obtained based on the clock network analysis.

According to other embodiments of the invention, a system to perform clock network analysis of a clock network of an integrated circuit that includes a grid includes a memory device to store parameters for each transmission line of the clock network that carries a clock signal between a source of the clock signal and the grid and models of nonlinear components of the clock network. The system also includes a processor to numerically solve a frequency domain nonlinear Harmonic Balance equation to obtain voltage values at an input and an output of each of the nonlinear components. A number of the voltage values obtained is limited by the number of the nonlinear components and the clock network analysis is used to obtain a physical implementation of the integrated circuit.

According to yet other embodiments of the invention, a computer program product for performing clock network analysis of a clock network of an integrated circuit that includes a grid includes a computer readable storage medium having program instructions embodied therewith. The program instructions are executable by a processor to perform a method that includes obtaining parameters for each transmission line of the clock network that carries a clock signal between a source of the clock signal and the grid, and obtaining models of nonlinear components of the clock network. A frequency domain nonlinear Harmonic Balance equation is numerically solved to obtain voltage values at an input and an output of each of the nonlinear components. A number of the voltage values obtained is proportional to the number of the nonlinear components. A physical implementation of the integrated circuit is obtained based on the clock network analysis.

DETAILED DESCRIPTION

As previously noted, clock network analysis is used to obtain a clock signal waveform at every node of the integrated circuit (chip). Because clock networks in a clock tree architecture are decoupled, clock networks can be treated like any other signal networks by using pre-characterized gate level models for the buffers and applying model order reduction techniques for clock wires. The clock network can be analyzed as part of the standard timing analysis (STA) phase of the chip design. In contrast to a clock tree architecture, the clock grid architecture, which is the focus of the present description, involves a pervasive clock grid that is driven by many global clock buffers simultaneously. These global clock buffers drive local clock structures by means of the grid. Thus, the analysis of a clock grid network must account for the coupling of endpoints of all the different clock signal paths according to the clock grid architecture.

The clock network analysis is essentially the analysis of an electrical circuit with the currents and voltages at each grid point that are unknown. Current and voltage are determined based on knowledge of transmission line parameters such as resistance R, inductance L, capacitance C, conductance G, and line length d. Frequency-dependent parasitic extraction and accurate simulation with transmission line modeling of wires is desirable. Because thick metal layers are used for long-distance interconnects in both the clock grid and the global clock tree that drives the clock grid, inductance and transmission line effects are significant. Thick metal layers and high frequency cause inductive and distributed effects. Further, because a goal of clock grid design can be to achieve skew as low as 5 picoseconds, the analysis must be accurate to fractions of a picosecond and must incorporate not only inductors but also transmission-line effects. Transition slews, waveform overshoots, and duty cycle, as well as current densities in wires, are of interest in addition to clock latencies and skews.

One prior approach to clock network analysis used time domain analysis to determine the current and voltage at nodes, including each grid point in the clock grid that is driven by the clock tree, at each time step. Time-domain simulation of the entire tree-driven grid network is composed of transmission line models for wires and transistor level models for buffers. However, based on the size of the network and the need to integrate over many periods until steady state is reached, time-domain analysis can become computationally prohibitive.

Another prior approach to clock network analysis focused on the periodicity of clock signals. Solving for the steady state in the frequency domain was proposed. However, because the approach focused on reduced order modeling of the clock wires, it was incompatible with inductive and distributed transmission-line effects.

Turning now to an overview of the present invention, the several embodiments detailed herein pertain to a nonlinear frequency domain analysis algorithm for clock network analysis of a clock network with a grid architecture. The clock network includes linear elements including the transmission lines and non-linear elements including the buffers that drive the grid. The embodiments of the invention obtain a model at the interfaces of the linear and nonlinear elements. As a result, the size of the analysis corresponds with the dimension of the interfaces rather than with the entire clock circuit. Based on the analysis at the interfaces, the analysis at each node within the grid can be completed.

Specifically, a special formulation of the known harmonic balance algorithm facilitates full frequency-dependent, frequency-domain transmission line models for the clock wires, and direct computation of the periodic steady state. The special formulation of the Harmonic Balance generates a system of equations whose size is determined only by the number of nonlinear nodes (i.e., number of buffers) and, thus, the number of interfaces of linear to nonlinear elements, rather than the full network size. Periodic steady state is computed directly instead of simulated in as many periods as computationally feasible. In addition, frequency-dependent per-unit-length transmission line parameters are used directly as they are produced by the extractor rather than by fitting a time-domain compatible model to them. Application of the Harmonic Balance algorithm to clock network analysis facilitates analysis of the clock network in the frequency domain. As detailed below, eliminating linear components of the circuit model reduces the total number of unknowns and facilitates the practical use of the Harmonic Balance algorithm.

FIG. 1is a representation of a tree-driven-grid clock network100that is analyzed according to one or more embodiments of the invention. The clock network100includes a phase-locked loop (PLL)110that is a source of the clock signal. The clock signal is propagated via transmission lines127through a buffered global tree120with buffers125at different levels to leaf buffers130at the final level of the tree120. The leaf buffers130are distributed across the chip401(FIG. 4) to drive the clock grid140simultaneously via grid driving points145. The clock grid140, in turn, drives local clock buffers and latches150through tapping points146. Although only one such tapping point146is shown inFIG. 1for illustrative purposes, the clock grid140can have many such tapping points146such that the conventional clock network analysis discussed previously is impractical. To be clear, the clock signal waveforms at the numerous tapping points146are what are of interest ultimately. According to the embodiments of the invention described herein, the clock signal waveforms at these tapping points146are found by addressing the non-linear nodes, as detailed herein.

The transmission lines127are linear components of the clock network100, and the buffers125,130are non-linear elements of the clock network100. The interface of each linear element (transmission line127) and nonlinear element (buffer125,130) is generally referred to herein as a non-linear clock tree node160. The exemplary clock network100shown inFIG. 1includes three levels of the tree120that drives the clock grid140and fourteen non-linear clock tree nodes160. Other clock networks100can include fewer or more levels of the tree120and fewer or more non-linear clock tree nodes160. The non-linear clock tree nodes160-4b,160-5b,160-6b,160-7bat the interface of the leaf buffers130and the transmission lines127to the clock grid140are of particular interest. This is because obtaining the clock signal waveform at each of these non-linear clock tree nodes160-4b,160-5b,160-6b,160-7bfacilitates obtaining the clock signal waveform at different tapping points146within the clock grid140.

FIG. 2shows an exemplary tree-driven-grid clock network100on which clock network analysis is performed according to one or more embodiments of the invention. The various transmission lines127(i.e., wires) of the clock network100must be modeled in order to obtain the clock signal waveform at the tapping points146,160. The transmission lines127shown inFIG. 2include those from the PLL110within the buffered global tree120through the leaf buffers130to those within the clock grid140. Coarser models can be used for the transmission lines127that connect to the local clock buffers and latches150. The discussion herein focuses on the analysis up to the clock grid140. Specifically, the non-linear clock tree nodes160are the non-linear nodes of interest and obtaining the clock signal waveforms at these non-linear nodes facilitates determining the clock network waveforms at the linear nodes, the grid driving points145and tapping points146.

As previously noted, the one or more embodiments of the invention relate to obtaining frequency-dependent, frequency-domain transmission line models for the transmission lines127. The special formulation of the Harmonic Balance algorithm is used to obtain direct computation of periodic steady state. A description of the derivation of the formulation is provided herein.

Periodic signals are represented as Fourier series. With a clock period T, all electrical signals in the clock distribution circuit can be expressed as circuit signals s(t):

s⁡(t)=∑k=-∞∞⁢Sk⁢ejk⁢⁢2⁢⁢π⁢tT[EQ.⁢1]
In EQ. 1, S is a vector of Fourier coefficients. The circuit signals s(t) are assumed to be band-limited such that they can be represented by a truncated Fourier series consisting of a direct current (DC) term and Nhharmonics of the fundamental frequency. Practically, the number of harmonics needed to accurately capture the signals is under 10. Thus, the Fourier series can be truncated such that the number of unknowns N is given by 2Nh+1 terms, where Nhis the number of harmonics being considered and the extra one is added for the DC term.

Then the circuit signals are given by:

s⁡(t)=∑k=-NhNh⁢Sk⁢ejk⁢⁢2⁢⁢π⁢tT[EQ.⁢2]
When one period of the time-domain signals are sampled equidistantly at time intervals ΔT=T/N, then:

sl=s⁡(l⁢⁢Δ⁢⁢T)=∑k=-NhNh⁢Sk⁢ejk⁢⁢2⁢⁢π⁢lN[EQ.⁢3]
Recognizing that the sample signals are proportional to the Inverse Discrete Fourier Transform (IDFT) of the Fourier coefficients, the equidistant time domain sample s and the frequency domain Fourier coefficients S have the following relationships:
S=F·s[EQ. 4]
s=F−1·S[EQ. 5]

As previously noted, S is the vector of Fourier coefficients and s is the vector of time-domain samples. That is:
S=[S−Nh, . . . , SNh]  [EQ. 6]
The operator F can be represented as a matrix with a special structure. Operations such as multiplication of a vector by F or F−1can be implemented using the fast Fourier transform (FFT) algorithm. The vector of samples of the time differentiated signal {dot over (s)} gives the following:
F{dot over (s)}=ΩS[EQ. 7]
where

The transmission line equations in the frequency domain are obtained as detailed below. Terminal voltages V and currents I of a multi-conductor transmission line127can be expressed in terms of the resistance R, inductance L, capacitance C, conductance G, and transmission line length d:

[V2I2]=e[0-(R+j⁢⁢ω⁢⁢L)-(G+j⁢⁢ω⁢⁢C)0]⁢d⁡[V1I1][EQ.⁢9]
The indices1and2are used to denote the two ends of the transmission line127. For nodal analysis, the terminal currents I can be expressed as a function of the terminal voltages V and the Y-parameter matrix:

[I1I2]=[h11⁡(ω)h12⁡(ω)h21⁡(ω)h⁢⁢22⁢(ω)]⁡[V1V2][EQ.⁢10]
As EQ. 9 indicates, the entries h of the Y-parameter matrix of EQ. 10 are easily computable for a given frequency ω because the resistance R, inductance L, capacitance C, conductance G, and transmission line length d are known. All the linear components of the clock network100, wires210, and lumped R, L, C models, vias, and other components will result in a large frequency domain system of equations for any given frequency ωk:
I(ωk)=Y(ωk)·V(ωk)  [EQ. 11]
In EQ. 11, V(ωk) is a matrix of voltages at all nodes (including non-linear clock tree nodes160, grid driving points145, and tapping points146) of the clock network100, Y(ωk) is a frequency-specific complex matrix, and I(ωk) is a matrix that represents the sum of the currents flowing into every node.

The variables can be partitioned according to their being part of the nonlinear side of the circuit (INk, VNk) or being exclusive to the linear network (VLk, ILk), where N denotes nonlinear and L denotes linear. This partitioning between the linear and nonlinear sides leads to the partitioning of the Y-matrix:

[0INk]=[YLLkYL⁢⁢NkYNLkYNNk]⁡[VLkVNk][EQ.⁢12]
The current sums at nodes that do not flow into the nonlinear part (e.g., current through transmission lines127within the grid140) must sum to zero by Kirchhoff s current law (KCL). As a consequence, the purely linear unknowns VLkcan be eliminated from EQ. 12. These are the voltages associated with the grid driving points145and tapping points146. The result for a given frequency ω, based on the Schur complement yk, is:
INk=(YNN−YNLYLL−1YLN)kVNk=ykVNk[EQ. 13]
The Fourier vectors of the voltages VN, which are associated with the non-linear clock tree nodes160, are then connected to the Fourier coefficient vectors of the currents INas:
IN=yVN[EQ.14]
In EQ. 14, y is given by:
y≡diag[y−Nh, . . . , yNh]  [EQ. 15]

The leaf buffers130, which are nonlinear elements, are modeled at the transistor level or by higher-level current source models. The models are expressed in the time domain as:

i⁡(t)=j⁡(x⁡(t))+ddt⁢q⁡(x⁡(t))[EQ.⁢16]
However, for the purpose of Harmonic Balance analysis, the operator must be expressed in terms of a mapping from the Fourier coefficients of the inputs X to the Fourier coefficients of the output I. The signals can be assumed to be band-limited for this operation. Assuming that the input time domain vector is sampled at x=[x0, x1, . . . , xN-1], the samples of the two components of the nonlinear terms can be evaluated as:
j=[j(x0), . . . ,j(xN-1)]  [EQ. 17]
q=[q(x0), . . . ,q(xN-1)]  [EQ. 18]
According to the notation in EQ. 17 and EQ. 18 and based on EQ. 4 and EQ. 5,
J(X)=F[j(⋅)]F−1X[EQ. 19]
Q(X)=F[q(⋅)]F−1X[EQ. 20]
I(X)=J(X)+ΩQ(X)=F[j(⋅)]F−1X+ΩF[q(⋅)]F−1X[EQ. 21]

EQ. 14 gives the current into the nonlinear components (e.g., buffers125,130) and EQ. 21 gives current within the nonlinear components. Thus, according to the KCL, the current obtained by EQ. 14 and the current obtained by EQ. 21 must sum to 0. Accordingly, EQ. 14 and EQ. 21 can be summed to obtain the special formulation of the Harmonic Balance equation:
yVN+J(VN)+ΩQ(VN)=0  [EQ. 22]

EQ. 22 is nonlinear and algebraic and VNcan be solved using a Newton algorithm. As previously noted, the size of the system (i.e., the number of elements of the vector VN) is equal to the number of non-linear clock tree nodes160multiplied by the number of necessary harmonics. In the exemplary clock network100shown inFIG. 1, there are fourteen non-linear clock tree nodes160and, thus, fourteen multiplied by the number of harmonics (e.g., 10) elements of VNto be obtained. The matrices involved in solving the system are amenable to iterative methods. That is, y in the first term of EQ. 22 can be computed. Then, based on the current models used to obtain EQ. 16 and, subsequently, EQ. 19 and EQ. 20, VNcan be solved iteratively. Once EQ. 22 is solved to obtain the nonlinear unknowns, the linear values (VLk) in the clock grid140, which correspond with the grid driving points145and tapping points146, can be solved using EQ. 12.

FIG. 3is a process flow of a method of performing clock network100analysis according to embodiments of the invention. According to the process flow shown inFIG. 3, clock signal waveforms are obtained at each node (e.g., tapping point145, grid driving point146, non-linear clock tree node160) in a clock network100that includes a clock tree120that drives a clock grid140. The clock signal waveforms are obtained at the non-linear clock tree nodes160(non-linear nodes), and those clock signal waveforms are used to obtain the clock signal waveforms at the grid driving points145and tapping points146(linear nodes). The clock signal waveforms are obtained as part of the design and verification process to ultimately obtain a physical implementation of the integrated circuit401(FIG. 4). At block310, obtaining transmission line parameters includes obtaining resistance R, inductance L, capacitance C, conductance G, and line length d in order to obtain the Y matrix according to EQ. 9, which provides y in the first term of EQ. 22. The transmission line parameters can be stored in a memory device (e.g., memory410of the system400(FIG. 4) that performs the clock network analysis according to embodiments of the invention). At block320, obtaining models of nonlinear components includes obtaining transistor or higher-level current source models. The models can also be stored in a memory device (e.g., memory410).

Numerically solving a special formulation of the Harmonic Balance equation to obtain voltage values, at block330, refers to solving EQ. 22 to obtain voltage values VNat the non-linear clock tree nodes160. The numerical solution involves iteratively evaluating current models for values of VN. EQ. 22 is a nonlinear algebraic equation obtained based on the fact that the current within a nonlinear component and the current into or out of the nonlinear component must be the same (must sum to 0 according to the KCL. Once the values of VNare obtained, solving for other voltage values, at block340, refers to obtaining VLaccording to EQ. 12. These include voltages at nodes in the clock grid140(grid driving points145and tapping points146). Obtaining clock signal waveforms, at block350, refers to obtaining the desired clock signal information from the voltages and corresponding currents determined at blocks330and340.

FIG. 4is a block diagram of a system400that performs clock network analysis according to one or more embodiments of the invention discussed herein. The design output by the system100based on processes including the clock network analysis according to one or more embodiments of the invention results in a physical implementation of the logic design in the form of the integrated circuit401. The system100and methods described herein can be implemented in hardware, software (e.g., firmware), or a combination thereof. In some embodiments of the invention, the methods described can be implemented, at least in part, in hardware and can be part of the microprocessor of a special or general-purpose computer system, such as a personal computer, workstation, minicomputer, or mainframe computer.

In some embodiments of the invention, as shown inFIG. 4, the system400includes a processor405, memory410coupled to a memory controller415, and one or more input devices445and/or output devices440, such as peripherals, that are communicatively coupled via a local I/O controller435. These devices440and445can include, for example, a printer, a scanner, a microphone, and the like. Input devices such as a conventional keyboard450and mouse455can be coupled to the I/O controller435. The I/O controller435can be, for example, one or more buses or other wired or wireless connections, as are known in the art. The I/O controller435can have additional elements, which are omitted for simplicity, such as controllers, buffers (caches), drivers, repeaters, and receivers, to enable communications.

The processor405is a hardware device for executing hardware instructions or software, particularly those stored in memory410. The processor405can be a custom made or commercially available processor, a central processing unit (CPU), an auxiliary processor among several processors associated with the system400, a semiconductor based microprocessor (in the form of a microchip or chip set), a macroprocessor, or other device for executing instructions. The processor405includes a cache470, which can include, but is not limited to, an instruction cache to speed up executable instruction fetch, a data cache to speed up data fetch and store, and a translation lookaside buffer (TLB) used to speed up virtual-to-physical address translation for both executable instructions and data. The cache470can be organized as a hierarchy of more cache levels (L1, L2, etc.).

The memory410can include one or combinations of volatile memory elements (e.g., random access memory, RAM, such as DRAM, SRAM, SDRAM, etc.) and nonvolatile memory elements (e.g., ROM, erasable programmable read only memory (EPROM), electronically erasable programmable read only memory (EEPROM), programmable read only memory (PROM), tape, compact disc read only memory (CD-ROM), disk, diskette, cartridge, cassette or the like, etc.). Moreover, the memory410can incorporate electronic, magnetic, optical, or other types of storage media. Note that the memory410can have a distributed architecture, where various components are situated remote from one another but can be accessed by the processor405.

The instructions in memory410can include one or more separate programs, each of which comprises an ordered listing of executable instructions for implementing logical functions. In the example ofFIG. 4, the instructions in the memory410include a suitable operating system (OS)411. The operating system411essentially can control the execution of other computer programs and provides scheduling, input-output control, file and data management, memory management, and communication control and related services.

Additional data, including, for example, instructions for the processor405or other retrievable information, can be stored in storage420, which can be a storage device such as a hard disk drive or solid state drive. The stored instructions in memory110or in storage420can include those enabling the processor to execute one or more aspects of the system400and methods of this detailed description.

The system400can further include a display controller425coupled to a monitor430. In some embodiments of the invention, the system400can further include a network interface460for coupling to a network465. The network465can be an IP-based network for communication between the system400and an external server, client and the like via a broadband connection. The network465transmits and receives data between the system400and external systems. In some embodiments of the invention, the network465can be a managed IP network administered by a service provider. The network465can be implemented in a wireless fashion, e.g., using wireless protocols and technologies, such as WiFi, WiMax, etc. The network465can also be a packet-switched network such as a local area network, wide area network, metropolitan area network, the Internet, or other similar type of network environment. The network465can be a fixed wireless network, a wireless local area network (LAN), a wireless wide area network (WAN) a personal area network (PAN), a virtual private network (VPN), intranet or other suitable network system and can include equipment for receiving and transmitting signals.

The flow diagrams depicted herein are just one example. There can be many variations to this diagram or the steps (or operations) described therein without departing from the spirit of the invention. For instance, the steps can be performed in a differing order or steps can be added, deleted or modified. All of these variations are considered a part of the claimed invention.

While the preferred embodiment to the invention had been described, it will be understood that those skilled in the art, both now and in the future, can make various improvements and enhancements which fall within the scope of the claims which follow. These claims should be construed to maintain the proper protection for the invention first described.