Tuning threshold voltage through meta stable plasma treatment

A method includes forming a first high-k dielectric layer over a first semiconductor region, forming a second high-k dielectric layer over a second semiconductor region, forming a first metal layer comprising a first portion over the first high-k dielectric layer and a second portion over the second high-k dielectric layer, forming an etching mask over the second portion of the first metal layer, and etching the first portion of the first metal layer. The etching mask protects the second portion of the first metal layer. The etching mask is ashed using meta stable plasma. A second metal layer is then formed over the first high-k dielectric layer.

BACKGROUND

Metal-Oxide-Semiconductor (MOS) devices are basic building elements in integrated circuits. Recent development of the MOS devices includes forming replacement gates, which include high-k gate dielectrics and metal gate electrodes over the high-k gate dielectrics. The formation of a replacement gate typically involves depositing a high-k gate dielectric layer and metal layers over the high-k gate dielectric layer, and then performing Chemical Mechanical Polish (CMP) to remove excess portions of the high-k gate dielectric layer and the metal layers. The remaining portions of the metal layers form the metal gates.

In conventional formation methods of the MOS devices, the threshold voltages of the MOS devices may be changed by performing a thermal anneal process when conducting ammonia to treat the high-k dielectric layers. Although the threshold voltage can be changed, it was impossible to adjust the threshold voltages to intended values, and further adjustment had to be achieved by adopting different work-function metals and adjusting the thickness of the work-function metals.

DETAILED DESCRIPTION

Transistors with replacement gates and the methods of adjusting the threshold voltages of the transistors are provided in accordance with various embodiments. The intermediate stages of forming the transistors are illustrated in accordance with some embodiments. Some variations of some embodiments are discussed. Throughout the various views and illustrative embodiments, like reference numbers are used to designate like elements. In accordance with some embodiments, the formation of Fin Field-Effect Transistors (FinFETs) is used as an example to explain the concept of the present disclosure. Other types of transistors such as planar transistors and Gate-All-Around (GAA) transistors may also adopt the concept of the present disclosure.

In accordance with some embodiments of the present disclosure, an ashing process for removing a Bottom Anti-Reflective Coating (BARC), which is used for patterning a layer (which may be a metal layer such as a work-function metal) on top of a gate dielectric layer, is utilized to adjust the threshold voltages of FinFETs. The flow rate of nitrogen, which is used for removing the BARC, is adjusted to adjust the threshold of the corresponding FinFETs to desirable values.

FIGS. 1-6, 7A, 7B, and 8-16illustrate the cross-sectional views and perspective views of intermediate stages in the formation of Fin Field-Effect Transistors (FinFETs) in accordance with some embodiments of the present disclosure. The processes shown in these figures are also reflected schematically in the process flow400as shown inFIG. 22.

InFIG. 1, substrate20is provided. The substrate20may be a semiconductor substrate, such as a bulk semiconductor substrate, a Semiconductor-On-Insulator (SOI) substrate, or the like, which may be doped (e.g., with a p-type or an n-type dopant) or undoped. The semiconductor substrate20may be a part of wafer10, such as a silicon wafer. Generally, an SOI substrate is a layer of a semiconductor material formed on an insulator layer. The insulator layer may be, for example, a Buried Oxide (BOX) layer, a silicon oxide layer, or the like. The insulator layer is provided on a substrate, typically a silicon substrate or a glass substrate. Other substrates such as a multi-layered or gradient substrate may also be used. In some embodiments, the semiconductor material of semiconductor substrate20may include silicon; germanium; a compound semiconductor including silicon carbide, gallium arsenic, gallium phosphide, indium phosphide, indium arsenide, and/or indium antimonide; an alloy semiconductor including SiGe, GaAsP, AlInAs, AlGaAs, GalnAs, GaInP, and/or GaInAsP; or combinations thereof.

Further referring toFIG. 1, well region22is formed in substrate20. The respective process is illustrated as process402in the process flow400as shown inFIG. 22. In accordance with some embodiments of the present disclosure, well region22is an n-type well region formed through implanting an n-type impurity, which may be phosphorus, arsenic, antimony, or the like, into substrate20. In accordance with other embodiments of the present disclosure, well region22is a p-type well region formed through implanting a p-type impurity, which may be boron, indium, or the like, into substrate20. The resulting well region22may extend to the top surface of substrate20. The n-type or p-type impurity concentration may be equal to or less than 1018cm−3, such as in the range between about 1017cm−3and about 1018cm−3.

Referring toFIG. 2, isolation regions24are formed to extend from a top surface of substrate20into substrate20. Isolation regions24are alternatively referred to as Shallow Trench Isolation (STI) regions hereinafter. The respective process is illustrated as process404in the process flow400as shown inFIG. 22. The portions of substrate20between neighboring STI regions24are referred to as semiconductor strips26. To form STI regions24, pad oxide layer28and hard mask layer30are formed on semiconductor substrate20, and are then patterned. Pad oxide layer28may be a thin film formed of silicon oxide. In accordance with some embodiments of the present disclosure, pad oxide layer28is formed in a thermal oxidation process, wherein a top surface layer of semiconductor substrate20is oxidized. Pad oxide layer28acts as an adhesion layer between semiconductor substrate20and hard mask layer30. Pad oxide layer28may also act as an etch stop layer for etching hard mask layer30. In accordance with some embodiments of the present disclosure, hard mask layer30is formed of silicon nitride, for example, using Low-Pressure Chemical Vapor Deposition (LPCVD). In accordance with other embodiments of the present disclosure, hard mask layer30is formed by thermal nitridation of silicon, or Plasma Enhanced Chemical Vapor Deposition (PECVD). A photo resist (not shown) is formed on hard mask layer30and is then patterned. Hard mask layer30is then patterned using the patterned photo resist as an etching mask to form hard masks30as shown inFIG. 2.

Next, the patterned hard mask layer30is used as an etching mask to etch pad oxide layer28and substrate20, followed by filling the resulting trenches in substrate20with a dielectric material(s). A planarization process such as a Chemical Mechanical Polish (CMP) process or a mechanical grinding process is performed to remove excess portions of the dielectric materials, and the remaining portions of the dielectric materials(s) are STI regions24. STI regions24may include a liner dielectric (not shown), which may be a thermal oxide formed through a thermal oxidation of a surface layer of substrate20. The liner dielectric may also be a deposited silicon oxide layer, silicon nitride layer, or the like formed using, for example, Atomic Layer Deposition (ALD), High-Density Plasma Chemical Vapor Deposition (HDPCVD), or Chemical Vapor Deposition (CVD). STI regions24may also include a dielectric material over the liner oxide, wherein the dielectric material may be formed using Flowable Chemical Vapor Deposition (FCVD), spin-on coating, or the like. The dielectric material over the liner dielectric may include silicon oxide in accordance with some embodiments.

The top surfaces of hard masks30and the top surfaces of STI regions24may be substantially level with each other. Semiconductor strips26are between neighboring STI regions24. In accordance with some embodiments of the present disclosure, semiconductor strips26are parts of the original substrate20, and hence the material of semiconductor strips26is the same as that of substrate20. In accordance with alternative embodiments of the present disclosure, semiconductor strips26are replacement strips formed by etching the portions of substrate20between STI regions24to form recesses, and performing an epitaxy to regrow another semiconductor material in the recesses. Accordingly, semiconductor strips26are formed of a semiconductor material different from that of substrate20. In accordance with some embodiments, semiconductor strips26are formed of silicon germanium, silicon carbon, or a III-V compound semiconductor material.

Referring toFIG. 3, STI regions24are recessed, so that the top portions of semiconductor strips26protrude higher than the top surfaces24A of the remaining portions of STI regions24to form protruding fins36. The respective process is illustrated as process406in the process flow400as shown inFIG. 22. The etching may be performed using a dry etching process, wherein HF3and NH3, for example, are used as the etching gases. During the etching process, plasma may be generated. Argon may also be included. In accordance with alternative embodiments of the present disclosure, the recessing of STI regions24is performed using a wet etch process. The etching chemical may include HF, for example.

Referring toFIG. 4, dummy gate stacks38are formed to extend on the top surfaces and the sidewalls of (protruding) fins36. The respective process is illustrated as process408in the process flow400as shown inFIG. 22. Dummy gate stacks38may include dummy gate dielectrics40and dummy gate electrodes42over dummy gate dielectrics40. Dummy gate electrodes42may be formed, for example, using polysilicon, and other materials may also be used. Each of dummy gate stacks38may also include one (or a plurality of) hard mask layer44over dummy gate electrodes42. Hard mask layers44may be formed of silicon nitride, silicon oxide, silicon carbo-nitride, or multi-layers thereof. Dummy gate stacks38may cross over a single one or a plurality of protruding fins36and/or STI regions24. Dummy gate stacks38also have lengthwise directions perpendicular to the lengthwise directions of protruding fins36.

Next, gate spacers46are formed on the sidewalls of dummy gate stacks38. The respective process is also shown as process408in the process flow400as shown inFIG. 22. In accordance with some embodiments of the present disclosure, gate spacers46are formed of a dielectric material(s) such as silicon nitride, silicon carbo-nitride, or the like, and may have a single-layer structure or a multi-layer structure including a plurality of dielectric layers.

An etching process is then performed to etch the portions of protruding fins36that are not covered by dummy gate stacks38and gate spacers46, resulting in the structure shown inFIG. 5. The respective process is illustrated as process410in the process flow400as shown inFIG. 22. The recessing may be anisotropic, and hence the portions of fins36directly underlying dummy gate stacks38and gate spacers46are protected, and are not etched. The top surfaces of the recessed semiconductor strips26may be lower than the top surfaces24A of STI regions24in accordance with some embodiments. Recesses50are accordingly formed. Recesses50comprise portions located on the opposite sides of dummy gate stacks38, and portions between remaining portions of protruding fins36.

Next, epitaxy regions (source/drain regions)52are formed by selectively growing (through epitaxy) a semiconductor material in recesses50, resulting in the structure inFIG. 6. The respective process is illustrated as process412in the process flow400as shown inFIG. 22. Depending on whether the resulting FinFET is a p-type FinFET or an n-type FinFET, a p-type or an n-type impurity may be in-situ doped with the proceeding of the epitaxy. For example, when the resulting FinFET is a p-type FinFET, silicon germanium boron (SiGeB), silicon boron (SiB), or the like may be grown. Conversely, when the resulting FinFET is an n-type FinFET, silicon phosphorous (SiP), silicon carbon phosphorous (SiCP), or the like may be grown. In accordance with alternative embodiments of the present disclosure, epitaxy regions52comprise III-V compound semiconductors such as GaAs, InP, GaN, InGaAs, InAlAs, GaSb, AlSb, AlAs, AlP, GaP, combinations thereof, or multi-layers thereof. After Recesses50are filled with epitaxy regions52, the further epitaxial growth of epitaxy regions52causes epitaxy regions52to expand horizontally, and facets may be formed. The further growth of epitaxy regions52may also cause neighboring epitaxy regions52to merge with each other. Voids (air gaps)53may be generated. In accordance with some embodiments of the present disclosure, the formation of epitaxy regions52may be finished when the top surface of epitaxy regions52is still wavy, or when the top surface of the merged epitaxy regions52has become planar, which is achieved by further growing on the epitaxy regions52as shown inFIG. 6.

After the epitaxy step, epitaxy regions52may be further implanted with a p-type or an n-type impurity to form source and drain regions, which are also denoted using reference numeral52. In accordance with alternative embodiments of the present disclosure, the implantation process is skipped when epitaxy regions52are in-situ doped with the p-type or n-type impurity during the epitaxy.

FIG. 7Aillustrates a perspective view of the structure after the formation of Contact Etch Stop Layer (CESL)58and Inter-Layer Dielectric (ILD)60. The respective process is illustrated as process414in the process flow400as shown inFIG. 22. CESL58may be formed of silicon oxide, silicon nitride, silicon carbo-nitride, or the like, and may be formed using CVD, ALD, or the like. ILD60may include a dielectric material formed using, for example, FCVD, spin-on coating, CVD, or another deposition method. ILD60may be formed of an oxygen-containing dielectric material, which may be a silicon-oxide based material formed using Tetra Ethyl Ortho Silicate (TEOS) as a precursor, Phospho-Silicate Glass (PSG), Boro-Silicate Glass (BSG), Boron-Doped Phospho-Silicate Glass (BPSG), or the like. A planarization process such as a CMP process or a mechanical grinding process may be performed to level the top surfaces of ILD60, dummy gate stacks38, and gate spacers46with each other.

FIG. 7Billustrates the cross-sectional views of an intermediate structure in the formation of a first FinFET and a second FinFET on the same substrate20, and in the same die and the same wafer. Either one of the First FinFET and the second FinFET may correspond to the cross-sectional view obtained from the vertical plane containing line7B-7B inFIG. 7A. The first FinFET is formed in device region100, and the second FinFET is formed in device region200. The threshold voltages of the first FinFET and the second FinFET may be different for each other. In accordance with some embodiments of the present disclosure, both the first FinFET and the second FinFET are n-type FinFETs or p-type FinFETs. In accordance with alternative embodiments of the present disclosure, the first FinFET is an n-type FinFET, and the second FinFET is a p-type FinFET. Alternatively, the first FinFET is a p-type FinFET, and the second FinFET is an n-type FinFET. In the discussed example, the formation of an n-type FinFET and a p-type FinFET are illustrated, while other combinations of FinFETs are also contemplated.

To distinguish the features in the First FinFET from the features in the second FinFET, the features in the First FinFET may be represented using the reference numerals of the corresponding features inFIG. 7Aplus number100, and the features in the second FinFET may be represented using the reference numerals of the corresponding features inFIG. 7Aplus number200. For example, the source/drain regions152and252inFIG. 7Bcorrespond to source/drain region52inFIG. 7A, and gate spacers146and246inFIG. 7Bcorrespond to the gate spacers46inFIG. 7A. The corresponding features in the First FinFET and the second FinFET may be formed in common processes.

After the structure shown inFIGS. 7A and 7Bis formed, the dummy gate stacks including hard mask layers44, dummy gate electrodes42, and dummy gate dielectrics40are replaced with metal gates and replacement gate dielectrics, as shown by the processes shown inFIGS. 8 through 16. InFIGS. 8 through 16, the top surfaces124A and224A of STI regions24are illustrated, and semiconductor fins136and236protrude higher than top surfaces124A and224A, respectively.

To form the replacement gates, hard mask layers44, dummy gate electrodes42, and dummy gate dielectrics40as shown inFIGS. 7A and 7Bare removed, forming openings147and247as shown inFIG. 8. The respective process is illustrated as process416in the process flow400as shown inFIG. 22. The top surfaces and the sidewalls of protruding fins136and236are exposed to openings147and247, respectively.

Next, referring toFIG. 9, gate dielectrics154/156and254/256are formed, which extend into openings147and247, respectively. The respective process is illustrated as process418in the process flow400as shown inFIG. 22. In accordance with some embodiments of the present disclosure, the gate dielectrics include Interfacial Layers (ILs)154and254, which are formed on the exposed surfaces of protruding fins136and236, respectively. ILs154and254may include oxide layers such as silicon oxide layers, which are formed through the thermal oxidation of protruding fins136and236, a chemical oxidation process, or a deposition process. The gate dielectrics may also include high-k dielectric layers156and256over the corresponding ILs154and254. High-k dielectric layers156and256may be formed of a high-k dielectric material such as hafnium oxide, lanthanum oxide, aluminum oxide, zirconium oxide, or the like. The dielectric constant (k-value) of the high-k dielectric material is higher than 3.9, and may be higher than about 7.0, and sometimes as high as 21.0 or higher. High-k dielectric layers156and256are overlying, and may contact, the respective underlying ILs154and254. High-k dielectric layers156and256are formed as conformal layers, and extend on the sidewalls of protruding fins136and236and the top surfaces and the sidewalls of gate spacers146and246, respectively. In accordance with some embodiments of the present disclosure, high-k dielectric layers156and256are formed using ALD or CVD.

Further referring toFIG. 9, a metal layer is formed. The respective process is illustrated as process420in the process flow400as shown inFIG. 22. The metal layer includes portion162in device region100, and portion262in device region200, and portions162and262are referred to as metal-containing layers. Metal-containing layers162and262are formed through deposition. The deposition may be performed using a conformal deposition method such as ALD or CVD, so that the horizontal thickness of the horizontal portions and vertical thickness of the vertical portions of metal-containing layer262(and each of sub-layers) are substantially equal to each other. For example, horizontal thickness T1and vertical thickness T2may have a difference smaller than about 20 percent or 10 percent of either of thicknesses T1and T2. In accordance with some embodiments of the present disclosure, metal-containing layers162and262extend into openings147and247(FIG. 8), and include some portions over ILD60.

Metal-containing layers162and262may include a p-type work-function metal layer such as a TiN layer. In accordance with some embodiments of the present disclosure, each of metal-containing layers162and262is a single layer such as a TiN layer. In accordance with other embodiments, each of metal-containing layers162and262is a composite layer including a plurality of layers formed of different materials. For example, each of metal-containing layers162and262may include a TiN layer, a TaN layer, and another TiN layer, respectively.

Bottom Anti-Reflective Coating (BARC)66is formed on metal-containing layers162and262. The respective process is illustrated as process422in the process flow400as shown inFIG. 22. In accordance with some embodiments of the present disclosure, BARC66is formed of a photo resist, which is baked and hence cross-linked. Next, photo resist68is applied and patterned, so that the portion of photo resist68in device region100is removed, and the portion of photo resist68in device region200remains. The respective process is illustrated as process424in the process flow400as shown inFIG. 22.

FIG. 10illustrates an etching process, in which photo resist68is used as the etching mask. The portion of BARC66in device region100is removed in the etching process. The respective process is illustrated as process426in the process flow400as shown inFIG. 22. In a subsequent process, as shown inFIG. 11, photo resist68is removed, and the underlying BARC66is revealed.

An etching process is then performed to etch metal-containing layer162. The respective process is illustrated as process428in the process flow400as shown inFIG. 22. As a result, high-k dielectric layer156is revealed. The resulting structure is shown inFIG. 12. BARC66is used as an etching mask to protect metal-containing layer262during the etching process. In accordance with some embodiments of the present disclosure, the etching process is performed through wet etching. For example, when metal-containing layer162is formed of TiN, the etching chemical may include a chemical solution including ammonia (NH3), hydrogen peroxide (H2O2), and water. In accordance with alternative embodiments, a dry etching process may be used.

FIG. 13illustrates the removal of BARC66through an ashing process, in which plasma is generated, which is represented by arrows67. The respective process is illustrated as process430in the process flow400as shown inFIG. 22. A production tool300used for the ashing of BARC66is shown inFIG. 17. Production tool300is configured to generate plasma, for example, through Inductively Coupled Plasma (ICP). Furthermore, Wafer10is placed over a wafer holder302, which may be an electric Chuck (E-Chuck). Shower head304is located over wafer10, in which plasma is generated from process gases. The plasma includes ions and radicals, which are filtered by shower head304, so that radicals pass through holes306A in shower head304to reach wafer10, and ions are blocked, and are not able to pass through holes306A.

Production tool300is configured to generate meta stable plasma, which have lifetime longer than typical plasma. Metastable state is an excited state of an atom or other system with a longer lifetime than the other excited states. For example, the atoms and radicals in the metastable state may remain excited for a considerable time in the order of about 1 second. However, the metastable state has a shorter lifetime than the stable ground state. The meta stable state is generated by conducting helium (He) gas and N2gas into shower head304, and plasma is generated from He to generate He* radical.

As shown inFIG. 17, shower head304is a dual plenum shower head, which includes two inputs310A and310B. The first input310A may be at the top of the shower head304. In accordance with some embodiments, the mixed gases N2and He are conducted into an inner chamber of shower head304through input310A, and hence the ions N+and He+, electrons e−, and radicals N* and He* are generated, for example, by coil308. The inner chamber is connected to holes306A, which are configured to trap the ions N+and He+and allows the radicals N* and He* to pass through.

The second input310B may be at on the sides of the shower head304, and the second input310B is not connected to the inner chamber. In accordance with some embodiments, hydrogen (H2) is conducted into shower head304through input310B. The second input310B is connected to holes306B, which are facing wafer10. Accordingly, the H2gas bypasses coil308, and is not excited by the coils308. Accordingly, the H2has a low energy.

Further referring toFIG. 17, when H2is conducted through the tunnels inside the sidewalls of shower head304to output from holes306B, the H2gas, meeting He* and N* radicals, are excited, and hence H* radicals are generated. Since the H* receives energy from He* and N* radicals rather than directly from the coil308, the energy state of H* is low. The low energy state of the resulting H* makes it possible to adjust the type and the amount of the trapped charges in high-k dielectric layer156(FIG. 13). The trapped charges affect the flat-band voltage (and the threshold voltage) of the resulting FinFET in device region100.

As a result of exposing high-k dielectric layer156to the meta stable plasma, the ions and molecules such as N+and NH−, etc., which are generated in the plasma, are trapped in high-k dielectric layer156, and hence the corresponding charges are trapped in high-k dielectric layer156. The trapping of the charges result in the change and the adjustment of the threshold voltage of FinFET in device region100, which is revealed byFIG. 18.

FIG. 18illustrates experiment results, wherein flat-band voltages are illustrated as a function of flow rates of N2. The flat-band voltages are obtained from MOS capacitors (MOSCAPs), whose gates include high-k gate dielectrics that are treated using meta stable plasma, which is discussed referring toFIG. 17. The X-axis represents the flow rates of N2, and the Y-axis represents the flat-band voltages of the MOS capacitors. The results inFIG. 18are obtained when the flow rate of H2is 4,000 sccm, and the flow rate of He is 1,000 sccm. Line320are the flat-band voltages obtained when different flow rates of N2are used for conducting the ashing process as inFIG. 13. Line320reveals that different flow rates of N2(in the ashing of BARC66) results in the resulting MOSCAPs to have different flat-band voltages, which are closely associated with threshold voltages. Furthermore, higher flat-band voltages are associated with higher threshold voltages. Accordingly, line320also reveals that different flow rates of N2(in the ashing of BARC66) results in the resulting FinFETs to have different threshold voltages.

As shown inFIG. 18, when the flow rate of N2is at a certain value, such as about 2,000 sccm, the corresponding flat-band voltage (hence the threshold voltage) is the lowest. When the flow rate of N2is increased or reduced, the flat-band voltages increase. This may be caused by the change in the amount of radicals H*, H*N*, and NH*, as shown inFIG. 18. In accordance with some embodiments of the present disclosure, the meta stable plasma treatment process uses a nitrogen flow rate smaller than about 10,000 sccm. Metastable type source can also produce by He, N2, and/or O2as side injection gases.

In accordance with some embodiments, the correlation between the threshold voltages and the flow rates of N2may be established. For example, a plurality of samples may be manufactured having, for example, the structure as shownFIG. 14. Each of the samples goes through an ashing process (to remove BARC66) using a certain flow rate of N2, and the flow rates of N2for different samples are different from each other. The threshold voltages (and flat-band voltages) of the samples are measured/determined, so that the correlation between the threshold voltages and the corresponding flow rates of N2is established. In the manufacturing of FinFETs, when some FinFETs are intended to have certain threshold voltages, the corresponding flow rates of N2may be found from the correlation, and the corresponding flow rates of N2is adopted in the corresponding ashing processes to adjust its threshold voltage.

In addition, on a same device die, if two or more FinFETs (which may be n-type, p-type, or some are n-type and some are p-type) on a same die (same wafer) are intended to have different threshold voltages Vt, the difference in the threshold voltages Vt may be achieved by adopting different flow rates of N2, while other structures and materials of the FinFETs may be identical to each other. For example, the two FinFETs may have identical work function metals with identical thicknesses. Furthermore, the two or more FinFETs may share same manufacturing processes, except that different flow rates of N2are adopted. In accordance with some embodiments, there are device regions100′ and200′ (schematically shown inFIG. 13) in addition to device regions100and200. The features and the formation processes in the device region100′ are identical to device region100, and the features and the formation processes in the device region200′ are identical to device region200. The BARC66in device region200is ashed using a first N2flow rate, and the high-k dielectric layer156in device region100is exposed to the plasma generated using the first N2flow rate when the BARC66in device region200is ashed. The BARC66in device region200′ is ashed using a second N2flow rate different from the first N2flow rate, and the high-k dielectric layer156in device region100′ is exposed to the respective plasma. As a result, the FinFETs in device regions100and100′ have different threshold voltages, and the rest of the structures of the FinFETs in device regions100and100′ are identical. The rest of the processes (such as what are shown inFIGS. 14-16) in device regions100and100′ may be the same with each other, and share same processes. The rest of the processes (such as what are shown inFIGS. 14-16) in device regions200and200′ may be the same with each other, and share same processes.

FIGS. 19 and 20illustrate experiment results, which demonstrate the difference in the flat-band voltages of the device in device region200when convention ICP and meta stable plasma, respectively, are used for the ashing of BARC66. Each ofFIGS. 19 and 20illustrates the flat-band voltages and the corresponding ashing duration.FIG. 19is obtained when conventional ICP is used, in which N2and H2(with no He used) are provided from the input310A inFIG. 17, hence the radicals have high energies. No gas is provided from input310B. Data322,324, and326inFIG. 19are obtained with the corresponding ashing duration being zero seconds (no ashing), 180 seconds, and 220 seconds, respectively. The data indicate that with the increase in the ashing time, the flat-band voltages increase, causing the increase in the threshold voltages of the devices in device region200(FIG. 13). This is undesirable since it is preferred that the threshold voltage of the device in device region200is not changed when the threshold voltage of the device in device region100is adjusted. The undesirable change in the threshold voltage of the device in device region200is due to the high energy of the radicals, hence metal-containing layer262and BARC66(FIG. 13) are unable to mask the effect of the radicals.

FIG. 20is obtained when meta stable plasma according to the embodiments of the present disclosure is used. Data328,330,332,334, and336are obtained with the corresponding ashing duration increase. The data indicate that with the increase in the ashing time, the flat-band voltages remain substantially stable, and hence the threshold voltages of the devices in device region200(FIG. 13) is not changed. This allows the threshold voltages of the FinFETs in device region100to be adjusted independently without affecting the threshold voltages of the FinFETs in device region200.

FIG. 21illustrates the hydrogen concentrations in high-k dielectric layer156(FIG. 13) when different ashing conditions are used. The X-axis represents the depth into the respective samples, and the Y-axis represents the concentrations (atoms/cm3). Lines337,338, and340represent the H−concentrations obtained when the N2flow rate is 3,000 sccm, 1,500 sccm, and 0 sccm (no ashing is performed), respectively. The results indicate that line336has a higher hydrogen concentrations than lines338and340, indicating it corresponding to more W trapped in high-k dielectric layer156. This also indicates that the N2flow of 3,000 sccm corresponds to more negative charges (H−), and hence the corresponding transistor formed using 3,000 sccm N2ashing has a higher threshold voltage than the transistor exposed to the 1,500 sccm N2ashing.FIG. 21also demonstrates that the threshold voltages of transistors may be adjusted by adjusting the flow rate of N2.

The meta stable plasma ashing also helps reduce oxidation of TiN, which may be used to form metal-containing layer262. X-ray Photoelectron Spectroscopy (XPS) analysis has been performed on TiN films, which have BARCs formed thereon, and the BARCs are ashed using either meta stable plasma or convention ICP plasma. It is observed that a sample undergoes a conventional ICP plasma ashing has Ti2P intensity values of 20.0 before the ashing process and 18.7 after the ashing process. Accordingly, the ICP plasma reduces the Ti2P value by 1.3. As a comparison, a sample undergoes meta stable plasma ashing has Ti2P intensity values of 19.6 before the ashing process and 19.1 after the ashing process, respectively. Accordingly, the meta stable plasma reduces the Ti2P value by 0.5, which is smaller than 1.3. This means that the meta stable plasma also results in less oxidation of the TiN (layer262) when its overlying BARC66is ashed.

The hydrogen radicals as generated by the meta stable plasma are used to ash and remove BARC66, as shown inFIGS. 13 and 14.FIG. 14illustrates the structure after BARC66is ashed. At this time, metal-containing layer262provides protection to the underlying high-k dielectric layer56from receiving charges such as N+and NH−, and prevents the adjustment of the threshold of the resulting FinFET.

As a result of the meta stable plasma ashing process that adopt N2as a process gas, nitrogen is trapped in high-k dielectric layer156, for example, in the form of N+and NH−. Accordingly, the meta stable plasma process may replace the conventional thermal nitridation processes performed on high-k dielectric layers, which uses ammonia as a process gas. Accordingly, in accordance with some embodiments of the present disclosure, no thermal nitridation processes using ammonia is performed on high-k dielectric layers throughout the formation of the FinFETs.

FIG. 15illustrates the continued formation of the FinFETs. In accordance with some embodiments of the present disclosure, an n-type work function layer, which includes portion164in device region100, and portion264in device region200, is deposited. The respective process is illustrated as process432in the process flow400as shown inFIG. 22. In accordance with some embodiments, the n-type work function layers164and264include a single layer such as a TiAl layer. In accordance with other embodiments, each of the n-type work function layers164and264includes a composite layer including a TiN layer, a TaN layer, and an Al-based layer (formed of, for example, TiAlN, TiAlC, TaAlN, or TaAlC). A blocking layer and a filling metal are then deposited to form metal regions168and268. The respective process is illustrated as process434in the process flow400as shown inFIG. 22. A planarization process such as a CMP process or a mechanical grinding process is then performed, forming metal gates170and270. Replacement gate stacks172and272, which include the corresponding gate electrodes170and270and the corresponding gate dielectrics154/156and254/256are also formed. FinFETs174and274are thus formed.

Referring toFIG. 16, gate electrodes170and270are recessed, and are filled with a dielectric material (such as SiN) to form hard masks176and276. Etch stop layer78is formed over hard masks176and276and ILD60. Etch stop layer78is formed of a dielectric material, which may include silicon carbide, silicon nitride, silicon oxynitride, or the like. ILD80is formed over etch stop layer78, and gate contact plugs182and282are formed in ILD80.

The embodiments of the present disclosure have some advantageous features. The etching mask for etching a metal layer formed on a high-k dielectric layer of a transistor is removed through ashing using meta stable plasma. The energy of the meta stable plasma is low. Accordingly, unlike the conventional ICP plasma ashing, in which the effect of adjusting threshold is saturated, the threshold voltage of the transistor can be adjusted by adjusting the flow rate of nitrogen. Also, the transistor whose metal layer is directly under the ashed mask is protected by the metal layer from being affected by the meta stable plasma, and hence the threshold voltage of the respective transistor is not affected by the ashing process.

In accordance with some embodiments of the present disclosure, a method comprises forming a first high-k dielectric layer over a first semiconductor region; forming a second high-k dielectric layer over a second semiconductor region; forming a first metal layer comprising a first portion over the first high-k dielectric layer and a second portion over the second high-k dielectric layer; forming an etching mask over the second portion of the first metal layer; etching the first portion of the first metal layer, wherein the etching mask protects the second portion of the first metal layer; ashing the etching mask using meta stable plasma; and forming a second metal layer over the first high-k dielectric layer. In accordance with some embodiments, the method further comprises generating the meta stable plasma using nitrogen gas, hydrogen gas, and helium gas. In accordance with some embodiments, the nitrogen gas and the helium gas are input into a first input of a shower head, and the hydrogen gas is input into a second input of the shower head to mix with radicals generated from the nitrogen gas and the helium gas. In accordance with some embodiments, when the etching mask is ashed, the first high-k dielectric layer is exposed to the meta stable plasma. In accordance with some embodiments, the first high-k dielectric layer is not thermally nitridated. In accordance with some embodiments, the first metal layer is a p work-function layer, and the second metal layer is an n-type work-function layer.

In accordance with some embodiments of the present disclosure, a method comprises forming a metal layer over a high-k dielectric layer; forming a Bottom BARC over the metal layer; forming a photo resist over the BARC; patterning the photo resist; etching the BARC using the patterned photo resist as an etching mask; and removing the BARC using meta stable plasma, wherein the meta stable plasma is generated by processes comprising: conducting nitrogen and helium into a first input of a shower head to generate a plasma; filtering to remove ions from the plasma, with nitrogen radicals and helium radicals left in the plasma; and conducting hydrogen into a second input of the shower head, wherein hydrogen is mixed with the nitrogen radicals and helium radicals. In accordance with some embodiments, the method further comprises exposing a high-k dielectric layer to the meta stable plasma. In accordance with some embodiments, the method further comprises forming source and drain regions on opposite sides of the high-k dielectric layer; and depositing a work function layer on the high-k dielectric layer. In accordance with some embodiments, the forming the metal layer comprises forming an n-type work function layer. In accordance with some embodiments, the forming the metal layer comprises forming a p-type work function layer. In accordance with some embodiments, when the nitrogen and helium are conducted into the first input of the shower head to generate the plasma, the hydrogen is not passed through coils surrounding the shower head. In accordance with some embodiments, the method further comprises forming a plurality of transistors comprising forming a plurality of high-k dielectric layers, wherein the plurality of high-k dielectric layers are formed of a same high-k dielectric material; performing a plurality of treatment processes using meta stable plasma, with nitrogen, hydrogen, and helium being used as process gases, wherein each of the plurality of treatment processes is performed on one of the plurality of high-k dielectric layers, and nitrogen flow rates in the plurality of treatment processes are different from each other; and determining threshold voltages of the plurality of transistors to establish a correlation between nitrogen flow rates and the threshold voltages. In accordance with some embodiments, hydrogen flow rates in the plurality of treatment processes are same as each other, and helium flow rates in the plurality of treatment processes are same as each other.

In accordance with some embodiments of the present disclosure, a method comprises forming a first high-k dielectric layer and a second high-k dielectric layer on a wafer, wherein the first high-k dielectric layer and the second high-k dielectric layer are formed of a same high-k dielectric material; performing a first treatment process on the first high-k dielectric layer using a first meta stable plasma process, with nitrogen, hydrogen, and helium being used as process gases, and the nitrogen having a first flow rate; performing a second treatment process on the second high-k dielectric layer using a second meta stable plasma process, with nitrogen, hydrogen, and helium being used as process gases, and the nitrogen having a second flow rate; and forming a first metal layer and a second metal layer over the first high-k dielectric layer and the second high-k dielectric layer, respectively. In accordance with some embodiments, hydrogen flow rates in the first treatment process and the second treatment process are same as each other, and helium flow rates in the first treatment process and the second treatment process are same as each other. In accordance with some embodiments, the first high-k dielectric layer and the second high-k dielectric layer are in a same die of the wafer. In accordance with some embodiments, the first high-k dielectric layer and the second high-k dielectric layer are parts of n-type transistors.