Method and apparatus for measuring wafer bias potential

A device for use in a wafer processing chamber having a plasma forming volume and a hot edge ring. The hot edge ring has a first surface and a second surface. The first surface is in contact with the plasma forming volume. The second surface is not in contact with the plasma forming volume. The device includes a detector operable to contact the second surface of the hot edge ring. The detector can detect a parameter of the hot edge ring and can provide a detected signal based on the detected parameter.

BACKGROUND

The present invention relates to wafer processing chambers. More particularly, the present invention relates to an apparatus for measuring the DC bias potential of a wafer during plasma processing.

In conventional wafer processing systems, it is common to affix the wafer to the lower electrode pedestal with an electrostatic attraction force provided by an electrostatic chuck (ESC). Electrostatic chucking is commonly implemented by providing a conductive film between two insulation films located on the upper surface of the pedestal. Once a semiconductor wafer is affixed to the ESC, the wafer may be processed.

In the conventional production of semiconductor integrated circuits, plasma is used to promote ionization of a process gas for etching, chemical vapor deposition or sputtering a wafer. In a conventional capacitive plasma processing system, upper and lower electrodes, e.g., large area parallel plates, are provided in a pressure-controlled process chamber with the electrodes facing each other.

In this plasma processing system, the electrode located at the top or upper portion of the chamber, is connected to ground potential, and a high-frequency voltage is applied to the electrode at the bottom or lower portion of the chamber. The lower electrode also serves as a pedestal. A process gas is converted into plasma by the electrical discharge between the upper and lower electrodes.

Strong electric field regions are produced between the electrodes and the plasma. These strong electric field regions are referred to as plasma sheaths. The strong electrical field regions accelerate the electrons and ions from the electrodes to the plasma and vice-versa.

Electrons and ions in the plasma are attracted to a semiconductor wafer residing on the pedestal by the force of an electric field. The ions react with the surface of the semiconductor.

In a conventional plasma processing apparatus, a high-frequency voltage is applied to the lower electrode by a capacitor, and as a result a high-frequency voltage is also applied to the wafer located on the pedestal. This configuration generates a substantially negative DC voltage potential on the pedestal and the wafer. The negative DC voltage potentials are commonly referred to as DC bias potentials.

During the half cycle when the high-frequency voltage is positive, negatively charged electrons in the plasma are attracted to the wafer, whereas during the other half cycle when the high-frequency voltage is negative, positively charged ions in the plasma are attracted to the wafer.

Since an electron has a smaller weight than that of an ion, electrons are more easily transferred to the wafer than the ions are. Consequently, the wafer becomes negatively charged, as more electrons are attracted to the wafer than ions. Thus, the wafer develops a substantially negative DC bias potential.

The DC bias potential increases the energy of the ion presented to the wafer and consequently alters the effectiveness of the wafer processing system. Excessively large bias voltages in the range of 400V to 500V can damage the oxide film on the surface of a wafer. Hence it is crucial in wafer processing systems to be able to monitor and control the DC bias potential of the wafer, or wafer potential. Direct measurement of wafer potential is very difficult. It is virtually impossible to attach or connect a probe to the wafer for direct measurement of the wafer potential, as probes are incapable of withstanding the harsh environment surrounding the wafer.

Several conventional methods have been developed for estimating the wafer potential in a semiconductor processing system. While these conventional methods are capable of providing an estimate of the wafer potential, each method has issues with respect to accuracy, longevity, maintenance, configuration and/or potential for errors.

One convention method for estimating wafer potential uses a probe located within the chamber wall of the plasma processing system. Such a conventional method will now be described with reference toFIG. 1.

FIG. 1illustrates an example of a conventional wafer processing system100. As illustrated, wafer processing system100includes a communication channel104, a user interface106, a 2 MHz RF generator110, a 27 MHz RF generator112, a 60 MHz RF generator114, an impedance matching circuit116, an ESC118, an ESC base plate120, a wafer processing chamber122, a ceramic coupling ring126, a hot edge ring (HER)128, a voltage measuring instrument130, and a probe132.

A wafer102resides on and is clamped to ESC118by an electrostatic attraction force. HER128surrounds ESC118and provides a uniform etch rate and reduced etch rate drift near the edge of wafer102. Ceramic coupling ring126surrounds ESC118and is located beneath HER128. ESC base plate120is located beneath ESC118and ceramic coupling ring126.

Impedance matching circuit116receives driving signals from 2 MHz RF generator110, 27 MHz RF generator112and 60 MHz RF generator114and provides an appropriate RF signal124to ESC base plate120. Impedance matching circuit116is configured such that its impedance is the complex conjugate of the impedance of wafer processing chamber122, thus minimizing reflected energy and enabling maximum RF energy transfer of the signals provided by 2 MHz RF generator110, 27 MHz RF generator112and 60 MHz RF generator to wafer processing chamber122.

A plasma108is generated above wafer102as a result of the RF energy supplied by RF signal124. Plasma108is used to convert or process wafer102by bombarding wafer102with positively charged ions. A plasma sheath136is located between plasma108and wafer102, HER128. Positively charged ions are propelled across plasma sheath136due to a strong electric field region located between plasma108and wafer102, HER128.

Information related to the status of wafer processing chamber122is communicated to user interface106by communication channel104. Further, a user (not shown) is operable to control 2 MHz RF generator110, 27 MHz RF generator112and 60 MHz RF generator114, by way of user interface106and communication channel136.

Probe132is fabricated from electrically conductive material and is attached to the side of wafer processing chamber122. An electrical conductor134is attached to probe132and exits wafer processing chamber122and connects to voltage measuring instrument130. Voltage measuring instrument130is capable of measuring either AC (peak-to-peak) or DC (bias level) voltages.

Voltage measuring instrument130measures the potential of wafer102.

In conventional wafer processing system100, probe132does not directly contact wafer102or plasma sheath136and is prone to errors in the measurement of the potential of wafer102as presented to voltage measuring instrument130. Additionally, for configurations of wafer processing system100using multi-frequency driven plasma, the errors in the estimated potential for wafer102are especially pronounced during complex load transitions. This method for processing wafers can be difficult to calibrate and configure as a result of the complex load transition errors which occur in the estimated potential of wafer102.

Another conventional method for estimating the wafer potential is by providing electrodes located about the periphery of the ESC, which are in contact with the wafer. The electrodes are commonly constructed of silicon carbide probes. Unfortunately, the use of these electrodes produces contaminants within the process chamber, as the electrodes are erroded by the plasma. This contamination negatively impacts the effectiveness of the plasma by reducing the plasma etch rate. Additionally, the electrodes are consumable and must frequently be replaced requiring significant time, effort and cost.

FIG. 2illustrates an example of a conventional wafer processing system200. Wafer processing system200contains several common elements wafer processing system100ofFIG. 1. However, probe132and electrical conductor134of wafer processing system100are replaced with a probe202and an electrical conductor204in wafer processing system200. As illustrated inFIG. 2, an upper end of a probe202contacts the underside of wafer102through a cavity206provided through ESC base plate120, ESC118and HER128. Lower end of probe202connects to electrical conductor204. Electrical conductor204connects to voltage measuring instrument130.

Probe202is commonly constructed of a silicon carbide pin. The potential of wafer102is detected by probe202and transferred to voltage measuring instrument130. Voltage measuring instrument130is then capable of measuring AC (peak-to-peak) or DC (bias level) voltages of wafer102.

While wafer processing system200enables accurate measurement of the potential of wafer102, it causes contaminants to be projected into the processing chamber from the consumption of probe202during wafer processing. These contaminates negatively impact the effectiveness of the plasma by reducing the plasma etch rate. Additionally, the electrodes are consumable and must frequently be replaced requiring significant time, effort and cost.

Another conventional method for measuring the wafer potential is performed by varying the DC voltage applied to the electrostatic chucking electrode and measuring the leakage current between the wafer and the electrostatic chucking electrode. The measured leakage current is then used to estimate the wafer potential.

While the leakage current measurement method for estimating the wafer potential provides a capable wafer processing system, the method is highly dependant upon the magnitude of the leakage current. The magnitude of the leakage current can vary significantly depending upon the configuration of the plasma processing system. Hence, the ESC leakage current detection method for estimating the wafer potential requires considerable time, effort and cost for calibration and configuration.

Unfortunately, conventional methods for measuring the wafer potential are inaccurate, have short lifetimes, are prone to errors and require significant effort for maintenance and configuration. What is needed is a method for measuring the wafer potential that is accurate, has a prolonged lifetime, is not prone to errors and does not require a significant amount of effort for maintenance and configuration.

BRIEF SUMMARY

It is an object of the present invention to provide an apparatus for measuring the wafer potential located in a plasma processing system that is accurate, provides a sustained lifetime, is not prone to errors and provides for ease of maintenance and configuration.

An aspect of the present invention includes a device for use in a wafer processing chamber having a plasma forming volume and a hot edge ring. The hot edge ring has a first surface and a second surface. The first surface is in contact with the plasma forming volume. The second surface is not in contact with the plasma forming volume. The device includes a detector operable to contact the second surface of the hot edge ring. The detector can detect a parameter of the hot edge ring and can provide a detected signal based on the detected parameter.

DETAILED DESCRIPTION

In accordance with an aspect of the present invention, an HER is used as a plasma sheath voltage transducer to monitor wafer potential in a wafer processing system. Accordingly, in accordance with an aspect of the present invention, voltage probe is not exposed to the plasma as with conventional systems discussed above with reference toFIGS. 1 and 2.

Aspects of the present inventions will now be described with reference toFIGS. 3-10B.

FIG. 3illustrates an example of a wafer processing system300in accordance with an aspect of the present invention. Wafer processing system300contains several common elements wafer processing system200ofFIG. 2. However, wafer processing system300does not include probe202and electrical conductor204. Wafer processing system300further includes a signal conditioner310and a processor304. Additionally, ESC base plate120and ceramic coupling ring126of wafer processing system200have been replaced with an ESC base plate312and a ceramic coupling ring314in wafer processing system300.

ESC base plate312and ceramic coupling ring314enable generation and transmission of an electrical signal308. Electrical signal308exits ceramic coupling ring314and is transmitted from wafer processing chamber122to signal conditioner310. Signal conditioner310includes circuitry for filtering the RF signal from electrical signal308to provide a DC bias potential306, which is a representation of the potential of wafer102.

DC bias potential306is useful for plasma tool process monitoring, process end point detection and detection of significant process events. DC bias potential306is transmitted to processor304. Processor304monitors DC bias potential306to verify the proper processing of wafer102and to monitor for error conditions within wafer processing chamber122. Processor304enables a user to monitor the operation of wafer processing chamber122and determine if an error condition has occurred.

A cutout302is provided in order to detail an embodiment of the present invention located within the cutout area, and will be described below with reference toFIG. 4.

FIG. 4is a cross-sectional view of cutout302as illustrated inFIG. 3. HER128has a bottom surface404and a slanted surface408. Ceramic coupling ring314has a top surface406. Bottom surface404of HER128rests on top surface406of ceramic coupling ring314. Slanted surface408is located on the inner diameter of HER128and is exposed to plasma during wafer processing. Wafer102is disposed upon ESC118and resides close to slanted surface408of HER128. Slanted surface408of HER128is provided in order to aid in positioning wafer102and also for beneficial shaping of plasma108near the edge of wafer102.

As illustrated in the figure, a signal detector400resides in a space402within ESC base plate312and ceramic coupling ring314. A hole410extends from space402to top surface406of ceramic coupling ring314. Signal detector400is in electrical contact with HER128through hole410and produces electrical signal308. Accordingly, HER128serves as a probe to measure wafer potential.

The aspect of using HER128as a probe to measure wafer potential is best explained by: first showing that the plasma potential as measured by a probe202is linearly related to the wafer potential as measured by a wired wafer; then by discussing that HER128being used as a probe to measure the plasma potential is linearly related to the plasma potential as measured by a probe202; and then experimentally verifying that HER128may be used as a probe to measure the wafer potential.

Returning toFIG. 2, it has been determined that the plasma potential as measured by probe202is linearly related to the wafer potential as measured by a wired wafer.

FIG. 5is a graph500comparing plasma potential as measured by probe202with a wafer potential as measured by a wired wafer. For wafer potential as measured by a wired wafer, a probe was placed in contact with the top or upper surface of a wafer. For both measurements, the signals derived from the probes were filtered to remove RF components. After applying the RF filter, the signals contained only the DC voltage.

In graph500, the x-axis is time (in seconds), whereas the y-axis is measured voltage (in volts). A dotted line502corresponds to the plasma potential as measured by probe202, whereas a dashed line504corresponds to the wafer potential as measured by a wired wafer.

As illustrated in graph500, dotted line502and dashed line504are very similar. Based on the similar behavior of dotted line502and dashed line504, it is determined the measurement of the plasma potential by probe202is an accurate representation of the wafer potential.

FIG. 6is a graph600comparing plasma potential as measured by probe202with the potential of wafer102as measured using HER128in accordance with an aspect of the present invention.

In graph600, the x-axis is time (in seconds), whereas the y-axis is measured voltage (in volts). A dotted line602corresponds to the plasma potential as measured by probe202, whereas a dashed line604corresponds to the potential of wafer102as measured using HER128in accordance with an aspect of the present invention.

As illustrated in graph600, dotted line602and dashed line604are very similar. Based on the similarity of dotted line602and dashed line604, it is determined the measurement of the potential of wafer102by HER128accurately represents the plasma potential as measured by probe202.

As discussed above with reference toFIG. 5, the measurement of the plasma potential by probe202is an accurate representation of the wafer potential. Further, as discussed above with reference toFIG. 6, the measurement of the potential of wafer102by HER128is an accurate representation of the plasma potential as measured by probe202. Therefore, the measurement of the potential of wafer102by HER128is an accurate representation of the wafer potential.

Returning toFIG. 4, since it has been determined that the potential of wafer102as measured by HER128is an accurate representation of the wafer potential, signal detector400determines the potential of wafer102, by measuring the potential of HER128.

Example embodiments of signal detector400will now be described with reference toFIGS. 7-10B.

FIG. 7illustrates an example embodiment of signal detector400in accordance with an aspect of the present invention.

In this example embodiment, signal detector400includes an electrical contact700and is disposed within a cavity702. An upper end of electrical contact700is disposed at hole410, such that the upper end of electrical contact700touches and electrically connects with bottom surface404of HER128. The potential of HER128is conveyed to signal detector400by electrical signal308.

FIG. 8illustrates another example embodiment of signal detector400in accordance with an aspect of the present invention.

In this example embodiment, signal detector400includes electrical contact700, a resistor800and an electrical contact802, all disposed within a cavity804. The lower end of electrical contact700is electrically connected to resistor800. Resistor800is additionally electrically connected to an upper end of electrical contact802. The potential of HER128is conveyed to signal detector400by electrical signal308.

With further reference toFIG. 3, resistor800impedes arcing that may result from an impedance mismatch between impedance matching circuit116and wafer processing chamber122. Particularly during system switching, it is possible to experience spurious impedance differentials between impedance matching circuit116and wafer processing chamber122. These periods of impedance mismatch can induce undesirable electrical arcing within wafer processing chamber122. Resistor800reduces the magnitude of impedance differentials between impedance matching circuit116and wafer processing chamber122.

FIG. 9illustrates another example embodiment of signal detector400in accordance with an aspect of the present invention.

In this example embodiment, signal detector400includes electrical contact700, resistor800, electrical contact802and a dielectric spacer900, all disposed within a cavity902. Dielectric spacer900is disposed adjacent to resistor800. Dielectric spacer900acts as a heat sink to draw heat from resistor800. Dielectric spacer900should have a low value of dielectric constant to provide a high impedance, as compared to resistor800. Such a comparatively high impedance would minimize transmission of electrical signals through dielectric spacer900and would maximize transmission of electrical signals through resistor800. A non-limiting example of a material exhibiting both a low value of dielectric constant and excellent thermal conductivity is quartz.

FIGS. 10A and 10Billustrate another example embodiment of signal detector400in accordance with an aspect of the present invention. In particular,FIG. 10Aillustrates a first state of signal detector400, when HER128is disposed on ceramic coupling ring314, whereasFIG. 10billustrates a second state of signal detector400, when HER128is separated from ceramic coupling ring314.

In this example embodiment, signal detector400includes a spring-loaded contact1000, resistor800, electrical contact802and dielectric spacer900, all disposed within a cavity1002. An upper end of spring-loaded contact1000is disposed at hole402, such that the upper end of spring-loaded contact1000touches and electrically connects with bottom surface404of HER128. A lower end of spring-loaded contact1000is electrically connected to resistor800. Resistor800is additionally electrically connected to an upper end of electrical contact802. The potential of HER128is conveyed to signal detector400by electrical signal308.

FIG. 10Aillustrates the operation of signal detector400during an operation time period topof wafer processing system300. During operation time period top, bottom surface404of HER128rests on top surface406of ceramic coupling ring314, forcing spring-loaded contact1000to contract. Accordingly, signal detector400is able to detect a signal from HER128.

HER128may have an operation lifetime, wherein HER128is likely to function within predetermined acceptable threshold parameters. However after the operation lifetime, HER128may not function within the predetermined acceptable threshold parameters as a result of wear and tear from exposure to plasma within wafer processing system300. Accordingly, after the operation lifetime, HER128may need to be removed and replaced with a new HER. In the event that HER128needs to be removed, HER128may be lifted off of ceramic coupling ring314. This will be described in greater detail below with reference toFIG. 10B.

FIG. 10Billustrates the disposition of signal detector400during a non-operation time period tnonopof wafer processing system300. During non-operation time period tnonop, wafer processing system300is turned off and signal detector400does not detect a signal from HER128. HER128may be lifted off of ceramic coupling ring314, wherein bottom surface404of HER128may be separated from top surface406of ceramic coupling ring314, thus disconnecting spring-loaded contact1000from HER128.

As illustrated inFIG. 10B, when HER128is separated from ceramic coupling ring314, HER128will continued to be lifted away from ceramic coupling ring314such that a space1004will continue to grow and spring-loaded contact1000will extend through hole402. At some time, spring-loaded contact1000will stop extending through hole410. After this time, as HER128continues to be lifted away from ceramic coupling ring314and space1004continues to grow, spring-loaded contact1000will be disconnected from HER128. In this state, spring-loaded contact1000does not make contact with HER128and does not provide an electrical path for the voltage potential from HER128.

Once HER128is removed, a new HER may replace HER128. At first, spring-loaded contact1000will not make contact with the new HER and will not provide an electrical path for the voltage potential from the new HER. As the new HER continues to be moved toward ceramic coupling ring314and space1004continues to decrease, spring-loaded contact1000will eventually contact the new HER. The new HER will continued to be moved toward ceramic coupling ring314such that space1004will continue to decrease and spring-loaded contact1000will compress down into hole410. The new HER will finally be disposed onto ceramic coupling ring314, such that the bottom surface of the new HER will rest on top surface406of ceramic coupling ring314. In this situation, the bottom surface of the new HER will remain in contact with spring-loaded contact1000. Wafer processing system300may then be turned on and signal detector400may then detect a signal from the newly-installed HER.

The benefit of the example embodiment illustrated inFIGS. 10A and 10B, is that the length of spring-loaded contact1000need not be as precise as the length of the contacts discussed above with reference toFIGS. 7-9. In particular, the contacts discussed above with reference toFIGS. 7-9should be sufficiently long to contact bottom surface404of HER128through hole410. However, the contacts discussed above with reference toFIGS. 7-9should not be so long as to damage bottom surface404of HER128. However, in the case of spring-loaded contact1000, the length of spring-loaded contact1000may extend and contract to maintain contact with bottom surface404of HER128without damaging bottom surface404of HER128.

In the example embodiments discuss above, a parameter of the HER is detected by contacting a bottom surface of the HER by way of a detector disposed within a ceramic coupling ring. In other embodiments, the detector is not disposed within the ceramic coupling ring, but is arranged to detect a parameter of the HER without being exposed to the plasma forming volume. A non-limiting example of such an embodiment includes the embodiment wherein the detector is disposed within the HER and is not exposed to the plasma forming volume.

In accordance with an aspect of the present invention, a HER is used as a portion of a detecting system to detect the wafer potential in a wafer processing system. Accordingly, in accordance with an aspect of the present invention, plasma-exposed probes are no longer needed, thus reducing operating and maintenance costs.