Systems and methods for multi-dimensional data processor operational marginalization

Systems, methods, devices, circuits for data processing, and more particularly to data processing including operational marginalization capability.

FIELD OF THE INVENTION

Embodiments are related to systems and methods for data processing, and more particularly to systems and methods for controlled degradation of a data processing system.

BACKGROUND

Various data transfer systems have been developed including storage systems, cellular telephone systems, radio transmission systems. In each of the systems data is transferred from a sender to a receiver via some medium. For example, in a storage system, data is sent from a sender (i.e., a write function) to a receiver (i.e., a read function) via a storage medium. The data processing includes application of various data processing algorithms to recover originally written data. Such processing results in a very small number of errors that in some cases are due to corruption of the originally received data. Such a level of errors make it difficult to make adjustments to either correct for the type of errors or make it difficult to characterize the quality of a device.

Hence, for at least the aforementioned reasons, there exists a need in the art for advanced systems and methods for data processing.

SUMMARY

Embodiments are related to systems and methods for data processing, and more particularly to systems and methods for controlled degradation of a data processing system.

Various embodiments of the present invention provide data processing systems that include: a first analog to digital converter circuit operable to convert a first input into a first series of digital samples; a second analog to digital converter circuit operable to convert a second input into a second series of digital samples; a multi-dimensional system marginalization circuit operable to apply a marginalization algorithm to a combination of the first series of digital samples and the second series of digital samples to yield a first marginalized input corresponding to the first series of digital samples and a second marginalized input corresponding to the second series of digital samples; and a processing circuit operable to apply a multi-dimensional data processing algorithm to a combination of the first marginalized input and the second marginalized input to yield a data output.

This summary provides only a general outline of some embodiments of the invention. The phrases “in one embodiment,” “according to one embodiment,” “in various embodiments,” “in one or more embodiments”, “in particular embodiments” and the like generally mean the particular feature, structure, or characteristic following the phrase is included in at least one embodiment of the present invention, and may be included in more than one embodiment of the present invention. Importantly, such phases do not necessarily refer to the same embodiment. Many other embodiments of the invention will become more fully apparent from the following detailed description, the appended claims and the accompanying drawings.

DETAILED DESCRIPTION OF SOME EMBODIMENTS

Embodiments are related to systems and methods for data processing, and more particularly to systems and methods for controlled degradation of a data processing system.

Various embodiments of the present invention provide data processing systems that include: a first analog to digital converter circuit operable to convert a first input into a first series of digital samples; a second analog to digital converter circuit operable to convert a second input into a second series of digital samples; a multi-dimensional system marginalization circuit operable to apply a marginalization algorithm to a combination of the first series of digital samples and the second series of digital samples to yield a first marginalized input corresponding to the first series of digital samples and a second marginalized input corresponding to the second series of digital samples; and a processing circuit operable to apply a multi-dimensional data processing algorithm to a combination of the first marginalized input and the second marginalized input to yield a data output.

In some instances of the aforementioned embodiments, the multi-dimensional system marginalization circuit includes: a first loop detector circuit operable to apply a loop detection algorithm to a first loop input derived from the first series of digital samples to yield a first loop output; a second loop detector circuit operable to apply the loop detection algorithm to a second loop input derived from the second series of digital samples to yield a first loop output; and a multi-dimensional signal marginalization circuit operable to marginalize the first loop input based upon a combination of the first loop output, the first loop input, and the second loop input to yield a first marginalized output; and to marginalize the second loop input based upon a combination of the second loop output, the first loop input and the second loop input to yield a second marginalized output.

In some cases, the multi-dimensional system marginalization circuit further includes a multi-dimensional joint equalizer circuit operable to apply a multi-dimensional equalization algorithm to a combination of the first series of digital samples and the second series of digital samples to yield the first loop input and the second loop input to yield a first equalized output corresponding to the first series of digital samples and a second equalized output corresponding to the second series of digital samples. In some such cases, the multi-dimensional signal marginalization circuit includes a vector by array multiplication circuit operable to multiply an array of errors derived from a combination of the first loop output, the second loop output, the first equalized output and the second equalized output by a marginalization matrix to yield a first marginalized error corresponding to the first series of digital samples and a second marginalized error corresponding to the second series of digital samples; a first summation circuit operable to sum the first equalized output with the first marginalized error to yield the first marginalized input; and a second summation circuit operable to sum the second equalized output with the second marginalized error to yield the second marginalized input. In one or more cases, the aforementioned marginalization matrix is user programmable. In various cases, the marginalization matrix is a matrix of values each less than unity.

In one or more cases, the multi-dimensional system marginalization circuit includes: a first loop detector circuit operable to apply a loop detection algorithm to the first series of digital samples to yield a first loop output; a first one dimensional marginalization circuit operable to modify the first series of digital samples to yield a first marginalized series of digital samples based at least in part on the first series of digital samples and a first marginalization value; a second loop detector circuit operable to apply the loop detection algorithm to the second series of digital samples to yield a second loop output; and a second one dimensional marginalization circuit operable to modify the second series of digital samples to yield a second marginalized series of digital samples based at least in part on the second series of digital samples and a second marginalization value. In some such cases, the first marginalization value is user programmable. In various of such cases, the first marginalization value is less than unity. In one or more cases, the multi-dimensional system marginalization circuit further includes a multi-dimensional joint equalizer circuit operable to apply a multi-dimensional equalization algorithm to a combination of the first marginalized series of digital samples and the second marginalized series of digital samples to yield a first equalized output corresponding to the first series of digital samples and a second equalized output corresponding to the second series of digital samples. In particular cases, the first one dimensional marginalization circuit includes: a first summation circuit operable to subtract an ideal value derived from the first series of digital samples to yield an error value; a multiplication circuit operable to multiply the error value by the first marginalization value to yield a product; and a second summation circuit operable to sum the product with the first series of digital samples to yield the first marginalized series of digital samples.

Other embodiments of the present invention provide methods for data processing that include: receiving a first input derived from a first read head disposed in relation to a storage medium; receiving a second input derived from a second read head disposed in relation to the storage medium; generating a first noise component based at least in part on a combination of data derived from both the first input and second input; generating a second noise component based at least in part on the combination of data derived from both the first input and second input; multiplying a vector of the first noise component and the second noise component by a marginalization matrix to yield a first marginalized noise component corresponding to the first input and a second marginalized noise component corresponding to the second input; summing the first input with the first marginalized noise component to yield a first marginalized output; and summing the second input with the second marginalized noise component to yield a second marginalized output.

Turning toFIG. 1a, a storage system100including a read channel circuit110having multi-dimensional noise injection circuitry is shown in accordance with various embodiments of the present invention. Storage system100may be, for example, a hard disk drive. Storage system100also includes a preamplifier170, an interface controller120, a hard disk controller166, a motor controller168, a spindle motor172, a disk platter178, and a read/write head176. Interface controller120controls addressing and timing of data to/from disk platter178. The data on disk platter178consists of groups of magnetic signals that may be detected by read/write head assembly176when the assembly is properly positioned over disk platter178. In one embodiment, disk platter178includes magnetic signals recorded in accordance with either a longitudinal or a perpendicular recording scheme.

In a typical read operation, read/write head assembly176is accurately positioned by motor controller168over multiple data tracks on disk platter178. Read/write head assembly176includes two or more read heads capable of sensing data from two or more tracks at the same time. An example151of read/write assembly176including three read heads163,165,167aligned over three consecutive tracks153,155,157of a disk platter is shown inFIG. 1b. Each of the three read heads senses data from the corresponding track. Referring again toFIG. 1a, motor controller168both positions read/write head assembly176in relation to disk platter178and drives spindle motor172by moving read/write head assembly to the proper data track on disk platter178under the direction of hard disk controller166. Spindle motor172spins disk platter178at a determined spin rate (RPMs). Once read/write head assembly176is positioned adjacent the proper data tracks, magnetic signals representing data on the tracks of disk platter178are sensed by read/write head assembly176as disk platter178is rotated by spindle motor172. The multiple streams of sensed magnetic signals are provided as a continuous, minute analog signals representative of the magnetic data on the respective tracks of disk platter178. These streams of minute analog signals is transferred from read/write head assembly176to read channel circuit110via preamplifier170. Preamplifier170is operable to amplify the minute analog signals accessed from disk platter178. In turn, read channel circuit110decodes and digitizes the received analog signals to recreate the information originally written to disk platter178. This data is provided as read data103to a receiving circuit. A write operation is substantially the opposite of the preceding read operation with write data101being provided to read channel circuit110. This data is then encoded and written to disk platter178.

As part of a device characterization process, read channel circuit110selects a test control causing a noise component to be added to data being accessed from disk platter178. The noise being added is designed to raise a minimal error rate generally yielded by read channel circuit110to an error rate that can meaningfully characterize storage system100. The noise being added is generated based upon data being accessed from disk platter178and is thus more representative of actual system operation than other types of noise that may be added. In some cases, the read channel circuit may include circuitry similar to that discussed in relation toFIGS. 3a-3b,FIGS. 4a-4band/orFIGS. 6a-6bas are described below to perform multi-dimensional marginalization; and/or may operate similar to the methods discussed below in relation toFIGS. 2a-2band/or5a-5b.

It should be noted that storage system100may be integrated into a larger storage system such as, for example, a RAID (redundant array of inexpensive disks or redundant array of independent disks) based storage system. Such a RAID storage system increases stability and reliability through redundancy, combining multiple disks as a logical unit. Data may be spread across a number of disks included in the RAID storage system according to a variety of algorithms and accessed by an operating system as if it were a single disk. For example, data may be mirrored to multiple disks in the RAID storage system, or may be sliced and distributed across multiple disks in a number of techniques. If a small number of disks in the RAID storage system fail or become unavailable, error correction techniques may be used to recreate the missing data based on the remaining portions of the data from the other disks in the RAID storage system. The disks in the RAID storage system may be, but are not limited to, individual storage systems such as storage system100, and may be located in close proximity to each other or distributed more widely for increased security. In a write operation, write data is provided to a controller, which stores the write data across the disks, for example by mirroring or by striping the write data. In a read operation, the controller retrieves the data from the disks. The controller then yields the resulting read data as if the RAID storage system were a single disk.

A data decoder circuit used in relation to read channel circuit110may be, but is not limited to, a low density parity check (LDPC) decoder circuit as are known in the art. Such low density parity check technology is applicable to transmission of information over virtually any channel or storage of information on virtually any media. Transmission applications include, but are not limited to, optical fiber, radio frequency channels, wired or wireless local area networks, digital subscriber line technologies, wireless cellular, Ethernet over any medium such as copper or optical fiber, cable channels such as cable television, and Earth-satellite communications. Storage applications include, but are not limited to, hard disk drives, compact disks, digital video disks, magnetic tapes and memory devices such as DRAM, NAND flash, NOR flash, other non-volatile memories and solid state drives.

In addition, it should be noted that storage system100may be modified to include solid state memory that is used to store data in addition to the storage offered by disk platter178. This solid state memory may be used in parallel to disk platter178to provide additional storage. In such a case, the solid state memory receives and provides information directly to read channel circuit110. Alternatively, the solid state memory may be used as a cache where it offers faster access time than that offered by disk platted178. In such a case, the solid state memory may be disposed between interface controller120and read channel circuit110where it operates as a pass through to disk platter178when requested data is not available in the solid state memory or when the solid state memory does not have sufficient storage to hold a newly written data set. Based upon the disclosure provided herein, one of ordinary skill in the art will recognize a variety of storage systems including both disk platter178and a solid state memory.

Turning toFIGS. 2a-2bare flow diagrams200,299showing a method for data processing relying on multi-dimensional noise injection in accordance with some embodiments of the present invention. Following flow diagram200ofFIG. 2a, multiple analog inputs are received from respective read heads (block205). The analog inputs may be derived from, for example, a storage medium. Based upon the disclosure provided herein, one of ordinary skill in the art will recognize a variety of sources of the analog inputs. Each of the analog inputs is converted to a respective series of digital samples (block210). This conversion may be done using analog to digital converter circuits or systems as are known in the art. Of note, any circuit known in the art that is capable of converting an analog signal into a series of digital samples representing the received analog signal may be used. The resulting sets of digital samples from the analog to digital converter circuits are provided to a multi-dimensional equalization circuit.

The multi-dimensional equalization circuit applies a multi-dimensional equalization to each of the series of digital samples incorporating information from the other series of digital samples to yield respective equalized outputs (block215). In some embodiments of the present invention, the equalization is done using a multi-dimensional digital finite impulse response circuit as are known in the art. Based upon the disclosure provided herein, one of ordinary skill in the art will recognize a variety of equalizer circuits that may be used in place of such a digital finite impulse response circuit to perform equalization in accordance with different embodiments of the present invention. The following equation represents the array of equalized outputs (y(k,n)):
y(k,n)=w(k)T·x(n),
where k indicates a particular set of the series of digital samples (i.e., k indicates a read head), and n indicates a particular element in the kthseries of digital samples. Thus, where a two-dimensional system is implemented that includes two read heads, the value of k is one or two. The term w(k)Trepresents the multi-dimensional equalization, and x(n) represents the digital samples at the output of the analog to digital converter circuit. In particular,
w(k)T=[w(k,1)T,w(k,2)T, . . . , w(k,N)T]T,
is NP×1 vector of equalizer for the kthtrack of a storage medium, where w(k,j) is Px1 vector of the equalizer filter for the data from the jthread head. Further, the following equation represents the value of x(n):
x(n)T=[x(n,1)T,x(n,2)T, . . . , x(n,N)T]T,
where x(n,j) is Px1 vector of the digital samples from the analog to digital converter circuit for the jthread head.

Where the multi-dimensional equalizer is a two dimensional equalizer, it is designed to use a two-dimensional target. In this situation, the equalized output is represented as follows:
y(k,n)=g(k)T·a(n),
where:
g(k)T=[g(k,1)T,g(k,2)T, . . . , g(k,N)T]T,
is NLx1 vector of a two dimensional target for the kthtrack of a storage medium, and a(n):
a(n)T=[a(n,1)T,a(n,2)T, . . . , a(n,N)T]T,
where NLx1 vector of the hard decision data (output of the loop detector circuits). L is the length of the target.

A loop detection algorithm is applied individually to each of the equalized outputs to yield respective loop detector outputs (block260). A loop detector applying the loop detection algorithm that generates decisions on data bits. The loop control circuits in the channel use these decisions to generate feedback for driving the loops in the correct direction. The loop detection algorithm may be applied by any circuit known in the art that applies some type of algorithm designed to return a representation of the data from which the analog input was derived. In one particular embodiment of the present invention, the loop detection algorithm is operable to determine bit decisions used to aid in timing feedback and other operations designed to align the sampling related to the analog to digital conversion, and/or to adjust a gain applied by an analog front end circuit. Based upon the disclosure provided herein, one of ordinary skill in the art will recognize a variety of loop detection algorithms capable of providing a representation of the data from which the analog input was derived that may be used in relation to different embodiments of the present invention.

A partial response target filtering is applied to each loop detector output to yield respective target filtered outputs (block265). The partial response target filtering may be done by any circuit known in the art that is capable of applying target based filtering to an input signal to yield an output conformed to a target. The resulting target filtered output is an ideal approximation of the equalized output.

It is determined whether a test control is asserted (block222). Where the test control is asserted (block222), each of the target filtered outputs is subtracted from a respective one of the equalized outputs to yield respective errors as an array of errors (block270). The errors may be calculated in accordance with the following equation:
e(k,n)=y(k,n)−yideal(k,n),
where e(k, n) is the error, y(k, n) is the equalized output, and yideal(k, n) is the target filtered output. The array of errors is multiplied by a marginalization matrix to yield an array of marginalized errors (block275). The array of marginalized errors may be calculated in accordance with the following equation:
e′(k,n)=A·e(k,n),
where A is the marginalization matrix and e′(k,n) is the array of marginalized errors. The following is an example of a two-dimensional marginalization matrix:

A={α1,1,α1,2α2,1,α2,2}.
In the simple case where interference in the data from the heads is not addressed, the aforementioned two-dimensional marginalization matrix can be reduced to:

A={α1,1,00α2,2}.
The array of marginalized errors includes a marginalization error corresponding to each of the read heads from which the analog data was originally received. These marginalized errors are added to the corresponding equalized output to yield respective noise marginalized outputs (block280). The noise marginalized outputs y′(k,n) may be calculated in accordance with the following equation:
y′(k,n)=y(k,n)+e′(k,n).
These respective noise marginalized outputs is used to replace the respective equalized outputs.

Whether or not the test control is asserted (block222), the equalized outputs (modified or unmodified) are buffered as an array of equalized outputs (block220). The array of equalized outputs includes one equalized output corresponding to each of the multiple read heads. It is determined whether a data detector circuit is available to process the buffered equalized output (block225). Where a data detector circuit is available to process a data set (block225), the next available array of equalized outputs from the buffer is selected for processing (block230). A multi-dimensional data detection algorithm is then applied to the selected array of equalized outputs to yield a detected output (block237). The data detection algorithm may be, for example, a Viterbi algorithm data detection or a maximum a posteriori data detection algorithm. The detected output (or a derivative thereof) is then stored to a central memory (block245).

Turning toFIG. 2band following flow diagram299, it is determined whether a data decoder circuit is available (block201) in parallel to the previously described data detection process ofFIG. 2a. The data decoder circuit may be, for example, a low density parity check data decoder circuit as are known in the art. Where the data decoder circuit is available (block201) the next derivative of a detected output is selected from the central memory (block206). The derivative of the detected output may be, for example, an interleaved (shuffled) version of a detected output from the data detector circuit. A first local iteration of a data decoding algorithm is applied by the data decoder circuit to the selected detected output to yield a decoded output (block211). It is then determined whether the decoded output converged (e.g., resulted in the originally written data as indicated by the lack of remaining unsatisfied checks) (block216).

Where the decoded output converged (block216), it is provided as a decoded output codeword to a hard decision output buffer (e.g., a re-ordering buffer) (block221). It is determined whether the received output codeword is either sequential to a previously reported output codeword in which case reporting the currently received output codeword immediately would be in order, or that the currently received output codeword completes an ordered set of a number of codewords in which case reporting the completed, ordered set of codewords would be in order (block256). Where the currently received output codeword is either sequential to a previously reported codeword or completes an ordered set of codewords (block256), the currently received output codeword and, where applicable, other codewords forming an in order sequence of codewords are provided to a recipient as an output (block261).

Alternatively, where the decoded output failed to converge (e.g., errors remain) (block216), it is determined whether the number of local iterations already applied equals the maximum number of local iterations (block226). In some cases, a default seven local iterations are allowed per each global iteration. Based upon the disclosure provided herein, one of ordinary skill in the art will recognize another default number of local iterations that may be used in relation to different embodiments of the present invention. Where another local iteration is allowed (block226), the multi-dimensional data decoding algorithm is applied to the selected data set using the decoded output as a guide to update the decoded output (block231). The processes of blocks starting at block216are repeated for the next local iteration.

Alternatively, where all of the local iterations have occurred (block226), it is determined whether all of the global iterations have been applied to the currently processing data set (block236). Where the number of global iterations has not completed (block236), the decoded output is stored to the central queue memory circuit to await the next global iteration (block241). Alternatively, where the number of global iterations has completed (block236), an error is indicated and the data set is identified as non-converging (block246).

Turning toFIG. 3a, a data processing circuit300is shown that includes a multi-dimensional signal marginalization circuit325in accordance with some embodiments of the present invention. Data processing circuit300includes a number of analog front end circuits310(310a,310b,310c) that receive respective ones of analog inputs308(308a,308b,308c) from respective read heads (not shown). Each of analog front end circuits310processes a respective one of the analog signals308and provides a processed analog signal312(one of312a,312b,312c) to a respective analog to digital converter circuit315(one of315a,315b,315c). Each of analog front end circuits310may include, but is not limited to, an analog filter and an amplifier circuit as are known in the art. Based upon the disclosure provided herein, one of ordinary skill in the art will recognize a variety of circuitry that may be included as part of analog front end circuit310. In some cases, analog input signal308is derived from a read/write head assembly (not shown) that is disposed in relation to a storage medium (not shown). Based upon the disclosure provided herein, one of ordinary skill in the art will recognize a variety of sources from which the analog input signals308may be derived.

Each of the analog to digital converter circuits315converts a respective one of the processed analog signals312into a respective corresponding series of digital samples317(one of317a,317b,317c). Each of the analog to digital converter circuits315may be any circuit known in the art that is capable of producing digital samples corresponding to an analog input signal. Based upon the disclosure provided herein, one of ordinary skill in the art will recognize a variety of analog to digital converter circuits that may be used in relation to different embodiments of the present invention. Each of the series of digital samples317are provided to a multi-dimensional joint equalizer circuit320. Multi-dimensional joint equalizer circuit320applies a multi-dimensional equalization algorithm to the sets of digital samples317a,317b,317cto yield equalized outputs322a,322b,322ceach corresponding to one of analog inputs308a,308b,308c. In some embodiments of the present invention, multi-dimensional joint equalizer circuit equalizer circuit320is a multi-dimensional digital finite impulse response filter circuit as are known in the art.

Equalized output322ais provided to a loop detector circuit394a, equalized output322bis provided to a loop detector circuit394b, and equalized output322cis provided to a loop detector circuit394c. Each of loop detector circuits394may be any circuit known in the art that applies some type of algorithm designed to return a representation of the data from which a corresponding input signal308was derived. In one particular embodiment of the present invention, each of the decisions from the loop detector circuits394may be used to determine timing feedback and other operations designed to align the sampling of the corresponding analog to digital converter circuit315(e.g., output323aof loop detector circuit394aprovided to analog to digital converter circuit315a) with the received data set, and/or to adjust a gain applied by the corresponding analog front end circuit310(e.g., output323aof loop detector circuit394aprovided to analog to analog front end circuit310a). Based upon the disclosure provided herein, one of ordinary skill in the art will recognize a variety of circuits capable of providing a representation of the data from which analog signal308was derived that may be used in relation to different embodiments of the present invention. Each of the loop detector circuits394provides a respective ideal output323that corresponds to an expected value based upon filtering.

An array of equalized outputs consisting of equalized outputs322a,322b,322cand an array of ideal outputs323a,323b,323care provided to multi-dimensional signal marginalization circuit325. Multi-dimensional signal marginalization circuit325is operable to inject a portion of noise calculated based upon the noise derived from equalized outputs322a,322b,322c. Turning toFIG. 3b, one implementation of multi-dimensional signal marginalization circuit325is shown in accordance with various embodiments of the present invention. As shown in the example implementation ofFIG. 3b, multi-dimensional signal marginalization circuit325includes a multi-dimensional convolution filter circuit380. Multi-dimensional convolution filter circuit380applies target filtering on ideal outputs323a,323b,323cbased upon a multi-dimensional partial response target381. Multi-dimensional convolution filter circuit380may be any multi-dimensional target filter as is known in the art. The result of the target filtering are filtered outputs382a,382b,382cthat correspond to respective ones of ideal outputs323a,323b,323c. Filtered outputs382a,382b,382care provided to respective summation circuits384a,384b,384cwhere they are subtracted from equalized outputs322a,322b,322cto yield error outputs386a,386b,386cin accordance with the following equation:
e(k,n)=y(k,n)−yideal(k,n),
where e(k,n) indicates the error outputs386a,386b,386c; y(k,n) indicates the equalized outputs322a,322b,322c; and yideal(k,n) indicates the filtered outputs382a,382b,382c.

The vector of error outputs386a,386b,386care provided to a vector by array multiplier circuit399where the vector is multiplied by a marginalization matrix393to yield a vector of marginalized errors397a,397b,397c. Marginalized errors397a,397b,397cmay be represented by the following equation:
e′(k,n)=A·e(k,n)
where e′(k,n) indicates the vector of marginalized errors, and A indicates the marginalization matrix.

A group of selector circuits332a,332b,332cselects either one of the marginalized errors397a,397b,397cor a zero value as a corresponding offset value334a,334b,334cbased upon an assertion level of a test control395. Where test control395indicates a test scenario where system marginalization is desired, selector circuit332aprovides marginalized error397aas offset value334a, selector circuit332bprovides marginalized error397bas offset value334b, and selector circuit332cprovides marginalized error397cas offset value334c. Alternatively, where normal operation is to be performed, test control395is de-asserted causing selector circuit332ato provide a zero value as offset value334a, selector circuit332bto provide a zero value as offset value334b, and selector circuit332cto provide a zero value as offset value334c.

Offset values334a,334b,334care provided to respective summation circuits385a,385b,385cwhere they are added to respective equalized outputs322a,322b,322cto yield noise injected outputs391a,391b,391c. Thus, where test control395is asserted, equalized outputs322a,322b,322care modified by injecting the marginalized error values to cause a corresponding operational marginalization of the system in which data processing circuit300is implemented. Noise injected outputs391a,391b,391care provided to multi-dimensional back end processing circuitry that is explained in relation toFIG. 3a.

Referring again toFIG. 3a, noise injected outputs391a,391b,391care provided to a multi-dimensional sample buffer circuit375where they are stored. In addition, noise injected outputs391a,391b,391care provided directly to a multi-dimensional data detector circuit326as are known in the art. Sample buffer circuit375includes sufficient memory to maintain one or more codewords until processing of that codeword is completed through multi-dimensional data detector circuit326and a multi-dimensional data decoder circuit350including, where warranted, multiple “global iterations” defined as passes through both multi-dimensional data detector circuit326and multi-dimensional data decoder circuit350and/or “local iterations” defined as passes through multi-dimensional data decoder circuit350during a given global iteration. Multi-dimensional sample buffer circuit375stores the received data as buffered data377.

Multi-dimensional data detector circuit326is a data detector circuit capable of producing a detected output327by applying a data detection algorithm to a vector of data inputs derived from different heads. As some examples, the data detection algorithm may be but is not limited to, a Viterbi algorithm detection algorithm or a maximum a posteriori detection algorithm as are known in the art. Based upon the disclosure provided herein, one of ordinary skill in the art will recognize a variety of data detection algorithms that may be used in relation to different embodiments of the present invention. Multi-dimensional data detector circuit326may provide both hard decisions and soft decisions. The terms “hard decisions” and “soft decisions” are used in their broadest sense. In particular, “hard decisions” are outputs indicating an expected original input value (e.g., a binary ‘1’ or ‘0’, or a non-binary digital value), and the “soft decisions” indicate a likelihood that corresponding hard decisions are correct. Based upon the disclosure provided herein, one of ordinary skill in the art will recognize a variety of hard decisions and soft decisions that may be used in relation to different embodiments of the present invention.

Detected output327is provided to a multi-dimensional central queue memory circuit360that operates to buffer data passed between multi-dimensional data detector circuit326and multi-dimensional data decoder circuit350. When multi-dimensional data decoder circuit350is available, multi-dimensional data decoder circuit350receives detected output327from multi-dimensional central queue memory360as a decoder input356. Multi-dimensional data decoder circuit350applies a multi-dimensional data decoding algorithm to decoder input356in an attempt to recover originally written data. The result of the data decoding algorithm is provided as a decoded output354. Similar to detected output327, decoded output354may include both hard decisions and soft decisions. For example, data decoder circuit350may be any data decoder circuit known in the art that is capable of applying a decoding algorithm to a received input. Multi-dimensional data decoder circuit350may be, but is not limited to, a low density parity check decoder circuit or a Reed Solomon decoder circuit as are known in the art. Based upon the disclosure provided herein, one of ordinary skill in the art will recognize a variety of data decoder circuits that may be used in relation to different embodiments of the present invention. Where the original data is recovered (i.e., the data decoding algorithm converges) or a timeout condition occurs, data decoder circuit350provides the result of the data decoding algorithm as a data output374. Data output374is provided to a hard decision output circuit396where the data is reordered before providing a series of ordered data sets as a data output398.

One or more iterations through the combination of multi-dimensional data detector circuit326and multi-dimensional data decoder circuit350may be made in an effort to converge on the originally written data set. As mentioned above, processing through both the data detector circuit and the data decoder circuit is referred to as a “global iteration”. For the first global iteration, multi-dimensional data detector circuit326applies the data detection algorithm without guidance from a decoded output. For subsequent global iterations, multi-dimensional data detector circuit326applies the data detection algorithm to buffered data377as guided by decoded output354. Decoded output354is received from central queue memory360as a detector input329.

During each global iteration it is possible for data decoder circuit350to make one or more local iterations including application of the data decoding algorithm to decoder input356. For the first local iteration, multi-dimensional data decoder circuit350applies the data decoder algorithm without guidance from a decoded output352. For subsequent local iterations, multi-dimensional data decoder circuit350applies the data decoding algorithm to decoder input356as guided by a previous decoded output352. In some embodiments of the present invention, a default of ten local iterations is allowed for each global iteration.

Turning toFIG. 4a, a data processing circuit400is shown that includes a two-dimensional signal marginalization circuit425in accordance with some embodiments of the present invention. Data processing circuit400includes a number of analog front end circuits410(410a,410b) that receive respective ones of analog inputs408(408a,408b) from one of two respective read heads (not shown). Each of analog front end circuits410processes a respective one of the analog signals408and provides a processed analog signal412(one of412a,412b) to a respective analog to digital converter circuit415(one of415a,415b). Each of analog front end circuits410may include, but is not limited to, an analog filter and an amplifier circuit as are known in the art. Based upon the disclosure provided herein, one of ordinary skill in the art will recognize a variety of circuitry that may be included as part of analog front end circuit410. In some cases, analog input signal408is derived from a read/write head assembly (not shown) that is disposed in relation to a storage medium (not shown). Based upon the disclosure provided herein, one of ordinary skill in the art will recognize a variety of sources from which the analog input signals408may be derived.

Each of the analog to digital converter circuits415converts a respective one of the processed analog signals412into a respective corresponding series of digital samples417(one of417a,417b). Each of the analog to digital converter circuits415may be any circuit known in the art that is capable of producing digital samples corresponding to an analog input signal. Based upon the disclosure provided herein, one of ordinary skill in the art will recognize a variety of analog to digital converter circuits that may be used in relation to different embodiments of the present invention. Each of the series of digital samples417are provided to a two-dimensional joint equalizer circuit420. Two-dimensional joint equalizer circuit420applies a two-dimensional equalization algorithm to the sets of digital samples417a,417bto yield equalized outputs422a,422beach corresponding to one of analog inputs408a,408b. In some embodiments of the present invention, two-dimensional joint equalizer circuit equalizer circuit420is a two-dimensional digital finite impulse response filter circuit as are known in the art.

Equalized output422ais provided to a loop detector circuit494a, and equalized output422bis provided to a loop detector circuit494b. Each of loop detector circuits494may be any circuit known in the art that applies some type of algorithm designed to return a representation of the data from which a corresponding input signal408was derived. In one particular embodiment of the present invention, each of the decisions from the loop detector circuits494may be used to determine timing feedback and other operations designed to align the sampling of the corresponding analog to digital converter circuit415(e.g., output423aof loop detector circuit494aprovided to analog to digital converter circuit415a) with the received data set, and/or to adjust a gain applied by the corresponding analog front end circuit410(e.g., output423aof loop detector circuit494aprovided to analog to analog front end circuit410a). Based upon the disclosure provided herein, one of ordinary skill in the art will recognize a variety of circuits capable of providing a representation of the data from which analog signal408was derived that may be used in relation to different embodiments of the present invention. Each of the loop detector circuits494provides a respective ideal output423that corresponds to an expected value based upon filtering.

An array of equalized outputs consisting of equalized outputs422a,422band an array of ideal outputs423a,423bare provided to two-dimensional signal marginalization circuit425. Two-dimensional signal marginalization circuit425is operable to inject a portion of noise calculated based upon the noise derived from equalized outputs422a,422b. Turning toFIG. 4b, one implementation of two-dimensional signal marginalization circuit425is shown in accordance with various embodiments of the present invention. As shown in the example implementation ofFIG. 4b, two-dimensional signal marginalization circuit425includes a two-dimensional convolution filter circuit480. Two-dimensional convolution filter circuit480applies target filtering on ideal outputs423a,423bbased upon a two-dimensional partial response target481. Two-dimensional convolution filter circuit480may be any two-dimensional target filter as is known in the art. The result of the target filtering are filtered outputs482a,482bthat correspond to respective ones of ideal outputs423a,423b. Filtered outputs482a,482bare provided to respective summation circuits484a,484bwhere they are subtracted from equalized outputs422a,422bto yield error outputs486a,486bin accordance with the following equation:
e(k,n)=y(k,n)−yideal(k,n),
where e(k,n) indicates the error outputs486a,486b; y(k,n) indicates the equalized outputs422a,422b; and yideal(k,n) indicates the filtered outputs482a,482b.

The vector of error outputs486a,486bare provided to a vector by array multiplier circuit499where the vector is multiplied by a marginalization matrix493to yield a vector of marginalized errors497a,497b. Marginalized errors497a,497bmay be represented by the following equation:
e′(k,n)=A·e(k,n)
where e′(k,n) indicates the vector of marginalized errors, and A indicates the marginalization matrix.

A group of selector circuits432a,432bselects either one of the marginalized errors497a,497bor a zero value as a corresponding offset value434a,434bbased upon an assertion level of a test control495. Where test control495indicates a test scenario where system marginalization is desired, selector circuit432aprovides marginalized error497aas offset value434a, and selector circuit432bprovides marginalized error497bas offset value434b. Alternatively, where normal operation is to be performed, test control495is de-asserted causing selector circuit432ato provide a zero value as offset value434a, and selector circuit432bto provide a zero value as offset value434b.

Offset values434a,434bare provided to respective summation circuits485a,485bwhere they are added to respective equalized outputs422a,422bto yield noise injected outputs491a,491b. Thus, where test control495is asserted, equalized outputs422a,422bare modified by injecting the marginalized error values to cause a corresponding operational marginalization of the system in which data processing circuit400is implemented. Noise injected outputs491a,491bare provided to two-dimensional back end processing circuitry that is explained in relation toFIG. 4a.

Referring again toFIG. 4a, noise injected outputs491a,491bare provided to a two-dimensional sample buffer circuit475where they are stored. In addition, noise injected outputs491a,491bare provided directly to a two-dimensional data detector circuit426as are known in the art. Sample buffer circuit475includes sufficient memory to maintain one or more codewords until processing of that codeword is completed through two-dimensional data detector circuit426and a two-dimensional data decoder circuit450including, where warranted, twople “global iterations” defined as passes through both two-dimensional data detector circuit426and two-dimensional data decoder circuit450and/or “local iterations” defined as passes through two-dimensional data decoder circuit450during a given global iteration. Two-dimensional sample buffer circuit475stores the received data as buffered data477.

Two-dimensional data detector circuit426is a data detector circuit capable of producing a detected output427by applying a data detection algorithm to a vector of data inputs derived from different heads. As some examples, the data detection algorithm may be but is not limited to, a Viterbi algorithm detection algorithm or a maximum a posteriori detection algorithm as are known in the art. Based upon the disclosure provided herein, one of ordinary skill in the art will recognize a variety of data detection algorithms that may be used in relation to different embodiments of the present invention. Two-dimensional data detector circuit426may provide both hard decisions and soft decisions. The terms “hard decisions” and “soft decisions” are used in their broadest sense. In particular, “hard decisions” are outputs indicating an expected original input value (e.g., a binary ‘1’ or ‘0’, or a non-binary digital value), and the “soft decisions” indicate a likelihood that corresponding hard decisions are correct. Based upon the disclosure provided herein, one of ordinary skill in the art will recognize a variety of hard decisions and soft decisions that may be used in relation to different embodiments of the present invention.

Detected output427is provided to a two-dimensional central queue memory circuit460that operates to buffer data passed between two-dimensional data detector circuit426and two-dimensional data decoder circuit450. When two-dimensional data decoder circuit450is available, two-dimensional data decoder circuit450receives detected output427from two-dimensional central queue memory460as a decoder input456. Two-dimensional data decoder circuit450applies a two-dimensional data decoding algorithm to decoder input456in an attempt to recover originally written data. The result of the data decoding algorithm is provided as a decoded output454. Similar to detected output427, decoded output454may include both hard decisions and soft decisions. For example, data decoder circuit450may be any data decoder circuit known in the art that is capable of applying a decoding algorithm to a received input. Two-dimensional data decoder circuit450may be, but is not limited to, a low density parity check decoder circuit or a Reed Solomon decoder circuit as are known in the art. Based upon the disclosure provided herein, one of ordinary skill in the art will recognize a variety of data decoder circuits that may be used in relation to different embodiments of the present invention. Where the original data is recovered (i.e., the data decoding algorithm converges) or a timeout condition occurs, data decoder circuit450provides the result of the data decoding algorithm as a data output474. Data output474is provided to a hard decision output circuit496where the data is reordered before providing a series of ordered data sets as a data output498.

One or more iterations through the combination of two-dimensional data detector circuit426and two-dimensional data decoder circuit450may be made in an effort to converge on the originally written data set. As mentioned above, processing through both the data detector circuit and the data decoder circuit is referred to as a “global iteration”. For the first global iteration, two-dimensional data detector circuit426applies the data detection algorithm without guidance from a decoded output. For subsequent global iterations, two-dimensional data detector circuit426applies the data detection algorithm to buffered data477as guided by decoded output454. Decoded output454is received from central queue memory460as a detector input429.

During each global iteration it is possible for data decoder circuit450to make one or more local iterations including application of the data decoding algorithm to decoder input456. For the first local iteration, two-dimensional data decoder circuit450applies the data decoder algorithm without guidance from a decoded output452. For subsequent local iterations, two-dimensional data decoder circuit450applies the data decoding algorithm to decoder input456as guided by a previous decoded output452. In some embodiments of the present invention, a default of ten local iterations is allowed for each global iteration.

Turning toFIGS. 5a-5bare flow diagrams500,599showing a method for data processing relying on multi-dimensional noise injection in accordance with some embodiments of the present invention. Following flow diagram500ofFIG. 5a, multiple analog inputs are received from respective read heads (block505). The analog inputs may be derived from, for example, a storage medium. Based upon the disclosure provided herein, one of ordinary skill in the art will recognize a variety of sources of the analog inputs. Each of the analog inputs is converted to a respective series of digital samples (block510). This conversion may be done using analog to digital converter circuits or systems as are known in the art. Of note, any circuit known in the art that is capable of converting an analog signal into a series of digital samples representing the received analog signal may be used.

A loop detection algorithm is applied individually to each of the series of digital samples to yield respective loop outputs (block560). A loop detector applying the loop detection algorithm that generates decisions on data bits. The loop control circuits in the channel use these decisions to generate feedback for driving the loops in the correct direction. The loop detection algorithm may be applied by any circuit known in the art that applies some type of algorithm designed to return a representation of the data from which the analog input was derived. In one particular embodiment of the present invention, the loop detection algorithm is operable to determine bit decisions used to aid in timing feedback and other operations designed to align the sampling related to the analog to digital conversion, and/or to adjust a gain applied by an analog front end circuit. Based upon the disclosure provided herein, one of ordinary skill in the art will recognize a variety of loop detection algorithms capable of providing a representation of the data from which the analog input was derived that may be used in relation to different embodiments of the present invention.

A partial response target filtering is applied to each loop detector output to yield respective target filtered outputs (block565). The partial response target filtering may be done by any circuit known in the art that is capable of applying target based filtering to an input signal to yield an output conformed to a target. The resulting target filtered output is an ideal approximation of the respective series of digital samples.

It is determined whether a test control is asserted (block522). Where the test control is asserted (block522), each of the target filtered outputs is subtracted from a respective one of the series of digital samples to yield respective errors as an array of errors (block570). The errors may be calculated in accordance with the following equation:
e(k,n)=x(k,n)−xideal(k,n),
where e(k,n) is the error, x(k,n) is the digital samples, and xideal(k,n) is the target filtered output. Each element of the array of errors is multiplied by a respective scalar value (α1, α2, α3) to yield an array of marginalized errors (block575). The array of marginalized errors may be calculated in accordance with the following equation:
e′(k,n)={α1·e(1,n),α2·e(2,n),α3·e(3,n)},
where e′(k,n) is the array of marginalized errors.
The scalar values each correspond to a read head from which the analog data was originally received. These marginalized errors are added to the corresponding digital samples to yield respective modified series of digital samples (block580). The modified series of digital samples x′(k,n) may be calculated in accordance with the following equation:
x′(k,n)=x(k,n)+e′(k,n).
These respective noise marginalized outputs is used to replace the respective modified series of digital samples.

Alternatively, where the test control is not asserted (block522), each of the modified series of digital samples is set equal to the corresponding series of digital samples (block523). The modified series of digital samples are provided to a multi-dimensional equalization circuit. The multi-dimensional equalization circuit applies a multi-dimensional equalization to each of the modified series of digital samples incorporating information from the other modified series of digital samples to yield respective equalized outputs (block515). In some embodiments of the present invention, the equalization is done using a multi-dimensional digital finite impulse response circuit as are known in the art. Based upon the disclosure provided herein, one of ordinary skill in the art will recognize a variety of equalizer circuits that may be used in place of such a digital finite impulse response circuit to perform equalization in accordance with different embodiments of the present invention.

Whether or not the test control is asserted (block522), the equalized outputs (modified or unmodified) are buffered as an array of equalized outputs (block520). The array of equalized outputs includes one equalized output corresponding to each of the multiple read heads. It is determined whether a data detector circuit is available to process the buffered equalized output (block525). Where a data detector circuit is available to process a data set (block525), the next available array of equalized outputs from the buffer is selected for processing (block530). A multi-dimensional data detection algorithm is then applied to the selected array of equalized outputs to yield a detected output (block537). The data detection algorithm may be, for example, a Viterbi algorithm data detection or a maximum a posteriori data detection algorithm. The detected output (or a derivative thereof) is then stored to a central memory (block545).

Turning toFIG. 5band following flow diagram599, it is determined whether a data decoder circuit is available (block501) in parallel to the previously described data detection process ofFIG. 5a. The data decoder circuit may be, for example, a low density parity check data decoder circuit as are known in the art. Where the data decoder circuit is available (block501) the next derivative of a detected output is selected from the central memory (block506). The derivative of the detected output may be, for example, an interleaved (shuffled) version of a detected output from the data detector circuit. A first local iteration of a data decoding algorithm is applied by the data decoder circuit to the selected detected output to yield a decoded output (block511). It is then determined whether the decoded output converged (e.g., resulted in the originally written data as indicated by the lack of remaining unsatisfied checks) (block516).

Where the decoded output converged (block516), it is provided as a decoded output codeword to a hard decision output buffer (e.g., a re-ordering buffer) (block521). It is determined whether the received output codeword is either sequential to a previously reported output codeword in which case reporting the currently received output codeword immediately would be in order, or that the currently received output codeword completes an ordered set of a number of codewords in which case reporting the completed, ordered set of codewords would be in order (block556). Where the currently received output codeword is either sequential to a previously reported codeword or completes an ordered set of codewords (block556), the currently received output codeword and, where applicable, other codewords forming an in order sequence of codewords are provided to a recipient as an output (block561).

Alternatively, where the decoded output failed to converge (e.g., errors remain) (block516), it is determined whether the number of local iterations already applied equals the maximum number of local iterations (block526). In some cases, a default seven local iterations are allowed per each global iteration. Based upon the disclosure provided herein, one of ordinary skill in the art will recognize another default number of local iterations that may be used in relation to different embodiments of the present invention. Where another local iteration is allowed (block526), the multi-dimensional data decoding algorithm is applied to the selected data set using the decoded output as a guide to update the decoded output (block531). The processes of blocks starting at block516are repeated for the next local iteration.

Alternatively, where all of the local iterations have occurred (block526), it is determined whether all of the global iterations have been applied to the currently processing data set (block536). Where the number of global iterations has not completed (block536), the decoded output is stored to the central queue memory circuit to await the next global iteration (block541). Alternatively, where the number of global iterations has completed (block536), an error is indicated and the data set is identified as non-converging (block546).

Turning toFIG. 6a, a data processing circuit600is shown that includes a multi-dimensional signal marginalization circuitry relying on individual dimension noise injection in accordance with some embodiments of the present invention. Data processing circuit600includes a number of analog front end circuits610(610a,610b,610c) that receive respective ones of analog inputs608(608a,608b,608c) from respective read heads (not shown). Each of analog front end circuits610processes a respective one of the analog signals608and provides a processed analog signal612(one of612a,612b,612c) to a respective analog to digital converter circuit615(one of615a,615b,615c). Each of analog front end circuits610may include, but is not limited to, an analog filter and an amplifier circuit as are known in the art. Based upon the disclosure provided herein, one of ordinary skill in the art will recognize a variety of circuitry that may be included as part of analog front end circuit610. In some cases, analog input signal608is derived from a read/write head assembly (not shown) that is disposed in relation to a storage medium (not shown). Based upon the disclosure provided herein, one of ordinary skill in the art will recognize a variety of sources from which the analog input signals608may be derived.

Each of the analog to digital converter circuits615converts a respective one of the processed analog signals612into a respective corresponding series of digital samples617(one of617a,617b,617c). Each of the analog to digital converter circuits615may be any circuit known in the art that is capable of producing digital samples corresponding to an analog input signal. Based upon the disclosure provided herein, one of ordinary skill in the art will recognize a variety of analog to digital converter circuits that may be used in relation to different embodiments of the present invention. Each of the series of digital samples617are provided to a respective one dimensional marginalization circuit625(one of625a,625b,625c). The digital marginalization circuits are operable to: (1) apply target filtering to digital samples617to yield ideal outputs, (2) subtract the ideal outputs from the digital samples617to yield error values, and multiply the error values by a respective marginalization value624(one of624a,624b,624c).

Turning toFIG. 6b, one implementation of an individual dimension noise injection circuit625is shown that may be used in relation to the data processing circuit ofFIG. 6ain accordance with various embodiments of the present invention. As shown in the example implementation ofFIG. 6b, individual dimension noise injection circuit625includes a loop DFIR circuit696that equalizes digital samples617to yield an equalized output629. A loop detector circuit694receives equalized output629and applies a loop detection algorithm to the digital samples to yield a detected output628. Detected output628is provided to a single dimension convolution filter680that applies target filtering on ideal detected output628based upon a single-dimensional partial response target681. Single-dimensional convolution filter circuit680may be any single-dimensional target filter as is known in the art. The result of the target filtering is provided as a filtered output682. Filtered output682is provided to a summation circuit684where it is subtracted from digital samples617to yield an error output686in accordance with the following equation:
e(n)=x(n)−xideal(n),
where e(n) indicates the error output686; x(n) indicates digital samples617; and xideal(n) indicates filtered output682.

Error output686is multiplied by marginalization value624using a multiplier circuit699to yield a marginalized error697. Marginalized error697may be represented by the following equation:
e′(n)=α·e(n),
where e′(n) indicates the vector of marginalized errors, and a indicates the marginalization value624. Marginalized error697is re-added to digital samples617by a summation circuit685to yield a series of modified digital samples623that are provided to a multi-dimensional equalizer ofFIG. 6a.

The modified digital samples623are set equal to the original digital samples617whenever a test control695is de-asserted indicating normal operation of circuit600. Referring again toFIG. 6a, each of the series of modified digital samples623(623a,623b,623c) is provided to a multi-dimensional joint equalizer circuit620. Multi-dimensional joint equalizer circuit620applies a multi-dimensional equalization algorithm to the sets of modified digital samples623a,623b,623cto yield a vector of equalized outputs691each corresponding to one of analog inputs608a,608b,608c. In some embodiments of the present invention, multi-dimensional joint equalizer circuit equalizer circuit620is a multi-dimensional digital finite impulse response filter circuit as are known in the art.

The vector of equalized outputs691is provided to a multi-dimensional sample buffer circuit675where they are stored. In addition, the vector equalized outputs691is provided directly to a multi-dimensional data detector circuit626as are known in the art. Sample buffer circuit675includes sufficient memory to maintain one or more codewords until processing of that codeword is completed through multi-dimensional data detector circuit626and a multi-dimensional data decoder circuit650including, where warranted, multiple “global iterations” defined as passes through both multi-dimensional data detector circuit626and multi-dimensional data decoder circuit650and/or “local iterations” defined as passes through multi-dimensional data decoder circuit650during a given global iteration. Multi-dimensional sample buffer circuit675stores the received data as buffered data677.

Multi-dimensional data detector circuit626is a data detector circuit capable of producing a detected output627by applying a data detection algorithm to a vector of data inputs derived from different heads. As some examples, the data detection algorithm may be but is not limited to, a Viterbi algorithm detection algorithm or a maximum a posteriori detection algorithm as are known in the art. Based upon the disclosure provided herein, one of ordinary skill in the art will recognize a variety of data detection algorithms that may be used in relation to different embodiments of the present invention. Multi-dimensional data detector circuit626may provide both hard decisions and soft decisions. The terms “hard decisions” and “soft decisions” are used in their broadest sense. In particular, “hard decisions” are outputs indicating an expected original input value (e.g., a binary ‘1’ or ‘0’, or a non-binary digital value), and the “soft decisions” indicate a likelihood that corresponding hard decisions are correct. Based upon the disclosure provided herein, one of ordinary skill in the art will recognize a variety of hard decisions and soft decisions that may be used in relation to different embodiments of the present invention.

Detected output627is provided to a multi-dimensional central queue memory circuit660that operates to buffer data passed between multi-dimensional data detector circuit626and multi-dimensional data decoder circuit650. When multi-dimensional data decoder circuit650is available, multi-dimensional data decoder circuit650receives detected output627from multi-dimensional central queue memory660as a decoder input656. Multi-dimensional data decoder circuit650applies a multi-dimensional data decoding algorithm to decoder input656in an attempt to recover originally written data. The result of the data decoding algorithm is provided as a decoded output654. Similar to detected output627, decoded output654may include both hard decisions and soft decisions. For example, data decoder circuit650may be any data decoder circuit known in the art that is capable of applying a decoding algorithm to a received input. Multi-dimensional data decoder circuit650may be, but is not limited to, a low density parity check decoder circuit or a Reed Solomon decoder circuit as are known in the art. Based upon the disclosure provided herein, one of ordinary skill in the art will recognize a variety of data decoder circuits that may be used in relation to different embodiments of the present invention. Where the original data is recovered (i.e., the data decoding algorithm converges) or a timeout condition occurs, data decoder circuit650provides the result of the data decoding algorithm as a data output674. Data output674is provided to a hard decision output circuit696where the data is reordered before providing a series of ordered data sets as a data output698.

One or more iterations through the combination of multi-dimensional data detector circuit626and multi-dimensional data decoder circuit650may be made in an effort to converge on the originally written data set. As mentioned above, processing through both the data detector circuit and the data decoder circuit is referred to as a “global iteration”. For the first global iteration, multi-dimensional data detector circuit626applies the data detection algorithm without guidance from a decoded output. For subsequent global iterations, multi-dimensional data detector circuit626applies the data detection algorithm to buffered data677as guided by decoded output654. Decoded output654is received from central queue memory660as a detector input629.

During each global iteration it is possible for data decoder circuit650to make one or more local iterations including application of the data decoding algorithm to decoder input656. For the first local iteration, multi-dimensional data decoder circuit650applies the data decoder algorithm without guidance from a decoded output652. For subsequent local iterations, multi-dimensional data decoder circuit650applies the data decoding algorithm to decoder input656as guided by a previous decoded output652. In some embodiments of the present invention, a default of ten local iterations is allowed for each global iteration.