Peak detector

A circuit includes a peak detector, a diode, a dynamic clamp circuit, and an offset correction circuit. The peak detector generates a voltage on the peak detector output proportional to a lowest voltage on the peak defector input. The anode of the diode is coupled to the peak detector input. The dynamic clamp circuit is coupled to the peak detector input and is configured to clamp a voltage on the peak detector input responsive to a voltage on the diode's anode being greater than the lowest voltage on the peak detector's input. The offset correction circuit is coupled to the peak detector output and is configured to generate an output signal whose amplitude is offset from an amplitude of the peak detector output.

BACKGROUND

Some systems include a laser diode driven by a laser driver integrated circuit (IC). The laser driver IC includes a current source. The laser diode is coupled between a supply voltage and an output terminal of the laser driver IC. When activated, the current source causes current to flow from the supply voltage, through the laser diode, and through the current source to ground. When on, a voltage drop develops across the laser diode, and the voltage on the output terminal of the laser driver IC is equal to the supply voltage less the voltage drop across the laser diode.

A parasitic inductance is typically present between the laser diode and the output terminal of the laser driver IC. The parasitic inductance is a combination of IC bond wire inductance and trace inductance of the printed circuit board on which the laser driver IC is mounted. As such, the current path is from the supply voltage, through the laser diode, through the parasitic capacitance, and through the IC's current source to ground.

The laser diode is pulsed on and off, and during each on-pulse, current from the IC's current source ramps up relatively rapidly. As the current through the parasitic inductance ramps up during each cycle, a voltage develops across the parasitic inductance proportional to the product of the slew rate of the increasing current and the value of the inductance of the parasitic inductance. In addition to the voltage drop across the laser diode, an additional voltage drop due to the parasitic inductance is present between the laser diode and the output terminal of the laser driver IC to which the laser diode is connected. As such, during the time that the current ramps up, the output voltage of the laser diode IC (i.e., the voltage on the output terminal coupled to the laser diode) falls to a level that is equal to the supply voltage less both the laser diode voltage drop and the parasitic inductance voltage. The time duration during which the output voltage drops due to the inductance voltage drop (in addition to the laser diode drop) is relatively short, but the current source within the laser driver IC unfortunately could be saturated during that time. The result of such saturation could be detrimental to the system performance.

SUMMARY

In one example, a circuit includes a peak detector, a diode, a dynamic clamp circuit, and an offset correction circuit. The peak detector generates a voltage on the peak detector output proportional to a lowest voltage on the peak defector input. The anode of the diode is coupled to the peak detector input. The dynamic clamp circuit is coupled to the peak detector input and is configured to clamp a voltage on the peak detector input responsive to a voltage on the diode's anode being greater than the lowest voltage on the peak detector's input. The offset correction circuit is coupled to the peak detector output and is configured to generate an output signal whose amplitude is offset from an amplitude of the peak detector output.

DETAILED DESCRIPTION

FIG. 1shows a system100in which a laser driver integrated circuit (IC)120is connected to an external laser diode110. The laser driver IC120and the laser diode110are mounted on a printed circuit board (PCB)119. While the example ofFIG. 1includes a laser diode, other examples include light sources other than laser diodes. In the example implementation ofFIG. 1, an anode of laser diode110is connected to a positive power supply node (VDD). Briefly ignoring the inductance L0, the cathode of laser diode110is coupled to an output node (also referred to as a terminal or pin)121of the laser driver IC120. The voltage on the output node121is labeled VOUT. The laser driver IC120includes a current source122and a minimum peak detector circuit130, and possibly other components. An input signal (VIN) is provided to the current source122to cause the current source122to produce current. In one example, VIN comprises a control signal to turn on and off the current source122. When the current source122is activated, IOUT current flows from VDD through the laser diode110and the current source122to ground.

Inductance L0is shown between the laser driver IC120output node121and the laser diode110. As explained above, inductance L0represents the parasitic inductance that is a combination of bond wire inductance (e.g., bond wire between the output node121and PCB119on which the laser diode IC120is mounted) and PCB trace inductance. When the current source122is activated, the current IOUT of the laser driver IC120ramps from its 0 amperes towards its steady state level during a period of time (e.g., 230 ps). During the IOUT rise time, a voltage develops across the inductance L0that is equal to L0*d(IOUT)/dt, where L0is the inductance value of inductance L0and d(IOUT)/dt is the time derivative of IOUT. With IOUT increasing, the voltage on the laser driver's output node121(VOUT) is thus VDD minus both the voltage drop across laser diode110as well as the voltage developed across the inductance L0. The waveform150inFIG. 1shows the time progression of VOUT. VOUT falls to a minimum level (VOUTmin) at152due to the voltages across the laser diode110and inductance L0. Tpeak is the amount of time that IOUT is increasing and thus the amount of time during which the voltage develops across the inductance L0. After IOUT reaches its steady state level and thus ceases changing over time, the voltage drop across the inductance L0becomes 0 V, and VOUT increases to its steady state level (VOUTst)154, which is VDD less the voltage drop across the laser diode110.

The laser diode110is turned on by the laser driver IC120for a period of time (Ton), and then turned for a period of time, Toff. During Toff and thus with no IOUT current flowing, VOUT is equal to VOUTmax (156). VOUTmax156is approximately equal to VDD. The laser driver IC120repeatedly pulses the laser diode110on and off, with a predetermined periodicity. Waveform160shows VIN as being a periodic waveform that is high during Ton, and then low during Toff. When VIN is high, the current source122is activated to source current through the laser diode110, and when VIN is low, the laser diode is turned off.

VOUTmin (the minimum voltage of VOUT that occurs as IOUT is ramping up to turn on the laser diode110) can be low enough to saturate the current source122. Saturation of the current source122could be detrimental to the system performance such as to cause a latch-up problem with a bipolar junction transistor within the current source122, cause a relatively large amount of current to flow from a power supply to the current source122, cause the turn-off time for the current source122to increase, etc. The minimum peak detector circuit130monitors the voltage VOUT on the output node121and, in response, generates an output signal VPEAK at a voltage level equal to VOUTmin. That is, while VOUT is only briefly at VOUTmin during each cycle of the laser diode110, VPEAK persists (following a short settling time) at a relatively constant voltage level (equal to VOUTmin). Thus, VPEAK indicates the lowest level to which VOUT drops during the portion Tpeak of each cycle. The minimum peak detector circuit130allows the system to adjust the laser diode supply voltage (VDD) and/or the magnitude of IOUT current in order to prevent saturation of the current source122.

FIG. 2shows an example implementation of the minimum peak detector circuit130. In this example, the minimum peak detector circuit130includes a dynamic clamp circuit210, a main peak detector circuit220, a charge current circuit230, a base current cancellation circuit240, an offset correction circuit250, and a blocking diode D0. Other components may be included as well. The cathode of diode D0is coupled to the output node121and thus receives VOUT. The main peak detector circuit220generates a signal shown as VPEAK_LS which is a voltage on node213that is proportional to VOUTmin but is offset above VOUTmin by the voltage drop across diode D0as well as well as another voltage offset described below. The offset correction circuit250corrects for these offsets and produces the resulting VPEAK signal.

The example circuit implementation ofFIG. 2shows multiple transistors of various types—npn bipolar junction transistors (BJTs), pnp BJTs, n-type metal oxide semiconductor field effect transistors (NMOS), and p-type metal oxide semiconductor field effect transistors (PMOS). Other implementations may include different circuit architectures, and a different type of transistor for one or more of the transistors shown inFIG. 2.

The dynamic clamp circuit210includes current source devices ISRC4, ISRC5, ISRC6, and ISRC7, resistor R2, capacitor C1, diode D1, pnp transistors QP1, QP2, and QP3, npn transistor QN2, and PMOS transistors MP0, MP1, and MP2. A voltage supply (VSUP) is provided to the emitter of QP1, the collector of QN2, and to ISRC5and ISRC7. The collector of QP1is connected to its base and to R2. The other terminal of R2is connected to the source of MP1at a node217whose voltage is designated VCLmax. The gates of MP0and MP1are connected together and to the drain of MP1. ISRC4connects between the drain of MP1and ground.

The base of QN2is connected to the sources of MP0and MP2and to ISRC5at a node whose voltage is designated VCL1. The emitters of QN2and QP2are connected together. The bases of QP2and QP3are connected together and to the collector of QP2, to ISRC6, and to C1. ISRC6, C1, and the collector of QP3connect to ground. The anode of D1connects to ISRC7, and the cathode of D1connects to the emitter of QP3. The anode of D1also connects to D0at node215whose voltage is VOUT_LS.

The main peak detector circuit220includes pnp transistors QP4and QP5, npn transistors QN1, QN0, resistors R0and R1. The base of QP4connects to node215and thus to the anodes of diodes D0and D1. The collector of QP4is connected to the collector and base of QN1. The emitter of QN1is connected to ground, as is the emitter of QN0. The bases of QN1and QN0are connected together. Resistors R0and R1are connected together and to C0and ISRC3at node221, whose voltage is designated VED. R1is connected to the emitter of QP4. R0is connected to the emitter of QP5. The collector of QP5is connected to ground. VSUP is provided to C0, ISRC3, and Cpk as shown.

The charge current circuit230comprises current sources ISRC0and ISRC1. Current from ISRC0is designated ICH_0TC. The ISRC1current source is a proportional to absolute temperature (PTAT) current source device in that its current varies proportional to temperature (the current increases as temperature rises, and the current decreases as the temperature falls). ISRC0and ISRC1are connected together as shown. Some of the ICH_0TC current from ISRC0is provided through ISRC1as ICH_PTAT (proportional to absolute temperature). The rest of the ICH_0TC (ICH_0TC−ICH_PTAT) is shown as ICH. The effect of temperature on the minimum peak detector130is described below.

The current sources ISRC0and ISRC1are connected to the collector of QN0at node231whose voltage is designated VPEAK_LS. Node231(VPEAK_LS) is connected to the base current cancellation circuit240. The base current cancellation circuit240in this example includes current source ISRC2, NMOS transistors MN0and MN1and pnp transistor QP0. MN0and MN1are configured as a current source and connect to the base of QP0. The emitter of QP0is connected to a current source ISRC2.

Node231(VPEAK_LS) also is coupled to the offset correction circuit250. The offset correction circuit250includes an operational amplifier (OP0), diode D2, current sources ISRC8, ISRC9, and ISRC10, capacitor Clp, and resistor Roff. The output of OP0is connected to the anode D2. The cathode of D2provides the output signal VPEAK, and also connects to ISRC10. Roff comprises a feedback resistor connected between the output of OP0and the negative input of OP0. Capacitor Clp is connected in parallel with Roff. VPEAK_LS is provided to the positive input of OP0. ISRC9is connected to Roff, Clp, and to the negative input of OP0.

The minimum peak detector circuit130detects the minimum or negative peaks in VOUT during each cycle. The term “negative peak” refers to the lowest voltage level of VOUT during each cycle (VOUTmin). VOUTmin, however, is not a negative voltage with respect to ground. The minimum peak detector circuit130addresses several design drivers. For example, VOUT may experience a large swing (due to the voltage that develops across the parasitic capacitance L0) as IOUT ramps up when turning on the laser diode110. For example, VOUT may swing from 10V or higher down to close to ground (e.g., 500 mV) over 230 ps. Further, there could be a large delta (e.g., more than 7V) between VOUTmin and VOUTst due to either a fast rise time of IOUT and/or a large total inductance L0. The minimum peak detector circuit130should accurately generate VPEAK for an input pulse at VIN (Ton) of a few nanoseconds or less and the pulse width of the negative peak (Tpeak) on the order of hundreds of picoseconds. These latter timing values generally require transistors made according to a high-speed process which is typically synonymous with lower breakdown voltages for the active devices. The minimum peak detector circuit130also should operate with a range of Toff from 20 ns to 200 ns. Further, the detection by the minimum peak detector circuit130should have a low temperature variation assuming no difference in the system response as the temperature varies. The minimum VOUT peaks to be detected may be in the range of 300 mV to 2.3 V with a maximum supply available of 4.8V. Further still, the total current consumption should be less than 500 uA. The disclosed minimum peak detector circuit130satisfies one or more of these design criteria.

The voltage on the anode of diode D0is VOUT_LS. Given the large voltage swing at VOUT (e.g., 6.5 V and possibly greater), diode D0functions as a blocking diode to allow only VOUT voltages one diode voltage drop lower than VOUT_LS during every negative transition of VOUT. The dynamic clamp circuit210limits the upper limit of VOUT_LS to a predetermined level (e.g., 2.88 V), while the minimum voltage on VOUT_LS is approximately 0.85V (one diode voltage drop) above VOUTmin. For example, in an example in which VOUTmin is 0.56V, VOUT_LS will be 1.41 V (0.56 V+0.85 V). As will be explained below, the voltage VCLmax on node217of the dynamic clamp circuit210represents the maximum voltage for VOUT_LS.FIG. 4(further described below) illustrates a case in which VOUT ranges from 8.8V down to 2.36V, and thus VOUT min is 2.36V. In this case the maximum voltage at VOUT_LS equals 3.57V which is the same voltage as VCLmax on node217. VCLmax thus sets (clamps) the maximum voltage for VOUT_LS.

The following discussion includes the operation of the example dynamic clamp circuit210ofFIG. 2. Reference is also mode to the waveforms ofFIG. 3which show VOUT and VOUT_LS during a portion of a cycle in which the laser diode110is turned on. When the laser diode110is off (as is the case at302) and before any negative peak occurs on VOUT, the following operating condition is present in the dynamic clamp circuit210. The voltage VOUT at302equals VOUTmax which in the case ofFIG. 3equals 7V. The voltage VOUT_LS when the laser diode110is off (312) equals VCLmax and is dictated by the voltage drop across the loop formed by transistors MP1, MP0, QN2, QP2, and QP3, and diode D1. In this example, the loop formed by transistors MP1, MP0, QN2, QP2, and QP3, and diode D1limits the high voltage for VOUT_LS to 2.88 V.

Current source ISRC7sinks current through D1and QP3to ground. For the example in which VSUP is 4.8V, VOUT_LS equals 3.57V at a temperature of 27 degrees Celsius. If VOUT equals 7V, diode D0is reverse biased by 7 V minus 3.57 V which equals 3.43V. In this implementation, diodes D0and D1are implemented as a base-collector junction of an NPN transistor (e.g., an NPN transistor whose base is connected to its collector), which has a reverse bias breakdown voltage larger than, for example, 10V. By solving Kirchoff's Voltage Law (KVL), it can be shown that the main peak detector circuit220will set the voltage VPEAK_LS on node231as follows: VPEAK_LS=VOUT_LS−VT*In[(Ibs0−ICH)/ICH], where ICH=ISRC0−ISRC1(described below), Ibs0is the current value of ISRC3, Ibs0is substantially greater than ICH, and VT=KT/q, T is the temperature of a p-n junction, K is Boltzmann's constant and q is the magnitude of the charge of an electron.

In one example, at 27 degrees Celsius, lbs0is approximately equal to 100*ICH, and VPEAK_LS=VOUT_LS−0.12V which equals 3.57 V−0.12 V=3.45 V. Transistor MP2is off because the voltage (VCL1) on its source is at the same voltage as VCLmax, which in one example equals 3.57 V, and the gate voltage of MP2is the VPEAK_LS, which is 3.45 V. As such, the gate-to-source voltage of MP2is lower than its threshold voltage, and thus MP2is off.

The collector current of QP4is equal to the collector current of QN1. QN1and QN0form a current mirror. In one example, the current mirror ratio of the current mirror QN1/QN0is 1:1 and the collector current through QN0also is equal to the collector current of QP4and QN1. The charge current ICH flow through QN0, and thus the collector current of QN0, QN1, and QP4is equal to ICH. At node221, the current lbs0from ISRC3divides between the branch comprising R1and QP4and the branch comprising R0and QP5. Some of the Ibs0current thus flows through R1/QP4, and the rest of the current flows through R0/QP5. The collector current of QP5is equal to Ibs0minus ICH. The magnitude of Ibs0is much greater than ICH which means that most of the current of ISRC3flows through QP5, and only ICH flows through QP4. The base current of QP5is provided via the base current cancelation circuit240.

FIGS. 3 and 4shows examples in which VOUTmax is 7 V (FIG. 3) and 8.8 V (FIG. 4). InFIG. 3, VOUT falls to 565 mV for VOUTmin, while inFIG. 4, VOUT falls to 2.36 V for VOUTmin. VOUT_LS also tracks downward as VOUT falls to its minimum value but remains about one diode voltage drop above VOUTmin due to the voltage drop across D0. InFIG. 3, the minimum value of VOUT_LS is 1.41 V, while inFIG. 4, the minimum value of VOUT_LS is 3.16 V. The main peak detector circuit220generates VPEAK_LS as an indication of the negative peak of VOUT, and the offset correction circuit250(described below) corrects the offset between VPEAK_LS and VOUTmin.

FIG. 5shows what happens during the first pulse on VOUT when diode D0turns on for the first time and VOUTmin is less than VCLmax minus the voltage drop across D0. For the narrow time duration in which VOUT_LS is substantially less than VPEAK_LS (approximately 230 ps in the example ofFIG. 5) a large pump current through QP4is present which is mirrored by QN1/QN0to the capacitor Cpk. Cpk functions as a sampling capacitor. The current to the sampling capacitor Cpk is I_DISCH and causes VPEAK_LS to drop quickly during Tpeak. The current in QP4during this short pulse has two components: a) the DC current component provided by ISRC3, which for power reasons is reasonably small (e.g., approximately 40 uA); and b) a transient component which is determined by C0, R1, the emitter area of QP4, and the initial voltage at VED (node221). The transient component dominates the I_DISCH current during the first few pulses of VOUT and becomes progressively smaller as VPEAK_LS approaches the minimum value of VOUT_LS (510).

Resistor R1limits the current in QP4during the first pulse, when VOUTmin is close to ground. After the minimum peak detector circuit130reaches steady state (VPEAK_LS has reached its lowest value),
ICH*(Ton+Toff)=I_DISCH*Tpeak.  (1)

That is, I_DISCH (during Tpeak) integrated over the period of the signal (Ton+Toff) will equal the constant pull-up current ICH. During this steady state condition, VOUT_LS during Tpeak drops approximately 250 mV (27 degrees Celsius) bellow VPEAK_LS for Eq. (1) to hold true.

FIG. 6shows multiple events610in which the laser diode110is turned on, each time with VOUT dropping (due to the inductance L0) to approximately 557 mV (VOUTmin). VOUT_LS also drops each time the laser diode110turns on. VOUT_LS drops to a level that is about one diode voltage drop higher than VOUTmin. During the progression of events610in which the laser diode110is repeatedly turned on, VPEAK_LS also begins to trend downward as shown at630. VPEAK_LS flattens out at approximately 250 mV higher than minimum level640of VPEAK_LS. The 250 mV offset results from maintaining a sufficient voltage across the capacitor Cpk to be able to charge and discharge the capacitor.FIG. 6also shows the progression of I_DISCH each time the laser diode110is turned on. Initially, I_DISCH is equal to 8.66 mA (as shown at660) but falls to 10 μamps at665.

FIG. 7shows a comparison of several signals when the dynamic clamp circuit210is included and used versus not used. The upper waveform710shows an example of VOUT as the laser diode110is repeatedly turned on and off. In this example, VOUTmin is 256.2 mV. The lower waveforms ofFIG. 7show the base-to-emitter voltage (Vbe) of QP4for the case in which the dynamic clamp circuit210is enabled (waveform720) and the case in which the dynamic clamp circuit is disabled (waveform730). For both cases the first peak on VOUT causes a maximum Vbe of approximately −1.23 V, which will not damage QP4. With the dynamic clamp circuit210disabled, Vbe reaches a steady state voltage of −1.45 V, which could damage QP4. With the dynamic clamp circuit enabled, Vbe reaches a steady state voltage of approximately −577 mV, which is not large enough to damage QP4. The Vbe of QP4is the difference between VOUT_LS (base of QP4) and the voltage on QP4's emitter.

FIG. 8shows the waveform805for VOUT_LS with the dynamic clamp circuit210enabled as the laser diode is repeatedly turned on and off. Waveform810shows VOUT_LS with the dynamic clamp circuit210disabled. With the dynamic clamp circuit210enabled, the maximum VOUT_LS voltage trends downward as shown to approximately 2.65 V in this example, thereby reducing QP4's Vbe. With the dynamic clamp circuit210disabled, VOUT_LS remains at VCLmax on node217(FIG. 2), which in this example is 3.56 V. The dynamic clamp circuit210, when enabled, adjusts downward the maximum voltage at VOUT_LS by 0.91 V (3.56 V down to 2.65 V) thereby preventing the degradation of QP4.

The bottom portion ofFIG. 8shows VPEAK_LS for the two scenarios (dynamic clamp circuit210enabled and disabled). Waveform820shows an example of VPEAK_LS with the dynamic clamp circuit disabled, and waveform830shows an example of VPEAK_LS with the dynamic clamp circuit enabled. VPEAK_LS is slightly lower (by approximately 30 mV in this example) because VOUT_LS drops less with the dynamic clamp circuit enabled (2.65V to 1.12V) than in the case in which the dynamic clamp circuit is enabled (3.56V to 1.12V). The smaller voltage swing results in a wider pulse, thus requiring less overdrive at the input of QP4/QP5to generate the same integrated I_DISCH current.

Referring back toFIG. 2, two offsets are compensated for by the offset correction circuit250. The voltage drop across D0is compensated by D2that has the same current density as D0when D0is on. The offset of approximately 250 mV, that VPEAK_LS is larger than VOUT_LS, is compensated in the feedback of op amp OP0by using Roff and ISRC8and ISRC9. In addition, a low-pass filter is created by capacitor Clp in parallel with Roff to filter out the small glitches on VPEAK_LS caused during pulsing.

FIG. 9shows example waveforms of VOUT, VOUT_LS, VPEAK_LS, and VPEAK, while the loop is acquiring VOUTmin, which in this example 796 mV. As shown, after the loop stabilizes, VPEAK settles at a level that is equal to VOUTmin. In this example, the loop took about 25 cycles (about 1 μsecs) to stabilize to produce an accurate level for VPEAK.

FIG. 10shows an example relationship between VPEAK and VOUTmin with VOUTmin ranging from 50 mV to 2.75 V. The settled value of VPEAK is shown (settled after 1.4 μsecs). The graph ofFIG. 10shows satisfactory linearity for VOUTmin in the range of approximately 0.3 V to 2.3V. Some compression of VPEAK is present for VOUTmin greater than 2.3V due to lose of headroom at the VOUT_LS node231. The compression issue can be improved if a larger voltage for supply VSUP is used.

Referring toFIG. 2, current ICH has a complementary to absolute temperature (CTAT) characteristic which helps the main peak detector circuit220maintain approximately the same minimum VOUT peak detection as temperature varies over a range of, for example, −20 degrees C. to 105 degrees C. Current ICH is the current from ISRC0less the current from current source ISRC1. The current from ISRC0is ICH_0TC and is a temperature-independent trimmed current. The current from ISRC2is proportional to absolute temperature (PTAT) current. The subtraction of the two, results in a CTAT characteristic for ICH. The reason for the relatively constant level of VPEAK over temperature is that as temperature rises, QP4slows down (e.g., lower bandwidth) and with that it conducts less pump current for the same VOUT_LS−VPEAK_LS voltage during time Tpeak. If ICH had a PTAT characteristic, as temperature increases, the peak detector loop would cause VPEAK_LS to increase so that it has more overdrive during Tpeak to compensate for ICH. By decreasing ICH as the temperature increases (CTAT), the peak detector loop can maintain about the same VPEAK voltage.

FIG. 11illustrates VPEAK for different VOUTmin values and for different temperatures. For example, plot1102shows VPEAK for a VOUTmin of 0.25 V for temperatures ranging from −20 degrees C. to 110 degrees C. Example plot1112shows VPEAK for a VOUTmin of 1.15 V across the same temperature range. For the range of VOUTmin of 250 mV to 2.3 V, the worst percentage variation is at VOUTmin=250 mV, where VPEAK varies by 19 mV for the detected VOUTmin peak of 250 mV, which is less than 8%.

Transistors comprise a control input and current terminals. In the case of a bipolar junction transistor, the control input is the base, and the current terminals are the emitter and collector. In the case of a metal oxide semiconductor field effect transistor, the control input is the gate, and the current terminals are the source and drain.