Three-dimensional decoupling integration within hole in motherboard

Semiconductor packages and a method of forming a semiconductor package are described. The semiconductor package has a foundation layer mounted on a motherboard. The semiconductor package also includes a hole in motherboard (HiMB) that is formed in the motherboard. The semiconductor package has one or more capacitors mounted on an electrical shield. The electrical shield may be embedded in the HiMB of the motherboard. Accordingly, the semiconductor package has capacitors vertically embedded between the electrical shield and the HiMB of the motherboard. The semiconductor package may also have one or more HiMB sidewalls formed on the HiMB, where each of the one or more HiMB sidewalls includes at least one or more plated through holes (PTHs) with an exposed layer. The PTHs may be electrically coupled to the capacitors as the capacitors are vertically embedded between the electrical shield sidewalls and the HiMB sidewalls (i.e., three-dimensional (3D) capacitors).

CROSS-REFERENCE TO RELATED APPLICATION

This patent application is a U.S. National Phase Application under 35 U.S.C. § 371 of International Application No. PCT/US2017/025152, filed Mar. 30, 2017, entitled “THREE-DIMENSIONAL DECOUPLING INTEGRATION WITHIN HOLE IN MOTHERBOARD,” which designates the United States of America, the entire disclosure of which is hereby incorporated by reference in its entirety and for all purposes.

FIELD

Embodiments relate to packaging for electronic devices. More particularly, the embodiments relate to packaging solutions that include decoupling capacitors on the side walls of a hole in motherboard (HiMB).

BACKGROUND

Integrated circuits (ICs), such as mobile small form factor package designs, present several problems. One such problem is that the ICs generate high-frequency noise. High-frequency noise typically propagates through the package resulting in electromagnetic interference (EMI) and radio frequency interference (RFI). High-frequency might further increase regulatory violations and degrade wireless performance.

As an effective approach, packaging solutions use a recess area or a HiMB level (hereinafter referred to as “HiMB”) typically in a printed circuit board (PCB). HiMB is required due to the z-height profile of decoupling land side capacitors (LSCs) located on the ICs. This HiMB is further accompanied with a metal shield enclosure that shields off the EMI and RFI to the surrounding components of the ICs. The drive to meet the need for miniaturization (or scaling down) of packages is, however, drastically decreasing the z-height of LSCs. This presents additional problems for packaging solutions, especially for (i) the PCB area utilization of the HiMB and (ii) the capacitors that are unable to be attached on the land side of the PCB under the die shadow, such as edge capacitors.

Conventionally, LSCs are used to suppress high-frequency noise, such as EMI and RFI. LSCs are typically soldered on the bottom of a package and lie between the package and a motherboard. Solder balls may be used to attach the package and the motherboard. The z-height of LSCs (i.e., the protruding height from the land side of the package) is typically a limiting factor in small form factor package design, for example, when the z-height of LSCs exceeds the z-height of solder balls. To accommodate the z-height of the LSCs, a HiMB can be formed on the motherboard and accompanied with an EMI shield that suppresses the EMI and RFI to the surrounding components of the package. The HiMB is typically enclosed with the EMI shield and, therefore, results in an unutilized PCB area.

To meet the demand for miniaturization, packaging solutions utilize the HiMB to house the z-height profile of the LSCs. This typical approach, however, has resulted in two problems. One problem of this approach is that larger capacitors are placed far from the package and on the edges of the motherboard (i.e., edge capacitors), which has proven to be ineffective. Another problem of this approach is that the large PCB area formed with the HiMB and EMI shield is unused and thus considered wasted in terms of PCB area utilization.

DETAILED DESCRIPTION

A semiconductor package is described herein that includes a foundation layer mounted on a motherboard. The semiconductor package further includes a hole in motherboard (HiMB) that is formed in the motherboard. The semiconductor package also includes an electrical shield (also referred to as an electromagnetic interference (EMI) shield) that is attached to one or more three-dimensional (3D) capacitors and embedded in the HiMB of the motherboard. The 3D capacitors are vertically embedded between the electrical shield and the HiMB. Accordingly, the 3D capacitors are implemented as decoupling capacitors that are embedded within the sidewalls of the HiMB to utilize the unused area under the hole.

Embodiments of the semiconductor package enhance packaging solutions. Embodiments of the semiconductor enable 3D decoupling integration within the HiMB. Embodiments of the semiconductor package include capacitors that are vertically embedded to the side walls of the HiMB (i.e., 3D capacitors) and thus utilizing the unused PCB area of the HiMB. With additional capacitors mounted on the sidewalls of the HiMB, embodiments of the semiconductor package help to reduce the land-side capacitors (LSCs) that are need for the foundation layer. This approach also enables a LSC cavity (also referred to as a land-side cavity) with a shrinking z-height and reduces the overall form factor package design.

Likewise, embodiments of the semiconductor package reduce the PCB area needed for edge capacitors, as the capacitors are instead embedded in the HiMB. These embodiments, therefore, reduce the PCB area utilization and improve the miniaturization of the small form factor packages/platforms. As such, embodiments of the semiconductor package help to overcome the limitations on shrinking packages by reducing the z-height of LSCs, the area (x-y footprint) of motherboards, and the z-height of the HiMBs.

Furthermore, embodiments of the semiconductor package provide EMI and RFI mitigation that improves the electrical performances of the integrated circuits (ICs). Embodiments of the semiconductor package include 3D capacitors that are located closer to the power/ground pads (or balls) of the foundation layer—unlike edge capacitors that are located on the edges of the motherboard and away from the foundation. Accordingly, as the 3D capacitors are located under the foundation layer, these 3D capacitors improve efficiency and have a smaller inductance loop with a shorter path to the ground pads/balls of the foundation layer.

According to one embodiment,FIG. 1is a cross-sectional view of a typical semiconductor package assembly100that includes a HiMB solution. The typical semiconductor package assembly100may include a motherboard101, a foundation layer102(or a chip carrier package/substrate), solder balls103, one or more land-side capacitors (LSCs)104, HiMB105, and EMI shield106. The LSCs104are usually soldered on the bottom of the foundation layer102and lie between the foundation layer102and the motherboard101. The solder balls103may be used to attach the foundation layer102and the motherboard101. To accommodate the z-height of the LSCs104, the HiMB105is formed on the motherboard101and accompanied with the EMI shield106that suppresses the EMI and RFI to the surrounding components of the typical semiconductor IC package100. HiMB105is a hole occupying a large x-y area and all the routing layers located under the die shadow region—and thus trading off platform form factors and electrical performance. For example, as shown inFIG. 1, the large hole of the HiMB105is enclosed with the EMI shield106and, therefore, results in an unutilized PCB area.

To meet the demand for miniaturization, packaging solutions utilize the typical semiconductor package assembly100with the HiMB105to house the z-height profile of the LSCs104. This typical approach, however, has provided problems. One problem of this approach is that larger capacitors are placed far from the foundation layer102and on the edges of the motherboard101(i.e., edge capacitors), which has proven to be ineffective. Another problem of this approach is that the large PCB area formed with the HiMB105and EMI shield106is unused and thus considered wasted in terms of PCB area utilization. Accordingly, other embodiments have been presented below that can overcome these problems.

FIG. 2Ais a side, perspective view of semiconductor package200that includes semiconductor die204, motherboard201, and foundation layer212. Motherboard201has HiMB210and LSC cavity230(as described in further detail below inFIG. 2B). As used herein, a “HiMB” refers to a recess, a cavity, or a hole in motherboard201. A “HiMB” is formed under semiconductor die204shadow, the land-side of foundation layer212, and LSC cavity230to accommodate LSCs214with a large z-height profile. As used herein, a “z-height” refers to a unit of measurement on the z-axis in a three-dimensional package, which is usually oriented vertically. Further, a “HiMB” is often accompanied with an EMI shield (e.g., EMI shield250ofFIG. 2B). As used herein, an “EMI shield” refers to a shield enclosure—typically a metal shield enclosure—used to suppress (or shield off) the EMI and RFI to the surrounding components of semiconductor package200. As used herein, a “foundation layer” refers to, but is not limited to, a package, a substrate, a motherboard, and a printed circuit board (PCB).

Foundation layer212is mounted on motherboard201. For one embodiment, foundation layer212is a PCB. For one embodiment, the PCB is made of an FR-4 glass epoxy base with thin copper foil laminated on both sides (not shown). For certain embodiments, a multilayer PCB can be used, with pre-preg and copper foil (not shown) used to make additional layers. For example, the multilayer PCB may include one or more dielectric layers, where each dielectric layer can be a photosensitive dielectric layer (not shown). Foundation layer212is patterned to form one or more conductive copper traces and pads (not shown) on the top and bottom of foundation layer212. For some embodiments, holes (not shown) may be drilled in foundation layer212.

Foundation layer212resides (or is mounted) between motherboard201and semiconductor die204. For another embodiment, foundation layer212may have a package/substrate (not shown) that is mounted above foundation layer212, where the semiconductor die204is mounted on the package/substrate rather than on foundation layer212. For one embodiment, semiconductor die204includes, but not limited to, an integrated circuit, a CPU, a microprocessor, and a platform controller hub (PCH).

For embodiment, foundation layer212may include LSCs (as shown inFIG. 2Bwith LSCs214) to decouple one or more interferences (e.g., EMI and RFI) generated by semiconductor die204. Semiconductor die204may be attached to foundation layer212using solder balls or controlled collapse chip connection (C4) bumps (not shown) that connect pads on semiconductor die204and foundation layer212.

For one embodiment, motherboard201is also made of a multilayer PCB having copper traces, holes, and metallic pads (not shown). Motherboard201may have one or more electronic components, such as microprocessors (or CPUs), memories, ICs, and microelectronics devices, that are mounted/located on the motherboard201.

Foundation layer212is attached to motherboard201through the use of solder balls (or bumps)203that connect pads (not shown) on foundation layer212and motherboard201. For example, solder balls203may be used on a ball grid array (BGA). Note that other methods of connectivity packaging may also be used such as pin grid array (PGA) or land grid array (LGA).

For one embodiment, semiconductor package200has foundation layer212, motherboard201, semiconductor die204, and EMI shield250. Foundation layer212is mounted above motherboard201. For some embodiments, foundation layer is mounted between semiconductor die204and motherboard201. Foundation layer212may include one or more LSCs mounted on the land-side of foundation212and under semiconductor die204.

Motherboard201is formed with HiMB210, LSC cavity230, and one or more ground pads260. HiMB210may be a circular hole, a square hole, a triangle, a rectangle, or any shape. For one embodiment, HiMB210is a square (or rectangular) hole with one or more sidewalls280, as such for this embodiment HiMB201has four sidewalls280. Note that number of sidewalls280will be proportional to the selected shape of HiMB210(e.g., a circular hole may have one sidewall, a triangular hole may have three sidewalls, etc.). Note that the sidewalls280may be formed using a plated thru hole (also referred to as plated through hole) (PTH) process (as shown in further detail inFIGS. 13-17) or any other drilling/plating process.

For one embodiment, EMI shield250is, but is not limited to, a metal plate that has one or more metal pads270located along each end of EMI shield250(as shown inFIGS. 3B and 4B). EMI shield250may be, but is not limited to, a metal plate/sheet, a metal screen, a metal foam, a metal mesh, a Faraday cage, etc., or any other type of material used for EMI/RFI shielding (e.g., a plastic enclosure coated with a metallic ink or similar material).

EMI shield250has one or more sidewalls680. EMI shield250also has one or more 3D capacitors251-252that are attached (or mounted) vertically to one or more sidewalls680of EMI shield250with adhesive265. As used herein, a “3D capacitor” refers to a decoupling capacitor that is mounted/located within HiMB210, and mounted under foundation layer212and LSC cavity region230. These “3D capacitors” are located closer to the power/ground balls of foundation layer212, thus providing a smaller/shorter inductance loop (back to the silicon) with a shorter path to the ground pads/balls of foundation layer212. Further, a “3D capacitor” refers to a capacitor that is vertically attached (on the z-axis) to the one or more sidewalls280of HiMB210and the one or more sidewalls680of EMI shield250.

The one or more 3D capacitors251-252may include one 3D capacitor, two 3D capacitors, three 3D capacitors, four 3D capacitors, etc., or any number of 3D capacitors that are needed. For one embodiment, each of the 3D capacitors251-252is a capacitor with a presolder layer that is dipped with a solder layer (as shown inFIG. 4A). For one embodiment, adhesive265may be an insulating adhesive, an epoxy adhesive, an adhesive tape, a thermal adhesive layer, a UV releasable tape, or any other type of insulated adhesive.

For one embodiment, the 3D capacitors251-252are located on, but not limited to, the outer edges of EMI shield250. For one embodiment, once EMI shield250is shaped (or formed), the side walls680of EMI shield250are then embedded in the sidewalls280of HiMB210, as the one or metal pads270of EMI shield250are coupled with the one or more ground pads260of motherboard201. Accordingly, the 3D capacitors251-252are vertically embedded between the sidewalls680of EMI shield250and sidewalls280of HiMB210.

According to some embodiments, 3D capacitors251-252are each connected on each end of the 3D capacitors251-252to a Vss terminal and a Vcc terminal (as shown inFIG. 19), where the terminals are formed on a PTH along sidewalls280of HiMB210. Accordingly, the 3D capacitors251-252are mounted/coupled vertically between the sidewalls680of EMI shield250and sidewalls280of HiMB210, where they are held in place using adhesive layer265and a reflow process.

For some embodiments, solder balls203collapse as foundation layer212is mounted on motherboard201. Accordingly, the collapsed solder balls203have a limited z-height that is smaller than the z-height profile of LSCs214. To accommodate for the shrinking z-height between foundation layer212and motherboard201, a LSC cavity230may be formed in a land-side layer of foundation layer212. One or more LSCs214may be mounted within the LSC cavity230. The z-height of the LSCs214may be a factor in establishing the minimum standoff distance between foundation layer212and motherboard201, and as such, may affect the minimum size solder balls203used in a BGA mounting structure. By mounting LSCs214within LSC cavity230, the amount that LSCs214protrude from the land-side surface of foundation layer212is reduced, also reducing the minimum required standoff distance and the minimum required solder ball size. Smaller solder balls may be spaced closer together, requiring less package surface area for a constant number of BGA connections.

LSC cavity230, however, may have a z-height that can accommodate the z-heights of some LSCs but not all of the LSCs. HiMB210is thus formed to house all the LSCs (e.g., LSCs214), even if the LSCs protrude past the z-heights of the LSC cavity230and solderballs203. As such, in addition to reducing the z-height of semiconductor package200, mounting LSCs214within LSC cavity230of foundation layer212and HiMB210of motherboard201may reduce the x-y-z dimensions of the semiconductor package200. To further add to reducing the dimensions of semiconductor package200, EMI shield250is embedded within the sidewalls280of HiMB210(i.e., reducing the z-height dimension of the overall package) and attached vertically to the 3D capacitors251-252to reduce (or eliminate) the requirement of edge capacitors on motherboard201(i.e., reducing the x-y dimensions of the overall package). Having the overall dimensions of semiconductor package200mitigated is advantageous because no additional assembly or part(s) is required, and as such the manufacturing (e.g., original equipment manufacturing (OEM)) complexity and uncertainty is drastically reduced.

For certain embodiments, embedding EMI shield250and 3D capacitors251-252within the sidewalls280of HiMB210help to facilitate a 3D decoupling integration within the HiMB210. As used herein, a “3D decoupling integration” (also referred to as “3D decoupling integration process”) refers to the EMI shield250and the 3D capacitors251-252being embedded/integrated into the HiMB210of motherboard201. This “3D decoupling integration” helps to suppress EMI and RFI to the package. Embedding EMI shield250with the attached 3D capacitors251-252within the sidewalls280of HiMB210is even more suitable for smaller form factors, as the dimensions of the package and solder balls keep shrinking. Having 3D capacitors251-252formed near semiconductor die204and foundation layer212rather than using edge capacitors is advantageous because the proximity (i) reduces the x-y dimensions of the overall package; and (ii) improves noise reduction as parasitic inductance generated by vias and routings is minimized.

The 3D decoupling integration within the HiMB210, therefore, helps to facilitate shrinking and cost saving of the package by reducing the overall dimensions of the package, while also shielding off EMI and RFI to the surrounding devices in the semiconductor package (or the platform). Likewise, with additional capacitors251-252placed on the sidewalls280of HiMB210, the semiconductor package200can have a smaller LSC cavity230and a reduced number of LSCs214on the foundation layer210, which reduces the overall package form factor. At the same time, the 3D decoupling integration helps to eliminate (or reduce) the requirement of edge caps on motherboard201by placing these capacitors within HiMB210.

Note that semiconductor package200may include fewer or additional packaging components based on the desired packaging design.

FIGS. 3-9illustrate a process flow (as shown inFIG. 20) of forming semiconductor package300with EMI shield250including one or more 3D capacitors251-254that is embedded in sidewalls280of HiMB210of motherboard201.

FIGS. 3A and 4Aare perspective view illustrations of a method of forming an EMI shield250with one or more 3D capacitors251-254.FIGS. 3B and 4Bare top view illustrations of a method of forming an EMI shield250with one or more 3D capacitors251-254.

Referring now toFIGS. 3A and 3B.FIG. 3Aillustrates semiconductor package300forming EMI shield250with one or more metal pads270. For one embodiment, as shown inFIG. 3B, EMI shield250is a metal plate (or sheet) with a folding edge line325(shown as a white broken line) that has four folding edges. For example, one metal pad270is located on the outer end (or at least one end) of each folding edge of EMI shield250. Note that folding edge line325is used to illustrate the top edge lines of EMI shield250that are formed as EMI shield250is molded with a molding jig (e.g., molding jig501ofFIG. 5). Also note that EMI shield250, as described above, may be formed of any type of shape, and folding edge line325may thus be formed of any type of shape.

FIG. 4Aillustrates mounting one or more 3D capacitors251on EMI shield250of semiconductor package300. For some embodiments, one or more 3D capacitors251are mounted (or attached) above EMI shield250using adhesive265. For one embodiment, each 3D capacitor251is a capacitor that has at least two terminals (e.g., voltage at the common collector (Vcc)1801and voltage at the source supply (Vss)1802ofFIG. 18A), where each terminal is located on one of the two ends of each 3D capacitor251. For one embodiment, each 3D capacitor251has presolder (or dipped with solder) on each terminal end, for example, a Vcc terminal and a Vss terminal. For one embodiment, the presolder of 3D capacitor351allows each terminal end of 3D capacitor251to be vertically attached (or coupled) to at least one of a Vcc PTH (e.g., Vcc PTH1801ofFIG. 19) or a Vss PTH (e.g., Vss PTH1802ofFIG. 19) that is formed on a sidewall of a motherboard (e.g., sidewall280of HiMB210ofFIG. 19). Note thatFIG. 4Aillustrates a side, perspective view of EMI shield250of semiconductor package300and may have omitted (or briefly described) one or more components to facilitate the described embodiments.

Referring now toFIG. 4B, one or more 3D capacitors251-254are mounted on EMI shield250. The 3D capacitors251-254are mounted on one of four folding edges, where each folding edge has three 3D capacitors251-254. For example, 3D capacitors251are located on one folding edge of EMI shield250and along (or beside) metal pad270, while 3D capacitors252are located on the opposite folding edge of EMI shield250. Each of the 3D capacitors251-254are mounted parallel to the axis along each of the metal pads270of EMI shield250, as such the 3D capacitors251-254will be vertically mounted on each edge of EMI shield250when EMI shield250is molded (as shown inFIGS. 5-9). Note that semiconductor package300may include fewer or additional 3D capacitors based on the desired packaging design.

FIGS. 5-9are cross-sectional view illustrations of semiconductor package300. Specifically,FIGS. 5-7illustrate a method of molding EMI shield250with one or more 3D capacitors251-252.

FIG. 5illustrates EMI shield250, 3D capacitors251-252, and molding jig501. For one embodiment, EMI shield250is placed above molding jig501. Molding jig501is a mold that is used to mold/form a metal plate into a desired shape (e.g., an EMI/RFI rectangular enclosure) based on the form factor package design. For example, folding edge lines (e.g., folding edge line325ofFIG. 4B) of EMI shield250may be directly placed above the top edge lines of molding jig501. Accordingly, EMI shield250has pressure applied to the top side of EMI shield250and thus compressed onto molding jig501(as shown inFIG. 6). For some embodiments, a molding process is used to apply pressure to EMI shield250and mold EMI shield250with molding jig501. Note that the molding process includes, but is not limited to, a compression molding/printing, a pressure printing, a vacuum printing, etc., a combination thereof, or any other type of similar process.

After applying pressure at the edges of EMI shield250,FIG. 6illustrates EMI shield250molded into an EMI shield enclosure (as shown inFIG. 18B) with one or more sidewalls680using molding jig501. For example, EMI shield250may have four sidewalls680. EMI shield250also has one or more 3D capacitors251-252that are mounted vertically to the one or more sidewalls680of EMI shield250, where each 3D capacitor251-252is attached to EMI shield250using adhesive265. Note, for example, that with a top view of EMI shield250(as shown inFIG. 4B) each of the 3D capacitors251-254is mounted vertically on each of the four sidewalls680of EMI shield250, respectively.

For example, EMI shield250may have formed an open rectangular shape, as the EMI shield enclosure, with at least four sidewalls680, a top wall, and four metal pads metal pads270. For one embodiment, the four side walls680of EMI shield250will be embedded into (or parallel to) the sidewalls280of HiMB210of motherboard201(as shown inFIG. 18A). Accordingly, for one embodiment, the top wall of EMI shield250will be mounted directly below the LSCs214and LSC cavity230of foundation layer212(as shown inFIG. 9). Continuing with the above example, the four metal pads (e.g., two of the four metal pads270are shown inFIG. 6) of EMI shield250are perpendicular to the four sidewalls680and located below the one or more 3D capacitors251-254, where each metal pad270will be coupled to a ground pad260of motherboard201(as shown inFIG. 9).FIG. 7illustrates removing EMI shield250from molding jig501after the EMI shield250has been firmly molded.

FIG. 8shows pressure being applied (as shown with the white arrows) to EMI shield250with spring mechanism800. For example, spring mechanism800may be used within EMI shield250to compress/squeeze the sidewalls680of EMI shield250(in the direction of the white arrows), which allows the EMI shield250to insert HiMB210. Spring mechanism800may be, but is not limited to, a spring, a coil, or any type of elastic mechanism. As shown inFIG. 8, when pressure is applied to the sidewalls680of EMI shield250, EMI shield250may now be embedded (or inserted) within sidewalls280of HiMB210of motherboard201—until metal pads270of EMI shield250are pressed (or coupled) with ground pads260of motherboard201.

FIG. 9shows sidewalls680of EMI shield250embedded within sidewalls280of HiMB210of motherboard201. For example, spring mechanism800has been released to its original state within EMI shield250, as such EMI shield250has been released to its original state. This includes 3D capacitors251-252mounted vertically between sidewalls280of HiMB210and sidewalls680of EMI shield250, and ground pads260of motherboard201coupled to metal pads270of EMI shield250. Continuing with the example above ofFIG. 8, spring mechanism800may now be released within EMI shield250to return the sidewalls680of EMI shield250(in the direction of the white arrows), which presses (or sandwiches) 3D capacitors into its place between sidewalls280of HiMB201and sidewall680of EMI shield250as shown inFIG. 9.

Accordingly, as shown inFIG. 9, once spring mechanism800is released, EMI shield250is embedded into HiMB210of motherboard201and located under LSCs214and LSC cavity230of foundation layer212. For some embodiments, 3D capacitors251-252and metal pads270of EMI shield250are held into place with a reflow/soldering process (as shown inFIGS. 18A, 18C, and 19) or any other processes known in the art. Note that foundation layer212may include a semiconductor die (e.g., semiconductor die204ofFIGS. 2A-B) mounted above foundation layer212and EMI shield250. Also note that semiconductor package300may include fewer or additional packaging components based on the desired packaging design.

FIG. 10shows pressure being applied (as shown with the white arrows) to EMI shield250with spring mechanism800. For example, spring mechanism800may be used within EMI shield250to compress/squeeze the sidewalls680of EMI shield250(in the direction of the white arrows), which allows the EMI shield250to insert HiMB210. As shown inFIG. 10, when pressure is applied to the sidewalls680of EMI shield250, EMI shield250may now be embedded (or inserted) within sidewalls280of HiMB210of motherboard201—until metal pads270of EMI shield250are pressed (or coupled) with ground pads260of motherboard201.

FIG. 11shows sidewalls680of EMI shield250embedded within sidewalls280of HiMB210of motherboard201. For example, spring mechanism800has been released to its original state within EMI shield250, as such EMI shield250has been released to its original state. This state includes 3D capacitors251-252mounted vertically between sidewalls280of HiMB210and sidewalls680of EMI shield250, and ground pads260of motherboard201coupled to metal pads270of EMI shield250. Continuing with the example above ofFIG. 10, spring mechanism800may now be removed from within EMI shield250to return the EMI shield250to its original state. Then, assembly handler1110is inserted (from below) into EMI shield250to hold/press (in the direction of the black arrows), which presses (or sandwiches) 3D capacitors into its place between sidewalls280of HiMB201and sidewalls680of EMI shield250as shown inFIG. 11.

For one embodiment, assembly handler1110has a “T” shape with at least two arms on each end of the assembly handler1110. Assembly handler1110may be made from any rigid material and have any other type of shape that may be used to hold and fit into an EMI shield enclosure, such as EMI shield250.

As shown inFIG. 11, each arm of assembly handler1110holds EMI shield250in place, i.e., capacitors251-252are mounted vertically between sidewalls280of HiMB210and EMI shield250(or sidewalls680of EMI shield250), and ground pads260of motherboard201are coupled to metal pads270of EMI shield250. EMI shield250is now embedded within sidewalls280of HiMB210of motherboard201using assembly handler1110and located under LSCs214and LSC cavity230of foundation layer212. For some embodiments, 3D capacitors251-252and metal pads270of EMI shield250are held in place with assembly handler1110, as a reflow/soldering process is used to couple (or attach) the terminals of each of the 3D capacitors251-252with their respective Vcc PTH and Vss PTH (e.g., as shown inFIGS. 18A, 18C, and 19).

FIG. 12shows removing assembly handler1110from under EMI shield250. For example, after the reflow process, assembly handler1110releases its grip from within EMI shield250and is thus removed. Note that foundation layer212ofFIGS. 10-12may include a semiconductor die (e.g., semiconductor die204ofFIGS. 2A-B) mounted above foundation layer212and EMI shield250. Also note that semiconductor package1000may include fewer or additional packaging components based on the desired packaging design.

FIGS. 13-15A and 16A-17are cross-sectional view illustrations of a method of forming a HiMB with one or more sidewalls in a motherboard for a semiconductor package.FIGS. 15B and 16Bare top view illustrations of a method of forming a HiMB with one or more sidewalls in a motherboard for a semiconductor package.FIGS. 13-17show forming sidewalls280of HiMB210of motherboard201in semiconductor package1300.FIGS. 13-17also show forming one or more PTHs (e.g., Vcc PTH or Vss PTH) along sidewalls280of HiMB210of motherboard201in semiconductor package1300. Note that semiconductor package1300ofFIGS. 13-17is similar to semiconductor package200ofFIGS. 2A-2Band semiconductor package300ofFIGS. 3-9. However, different features will be mainly described, while similar features will be omitted or briefly described.

Referring now toFIG. 13. For one embodiment, semiconductor package1300has motherboard201that may include multiple layers used to form a build-up structure. For example, motherboard201has eight layers and each layer is formed over the next layer, starting with top layer1306.

Motherboard201may have one or more PTHs1305that are formed on motherboard201based on the shape of the HiMB that is needed (as shown inFIGS. 15B and 16B). PTHs1305are formed with a drilling process, a laser process, or any other processes known in the art.

For one embodiment, each PTH1305may have a via opening (e.g., via openings1311-1312) and a PTH via (e.g., PTH vias1301-1302), where each PTH via may be routed through each layer of motherboard201.

FIG. 14shows a conductive material deposited into via openings1311-1312of PTHs1305to form filled PTH vias1401-1402of motherboard201. For one embodiment, the conductive material may be a metal material, a conductive material, or the like. For one embodiment, filler PTH vias1401-1402may be formed with a copper electroplating (or electroless plating) process, or the like. Note that filled PTH vias1401-1402may be used to form a Vcc PTH, a Vss PTH, or any similar PTH.

FIGS. 15A-Bshow the formation of HiMB region1550in motherboard201using a laser ablation/drilling1500process, or any other processes known in the art. The laser/drilling process may include a router bit1500(or the like) that is used to form HiMB210. To form HiMB210according to one embodiment, router bit1500lasers (or drills) along the outer edges of HiMB region1550(as shown with broken lines inFIGS. 15A-B), which includes lasering/drilling through each of the one or more PTHs1305.

FIGS. 16A-Bshow HiMB210formed with sidewalls280and HiMB opening1630. According to some embodiments, each sidewall280of HiMB210has one or more PTHs1305that are exposed as shown inFIGS. 16A-B. For example, each of the PTHs1305has an exposed copper layer (or wall) that is formed along the top layer1306to the bottom layer of motherboard201. For some embodiments, a desmear process may be used to remove any residue along each sidewall280of HiMB210. For example, the desmear process may include a plasma etch, a mechanical grinding process, a mechanical polishing process, a chemical mechanical polishing process, or the like.

FIG. 17shows foundation layer212mounted on top layer1306of motherboard201. Foundation layer212may include one or more LSCs214that are located on LSC cavity230and within HiMB210. As described above, filled PTH vias1401-1402of PTHs1305may include Vcc PTHs and Vss PTHs (not shown) that are formed along each sidewall280of HiMB210to vertically couple one or more 3D capacitors (e.g., 3D capacitors251-254ofFIGS. 18-19). Note that foundation layer212may be mounted to motherboard201either before or after the EMI shield (e.g., EMI shield250ofFIG. 2A) has been embedded with HiMB210of motherboard201. Also note that semiconductor package1300may include fewer or additional packaging components based on the desired packaging design.

FIG. 18Bshows a bottom layer1807of motherboard201and EMI shield250. For some embodiments, semiconductor package1800may include fewer or additional packaging components based on the desired packaging design.

Semiconductor package1900includes 3D capacitors251-254embedded (or coupled/attached) vertically onto sidewalls280of HiMB210of motherboard201.FIG. 19shows the placement (and coupling) of 3D capacitors251-254without an EMI shield attached. According to some embodiments, semiconductor package1900may be formed with 3D capacitors251-254vertically embedded on the sidewalls280of HiMB210—without using an EMI shield depending on its application. For some embodiments, semiconductor package1900may include fewer or additional packaging components based on the desired packaging design.

FIG. 20is a process flow2000illustrating a method of forming an EMI shield with one or more 3D capacitors embedded into a HiMB of a motherboard in a semiconductor package. Process flow2000shows a method of forming a semiconductor package with an EMI shield with one or more 3D capacitors that are embedded into a HiMB of a motherboard201, as shown inFIGS. 3-9. For one embodiment, process flow2000may implement a molding/compression process and a laser/drilling process as described herein. Accordingly, process flow2000enables 3D capacitors251-254to be embedded vertically within HiMB210and EMI shield250(and thus located below LSC cavity230of foundation layer212), and attached vertically to Vss and Vcc PTHs that are formed on sidewalls280of HiMB210in a semiconductor package (e.g., semiconductor package200ofFIGS. 2A-B).

At block2005, process flow mounts one or more 3D capacitors on an electrical shield (or an EMI shield) as shown inFIGS. 4A-B. According to some embodiments, prior to mounting the one or more 3D capacitors, process flow forms an electrical shield (or an EMI shield) with one or more metal pads as shown inFIGS. 3A-B. For one embodiment, the 3D capacitors are mounted on the electrical shield with an adhesive as shown inFIG. 4A. For one embodiment, the electrical shield may have at least one or more folding edges, where each folding edge may have at least one metal pad on one of its outer edges (as shown inFIGS. 3B and 4B). For some embodiments, the 3D capacitors are mounted on the folding edges of the electrical shield as shown inFIGS. 3B and 4B.

At block2010, process flow molds one or more sidewalls on the electrical shield with a molding jig as shown inFIGS. 5-6. For one embodiment, the electrical shield is mounted above the molding jig as shown inFIGS. 5-6. For one embodiment, process flow may apply pressure on the folding edges (or at the edges) of the electrical shield to mold/form the one or more sidewalls of the electrical shield as shown inFIGS. 3B, 4B, and 5-6. According to some embodiments, each sidewall of the electrical shield has at least one metal pad, where the metal pad is molded/formed perpendicular to the sidewall of the electrical shield (as shown inFIG. 6).

At block2015, process flow removes the electrical shield from the molding jig as shown inFIG. 7. Note that the process flow may either remove the electrical shield from the molding jig or remove the molding jig from (under) the electrical shield. Accordingly, the 3D capacitors are now mounted vertically on the sidewalls of the electrical shield as shown inFIG. 7. At block2020, process flow embeds the one or more sidewalls of the electrical shield into the sidewalls of a HiMB of a motherboard, where the one or more sidewalls include the 3D capacitors mounted vertically between the electrical shield and the sidewalls of the HiMB (as shown inFIGS. 8-9). For one embodiment, the motherboard has one or more ground pads as shown inFIGS. 8-9. For some embodiments, after embedding the electrical shield into the HiMB, the 3D capacitors may be electrically coupled to one or more PTHs (e.g., Vcc PTHs, Vss PTHs, etc.) that are formed on the sidewalls of the HiMB (e.g., as shown inFIG. 19). For one embodiment, the one or more ground pads of the motherboard are coupled to the metal pads of the electrical shield. Note that a spring mechanism and/or an assembly handler may be used to hold (or grip) the electrical shield in place during a reflow process (as shown inFIGS. 8-12).

FIG. 21illustrates an example of computing device2100. Computing device2100houses motherboard2102. For most embodiments, motherboard2102is similar to motherboard201ofFIGS. 2-19. Motherboard2102may include a number of components, including but not limited to processor2104, 3D decoupling integration circuit2110, and at least one communication chip2106. Motherboard2102may also be formed to implement the 3D decoupling integration process, as described herein. For example, motherboard2102may include similar components as shown inFIGS. 2A-B.

Processor2104is physically and electrically coupled to motherboard2102. For some embodiments, at least one communication chip2106is also physically and electrically coupled to motherboard2102. For other embodiments, at least one communication chip2106is part of processor2104.

Processor2104of computing device2100includes an integrated circuit die (e.g., semiconductor die204ofFIGS. 2A-B) packaged within processor2104. 3D decoupling integration circuit2110may be implemented near the integrated circuit die packaged within processor2104to suppress EMI and RFI. For some embodiments, 3D decoupling integration circuit2110may be used to implement the 3D decoupling integration process, as described herein. For example, 3D decoupling integration circuit (or component)2110may include similar components as shown inFIGS. 2A-B.

For certain embodiments, the integrated circuit die may be packaged with one or more devices on a foundation layer (or a package substrate) that includes a thermally stable RHC and antenna for use with wireless communications and one or more of the 3D decoupling integration components, as described herein, to mitigate EMI/RFI noise and improve electrical performance. The term “processor” may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory.

At least one communication chip2106also includes an integrated circuit die packaged within the communication chip2106. For some embodiments, the integrated circuit die of the communication chip may be packaged with one or more devices on a foundation layer (or a package substrate) that includes one or more of the 3D decoupling integration components, as described herein, to mitigate EMI/RFI noise and improve electrical performance.

In the foregoing specification, embodiments have been described with reference to specific exemplary embodiments thereof. It should be borne in mind, however, that all of these and similar terms are to be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. It will be evident that various modifications may be made thereto without departing from the broader spirit and scope. The specification and drawings are, accordingly, to be regarded in an illustrative sense rather than a restrictive sense.

The following examples pertain to further embodiments. The various features of the different embodiments may be variously combined with some features included and others excluded to suit a variety of different applications.

The following examples pertain to further embodiments:

For some embodiments, a semiconductor package includes a foundation layer mounted on a motherboard; a hole in motherboard (HiMB) formed in the motherboard; and one or more capacitors mounted on an electrical shield, the electrical shield embedded in the HiMB of the motherboard, wherein the one or more capacitors are vertically embedded between the electrical shield and the HiMB of the motherboard.

For one embodiment, the semiconductor package further comprising: an adhesive mounted between the electrical shield and the one or more capacitors; and one or more ground pads mounted on the motherboard.

For one embodiment of the semiconductor, wherein the electrical shield includes at least one or more metal pads and one or more electrical shield sidewalls, and wherein the one or more metal pads of the electrical shield are coupled with the one or more ground pads of the motherboard.

For one embodiment of the semiconductor, wherein each electrical shield sidewall is attached and perpendicular to at least one of the one or more metal pads.

For one embodiment, the semiconductor package further comprising: a land-side cavity formed on the foundation layer, wherein the land-side cavity resides underneath the foundation layer; and one or more land-side capacitors (LSCs) mounted on the land-side cavity of the foundation layer, wherein the one or more LSCs are mounted above the HiMB of the motherboard and the electrical shield.

For one embodiment of the semiconductor, wherein the HiMB of the motherboard resides below the land-side cavity and the LSCs of the foundation layer.

For one embodiment, the semiconductor package further comprising one or more HiMB sidewalls formed on the HiMB of the motherboard, wherein each of the one or more HiMB sidewalls includes at least one or more plated through holes (PTHs), and wherein each of the one or more PTHs includes an exposed layer.

For one embodiment of the semiconductor, wherein the one or more PTHs are electrically coupled to the one or more capacitors when the one or more capacitors are vertically embedded between the electrical shield sidewalls and the HiMB sidewalls.

For one embodiment, the semiconductor package further comprising: a semiconductor die mounted above the foundation layer and the HiMB of the motherboard, and wherein the foundation layer is attached to the motherboard with a plurality of solder balls.

For one embodiment, the semiconductor package further comprising at least one of a spring mechanism, an assembly handler, and a molding jig.

For some embodiments, a method of forming a semiconductor package, comprising: mounting one or more capacitors on an electrical shield; molding one or more electrical shield sidewalls on the electrical shield, wherein each electrical shield sidewall includes at least one or more metal pads; removing the electrical shield, wherein each electrical shield sidewall is molded perpendicular to the metal pad; and embedding the one or more electrical shield sidewalls of the electrical shield in a HiMB formed in a motherboard, wherein the one or more capacitors are vertically mounted between the one or more electrical shield sidewalls of the electrical shield and the HiMB of the motherboard.

For one embodiment, the method further comprising forming the electrical shield to have at least one or more folding edges prior to mounting the one or more capacitors.

For one embodiment of the method, wherein molding the one or more electrical shield sidewalls further comprises mounting the electrical shield above a molding jig, and applying pressure at least on the one or more folding edges of the electrical shield to mold the one or more electric shield sidewalls using the molding jig.

For one embodiment, the method further comprising: mounting an adhesive between the electrical shield and the one or more capacitors; mounting a foundation layer on the motherboard; and mounting one or more ground pads on the motherboard.

For one embodiment of the method, wherein the one or more metal pads of the electrical shield are coupled with the one or more ground pads of the motherboard.

For one embodiment, the method further comprising: forming a land-side cavity on the foundation layer, wherein the land-side cavity resides underneath the foundation layer; and mounting one or more land-side capacitors (LSCs) on the land-side cavity of the foundation layer, wherein the one or more LSCs are mounted above the HiMB of the motherboard and the electrical shield.

For one embodiment of the method, wherein the HiMB of the motherboard resides below the land-side cavity and the LSCs of the foundation layer.

For one embodiment, the method further comprising forming one or more HiMB sidewalls on the HiMB of the motherboard, wherein each of the one or more HiMB sidewalls includes at least one or more plated through holes (PTHs), and wherein each of the one or more PTHs includes an exposed layer.

For one embodiment of the method, wherein the one or more PTHs are electrically coupled to the one or more capacitors when the one or more capacitors are vertically embedded between the electrical shield sidewalls and the HiMB sidewalls.

For one embodiment, the method further comprising mounting a semiconductor die above the foundation layer and the HiMB of the motherboard; and mounting the foundation layer to the motherboard with a plurality of solder balls.

For one embodiment, the method further comprising at least one of a spring mechanism, and an assembly handler.

For some embodiments, a semiconductor package, comprising: a foundation layer mounted on a motherboard; a hole in motherboard (HiMB) formed in the motherboard; and one or more capacitors mounted on the HiMB, wherein the one or more capacitors are vertically embedded in the HiMB of the motherboard.

For one embodiment, the semiconductor package further comprising: an electrical shield embedded in the HiMB of the motherboard, wherein the one or more capacitors are vertically embedded between the electrical shield and the HiMB of the motherboard; an adhesive mounted between the electrical shield and the one or more capacitors; one or more ground pads mounted on the motherboard; a semiconductor die mounted above the foundation layer and the HiMB of the motherboard, wherein the foundation layer is attached to the motherboard with a plurality of solder balls; and one or more HiMB sidewalls formed on the HiMB of the motherboard, each of the one or more HiMB sidewalls includes at least one or more plated through holes (PTHs), wherein each of the one or more PTHs includes an exposed layer.

For one embodiment of the method, wherein the electrical shield includes at least one or more metal pads and one or more electrical shield sidewalls, wherein the one or more metal pads of the electrical shield are coupled with the one or more ground pads of the motherboard, wherein each electrical shield sidewall is attached and perpendicular to at least one of the one or more metal pads, and wherein each of the one or more PTHs is electrically coupled to the one or more capacitors when the one or more capacitors are vertically embedded between the electrical shield sidewalls and the HiMB sidewalls

For one embodiment, the semiconductor package further comprising: a land-side cavity formed on the foundation layer, wherein the land-side cavity resides underneath the foundation layer; and one or more land-side capacitors (LSCs) mounted on the land-side cavity of the foundation layer, the one or more LSCs are mounted above the HiMB of the motherboard and the electrical shield, wherein the HiMB of the motherboard resides below the land-side cavity and the LSCs of the foundation layer.

In the foregoing specification, methods and apparatuses have been described with reference to specific exemplary embodiments thereof. It will be evident that various modifications may be made thereto without departing from the broader spirit and scope. The specification and drawings are, accordingly, to be regarded in an illustrative sense rather than a restrictive sense.