METHOD OF MANUFACTURING VIAS CROSSING A SUBSTRATE

A method of manufacturing at least one element crossing a substrate, including a step of electrodeposition of at least a portion of said element in an opening crossing the substrate and on a portion of a conductive seed layer located on said at least a portion of a surface of the substrate, said seed layer portion being located on a same side of the opening as said surface of the substrate.

This application claims the priority benefit of French patent application number FR19/09113, the content of which is hereby incorporated by reference in its entirety to the maximum extent allowable by law.

TECHNICAL BACKGROUND

The present disclosure generally concerns electronic devices, and more particularly a device comprising a substrate crossed by conductive vias of connection between electronic circuits.

PRIOR ART

An electronic integrated circuit chip is defined by a substrate and by elements located on a surface, called front side, of the substrate. Among such elements, the chip comprises electronic circuits formed by components such as transistors, resistors, diodes, capacitors, etc., and by electrically-conductive links between the components. One or a plurality of electronic chips may be arranged in an integrated circuit package. Such a package typically comprises pins intended to be connected, for example, welded or soldered, to a device such as a PCB-type printed circuit board.

To electrically couple the electronic circuits of the chips to one another and/or to conductive structures such as the pins of the package, electric connections by conductive vias crossing the substrate of the chips and/or conductive vias crossing one or a plurality of substrates other than those of the chips may be provided.

SUMMARY

There is a need to have a method of forming a substrate crossed by vias having, as compared with current substrates, a higher number of vias per surface area unit.

There is a need to have a via forming method simpler to implement and/or faster than current methods.

An embodiment overcomes all or part of the disadvantages of known via forming methods.

An embodiment provides a method of manufacturing at least one element crossing a substrate, comprising a step of electrodeposition of at least part of said element in an opening crossing the substrate and on a portion of a conductive seed layer located on at least part of a surface of the substrate, said seed layer portion being located on a same side of the opening as said surface of the substrate.

According to an embodiment, the openings have a form factor greater than 10.

According to an embodiment, the seed layer and the substrate are assembled on a support and the conductive seed layer is located between the substrate and a support.

According to an embodiment, a first additional layer located between the support and the seed layer is capable of causing a lighter adhesion of the seed layer to the support than to the substrate.

According to an embodiment, a first additional etch stop layer of the support is located between the support and the seed layer.

According to an embodiment, a second additional adhesion layer of the seed layer is located between the seed layer and the first additional layer.

According to an embodiment, the seed layer and the support are separated by an electric insulator.

According to an embodiment, the support and the seed layer extend laterally beyond the substrate.

According to an embodiment, the walls of the opening are covered with an insulating layer.

According to an embodiment, said insulating layer is formed by thermal oxidation.

According to an embodiment, the method comprises a step of forming of blind cavities in a wafer comprising the future substrate, and a step of removal of a portion of the wafer comprising the bottoms of the cavities.

According to an embodiment, a portion of said insulating layer covering said bottoms of the cavities is left in place at the removal step, another insulating layer is deposited on another surface of the substrate opposite to said surface, and said portion is then removed.

According to an embodiment, an additional seed layer in contact with said seed layer covers at least part of the walls of the openings.

According to an embodiment, the method comprises a step of forming another seed layer on said other insulating layer or on another surface of the substrate opposite to said surface.

According to an embodiment, the electrodeposition step comprises the forming of a solder bump on the crossing element.

DESCRIPTION OF THE EMBODIMENTS

For the sake of clarity, only the steps and elements that are useful for an understanding of the embodiments described herein have been illustrated and described in detail. In particular, electronic integrated circuit chips and their electronic circuits are not described in detail, the described embodiments being compatible with usual integrated circuit chips.

FIG. 1is a simplified cross-section view showing an example of a device100to which the described embodiments apply.

Device100comprises two electronic chips110H and110L located on two opposite surfaces of a connection structure120. Connection structure120interconnects circuits of the chips and ensures the mechanical hold of the chips.

Connection structure120comprises a substrate122. Preferably, substrate122has the shape of a plate or of a wafer having two main opposite surfaces122H and122L. Substrate122is preferably a semiconductor wafer portion, for example, made of silicon. Substrate122may also be made of ceramic or, for example, of glass, or also may comprise an organic material such as epoxy resin, for example, a mixture of epoxy resin and glass fibers. More generally, the substrate may be any plate, wafer, or wafer portion having its two main surfaces capable of being at least partly covered with conductive elements.

Substrate122is crossed by vias124. Preferably, vias124interconnect electrically-conductive regions126L,126H located on the opposite surfaces of substrate122. Although two vias are shown as an example, connection structure120preferably comprises a number of vias greater than 2. Each of vias124is defined by a conductive element crossing substrate122. Each via124electrically connects a conductive region126L located on one of the opposite surfaces (122L) of the substrate to a conductive region126H located on the other one of the opposite surfaces (122H) of the substrate. Conductive regions126H and126L are typically metal regions. Vias124may have the shape of cylinders, of rings, of concentric rings, or shapes filling rectilinear trenches (wall shapes). Vias124typically have shapes elongated in the substrate thickness direction, that is, each via has a larger dimension in the substrate thickness direction (longitudinal direction of the via) than in at least one transverse direction of the via.

Each chip110H,110L comprises connection pads112. Connection pads112are intended to connect electronic circuits (not shown) of the chip to other circuits external to the chip. Such connection pads are typically metal regions located on the front side or on the back side of the chip.

The connection pads112of chips110H and110L are respectively connected to conductive regions126H and126L. More particularly, each connection pad112is in electric contact with one of conductive regions126H and126L, for example, via a solder or welding material130of by direct metal-to-metal bonding. For this purpose, the positions of conductive regions126H and126L correspond to those of connection pads112. Further, material130mechanically fastens connection pads112to conductive regions126H and126L, which enables to ensure the mechanical hold of the chips on connection structure120. In the shown example, the connection pads112of chips110H and110L are located in line with vias124(that is, above and under the vias), however, the chip connection pads are often not located in line with the vias.

Preferably, conductive regions126H and/or126L comprise one or a plurality of connection pads128and tracks129coupling connection pads128to vias124. Although a single connection pad128has been shown, the connection structure preferably comprises a plurality of connection pads128located on one and/or the other of the opposite surfaces122H and122L of substrate122. In an example, device100is intended to be arranged in a package provided with pins, and the connection pads128are intended to be connected to the pins. In another example, connection pads128are intended to connect device100to another device, not shown.

In a variant, connection structure120is formed by an electronic chip. The substrate is then preferably a semiconductor wafer portion, for example, made of silicon.

FIG. 2is a simplified cross-section view showing another example of a device200to which the described embodiments apply.

The device200ofFIG. 2differs from the device100ofFIG. 1in that:chip110L is omitted and conductive regions126L are replaced with connection pads128L intended to be connected, for example, to the pins of a package;a chip110A is located on a portion220deprived of vias of connection structure120, on the side of surface122H; andconductive regions126H comprise tracks coupling the connection pads112of chip110A to vias124.

The devices100and200described hereabove in relation withFIGS. 1 and 2are specific examples, and the embodiments described hereafter apply to any type of device comprising one or a plurality of chips connected to a connection structure120crossed by vias. More generally, the embodiments described hereafter apply to any device comprising a substrate such as substrate122crossed by conductive elements such as vias124.

FIGS. 3 to 5are simplified cross-section views showing steps of an embodiment of a method of manufacturing one or a plurality of conductive elements crossing a substrate322.

Substrate322may be of the type of the substrate122described hereabove in relation withFIGS. 1 and 2. However, preferably, substrate322is a plate, more preferably a semiconductor wafer, intended to be cut into connection structures such as the structures120ofFIGS. 1 and 2and/or into individual chips and/or into any substrate of the type described in relation withFIGS. 1 and 2.

The conductive elements that the method enables to form are preferably vias of the type of the vias124ofFIGS. 1 and 2, or form at least part of vias124. More particularly, the described embodiments comprise a step of electrolytic deposition, or electrodeposition, of at least part of the conductive elements. The electrodeposited material is preferably copper, although the described embodiments also apply to any material currently used for the forming of vias and capable of being electrodeposited, such as nickel, nickel and iron alloys, gold, antimony, or silver.

At the step ofFIG. 3, a stack is formed, which successively comprises (from bottom to top):a support310, typically plate-shaped;a conductive seed layer315, sometimes called nucleation layer, that is, a layer capable of forming a cathode on which the material of the conductive elements may be formed by electrodeposition; andsubstrate322, crossed by openings325located at the locations of the future conductive elements.

Support310is preferably of same nature as substrate322, or support310has a thermal expansion coefficient identical or substantially identical to that of substrate322. This enables to avoid various problems of deformation of the stack during subsequent steps of the method. Such problems would be likely to appear, for example, due to a rise in the temperature of the stack if the substrate and the support do not expand in the same way.

Openings325preferably extend orthogonally to the main surfaces122H and122L of substrate322, in other words, the openings have a side located on the side of surface122H and another side located on the side of surface122L. Openings325are formed at the locations of the future conductive elements such as vias. Openings325preferably have a form factor greater than 10. The form factor of an element such as openings325or the vias is defined by the ratio of the dimension of the element in a longitudinal direction orthogonal to the main surfaces of the substrate to the smallest transverse dimension of the element.

In the stack, substrate322and openings325are located on a same side of seed layer315. In other words, seed layer315has a surface317, facing the substrate, capable of receiving the material of the conductive elements. More precisely, for each of openings325, a portion316of the seed layer closes or seals the opening on the side of the substrate covered with the seed layer (surface122L).

Preferably, layer315is a full layer, that is, comprising no openings, more preferably uniform, that is, of constant thickness. Each portion316then fully seals the corresponding opening325. Layer315enables, as compared with a layer which would be discontinuous and/or non-uniform, to improve the adhesion of the layer and the subsequent filling of openings325by the electrodeposited material.

Preferably, seed layer315is planar, that is, portions316are located in line with seed layer315. However, this is not limiting, and portions316may be located in any position in and/or facing (or vertically in line with) the opening, on the side of the opening facing the support. The seed layer is for example may be made of the same material as that which will be deposited. As an example, the seed layer is a copper layer having a thickness in the range from 100 nm to 2 μm.

The described embodiments are compatible with any method of forming a stack such as that ofFIG. 3. Preferably, support310is previously covered with seed layer315. Openings325may be formed before or after the placing of the substrate on the seed layer315covering support310. Various embodiments of the stack of support310, of seed layer315, and of the substrate322crossed by openings325are described hereafter in relation withFIGS. 6 to 18.

Further, although the assembly of substrate322and of seed layer315is located on a support, this is not limiting, and support310may be omitted. However, the fact of providing support310previously covered with seed layer315eases (or allows, in the case where the substrate is too thin to be handled) the placing and the holding of the seed layer against openings325and surface122L of the substrate, as compared with an embodiment where support310would be omitted.

Preferably, in a peripheral portion of the stack, support310and seed layer315laterally extend beyond substrate322. In other words, a peripheral portion330of seed layer315and of support310protrudes around substrate322. The surface facing substrate322of seed layer315is thus accessible or exposed in peripheral portion330, that is, this surface is not covered with substrate322. As an example, peripheral portion330has a width of approximately 5 mm. Preferably, the substrate and the support are two circular plates having different diameters. As an example, the substrate and the support are obtained from two identical circular plates, for example, semiconductor wafers such as silicon wafers, and a peripheral portion of the plate intended to form substrate322has been removed.

An electric connection350is formed in contact with seed layer315in peripheral portion330. Electric connection350is provided to apply a cathode potential to the seed layer during the implementation of the electrodeposition. Although electric connection350is located on peripheral portion350, this is not limiting, the described embodiments being compatible with any electric connection with seed layer315. In particular, the peripheral portion may be omitted. However, the fact of providing electric connection350in the peripheral portion eases the arranging of the electric connection with respect to a device comprising no peripheral portion330. The support, in particular, its size, is compatible with current electrodeposition equipment.

At the step ofFIG. 4, the material of the conductive elements to be formed is deposited by electrodeposition in openings325. Preferably, the openings are totally filled, which provides vias124crossing substrate322. As a variant, only a portion of the openings is filled with the electrodeposited material, and the rest of the opening may be filled with another conductive material by any usual method.

The electrodeposition is performed by the passing of a current flowing from an anode to seed layer315through an electrolyte. The anode and the electrolyte are neither detailed nor shown, and the parameters of the electrolysis are not described herein, the described embodiments being compatible with usual electrodeposition methods. In particular, the described embodiments are compatible with current techniques used to improve the diffusion of chemical species in the electrolyte, such as stirring, the addition of an accelerating agent, etc.

Due to the fact that the seed layer covers at least part of surface122L, and that the portions316of the seed layer closing openings135are located on the side of surface122L, the current exclusively reaches the seed layer located at the bottom of openings325. At the beginning of the deposition, the metal ions located in the electrolyte are attracted by portions316of the seed layer (taken to the cathode potential). Thus, the deposition increases from the bottom of the openings. In other words, the electrodeposition is performed from the portions316of the seed layer315sealing openings325. In particular, as compared with a method that would use a seed layer covering upper surface122H, the risk for the electrolytic deposition forming on surface122H to close the openings before the complete filling is avoided. Form factors of the vias greater than 10, for example, greater than 20, can thus be simply obtained. In an example, the substrate has a thickness (corresponding to a via height) greater than 200 μm and the vias have widths smaller than 10 μm. In another example, the height of the vias is in the range from 100 to 400 μm and the vias have diameters in the range from 0.5 to 10 μm.

Increasing the form factor of the vias enables, for a given thickness of the substrate, to increase the number of vias per surface area unit of the substrate or, for a given number of vias per surface area unit, to increase the substrate thickness. Once can thus increase the number of vias and/or mechanically reinforce the substrate.

According to an advantage, the obtained vias are blind, that is, totally close openings325. Such blind vias form better electric connections (that is, with a lower electric resistance) than vias which do not totally close the openings, for example, vias having their conductive material covering the walls of the openings but leaving a passage at the center of the openings.

According to another advantage, it can be done without a seed layer on the walls of openings135. Various problems of deposition of this layer when the openings have high form factors, for example, greater than 10, are thus avoided. Further, the described embodiments are compatible with any method, conformal or non-conformal, of forming the seed layer on support310. As an example, the seed layer is formed by chemical or physical vapor deposition CVD or PVD or by ionized physical vapor deposition IPVD. The forming of the seed layer is thus simpler than for a seed layer covering the inner walls of openings135.

At the step ofFIG. 5, conductive regions126H, such as described in relation withFIG. 1, are formed on surface122H of substrate322. Conductive regions126H are preferably formed on an insulator layer, not shown inFIG. 5, crossed by vias124. Preferably, on each via124, one of regions126H covers the end of the via and extends on the substrate around the via. The described embodiments are compatible with usual methods of forming metal regions on the surfaces of a substrate.

Substrate310is then removed. Preferably, seed layer315remains on surface122L of substrate322. As a variant, substrate310is removed before the forming of conductive regions126H.

Conductive regions126L are then formed. As an example, conductive regions126L, such as described in relation withFIG. 1, are formed on surface122L. Preferably, conductive regions126L are portions of seed layer315and of a possible additional conductive layer (not shown) deposited on layer315after the removal of support310. As a variant, the additional layer is deposited on support310before forming seed layer315. A portion of the seed layer and of the possible additional layer are removed, for example, by etching, so that the remaining portions form conductive regions126L. Preferably, for each of vias124, one of regions126L covers the lower end of the via and extends on surface122L of the substrate around the via, and/or one of regions126H covers the upper end of the via and extends on surface122H of the substrate around the via.

Apart from the fact, previously mentioned in relation withFIGS. 1 and 2, that conductive regions126H and126L enable to form conductive tracks and connection pads, conductive regions126H and126L extending on the substrate around the via enable to improve the mechanical resistance of the via in place in the corresponding opening235. Thus, the vias are kept solidly fastened to the substrate. As a variant, the vias are solidly fastened to the substrate without providing regions126H and126L extending on the substrate around each via, for example, by adhesion in the openings.

As an example, at a subsequent step, substrate322is cut along cutting paths360to divide substrate322into individual substrates122.

FIG. 6is a partial simplified cross-section view showing an embodiment of support310covered with seed layer315such as described in relation withFIG. 3. More particularly, in this embodiment, additional layers400,410, and420are interposed, in this order from support310, between support310and seed layer315.

Additional layer400is electrically insulating, for example, layer400is a silicon oxide layer. Additional layer400is preferably in contact with support310. In the case of an electrically-conductive or semiconductor support, for example, made of silicon, the presence of this layer eases the electrolytic deposition, by avoiding for support310to be taken to the cathode potential at the same time as the seed layer. However, layer400may be omitted, in particular in the case where support310is electrically insulating.

Additional layer410is capable of causing a lower adhesion of the seed layer to support310than to substrate322. Layer410enables to remove the support at the step ofFIG. 5by exerting a separation force between the support and the substrate, to break layer410or separate it from layer400and/or from layer420. In an embodiment, layer410is for example made of a thermoplastic-type polymer material, that is, temporary glue. The thickness of layer410is preferably of a few micrometers, for example, in the range from 5 μm to 10 μm. Layer410may be made of any material, for example, metallic, having a sufficiently low energy of adhesion to layer400to be able to separate layers400and410while leaving seed layer315on substrate322. This is not limiting, the described embodiments are compatible with any mode of removal of support310. Thus, in a variant, support310is removed by etching, and additional layer410is omitted or forms an etch stop layer.

As a variant, additional layers400and410are confounded, that is, additional layer410, capable of easing the removal of support310, forms an electric insulation layer.

Additional layer420is made of a material capable of easing the forming and/or the bonding of the seed layer on and/or to layer410. Layer420is for example made of titanium or of titanium nitride. The thickness of layer420is for example in the range from 50 to 200 nm. As a variant, additional layer420is omitted.

FIGS. 7 to 9are simplified cross-section views showing steps of a first embodiment of the step ofFIG. 3. More particularly, in this embodiment, openings325are formed after the arranging of substrate322on support310.

At the step ofFIG. 7, substrate322, for example, a silicon wafer, is arranged on seed layer315covering support310. Preferably, surface122L of the substrate has been previously covered with an electrically-insulating layer510L, for example, made of silicon oxide. For such an arrangement, preferably, a polishing, for example, a chemical-mechanical polishing, of the surface of insulating layer510L (or of substrate322in the absence of layer510L) intended to be in contact with the seed layer and/or of the surface of the seed layer intended to be in contact with insulating layer510L (or with substrate322, surface122L) is previously carried out. Preferably, the surface conditions of the surfaces thus polished provide an adhesion of molecular bonding type between the seed layer and insulating layer510. The bonding is typically obtained by compression and heating.

Preferably, the obtained bonding is sufficient to be tight, in particular towards the electrolyte used at the step ofFIG. 4, over at least 90% of the bonded surface. This is not limiting, and substrate322and seed layer315may, as a variant, be non-tightly assembled, for example, the substrate may be simply laid on the support. However, as compared with such a variant, the tight bonding enables to ease the steps, subsequent to the electrodeposition, of removal of the support and of forming of conductive regions on surface122L from seed layer315.

Preferably, surface122H of the substrate is covered with an insulating layer510H. Insulating layer510H is for example formed at the same time as layer510L, for example, by thermal oxidation. As a variant, the insulating layer is formed after the step ofFIG. 8. In this variant, it may be provided to thin substrate322before the step ofFIG. 8.

At the step ofFIG. 8, a mask520crossed by openings522on the locations of the future openings325is formed by lithography. Openings325are then etched vertically in line with openings522, from the upper surface of layer510H to the level of the upper surface of seed layer315, or to a level located in seed layer315. Openings325cross upper insulating layer510H, substrate322, and insulating layer510L. Seed layer315has exposed or accessible portions316located at the bottom of openings325. The described embodiments are compatible with usual methods of directional etching of insulating and substrate layers.

At the step ofFIG. 9, mask520is removed. The walls of openings325are covered with a layer of electric insulator530, for example, silicon oxide. Insulating layer510H may be totally or partly formed at this step.

Insulating layer530enables to electrically insulate the substrate from the future vias formed in the openings. Further, the insulating layer enables to avoid for the material of the future vias to diffuse towards the substrate and to degrade the properties of the substrate material. Insulating layers510L and510H enable to obtain an electric insulation between the substrate and the future conductive regions126L and126H (FIG. 5) formed on its surfaces122L and122H.

According to a preferred embodiment, electric insulator530is conformally deposited, preferably by a CVD-type method. The thermal budget of such a deposition enables to provide an additional polymer layer, of the type of layer410(FIG. 6), located between support310and seed layer315. Further, the thermal budget of such a deposition is compatible with substrate322in the case where the latter is intended to be cut into individual chips, substrate322then comprising elements of the electronic circuits of the chips. The embodiments described herein are compatible with usual methods of conformal deposition of an insulating layer.

FIGS. 10 to 14are simplified cross-section views showing steps of a second embodiment of the step ofFIG. 3. More particularly, openings325are formed partly before and partly after the arranging of substrate322on support310.

At the step ofFIG. 10, a wafer622where the future substrate322will be defined is provided, for example, a semiconductor wafer such as a silicon wafer.

One then forms, from a surface of the silicon wafer intended to form the future lower surface122L of the future substrate (shown turned over), blind cavities625, that is, cavities which do not emerge onto the surface (surface622H) of wafer622opposite to surface122L.

Preferably, a peripheral portion of wafer622(corresponding to portion330inFIG. 3) is removed. The removal may be performed before or after the forming of cavities625.

After this, an insulating layer630covering all the surfaces of wafer622, as well as the walls and the bottoms of the cavities, is formed. Preferably, insulating layer630is formed by thermal oxidation. Thermal oxidation has the advantage over a deposition method of easing the forming of the insulating layer on the walls of cavities having the high form factors defined hereabove, particularly on the walls of cavities having very high form factors, for example, greater than 15.

At the step ofFIG. 11, wafer622is arranged on seed layer315covering support310. The portion of layer630covering surface122L is placed in contact with the seed layer. Such an arrangement is preferably performed similarly to what described in relation withFIG. 7. In particular, a molecular-type bonding is preferably performed after having performed a polishing of the surfaces to be bonded to each other. As an example, the distance between the bottom of cavities625and surface622H is in the range from 5 to 50 μm, preferably from 10 to 20 μm. Such a distance is, in the shown example, obtained at the step ofFIG. 10, however the distance is preferably obtained by a step, not shown, of thinning of wafer622on the side of its surface622H.

At the step ofFIG. 12, a portion of the wafer comprising the bottoms of the cavities is preferably removed by mechanical polishing. The remaining portion of the wafer forms substrate322. Each of cavities635becomes an openings325crossing the substrate.

Preferably, the removal of the material of the wafer is selective over the material of insulating layer630. Thus, a portion of insulating layer630initially covering the bottoms of cavities625is left in place at the removal step. Preferably, the removal is performed so that portions632of layer630initially located at the bottom of cavities625are located above the upper surface of the substrate (surface122H). The level of surface122H is preferably located at a height h of a few micrometers, for example, between 2 μm and 10 μm, under the lower level of portions632(that is, the level of the surfaces of portions632oriented towards openings325).

As a variant, the portions632of layer630are also removed, and the structure allowing the electrolysis of the step ofFIG. 4is obtained. The removal is for example performed by chemical-mechanical polishing or by dry etching, to avoid damaging the portions of layer630covering the walls of openings325and/or the portions316of the seed layer located under openings325.

At the step ofFIG. 13, another insulating layer (layer640), for example, made of silicon oxide, is deposited on the upper surface122H of the substrate. The portions of layer632enable to avoid for a portion of the material of layer640to be deposited in openings325. Preferably, the thickness of layer640is smaller than height h between surface122H and the lower level of portions632.

At the step ofFIG. 14, all the elements located above the upper level of layer640are removed, preferably by polishing. This removes portions632of insulating layer630. The portions of layer640located on portion632are also removed. Level difference h thus enables to open openings325by polishing, while avoiding damaging the portions of layer630covering the walls of openings325and/or the portions316of the seed layer located under openings325.

The structure obtained at the step ofFIG. 14may be used to perform the electrolysis described in relation withFIG. 4. The portions of layer630located on the walls of the openings enable to electrically insulate the vias or the conductive elements formed on the openings, and further enable to avoid the diffusion towards the substrate322of the material electrodeposited in openings325.

The obtained layer640will enable, in the structure obtained at the step ofFIG. 5, to obtain an electric insulation between conductive regions126H (FIG. 5) and substrate322.

FIG. 15is a simplified cross-section view showing a third embodiment of the step ofFIG. 3. More particularly, openings325are formed before the arranging of substrate322on seed layer315covering support310(support and seed layer not shown inFIG. 15).

At the step ofFIG. 15, openings325are formed in substrate322. The substrate is preferably defined by a semiconductor wafer portion, for example, made of silicon. This embodiment is compatible with any usual way of forming openings in a substrate, such as a chemical or plasma etching, a laser machining, a mechanical machining, a machining by pressurized water, etc.

An insulating layer730covering all the surfaces of substrate322and in particular the walls of openings325is then formed. Insulating layer730is preferably obtained by thermal oxidation, for example at a temperature in the order of 1,000° C. As mentioned, the thermal oxidation enables to form the insulating layer on the walls of openings having high form factors more easily than conformal deposition methods.

In a variant, an insulating layer is formed on upper surface122H and/or an insulating layer is formed on lower surface122L prior to the forming of openings325. The insulating layer(s) are then crossed by the openings. The presence of this layer enables to limit the oxide growth on surfaces122H and122L during the thermal oxidation.

FIGS. 16 and 17are simplified cross-section views showing steps of a fourth embodiment of the step ofFIG. 3.

At the step ofFIG. 16, openings325crossing substrate322are formed. A conductive layer810is then formed on surface122L of the substrate (surface intended to be covered with seed layer135). Conductive layer810is deposited so that a portion812of layer810covers a portion of the walls of openings325on the side of surface122L. This may be obtained by an incompletely uniform deposition, where the deposited material does not reach the portions of openings325most distant from surface122L, in particular due to a high form factor of openings325.

At the step ofFIG. 17, the substrate is arranged on support310. More particularly, layer810and seed layer315are placed in contact with each other, preferably by molecular-type bonding.

Preferably, layer810is made of the same material as the seed layer, or of another material on which the electrolytic deposition may be performed. Metal layer810thus forms an additional seed layer. The portions812of seed layer810are in contact with the portions316of seed layer315and enable to ease the initiation of the electrolytic deposition with respect to an electrodeposition performed without portions812.

Preferably, layer810is formed on a bonding layer, not shown, for example, made of titanium or of titanium nitride. The bonding layer provides a better adhesion of the metal, for example, copper, of layer810. This enables to ensure the mechanical hold between the future via and substrate322. Further, the bonding layer may have barrier properties enabling to avoid the diffusion of the electrodeposited material towards the substrate, and thus enables to avoid for the material of the substrate to be altered by the diffusion.

This embodiment can be combined with the embodiments where the openings or cavities are formed, or partially formed, before the arranging of the substrate on the support, for example, the embodiment ofFIGS. 10 to 14or that ofFIG. 15.

As a variant, layer810entirely covers the walls of openings325.

FIG. 18is a simplified cross-section view showing a step of a fifth embodiment of the step ofFIG. 3.FIG. 19is a simplified cross-section view showing a step similar to that ofFIG. 4after the implementation of the fifth embodiment.

At the step ofFIG. 18, another seed layer (layer850) is formed on upper surface122H of the substrate. Preferably, seed layer850is formed after the forming of openings325. Seed layer850may then, according to the conformity of the deposition, cover substrate322only around the openings or also cover at least part of the walls of the openings. Insulating portions860are then formed on layer850. Insulating portions860are preferably formed at the locations of surface122H which will be, after the implementation of the step ofFIG. 5, deprived of conductive regions126H. As an example, a resist layer, for example, made of dry film resist DFR, is formed so that the resist does not penetrate into cavities325. The resist portions at the locations of the future conductive regions126H are then removed by lithography. The remaining portions of the resist layer form insulating portions860.

At the step ofFIG. 19, vias124are formed by electrodeposition. At the end of the forming of vias124, the latter form an electric contact with seed layer850, and the deposition carries on, on all the seed layer portions which are not covered with portions860. The portions thus deposited will form conductive regions126H after the removal, at the step ofFIG. 5, of the portions of seed layer850located under portions860.

As long as the vias being formed have not reached seed layer850, the deposit only forms from the portions316of seed layer310(from the bottom of the openings). Vias124and conductive regions126H can thus be formed during a same electrolysis step, which simplifies the manufacturing method while benefiting from the above-mentioned advantages, in particular the advantage of forming vias having high form factors without risking closing the upper portions of the cavities before having completely formed the vias.

In an alternative embodiment, portions860are omitted. The electrodeposition is then performed over the entire surface of layer850. At the step ofFIG. 5, the portions of layer850located outside of conductive regions126H are then etched.

The present embodiment is compatible with the previous embodiments, that is, substrate322may correspond to the substrate obtained in the embodiments ofFIGS. 7 to 9, ofFIGS. 10 to 14, ofFIG. 15, and/or ofFIGS. 16 and 17. In particular, seed layer850may be formed on an insulating layer such as layer510H (FIG. 9),640(FIG. 14), or730(FIG. 15).

FIG. 20is a simplified cross-section view showing a variant of the step ofFIG. 5. In this variant, a solder pad910is formed by electrodeposition on each of vias124. For this purpose, the electrodeposition of the material of the vias is continued by the electrodeposition, preferably, of a fusible alloy, for example, a tin-based alloy. The alloy is then only deposited on the tops of vias124. This step may be followed by a melting step enabling to give connection pads910the shape of bumps. This embodiment is compatible with those ofFIGS. 7 to 9, 10 to 14, 15, and/or16and17.

Various embodiments and variants have been described. Those skilled in the art will understand that certain features of these embodiments can be combined and other variants will readily occur to those skilled in the art.