Voltage regulator including compensation circuit and memory device including voltage regulator

A voltage regulator and a memory device including same are provided. The voltage provider includes a resistive circuit configured to output at least one divided voltage; at least one driver circuit configured to be connected to the resistive circuit and to set the at least one divided voltage; and a compensation circuit configured to be connected to the at least one driver circuit, to receive a predetermined voltage, and to apply a power supply voltage to the at least one driver circuit. The at least one driver circuit may set the at least one divided voltage based on the power supply voltage received from the compensation circuit.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims priority from Korean Patent Application No. 10-2011-0070117 filed on Jul. 14, 2011, the disclosure of which is hereby incorporated by reference in its entirety.

BACKGROUND

Apparatuses consistent with the exemplary embodiments relate to a voltage regulator and a memory device including the same, and more particularly, to a voltage regulator for driving both high and low output voltages and having a good power supply rejection ratio (PSRR) and a memory device including the same.

A voltage regulator is a circuit which provides a regulated output voltage with a reference voltage as an input. The voltage regulator is desired to be designed to drive both high and low output voltages and to provide a good PSRR as well. However, related art voltage regulators do not satisfy both conditions.

SUMMARY

According to an aspect of an exemplary embodiment, there is provided a voltage regulator including a resistive circuit configured to output at least one divided voltage; at least one driver circuit configured to be connected to the resistive circuit and to set the at least one divided voltage; and a compensation circuit configured to be connected to the at least one driver circuit, to receive a predetermined voltage, and to apply a power supply voltage to the at least one driver circuit.

The at least one driver circuit may set the at least one divided voltage based on the power supply voltage received from the compensation circuit.

The compensation circuit may include a diode-connected transistor, which has a first terminal, a second terminal, and a gate terminal, the first terminal receives the predetermined voltage, the second terminal and the gate terminal are diode-connected to each other, and the compensation circuit may apply the power supply voltage to the at least one driver circuit through the second terminal and the gate terminal.

The power supply voltage may be lower than the predetermined voltage by a diode forward voltage drop.

The resistive circuit may include at least two resistors connected in series to each other, and at least one of the at least two resistors are connected between the first and second terminals of the at least one transistor of the at least one driver circuit.

A first end of the series of the at least two resistors may be connected to a ground voltage. An output voltage of the voltage regulator may be measured at a second end of the series of the at least two resistors.

The diode-connected transistor may be a p-type metal oxide semiconductor (pMOS) transistor.

The at least one transistor may be an n-type metal oxide semiconductor (nMOS) transistor or a p-type metal oxide semiconductor (pMOS) transistor.

According to another aspect of an exemplary embodiment, there is provided a voltage regulator including a resistive circuit configured to include at least two resistors connected in series to each other and to output a divided voltage of the voltage regulator; at least one pair of metal oxide semiconductor (MOS) transistors, wherein a first MOS transistor of the at least one pair of MOS transistors has a first terminal connected to a first end of a first resistor of the at least two resistors, and a second MOS transistor of the at least one pair of MOS transistors has a second terminal connected to a second end of a second resistor of the at least two resistors; at least one pair of inverters configured to have output terminals connected to respective gates of the at least one pair of MOS transistors; and a diode-connected transistor configured to be connected to the at least one pair of inverters and to have a first terminal receiving a predetermined voltage, a second terminal outputting a power supply voltage to the at least one pair of inverters, and a gate diode-connected to the second terminal.

According to an aspect of another exemplary embodiment, there is provided a memory device including the above-described voltage regulator and a row decoder configured to be connected to the voltage regulator and to select a row in a memory cell array using a voltage output from the voltage regulator.

DETAILED DESCRIPTION

Exemplary embodiments will be described more fully hereinafter with reference to the accompanying drawings. The inventive concept may, however, be embodied in many different forms and should not be construed as limited to the exemplary embodiments set forth herein. Rather, these exemplary embodiments are provided so that this disclosure will be thorough and complete. In the drawings, the size and relative sizes of layers and regions may be exaggerated for clarity. Like numbers refer to like elements throughout.

FIG. 1is a diagram of a voltage regulator100in a comparison example. The voltage regulator100includes an amplifier110, a first transistor TR11and a resistive circuit120. The first transistor TR11may be a p-type metal oxide semiconductor (pMOS) transistor.

The amplifier110receives a reference voltage Vref and a divided voltage Vfb1, which may be determined according to the reference voltage Vref. An output terminal of the amplifier110is connected to a gate of the first transistor TR11.

The first transistor TR11has a terminal connected to a predetermined voltage VDD1and another terminal connected to the resistive circuit120via an output voltage node N1.

The resistive circuit120may include a first resistor R11and a second resistor R12that are connected in series. The divided voltage Vfb1is generated at a node connected between the first and second resistors R11and R12.

The first resistor R11is also connected to a ground voltage and the second resistor R12is connected to the output voltage node N1.

The resistive circuit120may determine the divided voltage Vfb1and an output voltage Vout1based on the reference voltage Vref and a resistance ratio between the first and second resistors R11and R12. For instance, when the reference voltage Vref is 1 V and the resistance ratio,

R⁢⁢11R⁢⁢11+R⁢⁢12,
is 0.5, the divided voltage Vfb1is 1 V and the output voltage Vout1is 2 V.

The resistance value of the first resistor R11may be the same as or different from that of the second resistor R12, which may be depend on a designer's choice.

The two resistors R11and R12are connected in series in the comparison example shown inFIG. 1, but the number of resistors may be changed.

A power supply rejection ratio (PSRR) is defined by Equation 1:

PSRR=20⁢⁢log⁢Δ⁢⁢VDD⁢⁢1Δ⁢⁢Vout⁢⁢1.(Equation⁢⁢1)
According to Equation 1, as the PSRR increases, voltage fluctuation at the output voltage node N1decreases.

In the voltage regulator100illustrated inFIG. 1, when the output voltage Vout1needs to be changed, the resistance of the first and second resistors R11and R12also need to be changed.

FIG. 2is a diagram of a voltage regulator200in another comparison example. Referring toFIG. 2, the voltage regulator200includes a first inverter210, a second inverter220, a first transistor TR21, a second transistor TR22, and a resistive circuit230.

The resistive circuit230includes first through fourth resistors R21, R22, R23and R24. The first and second transistors TR21and TR22may be pMOS transistors.

The first and second inverters210and220receive an input voltage Vin. A divided voltage Vfb2at a first node N21may be determined according to the input voltage Vin.

An output terminal of the first inverter210is connected to a gate of the first transistor TR21and an output of the second inverter220is connected to a gate of the second transistor TR22. The first transistor TR21has a first terminal connected to an output voltage Vout2and a second terminal connected to a first terminal of the second transistor TR22.

The first resistor R21is connected between the first and second terminals of the first transistor TR21. The second resistor R22is connected between the first and second terminals of the second transistor TR22.

The second terminal of the second transistor TR22is also connected to a second node N22. The third resistor R23is connected between the first node N21and the second node N22. The fourth resistor R24is connected between a ground voltage and the first node N21.

Unlike the voltage regulator100illustrated inFIG. 1, the voltage regulator200illustrated inFIG. 2can generate four different voltage levels (e.g., a voltage level of the first node N21, a voltage level of the second node N22, a voltage level of the third node N23, and a voltage level of an output voltage node). In addition, the output voltage Vout2is used as a power supply voltage for the first and second inverters210and220. Accordingly, the voltage regulator200is advantageous in that it does not affect the PSRR.

However, when the output voltage Vout2of the voltage regulator200is very low, for example, when the voltage level of the second node N22is lower than the threshold voltage level of the second transistor TR22, the second transistor TR22may not be switched.

In this case, even when the output voltage Vout2having the voltage level of the second node N22is intended to be obtained, a voltage level greater than the voltage level of the second node N22may be formed for the output voltage Vout2. In other words, the voltage regulator200has difficulty in driving a low voltage. A voltage regulator300illustrated inFIG. 3may address this problem.

FIG. 3is a diagram of the voltage regulator300in a further comparison example. Referring toFIG. 3, the voltage regulator300includes a first inverter310, a second inverter320, a third inverter330, a fourth inverter340, a first transistor TR31, a second transistor TR32, a third transistor TR33, a fourth transistor TR34, and a resistive circuit350.

The resistive circuit350includes first through fourth resistors R31, R32, R33and R34. The first and second transistors TR31and TR32may be pMOS transistors and the third and fourth transistors TR33and TR34may be n-type MOS (nMOS) transistors.

The first through fourth inverters310through340receive an input voltage Vin. According to the input voltage Vin, a divided voltage Vfb3at a first node N31may be determined.

An output terminal of the first inverter310is connected to a gate of the first transistor TR31. An output terminal of the second inverter320is connected to a gate of the second transistor TR32. An output terminal of the third inverter330is connected to a gate of the third transistor TR33. An output terminal of the fourth inverter340is connected to a gate of the fourth transistor TR34.

A first terminal of the first transistor TR31and a first terminal of the third transistor TR33are connected to an output voltage Vout3. A second terminal of the first transistor TR31and a second terminal of the third transistor TR33are respectively connected to a first terminal of the second transistor TR32and a first terminal of the fourth transistor TR34.

The first resistor R31is connected between the first and second terminals of the first transistor TR31. The second resistor R32is connected between the first and second terminals of the second transistor TR32.

The second terminal of the second transistor TR32is also connected to a second node N32. The third resistor R33is connected between the first node N31and the second node N32. The fourth resistor R34is connected between a ground voltage and the first node N31.

A predetermined power supply voltage VDD3is used as a power supply voltage for the first through fourth inverters310through340.

Unlike in the voltage regulator200illustrated inFIG. 2, in the voltage regulator300illustrated inFIG. 3, even when the output voltage Vout3is very low, for example, when the voltage level of the second node N32is lower than the threshold voltage level of the second transistor TR32, the third and fourth transistors TR33and TR34can be switched. Accordingly, when the output voltage Vout3having the voltage level of the second node N32is intended to be obtained, it can be obtained under the same conditions as the voltage regulator200.

However, since the voltage regulator300uses the predetermined power supply voltage VDD3as the power supply voltage for the first through fourth inverters310through340, it deteriorates the PSRR.

FIG. 4is a diagram of a voltage regulator400according to an exemplary embodiment. Referring toFIG. 4, the voltage regulator400includes a first driver circuit405, a second driver circuit407, a compensation circuit460, and a resistive circuit450. The compensation circuit460may include a diode-connected transistor TR_D.

The first driver circuit405includes a first inverter410, a second inverter420, a first transistor TR41, and a second transistor TR42. The second driver circuit407includes a third inverter430, a fourth inverter440, a third transistor TR43, and a fourth transistor TR44.

The resistive circuit450includes a first through fourth resistors R41, R42, R43and R44. The diode-connected transistor TR_D and the first and second transistors TR41and TR42may be pMOS transistors. The third and fourth transistors TR43and TR44may be nMOS transistors. The first through fourth inverters410through440receive an input voltage Vin. A divided voltage Vfb4at a first node N41may be determined according to the input voltage Vin.

An output terminal of the first inverter410is connected to a gate of the first transistor TR41. An output terminal of the second inverter420is connected to a gate of the second transistor TR42. An output terminal of the third inverter430is connected to a gate of the third transistor TR43. An output terminal of the fourth inverter440is connected to a gate of the fourth transistor TR44.

A first terminal of the first transistor TR41and a first terminal of the third transistor TR43are connected to an output voltage Vout4. A second terminal of the first transistor TR41and a second terminal of the third transistor TR43are respectively connected to a first terminal of the second transistor TR42and a first terminal of the fourth transistor TR44.

The first resistor R41is connected between the first and second terminals of the first transistor TR41. The second resistor R42is connected between the first and second terminals of the second transistor TR42.

The second terminal of the second transistor TR42is also connected to a second node N42. The third resistor R43is connected between the first node N41and the second node N42. The fourth resistor R44is connected between a ground voltage and the first node N41.

The diode-connected transistor TR_D has a first terminal connected to a predetermined power supply voltage VDD4and a second terminal and a gate which are connected to each other. A voltage at the second terminal and the gate of the diode-connected transistor TR_D is used as a power supply voltage VDB for the first through fourth inverters410through440.

Unlike in the voltage regulator300illustrated inFIG. 3, in the voltage regulator400illustrated inFIG. 4, a power supply voltage VDB lower than the predetermined power supply voltage VDD4is applied to the first through fourth inverters410through440using the diode-connected transistor TR_D corresponding to a pMOS transistor.

FIG. 5is a diagram of the compensation circuit460according to an exemplary embodiment.FIG. 6is a diagram showing the compensation circuit460illustrated inFIG. 5and capacitances formed at the compensation circuit460.FIG. 7is a diagram of an equivalent circuit of the compensation circuit460illustrated inFIG. 6.

The compensation circuit460is also connected to a logic capacitance Clogicgenerated at logic components (e.g., the first through fourth inverters410through440or the first through fourth transistors TR41through TR44) connected thereto. In detail, the logic capacitance Clogicis connected to a drain of the diode-connected transistor TR_D.

Referring toFIG. 7, the diode-connected transistor TR_D is illustrated as a diode D1and the parasitic capacitances Cgsand Cdsare illustrated together.

For instance, when VDC+Vssin (wt) (where VDCis a direct current (DC) voltage and VSis the amplitude of a sine wave) is applied as the predetermined power supply voltage VDD4, the voltage VDB applied to the first through fourth inverters410through440is given by Equation 2:

Consequently, according to the voltage regulator400illustrated inFIG. 4, a DC voltage level is lower than the predetermined power supply voltage VDD4by the diode forward voltage drop VDFand the amplitude of the sine wave, i.e., voltage fluctuation is reduced. Accordingly, the voltage regulator400improves the PSRR unlike the voltage regulator300illustrated inFIG. 3and can be driven at a low voltage since it has the structure as shown inFIG. 3. The voltage regulator400can also drive (or provide) a high output voltage.

As described above, a voltage regulator according to an exemplary embodiment improves the PSRR and can drive (or provide) a low output voltage as well as a high output voltage.

FIG. 8is a diagram of a non-volatile memory device80according to an exemplary embodiment. The non-volatile memory device80includes a word line voltage generation circuit800, a row decoder820, and a memory cell array830. The word line voltage generation circuit800includes a voltage generator810and the voltage regulator400illustrated inFIG. 4. The voltage generator810applies the predetermined power supply voltage VDD4and the input voltage Vin to the voltage regulator400. The voltage regulator400applies a regulated voltage Vreg to the row decoder820based on those voltages VDD4and Vin.

The row decoder820selects a row in the memory cell array830based on the regulated voltage Vreg and provides the regulated voltage Vreg to the selected row.

The regulated voltage Vreg may be a voltage that has been adjusted to different levels by the voltage regulator400.

Although the voltage regulator400is included in the non-volatile memory device80in the exemplary embodiment illustrated inFIG. 8, the voltage regulator400is not required to be included in the non-volatile memory device80, and may be applied to various fields.