MICROELECTRONIC DEVICES, RELATED ELECTRONIC SYSTEMS, AND METHODS OF FORMING MICROELECTRONIC DEVICES

A microelectronic device comprises a first microelectronic device structure, a second microelectronic device structure vertically neighboring the first microelectronic device structure, and a third microelectronic device structure vertically neighboring the second microelectronic device structure. The first microelectronic device structure comprises a first memory array region and the third microelectronic device structure comprises a second memory array region. The second microelectronic device structure comprises a control logic region comprising a first sub word liner driver region comprising transistor structures in electrical communication with structures of the first microelectronic device structure and a second sub word line driver region comprising additional transistor structures in electrical communication with structures of the third microelectronic device structure. Related microelectronic devices, electronic systems, and methods are also described.

TECHNICAL FIELD

The disclosure, in various embodiments, relates generally to the field of microelectronic device design and fabrication. More specifically, the disclosure relates to methods of forming microelectronic devices from independently formed microelectronic device structures, and to related microelectronic devices and electronic systems.

BACKGROUND

Microelectronic device designers often desire to increase the level of integration or density of features within a microelectronic device by reducing the dimensions of the individual features and by reducing the separation distance between neighboring features. In addition, microelectronic device designers often desire to design architectures that are not only compact, but offer performance advantages, as well as simplified designs.

One example of a microelectronic device is a memory device. Memory devices are generally provided as internal integrated circuits in computers or other electronic devices. There are many types of memory devices including, but not limited to, volatile memory devices, such as dynamic random access memory (DRAM) devices; and non-volatile memory devices such as NAND Flash memory devices. A typical memory cell of a DRAM device includes one access device, such as a transistor, and one memory storage structure, such as a capacitor. Modern applications for semiconductor devices can employ significant quantities of memory cells, arranged in memory arrays exhibiting rows and columns of the memory cells. The memory cells may be electrically accessed through digit lines (e.g., hit lines, data lines) and word lines (e.g., access lines) arranged along the rows and columns of the memory cells of the memory arrays. Memory arrays can be two-dimensional (2D) so as to exhibit a single deck (e.g., a single tier, a single level) of the memory cells, or can be three-dimensional (3D) so as to exhibit multiple decks (e.g., multiple levels, multiple tiers) of the memory cells.

Control logic devices within a base control logic structure underlying a memory array of a memory device have been used to control operations (e.g., access operations, read operations, write operations) of the memory cells of the memory device. An assembly of the control logic devices may be provided in electrical communication with the memory cells of the memory array by way of routing and interconnect structures. However, processing conditions (e.g., temperatures, pressures, materials) for the formation of the memory array over the base control logic structure can limit the configurations and performance of the control logic devices within the base control logic structure. In addition, the quantities, dimensions, and arrangements of the different control logic devices employed within the base control logic structure can also undesirably impede reductions to the size (e.g., horizontal footprint) of the memory device, and/or improvements in the performance (e.g., faster memory cell ON/OFF speed, lower threshold switching voltage requirements, faster data transfer rates, lower power consumption) of the memory device. Furthermore, as the density and complexity of the memory array have increased, so has the complexity of the control logic devices. In some instances, the control logic devices consume more real estate than the memory devices, reducing the memory density of the memory device.

DETAILED DESCRIPTION

The illustrations included herewith are not meant to be actual views of any particular systems, microelectronic structures, microelectronic devices, or integrated circuits thereof, but are merely idealized representations that are employed to describe embodiments herein. Elements and features common between figures may retain the same numerical designation except that, for ease of following the description, reference numerals begin with the number of the drawing on which the elements are introduced or most fully described.

The following description provides specific details, such as material types, material thicknesses, and processing conditions in order to provide a thorough description of embodiments described herein. However, a person of ordinary skill in the art will understand that the embodiments disclosed herein may be practiced without employing these specific details. Indeed, the embodiments may be practiced in conjunction with conventional fabrication techniques employed in the semiconductor industry. In addition, the description provided herein does not form a complete process flow for manufacturing a microelectronic device (e.g., a semiconductor device, a memory device), apparatus, or electronic system, or a complete microelectronic device, apparatus, or electronic system. The structures described below do not form a complete microelectronic device, apparatus, or electronic system. Only those process acts and structures necessary to understand the embodiments described herein are described in detail below. Additional acts to form a complete microelectronic device, apparatus, or electronic system from the structures may be performed by conventional techniques.

The materials described herein may be formed by conventional techniques including, but not limited to, spin coating, blanket coating, chemical vapor deposition (CVD), atomic layer deposition (ALD), plasma enhanced ALD, physical vapor deposition (PVD), plasma enhanced chemical vapor deposition (PECVD), or low pressure chemical vapor deposition (LPCVD). Alternatively, the materials may be grown in situ. Depending on the specific material to be formed, the technique for depositing or growing the material may be selected by a person of ordinary skill in the art. The removal of materials may be accomplished by any suitable technique including, but not limited to, etching, abrasive planarization (e.g., chemical-mechanical planarization), or other known methods unless the context indicates otherwise.

As used herein, the terms “longitudinal,” “vertical,” “lateral,” and “horizontal” are in reference to a major plane of a substrate (e.g., base material, base structure, base construction, etc.) in or on which one or more structures and/or features are formed and are not necessarily defined by Earth's gravitational field. A “lateral” or “horizontal” direction is a direction that is substantially parallel to the major plane of the substrate, while a “longitudinal” or “vertical” direction is a direction that is substantially perpendicular to the major plane of the substrate. The major plane of the substrate is defined by a surface of the substrate having a relatively large area compared to other surfaces of the substrate. With reference to the figures, a “horizontal” or “lateral” direction may be perpendicular to an indicated “Z” axis, and may be parallel to an indicated “X” axis and/or parallel to an indicated “Y” axis; and a “vertical” or “longitudinal” direction may be parallel to an indicated “Z” axis, may be perpendicular to an indicated “X” axis, and may be perpendicular to an indicated “Y” axis.

As used herein, features (e.g., regions, materials, structures, devices) described as “neighboring” one another means and includes features of the disclosed identity (or identities) that are located most proximate (e.g., closest to) one another. Additional features (e.g., additional regions, additional materials, additional structures, additional devices) not matching the disclosed identity (or identities) of the “neighboring” features may be disposed between the “neighboring” features. Put another way, the “neighboring” features may be positioned directly adjacent one another, such that no other feature intervenes between the “neighboring” features; or the “neighboring” features may be positioned indirectly adjacent one another, such that at least one feature having an identity other than that associated with at least one the “neighboring” features is positioned between the “neighboring” features. Accordingly, features described as “vertically neighboring” one another means and includes features of the disclosed identity (or identities) that are located most vertically proximate (e.g., vertically closest to) one another. Moreover, features described as “horizontally neighboring” one another means and includes features of the disclosed identity (or identities) that are located most horizontally proximate (e.g., horizontally closest to) one another.

As used herein, the term “memory device” means and includes microelectronic devices exhibiting memory functionality, but not necessary limited to memory functionality. Stated another way, and by way of example only, the term “memory device” means and includes not only conventional memory (e.g., conventional volatile memory, such as conventional DRAM; conventional non-volatile memory, such as conventional NAND memory), but also includes an application specific integrated circuit (ASIC) (e.g., a system on a chip (SoC)), a microelectronic device combining logic and memory, and a graphics processing unit (GPU) incorporating memory.

As used herein, “conductive material” means and includes electrically conductive material such as one or more of a metal (e.g., tungsten (W), titanium (Ti), molybdenum (Mo), niobium (Nb), vanadium (V), hafnium (Hf), tantalum (Ta), chromium (Cr), zirconium (Zr), iron (Fe), ruthenium (Ru), osmium (Os), cobalt (Co), rhodium (Rh), iridium (Jr), nickel (Ni), palladium (Pa), platinum (Pt), copper (Cu), silver (Ag), gold (Au), aluminum (Al)), an alloy (e.g., a Co-based alloy, an Fe-based alloy, an Ni-based alloy, an Fe- and Ni-based alloy, a Co- and Ni-based alloy, an Fe- and Co-based alloy, a Co- and Ni- and Fe-based alloy, an Al-based alloy, a Cu-based alloy, a magnesium (Mg)-based alloy, a Ti-based alloy, a steel, a low-carbon steel, a stainless steel), a conductive metal-containing material (e.g., a conductive metal nitride, a conductive metal silicide, a conductive metal carbide, a conductive metal oxide), and a conductively doped semiconductor material (e.g., conductively doped polysilicon, conductively doped germanium (Ge), conductively doped silicon germanium (SiGe)). In addition, a “conductive structure” means and includes a structure formed of and including a conductive material.

As used herein, “insulative material” means and includes electrically insulative material, such one or more of at least one dielectric oxide material (e.g., one or more of a silicon oxide (SiOx), phosphosilicate glass, borosilicate glass, borophosphosilicate glass, fluorosilicate glass, an aluminum oxide (AlOx), a hafnium oxide (HfOx), a niobium oxide (NbOx), a titanium oxide (TiOx), a zirconium oxide (ZrOx), a tantalum oxide (TaOx), and a magnesium oxide (MgOx)), at least one dielectric nitride material (e.g., a silicon nitride (SiNy)), at least one dielectric oxynitride material (e.g., a silicon oxynitride (SiOxNy)), and at least one dielectric carboxynitride material (e.g., a silicon carboxynitride (SiOxCzNy)). Formulae including one or more of “x,” “y,” and “z” herein (e.g., SiOx, AlOx, HfOx, NbOx, TiOx, SiNy, SiOxNy, SiOxCzNy) represent a material that contains an average ratio of “x” atoms of one element, “y” atoms of another element, and “z” atoms of an additional element (if any) for every one atom of another element (e.g., Si, Al, Hf, Nb, Ti). As the formulae are representative of relative atomic ratios and not strict chemical structure, an insulative material may comprise one or more stoichiometric compounds and/or one or more non-stoichiometric compounds, and values of “x,” “y,” and “z” (if any) may be integers or may be non-integers. As used herein, the term “non-stoichiometric compound” means and includes a chemical compound with an elemental composition that cannot be represented by a ratio of well-defined natural numbers and is in violation of the law of definite proportions. In addition, an “insulative structure” means and includes a structure formed of and including an insulative material.

As used herein, “semiconductor material” or “semiconductive material” refers to a material having an electrical conductivity between those of insulative materials and conductive materials. For example, a semiconductor material may have an electrical conductivity of between about 10−8Siemens per centimeter (S/cm) and about 104S/cm (106S/m) at room temperature. Examples of semiconductor materials include elements found in column IV of the periodic table of elements such as silicon (Si), germanium (Ge), and carbon (C). Other examples of semiconductor materials include compound semiconductor materials such as binary compound semiconductor materials (e.g., gallium arsenide (GaAs)), ternary compound semiconductor materials (e.g., AlXGa1-XAs), and quaternary compound semiconductor materials (e.g., GaXIn1-XAsYP1-Y), without limitation. Compound semiconductor materials may include combinations of elements from columns III and V of the periodic table of elements (III-V semiconductor materials) or from columns II and VI of the periodic table of elements (II-VI semiconductor materials), without limitation. Further examples of semiconductor materials include oxide semiconductor materials such as zinc tin oxide (ZnxSnyO, commonly referred to as “ZTO”), indium zinc oxide (InxZnyO, commonly referred to as “IZO”), zinc oxide (ZnxO), indium gallium zinc oxide (InxGayZnzO, commonly referred to as “IGZO”), indium gallium silicon oxide (InxGaySizO, commonly referred to as “IGSO”), indium tungsten oxide (InxWyO, commonly referred to as “IWO”), indium oxide (InxO), tin oxide (SnxO), titanium oxide (TixO), zinc oxide nitride (ZnxONx), magnesium zinc oxide (MgxZnyO), zirconium indium zinc oxide (ZrxInyZnzO), hafnium indium zinc oxide (HfxInyZnzO), tin indium zinc oxide (SnxInyZnzO), aluminum tin indium zinc oxide (AlxZnySnzO), silicon indium zinc oxide (SixInyZnzO), aluminum zinc tin oxide (AlxZnySnzO), gallium zinc tin oxide (GaxZnySnzO), zirconium zinc tin oxide (ZrxZnySnzO), and other similar materials.

According to embodiments described herein, a microelectronic device includes a first microelectronic device structure including a first vertical stack of memory cells; a second microelectronic device structure vertically overlying the first microelectronic device structure and including a first control logic device region; and a third microelectronic device structure overlying the second microelectronic device structure and including a second vertical stack of memory cells and a second control logic device region. The first control logic device region includes control logic devices configured for effectuating control logic operations of each of the first vertical stack of memory cells and the second vertical stack of memory cells. In some embodiments, the first control logic device region includes a first sub word line driver region including sub word line drivers for the memory cells of the first microelectronic device structure and a second sub word line driver region including sub word line drivers for the memory cells of the third microelectronic device structure. In some embodiments, the first control logic device region further includes a first sense amplifier device region including sense amplifiers for memory cells of the first microelectronic device structure. The second control logic device region within the third microelectronic device structure may include a second sense amplifier device region including sense amplifiers for the memory cells of the third microelectronic device structure. The second control logic device region may include complementary metal-oxide-semiconductor (CMOS) circuitry and devices for effectuating control logic operations of the memory cells of the first microelectronic device structure and the memory cells of the third microelectronic device structure different than CMOS devices and circuitry of each of the first control logic device region, the second control logic device region, and the third control logic device region. A back end of line (BEOL) structure vertically overlies the third microelectronic device structure.

Forming the microelectronic device to include the second microelectronic device structure including the first control logic device region vertically between the first microelectronic device structure and the third microelectronic device structure may facilitate forming the microelectronic device to exhibit a reduced horizontal area (e.g., footprint) and an increased memory density compared to conventional microelectronic devices. For example, the vertical stacks of memory cells of the first microelectronic device structure and the third microelectronic device structure may be formed to include a greater number of levels of memory cells. Placing some of the control logic devices within the first control logic device region of the second microelectronic device structure and other control logic devices within the second control logic device region of the third microelectronic device structure facilitates forming a greater density of memory cells compared to conventional microelectronic devices.

FIG.1AthroughFIG.1Eare a simplified partial top-down view (FIG.1A) and simplified partial cross-sectional views (FIG.1BthroughFIG.1E) illustrating a first microelectronic device structure100to be included in a microelectronic device (e.g., a memory device, such as a 3D DRAM memory device) of the disclosure, in accordance with embodiments of the disclosure. With the description provided below, it will be readily apparent to one of ordinary skill in the art that the methods and structures described herein with reference toFIG.1AthroughFIG.1Emay be used in various devices and electronic systems. The first microelectronic device structure100may also be referred to herein as a first die or a first wafer.

FIG.1Ais a simplified partial top-down view of the first microelectronic device structure100;FIG.1Bis a simplified partial cross-sectional view of the first microelectronic device structure100taken through section line B-B ofFIG.1A;FIG.1Cis a simplified partial cross-sectional view of the first microelectronic device structure100taken through section line C-C ofFIG.1A;FIG.1Dis a simplified partial cross-sectional view of the first microelectronic device structure100taken through section line D-D ofFIG.1A; andFIG.1Eis a simplified partial cross-sectional view of the first microelectronic device structure100taken through section line E-E ofFIG.1A.

Referring toFIG.1A, the first microelectronic device structure100includes a first array region101(also referred to herein as a “first memory array region”) and one or more peripheral regions103located external to the first array region101. In some embodiments, the peripheral regions103horizontally (e.g., in at least X-direction) surround the first array region101. In some embodiments, the peripheral regions103substantially surround all horizontal sides of the first array region101in a first horizontal direction (e.g., the X-direction). In other embodiments, the peripheral regions103substantially surround all horizontal boundaries (e.g., an entire horizontal area) of the first array region101.

The peripheral region103may include, for example, socket regions104including one or more first conductive interconnect structures182(FIG.1A,FIG.1E) for forming electrical connections between the first microelectronic device structure100and an additional microelectronic device structure (e.g., third microelectronic device structure300FIG.3AthroughFIG.3D). In some embodiments, at least some of the socket regions104may individually be horizontally neighbored (e.g., in the Y-direction) by a first conductive contact exit region102.

The socket regions104may electrically connect circuitry of the first microelectronic device structure100to BEOL structures of an additional microelectronic device structure (e.g., the third microelectronic device structure300(FIG.3A)), to input/output devices, or both.

The first conductive contact exit regions102may horizontally neighbor (e.g., in the Y-direction) the socket regions104and horizontally neighbor (e.g., in the X-direction) the first array region101. In other embodiments, the first conductive contact exit regions102may not be horizontally neighbored (e.g., in the Y-direction) by any of the socket regions104. In some such embodiments, the first conductive contact exit regions102may horizontally extend (e.g., in the Y-direction) substantially an entire length (e.g., in the Y-direction) of the first microelectronic device structure100.

The first conductive contact exit regions102may be formed to include first conductive contact structures176for electrically connecting one or more components of the first microelectronic device structure100to circuitry of a second microelectronic device structure (e.g., second microelectronic device structure200(FIG.2A)).

In some embodiments, each of the first conductive contact exit regions102exhibits about a same size (e.g., horizontal area in the XY plane) as each of the other of the first conductive contact exit regions102. In other embodiments, at least some of the first conductive contact exit region102have a different size than other of the first conductive contact exit regions102. In some embodiments, first conductive contact exit regions102at horizontal ends (e.g., in the Y-direction) of the first microelectronic device structure100may have a smaller horizontal area (e.g., in the XY plane) than first conductive contact exit region102between horizontal ends (e.g., in the Y-direction) of the first microelectronic device structure100.

Second conductive contact exit regions106may horizontally neighbor (e.g., in the X-direction) the socket regions104and the first conductive contact exit regions102. In some embodiments, the second conductive contact exit regions106are located at horizontal ends (e.g., in the Y-direction) of the first array region101. The second conductive contact exit regions106may include second conductive contact structures190for electrically connecting one or more components of the first microelectronic device structure100(e.g., global digit lines108) to circuitry of a second microelectronic device structure (e.g., the second microelectronic device structure200(FIG.2A)) or a third microelectronic device structure (e.g., the third microelectronic device structure300(FIG.3A)).

Each of the second conductive contact exit regions106may exhibit about a same size (e.g., horizontal area in the XY plane) as the other of the second conductive contact exit regions106. In some embodiments, one or more (e.g., each) of the second conductive contact exit regions106exhibits a different size than one or more of (e.g., each of) the first conductive contact exit regions102.

With collective reference toFIG.1AandFIG.1B, global digit lines108(also referred to as “conductive lines,” “global bit lines,” or “bit lines”) horizontally extend (e.g., in the Y-direction) through the first array region101and horizontally terminate in the second conductive contact exit region106. The global digit lines108include first global digit lines108A and second global digit lines108B. The first global digit lines108A may be referred to herein as “through global digit lines” and the second global digit lines108B may be referred to herein as “reference global digit lines.” The first global digit lines108A and the second global digit lines108B may collectively be referred to herein as “global digit lines.” In some embodiments, the first global digit lines108A are located on a first horizontal end (e.g., in the Y-direction) of the first microelectronic device structure100and the second global digit lines108B are located on a second horizontal end (e.g., in the Y-direction) of the first microelectronic device structure100opposite the first horizontal end. For example, in the view illustrated inFIG.1A, the first global digit lines108A may be located in the upper horizontal half (e.g., in the Y-direction) of the first array region101and the second global digit lines108B may be located in a lower horizontal half (e.g., in the Y-direction) of the first array region101.

Each of the global digit lines108and the second conductive contact structures190may individually be formed of and include conductive material, such as, for example, one or more of a metal (e.g., tungsten, titanium, nickel, platinum, rhodium, ruthenium, aluminum, copper, molybdenum, iridium, silver, gold), a metal alloy, a metal-containing material (e.g., metal nitrides, metal silicides, metal carbides, metal oxides), a material including at least one of titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), titanium aluminum nitride (TiAlN), iridium oxide (IrOx), ruthenium oxide (RuOx), alloys thereof, a conductively doped semiconductor material (e.g., conductively doped silicon, conductively doped germanium, conductively doped silicon germanium, etc.), polysilicon, or other materials exhibiting electrical conductivity. In some embodiments, the global digit lines108and the second conductive contact structures190individually comprise tungsten. In other embodiments, the global digit lines108and the second conductive contact structures190individually comprise copper.

With reference toFIG.1AandFIG.1B, within the first array region101, the first microelectronic device structure100includes vertical (e.g., in the Z-direction) stacks of memory cells120over a first base structure110. Each vertical stack of memory cells120comprises a vertical stack of access devices130and a vertical stack of storage devices150, the storage devices150of the vertical stack of storage devices150coupled to the access devices130of the vertical stack of access devices130. The vertical stacks of memory cells120may individually include vertically spaced (e.g., in the Z-direction) levels of memory cells120, each memory cell120individually comprising a storage device150horizontally neighboring an access device130. AlthoughFIG.1Aillustrates forty (40) vertical stacks of memory cells120(e.g., five (5) rows and eight (8) columns of the vertical stacks of memory cells120), the disclosure is not so limited, and the first array region101may include greater than forty vertical stacks of memory cells120.

The first base structure110may include a conventional silicon substrate (e.g., a conventional silicon wafer), or another bulk substrate comprising a semiconductive material. As used herein, the term “bulk substrate” means and includes not only silicon substrates, but also silicon-on-insulator (SOI) substrates, such as silicon-on-sapphire (SOS) substrates and silicon-on-glass (SOG) substrates, epitaxial layers of silicon on a base semiconductive foundation, and other substrates formed of and including one or more semiconductive materials (e.g., one or more of a silicon material, such monocrystalline silicon or polycrystalline silicon; silicon-germanium; germanium; gallium arsenide; a gallium nitride; and indium phosphide). In some embodiments, the first base structure110comprises a silicon wafer.

In some embodiments, the first base structure110includes different layers, structures, devices, and/or regions formed therein and/or thereon. In some embodiments, the first base structure110does not include complementary metal-oxide-semiconductor (CMOS) circuitry and devices configured for effectuating operation of the vertical stacks of memory cells120of the first microelectronic device structure100. By way of non-limiting example, the first base structure110may not include sense amplifier devices (also referred to as “sense amplifiers” herein), sub word line driver devices, column select devices, or row select devices configured for effectuating operation of the memory cells120of the first microelectronic device structure100. In some embodiments, the first base structure110is substantially free of control logic devices and is substantially free of CMOS circuitry and devices.

Referring now toFIG.1B, the first base structure110may be electrically isolated from the vertical stacks of memory cells120by a first insulative material112vertically intervening (e.g., in the Z-direction) between the first base structure110and the vertical stacks of memory cells120. The first insulative material112may be formed of and include insulative material such as, for example, one or more of an oxide material (e.g., silicon dioxide (SiO2), phosphosilicate glass, borosilicate glass, borophosphosilicate glass, fluorosilicate glass, titanium dioxide (TiO2), hafnium oxide (HfO2), zirconium dioxide (ZrO2), hafnium dioxide (HfO2), tantalum oxide (TaO2), magnesium oxide (MgO), aluminum oxide (Al2O3), or a combination thereof), and amorphous carbon. In some embodiments, the first insulative material112comprises silicon dioxide.

As described above, each vertical stack of memory cells120comprises a vertical stack of access devices130and a vertical stack of storage devices150. Each of the access devices130may individually be operably coupled to a conductive structure132(FIG.1AthroughFIG.1C) of a stack structure135(FIG.1C) comprising levels of the conductive structures132(also referred to herein as “first conductive lines,” “access lines,” or “word lines”) vertically (e.g., in the Z-direction) spaced from one another by one or more insulative structures137.

The access devices130may each individually comprise a channel material134between a source material136and a drain material138. The channel material134may be horizontally (e.g., in the X-direction) between the source material136and the drain material138. The source material136and the drain material138may each individually comprise a semiconductive material (e.g., polysilicon) doped with at least one N-type dopant, such as one or more of arsenic ions, phosphorous ions, and antimony ions. In other embodiments, the source material136and the drain material138each individually comprise a semiconductive material doped with at least one P-type dopant, such as boron ions.

In some embodiments, the channel material134comprises a semiconductive material (e.g., polysilicon) doped with at least one N-type dopant or at least one P-type dopant. In some embodiments, the channel material134is doped with one of at least one N-type dopant and at least one P-type dopant and each of the source material136and the drain material138are each individually doped with the other of the at least one N-type dopant and the at least one P-type dopant.

With collective reference toFIG.1AandFIG.1C, the conductive structures132may extend horizontally (e.g., in the X-direction) through the vertical stacks of memory cells120as lines and may each be configured to be operably coupled to a vertically (e.g., in the Z-direction) neighboring channel material134of the vertically neighboring (e.g., in the Z-direction) access devices130. In other words, a conductive structure132may be configured to be operably coupled to a vertically neighboring access device130.

The conductive structures132may be configured to provide sufficient voltage to a channel region (e.g., channel material134) of each of the access devices130to electrically couple a horizontally neighboring (e.g., in the Y-direction) and associated storage device150to, for example, a conductive pillar structure (e.g., conductive pillar structure160) vertically extending (e.g., in the Z-direction) through the vertical stack of access devices130of the vertical stack of memory cells120. The stack structure135including the vertically spaced conductive structures132may intersect the vertical stacks of memory cells120, such as the vertical stacks of the access devices130of the vertical stacks of memory cells120, each of the conductive structures132of the stack structure135intersecting a level (e.g., a tier) of the memory cells120of the vertical stack of memory cells120. With reference toFIG.1A, each stack structure135individually extends through several vertical stacks of access devices130of the vertical stack of memory cells120. In some embodiments, each stack structure135extends through horizontally neighboring (e.g., in the X-direction) vertical stacks of memory cells120. In some embodiments, the stack structures135extending in a first horizontal direction (e.g., in the X-direction) are spaced from each other in a second horizontal direction (e.g., in the Y-direction).

AlthoughFIG.1AandFIG.1Billustrate that the conductive structures132of the stack structure135individually intersect five (5) and form portions of the vertical stacks of memory cells120, the disclosure is not so limited. In other embodiments, conductive structures132of the stack structure135individually intersect and form portions of fewer than five (5) of the vertical stacks of memory cells120, such as four (4) of the vertical stacks of the memory cells120. In other embodiments, conductive structures of the stack structure135individually intersect and form portions of more than five (5) of the vertical stacks of the memory cells120, such as more than six (6) of the vertical stacks of memory cells120, more than eight (8) of the vertical stacks of memory cells120, more than ten (10) of the vertical stacks of the memory cells120, more than twelve (12) of the vertical stacks of the memory cells120, more than sixteen (16) of the vertical stacks of the memory cells120, or more than twenty (20) of the vertical stacks of the memory cells120.

The conductive structures132may individually be formed of and include conductive material, such as one or more of the materials described above with reference to the global digit lines108. In some embodiments, the conductive structures132are individually formed of and include tungsten. In other embodiments, the conductive structures132are individually formed of and include copper.

Referring toFIG.1B, the channel material134may be separated from the conductive structures132by a dielectric material140, which may also be referred to herein as a “gate dielectric material.” The dielectric material140may be formed of and include insulative material. By way of non-limiting example, the dielectric material140may comprise one or more of phosphosilicate glass, borosilicate glass, borophosphosilicate glass (BPSG), fluorosilicate glass, silicon dioxide, titanium dioxide, zirconium dioxide, hafnium dioxide, tantalum oxide, magnesium oxide, aluminum oxide, niobium oxide, molybdenum oxide, strontium oxide, barium oxide, yttrium oxide, a nitride material, (e.g., silicon nitride (Si3N4)), an oxynitride (e.g., silicon oxynitride, another gate dielectric material, a dielectric carbon nitride material (e.g., silicon carbon nitride (SiCN))), or a dielectric carboxynitride material (e.g., silicon carboxynitride (SiOCN)). In other embodiments, the channel material134directly contacts a vertically neighboring conductive structure132.

In some embodiments, insulative structures137and additional insulative structures139vertically (e.g., in the Z-direction) intervene between vertically neighboring access devices130and vertically neighboring storage devices150. The additional insulative structures139may horizontally (e.g., in the Y-direction) neighbor each of the conductive structures132. With reference toFIG.1C, the levels of the conductive structures132vertically alternate with the levels of the insulative structures137. For clarity and ease of understanding the description, inFIG.1C, the levels of the insulative structures137are illustrated as comprising an integral structure. In other embodiments, the levels of the insulative structures137may exhibit distinct boundaries at interfaces of the levels of the conductive structures132.

The insulative structures137may individually be formed of and include insulative material. In some embodiments, the insulative structures137may each individually be formed of and include, for example, an insulative material, such as one or more of an oxide material (e.g., silicon dioxide (SiO2), phosphosilicate glass, borosilicate glass, borophosphosilicate glass, fluorosilicate glass, titanium dioxide (TiO2), hafnium oxide (HfO2), zirconium dioxide (ZrO2), hafnium dioxide (HfO2), tantalum oxide (TaO2), magnesium oxide (MgO), aluminum oxide (Al2O3), or a combination thereof), and amorphous carbon. In some embodiments, the insulative structures137comprise silicon dioxide. Each of the insulative structures137may individually include a substantially homogeneous distribution of the at least one insulating material, or a substantially heterogeneous distribution of the at least one insulating material. As used herein, the term “homogeneous distribution” means amounts of a material do not vary throughout different portions (e.g., different horizontal portions, different vertical portions) of a structure. Conversely, as used herein, the term “heterogeneous distribution” means amounts of a material vary throughout different portions of a structure. Amounts of the material may vary stepwise (e.g., change abruptly), or may vary continuously (e.g., change progressively, such as linearly, parabolically) throughout different portions of the structure. In some embodiments, each of the insulative structures137exhibits a substantially homogeneous distribution of insulative material. In additional embodiments, at least one of the insulative structures137exhibits a substantially heterogeneous distribution of at least one insulative material. The insulative structures137may, for example, be formed of and include a stack (e.g., laminate) of at least two different insulative materials. The insulative structures137may each be substantially planar, and may each individually exhibit a desired thickness.

The additional insulative structures139may be formed of and include an insulative material that is different than, and that has an etch selectivity with respect to, the insulative structures137. In some embodiments, the additional insulative structures139are formed of and include a nitride material (e.g., silicon nitride (Si3N4)) or an oxynitride material (e.g., silicon oxynitride). In some embodiments, the additional insulative structures139comprise silicon nitride. In other embodiments, the additional insulative structures139comprise substantially the same material composition as the insulative structures137. In some embodiments, the additional insulative structures139comprise silicon dioxide.

In some embodiments, the storage devices150are in electrical communication with a conductive structure142(not illustrated inFIG.1Afor clarity and ease of understanding the description). The conductive structure142may be formed of and include conductive material, such as one or more of the materials of an electrode (e.g., a second electrode154) of the storage devices150. In some embodiments, the conductive structure142comprises substantially the same material composition as an electrode of the storage devices150. In other embodiments, the conductive structure142comprises a different material composition than the electrodes of the storage devices150. The conductive structures142may be referred to herein as “conductive plates” or “ground structures.”

With continued reference toFIG.1B, one of the storage devices150is illustrated in enlarged box155. In some embodiments, each of the storage devices150individually comprises a first electrode152(also referred to herein as an “outer electrode,” “a first electrode plate,” or a “first node structure”), a second electrode154(also referred to herein as an “inner electrode,” “a second electrode plate,” or a “second node structure”), and a dielectric material156between the first electrode152and the second electrode154. In some such embodiments, the storage devices150individually comprise capacitors. However, the disclosure is not so limited and in other embodiments, the storage devices150may each individually comprise other structures, such as, for example, phase change memory (PCM), resistance random-access memory (RRAM), conductive-bridging random-access memory (conductive bridging RAM), or another structure for storing a logic state.

The first electrode152may be formed of and include conductive material such as, for example, one or more of a metal (e.g., tungsten, titanium, nickel, platinum, rhodium, ruthenium, aluminum, copper, molybdenum, iridium, silver, gold), a metal alloy, a metal-containing material (e.g., metal nitrides, metal silicides, metal carbides, metal oxides), a material including at least one of titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), titanium aluminum nitride (TiAlN), iridium oxide (IrOx), ruthenium oxide (RuOx), alloys thereof, a conductively doped semiconductor material (e.g., conductively doped silicon, conductively doped germanium, conductively doped silicon germanium), polysilicon, and other materials exhibiting electrical conductivity. In some embodiments, the first electrode152comprises titanium nitride.

The second electrode154may be formed of and include conductive material. In some embodiments, the second electrode154comprises one or more of the materials described above with reference to the first electrode152. In some embodiments, the second electrode154comprises substantially the same material composition as the first electrode152.

The second electrode154may be in electrical communication with one of the conductive structures142of a vertical stack of memory cells120. In some embodiments, the conductive structures142are individually formed of conductive material, such as one or more of the materials of the second electrode154. In some embodiments, the conductive structures142comprise substantially the same material composition as the second electrode154. In other embodiments, the conductive structures142comprise a different material composition than the second electrode154.

With continued reference toFIG.1AandFIG.1B, the first microelectronic device structure100may include conductive pillar structures160vertically (e.g., in the Z-direction) extending through the first microelectronic device structure100. The conductive pillar structures160may also be referred to herein as “digit lines,” “second conductive lines,” “digit line pillar structures,” “local digit lines,” or “vertical digit lines.” The conductive pillar structures160may be electrically coupled to the access devices130to facilitate operation of the memory cells120of a vertical stack of memory cells120. Stated another way, each conductive pillar structure160vertically extends through access devices130of a vertical stack of memory cells120. In some embodiments, each vertical stack of memory cells120includes one of the conductive pillar structures vertically extending (e.g., in the Z-direction) the vertical stack of memory cells120(e.g., through the vertical stack of access devices130of the memory cells120).

In some, the conductive pillar structures160in horizontally neighboring (e.g., in the Y-direction) stack structures135are horizontally aligned (e.g., in the X-direction) with each other. In other embodiments, conductive pillar structures160in horizontally neighboring (e.g., in the Y-direction) stack structures135are horizontally aligned (e.g., in the X-direction) with each other.

The conductive pillar structures160may individually be formed of and include conductive material, such as one or more of a metal (e.g., one or more of tungsten, titanium, nickel, platinum, rhodium, ruthenium, aluminum, copper, molybdenum, iridium, silver, gold), a metal alloy, a metal-containing material (e.g., metal nitrides, metal silicides, metal carbides, metal oxides), a material including at least one of titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), titanium aluminum nitride (TiAlN), iridium oxide (IrOx), ruthenium oxide (RuOx), alloys thereof, a conductively doped semiconductor material (e.g., conductively doped silicon, conductively doped germanium, conductively doped silicon germanium, etc.), polysilicon, or other materials exhibiting electrical conductivity. In some embodiments, the conductive pillar structures160comprise tungsten.

With reference still toFIG.1B, in some embodiments, each global digit line108(FIG.1A,FIG.1B) may be in electrical communication with one or more global digit line contact structures162that are, in turn, individually in electrical communication with a conductive structure164to selectively couple the respective global digit line108to one of the conductive pillar structures160through a multiplexer166, illustrated in box168. In some embodiments, the multiplexers166may facilitate selective provision of a voltage to a conductive pillar structure160to which it is electrically connected (by means of the global digit line contact structure162) and selective provision of a voltage of one of the conductive pillar structures160to the global digit line108through the multiplexer166. In other words, the global digit lines108are configured to be selectively electrically connected to the conductive pillar structures160by means of the multiplexers166. Accordingly, the global digit lines108are configured to be selectively electrically connected to each conductive pillar structure160vertically extending (e.g., in the Z-direction) through a vertical stack of memory cells120by applying a voltage to the multiplexer166electrically connecting the global digit line108to the particular conductive pillar structure160by means of the global digit line contact structure162and the conductive structures164between the global digit line108and the multiplexer166associated with the particular conductive pillar structure. The multiplexers166may be driven by a multiplexer driver and/or a multiplexer control logic device operably coupled to the conductive structure132to which the multiplexer166is coupled (e.g., the conductive structure132vertically above (e.g., in the Z-direction) the multiplexer166). For example, and as described in further detail herein, the multiplexers166may be coupled to one or more structures (e.g., transistor structures) within a multiplexer controller region of, for example, the first base structure110. In some embodiments, the multiplexers166are individually configured to receive a signal (e.g., a select signal) from a multiplexer controller region and provide the signal to a bit line (e.g., conductive pillar structures160(FIG.1B)) to selectively access desired memory cells within the first array region101for effectuating one or more control operations of the memory cells120.

Each global digit line108may be configured to be selectively coupled to more than one of the conductive pillar structures160by means of the multiplexers166coupled to each of the conductive pillar structures160. In some embodiments, each global digit line108is configured to selectively be in electrical communication with four (4) of the conductive pillar structures160. In other embodiments, each of the global digit lines108is configured to selectively be in electrical communication with eight (8) of the conductive pillar structures160or sixteen (16) of the conductive pillar structures160. One of the multiplexers166may be located between (e.g., horizontally between) a conductive pillar structure160and a horizontally neighboring conductive structure164that is, in turn, in electrical communication with a global digit line108by means of a global digit line contact structure162.

In some embodiments, the global digit line contact structures162and the conductive structures164individually comprise a conductive material, such as a material exhibiting a relatively low resistance value to facilitate an increased speed (e.g., low RC delay) of data transmission. In some embodiments, the global digit line contact structures162and the conductive structures164individually comprise copper. In other embodiments, the global digit line contact structures162and the conductive structures164individually comprise tungsten. In yet other embodiments, the global digit line contact structures162and the conductive structures164individually comprise titanium nitride.

The global digit lines108and at least a portion of each of the global digit line contact structures162may be formed within a second insulative material180vertically (e.g., in the Z-direction) overlying the vertical stacks of memory cells120. The second insulative material180may be formed of and include one or more of the materials described above with reference to the first insulative material112. In some embodiments, the second insulative material180comprises substantially the same material composition as the first insulative material112. In some embodiments, the second insulative material180comprises silicon dioxide.

In some embodiments, an access device130vertically (e.g., in the Z-direction) neighboring (e.g., vertically above) the multiplexer166may comprise a transistor170, one of which is illustrated in box171, configured to electrically couple a horizontally neighboring (e.g., in the X-direction) conductive pillar structure160to the conductive structure142through an additional conductive structure172. The transistor170may comprise a so-called “bleeder” transistor or a “leaker” transistor configured to provide a bias voltage to the conductive pillar structures160to which it is coupled (e.g., the horizontally neighboring (e.g., in the X-direction) conductive pillar structures160). In some embodiments, the conductive structure132coupled to the transistors170may be in electrical communication with a voltage, such as a drain voltage Vddor a voltage source supply Vss. In use and operation, the transistors170are configured to provide a negative voltage to the conductive pillar structures160of unselected (e.g., inactive) vertical stacks of memory cells120. In other words, the transistors170are configured to electrically connect unselected conductive pillar structures160with their respective conductive structures142(e.g., ground structures, cell plates), which may be coupled to a negative voltage. In some embodiments, each vertical stack of memory cells120includes at least one (e.g., one) of the multiplexers166and at least one (e.g., one) of the transistors170.

The additional conductive structure172may comprise one or more of the conductive materials described above with reference to the conductive structures164. In some embodiments, the additional conductive structure172comprises substantially the same material composition as the conductive structure164. In some embodiments, the additional conductive structure172comprises copper. In other embodiments, the additional conductive structure172comprises tungsten. In yet other embodiments, the additional conductive structure172comprises titanium nitride.

With reference toFIG.1BandFIG.1C, in some embodiments, the global digit lines108may be located vertically above (e.g., in the Z-direction) the stack structures135and the vertical stacks of memory cells120. In some embodiments, the global digit lines108are vertically spaced from the first base structure110a greater vertical distance than the vertical stacks of memory cells120.

With reference toFIG.1AandFIG.1C, the conductive structures132of the stack structure135may horizontally (e.g., in the X-direction) terminate at staircase structures174located at horizontally (e.g., in the X-direction) terminal portions of the stack structure135. While the staircase structures174are illustrated inFIG.1A, it will be understood that the staircase structures174are located beneath a vertically upper (e.g., in the Z-direction) surface of the first microelectronic device structure100. With reference toFIG.1C, vertically higher (e.g., in the Z-direction) conductive structures132may have a smaller horizontal dimension (e.g., in the X-direction) than vertically lower conductive structures132, such that horizontal edges of the conductive structures132at least partially define steps175of the staircase structures174. In some embodiments, the memory cells120of the vertical stack of memory cells120that are vertically higher (e.g., in the Z-direction) than other memory cells120comprise and are intersected by conductive structures132having a smaller horizontal dimension (e.g., in the X-direction) than conductive structures132of vertically lower memory cells120of the vertical stacks of memory cells120. In some embodiments, a horizontal dimension (e.g., in the X-direction) of the conductive structures132of the multiplexers166may be less than a horizontal dimension (e.g., in the X-direction) of the conductive structures132of the transistors170, which may be less than a horizontal dimension (e.g., in the X-direction) of the conductive structures132intersecting the memory cells120.

The staircase structures174may be located within the first conductive contact exit regions102(FIG.1A) of the peripheral regions103(FIG.1A). With reference toFIG.1A, in some embodiments, the staircase structures174of each of the stack structures135are horizontally aligned in a first direction (e.g., in the X-direction) and horizontally offset in a second direction (e.g., the Y-direction). In some such embodiments, the staircase structure174of each stack structure135may be located at a first horizontal end (e.g., in the X-direction) of the first microelectronic device structure100.

In other embodiments, the staircase structures174of horizontally neighboring (e.g., in the Y-direction) stack structures135may be located at opposing horizontal ends (e.g., in the X-direction) of the first microelectronic device structure100. In some such embodiments, every other stack structure135includes a staircase structure174at a first horizontal end (e.g., in the X-direction) of the first microelectronic device structure100while the other of the stack structures135individually include a staircase structure174at a second horizontal end (e.g., in the X-direction) of the first microelectronic device structure100opposite the first horizontal end. Stated another way, the staircase structures174of horizontally neighboring (e.g., in the Y-direction) stack structures135may alternate between a first horizontal end (e.g., in the X-direction) of the first microelectronic device structure100and a second horizontal end (e.g., in the X-direction) of the first microelectronic device structure100, the second horizontal end opposing the first horizontal end.

AlthoughFIG.1Aillustrates one staircase structure174for every stack structure135(e.g., a staircase structure174at one horizontal end (e.g., in the X-direction) of each stack structure135), the disclosure is not so limited. In other embodiments, the stack structures135may include one staircase structure174at each horizontal end (e.g., in the X-direction) of the stack structure135. In some such embodiments, each of the stack structures135individually includes two (2) staircase structures174.

The quantity of the steps175may correspond to the quantity of the levels of memory cells120of the vertical stack (minus one level for the multiplexers166and one level for the transistors170). AlthoughFIG.1AandFIG.1Cillustrate that the staircase structures174individually comprise a particular number (e.g., five (5)) steps175, the disclosure is not so limited. In other embodiments, the staircase structures174each individually include a desired quantity of the steps175, such as within a range from thirty-two (32) of the steps175to two hundred fifty-six (256) of the steps175. In some embodiments, the staircase structures174each individually include sixty-four (64) of the steps175. In other embodiments, the staircase structures174each individually include ninety-six (96) or more of the steps175. In some such embodiments, each vertical stack of memory cells120of the first microelectronic device structure100individually includes a corresponding quantity memory cells120(e.g., minus one memory cell120for the multiplexer166and one memory cell120for the transistor170). In other embodiments, the staircase structures174each individually include a different number of the steps175, such as less than sixty-four (64) of the steps175(e.g., less than or equal to sixty (60) of the steps175, less than or equal to fifty (50) of the steps175, less than about forty (40) of the steps175, less than or equal to thirty (30) of the steps175, less than or equal to twenty (20) of the steps175, less than or equal to ten (10) of the steps175); or greater than sixty-four (64) of the steps175(e.g., greater than or equal to seventy (70) of the steps175, greater than or equal to one hundred (100) of the steps175, greater than or equal to about one hundred twenty-eight (128) of the steps175, greater than two hundred fifty-six (256) of the steps175).

With continued reference toFIG.1AandFIG.1C, first conductive contact structures176may be in electrical communication with individual conductive structures132at the steps175. For example, the first conductive contact structures176may individually physically contact (e.g., land on) portions of upper surfaces of the conductive structures132at least partially defining treads of the steps175. In some embodiments, each step175may be in electrical communication with a first conductive contact structure176at the horizontal (e.g., in the X-direction) end of the staircase structure174. In other embodiments, every other step175of the staircase structures174may include a first conductive contact structure176in contact therewith. In other words, every other step175of the staircase structures174may individually be in contact with a first conductive contact structure176. In some such embodiments, each stack structure135may include one staircase structure174at each horizontal (e.g., in the X-direction) end thereof and each step175of a first staircase structure174at a first horizontal end of the stack structure135not in electrical communication with a first conductive contact structure176may individually be in electrical communication with a first conductive contact structure176at a second staircase structure174at a second, opposite horizontal end of the stack structure135.

The first conductive contact structures176may individually be formed of and include conductive material, such as one or more of the materials described above with reference to the conductive pillar structures160. In some embodiments, the first conductive contact structures176comprise substantially the same material composition as the conductive pillar structures160. In other embodiments, the first conductive contact structures176comprise a different material composition than the conductive pillar structures160. In some embodiments, the first conductive contact structures176comprise tungsten.

First pad structures178may vertically overlie and individually be in electrical communication with of the first conductive contact structures176. Each of the first conductive contact structures176is individually in electrical communication with one of the first pad structures178. The first pad structure178may be formed within the second insulative material180.

The first pad structures178are individually formed of and include conductive material, such as one or more of the materials described above with reference to the global digit lines108. In some embodiments, the first pad structures178are formed of and include tungsten. In other embodiments, the first pad structures178are formed of and include copper.

FIG.1Dis a simplified partial cross-sectional view of the first microelectronic device structure100taken through section line D-D ofFIG.1Aand horizontally spaced (e.g., in the Y-direction) from the cross-sectional view ofFIG.1C. The cross-section ofFIG.1Dis taken through the storage devices150and does not illustrate the access devices130(FIG.1C) or the conductive structures132(FIG.1A,FIG.1C).

With reference toFIG.1E, one or more first conductive interconnect structures182vertically extend (e.g., in the Z-direction) through the insulative structures137and the first insulative material112to contact the first base structure110. In some embodiments, the socket region104includes one or more of the first conductive interconnect structures182.

The first conductive interconnect structures182may individually be formed of and include conductive material, such as, for example, one or more of the materials described above with reference to the global digit lines108. In some embodiments, the first conductive interconnect structures182individually comprise tungsten.

Second pad structures184may individually vertically overlie and individually be in electrical communication with individual first conductive interconnect structures182. The second pad structures184may be located within the second insulative material180.

The second pad structures184may be formed of and include conductive material, such as one or more of the materials of the first pad structures178. In some embodiments, the second pad structures184individually comprise substantially the same material composition as the first pad structures178. In some embodiments, the second pad structures184are formed of and include tungsten. In other embodiments, the second pad structures184are formed of and include copper.

With collective reference toFIG.1BthroughFIG.1E, the second insulative material180vertically overlies the first microelectronic device structure100. As described in further detail herein, the second insulative material180may facilitate attaching (e.g., bonding) the first microelectronic device structure100to a second microelectronic device structure (e.g., the second microelectronic device structure200(FIG.2A)).

FIG.2Ais a simplified partial top-down view of a second microelectronic device structure200;FIG.2Bis a simplified partial cross-sectional view of the second microelectronic device structure200taken through section line B-B ofFIG.2A;FIG.2Cis a simplified partial cross-sectional view of the second microelectronic device structure200taken through section line C-C ofFIG.2A;FIG.2Dis a simplified partial cross-sectional view of the second microelectronic device structure200taken through section line D-D ofFIG.2A; andFIG.2Eis a simplified partial cross-sectional view of the second microelectronic device structure200taken through section line E-E ofFIG.2A. With reference toFIG.2A, in some embodiments, the second microelectronic device structure200exhibits substantially the same horizontal cross-sectional area as the first microelectronic device structure100(FIG.1A). The second microelectronic device structure200may also be referred to herein as a second die or a second wafer.

The second microelectronic device structure200may include one or more control logic devices (e.g., CMOS devices) and circuitry. With reference toFIG.2A, the second microelectronic device structure200may include one or more sub word line driver regions202, one or more socket regions204, and one or more additional CMOS regions206including one or more of (e.g., all of) one or more sense amplifier devices (e.g., equalization (EQ) amplifiers, isolation (ISO) amplifiers, NMOS sense amplifiers (NSAs), PMOS sense amplifiers (PSAs)), column decoders, multiplexer control logic devices, sense amplifier drivers, main word line driver devices, row decoder devices, and row select devices. The one or more socket regions204may be formed to include one or more interconnect devices to electrically connect the socket regions104(FIG.1A) of the first microelectronic device structure100(FIG.1A) to one or more devices of a third microelectronic device structure (e.g., third microelectronic device structure300(FIG.3A)).

The one or more sub word line driver regions202may be configured to be electrically coupled to the memory cells120(FIG.1B) of the first microelectronic device structure100(FIG.1B). The one or more sub word line driver regions202may be configured to be vertically above (e.g., in the Z-direction) (e.g., directly vertically above) and within horizontal boundaries of the first conductive contact exit regions102of the first microelectronic device structure100, such as within horizontal boundaries of the staircase structures174(FIG.1A,FIG.1C).

In some embodiments, as described in further detail below, the sub word line driver regions202may include sub word line driver devices including transistor structures that are electrically coupled to the first pad structures178(FIG.1C) in electrical communication with the first conductive contact structures176(FIG.1C), that are, in turn, electrically coupled to one of the conductive structures132. Each sub word line driver of the sub word line driver regions202may be, in turn, electrically coupled to a main word line driver by electrical connections. In some embodiments, the main word line drivers are located within the sub word line driver regions202and are horizontally offset (e.g., in the Y-direction) from the sub word line drivers. In other embodiments, the main word line drivers are located within the additional CMOS regions206and are horizontally offset (e.g., in the X-direction) from the sub word line drivers.

The main word line driver devices may be coupled to row decoder devices. The row decoder devices may be configured to receive an address signal from, for example, an address decoder and send a signal to a horizontally neighboring main word line driver. In some embodiments, the row decoder devices are located within the additional CMOS regions206and are horizontally offset (e.g., in the X-direction, in the Y-direction) from the main word line driver devices. In other embodiments, the row decoder devices are located within the sub word line driver regions202.

The sense amplifier devices of the additional CMOS region206may include, for example, one or more of equalization (EQ) amplifiers, isolation (ISO) amplifiers, NMOS sense amplifiers (NSAs) (also referred to as N sense amplifiers), and PMOS sense amplifiers (PSAs) (also referred to as P sense amplifiers).

As described in further detail below, the additional CMOS region206is configured to be vertically above (e.g., in the Z-direction) (e.g., directly vertically above) and within horizontal boundaries of the second conductive contact exit regions106of the first microelectronic device structure100such that sense amplifiers of the additional CMOS region206are vertically above (e.g., in the Z-direction) (e.g., directly vertically above) the global digit lines108. In some embodiments, the sense amplifier devices of the additional CMOS region206are electrically coupled to the second conductive contact structures190(FIG.1A) without horizontally (e.g., in the X-direction, in the Y-direction) rerouting (e.g., by way of intervening, conductive routing structures) the second conductive contact structures190to electrically connect the sense amplifiers of the additional CMOS region206to the global digit lines108.

In some embodiments, the one or more additional CMOS regions206comprises one or more column decoder devices. The column decoder devices are individually in electrical communication with one or more components of a horizontally neighboring (e.g., in the X-direction, in the Y-direction) sense amplifier device region of the additional CMOS region206. The column decoder devices may each individually be configured to receive an address signal from, for example, an address decoder and send a signal to a horizontally neighboring sense amplifier of the additional CMOS region206.

The additional CMOS region206may further include sense amplifier drivers (also referred to as “sense amplifier driver devices”) horizontally neighboring (e.g., in the X-direction, in the Y-direction) the sense amplifiers of the additional CMOS region206. The sense amplifier drivers may be electrically coupled to the sense amplifiers by way of conductive structures.

The sense amplifier drivers of the additional CMOS region206may include NMOS sense amplifier drivers (RNL) and PMOS sense amplifier drivers (ACT). The NMOS sense amplifier drivers may generate, for example, activation signals for driving the NMOS sense amplifiers of the sense amplifiers of the additional CMOS region206and the PMOS sense amplifier drivers may generate, for example, activation signals for driving the PMOS sense amplifiers of the sense amplifiers of the additional CMOS region206. By way of non-limiting example, NMOS sense amplifier drivers generate a low potential (e.g., ground) activation signal for activating an NMOS sense amplifier of the sense amplifiers and the PMOS sense amplifier drivers generate a high potential (e.g., Vcc) activation signal for activating a PMOS sense amplifier of the sense amplifiers. However, the disclosure is not so limited and the NMOS sense amplifier drivers and the PMOS sense amplifier drivers may generate sense amplifier activation signals other than those described.

In some embodiments, the additional CMOS region206includes multiplexer control logic devices configured for effectuating operation of the multiplexers166(FIG.1B). In some embodiments, the conductive structures132(FIG.1B) associated with the multiplexers166may be in electrical communication with circuitry of the multiplexer control logic devices for selectively electrically coupling a conductive pillar structure160(FIG.1B) associated with a multiplexer166to a global digit line108(FIG.1B).

The cross-sectional view ofFIG.2Billustrates the additional CMOS region206, the cross-sectional view ofFIG.2Cillustrates the sub word line driver region202, and the additional CMOS region206; and the cross-sectional view ofFIG.2Dillustrates the sub word line driver region202and the additional CMOS region206. With collective reference toFIG.2BthroughFIG.2D, the second microelectronic device structure200includes a first control logic device region205including the sub word line driver region202and the additional CMOS region206.

Each of the sub word line driver region202and the additional CMOS region206individually include transistor structure210for forming the control logic devices of the sub word line driver region202(e.g., sub word line drivers and, optionally, main word line drivers and row decoders) and control logic devices of the additional CMOS region206(e.g., sense amplifiers, column decoders, sense amplifier drivers, multiplexer control logic, and, optionally, main word line drivers and row decoders).

The transistor structures210may be separated from one another by isolation trenches212within a second base structure214(e.g., a second semiconductive wafer). The second base structure214may include a base material or construction upon which additional materials and structures of the second microelectronic device structure200are formed. The second base structure214may comprise a semiconductive structure (e.g., a semiconductive wafer), or a base semiconductive material on a supporting structure. For example, the second base structure214may comprise a conventional silicon substrate (e.g., a conventional silicon wafer), or another bulk substrate comprising a semiconductive material. In some embodiments, the second base structure214comprises a silicon wafer. In addition, the second base structure214may include one or more layers, structures, and/or regions formed therein and/or thereon.

The transistor structures210may each include conductively doped regions216, each of which includes a source region216A and a drain region216B. Channel regions of the transistor structures210may be horizontally interposed between the conductively doped regions216. In some embodiments, the conductively doped regions216of each transistor structure210individually comprises one or more semiconductive materials doped with at least one conductivity enhancing chemical species, such as at least one N-type dopant (e.g., one or more of arsenic, phosphorous, antimony, and bismuth) or at least one P-type dopant (e.g., one or more of boron, aluminum, and gallium). In some embodiments, the conductively doped regions216comprise conductively doped silicon.

The transistor structures210include gate structures218vertically overlying the second base structure214and horizontally extending between conductively doped regions216. The gate structures218may be horizontally aligned (e.g., in the Y-direction) with and shared by the channel regions of multiple transistor structures210horizontally neighboring (e.g., in the X-direction (FIG.2A)) one another. In some such embodiments, the gate structures218extend in a first horizontal direction (e.g., in the Y-direction). In addition, dielectric material (also referred to herein as a “gate dielectric material”) may be vertically interposed between the gate structures218and portions of the second base structure214at least partially defining the channel regions of the transistor structures210. The conductively doped regions216and the gate structures218may individually be electrically coupled to second conductive interconnect structures220. The second conductive interconnect structures220may individually electrically couple the conductively doped regions216and the gate structures218to one or more first routing structures222. InFIG.2B, the conductively doped regions216and the second conductive interconnect structures220in electrical communication with the conductively doped regions216are not illustrated, but it will be understood, that the conductively doped regions216and the second conductive interconnect structures220are located in a plane different than that in which the gate structures218extend. By way of non-limiting example, each gate structure218may be in electrical communication with a plurality of source regions216A on a first side of the gate structure218(e.g., spaced from the gate structure218in the X-direction) and a plurality of drain regions216B on a second, opposite side of the gate structure218(e.g., spaced from the gate structure218in the X-direction opposite the source regions216A). At least some of the first routing structures222(e.g., the first routing structures222not in electrical communication with the second conductive interconnect structures220in electrical communication with the gate structure218) may be in electrical communication with second conductive interconnect structures220that are, in turn, in electrical communication with one of the source regions216A or one of the drain regions216B, as illustrated inFIG.2CandFIG.2D.

Each of the gate structures218, the second conductive interconnect structure220, and the first routing structures222may individually be formed of and include conductive material. In some embodiments, the gate structures218, the second conductive interconnect structure220, and the first routing structures222are individually formed of and include tungsten. In other embodiments, the gate structures218, the second conductive interconnect structure220, and the first routing structures222are individually formed of and include copper.

The second microelectronic device structure200may include a third insulative material224between the transistor structures210and electrically isolating different portions of the transistor structures210, the second conductive interconnect structures220, and the first routing structures222.

The third insulative material224may be formed of and include one or more of the materials described above with reference to the first insulative material112(FIG.1B,FIG.1C). In some embodiments, the third insulative material224comprises substantially the same material composition as the first insulative material112. In some embodiments, the third insulative material224comprises silicon dioxide.

A fourth insulative material226vertically overlies the third insulative material224and the first routing structures222. The fourth insulative material226may be formed of and include one or more of the materials described above with reference to the third insulative material224. In some embodiments, the fourth insulative material226comprises substantially the same material composition as the third insulative material224. In some embodiments, the fourth insulative material226comprises a different material composition than the third insulative material224. In some embodiments, the fourth insulative material226comprises silicon dioxide.

FIG.2Eis a simplified partial cross-sectional view of the second microelectronic device structure200taken through section line E-E ofFIG.2A. With reference toFIG.2E, in some embodiments, the socket regions204include the third insulative material224vertically overlying (e.g., in the Z-direction) the second base structure214; and the fourth insulative material226vertically overlying the third insulative material224.

Referring now toFIG.2FthroughFIG.2I, a carrier wafer assembly230may be bonded to the second microelectronic device structure200and the second microelectronic device structure200may be vertically (e.g., in the Z-direction) inverted (e.g., flipped).FIG.2Fillustrates the same cross-sectional view of the second microelectronic device structure200illustrated inFIG.2B;FIG.2Gillustrates the same cross-sectional view of the second microelectronic device structure200illustrated inFIG.2C;FIG.2Hillustrates the same cross-sectional view of the second microelectronic device structure200illustrated inFIG.2D; andFIG.2Iillustrates the same cross-sectional view of the second microelectronic device structure200illustrated inFIG.2E.

The carrier wafer assembly230may include a wafer structure232and a fifth insulative material234over the wafer structure232. The wafer structure232may comprise, for example, a glass substrate. The fifth insulative material234may comprise an oxide material, such as, for example, silicon dioxide. In some embodiments, the fifth insulative material234comprises substantially the same material composition as the fourth insulative material226.

The carrier wafer assembly230may be attached to the second microelectronic device structure200by placing the fifth insulative material234in contact with the fourth insulative material226and exposing the second microelectronic device structure200and the carrier wafer assembly230to annealing conditions to form bonds (e.g., oxide-to-oxide bonds) between the fifth insulative material234in contact with the fourth insulative material226. In some embodiments, the second microelectronic device structure200and the carrier wafer assembly230are exposed to a temperature greater than, for example, 800° C., to form the oxide-to-oxide bonds and attach the second microelectronic device structure200to the carrier wafer assembly230.

After attaching the carrier wafer assembly230to the second microelectronic device structure200, the second microelectronic device structure200may be vertically (e.g., in the Z-direction) inverted (e.g., flipped) and the second base structure214may be vertically (e.g., in the Z-direction) thinned by exposing the second base structure214to a chemical mechanical planarization (CMP) process. In other embodiments, the second base structure214is vertically thinned by exposing the second base structure214to a dry etch. Vertically thinning the second base structure214may electrically isolate the transistor structures210from one another.

After vertically thinning the second base structure214, a sixth insulative material236is formed over the second microelectronic device structure200. The sixth insulative material236may be formed of and include one or more of the materials described above with reference to the third insulative material224. In some embodiments, the sixth insulative material236comprises silicon dioxide.

Referring now toFIG.2JthroughFIG.2M, the second microelectronic device structure200may be vertically (e.g., in the Z-direction) inverted (e.g., flipped) and attached to the first microelectronic device structure100to form a first microelectronic device structure assembly250comprising the first microelectronic device structure100and the second microelectronic device structure200attached to the first microelectronic device structure100.FIG.2Jillustrates the same cross-sectional view of the first microelectronic device structure100and the second microelectronic device structure200illustrated inFIG.1BandFIG.2F, respectively;FIG.2Killustrates the same cross-sectional view of the first microelectronic device structure100and the second microelectronic device structure200illustrated inFIG.1CandFIG.2G, respectively;FIG.2Lis a simplified partial cross-sectional view of the first microelectronic device structure100and the second microelectronic device structure200illustrated inFIG.1DandFIG.2H, respectively; andFIG.2Millustrates the same cross-sectional view of the first microelectronic device structure100and the second microelectronic device structure200illustrated inFIG.1EandFIG.2I, respectively.

In some embodiments, the second microelectronic device structure200is flipped (e.g., vertically flipped), and the sixth insulative material236of the second microelectronic device structure200is bonded to the second insulative material180of the first microelectronic device structure100to attach the first microelectronic device structure100to the second microelectronic device structure200and form the first microelectronic device structure assembly250. After attaching the second microelectronic device structure200to the first microelectronic device structure100, the carrier wafer assembly230may be removed from the second microelectronic device structure200.

With collective reference toFIG.2JthroughFIG.2M, after attaching the second microelectronic device structure200to the first microelectronic device structure100, at least some of the transistor structures210of the second microelectronic device structure200may be electrically connected to components of the first microelectronic device structure100. With reference toFIG.2J, third conductive interconnect structures252may be formed in electrical communication with the first routing structures222that are, in turn, electrically coupled to the transistors structures210vertically overlying (e.g., in the Z-direction) the global digit lines108within horizontal boundaries (e.g., in the X-direction, in the Y-direction) of the vertical stacks of memory cells120. The third conductive interconnect structures252may be formed vertically (e.g., in the Z-direction) through the fourth insulative material226.

Fourth conductive interconnect structures254may be formed in electrical communication with the global digit lines108vertically underlying (e.g., in the Z-direction) the second microelectronic device structure200. The fourth conductive interconnect structures254may vertically extend through the fourth insulative material226, the third insulative material224, the sixth insulative material236, and the second insulative material180. In some embodiments, the fourth conductive interconnect structures254are located in a different plane than the conductive structures218such that the fourth conductive interconnect structures254do not electrically short to the conductive structures218and are, therefore, illustrated in broken lines in the view ofFIG.2J.

In some embodiments, the fourth conductive interconnect structures254are electrically connected to the third conductive interconnect structures252by means of second routing structures256horizontally extending (e.g., in the Y-direction) between the fourth conductive interconnect structures254and the third conductive interconnect structures252.

In some embodiments, the first control logic device region205comprises a first sense amplifier device region262including transistor structures210forming the sense amplifier devices of the one or more additional CMOS regions206. In some embodiments, the transistor structures210of the first sense amplifier device region262are vertically (e.g., in the Z-direction) over the global digit lines108and located within horizontal boundaries (e.g., in the X-direction, in the Y-direction) of the first array region101(FIG.1A), such as within horizontal boundaries of the stacks of memory cells120. In some embodiments, the sense amplifier devices of the sense amplifier device region262are in electrical communication with the global digit lines108by means of the third conductive interconnect structures252, the second routing structures256, and the fourth conductive interconnect structures254. In some embodiments, each sense amplifier device of the first sense amplifier device region262is in electrical communication with one of the first global digit lines108A and one of the second global digit lines108B. In use and operation (e.g., such as during a read operation of the memory cells120), the sense amplifier devices of the first sense amplifier device region262are configured to amplify a signal (e.g., a difference in voltage) between the first global digit line108A and the second global digit line108B to which the sense amplifier device is connected.

In some embodiments, the first sense amplifier device region262further comprises transistor structures210forming column select devices and/or one or more additional control logic devices (e.g., row decoders, column decoders) that are in electrical communication with the sense amplifiers of the first sense amplifier device region262, such as by means of fifth conductive interconnect structures264and third routing structures266.

Each of the third conductive interconnect structures252, the fourth conductive interconnect structures254, and the second routing structures256may be formed of and include conductive material, such as one or more of the materials described above with reference to the first conductive interconnect structures182. In some embodiments, each of the third conductive interconnect structures252, the fourth conductive interconnect structures254, and the second routing structures256are individually formed of and include tungsten. In other embodiments, each of the third conductive interconnect structures252, the fourth conductive interconnect structures254, and the second routing structures256are individually formed of and include copper.

The third conductive interconnect structures252, the fourth conductive interconnect structures254, and the second routing structures256may be formed within a seventh insulative material258. The seventh insulative material258may include one or more of the materials described above with reference to the first insulative material112. In some embodiments, the seventh insulative material258comprises silicon dioxide.

With continued reference toFIG.2J, the sense amplifier devices of the first sense amplifier device region262may also be in electrical communication with sense amplifier driver circuitry (e.g., NMOS sense amplifier drivers (RNL) and PMOS sense amplifier drivers (ACT)) by means of the fifth conductive interconnect structures264and the third routing structures266.

Each of the fifth conductive interconnect structures264and the third routing structures266are individually be formed of and include conductive material, such as one or more of the materials described above with reference to the first conductive interconnect structures182. In some embodiments, each of the fifth conductive interconnect structures264and the third routing structures266are individually formed of and include tungsten. In other embodiments, each of the fifth conductive interconnect structures264and the third routing structures266are individually formed of and include copper.

With reference toFIG.2KandFIG.2L, transistors structures210vertically overlying (e.g., in the Z-direction) the staircase structures174(e.g., the steps175of the staircase structures174) may be located within the sub word line driver region202. With reference toFIG.2K, some of the transistor structures210may be in electrical communication with the first pad structures178of the first microelectronic device structure100and with reference toFIG.2L, others of the transistor structures210may not be in electrical communication with the first pad structures178of the first microelectronic device structure100and may be configured to be in electrical communication with pad structures of a third microelectronic device structure (e.g., third microelectronic device structure300) to be formed vertically (e.g., in the Z-direction) over the second microelectronic device structure200of the first microelectronic device structure assembly250. Accordingly, in some embodiments, the second microelectronic device structure200includes first sub word line driver regions202A (FIG.2K) including transistor structures210in electrical communication with the conductive structures132of the first microelectronic device structure100and second sub word line driver regions202B (FIG.2L) horizontally neighboring (e.g., in the Y-direction) the first sub word line driver regions202A and configured to be in electrical communication with conductive structures of a third microelectronic device structure to be formed vertically over the second microelectronic device structure200. In some embodiments, the first pad structures178in electrical communication with the conductive structures132connected to the multiplexers166and the first pad structures178in electrical communication with the conductive structures132connected to the transistors170are individually in electrical communication with transistor structures210that form a portion of a multiplexer controller.

With reference toFIG.2KandFIG.2L, the first sub word line driver region202A (FIG.2K) may be located within the horizontal boundaries (e.g., in the X-direction, in the Y-direction) of the staircase structure174(FIG.2K) and the second sub word line driver regions202B (FIG.2L) may be horizontally spaced (e.g., in the Y-direction) from the staircase structures174and may not be located within horizontal boundaries (e.g., in the X-direction, in the Y-direction) of the staircase structure174.

With continued reference toFIG.2KandFIG.2L, sixth conductive interconnect structures268may be in electrical communication with the first routing structures222of the transistor structures210within the first sub word line driver region202A (FIG.2K) and the transistor structures210within the second sub word line driver region202B (FIG.2L). The sixth conductive interconnect structures268may be in electrical communication with fourth routing structures270.

Each of the sixth conductive interconnect structures268and the fourth routing structures270may individually be formed of and include conductive material, such as one or more of the materials described above with reference to the first conductive interconnect structures182. In some embodiments, each of the sixth conductive interconnect structures268and the fourth routing structures270are individually formed of and include tungsten. In other embodiments, each of the sixth conductive interconnect structures268and the fourth routing structures270are individually formed of and include copper.

Referring toFIG.2K, the fourth routing structures270within the first sub word line driver region202A are in electrical communication with seventh conductive interconnect structures272that are, in turn, in electrical communication with the first pad structures178in electrical communication with the conductive structures132of the first microelectronic device structure100.

Referring toFIG.2L, the fourth routing structures270within the second sub word line driver region202B are in electrical communication with eighth conductive interconnect structures274that are, in turn, in electrical communication with third pad structures276. As described in further detail below, the third pad structures276are configured to be in electrical communication with portions of a third microelectronic device structure (e.g., the third microelectronic device structure300) to be formed vertically over the second microelectronic device structure200of the first microelectronic device structure assembly250.

Each of the eighth conductive interconnect structures274and the third pad structures276are individually formed of and include conductive material, such as one or more of the materials described above with reference to the first conductive interconnect structures182. In some embodiments, each of the eighth conductive interconnects structures274and the third pad structures276are individually formed of and include tungsten. In other embodiments, each of the eighth conductive interconnects structures274and the third pad structures276are individually are individually formed of and include copper.

Each of the sixth conductive interconnect structures268, the fourth routing structures270, the seventh conductive interconnect structures272, the eighth conductive interconnect structures274, and the third pad structures276may be formed within the seventh insulative material258.

With continued reference toFIG.2L, a vertical height H (e.g., in the Z-direction) between of the eighth conductive interconnect structures274and the third pad structures276may be within a range of from about 200 nm to about 500 nm, such as from about 200 nm to about 300 nm, from about 300 nm to about 400 nm, or from about 400 nm to about 500 nm.

Referring toFIG.2M, within the socket region204, one or more ninth conductive interconnect structures278may be formed through each of the seventh insulative material258, the fourth insulative material226, the third insulative material224, the sixth insulative material236, and the second insulative material180. A fourth pad structure280may individually be formed vertically over (e.g., in the Z-direction) each of the ninth conductive interconnect structures278.

Each of the ninth conductive interconnect structures278and the fourth pad structures280may individually be formed of and include conductive material, such as one or more of the materials described above with reference to the first conductive interconnect structures182. In some embodiments, each of the ninth conductive interconnect structures278and the fourth pad structures280are individually formed of and include tungsten. In other embodiments, each of the ninth conductive interconnect structures278and the fourth pad structures280are individually formed of and include copper.

FIG.3AthroughFIG.3Dare simplified partial cross-sectional views illustrating a third microelectronic device structure300, in accordance with embodiments of the disclosure. Components of the third microelectronic device structure300that are similar to corresponding components of the first microelectronic device structure100may retain the same numerical designation, except that reference numerals 1XX are replaced with 3XX. Put another way, inFIG.3AthroughFIG.3Dand the associated description, features (e.g., structures, materials, devices, regions) of the third microelectronic device structure300functionally similar to previously described features (e.g., structures, materials, devices, regions) of the first microelectronic device structure100described with reference toFIG.1AthroughFIG.1Eare referred to with similar reference numerals incremented by 100. To avoid repetition, not all features shown inFIGS.3A through3Dare described in detail herein. Rather, unless described otherwise below, inFIGS.3A through3D, a feature designated by a reference numeral that is a 100 increment of the reference numeral of a feature previously described with reference to one or more ofFIG.1AthroughFIG.1Ewill be understood to be substantially similar to the previously described feature. By way of non-limiting example, unless described otherwise below, a feature designated by the reference numeral330inFIG.3Awill be understood to be substantially similar to one of the access devices130(including the channel material134, the source material136, and the drain material138thereof) previously described herein with reference toFIG.1AandFIG.1B. The third microelectronic device structure300may also be referred to herein as a third die or a third semiconductive wafer.

With reference toFIG.3A, the third microelectronic device structure300includes a second control logic device region305and a second array region309(also referred to herein as a “second memory array region”) vertically overlying (e.g., in the Z-direction) the second control logic region305. With collective reference toFIG.3AthroughFIG.3C, the second control logic region305includes one or more second sense amplifier device region303; one or more additional CMOS device regions307horizontally neighboring (e.g., in the Y-direction) the second sense amplifier device region303and/or vertically underlying (e.g., in the Z-direction) the staircase structures374.

The second control logic region305includes a third base structure310that is substantially similar to the first base structure110and the second base structure214. Transistor structures311substantially similar to the transistor structures210of the second microelectronic device structure200of the first microelectronic device structure assembly250are formed within the third base structure310in the second control logic region305. Horizontally neighboring (e.g., in the X-direction, in the Y-direction) transistor structures311are isolated from one another by isolation trenches313comprising an eighth insulative material312. The eighth insulative material is substantially the same as the first insulative material112.

The transistor structures311may each individually include conductively doped regions317, each of which includes a source region317A and a drain region317B. Channel regions of the transistor structures311may be horizontally interposed between the conductively doped regions317. Each of the conductively doped regions317(including the source regions317A and the drain regions317B) may be substantially the same as the conductively doped regions216, the source regions216A, and the drain regions216B.

The transistor structures311include gate structures319vertically overlying (e.g., in the Z-direction) the third base structure310and horizontally extending between conductively doped regions317. The gate structures319may be horizontally aligned (e.g., in the Y-direction) with and shared by the channel regions of multiple transistor structures311horizontally neighboring (e.g., in the X-direction (FIG.3C)) one another. In some such embodiments, the gate structures319extend in a first horizontal direction (e.g., in the Y-direction). In addition, dielectric material (also referred to herein as a “gate dielectric material”) may be vertically interposed between the gate structures319and portions of the third base structure310at least partially defining the channel regions of the transistor structures311. The conductively doped regions317and the gate structures319may individually be electrically coupled to tenth conductive interconnect structures321. The tenth conductive interconnect structures321may individually electrically couple the conductively doped regions317and the gate structures319to one or more fifth routing structures323. InFIG.3A, the conductively doped regions317and the tenth conductive interconnect structures321in electrical communication with the conductively doped regions317are not illustrated, but it will be understood, that the conductively doped regions317and the tenth conductive interconnect structures321are located in a plane different than that in which the gate structures318extend. By way of non-limiting example, each gate structure318may be in electrical communication with a plurality of source regions317A on a first side of the gate structure318(e.g., spaced from the gate structure318in the X-direction) and a plurality of drain regions317B on a second, opposite side of the gate structure318(e.g., spaced from the gate structure318in the X-direction opposite the source regions317A). At least some of the fifth routing structures323(e.g., the fifth routing structures323not in electrical communication with the tenth conductive interconnect structures321in electrical communication with the gate structure318) may be in electrical communication with tenth conductive interconnect structures321that are, in turn, in electrical communication with one of the source regions317A or one of the drain regions317B, as illustrated inFIG.3BandFIG.3C.

Each of the gate structures319, the tenth conductive interconnect structure321, and the fifth routing structures323may individually be formed of and include conductive material, such as one or more of the materials described above with reference to the first conductive interconnect structure182. In some embodiments, the gate structures319, the tenth conductive interconnect structure321, and the fifth routing structures323are individually formed of and include tungsten. In other embodiments, the gate structures319, the tenth conductive interconnect structure321, and the fifth routing structures323are individually formed of and include copper.

Referring now toFIG.3A, the second sense amplifier device region303includes transistor structures311. At least some of the transistor structures311within the second sense amplifier device region303may be in electrical communication with eleventh conductive interconnect structures325by means of the fifth routing structures323. The eleventh conductive interconnect structures325are, in turn, in electrical communication with the global digit lines308, which include first global digit lines308A and second global digit lines308B, as described above with reference to the global digit lines108. In some such embodiments, the second sense amplifier device region303comprises sense amplifier devices that are in electrical communication with the global digit lines308, as described above with reference to the sense amplifier devices of the first sense amplifier device region262. In some embodiments, each sense amplifier device of the second sense amplifier device region303is in electrical communication with one of the first global digit lines308A and one of the second global digit lines308B. In use and operation, the sense amplifier devices of the second sense amplifier device region303are configured to amplify a signal (e.g., a difference in voltage) between the first global digit line308A and the second global digit line108B to which the sense amplifier device is connected.

In some embodiments, the second sense amplifier device region303further comprises transistor structures311forming column select devices that are in electrical communication with the sense amplifiers of the second sense amplifier device region303, such as by means of the fifth routing structures323and one or more additional conductive interconnect structures and/or additional routing structures.

In some embodiments, a voltage of the global digit lines308may be selectively provided to one of the conductive pillar structures360extending through the vertical stack of memory cells320by applying a voltage to the multiplexer366electrically connecting the global digit line308to the conductive pillar structure360by means of the global digit line contact structures362and the conductive structures364between the global digit line308and the multiplexer366, as described above with reference to the global digit lines108, the global digit line contact structures162, the conductive structures164, the multiplexers166, and the conductive pillar structures160.

With reference toFIG.3AthroughFIG.3C, the fifth routing structures323in electrical communication with at least some of the transistor structures311within horizontal boundaries of the second array region309are in electrical communication with twelfth conductive interconnect structures327that are, in turn in electrical communication with sixth routing structures329. The sixth routing structures329are in electrical communication with thirteenth conductive interconnect structures331that vertically extend (e.g., in the Z-direction) through the isolation trenches313to the back side of the third base structure310. As will be described in further detail herein, the thirteenth conductive interconnect structures331may be electrically coupled to back end of line (BEOL) structures and/or input/out devices to be formed over portions of the third base structure310. In some embodiments, the thirteenth conductive interconnect structures331are located in a different plane than the plane in which the conductive gates318extend such that the thirteenth conductive interconnect structures331do not electrically short to the conductive gates318. Accordingly, the thirteenth conductive interconnect structures331are illustrated in broken lines inFIG.3Ato indicate that the thirteenth conductive interconnect structures331are located in a different plane than the conductive gates318.

Each of the eleventh conductive interconnect structures325, the twelfth conductive interconnect structures327, the sixth routing structures329, and the thirteenth conductive interconnect structures331may individually be formed of and include conductive material, such as one or more of the materials described above with reference to the first conductive interconnect structures182. In some embodiments, each of the eleventh conductive interconnect structures325, the twelfth conductive interconnect structures327, the sixth routing structures329, and the thirteenth conductive interconnect structures331are individually formed of and include tungsten. In other embodiments, each of the eleventh conductive interconnect structures325, the twelfth conductive interconnect structures327, the sixth routing structures329, and the thirteenth conductive interconnect structures331are individually formed of and include copper.

The one or more additional CMOS device regions307may include one or more control logic devices configured for effectuating control operations of the memory cells120of the first microelectronic device structure100, the memory cells320of the third microelectronic device structure300, or both. By way of non-limiting example, the one or more additional CMOS device regions307may include one or more (e.g., each) of charge pumps (e.g., VCCPcharge pumps, VNEGWLcharge pumps, DVC2 charge pumps), delay-locked loop (DLL) circuitry (e.g., ring oscillators), one or more data output devices (e.g., DQU, DQL), data input/output terminals (e.g., DQ pins, DQ pads), drain supply voltage (VDD) regulators, control devices configured to control column operations and/or row operations for arrays (e.g., the first array region101, the second array region309) of the first microelectronic device structure100and the third microelectronic device structure300, such as decoders (e.g., local deck decoders), repair circuitry (e.g., column repair circuitry, row repair circuitry), memory test devices, array multiplexers (MUX), and error checking and correction (ECC) devices, self-refresh/wear leveling devices, page buffers, data paths, I/O devices (e.g., local I/O devices) and controller logic (timing circuitry, clock devices (e.g., a global clock device)), deck enable, read/write circuitry, address circuitry, or other logic devices and circuitry, and various chip/deck control circuitry. The devices and circuitry included in the one or more additional CMOS device regions307may employ different conventional conductive metal-oxide-semiconductor (CMOS) devices (e.g., conventional CMOS inverters, conventional CMOS NAND gates, conventional CMOS transmission pass gates, etc.), which are not described in detail herein.

With collective reference toFIG.3AthroughFIG.3C, and as described above with reference toFIG.1AthroughFIG.1D, the second array region309includes a vertical stack of memory cells320, each comprising a vertical stack of access devices330(each including a channel material334between a source material336and a drain material338) and a vertical stack of storage devices350neighboring the vertical stack of access devices330, the storage devices350of the vertical stack of storage devices350coupled to the access devices330of the vertical stack of access devices330. AlthoughFIG.3Aillustrates forty (40) vertical stacks of memory cells320, the disclosure is not so limited, and the second array region309may include greater than forty vertical stacks of memory cells320.

With reference toFIG.3C, fifth pad structures378may be formed in electrical communication with the conductive structures332of the steps375of the staircase structure374by means of additional first conductive contact structures376, as described above with reference to the first pad structures178, the first conductive contact structures176, and the conductive structures132.

The global digit lines308may be vertically between (e.g., in the Z-direction) the third base structure310and the vertical stacks of memory cells320. In some embodiments, the multiplexers366are located within the vertical stacks of memory cells320(and comprise a portion of the vertical stacks of memory cells320) and are the nearest ones of the access devices330of the vertical stacks to the global digit lines308. As described above with reference to the multiplexers166, the multiplexers366may be configured to selectively electrically connect one of the global digit lines308to the conductive pillar structure360by selective application of a voltage to the multiplexer366.

Vertically neighboring (e.g., in the Z-direction) memory cells320may be electrically isolated from one another by insulative structures337and additional insulative structures339, as described above with reference to the insulative structures137and the additional insulative structures139.

In some embodiments, an access device330vertically (e.g., in the Z-direction) neighboring (e.g., vertically above) the multiplexer366may comprise a transistor370, one of which is illustrated in box371, configured to electrically couple the conductive pillar structure360to the conductive structure342through an additional conductive structure372. The transistor370may comprise a so-called “bleeder” transistor, as described above with reference to the transistors170. In use and operation, the transistors370are configured to provide a negative voltage to the conductive pillar structures360of unselected (e.g., inactive) vertical stacks of memory cells320.

In some embodiments, the multiplexers366and the transistors370are located vertically between (e.g., in the Z-direction) the second control logic device region305and the memory cells320of the vertical stack of memory cells320. In some embodiments, the vertically lowermost (e.g., in the Z-direction) conductive structure332is in electrical communication the multiplexer366.

With continued reference toFIG.3C, in some embodiments, conductive interconnect structures399may be in electrical communication with conductive structures332that are in electrical communication with the multiplexers366and the transistors370to electrically connect the multiplexers366and the transistors370to one or more transistor structures311within the one or more additional CMOS device regions307(e.g., such as to transistor structures311of a multiplexer controller region). The conductive interconnect structures399may individually be formed of and include conductive material, such as one or more of the materials described above with reference to the first conductive interconnect structures182.

A ninth insulative material380may vertically overlie (e.g., in the Z-direction) the third microelectronic device structure300. The ninth insulative material380may be formed of and include one or more insulative materials, such as one or more of the materials described above with reference to the first insulative material112. In some embodiments, the ninth insulative material380comprises silicon dioxide.

With reference toFIG.3D, the insulative structure337may vertically overlie (e.g., in the Z-direction) the eighth insulative material312and a ninth insulative material380may vertically overlie the ninth insulative structure337.

FIG.4AthroughFIG.4Dare simplified partial cross-sectional views of a second microelectronic device structure assembly400formed by vertically (e.g., in the Z-direction) inverting (e.g., flipping) the third microelectronic device structure300and attaching the third microelectronic device structure300to the first microelectronic device structure assembly250.FIG.4Ais a simplified partial cross-sectional view illustrating the same cross-sectional view as that illustrated inFIG.2JandFIG.3A;FIG.4Bis a simplified partial cross-sectional view illustrating the same cross-sectional view as that illustrated inFIG.2KandFIG.3B;FIG.4Cis a simplified partial cross-sectional view illustrating the same cross-sectional view as that illustrated inFIG.2LandFIG.3C; andFIG.4Dis a simplified partial cross-sectional view illustrating the same cross-sectional view as that illustrated inFIG.2MandFIG.3D.

The third microelectronic device structure300may be attached to the first microelectronic device structure assembly250by placing the ninth insulative material380in contact with the seventh insulative material258and exposing the third microelectronic device structure300and the first microelectronic device structure assembly250to annealing conditions to form bonds (e.g., oxide-to-oxide bonds) between the ninth insulative material380and the seventh insulative material258. In some embodiments, the third microelectronic device structure300and the first microelectronic device structure assembly250are exposed to a temperature greater than, for example, 800° C., to form the oxide-to-oxide bonds and attach the third microelectronic device structure300to the first microelectronic device structure assembly250.

With reference toFIG.4C, in some embodiments, within the second sub word line driver regions202B (FIG.2L), attaching the third microelectronic device structure300to the first microelectronic device structure assembly250includes forming metal to metal bonds between the third pad structures276and the fifth pad structures378of the third microelectronic device structure300. In some such embodiments, attaching the third microelectronic device structure300to the first microelectronic device structure assembly250comprises forming oxide-to-oxide bonds between the ninth insulative material380in contact with the seventh insulative material258and metal to metal bonds between the third pad structures276and the fifth pad structures378.

With collective reference toFIG.4BandFIG.4C, in some embodiments, the first sub word line driver region202A may be horizontally aligned (e.g., in the Y-direction) with the staircase structure174, the first conductive contact structures176, and the first pad structures178of the first microelectronic device structure100and horizontally offset (e.g., in the Y-direction) from the staircase structures374(FIG.4C), the additional first conductive contact structures376(FIG.4C), and the fifth pad structures378(FIG.4C) of the third microelectronic device structure300. In some such embodiments, the steps375of the staircase structures374are horizontally offset (e.g., in the Y-direction) from the steps175of the staircase structures174. In some embodiments, the second sub word line driver region202B may be horizontally aligned (e.g., in the Y-direction) with the staircase structure374, the additional first conductive contact structures376, and the fifth pad structures378of the third microelectronic device structure300and horizontally offset (e.g., in the Y-direction) from the staircase structure174, the first conductive contact structures176, and the first pad structures178of the first microelectronic device structure100.

FIG.4EthroughFIG.4Hillustrate the second microelectronic device structure assembly400at a processing stage after the processing stage illustrated inFIG.4AthroughFIG.4D.FIG.4Eis a simplified partial cross-sectional view of the second microelectronic device structure assembly400illustrating the same cross-sectional view asFIG.4A;FIG.4Fis simplified partial cross-sectional view of the second microelectronic device structure assembly400illustrating the same cross-sectional view asFIG.4B;FIG.4Gis a simplified partial cross-sectional view of the second microelectronic device structure assembly400illustrating the same cross-sectional view asFIG.4C; andFIG.4His a simplified partial cross-sectional view of the second microelectronic device structure assembly400illustrating the same cross-sectional view asFIG.4D.

With collective reference toFIG.4EthroughFIG.4H, after attaching the third microelectronic device structure300to the first microelectronic device structure assembly250to form the second microelectronic device structure assembly400, the third base structure310may be vertically (e.g., in the Z-direction) thinned by exposing the third base structure310to a CMP process. In other embodiments, the third base structure310is vertically thinned by exposing the third base structure310to a dry etch. Vertically thinning the third base structure310may electrically isolate the transistor structures311from one another.

After vertically thinning the third base structure310, fourteenth conductive interconnect structures402(FIG.4H) may be formed vertically (e.g., in the Z-direction) the socket regions204and in electrical communication with the fourth pad structures280(FIG.4H) of the socket regions204; and a back end of line (BEOL) structure410may be formed vertically over (e.g., in the Z-direction) the second microelectronic device structure assembly400to form a microelectronic device450.

Referring toFIG.4H, the fourteenth conductive interconnect structures402may vertically extend (e.g., in the Z-direction) through a tenth insulative material404, the eighth insulative material312, the insulative structure337, the ninth insulative material380, and the seventh insulative material258to contact the fourth pad structure280. Each of the fourteenth conductive interconnect structures402may individually be in electrical communication with a sixth pad structure406.

With collective reference toFIG.4EthroughFIG.4H, fifteenth conductive interconnect structures408(FIG.4EthroughFIG.4G) may be formed in electrical communication with the thirteenth conductive interconnect structures331and sixth pad structures406are formed in electrical communication with the fifteenth conductive interconnect structures408.

Each of the fourteenth conductive interconnect structures402, the fifteenth conductive interconnect structures408, and the sixth pad structures406may individually be formed of and include conductive material, such as one or more of the materials described above with reference to the first conductive interconnect structures182. In some embodiments, each of the fourteenth conductive interconnect structures402, the fifteenth conductive interconnect structures408, and the sixth pad structures406are formed of and include tungsten. In other embodiments, each of the fourteenth conductive interconnect structures402, the fifteenth conductive interconnect structures408, and the sixth pad structures406are formed of and include copper.

Conductive line structures412may be formed vertically over (e.g., in the Z-direction) the sixth pad structures406, seventh pad structures414may be formed vertically over the conductive line structures412, and conductive landing pad structures416may be formed in electrical communication with the seventh pad structures414. In some embodiments, conductive interconnect structures vertically extend between and electrically connect at least some of the sixth pad structures406to at least some of the conductive line structures412; and at least some of the conductive line structures412to at least some of the seventh pad structures414.

Each of the conductive line structures412, the seventh pad structure414, and the conductive landing pad structures416are formed of and include conductive material. Each of the conductive line structures412, the seventh pad structures414, and the conductive landing pad structures416may individually be formed of and include tungsten. In other embodiments, each of the conductive line structures412, the seventh pad structure414, and the conductive landing pad structures416may individually be formed of and include copper. In yet other embodiments, each of the conductive line structures412, the seventh pad structure414, and the conductive landing pad structures416may individually be formed of and include aluminum.

The tenth insulative material404may be formed of and include insulative material, such as one or more of the materials described above with reference to the first insulative material112. In some embodiments, the tenth insulative material404comprises silicon dioxide.

Accordingly, the microelectronic device400may include the first microelectronic device structure100comprising the first array region101including vertical stacks of memory cells120and the third microelectronic device structure300vertically above (e.g., in the Z-direction) the first microelectronic device structure100and comprising the second array region309including additional vertical stacks of memory cells320. The second microelectronic device structure200including the first control logic device region205including the first sense amplifier device region262and each of the first sub word line driver regions202A and the second sub word line driver regions202B vertically intervenes (e.g., in the Z-direction) between the first microelectronic device structure100and the third microelectronic device structure300. The third microelectronic device structure300includes a second control logic device region305including a second sense amplifier device region303.

Forming the microelectronic device450to include the first microelectronic device structure100including the vertical stack of memory cells120; the second microelectronic device structure200including the first control logic device region205including the first sub word line driver region202A for the memory cells120of the first microelectronic device structure100, the second sub word line driver region202B for the memory cells320of the third microelectronic device structure300, the first sense amplifier device region for sense amplifiers of the vertical stack of memory cells120of the first microelectronic device structure100, and the first column select device region for the vertical stack of memory cells of the first microelectronic device structure100; and the third microelectronic device structure300including the second control logic device region305including the second sense amplifier device region303, and the one or more additional CMOS regions307may facilitate forming each of the first microelectronic device structure100to include a greater number of levels of memory cells120and the third microelectronic device structure300to include a greater number of levels of memory cells320in a smaller horizontal footprint (e.g., in the X-direction, in the Y-direction) compared to conventional microelectronic devices. In some embodiments, dividing at least some of the control logic circuitry among the first microelectronic device structure100(e.g., the multiplexers166), the second microelectronic device structure200(e.g., the first control logic device region205including the first sub word line driver region202A for the memory cells120of the first microelectronic device structure100, the second sub word line driver region202B for the memory cells320of the third microelectronic device structure300, the first sense amplifier device region for sense amplifiers of the vertical stack of memory cells120of the first microelectronic device structure100, and column select devices for the vertical stack of memory cells120of the first microelectronic device structure100), and the third microelectronic device structure300(e.g., the second sense amplifier device region303for the memory cells320of the third microelectronic device structure300, and the one or more additional CMOS regions307) may facilitate forming a greater quantity of levels of memory cells120,320within the first microelectronic device structure100and the third microelectronic device structure300.

In some embodiments, placing at least some of the control logic circuitry vertically above the first microelectronic device structure100and vertically below the third microelectronic device structure300(e.g., the second control logic region305) and placing at least some of the control logic circuitry vertically above both the first microelectronic device structure100and the third microelectronic device structure300facilitates forming the microelectronic device450to include a greater quantity and density of memory cells compared to conventional microelectronic devices. For example, the first sub word line driver region202A and the second sub word line driver region202B may be placed vertically between the first microelectronic device structure100and the third microelectronic device structure300(and within horizontal boundaries of each of the staircase structures174,374) facilitates formation of electrical connections for the sub word line driver circuitry within a smaller area compared to conventional microelectronic devices.

Thus, in accordance with some embodiments, a microelectronic device comprises a first microelectronic device structure, a second microelectronic device structure vertically neighboring the first microelectronic device structure, and a third microelectronic device structure vertically neighboring the second microelectronic device structure. The first microelectronic device structure comprises a first memory array region comprising a vertical stack of storage devices, a vertical stack of access devices horizontally neighboring and in electrical communication with the vertical stack of storage devices, conductive lines operatively associated with the vertical stack of access devices and extending in a horizontal direction, horizontal ends of the conductive lines forming a staircase structure, and conductive contact structures in electrical communication with the conductive lines at steps of the staircase structure. The second microelectronic device structure comprises a control logic device region comprising a first sub word line driver region comprising transistor structures in electrical communication with the conductive contact structures, and a second sub word line driver region comprising additional transistor structures horizontally spaced from the first sub word line driver region. The third microelectronic device structure comprises a second memory array region comprising an additional vertical stack of storage devices, an additional vertical stack of access devices horizontally neighboring and in electrical communication with the additional vertical stack of storage devices, additional conductive lines operatively associated with the additional vertical stack of access devices and extending in the horizontal direction, horizontal ends of the additional conductive lines forming an additional staircase structure, and additional conductive contact structures in electrical communication with the additional conductive lines at steps of the additional staircase structure and the additional transistor structures of the second sub word line driver region.

Furthermore, in accordance with additional embodiments of the disclosure, a microelectronic device comprises a first die comprising a stack structure comprising alternating conductive structures and insulative structures intersecting vertical stacks of memory cells, horizontal edges of the alternating conductive structures and insulative structures defining steps of a staircase structure, and conductive contact structures in electrical communication with the conductive structures at the steps of the staircase structure. The microelectronic device further comprises a second die vertically spaced from the first die and comprising an additional stack structure comprising alternating additional conductive structures and additional insulative structures intersecting additional vertical stacks of memory cells, horizontal edges of the alternating additional conductive structures and additional insulative structures defining steps of an additional staircase structure, and additional conductive contact structures in electrical communication with the additional conductive structures at the steps of the additional staircase structure. The microelectronic device further comprises a third die vertically between the first die and the second die and comprising first sub word line drivers in electrical communication with the conductive contact structures, and second sub word line drivers in electrical communication with the additional conductive contact structures and horizontally neighboring the first sub word line drivers in a horizontal direction.

Moreover, in accordance with some embodiments of the disclosure, a method of forming a microelectronic device comprises forming a first microelectronic device structure comprising a memory array region comprising vertical stacks of memory cells, a stack structure intersecting the vertical stacks of memory cells and comprising conductive structures defining steps of a staircase structure, conductive contact structures individually in electrical communication with each step of the staircase structure, and a first oxide material overlying the memory array region. The method further comprises forming a second microelectronic device structure comprising a first sub word line driver region, a second sub word line driver region, and a second oxide material overlying the first sub word line driver region and the second sub word line driver region. The method further comprises attaching the first microelectronic device structure to the second microelectronic device structure to form a microelectronic device structure assembly, attaching the first microelectronic device structure to the second microelectronic device structure comprising horizontally aligning the conductive contact structures with circuitry of the first sub word line driver region, and bonding the first oxide material to the second oxide material. The method further includes forming a third microelectronic device structure comprising an additional memory array region comprising additional vertical stacks of memory cells, an additional stack structure intersecting the additional vertical stacks of memory cells and comprising additional conductive structures defining steps of an additional staircase structure, additional conductive contact structures individually in electrical communication with each step of the additional staircase structure, and a third oxide material overlying the additional memory array region. The third microelectronic device structure is attached to the microelectronic device structure assembly by horizontally aligning the additional conductive contact structures with the second sub word line driver region, and bonding the third oxide material to a fourth oxide material of the microelectronic device structure assembly.

Structures, assemblies, and devices in accordance with embodiments of the disclosure may be included in electronic systems of the disclosure. For example,FIG.5is a block diagram of an illustrative electronic system500according to embodiments of disclosure. The electronic system500may comprise, for example, a computer or computer hardware component, a server or other networking hardware component, a cellular telephone, a digital camera, a personal digital assistant (PDA), portable media (e.g., music) player, a Wi-Fi or cellular-enabled tablet such as, for example, an iPad® or SURFACE® tablet, an electronic book, a navigation device, etc. The electronic system500includes at least one memory device502. The memory device502may comprise, for example, an embodiment of one or more of a microelectronic device structure, a microelectronic device structure assembly, a relatively larger microelectronic device structure assembly, and a microelectronic device previously described herein with reference toFIG.1AthroughFIG.4H. The electronic system500may further include at least one electronic signal processor device504(often referred to as a “microprocessor”). The electronic signal processor device504may, optionally, include an embodiment of one or more of a microelectronic device structure, a microelectronic device structure assembly, a relatively larger microelectronic device structure assembly, and a microelectronic device previously described herein with reference toFIG.1AthroughFIG.4H. While the memory device502and the electronic signal processor device504are depicted as two (2) separate devices inFIG.5, in additional embodiments, a single (e.g., only one) memory/processor device having the functionalities of the memory device502and the electronic signal processor device504is included in the electronic system500. In such embodiments, the memory/processor device may include one or more of a microelectronic device structure, a microelectronic device structure assembly, a relatively larger microelectronic device structure assembly, and a microelectronic device previously described herein with reference toFIG.1AthroughFIG.4H. The electronic system500may further include one or more input devices506for inputting information into the electronic system500by a user, such as, for example, a mouse or other pointing device, a keyboard, a touchpad, a button, or a control panel. The electronic system500may further include one or more output devices508for outputting information (e.g., visual or audio output) to a user such as, for example, one or more of a monitor, a display, a printer, an audio output jack, and a speaker. In some embodiments, the input device506and the output device508may comprise a single touchscreen device that can be used both to input information to the electronic system500and to output visual information to a user. The input device506and the output device508may communicate electrically with one or more of the memory device502and the electronic signal processor device504.

Thus, in accordance with embodiments of the disclosure, an electronic system comprises an input device, an output device, a processor device operably coupled to the input device and the output device, and a memory device operably coupled to the processor device. The memory device comprises a first die and a second die attached to the first die. The first die comprises a memory array region comprising vertical stacks of memory cells, conductive lines horizontally extending through the vertical stacks of memory cells, each conductive line of the conductive lines associated with a level of the memory cells of the vertical stacks of memory cells, conductive pillar structures vertically extending through the vertical stacks of memory cells, each conductive pillar structure of the conductive pillar structures vertically extending through access devices of the vertical stacks of memory cells, and conductive contact structures in electrical communication with the conductive lines. The second die comprises a sub word line driver region comprising sub word line drivers in electrical communication with the conductive contact structures. The memory device further comprises a third die attached to the second die opposite the first die, the third die comprising an additional memory array region comprising additional vertical stacks of memory cells, additional conductive lines horizontally extending through the additional vertical stacks of memory cells, each additional conductive line of the additional conductive lines associated with a level of the memory cells of the additional vertical stacks of memory cells, and complementary metal-oxide semiconductor (CMOS) circuits farther from the second die than the additional memory array region.

The methods, structures, assemblies, devices, and systems of the disclosure advantageously facilitate one or more of improved performance, reliability, durability, increased miniaturization of components, improved pattern quality, and greater packaging density as compared to conventional methods, conventional structures, conventional assemblies, conventional devices, and conventional systems. The methods, structures, and assemblies of the disclosure may substantially alleviate problems related to the formation and processing of conventional microelectronic devices, such as undesirable feature damage (e.g., corrosion damage), deformations (e.g., warping, bowing, dishing, bending), and performance limitations (e.g., speed limitations, data transfer limitations, power consumption limitations).