Power over ethernet method and apparatus for immediate power availability

A PSE control circuitry arranged to: control the power source to output a detection signal; responsive to the detection signal, determine the resistance of a signature resistive element; in the event that the determined resistance is within a predetermined range, control a power source to output power to the load; in the event that the determined resistance is outside the predetermined range, prevent the power source from outputting power for a predetermined disconnect time period; detect the amount of power drawn from the power source; in the event that the detected power amount is less than a predetermined minimum power draw value, control the power source to cease output of power for a predetermined power down time period, the predetermined power down time period less than the predetermined disconnect time period; immediately subsequent to both time periods, control the power source to output the detection signal.

TECHNICAL FIELD

The invention relates generally to the field of power over Ethernet (PoE), and in particular to a rapid start-up PoE system and method.

BACKGROUND

Power over Ethernet (PoE), in accordance with both IEEE 802.3af-2003 and IEEE 802.3at-2009, each published by the Institute of Electrical and Electronics Engineers, Inc., New York, the entire contents of each of which is incorporated herein by reference, defines delivery of power over a set of 2 twisted wire pairs without disturbing data communication. The aforementioned standards particularly provide for a power sourcing equipment (PSE) and a powered device (PD).

When a PD no longer draws power from the PSE, defined by the above mentioned standard as the lack of a maintain power signature (MPS), the PSE shuts down within a predetermined time period and periodically performs a detection stage to detect if a valid PD is connected to the PSE. In the event that a valid PD is detected, the PSE is arranged to supply power to the PD, optionally after performing a classification stage to determine the class of the PD. For some applications, such as lighting, the period between successive detection stages is longer than a user is willing to wait for. As a solution, the PD may be arranged to continuously draw a predetermined minimum amount of power from the PSE so as to maintain the MPS. In order to keep the PSE from shutting down, a direct current (DC) DC MPS is defined in the IEEE 802.3af-2003 standard as sinking at least 10 mA for a minimum duration of 75 ms followed by a dropout period of no more than 250 ms. Unfortunately, this constitutes a significant amount of wasted power, approximately 150 mW. In particular, any control electronics, e.g. a remote control switch, motion detectors, ambient light sensors and network cards, do not need such large amounts of power, thereby most of it is wasted. In the absence of an MPS, a command to energize a PoE based PD will not be actively responded until the next detection, optional classification, and powering cycle occurs. Such a cycle is typically performed every 1-2 seconds, which is not acceptable for lighting. Furthermore, power for any remote control receiving apparatus is not available from the PSE, unless the MPS is maintained.

There is thus a long felt need for a PoE system which can provide rapid turn on of a PD without drawing a large MPS.

SUMMARY OF THE INVENTION

Accordingly, it is a principal object of the present invention to overcome the disadvantages of prior art PoE systems. This is accomplished in certain embodiments by a rapid start-up power over Ethernet (PoE) system comprising: a power sourcing equipment (PSE); and a powered device (PD). The PD comprises: a PD interface comprising a first signature resistive element; a power converter; and a load in electrical communication with a power output of the power converter. The PSE comprises: a power source in electrical communication with the first signature resistive element and with a power input of the power converter, the power source arranged to provide power to the load via the power converter and to provide power to the first signature resistive element; and a PSE control circuitry in communication with the first signature resistive element.

The PSE control circuitry is arranged to: control the power source to output a detection signal exhibiting a first predetermined voltage; responsive to the output detection signal, determine the resistance of the first signature resistive element; in the event that the determined resistance of the first signature resistive element is within a predetermined range, control the power source to output power to the load, the output power exhibiting a second predetermined voltage, greater than the first predetermined voltage; in the event that the determined resistance of the first signature resistive element is outside the predetermined range, prevent the power source from outputting power for a predetermined disconnect time period; detect the amount of power drawn from the power source; in the event that the detected power amount is less than a predetermined minimum power draw value, control the power source to cease output of power for a predetermined power down time period, the predetermined power down time period less than the predetermined disconnect time period; immediately subsequent to the predetermined power down time period, control the power source to output the detection signal; and immediately subsequent to the predetermined disconnect time period, control the power source to output the detection signal.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Before explaining at least one embodiment of the invention in detail, it is to be understood that the invention is not limited in its application to the details of construction and the arrangement of the components set forth in the following description or illustrated in the drawings. The invention is applicable to other embodiments or of being practiced or carried out in various ways. Also, it is to be understood that the phraseology and terminology employed herein is for the purpose of description and should not be regarded as limiting. The term resistor as used herein refers to an element defined in an integrated circuit arranged to present resistance to a current flow there through.

FIG. 1Aillustrates a high level schematic diagram of a PoE system1comprising: a switch/hub11; a plurality of twisted pairs12constituted within a structured cable13; and a PD5, comprising a load6, a DC/DC power converter7, a plurality of data transformers8and a PD interface10. Switch/hub11comprises a plurality of data transformers8and a PSE2. A data pair is coupled across the primary of each data transformer8in switch/hub11and a first end of each twisted pair12is coupled across the secondary of each data transformer8in switch/hub11via respective connections, listed conventionally in two groups: connections1,2,3,6; and connections4,5,7and8. The outputs of PSE2are respectively connected to the center taps of the secondary windings of data transformers8of switch/hub11connected to twisted pairs12via connections1,2,3and6. Structured cable13typically comprises4twisted pairs12.

A data pair is connected across the primary of each data transformer8in PD5and a second end of each twisted pair12is connected across the secondary of each data transformer8in PD5via respective connections, listed conventionally in two groups: connections1,2,3,6; and connections4,5,7and8. The inputs of PD interface10are respectively connected to the center taps of the secondary windings of data transformers8of PD5connected to twisted pairs12via connections1,2,3and6. Load6is coupled to PD interface10via DC/DC power converter7, as described below in relation toFIG. 1B.

The above has been illustrated in an embodiment wherein a single PSE2is arranged to provide power over two twisted pairs12, however this is not meant to be limiting in any way. In another embodiment, switch/hub11comprises a pair of PSEs2, each arranged to provide power over a respective pair of twisted pairs12. Similarly, PSE2is illustrated as being part of switch/hub20however this is not meant to be limiting in any way, and midspan equipment may be utilized to provide a connection for PSE2without exceeding the scope. PSE2may be any equipment arranged to provide power over communication cabling, including equipment meeting the definition of a PSE under any of IEEE 802.3af and IEEE 802.3at, without limitation.

FIG. 1Billustrates a high level schematic diagram of PoE system1, with a more detailed illustration of PD interface10. PD interface10comprises: a power reception port20, comprising a pair of port nodes30; an ideal diode bridge40; a signature resistive element50; an electronically controlled switch60, denoted herein as “resistance switch60” for brevity; a voltage detection circuitry70; a current detection circuitry80comprising a resistor90and a current sense unit100; a unidirectional electronic valve110, denoted herein as “valve110” for brevity; an isolation electronically controlled switch120, denoted herein as “isolation switch120” for brevity; an under voltage lock-out (UVLO) circuit130; an optional class circuit140; and an input capacitance element150.

FIG. 1Cillustrates a high level schematic diagram of ideal diode bridge40ofFIG. 1B, comprising: a plurality of electronically controlled switches160, denoted herein as “diode switches160” for brevity, each coupled in parallel to a respective one of a plurality of unidirectional electronic valves170; and a diode bridge control circuitry180.

FIG. 1Dillustrates a high level schematic diagram of PSE2ofFIGS. 1A-1B, comprising: an adjustable power source3; and a PSE control circuitry4. PSE control circuitry4comprises: a power source control14; a resistance detector15;

an optional class detector16; and a power draw detector17. For clarity, the arrangement ofFIGS. 1A-1Dwill be described together.

PoE system1is described herein as comprising an ideal diode bridge40, however this is not meant to be limiting in any way and any type of bridge circuit which results in polarity insensitivity may be utilized without exceeding the scope. In one embodiment, signature resistive element50comprises a resistor exhibiting a resistance of 26.5 kΩ. In another embodiment, valve110comprises a diode and is described herein as such for simplicity. In another embodiment, isolation switch120comprises an n-channel metal-oxide-semiconductor field-effect transistor (NMOSFET), and is described herein as such for simplicity. In one embodiment, input capacitance element150comprises a capacitor. In another embodiment, each diode switch160comprises an NMOSFET and is described herein as such for simplicity, and the respective unidirectional electronic valve170of each diode switch160is in one embodiment implemented by the body diode thereof and is denoted herein “body diode170” for simplicity.

Each input of ideal diode bridge40is coupled to a center tap of a respective data transformer8of PD5via a respective port node30of power reception port20. A first input of ideal diode bridge40, denoted “IN1”, is coupled to: a first input of diode bridge control circuitry180; the source of a first diode switch160and the anode of body diode170thereof; and the drain of a second diode switch160and the cathode of body diode170thereof. A second input of ideal diode bridge40, denoted “IN2”, is coupled to: a second input of diode bridge control circuitry180; the source of a third diode switch160and the anode of body diode170thereof; and the drain of a fourth diode switch160and the cathode of body diode170thereof.

The output of ideal diode bridge40, denoted “OUT”, is coupled to: the drain of first diode switch160and the cathode of body diode170thereof; and the drain of third diode switch160and the cathode of body diode170thereof. The return of ideal diode bridge40, denoted “RET”, is coupled to: the source of second diode switch160and the anode of body diode170thereof; and the source of fourth diode switch160and the anode of body diode170thereof. A respective output of diode bridge control circuitry180is coupled to the gate of each diode switch160.

Output OUT of ideal diode bridge40is further coupled to a first end of signature resistive element50, a first input of voltage detection circuitry70, a first input of UVLO circuit130, an input of optional class circuit140and the anode of valve110. The cathode of valve110is coupled to a first end of input capacitance element150and a power input of DC/DC converter7. A power output of DC/DC converter7is coupled to the input of load6. The return of load6is coupled to a return input of DC/DC converter7. A return output of DC/DC converter7is coupled to the second end of input capacitance element150and the drain of isolation switch120. The gate of isolation switch120is coupled to an output of UVLO circuit130. The source of isolation switch120is coupled to a second input of UVLO circuit130, an output of optional class circuit140, a first end of resistor90and a first input of current sense unit100of current detection circuitry80. A second end of resistor90is coupled to a second input of current sense unit100, a second input of voltage detection circuitry70, a first terminal of resistance switch60and return RET of ideal diode bridge40. The second terminal of resistance switch60is coupled to the second end of signature resistive element50and the control input of resistance switch60is in communication with a respective output of voltage detection circuitry70. An enabling input of current sense unit100is in communication with a respective output of voltage detection circuitry70and an output of current sense unit100is in communication with an enabling input of ideal diode bridge40, in particular with an enabling input of diode bridge control circuitry180(connection not shown).

Each of a pair of inputs IN1, IN2is coupled to a respective one of the power terminal and the return of adjustable power source3. An output of PSE control circuitry4is coupled to a voltage adjustment input of adjustable power source3.

FIG. 1Eillustrates a high level flow chart of a method of operation of PSE2, the operation of PD interface10and PSE2being described together. In operation, in stage1000, a detection stage is implemented. In the detection stage, power source control14is arranged to control adjustable power source3to output a first detection signal, exhibiting a first voltage value, for a first time period and a second detection signal, exhibiting a second voltage value, for a second time period, in accordance with the standards described above. The first and second voltage values are in the range of 2.8-10V, with a difference of at least 1V between the first voltage and the second voltage. The second time period begins at least 2 ms after the end of the first time period and the overall period from the beginning of the first time period to the end of the second time period is less than 500 ms.

Voltage detection circuitry70is arranged to detect the potential difference between output OUT and return RET of ideal diode bridge40, denoted VOUT, and enable/disable resistance switch60and current sense unit100responsive thereto. In particular, in the event that VOUT is less than a predetermined minimum detection stage voltage value, optionally 12V, voltage detection circuit70is arranged to close resistance switch60, thus presenting signature resistive element50to PSE control circuitry4via ideal diode bridge40. In one embodiment, resistance switch60is arranged to be normally closed in the absence of an active signal from voltage detection circuit70. As will be described below in relation to stage1060, voltage detection circuitry70is further arranged to enable current sense unit100when VOUT is greater than a predetermined minimum power stage voltage value.

In stage1010, resistance detector15is arranged to determine the signature resistance of PD interface10, i.e. determine the resistance of signature resistive element50, responsive to the output voltages of stage1000. In particular, as described above, PSE2is in electrical communication with signature resistive element50via ideal diode bridge40, responsive to resistance switch60being closed during the detection stage. Thus, PSE control circuitry4is able to determine the resistance of signature resistive element50responsive to the applied first and second voltages, as known to those skilled in the art at the time of the invention.

Valve110isolates input capacitance element150from signature resistive element50, therefore charge stored on input capacitance element150is prevented from being transferred to signature resistive element50and therefore does not impact the resistance detection by PSE control circuitry4. In particular, without the isolation of valve110the detection signals of stage1000would be affected by the charge stored on input capacitance element150, since PSE control circuitry4would be determining the resistance of signature resistive element50responsive to a detection signal which has been altered by the charge of input capacitance element150and would therefore make an incorrect resistance determination. Valve110, however, is arranged to block potential difference across capacitance element150from being seen across signature resistive element50. Valve160thus enables the detection of stage1010may be performed after only a short time period following powering down of PD5, irrespective of charge held across capacitance element150, as will be described further below in relation to stage1080.

Additionally, UVLO circuit130is arranged to maintain isolation switch120open as long as voltage VOUT is less than a predetermined minimum operating voltage value, optionally 30-35V. The first and second detection signals of stage1000each exhibit a voltage less than the predetermined minimum operating voltage value, therefore isolating switch120is open during the detection stage and input capacitance element150is isolated from PSE2. As described above in relation to signature resistive element50, valve110isolates UVLO circuit130from input capacitance element150such that UVLO circuit130reads the voltage output by PSE2and not the potential difference across input capacitance element150.

In stage1020, power source control14is arranged to compare the determined signature resistance of stage1010with a predetermined resistance range, in accordance with the standards described above. In one embodiment, the predetermined resistance range is 19-26.5 kΩ. In another embodiment, the lower boundary of the predetermined resistance range is 15-19 kΩ and the upper boundary of the predetermined resistance ranged is 26.5-33 kΩ. In the event that the determined signature resistance is within the predetermined resistance range, it is determined that a valid PD5is coupled to twisted pairs12and power can be provided thereto.

In optional stage1030, a classification stage is implemented. In the classification stage, power source control14is arranged to control adjustable power source3to output a classification signal to optional class circuit140, the classification signal exhibiting a voltage greater than the voltage of the first and second detection signals of stage1000, optionally 15.5-20.5V. Optional class circuit140outputs a predetermined current to PSE2indicating the class of PD5, in accordance with the standards described above. In optional stage1040, optional class detector16is arranged to receive the current output by optional class circuit140and in optional stage1050is arranged to determine the class of PD5responsive to the received current. Advantageously, valve110isolates optional class circuit140from input capacitance element150, therefore charge stored on input capacitance element150does not impact the voltage received by optional class circuit140, as described above in relation to the isolation of signature resistive element50.

In stage1060, power source control14is arranged to control adjustable power source3to provide DC power to load6via DC-DC converter7. The voltage of power stage1060is within a range greater than the voltage range of the detection of stage1010and the classification of optional stage1030, optionally the voltage of power stage106is 44-57V. Voltage detection circuitry70is arranged to enable the operation of current sense unit100responsive to voltage VOUT rising above a predetermined minimum operating voltage value, optionally 30-35V. Current sense unit100is arranged to sense the current flowing through resistor90, the current denoted “IL”. In the event that current sense unit100determines that the magnitude of current IL is greater than a predetermined value, i.e. that enough power is being provided to operate diode switches160of ideal diode bridge40, current sense unit100enables the operation of diode bridge control circuitry180. Such a current based control of ideal diode bridge40provides improved control over ideal diode bridge40as compared to prior art voltage based controls, and thus results in reduced power loss.

Diode bridge control circuitry180is arranged to compare the voltage potential at input IN1to the voltage potential at input IN2. In the event that the voltage potential at input IN1is greater than the voltage potential at input IN2by a predetermined minimum amount, diode bridge control circuitry180is arranged to: close first diode switch160coupling input IN1with output OUT; close fourth diode switch160coupling input IN2with return RET; and open second and third diode switches160. As a result, the voltage potential at power OUT will be greater than the voltage potential at return RET. In the event that the voltage potential at input IN1is less than the voltage potential at input IN2by the predetermined minimum amount, diode bridge control circuitry180is arranged to: close second diode switch160coupling input IN1with return RET; close third diode switch160coupling input IN2with output OUT; and open first and fourth diode switches160. As a result, the voltage potential at output OUT will be greater than the voltage potential at return RET. Diode switches160, responsive to diode bridge control circuitry180, thus operate in the same manner of a diode bridge, i.e. the polarity of output voltage VOUT is always the same, regardless of the polarity of the potential difference between inputs IN1and IN2, with a substantially lower voltage drop than that of a conventional diode bridge.

In the event that PD5is switched off or disconnected, i.e. load6no longer draws power from adjustable power source3of PSE2, power control14is arranged to shut down adjustable power source3for one of a first and second predetermined time period. Particularly, in stage1070, power draw detector17monitors the power being drawn from adjustable power source3, and power draw detector17determines if the power being drawn from adjustable power source3is less than a predetermined minimum power draw value. In one embodiment, the predetermined minimum power draw value is power of less than 10 mA being drawn over a period of 300-400 ms, i.e. power draw detector17determines the absence of a valid MPS. In stage1080, power source control14prevents adjustable power source3from outputting power for a predetermined power down time period. In one embodiment, the predetermined power down time period is about 40 ms.

After the predetermined power down time period of stage1080has elapsed, detection of stage1090is immediately performed. Detection of stage1090may be identical to the detection of stages1010-1020, or alternatively pre-detection as described in U.S. Pat. No. 7,849,343 issued to Ferentz et al Dec. 7, 2010, the entire contents of which is incorporated herein by reference, is performed. In another embodiment any detection method that identifies that an open circuit does not appear across PSE2may be performed, since the detection of stage1010was valid and only an invalid MPS has been detected in stage1070. In the event that a potentially valid load is detected, stage1060as described is performed, preferably immediately to provide power to the PD. Advantageously, in the event that during the power down time period PD5was switched back on, start-up of PD5will begin quickly because the power down time period is very short.

In the event that in stage1090a resistance is detected which is not indicative of a potentially valid load, for example it is indicative of an open circuit condition, or in the event that detection as in stages1010-1020is performed, the resistance is outside the acceptable range, in stage1100power source control14prevents adjustable power source3from outputting power for a predetermined disconnect time period, the predetermined disconnect time period significantly longer than the power down time period of stage1080. In one embodiment, the predetermined disconnect time period is about 1 s. After the predetermined disconnect time period has elapsed, the detection of stage1000is again performed. Thus, in the event that a potentially valid load is not detected in stage1090the longer disconnect time period is utilized to time the subsequent detection, whereas in the event of an invalid MPS the shorter power time period is utilized to time the subsequent detection. The power down time period of stage1080is thus less than 1/10 the disconnect time period of stage1100.

FIG. 2illustrates a high level schematic diagram of a PoE system300, comprising: a PSE2comprising aN adjustable power source3and a PSE control circuitry4; and a PD310comprising a load6, a DC-DC converter7and a PD interface320. PD interface320comprises: a power reception port20, comprising a pair of port nodes30; a diode bridge225; an input capacitance element150; a diode bridge330; a signature resistive element50; an electronically controlled switch340; and a detection control circuit350.

Each input of diode bridge225is coupled to a respective output of PSE2via a respective port node30of power reception port20, as described above in relation to PoE system1ofFIG. 1A. The output of diode bridge225is coupled to a first end of input capacitance element150and to a power input of DC/DC converter7. A power output of DC/DC converter7is coupled to an input of load6. A return of load6is coupled to a return input of DC/DC converter7and a return output of DC/DC converter7is coupled to a second end of input capacitance element150and the return of diode bridge225. Each input of diode bridge225is further coupled to a respective input of diode bridge330. The positive output of diode bridge330is coupled to a first end of signature resistive element50and to a first input of detection circuit350. A second end of signature resistive element50is coupled to a first port of electronically controlled switch340. The return of diode bridge330is coupled to a second port of electronically controlled switch340and to a second input of detection circuit350. An output of detection circuit350is connected to the control input of electronically controlled switch340.

In operation, PSE2operates in all respects as described above in relation toFIG. 1C. In particular, as described above in relation to stage1010, PSE control circuitry4is arranged to detect the resistance of signature resistive element50. In contrast with PoE system1, where signature resistive element50is isolated from input capacitance element150by valve110, in PoE system300signature resistive element50is isolated from input capacitance element150by diode bridge225. Advantageously, the arrangement of PoE system300does not require valve110within the power line connecting diode bridge225and DC/DC converter7, as is required in PoE system1ofFIG. 1A, thereby avoiding power loss due to current flowing through valve110.

PoE system300has been described and illustrated as not comprising optional class circuit140, however this is not meant to be limiting in any way. In another embodiment, optional class circuit140is provided, as described above in relation toFIG. 1A, and the classification of stages1030-1050are performed, as described above. In the event that a class circuit is provided, in certain embodiments a memory is provided arranged to ensure that detection of the type of PSE2, identified by class circuit140, is remembered in the absence of power from PSE2and may be polled by a control device (not shown).

FIG. 2has been described with diode bridge330and a single signature resistive element50, however this is not meant to be limiting in any way. In another embodiment a half bridge circuit is provided with separate signature resistive elements for each path, without exceeding the scope.

FIG. 3illustrates a high level schematic diagram of a PoE system400. PoE system400is in all respects similar to PoE system1ofFIG. 1B, with the exception that isolation switch120is removed from the current return path, i.e. isolation switch120is coupled between input capacitance element150and the current path between the return output of DC/DC converter7and return RET of ideal diode bridge40. In particular, the drain of isolation switch120is coupled to the second end of input capacitance element150and the source of isolation switch120is coupled to the return output of DC/DC converter7, the output of optional class circuit140, the second input of UVLO circuit130, the first end of resistor90and the first input of current sense unit100. A respective output of UVLO circuit130is in communication with a control input of DC/DC converter7. The operation of PoE system400is in all respects similar to the operation of PoE system1, except as described below, and in the interest of brevity will not be further described. Advantageously, current output from the return of DC/DC converter7towards ideal diode bridge40does not flow through isolation switch120, thereby preventing unnecessary power loss therefrom. When UVLO circuit130opens isolation switch120, UVLO circuit130is further preferably arranged to disable DC/DC converter7such that power does not flow therethrough and DC/DC converter7is enabled when isolation switch120is closed. The control of DC/DC converter7is illustrated as being responsive to UVLO circuit130, however this is not meant to be limiting in any way, and a separate UVLO circuit may be supplied for DC/DC converter7without exceeding the scope. Alternately, DC/DC converter7may detect a lack of power draw by the load and disable itself.

FIG. 4illustrates a high level schematic diagram of a PoE system500, comprising: a PSE2comprising an adjustable power source3and a PSE control circuitry4; and a PD510comprising a load6, a DC-DC converter7and a PD interface520. PD interface520comprises: a power reception port20, comprising a pair of port nodes30; an ideal diode bridge40; a signature resistive element50; a resistance switch60; a voltage detection circuitry70; a current detection circuitry80, comprising a resistor90and a current sense unit100; an optional class circuit140; an input capacitance element150; a diode bridge330; a power source530; a DC/DC power converter535; and a UVLO circuit540. In one embodiment, power source530comprises a Lithium battery and optionally DC/DC power converter535comprises a boost converter.

Each input of ideal diode bridge40is coupled to a respective output of PSE2via a respective port node30of power reception port20, as described above in relation to PoE system1ofFIG. 1A. The output of ideal diode bridge40is coupled to a first input of UVLO circuit540, an output of DC/DC power converter535, a first end of input capacitance element150and a power input of DC/DC converter7. A power output of DC/DC converter7is coupled to an input of load6. The return of load6is coupled to a return input of DC/DC converter7. A return output of DC/DC converter7is coupled to the second end of input capacitance element150, the return of power source530, a second input of UVLO circuit540, a first end of resistor90and a first input of current sense unit100of current detection circuitry80. A second end of resistor90is coupled to a second input of current sense unit100and the return of ideal diode bridge40. The output of DC/DC power converter535is coupled to the power terminal of power source530.

Each input of ideal diode bridge40is further coupled to a respective input of diode bridge330. The positive output of diode bridge330is coupled to a first end of signature resistive element50, a first input of voltage detection circuitry70, and the input of optional class circuit140. The output of optional class circuit140is coupled to a second input of voltage detection circuitry70, a first terminal of resistance switch60and the return of diode bridge330. The second terminal of resistance switch60is coupled to the second end of signature resistance element50and the control input of resistance switch60is in communication with a first output of voltage detection circuitry70. A second output of voltage detection circuitry70is in electrical communication with an enabling input of current sense unit100and an enabling input of load6.

The operation of PSE2is as described above in relation toFIG. 1Cand in the interest of brevity will not be further described, only the operation of PD interface510being described in some detail. In operation, voltage detection circuitry70is arranged to detect the potential difference between the output and return of diode bridge330, denoted VOUT, and enable/disable resistance switch60, current sense unit100and load6responsive thereto. In particular, as described above, in the event that VOUT is less than a predetermined minimum detection stage voltage value, optionally 12V, voltage detection circuit70is arranged to close resistance switch60, thus presenting signature resistive element50to PSE control circuitry4via diode bridge330for the signature detection of stages1000-1020. When power is provided by PSE2, in stage1060described above, voltage detection circuitry70is arranged to enable the operation of current sense unit100and load6, responsive to voltage VOUT rising above a predetermined minimum operating voltage value, optionally 30-35V. current sense unit100, upon sensing a flow of current above a predetermined level, and responsive to the voltage detected by voltage detection circuitry70enables operation of ideal diode bridge40. The operation of current sense unit100and optional class circuit140are as described above in relation toFIGS. 1A-1Cand in the interest of brevity will not be further described.

The combination of UVLO circuit540, DC/DC power converter535and power supply530maintains the voltage of input capacitance element150to be above a predetermined power down voltage value, the predetermined power down voltage value being above the detection and/or classification voltage level, optionally 22V. In particular, UVLO circuit540is arranged to detect the potential difference across input capacitance element150. In the event the potential difference across input capacitance element150drops below the predetermined power down voltage value, UVLO circuit540is arranged to enable DC/DC power converter535to charge input capacitance element150with power output by power supply530. In absence of such an arrangement, input capacitance element150is typically isolated from ideal diode bridge40so as not to interfere during the detection stage and optional classification stage. Advantageously, since the voltage of input capacitance element150is being maintained above the detection and classification voltage levels, ideal diode bridge40prevents any voltage across input capacitance element150from appearing across the input to ideal diode bridge40, and thus any voltage across input capacitance element150does not interference with detection or classification. An isolation switch, such as isolation switch120described above, is thus not required and unnecessary power loss across such an isolation switch is prevented.

FIG. 5illustrates a high level schematic diagram of PoE system600, comprising: a PSE2comprising a adjustable power source3and a PSE control circuitry4; and a PD610comprising a load6, a DC-DC converter7and a PD interface620. PD interface620comprises: a power reception port20, comprising a pair of port nodes30; a signature resistive element50; a diode bridge225; an isolation switch120; a UVLO circuit130; an input capacitance element150; and a diode bridge330.

Each input of diode bridge225is coupled to a respective output of PSE2via a respective port node30of power reception port20, as described above in relation to PoE system1ofFIG. 1A. The output of diode bridge225is coupled to a first end of signature resistive element50, a first end of input capacitance element150and to a power input of DC/DC converter7. A power output of DC/DC converter7is coupled to an input of load6. A return of load6is coupled to a return input of DC/DC converter7and a return output of DC/DC converter7is coupled to a second end of input capacitance element150and the drain of isolation switch120. The source of isolation switch120is coupled to the second end of signature resistive element50and the return of diode bridge225. Each input of diode bridge225is further coupled to a respective input of diode bridge330. The output of diode bridge330is coupled to a first input of UVLO circuit130and the return of diode bridge330is coupled to a second input of UVLO circuit130. An output of UVLO circuit130is coupled to the gate of isolation switch120.

In operation, PSE2operates in all respects as described above in relation toFIG. 1C. In particular, as described above in relation to stage1010, PSE control circuitry4is arranged to detect the resistance of signature resistive element50. UVLO circuit130is arranged to open isolation switch120responsive to the potential difference between the output and the return of diode bridge330being less than the predetermined minimum operating voltage, as described above. Thus, signature resistive element50is isolated from input capacitance element150responsive to the opening of isolation switch120.

Advantageously, the embodiments depicted herein provide an almost 100% power availability for load6, while still maintaining the key features of the above mentioned standards. In particular the shortened power down period responsive to an MPS detection, followed by a potentially valid load detection, as described in stages1080-1090ofFIG. 1E, provides for almost full time power availability for the load. Thus, in the event that load6is constituted of a light, such as an LED strip, turn on of the switch is responded to by the PoE system described herein without perceptible delay.

The terms “include”, “comprise” and “have” and their conjugates as used herein mean “including but not necessarily limited to”.