Semiconductor devices including vertical transistors and methods of fabricating the same

A semiconductor device includes a first capacitor in a trench of a semiconductor substrate and an active pillar disposed on the semiconductor substrate opposite the first capacitor. The active pillar includes first region, first channel region, second region, second channel region and third region, sequentially stacked. A pillar connection pattern electrically connects the first capacitor to a first source region. A first gate electrode is disposed on a sidewall of the first channel region. A common drain region is disposed in the second region, and a common bit line is disposed on a sidewall of the common drain region. A second gate electrode is disposed on a sidewall of the second channel region, and a second source region is disposed in the third region. A second capacitor is disposed on a top surface of the second source region opposite the second channel region.

CROSS-REFERENCES TO RELATED APPLICATIONS

The present application claims priority under 35 U.S.C 119(a) to Korean Application No. 10-2012-0084010, filed on Jul. 31, 2012, in the Korean Intellectual Property Office, which is incorporated herein by reference in its entirety as set forth in full.

BACKGROUND

Embodiments of the present disclosure relate to semiconductor devices and methods of fabricating the same and, more particularly, to semiconductor devices including vertical transistors and methods of fabricating the same.

As mobile systems become more supplied and digital home appliances become excessively scaled down, semiconductor devices constituting the mobile systems or the digital home appliances have been more highly integrated. Particularly, various attempts to increase integration density of semiconductor memory devices have been made to store more data in a limited planar area. The semiconductor memory devices may include dynamic random access memory (DRAM) devices which are widely used and employed in the mobile systems and/or the digital home appliances. In general, each of memory cells of the DRAM devices includes a planar cell transistor and a cell capacitor stacked on the planar cell transistor, and the planar cell transistor has a source region and a drain region which are located at the same horizontal level on or in a semiconductor substrate. If a gate width (e.g., a channel length) of the planar cell transistor is reduced to have about 40 nanometers or less, the planar cell transistor may suffer from a short channel effect causing a channel leakage current and the channel leakage current may result in high power consumption.

Recently, vertical transistors have been proposed to overcome the disadvantages of the planar cell transistors. Each of the vertical transistors may include a drain region, a channel region and a source region which are vertically stacked in a semiconductor substrate such as a silicon substrate. Further, each of the vertical transistors may include a gate electrode disposed to cover at least a portion of a sidewall of the channel region. A method of fabricating a vertical transistor is taught in U.S. patent publication No. 2012-0135573 A1 to Kim, entitled “method for manufacturing vertical transistor having one side contact”. If the vertical transistors are employed in the semiconductor memory devices, the integration density of the semiconductor memory devices may be increased without degradation of performance of the semiconductor memory devices.

SUMMARY

Example embodiments are directed to semiconductor devices including vertical transistors and methods of fabricating the same.

According to some embodiments, a semiconductor device includes a first capacitor in a trench of a semiconductor substrate and an active pillar disposed on a top surface of the semiconductor substrate opposite to the first capacitor. The active pillar includes a first region, a first channel region, a second region, a second channel region and a third region which are sequentially stacked. A pillar connection pattern is disposed to electrically connect the first capacitor to a first source region formed in the first region of the active pillar. A first gate electrode is disposed on a sidewall of the first channel region of the active pillar, and a common drain region is disposed in the second region of the active pillar. A common bit line is disposed on a sidewall of the common drain region, and a second gate electrode is disposed on a sidewall of the second channel region of the active pillar. A second source region is disposed in the third region of the active pillar, and a second capacitor is disposed on a top surface of the second source region opposite to the second channel region.

According to further embodiments, a semiconductor device includes an active pillar disposed on a semiconductor substrate to include a first source region, a common drain region and a second source region which are spaced apart from each other, a first capacitor disposed in a trench of a semiconductor substrate and electrically connected to the first source region, a common bit line electrically connected to the common drain region, a first gate electrode generating a first channel layer which is located between the first capacitor and the common bit line to transmit a bit signal, a second capacitor electrically connected to the second source region, and a second gate electrode generating a second channel layer which is located between the second capacitor and the common bit line to transmit the bit signal.

According to further embodiments, a method of fabricating a semiconductor device includes forming a first capacitor in a trench of a semiconductor substrate and forming an active pillar on a top surface of the semiconductor substrate opposite to the first capacitor. The active pillar is formed to include a first region, a first channel region, a second region, a second channel region and a third region which are sequentially stacked. A pillar connection pattern is formed to electrically connect the first capacitor to a first source region in the first region of the active pillar. A first gate electrode is formed on a sidewall of the first channel region, and a common drain region is formed in the second region. A common bit line is formed on a sidewall of the common drain region, and a second gate electrode is formed on a sidewall of the second channel region. A second source region is formed in the third region, and a second capacitor is formed on a top surface of the second source region opposite to the second channel region.

According to still other embodiments, a semiconductor device includes a first capacitor having a storage node electrode in a trench in a semiconductor substrate. An active pillar is disposed on a top surface of the semiconductor substrate adjacent to the first capacitor. The active pillar includes a first region, a second region, a third region, a fourth region, and a fifth region, which are sequentially stacked. The semiconductor device also includes a first source region formed in the first region of the active pillar, a pillar connection pattern configured for electrically connecting the storage node electrode of the first capacitor to the first source region, a first gate electrode on a sidewall of a first channel region formed in the second region of the active pillar, a common drain region formed in the third region of the active pillar, a common drain electrode on a sidewall of the common drain region, a second gate electrode on a sidewall of a second channel region formed in the fourth region of the active pillar, and a second source region formed in the fifth region of the active pillar. The semiconductor device also has a second capacitor stacked on the active pillar and having a storage node electrode formed on a top surface of the second source region.

In some embodiments of the above semiconductor device, the first gate electrode completely surrounds the sidewall of the second region of the active pillar, the common drain electrode completely surrounds the sidewall of the third region of the active pillar, and the second gate electrode completely surrounds the fourth region of the active pillar.

According to alternative embodiments, a semiconductor memory array includes a plurality of the semiconductor device described above. The semiconductor memory array includes a first word line connecting the first gate electrodes in a row of the semiconductor devices, and the first word line extends in a first direction which is parallel with a top surface of the semiconductor substrate. The semiconductor memory array also has a second word line connecting the second gate electrodes in said row of the semiconductor devices, and the second word line extends in said first direction which is parallel with a top surface of the semiconductor substrate. The semiconductor memory array also has a common bit line connecting the common drain electrodes in a column of the semiconductor devices, and the common bit line extends in a second direction which is perpendicular to the first direction and is parallel with the top surface of the semiconductor substrate.

DETAILED DESCRIPTION OF THE EMBODIMENTS

It will be understood that when an element is referred to as being “coupled to,” “connected to,” “responsive to,” or “on” another element, it can be directly coupled to, connected to, responsive to, or on the other element, or intervening elements may also be present. In contrast, when an element is referred to as being “directly coupled to,” “directly connected to,” “directly responsive to,” or “directly on” another element, there are no intervening elements present. As used herein the term “and/or” includes any and all combinations of one or more of the associated listed items. The same reference numerals or the same reference designators denote substantially the same elements throughout the specification.

Moreover, in explanation of methods such as fabrication methods, the sequence of the process steps described herein may be changed unless the context clearly indicates a specific order. That is, the process steps may be performed in the same order as described herein or in a different order from the descriptions.

FIG. 1Aillustrates an equivalent circuit diagram of a portion of a semiconductor device according to an example embodiment. Referring toFIG. 1A, a semiconductor device according to an example embodiment may include common bit lines122, a first word line140disposed below the common bit lines122, a second word line160disposed over the common bit lines122, and first and second capacitors150and170electrically connected to each of the common bit lines122. InFIG. 1A, a unit cell100may include a first gate electrode142receiving a control signal through the first word line140and a second gate electrode162receiving another control signal through the second word line160. The first gate electrode142may correspond to a gate electrode of a lower transistor T1, and source and drain regions of the lower transistor T1may be electrically connected to the first capacitor150and a selected one of the common bit lines122, respectively. Similarly, the second gate electrode162may correspond to a gate electrode of an upper transistor T2, and source and drain regions of the upper transistor T2may be electrically connected to the second capacitor170and the selected one of the common bit lines122, respectively.

In the unit cell100, if a bit signal is applied to the selected common bit line122and a voltage over a threshold voltage of the lower transistor T1is applied to the first gate electrode142, the lower transistor T1may be turned on to store a datum corresponding to the bit signal in the first capacitor150. The first capacitor150may include a first storage node electrode152electrically connected to the lower transistor T1and a plate electrode154facing the first storage node electrode152. The plate electrode154may be grounded or may have a predetermined electric potential. If a bit signal is applied to the selected common bit line122and a voltage over a threshold voltage of the upper transistor T2is applied to the second gate electrode162, the upper transistor T2may be turned on to store a datum corresponding to the bit signal in the second capacitor170. The second capacitor170may include a second storage node electrode172electrically connected to the upper transistor T2and a plate electrode174facing the second storage node electrode172. The plate electrode174may be grounded or may have a predetermined electric potential.

As described above, if a voltage over the threshold voltages of the lower and upper transistors T1and T2is applied to any one of the first and second gate electrodes142and162when the bit signal is applied to the selected common bit line122, a datum corresponding to the bit signal may be stored in one of the first and second capacitors150and170. In some embodiments, the semiconductor device may be designed such that a control signal is independently applied to the first and second word lines140and160and the first capacitor150has a different capacitance from the second capacitor170. In such a case, the unit cell100may operate as a multi-bit cell. For example, the unit cell100may have a first logic state if both the first and second capacitors150and170are not charged, the unit cell100may have a second logic state if only the first capacitor150is charged, the unit cell100may have a third logic state if only the second capacitor170is charged, and the unit cell100may have a fourth logic state if both the first and second capacitors150and170are charged. An electric potential (corresponding to one of the first to fourth logic states) induced by the first and second capacitors150and170may be transmitted to the selected common bit line122when the lower and upper transistors T1and T2are turned on, and the electric potential of the selected common bit line122may be amplified by a sense amplifier electrically connected to the selected common bit line122. Further, the sense amplifier may discriminate the logic state of the unit cell100using the amplified electric potential and may output the corresponding datum.

FIG. 1Bis a cross sectional view illustrating a portion of a semiconductor device according to an example embodiment. Referring toFIG. 1B, a semiconductor device according to an example embodiment may include first capacitors150disposed in respective ones of trenches114in a semiconductor substrate110, active pillars130disposed on the semiconductor substrate110, and pillar connection patterns133electrically connecting the first capacitors150to respective ones of the active pillars130. The semiconductor device may further include first gate electrodes142disposed on respective ones of lower sidewalls of the active pillars130, common bit lines122disposed on respective ones of middle sidewalls of the active pillars130, and second gate electrodes162disposed on respective ones of upper sidewalls of the active pillars130. In addition, the semiconductor device may include second capacitors170disposed on respective ones of the active pillars130. The semiconductor substrate110may be a silicon substrate doped with p-type impurities.

The first capacitors150may be trench structural capacitors. Each of the first capacitors150may include a capacitor dielectric layer153and a storage node electrode152which are sequentially stacked on an inner surface (e.g., a bottom surface and a sidewall surface) of a trench114in the semiconductor substrate110. The capacitor dielectric layer153may include, for example, at least one of a tantalum oxide (TaO2) layer, a zirconium oxide (ZrO2) layer, an aluminum oxide (Al2O3) layer and a hafnium oxide (HfO2) layer. The storage node electrode152may include, for example, at least one of a doped silicon layer, a titanium (Ti) layer, a tantalum (Ta) layer, a ruthenium (Ru) layer, an iridium (Ir) layer, a tungsten (W) layer, a titanium nitride (TiN) layer, a tantalum nitride (TaN) layer, a ruthenium oxide (RuO2) layer and a tungsten nitride (WN) layer. The first capacitors150may share a doped semiconductor layer154that surrounds the trenches114to act as a plate electrode thereof. The plate electrode154may be a well region which is formed by implanting or injecting impurities into the semiconductor substrate110with a relatively high dose. A top surface of the plate electrode154may be located at a first depth D1from a top surface of the semiconductor substrate110, and a bottom surface of the plate electrode154may be located at a second depth D2from the top surface of the semiconductor substrate110. The first depth D1is less than a depth of the trenches114, and the second depth D2is greater than a depth of the trenches114. The plate electrode154may have an opposite conductivity type to the semiconductor substrate110. For example, when the semiconductor substrate110is a p-type substrate, the plate electrode154may have an n-type.

The active pillars130may be disposed not to overlap with the first capacitors150when viewed from a plan view. The active pillars130may be the same material as the semiconductor substrate110. For example, the active pillars130may be a plurality of protrusions that upwardly extend from the semiconductor substrate110. That is, the active pillars130may be formed by etching a portion of the semiconductor substrate110. Each of the active pillars130may have a cylinder-shaped pillar or a polygonal pillar. That is, each of the active pillars130may have a circular shape or a polygonal shape when viewed form a plan view. The active pillars130may act as bodies of vertical transistors. That is, each of the active pillars130may include a first source region132, a first channel region, a common drain region134, a second channel region and a second source region136. The first source region132, the common drain region134and the second source region136may be disposed in a first region, a second region and a third region of each active pillar130, respectively. The first source region132, the common drain region134and the second source region136may be n-type regions which are disposed at a sidewall surface of each of the active pillars130or in a bulk region of each of the active pillars130. Unlike the drawing ofFIG. 1B, the first source region132, the common drain region134and the second source region136may be conductive layers which are disposed on a sidewall surface of each of the active pillars130.

The pillar connection patterns133may be disposed on the semiconductor substrate110. The pillar connection patterns133may electrically connect the storage node electrodes152of the first capacitors150to the first source regions132. The pillar connection patterns133may be, for example, doped silicon patterns. Specifically, when the semiconductor substrate110contacting the pillar connection patterns133has a p-type, the pillar connection patterns133may be n-type silicon patterns.

The first gate electrodes142may be disposed on respective ones of sidewalls of the first channel regions between the first source regions132and the common drain regions134, and first gate dielectric layers141may be disposed between the first gate electrodes142and the first channel regions. In some embodiments, the first gate dielectric layers141may be disposed to surround the sidewalls of the first channel regions. Each of the first gate dielectric layers141may include, for example, at least one of a silicon oxide (SiO2) layer, a silicon nitride (SiN) layer, a silicon oxynitride (SiON) layer, a hafnium oxide (HfO2) layer, an aluminum oxide (Al2O3) layer and a tantalum oxide (TaO2) layer. The first gate electrodes142may be disposed to surround outer sidewalls of the first gate dielectric layers141opposite to the active pillars130(e.g., the first channel regions). Further, the first gate electrodes142may extend in a first direction, which is parallel with a top surface of the semiconductor substrate110, to act as first word lines. A first interlayer insulation layer1310may be disposed between the pillar connection patterns133and the first gate electrodes142, thereby electrically insulating the pillar connection patterns133from the first gate electrodes142.

The common bit lines122may be disposed on respective ones of sidewalls of the common drain regions134. The common bit lines122may be electrically connected to respective ones of the common drain regions134, and bit signals applied to the common bit lines122may be transmitted to the common drain regions134. In some embodiments, the common bit lines122may be disposed to surround respective ones of sidewalls of the common drain regions134of the active pillars130. Further, the common bit lines122may extend in a second direction, which is parallel with a top surface of the semiconductor substrate110and perpendicular to the first direction, to act as bit lines. A second interlayer insulation layer1410may be disposed between the first gate electrodes142and the common bit lines122, thereby electrically insulating the common bit lines122from the first gate electrodes142.

The second gate electrodes162may be disposed on respective ones of sidewalls of the second channel regions between the second source regions136and the common drain regions134, and second gate dielectric layers161may be disposed between the second gate electrodes162and the second channel regions. In some embodiments, the second gate dielectric layers161may be disposed to surround the sidewalls of the second channel regions. Each of the second gate dielectric layers161may include, for example, at least one of a silicon oxide (SiO2) layer, a silicon nitride (SiN) layer, a silicon oxynitride (SiON) layer, a hafnium oxide (HfO2) layer, an aluminum oxide (Al2O3) layer and a tantalum oxide (TaO2) layer. The second gate electrodes162may be disposed to surround outer sidewalls of the second gate dielectric layers161opposite to the active pillars130(e.g., the second channel regions). Further, the second gate electrodes162may extend in the first direction to act as second word lines. A third interlayer insulation layer1610may be disposed between the common bit lines122and the second gate electrodes162, thereby electrically insulating the common bit lines122from the second gate electrodes162. The second gate electrodes161and the third interlayer insulation layer1610may be covered with a fourth interlayer insulation layer1710.

The second capacitors170may be disposed on respective ones of the second source regions136(e.g., the third regions) of the active pillars130. Each of the second capacitors170may include a storage node electrode172and a capacitor dielectric layer173. Further, each of the second capacitors170may include a plate electrode174which is disposed on a surface of the capacitor dielectric layer173opposite to the storage node electrodes172. The storage node electrodes172may be electrically connected to respective ones of the second source regions136. Each of the storage node electrodes172may include, for example, at least one of a doped silicon layer, a titanium (Ti) layer, a tantalum (Ta) layer, a ruthenium (Ru) layer, an iridium (Ir) layer, a tungsten (W) layer, a titanium nitride (TiN) layer, a tantalum nitride (TaN) layer, a ruthenium oxide (RuO2) layer and a tungsten nitride (WN) layer. The capacitor dielectric layer173may include, for example, at least one of a tantalum oxide (TaO2) layer, a zirconium oxide (ZrO2) layer, an aluminum oxide (Al2O3) layer and a hafnium oxide (HfO2) layer. The plate electrode174may include, for example, at least one of a doped silicon layer, a titanium (Ti) layer, a tantalum (Ta) layer, a ruthenium (Ru) layer, an iridium (Ir) layer, a tungsten (W) layer, a titanium nitride (TiN) layer, a tantalum nitride (TaN) layer, a ruthenium oxide (RuO2) layer and a tungsten nitride (WN) layer. The first source region132and the common drain region134disposed in one of the active pillars130as well as the first gate electrode142therebetween may constitute a first vertical transistor, that is, a lower vertical transistor (T1ofFIG. 1), and the second source region136and the common drain region134disposed in one of the active pillars130as well as the second gate electrode162therebetween may constitute a second vertical transistor, that is, an upper vertical transistor (T2ofFIG. 1).

As described above, bit signals may be applied to the common bit lines122. If the first vertical transistors or the second vertical transistors are turned on, the bit signals may be transmitted to the first source regions132or the second source regions136through the turned-on vertical transistors. As a result, data corresponding to the bit signals may be stored in the first capacitors150or the second capacitors170. In some embodiments, the semiconductor device may be designed such that control signals are independently applied to the first gate electrodes142and the second gate electrodes162and the first capacitors150have a different capacitance from the second capacitors170. In such a case, a semiconductor memory device having multi-bit cells may be realized.

FIG. 2is a process flowchart illustrating a method of fabricating a semiconductor device according to an example embodiment, andFIGS. 3A to 18Aare plan views illustrating a method of fabricating a semiconductor device according to an example embodiment.FIGS. 3B to 18Bare cross sectional views taken along lines A-A′ ofFIGS. 3A to 18A, respectively.FIGS. 3C to 18Care cross sectional views taken along lines B-B′ ofFIGS. 3A to 18A, respectively.

Referring toFIGS. 2(a block210),3A to5A,3B to5B, and3C to5C, first capacitors150may be formed in respective ones of trenches114of a semiconductor substrate110. Specifically, the semiconductor substrate110may be provided. The semiconductor substrate110may be, for example, a p-type substrate. A plate electrode154may be formed in the semiconductor substrate110. The plate electrode154may be a well region which is heavily doped with impurities. In some embodiments, when the semiconductor substrate110is doped with p-type impurities, the plate electrode154may be doped with n-type impurities. In such a case, the plate electrode154may be formed by implanting phosphorous (P) ions or arsenic (As) ions into the semiconductor substrate110with a relatively high dose. A depth and a thickness of the plate electrode154may be appropriately adjusted in consideration of a final height (or a depth) of the first capacitors150completed after active pillars are formed in a subsequent process.

Referring toFIGS. 4A,4B and4C, trenches114may be formed in the semiconductor substrate110. Specifically, a hard mask layer may be formed on the semiconductor substrate110. The hard mask layer may be formed of a material layer having an etch selectivity with respect to the semiconductor substrate110. For example, the hard mask layer may be formed of a nitride layer or an oxide layer. In some embodiments, the hard mask layer may be formed using an evaporation process, a coating process, a chemical vapor deposition (CVD) process, a sputtering process or the like. A photoresist pattern (not shown) may be formed on the hard mask layer, and the hard mask layer may be etched using the photoresist pattern as an etch mask to form a hard mask pattern112. The hard mask pattern112may be formed to have holes penetrating the hard mask layer, and the holes may be formed to have a predetermined width. The semiconductor substrate110may be etched using the hard mask pattern112as an etch mask to form the trenches114in the semiconductor substrate110. The trenches114may be formed such that bottom surfaces of the trenches114are located in the plate electrode154. The photoresist pattern may be removed before or after formation of the trenches114.

Referring toFIGS. 5A,5B and5C, the first capacitors150may be formed in respective ones of the trenches114. Specifically, a capacitor dielectric layer153may be conformally formed in the trenches114. The capacitor dielectric layer153may be formed of an oxide layer, for example, at least one of a tantalum oxide (TaO2) layer, a zirconium oxide (ZrO2) layer, an aluminum oxide (Al2O3) layer and a hafnium oxide (HfO2) layer. The capacitor dielectric layer153may be formed using a chemical vapor deposition (CVD) process, an evaporation process or an atomic layer deposition (ALD) process. A storage node electrode layer may be formed to fill the trenches114surrounded by the capacitor dielectric layer153. The storage node electrode layer may be formed to include, for example, a doped silicon layer, a titanium (Ti) layer, a tantalum (Ta) layer, a ruthenium (Ru) layer, an iridium (Ir) layer, a tungsten (W) layer, a titanium nitride (TiN) layer, a tantalum nitride (TaN) layer, a ruthenium oxide (RuO2) layer or a tungsten nitride (WN) layer. The storage node electrode layer may be formed using a chemical vapor deposition (CVD) process, an evaporation process, an atomic layer deposition (ALD) process or a sputtering process. The storage node electrode layer and the capacitor dielectric layer153may be planarized using a chemical mechanical polishing (CMP) process, thereby exposing a top surface of the hard mask pattern112. As result, storage node electrodes152separated from each other may be formed in respective ones of the trenches114. The capacitor dielectric layer153and the storage node electrode152in each trench114may constitute one of the first capacitors150, and the first capacitors150may share the plate electrode154.

Referring toFIGS. 2(a block220),6A,6B and6C, active pillars130may be formed on the semiconductor substrate110. The active pillars130may be formed not to overlap with the first capacitors150in a plan view. Specifically, the semiconductor substrate110including the first capacitors150may be partially and anisotropically etched to form the active pillars130that relatively protrude from the remaining portion of the substrate. The first capacitors150may also be etched during an etch process for forming the active pillars130. That is, the storage node electrodes152and the capacitor dielectric layer153may be etched during formation of the active pillars130. Thus, a height of the first capacitors150may be reduced. After the etch process for forming the active pillars130, the substrate including the active pillars130may be cleaned using a first standard cleaning (SC1) solution and a buffer oxide etchant (BOE) to remove contaminants and/or byproducts that remain on a surface of the substrate. The SC1solution is a chemical solution containing ammonium hydroxide (NH4OH), hydrogen peroxide (H2O2) and de-ionized water. Accordingly, the active pillars130may be formed on the semiconductor substrate110between the first capacitors150, as illustrated inFIG. 6B. As described above, the height of the first capacitors150may be determined after the active pillars130are formed. After formation of the active pillars130, a top surface of the plate electrode154may be located at a first depth D1from a top surface of the recessed semiconductor substrate110and a bottom surface of the plate electrode154may be located at a second depth D2from the top surface of the recessed semiconductor substrate110. The first depth D1may be less than a depth of the first capacitors150, and the second depth D2may be greater than the depth of the first capacitors150.

Referring toFIGS. 2(a block230),7A to12A,7B to12B, and7C to12C, pillar connection patterns133may be formed to electrically connect the storage node electrodes152of the first capacitors150to first source regions132formed in first regions (e.g., lower portions) of the active pillars130. Specifically, a spacer oxide layer710and a spacer nitride layer720may be sequentially formed on the substrate including the first capacitors150and the active pillars130, as illustrated inFIGS. 7A,7B and7C. The spacer oxide layer710and the spacer nitride layer720may be formed to conformally cover the top surface of the recessed semiconductor substrate110, sidewalls of the active pillars130, and sidewalls and top surfaces of the hard mask pattern112. The spacer oxide layer710and the spacer nitride layer720may be formed using a chemical vapor deposition (CVD) process, an atomic layer deposition (ALD) process or an evaporation process.

Referring toFIGS. 8A,8B,8C,9A,9B and9C, portions of the spacer oxide layer710and the spacer nitride layer720may be removed to expose the first regions932(e.g., the lower portions) of the active pillars130. According to an example embodiment, the spacer nitride layer720may be anisotropically etched to selectively expose the spacer oxide layer710on the top surface of the recessed semiconductor substrate110and on the top surface of the hard mask pattern112, as illustrated inFIGS. 8A,8B and8C. Subsequently, the exposed spacer oxide layer710may be etched using an isotropic etch process. In some embodiments, the isotropic etch process may be performed using a wet etch process. The wet etch process may be performed with a wet etchant, for example, a hydrofluoric acid (HF) solution or a buffered oxide etchant (BOE). As the time elapses during the wet etch process, the exposed spacer oxide layer710on the recessed semiconductor substrate110may be removed and the spacer oxide layer710on the sidewalls of the active pillars130may be additionally etched. As a result, the spacer oxide layer710on the lower sidewalls of the active pillars130may be selectively removed and the spacer nitride layer720covering the lower sidewalls of the active pillars130may be lifted off. Thus, the first regions932of the active pillars130may be exposed, as illustrated inFIGS. 9A,9B and9C. Exposed areas of the first regions932may be controlled by adjusting a wet etch process condition, for example, a concentration of the wet etchant, a wet etch process temperature and/or a wet etch time.

An impurity injection process may be applied to the active pillars130to form first source regions132in respective ones of the first regions932. The impurity injection process may be, for example, an ion implantation process or a plasma doping process. In some embodiments, the first source regions132may be formed by implanting n-type impurity ions such as phosphorus ions or arsenic ions into the active pillars130at a tilted angle with respect to the sidewalls of the active pillars130. The tilted ion implantation process may be applied to only a portion of a sidewall of each first region932. In such a case, the first source regions132may be formed only at a portion of a sidewall of each first region932. Alternatively, the tilted ion implantation process may be applied to entire regions of the sidewalls of the first regions932by rotating the semiconductor substrate110during the tilted ion implantation process. In such a case, the first source regions132may be formed to surround the sidewalls of the first regions932. In some embodiments, the first source regions132may be formed using a plasma doping process. The plasma doping process may be performed by generating plasma using an n-type doping gas (e.g., a phosphorus gas or an arsenic gas) as a reaction gas and by doping the first regions932with the n-type doping gas. The first source regions132may be formed only at the sidewall surfaces of the first regions932or even in the bulk regions of the first regions932.

Referring toFIGS. 10A,10B and10C, a conductive layer1010may be formed on the substrate including the first source regions132. The conductive layer1010may be formed by depositing a conductive material to fill spaces between the active pillars130and by recessing the conductive material to have a predetermined thickness (e.g., a predetermined vertical height) which is less than a height of the first source regions132. The conductive material may be deposited using a chemical vapor deposition (CVD) process, a sputtering process or the like, and the conductive material may be recessed using a wet etching process or a dry etching process. The thickness (e.g., a vertical height) of the conductive layer1010may be controlled by some process conditions, for example, a deposition condition and/or an etch condition of the conductive material. The conductive layer1010may be formed to include, for example, a doped silicon layer, a metal layer or a metal nitride layer. The metal layer may be a titanium (Ti) layer, a tantalum (Ta) layer, a tungsten (W) layer or a ruthenium (Ru) layer, and the metal nitride layer may be a titanium nitride (TiN) layer, a tantalum nitride (TaN) layer, a tungsten nitride (WN) layer or a ruthenium nitride (Ru N) layer.

Referring toFIGS. 11A,11B and11C, sacrificial layer patterns1110may be formed on portions of the conductive layer1010. Each of the sacrificial layer patterns1110may be formed to cover a portion of a sidewall of each active pillar130and to overlap with a portion of the conductive layer1010between the storage node electrode152of the first capacitor150and the first source region132of the active pillar130adjacent thereto in a plan view. The sacrificial layer patterns1110may be photoresist patterns, but not limited thereto. For example, the sacrificial layer patterns1110may be formed of any material having an etch selectivity with respect to the conductive layer1010. In some embodiments, forming the sacrificial layer patterns1110may include forming a sacrificial layer, forming photoresist patterns on the sacrificial layer, and etching the sacrificial layer using the photoresist patterns as etch masks. The sacrificial layer may be formed of a spin-on-carbon (SOC) material or an oxide material. The sacrificial layer may be formed using a coating process or a chemical vapor deposition (CVD) process and may be etched using a dry etching process or a wet etching process.

Referring toFIGS. 12A,12B and12C, the conductive layer1010may be patterned using the sacrificial layer patterns1110as etch masks, thereby forming pillar connection patterns133that electrically connect the storage node electrodes152of the first capacitors150to the first source regions132of the active pillars130. As illustrated inFIG. 12A, each of the pillar connection patterns133may be formed to have a predetermined line width and to extend along a surface of the semiconductor substrate110from a top surface of the storage node electrode152toward the first source region132of the active pillar130adjacent thereto. After the pillar connection patterns133are formed, the spacer nitride layer720may be removed.

Referring toFIGS. 2(a block240),13A,13B and13C, first gate dielectric layers141may be formed on respective ones of sidewalls of the active pillars130and first gate electrodes142may be formed on respective ones of outer sidewalls of the first gate dielectric layers141opposite to the active pillars130. For example, the first gate dielectric layers141and the first gate electrodes142may be formed to surround first channel regions of the active pillars130, which are located on the first source regions132. Specifically, a first interlayer insulation layer1310having a predetermined thickness may be formed on the substrate including the pillar connection patterns133. The predetermined thickness of the first interlayer insulation layer1310may be determined in consideration of a vertical height of the first source regions132. For example, the first interlayer insulation layer1310may be formed to cover the first source regions132and the pillar connection patterns133.

The active pillars130may then be oxidized to form a dielectric layer on the sidewalls of the active pillars130over the first source regions132. Subsequently, a conductive layer having a predetermined vertical thickness may be formed on the first interlayer insulation layer1310, and the conductive layer may then be patterned to form first gate electrodes142that surround the first channel regions of the active pillars130and extend in one direction. The conductive layer having the predetermined vertical thickness may be formed by depositing a conductive material on the first interlayer insulation layer1310and by recessing the conductive material, and the conductive layer may be patterned to form the first gate electrodes142extending in one direction as illustrated inFIG. 13A. Further, the dielectric layers between the first gate electrodes142and the active pillars130may correspond to the first gate dielectric layers141. A vertical height of the first gate electrodes142may be determined in consideration of a length of channel layers (e.g., the first channel regions) which are modulated or controlled by the first gate electrodes142. The first gate electrodes142may be formed to include, for example, a doped silicon layer, a metal layer or a metal nitride layer. The metal layer may be a titanium (Ti) layer, a tantalum (Ta) layer, a tungsten (W) layer or a ruthenium (Ru) layer, and the metal nitride layer may be a titanium nitride (TiN) layer, a tantalum nitride (TaN) layer, a tungsten nitride (WN) layer or a ruthenium nitride (RuN) layer. The conductive material for forming the first gate electrodes142may be deposited using a chemical vapor deposition (CVD) process, a sputtering process, an evaporation process or the like.

In some embodiments, a channel ion implantation process may be applied to the first channel regions of the active pillars130before the dielectric layer is formed on sidewalls of the active pillars130. Impurity ions injected by the channel ion implantation process may have an opposite conductivity type to the first source regions132. For example, when the first source regions132have an n-type, Impurity ions injected by the channel ion implantation process may have a p-type. The channel ion implantation process may be performed to adjust a threshold voltage of vertical transistors including the first gate electrodes142.

Referring toFIGS. 2(a block250),14A and15A,14B and15B, and14C and15C, common drain regions134may be formed in respective ones of second regions of the active pillars130which are located over the first channel regions, and common bit lines122may be formed to surround sidewalls of the common drain regions134. Specifically, referring toFIGS. 14A,14B and14C, a second interlayer insulation layer1410having a predetermined vertical height may be formed on the first interlayer insulation layer1310. The predetermined vertical height of the second interlayer insulation layer1410may be determined in consideration of the heights of the first gate electrodes142and the common drain regions134. For example, the second interlayer insulation layer1410may be formed to cover the first gate electrodes142and to expose the second regions1434of the active pillars130.

Subsequently, an impurity injection process may be applied to the second regions1434of the active pillars130to form common drain regions134in respective ones of the second regions1434. The common drain regions134may be formed to have the same conductivity type as the first source regions132. That is, when the first source regions132are formed to have an n-type, the common drain regions134may also be formed to have an n-type. The impurity injection process for forming the common drain regions134may be, for example, an ion implantation process or a plasma doping process. In some embodiments, the common drain regions134may be formed by implanting n-type impurity ions such as phosphorus ions or arsenic ions into the second regions1434of the active pillars130at a tilted angle with respect to the sidewalls of the active pillars130. Each of the common drain regions134may be formed only at a portion of a sidewall of each second region1434or at an entire sidewall of each second region1434. In some embodiments, the common drain regions134may be formed using a plasma doping process. The plasma doping process may be performed by generating plasma using an n-type doping gas (e.g., a phosphorus gas or an arsenic gas) as a reaction gas and by doping the second regions1434with the n-type doping gas. The common drain regions134may be formed only at the sidewall surfaces of the second regions1434or even in the bulk regions of the second regions1434.

Referring toFIGS. 15A,15B and15C, a conductive layer having a predetermined thickness (e.g., a predetermined vertical height) may be formed on the second interlayer insulation layer1410, and the conductive layer may be patterned to form the common bit lines122surrounding sidewalls of the common drain regions134and extending in one direction. Specifically, the conductive layer having the predetermined thickness may be formed by depositing a conductive material on the second interlayer insulation layer1410and by recessing the conductive material. Subsequently, the conductive layer may be patterned to form the common bit lines122that extend in one direction to have line shapes, as illustrated inFIG. 15A. The common bit lines122may be formed to intersect the first gate electrodes142when viewed from a plan view. In some embodiments, the common bit lines122may be arrayed to cross the first gate electrodes142at right angles in plan view. A vertical height of the common bit lines122may be determined in consideration of a vertical height of the common drain regions134. The common bit lines122may be formed to include, for example, a doped silicon layer, a metal layer or a metal nitride layer. The metal layer may include a titanium (Ti) layer, a tantalum (Ta) layer, a tungsten (W) layer or a ruthenium (Ru) layer, and the metal nitride layer may include a titanium nitride (TiN) layer, a tantalum nitride (TaN) layer, a tungsten nitride (WN) layer or a ruthenium nitride (RuN) layer. The conductive material for forming the common bit lines122may be deposited using a chemical vapor deposition (CVD) process, a sputtering process, an evaporation process or the like.

According to some embodiments, the dielectric layer formed on the active pillars130to form the first gate dielectric layers141may be removed prior to formation of the common drain regions134shown inFIGS. 14A,14B and14C or prior to formation of the common bit lines122shown inFIGS. 15A,15B and15C.

Referring toFIGS. 2(a block260),16A,16B and16C, second gate dielectric layers161may be formed on respective ones of sidewalls of the active pillars130and second gate electrodes162may be formed on respective ones of outer sidewalls of the second gate dielectric layers161opposite to the active pillars130. For example, the second gate dielectric layers161and the second gate electrodes162may be formed to surround second channel regions of the active pillars130, which are located on the common drain regions134. Specifically, referring toFIGS. 16A,16B and16C, a third interlayer insulation layer1610having a predetermined thickness may be formed on the substrate including the common bit lines122. The predetermined thickness of the third interlayer insulation layer1610may be determined in consideration of a vertical height of the common drain regions134. For example, the third interlayer insulation layer1610may be formed to cover the second interlayer insulation layer1410, the common bit lines122and the common drain regions134.

The active pillars130may then be oxidized to form a dielectric layer on the sidewalls of the active pillars130over the common drain regions134. Subsequently, a conductive material may be formed on the third interlayer insulation layer1610, and the conductive material may be recessed to form a conductive layer having a predetermined thickness. The conductive layer may then be patterned to form second gate electrodes162that surround the second channel regions of the active pillars130and extend in one direction. As a result, the second gate electrodes162may be formed to have line shapes, as illustrated inFIG. 16A. The dielectric layers between the second gate electrodes162and the active pillars130may correspond to the second gate dielectric layers161. The second gate electrodes162may extend in the same direction as the first gate electrodes142and may be perpendicular to the common bit lines122in a plan view. A vertical height of the second gate electrodes162may be determined in consideration of a length of channel layers (e.g., the second channel regions) which are modulated or controlled by the second gate electrodes162. The second gate electrodes162may be formed to include, for example, a doped silicon layer, a metal layer or a metal nitride layer. The metal layer may be a titanium (Ti) layer, a tantalum (Ta) layer, a tungsten (W) layer or a ruthenium (Ru) layer, and the metal nitride layer may be a titanium nitride (TiN) layer, a tantalum nitride (TaN) layer, a tungsten nitride (WN) layer or a ruthenium nitride (Ru N) layer. The conductive material for forming the second gate electrodes162may be deposited using a chemical vapor deposition (CVD) process, a sputtering process, an evaporation process or the like.

In some embodiments, a channel ion implantation process may be applied to the second channel regions of the active pillars130before the dielectric layer is formed on sidewalls of the active pillars130. Impurity ions injected by the channel ion implantation process may have an opposite conductivity type to the common drain regions134. For example, when the common drain regions134have an n-type, Impurity ions injected by the channel ion implantation process may have a p-type. The channel ion implantation process may be performed to adjust a threshold voltage of vertical transistors including the second gate electrodes162.

Referring toFIG. 2(a block270),17A,17B and17C, second source regions136may be formed in respective ones of third regions1734(e.g., topmost regions) of the active pillars130which are located over the second channel regions surrounded by the second gate electrodes162. Specifically, a fourth interlayer insulation layer1710having a predetermined vertical height may be formed on the third interlayer insulation layer1610. The predetermined vertical height of the fourth interlayer insulation layer1710may be determined in consideration of the heights of the second gate electrodes162. For example, the fourth interlayer insulation layer1710may be formed to cover the second gate electrodes162and to expose the third regions1734of the active pillars130.

Subsequently, an impurity injection process may be applied to the third regions1734of the active pillars130to form the second source regions136in respective ones of the third regions1734. The second source regions136may be formed to have the same conductivity type as the first source regions132. That is, when the first source regions132are formed to have an n-type, the second source regions136may also be formed to have an n-type. The impurity injection process for forming the second source regions136may be, for example, an ion implantation process or a plasma doping process. In some embodiments, the second source regions136may be formed by implanting n-type impurity ions such as phosphorus ions or arsenic ions into the third regions1734of the active pillars130at a tilted angle with respect to the sidewalls of the active pillars130. Each of the second source regions136may be formed only at a portion of a sidewall of each third region1734. Alternatively, each of the second source regions136may be formed at an entire sidewall of each third region1734by rotating the semiconductor substrate110during the tilted ion implantation process. In some embodiments, the second source regions136may be formed using a plasma doping process. The plasma doping process may be performed by generating plasma using an n-type doping gas (e.g., a phosphorus gas or an arsenic gas) as a reaction gas and by doping the third regions1734with the n-type doping gas. The second source regions136may be formed only at the sidewall surfaces of the third regions1734or even in the bulk regions of the third regions1734.

According to some embodiments, in the event that the active pillars130do not have sufficient heights to form the second source regions136, semiconductor pillars such as silicon pillars may be additionally formed on the active pillars130using an epitaxial growth technique. In such a case, the second source regions136may be formed in respective ones of the semiconductor pillars. Similarly, even when the active pillars130do not have sufficient heights to form the common drain regions134, the second channel regions surrounded by the second gate electrodes162, and the second source regions136, the semiconductor pillars may also be additionally formed on the active pillars130. The semiconductor pillars may be formed using one of various epitaxial growth techniques, for example, a silicon epitaxial growth technique, a germanium epitaxial growth technique or a silicon-germanium epitaxial growth technique.

Referring toFIGS. 2(a block280),18A,18B and18C, second capacitors170may be formed on respective ones of the second source regions136. Specifically, the hard mask pattern112may be removed, and a storage node electrode layer may be formed on the fourth interlayer insulation layer1710and the second source regions136. The storage node electrode layer may be patterned to form storage node electrodes172which are electrically connected to respective ones of the second source regions136. For example, the storage node electrode layer may be formed on respective ones of the second source regions136. The storage node electrode layer may be formed to include, for example, a doped silicon layer, a metal layer, a metal nitride layer or a conductive metal oxide layer. The metal layer may be a titanium (Ti) layer, a tantalum (Ta) layer, a tungsten (W) layer, an iridium (Ir) layer or a ruthenium (Ru) layer, and the metal nitride layer may be a titanium nitride (TiN) layer, a tantalum nitride (TaN) layer or a tungsten nitride (WN) layer. The conductive metal oxide layer may be a ruthenium oxide (RuO2) layer or an iridium oxide (IrO2) layer. The storage node electrode layer may be formed using a chemical vapor deposition (CVD) process, a sputtering process, an evaporation process or the like.

A capacitor dielectric layer173may be formed on the storage node electrodes172. The capacitor dielectric layer173may be formed to include, for example, at least one of a tantalum oxide (TaO2) layer, a zirconium oxide (ZrO2) layer, an aluminum oxide (Al2O3) layer and a hafnium oxide (HfO2) layer. The capacitor dielectric layer173may be formed using a chemical vapor deposition (CVD) process, an atomic layer deposition (ALD) process or the like. A plate electrode layer (174ofFIG. 1B) may then be formed on the capacitor dielectric layer173. The plate electrode layer174may be formed to include, for example, at least one of a doped silicon layer, a titanium (Ti) layer, a tantalum (Ta) layer, a ruthenium (Ru) layer, an iridium (Ir) layer, a tungsten (W) layer, a titanium nitride (TiN) layer, a tantalum nitride (TaN) layer, a ruthenium oxide (RuO2) layer and a tungsten nitride (WN) layer. The plate electrode layer174may be formed using a chemical vapor deposition (CVD) process, a sputtering process, an evaporation process or the like.

The semiconductor device including the unit cells shown inFIGS. 1A and 1Bmay be fabricated using the processes described above. As described above, according to the embodiments, multi-bit cells may be realized by forming active pillars on a semiconductor substrate, by forming vertical transistors in and on the active pillars, and by forming capacitors below and on the active pillars. Thus, the integration density of the semiconductor device may be improved in a limited planar area.