Digital data transmission systems

In a receiver arrangement for a quadrature phase-shift digital data transmission system including an adaptive equalizing regenerator, a phase control signal for the local oscillator is derived from an output of the regenerator and decision feedback signals within the regenerator are applied by way of balanced current switching circuits.

The present invention relates to digital data transmission systems. 
In particular the invention relates to receiver arrangements for quadrature 
phase shift transmission systems. The process of phase demodulation 
requires that a reference oscillation at the carrier frequency be 
generated in the correct phase relationship with respect to the phases 
representing the four possible signal states. This process has in the past 
been performed using a frequency multiplier type phase-locked loop 
extraction circuit. However, in more recent work aimed at reducing the 
bandwidth of the channel filters in order to increase spectrum efficiency 
the frequency multiplier technique has been found unsatisfactory. 
According to one aspect of the present invention in a receiver arrangement 
for a quadrature phase shift digital data transmission system comprising 
quadrature phase detectors, a local oscillator, and an adaptive equalising 
regenerator for regenerating digital data signals detected by said phase 
detectors, there are provided means responsive to elements of cross-talk 
in said digital data signals to derive a phase control signal for said 
local oscillator. 
Preferably said regenerator includes in respect of each phase detector a 
plurality of threshold detectors connected to receive digital data signals 
from the respective phase detector, and said phase control signal is 
arranged to be derived in dependence upon the outputs of some at least of 
the threshold detectors associated with each of said phase detectors. 
According to another aspect of the present invention in a receiver 
arrangement for a quadrature phase shift digital data transmission system, 
an adaptive equalising regenerator for regenerating digital data signals 
detected by quadrature phase detectors of the receiver comprises, in 
respect of each phase detector, a plurality of threshold detectors and 
means selectively to add current or voltage increments to output signals 
from the respective phase detector before said output signals are applied 
to said threshold detectors in dependence upon the value or values of one 
or more preceding digits. 
Preferably triangular waveforms are superimposed on reference voltages 
provided for some at least of said threshold detectors, said triangular 
waveforms enabling the adjustment of the mean levels of said threshold 
voltages and of the values of the current or voltage increments added to 
said output signals from the phase detectors.

Referring first to FIG. 1, the receiver arrangement comprises a receiver 
head and down changer 1 which is arranged to receive phase-shift modulated 
radio frequency signals and to apply corresponding intermediate frequency 
signals to a pair of phase detectors 2 and 3. Local oscillator signals at 
the intermediate frequency are applied in quadrature to the two detectors 
from a voltage-controlled oscillator 4, there being for example a ninety 
degree phase shift circuit 5 in the path from the oscillator 4 to the 
detector 3. 
Output signals from the phase detectors 2 and 3 are applied by way of 
respective low-pass filters 6 and 7 to a two-symbol cross-coupled adaptive 
equalising regnerator 8, which provides two streams of regenerated digits 
on paths 9 and 10 and a phase control voltage for the oscillator 4 by way 
of a differential amplifier 11 and a low-pass filter 12. 
Referring now to FIG. 2, which shows effectively half of the regenerator 8, 
signals from, say, the phase detector 2 are applied by way of the filter 6 
and a buffer amplifier 13 to a transmission path 14, which is connected in 
common to respective inputs of an upper threshold detector 15, a lower 
threshold detector 16 and a main threshold detector 17. The signals on the 
path 14 are not in general of ideal rectangular waveform, and the output 
decisions of the threshold detectors 15, 16 and 17 are entered into 
respective bistable circuits 18, 19 and 20 at approximately the midpoints 
of the received data digit periods under the control of timing signals or 
clock signals derived from, say, transitions in the signals on the path 
14. An output from the bistable circuit 20 is passed to the path 9, while 
an output from a corresponding bistable circuit (not shown) in the other 
half of the regenerator 8 is passed to the path 10 (FIG. 1). 
Connected to the transmission path 14 are four current switches 21 to 24 
which are arranged to apply to the line 14 currents of respective values 
dependent upon weighting signals applied to the switches 21 to 24 over 
paths 25 to 28. The current values are also dependent respectively on 
outputs from the bistable circuit 20, a further bistable circuit 29 and 
outputs from corresponding bistable circuits (not shown) in the other half 
of the regenerator 8. The bistable circuits 20 and 29 effectively store 
the values of the two digits preceding that present on the path 14 at any 
given time. 
Reference voltages for the threshold detectors 15, 16 and 17 are set up in 
a circuit 30, those for the detectors 15 and 16 having superimposed on 
them anti-phase triangular waveforms from a generator 31. These triangular 
waveforms enable logic circuits (not shown) receiving signals from the 
threshold circuits 15, 16 and 17, and the corresponding circuits in the 
other half (not shown) of the regenerator 8, to adapt the mean values of 
the reference or threshold voltages set up in the circuit 30 to suit the 
amplitudes of the signals on the path 14, and also to adapt the values of 
the weighting signals applied to the current switches 21 to 24. In this 
way the signal levels on the path 14 and the threshold voltages are 
arranged to vary so that the received data digits are equalised and 
regenerated accurately. 
Referring to FIG. 3, to derive a measure of a particular contribution to 
the inter-symbol degradation of each data digit stream, correlations are 
made between the appropriate delayed digit signal sequences and the 
degraded signals. In this way the various interference contributions may 
be separately determined. Positive and negative interferences produce 
corresponding effects on the digital sequence at the output of say, the 
detector 15, and the output of this detector is correlated digitally in a 
circuit 40 with each of the interfering sequences, (for example, with the 
main signal delayed by one symbol period, from the output of the bistable 
circuit 20, in which case intersymbol interference from the previous bit 
is measured). The output of the correlator 40 is converted into a constant 
amplitude bipolar signal and used via a low-pass filter (not shown) and a 
high-gain amplifier (not shown) as the weighting signal for a respective 
one of the switches 21 to 24. The triangular waveform sweep voltage 
superimposed on the upper and lower decision reference voltages enables, 
say, the mean levels of the respective bipolar signals to be made 
proportional to the departure of the degraded signals from the respective 
threshold voltages, at least over a range of levels determined by the 
amplitude of the triangular waveform. 
Referring now to FIG. 4, when the phase of the local oscillator signals is 
substantially correct the two data streams are correctly equalised as 
shown in waveforms 32 and 33, where the dashed lines 34, 35 and 36 
represent respectively the upper, main and lower threshold voltages. If 
the local oscillator phase is incorrect in either sense there is a degree 
of cross-talk between the data streams such that the waveform 33 say 
becomes distorted in one or other sense as shown by waveforms 37 and 38. 
To derive a phase correcting voltage from these waveforms a logic function 
L is developed by means of a logic circuit arrangement 39 such that 
EQU L=(U.sub.B .multidot.M.sub.B +L.sub.B .multidot.M.sub.B).sym.M.sub.A 
where the terms M.sub.A, M.sub.B, U.sub.B and L.sub.B have the value "1" 
when the signal values applied to the respective threshold circuits are 
above the respective main thresholds of the A and B channels and the upper 
and lower thresholds of the B channel respectively, and the operators ".", 
"+" and ".sym." are logic "AND", "OR" and "Exclusive OR" respectively. 
By inspection it will be seen that the function L has the value "0" 
continuously for the waveform 37 and the value "1" continuously for the 
waveform 38. 
For lesser phase errors than those represented by the waveforms 37 and 38 
the triangular waveforms superimposed on the threshold voltages 34 and 36 
have the effect of producing alternating values for L such that the mean 
value of this function varies progressively between the two extremes over 
a range of phase errors centred on the correct phase. 
Corresponding logic functions L developed in the two halves of the 
regenerator 8 are applied to the differential amplifier 11 to derive the 
phase control voltage for the local oscillator 4. 
Referring now to FIG. 5, which shows in detail one of the current switches 
21 to 24, for example the switch 24, signals representing the value of the 
digit last received and its inverse are applied from the bistable circuit 
20 (FIG. 2) to inputs 41 and 42. By means of these digit value signals one 
or other of two long-tail pair switching circuits 43 and 44 is arranged to 
connect a respective path 45 or 46 to the path 14, in dependence upon 
whether the last received digit was a one or a zero, the other path 45 or 
46 then being connected to a 6 volt supply line. 
A substantially constant current from a source 47 is split between the two 
paths 45 and 46 by a long-tail pair differential amplifier circuit 48 in 
dependence upon the value of the weighting signal applied over the path 
28. 
By means of this circuit a current can be effectively added or subtracted 
from the incoming signal on the path 14 in dependence upon whether the 
last received digit was a one or a zero, the current having any negative 
or positive value over a range of values in dependence upon the weighting 
signal on the path 28. Thus, denoting the currents in the paths 45 and 46 
as I.sub.1 and I.sub.2 respectively and the constant current from the 
source 47 as I.sub.o : 
EQU I.sub.1 +I.sub.2 =I.sub.o 
Writing: 
EQU I.sub.1 =1/2(I.sub.1 +I.sub.2)+1/2(I.sub.1 -I.sub.2) 
it can be seen that: 
EQU I.sub.1 =1/2I.sub.o +1/2(I.sub.1 -I.sub.2) 
Similarly: 
EQU I.sub.2 =1/2I.sub.o -1/2(I.sub.1 -I.sub.2) 
Thus there is a constant standing current of 1/2I.sub.o flowing in the path 
14 by way of the switching circuits 43 and 44 with 1/2(I.sub.1 -I.sub.2) 
being added to this standing current when the signal at input 41 is a zero 
and being subtracted from this standing current when the signal at input 
41 is a one. It can be seen that the current difference (I.sub.1 -I.sub.2) 
will be dependent upon the weighting signal on the input path 28. 
The transistors used in the circuit arrangement shown in FIG. 5 are all 
N-P-N transistors, resulting in fast switching and ease of integration.