Switch/network adapter port incorporating shared memory resources selectively accessible by a direct execution logic element and one or more dense logic devices

An enhanced switch/network adapter port (“SNAP™”) including collocated shared memory resources (“SNAPM™”) in a dual in-line memory module (“DIMM”) or any other memory module format for clustered computing systems employing direct execution logic such as multi-adaptive processor elements (“MAP®”, all trademarks of SRC Computers, Inc.). Functionally, the SNAPM modules incorporate and properly allocate memory resources so that the memory appears to the associated dense logic device(s) (e.g. a microprocessor) to be functionally like any other system memory such that no time penalties are incurred when accessing it. Through the use of a programmable access coordination mechanism, the control of this memory can be handed off to the SNAPM memory controller and, once in control, the controller can move data between the shared memory resources and the computer network such that the transfer is performed at the maximum rate that the memory devices themselves can sustain. This provides the highest performance link to the other network devices such as MAP® elements, common memory boards and the like.

BACKGROUND OF THE INVENTION

The present invention relates, in general, to the field of reconfigurable processor-based computing systems. More particularly, the present invention relates to a switch/network adapter port incorporating shared memory resources selectively accessible by a direct execution logic element (such as a reconfigurable computing element comprising one or more field programmable gate arrays “FPGAs”) and one or more dense logic devices comprising commercially available microprocessors, digital signal processors (“DSPs”), application specific integrated circuits (“ASICs”) and other typically fixed logic components having relatively high clock rates.

As disclosed in one or more representative embodiments illustrated and described in the aforementioned patents and patent applications, SRC Computers, Inc. proprietary Switch/Network Adapter Port technology (SNAP™, a trademark of SRC Computers, Inc., assignee of the present invention) has previously been enhanced such that the signals from two or more dual in-line memory module (“DIMM”) (or Rambus™ in-line memory module “RIMM”) slots are routed to a common control chip.

Physically, in a by-two configuration, two DIMM form factor switch/network adapter port boards may be coupled together using rigid flex circuit construction to form a single assembly. One of the DIMM boards may also be populated with a control field programmable gate array (“FPGA”) which may have the signals from both DIMM slots routed to it. The control chip then samples the data off of both slots using the independent clocks of the slots. The data from both slots is then used to form a data packet that is then sent to other parts of the system. In a similar manner, the technique may be utilized in conjunction with more than two DIMM slots, for example, four DIMM slots in a four-way interleaved system.

In operation, an interleaved memory system may use two or more memory channels running in lock-step wherein a connection is made to one of the DIMM slots and the signals derived are used in conjunction with the original set of switch/network adapter port board signals. In operation, this effectively doubles (or more) the width of the data bus into and out of the memory. This technique can be implemented in conjunction with the proper selection of a memory and input/output (“I/O”) controller (“North Bridge”) chip that supports interleaved memory.

Currently described in the literature is a reconfigurable computing development environment called “Pilchard” which plugs into a personal computer DIMM slot. See, for example, “Pilchard—A Reconfigurable Computing Platform with Memory Slot Interface” developed at the Chinese University of Hong Kong under a then existing license and utilizing SRC Computers, Inc. technology. The Pilchard system, and other present day systems rely on relatively long column address strobe (“CAS”) latencies to enable the FPGA to process the memory transactions and are essentially slaves to the memory and I/O controller.

With the speed gap ever increasing between the processor speeds and the memory subsystem, processor design has been optimized to keep the cache subsystem filled with data that will be needed by the program currently executing on the processor. Thus, the processor itself is becoming less efficient at performing the large block transfers that may be required in certain systems utilizing currently available switch/network devices.

SUMMARY OF THE INVENTION

In order to increase processor operational efficiency in conjunction with a switch/network adapter port, the present invention advantageously incorporates and properly allocates memory resources, such as dynamic random access memory (“DRAM”), located on the module itself. Functionally, this memory appears to the dense logic device (e.g. a microprocessor) to be like other system memory and no time penalties are incurred when reading to, or writing from, it.

Through the use of an access coordination mechanism, the control of this memory can be handed off to the switch/network adapter port memory controller. Once in control, the controller can move data between the memory resources and the computer network, based for example, on control parameters that may be located in on-board registers. This data movement is performed at the maximum rate that the memory devices themselves can sustain, thereby providing the highest performance link to the other network devices such as direct execution logic devices such as Multi-Adaptive Processing elements (MAP® a trademark of SRC Computers, Inc.), common memory boards and the like.

Unlike the Pilchard system described previously, the system and method of the present invention does not need to rely on relatively long CAS memory latencies to enable the associated FPGA to process the memory transactions. Moreover, the system and method of the present invention functions as a true peer to the system memory and I/O controller and access to the shared memory resources is arbitrated for between the memory and I/O controller and the switch/network adapter port controller.

Further, with increasing system security demands, as well as other functions that require unique memory address access patterns, the addition of a programmable memory controller to the system/network adapter port control unit enables this improved system to meet these needs. Functionally, the memory controller is enabled such that the address access patterns utilized in the performance of the data movement to and from the collocated memory resources is programmable. This serves to effectively eliminate the performance penalty that is common when performing scatter/gather and other similar functions.

In a representative embodiment of the present invention disclosed herein, the memory and I/O controller, as well as the enhanced switch/network adapter port memory (“SNAPM™”) controller, can control the common memory resources on the SNAPM modules through the inclusion of various data and address switches (e.g. field effect transistors “FETs”, or the like) and tri-stable latches. These switching resources and latches are configured such that the data and address lines may be driven by either the memory and I/O controller or the SNAPM memory controller while complete DIMM (and RIMM or other memory module format) functionality is maintained. Specifically, this may be implemented in various ways including the inclusion of a number of control registers added to the address space accessible by the memory and I/O controller which are used to coordinate the use of the shared memory resources.

In operation, when the memory and I/O controller is in control, the SNAPM memory controller is barred from accessing the DRAM memory. Conversely, when the SNAPM memory controller is in control, the address/control and data buses from the memory and I/O controller are disconnected from the DRAM memory. However, the SNAPM memory controller continues to monitor the address and control bus for time critical commands such as memory refresh commands. Should the memory and I/O controller issue a refresh command while the SNAPM memory controller is in control of the DRAM memory, it will interleave the refresh command into its normal command sequence to the DRAM devices. Additionally, when the memory and I/O controller is in control, the SNAPM modules monitor the address and command bus for accesses to any control registers located on the module and can accept or drive replies to these commands without switching control of the collocated memory resources.

Functionally, the SNAPM controller contains a programmable direct memory access (“DMA”) engine which can perform random access and other DMA operations based on the state of any control registers or in accordance with other programmable information. The SNAPM controller is also capable of performing data re-ordering functions wherein the contents of the DRAM memory can be read out and then rewritten in a different sequence.

Particularly disclosed herein is a computer system comprising at least one dense logic device, a controller for coupling the dense logic device to a control block and a memory bus, a plurality of memory module slots coupled to the memory bus, an adapter port including shared memory resources associated with a subset of the plurality of memory module slots and a direct execution logic element coupled to the adapter port. The dense logic device and the direct execution logic element may both access the shared memory resources. In a preferred embodiment, the adapter port may be conveniently provided in a DIMM, RIMM or other memory module form factor.

Also disclosed herein is a computer system comprising at least one dense logic device, an interleaved controller for coupling the dense logic device to a control block and a memory bus, a plurality of memory slots coupled to the memory bus, an adapter port including shared memory resources associated with at least two of the memory slots and a direct execution logic element coupled to at least one of the adapter ports.

Further disclosed herein is a computer system including an adapter port for electrical coupling between a memory bus of the computer system and a network interface. The computer system comprises at least one dense logic device coupled to the memory bus and the adapter port comprises a memory resource associated with the adapter port and a control block for selectively enabling access by the dense logic device to the memory resource. In a particular embodiment disclosed herein, the computer system may further comprise an additional adapter port having an additional memory resource associated with it and the control block being further operative to selectively enable access by the dense logic device to the additional memory resource.

Broadly, the system and method of the present invention disclosed herein includes a switch/network adapter port with collocated memory that may be isolated to allow peer access to the memory by either a system memory and I/O controller or switch/network adapter port memory controller. The switch/network adapter port with on-board memory disclosed may be utilized as an interface itself and also allows the switch/network adapter port memory controller to operate directly on data retained in the shared memory resources. This enables it to prepare the data for transmission in operations requiring access to a large block of non-sequential data, such as scatter and gather. The system and method of the present invention described herein further discloses a switch/network adapter port with shared memory resources which incorporates a smart, fully parameterized DMA engine providing the capability of performing scatter/gather and other similar functions.

DESCRIPTION OF A REPRESENTATIVE EMBODIMENT

With reference now toFIG. 1, a functional block diagram of an exemplary embodiment of a computer system100is shown comprising a switch/network adapter port for clustered computers employing a chain of multi-adaptive processors functioning as direct execution logic elements in a DIMM format to significantly enhance data transfer rates over that otherwise available from the peripheral component interconnect (“PCI”) bus.

In the particular embodiment illustrated, the computer system100includes one or more dense logic devices in the form of processors1020and1021which are coupled to an associated memory and I/O controller104(e.g. a “North Bridge”). In the operation of the particular embodiment illustrated, the controller104sends and receives control information from a separate PCI control block106. It should be noted, however, that in alternative implementations of the present invention, the controller104and/or the PCI control block106(or equivalent) may be integrated within the processors102themselves and that the control block106may also be an accelerated graphics port (“AGP”) or system maintenance (“SM”) control block. The PCI control block106is coupled to one or more PCI card slots108by means of a relatively low bandwidth PCI bus110which allows data transfers at a rate of substantially 256 MB/sec. In alternative embodiments, the card slots108may alternatively comprise PCI-X, PCI Express, accelerated graphics port (“AGP”) or system maintenance (“SM”) bus connections.

The controller104is also conventionally coupled to a number of DIMM slots114by means of a much higher bandwidth DIMM bus116capable of data transfer rates of substantially 2.1 GB/sec. or greater. In accordance with a particular implementation of the system shown, a DIMM MAP® element112may be associated with, or physically located within, one of the DIMM slots114. Control information to or from the DIMM MAP® element112may be provided by means of a connection118interconnecting the PCI bus110and the DIMM MAP® element112. The DIMM MAP® element112then may be coupled to another clustered computer MAP® element by means of a cluster interconnect fabric connection120connected to MAP® chain ports. It should be noted that, the DIMM MAP® element12may also comprise a Rambus™ DIMM (“RIMM”) MAP® element.

Since the DIMM memory located within the DIMM slots114comprises the primary storage location for the microprocessor(s)1020,1021, it is designed to be electrically very “close” to the processor bus and thus exhibit very low latency. As noted previously, it is not uncommon for the latency associated with the DIMM to be on the order of only 25% of that of the PCI bus110. By, in essence, harnessing this bandwidth as an interconnect between computer systems100, greatly increased cluster performance may be realized as disclosed in the aforementioned patents and patent applications.

To this end, by placing the DIMM MAP® element112, in one of the PC's DIMM slots114, its control chip can accept the normal memory “read” and “write” transactions and convert them to a format used by an interconnect switch or network. To this end, each MAP® element112may also include chain ports to enable it to be coupled to other MAP® elements112. Through the utilization of the chain port to connect to the external clustering fabric over connection120, data packets can then be sent to remote nodes where they can be received by an identical board. In this particular application, the DIMM MAP® element112would extract the data from the packet and store it until needed by the receiving processor102.

This technique results in the provision of data transfer rates several times higher than that of any currently available PC interface such as the PCI bus110. However, the electrical protocol of the DIMMs is such that once the data arrives at the receiver, there is no way for a DIMM module within the DIMM slots114to signal the microprocessor102that it has arrived, and without this capability, the efforts of the processors102would have to be synchronized through the use of a continued polling of the DIMM MAP® elements112to determine if data has arrived. Such a technique would totally consume the microprocessor102and much of its bus bandwidth thus stalling all other bus agents.

To avoid this situation, the DIMM MAP® element112may be further provided with the connection118to allow it to communicate with the existing PCI bus110which could then generate communications packets and send them via the PCI bus110to the processor102. Since these packets would account for but a very small percentage of the total data moved, the low bandwidth effects of the PCI bus110are minimized and conventional PCI interrupt signals could also be utilized to inform the processor102that data has arrived. In accordance with another possible implementation, the system maintenance (“SM”) bus (not shown) could also be used to signal the processor102. The SM bus is a serial current mode bus that conventionally allows various devices on the processor board to interrupt the processor102. In an alternative embodiment, the accelerated graphics port (“AGP”) may also be utilized to signal the processor102.

With a DIMM MAP® element112associated with what might be an entire DIMM slot114, the system will allocate a large block of addresses, typically on the order of 1 GB, for use by the DIMM MAP® element112. While some of these can be decoded as commands, many can still be used as storage. By having at least as many address locations as the normal input/output (“I/O”) block size used to transfer data from peripherals, the conventional Intel™ chip sets used in most personal computers (including controller104) will allow direct I/O transfers into the DIMM MAP® element112. This then allows data to arrive from, for example, a disk and to pass directly into a DIMM MAP® element112. It then may be altered in any fashion desired, packetized and transmitted to a remote node over connection120. Because both the disk's PCI bus110and the DIMM MAP® element112and DIMM slots114are controlled by the PC memory controller104, no processor bus bandwidth is consumed by this transfer.

It should also be noted that in certain computer systems, several DIMMs within the DIMM slots114may be interleaved to provide wider memory access capability in order to increase memory bandwidth. In these systems, the previously described technique may also be utilized concurrently in several DIMM slots114. Nevertheless, regardless of the particular implementation chosen, the end result is a DIMM-based MAP® element112having one or more connections to the PCI bus110and an external switch or network over connection120which results in many times the performance of a PCI-based connection alone as well as the ability to process data as it passes through the interconnect fabric.

With reference additionally now toFIG. 2A, a functional block diagram of an exemplary embodiment of a switch/network adapter port200A incorporating collocated common memory resources in accordance with the present invention is shown. In this regard, like structure and functionality to that disclosed with respect to the foregoing figure is here like numbered and the foregoing description thereof shall suffice herefor. The switch/network adapter port with common memory (“SNAPM”)200A is shown in an exemplary by-two configuration of interleaved DIMM slot form factor SNAPM elements204(SNAPM A and SNAPM B) each coupled to a common control element202(comprising, together with the two SNAPM elements204“SNAPM”) and with each of the SNAPM elements204including respective DRAM memory206A and206B in conjunction with associated switches and buses208A and208B respectively as will be more fully described hereinafter. In this embodiment, the controller104is an interleaved memory controller bi-directionally coupled to the DIMM slots114and SNAPM elements204by means of a Channel A216A and a Channel B216B.

With reference additionally now toFIG. 2B, a functional block diagram of another exemplary embodiment of a switch/network adapter port200B incorporating collocated common memory resources in accordance with the present invention is shown. Again, like structure and functionality to that disclosed with respect to the preceding figures is like numbered and the foregoing description thereof shall suffice herefor. The switch/network adapter port200B with common memory is shown in a by-four configuration of interleaved DIMM slot form factor SNAPM elements204coupled to a common SNAPM memory control element202(comprising, together with the four SNAPM elements204“SNAPM”). In this embodiment, the controller104is again an interleaved memory controller bi-directionally coupled to the DIMM slots114and SNAPM elements204by means of a respective Channel A216A, Channel B216B, Channel C216C and Channel D216D.

With reference additionally now toFIG. 3, a functional block diagram of a representative embodiment of a by-two SNAPM system300in accordance with the present invention is shown. The SNAPM system, in the exemplary embodiment shown, comprises a pair of circuit boards204, each of which may be physically and electrically coupled into one of two DIMM (RIMM or other memory module form factor) memory slots, and one of which may contain a SNAPM control block202in the form of, for example, an FPGA programmed to function as the SNAPM memory control block of the precedingFIGS. 2A and 2B.

Each of the SNAPM circuit boards204comprises respective collocated common memory resources206A (“Memory A”) and206B (“Memory B”) which may be conveniently provided in the form of DRAM, SRAM or other suitable memory technology types. Each of the memory resources206A and206B is respectively associated with additional circuitry208A and208B comprising, in pertinent part, respective DIMM connectors302A and302B, a number of address switches304A and304B and a number of data switches306A and306B along with associated address/control and data buses. The address switches304A and304B and data switches306A and306B are controlled by a switch direction control signal provided by the SNAPM control block202on control line308as shown. The address switches304and data switches306may be conveniently provided as FETs, bipolar transistors or other suitable switching devices. The network connections120may be furnished, for example, as a flex connector and corresponds to the cluster interconnect fabric of the preceding figures for coupling to one or more elements of direct execution logic such as MAP® elements available from SRC Computers, Inc.

With reference additionally now toFIG. 4A, a corresponding functional block diagram of the embodiment of the preceding figure is shown wherein the memory and I/O controller (element104ofFIGS. 1,2A and2B) drives the address/control and data buses for access to the shared memory resources206of the SNAPM elements204through the respective address and data switches304AND306in accordance with the state of the switch direction control signal on control line308.

With reference additionally now toFIG. 4B, an accompanying functional block diagram of the embodiment ofFIG. 3is shown wherein the SNAPM memory control block202provides access to the shared memory resources206and disconnects the address/control and data buses from the system memory and I/O controller (element104ofFIGS. 1,2A and2B) in accordance with an opposite state of the switch direction control signal on control line308.

As shown with respect toFIGS. 4A and 4B, the memory and I/O controller (element104ofFIGS. 1,2A and2B), as well as the SNAPM memory controller202, can control the common memory resources206on the SNAPM modules204. The switches304and306are configured such that the data and address lines may be driven by either the memory and I/O controller104or the SNAPM memory controller202while complete DIMM (and RIMM or other memory module format) functionality is maintained. Specifically, this may be implemented in various ways including the inclusion of a number of control registers added to the address space accessible by the memory and I/O controller104which are used to coordinate the use of the shared memory resources206. In the embodiment illustrated, the least significant bit (“LSB”) data lines (07:00) of lines (71:00) and/or selected address bits may be used to control the SNAPM control block202, and hence, the allocation and use of the shared memory resources206.

In operation, when the memory and I/O controller104is in control, the SNAPM memory controller202is barred from accessing the DRAM memory206. Conversely, when the SNAPM memory controller202is in control, the address/control and data buses from the memory and I/O controller104are disconnected from the DRAM memory206. However, the SNAPM memory controller202continues to monitor the address and control bus for time critical commands such as memory refresh commands. Should the memory and I/O controller104issue a refresh command while the SNAPM memory controller202is in control of the DRAM memory206, it will interleave the refresh command into its normal command sequence to the DRAM devices. Additionally, when the memory and I/O controller104is in control, the SNAPM modules204monitor the address and command bus for accesses to any control registers located on the module and can accept or drive replies to these commands without switching control of the collocated memory resources206.