SYNCHRONIZATION SIGNAL GENERATION CIRCUIT AND SYNCHRONIZATION METHOD BETWEEN MULTIPLE DEVICES

A synchronization signal generation circuit and a synchronization method among a plurality of devices are proposed. The synchronization signal generation circuit includes a clock signal generator and a controller. The clock signal generator generates a reference clock signal. The controller receives an input clock signal from a host end device and generates a plurality of candidate clock signals through a plurality of counting operations based on the reference clock signal. The controller selectively transmits one of the candidate clock signals to each peripheral device according to request information corresponding to each peripheral device. The candidate clock signals and the input clock signal have mutually aligned start time points in each frame period.

BACKGROUND

Technical Field

The disclosure relates to a synchronization signal generation circuit and a synchronization method among a plurality of devices, and particularly relates to a synchronization signal generation circuit used in an augmented reality display system and a synchronization method among a plurality of devices.

Description of Related Art

In the conventional technical field, an augmented reality display device includes a display and a plurality of sensing devices. The display and the sensing devices may perform tracking operations for a variety of objects. The display may be used as an output device and the sensing devices may be used as input devices. Since the display and the sensing devices may respectively perform operations based on different frame rates, it is difficult to synchronize the operations among the display and the plurality of sensing devices.

SUMMARY

The disclosure provides a synchronization signal generation circuit and a synchronization method among a plurality of devices, which may synchronize the plurality of devices working at different frame rates with each other.

A synchronization signal generation circuit of the disclosure includes a clock signal generator and a first controller. The clock signal generator generates a reference clock signal. The first controller is coupled among a host end device and a plurality of first peripheral devices, and receives an input clock signal from the host end device. The first controller generates a plurality of candidate clock signals through a plurality of counting operations based on the reference clock signal. The first controller selectively transmits one of the candidate clock signals to each first peripheral device according to the request information corresponding to each first peripheral device. The candidate clock signals and the input clock signal have mutually aligned start time points in each frame period.

A synchronization method among a plurality of devices of the disclosure includes the following steps. A clock signal generator is configured to generate a reference clock signal. A first controller is disposed among a host end device and a plurality of first peripheral devices. The first controller is configured to receive an input clock signal from the host end device, and the first controller is configured to generate a plurality of candidate clock signals through a plurality of counting operations based on the reference clock signal. The first controller is configured to selectively transmit one of the candidate clock signals to each first peripheral device according to request information corresponding to each first peripheral device, where the candidate clock signals and the input clock signal have mutually aligned start time points in each frame period.

Based on the above, in the synchronization signal generation circuit of the disclosure, the first controller performs the plurality of counting operations based on the reference clock signal to generate the plurality of candidate clock signals, and selects one of the candidate clock signals to transmit to each peripheral device so as to be used as a synchronization signal of the peripheral device according to the frame rate requirement of each peripheral device. The controller is configured to make the candidate clock signals and the input clock signal of the host end device have mutually aligned start time points in each frame period, and thereby make the operations among the host end device and the plurality of peripheral devices synchronize with each other.

DESCRIPTION OF THE EMBODIMENTS

Referring toFIG.1,FIG.1is a schematic diagram of a synchronization signal generation circuit according to an embodiment of the disclosure. A synchronization signal generation circuit100includes a controller110and a clock signal generator120. The controller110is coupled to the clock signal generator120. The clock signal generator120is configured to generate a reference clock signal CLK and transmit the reference clock signal CLK to the controller110. In the embodiment, the clock signal generator120is external to the controller110.

On the other hand, the controller110is coupled to a host end device101and coupled to a plurality of peripheral devices130-1to130-3. The controller110receives an input clock signal INCK transmitted by the host end device101, where the input clock signal INCK may be a synchronization signal sent by the host end device101. The controller110may generate a plurality of candidate clock signals through a plurality of counting operations based on the received reference clock signal CLK. Further, the controller110may selectively transmit one of the candidate clock signals to generate an output clock signal OUTCK1according to the request information of the peripheral devices130-1and130-2, and transmit the output clock signal OUTCK1to the peripheral devices130-1and130-2. The controller110may also selectively transmit one of the candidate clock signals to generate an output clock signal OUTCK2according to the request information of the peripheral device130-3, and transmit the output clock signal OUTCK2to the peripheral device130-3.

The request information of the peripheral devices130-1,130-2, and130-3is the frame rate at which the peripheral devices130-1,130-2, and130-3perform work. In the embodiment, the peripheral devices130-1and130-2may have the same working frame rate and receive the same output clock signal OUTCK1. The peripheral devices130-1and130-2receive the output clock signal OUTCK1as the synchronization signal. In contrast, the working frame rate of the peripheral device130-3may be different from the working frame rate of the peripheral device130-1, and the output clock signal OUTCK2may be received as a synchronization signal. The output clock signals OUTCK2and OUTCK1may have different frequencies.

Based on the fact that the output clock signals OUTCK1and OUTCK2are both selected by the controller110from the plurality of candidate clock signals generated internally, the output clock signal OUTCK1may be one of the candidate clock signals, and the output clock signal OUTCK2may be another one of the candidate clock signals. In addition, the request information of the peripheral devices130-1to130-3does not need to be fixed, but may be dynamically adjusted. Taking the peripheral device130-1as an example, when the request information of the peripheral device130-1changes, the controller110may correspondingly select another candidate clock signal (having a different frequency than the output clock signal OUTCK1) other than the output clock signal OUTCK1as the output clock signal, and transmit the output clock signal to the peripheral device130-1as a synchronization signal of the peripheral device130-1.

It is worth mentioning that in order to synchronize the operations of the host end device101and the peripheral devices130-1to130-3with each other, the controller110may make the start time point of each candidate clock signal generated aligned with the start time point of the input clock signal INCK in each frame period.

Incidentally, in the embodiment, the host end device101may be an electronic device with a display. Furthermore, the host end device101may have a processor. The input clock signal INCK provided by the host end device101may be a synchronization signal for the display to perform display operations, such as a vertical synchronization signal. Each of the peripheral devices130-1to130-3may be a sensing element, such as a light sensor array and a light emitter array and/or a microelectromechanical system (MEMS).

Referring toFIG.2below,FIG.2is a schematic diagram of a synchronization signal generation circuit according to another embodiment of the disclosure. A synchronization signal generation circuit200includes a controller210and a clock signal generator220. The controller210is coupled to the clock signal generator220, wherein the clock signal generator220is embedded in the controller210. The clock signal generator220is configured to generate the reference clock signal CLK inside the controller210. In the embodiment, the controller210is coupled to a host end device201and is further coupled to peripheral devices230-1to230-3. Peripheral device230-4may be directly coupled to the host end device201. The controller210is the same as the controller110of the previous embodiment, and may generate and transmit the output clock signal OUTCK1to the peripheral devices230-1and230-2according to the request information of the peripheral devices230-1to230-3, and generate and transmit the output clock signal OUTCK2to the peripheral device230-3, so that the peripheral devices230-1to230-3may be configured to perform synchronization operations according to the received output clock signal OUTCK1or OUTCK2.

Regarding the synchronization operations of the peripheral device230-4, the host end device201may directly send a synchronization signal SYNC to the peripheral device230-4, so that the peripheral device230-4may be configured to perform synchronization operations according to the synchronization signal SYNC. Furthermore, in the embodiment, the peripheral device230-1may also generate a post-synchronization signal PSYNC according to the received output clock signal OUTCK1. The peripheral device230-1may transmit the post-synchronization signal PSYNC to the peripheral device230-4. In this way, the peripheral device230-4may perform synchronization operations according to the post-synchronization signal PSYNC and the synchronization signal SYNC.

For details about the generation of the candidate clock signals and the output clock signals OUTCK1and OUTCK2in the above-mentioned embodiments ofFIG.1andFIG.2, please refer to the following embodiments.

Referring toFIG.3,FIG.3is a schematic diagram of an implementation of a controller in a synchronization signal generation circuit according to an embodiment of the disclosure. A controller300includes a clock generator301. The clock generator301includes an arbiter310, counters321and322, and a selector330. It is worth mentioning that one clock generator301may correspond to at least one peripheral device. When the controller300correspondingly controls a plurality of peripheral devices with different request information, a plurality of clock generators301may be disposed in the controller300.

In the embodiment, the arbiter310is coupled to the counters321and322and the selector330. The arbiter310receives a request information RQI of the corresponding peripheral device, and generates a selection signal SEL according to the request information RQI. The counters321and322receive the reference clock signal CLK generated by the clock generator301, perform counting operations based on the reference clock signal CLK, and thereby generate candidate clock signals dCK1and dCK2respectively. The selector330is coupled to the counters321and322and the arbiter310. The selector330selects one of the candidate clock signals dCK1and dCK2according to the selection signal SEL to generate an output clock signal OUTCKx.

In terms of operation details, the arbiter310is configured to decode the received request information RQI. The request information RQI includes the possible working frame rate of the corresponding peripheral device and the currently required working frame rate. In the embodiment, the arbiter310may decode the possible working frame rate in the request information RQI to generate a first target frequency GF1and a second target frequency GF2. The arbiter310may also decode the currently required working frame rate in the request information RQI to generate the selection signal SEL.

The counters321and322receive the first target frequency GF1and the second target frequency GF2respectively. The counter321performs counting operations based on the reference clock signal CLK according to the first target frequency GF1, and thereby generates the candidate clock signal dCK1with a frequency equal to the first target frequency GF1. It is worth mentioning that the reference clock signal CLK may be a signal with a relatively high frequency, such as millions or tens of millions of Hertz (Hz). The first target frequency GF1may be a relatively low frequency, such as tens of Hertz. The counter321may generate the candidate clock signal dCK1through the counting operations according to the multiple relationship between the frequency of the reference clock signal CLK and the first target frequency GF1. In the embodiment, the counter321may include a frequency dividing circuit.

The counter322performs counting operations based on a reference clock signal INCK according to the second target frequency GF2, and thereby generates the candidate clock signal dCK2with a frequency equal to the second target frequency GF2. The counter322has similar circuit characteristics to the counter321, which will not be described in detail here.

In the embodiment, the arbiter310may be a digital circuit. The counters321and322may be any form of counting circuits that are well known to those skilled in the art, which should not be construed as a limitation in the disclosure. The selector330may be any form of multiplexing circuits that are well known to those skilled in the art, which should neither be construed as a limitation in the disclosure.

Referring toFIG.4below,FIG.4is a waveform diagram of an input clock signal and an output clock signal according to an embodiment of the disclosure. InFIG.4, taking the frame rate of the host end device as 30 Hz as an example, the controller may learn start time points ST1and ST2of next frame periods FP2and FP3by counting the pulse wave number of the input clock signal INCK provided by the host end device in frame periods FP1and FP2respectively.

On the other hand, in the frame period FP1, the controller selects the candidate clock signal dCK1to generate the output clock signal OUTCK1, selects the candidate clock signal dCK2to generate the output clock signal OUTCK2, and taking the frequencies of the candidate clock signals dCK1and dCK2as 30 Hz and 20 Hz respectively, the counters in the controller (the counters321and322inFIG.3) may count the pulse wave number of the candidate clock signals dCK1and dCK2. When the pulse wave number of the candidate clock signal dCK1reaches the first target value, the counter321may enter a reset interval RST1and maintain the output clock signal OUTCK1(equivalent to the candidate clock signal dCK1) at the state of the set logical value (e.g. logical value 0). Similarly, when the pulse wave number of the candidate clock signal dCK2reaches the second target value, the counter322may enter the reset interval RST1and maintain the output clock signal OUTCK2(equivalent to the candidate clock signal dCK2) at the state of the set logical value (e.g., logical value 0).

The above-mentioned first target value and second target value may be determined according to the frequencies of the candidate clock signals dCK1and dCK2and the length of the frame period FP1. Taking the frame period FP1as 1 second as an example, the first target value corresponding to the candidate clock signal dCK1may be 20, and the second target value corresponding to the candidate clock signal dCK2may be 30.

The controller maintains the output clock signals OUTCK1and OUTCK2at the logical value 0 in the reset interval RST1, and synchronously releases the reset state of the output clock signals OUTCK1and OUTCK2at the start time point ST1of the frame period FP2, so that the output clock signals OUTCK1and OUTCK2may be configured to synchronously start the oscillation operation. In this way, the output clock signals OUTCK1and OUTCK2may achieve a synchronized state with the input clock signal INCK.

In the frame period FP2, based on the request information of the peripheral device, the controller switches to select the candidate clock signal dCK2to generate the output clock signal OUTCK1, and selects the candidate clock signal dCK1to generate the output clock signal OUTCK2. Similarly, the counters321and322generate a reset interval RST2by counting the pulse wave number of the candidate clock signals dCK1and dCK2respectively in the frame period FP2, and maintain the output clock signals OUTCK1and OUTCK2at the logical value 0 in the reset interval RST2. Moreover, at the start time point ST2of the frame period FP3, the output clock signals OUTCK1and OUTCK2may synchronously start the oscillation operation.

Referring toFIG.5below.FIG.5is a schematic diagram of a partial circuit of a controller in a synchronization signal generation circuit according to an embodiment of the disclosure. A counter510in the controller may be coupled to a comparator520. The counter510may be any of the counters321and322in the embodiment ofFIG.3. The counter510may count a pulse wave number NP of the generated candidate clock signal, and the comparator520is configured to compare the pulse wave number NP with a corresponding target value TV. When the pulse wave number NP is equal to the corresponding target value TV, the comparator520may generate a reset signal RST to reset the counter510and maintain the candidate clock signal at the set logical value (e.g., logical value 0).

Referring toFIG.6,FIG.6is a schematic diagram of a synchronization signal generation circuit according to another embodiment of the disclosure. A synchronization signal generation circuit600includes controllers610and620. The controllers610and620may receive the reference clock signal CLK generated by the clock signal generator (not shown). The controller610is coupled between a display device601as the host end device and a peripheral device631-1. The controller620is coupled among the display device601, the controller610, and the peripheral devices631-2and631-3.

The controller610may transmit and receive input and output data IO1with the display device601. The controller610may also receive the input clock signal INCK from the display device610. The controller610may be configured to generate the plurality of candidate clock signals through the plurality of counting operations based on the reference clock signal CLK, selectively transmit one of the plurality of candidate clock signals as the output clock signal OUTCK1according to the request information of the corresponding peripheral device631-1, and transmit the output clock signal OUTCK1to the peripheral device631-1.

On the other hand, the controller610may select another one of the plurality of candidate clock signals to be the output clock signal OUTCK2, and transmit the output clock signal OUTCK2to the controller620. The controller620may have a similar circuit architecture as the controller610. The controller620receives the output clock signal OUTCK2as its input clock signal, and performs operations similar to the controller610to generate an output clock signal OUTCK3and an output clock signal OUTCK4, and provide the output clock signal OUTCK3and the output clock signal OUTCK4to the corresponding peripheral devices631-2and431-3respectively.

In the embodiment, the controller620may serve as a relay circuit among the plurality of peripheral devices631-2and631-3and the controller610, and by providing the output clock signal OUTCK3and the output clock signal OUTCK4to the corresponding peripheral devices631-2and631-3, the peripheral devices631-2and631-3may be configured to perform synchronization operations according to the output clock signal OUTCK3and the output clock signal OUTCK4respectively.

In the embodiment, the details of the operations of the controllers610and620have been described in detail in the foregoing embodiments and implementation modes, and will not be described again here.

It is worth mentioning that in the embodiment, the controller620may be directly coupled to the display device601, and may directly transmit and receive input and output data IO2with the display device601.

Referring toFIG.7,FIG.7is a schematic diagram of a synchronization signal generation circuit according to another embodiment of the disclosure. A synchronization signal generation circuit700includes a controller710. In the embodiment, the host end device may be one of a plurality of peripheral devices. The controller710is coupled among peripheral device701and the peripheral devices730-1and730-2. The controller710may receive the synchronization signal provided by the peripheral device701as the input clock signal INCK, and generate the output clock signals OUTCK1and OUTCK2based on the reference clock signal CLK. The controller710also provides the output clock signals OUTCK1and OUTCK2to the peripheral devices730-1and730-2respectively as the synchronization signals. In this way, the synchronization signal generation circuit700may perform synchronization operations among the peripheral devices701,730-1, and730-2.

In the embodiment, the details of the operations of the controller710have been described in detail in the foregoing embodiments and implementation modes, and will not be described again here.

Referring toFIG.8,FIG.8is a flowchart of a synchronization method among a plurality of devices according to an embodiment of the disclosure. In step S810, the clock signal generator is configured to generate the reference clock signal; in step S820, the first controller is disposed among the host end device and the plurality of first peripheral devices; in step S830, the first controller is configured to receive the input clock signal from the host end device, and the first controller is configured to generate the plurality of candidate clock signals through a plurality of counting operations based on the reference clock signal; in step S840, the first controller is configured to selectively transmit one of the candidate clock signals to each first peripheral device according to the request information corresponding to each first peripheral device, where the candidate clock signals and the input clock signal have mutually aligned start time points in each frame period.

The implementation details of the above steps have been described in detail in the foregoing embodiments and implementation modes, and will not be described again here.

In summary, the synchronization signal generation circuit of the disclosure performs the plurality of counting operations through the first controller, and then selectively transmits one of the plurality of candidate clock signals to each first peripheral device according to the request information of the corresponding peripheral device as the synchronization signal for each first peripheral device. The key point is that the controller of the disclosure enables the candidate clock signals and the input clock signal provided by the host end device to have mutually aligned start time points in each frame period. In this way, the synchronization operations among the host end device and the plurality of peripheral devices may be effectively executed, thereby effectively improving the overall efficiency of the system.