Photoelectric conversion apparatus, image capturing system, method for driving photoelectric conversion apparatus, and moving object

In an aspect of the present disclosure, a photoelectric conversion apparatus comprising includes a scan unit and a plurality of pixels each including a photoelectric conversion unit and configured to output a digital signal corresponding to an electric charge generated by the photoelectric conversion unit. The scan unit performs a scan to read the digital signal from the plurality of pixels and an operation of inputting a signal based on the digital signal output from the plurality of pixels to the plurality of pixels.

BACKGROUND

Field

The present disclosure relates to photoelectric conversion apparatuses, image capturing systems, methods for driving a photoelectric conversion apparatus, and moving objects.

Description of the Related Art

There is known a photoelectric conversion apparatus that outputs a pixel signal based on photoelectric conversion as a digital signal from a pixel. It is greatly advantageous to digitalize a pixel signal output from a pixel in terms of noise and signal calculation processing. United States Patent Application Publication No. 2017/0176250 discusses a photoelectric conversion apparatus that digitally counts photons incident on a photodiode. In United States Patent Application Publication No. 2017/0176250, a pixel includes a digital memory, and data for deactivating a defective pixel is written to the digital memory using row and column control lines.

The photoelectric conversion apparatus discussed in United States Patent Application Publication No. 2017/0176250 needs the row and column control lines for writing data to the digital memory of the pixel and the row and column control lines for writing a pixel signal output from the pixel. United States Patent Application Publication No. 2017/0176250 is silent about reduction of the number of wiring lines of the photoelectric conversion apparatus. In United States Patent Application Publication No. 2017/0176250, pixel signals from a plurality of pixels arranged on an array are collectively read. In other words, a case where reading of a digital signal from each pixel on the array is individually controlled is not considered in United States Patent Application Publication No. 2017/0176250.

SUMMARY

The present disclosure is directed to a photoelectric conversion apparatus that realizes both control of each of digital signal writing to and digital signal reading from a pixel and reduction of at least one of a circuit area and a wiring line area.

According to an aspect of the present disclosure, a photoelectric conversion apparatus includes a scan unit and a plurality of pixels each including a photoelectric conversion unit and configured to output a digital signal corresponding to an electric charge generated by the photoelectric conversion unit. The scan unit performs a scan to read the digital signal from the plurality of pixels and an operation of inputting a signal based on the digital signal output from the plurality of pixels to the plurality of pixels.

According to another aspect of the present disclosure, a photoelectric conversion apparatus includes a first signal input/output unit and a plurality of pixels each including a photoelectric conversion unit and a storage unit and configured to output a digital signal corresponding to an electric charge generated by the photoelectric conversion unit, and the photoelectric conversion apparatus further includes a transmission line including an electric path for transmitting the digital signal from the plurality of pixels to the first signal input/output unit and configured to transmit a predetermined digital signal from the first signal input/output unit to the plurality of pixels using the electric path.

According to another aspect of the present disclosure, a method is provided for driving a photoelectric conversion apparatus including a scan unit and a plurality of pixels each including a photoelectric conversion unit and configured to output a digital signal corresponding to an electric charge generated by the photoelectric conversion unit. The scan unit performs a scan to read the digital signal from the plurality of pixels and a scan to store a predetermined digital signal in the plurality of pixels.

DESCRIPTION OF THE EMBODIMENTS

A first exemplary embodiment of the present disclosure will be described below. A photoelectric conversion apparatus according to the present exemplary embodiment will be described below with reference toFIGS. 1 and 2.FIG. 1is a schematic configuration diagram illustrating the photoelectric conversion apparatus according to the present exemplary embodiment.FIG. 2is a timing chart illustrating the driving of the photoelectric conversion apparatus according to the present exemplary embodiment.

As illustrated inFIG. 1, a photoelectric conversion apparatus1according to the present exemplary embodiment includes a pixel array unit2, a vertical scan unit3, a signal transmission/reception unit4, a horizontal scan unit5, a memory unit6, and a signal output unit7. The pixel array unit2includes a plurality of pixels2ato2darranged two-dimensionally.FIG. 1illustrates a case where the pixel array unit2includes the pixels2ato2darranged in two rows and two columns. The numbers of rows and columns of the pixel array unit2are not particularly limited.

A transmission line PMW1is commonly connected to the plurality of pixels2aand2cof the same column of the pixel array unit2, and a transmission line PMW2is commonly connected to the plurality of pixels2band2dof the same column of the pixel array unit2. Similarly, a transmission line PDAT1is commonly connected with the plurality of pixels2aand2cof the same column of the pixel array unit2, and a transmission line PDAT2is commonly connected with the plurality of pixels2band2dof the same column of the pixel array unit2. The transmission lines PMW1and PMW2are illustrated as n bus wiring lines inFIG. 1. Similarly, the transmission lines PDAT1and PDAT2are illustrated as n bus wiring lines inFIG. 1.

The signal transmission/reception unit4includes input/output units41aand41b. The input/output unit41ais connected to the transmission lines PMW1and PDAT1. The input/output unit41atransmits a predetermined signal to the pixels2aand2cvia the transmission line PMW1and receives a pixel signal output from each of the pixels2aand2cvia the transmission line PDAT1. As used herein, the term “predetermined signal” refers to a predetermined digital signal. The predetermined digital signal is, for example, a signal for deactivating a defective pixel and activating a non-defective pixel in a case where the plurality of pixels includes the non-defective pixel and the defective pixel. As used herein, the term “pixel signal” refers to a digital signal based on light incident on a photoelectric conversion unit of each of the pixels2ato2d. Specifically, the pixel signal is a digital signal corresponding to an electric charge generated by the photoelectric conversion unit of each of the pixels2ato2d. The photoelectric conversion unit is, for example, a photodiode in a semiconductor substrate. Similarly, the input/output unit41bis connected to the transmission lines PMW2and PDAT2. The input/output unit41btransmits a predetermined signal to the pixels2band2dvia the transmission line PMW2and receives a pixel signal output from each of the pixels2band2dvia the transmission line PDAT2.

The input/output units41aand41bare further connected to transmission lines IPMW and IDAT. The memory unit6sequentially transmits a predetermined signal to the input/output units41aand41bvia the transmission line IPMW. The signal output unit7receives a pixel signal output sequentially from the input/output units41aand41band outputs the pixel signal as an output signal SDAT of the photoelectric conversion apparatus1. The transmission line IDAT and the output signal SDAT are respectively illustrated as n bus wiring lines and n-bit digital signal inFIG. 1.

Column selection control lines HSEL1and HSEL2control reception and transmission of the input/output units41aand41b. The horizontal scan unit5feeds a control signal to the column selection control lines HSEL1and HSEL2. With this configuration, the input/output units41aand41bsequentially receive a predetermined signal output from the memory unit6and transmit the received predetermined signal to the pixels2ato2dand receive a pixel signal from the pixels2ato2dand sequentially transmit the received pixel signal to the signal output unit7.

In the present exemplary embodiment, predetermined signal writing to and pixel signal reading from the input/output units41aand41bare performed. More specifically, the input/output units41aand41bare used to write both a predetermined signal and a read pixel signal. For example, a digital memory of each of the input/output units41aand41bstores both a predetermined signal and a pixel signal. Here, if the reading of the predetermined signal and the writing of the pixel signal are performed by different input/output units, for example, a first digital memory for storing a pixel signal and a second digital memory for storing a predetermined signal are presumably needed. This requires a certain circuit area to arrange two digital memories for each input/output unit. By contrast, in the present exemplary embodiment, the digital memories of the input/output units41aand41bfor storing the read pixel signal are also used for writing of the predetermined signal. This reduces the circuit area of the signal transmission/reception unit4.

The pixels2ato2deach include an input/output unit23and pixel circuit units21and22. The input/output units23of the pixels2aand2care each connected to the transmission lines PMW1and PDAT1. The input/output units23of the pixels2aand2ceach receive a predetermined signal output from the input/output unit41avia the transmission line PMW1and transmit a pixel signal to the input/output unit41avia the transmission line PDAT1. Similarly, the input/output units23of the pixels2band2dare each connected to the transmission lines PMW2and PDAT2and receive a predetermined signal from the input/output unit41bvia the transmission line PMW2and transmit a pixel signal to the input/output unit41bvia the transmission line PDAT2. Furthermore, the input/output units23of the pixels2aand2bare each connected to control lines LSEL1and VSEL1, and the input/output units23of the pixels2cand2dare each connected to control lines LSEL2and VSEL2. Each output unit23controls signal transmission and reception based on a control signal fed from the vertical scan unit3via the control lines LSEL1, LSEL2, VSEL1, and VSEL2. The pixel circuit unit21outputs a pixel signal to the input/output unit23. The pixel circuit unit21is, for example, an analog to digital conversion circuit configured to convert a signal that is photoelectrically converted by the photoelectric conversion unit into a digital signal. Alternatively, the pixel circuit unit21can be a counter circuit configured to count incident photons detected by the photoelectric conversion unit and output a result thereof. In the latter case, for example, an avalanche diode is used as a photoelectric conversion unit. The respective pixel circuit units22are configured to control an operation of the corresponding pixel based on a predetermined signal from the input/output units23. The pixel circuit unit22is, for example, a storage unit that stores a predetermined signal and a control circuit that activates or deactivates an operation of the pixel circuit unit21. For example, in a case where an avalanche diode is used as a photoelectric conversion unit, the pixel circuit unit21generally includes the avalanche diode, a waveform shaping circuit, and a counter. The waveform shaping circuit shapes a waveform output from the avalanche diode into a pulse wave. The counter counts pulses output from the waveform shaping circuit. The “predetermined digital signal” is a signal for performing at least one of control for stopping avalanche multiplication, control for stopping the waveform shaping circuit, control for stopping the counter, and control for stopping digital signal output from the counter to the transmission line PDAT1.

Operations of the photoelectric conversion apparatus1inFIG. 1will be described below with reference to a timing chart inFIG. 2.

FIG. 2illustrates timings of signals fed to the control lines LSEL1, LSEL2, VSEL1, and VSEL2by the vertical scan unit3.FIG. 2further illustrates timings of signals fed to the column selection control lines HSEL1and HSEL2by the horizontal scan unit5, the transmission line IPMW, the output signal SDAT, and a vertical scan synchronization signal VD. If the vertical scan synchronization signal VD is turned on, a vertical scan is started from a row of pixels to be read first. Then, the next time the vertical scan synchronization signal VD is turned on, a vertical scan is started from the row of the pixels to be read first again. InFIG. 2, the vertical scan synchronization signal VD is set at a high-level throughout a period during which the vertical scan unit3scans the pixels of each row. Alternatively, the vertical scan synchronization signal VD can be changed to a low-level after being maintained at the high-level during a period corresponding to a predetermined period of a clock pulse from the time of the change of the vertical scan synchronization signal VD to the high-level. Even in such a case, the vertical scan synchronization signal VD is used as a trigger signal for starting a scan by the vertical scan unit3.

InFIG. 2, at time t1, data M11is transmitted from the memory unit6to the transmission line IPMW and the column selection control line HSEL1is changed to the high-level, and then the input/output unit41astores the data M11. Here, the term “data” is used as a word expressing a predetermined digital signal that is written to the pixels2ato2d. Similarly, at time t2, data M12is transmitted from the memory unit6to the transmission line IPMW and the column selection control line HSEL2is changed to the high-level, and then the input/output unit41bstores the data M12. At time t3, the control line VSEL1is changed to the high-level, and the input/output unit23of the pixel2areceives the data M11via the transmission line PMW1and outputs the data M11to the pixel circuit unit22. At the same time, similarly, the input/output unit23of the pixel2breceives the data M12via the transmission line PMW2and outputs the data M12to the pixel circuit unit22. At this time, the control line LSEL1is set at the high-level. Next, at time t4, data M21is transmitted from the memory unit6to the transmission line IPMW and the column selection control line HSEL1is changed to the high-level, and then the input/output unit41astores the data M21. Similarly, at time t5, data M22is transmitted from the memory unit6to the transmission line IPMW and the column selection control line HSEL2is changed to the high-level, and then the input/output unit41bstores the data M22. At time t6, the control line VSEL2is changed to the high-level, and the input/output unit23of the pixel2creceives the data M21via the transmission line PMW1and outputs the data M21to the pixel circuit unit22. At the same time, similarly, the input/output unit23of the pixel2dreceives the data M22via the transmission line PMW2and outputs the data M22to the pixel circuit unit22. At this time, the control line LSEL2is at the high-level.

At this time, the pixels2a,2b,2c, and2dhave respectively received the data M11, M12, M21, and M22as predetermined signals. Thus, the pixels2a,2b,2c, and2dare individually controlled by the respective predetermined signals received by the pixel circuit units22.

At time t7, the control lines LSEL1and LSEL2are changed to the low-level, and at time t8, the vertical scan synchronization signal VD is changed to the high-level, and then the operation of the photoelectric conversion apparatus1proceeds to an operation of outputting a pixel signal based on photoelectric conversion. At time t8, the control line VSEL1is changed to the high-level, and the input/output units23of the pixels2aand2beach output a pixel signal to the transmission lines PDAT1and PDAT2. At the same time, the signal transmission/reception unit4stores the pixel signals output from the pixels2aand2bin the input/output units41aand41b, respectively. At time t9, the column selection control line HSEL1is changed to the high-level, and the signal transmission/reception unit4outputs a signal based on the pixel signal from the pixel2a, from the input/output unit41ato the transmission line IDAT. At this time, the signal based on the pixel signal from the pixel2ais output as an output signal S11of the photoelectric conversion apparatus1from the signal output unit7. At time t10, the column selection control line HSEL2is changed to the high-level, and the signal transmission/reception unit4outputs a signal based on the pixel signal from the pixel2b, from the input/output unit41bto the transmission line IDAT. At this time, the signal based on the pixel signal from the pixel2bis output as an output signal S12of the photoelectric conversion apparatus1from the signal output unit7. Next, at time t11, the control line VSEL2is changed to the high-level, and, similarly, the pixel signals from the pixels2cand2dare respectively stored in the input/output units41aand41bof the signal transmission/reception unit4. Furthermore, at time t12, the column selection control line HSEL1is changed to the high-level and, similarly, a signal based on the pixel signal from the pixel2cis output as an output signal S21of the photoelectric conversion apparatus1from the signal output unit7. At time t13, the column selection control line HSEL2is changed to the high-level and, similarly, a signal based on the pixel signal from the pixel2dis output as an output signal S22of the photoelectric conversion apparatus1from the signal output unit7. Thereafter, the vertical scan synchronization signal VD is changed to the low-level. At time t14, the vertical scan synchronization signal VD is changed to the high-level again, and the photoelectric conversion apparatus1repeats an operation of outputting a pixel signal based on photoelectric conversion.

InFIG. 1, the plurality of pixels2ato2dis arranged in a matrix form, and the vertical scan unit3and the horizontal scan unit5control signal writing and reading to and from the pixels2ato2d. The present exemplary embodiment is not limited to the above-described configuration and also encompasses a configuration where a plurality of pixels is arranged in a row or column direction and one of a horizontal scan unit and a vertical scan unit controls writing to and reading from the pixels. In such a case, the horizontal scan unit or the vertical scan unit corresponds to a scan unit.

While predetermined signal writing to and pixel signal reading from each pixel are controlled in the present exemplary embodiment, predetermined signal writing to and pixel signal reading from two or more pixels can be controlled collectively. More specifically, writing to and reading from a first pixel group including two or more pixels of a pixel array are controlled, and writing to and reading from a second pixel group including other two or more pixels of the pixel array are controlled.

As described above, the photoelectric conversion apparatus1according to the present exemplary embodiment controls digital signal writing to and digital signal reading from the pixels2ato2dusing the vertical scan unit3and the horizontal scan unit5. United States Patent Application Publication No. 2017/0176250 discusses signal writing to a pixel but is silent about a case where a pixel signal is individually read. To read a pixel signal individually in United States Patent Application Publication No. 2017/0176250, a vertical scan circuit and a horizontal scan circuit for writing and another vertical scan circuit and another horizontal scan circuit for reading are needed. Thus, a circuit area is needed to arrange a vertical scan circuit and a horizontal scan circuit for writing and another vertical scan circuit and another horizontal scan circuit for reading. By contrast, in the present exemplary embodiment, the vertical scan unit3and the horizontal scan unit5control writing and reading. In other words, the vertical scan unit3and the horizontal scan unit5are commonly used for predetermined signal transmission and control of pixel signal transmission. This reduces the circuit area compared with a configuration that includes a vertical scan circuit and a horizontal scan circuit for writing and another vertical scan circuit and another horizontal scan circuit for reading. The input/output units41aand41btransmit a predetermined signal to the input/output units23of the pixels2ato2d, so that digital signal writing to the pixels2ato2dand pixel signal reading from the pixels2ato2dare both controlled.

Other examples of digital signals to be written to the pixels2ato2dinclude an analog to digital (AD) conversion gain setting, an amplification rate setting in a case where an analog signal amplification unit based on incident light is provided, and a control signal for reducing the consumption of electric currents in the pixels2ato2dof a non-scan row. As described above, various signals are applicable to digital signals to be written to the pixels2ato2dthat are described in the present exemplary embodiment.

With the photoelectric conversion apparatus1according to the present exemplary embodiment, control of digital signal writing to the pixels2ato2dand pixel signal reading from the pixels2ato2dand circuit area reduction are realized as described above.

A second exemplary embodiment of the present disclosure will be described below. A photoelectric conversion apparatus according to the present exemplary embodiment will be described below with reference toFIGS. 3 and 4.FIG. 3is a schematic configuration diagram illustrating the photoelectric conversion apparatus according to the present exemplary embodiment.FIG. 4is a timing chart illustrating the driving of the photoelectric conversion apparatus according to the present exemplary embodiment.

The photoelectric conversion apparatus according to the present exemplary embodiment is different from the first exemplary embodiment in that, in the present exemplary embodiment, the transmission lines PMW1and PMW2and the transmission lines PDAT1and PDAT2connect to different circuits, input/output units41cand41dand input/output units81aand81b, respectively. In the present exemplary embodiment, while the inclusion of a signal output unit8including the input/output units81aand81bincreases the circuit area compared to the first exemplary embodiment, the advantage of circuit area reduction by the shared use of the vertical scan unit3and the horizontal scan unit5is still produced. Moreover, signal reading is performed faster than the first exemplary embodiment. Each component similar to that of the photoelectric conversion apparatus1according to the first exemplary embodiment is given the same reference numeral, and descriptions thereof are omitted or simplified.

As illustrated inFIG. 3, the photoelectric conversion apparatus1according to the present exemplary embodiment includes the pixel array unit2, the vertical scan unit3, the signal transmission/reception unit4, the horizontal scan unit5, the memory unit6, and the signal output unit8. The pixel array unit2includes the plurality of pixels2ato2d.

The transmission line PMW1is commonly connected to the pixels2aand2cof the same column of the pixel array unit2, and the transmission line PMW2is commonly connected to the pixels2band2dof the same column of the pixel array unit2. The transmission line PDAT1is commonly connected to the pixels2aand2bof the same row of the pixel array unit2, and the transmission line PDAT2is commonly connected to the pixels2cand2dof the same row of the pixel array unit2. The signal transmission/reception unit4includes the input/output units41cand41d. The input/output unit41cis connected to the transmission line PMW1and transmits a predetermined signal to the pixels2aand2cvia the transmission line PMW1. Similarly, the input/output unit41dis connected to the transmission line PMW2and transmits a predetermined signal to the pixels2band2dvia the transmission line PMW2. The input/output units41cand41dare further connected to the transmission line IPMW. The memory unit6sequentially transmits a predetermined signal to the input/output units41cand41dvia the transmission line IPMW.

The signal output unit8includes the input/output units81aand81b. The input/output unit81ais connected to the transmission line PDAT1and receives a pixel signal from each of the pixels2aand2bvia the transmission line PDAT1. Similarly, the input/output unit81bis connected to the transmission line PDAT2and receives a pixel signal from each of the pixels2cand2dvia the transmission line PDAT2. The input/output units81aand81bare connected to a transmission line SDAT. The signal output unit8sequentially outputs a pixel signal received by each of the input/output units81aand81bas the output signal SDAT of the photoelectric conversion apparatus1.

The pixels2ato2deach include an input/output unit24and the pixel circuit units21and22. The horizontal scan unit5feeds a control signal to the column selection control lines HSEL1and HSEL2to enable predetermined signal transmission/reception and pixel signal transmission. The signal output unit8synchronizes with the horizontal scan unit5using a control line HSEL0.

With this configuration, the input/output units41cand41dsequentially receive a predetermined signal output from the memory unit6and transmit the predetermined signal to each of the pixels2ato2d. The input/output units81aand81breceive a pixel signal from the pixels2ato2dand sequentially output the pixel signal as the output signal SDAT of the photoelectric conversion apparatus1by an action of the signal output unit8.

Operations of the photoelectric conversion apparatus1inFIG. 3will be described below with reference to a timing chart inFIG. 4.

FIG. 4illustrates signals fed to the control lines LSEL1, LSEL2, VSEL1, and VSEL2by the vertical scan unit3and signals fed to the column selection control lines HSEL1and HSEL2by the horizontal scan unit5, the transmission line IPMW, the output signal SDAT, and the vertical scan synchronization signal VD.

InFIG. 4, at time t1, the data M11is transmitted from the memory unit6to the transmission line IPMW and the control line VSEL1and the column selection control line HSEL1are changed to the high-level, and then the input/output unit41cstores the data M11. At the same time, the input/output unit24of the pixel2areceives the data M11via the transmission line PMW1and outputs the data M11to the pixel circuit unit22. At time t2, the data M12is transmitted from the memory unit6to the transmission line IPMW and the column selection control line HSEL2is changed to the high-level, and then the input/output unit41dstores the data M12. At the same time, the input/output unit24of the pixel2breceives the data M12via the transmission line PMW2and outputs the data M12to the pixel circuit unit22. At this time, the control line LSEL1is at the high-level. After the control line VSEL1is changed to the low-level, at time t3, the data M21is transmitted from the memory unit6to the transmission line IPMW and the control line VSEL2and the column selection control line HSEL1are changed to the high-level, and then the input/output unit41cstores the data M21. At the same time, the input/output unit24of the pixel2creceives the data M21via the transmission line PMW1and outputs the data M21to the pixel circuit unit22. At time t4, the data M22is transmitted from the memory unit6to the transmission line IPMW and the column selection control line HSEL2is changed to the high-level, and then the input/output unit41dstores the data M22. At the same time, the input/output unit24of the pixel2dreceives the data M22via the transmission line PMW2and outputs the data M22to the pixel circuit unit22. At this time, the control line LSEL2is at the high-level.

At this time point, the pixels2a,2b,2cand2dhave respectively received the data M11, M12, M21and M22as predetermined signals. Thus, the pixels2a,2b,2cand2dare each controlled based on the predetermined signals received by the pixel circuit units22. At time t5, the control lines LSEL1and LSEL2are changed to the low-level, and at time t6, the vertical scan synchronization signal VD is changed to the high-level, and then the photoelectric conversion apparatus1changes to an operation of outputting a pixel signal based on photoelectric conversion. At time t6, the control line VSEL1and the column selection control line HSEL1are changed to the high-level, and then the input/output unit24of the pixel2aoutputs a pixel signal to the input/output unit81a. At this time, a signal based on the pixel signal from the pixel2ais output as the output signal S11of the photoelectric conversion apparatus1from the signal output unit8. At time t7, the column selection control line HSEL2is changed to the high-level, and then the input/output unit24of the pixel2boutputs a pixel signal to the input/output unit81a. At this time, a signal based on the pixel signal from the pixel2bis output as the output signal S12of the photoelectric conversion apparatus1from the signal output unit8. Next, after the control line VSEL1is changed to the low-level, at time t8, the control line VSEL2and the column selection control line HSEL1are changed to the high-level, and then the input/output unit24of the pixel2coutputs a pixel signal to the input/output unit81b. At this time, a signal based on the pixel signal from the pixel2cis output as the output signal S21of the photoelectric conversion apparatus1from the signal output unit8. At time t9, the column selection control line HSEL2is changed to the high-level, and then the input/output unit24of the pixel2doutputs a pixel signal to the input/output unit81b. At this time, a signal based on the pixel signal from the pixel2dis output as the output signal S22of the photoelectric conversion apparatus1from the signal output unit8. Thereafter, the vertical scan synchronization signal VD is changed to the low-level, and at time t11, the vertical scan synchronization signal VD is changed to the high-level again, and then the photoelectric conversion apparatus1repeats an operation of outputting a pixel signal based on photoelectric conversion.

As described above, the input/output units41cand41dtransmit a predetermined signal to the input/output units24of the pixels2ato2din the photoelectric conversion apparatus1according to the present exemplary embodiment so that predetermined signal writing to each pixel and pixel signal reading from each pixel are both controlled. At this time, the horizontal scan unit5and the vertical scan unit3control selection of signal transmission to each of the pixels2ato2d. In other words, the vertical scan unit3and the horizontal scan unit5are commonly used to control both predetermined signal transmission and pixel signal transmission. With the above-described configuration, the photoelectric conversion apparatus1according to the present exemplary embodiment realizes both control of predetermined signal writing to and pixel signal reading from the pixels2ato2dand circuit area reduction. Furthermore, the transmission line PDAT1is commonly connected to the plurality of pixels2aand2bof the same row of the pixel array unit2, and the transmission line PDAT2is commonly connected to the plurality of pixels2cand2dof the same row of the pixel array unit2, and the signal output unit8includes the input/output units81aand81b. Thus, the photoelectric conversion apparatus1according to the present exemplary embodiment realizes faster pixel signal reading than the photoelectric conversion apparatus1according to the first exemplary embodiment.

A third exemplary embodiment of the present disclosure will be described below. A photoelectric conversion apparatus according to the present exemplary embodiment will be described below with reference toFIGS. 5 and 6.FIG. 5is a schematic configuration diagram illustrating the photoelectric conversion apparatus according to the present exemplary embodiment.FIG. 6is a timing chart illustrating the driving of the photoelectric conversion apparatus according to the present exemplary embodiment.

The photoelectric conversion apparatus1according to the present exemplary embodiment is different from the first exemplary embodiment in that, in the present exemplary embodiment, the transmission lines PDAT1and PDAT2are used as a transmission unit from the pixels2ato2dto input/output units41eand41fand also as a transmission unit from the input/output units41eand41fto the pixels2ato2d. In other words, unlike the first exemplary embodiment, the transmission lines PDAT1and PDAT2are bi-directional signal lines in the present exemplary embodiment. Moreover, unlike the first exemplary embodiment, the transmission line IDAT is used for both predetermined signal transmission from the memory unit6and pixel signal transmission from the pixels2ato2din the photoelectric conversion apparatus1according to the present exemplary embodiment. Each component similar to that of the photoelectric conversion apparatus1according to the first exemplary embodiment is given the same reference numeral, and descriptions thereof are omitted or simplified.

As illustrated inFIG. 5, the photoelectric conversion apparatus1according to the present exemplary embodiment includes the pixel array unit2, the vertical scan unit3, the signal transmission/reception unit4, the horizontal scan unit5, the memory unit6, and a signal output unit9. The pixel array unit2includes the plurality of pixels2ato2d.

The input/output unit41eis connected to the transmission line PDAT1. The input/output unit41etransmits a predetermined signal to the pixels2aand2cand receives a pixel signal from the pixels2aand2cvia the transmission line PDAT1. Similarly, the input/output unit41fis connected to the transmission line PDAT2. The input/output unit41ftransmits a predetermined signal to the pixels2band2dand receives a pixel signal from the pixels2band2dvia the transmission line PDAT2. The input/output units41eand41fare further connected to the transmission line IDAT. The memory unit6sequentially transmits a predetermined signal to the input/output units41eand41fvia the transmission line IDAT.

The transmission line IDAT is used for both predetermined signal transmission from the memory unit6and signal transmission from the pixels2ato2d. In other words, a signal from the pixels2ato2dis transmitted using an electric path for predetermined signal transmission. This reduces the number of transmission lines compared to the first exemplary embodiment, so that the area of the photoelectric conversion apparatus1is further reduced.

The signal output unit9receives a pixel signal sequentially output from the input/output units41eand41fand outputs the pixel signal as the output signal SDAT of the photoelectric conversion apparatus1.

The pixels2ato2deach include an input/output unit26and the pixel circuit units21and25. The input/output units26of the pixels2aand2care connected to the transmission line PDAT1. Predetermined signal reception from the input/output unit41eand pixel signal transmission to the input/output unit41eare performed via the transmission line PDAT1. Similarly, the input/output units26of the pixels2band2dare connected to the transmission line PDAT2. Predetermined signal reception from the input/output unit41fand pixel signal transmission to the input/output unit41fare performed via the transmission line PDAT2.

Operations of the photoelectric conversion apparatus1inFIG. 5will be described below with reference to a timing chart inFIG. 6.

FIG. 6illustrates data about signals fed to the control lines LSEL1, LSEL2, VSEL1, and VSEL2by the vertical scan unit3.FIG. 6further illustrates data about signals fed to the column selection control lines HSEL1and HSEL2by the horizontal scan unit5, the transmission lines PDAT1, PDAT2, and IDAT, the output signal SDAT, and the vertical scan synchronization signal VD.

InFIG. 6, at time t1, the data M11is transmitted from the memory unit6to the transmission line IDAT and the column selection control line HSEL1is changed to the high-level, and then the input/output unit41estores the data M11. At the same time, the input/output unit41etransmits the data M11to the transmission line PDAT1. Similarly, at time t2, the data M12is transmitted from the memory unit6to the transmission line IDAT and the column selection control line HSEL2is changed to the high-level, and then the input/output unit41fstores the data M12. At the same time, the input/output unit41ftransmits the data M12to the transmission line PDAT2. At time t3, the control line VSEL1is changed to the high-level, and then the input/output unit26of the pixel2areceives the data M11via the transmission line PDAT1and outputs the data M11to the pixel circuit unit25. At the same time, similarly, the input/output unit26of the pixel2breceives the data M12via the transmission line PDAT2and outputs the data M12to the pixel circuit unit25. At this time, the control line LSEL1is at the high-level. Next, at time t4, the data M21is transmitted from the memory unit6to the transmission line IDAT and the column selection control line HSEL1is changed to the high-level, and then the input/output unit41estores the data M21. At the same time, the input/output unit41etransmits the data M21to the transmission line PDAT1. Similarly, at time t5, the data M22is transmitted from the memory unit6to the transmission line IDAT and the column selection control line HSEL2is changed to the high-level, and then the input/output unit41bstores the data M22. At the same time, the input/output unit41ftransmits the data M22to the transmission line PDAT2. At time t6, the control line VSEL2is changed to the high-level, and then the input/output unit26of the pixel2creceives the data M21via the transmission line PDAT1and outputs the data M21to the pixel circuit unit25. At the same time, similarly, the input/output unit26of the pixel2dreceives the data M22via the transmission line PDAT2and outputs the data M22to the pixel circuit unit25. At this time, the control line LSEL2is at the high-level.

At this time point, the pixels2a,2b,2cand2dhave respectively received the data M11, M12, M21and M22as predetermined signals. Thus, the pixels2a,2b,2cand2dare respectively controlled based on the predetermined signals received by the pixel circuit units25.

At time t7, the control lines LSEL1and LSEL2are changed to the low-level, and at time t8, the vertical scan synchronization signal VD is changed to the high-level, and then the photoelectric conversion apparatus1changes to an operation of outputting a pixel signal based on photoelectric conversion. At time t8, the control line VSEL1is changed to the high-level, and then the input/output units26of the pixels2aand2brespectively output pixel signals P11and P12to the transmission lines PDAT1and PDAT2. At the same time, the signal transmission/reception unit4stores the pixel signal P11output from the pixel2ain the input/output unit41eand stores the pixel signal P12output from the pixel2bin the input/output unit41f. At time t9, the column selection control line HSEL1is changed to the high-level, and then the signal transmission/reception unit4outputs a signal based on the pixel signal P11from the pixel2afrom the input/output unit41eto the transmission line IDAT. At this time, the signal based on the pixel signal P11from the pixel2ais output as the output signal S11of the photoelectric conversion apparatus1from the signal output unit9. At time t10, the column selection control line HSEL2is changed to the high-level, and then the signal transmission/reception unit4outputs a signal based on the pixel signal P12from the pixel2bfrom the input/output unit41fto the transmission line IDAT. At this time, the signal based on the pixel signal P12from the pixel2bis output as the output signal S12of the photoelectric conversion apparatus1from the signal output unit9. Next, at time t11, the control line VSEL2is changed to the high-level, and then, similarly, pixel signals P21and P22from the pixels2cand2dare respectively stored in the input/output units41eand41fof the signal transmission/reception unit4. At time t12, the column selection control line HSEL1is changed to the high-level, and then, similarly, a signal based on the pixel signal P21from the pixel2cis output as the output signal S21of the photoelectric conversion apparatus1from the signal output unit9. At time t13, the column selection control line HSEL2is changed to the high-level, and then, similarly, a signal based on the pixel signal P22from the pixel2dis output as the output signal S22of the photoelectric conversion apparatus1from the signal output unit9. Thereafter, the vertical scan synchronization signal VD is changed to the low-level, and at time t14, the vertical scan synchronization signal VD is changed to the high-level again, and then the photoelectric conversion apparatus1repeats an operation of outputting a pixel signal based on photoelectric conversion.

As described above, the input/output units41eand41ftransmit a predetermined signal to each of the input/output units26of the pixels2ato2din the photoelectric conversion apparatus1according to the present exemplary embodiment, so that predetermined digital signal writing to the pixels2ato2dand pixel signal reading from the pixels2ato2dare both controlled. At this time, the horizontal scan unit5and the vertical scan unit3control selection of signal transmission to the pixels2ato2d. The input/output units26of the pixels2ato2deach transmit a pixel signal to the input/output units41eand41f, so that the photoelectric conversion apparatus1outputs a pixel signal based on photoelectric conversion. At this time, the vertical scan unit3and the horizontal scan unit5control selection of signal transmission to the pixels2ato2d. Thus, the vertical scan unit3and the horizontal scan unit5are commonly used to control both predetermined signal transmission and pixel signal transmission. With the above-described configurations, the photoelectric conversion apparatus1according to the present exemplary embodiment realizes both control of predetermined signal writing to and pixel signal reading from the pixels2ato2dand circuit area reduction. Furthermore, the photoelectric conversion apparatus1according to the present exemplary embodiment uses a common transmission line for setting signal transmission and pixel signal transmission so that the number of wiring lines is reduced and the area of the photoelectric conversion apparatus1is further reduced compared with the photoelectric conversion apparatus1according to the first exemplary embodiment.

InFIG. 5, the transmission lines PDAT1, PDAT2, and IDAT are illustrated as n bus wiring lines. This is based on a case where a pixel signal from the pixels2ato2dis n-bit data, and a predetermined setting signal output from the memory unit6does not necessarily have to be n-bit data. For example, a predetermined signal can be m-bit data, where m is less than n. In such a case, the memory unit6may transmit a predetermined signal to the pixels2ato2dvia the transmission line IDAT and part of the transmission lines PDAT1and PDAT2. Employing several-bit data as a predetermined signal improves the function of controlling each pixel. For example, an exposure time is controlled for each pixel.

Control of each pixel by the vertical scan unit3and the horizontal scan unit5is not essential. For example, in writing a predetermined signal, signal transmission to the input/output units23of the pixels2ato2dcan be performed while the vertical scan unit3or the horizontal scan unit5is performing signal control. Even in such a case, since the common transmission line is used for predetermined signal transmission to the pixels2ato2dand signal transmission from the pixels2ato2d, the area of the photoelectric conversion apparatus1is still reduced.

The plurality of pixels2ato2dis arranged in a matrix form and the transmission lines PDAT1and PDAT2are arranged with respect to the respective columns inFIG. 5, but this is not restrictive. In another configuration according to the present exemplary embodiment, for example, a plurality of pixels is arranged in a row or column direction and a transmission line is connected to the plurality of pixels.

A fourth exemplary embodiment of the present disclosure will be described below. A photoelectric conversion apparatus according to the present exemplary embodiment will be described below with reference toFIGS. 7 and 8.FIG. 7is a schematic configuration diagram illustrating the photoelectric conversion apparatus according to the present exemplary embodiment.FIG. 8is a timing chart illustrating the driving of the photoelectric conversion apparatus according to the present exemplary embodiment.

The photoelectric conversion apparatus according to the present exemplary embodiment is different from the third exemplary embodiment in that, in the present exemplary embodiment, the transmission line PDAT1is commonly connected to the plurality of pixels2aand2bof the same row and the transmission line PDAT2is commonly connected to the plurality of pixels2cand2dof the same row. Another difference from the third exemplary embodiment is that a signal transmission/reception unit10includes input/output units12aand12band outputs a signal in the present exemplary embodiment. Each component similar to that of the photoelectric conversion apparatus1according to the third exemplary embodiment is given the same reference numeral, and descriptions thereof are omitted or simplified.

As illustrated inFIG. 7, the photoelectric conversion apparatus1according to the present exemplary embodiment includes the pixel array unit2, the vertical scan unit3, the horizontal scan unit5, and the signal transmission/reception unit10. The pixel array unit2includes the plurality of pixels2ato2d.

The transmission line PDAT1is commonly connected to the plurality of pixels2aand2bof the same row of the pixel array unit2, and the transmission line PDAT2is commonly connected to the plurality of pixels2cand2dof the same row of the pixel array unit2. The transmission lines PDAT1and PDAT2are illustrated as n bus wiring lines inFIG. 7. The signal transmission/reception unit10includes the input/output units12aand12b. The input/output unit12ais connected to the transmission line PDAT1. The input/output unit12bis connected to the transmission line PDAT2. The signal transmission/reception unit10includes a memory unit11. Furthermore, the memory unit11and the input/output units12aand12bare connected to the transmission line IDAT for input/output signal transmission from the transmission line SDAT. The transmission lines IDAT and SDAT are illustrated as n bus wiring lines inFIG. 7. The signal transmission/reception unit10stores a predetermined signal input via the transmission line SDAT in the memory unit11and sequentially transmits the predetermined signal to the input/output units12aand12b. Furthermore, the input/output units12aand12bof the signal transmission/reception unit10each receive a pixel signal from the pixels2ato2d, and the signal transmission/reception unit10sequentially outputs the pixel signal as the output signal SDAT of the photoelectric conversion apparatus1.

The pixels2ato2deach include an input/output unit27and the pixel circuit units21and25. The input/output units27of the pixels2aand2bare connected to the transmission line PDAT1. Similarly, the input/output units27of the pixels2cand2dare connected to the transmission line PDAT2. The column selection control line HSEL1is connected to the horizontal scan unit5and the input/output units27of the pixels2aand2c. Similarly, the column selection control line HSEL2is connected to the horizontal scan unit5and the input/output units27of the pixels2band2d. The horizontal scan unit5feeds a control signal to the column selection control lines HSEL1and HSEL2to thereby enable predetermined signal transmission/reception and pixel signal transmission. The signal transmission/reception unit10synchronizes with the horizontal scan unit5using the control line HSEL0.

With the above-described configuration, the input/output units12aand12bsequentially receive a predetermined signal output from the memory unit11and transmit the predetermined signal to the pixels2ato2d. Furthermore, the input/output units12aand12breceive a pixel signal from each of the pixels2ato2dand sequentially output the pixel signal as the output signal SDAT of the photoelectric conversion apparatus1by an action of the signal transmission/reception unit10.

Operations of the photoelectric conversion apparatus1inFIG. 7will be described below with reference to a timing chart inFIG. 8.

FIG. 8illustrates timings of signals fed to the control lines LSEL1, LSEL2, VSEL1, and VSEL2by the vertical scan unit3, a signal fed to the control line HSEL0by the signal transmission/reception unit10, and signals fed to the column selection control lines HSEL1and HSEL2by the horizontal scan unit5.FIG. 8further illustrates data about the transmission lines PDAT1, PDAT2, and IDAT, the input/output signal SDAT, and the vertical scan synchronization signal VD.

InFIG. 8, at time t1, data S00is input to the photoelectric conversion apparatus1. The data S00is a data group (plurality of predetermined signals) corresponding to the predetermined signals for the pixels2ato2dand as described above, the data S00is stored in the memory unit11via the transmission line IDAT.

At time t3, the control lines LSEL1and LSEL2are changed to the high-level, and then the photoelectric conversion apparatus1changes to an operation of outputting a predetermined signal to the pixels2ato2d.

At time t4, the data M11is transmitted from the memory unit11to the transmission line IDAT, and is stored in the input/output unit12a. As the control lines VSEL1and HSEL0are changed to the high-level, the column selection control line HSEL1is changed to the high-level, and then the input/output unit27of the pixel2areceives the data M11via the transmission line PDAT1and outputs the data M11to the pixel circuit unit25. At time t5, the data M12is transmitted from the memory unit11to the transmission line IDAT, and is stored in the input/output unit12a. As the control line HSEL0is changed to the high-level, the column selection control line HSEL2is changed to the high-level, and then the input/output unit27of the pixel2breceives the data M12via the transmission line PDAT1and outputs the data M12to the pixel circuit unit25. Similarly, at time t6, the data M21is transmitted from the memory unit11to the transmission line IDAT, and is stored in the input/output unit12b. As the control lines VSEL2and HSEL0are changed to the high-level, the column selection control line HSEL1is changed to the high-level, and then the input/output unit27of the pixel2creceives the data M21via the transmission line PDAT2and outputs the data M21to the pixel circuit unit25. At time t7, the data M22is transmitted from the memory unit11to the transmission line IDAT, and is stored in the input/output unit12b. As the control line HSEL0is changed to the high-level, the column selection control line HSEL2is changed to the high-level, and then the input/output unit27of the pixel2dreceives the data M22via the transmission line PDAT2and outputs the data M22to the pixel circuit unit25.

At this time point, the pixels2a,2b,2cand2dhave respectively received the data M11, M12, M21and M22as predetermined signals. Thus, the pixels2a,2b,2cand2dare each controlled based on the corresponding predetermined signal received by the pixel circuit units25. At time t8, the control lines LSEL1and LSEL2is changed to the low-level, and at time t9, the vertical scan synchronization signal VD is changed to the high-level, and then the photoelectric conversion apparatus1changes to an operation of outputting a pixel signal based on photoelectric conversion.

At time t9, the control lines VSEL1and HSEL0are changed to the high-level and the column selection control line HSEL1is changed to the high-level, and then the input/output unit27of the pixel2aoutputs the pixel signal P11to the input/output unit12a. At this time, a signal based on the pixel signal P11from the pixel2ais output as the output signal S11of the photoelectric conversion apparatus1from the signal transmission/reception unit10via the transmission line IDAT. At time t10, the control line HSEL0is changed to the high-level and the column selection control line HSEL2is changed to the high-level, and then the input/output unit27of the pixel2boutputs the pixel signal P12to the input/output unit12a. At this time, a signal based on the pixel signal P12from the pixel2bis output as the output signal S12of the photoelectric conversion apparatus1from the signal transmission/reception unit10via the transmission line IDAT. Similarly, at time t11, the control lines VSEL2and HSEL0are changed to the high-level and the column selection control line HSEL1is changed to the high-level, and then the input/output unit27of the pixel2coutputs the pixel signal P21to the input/output unit12b. At this time, a signal based on the pixel signal P21from the pixel2cis output as the output signal S21of the photoelectric conversion apparatus1from the signal transmission/reception unit10via the transmission line IDAT. At time t12, the control line HSEL0is changed to the high-level and the column selection control line HSEL2is changed to the high-level, and then the input/output unit27of the pixel2doutputs the pixel signal P22to the input/output unit12b. At this time, a signal based on the pixel signal P22from the pixel2dis output as the output signal S22of the photoelectric conversion apparatus1from the signal transmission/reception unit10via the transmission line IDAT. Thereafter, the vertical scan synchronization signal VD is changed to the low-level, and at time t13, the vertical scan synchronization signal VD is changed to the high-level again, and then the photoelectric conversion apparatus1repeats an operation of outputting a pixel signal based on photoelectric conversion.

As described above, the input/output units12aand12beach transmit a predetermined signal to the input/output units27of the pixels2ato2din the photoelectric conversion apparatus1according to the present exemplary embodiment, so that predetermined signal writing to the pixels2ato2dand pixel signal reading from the pixels2ato2dare both controlled. At this time, the horizontal scan unit5and the vertical scan unit3control selection of signal transmission to the pixels2ato2d. The input/output units27of the pixels2ato2dtransmit a pixel signal to the input/output units12aand12b, so that the photoelectric conversion apparatus1outputs a pixel signal based on photoelectric conversion. At this time, the vertical scan unit3and the horizontal scan unit5control selection of signal transmission to the pixels2ato2d. Thus, the vertical scan unit3and the horizontal scan unit5are commonly used to control both predetermined signal transmission and pixel signal transmission. With the above-described configuration, the photoelectric conversion apparatus1according to the present exemplary embodiment realizes both control of predetermined signal writing to and pixel signal reading from the pixels2ato2dand circuit area reduction. Furthermore, the transmission line PDAT1is commonly connected to the plurality of pixels2aand2bof the same row of the pixel array unit2, and the transmission line PDAT2is commonly connected to the plurality of pixels2cand2dof the same row of the pixel array unit2, and the signal transmission/reception unit10includes the input/output units12aand12bin the photoelectric conversion apparatus1according to the present exemplary embodiment. This realizes faster pixel signal reading than the photoelectric conversion apparatus1according to the third exemplary embodiment.

In the present exemplary embodiment, the transmission lines PDAT1, PDAT2, and IDAT are illustrated as n bus wiring lines. This is based on a case where a pixel signal from each of the pixels2ato2dis n-bit data, and a predetermined signal output from the memory unit11does not necessarily have to be n-bit data. For example, a predetermined signal can be m-bit data, where m is less than n. In such a case, a predetermined signal can be transmitted from the memory unit11to the pixels2ato2dvia the transmission line IDAT and part of the transmission lines PDAT1and PDAT2. Employing several-bit data as a predetermined signal improves the function of controlling each pixel in predetermined signal writing and pixel signal reading. For example, an exposure time is controlled for each pixel.

A fifth exemplary embodiment of the present disclosure will be described below. An image capturing system according to the present exemplary embodiment will be described below with reference toFIG. 9.FIG. 9is a block diagram illustrating an example of a configuration of the image capturing system according to the present exemplary embodiment.

As illustrated inFIG. 9, an image capturing system200according to the present exemplary embodiment includes a barrier201, a lens202, a diaphragm203, a photoelectric conversion apparatus204, and an autofocus (AF) sensor205. The lens202is an optical system configured to form an optical subject image. The barrier201protects the lens202. The diaphragm203adjusts the amount of light that passes through the lens202. The photoelectric conversion apparatus204employs the photoelectric conversion apparatus1according to any of the first to fourth exemplary embodiments and acquires an optical subject image formed by the lens202as an image signal. The AF sensor205acquires a signal for focal point detection.

The image capturing system200further includes a signal processing unit208. The signal processing unit208processes a signal output from the photoelectric conversion apparatus204or the AF sensor205and performs various types of correction on acquired image data or compresses data.

The image capturing system200further includes a memory unit209, an external interface (external I/F) circuit210, a timing generation unit211, an overall control/calculation unit212, and a recording medium control interface (recording medium control I/F) unit213. The memory unit209temporarily stores image data. The external I/F circuit210communicates with an external device such as an external computer215. The timing generation unit211outputs various timing signals to the signal processing unit208. The overall control/calculation unit212controls various types of calculation and an entire camera. The recording medium control I/F unit213transmits and receives data to and from a removable recording medium214such as a semiconductor memory for recording acquired image data or reading image data.

When the barrier201is opened, an optical image from a subject enters the AF sensor205via the lens202and the diaphragm203. The overall control/calculation unit212calculates a distance to the subject by a phase difference detection method based on the output signal from the AF sensor205. Thereafter, the overall control/calculation unit212drives the lens202based on the calculation result and determines whether an image capturing surface is in focus again. In a case where the overall control/calculation unit212determines that the image capturing surface is not in focus, the overall control/calculation unit212performs AF control to drive the lens202again.

Next, after the overall control/calculation unit212determines that the image capturing surface is in focus, the photoelectric conversion apparatus204starts an electric charge accumulation operation. If the photoelectric conversion apparatus204finishes the electric charge accumulation operation, the overall control/calculation unit212writes an image signal output from the photoelectric conversion apparatus204to the memory unit209via the signal processing unit208.

Thereafter, data accumulated in the memory unit209is recorded on the recording medium214via the recording medium control I/F unit213under control by the overall control/calculation unit212. Alternatively, data accumulated in the memory unit209can be input directly to the external computer215via the external I/F circuit210.

As described above in the first to fourth exemplary embodiments, use of the photoelectric conversion apparatus1according to any of the first to fourth exemplary embodiments realizes control of both digital signal writing to and digital signal reading from the pixels2ato2d. Thus, with the image capturing system200according to the present exemplary embodiment using the photoelectric conversion apparatus204, an image with improved quality is acquired.

A sixth exemplary embodiment of the present disclosure will be described below. An image capturing system and a moving object according to the present exemplary embodiment will be described below with reference toFIGS. 10A and 10B.FIGS. 10A and 10Billustrate configurations of the image capturing system and the moving object according to the present exemplary embodiment.

FIG. 10Aillustrates an example of an image capturing system that relates to an in-vehicle camera. An image capturing system300includes an image capturing apparatus310. The image capturing apparatus310is a photoelectric conversion apparatus1according to any one of the first to fourth exemplary embodiments. The image capturing system300includes an image processing unit312and a parallax acquisition unit314. The image processing unit312performs image processing on a plurality of pieces of image data acquired by the image capturing apparatus310. The parallax acquisition unit314calculates a parallax (phase difference in parallax image) from the plurality of pieces of image data acquired by the image capturing system300. The image capturing system300includes a distance acquisition unit316and a collision determination unit318. The distance acquisition unit316calculates a distance to a target object based on the calculated parallax. The collision determination unit318determines a possibility of a collision based on the calculated distance. The parallax acquisition unit314and the distance acquisition unit316are an example of a distance information acquisition unit configured to acquire distance information about a distance to a target object. Specifically, the distance information is information about a parallax, defocus amount, and distance to a target object. The collision determination unit318may determine a possibility of a collision using any of the distance information. The distance information acquisition unit may be realized by dedicated hardware or software module. Alternatively, the distance information acquisition unit may be realized by a field programmable gate array (FPGA) or an application-specific integrated circuit (ASIC) or a combination thereof.

The image capturing system300is connected to a vehicle information acquisition apparatus320and acquires vehicle information, such as a vehicle speed, yaw rate, and rudder angle. The image capturing system300is connected to a control engine control unit (ECU)330. The control ECU330is a control apparatus configured to output a control signal for generating braking force on a vehicle based on a determination result of the collision determination unit318. The image capturing system300is also connected to a warning apparatus340configured to provide a warning to a driver based on the determination result of the collision determination unit318. For example, in a case where the collision determination unit318determines that there is a high possibility of a collision, the control ECU330controls the vehicle to avoid a collision or reduce damage by applying a brake, releasing an accelerator, or reducing the engine output. The warning apparatus340warns a user by producing a warning sound, displaying warning information on a screen of a car navigation system, or vibrating a seatbelt or steering.

In the present exemplary embodiment, the image capturing system300captures an image of a region in the vicinity of the vehicle, e.g., the front or back of the vehicle.FIG. 10Billustrates the image capturing system300in a case where an image of the front (image capturing range350) of the vehicle is captured. The vehicle information acquisition apparatus320transmits an instruction to the image capturing system300or the image capturing apparatus310. This configuration further increases the accuracy of distance measurement.

While the example where control is performed to not collide with other vehicles is described above, the present exemplary embodiment is also applicable to the control of automatic driving to follow another vehicle or the control of automatic driving to stay within a traffic lane. Furthermore, the image capturing system300is applicable not only to vehicles such as private vehicles but also to moving objects (moving apparatuses), such as ships, aircraft, or industrial robots. The image capturing system300is also applicable not only to moving objects but also to devices that widely use object recognition, such as an intelligent transport system (ITS).

A seventh exemplary embodiment of the present disclosure will be described below.FIG. 11illustrates a configuration example of a photoelectric conversion apparatus101according to the present exemplary embodiment. The photoelectric conversion apparatus101according to the present exemplary embodiment is a photon-counting photoelectric conversion apparatus. The photon counting photoelectric conversion apparatus employs an avalanche diode as a photoelectric conversion unit and counts the number of photons incident on the avalanche diode. A configuration outline of the photoelectric conversion apparatus101and the functions thereof will be described below.

The photoelectric conversion apparatus101according to the present exemplary embodiment includes pixels102to105, a counter control circuit106, and a count-upper-limit storage circuit107as illustrated inFIG. 11.

FIG. 11illustrates a case where the pixels102to105arranged in two rows and two columns. The numbers of rows and columns of pixels are not limited thereto.

The configuration of the pixel102will be mainly described as a representative of the configurations of pixels102to105. The pixel102includes a photoelectric conversion unit, a switch108(switches109to111for the pixels103to105, respectively), a power supply unit, a ground, a resistor, and a counter circuit112(counter circuits113to115for the pixels103to105, respectively). The photoelectric conversion unit includes an avalanche diode.

One node of the photoelectric conversion unit is connected to the ground, and a ground potential is applied to the node. The other node of the photoelectric conversion unit is connected to the power supply unit via the switch108and the resistor. The turning on and off of the switch108is controlled to control supply of a power source voltage to the other node of the photoelectric conversion unit. The resistor is connected to a position between the switch108and the power supply unit.

The counter circuit112is connected to a connection node between the switch108and the resistor. Signals from the photoelectric conversion unit are transmitted to the counter circuit112via the switch108. While not illustrated, the counter circuit112may be connected to a connection node between the switch108and the resistor via an inverter circuit that configures a waveform shaping circuit. In such a case, electrical signals having been subjected to the photoelectric conversion are shaped into digital signals through the waveform shaping circuit, and the digital signals are transmitted to the counter circuit112.

Horizontal control lines HL1and HL2are each connected to the counter control circuit106. The horizontal control line HL1is connected to the counter circuits112and113of the pixels102and103, respectively, which are arranged in the horizontal direction. The horizontal control line HL2is connected to the counter circuits114and115of the pixels104and105, respectively, which are arranged in the horizontal direction. Vertical control lines VL1and VL2are each connected to the counter control circuit106. The vertical control line VL1is connected to the counter circuits112and114of the pixels102and104, respectively, which are arranged in the vertical direction. The vertical control line VL2is connected to the counter circuits113and115of the pixels103and105, respectively, which are arranged in the vertical direction.

Output lines OL1and OL2are each connected to the counter control circuit106. The output line OL1is connected to the counter circuits112and114, and is used for transmitting a pixel signal output from each of the counter circuits112and114. The output line OL2is connected to the counter circuits113and115, and is used for transmitting a pixel signal output from each of the counter circuits113and115. The number of bits of each of the signals is not limited.

A count-upper-limit request signal line and a count-upper-limit output signal line are connected to the count-upper-limit storage circuit107and the counter control circuit106. The counter control circuit106transmits a signal for requesting a count-upper limit to the count-upper-limit storage circuit107by the count-upper-limit request signal line. The count-upper-limit storage circuit107outputs a count-upper limit (count-upper-limit output signal) to the counter control circuit106by the count-upper-limit output signal line. The number of bits of each of the count-upper-limit request signal and the count-upper-limit output signal is not limited.

FIG. 11illustrates the counter control circuit106only in the horizontal direction, and the horizontal control lines HL1and HL2are detoured. Alternatively, the counter control circuit106may be arrange in both the horizontal and vertical directions, and the horizontal control lines HL1and HL2may be connected to the counter control circuit106in the vertical direction. Such an arrangement reduces a density of signal lines near the counter control circuit106.

The counter control circuit106transmits, by the horizontal control line HL1, a counter selection signal, a count value request signal, a counter-stop-command signal, and a counter-reset-command signal to the counter circuits112and113of the pixels102and103, respectively, arranged in the horizontal direction. The counter control circuit106transmits, by the horizontal control line HL2, the counter selection signal, the count value request signal, the counter-stop-command signal, and the counter-reset-command signal to the counter circuits114and115of the pixels104and105, respectively, arranged in the horizontal direction. The counter control circuit106transmits, by the vertical control line VL1, the counter selection signal, the count value request signal, the counter-stop-command signal, the counter-reset-command signal to the counter circuits112and114of the pixels102and104, respectively, arranged in the vertical direction. The counter control circuit106transmits, by the vertical control line VL2, the counter selection signal, the count value request signal, the counter-stop-command signal, the counter-reset-command signal to the counter circuits113and115of the pixels103and105, respectively, arranged in the vertical direction.

FIG. 12illustrates a configuration example of a pixel. InFIG. 12, the configuration of the pixel102is illustrated as a representative description of the pixels102to105. The configuration of the other pixels, the pixels103to105, is similar to that of the pixel102, and thus, descriptions thereof are omitted.

The horizontal control lines HL01to HL04illustrated inFIG. 12correspond to the horizontal control line HL1illustrated inFIG. 11. The vertical control lines VL01to VL04illustrated inFIG. 12correspond to the vertical control line VL1illustrated inFIG. 11. Thus, the horizontal control lines HL01to HL04and the vertical control lines VL01to VL04are connected to the counter control circuit106.

The counter circuit112is controlled by control of the potential to be applied to the horizontal control lines HL01to HL04constituting the horizontal control line HL1and to the vertical control lines VL01to VL04constituting the vertical control line V11

The pixel102further includes a pixel selection switch123, a count-value-request switch124, a counter-off-command switch125, a counter-value-output switch126, and a counter reset switch127which are connected to the counter circuit112, as illustrated inFIG. 12.FIG. 12illustrates an example in which each switch is configured with a transistor, but the configuration of each switch is not limited thereto. A transfer gate may be used as each switch.

The pixel selection switch123is connected to the horizontal control line HL01and the vertical control line VL01. The counter circuit112is selected as a control target in a case where both the horizontal control line HL01and the vertical control line VL01become a high-level.

The count-value-request switch124is connected to the counter-value-output switch126. Such a structure realizes the configuration in which the counter-value-output switch126is turned ON in a case where the count-value-request switch124is turned ON, which will be described in detail below.

The count-value-request switch124is connected to the horizontal control line HL02and the vertical control line VL02. In a case where both the horizontal control line HL02and the vertical control line VL02become a high level, a count value of the counter circuit112is requested, and the count-value-request switch124is turned ON.

The counter-off-command switch125is connected to the counter circuit112. The counter-off-command switch125is also connected to the horizontal control line HL03and the vertical control line VL03. The counter-off-command switch125is turned on in a case where both the horizontal control line HL03and the vertical control line VL03become a high level, and an OFF-signal for stopping a counting operation is transmitted to the counter circuit112. This stops the counting operation of the counter circuit.

The counter reset switch127is connected to the counter circuit112. The counter reset switch127is also connected to the horizontal control line HL04and the vertical control line VL04. The counter reset switch127is turned ON in a case where both the horizontal control line HL04and the vertical control line VL04become a high level, and a counter-reset signal is transmitted to the counter circuit112. This resets the count value of the counter circuit.

The counter-value-output switch126is connected to the counter circuit112, the count-value-request switch124, and the output line OL1. WhileFIG. 12illustrates one bit of data is output, a plurality of bits of data may be output. In such a case, as many signal lines as the number of bits of data to be output from the counter-value-output switch126are required.

In a case where the count-value-request switch124is turned on and the count value is output from the counter circuit112, the count value is output via the counter-value-output switch126to the output line OL1.

In this circuit configuration, the number of switches necessary for the counter control for each pixel is five when information for the count value is one bit. Thus, the circuit scale necessary for the counter control is kept at minimum.

While the pixel selection switch123is connected to the counter circuit112inFIG. 12, the pixel selection switch123may be connected to a pixel element other than the counter circuit112.

FIG. 13illustrates a flowchart of the counter circuit control of the photoelectric conversion apparatus101according to the seventh exemplary embodiment.

Initially in step S301, the counter control circuit106issues a request for a count-upper limit to the count-upper-limit storage circuit107. In step302, the count-upper-limit storage circuit107then outputs the count-upper limit to the counter control circuit106.

In step S303, the counter control circuit106issues a request for the count value to the counter circuit112. In step S304, the counter circuit112transmits the count value to the counter control circuit106.

Next in step S305, the counter control circuit106compares the count value and the count-upper limit.

The flowchart inFIG. 13illustrates merely an example, and the operations in step S301, S302, S303, and S304may be simultaneously performed if the operations in step S301to S304are completed before the execution of the operation in step S305.

If the count value is greater than or equal to the count-upper limit (YES, in step S305), the processing proceeds to step S306. In step S306, the counter control circuit106transmits a counter-off instruction to the counter circuit112.

If the count value is less than the count-upper limit (NO, in step S305), the processing proceeds to step S307. In step S307, the counter control circuit106does not transmit the counter-OFF instruction to stop the counting operation to the counter circuit112.

In steps S308and S309, it is determined whether the comparison is performed for all target pixels in order to move the control target to a different pixel.

If it is determined that not all the target pixels have been subjected to the comparison, the processing proceeds to step S310. In step S310, a different pixel is selected. The processing then returns to step S301.

The foregoing processing is merely an example, and, in a case where the count-upper limit is not changed, the processing may return, not to step S301, but to step S303. Then, the operation of the processing may be performed. In such a case, it can be expected that processing speed will be improved.

A method for selecting a different pixel is not limited. For example, the different pixel may be selected one by one in a row direction or a column direction. The providing of the method for selecting the different pixel to the counter control circuit106enables the counter control circuit106to determine whether the comparison is performed for all the target pixels.

If it is determined that the comparison is performed for all the target pixels (YES, in step S308or in step S309), the processing proceeds to step S311. In step S311, a signal for resetting the count value is transmitted to all pixels. In step S312, the counter-off instruction is cancelled for all the pixels. The operation in step S312enables a restart of the counting.

FIG. 14illustrates a timing chart of the counter control of the photoelectric conversion apparatus101according to the present exemplary embodiment in a case where the counter is turned off. The operation of the photoelectric conversion apparatus101illustrated inFIG. 11will be described below with reference toFIG. 14.

FIG. 14illustrates an upper limit to be stored in the count-upper-limit storage circuit107.FIG. 14further illustrates an upper-limit request command (count-upper-limit request signal) which the counter control circuit106transmits, an acquired upper limit which is received by the counter control circuit106, a count value request command which the counter control circuit106transmits, an acquired count value which the counter control circuit106receives, and a counter-OFF instruction which the counter control circuit106transmits. A counter signal in a certain pixel is illustrated with three bits. Here, the counter signal may be greater or less than, or equal to three bits.

InFIG. 14, at time T1, a signal for the upper-limit request command is changed to a high level. As a result, the acquired upper limit is updated. At time T2, a counter circuit in a certain pixel starts an operation.

At time T3, a signal for the count value request command is changed to a high level. As a result, the count value is transmitted to the counter control circuit106from the certain pixel, and the acquired count value is updated

The acquired upper limit and the acquired count value are then compared, and, in a case where the acquired count value is greater than or equal to the acquired upper limit, the counter-OFF instruction of the counter control circuit106is changed to the high level at time T4.

In response to the certain pixel having received the counter-OFF instruction signal at the high level, the counter circuit of the certain pixel is stopped and the counter operation becomes an off state. In such a case, the respective bits of the signals in the counter circuit retain the values thereof before the stop.

While the operation at time T2is performed after the operation at time T1inFIG. 14, the order of the operations is not limited thereto. For example, the operation at time T2may be performed before the operation at time T1, or the operation at time T1and the operation at time T2may be simultaneously performed.

FIG. 15illustrates a timing chart of the counter control of the photoelectric conversion apparatus101according to the present exemplary embodiment in a case where the counter circuit is not turned off. The operation of the photoelectric conversion apparatus101illustrated inFIG. 11will be described below with reference toFIG. 15.

The names of the signals illustrated inFIG. 15are the same as those inFIG. 14, and thus, descriptions thereof are omitted. The operations at times T1and T2are similar to those inFIG. 14, and thus, descriptions thereof are omitted.

After the acquired count value is updated, the acquired upper limit and the acquired count value are compared at time T3, and, in a case where the acquired count value is less than the acquired upper limit, the signal for the counter-OFF instruction of the counter control circuit106is kept at a low level. Accordingly, the counter circuit of a certain pixel is continued to operate.

FIG. 16illustrates a timing chart of the counter control of the photoelectric conversion apparatus101according to the present exemplary embodiment in a case where the counter circuit is restarted. The operation of the photoelectric conversion apparatus101illustrated inFIG. 11will be described below with reference toFIG. 16.

The names of the signals illustrated inFIG. 16are the same as those ofFIG. 14except for a counter-reset instruction, and thus, descriptions of those with the same names are omitted.

FIG. 16illustrates a counter-reset instruction which is transmitted from the counter control circuit106to a pixel circuit. The operations at times T1, T2, and T3are similar to those inFIG. 14, and thus, descriptions thereof are omitted.

A signal for the counter-reset instruction of the counter control circuit106to reset the counter circuit is changed to a high level at time T5. In response to the pixel circuit having received the high signal for the counter-reset instruction, all bits of the counter circuit of the pixel circuit are changed to a low level. In other words, the counter circuit is reset.

At time T6, the signal for the counter-off instruction of the counter control circuit106is changed to the low level. In response to a certain pixel circuit having received the low signal for the counter-off instruction, the counter of the certain pixel circuit starts operation. In other words, the counter circuit is restarted.

According to the present exemplary embodiment, a signal based on a signal output from a pixel is input to the pixel as described above. More specifically, a signal for controlling a counter circuit is input to the counter circuit of a pixel on the basis of a signal output from the counter circuit.

According to the present exemplary embodiment, the counter control circuit106individually controls each of a plurality of pixels. Thus, the circuit scale can be reduced compared with a configuration in which the counter control circuit106is provided for each pixel. Additionally, power consumption can be reduced by the counter circuit being turned off in a case where the count value is greater than or equal to the count-upper limit.

An eighth exemplary embodiment of the present disclosure will be described below.FIG. 17illustrates a schematic configuration example of a photoelectric conversion apparatus101according to the present exemplary embodiment. The photoelectric conversion apparatus101according to the present exemplary embodiment is different from the seventh exemplary embodiment in that a photoelectric conversion unit includes a photodiode and each pixel includes an analog to digital converter (ADC) circuit in the present exemplary embodiment. The eighth exemplary embodiment will be described, assigning the same reference numerals or signs to portions similar to the seventh exemplary embodiment and omitting descriptions thereof.

FIG. 17illustrate a configuration example of the photoelectric conversion apparatus101according to the eighth exemplary embodiment. The photoelectric conversion apparatus101according to the present exemplary embodiment includes pixels102to105, a counter control circuit106, and a count-upper-limit storage circuit107as illustrated inFIG. 17.

The pixels102to105each include the ADC circuit as described above. WhileFIG. 17illustrates a case where the pixels102to105are arranged in two rows and two columns, the numbers of the rows and the columns are not limited thereto.

The configuration of pixel102will be mainly described as a representative of the configurations of pixels102to105. The pixel102includes a photoelectric conversion unit, a switch108(switches109to111for the pixels103to105, respectively), a power supply unit, a ground, a resistor, and the ADC circuit701(ADC circuits702to704for the pixels103to105, respectively). The ADC circuit701includes a counter circuit705and a comparison circuit709(ADC circuits702to704each include counter circuits706to708, respectively).

One node of the photoelectric conversion unit is connected to the ground, and the ground potential is applied to the node. The other node of the photoelectric conversion unit is connected to the power supply unit via the switch108and the resistor. The turning on and off of the switch108is controlled to control supply of power source voltage to the other node of the photoelectric conversion unit. The resistor is connected to a position between the switch108and the power supply unit.

The other node of the photoelectric conversion unit is connected to the power supply unit via the switch108.

The configuration of the ADC circuit701will be described below as a representative of the configuration of each of the ADC circuits701to704. The ADC circuit701includes a counter circuit705and a comparison circuit709.

A signal from the photoelectric conversion unit is transmitted to the comparison circuit709via the switch108. The comparison circuit709is connected to a Vref signal line for a Vref signal used for a reference voltage. The Vref signal may be included in each pixel or set from a circuit outside of the pixels102to105.

The counter circuit705and the comparison circuit709are connected, and configured to output signals to each other. For example, the comparison circuit709is capable of outputting to the counter circuit705a signal for requesting a count value. The counter circuit705is capable of outputting the count value to the comparison circuit709.

The counter circuit705has the function of measuring a time for an output voltage from the photoelectric conversion unit to reach a reference voltage.

The comparison circuit709has, for example, the function of comparing the reference voltage and the output voltage from the photoelectric conversion unit.

Here, the circuit configuration inFIG. 17is based on the assumption that analog to digital (AD) conversion is performed based on the comparison of the reference voltage and the output voltage. However, if a configuration including a counter circuit is employed, the method used for the ADC circuit is not limited thereto.

A horizontal control line HL1is connected to the counter control circuit106and the counter circuits705and706of the pixels102and103, respectively, which are arranged in the horizontal direction. A horizontal control line HL2is connected to the counter control circuit106and the counter circuits707and708of the pixels104and105, respectively, which are arranged in the horizontal direction. A vertical control line VL1is connected to the counter control circuit106and the counter circuits705and707of the pixels102and104, respectively, which are arranged in the vertical direction. A vertical control line VL2is connected to the counter circuits706and708of the pixels103and105, respectively, which are arranged in the vertical direction.

An output line OL1is connected to the counter control circuit106and the counter circuits705and707of the pixels102and104, respectively, which are arranged in the vertical direction. An output line OL2is connected to the counter control circuit106and the counter circuits706and708of the pixels103and105, respectively, which are arranged in the vertical direction. The number of bits of the signals are not limited.

While the counter control circuit106is arranged only in the horizontal direction also inFIG. 17, the counter control circuit106may be arranged in both the horizontal and vertical directions as in the seventh exemplary embodiment.

The counter control circuit106transmits, by the horizontal control line HL1, a counter selection signal, a count value request signal, a counter-stop-command signal, a counter-reset-command signal to the counter circuits705and706of the pixels102and103, respectively, which are arranged in the horizontal direction. The counter control circuit106transmits, by the horizontal control line HL2, the counter selection signal, the count value request signal, the counter-stop-command signal, and the counter-reset-command signal to the counter circuits707and708of the pixels104and105, respectively, which are arranged in the horizontal direction.

The counter control circuit106transmits, by the vertical control line VL1, the counter selection signal, the count value request signal, the counter-stop-command signal, and the counter-reset-command signal to the counter circuits705and707of the ADC circuits701and703in the pixels102and104, respectively, which are arranged in the vertical direction. The counter control circuit106transmits, by the vertical control line VL2, the counter selection signal, the count value request signal, the counter-stop-command signal, and the counter-reset-command signal to the counter circuits706and708of the ADC circuits702and704in the pixels103and105, respectively, which are arranged in the vertical direction.

The output line OL1is used for transmitting the count value to the counter control circuit106from each of the counter circuits705and707of the ADC circuits701and703in the pixels102and104arranged in the vertical direction. The output line OL2is used for transmitting the count value to the counter control circuit106from each of the counter circuits706and708of the ADC circuits702and704in the pixels103and105arranged in the vertical direction.

A count-upper-limit request signal line and a count-upper-limit output signal line are connected to the count-upper-limit storage circuit107and the counter control circuit106. The range of bits for the count-upper-limit request signal line and the count-upper-limit output signal line are not limited.

The count-upper-limit request signal line is used for transmitting a signal for requesting the count-upper limit from the counter control circuit106to the count-upper-limit storage circuit107. The count-upper-limit output signal line is used for transmitting the count-upper limit from the count-upper-limit storage circuit107to the counter control circuit106.

The above-described configuration enables the counter control circuit106to control each of the plurality of pixel circuits. Thus, the circuit scale is reduced compared with a configuration in which the counter control circuit106is provided for each of the plurality of pixels.

FIG. 18illustrates a configuration example of a pixel according to the present exemplary embodiment. The pixel includes a photoelectric conversion unit, a switch, a power supply unit, a ground, a resistor, and the ADC circuit. The pixel further includes a pixel selection switch123, a count-value-request switch124, a counter-off-command switch125, a counter-value-output switch126, and a counter reset switch127. The ADC counter circuit includes the counter circuit and the comparison circuit. The Vref signal and the configuration of the comparison circuit are similar to those described with reference toFIG. 17. WhileFIG. 18illustrates an example in which each switch is configured with a transistor, the configuration of the switch is not limited to the transistor. A transfer gate may be used as each switch.

The pixel selection switch123, the count-value-request switch124, the counter-off-command switch125, the counter-value-output switch126, and the counter reset switch127are connected to the counter circuit in the ADC circuit. Other than this configuration, the configuration and the function of the pixel are similar to those described in the seventh exemplary embodiment, and thus, descriptions thereof are omitted.

The processing of the counter control operation and the timing chart according to the present exemplary embodiment are similar to those in a case where a single photon avalanche diode (SPAD) pixel that performs photon counting is used (as illustrated inFIGS. 13 to 16).

According to the present exemplary embodiment, a signal based on a signal output from a pixel is input to the pixel as described above. More specifically, a signal for controlling the counter circuit is input to the counter circuit of the pixel on the basis of a signal output from the counter circuit.

The present exemplary embodiment also enables the counter control circuit106to control each of the plurality of pixels, as in the seventh exemplary embodiment. Thus, the circuit scale can be reduced compared with the configuration in which the counter control circuit106is arranged for each pixel. Additionally, power consumption can be reduced by the counter circuit being turned off in a case where the count value is greater than or equal to the count-upper limit.

A ninth exemplary embodiment of the present disclosure will be described below.FIG. 19illustrate a configuration example of a photoelectric conversion apparatus101according to the present exemplary embodiment. The photoelectric conversion apparatus101according to the present exemplary embodiment is different from the seventh exemplary embodiment in that the exposing of each pixel is controlled in the present exemplary embodiment. The ninth exemplary embodiment will be described, assigning the same reference numerals or signs to portions similar to the seventh exemplary embodiment and omitting descriptions thereof.

The photoelectric conversion apparatus101according to the present exemplary embodiment includes a pixel address designation circuit901, and a pixel address storage circuit902in addition to the components illustrated inFIG. 11. The pixels102to105include exposure command switches903to906, respectively.

A horizontal exposure control line HEL1is connected to the pixel address designation circuit901and the exposure command switches903and904of the pixels102and103arranged in the horizontal direction. A horizontal exposure control line HEL2is connected to the pixel address designation circuit901and the exposure command switches905and906of the pixels104and105arranged in the horizontal direction. A vertical exposure control line VEL1is connected to the pixel address designation circuit901and the exposure command switches903and905of the pixels102and104arranged in the vertical direction. The number of bits of each of the signals is not limited. A vertical exposure control line VEL2is connected to the pixel address designation circuit901and the exposure command switches904and906of the pixels103and105arranged in the vertical direction.

The horizontal exposure control line HEL1is used for transmitting an exposure command signal from the pixel address designation circuit901to switches108and109of the pixels102and103via the exposure command switches903and904, respectively. The horizontal exposure control line HEL2is used for transmitting the exposure command signal from the pixel address designation circuit901to switches110and111of the pixels104and105via the exposure command switches905and906, respectively.

The vertical exposure control line VEL1is used for transmitting the exposure command signal from the pixel address designation circuit901to the switches108and110of the pixels102and104via the exposure command switches903and905, respectively. The vertical exposure control line VEL2is used for transmitting the exposure command signal from the pixel address designation circuit901to switches109and111of the pixels103and105via the exposure command switches904and906, respectively.

A pixel address output signal line1is connected to the pixel address designation circuit901and the pixel address storage circuit902. The range of bits for the pixel address output signal line1is not limited.

The pixel address designation circuit901transmits a pixel address of a pixel to be exposed to the pixel address storage circuit902by the pixel address output signal line1.

A pixel address request signal line and a pixel address output signal line2are connected to the pixel address storage circuit902and the counter control circuit106. The range of bits for the pixel address output signal line2is not limited.

The counter control circuit106transmits a signal for requesting an address of a pixel to be controlled to the pixel address storage circuit902by the pixel address request signal line.

The pixel address storage circuit902outputs the address of the pixel to be controlled to the counter control circuit106by the pixel address output signal line2.

The above-described configuration enables the control of each pixel while limiting target pixels to exposed pixels by using the pixel address designation circuit901and the pixel address storage circuit902. Thus, the present exemplary embodiment reduces an operation time for the counter control while the circuit scale increases in the present exemplary embodiment, compared with the seventh exemplary embodiment.

FIG. 20illustrates a pixel configuration according to the present exemplary embodiment. Descriptions of portions similar to those inFIG. 12will be omitted.

An exposure command switch1001is connected to a switch.

The exposure command switch1001is connected to a horizontal control line HL05and a vertical control line VL05. The horizontal control line HL05and the vertical control line VL05are connected to the pixel address designation circuit901.

In a case where both the horizontal control line HL05and the vertical control line VL05are changed to a high level, the exposure command switch1001is turned on. The switch is turned on, accordingly, and an exposure is started for a target pixel.

The number of switches necessary for the counter control for each pixel is six when information about the count value is one bit. In the configuration of the present exemplary embodiment, pixels to be counter-controlled is limited with pixel addresses and the operation time can be reduced, while the circuit scale increases by the area of one switch, compared with the seventh exemplary embodiment.

FIG. 21illustrates a flowchart for acquiring an address of a pixel to be exposed, which is performed by the photoelectric conversion apparatus101according to the present exemplary embodiment.

Initially in step S1101, the pixel address designation circuit901transmits an exposure command to a target pixel. In step S1102, the address of the target pixel to which the pixel address designation circuit901outputs the exposure command is transmitted to the pixel address storage circuit902.

Next in step S1103, the counter control circuit106requests the pixel address from the pixel address storage circuit902. In step S1104, the pixel address storage circuit902then outputs the pixel address to the counter control circuit106.

The operations in step S1101to1104are repeated the same number of times as the number of pixels to be exposed. In such a case, in order to improve processing speed, pipeline processing may be performed.

Pipeline processing may be performed also in the processing of the flowchart according to the seventh exemplary embodiment illustrated inFIG. 13. In such a case, the operation in step S303inFIG. 13is performed after the operation in step S1104is completed at least once.

As described above, the present exemplary embodiment enables reduction of the circuit scale compared with a configuration in which the counter control circuit106is provided for each pixel. Moreover, control target pixels are limited only to exposed pixels in the present exemplary embodiment, so that the processing speed is improved compared with a case where all pixels are scanned.

A tenth exemplary embodiment of the present disclosure will be described.FIG. 22illustrates a configuration example of a photoelectric conversion apparatus101according to the present exemplary embodiment. The photoelectric conversion apparatus101according to the present exemplary embodiment is configured such that a photoelectric conversion unit is configured with a photodiode and each pixel includes an ADC circuit, which is different from the configuration according to the ninth exemplary embodiment. The tenth exemplary embodiment will be described, assigning the same reference numerals or signs to portions similar to the seventh exemplary embodiment or the ninth exemplary embodiment and omitting descriptions thereof.

FIG. 22illustrates a configuration example of the photoelectric conversion apparatus101according to the present exemplary embodiment. The photoelectric conversion apparatus101according to the present exemplary embodiment includes a pixel address designation circuit901and a pixel address storage circuit902in addition to the components illustrated inFIG. 17. The pixels102to105include exposure command switches903to906, respectively.

According to the present exemplary embodiment, target pixels are limited to exposed pixels by using the pixel address designation circuit901and the pixel address storage circuit902, and it is possible to control each of the pixels102to105. Thus, an operation time for counter control is reduced while the circuit scale of the photoelectric conversion apparatus101increases, compared with the configuration according to the eighth exemplary embodiment.

FIG. 23illustrates a configuration example of a pixel according to the present exemplary embodiment. Descriptions of portions similar to those inFIG. 18will be omitted.

An exposure command switch1001is connected to a switch. The configuration and the function in the present exemplary embodiment are similar to those in the ninth exemplary embodiment expect that the exposure command switch1001is connected to the counter circuit of the ADC circuit, and thus, descriptions thereof are omitted. The processing of flowchart for acquiring an address of a pixel to be exposed is similar to that of the flowchart inFIG. 21, and thus, descriptions thereof are omitted.

According to the present exemplary embodiment, control target pixels are limited to exposed pixels also in the photoelectric conversion apparatus101that includes the ADC circuit in the pixel circuit, so that the processing speed is improved compared with a case where all pixels are scanned, as described above.

The present disclosure is not limited to the above-described exemplary embodiments, and various modifications are possible. An example where a configuration of part of an exemplary embodiment is added to another exemplary embodiment and an example where a configuration of part of an exemplary embodiment is replaced by a configuration of part of another exemplary embodiment are also an exemplary embodiment of the present disclosure.

It should be noted that the exemplary embodiments disclosed herein are mere examples of implementation of the present disclosure and are not intended to limit interpretations of the technical scope of the present disclosure. In other words, the present disclosure is implementable in various forms within the technical concept or major feature of the present disclosure.

The present disclosure provides a photoelectric conversion apparatus that realizes both control of digital signal writing to and digital signal reading from a pixel and reduction of at least one of a circuit area and a wiring line area.

This application claims the benefit of Japanese Patent Applications No. 2019-180966, filed Sep. 30, 2019, and No. 2020-129815, filed Jul. 31, 2020 which are hereby incorporated by reference herein in their entirety.