Method for fabricating memory device having a deep trench capacitor

A method of fabricating a memory device having a deep trench capacitor is described. A first conductive layer is formed in the lower and middle portions of a deep trench in a substrate. An undoped semiconductor layer is formed in the upper portion of the deep trench. A mask layer is formed on the substrate, wherein the mask layercovers the periphery of the undoped semiconductor layer that is adjacent to the neighboring region, pre-defined for the active region of the deep trench. An ion implantation process is performed to implant dopants into the undoped semiconductor layer exposed by the mask layer so as to form a second conductive layer. The first and the second conductive layers constitute the upper electrode of the deep trench capacitor.

CROSS REFERENCE TO RELATED APPLICATIONS

This application claims the priority benefit of Taiwan application serial no. 92115650, filed on Jun. 10, 2003.

BACKGROUND OF INVENTION

1. Field of the Invention

The present invention relates to a fabrication method for a memory device. More particularly, the present invention relates to memory device with a deep trench capacitor.

2. Description of Related Art

Along with the miniaturization of devices, the dimensions of devices progressively diminish. As for a memory device that comprises a capacitor, the space for forming a capacitor also gradually reduces. A deep trench capacitor memory device which uses the space in the substrate to form a capacitor to render a greater area. A deep trench capacitor memory device thus conforms to the demands of the current market.

A conventional fabrication method for a deep trench capacitor memory device includes depositing multi layers of doped polysilicon layer to form an upper electrode. The upper most doped polysilicon layer is formed by forming a layer of non-crystalline silicon layer, followed by delivering an arsenic gas into the reaction chamber for arsenic to be adsorbed onto the non-crystalline silicon layer. An undoped polysilicon layer is further deposited. Thereafter, in a subsequent thermal process, dopants are driven-in to the undoped polysilicon layer to transform the non-crystalline silicon layer into a polysilicon layer.

In the above conventional method, during the diffusion of the arsenic ions that are being adsorbed on the non-crystalline silicon layer to the polysilicon layer, the arsenic ions may also diffuse into the substrate surrounding the deep trench. The substrate around the deep trench, as a result, also comprises the arsenic dopants. Therefore, in the subsequent definition of an active region, the active region may be shifted to the peripheral of the deep trench when a misalignment occurs. Since the channel region of the active region, which is positioned in the peripheral region of the deep trench, could have a high concentration of the arsenic dopants, the sub-threshold voltage of a subsequently formed gate is generated and the normal on-and-off of the device can not be operated. If a capacitor is to be fabricated according to the original dimension of the deep trench, and the problems related to the misalignment, when the active region is defined, are to be avoided, the overlay margin would become very small. In order to increase the overlay margin, one conventional approach is to reduce the dimension of the deep trench. However, the reduction of the deep trench would lead to the generation of the loading effect, which would limit the depth of the trench, and affect ultimately the capacity of the capacitor.

SUMMARY OF INVENTION

The present invention provides a fabrication method of a deep trench capacitor memory device, in which the overlay margin can be increased.

The present invention also provides a fabrication method for a memory device having a deep trench capacitor, wherein the dimension of the capacitor can be larger.

The present invention further provides a fabrication method of a memory device having a deep trench capacitor, in which a first conductive layer is formed in the bottom and the middle parts of the deep trench in the substrate. An undoped semiconductor layer is formed in the top part of the deep trench. A mask layer is then formed on the substrate, wherein the mask layer covers the undoped semiconductor layer at the border of the deep trench adjacent to the region for forming the active region. Thereafter, an ion implantation is conducted to implant dopants to the undoped semiconductor layer that is not covered by the mask layer and to form a second conductive layer. The second conductive layer and the first conductive layer together form the electrode of the capacitor.

In accordance to one aspect of the present invention, the aforementioned second conductive layer is sandwiched in between the undoped semiconductor layer. The undoped semiconductor layer thus serves as a buffer layer, which can prevent the dopants in the second conductive layer to diffuse directly to the substrate at the peripheral of the deep trench. As a result, during the subsequent definition of the active region, a larger overlay margin is provided. Therefore, even there are errors in alignment, the defined active region positioned at the peripheral of the deep trench is precluded from the sub-threshold voltage problem generated due to the diffusion of dopants as in the prior art.

Accordingly, the fabrication method of a memory device, wherein the overlay margin can be increased.

Further, since the present invention can provide a larger overlay margin, the reduction of the dimension of the capacitor is precluded.

DETAILED DESCRIPTION

The present invention can be better understood by way of the following example which is representative of a preferred embodiment but which is not to be construed as limiting the scope of the invention.

Referring toFIG. 1, a mask layer is formed on a substrate100, wherein the mask layer is, for example, a pad oxide layer102and a silicon nitride layer104that are formed sequentially on the substrate100. The pad oxide layer102is formed by, for example, a thermal oxidation method. The silicon nitride layer104is formed by, for example, a chemical vapor deposition method. The pad oxide layer102and the silicon nitride layer104are further patterned, and the substrate100is etched to form a plurality of deep trenches106in the substrate100. The arrangement of the deep trenches106is, for example, a division into a plurality of columns. As shown inFIG. 2, the deep trenches106aand the deep trenches106bbelong to different columns of deep trenches. For example, the deep trenches106abelong to an even column, while the deep trenches106bbelong to an odd row. The region between two neighboring deep trenches106that are further apart is preserved as the active region. The shape of the deep trench106basically appears to be rectangular when being viewed from the top, wherein the corners can be rounded to form approximately an oval shape. The short sides110and112of the deep trench106are essentially parallel to the direction where the neighboring active region122is extended along. The regions where the diffusion of dopants of the electrode to the periphery in the substrate as often occurs in the prior art the circled regions inFIG. 2, and these regions are depicted by the reference number108. The fabrication method of a deep trench capacitor of the present invention is intended to overcome the problems encountered in the prior art.

Still referring toFIG. 1, a doped region108is formed in the substrate100surrounding the bottom and the lower parts of the deep trench106. The doped region108is formed as the bottom electrode of a capacitor. Thereafter, a dielectric layer110is formed of the surfaces of the bottom and the lower surface of the deep trench108, followed by forming a first conductive layer112inside the trench106, encompassed by the dielectric layer110. The dielectric layer110and the conductive layer112are formed by, for example, forming a thin conformal dielectric layer and a conductive material that fills the trench106, for example, a silicon oxide layer and a doped polysilicon layer. Thereafter, chemical mechanical polishing is conducted to remove the conductive material layer that covers the silicon nitride layer104, followed by etching back a portion of the conductive material layer in the deep trench106to form the conductive layer112. Thereafter, the dielectric layer disposed above the silicon nitride layer104and on the upper and middle parts of the deep trench106are removed by dipping, leaving behind only the dielectric layer110at the periphery of the first conductive layer112. An annealing is then conductive to repair the first conductive layer112, wherein the oxide layer is formed on the sidewall surface of the middle part and the upper part of the deep trench106. The oxide layer becomes the oxide layer114after a subsequent dipping process.

Still referring toFIG. 1, a collar oxide layer116is then formed in the middle part of the deep trench106on the oxide layer114. A conductive layer118is formed inside the deep trench106, encompassed by the collar oxide layer116. Forming the collar oxide layer116and the conductive layer118is by, for example, forming a chemically vapor deposited collar oxide layer116on the oxide layer114. An etching-back process is then performed to remove the collar oxide layer that covers the surface of the conductive layer112, leaving behind only the oxide layer114and the collar oxide116on the sidewall of the deep trench106. Thereafter, a conductive material layer, for example, a doped polysilicon layer, is formed on the substrate100. Chemical mechanical polishing is then conducted to remove the conductive material layer on the surface of the silicon nitride layer104. An etching-back is further conducted, leaving behind the conductive layer118in the middle part of the deep trench106. After removing the oxide layer114and the collar oxide layer116after dipping, only the oxide layer114surrounding the second conductive layer118and the collar oxide layer116remain.

Referring toFIG. 3, an undoped semiconductor layer120is formed on the substrate100, wherein the undoped semiconductor layer120is, for example, an undoped polysilicon layer formed by a chemical vapor deposition method.

Continuing toFIG. 4, the undoped semiconductor layer120outside the deep trench106is removed, leaving behind a portion120aof the undoped semiconductor layer120in the upper part of the deep trench106. The undoped semiconductor layer120is removed by, for example, performing a chemical mechanical polishing process first to remove the undoped semiconductor layer120that covers the silicon nitride layer104, followed by an etching back process. Referring toFIG. 5, viewing from the top of the substrate100, the substrate is covered by the patterned silicon nitride layer104that has openings for the deep trenches106, and the semiconductor layer120that fills the deep trenches106.

Thereafter, as shown inFIG. 6, a patterned mask layer, for example a patterned photoresist layer126, is formed on the substrate100. Preferably, an anti-reflection layer124is formed before forming the patterned photoresist layer126.

Referring toFIG. 7, the anti-reflection layer124not covered by the photoresist layer126is removed, leaving behind the anti-reflection layer124a.An ion implantation process128is then conducted to implant dopants into the semiconductor layer120ato form the conductive layer120b,using the photoresist layer126and the silicon nitride layer104as an implantation mask.

Referring toFIG. 8, it is important to note that the photoresist layer126covers the region108of the deep trenches106, wherein the region108refers to the borders of the deep trenches that are adjacent to the predefined region for the active region122. Using the deep trench106aas an illustration, the borders of the deep trench106athat are adjacent to the edges of the active region122b,are regions108aand108bat the short side110and the short side112of the rectangular deep trench106a.In this aspect of the invention, the photoresist layer126is a long stripe, which covers the region between two neighboring columns of deep trenches106. More specifically, the region108bat the short side112of the deep trench106aand the region108aat the short side110of a neighboring deep trench106bare covered by the long, stripe-shaped photoresist layer126. When the ion implantation process128is conducted, the undoped semiconductor layer120ainside the deep trench106not covered by the photoresist layer126is going to be doped to form the conductive layer120b,whereas the undoped semiconductor layer120ainside the deep trench120acovered by the photoresist layer126is not going to be doped. The conductive layer120b,the conductive layer118and the conductive layer112serve as the upper electrode of the capacitor.

Referring to bothFIGS. 9 and 10, the photoresist layer126and the antireflection layer124are removed, and another mask layer130is formed on the substrate100to define the active region122. The mask layer130is, for example, a photoresist layer, which covers the predefined region for the active region122. In other words, the mask layer130covers a portion of the conductive the120binside the deep trenches106, and the silicon nitride layer104between two neighboring deep trenches106that are along a same column but at a further distance apart. Using the mask layer130as an etching mask, the silicon nitride layer104not covered by the mask layer130and the underlying pad oxide layer102and the substrate, and the undoped semiconductor layer120anot covered by the mask layer130and the conductive layer120bare etched to form shallow trenches131in the substrate100.

Referring toFIG. 11, an insulation layer132is formed over the substrate100to cover the silicon nitride layer104and to fill the shallow trenches131. The insulation layer is, for example, silicon oxide, and is formed by a method, such as, high density plasma chemical vapor deposition (HDPCVD).

Referring toFIG. 12, chemical mechanical polishing is then conducted to remove the insulation layer132that covers the silicon nitride layer104. An etching-back is conducted, the insulation layer132athat remains inside the shallow trench131forms the isolation structure. After the formation of the isolation structure132a,a plurality of active regions is defined on the substrate100.

Thereafter, referring to FIG.13andFIG. 14, the silicon nitride layer104and the pad oxide layer102are removed. A gate dielectric layer134is formed on the active region122, followed by forming a patterned gate conductive layer136. The gate conductive layer136is formed with a material, such as, doped polysilicon, by a method, for example, chemical vapor deposition. The gate conductive layer136extends along the row direction; in other words, the gate dielectric layer136is perpendicular to the direction at which the active region122is extended. The gate dielectric layer136crosses over two rows of gate conductive layer136. For each active region122, two rows of gate dielectric layer136are formed thereabove. Source/drain regions138,140are further formed in the active region122, followed by forming contact windows above the source/drain regions138/140. Therefore, back-end process is continued according to the conventional techniques, and the details of which not be reiterated here.

According to the aforementioned embodiment of the invention, a larger overlay margin is provided during the defining of the active region122. This is because, as shown inFIG. 10, the regions108of the conductive layer120bthat are adjacent to both edges of the neighboring active region122comprise the undoped semiconductor layer120a.The undoped semiconductor layer120athereby serves as a buffer layer, which can prevent the direct diffusion of dopants in the conductive layer120bto the periphery of the trenches160in the substrate100. Therefore, in the subsequent defining of the active region, even though a misalignment occurs and the active region122is defined on the border of the deep trenches106, the channel region of the defined active region122will not contain any arsenic dopants because the border of the deep trenches106is an undoped semiconductor layer120a.Therefore, the channel region of the defined active region122does not contain the arsenic dopants. As a result, the diffusion of dopants to periphery of the deep trenches, leading to the problem of the sub-threshold voltage as in the prior, is prevented. Beside the defined active region122comprises a larger overlay margin, the dimension of the capacitor can be increased. Further, the dimension of the capacitor is prevented from being reduced due to a small overlay margin. Therefore, the present invention is applicable for the fabrication of the next generation deep trench capacitor, and can accommodate the demand for miniaturization.