Control circuit for controlling a floating well bias voltage in a semiconductor integrated structure

A control circuit comprises a plurality of input terminals and an output terminal for biasing a floating well in a semiconductor integrated circuit structure. The control circuit also includes a first transistor which has its conduction terminals connected between a first input terminal and an output terminal, and a second transistor which has its conduction terminals connected between a second input terminal and the output terminal. The control circuit further includes a regulator coupling the output terminal to each of the control terminals of said first and second transistors.

FIELD OF THE INVENTION 
This invention relates to a control circuit for controlling the bias 
voltage of a floating well in a semiconductor integrated circuit 
structure. 
The invention relates, in particular but not exclusively, to a control 
circuit for controlling the bias voltage of a floating well, in order to 
form transistors for use in switching regulators, and the ensuing 
description will cover this specific field of application for convenience 
of illustration. 
BACKGROUND OF THE INVENTION 
As is known, there are many electrical applications wherein the value of a 
current flowing through an electric load needs to be regulated. 
In most cases, the current through the electric load has been regulated by 
a power transistor which may either be of the integrated or the discrete 
types. 
The power transistor, in turn, is driven by an integrated drive circuit 
commonly referred to as the high side driver. 
This power transistor is usually a MOS transistor having gate, source, and 
drain terminals. To charge the gate terminal of this transistor, a second 
voltage supply, higher than that to be applied to the drain terminal, must 
be made available. 
To produce this second voltage supply, a bootstrap capacitor is employed 
which can be re-charged during the conduction phase of a second power 
transistor, for example. This transistor is itself driven by means of an 
integrated drive circuit referred to as the low side driver. 
However, the supply voltage to the bootstrap capacitor must be high, if the 
efficiency of switching circuits is to be enhanced. Thus, the MOS power 
transistor is driven with gate-source voltages selected to have the 
smallest possible switch-on resistance RDSon. 
A possible construction of transistors using MOS technology is illustrated 
by FIG. 1. 
An epitaxial well II of the N type is grown over a substrate I of the P 
type. Body regions III of the P type and IV of the N type are then formed 
to respectively provide N-channel and P-channel transistors. 
For example, two regions of the N+ type are formed in the region BODY III 
of the P type to provide the source and drain regions of an N-channel 
transistor. The source region and the body region III are conventionally 
connected together by a common terminal HSRC. 
By using a conventional process of manufacturing structures such as that 
shown in FIG. 1, e.g., with BCDIII technology, the operation of MOS 
transistors at relatively high working voltages can be ensured. In 
particular, for circuits employing voltage bootstrap structures, working 
voltages may be provided whose values equal the voltage drop across the 
bootstrap capacitor. However, as the bootstrap voltage is increased, a 
bias voltage of the epitaxial well II cannot be ensured to equal the 
working voltage, because the breakdown voltage of the junction created 
between this well II and the regions III of the P type is smaller than the 
voltage drop across the bootstrap capacitor. 
SUMMARY OF THE INVENTION 
An embodiment of this invention is directed to a control circuit for 
controlling the bias voltage of a floating well, which circuit has 
structural and functional features such that relatively high bias voltages 
can be used, and a breakdown of the junction created between the floating 
well and strongly biased regions effectively prevented, thereby overcoming 
the limitations and/or drawbacks with which prior art devices are beset. 
The control circuit for the bias voltage of the floating well during 
operation of switching regulators such that the well voltage becomes 
variable proportionally to the voltages of contiguous regions, instead of 
being a fixed voltage. 
The control circuit includes a plurality of input terminals; an output 
terminal for biasing a floating well in a semiconductor integrated circuit 
structure; a first transistor having its conduction terminals connected 
between a first input terminal and the output terminal, a second 
transistor having its conduction terminals connected between a second 
input terminal and the output terminal; and a regulator coupling the 
output terminal to each of the control terminals of the first and second 
transistors. In one embodiment, the regulator is a Zener diode. 
The features and advantages of a device according to the invention will be 
apparent from the following description of an embodiment thereof, given by 
way of non-limitative example with reference to the accompanying drawings.

DETAILED DESCRIPTION 
Referring to the drawing figures, generally shown at 6 is a control circuit 
according to an embodiment of the invention. 
The circuit 6 includes two input terminals HSTRAP and HSRC, and an output 
terminal POLEPI. 
An N-channel first transistor NCH1 has a first conduction terminal 1 
connected to the terminal HSTRAP, a second conduction terminal 2 connected 
to the terminal POLEPI, and a control terminal 3. 
A P-channel second transistor PCH1 has a first conduction terminal 10 
connected to the input terminal HSCR, a second conduction terminal 2 
connected to the output terminal POLEPI, and a control terminal 30 
connected to the control terminal 3 of the transistor NCH1 at a node G. 
Advantageously, the body terminals of said transistors are connected to 
their respective second conduction terminals. 
The control terminals 3, 30 of the two transistors NCH1, PCH1 are connected 
to a common node G. The terminal HSCR controls the voltage at the node G 
by means of a regulator Dz. This regulator may be a reverse biased Zener 
diode D.sub.Z. However, the regulator could be obtained in an another way 
known to the skilled ones in the art. 
Advantageously, a capacitor C.sub.Z is connected in parallel with the diode 
Dz. 
The bias for the diode Dz may be provided by a first current mirror 4 
connected between the terminal HSTRAP and the node G. 
The mirror 4 comprises first M1 and second M2 mirror transistors which are 
both of the PMOS type in the example considered. 
The first mirror transistor M1 has its respective source and drain 
conduction terminals connected to the terminal HSTRAP and the node G, and 
has a control terminal connected to the control terminal of the second 
mirror transistor M2, which is diode-connected and has its drain terminal 
connected to the ground GND through a second current mirror 5. 
The second current mirror 5 comprises a pair of mirror transistors M3 and 
M4 of the NMOS type having their respective control terminals connected 
together. The transistor M3 is diode-connected. 
The control terminal of the transistor M3 is connected by a capacitor C1 to 
ground. 
As the skilled ones in art know well, the Zener diode Dz could also be 
biased in other ways. 
Shown in FIG. 3 is an integrated circuit 7 which includes an output stage 
of switching regulators with power transistors, and incorporates a 
conventional bootstrap capacitor. This capacitor could be external of the 
integrated circuit 7. 
The control circuit 6 of FIG. 2 may be associated to advantage with the 
integrated circuit 7. 
In this integrated circuit 7, a first power transistor T1 operates as a 
switch and has a first conduction terminal connected to a voltage Vin, and 
has a second conduction terminal connected to the node HSTRAP and to a 
ground reference through a second power transistor T2. 
The control terminal of the first transistor T1 is connected to the output 
of a first drive circuit Driver Hside. The control terminal of the second 
transistor T2 is connected to the output of a second drive circuit Driver 
Lside. 
A bootstrap capacitor Cboot is connected between the terminals HSTRAP and 
HSRC of the drive circuit Driver Hside, and is powered from a voltage 
generator Vdriver having a diode Dboot in series therewith. 
The control circuit 6 of FIG. 2 is connected to the terminals HSTRAP and 
HSRC. 
FIG. 1 shows a portion of a semiconductor device wherein the input terminal 
HSCR is connected to the body region III of the P type, and the output 
terminal POLEPI is connected to the epitaxial well II. 
A diode Cepi-sub represents the junction between an epitaxial well II and 
the substrate I where the integrated circuit is formed. 
The operation of the control circuit of FIG. 2 will now be described. 
With the transistor T1 in the off state and the transistor T2 in the on 
state, the bootstrap capacitor Cboot is charged, and the terminal HSTRAP 
is at the drive voltage of the drivers, so that: 
EQU V.sub.HSTRAP =Vdriver-Vbe 
where, Vbe is the voltage drop across the diode Dboot. The voltage 
V.sub.HSRC at the terminal HSRC is substantially equal to zero (negligible 
voltage drop across transistor T2. 
When the transistor T1 is turned on, and the transistor T2 turned off, the 
terminal HSRC goes to a voltage value V.sub.HSRC =Vin, and the terminal 
HSTRAP to a voltage value given as V.sub.HSTRAP =Vin+Vdriver-Vbe. 
This rising edge of the signal Vin applied to the terminal HSRC is sensed 
by the Zener diode Dz, which will cause the transistor NCH1 to conduct. 
The terminal POLEPI will then attain a voltage value given as: 
EQU V.sub.EPI =V.sub.zener -V.sub.gs(NCH1) +V.sub.HSRC. 
Advantageously, the capacitor Cz provided holds the voltage constant across 
the Zener diode Dz. 
When the transistor T1 is turned off, and the transistor T2 turned on, the 
terminals HSRC and HSTRAP attain respectively V.sub.HSRC =0 and 
V.sub.HSTRAP =Vdriver-Vbe. In this condition, the transistor NCH1 is 
turned off and the transistor PCH1 turned on. Thus, the voltage at the 
terminal POLEPI is controlled to a value given by: 
EQU V.sub.EPI =V.sub.zener -V.sub.gs(PCH1). 
Shown schematically in FIG. 4a is a voltage vs. time plot of the voltages 
V.sub.HSTRAP, V.sub.HSRC, and V.sub.EPI, on a common time base. 
This first plot brings out the fact that the voltage V.sub.EPI follows the 
patterns of the voltages V.sub.HSTRAP, V.sub.HSRC. 
FIG. 4b shows a plot illustrating the difference between the epitaxial well 
voltage (V.sub.EPI) and that of the BODY regions (V.sub.BODY) where the 
N-channel transistors of the integrated circuit 7, the drive circuit 
Driver Hside, and the circuit 6 of FIG. 2, and the transistor T1 are all 
formed. 
The use of the control circuit 6 ensures that the voltage across the 
epitaxial well and the BODY regions will not exceed the breakdown voltage 
of the resulting junction. 
To summarise, the control circuit 6 affords control of the bias voltage of 
a floating well as an input voltage varies. 
From the foregoing it will be appreciated that, although specific 
embodiments of the invention have been described herein for purposes of 
illustration, various modifications may be made without deviating from the 
spirit and scope of the invention. Accordingly, the invention is not 
limited except as by the appended claims.