Semiconductor device and method of manufacturing the same

A conventional semiconductor device, for example, a lateral PNP transistor has a problem that it is difficult to obtain a desired current-amplification factor while maintaining a breakdown voltage characteristic without increasing the device size. In a semiconductor device, that is a lateral PNP transistor, according to the present invention, an N type epitaxial layer is formed on a P type single crystal silicon substrate. The epitaxial layer is used as a base region. Moreover, molybdenum (Mo) is diffused in the substrate and the epitaxial layer. With this structure, the base current is adjusted, and thereby a desired current-amplification factor (hFE) of the lateral PNP transistor is achieved.

Priority is claimed to Japanese Patent Application Number JP2006-206967 filed on Jul. 28, 2006, the disclosure of which is incorporated herein by reference in its entirety.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a semiconductor device in which a characteristic of a lateral PNP transistor is improved, and to a method of manufacturing the semiconductor device.

2. Description of the Related Art

As an example of a conventional semiconductor device, a following lateral PNP transistor has been known. In the lateral PNP transistor, an N type epitaxial region of a low impurity concentration is formed on a P type semiconductor substrate. An N type impurity buried region is formed so as to extend in the P type semiconductor substrate and the N type epitaxial region. A first N type impurity region is formed in the epitaxial region. The impurity concentration of the first N type impurity region is two to three times higher than that of the N type epitaxial region. Moreover, a second N type impurity region as a base region, a first P type impurity region as an emitter region, a second P type impurity region as a collector region are formed in the first N type impurity region. This technology is described, for instance, in Japanese Patent Application Publication No. Hei 5 (1993)-144830 (Page 2, and FIG. 1).

As another example of the conventional semiconductor device, a following lateral PNP transistor has been known. In the lateral PNP transistor, an N type epitaxial layer is formed on a P type semiconductor substrate. An N type buried diffusion layer is formed so as to extend in the P type semiconductor substrate and the N type epitaxial layer. An N type diffusion layer as a base region, a P type diffusion layer as an emitter region, and a P type diffusion layer as a collector region are formed in the N type epitaxial layer. The P type diffusion layer as the collector region is circularly formed around the P type diffusion layer as the emitter region. This technology is described, for instance, in Japanese Patent Application Publication No. 2004-95781 (Pages 4-5, and FIG. 1).

As an example of a conventional method of manufacturing a semiconductor device, the following method of manufacturing an NPN transistor has been known. Firstly, an N type single crystal silicon substrate is prepared, and a thermal oxide film is formed on the substrate. The thermal oxide film is patterned, and an opening is accordingly formed in the thermal oxide film on a region where a P type diffusion layer is to be formed. Then, a liquid source containing both boron (B) and platinum (Pt) which serves as a lifetime killer substance is applied to the substrate to form a diffusion-source film. Subsequently, the boron (B) and platinum (Pt) are diffused from the diffusion-source film into the substrate by heat treatment at 1000° C. to 1050° C. in a non-oxidation atmosphere. This technology is described, for instance, in Japanese Patent Application Publication No. Hei 2 (1990)-135737 (Pages 2-3, and FIG. 1).

As another example of the conventional method of manufacturing a semiconductor device, the following method of manufacturing a transistor has been known. Firstly, in a semiconductor substrate as a collector, a diffusion layer as a base region, and a diffusion layer as an emitter region are formed. Then, a silicon oxide film is formed on the substrate, and an opening is formed in the silicon oxide film on a region where a diode is to be formed. Subsequently, a liquid source containing platinum (Pt) as a lifetime killer substance is applied to the substrate to form a diffusion-source film. Thereafter, the platinum (Pt) is diffused from the diffusion-source film into the substrate by heat treatment at 800° C. to 1000° C. in a non-oxidation atmosphere. This technology is described, for instance, in Japanese Patent Application Publication No. Hei 4 (1992)-85934 (Page 3, and FIG. 1).

As described above, in the conventional semiconductor device, the first N type impurity region as the base region is formed in the N type epitaxial region. The concentration of the first N type impurity region is two to three times higher than that of the N type epitaxial region. With this structure of the lateral PNP transistor, the concentration of the base region is affected by the concentration of the N type impurity region, and thus the current-amplification factor of the lateral PNP transistor is stabilized. Nevertheless, the first N type impurity region used as the base region has a high impurity concentration, resulting in a problem that the breakdown voltage characteristic of the lateral PNP transistor is deteriorated.

Moreover, in the conventional semiconductor device, the P type diffusion layer as the collector region is circularly formed around the P type diffusion layer as the emitter region in the N type epitaxial layer. This structure makes it possible to efficiently place the P type diffusion layer as the collector region in relation to the P type diffusion layer as the emitter region. Specifically, by reducing the width of the base region (separation distance between the emitter and collector regions), the current-amplification factor of the lateral PNP transistor can be increased. In contrast, when the value of the current-amplification factor of the lateral PNP transistor becomes too high by using the N type epitaxial layer of the low impurity concentration as the base region, it is possible to manage the situation by increasing the width of the base region (separation distance between the emitter and collector regions). In this case, there is a problem that the device size of the lateral PNP transistor becomes too large.

Furthermore, in the conventional method of manufacturing a semiconductor device, the liquid source containing platinum (Pt) as the lifetime killer substance is applied to the substrate to form the diffusion-source film. Thereafter, the platinum (Pt) is diffused from the diffusion-source film into the substrate by heat treatment in the non-oxidation atmosphere. At this time, there is a problem that the use of the platinum (Pt) results in an increase in the specific resistance of the region where the N type impurities are diffused.

SUMMARY OF THE INVENTION

The present invention is made in consideration of the above-described circumstances. A semiconductor device according to the present invention includes a semiconductor layer, and an emitter region, a base region, and a collector region, which are formed in the semiconductor layer. The semiconductor device includes that molybdenum (Mo) is diffused in the semiconductor layer used as the base region. Accordingly, in the present invention, the base current is adjusted by the molybdenum (Mo) diffused in the semiconductor layer, and thereby a desired current-amplification factor is achieved without increasing the device size.

Moreover, a method of manufacturing a semiconductor device according to the present invention includes the steps of forming an insulating layer on a semiconductor layer, and forming an opening in the insulating layer on at least a region where any one of an emitter region and a collector region is to be formed, washing the surface of the semiconductor layer so that the surface exposed to the opening can be hydrophilic, and thereafter applying, to the surface, a solution containing molybdenum (Mo) to be diffused into the semiconductor layer, and applying, to the semiconductor layer, a liquid source containing impurities to form any one of the emitter region and the collector region, and thereafter thermally diffusing the molybdenum (Mo) and the impurities into the semiconductor layer. Accordingly, in the present invention, the molybdenum (Mo) is diffused into the semiconductor layer in the common step of forming at least any one of the emitter region and the collector region. This manufacturing method makes it possible to reduce the variation in the current-amplification factor caused by metallic contamination in a manufacturing line for the semiconductor device.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Hereinafter, description will be given in detail of a semiconductor device according to a preferred embodiment of the present invention with reference toFIG. 1andFIG. 2.FIG. 1is a cross-sectional view for describing the semiconductor device according to this preferred embodiment.FIG. 2is a table for describing the current-amplification factor (hFE) of the semiconductor device according to this preferred embodiment.

As shown inFIG. 1, a lateral PNP transistor1mainly includes a P type single crystal silicon substrate3, an N type epitaxial layer4used as a base region, an N type buried diffusion layer5, an N type diffusion layer6used as a base leading region, a P type diffusion layer7used as an emitter region, and P type diffusion layers8and9used as collector regions.

The N type epitaxial layer4is formed on the P type single crystal silicon substrate3. Note that, although only one epitaxial layer4is formed on the substrate3in this embodiment, the preferred embodiment of the present invention is not limited to this case. For example, the preferred embodiment of the present invention may include only the substrate with no epitaxial layer thereon, or a plurality of epitaxial layers can be stacked on the substrate. Alternatively, the substrate may be an N type single crystal silicon substrate.

The N type buried diffusion layer5is formed so as to extend in both regions of the substrate3and the epitaxial layer4. The N type buried diffusion layer5is formed across a region where the lateral PNP transistor1is formed.

The N type diffusion layer6is formed in the epitaxial layer4. The N type epitaxial layer4is used as the base region. The N type diffusion layer6is used as the base leading region.

The P type diffusion layer7is formed in the epitaxial layer4, and used as the emitter region.

The P type diffusion layers8and9are formed in the epitaxial layer4, and used as the collector regions. Incidentally, the P type diffusion layers8and9can be circularly formed around the P type diffusion layer7.

An insulating layer10is formed over the epitaxial layer4. The insulating layer10is formed of a PSG (Phospho Silicate Glass) film or the like. In addition, by means of a known photolithography technique, contact holes11,12,13and14are formed in the insulating layer10by dry etching using CHF3+O2gas, for example.

In each of the contact holes11,12,13and14, an aluminum alloy film such as an Al—Si film is selectively formed, so that collector electrodes15and17, an emitter electrode16, and a base electrode18are formed respectively in the contact holes11,13,12and14.

On the other hand, an NPN transistor2mainly includes, the P type single crystal silicon substrate3, the N type epitaxial layer4, an N type buried diffusion layer19used as a collector region, an N type diffusion layer20used as a collector region, a P type diffusion layer21used as a base region, and an N type diffusion layer22used as an emitter region.

The N type epitaxial layer4is formed on the P type single crystal silicon substrate3.

The N type buried diffusion layer19is formed so as to extend in both regions of the substrate3and the epitaxial layer4.

The N type diffusion layer20is formed in the N type epitaxial layer4. The N type diffusion layer20is connected to the N type buried diffusion layer19, and used as the collector region. The N type epitaxial layer20and the N type buried diffusion layer19are formed so as to be connected to each other.

The P type diffusion layer21is formed in the N type epitaxial layer4, and used as the base region.

The N type diffusion layer22is formed as overlapped with the P type diffusion layer21.

The insulating layer10is formed over the epitaxial layer4. In addition, by means of the known photolithography technique, contact holes23,24and25are formed in the insulating layer10by dry etching using CHF3+O2gas, for example.

In each of the contact holes23,24and25, an aluminum alloy film such as an Al—Si film is selectively formed, so that an emitter electrode26, a base electrode27, and a collector electrode28are formed respectively in the contact holes23,24and25.

Although the specifics will be explained in the description of a method of manufacturing a semiconductor device later, molybdenum (Mo) is diffused in the substrate3and the epitaxial layer4used as the base region of the lateral PNP transistor1. In the lateral PNP transistor1, holes are injected from the P type diffusion layer7as the emitter region to the epitaxial layer4as the base region. Then, the holes flow into the P type diffusion layers8and9as the collector regions via the vicinity of the surface of the epitaxial layer4where the base width (Wb) is the narrowest. At this time, the hole is a minor carrier in the N type epitaxial layer4, and easy to recombine with electrons because of the molybdenum (Mo) in the epitaxial layer4. In other words, the lifetime of the hole is reduced by the accelerating effect on the recombination of the molybdenum (Mo). Thereby, the current-amplification factor (hFE) of the lateral PNP transistor1is reduced.

Specifically, as shown inFIG. 2, the current-amplification factor (hFE) of the lateral PNP transistor1is reduced in accordance with the diffusion amount of the molybdenum (Mo) in the epitaxial layer4. Note that,FIG. 2shows the mean value (X) of the current-amplification factor (hFE) in a case where the emitter current (Ie) in the lateral PNP transistor1is 10 μA.

As shown inFIG. 2, in a case where molybdenum (Mo) is not diffused into the lateral PNP transistor1, the mean value (X) of the current-amplification factor (hFE) of the lateral PNP transistor1is 273. In the meanwhile, in a case where the molybdenum (Mo) solution in a concentration of 0.1 ppm is used (refer to the description ofFIG. 7), the mean value (X) is 236. In addition, in a case of 1.0 ppm, the mean value (X) is 201. Moreover, in a case of 10.0 ppm, the mean value (X) is 188. Furthermore, in a case of 100.0 ppm, the mean value (X) is 151. More specifically, as the diffusion amount of the molybdenum (Mo) in the epitaxial layer4is increased, the current-amplification factor (hFE) of the lateral PNP transistor1is reduced.

Note that, although various semiconductor elements are formed on the substrate3, the molybdenum (Mo) does not influence the characteristics of the other semiconductor elements. Thereby, the concentration of the molybdenum solution can be determined in accordance with the current-amplification factor (hFE) characteristic of the lateral PNP transistor1. Particularly, even when molybdenum is diffused into the substrate3and the epitaxial layer4, no increase is observed in the specific resistance, or in the on-resistance of the lateral PNP transistor1and the other semiconductor elements either.

Furthermore, as shown inFIG. 2, the coefficient of variation (σ/X) of the current-amplification factor (hFE) of the lateral PNP transistor1is reduced in accordance with the diffusion amount of molybdenum (Mo) in the epitaxial layer4. Note that,FIG. 2shows the mean value (X) and the standard deviation (σ) of the current-amplification factor (hFE) in a case where the emitter current (Ie) in the lateral PNP transistor1is 10 μA.

As shown inFIG. 2, in a case where molybdenum (Mo) is not diffused into the epitaxial layer4, the standard deviation (σ) of the current-amplification factor (hFE) of the lateral PNP transistor1is 38.0, and the coefficient of variation (σ/X) is 14%. In the meanwhile, in a case where the molybdenum (Mo) solution in a concentration of 0.1 ppm is used (refer to the description ofFIG. 7), the standard deviation (σ) is 13.0, and the coefficient of variation (σ/X) is 6%. In addition, in a case of 1.0 ppm, the standard deviation (ν) is 11.0, and the coefficient of variation (σ/X) is 6%. Moreover, in a case of 10.0 ppm, the standard deviation (σ) is 5.9, and the coefficient of variation (σ/X) is 3%. Furthermore, in a case of 100.0 ppm, the standard deviation (σ) is 8.0, and the coefficient of variation (σ/X) is 5%. More specifically, it is possible to avoid the adverse influence from the metallic contamination in a manufacturing line for the semiconductor device by diffusing a certain amount of molybdenum (Mo) into the epitaxial layer4. This is because the molybdenum (Mo) is diffused into the epitaxial layer4more than the amount of the metallic contamination in the manufacturing line, and thereby the variation in the current-amplification factor (hFE) of the lateral PNP transistor1is reduced.

As described above, in the lateral PNP transistor1, by utilizing the accelerating effect on the recombination with the molybdenum (Mo), the lifetime of the hole is reduced, and the current-amplification factor (hFE) is reduced. Thereby, a desired current-amplification factor (hFE) is obtained. At this time, since the impurity concentration of the N type epitaxial layer4is not set high, it is possible to prevent the breakdown voltage characteristic of the lateral PNP transistor1from deteriorating. Furthermore, by reducing the current-amplification factor (hFE) without increasing the base width (separation distance between the emitter and collector regions) of the lateral PNP transistor1, it is also possible to prevent the device size of the lateral PNP transistor1from increasing.

Next, description will be given in detail of a method of manufacturing a semiconductor device according to another preferred embodiment of the present invention with reference toFIGS. 3 to 8.FIGS. 3 to 8are cross-sectional views for describing the method of manufacturing the semiconductor device shown inFIG. 1according to this preferred embodiment.

Firstly, as shown inFIG. 3, a P type single crystal silicon substrate3is prepared. The surface of the substrate3is thermally oxidized to form a silicon oxide film31thereon. Then, the silicon oxide film31is selectively removed, so that openings are formed on regions where N type buried diffusion layers5and19are to be formed. Subsequently, by using the silicon oxide film31as a mask, a liquid source32containing an N type impurity, for example, antimony (Sb) is applied to the surface of the substrate3by means of a spin-coating method. Thereafter, the antimony (Sb) is thermally diffused, so that the N type buried diffusion layers5and19are formed. After that, the silicon oxide film31and the liquid source32are removed.

Next, as shown inFIG. 4, a silicon oxide film33is deposited to a thickness of, for example, 100 Å to 450 Å on the substrate3. Then, a photoresist34is formed on the silicon oxide film33. Thereafter, by means of a known photolithography technique, openings are formed in the photoresist34on regions where P type buried diffusion layers35to37are to be formed. Subsequently, ions of a P type impurity, for example, boron (B) are implanted from the surface of the substrate3at an accelerating voltage of 90 to 180 (keV) and a dose of 0.5×1014to 1.0×1016(/cm2). After that, the photoresist34is removed, and then the P type buried diffusion layers35to37are formed by thermal diffusion.

Next, as shown inFIG. 5, the substrate3is placed on a susceptor of a vapor phase epitaxial growth apparatus so as to form an epitaxial layer4on the substrate3. The vapor phase epitaxial growth apparatus mainly includes a gas supply system, a reactor, an exhaust system, and a control system. In this embodiment, by use of a vertical reactor, the thickness uniformity of the epitaxial layer can be improved. The N type impurities in the N type buried diffusion layers5and19as well as the P type impurities in the P type buried diffusion layers35to37are thermally diffused by heat treatment in the process of forming the epitaxial layer4.

Next, a silicon oxide film38is deposited to a thickness of, for example, 100 Å to 450 Å on the epitaxial layer4. Then, a photoresist39is formed on the silicon oxide film38. Thereafter, by means of the known photolithography technique, openings are formed in the photoresist39on regions where P type diffusion layers40to42are to be formed. Subsequently, ions of a P type impurity, for example, boron (B) are implanted from the surface of the epitaxial layer4at an accelerating voltage of 90 to 180 (keV) and a dose of 0.5×1014to 1.0×1016(/cm2). After that, the photoresist39is removed, and then the P type diffusion layers40to42are formed.

Next, as shown inFIG. 6, a photoresist43is formed on the silicon oxide film38. Thereafter, by means of the known photolithography technique, opening is formed in the photoresist43on regions where an N type diffusion layer20is to be formed. Subsequently, by using the photoresist43as a mask, ions of an N type impurity, for example, phosphorus (P) are implanted from the surface of the epitaxial layer4at an accelerating voltage of 90 to 110 (keV) and a dose of 1.0×1013to 1.0×1015(/cm2). After that, the silicon oxide film38and the photoresist43are removed, and then the N type diffusion layer20is formed by thermally diffusing the phosphorus.

Next, as shown inFIG. 7, the surface of the epitaxial layer4is thermally oxidized to form a silicon oxide film44thereon. The silicon oxide film44is selectively removed, so that openings are formed on regions where P type diffusion layers7,8,9and21are to be formed. Subsequently, by washing an unillustrated wafer on which the epitaxial layer4is formed, the regions of the surface of the epitaxial layer4exposed to the openings in the silicon oxide film44are made hydrophilic.

Thereafter, approximately 10 ml of a molybdenum (Mo)-containing solution (solution made by dissolving molybdenum trioxide in ammonium water) is applied to the surface of the epitaxial layer4by means of the spin-coating method. Then, the surface of the wafer is dried by rotating the wafer. Subsequently, a liquid source45containing a P type impurity, for example, boron (B) is applied to the surface of the epitaxial layer4by means of the spin-coating method. Thereafter, the molybdenum (Mo) and the boron (B) are thermally diffused simultaneously, so that P type diffusion layers7,8,9and21are formed. At this time, the molybdenum (Mo) is diffused into the substrate3and the epitaxial layer4simultaneously. After that, the silicon oxide film44and the liquid source45are removed. Note that, it is only necessary that the molybdenum (Mo) be diffused into at least the epitaxial layer4.

Next, as shown inFIG. 8, by means of the known photolithography technique, N type diffusion layers6and22are formed by a desired forming method. Then, a PSG film or the like is deposited as an insulating layer10over the epitaxial layer4. Subsequently, by means of the known photolithography technique, contact holes11,12,13,14,23,24and25are formed in the insulating layer10by dry etching using CHF3+O2gas, for example. In each of the contact holes11,12,13,14,23,24and25, an aluminum alloy film such as an Al—Si film is selectively formed, so that collector electrodes15,17and28and emitter electrodes16and26as well as base electrodes18and27are formed respectively in the contact holes11,13,25,12,23,14and24.

Note that, in this embodiment, description has been given of the case where the molybdenum (Mo) is diffused into the substrate3and the epitaxial layer4in the common step of forming the P type diffusion layers7,8,9and21. However, the preferred embodiment of the present invention is not limited to this case. For example, the molybdenum (Mo) can be diffused into the substrate3and the epitaxial layer4in a common step of forming a P type diffusion layer for an isolation region in the epitaxial layer4. Additionally, in this embodiment, description has been given of the case where the solution containing the molybdenum (Mo) is applied by the spin-coating method. However, the preferred embodiment of the present invention is not limited to this case. The molybdenum (Mo) may be diffused into the substrate3and the epitaxial layer4by means of, for example, an ion implantation method, a method to immerse the wafer into the solution containing molybdenum (Mo), or a method to make the liquid source45containing boron (B) include a molybdenum (Mo) compound, and to diffuse the molybdenum (Mo) together with the boron (B). Moreover, various modifications are possible to be made on the preferred embodiment of the present invention without departing from the spirit of the present invention.

The molybdenum (Mo) is diffused into the base region of the lateral PNP transistor according to the preferred embodiment of the present invention. With the structure, holes injected from the emitter and electrons which are majority carriers in the base region are recombined with each other via the deep level of molybdenum (Mo), and thereby a desired current-amplification factor (hFE) of the lateral PNP transistor is achieved.

Moreover, according to the preferred embodiment of the present invention, the holes injected from the emitter and the electrons which are the majority carriers in the base region are recombined with each other via the deep level of molybdenum (Mo), and thereby a desired current-amplification factor (hFE) of the lateral PNP transistor is achieved. Thus, it is possible to prevent the device size of the lateral PNP transistor from increasing.

Furthermore, according to the preferred embodiment of the present invention, the holes injected from the emitter and the electrons which are the majority carriers in the base region are recombined with each other via the deep level of molybdenum (Mo), and thereby a desired current-amplification factor (hFE) of the lateral PNP transistor is achieved. Accordingly, the diffusion of the molybdenum (Mo) makes possible to reduce the variation in the current-amplification factor (hFE) caused by metallic contamination in a manufacturing line for the semiconductor device.