Flip-chip assembly comprising an array of vertical cavity surface emitting lasers (VCSELSs), and an optical transmitter assembly that incorporates the flip-chip assembly

A plurality of flip-chips, each having a plurality of optoelectronic elements formed therein, are flip-chip mounted on a top surface of a substrate that is comprised of a material that is transparent to the operating wavelength of the light produced by optoelectronic elements of the flip-chips. The combination of flip-chips comprises an array of precisely-aligned optoelectronic elements. When the substrate comprising the array of optoelectronic elements is mounted on a PCB, electrical contact pads disposed on the bottom and/or top surface of the substrate are in contact with the respective electrical contact pads disposed on the top surface of the PCB to electrically interconnect the PCB with the flip-chips. Mating features on the substrate that have been precisely positioned by semiconductor fabrication steps are disposed for mating with respective mating features of a multi-optical fiber ferrule device that have been precisely formed in the ferrule device at precise locations.

TECHNICAL FIELD OF THE INVENTION

The invention relates to semiconductor lasers, and more particularly, to a flip-chip assembly comprising an array of vertical cavity surface emitting lasers (VCSELs).

BACKGROUND OF THE INVENTION

In optical communications networks, optical transceiver and transmitter modules are used to transmit optical signals over optical fibers. The optical transceiver or transmitter module includes a laser that generates amplitude modulated optical signals that represent data, which are then transmitted over an optical fiber coupled to the transceiver or transmitter module. Various types of semiconductor lasers are typically used for this purpose, including, for example, VCSELs and edge emitting lasers, which may be further divided into subtypes that include Fabry Perot (FP) and Distributed Feedback (DFB) lasers.

Some optical transmitter or transceiver modules have only a single transmit channel comprising a single laser, which is sometimes referred to as a singlet. Other optical transmitter or transceiver modules have multiple transmit channels comprising multiple lasers. The multi-channel optical transmitter or transceiver module is commonly referred to as a parallel optical transmitter or transceiver module.

There is an ever-increasing demand for optical transmitter or transceiver modules that have increasingly larger numbers of transmit channels. Of course, increasing the number of transmit channels allows the bandwidth capacity of an optical communications network to be increased. In order to meet this demand, it is known to fabricate an array of lasers on a single semiconductor substrate of the electrical subassembly (ESA) of the module. For example, it is known to fabricate a one-dimensional or two-dimensional array of VCSELs on a single semiconductor substrate. Fabricating the VCSELs on a single semiconductor substrate allows the spacing, or pitch, between adjacent VCSELs to be decreased, which, in turn, allows the number of VCSELs that can be integrated on a single semiconductor substrate to be increased. However, the manufacturing yield for this type of semiconductor device is relatively low due to the fact that the semiconductor device is deemed defective and is discarded if even one of the VCSELs of the array is found to be defective. The relatively low manufacturing yield of this type of semiconductor device increases the overall costs of the semiconductor devices.

Because semiconductor devices that have fewer numbers of VCSELs on them can be manufactured with higher yield, and thus at reduced costs, it is known to construct an array of VCSELs by creating an array of multiple semiconductor devices that have either only a singlet VCSEL or a few VCSELs on them. This approach presents other difficulties, however, one of which is the difficulty associated with precisely aligning the VCSELs with their respective optical coupling elements. Consequently, to date, using multiple semiconductor devices having only either a singlet VCSEL or a very small number of VCSELs on them to create a larger array of VCSELs is not a viable solution.

Accordingly, a need exists for an assembly having multiple semiconductor devices with only either a singlet or a very small number of VCSELs on them that can be combined to create a precisely-aligned larger array of VCSELs.

SUMMARY OF THE INVENTION

The present invention is directed to a flip-chip assembly, and to an optical communications module that incorporates the flip-chip assembly. The flip-chip assembly comprises a substrate, at least a first set of electrically-conductive contact pads disposed on the substrate, at least a first set of electrically-conductive traces disposed on the substrate, and a plurality of flip-chips that are flip-chip-mounted in respective flip-chip mounting areas of the top surface of the substrate. The substrate is transparent to a particular wavelength of light and has top and bottom surfaces. The bottom surface of the substrate has a plurality of mating features disposed thereon at precise locations on the bottom surface of the substrate. Each mating feature is sized and shaped to mate with a respective mating feature of a multi-optical fiber ferrule device. The traces have first and second ends. The first ends of the traces are connected to respective contact pads of the first set of electrically-conductive contact pads. Each flip-chip includes a plurality of electrically-conductive contact pads that are connected to second ends of respective traces of the first set of traces. The mating of the mating features disposed on the bottom surface of the substrate with the respective mating features of the ferrule device precisely aligns the optoelectronic elements of the flip-chips with ends of respective ferrules of the ferrule device.

The optical communications module comprises the flip-chip assembly, a circuit board, and a multi-optical fiber ferrule device. The substrate is mounted on the circuit board such that the mating features disposed on the bottom surface of the substrate are exposed to mate with the mating features of the ferrule device. The multi-optical fiber ferrule device has a front side and a back side and N ferrules formed therein. The front side has the mating features thereon at particular locations that are shaped and sized to mate with the respective mating features disposed on the bottom surface of the substrate. The mating features of the ferrule device are fully mated with the respective mating features of the substrate, and the full mating of the respective mating features brings the ferrules of the ferrule device into precise alignment with respective optoelectronic elements of the flip-chips.

These and other features and advantages of the invention will become apparent from the following description, drawings and claims.

DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS

In accordance with illustrative embodiments described herein, a plurality of flip-chips are flip-chip mounted on a top surface of a substrate that is comprised of a material that is transparent to the operating wavelength of the light produced by optoelectronic elements of the flip-chips. Each flip-chip has a plurality of optoelectronic elements formed therein such that the combination of flip-chips mounted on the substrate comprises an array of precisely-aligned optoelectronic elements. When the substrate comprising the array of optoelectronic elements is mounted on the PCB, electrical contact pads disposed on the bottom and/or top surface of the substrate are in contact with the respective electrical contact pads disposed on the top surface of the PCB to electrically interconnect the PCB with the flip-chips. Mating features on the substrate that have been precisely positioned by semiconductor fabrication steps are disposed for mating with respective mating features of a multi-optical fiber ferrule device that have been precisely formed in the ferrule device at precise locations. When the mating features on the substrate fully engage the respective mating features of the ferrule device, the optoelectronic elements of the array are brought into precise, fine alignment with respective ferrules formed in the ferrule device.

First ends of a plurality of optical fibers are held within respective ferrules of the ferrule device. The precision mating of the ferrule device with the substrate ensures that the ferrules of the ferrule device are precisely aligned with the respective optoelectronic elements of the flip-chips, which ensures that the first ends of the fibers are precisely aligned with the respective optoelectronic elements. Second ends of the optical fibers may be secured to one or more optical connectors, which may be pluggable connectors configured to be plugged into one or more respective optical receptacles.

Illustrative embodiments will now be described with reference toFIGS. 1A-11, in which like reference numerals represent like components, elements or features. It should be noted that features, components or elements shown in the drawings are not necessarily drawn to scale. The term “optoelectronic element,” as that term is used herein, denotes either a photosensor or a VCSEL. The term “flip-chip,” as that term is used herein, denotes a chip having a top surface in which apertures of optoelectronic elements exist and which is designed to be mounted with the top surface of the chip in contact with a mounting surface such that the apertures face, and are possibly in contact with, the mounting surface. In accordance with embodiments described herein, the mounting surface is a substrate that is transparent to an operating wavelength of the optoelectronic elements and the flip-chips are mounted with the top surface down on the substrate such that the apertures face the top surface of the substrate. In the case where the optoelectronic elements are VCSELs, the light produced by the VCSELs passes out of the respective apertures through the top surface of the substrate, propagates through the substrate, and exits the substrate through the bottom surface of the substrate. In the case where the optoelectronic elements are photosensors, the light passes through the bottom surface of the substrate, propagates through the substrate, exits the substrate through the top surface of the substrate, and enters the apertures of the photosensors. The term “flip-chip-mounted” is used herein to denote a flip-chip mounted on a mounting surface with the apertures of the optoelectronic elements of the chips facing the mounting surface. For ease of discussion, it will be assumed that the flip-chips are VCSEL flip-chips, each having multiple VCSELs.

FIG. 1Aillustrates a top perspective view of a VCSEL flip-chip assembly1in accordance with an illustrative embodiment.FIG. 1Billustrates a bottom perspective view of the VCSEL flip-chip assembly1shown inFIG. 1A.FIG. 1Cillustrates a side perspective view of the VCSEL flip-chip assembly1shown inFIGS. 1A and 1B. The VCSEL flip-chip assembly1comprises a plurality of VCSEL flip-chips2that are flip-chip mounted on a top surface3aof a substrate3. The substrate3is made of a material that is transparent to the operating wavelength of the light produced by VCSELs of the flip-chips2. Each VCSEL flip-chip2has a plurality of VCSELs formed therein such that the combination of VCSEL flip-chips2mounted on the substrate3comprises an array of precisely-aligned VCSELs.

The manner in which known semiconductor fabrication processes may be used to form VCSELs at very precise locations in an integrated circuit (IC) chip is well known. The manner in which individual IC chips can be mounted relative to one another at very precise locations and with very precise orientations on a substrate is also known. The parent application discloses embodiments for accomplishing this for the VCSEL flip-chips. Therefore, persons of skill in the art will understand how to use such techniques to form VCSELs at very precise locations in flip-chips2and mount the flip-chips2at very precise locations and with very precise orientations on the substrate3relative to one another to achieve an array of very precisely aligned VCSELs. In accordance with embodiments described herein, such techniques are used to mount the flip-chips2on the top surface3aof the substrate3at very precise locations and with very precise orientations relative to one another to achieve an array of VCSELs that are precisely aligned. For example, assuming for exemplary purposes that each of the VCSEL flip-chips2has four VCSELs and that the VCSEL flip-chip assembly1has four VCSEL flip-chips2, the resulting VCSEL array would be a 1×16 array of VCSELs with the sixteen VCSELs being aligned along an imaginary line that passes through the centers of the sixteen VCSELs.

The top surface3aof the substrate has a plurality of electrical traces4disposed thereon. Each of the electrical traces4is connected on a first end thereof to a first end5aof a respective electrical via5and is connected on a second end thereof to an electrical contact pad6(FIG. 1B) of the respective VCSEL flip-chip2. A bottom surface3bof the substrate3has electrical traces7thereon. Each of the electrical traces7is connected on a first end thereof to a respective electrical contact pad8disposed on the bottom surface3bof the substrate3and is connected on a second end thereof to a second end5bof a respective electrical via5. As will be described below with reference to the PCB shown inFIG. 3, when the VCSEL flip-chip assembly1is mounted on the PCB, the electrical contact pads8located at the edges of the substrate3are in contact with respect electrical contact pads of the PCB. Through all of these electrical connections5a,5b,6,7, and8, electrical signals are delivered from the PCB to the VCSEL flip-chips2in order to drive the VCSELS of the flip-chips2.

The bottom surface3bof the substrate3has an array of lenses11formed therein (FIG. 1B). The lenses11are typically diffractive or refractive lenses. Each lens11is precisely aligned with a respective VCSEL of one of the VCSEL flip-chips2. Each lens11directs a beam of light produced by a respective VCSEL toward an end of an optical fiber held in a ferrule of a multi-optical fiber ferrule device, as will be described below in more detail with reference toFIGS. 5A-6. As can be seen inFIG. 1B, each VCSEL flip-chip2has a group of the lenses11located beneath it. The VCSEL flip-chip assembly1has an array of N VCSELs, where N is an integer than is equal to or greater than two (i.e., the assembly1has at least two chips2, each having at least one VCSELs). Likewise, the substrate has an array of N lenses11, where each lens is associated with a respective one of the VCSELs.

As can be seen inFIGS. 1B and 1C, the bottom surface3bof the substrate3has a plurality of balls10disposed thereon. The balls10are disposed at precise locations on the bottom surface3brelative to one another and relative to the VCSEL flip-chips2. As will be described below in more detail with reference toFIGS. 4-5b, the balls10are used as a mating feature for mating the flip-chip assembly1with a multi-optical fiber ferrule device that holds ends of a plurality of optical fibers (not shown). The mating of the flip-chip assembly1with the multi-optical fiber ferrule device brings the ends of the optical fibers into alignment with the respective VCSELs of the flip-chips, as will be described below in more detail.

Semiconductor fabrication processes are used to form the traces4and7, the contact pads8and the vias5in the substrate3. The substrate3may, for example, be glass, although the substrate3is not limited to any particular materials, provided the material is transparent to the operating wavelength of light of the VCSELs. As is well known in the art of semiconductor fabrication, very precise features can be formed at very precise locations on a substrate material using semiconductor fabrication processes such as, for example, photolithography. In accordance with an illustrative embodiment, such techniques are used to define the locations at which the balls10will be placed on the bottom surface3aof the substrate. The locations for the balls10can be defined by, for example, forming a round pad for each ball location using photolithography. After the VCSEL flip-chips2have been flip-chip mounted on the upper surface3aof the substrate3, a material that is capable of being melted such as, for example, gold-tin (AuSn) alloy, in the form of a ball can be attached to each pad. Such solder ball attachment processes are well known to those skilled in the art, and therefore will not be further described herein in the interest of brevity.

The balls10may be made of a variety of materials that have characteristics that make them suitable for use as mating features. Examples of suitable materials are AuSn solder and epoxy. The shape and size of the balls10are chosen to provide an interference fit with openings with which the balls10mate, as will be described below in more detail with reference toFIGS. 5A and 5B. The balls10are depicted as being perfectly spherical in shape, but they are typically shaped as truncated spheres, where the portions of the balls10that are in contact with the bottom surface3bare the truncated portions of the balls10and where the portions of the balls10that are not in contact with the bottom surface3bare the spherical portions of the balls10.

FIG. 2illustrates a top perspective view of the VCSEL flip-chip assembly shown inFIGS. 1A-1Cafter the top surface of the assembly has been covered with an encapsulation material20. The encapsulation material20extends between the outer peripheries of the VCSEL flip-chips2and the upper surface3aof the substrate3of the assembly1. The VCSEL flip-chips2are at least partially encapsulated in the encapsulation material20, which comprises a sealing material such as epoxy, for example. The encapsulation material20forms seals that extend between the outer periphery of each flip-chip2and the top surface3aof the substrate3, as depicted inFIG. 3. The encapsulation material20seals gaps between the surfaces of the flip-chips2and the top surface3aof the substrate, thereby preventing particulates and contaminants from impeding the optical pathways between the VCSELs of the flip-chips2and the respective lenses11. In environments in which particulates or contaminants are not a concern, the encapsulation material20may not be needed.

FIG. 3illustrates a top perspective view of a PCB30prior to the VCSEL flip-chip assembly1shown inFIG. 2being mounted thereon.FIGS. 4A and 4Billustrate top and bottom perspective views, respectively, of the PCB30shown inFIG. 3with the VCSEL flip-chip assembly1mounted thereon. The PCB30has an opening31(FIG. 3) formed therein that extends through the PCB30.FIGS. 5A and 5Billustrate back and front perspective views, respectively, of a multi-optical fiber ferrule device40that mates with the VCSEL flip-chip assembly1to align ends of optical fibers (not shown) held in the ferrule device40with VCSELs of the VCSEL flip-chips2. The top surface30aof the PCB30has electrical contact pads32thereon that come into contact with respective electrical contacts8disposed on the bottom surface3bof the substrate3(FIG. 1B) when the VCSEL flip-chip assembly1is mounted on the PCB30, as shown inFIG. 4A.

The opening31has a width that is defined by upper and lower sides31aand31b, respectively, and a length that is defined by left and right sides31cand31d, respectively. The shape and size of the opening31defined by the sides31a-31dis complementary to the shape and size of the ferrule device40(FIGS. 5A and 5B) that mates with the VCSEL flip-chip assembly1. In other words the opening31has a length and a width that is about the same, but slightly greater than, the length and width of the ferrule device40such that when the ferrule device40is inserted into the opening31, there is very little space between the sides31a-31dand the respective sides of the ferrule device40. The opening31has rounded corners31e-31hto ease the insertion of the ferrule device40into the opening31. The rounded corners31e-31hallow an adhesive material such as epoxy (not shown) to be dispensed therein in order to bond the assembly1to the PCB30.

In accordance with an illustrative embodiment, a controller IC33is mounted on the top surface30aof the PCB30, as shown inFIGS. 3 and 4A. The controller IC may be, for example, a laser diode driver IC for driving the VCSELs of the VCSEL flip-chips2(FIG. 1A), in which case electrical drive signals (e.g., modulation and bias current signals) outputted from the IC33are transferred over electrically-conductive traces (not shown) of the PCB30to the contact pads32disposed on the top surface30aof the PCB30. The electrical drive signals are then conducted by the contact pads8, traces7, and vias5to the contact pads of the VCSEL flip-chips2.

As shown inFIG. 4B, when the assembly1is mounted on the PCB30, the bottom surface3bof the substrate3is positioned immediately above the opening31formed in the PCB30, and the sides of the flip-chips2on which the VCSEL apertures (not shown) are disposed face the opening31. The corners of the assembly1are above the rounded corners31e-31hof the opening31, and are therefore in contact with the adhesive material (not shown) that is disposed within the rounded corners31e-31hof the opening31. The adhesive material may also be dispensed on the top surface30aof the PCB30at locations where the assembly1comes into contact with the top surface30aof the PCB30. The adhesive material bonds the assembly1to the top surface30aof the PCB30, although other or additional mechanisms or devices may be used to secure the assembly1to the PCB30.

FIGS. 5A and 5Billustrate back and front perspective views, respectively, of a multi-optical fiber ferrule device40that mates with the VCSEL flip-chip assembly1to align ends of optical fibers (not shown) held in the ferrule device40with VCSELs of the VCSEL flip-chips2. The ferrule device40has a back side40a, a front side40b, a top side40c, a bottom side40d, a left side40e, and a right side40f. The back side40ahas openings41formed therein that extend a distance into the ferrule device40in a direction toward the front side40band normal to at least the back side40a. In accordance with this illustrative embodiment, the ferrule device40is rectangular in shape such that the back side40aand front side40bare parallel to one another, the top side40cand the bottom side40dare parallel to one another and perpendicular to the back side40aand front side40b, and the left and right sides40eand40fare parallel to one another and perpendicular to the back side40a, the front side40b, the top side40c, and the bottom side40d. However, the ferrule device40does not necessarily have this shape, but could have a variety of shapes, as will be understood by persons of skill in the art in view of the description being provided herein.

The openings41are ferrules that are shaped and sized to receive respective optical fiber cables (not shown) and have back portions41athat are complementary in shape to the shape of the fiber cables and front portions41bthat are complementary in shape to the fibers of the fiber cables. When the fiber cables are held within the respective ferrules41, ends of the respective optical fibers are disposed in the respective front portions41bof the ferrules41. In accordance with this illustrative embodiment, the front side40bof the ferrule device40has N lenses42formed therein, where N is the number of VCSELs in the VCSEL array of the VCSEL flip-chip assembly1(FIG. 1A). The lenses42are transparent to the operating wavelength of light produced by the VCSELs, and in some case the entire ferrule device40may be transparent to the operating wavelength of light produced by the VCSELs.

The front side40bof the ferrule device40has openings50formed therein that are shaped and sized to mate with the balls10(FIG. 4B) disposed on the bottom surface3bof the substrate3of the assembly1. After the assembly1has been secured to the PCB30, as shown inFIG. 4B, the ferrule device40is inserted into the opening31formed in the PCB30with the front side40bof the ferrule device40facing toward the bottom surface3bof the substrate3of the assembly1. As the front side40bof the ferrule device40passes into the opening31, the balls10begin to mate with the respective openings50formed in the front side40bof the ferrule device40. When the balls10are fully mated with the openings50, the lenses42of the ferrule device40are in abutment with, or at least in proximity to, the respective lenses11formed in the bottom surface3bof the substrate3. The mating of the balls10with the openings50precisely aligns the assembly1with the ferrule device40, which brings the VCSELs into precise alignment with the ends of the optical fibers held in the front portions41bof the ferrules41. The lenses11and42together cause the light produced by the respective VCSELs to be focused onto the ends of the respective optical fibers held in the front portions41bof the respective ferrules41. It should be noted that both sets of lenses11and42are not needed in all cases. Because of the precise alignment between the VCSELS and the ends of the optical fibers, and because of the proximity of the VCSELs to the respective ends of the optical fibers, it is possible that only the lenses11or the lenses42, but not both, are needed.

The ferrule device40is typically made of a molded plastic material. One of the advantages of making the ferrule device40out of molded plastic is that plastic molding processes allow features to made with very high precision. Therefore, it can be ensured that the locations, sizes and shapes of the openings50are very precise, which ensures that the mating of the openings50with the balls10will bring the ends of the fibers that are disposed within the front portions41bof the ferrules41into precise alignment with the lenses11and42. It should be noted, however, that the ferrule device40may be made of any suitable material, including, but not limited to, a variety of plastic and metal materials.

One of the advantages of the VCSEL flip-chip assembly1is that it can be handled as an SMT component. In other words, during the process of mounting the IC33(FIGS. 3 and 4A) and the assembly1on the PCB30, a machine vision system and pick-and-place tool of the type that are normally used to mount SMT components on a PCB may be used to mount the IC33, the assembly1and any other SMT components on the PCB30. Also, the assembly1can be constructed at the wafer level and then singulated into the individual assemblies1. Thus, the assemblies1can be cost-effectively mass produced with very tight tolerances to produce precisely aligned VCSEL arrays. Once the assemblies1have been mounted on the respective PCBs30, the respective ferrule devices40can be easily mated with the assemblies1in the manner described above to bring the VCSELs of the arrays into precise alignment with ends of the fibers held within the front portions41bof the ferrules41. After the ferrule devices40have been mated with the respective assemblies1, suitable securing mechanisms (not shown for ease of illustration and clarity) are typically used to fixedly secure the ferrule devices40to the respective PCBs30.

It should be noted that the mating features10and50may have any desired shapes or configurations provided that the mating features10and50precisely mate with one another. For example, while the mating features10have been described as being balls, they could be rectangles or some other shape. Also, the balls10could be disposed on the ferrule device40and the openings50could be formed in the substrate3.

FIG. 6illustrates a top perspective view of a parallel optical transmitter module60comprising the PCB30shown inFIGS. 3A and 3B, the VCSEL flip-chip assembly1and the multi-optical fiber ferrule device40. First ends of a first plurality of optical fibers51are held in the ferrule device40, as described above, and an MT connector52is secured to second ends of the optical fibers51. As an example of one possible implementation scenario, the PCB30having the assembly1and the ferrule device40secured thereto may be disposed inside of box (not shown), such as an electromagnetic interference (EMI) cage housing, and the MT connector52may be positioned in a front panel of a rack (not shown) that contains the EMI cage housing. The MT connector52is a known male version of a connector that has alignment pins53for mating with respective alignment holes formed in a known female MT connector (not shown). In this exemplary scenario, the female MT connector would be plugged into the male MT connector52on the front panel of the rack. The female MT connector would be connected to ends of a second plurality of optical fibers (not shown) of an optical communications network (not shown) for communicating the optical signals produced by the VCSELs of the assembly1over the network.

FIG. 7illustrates a top perspective view of the VCSEL flip-chip assembly100in accordance with another illustrative embodiment.FIG. 8illustrates a top perspective view of a PCB130on which the VCSEL flip-chip assembly100shown inFIG. 7may be mounted.FIG. 9illustrates a top perspective view of the PCB130shown inFIG. 8with the VCSEL flip-chip assembly100shown inFIG. 7mounted thereon.FIG. 10illustrates a side perspective view of the PCB130shown inFIG. 9with the VCSEL flip-chip assembly100mounted thereon and with a multi-optical fiber ferrule device140secured thereto.FIG. 11illustrates a top perspective view of a parallel optical transmitter module150comprising a connector52connected to optical fibers51that are connected to the ferrule device140shown inFIG. 10, which is secured to the PCB130in alignment with the VCSEL flip-chip assembly100.

The VCSEL flip-chip assembly100shown inFIG. 7is identical to the VCSEL flip-chip assembly1shown inFIGS. 1A-1Cexcept that the assembly100does not have the electrical contacts8and electrical traces7disposed on the bottom surface3bof the substrate3and does not have the vias5formed in the substrate3. Because many features of the VCSEL flip-chip assembly100are identical to features of the VCSEL flip-chip assembly1shown inFIGS. 1A-2, like reference numerals inFIGS. 1A-2and7are used to represent like features. Likewise, the PCB130shown inFIG. 8is identical to the PCB30shown inFIG. 3except that the PCB130has holes134formed therein on opposite sides of the opening31for securing the ferrule device140to the PCB130, as will be described below in more detail with reference toFIG. 10. Because many features of the PCB130are identical to features of the PCB30, like reference numerals inFIGS. 3 and 8are used to represent like features. Likewise, the ferrule device140shown inFIG. 10is identical to the ferrule device40shown inFIGS. 5A and 5Bexcept that the ferrule device140has posts141disposed at opposite ends thereof for mating with the holes134formed in the PCB130. Because many features of the ferrule device140are identical to features of the ferrule device40, like reference numerals inFIGS. 5,5B and10are used to represent like features.

Electrical contact pads101and electrical traces102(FIG. 7) are disposed on the top surface3aof the substrate3of the assembly100. First ends of the electrical traces102are connected to the contact pads101of the PCB130and second ends of the traces102are connected to the contact pads6(FIG. 9) of the VCSEL flip-chips2(FIG. 7). When the assembly100is mounted on the PCB130as shown inFIG. 9, the electrical contact pads101disposed on the top surface3aof the assembly100are in contact with the electrical contact pads32(FIG. 8) disposed on the top surface130aof the PCB130via the traces102. The ferrule device140(FIG. 10) has posts141thereon that mate with the holes134formed in the PCB130to roughly align the ferrule device140with the assembly100. The balls10(FIGS. 7 and 9) disposed on the bottom surface3bof the assembly100then mate with the openings50(FIG. 10) formed in the ferrule device140to finely align the ferrule device140with the assembly100. After fine alignment has been achieved, the holes134and the posts141are fixedly secured to one another by an adhesive material such epoxy.

It can be seen in the embodiment ofFIG. 10that the assembly100is positioned in between the PCB130and the ferrule device140, whereas in the embodiment ofFIG. 6, the PCB30is positioned in between the assembly1and the ferrule device40. As shown inFIG. 11, the connector52and fibers51shown inFIG. 6may be connected to the ferrule device140in the same manner depicted inFIG. 6. The same result is achieved in both embodiments, but the mounting configurations are different and the configurations for electrically interconnecting the assemblies1and100to the PCBs30and130, respectively, are different.

It should be noted that the VCSEL flip-chip assemblies1and100have been described with reference to their uses in forming arrays of VCSELs that can be used in optical transmitters. The flip-chip assemblies could instead be made up of flip-chips that have photosensors instead of, or in addition to, VCSELs. For example, each of the VCSELs of the flip-chips2could be replaced by photosensors, such as P-intrinsic-N (PIN) photosensors, or one or more of the optoelectronic elements of each flip-chip2may be photosensors and the other optoelectronic elements of each flip-chip2may be VCSELs. In such cases, the optical transmitters60and150would instead be optical receivers or transceivers. Persons of skill in the art will understand the manner in which such flip-chips having such optoelectronic elements may be manufactured and incorporated into the assemblies1and100. The term “optical communications module,” as that term is used herein, denotes an optical transmitter module, an optical receiver module and an optical transceiver module.

It should be noted that the assemblies1and100, the ferrule devices40and140and the optical communication modules60and150have been described with reference to a few illustrative embodiments for the purposes of demonstrating the principles and concepts of the invention and to provide a few examples of the manner in which the invention may be implemented. The invention is not limited to these embodiments, as will be understood by persons skilled in the art in view of the description provided herein. The assemblies1and100, the ferrule devices40and140and the optical communications modules60and150may have a variety of configurations that are different from the illustrative embodiments described herein, as will be understood by persons of skill in the art.