Circuits and methods for multi-phase clock generators and phase interpolators

Circuits and methods for multi-phase clock generators and phase interpolators are provided. The multi-phase clock generators include a delay line and multi-phase injection locked oscillator. At each stage of the multi-phase injection locked oscillator, injection currents are provided from a corresponding stage of the delay line. Outputs of the multi-phase injection locked oscillator and provided to mixers which produce inputs to an operational transconductance amplifier which provides feedback to the delay line and the multi-phase injection locked oscillator. The phase interpolator uses a technique of flipping certain input clock signals to reduce the number of components required while still being able to interpolate phase over 360 degrees and to reduce noise.

BACKGROUND

An insatiable demand for high-capacity and high-speed I/Os is pushing wireline transceivers to a higher aggregate data rate. Multi-phase sampling is adopted in receivers to achieve the same data rate with a lower clock frequency, thus relaxing the analog-to-digital (ADC) speed requirement. Multi-phase sampling clocks can be directly generated by multi-phase clock generators (MPCGs) from de-skewed clock sources or can be generated by one or more phase interpolators (PIs).

The reduced symbol period of a higher data rate puts more stringent requirements on jitter and phase accuracy of multi-phase clocks and the linearity of PIs.

Accordingly, new circuits and methods for MPCGs and PIs are desirable.

SUMMARY

In accordance with some embodiments, circuits and methods multi-phase clock generators and phase interpolators are provided. In some embodiments, circuits for a multi-phase clock generator are provided, the circuits comprising: a delay line comprising a first plurality of differential unit delay cells, wherein each of the first plurality of differential unit delay cells has a pair of clock inputs and a pair clock outputs, wherein the first plurality of differential unit delay cells are connected in series such that the pair of clock outputs of a first of the first plurality of differential unit delay cells is connected to the pair of clock inputs of a second of the first plurality of differential unit delay cells, and wherein each unit cell of the first plurality of differential unit delay cells outputs a pair of clock signals having different phases than each pair of clock signals output by other of the first plurality of differential unit delay cells; and a ring oscillator comprising a second plurality of differential unit delay cells, wherein each of the second plurality of differential unit delay cells has a pair of clock inputs, a pair of current injection inputs, and a pair clock outputs, wherein the pair of current injection inputs of each of the second plurality of differential unit delay cells is coupled to the pair of clock outputs of a corresponding one of the first plurality of differential unit delay cells, wherein the second plurality of differential unit delay cells are connected in series such that the pair of clock outputs of a first of the second plurality of differential unit delay cells is connected to the pair of inputs of a second of the second plurality of differential unit delay cells, wherein the pair of outputs of a last of the second plurality of differential unit delay cells are flipped and connected to the pair of inputs of a first of the second plurality of differential unit delay cells, and wherein each unit cell of the second plurality of differential unit cells outputs a pair of clock signals having different phases than each pair of clock signals output by other of the second plurality of differential unit delay cells.

In some of these embodiments, the delay line further comprises a dummy unit cell connected to a last of the first plurality of differential unit delay cells.

In some of these embodiments, the pair of current injection inputs of each of the second plurality of differential unit delay cells is coupled to the pair of output of a corresponding one of the first plurality of differential unit delay cells by a buffer.

In some of these embodiments, each unit cell in the first plurality of differential unit delay cells comprises: a first inverter having an input connected to a first of the pair of clock inputs of the unit cell and having an output connected to a first of the pair of clock outputs of the unit cell; a second inverter having an input connected to a second of the pair of clock inputs of the unit cell and having an output connected to a second of the pair of clock outputs of the unit cell; a third inverter having an input connected to the output of the first inverter and having an output connected to the output of the second inverter; and a fourth inverter having an input connected to the output of the second inverter and having an output connected to the output of the first inverter.

In some of these embodiments, each of the first plurality of differential unit cells also has a pair of current injection inputs.

In some of these embodiments, the pair of current injection inputs for each of the first plurality of differential unit delay cells is connected to ground.

In some of these embodiments, each unit cell in the first plurality of differential unit delay cells comprises: a first inverter having an input connected to a first of the pair of clock inputs of the unit cell and having an output connected to a first of the pair of clock outputs of the unit cell; a second inverter having an input connected to a second of the pair of clock inputs of the unit cell and having an output connected to a second of the pair of clock outputs of the unit cell; a third inverter having an input connected to the output of the first inverter and having an output connected to the output of the second inverter; a fourth inverter having an input connected to the output of the second inverter and having an output connected to the output of the first inverter; and a first buffer having an input connected to a first of the pair of current injection inputs of the unit cell and having an output connected to the first of the pair of clock outputs of the unit cell; and a second buffer having an input connected to a second of the pair of current injection inputs of the unit cell and having an output connected to the second of the pair of clock outputs of the unit cell.

In some of these embodiments, the first buffer is formed from a plurality of selectable, parallel transistors.

In some of these embodiments, each unit cell in the second plurality of differential unit delay cells comprises: a first inverter having an input connected to a first of the pair of clock inputs of the unit cell and having an output connected to a first of the pair of clock outputs of the unit cell; a second inverter having an input connected to a second of the pair of clock inputs of the unit cell and having an output connected to a second of the pair of clock outputs of the unit cell; a third inverter having an input connected to the output of the first inverter and having an output connected to the output of the second inverter; a fourth inverter having an input connected to the output of the second inverter and having an output connected to the output of the first inverter; and a first buffer having an input connected to a first of the pair of current injection inputs of the unit cell and having an output connected to the first of the pair of clock outputs of the unit cell; and a second buffer having an input connected to a second of the pair of current injection inputs of the unit cell and having an output connected to the second of the pair of clock outputs of the unit cell.

In some of these embodiments, each unit cell of the first plurality of differential unit delay cells has includes an identical set of components interconnected in an identical manner.

In some of these embodiments, each unit cell of the second plurality of differential unit delay cells includes an identical set of components interconnected in an identical manner.

In some of these embodiments, at least one unit cell of the first plurality of differential unit delay cells and at least one unit cell of the second plurality of differential unit delay cells include an identical set of components interconnected in an identical manner.

In some of these embodiments, the circuit further comprises a first mixer that mixes the pairs of outputs of two of the second plurality of differential unit delay cells to produce a first mixer output signal and a second mixer that mixes the pairs of outputs of another two of the second plurality of differential unit delay cells to produce a second mixer output signal.

In some of these embodiments, the circuit further comprises an operation transconductance amplifier that receives the first mixer output signal and the second mixer output signal and produce tuning feedback signal that is provided to the delay line and to the ring oscillator.

DETAILED DESCRIPTION

In accordance with some embodiments, new circuits and methods multi-phase clock generators and phase interpolators are provided.

Turning toFIG.1, an example block diagram of a multi-phase clock generator (MPCG) and phase interpolator (PI) circuit100in accordance with some embodiments is shown. As illustrated, circuit100includes a MPCG102and a PI104.

MPCG102can be any suitable multi-phase clock generator in some embodiments. For example, as shown inFIG.1, MPCG102can include a quadrature delay line loop (QDLL)106and a multi-phase injection locked oscillator (MPILOSC)116in some embodiments.

Any suitable QDLL can be used as QDLL106in some embodiments. For example, as shown inFIG.1, QDLL106can include a delay line108, passive mixers110, operational transconductance amplifier (OTA)112, and capacitor114.

PI104can be any suitable phase interpolator in some embodiments. For example, as shown inFIG.1, PI104can include a PI core118and a PI controller120in some embodiments.

In some embodiments, by tuning the delay of the stages in delay line108, the f0of MPILOSC116can be tuned. A control voltage Vtuneof QDLL106biases both the stages in delay line108to have a unit delay of 1/(2N finj) and the stages in the MPILOSC to have f0=finj, in some embodiments. In some embodiments, the delay line outputs have a high spectral purity and suppress the MPILOSC phase noise over a wide injection bandwidth. Moreover, the phase errors due to the finite QDLL loop gain, finite matching of the loading within the delay line, and layout asymmetry are corrected by the MPILOSC, in some embodiments. The two-step multi-phase clock generation scheme thus combines the advantages of low-noise delay lines and symmetric ROSCs and breaks the tradeoff between jitter and phase accuracy in two-phase IL-ROSCs in some embodiments.

Turning toFIG.2A, further details of a QDLL206that can used as QDLL106in accordance with some embodiments is shown.

As illustrated, QDLL206includes a delay line208that receives a differential reference clock (Ref_P and Ref_N) and a Vdd_DL_tune signal, and that outputs eight clock signals (CKDL_0, CKDL_180, CKDL_45, CKDL_225, CKDL_90, CKDL_270, CKDL_135, CKDL_315). Although delay line208outputs eight clock signals, delay line208can output any suitable number (such as four, for example) of clock signals in some embodiments.

As also illustrated inFIG.2A, delay line208includes four unit delay cells226,228,230, and232and a dummy stage234. Unit delay cell226generates CKDL_0 and CKDL_180, unit delay cell228generates CKDL_45 and CKDL_225, unit delay cell230generates CKDL_90 and CKDL_270, and unit delay cell232generates CKDL_135 and CKDL_315. Although delay line208includes four unit delay cells, delay line208can include any suitable number (such as two, for example) of unit delay cells in some embodiments.

Dummy stage234provides loading to cell232that is uniform with the loading provided to cells226,228, and230by cells228,230, and232, respectively.

Unit delay cells226,228,230,232, and234can be any suitable unit delay cells in some embodiments. For example, in some embodiments, unit delay cells226,228,230,232, and234can be implemented as described below in connection withFIGS.3A and3B.

FIG.3Aillustrates pin definitions of a unit delay cells in accordance with some embodiments. For example, the differential input to each unit delay cell is identified by Vip and Vin, the differential output from each unit delay cell is identified by Vop and Von, and the differential injection current to the unit delay cell is identified by Iinjp and Iinjn.

FIG.3Billustrates an example schematic of a unit delay cell in accordance with some embodiments. Any suitable transistors can be used as the transistors shown inFIG.3B, in some embodiments. For example, these transistors can be MOSFETs, in some embodiments. More particularly, for example, transistors302and304can be p-MOSFETs having a width of 8 μm and a length of 60 nm, transistors310and312can be p-MOSFETs that are a quarter of the size of transistors302and304, transistors306and308can be n-MOSFETs having a width of 4 μm and a length of 60 nm, transistors314and316can be n-MOSFETs that are a quarter of the size of transistors306and308, and the transistors in318and320can be n-MOSFETs having a width of 300 nm and a length of 60 nm, in some embodiments. The sizing ratio between the transistors in318and320and the transistors306,308,302, and304determines the injection strength in some embodiments. In some embodiments, multiple, selectable parallel transistors can be implemented for transistors318and320. In this way, the injection strength can be controlled by controlling how many transistors in each of transistors318and320are active. For example, the injection strength for the unit delay cell shown inFIG.3Bwith only one transistor in each of transistors318and320active is 0.3 μm/(4 μm+8 μm/2), that is, 0.04. A total injection strength of 0.12 provides a simulated locking range of ±1 GHz and phase-error sensitivity of less than 0.05 in some embodiments.

The per-stage gain KDLof each unit delay cell can be linearized and expressed in terms of the N-stage MPILOSC's gain KVCOas follows:

In some embodiments, the KVCOcan vary from 2 to 6 GHz/V across the tuning range. In some embodiments, a waveform-shaping buffer at the delay-line input reduces the amplitude of the rail-to-rail input clock to be close to the delay-line internal voltage amplitude.

As further illustrated inFIG.2A, QDLL206can also include buffers222, in some embodiments. Any suitable buffers can be used in some embodiments. For example, in some embodiments, buffers222can be AC-coupled buffers. Any suitable number of buffers can be included in buffers222, in some embodiments. The outputs of buffers222(CKD_0, CKD_180, CKD_45, CKD_225, CKD_90, CKD_270, CKD_135, CKD_315) can be provided to the inputs of mixers110, in some embodiments.

Passive mixers110inFIG.2Acan be any suitable mixers in some embodiments. For example, passive mixers110can be implemented using passive mixers410and411as shown inFIG.4, in some embodiments. Any suitable transistors can be used as the transistors shown inFIG.4. For example, these transistors can be MOSFETs in some embodiments. More particularly, for example, the transistors can be n-MOSFETs having a width of 2 μm and a length of 60 nm, in some embodiments. Resistors RD inFIG.4can be any suitable resistors in some embodiments. For example, in some embodiments, resistors RD can be 1.5 kΩ resistors.

OTA112inFIG.2Acan be any suitable OTA in some embodiments. For example, OTA112can be implemented as shown in the schematic ofFIG.5in some embodiments. Any suitable transistors can be used as the transistors shown inFIG.5, in some embodiments. For example, these transistors can be MOSFETs, in some embodiments. More particularly, for example, the transistor in the top left can be p-MOSFETs having a width of 24 μm and a length of 300 nm, the transistor in the top right can be p-MOSFETs having a width of 12 μm and a length of 300 nm, the transistors in the middle row can be p-MOSFETs having a width of 12 μm and a length of 300 nm, and the transistors in the bottom row can be n-MOSFETs having a width of 12 μm and a length of 300 nm, in some embodiments. Resistor RCinFIG.5can be any suitable resistor in some embodiments. For example, in some embodiments, resistors RCcan be a 1.2 kΩ resistor. Capacitor CCinFIG.5can be any suitable capacitor in some embodiments. For example, in some embodiments, capacitor can be a 2.5 pF capacitor.

The control voltage Vtune of the QDLL controls the delay of the delay stages in delay line208.

As shown inFIG.2A, in some embodiments, DQLL206also includes an array (including transistors224and238) of five (or any other suitable number) pMOS transistors that control the supply voltage of unit delay cells226,228,230,232, and234. The gates of these pMOS transistors are connected to the QDLL control voltage Vtune, or connected to the supply, depending a digital control code received by array224. In some embodiments, an always-on pMOS transistor236is placed in shunt with array252to linearize the gain of delay line208. The supply tuning does not add any parasitic capacitance to the oscillation nodes and achieves a higher self-oscillation frequency f0compared to load tuning or current tuning, in some embodiments. As shown, a transistor230is also provided to buffer Vdd_DL_tune from Vtune.

Turning toFIG.2B, further details of a MPILOSC216that can used as MPILOSC116in accordance with some embodiments is shown.

As illustrated, MPILOSC216receives eight clock signals (CKDL_0, CKDL_180, CKDL_45, CKDL_225, CKDL_90, CKDL_270, CKDL_135, CKDL_315) and a Vtune signal from QDLL206, and outputs eight clock signals (CKRO_0, CKRO_180, CKRO_45, CKRO_225, CKRO_90, CKRO_270, CKRO_135, CKRO_315). Although MPILOSC216receives and outputs eight clock signals, MPILOSC216can receive and output any suitable number (such as four, for example) of clock signals in some embodiments.

As also illustrated inFIG.2B, MPILOSC216includes four unit delay cells242,244,246, and248. Unit delay cell242generates CKRO_0 and CKRO_180, unit delay cell244generates CKRO_45 and CKRO_225, unit delay cell246generates CKRO_90 and CKRO_270, and unit delay cell248generates CKRO_135 and CKRO_315. Although MPILOSC216includes four unit delay cells, MPILOSC216can include any suitable number (such as two, for example) of unit delay cells in some embodiments.

Unit delay cells242,244,246, and248can be any suitable unit delay cells in some embodiments. For example, unit delay cells242,244,246, and248can be the same as unit delay cells226,228,230,232, and234, in some embodiments. In some embodiments, unit delay cells226,228,230,232, and234can be implemented as described above in connection withFIGS.3A and3B

As further illustrated inFIG.2A, MPILOSC216can also include buffers256, in some embodiments. Any suitable buffers can be used in some embodiments. For example, in some embodiments, buffers256can be AC-coupled buffers. Any suitable number of buffers can be included in buffers256, in some embodiments. The outputs of buffers256(CKR_0, CKR_180, CKR_45, CKR_225, CKR_90, CKR_270, CKR_135, CKR_315) can be provided to device, such as phase interpolator118ofFIG.1, in some embodiments.

The control voltage Vtune of the QDLL controls the delay of the delay stages in the MPILOSC216.

As shown inFIG.2B, in some embodiments, MPILOSC216also includes an array (including transistors252and250) of five (or any other suitable number) pMOS transistors that control the supply voltage of unit delay cells242,244,246, and248. The gates of these pMOS transistors are connected to the QDLL control voltage Vtune, or connected to the supply, depending a digital control code received by array252. In some embodiments, an always-on pMOS transistor254is placed in shunt with array252to linearize the gain of MPILOSC216. The supply tuning does not add any parasitic capacitance to the oscillation nodes and achieves a higher self-oscillation frequency f0compared to load tuning or current tuning, in some embodiments. As shown, a transistor250is also provided to buffer Vdd_tune from Vtune.

In some embodiments, when implemented on-chip, MPILOSC216can be laid out in a bowtie pattern, as illustrated for example inFIG.6, in order to minimize the layout-induced mismatch.

Referring back toFIG.1, as shown, circuit100includes a phase interpolator (PI)104. PI104can be any suitable phase interpolator in some embodiments. For example, PI104can be an eight-phase, seven-bit phase interpolator. PI104can interpolate phases by providing a weighted combination of phases as shown inFIG.7. For example, as illustrated, PI104can provide a 22.5 degree clock by equally weighting (e.g., [8,8]) a 0 degree clock and a 45 degree clock.

Turning toFIG.8, an example schematic of a current-mode-logic (CIVIL) implementation of a phase interpolator (PI)800that can be used to implement PI104in accordance with some embodiments is shown. As illustrated, PI800includes a PI core801(that can be used to implement PI core118) and a PI controller803(that can be used to implement PI controller120), in some embodiments.

As shown inFIG.8, PI core801includes four slices (i.e., slice1802, slice2804, slice3806, and slice4808) and CIVIL-to-CMOS buffers830. Each of slices802,804,806, and808includes flipping buffers810and812, CMOS-to-CML buffers814,816,818, and820, and dual differential pair layers822. In some embodiments, there are 16 dual differential pair layers822in each slice (although any suitable number can be used in some embodiments) and each layer822includes a current source824(which can be 150 μA or any other suitable value in some embodiments), and differential pairs826and828(which can each be biased at 0.9 V or any other suitable value in some embodiments). Any suitable transistors can be used in differential pairs826and828. For example, these transistors can be MOSFETs. More particularly, for example, these transistors can each be an n-MOSFET having a width of 240 nm and a length of 60 nm. The sources of the transistors in each differential pair826and828in each layer are connected to ground by a switch (which can me any suitable device, such as an n-MOSFET having any suitable size) for that pair and layer.

In some embodiments, PI core801receives eight (or any other suitable number) quadrature clock signals (CKRO_0, CKRO_180, CKRO_45, CKRO_225, CKRO_90, CKRO_270, CKRO_135, CKRO_315) from MPILOSC116(which can be implemented using MPILOSC216in some embodiments), receives eight 16-bit (or any other suitable number of bits) thermometer encoded digital control words (one word for each set of layers for each differential pair826/828in each slice (i.e.:1. one 16-bit word for differential pair826in slice1802wherein each bit corresponds to one of the layers for that differential pair;2. one 16-bit word for differential pair828in slice1802wherein each bit corresponds to one of the layers for that differential pair;3. one 16-bit word for differential pair826in slice2804wherein each bit corresponds to one of the layers for that differential pair;4. one 16-bit word for differential pair828in slice2804wherein each bit corresponds to one of the layers for that differential pair,5. one 16-bit word for differential pair826in slice3806wherein each bit corresponds to one of the layers for that differential pair;6. one 16-bit word for differential pair828in slice3806wherein each bit corresponds to one of the layers for that differential pair;7. one 16-bit word for differential pair826in slice4808wherein each bit corresponds to one of the layers for that differential pair; and8. one 16-bit word for differential pair828in slice4808wherein each bit corresponds to one of the layers for that differential pair),
receives eight flip control signals (one for each pair clock signals received at each of the slices) from PI controller803, and outputs differential phase interpolated clock phase interpolated clock signal.

While PI800is implemented with four slices, the PI can be implemented with any suitable arrangement of components (whether with slices or not) to achieve the same functionality as what is provided by the arrangement ofFIG.8.

In some embodiments, the seven bits of the phase interpolator are one bit for the clock polarity (e.g., the most significant bit), two bits for the selection of one slice from four slices (e.g., the next two most significant bits), and four bits used to encode the thermometer encoded digital control words SelX and SelBX (e.g., the remaining four least significant bits).

During operation, in some embodiments, the eight-phase clock signals from the QDLL are received at the flip buffers of each slice. Depending on the flip control signal, the eight-phase clock signals will pass straight through the flip buffers (as represented by the straight lines in the flip buffer schematic symbols) or be swapped by them (as represented by the X lines in the flip buffer schematic symbols).

The CMOS-to-CML buffers (which can be implemented using 2-bit programmable inverters, in some embodiments) will then shape the clipped eight-phase clock signals to sinusoidal 250-mVpp clocks. The shaped CML signals are then received at the gates of the corresponding transistors in the differential pairs. The switches at the sources of the transistors in differential pairs826and828are controlled by the thermometer encoded digital control words received on busses SelX and SelBX, where X corresponds to the slice number for the differential pairs. These switches make active or inactive the corresponding differential pairs across the 16 layers. For example, Sel1<0> makes active differential pair826of layer 1 of slice1; Sel2<1> makes active differential pair826of layer 2 of slice2; SelB1<0> makes active differential pair828of layer 1 of slice1; Sel2B<1> makes active differential pair828of layer 2 of slice2. The currents of each active differential pair across all layers and slices sum as controlled by the shaped CIVIL signals at their gates to provide interpolated CIVIL clock signals CKPI_p and CKPI_n. In some embodiments, differential pairs will only be active in one slice at a time. The interpolated CML clock signals are then converted to CMOS signals by CML-to-CMOS buffers to provide interpolated CMOS clock signals.

Unfortunately, gate-to-drain parasitic capacitance coupling at the transistors of the differential pairs of each layer of each slice introduce non-linearities into the interpolated CML clock signals (and thus the interpolated CMOS clock signals). To counter these non-linearities, the quadrature clock signals at one or more of the flip buffers corresponding to inactive differential pairs can be swapped.

In some embodiments, the PI can use an octagonal constellation (for example, as illustrated inFIG.7) to interpolate eight-phase clocks with unitary steps.

In some embodiments, clock-flipping buffers810and812can flip the received clocks so that the same slice can cover the lower half-plane of the constellation diagram inFIG.7. More particularly, when a flip signal is received by one or both of buffers810and812, the corresponding buffer(s) can flip the signals at its input. For example:if buffer810of slice1802receives a flip signal, CKR_180 can be provided to buffer814(instead of buffer816) of slice1802and CKR_0 can be provided to buffer816(instead of buffer814) of slice1802;if buffer812of slice1802receives a flip signal, CKR_225 can be provided to buffer820(instead of buffer818) of slice1802and CKR_45 can be provided to buffer818(instead of buffer820) of slice1802;if buffer810of slice2804receives a flip signal, CKR_225 can be provided to buffer814(instead of buffer816) of slice2804and CKR_45 can be provided to buffer816(instead of buffer814) of slice2804;if buffer812of slice2804receives a flip signal, CKR_270 can be provided to buffer820(instead of buffer818) of slice2804and CKR_90 can be provided to buffer818(instead of buffer820) of slice2804;if buffer810of slice3806receives a flip signal, CKR_270 can be provided to buffer814(instead of buffer816) of slice3806and CKR_90 can be provided to buffer816(instead of buffer814) of slice3806;if buffer812of slice3806receives a flip signal, CKR_315 can be provided to buffer820(instead of buffer818) of slice3806and CKR_135 can be provided to buffer818(instead of buffer820) of slice3806;if buffer810of slice4808receives a flip signal, CKR_315 can be provided to buffer814(instead of buffer816) of slice4808and CKR_135 can be provided to buffer816(instead of buffer814) of slice4808; andif buffer812of slice4808receives a flip signal, CKR_180 can be provided to buffer820(instead of buffer818) of slice4808and CKR_0 can be provided to buffer818(instead of buffer820) of slice4808.
In some embodiments, this flipping arrangement can enable the PI core to interpolate over 360 degrees with only four slices.

In some embodiments, the clock-flipping scheme in the table ofFIG.9can be used. For example, as shown in this table:when the interpolation range is from 0 to 45 degrees, the differential pairs in slice1802are active and the 135/315 degree clocks are flipped;when the interpolation range is from 45 to 90 degrees, the differential pairs in slice2804are active and no clocks are flipped;when the interpolation range is from 90 to 135 degrees, the differential pairs in slice3806are active and the 0/180 degree clocks are flipped;when the interpolation range is from 135 to 180 degrees, the differential pairs in slice4808are active, the 0/180 degree clocks are flipped, and the 45/225 degree clocks are flipped;when the interpolation range is from 180 to 225 degrees, the differential pairs in slice1802are active, the 0/180 degree clocks are flipped, the 45/225 degree clocks are flipped, and the 90/270 degree clocks are flipped;when the interpolation range is from 225 to 270 degrees, the differential pairs in slice2804are active, the 0/180 degree clocks are flipped, the 45/225 degree clocks are flipped, the 90/270 degree clocks are flipped, and the 135/315 degree clocks are flipped;when the interpolation range is from 270 to 315 degrees, the differential pairs in slice3806are active, the 45/225 degree clocks are flipped, the 90/270 degree clocks are flipped, and the 135/315 degree clocks are flipped; andwhen the interpolation range is from 315 to 360 degrees, the differential pairs in slice4808are active, the 90/270 degree clocks are flipped, and the 135/315 degree clocks are flipped,
wherein differential pairs being active means that the switches of the sources of the transistors of the differential pairs are not completely off.

Turning toFIGS.10A and11A, the clock signals present at the gates of the left transistor of differential pair826across slices802,804,806, and808when interpolating 0-45 degrees are shown. More particularly, from left to right inFIG.10A, clock signals of 0 degrees, 45 degrees, 45 degrees, 90 degrees, 90 degrees, 315 degrees, 315 degrees, and 0 degrees are present at the gates of the transistors. These clock signals couple through the parasitic gate-to-drain capacitances of the transistors to CKPI_p.

Turning toFIGS.10B and11B, the clock signals present at the gates of the left transistor of differential pair826across slices802,804,806, and808when interpolating 45-90 degrees are shown. More particularly, from left to right inFIG.10B, clock signals of 0 degrees, 45 degrees, 45 degrees, 90 degrees, 90 degrees, 135 degrees, 135 degrees, and 0 degrees are present at the gates of the transistors. These clock signals couple through the parasitic gate-to-drain capacitances of the transistors to CKPI_p. As shown, in bold above, the 315 degree couplings inFIG.10Aare 135 degree couplings when interpolating 45-90 degrees as shown inFIG.10B.

In some embodiments, the flipping buffers can be omitted and double the number of slices provided such that each slice corresponds to one row in the table ofFIG.9and the CKR clocks are provided to the CMOS-to-CIVIL buffers based on the clocks that would be present after flipping described above.

In some embodiments, the circuits described herein can be implemented in any suitable process. For example, in some embodiments, the circuits described herein can be implemented in a 65-nm bulk CMOS process.