Integrated structures of acoustic wave device and varactor, and acoustic wave device, varactor and power amplifier, and fabrication methods thereof

An integrated structure of acoustic wave device and varactor comprises an acoustic wave device and a varactor formed on a first part and a second part of a semiconductor substrate respectively. The acoustic wave device comprises an acoustic wave device upper structure and a first part of a bottom epitaxial structure. The acoustic wave device upper structure is formed on the first part of the bottom epitaxial structure. The varactor comprises a varactor upper structure and a second part of the bottom epitaxial structure. The varactor upper structure is formed on the second part of the bottom epitaxial structure. The integrated structure of the acoustic wave device and the varactor formed on the same semiconductor substrate is capable of reducing the module size, optimizing the impedance matching, and reducing the signal loss between the varactor and the acoustic wave device.

FIELD OF THE INVENTION

The present invention relates to an integrated structure of power amplifier and acoustic wave device, wherein the integrated structure of the power amplifier and the acoustic wave device on the same compound semiconductor epitaxial substrate is capable of reducing the component size, optimizing the impedance matching, and reducing the signal loss between the power amplifier and the acoustic wave device.

BACKGROUND OF THE INVENTION

Please refer toFIG. 7˜7D, which are the schematics of conventional production processes of acoustic wave device. First, forming a recess702on a silicon substrate701; then forming a protection layer703on the silicon substrate701and the recess702; and then forming a phosphosilicate glass (PSG) layer705on the protection layer703such that the phosphosilicate glass (PSG) layer705at least filled the recess702; then polishing to remove the phosphosilicate glass (PSG) layer705outside the recess702by chemical mechanical polishing (CMP). Forming an acoustic wave device710with metal711—insulator712—metal713structure above the recess702such that the two ends of the acoustic wave device710with metal711—insulator712—metal713structure across outside of the recess702; removing the rest of the phosphosilicate glass (PSG) layer705within the recess702such that the recess702forms a cavity.

Conventional technical producing the acoustic wave device needs to apply chemical mechanical polishing (CMP) technique for polishing to remove the phosphosilicate glass (PSG) layer705outside the recess702. Furthermore the polishing requires fine polishing such that the roughness of polished surface is very smooth. Otherwise, the formation of the acoustic wave device710with metal711—insulator712—metal713structure will be influenced by the roughness of the polished surface. However the fine polished surface requirement for chemical mechanical polishing (CMP) process, not only the cost of the equipment is very expensive but also the time consuming and the materials cost are very high, such that the cost of production is too high.

Furthermore, the design of the single recess702has the problem that the gap between the bottom of the acoustic wave device710and the bottom of the recess702cannot efficiently widen. Hence, when the acoustic wave device710is affected by stress such that the acoustic wave device710is bended downwardly, the bottom of the acoustic wave device710may easily contact with the bottom of the recess702such that the characteristics of the acoustic wave device710been affected.

On the other hand, the application of the acoustic wave device710is often used as a radio frequency signal filter. When the application is with the power amplifier, the acoustic wave device plays a role to filter the signal firstly and then transmits the filtered signal to the power amplifier; or the power amplifier amplifies the signal firstly and then transmits the amplified signal to the acoustic wave device for filtering. However, the conventional acoustic wave device design is usually based on the silicon substrate. There is no one who ever tries to integrate the acoustic wave device with the compound semiconductor power amplifier on the same compound semiconductor epitaxial substrate. Integrating the acoustic wave device and the power amplifier on the same compound semiconductor epitaxial substrate may reduce the component size, and optimize the impedance matching, and reduce the signal loss between the power amplifier and the acoustic wave device.

Accordingly, the inventor has developed the design which may effectively widen the gap between the bottom of the acoustic wave device and the bottom of the recess, also may integrate the acoustic wave device and the power amplifier on the same compound semiconductor epitaxial substrate with the above mentioned benefits, the advantage of low cost, and with reduced component size, the optimized impedance matching, and the reduced signal loss between the power amplifier and the acoustic wave device.

SUMMARY OF THE INVENTION

There are two technical problems the present invention desires to solve: 1. How to provide a design which may effectively widen the gap between the bottom of the acoustic wave device and the bottom of the recess? 2. How to integrate the acoustic wave device and the power amplifier on the same compound semiconductor epitaxial substrate such that the component size is reduced, the impedance matching is optimized, and the signal loss between the power amplifier and the acoustic wave device is reduced?

To solve the above technical problems to achieve the expected effect, the present invention provides an integrated structure of acoustic wave device and varactor, which comprises a semiconductor substrate, an acoustic wave device and a varactor. The semiconductor substrate includes a first part and a second part of the semiconductor substrate. The acoustic wave device is formed on the first part of the semiconductor substrate, wherein the acoustic wave device comprises an acoustic wave device upper structure and a first part of a bottom epitaxial structure. The bottom epitaxial structure is formed on the semiconductor substrate, wherein the bottom epitaxial structure includes the first part and a second part of the bottom epitaxial structure formed on the first part and the second part of the semiconductor substrate respectively. The acoustic wave device upper structure is formed on the first part of the bottom epitaxial structure. The varactor is formed on the second part of the semiconductor substrate, wherein the varactor comprises a varactor upper structure and the second part of the bottom epitaxial structure. The varactor upper structure is formed on the second part of the bottom epitaxial structure. The integrated structure of the acoustic wave device and the varactor formed on the same the semiconductor substrate is capable of reducing the module size, optimizing the impedance matching, and reducing the signal loss between the varactor and the acoustic wave device.

In an embodiment, the first part of the bottom epitaxial structure comprises a bottom epitaxial structure recess on the top of the bottom epitaxial structure, wherein a bottom of the bottom epitaxial structure recess is the bottom epitaxial structure or the semiconductor substrate; and wherein the acoustic wave device upper structure comprises an acoustic wave device protection layer and an acoustic wave resonance structure. The acoustic wave device protection layer is formed on the first part of the bottom epitaxial structure, wherein the acoustic wave device protection layer comprises an acoustic wave device protection layer recess on a bottom of the acoustic wave device protection layer and an upwardly protruding acoustic wave device protection layer mesa right above the acoustic wave device protection layer recess, and wherein the acoustic wave device protection layer recess is located right above the bottom epitaxial structure recess, the acoustic wave device protection layer recess is communicated with the bottom epitaxial structure recess, and wherein the acoustic wave device protection layer recess and the bottom epitaxial structure recess have a boundary therebetween and the boundary is extended from a top surface of the bottom epitaxial structure. The acoustic wave resonance structure is formed on the acoustic wave device protection layer mesa. The acoustic wave resonance structure comprises an acoustic wave device bottom electrode, a dielectric layer and an acoustic wave device top electrode. The acoustic wave device bottom electrode is formed on the acoustic wave device protection layer mesa. The dielectric layer is formed on the acoustic wave device bottom electrode. The acoustic wave device top electrode is formed on the dielectric layer. A gap between the acoustic wave device protection layer and the bottom of the bottom epitaxial structure recess is increased by the communication of the acoustic wave device protection layer recess and the bottom epitaxial structure recess, so as to avoid the contact of the acoustic wave device protection layer and the bottom of the bottom epitaxial structure recess when the acoustic wave device is affected by stress such that the acoustic wave device protection layer is bended downwardly.

In an embodiment, the acoustic wave device protection layer recess has an opening smaller than or equal to that of the bottom epitaxial structure recess.

In an embodiment, the acoustic wave device comprises an auxiliary layer, a dielectric layer and an interdigital transducer electrode. The auxiliary layer is formed on the first part of the bottom epitaxial structure. The dielectric layer is formed on the auxiliary layer. The interdigital transducer electrode is formed on the dielectric layer.

In an embodiment, the bottom epitaxial structure comprises a bottom n-type doped layer. The varactor upper structure comprises a varactor middle epitaxial structure mesa, a varactor top electrode and a varactor bottom electrode, wherein the varactor top electrode is formed on the varactor middle epitaxial structure mesa, wherein the varactor bottom electrode is formed on the second part of the bottom epitaxial structure. The varactor middle epitaxial structure mesa comprises a middle n-type graded doped layer and a middle p-type doped layer. The middle n-type graded doped layer is formed on the bottom epitaxial structure. The middle p-type doped layer is formed on the middle n-type graded doped layer.

In an embodiment, a thickness of the bottom n-type doped layer is between 200 nm and 600 nm, wherein a thickness of the middle n-type graded doped layer is between 100 nm and 2000 nm, and wherein a thickness of the middle p-type doped layer is between 10 nm and 150 nm.

In an embodiment, the bottom n-type doped layer is made of InGaAs; the middle n-type graded doped layer is made of InGaAs; and the middle p-type doped layer is made of InGaAs.

In an embodiment, the varactor middle epitaxial structure mesa further comprises a varactor ledge layer formed on the middle p-type doped layer, wherein the varactor ledge layer is n-type doped and made of InGaAs, and wherein a thickness of the varactor ledge layer is between 1 nm and 60 nm.

In an embodiment, the bottom epitaxial structure further comprises an etching stop layer formed on the bottom n-type doped layer, wherein the etching stop layer is made of InP. The etching stop layer has a varactor bottom electrode recess, wherein a bottom of the varactor bottom electrode recess is the bottom n-type doped layer such that the varactor bottom electrode is formed on the bottom n-type doped layer within the varactor bottom electrode recess.

In an embodiment, the bottom n-type doped layer is made of GaAs; the middle n-type graded doped layer is made of GaAs; and the middle p-type doped layer is made of GaAs.

In an embodiment, the varactor middle epitaxial structure mesa further comprises a varactor ledge layer formed on the middle p-type doped layer, wherein the varactor ledge layer is n-type doped and made of InGaP, and wherein a thickness of the varactor ledge layer is between 1 nm and 60 nm.

In an embodiment, the bottom epitaxial structure further comprises an etching stop layer formed on the bottom n-type doped layer, wherein the etching stop layer is made of InGaP. The etching stop layer has a varactor bottom electrode recess, wherein a bottom of the varactor bottom electrode recess is the bottom n-type doped layer such that the varactor bottom electrode is formed on the bottom n-type doped layer within the varactor bottom electrode recess.

In an embodiment, the varactor upper structure further comprises a varactor protection layer, the varactor protection layer covers the exposed surfaces of the varactor middle epitaxial structure mesa and the second part of the bottom epitaxial structure.

In an embodiment, the semiconductor substrate is made of one material selected from the group consisting of: Si, GaAs, SiC, InP, GaN, AlN and Sapphire.

In addition, the present invention further provides a method for fabricating an integrated structure of acoustic wave device and varactor, which comprises a following step of: Step F1: forming an acoustic wave device and a varactor on a first part and a second part of a semiconductor substrate respectively, which comprises following steps of: Step F11: forming a bottom epitaxial structure on the semiconductor substrate, wherein the bottom epitaxial structure includes a first part and a second part of the bottom epitaxial structure formed on the first part and the second part of the semiconductor substrate respectively; and Step F12: forming an acoustic wave device upper structure and a varactor upper structure on the first part and the second part of the bottom epitaxial structure respectively; wherein the acoustic wave device comprises the acoustic wave device upper structure and the first part of the bottom epitaxial structure, wherein the varactor comprises the varactor upper structure and the second part of the bottom epitaxial structure; wherein the integrated structure of the acoustic wave device and the varactor formed on the same the semiconductor substrate is capable of reducing the module size, optimizing the impedance matching, and reducing the signal loss between the varactor and the acoustic wave device.

In an embodiment, wherein the Step F12further comprises following steps of: Step F121: forming a middle epitaxial structure on the bottom epitaxial structure; and Step F122: defining a middle epitaxial structure etching area, and etching the middle epitaxial structure within the middle epitaxial structure etching area to form (a) an acoustic wave device middle epitaxial structure mesa and a varactor middle epitaxial structure mesa on the first part and the second part of the bottom epitaxial structure respectively or (b) a varactor middle epitaxial structure mesa on the second part of the bottom epitaxial structure.

In an embodiment, the Step F11comprises a following step of: forming a bottom n-type doped layer on the semiconductor substrate, wherein the bottom epitaxial structure comprises the bottom n-type doped layer; wherein the Step F121comprises following steps of: forming a middle n-type graded doped layer on the bottom epitaxial structure; and forming a middle p-type doped layer on the middle n-type graded doped layer, wherein the middle epitaxial structure comprises the middle n-type graded doped layer and the middle p-type doped layer; wherein the Step F122comprises following steps of: defining a middle p-type doped layer etching area, and etching the middle p-type doped layer within the middle p-type doped layer etching area; and defining a middle n-type graded doped layer etching area, and etching the middle n-type graded doped layer within the middle n-type graded doped layer etching area, thereby the varactor middle epitaxial structure mesa is formed, wherein the varactor middle epitaxial structure mesa comprises the middle n-type graded doped layer and the middle p-type doped layer on the second part of the bottom epitaxial structure; and wherein the Step F12further comprises following steps of: forming a varactor top electrode on the varactor middle epitaxial structure mesa; and forming a varactor bottom electrode on the second part of the bottom epitaxial structure, wherein the varactor upper structure comprises the varactor middle epitaxial structure mesa, the varactor top electrode and the varactor bottom electrode.

In an embodiment, a thickness of the bottom n-type doped layer is between 200 nm and 600 nm, wherein a thickness of the middle n-type graded doped layer is between 100 nm and 2000 nm, and wherein a thickness of the middle p-type doped layer is between 10 nm and 150 nm.

In an embodiment, the bottom n-type doped layer is made of InGaAs; the middle n-type graded doped layer is made of InGaAs; and the middle p-type doped layer is made of InGaAs.

In an embodiment, the Step F121further comprises a following step of: forming a varactor ledge layer on the middle p-type doped layer, wherein the varactor ledge layer is n-type doped and made of InGaAs, wherein a thickness of the varactor ledge layer is between 1 nm and 60 nm; and wherein the Step F122further comprises a following step of: defining a varactor ledge layer etching area, and etching the varactor ledge layer within the varactor ledge layer etching area; wherein the varactor middle epitaxial structure mesa comprises the middle n-type graded doped layer, the middle p-type doped layer and the varactor ledge layer on the second part of the bottom epitaxial structure.

In an embodiment, the Step F11further comprises following steps of: forming an etching stop layer on the bottom n-type doped layer, wherein the bottom epitaxial structure comprises the bottom n-type doped layer and the etching stop layer, wherein the etching stop layer is made of InP; and etching the etching stop layer to form a varactor bottom electrode recess, wherein a bottom of the varactor bottom electrode recess is the bottom n-type doped layer such that the varactor bottom electrode is formed on the bottom n-type doped layer within the varactor bottom electrode recess.

In an embodiment, the bottom n-type doped layer is made of GaAs; the middle n-type graded doped layer is made of GaAs; and the middle p-type doped layer is made of GaAs.

In an embodiment, the Step F121further comprises a following step of: forming a varactor ledge layer on the middle p-type doped layer, wherein the varactor ledge layer is n-type doped and made of InGaP, wherein a thickness of the varactor ledge layer is between 1 nm and 60 nm; and wherein the Step F122further comprises a following step of: defining a varactor ledge layer etching area, and etching the varactor ledge layer within the varactor ledge layer etching area; wherein the varactor middle epitaxial structure mesa comprises the middle n-type graded doped layer, the middle p-type doped layer and the varactor ledge layer on the second part of the bottom epitaxial structure.

In an embodiment, the Step F11further comprises following steps of: forming an etching stop layer on the bottom n-type doped layer, wherein the bottom epitaxial structure comprises the bottom n-type doped layer and the etching stop layer, wherein the etching stop layer is made of InGaP; and etching the etching stop layer to form a varactor bottom electrode recess, wherein a bottom of the varactor bottom electrode recess is the bottom n-type doped layer such that the varactor bottom electrode is formed on the bottom n-type doped layer within the varactor bottom electrode recess.

In an embodiment, the Step F12further comprises a following step of: forming a varactor protection layer, wherein the varactor protection layer covers the exposed surfaces of the second part of the bottom epitaxial structure and the varactor middle epitaxial structure mesa, wherein the varactor upper structure comprises the varactor middle epitaxial structure mesa, the varactor top electrode, the varactor bottom electrode and the varactor protection layer.

In an embodiment, in the Step F122the middle epitaxial structure on the first part of the bottom epitaxial structure is etched and removed; and wherein the Step F12further comprises following steps of: forming an auxiliary layer on the first part of the bottom epitaxial structure; forming a dielectric layer on the auxiliary layer; and forming an interdigital transducer electrode on the dielectric layer, wherein the acoustic wave device upper structure comprises the auxiliary layer, the dielectric layer and the interdigital transducer electrode.

In an embodiment, in the Step F122the acoustic wave device middle epitaxial structure mesa and the varactor middle epitaxial structure mesa are formed on the first part and the second part of the bottom epitaxial structure respectively; and wherein the Step F12further comprises following steps of: forming an acoustic wave device protection layer, wherein the acoustic wave device protection layer covers the exposed surfaces of the first part of the bottom epitaxial structure and the acoustic wave device middle epitaxial structure mesa, and wherein the acoustic wave device protection layer covers the acoustic wave device middle epitaxial structure mesa to form an acoustic wave device protection layer mesa; forming an acoustic wave resonance structure on the acoustic wave device protection layer mesa, which comprises following steps of: forming an acoustic wave device bottom electrode on the acoustic wave device protection layer mesa; forming a dielectric layer on the acoustic wave device bottom electrode; and forming an acoustic wave device top electrode on the dielectric layer, wherein the acoustic wave resonance structure comprises the acoustic wave device bottom electrode, the dielectric layer and the acoustic wave device top electrode; and etching the acoustic wave device middle epitaxial structure mesa to form an acoustic wave device protection layer recess, wherein at least one middle epitaxial structure etching solution contacts with the acoustic wave device middle epitaxial structure mesa and etches and removes the acoustic wave device middle epitaxial structure mesa, thereby a top and a bottom of the acoustic wave device protection layer recess are the acoustic wave device protection layer and the bottom epitaxial structure respectively, wherein the acoustic wave device upper structure comprises the acoustic wave device protection layer and the acoustic wave resonance structure; wherein the Step F1further comprises a following step of: etching the bottom epitaxial structure below the acoustic wave device protection layer recess to form a bottom epitaxial structure recess, wherein a bottom of the bottom epitaxial structure recess is the bottom epitaxial structure or the semiconductor substrate, wherein at least one bottom epitaxial structure etching solution contacts with a top surface of the bottom epitaxial structure and the acoustic wave device protection layer recess, the at least one bottom epitaxial structure etching solution is uniformly distributed on the top surface of the bottom epitaxial structure through the acoustic wave device protection layer recess so as to uniformly etch part of the bottom epitaxial structure below the acoustic wave device protection layer recess to form the bottom epitaxial structure recess, and thereby prevents the side etching phenomenon during the etching, wherein the acoustic wave device protection layer recess is communicated with the bottom epitaxial structure recess, and the acoustic wave device protection layer recess and the bottom epitaxial structure recess have a boundary therebetween and the boundary is extended from the top surface of the bottom epitaxial structure, wherein a gap between the acoustic wave device protection layer and the bottom of the bottom epitaxial structure recess is increased by the communication of the acoustic wave device protection layer recess and the bottom epitaxial structure recess, so as to avoid the contact of the acoustic wave device protection layer and the bottom of the bottom epitaxial structure recess when the acoustic wave device is affected by stress such that the acoustic wave device protection layer is bended downwardly.

In an embodiment, the acoustic wave device protection layer recess has an opening smaller than or equal to that of the bottom epitaxial structure recess.

In an embodiment, the Step F121further comprises following steps of: forming a middle n-type graded doped layer on the bottom epitaxial structure; and forming a middle p-type doped layer on the middle n-type graded doped layer, wherein the middle epitaxial structure comprises the middle n-type graded doped layer and the middle p-type doped layer; and wherein the Step F122comprises following steps of: defining a middle p-type doped layer etching area, and etching the middle p-type doped layer within the middle p-type doped layer etching area; and defining a middle n-type graded doped layer etching area, and etching the middle n-type graded doped layer within the middle n-type graded doped layer etching area; wherein the varactor middle epitaxial structure mesa comprises the middle n-type graded doped layer and the middle p-type doped layer on the second part of the bottom epitaxial structure; and wherein the acoustic wave device middle epitaxial structure mesa comprises (a) the middle n-type graded doped layer on the first part of the bottom epitaxial structure, or (b) the middle n-type graded doped layer and the middle p-type doped layer on the first part of the bottom epitaxial structure.

In an embodiment, the Step F121further comprises a following step of: forming a varactor ledge layer on the middle p-type doped layer; and wherein the Step F122further comprises a following step of: defining a varactor ledge layer etching area, and etching the varactor ledge layer within the varactor ledge layer etching area; wherein the varactor middle epitaxial structure mesa comprises the middle n-type graded doped layer, the middle p-type doped layer and the varactor ledge layer on the second part of the bottom epitaxial structure, and wherein the acoustic wave device middle epitaxial structure mesa comprises (a) the middle n-type graded doped layer on the first part of the bottom epitaxial structure, (b) the middle n-type graded doped layer and the middle p-type doped layer on the first part of the bottom epitaxial structure, or (c) the middle n-type graded doped layer, the middle p-type doped layer and the varactor ledge layer on the first part of the bottom epitaxial structure.

In an embodiment, the semiconductor substrate is made of one material selected from the group consisting of: Si, GaAs, SiC, InP, GaN, AlN and Sapphire.

In addition, the present invention further provides an integrated structure of acoustic wave device, varactor and heterojunction bipolar transistor, which comprises a semiconductor substrate, a bottom epitaxial structure, an acoustic wave device, a middle epitaxial structure, a varactor and an heterojunction bipolar transistor. The semiconductor substrate includes a first part, a second part and a third part of the semiconductor substrate. The acoustic wave device is formed on the first part of the semiconductor substrate, wherein the acoustic wave device comprises an acoustic wave device upper structure and a first part of a bottom epitaxial structure, wherein the bottom epitaxial structure is formed on the semiconductor substrate, wherein the bottom epitaxial structure includes the first part, a second part and a third part of the bottom epitaxial structure formed on the first part, the second part and the third part of the semiconductor substrate respectively, wherein the acoustic wave device upper structure is formed on the first part of the bottom epitaxial structure. The varactor is formed on the second part of the semiconductor substrate, wherein the varactor comprises a varactor upper structure and the second part of the bottom epitaxial structure, wherein the varactor upper structure is formed on the second part of the bottom epitaxial structure. The heterojunction bipolar transistor is formed on an heterojunction bipolar transistor middle epitaxial structure mesa, wherein heterojunction bipolar transistor middle epitaxial structure mesa is formed on the third part of the bottom epitaxial structure. The integrated structure of the acoustic wave device, the varactor and the heterojunction bipolar transistor formed on the same the semiconductor substrate is capable of reducing the module size, optimizing the impedance matching, and reducing the signal loss between the heterojunction bipolar transistor, the varactor and the acoustic wave device.

In an embodiment, the first part of the bottom epitaxial structure comprises a bottom epitaxial structure recess on the top of the bottom epitaxial structure, wherein a bottom of the bottom epitaxial structure recess is the bottom epitaxial structure or the semiconductor substrate; and wherein the acoustic wave device upper structure comprises an acoustic wave device protection layer and an acoustic wave resonance structure. The acoustic wave device protection layer is formed on the first part of the bottom epitaxial structure, wherein the acoustic wave device protection layer comprises an acoustic wave device protection layer recess on a bottom of the acoustic wave device protection layer and an upwardly protruding acoustic wave device protection layer mesa right above the acoustic wave device protection layer recess, and wherein the acoustic wave device protection layer recess is located right above the bottom epitaxial structure recess, the acoustic wave device protection layer recess is communicated with the bottom epitaxial structure recess, and wherein the acoustic wave device protection layer recess and the bottom epitaxial structure recess have a boundary therebetween and the boundary is extended from a top surface of the bottom epitaxial structure. The acoustic wave resonance structure is formed on the acoustic wave device protection layer mesa. The acoustic wave resonance structure comprises an acoustic wave device bottom electrode, a dielectric layer and an acoustic wave device top electrode. The acoustic wave device bottom electrode is formed on the acoustic wave device protection layer mesa. The dielectric layer is formed on the acoustic wave device bottom electrode. The acoustic wave device top electrode is formed on the dielectric layer. A gap between the acoustic wave device protection layer and the bottom of the bottom epitaxial structure recess is increased by the communication of the acoustic wave device protection layer recess and the bottom epitaxial structure recess, so as to avoid the contact of the acoustic wave device protection layer and the bottom of the bottom epitaxial structure recess when the acoustic wave device is affected by stress such that the acoustic wave device protection layer is bended downwardly.

In an embodiment, the acoustic wave device protection layer recess has an opening smaller than or equal to that of the bottom epitaxial structure recess.

In an embodiment, the acoustic wave device comprises an auxiliary layer, a dielectric layer and an interdigital transducer electrode. The auxiliary layer is formed on the first part of the bottom epitaxial structure. The dielectric layer is formed on the auxiliary layer. The interdigital transducer electrode is formed on the dielectric layer.

In an embodiment, the heterojunction bipolar transistor comprises a top epitaxial structure mesa, a collector electrode, a base electrode and an emitter electrode. The top epitaxial structure mesa comprises a subcollector layer, a collector layer, a base layer and an emitter layer. The subcollector layer is formed on the heterojunction bipolar transistor middle epitaxial structure mesa. The collector layer is formed on the subcollector layer. The base layer is formed on the collector layer. The emitter layer is formed on the base layer. The collector electrode is formed on the subcollector layer. The base electrode is formed on the base layer. The emitter electrode is formed on the emitter layer.

In an embodiment, the subcollector layer is n-type doped and made of InGaAs; the collector layer is n-type doped and made of InGaAs; the base layer is p-type doped and made of InGaAs; and the emitter layer is n-type doped and made of InP; and wherein the heterojunction bipolar transistor is an InP heterojunction bipolar transistor.

In an embodiment, the top epitaxial structure mesa further comprises an emitter ledge layer formed on the base layer, the emitter layer is formed on the emitter ledge layer, wherein the emitter ledge layer is n-type doped and made of InGaAs, and wherein the emitter ledge layer has a base electrode recess, and wherein a bottom of the base electrode recess is the base layer such that the base electrode is formed on the base layer within the base electrode recess.

In an embodiment, the top epitaxial structure mesa further comprises a second etching stop layer, wherein the second etching stop layer is formed on the subcollector layer, the collector layer is formed on the second etching stop layer, wherein the second etching stop layer is made of InP. The second etching stop layer has a collector electrode recess, a bottom of the collector electrode recess is the subcollector layer such that the collector electrode is formed on the subcollector layer within the collector electrode recess.

In an embodiment, the subcollector layer is n-type doped and made of GaAs; the collector layer is n-type doped and made of GaAs; the base layer is p-type doped and made of GaAs; and the emitter layer is n-type doped and made of GaAs; wherein the heterojunction bipolar transistor is an GaAs heterojunction bipolar transistor.

In an embodiment, the top epitaxial structure mesa further comprises an emitter ledge layer formed on the base layer, the emitter layer is formed on the emitter ledge layer, wherein the emitter ledge layer is n-type doped and made of InGaP, and wherein the emitter ledge layer has a base electrode recess, and wherein a bottom of the base electrode recess is the base layer such that the base electrode is formed on the base layer within the base electrode recess.

In an embodiment, the top epitaxial structure mesa further comprises a second etching stop layer, wherein the second etching stop layer is formed on the subcollector layer, the collector layer is formed on the second etching stop layer, wherein the second etching stop layer is made of InGaP. The second etching stop layer has a collector electrode recess, a bottom of the collector electrode recess is the subcollector layer such that the collector electrode is formed on the subcollector layer within the collector electrode recess.

In an embodiment, the heterojunction bipolar transistor further comprises an heterojunction bipolar transistor protection layer, the heterojunction bipolar transistor protection layer covers the exposed surfaces of the top epitaxial structure mesa, the heterojunction bipolar transistor middle epitaxial structure mesa and the third part of the bottom epitaxial structure.

In an embodiment, the bottom epitaxial structure comprises a bottom n-type doped layer. The varactor upper structure comprises a varactor middle epitaxial structure mesa, a varactor top electrode and a varactor bottom electrode, wherein the varactor top electrode is formed on the varactor middle epitaxial structure mesa, wherein the varactor bottom electrode is formed on the second part of the bottom epitaxial structure. The varactor middle epitaxial structure mesa comprises a middle n-type graded doped layer and a middle p-type doped layer. The middle n-type graded doped layer is formed on the bottom epitaxial structure. The middle p-type doped layer is formed on the middle n-type graded doped layer.

In an embodiment, a thickness of the bottom n-type doped layer is between 200 nm and 600 nm, wherein a thickness of the middle n-type graded doped layer is between 100 nm and 2000 nm, and wherein a thickness of the middle p-type doped layer is between 10 nm and 150 nm.

In an embodiment, the bottom n-type doped layer is made of InGaAs; the middle n-type graded doped layer is made of InGaAs; and the middle p-type doped layer is made of InGaAs.

In an embodiment, the varactor middle epitaxial structure mesa further comprises a varactor ledge layer formed on the middle p-type doped layer, wherein the varactor ledge layer is n-type doped and made of InGaAs, and wherein a thickness of the varactor ledge layer is between 1 nm and 60 nm.

In an embodiment, the bottom epitaxial structure further comprises an etching stop layer formed on the bottom n-type doped layer, wherein the etching stop layer is made of InP. The etching stop layer has a varactor bottom electrode recess, wherein a bottom of the varactor bottom electrode recess is the bottom n-type doped layer such that the varactor bottom electrode is formed on the bottom n-type doped layer within the varactor bottom electrode recess.

In an embodiment, the bottom n-type doped layer is made of GaAs; the middle n-type graded doped layer is made of GaAs; and the middle p-type doped layer is made of GaAs.

In an embodiment, the varactor middle epitaxial structure mesa further comprises a varactor ledge layer formed on the middle p-type doped layer, wherein the varactor ledge layer is n-type doped and made of InGaP, and wherein a thickness of the varactor ledge layer is between 1 nm and 60 nm.

In an embodiment, the bottom epitaxial structure further comprises an etching stop layer formed on the bottom n-type doped layer, wherein the etching stop layer is made of InGaP. The etching stop layer has a varactor bottom electrode recess, wherein a bottom of the varactor bottom electrode recess is the bottom n-type doped layer such that the varactor bottom electrode is formed on the bottom n-type doped layer within the varactor bottom electrode recess.

In an embodiment, the varactor upper structure further comprises a varactor protection layer, the varactor protection layer covers the exposed surfaces of the varactor middle epitaxial structure mesa and the second part of the bottom epitaxial structure.

In an embodiment, the semiconductor substrate is made of one material selected from the group consisting of: Si, GaAs, SiC, InP, GaN, AlN and Sapphire.

In addition, the present invention further provides a method for fabricating an integrated structure of acoustic wave device, varactor and heterojunction bipolar transistor, which comprises following steps of: Step G1: forming an acoustic wave device, a varactor and an heterojunction bipolar transistor on a first part, a second part and a third part of a semiconductor substrate respectively, which comprises following steps of: Step G11: forming a bottom epitaxial structure on the semiconductor substrate, wherein the bottom epitaxial structure includes a first part, a second part and a third part of the bottom epitaxial structure formed on the first part, the second part and the third part of the semiconductor substrate respectively; Step G12: forming a middle epitaxial structure on the bottom epitaxial structure, wherein the middle epitaxial structure includes a first part, a second part and a third part of the middle epitaxial structure formed on the first part, the second part and the third part of the bottom epitaxial structure; Step G13: etching the middle epitaxial structure and forming an acoustic wave device upper structure, a varactor upper structure and an heterojunction bipolar transistor middle epitaxial structure mesa on the first part, the second part and the third part of the bottom epitaxial structure respectively, wherein the acoustic wave device comprises the acoustic wave device upper structure and the first part of the bottom epitaxial structure, wherein the varactor comprises the varactor upper structure and the second part of the bottom epitaxial structure, wherein the heterojunction bipolar transistor middle epitaxial structure mesa is formed by etching the third part of the middle epitaxial structure; and Step G14: forming an heterojunction bipolar transistor on the heterojunction bipolar transistor middle epitaxial structure mesa; wherein the integrated structure of the acoustic wave device, the varactor and the heterojunction bipolar transistor formed on the same the semiconductor substrate is capable of reducing the module size, optimizing the impedance matching, and reducing the signal loss between the heterojunction bipolar transistor, the varactor and the acoustic wave device.

In an embodiment, the Step G14comprises following steps of: forming a top epitaxial structure mesa on the heterojunction bipolar transistor middle epitaxial structure mesa, which comprises following steps of: forming a subcollector layer on the heterojunction bipolar transistor middle epitaxial structure mesa; forming a collector layer on the subcollector layer; forming a base layer on the collector layer; forming an emitter layer on the base layer; defining an emitter layer etching area, and etching the emitter layer within the emitter layer etching area; defining a base layer etching area, and etching the base layer within the base layer etching area; defining a collector layer etching area, and etching the collector layer within the collector layer etching area; and defining a subcollector layer etching area, and etching the subcollector layer within the subcollector layer etching area, wherein the top epitaxial structure mesa comprises the subcollector layer, the collector layer, the base layer and the emitter layer; forming an emitter electrode on the emitter layer; forming a base electrode on the base layer; and forming a collector electrode on the subcollector layer, wherein the heterojunction bipolar transistor comprises the top epitaxial structure mesa, the emitter electrode, the base electrode and the collector electrode.

In an embodiment, the subcollector layer is n-type doped and made of InGaAs; the collector layer is n-type doped and made of InGaAs; the base layer is p-type doped and made of InGaAs; and the emitter layer is n-type doped and made of InP; and wherein the heterojunction bipolar transistor is an InP heterojunction bipolar transistor.

In an embodiment, the Step G14further comprises following steps of: forming an emitter ledge layer on the base layer, wherein the emitter layer is formed on the emitter ledge layer, wherein the emitter ledge layer is n-type doped and made of InGaAs, and defining an emitter ledge layer etching area, and etching the emitter ledge layer within the emitter ledge layer etching area to form a base electrode recess, wherein a bottom of the base electrode recess is the base layer such that the base electrode is formed on the base layer within the base electrode recess, wherein the top epitaxial structure mesa comprises the subcollector layer, the collector layer, the base layer, the emitter ledge layer and the emitter layer.

In an embodiment, the Step G14further comprises following steps of: forming a second etching stop layer on the subcollector layer, wherein the collector layer is formed on the second etching stop layer, wherein the second etching stop layer is made of InP; and defining a second etching stop layer etching area, and etching the second etching stop layer within the second etching stop layer etching area to form a collector electrode recess of the second etching stop layer, wherein a bottom of the collector electrode recess is the subcollector layer such that the collector electrode is formed on the subcollector layer within the collector electrode recess, wherein the top epitaxial structure mesa comprises the subcollector layer, the second etching stop layer, the collector layer, the base layer and the emitter layer.

In an embodiment, the subcollector layer is n-type doped and made of GaAs; the collector layer is n-type doped and made of GaAs; the base layer is p-type doped and made of GaAs; and the emitter layer is n-type doped and made of GaAs; wherein the heterojunction bipolar transistor is an GaAs heterojunction bipolar transistor.

In an embodiment, the Step G14further comprises following steps of: forming an emitter ledge layer on the base layer, wherein the emitter layer is formed on the emitter ledge layer, wherein the emitter ledge layer is n-type doped and made of InGaP, and defining an emitter ledge layer etching area, and etching the emitter ledge layer within the emitter ledge layer etching area and to form a base electrode recess, wherein a bottom of the base electrode recess is the base layer such that the base electrode is formed on the base layer within the base electrode recess, wherein the top epitaxial structure mesa comprises the subcollector layer, the collector layer, the base layer, the emitter ledge layer and the emitter layer.

In an embodiment, the Step G14further comprises following steps of: forming a second etching stop layer on the subcollector layer, wherein the collector layer is formed on the second etching stop layer, wherein the second etching stop layer is made of InGaP; and defining a second etching stop layer etching area, and etching the second etching stop layer within the second etching stop layer etching area to form a collector electrode recess of the second etching stop layer, wherein a bottom of the collector electrode recess is the subcollector layer such that the collector electrode is formed on the subcollector layer within the collector electrode recess, wherein the top epitaxial structure mesa comprises the subcollector layer, the second etching stop layer, the collector layer, the base layer and the emitter layer.

In an embodiment, the Step G14further comprises a following step of: forming an heterojunction bipolar transistor protection layer, wherein the heterojunction bipolar transistor protection layer covers the exposed surfaces of the third part of the bottom epitaxial structure, the heterojunction bipolar transistor middle epitaxial structure mesa and the top epitaxial structure mesa, wherein the heterojunction bipolar transistor comprises the top epitaxial structure mesa, the emitter electrode, the base electrode, the collector electrode and the heterojunction bipolar transistor protection layer.

In an embodiment, in the Step G13, the first part and the second part of the middle epitaxial structure are etched such that (a) an acoustic wave device middle epitaxial structure mesa and a varactor middle epitaxial structure mesa are formed on the first part and the second part of the bottom epitaxial structure respectively or (b) the middle epitaxial structure on the first part of the bottom epitaxial structure is etched and removed and a varactor middle epitaxial structure mesa is formed on the second part of the bottom epitaxial structure.

In an embodiment, the Step G11comprises a following step of: forming a bottom n-type doped layer on the semiconductor substrate, wherein the bottom epitaxial structure comprises the bottom n-type doped layer; wherein the Step G12comprises following steps of: forming a middle n-type graded doped layer on the bottom epitaxial structure; and forming a middle p-type doped layer on the middle n-type graded doped layer, wherein the middle epitaxial structure comprises the middle n-type graded doped layer and the middle p-type doped layer; wherein the Step G13comprises following steps of: defining a middle p-type doped layer etching area, and etching the middle p-type doped layer within the middle p-type doped layer etching area; defining a middle n-type graded doped layer etching area, and etching the middle n-type graded doped layer within the middle n-type graded doped layer etching area, thereby the varactor middle epitaxial structure mesa is formed, wherein the varactor middle epitaxial structure mesa comprises the middle n-type graded doped layer and the middle p-type doped layer on the second part of the bottom epitaxial structure; forming a varactor top electrode on the varactor middle epitaxial structure mesa; and forming a varactor bottom electrode on the second part of the bottom epitaxial structure, wherein the varactor upper structure comprises the varactor middle epitaxial structure mesa, the varactor top electrode and the varactor bottom electrode.

In an embodiment, a thickness of the bottom n-type doped layer is between 200 nm and 600 nm, wherein a thickness of the middle n-type graded doped layer is between 100 nm and 2000 nm, and wherein a thickness of the middle p-type doped layer is between 10 nm and 150 nm.

In an embodiment, the bottom n-type doped layer is made of InGaAs; the middle n-type graded doped layer is made of InGaAs; and the middle p-type doped layer is made of InGaAs.

In an embodiment, the Step G12further comprises a following step of: forming a varactor ledge layer on the middle p-type doped layer, wherein the varactor ledge layer is n-type doped and made of InGaAs, wherein a thickness of the varactor ledge layer is between 1 nm and 60 nm; and wherein the Step G13further comprises a following step of: defining a varactor ledge layer etching area, and etching the varactor ledge layer within the varactor ledge layer etching area; wherein the varactor middle epitaxial structure mesa comprises the middle n-type graded doped layer, the middle p-type doped layer and the varactor ledge layer on the second part of the bottom epitaxial structure.

In an embodiment, the Step G11further comprises following steps of: forming an etching stop layer on the bottom n-type doped layer, wherein the bottom epitaxial structure comprises the bottom n-type doped layer and the etching stop layer, wherein the etching stop layer is made of InP; and etching the etching stop layer to form a varactor bottom electrode recess, wherein a bottom of the varactor bottom electrode recess is the bottom n-type doped layer such that the varactor bottom electrode is formed on the bottom n-type doped layer within the varactor bottom electrode recess.

In an embodiment, the bottom n-type doped layer is made of GaAs; the middle n-type graded doped layer is made of GaAs; and the middle p-type doped layer is made of GaAs.

In an embodiment, the Step G12further comprises a following step of: forming a varactor ledge layer on the middle p-type doped layer, wherein the varactor ledge layer is n-type doped and made of InGaP, wherein a thickness of the varactor ledge layer is between 1 nm and 60 nm; and wherein the Step G13further comprises a following step of: defining a varactor ledge layer etching area, and etching the varactor ledge layer within the varactor ledge layer etching area; wherein the varactor middle epitaxial structure mesa comprises the middle n-type graded doped layer, the middle p-type doped layer and the varactor ledge layer on the second part of the bottom epitaxial structure.

In an embodiment, the Step G11further comprises following steps of: forming an etching stop layer on the bottom n-type doped layer, wherein the bottom epitaxial structure comprises the bottom n-type doped layer and the etching stop layer, wherein the etching stop layer is made of InGaP; and etching the etching stop layer to form a varactor bottom electrode recess, wherein a bottom of the varactor bottom electrode recess is the bottom n-type doped layer such that the varactor bottom electrode is formed on the bottom n-type doped layer within the varactor bottom electrode recess.

In an embodiment, the Step G13further comprises a following step of: forming a varactor protection layer, wherein the varactor protection layer covers the exposed surfaces of the second part of the bottom epitaxial structure and the varactor middle epitaxial structure mesa, wherein the varactor upper structure comprises the varactor middle epitaxial structure mesa, the varactor top electrode, the varactor bottom electrode and the varactor protection layer.

In an embodiment, in the Step G13the varactor middle epitaxial structure mesa on the first part of the bottom epitaxial structure is etched and removed; and wherein the Step G13further comprises following steps of: forming an auxiliary layer on the first part of the bottom epitaxial structure; forming a dielectric layer on the auxiliary layer; and forming an interdigital transducer electrode on the dielectric layer, wherein the acoustic wave device upper structure comprises the auxiliary layer, the dielectric layer and the interdigital transducer electrode.

In an embodiment, in the Step G13the acoustic wave device middle epitaxial structure mesa and the varactor middle epitaxial structure mesa are formed on the first part and the second part of the bottom epitaxial structure respectively; wherein the Step G13comprises following steps of: forming an acoustic wave device protection layer, wherein the acoustic wave device protection layer covers the exposed surfaces of the first part of the bottom epitaxial structure and the acoustic wave device middle epitaxial structure mesa, and wherein the acoustic wave device protection layer covers the acoustic wave device middle epitaxial structure mesa to form an acoustic wave device protection layer mesa; forming an acoustic wave resonance structure on the acoustic wave device protection layer mesa, which comprises following steps of: forming an acoustic wave device bottom electrode on the acoustic wave device protection layer mesa; forming a dielectric layer on the acoustic wave device bottom electrode; and forming an acoustic wave device top electrode on the dielectric layer, wherein the acoustic wave resonance structure comprises the acoustic wave device bottom electrode, the dielectric layer and the acoustic wave device top electrode; and etching the acoustic wave device middle epitaxial structure mesa to form an acoustic wave device protection layer recess, wherein at least one middle epitaxial structure etching solution contacts with the acoustic wave device middle epitaxial structure mesa and etches and removes the acoustic wave device middle epitaxial structure mesa, thereby a top and a bottom of the acoustic wave device protection layer recess are the acoustic wave device protection layer and the bottom epitaxial structure respectively, wherein the acoustic wave device upper structure comprises the acoustic wave device protection layer and the acoustic wave resonance structure; wherein the Step G1further comprises a following step of: etching the bottom epitaxial structure below the acoustic wave device protection layer recess to form a bottom epitaxial structure recess, wherein a bottom of the bottom epitaxial structure recess is the bottom epitaxial structure or the semiconductor substrate, wherein at least one bottom epitaxial structure etching solution contacts with a top surface of the bottom epitaxial structure and the acoustic wave device protection layer recess, the at least one bottom epitaxial structure etching solution is uniformly distributed on the top surface of the bottom epitaxial structure through the acoustic wave device protection layer recess so as to uniformly etch part of the bottom epitaxial structure below the acoustic wave device protection layer recess to form the bottom epitaxial structure recess, and thereby prevents the side etching phenomenon during the etching, wherein the acoustic wave device protection layer recess is communicated with the bottom epitaxial structure recess, and the acoustic wave device protection layer recess and the bottom epitaxial structure recess have a boundary therebetween and the boundary is extended from the top surface of the bottom epitaxial structure, wherein a gap between the acoustic wave device protection layer and the bottom of the bottom epitaxial structure recess is increased by the communication of the acoustic wave device protection layer recess and the bottom epitaxial structure recess, so as to avoid the contact of the acoustic wave device protection layer and the bottom of the bottom epitaxial structure recess when the acoustic wave device is affected by stress such that the acoustic wave device protection layer is bended downwardly.

In an embodiment, the acoustic wave device protection layer recess has an opening smaller than or equal to that of the bottom epitaxial structure recess.

In an embodiment, the Step G12comprises following steps of: forming a middle n-type graded doped layer on the bottom epitaxial structure; and forming a middle p-type doped layer on the middle n-type graded doped layer, wherein the middle epitaxial structure comprises the middle n-type graded doped layer and the middle p-type doped layer; and wherein the Step G13comprises following steps of: defining a middle p-type doped layer etching area, and etching the middle p-type doped layer within the middle p-type doped layer etching area; and defining a middle n-type graded doped layer etching area, and etching the middle n-type graded doped layer within the middle n-type graded doped layer etching area; wherein the varactor middle epitaxial structure mesa comprises the middle n-type graded doped layer and the middle p-type doped layer on the second part of the bottom epitaxial structure; and wherein the acoustic wave device middle epitaxial structure mesa comprises (a) the middle n-type graded doped layer on the first part of the bottom epitaxial structure; or (b) the middle n-type graded doped layer and the middle p-type doped layer on the first part of the bottom epitaxial structure.

In an embodiment, the Step G12further comprises a following step of: forming a varactor ledge layer on the middle p-type doped layer; wherein the Step G13further comprises a following step of: defining a varactor ledge layer etching area, and etching the varactor ledge layer within the varactor ledge layer etching area; wherein the varactor middle epitaxial structure mesa comprises the middle n-type graded doped layer, the middle p-type doped layer and the varactor ledge layer on the second part of the bottom epitaxial structure; and wherein the acoustic wave device middle epitaxial structure mesa comprises (a) the middle n-type graded doped layer on the first part of the bottom epitaxial structure; (b) the middle n-type graded doped layer and the middle p-type doped layer on the first part of the bottom epitaxial structure; or (c) the middle n-type graded doped layer, the middle p-type doped layer and the varactor ledge layer on the first part of the bottom epitaxial structure.

In an embodiment, the semiconductor substrate is made of one material selected from the group consisting of: Si, GaAs, SiC, InP, GaN, AN and Sapphire.

For further understanding the characteristics and effects of the present invention, some preferred embodiments referred to drawings are in detail described as follows

DETAILED DESCRIPTIONS OF PREFERRED EMBODIMENTS

Please refer toFIG. 1, the cross-sectional view of an embodiment of the integrated structure of power amplifier and acoustic wave device of the present invention, the integrated structure comprises: a compound semiconductor epitaxial substrate10, a power amplifier upper structure21and a film bulk acoustic resonator51. The compound semiconductor epitaxial substrate10includes a compound semiconductor substrate12and an epitaxial structure13formed on the compound semiconductor substrate12. The power amplifier upper structure21is formed on a first side101of the compound semiconductor epitaxial substrate10, wherein the first side101of the compound semiconductor epitaxial substrate10and the power amplifier upper structure21form a power amplifier20. The film bulk acoustic resonator51is formed on a second side102of the compound semiconductor epitaxial substrate10, wherein the second side102of the compound semiconductor epitaxial substrate10and the film bulk acoustic resonator51form an acoustic wave device50. The integrated structure1of the power amplifier20and the acoustic wave device50on the same the compound semiconductor epitaxial substrate10is capable of reducing the component size, optimizing the impedance matching, and reducing the signal loss between the power amplifier20and the acoustic wave device50.

The film bulk acoustic resonator51comprises: a supporting layer61and a bulk acoustic resonator structure60. The supporting layer61is formed on the compound semiconductor epitaxial substrate10, wherein the supporting layer61has a supporting layer recess612on the bottom of the supporting layer61, and the supporting layer61has an upwardly protruding supporting layer mesa611right above the supporting layer recess612. The compound semiconductor epitaxial substrate10has a substrate recess15on the top of the compound semiconductor epitaxial substrate10, and the substrate recess15is located right below the supporting layer recess612. The supporting layer recess612is communicated with the substrate recess15, and the supporting layer recess612and the substrate recess15have a boundary103therebetween and the boundary103is the extended from the top surface of the compound semiconductor epitaxial substrate10. The bulk acoustic resonator structure60is formed on the supporting layer61, wherein the bulk acoustic resonator structure60includes: a bottom electrode601, a dielectric layer602and a top electrode603. The bottom electrode601is formed on one end of the supporting layer61, where the bottom electrode601is formed on and at least extended along the supporting layer mesa611. The dielectric layer602is formed at least on the bottom electrode601above the supporting layer mesa611. In the embodiment ofFIG. 1, the dielectric layer602is formed on both the bottom electrode601and the supporting layer61, and the dielectric layer602is also formed on the bottom electrode601above the supporting layer mesa611. Please also refer toFIG. 1A, which shows the cross-sectional view of another embodiment of the integrated structure of power amplifier and acoustic wave device of the present invention. The main structure inFIG. 1Ais basically the same as the structure shown inFIG. 1, except that the dielectric layer602is formed on the bottom electrode601above the supporting layer mesa611and also formed on a small part of the supporting layer61above the supporting layer mesa611. The top electrode603is formed on the other end with respect to the bottom electrode601, where the top electrode603is formed on the dielectric layer602or formed on both the dielectric layer602and the supporting layer61, and the top electrode603is formed on and at least extended along the dielectric layer602above the supporting layer mesa611. In the embodiment ofFIG. 1, the top electrode603is formed on the dielectric layer602, while in embodiment ofFIG. 1A, the top electrode603is formed on both the dielectric layer602and the supporting layer61. The top electrode603and the bottom electrode601are not electrically connected. The gap between the supporting layer mesa611and the bottom of the substrate recess15is increased by the communication of the supporting layer recess612and the substrate recess15, so as to avoid the contact of the supporting layer mesa611and the bottom of the substrate recess15when the film bulk acoustic resonator51is affected by stress such that the supporting layer mesa611is bended downwardly.

In an embodiment, the integrated structure1of power amplifier20and acoustic wave device50is not limited to integrating one single power amplifier20and one single acoustic wave device50. In another embodiment, the integrated structure1of power amplifier20and acoustic wave device50may integrates one single power amplifier20and plural acoustic wave devices50, plural power amplifiers20and one single acoustic wave device50or plural power amplifiers20and plural acoustic wave devices50.

In an embodiment, the integrated structure1of power amplifier20and acoustic wave device50may also integrate other components, such as metal-insulator-metal capacitor, resistor, inductor or diode, on the same the compound semiconductor epitaxial substrate10, wherein the components may be directly or indirectly electrically connected. In another embodiment, the power amplifier20and the acoustic wave device50may be directly electrically connected. In other embodiment, the power amplifier20may be indirectly electrically connected with the acoustic wave device50through other component(s) on the integrated structure.

In an embodiment, the application of the acoustic wave device50may be a filter. Usually plural acoustic wave devices50are in series and/or in parallel in the combination of circuit to form a filter which may filter the signal. In another embodiment, the signal may flow into the filter formed by the acoustic wave devices50to be filtered, and then the filtered signal flows into the power amplifier20to be amplified. In other embodiment, the signal may flow into the power amplifier20to be amplified, and then the amplified signal flows into the filter formed by the acoustic wave devices50to be filtered. In one another embodiment, the integrated structure may integrate one power amplifier20and two filters formed by acoustic wave devices50. The signal may firstly flow into the first filter formed by acoustic wave devices50to be filtered, and then flow into the power amplifier20to be amplified, and finally flow into the second filter formed by acoustic wave devices50to be filtered.

In one embodiment, the application of the acoustic wave device50may be a mass sensing device, a biomedical sensing device, an UV sensing device, a pressure sensing device or a temperature sensing device.

In an embodiment, the compound semiconductor substrate12may be made of GaAs, SiC, InP, GaN, AlN or Sapphire.

In an embodiment, the function of the supporting layer61may be the supporting for the film bulk acoustic resonator51for preventing the film bulk acoustic resonator51from collapsing. The supporting layer61also may be the seed layer for the bottom electrode601and the dielectric layer602for improving the crystalline quality. In an embodiment, the supporting layer61is made of SiNxor AlN. The supporting layer61is formed on the epitaxial structure13by molecular beam epitaxy (MBE), sputtering or chemical vapor deposition (CVD).

In an embodiment, the bottom electrode601is needed to have a lower roughness and resistivity for benefit the preferable crystal growth axis. In an embodiment, the bottom electrode601is made of Mo, Pt, Al, Au, W or Ru. The bottom electrode601is formed on the supporting layer61by evaporation or sputtering.

In an embodiment, the dielectric layer602is made of AlN, monocrystalline SiO2, ZnO, HfO2, barium strontium titanate (BST) or lead zirconate titanate (PZT), and is formed on the bottom electrode601or formed on both the electrode601and the supporting layer61by epitaxial growth or sputtering. The selection of the materials of the dielectric layer602is associated with the application. AlN is a high acoustic wave velocity material (12000 m/s) and is suitable for high frequency application, and after the formation of the micro structure of the material, it has good physical and chemical stability and its properties are not easily to be influenced by the circumstance. ZnO may be formed under lower temperature and it has an acoustic wave velocity 6000 m/s. Its electromechanical coupling coefficient is higher (8.5%) and it is suitable for the application of broadband filter. However when forming ZnO, the concentration of oxygen vacancies in ZnO is not easily controlled, yet it is easily influenced by the humidity and oxygen of the circumstance. Both barium strontium titanate (BST) and lead zirconate titanate (PZT) are ferroelectric materials. Their dielectric constant may vary under external electric field. Hence, they are suitable for the application of acoustic wave device with tunable frequency within dozen MHz range of frequencies. Both barium strontium titanate (BST) and lead zirconate titanate (PZT) need to be polarized under high voltage electric field in order to obtain their piezoelectric characteristics. Lead zirconate titanate (PZT) has higher electromechanical coupling coefficient, however it contains lead.

In an embodiment, the top electrode603is needed to have a lower resistivity for reducing power loss so as to reduce the insertion loss. In an embodiment, the top electrode603may be made of Mo, Pt, Al, Au, W or Ru. The top electrode603is formed on the dielectric layer602or is formed on both the dielectric layer602and the supporting layer61by evaporation or sputtering.

In an embodiment, the bottom electrode601is made of Mo or Pt, while the dielectric layer602is made of AlN. The Mo of the bottom electrode601may be etched by Lithography and Lift-off process. And the AlN of the dielectric layer602may be etched by inductively coupled plasma (ICP) process with CF4plasma.

In an embodiment, the depth of the substrate recess15is between 50 nm and 10000 nm.

In an embodiment, the depth of the supporting layer recess612is between 10 nm and 3500 nm. In another embodiment, the optimized depth of the supporting layer recess612is between 10 nm and 1500 nm.

Please refer toFIG. 1B, which shows the cross-sectional view of another embodiment of the integrated structure of power amplifier and acoustic wave device of the present invention. The main structure inFIG. 1Bis basically the same as the structure shown inFIG. 1, except that the film bulk acoustic resonator51further comprises at least one etching recess62. The cross-sectional direction ofFIG. 1Bis orthogonal to that ofFIG. 1. And there is only the acoustic wave device50at the position of the cross-sectional direction ofFIG. 1B, hence there is no power amplifier20shown inFIG. 1B. One end of the at least one etching recess62is communicated with the supporting layer recess612, the other end of the at least one etching recess62penetrates the supporting layer61or penetrates both the supporting layer61and the bulk acoustic resonator structure60such that the at least one etching recess62is communicated with the outside, and thereby the supporting layer recess612is communicated with the outside.

Please refer to the embodiment ofFIGS. 1 and 1B, the present invention provides a fabrication method for integrated structure of power amplifier and acoustic wave device. The fabrication method for the embodiment ofFIGS. 1 and 1Bcomprises following steps of: Step A1: forming an epitaxial structure13on a compound semiconductor substrate12to form a compound semiconductor epitaxial substrate10; Step A2: forming a power amplifier upper structure21on a first side101of the compound semiconductor epitaxial substrate10to form a power amplifier20; and Step A3: forming a film bulk acoustic resonator51on a second side102of the compound semiconductor epitaxial substrate10to form an acoustic wave device50. The integrated structure1of the power amplifier20and the acoustic wave device50on the same the compound semiconductor epitaxial substrate10is capable of reducing the component size, optimizing the impedance matching, and reducing the signal loss between the power amplifier20and the acoustic wave device50. Step A3includes following steps of: Step A31: (Please referring toFIG. 1C) forming a top sacrificial layer63on the compound semiconductor epitaxial substrate10; Step A32: defining a top sacrificial layer etching area, and etching to remove the top sacrificial layer63within the top sacrificial layer etching area to form a top sacrificial layer mesa632, such that the compound semiconductor epitaxial substrate10within the top sacrificial layer etching area is exposed; Step A33: (Please referring toFIG. 1D) forming a supporting layer61on the top sacrificial layer63and the compound semiconductor epitaxial substrate10, wherein the supporting layer61has a supporting layer mesa611right above the top sacrificial layer mesa632; Step A34: forming a bulk acoustic resonator structure60on the supporting layer61(Please referring toFIGS. 1E and 1F, wherein the cross-sectional direction ofFIG. 1Fis orthogonal to that ofFIG. 1E, and there is only the acoustic wave device50at the position of the cross-sectional direction ofFIG. 1F, hence there is no power amplifier20shown inFIG. 1F), which includes following steps of: Step A341: forming a bottom electrode601on one end of the supporting layer61, where the bottom electrode601is formed on and at least extended along the supporting layer mesa611; Step A342: forming a dielectric layer602, wherein the dielectric layer602is formed at least on the bottom electrode601above the supporting layer mesa611; and Step A343: forming a top electrode603, wherein the top electrode603is formed on the other end with respect to the bottom electrode601, where the top electrode603is formed on the dielectric layer602or formed on both the dielectric layer602and the supporting layer61, and the top electrode603is formed on and at least extended along the dielectric layer602above the supporting layer mesa611; Step A35: (Please referring toFIG. 1G) defining at least one recess etching area, and etching to remove the supporting layer61within the at least one recess etching area or etching to remove the supporting layer61and the bulk acoustic resonator structure60within the at least one recess etching area such that the etching stops at the top sacrificial layer mesa632and/or the compound semiconductor epitaxial substrate10to form at least one etching recess62, thereby part of the top sacrificial layer mesa632is exposed; Step A36: (Please referring toFIG. 1H) etching to remove the top sacrificial layer mesa632to form a supporting layer recess612, wherein at least one top sacrificial layer etching solution contacts with the top sacrificial layer mesa632via the at least one etching recess62and etches to remove the top sacrificial layer mesa632, thereby the top and the bottom of the supporting layer recess612are the supporting layer61and the compound semiconductor epitaxial substrate10respectively; and Step A37: etching to remove part of the compound semiconductor epitaxial substrate10below the supporting layer recess612to form a substrate recess15(Please referring toFIGS. 1 and 1B, wherein the cross-sectional direction ofFIG. 1Bis orthogonal to that ofFIG. 1, and there is only the acoustic wave device50at the position of the cross-sectional direction ofFIG. 1B, hence there is no power amplifier20shown inFIG. 1B), wherein the bottom of the substrate recess15is the compound semiconductor epitaxial substrate10, wherein at least one substrate recess etching solution contacts with the top surface of the compound semiconductor epitaxial substrate10via the at least one etching recess62and the supporting layer recess612, the at least one substrate recess etching solution is uniformly distributed on the top surface of the compound semiconductor epitaxial substrate10through the supporting layer recess612so as to uniformly etch part of the compound semiconductor epitaxial substrate10below the supporting layer recess612to form the substrate recess15, and thereby prevents the side etching phenomenon during the etching, wherein the supporting layer recess612is communicated with the substrate recess15, and the supporting layer recess612and the substrate recess15have a boundary103therebetween and the boundary103is the extended from the top surface of the compound semiconductor epitaxial substrate10, wherein the gap between the supporting layer mesa611and the bottom of the substrate recess15is increased by the communication of the supporting layer recess612and the substrate recess15, so as to avoid the contact of the supporting layer mesa611and the bottom of the substrate recess15when the film bulk acoustic resonator51is affected by stress such that the supporting layer mesa611is bended downwardly.

Please refer toFIG. 1I, which shows the partial enlarged cross-sectional view of an embodiment of the integrated structure of power amplifier and acoustic wave device of the present invention. In the embodiment ofFIG. 1I, the supporting layer recess612has an opening smaller than that of the substrate recess15. Please refer toFIG. 1J, which shows the partial enlarged cross-sectional view of another embodiment of the integrated structure of power amplifier and acoustic wave device of the present invention. In the embodiment ofFIG. 1J, the supporting layer recess612has an opening almost equal to that of the substrate recess15.

Please refer toFIGS. 1K, 1L, 1M and 1N, which show the top views of the relative position of the etching recess and the supporting layer mesa in the embodiments of the integrated structure of power amplifier and acoustic wave device of the present invention. In the embodiment ofFIG. 1K, the integrated structure1of power amplifier20and acoustic wave device50has two etching recess62with long strip opening. The two etching recesses62are located on two opposite sides of the supporting layer mesa611respectively. And the etching recesses62penetrate the supporting layer61(not shown inFIG. 1K), and thereby the supporting layer recess612(not shown inFIG. 1K) is communicated with the outside. In the embodiment ofFIG. 1L, the integrated structure1of power amplifier20and acoustic wave device50has two etching recess62with long strip opening. The two etching recesses62are located on two opposite sides of the supporting layer mesa611respectively. (part of the etching recesses62are within the supporting layer mesa611, the rest part of the etching recesses62are outside the supporting layer mesa611) And the etching recesses62penetrate the supporting layer61(not shown inFIG. 1L) and the dielectric layer602. In the embodiment ofFIG. 1M, the integrated structure1of power amplifier20and acoustic wave device50has two etching recess62with long strip opening. The two etching recesses62are located respectively on two opposite sides of the supporting layer mesa611within the supporting layer mesa611. And the etching recesses62penetrate the supporting layer61(not shown inFIG. 1M), the bottom electrode601, the dielectric layer602and the top electrode603. In the embodiment ofFIG. 1N, the integrated structure1of power amplifier20and acoustic wave device50has four etching recess62with square opening. The four etching recesses62are located on four corners of the supporting layer mesa611respectively. And the etching recesses62penetrate the supporting layer61(not shown inFIG. 1N). The amount of the etching recesses62is not limited to one, two, three, four or more. The etching recesses62may locate on other position and should not be limited byFIG. 1K, 1L, 1M or 1N.

In one embodiment, the power amplifier20may be a heterojunction bipolar transistor (HBT). In another embodiment, the power amplifier20may be a field effect transistor (FET), a high electron mobility transistor (HEMT) or a pseudomorphic high electron mobility transistor (pHEMT). In an embodiment, the power amplifier20may be any other type of amplifier which may be formed on the compound semiconductor substrate12.

Please refer toFIG. 2, which shows the cross-sectional view of another embodiment of the integrated structure of power amplifier and acoustic wave device of the present invention. The main structure inFIG. 2is basically the same as the structure shown inFIG. 1, except that the power amplifier20is a heterojunction bipolar transistor30(HBT). The epitaxial structure13includes: a subcollector layer31and a collector layer33. The subcollector layer31formed on the compound semiconductor substrate12; the collector layer33formed on the subcollector layer31. The first side101of the compound semiconductor epitaxial substrate10further comprises a collector recess331, and the bottom of the collector recess331is the subcollector layer31. The power amplifier upper structure21includes: a base layer34, an emitter ledge layer35, an emitter layer36, a base electrode38, an emitter electrode39and a collector electrode37. The base layer34is formed on the collector layer33; the emitter ledge layer35is formed on the base layer34; the emitter layer36is formed on the emitter ledge layer35; the base electrode38is formed on the emitter ledge layer35; the emitter electrode39is formed on the emitter layer36; the collector electrode37is formed on the subcollector layer31within the collector recess331. The first side101of the compound semiconductor epitaxial substrate10includes: the compound semiconductor substrate12, the subcollector layer31, the collector layer33and the collector recess331. The first side101of the compound semiconductor epitaxial substrate10and the power amplifier upper structure21form the heterojunction bipolar transistor30. The acoustic wave device50inFIG. 2is basically the same as the acoustic wave device50inFIG. 1. The substrate recess15of the second side102of the compound semiconductor epitaxial substrate10is peripherally surrounded by the collector layer33, and the bottom of the substrate recess15is the subcollector layer31. The second side102of the compound semiconductor epitaxial substrate10and the film bulk acoustic resonator51form the acoustic wave device50.

In one embodiment, the collector layer33is made of GaAs. The thickness of the collector layer33is between 500 nm and 3000 nm.

In another embodiment, the base layer34is made of GaAs. The thickness of the base layer34is between 60 nm and 100 nm.

In one embodiment, the subcollector layer31is made of GaAs and is formed on the compound semiconductor substrate12by epitaxial growth.

Please refer toFIG. 2A, which shows the cross-sectional view of another embodiment of the integrated structure of power amplifier and acoustic wave device of the present invention. The main structure inFIG. 2Ais basically the same as the structure shown inFIG. 2, except that the base electrode38is formed on the base layer34. In one other embodiment, the base electrode38may be formed on both the base layer34and the emitter ledge layer35. In other embodiments having basically the same structure as the embodiment inFIG. 2, the base electrode38may be formed on the base layer34and/or the emitter ledge layer35.

Please refer toFIG. 2B, which shows the cross-sectional view of another embodiment of the integrated structure of power amplifier and acoustic wave device of the present invention. The main structure inFIG. 2Bis basically the same as the structure shown inFIG. 2, except that the heterojunction bipolar transistor30further comprises the supporting layer61. The supporting layer61plays a role of protection, and may prevent the heterojunction bipolar transistor30from oxidation or corrosion. In other embodiments having basically the same structure as the embodiment inFIG. 2, the power amplifier20may also include the supporting layer61.

Please refer toFIG. 2C, which shows the cross-sectional view of another embodiment of the integrated structure of power amplifier and acoustic wave device of the present invention. The main structure inFIG. 2Cis basically the same as the structure shown inFIG. 2, except that the film bulk acoustic resonator51further comprises at least one etching recess62. The cross-sectional direction ofFIG. 2Cis orthogonal to that ofFIG. 2. And there is only the acoustic wave device50at the position of the cross-sectional direction ofFIG. 2C, hence there is no power amplifier20shown inFIG. 2C. One end of the at least one etching recess62is communicated with the supporting layer recess612, the other end of the at least one etching recess62penetrates the supporting layer61or penetrates both the supporting layer61and the bulk acoustic resonator structure60such that the at least one etching recess62is communicated with the outside, and thereby the supporting layer recess612is communicated with the outside. The feature of the at least one etching recess62of the embodiment inFIG. 2Cis basically the same as that of the embodiment inFIG. 1B. The power amplifier20may also include the supporting layer61, or may choose not to include the supporting layer61.

Please refer toFIG. 2D, which shows the cross-sectional view of another embodiment of the integrated structure of power amplifier and acoustic wave device of the present invention. The main structure inFIG. 2Dis basically the same as the structure shown inFIG. 2B, except that the epitaxial structure13further comprises an etching stop layer32; wherein the etching stop layer32is formed on the subcollector layer31; and the collector layer33is formed on the etching stop layer32. The bottom of the collector recess331is the subcollector layer31, the collector electrode37is formed on the subcollector layer31within the collector recess331. The substrate recess15is peripherally surrounded by the collector layer33and the etching stop layer32, and the bottom of the substrate recess15is the subcollector layer31. The power amplifier20may also include the supporting layer61, or may choose not to include the supporting layer61.

In an embodiment, the etching stop layer32is made of InGaP. In one embodiment, the thickness of the etching stop layer32is between 5 nm and 1000 nm. In another embodiment, the optimized thickness of the etching stop layer32is 20 nm.

Please refer toFIG. 2E, which shows the cross-sectional view of another embodiment of the integrated structure of power amplifier and acoustic wave device of the present invention. The main structure inFIG. 2Eis basically the same as the structure shown inFIG. 2D, except that the film bulk acoustic resonator51further comprises at least one etching recess62. The cross-sectional direction ofFIG. 2Eis orthogonal to that ofFIG. 2D. And there is only the acoustic wave device50at the position of the cross-sectional direction ofFIG. 2E, hence there is no power amplifier20shown inFIG. 2E. One end of the at least one etching recess62is communicated with the supporting layer recess612, the other end of the at least one etching recess62penetrates the supporting layer61or penetrates both the supporting layer61and the bulk acoustic resonator structure60such that the at least one etching recess62is communicated with the outside, and thereby the supporting layer recess612is communicated with the outside. The feature of the at least one etching recess62of the embodiment inFIG. 2Eis basically the same as that of the embodiment inFIG. 1B. The power amplifier20may also include the supporting layer61, or may choose not to include the supporting layer61.

Please refer toFIGS. 2B and 2C. The cross-sectional direction ofFIG. 2Cis orthogonal to that ofFIG. 2B. And there is only the acoustic wave device50at the position of the cross-sectional direction ofFIG. 2C, hence there is no power amplifier20shown inFIG. 2C. The present invention provides a fabrication method for integrated structure of power amplifier and acoustic wave device. The fabrication method for the embodiment ofFIGS. 2B and 2Ccomprises following steps of: Step B1: forming an epitaxial structure13on a compound semiconductor substrate12to form a compound semiconductor epitaxial substrate10; Step B2: forming a power amplifier upper structure21on a first side101of the compound semiconductor epitaxial substrate10to form a power amplifier20, wherein the power amplifier20is a heterojunction bipolar transistor30(HBT); and Step B3: forming a film bulk acoustic resonator51on a second side102of the compound semiconductor epitaxial substrate10to form an acoustic wave device50; wherein, the integrated structure1of the power amplifier20and the acoustic wave device50on the same the compound semiconductor epitaxial substrate10is capable of reducing the component size, optimizing the impedance matching, and reducing the signal loss between the power amplifier20and the acoustic wave device50. In this embodiment, Step B1further includes following steps of: Step B11: (Please referring toFIG. 2F) forming a subcollector layer31on the compound semiconductor substrate12; and Step B12: forming a collector layer33on the subcollector layer31. Step B2and Step B3include following steps of: Step B41: (Please referring toFIG. 2H) forming a base layer34on the collector layer33; Step B42: forming an emitter ledge layer35on the base layer34; Step B43: forming an emitter layer36on the emitter ledge layer35; Step B44: (Please referring toFIG. 2I) defining an emitter layer etching area, and etching to remove the emitter layer36within the emitter layer etching area; Step B45: forming a base electrode38on the emitter ledge layer35; Step B46: (Please referring toFIG. 2J) defining an emitter ledge layer etching area, and etching to remove the emitter ledge layer35within the emitter ledge layer etching area; Step B47: defining a base layer etching area, and etching to remove the base layer34within the base layer etching area; Step B48: (Please referring toFIG. 2L) forming a top sacrificial layer63on the compound semiconductor epitaxial substrate10(the collector layer33); Step B49: defining a top sacrificial layer etching area, and etching to remove the top sacrificial layer63within the top sacrificial layer etching area to form a top sacrificial layer mesa632, such that the compound semiconductor epitaxial substrate10(the collector layer33) within the top sacrificial layer etching area is exposed; Step B50: (Please referring toFIGS. 2M and 2N) forming a supporting layer61on the top sacrificial layer63and the compound semiconductor epitaxial substrate10(the collector layer33), wherein the supporting layer61has a supporting layer mesa611right above the top sacrificial layer mesa632; wherein the supporting layer61may also be formed on the base layer34, the emitter ledge layer35, the emitter layer36and the base electrode38, and the supporting layer61may play a role of protection; Step B51: forming a bulk acoustic resonator structure60on the supporting layer61, which includes following steps of: Step B511: (Please referring toFIG. 20) forming a bottom electrode601on one end of the supporting layer61, where the bottom electrode601is formed on and at least extended along the supporting layer mesa611; and forming an emitter electrode39on the emitter layer36(the emitter electrode39may choose to be formed on the emitter layer36through other step); Step B512: (Please referring toFIG. 2P) forming a dielectric layer602, wherein the dielectric layer602is formed at least on the bottom electrode601above the supporting layer mesa611; and Step B513: (Please referring toFIG. 2Q) forming a top electrode603, wherein the top electrode603is formed on the other end with respect to the bottom electrode601, where the top electrode603is formed on the dielectric layer602or formed on both the dielectric layer602and the supporting layer61, and the top electrode603is formed on and at least extended along the dielectric layer602above the supporting layer mesa611; Step B52: defining at least one recess etching area, and etching to remove the supporting layer61within the at least one recess etching area or etching to remove the supporting layer61and the bulk acoustic resonator structure60within the at least one recess etching area such that the etching stops at the top sacrificial layer mesa632and/or the compound semiconductor epitaxial substrate10(the collector layer33) to form at least one etching recess62, thereby part of the top sacrificial layer mesa632is exposed (Please referring toFIGS. 2R and 2S, wherein the cross-sectional direction ofFIG. 2Sis orthogonal to that ofFIG. 2R, and there is only the acoustic wave device50at the position of the cross-sectional direction ofFIG. 2S, hence there is no power amplifier20shown inFIG. 2S); Step B53: etching to remove the top sacrificial layer mesa632to form a supporting layer recess612, wherein at least one top sacrificial layer etching solution contacts with the top sacrificial layer mesa632via the at least one etching recess62and etches to remove the top sacrificial layer mesa632, thereby the top and the bottom of the supporting layer recess612are the supporting layer61and the compound semiconductor epitaxial substrate10(the collector layer33) respectively (Please referring toFIGS. 2T and 2U, wherein the cross-sectional direction ofFIG. 2Uis orthogonal to that ofFIG. 2T, and there is only the acoustic wave device50at the position of the cross-sectional direction ofFIG. 2U, hence there is no power amplifier20shown inFIG. 2U); Step B54: defining a collector electrode etching area, and etching to remove the collector layer33within the collector electrode etching area such that the etching stops at the subcollector layer31to form a collector recess331(Please referring toFIGS. 2V and 2W, wherein the cross-sectional direction ofFIG. 2Wis orthogonal to that ofFIG. 2V, and there is only the acoustic wave device50at the position of the cross-sectional direction ofFIG. 2W, hence there is no power amplifier20shown inFIG. 2W), thereby the subcollector layer31within the collector recess331is exposed; and etching to remove part of the compound semiconductor epitaxial substrate10below the supporting layer recess612to form a substrate recess15, wherein the bottom of the substrate recess15is the compound semiconductor epitaxial substrate10(the subcollector layer31), wherein at least one substrate recess etching solution contacts with the top surface of the compound semiconductor epitaxial substrate10(the collector layer33) via the at least one etching recess62and the supporting layer recess612, the at least one substrate recess etching solution is uniformly distributed on the top surface of the compound semiconductor epitaxial substrate10(the collector layer33) through the supporting layer recess612so as to uniformly etch part of the compound semiconductor epitaxial substrate10below the supporting layer recess612to form the substrate recess15, and thereby prevents the side etching phenomenon during the etching, wherein the supporting layer recess612is communicated with the substrate recess15, and the supporting layer recess612and the substrate recess15have a boundary103therebetween and the boundary103is the extended from the top surface of the compound semiconductor epitaxial substrate10, wherein the gap between the supporting layer mesa611and the bottom of the substrate recess15is increased by the communication of the supporting layer recess612and the substrate recess15, so as to avoid the contact of the supporting layer mesa611and the bottom of the substrate recess15when the film bulk acoustic resonator51is affected by stress such that the supporting layer mesa611is bended downwardly; and Step B55: forming a collector electrode37on the subcollector layer31within the collector recess331(Please referring toFIGS. 2B and 2C, wherein the cross-sectional direction ofFIG. 2Cis orthogonal to that ofFIG. 2B, and there is only the acoustic wave device50at the position of the cross-sectional direction ofFIG. 2C, hence there is no power amplifier20shown inFIG. 2C); thereby the first side101of the compound semiconductor epitaxial substrate10includes: the compound semiconductor substrate12, the subcollector layer31, the collector layer33and the collector recess331; the power amplifier upper structure21includes: the base layer34, the emitter ledge layer35, the emitter layer36, the base electrode38, the emitter electrode39and the collector electrode37; wherein the first side101of the compound semiconductor epitaxial substrate10and the power amplifier upper structure21form the heterojunction bipolar transistor30; wherein the substrate recess15is peripherally surrounded by the collector layer33, and the bottom of the substrate recess15is the subcollector layer31.

Step B44, Step B45and Step B46may be substituted by Step B441, Step B451, Step B461and Step B462. These steps are as follows: Step B441: (Please referring toFIG. 2K) defining an emitter layer etching area, and etching to remove the emitter layer36within the emitter layer etching area; Step B451: defining an emitter ledge layer etching area, and etching to remove the emitter ledge layer35within the emitter ledge layer etching area; Step B461: forming a base electrode38on the base layer34; Step B462: defining a base layer etching area, and etching to remove the base layer34within the base layer etching area.

Please refer toFIGS. 2G, 2D and 2E, in whichFIG. 2Gshows the cross-sectional schematic of the steps of the fabrication method for the embodiment ofFIGS. 2D and 2Eof the integrated structure of power amplifier and acoustic wave device of the present invention. The steps of the fabrication method for the embodiment ofFIGS. 2D and 2Eare basically the same as the fabrication method steps for the embodiment ofFIGS. 2B and 2C, except that Step B1further comprises Step B115: forming an etching stop layer32on the subcollector layer31; and Step B545: etching to remove the etching stop layer32within the collector electrode etching area such that the etching stops at the subcollector layer31to form the collector recess331, and thereby the subcollector layer31within the collector recess331is exposed. Step B115is between Step B11and Step B12, i.e. first, forming the subcollector layer31on the compound semiconductor substrate12, then forming the etching stop layer32on the subcollector layer31, and then forming the collector layer33on the etching stop layer32, such that the epitaxial structure13includes: the subcollector layer31, the etching stop layer32and the collector layer33. Step B545is between Step B54and Step B55. Step B545may also includes a step of etching to remove the etching stop layer32below the bottom of the substrate recess15, such that the substrate recess15is peripherally surrounded by the collector layer33and the etching stop layer32, and the bottom of the substrate recess15is the subcollector layer31. The collector electrode37is formed on the subcollector layer31within the collector recess331. Thereby the first side101of the compound semiconductor epitaxial substrate10includes: the compound semiconductor substrate12, the subcollector layer31, the etching stop layer32, the collector layer33and the collector recess331. The power amplifier upper structure21includes: the base layer34, the emitter ledge layer35, the emitter layer36, the base electrode38, the emitter electrode39and the collector electrode37. The first side101of the compound semiconductor epitaxial substrate10and the power amplifier upper structure21form the heterojunction bipolar transistor30.

In an embodiment, the top sacrificial layer63is made of AlAs or TiW.

In an embodiment, the TiW of the top sacrificial layer63may be formed by sputtering on the epitaxial structure13(the collector layer33). TiW may be etched by H2O2.

In an embodiment, the AlAs of the top sacrificial layer63may be formed by molecular beam epitaxy (MBE) or metal organic chemical vapor deposition (MOCVD) on the epitaxial structure13(the collector layer33).

In an embodiment, the thickness of the top sacrificial layer63is between 10 nm and 3500 nm. In another embodiment, the optimized thickness of the top sacrificial layer63is between 10 nm and 1500 nm.

Please refer toFIG. 3, which shows the cross-sectional view of another embodiment of the integrated structure of power amplifier and acoustic wave device of the present invention. The main structure inFIG. 3is basically the same as the structure shown inFIG. 1, except that the power amplifier20is a pseudomorphic high electron mobility transistor40(pHEMT). The epitaxial structure13includes: a buffer layer41, a channel layer42, a Schottky layer43and a cap layer44; wherein the buffer layer41is formed on the compound semiconductor substrate12; the channel layer42is formed on the buffer layer41; the Schottky layer43is formed on the channel layer42; the cap layer44is formed on the Schottky layer43. The first side101of the compound semiconductor epitaxial substrate10further comprises a gate recess451; the bottom of the gate recess451is the Schottky layer43; wherein the power amplifier upper structure21includes: a drain electrode47, a source electrode46and a gate electrode45; wherein the drain electrode47is formed on one end of the cap layer44; the source electrode46is formed on the other end of the cap layer44, wherein the gate recess451is located between the drain electrode47and the source electrode46; the gate electrode45is formed on the Schottky layer43within the gate recess451; thereby the first side101of the compound semiconductor epitaxial substrate10includes: the compound semiconductor substrate12, the buffer layer41, the channel layer42, the Schottky layer43, the cap layer44and the gate recess451; wherein the first side101of the compound semiconductor epitaxial substrate10and the power amplifier upper structure21form the pseudomorphic high electron mobility transistor40. The acoustic wave device50inFIG. 3is basically the same as the acoustic wave device50inFIG. 1. The substrate recess15of the second side102of the compound semiconductor epitaxial substrate10is peripherally surrounded by the buffer layer41, the channel layer42, the Schottky layer43and the cap layer44; and the bottom of the substrate recess15is the buffer layer41. The second side102of the compound semiconductor epitaxial substrate10and the film bulk acoustic resonator51form the acoustic wave device50.

In an embodiment, the buffer layer41is made of GaAs, SiO2or GaN and is formed on the compound semiconductor substrate12by epitaxial growth.

In an embodiment, the compound semiconductor substrate12is made of GaAs, while the buffer layer41is preferable to be made of GaAs. In another embodiment, the compound semiconductor substrate12is made of Sapphire, while the buffer layer41is preferable to be made of GaN.

Please refer toFIG. 3A, which shows the cross-sectional view of another embodiment of the integrated structure of power amplifier and acoustic wave device of the present invention. The main structure inFIG. 3Ais basically the same as the structure shown inFIG. 3, except that the pseudomorphic high electron mobility transistor40further comprises the supporting layer61. The supporting layer61plays a role of protection, and may prevent the pseudomorphic high electron mobility transistor40from oxidation or corrosion. In other embodiments having basically the same structure as the embodiment inFIG. 3, the power amplifier20may also include the supporting layer61.

Please refer toFIG. 3B, which shows the cross-sectional view of another embodiment of the integrated structure of power amplifier and acoustic wave device of the present invention. The main structure inFIG. 3Bis basically the same as the structure shown inFIG. 3, except that the substrate recess15of the second side102of the compound semiconductor epitaxial substrate10is peripherally surrounded by the channel layer42, the Schottky layer43and the cap layer44, and the bottom of the substrate recess15is the buffer layer41. The power amplifier20may also include the supporting layer61, or may choose not to include the supporting layer61.

Please refer toFIG. 3C, which shows the cross-sectional view of another embodiment of the integrated structure of power amplifier and acoustic wave device of the present invention. The main structure inFIG. 3Cis basically the same as the structure shown inFIG. 3, except that the film bulk acoustic resonator51further comprises at least one etching recess62. The cross-sectional direction ofFIG. 3Cis orthogonal to that ofFIG. 3. And there is only the acoustic wave device50at the position of the cross-sectional direction ofFIG. 3C, hence there is no power amplifier20shown inFIG. 3C. One end of the at least one etching recess62is communicated with the supporting layer recess612, the other end of the at least one etching recess62penetrates the supporting layer61or penetrates both the supporting layer61and the bulk acoustic resonator structure60such that the at least one etching recess62is communicated with the outside, and thereby the supporting layer recess612is communicated with the outside. The feature of the at least one etching recess62of the embodiment inFIG. 3Cis basically the same as that of the embodiment inFIG. 1B. The power amplifier20may also include the supporting layer61, or may choose not to include the supporting layer61.

Please refer toFIGS. 3A and 3C. The cross-sectional direction ofFIG. 3Cis orthogonal to that ofFIG. 3A. And there is only the acoustic wave device50at the position of the cross-sectional direction ofFIG. 3C, hence there is no power amplifier20shown inFIG. 3C. The present invention provides a fabrication method for integrated structure of power amplifier and acoustic wave device. The fabrication method for the embodiment ofFIGS. 3A and 3Ccomprises following steps of: Step C1: forming an epitaxial structure13on a compound semiconductor substrate12to form a compound semiconductor epitaxial substrate10; Step C2: forming a power amplifier upper structure21on a first side101of the compound semiconductor epitaxial substrate10to form a power amplifier20, wherein the power amplifier20is a pseudomorphic high electron mobility transistor40; and Step C3: forming a film bulk acoustic resonator51on a second side102of the compound semiconductor epitaxial substrate10to form an acoustic wave device50; wherein, the integrated structure1of the power amplifier20and the acoustic wave device50on the same the compound semiconductor epitaxial substrate10is capable of reducing the component size, optimizing the impedance matching, and reducing the signal loss between the power amplifier20and the acoustic wave device50. Step C1includes following steps of: Step C11: (Please referring toFIG. 3D) forming a buffer layer41on the compound semiconductor substrate12; Step C12: forming a channel layer42on the buffer layer41; Step C13: forming a Schottky layer43on the channel layer42; and Step C14: forming a cap layer44on the Schottky layer43. Step C2includes following steps of: Step C21: (Please referring toFIG. 3E) defining a gate electrode etching area, and etching to remove the cap layer44within the gate electrode etching area such that the etching stops at the Schottky layer43to form a gate recess451, thereby the Schottky layer43within the gate recess451is exposed; Step C22: (Please referring toFIG. 3F) forming a drain electrode47on one end of the cap layer44; Step C23: forming a source electrode46on the other end of the cap layer44, wherein the gate recess451is located between the drain electrode47and the source electrode46; and Step C24: forming a gate electrode45on the Schottky layer43within the gate recess451. Step C3includes following steps of: Step C31: (Please referring toFIG. 3G) forming a top sacrificial layer63on the compound semiconductor epitaxial substrate10(the cap layer44); Step C32: defining a top sacrificial layer etching area, and etching to remove the top sacrificial layer63within the top sacrificial layer etching area to form a top sacrificial layer mesa632, such that the compound semiconductor epitaxial substrate10(the cap layer44) within the top sacrificial layer etching area is exposed; Step C33: (Please referring toFIGS. 3H and 3I) forming a supporting layer61on the top sacrificial layer63and the compound semiconductor epitaxial substrate10(the cap layer44), wherein the supporting layer61has a supporting layer mesa611right above the top sacrificial layer mesa632; wherein the supporting layer61may also be formed on the gate electrode45, the source electrode46, the drain electrode47and the gate recess451, where the supporting layer61plays a role of protection; Step C34: forming a bulk acoustic resonator structure60on the supporting layer61, which includes following steps of: Step C341: (Please referring toFIG. 3J) forming a bottom electrode601on one end of the supporting layer61, where the bottom electrode601is formed on and at least extended along the supporting layer mesa611; Step C342: (Please referring toFIG. 3K) forming a dielectric layer602, wherein the dielectric layer602is formed at least on the bottom electrode601above the supporting layer mesa611; and Step C343: (Please referring toFIG. 3L) forming a top electrode603, wherein the top electrode603is formed on the other end with respect to the bottom electrode601, where the top electrode603is formed on the dielectric layer602or formed on both the dielectric layer602and the supporting layer61, and the top electrode603is formed on and at least extended along the dielectric layer602above the supporting layer mesa611; Step C35: defining at least one recess etching area, and etching to remove the supporting layer61within the at least one recess etching area or etching to remove the supporting layer61and the bulk acoustic resonator structure60within the at least one recess etching area such that the etching stops at the top sacrificial layer mesa632and/or the compound semiconductor epitaxial substrate10(the cap layer44) to form at least one etching recess62, thereby part of the top sacrificial layer mesa632is exposed (Please referring toFIGS. 3L and 3M, wherein the cross-sectional direction ofFIG. 3Mis orthogonal to that ofFIG. 3L, and there is only the acoustic wave device50at the position of the cross-sectional direction ofFIG. 3M, hence there is no power amplifier20shown inFIG. 3M); Step C36: etching to remove the top sacrificial layer mesa632to form a supporting layer recess612, wherein at least one top sacrificial layer etching solution contacts with the top sacrificial layer mesa632via the at least one etching recess62and etches to remove the top sacrificial layer mesa632, thereby the top and the bottom of the supporting layer recess612are the supporting layer61and the compound semiconductor epitaxial substrate10(the cap layer44) respectively (Please referring toFIGS. 3N and 3O, wherein the cross-sectional direction ofFIG. 3Ois orthogonal to that ofFIG. 3N, and there is only the acoustic wave device50at the position of the cross-sectional direction ofFIG. 3O, hence there is no power amplifier20shown inFIG. 3O); and Step C37: etching to remove part of the compound semiconductor epitaxial substrate10below the supporting layer recess612to form a substrate recess15(Please referring toFIGS. 3A and 3C, wherein the cross-sectional direction ofFIG. 3Cis orthogonal to that ofFIG. 3A, and there is only the acoustic wave device50at the position of the cross-sectional direction ofFIG. 3C, hence there is no power amplifier20shown inFIG. 3C), wherein at least one substrate recess etching solution contacts with the top surface of the compound semiconductor epitaxial substrate10(the cap layer44) via the at least one etching recess62and the supporting layer recess612, the at least one substrate recess etching solution is uniformly distributed on the top surface of the compound semiconductor epitaxial substrate10(the cap layer44) through the supporting layer recess612so as to uniformly etch part of the compound semiconductor epitaxial substrate10below the supporting layer recess612to form the substrate recess15, and thereby prevents the side etching phenomenon during the etching, wherein the supporting layer recess612is communicated with the substrate recess15, and the supporting layer recess612and the substrate recess15have a boundary103therebetween and the boundary103is the extended from the top surface of the compound semiconductor epitaxial substrate10, wherein the gap between the supporting layer mesa611and the bottom of the substrate recess15is increased by the communication of the supporting layer recess612and the substrate recess15, so as to avoid the contact of the supporting layer mesa611and the bottom of the substrate recess15when the film bulk acoustic resonator51is affected by stress such that the supporting layer mesa611is bended downwardly; thereby the first side101of the compound semiconductor epitaxial substrate10includes: the compound semiconductor substrate12, the buffer layer41, the channel layer42, the Schottky layer43, the cap layer44and the gate recess451; the power amplifier upper structure21includes: the drain electrode47, the source electrode46and the gate electrode45; wherein the first side101of the compound semiconductor epitaxial substrate10and the power amplifier upper structure21form the pseudomorphic high electron mobility transistor40; wherein the bottom of the substrate recess15is the compound semiconductor epitaxial substrate10(the buffer layer41), and the substrate recess15is peripherally surrounded by the channel layer42, the Schottky layer43and the cap layer44or by the buffer layer41, the channel layer42, the Schottky layer43and the cap layer44(Please referring toFIG. 3B).

Please refer toFIG. 4, the cross-sectional view of an embodiment of the improved acoustic wave device structure of the present invention, the improved acoustic wave device structure comprises: a substrate11and a film bulk acoustic resonator51; wherein the substrate11has a substrate recess15on the top of the substrate11; the film bulk acoustic resonator51is formed on the substrate11; wherein the film bulk acoustic resonator51includes: a supporting layer61and a bulk acoustic resonator structure60; wherein supporting layer61is formed on the substrate11, wherein the supporting layer61has a supporting layer recess612on the bottom of the supporting layer61, the supporting layer61has an upwardly protruding supporting layer mesa611right above the supporting layer recess612, and the supporting layer recess612is located right above the substrate recess15, the supporting layer recess612is communicated with the substrate recess15, and the supporting layer recess612and the substrate recess15have a boundary113therebetween and the boundary113is the extended from the top surface of the substrate11; the bulk acoustic resonator structure60is formed on the supporting layer61, wherein the bulk acoustic resonator structure60includes: a bottom electrode601, a dielectric layer602and a top electrode603. The bottom electrode601is formed on one end of the supporting layer61, where the bottom electrode601is formed on and at least extended along the supporting layer mesa611. The dielectric layer602is formed at least on the bottom electrode601above the supporting layer mesa611. In the embodiment ofFIG. 4, the dielectric layer602is formed on both the bottom electrode601and the supporting layer61, and the dielectric layer602is also formed on the bottom electrode601above the supporting layer mesa611. Please also refer toFIG. 4A, which shows the cross-sectional view of another embodiment of the improved acoustic wave device structure of the present invention. The main structure inFIG. 4Ais basically the same as the structure shown inFIG. 4, except that the dielectric layer602is formed on the bottom electrode601above the supporting layer mesa611and on a small part of the supporting layer61above the supporting layer mesa611. The top electrode603is formed on the other end with respect to the bottom electrode601, where the top electrode603is formed on the dielectric layer602or formed on both the dielectric layer602and the supporting layer61, and the top electrode603is formed on and at least extended along the dielectric layer602above the supporting layer mesa611. In the embodiment ofFIG. 4, the top electrode603is formed on the dielectric layer602, while in embodiment ofFIG. 4A, the top electrode603is formed on both the dielectric layer602and the supporting layer61. The top electrode603and the bottom electrode601are not electrically connected. The gap between the supporting layer mesa611and the bottom of the substrate recess15is increased by the communication of the supporting layer recess612and the substrate recess15, so as to avoid the contact of the supporting layer mesa611and the bottom of the substrate recess15when the film bulk acoustic resonator51is affected by stress such that the supporting layer mesa611is bended downwardly.

In an embodiment, the application of the acoustic wave device50may be a filter. Usually plural acoustic wave devices50are in series and/or in parallel in the combination of circuit to form a filter which may filter the signal.

In one embodiment, the application of the acoustic wave device50may be a mass sensing device, a biomedical sensing device, an UV sensing device, a pressure sensing device or a temperature sensing device.

In an embodiment, the function of the supporting layer61may be the supporting for the film bulk acoustic resonator51for preventing the film bulk acoustic resonator51from collapsing. The supporting layer61also may be the seed layer for the bottom electrode601and the dielectric layer602for improving the crystalline quality. In an embodiment, the supporting layer61is made of SiNxor AlN. The supporting layer61is formed on the substrate11by molecular beam epitaxy (MBE), sputtering or chemical vapor deposition (CVD).

In an embodiment, the bottom electrode601is needed to have a lower roughness and resistivity for benefit the preferable crystal growth axis. In an embodiment, the bottom electrode601is made of Mo, Pt, Al, Au, W or Ru. The bottom electrode601is formed on the supporting layer61by evaporation or sputtering.

In an embodiment, the dielectric layer602is made of AlN, monocrystalline SiO2, ZnO, HfO2, barium strontium titanate (BST) or lead zirconate titanate (PZT), and is formed on the bottom electrode601or formed on both the electrode601and the supporting layer61by epitaxial growth or sputtering. The selection of the materials of the dielectric layer602is associated with the application. AlN is a high acoustic wave velocity material (12000 m/s) and is suitable for high frequency application, and after the formation of the micro structure of the material, it has good physical and chemical stability and its properties are not easily to be influenced by the circumstance. ZnO may be formed under lower temperature and it has an acoustic wave velocity 6000 m/s. Its electromechanical coupling coefficient is higher (8.5%) and it is suitable for the application of broadband filter. However when forming ZnO, the concentration of oxygen vacancies in ZnO is not easily controlled, yet it is easily influenced by the humidity and oxygen of the circumstance. Both barium strontium titanate (BST) and lead zirconate titanate (PZT) are ferroelectric materials. Their dielectric constant may vary under external electric field. Hence, they are suitable for the application of acoustic wave device with tunable frequency within dozen MHz range of frequencies. Both barium strontium titanate (BST) and lead zirconate titanate (PZT) need to be polarized under high voltage electric field in order to obtain their piezoelectric characteristics. Lead zirconate titanate (PZT) has higher electromechanical coupling coefficient, however it contains lead.

In an embodiment, the top electrode603is needed to have a lower resistivity for reducing power loss so as to reduce the insertion loss. In an embodiment, the top electrode603may be made of Mo, Pt, Al, Au, W or Ru. The top electrode603is formed on the dielectric layer602or is formed on both the dielectric layer602and the supporting layer61by evaporation or sputtering.

In an embodiment, the bottom electrode601is made of Mo or Pt, while the dielectric layer602is made of AlN. The Mo of the bottom electrode601may be etched by Lithography and Lift-off process. And the AlN of the dielectric layer602may be etched by inductively coupled plasma (ICP) process with CF4plasma.

In an embodiment, the depth of the substrate recess15is between 50 nm and 10000 nm.

In an embodiment, the depth of the supporting layer recess612is between 10 nm and 3500 nm. In another embodiment, the optimized depth of the supporting layer recess612is between 10 nm and 1500 nm.

Please refer toFIG. 4B, which shows the cross-sectional view of another embodiment of the improved acoustic wave device structure of the present invention. The main structure inFIG. 4Bis basically the same as the structure shown inFIG. 4, except that the film bulk acoustic resonator51further comprises at least one etching recess62. The cross-sectional direction ofFIG. 4Bis orthogonal to that ofFIG. 4. One end of the at least one etching recess62is communicated with the supporting layer recess612, the other end of the at least one etching recess62penetrates the supporting layer61or penetrates both the supporting layer61and the bulk acoustic resonator structure60such that the at least one etching recess62is communicated with the outside, and thereby the supporting layer recess612is communicated with the outside.

Please refer toFIG. 4C, which shows the partial enlarged cross-sectional view of an embodiment of the improved acoustic wave device structure of the present invention. In the embodiment ofFIG. 4C, the supporting layer recess612has an opening smaller than that of the substrate recess15. Please refer toFIG. 4D, which shows the partial enlarged cross-sectional view of another embodiment of the improved acoustic wave device structure of the present invention. In the embodiment ofFIG. 4D, the supporting layer recess612has an opening almost equal to that of the substrate recess15.

Please refer toFIGS. 4E, 4F, 4G and 4H, which show the top views of the relative position of the etching recess and the supporting layer mesa in the embodiments of the improved acoustic wave device structure of the present invention. In the embodiment ofFIG. 4E, the improved acoustic wave device structure50has two etching recess62with long strip opening. The two etching recesses62are located on two opposite sides of the supporting layer mesa611respectively. And the etching recesses62penetrate the supporting layer61(not shown inFIG. 4E), and thereby the supporting layer recess612(not shown inFIG. 4E) is communicated with the outside. In the embodiment ofFIG. 4F, the improved acoustic wave device structure50has two etching recess62with long strip opening. The two etching recesses62are located on two opposite sides of the supporting layer mesa611respectively. (part of the etching recesses62are within the supporting layer mesa611, the rest part of the etching recesses62are outside the supporting layer mesa611) And the etching recesses62penetrate the supporting layer61(not shown inFIG. 4F) and the dielectric layer602. In the embodiment ofFIG. 4G, the improved acoustic wave device structure50has two etching recess62with long strip opening. The two etching recesses62are located respectively on two opposite sides of the supporting layer mesa611within the supporting layer mesa611. And the etching recesses62penetrate the supporting layer61(not shown inFIG. 4G), the bottom electrode601, the dielectric layer602and the top electrode603. In the embodiment ofFIG. 4H, the improved acoustic wave device structure50has four etching recess62with square opening. The four etching recesses62are located on four corners of the supporting layer mesa611respectively. And the etching recesses62penetrate the supporting layer61(not shown inFIG. 4H). The amount of the etching recesses62is not limited to one, two, three, four or more. The etching recesses62may locate on other position and should not be limited byFIG. 4E, 4F, 4G or 4H.

Please refer toFIG. 5, which shows the cross-sectional view of another embodiment of the improved acoustic wave device structure of the present invention. The main structure inFIG. 5is basically the same as the structure shown inFIG. 4, except that the substrate11includes a base substrate16and an epitaxial structure13formed on the base substrate16. The epitaxial structure13includes: a buffer layer41, an etching stop layer32and a bottom sacrificial layer65; wherein the buffer layer41is formed on the base substrate16; the etching stop layer32is formed on the buffer layer41; the bottom sacrificial layer65is formed on the etching stop layer32; wherein the substrate recess15is peripherally surrounded by the bottom sacrificial layer65, and the bottom of the substrate recess15is the etching stop layer32.

In an embodiment, the base substrate16may be made of GaAs, SiC, InP, GaN, AlN, Sapphire, Si or glass.

In an embodiment, the buffer layer41is made of GaAs, SiO2or GaN and is formed on the base substrate16by epitaxial growth.

In an embodiment, the base substrate16is made of GaAs, while the buffer layer41is preferable to be made of GaAs. In another embodiment, the base substrate16is made of Sapphire, while the buffer layer41is preferable to be made of GaN. In one embodiment, the base substrate16is made of Si, while the buffer layer41is preferable to be made of SiO2.

In an embodiment, the etching stop layer32is made of InGaP. In one embodiment, the thickness of the etching stop layer32is between 5 nm and 1000 nm. In another embodiment, the optimized thickness of the etching stop layer32is 20 nm.

In an embodiment, the bottom sacrificial layer65is made of GaAs and is formed on the etching stop layer32by molecular beam epitaxy (MBE) or metal organic chemical vapor deposition (MOCVD). In another embodiment, the thickness of the bottom sacrificial layer65is between 500 nm and 3000 nm.

In an embodiment, the buffer layer41is made of GaAs, SiO2or GaN. The bottom sacrificial layer65is made of GaAs, Phosphosilicate glass (PSG) or Borophosphosilicate glass (BPSG). The etching stop layer32is made of InGaP, SiNx, Pt, Al or Au.

In an embodiment, the bottom sacrificial layer65is made of GaAs; the etching stop layer32is made of InGaP; GaAs of the bottom sacrificial layer65may be etched by citric acid; and the etching may stop at InGaP of the etching stop layer32. In another embodiment, the bottom sacrificial layer65is made of Phosphosilicate glass (PSG) or Borophosphosilicate glass (BPSG); the etching stop layer32is made of SiNx, Pt, Al or Au.

Please refer toFIG. 5A, which shows the cross-sectional view of another embodiment of the improved acoustic wave device structure of the present invention. The main structure inFIG. 5Ais basically the same as the structure shown inFIG. 5, except that the film bulk acoustic resonator51further comprises at least one etching recess62. The cross-sectional direction ofFIG. 5Ais orthogonal to that ofFIG. 5. One end of the at least one etching recess62is communicated with the supporting layer recess612, the other end of the at least one etching recess62penetrates the supporting layer61or penetrates both the supporting layer61and the bulk acoustic resonator structure60such that the at least one etching recess62is communicated with the outside, and thereby the supporting layer recess612is communicated with the outside. The feature of the at least one etching recess62of the embodiment inFIG. 5Ais basically the same as that of the embodiment inFIG. 4B.

Please refer toFIGS. 5B and 5C. The cross-sectional direction ofFIG. 5Cis orthogonal to that ofFIG. 5B. The present invention provides a fabrication method for improved acoustic wave device structure. The fabrication method for the embodiment ofFIGS. 5B and 5Ccomprises following steps of: Step D1: forming an epitaxial structure13on a base substrate16to form a substrate11; and Step D2: forming a film bulk acoustic resonator51on the substrate11(the epitaxial structure13). Step D1includes following steps of: Step D11: (Please referring toFIG. 5D) forming a buffer layer41on the base substrate16; Step D12: forming an etching stop layer32on the buffer layer41; and Step D13: forming a bottom sacrificial layer65on the etching stop layer32; wherein the epitaxial structure13includes: the buffer layer41, the etching stop layer32and the bottom sacrificial layer65. Step D2includes following steps of: Step D21: (Please referring toFIG. 5D) forming a top sacrificial layer63on the substrate11(the bottom sacrificial layer65); Step D22: (Please referring toFIG. 5E) defining a top sacrificial layer etching area, and etching to remove the top sacrificial layer63within the top sacrificial layer etching area to form a top sacrificial layer mesa632, such that the substrate11(the bottom sacrificial layer65) within the top sacrificial layer etching area is exposed; Step D23: forming a supporting layer61on the top sacrificial layer63and the substrate11(the bottom sacrificial layer65), wherein the supporting layer61has a supporting layer mesa611right above the top sacrificial layer mesa632(Please referring toFIGS. 5F and 5G, wherein the cross-sectional direction ofFIG. 5Gis orthogonal to that ofFIG. 5F); wherein after Step D23, it may also choose to execute the step: defining a supporting layer etching area, and etching to remove the supporting layer61within the supporting layer etching area, such that the top sacrificial layer mesa632and/or the substrate11(the bottom sacrificial layer65) within the supporting layer etching area are/is exposed (please also referring toFIGS. 5H and 5I, wherein the cross-sectional direction ofFIG. 5Iis orthogonal to that ofFIG. 5H); Step D24: forming a bulk acoustic resonator structure60on the supporting layer61(Please referring toFIGS. 5J and 5K, wherein the cross-sectional direction ofFIG. 5Kis orthogonal to that ofFIG. 5J), which includes following steps of: Step D241: forming a bottom electrode601on one end of the supporting layer61, where the bottom electrode601is formed on and at least extended along the supporting layer mesa611; Step D242: forming a dielectric layer602, wherein the dielectric layer602is formed at least on the bottom electrode601above the supporting layer mesa611; and Step D243: forming a top electrode603, wherein the top electrode603is formed on the other end with respect to the bottom electrode601, where the top electrode603is formed on the dielectric layer602or formed on both the dielectric layer602and the supporting layer61, and the top electrode603is formed on and at least extended along the dielectric layer602above the supporting layer mesa611; Step D25: defining at least one recess etching area, and etching to remove the supporting layer61within the at least one recess etching area or etching to remove the supporting layer61and the bulk acoustic resonator structure60within the at least one recess etching area such that the etching stops at the top sacrificial layer mesa632and/or the substrate11(the bottom sacrificial layer65) to form at least one etching recess62, thereby part of the top sacrificial layer mesa632is exposed; Step D26: etching to remove the top sacrificial layer mesa632to form a supporting layer recess612, wherein at least one top sacrificial layer etching solution contacts with the top sacrificial layer mesa632via the at least one etching recess62and etches to remove the top sacrificial layer mesa632, thereby the top and the bottom of the supporting layer recess612are the supporting layer61and the substrate11(the bottom sacrificial layer65) respectively (Please referring toFIGS. 5L and 5M, wherein the cross-sectional direction ofFIG. 5Mis orthogonal to that ofFIG. 5L); and Step D27: etching to remove part of the substrate11below the supporting layer recess612to form a substrate recess15(Please referring toFIGS. 5B and 5C, wherein the cross-sectional direction ofFIG. 5Cis orthogonal to that ofFIG. 5B), wherein the substrate recess15is peripherally surrounded by the bottom sacrificial layer65, and the bottom of the substrate recess15is the etching stop layer32, wherein at least one substrate recess etching solution contacts with the top surface of the substrate11via the at least one etching recess62and the supporting layer recess612, the at least one substrate recess etching solution is uniformly distributed on the top surface of the substrate11through the supporting layer recess612so as to uniformly etch part of the substrate11below the supporting layer recess612to form the substrate recess15, and thereby prevents the side etching phenomenon during the etching, wherein the supporting layer recess612is communicated with the substrate recess15, and the supporting layer recess612and the substrate recess15have a boundary113therebetween and the boundary113is the extended from the top surface of the substrate11, wherein the gap between the supporting layer mesa611and the bottom of the substrate recess15is increased by the communication of the supporting layer recess612and the substrate recess15, so as to avoid the contact of the supporting layer mesa611and the bottom of the substrate recess15when the film bulk acoustic resonator51is affected by stress such that the supporting layer mesa611is bended downwardly.

In an embodiment, the top sacrificial layer63is made of AlAs or TiW.

In an embodiment, the TiW of the top sacrificial layer63may be formed by sputtering on the epitaxial structure13. TiW may be etched by H2O2.

In an embodiment, the AlAs of the top sacrificial layer63may be formed by molecular beam epitaxy (MBE) or metal organic chemical vapor deposition (MOCVD) on the epitaxial structure13.

In an embodiment, the thickness of the top sacrificial layer63is between 10 nm and 3500 nm. In another embodiment, the optimized thickness of the top sacrificial layer63is between 10 nm and 1500 nm.

Please refer toFIG. 6, which shows the cross-sectional view of another embodiment of the improved acoustic wave device structure of the present invention. The main structure inFIG. 6is basically the same as the structure shown inFIG. 4, except that the substrate11is a silicon substrate14.

In another embodiment, the substrate11is a glass substrate.

Please refer toFIG. 6A, which shows the cross-sectional view of another embodiment of the improved acoustic wave device structure of the present invention. The main structure inFIG. 6Ais basically the same as the structure shown inFIG. 6, except that the film bulk acoustic resonator51further comprises at least one etching recess62. The cross-sectional direction ofFIG. 6Ais orthogonal to that ofFIG. 6. One end of the at least one etching recess62is communicated with the supporting layer recess612, the other end of the at least one etching recess62penetrates the supporting layer61or penetrates both the supporting layer61and the bulk acoustic resonator structure60such that the at least one etching recess62is communicated with the outside, and thereby the supporting layer recess612is communicated with the outside. The feature of the at least one etching recess62of the embodiment inFIG. 6Ais basically the same as that of the embodiment inFIG. 4B.

Please refer toFIGS. 6 and 6A. The cross-sectional direction ofFIG. 6Ais orthogonal to that ofFIG. 6. The present invention provides a fabrication method for improved acoustic wave device structure. The fabrication method for the embodiment ofFIGS. 6 and 6Acomprises following steps of: Step E1: forming a film bulk acoustic resonator51on a substrate11, which includes following steps of: Step E11: (Please referring toFIG. 6B) forming a top sacrificial layer63on the substrate11, wherein the substrate11is a silicon substrate14; Step E12: (Please referring toFIG. 6C) defining a top sacrificial layer etching area, and etching to remove the top sacrificial layer63within the top sacrificial layer etching area to form a top sacrificial layer mesa632, such that the substrate11within the top sacrificial layer etching area is exposed; Step E13: forming a supporting layer61on the top sacrificial layer63and the substrate11, wherein the supporting layer61has a supporting layer mesa611right above the top sacrificial layer mesa632(Please referring toFIGS. 6D and 6E, wherein the cross-sectional direction ofFIG. 6Eis orthogonal to that ofFIG. 6D); wherein after Step E13, it may also choose to execute the step: defining a supporting layer etching area, and etching to remove the supporting layer61within the supporting layer etching area, such that the top sacrificial layer mesa632and/or the substrate11within the supporting layer etching area are/is exposed (please also referring toFIGS. 6F and 6G, wherein the cross-sectional direction ofFIG. 6Gis orthogonal to that ofFIG. 6F); Step E14: forming a bulk acoustic resonator structure60on the supporting layer61(Please referring toFIGS. 6H and 6I, wherein the cross-sectional direction ofFIG. 6Iis orthogonal to that ofFIG. 6H), which includes following steps of: Step E141: forming a bottom electrode601on one end of the supporting layer61, where the bottom electrode601is formed on and at least extended along the supporting layer mesa611; Step E142: forming a dielectric layer602, wherein the dielectric layer602is formed at least on the bottom electrode601above the supporting layer mesa611; and Step E143: forming a top electrode603, wherein the top electrode603is formed on the other end with respect to the bottom electrode601, where the top electrode603is formed on the dielectric layer602or formed on both the dielectric layer602and the supporting layer61, and the top electrode603is formed on and at least extended along the dielectric layer602above the supporting layer mesa611; Step E15: defining at least one recess etching area, and etching to remove the supporting layer61within the at least one recess etching area or etching to remove the supporting layer61and the bulk acoustic resonator structure60within the at least one recess etching area such that the etching stops at the top sacrificial layer mesa632and/or the substrate11to form at least one etching recess62, thereby part of the top sacrificial layer mesa632is exposed; Step E16: etching to remove the top sacrificial layer mesa632to form a supporting layer recess612, wherein at least one top sacrificial layer etching solution contacts with the top sacrificial layer mesa632via the at least one etching recess62and etches to remove the top sacrificial layer mesa632, thereby the top and the bottom of the supporting layer recess612are the supporting layer61and the substrate11respectively (Please referring toFIGS. 6J and 6K, wherein the cross-sectional direction ofFIG. 6Kis orthogonal to that ofFIG. 6J); and Step E17: etching to remove part of the substrate11below the supporting layer recess612to form a substrate recess15(Please referring toFIGS. 6 and 6A, wherein the cross-sectional direction ofFIG. 6Ais orthogonal to that ofFIG. 6), wherein the bottom of the substrate recess15is the substrate11, wherein at least one substrate recess etching solution contacts with the top surface of the substrate11via the at least one etching recess62and the supporting layer recess612, the at least one substrate recess etching solution is uniformly distributed on the top surface of the substrate11through the supporting layer recess612so as to uniformly etch part of the substrate11below the supporting layer recess612to form the substrate recess15, and thereby prevents the side etching phenomenon during the etching, wherein the supporting layer recess612is communicated with the substrate recess15, and the supporting layer recess612and the substrate recess15have a boundary113therebetween and the boundary113is the extended from the top surface of the substrate11, wherein the gap between the supporting layer mesa611and the bottom of the substrate recess15is increased by the communication of the supporting layer recess612and the substrate recess15, so as to avoid the contact of the supporting layer mesa611and the bottom of the substrate recess15when the film bulk acoustic resonator51is affected by stress such that the supporting layer mesa611is bended downwardly.

In another embodiment, the substrate11is a silicon substrate14, the top sacrificial layer63is made of TiW.

In an embodiment, the TiW of the top sacrificial layer63may be formed by sputtering on the substrate11. TiW may be etched by H2O2.

In an embodiment, the thickness of the top sacrificial layer63is between 10 nm and 3500 nm. In another embodiment, the optimized thickness of the top sacrificial layer63is between 10 nm and 1500 nm.

Please refer toFIGS. 6M and 6N, which show the cross-sectional views of another embodiment of the improved acoustic wave device structure of the present invention, wherein the cross-sectional direction ofFIG. 6Nis orthogonal to that ofFIG. 6M.

The main structure inFIGS. 6M and 6Nis basically the same as the structure shown inFIGS. 6 and 6A, except that in Step E12(Please compareFIGS. 6C and 6L), the top sacrificial layer63is etched and removed, except the top sacrificial layer mesa632.

Please refer toFIG. 8G, which is the cross-sectional schematic showing an embodiment of an integrated structure of acoustic wave device and varactor of the present invention. The present invention further provides an integrated structure of acoustic wave device and varactor. The integrated structure comprises a semiconductor substrate12, an acoustic wave device50and a varactor26. The semiconductor substrate12includes a first part12(1) and a second part12(2) of the semiconductor substrate12. The acoustic wave device50and the varactor26are formed on the first part12(1) and the second part12(2) of the semiconductor substrate12respectively. The acoustic wave device50comprises an acoustic wave device upper structure4and a first part22(1) of a bottom epitaxial structure22, wherein the bottom epitaxial structure22is formed on the semiconductor substrate12, wherein the bottom epitaxial structure22includes the first part22(1) and a second part22(2) of the bottom epitaxial structure22, wherein the first part22(1) and the second part22(2) of the bottom epitaxial structure22are formed on the first part12(1) and the second part12(2) of the semiconductor substrate12respectively, and wherein the acoustic wave device upper structure4is formed on the first part22(1) of the bottom epitaxial structure22. The varactor26comprises a varactor upper structure5and the second part22(2) of the bottom epitaxial structure22, wherein the varactor upper structure5is formed on the second part22(2) of the bottom epitaxial structure22. In current embodiment, the acoustic wave device50may be a bulk acoustic wave device. The integrated structure of the acoustic wave device50and the varactor26formed on the same the semiconductor substrate12is capable of reducing the module size, optimizing the impedance matching, and reducing the signal loss between the varactor26and the acoustic wave device50. The first part22(1) of the bottom epitaxial structure22comprises a bottom epitaxial structure recess24on the top of the bottom epitaxial structure22. A bottom of the bottom epitaxial structure recess24is the bottom epitaxial structure22. The acoustic wave device upper structure4comprises an acoustic wave device protection layer66(1) and an acoustic wave resonance structure64. The acoustic wave device protection layer66(1) is formed on the first part22(1) of the bottom epitaxial structure22. The acoustic wave device protection layer66(1) comprises an acoustic wave device protection layer recess608on the bottom of the acoustic wave device protection layer66(1) and an upwardly protruding acoustic wave device protection layer mesa607right above the acoustic wave device protection layer recess608. The acoustic wave device protection layer recess608is located right above the bottom epitaxial structure recess24, and the acoustic wave device protection layer recess608is communicated with the bottom epitaxial structure recess24, and wherein the acoustic wave device protection layer recess608and the bottom epitaxial structure recess24have a boundary104therebetween and the boundary104is extended from a top surface of the bottom epitaxial structure22. The acoustic wave resonance structure64is formed on the acoustic wave device protection layer mesa607. The acoustic wave resonance structure64comprises an acoustic wave device bottom electrode604, a dielectric layer605and an acoustic wave device top electrode606. The acoustic wave device bottom electrode604is formed on the acoustic wave device protection layer mesa607. The dielectric layer605is formed on the acoustic wave device bottom electrode604. The acoustic wave device top electrode606is formed on the dielectric layer605. A gap between the acoustic wave device protection layer66(1) and the bottom of the bottom epitaxial structure recess24is increased by the communication of the acoustic wave device protection layer recess608and the bottom epitaxial structure recess24, so as to avoid the contact of the acoustic wave device protection layer66(1) and the bottom of the bottom epitaxial structure recess24when the acoustic wave device50is affected by stress such that the acoustic wave device protection layer66(1) is bended downwardly. In some embodiments, the acoustic wave device protection layer recess608has an opening smaller than or equal to that of the bottom epitaxial structure recess24. In another embodiment, the acoustic wave device protection layer recess608may have an opening greater than that of the bottom epitaxial structure recess24. The varactor upper structure5comprises a varactor middle epitaxial structure mesa7(2), a varactor protection layer66(2), a varactor top electrode55and a varactor bottom electrode54. The middle epitaxial structure7comprises a middle n-type graded doped layer70and a middle p-type doped layer71. The middle n-type graded doped layer70is formed on the bottom epitaxial structure22. The middle p-type doped layer71is formed on the middle n-type graded doped layer70. The varactor middle epitaxial structure mesa7(2) comprises the middle n-type graded doped layer70and the middle p-type doped layer71on the second part22(2) of the bottom epitaxial structure22. The varactor protection layer66(2) covers the exposed surfaces of the varactor middle epitaxial structure mesa7(2) and the second part22(2) of the bottom epitaxial structure22. Please also refer toFIG. 8D, the varactor protection layer66(2) comprises a varactor bottom electrode recess52and a varactor top electrode recess53. A bottom of the varactor bottom electrode recess52is defined by the second part22(2) of the bottom epitaxial structure22. A bottom of the varactor top electrode recess53is defined by the varactor middle epitaxial structure mesa7(2). The varactor bottom electrode54is formed within the varactor bottom electrode recess52on the second part22(2) of the bottom epitaxial structure22. The varactor top electrode55is formed within the varactor top electrode recess53on the varactor middle epitaxial structure mesa7(2). In current embodiment, the bottom of the varactor top electrode recess53is defined by the middle p-type doped layer71, and the varactor top electrode55is formed within the varactor top electrode recess53on the middle p-type doped layer71. The bottom epitaxial structure22comprises a bottom n-type doped layer25. The bottom of the varactor bottom electrode recess52is defined by the bottom n-type doped layer25, and the varactor bottom electrode54is formed within the varactor bottom electrode recess52on the bottom n-type doped layer25. The bottom n-type doped layer25on the second part12(2) of the semiconductor substrate12, the middle n-type graded doped layer70and the middle p-type doped layer71on the second part22(2) of the bottom epitaxial structure22, the varactor protection layer66(2), the varactor top electrode55and the varactor bottom electrode54form the varactor26.

The semiconductor substrate12is made of one material selected from the group consisting of: Si, GaAs, SiC, InP, GaN, AlN and Sapphire.

In the present invention, there are two types of applications of embodiments, a first type and a second type. In the first type of applications of embodiments, the bottom n-type doped layer25is made of InxGa1-xAs, wherein x is greater than 0 and less than 1; in a preferable embodiment, x is about 0.53; the doping concentration of the bottom n-type doped layer25is greater than or equal to 2×1018and less than or equal to 5×1019; and a thickness of the bottom n-type doped layer25is between 200 nm and 600 nm. The middle n-type graded doped layer70is made of InxGa1-xAs, wherein x is greater than 0 and less than 1; in a preferable embodiment, x is about 0.53; the doping concentration of the middle n-type graded doped layer70is greater than or equal to 1×1015and less than or equal to 5×1017; and a thickness of the middle n-type graded doped layer70is between 100 nm and 2000 nm. The middle p-type doped layer71is made of InxGa1-xAs, wherein x is greater than 0 and less than 1; in a preferable embodiment, x is about 0.53; the doping concentration of the middle p-type doped layer71is greater than or equal to 1×1019and less than or equal to 1×1020; and a thickness of the middle p-type doped layer71is between 10 nm and 150 nm. In the second type of applications of embodiments, the bottom n-type doped layer25is made of GaAs; the doping concentration of the bottom n-type doped layer25is greater than or equal to 2×1018and less than or equal to 5×1019; and a thickness of the bottom n-type doped layer25is between 200 nm and 600 nm. The middle n-type graded doped layer70is made of GaAs; the doping concentration of the middle n-type graded doped layer70is greater than or equal to 1×1015and less than or equal to 5×1017; and a thickness of the middle n-type graded doped layer70is between 100 nm and 2000 nm. The middle p-type doped layer71is made of GaAs; the doping concentration of the middle p-type doped layer71is greater than or equal to 1×1019and less than or equal to 1×1020; and a thickness of the middle p-type doped layer71is between 10 nm and 150 nm.

The present invention further provides a method for fabricating an integrated structure of acoustic wave device and varactor. Please refer toFIGS. 8A-8F, which are the cross-sectional schematics showing steps of an embodiment of a method for fabricating an integrated structure of acoustic wave device and varactor of the present invention. The method fabricates the embodiment as shown inFIG. 8G. The method comprises a following step of: (please referring toFIG. 8AandFIG. 8G) Step F1: forming an acoustic wave device50and a varactor26on a first part12(1) and a second part12(2) of a semiconductor substrate12respectively. The Step F1comprises following steps of: Step F11: forming a bottom epitaxial structure22on the semiconductor substrate12, wherein the bottom epitaxial structure includes a first part22(1) and a second part22(2) of the bottom epitaxial structure22formed on the first part12(1) and the second part12(2) of the semiconductor substrate12respectively; and Step F12: forming an acoustic wave device upper structure4and a varactor upper structure5on the first part22(1) and the second part22(2) of the bottom epitaxial structure22respectively. The acoustic wave device50comprises the acoustic wave device upper structure4and the first part22(1) of the bottom epitaxial structure22. The varactor26comprises the varactor upper structure5and the second part22(2) of the bottom epitaxial structure22. The Step F12comprises a following step: Step F121: forming a middle epitaxial structure7on the bottom epitaxial structure22. InFIG. 8A, the middle epitaxial structure7comprises a middle n-type graded doped layer70and a middle p-type doped layer71. The Step F121comprises following steps of: forming the middle n-type graded doped layer70on the bottom epitaxial structure22; and forming the middle p-type doped layer71on the middle n-type graded doped layer70. In current embodiment, the bottom epitaxial structure22comprises a bottom n-type doped layer25. The Step F11comprises a following step of: forming a bottom n-type doped layer25on the semiconductor substrate12. Please refer toFIG. 8B, the Step F12further comprises a following step of: Step F122(case a): defining a middle epitaxial structure etching area, and etching the middle epitaxial structure7within the middle epitaxial structure etching area to form an acoustic wave device middle epitaxial structure mesa7(1) on the first part22(1) of the bottom epitaxial structure22and a varactor middle epitaxial structure mesa7(2) on the second part22(2) of the bottom epitaxial structure22respectively. The Step F122comprises following steps of: defining a middle p-type doped layer etching area, and etching the middle p-type doped layer71within the middle p-type doped layer etching area; and defining a middle n-type graded doped layer etching area, and etching the middle n-type graded doped layer70within the middle n-type graded doped layer etching area, thereby the acoustic wave device middle epitaxial structure mesa7(1) and the varactor middle epitaxial structure mesa7(2) are formed on the first part22(1) and the second part22(2) of the bottom epitaxial structure22respectively; wherein the acoustic wave device middle epitaxial structure mesa7(1) comprises the middle n-type graded doped layer70and the middle p-type doped layer71on the first part22(1) of the bottom epitaxial structure22; and wherein the varactor middle epitaxial structure mesa7(2) comprises the middle n-type graded doped layer70and the middle p-type doped layer71on the second part22(2) of the bottom epitaxial structure22. Please refer toFIG. 8C, the Step F12further comprises a following step of: forming an acoustic wave device protection layer66(1) and a varactor protection layer66(2); wherein the acoustic wave device protection layer66(1) covers the exposed surfaces of the first part22(1) of the bottom epitaxial structure22and the acoustic wave device middle epitaxial structure mesa7(1), wherein the acoustic wave device protection layer66(1) covers the acoustic wave device middle epitaxial structure mesa7(1) to form an acoustic wave device protection layer mesa607; and wherein the varactor protection layer66(2) covers the exposed surfaces of the second part22(2) of the bottom epitaxial structure22and the varactor middle epitaxial structure mesa7(2), wherein the varactor protection layer66(2) covers the varactor middle epitaxial structure mesa7(2) to form a varactor protection layer mesa609. Please refer toFIG. 8D, the Step F12further comprises a following step of: etching the varactor protection layer66(2) to form a varactor bottom electrode recess52and a varactor top electrode recess53respectively. A bottom of the varactor bottom electrode recess52is defined by the second part22(2) of the bottom epitaxial structure22such that part of the second part22(2) of the bottom epitaxial structure22is exposed through the varactor bottom electrode recess52. A bottom of the varactor top electrode recess53is defined by the varactor middle epitaxial structure mesa7(2) such that part of the varactor middle epitaxial structure mesa7(2) is exposed through the varactor top electrode recess53. Please refer toFIG. 8E, the Step F12further comprises following steps of: forming a varactor top electrode55on the varactor middle epitaxial structure mesa7(2) within the varactor top electrode recess53; forming a varactor bottom electrode54on the second part22(2) of the bottom epitaxial structure22within the varactor bottom electrode recess52; and forming an acoustic wave resonance structure64on the acoustic wave device protection layer mesa607, which comprises following steps of: forming an acoustic wave device bottom electrode604on the acoustic wave device protection layer mesa607; forming a dielectric layer605on the acoustic wave device bottom electrode604; and forming an acoustic wave device top electrode606on the dielectric layer605. The varactor upper structure5comprises the varactor middle epitaxial structure mesa7(2), the varactor protection layer66(2), the varactor top electrode55and the varactor bottom electrode54. In current embodiment, the bottom n-type doped layer25on the second part12(2) of the semiconductor substrate12, the middle n-type graded doped layer70and the middle p-type doped layer71on the second part22(2) of the bottom epitaxial structure22, the varactor protection layer66(2), the varactor top electrode55and the varactor bottom electrode54form the varactor26. The acoustic wave resonance structure64comprises the acoustic wave device bottom electrode604, the dielectric layer605and the acoustic wave device top electrode606. The Step F12further comprises a following step of: defining at least one recess etching area, and etching the acoustic wave device protection layer66(1) within the at least one recess etching area or etching the acoustic wave device protection layer66(1) and the acoustic wave resonance structure64within the at least one recess etching area such that the etching stops at the acoustic wave device middle epitaxial structure mesa7(1) and/or the first part22(1) of the bottom epitaxial structure22to form at least one etching recess, thereby part of the acoustic wave device middle epitaxial structure mesa7(1) is exposed. Although in current embodiment, the at least one etching recess is not shown inFIG. 8EorFIG. 8F, the structure of the at least one etching recess may be similar to the structure of the at least one etching recess62inFIG. 1GorFIG. 1H. Please refer toFIG. 8F, the Step F12further comprises a following step of: etching the acoustic wave device middle epitaxial structure mesa7(1) to form an acoustic wave device protection layer recess608, wherein at least one middle epitaxial structure etching solution contacts with the acoustic wave device middle epitaxial structure mesa7(1) via the at least one etching recess and etches and removes the acoustic wave device middle epitaxial structure mesa7(1), thereby a top and a bottom of the acoustic wave device protection layer recess608are the acoustic wave device protection layer66(1) and the first part22(1) of the bottom epitaxial structure22respectively. Please refer toFIG. 8G, the Step F1further comprises a following step of: etching the first part22(1) of the bottom epitaxial structure22below the acoustic wave device protection layer recess608to form a bottom epitaxial structure recess24, wherein a bottom of the bottom epitaxial structure recess24is the first part22(1) of the bottom epitaxial structure22, wherein at least one bottom epitaxial structure etching solution contacts with a top surface of the first part22(1) of the bottom epitaxial structure22via the at least one etching recess and the acoustic wave device protection layer recess608, the at least one bottom epitaxial structure etching solution is uniformly distributed on the top surface of the first part22(1) of the bottom epitaxial structure22through the acoustic wave device protection layer recess608so as to uniformly etch part of the first part22(1) of the bottom epitaxial structure22below the acoustic wave device protection layer recess608to form the bottom epitaxial structure recess24, and thereby prevents the side etching phenomenon during the etching, wherein the acoustic wave device protection layer recess608is communicated with the bottom epitaxial structure recess24, and the acoustic wave device protection layer recess608and the bottom epitaxial structure recess24have a boundary104therebetween and the boundary104is extended from the top surface of the first part22(1) of the bottom epitaxial structure22, wherein a gap between the acoustic wave device protection layer66(1) and the bottom of the bottom epitaxial structure recess24is increased by the communication of the acoustic wave device protection layer recess608and the bottom epitaxial structure recess24, so as to avoid the contact of the acoustic wave device protection layer66(1) and the bottom of the bottom epitaxial structure recess when the acoustic wave device50is affected by stress such that the acoustic wave device protection layer66(1) is bended downwardly. The integrated structure of the acoustic wave device50and the varactor26formed on the same the semiconductor substrate12is capable of reducing the module size, optimizing the impedance matching, and reducing the signal loss between the varactor26and the acoustic wave device50. In some embodiments, the acoustic wave device protection layer recess608has an opening smaller than or equal to that of the bottom epitaxial structure recess24. In another embodiment, the acoustic wave device protection layer recess608may have an opening greater than that of the bottom epitaxial structure recess24.

Please refer toFIG. 8H, which is the cross-sectional schematic showing another embodiment of an integrated structure of acoustic wave device and varactor of the present invention. The Step F1further comprises a following step of: forming an isolation structure23between the varactor26and the acoustic wave device50. The main structure inFIG. 8His basically the same as the structure shown inFIG. 8G, except that the isolation structure23is formed between the varactor26and the acoustic wave device50. The varactor26and the acoustic wave device50are electrically isolated by the isolation structure23.

Please refer toFIG. 8I, which is the cross-sectional schematic showing another embodiment of an integrated structure of acoustic wave device and varactor of the present invention. The main structure inFIG. 8Iis basically the same as the structure shown inFIG. 8H, except that the varactor middle epitaxial structure mesa7(2) further comprises a varactor ledge layer72formed on the middle p-type doped layer71. The Step F121further comprises a following step of: forming a varactor ledge layer72on the middle p-type doped layer71. The Step F122further comprises a following step of: defining a varactor ledge layer etching area, and etching the varactor ledge layer72within the varactor ledge layer etching area; wherein the varactor middle epitaxial structure mesa7(2) comprises the middle n-type graded doped layer70, the middle p-type doped layer71and the varactor ledge layer72on the second part22(2) of the bottom epitaxial structure22. In the first type of applications of embodiments, the varactor ledge layer72is made of InxGa1-xAs, wherein x is greater than 0 and less than 1; in a preferable embodiment, x is about 0.53; the varactor ledge layer72is n-type doped and the doping concentration of the varactor ledge layer72is greater than or equal to 5×1016and less than or equal to 5×1017; and a thickness of the varactor ledge layer72is between 1 nm and 60 nm. In the second type of applications of embodiments, the varactor ledge layer72is made of InxGa1-xP, wherein x is greater than 0 and less than 1; in a preferable embodiment, x is about 0.48; the varactor ledge layer72is n-type doped and the doping concentration of the varactor ledge layer72is greater than or equal to 5×1016and less than or equal to 5×1017; and a thickness of the varactor ledge layer72is between 1 nm and 60 nm.

Please refer toFIG. 8J, which is the cross-sectional schematic showing another embodiment of an integrated structure of acoustic wave device and varactor of the present invention. The main structure inFIG. 8Jis basically the same as the structure shown inFIG. 8H, except that the bottom epitaxial structure22further comprises an etching stop layer27. The etching stop layer27is formed on the bottom n-type doped layer25, wherein the bottom epitaxial structure22comprises the bottom n-type doped layer25and the etching stop layer27. The Step F11further comprises following steps of: forming an etching stop layer27on the bottom n-type doped layer25; and etching the etching stop layer27to form the varactor bottom electrode recess52on the second part22(2) of the bottom epitaxial structure22such that the bottom of the varactor bottom electrode recess52is the second part22(2) of the bottom epitaxial structure22; wherein the varactor bottom electrode54is formed on the bottom n-type doped layer25within the varactor bottom electrode recess52. In the first type of applications of embodiments, the etching stop layer27is made of InP; the etching stop layer27is n-type doped and the doping concentration of etching stop layer27is greater than or equal to 2×1018and less than or equal to 5×1019; and a thickness of the varactor ledge layer72is between 1 nm and 40 nm. In the second type of applications of embodiments, the etching stop layer27is made of InxGa1-xP, wherein x is greater than 0 and less than 1; in a preferable embodiment, x is about 0.48; the etching stop layer27is n-type doped and the doping concentration of etching stop layer27is greater than or equal to 2×1018and less than or equal to 5×1019; and a thickness of the varactor ledge layer72is between 1 nm and 40 nm.

Please refer toFIG. 8K, which is the cross-sectional schematic showing another embodiment of an integrated structure of acoustic wave device and varactor of the present invention. The main structure inFIG. 8Kis basically the same as the structure shown inFIG. 8J, except that the varactor middle epitaxial structure mesa7(2) further comprises a varactor ledge layer72formed on the middle p-type doped layer71. The Step F121further comprises a following step of: forming a varactor ledge layer72on the middle p-type doped layer71. The Step F122further comprises a following step of: defining a varactor ledge layer etching area, and etching the varactor ledge layer72within the varactor ledge layer etching area; wherein the varactor middle epitaxial structure mesa7(2) comprises the middle n-type graded doped layer70, the middle p-type doped layer71and the varactor ledge layer72on the second part22(2) of the bottom epitaxial structure22. In the first type of applications of embodiments, the varactor ledge layer72is made of InxGa1-xAs, wherein x is greater than 0 and less than 1; in a preferable embodiment, x is about 0.53; the varactor ledge layer72is n-type doped and the doping concentration of the varactor ledge layer72is greater than or equal to 5×1016and less than or equal to 5×1017; and a thickness of the varactor ledge layer72is between 1 nm and 60 nm. In the second type of applications of embodiments, the varactor ledge layer72is made of InxGa1-xP, wherein x is greater than 0 and less than 1; in a preferable embodiment, x is about 0.48; the varactor ledge layer72is n-type doped and the doping concentration of the varactor ledge layer72is greater than or equal to 5×1016and less than or equal to 5×1017; and a thickness of the varactor ledge layer72is between 1 nm and 60 nm.

Please refer toFIG. 8L, which is the cross-sectional schematic showing another embodiment of an integrated structure of acoustic wave device and varactor of the present invention. The main structure inFIG. 8Lis basically the same as the structure shown inFIG. 8K, except that the bottom of the bottom epitaxial structure recess24is defined by the semiconductor substrate12, thereby the gap between the acoustic wave device protection layer66(1) and the bottom of the bottom epitaxial structure recess24is further increased.

Please refer toFIG. 8Nis the cross-sectional schematic showing another embodiment of an integrated structure of acoustic wave device and varactor of the present invention. The main structure inFIG. 8Nis basically the same as the structure shown inFIG. 8H, except that the acoustic wave device upper structure4comprises an auxiliary layer280, a dielectric layer28and an interdigital transducer electrode29, wherein the auxiliary layer280is formed on the first part22(1) of the bottom epitaxial structure22, the dielectric layer28is formed on the auxiliary layer280, wherein the interdigital transducer electrode29is formed on the dielectric layer28, and wherein the first part22(1) of the bottom epitaxial structure22has no bottom epitaxial structure recess24. In current embodiment, the acoustic wave device50may be a surface acoustic wave device. The integrated structure of the acoustic wave device50and the varactor26formed on the same the semiconductor substrate12is capable of reducing the module size, optimizing the impedance matching, and reducing the signal loss between the varactor26and the acoustic wave device50.

Please refer toFIGS. 8A, 8M and 8N, which are the cross-sectional schematics showing steps of an embodiment of a method for fabricating an integrated structure of acoustic wave device and varactor of the present invention. The method fabricates the embodiment as shown inFIG. 8N. The method for fabricating the embodiment ofFIG. 8Nis basically the same as the method for fabricating the embodiment ofFIG. 8H(that is the method for fabricating the varactor26on the second part12(2) of the semiconductor substrate12of the embodiment ofFIG. 8Nis basically the same as the method for fabricating the varactor26on the second part12(2) of the semiconductor substrate12of the embodiment ofFIG. 8H, while the method for fabricating the acoustic wave device50on the first part12(1) of the semiconductor substrate12of the embodiment ofFIG. 8Nis different from the method for fabricating the acoustic wave device50on the first part12(1) of the semiconductor substrate12of the embodiment ofFIG. 8H), except that the Step F122(case b) is modified as following: defining a middle epitaxial structure etching area, and etching the middle epitaxial structure7within the middle epitaxial structure etching area to form a varactor middle epitaxial structure mesa7(2) on the second part22(2) of the bottom epitaxial structure22(therefore, there is no such an acoustic wave device middle epitaxial structure mesa7(1) formed on the first part22(1) of the bottom epitaxial structure22as shown inFIG. 8B, the first part of the middle epitaxial structure7on the first part22(1) of the bottom epitaxial structure22is etched and removed); in the Step F12, forming the acoustic wave device upper structure4on the first part22(1) of the bottom epitaxial structure22comprises following steps of: forming an auxiliary layer280on the first part22(1) of the bottom epitaxial structure22; forming a dielectric layer28on the auxiliary layer280; and forming an interdigital transducer electrode29on the dielectric layer28; and in the Step F1, there is no such a step to etch the first part22(1) of the bottom epitaxial structure22to form the bottom epitaxial structure recess24. In the embodiment ofFIG. 8N, the acoustic wave device upper structure4comprises the auxiliary layer280, the dielectric layer28and the interdigital transducer electrode29. The acoustic wave device50may be a surface acoustic wave device. In the embodiment ofFIG. 8N, the structure of the varactor26is basically the same structure as the structure of the varactor26in the embodiment ofFIG. 8H.

Please refer toFIGS. 8B, 8I and 8O, which are the cross-sectional schematics showing steps of an embodiment of a method for fabricating an integrated structure of acoustic wave device and varactor of the present invention. The method fabricates the embodiment as shown inFIG. 8I. InFIG. 8B, the varactor middle epitaxial structure mesa7(2) comprises the middle n-type graded doped layer70and the middle p-type doped layer71on the second part22(2) of the bottom epitaxial structure22. The acoustic wave device middle epitaxial structure mesa7(1) comprises the middle n-type graded doped layer70and the middle p-type doped layer71on the first part22(1) of the bottom epitaxial structure22. To form the structure ofFIG. 8O, the Step F121may further comprise a following step of: forming a varactor ledge layer72on the middle p-type doped layer71. And the Step F122may further comprise a following step of: defining a varactor ledge layer etching area, and etching the varactor ledge layer72within the varactor ledge layer etching area. Then the structure ofFIG. 8Omay be fabricated. InFIG. 8O, the varactor middle epitaxial structure mesa7(2) comprises the middle n-type graded doped layer70, the middle p-type doped layer71and the varactor ledge layer72on the second part22(2) of the bottom epitaxial structure22. The acoustic wave device middle epitaxial structure mesa7(1) comprises the middle n-type graded doped layer70, the middle p-type doped layer71and the varactor ledge layer72on the first part22(1) of the bottom epitaxial structure22. Therefore, after forming the acoustic wave device protection layer66(1) and the varactor protection layer66(2), the acoustic wave device protection layer mesa607and the varactor protection layer mesa609may have the same height (as shown inFIG. 8I).

Please refer toFIGS. 8P, 8Q and 8R, which are the cross-sectional schematics showing steps of an embodiment of a method for fabricating an integrated structure of acoustic wave device and varactor of the present invention. The method fabricates the embodiment as shown inFIG. 8R. The main structure inFIG. 8Ris basically the same as the structure shown inFIG. 8I, except that a height of the varactor protection layer mesa609is greater than a height of the acoustic wave device protection layer mesa607. To form the structure ofFIG. 8Pfrom the structure ofFIG. 8O, the Step F12may further comprise a following step of: etching the varactor ledge layer72of the acoustic wave device middle epitaxial structure mesa7(1) such that the acoustic wave device middle epitaxial structure mesa7(1) comprises the middle n-type graded doped layer70and the middle p-type doped layer71on the first part22(1) of the bottom epitaxial structure22, while the varactor middle epitaxial structure mesa7(2) comprises the middle n-type graded doped layer70, the middle p-type doped layer71and the varactor ledge layer72on the second part22(2) of the bottom epitaxial structure22. To form the structure ofFIG. 8Qfrom the structure ofFIG. 8P, the Step F12may further comprise a following step of: etching the middle p-type doped layer71of the acoustic wave device middle epitaxial structure mesa7(1) such that the acoustic wave device middle epitaxial structure mesa7(1) comprises the middle n-type graded doped layer70on the first part22(1) of the bottom epitaxial structure22, while the varactor middle epitaxial structure mesa7(2) comprises the middle n-type graded doped layer70, the middle p-type doped layer71and the varactor ledge layer72on the second part22(2) of the bottom epitaxial structure22. The structure ofFIG. 8Rmay be formed from the structure ofFIG. 8PorFIG. 8Q. And therefore, after forming the acoustic wave device protection layer66(1) and the varactor protection layer66(2), the height of the varactor protection layer mesa609is greater than the height of the acoustic wave device protection layer mesa607(as shown inFIG. 8R).

Please refer toFIG. 8S, which is the cross-sectional schematic showing an embodiment of an integrated structure of acoustic wave device and varactor of the present invention. The main structure inFIG. 8Sis basically the same as the structure shown inFIG. 8H, except that an auxiliary layer610is inserted between the acoustic wave device protection layer mesa607and the acoustic wave device bottom electrode604, wherein the auxiliary layer610is formed on the acoustic wave device protection layer mesa607and the acoustic wave device bottom electrode604is formed on the auxiliary layer610. Similarly the auxiliary layer610may be introduced and inserted between the acoustic wave device protection layer mesa607and the acoustic wave device bottom electrode604in the embodiments ofFIGS. 8G, 8I, 8J, 8K, 8L and 8R.

Please refer toFIG. 9G, which is the cross-sectional schematic showing an embodiment of an integrated structure of acoustic wave device, varactor and heterojunction bipolar transistor of the present invention. The present invention further provides an integrated structure of acoustic wave device, varactor and heterojunction bipolar transistor. The integrated structure comprises a semiconductor substrate12, an acoustic wave device50, a varactor26, an heterojunction bipolar transistor middle epitaxial structure mesa7(3) and an heterojunction bipolar transistor30. The semiconductor substrate12includes a first part12(1), a second part12(2) and a third part12(3) of the semiconductor substrate12. The acoustic wave device50and the varactor26are formed on the first part12(1) and the second part12(2) of the semiconductor substrate12respectively. The acoustic wave device50comprises an acoustic wave device upper structure4and a first part22(1) of a bottom epitaxial structure22, wherein the bottom epitaxial structure22is formed on the semiconductor substrate12, wherein the bottom epitaxial structure22includes the first part22(1), a second part22(2) and a third part22(3) of the bottom epitaxial structure22, wherein the first part22(1), the second part22(2) and the third part22(3) of the bottom epitaxial structure22are formed on the first part12(1), the second part12(2) and the third part12(3) of the semiconductor substrate12respectively, and wherein the acoustic wave device upper structure4is formed on the first part22(1) of the bottom epitaxial structure22. The varactor26comprises a varactor upper structure5and the second part22(2) of the bottom epitaxial structure22, wherein the varactor upper structure5is formed on the second part22(2) of the bottom epitaxial structure22. The heterojunction bipolar transistor middle epitaxial structure mesa7(3) is formed on the third part22(3) of the bottom epitaxial structure22. The heterojunction bipolar transistor30is formed on the heterojunction bipolar transistor middle epitaxial structure mesa7(3). In current embodiment, the acoustic wave device50may be a bulk acoustic wave device. The integrated structure of the acoustic wave device50, the varactor26and the heterojunction bipolar transistor30formed on the same the semiconductor substrate12is capable of reducing the module size, optimizing the impedance matching, and reducing the signal loss between the varactor26, the acoustic wave device50and the heterojunction bipolar transistor30. The first part22(1) of the bottom epitaxial structure22comprises a bottom epitaxial structure recess24on the top of the bottom epitaxial structure22. A bottom of the bottom epitaxial structure recess24is the bottom epitaxial structure22(In another embodiment, the bottom of the bottom epitaxial structure recess24may be the semiconductor substrate12, which is similar to the embodiment ofFIG. 8L). The acoustic wave device upper structure4comprises an acoustic wave device protection layer66(1) and an acoustic wave resonance structure64. The acoustic wave device protection layer66(1) is formed on the first part22(1) of the bottom epitaxial structure22. The acoustic wave device protection layer66(1) comprises an acoustic wave device protection layer recess608on the bottom of the acoustic wave device protection layer66(1) and an upwardly protruding acoustic wave device protection layer mesa607right above the acoustic wave device protection layer recess608. The acoustic wave device protection layer recess608is located right above the bottom epitaxial structure recess24, and the acoustic wave device protection layer recess608is communicated with the bottom epitaxial structure recess24, and wherein the acoustic wave device protection layer recess608and the bottom epitaxial structure recess24have a boundary104therebetween and the boundary104is extended from a top surface of the bottom epitaxial structure22. The acoustic wave resonance structure64is formed on the acoustic wave device protection layer mesa607. The acoustic wave resonance structure64comprises an acoustic wave device bottom electrode604, a dielectric layer605and an acoustic wave device top electrode606. The acoustic wave device bottom electrode604is formed on the acoustic wave device protection layer mesa607. The dielectric layer605is formed on the acoustic wave device bottom electrode604. The acoustic wave device top electrode606is formed on the dielectric layer605. A gap between the acoustic wave device protection layer66(1) and the bottom of the bottom epitaxial structure recess24is increased by the communication of the acoustic wave device protection layer recess608and the bottom epitaxial structure recess24, so as to avoid the contact of the acoustic wave device protection layer66(1) and the bottom of the bottom epitaxial structure recess24when the acoustic wave device50is affected by stress such that the acoustic wave device protection layer66(1) is bended downwardly. In some embodiments, the acoustic wave device protection layer recess608has an opening smaller than or equal to that of the bottom epitaxial structure recess24. In another embodiment, the acoustic wave device protection layer recess608may have an opening greater than that of the bottom epitaxial structure recess24. The varactor upper structure5comprises a varactor middle epitaxial structure mesa7(2), a varactor protection layer66(2), a varactor top electrode55and a varactor bottom electrode54. The middle epitaxial structure7comprises a middle n-type graded doped layer70and a middle p-type doped layer71. The middle n-type graded doped layer70is formed on the bottom epitaxial structure22. The middle p-type doped layer71is formed on the middle n-type graded doped layer70. The varactor middle epitaxial structure mesa7(2) comprises the middle n-type graded doped layer70and the middle p-type doped layer71on the second part22(2) of the bottom epitaxial structure22. The varactor protection layer66(2) covers the exposed surfaces of the varactor middle epitaxial structure mesa7(2) and the second part22(2) of the bottom epitaxial structure22. Please also refer toFIG. 9D, the varactor protection layer66(2) comprises a varactor bottom electrode recess52and a varactor top electrode recess53. A bottom of the varactor bottom electrode recess52is defined by the second part22(2) of the bottom epitaxial structure22. A bottom of the varactor top electrode recess53is defined by the varactor middle epitaxial structure mesa7(2). The varactor bottom electrode54is formed within the varactor bottom electrode recess52on the second part22(2) of the bottom epitaxial structure22. The varactor top electrode55is formed within the varactor top electrode recess53on the varactor middle epitaxial structure mesa7(2). In current embodiment, the bottom of the varactor top electrode recess53is defined by the middle p-type doped layer71, and the varactor top electrode55is formed within the varactor top electrode recess53on the middle p-type doped layer71. The bottom epitaxial structure22comprises a bottom n-type doped layer25. The bottom of the varactor bottom electrode recess52is defined by the bottom n-type doped layer25, and the varactor bottom electrode54is formed within the varactor bottom electrode recess52on the bottom n-type doped layer25. The bottom n-type doped layer25on the second part12(2) of the semiconductor substrate12, the middle n-type graded doped layer70and the middle p-type doped layer71on the second part22(2) of the bottom epitaxial structure22, the varactor protection layer66(2), the varactor top electrode55and the varactor bottom electrode54form the varactor26. The heterojunction bipolar transistor middle epitaxial structure mesa7(3) comprises the middle n-type graded doped layer70and the middle p-type doped layer71on the third part22(3) of the bottom epitaxial structure22. The heterojunction bipolar transistor30comprises a top epitaxial structure mesa8(3), an heterojunction bipolar transistor protection layer66(3), a collector electrode37, a base electrode38and an emitter electrode39. The top epitaxial structure mesa8(3) comprises a subcollector layer80, a collector layer82, a base layer83and an emitter layer85. The subcollector layer80is formed on the heterojunction bipolar transistor middle epitaxial structure mesa7(3). The collector layer82is formed on the subcollector layer80. The base layer83is formed on the collector layer82. The emitter layer85is formed on the base layer83. The heterojunction bipolar transistor protection layer66(3) covers the exposed surfaces of the top epitaxial structure mesa8(3), the heterojunction bipolar transistor middle epitaxial structure mesa7(3) and the third part22(3) of the bottom epitaxial structure22. Please also refer toFIG. 9D, the heterojunction bipolar transistor protection layer66(3) comprises a collector electrode recess67, a base electrode recess68and an emitter electrode recess69. A bottom of the collector electrode recess67is defined by the subcollector layer80. A bottom of the base electrode recess68is defined by the base layer83. A bottom of the emitter electrode recess69is defined by the emitter layer85. The collector electrode37is formed within the collector electrode recess67on the subcollector layer80. The base electrode38is formed within the base electrode recess68on the base layer83. The emitter electrode39is formed within the emitter electrode recess69on the emitter layer85.

The semiconductor substrate12is made of one material selected from the group consisting of: Si, GaAs, SiC, InP, GaN, AlN and Sapphire. There are two types of applications of embodiments, a first type and a second type. In the first type of applications of embodiments, the bottom n-type doped layer25is made of InxGa1-xAs, wherein x is greater than 0 and less than 1; in a preferable embodiment, x is about 0.53; the doping concentration of the bottom n-type doped layer25is greater than or equal to 2×1018and less than or equal to 5×1019; and a thickness of the bottom n-type doped layer25is between 200 nm and 600 nm. The middle n-type graded doped layer70is made of InxGa1-xAs, wherein x is greater than 0 and less than 1; in a preferable embodiment, x is about 0.53; the doping concentration of the middle n-type graded doped layer70is greater than or equal to 1×1015and less than or equal to 5×1017; and a thickness of the middle n-type graded doped layer70is between 100 nm and 2000 nm. The middle p-type doped layer71is made of InxGa1-xAs, wherein x is greater than 0 and less than 1; in a preferable embodiment, x is about 0.53; the doping concentration of the middle p-type doped layer71is greater than or equal to 1×1019and less than or equal to 1×1020; and a thickness of the middle p-type doped layer71is between 10 nm and 150 nm. The subcollector layer80is made of InxGa1-xAs, wherein x is greater than 0 and less than 1; in a preferable embodiment, x is about 0.53; the subcollector layer80is n-type doped and the doping concentration of the subcollector layer80is greater than or equal to 2×1018and less than or equal to 5×1019; and a thickness of the subcollector layer80is between 200 nm and 600 nm. The collector layer82is made of InxGa1-xAs, wherein x is greater than 0 and less than 1; in a preferable embodiment, x is about 0.53; the collector layer82is n-type doped and the doping concentration of the collector layer82is greater than or equal to 1×1015and less than or equal to 5×1017; and a thickness of the collector layer82is between 100 nm and 2000 nm. The base layer83is made of InxGa1-xAs, wherein x is greater than 0 and less than 1; in a preferable embodiment, x is about 0.53; the base layer83is p-type doped and the doping concentration of the base layer83is greater than or equal to 1×1019and less than or equal to 1×1020; and a thickness of the base layer83is between 10 nm and 150 nm. The emitter layer85is made of InP; the emitter layer85is n-type doped and the doping concentration of emitter layer85is greater than or equal to 2×1018and less than or equal to 5×1019; and a thickness of the emitter layer85is between 100 nm and 500 nm. In the second type of applications of embodiments, the bottom n-type doped layer25is made of GaAs; the doping concentration of the bottom n-type doped layer25is greater than or equal to 2×1018and less than or equal to 5×1019; and a thickness of the bottom n-type doped layer25is between 200 nm and 600 nm. The middle n-type graded doped layer70is made of GaAs; the doping concentration of the middle n-type graded doped layer70is greater than or equal to 1×1015and less than or equal to 5×1017; and a thickness of the middle n-type graded doped layer70is between 100 nm and 2000 nm. The middle p-type doped layer71is made of GaAs; the doping concentration of the middle p-type doped layer71is greater than or equal to 1×1019and less than or equal to 1×1020; and a thickness of the middle p-type doped layer71is between 10 nm and 150 nm. The subcollector layer80is made of GaAs; the subcollector layer80is n-type doped and the doping concentration of the subcollector layer80is greater than or equal to 2×1018and less than or equal to 5×1019; and a thickness of the subcollector layer80is between 200 nm and 600 nm. The collector layer82is made of GaAs; the collector layer82is n-type doped and the doping concentration of the collector layer82is greater than or equal to 1×1015and less than or equal to 5×1017; and a thickness of the collector layer82is between 100 nm and 2000 nm. The base layer83is made of GaAs; the base layer83is p-type doped and the doping concentration of the base layer83is greater than or equal to 1×1019and less than or equal to 1×1020; and a thickness of the base layer83is between 10 nm and 150 nm. The emitter layer85is made of GaAs; the emitter layer85is n-type doped and the doping concentration of the emitter layer85is greater than or equal to 2×1018and less than or equal to 5×1019; and a thickness of the emitter layer85is between 100 nm and 500 nm.

The present invention further provides a method for fabricating an integrated structure of acoustic wave device, varactor and heterojunction bipolar transistor. Please refer toFIGS. 9A˜9F, which are the cross-sectional schematics showing steps of an embodiment of a method for fabricating an integrated structure of acoustic wave device, varactor and heterojunction bipolar transistor of the present invention. The method fabricates the embodiment as shown inFIG. 9G. The method comprises following a step of: (please referring toFIG. 9AandFIG. 9G) Step G1: forming an acoustic wave device50, a varactor26and an heterojunction bipolar transistor30on a first part12(1), a second part12(2) and a third part12(3) of a semiconductor substrate12respectively, wherein the Step G1comprises following steps of: Step G11: forming a bottom epitaxial structure22on the semiconductor substrate12, wherein the bottom epitaxial structure22includes a first part22(1), a second part22(2) and a third part22(3) of the bottom epitaxial structure22; wherein the first part22(1), the second part22(2) and the third part22(3) of the bottom epitaxial structure22are formed on the first part12(1), the second part12(2) and the third part12(3) of the semiconductor substrate12respectively; Step G12: forming a middle epitaxial structure7on the bottom epitaxial structure22, wherein the middle epitaxial structure7includes a first part, a second part and a third part of the middle epitaxial structure7. The first part, the second part and the third part of the middle epitaxial structure7are formed on the first part22(1), the second part22(2) and the third part22(3) of the bottom epitaxial structure22; Step G13: etching the middle epitaxial structure7and forming an acoustic wave device upper structure4, a varactor upper structure5and an heterojunction bipolar transistor middle epitaxial structure mesa7(3) on the first part22(1), the second part22(2) and the third part22(3) of the bottom epitaxial structure22respectively, wherein the acoustic wave device50comprises the acoustic wave device upper structure4and the first part22(1) of the bottom epitaxial structure22, wherein the varactor26comprises the varactor upper structure5and the second part22(2) of the bottom epitaxial structure22, wherein the heterojunction bipolar transistor middle epitaxial structure mesa7(3) is formed by etching the third part of the middle epitaxial structure7; and Step G14: forming an heterojunction bipolar transistor30on the heterojunction bipolar transistor middle epitaxial structure mesa7(3). To form the structure ofFIG. 9A, the Step G11comprises a following step of: forming a bottom n-type doped layer25on the semiconductor substrate12, wherein the bottom epitaxial structure22comprises the bottom n-type doped layer25; the Step G12further comprises following steps of: forming a middle n-type graded doped layer70on the bottom epitaxial structure22; and forming a middle p-type doped layer71on the middle n-type graded doped layer70, wherein the middle epitaxial structure7comprises the middle n-type graded doped layer70and the middle p-type doped layer71; and the Step G14comprises a following step of: forming a top epitaxial structure8on the middle epitaxial structure7, which comprises following steps of: forming a subcollector layer80on the middle epitaxial structure7; forming a collector layer82on the subcollector layer80; forming a base layer83on the collector layer82; and forming an emitter layer85on the base layer83. Please refer toFIG. 9B, the Step G14further comprises a following step of: defining a top epitaxial structure etching area, and etching the top epitaxial structure8within the top epitaxial structure etching area to form a top epitaxial structure mesa8(3), wherein the top epitaxial structure mesa8(3) comprises the subcollector layer80, the collector layer82, the base layer83and the emitter layer85(this step may include following steps of: defining an emitter layer etching area, and etching the emitter layer85within the emitter layer etching area; defining a base layer etching area, and etching the base layer83within the base layer etching area; defining a collector layer etching area, and etching the collector layer82within the collector layer etching area; and defining a subcollector layer etching area, and etching the subcollector layer80within the subcollector layer etching area). The Step G13(case a) comprises following steps of: defining a middle p-type doped layer etching area, and etching the middle p-type doped layer71within the middle p-type doped layer etching area; and defining a middle n-type graded doped layer etching area, and etching the middle n-type graded doped layer70within the middle n-type graded doped layer etching area, thereby an acoustic wave device middle epitaxial structure mesa7(1), a varactor middle epitaxial structure mesa7(2) and the heterojunction bipolar transistor middle epitaxial structure mesa7(3) are formed on the first part22(1), the second part22(2) and the third part22(3) of the bottom epitaxial structure22respectively, wherein the acoustic wave device middle epitaxial structure mesa7(1) comprises the middle n-type graded doped layer70and the middle p-type doped layer71on the first part22(1) of the bottom epitaxial structure22, wherein the varactor middle epitaxial structure mesa7(2) comprises the middle n-type graded doped layer70and the middle p-type doped layer71on the second part22(2) of the bottom epitaxial structure22, wherein the heterojunction bipolar transistor middle epitaxial structure mesa7(3) comprises the middle n-type graded doped layer70and the middle p-type doped layer71on the third part22(3) of the bottom epitaxial structure22, wherein the top epitaxial structure mesa8(3) is formed on the heterojunction bipolar transistor middle epitaxial structure mesa7(3). Please refer toFIG. 9C, the Step G13further comprises a following step of: forming an acoustic wave device protection layer66(1), a varactor protection layer66(2) and an heterojunction bipolar transistor protection layer66(3), wherein the acoustic wave device protection layer66(1) covers the exposed surfaces of the first part22(1) of the bottom epitaxial structure22and the acoustic wave device middle epitaxial structure mesa7(1), and wherein the acoustic wave device protection layer66(1) covers the acoustic wave device middle epitaxial structure mesa7(1) to form an acoustic wave device protection layer mesa607; wherein the varactor protection layer66(2) covers the exposed surfaces of the second part22(2) of the bottom epitaxial structure22and the varactor middle epitaxial structure mesa7(2), wherein the varactor protection layer66(2) covers the varactor middle epitaxial structure mesa7(2) to form a varactor protection layer mesa609, wherein the heterojunction bipolar transistor protection layer66(3) covers the exposed surfaces of the third part22(3) of the bottom epitaxial structure22, the heterojunction bipolar transistor middle epitaxial structure mesa7(3) and the top epitaxial structure mesa8(3). Please refer toFIG. 9D, the Step G13further comprises a following step of: etching the varactor protection layer66(2) to form a varactor bottom electrode recess52and a varactor top electrode recess53respectively. A bottom of the varactor bottom electrode recess52is defined by the second part22(2) of the bottom epitaxial structure22such that part of the second part22(2) of the bottom epitaxial structure22is exposed through the varactor bottom electrode recess52. A bottom of the varactor top electrode recess53is defined by the varactor middle epitaxial structure mesa7(2) such that part of the varactor middle epitaxial structure mesa7(2) is exposed through the varactor top electrode recess53. The Step G14further comprises a following step of: etching the heterojunction bipolar transistor protection layer66(3) to form a collector electrode recess67, a base electrode recess68and an emitter electrode recess69respectively. In current embodiment, a bottom of the collector electrode recess67is defined by the subcollector layer80; a bottom of the base electrode recess68is defined by the base layer83; and a bottom of the emitter electrode recess69is defined by the emitter layer85. Please refer toFIG. 9E, the Step G13further comprises following steps of: forming an acoustic wave resonance structure64on the acoustic wave device protection layer mesa607(the step may include following steps of: forming an acoustic wave device bottom electrode604on the acoustic wave device protection layer mesa607; forming a dielectric layer605on the acoustic wave device bottom electrode604; and forming an acoustic wave device top electrode606on the dielectric layer605), wherein the acoustic wave resonance structure64comprises the acoustic wave device bottom electrode604, the dielectric layer605and the acoustic wave device top electrode606, and wherein the acoustic wave device upper structure4comprises an acoustic wave device protection layer66(1) and an acoustic wave resonance structure64; forming a varactor top electrode55on the varactor middle epitaxial structure mesa7(2) within the varactor top electrode recess53; and forming a varactor bottom electrode54on the second part22(2) of the bottom epitaxial structure22within the varactor bottom electrode recess52, wherein the varactor upper structure5comprises the varactor middle epitaxial structure mesa7(2), the varactor protection layer66(2), the varactor top electrode55and the varactor bottom electrode54. In current embodiment, the bottom n-type doped layer25on the second part12(2) of the semiconductor substrate12, the middle n-type graded doped layer70and the middle p-type doped layer71on the second part22(2) of the bottom epitaxial structure22, the varactor protection layer66(2), the varactor top electrode55and the varactor bottom electrode54form the varactor26. The Step G14further comprises following steps of: forming an emitter electrode39on the emitter layer85within the emitter electrode recess69; forming a base electrode38on the base layer83within the base electrode recess68; and forming a collector electrode37on the subcollector layer80within the collector electrode recess67, wherein the heterojunction bipolar transistor30comprises the top epitaxial structure mesa8(3), the heterojunction bipolar transistor protection layer66(3), the emitter electrode39, the base electrode38and the collector electrode37. Please refer toFIG. 9F, the Step G13further comprises following steps of: defining at least one recess etching area, and etching the acoustic wave device protection layer66(1) within the at least one recess etching area or etching the acoustic wave device protection layer66(1) and the acoustic wave resonance structure64within the at least one recess etching area such that the etching stops at the acoustic wave device middle epitaxial structure mesa7(1) and/or the first part22(1) of the bottom epitaxial structure22to form at least one etching recess, thereby part of the acoustic wave device middle epitaxial structure mesa7(1) is exposed. Although in current embodiment, the at least one etching recess is not shown inFIG. 9F, the structure of the at least one etching recess may be similar to the structure of the at least one etching recess62inFIG. 1GorFIG. 1H. The Step G13further comprises a following step of: etching the acoustic wave device middle epitaxial structure mesa7(1) to form an acoustic wave device protection layer recess608, wherein at least one middle epitaxial structure etching solution contacts with the acoustic wave device middle epitaxial structure mesa7(1) via the at least one etching recess and etches and removes the acoustic wave device middle epitaxial structure mesa7(1), thereby a top and a bottom of the acoustic wave device protection layer recess608are the acoustic wave device protection layer66(1) and the first part22(1) of the bottom epitaxial structure22respectively. Please refer toFIG. 9G, the Step G1further comprises a following step of: etching the first part22(1) of the bottom epitaxial structure22below the acoustic wave device protection layer recess608to form a bottom epitaxial structure recess24, wherein a bottom of the bottom epitaxial structure recess24is the first part22(1) of the bottom epitaxial structure22, wherein at least one bottom epitaxial structure etching solution contacts with a top surface of the first part22(1) of the bottom epitaxial structure22via the at least one etching recess and the acoustic wave device protection layer recess608, the at least one bottom epitaxial structure etching solution is uniformly distributed on the top surface of the first part22(1) of the bottom epitaxial structure22through the acoustic wave device protection layer recess608so as to uniformly etch part of the first part22(1) of the bottom epitaxial structure22below the acoustic wave device protection layer recess608to form the bottom epitaxial structure recess24, and thereby prevents the side etching phenomenon during the etching, wherein the acoustic wave device protection layer recess608is communicated with the bottom epitaxial structure recess24, and the acoustic wave device protection layer recess608and the bottom epitaxial structure recess24have a boundary104therebetween and the boundary104is extended from the top surface of the first part22(1) of the bottom epitaxial structure22, wherein a gap between the acoustic wave device protection layer66(1) and the bottom of the bottom epitaxial structure recess24is increased by the communication of the acoustic wave device protection layer recess608and the bottom epitaxial structure recess24, so as to avoid the contact of the acoustic wave device protection layer66(1) and the bottom of the bottom epitaxial structure recess when the acoustic wave device50is affected by stress such that the acoustic wave device protection layer66(1) is bended downwardly. The integrated structure of the acoustic wave device50, the varactor26and the heterojunction bipolar transistor30formed on the same the semiconductor substrate12is capable of reducing the module size, optimizing the impedance matching, and reducing the signal loss between the heterojunction bipolar transistor30, the varactor26and the acoustic wave device50. In some embodiments, the acoustic wave device protection layer recess608has an opening smaller than or equal to that of the bottom epitaxial structure recess24. In another embodiment, the acoustic wave device protection layer recess608may have an opening greater than that of the bottom epitaxial structure recess24.

Please refer toFIG. 9H, which is the cross-sectional schematic showing another embodiment of an integrated structure of acoustic wave device, varactor and heterojunction bipolar transistor of the present invention. The Step G1further comprises a following step of: forming at least one isolation structure23between any two of the varactor26, the acoustic wave device50and the heterojunction bipolar transistor30such that any two of the varactor26, the acoustic wave device50and the heterojunction bipolar transistor30are electrically isolated by the at least one isolation structure23. The main structure inFIG. 9His basically the same as the structure shown inFIG. 9G, except that the at least one isolation structure23is formed between the varactor26and the acoustic wave device50and between the varactor26and the heterojunction bipolar transistor30. The varactor26and the acoustic wave device50are electrically isolated by the at least one isolation structure23. And the varactor26and the heterojunction bipolar transistor30are electrically isolated by the at least one isolation structure23. In some embodiments, the at least one isolation structure23is formed between the acoustic wave device50and the heterojunction bipolar transistor30. The acoustic wave device50and the heterojunction bipolar transistor30are electrically isolated by the at least one isolation structure23.

Please refer toFIG. 9I, which is the cross-sectional schematic showing another embodiment of an integrated structure of acoustic wave device, varactor and heterojunction bipolar transistor of the present invention. The main structure inFIG. 9Iis basically the same as the structure shown inFIG. 9H, except that the varactor middle epitaxial structure mesa7(2) and the heterojunction bipolar transistor middle epitaxial structure mesa7(3) further comprise a varactor ledge layer72formed on the middle p-type doped layer71. The Step G12further comprises a following step of: forming a varactor ledge layer72on the middle p-type doped layer71. The Step G13further comprises a following step of: defining a varactor ledge layer etching area, and etching the varactor ledge layer72within the varactor ledge layer etching area; wherein the varactor middle epitaxial structure mesa7(2) comprises the middle n-type graded doped layer70, the middle p-type doped layer71and the varactor ledge layer72on the second part22(2) of the bottom epitaxial structure22; and wherein the heterojunction bipolar transistor middle epitaxial structure mesa7(3) comprises the middle n-type graded doped layer70, the middle p-type doped layer71and the varactor ledge layer72on the third part22(3) of the bottom epitaxial structure22. In the first type of applications of embodiments, the varactor ledge layer72is made of InxGa1-xAs, wherein x is greater than 0 and less than 1; in a preferable embodiment, x is about 0.53; the varactor ledge layer72is n-type doped and the doping concentration of the varactor ledge layer72is greater than or equal to 5×1016and less than or equal to 5×1017; and a thickness of the varactor ledge layer72is between 1 nm and 60 nm. In the second type of applications of embodiments, the varactor ledge layer72is made of InxGa1-xP, wherein x is greater than 0 and less than 1; in a preferable embodiment, x is about 0.48; the varactor ledge layer72is n-type doped and the doping concentration of the varactor ledge layer72is greater than or equal to 5×1016and less than or equal to 5×1017; and a thickness of the varactor ledge layer72is between 1 nm and 60 nm.

Please refer toFIG. 9J, which is the cross-sectional schematic showing another embodiment of an integrated structure of acoustic wave device, varactor and heterojunction bipolar transistor of the present invention. The main structure inFIG. 9Jis basically the same as the structure shown inFIG. 9I, except that the bottom epitaxial structure22further comprises an etching stop layer27. The bottom epitaxial structure22comprises the bottom n-type doped layer25and the etching stop layer27, wherein the etching stop layer27is formed on the bottom n-type doped layer25. The Step G11further comprises following steps of: forming an etching stop layer27on the bottom n-type doped layer25; and etching the etching stop layer27to form the varactor bottom electrode recess52on the second part22(2) of the bottom epitaxial structure22such that the bottom of the varactor bottom electrode recess52is the second part22(2) of the bottom epitaxial structure22; wherein the varactor bottom electrode54is formed on the bottom n-type doped layer25within the varactor bottom electrode recess52. In the first type of applications of embodiments, the etching stop layer27is made of InP; the etching stop layer27is n-type doped and the doping concentration of etching stop layer27is greater than or equal to 2×1018and less than or equal to 5×1019; and a thickness of the varactor ledge layer72is between 1 nm and 40 nm. In the second type of applications of embodiments, the etching stop layer27is made of InxGa1-xP, wherein x is greater than 0 and less than 1; in a preferable embodiment, x is about 0.48; the etching stop layer27is n-type doped and the doping concentration of etching stop layer27is greater than or equal to 2×1018and less than or equal to 5×1019; and a thickness of the varactor ledge layer72is between 1 nm and 40 nm.

Please refer toFIG. 9K, which is the cross-sectional schematic showing another embodiment of an integrated structure of acoustic wave device, varactor and heterojunction bipolar transistor of the present invention. The main structure inFIG. 9Kis basically the same as the structure shown inFIG. 9I, except that the top epitaxial structure mesa8(3) further comprises an emitter ledge layer84. The emitter ledge layer84is formed on the base layer83, and the emitter layer85is formed on the emitter ledge layer84. The top epitaxial structure mesa8(3) comprises the subcollector layer80, the collector layer82, the base layer83, the emitter ledge layer84and the emitter layer85. The emitter ledge layer84has a base electrode recess68(please referring toFIG. 9D), and wherein a bottom of the base electrode recess68is the base layer83such that the base electrode38is formed on the base layer83within the base electrode recess68. The Step G14further comprises following steps of: forming an emitter ledge layer84on the base layer83, wherein the emitter layer85is formed on the emitter ledge layer84; and defining an emitter ledge layer etching area, and etching the emitter ledge layer84within the emitter ledge layer etching area to form a base electrode recess68, wherein a bottom of the base electrode recess68is the base layer83such that the base electrode38is formed on the base layer83within the base electrode recess68. In the first type of applications of embodiments, the emitter ledge layer84is made of InxGa1-xAs, wherein x is greater than 0 and less than 1; in a preferable embodiment, x is about 0.53; the emitter ledge layer84is n-type doped and the doping concentration of the emitter ledge layer84is greater than or equal to 5×1016and less than or equal to 5×1017; and a thickness of the emitter ledge layer84is between 1 nm and 60 nm. In the second type of applications of embodiments, the emitter ledge layer84is made of InxGa1-xP, wherein x is greater than 0 and less than 1; in a preferable embodiment, x is about 0.48; the emitter ledge layer84is n-type doped and the doping concentration of the emitter ledge layer84is greater than or equal to 5×1016and less than or equal to 5×1017; and a thickness of the emitter ledge layer84is between 1 nm and 60 nm.

Please refer toFIG. 9L, which is the cross-sectional schematic showing another embodiment of an integrated structure of acoustic wave device, varactor and heterojunction bipolar transistor of the present invention. The main structure inFIG. 9Lis basically the same as the structure shown inFIG. 9K, except that the top epitaxial structure mesa8(3) further comprises a second etching stop layer81. The second etching stop layer81is formed on the subcollector layer80. The collector layer82is formed on the second etching stop layer81. The top epitaxial structure mesa8(3) comprises the subcollector layer80, the second etching stop layer81, the collector layer82, the base layer83, the emitter ledge layer84and the emitter layer85. The second etching stop layer81has a collector electrode recess67(please referring toFIG. 9D), wherein a bottom of the collector electrode recess67is the subcollector layer80such that the collector electrode37is formed on the subcollector layer80within the collector electrode recess67. The Step G14further comprises following steps of: forming a second etching stop layer81on the subcollector layer80, wherein the collector layer82is formed on the second etching stop layer81; and defining a second etching stop layer etching area, and etching the second etching stop layer81within the second etching stop layer etching area to form a collector electrode recess67of the second etching stop layer81, wherein a bottom of the collector electrode recess67is the subcollector layer80such that the collector electrode37is formed on the subcollector layer80within the collector electrode recess67. In the first type of applications of embodiments, the second etching stop layer81is made of InP; the second etching stop layer81is n-type doped and the doping concentration of the second etching stop layer81is greater than or equal to 2×1018and less than or equal to 5×1019; and a thickness of the second etching stop layer81is between 1 nm and 40 nm. In the second type of applications of embodiments, the second etching stop layer81is made of InxGa1-xP, wherein x is greater than 0 and less than 1; in a preferable embodiment, x is about 0.48; the second etching stop layer81is n-type doped and the doping concentration of the second etching stop layer81is greater than or equal to 2×1018and less than or equal to 5×1019; and a thickness of the second etching stop layer81is between 1 nm and 40 nm.

Please refer toFIG. 9M, which is the cross-sectional schematic showing another embodiment of an integrated structure of acoustic wave device, varactor and heterojunction bipolar transistor of the present invention. The main structure inFIG. 9Mis basically the same as the structure shown inFIG. 9L, except that the bottom epitaxial structure22further comprises an etching stop layer27. The bottom epitaxial structure22comprises the bottom n-type doped layer25and the etching stop layer27, wherein the etching stop layer27is formed on the bottom n-type doped layer25. The Step G11further comprises following steps of: forming an etching stop layer27on the bottom n-type doped layer25; and etching the etching stop layer27to form the varactor bottom electrode recess52on the second part22(2) of the bottom epitaxial structure22such that the bottom of the varactor bottom electrode recess52is the second part22(2) of the bottom epitaxial structure22; wherein the varactor bottom electrode54is formed on the bottom n-type doped layer25within the varactor bottom electrode recess52. In the first type of applications of embodiments, the etching stop layer27is made of InP; the etching stop layer27is n-type doped and the doping concentration of etching stop layer27is greater than or equal to 2×1018and less than or equal to 5×1019; and a thickness of the varactor ledge layer72is between 1 nm and 40 nm. In the second type of applications of embodiments, the etching stop layer27is made of InxGa1-xP, wherein x is greater than 0 and less than 1; in a preferable embodiment, x is about 0.48; the etching stop layer27is n-type doped and the doping concentration of etching stop layer27is greater than or equal to 2×1018and less than or equal to 5×1019; and a thickness of the varactor ledge layer72is between 1 nm and 40 nm.

Please refer toFIG. 9Ois the cross-sectional schematic showing another embodiment of an integrated structure of acoustic wave device, varactor and heterojunction bipolar transistor of the present invention. The main structure inFIG. 9Ois basically the same as the structure shown inFIG. 9H, except that the acoustic wave device upper structure4comprises an auxiliary layer280, a dielectric layer28and an interdigital transducer electrode29, wherein the auxiliary layer280is formed on the first part22(1) of the bottom epitaxial structure22, the dielectric layer28is formed on the auxiliary layer280, wherein the interdigital transducer electrode29is formed on the dielectric layer28, and wherein the first part22(1) of the bottom epitaxial structure22has no bottom epitaxial structure recess24. In current embodiment, the acoustic wave device50may be a surface acoustic wave device. The integrated structure of the acoustic wave device50, the varactor26and the heterojunction bipolar transistor30formed on the same the semiconductor substrate12is capable of reducing the module size, optimizing the impedance matching, and reducing the signal loss between the varactor26, the acoustic wave device50and the heterojunction bipolar transistor30.

Please refer toFIGS. 9A, 9N and 9O, which are the cross-sectional schematics showing steps of an embodiment of a method for fabricating an integrated structure of acoustic wave device, varactor and heterojunction bipolar transistor of the present invention. The method fabricates the embodiment as shown inFIG. 9O. The method for fabricating the embodiment ofFIG. 9Ois basically the same as the method for fabricating the embodiment ofFIG. 9H(that is the method for fabricating the varactor26and the heterojunction bipolar transistor30on the second part12(2) and the third part12(3) of the semiconductor substrate12of the embodiment ofFIG. 9Ois basically the same as the method for fabricating the varactor26and the heterojunction bipolar transistor30on the second part12(2) and the third part12(3) of the semiconductor substrate12of the embodiment ofFIG. 9H, while the method for fabricating the acoustic wave device50on the first part12(1) of the semiconductor substrate12of the embodiment ofFIG. 9Ois different from the method for fabricating the acoustic wave device50on the first part12(1) of the semiconductor substrate12of the embodiment ofFIG. 9H), except that the Step G13(case b) is modified as following: defining a middle p-type doped layer etching area, and etching the middle p-type doped layer71within the middle p-type doped layer etching area; and defining a middle n-type graded doped layer etching area, and etching the middle n-type graded doped layer70within the middle n-type graded doped layer etching area, thereby a varactor middle epitaxial structure mesa7(2) and the heterojunction bipolar transistor middle epitaxial structure mesa7(3) are formed on the second part22(2) and the third part22(3) of the bottom epitaxial structure22respectively (therefore, there is no such an acoustic wave device middle epitaxial structure mesa7(1) formed on the first part22(1) of the bottom epitaxial structure22as shown inFIG. 9B, the first part of the middle epitaxial structure7on the first part22(1) of the bottom epitaxial structure22is etched and removed); in the Step G13, forming the acoustic wave device upper structure4on the first part22(1) of the bottom epitaxial structure22comprises following steps of: forming an auxiliary layer280on the first part22(1) of the bottom epitaxial structure22; forming a dielectric layer28on the auxiliary layer280; and forming an interdigital transducer electrode29on the dielectric layer28; and in the Step G1, there is no such a step to etch the first part22(1) of the bottom epitaxial structure22to form the bottom epitaxial structure recess24. In the embodiment ofFIG. 9O, the acoustic wave device upper structure4comprises the auxiliary layer280, the dielectric layer28and the interdigital transducer electrode29. The acoustic wave device50may be a surface acoustic wave device. In the embodiment ofFIG. 9O, the structure of the varactor26and the heterojunction bipolar transistor30is basically the same as the structure of the varactor26and the heterojunction bipolar transistor30in the embodiment ofFIG. 9H.

Please refer toFIGS. 9B, 9I and 9P, which are the cross-sectional schematics showing steps of an embodiment of a method for fabricating an integrated structure of acoustic wave device, varactor and heterojunction bipolar transistor of the present invention. The method fabricates the embodiment as shown inFIG. 9I. InFIG. 9B, the varactor middle epitaxial structure mesa7(2) comprises the middle n-type graded doped layer70and the middle p-type doped layer71on the second part22(2) of the bottom epitaxial structure22. The acoustic wave device middle epitaxial structure mesa7(1) comprises the middle n-type graded doped layer70and the middle p-type doped layer71on the first part22(1) of the bottom epitaxial structure22. The heterojunction bipolar transistor middle epitaxial structure mesa7(3) comprises the middle n-type graded doped layer70and the middle p-type doped layer71on the third part22(3) of the bottom epitaxial structure22. To form the structure ofFIG. 9P, the Step G12may further comprise a following step of: forming a varactor ledge layer72on the middle p-type doped layer71. And the Step G13may further comprise a following step of: defining a varactor ledge layer etching area, and etching the varactor ledge layer72within the varactor ledge layer etching area. Then the structure ofFIG. 9Pmay be fabricated. InFIG. 9P, the varactor middle epitaxial structure mesa7(2) comprises the middle n-type graded doped layer70, the middle p-type doped layer71and the varactor ledge layer72on the second part22(2) of the bottom epitaxial structure22. The acoustic wave device middle epitaxial structure mesa7(1) comprises the middle n-type graded doped layer70, the middle p-type doped layer71and the varactor ledge layer72on the first part22(1) of the bottom epitaxial structure22. The heterojunction bipolar transistor middle epitaxial structure mesa7(3) comprises the middle n-type graded doped layer70, the middle p-type doped layer71and the varactor ledge layer72on the third part22(3) of the bottom epitaxial structure22. Therefore, after forming the acoustic wave device protection layer66(1) and the varactor protection layer66(2), the acoustic wave device protection layer mesa607and the varactor protection layer mesa609may have the same height (as shown inFIG. 9I).

Please refer toFIGS. 9Q, 9R and 9S, which are the cross-sectional schematics showing steps of an embodiment of a method for fabricating an integrated structure of acoustic wave device, varactor and heterojunction bipolar transistor of the present invention. The method fabricates the embodiment as shown inFIG. 9S. The main structure inFIG. 9Sis basically the same as the structure shown inFIG. 9I, except that a height of the varactor protection layer mesa609is greater than a height of the acoustic wave device protection layer mesa607. To form the structure ofFIG. 9Qfrom the structure ofFIG. 9P, the Step G13may further comprise a following step of: etching the varactor ledge layer72of the acoustic wave device middle epitaxial structure mesa7(1) such that the acoustic wave device middle epitaxial structure mesa7(1) comprises the middle n-type graded doped layer70and the middle p-type doped layer71on the first part22(1) of the bottom epitaxial structure22, while the varactor middle epitaxial structure mesa7(2) comprises the middle n-type graded doped layer70, the middle p-type doped layer71and the varactor ledge layer72on the second part22(2) of the bottom epitaxial structure22and the heterojunction bipolar transistor middle epitaxial structure mesa7(3) comprises the middle n-type graded doped layer70, the middle p-type doped layer71and the varactor ledge layer72on the third part22(3) of the bottom epitaxial structure22. To form the structure ofFIG. 9Rfrom the structure ofFIG. 9Q, the Step G13may further comprise a following step of: etching the middle p-type doped layer71of the acoustic wave device middle epitaxial structure mesa7(1) such that the acoustic wave device middle epitaxial structure mesa7(1) comprises the middle n-type graded doped layer70on the first part22(1) of the bottom epitaxial structure22, while the varactor middle epitaxial structure mesa7(2) comprises the middle n-type graded doped layer70, the middle p-type doped layer71and the varactor ledge layer72on the second part22(2) of the bottom epitaxial structure22and the heterojunction bipolar transistor middle epitaxial structure mesa7(3) comprises the middle n-type graded doped layer70, the middle p-type doped layer71and the varactor ledge layer72on the third part22(3) of the bottom epitaxial structure22. The structure ofFIG. 9Smay be formed from the structure ofFIG. 9QorFIG. 9R. And therefore, after forming the acoustic wave device protection layer66(1) and the varactor protection layer66(2), the height of the varactor protection layer mesa609is greater than the height of the acoustic wave device protection layer mesa607(as shown inFIG. 9S).

In the embodiment inFIG. 8S, the auxiliary layer610is introduced and is inserted between the acoustic wave device protection layer mesa607and the acoustic wave device bottom electrode604. Similarly the auxiliary layer610may be introduced and inserted between the acoustic wave device protection layer mesa607and the acoustic wave device bottom electrode604in the embodiments ofFIGS. 9G, 9H, 9I, 9J, 9K, 9L, 9M and 9S.

In the present invention, the acoustic wave device protection layer66(1), the varactor protection layer66(2) and the heterojunction bipolar transistor protection layer66(3) is made of at least one material selected from the group consisting of: polymer, SiO2, SiNxand AlN. The acoustic wave device bottom electrode604is needed to have a lower roughness and resistivity for benefit the preferable crystal growth axis. The acoustic wave device bottom electrode604is made of at least one material selected from the group consisting of: Mo, Pt, Al, Au, W and Ru. And the acoustic wave device bottom electrode604is formed on the acoustic wave device protection layer66(1) by evaporation or sputtering. The dielectric layer605is made of at least one material selected from the group consisting of: AlN, monocrystalline SiO2, ZnO, HfO2, barium strontium titanate (BST) and lead zirconate titanate (PZT), and is formed on the acoustic wave device bottom electrode604or formed on both the acoustic wave device bottom electrode604and the acoustic wave device protection layer66(1) by epitaxial growth or sputtering. The selection of the materials of the dielectric layer605is associated with the application. AlN is a high acoustic wave velocity material (12000 m/s) and is suitable for high frequency application, and after the formation of the micro structure of the material, it has good physical and chemical stability and its properties are not easily to be influenced by the circumstance. ZnO may be formed under lower temperature and it has an acoustic wave velocity 6000 m/s. Its electromechanical coupling coefficient is higher (8.5%) and it is suitable for the application of broadband filter. However when forming ZnO, the concentration of oxygen vacancies in ZnO is not easily controlled, yet it is easily influenced by the humidity and oxygen of the circumstance. Both barium strontium titanate (BST) and lead zirconate titanate (PZT) are ferroelectric materials. Their dielectric constant may vary under external electric field. Hence, they are suitable for the application of acoustic wave device with tunable frequency within dozen MHz range of frequencies. Both barium strontium titanate (BST) and lead zirconate titanate (PZT) need to be polarized under high voltage electric field in order to obtain their dielectric characteristics. Lead zirconate titanate (PZT) has higher electromechanical coupling coefficient, however it contains lead. The acoustic wave device top electrode606may be made of at least one material selected from the group consisting of: Mo, Pt, Al, Au, W and Ru. The acoustic wave device top electrode606is formed on the dielectric layer605or is formed on both the dielectric layer605and the acoustic wave device protection layer66(1) by evaporation or sputtering. In an embodiment, the acoustic wave device bottom electrode604is made of at least one material selected from the group consisting of: Mo and Pt, while the dielectric layer605is made of AlN. The Mo of the acoustic wave device bottom electrode604may be etched by Lithography and Lift-off process. And the AlN of the dielectric layer605may be etched by inductively coupled plasma (ICP) process with CF4plasma. The dielectric layer28is made of at least one material selected from the group consisting of: AlN, monocrystalline SiO2, ZnO, HfO2, Lithium Tantalate (LiTaO3), Lithium Niobate (LiNbO3), barium strontium titanate (BST) and lead zirconate titanate (PZT), and is formed on the auxiliary layer280by epitaxial growth or sputtering. In an embodiment, the interdigital transducer electrode29is made of at least one material selected from the group consisting of: Au, Al, Cu and Al—Cu alloy. In an embodiment, the varactor bottom electrode54and the varactor top electrode55is made of Au.

As disclosed in the above description and attached drawings, the present invention can provide an integrated structure of an acoustic wave device, a varactor and an heterojunction bipolar transistor, and fabrication methods thereof with reduced module size, optimized the impedance matching, and reduced the signal loss between the heterojunction bipolar transistor, the varactor and the acoustic wave device. It is new and can be put into industrial use.

Although the embodiments of the present invention have been described in detail, many modifications and variations may be made by those skilled in the art from the teachings disclosed hereinabove. Therefore, it should be understood that any modification and variation equivalent to the spirit of the present invention be regarded to fall into the scope defined by the appended claims.