WIRING SUBSTRATE, ELECTRONIC DEVICE, AND ELECTRONIC MODULE

A wiring substrate includes an insulating substrate including a first surface and a wiring conductor located at the insulating substrate, the insulating substrate containing multiple bulk crystallites of SiC with different polytypes. An electronic device includes the wiring substrate described above and an electronic component mounted on the wiring substrate. An electronic module includes the electronic device described above and a module substrate on which the electronic device is mounted.

TECHNICAL FIELD

The present disclosure relates to a wiring substrate, an electronic device, and an electronic module.

BACKGROUND

To mount an electronic component on a package or a module substrate, there is a wiring substrate interposed between the electronic component and the package or between the electronic component and the module substrate. Japanese Unexamined Patent Application Publication No. 2019-62212 discloses a semiconductor laser device including a wiring substrate of single-crystal SiC (silicon carbide).

Although single-crystal SiC substrates have high heat dissipation performance, their production costs are high.

SUMMARY

A wiring substrate according to the present disclosure includes:

an insulating substrate including a first surface, and

a wiring conductor located at the insulating substrate,

the insulating substrate containing multiple bulk crystallites of SiC with different polytypes.

An electronic device according to the present disclosure includes:

the wiring substrate described above, and an electronic component mounted on the wiring substrate.

An electronic module according to the present disclosure includes:

the electronic device described above, and

a module substrate on which the electronic device is mounted.

DETAILED DESCRIPTION

Embodiments of the present disclosure will be described in detail below with reference to the drawings.

First Embodiment

FIG. 1illustrates an electronic device including a wiring substrate, and an electronic module according to a first embodiment of the present disclosure. The wiring substrate1according to the first embodiment includes an insulating substrate10, which is a plate-like member, including a first surface11, and a wiring conductor20located at the first surface11of the insulating substrate10. The wiring substrate1includes a second surface12opposite to the first surface11. The first surface11and the second surface12may be two wider surfaces of the plate-like member or may be ones on which electronic components are mounted. The wiring conductor20may be formed of a stack of an adhesion layer21composed mainly of, for example, Ti (titanium), Cr (chromium), or both Ti and Cr, a barrier layer22composed mainly of, for example, Pt (platinum), a conductor layer23composed mainly of, for example, Au (gold), and a bonding conductor25, such as AuSn (gold-tin), that bonds an electronic component50.

The wiring substrate1may be a submount that is interposed between an electronic component50and a package or between the electronic component50and a module substrate110and that is responsible for a heat removal effect and an electrical connection function for the electronic component50. In the submount, the first surface11on which the electronic component50is mounted has a size of 0.01 cm2to 1.00 cm2. The submount has a thickness of 0.1 mm to 0.8 mm.

FIG. 2is a longitudinal sectional view of the insulating substrate illustrated inFIG. 1.FIG. 3is a plan view illustrating the insulating substrate illustrated inFIG. 1.

The insulating substrate10is a polycrystalline SiC substrate containing multiple bulk crystallites bonded together while undergoing crystal growth, and contains multiple bulk crystallites G1to G7. The term “bulk crystallite” refers to a mass of a single crystal grown three-dimensionally. A grain boundary phase (for example, a phase containing a sintering aid for use in firing for a SiC multiparticle sintered substrate) is not contained between adjacent bulk crystallites. A grain boundary B as an interfacial boundary may be interposed therebetween. The term “phase” refers to a structure having a thickness even if it is minute.

The number of the bulk crystallites G1to G7contained in the first surface11of the insulating substrate10may be 2 pieces/cm2or more and 100 pieces/cm2or less. The number density of bulk crystallites as described above results in a thermal conductivity equivalent to that of a single-crystal SiC substrate. If the number density of the bulk crystallites is higher than 100 pieces/cm2, the thermal conductivity is lower than that of the single-crystal SiC substrate. If the number density of the bulk crystallites is lower than 2 pieces/cm2, the number of micropipes generated from grain boundaries due to crystal mismatch is increased, and the number of micropipes that penetrate from the first surface11to the second surface12is increased. With regard to the size of the bulk crystallites G1to G7contained in the first surface11of the insulating substrate10, the minimum width may be 1 mm to 5 mm. The number of the bulk crystallites G1to G7contained in the first surface11may be 2 pieces/cm2or more and 10 pieces/cm2or less.

The insulating substrate10includes regions E1to E3(FIG. 2) where no grain boundaries are present between the first surface11and the second surface12. In other words, the insulating substrate10includes the regions E1to E3each occupied by a single bulk crystallite from the first surface11to the second surface12.

The grain boundary B-free regions E1, E2, and E3may be superimposed on a region where the wiring conductor20is located in a perspective plan view of the first surface11(a perspective view of the insulating substrate10in a direction perpendicular to the first surface11). A configuration may be used in which no grain boundary B is present at a position superimposed on the wiring conductor20in the perspective plan view of the first surface11. In the insulating substrate10, a region in which two or more grain boundaries B are contained between the first surface and the second surface12in the perspective view in the direction perpendicular to the first surface11may be 20% or less in area fraction.

FIG. 4is an image drawing of an electron micrograph of a surface of an insulating substrate. The photograph inFIG. 4has different lightness levels in accordance with the polytypes of the bulk crystallites.

As illustrated inFIG. 4, the wiring substrate1contains multiple bulk crystallites of SiC with different polytypes. The term “polytype” refers to the type of polymorphism in which the chemical composition is identical and the atomic arrangement of the crystals is different. The multiple bulk crystallites may all belong to α-SiC. α-SiC refers to bulk crystallites other than the 3C type and is a high-purity SiC crystal. α-SiC can be formed by crystal growth at 2,000° C. or higher using a sublimation-recrystallization method. With regard to all the bulk crystallites contained in the insulating substrate10, any of 4H-type, 6H-type, and 15R-type bulk crystallites may be contained, and the total volume fraction of the 4H-type, 6H-type, and 15R-type bulk crystallites may be 80% or more. The volume fraction of the 3C-type bulk crystallites contained in the insulating substrate10may be 1% or less.

The multiple bulk crystallites may include those having different plane directions from each other. The term “plane direction” refers to the direction of a specific crystal plane. The bulk crystallites of different polytypes contained in the insulating substrate10may have different plane directions from each other. The multiple bulk crystallites of the same polytype contained in the insulating substrate10may have different plane directions from each other.

<Method for Producing Crystalline SiC Substrate>

FIGS. 5A to 5Cillustrate three types of SiC substrates.FIG. 5Aillustrates a section of a single-crystal SiC substrate.FIG. 5Billustrates a section of a crystalline SiC substrate according to the first embodiment.FIG. 5Cillustrates a section of a SiC multiparticle sintered substrate.

There are several types of SiC substrates: for example, single-crystal SiC substrate K1(FIG. 5A), which is made by single-crystal growth using the sublimation-recrystallization method; polycrystalline SiC substrate K2(FIG. 5B), which is made by bonding multiple bulk crystallites while they are grown using the sublimation-recrystallization method; and SiC multiparticle sintered substrate K3(FIG. 5C), which is made by grinding SiC crystals into fine particles and then sintering them through firing.

Single-crystal SiC substrate K1has high thermal conductivity because it is a single crystal. Single-crystal SiC substrate K1is anisotropic with respect to the thermal expansion coefficient and thus often contains micropipe P formed of a series of crystal defects during the crystal growth process. Micropipe P is often continuous from the first surface11of single-crystal SiC substrate K1to the surface opposite to the first surface11. The production cost of the single-crystal SiC substrate K1is high due to a wide margin for production because a single-crystal portion is extracted and additionally due to the need for a seed crystal.

The polycrystalline SiC substrate K2is obtained by growing SiC crystals using a physical vapor deposition method, such as the sublimation-recrystallization method, without a seed-crystal substrate or with a substrate containing multiple seed crystals. In the polycrystalline SiC substrate K2, during the growth of multiple bulk crystallites, adjacent bulk crystallites come into contact with each other to form bonded grain boundaries B. The polycrystalline SiC substrate K2contains multiple bulk crystallites having different growth directions (i.e., plane directions) and thus contains the grain boundaries B having irregular orientations. If micropipes P are formed during the growth process of multiple bulk crystallites, the polycrystalline SiC substrate K2contains multiple micropipes extending in different directions (central axis directions) because of the different plane directions of the multiple bulk crystallites. Since the grain boundaries B are formed if adjacent bulk crystallites come into contact with each other during the growth process, if the bulk crystallites contain micropipes, the end portions of the micropipes may be blocked by the adjacent bulk crystallites. In other words, during the crystal growth process, micropipes P with their end portions blocked by adjacent bulk crystallites may be formed. For the polycrystalline SiC substrate K2, there is no need to extract a single-crystal portion. Thus, the polycrystalline SiC substrate K2can be produced at a lower cost than the single-crystal SiC substrate K1. The insulating substrate10of the first embodiment is obtained by cutting the polycrystalline SiC substrate K2into a predetermined size.

The SiC multiparticle sintered substrate K3is formed by gathering particles with a sintering aid, such as a binder, before firing, and sintering the particles together using the sintering aid. The sintering aid is a liquid phase and is, for example, alumina. The SiC multiparticle sintered substrate K3contains a large number of fine grain boundaries BL and the remaining sintering aid J. Layer-like materials having thickness are contained in the grain boundaries BL in the SiC multiparticle sintered substrate K3. The SiC multiparticle sintered substrate K3has a low thermal conductivity because thermal vibrations are diffused or absorbed by the many grain boundaries BL and the sintering aid J. The production process of the SiC multiparticle sintered substrate K3does not include a crystal growth step.

FIG. 6Ais a plan view illustrating an example of micropipes contained in the insulating substrate according to the first embodiment.FIG. 6Bis a side view of an example of micropipes contained in the insulating substrate according to the first embodiment.FIG. 7is a side view illustrating an example of a micropipe contained in the insulating substrate according to the first embodiment.FIGS. 6A, 6B and 7illustrate an insulating substrate different from the insulating substrate10illustrated inFIGS. 2 and 3.

The insulating substrate10of the first embodiment is obtained by cutting the polycrystalline SiC substrate K2, as described above. Thus, as illustrated inFIGS. 6A and 6B, in some cases, multiple bulk crystallites G11to G19having different plane directions are contained, and, in addition, multiple micropipes P1to P5extending in different directions are contained. The micropipes P1to P5with first ends open to the first surface11have central axes inclined at various angles with respect to the first surface11. As illustrated inFIG. 7, a micropipe P6having a first end open to the first surface11and having a second end blocked by the grain boundary B is contained, in some cases.

FIG. 8illustrates the action of a micropipe contained in the insulating substrate according to the first embodiment.

As illustrated inFIG. 8, in the insulating substrate10of the first embodiment, the micropipe P4is open to the first surface11and extends obliquely with respect to the first surface11. Accordingly, if the wiring conductor20is formed in the opening portion of the micropipe P4, the wiring conductor20extends partially in the micropipe P4. The diagonally extending portion20k provides an anchoring effect and enables the film of the wiring conductor20to be less likely to peel off. Furthermore, the wiring conductor20is formed in the area where the multiple micropipes P1to P5are open, and extend in the end portions of the multiple micropipes P1to P5. This provides the extended portions at different angles and enables the film of the wiring conductor20to be less likely to peel off.

Furthermore, in the insulating substrate10of the first embodiment, the micropipe P4open to the first surface11is blocked at some midpoint by other bulk crystallites via the grain boundary B and does not reach the second surface12, in many cases. This enables a high degree of insulation between the first surface11and the second surface12.

The insulating substrate10may have a resistivity of 1×103Ω·cm or more. The insulating substrate10may have a nitrogen content of 3×1017atoms/cm3(atomic number density) or less. The insulating substrate10may have a resistivity of 1×105Ω·cm or more. The insulating substrate10may have a vanadium content of 1×1015atoms/cm3or more and 1×1018atoms/cm3or less.

As described above, in the SiC substrate, a reduction in the amount of nitrogen serving as a dopant and an increase in the amount of vanadium, which traps free electrons, enable the insulating substrate10to have an increased resistivity and enhanced insulation performance. In addition, the use of a vanadium content of lower than or equal to the foregoing level enables a reduction in the number of micropipes and suppression of the scattering effect of thermal vibrations, thereby maintaining a high thermal conductivity of the insulating substrate10.

As described above, according to the wiring substrate1of the first embodiment, the multiple bulk crystallites G1to G7and G11to G19of SiC having different polytypes are contained. Thus, the production cost can be reduced because a single-crystal substrate is not used. In addition, the presence of the SiC bulk crystallites G1to G7and G11to G19in the insulating substrate10can provide the high thermal conductivity performance of the wiring substrate1. Furthermore, higher thermal conductivity performance can be obtained by using the number of the bulk crystallites G1to G7and G11to G19, per unit area, on the first surface11, the grain boundary B-free regions E1to E3(FIG. 2), the positional relationship between the regions E1to E3and the wiring conductor20, or two or more thereof.

According to the wiring substrate1of the first embodiment, the insulating substrate10includes the multiple bulk crystallites G1to G7and G11to G19having different plane directions. Accordingly, the anisotropy of the thermal expansion is reduced, and the amount of thermal deformation of the entire insulating substrate10is reduced, thereby enabling reductions in the distortion of the electronic component50and the stress between the insulating substrate10and the electronic component50. In addition, a stress due to a difference in thermal expansion between the insulating substrate10and the wiring conductor20or a stress due to a difference in thermal expansion between the wiring substrate1and the electronic component50is isotropic, so that adverse effects caused by stress can be less likely to occur. Moreover, in the insulating substrate10, the various plane directions result in isotropic properties in terms of thermal conductivity.

According to the wiring substrate1of the first embodiment, the SiC crystals of the insulating substrate10have the polytype fraction as described above, thus making it possible to achieve a higher thermal conductivity.

According to the wiring substrate1of the first embodiment, owing to the above-mentioned characteristics of the micropipes P1to P6, the film of the wiring conductor20can be less likely to peel off. In addition, the micropipes P1to P6can be less likely to cause the effect of deteriorating the insulating properties. The high resistivity of the insulating substrate10itself can be achieved by the amount of the above-mentioned components contained in the insulating substrate10. Accordingly, it is possible to improve the reliability of the wiring conductor20of the wiring substrate1and the insulation properties of the insulating substrate10.

(Electronic Device and Electronic Module)

As illustrated inFIG. 1, an electronic device60of the first embodiment includes an electronic component50mounted on the wiring substrate1. The electrodes of the electronic component50are electrically connected to the wiring conductor20. An electrode of the electronic component50may be directly bonded to the wiring conductor20or may be connected thereto with a bonding member, such as a bonding wire provided therebetween. The electronic device60may include a package that receives the wiring substrate1and the electronic component50.

Examples of the electronic component50that can be used include various electronic components, such as optical elements, e.g., laser diodes (LDs), photodiodes (PDs), and light-emitting diodes (LEDs), image-pickup elements of charge-coupled device (CCD) types and complementary metal oxide semiconductor (CMOS) types, piezoelectric oscillators, e.g., quartz oscillators, surface acoustic wave elements, semiconductor elements, e.g., semiconductor integrated circuits (ICs), electric capacitive elements, inductor elements, and resistors.

An electronic module100according to the first embodiment includes the electronic device60mounted on the module substrate110. In addition to the electronic device60, other electronic devices, electronic elements, electric elements, and the like may be mounted on the module substrate110. The module substrate110may be provided with an electrode111. The electronic device60may be bonded to the electrode111with a bonding material113, such as solder or gold-tin, provided therebetween. If the electronic device60includes a package, the electrode111of the module substrate110may be bonded to a wiring conductor of the package.

According to the electronic device60and the electronic module100of the first embodiment, good heat dissipation characteristics and good electrical characteristics of the electronic component50can be obtained, thus improving reliability.

Second Embodiment

FIG. 9Ais a plan view illustrating a wiring substrate, an electronic device, and an electronic module according to a second embodiment of the present disclosure.FIG. 9Bis a longitudinal sectional view taken along line A-A ofFIG. 9A. In the following description, inFIGS. 9A and 9B, the X direction is defined as a forward direction, the Y direction is defined as a leftward direction, and the Z direction is defined as an upward direction. The directions indicated in the second embodiment may be different from the directions when the wiring substrate is in use.

A wiring substrate1A according to the second embodiment of the present disclosure is a submount on which the electronic component (light-emitting element)50, such as a LD, a PD, or a LED is mounted. The submount is a wiring substrate that is interposed between the electronic component50and the package or between the electronic component50and the module substrate110, directs heat from the electronic component50and releases the heat to the package or module substrate110, and passes a drive current through the electronic component50.

The wiring substrate1A includes the insulating substrate10having the first surface11, the second surface12opposite to the first surface11, a first side13, and a second side14opposite to the first side13. The first surface11corresponds to the upper surface, the second surface12corresponds to the lower surface, the first side corresponds to the left side, and the second side corresponds to the right side. The insulating substrate10includes groove portions17aand17b, which are castellations, located on the first and second sides13and14, respectively. Each of the groove portions17aand17bextends from the first surface11to the second surface12.

The first surface11includes a mounting portion R for the electronic component50. The first surface11includes a front end (first end) b1and a rear end (second end) b2opposite to the front end b1in a plan view. The mounting portion R is located closer to the front end b1than to the rear end b2. The mounting portion R may be in contact with the front end b1. The mounting portion R may be located at the center of the first surface11in the left-right direction. The maximum heat generation point of the electronic component50may be located at the front portion of the mounting portion R.

The groove portions17aand17b, which are the castellations, are located closer to the rear end b2than to the front end b1of the first surface11. The groove portions17aand17bmay be located closer to the rear end than to the front end of the insulating substrate10in the entire region in the thickness direction.

The wiring substrate1A further includes a wiring conductor41located on the first surface11, a wiring conductor42located over the first surface11, the second surface12, the first side13, and the second side14, a bonding conductor43located on the wiring conductor41on the first surface11, and a bonding conductor44located on the wiring conductor42on the second surface12. On the first and second sides13and14, the wiring conductor42is located in the groove portions17aand17b, which are the castellations. Each of the wiring conductors41and42may be a film-like conductor and may be a conductor formed of a stack of an adhesion layer containing, for example, Ti (titanium), a barrier layer containing, for example, Pt (platinum), and a conductor layer containing, for example, Au (gold). For the wiring conductor42, a portion of the wiring conductor42located on the first surface11corresponds to an example of the first line according to the present disclosure, a portion of the wiring conductor42located on the second surface12corresponds to an example of the second line according to the present disclosure, and a portion of the wiring conductor42(conductor film421) located in each of the groove portions17aand17bcorresponds to an example of the third line according to the present disclosure.

The wiring conductor41is located in a region overlapping the mounting portion R on the first surface11. The wiring conductor41may extend from the vicinity of the front end to the vicinity of the rear end of the first surface11, may extend from the vicinity of the left end to the vicinity of the right end near the rear end of the first surface11, and may have an inverted T-shape in a view from above.

The wiring conductor42is separated from the wiring conductor41on the first surface11. The wiring conductor42is located on the first surface11and the second surface12as a conductor film. The wiring conductor42further includes the conductor films421that are thicker than the conductor films located on the first surface11and the second surface12and that are located in the groove portions17aand17b. The conductor films421can be thickened by performing plating of a conductor, such as Au, on the conductor films that have been formed in the groove portions17aand17band that have been formed together with the conductor films on the first surface11and the second surface12.

The bonding conductors43and44may be formed of a stack of a barrier layer containing, for example, Pt and a conductor layer of, for example, AuSn (gold-tin). The bonding conductor43on the upper surface is located on the mounting portion R on the wiring conductor41and bonded to the electronic component50. The bonding conductor43may extend from the front end b1to the rear end b2of the first surface11beyond the mounting portion R. The bonding conductor44on the lower surface is located on the wiring conductor42(in contact with the lower surface of the wiring conductor42) and is bonded to the electrode111of the package or module substrate110.

The maximum width (for example, front-to-rear width) of the insulating substrate10in a planar direction along the first surface11is greater than the average thickness in the direction perpendicular to the first surface11(thickness direction). For example, the first surface11is a square or near-square rectangle having an area of 0.01 cm2to 1.00 cm2and a thickness of 0.1 mm to 0.8 mm.

FIG. 10illustrates a first surface of an insulating substrate according to the second embodiment.

The insulating substrate10is a polycrystalline SiC substrate cut to a predetermined size, as illustrated inFIG. 4, and contains multiple bulk crystallites G21to G25, as illustrated inFIG. 10. The term “bulk crystallite” refers to a mass of a single crystal grown three-dimensionally. Between adjacent bulk crystallites G21to G25, a grain boundary phase (for example, a phase containing a sintering aid for a ceramic substrate) is not contained, and a grain boundary B as an interfacial boundary is present.

The insulating substrate10may contain multiple bulk crystallites of SiC with different polytypes, as illustrated inFIG. 4. The term “polytype” refers to the type of polymorphism in which the chemical composition is identical and the atomic arrangement of the crystals is different. The multiple bulk crystallites may all belong to α-SiC. α-SiC refers to bulk crystallites other than the 3C type and is a high-purity SiC crystal. α-SiC can be formed by crystal growth at 2,000° C. or higher using a sublimation-recrystallization method. With regard to all the bulk crystallites contained in the insulating substrate10, any of 4H-type, 6H-type, and 15R-type bulk crystallites may be contained, and the total volume fraction of the 4H-type, 6H-type, and 15R-type bulk crystallites may be 80% or more. The volume fraction of the 3C-type bulk crystallites contained in the insulating substrate10may be 1% or less.

The plane directions of the multiple bulk crystallites G21to G25may be different from each other. The term “plane direction” refers to the direction of a specific crystal plane. The bulk crystallites of different polytypes contained in the insulating substrate10may have different plane directions from each other. The multiple bulk crystallites of the same polytype contained in the insulating substrate10may have different plane directions from each other.

The insulating substrate10has a higher thermal conductivity in the planar direction (X and Y directions) along the first surface11than a thermal conductivity in the thickness direction (Z direction). The thermal conductivity in a specific direction is determined by cutting the insulating substrate10into cubes, for example, and measuring the thermal conductivity in a specific direction using a laser flash method.

In the insulating substrate10, the number of grain boundaries B per unit length in the planar direction along the first surface11is smaller than the number of grain boundaries B per unit length in the thickness direction. In the insulating substrate10, the number of grain boundaries B in the planar direction (for example, the number of grain boundaries B from the front end to the rear end of the insulating substrate10) is 0 to 3. The number of grain boundaries B in a specific direction can be determined on the basis of the number of intersections N of the grain boundaries B and a virtual straight line L extending in a specific direction on the surface or a section of the insulating substrate10, as illustrated by a dot-dash line inFIG. 10. The number of grain boundaries B is defined as a value obtained by counting the number of intersections N of the grain boundaries B and five or more virtual lines L arranged randomly in a specific direction and in the insulating substrate10, and averaging the total number of intersections.

The polycrystalline SiC substrate, which is a material for the insulating substrate10, can be produced in the same way as the polycrystalline SiC substrate K2of the first embodiment. The insulating substrate10is obtained by cutting a polycrystalline SiC substrate to a predetermined size. The cutting point and the direction of cutting are determined so as to satisfy the requirement for the number of grain boundaries.

(Electronic Device and Electronic Module)

An electronic device60A according to the second embodiment includes the electronic component50, which is a light-emitting element, mounted on the wiring substrate1A, as illustrated inFIG. 9B. One of the electrodes of the electronic component50is bonded to the bonding conductor43on the wiring conductor41. The other electrode of the electronic component50is connected to the wiring conductor42on the first surface11through a bonding member, such as a bonding wire w.

An electronic module100A according to the second embodiment includes the electronic device60A mounted on the module substrate110, as illustrated inFIG. 9B. In addition to the electronic device60A, other electronic devices, electronic elements, electric elements, and the like may be mounted on the module substrate110. The module substrate110is provided with the electrode111, and the electronic device60A may be bonded to the electrodes111with the bonding conductor44provided therebetween. If the electronic device60A includes a package, the electrode111of the module substrate110may be bonded to a wiring conductor of the package.

Applying a voltage across the wiring conductors41and42of the wiring substrate1A allows a drive current to flow to the electronic component50, thereby causing the electronic component to emit light. The drive current flows from the wiring conductor42on the first surface11to the wiring conductor42on the second surface12through the conductor films421, which are the castellations. Each of the conductor films421, which are the castellations, has a small surface area and large thickness, compared with the wiring conductor42on the first surface11and the second surface12. This eliminates the concentration of Joule heat on the wiring conductor42and enables the conductor films421, which are the castellations, to be less likely to deteriorate.

When the electronic component50is driven, the electronic component50generates heat. For example, the amount of heat generated increases at the front end of the electronic component50where light is emitted. After the heat generated from the electronic component50is transferred from the bonding conductor on the mounting portion R to the first surface11of the insulating substrate10through the wiring conductor41, the heat is transferred toward the second surface12(−Z direction) while spreading widely in the planar direction (±X direction and ±Y direction) along the first surface11in the insulating substrate10. Heat spreads widely in the planar direction because the thermal conductivity of the insulating substrate10in the X and Y directions is higher than that in the Z direction. The heat transferred through the insulating substrate10spreads uniformly over the entire area of the second surface12and is released to the module substrate110through the wiring conductor42and the bonding conductor44. The insulating substrate10is formed of a polycrystalline SiC substrate and thus has high thermal conductivity also in the Z direction, and the heat of the electronic component50can be efficiently released by the high heat dissipation effect with the addition of the above mode of thermal conduction.

As described above, according to the wiring substrate1A of the second embodiment, the insulating substrate10on which the wiring conductors41and42are located is a polycrystalline SiC substrate, and the maximum width in the planar direction (X-Y direction) along the first surface11having the mounting portion R of the electronic component50is greater than the average thickness in the Z direction perpendicular to the first surface11. Furthermore, the thermal conductivity of the insulating substrate10in the planar direction is higher than that in the thickness direction. Accordingly, the heat of the electronic component50mounted on the mounting portion R can be efficiently released owing to the high heat dissipation effect, as described above. The production cost of the polycrystalline SiC substrate can be suppressed as compared with the single-crystal SiC substrate; thus, the wiring substrate1A can be produced at low cost.

According to the wiring substrate1A of the second embodiment, the number of the grain boundaries B per unit length in the planar direction in the insulating substrate10is smaller than the number of the grain boundaries B per unit length in the thickness direction. The grain boundaries B have the effect of decreasing the thermal conductivity. By controlling the number of the grain boundaries B generated and the direction in which the grain boundaries B are easily formed during the production of the polycrystalline SiC substrate, the insulating substrate10with characteristics where the thermal conductivity in the planar direction is higher than the thermal conductivity in the thickness direction can be easily produced at low cost.

According to the wiring substrate1A of the second embodiment, the number of the grain boundaries B in the planar direction of the insulating substrate10is 0 to 3. At this number, it is possible to produce the wiring substrate1A having high heat dissipation performance while maintaining low production cost of the insulating substrate10.

According to the wiring substrate1A of the second embodiment, the castellations (groove portions17aand17band conductor films421) are located closer to the rear end b2than to the front end b1of the first surface11, although the mounting portion R on which the electronic component50is mounted is located closer to the front end b1than to the rear end b2of the first surface11. Since the heat of the electronic component50is transmitted in the thickness direction while spreading in the planar direction in the insulating substrate10, the larger volume of the insulating substrate10near the heat generation point leads to an improvement in heat dissipation performance. The castellations provide the effect of reducing the volume of the insulating substrate10by means of the groove portions17aand17b, but the above arrangement allows regions that reduce the volume of the insulating substrate10to be separated from the mounting portion R. Thus, the heat dissipation performance of the wiring substrate1A due to the reduction in the volume of the insulating substrate10caused by the castellations is less likely to deteriorate.

According to the wiring substrate1A of the second embodiment, the conductor films421, which are the castellations, are thicker than the wiring conductors41and42on the first surface11and the wiring conductor42on the second surface12. Accordingly, if the current is concentrated in the conductor films421, which are the castellations, the Joule heat of the conductor films421can be reduced, thereby enabling the conductor films421to be less likely to deteriorate.

According to the electronic device60A and the electronic module100A of the second embodiment, good heat dissipation characteristics of the electronic component50can be obtained, thus improving reliability.

The embodiments of the present disclosure have been described above. However, the wiring substrate, the electronic device, and the electronic module of the present disclosure are not limited to the above-described embodiments. For example, although the first embodiment provides an example of a method for producing the insulating substrate for the wiring substrate, another production method by which a similar insulating substrate can be produced may be employed. In the first embodiment, an example of a wiring substrate used as a submount on which one electronic component is mounted has been described; however, the wiring substrate may also be used as a wiring board on which multiple electronic components are mounted. The type and arrangement of the wiring conductors described in the first embodiment are merely an example. In the second embodiment, the shape of the insulating substrate and the arrangement, pattern, and components of the wiring conductors located on the insulating substrate can be changed as appropriate.

INDUSTRIAL APPLICABILITY

The present disclosure can be used for wiring substrates, electronic devices, and electronic modules.

REFERENCE SIGNS LIST

60,60A electronic device

100,100A electronic module

B grain boundary

R mounting portion