Static and dynamic firewalls

A system comprising control logic adapted to activate multiple security levels for the system. The system further comprises a storage coupled to the control logic and comprising a stack, the stack associated with one, but not all, of the multiple security levels. The system also comprises security logic coupled to the control logic and adapted to restrict usage of the system if the control logic attempts to fetch an instruction op-code from the stack.

BACKGROUND

Mobile electronic devices such as personal digital assistants (PDAs) and digital cellular telephones are increasingly used for electronic commerce (e-commerce) and mobile commerce (m-commerce). Programs that execute on the mobile devices to implement e-commerce and/or m-commerce functionality may need to operate in a secure mode to reduce the likelihood of attacks by malicious programs (e.g., virus programs) and to protect sensitive data.

For security reasons, at least some processors provide two levels of operating privilege: a first level of privilege for user programs; and a higher level of privilege for use by the operating system. The higher level of privilege may or may not provide adequate security, however, for m-commerce and e-commerce, given that this higher level relies on proper operation of operating systems with highly publicized vulnerabilities. In order to address security concerns, some mobile equipment manufacturers implement yet another third level of privilege, or secure mode, that places less reliance on corruptible operating system programs, and more reliance on hardware-based monitoring and control of the secure mode. An example of one such system may be found in U.S. Patent Publication No. 2003/0140245, entitled “Secure Mode for Processors Supporting MMU and Interrupts.”

In addition to this secure mode, various hardware-implemented security firewalls and other security monitoring components have been added to the processing systems used in mobile electronic devices to further reduce the vulnerability to attacks. Despite this addition of security protection in the processing hardware, mobile electronic devices remain vulnerable to a common software security attack known generically as “stack buffer overflow.” In a stack buffer overflow attack, executable code is written on an execution stack and the return address of a currently executing function is modified so that it will point to the beginning of this new code. When the function call returns, the attacker's code is executed.

SUMMARY

Accordingly, there are disclosed herein techniques by which a system is protected from malicious attacks such as those described above (e.g., buffer overflow attacks). An illustrative embodiments includes a system comprising control logic adapted to activate multiple security levels for the system. The system further comprises a storage coupled to the control logic and comprising a stack, the stack associated with one, but not all, of the multiple security levels. The system also comprises security logic coupled to the control logic and adapted to restrict usage of the system if the control logic attempts to fetch an instruction op-code from the stack.

Another illustrative embodiment includes a system comprising a storage having a range of memory addresses associated with a security mode of the system. The system also comprises firewall logic coupled to the storage and adapted to restrict usage of the system if a signal attempting to access an instruction op-code from memory associated with the range of addresses is detected.

Yet another illustrative embodiment includes a method of protecting a system comprising monitoring memory access signals, at least a portion of the memory associated with one, but not all, of a plurality of security modes. The method also comprises restricting usage of the system if one of the memory access signals attempts to access an instruction op-code from the portion.

NOTATION AND NOMENCLATURE

DETAILED DESCRIPTION

Inasmuch as the systems and methods described herein were developed in the context of a mobile computing system, the description herein is based on a mobile computing environment. However, the discussion of the various systems and methods in relation to a mobile computing environment should not be construed as a limitation as to the applicability of the systems and methods described herein to only mobile computing environments. The teachings herein can be applied to any type of system (e.g., desktop computers).

The system disclosed herein comprises a hardware-based firewall subsystem which protects the system from malicious attacks, such as buffer overflow attacks.FIG. 1shows the system100in accordance with one or more embodiments of the invention. The system100preferably comprises an ARM® TrustZone® architecture, but the scope of this disclosure is not limited as such. In accordance with at least some embodiments, the system100may be, or may be contained within, a mobile device such as a cellular telephone, personal digital assistant (PDA), text messaging system, and/or a device that combines the functionality of a messaging system, PDA and a cellular telephone. The system100includes a multiprocessor unit (MPU)102and a secure state machine (SSM)104comprising the firewall subsystem (shown inFIG. 4). The MPU102couples to a storage106via an interface110, a write bus112and a read bus114. The write bus112and read bus114also couple to the SSM104via buses118and116, respectively. The SSM104monitors activity (e.g., data transactions, instruction op-code fetches) on the read and write buses to detect specific activities which indicate the possibility that a malicious attack is being carried out on the system100. If such malicious activity is detected, the SSM104sends security violation signals to one or more of the MPU102, the interface110, and/or the security enforcement module108, depending on the specific violation that has occurred. Upon receiving a security violation signal, each of the MPU102, the interface110, and the security enforcement module108takes a different action to prevent or at least mitigate damage to the system100.

The system100is capable of operating within a variety of different security modes. The security modes of the system100are established to protect memory in the storage106from attack. Specifically, the storage106, which may comprise random access memory (RAM), NOR and NAND flash memory, synchronous dynamic RAM (SDRAM), etc., is partitioned into public and secure domains. The public domain is accessible in a non-secure mode and the secure domain is accessible only in a secure mode. In at least some embodiments, the public and secure domain partitions are virtual (i.e., non-physical) partitions generated and enforced by a memory management unit (MMU) in the MPU102(shown inFIG. 4).

Each of the secure and non-secure modes may be partitioned into “user” and “privileged” modes. Programs that interact directly with an end-user, such as a web browser, are executed in the user mode. Programs that do not directly interact with an end-user, such as the operating system (OS), are executed in the privileged mode. By partitioning the secure and non-secure modes in this fashion, a total of four security modes are available. As shown inFIG. 2, in order of ascending security level, these four modes include the non-secure user mode200, the non-secure privileged mode202, the secure user mode204, and the secure privileged mode206. There is an additional security mode, called the monitor mode208, between the modes202and204. The computer system100may operate in any one of these five modes at a time.

The computer system100may switch from one mode to another.FIG. 2illustrates a preferred mode-switching sequence210. The sequence210is preferred because it is more secure than other possible switching sequences. For example, to switch from the non-secure user mode200to the secure privileged mode204, the system100should first pass through non-secure privileged mode202and the monitor mode208. Likewise, to pass from the secure user mode206to the non-secure user mode200, the system100should switch from the secure user mode206to the secure privileged mode204, from the secure privileged mode204to the monitor mode208, from the monitor mode208to the non-secure privileged mode202, and from the non-secure privileged mode202to the non-secure user mode200.

Some of the five security modes shown inFIG. 2comprise additional sub-modes, as shown inFIG. 3.FIG. 3shows the non-secure privileged mode202comprising six sub-modes300-310. Specifically, the non-secure privileged mode202comprises a non-secure supervisor mode300, a non-secure system mode302, a non-secure FIQ mode304, a non-secure IRQ mode306, a non-secure abort mode308, and a non-secure UNDEF mode310. Similarly, the secure privileged mode204comprises six sub-modes312-322. In particular, the secure privileged mode204comprises a secure supervisor mode312, a secure system mode314, a secure FIQ mode316, a secure IRQ mode318, a secure abort mode320, and a secure UNDEF mode322. Each of these modes, except for the supervisor and system modes, is dedicated to one or more software actions and is triggered by an exception vector. By contrast, the supervisor and system modes are execution modes.

Briefly referring toFIG. 1, the security mode of the system100is determined using security bits stored in the MPU102. Adjusting the security bits adjusts the security mode of the system100. Bus128, which couples the MPU102and the SSM104, provides a copy of the security bits to the SSM104so that the SSM104may determine the current security mode of the system100. Informing the SSM104of the current security mode of the system100enables the SSM104to protect the system100appropriately.

Each of the security modes shown inFIG. 3preferably is allocated a portion of the memory in storages106. At least some of the memory allocated to the security modes is in the form of “stacks,” which are data structures capable of storing data in a last-in, first-out (LIFO) format. Each security mode is assigned a different stack so that, for example, the stack of a secure mode is not corrupted by data associated with a non-secure mode. When the system100is operating in a particular security mode, the stack associated with that mode is used and stacks associated with other modes are not used.

In some cases, the system100may engage in multi-thread processing. Accordingly, some of the security modes shown inFIG. 3are assigned multiple stacks, each stack associated with a different thread (or “context”). For example, while in secure supervisor mode312, the MPU102may use a stack associated with the secure supervisor mode312to temporarily store data while executing in a first thread. If the MPU102needs to switch to a second thread while operating in the same secure supervisor mode312, a second stack associated with the secure supervisor mode312is used in the second thread. If the MPU102needs to resume operating in the first thread, the original stack is used in lieu of the second stack.

Referring toFIG. 1, when switching from a first thread to a second thread (and thus from a first stack to a second stack), the MPU102stores context information associated with the first stack in the SSM104. Context information may include the range of addresses associated with the first stack, a pointer indicating a current position in the first stack, and one or more bits indicating the type of security mode associated with the first stack. When the MPU102needs to resume using the first stack, the context information is retrieved from the SSM104and is used to find the first stack and to find the current position in the first stack.

The storage of context information in the SSM104is advantageous because the SSM104may use the context information to monitor the write and read buses112and114for malicious activity. The SSM104may conceivably use the context information to enforce security in myriad ways, and all such permutations are encompassed within the scope of this disclosure. In one possible security technique, the SSM104restricts access to the various memory stacks in the storage106to data accesses only. If the SSM104detects an attempt by the MPU102to fetch an instruction op-code from a stack, the SSM104generates one or more alert signals, which are serviced as described further below. In this way, the SSM104is able to thwart various types of attacks, such as buffer overflow attacks, which intend to hijack execution flow and which can involve the fetching of instruction op-codes off of dedicated security mode stacks in the storage106.

In another possible security technique, the SSM104ensures that each dedicated security mode stack in the storage106is protected from being accessed in unauthorized security modes. For example, if the SSM104determines (i.e., using the SECMON bus128) that the system100is in a non-secure user mode200and that the MPU102is attempting to access a stack that is associated with the monitor mode208, the SSM104generates one or more alert signals.

In still another possible security technique, the SSM104may be pre-programmed to monitor the write and read buses112and114for specific activities which, if detected, cause the SSM104to generate security violation signals. For example, if the SSM104determines via the write bus112that the MPU102is attempting to write to the same location in the same stack two consecutive times (as is often done with buffer overflow attacks), the SSM104may generate one or more alert signals. The SSM104is not limited to the protective security measures described above. Any and all such monitoring techniques are encompassed within the scope of this disclosure. The three possible security techniques specifically mentioned above are now described in detail with reference toFIG. 4.

FIG. 4shows the system100ofFIG. 1in detail. The MPU102comprises a core400which couples to a plurality of caches402, a memory management unit (MMU)404and an interrupt handler406. The storage106comprises an interconnect432which couples ROM424, RAM426, SDRAM428and FLASH430with the write and read buses112and114. The security enforcement module108comprises a security attack indicator420and a program reset control module422. The SSM104comprises a write access handler408and a read access handler410. The write access handler408couples to a static firewall416and a dynamic firewall418via bus434. The read access handler410couples to the static firewall416and the dynamic firewall418via bus436. The dynamic firewall418couples with a violation handler412via bus438and registers414via bus442. The static firewall416couples with the violation handler412via bus440and registers414via bus444. The violation handler412couples with the security attack indicator420via bus126A and the program reset control module422via bus126B. The violation handler412further couples with the interface110via bus446and the interrupt handler406via bus122.

As described above, memories in the storage106(e.g., ROM424, RAM426) allocate memory space for a plurality of dedicated security mode stacks. Each security mode of the system100is assigned to one or more of the stacks, so that when the system100is operating in a particular security mode, the stack of that security mode is used to temporarily store data. If a thread switch occurs from a first thread to a second thread, the context of the stack used in the first thread is stored in the registers414(e.g., via interface110and bus120), and a different stack is used in the second thread. As previously mentioned, the context of the stack may include information such as a range of memory addresses associated with the stack, a pointer indicating a current position in the stack, a security level associated with the stack, etc. In some embodiments, the registers414in the SSM104are programmed with the range of addresses associated with each dedicated security mode stack, as well as an identifier indicating the security mode associated with each stack.

Data writes performed via the write bus112are monitored by the write access handler408via bus118. Likewise, data reads performed via the read bus114are monitored by the read access handler410via bus116. The write and read access handlers408and410decode signals carried on the buses112and114and transfer the decoded signals to the static firewall416and dynamic firewall418via buses434and436, respectively.

Although each of the firewalls416and418monitors the decoded signals for different types of malicious activity, each of the firewalls operates in a similar manner. Specifically, each firewall receives a decoded signal from one of the write or read access handlers and compares the decoded signal to context information stored in the registers414. If, by performing such a comparison, a firewall determines that an attack is being carried out, the firewall sends a violation signal to the violation handler412. In turn, the violation handler412takes appropriate action to prevent or at least mitigate damage to the system100. Each of the firewalls is now described in turn.

The static firewall416preferably is a hardware-based firewall. The static firewall416uses signals received from the write and read access handlers408and410to detect malicious activity. Specifically, each signal processed by the read access handler408comprises a memory address and further comprises data associated with that memory address. The static firewall416compares the memory address with each of the ranges of addresses associated with the security mode stacks stored in the storage106. If the memory address falls within one of these ranges, and further if the static firewall416determines that the read signal is an attempt to fetch an instruction op-code from this memory address, then it is determined that the MPU102is attempting to fetch an instruction op-code from a dedicated security mode stack, an action which is indicative of a buffer overflow attack. Accordingly, the static firewall416issues a violation signal to the violation handler412via bus440. The violation handler412services the violation signal as described further below.

In addition, the static firewall416compares the address associated with each read and/or write signal to the ranges of addresses associated with the dedicated security mode stacks to determine if the MPU102is attempting to access a stack whose security level is higher than the current security level of the system100. Specifically, if it is determined that the MPU102is attempting to access a dedicated security mode stack, the static firewall416further compares the current security mode of the system100(i.e., determined using SECMON bus128) to the security mode associated with that stack. If the two security modes match, or if the current security mode of the system100is more secure than the security mode associated with the stack, the static firewall416preferably takes no action. However, if the two security modes do not match, or if the current security mode of the system100is less secure than the security mode associated with the stack, the static firewall416issues a violation signal to the violation handler412via bus440. The violation handler412services the violation signal as described further below.

Like the static firewall416, the dynamic firewall418preferably is a hardware-based firewall. The dynamic firewall418monitors stack accesses for activity that is indicative of a malicious attack. The dynamic firewall418may be programmed with one or more pre-determined activities which, if detected, indicate a malicious attack. If the activity detected on a read or write bus matches one of the pre-determined activities, the dynamic firewall418issues a violation signal to the violation handler412via bus438. For example, buffer overflow attacks are often characterized by the writing of data to the same memory location in the same stack two or more times in a row. If the dynamic firewall418detects two consecutive write signals that have the same destination memory address, and further if this destination memory address falls within an address ranges of a dedicated security mode stack (i.e., determined using registers414and bus442), the dynamic firewall418may issue a violation signal to the violation handler412via bus438.

Specifically, the dynamic firewall418may comprise a temporary storage (e.g., a register) in which it logs the destination memory address of each write operation to a dedicated security mode stack. Upon receiving a next write operation, the firewall418compares the destination address stored in the temporary storage with the destination memory address of the received write operation. If the two match, it is determined that the MPU102is attempting to write to the same location in the same stack two consecutive times in a row. As such activity is indicative of a buffer overflow attack, the firewall418issues a violation signal to the violation handler412via bus438. Multiple variations of this general security technique are possible, and the scope of this disclosure encompasses any and all such variations.

Upon receiving a violation signal from a firewall, the violation handler412takes appropriate action to prevent or at least mitigate damage to the system100. Specifically, the violation handler412decodes a received violation signal to determine what type of action should be taken in response to the malicious activity being carried out on the system100. In some cases, the violation handler412may send an alert signal to the program reset control module422, thereby resetting a currently executing program. In other cases, the violation handler412may send an alert signal to the security attack indicator420, thereby providing an indication to a user of the system100that system integrity has been compromised. Such an indication may take the form of a visual indication (e.g., an alert message on a display, a flashing light-emitting-diode (LED)), an audible indication (e.g., a ring tone or a beeping tone), or a tactile indication (e.g., vibration), although the scope of this disclosure is not limited to these possibilities. In yet other cases, the violation handler412may send an alert signal to the interface110, causing the interface110to abort a current instruction op-code fetch or data retrieval. In still other cases, the violation handler412may send an alert signal to the interrupt handler406, causing the interrupt handler406to stop the core400from executing malicious code. In some embodiments, a combination of one or more of the above alert signals may be generated by the violation handler412in response to a received violation signal. The violation handler412may comprise a data structure that cross-references various types of possible violation signals with suitable actions that may be taken in response to receipt of the violation signals.

FIG. 5shows a flow diagram of a method500usable in accordance with embodiments of the invention. The method500begins by determining a destination address of an access to storage106(block502) and determining whether the MPU102is attempting to access dedicated security mode stacks (block504). As described above, the firewalls in the SSM104may determine whether the MPU102is attempting to access dedicated security mode stacks by comparing the destination address of the access to the ranges of addresses stored in the registers414of the SSM104. If the MPU is not attempting to access the dedicated security mode stacks, control of the method500returns to block502. However, if the MPU is attempting to access one of the dedicated stacks, the method500also comprises determining whether the MPU is fetching an instruction op-code from the stack (block506). If the MPU is fetching an instruction op-code from the stack, the method500comprises issuing a violation signal (block512) and taking protective action (block514).

However, if the MPU is not fetching an op-code from a dedicated stack, the method500further comprises determining whether the current security mode of the system100(i.e., determined using the bus128) is more secure than or equivalent in security to the security mode of the destination stack of the current access (block508). If not, the method500comprises issuing a violation signal (block512) and taking protective action (block514). Otherwise, the method500comprises determining whether the destination address is the same as the destination address of a preceding write signal (block510). If the destination address of the current access is identical to that of a preceding write signal, a buffer overflow attack is likely being carried out on the system100. Accordingly, the method500comprises issuing a violation signal (block512) and taking protective action (block514). Otherwise, control of the method500resumes at block502.