Driving circuit for a magnetic head and magnetic recording apparatus

A magnetic head driving circuit includes a main driving circuit symmetrical with respect to a centered recording coil, and at least two pairs of adding circuits, each pair including a positive pulse adding circuit and a negative pulse superposed circuit symmetrical with respect to the centered coil. And, by reversing the direction of the magnetic head coil current, at least one of the adding circuits is made to operate and make it as a magnetic head driving circuit for adding a potential equal to or higher than the power supply, thereby to drive as a sub-driving circuit arranged symmetrically with respect to the centered coil, which promotes the reversal of the magnetic head coil current, and which drives stably with a central potential of the coil at about the disk potential.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a magnetic recording apparatus for generating, by a magnetic head, a magnetic field corresponding to data intended to record, and for recording the data on a recording medium by the generated magnetic field.

2. Description of the Related Art

Recently, in the magnetic recording apparatus such as a hard disk apparatus, the recording density has rapidly increased, and the writing speed has also increased.

In the magnetic recording apparatus, the writing of data is performed by reversing the direction of the current flowing through a magnetic head coil positioned close to a recording medium on which the writing is to be made, in accordance with the data to be recorded.

FIG. 10shows an outline of a magnetic head driving circuit of a magnetic recording apparatus (STEVE, L., DAVID, Y., “A 550 MB/S GMR READ/WRITE AMPLIFIER USING 0.5 UM 5V CMOS PROCESS”, ISSCC2000, PP358-359, FEBRUARY, 2000). InFIG. 10, the magnetic head driving circuit is formed by PMOS transistors MP1, MP2, and NMOS transistors MN7to MN10which operate as switches, NMOS transistors MN1, MN2, and PMOS transistors MP3, MP4which operate as protection devices, and a current mirror circuit including NMOS transistors MN3to MN7, MN10, and a current source IS1, and a DAMPING-RESISTOR circuit. This circuit is operated at a timing shown inFIG. 11, and each transistor and the DAMPING-RESISTOR circuit are controlled. A magnetic head coil is formed by an inductance component Lh and a resistance component Rh. At a time t1, by turning off the PMOS transistor MP1and the NMOS transistor MN10which have been turned on, and at the same time, by turning on the PMOS transistor MP2and the NMOS transistor MN7which have been turned off, the current which has been flowing in the magnetic head coil from a node HWL towards a node HWR is reversed to flow from the node HWR towards the node HWL, at this time due to the turning on of the NMOS transistor MN8only during a time interval until a time t2, a large voltage (here, the power supply voltage) is applied across both terminals of the magnetic head coil so that the reverse time of the current is shortened. Next, from the time t2to the time t3, assuming that the current flowing in the current source IS1is IW1, in the magnetic head coil, a constant current IW1flows from the node HWR towards the node HWL. Next, at the time t3, the PMOS transistor MP2and the NMOS transistor MN7which have been turned on are turned off, and at the same time, the PMOS transistor MP1and the NMOS transistor MN10which have been turned off are turned on, so that the current which has been flowing in the magnetic head coil from the node HWR towards the node HWL is reversed to flow from the node HWL towards the node HWR. At this time, since the NMOS transistor MN9is turned on only until the time t4, similar to the time period between the time t2and the time t3, a large voltage (here, the power supply voltage) is applied in a reverse direction to the case mentioned above across both terminals of the magnetic head coil, and the reverse time of the current is shortened. During the time period between the time t4and the time t5, a current IW1flows from the node HWL towards the node HWR, and thereafter from the time t5, performs the operation from the time t1repeatedly. Here, in the circuit described above, the problems mentioned below are supposed.

First, as a first problem, in recent years, there is a trend that the power supply voltage of the integrated circuits becomes lower than the withstand voltage of the transistors due to the fact that the device is made smaller, and the operating speed is made faster, and recently, it is 3V to 5V or lower. In the magnetic head driving circuit described in the foregoing, when the power supply voltage becomes low, the time required for reversing the current of the magnetic head coil increases. Furthermore, due to an increase of the data transfer speed accompanied by a large capacity of recent magnetic disk apparatus, further high speed rise/fall is requested, and in order to realize the high speed rise/fall with the above-mentioned magnetic head driving circuit, the power supply voltage must be increased. However, in the case of considering the withstand voltage of the device, it is necessary to insert at many stages the protection devices such as the transistors MP3, MP4, MN1, and MN2, and then in turn, the on-resistances of the protection devices can not be neglected. In order to decrease the on-resistance, it is necessary to increase the size of the protection devices. In particular, in the integrated circuits, the chip size, and the parasitic capacitance are increased, and this raises a problem in view of the economy and the switching speed.

Next, in recent years, there is a trend that the distance between the magnetic head and the recording medium is reduced (several tens of nm), and it is desired that the central potential of the magnetic head coil is stable near the disk potential from the view point of discharge prevention between the magnetic head and the disk. However, in the present circuit, assuming that the current flowing in the current source IS1is IW1, the resistance of the magnetic head coil RH≈0, and the on-resistance of each transistor is; RMP1=RMP2=RPON1, RMP3=RMP4=RPON2, RMN1=RMN2=RNON1, RMN8=RMN9=RNON2, at the time t1, the central potential VHC of the magnetic head coil is changed from VCC−IW1×(RPON1+RPON2) to VCC×(RPON1+RNON2)/(RPON1+RPON2+RNON1+RNON2) potential, and at the time t2, returns to VCC−IW1×(RPON1+RPON2). Here, since each transistor MP1to MP4, MN1, MN2, MN7, MN8is a switch and a protection device, assuming that its on-resistance is sufficiently small and equal, ultimately, the central potential of the magnetic head coil becomes approximately VCC→VCC/2→VCC as shown in FIG.11. Also, at times t3, and t4, a similar change is exhibited, and there is also a problem that at the time of reversal of the direction of the magnetic head coil current, the central potential of the magnetic head coil is varied to a great extent.

SUMMARY OF THE INVENTION

The object of the present invention is, even when the power supply voltage is made low, capable of applying a sufficient voltage equal to or greater than the power supply voltage to both terminals of the magnetic head coil while suppressing the voltage applied to a driving transistor at the time of reversal of the magnetic head coil current, thereby to reduce the reverse time of the magnetic head coil current, and to enable to drive the central potential of the magnetic head coil stably at the vicinity of the disk potential even at the time of reversal of the magnetic head coil current. Furthermore, it is intended to realize a magnetic head driving circuit which reduces the reverse time and allows to cause an overshoot.

In order to achieve the object mentioned above, there is provided a magnetic head driving circuit which comprises a main driving circuit including at least one coil for data writing; and a sub-driving circuit including at least two pairs of adding circuits, one of which includes a positive pulse adding circuit connected to one terminal of the coil and a negative pulse adding circuit connected to the other terminal of the coil, and the other of which includes a negative pulse adding circuit and a positive pulse adding circuit, each of the circuits connected to the opposite terminal of the former pair. At the time of reversing the current direction of the coil by the main driving circuit, at least one pair of the adding circuit is operated so that a potential difference equal to or greater than the power supply is applied to both terminals of the coil, thereby to promote the reversal of the current of the coil, and to drive stable with the central potential of the coil being near the disk potential.

DETAILED DESCRIPTION OF THE EMBODIMENTS

Hereinafter, a first embodiment will be explained with reference to the drawings.FIG. 1shows—a configuration example of the embodiment. As shown inFIG. 1, a magnetic head driving circuit relating to a magnetic recording apparatus is constituted by a controller1, a main driving circuit2, a sub-driving circuit10, and a magnetic head coil9.

First, the main driving circuit2is formed by switches3to6, and resistors7,8.

The controller1is a circuit for changing the direction of a magnetizing current Iw flowing through the magnetic head coil9by changing over the on/off of the switches3,5and switches4,6of the main driving circuit2as shown inFIG. 2, and at the same time generates a control signal of the sub-driving circuit10. A steady state current Iw is expressed by expression 2, under the condition of expression 1.

Next, the sub-driving circuit10is connected symmetrically with respect to the magnetic head coil9as two sets (11and12), and each set is constituted by a pair of positive pulse adding circuit13and negative pulse adding circuit14.

Next, the operation of the present embodiment will be explained. By the control signal, shown inFIG. 2, output from the controller1, the main driving circuit2and the sub-driving circuit10are controlled. At a time t1, the switches4,5having been turned on are turned off, and the switches3,6having been turned off are turned on. Also, at the same time, the adding circuit11of the sub-driving circuit10is turned on at the time t1and is turned off at a time t2. At this time, the magnetizing current Iw flowing from a node Hy towards a node Hx is reversed from the node Hx towards the node Hy. On the other hand, by the adding circuit11which is turned on at the same time, the potential at both terminals of the magnetic head coil9become states as shown inFIG. 2, and a large voltage VL is generated at both terminals of the magnetic head coil9. Because of this, until the adding circuit11is turned off at the time t2, the change of the magnetizing current Iw is promoted, and the reverse time is shortened. Next, during the time t3to t5, the reverse operation to that mentioned above is carried out. That is, at the time t3, the switches4,5which have been turned off, are turned on, and the switches3,6which have been turned on, are turned off. Also, at the same time, adding circuit12of the sub-driving circuit10is turned on at the time t3, and is turned off at the time t4. At this time, magnetizing current Iw flowing from the node Hy towards the node Hx is reversed to flow from the node Hx towards the node Hy. On the other hand, due to the adding circuit12which is turned on at the same time, the potentials VHx and VHy at both terminals of the magnetic head coil9become states as shown inFIG. 2, and a large voltage VL is generated at the time t3at both terminals of the magnetic head coil9. Because of this, until the adding circuit12is turned off at the time t4, the change of the magnetizing current Iw is promoted, and the reverse time is shortened.

The resistors7and8limit the current flowing through the magnetic head coil9at the steady state, and serve as the output terminals of the main driving circuit2, and they are always connected in series with the magnetic head coil9. Owing to this, when a large voltage is generated at both the terminals of the coil, the voltage emerged on the switches is divided by the resistors7,8and the on-resistances of the switches. Normally, since the on-resistance of the switch is sufficiently small, the application of the large voltage to the switch devices can be prevented.

Also, the steady state magnetizing current Iw is expressed by expression 2 under the condition of expression 1.
Ron3=Ron5, andRon4=Ron6, andR7=R8(1)
Iw=(Vcc−VEE)/(R7+R8+Ron3+Ron4)  (2)

In particular, by making the on-resistances Ron3to Ron6satisfy the expression 3, and by setting the power supply voltage Vcc and VEEas in expression 4, it is possible to make the central potential of the magnetic head coil9at about 0 volt.
Ron3=Ron4=Ron5=Ron6(3)
VEE=−Vcc(4)
Next, by symmetrically arranged and symmetrically operating sub-driving circuit10, as shown inFIG. 2, at the time of changing the direction of the current, a large voltage VL is made to be generated so that the switching time is shortened, and also the central potential VHc of the magnetic head coil9is maintained at about the disk potential.

Next,FIGS. 3 and 4show a configuration example of the adding circuit. First, the positive pulse adding circuit13shown inFIG. 3includes switches15to17, a diode18and a capacitor19. The positive pulse adding circuit13is controlled by a signal from the controller1at a non-operating time and at an operating time. In the positive pulse adding circuit13, at the non-operating time, the switches15and16are in off-state, and the switch17enters on-state, and by forming a series circuit of the diode18and the capacitor19, the capacitor19is charged, and the voltage Vc of expression 5 is generated at both terminals of the capacitor19.
Vc=Vcc−VEE−Vpn(5)
But, Vpn is a forward voltage of the diode18, and it is supposed that the on-resistance of the switches can be neglected.

Also, at the operating time, since the switches15and16enter the on-state, and the switch17enters the off-state, the voltage at a node T2is Vcc, and a node T1indicates a voltage VT1given by expression 6. At this time, the diode18is reverse-biased and automatically turned off.
VT1=2Vcc−VEE−Vpn(6)
But, Vpn is a forward voltage of the diode18, and it is supposed that the on-resistance of the switches can be neglected.

Next, the negative pulse adding circuit14includes switches20to22and a diode23and a capacitor24, and performs a reverse operation to the above-mentioned positive pulse adding circuit13. Specifically, by the controller1, similar to the positive pulse adding circuit13, the operating time and the non-operating time are controlled, and at the non-operating time, switches20and21become the off state, the switch22becomes on state, and by constituting a series circuit of a diode23and a capacitor24, the capacitor24is charged, and similar to the positive pulse adding circuit13, a voltage Vc is emerged at both terminals of the capacitor24. Also, at the operating time, since the switches20and21become the on-state, and the switch22becomes the off-state, the voltage of a node T3isVEE, and the voltage VT4given by the expression 7 is emerged at a node T4. At this time, the diode23is reverse-biased and automatically turned off.
VT4=2VEE−Vcc+Vpn(7)
But, Vpn is a forward voltage of the diode23, and it is supposed that the on-resistance of the switches can be neglected.

From the above description, the potentials VHx, VHy at both terminals of the magnetic head coil9shown inFIG. 2, and the potential difference VL generated in the magnetic head coil9is expressed as follows.
VHx=2Vcc−VEE−Vpn(8)
VHy=2VEE−Vcc+Vpn(9)
VL=3(Vcc−VEE)−2Vpn(10)
Also, the potential VHx, VHy at both terminals of the magnetic head coil9at a node T3are similarly expressed as follows, and the voltage VL the same as expression 10, at both terminals of the coil is obtained.
VHx=2VEE−Vcc+Vpn(11)
VHy=2Vcc−VEE−Vpn(12)

Next, referring toFIGS. 5 and 6, examples of concrete configuration of the switches15to17,20to22in the positive pulse adding circuit13and the negative pulse adding circuit14will be explained. In the present embodiment, the switches15,16,22use a switch circuit S1inFIG. 5, and the switches17,20,21uses a switch circuit S2in FIG.6.

First, the switch circuit S1will be explained. This switch circuit S1is constituted by an NPN transistor25, a PMOS transistor26connected between a collector and a base of the NPN transistor25, and a PMOS transistor27connected between the base and an emitter of the NPN transistor25. When the switch circuit S1is an on-state, the PMOS transistor26is turned on by making the gate of the PMOS transistor26at low level, thereby to make a short circuit between the collector and the base of the NPN transistor25, and the PMOS transistor27is turned off by making the gate of the PMOS transistor27at high level, thereby to open between the base and the emitter of the NPN transistor25. As a result, the NPN transistor25indicates a diode connection of forward bias between a node T5and a node T6, and the switch circuit S1becomes the on-state. On the other hand, when the switch circuit S1is off-state, the PMOS transistor26is turned off by making the gate of the PMOS transistor26at high level, thereby to open between the collector and the base of the NPN transistor25, and the PMOS transistor27is turned on by making the gate of the PMOS transistor27at low level, thereby to make a short circuit between the base and the emitter of the NPN transistor25. As a result, the NPN transistor25indicates a diode connection of reverse bias between the node T5and the node T6, and switch circuit S1becomes the off-state.

Next, the switch circuit S2is constituted by an NPN transistor28, an NMOS transistor29connected between a collector and a base of the NPN transistor28, and an NMOS transistor30connected between the base and an emitter of the NPN transistor28. When the switch circuit S2is an on-state, the NMOS transistor29is turned on by making the gate of the NMOS transistor29at high level, thereby to make a short circuit between the collector and the base of the NPN transistor28, and the NMOS transistor30is turned off by making the gate of the NMOS transistor30at low level, thereby to open between the base and the emitter of the NPN transistor28. As a result, the NPN transistor28indicates a diode connection of forward bias between a node T7and a node T8, and the switch circuit S2becomes on-state. On the other hand, when the switch circuit S2is in an off-state, the NMOS transistor29is turned off by making the gate of the NMOS transistor29at low level, thereby to open between the collector and the base of the NPN transistor28, and the NMOS transistor30is turned on by making the gate of the NMOS transistor30at high level, thereby to make a short circuit between the base and the emitter of the NPN transistor28. As a result, the NPN transistor28indicates a diode connection of reverse bias between the node T7and the node T8, and switch circuit S2becomes the off-state.

These switch circuits are, when they are on-state, equivalent to a forward-biased diode and the on-resistance is small. Furthermore, by controlling the gates of vertically stacked same type of MOS transistors with signals of opposite phase, the influence of the parasitic capacitances (a capacitance between gate and drain, and a capacitance between gate and source) of the upper stage MOS transistors26,29is cancelled out by the influence of the parasitic capacitances (a capacitance between gate and source, and a capacitance between gate and drain) of the lower stage MOS transistors27,30, and thus the switching speed is also fast.

Next, in the magnetic head driving circuit, it is necessary to change a steady state current depending on the magnetic head and the magnetic recording disk, and it is necessary to maintain the central potential of the magnetic head coil at about 0 volt. As a method for this, the Vcc and VEEpotentials are changed. An example of configuration to achieve such Vcc, VEEwill be explained with reference toFIGS. 7,8and9. As shown inFIG. 7, a ground terminal of a magnetic head driving circuit of an integrated circuit31including the magnetic head driving circuit of the present embodiment and a ground of a driving apparatus33for driving a magnetic disk32are connected to a ground34of a magnetic recording apparatus and the ground34is shared.

FIG. 8shows an example of configuration to achieve the Vcc. A voltage Vref1on the basis of the ground34is expressed by a current Iref1flowing to a current source35and a resistor37(R37) by expression 14, and by outputting by using an NPN transistor36as an emitter follower, Vcc expressed by expression 15 is realized.
Vref1=Iref1×R37(14)
Vcc=Vref1−Vthnpn=Iref1×R37−Vthnpn(15)
Also,FIG. 9shows an example of configuration to achieve the VEE. Similar to the above-mentioned Vcc, a voltage Vref2on the basis of the ground34is expressed by a current Iref2flowing to a current source38and a resistor40(R40) by expression 16, and by outputting by using the NPN transistor39as an emitter follower, VEEof expression 17 is realized.
Vref2=−Iref2×R40(16)
VEE=Vref2+Vthpnp=−Iref2×R40+Vthpnp(17)
Here, supposing that, Iref1=Iref2, Vthnpn=Vthpnp, R38=R40, expression 18 is introduced, and Vcc and VEEwhich are symmetrical with respect to the ground34can be obtained, and the central potential of the magnetic head coil9can be controlled to be at about 0 volt, and further, the current Iw flowing through the magnetic head coil9in the steady state can be expressed by expression 19, and it can be controlled by Iref1.
Vcc=Vref1−Vthnpn=−(Iref2×R40+Vthnpn)=−VEE(18)
Iw=(Vcc−VEE)/(R7+R8)=Iref1×2R38/(R7+R8)  (19)

In the above description, both Vcc and VEEare controlled, however, in the magnetic recording apparatus which does not require to such an extent, only Vcc or VEEmay be controlled.

As described in the foregoing, in the present invention, in the magnetic recording apparatus for recording by magnetizing the medium by supplying the magnetizing current corresponding to recording data to the magnetic head coil, there are provided with the magnetic head coil and the main driving circuit symmetrical with respect to the centered magnetic head coil, and the symmetrical sub-driving circuit including at least two pairs of adding circuits, each pair including a positive pulse adding circuit and a negative pulse adding circuit symmetrical with respect to the centered magnetic head coil, and at the time of reversing the direction of the magnetizing current flowing through the magnetic head coil by the main driving circuit, at least one pair of adding circuit of the sub-driving circuit is operated, and positive and negative symmetrical voltages for promoting the reversal of the magnetizing current centered on the magnetic head coil are added, thereby to suppress the variation of the central potential of the magnetic head coil, and to reduce the reverse time, and to enable to reduce the voltage of the power supply voltage. Here, by making the central potential of the magnetic head coil the same as the magnetic disk potential, there is an advantage of preventing the discharge of the magnetic disk. Furthermore, by superposing a voltage to both terminals of the magnetic head coil by the sub-driving circuit, even when under the limited voltage of the withstand voltage of the device of the main driving circuit, it is possible to generate a voltage larger than the power supply voltage in the magnetic head coil, and it is possible to realize the lower voltage of the power supply voltage. Furthermore, at the output of the main driving circuit, by always connecting the resistor in series with the magnetic head coil, when the voltage is adding to both terminals of the magnetic head coil by the sub-driving circuit, there is an advantage of preventing the adding voltage from being applied directly to the main driving circuit.

In the above description, the main driving circuit is constituted by using four semiconductor switches, however, the symmetrical sub-driving circuit for applying a large voltage to both terminals of the coil is naturally applicable to the related art example shown in FIG.10.

Also, in order to obtain the characteristics described above, it is possible to suitably change the configuration of the head driving circuit, and the control method (pulse timing, pulse voltage).