ELECTRONIC DEVICES INCLUDING OXIDE DIELECTRIC AND INTERFACE LAYERS

An electronic device may include a substrate, an oxide dielectric layer on the substrate, an interface layer on the oxide dielectric layer, and an electrode on the interface layer. The oxide dielectric layer may include an aluminum oxide layer between first and second zirconium oxide layers. The interface layer may have a first formation enthalpy, and the oxide dielectric layer may be between the substrate and the interface layer. The electrode may have a second formation enthalpy higher than the first formation enthalpy, and the interface layer may be between the oxide dielectric layer and the electrode.

DETAILED DESCRIPTION OF THE EMBODIMENTS

Present inventive concepts will now be described more fully hereinafter with reference to the accompanying drawings, in which examples of embodiments of inventive concepts are shown, Inventive concepts may, however, be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of inventive concepts to those skilled in the art. The same reference numbers indicate the same components throughout the specification. In the attached figures, thicknesses of layers and/or regions may be exaggerated for clarity.

It will also be understood that when a layer/element is referred to as being “on” another layer/element or substrate, it can be directly on the other layer/element or substrate, or intervening layers/elements may also be present. In contrast, when a layer/element is referred to as being “directly on” another layer/element, there are no intervening layers/elements present.

It will be understood that, although the terms first, second, etc. may be used herein to describe various layers/elements, these layers/elements should not be limited by these terms. These terms are only used to distinguish one layer/element from another layer/element. Thus, for example, a first layer/element, a first component or a first section discussed below could be termed a second layer/element, a second component or a second section without departing from the teachings of present inventive concepts.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the inventive concepts belong. It is noted that the use of any and all examples, or exemplary terms provided herein is intended merely to better illuminate inventive concepts and is not a limitation on the scope of inventive concepts unless otherwise specified. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

Hereinafter, a semiconductor device according to first embodiments of present inventive concepts will be described with reference toFIGS. 1 to 2B.

FIG. 1illustrates a cross-sectional view of a semiconductor device according to first embodiments, andFIG. 2Ais a diagram illustrating the formation enthalpy between a second conductor and an interface layer shown inFIG. 1.FIG. 2Bis a graph illustrating the formation enthalpy between TiN and TiOxused as the second conductor and the interface layer shown inFIG. 1, respectively.

Referring toFIG. 1, semiconductor device1includes a first conductor10, an oxide dielectric layer20, an interface layer25and a second conductor30.

The first conductor10may include at least one selected from the group consisting of doped polysilicon, a conductive metal nitrite (for example, titanium nitride, tantalum nitride or tungsten nitride), a metal (for example, ruthenium, iridium, titanium or tantalum), and a conductive metal oxide (for example, iridium oxide). Alternatively, the first conductor10may be a doped portion of a semiconductor substrate, for example, a P-type substrate, or an N-type substrate.

As will be described below with reference toFIGS. 5 to 7, the first conductor10may be a lower electrode of a capacitor. Alternatively, the first conductor10may be a channel region of a transistor.

The oxide dielectric layer20is formed on the first conductor10. The oxide dielectric layer20may be, for example, a metal oxide dielectric layer, and may include a high-k dielectric layer. The high-k dielectric layer may include, for example, zirconium oxide (ZrO2), hafnium oxide (HfO2), zirconium silicon oxide (ZrSiOx), hafnium silicon oxide (HfSiOx), zirconium hafnium silicon oxide (ZrHfSiOx), aluminum oxide (Al2O3) and combinations thereof, but not limited thereto.

The interface layer25is formed on the oxide dielectric layer20. The interface layer25may include, for example, an oxygen-containing compound, such as a metal oxide.

The interface layer25may include, for example, one of titanium oxide (TiOx, where 0<x<2), aluminum oxide (AlOx, where 1<x<2), titanium aluminum oxide (TiyAl1-yOx, where 0<x<2) and manganese oxide (MnOx, where 0<x<2). If the interface layer25is titanium aluminum oxide, a ratio of a metal element contained in the interface layer25to an aluminum element may be in a range of, for example, 0.001 to 0.5. In other words, the interface layer25may include a compound further including aluminum in titanium oxide.

The interface layer25may include at least one of TixOy, AlxOy, TixAlz, and/or MnxOywhere a ratio of a number of oxygen atoms to a number metal atoms is in the range of 1 to 2. The ratio of the number of oxygen atoms to the number of metal atoms may be greater than 1 and no greater than 2, and more particularly, greater than 1 and less than 2.

In the metal oxide forming the interface layer25, the metal contained in the metal oxide may be a transition metal and may have several oxidation numbers. Therefore, the metal contained in the metal oxide forming the interface layer25is bonded with oxygen, thereby forming compounds having various chemical formulas. For example, when the interface layer25is titanium oxide, titanium as a metal element contained in the titanium oxide may have multiple oxidation numbers, thereby forming a variety of oxides, including TiO, Ti2O3, Ti3O5, Ti4O7, and TiO2,

The interface layer25may be sufficiently thin so that it does not act as a dielectric layer. The thickness of the interface layer25may be in a range of, for example, 1 Å (Angstrom) to 10 Å (Angstroms), In addition, the thickness of the interface layer25may be less than that of the oxide dielectric layer20.

In the semiconductor device according to first embodiments, the interface layer25may be a conductive layer that is electrified. That is to say, the interface layer25formed on the oxide dielectric layer20may serve as an electrode or a portion of an electrode providing an electric signal/field to the oxide dielectric layer20. During the manufacturing process of the semiconductor device, the interface layer25may be formed from a pre-interface layer (25aofFIG. 9), and it may include oxygen vacancies. Since oxygen vacancies in the interface layer25may form a current path, along which electrical current can flow, the interface layer25may be a conductive layer that is electrified.

The interface layer25can reduce/prevent diffusion of oxygen atoms contained in the oxide dielectric layer20into the second conductor30, and may function as an oxygen donating layer providing oxygen atoms to the second conductor30during the manufacturing process of the semiconductor device. In addition, the interface layer25may reduce/prevent penetration of nitrogen atoms contained in the second conductor30into the oxide dielectric layer20. Functions of the interface layer25will be described below in greater detail.

The second conductor30is formed on the interface layer25to be in contact with the interface layer25. In detail, the second conductor30may make direct contact with the interface layer25. The second conductor30may be made of a conductive metal nitride and may include, for example, at least one of titanium nitride (TiN), zirconium nitride (ZrN), aluminum nitride (AIN), hafnium nitride (HfN), tantalum nitride (TaN), niobium nitride (NbN), yttrium nitride (YN), lanthanium nitride (LaN), vanadium nitride (VN), and/or manganese nitride (Mn4N).

As will be described below with reference toFIGS. 5 to 7, the second conductor30may be an upper electrode of a capacitor. Alternatively, the second conductor30may be a gate electrode of a transistor.

First, reducing/preventing diffusion of oxygen atoms contained in the oxide dielectric layer20into the second conductor30, which may be a function of the interface layer25, will be described in view of formation enthalpy.

The relationship between the interface layer25and the second conductor30may be as follows. Formation enthalpy having a negative value may suggest that the energy state of a reaction start material is higher than that of a reaction end product, and formation enthalpy having a positive value may suggest that the energy state of a reaction start material is lower than that of a reaction end product. From the view point of stoichiometry, a substance generally tends to move to a lower energy state. This tendency may change according to ambient reaction conditions, though.

Referring toFIGS. 1 and 2A, reference symbol a denotes the second conductor30, and reference symbol b denotes the interface layer25. In addition, a portion existing at the right side of b (i.e., below the interface layer25), denotes the oxide dielectric layer20. The second conductor30may have first formation enthalpy H1, and the interface layer25may have second formation enthalpy H2. The first formation enthalpy H1 is higher than the second formation enthalpy H2. That is to say, the formation enthalpy H1 of the second conductor30is higher than the formation enthalpy H2 of the interface layer25.

FIG. 2Ashows that the formation enthalpy of the oxide dielectric layer20may be positioned between the formation enthalpy H1 of the second conductor30and the formation enthalpy H2 of the interface layer25, which is, however, provided only for illustration, but aspects of present inventive concepts are not limited thereto.

In semiconductor devices according to embodiments of present inventive concepts, the formation enthalpy H2 of the metal oxide forming the interface layer25may be the lowest one of formation enthalpies of compounds that can be formed by binding metal elements of the metal oxide forming the interface layer25with oxygen atoms.

A substance having low formation enthalpy may be in a more stable state than a substance having high formation enthalpy. That is to say, in order to convert the substance having low formation enthalpy into the substance having high formation enthalpy, a relatively large amount of energy may be required. In order to allow oxygen atoms to diffuse from the oxide dielectric layer20and then move to the second conductor30, the oxygen atoms should pass through the interface layer25. However, since the formation enthalpy H2 of the interface layer25is lowest among formation enthalpies of compounds that can be formed by binding metal elements of the metal oxide forming the interface layer25with the oxygen atoms, the oxygen atoms contained in the oxide dielectric layer20are diffused into the interface layer25, so that an oxygen concentration of the interface layer25may increase. In such a case, the formation enthalpy of the interface layer25may increase.

However, a substance may tend to be maintained at a lower energy state. Thus, even if the oxygen atoms diffuse from the oxide dielectric layer20, they may not pass through an interface between the interface layer25and the oxide dielectric layer20. That is to say, the interface layer25may reduce/prevent diffusion of oxygen atoms contained in the oxide dielectric layer20into the second conductor30. In other words, the interface layer25having low formation enthalpy is positioned between the second conductor30and the oxide dielectric layer20. That is to say, the interface layer25may function as a potential barrier, thereby reducing/preventing movement of the oxygen atoms contained in the oxide dielectric layer20to the second conductor30,

In more detail, in a case where TiN and TiOxare used as the second conductor30and the interface layer25, respectively, the formation enthalpy relationship between the second conductor30and the interface layer25will be described with reference toFIG. 2B.

The second conductor30and the interface layer25may include the same metal element, that is, titanium. Here, the second conductor30is a metal nitride, and the interface layer25is a metal oxide.

The formation enthalpy of the titanium nitride contained in the second conductor30is higher than that of titanium oxide (TiOx) contained in the interface layer25. InFIG. 2B, since formation enthalpies of various kinds of titanium oxides are lower than the formation enthalpy of the titanium nitride, the interface layer25containing titanium oxide may be in a more stable energy state than the second conductor30containing titanium nitride.

In order to allow the oxygen atoms contained in the oxide dielectric layer20to diffuse into and move to the second conductor30containing titanium nitride, the oxygen atoms contained in the oxide dielectric layer20would pass through the interface layer25containing titanium oxide in a more stable energy state than titanium nitride. However, since the titanium oxide may function as a potential barrier against oxygen diffusion, the interface layer25may reduce/prevent diffusion of oxygen atoms from the oxide dielectric layer20to the second conductor30containing the titanium nitride.

Next, a function performed by the interface layer25may be to serve as an oxygen donating layer providing oxygen atoms to the second conductor30, instead of the oxide dielectric layer20, during the manufacturing process of the semiconductor device. That is to say, the interface layer25may be an oxygen sacrificial layer supplying oxygen.

In the semiconductor device according to first embodiments, the formation enthalpy of the second conductor30may be higher than that of the oxide of the interface layer25, which may be produced by oxidizing the second conductor30. Referring toFIG. 2B, when the titanium nitride to be contained in the second conductor30reacts with oxygen to turn into titanium oxide, the formation enthalpy may be lowered. That is to say, if titanium nitride is oxidized, titanium oxide (which has a more stable energy state than titanium nitride) is produced.

That is to say, if the second conductor30is formed on the oxide dielectric layer20, the second conductor30may take oxygen atoms contained in the oxide dielectric layer20. However, if the oxygen atoms contained in the oxide dielectric layer20are taken by the second conductor30, the capacitance of the oxide dielectric layer20may be lowered and the reliability of the dielectric layer20may also be reduced.

These disadvantages may be overcome/reduced by introducing the interface layer25containing metal oxide. In other words, the interface layer25may reduce/prevent diffusion of oxygen atoms contained in the oxide dielectric layer20into the second conductor30while providing some of the oxygen atoms contained in the interface layer25to the second conductor30. In such a manner, the interface layer25may improve electrical characteristics of a structure including the oxide dielectric layer20and the second conductor30.

In detail, when the second conductor30is made of a metal nitride and the metal element of the second conductor30is bonded with oxygen, forming an oxide, it may become stabilized in view of energy by accepting oxygen atoms supplied from the interface layer25. However, the oxygen atoms supplied from the interface layer25to the second conductor30may not form a metal oxide layer with the metal element due to formation conditions of the second conductor30, and may escape from the second conductor30, but aspects of present inventive concepts are not limited thereto.

During the manufacturing process of the semiconductor device, the interface layer25is formed such that the number of oxygen atoms bonded for each metal atom is relatively low. In other words, during the manufacturing process of the semiconductor device, the interface layer25is formed from a pre-interface layer (25aofFIG. 9). That is to say, the oxygen atoms remaining while the pre-interface layer is converted to the interface layer25may be supplied to an ambient layer, that is, the second conductor30or the oxide dielectric layer20. Since the oxide dielectric layer20is to be formed according to the stoichiometry, the remaining oxygen atoms produced from the interface layer25may be supplied to the second conductor30.

In addition, before the interface layer25is formed, a pre-interface layer may be formed to have a stoichiometric composition. Therefore, the interface layer25, formed when the pre-interface layer loses oxygen atoms, may include a compound having a nonstoichiometric composition. That is to say, materials forming the interface layer25are bonded to each other with a composition ratio not satisfying the stoichiometry,

In other words, a concentration of oxygen contained in the interface layer25may be smaller than that of the oxygen contained in a pre-interface layer formed to have the stoichiometric composition.

Referring toFIG. 2B, for example, a pre-interface layer may include TiO2having a stoichiometric composition, while the interface layer25formed when the pre-interface layer loses some oxygen atoms may include TiOx, where 0<x<2, which does not have the stoichiometric composition. When oxygen concentrations of TiO2and TiOxare compared, the concentration of the oxygen contained in TiO2contained in the pre-interface layer is greater than that of the oxygen contained in TiOxcontained in the interface layer25.

Next, reducing/preventing diffusion of nitrogen atoms contained in the second conductor30into the oxide dielectric layer20, which may be a function of the interface layer25, will be described. That is to say, the interface layer25may serve as a nitrogen diffusion reduction/prevention layer.

As described above, the second conductor30may include a metal nitride. In a case where the second conductor30is disposed on the oxide dielectric layer20without using the interface layer25, nitrogen atoms contained in the second conductor30may diffuse into the oxide dielectric layer20, so that oxynitride may be formed in the oxide dielectric layer20.

When an oxynitride layer is formed due to diffusion of nitrogen atoms into the oxide dielectric layer20, a crystallization temperature of the oxide dielectric layer20may rise. In detail, the crystallization temperature of the oxide dielectric layer20may be higher than that of the oxide dielectric layer20with the nitrogen atoms diffused therein.

Thus, during the manufacturing process of the semiconductor device, to crystallize the deposited oxide dielectric layer20, it may be necessary to anneal the oxide dielectric layer20at a higher temperature. If the oxide dielectric layer20with the nitrogen atoms diffused therein is crystallized at a crystallization temperature of the oxide dielectric layer20without nitrogen atoms, the oxide dielectric layer20with the nitrogen atoms may not be properly crystallized, reducing crystallinity of the oxide dielectric layer20.

However, the interface layer25capable of reducing/preventing penetration/diffusion of nitrogen into the oxide dielectric layer20is inserted between the oxide dielectric layer20and the second conductor30, thereby allowing crystallization of the oxide dielectric layer20at a relatively low temperature. Accordingly, the crystallinity of the oxide dielectric layer20can be improved.

In semiconductor devices according to some embodiments, the interface layer25is formed only between the oxide dielectric layer20and the second conductor30and not between the oxide dielectric layer20and the first conductor10. That is to say, interface layers25are not symmetrically formed at opposite sides of the oxide dielectric layer with the oxide dielectric layer20interposed therebetween. Since the interface layer having second formation enthalpy H2 is not formed between the first conductor10and the oxide dielectric layer20, oxygen atoms from the oxide dielectric layer20may more easily diffuse to the first conductor10. Stated in other words, a barrier layer capable of reducing/preventing oxygen diffusion may be omitted between the first conductor10and the oxide dielectric layer20.

A semiconductor device according to second embodiments of present inventive concepts will be described with reference toFIG. 3. Since the embodiment ofFIG. 3is similar to the first embodiment ofFIG. 1, except that an insertion layer is further formed between an interface layer and an oxide dielectric layer, elements/layers that are the same as those ofFIG. 1are denoted by the same reference numerals, and repeated descriptions thereof will be briefly made or will be omitted.

FIG. 3illustrates a semiconductor device according to second embodiments of present inventive concepts,

Referring toFIG. 3, the semiconductor device2according to second embodiments includes a first conductor10, an oxide dielectric layer20, an insertion layer23, an interface layer25, and a second conductor30.

The oxide dielectric layer20, the interface layer25and the second conductor30are sequentially formed on the first conductor10.

The insertion layer23is provided between the oxide dielectric layer20and the interface layer25. The insertion layer23is formed to be in contact with the interface layer25. That is to say, the interface layer25may be in direct contact with the insertion layer23and the second conductor30, between the insertion layer23and the second conductor30. Along with the interface layer25, the insertion layer23may prevent/reduce diffusion of oxygen atoms contained in the oxide dielectric layer20into the second conductor30. That is to say, the insertion layer23may be another oxygen diffusion reducing/preventing layer, which can supplement the oxygen diffusion preventing/reducing function performed by the interface layer25.

The insertion layer23may include an oxygen containing compound. In greater detail, the insertion layer23may include aluminum oxide (Al2O3). Aluminum contained in the insertion layer23may exist in the insertion layer23in the form of an Al3+ion, having relatively strong oxygen affinity. Therefore, the insertion layer23may prevent/reduce diffusion of oxygen contained in the oxide dielectric layer20into the second conductor30through the insertion layer23.

In order to prevent/reduce lowering of a dielectric constant of the oxide dielectric layer20and/or to reduce/minimize the interface layer25from functioning as a dielectric layer, the insertion layer23may have a thickness in a range of, for example, 1 Å (Angstrom) to 5 Å (Angstroms), In addition, the thickness of the insertion layer23may be less than that of the interface layer25.

In the semiconductor device according to second embodiments, an oxygen diffusion preventing/reducing layer (to prevent/reduce oxygen diffusion in the oxide dielectric layer20) may have a double layered structure including the interface layer25and the insertion layer23.

Although the oxygen diffusion preventing/reducing layer on the oxide dielectric layer20has a double layered structure, the interface layer25of the oxygen diffusion preventing/reducing layer is a conductive layer and the insertion layer23of the oxygen diffusion preventing/reducing layer is a dielectric layer.

The use semiconductor devices1and2shown inFIGS. 1 and 3, for information storage units of memory devices will now be described with reference toFIGS. 4 to 6. In the following description, the information storage units are capacitors, but aspects of present inventive concepts are not limited thereto.

FIG. 4is a layout view illustrating semiconductor devices according to third and fourth embodiments of present inventive concepts. That is to say,FIG. 4is a layout view illustrating semiconductor devices prior to formation of the information storage units (i.e., capacitors).

Referring toFIG. 4, in the semiconductor device according to second embodiments, a unit active region(s)103is defined by forming an isolation region(s)105in a substrate100.

In greater detail, each unit active region103extends in a first direction DR1, each gate electrode (that is, word line)130extends in a second direction DR2 (which forms an acute angle with respect to the first direction DR1), and each bit line170extends in a third direction D3, which forms an acute angle with respect to the first direction DR1.

Here, the term “angle” used in the phrase “a predetermined angle formed between a particular direction and another particular direction” may mean a smaller angle of two angles formed when two directions cross each other, for example, 60° in a case where angles formed by two crossing directions are 120° and 60°. Therefore, as shown inFIG. 4, an angle formed by the first direction DR1 and the second direction DR2 is θ1, and an angle formed by the first direction DR1 and the third direction DR3 is θ2.

As described above, θ1 and/or θ2 are established as acute angles for the purpose of providing an increased/maximum distance between a bit line contact160connecting the unit active region103and the bit line170, and a storage node contact180(i.e., a second contact plug ofFIG. 5) connecting the unit active region103and the capacitor. For example, θ1 and θ2 may be 45° and 45°, 30° and 60°, or 60° and 30°, respectively, but aspects of present inventive concepts are not limited thereto. More generally, the second and third directions may be orthogonal second and third directions, and the first direction may be non-orthogonal with respect to both of the second and third directions.

Next, a semiconductor device according to third embodiments of present inventive concepts will be described with reference toFIG. 5.

FIG. 5illustrates a semiconductor device according to third embodiments of present inventive concepts. Specifically,FIG. 5is a cross-sectional view taken along the line AA ofFIG. 1, illustrating an example of a semiconductor device including a capacitor.

Referring toFIG. 5, a semiconductor device3includes a substrate100, a transistor T, a bit line170and a capacitor C.

A unit active region103and an isolation region105are formed on a substrate100. The substrate100may be a bulk silicon or a silicon-on-insulator (SOI) substrate. Alternatively, the substrate100may be a silicon substrate or a substrate made of another material such as germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide. In the following description, a silicon substrate is exemplified. The isolation region105may be formed by a shallow trench isolation (STI) process. InFIG. 4, the unit active region103extending in the first direction DR1 may be defined by the isolation region105.

Two transistors T may be formed in one unit active region103. The two transistors T may include two gate electrodes130formed to cross the unit active region103, a first impurity region107aformed in the unit active region103between the two gate electrodes130, and second impurity regions107bformed between each of the gate electrodes130and the respective isolation region105. That is to say, the two transistors T may share the first impurity region107awhile not sharing the respective second impurity regions107b.

Each of the two transistors T may include a gate insulation layer120, a gate electrode130and a capping pattern140.

The gate insulation layer120may be formed along lateral surfaces and a bottom surface of a trench110formed in the substrate100. The gate insulation layer120may include, for example, silicon oxide or a high-k dielectric having a higher dielectric constant than silicon oxide. InFIG. 5, the gate insulation layer120may be entirely formed on the entirety of the lateral surfaces of the trench110, but aspects of present inventive concepts are not limited thereto. That is to say, the gate insulation layer120may be formed to be in contact with lower portions of the lateral surfaces of the trench110, and a capping pattern140(to be described later) may be formed to be in contact with upper portions of the lateral surfaces of the trench110.

The gate electrode130may be formed to fill a portion of the trench110, rather than completely filling the trench110. Stated in other words, the gate electrode130may be recessed. The gate electrode130may be formed using, for example, doped polysilicon, titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), titanium (Ti), tantalum (Ta), and/or tungsten (W), but the gate electrode is not limited thereto. The capping pattern140may be formed on the gate electrode130to fill the trench110. The capping pattern140may be made of an insulating material, and may include, for example, at least one of silicon oxide, silicon nitride, and/or silicon oxynitride. InFIG. 5, the capping pattern140fills a portion of trench110between the gate electrode130and dielectric layer150and between portions of the gate insulation layer120formed on opposite sidewalls of the trench110, but aspects of present inventive concepts are not limited thereto. For example, the capping pattern140may be formed in contact with the substrate100, that is, the first impurity region107aand the second impurity region107b.

In the semiconductor device according to third embodiments, the transistor T is a buried channel array transistor (BCAT), but aspects of present inventive concepts are not limited thereto. For example, the transistor T may have various structures including a planar transistor or a pillar-shaped vertical channel array transistor (VCAT) structure.

An interlayer dielectric layer150may be formed on the substrate100. The interlayer dielectric layer150may include, for example, at least one of silicon oxide, silicon nitride, and/or silicon oxynitride. The interlayer dielectric layer150may be formed of a single layer or multiple layers.

A first contact plug (bit line contact)160(electrically connected to the first impurity region107a) may be formed in the interlayer dielectric layer150. The first contact plug160may be made of a conductive material, and may include, for example, at least one of polysilicon, a metal silicide compound, and/or a metal, but aspects of present inventive concepts are not limited thereto. A bit line170(electrically connected through first contact plug160to the first impurity region107a) may be formed on the first contact plug160. The bit line170may be made of a conductive material, and may include, for example, at least one of polysilicon, a metal silicide compound, a conductive metal nitride, and/or a metal, but aspects of present inventive concepts are not limited thereto.

A second contact plug180may be formed through the interlayer dielectric layer150. The second contact plug180may be electrically connected to a second impurity region107b. The second contact plug180may be a storage node contact. The second contact plug180may be made of a conductive material, and may include, for example, at least one of polysilicon, a metal silicide compound, a conductive metal nitride, and/or a metal, but aspects of present inventive concepts are not limited thereto.

A capacitor C (electrically connected to the second impurity region107b) may be formed on the interlayer dielectric layer150. The capacitor C may be electrically connected to the second impurity region107bthrough the second contact plug180.

The capacitor C may include a lower electrode200, a capacitor dielectric layer210, a capacitor interface layer220, and an upper electrode230.

Referring toFIGS. 1 and 3, the lower electrode200may be a first conductor10, the capacitor dielectric layer210may be an oxide dielectric layer20, and the upper electrode230may be a second conductor30. In addition, the capacitor interface layer220may be formed as an interface layer25as shown inFIG. 1, or as a double layer including the interface layer25and the insertion layer23as shown inFIG. 3.

The lower electrode200may be formed to protrude from the substrate100and may be electrically connected to the second contact plug180. The lower electrode200protruding from the substrate100may extend lengthwise in one direction, that is, in a thickness direction of the substrate100.

In the semiconductor device according to third embodiments, the lower electrode200may have a cylindrical shape with inner and outer sidewalls. The cylindrical shape shown inFIG. 5is provided only for illustration, but aspects of present inventive concepts are not limited thereto. Stated in other words, the lower electrode200may have various shapes.

The capacitor dielectric layer210is formed on the lower electrode200. The capacitor dielectric layer210may be formed along the inner and outer sidewalls of the cylindrical lower electrode200.

The capacitor interface layer220is formed on the capacitor dielectric layer210. As described above with reference toFIGS. 1 and 3, the capacitor interface layer220may be formed of the interface layer25made of a metal oxide and may have formation enthalpy H2. If the capacitor interface layer220has a double layered structure including the interface layer25and the insertion layer23, as shown inFIG. 3, it may further include an Al2O3layer formed on the capacitor dielectric layer210.

The upper electrode230is formed on the capacitor interface layer220to be in contact with the capacitor interface layer220. The upper electrode230may include, for example, a metal nitride. The metal nitride included in the upper electrode230has formation enthalpy H1 higher than formation enthalpy H2 of the metal oxide forming the capacitor interface layer220.

InFIG. 5, the upper electrode230is formed on the interlayer dielectric layer150to have a plate shape, but aspects of present inventive concepts are not limited thereto. The upper electrode230may be formed along the inner and outer sidewalls of the cylindrical lower electrode200.

A semiconductor device according to fourth embodiments of present inventive concepts will now be described with reference toFIG. 6. Since this embodiment is substantially the same as the third embodiment, except for the shape of a lower electrode, elements/layers that are substantially the same as those of the previous embodiment are denoted by the same reference numerals, and repeated descriptions thereof may be briefly made or omitted.

FIG. 6illustrates the semiconductor device according to fourth embodiments of present inventive concepts. Specifically,FIG. 6is a cross-sectional view taken along the line AA ofFIG. 4, illustrating an exemplary semiconductor device including a capacitor.

Referring toFIG. 6, the semiconductor device4according to fourth embodiments may include a substrate100, a transistor T, a bit line170, and a capacitor C.

The lower electrode200is formed to protrude from substrate100and is electrically connected to a second contact plug180. The lower electrode200protruding from substrate100may extend lengthwise in one direction, that is, in a thickness direction of the substrate100.

In the semiconductor device according to fourth embodiments, the lower electrode200may be pillar shaped. The pillar shape shown inFIG. 6is provided only for illustration, but aspects of present inventive concepts are not limited thereto. That is to say, the lower electrode200may have various shapes.

The capacitor dielectric layer210and the capacitor interface layer220are formed along the outer sidewalls of the lower electrode200.

A semiconductor device according to fifth embodiments of present inventive concepts will now be described with reference toFIG. 7.FIG. 7illustrates embodiments of semiconductor devices1and2ofFIGS. 1 and 3used as components of a transistor.

FIG. 7illustrates a semiconductor device according to fifth embodiments of present inventive concepts.

Referring toFIG. 7, the semiconductor device5according to fifth embodiments may include a substrate300, a gate insulation layer310, a gate interface layer320, and a gate electrode330.

An active region303and an isolation region305are formed on/in a substrate300. The substrate300may be bulk silicon or a silicon-on-insulator (SOI) substrate. Alternatively, the substrate300may be a silicon substrate or a substrate made of another material such as germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, and/or gallium antimonide, but not limited thereto.

A channel region of the transistor formed on/in the active region303of the substrate300may be a first conductor10, the gate insulation layer310may be an oxide dielectric layer20, and the gate electrode330may be a second conductor30. In addition, the gate interface layer320may include interface layer25as shown inFIG. 1, or may be a double layer including interface layer25and insertion layer23ofFIG. 3.

The gate interface layer320is formed on the gate insulation layer310. As described above with reference toFIGS. 1 and 3, the gate interface layer320may be formed of metal oxide interface layer25. If the gate interface layer320has a double layer structure including interface layer25and insertion layer23, as shown inFIG. 3, it may further include an Al2O3layer formed on the capacitor dielectric layer310. If the transistor is a PMOS transistor, N-type impurity is doped into the active region303on opposite sides of electrode330, and if the transistor is an NMOS transistor, P-type impurity is doped into the active region303on opposite sides of electrode330.

In semiconductor devices according to fifth embodiments, the transistor is a planar transistor, but aspects of present inventive concepts are not limited thereto. The transistor may have various structures including a buried channel array transistor (BCAT), a vertical channel array transistor (VCAT), and so on.

InFIG. 7, the gate insulation layer310and the gate interface layer320are formed to be parallel with a top surface of the substrate100, but aspects of present inventive concepts are not limited thereto. For example, portions of gate insulation layer310and/or gate interface layer320may extend in a thickness direction of the substrate300.

Hereinafter, methods for fabricating semiconductor devices according to first embodiments of present inventive concepts will be described with reference toFIGS. 1,2A and8to10.

FIGS. 8 and 9illustrate intermediate process operations of a method for fabricating the semiconductor device according to first embodiments of present inventive concepts, andFIG. 10is a diagram illustrating a change in formation enthalpy generated in an interface layer in the course of forming a second conductor.

Referring toFIG. 8, a first conductor10and an oxide dielectric layer20are sequentially formed. Stated in other words, the oxide dielectric layer20is formed on the first conductor10.

The first conductor10may be a lower electrode of an information storage unit, and may include, for example, at least one selected from the group consisting of doped polysilicon, a conductive metal nitride (such as titanium nitride (TiN), tantalum nitride (TaN), and/or tungsten nitride (WN), a metal (such as ruthenium (Ru), iridium (Ir), titanium (Ti), and/or tantalum (Ta)), and/or a conductive metal oxide (such as iridium oxide). According to other embodiments, the first conductor10may be a channel region of a transistor, in a doped substrate, for example, a P-type substrate or an N-type substrate.

Referring toFIG. 9, a pre-interface layer25ais formed on the oxide dielectric layer20. The pre-interface layer25amay have a formation enthalpy H3.

The pre-interface layer25amay include, for example, one of titanium oxide (TiOx, where 0<x<2), aluminum oxide (AlOx, where 1<x<2), titanium aluminum oxide (TiyAl1=yOx, where 0<x<2), and/or manganese oxide (MnOxwhere 0<x<2). If the pre-interface layer25ais titanium aluminum oxide, a ratio of a metal element in the pre-interface layer25ato an aluminum element may be in a range of, for example, 0.001 to 0.5.

The pre-interface layer25amay be formed by, for example, atomic layer deposition (ALD) or chemical vapor deposition (CVD).

Referring toFIGS. 1 and 10, the second conductor30is formed on the pre-interface layer25ato be in contact with the pre-interface layer25a.

The second conductor30may be formed by, for example, atomic layer deposition (ALD) and/or chemical vapor deposition (CVD).

During formation of the second conductor30, the pre-interface layer25amay be converted into the interface layer25, so that the interface layer25is formed between the second conductor30and the oxide dielectric layer20.

The formation enthalpy H2 of the interface layer25is lower than the formation enthalpy H3 of the pre-interface layer25a. That is to say, during formation of the second conductor30, the pre-interface layer25amay be converted into the interface layer25having lower formation enthalpy than the pre-interface layer25a.

In addition, the formation enthalpy H2 of the interface layer25produced from the pre-interface layer25ais lower than the formation enthalpy H1 of the second conductor30. That is to say, the formation enthalpy H1 of the second conductor30is higher than the formation enthalpy H2 of the interface layer25.

During formation of the second conductor30, the pre-interface layer25amay provide some oxygen atoms contained therein to the second conductor30. At the same time, the pre-interface layer25amay prevent/reduce diffusion of oxygen atoms from the oxide dielectric layer20into the second conductor30. In addition, the pre-interface layer25amay prevent/reduce penetration/diffusion of nitrogen atoms (provided when the second conductor30is formed) into the oxide dielectric layer20.

Since some oxygen atoms contained in the pre-interface layer25amay be provided to the second conductor30, a number of oxygen atoms bonded for each metal atom in the pre-interface layer25ais greater than a number of oxygen atoms bonded for each metal atom in the interface layer25. That is to say, a reaction in which the pre-interface layer25ais converted into the interface layer25is a reduction, and oxidation enthalpy of the reaction in which the pre-interface layer25aturns into the interface layer25has a positive value.

Since oxygen atoms are provided from the pre-interface layer25ato the second conductor to then form the interface layer25, oxygen vacancies may be formed in the interface layer25. The oxygen vacancies in the interface layer25(a kind of defects), may serve as a path for the flow of current. Therefore, the interface layer25may be made of a metal oxide that is electrically conductive.

In methods for fabricating the semiconductor devices according to embodiments of present inventive concepts, the pre-interface layer25amay be formed of a compound satisfying stoichiometry, but aspects of present inventive concepts are not limited thereto. For example, the pre-interface layer25amay be made of an oxygen rich metal oxide having excessive oxygen atoms included in the metal oxide satisfying stoichiometry.

Methods for fabricating semiconductor devices according to second embodiments of present inventive concepts will now be described with reference toFIGS. 2A,3and11. Since these embodiments may be substantially the same as first embodiments, except that an insertion layer is further provided, layers/elements that are the same as those of the previous embodiments are denoted by the same reference numerals, and repeated descriptions thereof may be briefly made or omitted.

FIG. 11illustrates intermediate process steps in a method for fabricating semiconductor devices according to second embodiments of present inventive concepts.

Referring toFIG. 11, a first conductor10, an oxide dielectric layer20, an insertion layer23and a pre-interface layer25aare sequentially formed. The pre-interface layer25aand the insertion layer23are formed to directly contact each other.

The insertion layer23may include, for example, an oxygen-containing compound, such as an aluminum oxide (Al2O3). The insertion layer23may be formed by, for example, atomic layer deposition (ALD) and/or chemical vapor deposition (CVD).

Referring toFIGS. 3 and 10, a second conductor30is formed on the pre-interface layer25ato be in contact with the pre-interface layer25a.

During formation of the second conductor30, the pre-interface layer25ais converted into an interface layer25, so that the interface layer25is formed between the second conductor30and the insertion layer23.

During formation of the second conductor30, along with the pre-interface layer25a, the insertion layer23may reduce/prevent diffusion of oxygen atoms from the oxide dielectric layer20into the second conductor30. In addition, the pre-interface layer25aand the insertion layer23may reduce/prevent penetration/diffusion of nitrogen atoms (provided when the second conductor30is formed) into the oxide dielectric layer20.

FIG. 12is a block diagram illustrating an exemplary electronic system including semiconductor devices according to embodiments of present inventive concepts.

Referring toFIG. 12, the electronic system1100according to some embodiments of present inventive concepts may include a controller1110, an input/output (I/O) device1120, a memory device1130, an interface1140, and a bus1150. The controller1110, the I/O device1120, the memory device1130, and/or the interface1140may be connected to each other through the bus1150. The bus1150may provide path through which data moves.

The controller1110may include at least one of a microprocessor, a digital signal processor, a microcontroller, and logic devices capable of performing similar functions to those performed by these devices. The I/O device1120may include a keypad, a keyboard, a display device, and the like. The memory device1130may store data and/or instructions. The memory device1130may include semiconductor devices according to embodiments of present inventive concepts. For example, the memory device1130may include a DRAM. The interface1140may transmit/receive data to/from a communication network. The interface1140may be wired or wireless. For example, the interface1140may include an antenna and/or a wired/wireless transceiver.

The electronic system1100may be applied to a personal digital assistant (PDA), a portable computer, a web tablet, a wireless phone, a mobile phone, a digital music player, a memory card, or any type of electronic device capable of transmitting and/or receiving information in a wireless environment.

FIG. 13is a block diagram illustrating an example of a memory card including semiconductor devices according to embodiments of present inventive concepts.

Referring toFIG. 13, the memory1210including the semiconductor devices according to various embodiments of present inventive concepts may be employed in a memory card1200. The memory card1200may include a memory controller1220controlling data exchange between host1230and memory1210. A static random access memory (SRAM)1221may be used as an operating memory of a central processing unit1222. A host interface1223may include a protocol for exchanging data by allowing the host1230to be connected to the memory card1200. An error correction code (ECC)1224may detect an error from data read from the memory1210to then correct the detected error. A memory interface1225may interface with the memory1210. The central processing unit1222may perform overall control operations associated with the data exchange of the memory controller1220.

According to some embodiments, dielectric layers20,210, and/or310may be provided as dielectric oxide stacks. For example, dielectric oxide layer20,210, and/or310may include an aluminum oxide layer between first and second zirconium oxide layers.

While present inventive concepts have been particularly shown and described with reference to examples of embodiments thereof, it will be understood by those of ordinary skill in the art that various changes in form and details may be made therein without departing from the spirit and scope of present inventive concepts as defined by the following claims. It is therefore desired that present embodiments be considered in all respects as illustrative and not restrictive, reference being made to the appended claims rather than the foregoing description to indicate the scope of present inventive concepts.