Integrated circuit containing polysilicon gate transistors and fully silicidized metal gate transistors

A method for manufacturing an integrated circuit 10 having transistors 20, 30 of two threshold voltages where protected transistor stacks 270 have a gate protection layer 220 that are formed with the use of a single additional mask step. Also, an integrated circuit 10 having at least one polysilicon gate transistor 20 and at least one FUSI metal gate transistor 30.

BACKGROUND OF THE INVENTION

This invention relates to the fabrication and structure of integrated circuits containing both polysilicon gate transistors and fully silicidized (“FUSI”) metal gate transistors.

DETAILED DESCRIPTION OF THE INVENTION

Referring to the drawings,FIG. 1is a cross-sectional view of an integrated circuit10in accordance with the present invention. In the example application, CMOS transistors20,30are formed within an n-well or p-well region40of a semiconductor substrate50. It is within the scope of the invention for the remainder of the integrated circuit10to contain any combination of additional active or passive devices (not shown), such as additional MOSFET, BiCMOS and bipolar junction transistors, capacitors, optoelectronic devices, inductors, resistors, or diodes.

The semiconductor substrate50is a single-crystalline substrate that is doped to be n-type or p-type; however, it may be an amorphous silicon substrate or a substrate that is fabricated by forming an epitaxial silicon layer on a single-crystal substrate. The CMOS transistors20,30are electrically insulated from other active devices by shallow trench isolation structures60formed within the semiconductor substrate50; however, any conventional isolation structures may be used such as field oxide regions or implanted isolation regions.

In general, transistors20,30are comprised of a gate, source, and drain. More specifically, as shown inFIG. 1, the active portion of the transistors are comprised of sources/drains70, source/drain extensions80, and a gate that is comprised of a gate oxide90and gate electrode100/110. The CMOS transistors20,30may be either a p-channel MOS transistor (“PMOS”) or an n-channel MOS transistor (“NMOS”).

In the example application shown inFIG. 1, transistors20and30are PMOS transistors. Therefore they are formed within an n-well region40of the semiconductor substrate50. In addition, the deep sources and drains70and the source and drain extensions80have p-type dopants such as boron. The sources/drains70are usually heavily doped. However, the source/drain extensions80may be lightly doped (“LDD”), medium doped (“MDD”), or highly doped (“HDD”).

The gates of the PMOS transistors20,30are created from a gate oxide dielectric90plus a p-type doped polysilicon gate electrode100or a fully silicidized gate electrode110(“FUSI”). This use of both polysilicon gate electrodes100and fully silicidized gate electrodes110in the same integrated circuit accommodates circuit designs requiring transistors that have one of two threshold voltages on the same integrated circuit10.

One skilled in the art understands that the transistors20,30could also be NMOS transistors without departing from the scope of the invention. In this alternative embodiment each of the dopant types described throughout the remainder of this document would be reversed. For example, NMOS transistors20,30would be formed within a p-well region40of the semiconductor substrate50. In addition, the deep sources and drains70and the source and drain extensions80would have n-type dopants such as arsenic, phosphorous, antimony, or a combination of n-type dopants. The sources/drains70of NMOS transistors20,30would also be heavily doped. However, the source/drain extensions80could be LDD, MDD, or HDD. The gate of the NMOS transistors would be created from a gate oxide dielectric90plus a p-type doped polysilicon gate electrode100or a fully silicidized gate electrode110. For clarity, this opposite structure will not be discussed in detail since it is well know how to reverse the dopant types to create an NMOS transistor that is the counterpart to the PMOS transistor described herein.

Referring again toFIG. 1, an offset structure comprising extension sidewalls120and spacer sidewalls130are used during fabrication to enable the proper placement of the source/drain extensions80and the sources/drains70, respectively. More specifically, the source/drain extensions80are usually formed using the gate stack (90,100/110) and the extension sidewalls120as a mask. In addition, the sources/drains70are usually formed with the gate stack (90,100/110) and the spacer sidewalls130as a mask.

In this example application, the sources/drains70have a layer of silicide140that is formed within the top surface of the sources/drains70during the fabrication process (as described below). The silicide layer140formed within the top surface of the sources/drains70is preferably CoSi2; however, it is within the scope of the invention to fabricate the silicide140with other metals (such as nickel, platinum, titanium, tantalum, molybdenum, tungsten, or alloys of these metals). In addition, the silicide layer140formed on the top surface of the sources/drains70may be a self-aligned silicide (i.e. a “salicide”)

In accordance with the invention, the gate electrodes100/110are either partially or fully silicidized during the semiconductor fabrication process described below. More specifically, the polysilicon gate transistor20has a partially silicidized gate electrode100while the fully silicidized metal gate transistor30has a gate electrode110that is fully silicidized. A benefit of the silicide formed within the gate electrodes100/110and the top portion of the sources/drains70is the reduction of the contact resistance between the transistors20,30and the electrical contacts160/170. In the example application, the polycrystalline silicon (i.e. “polysilicon” or “poly”) gate electrode100is preferably CoSi2; however, it is within the scope of the invention to fabricate the silicide100with other metals, such as nickel, platinum, titanium, tantalum, molybdenum, tungsten, or alloys of these metals. In contrast, the FUSI gate electrode silicide110is preferably comprised of NiSi; however, other metals may be used, such as cobalt, platinum, titanium, tantalum, molybdenum, tungsten, or an alloy.

The integrated circuit10has a layer of dielectric insulation150that surrounds the CMOS transistors20,30. The composition of dielectric insulation150may be any suitable material such as SiO2or organosilicate glass (“OSG”). The dielectric material150electrically insulates the metal contacts160/170that electrically connect the CMOS transistors20,30that are shown inFIG. 1to other active or passive devices (not shown) that are located throughout the integrated circuit10. An optional dielectric liner (not shown) may be formed immediately below the dielectric insulation layer150. If used, the dielectric liner may be any suitable material such as silicon nitride.

In this example application, the contact cores160are comprised of W; however, any suitable material (such as Cu, Ti, Al, or an alloy) may be used. In addition, an optional liner material170such as Ti, TiN, or Ta (or any combination or layer stack thereof) may be used to reduce the contact resistance at the interface between the liner170and the silicidized regions of the poly gate electrode100and sources/drains140.

Subsequent fabrication will create the “back-end” portion180of the integrated circuit. The back-end180is generally comprised of one or more interconnect layers (and possibly via layers) containing metal interconnects190that properly route electrical signals and power though out the completed integrated circuit. The metal interconnects190may contain any suitable metal such as copper. In addition, the metal interconnects190are electrically insulated by dielectric material200, which may be any insulative material such as fluorinated silica glass (“FSG”) or OSG. Moreover, a thin dielectric layer210may be formed between the areas of dielectric material200of each interconnect layer. If used, the thin dielectric layer210may be comprised of any suitable material, such as SiC, SiCN, SiCO, or Si3N4. The very top portion of the back-end180(not shown) contains bond pads to connect the integrated circuit10to the device package plus an overcoat layer to seal the integrated circuit10.

Referring again to the drawings,FIGS. 2A–2Nare cross-sectional views of a partially fabricated integrated circuit10illustrating a process for forming example PMOS transistors20,30in accordance with the present invention. As noted above, those skilled in the art of semiconductor fabrication will easily understand how to modify this process to manufacture other types of transistors (such as NMOS transistors) in accordance with this invention.

FIG. 2Ais a cross-sectional view of the integrated circuit10where example PMOS transistors20,30will be formed. The integrated circuit10contains the shallow trench isolation structures60, the gate oxide layer95, and the gate electrode layer105, which are formed on the top surface of the n-well region40a semiconductor substrate50. In the example application, the semiconductor substrate50is silicon; however any suitable material such as silicon germanium, germanium, or gallium arsenide may be used. The shallow trench isolation structures60are formed using any suitable known process.

The gate oxide layer95and the gate electrode layer105are also formed using well-known manufacturing techniques. The first layer formed over the surface of the semiconductor substrate50is a gate oxide layer95. As an example, the gate oxide layer95is silicon dioxide that is formed with a thermal oxidation process. However, the gate oxide layer95may be any suitable material, such as nitrided silicon oxide, silicon nitride, or a high-k gate dielectric material, and it may be formed using any one of a variety of processes such as an oxidation process, thermal nitridation, plasma nitridation, physical vapor deposition (“PVD”), chemical vapor deposition (“CVD”), or atomic layer deposition (“ALD”).

A gate electrode layer105is then formed on the surface of the gate oxide layer95. The gate electrode layer105is comprised of polycrystalline silicon in the example application. However, it is within the scope of the invention to use other materials such as an amorphous silicon, a silicon alloy (e.g. SiGe), or other suitable materials. The gate electrode layer105may be formed using any suitable process technique such as CVD or PVD.

The next step in the example application is the formation of a gate protection layer225over the entire semiconductor wafer (i.e. over the gate electrode layer105). Preferably, the gate protection layer is formed using a CVD process; however, any suitable process may be used. In the best mode application, the protection layer is comprised of silicon nitride. However, it is within the scope of the invention to form a gate protection layer225comprising a stack of materials, such as SiO2, SixNy, SiC, other metal nitrides, or combinations and stacks thereof. For example, the gate protection layer225may be comprised of silicon oxide layers above and below a silicon nitride layer. If used, the silicon oxide layers may serve as buffers for better process control.

Preferably, the gate protection layer225is at least 50 Å thick in order to protect the FUSI gate electrode layer110from being silicidized or oxidized during the integrated FUSI process, as described below. However, the thickness of the protection layer225may vary between 50–500 Å thick. In the example application, the silicon nitride gate protection layer225is deposited by a rapid thermal CVD process using silane or dichlorosilane and ammonia precursors.

A photoresist layer230is deposited over the gate protection layer225in order to pattern the gate stacks for transistors20,30. Any suitable photoresist material may be used during this process. Alternatively, other materials may be used as the mask layer230, such as silicon dioxide.

As shown inFIG. 2B, the photoresist layer230is patterned and etched so that the photoresist layer230covers the gate protection layer225corresponding to the FUSI metal gate transistor30. Then, as shown inFIG. 2C, the portions of the gate protection layer225not covered by the patterned photoresist230are removed. Preferably, the exposed portions of the gate protection layer225are removed with a wet process that uses a H3PO4etchant in a wet etch chamber having a temperature between 100–160° C. (but preferably at 130° C.). If oxide layers are used in the gate protection layer225then a wet etch process involving HF should be employed to remove the oxide layers. The photoresist230is then removed, as shown inFIG. 2C, using any suitable ashing process.

A gate stack240having no gate protection layer220(“unprotected gate stack”) and a gate stack250having the gate protection layer220(“protected gate stack”) are now formed. The unprotected and protected gate stacks, shown inFIG. 2D, may be created through a variety of processes. For example, the gate stacks240,250may be created by forming a layer of standard photoresist230over the semiconductor substrate, patterning the photoresist, and then using the patterned photoresist to properly etch the gate oxide layer95, the gate electrode layer105, and the protection layer225. The gate stacks240,250may be etched using any suitable etch process, such as an anisotropic etch using plasma or reactive ions. After the pattern and etch process, an unprotected gate stack240having a gate oxide layer90and a gate electrode layer100will be formed from the gate oxide layer95, the gate electrode layer105respectively. In addition, a protected gate stack250having a gate oxide layer90, a gate electrode layer110, and gate protection layer220will be formed from the gate oxide layer95, the gate electrode layer105, and the gate protection layer225respectively.

The next step in the fabrication of the PMOS transistors20,30is the formation of the extension regions80using extension sidewalls120as a template. As shown inFIG. 2E, extension sidewalls120are formed on the outer surface of the gate stacks using any suitable processes and materials. The extension sidewalls120may be formed from a single material or may be formed from more than one layer of materials. For example, the extension sidewalls120may be comprised of an oxide, oxi-nitride, silicon dioxide, nitride, or any other dielectric material or layered stack of dielectric materials. The layers for the extension sidewalls120may be formed with any suitable process, such as thermal oxidation, or deposition by ALD, CVD, or PVD. Preferably, at least one layer of the extension sidewall120is comprised of a silicon nitride that is formed with a CVD process that uses a bis-t-butylaminosilane (“BTBAS”) precursor. Forming the silicon nitride layer with that precursor will help guard against the etching of the extension sidewalls120during the process of removing the gate protection layer220later in the fabrication process (due to the low etch rate of BTBAS in the etching solution that is used for the protection layer removal). Usually, an anisotropic etch process is used to shape the extension sidewall layer or layers into the extension sidewalls120.

The extension sidewalls120are now used as a template to direct the proper placement of the extension regions80, as shown inFIG. 2E. The extension regions80are formed near the top surface of the semiconductor substrate50using any standard process. For example, the extension regions80may be formed by low-energy ion implantation, gas phase diffusion, or solid phase diffusion. The dopants used to create the extension regions80for the PMOS transistors20,30are p-type, such as boron. However, other dopants or combinations of dopants may be used.

At some point after the implantation of the extension regions80, the extension regions80are activated by an anneal process (performed now or later) to form source/drain extensions80(as shown inFIG. 2E). This anneal step may be performed with any suitable process such as rapid thermal anneal (“RTA”).

Referring toFIG. 2F, spacer sidewalls130are now formed proximate to the extension sidewalls120. The spacer sidewalls130may be formed using any standard process and materials. In addition the spacer sidewalls130may be formed from a single material or from two or more layers of materials. For example, the spacer sidewalls130may be comprised of a cap oxide and a BTBAS nitride layer that are formed with a CVD process and subsequently anisotropically etched (preferably using standard anisotropic plasma etch processes). However, it is within the scope of the invention to use more layers (i.e. an L-shaped cap oxide layer, an L-shaped nitride layer, and a final sidewall oxide layer) or less layers (i.e. just a silicon oxide layer or a silicon nitride layer) to create the spacer sidewalls150. It is to be noted that the integrated circuit10is usually subjected to a standard post-etch cleaning process after the formation of the spacer sidewalls130.

Now the source/drain sidewalls130are used as a template for the implantation of the source/drain regions75. The source/drain regions75may be formed through any one of a variety of processes, such as deep ion implantation or deep diffusion. The dopants used to create the source/drain regions75for the PMOS transistors20,30are typically boron; however, other dopants or combinations for dopants may be used.

In the example application, the source/drain regions75are activated by a second anneal step to create sources/drains70. (However, the extension region anneal and the source/drain region anneal may be combined and performed at this point in the fabrication process.) This anneal step acts to repair the damage to the semiconductor wafer and to activate the dopants. The activation anneal may be performed by any technique such as RTA, flash lamp annealing (“FLA”), or laser annealing. This anneal step often causes lateral and vertical migration of dopants in the source/drain extensions80and the sources/drains70, as shown inFIG. 2G.

At this point in the fabrication process there are two transistor structures formed within the semiconductor substrate50. Namely, an unprotected transistor stack260having the unprotected gate stack240, and a protected transistor stack270having the protected gate stack250.

As shown inFIG. 2H, a first layer of silicidation material280is now formed over the semiconductor substrate50. The silicidation material280is preferably comprised of cobalt; however, other suitable materials such as nickel, platinum, titanium, tantalum, molybdenum, tungsten, or alloys may be used. In the example application, the cobalt first silicidation layer280is between 40–75 Å thick and is formed using a PVD process. Various other thicknesses could be used if the first layer of silicidation material280is one of the alternative metals, such as nickel.

An optional cap layer290may also be formed over the first layer of silicidation metal280. If used, the cap layer290acts as a passivation layer that prevents the diffusion of oxygen from ambient into the first silicidation metal layer280. The cap layer may be any suitable material, such as TiN. In the example application, the cap layer290is between 150–300 Å thick.

The integrated circuit10is now annealed with any suitable process, such as RTA. In the example application, the RTA is performed for 10–60 seconds at a temperature between 400–600° C.

This substrate silicide anneal process will cause a silicide140(i.e. a Co-rich silicide or Co mono-silicide) to form at the top surface of the gate electrode layer100of the unprotected transistor stack260and also at the top surface of the sources/drains70of both the protected transistor stacks270and the unprotected transistor stacks260, as shown inFIG. 2I.

It is to be noted that the silicidation metal layer140will only react with the active substrate (i.e. the exposed Si); namely, the sources/drains70and the exposed polysilicon gate electrode layer100. Therefore, the silicide140formed by the annealing process is a salicide. It is also important to note that the gate electrode110was not modified by the anneal process because the gate electrode110was protected by the gate protection layer220and the extension sidewalls120.

The next step is the removal of the unreacted portions of the first layer of silicidation metal280, as shown inFIG. 2J. The first layer of silicidation metal280(and the capping layer290, if used) is removed with any suitable process such as a wet etch process (e.g. using a fluid mixture of sulfuric acid, hydrogen peroxide, and water).

It is within the scope of the invention to perform a second RTA at this point in the manufacturing process in order to further react the silicide140with the sources/drains70and the gate electrode layer100. In the example application, a second silicide anneal is performed for 10–60 seconds at a temperature between 650–800° C. If the initial anneal process did not complete the silicidation process, this second anneal will ensure the formation of a mono-silicide CoSi, which lowers the sheet resistance of the silicide140. It should be noted that the preferred temperature and time period for the second RTA process should be based on the silicide material used and the ability to form the silicidized sources/drains70and gate electrode100to the desired depth.

The gate protection layer220is now removed, as shown inFIG. 2K. The gate protection layer220may be removed by any suitable process such as a wet etch using a solution containing phosphoric acid at elevated temperatures in the range of 100–160° C. Alternatively, the gate protection layer can be removed by using a dilute HF solution at room temperature (i.e. 23° C.). With the gate protection layer220removed, the gate electrode110is now exposed and therefore available for gate electrode silicidation.

As shown inFIG. 2L, a second layer of silicidation metal300is now formed over the top of the semiconductor substrate50. The second layer of silicidation metal300is preferably comprised of nickel; however, other suitable materials such as cobalt, platinum, titanium, tantalum, molybdenum, tungsten, or an alloy may be used. Preferably, the second layer of silicidation metal300is designed to fully silicidize the polysilicon gate electrode layer110. As it takes approximately 10 Å of nickel to fully silicidize approximately 18 Å of polysilicon, the thickness of the silicidation metal300should be at least 56% of the thickness of the polysilicon gate electrode110. To be comfortable however, it is suggested that the thickness of the silicidation metal300should be at least 60% of the thickness of the polysilicon gate electrode110. Thus, where the thickness of the polysilicon gate electrode110ranges from about 600 Å to about 1500 Å in the example application, the thickness of the nickel second layer of silicidation metal300should range from approximately 400–2000 Å. However, various other thicknesses would be proper if the second layer of silicidation material300is one of the alternative metal materials.

The integrated circuit10is now annealed with any suitable process, such as RTA. In the example application, the gate silicide anneal is performed for 10–60 seconds at a temperature between 200–500° C. Once the first RTA of the gate silicide anneal is complete, the gate electrode110should be almost fully silicidized to a metal-rich phase, as shown inFIG. 2M. It is to be noted that the second layer of silicidation metal300will not react with the silicidized sources/drains70and the silicidized surface of the gate electrode layer100because they are protected from further silicidation by their previously formed silicide layer140.

The next step is the removal of the unreacted portions of the second layer of silicidation metal300, as shown inFIG. 2N. The second layer of silicidation metal300(and the capping layer290, if used) is removed with any suitable process such as a selective wet etch process (i.e. using a fluid mixture of sulfuric acid, hydrogen peroxide, and water).

In the example application a second RTA is performed at this point in the manufacturing process in order to fully react the gate silicide110, as shown inFIG. 2N. Preferably, the second RTA is performed for 30–120 seconds at a temperature between 400–600° C. This second anneal will ensure the formation of a fully silicidized gate electrode layer110having a lowered sheet resistance.

It is to be noted that the example fabrication process described above creates transistors having two different threshold voltages on the same integrated circuit10. Specifically the poly gate transistors20will have one threshold voltage (that is determined by the doping levels of the polysilicon gate electrode100during the formation of the sources/drains and the source/drain extensions) and the FUSI gate transistors30will have a second (different) threshold voltage (that is determined by the work-function of the FUSI gate electrode). (The work-function of the FUSI gate transistors30will also be affected by the doping levels of the gate electrode110during the deposition of the sources/drains and the source/drain extensions.)

It is also to be noted that only one additional mask step (FIGS. 2A–2C) was used to create transistors with and without the gate protection layer220for both electrical parities (e.g. for NMOS and PMOS). It is within the scope of the invention to form multiple poly gate transistors20and multiple FUSI gate transistors30in the n-well regions, the p-well regions, or both the n-well and the p-well regions of the integrated circuit10.

Other process flows for creating poly gate transistors20and FUSI gate transistors30in a single integrated circuit10are within the scope of the invention. For example, instead of forming the poly gate transistors20first and the FUSI gate transistors second; these transistors may be formed in the opposite order. A portion of this alternative process flow is shown inFIGS. 3A–3I. With this alternative manufacturing process, protected transistor stacks270and unprotected transistor stacks260may be formed using the process described above and shown inFIGS. 2A–2G. Next, as shown inFIG. 3A, a silicide blocking layer is formed over the active substrate (i.e. the exposed Si). More specifically, an oxide layer310is formed within the top surface of the gate electrode layer100of the unprotected transistor stack260and also within the top surface of the sources/drains70of both the protected transistor stacks270and the unprotected transistor stacks260. Any suitable technique may be used to form the oxide layers310. For instance, a low temperature oxidation process (e.g. a plasma oxidation process) may be performed within a low temperature range (i.e. 200° C. to 600° C.) to grow an oxide layer having a thickness between 50–100 Å. This process has the benefit of not changing the doping profile of the sources/drains70and the source/drain extensions80.

After the oxide layer310has been formed, the gate protection layer220is removed from the protected gate stack270, as shown inFIG. 3B. The gate protection layer220may be removed by any suitable process such as a wet etch using a solution containing phosphoric acid at elevated temperatures in the range of 100–160° C. With the gate protection layer220removed, the gate electrode110is now exposed and therefore available for gate electrode silicidation. The oxide layer310is not affected by the wet etch process to remove the gate protection layer220. Therefore, transistor stack260is still covered by the oxide layer310.

As shown inFIG. 3C, a first layer of silicidation metal280is now formed over the top of the semiconductor substrate50. The first layer of silicidation metal280is preferably comprised of nickel; however, other suitable materials such as cobalt, platinum, titanium, tantalum, molybdenum, tungsten, or an alloy may be used. Preferably, the first layer of silicidation metal280is designed to fully silicidize the polysilicon gate electrode layer110. As it takes approximately 10 Å of nickel to fully silicidize approximately 18 Å of polysilicon, the thickness of the silicidation metal280should be at least 56% of the thickness of the polysilicon gate electrode110. To be comfortable however, it is suggested that the thickness of the silicidation metal280should be at least 60% of the thickness of the polysilicon gate electrode110. Thus, where the thickness of the polysilicon gate electrode110ranges from about 600–1500 Å, in the example application, the thickness of the nickel first layer of silicidation metal280should range from approximately 400–2000 Å. However, various other thicknesses would be proper if the first layer of silicidation material280is one of the alternative metals.

An optional cap layer290may also be used over the first layer of silicidation metal280. If used, the cap layer290acts as a passivation layer that prevents the diffusion of oxygen from the ambient into the first layer of silicidation metal280. The cap layer may be any suitable material, such as TiN or Ti. In the example application, the cap layer290is between 150–300 Å thick.

The integrated circuit10is now annealed with any suitable process, such as RTA. In the example application, the gate silicide anneal is performed for 1–60 seconds at a temperature between 200–500° C. Once the first RTA of the gate silicide anneal is complete, the gate electrode110should be almost fully silicidized to a metal-rich phase, as shown inFIG. 3D. It is to be noted that the first layer of silicidation metal280will not react with the oxidized sources/drains70and the oxidized surface of the gate electrode layer100because they are protected from silicidation by the previously formed oxide layer310.

The next step is the removal of the unreacted portions of the first layer of silicidation metal280, as shown inFIG. 3E. The first layer of silicidation metal280(and the capping layer290, if used) is removed with any suitable process such as a selective wet etch process (i.e. using a fluid mixture of sulfuric acid, hydrogen peroxide, and water).

In the example application a second RTA is now performed in order to fully react the gate silicide110, as shown inFIG. 3E. Preferably, the second RTA is performed for 30–120 seconds at a temperature between 400–600° C. This second anneal will ensure the formation of a fully silicidized gate electrode layer110having a lowered sheet resistance.

Now, the oxide layer310is also removed, as shown inFIG. 3F, using any suitable process. For example, the oxide layer may be removed with a dilute HF solution at room temperature. As shown inFIG. 3F, recesses will be formed at the locations where the oxide layers310were removed. Therefore, it is within the scope of this invention to form a silicide blocking layer310that won't consume active silicon (thereby creating the recesses when etched) by using other techniques and materials, such as a high temperature oxidation technique (e.g. a rapid thermal oxidation technique). Alternatively, a selective thin epitaxial silicon layer may be deposited just prior to the formation of the oxide layer310to provide a sacrificial silicon layer to compensate for the silicon consumed by forming the oxide layer310with a low temperature oxidation process.

As shown inFIG. 3G, a second layer of silicidation material300is now formed over the semiconductor substrate50. The silicidation material300is preferably comprised of nickel; however, other suitable materials such as cobalt, platinum, titanium, tantalum, molybdenum, tungsten, or alloys may be used. In the example application, the nickel second silicidation metal layer300is between 50–120 Å thick and is formed using a PVD process. Various other thicknesses could be used if the second layer of silicidation material300is one of the alternative metals, such as cobalt.

An optional cap layer290may also be formed over the second layer of silicidation metal300. If used, the cap layer290acts as a passivation layer that prevents the diffusion of oxygen from ambient into the second silicidation metal layer300. The cap layer may be any suitable material, such as TiN. In the example application, the cap layer290is between 150–300 Å thick.

The integrated circuit10is now annealed with any suitable process, such as RTA. In the example application, the RTA is performed for 1–60 seconds at a temperature between 200–500° C.

This substrate silicide anneal process will cause a silicide140(i.e. a Ni-rich silicide or Ni mono-silicide) to form at the top surface of the gate electrode layer100of the unprotected transistor stack260and also at the top surface of the sources/drains70of both the protected transistor stacks270and the unprotected transistor stacks260, as shown inFIG. 3H.

It is to be noted that the silicidation metal layer140will only react with the active substrate (i.e. the exposed Si); namely, the sources/drains70and the exposed polysilicon gate electrode layer100. Therefore, the silicide140formed by the annealing process is a salicide. It is also important to note that the gate electrode110was not modified by the anneal process because the gate electrode110was already fully silicidized.

The next step is the removal of the unreacted portions of the second layer of silicidation metal300, as shown inFIG. 3I. The second layer of silicidation metal300(and the capping layer290, if used) is removed with any suitable process such as a wet etch process (e.g. using a fluid mixture of sulfuric acid, hydrogen peroxide, and water).

It is within the scope of the invention to perform a second RTA at this point in the manufacturing process in order to further react the silicide140with the sources/drains70and the gate electrode layer100. In the example application, a second silicide anneal is performed for 10–60 seconds at a temperature between 300–600° C. If the initial anneal process did not complete the silicidation process, this second anneal will ensure the formation of a mono-silicide NiSi, which lowers the sheet resistance of the silicide140. It should be noted that the preferred temperature and time period for the second RTA process should be based on the silicide material used and the ability to form the silicidized sources/drains70and gate electrode100to the desired depth.

After the formation of FUSI gate electrode110, as well as the silicide layers within the source/drain70and the gate electrode layer100, using any process flow described above, the fabrication of the integrated circuit10now continues, using standard process steps, until the integrated circuit is complete. Generally, the next step is the formation of the dielectric insulator layer150(seeFIG. 1) using plasma-enhanced chemical vapor deposition (“PECVD”) or another suitable process. The dielectric insulator150may be comprised of any suitable material such as SiO2or OSG.

The contacts160/170are formed by etching the dielectric insulator layer150to expose the desired gate, source and/or drain. The etched spaces are usually filled with a contact liner170to improve the electrical interface between the silicide and the contact core160. Then contact cores160are formed within the liner170; creating the electrical interconnections between various electrical components located within the semiconductor substrate50.

The fabrication of the final integrated circuit continues with the fabrication of the back-end structure using any suitable well-known processes. Once the fabrication process is complete, the integrated circuit10will be tested and then cut from the semiconductor wafer and packaged.

Various additional modifications to the invention as described above are within the scope of the claimed invention. For example, instead of forming the protected and unprotected transistor stacks as described above in relation toFIGS. 2A–2G, the protected and unprotected transistor stacks may be formed with any suitable process that uses only one additional mask step, such as the process shown inFIGS. 4A–4I. Analogous reference numbers to those used in prior drawingFIGS. 1–3Iare used inFIGS. 4A–4I.

FIG. 4Ais a cross sectional view of the integrated circuit10where example PMOS transistors20,30will be formed. The integrated circuit10contains the shallow trench isolation structures60, the gate oxide layer95, and the gate electrode layer105, which are formed on the top surface of the n-well region40a semiconductor substrate50. In the example application, the semiconductor substrate50is silicon; however any suitable material such as silicon germanium, germanium, or gallium arsenide may be used. The shallow trench isolation structures60are formed using any suitable known process.

The gate oxide layer95and the gate electrode layer105are also formed using well-known manufacturing techniques. The first layer formed over the surface of the semiconductor substrate50is a gate oxide layer95. As an example, the gate oxide layer95is silicon dioxide that is formed with a thermal oxidation process. However, the gate oxide layer95may be any suitable material, such as nitrided silicon oxide, silicon nitride, or a high-k gate dielectric material, and it may be formed using any one of a variety of processes such as an oxidation process, thermal nitridation, plasma nitridation, PVD, CVD, or ALD.

A gate electrode layer105is then formed on the surface of the gate oxide layer95. The gate electrode layer105is comprised of polycrystalline silicon in the example application. However, it is within the scope of the invention to use other materials such as an amorphous silicon, a silicon alloy (e.g. SiGe), or other suitable materials. The gate electrode layer105may be formed using any suitable process technique such as CVD or PVD.

The next step in the example application is the formation of a gate protection layer225over the entire semiconductor wafer (i.e. over the gate electrode layer105). Preferably, the gate protection layer is formed using a CVD process; however, any suitable process may be used. Preferably, the protection layer is comprised of silicon nitride. However, it is within the scope of the invention to form a gate protection layer225comprising a stack of materials, such as SiO2, SixNy, SiC, other metal nitrides, or combinations and stacks thereof. For example, the gate protection layer225may be comprised of silicon oxide layers above and below a silicon nitride layer. If used, the silicon oxide layers may serve as buffers for better process control.

Preferably, the gate protection layer225is at least 50 Å thick in order to protect the FUSI gate electrode layer110from being silicidized or oxidized during the integrated FUSI process, as described below. However, the thickness of the protection layer225may vary between 50–500 Å thick. In the example application, the silicon nitride gate protection layer225is deposited by a rapid thermal CVD process using silane or dichlorosilane and ammonia precursors.

The gate stack240for the unprotected transistor stack260and the gate stack250for the protected transistor stack270are now formed. The unprotected and protected gate stacks, shown inFIG. 4B, may be created through a variety of processes. For example, the gate stacks240,250may be created by forming a layer of standard photoresist230over the semiconductor substrate, patterning the photoresist, and then using the patterned photoresist to properly etch the gate oxide layer95, the gate electrode layer105, and the protection layer225. The gate stacks240,250may be etched using a suitable etch process, such as an anisotropic etch using plasma or reactive ions. After the pattern and etch process, a protected gate stack250having a gate oxide layer90, a gate electrode layer110, and gate protection layer220will be formed from the gate oxide layer95, the gate electrode layer105, and the gate protection layer225respectively. Similarly, an unprotected gate stack240having a gate oxide layer90, a gate electrode layer100, and gate protection layer220will be formed from the gate oxide layer95, the gate electrode layer105, and the gate protection layer225respectively.

The next step in the fabrication of the PMOS transistors20,30is the formation of the extension regions80using extension sidewalls120as a template. As shown inFIG. 4C, extension sidewalls120are formed on the outer surface of the gate stacks using any suitable processes and materials. The extension sidewalls120may be formed from a single material or may be formed from more than one layer of materials. For example, the extension sidewalls120may be comprised of an oxide, oxi-nitride, silicon dioxide, nitride, or any other dielectric material or layered stack of dielectric materials. The layers for the extension sidewalls120may be formed with any suitable process, such as thermal oxidation, or deposition by ALD, CVD, or PVD. Preferably, at least one layer of the extension sidewall120is comprised of a silicon nitride that is formed with a CVD process that uses a BTBAS precursor. Forming the silicon nitride layer with that precursor will help guard against the etching of the extension sidewalls120during the process of removing the gate protection layer220later in the fabrication process (due to the low etch rate of BTBAS in the etching solution that is used for the protection layer removal). Usually, an anisotropic etch process is used to shape the extension sidewall layer or layers into the extension sidewalls120.

The extension sidewalls120are now used as a template to direct the proper placement of the extension regions80, as shown inFIG. 4C. The extension regions80are formed near the top surface of the semiconductor substrate50using any standard process. For example, the extension regions80may be formed by low-energy ion implantation, gas phase diffusion, or solid phase diffusion. The dopants used to create the extension regions80for the PMOS transistors20,30are p-type, such as boron. However, other dopants or combinations of dopants may be used.

At some point after the implantation of the extension regions80, the extension regions80are activated by an anneal process (performed now or later) to form source/drain extensions80(as shown inFIG. 4C). This anneal step may be performed with any suitable process such as RTA.

Referring toFIG. 4D, spacer sidewalls130are now formed proximate to the extension sidewalls120. The spacer sidewalls130may be formed using any standard process and materials. In addition the spacer sidewalls130may be formed from a single material or from two or more layers of materials. For example, the spacer sidewalls130may be comprised of a cap oxide and a BTBAS nitride layer that are formed with a CVD process and subsequently anisotropically etched (preferably using standard anisotropic plasma etch processes). However, it is within the scope of the invention to use more layers (i.e. an L-shaped cap oxide layer, an L-shaped nitride layer, and a final sidewall oxide layer) or less layers (i.e. just a silicon oxide layer or a silicon nitride layer) to create the spacer sidewalls150. It is to be noted that the integrated circuit10is usually subjected to a standard post-etch cleaning process after the formation of the spacer sidewalls130.

Now the source/drain sidewalls130are used as a template for the implantation of the source/drain regions75. The source/drain regions75may be formed through any one of a variety of processes, such as deep ion implantation or deep diffusion. The dopants used to create the source/drain regions75for the PMOS transistors20,30are typically boron; however, other dopants or combinations for dopants may be used.

In the example application, the source/drain regions75are activated by a second anneal step to create sources/drains70. (However, the extension region anneal and the source/drain region anneal may be combined and performed at this point in the fabrication process.) This anneal step acts to repair the damage to the semiconductor wafer and to activate the dopants. The activation anneal may be performed by any technique such as RTA, FLA, or laser annealing. This anneal step often causes lateral and vertical migration of dopants in the source/drain extensions80and the sources/drains70, as shown inFIG. 4E.

As shown inFIG. 4F, a photoresist layer230is now formed over the semiconductor substrate50. Any suitable photoresist material may be used during this process. Alternatively, other materials may be used as the mask layer230, such as silicon dioxide. This single mask step will facilitate the formation of all protected transistor stacks270and unprotected transistor stacks260throughout the integrated circuit10.

As shown inFIG. 4G, the photoresist layer230is patterned and etched so that the photoresist layer230covers the PMOS FUSI metal gate transistor30. Alternatively, the photoresist layer could be patterned to cover just the gate protection layer225overlying the FUSI metal gate transistor30(i.e.230a,as indicated by the dashed lines). Then, as shown inFIG. 4H, the portions of the gate protection layer225not covered by the patterned photoresist230or230a(specifically, the gate protection layers225belonging to the unprotected transistor stacks260) are removed. Preferably, the exposed portions of the gate protection layer225are removed with a wet process that uses a H3PO4etchant in a wet etch chamber having a temperature between 100–160° C. (and preferably around 130° C.). If oxide layers are used in the gate protection layer225then a wet etch process involving HF should be employed to remove the oxide layers. Next, the photoresist230is removed, as shown inFIG. 4I, using any suitable ashing process.

At this point in the fabrication process there are two transistor structures formed within the semiconductor substrate50. Namely, an unprotected transistor stack260having the unprotected gate stack240, and a protected transistor stack270having the protected gate stack250. The fabrication of the integrated circuit now continues with the process step corresponding toFIG. 2Hor the process step corresponding toFIG. 3A.

Various additional modifications to the invention as described above are within the scope of the claimed invention. As an example, interfacial layers may be formed between any of the layers shown. In addition, an anneal process may be performed after any step in the above-described fabrication process. When used, the anneal process can improve the microstructure of materials and thereby improve the quality of the semiconductor structure. Conversely, any anneal process used in the example application may be removed. For example, if a FUSI gate electrode can be formed with one RTA process (FIGS. 2M and 3D) then the second RTA step can be deleted from the process flow in order to save manufacturing costs.