Diodes for package substrate electrostatic discharge (ESD) protection

Embodiments may relate to a package substrate that is to couple with the die. The package substrate may include a signal line that is communicatively coupled with the die. The package substrate may further include a conductive line. The package substrate may further include a diode communicatively coupled with the signal line and the conductive line. Other embodiments may be described or claimed.

BACKGROUND

One concern for microelectronic packages is electrostatic discharge (ESD). ESD may refer to a sudden onset of charge transfer (i.e., electron flow) between two objects with different electric potentials. These static voltages may cause partial to full breakdown of an integrated circuit (IC) of the microelectronic package.

DETAILED DESCRIPTION

For the purposes of the present disclosure, the phrase “A or B” means (A), (B), or (A and B). For the purposes of the present disclosure, the phrase “A, B, or C” means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B and C).

In various embodiments, the phrase “a first feature [[formed/deposited/disposed/etc.]] on a second feature,” may mean that the first feature is formed/deposited/disposed/etc. over the feature layer, and at least a part of the first feature may be in direct contact (e.g., direct physical or electrical contact) or indirect contact (e.g., having one or more other features between the first feature and the second feature) with at least a part of the second feature.

Embodiments herein may be described with respect to various Figures. Unless explicitly stated, the dimensions of the Figures are intended to be simplified illustrative examples, rather than depictions of relative dimensions. For example, various lengths/widths/heights of elements in the Figures may not be drawn to scale unless indicated otherwise. Additionally, some schematic illustrations of example structures of various devices and assemblies described herein may be shown with precise right angles and straight lines, but it is to be understood that such schematic illustrations may not reflect real-life process limitations which may cause the features to not look so “ideal” when any of the structures described herein are examined, e.g., using scanning electron microscopy (SEM) images or transmission electron microscope (TEM) images. In such images of real structures, possible processing defects could also be visible, e.g., not-perfectly straight edges of materials, tapered vias or other openings, inadvertent rounding of corners or variations in thicknesses of different material layers, occasional screw, edge, or combination dislocations within the crystalline region, and/or occasional dislocation defects of single atoms or clusters of atoms. There may be other defects not listed here but that are common within the field of device fabrication.

It will be understood that the term “microelectronic package” may, in other situations, be referred to as a “semiconductor package.” However, the term “microelectronic package” will be used herein for the sake of consistency.

As noted, ESD may be undesirable in a microelectronic package because it may cause partial to full breakdown of ICs of the microelectronic package, even when the ICs are only exposed to the static voltages for a relatively short period of time. Hence, ESD protection may be viewed as a reliability concern and an important element of any electronic system, especially when IC costs are considered.

Generally, innovation into ESD protection may be desired to keep up with the ongoing trend of shrinking IC sizes and the increased number of high-speed signal lines or higher operating frequencies. This trend may result in a desire for minimizing the IC area that is dedicated to ESD protection features on-die (such as on-die diodes). It may therefore be desirable to offload some of the ESD protection features from the die and integrate them in the package as an embedded package solution in next-generation packaging technologies.

More specifically, in legacy packaging solutions, ESD protection of IC chips may have been achieved by using on-die diodes that are fabricated between the exposed locations on the chips (e.g., first level interconnect (FLI) bumps) and ground (e.g., the bulk silicon). The diodes in legacy packaging solutions may have been designed such that their forward bias voltage is just below the threshold value at which the functional devices in the chip (e.g., transistors) start getting damaged. When an external voltage greater than, or equal to, this value is applied at the exposed port, the diode may be forward biased, shunting the high-voltage input to ground and shielding the devices. When a normal voltage (below the threshold value) is applied at the input port, the diode may act as a capacitor between this port and ground, and the signal may be transmitted to the devices for processing.

While this approach may have been used in previous microelectronic packages, it may be undesirable in current or upcoming microelectronic packages for a few reasons. The first reason may be that the ESD diodes may consume a large portion of on-chip real-estate, which may become more pronounced as the devices on those chips are shrunk down in size. Secondly, the diodes may induce capacitive loading and consume leakage power during normal device operation, which may be undesirable at a chip-level.

By contrast, embodiments herein relate to the creation of semiconductor diodes in the package substrate of a microelectronic package for ESD protection. The diodes may be situation between, for example, ground and signal lines of the package substrate or between power and signal lines of the package substrate, and provide protection from an ESD event.

The package-level semiconductor diodes may be Schottky or pn-junction diodes that use materials compatible with panel-level organic package substrate processing. For example, the diodes may be based on oxide-based or organic-based semiconductor materials, or a combination thereof. Example oxide-based semiconductor materials may include gallium oxide (Ga2O3), indium oxide (In2O3), indium gallium zinc oxide (IGZO), or zinc oxide (ZnO2). Example organic-based semiconductor materials may include copper phthalocyanine (CuPc), titanium phthalocyanine (TiPc), copper hexadecafluorophthalocyanine (F16CuPc), titanium hexadecafluorophthalocyanine (F16TiPc), poly(3-hexylthiophene) (P3HT), Hexaazatriphenylenehexacarbonitrile (HAT-CN), 2,3,5,6-Tetrafluoro-7,7,8,8-tetracyanoquinodimethane (F4TCNQ), or rubrene. However, it will be understood that this list of materials is not intended as an exhaustive list and other oxide-based or organic-based semiconductor materials may be present in other embodiments.

The above-listed semiconductor materials may exhibit a strong preference for doping (i.e., are either easily n-doped or p-doped, but not the other way around), so may lend themselves towards use as a Schottky diode. As used herein, a Schottky diode may refer to a semiconductor diode formed by the junction of a semiconductor material (e.g., the above-listed organic-based or oxide-based semiconductor materials) with a metal. Because many of the above-mentioned semiconductor materials, particularly the oxide-based semiconductor materials, have a significantly wider band-gap (i.e., energy level required for the semiconductor material to become conductive) than silicon, creating Schottky diodes with a barrier height (i.e., the potential energy barrier for electronics formed at a metal-semiconductor junction) that is identical to the built-in voltage of a pn-junction diode may be possible.

Schottky diodes may be referred to herein as “n-doped” or “p-doped” (or, similarly, n-type or p-type). As used herein, an n-doped Schottky diode may refer to a Schottky diode with a semiconductor material that includes a dopant such as antimony, arsenic, phosphorous, or some other pentavalent dopant. In an n-doped Schottky diode, current may flow from the Schottky contact to the semiconductor material. By contrast, a p-doped Schottky diode may refer to a Schottky diode with a semiconductor material that includes a dopant such as boron, aluminum, or gallium. In a p-doped Schottky diode, current may flow from the semiconductor material to the Schottky contact.

The use of Schottky diodes may also provide a variety of benefits. One such benefit is that Schottky diodes may be simpler to manufacture, as only one semiconductor conductivity type is required (rather than, for example, a pn-junction diode that requires at least two semiconductor materials). An additional advantage is that the reaction time of a Schottky diode, and their associated speed, may be much higher than for pn-junction diodes because Schottky diodes are majority carrier devices.

Embodiments herein may provide a variety of additional advantages. For example, embodiments may allow for offloading of ESD protection from the die to the package substrate, and thus free up valuable on-die space. Additionally, embodiments may provide an additional level of protection which, in conjunction to on-die solutions, may provide valuable robustness for microelectronic packages in environments where an ESD event is highly likely.

FIGS. 1 and 2depict an example microelectronic package100with an ESD protection structure145, in accordance with various embodiments. Generally, the package100may include a die105coupled with a package substrate110. The die105may be or include, for example, a processor such as a central processing unit (CPU), general processing unit, a core of a distributed processor, or some other type of processor. Alternatively, the die105may be or include a memory such as a double data rate (DDR) memory, a nonvolatile memory (NVM), a volatile memory, a read-only memory (ROM), or some other type of memory or die. In some embodiments the die105may be or include a radio frequency (RF) chip or RF circuitry that is configured to generate, process, transmit, or receive a wireless signal such as a third generation (3G), a fourth generation (4G), a fifth generation (5G), a Wi-Fi, or some other type of wireless signal. In some embodiments the die105may include one or more passive components such as capacitors, resistors, etc. The various active or passive components may be positioned within, partially within, or on the surface of the die105.

The package substrate110may be, for example, considered to be a cored or coreless substrate. The package substrate110may include one or more layers of a dielectric material which may be organic or inorganic. The package substrate110may further include one or more conductive elements such as vias, pads, traces, microstrips, striplines, etc. The conductive elements may be internal to, or on the surface of, the package substrate. Generally, the conductive elements may allow for the routing of signals through the package substrate110, or between elements that are coupled to the package substrate110. In some embodiments the package substrate110may be, for example, a printed circuit board (PCB), an interposer, a motherboard, or some other type of substrate. It will be understood that although the package substrate110is discussed herein as an element of the microelectronic package100, in other embodiments the package substrate110may be considered to be an element separate from the microelectronic package100to which the microelectronic package100is coupled.

The die105may be coupled with the package substrate110by one or more interconnects115. The interconnects115may be, for example, C4 (controlled collapse chip), or flip-chip, bumps that are formed of a material such as tin, silver, copper, etc. Generally, the interconnects115may physically or communicatively couple the die105with the package substrate110. For example, one or more of the interconnects115may physically couple with, and allow electrical signals to pass between, pads of the die105and pads of the package substrate110(not shown for the sake of elimination of clutter ofFIGS. 1 and 2). In other embodiments, one or more of the interconnects115may physically couple the die105and the package substrate110, but the interconnects115may not communicatively couple the die105and the package substrate110.

The microelectronic package100may further include a plurality of interconnects such as interconnects120and125. The interconnects120and125may be formed of a material such as tin, copper, silver, etc. Specifically, the interconnects120/125may be elements of a ball grid array (BGA), pin grid array (PGA), land grid array (LGA), etc. The interconnects120/125may communicatively or physically couple the microelectronic package100to another element of an electronic device such as a PCB, a motherboard, an interposer, etc.

More specifically, the interconnect120may communicatively couple the microelectronic package100with a voltage input. The voltage input may be, for example, a power source, a communicative pathway (e.g., a signal line or a power line), or some other element of an electronic device of which the microelectronic package100is a part. Specifically, the voltage input may provide an electrical signal130with an input voltage Vin. The interconnect125may communicatively couple the microelectronic package100with a ground. The ground may be, for example, a ground plane of the electronic device or some other ground.

As noted above, the substrate110of the microelectronic package100may include a number of conductive elements such as vias, traces, microstrips, striplines, pads, etc. The conductive elements may form a number of signal/electronic pathways through the substrate110. One such pathway is signal path135. The signal path135may allow for the electrical signal130to travel between the interconnect120and the die105. The electrical signal130may be, for example, a data signal, a power signal, or some other type of electrical signal.

The substrate110may further include a ground path140. The ground path140may be coupled with the interconnect125and, through interconnect125, to ground. In some embodiments, the ground path140may be referred to as a “shunt” to ground.

The ground path140and the signal path135may be communicatively coupled by an ESD protection structure145. As can be seen, the ESD protection structure145may be communicatively located between the ground path140and the signal path135. The specific makeup of the ESD protection structure145may be discussed in greater detail below, however, at a high level the ESD protection structure145may behave as an insulator at low voltages, and be conductive at relatively high voltages. Specifically, the ESD protection structure145may have a voltage threshold referred to herein as +Vtrigger. If Vinis below (or, in some embodiments, at or below) +Vtrigger, then the ESD protection structure145may be insulative and not allow electrical signals to flow between the signal path135and the interconnect125. An example of such an insulative state is shown inFIG. 1.

However, if Vinis above (or, in some embodiments, at or above) +Vtrigger, then the ESD protection structure145may switch to a conductive state. An example of such a conductive state is shown inFIG. 2. Specifically, at least a portion of the electrical signal130may still traverse through the signal path135. However, a portion150of the electrical signal may also be shunted to ground through the ground path140.

In operation, +Vtriggermay be set to a level that is above the level at which a data or power signal may desirably traverse along the signal path135. However, it may also be desirable for +Vtriggerto be at a level that is below a voltage level at which ICs of the die105may become damaged. More specifically, it may be desirable for +Vtriggerto be at a level that is below the voltage level which may be present in an ESD event. As such, if ESD occurs, then Vinmay become greater than (or equal to, in some embodiments) +Vtrigger, and so the ESD protection structure145may become conductive and at least a portion of the voltage from the ESD may shunt to ground through the ground path140. However, if there is no ESD event, then Vinmay be below (or equal to, in some embodiments) +Vtriggerand so electrical communication along the signal path135may occur as normal.

Generally, it may be desirable for +Vtriggerto be less than or equal to a few volts (e.g. between approximately 2 and approximately 10 volts (V), or more specifically between approximately 4 and approximately 5 V.) However, it will be understood that these are example ranges and the +Vtriggerlevel of other embodiments may vary. Such variation may be based on, for example, the specific use case to which the microelectronic package may be put, specific properties of the die105, properties of the ICs of the die105, or other material or design considerations. More specifically, +Vtriggermay be based on or derived from the specific structure of the ESD protection structure.

The example ofFIGS. 1 and 2are described above with respect to +Vtriggerbeing a positive value, and the ESD event occurring when Vinis greater than +Vtrigger. In this situation, a shunt of excess current from the signal path135may shunt to ground through the ground path140, as depicted inFIG. 2. This excess current may shunt to ground because the voltage of the signal path135may be greater than that of ground, and so the current may flow from the higher voltage to the lower voltage along the ground path140. However, it will be understood that a significant negative voltage swing may likewise cause damage to the die105. As such, in some embodiments it may be desirable for the ESD protection structure145to likewise have a negative threshold voltage −Vtriggerwhich may help to protect against negative swings in the voltage Vin. In this embodiment, if Vinis at or below −Vtrigger, then current may flow from the ground path140into the signal path135. The specific values or configuration of the ESD protection structure145, specifically with respect to the existence of, or values of, +Vtriggeror −Vtrigger, may be based on design-related factors or the specific use case to which the microelectronic package100may be put. Various examples of use cases related to threshold voltages may be described in greater detail below with respect to other embodiments herein.

Additionally, with respect to the signs of the various voltages, it will be understood that the examples described herein are based on the assumption that ground is equal to approximately 0 V. However, in some embodiments “ground” may be kept at a constant positive or negative voltage, and so the specific values of voltages such as +Vtrigger, −Vtrigger, etc. may be considered to be with respect to the value of ground. In other words, in some embodiments −Vtriggermay be a positive voltage, or +Vtriggermay be a negative voltage, dependent on the voltage at which ground is held.

It will be understood that the above-describedFIGS. 1 and 2are intended as examples, and other embodiments may vary with respect to number of elements, specific configurations, etc. For example, it will be understood that the signal path135and the ground path140are highly simplified examples, and other embodiments may include additional conductive elements such as pads, traces, etc. Similarly, the relative sizes, shapes, or number of the paths, the dies, the interconnects, etc. may be different in other embodiments. For example, some embodiments may have additional dies105, additional interconnects115/120/125, additional signal paths135or ground paths140, additional ESD protection structures145, etc., or one or more of those elements in a location that is different than the location depicted inFIG. 1 or 2. Other variations may be present in other embodiments.

FIGS. 3-6illustrate embodiments wherein an ESD protection structure (e.g., ESD protection structure145) includes a package-level Schottky diode. Specifically,FIGS. 3 and 4depict a single-sided ESD protection wherein the Schottky diode may shunt the signal line against a ground line or plane that is adjacent to the signal line.

Specifically,FIG. 3depicts a simplified cross-sectional view of a package substrate310with a diode-based ESD protection structure, in accordance with various embodiments. The package substrate310may be similar to, and share one or more characteristics with, package substrate110. The package substrate310may include a substrate material312which may be, for example, an organic or inorganic dielectric material such as a build-up film (BUF), ceramic, or some other type of dielectric material. It will be understood, however, that the package substrate310is depicted as only include two layers with a substrate material312therebetween. However, in other embodiments the package substrate may have significantly more layers than depicted, for example on the order of 4-32 layers.

The package substrate310may include a signal line307and a ground line303. The signal and ground lines307and303may be or may include, for example, conductive elements such as a trace, a microstrip, a stripline, a via, a pad, etc. The signal and ground lines307and303may be formed of a conductive material such as copper, gold, or some other conductive material. The signal line307may be an element of a signal path such as signal path135. Specifically, the signal line307may be communicatively coupled to, and convey data signals to or from, a die such as die105. In some embodiments the signal line307may be referred to as an input/output (I/O) line. The ground line303may be an element of a ground path such as ground path140. In some embodiments, the ground line303may be one of the conductive elements described above. In other embodiments, the ground line303may be a ground plane (e.g., a sheet of a conductive material that takes up a substantial portion of the layer of the package substrate310in which its positioned).

The package substrate310may further include a diode355, which may act as an ESD protection structure such as ESD protection structure145described above. Specifically, the diode355may be a Schottky diode that includes a Schottky contact317, a semiconductor material323, and an ohmic contact327. The semiconductor material323may be an organic-based or an oxide-based semiconductor material as described above. Specifically, the semiconductor material323may be, or may be some combination of, Ga2O3, In2O3, IGZO, ZnO2, CuPc, TiPc, F16CuPc, F16CuPc, P3HT, HAT-CN, F4TCNQ, rubrene, or some other appropriate organic-based or oxide-based semiconductor material.

The Schottky contact317may be a metal material such as molybdenum, platinum, chromium, tungsten, or a silicide such as palladium silicide or platinum silicide. More specifically, if the semiconductor material323is, for example, IGZO, then it may be desirable for the Schottky contact317to be or include palladium (Pd), titanium nitride (TiN), gold (Au), platinum (Pt), etc. (or some combination thereof). As another example, if the semiconductor material323is Ga2O3, it may be desirable for the Schottky contact317to be or include nickel (Ni), Pt, Pd, Au, etc. (or some combination thereof).

As can be seen inFIG. 3, the Schottky contact317may be positioned directly adjacent to the semiconductor material323, which may form a Schottky barrier. As noted above, the Schottky barrier may be a potential energy barrier for electrons formed at the junction of the Schottky contact317and the semiconductor material323. The potential energy barrier may be a Vtriggersuch as +Vtriggeror −Vtriggeras described above. Once the voltage Vinbecomes greater than (or equal to) +Vtrigger(or less than or equal to −Vtrigger), then the diode355may become conductive and allow current to flow through the diode between, for example, the signal line307and the ground line303. Generally, a Schottky diode may be referred to as “forward-rectified” which means that current may generally only flow in a single direction through the diode355, e.g. from the signal line307to the ground line303if the semiconductor material323is n-doped, or from the ground line303to the signal line307if the semiconductor material323is p-doped, but not vice-versa.

The ohmic contact327may be a non-rectified contact which allows current to flow in both directions through it. Generally, the ohmic contact327may be a material such as aluminum (Al), aluminum-silicon (Al—Si), titanium disulfide (TiS2), titanium nitride (TiN), tungsten (W), molybdenum disilicide (MoSi2), platinum silicide (PtSi), cobalt silicide (CoSi2), tungsten silicide (WSi2), or some other appropriate material.

As can be seen, the Schottky contact317and the semiconductor material323may form a Schottky barrier as described above. A trace protrusion313may be an element of, or coupled to, the signal line307, and may communicatively couple the signal line307to the Schottky contact. In this manner, current may flow between the signal line307and the Schottky contact317through the trace protrusion.

It will be understood that the particular embodiment depicted inFIG. 3is intended as an example embodiment, and other embodiments may vary in one or more respects. For example, in some embodiments the trace protrusion313may not be present, and rather the Schottky contact317may directly abut the signal line307. In some embodiments the signal line307may be below the ground line303rather than above it as depicted inFIG. 3. In some embodiments, the signal line307or the trace protrusion313may be formed of a material which may be appropriate for use as a Schottky contact, and therefore the additional Schottky contact317may not be present. Similarly, in some embodiments the ohmic contact327may not be present, as the material used for the ground line303may be appropriate for use as an ohmic contact. In other embodiments, dependent on the type of doping (n-doped or p-doped) of the semiconductor material323, and hence the resultant conductivity, the Schottky contact317may be coupled with the ground line303, and the ohmic contact327may be coupled with the signal line307. Other factors that may affect the specific configuration of the diode355may include manufacturing or circuit-design considerations. It will be noted that other variations may be present in other embodiments. For example, the relative sizes, shapes, etc. of various elements of the Figure may be different in different embodiments. For example, in some embodiments the Schottky contact317may be generally the same lateral size as the semiconductor material323or the ohmic contact327. In some embodiments, even though the ESD protection structure is described as being internal to the package substrate310, in some embodiments the signal line307or the ground line303may be an outer-layer of the package substrate310. In some embodiments the signal line307and the ground line303may be perpendicular to one another rather than parallel, or at some other angle with respect to one another.

FIG. 4depicts a simplified circuit diagram of the diode-based ESD protection structure ofFIG. 3, in accordance with various embodiments. The circuit may be an element of the package substrate such as package substrate310. The circuit may include a connection to a die such as interconnect415. The interconnect may be similar to, and share one or more characteristics with, interconnect115and may provide a connection between the circuit and a die such as die105. The interconnect415may be coupled with a signal line407which may be similar to, and share one or more characteristics with, signal line307. The circuit may also include a connection to ground403, which may be similar to, and share one or more characteristics with, ground303. A diode455, which may be similar to, and share one or more characteristics with, diode355may be positioned between the ground403and the signal line407.

In the specific embodiment ofFIGS. 3 and 4, is may be seen that the semiconductor material323is p-doped, and the diode355may have a negative threshold voltage −Vtrigger. When the voltage Vinof the signal line307/407drops below the negative threshold voltage −Vtrigger, the diode355/455may become conductive and allow current to flow from ground403(i.e., the ground line303) through the diode355/455(and, more specifically, from the ohmic contact327through the semiconductor material323to the Schottky contact317) and into the signal line307/407.

It will be understood that the embodiment ofFIG. 4is intended as an example embodiment and other embodiments may include additional elements to those depicted. For example, additional elements such as resistors, capacitors, etc. are not depicted inFIG. 4but may be present in real-world embodiments. It will also be understood that other embodiments may have a different configuration than that depicted inFIG. 4. For example, if the semiconductor material323was n-doped, then the Schottky contact317may be coupled with the ground line303and the ohmic contact327may be coupled with the signal line307. In other embodiments, it may be desired for the diode355/455to have a positive threshold voltage +Vtrigger. In this embodiment, the depicted diode455in the circuit diagram ofFIG. 4may be flipped such that it allows current to flow from the signal line407to ground403, and the physical structure of the diode355may be similarly altered (if necessary) based on whether the semiconductor material323is n-doped or p-doped.

FIG. 5depicts an alternative configuration where two diodes may be present. One diode may connect the signal path to ground, and the other diode may connect the signal path to a power line. Specifically,FIG. 5depicts a simplified cross-sectional view of an alternative package substrate510with a diode-based ESD protection structure, in accordance with various embodiments. It will be understood that although each and every element ofFIG. 5may not be specifically enumerated, elements that are generally identical to one another (e.g., the labelled Schottky contact517and the unlabeled Schottky contact) may be considered to have similar properties to one another.

The package substrate510may be similar to, and share one or more characteristics or elements with, the package substrate310ofFIG. 3. Specifically, the package substrate510may include a substrate material512, a signal line507, and a ground line503which may be similar to, and share one or more characteristics with, substrate material312, signal line307, and ground line303. The package substrate510may further include a diode555bpositioned between the signal line507and the ground line503. The diode555bmay be similar to, and share one or more characteristics with, diode355. The diode555bmay include an ohmic contact527, a semiconductor material523, and a Schottky contact517. The ground line503may include a trace protrusion513which may be similar to, and share one or more characteristics with, trace protrusion313. As described above with respect to trace protrusion313, the trace protrusion513may not be present in some embodiments.

The package substrate510may further include a power line509. The power line may be coupled with a power source such as a battery or some other power source and configured to provide power to elements of the package substrate510, or an element that is coupled to the package substrate such as a die like die105.

A diode555amay be positioned between, and coupled to, the signal line507and the power line509. The diode555amay be similar to, and share one or more characteristics with, diode555b. Specifically, the diode555amay include a Schottky contact517, a semiconductor material523, and an ohmic contact527. The diode555amay be coupled with the signal line507by a trace protrusion513(which may be optional, as described above).

In some embodiments, the diode555amay be generally identical to the diode555bin terms of materials used, relative sizes of various elements, etc. In other embodiments, the diode555amay use different materials (e.g., have a different material for the Schottky contact517, a different material for the semiconductor material523, etc.) than the diode555b. In some embodiments, the semiconductor material523of diode555amay have a different doping type (e.g., n-doped or p-doped) than the semiconductor material523of diode555b. Similarly, in some embodiments, the diode555amay have different dimensions than the diode555b. The specific materials used, dimensions, etc. may vary based on factors such as a desired +Vtriggeror −Vtriggerfor the diodes, manufacturing considerations, circuit considerations, etc.

The dual-diode structure of the package substrate510may be desirable because it may allow for both positive and negative voltage swings of Vin, and provide a shunt for the excess current in both directions. For example, in the specific embodiment depicted inFIGS. 5 and 6, the semiconductor material523of both diodes555aand555bmay be p-doped. In this embodiment, current may flow through diode555bin one direction from the ground line503to the signal line507(or vice-versa). Similarly, current may flow through diode555ain one direction from the signal line507to the power line509. As a result, the diode555bmay have one trigger voltage of (e.g., −Vtrigger), and the diode555amay have another trigger voltage (e.g., +Vtrigger). In some embodiments +Vtriggerand −Vtriggermay have the same value (e.g., +5 V and −5V) while in other embodiments +Vtriggerand −Vtriggermay have different values.

It will be understood that the above-described embodiment is intended as one example of various voltages or a specific arrangement of the trigger voltages. Other embodiments may vary. For example, in some embodiments the diode555bmay have a positive trigger voltage (e.g., +Vtrigger) and the diode555amay have a negative trigger voltage (e.g., −Vtrigger). This may occur, for example, if the specific structure of the diodes was altered, the doping of the semiconductor material within the diodes was altered, etc. In some embodiments, both of the diodes555aand555bmay have positive trigger voltages (e.g., +5V and +10V) or both of the diodes555aand555bmay have a negative trigger voltage (e.g., −5V and −10V). In some embodiments, one of the trigger voltages may be 0V. Other embodiments may vary.

As may be seen, the package substrate510may further include a via565coupled with the signal line507, and a pad560coupled with the via. These elements may be used to communicatively couple the signal line507to a die such as die105. Specifically, the pad560may couple with an interconnect such as interconnect115.

FIG. 6depicts a simplified circuit diagram of the diode-based ESD protection structure ofFIG. 5, in accordance with various embodiments. Similarly to the circuit ofFIG. 4, the circuit ofFIG. 6may include an interconnect615, a signal line607, a diode655b, and a connection to ground603which may be respectively similar to, and share one or more characteristics with, interconnect415, signal line507, diode555b, and ground403. The circuit may further include a power line609and a diode655a. The power line609may be similar to, and share one or more characteristics with, power line509ofFIG. 5. Specifically, the power line609may be coupled with a power source such as a battery or some other power source. A diode655a, which may be similar to diode655b, may be positioned between, and electrically coupled to, the signal line607and the power line609. As noted above with respect toFIG. 5, in some embodiments the diode655amay be identical to diode655b, while in other embodiments the diode655aand655bmay have one or more characteristics that are different from one another which may result, for example, in the two diodes655a/655bhaving different trigger voltages Vtrigger.

As described above, diode655b/555bmay have a trigger voltage of −Vtrigger. If the voltage Vinof the signal line507/607falls to a value at or below −Vtrigger(as may occur in an ESD event), then the signal line507/607may draw current from ground603(e.g., through the ground line503) through the diode555b/655bto increase the voltage Vinbefore a die coupled with the package substrate510is harmed. Specifically, the voltage difference between Vinof the signal line507/607and ground603may be such that diode555b/655bbecomes conductive and draws current from the ground line503through the p-doped semiconductor material523to the Schottky contact517of the diode555b/655band into the signal line507/607.

Similarly, diode655a/555amay have a trigger voltage of +Vtrigger, as described above. If the voltage Vinof the signal line507/607goes to a value at or above +Vtrigger(as may occur in an ESD event), then the signal line507/607may shunt current from the signal line507/607through the diode555a/655ato the power line509to decrease the voltage Vinbefore a die coupled with the package substrate510is harmed. Specifically, the voltage difference between Vinof the signal line507/607and the power line509/609may be such that the diode555a/655abecomes conductive and draws current from the signal line507/607through the p-doped semiconductor material523to the Schottky contact517of the diode555a/655aand into the power line509/609.

Similarly toFIGS. 3 and 4, it will be understood thatFIGS. 5 and 6are intended as an example embodiment, and other embodiments may vary from the specific configuration ofFIG. 5 or 6. For example, in some embodiments the ground line503may be below the signal line507, and the power line509may be above the signal line507(with respect to the orientation ofFIG. 5). Additionally, the circuit diagram ofFIG. 6may include one or more additional elements such as additional resistors, capacitors, etc. Additionally, as described above with respect toFIGS. 3 and 4, it will be understood thatFIGS. 5 and 6are one example depiction of a specific arrangement of Schottky diodes and a circuit diagram. In some embodiments, the arrangement of one or both of diodes555aand555b(e.g., which line the Schottky contact of the diode is closest to) may be based on the type of doping of the semiconductor material of that diode. In some embodiments, the semiconductor materials of diodes555aand555bmay be doped differently from one another (i.e., one may be n-doped and the other may be p-doped). Similarly, in some embodiments the diodes655aand655bmay be switched such that, for example, diode655bis configured to draw current from signal line607into ground603, diode655ais configured to draw current from power line609into signal line607, or both. In some embodiments, the specific threshold voltage of the diodes, and whether it is positive or negative (i.e., +Vtriggeror −Vtrigger) may different based on the physical structure of the diodes, the direction in which it is desired to draw current, etc. Such differences may be based on factors such as materials used, use cases of the resultant package substrate or circuit (or microelectronic package), design considerations, etc.

In some embodiments, it may be desirable to combine aspects of the package substrates ofFIGS. 3 and 5. For example,FIG. 3may be seen to depict only a signal line307and a ground line303with a single diode. In this embodiment, current may only flow in one direction if, for example, the voltage along the signal line is significantly higher than above the ground line and, more specifically, above Vtrigger. However, if the voltage swings too low (e.g., below −Vtrigger), the ESD protection ofFIG. 3may not provide significant protection. By contrast,FIG. 5may offer ESD protection based on both +Vtriggerand −Vtrigger, as described above. However, such additional protection may be based on the presence of both a ground line503and a power line509.

FIG. 13depicts an example configuration that may combine aspects of the package substrates of bothFIGS. 3 and 5. Specifically,FIG. 13illustrates a simplified cross-sectional view of an alternative package substrate1310with a diode-based ESD protection structure, in accordance with various embodiments. InFIG. 13, an n-doped diode and a p-doped diode may be used to couple a signal line and a ground line, thereby providing ESD protection for both positive and negative voltage swings without the use of an extra line.

Specifically,FIG. 13depicts a package substrate1310which may be similar to, and share one or more characteristics with, package substrate310. The package substrate1310may include a signal line1307, a ground line1303, and a substrate material1312which may be respectively similar to, and share one or more characteristics with, signal line307, ground line303, and substrate material312. The signal lines1307may include trace protrusions1313which may be similar to, and share one or more characteristics with, trace protrusions313.

The package substrate1310may further include a pair of diodes1355aand1355b(collectively “diodes1355”). Respective ones of the diodes1355aand1355bmay include a Schottky contact1317, an ohmic contact1327, and a semiconductor material1323aand1323b(collectively, “semiconductor material1323”), which may each be respectively similar to Schottky contacts317, ohmic contact327, and semiconductor material323. In this specific embodiment, the semiconductor material1323amay be p-doped, which may result in the Schottky diode1355a(which would be a p-doped Schottky diode) allowing current to flow from the ground line1303to the signal line1307. Also, the semiconductor material1323bmay be n-doped, which may result in the Schottky diode1355b(which would be an n-doped Schottky diode) allowing current to flow from the signal line1307to the ground line1303.

FIG. 14depicts a simplified circuit diagram of the diode-based ESD protection structure ofFIG. 13, in accordance with various embodiments. Similarly to other circuits described herein, the circuit ofFIG. 14may include an interconnect1415, a signal line1407, diodes1455aand1455b, and connections to ground1403which may be respectively similar to, and share one or more characteristics with, interconnect415, signal line1307, diodes1355aand1355b, and ground403.

As previously noted, and as depicted inFIG. 14, the diodes1355a/1455aand1355b/1455bmay be differently doped. Specifically, diode1355a/1455amay be p-doped, and diode1355b/1455bmay be n-doped. As such, the p-doped diode1355a/1455amay have a negative voltage threshold −Vtriggersuch that if the signal voltage Vinof the signal line1307/1407falls at or below −Vtrigger, the p-doped diode1355a/1455amay become conductive and draw current from ground1403(for example, from the ground line1303through the semiconductor material1323ato the Schottky contact1317and into the signal line1307). By contrast, the n-doped diode1355b/1455bmay have a positive voltage threshold +Vtriggersuch that if the signal voltage Vinof the signal line1307/1407rises at to a value at or above +Vtrigger, the n-doped diode1355b/1455bmay become conductive and shunt excess current from the signal line1307/1407to ground1403(for example, from the signal line1307through the Schottky contact1317to the n-doped semiconductor material1323band into the ground line1303). In this way, a die coupled with the package substrate1310may be protected from both positive and negative ESD events while only using a single signal line and a single ground line.

FIG. 15depicts another example configuration that may combine aspects of the package substrates of bothFIGS. 3 and 5. Specifically,FIG. 15illustrates a simplified cross-sectional view of an alternative package substrate1510with a diode-based ESD protection structure, in accordance with various embodiments.

Package substrate1510may be similar to, and share one or more characteristics with, package substrate510. For example, the package substrate1510may include a substrate material1512, a signal line1507, trace protrusions1513, a pad1560, and a via1565which may be respectively similar to, and share one or more characteristics with, substrate material512, signal line507, trace protrusions513, pad560, and via565. As can be seen, package substrate1510may include at least two ground lines1503aand1503b(collectively “ground lines1503”) which may be respectively similar to, and share one or more characteristics with, ground line1503. The ground lines1503may be positioned on opposite sides of the signal line1507(although, as mentioned elsewhere, in some embodiments the exact configuration of the various signal lines may be different in different embodiments).

The package substrate1510may further include diodes1555aand1555b(collectively, “diodes1555”) which may be respectively similar to, and share one or more characteristics with, diodes555aand555b. As can be seen, diode1555amay couple the signal line1507and ground line1503a, while the other of the diodes1555bmay couple the signal line1507and ground line1503b. Each of the diodes1555may include an ohmic contact1527, a semiconductor material1523, and a Schottky contact1517which may be respectively similar to, and share one or more characteristics with, ohmic contact527, semiconductor material523, and Schottky contact517.

FIG. 16depicts a simplified circuit diagram of the diode-based ESD protection structure ofFIG. 15, in accordance with various embodiments. Similarly to other circuits described herein, the circuit ofFIG. 16may include an interconnect1615, a signal line1607, and diodes1655aand1655b(collectively, “diodes1655”), which may be respectively similar to, and share one or more characteristics with, interconnect415, signal line1507, and diodes1555aand1555b. The circuit ofFIG. 16may further include connections to ground1603aand1603b, which may be respectively similar to ground403.

In the embodiment ofFIGS. 15 and 16, the semiconductor material1523of the diodes1555/1655may be p-doped. As such, the diodes1555may allow current to flow from the p-doped semiconductor material1523to the Schottky contact1517of the respective diodes1555. More specifically, as can be seen inFIG. 16, the p-doped diode1655amay allow current to flow from ground1603a(i.e., ground line1503a) to the signal line1507/1607. The p-doped diode1655bmay allow current to flow from the signal line1507/1607to ground1603b(i.e., the ground line1503b).

In this embodiment, diode1555a/1655amay have a threshold voltage of −Vtrigger. When the signal voltage Vinof the signal line1507/1607is at or below −Vtrigger, the diode1555a/1655amay become conductive and the signal line1507/1607is able to draw current from ground1603a(e.g., by way of the ground line1503a). By contrast, diode1555b/1655bmay have a threshold voltage of +Vtrigger. When the signal voltage Vinof the signal line1507/1607is at or above +Vtrigger, the diode1555b/1655bmay become conductive and shunt excess current from the signal line1507/1607through the diode1555b/1655bto ground1603b(e.g., by way of the ground line1503b). In this way, similarly to other embodiments, a die coupled with the signal line1507/1607should be protected from excess voltage swings (such as those caused by an ESD event) in either the positive or negative direction.

Similarly to other embodiments described herein, it will be understood that the specific configurations depicted inFIGS. 13-16are intended as example embodiments, and other embodiments may vary in terms of the size, shape, or position of various materials such as the contacts or lines, the specific doping of the semiconductor material, whether a diode has a positive or negative voltage threshold, and direction in which current may flow through a diode, etc. as described above with respect to, for example,FIGS. 5 and 6. Similarly to the other embodiments, the specific configuration of a diode may be based on factors such as materials used, design considerations, manufacturing considerations, use cases, etc.

In some embodiments, rather than having the various lines and diodes spanning multiple layers of the package substrate, the structures and the diodes may be placed in a single layer of the package substrate and be arranged in a lateral configuration rather than the multi-layer configuration of other embodiments depicted herein.

FIG. 7depicts a simplified top-down view of a package substrate710with a diode-based ESD protection structure, in accordance with various embodiments.FIG. 8depicts a simplified cross-sectional view of the package substrate710ofFIG. 7along line A-A′, in accordance with various embodiments.

The package substrate710may include a substrate material712, ground line703, a signal line707, and a power line709which may be similar to, and share one or more characteristics with, substrate material312, ground line303, signal line307, and power line309. However, as may be seen inFIGS. 7 and 8, the ground, signal, and power lines303/307/309may be arranged in a single layer of the package substrate710rather than multiple layers as depicted with respect to package substrates310and510. As can be seen inFIG. 7, the ground, signal, and power lines703/707/709may be communicatively coupled with a die705which may be similar to, and share one or more characteristics with, die105.

The package substrate710may further include a diode755bpositioned between the ground line703and the signal line707, and a diode755apositioned between the signal line and the power line709. The diodes755band755amay be respectively similar to, and share one or more characteristics with, diodes555band555a. Specifically, the diodes755band755amay include a Schottky contact717, a semiconductor material723, and an ohmic contact727which may be respectively similar to, and share one or more characteristics with, Schottky contact517, semiconductor material523, and ohmic contact527.

It will also be noted that inFIG. 8various of the elements of the diodes755aand755bmay at least partially overlap one another. For example, the semiconductor material723may at least partially overlap the ohmic contact727, and the Schottky contact717may at least partially overlap the semiconductor material723and the signal line707. The reason for this overlap may be because manufacturing tolerances may not permit perfect (e.g., non-overlapping) alignment. However, in some embodiments the depicted overlap may be eliminated, for example through the use of self-aligned manufacturing processes.

FIG. 17depicts a simplified circuit diagram of the diode-based ESD protection structure ofFIGS. 7 and 8, in accordance with various embodiments. Similarly to the circuit ofFIG. 4 or 6, the circuit ofFIG. 17may include an interconnect1115, a signal line1107, diodes1155aand1155b, a power line1109, and a connection to ground1103which may be respectively similar to, and share one or more characteristics with, interconnect415, signal line707, diodes755aand755b, power line709, and connection to ground403.

In the embodiment ofFIGS. 7, 8, and 17, it will be noted that the semiconductor material723of diodes755a/1155aand755b/1155bmay be p-doped. That is, the semiconductor material723may draw current from the semiconductor material723to the Schottky contact717of the diodes. In this embodiment, diode755b/1155bmay have a positive trigger voltage +Vtriggersuch that when the signal voltage Vinof the signal line707/1107is at or above +Vtrigger, the diode755b/1155bmay become conductive and shunt excess current from the signal line707/1107to the ground line703and ground1103. Similarly, diode755a/1155amay have a negative trigger voltage −Vtriggersuch that when the signal voltage Vinof the signal line707/1107is at or below −Vtrigger, the diode755a/1155amay be come conductive and draw current from the power line709/1109through the diode755a/1155ato the signal line707/1107.

Similarly to other embodiments described above, it will be understood that the embodiment ofFIGS. 7, 8, and 17are intended as an example embodiment and other embodiments may vary in terms of the specific size of materials, the specific configuration, the specific shape, etc. For example, in some embodiments one or both of the diodes755aand755bmay be configured such that the Schottky contacts or ohmic contacts are coupled with a line (e.g., signal line, ground line, power line, etc.) that is different than the one depicted in the Figures. In some embodiments, the semiconductor material, the values (positive or negative) of the various trigger voltages, the direction which the current may flow through the diodes, etc. may be different in different embodiments. In some embodiments the ohmic contacts727or the Schottky contacts717may not be present in one or both of the diodes755a. Some embodiments may combine aspects of the embodiments ofFIG. 3 or 5with aspects of the embodiments ofFIGS. 7 and 8. Specifically, one of the lines (e.g., the ground line703) may be adjacent to the signal line707in a same layer of the package substrate710, and another of the lines (e.g., the power line)709may be adjacent to the signal line707in a different layer of the package substrate710. Other variations may be present in other embodiments. The specific configurations, doping, direction of current flow, etc. may be based on aspects such as use cases, materials used, manufacturing considerations, design considerations, etc.

In some embodiments, the ESD protection structure may include a pn-junction diode rather than a Schottky diode.FIG. 9depicts such an example using a pn-junction diode. Specifically,FIG. 9depicts a simplified cross-sectional view of an alternative package substrate910with a diode-based ESD protection structure, in accordance with various embodiments.

The package substrate910may be similar to, and include one or more characteristics of, package substrate310. Specifically, the package substrate910may include a signal line907, a substrate material912, and a ground line903, which may be respectively similar to, and share one or more characteristics of, signal line307, substrate material312, and ground line303. The signal line907may include a trace protrusion913, which may be similar to, and share one or more characteristics with, trace protrusion313.

The package substrate910may also include a diode955. The diode955may include two ohmic contacts927aand927b, which may be respectively similar to ohmic contact327. The diode955may additionally include two semiconductor materials923aand923b. One of the semiconductor materials, e.g. semiconductor material923b, may be an n-type semiconductor material. The other of the semiconductor materials, e.g. semiconductor material923a, may be a p-type semiconductor material. The specific configuration of the semiconductor materials923aand923bmay rectify the diode955such that current may only flow in a single direction through the diode955, e.g. from signal line907to ground line903, when the voltage Vinis at or above Vtrigger. In this way, the diode955may serve as an ESD protection structure in a manner similar to that of diode355described above. The circuit diagram of the package substrate910may be generally similar, or identical, to the circuit diagram depicted inFIG. 4with respect toFIG. 3.

Similarly to other Figures herein, it will be understood thatFIG. 9is intended as an example embodiment, and other embodiments may vary from the specific configuration ofFIG. 9. For example, the embodiment ofFIG. 5may vary as described above with respect toFIG. 3. For example, in some embodiments the ground line503may be below the signal line507, and the power line509may be above the signal line507. In some embodiments, the locations of the n-type semiconductor material923band the p-type semiconductor material923amay be switched dependent on the desired rectification of the diode955.

As can be seen the n-side (e.g., the side on which the n-type semiconductor material923bis present) and the p-side (e.g., the side on which the p-type semiconductor material923ais present) of the diode include ohmic contacts927aand927b. However, the n-type semiconductor material923band the p-type semiconductor material923amay have entirely different work functions. As a result, the ohmic contacts927aand927bmay be formed of two dissimilar metals, that is, the material of the ohmic contact927amay be different than the material of the ohmic contact927b.

It will be understood that although various embodiments herein are described as including a single diode coupling two lines, in some embodiments the package substrate may include an array of diodes that perform an ESD protection function for a die.FIG. 18depicts a simplified top-down view of an array of diodes in an ESD protection structure of a package substrate, in accordance with various embodiments.

Specifically,FIG. 18depicts a package substrate1210which may be similar to, and share one or more characteristics of, package substrate310. The package substrate1210may include a substrate material1212, a ground line1203, a signal line1207, and a power line1209, which may be respectively similar to, and share one or more characteristics with, substrate material312, ground line303, signal line307, and power line309.

The package substrate1210may further include a number of diodes1255aand1255b. Specifically, diodes1255amay be positioned between, and communicatively couple, the signal line1207and the ground line1203. Diodes1255bmay be positioned between, and communicatively couple, the signal line1207and the power line1209.

The diodes1255aand1255bare depicted inFIG. 18as featureless circles because the diodes1255aand1255bmay have a variety of properties of diodes described herein. For example, one or more of the diodes may be a Schottky diode or a pn-junction diode. One or more of the diodes may be p-doped or n-doped, which may likewise influence the specific configuration of how the Schottky contact and the semiconductor material are arranged within the diode.

Additionally, not all of the diodes1255aand1255bmay be identical to one another. For example, one of diodes1255amay be a Schottky diode and another of diodes1255amay be a pn-junction diode. Other variations may be present. For example, one may be p-doped and another may be n-doped. One may allow current flow from the ground line1203to the signal line1207, while another may allow current flow from the signal line1207to the ground line1203. In some embodiments, they may have different threshold voltages.

Other variations may be present in other embodiments. For example, in some embodiments the diodes1255aand1255bmay not be placed in a staggered array as shown, but rather may be positioned in a different configuration. In some embodiments, the diode may be in a 2D or three-dimensional (3D) configuration. In some embodiments the configuration or presence of various lines may be different, for example lacking the power line1209, replacing the power line1209with another ground line1203, configuring the lines in a single layer of the package substrate1210rather than a plurality of layers, etc. Other variations may be present in other embodiments.

FIG. 10depicts an example technique for the manufacture of a package substrate with a diode-based ESD protection structure, in accordance with various embodiments. Generally,FIG. 10may be described with reference to the embodiment ofFIG. 3, however it will be understood thatFIG. 10may be applicable, in whole or in part, with or without modification, to other embodiments of the present disclosure.

The technique may include forming, at1005, in the package substrate, a signal line that is to carry a data signal to or from a die that is coupled with the package substrate. The package substrate may be similar to, for example, package substrate310. The signal line may be similar to, for example, signal line307. The die may be similar to, for example, a die such as die105. Forming the signal line may be performed through a technique such as plating, lithographic deposition, or some other type of deposition technique.

The technique may further include forming, at1010, in the package substrate, a conductive line. The conductive line may be similar to, for example, ground line303. In other embodiments, the conductive line may be similar to, for example a power line such as power line509. Similarly to element1005, the formation of the conductive line may be performed through a technique such as plating, lithographic deposition, or some other type of deposition technique.

The technique may further include forming, at1015, in the package substrate, an ESD protection structure that includes a diode communicatively coupled to the signal trace and the conductive trace. The diode may be similar to, for example, diode355. In some embodiments, the diode may be pre-formed and positioned in the package substrate, for example on top of the ground line, and then the substrate material may be deposited around the diode. In some embodiments, deposition of the diode material may be achieved through various techniques such as sputter deposition, physical vapor deposition (PVD), atomic layer deposition (ALD), vacuum evaporation, etc.

It will be understood that the above-described embodiment is an example embodiment, and other embodiments may vary from that depicted. For example, some embodiments may include additional steps (e.g., etching, annealing, etc.) In some embodiments, certain elements may be performed in an order that is different from that depicted inFIG. 10. For example, element1010may be performed prior to, or at the same time as, element1005. In some embodiments, element1015may be performed prior to, or at the same time as, element1010. Other variations may be present in other embodiments.

FIG. 11is a side, cross-sectional view of an IC device assembly1700that may include one or more IC packages or other electronic components (e.g., a die) with a package substrate with a diode-based ESD protection structure, in accordance with any of the embodiments disclosed herein. The IC device assembly1700includes a number of components disposed on a circuit board1702(which may be, e.g., a motherboard). The IC device assembly1700includes components disposed on a first face1740of the circuit board1702and an opposing second face1742of the circuit board1702; generally, components may be disposed on one or both faces1740and1742.

The IC device assembly1700illustrated inFIG. 11includes a package-on-interposer structure1736coupled to the first face1740of the circuit board1702by coupling components1716. The coupling components1716may electrically and mechanically couple the package-on-interposer structure1736to the circuit board1702, and may include solder balls (as shown inFIG. 11), male and female portions of a socket, an adhesive, an underfill material, and/or any other suitable electrical and/or mechanical coupling structure.

The package-on-interposer structure1736may include an IC package1720coupled to a package interposer1704by coupling components1718. The coupling components1718may take any suitable form for the application, such as the forms discussed above with reference to the coupling components1716. Although a single IC package1720is shown inFIG. 11, multiple IC packages may be coupled to the package interposer1704; indeed, additional interposers may be coupled to the package interposer1704. The package interposer1704may provide an intervening substrate used to bridge the circuit board1702and the IC package1720. The IC package1720may be or include, for example, a die, an IC device, or any other suitable component. Generally, the package interposer1704may spread a connection to a wider pitch or reroute a connection to a different connection. For example, the package interposer1704may couple the IC package1720(e.g., a die) to a set of BGA conductive contacts of the coupling components1716for coupling to the circuit board1702. In the embodiment illustrated inFIG. 11, the IC package1720and the circuit board1702are attached to opposing sides of the package interposer1704; in other embodiments, the IC package1720and the circuit board1702may be attached to a same side of the package interposer1704. In some embodiments, three or more components may be interconnected by way of the package interposer1704.

The IC device assembly1700may include an IC package1724coupled to the first face1740of the circuit board1702by coupling components1722. The coupling components1722may take the form of any of the embodiments discussed above with reference to the coupling components1716, and the IC package1724may take the form of any of the embodiments discussed above with reference to the IC package1720.

The IC device assembly1700illustrated inFIG. 11includes a package-on-package structure1734coupled to the second face1742of the circuit board1702by coupling components1728. The package-on-package structure1734may include an IC package1726and an IC package1732coupled together by coupling components1730such that the IC package1726is disposed between the circuit board1702and the IC package1732. The coupling components1728and1730may take the form of any of the embodiments of the coupling components1716discussed above, and the IC packages1726and1732may take the form of any of the embodiments of the IC package1720discussed above. The package-on-package structure1734may be configured in accordance with any of the package-on-package structures known in the art.

FIG. 12is a block diagram of an example electrical device1800that may include one or more package substrates with a diode-based ESD protection structure, in accordance with any of the embodiments disclosed herein. For example, any suitable ones of the components of the electrical device1800may include one or more of the IC device assemblies1700, IC packages, IC devices, or dies disclosed herein. A number of components are illustrated inFIG. 12as included in the electrical device1800, but any one or more of these components may be omitted or duplicated, as suitable for the application. In some embodiments, some or all of the components included in the electrical device1800may be attached to one or more motherboards. In some embodiments, some or all of these components are fabricated onto a single system-on-a-chip (SoC) die.

Additionally, in various embodiments, the electrical device1800may not include one or more of the components illustrated inFIG. 12, but the electrical device1800may include interface circuitry for coupling to the one or more components. For example, the electrical device1800may not include a display device1806, but may include display device interface circuitry (e.g., a connector and driver circuitry) to which a display device1806may be coupled. In another set of examples, the electrical device1800may not include an audio input device1824or an audio output device1808, but may include audio input or output device interface circuitry (e.g., connectors and supporting circuitry) to which an audio input device1824or audio output device1808may be coupled.

The electrical device1800may include battery/power circuitry1814. The battery/power circuitry1814may include one or more energy storage devices (e.g., batteries or capacitors) and/or circuitry for coupling components of the electrical device1800to an energy source separate from the electrical device1800(e.g., AC line power).

The electrical device1800may include a display device1806(or corresponding interface circuitry, as discussed above). The display device1806may include any visual indicators, such as a heads-up display, a computer monitor, a projector, a touchscreen display, a liquid crystal display (LCD), a light-emitting diode display, or a flat panel display.

The electrical device1800may include an audio output device1808(or corresponding interface circuitry, as discussed above). The audio output device1808may include any device that generates an audible indicator, such as speakers, headsets, or earbuds.

The electrical device1800may include an audio input device1824(or corresponding interface circuitry, as discussed above). The audio input device1824may include any device that generates a signal representative of a sound, such as microphones, microphone arrays, or digital instruments (e.g., instruments having a musical instrument digital interface (MIDI) output).

The electrical device1800may include a GPS device1818(or corresponding interface circuitry, as discussed above). The GPS device1818may be in communication with a satellite-based system and may receive a location of the electrical device1800, as known in the art.

The electrical device1800may include another output device1810(or corresponding interface circuitry, as discussed above). Examples of the other output device1810may include an audio codec, a video codec, a printer, a wired or wireless transmitter for providing information to other devices, or an additional storage device.

EXAMPLES OF VARIOUS EMBODIMENTS

Example 1 includes a microelectronic package comprising: a die; a package substrate coupled with the die, wherein the package substrate includes: a signal line in a first layer of the package substrate, wherein the signal line is communicatively coupled with the die, and is further to convey data signals to and from the die; a conductive line in a second layer of the package substrate; and a diode communicatively coupled with the signal line and the conductive line.

Example 2 includes the microelectronic package of example 1, wherein the diode is to allow for charge to pass between the signal line and the conductive line based on a voltage threshold related to a voltage difference between the signal line and the conductive line.

Example 3 includes the microelectronic package of example 1, wherein the conductive line is a power line or a ground line.

Example 4 includes the microelectronic package of any of examples 1-3, wherein the diode is a Schottky diode that includes a Schottky contact, an ohmic contact, and a semiconductor material positioned between the Schottky and the ohmic contact.

Example 5 includes the microelectronic package of example 4, wherein the semiconductor material is an oxide-based semiconductor material or an organic semiconductor material.

Example 6 includes the microelectronic package of any of examples 1-3, wherein the diode is a pn-junction diode that includes a first ohmic contact coupled with the signal line, a second ohmic contact coupled with the conductive line, an n-type semiconductor material, and a p-type semiconductor material, wherein the n-type and p-type semiconductor materials are between the first and second ohmic contacts.

Example 7 includes the microelectronic package of any of examples 1-3, wherein the package substrate further includes: a second conductive line in a third layer of the package substrate; and a second diode communicatively coupled with the signal line and the second conductive line, wherein the second diode is to allow for charge to pass between the signal line and the second conductive line based on a second voltage threshold related to a voltage difference between the signal line and the second conductive line.

Example 8 includes a package substrate for use in a microelectronic package, wherein the package substrate comprises: a signal line in a layer of the package substrate, wherein the signal line is to communicatively couple with a die, and is further to convey data signals to and from the die; a ground line in the layer of the package substrate; and a diode communicatively coupled with the signal line and the ground line.

Example 9 includes the package substrate of example 8, wherein the package substrate further comprises a power line in the layer of the package substrate, and a second diode communicatively coupled with the signal line and the power line.

Example 10 includes the package substrate of examples 8 or 9, wherein the diode includes a Schottky contact, an ohmic contact, and a semiconductor material coupled with the Schottky and ohmic contacts.

Example 11 includes the package substrate of example 10, wherein the ohmic contact is coupled with the signal line, and the Schottky contact is coupled with the ground line.

Example 12 includes the package substrate of example 10, wherein the semiconductor material is an oxide-based semiconductor material.

Example 13 includes the package substrate of example 12, wherein the semiconductor material is semiconductor material is gallium oxide (Ga2O3), indium oxide (In2O3), IGZO, or zinc oxide (ZnO2).

Example 14 includes the package substrate of example 10, wherein the Schottky contact is coupled with the signal line, and the ohmic contact is coupled with the ground line.

Example 15 includes the package substrate of example 10, wherein the semiconductor material is an organic-based semiconductor material.

Example 17 includes a method of forming a package substrate for use in a microelectronic package, wherein the method comprises: forming, in the package substrate, a signal line that is to carry a data signal to or from a die that is coupled with the package substrate; forming, in the package substrate, a conductive line; and forming, in the package substrate, an electrostatic discharge (ESD) protection structure that includes a diode communicatively coupled to the signal line and the conductive line.

Example 18 includes the method of example 17, further comprising: forming, in the package substrate, a second conductive line; and wherein forming the ESD protection structure includes forming, in the package substrate, a second diode communicatively coupled to the signal line and the second conductive line.

Example 19 includes the method of example 18, wherein forming the second conductive line includes forming the second conductive line in a same layer of the package substrate as the signal line.

Example 20 includes the method of example 18, wherein forming the second conductive line includes forming the second conductive line in a different layer of the package substrate than the signal line.

Example 21 includes an electronic device comprising: a logic; and a microelectronic package communicatively coupled with the logic, wherein the microelectronic package includes: a die coupled with a package substrate; a signal line in the package substrate, wherein the signal line is part of a signal path between the die and the logic; a conductive line in the package substrate; and a diode communicatively coupled with the signal line and the conductive line.

Example 22 includes the electronic device of example 21, wherein the diode is to become conductive based on a voltage difference between the signal line and the conductive line.

Example 23 includes the electronic device of examples 21 or 22, wherein the conductive line is a power line or a ground line.

Example 24 includes the electronic device of examples 21 or 22, wherein the diode is a Schottky diode.

The above description of illustrated embodiments, including what is described in the Abstract, is not intended to be exhaustive or limiting as to the precise forms disclosed. While specific implementations of, and examples for, various embodiments or concepts are described herein for illustrative purposes, various equivalent modifications may be possible, as those skilled in the relevant art will recognize. These modifications may be made in light of the above detailed description, the Abstract, the Figures, or the claims.