Semiconductor device and method for fabricating the same

A semiconductor device and a method for fabricating the same selectively forms a nitride layer having high tensile stress in an NMOS transistor area, to thereby form a strained-silicon structure in an NMOS channel region, whereby electron mobility is improved and drain current is increased. The semiconductor device includes an isolation region that, electrically isolates an N-type MOS transistor area from a P-type MOS transistor area, and a nitrade layer formed on an entire upper surface of a substrate, wherein the nitrade layer has silicon ions (Si+) selectively implanted in the P-type MOS transistor area.

This application claims the benefit of Korean Patent Application No. 10-2004-0116552, filed on Dec. 30, 2004, which is hereby incorporated by reference for all purposes as if fully set forth herein.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to semiconductor devices, and more particularly, to a semiconductor device and a method for fabricating the same, which prevents a decrease in the drain current of a metal-oxide-silicon transistor that is subject to short channel effects.

2. Discussion of the Related Art

A highly integrated semiconductor device includes a multitude of transistors formed on a semiconductor substrate, each having a finite channel length. Short channel effects, which destroy normal transistor operation as an electrical field is rapidly developed and applied to a channel region, are increasingly prevalent in more highly integrated semiconductor devices, which inherently have shorter channel lengths.

To prevent such deterioration of transistor characteristics, short channels effects should be minimized. Minimizing short channel effects may be achieved by performing an additional ion implantation step when forming a transistor having a lightly doped drain structure in which low-density source and drain regions are formed on either side of a gate before forming spacers on gate sidewalls. However, a decrease in the intensity of the electrical field, while minimizing the short channel effect, results in a rapid decrease in drain current.

SUMMARY OF THE INVENTION

Accordingly, the present invention is directed to a semiconductor device and a method for fabricating the same that substantially obviates one or more problems due to limitations and disadvantages of the related art.

An advantage of the present invention is to provide a semiconductor device and a method for fabricating the same, which prevents a decrease in the drain current of a metal-oxide-silicon transistor that is subject to short channel effects.

To achieve these and other advantages and in accordance with the purpose of the present invention, as embodied and broadly described, a semiconductor device includes an isolation region formed in a semiconductor substrate that electrically isolates an N-type MOS transistor area from a P-type MOS transistor area, and a nitride layer formed on an entire upper surface of the semiconductor substrate, wherein the nitride layer has silicon ions (Si+) selectively implanted in the P-type MOS transistor area.

According to another aspect of the present invention, a semiconductor device includes an isolation region formed in a semiconductor substrate defining a plurality of active regions, a plurality of gates formed on the substrate of the plurality of active regions, a plurality of source/drain regions formed in the substrate corresponding to both sides of each of the plurality of gates, a silicide layer formed on an upper surface of each of the plurality of gates and the plurality of source/drain regions, and a nitride layer formed on an entire upper surface of the substrate.

According to another aspect of the present invention, a method for fabricating a semiconductor device includes forming an isolation region by etching a predetermined portion of a semiconductor substrate and filling the predetermined portion with an insulating material, forming a gate by patterning a gate oxide layer and a gate electrode layer on the semiconductor substrate, forming source/drain regions of a lightly doped drain structure at both sides of the gate by implanting impurity ions into the semiconductor substrate at a high density and at a low density, selectively forming a silicide layer on the gate and the source/drain regions, and forming a nitride layer on an entire upper surface of the semiconductor substrate.

DETAILED DESCRIPTION OF THE INVENTION

Reference will now be made in detail to exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Wherever possible, like reference designations will be used throughout the drawings to refer to the same or similar parts.

FIGS. 1A-1Ccross-sectional views of a semiconductor device and respectively illustrate sequential steps of a method for fabricating a semiconductor device according to the present invention.

Referring toFIG. 1A, a predetermined portion of a semiconductor substrate11is etched to form a trench. The trench is filled with an insulating material to form an isolation region12defining an active region of a semiconductor device. The isolation region12is a shallow-trench isolation (STI) region generally applied to a highly integrated semiconductor device. The active area will include a P-type metal-oxide-silicon (PMOS) transistor to be formed in the PMOS area and an N-type metal-oxide-silicon (NMOS) transistor to be formed in the NMOS area. A gate oxide layer and a gate electrode layer are successively formed on an entire upper surface of the semiconductor substrate11including the isolation region12to cover both the PMOS and NMOS areas. The gate oxide and gate electrode layers are patterned to form a gate electrode structure comprising a gate oxide13, disposed under a gate electrode14for each of a PMOS transistor and an NMOS transistor. Using the gate electrode structures as an ion implantation mask, impurity ions are implanted at a low density to form lightly doped source/drain regions15in a surface of the semiconductor substrate11. Source/drain regions are thus disposed on either side of both gates, i.e., the respective gates of the PMOS and NMOS transistors. The impurities forming the source/drain regions of the two transistor types have opposite conductivities. Ions of a first conductivity form the source/drain regions of the PMOS transistor and ions of a second conductivity form the source/drain regions of the NMOS transistor. Separate successive ion implantation steps are performed. That is, an ion implantation step is first performed in either the PMOS area or NMOS area, and then another ion implantation step is performed in the other of the PMOS area or NMOS area. Spacers16are then formed on the sidewalls of the respective gates of the PMOS and NMOS transistors. The spacers16are used as an ion implantation mask when impurity ions are again implanted into the semiconductor substrate11, but at a high density this time, to form heavily doped source/drain regions17adjacent the lightly doped source/drain regions15. A silicide layer (not shown) is selectively formed on upper surfaces of the gates and source/drain regions of the PMOS and NMOS transistors, and a nitride layer18is formed to a thickness of approximately 1,000 to 3,000 Å by a thermal chemical vapor deposition over the entire resulting structure. Since the nitride layer18has a high tensile stress, a strained-silicon structure is formed in a channel region below the gate oxide layer13.

Referring toFIG. 1B, a layer of photoresist is formed on the entire upper surface of the semiconductor substrate11. The photoresist is treated with exposure and development to selectively remove the photoresist from the PMOS area, to thereby form a photoresist pattern PR11, which exposes the nitride layer18of the PMOS area where silicon ions (Si+) may be implanted at energy of approximately 20 to 130 KeV to a concentration of approximately 1×1014to 1×1015ions/cm2. This implantation enables a decrease in the tensile stress of the nitride layer18formed in the PMOS area. Since the stressed nitride layer remains in the NMOS area, the strained-silicon structure remains in the channel region of the NMOS transistor. Thus, a stressed nitride layer can be selectively formed in the NMOS area.

Referring toFIG. 1C, the photoresist pattern PR11is removed from the NMOS area. Fabrication of the semiconductor device may be completed by general processing.

Accordingly, in the semiconductor device and the method for fabricating the same according to the present invention, since a nitride layer having a high tensile stress can be selectively formed in the NMOS area, the strained-silicon structure is formed in the channel region of the NMOS transistor. Thus, it is possible to improve electron mobility and enable higher drain currents in the NMOS transistor.