Electronic device and electronic system including the same

An electronic device includes a control logic portion suitable for generating a hold control signal based on a count enable signal, and a counting portion suitable for performing a counting operation while a latch operation stops during a counting section and performing the latch operation while the counting operation stops during a holding section based on the hold control signal and a counting clock signal.

CROSS-REFERENCE TO RELATED APPLICATIONS

The present application claims priority of Korean Patent Application No. 10-2014-0098096, filed on Jul. 31, 2014, which is incorporated herein by reference in its entirety.

BACKGROUND

Various embodiments of the present invention relate to a semiconductor design technology and, more particularly, to an electronic device supporting a counting operation and an electronic system including the same.

2. Description of the Related Art

Counting circuits may be used for various electronic devices to convert physical parameters, such as light intensity, sound intensity or time, into digital signals.

For example, a complementary metal oxide semiconductor (CMOS) image sensor acquires an image using semiconductors that respond to incident light, analog-to-digital converters (ADC) to convert analog signals (i.e., a pixel signal) outputted from a pixel array into digital signals. An ADC may include a counting circuit that performs counting operations using a clock signal.

The operating speed and power consumption of the counting circuit have a direct influence on the performance of a device or system including the counting circuit.

For example, the number of counting circuits included in the CMOS image sensor may increase depending on the resolution of the CMOS image sensor. As the number of counting circuits increases, the operating speed and power consumption of the counting circuits may become an important factor in determining overall performance of the CMOS image sensor.

SUMMARY

Various embodiments of the present invention are directed to an electronic device appropriate for a high-speed counting operation and an electronic system including the electronic device.

In accordance with an embodiment of the present invention, an electronic device includes: a first portion suitable for generating a hold control signal based on a count enable signal; and a second portion suitable for performing a counting operation while a latch operation stops during a counting section and performing the latch operation while the counting operation stops during a holding section based on the hold control signal and a counting clock signal.

The second portion may include a plurality of division blocks suitable for generating a plurality of division clock signals divided at respectively predetermined division ratios as compared with the counting clock signal during the counting section and latching the division clock signals during the holding section based on the counting clock signal or one among the division clock signals and the hold control signal.

The division blocks may include a plurality of first gating units suitable for outputting a plurality of complementary division signals based on the counting clock signal or one among the division clock signals; a plurality of first inversion units suitable for inverting a plurality of first output signals outputted from the first gating units; a plurality of second inversion units suitable for inverting a plurality of first inversion signals outputted from the first inversion units and feeding back the inverted first inversion signals to the first inversion units; a plurality of second gating units suitable for selectively coupling the first inversion units and the second inversion units with each other based on the hold control signal; a plurality of third gating units suitable for outputting the first inversion signals based on an inversion signal of the counting clock signal or an inversion signal among the division clock signals; a plurality of third inversion units suitable for inverting a plurality of second output signals outputted from the third gating units and generating the division clock signals; a plurality of fourth inversion units suitable for inverting the division clock signals and feeding back the inverted division clock signals to the third inversion units; and a plurality of fourth gating units suitable for selectively coupling the third inversion units and the fourth inversion units with each other based on the hold control signal.

The second gating units may be formed between input terminals of the first inversion units and output terminals of the second inversion units and continuously decouple the first inversion units and the second inversion units from each other during the counting section and continuously couple the first inversion units and the second inversion units with each other during the holding section, and the fourth gating units may be formed between input terminals of the third inversion units and output terminals of the fourth inversion units and continuously decouple the third inversion units and the fourth inversion units from each other during the counting section and continuously couple the third inversion units and the fourth inversion units with each other during the holding section.

The division blocks may include a plurality of first gating units suitable for outputting a plurality of complementary division signals based on the counting clock signal or one among the division clock signals; a plurality of first inversion units suitable for inverting a plurality of first output signals outputted from the first gating units; a plurality of second inversion units suitable for inverting a plurality of first inversion signals outputted from the first inversion units based on the hold control signal and feeding back the inverted first inversion signals to the first inversion units; a plurality of second gating units suitable for outputting the first inversion signals based on an inversion signal of the counting clock signal or an inversion signal among the division clock signals; a plurality of third inversion units suitable for inverting a plurality of second output signals outputted from the second gating units and generating the division clock signals; and a plurality of fourth inversion units suitable for inverting the division clock signals based on the hold control signal and feeding back the inverted division clock signals to the third inversion units.

Each of the second inversion units and the fourth inversion units may include a gated inverter that is disabled during the counting section and enabled during the holding section based on the hold control signal.

In accordance with an embodiment of the present invention, an electronic device includes: a control logic portion suitable for generating a hold control signal and a counting clock signal based on a count enable signal and a source clock signal; a lower-level bit counting portion suitable for performing a counting operation while a latch operation stops during a counting section and performing the latch operation while the counting operation stops during a holding section based on the hold control signal and the counting clock signal; and an upper-level bit counting portion suitable for performing the counting operation while the latch operation selectively stops during the counting section and performing the latch operation while the counting operation stops during the holding section based on an uppermost lower-level bit signal among one or more lower-level bit signals outputted from the lower-level bits counting portion.

The control logic portion may include a clock sampling block suitable for generating the counting clock signal toggling during the counting section based on the count enable signal and the source clock signal; and an inversion block suitable for inverting the count enable signal to generate the hold control signal.

The lower-level bit counting portion may include a plurality of lower-level bit division blocks suitable for generating a plurality of lower-level bit signals divided at respectively predetermined division ratios as compared with the counting clock signal during the counting section and latching the lower-level bit signals during the holding section based on the counting clock signal or one among the lower-level bit signals and the hold control signal.

The lower-level bit division blocks may include a plurality of first gating units suitable for receiving a plurality of complementary lower-level bit signals based on the counting clock signal or one among the lower-level bit signals; a plurality of first inversion units suitable for inverting a plurality of first output signals outputted from the first gating units; a plurality of second inversion units suitable for inverting a plurality of first inversion signals outputted from the first inversion units and feeding back the inverted first inversion signals to the first inversion units; a plurality of second gating units suitable for selectively coupling the first inversion units and the second inversion units with each other based on the hold control signal; a plurality of third gating units suitable for outputting the first inversion signals based on an inversion signal of the counting clock signal or an inversion signal among the lower-level bit signals; a plurality of third inversion units suitable for inverting a plurality of second output signals outputted from the third gating units and generating the lower-level bit signals; a plurality of fourth inversion units suitable for inverting the lower-level bit signals and feeding back the inverted lower-level bit signals to the third inversion units; and a plurality of fourth gating units suitable for selectively coupling the third inversion units and the fourth inversion units with each other based on the hold control signal.

The second gating units may be formed between input terminals of the first inversion units and output terminals of the second inversion units and continuously decouple the first inversion units and the second inversion units from each other during the counting section and continuously couple the first inversion units and the second inversion units with each other during the holding section, and the fourth gating units may be formed between input terminals of the third inversion units and output terminals of the fourth inversion units and continuously decouple the third inversion units and the fourth inversion units from each other during the counting section and continuously couple the third inversion units and the fourth inversion units with each other during the holding section.

The lower-level bit division blocks may include a plurality of first gating units suitable for receiving a plurality of complementary lower-level bit signals based on the counting clock signal or one among the lower-level bit signals; a plurality of first inversion units suitable for inverting a plurality of first output signals outputted from the first gating units; a plurality of second inversion units suitable for inverting a plurality of first inversion signals outputted from the first inversion units based on the hold control signal and feeding back the inverted first inversion signals to the first inversion units; a plurality of second gating units suitable for outputting the first inversion signals based on an inversion signal of the counting clock signal or an inversion signal among the lower-level bit signals; a plurality of third inversion units suitable for inverting a plurality of second output signals outputted from the second gating units and generating the lower-level bit signals; and a plurality of fourth inversion units suitable for inverting the lower-level bit signals based on the hold control signal and feeding back the inverted lower-level bit signals to the third inversion units.

Each of the second inversion units and the fourth inversion units may include a gated inverter that is disabled during the counting section and enabled during the holding section based on the hold control signal.

The upper-level bit counting portion may include a plurality of upper-level bit division blocks suitable for generating a plurality of upper-level bit signals divided at respectively predetermined division ratios as compared with the uppermost lower-level bit signal during the counting section and latching the upper-level bit signals during the holding section based on the uppermost lower-level bit signal or one among the upper-level bit signals.

The upper-level bit division blocks may include a plurality of first gating units suitable for receiving a plurality of complementary upper-level bit signals based on the uppermost lower-level bit signal or one among the upper-level bit signals; a plurality of first inversion units suitable for inverting a plurality of first output signals outputted from the first gating units; a plurality of second inversion units suitable for inverting a plurality of first inversion signals outputted from the first inversion units and feeding back the inverted first inversion signals to the first inversion units; a plurality of second gating units suitable for selectively coupling the first inversion units and the second inversion units with each other based on an inversion signal of the uppermost lower-level bit signal or an inversion signal of one among the upper-level bit signals; a plurality of third gating units suitable for outputting the first inversion signals based on the inversion signal of the uppermost lower-level bit signal or the inversion signal of one among the upper-level bit signals; a plurality of third inversion units suitable for inverting a plurality of second output signals outputted from the third gating units and generating the upper-level bit signals; a plurality of fourth inversion units suitable for inverting the upper-level bit signals and feeding back the inverted upper-level bit signals to the third inversion units; and a plurality of fourth gating units suitable for selectively coupling the third inversion units and the fourth inversion units with each other based on the uppermost lower-level bit signal or one among the upper-level bit signals.

The upper-level bit division blocks may include a plurality of first gating units suitable for receiving a plurality of complementary upper-level bit signals based on the uppermost lower-level bit signal or one among the upper-level bit signals; a plurality of first inversion units suitable for inverting a plurality of first output signals outputted from the first gating units; a plurality of second inversion units suitable for inverting a plurality of first inversion signals outputted from the first inversion units and feeding back the inverted first inversion signals to the first inversion units based on an inversion signal of the uppermost lower-level bit signal or an inversion signal of one among the upper-level bit signals; a plurality of second gating units suitable for outputting the first inversion signals based on the inversion signal of the uppermost lower-level bit signal or the inversion signal of one among the upper-level bit signals; a plurality of third inversion units suitable for inverting a plurality of second output signals outputted from the second gating units and generating the upper-level bit signals; and a plurality of fourth inversion units suitable for inverting the upper-level bit signals and feeding back the inverted upper-level bit signals to the third inversion units based on the uppermost lower-level bit signal or one among the upper-level bit signals.

In accordance with an embodiment of the present invention, an electronic system includes: a control device suitable for generating a control signal based on an information signal corresponding to an operation frequency; and an electronic device suitable for generating a plurality of lower-level bit signals by performing a counting operation while a latch operation stops during a counting section based on the control signal or generating some of the lower-level bit signals by performing the counting operation while the latch operation stops during the counting section based on the control signal and generating the other lower-level bit signals by performing the counting operation while the latch operation selectively stops during the counting section.

The electronic device may perform the latch operation while the counting operation stops during a holding section and alternates the counting section and the holding section.

The electronic device may include a frequency detection portion suitable for generating the information signal based on a source clock signal; a logic control portion suitable for generating a hold control signal and a counting clock signal based on the source clock signal and a count enable signal; a plurality of selection portions suitable for selecting one among respectively predetermined signals including the counting clock signal or one among the lower-level bit signals and the hold control signal and generating a plurality of selection signals; and a plurality of lower-level bit division portions suitable for generating the lower-level bit signals divided at respectively predetermined division ratios as compared with the counting clock signal during the counting section and latching the lower-level bit signals during the holding section based on the counting clock signal or one among the lower-level bit signals and one among the selection signals.

The electronic device may further include a plurality of upper-level bit division portions suitable for generating the upper-level bit signals divided at respectively predetermined division ratios as compared with the counting clock signal during the counting section and latching the upper-level bit signals during the holding section based on an uppermost lower-level bit signal among the lower-level bit signals or one among the upper-level bit signals.

DETAILED DESCRIPTION

It is also noted that in this specification, “connected/coupled” refers to one component not only directly coupling another component but also indirectly coupling another component through an intermediate component. In addition, a singular form may include a plural form as long as it is not specifically mentioned in a sentence. It should be readily understood that the meaning of “on” and “over” in the present disclosure should be interpreted in the broadest manner such that “on” means not only “directly on” but also “on” something with an intermediate feature(s) or a layer(s) therebetween, and that “over” means not only directly on top but also on top of something with an intermediate feature(s) or a layer(s) therebetween. When a first layer is referred to as being “on” a second layer or “on” a substrate, it not only refers where the first layer is formed directly on the second layer or the substrate but also to where a third layer exists between the first layer and the second layer or the substrate.

FIG. 1is a block diagram illustrating an electronic system100in accordance with an embodiment of the present invention.

Referring toFIG. 1, the electronic system100may include a control device110and an electronic device120.

The control device110may control general operations of the electronic device120. The control device110may transmit a source clock signal CLK and an initialization signal RST. For example, the control device110may include a central processing unit (CPU).

The electronic device120may perform a predetermined operation under the control of the control device110. For example, the electronic device120may include a memory device such as a dynamic random access memory (DRAM) device or an image sensing device such as a CMOS image sensor. The electronic device120may include a counting circuit, and hereafter the description will be focused on the counting circuit.

FIG. 2is a block diagram illustrating a counting circuit120A in accordance with an embodiment of the present invention, which may be included in the electronic device120shown inFIG. 1. Referring toFIG. 2, the counting circuit120A may include a control logic portion121, a lower-level bit counting portion123, and an upper-level bit counting portion125. From another point of view, the counting circuit120A may include first and second portions. The control logic portion121may correspond to the first portion, and the lower-level bit counting portion123and the upper-level bit counting portion125may correspond to the second portion (i.e., a counting portion). Here, the second portion may perform a counting operation while a latch operation stops during a counting section and performs the latch operation while the counting operation stops during a holding section. Furthermore, the second portion may include a plurality of division blocks that generate a plurality of division signals divided at respectively predetermined division ratios and latch the division signals during the holding section.

The control logic portion121generates a hold control signal HOLD_IN and a counting clock signal ICLK in response to a count enable signal PULSE_IN and the source clock signal CLK. The lower-level bit counting portion123performs a counting operation while a latch operation stops during a counting section and the latch operation while the counting operation stops during a holding section in response to the hold control signal HOLD_IN, the counting clock signal ICLK and the initialization signal RST. The upper-level bit counting portion125performs the counting operation while the latch operation selectively stops during the counting section and the latch operation while the counting operation stops during the holding section in response to an uppermost lower-level bit signal D[m] among a plurality of lower-level bit signals D[0] to D[m] outputted from the lower-level bit counting portion123.

Herein, the source clock signal CLK and the initialization signal RST may be external signals inputted from the control device110and internal signals generated inside the electronic device120. The count enable signal PULSE_IN may be an internal signal generated inside the electronic device120. For example, an image sensing device includes comparators that may compare a ramp signal with a pixel signal, outputted from a pixel array, and internally generate the count enable signal PULSE_IN corresponding to the comparison result.

FIG. 3is a detailed diagram of the control logic portion121shown inFIG. 2.

Referring toFIG. 3, the control logic portion121may include a clock sampling block (or a clock gating block)121_1and an inversion block121_3. The clock sampling block121_1generates the counting clock signal ICLK toggling during the counting section in response to the source clock signal CLK and the count enable signal PULSE_IN. The inversion block121_3generates the hold control signal HOLD_IN by inverting the count enable signal PULSE_IN. For example, the clock sampling block121_1may include an AND gate, and the inversion block121_3may include an inverter.

FIG. 4is a detailed diagram of the lower-level bit counting portion123shown inFIG. 2.

Referring toFIG. 4, the lower-level bit counting portion123may include a plurality of lower-level bit division blocks123_1to123_m+1. The lower-level bit division blocks123_1to123_m+1 generate the lower-level bit signals D[0] to D[m] divided at predetermined division ratios, respectively, as compared with the counting clock signal ICLK during the counting section based on the counting clock signal ICLK or one among the lower-level bit signals D[0] to D[m] and the hold control signal HOLD_IN and latch the lower-level bit signals D[0] to D[m] during the holding section.

For example, the lower-level bit division blocks123_1to123_m+1 may be coupled with each other in series and include D-flip flops, individually. The first lower-level bit division block123_1 among the lower-level bit division blocks123_1to123_m+1 may divide the counting clock signal ICLK by 2 and output the divided counting clock signal ICLK, and the other lower-level bit division blocks123_2to123_m+1 among the lower-level bit division blocks123_1to123_m+1 may divide the lower-level bit signals D[0] to D[m−1] outputted from the former lower-level bit division blocks123_1to123_mby 2 and output the divided lower-level bit signals D[0] to D[m−1]. As a result, the first lower-level bit signal D[0] may be a division signal divided by 2 as compared with the counting clock signal ICLK, and the second lower-level bit signal D[1] may be a division signal divided by 4 as compared with the counting clock signal ICLK, and the third lower-level bit signal D[2] may be a division signal divided by 8 as compared with the counting clock signal ICLK. Since the other lower-level bit signals D[3] to D[m] are predictable, detailed descriptions thereon are omitted herein.

FIGS. 5A and 5Bare detailed diagrams of a portion of the first lower-level bit division block123_1shown inFIG. 4.

Referring toFIG. 5A, the first lower-level bit division block123_1may include a first gating unit TG1, a first inversion unit INV1, a second inversion unit INV2, a second gating unit TG2, a third gating unit TG3, a third inversion unit INV3, a fourth inversion unit INV4, and a fourth gating unit TG4. The first gating unit TG1receives a complementary first lower-level bit signal Db[0], which is in an inverse relationship with the first lower-level bit signal D[0], based on the counting clock signal ICLK. The first inversion unit INV1inverts a first output signal outputted from the first gating unit TG1. The second inversion unit INV2inverts a first inversion signal outputted from the first inversion unit INV1and feeds back the inverted first inversion signal to the first inversion unit INV1. The second gating unit TG2selectively couples the first inversion unit INV1and the second inversion unit INV2with each other based on the hold control signal HOLD_IN. The third gating unit TG3outputs the first inversion signal based on a complementary counting clock signal ICLKb, which is an inversion signal of the counting clock signal ICLK. The third inversion unit INV3inverts a second output signal outputted from the third gating unit TG3and generates the first lower-level bit signal D[0]. The fourth inversion unit INV4inverts the first lower-level bit signal D[0] and feeds back the inverted first lower-level bit signal D[0] to the third inversion unit INV3. The fourth gating unit TG4selectively couples the third inversion unit INV3and the fourth inversion unit INV4with each other based on the hold control signal HOLD_IN.

Herein, the second gating unit TG2may be formed between an input terminal of the first inversion unit INV1and an output terminal of the second inversion unit INV2. The second gating unit TG2may continuously decouple the input terminal of the first inversion unit INV1from the output terminal of the second inversion unit INV2during the counting section and continuously couple the input terminal of the first inversion unit INV1with the output terminal of the second inversion unit INV2during the holding section.

The first inversion unit INV1and the second inversion unit INV2may be electrically decoupled from each other by the second gating unit TG2during the counting section. Then, a latch operation performed by the first inversion unit INV1and the second inversion unit INV2may stop. Also, the first inversion unit INV1and the second inversion unit INV2may be electrically coupled with each other by the second gating unit TG2during the holding section. Then, the latch operation may be performed by the first inversion unit INV1and the second inversion unit INV2.

The fourth gating unit TG4may be formed between an input terminal of the third inversion unit INV3and an output terminal of the fourth inversion unit INV4. The fourth gating unit TG4may electrically decouple the input terminal of the third inversion unit INV3from the output terminal of the fourth inversion unit INV4during the counting section and electrically couple the input terminal of the third inversion unit INV3with the output terminal of the fourth inversion unit INV4during the holding section.

The third inversion unit INV3and the fourth inversion unit INV4may be electrically decoupled from each other by the fourth gating unit TG4during the counting section. Then, a latch operation performed by the third inversion unit INV3and the fourth inversion unit INV4may stop. Also, the third inversion unit INV3and the fourth inversion unit INV4may be electrically coupled with each other by the fourth gating unit TG4during the holding section. Then, the latch operation may be performed by the third inversion unit INV3and the fourth inversion unit INV4.

Herein, the complementary first lower-level bit signal Db[0] may include the second output signal outputted from the third gating unit TG3or a inverted signal of the first lower-level bit signal D[0].

Since the other lower-level bit division blocks123_2to123_m+1, except for the first lower-level bit division block123_1, among the lower-level bit division blocks123_1to123_m+1 may have the same structure as the first lower-level bit division block123_1, a detailed description thereon is omitted herein. However, the other lower-level bit division blocks123_2to123_m+1 may receive the lower-level bit signals D[0] to D[m−1] outputted from the former lower-level bit division blocks123_1to123_minstead of the counting clock signal ICLK, respectively.

Referring toFIG. 5B, the first lower-level bit division block123_1may include a first gating unit TG11, a first inversion unit INV11, a first gated inversion unit GINV11, a second gating unit TG12, a second inversion unit INV12, and a second gated inversion unit GINV12. The first gating unit TG11receives a complementary first lower-level bit signal Db[0], which is in an inverse relationship with the first lower-level bit signal D[0], based on the counting clock signal ICLK. The first inversion unit INV11inverts a first output signal outputted from the first gating unit TG11. The first gated inversion unit GINV11inverts a first inversion signal outputted from the first inversion unit INV11based on the hold control signal HOLD_IN and feeds back the inverted first inversion signal to the first inversion unit INV11. The second gating unit TG12outputs the first inversion signal based on a complementary counting clock signal ICLKb which is an inversion signal of the counting clock signal ICLK. The second inversion unit INV12inverts a second output signal outputted from the second gating unit TG12and generates the first lower-level bit signal D[0]. The second gated inversion unit GINV12inverts the first lower-level bit signal D[0] based on the hold control signal HOLD_IN and feeds back the inverted first lower-level bit signal D[0] to the second inversion unit INV12.

Herein, the first and second gated inversion units GINV11and GINV12may be disabled during the counting section and enabled during the holding section based on the hold control signal HOLD_IN. For example, each of the first and second gated inversion units GINV11and GINV12may include a gated inverter that is controlled based on the hold control signal HOLD_IN.

Herein, the complementary first lower-level bit signal Db[0] may include the second output signal outputted from the second gating unit TG12or a inverted signal of the first lower-level bit signal D[0].

Since the other lower-level bit division blocks123_2to123_m+1, except for the first lower-level bit division block123_1, among the lower-level bit division blocks123_1to123_m+1 may have the same structure as the first lower-level bit division block123_1, a detailed description thereon is omitted herein. However, the other lower-level bit division blocks123_2to123_m+1 may receive the lower-level bit signals D[0] to D[m−1] outputted from the former lower-level bit division blocks123_1to123_minstead of the counting clock signal ICLK, respectively.

FIG. 6is a detailed diagram of the upper-level bit counting portion125shown inFIG. 2.

Referring toFIG. 6, the upper-level bit counting portion125may include a plurality of upper-level bit division blocks125_1to125_n−m. The upper-level bit division blocks125_1to125_n−mgenerate a plurality of upper-level bit signals D[m+1] to D[n] divided at predetermined division ratios, respectively, as compared with the uppermost lower-level bit signal D[m] during the counting section and latch the upper-level bit signals D[m+1] to D[n] during the holding section based on the uppermost lower-level bit signal D[m] among the lower-level bit signals D[0] to D[m] or one among the upper-level bit signals D[m+1] to D[n].

For example, the upper-level bit division blocks125_1to125_n−mmay be coupled with each other in series and include a D-flip flop, respectively. The first upper-level bit division block125_1 among the upper-level bit division blocks125_1to125_n−mmay divide the uppermost lower-level bit signal D[m] by 2 and output the divided uppermost lower-level bit signal D[m], and the other upper-level bit division blocks125_2to125_n−mamong the upper-level bit division blocks125_1to125_n−mmay divide the upper-level bit signals D[m+1] to D[n−1] outputted from the former upper-level bit division blocks125_1to125_n−m−1 by 2 and output the divided upper-level bit signals D[m+1] to D[n−1]. As a result, the first upper-level bit signal D[m+1] may be a division signal divided by 2 as compared with the uppermost lower-level bit signal D[m], and the second upper-level bit signal D[m+2] may be a division signal divided by 4 as compared with the uppermost lower-level bit signal D[m], and the third upper-level bi signal D[m+3] may be a division signal divided by 8 as compared with the uppermost lower-level bit signal D[m]. Since the other upper-level bit signals D[m+4] to D[n] are predictable, a detailed description thereon is omitted herein.

FIGS. 7A and 7Bare detailed diagrams of a portion of the first upper-level bit division block125_1shown inFIG. 6.

Referring toFIG. 7A, the first upper-level bit division block125_1may include a first gating unit TG21, a first inversion unit INV21, a second inversion unit INV22, a second gating unit TG22, a third gating unit TG23, a third inversion unit INV23, a fourth inversion unit INV24, and a fourth gating unit TG24. The first gating unit TG21receives a complementary first upper-level bit signal Db[m+1], which is in an inverse relationship with the first upper-level bit signal D[m+1], based on the uppermost lower-level bit signal D[m]. The first inversion unit INV21inverts a first output signal outputted from the first gating unit TG21. The second inversion unit INV22inverts a first inversion signal outputted from the first inversion unit INV21and feeds back the inverted first inversion signal to the first inversion unit INV21. The second gating unit TG2selectively couples the first inversion unit INV21and the second inversion unit INV22with each other based on a complementary uppermost lower-level bit signal Db[m], which is in inverse relationship with the uppermost lower-level bit signal D[m]. The third gating unit TG23outputs the first inversion signal based on the complementary uppermost lower-level bit signal Db[m]. The third inversion unit INV23inverts a second output signal outputted from the third gating unit TG23and generates the first upper-level bit signal D[m+1]. The fourth inversion unit INV24inverts the first upper-level bit signal D[m+1] and feeds back the inverted first upper-level bit signal D[m+1] to the third inversion unit INV23. The fourth gating unit TG24selectively couples the third inversion unit INV23and the fourth inversion unit INV24with each other based on the uppermost lower-level bit signal D[m].

Herein, the second gating unit TG22may be formed between an input terminal of the first inversion unit INV21and an output terminal of the second inversion unit INV22. The second gating unit TG22may selectively couple the input terminal of the first inversion unit INV21with the output terminal of the second inversion unit INV22during the counting section and continuously couple the input terminal of the first inversion unit INV21with the output terminal of the second inversion unit INV22during the holding section.

The first inversion unit INV21and the second inversion unit INV22may be selectively coupled with each other by the second gating unit TG22during the counting section. Then, a latch operation performed by the first inversion unit INV21and the second inversion unit INV22may repeatedly stop and be performed during the counting section. Also, the first inversion unit INV21and the second inversion unit INV22may be continuously coupled with each other by the second gating unit TG22during the holding section. Then, the latch operation may be continuously performed by the first inversion unit INV21and the second inversion unit INV22during the holding section.

The fourth gating unit TG24may be formed between an input terminal of the third inversion unit INV23and an output terminal of the fourth inversion unit INV24. The fourth gating unit TG24may selectively couple the input terminal of the third inversion unit INV23with the output terminal of the fourth inversion unit INV24during the counting section and continuously decouple the input terminal of the third inversion unit INV23from the output terminal of the fourth inversion unit INV24during the holding section.

The third inversion unit INV23and the fourth inversion unit INV24may be selectively coupled with each other by the fourth gating unit TG24during the counting section. Then, a latch operation performed by the third inversion unit INV23and the fourth inversion unit INV24may repeatedly stop and be performed during the counting section. Also, the third inversion unit INV23and the fourth inversion unit INV24may be continuously decoupled from each other by the fourth gating unit TG24during the holding section. Then, the latch operation by the third inversion unit INV23and the fourth inversion unit INV24may continuously stop during the holding section.

Herein, the complementary first upper-level bit signal Db[m+1] may include the second output signal outputted from the third gating unit TG23or a inverted signal of the first upper-level bit signal D[m+1].

Since the other upper-level bit division blocks125_2to125_n−m, except for the first upper-level bit division block125_1, among the upper-level bit division blocks125_1to125_mmay have the same structure as the first upper-level bit division block125_1, a detailed description thereon is omitted herein. However, the other upper-level bit division blocks125_2to125_n−mmay receive the upper-level bit signals D[m+1] to D[n−1] outputted from the former upper-level bit division blocks125_1to125_n−minstead of the uppermost lower-level bit signal D[m], respectively.

Referring toFIG. 7B, the first upper-level bit division block125_1may include a first gating unit TG31, a first inversion unit INV31, a first gated inversion unit GINV31, a second gating unit TG32, a second inversion unit INV32, and a second gated inversion unit GINV32. The first gating unit TG31receives a complementary first upper-level bit signal Db[m+1] based on the uppermost lower-level bit signal D[m]. The first inversion unit INV31inverts a first output signal outputted from the first gating unit TG31. The first gated inversion unit GINV31inverts a first inversion signal outputted from the first inversion unit INV31based on the complementary uppermost lower-level bit signal Db[m] and feeds back the inverted first inversion signal to the first inversion unit INV31. The second gating unit TG32outputs the first inversion signal based on the complementary uppermost lower-level bit signal Db[m]. The second inversion unit INV32inverts a second output signal outputted from the second gating unit TG32and generates the first upper-level bit signal D[m+1]. The second gated inversion unit GINV32inverts the first upper-level bit signal D[m+1] based on the uppermost lower-level bit signal D[m] and feeds back the inverted first upper-level bit signal D[m+1] to the second inversion unit INV32.

The first gated inversion unit GINV31may be repeatedly disabled and enabled during the counting section and continuously enabled during the holding section based on the complementary uppermost lower-level bit signal Db[m]. The second gated inversion unit GINV32may be repeatedly disabled and enabled during the counting section and continuously disabled during the holding section based on the uppermost lower-level bit signal D[m]. The first and second gated inversion units GINV31and GINV32may be reversely disabled and enabled during the counting section.

For example, each of the first and second gated inversion units GINV31and GINV32may include a gated inverter that is controlled based on the uppermost lower-level bit signal D[m] and/or the complementary uppermost lower-level bit signal Db[m].

Herein, the complementary first upper-level bit signal Db[m+1] may include the second output signal outputted from the second gating unit TG32or a inverted signal of the first upper-level bit signal D[m+1].

Since the other upper-level bit division blocks125_2to125_n−mexcept for the first upper-level bit division block125_1 among the upper-level bit division blocks125_1to125_mmay have the same structure as the first upper-level bit division block125_1, a detailed description thereon is omitted herein. However, the other upper-level bit division blocks125_2to125_n−mmay receive the upper-level bit signals D[m+1] to D[n−1] outputted from the former upper-level bit division blocks125_1to125_n−minstead of the uppermost lower-level bit signal D[m], respectively.

FIG. 8is a timing diagram for describing the operation of the counting circuit121A shown inFIG. 1.

For the sake of convenience in description, the lower-level bit signals D[0] to D[m] are described as first to fifth lower-level bit signals D[0] to D[4], and the upper-level bit signals D[m+1] to D[n] are described as first to fifth upper-level bit signals D[5] to D[9].

Referring toFIG. 8, the control logic portion121may generate the hold control signal HOLD_IN and the counting clock signal ICLK in response to the count enable signal PULSE_IN and the source clock signal CLK. For example, the control logic portion121may generate the hold control signal HOLD_IN by inverting the count enable signal PULSE_IN, and generate the counting clock signal ICLK by performing an AND operation on the count enable signal PULSE_IN and the source clock signal CLK. The counting clock signal ICLK may be fixed with a logic low level during a holding section HS where the count enable signal PULSE_IN is deactivated to a logic low level, and the counting clock signal ICLK may toggle and correspond to the source clock signal CLK during a counting section CS where the count enable signal PULSE_IN is activated to a logic high level.

The lower-level bit counting portion123and the upper-level bit counting portion125may be initialized in response to the initialization signal RST. For example, when the initialization signal RST is activated to a logic high level, the lower-level bit counting portion123may initialize the first to fifth lower-level bit signals D[0] to D[4] to a logic low level, and the upper-level bit counting portion125may initialize the first to fifth upper-level bit signals D[5] to D[9] to a logic low level. The first lower-level bit signal D[0] may be a least significant bit (LSB), and the fifth upper-level bit signal D[9] may be a most significant bit (MSB).

Under the above condition, when entering the counting section CS, the lower-level bit counting portion123may divide the counting clock signal ICLK to generate the first to fifth lower-level bit signals D[0] to D[4]. For example, the first lower-level bit division block123_1may divide the counting clock signal ICLK by 2 to generate the first lower-level bit signal D[0], and the second lower-level bit division block123_2may divide the first lower-level bit signal D[0] by 2 to generate the second lower-level bit signal D[1], the third lower-level bit division block123_3may divide the second lower-level bit signal D[1] by 2 to generate the third lower-level bit signal D[2], and the fourth lower-level bit division block123_4may divide the third lower-level bit signal D[2] by 2 to generate the fourth lower-level bit signal D[3], and the fifth lower-level bit division block123_5may divide the fourth lower-level bit signal D[3] by 2 to generate the fifth lower-level bit signal D[4].

The first to fifth lower-level bit division block123_1to123_5may generate the first to fifth lower-level bit signals D[0] to D[4] while the latch operation selectively stops during the counting section CS based on the hold control signal HOLD_IN.

For example, referring toFIG. 5A, since the second and fourth gating unit TG2and TG4, each included in the first to fifth lower-level bit division block123_1to123_5, may be disabled during the counting section CS, and then feedback paths each including the second and fourth inversion units INV2and INV4may electrically open, the latch operation by the first and second inversion units INV1and INV2and the latch operation by the third and fourth inversion units INV3and INV4may stop.

The first to fifth lower-level bit signals D[0] to D[4] may be generated although the latch operation stops since the floating state of latch nodes including the input terminals of the first and third inversion units INV1and INV3may be ignored as the signals for controlling the first and third gating units TG1and TG3, including the counting clock signal ICLK and the first to fourth lower-level bit signals D[0] to D[3], have high frequencies. For example, when the minimum floating time when the floating state may be ignored is approximately 20 ns, and the frequency of the counting clock signal ICLK is approximately 800 Mhz, the high frequency range may be from the counting clock signal ICLK, whose frequency is approximately 800 Mhz, to the fourth lower-level bit signal D[3], whose frequency is approximately 50 Mhz.

Therefore, since the lower-level bit counting portion123may stop performing the latch operation during counting section CS, the loading time taken for the latch operation and power consumption may be reduced.

Although not illustrated in the drawing, the upper-level bit counting portion125may divide the fifth lower-level bit signal D[4] to generate the first to fifth upper-level bit signals D[5] to D[9]. For example, the first upper-level bit division block125_1may divide the fifth lower-level bit signal D[4] by 2 to generate the first upper-level bit signal D[5], and the second upper-level bit division block125_2may divide the first upper-level bit signal D[5] by 2 to generate the second upper-level bit signal D[6], and the third upper-level bit division block125_3may divide the second upper-level bit signal D[6] by 2 to generate the third upper-level bit signal D[7], and the fourth upper-level bit division block125_4may divide the third upper-level bit signal D[7] by 2 to generate the fourth upper-level bit signal D[8], and the fifth upper-level bit division block125_5may divide the fourth upper-level bit signal D[8] by 2 to generate the fifth upper-level bit signal D[9].

The first to fifth upper-level bit division blocks125_1to125_5may generate the first to fifth upper-level bit signals D[5] to D[9] while the latch operation selectively stops during the counting section CS based on the fifth lower-level bit signal D[4] or one among the first to fourth upper-level bit signals D[5] to D[8].

For example, referring toFIG. 7A, since the second and fourth gating units TG22and TG24, each included in the first to fifth upper-level bit division blocks125_1to125_5, may be repeatedly disabled and enabled during the counting section CS, and then feedback paths each including the second and fourth inversion units INV22and INV4may repeatedly open and be closed, the latch operation by the first and second inversion units INV21and INV22and the latch operation by the third and fourth inversion units INV23and INV24may selectively stop. In other words, when the first gating unit TG21is enabled, and the third gating unit TG23is disabled, the latch operations by the first and second inversion units INV21and INV22may stop while the second gating unit TG22is disabled, and simultaneously the latch operations by the third and fourth inversion units INV23and INV24may be performed while the fourth gating unit TG24is enabled. In contrast, when the first gating unit TG21is disabled, and the third gating unit TG23is enabled, the latch operations by the first and second inversion units INV21and INV22may be performed while the second gating unit TG22is enabled, and simultaneously the latch operations by the third and fourth inversion units INV23and INV24may stop while the fourth gating unit TG24is disabled.

The reason why the latch operation of the first to fifth upper-level bit division blocks125_1to125_5may selectively stop and be performed during the counting section CS is to avoid the floating state of latch nodes including the input terminals of the first and third inversion units INV21and INV23as signals for controlling the first and third gating units TG21and TG23including the fifth lower-level bit signal D[4] and the first to fourth upper-level bit signal D[5] to D[8] have low frequencies. For example, when the minimum floating time when the floating state may be ignored is approximately 20 ns, and the frequency of the counting clock signal ICLK is approximately 800 Mhz, the range of the low frequency may be from the fifth lower-level bit signal D[4], whose frequency is approximately 25 Mhz or less, to the fifth upper-level bit signal D[9].

Subsequently, when entering the holding section HS, the lower-level bit counting portion123may perform a latch operation during the holding section HS based on the hold control signal HOLD_IN. In other words, the first to fifth lower-level bit division blocks123_1to123_5may latch the first to fifth lower-level bit signals D[0] to D[4] during the holding section HS. Also, the upper-level bit counting portion125may perform a latch operation during the holding section HS based on the fifth lower-level bit signal D[4] and the first to fourth upper-level bit signals D[5] to D[8]. In other words, the first to fifth upper-level bit division blocks125_1to125_5may latch the first to fifth upper-level bit signals D[5] to D[9] during the holding section HS.

The first to fifth lower-level bit signals D[0] to D[4] and the first to fifth upper-level bit signals D[5] to D[9] latched during the holding section HS may by accumulatively counted during a next counting section CS. Since the next counting section CS and a next holding section HS operate in the same manner as the previous counting section CS, a detailed description thereon is omitted herein.

In accordance with the embodiments of the present invention as described above, there are advantages in that loading time and power consumption may be reduced by stopping the latch operation during the counting section, and accumulative counting may be performed by a latch operation during the holding section.

FIG. 9is a block diagram illustrating an electronic system200in accordance with an embodiment of the present invention.

In this embodiment of the present invention, the number of division blocks where a latch operation stops during a counting section may be controlled based on operation frequency.

In this embodiment, the structure related to a counting circuit is described as in the embodiment ofFIG. 1, and the same reference numerals for the same signals described in the embodiment ofFIG. 1are used.

Referring toFIG. 9, the electronic system200may include a control device210and an electronic device220.

The control device210may generate number control signals CTRL<0:m> in response to an information signal DET_INF corresponding to an operation frequency.

The electronic device220may generate the information signal DET_INF in response to a source clock signal CLK and perform a counting operation in response to the number control signals CTRL<0:m>.

FIG. 10is a detailed diagram illustrating a counting circuit220A in accordance with an embodiment of the present invention, which may be included in the electronic device220shown inFIG. 9.

Referring toFIG. 10, the counting circuit220A may include a frequency detection portion221, a control logic portion223, a lower-level bit counting portion225, and an upper-level bit counting portion227. The frequency detection portion221detects a frequency of the source clock signal CLK and generates the information signal DET_INF corresponding to the detection result. The control logic portion223generates a hold control signal HOLD_IN and a counting clock signal ICLK in response to the source clock signal CLK and a count enable signal PULSE_IN. The lower-level bit counting portion225generates a plurality of lower-level bit signals D[0] to D[m] in response to the number control signals CTRL<0:m>, the hold control signal HOLD_IN, the counting clock signal ICLK and an initialization signal RST. The upper-level bit counting portion227generates a plurality of upper-level bit signals D[m+1] to D[n] in response to the initialization signal RST and the uppermost lower-level bit signal D[m] among the lower-level bit signals D[0] to D[m].

Since the frequency detection portion221is widely known to those skilled in the art, and the control logic portion223and the upper-level bit counting portion227have the same structures as the control logic portion121and the upper-level bit counting portion125described in the embodiment ofFIG. 1, a detailed description on the frequency detection portion221, the control logic portion223and the upper-level bit counting portion227is omitted herein. The lower-level bit counting portion225is described hereafter.

Referring toFIG. 11, the lower-level bit counting portion225may include a plurality of selection blocks225A_1to225A_m+1 and a plurality of lower-level bit division blocks2258_1to225B_m+1. The selection blocks225A_1to225A_m+1 select one among respectively predetermined signals including one among the lower-level bit signals D[0] to D[m] or the counting clock signal ICLK and the hold control signal HOLD_IN and output the selected signal as a plurality of selection signals SEL<0:m> in response to the number control signals CTRL<0:m>. The lower-level bit division blocks225B_1to225B_m+1 generate the lower-level bit signals D[0] to D[m] divided at respectively predetermined division ratios as compared with the counting clock signal ICLK during a counting section and latch the lower-level bit signals D[0] to D[m] during a holding section based on one among the selection signals SEL<0:m> and the predetermined signals.

For example, the selection blocks225A_1to225A_m+1 may include a multiplexer MUX, individually, and the lower-level bit division blocks225B_1to225B_m+1 may include a D-flip flop, individually. Since the selection blocks225A_1to225A_m+1 are widely known to those skilled in the art, and the lower-level bit division blocks225B_1to2258_m+1 have the same structure as the lower-level bit division blocks123_1to123_m+1 described in the embodiment ofFIG. 1, a detailed description on the selection blocks225A_1to225A_m+1 and the lower-level bit division blocks225B_1to225B_m+1 is omitted herein. However, the lower-level bit division blocks225B_1to225B_m+1 may receive the selection signals SEL<0:m> instead of the hold control signal HOLD_IN.

Although not Illustrated in the drawing, the lower-level bit division blocks225B_1to225B_m+1 may receive the selection signals SEL<0:m> or inversion signals of the selection signals SEL<0:m> based on the number control signals CTRL<0:m>.

Hereafter, an operation of the electronic system200having the aforementioned structure in accordance with the embodiment of the present invention is described.

In this embodiment, it is described as in the embodiment ofFIG. 1that the first to fifth lower-level bit signals D[0] to D[4] and the first to fifth upper-level bit signals D[5] to D[9] are generated.

The electronic device220may detect a frequency of the source clock signal CLK, generate the information signal DET_INF corresponding to the detection result, and provide the control device210with the information signal DET_INF. The control device210may generate the number control signals CTRL<0:m> corresponding to the information signal DET_INF and provide the electronic device220with the number control signals CTRL<0:m>.

Thus, the counting circuit220A may control the number of the lower-level bit division blocks where the latch operation stops during the counting section among the first to fifth lower-level bit division blocks2258_1to225B_5in response to the number control signals CTRL<0:m>. For example, when the frequency of the source clock signal CLK is approximately 800 Mhz, the first to fifth lower-level bit division blocks225B_1to225B_5may receive the first to fifth selection signals SEL<0:4> corresponding to the hold control signal HOLD_IN. Then, the first to fifth lower-level bit division blocks225B_1to225B_5may perform a counting operation while the latch operation stops during the counting section. When the frequency of the source clock signal CLK is approximately 400 Mhz, the first to fourth lower-level bit division blocks225B_1to225B_4may receive the first to fourth selection signals SEL<0:3> corresponding to the hold control signal HOLD_IN and the fifth selection signal SEL<4> corresponding to the fourth lower-level bit signal D[3]. Then, the first to fourth lower-level bit division blocks2255_1to225B_4may perform the counting operation while the latch operation stops during the counting section, and the fifth lower-level bit division block225B_5may perform the counting operation while the latch operation selectively stops during the counting section.

Under these circumstances, the counting circuit220A may perform the counting operation. Since the counting operation is the same as shown in the embodiment ofFIG. 1, a detailed description thereon is omitted herein (refer toFIG. 8). However, the lower-level bit counting portion225may generate the first to fifth lower-level bit signals D[0] to D[4] by performing the counting operation while the latch operation stops during the counting section CS or generate some signals among the first to fifth lower-level bit signals D[0] to D[4] by performing the counting operation while the latch operation stops during the counting section CS and generate the other signals among the first to fifth lower-level bit signals D[0] to D[4] by performing the counting operation while the latch operation selectively stops during the counting section CS in response to the number control signals CTRL<0:m>. For example, when the first to fifth number control signals CTRL<0:4> are enabled, the lower-level bit counting portion225may generate the first to fifth lower-level bit signals D[0] to D[4] by performing the counting operation while the latch operation stops during the counting section CS. When the first to fourth number control signals CTRL<0:3> are enabled, and the fifth number control signal CTRL<4> is disabled, the lower-level bit counting portion225may generate the first to fourth lower-level bit signals D[0] to D[3] by the performing the counting operation while the latch operation stops during the counting section CS and the fifth lower-level bit signal D[4] by performing the counting operation while the latch operation selectively stops during the counting section CS.

In accordance with the embodiment of the present invention, loading time and power consumption may be reduced by stopping the latch operation during the counting section, and accumulative counting may be performed by the latch operation during the holding section. Also, the adaptability to operation conditions is improved by controlling the number of division blocks where the latch operation stops based on operation frequency.

In accordance with the embodiments of the present invention, power consumption may be reduced by controlling whether to perform a latch operation or not during a counting section based on operation frequency.

FIG. 12is a block diagram Illustrating an image sensing device300in accordance with an embodiment of the present invention.

Referring toFIG. 12, the image sensing device300may include a pixel array310, a comparator block320, and a counter block330. For example, the image sensing device300may be a CMOS image sensor, and the comparator block320and the counter block330may form an analog-to-digital converter (ADC) block.

The pixel array310includes a plurality of pixels. The pixel array310may generate a plurality of pixel signals SIG_PIXELs corresponding to incident light, which have analog values. The comparator block320includes a plurality of comparators corresponding to the respective pixel signals SIG_PIXELs. The comparator block320may compare the pixel signals SIG_PIXELs with a ramp signal (a reference signal) VRAMP to generate a plurality of count enable signals PULSE_INs corresponding to the comparison result.

The counter block330includes a plurality of counters. The counter block330may perform counting operations based on a source clock signal CLK, an initialization signal RST and the count enable signals PULSE_INs to generate pixel data DATA_PIXELs which have digital values. For example, the counter included in the counter block330may include the counting circuit120A ofFIG. 2. In addition, the counter included in the counter block330may include the counting circuit220A ofFIG. 10. In such case, the counter block330may further receive the number control signals CTRL<0:m>.

While the present invention has been described with respect to specific embodiments, the embodiments are not intended to be restrictive, but rather descriptive. Further, it is noted that the present invention may be achieved in various ways through substitution, change, and modification, by those skilled in the art without departing from the scope of the present invention as defined by the following claims.