Bonding Semiconductor Dies Through Wafer Bonding Processes

A method comprises bonding a first wafer with a second wafer through wafer-on-wafer bonding, wherein the second wafer includes a first plurality of device dies therein. A second plurality of device dies are bonded on the second wafer through chip-on-wafer bonding. A gap-filling process is performed to fill the gaps between the second plurality of device dies with gap-filling regions. The gap-filling regions and the second plurality of device dies collectively form a reconstructed wafer.

BACKGROUND

With the increasingly greater integration level of integrated circuits, semiconductor devices, instead of having all integrated circuits formed in the same die, having more and more device dies bonded together to form packages, wherein the device dies having different functions may work together to achieve system functions.

DETAILED DESCRIPTION

A multi-die stack and the method of forming the same are provided. In accordance with some embodiments, a device wafer is bonded to a first carrier through wafer-on-wafer bonding. The device wafer is then thinned from backside, and backside redistribution lines are formed on the wafer. Device dies are then bonded on the wafer through chip-on-wafer bonding to form a reconstructed wafer. A bevel filling process is performed to fill the corners on the reconstructed wafer. A carrier switch process is preformed, and electrical connectors may be formed on the front side of the wafer. The wafer is then sawed. Through the wafer-on-wafer bonding process, the manufacturing cost may be reduced. Embodiments discussed herein are to provide examples to enable making or using the subject matter of this disclosure, and a person having ordinary skill in the art will readily understand modifications that can be made while remaining within contemplated scopes of different embodiments. Throughout the various views and illustrative embodiments, like reference numbers are used to designate like elements. Although method embodiments may be discussed as being performed in a particular order, other method embodiments may be performed in any logical order.

FIGS.1-18illustrate the cross-sectional views of intermediate stages in the formation of a package through wafer-on-wafer bonding in accordance with some embodiments. The corresponding processes are also reflected schematically in the process flow200as shown inFIG.25.

Referring toFIG.1, wafer10is formed. In accordance with some embodiments, wafer10is a carrier that has no active devices (such as transistors) and passive devices therein, and hence is referred to as carrier10hereinafter. Carrier10may have a round top view shape, withFIG.1illustrating a corner part of wafer10. In accordance with some embodiments, carrier10includes substrate12. Substrate12may be a blank substrate, and may be formed of a same material as the substrate32in device wafer30, so that in the subsequent packaging process, the warpage due to the mismatch in Coefficients of Thermal Expansion (CTE) values between carrier10and device wafer30is reduced. Substrate12may be formed of or comprise silicon, while other materials such as ceramic, glass, silicate glass, or the like may also be used. In accordance with some embodiments, the entire substrate12is formed of a homogeneous material, with no other material different from the homogeneous material therein. For example, the entire substrate12may be formed of silicon (doped or undoped), and there is no metal region, dielectric region, etc., therein.

In accordance with alternative embodiments, wafer10is a device wafer including active devices (such as transistors) and/or passive devices (such as capacitors, resistors, inductors, and/or the like) therein. Wafer10, when being the device wafer, may be an un-sawed wafer including a semiconductor substrate continuously extending into all device dies in the wafer, or may be a reconstructed wafer including discrete device dies that are packaged in an encapsulant (such as a molding compound or inorganic gap-filling regions).

Bond layer14is deposited on substrate12. In accordance with some embodiments, bond layer14is formed of or comprises a dielectric material, which may be a silicon-based dielectric material such as silicon oxide (SiO2), SiN, SiON, SiOCN, SiC, SiCN, or the like, or combinations thereof. In accordance with some embodiments, bond layer14is formed using High-Density Plasma Chemical Vapor Deposition (HDPCVD), Plasma Enhanced Chemical Vapor Deposition (PECVD), Chemical Vapor Deposition (CVD), Low-Pressure Chemical Vapor Deposition (LPCVD), Atomic Layer deposition (ALD), or the like.

In accordance with some embodiments, bond layer14is in physical contact with substrate12. In accordance with alternative embodiments, carrier10includes a plurality of layers (not shown) between bond layer14and substrate12. For example, there may be an oxide-based layer formed of an oxide-based material (which may also be silicon oxide based) such as silicon oxide, phospho-silicate glass (PSG), borosilicate glass (BSG), boron-doped phospho silicate glass (BPSG), fluorine-doped silicate glass (FSG), or the like. There may also be a nitride-based layer formed of or comprising silicon nitride, silicon oxynitride (SiON), or the like. In accordance with some embodiments, the layers between substrate12and bond layer14may be formed using PECVD, CVD, LPCVD, ALD, or the like. There may also be alignment marks (not shown) formed between bond layer14and substrate12. The alignment marks may be formed as metal plugs, which may be formed through damascene processes.

Device wafer30is also formed. Device wafer30may be an un-sawed wafer, and the bonding process as shown inFIG.2is a wafer-on-wafer bonding process. In accordance with some embodiments, device wafer30includes substrate32, and integrated circuit devices34at a surface of substrate32. In accordance with some embodiments, through-substrate vias36are formed extending from the front side (the illustrated bottom side) into substrate32. In accordance with alternative embodiments, no through-vias are formed at this stage, and the through-vias are formed in the process as shown inFIG.3. Substrate32may be a semiconductor substrate such as a silicon substrate. In accordance with other embodiments, substrate32may include other semiconductor materials such as silicon germanium, carbon-doped silicon, or the like. Substrate32may be a bulk substrate, or may have a layered structure, for example, including a silicon substrate and a silicon germanium layer over the silicon substrate.

In accordance with some embodiments, device wafer30includes device dies, which may include logic dies, memory dies, input-output dies, Integrated Passive Devices (IPDs), or the like, or combinations thereof. For example, the logic device dies in device wafer30may be Central Processing Unit (CPU) dies, Graphic Processing Unit (GPU) dies, mobile application dies, Micro Control Unit (MCU) dies, BaseBand (BB) dies, Application processor (AP) dies, or the like. The memory dies in device wafer30may include Static Random-Access Memory (SRAM) dies, Dynamic Random-Access Memory (DRAM) dies, or the like. Device wafer30may be a simple device wafer including a semiconductor substrate extending continuously throughout device wafer30, or may be a reconstructed wafer including device dies packaged therein, which device dies may be integrated as a system.

In accordance with some embodiments, integrated circuit devices34are formed on the front surface (the illustrated bottom surface) of semiconductor substrate32. Example integrated circuit devices34may include Complementary Metal-Oxide Semiconductor (CMOS) transistors, resistors, capacitors, diodes, and/or the like. The details of integrated circuit devices34are not illustrated herein. In accordance with alternative embodiments, device wafer30is used for forming interposers, in which substrate32may be a semiconductor substrate or a dielectric substrate.

Front-side interconnect structure38is formed on the front side of substrate32. The front-side interconnect structure38may include a plurality of dielectric layers40such as an Inter-Layer Dielectric (ILD), Inter-Metal Dielectrics (IMDs), non-low-k passivation layers, polymer layers, and/or the like. In accordance with some example embodiments, the ILD is formed of or comprises silicon oxide, PSG, BSG, BPSG, FSG, or the like. The IMD layers may be formed of low-k dielectric materials having dielectric constant values (k-values) lower than about 3.0. For example, the IMD layers may comprise a carbon-containing low-k dielectric material(s), Hydrogen SilsesQuioxane (HSQ), MethylSilsesQuioxane (MSQ), or the like.

The front-side interconnect structure38further includes conductive features in the dielectric layers. The conductive features may include contact plugs, metal lines, and metal pads, (schematically illustrated as42), metal vias, and/or the like. The contact plugs may be formed of tungsten, aluminum, copper, titanium, tantalum, titanium nitride, tantalum nitride, alloys therefore, and/or multi-layers thereof. Each of the metal lines and the metal vias may include a diffusion barrier layer and a copper-containing metallic material on the diffusion barrier layer. The diffusion barrier layer may include titanium, titanium nitride, tantalum, tantalum nitride, or the like.

In accordance with some embodiments, there may be metal pads44formed in dielectric layers40. The metal pads44may be formed of or comprise aluminum, copper, nickel, titanium, palladium, or the like, or alloys thereof. In accordance with some embodiments, metal pads44are in a passivation layer. In accordance with alternative embodiments, a polymer layer (which may be polyimide, polybenzoxazole (PBO), or the like) may be formed, with the metal pads44being in the polymer layer.

Device wafer30is bonded to carrier10through wafer-on-wafer bonding. The respective process is illustrated as process202in the process flow200as shown inFIG.25. The resulting structure is shown inFIG.2. A surface dielectric layer in dielectric layers40is bonded to bond layer14through fusion bonding, with Si—O—Si bonds being formed to join the surface dielectric layer in dielectric layers40to bond layer14.

Further referring toFIG.2, edge-sealing layer48is dispensed into the edge gap between substrate12and substrate32, and on the sidewalls of interconnect structure38. The respective process is illustrated as process204in the process flow200as shown inFIG.25. In accordance with some embodiments, edge-sealing layer48is formed of or comprises a polymer, which may be polyimide, PBO, or the like. Edge-sealing layer48may be dispensed in a flowable form, and is then cured and solidified. Furthermore, edge-sealing layer48is dispensed as a ring fully encircling interconnect structure38.

Referring toFIG.3, a wafer edge trimming process is performed to form recess50, which forms a recess ring along the peripheral of wafers10and30. The respective process is illustrated as process206in the process flow200as shown inFIG.25. A backside grinding process is then performed from the backside of device wafer30, and substrate32is thinned. The backside grinding process may be performed through a Chemical Mechanical Polish (CMP) process or a mechanical polishing process. In the backside grinding process, edge-sealing layer48has the function of preventing device wafer30from peeling off from carrier10. The backside grinding process is performed until through-vias36are exposed.

In accordance with some embodiments, after through-vias36are exposed, semiconductor substrate32is slightly recessed, for example, through an etching process, so that the top portions of through-vias36protrude out of the recessed semiconductor substrate32.

Next, as shown inFIG.4, dielectric isolation layer52is formed to embed the protruding portions of through-vias36therein. In accordance with some embodiments, dielectric isolation layer52is first formed by depositing a dielectric material, which may be formed of or comprise silicon oxide, silicon nitride, or the like. A planarization process is then performed to remove the excess portions of the dielectric material over through-vias36, so that through-vias36are revealed again. The remaining dielectric material is dielectric isolation layer52.

Further referring toFIG.4, backside interconnect structure54is formed. The respective process is illustrated as process208in the process flow200as shown inFIG.25. Backside interconnect structure54includes one or a plurality of dielectric layers56and one or a plurality of layers of redistribution lines (RDLs)58. In accordance with some embodiments, RDLs58are formed through damascene processes, which include depositing the corresponding dielectric layers56, forming trenches and via openings in the dielectric layers56, and filling the trenches and the via openings with a metallic material(s) to form RDLs58. Dielectric layers56may be formed of or comprise inorganic dielectric materials such as silicon oxide, silicon nitride, silicon oxynitride, or the like. In accordance with alternative embodiments, dielectric layers56may be formed of polymers, which may be photo-sensitive, and the formation process of an RDLs58may include depositing a metal seed layer, forming and patterning a plating mask over the metal seed layer, performing a plating process to form the RDLs, removing the plating mask to expose the underlying portions of the metal seed layer, and etching the exposed portions of the metal seed layer.

In accordance with some embodiments, bond pads60are formed as the surface conductive features of wafer30. Bond pads60may have top surfaces coplanar with the top surface of a top dielectric layer in dielectric layers56. In accordance with some embodiments, bond pads60are formed of or comprise copper. The top dielectric layer in dielectric layers56may be formed of or comprise a silicon-containing dielectric material such as silicon oxide, silicon nitride, SiC, SiOC, SiON, SiOC, or the like.

Referring toFIG.5, a plurality of device dies62are bonded to wafer30through chip-on-wafer bonding. The respective process is illustrated as process210in the process flow200as shown inFIG.25. The bonding may be achieved through face-to-back bonding, with the front side of device dies62being bonded to the backside of the dies in wafer30. Each die in wafer30may be bonded with one or more of device dies62. Each die62may also be bonded with one or more dies in wafer30. Device dies62may include semiconductor substrates64, and integrated circuits66at the surface of semiconductor substrates64. Semiconductor substrates64may be a silicon substrate.

Each device die62may include interconnect structure68, which includes dielectric layers70and conductive features (not shown) therein. Bond pads72are formed as the surface conductive features of device dies62. Bond pads72may have surfaces (the illustrated bottom surfaces) coplanar with the surface of a surface dielectric layer in dielectric layers70. In accordance with some embodiments, bond pads72are formed of or comprise copper. The surface dielectric layer in dielectric layers70may be formed of or comprise a silicon-containing dielectric material such as silicon oxide, silicon nitride, SiC, SiOC, SiON, SiOC, or the like.

The bonding may be achieved through hybrid bonding. For example, bond pads72are bonded to bond pads60through metal-to-metal direct bonding. In accordance with some embodiments, the metal-to-metal direct bonding is copper-to-copper direct bonding. Furthermore, the surface dielectric layer in dielectric layers70is bonded to the surface dielectric layer in dielectric layers56through fusion bonding, for example, with Si—O—Si bonds generated.

FIG.6illustrates a gap-filling process for forming gap-filling layers/regions. The respective process is illustrated as process212in the process flow200as shown inFIG.25. In accordance with some embodiments, the gap-filling layers includes adhesion layer74, and dielectric layer76over and contacting adhesion layer74. Adhesion layer74may be deposited using a conformal deposition process such as Atomic Layer Deposition (ALD) or Chemical Vapor Deposition (CVD). Accordingly, adhesion layer74may be a conformal layer, for example, with the thickness of the horizontal portions and the thickness of the vertical portions being substantially equal to each other (for example, with a variation smaller than about 20 percent). Adhesion layer74is formed of a dielectric material that has good adhesion to the sidewalls of device dies62and the top surface of dielectric layer56. In accordance with some embodiments, adhesion layer74is formed of or comprises a nitride-containing material such as silicon nitride.

Dielectric layer76is formed of a material different from the material of adhesion layer74. In accordance with some embodiments, dielectric layer76is formed of or comprises silicon oxide, while other dielectric materials such as silicon carbide, silicon oxynitride, silicon oxy-carbo-nitride, or the like may also be used. Dielectric layer76may be a non-conformal layer with the thicknesses of the horizontal portions and vertical portions being different from each other, or may be a conformal layer.

Further referring toFIG.6, a planarization process such as a CMP process or a mechanical grinding process is performed to remove excess portions of the gap-filling layers74and76, so that the top surface of substrates64are exposed. Substrates64may also be polished to a desirable thickness, for example, smaller than about 50 μm. The remaining portions of layers74and76are collectively referred to as gap-filling regions78. Throughout the description, the structure shown inFIG.6is referred to as reconstructed wafer100.

Device dies62and the gap-filling regions78are collectively referred to as reconstructed wafer81. In accordance with alternative embodiments, instead of bonding device dies62to wafer30and forming reconstructed wafer81based on the bonded device dies62, the reconstructed wafer81may be pre-formed, and then bonded to the underlying wafer through wafer-on-wafer bonding. Similarly, wafer30may be an unsawed device wafer, or may be a reconstructed wafer having a similar structure as reconstructed wafer81. The reconstructed wafer is bonded to carrier10through wafer-on-wafer bonding.

Gap-filling regions78have chamfers, and hence have bevel recesses80, which laterally extend to the sidewalls of the trimmed wafer30. The bevel recesses80may adversely affect the subsequent processes such as the bonding of a supporting substrate. For example, as shown inFIG.24, since device dies62may be positioned as an array, and the top view of wafer30is rounded, some device dies62may be farther away from the wafer edges than other device dies62, resulting in large and wide bevel recesses80. Accordingly, bevel recesses80may be filled before the subsequent processes.FIGS.7through10illustrate some example processes for filling the bevel recesses with bevel-recess filling regions82in accordance with some embodiments.

Referring toFIG.7, a sacrificial layer84is formed Sacrificial layer84A may be formed to cover the regions of reconstructed wafer100where device dies are distributed, but not some regions between the outmost ones of device dies62and the respective closest edges of reconstructed wafer100. The respective process is illustrated as process214in the process flow200as shown inFIG.25. Sacrificial layer84A may comprise a photoresist.

FIG.24illustrates an example top view of sacrificial layer84A, which may cover all of the device dies62, and having edges vertically aligned to the outer edges of the outmost device dies62, or expand slightly beyond the outer edges of the outmost device dies62. Due to that the bevel recesses may be larger where the outmost edges of the outmost device dies62are farther away from the edges of the wafer30than where they are closer to the edges of wafer20, sacrificial layer84A may have the edges close to device dies62. In accordance with some embodiments, in the top view of the reconstructed wafer100, sacrificial layer84A may be formed as having a non-circular shape (although wafer30has a circular top-view shape).

Referring again toFIG.7, a first filling layer82A is deposited. The respective process is illustrated as process216in the process flow200as shown inFIG.25. The first filling layer82A may comprise or may be formed of silicon oxide, silicon oxynitride, silicon oxycarbide, silicon oxy-carbo-nitride, or the like, or combinations thereof. The material of the first filling layer82A may be the same as or different from the material of dielectric layer76.

In accordance with alternative embodiments, sacrificial layer84is not formed, and the first filling layer82A is in contact with semiconductor substrate directly. Processes214and218illustrated in the process flow200inFIG.25are thus shown as being dashed to indicate that these processes may be, or may not be, performed.

In accordance with some embodiments, the deposition of the first filling layer82A may adopt a non-conformal deposition process such as PVD or PECVD, so that the top portions of the first filling layer82A are thicker than the sidewall portions. The non-conformal first filling layer82A is more efficient in filling the bevel recesses. Alternatively, the first filling layer82A may be formed of a conformal deposition process such as CVD. Some portions of first filling layer82A are deposited on Sacrificial layer84A.

After the deposition process, sacrificial layer84A is removed, for example, in an etching process. The respective process is illustrated as process218in the process flow200as shown inFIG.25. The portions of the first filling layer82A on top of sacrificial layer84A are thus removed, which is also referred to as being lifted. A first planarization process such as a CMP process may then be performed to level the top surface of the deposited first filling layer82A with the top surface of device dies62. The respective process is illustrated as process220in the process flow200as shown inFIG.25. The preceding process including forming the sacrificial layer84A, depositing the first filling layer82A, removing the sacrificial layer84A, and the planarization process are collectively referred to a first bevel-filling cycle.

In accordance with alternative embodiments, the first bevel-filling cycle includes the deposition of the first filling layer82A and the subsequent planarization process, and does not include the deposition and the removal of the sacrificial layer84A. In accordance with yet alternative embodiments, the first bevel-filling cycle includes deposition the sacrificial layer84A, depositing the first filling layer82A, removing the sacrificial layer84A, and does not include the subsequent planarization process. The planarization process is performed after all subsequent bevel-filling cycles have been finished.

In accordance with some embodiments in which the bevel-recesses are not fully filled, after the first bevel-filling cycle, a second bevel-filling cycle may be performed. The respective process is shown inFIG.25as looping back to process214. For example,FIG.9illustrates an intermediate stage in the second bevel-filling cycle, which includes forming and patterning sacrificial layer84B, depositing a second filling layer82B, removing the sacrificial layer84B to lift some portions of the second filling layer82B, and possibly performing a second planarization process. The second filling layer82B may comprise or may be formed of silicon oxide, silicon oxynitride, silicon oxycarbide, silicon oxy-carbo-nitride, or the like, or combinations thereof. Also, the material of the second filling layer82B may be the same as or different from the material of the first filling layer82A.

The bevel-filling cycles may be repeated until the bevel recesses are fully filled or substantially fully filled, for example, with more than 90 percent of the volume filled. The remaining portions of the filling layers (including second filling layers82A and82B or more if more bevel-filling cycles are included) are collectively referred to as bevel-filling layers/regions82.FIG.10illustrates a structure after a planarization process is performed. The planarization process may be in the last bevel-filling cycle, or may be a planarization process after the plurality of bevel-filling cycles if the bevel-filling cycles do not include planarization processes. As a result of the planarization process(es), the top surfaces of the substrates64in device dies62may be revealed, and are coplanar with the top surfaces of bevel-filling regions82and dielectric layer76.

FIG.11illustrates the formation of bond layer86. The respective process is illustrated as process222in the process flow200as shown inFIG.25. In accordance with some embodiments, bond layer86comprises a silicon-containing dielectric material such as silicon oxide, silicon nitride, silicon carbide, SiOC, SiON, SiOCN, or combinations thereof. The formation process may be a conformal deposition process such as ALD, CVD, or the like.

FIG.12illustrates a bevel removal process, in which some previously deposited materials are removed through etching. The respective process is illustrated as process224in the process flow200as shown inFIG.25. The bevel removal process may reduce the chipping and the particles of these materials during the subsequent processes. In accordance with some embodiments, a photoresist (not shown) may be formed to cover the middle portions of the reconstructed wafer100as shown inFIG.11. An etching process(es) may then be performed to remove the portions of bond layer86and dielectric layer76at the bottom corners of carrier10.

FIG.13illustrates the bonding of supporting substrate88to reconstructed wafer100in accordance with some embodiments. The respective process is illustrated as process226in the process flow200as shown inFIG.25. Supporting substrate88is in wafer form, and hence is also referred to as a supporting wafer. Supporting substrate88may be bonded to bond layer86through bond layer92. In accordance with some embodiments, bond layer92is pre-formed on supporting substrate88, for example, through a thermal oxidation process or a deposition process, and the structure including both of bond layer92and supporting substrate88are bonded to bond layer86.

Bond layer92may be a silicon-containing dielectric layer formed of or comprising SiO2, SiN, SiC, SiON, or the like. The deposition process may include LPCVD, PECVD, PVD, ALD, PEALD, or the like. Supporting substrate88may be formed of a material that has a high thermal conductivity. In accordance with some embodiments, supporting substrate88is a silicon substrate, while another type of substrate such as another semiconductor substrate, a dielectric substrate, a metallic substrate, or the like may be used. The entire supporting substrate88may be formed of a homogenous material. For example, supporting substrate88may be free from active and passive devices, metal lines, dielectric layers, and the like therein. The bonding of bond layer92to bond layer86may include fusion bonding.

In accordance with some embodiments, after the bonding process, supporting substrate88is thinned, for example, in a mechanical grinding process or a CMP process, so that the thickness of supporting substrate88is reduced to a proper value. Supporting substrate88is thus thick enough to support the subsequent grinding of wafer120(FIG.12), and is not too thick. In accordance with alternative embodiments, supporting substrate88is not thinned.

Reconstructed wafer100is then flipped upside down, as shown inFIG.14. Next, carrier10is removed, for example, through a mechanical grinding process. The respective process is illustrated as process228in the process flow200as shown inFIG.25. The carrier-removal process may be performed until wafer30is exposed, as shown inFIG.15. The resulting structure is shown inFIG.15, and is referred to as reconstructed wafer96.

Referring toFIG.16, passivation layer98is deposited. The respective process is illustrated as process230in the process flow200as shown inFIG.25. Passivation layer98may be formed of a non-low-k dielectric layer, which has the function of blocking moisture. In accordance with some embodiments, passivation layer98is formed of or comprises silicon oxide, silicon nitride, USG, or the like, combinations thereof, or multi-layers thereof. Passivation layer98may be conformal, and may be formed using ALD, CVD, or the like.

FIG.17illustrates the formation of opening102, which is formed by etching passivation layer98and dielectric layer40. The respective process is illustrated as process232in the process flow200as shown inFIG.25. Polymer layer104may then be formed, and may extend into opening102. The respective process is illustrated as process234in the process flow200as shown inFIG.25. Metal pads44are exposed by removing the portion of the polymer layer104directly over metal pads44. Next, as shown inFIG.18, electrical connectors106are formed to electrically connect to metal pads44. The respective process is illustrated as process236in the process flow200as shown inFIG.25. Electrical connectors106may be solder regions, metal pillars, metal pads, or the like.

Reconstructed wafer96may be used in wafer form, wherein the entire wafer96is used as a package. Alternatively stated, reconstructed wafer96is used (powered up) in the final product. This may be used in performance-demanding applications such as Artificial Intelligence (AI) application. In accordance with these embodiments, reconstructed wafer96may or may not be trimmed to remove some edge portions that don't include device dies, circuits, routing lines, etc. For example,FIG.24schematically illustrates trimming lines97when reconstructed wafer96is trimmed, wherein the portions of the reconstrued wafer96outside of the trimming lines97are removed.

Referring toFIG.18, in accordance with alternative embodiments, a singulation process is performed to saw reconstructed wafer96into discrete packages96′, which are identical to each other. The respective process is illustrated as process238in the process flow200as shown inFIG.25. In packages96′, device dies30′, which are parts of the sawed wafer30, are referred to as tier-1 (T1) dies since they are the first to be bonded in the package formation process. Device dies62are referred to as tier-2 (T2) dies. The packages96′ may also include supporting substrates88′, which are pieces sawed from the wafer-level supporting substrate88.

The singulation process may be performed along scribe lines108. Scribe lines108A,108B,108C,108D, and108E illustrate some possible positions of the singulation or trimming lines (which are shown as97inFIG.24). Some of the packages96′ at the edges of reconstructed wafer96may have unique structures. For example, when scribe line108A is adopted, the respective package96′ is free from the bevel-filling regions82. Also, the edges of semiconductor substrate32are exposed. Otherwise, when scribe line108B is adopted, the respective package96′ may include bevel-filling regions82, which is on the illustrated left side, but not on the illustrated right side, of package96′. When scribe line108C,108D, or108E is adopted, the respective package96′ may further include adhesion layer74on the illustrated left side, but not on the illustrated right side, of package96′. The scribe line may also be at any position between the positions of scribe line108A and108E.

FIGS.19through23illustrate some packages96′ formed in accordance with the embodiments of the present disclosure. The formation of these packages includes wafer-on-wafer bonding processes, wherein the wafers may include unsawed device wafers, or the reconstructed wafers that include discrete device dies encapsulated in encapsulants (gap-filling regions). In these packages, unless specified otherwise, the device dies marked as T1 are the device dies that are bonded (to initial carrier10) before the bonding of T2 dies, and the device dies T2 are the device dies that are bonded to T1 dies before the bonding of T3 dies. The electrical connectors106are not shown inFIGS.19-23, although they may exist.

FIG.19schematically illustrates a two-tier package96′ same as the package96′ as shown inFIG.18, with some details omitted. The formation of the package includes a wafer-on-wafer bonding process, in which a device wafer including T1 dies is bonded to a carrier, followed by a chip-on-wafer bonding process, in which discrete T2 dies are bonded to the device wafer including the T1 dies through wafer-on-wafer bonding.

FIG.20schematically illustrates a two-tier package96′. The formation of the package includes a chip-on-wafer bonding process, in which discrete T1 dies are bonded to a carrier wafer, followed by a gap-filling process to form a reconstructed wafer. A wafer-on-wafer bonding process may then be performed, in which an unsawed device wafer including T2 dies is bonded to the reconstructed wafer including the T1 dies. Supporting substrate88may then be bonded, and the carrier may be removed. A singulation process may be, or may not be, performed.

FIG.21schematically illustrates a three-tier package96′. The formation of the package includes a chip-on-wafer bonding process, in which a device wafer including T1 dies is bonded to a carrier, followed by a chip-on-wafer bonding process, in which discrete T2 dies are bonded to the device wafer including the T1 dies. The T2 dies are encapsulated (gap-filled) to form a first reconstructed wafer. A second reconstructed wafer including the encapsulated T3 dies are then bonded to the first reconstructed wafer through wafer-on-wafer bonding. Alternatively, the T3 dies may be bonded to the T2 dies through chip-on-wafer bonding. A singulation process may be, or may not be, performed.

FIG.22schematically illustrates a three-tier package96′. The formation of the package includes a chip-on-wafer bonding process, in which discrete T1 dies are bonded to a carrier to form a first reconstructed wafer, followed by a wafer-on-wafer bonding process, in which a device wafer including T2 dies is bonded to the first reconstructed wafer to form a second reconstrued wafer. Discrete T3 dies are then bonded to the T2 dies in the second reconstructed wafer through chip-on-wafer bonding, followed by an encapsulation process to fill the gaps between the T3 dies. Alternatively, the T3 dies may be pre-packaged to form a reconstructed wafer, which is bonded to the T2 dies through wafer-on-wafer bonding. A singulation process may be, or may not be, performed.

FIG.23schematically illustrates a three-tier package96′. The formation of the package includes a chip-on-wafer bonding process, in which discrete T1 dies are bonded to a carrier to form a first reconstructed wafer, followed by a chip-on-wafer bonding process, in which discrete T2 dies are bonded to the first reconstructed wafer to form a second reconstrued wafer. Alternatively, the T2 dies may be pre-packaged to form a reconstructed wafer, which is bonded to the T1 dies through wafer-on-wafer bonding. A wafer including T3 dies is then bonded to the second reconstructed wafer through wafer-on-wafer bonding. A singulation process may be, or may not be, performed.

The embodiments of the present disclosure have some advantageous features. By performing wafer-on-wafer processes to form packages, the manufacturing cost is reduced since the preparation and the gap-filling process for the chips in the wafers may be saved. Combining the wafer-on-wafer process with chip-on-wafer bonding further provides more flexible in the manufacturing process of the integrated circuits.

In accordance with some embodiments, a method comprises bonding a first wafer with a second wafer through wafer-on-wafer bonding, wherein the second wafer comprises a first plurality of device dies therein; bonding a second plurality of device dies on the second wafer through chip-on-wafer bonding; and performing a gap-filling process to fill gaps between the second plurality of device dies with gap-filling regions, wherein the gap-filling regions and the second plurality of device dies collectively form a reconstructed wafer.

In an embodiment, the first wafer comprises a carrier, and the method further comprises bonding a supporting substrate on the second plurality of device dies through wafer-on-wafer bonding, wherein the supporting substrate and the first wafer are on opposing sides of the second wafer; and removing the first wafer. In an embodiment, the removing the first wafer comprises a grinding process. In an embodiment, the method further comprises, after the first wafer is removed, etching a dielectric layer in the second wafer to form an opening, with a metal pad in the second wafer being exposed; and forming an electrical connector on the metal pad.

In an embodiment, the method further comprises, after the gap-filling process, performing a bevel-filling process to fill bevel recesses that are close to edge regions of the reconstructed wafer. In an embodiment, the bevel-filling process comprises a plurality of cycles, and wherein each of the plurality of cycles comprises depositing a filling layer; and planarizing the filling layer. In an embodiment, each of the plurality of cycles further comprises forming a sacrificial layer covering a center portion of the reconstructed wafer, with edge portions of the reconstructed wafer being exposed, and a portion of the filling layer is deposited on the sacrificial layer; and after the filling layer is deposited, removing the sacrificial layer, with the portion of the filling layer being removed.

In an embodiment, the second wafer comprises a semiconductor substrate, and through-vias extending into the semiconductor substrate, and wherein the method further comprises before the second plurality of device dies are bonded on the second wafer, thinning the semiconductor substrate to reveal the through-vias. In an embodiment, the method further comprises sawing the reconstructed wafer to form a plurality of packages. In an embodiment, the method further comprises trimming edge portions of the reconstructed wafer to remove portions of the reconstructed wafer, with the trimmed portions being free from circuits. In an embodiment, the method further comprises, before the second plurality of device dies are bonded on the second wafer, performing an edge trimming process to remove an edge portion of the second wafer.

In accordance with some embodiments, a comprises bonding a device wafer to a carrier through fusion bonding, wherein the device wafer comprises integrated circuits therein; bonding a plurality of device dies on the device wafer through chip-on-wafer bonding; performing a gap-filling process to fill gaps between the plurality of device dies with gap-filling regions; bonding a supporting substrate to the gap-filling regions and the plurality of device dies; removing the carrier from the device wafer; and forming electrical connectors on the device wafer, wherein the electrical connectors are electrically connected to the integrated circuits in the device wafer.

In an embodiment, the supporting substrate comprises a blank silicon substrate. In an embodiment, the method further comprises, after the gap-filling process and before the supporting substrate is bonded to the gap-filling regions depositing a bond layer on the gap-filling regions and the plurality of device dies. In an embodiment, the method further comprises, before the supporting substrate is bonded, etching a portion of the gap-filling regions, wherein the etched portion being deposited on an edge of the carrier. In an embodiment, the method further comprises, before the plurality of device dies are bonded to the carrier, performing an edge trimming process to remove edge portions of the device wafer. In an embodiment, in the edge trimming process, an edge recess is formed to extend from a top surface of the carrier to an intermediate level between the top surface and a bottom surface of the carrier.

In accordance with some embodiments, a method comprises bonding a first plurality of device dies over a carrier through a first bonding process; bonding a second plurality of device dies over the first plurality of device dies through a second bonding process, wherein a first one of the first bonding process and the second bonding process comprises a wafer-on-wafer bonding process, and a second one of the first bonding process and the second bonding process comprises a chip-on-wafer bonding process; bonding a blanket silicon wafer over the second plurality of device dies; and removing the carrier. In an embodiment, the first plurality of device dies are in an un-sawed device wafer when the wafer-on-wafer bonding process is performed. In an embodiment, the first plurality of device dies are in a reconstructed wafer when the wafer-on-wafer bonding process is performed.