Semiconductor device with aligned bumps

In a semiconductor device in which semiconductor chips having a number of signal TSVs are stacked, a huge amount of man-hours have been required to perform a continuity test for each of the signal TSVs. According to the present invention, no continuity test is performed directly on signal TSVs. Dummy bumps are arranged in addition to signal TSVs. The dummy bumps of the semiconductor chips are connected through a conduction path that can pass the dummy bumps between the semiconductor chips with one stroke when the semiconductor chips are stacked. A continuity test of the conduction path allows a bonding defect on bonded surfaces of two of the stacked semiconductor chips to be measured and detected.

This application is based upon and claims the benefit of priority from Japanese patent application No. 2011-210987, filed on Sep. 27, 2011 and Japanese patent application No. 2011-273703, filed on Dec. 14, 2011, the disclosures of which are incorporated herein in their entirety by reference.

BACKGROUND

The present invention relates to a semiconductor chip, a semiconductor device having a structure in which semiconductor chips are stacked, and a method of measuring a semiconductor device.

Recently, proposals have been made about a semiconductor device which has a multilayer structure of stacking semiconductor chips through a number of through electrodes, which are called through silicon vias (TSVs). In a semiconductor device having such a multilayer structure, a continuity test or conduction test is performed for each of TSVs after the stacking of semiconductor chips in order to determine whether or not a normal connection is established between the semiconductor chips. In this case, a continuity test is usually conducted for each of TSVs by bringing a test terminal into contact with a signal bump provided on each of the TSVs. However, since a great number of TSVs are provided in such a semiconductor device, a huge amount of man-hours are required for continuity tests if a continuity test is performed for every one of the TSVs.

In a case where a continuity test of a TSV is usually carried out after a semiconductor device has been assembled into a product, the entire product becomes defective if any defect is found between TSVs after the assembly.

Meanwhile, JR-A 2009-139273 (Patent Literature 1) discloses a multilayer semiconductor device and a continuity test method that can individually confirm a connection state of each of semiconductor chips of a semiconductor device. In order to confirm a connection state of each layer of the semiconductor chips after stacking of the semiconductor chips, a test-dedicated terminal is provided on each of the semiconductor chips, and a diode for a continuity test is connected between the test-dedicated terminal and an internal terminal.

JP-A 2011-145257 (Patent Literature 2) discloses a semiconductor device having an interface chip and a core chip separated from each other. The interface chip and the core chip are electrically coupled to each other by a measurement signal wiring including a through electrode and a reference signal wiring. Specifically, Patent Literature 2 proposes providing a signal generation circuit and a signal judgment circuit on the interface chip, transmitting a test clock and a predetermined measurement signal to the core chip from the signal generation circuit, and detecting a phase difference of the predetermined measurement signals received via the measurement signal wiring and the reference signal wiring.

Both of Patent Literature 1 and Patent Literature 2 propose a test method of a semiconductor device having semiconductor chips with through electrodes after the semiconductor device has been assembled into a product. Furthermore, a connection state is confirmed by electrically coupling signal through electrodes and confirming a connection state of signal wirings between the semiconductor chips.

According to inventors' study, it has been found that, if a connection failure or defect occurs between semiconductor chips, the connection failure widely extends not only to signal through electrodes, but also to the vicinity of the signal through electrodes. If such a connection failure or defect can be detected at an early stage, a semiconductor chip can be restacked, so that a remarkable increase of yields of products can be expected.

SUMMARY OF THE INVENTION

The present invention has been made from the aforementioned points of view.

Thus, the present invention seeks to provide a semiconductor device which solves at least one of the above-mentioned points.

According to a first aspect of the present invention, there is provided a semiconductor device comprising a first chip including a plurality of first bumps and a plurality of first wirings, and a second chip including a plurality of second bumps and a plurality of second wirings, and being stacked with the first chip such that each of the second bumps is coupled to a corresponding one of the first bumps of the first chip, wherein the first wirings, the first bumps, the second wirings, and the second bumps constitute a single electrical path, and the first wirings, the first bumps, the second wirings and the second bumps are arranged in series with one another in the single electrical path.

According to a second aspect of the present invention, there is provided a semiconductor chip comprising a first surface and a second surface opposite to the first surface, a first group of dummy bumps on the first surface, a second group of dummy bumps on the second surface, and wirings which are placed within the semiconductor chip and which electrically connect the dummy bumps of the first and the second groups, wherein the wirings include first wirings which connect two of the dummy bumps of the first group, and second wirings which connect two of the dummy bumps of the second group.

According to a third aspect of the present invention, there is provided a method of measuring a semiconductor device which has a plurality of semiconductor chips bonded to each other through dummy bumps of each semiconductor chip, comprising constituting a single electrical path which extends through the dummy bumps and internal wirings of the plurality of the semiconductor chips connected to the dummy bumps and which is connected in series with the dummy bumps and the internal wirings of the plurality of the semiconductor chips and detecting whether or not the single electrical path is normal.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

FIGS. 1A and 1Bare a perspective view and a cross-sectional view showing a semiconductor chip10according to an embodiment of the present invention. The semiconductor chip10will be explained as being a DRAM. Nevertheless, semiconductor chips to which the present invention is applicable are not limited to a DRAM, and the present invention may be applied to an SRAM and a non-volatile memory, such as a flash memory, a ReRAM, an MRAM, a PRAM, and the like. For convenience of explanation, a lower surface of the semiconductor chip10illustrated inFIGS. 1A and 1Bis referred to as a first surface P1, and an upper surface of the semiconductor chip10illustrated inFIGS. 1A and 1Bis referred to as a second surface P2.

The semiconductor chip10includes a large number of signal through electrodes formed at a central portion of the semiconductor chip10. Those signal through electrodes are hereinafter referred to as signal TSVs. The signal TSVs extend through the semiconductor chip10from the first surface P1to the second surface P2. The signal TSVs include not only signal TSVs for transmitting/receiving signals such as data signals, address signals, and clock signals, but also signal TSVs for supplying a power source voltage.

The semiconductor chip10includes first signal bumps121provided on the signal TSVs of the first surface P1and second signal bumps122provided on the signal TSVs of the second surface P2. Thus, the first and second signal bumps121and122are electrically coupled to each other in a one-to-one relationship via the corresponding signal TSVs. In other words, the first and second signal bumps121and122are arranged at corresponding positions of the first and second surfaces P1and P2of the semiconductor chip10.

The semiconductor chip10illustrated inFIG. 1Afurther includes dummy bump arrays15aand15barranged on the first and second surfaces P1and P2. The dummy bump arrays15aand15bare provided so as to interpose therebetween an area of the first signal bumps121or the second signal bumps122coupled to the signal TSVs. Since the dummy bump arrays15aand15bhave the same configuration, the dummy bump array15awill primarily be described below.

The dummy bump array15aincludes a first dummy bump group151formed on the first surface P1and a second dummy bump group152formed on the second surface P2. The first and second dummy bump groups151and152have connection arrangements that are different from those of the first and second signal bumps121and122.

Specific configurations of the signal bumps121and122and the signal TSVs will be described below with reference toFIG. 2A. As shown inFIG. 2A, the semiconductor chip10has a silicon substrate21and an insulator layer23formed on the silicon substrate21. The silicon substrate21includes signal TSVs25provided therein. The signal TSVs25extend to part of the insulator layer23. The signal TSVs25are coupled to the first signal bumps121. An insulating ring27is formed around each of the signal TSVs25.

Meanwhile, multilayer metallic wirings29are provided in the insulator layer23. The multilayer metallic wirings29are coupled to the second signal bumps122and also electrically coupled to the signal TSVs.

Thus, the first signal bumps121and the second signal bumps122are electrically coupled to each other via the signal TSVs25and the multilayer metallic wirings29.

FIG. 2Billustrates simplified connection arrangements ofFIG. 2A. InFIG. 2B, a set of a signal TSV25and a multilayer metallic wiring is represented by a single line.

FIG. 3Aillustrates connection arrangements of the dummy bumps of the dummy bump groups151and152shown inFIGS. 1A and 1B. The first dummy bumps151d1-151d3are provided on the first surface P1of the semiconductor chip10. The second dummy bumps152d1-152d3are provided on the second surface P2of the semiconductor chip10. The first dummy bumps151d1-151d3and the second dummy bumps152d1-152d3are placed at corresponding positions like in the case of the first signal bumps121and the second bumps122.

Furthermore, the first dummy bumps151d1-151d3are electrically coupled to dummy TSVs31a-31cformed in the silicon substrate21. An insulating ring32is formed around each of the dummy TSVs31a-31c. Specifically, the dummy TSV31ais coupled to a first dummy metallic wiring33ain the insulator layer23. The dummy TSVs31band31care coupled to a second dummy metallic wiring33b. As described above, the signal TSVs and the dummy TSVs have substantially the same configuration.

Meanwhile, the second dummy bumps152d1-152d3differ from the signal bumps121and122shown inFIG. 2in that they are not coupled directly to the corresponding dummy TSVs31a-31c. Specifically, in the example illustrated inFIG. 3A, the dummy bumps152d1and152d2are coupled to each other via a third dummy metallic wiring33c, and the dummy bump152d3is coupled to a fourth dummy metallic wiring33d.

Thus,FIG. 2AandFIG. 3Adiffer from each other in the structure of the multilayer metallic wirings. Specifically, the multilayer metallic wirings shown inFIG. 2Aare used to electrically couple the corresponding first and second signal bumps while the multilayer metallic wirings shown inFIG. 3Ado not couple the corresponding first or second dummy bumps to each other. The multilayer metallic wirings ofFIG. 3Aare used to establish a different electric connection from that ofFIG. 2A. Therefore, connections between the dummy TSVs31a-31cdiffer from the connections of the signal TSVs.

FIG. 3Bshows simplified connections between the dummy bumps151d1-151d3and152d1-152d3illustrated inFIG. 3A. InFIG. 3B, a set of a dummy TSV and a dummy metallic wiring is represented by a single line.

A specific configuration of a semiconductor chip according to an embodiment of the present invention will be described below with reference toFIG. 4.FIG. 4is a cross-sectional view showing a part of the dummy bump array15aillustrated inFIG. 1B. The details of the cross-section are as shown in FIG.3A. The illustrated first dummy bump group151on the first surface P1includes a first dummy bump151d1to an (N+2)th dummy bump151d(N+2). The second dummy bump group152on the second surface P2includes a first dummy bump152d1to an (N+2)th dummy bump152d(N+2).

The first dummy bump151d1and the first dummy bump152d1are connected to each other. Furthermore, the Nth dummy bump151dN and the (N+1)th dummy bump152d(N+1), the (N+1)th dummy bump151d(N+1) and the (N+2)th dummy bump152d(N+2), and the (N+2)th dummy bump151d(N+2) and the Nth dummy bump152dN are respectively connected to each other. Connection parts between the dummy bumps of the first and second dummy bump groups151and152are referred to as interconnection parts.

Two adjacent dummy bumps of the second to Nth dummy bumps151d2-151dN of the first dummy bump group151are coupled to each other. For example, dummy bumps151d2and151d3, dummy bumps151d4and151d5, . . . , and dummy bumps151d(N−1) and151dN are respectively coupled to each other in the first dummy bump group151. Connection parts connecting between the dummy bumps of the first dummy bump group151are referred to as first group connection parts.

Meanwhile, two adjacent dummy bumps of the first to (N−1)th dummy bumps152d2-152d(N−1) of the second dummy bump group152are connected to each other in the illustrated manner. For example, dummy bumps152d1and152d2, dummy bumps152d3and152d4, . . . , and dummy bumps152d(N−2) and152d(N−1) are respectively coupled to each other in the second dummy bump group152. Connection parts between the dummy bump of the second dummy bump group152are referred to as second group connection parts.

Thus, two adjacent dummy bumps on each of the first and second surfaces P1and P2are connected to each other in each surface P1and P2. A connection side of the dummy bumps provided on the first surface P1is opposite to a connection side of the dummy bumps provided on the second surface P2. In other words, when a dummy bump on the first surface P1(e.g., the dummy bump151d3) is connected to a rightward dummy bump, the corresponding dummy bump on the second surface P2(e.g., the dummy bump152d3) is connected to a leftward dummy bump.

Furthermore, configurations of the first and second group connection parts on the first and second surfaces P1and P2shown inFIG. 4may alternatively be expressed in the following manner: It is assumed that numbers 1 to N are assigned to the dummy bumps that constitute each of the first and second group connection parts where N is an even number. In this case, the first group connection parts include connecting portions between the (n+1)th dummy bump and the (n+2) dummy bump adjacent to each other where n is an odd number smaller than N, whereas the second group connection parts include connecting portions between the nth dummy bump and the (n+1)th dummy bump adjacent to each other.

According to the present invention, a plurality of semiconductor chips10each including the dummy bump groups151and152as illustrated inFIG. 4are prepared. Those semiconductor chips are stacked so as to produce a semiconductor device having a multilayer structure. In other words, the semiconductor chips10being stacked have the same structure in configurations of the dummy bump groups151and152and the signal bumps121and122having the same structure.

FIG. 5shows a semiconductor device in which four semiconductor chips10as illustrated inFIG. 4have been stacked. Each of the semiconductor chips101-104has the same structure as the semiconductor chip10illustrated inFIG. 4.FIG. 5only shows the first and second dummy bump groups. A bonded surface1is formed between the first and second semiconductor chips101and102. Similarly, a bonded surface2is formed between the second and third semiconductor chips102and103, and a bonded surface3is formed between the third and fourth semiconductor chips103and104.

InFIG. 5, a first dummy bump151d1of the first dummy bump group of the first semiconductor chip101is connected to a first dummy bump152d1of the second dummy bump group of the semiconductor chip101. Furthermore, the first dummy bump151d1of the first dummy bump group of the first semiconductor chip101is connected to first dummy bumps151d1and152d1of the second semiconductor chip102. Similarly, the first dummy bump151d1of the first dummy bump group of the first semiconductor chip101is electrically connected to first dummy bumps151d1and152d1of the third and fourth semiconductor chips103and104.

Furthermore, a second dummy bump152d2of the second dummy bump group of the first semiconductor chip101is connected to a second dummy bump151d2of the first dummy bump group of the second semiconductor chip102and also connected to a third dummy bump152d3of the first semiconductor chip101via a third dummy bump151d3of the second semiconductor chip102. Other dummy bumps of the first semiconductor chip101and the second semiconductor chip102are connected to each other in the same manner as described above. Thus, dummy bumps of the first semiconductor chip101are successively connected to those of the second semiconductor chip102until a dummy bump151N of the second semiconductor chip102is connected to a dummy bump152N of the first semiconductor chip101.

Those connecting relationships of the dummy bumps similarly apply to connecting relationships of the dummy bumps of the second and third semiconductor chips102and103and also apply to connecting relationships of the dummy bumps of the third and fourth semiconductor chips103and104.

Furthermore, the Nth dummy bump152dN of the second dummy bump group152of the first semiconductor chip101is connected to the Nth dummy bump151dN of the first dummy bump group151of the second semiconductor chip102. The (N+1)th dummy bump152d(N+1) of the first semiconductor chip101is connected to the (N+1)th dummy bump151d(N+1) of the second semiconductor chip102. The (N+2)th dummy bump152d(N+2) of the first semiconductor chip101is connected to the (N+2)th dummy bump151d(N+2) of the second semiconductor chip102. The dummy bumps152d(N+2) and the dummy bumps151d(N+2) provided on the second and third semiconductor chips102and103are connected in the same manner as described above. The third and fourth semiconductor chips103and104are also connected in the same manner.

Specifically, if the rightmost dummy bump151d1illustrated inFIG. 5is defined as a terminal0, a conduction path coupled to the terminal0reciprocally intersects the bonded surface1between the first semiconductor chip101and the second semiconductor chip102and extends to the leftmost dummy bump151d(N+2) of the first semiconductor chip101through the dummy bump151dN of the second semiconductor chip102and the dummy bump152dN of the first semiconductor chip101. If the leftmost dummy bump151d(N+2) is defined as a terminal1, the conduction path from the terminal0to the terminal1intersects the bonded surface1a plurality of times.

Furthermore, a conduction path extending from the terminal0to the bonded surface2is connected to the dummy bump151d2formed on the first surface of the third semiconductor chip103via an inside connection part of the dummy bumps152d1and152d2formed on the second surface of the second semiconductor chip102. The conduction path alternately intersects the bonded surface2between the second semiconductor chip102and the third semiconductor chip103and reaches the dummy bump152dN of the second semiconductor chip102. The conduction path is connected to the dummy bump151d(N+1) of the first semiconductor chip101, which is indicated as a terminal2, via the interconnection parts from the dummy bump152dN. Thus, a conduction path extending across the bonded surface2is formed.

A conduction path extending from the terminal0to the bonded surface3is connected to the dummy bump151d2formed on the first surface of the fourth semiconductor chip104via an inside connection part of the dummy bumps152d1and152d2formed on the second surface of the third semiconductor chip103. The conduction path alternately or reciprocally intersects the bonded surface3between the third semiconductor chip103and the fourth semiconductor chip104and reaches the dummy bump152dN of the third semiconductor chip103. The connection path is connected to the dummy bump151dN of the first semiconductor chip101, which is indicated as a terminal3, via the interconnection parts from the dummy bump152dN. Thus, a conduction path extending across the bonded surface3is formed.

In the semiconductor device having the above structure, since dummy bumps are configured in the aforementioned manner on the first to fourth semiconductor chips101-104, it is possible to examine whether or not any disconnection or opening takes place within the conduction paths formed through the bonded surfaces1-3. Herein, disconnection may include, for example, electrical disconnection caused by shape defects of a dummy TSV or disconnection of a metallic dummy wiring. Opening may include, for example, separation of dummy bumps in a bonded surface, that results from warp of a semiconductor substrate or electrical disconnection that results from interposition of an insulator between dummy bumps.

FIG. 6shows a state of connecting the signal TSVs and the signal bumps121and122of the semiconductor device including the semiconductor chips101-104illustrated inFIG. 5. The signal TSVs are electrically continuously connected from the signal bump121provided on the lower surface of the first semiconductor chip101to the signal bump122provided on the upper surface of the fourth semiconductor chip104. Thus, conduction paths of the signal TSVs and the signal bumps121and122extend in a stacking direction.

With the aforementioned configuration, for example, the present invention can exhibit the following advantageous effects.

When a signal TSV or a signal bump has any defect, a semiconductor device including such a signal TSV or a signal bump becomes defective irrespective of the quality of a dummy TSV and a dummy bump. On the other hand, when a signal TSV or a signal bump has no defect, there is no problem in connection with a semiconductor device including such a signal TSV or a signal bump, even if the aforementioned disconnection or opening takes place in a dummy TSV or a dummy bump. This is because the dummy TSV and the dummy bump are not used in a normal operation of the semiconductor device.

Herein, it is assumed that any defect or malfunction is caused to occur in a dummy TSV and/or a dummy bump of a semiconductor device manufactured by a certain semiconductor manufacturing apparatus and semiconductor devices are subsequently and continuously manufactured by the same semiconductor manufacturing apparatus. In this event, there may be a probability that any malfunction takes place also in the semiconductor devices continuously manufactured by the use of the same semiconductor manufacturing apparatus due to some changes of conditions (size or manufacturing processes of those semiconductor devices), when the malfunction or defect appears in a dummy TSV and/or a dummy bump. Therefore, in consideration of subsequent manufacturing processes, it is preferable to form dummy TSVs and dummy bump without any defects or malfunctions. The present invention is very effective to prevent such possible connection defects that might appear in the future.

The present invention can detect the aforementioned connection defect early and readily with dummy bumps provided on each of semiconductor chips as shown inFIG. 5.

In the above embodiment, the dummy bump arrays15aand15bare arranged as shown inFIG. 1A. The arrangement of the dummy bump arrays is not limited toFIG. 1A. The dummy bump arrays may be formed so as to surround signal bumps as shown inFIGS. 7A and 7B. The dummy bump arrays15cshown inFIGS. 7A and 7Bare close to the signal bumps122.

However, the arrangement of the dummy bump arrays is not limited toFIGS. 7A and 7B. As shown inFIGS. 8A and 8B, the dummy bump arrays15c′ may be arranged at a periphery of a chip. Furthermore, only one dummy bump array may be provided along one side of a chip. Alternatively, two, three, or four dummy bump arrays may be provided along two, three, or four sides of a chip. At any rate, the first and second dummy bump groups151and152may independently be connected to each other on each side of a chip in the same manner as illustrated inFIG. 5, or may be connected to each other in a manner in which they are continuously electrically connected through four sides of a chip. In any event, a conduction path may reciprocally or alternately intersect a bonded surface.

FIGS. 9A and 9Bshow a semiconductor chip10baccording to another embodiment of the present invention. In this example, there are no signal bumps122connected to signal TSVs at a central portion of the semiconductor chip10b. Instead, a dummy bump array15dis arranged straight at the central portion of the semiconductor chip10b. The dummy bump array15dof this example has first and second dummy bump groups151and152provided on a first surface P1and a second surface P2, respectively. For example, those first and second dummy bump groups151and152are connected to each other in the manner illustrated inFIG. 5. With this configuration, a continuity test or a conduction test can readily be performed in a case where semiconductor chips10bare stacked.

FIGS. 10A and 10Bshow a semiconductor chip10caccording to still another embodiment of the present invention. In this example, no signal bumps122are disposed in a crisscross area left at a central portion of the semiconductor chip11c. Instead, a dummy bump array15eis arranged in the crisscross area in a cruciform manner. The dummy bump array15eof this example has a first dummy bump group151provided on a first surface P1and a second dummy bump group152provided on a second surface P2. The first and second dummy bump groups151and152may independently be connected to each other on each of the two crossed lines, or may be connected to each other in a manner in which they are continuous on the two crossed lines.

In the above examples, the first and second dummy bump groups are arranged straight. The arrangement of the dummy bump groups according to the present invention is not limited to a straight arrangement. The dummy bump groups may be arranged on curved lines.

FIG. 11shows an interposer chip40having a multilayer structure (e.g., the multilayer structure shown inFIGS. 5 and 6). Specifically, the interposer chip40forms a part of a semiconductor device together with the stacked semiconductor chips101-104illustrated inFIG. 5or the like. For example, the interposer chip40may be an interface chip of a DRAM.

The illustrated interposer chip40has a rectangle shape and has signal TSVs41provided at a central area thereof and two lines of conduction measurement TSVs42arranged linearly in two areas interposing the central area. For example, each line of the conduction measurement TSVs42is connected to the first dummy bump group151of the first semiconductor chip101ofFIG. 5. Furthermore, the conduction measurement TSVs42are connected to judgment circuits44via connection lines43for conduction. Each of the judgment circuits44is connected to input/output signal pads45. In this example, the input/output signal pads45are used for input and output of normal input/output signals and also used for input of bond state judgment control signals and output of measurement results during conduction measurement.

As is apparent from the description in connection withFIG. 5, a conduction measurement is performed for judging a bonding state of bonded surfaces1,2, and3. The number of signal pads45that are also used for judging a bonding state might be at least the sum of the number corresponding to the number of the terminals0-3(used to measure the bonded surfaces1,2, and3) and the number of pads (used to input control signals for judging or detecting each bonding state).

Each of the judgment circuits44shown inFIG. 11has a configuration illustrated inFIG. 12. Specifically, the judgment circuit44is connected to the input/output signal pads45. In response to the bond state judgment control signals, the judgment circuit44selects the connection lines43for conduction and outputs output signals from the selected connection lines43for conduction to the input/output pads corresponding to the bonded portions. Specifically, the judgment circuit44may be formed of a MOS transistor as shown inFIG. 13. The illustrated MOS transistor comprises an N-channel MOS transistor. The MOS transistor has a drain and a source connected to the connection line43for conduction and the input/output pad45. In response to a bond state judgment control signal supplied to the gate, the MOS transistor is turned on so as to output a signal from the connection line43for conduction, i.e., a signal indicative of a result of a continuity test, to the input/output pad.

An operation of the judgment circuit44shown inFIGS. 12 and 13in an example of the semiconductor device illustrated inFIG. 5will be described with reference toFIG. 14. It is assumed that a signal having a high level is supplied to the input/output pad45corresponding to the terminal0ofFIG. 5and that a signal indicative of a continuity test result is outputted to the input/output pads45corresponding to the terminals1,2, and3.

The example ofFIG. 14shows the case where there is no defect in a bonded surface including a conduction path between the terminal0and the terminal1but a bonding malfunction, such as an open state, is caused to occur in a bonded surface which includes a conduction path between the terminal0and the terminal2.

Under the circumstances, the continuity test is performed by supplying a signal of a high level to the input/output pad45corresponding to the terminal0which is used as a common terminal.

In addition, a bonding state judgment control signal is given at a time point t1and the connection line43connected to the terminal1is selected so that a signal indicative of a continuity test result is outputted to the input/output pad45from the terminal1. In this case, since there is no problem in the conduction path between the terminal0and the terminal1, as mentioned above, a signal of a high level supplied to the terminal1is outputted from the input/output pad45corresponding to the terminal1.

On the other hand, the conduction path between the terminal0and the terminal2is in an opened state, as mentioned above. Therefore, even if an input/output pad45corresponding to the terminal2is selected by the bonding state judgment control signal and the signal of the high level is supplied from the terminal0, the input/output pad45corresponding to the terminal2is held at the low level.

Accordingly, the bonding states of the bonded surfaces between the semiconductor chips101-104can be judged by detecting and measuring the level of signals outputted to the input/output pads45.

Specifically, a method of measuring a semiconductor device as described in connection withFIGS. 11-14is to measure bonding states of a semiconductor device in which semiconductor chips having through silicon vias (TSVs) are bonded to and stacked on each other via signal bumps. Dummy bumps are arranged, and wirings are formed between the dummy bumps of the bonded semiconductor chips so that a conduction path or paths are formed between the dummy bumps. Specifically, wirings are provided between two semiconductor chips stacked in the vertical direction so as to couple the dummy bumps to each other with a single continuous stroke.

According to the present invention, bonding states of the stacked semiconductor chips can be measured by judging whether or not conduction paths are formed between the dummy bumps thus configured.

Next, a specific configuration of a semiconductor chip according to still another embodiment of the present invention will be described with reference toFIG. 15.FIG. 15shows a dummy bump array which corresponds toFIG. 4but which is different fromFIG. 4in inside wirings of first and second dummy bump groups161and162formed on a first surface P1and a second surface P2of a semiconductor chip10. The illustrated first dummy bump group161includes a first dummy bump161d1to a fifteenth dummy bump161d15. Similarly, the second dummy bump group162includes a first dummy bump162d1to a fifteenth dummy bump162d15. Dummy bumps of the first and second dummy bump groups161and162are placed at positions having one-to-one relationship.

The connection arrangements or inside wirings of the first and second dummy bump groups161and162illustrated inFIG. 15differ from the connection arrangements or inside wirings of the first and second dummy bump groups151and152illustrated inFIG. 4. Specifically, the first and second dummy bump groups161and162illustrated inFIG. 16are internally connected in a manner as indicated by solid lines and broken lines. More specifically, every other dummy bump is internally connected to each other, as shown by the solid lines or broken lines and two dummy bumps connected to each other by the solid lines are located alternately with two dummy bumps connected by the broken lines in the vertical direction, as illustrated inFIG. 16.

Specifically, odd-numbered dummy bumps of the first dummy bump group161provided on the first surface P1(e.g., dummy bumps161d1and161d3, dummy bumps161d5and161d7, and so on) are connected to each other, as shown by the solid lines. Odd-numbered dummy bumps of the second dummy bump group162provided on the second surface P2(e.g., dummy bumps162d3and162d5, dummy bumps162d7and162d9, and so on) are connected to each other by the solid lines. A first one162d1of the odd-numbered dummy bump of the second surface P2is connected to an external circuit or another odd-numbered dummy bump (not shown).

Furthermore, even-numbered dummy bumps of the first dummy bump group161provided on the first surface P1(e.g., dummy bumps161d4and161d6, dummy bumps161d8and161d10) are connected to each other, as shown by the broken lines. A leading one161d2of the even-numbered dummy bumps of the first surface P1is connected to an external circuit or another even-numbered dummy bump (not shown).

Even-numbered dummy bumps of the second dummy bump group162provided on the second surface P2(e.g., dummy bumps162d2and162d4, dummy bumps162d6and162d8) are connected to each other, as shown by the broken lines. Thus, even-numbered dummy bumps on the first and second surfaces P1and P2are each connected to each other alternately in the vertical direction. This shows that each of the odd-numbered dummy bumps and the on the second surface P2is connected in series to each other when another semiconductor chip is stacked and the odd-numbered and the even-numbered dummy bumps of another semiconductor chip are mounted to those of the illustrated semiconductor chip.

As mentioned before, the first and the second dummy bumps162d1aand162d2on the second surface P2may be connected to the external terminal.

The dummy bump161d14as an even-numbered end on the first surface P1and the dummy bump161d15as an odd-numbered end on the first surface P1are connected to different ground sources (e.g., VSSQ and VSS), respectively. Those ground sources may be supplied from different external terminals or may be supplied through the signal TSVs.

FIG. 16shows a semiconductor device in which two semiconductor chips10illustrated inFIG. 15are stacked.

InFIG. 16, a short-circuit portion50is caused to occur between the first and second semiconductor chips101and102. In the illustrated example, the short-circuit portion50appears between the eleventh dummy bump162d11and the twelfth dummy bump162d12on the second surface P2of the first semiconductor chip101and between the eleventh dummy bump161d11and the twelfth dummy bump161d12on the first surface P1of the second semiconductor chip102.

It is possible to detect generation or appearance of the short-circuit portion50shown inFIG. 16when the semiconductor chips101and102being stacked have dummy bump groups with the configuration illustrated inFIG. 15.

As described above, the fourteenth and fifteenth dummy bumps161d14and161d15of the first and second semiconductor chips101and102are coupled to different ground sources, respectively.

In the illustrated example, a continuity test between the second dummy bump161d2and the fourteenth dummy bump161d14is performed by applying a voltage to the second dummy bump161d2of the second semiconductor chip102from the external circuit through a broken line BR1. In this case, a current path is formed from the second dummy bump162d1of the second semiconductor chip toward the second dummy bump162d2of the first semiconductor chip. Thereafter, the current path extends through the internal wirings shown by the broken lines drawn in the first and the second semiconductor chips to the fourteenth dummy bump161d14of the second semiconductor chip connected to the ground source.

The current path indicated by the broken lines passes through the dummy bumps162d12and161d12at the short-circuit portion50and reaches the fourteenth dummy bump162d14of the second semiconductor chip102.

Similarly, as indicated by solid lines, another current path is formed so as to pass through the eleventh dummy bump162d11(on the first semiconductor chip101) and161d11(on the second semiconductor chip102) at the short-circuit portion50and reach the fifteenth dummy bump161d15of the second semiconductor chip102.

Since the fourteenth dummy bump162d14and the fifteenth dummy bump161d15of the second semiconductor chip102are respectively grounded, two DC connection paths are formed via the short-circuit portion50.

Thus, any defect or malfunction, such as the short-circuit portion50, can be detected in the multilayer semiconductor device by detecting formation of a plurality of DC paths.

It is preferable to perform a measurement using dummy bumps according to the present invention before a continuity test of testing signal TSVs which are individually contacted.

Thus, the present invention is featured by introducing, in semiconductor chips, a TSV internal wiring pattern for completing a conduction path on bonding those semiconductor chips, and by confirming a conduction path by the use of an interposer chip.

FIG. 17illustrates still another embodiment of the present invention. For example, the semiconductor device includes a controller chip60located as the lowermost layer and a plurality of memory chips which are stacked on the controller chip60and which are called first, second, third, and fourth memory chips from the bottom ofFIG. 17. InFIG. 17, each of the first, the second, the third, and the fourth memory chips61,62,63, and64includes a plurality of dummy bumps on each of the first and the second surfaces and wirings connected to the bumps within each memory chip in a manner similar toFIG. 5. Each of the first through the fourth memory chips61to64is divided into a chip selection section A, a control section B, and a dummy bump connection section C.

Although the first through the fourth memory chips are mounted as the plurality of the memory chips on the controller chip60in the illustrated example, the present invention is applicable to the semiconductor device which includes at least the first and the second memory chips61and62. In this connection, the first and the second memory chips61and62may be simply called first and second chips, respectively, while the control chip60may be called a third chip, for convenience of description. The third memory chip63may be called a fourth chip. In this event, the dummy bumps which are formed on the second surface of the first chip61and which are directed upwards ofFIG. 17may refer to as first bumps and the wirings of the first chip61may refer to as first wirings. Likewise, the dummy bumps on the first and the second surfaces of the second chip62may be called second and third bumps, respectively, and the wirings of the second chip62may be called second wirings. Similarly, the dummy bumps on the first and the second surfaces of the third memory chip (fourth chip)63may be called fourth and fifth bumps, respectively, and the wirings of the third memory chip63may be called third wirings.

It is to be noted that the first wirings, the first bumps, the second wirings, and the second bumps constitute a single electrical path and are arranged in series with one another in the single electrical path, when the first and the second chips are stacked to each other in the manner mentioned inFIG. 5. This applies to the semiconductor device that further includes the third memory chip63and/or the fourth memory chip64in addition to the first and the second memory chips61and62.

In the foregoing embodiments, different terminals (the terminals1-3inFIG. 5) are individually used to perform a test of conduction paths in each of bonded surfaces. In the present embodiment, however, it is to be noted that a single terminal is used in common to perform such a test.

Now, conduction paths indicated by C inFIG. 17correspond to the conduction paths of the dummy bumps and the dummy TSV inFIG. 5. An end of each conduction path in each of bonded surfaces is connected in common to a terminal Vb (which may be supplied with Vss, for example, and which is attached to the control chip60). Another end of each conduction path is electrically selected by an electrical control operation, and, as a result, the selected end alone is connected to a terminal Va (which is supplied with Vdd, for example, and which is attached to the control chip60also). Thus, the test is performed only for the selected bonded surface. As an example of performing the test, description will be made about testing a bonded surface2between the second and the third memory chips62and63.

In this event, a plurality of control terminals (specified by CONTROL inFIG. 17) of the control chip60are supplied with predetermined signals, respectively in a state in which different voltages Vdd and Vss are supplied to the terminals Va and Vb, respectively. Specifically, those predetermined signals include an MRS signal (MRS terminal) which is activated to initiate a mode for performing the test and which serves as a signal for selecting one of chip selection terminals (CS) which correspond to the first through the fourth memory chips61to64and which serve to select the bonded surface2. The CS terminals <0:3> illustrated inFIG. 17are numbered from0to3from the left side ofFIG. 17. In this example, the third memory chip63from the bottom is to be activated. In this event, CS <0:3> are put into 1000 (CS0→3from the left side of the figure). The control circuit Cont is configured to activate an output signal when CS is selected and MRS is activated. In the illustrated example, only the control circuit Cont of the third memory chip63from the bottom activates an output signal, whereas the control circuits Cont of the other memory chips deactivate an output signal. A transfer gate TG is a circuit that becomes an ON-state when the output signal from the control circuit Cont is activated. As a result, only the third memory chip63becomes an ON-state. Consequently, a conduction path can selectively be formed only in the bonded surface2.

Herein, it is possible to apply TSV configurations shown inFIG. 2AandFIG. 3A, connections of dummy bumps shown inFIG. 4andFIG. 15, and arrangements of dummy bumps shown inFIG. 7A,FIG. 8A,FIG. 9A, andFIG. 10Ato this embodiment illustrated inFIG. 17.

INDUSTRIAL APPLICABILITY

The present invention is not limited to a DRAM and is also applicable to general semiconductor devices, such as a central processing unit (CPU), a micro control unit (MCU), a digital signal processor (DSP), an application specific integrated circuit (ASIC), an application specific standard product (ASSP) as long as the semiconductor devices have a chip-on-chip configuration (COC) with through electrodes (TSVs). Furthermore, devices to which the present invention has been applied can also be used as semiconductor devices for system-on-chip (SOC), multichip package (MCP), package-on-package (POP), and the like.