SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME

The present disclosure provides a semiconductor device and a method of fabricating the same, the semiconductor device includes a substrate, an insulating layer, a plurality of bit lines, and a bit line contact. The insulating layer is disposed on the substrate, the bit lines are disposed on the insulating layer, and the bit line contact is disposed between the bit lines and the substrate, to electrically connect the bit lines, wherein the bit line contact comprises a first conductive layer and a first oxidized interface layer, and a bottommost surface of the first oxidized interface layer is lower than a top surface of the insulating layer. Through these arrangements, the semiconductor device includes the bit line contact having a composite semiconductor layer, which is allowable to improve the structural reliability of the bit lines and the bit line contacts, thereby achieve better performance.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present disclosure relates generally to a semiconductor device and a method of fabricating the same, and more particularly to a semiconductor memory device and a method of fabricating the same.

2. Description of the Prior Art

With the trend of miniaturization of various electronic products, the design of semiconductor memory devices must meet the requirements of high integration and high density. For a dynamic random access memory (DRAM) having recessed gate structures, because the carrier channel of which is relatively long in the same semiconductor substrate compared with that of the DRAM without recessed gate structures, the leakage current from the capacitor structure in the DRAM can be reduced. Therefore, the DRAM having recessed gate structures has gradually replaced DRAM having planar gate structures under the current mainstream development trend.

Generally, the DRAM having recessed gate structure is constructed by a large number of memory cells which are arranged to form an array area, and each of the memory cells can be used to store information. Each memory cell may include a transistor element and a capacitor element connected in series, which is configured to receive voltage information from word lines (WL) and bit lines (BL). In order to fulfill the requirements of advanced products, the density of memory cells in the array area must be further increased, which increases the difficulty and complexity of related fabricating processes and designs. Therefore, the present technology needs further improvement to effectively improve the efficiency and reliability of related memory devices.

SUMMARY OF THE INVENTION

An object of the present disclosure is to provide a semiconductor device and a fabricating method thereof, where a bit line contact having a composite conductive layer is formed to improve the structural reliability of the bit lines and the bit line contact. Then, the semiconductor device may therefore achieve better functions and performance.

To achieve the aforementioned objects, the present disclosure provides a semiconductor device including a substrate, an insulating layer, a plurality of bit lines, and a bit line contact. The insulating layer is disposed on the substrate, and the bit lines are disposed on the substrate. The bit line contact is disposed between the bit lines and the substrate, to electrically connect the bit lines, wherein the bit line contact includes a first conductive layer and a first oxidized interface layer, and a bottommost surface of the first oxidized interface layer is lower than a top surface of the insulating layer.

To achieve the aforementioned objects, the present disclosure provides a method of fabricating a semiconductor device including the following steps. Firstly, a substrate is provided, and an insulating layer is formed on the substrate. Next, a plurality of bit lines is formed on the substrate, and a bit line contact is formed between the bit lines and the substrate, to electrically connect the bit lines, wherein the bit line contact includes a first conductive layer and a first oxidized interface layer, and a bottommost surface of the first oxidized interface layer is lower than a top surface of the insulating layer.

DETAILED DESCRIPTION

To provide a better understanding of the presented disclosure, preferred embodiments will be described in detail. The preferred embodiments of the present disclosure are illustrated in the accompanying drawings with numbered elements. In addition, the technical features in different embodiments described in the following may be replaced, recombined, or mixed with one another to constitute another embodiment without departing from the spirit of the present disclosure.

Please refer toFIG.1toFIG.9, which illustrate schematic diagrams of a semiconductor device100according to the first embodiment of the present disclosure, withFIG.1,FIG.3, andFIG.8respectively illustrating a top view of the semiconductor device100during various fabricating processes, and withFIG.2,FIG.4toFIG.7, andFIG.9respectively illustrating a cross-sectional view of the semiconductor device100during various fabricating processes. Firstly, as shown inFIG.1andFIG.2, a substrate110, for example a silicon substrate, a silicon containing substrate (such as SiC or SiGe), or a silicon-on-insulator (SOI) substrate, is provided, and at least one shallow trench isolation (STI)112is formed in the substrate110, to define a plurality of active areas (AAs)114, with all of the active areas114being surrounded by the shallow trench isolation112, as shown inFIG.1.

Precisely speaking, the active areas114is parallel extended with each other along a same direction Dl, with each of the active areas114having the same length and the same pitch, wherein the direction D1for example intersects and is not perpendicular to the y direction or the x direction, as shown inFIG.1, but not limited thereto. In one embodiment, the formation of the shallow trench isolation112is accomplished by firstly performing an etching process to form a plurality of trenches (not shown in the drawings), followed by filling in an insulating material (such as silicon oxide or silicon oxynitride) in the trenches, but is not limited thereto.

Also, at least two regions are defined on the substrate110, for example including a memory cell region (not shown in the drawings) being relative higher integrity and a periphery region (not shown in the drawings) being relative lower integrity, and a plurality of buried word lines120is formed in the substrate110, within the memory cell region, wherein the buried word lines120are parallelly extended with each other in the y-direction, to intersect with each of the active areas114. In one embodiment, the formation of the buried word lines120includes but not limited to the following steps. Firstly, a plurality of trenches (not shown in the drawings) parallelly and separately extended along the y-direction is formed in the substrate110. Next, a dielectric layer (not shown in the drawings) covering entire surfaces of each of the trenches, a gate dielectric layer (not shown in the drawings) covering surfaces of a bottom portion of each of the trenches, and a gate electrode (not shown in the drawings) filled in the bottom portion of each of the trenches, are sequentially formed in each of the trenches. Then, after removing the gate electrode and the gate dielectric layer formed in a top portion of each of the trenches through an etching process, a covering layer (not shown in the drawings) filled in the top portion of each of the trenches is formed. Accordingly, the covering layer may therefore have a top surface leveled with a top surface of the substrate110, so that, the gate electrode, the gate dielectric layer and the dielectric layer formed in the substrate110may together form the buried word lines120of the semiconductor device100for accepting or transmitting the voltage signals from memory cells (not shown in the drawings).

As shown inFIG.1andFIG.2, an insulating layer130, and a mask layer140are sequentially formed on the substrate110, entirely covering the top surface of the substrate110, wherein the insulating layer130preferably includes a composite structure for example including an oxide layer132-anitride layer134-anoxide layer136(ONO) structure, but is not limited thereto. The mask layer140for example includes a semiconductor layer142and a protection layer144formed sequentially on the insulating layer130, wherein the semiconductor layer142for example includes a semiconductor material like doped silicon, doped phosphorus or silicon phosphide (SiP), and preferably includes doped silicon, but not limited thereto. The protection layer144for example includes a material like silicon oxide or silicon oxynitride (SiON), but not limited thereto.

Then, as shown inFIG.3andFIG.4, a plurality of contact openings146is formed in the mask layer140, with each of the contact openings146penetrating through the protection layer144, the semiconductor layer142, and the insulating layer130to extend into the substrate110, and with a portion of the active areas114being exposed from the contact openings146. The formation of the contact openings146includes but not limited to the following steps. Firstly, a mask structure (not shown in the drawings) is formed on the substrate110, with the mask structure for example including a sacrificial layer (not shown in the drawings, for example including an organic dielectric layer), a silicon-containing hard mask (SHB, not shown in the drawings), and a patterned photoresist layer (not shown in the drawings) stacked one over another on the protection layer144. The patterned photoresist layer includes at least one pattern for defining the contact openings146, and an etching process such as a dry etching process is performed through the patterned photoresist layer, to form the contact openings146in the insulating layer130, the semiconductor layer142, and the protection layer144, wherein each of the contact openings146is in alignment with each of the active areas114. It is noted that, each of the contact openings146is formed between two adjacent ones of the buried word lines120as shown inFIG.3, so that, a portion of the active areas114(namely, the substrate110) may be exposed from the bottom of the contact openings146, as shown inFIG.4. After that, the mask structure is completely removed.

As shown inFIG.5, a first semiconductor material layer152is formed on the substrate110, entirely covering the mask layer140, and surfaces of each contact opening146without filling the contact openings146, wherein the first semiconductor material layer152for example includes a semiconductor material like doped silicon, doped phosphorus, or silicon phosphide, but not limited thereto. It is noted that, in the present embodiment, after forming the first semiconductor material layer152, the lattice structure of the surface of the first semiconductor material layer152is destroyed by breaking the vacuum or introducing oxygen, so that the lattice structure of a semiconductor material layer deposited on the top in the subsequent process will not continuously grow along the lattice structure of the first semiconductor material layer152, so as to obtain a relatively smaller grain size. Accordingly, a first oxidized interface layer153is further formed on the surface of the first semiconductor material layer152, and the first oxidized interface layer153for example includes silicon oxide, phosphorus oxide or silicon phosphorus oxide, and preferably includes silicon phosphorus oxide, but not limited thereto. In one embodiment, since the first oxidized interface layer153is conformally formed on the surface of the first semiconductor material layer152, an U-shaped cross-section may be obtained thereby within each contact opening146, as shown inFIG.5.

Furthermore, it is also known that, a thickness of the first oxidized interface layer153is quite thin, for example being about angstroms to 1 angstroms, and which may not affect the electrical connection between the bit line contacts and other elements. In one embodiment, the formation of the first semiconductor material layer152is for example carried out through a deposition process such as a chemical vapor deposition (CVD) process, and preferably through a selective epitaxial growing (SEG) process, to precisely monitor a thickness T1of the first semiconductor material layer152, preferably being about 20-50 nanometers (nm), but not limited thereto. In this way, the first oxidize interface layer153formed over the first semiconductor material layer152may therefore obtain a relative lower forming position within each contact opening146, for example being lower than the top surface of the insulating layer130. In one embodiment, a bottommost surface B1of the first oxidized interface layer153is for example lower than the top surface of the insulating layer (namely, the top surface of the oxide layer136), even lower than the bottommost surface of the insulating layer130(namely, the bottom surface of the oxide layer132), as shown inFIG.5.

As shown inFIG.6, a deposition process such as a chemical vapor deposition is performed, to sequentially form a second semiconductor material layer154and a third semiconductor material layer156on the substrate110, wherein the second semiconductor material layer154entirely covers the first semiconductor material layer152, to partially fill in each contact opening146, and the third semiconductor material layer156further covers on the second semiconductor material layer154, to fill up the rest space of each contact opening146. The second semiconductor material layer154and the third semiconductor material layer156for example include a semiconductor material like doped silicon, doped phosphorus, or silicon phosphide, but not limited thereto. In one preferably embodiment, the forming process of the second semiconductor material layer154and the third semiconductor material layer156may be different from that of the first semiconductor material layer152, for example, the second semiconductor material layer154and the third semiconductor material layer156may be formed through a CVD process, and the first semiconductor material layer152maybe formed through a SEG process, but not limited thereto. Also, the first semiconductor material layer152, the second semiconductor material layer154, and the third semiconductor material layer156include the same material like silicon phosphide, but not limited thereto.

As the semiconductor material of the second semiconductor material layer154may also generate a second oxidize interface layer155through breaking vacuum or introducing oxygen, the second oxidize interface layer155may be formed between the second semiconductor material layer154and the third semiconductor material layer156, and also, to obtain an U-shaped cross-section within each contact opening146, as shown inFIG.6. The second oxidized interface layer155for example includes silicon oxide, silicon nitride, or silicon phosphorus oxide, and preferably includes silicon phosphorus oxide, but not limited thereto. It is noted that, a thickness of the second oxidized interface layer155is also quite thin, for example being about 0.01 angstroms to 1 angstroms, and which will not affect the electrical connection between the bit line contacts and other elements formed in the subsequent processes. Furthermore, it is also noted that, the second semiconductor material layer154and the third semiconductor material layer156stacked sequentially on the first semiconductor material layer152preferably include a relative smaller thickness T2, for example being about 10-20 nanometers, but not limited thereto. Accordingly, the second semiconductor material layer154and the third semiconductor material layer156stacked over the first semiconductor material layer152may therefore obtain a relative smaller grain size and a relative finer lattice structure, so as to present a further smooth surface.

As shown inFIG.7, an etching process such as a dry etching process is performed, to completely remove the third semiconductor material layer156, the second semiconductor material layer154, and the first semiconductor material layer152covered on the top surface of the mask layer140, and to further remove the mask layer140underneath, with the protection layer144being completely removed and with the semiconductor layer142being partially removed. Meanwhile, the third semiconductor material layer156, the second semiconductor material layer154, and the first semiconductor material layer152filled in each contact opening146are all partially removed, so that, a semiconductor layer152a, a first oxidized interface layer153a, a first conductive layer154a, a second oxidized interface layer155a, and a second conductive layer156aare sequentially formed within each contact opening146, thereby forming a plurality of bit line contacts (BLC)160filled in each contact opening146respectively, wherein the first oxidized interface layer153aand the second oxidized interface layer155aboth include an U-shape cross-section as shown inFIG.7. Then, the top surface of each of the bit line contacts160may be coplanar with the top surface of the etched semiconductor layer142, as shown inFIG.7.

Following these, a deposition process is then performed to form a barrier material layer162, a metal material layer164, and a covering material layer166stacked sequentially on the semiconductor layer142. Precisely speaking, the barrier material layer162entirely covers the semiconductor layer142and the bit line contacts160, to directly in contact with the semiconductor layer142and the bit line contacts160disposed underneath, and the metal material layer164and the covering material layer166are sequentially covering on the barrier material layer162. In one embodiment, the barrier material layer162for example includes tantalum (Ta) and/or tantalum nitride (TaN), or titanium (Ti) and/or titanium. nitride (TiN), and the metal material layer164for example includes a low-resistant metal like aluminum (Al), titanium, copper (Cu), or tungsten (W), and the covering material layer166for example includes a dielectric material like silicon oxide, silicon nitride, or silicon oxynitride, but is not limited thereto.

Then, as shown inFIG.8andFIG.9, a photolithography process is performed, and the semiconductor layer142, the barrier material layer162, the conductive material layer164, and the capping material layer166stacked sequentially are patterned through a mask layer (not shown in the drawings), to form a plurality of bit lines168extended along the x-direction in the memory cell region of the substrate110, across the active areas114and the buried word lines120. Precisely speaking, each of the bit lines168includes a semiconductor layer142a, a barrier layer162a, a metal layer164a, and a capping layer166astacked sequentially form bottom to top. It is noted that the bit line contacts160are further disposed below a portion of the bit lines168, so that, the portion of the bit lines168may enable to extend into the active areas114of the substrate110, to directly contact the active areas114. The bit line contacts160are also patterned during performing the photolithography process, with the semiconductor layer152aand the first oxidized interface layer153adisposed at two sides of each bit line contact160being partially removed. Then, each of the bit line contacts160may include a composite conductive layer, which includes the semiconductor layer152a, the first oxidized interface layer153a, the first conductive layer154a, the second oxidized interface layer155a, and the second conductive layer156astacked sequentially, with the first oxidized interface layer153ahaving a linear cross-section, and with the second oxidized interface layer155ahaving an U-shaped cross-section, as shown inFIG.9.

Furthermore, as shown inFIG.8andFIG.9, a deposition process and an etching back process are sequentially performed, to form a plurality of bit line spacers170on two opposite sidewalls of each of the bit lines168, respectively. It is noted that, a portion of the bit line spacers170further extends into active areas114of the substrate110to cover on sidewalls of each of the bit line contacts160, and the portion of the bit line spacers170may directly contact two opposite ends of the linear first oxidized interface layer153a, as shown inFIG.9.

Through the above-mentioned processes, the semiconductor device100according to the first embodiment of the present disclosure is formed. Accordingly to the fabricating method of the present embodiment, the semiconductor layer142entirely covering the substrate110is firstly formed, followed by defining the contact openings146through the semiconductor layer142, and forming the bit line contacts160in the contact openings146. The fabrication of the bit line contacts160is carried out by a multi-stepped deposition process, or by an epitaxial process combined with a deposition process, so that each of the bit line contacts160may therefor obtain a composite conductive layer, which includes the semiconductor layer152a, the first conductive layer154a, and the second conductive layer156astacked sequentially. It is noted that, the semiconductor layer152a, the first conductive layer154a, and the second conductive layer156amay respectively include the same semiconductor material or different semiconductor materials, such as doped silicon, doped phosphorus, or silicon phosphide, and preferably all include silicon phosphide. Also, the first conductive layer154aand the second conductive layer156adisposed over the semiconductor layer152aare preferably include a relative smaller thickness T2, for example being about 10-20 nanometers, so that, the top surface of each of the bit line contacts160may obtain a relative smaller grain size and a relative finer lattice structure, to present further smooth surface thereby.

Furthermore, while the composite conductive layer is formed after forming the semiconductor material, through breaking vacuum or introducing oxygen, the lattice structure at the top of the semiconductor material is broken, and the first oxidized interface layer153ais additionally formed between the semiconductor layer152aand the first conductive layer154a, and the second oxidized interface layer155ais additionally formed between the first conductive layer154aand the second conductive layer156a. The first oxidized interface layer153aincludes a linear cross-section, and the second oxidized interface layer155astill includes an U-shaped cross-section, and the first oxidized interface layer153aand the second oxidized interface layer155aare respectively disposed at the bottom surface and the top surface of the first conductive layer154a, but not limited thereto. The thickness of the first oxidized interface layer153aand the second oxidized interface layer155ais quite thin, for example being about 0.01-1 angstroms. In this way, the existing of first oxidized interface layer153aand the second oxidized interface layer155awill not affect the electrical connection between each bit line168and each bit line contact160, and which may further improve the grain size and the lattice structure of the bit line contacts160(being more smooth), so as to improve the structural defects of the semiconductor material, such as excessive grain size and rough surface layer, caused by thicker stacked films. Then, the fabricating method of present disclosure is allowable to form the semiconductor device100with better performances under a simplified process flow.

People in the art shall easily realize that the semiconductor device and the method of fabricating the same in the present disclosure are not limited to the aforementioned embodiment, and may include other examples. The following description will detail the different embodiments of the semiconductor device and method of fabricating the same in the present disclosure. To simplify the description, the following description will detail the dissimilarities among the different embodiments and the identical features will not be redundantly described. In order to compare the differences between the embodiments easily, the identical components in each of the following embodiments are marked with identical symbols.

Please refer toFIG.10andFIG.11, which illustrate schematic diagrams of a semiconductor device300according to the second embodiment in the present disclosure. The forming process at the front end of the present embodiment is substantially the same or similar to those in the first embodiment, and those steps will not be redundantly described herein. The difference between the present embodiment and the aforementioned first embodiment is in that the contact openings of the present embodiment include a relative smaller diameter, and each of the bit line contacts260formed subsequently in the contact openings may therefore include the first oxidized interface layer253aand the second oxidized interface layer255aboth in an U-shaped cross-section.

Precisely speaking, as shown inFIG.10, a SEG process and a deposition process are sequentially performed on the substrate110, to form a first semiconductor material layer252, a second semiconductor material layer254, and a third semiconductor material layer256stacked from bottom to top, wherein the first semiconductor material layer252, the second semiconductor material layer254, and the third semiconductor material layer256for example include a semiconductor material like doped silicon, doped phosphorus or silicon phosphide, and preferably includes silicon phosphide, but not limited thereto. Also, as the semiconductor materials of the first semiconductor material layer252, the second semiconductor material layer254, and the third semiconductor material layer256are treated by breaking the vacuum or introducing oxygen, a first oxidized interface layer253is additionally formed between the first semiconductor material layer252and the second semiconductor material layer254, and a second oxidized interface layer255is additionally formed between the second semiconductor material layer254and the third semiconductor material layer256. The first oxidized interface layer253and the second oxidized interface layer255respectively include a quite thin thickness, for example being about 0.01-1 angstroms, and which will not affect the electrical connection between each bit line contact and other elements formed subsequently. In one embodiment, the first oxidized interface layer253and the second oxidized interface layer255for example include silicon oxide, phosphorus oxide, or silicon phosphorus oxide, and preferably both include silicon phosphorus oxide, but not limited thereto.

Then, an etching process and a deposition process are sequentially performed, to form a barrier material layer (not shown in the drawings), a metal material layer (not shown in the drawings), and a capping material layer (not shown in the drawings) stacked sequentially, after partially removing the third semiconductor material layer256, the second semiconductor material layer254, the first semiconductor material layer252, and the mask layer140. Following these, after performing the photolithography process, the barrier material layer, the metal material layer, and the capping material layer stacked sequentially are patterned to form a plurality of bit lines268. As shown inFIG.11, each of the bit lines268includes a semiconductor layer242a, a barrier layer262a, a metal layer264a, and a capping layer266astacked from bottom to top. It is noted that, the bit line contacts260are disposed under a portion of the bit lines268, to further extend into the active areas114of the substrate110to directly contact thereto. Furthermore, the bit line contacts260are also patterned through the photolithography process, to partially remove the first semiconductor material252disposed at two sides of each bit line contact260. Accordingly, each of the bit line contacts260may include a composite conductive layer, which includes the semiconductor layer252a, the first oxidized interface layer253a, the first conductive layer254a, the second oxidized interface layer255a, and the second conductive layer256astacked sequentially, with the first oxidized interface layer253aand the second oxidized interface layer255aboth having an U-shaped cross-section, as shown inFIG.11.

After that, as shown inFIG.11, a deposition process and an etching back process are sequentially performed, to form a plurality of bit line spacers270on two opposite sidewalls of each of the bit lines268, respectively. It is noted that, a portion of the bit line spacers270further extends into active areas114of the substrate110to cover on sidewalls of each of the bit line contacts260, and the portion of the bit line spacers270may directly contact two opposite ends of the U-shaped first oxidized interface layer253a, as shown inFIG.11.

Through the above-mentioned processes, the semiconductor device300according to the second embodiment of the present disclosure is formed. Accordingly to the fabricating method of the present embodiment, the formation of the bit line contacts260is also carried out by an epitaxial process combined with a deposition process, so that each of the bit line contacts260may therefor obtain a composite conductive layer, which includes the semiconductor layer252a, the first conductive layer254a, and the second conductive layer256astacked sequentially. It is noted that, the semiconductor layer252a, the first conductive layer254a, and the second conductive layer256amay respectively include the same semiconductor material or different semiconductor materials, such as doped silicon, doped phosphorus, or silicon phosphide, and the first oxidized interface layer253ais additionally formed between the semiconductor layer252aand the first conductive layer254a, and the second oxidized interface layer255ais additionally formed between the first conductive layer254aand the second conductive layer256a, with the first oxidized interface layer253aand the second oxidized interface layer255aboth including an U-shaped cross-section. In this way, the existing of first oxidized interface layer253aand the second oxidized interface layer255awill not affect the electrical connection between each bit line268and each bit line contact260, and which may further improve the grain size and the lattice structure of the bit line contacts260(being more smooth), so as to improve the structural reliability of the semiconductor device300, and to promote the device performance thereby.