Fully testable DCVS circuits with single-track global wiring

Groups of DCVS (Differential Cascode Voltage Switch) circuits are interconnected by single-track data transfer connections. Each group contains one or more DCVS tree circuits, through which data signals propagate only on dual-track connections. In each group, at least one DCVS tree circuit is configured as an input boundary tree, and at least one tree circuit is configured as an output boundary tree. All data inputs externally applied to a group, are transferred only through input boundary trees of the group, and all data outputs transferred out of a group leave the group only through output boundary trees of the group. If a group has only a single tree, that tree serves as input and output boundary tree of the group. Each input boundary tree of each group has one or more associated primary shift register latch (SRL) circuits through which all external data inputs to that tree are transferred. Such external data inputs are received through the single-track connections mentioned above. The primary SRL circuits are also used to present predeterminable test data inputs to respective trees, and to collect primary test data outputs representing signals received through the single-track connections. In such usage, the SRL circuits are connected as a scannable shift register. Each output boundary tree has an exclusive-OR (XOR) circuit for indicating if the respective tree is in a legal or illegal state. The XOR circuits connect to secondary scannable SRL circuits for external presentation of illegal state indication. The primary test data outputs together with the externally presented illegal state indications form a basis for detecting and locating any faulty state in any group.

FIELD OF THE INVENTION 
This invention relates to differential cascode voltage switch (DCVS) 
circuits, and particularly to arrangements permitting efficient layout and 
accurate testing of such circuits. 
BACKGROUND OF THE INVENTION 
DCVS (Differential Cascode Voltage Switch) circuits, developed for VLSI 
applications, are capable of providing high functional density and 
performance. Such circuits comprise "tree" clusters of active device pairs 
which operate as discrete logic circuits. Each tree receives complementary 
input signals on pairs of conductors, and produces an output signal having 
a predetermined logical relation to the input signals. The output signal, 
presented on a pair of conductors, is in a "legal" state only if the 
signals on the respective conductors are at different levels, and in an 
"illegal" state otherwise. 
Presently, the paired conductors on which input and output signals are 
conveyed relative to trees are termed "2-track" or "dual-track" 
connections". Dual-track connections consume more chip space and are more 
difficult to route through a chip than single-track (single wire) 
connections. However, single-track connections have not been considered 
feasible because they permit propagation of faulty signals between trees 
with essentially indeterminate effects. 
It is also desirable to be able to test integrated logic circuits on a 
chip, including DCVS tree circuits. A simple presently well known testing 
technique involves arranging circuits to be tested in "level sensitive 
scan design" (LSSD) groups, and providing "scannable shift register latch" 
(SRL) circuits integral with each group. Test signals scanned into the SRL 
latches are applied to respective groups, the groups are operated for a 
clock cycle during which signals representing states of groups are scanned 
into SRL circuits (usually of other groups), and the signals then stored 
in the SRL circuits are scanned out for evaluation (fault detection and 
location) either off chip or on chip. The LSSD grouping is supposed to 
ensure that any fault conditions in a group can be detected and traced by 
one or more scan in/scan out operations. 
Arrangements of this kind and their rationale are presented in "A Logic 
Design Structure For LSI Testability", E. B. Eichelberger et al, 
Proceedings of the 14th Design Automation Conference (1977), IEEE, pages 
206-215 (hereafter referred to as the "Eichelberger paper"). 
It has been proposed also to use scannable shift register latches to 
facilitate testing of DCVS circuits. Refer, for instance, to U.S. Pat. 
Nos. 4,698,830 and 4,656,417, and IBM Technical Disclosure Bulletin, Vol. 
27, No. 10B, pages 6148-6152, J. B. Hickson et al, "Testing Scheme For 
Differential Cascode Voltage Switch Circuits. However, these proposals 
have a number of shortcomings in that their implementations would require 
departure from existing (and proven) LSSD design practices, and not 
alleviate the previously stated use of 2-track connections between DCVS 
circuit groups. 
Accordingly, the aim of this invention is to provide an arrangement of DCVS 
circuits which allows for routing of signals between DCVS circuits over 
single-track connections (hereafter also termed single-track global 
interconnect wiring), while permitting complete and accurate testing such 
that all faults including illegal output states of DCVS tree circuits are 
detectable and traceable. 
OBJECTS OF THE INVENTION 
An object of the present invention is to provide an arrangement of DCVS 
circuits in which signals are conveyed between DCVS tree circuits, or 
groups of circuits, on single-track connections while the circuits are so 
configured that all faults, including illegal states of DCVS tree 
circuits, are fully detectable and traceable (to a circuit at fault). 
Another object is to provide an arrangement of DCVS circuits in which 
signals are conveyed between DCVS tree circuits through single-track 
connections, and in which signals representing test data can be applied to 
and collected from such circuits in a manner permitting accurate detection 
and location of faults. 
Another object is to provide an arrangement of DCVS circuits which is 
configurable in accordance with existing LSSD design practices, which can 
be efficiently integrated with scannable shift register (SRL) latches for 
testability, which allows for signals to be transferred between DCVS 
circuits via single-track connections, and which allows for accurate 
detection and location of all faults including illegal output states of 
individual DCVS trees. 
SUMMARY OF THE INVENTION 
In accordance with the invention, SRL latch circuits for LSSD logic testing 
are integrated with groups of DCVS tree circuits (logic groups) so that 
test signals are scannable into each group and signals representing 
resulting group states after a cycle of operation are scannable out of 
each group. Each group comprises one or more DCVS trees. The SRL circuits 
are interconnected globally so that signals can be scanned into all groups 
from a single source (either a single pin on the chip or a single bit 
output of one on-chip source device), and so that all group states can be 
scanned out to one evaluating circuit or device (either through one or 
more pins on the chip or through one or more input connections to an 
on-chip device). Furthermore, signal connections between groups are 
carried on single-track connections between tree outputs of groups and 
inputs of SRL circuits in other groups. 
Groups are operated in "normal" and "test" modes. In normal mode, each 
group receives inputs representing logical arguments, from other groups 
(or off-chip) sources via single-track connections to respective SRL 
circuits, and produces output signals which are forwarded to other groups 
(on the same chip or other chips) via single-track connections to SRL 
circuits of the other groups. In test mode, test data is scanned serially 
into the SRL circuits of all groups, groups are operated for one or more 
clock cycles, and signals representing resulting group states are scanned 
serially out of the SRL circuits of all groups. 
Since illegal states of DCVS trees are not always detectable by the test 
mode operations, the groups are augmented by exclusive-OR circuits for 
positively detecting such illegal states. The exclusive-OR circuits 
receive dual-track outputs of DCVS tree circuits and produce an illegal 
indication when respective tree outputs are at equal (or almost equal) 
voltage levels. When the tree outputs are at unequal levels, the 
exclusive-OR circuits produce outputs representing legal indications. 
In preferred embodiments, the exclusive-OR circuits are connected to 
secondary SRL latch circuits so that their legal/illegal state indications 
can be scanned out efficiently (e.g., for evaluation with test signals 
scanned out from the primary SRL circuits through which test signals are 
applied to the groups). In several of these embodiments, each exclusive-OR 
circuit is connected to an associated SRL circuit to form a circuit 
combination presently called an exclusive-OR scannable circuit array 
(XSCA) unit. The secondary SRL circuits in the XSCA units and the primary 
SRL circuits for test inputs may be scanned out in coordination for test 
analysis.

DETAILED DESCRIPTION OF THE INVENTION 
Referring to FIG. 1, six groups of logic circuits are shown at 1-6. The 
groups are also denoted Logic Groups 1-6 (LG1-LG6). Multiple such groups 
may be contained on a single LSI semiconductor chip. Elements of typical 
group LG1 are illustrated in FIG. 2 and discussed below. 
In accordance with the present invention, signals transferred between such 
logic groups are conveyed over single-track (single conductor) connections 
suggested at 7-12. As shown later, each group may contain multiple DCVS 
trees and other circuits. Within each group, signals are conveyed between 
trees and other circuits over dual-track (2 wire) connections. Multiple 
inputs to LG 1 are indicated specifically at 13. For reasons which will be 
apparent as the description of FIG. 2 unfolds, three of these inputs are 
shown by solid lines preceded by symbols a, b and c, while other inputs to 
the same group are suggested by broken lines. 
Referring to FIG. 2, typical logic group LG1, shown at 17, comprises shift 
register latch (SRL) circuits 18-20 in which (single-track) group inputs 
(a, b, c, . . . ) are buffered, DCVS tree circuits 21-23 having dual-track 
connections to outputs of the SRL circuits, and other DCVS tree circuits 
24-26 at which respective group outputs 27-29 are formed. DCVS trees such 
as 21-23, which receive buffered group inputs directly from SRL circuits, 
are referred to hereafter as "input boundary trees". DCVS trees such as 
24-26, from which group output signals are transferred, are referred to 
hereafter as output boundary trees. Although not shown in this Figure, a 
group may have intermediate trees which are neither at input nor output 
boundaries of the group. 
During normal mode system operations (normal and test mode system 
operations are defined later), Tree 21 receives a 2-track input from SRL 
18, which corresponds to true and complement forms of the group input 
signal "a", and other 2-track inputs suggested symbolically at 30, and 
produces a 2-track output signal having a particular logical relation to 
its input. True (T) and complement (C) outputs of tree 21 are applied as a 
dual-track input to tree 24, along with other inputs to the latter tree 
suggested symbolically at 31. Tree 24 produces true and complement outputs 
also designated T and C respectively. 
As suggested at 30 and 31, each tree may have plural two-track inputs, but 
each tree has only a single two-track output. The additional two-track 
inputs suggested at 30 and 31 originate either externally, and are 
conveyed through other SRL circuits (not shown), or they originate at 
outputs of trees within the group and are conveyed directly (without 
intervening SRL's). 
True phase outputs T of the output boundary trees 24-26, are presented at 
27-29 for single-track connection to other groups (on the same chip or 
other chips). Full 2-track outputs of output boundary tree 24-26 are 
coupled as inputs to test circuits 32-34, each of the latter designated as 
an "exclusive-OR scanning circuit arrray" (XSCA). 
Each logic group such as LG1 is operated in two modes; a normal mode and a 
test mode. In normal mode, data signals such as a, b, c, . . . (from other 
groups or other chips) are transferred over single-track connections to 
SRL circuits such as 18-20 in parallel. SRL circuits within each group, 
and between groups, are interconnected as a serial bit shifting array, and 
in test mode test bits are shifted serially into the SRL circuits 
(typically from a source external to the chip), clocked in parallel from 
the SRL's to respective input boundary trees, and resulting signals 
received in the SRL's from their single-track inter-group input data 
connections are shifted out of the SRL's (typically to a test evaluating 
system or circuit external to the chip). 
For test mode operations, SRL circuits such as 18-20 in each group are 
connected as a "scannable" test bit shifting array, with the first circuit 
18 having a scan-in input SI, and the last circuit 20 having a scan-out 
output SO. Furthermore, SRL circuits in all groups on a chip are 
interconnected "globally" as a bit shifting array, with the SO output of 
each group other than a "last" group connecting to an SI input of a 
following group, and the SI input of each group other than a first group 
connecting to the SO output of a preceding group. The SI input of the 
first group and SO output of the last group connect to respective pins on 
the chip, and through those pins to test circuits or systems external to 
the chip. 
In test mode, all SRL circuits on a chip are initialized to a predetermined 
test state by a "scan in" operation, in which test bits are shifted into 
the SRL's (from a source external to the chip thru a single SI input pin 
on the chip). Upon completion of the scan in function, the test signals 
stored in the SRL's are clocked in parallel into respective input boundary 
trees such as 21-23, to establish a desired initial test state in those 
tree circuits. The resulting interaction between the trees in the group 
causes logically related output signals to appear at output boundary 
trees. The latter signals are latched into SRL circuits of the same or 
other groups (through single-track connections between the output boundary 
tree circuits and SRL circuits in the other groups). These states of the 
SRL's, representing conditions received through their single-track 
inter-group data input connections, are examined as test indications by 
means of a "scan out" process in which states instantly stored in all 
SRL's are shifted serially out to an examining circuit or system through 
one or more SO pins on the chip. 
XSCA circuits such as 32-34 are also interconnected as a scannable array, 
and used as auxiliary test circuits for detecting illegal states of a 
group. Recall that illegal states occur when outputs of a DCVS tree are at 
equal levels. As explained later, test data scanned out of SRL circuits 
such as 18-20 is useful only for detecting faults other than illegal tree 
states, and data scanned out of the XSCA circuits is needed for detecting 
and tracing illegal states. 
Each XSCA circuit contains an exclusive-OR circuit which determines if the 
2-track input to the respective circuit represents a legal or illegal 
state. If the XSCA input is legal the signals on the two input tracks are 
at different voltage levels, and the output of the exclusive-OR circuit is 
at a first voltage level associated with that condition. However, if the 
inputs to the exclusive-OR circuit are illegal, they are at the same (or 
about the same) voltage level, and the output of that circuit goes to a 
second voltage level different from the first level thereby distinguishing 
the illegal condition. 
An SRL circuit is shown schematically in FIG. 2A, a typical DCVS tree 
circuit is shown schematically in FIG. 2B, and a typical XSCA circuit is 
shown schematically in FIG. 2C. These circuits and their operations are 
described next. 
The SRL circuit shown schematically in FIG. 2A, and its use in LSSD circuit 
testing operations in general, are fully described in the previously cited 
Eichelberger paper. The circuit shown in FIG. 2A is representative of all 
presently considered SRL's, but its inputs correspond specifically to 
those associated with SRL 18 of FIG. 2. 
Each SRL comprises a pair of latch circuits L1 and L2. Latch circuit L1 has 
a normal data input "a" connected to the respective single-track data 
connection (the path of signal "a" in respect to SRL 18 of FIG. 2), and a 
test data input SI connected to the SI test bit source of the respective 
SRL (see FIG. 2). Latch circuit L1 has a normal mode clock signal input 
"C" and a test mode clock signal input "A". Latch L2 has a data input 
connected to the output of L1, a clock signal input "B", and a 2-track 
output T, C at which signals appear that represent respective true and 
complement phases of a signal stored in that latch. 
In normal mode operations clock signal C is activated to transfer data from 
single track input "a" into L1. At the same time, clock signal B is 
activated so that the signal latched into L1 flows instantly into L2 and 
is simultaneously latched there. The signal held in L2 is applied 
subsequently as a logical input argument to the respective input boundary 
tree, during a "validation" operation conducted relative to all DCVS trees 
as described below with respect to FIG. 2B, and the latter operations 
determine tree and logic group outputs which are subsequently latched into 
SRL's by a next clock signal C. 
In test mode operations, clock signal A is activated to shift a test bit 
into L1 from the SI input of that latch (which is connected either to an 
SI input pin of the chip or an L2 output of another SRL circuit as 
explained previously). Thereafter, clock signal B is activated to shift 
data from L1 into L2. If the SRL is other than the last element in the 
associated scannable array, the true output T of L2 is coupled to the SI 
input of a latch L1 in a next SRL. If the SRL is the last scannable 
element of a logic group or chip, the True output of L2 appears at the SO 
output of the respective group or chip. 
The exemplary DCVS tree circuit shown in FIG. 2B represents the DCVS 
equivalent of a 5 way exclusive OR logic circuit. A similar circuit is 
shown in a paper by Hickson et al "Testing Scheme For Differential Cascode 
Voltage Switch Circuits", published in the IBM Technical Disclosure 
Bulletin, Vol. 27 No. 10B, March 1985 (pages 6148-6152). That paper also 
describes an arrangement for testing DCVS tree circuits using SRL 
circuits; but without the present features of providing single-track 
connections between groups of DCVS tree circuits with full testability for 
detection and location of all faults including illegal states. 
As shown in FIG. 2B, a DCVS tree circuit comprises a logical transfer 
section indicated generally at 35 and a load circuit section indicated 
generally at 36. Logical transfer section 35 receives multiple two track 
inputs, illustrated presently as true and complement phases of signals a, 
b, . . , e. Load circuit 36 produces the two track result output of the 
tree, illustrated presently as true and complement phases of signal Q. 
As is presently well known in the art, DCVS tree circuits such as that 
shown in FIG. 2B are operated cyclically in precharge and validation 
phases. Charges developed between the logic transfer and load circuit 
sections, during precharge, discharge through the transistors in the load 
section and some of the transistors in the logic transfer section; the 
circuit paths through the latter section being established as a function 
of states of respective inputs a-e. In the particular circuit illustrated, 
output Q is active/high after validation if and only if true phases of 
inputs a-e are all coincidentally active/high. 
Referring to FIG. 2C, typical XSCA circuit 32 (of FIG. 2) comprises an 
exclusive-OR circuit 37 and an SRL circuit 38. SRL 38 has a data input SI, 
for input of data stored in another secondary SRL, a normal data input 
coupled to the output of exclusive-OR 37, and 3 clock signal inputs (for 
clocks A, B and C) indicated collectively at 39. SRL circuits such as 38 
are presently termed "secondary SRL circuits" to distinguish them from the 
"primary SRL circuits" shown at 18-20 in FIG. 2. 
The secondary and primary SRL circuits are similar in form, but the 
secondary SRL circuits are connected only for scan out and do not have a 
scan in mode comparable to that of the primary SRL circuits. During 
operations of logic groups LG (FIGS. 1, 2), exclusive-OR circuits 37 are 
activated by C clock signals to transfer legal or illegal state 
indications, and simultaneously, secondary SRL circuits such as 38 are 
activated by B clock signals to store state signals transferred by 
respective exclusive-OR circuits 37. Accordingly, when so activated, a 
secondary SRL circuit will store an illegal state indication if and only 
if both inputs to the associated exclusive-OR circuit 37 are at the same 
level (and otherwise a legal state indication is stored). 
Faults detectable by scan out of the primary SRL circuits such as 18-20 
(FIG. 2) are presently termed class 1 faults, and faults detectable by 
scan out of secondary SRL circuits are termed class 2 faults. Class 2 
faults are associated only with detectable illegal states and class 1 
faults are all faults other than detectable illegal states (including 
faults due to malfunctions in primary SRL's, faults caused by multiple 
stuck conditions in trees or other malfunctions in trees). That all class 
1 faults are detectable and traceable (as to origin) may be appreciated by 
considering that states scanned into the primary SRL circuits in test mode 
are both predetermined and can be chosen by design to evoke scan out 
indications of class 1 faults that are detectable and traceable (to 
specific primary SRL or tree circuits). 
In conjunction (or association) with the scan out of test data from primary 
SRL's, secondary SRL's may be scanned out. If directed to an off-chip 
evaluating circuit, data of a secondary scan out can be transferred either 
through the same SO pin as data of the related primary scan out or through 
a separate pin. By its position in the secondary scan out sequence, a bit 
representing an illegal state indication may be correlated to an illegal 
state (class 2) fault in either an output boundary tree coupled to a 
specific XSCA circuit or in the set of trees which affect inputs of that 
circuit. Any other fault--i.e., class 1 fault--is detectable through 
evaluation of data produced in (one or more) primary scan outs. Thus, by 
conjointly evaluating data recovered from both primary and secondary scan 
outs, the source of any fault indication can be traced to a specific tree 
or SRL circuit within a specific logic group. 
Variations of the XSCA circuit configuration just described relative to 
FIGS. 2 and 2C, are discussed next with reference to FIGS. 3-5. In these 
figures, the primary SRL's are not shown for clarity, but it should be 
understood that they are present in essentially the same positions as 
shown in FIG. 2. 
In FIG. 3, a set of five output boundary trees of a logic group, shown at 
40, has outputs coupled to five associated XOR (exclusive-OR) circuits 41, 
for developing fault indications relative to the associated set of trees. 
XOR circuits 41 have their outputs coupled through one AND circuit 42 to 
the fault data input of only one (secondary) SRL circuit 43. By comparison 
to the XSCA configuration exemplified in FIGS. 2 and 2C, it is seen that 
SRL 43 and its associated circuits are capable of providing almost the 
same range of (class 2) fault indication as five of the XSCA circuits of 
FIG. 2; and can do so with four fewer SRL circuits and one additional AND 
circuit. It is understood that AND 42 transfers a fault indication to SRL 
43 if and only if one or more of the five associated XOR circuits 41 is 
indicating a (class 2) fault. 
A point to note however is that if more than one XOR 41 is indicating a 
class 2 fault condition, the existence of those conditions (as 2 discrete 
faults), and locations of circuits responsible therefor, would be more 
difficult to trace than a comparable set of conditions presented to the 
XSCA configuration of FIGS. 2 (wherein each fault indication is scanned 
out through a separate SRL). 
In FIG. 3, the logic group containing the trees 40 is shown as containing 
10 output boundary trees; the 5 indicated at 40 and another set of 5 
indicated generally at 44, the latter set having a separate associated set 
of XOR's which interacts through one AND circuit and another secondary SRL 
circuit to provide a separate scan out indication. The intent here is to 
show that in a logic group with many output boundary trees, the output 
boundary trees could be grouped into sets of 5 trees (or other numbers of 
trees) for sharing secondary SRL circuits as shown. 
FIG. 4 illustrates an arrangement distinguished by less sharing of 
components than either the arrangement of FIG. 2 or that of FIG. 3. In 
FIG. 4, the output of each tree in a logic group containing 9 trees (trees 
1-9) is coupled for fault detection to a respective XSCA circuit of the 
type shown in FIG. 2C, so that each tree has an associated secondary SRL 
circuit. With this arrangement, a fault indication scanned out of any XSCA 
circuit is traceable directly to the corresponding tree (whereas in FIG. 
2, a fault in any XSCA is traceable to a sub-group of trees consisting of 
one output boundary tree and trees coupled to that boundary tree). 
FIG. 5 shows how the fault indicating arrangement of FIG. 4 can be modified 
to share components with little if any sacrifice of fault location 
resolution capability. In FIG. 5, the XSCA circuits of FIG. 4 are replaced 
by XOR circuits 60, and the trees and their XOR's are configured in 
discrete rows and columns. The XOR's in each row have outputs connected 
through one "row" AND circuit to one (secondary) "row" SRL circuit. Row 
AND and SRL circuits associated with the first and second rows are 
indicated respectively at 61 and 62. The XOR's associated with each column 
have outputs connected through an associated column AND circuit to an 
associated column (secondary) SRL circuit. Associated AND and SRL circuits 
for the first and second columns are indicated respectively at 63 and 64. 
The row and column SRL's are connected into a single scan array. 
Thus, a single class 2 fault in any tree is easily detectable and 
locatable, since corresponding fault indications will register uniquely in 
both the associated row SRL and column SRL, and can be easily correlated 
with the respective tree upon scan out. A point to note here is that if 
more than one tree in any one row (or column) is in a detectable class 2 
fault condition, there will be one fault indication in the associated row 
(or column) SRL and more than one fault indication in the respective 
column (or row) SRL's. Thus, locations of multiple class 2 faults may be 
immediately traceable by this arrangement. 
FIG. 6 illustrates the topological an circuit packaging advantages of 
having the present single-track connections between groups (also termed 
single-track "global" interconnect wiring). This Figure shows 12 logic 
groups LG1-LG12, intended to represent a densely configured arrangement of 
circuits with minimal available space between groups. Some of the 
single-track wiring connections are illustrated, and one in particular is 
cited at 70-72 for explaining advantages of using single-track global 
interconnects for transferring data signals between groups. 
Group LG1 has a data output connected to group LG12 via linear segment 
70-72 of one single track wiring path. Since the space available for 
accommodating the logic groups, their powering conductors and their global 
interconnect wiring would be tightly rationed, in an efficiently packaged 
chip, and since the power and global interconnect wiring may include 
hundreds of conductors requiring placement in spaces not overshadowed by 
the group components, it may be appreciated that conductive elements 
forming a single interconnect path such as 70-72 may have to cross and run 
adjacent to many other conductors with limited separation spacing between 
conductors, and the logistical complexity of placing such wiring increases 
in proportion to the distance between the origin and destination groups. 
Furthermore, the spacing between such conductors is constrained by 
considerations of restricting crosstalk/noise between conductors. Now, if 
global interconnect wiring were the conventional dual-track form, instead 
of the present single-track form, the number of interconnect wiring 
segments to be placed within a given segment of chip space would double 
and the cross-talk constraints upon the segments would become increasingly 
severe.