Apparatuses, methods, and systems for instructions to compartmentalize code

Systems, methods, and apparatuses relating to instructions to compartmentalize memory accesses and execution (e.g., non-speculative and speculative) are described. In one embodiment, a compartment manager circuit is to determine, when a compartment control register of a hardware processor core is set to an enable value, that a first subset of code requested for execution on the hardware processor core in user privilege is within a first compartment of memory, load a first compartment descriptor for the first compartment into one or more registers of the hardware processor core from the memory, check if the first compartment is marked in the first compartment descriptor, within the one or more registers of the hardware processor core, as a management compartment, and, when the first compartment is marked in the first compartment descriptor as the management compartment, allowing the first subset of the code within the first compartment to load a second compartment descriptor for a second compartment of the memory into the one or more registers of the hardware processor core from the memory, switching execution from the first subset of code within the first compartment to a second subset of code in user privilege within the second compartment, allowing speculative memory accesses for the second subset of code only within the second compartment, and preventing a memory access outside of the second compartment for the second subset of code as indicated by the second compartment descriptor stored within the one or more registers of the hardware processor core.

TECHNICAL FIELD

The disclosure relates generally to electronics, and, more specifically, an embodiment of the disclosure relates to circuitry to implement instructions to compartmentalize code.

BACKGROUND

A processor, or set of processors, executes instructions from an instruction set, e.g., the instruction set architecture (ISA). The instruction set is the part of the computer architecture related to programming, and generally includes the native data types, instructions, register architecture, addressing modes, memory architecture, interrupt and exception handling, and external input and output (I/O). It should be noted that the term instruction herein may refer to a macro-instruction, e.g., an instruction that is provided to the processor for execution, or to a micro-instruction, e.g., an instruction that results from a processor's decoder decoding macro-instructions.

DETAILED DESCRIPTION

A (e.g., hardware) processor (e.g., having one or more cores) may execute instructions (e.g., a thread of instructions) to operate on data, for example, to perform arithmetic, logic, or other functions. For example, software may request an operation and a hardware processor (e.g., a core or cores thereof) may perform the operation in response to the request. In certain embodiments, a processor includes hardware and/or instruction(s) to compartmentalize code (e.g., memory accesses, execution, and/or access to architectural and micro-architectural state, etc., for that code). For example, instruction(s) to provide scalable software compartmentalization. Software sandboxing may be used in browsers or other just-in-time workloads such as code written in a general-purpose language (e.g., a class-based, object-oriented language) or code written in a scripting language (e.g., a just-in-time complied language). However, certain embodiments of software sandboxing have limited resiliency against logic flaws and memory corruption attacks which can be used for type-confusion, use-after-free, and/or information disclosure attacks leading to sandbox evasion. Certain speculative cache side-channel attacks may utilize untrusted code execution in a process to leak sensitive data with software-only sandboxing.

Thus, certain embodiments herein are directed to a hardware processor (e.g., architecture and an instruction set architecture (e.g., ISA) for hardware compartmentalization (e.g., hardware sandboxing) to split a process into sub-processes and restrict data accesses for sub-process components within the process. Certain embodiments herein split memory (e.g., a single address space in memory) into multiple compartments managed and/or controlled by the hardware processor (and/or instructions) to prevent any data access outside a compartment unless explicitly shared. Certain embodiments herein allow speculative (e.g., memory) accesses are permitted within a compartment and/or prevent speculative (e.g., memory) accesses across (e.g., between) compartments. Certain embodiments herein utilize compartments that are not merely process isolation, e.g., where the impact of using separate processes to isolate components that normally operate within the same address space are decreased performance (e.g., due to scheduling and an increased number of instructions (assuming the number of instructions per cycle (IPC) is the same) and memory costs (e.g., due to replicated runtime infrastructure).

Certain embodiments herein utilize software components, software flows, and a processor (e.g., and its ISA) to enable: efficient hardware-based isolation between compartments, a (e.g., privileged) management compartment for permission(s) management, an un-compartment for native (e.g., legacy) code compatibility, and/or shared memory between compartments for communications between compartments. Certain embodiments herein thus provide increased performance for light-weight contexts for hardware-isolated compartments (e.g., sandboxes) and/or scalability for a large number of compartments for server usages, such as, but not limited to, a scripting language engine, intermediate binary representations, scripting language isolates, scripting language nodes, etc. Certain embodiments use a compartment dedicated to providing communication services between compartments via shared memory.

In certain embodiments, the software components include a management runtime that manages permissions for other compartments (e.g., non-management compartments), an un-compartment mode of operation of each processor core (e.g., logical processor implemented by the core) that provides a default permission set for native (e.g., existing) code, and a compartment runtime mode of operation of the processor where software provides services to the compartmentalized (e.g., sandboxed) code.

In certain embodiments, the hardware components include a compartment (e.g., sandbox) descriptor that is an in-memory structure interpreted by the processor as a compartment (e.g., sandbox) control structure, a linear prefix that is the linear address range for which compartments are enabled (e.g., where an address generation unit of a processor core enforces compartments to operate within this linear address region), a linear slice of 1 of N regions corresponding to the compartment accessible memory (e.g., where an address generation unit of a processor core enforces permissions based on the region), a linear slice protection key that indicated the permissions for the N slices (e.g., with a register holding the readable, writeable, and/or executable (RWX) permissions for each slice (e.g., 64B slice, 4 KB slice, 2 MB slice, 1 GB slice, any other multiple of 64B, or any other slice size) for a compartment, and/or compartmentalization instructions (e.g., SBXxx instructions) for compartmentalization that are used by the operating system (OS) and/or the management compartment. In one embodiment, the memory slices correspond to linear memory that is backed by volatile memory (e.g., DRAM) or to btye-addressable persistent memory, including configurations such as one-level memory (1LM) and two-level memory (2LM).

In one embodiment, compartmentalization hardware touch points can be broken down to support in following areas: control structures management by OS and new instructions for management runtime, instruction handling in a compartment, and memory access handling in a compartment. Turning now toFIG. 1, an example core architecture is depicted.FIG. 1illustrates a block diagram of a computer system100including a hardware processor core109that includes a compartment manager110(e.g., compartment manager circuit) according to embodiments of the disclosure. Processor core109includes multiple components (e.g., microarchitectural prediction and caching mechanisms) that may be shared by multiple contexts. For example, branch target buffer (BTB)126, instruction cache132, and/or return stack buffer (RSB)144may be shared by multiple contexts.

Certain embodiments include a compartment manager110to utilize the hardware components and/or instruction(s) to compartmentalize code (e.g., memory and cached micro-architectural state for the code), for example, to allow or deny speculative memory accesses. Speculative execution (e.g., and speculative memory accesses) may be used by a processor (e.g., processor core109) to improve performance. In one embodiment of speculative execution, instructions are executed ahead of knowing that they are required, such that without speculative execution, the processor would need to wait for prior instructions to be resolved before executing subsequent ones. By executing instructions speculatively, performance can be increased by minimizing latency and extracting greater parallelism. The results may be discarded if it is discovered that the instructions were not needed after all. One form of speculative execution involves the control flow of a program, e.g., instead of waiting for all branch instructions to resolve to determine which operations are needed to execute, the processor predicts the control flow (e.g., using branch predictor125). The predictions may be correct, which allows high performance to be achieved by hiding the latency of the operations that determine the control flow and increasing the parallelism the processor can extract by having a larger pool of instructions to analyze. However, if a prediction is wrong, then the work that was executed speculatively is discarded and the processor will be redirected to execute down the correct instruction path in certain embodiments.

Depicted computer system100includes a branch predictor125and a branch address calculator142(BAC) in a pipelined processor core109(1)-109(N) according to embodiments of the disclosure. Referring toFIG. 1, a pipelined processor core (e.g.,109(1)) includes an instruction pointer generation (IP Gen) stage111, a fetch stage130, a decode stage140, and an execution stage150. In one embodiment, processor100includes multiple cores109(1-N), where N is any positive integer. In another embodiment, processor100includes a single core. In certain embodiments, each processor core109(1-N) instance supports multithreading (e.g., executing two or more parallel sets of operations or threads on a first and second logical core), and may do so in a variety of ways including time sliced multithreading, simultaneous multithreading (e.g., where a single physical core provides a logical core for each of the threads that physical core is simultaneously multithreading), or a combination thereof (e.g., time sliced fetching and decoding and simultaneous multithreading thereafter). In the depicted embodiment, each single processor core109(1) to 109(N) includes an instance of branch predictor125. Branch predictor125may include a branch target buffer (BTB)126. Branch predictor125may be coupled to a branch resolution unit (BRU)156(e.g., in execution circuit154). BRU156may insert a special instruction, prior to the indirect branch instructions, to cause a store of the branch targets in the branch registers (e.g., within branch predictor125). For example, when the compiler code104is translating a “high level” indirect branch instruction into machine level instruction, the compiler code104will generate a set_BR instruction, that is to be executed prior the actual indirect branch instruction, in certain embodiments.

In certain embodiments, branch target buffer126stores (e.g., in a branch predictor array) the predicted target instruction corresponding to each of a plurality of branch instructions (e.g., branch instructions of a section of code that has been executed multiple times). In the depicted embodiment, a branch address calculator (BAC)142is included which accesses (e.g., includes) a return stack buffer144(RSB). In certain embodiments, return stack buffer144is to store (e.g., in a stack data structure of last data in is the first data out (LIFO)) the return addresses of any CALL instructions (e.g., that push their return address on the stack).

Branch address calculator (BAC)142is used to calculate addresses for certain types of branch instructions and/or to verify branch predictions made by a branch predictor (e.g., BTB). In certain embodiments, the branch address calculator performs branch target and/or next sequential linear address computations. In certain embodiments, the branch address calculator performs static predictions on branches based on the address calculations.

In certain embodiments, the branch address calculator142contains a return stack buffer144to keep track of the return addresses of the CALL instructions. In one embodiment, the branch address calculator attempts to correct any improper prediction made by the branch predictor125to reduce branch misprediction penalties. As one example, the branch address calculator verifies branch prediction for those branches whose target can be determined solely from the branch instruction and instruction pointer.

In certain embodiments, the branch address calculator142maintains the return stack buffer144utilized as a branch prediction mechanism for determining the target address of return instructions, e.g., where the return stack buffer operates by monitoring all “call subroutine” and “return from subroutine” branch instructions. In one embodiment, when the branch address calculator detects a “call subroutine” branch instruction, the branch address calculator pushes the address of the next instruction onto the return stack buffer, e.g., with a top of stack pointer marking the top of the return stack buffer. By pushing the address immediately following each “call subroutine” instruction onto the return stack buffer, the return stack buffer contains a stack of return addresses in this embodiment. When the branch address calculator later detects a “return from subroutine” branch instruction, the branch address calculator pops the top return address off of the return stack buffer, e.g., to verify the return address predicted by the branch predictor125. In one embodiment, for a direct branch type, the branch address calculator is to (e.g., always) predict taken for a conditional branch, for example, and if the branch predictor does not predict taken for the direct branch, the branch address calculator overrides the branch predictor's missed prediction or improper prediction.

The core109inFIG. 1includes circuitry to validate branch predictions made by the branch predictor125. Each branch predictor125entry (e.g., in BTB126) may further includes a valid field and a bundle address (BA) field which are used to increase the accuracy and validate branch predictions performed by the branch predictor125, as is discussed in more detail below. In one embodiment, the valid field and the BA field each consist of one-bit fields. In other embodiments, however, the size of the valid and BA fields may vary. In one embodiment, a fetched instruction is sent (e.g., by BAC142from line137) to the decoder146to be decoded, and the decoded instruction is sent to the execution circuit (e.g., unit)154to be executed, for example, with any memory accesses requests to be serviced by address generation unit158(e.g., the unit that calculates an address used by the core to access (e.g., main) memory102). In one embodiment, the (e.g., linear) address checks for a compartment are performed at the address generation unit158.

In one embodiment, the branch instructions stored in the branch predictor125are pre-selected by a compiler as branch instructions that will be taken. In certain embodiments, the compiler code104, as shown stored in the memory102ofFIG. 1, includes a sequence of code that, when executed, translates source code of a program written in a high-level language into executable machine code. In one embodiment, the compiler code104further includes additional branch predictor code106that predicts a target instruction for branch instructions (for example, branch instructions that are likely to be taken (e.g., pre-selected branch instructions)). The branch predictor125(e.g., BTB126thereof) is thereafter updated with target instruction for a branch instruction. In one embodiment, software manages a hardware BTB, e.g., with the software specifying the prediction mode or with the prediction mode defined implicitly by the mode of the instruction that writes the BTB also setting a mode bit in the entry.

Memory102may include compartment descriptors160, compartment thread descriptors162, an XSAVE area164(e.g., the location to store an extended processor state into), stack166, shadow stack168, operating system (OS) code174, application (e.g., program) code176, or any combination thereof. In certain embodiments, one or more values of compartment descriptors160and/or compartment thread descriptors162are stored into an XSAVE area164(e.g., an area not accessible by user privilege code).

In certain embodiments, processor core109includes a stack register170and/or a shadow stack register172.

In certain embodiments, one or more shadow stacks may be included and used to protect an apparatus and/or method from tampering and/or increase security. The shadow stack(s) (e.g., shadow stack168inFIG. 1) may represent one or more additional stack type of data structures that are separate from the stack (e.g., stack166inFIG. 1). In one embodiment, the shadow stack (or shadow stacks) is used to store control information but not data (e.g., not parameters and other data of the type stored on the stack, e.g., that user-level application programs are to write and/or modify). In one embodiment, the control information stored on the shadow stack (or stacks) is return address related information (e.g., actual return address, information to validate return address, and/or other return address information). In one example, the shadow stack is used to store copies of a return addresses for a thread, e.g., a return address corresponding to a thread whose context or other data has been previously pushed on the (e.g., data) stack. For example, when functions or procedures have been called, a copy of a return address for the caller may have been pushed onto the shadow stack. The return information may be a shadow stack pointer (SSP), e.g., that identifies the most recent element (e.g., top) of the shadow stack. In certain embodiments, the shadow stack may be read and/or written to in user level mode (for example, current privilege level (CPL) equal to three, e.g., a lowest level of privilege) or in a supervisor privilege level mode (for example, a current privilege level (CPL) less than three, e.g., a higher level of privilege than CPL=3). In one embodiment, multiple shadow stacks may be included, but only one shadow stack (e.g., per logical processor) at a time may be allowed to be the current shadow stack. In certain embodiments, there is a (e.g., one) register170of the processor to store the (e.g., current) stack pointer. In certain embodiments, there is a (e.g., one) register172of the processor to store the (e.g., current) shadow stack pointer.

In embodiments of computing, memory102includes a virtual machine monitor code, e.g., to manage one or more virtual machines (VMs), where a VM is an emulation of a computer system. In certain embodiments, VMs are based on a specific computer architecture and provide the functionality of an underlying physical computer system. Their implementations may involve specialized hardware, firmware, software, or a combination. In certain embodiments, Virtual Machine Monitor (VMM) (also known as a hypervisor) is a software program that, when executed (e.g., in supervisor mode but not in user mode), enables the creation, management, and governance of VM instances and manages the operation of a virtualized environment on top of a physical host machine. A VMM is the primary software behind virtualization environments and implementations in certain embodiments. When installed over a host machine (e.g., processor) in certain embodiments, a VMM facilitates the creation of VMs, e.g., each with separate operating systems (OS) and applications. The VMM may manage the backend operation of these VMs by allocating the necessary computing, memory, storage and other input/output (I/O) resources, such as, but not limited to, an input/output memory management unit (IOMMU). The VMM may provide a centralized interface for managing the entire operation, status and availability of VMs that are installed over a single host machine or spread across different and interconnected hosts. In certain embodiments, switching between VMs requires a switch of the processor core to a supervisor mode (e.g., instead of staying in a user mode).

As discussed below, depicted core (e.g., branch predictor125thereof) includes access to one or more registers. In certain embodiments, core include one or more general purpose register(s)108.

In certain embodiments, each entry for the branch predictor125(e.g., in BTB126thereof) includes a tag field and a target field. In one embodiment, the tag field of each entry in the BTB stores at least a portion of an instruction pointer (e.g., memory address) identifying a branch instruction. In one embodiment, the tag field of each entry in the BTB stores an instruction pointer (e.g., memory address) identifying a branch instruction in code. In one embodiment, the target field stores at least a portion of the instruction pointer for the target of the branch instruction identified in the tag field of the same entry. Moreover, in other embodiment, the entries for the branch predictor125(e.g., in BTB126thereof) includes one or more other fields. In certain embodiments, an entry does not include a separate field to assist in the prediction of whether the branch instruction is taken, e.g., if a branch instruction is present (e.g., in the BTB), it is considered to be taken.

As shown inFIG. 1, the IP Gen mux113of IP generation stage111receives an instruction pointer from line114A. The instruction pointer provided via line115A is generated by the incrementer circuit115, which receives a copy of the most recent instruction pointer from the path113A. The incrementer circuit115may increment the present instruction pointer by a predetermined amount, to obtain the next sequential instruction from a program sequence presently being executed by the core.

In one embodiment, upon receipt of the IP from IP Gen mux113, the branch predictor125compares a portion of the IP with the tag field of each entry in the branch predictor125(e.g., BTB126). If no match is found between the IP and the tag fields of the branch predictor125, the IP Gen mux will proceed to select the next sequential IP as the next instruction to be fetched in this embodiment. Conversely, if a match is detected, the branch predictor125reads the valid field of the branch predictor entry which matches with the IP. If the valid field is not set (e.g., has logical value of 0) the branch predictor125considers the respective entry to be “invalid” and will disregard the match between the IP and the tag of the respective entry in this embodiment, e.g., and the branch target of the respective entry will not be forwarded to the IP Gen Mux. On the other hand, if the valid field of the matching entry is set (e.g., has a logical value of 1), the branch predictor125proceeds to perform a logical comparison between a predetermined portion of the instruction pointer (IP) and the branch address (BA) field of the matching branch predictor entry in this embodiment. If an “allowable condition” is present, the branch target of the matching entry will be forwarded to the IP Gen mux, and otherwise, the branch predictor125disregards the match between the IP and the tag of the branch predictor entry. In some embodiment, the entry indicator is formed from not only the current branch IP, but also at least a portion of the global history.

More specifically, in one embodiment, the BA field indicates where the respective branch instruction is stored within a line of cache memory132. In certain embodiments, a processor is able to initiate the execution of multiple instructions per clock cycle, wherein the instructions are not interdependent and do not use the same execution resources.

For example, each line of the instruction cache132shown inFIG. 1includes multiple instructions (e.g., six instructions). Moreover, in response to a fetch operation by the fetch unit134, the instruction cache132responds (e.g., in the case of a “hit”) by providing a full line of cache to the fetch unit134in this embodiment. The instructions within a line of cache may be grouped as separate “bundles.” For example, as shown inFIG. 1, the first three instructions in a cache line133may be addressed as bundle 0, and the second three instructions may be address as bundle 1. Each of the instructions within a bundle are independent of each other (e.g., can be simultaneously issued for execution). The BA field provided in the branch predictor125entries is used to identify the bundle address of the branch instruction which corresponds to the respective entry in certain embodiments. For example, in one embodiment, the BA identifies whether the branch instruction is stored in the first or second bundle of a particular cache line.

In one embodiment, the branch predictor125performs a logical comparison between the BA field of a matching entry and a predetermined portion of the IP to determine if an “allowable condition” is present. For example, in one embodiment, the fifth bit position of the IP (e.g. IP[4]) is compared with the BA field of a matching (e.g., BTB) entry. In one embodiment, an allowable condition is present when IP [4] is not greater than the BA. Such an allowable condition helps prevent the apparent unnecessary prediction of a branch instruction, which may not be executed. That is, when less than all of the IP is considered when doing a comparison against the tags of the branch predictor125, it is possible to have a match with a tag, which may not be a true match. Nevertheless, a match between the IP and a tag of the branch predictor indicates a particular line of cache, which includes a branch instruction corresponding to the respective branch predictor entry, may about to be executed. Specifically, if the bundle address of the IP is not greater than the BA field of the matching branch predictor entry, then the branch instruction in the respective cache line is soon to be executed. Hence, a performance benefit can be achieved by proceeding to fetch the target of the branch instruction in certain embodiments.

As discussed above, if an “allowable condition” is present, the branch target of the matching entry will be forwarded to the IP Gen mux in this example. Otherwise, the branch predictor will disregard the match between the IP and the tag. In one embodiment, the branch target forwarded from the branch predictor is initially sent to a Branch Prediction (BP) resteer mux128, before it is sent to the IP Gen mux. The BP resteer mux128, as shown inFIG. 1, may also receive instruction pointers from other branch prediction devices. In one embodiment, the input lines received by the BP resteer mux will be prioritized to determine which input line will be allowed to pass through the BP resteer mux onto the IP Gen mux.

In addition to forwarding a branch target to the BP resteer mux, upon detecting a match between the IP and a tag of the branch predictor, the BA of the matching branch predictor entry is forwarded to the Branch Address Calculator (BAC)142. The BAC142is shown inFIG. 1to be located in the decode stage140, but may be located in other stage(s). The BAC of may also receive a cache line from the fetch unit134via line137.

The IP selected by the IP Gen mux is also forwarded to the fetch unit134, via data line135in this example. Once the IP is received by the fetch unit134, the cache line corresponding to the IP is fetched from the instruction cache132. The cache line received from the instruction cache is forwarded to the BAC, via data line137.

Upon receipt of the BA in this example, the BAC will read the BA to determine where the pre-selected branch instruction (e.g., identified in the matching branch predictor entry) is located in the next cache line to be received by the BAC (e.g., the first or second bundle of the cache line). In one embodiment, it is predetermined where the branch instruction is located within a bundle of a cache line (e.g., in a bundle of three instructions, the branch instruction will be stored as the second instruction).

In alternative embodiments, the BA includes additional bits to more specifically identify the address of the branch instruction within a cache line. Therefore, the branch instruction would not be limited to a specific instruction position within a bundle.

After the BAC determines the address of the pre-selected branch instruction within the cache line, and has received the respective cache line from the fetch unit134, the BAC will decode the respective instruction to verify the IP truly corresponds to a branch instruction. If the instruction addressed by BA in the received cache line is a branch instruction, no correction for the branch prediction is necessary. Conversely, if the respective instruction in the cache line is not a branch instruction (i.e., the IP does not correspond to a branch instruction), the BAC will send a message to the branch predictor to invalidate the respective branch predictor entry, to prevent similar mispredictions on the same branch predictor entry. Thereafter, the invalidated branch predictor entry will be overwritten by a new branch predictor entry.

In addition, in one embodiment, the BAC will increment the IP by a predetermined amount and forward the incremented IP to the BP resteer mux128, via data line145, e.g., the data line145coming from the BAC will take priority over the data line from the branch predictor. As a result, the incremented IP will be forwarded to the IP Gen mux and passed to the fetch unit in order to correct the branch misprediction by fetching the instructions that sequentially follow the IP.

In certain embodiments, the compartment manager110manages one of more compartments as discussed herein, e.g., while alleviating information being leaked across compartments by directly or indirectly observing the information stored.

Computing system100(e.g., compartment manager110) may include a control register112(e.g., XCR0 register). In one embodiment, one or more bits of the control register112store a value, and when the value is a first value, the compartmentalization features are enabled for the core109and when the value is a second, different value, the compartmentalization features are disabled for the core109. The control register112may have a format that includes the enable/disable field for memory compartmentalization, and may include one or more of the following: bit0must be 1 (e.g., where an attempt to write 0 to this bit causes a general protection fault (#GP) exception), bit1, if set to 1, the XSAVE feature set (saving state to XSAVE area164) can be used to manage the general purpose registers108(e.g., XMM0-XMM15 in 64-bit mode; otherwise XMM0-XMM7), bit2, is set to 1, advanced vector extension (AVX) instructions can be executed and the XSAVE feature set can be used to manage the upper halves of the general purpose registers (e.g., YMM0-YMM15 in 64-bit mode; otherwise YMM0-YMM7), bit3, if set to 1, memory protection extension (MPX) instructions can be executed and the XSAVE feature set can be used to manage the bounds registers BND0-BND3, bit4, if set to 1, MPX instructions can be executed and the XSAVE feature set can be used to manage the BNDCFGU and BNDSTATUS registers, bit5, if set to 1, AVX-512 instructions can be executed and the XSAVE feature set can be used to manage the opmask registers k0-k7, bit6, if set to 1, AVX-512 instructions can be executed and the XSAVE feature set can be used to manage the upper halves of the general purpose registers108(e.g., ZMM0-ZMM15 in 64-bit mode; otherwise ZMM0-ZMM7), bit7, if set to 1, AVX-512 instructions can be executed and the XSAVE feature set can be used to manage the upper general purpose registers108(e.g., ZMM16-ZMM31, only in 64-bit mode), or bit9, if set to 1, the XSAVE feature set can be used to manage the protection key rights register for user pages (PKRU) register.

Computing system100(e.g., compartment manager110) may include a compartment (e.g., sandbox (SBX)) state register114to store the current state for a compartment, a compartment (e.g., sandbox (SBX)) description pointer to store a pointer to the compartment descriptor160(and/or compartment thread descriptor162) for a particular compartment, a compartment (e.g., sandbox (SBX)) base register118to store the base address for a linear range, a compartment (e.g., sandbox (SBX)) exit instruction pointer (e.g., IP, EIP, or RIP) register120to store the instruction pointer to be used when exiting a compartment, a compartment (e.g., sandbox (SBX)) attribute register122to store one or more bits to indicate if a compartment is a management compartment or not, what, if any, of certain instructions are allowed or disallowed in the compartment, and/or if speculation is allowed or prevented within a compartment), and/or a linear address checking register(s) (LACR)124. Although the above are discussed as being stored in a certain register, it should be understood that other data storage may be used to store the compartment management data, e.g., secure storage within core109when data is loaded from compartment descriptor160(and/or compartment thread descriptor162).

Core109may include a segment register to store a value indicating a current privilege level of software operating on a logical core, e.g., separately for each logical core. In one embodiment, current privilege level is stored in a current privilege level (CPL) field of a code segment selector register of segment register. In certain embodiments, processor core109requires a certain level of privilege (e.g., supervisor privilege instead of user privilege) to perform certain actions, for example, actions requested by a particular logical core (e.g., actions requested by software running on that particular logical core). An instance of a compartment manager110may be in each core109(1-N) of computer system100. A single instance of a compartment manager110may be anywhere in computer system100, e.g., a single instance of compartment manager110used for all cores109(1-N) present.

In one embodiment, model specific registers112include configuration and/or control registers. In one embodiment, control registers are separate/distinct from model specific registers. In one embodiment, one or more (e.g., model specific) registers are (e.g., only) written to at the request of the OS running on the processor, e.g., where the OS operates in privileged (e.g., system) mode, but not for code running in non-privileged (e.g., user) mode. In one embodiment, a model specific register is only be written to by software running in supervisor mode, and not by software running in user mode and/or is only accessible to a management compartment.

In certain embodiments, decoder146decodes an instruction according to this disclosure, and that decoded instruction is executed by the execution circuit154, for example, to manage compartments within memory102. Examples of compartments within memory are discussed below in reference toFIGS. 5, and 11-19.

Each core109of computer system100may be the same (e.g., symmetric cores) or a proper subset of one or more of the cores may be different than the other cores (e.g., asymmetric cores). In one embodiment, a set of asymmetric cores includes a first type of core (e.g., a lower power core) and a second, higher performance type of core (e.g., a higher power core).

In certain embodiments, a computer system includes multiple cores that all execute a same instruction set architecture (ISA). In certain embodiments, a computer system includes multiple cores, each having an instruction set architecture (ISA) according to which it executes instructions issued or provided to it and/or the system by software. In this specification, the use of the term “instruction” may generally refer to this type of instruction (which may also be called a macro-instruction or an ISA-level instruction), as opposed to: (1) a micro-instruction or micro-operation that may be provided to execution and/or scheduling hardware as a result of the decoding (e.g., by a hardware instruction-decoder) of a macro-instruction, and/or (2) a command, procedure, routine, subroutine, or other software construct, the execution and/or performance of which involves the execution of multiple ISA-level instructions.

In some such systems, the system may be heterogeneous because it includes cores that have different ISAs. A system may include a first core with hardware, hardwiring, microcode, control logic, and/or other micro-architecture designed to execute particular instructions according to a particular ISA (or extensions to or other subset of an ISA), and the system may also include a second core without such micro-architecture. In other words, the first core may be capable of executing those particular instructions without any translation, emulation, or other conversion of the instructions (except the decoding of macro-instructions into micro-instructions and/or micro-operations), whereas the second core is not. In that case, that particular ISA (or extensions to or subset of an ISA) may be referred to as supported (or natively supported) by the first core and unsupported by the second core, and/or the system may be referred to as having a heterogeneous ISA.

In other such systems, the system may be heterogeneous because it includes cores having the same ISA but differing in terms of performance, power consumption, and/or some other processing metric or capability. The differences may be provided by the size, speed, and/or microarchitecture of the core and/or its features. In a heterogeneous system, one or more cores may be referred to as “big” because they are capable of providing, they may be used to provide, and/or their use may provide and/or result in a greater level of performance, power consumption, and/or some other metric than one or more other “small” or “little” cores in the system.

A processor may contain other shared structures dealing with state including, for example, prediction structures, caching structures, a physical register file (renamed state), and buffered state (a store buffer). Prediction structures, such as branch predictors or prefetchers, may store state about past execution behavior that is used to predict future behavior. A processor may use these predictions to guide speculation execution, achieving performance that would not be possible otherwise. Caching structures, such as caches or TLBs, may keep local copies of shared state so as to make accesses by the processor very fast.

Shared structures are a security risk. Information can be leaked across contexts by directly or indirectly observing the information stored. Further, behavior in a victim context can be influenced by training from within an attacking context. The disclosure herein alleviates some of these problems in certain embodiments by utilizing memory compartmentalization, for example, clearing/flushing/re-keying shared structures setup in one compartment so that compartment (e.g., code therein) cannot influence the execution of another compartment.

FIG. 2illustrates example formats for linear address checking registers124according to embodiments of the disclosure. Depicted linear address checking registers124(e.g., each being 64 bits wide or wider) includes a domain configuration register202, a domain prefix register204, and a slice prefix register206.

An example format of domain configuration register202includes one or more of: reserved field202A, linear address prefix length field202B, enable field202C. An example format of domain prefix register204includes one or more of: a first reserved field204A, address prefix field204B, a second reserved field204C, and an “in compartment” field204D. An example format of slice prefix register206includes one or more of: reserved field206A, first permission field206B (e.g., to store a bit that indicate a write disable (WD), that when set, denies a memory write to that slice), a second permission field206C (e.g., to store a bit that indicate an access disable (AD), that when set, denies a memory access to that slice), and an address prefix field206D. A slice prefix register may include an execute disable (XD) bit, that when set, denies execution of code within that slice. Further discussion of an example domain, slice, and compartment is below in reference toFIG. 16.

In certain embodiments, domain configuration register202(e.g., IA32_DOMAIN_CONFIG_MSR) is a (e.g., model specific) register that determines (e.g., for each core, or for each logical processor of a plurality of logical processors of a core) whether the feature of compartmentalization is enabled or not in field202C and specifies the length of bits in field202B for address domain selection located in domain prefix register204(e.g., IA32_DOMAIN_PREFIX MSR). In certain embodiments, domain prefix register204(e.g., IA32_DOMAIN_PREFIX) is a (e.g., model specific) register that contains the bits for address domain checking in field204B. In one such embodiment, there is only one address domain (e.g., a single address space) so this register contains the bits for checking whether it is compartment memory or not, for example, with the address prefix field204B storing the content while its length is specified by field202B in domain configuration register202. In one embodiment, domain configuration register202and domain prefix register204are programmable by code with supervisor privilege (e.g., ring 0 accessible) and slice prefix register206is programmable by code with user privilege (e.g., ring 3 accessible). In certain embodiments, slice prefix register206stores the bits for slice selection, e.g., one of a plurality (e.g., eight) slices as indicated by address prefix field206D, and permission one field206B being a first permission (e.g., WD) for that slice and permission two field206B being a second permission (e.g., AD) for that slice, e.g., and a third permission (e.g., XD) for that slice. Thus, linear address checking registers124may be used to enforce memory compartmentalization. The data within linear address checking registers may stored in a compartment descriptor160and/or compartment thread descriptor162.

Certain embodiments of memory compartmentalization utilize (e.g., swap into a core and out of a core) compartment descriptors160and/or compartment thread descriptors162.

FIG. 3illustrates an example format for a compartment descriptor160according to embodiments of the disclosure. InFIG. 3, each entry in compartment descriptor160includes a field name302, e.g., a name of a particular linear range (e.g., slice) of memory, etc. per description306(which description306may not be an entry in each line in compartment descriptor160), and a field304having an indicated width (e.g., to store data indicating the base address for that particular linear range). InFIG. 3, compartment descriptor160may thus store multiple base addresses for each respective linear range (e.g., slice), an instruction pointer (e.g., RIP) for an instruction to execute once exiting a compartment (e.g., which may be one or more slices as discussed herein), and attributes, for example, a bit indicating if a compartment is a management compartment, if a proper subset of instructions of the ISA are allowed to be executed in a compartment, and/or is speculative execution is allowed in a compartment. In one embodiment, each compartment includes its own compartment descriptor160.

FIG. 4illustrates an example format for a compartment thread descriptor162according to embodiments of the disclosure. In certain embodiments, each thread in a compartment can have its own compartment thread descriptor162. InFIG. 4, each entry in compartment thread descriptor162includes a field name402, per description406(which description406may not be an entry in each line in compartment thread descriptor162), and a field404having an indicated width (e.g., to store data according to the description406). In one embodiment, an entry in compartment thread descriptor162includes one or any combination of: a field for a return stack pointer (RSP) after exiting the compartment (e.g., to be stored into stack register170inFIG. 1), a field for return shadow stack pointer (RSSP) after exiting the compartment (e.g., to be stored in shadow stack register172inFIG. 1), a field that indicates a reason for exiting the compartment (e.g., execution of an SBXEXIT instruction or otherwise), a field that indicates further information (e.g., qualities) when an instruction that is marked as being an instruction not allowed to be executed in the compartment (e.g., thread) is requested to be executed in the compartment (e.g., the information can be that instructions length and opcode), a field that indicates the instruction pointer (e.g., RIP) for tenant code (e.g., code running inside of a compartment), a field that indicates the RSP for the tenant code, or a field that indicates the RSSP for the tenant code.

FIG. 5illustrates a compartment execution model500according to embodiments of the disclosure. InFIG. 5, there is a first process address space502A (e.g., and may include a second or more process address space502M). Native (e.g., legacy) code504is within the process address space502A within memory. As depicted, a management compartment506has been initialized (e.g., by marking the management attribute for that compartment's compartment descriptor160as discussed in reference toFIG. 3), along with a first compartment508, and one or more other compartments (e.g., second compartment510and third or more compartment512). For example, with each compartment having a respective compartment descriptor514. In certain embodiments, core (e.g., logical processor)516is executing code in management compartment506and can execute a compartment enter instruction (e.g., SBXENTER mnemonic) to enter a compartment. For example, to enter first compartment508and that compartment508can execute an exit instruction (e.g., SBXEXIT mnemonic) to exit the compartment into management compartment506. In some embodiments, switching a compartment descriptor switches other state such as encryption keys that may be used for all memory load/store operations inside the compartment. This embodiment may be used to further isolate architectural state (e.g., memory, registers, etc.), and micro-architectural state (e.g., branch predictors, load/store queues, fill buffers, etc.). The encryption keys for the compartment may be derived from a combination of key material for the context in which the compartment is executing (such as a trusted execution environment, e.g. SGX enclaves, TDX trust domains), and tweak keys that are specific to the compartment descriptor. The encryption keys may be used for confidentiality, integrity, and replay-protection of data in the compartment.

As discussed below in reference toFIG. 6, core516(e.g., at the request of management compartment506) may execute a load pointer instruction to load a pointer to (e.g., secure) memory storing the compartment descriptor for a (e.g., non-management) compartment into core516. Then management compartment506may execute a compartment enter instruction (e.g., SBXENTER mnemonic) to load that compartment's descriptor into core516and enter execution within that compartment. As discussed below in reference toFIG. 6, core516(e.g., at the request of management compartment506) may execute a store pointer instruction to store a pointer to (e.g., secure) memory storing the compartment descriptor for a (e.g., non-management) compartment from the core516.

In certain embodiments, management compartment506can access the slices of first compartment508and second compartment510, but first compartment508cannot access the slices of second compartment510and second compartment510cannot access the slices of first compartment508. In certain embodiments, management compartment506can access the slices of first compartment508, second compartment510, and third (or more) compartment512, but the first compartment508, second compartment510, and third (or more) compartment512can only access the slices in their own compartment. In certain embodiments, each compartment can access code outside of any compartment (e.g., native code504).

In certain embodiments, the management compartment506forms a hierarchical structure of access permissions, e.g., such that management compartment506is permitted to access the slices of first compartment508, and delegates its management authority specifically such that compartment508can access the slice of second compartment510but second compartment510cannot access the memory slices of first compartment508or management compartment506.

Compartment hardware may be exposed to the software as an X-feature. Referring again toFIG. 1, a core109may include a control register112such that the compartment management by the hardware is enabled by setting a (e.g. [SBX_EN]) bit to enable the features. For example, when this bit is set, the core109(e.g., logical processor) is to save additional internal state (e.g., a compartment descriptor) in the XSAVE area164. This internal state may be internally cached (e.g., maintained) within core. The internal state may include values for sbx_state114, sbx_desc_ptr116, sbx_rbase0 . . . 7118, etc. as discussed herein. In certain embodiments, core109includes a compartment state register114(e.g., SBX_STATE) to store a current state (e.g., operating mode) to be used by core (e.g., by compartment manager110). When (e.g., XCR0[SBX_EN]) enable bit for compartment manager110is set in control register112, the core109(e.g., logical processor) then checks the sbx_state internal register114. Possible states for compartment state register114include 00 for SBX*CLEAR state (e.g., to cause the current compartment to be removed (e.g., so that it is not accessible)), 01 for SBX_OUTSIDE state (e.g., operating outside a compartment), 10 for SBX_INSIDE state (e.g., operating within a compartment and/or within native code504inFIG. 5), and 11 for SBX_SUSPENDED state.

In one embodiment, when (e.g., XCR0[SBX_EN]) enable bit changes value from 1 to 0, sbx_state register114is reset to 00 (e.g., to cause the current compartment to be removed (e.g., so that it is not accessible)). In certain embodiments, executing a clear compartment instruction (e.g., SBXCLEAR mnemonic) resets this register114to 00. In one embodiment, executing an extended state restore instruction (e.g., XRESTOR mnemonic) with (e.g., XCR0[SBX_EN]) enable set to 1 will restore the value of this register114from XSAVE area164.

A core may include as part of its ISA one or more compartmentalization instructions. The instructions may include one or any combination of: a load compartment descriptor pointer instruction (e.g., SBXLDPTR mnemonic), a store compartment descriptor pointer instruction (e.g., SBXSTPTR mnemonic), a clear compartment instruction (e.g., SBXCLEAR mnemonic), a compartment enter instruction (e.g., SBXENTER mnemonic), or a compartment exit instruction (e.g., SBXEXIT mnemonic). An operating system (OS) may use one or more of these instructions to set up one or more compartments.

FIG. 6is a block flow diagram illustrating execution of one or more compartmentalization instructions604by processor600according to embodiments of the disclosure. Instruction(s)604may include a load compartment descriptor pointer instruction (e.g., SBXLDPTR mnemonic) that, when decoded and executed, loads the compartment descriptor pointer into core109(e.g., into compartment descriptor pointer register116from compartment descriptor160in memory102), cache the compartment ranges and permissions into internal registers (e.g., registers118,120,122,124, etc.), set compartment mode (e.g., sbx_mode) in register114to SBX_OUTSIDE, or any combination thereof.

Instruction(s)604may include a store compartment descriptor pointer instruction (e.g., SBXSTPTR mnemonic) that, when decoded and executed, writes out the compartment descriptor pointer to memory (e.g., stores the pointer into an XSAVE area164), for example, without altering any value in the compartment mode register (e.g., sbx_state register114).

Instruction(s)604may include a clear compartment instruction (e.g., SBXCLEAR mnemonic) that, when decoded and executed, clears a compartment descriptor, for example, clearing all internal processor state for that compartment descriptor (e.g., to disallow any future entry into that compartment, such as, but not limited to, disallowing future execution of a compartment enter instruction for that compartment). In one embodiment, a clear compartment instruction takes as input a linear address of the compartment descriptor in the process address space (e.g., the compartment descriptor must be in the management compartment's memory).

Instruction(s)604may include a compartment enter instruction (e.g., SBXENTER mnemonic) that, when decoded and executed, installs the data for a compartment descriptor (e.g., from memory102into core109inFIG. 1) e.g., and enters execution within the compartment. In certain embodiments, the compartment enter instruction takes as an operand the compartment descriptor pointer currently stored in compartment descriptor pointer register116(e.g., SBX_DESC_PTR) and loads the corresponding data from memory102for that compartment descriptor into core109, e.g., and enters execution of code within the compartment. In one embodiment, pseudocode for execution of a compartment enter instruction includes:

if (lp.CPL !=3) //where lp is an identifier of a logical processor (lp)#GP // general protection faultif (lp.sbx_mode==SBX_INSIDE)// follow “Illegal Instruction” flow for a compartmentlp.sbx_lrange[0 . . . n−1]←sbx_desc_ptr→sbx_lrange[0 . . . n−1]lp.RIP←sbx_desc_ptr→SBX_RIPlp.sbx_desc_ptr←sbx_desc_ptrlp.sbx_mode←SBX_INSIDE //compartment is now active
In certain embodiments, software is responsible for managing (e.g., all) other registers. In some embodiments, operands are passed to SBXENTER to, optionally, flush, clear, and/or re-key common shared hardware state (such as Branch predictors, micro-architectural buffers, etc.) to prevent one compartment from causing speculative execution in another compartment, for example, and enforce a load fence to resolve any pending loads before the target compartment starts executing.

Instruction(s)604may include a compartment exit instruction (e.g., SBXEXIT mnemonic) that, when decoded and executed, uninstalls the data for a compartment descriptor (e.g., from core109into memory102inFIG. 1) e.g., and exits execution within the compartment. In one embodiment, pseudocode for execution of a compartment exit instruction includes:

lp.sbx_mode←SBX_OUTSIDE //compartment is now inactive

In one embodiment, e.g., in response to a request to perform an operation, a compartmentalization instruction (e.g., macro-instruction)604is fetched from storage602and sent to decoder606(e.g., decoder circuit146inFIG. 1). In the depicted embodiment, the decoder606(e.g., decoder circuit) decodes the instruction into a decoded instruction (e.g., one or more micro-instructions or micro-operations). The decoded instruction is then sent for execution, e.g., via scheduler circuit608to schedule the decoded instruction for execution.

In certain embodiments, (e.g., where the processor/core supports out-of-order (OoO) execution), the processor includes a register rename/allocator circuit coupled to register file/memory circuit610(e.g., unit) to allocate resources and perform register renaming on registers (e.g., registers associated with the instruction). In certain embodiments, (e.g., for out-of-order execution), the processor includes one or more scheduler circuits608coupled to the decoder. The scheduler circuit(s) may schedule one or more operations associated with decoded instructions, including one or more operations decoded from a synchronization instruction, for execution on the execution circuit612.

In certain embodiments, a write back circuit614is included to write back results of an instruction to a destination (e.g., write them to a register(s) and/or memory), for example, so those results are visible within a processor (e.g., visible outside of the execution circuit that produced those results).

One or more of these components (e.g., decoder606, register rename/register allocator/scheduler608, execution circuit612, register file/memory610, or write back circuit614) may be in a single core of a hardware processor (e.g., and multiple cores each with an instance of these components.

FIG. 7illustrates a method700of instantiating one or more compartments according to embodiments of the disclosure. Method flow700includes starting at702, an OS loader loading native (e.g., legacy) code into a process address space at704, the OS loader selecting memory region(s) (e.g., one or more slices) within the process address space for each compartment it instantiates at706, OS loader programming memory ranges into at least one compartment descriptor (e.g., and programing the initial state for threads into one or more compartment thread descriptors) at708, checking if the OS loader is delegating compartment management to a management compartment at710, and, if yes, the OS loader specifies one or more of the compartments as the management compartment (e.g., by configuring SBX_ATTR for each of the one or more specified compartments) at712and then the OS loader resumes code execution in the native code (e.g., via executing a return instruction (e.g., IRET/SYSRET)) at714, and if no at710, checking if the OS is loading additional (e.g., sub-process) compartment(s) at718, and if yes at718, then the OS loader programs at least one or more compartment descriptors in the memory range of the management compartment at720, and it no at718, then proceeding to714. In certain embodiments after714, the instantiating is ended at716.

FIG. 8illustrates a method800of utilizing a compartment to execute code within the compartment according to embodiments of the disclosure. Method flow800includes starting at802, management compartment invokes a compartment load pointer instruction (e.g., SBXLDPTR) to load a selected compartment descriptor at804, core (e.g., logical processor) caches the data from the compartment descriptor (e.g., associated memory permissions and other state) into the core (e.g., core's registers) at806, core (e.g., logical processor) sets SBX_STATE to “SBX_OUTSIDE” at808, management compartment adjusts the entry point, stack, and base pointers for the loaded compartment descriptor (e.g., via direct memory stores or via instructions to access the compartment descriptor) at810, management compartment sets any initialization parameters passed through memory for the compartment (e.g., or marshals parameters for compartment exported function) at812, management compartment executes a compartment enter instruction (e.g., SBXENTER) at814, core (e.g., logical processor) sets the SBX_STATE to “SBX_INSIDE” (e.g., for that logical processor) and transfers execution to the entry point for the compartment (e.g., and optionally switches stack and other register values) at816, the invoked compartment dispatch code unmarshals the parameters and invokes the compartment sub-routine with native (e.g., legacy) call/jump_indirect at818, and compartment code executes with access to compartment data per the memory permissions of the compartment at820. In certain embodiments after820, the flow800is ended at822.

FIG. 9illustrates a method900of a processor managing the utilizing of a compartment according to embodiments of the disclosure. Method flow900includes determining, when a compartment control register of a hardware processor core is set to an enable value, that a first subset of code requested for execution on the hardware processor core in user privilege is within a first compartment of memory at902, loading a first compartment descriptor for the first compartment into one or more registers of the hardware processor core from the memory at904, checking if the first compartment is marked in the first compartment descriptor, within the one or more registers of the hardware processor core, as a management compartment at906; and, when the first compartment is marked in the first compartment descriptor as the management compartment, allowing the first subset of the code within the first compartment to load a second compartment descriptor for a second compartment of the memory into the one or more registers of the hardware processor core from the memory, switching execution from the first subset of code within the first compartment to a second subset of code in user privilege within the second compartment, allowing speculative memory accesses for the second subset of code only within the second compartment, and preventing a memory access outside of the second compartment for the second subset of code as indicated by the second compartment descriptor stored within the one or more registers of the hardware processor core, wherein the second compartment, as indicated by the second compartment descriptor, comprises a plurality of non-continuous (e.g., discontinuous) slices in a single address space in the memory908.

FIG. 10illustrates a block diagram of circuitry1000including a linear address prefix checking circuit1010according to embodiments of the disclosure. Circuity100includes an input1002to receive a data access request (e.g., from an execution circuit), for example, a linear address for the data to be accessed (e.g., loaded and/or stored). In one embodiment, the linear address is checked within translation lookaside buffer (TLB)1004for its corresponding physical address in memory (e.g., cache)1006. If present (e.g., a “hit”) in TLB1004then the data access occurs at that physical address is memory1006in certain embodiments. If not present in TLB1004(e.g., a “miss”) then the linear address is sent to page miss handler1008to determine (e.g., “fill”) the corresponding physical address (e.g., via a page walk) in certain embodiments. In certain embodiments, for a miss, the linear address is checked to see if it is within a compartment (e.g., if the access to that address is allowed per the compartment hardware disclosed herein). In one embodiment, this places the linear address checking behind the TLB match instead of putting it in the critical path at runtime. One benefit is that the address checking (e.g., by linear address prefix checking circuit1010) does not have to be triggered in these embodiments if a hit in the TLB, e.g., and for any TLB miss the linear address prefix checking circuit1010is triggered. In one embodiment, if linear address checking is passed, and PMH has occurred (e.g., returning the physical address) (e.g., with these two conditions determined by AND logic gate1012taking a respective status input from linear address prefix checking circuit1010and page miss handler1008), then the TLB will have a tag (e.g., for the fill) corresponding to a compartment of the current thread. In certain embodiments, having the linear address prefix checking circuit1010logically behind a TLB match increases the TLB pressure if a thread switching across multiple compartments are all accessing similar/same native memory regions. To alleviate that, certain embodiments herein only tag the TLB within a compartment address but not native memory. For security reason, certain embodiments herein provide an instruction that flushes the TLB when switching compartments.

In certain embodiments, an error may occur within a compartment (e.g., when executing code at an address within the compartment. Table 1 below depicts nine possible error codes and their descriptions.

TABLE 1ERROR HANDLING IN A COMPARTMENTNumeric Id.MnemonicDescription0SBX_REASON_AVAILThis reason is available for software use,and hardware will not (e.g., ever) use thisreason1SBX_REASON_SBX_EXITSoftware inside the compartmentexecuted SBX_ EXIT instruction2SBX_REASON_ILLEGAL_ACCESSSoftware inside the compartmentperformed an illegal accessLinear address of the illegal access isprovided in SBX_EXIT_QUAL field ofthe compartment descriptor3SBX_REASON_SYSCALLSoftware inside the compartmentexecuted this instruction4SBX_REASON_SYSENTERSoftware inside the compartmentexecuted this instruction5SBX_REASON_VMCALLSoftware inside the compartmentexecuted this instruction6SBX_REASON_INT_NSoftware inside the compartmentexecuted this instruction7SBX_REASON_SEGREG_WRITESBX_EXIT_QUAL field containsnumeric identifier of the segreg0→DS 1→ES 2→FS 3→GS 4→SS8SBX_REASON_CPControl flow violation due to indirectcall/jmp

In one embodiment, corrective action for 2-9 (e.g., but not for 0 or 1) of the above error reasons in Table 1 is handled by an OS (or VMM).

While in a compartment, memory accesses outside the compartment range(s) are not permitted by the core (e.g., CPU) in certain embodiments. An example memory access enforcement model when a compartment is executing is described below.

As one example, three options are possible for memory access violation reporting with the disclosed instructions and hardware herein:

Pseudocode of Approach 1:

Set lp.sbx_mode to SBX_SUSPENDED

Pseudocode of Approach 2:

Set lp.sbx_mode to SBX_SUSPENDED

Deliver a new exception #CV (e.g., Compartment Violation)

Pseudocode of Approach 3:

In certain embodiments, the pseudocode for operation for a compartment when experiencing an Interrupt/Exception/Virtual Machine Exit (VMEXIT), or System Management Interrupt (SMI) Operation is:

if (lp.sbx_mode==SBX_INSIDE)

Continue with the interrupt/exception/vmexit/SMI flow

In certain embodiments, the pseudocode for operation for a compartment when experiencing an Interrupt Return (IRET), Resuming a Virtual Machine (VMRESUME), a Launch of a Virtual Machine (VMLAUNCH), or a Resume from System Management Mode (RSM) Operation is:

Continue with IRET/VMRESUME/VMLAUNCH/RSM flow

Note: Exception handling utilizes special OS enabling in certain embodiments. For example, the OS may execute an interrupt return (IRET) instruction to deliver exception to the exception handler, and this will enable the compartment without going into the compartment. In another embodiment, an OS ensures that the exception handler is outside of all the compartment ranges, and an interrupt return (IRET) instruction to this location causes EXIT_REASON_ILLEGAL_ACCESS exit from compartment (e.g., which can be used by software to unwind with additional information from the core).

The following discussed examples of software's use of one or more compartmentalization instructions.

Software may call into a compartment: using the management compartment and/or protected runtime to adjust stack and base pointers, using the management compartment and/or protected runtime to marshals the parameters, using the management compartment and/or protected runtime to sets compartment entry (e.g., SBX_ENTRY) to point to the entry point of an unprotected runtime, using the management compartment and/or protected runtime to execute a compartment enter instruction (e.g., SBXENTER), using a compartment unprotected runtime to unmarshal the parameters, using a compartment unprotected runtime to call the appropriate plugin function, using software to handle parameters between a management compartment (and/or protected runtime) and a compartment (and/or unprotected runtime).

Software may call a compartment using a stack. In one embodiment, all parameters are passed on stack. Additionally or alternatively, register-based parameter passing can be used. For example, a compartment code may implement two example functions: foo and bar, each taking two parameters. In one embodiment, software uses a register (e.g., RAX register) to indicate which function inside the compartment is desired, e.g., where RAX=0 for “foo” and RAX=1 for “bar”. In certain embodiments, management runtime performs the following actions: push all parameters on the stack and/or push pointer to appropriate compartment descriptor on the stack.

Software may return from use of a compartment. For example, by the compartment code executing a return instruction that transfers control to the unprotected runtime (e.g., still inside compartment), to the instruction after “call” that was executed by the unprotected runtime. In one embodiment, unprotected runtime sets up appropriate “reason code” inside the compartment memory. In one embodiment, unprotected runtime executes a compartment exit instruction (e.g., “SBXEXIT”). In one embodiment, control transfers to the (e.g., SBX_EXIT) routine inside the protected runtime, for example, where this routine adjusts the stack and base pointers and returns. In some embodiments, operands are passed to SBXEXIT to, optionally, flush, clear, and/or re-key common shared hardware state (such as Branch predictors, micro-architectural buffers, etc.) to prevent one compartment from causing speculative execution in another compartment, for example, and enforce a load fence to resolve any pending loads before the target compartment starts executing.

Embodiments herein provide compartmentalization of memory that uses low memory overhead per compartment and/or a low entry/exit cost. Embodiments herein provide that compartments can share protected memory, compartments do not create new CPL rings, multiple threads can execute, a compartment can call into an OS, a compartment can take interrupts, and the compartments can share a (e.g., single) application address space. Certain embodiments herein provide linear compartments with multiple prefix registers for software compartmentalization.

Certain embodiments herein allow for software compartmentalization. Compartmentalization may be utilized to maintain memory safety, e.g., to avoid memory corruption to prevent code (e.g., a software application) from being hijacked but at the same time retaining highest performance. Compartmentalization may be utilized for side channel prevention, e.g., preventing speculative memory accesses from other compartments for software running in one compartment. Embodiments herein provide compartmentalization that is scalable to a large number of (e.g., 1000 or more) compartments. Embodiments herein provide compartmentalization that has little to no observable performance penalty in normal execution (e.g., performance at native speed) and/or little to no performance overhead on transition between compartments or compartment and non-compartments. Embodiments herein provide hardware compartmentalization that does not require changes in software, e.g., so that developers can make their software architectures more consistent across all platforms. Embodiments herein provide compartmentalization that is not as simple as defining a region of code and data, for example, where software uses different resources in different memory regions and/or indicating setting up memory permission of different locations at different time, the hardware is to allow software to set up different permissions to different memory ranges. Embodiments herein provide compartmentalization that supports numerous compartments (e.g., more than 1000, 2000, 3000, 4000 (e.g., 4096), 5000, etc. compartments). Embodiments herein provide compartmentalization that has little to no overhead on normal program execution (e.g., inside compartment or outside) and/or has little to no time added for switching memory permission view. Embodiments herein provide compartmentalization that is not intrusive on existing software architecture. Embodiments herein provide compartmentalization does not force the usage of compartments in the whole address space but only using a small portion of it with configurable size. Embodiments herein provide compartmentalization that provides a flexible view on various situations when a program is running in a compartment or outside of a compartment. Embodiments herein provide compartmentalization that do not conflict with memory tagging, for example, in embodiments that only uses valid linear address bits instead of the top bits of a linear address, they are not conflicting with any techniques that leverage the top linear address bits such as memory tagging. Embodiments herein provide compartmentalization that is greater than about sixteen, e.g., memory domains. Embodiments herein provide compartmentalization that is not merely process isolation, e.g., where process-based isolation does not scale because of its high usage of kernel resources. Embodiments herein provide compartmentalization that does not require any virtualization to be turned on or that all guest physical memory allocated. Embodiments herein provide compartmentalization that is power efficient.

Certain embodiments herein provide linear compartments (e.g., with multiple prefixes) via linear memory access control hardware. Embodiments herein allow user applications (e.g., code) to sandbox their components into different memory ranges, for example, such that code and data in each range is isolated (e.g., no access allowed) or selectively connected (e.g., limited access allowed) from the remaining part of the application code running outside.

Certain embodiments herein use linear compartments as a hardware mechanism for memory isolation within one address space, e.g., where running multiple instances using only one process saves resources from OS and allows applications to have better launch time and runtime performance.

One difficulty of a proper hardware design is how to handle software complexities in a simple manner, given that 1) certain software allocates memory from various places and 2) the memory to be compartmentalized may be scattered around the whole address space. The below discussed a software case and a confused deputy attack, linear compartments design, and then OS and software enabling.

Certain embodiments herein provide compartmentalization hardware (e.g., and/or instructions) that has a small overhead, low extra power cos, and minimum software changes for enabling, e.g., as a software vendor may be reluctant to have their software architecture fragmented to fit hardware features that are only available in some types of processors and/or ISAs. Certain embodiments herein provide compartmentalization hardware (e.g., and/or instructions) that provides speculation safety, e.g., code running in compartment A should not be able to use side channel code to read content of any other compartments).

The below example is a use case for a scripting language engine, e.g., which can be used to build a content delivery network (CDN). One key limitation of running multiple instances within one address space is the lack of security. Certain embodiments herein reuse a proper subset of linear address bits for compartmentalization, for example, with a hardware mechanism (e.g., one or more instructions of a processor ISA) to create/check/destroy compartments.

A scripting language (e.g., in contrast to a general purpose language such as, but not limited to C or C++) may use a scripting language engine to run multiple instances within the same address space. The scripting language runtime may support intermediate formats that are interpreted code or ahead-of-time compiled code compilation (e.g, such as but not limited to a WebAssembly (WASM) standard).

FIG. 11illustrates three types of memory1102,1104,1106used by a scripting language engine1100according to embodiments of the disclosure. Memory1102is a general purpose language memory, e.g., to store other native libraries1108or data1110. Memory1104is a general purpose language memory for scripting language code, e.g., to store scripting language engine1100, its global data1112, addons1116, an d data1114(e.g., the memory that is used to support the running of a scripting language engine1100instance). Memory1106is a scripting language memory, e.g., to store a plurality of scripting language code (e.g., a plurality of isolates1120A-1120C). Zoomed-in view of isolate1120C illustrates a code space, an object space, and metadata.

A scripting language engine1000may utilize a memory hierarchy as follows: (i) an isolate (e.g., isolate1120C) represents one scripting language virtual machine (VM) instance (e.g., in certain embodiments, each isolate includes one scripting language heap), (ii) a space that represents one type of scripting language object within an isolate, and (iii) a page that is a chunk of memory (e.g., 512K or 1 MB) that contains a sequence of scripting language objects. In certain embodiments, the terms isolate, space and page are logical and they are defined by the scripting language engine1100itself. Each isolate may thus represents one scripting language instance, e.g., one entity to be compartmentalized. However, an isolate may not be continuous in memory, instead it may be classified into several spaces and each spaces is further fragmented into a collection of memory chunks. In one embodiment, the scripting language engine1100is to guaranty there is no linear memory sharing across any two different isolates. At circle (1) the scripting language engine1100creates just-in-time code in isolate1120C, at circle (2) the just-in-time code is entered, at circle (3), the general purpose language code is entered, and at circle (4), the garbage collection (GC) begins (e.g., to reclaim memory) and just-in-time data is updated.

FIG. 12illustrates scripting language memory1202and general purpose language memory1204according to embodiments of the disclosure. In certain embodiments, scripting language code running in an isolate1206is to access memory (e.g., general purpose language memory1204) outside of where it is stored (e.g., outside of scripting language memory1202). InFIG. 12, general purpose language memory1204stores the scripting language engine1200, global data1212for isolates (e.g., to be read by isolate1206), scripting language stack frames1208(e.g., to be read or written to by isolate1206), user stack1210(e.g., to be read by isolate1206), and heap1214(e.g., to be read by isolate1206) (e.g., where the allocation and deallocation of the heap is by a programmer).

In one embodiment, each isolate could only occupy one running thread and each running thread is allowed to switch to another isolate. However, the problem is that when switching isolate, in certain embodiments the thread does not switch stack, and thus not all memory regions are attached permanently to an isolate. Certain embodiments herein overcome these issues.FIGS. 13A-13Bdemonstrates the situation when a thread switches its isolate.

FIG. 13Aillustrates memory1300A before a switch of a first isolate1302B to a second isolate, andFIG. 13Billustrates the memory1300B after the switch of the first isolate1302B to the second isolate1304B according to embodiments of the disclosure. First isolate1302B is to access four slices of memory, e.g., one each from global data controlled by the OS1302A, from first isolate controlled by scripting language engine1302B, from heap memory controlled by general purpose language runtime1302C, and global memory controlled by the OS1302D (e.g., user stack). After switching to second isolate1304B, second isolate1304B is to access four slices of memory, e.g., one each from global data controlled by the OS1304A, from second isolate controlled by scripting language engine1304B, from heap memory controlled by general purpose language runtime1304C, and global memory controlled by the OS1304D (e.g., user stack). In one embodiment, each scripting language thread owns its own scripting language memory and its own stack, but shares the same (e.g., C++) heap and global data (e.g., user stack), for example, such that heap is in fact virtual now because there is so far no compartmentalization implementation even in software.

From the previous section, the example high level memory layout of each scripting language thread has at least 4 pieces (e.g., slices) of memory that it needs to access. In addition to that, in embodiments the isolate is not self-contained, e.g., anything related to the system requires an application programming interface (API) call(s) outside of the isolate. In certain embodiments, each thread has two states: (1) inside isolate and (2) outside of isolate. However, in certain embodiments, a scripting language code can call into the whole address space of general purpose language code as shown in the confused deputy attack inFIGS. 14 and 15.

FIG. 14illustrates an untrusted scripting language thread1402constrained within an isolate1404according to embodiments of the disclosure. In certain embodiments, the untrusted scripting language thread1402is not allowed to call into another isolate or native code.

FIG. 15illustrates an untrusted scripting language thread1402calling out into general purpose language code1502according to embodiments of the disclosure. In this embodiment, the general purpose language code1502is allowed to call into another isolate or native code, and thus an exit from the isolate has given a (e.g., untrusted) running thread1402full access control capability (e.g., and may allow the thread1402to corrupt/leak code/data in other isolates).

Certain embodiments herein overcome these issues by using hardware compartmentalization of memory.

FIG. 16illustrates an address domain1602in memory1600, a memory slice1604in the address domain1602, and a compartment1606that includes multiple memory slices1606A-C according to embodiments of the disclosure. In one embodiment, memory slice1606A of single compartment1606stores an isolate, memory slice1606B of single compartment1606stores the heap for that isolate, and memory slice1606C of single compartment1606stores the user stack for that isolate.

In one embodiment, an address domain is a contiguous linear address space of memory that needs to be isolated (e.g., to prevent a confused deputy attack), a memory slice is a contiguous address range that can be isolated from other ranges within the same address domain, and/or a compartment is a logical entity that consists of a collection of memory slices. In certain embodiments, a compartment can span across several address domains, a compartment can have multiple memory slices, and/or a compartment should not change its linear memory boundaries by itself.

In certain embodiments, a hardware compartment is aware of address domains as well as memory slices. Thus, certain embodiments herein utilize two-level linear address checking to satisfy this two-level awareness, e.g., as shown in the followingFIG. 17.

FIG. 17illustrates two level hardware address checking for an access request1702to memory1700according to embodiments of the disclosure. Depicted access request is a linear address1702including high address canonical bits1702A, a field1702B to perform a prefix match on, a field1702C to perform a slice match on, and a field1702D for the rest of the linear address1702. Depicted memory includes isolates stored in slices within scripting language program code1704domain of memory1700, a heap1706domain, and a user stack1708domain. Thus, a memory access request (e.g., from an execution circuit at the request of code) may check linear address1702to ensure that the code requesting the access matches its prefix1702B to the prefix(es) allowed to be accessed by that code and matches its slice index1702C to the slice index(es) allowed to be accessed by that code.

Thus, certain embodiments herein utilize two level address checking, e.g., a check of a “prefix” match to an address domain and within each address domain, a check of a “slice index” match to a slice number. In one embodiment with N (where N is any positive integer greater than one) address domains, a compartment could have N memory slices. To achieve compartment address checking, one embodiment would use N number of prefix registers for address domain bit matching and memory slice selection in equal size. In other embodiment, only one prefix register is used for address domain matching and N number of slice registers are used for slice matching. The followingFIG. 18shows an example of this.

FIG. 18illustrates two level hardware address checking within one address domain1804for an access request1802to memory1800according to embodiments of the disclosure. Compartment1806includes a slice1806A for an isolate, a slice1806B for the isolate's heap, and a slice1806C for isolate's stack. Depicted access request is a linear address1802including high address canonical bits1802A, a field1802B to perform a prefix match on, a field1802C to perform a slice match on, and a field1802D for the rest of the linear address1802. Thus, a memory access request (e.g., from an execution circuit at the request of code) may check linear address1802to ensure that the code requesting the access matches its prefix1802B to the domain allowed to be accessed by that code and matches its slice index1702C to the slice(s) index(es) allowed to be accessed by that code. An example of linear address checking registers is discussed in reference toFIG. 2. In certain embodiments, domain configuration register202and domain prefix register204are managed by an OS and initially setup by applications (e.g., assuming the OS manages the contents within these two registers). In certain embodiments, the slice prefix register206is set by user level code, e.g., not only set by the OS.

FIG. 19illustrates linear address checking management data structures according to embodiments of the disclosure. Depicted data structures include a compartment table1902, for example, with compartment table entry1902A including a plurality of entries (e.g., where each entry includes permissions bits (e.g., a bit for WD permission, a bit for AD permission, and/or a bit for XD permission for that slice) and slice index bits indicating the particular slice of that particular compartment, e.g., for a plurality (e.g., 8) slices). In certain embodiments, the compartment table1902is used purely for management purpose, but there is a permission table1904in exactly the same format, for example, with a key difference being that the permission table is used by each thread, and thus they are thread local and it is used by the core to enforce a permission check at runtime. In one embodiment, entry1904A in table1904corresponds to the same location (i.e., table entry1902A) in table1902. In certain embodiments, separating the permission table1904from the compartment table1902provides the benefits of least privilege, e.g., even if there are four compartments allocated, thread one could only use compartment four. Depicted data structures include an allocation table1906showing the allocation status of each memory slice (e.g., with the filled in boxes being allocated memory slices), for example, with allocation table1906used by a linear memory slice allocator to satisfy address range allocation and potential sharing purposes.

The above discussed examples of how each compartment boundary and permission is managed (e.g., using the data structures inFIG. 19).

In certain embodiments, these data structure are managed and updated at runtime, e.g., the memory of those data structures is to be writable for some period of time. In certain embodiments, to provide memory security, the data structures are managed by a management compartment. In certain embodiments, a given memory slice (e.g., slice 0) of the management compartment includes the data structures inFIG. 19, e.g., and any code and data to support running a local thread. In one embodiment, the thread running inside a management compartment is responsible for handling a request for compartment creation/destruction, memory slice allocation/deallocation, etc. To ensure that its own memory slice is not accessible by other threads, this thread in the management compartment ensures that any compartment/slice allocation will not use the slices used by the management compartment in certain embodiments, for example, to ensure the management compartment's memory is not accessible by any threads (e.g., other than the management thread itself in ring-3).

The following instructions may be utilized to manage the data structures discussed herein, for example, to keep an attacker from switching to other compartments and corrupting their memory (e.g., such that an attacker cannot abuse the privilege provided by the ISA to corrupt native memory).

A compartment setup instruction may take an operand of either a compartment table1902or a permission table1904and setup the values (e.g., populate the entries) in that table. In one embodiment, the core will record the table address as the base for compartment selection. In certain embodiments, this instruction can only be executed in ring-0 to prevent itself from being abused.

A compartment enter instruction may set the InCompartment bit204D of the domain prefix register204inFIG. 2to turn off the access permission towards external (e.g., from the compartment) memory, e.g., and the instruction may take no operands in certain embodiments.

A compartment exit instruction may set the InCompartment bit204D of the domain prefix register204inFIG. 2to turn on the access permission towards external (e.g., from the compartment) memory, e.g., and the instruction may take no operands in certain embodiments. In certain embodiments, the core is expected to execute an instruction outside of any compartment memory. In certain embodiments, the compartment exit instruction is privileged instruction in ring-3 because it turns on the access to native memory and its usage should be controlled (e.g., by preventing execution of instructions in that compartment's memory after execution of the compartment exit instruction. This may be achieved by including a special prefix for opcodes of indirect call/jump or a return.

A compartment switch instruction may take one (e.g., integer) operand, used by the core as an index to the permission table previously setup. In certain embodiments, the index is bound-checked. To prevent untrusted code from maliciously switching compartments, certain embodiments herein disallow any execution of this instruction within compartment memory, e.g., the compartment switch instruction cannot be executed in scripting language (e.g., JITed) code. In one embodiment, a compartment switch instruction reads memory of the permission table, which may be located in memory slice 0, as mentioned above. In an embodiment where threads other than the management thread in the management compartment cannot access memory in that slice, compartment switch instruction temporarily allows access to slice 0, reads the data, and disables the access to slice 0 (e.g., with these three operations done sequentially in an atomic transaction).

Exemplary architectures, systems, etc. that the above may be used in are detailed below.

In yet another embodiment, an apparatus comprises a data storage device that stores code that when executed by a hardware processor causes the hardware processor to perform any method disclosed herein. An apparatus may be as described in the detailed description. A method may be as described in the detailed description.

Exemplary Instruction Formats

Generic Vector Friendly Instruction Format

FIGS. 20A-20Bare block diagrams illustrating a generic vector friendly instruction format and instruction templates thereof according to embodiments of the disclosure.FIG. 20Ais a block diagram illustrating a generic vector friendly instruction format and class A instruction templates thereof according to embodiments of the disclosure; whileFIG. 20Bis a block diagram illustrating the generic vector friendly instruction format and class B instruction templates thereof according to embodiments of the disclosure. Specifically, a generic vector friendly instruction format2000for which are defined class A and class B instruction templates, both of which include no memory access2005instruction templates and memory access2020instruction templates. The term generic in the context of the vector friendly instruction format refers to the instruction format not being tied to any specific instruction set.

The class A instruction templates inFIG. 20Ainclude: 1) within the no memory access2005instruction templates there is shown a no memory access, full round control type operation2010instruction template and a no memory access, data transform type operation2015instruction template; and 2) within the memory access2020instruction templates there is shown a memory access, temporal2025instruction template and a memory access, non-temporal2030instruction template. The class B instruction templates inFIG. 20Binclude: 1) within the no memory access2005instruction templates there is shown a no memory access, write mask control, partial round control type operation2012instruction template and a no memory access, write mask control, vsize type operation2017instruction template; and 2) within the memory access2020instruction templates there is shown a memory access, write mask control2027instruction template.

The generic vector friendly instruction format2000includes the following fields listed below in the order illustrated inFIGS. 20A-20B.

Base operation field2042—its content distinguishes different base operations.

Modifier field2046—its content distinguishes occurrences of instructions in the generic vector instruction format that specify memory access from those that do not; that is, between no memory access2005instruction templates and memory access2020instruction templates. Memory access operations read and/or write to the memory hierarchy (in some cases specifying the source and/or destination addresses using values in registers), while non-memory access operations do not (e.g., the source and destinations are registers). While in one embodiment this field also selects between three different ways to perform memory address calculations, alternative embodiments may support more, less, or different ways to perform memory address calculations.

Augmentation operation field2050—its content distinguishes which one of a variety of different operations to be performed in addition to the base operation. This field is context specific. In one embodiment of the disclosure, this field is divided into a class field2068, an alpha field2052, and a beta field2054. The augmentation operation field2050allows common groups of operations to be performed in a single instruction rather than 2, 3, or 4 instructions.

Scale field2060—its content allows for the scaling of the index field's content for memory address generation (e.g., for address generation that uses 2scale*index+base).

Displacement Field2062A—its content is used as part of memory address generation (e.g., for address generation that uses 2scale*index+base+displacement).

Displacement Factor Field2062B (note that the juxtaposition of displacement field2062A directly over displacement factor field2062B indicates one or the other is used)—its content is used as part of address generation; it specifies a displacement factor that is to be scaled by the size of a memory access (N)—where N is the number of bytes in the memory access (e.g., for address generation that uses 2scale*index+base+scaled displacement). Redundant low-order bits are ignored and hence, the displacement factor field's content is multiplied by the memory operands total size (N) in order to generate the final displacement to be used in calculating an effective address. The value of N is determined by the processor hardware at runtime based on the full opcode field2074(described later herein) and the data manipulation field2054C. The displacement field2062A and the displacement factor field2062B are optional in the sense that they are not used for the no memory access2005instruction templates and/or different embodiments may implement only one or none of the two.

Class field2068—its content distinguishes between different classes of instructions. With reference toFIGS. 20A-B, the contents of this field select between class A and class B instructions. InFIGS. 20A-B, rounded corner squares are used to indicate a specific value is present in a field (e.g., class A2068A and class B2068B for the class field2068respectively inFIGS. 20A-B).

Instruction Templates of Class A

In the case of the non-memory access2005instruction templates of class A, the alpha field2052is interpreted as an RS field2052A, whose content distinguishes which one of the different augmentation operation types are to be performed (e.g., round2052A.1and data transform2052A.2are respectively specified for the no memory access, round type operation2010and the no memory access, data transform type operation2015instruction templates), while the beta field2054distinguishes which of the operations of the specified type is to be performed. In the no memory access2005instruction templates, the scale field2060, the displacement field2062A, and the displacement scale filed2062B are not present.

In the no memory access full round control type operation2010instruction template, the beta field2054is interpreted as a round control field2054A, whose content(s) provide static rounding. While in the described embodiments of the disclosure the round control field2054A includes a suppress all floating point exceptions (SAE) field2056and a round operation control field2058, alternative embodiments may support may encode both these concepts into the same field or only have one or the other of these concepts/fields (e.g., may have only the round operation control field2058).

SAE field2056—its content distinguishes whether or not to disable the exception event reporting; when the SAE field's2056content indicates suppression is enabled, a given instruction does not report any kind of floating-point exception flag and does not raise any floating point exception handler.

In the no memory access data transform type operation2015instruction template, the beta field2054is interpreted as a data transform field2054B, whose content distinguishes which one of a number of data transforms is to be performed (e.g., no data transform, swizzle, broadcast).

In the case of a memory access2020instruction template of class A, the alpha field2052is interpreted as an eviction hint field2052B, whose content distinguishes which one of the eviction hints is to be used (inFIG. 20A, temporal2052B.1and non-temporal2052B.2are respectively specified for the memory access, temporal2025instruction template and the memory access, non-temporal2030instruction template), while the beta field2054is interpreted as a data manipulation field2054C, whose content distinguishes which one of a number of data manipulation operations (also known as primitives) is to be performed (e.g., no manipulation; broadcast; up conversion of a source; and down conversion of a destination). The memory access2020instruction templates include the scale field2060, and optionally the displacement field2062A or the displacement scale field2062B.

Memory Access Instruction Templates—Temporal

Memory Access Instruction Templates—Non-Temporal

Instruction Templates of Class B

In the case of the instruction templates of class B, the alpha field2052is interpreted as a write mask control (Z) field2052C, whose content distinguishes whether the write masking controlled by the write mask field2070should be a merging or a zeroing.

In the case of the non-memory access2005instruction templates of class B, part of the beta field2054is interpreted as an RL field2057A, whose content distinguishes which one of the different augmentation operation types are to be performed (e.g., round2057A.1and vector length (VSIZE)2057A.2are respectively specified for the no memory access, write mask control, partial round control type operation2012instruction template and the no memory access, write mask control, VSIZE type operation2017instruction template), while the rest of the beta field2054distinguishes which of the operations of the specified type is to be performed. In the no memory access2005instruction templates, the scale field2060, the displacement field2062A, and the displacement scale filed2062B are not present.

In the no memory access, write mask control, partial round control type operation2010instruction template, the rest of the beta field2054is interpreted as a round operation field2059A and exception event reporting is disabled (a given instruction does not report any kind of floating-point exception flag and does not raise any floating point exception handler).

Round operation control field2059A—just as round operation control field2058, its content distinguishes which one of a group of rounding operations to perform (e.g., Round-up, Round-down, Round-towards-zero and Round-to-nearest). Thus, the round operation control field2059A allows for the changing of the rounding mode on a per instruction basis. In one embodiment of the disclosure where a processor includes a control register for specifying rounding modes, the round operation control field's2050content overrides that register value.

In the no memory access, write mask control, VSIZE type operation2017instruction template, the rest of the beta field2054is interpreted as a vector length field2059B, whose content distinguishes which one of a number of data vector lengths is to be performed on (e.g., 128, 256, or 512 byte).

In the case of a memory access2020instruction template of class B, part of the beta field2054is interpreted as a broadcast field2057B, whose content distinguishes whether or not the broadcast type data manipulation operation is to be performed, while the rest of the beta field2054is interpreted the vector length field2059B. The memory access2020instruction templates include the scale field2060, and optionally the displacement field2062A or the displacement scale field2062B.

With regard to the generic vector friendly instruction format2000, a full opcode field2074is shown including the format field2040, the base operation field2042, and the data element width field2064. While one embodiment is shown where the full opcode field2074includes all of these fields, the full opcode field2074includes less than all of these fields in embodiments that do not support all of them. The full opcode field2074provides the operation code (opcode).

The augmentation operation field2050, the data element width field2064, and the write mask field2070allow these features to be specified on a per instruction basis in the generic vector friendly instruction format.

Exemplary Specific Vector Friendly Instruction Format

FIG. 21is a block diagram illustrating an exemplary specific vector friendly instruction format according to embodiments of the disclosure.FIG. 21shows a specific vector friendly instruction format2100that is specific in the sense that it specifies the location, size, interpretation, and order of the fields, as well as values for some of those fields. The specific vector friendly instruction format2100may be used to extend the x86 instruction set, and thus some of the fields are similar or the same as those used in the existing x86 instruction set and extension thereof (e.g., AVX). This format remains consistent with the prefix encoding field, real opcode byte field, MOD R/M field, SIB field, displacement field, and immediate fields of the existing x86 instruction set with extensions. The fields fromFIG. 20into which the fields fromFIG. 21map are illustrated.

It should be understood that, although embodiments of the disclosure are described with reference to the specific vector friendly instruction format2100in the context of the generic vector friendly instruction format2000for illustrative purposes, the disclosure is not limited to the specific vector friendly instruction format2100except where claimed. For example, the generic vector friendly instruction format2000contemplates a variety of possible sizes for the various fields, while the specific vector friendly instruction format2100is shown as having fields of specific sizes. By way of specific example, while the data element width field2064is illustrated as a one bit field in the specific vector friendly instruction format2100, the disclosure is not so limited (that is, the generic vector friendly instruction format2000contemplates other sizes of the data element width field2064).

The generic vector friendly instruction format2000includes the following fields listed below in the order illustrated inFIG. 21A.

Format Field2040(EVEX Byte 0, bits [7:0])—the first byte (EVEX Byte 0) is the format field2040and it contains 0x62 (the unique value used for distinguishing the vector friendly instruction format in one embodiment of the disclosure).

The second-fourth bytes (EVEX Bytes 1-3) include a number of bit fields providing specific capability.

Data element width field2064(EVEX byte 2, bit [7]-W)—is represented by the notation EVEX.W. EVEX.W is used to define the granularity (size) of the datatype (either 32-bit data elements or 64-bit data elements).

EVEX.U2068Class field (EVEX byte 2, bit [2]-U)—If EVEX.0=0, it indicates class A or EVEX.U0; if EVEX.0=1, it indicates class B or EVEX.U1.

Alpha field2052(EVEX byte 3, bit [7]-EH; also known as EVEX.EH, EVEX.rs, EVEX.RL, EVEX.write mask control, and EVEX.N; also illustrated with a)—as previously described, this field is context specific.

Real Opcode Field2130(Byte 4) is also known as the opcode byte. Part of the opcode is specified in this field.

MOD R/M Field2140(Byte 5) includes MOD field2142, Reg field2144, and R/M field2146. As previously described, the MOD field's2142content distinguishes between memory access and non-memory access operations. The role of Reg field2144can be summarized to two situations: encoding either the destination register operand or a source register operand, or be treated as an opcode extension and not used to encode any instruction operand. The role of R/M field2146may include the following: encoding the instruction operand that references a memory address, or encoding either the destination register operand or a source register operand.

Scale, Index, Base (SIB) Byte (Byte 6)—As previously described, the scale field's2050content is used for memory address generation. SIB.xxx2154and SIB.bbb2156—the contents of these fields have been previously referred to with regard to the register indexes Xxxx and Bbbb.

Displacement field2062A (Bytes 7-10)—when MOD field2142contains 10, bytes 7-10 are the displacement field2062A, and it works the same as the legacy 32-bit displacement (disp32) and works at byte granularity.

Full Opcode Field

FIG. 21Bis a block diagram illustrating the fields of the specific vector friendly instruction format2100that make up the full opcode field2074according to one embodiment of the disclosure. Specifically, the full opcode field2074includes the format field2040, the base operation field2042, and the data element width (W) field2064. The base operation field2042includes the prefix encoding field2125, the opcode map field2115, and the real opcode field2130.

Register Index Field

FIG. 21Cis a block diagram illustrating the fields of the specific vector friendly instruction format2100that make up the register index field2044according to one embodiment of the disclosure. Specifically, the register index field2044includes the REX field2105, the REX′ field2110, the MODR/M.reg field2144, the MODR/M.r/m field2146, the VVVV field2120, xxx field2154, and the bbb field2156.

Augmentation Operation Field

FIG. 21Dis a block diagram illustrating the fields of the specific vector friendly instruction format2100that make up the augmentation operation field2050according to one embodiment of the disclosure. When the class (U) field2068contains 0, it signifies EVEX.U0 (class A2068A); when it contains 1, it signifies EVEX.U1 (class B2068B). When U=0 and the MOD field2142contains 11 (signifying a no memory access operation), the alpha field2052(EVEX byte 3, bit [7]-EH) is interpreted as the rs field2052A. When the rs field2052A contains a 1 (round2052A.1), the beta field2054(EVEX byte 3, bits [6:4]-SSS) is interpreted as the round control field2054A. The round control field2054A includes a one bit SAE field2056and a two bit round operation field2058. When the rs field2052A contains a 0 (data transform2052A.2), the beta field2054(EVEX byte 3, bits [6:4]-SSS) is interpreted as a three bit data transform field2054B. When U=0 and the MOD field2142contains 00, 01, or 10 (signifying a memory access operation), the alpha field2052(EVEX byte 3, bit [7]-EH) is interpreted as the eviction hint (EH) field2052B and the beta field2054(EVEX byte 3, bits [6:4]-SSS) is interpreted as a three bit data manipulation field2054C.

When U=1, the alpha field2052(EVEX byte 3, bit [7]-EH) is interpreted as the write mask control (Z) field2052C. When U=1 and the MOD field2142contains 11 (signifying a no memory access operation), part of the beta field2054(EVEX byte 3, bit [4]-S0) is interpreted as the RL field2057A; when it contains a 1 (round2057A.1) the rest of the beta field2054(EVEX byte 3, bit [6-5]-S2-1) is interpreted as the round operation field2059A, while when the RL field2057A contains a 0 (VSIZE 2057.A2) the rest of the beta field2054(EVEX byte 3, bit [6-5]-S2-1) is interpreted as the vector length field2059B (EVEX byte 3, bit [6-5]-L1-0). When U=1 and the MOD field2142contains 00, 01, or 10 (signifying a memory access operation), the beta field2054(EVEX byte 3, bits [6:4]-SSS) is interpreted as the vector length field2059B (EVEX byte 3, bit [6-5]-L1-1) and the broadcast field2057B (EVEX byte 3, bit [4]-B).

Exemplary Register Architecture

FIG. 22is a block diagram of a register architecture2200according to one embodiment of the disclosure. In the embodiment illustrated, there are 32 vector registers2210that are 512 bits wide; these registers are referenced as zmm0 through zmm31. The lower order 256 bits of the lower 16 zmm registers are overlaid on registers ymm0-16. The lower order 128 bits of the lower 16 zmm registers (the lower order 128 bits of the ymm registers) are overlaid on registers xmm0-15. The specific vector friendly instruction format2100operates on these overlaid register file as illustrated in the below tables.

In other words, the vector length field2059B selects between a maximum length and one or more other shorter lengths, where each such shorter length is half the length of the preceding length; and instructions templates without the vector length field2059B operate on the maximum vector length. Further, in one embodiment, the class B instruction templates of the specific vector friendly instruction format2100operate on packed or scalar single/double-precision floating point data and packed or scalar integer data. Scalar operations are operations performed on the lowest order data element position in an zmm/ymm/xmm register; the higher order data element positions are either left the same as they were prior to the instruction or zeroed depending on the embodiment.

Write mask registers2215—in the embodiment illustrated, there are 8 write mask registers (k0 through k7), each 64 bits in size. In an alternate embodiment, the write mask registers2215are 16 bits in size. As previously described, in one embodiment of the disclosure, the vector mask register k0 cannot be used as a write mask; when the encoding that would normally indicate k0 is used for a write mask, it selects a hardwired write mask of 0xFFFF, effectively disabling write masking for that instruction.

Alternative embodiments of the disclosure may use wider or narrower registers. Additionally, alternative embodiments of the disclosure may use more, less, or different register files and registers.

Exemplary Core Architectures

In-Order and Out-of-Order Core Block Diagram

InFIG. 23A, a processor pipeline2300includes a fetch stage2302, a length decode stage2304, a decode stage2306, an allocation stage2308, a renaming stage2310, a scheduling (also known as a dispatch or issue) stage2312, a register read/memory read stage2314, an execute stage2316, a write back/memory write stage2318, an exception handling stage2322, and a commit stage2324.

FIG. 23Bshows processor core2390including a front end unit2330coupled to an execution engine unit2350, and both are coupled to a memory unit2370. The core2390may be a reduced instruction set computing (RISC) core, a complex instruction set computing (CISC) core, a very long instruction word (VLIW) core, or a hybrid or alternative core type. As yet another option, the core2390may be a special-purpose core, such as, for example, a network or communication core, compression engine, coprocessor core, general purpose computing graphics processing unit (GPGPU) core, graphics core, or the like.

The front end unit2330includes a branch prediction unit2332coupled to an instruction cache unit2334, which is coupled to an instruction translation lookaside buffer (TLB)2336, which is coupled to an instruction fetch unit2338, which is coupled to a decode unit2340. The decode unit2340(or decoder or decoder unit) may decode instructions (e.g., macro-instructions), and generate as an output one or more micro-operations, micro-code entry points, micro-instructions, other instructions, or other control signals, which are decoded from, or which otherwise reflect, or are derived from, the original instructions. The decode unit2340may be implemented using various different mechanisms. Examples of suitable mechanisms include, but are not limited to, look-up tables, hardware implementations, programmable logic arrays (PLAs), microcode read only memories (ROMs), etc. In one embodiment, the core2390includes a microcode ROM or other medium that stores microcode for certain macro-instructions (e.g., in decode unit2340or otherwise within the front end unit2330). The decode unit2340is coupled to a rename/allocator unit2352in the execution engine unit2350.

The execution engine unit2350includes the rename/allocator unit2352coupled to a retirement unit2354and a set of one or more scheduler unit(s)2356. The scheduler unit(s)2356represents any number of different schedulers, including reservations stations, central instruction window, etc. The scheduler unit(s)2356is coupled to the physical register file(s) unit(s)2358. Each of the physical register file(s) units2358represents one or more physical register files, different ones of which store one or more different data types, such as scalar integer, scalar floating point, packed integer, packed floating point, vector integer, vector floating point status (e.g., an instruction pointer that is the address of the next instruction to be executed), etc. In one embodiment, the physical register file(s) unit2358comprises a vector registers unit, a write mask registers unit, and a scalar registers unit. These register units may provide architectural vector registers, vector mask registers, and general purpose registers. The physical register file(s) unit(s)2358is overlapped by the retirement unit2354to illustrate various ways in which register renaming and out-of-order execution may be implemented (e.g., using a reorder buffer(s) and a retirement register file(s); using a future file(s), a history buffer(s), and a retirement register file(s); using a register maps and a pool of registers; etc.). The retirement unit2354and the physical register file(s) unit(s)2358are coupled to the execution cluster(s)2360. The execution cluster(s)2360includes a set of one or more execution units2362and a set of one or more memory access units2364. The execution units2362may perform various operations (e.g., shifts, addition, subtraction, multiplication) and on various types of data (e.g., scalar floating point, packed integer, packed floating point, vector integer, vector floating point). While some embodiments may include a number of execution units dedicated to specific functions or sets of functions, other embodiments may include only one execution unit or multiple execution units that all perform all functions. The scheduler unit(s)2356, physical register file(s) unit(s)2358, and execution cluster(s)2360are shown as being possibly plural because certain embodiments create separate pipelines for certain types of data/operations (e.g., a scalar integer pipeline, a scalar floating point/packed integer/packed floating point/vector integer/vector floating point pipeline, and/or a memory access pipeline that each have their own scheduler unit, physical register file(s) unit, and/or execution cluster—and in the case of a separate memory access pipeline, certain embodiments are implemented in which only the execution cluster of this pipeline has the memory access unit(s)2364). It should also be understood that where separate pipelines are used, one or more of these pipelines may be out-of-order issue/execution and the rest in-order.

The set of memory access units2364is coupled to the memory unit2370, which includes a data TLB unit2372coupled to a data cache unit2374coupled to a level 2 (L2) cache unit2376. In one exemplary embodiment, the memory access units2364may include a load unit, a store address unit, and a store data unit, each of which is coupled to the data TLB unit2372in the memory unit2370. The instruction cache unit2334is further coupled to a level 2 (L2) cache unit2376in the memory unit2370. The L2 cache unit2376is coupled to one or more other levels of cache and eventually to a main memory.

In certain embodiments, a prefetch circuit2378is included to prefetch data, for example, to predict access addresses and bring the data for those addresses into a cache or caches (e.g., from memory2380).

By way of example, the exemplary register renaming, out-of-order issue/execution core architecture may implement the pipeline2300as follows: 1) the instruction fetch2338performs the fetch and length decoding stages2302and2304; 2) the decode unit2340performs the decode stage2306; 3) the rename/allocator unit2352performs the allocation stage2308and renaming stage2310; 4) the scheduler unit(s)2356performs the schedule stage2312; 5) the physical register file(s) unit(s)2358and the memory unit2370perform the register read/memory read stage2314; the execution cluster2360perform the execute stage2316; 6) the memory unit2370and the physical register file(s) unit(s)2358perform the write back/memory write stage2318; 7) various units may be involved in the exception handling stage2322; and 8) the retirement unit2354and the physical register file(s) unit(s)2358perform the commit stage2324.

Specific Exemplary In-Order Core Architecture

FIG. 24Ais a block diagram of a single processor core, along with its connection to the on-die interconnect network2402and with its local subset of the Level 2 (L2) cache2404, according to embodiments of the disclosure. In one embodiment, an instruction decode unit2400supports the x86 instruction set with a packed data instruction set extension. An L1 cache2406allows low-latency accesses to cache memory into the scalar and vector units. While in one embodiment (to simplify the design), a scalar unit2408and a vector unit2410use separate register sets (respectively, scalar registers2412and vector registers2414) and data transferred between them is written to memory and then read back in from a level 1 (L1) cache2406, alternative embodiments of the disclosure may use a different approach (e.g., use a single register set or include a communication path that allow data to be transferred between the two register files without being written and read back).

FIG. 24Bis an expanded view of part of the processor core inFIG. 24Aaccording to embodiments of the disclosure.FIG. 24Bincludes an L1 data cache2406A part of the L1 cache2404, as well as more detail regarding the vector unit2410and the vector registers2414. Specifically, the vector unit2410is a 16-wide vector processing unit (VPU) (see the 16-wide ALU2428), which executes one or more of integer, single-precision float, and double-precision float instructions. The VPU supports swizzling the register inputs with swizzle unit2420, numeric conversion with numeric convert units2422A-B, and replication with replication unit2424on the memory input. Write mask registers2426allow predicating resulting vector writes.

FIG. 25is a block diagram of a processor2500that may have more than one core, may have an integrated memory controller, and may have integrated graphics according to embodiments of the disclosure. The solid lined boxes inFIG. 25illustrate a processor2500with a single core2502A, a system agent2510, a set of one or more bus controller units2516, while the optional addition of the dashed lined boxes illustrates an alternative processor2500with multiple cores2502A-N, a set of one or more integrated memory controller unit(s)2514in the system agent unit2510, and special purpose logic2508.

Thus, different implementations of the processor2500may include: 1) a CPU with the special purpose logic2508being integrated graphics and/or scientific (throughput) logic (which may include one or more cores), and the cores2502A-N being one or more general purpose cores (e.g., general purpose in-order cores, general purpose out-of-order cores, a combination of the two); 2) a coprocessor with the cores2502A-N being a large number of special purpose cores intended primarily for graphics and/or scientific (throughput); and 3) a coprocessor with the cores2502A-N being a large number of general purpose in-order cores. Thus, the processor2500may be a general-purpose processor, coprocessor or special-purpose processor, such as, for example, a network or communication processor, compression engine, graphics processor, GPGPU (general purpose graphics processing unit), a high-throughput many integrated core (MIC) coprocessor (including 30 or more cores), embedded processor, or the like. The processor may be implemented on one or more chips. The processor2500may be a part of and/or may be implemented on one or more substrates using any of a number of process technologies, such as, for example, BiCMOS, CMOS, or NMOS.

The memory hierarchy includes one or more levels of cache within the cores, a set or one or more shared cache units2506, and external memory (not shown) coupled to the set of integrated memory controller units2514. The set of shared cache units2506may include one or more mid-level caches, such as level 2 (L2), level 3 (L3), level 4 (L4), or other levels of cache, a last level cache (LLC), and/or combinations thereof. While in one embodiment a ring based interconnect unit2512interconnects the integrated graphics logic2508, the set of shared cache units2506, and the system agent unit2510/integrated memory controller unit(s)2514, alternative embodiments may use any number of well-known techniques for interconnecting such units. In one embodiment, coherency is maintained between one or more cache units2506and cores2502-A-N.

In some embodiments, one or more of the cores2502A-N are capable of multithreading. The system agent2510includes those components coordinating and operating cores2502A-N. The system agent unit2510may include for example a power control unit (PCU) and a display unit. The PCU may be or include logic and components needed for regulating the power state of the cores2502A-N and the integrated graphics logic2508. The display unit is for driving one or more externally connected displays.

Exemplary Computer Architectures

Referring now toFIG. 26, shown is a block diagram of a system2600in accordance with one embodiment of the present disclosure. The system2600may include one or more processors2610,2615, which are coupled to a controller hub2620. In one embodiment the controller hub2620includes a graphics memory controller hub (GMCH)2690and an Input/Output Hub (IOH)2650(which may be on separate chips); the GMCH2690includes memory and graphics controllers to which are coupled memory2640and a coprocessor2645; the IOH2650is couples input/output (I/O) devices2660to the GMCH2690. Alternatively, one or both of the memory and graphics controllers are integrated within the processor (as described herein), the memory2640and the coprocessor2645are coupled directly to the processor2610, and the controller hub2620in a single chip with the IOH2650. Memory2640may include compartment code2640A, for example, to store code that when executed causes a processor to perform any method of this disclosure.

The optional nature of additional processors2615is denoted inFIG. 26with broken lines. Each processor2610,2615may include one or more of the processing cores described herein and may be some version of the processor2500.

The memory2640may be, for example, dynamic random access memory (DRAM), phase change memory (PCM), or a combination of the two. For at least one embodiment, the controller hub2620communicates with the processor(s)2610,2615via a multi-drop bus, such as a frontside bus (FSB), point-to-point interface such as Quickpath Interconnect (QPI), or similar connection2695.

In one embodiment, the coprocessor2645is a special-purpose processor, such as, for example, a high-throughput MIC processor, a network or communication processor, compression engine, graphics processor, GPGPU, embedded processor, or the like. In one embodiment, controller hub2620may include an integrated graphics accelerator.

There can be a variety of differences between the physical resources2610,2615in terms of a spectrum of metrics of merit including architectural, microarchitectural, thermal, power consumption characteristics, and the like.

In one embodiment, the processor2610executes instructions that control data processing operations of a general type. Embedded within the instructions may be coprocessor instructions. The processor2610recognizes these coprocessor instructions as being of a type that should be executed by the attached coprocessor2645. Accordingly, the processor2610issues these coprocessor instructions (or control signals representing coprocessor instructions) on a coprocessor bus or other interconnect, to coprocessor2645. Coprocessor(s)2645accept and execute the received coprocessor instructions.

Referring now toFIG. 27, shown is a block diagram of a first more specific exemplary system2700in accordance with an embodiment of the present disclosure. As shown inFIG. 27, multiprocessor system2700is a point-to-point interconnect system, and includes a first processor2770and a second processor2780coupled via a point-to-point interconnect2750. Each of processors2770and2780may be some version of the processor2500. In one embodiment of the disclosure, processors2770and2780are respectively processors2610and2615, while coprocessor2738is coprocessor2645. In another embodiment, processors2770and2780are respectively processor2610coprocessor2645.

Processors2770and2780are shown including integrated memory controller (IMC) units2772and2782, respectively. Processor2770also includes as part of its bus controller units point-to-point (P-P) interfaces2776and2778; similarly, second processor2780includes P-P interfaces2786and2788. Processors2770,2780may exchange information via a point-to-point (P-P) interface2750using P-P interface circuits2778,2788. As shown inFIG. 27, IMCs2772and2782couple the processors to respective memories, namely a memory2732and a memory2734, which may be portions of main memory locally attached to the respective processors.

Processors2770,2780may each exchange information with a chipset2790via individual P-P interfaces2752,2754using point to point interface circuits2776,2794,2786,2798. Chipset2790may optionally exchange information with the coprocessor2738via a high-performance interface2739. In one embodiment, the coprocessor2738is a special-purpose processor, such as, for example, a high-throughput MIC processor, a network or communication processor, compression engine, graphics processor, GPGPU, embedded processor, or the like.

Chipset2790may be coupled to a first bus2716via an interface2796. In one embodiment, first bus2716may be a Peripheral Component Interconnect (PCI) bus, or a bus such as a PCI Express bus or another third generation I/O interconnect bus, although the scope of the present disclosure is not so limited.

As shown inFIG. 27, various I/O devices2714may be coupled to first bus2716, along with a bus bridge2718which couples first bus2716to a second bus2720. In one embodiment, one or more additional processor(s)2715, such as coprocessors, high-throughput MIC processors, GPGPU's, accelerators (such as, e.g., graphics accelerators or digital signal processing (DSP) units), field programmable gate arrays, or any other processor, are coupled to first bus2716. In one embodiment, second bus2720may be a low pin count (LPC) bus. Various devices may be coupled to a second bus2720including, for example, a keyboard and/or mouse2722, communication devices2727and a storage unit2728such as a disk drive or other mass storage device which may include instructions/code and data2730, in one embodiment. Further, an audio I/O2724may be coupled to the second bus2720. Note that other architectures are possible. For example, instead of the point-to-point architecture ofFIG. 27, a system may implement a multi-drop bus or other such architecture.

Referring now toFIG. 28, shown is a block diagram of a second more specific exemplary system2800in accordance with an embodiment of the present disclosure. Like elements inFIGS. 27 and 28bear like reference numerals, and certain aspects ofFIG. 27have been omitted fromFIG. 28in order to avoid obscuring other aspects ofFIG. 28.

FIG. 28illustrates that the processors2770,2780may include integrated memory and I/O control logic (“CL”)2772and2782, respectively. Thus, the CL2772,2782include integrated memory controller units and include I/O control logic.FIG. 28illustrates that not only are the memories2732,2734coupled to the CL2772,2782, but also that I/O devices2814are also coupled to the control logic2772,2782. Legacy I/O devices2815are coupled to the chipset2790.

Referring now toFIG. 29, shown is a block diagram of a SoC2900in accordance with an embodiment of the present disclosure. Similar elements inFIG. 25bear like reference numerals. Also, dashed lined boxes are optional features on more advanced SoCs. InFIG. 29, an interconnect unit(s)2902is coupled to: an application processor2910which includes a set of one or more cores202A-N and shared cache unit(s)2506; a system agent unit2510; a bus controller unit(s)2516; an integrated memory controller unit(s)2514; a set or one or more coprocessors2920which may include integrated graphics logic, an image processor, an audio processor, and a video processor; an static random access memory (SRAM) unit2930; a direct memory access (DMA) unit2932; and a display unit2940for coupling to one or more external displays. In one embodiment, the coprocessor(s)2920include a special-purpose processor, such as, for example, a network or communication processor, compression engine, GPGPU, a high-throughput MIC processor, embedded processor, or the like.

FIG. 30is a block diagram contrasting the use of a software instruction converter to convert binary instructions in a source instruction set to binary instructions in a target instruction set according to embodiments of the disclosure. In the illustrated embodiment, the instruction converter is a software instruction converter, although alternatively the instruction converter may be implemented in software, firmware, hardware, or various combinations thereof.FIG. 30shows a program in a high level language3002may be compiled using an x86 compiler3004to generate x86 binary code3006that may be natively executed by a processor with at least one x86 instruction set core3016. The processor with at least one x86 instruction set core3016represents any processor that can perform substantially the same functions as an Intel® processor with at least one x86 instruction set core by compatibly executing or otherwise processing (1) a substantial portion of the instruction set of the Intel® x86 instruction set core or (2) object code versions of applications or other software targeted to run on an Intel® processor with at least one x86 instruction set core, in order to achieve substantially the same result as an Intel® processor with at least one x86 instruction set core. The x86 compiler3004represents a compiler that is operable to generate x86 binary code3006(e.g., object code) that can, with or without additional linkage processing, be executed on the processor with at least one x86 instruction set core3016. Similarly,FIG. 30shows the program in the high level language3002may be compiled using an alternative instruction set compiler3008to generate alternative instruction set binary code3010that may be natively executed by a processor without at least one x86 instruction set core3014(e.g., a processor with cores that execute the MIPS instruction set of MIPS Technologies of Sunnyvale, Calif. and/or that execute the ARM instruction set of ARM Holdings of Sunnyvale, Calif.). The instruction converter3012is used to convert the x86 binary code3006into code that may be natively executed by the processor without an x86 instruction set core3014. This converted code is not likely to be the same as the alternative instruction set binary code3010because an instruction converter capable of this is difficult to make; however, the converted code will accomplish the general operation and be made up of instructions from the alternative instruction set. Thus, the instruction converter3012represents software, firmware, hardware, or a combination thereof that, through emulation, simulation or any other process, allows a processor or other electronic device that does not have an x86 instruction set processor or core to execute the x86 binary code3006.