LED driver with adaptive dynamic headroom voltage control

A multi-channel LED driver includes a plurality of linear current regulators, each connected to a bottom of a string of series connected LEDs of a multi-channel LED that controls a bias current and the string of series connected LEDs responsive to an LED bias reference voltage. A dynamic headroom regulation voltage control circuit monitors the headroom regulation voltage at the bottom of each string of the series connected LEDs in the multi-channel LED and generates a reference voltage controlling each of the headroom regulation voltages responsive to the LED bias reference voltage.

BRIEF DESCRIPTION OF THE DRAWINGS

For a more complete understanding, reference is now made to the following description taken in conjunction with the accompanying Drawings in which:

FIG. 1is a block diagram of a multi-channel LED driver using adaptive dynamic headroom voltage control;

FIG. 2is a block diagram of the control logic for determining a minimum dynamic headroom control regulation voltage;

FIG. 3is a schematic block diagram of the logic for generating a load dependent threshold voltage within an adaptive dynamic headroom voltage control scheme; and

FIG. 4illustrates various waveforms associated with the operation of the dynamic headroom voltage control circuit ofFIG. 1.

FIG. 5illustrates a flow diagram describing the operation of the circuit ofFIG. 1.

DETAILED DESCRIPTION

Referring now to the drawings, wherein like reference numbers are used herein to designate like elements throughout, the various views and embodiments of an LED driver with adaptive dynamic headroom voltage control are illustrated and described, and other possible embodiments are described. The figures are not necessarily drawn to scale, and in some instances the drawings have been exaggerated and/or simplified in places for illustrative purposes only. One of ordinary skill in the art will appreciate the many possible applications and variations based on the following examples of possible embodiments.

In view of the expanded use of various portable electronic devices, LEDs have been widely adopted in many applications such as backlighting, illuminations, etc. Many of these applications within various portable electronic devices require multiple LEDs that are tied together in order to generate more lumens. One manner for implementing this is to place the LEDs in series such that all LEDs are running at the same time and provide the same or similar brightness. However, when more LEDs are placed in series, this increases the requirements of the required operating voltage. The higher operating voltage requirements cause a need for higher cost semi-conductor devices within the device.

Another solution is to place the LEDs in a hybrid connection where multiple strings are placed in parallel. However, this solution presents additional problems. First, the brightness balance of each channel must be maintained by the associated circuitry. Additionally, the LED forward voltage variations must be regulated. These problems are related to each other. Thus, there is a need to provide an adaptive dynamic headroom voltage control approach for multiple channel LED drivers in order to improve operating efficiency of a hybrid connection. Rather than using a fixed dynamic headroom control regulation voltage, a load dependent regulation voltage may be used to reduce power losses in all loading conditions. This type of LED driving system overcomes the problems discussed with the previously implemented solutions.

Referring now to the drawings, and more particularly toFIG. 1, there is illustrated a block diagram of a multi-channel LED driver using adaptive dynamic headroom voltage control. The circuit includes a voltage regulator102that may comprise a DC/DC converter such as a boost converter, buck converter, buck-boost converter, etc. The voltage regulator102provides a regulated output voltage VOUTat node104to a plurality of LED strings106that are connected in parallel with each other between node104and nodes108. The voltage regulator102generates a single output voltage for each of the LED strings106. The output voltage VOUTprovided by the voltage regulator102is controlled by the headroom regulation voltage (VD1to VDN) provided at node108at the bottom of each LED string106. The multi-channel LED driver circuitry110ensures that the LED strings106have enough forward voltage to maintain the bias current through the LED strings106. The voltage regulator102receives an input voltage VINand a reference voltage VREFfrom the output of a multi-channel LED driver110. The voltage regulator102additionally monitors a feedback voltage VFBthat is responsive to the regulated output voltage VOUTsupplied from the voltage regulator102at node104.

The feedback voltage VFBis provided at a node112of a resistor divider circuit114. The resistor divider circuit114consists of a resistor116connected between node104and node112and a resistor118connected between node112and ground. A load capacitor120is connected in series with the resistor divider114between node104and ground. The multiple parallel LED strings106are connected at their top ends to the output voltage node104and at their bottom ends to an associated node108. Each LED string106consists of a plurality of LEDs that are connected in series with each other between node104and nodes108. The voltage provided at the bottom of each LED string106at nodes108comprises the headroom regulation voltage. Each LED string106has a separate headroom regulation voltage associated therewith that is monitored by the multi-channel LED driver circuitry110at nodes108.

The current through the LED string106is controlled by a linear current regulator consisting of transistor122, resistor124and error amplifier126. The linear regulator provides high accuracy control of the bias current through the LED string106. In this manner, a current balance is achieved and signal VLEDprovided from a controller at a higher system level sets the bias current of the LED strings and is equal to VLED=ILED*RSNS1. VLEDis a reference voltage used to set the current value through each LED string. The LED current is regulated to be VLED/RSNS1. RSNS1 is resistor124. VLEDsets the current of the LED strings. Headroom voltages VD1to VDN play important roles to the LED driving system. VD1to VDNmust be maintained at a proper level such that the power losses on MOSFET transistor122for each LED channel are minimized while the LED bias current is not compromised. This means that all MOSFET transistors122operate in their saturated region.

The N-channel transistor122has its drain/source path connected between node108and node128. The resistor124is connected between node128and ground. The error amplifier126has its output connected to the gate of transistor122. The inverting input of error amplifier126is connected to node128and its non-inverting input is connected to receive the signal VLEDfrom a controller at a higher system level. The signal VLEDis also provided to the load dependent comparison logic130of the multi-channel LED driver circuitry110. Each LED string106includes the same combination of the transistor122, resistor124and error amplifier126at the headroom regulation voltage node108at the bottom of each LED string. The VLEDsignal is applied to the non-inverting input of each comparator126associated with an LED string106.

The remainder of the multi-channel LED driver circuitry110includes find minimum logic132, load dependent comparison logic130, up-down counter134, clock136and digital to analog converter138. The find minimum logic132is connected to each of the nodes108at the bottom of each LED string106to detect the headroom regulation voltage from the bottom of each of the LED strings106. The find minimum logic132compares each of the headroom voltages VDnat the bottom of each LED string106to determine the minimum headroom voltage VDMINand provide it to the load dependent comparison logic130. As will be more fully described herein below, the find minimum logic132comprises a comparator array that determines the minimum headroom voltage of all the voltages at the bottom of each LED string106. The find minimum logic132guarantees that the headroom voltage is above a safe operating region.

The load dependent comparison logic130receives the minimum headroom voltage VDMINfrom the find minimum logic132and receives the VLEDvoltage signal. The load dependent comparison logic130provides UP and DOWN control signals to an up-down counter circuit134. The load dependent comparison logic130is a control circuit that ensures that the headroom regulation voltages (VD1to VDn) are low enough to achieve maximum power efficiency for driving the multiple LED strings106. If the minimum headroom regulation voltage VDi (i=1 . . . N) is lower than a particular threshold, the load dependent comparison logic130generates a logical “high” value on the UP signal line. Otherwise, the load dependent comparison logic130generates a logical “high” value on the DOWN signal line to the up-down counter circuit134. These UP and DOWN control values are used to alter the output voltage VOUTof the voltage regulator102.

The up-down counter circuit134receives the UP-DOWN control signals from the load dependent comparison logic130and a clock signal from a clock circuit136. The up-down counter134, clock circuit136and DAC138act as a reference voltage generator. The reference voltage generator is driven by the internal clock signal generated by the clock circuit136. During each cycle, the counter134counts the “UP” or “DOWN” signal that will increase or decrease the reference voltage VREF. The N-bit digital signal is a digital value of a desired reference voltage VREF. The up-down counter circuit130generates the N-bit digital signal to the digital to analog converter138. The digital to analog converter138generates a reference voltage signal VREFresponsive to the N-bit digital signal from the up-down counter134which is provided to the voltage regulator102as the reference voltage VREF.

Referring now toFIG. 2, there is illustrated a block diagram of the find minimum logic132ofFIG. 1. Each of the headroom voltages at nodes108are divided into pairs and every two headroom voltages, e.g., VD1and VD2, are compared with each other using a comparator202. The smaller of the two voltages is output from an associated multiplexer204such that this voltage may be compared with a lower voltage provided from another multiplexer204. In this way, the minimum voltage determined by comparator202is output from the multiplexer204such the voltage they may be compared in another comparator206which will output the lower of another two headroom voltages from another multiplexer208. This process will continue until the last two minimum voltages are compared, and the minimum overall headroom voltage VDMINis determined. Thus, N−1 comparators are used to determine the minimum headroom voltage VDMIN. This is a much more efficient process than using direct comparison where each headroom voltage (VDi) is directly compared to a threshold and would require 2Ncomparators. Thus, the comparison process described within the find minimum logic132is much more die size efficient.

As illustrated inFIG. 2, a comparator202compares each pair of adjacent headroom voltages from each of the nodes108at the bottom of an LED string106. The result of each comparison from a comparator202is used to control a multiplexer204that is also receiving the two headroom voltages that are being compared at the comparator202. The output of the comparator202selects the minimum voltage from the multiplexer204this is provided at the output thereof. The multiplexer204provides its outputs to a next set of comparators206that compare additional pairs of voltages to generate a further selection control signal. This selection control signal again selects from a multiplexer208the minimum of the pair of threshold voltages compared at the comparator206. The process continues through multiple layers of circuitry consisting of comparators202and multiplexers204until only a single threshold voltage, the minimum threshold voltage, VDMINis remaining. This is the signal that is provided to the input of the load dependent comparison logic130.

Referring now toFIG. 3, there is illustrated a schematic block diagram of the load dependent comparison logic130. If VDMINis higher than VHIGH, the DOWN signal is set to a logical “high” level indicating that the output of the voltage regulator102VOUTneeds to drop. If VDMINis lower than VLOW, the UP control signal is set to a logical “high” level indicating that the output voltage VOUTof the voltage regulator102needs to rise. The load dependent comparison logic130generates the DOWN control signals and UP control signals responsive to minimum threshold voltage VDMINand two load dependent threshold voltages VHIGHand VLOW. The load dependent comparison logic130includes a pair of comparators302and304for generating the DOWN and UP control signals. The VHIGHload dependent threshold voltage is applied to the inverting input of comparator302while the minimum threshold voltage VDMINis applied to the non-inverting input of comparator302. Comparator302generates the DOWN control signal when VDMINexceeds VHIGH. The load dependent threshold voltage VLOWis applied to the non-inverting input of comparator304, and the minimum threshold voltage VDMINis applied to the inverting input of comparator304. This is used to generate the UP control signal when the VDMINvoltage falls below the VLOWload dependent threshold voltage. The remainder of the circuitry ofFIG. 3is used for generating the load dependent threshold voltages VHIGHand VLOW.

The LED bias voltage reference VLEDis applied to the non-inverting input of amplifier306. Error amplifier306, N-channel transistor308and resistor314form a current source, the current of whish is VLED/R1 (tracking the current of the LED strings), which is turned around by316-318current mirror and create a Vlowvoltage on resistor324. The output of the error amplifier306is provided to the gate of N-channel transistor308. N-channel transistor308has its drain/source path connected between node310and node312. A resistor314is connected between node312and ground. The inverting input of error amplifier306is connected to node312. A current mirror consisting of transistors316and318is connected to the drain of transistor310. Transistor316comprises a P-channel transistor having its source/drain path connected between node320and node310. Transistor318is an P-channel transistor having its source/drain path connected between VSSand node322. The gates of transistors316and318are connected with each other and to node310. Node322provides the low load dependent threshold voltage VLOWwhich is provided to the non-inverting input of comparator304. A resistor324is connected between node322and ground. A current source IOS326is connected between node320and node328. Node328provides the high load dependent threshold voltage VHIGHat node328to the inverting input of comparator302. A resistor330is connected between node328and node322.

The LED bias voltage VLEDis scaled according to the ratio of resistor324and314in the ratio of R2/R1. An offset current is overlaid on VLED×R2/R1. Thus, the low load dependent threshold voltage VLOW=VLED×R2/R1+IOS×R2, and the high load dependent threshold voltage VHIGH=VLED×R2/R1+IOS×R2+IOS×R3. IOS×R3comprises a hysteresis voltage. As long as VDMINis within the range of the hysteresis voltage, the output voltage VOUTremains unchanged. VHIGHand VLOWshould be high enough such that under all conditions, MOSFET transistor122(FIG. 1) can sustain the LED bias voltage with enough margin. The worst case scenario happens in high temperature and low driving voltage as the channel resistance is high.

Referring now toFIG. 4, there is illustrated the operation of the LED drivers. In this configuration, two strings of LEDs are deployed with different forward voltages. Plane402illustrates the LED current reference signal VLED, changing this signal changes the LED brightness. It is set to be up and down for demonstration purposes. The second pane404illustrates two headroom regulation voltages of the different LED voltages. The third pane406illustrates the LED bias currents of different strings that are equal in a steady state. Finally, the fourth pane,408, illustrates the output voltage of the voltage regulator102as it changes following the trend of the LED bias voltage current as desired.

Referring now toFIG. 5, there is illustrated a flow diagram describing the operation of the circuit ofFIG. 1. Initially, the LED current is set by setting VLED at step500. The headroom regulation voltage is monitored at nodes108at the bottom of each LED string at step502. A determination is made by the find minimum logic132of the minimum headroom regulation voltage at step504using the layered comparator circuitry described with respect toFIG. 2. The minimum headroom regulation voltage is compared with a scaled VLED voltage of VLOWand another threshold voltage VHIGHwhish is an offset voltage higher than VLOW. and load dependent threshold voltages at step508. Inquiry step510determines if the headroom regulation voltage exceeds the high load dependent threshold voltage. If so, a signal is generated to decrease the reference voltage at step512which will alter the output voltage at step513within the voltage regulator102. If inquiry step510determines that the headroom regulation voltage does not exceed the high load dependent threshold voltage, inquiry step514determines if the headroom regulation voltage is below the low load dependent threshold voltage VLOW. If so, the reference voltage is caused to increase at step516which will increase the reference voltage when VOUTis set according to Vrefat step513. If inquiry step514does not determine that the headroom regulation voltage is below the low load dependent threshold voltage, the reference voltage is maintained at step518at its present level. The reference level will cause the VOUTto be set at the present level at step513.

Using the above-described approach, better efficiency within light and medium load operating conditions of a voltage regulator may be achieved. This will extend the battery life of a portable electronic device in a simple and robust manner. The adaptive dynamic headroom control approach uses a load dependent voltage for the DHC regulation voltage instead of a fixed value. This improves the efficiency in light and medium load conditions in the described manner.

It will be appreciated by those skilled in the art having the benefit of this disclosure that this LED driver with adaptive dynamic headroom voltage control provides improved control of a multi-LED string. It should be understood that the drawings and detailed description herein are to be regarded in an illustrative rather than a restrictive manner, and are not intended to be limiting to the particular forms and examples disclosed. On the contrary, included are any further modifications, changes, rearrangements, substitutions, alternatives, design choices, and embodiments apparent to those of ordinary skill in the art, without departing from the spirit and scope hereof, as defined by the following claims. Thus, it is intended that the following claims be interpreted to embrace all such further modifications, changes, rearrangements, substitutions, alternatives, design choices, and embodiments.