METHOD FOR GAP FILLING WITH SELECTIVELY FORMED SEED LAYER AND HETEROEPITAXIAL CAP LAYER

Embodiments of the present disclosure provide a method for selectively forming a seed layer over semiconductor fins. Some embodiments provide forming the selective seed layer using a mono-silane at an increased temperature. Some embodiments provide depositing a hetero-crystalline silicon cap layer over the bottom-up gap layer to improve gap filling and tune profiles of fin structures.

BACKGROUND

With the increasing down scaling of semiconductor devices, various processing techniques are adapted to allow for the manufacture of devices with increasingly smaller dimensions. As semiconductor devices continue to shrink, the spacing between elements, i.e., the pitch, of a device also reduces. However, traditional techniques and/or process flows may hinder pitch reduction.

Therefore, there is a need to solve the above problems.

DETAILED DESCRIPTION

The foregoing broadly outlines some aspects of embodiments described in this disclosure. While some embodiments described herein are described in the context of nanosheet channel FETs, implementations of some aspects of the present disclosure may be used in other processes and/or in other devices, such as planar FETs, Fin-FETs, Horizontal Gate All Around (HGAA) FETs, Vertical Gate All Around (VGAA) FETs, and other suitable devices. A person having ordinary skill in the art will readily understand other modifications that may be made are contemplated within the scope of this disclosure. In addition, although method embodiments may be described in a particular order, various other method embodiments may be performed in any logical order and may include fewer or more steps than what is described herein. In the present disclosure, a source/drain refers to a source and/or a drain. A source and a drain are interchangeably used.

Gap-filling processes are used in various stages of FinFET fabrication. For example, depositing a sacrificial gate electrode layer in trenches between fin structures. As the dimension of the semiconductor device reduces, aspect ratio of trenches in FinFET also increases, which results in more challenges faced by trench gap-filling. The aspect ratio is even higher in trenches between semiconductor fins and dielectric fins. Embodiments of present disclosure provide a method for gap-filling. In some embodiments, a seed layer is selectively formed on sidewalls of trenches is deposited prior to a bottom-up gap filling deposition process. Compared to a uniform seed layer, the selective seed layer of the present disclosure reduces aspect ratio increase caused by the seed layer prior to gap filling. In some embodiments, a heteroepitaxial cap layer is used over the bottom-up gap filling layer. For example, a cap layer according to the present disclosure may include a layer of amorphous silicon (a-Si) and a layer of crystalline silicon (c-Si). Composition of the heteroepitaxial cap layer may be selected to tune profiles of semiconductor fins. For example, a-Si may be selected to reduce outward bending of fin structures, and c-Sil may be selected to achieve outward bending of fin structures.

FIGS.1-3,4A-4J,5A-5F,6A-6C,7A-7B,8-10, and11A-11Bschematically illustrate a semiconductor device100at various stages of fabrication according to a method according to the present disclosure. Particularly,FIGS.1-3,4A-4J,5A-5F,6A-6C,7A-7B,8-10, and11A-11Bare schematic views of the semiconductor device100at various stages of manufacturing the semiconductor device according to embodiments of the present disclosure.FIG.12is a flow chart of an exemplary method200for forming a semiconductor device according to embodiments of the present disclosure. As discussed below, the semiconductor device100may be fabricated using the method200.

At operation202of the method200, fin structures104are formed on a substrate102, as shown inFIG.1.FIG.1is a schematic perspective view of the semiconductor device100after operation202. The substrate102may include a single crystalline semiconductor material such as, but not limited to Si, Ge, SiGe, GaAs, InSb, GaP, GaSb, InAIAs, InGaAs, GaSbP, GaAsSb, and InP. The substrate102may include various doping configurations depending on circuit design. For example, different doping profiles, e.g., n-wells, p-wells, may be formed in the substrate102in regions designed for different device types, such as n-type field effect transistors (NFET), and p-type field effect transistors (PFET). In some embodiments, the substrate102may be a silicon-on-insulator (SOI) substrate including an insulator structure for enhancement.

In some embodiments, the fin structures104may be formed depositing epitaxial semiconductor layers over the substrate102according to the device type to be formed. The fin structures104are then formed by lithography and etching processes using one or more patterning layers. In some embodiments, the fin structures104may include fin structures104afor a first type of devices and fin structures104bfor a second type of devices.

Each of the fin structures104amay include a well portion106aformed in a first well region of the substrate102, and a fin portion108aformed from the epitaxially grown layer over the substrate102. The fin portion108amay include epitaxially grown silicon germanium (SiGe), epitaxially grown silicon (Si), or other epitaxially grown semiconductor materials, such as germanium (Ge), a compound semiconductor such as SiC, GeAs, GaP, InP, InAs, and/or InSb, an alloy semiconductor such as GaAsP, AlInAs, AlGaAs, InGaAs, GaInP, and/or GaInAsP, or combinations thereof. In some embodiments, the fin structures104aare configured to function of channel regions for N-type devices. The well portion106amay include p-type dopants. The fin portion108aof the fin structures104amay include epitaxially grown silicon.

Each of the fin structures104bmay include a well portion106bformed in a second well region of the substrate102, and a fin portion108bformed from the epitaxially grown layer over the substrate102. The fin portion108bmay include epitaxially grown Si, epitaxially grown SiGe, or other epitaxially grown semiconductor materials, such as Ge, a compound semiconductor such as SiC, GeAs, GaP, InP, InAs, and/or InSb, an alloy semiconductor such as GaAsP, AlInAs, AlGaAs, InGaAs, GaInP, and/or GaInAsP, or combinations thereof. In some embodiments, the fin structures104bare configured to function of channel regions for P-type devices. The well portion106bmay formed in a n-well and includes n-type dopants. The fin portion108bof the fin structures104bmay include epitaxially grown SiGe.

The fin structures104extend from the substrate102forming trenches between neighboring fins. As shown inFIG.1, trenches110aare formed between neighboring fin structures104a, trenches110bare formed between neighboring fin structures104b, and trenches112are formed between neighboring fin structures104a,104b. The trenches112are wider than the trenches110a,110b. In some embodiments, dielectric fins may be subsequently formed in the trenches112to isolate transistors on opposite sides of the trenches112.

In operation204, isolation layer114and dielectric fin120are formed in trenches110,112between the fin structures104, as shown inFIG.2.FIG.2is a schematic perspective view of the semiconductor device100after operation204.

The isolation layer114is formed in the trenches between the fin structures104by a suitable deposition followed by an etch back process. The bottom profile of the isolation layer114is shown to be curved as an example. Depending on pitch and/or height of the fin structures104, a bottom profile of the isolation layer114may vary, for example curved, substantially flat, or other shapes. The isolation layer114may be formed by a high-density plasma chemical vapor deposition (HDP-CVD), a flowable CVD (FCVD), or other suitable deposition process. In some embodiments, the isolation layer114may include silicon oxide, silicon nitride, silicon oxynitride, fluorine-doped silicate glass (FSG), a low-k dielectric, or combinations thereof.

In some embodiments, the isolation layer114may be conformally formed. After deposition of the isolation layer114, the narrower trenches110a,110bmay be fully filled while the wider trenches112are partially filled so that the dielectric fins120may be formed therein. In some embodiments, a liner layer116and a dielectric filling layer118are then sequentially deposited over the isolation layer114to fill the trench112. The liner layer116may be selected from a dielectric material with etch selectivity to allow the isolation layer114to be etched back. In some embodiments, the liner layer116and dielectric filling layer118may include a low-k material, such as SiONC, SiCN, SiOC, or other dielectric material, that provide etch resistance during replacement gate processes.

After the trenches110,112between the fin structures104are filled, a planarization process may be performed to expose the fin structures104, and then recess etched using a suitable anisotropic etching process to remove a portion of the isolation layer114. After the recess etch, the fin portions108a,108bof the fin structures104a,104bare exposed and extending from the isolation layer114. In the trench112, the dielectric fin120is formed. As shown in the example ofFIG.2, the dielectric fin120extends from the isolation layer114. In some embodiments, the liner layer116may be etch from the dielectric filling layer118so that sidewalls of the dielectric fin120comprise the dielectric filling layer118.

The dielectric fins120, also referred to as dummy fins or hybrid fins, may include one or more layers of dielectric materials sequentially deposited within the trench112. For example, the dielectric fins120may include a high-k dielectric material layer, such as HfO2, ZrO2, HfAlOx, HfSiOx, Al2O3, and the like; a low-k dielectric material layer, SiONC, SiCN, SiOC, or other dielectric material; or a bi-layer dielectric material including high-k upper part and a low-k lower part. In some embodiments, an external layer of the dielectric fins120may be selected from a material to facilitate selective formation of a seed layer, as discussed below. In some embodiments, sidewalls120sof the dielectric fins120comprise SiCN. In some embodiments, the sidewalls120sof the dielectric fins120comprises SiCN with a carbon molar concentration in a range between about 8% and about 16%, for example about 12%.

After operation204, the fin structures104have a height H1along the Z-direction over the isolation layer114. The height H1may vary according to circuit design. In some embodiments, the height H1is in a range between about 20 nm to about 100 nm. The trenches110a,110bhave a width W1along the Y direction. In some embodiments, the width W1is in a range from about 3 nm to about 50 nm.

In some embodiments, the dielectric fins120may extend from the isolation layer114for the substantially the same height H1as the fin structures104. Trenches112a,112bare formed on opposite sides of the dielectric fin120. In some embodiments, the trenches112a,112bhave a width W2along the Y direction. In some embodiments, the width W2is in a range from about 3 nm to about 50 nm. In some embodiments, the width W2may be narrower than the width W1.

In operation206, a sacrificial gate dielectric layer122is formed over the fin structures104, as shown inFIG.3.FIG.3is a schematic cross-sectional view of the semiconductor device100. The sacrificial gate dielectric layer122is formed over the fin structures104. The sacrificial gate dielectric layer122may include oxides of semiconductor material. In some embodiments, the sacrificial gate dielectric layer122may be thermally grown from the fin structures104according to acceptable techniques, such as thermal CVD, CVD, ALD, and other suitable methods.

In some embodiments, the sacrificial gate dielectric layer122may have a thickness in a range between about 1 nm and about 3 nm. As shown inFIG.3, after formation of the sacrificial gate dielectric layer122, width of the trenches110a/110band112a/112bmay be reduced to width W1′ and W2′ respectively. Aspect ratio, i.e. a ratio of the fin height H1over the widths W1′/W2′, of the trenches110a/110band112a/112bare increased. In some embodiments, the aspect ratio of the trenches110a/110band112a/112bmay be greater than 5. A greater aspect ratio makes it difficult to fill the trenches110a/110band112a/112bwith a sacrificial gate electrode layer. For example, seams and/or voids may be formed in the sacrificial gate electrode layer. The seams and voids may lead to allow epitaxial source/drain or source/drain contact to sip in the gate structure, causing leakage. Operations208-214provide an improve gap filling process to form a sacrificial gate electrode layer between the trenches110a/110band112a/112band over the fin structures104.

In operation208, a seed layer124is selectively formed over the fin structures104, as shown inFIGS.4A-4C. Particularly, the seed layer124are formed over the sidewalls of the fin structures104, but not on the sidewalls120sof the dielectric fin120. By selectively forming the seed layer124on the semiconductor fin structures104, embodiments of the present disclosure avoid further increasing aspect ratio of the trenches between the semiconductor fins and the dielectric fins, such as the trenches112a,112b.FIGS.4A-4Care cross-sectional views of the semiconductor device100during various phases of forming the seed layer124.

In some embodiments, the seed layer124may be formed by a deposition process, an etch process, and a surface treatment. For example, the operation208may be performed using a method300shown inFIG.13.

The method300includes an operation302, a non-uniform deposition process is performed to deposit a seed layer1240over the semiconductor device100, as shown inFIG.4A. The seed layer1240includes a thicker and continuous portion1241formed over the semiconductor fin structures104and a thinner and discontinuous portion1242formed over the dielectric fin120. In some embodiments, the seed layer1240is a silicon seed layer. In some embodiments, the seed layer1240may be a silicon layer free from other elements such as germanium, n-type impurities (such as phosphorous and arsenic), and p-type impurities (such as boron and indium). In some embodiments, the thicker and continuous portion1241of the seed layer1240may have a thickness in the range between about 5 Å and about 25 Å. The thinner and discontinuous portion1242of the seed layer1240may have a single atomic layer of silicon that is not continuous.

The seed layer1240may be deposited using a suitable deposition, such as atomic layer deposition (ALD). The non-uniformity or selectivity of the deposition may be achieved by selecting a suitable precursor and a suitable processing condition according to the surface composition on the fin structures104and the dielectric fin120. In some embodiments, the seed layer1240is deposited using a mono-silicon containing precursor and at an increased temperature to reduce deposition rate on the sidewalls120sof the dielectric fin120. In some embodiments, when the sidewalls120sof the dielectric fin120includes SiCN while the fin structures104a,104bare Si and SiGe, the seed layer1240may be deposited using monosilane (SiH4). The deposition may be performed at a temperature in a range between about 460° C. and about 480° C., for example, about 470° C.

The method300further includes an operation304performed after the operation302. In operation304, an etch process is performed to remove a portion of the seed layer1240. In some embodiments, the dry etch process may be an ex-situ dry etch process performed to substantially remove the thinner and discontinuous portion1242of the seed layer1240, as shown inFIG.4B.

In some embodiments, the dry etch process may be an isotropic etch process. In some embodiments, the etchant gas may include a mixture of chlorine (Cl2) and nitrogen (N2), a mixture of fluorine (F2) and nitrogen (N2), or a mixture of NF3, H2, and helium (He), or HCl. In some embodiments, the etching may be performed using, for example, Reactive Ion Etch (RIE). In some embodiments, the etching process may be performed for a time period between about 3 seconds and 8 seconds, for example about 5 seconds.

As shown inFIG.4B, after the etch process in operation304, the thinner and discontinuous portion1242of the seed layer1240may be substantially removed from the dielectric fins120. The thicker and continuous portion1241of the seed layer1240is reduced to a continuous portion1243, which a thickness in the range between about 3 Å and about 20 Å. In some embodiments, agglomerates1244may result on surfaces of the semiconductor device100, such as on the sidewalls120sof the dielectric fin120.

The method300further includes an operation306, in which a surface treatment is performed to remove particles and agglomerates1244, as shown inFIG.4C. In some embodiments, the surface treatment in the operation306may be a selective surface treatment to achieve highly selective surface property modification, for example to selectively remove the surface agglomerates1244. In some embodiments, the surface treatment may be performed by flowing inert atoms, such as argon, over the surface of the semiconductor device100to a process chamber and generating very gentle radical plasma to remove the agglomerates1244. For example, the radials used during the surface treatment carry an energy in a range between about 1% to about 10% of the plasma energy level during a plasma each. For example, the radials may be argon atoms at an energy level around 11.7 eV. In some embodiments, the surface treatment may be performed using Argos system by Lamb Technologies, Inc.

FIG.4Cschematically illustrates the semiconductor device100after operation208. As shown inFIG.4C, the seed layer124is selectively formed over the semiconductor fin structures104while no seed layer is formed over the dielectric fin120.

It has been proven that when forming a dielectric fin with SiCN containing surface and using monosilane as a precursor to deposit a silicon seed layer, the silicon seed layer can be selectively deposited on the semiconductor fins.FIGS.4D-4Fare schematic plot of surface composition using x-ray photoelectron spectroscopy (XPS) on a SiCN surface having 12% of carbon in molar percentage under different deposition conditions. InFIG.4D, curve402is a plot of normalized surface composition of on the SiCN surface using disilane (Si2H6), as precursor; curve404is a plot of normalized surface composition of on the SiCN surface using monosilane as precursor and deposition time is 18 minutes; curve406is a plot of normalized surface composition of on the SiCN surface using monosilane as precursor and deposition time is 34 minutes. As shown in curve402, using disilane as precursor, a silicon seed layer, represented by the peak at energy level Si0, is formed. In comparison, there is no peak at the energy level Si0along the curves404and406, which indicates that when using monosilane as precursor, a silicon seed layer would not form on the SiCN surface even if the deposition time is nearly doubled.FIGS.4E and4Fare enlarged plots showing the curves404and406showing the concentration of Si0.

In some embodiments, the seed layer124may be a continuous silicon layer having a thickness in a range between about 3 Å and about 20 Å. As a result of the seed layer124, the width of trenches between semiconductor fins, i.e. the trenches110a,110b, is reduced from the width W1to the width W3, and the width of trenches between a semiconductor fin and a dielectric fin, i.e. the trenches112a,112b, is reduced from the width W2to the width W4. The reduction from the width W1to the width W3is greater than the reduction from the width W2to the width W4.

FIG.4Gis an example device showing a cross sectional view of fin structures with a selectively formed silicon seed layer according to embodiments of the present disclosure. The silicon seed layer124is formed on sidewalls of the semiconductor fin structures104a,104b. As shown in regions408,410, there is no growth of the silicon seed layer124on the sidewalls120sof the dielectric fin120.

FIG.4Hinclude TEM showing top views of the fin structures before and after forming the seed layer124in the operation208. As shown inFIG.4H, after forming the seed layer124, width of the semiconductor fin structures104increases by two times the thickness of the seed layer124while width of the dielectric fin120does not increase. In some embodiments, the dielectric fin120may reduce during the post deposition etch in operation304and the surface treatment in operation306. As a result, the width of the trenches110a,110bis reduced by about two thicknesses of the seed layer124, the width of the trenches112a,112badjacent the dielectric fin120reduces at the most by one thickness of the seed layer124. Because the dielectric fin120may lose some thickness, the overall width W4after operation208of the trenches112a,112bincrease for about 1 nm from W2. Therefore, comparing uniform seed layer deposition, embodiments of the present disclosure enlarge spaces in the trenches112a,112bbetween the dielectric fin120and the semiconductor fin structures104.

In some embodiment, when the semiconductor fin structures104include Ge, e.g. SiGe, the silicon seed layer deposited according to the present disclosure may improve Ge abruptness performance, therefore, preventing Ge diffusion and avoiding SiGe oxidation. As a result, the silicon seed layer124according to the present disclosure improves interface trap density (Dit) at the germanium containing channels.

FIGS.4I-4Jillustrate normalized germanium abruptness corresponding to the silicon seed layer formed using disilane and monosilane at different temperatures. Particularly,FIGS.4I-4Jinclude Ge abruptness corresponding to silicon seed layers formed using disilane at 380° C., 405° C., 415° C., and using monosilane at 450° C., 470° C., 485° C., 500° C.FIG.4Ishows Ge abruptness at amorphous silicon deposition.FIG.4Jshows Ge abruptness at subsequent anneal. Not meaning to be bound by theory, at low temperatures, there are less germanium segregation while at high temperatures, material intents to complete lattice structure before Ge segregation. As shown inFIGS.4I and4J, silicon seed layer formed using disilane at 405° C. has better Ge abruptness at amorphous silicon deposition and anneal than silicon seed layer formed using disilane at 380° C. Silicon seed layer formed using disilane at 415° C. and silicon seed layer formed using monosilane at 470° C. have comparable Ge abruptness at amorphous silicon deposition, and better Ge abruptness during anneal than silicon seed layer formed using disilane at 380° C.

In operation210, a bottom-up gap deposition is performed to form a silicon layer126over the fin structures104, the dielectric fins120, and in the trenches110,112, as shown inFIGS.5A-5C. In some embodiments, the silicon layer126may be formed by one or more deposition-anneal-etch cycles to achieve bottom-up gap filling in the trenches110,112.FIGS.5A-5Care cross sectional views of the semiconductor device100after the first, second, and final deposition-anneal-etch cycles respectively.

After the formation of the silicon seed layer124, silicon may be grown on the silicon seed layer124using a silicon-containing precursor such as disilane (Si2H6), monosilane (SiH4), or the mixture of disilane and monosilane. The temperature for growing the silicon layer using disilane may be in the range between about 350° C. and about 400° C. The temperature for growing the silicon layer using monosilane may be in the range between about 400° C. and about 500° C. Depending on the temperature, the growth rate of silicon layer126, and other process conditions, silicon layer126may be an amorphous silicon layer or a polysilicon layer. During the deposition step of each deposition-anneal-etch cycle, the silicon layer126may be formed as a conformal layer.

After deposition, an anneal is performed. In some embodiments, the anneal is performed at a temperature in the range between about 450° C. and about 600° C. The anneal may last between about 2 minutes and about 2 hours, depending on the temperature, with a higher temperature corresponding to a shorter anneal time, and a lower temperature corresponding to a longer anneal time. During the anneal, process gases such as nitrogen (N2) or hydrogen (H2) may be introduced. As a result of the anneal, silicon atoms migrate. The migration of the silicon atoms may involve the anneal breaking hydrogen atoms (coming from the precursors) from silicon atoms. The silicon atoms having the dangling bonds tend to migrate to the places with higher surface energies or lower potential, and eventually reduce the total system energy by filling the trenches110,112. The silicon atoms with the dangling bonds are then bonded with other silicon atoms. The migration of silicon atoms from higher places to lower places is similar to the reflow of silicon, although at the anneal temperature, silicon is neither molten nor partially molten. The migration of silicon atoms results in a bottom-up effect, that is, more silicon migrates to the bottom of trenches, which is equivalent to growing silicon in a bottom-up way. And the migration of silicon causes the sidewalls of silicon layer126to be smoothened and necking profile near entrances of the trenches110,112may be reduced or eliminated.

After the anneal process, an etch-back process may be performed on silicon layer126to form an improved trench profile, i.e. more V-shape like, for the subsequent gap-fill process. In some embodiments, the etch-back process may use an etchant gas comprising chlorine (Cl2), for example an etchant including a mixture of chlorine (Cl2) and nitrogen (N2), a mixture of fluorine (F2) and nitrogen (N2), or a mixture of NF3, H2, and helium (He), or HCl. In some embodiments, the etch-back is isotropic etch, for example, without applying bias power in the etching chamber during the etch-back.

As shown inFIGS.5A-5C, each deposition-anneal-etch cycle, profiles of the silicon layer1261,1262,126nmay sequentially become rounded with greater thickness at bottoms of the trenches110,112. The deposition-anneal-etch cycle in operation210when the profile of the silicon layer126nin the trenches110,112are V-shaped and may be filled with a bulk deposition.

It has been observed that during bottom-up deposition the fin structures104may bend due to unbalanced forces on opposing sides of the fin structures104.FIG.5Dis a schematic view of the semiconductor device100with outward bending fin structures104after bottom-up deposition of the silicon layer126. As shown inFIG.5D, the trenches112between the fin structures104and the dielectric fin120are narrower than the trench110between the fin structures104. The silicon layer126fills up the narrower trenches112faster than the wider trenches110. As a result, the fin structures104bend outwards from the trench110and towards the dielectric fins120.

FIG.5Eis a TEM image of a semiconductor device after recess of isolation layer.FIG.5Fis a TEM image of the semiconductor device after formation of the silicon layer126according to embodiments of the present disclosure. As shown inFIGS.5E and5F, the silicon layer126causes the semiconductor fin structures104bend outwards from each other and towards the neighboring dielectric fins120. According to embodiments of the present disclosure, bending of the semiconductor fin structures104may be reduced or controlled by selecting suitable crystalline structure of one or more cap silicon layers above the silicon layer126. For example, depositing an amorphous silicon cap layer on the silicon layer126to reduce outward bending of the fin structures104.

In operation212, a first silicon cap layer128is deposited over the silicon layer126, as shown inFIG.6A.FIG.6Ais a schematic cross-sectional view of the semiconductor device100. The first silicon cap layer128may be formed by a blanket deposition to fill remaining regions in the trenches110,112. In some embodiments, the first silicon cap layer128may have a thickness in a range between about 5 nm and about 20 nm, for example about 10 nm.

In some embodiments, the first silicon cap layer128may be deposited using a silicon-containing precursor such as disilane (Si2H6), monosilane (SiH4), or the mixture of disilane and monosilane. Depending on the temperature and other process conditions, the first silicon cap layer128may be an amorphous silicon layer or a crystalline silicon layer. In some embodiments, the temperature for growing the first silicon cap layer128may be selected to generate desirable crystalline structure.

In some embodiments, the first silicon cap layer128is an amorphous silicon layer to reduce the outward bending of the fin structures104. For example, the first silicon cap layer128may be deposited using monosilane as precursor at a temperature in the range between about 450° C. and about 500° C.

In operation214, a second silicon cap layer130is deposited over the first silicon cap layer128, as shown inFIG.6B.FIG.6Bis a schematic cross-sectional view of the semiconductor device100. The second silicon cap layer130may be formed by a blanket deposition to reach a target thickness for a sacrificial gate electrode to be formed. In some embodiments, the second silicon cap layer130may have a thickness in a range between about 150 nm and about 250 nm, for example about 185 nm. In some embodiments, the second silicon cap layer130may be deposited using a silicon-containing precursor such as disilane (Si2H6), monosilane (SiH4), or the mixture of disilane and monosilane. Depending on the temperature and other process conditions, the second silicon cap layer130may be an amorphous silicon layer or a crystalline silicon layer. In some embodiments, the temperature for growing the second silicon cap layer130may be selected to generate desirable crystalline structure.

In some embodiments, the second silicon cap layer130is a crystalline silicon layer, such as a polycrystalline silicon layer. The crystalline structure in the second silicon cap layer130may interact with the first silicon cap layer128to remove any seams formed with the trenches110and112. In some embodiments, the second silicon cap layer130may be deposited using monosilane as precursor at a temperature greater than 500° C., for example in the range between about 500° C. and about 700° C.

In some embodiments, the first and second silicon cap layers128,130may be deposited in the same processing chamber. For example, upon depositing the first silicon cap layer128to a target thickness, processing conditions are changed, for example increasing the processing temperature to greater than 500° C., to deposit the second silicon cap layer130.

As shown inFIG.6B, the first and silicon cap layers128,130according to the present disclosure have different crystalline structures. The different crystalline structure arrangement in the cap layers enables a void free sacrificial gate electrode layer deposition in high aspect ratio trenches.

FIG.6Cincludes a cartoon illustration of gap filling results using cap layers of different crystalline structures. InFIG.6C, graphs (a) and (b) schematically illustrate a bottom-up deposition in a trench between two semiconductor fins. The bottom-up filling may be performed using operation210according to the present disclosure. The bottom-up deposition results in an amorphous silicon in the trench, as shown in graph (b). Graph (c) demonstrates that a seam is formed in the trench if a silicon cap layer with amorphous silicon is deposited after the bottom-up deposition in graph (b). Graph (d) demonstrates that a void is formed in the trench if a silicon cap layer with crystalline silicon is deposited after the bottom-up deposition in graph (b). The void may be caused by the outward fin bending effect of the crystalline silicon layer. Graphs (e) and (f) demonstrate that void free and seam free silicon is formed in the trench when a hetero-crystalline cap layer is deposited after the bottom-up deposition in graph (b). Particularly, a cap layer including an amorphous sublayer and a crystalline sublayer may be deposited to improve gap filling.

In operation216, sacrificial gate structures138are formed as shown inFIGS.7A and7B.FIG.7Ais a cross sectional view of the semiconductor device100along the line A-A inFIG.7B.FIG.7Bis a cross sectional view of the semiconductor device100along the line B-B inFIG.7A.

The seed layer124, silicon layer126, first silicon cap layer128, and second silicon cap layer130may be collectively referred to as sacrificial gate electrode layer132. In some embodiments, after deposition of the second silicon cap layer130, a planarization process, such as by a CMP process, is performed resulting in the sacrificial gate electrode layer132as shown inFIG.7A. In some embodiments, a pad layer134, and a mask layer136are sequentially deposited over the sacrificial gate electrode layer132. The pad layer134may include silicon nitride. The mask layer136may include silicon oxide. A patterning operation is performed on the mask layer136, the pad layer134, the sacrificial gate electrode layer132, and the sacrificial gate dielectric layer122to form the sacrificial gate structures138using one or more etching processes, such as one or more plasma etching processes or one or more wet etching processes. In some embodiments, the mask layer136and pad layer134are first patterned using a patterning process. The sacrificial gate electrode layer132is then patterned using the patterned mask layer136and pad layer134as an etching mask. In some embodiments, the sacrificial gate electrode layer132may be etched by an anisotropic etching, such as a reactive ion etching (RIE) process. The anisotropic etching has a greater etching rate along the Z direction than etching rates along the X and Y directions. During the etching of the sacrificial gate electrode layer132, the sacrificial gate dielectric layer122on the fin structures104may act as an etch stop to prevent the etchant from removing the fin structures104. The sacrificial gate structure138covers portions of the fin structures104. The portions of the fin structures104covered by the sacrificial gate structures138eventually form channel regions for FinFET to be formed.

In operation218, sidewall spacers140are formed on the sacrificial gate structure138, as shown inFIG.8.FIG.8is a schematic cross-sectional view of the semiconductor device100along the line A-A ofFIG.7B.

The sidewall spacers140may be formed by depositing one or more dielectric layers by ALD or CVD, or any other suitable method. The dielectric layers may include suitable dielectric material, such as silicon oxide, silicon oxynitride, or combinations thereof. The dielectric layers may be formed by blanket deposition sequentially. In some embodiments, an anisotropic etching may be performed to remove the dielectric layers from horizontal surfaces, such that the sidewall spacers140are positioned on sidewalls of the sacrificial gate structures138.

In operation220, the fin structures104in source/drain region, or regions not covered by the sacrificial gate structures138and sidewall spacers140, are recess etched, as shown inFIG.8. In some embodiments, suitable dry etching and/or wet etching may be used to remove the semiconductor material in the fin structures104. In some embodiments, the fin structures104a,104bare recessed to a level below the isolation layer114. As shown inFIG.8, source/drain recesses142are formed on both sides of the sacrificial gate structures138.

In operation222, epitaxial source/drain regions144are formed in the source/drain recesses142, as shown inFIG.9.FIG.9is a schematic cross-sectional view of the semiconductor device100along the line A-A ofFIG.7B. The epitaxial source/drain regions144may be formed by any suitable method, such as by CVD, CVD epitaxy, molecular beam epitaxy (MBE), or any suitable deposition technique. The epitaxial source/drain regions144may include one or more layers of Si, SiP, SiC and SiCP for n-type device or Si, SiGe, Ge for p-type devices. For n-type devices, the epitaxial source/drain regions144also include n-type dopants, such as phosphorus (P), arsenic (As), etc. For p-type devices, the epitaxial source/drain regions144include p-type dopants, such as boron (B).

The epitaxial source/drain regions144may be grown in an epitaxial chamber by a suitable process. For example, the epitaxial source/drain regions144are formed by a selective etching growth process, in which a thin film is deposited by introducing a reactant gas including deposition agent and etchant together. In some embodiments, an optional etching process may be performed to achieve desired shape and/or thickness of the epitaxial layer being formed.

At operation224, a contact etch stop layer (CESL)146and an interlayer dielectric (ILD) layer148are formed over the semiconductor device100, as shown inFIG.10.FIG.10is a schematic cross-sectional view of the semiconductor device100along the line A-A ofFIG.7B. The CESL146is conformally formed over exposed surfaces of the semiconductor device100. The CESL146is formed on the epitaxial source/drain regions144, the sidewall spacers140, and the isolation layer114if exposed. The CESL146may include SiN, SiON, SiCN or any other suitable material, and may be formed by CVD, PVD, or ALD.

The interlayer dielectric (ILD) layer148is formed over the CESL146. The materials for the ILD layer148include compounds comprising Si, O, C, and/or H, such as silicon oxide, SiCOH and SiOC. Organic materials, such as polymers, may be used for the ILD layer148. In some embodiments, the ILD layer148may be formed by flowable CVD (FCVD). The ILD layer148protects the epitaxial source/drain regions144during the removal of the sacrificial gate structures138.

At operation226, replacement gate structures150are formed, as shown inFIGS.11A and11B.FIG.11Ais a cross sectional view of the semiconductor device100along the line A-A inFIG.11B.FIG.11Bis a cross sectional view of the semiconductor device100along the line B-B inFIG.11A. The sacrificial gate dielectric layer122and sacrificial gate electrode layer132are removed by one or more suitable process, such as dry etch, wet etch, or a combination thereof, to expose the fin structures104. In some embodiments, a wet etchant such as a tetramethylammonium hydroxide (TMAH) solution is used. The replacement gate structure150may include a gate dielectric layer152, and a gate electrode layer154. Optionally, the replacement gate structure may include a self-aligned contact (SAC) layer156.

The gate dielectric layer152may be conformally deposited on exposed surfaces in the gate cavities. The gate dielectric layer152may have different composition and dimensions for N-type devices and P-type devices and are formed separately using patterned mask layers and different deposition recipes. The gate dielectric layer152may include one or more layers of a dielectric material, such as silicon oxide, silicon nitride, or high-k dielectric material, other suitable dielectric material, and/or combinations thereof. Examples of high-k dielectric material include HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, zirconium oxide, aluminum oxide, titanium oxide, hafnium dioxide-alumina (HfO2—Al2O3) alloy, other suitable high-k dielectric materials, and/or combinations thereof. The gate dielectric layer152may be formed by CVD, ALD or any suitable method.

The gate electrode layer154is then formed on the gate dielectric layer152to fill the gate cavities. The gate electrode layer154may include one or more layers of conductive material, such as polysilicon, aluminum, copper, titanium, tantalum, tungsten, cobalt, molybdenum, tantalum nitride, nickel silicide, cobalt silicide, TiN, WN, TiAl, TiAlN, TaCN, TaC, TaSiN, metal alloys, other suitable materials, and/or combinations thereof. In some embodiments, the gate electrode layer154may be formed by CVD, ALD, electro-plating, or other suitable method. After the formation of the gate electrode layer154, a planarization process, such as a CMP process, is performed to remove excess deposition of the gate electrode material and expose the top surface of the ILD layer148.

In some embodiments, a metal gate etching back (MGEB) process is performed to form the self-aligned contact (SAC) layer156. One or more etching processes are performed to remove portions of the gate dielectric layer152and the gate electrode layer154to form trenches in the region above the remaining gate electrode layer154. The MGEB process may be a plasma etching process employing one or more etchants such as chlorine-containing gas, a bromine-containing gas, and/or a fluorine-containing gas. The etching process allows the gate dielectric layer152and the gate electrode layer154to be selectively etched from the ILD layer148and the CESL146.

After filling the trenches with the SAC layer156, a planarization process, such as a CMP process, is performed to remove excess deposition of the SAC layer156to expose the top surface of the ILD layer148. Source/drain contact features158and gate contact features160are formed as shown inFIGS.11A and11B.

Referring toFIG.11A, profiles of the fin structures104in the replacement gate structure150may reflect the profiles shown inFIG.5F. For example, the fin structures104may bend outward from each other and toward the neighboring dielectric fin120.

Various embodiments or examples described herein offer multiple advantages over the state-of-art technology. Embodiments of the present disclosure provide a method for selectively forming a seed layer over semiconductor fins, therefore, reducing aspect ratio increase and improving gap-fill quality. By forming the selective seed layer using a mono-silane at an increased temperature, embodiments of the present disclosure also improves abruptness of germanium, preventing germanium in the channel region from diffusion and oxidation, and eventually improve trap density in the channel region. By depositing a hetero-crystalline silicon cap layer over the bottom-up gap layer during formation of sacrificial gate electrode, embodiments of the present disclosure further improve gap filling. The hetero-crystalline silicon cap layer may also tune profiles of the semiconductor fin structures.

Some embodiments of the present disclosure relate to a method for manufacturing a semiconductor device, comprising: forming a first semiconductor fin structure and a second semiconductor fin structure; forming a dielectric fin structure between the first and second semiconductor fin structures; selectively forming a seed layer on the first and second semiconductor fin structures, wherein sidewalls of the dielectric fin structure remain exposed after formation of the seed layer; depositing a sacrificial gate electrode layer over the seed layer and the dielectric fin structure; forming a sacrificial gate structure from the sacrificial gate electrode layer; forming sidewall spacers on the sacrificial gate structure; etching the first and second semiconductor fin structures; forming epitaxial source/drain regions; removing the sacrificial gate structure; and forming a replacement gate structure between the sidewall spacers.

Some embodiments of the present disclosure relate to a method for manufacturing a semiconductor device, comprising: forming a first semiconductor fin structure and a second semiconductor fin structures, wherein a first trench is formed between the first and second semiconductor fin structure; forming a first silicon layer over the first and second semiconductor fin structures, wherein the first silicon layer is disposed in the first trench in a bottom-up manner; depositing a first cap layer over the first silicon layer; depositing a second cap layer over the first cap layer, wherein the first and second cap layers have different crystalline structures; etching the first silicon layer, the first cap layer, and the second cap layer to form a sacrificial gate structure; forming sidewall spacers on the sacrificial gate structure; etching the first and second semiconductor fin structures; forming epitaxial source/drain regions; removing the sacrificial gate structure; and forming a replacement gate structure between the sidewall spacers.

Some embodiments of the present disclosure relate to a method for manufacturing a semiconductor device, comprising: forming two first fin structures, wherein a first trench is formed between the two first fin structures; forming two second fin structures, wherein a second trench is formed between the two first fin structures; forming a dielectric fin structure, wherein the dielectric fin structure is disposed between the first fin structures and the second fin structures, a third trench is formed between the dielectric fin structure and the first fin structure, and the third trench is narrower than the first and second trenches; selectively forming a seed layer on the first and second fin structures, wherein sidewalls of the dielectric fin structure remain exposed after formation of the seed layer; and forming a gap-fill silicon layer in the first, second, and third trenches.