Method and apparatus for realistic current and power calculation using simulation with realistic test vectors

An innovative method and system for calculating realistic current and power of a circuit prior to silicon utilizes simulation and test vectors to determine a number of variables to accurately perform current calculations close to actual silicon results. Input test vectors which preferably are similar in function to applications utilized with the circuit are used to drive a model of the circuit. The simulator operating the model maintains the toggle count for each device of the circuit. A characterization table is generated which contains an average switching current value of a type of a device for different values of capacitive loads. Typically, this table is generated once and is used for a multiplicity of calculations. An activity factor can then be generated based on the number of the toggle count during a sample time period and the number of clock cycles during the sample period. Using the activity factor, the current is determined from the average switching current for the device times the activity factor. The current can then be used to perform such calculations as power consumption and electromigration testing.

BACKGROUND OF THE INVENTION 
1. Field of the Invention 
The present invention relates to the determination of current and power 
consumption by circuit. More particularly, the present invention relates 
to a method for realistic current and power analysis. 
2. Art Background 
Although current and power consumption analysis of a circuit has been 
performed in the past, only recently, with the increasing focus on circuit 
design for portable computing devices, has the need for accurate 
calculation of current and power consumption early in the design process 
of the circuit become increasingly important. In addition, greater chip 
densities, more stringent design rules and higher operating frequencies 
call for stricter, more realistic power analysis and power bus design 
early in the design cycle, prior to fabrication on silicon. 
Evaluation of power and power saving features can be performed once the 
circuit has been fabricated, i.e., after first silicon. This has obvious 
drawbacks such as redesigning the circuit late in the design cycle and 
hence, increasing the period of time from initial design to market. 
Moreover, even after first silicon, only the total current/power consumed 
by the chip as a whole can be obtained. The estimation of current/power 
consumed by each module/unit inside the chip during various debugging 
phases is still very difficult to obtain and typically inaccurate. 
In the past, device counts of a circuit were used to estimate power. The 
number of each type of device and the typical power/current consumption by 
a device type were then used to generate a rough estimate of the current 
and power consumed. 
SUMMARY OF THE INVENTION 
It is therefore an object of the present invention to provide a method and 
apparatus for realistic power and current analysis. 
It is further an object of the present invention to provide a system which 
uses the simulation of circuits to provide realistic current and power 
analysis on a device and circuit level. 
In the system and method of the present invention, an actual toggle count, 
that is, the number of transitions from a low state to a high state and/or 
from a high state to a low state, is determined for each node in the 
circuit during simulation of the circuit. Using input vectors 
representative of applications to be applied to the circuit, a toggle 
count for a sample period can be generated which provides an accurate 
representation of the activity of each node in the circuit. The toggle 
count is divided by the total number of dock cycles during the simulation 
sample period to provide a more precise and accurate activity factor. In 
addition, for each node, the driver which drives the signal at that node 
is determined. Once the driver is identified, the strength or size of the 
driver, in terms of the capacitive load it drives, is determined. 
Prior to simulation of the circuit, it is preferred that an average current 
for each device is determined for various devices in the circuit at 
various capacitive loads. Using a table generated therefrom as a 
reference, the current at the device is determined based on the capacitive 
load it drives and type of device. Therefore, a more accurate current 
measurement at each node (i) is determined according to the following 
equation: 
EQU Current (i)=Iavg(i).multidot.A(i) 
where Iavg(i) represents the average current provided by the driver and 
A(i) represents the activity factor for the device which is equal to 
toggle(count)/total number of clock cycles. 
Power can therefore be obtained as a product of the current multiplied by 
the operating voltage of the circuit. Furthermore, the total current of 
the circuit can be determined as: 
##EQU1## 
where n is the total number of nodes of the circuit. 
Using this new methodology, realistic current and power calculations are 
provided. Other calculations such as electromigration, average current 
analysis and pre-silicon power estimations can be performed using this 
system. This capability enables designers and manufacturers to achieve the 
desired power and current consumption requirements during the early stages 
of the design process thereby enabling the product to get more quickly to 
market. Furthermore, the method described herein is readily applied to 
automation and requires little user input unlike prior methods which 
require input regarding device types and activity factors.

DETAILED DESCRIPTION OF THE INVENTION 
In the following description, for purposes of explanation, numerous details 
are set forth in order to provide a thorough understanding of the present 
invention. However, it will be apparent to one skilled in the art that 
these specific details are not required in order to practice the present 
invention. In other instances, well-known electrical structures and 
circuits are shown in block diagram form in order not to obscure the 
present invention unnecessarily. 
A general flow diagram for the method for determining current and power is 
illustrated in FIG. 1. At step 10, a characterization table of average 
current values (I.sub.cell table) is determined for the circuit. This 
table can be generated once for a particular circuit or family of circuits 
and used as a reference over and over for multiple calculations. 
Preferably, using an accurate circuit simulator, a table of average 
current values for each type cell or type of device and capacitive load of 
the cell or device is generated. Preferably, these calculations are 
performed at a given frequency, voltage and temperature. More 
particularly, the table contains average current values for standard cells 
and special circuit cells that are contained in the circuit to be tested. 
A cell may be defined to include one or more devices. The current 
consumption values are generated for different sizes or strengths of each 
device and for different values of capacitive loading of the inputs. For 
example, for a particular device, the aver age current value is determined 
for capacitive values of 20%, 40%, 50%, 80% and a 100% of the maximum 
capacitive load of the cell. This table can be generated based on 
information output by a circuit simulators, such as a simulator using 
tools which allow a user to set and control simulation parameters in the 
specified circuit simulation and analyze the results of the simulation. An 
example of such a simulator is HSPICE, manufactured by Cadence, Inc. 
Preferably, the average current of a cell, I.sub.avg (cell), is determined 
during circuit simulation. In addition, it is preferred that the average 
current determined includes both the switching current and the charging 
and discharging of the capacitances of the load of the cell. In contrast, 
prior art methods consider only the charging and discharging of 
capacitance and do not take into account the switching current. The 
switching current is generated by the current conducting directly from VCC 
to VSS when the input swings between logic states. In many situations, 
this current may contribute significantly to the total current. The new 
device current calculation and the difference between the new method and a 
prior art method is shown below: 
##EQU2## 
where C is the maximum capacitance of the device, V is the voltage in the 
circuit, T is the amount of the time of the sample, and I(t) is the 
switching current needed to switch the state of the device. 
To determine the activity factor, logic simulation of the circuit is used 
to generate a toggle count at each node in the circuit. That is, each time 
a node changes state, the toggle count for that node is incremented. To 
operate the logic simulator, test vectors are used as input. Preferably, 
the test vectors are selected with the end application in mind in order to 
provide an accurate toggle count and an indication of the activity of a 
node for that application. The toggle count is used along with the vector 
clock information to derive the activity factors. Preferably, a logic 
simulator engine is used, such as XPLUS.TM., a comprehensive package of 
software tools that run logic and fault circuit simulations on the XP line 
of simulation accelerators and is manufactured by Zycad Corporation. 
At step 30, the driver or drivers for each node are determined. Preferably, 
the drivers are determined from the circuit model, for example, a circuit 
modeled in the EDIF2 format, a hierarchical net list description language 
(EDIF2 is the Electronic Design Interchange Format version 2.0.0, 
Recommend Standard EIA-548, available from the Electronic Industries 
Association, Engineering Department, 2001 Pennsylvania Avenue, N.W. 
Washington, D.C. 20006). An EDIF2 circuit model can be generated using a 
software tool or package with circuit modeling/simulation capability that 
supports the EDIF2 net list description language. An example of such a 
tool is the XPLUS.TM. software, available from System Science, Inc. 
Therefore using the hierarchical net list of the circuit model, the driver 
or drivers of each node are determined. 
At step 40, the loading at each node is then determined. As is known in the 
art, the loading of a node is determined by such factors as the fan out of 
signals from the node and the placement and routing of the signals. The 
capacitive loading on a node can be traced using a variety of methods or 
tools which can identify the capacitive loading at a node identified by a 
node name. The loading can be selected to be pre-layout or post-layout 
capacitances. At step 50, based upon the type of driver device and 
preferable size or strength of the driver device and the capacitive 
loading on the node, a lookup is performed in the characterization table 
(I.sub.cell table). This provides an average current value for each 
driving device for a particular mode. At step 60, the total average 
current for the circuit or a unit of the circuit can be determined using 
the following equation: 
##EQU3## 
where Iavg(cell(i)) represents the average current for the device, 
toggle(i) represents toggle count for the node driven by the device, and 
Total Clock Count represents the clock count for the sample period 
utilized. 
It should be realized that a node may be driven by more than one device. A 
bus is a common example. A number of different alternatives may be used to 
provide accurate current and power for a node driven by multiple devices. 
For example, an average value of the current values determined with 
respect to each driver for particular node can be utilized in the 
calculation. Alternately, another approach would be to consider the worst 
case driver of the drivers identified for a particular node and use the 
worst case calculation as the current value for the node. 
Sometimes, the load values for a particular device are not found when a 
lookup is performed in the characterization table. If an exact match for 
the load is not found, a linear approximation or similar approximating 
process may be performed to obtain the average current value of a cell 
from the load values and corresponding current values found in the table. 
Preferably, the characterization table has values not only for standard 
cells but for special circuits that are found in the subject circuit being 
tested. This provides flexibility and more accurate current analysis. 
However, any cell, standard or non-standard described in a model, is built 
using a standard set of primitives (devices) and can be quantified 
according to the primitives. Also, the cell and the primitives which 
compose a cell have associated strengths (i.e., a maximum capacitive load 
a cell or primitive can drive) for modeling purposes. Using the 
information regarding the primitives which build a non-standard cell and 
their associated strengths, a mapping of the non-standard cell to the an 
equivalent standard cell can be performed. Once mapped, the current for a 
non-standard cell can be obtained from its equivalent standard cell value 
in the table. Although it is preferred that each special circuit have its 
own entry in the characterization table, a mapping of the primitives which 
compose the special circuit can alternatively be used. 
A simplified block diagram of system of the present invention is 
illustrated in FIG. 2. The circuit to be analyzed 105 is provided as input 
to the characterizer 110 which generates as its output the 
characterization (I.sub.cell) table 115. Preferably, the characterizer 
that is used is found in a circuit simulation tool, such as HSPICE, 
provided by Cadence, Inc. The logic simulator engine 120 operates a model 
of the circuit 105 using test vectors as input to determine the toggle 
count 130. Preferably, the engine is a simulator engine such as the XP 
series of accelerators, manufactured by Zycad Corporation and running the 
XPLUS.TM. logic software tools provided by System Sciences, Inc. 
The driver identifier 135, determines from the net list of the circuit 105, 
the driver device or devices 140 which drive each node. Using the driver 
device(s) identified for each node, a circuit simulator 145, for example, 
HSPICE, is operated to determine the capacitive loading contribution at 
each node by each driver 147. The I.sub.cell table 115, toggle count 130 
and device driver loading for each node 140 are input to a device such as 
a processor 150 which performs the computations necessary to determine the 
total current and power consumption for the circuit 105. 
FIG. 3 is a block diagram, which illustrates the process steps and the 
input and output data used to determine the current for the circuit from 
which such things as power bus analysis, power saving features analysis 
and other circuit analysis, can be performed. In particular, the 
characterization process 200, receives as input cell definitions and 
capacitive loads for which average current values of the characterization 
table are determined. The cell definitions include standard circuit cells 
(Std Cell) as well as special circuit cells (Special Circuits) defined by 
the user. The maximum capacitive load for a device (Cmax) as well as the 
capacitive load values to utilize (Cload) are also input. The output of 
the process is the characterization table (I.sub.cell table) which 
identifies average current values for each cell at different capacitance 
loads. 
The engine model building and simulation process 210 receives as input the 
files which define the circuit schematic and input test vectors. A net 
list file is derived from the circuit schematic, such as a net list file 
in EDIF2 format. Using logic simulation of the circuit and test vectors, a 
simulation of the circuit is operated and a toggle count for each node is 
generated. 
During the current estimation process 220, the drivers for each node are 
identified from the net list file and the capacitive loading at the nodes 
due to the identified drivers is determined from the circuit schematic 
input. The toggle count and characterization table are also input to 
generate the current and power information for the circuit. 
The advantages of the system and method of the present invention can be 
realized by reference to the simplified example of FIG. 4a, which includes 
inputs A and B and an output C in which A and B are input to the NAND 
gate, and C is the output of the NAND gate which is input to a Latch 
triggered by clock input signal. FIG. 4b illustrates a sample input on 
nodes A and B, and the operation of the circuit of FIG. 4a. FIG. 4c is a 
table which illustrates the activity factor calculated for the Latch 
output ("OUT") and the NAND gate ("C"). Using prior techniques, the NAND 
gate is estimated to have an activity factor of 0.5 and the Latch is 
estimated to have an activity factor of 0.25. Using the techniques 
described herein, the activity factor from the gate is determined to be 
0.25 as only one toggle occurred during the 4-clock cycles of the sample 
period. Similarly, the Latch is determined to have an activity factor of 
0.25. FIG. 4d shows the activity factors calculated for the second sample 
period shown in FIG. 4b. In this situation using prior techniques, the 
output of the gate activity factor is again generally estimated to be 0.5 
and the output of the Latch is estimated to have an activity factor of 
0.25. In this sample period, two toggles occurred during 2-clock cycles. 
Therefore, the actual activity factor using the techniques described 
herein for both the node of the output of the gate and the output of Latch 
is 1.0, a significant difference from the activity factors of 0.5 and 0.25 
estimated using prior methods. Thus, it can be seen that simple estimation 
does not work consistently and overestimation and underestimation of 
current can easily result. 
Realistic input or test vectors suites play an important role in the 
accuracy of the results. Preferably, the vectors should be representative 
of the type of processes of the application program that the circuit is to 
be used with. To calculate the average current of the model of the 
circuit, the vector should be close in function to the user application to 
be utilized with the circuit. In other cases such as for testing power 
saving features, for performing electromigration design, etc., the need 
may be different. The number of NOPs, the number of loops and the way they 
are modeled are also factors which need attention. The number of NOPs, the 
number of loops and the way they are modeled, are preferences of the 
writer of the vectors utilized. A statistical study of operations 
performed can eliminate the bias or preference of a single writer and 
provide a fair vector input. It is preferred that an accurate vector come 
from statistical studies of the real applications. The vectors can be 
developed or converted from several bench mark programs, or else an 
interface to run the user applications directly on the model can be used. 
Preferably, the vector should not be too large to effect the verification 
time and not too small to effect the sample size. FIG. 5 shows exemplary 
vectors that were developed based on the X86 instruction mix analysis of 
assembly instructions frequently used in typical applications round out 
the X86 line of microprocessors manufactured by Intel Corporation, Santa 
Clara, Calif. This instruction mix was determined to have the same 
percentage of instruction mix as the application program typically used 
with the circuit to be tested. 
FIG. 6a is a simplified portion of a processor, specifically, the adder 
circuit from the segmentation unit of the i486 core. In the present 
example, the simulation conditions for the characterization to be used 
were 3.6 V operating voltage, 33 Mhz frequency, RF process, 120.degree. 
C., 1.5 ns input transition and 2 transitions (high and low) per device. 
The inverter A drives a load of 0.0894 pF. Based on values from the table, 
the inverter A consumes 12 .mu.A for every toggle. Running vector diag4, 
the toggle count of inverter A is found to be 4,217. The clock count of 
the vector is 10,638 producing an activity factor of 4217/10638=0.39. 
Thus, the average current drawn by inverter A is 0.39*12=4.68 .mu.A. As a 
comparison, using the prior method of assigning activity factors, the 
activity factors assigned to the inverter A would be 0.5 and the average 
current drawn by the device would be 1/2*12=6 .mu.A. 
FIG. 6b shows a data comparison of current consumed by devices A, B and C 
determined by the new method and a prior art method. By referencing to 
FIG. 6b, it can be seen that the new method can generate significantly 
different results compared to a prior art method, particularly for device 
C. In subsequent tests on the segmentation unit of the i486 core using the 
vectors shown in FIG. 5, the total average current estimated is 52.25 
.mu.A. Using prior techniques, the estimated current is 180 .mu.A. This is 
3.5 times over that of current estimated using the method of the present 
invention. 
The current consumed by the floating point unit of the i486 core as 
estimated by the method of the present invention was compared against the 
results determined by testing silicon. This was performed by running the 
same vectors utilized during physical testing of the device. The silicon 
current was determined by calculating the difference in current with the 
floating point unit enabled and disabled. After scaling for the 
differences in simulation conditions (i.e., temperature, process skew, 
etc.), between the tester and the configuration table, the results, shown 
in FIG. 7, were determined. The results determined using the method of the 
present invention, came within 15% of the silicon results. The results 
determined using prior techniques show an overestimation by a factor of at 
lest 6.8 times the silicon current determined. 
Although the invention has been described in conjunction with the preferred 
embodiment, it is evident that numerous alternatives, modifications, 
variations and uses will be apparent to those skilled in the art in light 
of the foregoing description.