Electrostatic discharge protection device capable of adjusting holding voltage

An electrostatic discharge protection device includes: a substrate of a second conductivity type, the substrate including a well of a first conductivity type; a cathode electrode connected to the substrate; a first diffusion region of the second conductivity type and a second diffusion region of the first conductivity type, formed in the substrate and connected to the cathode electrode; an anode electrode connected to the substrate; a third diffusion region of the second conductivity type and a fourth diffusion region of the first conductivity type, formed in the well and connected to the anode electrode; a fifth diffusion region of the first conductivity type, formed on a border of the substrate and the well; and a sixth diffusion region of the first conductivity type, formed in the substrate between the first and second diffusion regions and the fifth diffusion region and configured to receive a bias voltage from outside.

CROSS-REFERENCE TO RELATED APPLICATIONS

This U.S. non-provisional patent application claims priority under 35 U.S.C. § 119 to Korean Patent Application No. 10-2015-0179368, filed on Dec. 15, 2015, the entire contents of which are hereby incorporated by reference.

BACKGROUND

The exemplary embodiments disclosed herein relate to electrostatic discharge protection devices, and more particularly, to an electrostatic discharge protection device capable of adjusting a holding voltage.

2. Description of Related Art

A SCR (silicon controlled rectifier)-based electrostatic discharge protection device is a high efficiency device using a latch-up. However, the SCR-based electrostatic discharge protection device may become latched up while power is supplied thereto and thereby an incorrect operation may occur. A device may be damaged irreparably due to such an incorrect operation.

To prevent the SCR-based electrostatic discharge protection device from becoming latched up, one technique is to increase a holding voltage of the SCR-based electrostatic discharge protection device. Even though there has been a significant amount of effort to develop this technique of increasing a holding voltage to prevent a latch-up, there is a problem that this technique may cause an increase of a size of the SCR-based electrostatic discharge protection device or may adversely affect a deterioration characteristic of the SCR-based electrostatic discharge protection device.

SUMMARY

Exemplary embodiments disclosed herein provide an electrostatic discharge protection device.

According to an aspect of an exemplary embodiment, there is provided an electrostatic discharge protection device including: a substrate of a second conductivity type, the substrate including a well of a first conductivity type; a cathode electrode connected to the substrate; a first diffusion region of the second conductivity type and a second diffusion region of the first conductivity type, the first diffusion region and the second diffusion region being formed in the substrate and connected to the cathode electrode; an anode electrode connected to the substrate; a third diffusion region of the second conductivity type and a fourth diffusion region of the first conductivity type, the third diffusion region and the fourth diffusion region being formed in the well and connected to the anode electrode; a fifth diffusion region of the first conductivity type, the fifth diffusion region being formed on a border of the substrate and the well; and a sixth diffusion region of the first conductivity type, the sixth diffusion region being formed in the substrate between the first and second diffusion regions and the fifth diffusion region and configured to receive a bias voltage from outside.

According to an aspect of another exemplary embodiment, there is provided an electrostatic discharge protection device including: a substrate of a second conductivity type in which a first well of a first conductivity type is formed, wherein a second well of a second conductivity is formed in the first well; a cathode electrode connected to the substrate; a first diffusion region of a second conductivity type and a second diffusion region of a first conductivity type, the first diffusion region and the second diffusion region being formed in the second well and connected to the cathode electrode; an anode electrode connected to the substrate; a third diffusion region of the second conductivity type and a fourth diffusion region of the first conductivity type, the third diffusion region and the fourth diffusion region being formed in the first well and connected to the anode electrode; a fifth diffusion region formed on a border of the first well and the second well; a sixth diffusion region of the first conductivity type, the sixth diffusion region being formed in the second well between the second diffusion region and the fifth diffusion region and configured to receive a bias voltage from outside; a first gate electrode formed on a first region between the second diffusion region and the sixth diffusion region; a second gate electrode formed on a second region between the fifth diffusion region and the sixth diffusion region; a resistor connected to the cathode electrode; and a capacitor connected to the anode electrode, wherein the first gate electrode is connected to the cathode electrode through the resistor, the second gate electrode is connected to the anode electrode through the capacitor, and the first gate electrode and the second gate electrode are connected to each other.

According to an aspect of another exemplary embodiment, there is provided an electrical device including: a substrate including a well; a cathode electrode and an anode electrode forming a current path therebetween; a first diffusion region formed in the substrate and connected to the cathode electrode; a second diffusion region formed on a border of the substrate and the well; and a third diffusion region formed between the first diffusion region and the second diffusion region, wherein the third diffusion region is configured to adjust a length of the current path.

DETAILED DESCRIPTION

It will be understood that, although the terms first, second, etc., may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first region/layer could be termed a second region/layer, and, similarly, a second region/layer could be termed a first region/layer without departing from the teachings of the disclosure.

FIG. 1is a top plan view illustrating an electrostatic discharge protection device100in accordance with an exemplary embodiment.FIG. 2is a cross sectional view taken along the line I-I′ of the electrostatic discharge protection device100illustrated inFIG. 1.

Referring toFIGS. 1 and 2, the electrostatic discharge protection device100includes a P type substrate110, an N well120formed in the P type substrate110, a first diffusion region131and a second diffusion region132that are formed in the substrate110, a third diffusion region133and a fourth diffusion region134that are formed in the N well120, a fifth diffusion region135formed on the border of the substrate110and the N well120, and a sixth diffusion region136formed between the second diffusion region132and the fifth diffusion region135. The first to sixth diffusion regions131˜136may be formed to extend in a first direction D1along a second direction D2.

The electrostatic discharge protection device100may include a first gate electrode G1formed on a first region R1between the second diffusion region132and the sixth diffusion region136. The first diffusion region131and the second diffusion region132may be formed to be adjacent to each other. The third diffusion region133and the fourth diffusion region134may be formed to be adjacent to each other. The first gate electrode G1and the second gate electrode G2may be formed to extend in the first direction D1along the second direction D2.

The N well120may be doped with low concentration N type impurities. The first diffusion region131and the third diffusion region133may be P type conductivity type regions. The second diffusion region132, the fourth diffusion region134, the fifth diffusion region135and the sixth diffusion region136may be N type conductivity type regions. For example, the second diffusion region132, the fourth diffusion region134, the fifth diffusion region135and the sixth diffusion region136may be regions doped with higher concentration N type impurities than the N well120.

The electrostatic discharge protection device100may include a second gate electrode G2formed on a second region R2between the fifth diffusion region135and the sixth diffusion region136. The electrostatic discharge protection device100may further include a first insulating layer provided between the first region R1and the first gate electrode G1, and a second insulating layer provided between the second region R2and the second gate electrode G2. A channel of a first NMOS transistor generated by the first gate electrode G1, the second diffusion region132and the sixth diffusion region136may be formed in the first region R1. A channel of a second NMOS transistor generated by the second gate electrode G2, the fifth diffusion region135and the sixth diffusion region136may be formed in the second region R2. The electrostatic discharge protection device100may further include a device isolation layer STI, which may be formed using a shallow-trench isolation technology, provided between the third diffusion region133and the fifth diffusion region135.

A bias voltage Vbias may be supplied to the sixth diffusion region136. For example, the bias voltage Vbias may be provided to the sixth diffusion region136through a conductive line141. The first diffusion region131and the second diffusion region132may be connected to a cathode electrode. For example, a ground voltage may be provided through the cathode electrode. The third diffusion region133and the fourth diffusion region134may be connected to an anode electrode. For example, an electrostatic discharge (ESD) current may be input through the anode electrode. The ESD current may be a current (e.g., a surge current) that significantly changes during a short period of time. The first diffusion region131, the second diffusion region132and the first gate electrode G1may be connected to one another through a first resistor R1. The third diffusion region133, the fourth diffusion region134and the second gate electrode G2may be connected to one another through a capacitor C. The first gate electrode G1and the second gate electrode G2may be connected to each other.

To connect the above-mentioned elements to one another, a conductive line that connects the first diffusion region131and the second diffusion region132to the cathode electrode, a conductive line that connects the third diffusion region133and the fourth diffusion region134to the anode electrode, and a conductive line that connects the first gate electrode G1to the second gate electrode G2may be further provided.

According to exemplary embodiments, to adjust a holding voltage of the electrostatic discharge protection device100, a sixth diffusion region136for receiving a bias voltage Vbias from the outside may be provided. When an ESD current is input through the anode electrode, the bias voltage Vbias is applied to the sixth diffusion region136to increase a level (e.g., voltage level) of the holding voltage, thereby improving performance of the electrostatic discharge protection device100.

FIG. 3illustrates a case in which a bias voltage Vbias is not applied to the sixth diffusion region136of the electrostatic discharge protection device100.FIG. 4is an illustrative equivalent circuit of an electrostatic discharge protection device illustrated inFIG. 3. In the present exemplary embodiment, a case in which the ESD current IESDis input to the anode electrode and the bias voltage Vbias is not applied to the sixth diffusion region136will be described.

Referring toFIGS. 3 and 4, when the ESD current IESDis input to the anode electrode, the second NMOS transistor constituted by the second gate electrode G2, the fifth diffusion region135, and the sixth diffusion region136may be driven. In this case, the fifth diffusion region135may be a drain terminal of the second NMOS transistor and the sixth diffusion region136may be a source terminal of the second NMOS transistor. When the ESD current IESDis input to the anode electrode, the first NMOS transistor constituted by the first gate electrode G1, the second diffusion region132, and the sixth diffusion region136may be driven. In this case, the sixth diffusion region136may be a drain terminal of the first NMOS transistor and the second diffusion region132may be a source terminal of the first NMOS transistor. As a result, a current path passing through a third resistor R3, the second NMOS transistor, and the first NMOS transistor may be formed. In this case, the time when the first NMOS transistor and the second NMOS transistor are turned on may be determined by a time constant (R1×C). That is, the first resistor R1and the capacitor C may be used to adjust a level of a trigger voltage for driving the electrostatic discharge protection device100.

When the ESD current IESDis input to the anode electrode, a first BJT (bipolar junction transistor) Q1may be formed by an NPN junction of the second diffusion region132, the P type110, and the sixth diffusion region136. A second BJT (Q2) may also be formed by an NPN junction of the sixth diffusion region136, the P type110, and the fifth diffusion region135. As a result, a current path {circle around (a)} passing through the N well120, the second BJT (Q2), and the first BJT (Q1) may be formed. The BJTs generated when the ESD current IESDis input may be parasitic BJTs. A current path passing through the BJTs is a main path for discharging the ESD current IESD.

A third BJT (Q3) may be formed by a PNP junction of the third diffusion region133, the P type110, and the first diffusion region131.

In the present exemplary embodiment, when the ESD current IESDis input to a base terminal of the third BJT (Q3), the third BJT (Q3) is turned on. A current flowing through the third BJT (Q3) is input to a base terminal of the first BJT (Q1) and a base terminal of the second BJT (Q2) to turn on the first BJT (Q1) and the second BJT (Q2). Consequently, the ESD current IESDmay be grounded through the cathode electrode. In a case in which the bias voltage Vbias is not applied, the current path {circle around (a)} through the BJTs passes through the second BJT (Q2) and the first BJT (Q1). The current path {circle around (a)} has the shortest distance which is a relatively straight line represented by an arrow illustrated inFIG. 3.

FIG. 5illustrates a case in which a bias voltage is applied to a sixth diffusion region136of an electrostatic discharge protection device100illustrated inFIG. 2.FIG. 6is an illustrative equivalent circuit of an electrostatic discharge protection device illustrated inFIG. 5. In the present exemplary embodiment, a case in which the ESD current IESDis input to the anode electrode and the bias voltage Vbias is applied to the sixth diffusion region136will be described.

Unlike the example described inFIGS. 3 and 4, when a bias voltage Vbias higher than a specific voltage level is applied to the sixth diffusion region136, the second BJT (Q2) is turned off. This result is because a reverse bias is applied between the base terminal110of the second BJT (Q2) and the emitter terminal136thereof. Instead of the second BJT (Q2) being turned on, a fourth BJT (Q4) constituted by the second diffusion region132, the P type substrate110and the fifth diffusion region135is turned on. In this case, a current path {circle around (b)} has a shape represented as an arrow including a curved portion and a length thereof is relatively longer than a length of the current path {circle around (a)} illustrated inFIG. 3. As a level of the bias voltage Vbias becomes higher, the current path {circle around (b)} may be formed such that the ESD current IESDflows through a deeper region of the P type substrate110. If a resistance of the electrostatic discharge protection device100increases due to an increase of the current path, a level of a holding voltage of the electrostatic discharge protection device100may increase.FIG. 7illustrates an increase of a level of a holding voltage of the electrostatic discharge protection device100.

FIG. 7is a graph illustrating a voltage-current characteristic of an electrostatic discharge protection device in accordance with an exemplary embodiment. A horizontal axis of the graph is a voltage of the cathode electrode of the electrostatic discharge protection device100described inFIGS. 2 to 6and a vertical axis represents a cathode current. A graph labeled {circle around (1)} is a graph of when the bias voltage Vbias is not applied to the sixth diffusion region136and a graph labeled {circle around (2)} is a graph of when the bias voltage Vbias is applied to the sixth diffusion region136.

Referring to the graph {circle around (1)}, a voltage level of the anode electrode increases by an inflow of the ESD current IESDto reach a first trigger voltage Vtrig1. In response to the voltage level reaching the first trigger voltage Vtrig1, the electrostatic discharge protection device100operates and thereby the ESD current IESDmay be discharged to the cathode electrode. The trigger voltage may refer to a voltage for driving the electrostatic discharge protection device100. As the electrostatic discharge protection device100discharges the ESD current IESD, a voltage of the anode electrode reaches a first holding voltage Vhold1. If the first holding voltage Vhold1is lower than a level of an operation voltage Vop, the electrostatic discharge protection device100becomes latched up and thereby an incorrect operation may occur in the electrostatic discharge protection device100. The operation voltage Vop may refer to a voltage for driving a chip to prevent damage due to the ESD current IESDby using the electrostatic discharge protection device100.

According to exemplary embodiments, to prevent an incorrect operation due to a latch-up of the electrostatic discharge protection device100, the bias voltage Vbias may be applied to the sixth diffusion region136so that the electrostatic discharge protection device100has a holding voltage (e.g., Vhold2) that is higher than the operation voltage Vop. As described inFIG. 5, a current path passing through the BJTs may be formed, for example, as the path {circle around (b)} by applying the bias voltage Vbias to the sixth diffusion region136. As a result, since a resistance of the current path increases due to an increase of a length of the current path, a level (e.g., voltage level) of the holding voltage of the electrostatic discharge protection device100may be increased. According to an exemplary embodiment, a level of the holding voltage may be changed by changing a level of the bias voltage Vbias being applied to the sixth diffusion region136. Since the electrostatic discharge protection device100maintains the first holding voltage Vhold1in a state where a device (e.g., solid state drive (SSD), smart phone) including the electrostatic discharge protection device100is powered off, damage due to deterioration can be minimized.

FIG. 8is a cross-sectional view of an electrostatic discharge protection device200in accordance with another exemplary embodiment.FIGS. 9 and 10are illustrative equivalent circuits of the electrostatic discharge protection device illustrated inFIG. 8.FIG. 9illustrates a case in which a bias voltage Vbias is not applied to a sixth diffusion region236.FIG. 10illustrates a case in which the bias voltage Vbias is applied to the sixth diffusion region236. The electrostatic discharge protection device200is similar to the electrostatic discharge protection device100described inFIGS. 2 to 6, except that the electrostatic discharge protection device200excludes the capacitor C. Thus, a description of common features already discussed with respect to the electrostatic discharge protection device100is omitted.

Referring toFIG. 8, the electrostatic discharge protection device200includes a first diffusion region231, a second diffusion region232, a third diffusion region233, a fourth diffusion region234, a fifth diffusion region235, a sixth diffusion region236, a substrate210(e.g., P-type substrate), and an N-well220. A first gate electrode G1and a second gate electrode G2are not connected to an anode electrode. The first gate electrode G1and the second gate electrode G2are connected to a cathode electrode through a first resistor R1. That is, a gate electrode G1of a first NMOS transistor constituted by the first gate electrode G1, the second diffusion region232, and the sixth diffusion236is always grounded. Similarly, a gate electrode G2of a second NMOS transistor constituted by the second gate electrode G2, the fifth diffusion region235, and the sixth diffusion236is always grounded. Thus, the first NMOS transistor and the second NMOS transistor are always turned off.

Referring toFIGS. 8 and 9, when the bias voltage Vbias is not applied to the sixth diffusion region236, a first BJT (Q1) constituted by the second diffusion region232, the substrate210, and the sixth diffusion region236is turned on. A second BJT (Q2) constituted by the fifth diffusion region235, the substrate210, and the sixth diffusion region236is turned on. Thus, an ESD current IESDinput to the anode electrode flows into the cathode electrode through a path to the path (e.g., path {circle around (a)} illustrated inFIG. 3.

Referring toFIGS. 8 and 10, when the bias voltage Vbias is applied to the sixth diffusion region236, the second BJT (Q2) is turned off by a reverse bias. A fourth BJT (Q4) constituted by the second diffusion region232, the substrate210and the fifth diffusion region235is instead turned on. As a result, an ESD current IESDinput to the anode electrode flows into the cathode electrode through a path to the path (e.g., path {circle around (b)} illustrated inFIG. 5. That is, since a resistance of the electrostatic discharge protection device200increases due to an increase of a length of the current path, a level of a holding voltage of the electrostatic discharge protection device200may be increased.

FIG. 11is a cross-sectional view of an electrostatic discharge protection device300in accordance with another exemplary embodiment.FIGS. 12 and 13are illustrative equivalent circuits of the electrostatic discharge protection device illustrated inFIG. 11.FIG. 12illustrates a case in which a bias voltage Vbias is not applied to a sixth diffusion region336.FIG. 13illustrates a case in which the bias voltage Vbias is applied to the sixth diffusion region336. The electrostatic discharge protection device300is similar to the electrostatic discharge protection device100described inFIGS. 2 to 6, except that the electrostatic discharge protection device300excludes the first gate electrode G1, the second gate electrode G2, the first resistor R1, and the capacitor C. Thus, a description of common features already discussed with respect to the electrostatic discharge protection device100is omitted.

Referring toFIGS. 11 and 12, the electrostatic discharge protection device300includes a first diffusion region331, a second diffusion region332, a third diffusion region333, a fourth diffusion region334, a fifth diffusion region335, a sixth diffusion region336, a substrate310(e.g., P type substrate), and an N-well320. When the bias voltage Vbias is not applied to the sixth diffusion region336, a first BJT (Q1) constituted by a second diffusion region332, the substrate310, and the sixth diffusion region336is turned on. A second BJT (Q2) constituted by the fifth diffusion region335, the substrate310, and the sixth diffusion region336is turned on. Thus, an ESD current IESDinput to an anode electrode flows into the cathode electrode through a path to a path (e.g., path {circle around (a)} illustrated inFIG. 3.

Referring toFIGS. 11 and 13, when the bias voltage Vbias is applied to the sixth diffusion region336, the second BJT (Q2) is turned off by a reverse bias. A fourth BJT (Q4) constituted by the second diffusion region332, the substrate310and the fifth diffusion region335is instead turned on. As a result, an ESD current IESDinput to the anode electrode flows into the cathode electrode through a path similar to a path (e.g., path {circle around (b)} illustrated inFIG. 5. That is, since a resistance of the electrostatic discharge protection device300increases due to an increase of a length of the current path, a level of a holding voltage of the electrostatic discharge protection device300may be increased.

FIG. 14is a top plan view illustrating an electrostatic discharge protection device400in accordance with another exemplary embodiment.FIG. 15is a cross sectional view taken along the line II-II′ of an electrostatic discharge protection device illustrated inFIG. 14.

Referring toFIGS. 14 and 15, an electrostatic discharge protection device400includes a P type substrate410, an N well420formed on the P type substrate410, a P well425formed in the N well420, a first diffusion region431and a second diffusion region432that are formed in the P well425, a third diffusion region433and a fourth diffusion region434that are formed in the N well420, a fifth diffusion region435formed on the border of the P well425and the N well120, and a sixth diffusion region436formed between the second diffusion region432and the fifth diffusion region435. The first to sixth diffusion regions431˜436may be formed to extend in a first direction D1along a second direction D2.

The electrostatic discharge protection device400further includes a first gate electrode G1formed on a first region R1between the second diffusion region432and the sixth diffusion region436. The first diffusion region431and the second diffusion region432may be formed to be adjacent to each other. The third diffusion region433and the fourth diffusion region434may be formed to be adjacent to each other. The first gate electrode G1and the second gate electrode G2may be formed to extend in the first direction D1along the second direction D2.

The N well420may be doped with low concentration N type impurities. The P well425may be doped with low concentration P type impurities. The first diffusion region431and the third diffusion region433may be regions doped with higher concentration P type impurities than the P well425. The second diffusion region432, the fourth diffusion region434, the fifth diffusion region435and the sixth diffusion region436may be N type conductivity type regions. For example, the second diffusion region432, the fourth diffusion region434, the fifth diffusion region435and the sixth diffusion region436may be regions doped with higher concentration N type impurities than the N well120.

The electrostatic discharge protection device400may include a second gate electrode G2formed on a second region R2between the fifth diffusion region435and the sixth diffusion region436. The electrostatic discharge protection device400may further include a first insulating layer provided between the first region R1and the first gate electrode G1, and a second insulating layer provided between the second region R2and the second gate electrode G2. A channel of a first NMOS transistor generated by the first gate electrode G1, the second diffusion region432and the sixth diffusion region436may be formed in the first region R1. A channel of a second NMOS transistor generated by the second gate electrode G2, the fifth diffusion region435and the sixth diffusion region436may be formed in the second region R2. The electrostatic discharge protection device400may further include a device isolation layer STI, which may be formed using a shallow-trench isolation technology, provided between the third diffusion region433and the fifth diffusion region435.

A bias voltage Vbias may be supplied to the sixth diffusion region436. For example, the bias voltage Vbias may be provided to the sixth diffusion region436through a conductive line441. The first diffusion region431and the second diffusion region432may be connected to a cathode electrode. For example, a ground voltage may be provided through the cathode electrode. The third diffusion region433and the fourth diffusion region434may be connected to an anode electrode. For example, an electrostatic discharge (ESD) current may be input through the anode electrode. The first diffusion region431, the second diffusion region432and the first gate electrode G1may be connected to one another through a first resistor R1. The third diffusion region433, the fourth diffusion region434and the second gate electrode G2may be connected to one another through a capacitor C. The first gate electrode G1and the second gate electrode G2may be connected to each other.

To connect the above-mentioned elements to one another, a conductive line that connects the first diffusion region431and the second diffusion region432to the cathode electrode, a conductive line that connects the third diffusion region433and the fourth diffusion region434to the anode electrode, and a conductive line that connects the first gate electrode G1to the second gate electrode G2may be further provided.

FIGS. 16 and 17are illustrative equivalent circuits of an electrostatic discharge protection device illustrated inFIG. 15.FIG. 16illustrates a case in which a bias voltage Vbias is not applied to the sixth diffusion region436.FIG. 17illustrates a case in which the bias voltage Vbias is applied to the sixth diffusion region436.

Referring toFIGS. 15 and 16, when the bias voltage Vbias is not applied to the sixth diffusion region436, a first BJT (Q1) constituted by the second diffusion region432, the P well425and the sixth diffusion region436is turned on. A second BJT (Q2) constituted by the fifth diffusion region435, the P well425and the sixth diffusion region436is also turned on. Thus, the ESD current IESDinput to the anode electrode flows into the cathode electrode along a surface of the substrate410.

Referring toFIGS. 15 and 17, when the bias voltage Vbias is applied to the sixth diffusion region436, the second BJT (Q2) is turned off by a reverse bias. A fourth BJT (Q4) constituted by the second diffusion region432, the P well425and the fifth diffusion region435is instead turned on. As a result, the ESD current IESDinput to the anode electrode flows through a deeper region of the substrate410compared with a case in which the bias voltage Vbias is not applied. That is, since a resistance between the anode electrode of the electrostatic discharge protection device400and the cathode electrode thereof increases due to an increase of a length of the current path, a level of a holding voltage of the electrostatic discharge protection device400may be increased. Also, it is understood that, according to other exemplary embodiments, techniques other than applying a bias voltage may also be used to increase the resistance between the anode and cathode electrodes.

As described above, an incorrect operation due to a latch-up of the electrostatic discharge protection device may be prevented by placing a separate diffusion region that is provided with a bias voltage from the outside in the electrostatic discharge protection device. A holding voltage can be adjusted without increasing a size of the electrostatic discharge protection device by applying a bias voltage to the separate diffusion region. Additionally, when a device (e.g., SSD, smart phone, etc.) including the electrostatic discharge protection device is powered off, the bias voltage is not applied to the separate diffusion region and thereby the electrostatic discharge protection device can maintain a lower holding voltage as compared with when the bias voltage is applied to the separate diffusion region. As a result, damage due to deterioration can be minimized.

FIG. 18is a block diagram illustrating a device1000including an electrostatic discharge protection device1100in accordance with another exemplary embodiment. The device1000may include the electrostatic discharge (ESD) protection device1100and a chip1200. The ESD protection device1100may be implemented as any of the ESD protection devices100,200,300, or400, or a combination thereof. The chip1200may be implemented as many different types of chips, and may be a device supplied with a power supply VDDto drive the device1000.

When the device1000is powered on (or is booted), the power supply VDDis supplied to the chip1200. In this case, an ESD current IESDmay be generated and the electrostatic discharge protection device1100may be provided with a separate bias voltage Vbias from the outside and the bias voltage Vbias may be applied to a separate diffusion region prepared according to the exemplary embodiments to be used to increase a level of a holding voltage of the electrostatic discharge protection device1100. In addition, since the bias voltage Vbias is applied only when the device1000is powered on (or is booted), the electrostatic discharge protection device1100can be prevented from being damaged by deterioration.

FIG. 19is a block diagram illustrating a device2000including an electrostatic discharge protection device2100in accordance with an exemplary embodiment. The device2000may include the electrostatic discharge (ESD) protection device2100, a chip2200, and a voltage controller2300. The ESD protection device2100may be implemented as any of the ESD protection devices100,200,300, or400, or a combination thereof. The present exemplary embodiment illustrates a case in which the electrostatic discharge protection device2100uses a voltage VDDfor driving the chip2200instead of receiving a separate external bias voltage.

The voltage controller2300can use the voltage VDDfor driving the chip2200to generate a bias voltage Vbias. The bias voltage Vbias generated by the voltage controller2300can applied to a separate diffusion region included in the electrostatic discharge protection device2100to be used to increase a level of a holding voltage of the electrostatic discharge protection device2100.

According to exemplary embodiments disclosed herein, a holding voltage may be increased by increasing a resistance between an anode electrode and a cathode electrode without increasing a size of an electrostatic discharge protection device.