Monolithic MOSFET and Schottky diode device

A Schottky diode is integrated into a planar or trench topology MOSFET having parallel spaced source regions diffused into spaced base stripes. The diffusions forming the source and base stripes are interrupted to permit the drift region to extend to the top of the die and receive a Schottky barrier metal and the source contact. The MOSFET and Schottky share the same drift region, and the pitch between base and source stripes is not changed to receive the Schottky structure.

FIELD OF THE INVENTION

This invention relates to semiconductor devices and more specifically relates to a power MOSFET and Schottky diode integrated in a common chip.

BACKGROUND OF THE INVENTION

It is frequently desirable to integrate a Schottky diode and MOSFET into a common chip or die and package. For example, in a synchronous buck converter circuit, the low side FET requires a low Rdson, a low Vf(forward voltage drop) in the third quadrant and a low reverse recovery charge.

Such devices have been proposed in the past in both planar and trench topologies. For example, such a device is proposed by B. J. Baliga and Dev Alok Girdhar; Paradigm Shift In Planar Power MOSFET Technology, Power Electronics, page 24, November 2003. This device has the disadvantage of changed cell pitch and relatively poor use of silicon area.

It is also known to have laterally displaced MOSFET areas and Schottky areas, as in the IRF6691 device of International Rectifier, the assignee of the present application. This structure however, has a significant die area penalty because the drift region of the 2 devices is not shared.

Still another monolithic Schottky and MOSFET is shown in U.S. Pat. No. 6,987,305 (IR-2014).

It would be very desirable to provide a monolithic Schottky and FET which preserves die area and can be fabricated with a minimum change in process as compared to that used to make the MOSFET, and which employs a space saving termination structure.

BRIEF DESCRIPTION OF THE INVENTION

In accordance with the invention, a Schottky structure is inserted in short sections along the length of interrupted source and base diffusion strips of a MOSFET junction pattern. The elongated source strips can be formed in the silicon surface of a planar MOSFET, or in the mesas of a MOSFET in a trench type topology. The novel structure is formed by adding a single mask for masking the P−base region at spaced region to permit the underlying N−body to reach the surface to be contacted by the source/Schottky contact to form the Schottky portion of the device.

The pitch of the source stripes need not change to accommodate the Schottky and the same N−drift region accommodates both the Schottky and MOSFET for a reduced area penalty. Further, a reduced area termination is also created.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

Referring first toFIGS. 1 and 2, there is shown a planar embodiment in which a small segment of a silicon wafer (or die)20has the conventional N+substrate21and an N−drift region22which is usually an epitaxially deposited silicon layer. A plurality of parallel spaced P type base strips, one of which is shown as P−strip23are diffused into drift region22, and a plurality of N+source strips, one of which is shown as strip24are diffused into the P base in the usual manner. A gate oxide25is formed over the invertible channel region26between source24and base23and a conductive polysilicon gate electrode27is formed atop oxide25. An insulation layer28, usually TEOS, covers and insulates conductive gate27from source electrode29, usually aluminum.

In accordance with one aspect of the invention, the length of N+source strip24and base diffusion23are interrupted as shown inFIG. 2and a Schottky device40is formed at that location. More specifically, the base diffusion23and source diffusion are blocked in area40and a Schottky contact is made to the exposed N−drift in area40. If desired, a conductive silicide barrier can be first formed atop the exposed N−drift region, and covered by the aluminum contact. One or more such Schottky contacts may be formed in each of the base and source strips inFIGS. 1 and 2.

FIGS. 3 and 4show an embodiment in which the Schottky diode can be incorporated into a trench type MOSFET. Thus, the starting silicon20has the usual N+substrate21and N−layer22. A P type channel diffusion48is formed in the top surface of layer22and an N+source layer is formed atop channel region48. Plural spaced source trenches50,51and a gate trench52are formed through source layer49and P channel region48and into silicon layer22as shown inFIG. 3. These trenches are then filled with insulation, for example, oxide bodies53,54and55respectively, which is etched to receive conductive polysilicon source bodies56and57and a conductive gate polysilicon58respectively. A thin gate oxide (or nitride) is left between channel48and source bodies56,57and gate58. A conductive source electrode, usually aluminum is deposited atop the wafer or die, in contact with source diffusions49and source polysilicon masses56and57.

As shown inFIG. 4, the source and base diffusions are patterned by suitable masks so that the N−region22reaches the device surface at Schottky areas60and61where they can be contacted by the source49or some other Schottky forming metal layer. Thus, the novel Schottky structures are formed in the mesas between trenches50and52with no reduction in device pitch due to integrating Schottky devices and with little interference with the manufacturing process.

FIGS. 5,6and7show a further trench embodiment of the invention,FIG. 5showing the structure in partial isometric form, with the device termination. Thus, the starting wafer20has an N+substrate21, and N−epitaxially formed layer (drift region)22. A P−base diffusion48is formed in layer22and an N+source diffusion49is formed in base layer48. Further P+base contact diffusions70are also formed, as usual.

The device active region is formed of a plurality of spaced trenches71,72, and a termination trench73is also formed and surrounds the die. An oxide layer80overlies the surface of base48at the outer periphery of the die and into termination trench73.

Trenches71and72are lined with gate oxides81and82respectively and are filled with conductive polysilicon gates83and84respectively. Insulation caps85and86seal and insulate the tops of polysilicon stripe masses83and84.

A further conductive polysilicon mass90fills termination trench76.

As best shown inFIGS. 6 and 7short sections of the P base48and N+source49and SP+contact region70are eliminated along the length of the P base to expose a Schottky area90at which the N− epi region22reaches the surface of die20. Preferably, a thin conductive silicide, for example titanium silicide contacts the surface of region90and the N+and P+regions49and70, forming a Schottky barrier to N−silicon22in area90.

A contact metal, for example, aluminum is then deposited atop the chip and, as shown inFIG. 5, is etched to form source contact100and gate contact bus101. Source contact100contacts source regions49and SP+regions70, and gate bus100contacts trench polysilicon ring90. Note that the ends of polysilicon strips83,84extend to and contacted by gate aluminum bus90.