Semiconductor device and method for forming the same

A semiconductor device includes a semiconductor substrate including a pad region and a peripheral region, a first buffer layer formed to include a capacitor over the semiconductor substrate in the pad region, a second buffer layer formed to include a first contact pad over the first buffer layer, and a third buffer layer formed to include a second contact pad over the first contact pad. The semiconductor device, by additionally forming a buffer layer at a lower part in the pad region, reduces a stress caused by wire bonding. Thus, an applied stress to a lower structure in the pad region is also reduced. As a result, the buffer layer prevents formation of an electrical bridge between the pad region and the peripheral region.

CROSS-REFERENCE TO RELATED APPLICATION

The priority of Korean patent application No. 10-2013-0053895 filed on 13 May 2013, the disclosure of which is incorporated by reference hereby in its entirety, is claimed.

BACKGROUND

Embodiments relate to a semiconductor device and a method for forming the same, and more particularly to a semiconductor device for preventing formation of a crack from in a pad region and a peripheral region of the semiconductor device, and a method for forming the semiconductor device.

Generally, highly-integrated semiconductor devices have been formed by stacking conductive and by interconnecting upper and lower conductive layers.

The number of stacked conductive layers increases in proportion to increasing precision and complexity of the semiconductor devices. If stacking and patterning processes to form a desired number of conductive layers have been carried out, a bonding pad having a multi-layered conductive film is formed.

The bonding pad has a line structure formed over a surface of the integrated circuit and is configured to provide a contact surface between an external pin lead and an internal circuit. A bonding wire provides an electrical connection between the pin and the bonding pad. During attachment of the bonding wire to the bonding pad, one end of the bonding wire is positioned in a certain location of the bonding pad, using a precise position adjustment machine. In the attachment process, a mechanical stress is applied to the location of the bonding pad by the precision position adjustment machine. This stress can in turn be transferred and applied to a MOS capacitor and a specific circuit, both of which are disposed in a lower part of the semiconductor device and configured to reduce noise of the semiconductor device. As a result, a defect (e.g., a crack or void) occurs in the semiconductor device that may result in a micro bridge in the pad region and the peripheral region.

SUMMARY

Various embodiments are directed to providing a semiconductor device and a method for forming the same to address issues of the related arts.

An embodiment relates to a semiconductor device for addressing the above-described issues that a mechanical stress is applied to a bonding pad at a contacting location with a bonding wire may result in a crack in a lower structure of a semiconductor device, so that a micro bridge occurs in the pad region and the peripheral region.

In accordance with an embodiment, a semiconductor device includes: a semiconductor substrate including a pad region and a peripheral region; a first buffer layer formed to include a capacitor over the semiconductor substrate in the pad region; a second buffer layer formed to include a first contact pad over the first buffer layer; and a third buffer layer formed to include a second contact pad over the first contact pad.

The semiconductor device may further include: a metal-oxide-semiconductor (MOS) transistor formed below the first buffer layer, and formed over the semiconductor substrate in the pad region and the peripheral region.

The MOS transistor may include a laminate structure of a polysilicon layer, a metal layer, and a hard mask layer.

The semiconductor device may further include: a first metal line formed over the MOS transistor.

The semiconductor device may further include: a first metal contact formed over the first metal line in the peripheral region.

The first buffer structure may be formed over the first metal line.

The first contact pad may include tungsten.

A top surface of the first contact pad may be formed approximately at a same level as a top surface of the first metal contact.

The semiconductor device may further include: a second metal line formed over the first metal contact in the peripheral region.

The second metal line may include a copper (Cu) line.

The semiconductor device may further include: a second metal contact formed over the second metal line in the peripheral region.

The second contact pad may include tungsten.

A top surface of the second contact pad may be formed approximately at a same level as a top surface of the second metal contact. The first contact pad and the second contact pad may be spaced apart from each other by an insulation film.

The semiconductor device may further include a metal pad formed over the third insulation film in the pad region and the peripheral region.

The metal pad may include aluminum. The semiconductor device may further include: a pad open portion including a portion of the metal pad in the pad region and defined by a passivation layer formed over the metal pad in the peripheral region.

In accordance with an embodiment, a method for forming a semiconductor device includes: forming a first buffer structure including a capacitor over a semiconductor substrate in a pad region, the semiconductor substrate including the pad region and a peripheral region; forming a second buffer layer including a first contact pad over the first buffer layer; and forming a third buffer layer including a second contact pad over the first contact pad.

The method may further include: before forming the first buffer structure, forming a MOS transistor over the semiconductor substrate in the pad region and the peripheral region.

The MOS transistor may include a laminate structure of a polysilicon layer, a metal layer, and a hard mask layer.

The method may further include: forming a first metal line over the MOS transistor.

The forming the first buffer layer may include: forming a storage node; forming a dielectric film over the storage node; and forming an upper electrode over the dielectric film.

The forming the second buffer layer may include: forming a first insulation film over the first buffer layer in the pad region and the peripheral region; forming a first pad trench by etching the first insulation film to expose a portion of the first buffer layer; and forming the first pad contact by forming a barrier metal layer and a conductive material to fill the first pad trench.

The conductive material may include tungsten.

The method may further include: while forming the second buffer layer, forming a first metal contact penetrating the first insulation film over the first metal line in the peripheral region.

The method may further include: forming a second metal line over the first metal contact.

The forming the second metal line may includes: forming a second insulation film over the first insulation film; forming a trench by etching the second insulation film to expose the first metal contact in the peripheral region; and filling a metal layer in the trench.

The forming the third buffer layer may include: forming a third insulation film over the second insulation film; forming a second pad trench by etching the third insulation film to a depth shallower than a thickness of the third insulation film in the pad region; and forming the second pad contact by forming a barrier metal layer and a conductive material to fill the second pad trench.

The conductive material may include tungsten.

The method may further include: while forming the third buffer layer, forming a second metal contact penetrating the third insulation film over the second metal line in the peripheral region.

The method may further include: forming a metal pad over the third insulation film in the pad region and the peripheral region. The metal pad may include aluminum.

The method may further include: after forming of the metal pad, forming a passivation layer over the metal pad; and forming a pad open portion by etching the passivation layer in the pad region to expose the metal pad in the pad region.

DESCRIPTION OF EMBODIMENTS

Embodiments of the present invention are described herein with reference to illustrations that are schematic illustrations of embodiments (and intermediate structures). As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, exemplary embodiments should not be construed as limited to the particular shapes of regions illustrated herein but may include deviations in shapes that result, for example, from manufacturing. In the drawings, lengths and sizes of layers and regions may be exaggerated for clarity. Like reference numerals in the drawings denote like elements. It will be understood that when an element is referred to as a “layer,” the element may be a single layer or the layer may comprise a plurality of layers. It will also be understood that when an element or structure is referred to as being “over” another element, a portion of the structure may be provided over the element, or the entire structure may be provided over the element.FIG. 1is a cross-sectional view illustrating a semiconductor device according to an embodiment.

Referring toFIG. 1, a semiconductor device according to an embodiment includes a semiconductor substrate100including a pad region (i) and a peripheral region (ii), a first buffer layer including a capacitor formed over the semiconductor substrate100in the pad region (i), a second buffer layer including a first contact pad132formed over the first buffer layer, and a third buffer layer including a second contact pad148formed over the first contact pad132.

The capacitor included in the first buffer layer may have a storage node114, a dielectric film118, and an upper electrode120in the pad region (i). The capacitor may further include a support film116over the storage node114to prevent leaning of the storage node114. The first buffer layer reduces a stress generated when a wire is bonded to a certain position in a pad open portion158, so that a stress applied to a lower structure in the pad region (i) and the peripheral region (ii) of the semiconductor device is reduced. A MOS transistor105may further be formed over the semiconductor substrate100in the pad region (i) and the peripheral region (ii), and a metal line110may further be formed over the MOS transistor105. The MOS transistor105may be isolated by an insulation film107. Here, the storage node114may be formed over the metal line110. For example, the MOS transistor105may have a laminate structure of a polysilicon layer102, a metal layer103, and a hard mask layer104. In an embodiment, the semiconductor device may further include a first metal contact134configured to penetrate an insulation film122in the peripheral region (ii). The insulation film122may be formed over the metal line110in the peripheral region (ii). The insulation film122may be formed in the peripheral region (ii) and the pad region (i).

The first contact pad132may include a laminate structure of a barrier metal layer128and a conductive material130at an upper part of the upper electrode120. The first contact pad132may serve as a second buffer layer. The first contact pad132reduces a stress generated when a wire is bonded to the pad in the pad open portion158, so that a stress applied to the lower structure in the pad region (i) and the peripheral region (ii) is reduced. As a result, the first contact pad132may prevent forming of an electric bridge between the pad region (i) and the peripheral region (ii). For example, the barrier metal layer128may include a titanium (Ti) film or a titanium nitride (TiN) film, and the conductive material130may include tungsten (W). In this case, a top surface of the first contact pad132may be located approximately at the same level as a top surface of the first metal contact134. A metal line140may be formed over the first metal contact134in the peripheral region (ii). For example, the metal line140may include a copper (Cu) line. When the metal line140is formed by a damascene process, insulation films136and138may be formed over the insulation film122and etched. Then, in the damascene process, the metal line140fills the etched portions of the insulation films136and138. In this case, the insulation film136may be a nitride film, and the insulation film138may be an oxide film. In addition, a second metal contact150may further be formed over the metal line140. For example, the second metal contact150may be formed to penetrate the insulation film142formed over the insulation film138, and the insulation film142may include a Tetra Ethyl Ortho Silicate (TEOS).

The second contact pad148is spaced apart from the first contact pad132by the insulation films136,138and142, and includes a laminate structure of a barrier metal layer144and a conductive material146. The second contact pad148may serve as a third buffer layer. Specifically, the second contact pad148may reduce a stress generated when a wire is bonded to the pad in the pad open portion158, so that a stress applied to the lower structure in the pad region (i) and the peripheral region (ii) of the semiconductor device is reduced. As a result, the second contact pad148may prevents forming of an electric bridge between the pad region (i) and the peripheral region (ii). For example, the barrier metal layer144may include a titanium (Ti) film or a titanium nitride (TiN) film, and the conductive material146may include tungsten (W). In this case, a top surface of the second contact pad148may be located approximately at the same level as a top surface of the second metal contact150.

In addition, a metal pad152formed over the second contact pad148may be included in the pad region (i) and the peripheral region (ii). For example, the metal pad152may include aluminum (Al). The pad open portion158may be formed by etching passivation layers154and156formed over the metal pad152, thereby exposing the metal pad152in the pad region (i) and defining the pad open region158. The remaining passivation layers154and156may be included in the peripheral region (ii).

The semiconductor device according to this embodiment reduces a stress applied to the lower structure including a lower MOS transistor or a specific circuit in the pad region (i) and the peripheral region (ii). Such reduction in the applied stress may be achieved by using the first buffer layer, the second buffer layer, and the third buffer layer contained in the pad region (i). As a result, these buffer layers may prevent formation of electric bridging between the pad region (i) and the peripheral region (ii). A method for forming the semiconductor device according to an embodiment will hereinafter be described with reference toFIGS. 2ato 2h.FIGS. 2ato 2hare cross-sectional views illustrating a method for forming the semiconductor device according to an embodiment.

Referring toFIG. 2a, a MOS transistor105including a polysilicon layer102, a metal layer103, and a hard mask layer104is formed over the semiconductor substrate100including the pad region and the peripheral region. Although the MOS transistor105is formed in both of the pad region and the peripheral region as shown inFIGS. 2cto 2h, the MOS transistor105formed in the peripheral region is not shown inFIGS. 2aand 2bfor convenience of description and better understanding of the present invention. Subsequently, an insulation film107is buried between the MOS transistors105. Thereafter, a metal line110including a barrier metal layer108and a conductive layer109is formed over the MOS transistor105and the insulation film107.

Referring toFIG. 2b, after an insulation film112is formed over the metal line110in the pad region, the insulation film112is etched to define a storage node region. Subsequently, a conductive layer is formed in the storage node region, so that a storage node114of the pad region can be formed. Although the storage node114in the pad region is generally deposited along a surface of the storage node region, the storage node114for use in this embodiment completely fills an inside of the storage node region for convenience of description and better understanding of the present invention. In an embodiment, the storage node114of the pad region may be formed simultaneously when the storage node of a cell region (not shown) is formed. Since an additional process for forming the storage node114in the pad region may be omitted, a process time may be reduced and the storage node114can be easily formed. In order to prevent leaning of the storage node114of the pad region, a support film116may further be formed over the storage node114in the pad region. Subsequently, a dielectric film118and an upper electrode120are formed over the storage node114and the support film116.

A capacitor configured to include the storage node114, the dielectric film118and the upper electrode120in the pad region is used as a first buffer layer for reducing a stress generated when a wire is bonded to the pad in a pad open portion158(seeFIG. 2h), so that a stress transferred and applied to a lower structure including a MOS transistor and a specific circuit in the pad and peripheral regions is reduced. As a result, the capacitor acting as the first buffer layer can prevent formation of electric bridging between the pad region and the peripheral region.

In order to explain patterns formed in the pad region (i) and the peripheral region (ii), how the patterns in the pad region (i) and the peripheral region (ii) are formed will hereinafter be described.

Referring toFIG. 2c, an insulation film122is formed over the entire surface including the pad region (i) and the peripheral region (ii). Subsequently, the insulation film122is etched to expose a portion of the upper electrode120in the pad region (i), so that a first pad trench124is formed. At the same time a metal contact hole126exposing a surface of the metal line110in the peripheral region (ii) is formed. In this case when the first pad trench124is formed simultaneously with the metal contact hole126, a metal contact connected to the upper electrode120in the cell region (not shown) may also be formed.

Referring toFIG. 2d, after a barrier metal layer128is formed over the first pad trench124in the pad region (i) and the metal contact hole126in the peripheral region (ii), a conductive material130is formed to fill the first pad trench124and the metal contact hole126. As a result, a first contact pad132is formed in the pad region (i) and a first metal contact134is formed in the peripheral region (ii). For example, the barrier metal layer128may include a titanium (Ti) film or a titanium nitride (TiN) film, and the conductive material130may include tungsten (W).

In this case, the first contact pad132may serve as a second buffer layer that reduces a stress generated when the wire is bonded to the pad in the pad open portion158(seeFIG. 2h), so that a stress applied to the lower structure including the MOS transistor and the circuit is reduced. As a result, the first contact pad132acting as the second buffer layer can prevent formation of electric bridging between the pad region (i) and the peripheral region (ii).

Referring toFIG. 2e, insulation films136and138are formed over the insulation film122, the first contact pad132, and the first metal contact134. For example, the insulation film136may include a nitride film and the insulation film138may include an oxide film, because a metal line140connected to the first metal contact134is formed by a damascene process. In the damascene process, the insulation films136and138are etched to expose the first metal contact134, resulting in formation of a trench. Then, a metal layer is filled in the trench so that the metal line140is formed. In an embodiment, the metal line140may include a copper (Cu) line.

Referring toFIG. 2f, an insulation film142is formed over the insulation film138and the metal line140. For example, the insulation film142may include a TEOS. Subsequently, some parts of the insulation film142in the pad region (i) and the peripheral region (ii) are etched to form a second pad trench and a metal contact hole, respectively. After a barrier metal layer144is formed in the second pad trench and the metal contact hole, a conductive material146is formed to fill the second pad trench and the metal contact hole. As a result, a second contact pad148is formed in the pad region (i) and a second metal contact150is formed in the peripheral region (ii). For example, the barrier metal layer144may include a titanium (Ti) film or a titanium nitride (TiN) film, and the conductive material146may include tungsten (W).

In this case, the second contact pad148may serve as a third buffer layer that reduces a stress generated when the wire is bonded to the pad in the pad open portion158(seeFIG. 2h), so that a stress applied to the lower structure including the MOS transistor and the circuit is reduced. As a result, the second contact pad148acting as the third buffer layer can prevent forming of electric bridging between the pad region (i) and the peripheral region (ii).

Referring toFIG. 2g, a metal pad152is formed over the insulation film142, the second contact pad148and the second metal contact150. For example, the metal pad152may include aluminum (Al).

Referring toFIG. 2h, after passivation layers154and156are formed over the metal pad152, the passivation layers154and156in the pad region (i) are etched to define the pad open portion158by exposing the metal pad152. In this case, the passivation layer154may be formed by a high density plasma (HDP) deposition method, and the passivation layer156may include a nitride film.

The semiconductor device and the method for forming the same according to an embodiment reduces a stress generated when a wire is bonded to the pad metal in the pad open portion158. As a result, a stress applied to a lower MOS transistor in the pad region (i) is reduced by using the storage node114and the upper electrode116serving as the first buffer layer, the first contact pad132serving as the second buffer layer, and the second contact pad148serving as the third buffer layer. In this manner, formation of electric bridging between the pad region (i) and the peripheral region (ii) is prevented.

As is apparent from the above description, the semiconductor device and the method for forming the same according to an embodiment form a plurality of buffer layer at a lower part in the pad region (i). The additional buffer layer reduces the stress caused by the wire bonding, so that the applied stress to the lower structure. As a result, the additional buffer layer prevents forming of an electrical bridge between the pad region (i) and the peripheral region (ii).

Those skilled in the art will appreciate that embodiments may be carried out in other specific ways than those set forth herein without departing from the spirit and characteristics of the above-described embodiments. These embodiments are therefore to be construed as being illustrative and not restrictive.

The above-described embodiments are illustrative and not restrictive. Various alternatives and equivalents are possible. These embodiments are not limited by a type of deposition, etching, polishing, and patterning processes described herein. Nor are these embodiments limited to any specific type of semiconductor device. For example, the above-described embodiments may be implemented in a dynamic random access memory (DRAM) device or a non-volatile memory device.