A fractional-N synthesized chirp generator includes a fractional-N synthesizer and a digital ramp synthesizer. The fractional-N synthesizer has a frequency synthesizer and a sigma-delta modulator module. The fractional-N synthesizer is configured to receive a reference frequency input signal and a frequency control value. The fractional-N synthesizer is configured to transform the reference frequency signal and the frequency control value to a chirped radio frequency (RF) output signal in a deterministic manner. The digital ramp synthesizer is configured to receive the reference frequency input signal and configured to generate the frequency control value utilizing the reference frequency input signal. The digital ramp synthesizer is further configured to provide the frequency control value to the fractional-N synthesizer. The frequency control value varies with time.

BACKGROUND

The subject technology relates generally to signal generation, and more specifically to fractional-N synthesized chirp generators.

Modern radar systems often employ so-called chirped-FM waveforms in which the frequency of the transmitted signal is varied linearly between an upper and lower frequency at a rapid, and often times variable, rate of change with time. In such applications, it is important that the rate of change of the frequency be constant during an interval of up-chirp and/or down-chirp as inaccuracies in this parameter degrade the accuracy performance of the radar system as well as its sensitivity.

One approach to generating a chirped-FM waveform involves applying a voltage ramp to a low phase noise voltage controlled oscillator (VCO). This approach is limited by inherent nonlinearities in the frequency versus control voltage tuning curve of the VCO. Correction for this error term, while possible, is problematic. Another significant problem, and one that is less easily dealt with, is the frequency noise associated with the VCO. At low frequency offsets, the VCO's frequency noise power spectral density is typically quite poor, and this often degrades system performance. This problem is particularly acute in monolithic implementations where limitations on the achievable quality factor of on-chip passive structures results in much poorer VCO frequency and phase noise than that associated with off-chip circuits.

SUMMARY

According to one aspect of the subject technology, a fractional-N synthesized chirp generator comprises a fractional-N synthesizer and a digital ramp synthesizer. The fractional-N synthesizer is configured to receive a reference frequency input signal and a first frequency control value. The fractional-N synthesizer is configured to transform the reference frequency signal and the first frequency control value to a chirped radio frequency (RF) output signal in a deterministic manner.

The fractional-N synthesizer comprises a frequency synthesizer and a sigma-delta modulator module. The frequency synthesizer comprises a voltage controlled oscillator and a programmable frequency divider. The programmable frequency divider is configured to receive a second frequency control value.

The sigma-delta modulator module comprises a sigma-delta modulator and a summation block. The sigma-delta modulator is configured to receive one or more lower significant values of the first frequency control value and the reference frequency input signal. The sigma-delta modulator is configured to transform the one or more lower significant values of the frequency control value to a third frequency control value utilizing a pseudo-random sequence. The third frequency control value represents a fractional count value when averaged over a time window. The summation block is configured to add the third frequency control value and one or more most significant values of the first frequency control value. The summation block is configured to produce the second frequency control value having a frequency spectra content that is higher than a loop bandwidth defined by the frequency synthesizer.

The digital ramp synthesizer is configured to receive the reference frequency input signal and configured to generate the first frequency control value utilizing the reference frequency input signal. The digital ramp synthesizer is further configured to provide the first frequency control value to the fractional-N synthesizer. The first frequency control value varies with time.

The digital ramp synthesizer comprises a ramp synthesizer block and a ramp controller block. The ramp synthesizer block comprises an up-chirp ramp rate block configured to provide an up-chirp ramp rate and a down-chirp ramp rate block configured to provide a down-chirp ramp rate. The ramp synthesizer block further comprises a selector configured to select the up-chirp ramp rate or the down-chirp ramp rate based on a counter control value. The selector is configured to produce a frequency ramp control value. The ramp synthesizer block further comprises a frequency control value generation block configured to produce the first frequency control value utilizing the reference frequency input signal and the frequency ramp control value.

The ramp controller block comprises an upper frequency limit block configured to provide an upper frequency limit value and a lower frequency limit block configured to provide a lower frequency limit value. The ramp controller block further comprises a selector configured to select the upper frequency limit value or the lower frequency limit value based on a counter control value. The selector is configured to produce a frequency limit value. The ramp controller block further comprises a compare logic block configured to receive the frequency limit value and the first frequency control value. The compare logic block is configured to produce a counter control value.

According to one aspect of the subject technology, a fractional-N synthesized chirp generator comprises a fractional-N synthesizer and a digital ramp synthesizer. The fractional-N synthesizer comprises a frequency synthesizer and a sigma-delta modulator module. The fractional-N synthesizer is configured to receive a reference frequency input signal and a frequency control value. The fractional-N synthesizer is configured to transform the reference frequency signal and the frequency control value to a chirped radio frequency (RF) output signal in a deterministic manner.

The digital ramp synthesizer is configured to receive the reference frequency input signal and configured to generate the frequency control value utilizing the reference frequency input signal. The digital ramp synthesizer is further configured to provide the frequency control value to the fractional-N synthesizer. The frequency control value varies with time.

According to one aspect of the subject technology, a method is provided for generating a chirped radio frequency (RF) output signal. The method comprises receiving a reference frequency input signal, and generating a first frequency control value utilizing the reference frequency input signal. The first frequency control value varies with time.

The method further comprises generating a second frequency control value based on the first frequency control value. The second frequency control value includes a pseudo-random sequence. The second frequency control value has a frequency spectra content that is higher than a loop bandwidth defined by a frequency synthesizer. The frequency synthesizer comprises a voltage controlled oscillator. The voltage controlled oscillator does not follow an instantaneous value of the second frequency control value but rather follows a time-averaged value of the second frequency control value. The method further comprises generating a chirped radio frequency (RF) output signal utilizing the reference frequency input signal and the second frequency control value.

DETAILED DESCRIPTION

According to one aspect, the subject technology can provide a highly accurate chirped-FM waveform, which may be realized with circuit elements in a fully-monolithic implementation. This approach utilizes fractional-N synthesizer technology operating off of a stable low-frequency reference clock supplied by an off-chip crystal oscillator.

FIG. 1is a diagram illustrating an example of a fractional-N synthesized chirp generator according to one aspect of the subject technology. A fractional-N synthesized chirp generator100can be fabricated as a monolithic circuit (e.g., a semiconductor integrated circuit) and can be included in a transceiver or a transmitter/receiver chipset, where each of a transceiver or transmitter/receiver chipset may be comprised of one or more integrated circuits. A fractional-N synthesized chirp generator100may include a fractional-N synthesizer110and a digital ramp synthesizer120. A fractional-N synthesizer110may include a frequency synthesizer112and a sigma-delta modulator module114. A frequency synthesizer112may be an integer-N frequency synthesizer. A digital ramp synthesizer120may include a ramp synthesizer block122and a ramp controller block124.

A ramp synthesizer block122may generate a frequency control word M(t) (e.g., a binary word) whose value changes in a linear-step fashion with time. For instance, M(t) may be incremented by a count increment amount between two limits (e.g., an upper frequency limit value FRHand a lower frequency limit value FRL). A ramp controller block124can set these upper and lower frequency limit values FRHand FRLand set the ramp synthesizer block122in a count-up mode (or a ramp-up mode) or a count-down mode (or a ramp-down mode). A fractional-N synthesizer110may translate a frequency control word M(t) to an output frequency fo(t) of a chirped radio frequency (RF) output signal in a deterministic manner.

A frequency synthesizer112may be a phaselock loop frequency synthesizer including a phase detector1, a charge pump2, a loop filter3, a voltage controlled oscillator (VCO)4, and a programmable frequency divider5. A frequency synthesizer112may receive a reference frequency input signal having an input frequency fREF(t). The reference frequency input signal may be generated by an off-chip crystal oscillator. A frequency synthesizer112may produce a chirped radio frequency (RF) output signal having an output frequency fo(t), utilizing the reference frequency input signal, the phase detector1, the charge pump2, the loop filter3, the voltage controlled oscillator (VCO)4, and the programmable frequency divider5. An input frequency fREF(t) may be frequency-scaled to output frequency fo(t). The relationship between an output frequency fo(t) and an input frequency fREF(t) may be expressed as follows:
fo(t)=N*fREF(t),
where N is an integer divide constant associated with the programmable frequency divider5(e.g., N may be Ni, which is described later). An input frequency fREF(t) may be received by a fractional-N synthesizer110and by a digital ramp synthesizer120. More specifically, an input frequency fREF(t) may be received by a frequency synthesizer112or a phase detector1, by a sigma-delta modulator module114or a sigma-delta modulator6, and by a ramp synthesizer block122or a programmable frequency divider9a.

A sigma-delta modulator module114may comprise a sigma-delta modulator6and a summation block7. By including a sigma-delta modulator module114, non-integer values of frequency multiplication may be realized. Lower significant bit(s) K of a frequency control word M(t) can be provided to the sigma-delta modulator6. The sigma-delta modulator6can generate a fractional count value by realizing as a sequence of count values Ki. The summation block7can add the sequence of count values Kito the count value N, which includes the most significant bit(s) of the frequency control word M(t) to realize the ultimate frequency control word sequence denoted as NiinFIG. 1.

Kiand Nimay represent noise-shaped pseudo-random sequences whose mean value is fractional in nature resulting in an average value that is a non-integer count value. A sigma-delta modulator6can translate each K of the frequency control word M(t) into a plurality of unbalanced noise-shaped pseudo-random sequences Kihaving a pseudo-random frequency spectra content that is higher than a loop bandwidth defined by a frequency synthesizer. A sigma-delta modulator module114can translate each frequency control word M(t) into a plurality of unbalanced noise-shaped pseudo-random sequences Nihaving a frequency spectra content that is higher than a loop bandwidth defined by a frequency synthesizer.

As an exemplary illustration, assume that fREF(t) is about 16-20 MHz, and a loop bandwidth defined by a frequency synthesizer112is 100 kHz. A fractional-N synthesized chirp generator can produce an output signal with fo(t) having a noise that is outside the 100 kHz loop bandwidth. A fractional-N synthesized chirp generator can thus produce an output signal with fo(t) having low phase noise and low frequency noise values that are not impacted significantly by the pseudo-random sequence Niproduced by the sigma-delta operation. An output signal may be also independent of a tuning curve of a voltage controlled oscillator (e.g., VCO4).

A programmable frequency divider5may receive a plurality of unbalanced noise-shaped pseudo-random sequences Ni. For each value of M(t), a programmable frequency divider5may oscillate between a corresponding set of values consisting of the value Kiadded to the non-fractional component of the frequency control word, N resulting in bit sequence Ni. These values may be, for example,220,222,224, and226. It should be noted that the subject technology is not limited to any particular values or any particular number of values.

According to one aspect of the subject technology, since the frequency spectra of Nias applied to the programmable frequency divider5inFIG. 1is higher than the frequency synthesizer's loop bandwidth, as defined by the circuit blocks1,2,3,4, and5ofFIG. 1, a voltage controlled oscillator (VCO)4is configured to follow a time-averaged value of Ni, and VCO4is not configured to follow an instantaneous value of Ni. A response rate of VCO4is thus slower than a rate of change of the instantaneous value of Ni, as the loop bandwidth of the frequency synthesizer controlling the VCO4is considerably lower than the dominant spectrum of the sequence Ni.

To realize a chirped-FM waveform in which the frequency fo(t) of the output signal is ramped up and down at various desired ramp rates, the frequency control word M(t) may be varied in a linear manner. This may be accomplished by the up/down counter8a, which is, for example, an up/down frequency counter. By counting up from a predetermined starting count value (i.e., an initial count value), at a predetermined clocking rate fCOUNT(t), the frequency control word M(t) may be ramped up. A clocking rate fCOUNT(t) is the frequency of the clock signal supplied to the up/down counter8a(i.e., a counter clock frequency signal). If this is done at a rate that is sufficiently higher than the phaselock loop bandwidth, then the VCO4can ramp up in frequency at the desired rate. In this implementation, the phaselock loop (i.e., circuit blocks1,2,3,4, and5) performs a tracking filter function. This suppresses frequency noise processes that are outside the loop bandwidth of the synthesizer phaselock loop, thereby suppressing the majority of the frequency noise induced by the spectrally-shaped sequence Niacting upon the programmable frequency divider5inFIG. 1.

By having a programmable frequency divider9a, an up-chirp ramp rate block10, a down-chirp ramp rate block11, and a selector12in the ramp synthesizer block122, the frequency ramp rate for the up-chirp and down-chirp periods may be made to be different. In this exemplary implementation, the up-chirp ramp rate block10and the down-chirp ramp rate block11contain values associated with the desired frequency ramp rates. The selector12is controlled by a counter control value C(t) (e.g., an up/down counter control bit value). The output of the selector12is a frequency ramp control word R(t) (sometimes referred to as a ramp rate) for the programmable frequency divider9a. The frequency ramp control word R(t) may control not only the ramp rate but also the direction of the ramp (up or down).

Phrases such as up-chirp and down-chirp are sometimes referred to as ramp-up and ramp-down, or count-up and count-down; and phrases such as up-chirp and down-chirp modes or periods are sometimes referred to as ramp-up and ramp-down modes or periods, or count-up and count-down modes or periods. An up-chirp mode or period (or a ramp-up or count-up mode or period) may be represented, for example, as a mode or period between tOand tAand between tBand tC, as shown inFIGS. 2,4and5. A down-chirp mode or period may be represented, for example, as a mode or period between tAand tBand between tCand tD, as shown inFIGS. 2,4and5. As shown in these figures, an up-chirp mode and a down-chirp mode repeats.

FIG. 2illustrates an exemplary timing diagram of a frequency ramp control word R(t), a frequency control value M(t), and an output frequency fo(t) according to one aspect of the subject technology. Referring toFIGS. 1 and 2, the up/down counter8ais configured to change the frequency control word M(t) at a rate determined by a time interval T (which is determined fCOUNT(t)). At each time interval T, the frequency control word M(t) may ramp up by a count increment amount during a ramp-up period (e.g., a time period between tOand tA, and a time period between tBand tC). At each time interval T, the frequency control word M(t) may ramp down by the count increment amount during a ramp-down period (e.g., a time period between tAand tB, and a time period between tCand tD). A counter increment amount may be, for example, an integer (e.g., 1).

In this example, the count increment amount remains constant for a given operating mode. In other words, a count increment amount, by which the up/down counter8a's output M(t) varies for each clocking time interval T (defined by fCOUNT(t)) is constant for a given operating mode. By the frequency ramp control word R(t), the clocking rate fCOUNT(t) may be varied between two values, and the rate of change of the frequency control word M(t) produced by the up/down counter8amay be altered, and with it, the rate at which the frequency control word M(t) is ramped up or down.

Still referring toFIGS. 1 and 2, by having an upper frequency limit block13, a lower frequency limit block14, a selector15, and a compare logic block16in a ramp controller block124, the upper frequency limit value FRHand the lower frequency limit value FRLmay be selected, and the fractional-N synthesized chirp generator100can be set to free-run (e.g., operate automatically without a user interruption). This can produce a continuous sequence of repeating up and down ramp periods as defined by the counter control value C(t) generated by the compare logic block16. In this example, the selector15is configured to select the upper frequency limit value FRHor the lower frequency limit value FRLbased on a counter control value C(t), and the selector is configured to produce a frequency limit value FR. The compare logic16may compare the frequency control word M(t) to the frequency limit value FR. The upper frequency limit value FRHand the lower frequency limit value FRLmay be loaded into the upper frequency limit block13and the lower frequency limit block14, respectively. The blocks13and14may be digital registers.

When the counter control value C(t) is logic-high (1), i.e., in a count-up mode (or an up-chirp mode), if a frequency control word M(t) is less than the upper frequency limit value FRH, then the next counter control value C(t+1) will remain in logic-high (1), i.e., in a count-up mode (or an up-chirp mode). When the counter control value C(t) is logic-high (1), i.e., a count-up mode (or an up-chirp mode), if a frequency control word M(t) is greater than the upper frequency limit value FRH, then the next counter control value C(t+1) will go to logic-low (0), i.e., a count-down mode (or a down-chirp mode).

When the counter control value C(t) is logic-low (0), i.e., in a count-down mode (or a down-chirp mode), if a frequency control word M(t) is less than the lower frequency limit value FRL, then the next counter control value C(t+1) will go to logic-high (1), i.e., a count-up mode (or an up-chirp mode). While the counter control value C(t) is logic-low (0), i.e., in a count-down mode (or a down-chirp mode), if a frequency control word M(t) is greater than the lower frequency limit value FRL, then the next counter control value C(t+1) will remain in logic-low (0), i.e., in a count-down mode (or a down-chirp mode).

FIG. 2illustrates how a frequency ramp control word R(t) may vary with time. Referring toFIGS. 1 and 2, during an up-chirp period between tOand tA, the selector12may select a ramp-up rate RUP1from the up-chirp ramp rate block10, and during a down-chirp period between tAand tB, the selector12may select a ramp-down rate RDN1from the down-chirp ramp rate block11. Thus, in this example, the frequency ramp control word R(t) is RUP1during an up-chirp period between tOand tA, and the frequency ramp control word R(t) is RDN1during a down-chirp period between tAand tB.

FIG. 2also illustrates how a frequency control value M(t) may vary with time. Again referring toFIGS. 1 and 2, a clocking rate fCOUNT(t) (i.e., the frequency of a clock signal supplied to the up/down counter8a) is determined by the frequency ramp control word R(t) and the input frequency fREF(t). A one-to-one correspondence may exist between (i) the frequency ramp control word R(t) (or the values contained in the up-chirp ramp rate block10and the down-chirp ramp rate block11) and (ii) the clocking rate fCOUNT(t). A time interval T is 1/fCOUNT(t). An up/down counter8ais configured to change the frequency control word M(t) at a rate determined by the clocking rate fCOUNT(t), and the up/down counter8aoutputs a frequency control word M(t) at each time interval T. M(t) may be ramped up at each time interval T during an up-chirp period, and M(t) may be ramped down at each time interval T during a down-chirp period.

In this example, a time interval T for an up-chirp period between tOand tAis a constant value, and a time interval T for a down-chirp period between tAand tBis another constant value. In this example, a time interval T for an up-chirp period between tOand tAis longer than a time interval T for a down-chirp period between tAand tBbecause R(t) for the up-chirp period between tOand tA(which is RUP1) is smaller than R(t) for the down-chirp period between tAand tB(which is RDN1).

The up/down counter8ais also configured to change the magnitude of the frequency control word M(t) by a count increment amount at each time interval T, and in this example, the count increment amount is constant for a given mode of operation, as described earlier.

As shown inFIG. 2, the frequency control word M(t) increases in linear steps with time at a first constant rate determined by fCOUNT(t) during an up-chirp period (e.g., between tOand tA), and the frequency control word M(t) decreases in linear steps with time at a second constant rate determined by fCOUNT(t) during a down-chirp period (e.g., between tAand tB). The up-chirp period and the down-chirp period are consecutive, and fCOUNT(t) is at a first constant value during an up-chirp period, and fCOUNT(t) is at a second constant value during a down-chirp period. Accordingly, a time interval T remains constant during an up-chirp period, and a time interval T remains constant during a down-chirp period. The frequency fCOUNT(t) for an up-chirp period may be the same or different from fCOUNT(t) for a down-chirp period; a time interval T for an up-chirp period may be the same or different from a time interval T for a down-chirp period.

FIG. 2further illustrates how the output frequency fo(t) of a chirped RF output signal may vary with time. A one-to-one correspondence exists between the frequency control word M(t) and the output frequency fo(t) of a chirped RF output signal. For a given fREF(t), M(t) may define fo(t). For example, during an up-chirp period (e.g., between tOand tA), the frequency control word M(t) may ramp up in linear steps from a lower frequency limit value FRLto an upper frequency limit value FRH. In response to the change in M(t), the output frequency fo(t) may ramp up linearly from a minimum output frequency value FMINto a maximum output frequency value FMAX. During a down-chirp period (e.g., between tAand tB), the frequency control word M(t) may ramp down in linear steps from the upper frequency limit value FRHto the lower frequency limit value FRL. In response to the change in M(t), the output frequency fo(t) may ramp down linearly from the maximum output frequency value FMAXto the minimum output frequency value FMIN.

In this example, RDN1=2*RUP1. Thus, fCOUNT(t) for a down-chirp period is twice the fCOUNT(t) for an up-chirp period, and the time interval T for an up-chirp period is twice the time interval T for a down-chirp period. M(t) for a down-chirp period changes twice as fast as M(t) for an up-chirp period, and in response to the change in M(t), fo(t) for a down-chirp period also changes twice as fast as fo(t) for an up-chirp period.

In operation, a fractional-N synthesized chirp generator100may have many operating modes (e.g., mode1, mode2, mode3, through mode P). For each operating mode, a fractional-N synthesized chirp generator100may have many cycles of an up-chirp period and a down-chirp period. In other words, the up-chirp period and the down-chirp period may be repeated many times (e.g., a few hundred times).FIG. 2merely shows a portion of the cycles (e.g., a little more than three cycles) in an operating mode. Each operating mode may have different values for parameters such as RUP, RDN1, fCOUNT(t), T, FRH, FRL, FMIN, and FMAX. These values may be predetermined.

For one mode, RDNmay be equal to RUP, in which case, fCOUNT(t) for an up-chirp period is equal to fCOUNT(t) for a down-chirp period. The time interval T for an up-chirp period is equal to the time interval T for a down-chirp period. M(t) changes at the same rate for an up-chirp period and a down-chirp period, and fo(t) also changes at the same rate for an up-chirp period and a down-chirp period.

For another mode, RDNmay be different from RUP, in which case, fCOUNT(t) for an up-chirp period is different from fCOUNT(t) for a down-chirp period. The time interval T for an up-chirp period is also different from the time interval T for a down-chirp period. M(t) changes at one rate for an up-chirp period and at a different rate for a down-chirp period, and fo(t) changes at one rate for an up-chirp period and at a different rate for a down-chirp period.

FIG. 3is a diagram illustrating another example of a fractional-N synthesized chirp generator according to one aspect of the subject technology. A fractional-N synthesized chirp100shown inFIG. 3is the same as the fractional-N synthesized chirp100shown inFIG. 1, except for a frequency control value generation block132in which a frequency divider9bis used instead of the programmable frequency divider9aofFIG. 1, and an adder8bis used instead of an up/down counter8aofFIG. 1. InFIG. 3, the frequency divider9bis configured to receive fREF(t) and is configured to produce fCOUNT(t) based on fREF(t). The adder8bis configured to receive R(t) from a selector12, fCOUNT(t) from the frequency divider9b, an initial count value, and a frequency control word M(t). In response to its input, the adder8bis configured to produce a frequency control word M(t).

In this example, the frequency control word M(t) and the output frequency fo(t) vary utilizing a clocking rate fCOUNT(t) that is constant for a given operating mode. The clocking rate fCOUNT(t) is derived by the fixed frequency divider9b. In this exemplary implementation, the adder8badds R(t), which may be a selectable integer value, to the present value of the output from the adder8b(i.e., the present value of a frequency control word M(t)). By selecting a different value for R(t), depending upon the direction and rate of ramp desired, the frequency ramp rate will also be varied. The selection of which value (RUPor RDN) is desired is derived by the same compare logic16as was used in the previous configuration shown inFIG. 1. It should be noted that values RUPand RDNfor the exemplary configuration shown inFIG. 3may have signed words, while values RUPand RDNfor the exemplary configuration shown inFIG. 1may have unsigned words according to one aspect. For the exemplary configuration shown inFIG. 3, RDNmay have a negative sign bit, and RUPmay have a positive sign bit.

FIGS. 4 and 5illustrate exemplary timing diagrams of a frequency ramp control word R(t), a frequency control word M(t), and an output frequency fo(t) for the fractional-N synthesized chirp generator shown inFIG. 3according to one aspect of the subject technology.FIG. 4illustrates waveforms where the magnitude of a ramp-up rate RUP(sometimes referred to as an up-chirp rate) is equal to the magnitude of a ramp-down rate RDN(sometimes referred to as a down-chirp rate), except that RUPis positive, and RDNis negative (i.e., RDN2=−RUP2).FIG. 5illustrates waveforms where the magnitude of a ramp-down rate RDN(or a down-chirp rate) is different from the magnitude of a ramp-up rate RUP(or an up-chirp rate), where RDNis negative, and RUPis positive. In this example, the magnitude of a ramp-down rate RDNis twice the magnitude of a ramp-up rate RUP(i.e., RDN3=−2*RUP3).

The output frequency fo(t) versus time waveforms are shown, where the increasing and decreasing frequency ramp rates are shown for the case where the ramp-up and ramp-down rates are equal (FIG. 4) and unequal (FIG. 5). A maximum output frequency value FMAXis associated with an upper frequency limit value FRH; a minimum output frequency value FMINis associated with a lower frequency limit value FRL. When the frequency control word M(t) from the adder8bofFIG. 3crosses the selected threshold FRH, at time tA, a ramp rate R(t) is switched by a selector12based on a counter control value C(t). The selector12selects RDNfrom a down-chirp ramp rate block11. In response to the change in the ramp rate R(t), the adder8bis also switched to a down-chirp mode. C(t), now at logic low (0), also controls a selector15, which then selects FRLfrom a lower frequency limit block14. The frequency control word M(t) is ramped down until M(t) is less than FRL. This occurs at time tB. At this time a compare logic16sets C(t) to logic-high, and both selectors12and15are switched back to select RUPand FRH, respectively. This pattern may repeat.

Similar toFIG. 2, inFIG. 3, C(t) is in a count-up mode (or an up-chirp mode) if C(t) is logic-high (1), and C(t) is in a count-down mode (or a down-chirp mode) if C(t) is logic-low (0). According to one aspect, RDNis a negative number, and is selected for a count-down mode (or a down-chirp mode), and RUPis a positive number, and is selected for a count-up mode (or an up-chirp mode).

One of the differences betweenFIG. 2(a timing diagram for the configuration shown inFIG. 1) andFIGS. 4 and 5(timing diagrams for the configuration shown inFIG. 3) is that inFIG. 2, the time interval T may vary but the count increment amount remains constant for a given operating mode while inFIGS. 4 and 5, the time interval T remains constant but the count increment amount may vary for a given operating mode, according to one aspect of the subject technology. In other words, inFIG. 2(or for the configuration shown inFIG. 1), the rate at which M(t) changes its value may vary with time while the amount of change in magnitude of M(t) for each time interval T remains constant for a given operating mode, and inFIGS. 3 and 4(or for the configuration shown inFIG. 3), the rate at which M(t) changes its value stays constant with time while the amount of change in magnitude of M(t) for each time interval T may vary for a given operating mode.

FIG. 6is a diagram illustrating an example of a sigma-delta modulator module according to one aspect of the subject technology. A sigma-delta modulator module114may include a sigma-delta modulator6and a summation block7. The sigma-delta modulator6may include a first integrator stage610, a second integrator stage620, a third integrator stage630, and a rounding block640.

The first integrator stage610may include a summation block611and a register block613. The first integrator stage610may receive the lower significant bits K of the frequency control word M(t) as an input. The first integrator stage610may be configured (i) to add one or more lower significant bits K of the frequency control word M(t) to a value from the register block613and (ii) to subtract a sequence of count values Kioutputted by the sigma-delta modulator6from the result of (i). The register block613may store the output of the first integrator stage610.

The second integrator stage620may include a summation block621, a register block623, and a multiplier629. The second integrator stage620may be configured (i) to add an output of the first integrator stage610to a value from the register block623and (ii) to subtract a sequence of count values Kimultiplied by a weighting factor W, from the result of (i). The register block623may store the output of the second integrator stage620.

The third integrator stage630may include a summation block631, a summation block635, a register block633, and a pseudo-random bit sequence generator637. The pseudo-random bit sequence generator637can improve the spurious performance of the fractional-N synthesizer110. The output of the summation block631may be stored in the register block633. The summation block635may add a value from the pseudo-random bit sequence generator637to a value from the register block633. The summation block631may be configured (i) to add the output of the second integrator stage620to the output of the summation block635and (ii) to subtract a sequence of count values Kioutputted by the sigma-delta modulator6from the result of (i). The output of the third integrator stage630may be provided to the rounding block640.

The rounding block640may be configured to generate integer values. The output of the rounding block640may be coupled to the summation block611of the first integrator stage610, to the multiplier629, and to the summation block631.

The summation block7may be configured to add the integer values from the rounding block640to one or more most significant values N of the frequency control word M(t) and may be configured to produce the ultimate frequency control word sequence denoted as Ni.

In operation, the first integrator stage610may receive one or more lower significant bits K of the frequency control word M(t). The first integrator stage610may produce a difference value (or an error term) between K and the output of the sigma-delta modulator6(Ki). The second integrator stage620may integrate error terms with a weighting factor W. The third integrator stage630may integrate error terms with a pseudo-random bit sequence, perform steep noise shaping, and produce a sequence of bits or a sequence of count values (non-integer values). The rounding block640rounds up the sequence of count values from the third integrator stage630to produce integer values.

For example, if M(t) includes 32 bits, K may include 12 bits, and N may include 20 bits. The rounding block640may round up the output of the third integrator stage630and produce, for example, 3 bits as Ki(e.g., values between −4 and +4) that are integer values. However, these integer values on the average over a certain time window represent a non-integer value. In other words, these integer values Kirepresent a fractional count value when averaged over a time window TLdetermined by a phaselock loop bandwidth of a frequency synthesizer (e.g.,112). The relationship between TLand a phaselock loop bandwidth of a frequency synthesizer (e.g.,112) may be expressed as follows: TL=1/(a phaselock loop bandwidth of a frequency synthesizer).

For each time interval T, a sigma-delta modulator6may produce a plurality of values Ki, and a sigma-delta modulator module114may produce a plurality of values Nibecause (i) a sigma-delta modulator6(or a sigma-delta modulator module114) receives and operates utilizing fREF(t) which is greater than fCOUNT(t), and (ii) M(t) is produced by an up/down counter8aor an adder8b, which receives and operates utilizing fCOUNT(t).

Various aspects of the subject technology are described below.FIG. 7is a flow chart illustrating an exemplary operation of a fractional-N synthesized chirp generator according to one aspect of the subject technology. A method is provided for generating a chirped radio frequency (RF) output signal. The method comprises receiving a reference frequency input signal (710), and generating a first frequency control value utilizing the reference frequency input signal (720). The first frequency control value varies with time.

The method further comprises generating a second frequency control value based on the first frequency control value (730). The second frequency control value includes a pseudo-random sequence. The second frequency control value has a frequency spectra content that is higher than a loop bandwidth defined by a frequency synthesizer. The frequency synthesizer comprises a voltage controlled oscillator. The voltage controlled oscillator does not follow an instantaneous value of the second frequency control value but rather follows a time-averaged value of the second frequency control value. The method further comprises generating a chirped radio frequency (RF) output signal utilizing the reference frequency input signal and the second frequency control value (740).

According to another aspect of the subject technology, a response rate of the voltage controlled oscillator is slower than a rate of change of the instantaneous value of the second frequency control value.

According to another aspect of the subject technology, the method further comprises selecting an upper frequency limit value or a lower frequency limit value based on a counter control value, producing a frequency limit value, and comparing the first frequency control value to the frequency limit value to produce a counter control value.

According to another aspect of the subject technology, the method further comprises selecting an up-chirp ramp rate or a down-chirp ramp rate based on a counter control value, producing a frequency ramp control value, and generating a counter clock frequency signal based on the reference frequency input signal and the frequency ramp control value. The first frequency control value is generated based on a counter control value and the counter clock frequency signal.

According to another aspect of the subject technology, the method further comprises selecting an up-chirp ramp rate or a down-chirp ramp rate based on a counter control value, producing a ramp control value, and generating an adder clock frequency signal based on the reference frequency input signal. The first frequency control value is generated based on the ramp control value and the adder clock frequency signal.

According to one aspect of the subject technology, a fractional-N synthesized chirp generator comprises a fractional-N synthesizer and a digital ramp synthesizer. The fractional-N synthesizer comprises a frequency synthesizer and a sigma-delta modulator module. The fractional-N synthesizer is configured to receive a reference frequency input signal and a frequency control value. The fractional-N synthesizer is configured to transform the reference frequency signal and the frequency control value to a chirped radio frequency (RF) output signal in a deterministic manner.

The digital ramp synthesizer is configured to receive the reference frequency input signal and configured to generate the frequency control value utilizing the reference frequency input signal. The digital ramp synthesizer is further configured to provide the frequency control value to the fractional-N synthesizer. The frequency control value varies with time.

According to another aspect of the subject technology, the frequency synthesizer comprises a phase detector, a charge pump coupled to the phase detector, a loop filter coupled to the charge pump, a voltage controlled oscillator coupled to the loop filter, and a frequency divider coupled to the phase detector and the voltage controlled oscillator. The fractional-N synthesizer is configured to generate the chirped RF output signal independent of a tuning curve of the voltage controlled oscillator.

According to another aspect of the subject technology, the sigma-delta modulator module comprises a sigma-delta modulator configured to receive one or more lower significant values of the frequency control value and the reference frequency input signal. The sigma-delta modulator is configured to transform the one or more lower significant values of the frequency control value to a second frequency control value utilizing a pseudo-random sequence. The second frequency control value represents a fractional count value when averaged over a time window.

According to another aspect of the subject technology, the sigma-delta modulator module further comprises a summation block configured to add the second frequency control value and one or more most significant values (N) of the frequency control value. The summation block is configured to produce a fractional-N frequency control value having a frequency spectra content that is higher than a loop bandwidth defined by the frequency synthesizer.

According to another aspect of the subject technology, the sigma-delta modulator module comprises a first integrator stage, a second integrator stage, a third integrator stage, a rounding block, and a summation block. The first integrator stage comprises a summation block and a register block. The first integrator stage is configured to receive one or more lower significant values of the frequency control value. The second integrator stage comprises a summation block, a register block, and a multiplier.

The third integrator stage comprises one or more summation blocks, a register block, and a pseudo-random bit sequence generator. The rounding block is configured to generate integer values. An output of the rounding block is coupled to the summation block of the first integrator stage, to the multiplier, and to one of the one or more summation blocks. A summation block is configured to receive the integer values and one or more most significant values (N) of the frequency control value and is configured to produce a second frequency control value.

According to another aspect of the subject technology, the digital ramp synthesizer comprises a ramp synthesizer block and a ramp controller block.

According to another aspect of the subject technology, the ramp synthesizer block comprises an up-chirp ramp rate block configured to provide an up-chirp ramp rate and a down-chirp ramp rate block configured to provide a down-chirp ramp rate. The ramp synthesizer block further comprises a selector configured to select the up-chirp ramp rate or the down-chirp ramp rate based on a counter control value. The selector is configured to produce a frequency ramp control value.

The ramp synthesizer block further comprises a frequency divider configured to receive the reference frequency input signal and the frequency ramp control value and is configured to produce a counter clock frequency signal based on the reference frequency input signal and the frequency ramp control value. The ramp synthesizer block further comprises an up/down counter configured to receive the counter control value, the counter clock frequency signal and an initial count value. The up/down counter is configured to produce the frequency control value.

According to another aspect of the subject technology, the up/down counter is configured to change the frequency control value at a rate determined by a frequency of the counter clock frequency signal and configured to change the frequency control value by a count increment amount at each time interval. The count increment amount is constant for a given mode of operation. The frequency control value increases in linear steps with time at a first rate determined by the frequency of the counter clock frequency signal during a first time period. The frequency control value decreases in linear steps with time at a second rate determined by the frequency of the counter clock frequency signal during a second time period. The first and second time periods are consecutive. The frequency of the counter clock frequency signal is at a constant value during the first time period, and the frequency of the counter clock frequency signal is at a constant value during the second time period.

According to another aspect of the subject technology, the ramp controller block comprises an upper frequency limit block configured to provide an upper frequency limit value, a lower frequency limit block configured to provide a lower frequency limit value, a selector configured to select the upper frequency limit value or the lower frequency limit value based on a counter control value. The selector is configured to produce a frequency limit value. The ramp controller block further comprises a compare logic block configured to receive the frequency limit value and the frequency control value. The compare logic block is configured to produce the counter control value.

According to another aspect of the subject technology, the ramp synthesizer block comprises an up-chirp ramp rate block configured to provide an up-chirp ramp rate, a down-chirp ramp rate block configured to provide a down-chirp ramp rate, a selector configured to select the up-chirp ramp rate or the down-chirp ramp rate based on a counter control value. The selector is configured to produce a ramp control value. The ramp synthesizer block further comprises a frequency divider configured to receive the reference frequency input signal and is configured to produce an adder clock frequency signal. The ramp synthesizer block further comprises an adder configured to receive the ramp control value, the adder clock frequency signal, and an initial count value. The adder is configured to produce the frequency control value.

According to another aspect of the subject technology, the adder is configured to change the frequency control value at each time interval determined by the adder clock frequency signal, and the adder is configured to change the frequency control value by an increment amount determined by the ramp control value.

According to another aspect of the subject technology, the fractional-N synthesizer is configured to generate a second frequency control value utilizing a pseudo-random sequence and at least a portion of the frequency control value. The second frequency control value has a frequency spectra content that is higher than a loop bandwidth defined by the frequency synthesizer.

According to another aspect of the subject technology, the frequency synthesizer comprises a voltage controlled oscillator configured to follow a time-averaged value of the second frequency control value and configured not to follow an instantaneous value of the second frequency control value. The frequency synthesizer further comprises and a frequency divider coupled to the voltage controlled oscillator. The frequency divider is configured to oscillate between multiple values of the second frequency control value. A response rate of the voltage controlled oscillator is slower than a rate of change of the instantaneous value of the second frequency control value.

According to another aspect of the subject technology, a one-to-one correspondence exists between the frequency control value and the frequency of the chirped RF output signal.

According to another aspect of the subject technology, the chirped RF output signal varies linearly with time. The chirped RF output signal increases linearly with time at a first rate during a first time period. The chirped RF output signal decreases linearly with time at a second rate during a second time period. The first and second time periods are consecutive.

According to another aspect of the subject technology, the first rate is equal to the second rate. According to another aspect of the subject technology, a transmitter integrated circuit comprises the fractional-N synthesized chirp generator.

Those of skill in the art would appreciate that various components and blocks may be arranged differently (e.g., arranged in a different order, or partitioned in a different way) all without departing from the scope of the subject technology. It is understood that the specific order or hierarchy of steps in the processes disclosed is an illustration of exemplary approaches. Based upon design preferences, it is understood that the specific order or hierarchy of steps in the processes may be rearranged. Some of the steps may be performed simultaneously. The accompanying method claims present elements of the various steps in a sample order, and are not meant to be limited to the specific order or hierarchy presented.

A phrase such as an “aspect” does not imply that such aspect is essential to the subject technology or that such aspect applies to all configurations of the subject technology. A disclosure relating to an aspect may apply to all configurations, or one or more configurations. A phrase such as an “embodiment” does not imply that such embodiment is essential to the subject technology or that such embodiment applies to all configurations of the subject technology. A disclosure relating to an embodiment may apply to all embodiments, or one or more embodiments.