Electronic device and method for fabricating the same

An electronic device including a semiconductor memory includes a plurality of first electrodes and a plurality of second electrodes, which are disposed over a substrate and alternately arrayed in a first direction that is parallel to a plane of the substrate; and a plurality of resistance variable patterns, each of which is interposed between a corresponding one of the first electrodes and a corresponding one of the second electrodes, wherein the first and second electrodes and the resistance variable patterns extend upwards by a predetermined height from the substrate.

CROSS-REFERENCE TO RELATED APPLICATIONS

The present application claims priority of Korean Patent Application No. 10-2013-0134788, entitled “ELECTRONIC DEVICE AND METHOD FOR FABRICATING THE SAME” and filed on Nov. 7, 2013, which is incorporated herein by reference in its entirety.

TECHNICAL FIELD

Embodiments of the present invention relates to electronic devices or systems including a memory device, and a method for fabricating the same.

BACKGROUND

As electronic appliances become smaller, semiconductor devices that have low power consumption, high performance, multi-functionality, and so on, are increasingly in demand. Semiconductor devices are devices that store information and are utilized in various electronic appliances such as computers, portable communication devices, and so on. Such semiconductor devices store data using a characteristic switching between different resistance states according to a voltage or current applied thereto. For example, semiconductor devices include resistive random access memory (RRMA) devices, phase change random access memory (PRAM) devices, ferroelectric random access memory (FRAM) devices, magnetic random access memory (MRAM) devices, E-fuses, etc.

SUMMARY

Embodiments of the present invention relate to a memory device, an electronic device including the same, and a method of fabricating the same, which has a high degree of integration. Embodiments also relate to a memory device, an electronic device including the same, and a method of fabricating the same, which has uniform cell characteristics and simplified fabrication process.

In one aspect, an electronic device including a semiconductor memory unit that includes: a plurality of first electrodes and a plurality of second electrodes stretched in a direction perpendicular to a substrate over the substrate and alternately arrayed in a first direction that is in parallel to the substrate; and a plurality of resistive variable patterns interposed between the first electrodes and the second electrodes in the first direction and stretched in the direction perpendicular to the substrate.

In another aspect, an electronic device including a semiconductor memory unit that includes: a plurality of first electrodes and a plurality of second electrodes, which are disposed over a substrate and alternately arrayed in a first direction that is parallel to a plane of the substrate; and a plurality of resistance variable patterns, each of which is interposed between a corresponding one of the first electrodes and a corresponding one of the second electrodes, wherein the first and second electrodes and the resistance variable patterns extend upwards by a predetermined height from the substrate.

Implementations of the above devices may include one or more of the following.

Upper surfaces of the first electrodes, the resistive variable patterns, and the second electrodes are positioned at the same level, and lower surfaces of the first electrodes and the resistive variable patterns are disposed below lower surfaces of the second electrodes. The semiconductor memory unit further comprises first insulation patterns disposed under the second electrodes. Each of the resistive variable patterns includes a plurality of layers which have resistive variable characteristics in combination, and a lowermost portion of a remaining layer other than a first layer that contacts the second electrodes among the plurality of layers has a shape of being bent toward the second electrodes in a direction parallel to the substrate, and the first insulation patterns cover at least the lowermost portion of the remaining layer. Each of the resistive variable patterns include an oxygen-rich metal oxide layer and an oxygen-deficient metal oxide layer, the oxygen-rich metal oxide layer and the oxygen-deficient metal oxide layer are stretched in the direction perpendicular to the substrate at least between the first electrodes and the second electrodes. Upper surfaces of the first electrodes, the resistive variable patterns and the second electrodes are positioned at the same level, and lower surfaces of the first electrodes, the resistive variable patterns and the second electrodes are positioned at the same level.

A cell structure includes the first electrodes, the second electrodes, and the resistive variable patterns that are arrayed in the first direction, and the cell structure is provided in plural and plural cell structures are arrayed to be spaced out from each other in a second direction that is parallel to the substrate and intersects with the first direction, and the first electrodes are arrayed in one row in the second direction, and the second electrodes are arrayed in one row in the second direction, and the resistive variable patterns are arrayed in one row in the second direction. Wherein the semiconductor memory unit further comprises first lines stretched in the first direction and electrically connected to the first electrodes that are arrayed in the first direction; and second lines stretched in the second direction and electrically connected to the second electrodes that are arrayed in the second direction, wherein ones between the first lines and the second lines are disposed over the cell structure and the others are disposed under the cell structure. Each of a first stack structure and a second structure includes the plural cell structures, and the first stack structure and the second structure are stacked in the direction perpendicular to the substrate. The semiconductor memory unit further comprises first lines stretched in the first direction under the first stack structure and electrically connected to the first electrodes that are included in the first stack structure and arrayed in the first direction; second lines stretched in the second direction between the first stack structure and the second stack structure, and electrically connected to the second electrodes that are included in the first stack structure and arrayed in the second direction and the second electrodes that are included in the second stack structure and arrayed in the second direction; and third lines stretched in the first direction over the second stack structure and electrically connected to the first electrodes that are included in the second stack structure and arrayed in the first direction. The semiconductor memory unit further comprises first lines stretched in the second direction under the first stack structure and electrically connected to the first electrodes that are included in the first stack structure and arrayed in the second direction; second lines stretched in the first direction between the first stack structure and the second stack structure, and electrically connected to the second electrodes that are included in the first stack structure and arrayed in the first direction and the second electrodes that are included in the second stack structure and arrayed in the first direction; and third lines stretched in the second direction over the second stack structure and electrically connected to the first electrodes that are included in the second stack structure and arrayed in the second direction.

Alternately, a cell structure includes the first electrodes, the second electrodes, the first insulation patterns under the second electrodes, and the resistive variable patterns that are arrayed in the first direction, and the cell structure is provided in plural and plural cell structures are arrayed to be spaced out from each other in a second direction that is parallel to the substrate and intersects with the first direction, and the first electrodes are arrayed in one row in the second direction, and the second electrodes are arrayed in one row in the second direction, and the resistive variable patterns are arrayed in one row in the second direction. Wherein the semiconductor memory unit further comprises first lines stretched in the first direction under the cell structure and electrically connected to the first electrodes that are arrayed in the first direction; and second lines stretched in the second direction over the cell structure and electrically connected to the second electrodes that are arrayed in the second direction. The semiconductor memory unit further comprises first lines stretched in the second direction under the cell structure and electrically connected to the first electrodes that are arrayed in the second direction; and second lines stretched in the first direction over the cell structure and electrically connected to the second electrodes that are arrayed in the first direction. Each of a first stack structure and a second structure includes the plural cell structures, and the first stack structure and the second structure are stacked in the direction perpendicular to the substrate. The first electrodes of the first stack structure overlap the second electrodes of the second stack structure in the first direction, and the second electrodes of the first stack structure overlap the first electrodes of the second stack structure in the first direction. The semiconductor memory unit further comprises first lines stretched in the first direction under the first stack structure and electrically connected to the first electrodes that are included in the first stack structure and arrayed in the first direction; second lines stretched in the second direction between the first stack structure and the second stack structure, and electrically connected to the second electrodes that are included in the first stack structure and arrayed in the second direction and the second electrodes that are included in the second stack structure and arrayed in the second direction; and third lines stretched in the first direction over the second stack structure and electrically connected to the second electrodes that are included in the second stack structure and arrayed in the first direction. The semiconductor memory unit further comprises first lines stretched in the second direction under the first stack structure and electrically connected to the first electrodes that are included in the first stack structure and arrayed in the second direction; second lines stretched in the first direction between the first stack structure and the second stack structure, and electrically connected to the second electrodes that are included in the first stack structure and arrayed in the first direction and the first electrodes that are included in the second stack structure and arrayed in the first direction; and third lines stretched in the second direction over the second stack structure and electrically connected to the second electrodes that are included in the second stack structure and arrayed in the second direction.

The semiconductor memory unit further comprises a plurality of selectors that are interposed between the first electrodes and the resistive variable patterns or between the second electrodes and the resistive variable patterns in the first direction and stretched in the direction perpendicular to the substrate.

The electronic device may further include a microprocessor which includes: a control unit configured to receive a signal including a command from an outside of the microprocessor, and performs extracting, decoding of the command, or controlling input or output of a signal of the microprocessor; an operation unit configured to perform an operation based on a result that the control unit decodes the command; and a memory unit configured to store data for performing the operation, data corresponding to a result of performing the operation, or an address of data for which the operation is performed, wherein the semiconductor memory unit is part of the memory unit in the microprocessor.

The electronic device may further include a processor which includes: a core unit configured to perform, based on a command inputted from an outside of the processor, an operation corresponding to the command, by using data; a cache memory unit configured to store data for performing the operation, data corresponding to a result of performing the operation, or an address of data for which the operation is performed; and a bus interface connected between the core unit and the cache memory unit, and configured to transmit data between the core unit and the cache memory unit, wherein the semiconductor memory unit is part of the cache memory unit in the processor.

The electronic device may further include a processing system which includes: a processor configured to decode a command received by the processor and control an operation for information based on a result of decoding the command; an auxiliary memory device configured to store a program for decoding the command and the information; a main memory device configured to call and store the program and the information from the auxiliary memory device such that the processor can perform the operation using the program and the information when executing the program; and an interface device configured to perform communication between at least one of the processor, the auxiliary memory device and the main memory device and the outside, wherein the semiconductor memory unit is part of the auxiliary memory device or the main memory device in the processing system.

The electronic device may further include a data storage system which includes: a storage device configured to store data and conserve stored data regardless of power supply; a controller configured to control input and output of data to and from the storage device according to a command inputted form an outside; a temporary storage device configured to temporarily store data exchanged between the storage device and the outside; and an interface configured to perform communication between at least one of the storage device, the controller and the temporary storage device and the outside, wherein the semiconductor memory unit is part of the storage device or the temporary storage device in the data storage system.

The electronic device may further include a memory system which includes: a memory configured to store data and conserve stored data regardless of power supply; a memory controller configured to control input and output of data to and from the memory according to a command inputted form an outside; a buffer memory configured to buffer data exchanged between the memory and the outside; and an interface configured to perform communication between at least one of the memory, the memory controller and the buffer memory and the outside, wherein the semiconductor memory unit is part of the memory or the buffer memory in the memory system.

In another aspect, a method for fabricating an electronic device including a semiconductor memory unit includes: forming a plurality of first conductive patterns stretched in a second direction over a substrate and arrayed in a first direction to be spaced out from each other; forming a material layer pattern having resistive variable characteristics on sidewalls of each first conductive pattern; forming second conductive patterns each of which fills a space between the first conductive patterns where the material layer patterns are formed; and selectively etching the first conductive patterns, the material layer patterns, and the second conductive patterns in such a manner that the first conductive patterns, the material layer patterns, and the second conductive patterns are divided into more than two parts in the second direction.

In another aspect, a method for fabricating an electronic device including a semiconductor memory unit includes: forming a plurality of first conductive patterns that extends in a second direction over a substrate, each of the first conductive patterns being arrayed in a first direction and spaced apart from each other, the first direction crossing the second direction; forming a plurality of material layer patterns having resistance variable characteristics on sidewalls of the first conductive patterns; forming a plurality of second conductive patterns each of which fills a space between two neighboring material layer patterns; and dividing the first conductive patterns, the material layer patterns, and the second conductive patterns into two or more parts arrayed in the second direction by forming a trench between each of the parts, the trench extending in the first direction.

Implementations of the above methods may include one or more the following.

The method further comprises forming first insulation patterns each of which fills a lower portion of the space, before the forming of the second conductive patterns. The forming of the material layer pattern comprises forming a plurality of material layers conformally over the substrate where the first conductive patterns are formed, wherein the plurality of material layers have resistive variable characteristics in combination; and performing a blanket etch process on the material layers until upper surfaces of the first conductive patterns and the substrate are exposed.

These and other aspects, implementations and associated advantages will become apparent in view of the drawings and the description of embodiments provided herein, which are intended to provide further explanation of the invention as claimed.

DETAILED DESCRIPTION

Embodiments of the present disclosure are described with reference to the accompanying drawings.

FIG. 1is a perspective view illustrating a semiconductor device in accordance with a first embodiment of the present disclosure.

Referring toFIG. 1, the semiconductor device includes a plurality of first electrodes110A, a plurality of second electrodes140A, and resistance variable patterns120B. The first electrodes110A and the second electrodes140A are disposed over a substrate (not shown) and extend upwards from the substrate. The first electrode110A and the second electrode140A are alternately arrayed in a first direction that is parallel to a plane of the substrate. Each of the resistance variable patterns120B is interposed between a first electrode110A and a second electrode140A.

The first electrode110A and the second electrode140A each contact a side of the resistance variable pattern120B and supply a voltage or current to the resistance variable pattern120B. Any of the first electrodes110A and the second electrodes140A may be formed of a conductive layer such as a metal layer, a metal nitride layer, a polysilicon layer doped with an impurity, or a combination thereof.

The resistance variable patterns120B may be formed of a material having a resistance level that changes depending on a level of a voltage or current applied thereto. For example, the resistance variable patterns120B may be formed of at least one of diverse materials used for an RRAM device, a PRAM device, a FRAM device, an MRAM device, and so forth. Such materials include metal oxide such as transition metal oxide and a perovskite-based material, a phase-change material such as a chalcogenide-based material, a ferroelectric material, and a ferromagnetic material. The resistance variable patterns120B may have a single-layer structure or a multi-layer structure.

One memory cell may be formed of one first electrode110A, one second electrode140A, and one resistance variable pattern120B interposed between the first electrode110A and the second electrode140A. For example, the first electrode110A and the second electrode140A on both sides of the resistance variable pattern120B form a first memory cell MCl. Accordingly, a plurality of memory cells may be arrayed in series along the first direction. The first electrodes110A, the resistance variable patterns120B, and the second electrodes140A, which are arrayed in the first direction, are referred to as cell structures CSs, hereafter.

Upper surfaces of the first electrode110A, the resistance variable pattern120B, and the second electrode140A may be positioned at the same level. In other words, the first electrode110A, the resistance variable pattern120B, and the second electrode140A may extend to substantially the same height from the substrate.

On the other hand, lower surfaces of the first electrode110A, the resistance variable pattern120B, and the second electrode140A may be positioned at different levels. In an embodiment, the lower surface of the first electrode110A and the lower surface of the resistance variable pattern120B may be positioned lower than the lower surface of the second electrode140A. Under the second electrode140A is a first insulation pattern130B filling a space between the second electrode140A and the substrate. In short, an upper surface of the first insulation pattern130B contacts the lower surface of the second electrode140A, and the lower surface of the first insulation pattern130B may be positioned at the same level as those of the lower surfaces of the first electrode110A and the resistance variable pattern120B. The first insulation pattern130B is interposed between the second electrode140A and the substrate due to a layer structure of the resistance variable pattern120B, which will be described in detail below. According to another embodiment, the first insulation pattern130B is omitted (refer toFIGS. 3A and 3B).

As mentioned above, the resistance variable pattern120B may have a multi-layer structure including two or more layers. The two or more layers, in combination, have resistance variable characteristics. In an embodiment, the resistance variable pattern120B has a dual-layer structure including a first resistance variable layer122B and a second resistance variable layer124B. One of the first resistance variable layer122B and the second resistance variable layer124B may be formed of an oxygen-deficient metal oxide material, and the other may be formed of an oxygen-rich metal oxide material.

The oxygen-rich metal oxide material may include a material that satisfies a stoichiometric ratio, such as titanium oxide (TiO2) or tantalum oxide (Ta2O5). The oxygen-deficient metal oxide material may include a material having a less oxygen content than the oxygen-rich metal oxide material, such as titanium oxide (TiOx), x being smaller than 2 (x<2), or tantalum oxide (TaOy), y being smaller than 2.5 (y<2.5).

In an embodiment, the resistance state of the resistance variable pattern120B may change between a high resistance level and a low resistance level according to whether or not oxygen vacancies of the oxygen-deficient metal oxide layer are supplied to the oxygen-rich metal oxide layer as a result of the voltage applied from the first electrode110A and the second electrode140A to the resistance variable pattern120B. Thus, a filament current path is formed in the oxygen-rich metal oxide layer by the oxygen vacancies. The filament current path may be formed in a direction parallel to a surface of the substrate to couple the first electrode110A and the second electrode140A.

In the resistance variable pattern120B having the dual-layer structure described above, the lowermost portion of the first resistance variable layer122B may have a portion bent towards the second electrode140A to be parallel to a surface of the substrate (refer to a circled region ‘B’). That is, the first resistance variable layer122B may have a portion that extends laterally below the second resistance variable layer124B toward the second electrode140A. This is due to characteristics of a subsequent etch process, which will be described with reference toFIG. 2Blater.

The second resistance variable layer124B may be positioned over the bent portion of the first resistance variable layer122B. The upper surface of the first insulation pattern130B may be positioned at a higher level than the bent portion of the first resistance variable layer122B, so that the bent portion of the first resistance variable layer122B does not contact the second electrode140A. As described above, the resistance variable pattern120B have a shape that extends upwards by a predetermined height from the substrate, and is provided at least between the first electrode110A and the second electrode140A.

In an embodiment, if the first insulation pattern130B is omitted, that is, if the lower surface of the second electrode140A is positioned at substantially the same level as that of the lower surface of the first electrode110A, the second electrode140A may contact not only the second resistance variable layer124B, but also the bent portion of the first resistance variable layer122B. This may cause a problem in a normal switching operation of a memory cell. However, as shown inFIG. 1, if the first insulation pattern130B is formed to cover at least the lowermost portion of the resistance variable pattern120B, it is possible to prevent the bent portion of the first resistance variable layer122B from causing a problem in a normal switching operation.

This may be true not only for a resistance variable pattern120B having a dual-layer structure, but also for a resistance variable pattern having a multi-layer structure of three or more layers. In a multi-layer structure, the layers that are not in contact with the second electrode140A may have lowermost portions that are bent toward the second electrode140A due to an etch process. The first insulation pattern130B may be formed to fully cover the bent portions of these layers so that they do not contact the second electrode140A. As a result, since all the multiple layers of the resistance variable pattern120B may extend upwards by a predetermined height from the substrate100between the first electrode110A and the second electrode140A, upper surfaces of the first electrode110A, the second electrode140A, and the resistance variable pattern120B are provided at substantially the same level over the substrate100. Thus, a memory cell may obtain its operational characteristics.

In an embodiment, the above-described cell structure CS is iteratively arrayed in a second direction, which crosses the first direction.FIG. 1illustrates two cell structures CS each extending in the first direction, and the cell structures CS that are iteratively arrayed in the second direction with a second insulation pattern150provided between the cell structures arrayed in the second direction. That is, the second insulation pattern150extends in the first direction and is interposed between two neighboring cell structures CS to isolate the cell structures CS from each other. Thus, the first electrodes110A included in each cell structure CS are arrayed in series in the second direction. Similarly, the resistance variable patterns120B and the second electrodes are also arrayed in series in the second direction.

FIGS. 2A to 2Eare cross-sectional views illustrating a method for fabricating the semiconductor device shown inFIG. 1. In each ofFIGS. 2A to 2E, a left portion shows a cross-sectional view taken along the line A-A′ ofFIG. 1, and a right portion shows a cross-sectional view taken along the line B-B′ ofFIG. 1.

Referring toFIG. 2A, a conductive material is deposited on a substrate100including a predetermined lower structure (not shown), and then the conductive material is patterned so that a plurality of first conductive patterns110is formed in a shape of lines extending in the second direction. The first conductive patterns110are arrayed to be spaced apart from each other in the first direction.

Subsequently, a material layer120having variable resistance characteristics is formed over a resultant structure, including the first conductive patterns110. The material layer120includes a first material layer122and a second material layer124. The first material layer122is formed over the resultant structure, and the second material layer124is formed over the first material layer122. The first material layer122and the second material layer124together show the variable resistance characteristics. In an embodiment, one of the first material layer122and the second material layer124includes an oxygen-rich metal oxide layer, and the other includes an oxygen-deficient metal oxide layer.

Referring toFIG. 2B, a material layer pattern120A is formed on each sidewall of each first conductive pattern110by performing a blanket etch process on the material layer120until upper surfaces of the first conductive patterns110and the substrate100are exposed. The material layer patterns120A extend in the second direction, like the first conductive patterns110. The material layer pattern120A includes a first material layer pattern122A and a second material layer pattern124A, which are formed by the blanket etch process. In the material layer pattern120A, the first material layer pattern122A is formed to have the lowermost portion that is bent in a direction away from the first conductive pattern110. That is, the first material layer pattern122A covers one side and the bottom of the second material layer pattern124A.

Subsequently, an insulation material130is deposited over a resultant structure, including the material layer pattern120A, to fill the space between the first conductive patterns110where the material layer pattern120A is formed. The insulation material130has excellent gap-filling characteristics and may include a Spin-On-Dielectric (SOD) substance.

Referring toFIG. 2C, insulation patterns130A are formed to fill a portion of the space between the first conductive patterns110after the material layer pattern120A is formed. The insulation pattern130A is formed to cover the bent portion of the first material layer pattern122A, and is formed by removing a portion of the insulation material130through a Chemical Mechanical Polishing (CMP) process, an etch-back process, or a combination thereof. The insulation patterns130A may include line shapes extending in the second direction.

Referring toFIG. 2D, second conductive patterns140are formed to fill the space between the first conductive patterns110after the material layer pattern120A and the insulation patterns130A are formed. The second conductive patterns140are formed by depositing a conductive material over a structure resulting from the process ofFIG. 2C, and planarizing the deposited conductive material through a CMP process until the upper surfaces of the first conductive patterns110are exposed. The second conductive patterns140may include line shapes extending in the second direction.

After that, one or more trenches are formed to extend in the first direction while penetrating through the first conductive patterns110, the material layer patterns120A, the insulation patterns130A, and the second conductive patterns140by selectively etching the first conductive patterns110, the material layer patterns120A, the insulation patterns130A, and the second conductive patterns140. As a result, the first conductive pattern110, the material layer pattern120A, the insulation pattern130A, and the second conductive pattern140are separated into two or more parts in the second direction.

InFIG. 2E, one trench is formed, and accordingly, the first conductive pattern110, the material layer pattern120A, the insulation pattern130A, and the second conductive pattern140are divided into two parts in the second direction. However, embodiments of the present disclosure are not limited thereto. In another embodiment, the first conductive pattern110, the material layer pattern120A, the insulation pattern130A, and the second conductive pattern140are divided into more than two parts in the second direction according to the number of the trenches. As a result of the dividing process, the first electrodes110A, the resistance variable patterns120B, the first insulation patterns130B, and the second electrodes140A are formed. The first electrodes110A, the resistance variable patterns120B, the first insulation patterns130B, and the second electrodes140A correspond to the first conductive patterns110, the material layer patterns120A, the insulation patterns130A, and the second conductive patterns140, respectively.

Subsequently, the second insulation pattern150is formed by filling the trench with an insulation material such as oxide or nitride. As a result, a semiconductor device in accordance with an embodiment as illustrated inFIG. 1is obtained.

The embodiment ofFIGS. 1 to 2Edescribed above has the following advantages.

First of all, in the above-described embodiment, a plurality of memory cells in a cell structure CS is arrayed in the first direction, and a mask process, which is an essential process for forming a memory cell array, is required only one time to form the memory cell array. For example, the resistance variable patterns120B and the second electrodes140A are formed in a process of filling the space between the first electrodes110A without performing an additional mask process. Moreover, since the first electrodes110A, the resistance variable patterns120B, and the second electrodes140A are alternate laterally in a pattern across a surface of the substrate100and extend vertically from the substrate100to form a single vertical layer comprised of a plurality of parts, it is easy to perform an etch process to form the first electrodes110A, the resistance variable patterns120B, and the second electrodes140A. As a result, a process for fabricating a semiconductor device is simplified. Furthermore, it is possible to realize a highly integrated memory device through the simplified fabricating process.

In addition, a desired etch profile may be easily obtained according to the above-described processes, and thus the shapes of the first electrodes110A, the resistance variable patterns120B, and the second electrodes140A may be uniformly formed. As a result, it is possible to obtain uniformity in the characteristics of multiple memory cells.

Furthermore, although the resistance variable patterns120B are of a multi-layer structure, it is possible to obtain switching characteristics.

FIG. 3Ais a perspective view illustrating a semiconductor device in accordance with a second embodiment of the present disclosure, andFIG. 3Bis a cross-sectional view illustrating a semiconductor device in accordance with a third embodiment of the present disclosure. Hereafter, a description of the second and third embodiments will focus on differences from the first embodiment illustrated inFIG. 1.

Referring toFIG. 3A, the semiconductor device includes a plurality of first electrodes310, a plurality of second electrodes340, and resistance variable patterns320. The first electrodes310and the second electrodes340are disposed over a substrate (not shown) and extend upwards from the substrate to a predetermined height. The first electrode310and the second electrode340are alternately arrayed in a first direction that is parallel to a plane of the substrate. Each of the resistance variable patterns320is interposed between a first electrode310and a second electrode340.

In the embodiment shown inFIG. 3A, the resistance variable pattern320has a single-layer structure extending upwards by a predetermined height from the substrate. A second insulation pattern350is formed to isolate neighboring cell structures from each other in the second direction.

In another embodiment, the resistance variable pattern320may have a multi-layer structure, and each of the multiple layers extends upwards by a predetermined height from the substrate. However, each of the multiple layers does not have a bent portion, unlike the first resistance variable layer122B of the resistance variable pattern120B. In other words, all of the layers of the multi-layer structure that form the resistance variable pattern320between the first electrode310and the second electrode340are straight and extend upwards from the substrate by a predetermined height from the substrate. This embodiment is illustrated inFIG. 3B.

Referring toFIG. 3B, the resistance variable pattern320is formed to have a dual-layer structure that includes a first material layer pattern322and a second material layer pattern324. The first material layer pattern322is formed on each sidewall of each of the first electrodes310by forming a first material layer over a resultant structure after the formation of the first electrodes310and performing a blanket etch process on the first material layer. Subsequently, the second material layer pattern324is formed on an exposed sidewall of the first material layer pattern322by forming a second material layer over a resultant structure after the formation of the first material layer pattern322, and then performing a blanket etch process on the second material layer. When the second material layer patterns324are formed in this way, the first material layer patterns322may not contact the second electrodes340, each of which is buried in a trench region between two adjacent second material layer patterns324.

In this embodiment, the first insulation patterns130B shown inFIG. 1are omitted, and the first electrodes310, the resistance variable patterns320′, and the second electrodes340are all positioned at the same level. Upper and lower surfaces of the first electrodes310, the resistance variable patterns320′, and the second electrodes340may be positioned to have substantially the same height from the substrate.

In an embodiment of the present disclosure, the first electrodes110A (or310) and the second electrodes140A (or340) are electrically connected to lines, e.g., voltage supplying lines through which an operating voltage for performing an operation of a memory cell is supplied. The lines may be realized in diverse forms. In an embodiment, the lines are formed as shown inFIGS. 4A to 5to achieve high integration and simplify a fabricating process.

FIG. 4Ais a perspective view illustrating a semiconductor device including voltage supplying lines in accordance with an embodiment of the present disclosure, andFIG. 4Bis a cross-sectional view illustrating the semiconductor device ofFIG. 4Ataken along a line in the first direction.FIGS. 4A and 4Billustrate a cell structure that is substantially the same as that of the semiconductor device shown inFIG. 1. However, embodiments are not limited thereto. Voltage supplying lines may be connected to a cell structure having a different configuration. For example, in another embodiment, the voltage supplying lines shown inFIGS. 4A and 4Bmay be connected to the cell structure shown in any ofFIGS. 3A and 3B.

Referring toFIGS. 4A and 4B, first lines420extending in a first direction are disposed under cell structures, which correspond to the cell structures CS shown inFIG. 1. A plurality of first electrodes110A in each cell structure CS is electrically connected to a corresponding one of the first lines420. In particular, each of the first electrodes110A is electrically connected to a first line420through a corresponding one of the first contacts410, which are respectively coupled to the first electrodes110A and disposed under the first electrodes110A.

Disposed over the cell structures CS are second lines440, which extend in a second direction. Second electrodes140A that are iteratively arrayed to form two or more cell structures CS along one straight line extending in the second direction may be referred to as a column of the second electrodes140A. A column of the second electrodes140A is electrically coupled to a corresponding one of the second lines440. Particularly, each of the second electrodes140A in the column is electrically coupled to the corresponding second line440through a corresponding one of second contacts430, which are respectively coupled to the second electrodes140A and disposed over the second electrodes140A.

The first contacts410, the first lines420, the second contacts430, and the second lines440may be formed of any conductive material, including metal, a metallic material such as metal nitride, and so on. The space between the first lines420and the first contacts410and the space between the second contacts430and the second lines440may be filled with an insulating substance, which is not illustrated in the drawings.

In the semiconductor device shown inFIGS. 4A and 4B, when a read operation for reading data stored in a first memory cell MC1is performed or when a program operation for programming data in the first memory cell MC1is performed, a required operating voltage is applied to the first line420and the second line440, which are respectively coupled to the first electrode110A and the second electrode140A of the first memory cell MC1. As a result, a current flow may be generated through the first memory cell MC1between the second line440and the first line420as shown inFIG. 4B. The other first lines420and the other second lines440that are not coupled to the first memory cell MC1may be in a floating state or may receive a predetermined voltage such as a ground voltage.

According to an embodiment, as shown inFIGS. 4A and 4B, since the first lines420and the second lines440are disposed under or over the cell structures CS, memory cells in the cell structures CS may be easily controlled without affecting a degree of integration of the semiconductor device. Also, since the first and second contacts410and430and the first and second lines420and440are formed in an iterative form, a fabricating process of the semiconductor device becomes simple. Furthermore, since the first lines420and the second lines440are respectively disposed under and over the cell structures CS, a short circuit between the first contacts410and the second contacts430may be prevented.

Meanwhile, in accordance with an embodiment as shown inFIGS. 4A and 4B, the first lines420are coupled to the first electrodes110A under the cell structures CS and the second lines440are coupled to the second electrodes140A over the cell structures CS due to the presence of the first insulation patterns130B under the second electrodes140A. However, in another embodiment, if the first insulation patterns130B are omitted, for example, as illustrated inFIG. 3, the positions of the first lines420and the second lines440may be switched. That is, the first lines420may be disposed over the cell structures CS, and the second lines440may be disposed under the cell structures CS.

In another embodiment, the directions of the first lines420and the second lines440may be changed as long as the first lines420and the second lines440cross each other, as illustrated, for example, inFIG. 5.

FIG. 5is a cross-sectional view illustrating a semiconductor device including voltage supplying lines in accordance with another implementation of the present disclosure.

Referring toFIG. 5, first lines420′ are formed to extend in a second direction under cell structures CS. A column of the first electrodes110A iteratively arrayed to form two or more cell structures CS is electrically coupled to a corresponding one of the first lines420′.

Also, second lines440′ are formed to extend in a first direction over the cell structures CS. A column of the second electrodes140A arrayed in the first direction is electrically coupled to a corresponding one of the second lines440′.

Since an operation of a memory cell shown inFIG. 5is substantially the same as that of the memory cell MC1shown inFIGS. 4A and 4B, a detailed description thereof is not provided herein for the simplicity of explanation.

In this embodiment, the first lines420′ are coupled to the first electrodes110A under the cell structures CS, and the second lines440′ are coupled with the second electrodes140A over the cell structures CS due to the presence of the first insulation patterns130B under the second electrodes140A. However, in another embodiment, if the first insulation patterns130B are omitted, for example, as illustrated inFIG. 3, positions of the first lines420′ and the second lines440′ may be switched. That is, the first lines420′ may be disposed over the cell structures CS, and the second lines440′ may be disposed under the cell structures CS.

In another embodiment, any structure ofFIGS. 1, 3A, and 3Bmay be stacked two or more times in a vertical direction. This will be described with reference toFIG. 6.

FIG. 6is a cross-sectional view illustrating a semiconductor device including a stacked cell structure in accordance with an embodiment of the present disclosure.

Referring toFIG. 6, each of a first stack structure ST1and a second stack structure ST2includes a cell structure in accordance with an embodiment.FIG. 6illustrates a cell structure that is substantially the same as the cell structure illustrated inFIG. 1, but embodiments are not limited thereto. The first stack structure ST1includes a first cell structure CS1, and the second stack structure ST2includes a second cell structure CS2.

First electrodes110A of the first stack structure ST1are electrically connected through first contacts410to first lines420that are disposed under the first cell structure CS1and extend in a first direction. Second electrodes140A of the first stack structure ST1are electrically connected through second contacts430to second lines440that are disposed over the first cell structure CS1and extend in a second direction.

The second stack structure ST2shares the second lines440with the first stack structure ST1. Thus, first electrodes210A of the second stack structure ST2are electrically connected through third contacts630to the second lines440that are disposed under the second cell structure CS2. Second electrodes240A of the second stack structure ST2are electrically connected through fourth contacts610to third lines620that are disposed over the second cell structure CS2and extend in the first direction.

As described above, the first electrodes110A and210A are electrically connected to the lines under the cell structures CS1and CS2, respectively, due to the presence of first insulation patterns130B and230B. However, since the second lines440, which are coupled to the first electrodes210A of the second stack structure ST2, are also coupled to the second electrodes140A of the first stack structure ST1, the first electrodes210A of the second stack structure ST2and the second electrodes140A of the first stack structure ST1may be aligned. That is the first electrodes210A and the second electrodes140A may be parallel to and overlap with each other. In addition, the second electrodes240A of the second stack structure ST2and the first electrodes110A of the first stack structure ST1may be aligned to be parallel to and overlap with each other.

To be specific, the first electrodes110A and the second electrodes140A of the first stack structure ST1and the first electrodes210A and the second electrodes240A of the second stack structure ST2, respectively, alternate with each other in the first direction. When it is assumed that the first electrodes110A and the second electrodes140A of the first stack structure ST1are in odd-numbered positions and even-numbered positions, respectively, in the first direction, the first electrodes210A and the second electrodes240A of the second stack structure ST2are in even-numbered positions and odd-numbered positions, respectively, in the first direction.

AlthoughFIG. 6shows a case where the cell structure ofFIG. 1is stacked two times, embodiments are not limited thereto. In another embodiment, the cell structure ofFIG. 1may be stacked more than two times. If a third stack structure (not shown) is disposed over the second stack structure ST2, the third stack structure may have substantially the same configuration as that of the first stack structure ST1, except for the first lines420. For the third stack structure, the first lines420may be substituted with the third lines620. Similarly, if a fourth stack structure (not shown) is stacked over the third stack structure, the fourth stack structure may have substantially the same configuration as that of the second stack structure ST2. Other stack structures may be stacked in the same manner as described above.

AlthoughFIG. 6shows that the first lines420and the third lines620extend in the first direction while the second lines440extend in the second direction, the directions in which these lines extend may be reversed. That is, the first lines420and the third lines620may extend in the second direction while the second lines440may extend in the first direction.

Also, althoughFIG. 6shows that the cell structure ofFIG. 1is stacked two times, it is possible to stack the cell structure ofFIG. 3A or 3Btwo or more times according to another embodiment. If the cell structure ofFIG. 3A or 3Bis stacked two or more times, the second electrodes340of the cell structure ofFIG. 3may be coupled with any of lines over the cell structure or lines under the cell structure since the cell structure ofFIG. 3does not include an insulation pattern such as the first insulation patterns130B inFIG. 1. Thus, if a first stack structure and a second stack structure, which include the cell structure ofFIG. 3, are vertically stacked, first electrodes of the first stack structure can be aligned with the first electrodes of the second stack structure so that they are parallel to and overlap with first electrodes of the second stack structure. In addition, second electrodes of the first stack structure can be aligned with second electrodes of the second stack structure so that they are parallel to and overlap with second electrodes of the second stack structure.

In another embodiment, the semiconductor devices described above may further include a selection unit interposed between electrodes and resistance variable patterns to supply a current to the resistance variable patterns. This will be described with reference toFIGS. 7A to 8.

FIGS. 7A and 7Bare cross-sectional views illustrating semiconductor devices in accordance with fourth and fifth embodiments of the present disclosure, respectively. Each of the semiconductor devices shown inFIGS. 7A and 7Bincludes a selection unit.

Referring toFIG. 7A, a selection layer126is interposed between a second electrode140A and a resistance variable pattern120B. The selection layer126extends upwards by a predetermined height from a substrate.

In an embodiment, since the selection layers126are formed of a material having non-linear current-voltage characteristics, a current scarcely flows through the selection layers126under a predetermined threshold voltage, but may flow through the selection layers126at a voltage level that is equal to or higher than the predetermined threshold voltage. The selection layers126may include any of diodes, transistors, varistors, MIT (Metal-Insulator Transition) devices, tunneling barriers, and so forth.

The selection layers126may be formed by, after depositing a first material layer and a second material layer for forming the resistance variable patterns120B, depositing a third material layer for forming the selection layers126over the second material layer, and performing a blanket etch process on the first to third material layers. As a result, first resistance variable patterns122B and second resistance variable patterns124B are formed to have portions that are bent toward the second electrodes140A. Each selection layer126is formed to be positioned over the bent portion of the second resistance variable pattern124B.

Referring toFIG. 7B, a selection layer128is interposed between a first electrode110A and a resistance variable pattern120B, and the selection layer128extends upwards by a predetermined height from a substrate.

A selection layer128may be formed by depositing a material layer for forming the selection units128over a resultant structure after first electrodes110A are formed, depositing a first material layer and a second material layer for forming resistance variable patterns120B over the material layer, and performing a blanket etch process on the material layers. As a result, the selection layer128is formed to have a portion bent toward a second electrode140A, and the resistance variable pattern120B is positioned over the bent portion of the selection layer128.

FIG. 8is a cross-sectional view illustrating a semiconductor device in accordance with a sixth embodiment of the present disclosure. The semiconductor device further includes selection layers.

Referring toFIG. 8, a selection layer326is interposed between a second electrode340and a resistance variable pattern320. The selection layers326may be positioned at the same level on a substrate300as first electrodes310, the resistive variable patterns320, and the second electrodes340, and may extend to substantially the same height over the substrate300.

The selection layers326may be formed on sidewalls of the resistance variable patterns320by depositing a material layer for forming the selection layers326over a resultant structure after the resistance variable patterns320are formed, and performing a blanket etch process on the material layer.

Although not illustrated in the drawings, in another embodiment, the selection layers326may be interposed between the first electrodes310and the resistance variable patterns320. The selection layers326may be formed on both sidewalls of the first electrodes310before the formation of the resistance variable patterns320.

According to the embodiments of the present disclosure, which are described above, a semiconductor device having a high degree of integration and uniform cell characteristics may be secured, and may be manufactured with a simplified fabricating process.

The above and other memory circuits or semiconductor devices in accordance with the present disclosure can be used in a range of devices or systems.FIGS. 9-13provide some examples of devices or systems that can implement the memory circuits disclosed herein.

FIG. 9is an example of configuration diagram of a microprocessor implementing memory circuitry based on the disclosed technology.

Referring toFIG. 9, a microprocessor1000may perform tasks for controlling and tuning a series of processes of receiving data from various external devices, processing the data, and outputting processing results to external devices. The microprocessor1000may include a memory unit1010, an operation unit1020, a control unit1030, and so on. The microprocessor1000may be various data processing units such as a central processing unit (CPU), a graphic processing unit (GPU), a digital signal processor (DSP) and an application processor (AP).

The memory unit1010is a part which stores data in the microprocessor1000, as a processor register, register or the like. The memory unit1010may include a data register, an address register, a floating point register and so on. Besides, the memory unit1010may include various registers. The memory unit1010may perform the function of temporarily storing data for which operations are to be performed by the operation unit1020, result data of performing the operations and addresses where data for performing of the operations are stored.

The memory unit1010may include one or more of the above-described semiconductor devices in accordance with the implementations. For example, the memory unit1010may include a plurality of first electrodes and a plurality of second electrodes, which are disposed over a substrate and alternately arrayed in a first direction that is parallel to a plane of the substrate; and a plurality of resistance variable patterns, each of which is interposed between a corresponding one of the first electrodes and a corresponding one of the second electrodes, wherein the first and second electrodes and the resistance variable patterns extend upwards by a predetermined height from the substrate. Through this, integration degree of the memory unit1010may be raised and data storage characteristics of the memory unit1010may be improved. As a consequence, a size of the microprocessor1000may be reduced and performance characteristics of the microprocessor1000may be improved.

The operation unit1020may perform four arithmetical operations or logical operations according to results that the control unit1030decodes commands. The operation unit1020may include at least one arithmetic logic unit (ALU) and so on.

The control unit1030may receive signals from the memory unit1010, the operation unit1020and an external device of the microprocessor1000, perform extraction, decoding of commands, and controlling input and output of signals of the microprocessor1000, and execute processing represented by programs.

The microprocessor1000according to the present implementation may additionally include a cache memory unit1040which can temporarily store data to be inputted from an external device other than the memory unit1010or to be outputted to an external device. In this case, the cache memory unit1040may exchange data with the memory unit1010, the operation unit1020and the control unit1030through a bus interface1050.

FIG. 10is an example of configuration diagram of a processor implementing memory circuitry based on the disclosed technology.

Referring toFIG. 10, a processor1100may improve performance and realize multi-functionality by including various functions other than those of a microprocessor which performs tasks for controlling and tuning a series of processes of receiving data from various external devices, processing the data, and outputting processing results to external devices. The processor1100may include a core unit1110which serves as the microprocessor, a cache memory unit1120which serves to storing data temporarily, and a bus interface1130for transferring data between internal and external devices. The processor1100may include various system-on-chips (SoCs) such as a multi-core processor, a graphic processing unit (GPU) and an application processor (AP).

The core unit1110of the present implementation is a part which performs arithmetic logic operations for data inputted from an external device, and may include a memory unit1111, an operation unit1112and a control unit1113.

The memory unit1111is a part which stores data in the processor1100, as a processor register, a register or the like. The memory unit1111may include a data register, an address register, a floating point register and so on. Besides, the memory unit1111may include various registers. The memory unit1111may perform the function of temporarily storing data for which operations are to be performed by the operation unit1112, result data of performing the operations and addresses where data for performing of the operations are stored. The operation unit1112is a part which performs operations in the processor1100. The operation unit1112may perform four arithmetical operations, logical operations, according to results that the control unit1113decodes commands, or the like. The operation unit1112may include at least one arithmetic logic unit (ALU) and so on. The control unit1113may receive signals from the memory unit1111, the operation unit1112and an external device of the processor1100, perform extraction, decoding of commands, controlling input and output of signals of processor1100, and execute processing represented by programs.

The cache memory unit1120is a part which temporarily stores data to compensate for a difference in data processing speed between the core unit1110operating at a high speed and an external device operating at a low speed. The cache memory unit1120may include a primary storage section1121, a secondary storage section1122and a tertiary storage section1123. In general, the cache memory unit1120includes the primary and secondary storage sections1121and1122, and may include the tertiary storage section1123in the case where high storage capacity is required. As the occasion demands, the cache memory unit1120may include an increased number of storage sections. That is to say, the number of storage sections which are included in the cache memory unit1120may be changed according to a design. The speeds at which the primary, secondary and tertiary storage sections1121,1122and1123store and discriminate data may be the same or different. In the case where the speeds of the respective storage sections1121,1122and1123are different, the speed of the primary storage section1121may be largest. At least one storage section of the primary storage section1121, the secondary storage section1122and the tertiary storage section1123of the cache memory unit1120may include one or more of the above-described semiconductor devices in accordance with the implementations. For example, the cache memory unit1120may include a plurality of first electrodes and a plurality of second electrodes, which are disposed over a substrate and alternately arrayed in a first direction that is parallel to a plane of the substrate; and a plurality of resistance variable patterns, each of which is interposed between a corresponding one of the first electrodes and a corresponding one of the second electrodes, wherein the first and second electrodes and the resistance variable patterns extend upwards by a predetermined height from the substrate. Through this, integration degree of the cache memory unit1120may be raised and data storage characteristics of the cache memory unit1120may be improved. As a consequence, a size of the processor1100may be reduced and performance characteristics of the processor1100may be improved.

Although it was shown inFIG. 10that all the primary, secondary and tertiary storage sections1121,1122and1123are configured inside the cache memory unit1120, it is to be noted that all the primary, secondary and tertiary storage sections1121,1122and1123of the cache memory unit1120may be configured outside the core unit1110and may compensate for a difference in data processing speed between the core unit1110and the external device. Meanwhile, it is to be noted that the primary storage section1121of the cache memory unit1120may be disposed inside the core unit1110and the secondary storage section1122and the tertiary storage section1123may be configured outside the core unit1110to strengthen the function of compensating for a difference in data processing speed. In another implementation, the primary and secondary storage sections1121,1122may be disposed inside the core units1110and tertiary storage sections1123may be disposed outside core units1110.

The bus interface1130is a part which connects the core unit1110, the cache memory unit1120and external device and allows data to be efficiently transmitted.

The processor1100according to the present implementation may include a plurality of core units1110, and the plurality of core units1110may share the cache memory unit1120. The plurality of core units1110and the cache memory unit1120may be directly connected or be connected through the bus interface1130. The plurality of core units1110may be configured in the same way as the above-described configuration of the core unit1110. In the case where the processor1100includes the plurality of core unit1110, the primary storage section1121of the cache memory unit1120may be configured in each core unit1110in correspondence to the number of the plurality of core units1110, and the secondary storage section1122and the tertiary storage section1123may be configured outside the plurality of core units1110in such a way as to be shared through the bus interface1130. The processing speed of the primary storage section1121may be larger than the processing speeds of the secondary and tertiary storage section1122and1123. In another implementation, the primary storage section1121and the secondary storage section1122may be configured in each core unit1110in correspondence to the number of the plurality of core units1110, and the tertiary storage section1123may be configured outside the plurality of core units1110in such a way as to be shared through the bus interface1130.

The processor1100according to the present implementation may further include an embedded memory unit1140which stores data, a communication module unit1150which can transmit and receive data to and from an external device in a wired or wireless manner, a memory control unit1160which drives an external memory device, and a media processing unit1170which processes the data processed in the processor1100or the data inputted from an external input device and outputs the processed data to an external interface device and so on. Besides, the processor1100may include a plurality of various modules and devices. In this case, the plurality of modules which are added may exchange data with the core units1110and the cache memory unit1120and with one another, through the bus interface1130.

The embedded memory unit1140may include not only a volatile memory but also a nonvolatile memory. The volatile memory may include a DRAM (dynamic random access memory), a mobile DRAM, an SRAM (static random access memory), and a memory with similar functions to above mentioned memories, and so on. The nonvolatile memory may include a ROM (read only memory), a NOR flash memory, a NAND flash memory, a phase change random access memory (PRAM), a resistive random access memory (RRAM), a spin transfer torque random access memory (STTRAM), a magnetic random access memory (MRAM), a memory with similar functions.

The memory control unit1160is to administrate and process data transmitted between the processor1100and an external storage device operating according to a different communication standard. The memory control unit1160may include various memory controllers, for example, devices which may control IDE (Integrated Device Electronics), SATA (Serial Advanced Technology Attachment), SCSI (Small Computer System Interface), RAID (Redundant Array of Independent Disks), an SSD (solid state disk), eSATA (External SATA), PCMCIA (Personal Computer Memory Card International Association), a USB (universal serial bus), a secure digital (SD) card, a mini secure digital (mSD) card, a micro secure digital (micro SD) card, a secure digital high capacity (SDHC) card, a memory stick card, a smart media (SM) card, a multimedia card (MMC), an embedded MMC (eMMC), a compact flash (CF) card, and so on.

The media processing unit1170may process the data processed in the processor1100or the data inputted in the forms of image, voice and others from the external input device and output the data to the external interface device. The media processing unit1170may include a graphic processing unit (GPU), a digital signal processor (DSP), a high definition audio device (HD audio), a high definition multimedia interface (HDMI) controller, and so on.

FIG. 11is an example of configuration diagram of a system implementing memory circuitry based on the disclosed technology.

Referring toFIG. 11, a system1200as an apparatus for processing data may perform input, processing, output, communication, storage, etc. to conduct a series of manipulations for data. The system1200may include a processor1210, a main memory device1220, an auxiliary memory device1230, an interface device1240, and so on. The system1200of the present implementation may be various electronic systems which operate using processors, such as a computer, a server, a PDA (personal digital assistant), a portable computer, a web tablet, a wireless phone, a mobile phone, a smart phone, a digital music player, a PMP (portable multimedia player), a camera, a global positioning system (GPS), a video camera, a voice recorder, a telematics, an audio visual (AV) system, a smart television, and so on.

The processor1210may decode inputted commands and processes operation, comparison, etc. for the data stored in the system1200, and controls these operations. The processor1210may include a microprocessor unit (MPU), a central processing unit (CPU), a single/multi-core processor, a graphic processing unit (GPU), an application processor (AP), a digital signal processor (DSP), and so on.

The main memory device1220is a storage which can temporarily store, call and execute program codes or data from the auxiliary memory device1230when programs are executed and can conserve memorized contents even when power supply is cut off. The main memory device1220may include one or more of the above-described semiconductor devices in accordance with the implementations. For example, the main memory device1220may include a plurality of first electrodes and a plurality of second electrodes, which are disposed over a substrate and alternately arrayed in a first direction that is parallel to a plane of the substrate; and a plurality of resistance variable patterns, each of which is interposed between a corresponding one of the first electrodes and a corresponding one of the second electrodes, wherein the first and second electrodes and the resistance variable patterns extend upwards by a predetermined height from the substrate. Through this, integration degree of the main memory device1220may be raised and data storage characteristics of the main memory device1220may be improved. As a consequence, a size of the system1200may be reduced and performance characteristics of the system1200may be improved.

Also, the main memory device1220may further include a static random access memory (SRAM), a dynamic random access memory (DRAM), and so on, of a volatile memory type in which all contents are erased when power supply is cut off. Unlike this, the main memory device1220may not include the semiconductor devices according to the implementations, but may include a static random access memory (SRAM), a dynamic random access memory (DRAM), and so on, of a volatile memory type in which all contents are erased when power supply is cut off.

The auxiliary memory device1230is a memory device for storing program codes or data. While the speed of the auxiliary memory device1230is slower than the main memory device1220, the auxiliary memory device1230can store a larger amount of data. The auxiliary memory device1230may include one or more of the above-described semiconductor devices in accordance with the implementations. For example, the auxiliary memory device1230may include a plurality of first electrodes and a plurality of second electrodes, which are disposed over a substrate and alternately arrayed in a first direction that is parallel to a plane of the substrate; and a plurality of resistance variable patterns, each of which is interposed between a corresponding one of the first electrodes and a corresponding one of the second electrodes, wherein the first and second electrodes and the resistance variable patterns extend upwards by a predetermined height from the substrate. Through this, integration degree of the auxiliary memory device1230may be raised and data storage characteristics of the auxiliary memory device1230may be improved. As a consequence, a size of the system1200may be reduced and performance characteristics of the system1200may be improved.

Also, the auxiliary memory device1230may further include a data storage system (see the reference numeral1300ofFIG. 10) such as a magnetic tape using magnetism, a magnetic disk, a laser disk using optics, a magneto-optical disc using both magnetism and optics, a solid state disk (SSD), a USB memory (universal serial bus memory), a secure digital (SD) card, a mini secure digital (mSD) card, a micro secure digital (micro SD) card, a secure digital high capacity (SDHC) card, a memory stick card, a smart media (SM) card, a multimedia card (MMC), an embedded MMC (eMMC), a compact flash (CF) card, and so on. Unlike this, the auxiliary memory device1230may not include the semiconductor devices according to the implementations, but may include data storage systems (see the reference numeral1300ofFIG. 10) such as a magnetic tape using magnetism, a magnetic disk, a laser disk using optics, a magneto-optical disc using both magnetism and optics, a solid state disk (SSD), a USB memory (universal serial bus memory), a secure digital (SD) card, a mini secure digital (mSD) card, a micro secure digital (micro SD) card, a secure digital high capacity (SDHC) card, a memory stick card, a smart media (SM) card, a multimedia card (MMC), an embedded MMC (eMMC), a compact flash (CF) card, and so on.

The interface device1240may be to perform exchange of commands and data between the system1200of the present implementation and an external device. The interface device1240may be a keypad, a keyboard, a mouse, a speaker, a mike, a display, various human interface devices (HIDs), a communication device, and so on. The communication device may include a module capable of being connected with a wired network, a module capable of being connected with a wireless network and both of them. The wired network module may include a local area network (LAN), a universal serial bus (USB), an Ethernet, power line communication (PLC), such as various devices which send and receive data through transmit lines, and so on. The wireless network module may include Infrared Data Association (IrDA), code division multiple access (CDMA), time division multiple access (TDMA), frequency division multiple access (FDMA), a wireless LAN, Zigbee, a ubiquitous sensor network (USN), Bluetooth, radio frequency identification (RFID), long term evolution (LTE), near field communication (NFC), a wireless broadband Internet (Wibro), high speed downlink packet access (HSDPA), wideband CDMA (WCDMA), ultra wideband (UWB), such as various devices which send and receive data without transmit lines, and so on.

FIG. 12is an example of configuration diagram of a data storage system implementing memory circuitry based on the disclosed technology.

Referring toFIG. 12, a data storage system1300may include a storage device1310which has a nonvolatile characteristic as a component for storing data, a controller1320which controls the storage device1310, an interface1330for connection with an external device, and a temporary storage device1340for storing data temporarily. The data storage system1300may be a disk type such as a hard disk drive (HDD), a compact disc read only memory (CDROM), a digital versatile disc (DVD), a solid state disk (SSD), and so on, and a card type such as a USB memory (universal serial bus memory), a secure digital (SD) card, a mini secure digital (mSD) card, a micro secure digital (micro SD) card, a secure digital high capacity (SDHC) card, a memory stick card, a smart media (SM) card, a multimedia card (MMC), an embedded MMC (eMMC), a compact flash (CF) card, and so on.

The storage device1310may include a nonvolatile memory which stores data semi-permanently. The nonvolatile memory may include a ROM (read only memory), a NOR flash memory, a NAND flash memory, a phase change random access memory (PRAM), a resistive random access memory (RRAM), a magnetic random access memory (MRAM), and so on.

The controller1320may control exchange of data between the storage device1310and the interface1330. To this end, the controller1320may include a processor1321for performing an operation for, processing commands inputted through the interface1330from an outside of the data storage system1300and so on.

The interface1330is to perform exchange of commands and data between the data storage system1300and the external device. In the case where the data storage system1300is a card type, the interface1330may be compatible with interfaces which are used in devices, such as a USB memory (universal serial bus memory), a secure digital (SD) card, a mini secure digital (mSD) card, a micro secure digital (micro SD) card, a secure digital high capacity (SDHC) card, a memory stick card, a smart media (SM) card, a multimedia card (MMC), an embedded MMC (eMMC), a compact flash (CF) card, and so on, or be compatible with interfaces which are used in devices similar to the above mentioned devices. In the case where the data storage system1300is a disk type, the interface1330may be compatible with interfaces, such as IDE (Integrated Device Electronics), SATA (Serial Advanced Technology Attachment), SCSI (Small Computer System Interface), eSATA (External SATA), PCMCIA (Personal Computer Memory Card International Association), a USB (universal serial bus), and so on, or be compatible with the interfaces which are similar to the above mentioned interfaces. The interface1330may be compatible with one or more interfaces having a different type from each other.

The temporary storage device1340can store data temporarily for efficiently transferring data between the interface1330and the storage device1310according to diversifications and high performance of an interface with an external device, a controller and a system. The temporary storage device1340for temporarily storing data may include one or more of the above-described semiconductor devices in accordance with the implementations. The temporary storage device1340may include a plurality of first electrodes and a plurality of second electrodes, which are disposed over a substrate and alternately arrayed in a first direction that is parallel to a plane of the substrate; and a plurality of resistance variable patterns, each of which is interposed between a corresponding one of the first electrodes and a corresponding one of the second electrodes, wherein the first and second electrodes and the resistance variable patterns extend upwards by a predetermined height from the substrate. Through this, integration degree of the temporary storage device1340may be raised and data storage characteristics of the temporary storage device1340may be improved. As a consequence, a size of the data storage system1300may be reduced and performance characteristics of the data storage system1300may be improved.

FIG. 13is an example of configuration diagram of a memory system implementing memory circuitry based on the disclosed technology.

Referring toFIG. 13, a memory system1400may include a memory1410which has a nonvolatile characteristic as a component for storing data, a memory controller1420which controls the memory1410, an interface1430for connection with an external device, and so on. The memory system1400may be a card type such as a solid state disk (SSD), a USB memory (universal serial bus memory), a secure digital (SD) card, a mini secure digital (mSD) card, a micro secure digital (micro SD) card, a secure digital high capacity (SDHC) card, a memory stick card, a smart media (SM) card, a multimedia card (MMC), an embedded MMC (eMMC), a compact flash (CF) card, and so on.

The memory1410for storing data may include one or more of the above-described semiconductor devices in accordance with the implementations. For example, the memory1410may include a plurality of first electrodes and a plurality of second electrodes, which are disposed over a substrate and alternately arrayed in a first direction that is parallel to a plane of the substrate; and a plurality of resistance variable patterns, each of which is interposed between a corresponding one of the first electrodes and a corresponding one of the second electrodes, wherein the first and second electrodes and the resistance variable patterns extend upwards by a predetermined height from the substrate. Through this, integration degree of the memory1410may be raised and data storage characteristics of the memory1410may be improved. As a consequence, a size of the memory system1400may be reduced and performance characteristics of the memory system1400may be improved.

Also, the memory1410according to the present implementation may further include a ROM (read only memory), a NOR flash memory, a NAND flash memory, a phase change random access memory (PRAM), a resistive random access memory (RRAM), a magnetic random access memory (MRAM), and so on, which have a nonvolatile characteristic.

The memory controller1420may control exchange of data between the memory1410and the interface1430. To this end, the memory controller1420may include a processor1421for performing an operation for and processing commands inputted through the interface1430from an outside of the memory system1400.

The interface1430is to perform exchange of commands and data between the memory system1400and the external device. The interface1430may be compatible with interfaces which are used in devices, such as a USB memory (universal serial bus memory), a secure digital (SD) card, a mini secure digital (mSD) card, a micro secure digital (micro SD) card, a secure digital high capacity (SDHC) card, a memory stick card, a smart media (SM) card, a multimedia card (MMC), an embedded MMC (eMMC), a compact flash (CF) card, and so on, or be compatible with interfaces which are used in devices similar to the above mentioned devices. The interface1430may be compatible with one or more interfaces having a different type from each other.

The memory system1400according to the present implementation may further include a buffer memory1440for efficiently transferring data between the interface1430and the memory1410according to diversification and high performance of an interface with an external device, a memory controller and a memory system. For example, the buffer memory1440for temporarily storing data may include one or more of the above-described semiconductor devices in accordance with the implementations. The buffer memory1440may include a plurality of first electrodes and a plurality of second electrodes, which are disposed over a substrate and alternately arrayed in a first direction that is parallel to a plane of the substrate; and a plurality of resistance variable patterns, each of which is interposed between a corresponding one of the first electrodes and a corresponding one of the second electrodes, wherein the first and second electrodes and the resistance variable patterns extend upwards by a predetermined height from the substrate. Through this, integration degree of the buffer memory1440may be raised and data storage characteristics of the buffer memory1440may be improved. As a consequence, a size of the memory system1400may be reduced and performance characteristics of the memory system1400may be improved.

Moreover, the buffer memory1440according to the present implementation may further include an SRAM (static random access memory), a DRAM (dynamic random access memory), and so on, which have a volatile characteristic, and a phase change random access memory (PRAM), a resistive random access memory (RRAM), a spin transfer torque random access memory (STTRAM), a magnetic random access memory (MRAM), and so on, which have a nonvolatile characteristic. Unlike this, the buffer memory1440may not include the semiconductor devices according to the implementations, but may include an SRAM (static random access memory), a DRAM (dynamic random access memory), and so on, which have a volatile characteristic, and a phase change random access memory (PRAM), a resistive random access memory (RRAM), a spin transfer torque random access memory (STTRAM), a magnetic random access memory (MRAM), and so on, which have a nonvolatile characteristic.

Features in the above examples of electronic devices or systems inFIGS. 9-13based on the memory devices disclosed in this document may be implemented in various devices, systems or applications. Some examples include mobile phones or other portable communication devices, tablet computers, notebook or laptop computers, game machines, smart TV sets, TV set top boxes, multimedia servers, digital cameras with or without wireless communication functions, wrist watches or other wearable devices with wireless communication capabilities.

The present disclosure describes implementations and examples of embodiments. Other implementations, enhancements and variations can be made based on what is described and illustrated in the present disclosure.