Semiconductor device for charge pumping

Provided is a semiconductor device for performing charge pumping. The semiconductor device may include a first pumping unit, a second pumping unit, and a controller. The first pumping unit may be configured to output a boosted voltage via an output node by using a first input signal and the initial voltage, where the boosted voltage is greater than an initial voltage. The second pumping unit may be configured to output the boosted voltage via the output node by using a second input signal and the initial voltage. The controller may be configured to control the first and second pumping units. Each of the first and second pumping units may include an initialization unit, a boosting unit, and a transmission unit. The initialization unit may be configured to control a voltage of a boosting node to be equal to the initial voltage during an initialization operation. The boosting unit may be configured to boost the voltage of the boosting node based on the first and second input signals. Also, the transmission unit may be configured to control output of the boosted voltage.

CROSS-REFERENCE TO RELATED APPLICATIONS

This U.S. non-provisional application claims priority under 35 U.S.C. §119 to Korean Patent Application No. 10-2008-0075618, filed on Aug. 1, 2008, in the Korean Intellectual Property Office, the entire contents of which are hereby incorporated herein by reference.

BACKGROUND

Example embodiments relate to a semiconductor device (e.g., semiconductor device for charge pumping).

2. Description of Conventional Art

Semiconductor memory devices and/or circuits included in semiconductor memory devices may need to be supplied with a voltage that is higher than the conventional power supply voltage. A boosting circuit (e.g., a charge pump) that may be used to boost the power supply voltage has been proposed.

SUMMARY

Example embodiments provide a semiconductor device capable of increasing the efficiency of charge pumping by minimizing the amount of leakage current generated during charge pumping.

In an example embodiment, a semiconductor device for performing charge pumping may include a first pumping unit, a second pumping unit, and a controller. The first pumping unit may be configured to output a boosted voltage via an output node based on a first input signal and an initial voltage, such that the boosted voltage is greater than the initial voltage. The second pumping unit may be configured to output the boosted voltage via the output node based on a second input signal and the initial voltage. The controller may be configured to control the first and second pumping units based on at least a logic state of the first input signal and the second input signal. Each of the first and second pumping units may include an initialization unit, a boosting unit, and a transmission unit. The initialization unit may be configured to control a voltage of a boosting node to be equal to the initial voltage during an initialization operation. The boosting unit may be configured to boost the voltage of the boosting node to the boosted voltage based on one of the first and second input signals. The transmission unit may be configured to control output of the boosted voltage. The controller may (i) control the transmission unit to selectively output the boosted voltage, and/or (ii) disable the initialization unit, if the first input signal and the second input signal are in the same logic state.

DETAILED DESCRIPTION OF EXAMPLE EMBODIMENTS

Example embodiments may be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein; rather, these embodiments may be provided so that this disclosure will be thorough and complete, and will fully convey the concept of example embodiments to those skilled in the art.

Example embodiments of the present concept will be described in detail with reference to the accompanying drawings. The reference numerals denote the same elements throughout the drawings.

FIG. 1is a circuit diagram of a semiconductor device100for performing charge pumping according to an example embodiment. The semiconductor device100may include a first pumping unit110, a second pumping unit140and a controller170. The controller170includes first and second controller units160and180. It should be noted thatFIG. 1illustrates only an example embodiment of a semiconductor device. Thus, further embodiments are not limited to the first pumping unit110, the second pumping unit140, the first controller unit160and the second controller unit180. That is to say, various circuits may be used as long as the various circuits perform the operations of the first pumping unit110, the second pumping unit140, the first controller unit160and the second controller unit180

RegardingFIG. 1, the first pumping unit110outputs a boosted voltage higher than an initial voltage Vin to an output node Vout by using a first input signal Ø1and the initial voltage Vin, and the second pumping unit140outputs a boosted voltage higher than the initial voltage Vin to the output node Vout by using a second input signal Ø2and the initial voltage Vin. The first pumping unit110may include a first initialization unit113, a first boosting unit115and a first transmission unit117. The second pumping unit140may include a second initialization unit143, a second boosting unit145and a second transmission unit147.

For an initialization operation, the first initialization unit113controls a voltage of a boosting node BL of the first pumping unit110(hereinafter referred to as a ‘first boosting node’) to be equal to the initial voltage Vin. For charge pumping, the first boosting unit115boosts the voltage of the first boosting node BL to a desired voltage by using the first input signal Ø1. The first boosting unit115may then output the boosted voltage to the first transmission unit117(according to another example embodiment), and/or a first transmission control unit162as illustrated inFIG. 1(discussed further below). The first transmission unit117controls whether to apply the boosted voltage to the output node Vout.

Regarding the operation the second initialization unit143, the operation of the second initialization unit143may be similar to the operation of the first initialization unit113. Likewise, operation of the second boosting unit145and the second transmission unit147may be similar to the operation of the first boosting unit115and the first transmission unit117, respectively. More specifically, the second initialization unit143controls a voltage of a boosting node BR of the second pumping unit140(hereinafter referred to as a ‘second boosting node’) to be equal to the initial voltage Vin. For charge pumping, the second boosting unit145boosts the voltage of the second boosting node BR to the desired voltage by using the second input signal Ø2. The second boosting unit145may then output the boosted voltage to the second transmission unit147(according to another example embodiment), and/or a second transmission control unit182as illustrated inFIG. 1(discussed further below). The second transmission unit147controls whether to apply the boosted voltage to the output node Vout.

The operational relationship of the first pumping unit110and the second pumping unit140is briefly discussed. When the first pumping unit110performs the initialization operation, the second pumping unit140performs voltage boosting and outputs the boosted voltage to the output node Vout. Conversely, when the first pumping unit110performs voltage boosting and outputs the boosted voltage to the output node Vout, the second pumping unit140performs the initialization operation. The initialization operation and voltage boosting will be described in greater detail during the discussion ofFIGS. 2A and 2B.

The first and second controller units160and180may: (i) control the boosted voltage to be applied to the output node Vout; and/or (ii) control the first and second initialization units113and143to be disabled if a certain logic state is provided by the input signals Ø1and Ø2(e.g., the first input signal Ø1and the second input signal Ø2are in the same logic state). The first controller unit160includes a first transmission control unit162and a first enable control unit165. The second controller unit180includes a second transmission control unit182and a second enable control unit185.

The first transmission control unit162is connected between the first boosting node BL and the first transmission unit117. The second transmission control unit182is connected between the second boosting node BR and the second transmission unit147. The first transmission control unit162and/or the second transmission control unit182may control whether to output the boosted voltage in response to a first control signal TCO. For example, the first control signal TCO may be in a first logic state if the first input signal Ø1and the second input signal Ø2are in the same logic state (e.g., Ø1=Ø2). Hereinafter, the first logic state of the first control signal TCO is logic high. The first control signal TCO may be in a second logic state if the first input signal Ø1and the second input signal Ø2are not in the same logic state (e.g., Ø≠Ø2). Hereinafter, the second logic state of the first control signal TCO is logic low. However, embodiments are not limited to these logic states. The same effect may be obtained even when the first logic state is logic low and the second logic state is logic high.

The first enable control unit165may control whether to enable the first initialization unit113in response to a second control signal Ø1A. The second control signal Ø1A may have the opposite phase to the first input signal Ø1, and/or may be in the second logic stage for a longer time interval than the time interval for the first input signal Ø1in the first logic state. The second enable control unit185may control whether to enable the second initialization unit143in response to a third control signal Ø2A. The third control signal Ø2A may have the opposite phase to the second input signal Ø2and/or may be in the first logic state for a longer time interval than the time interval for the second input signal Ø2in the second logic state (discussed above). The operations of the first and second controller units160and180will be described later in detail with reference toFIGS. 2A and 2B.

The circuit constructions of the first pumping unit110, the second pumping unit140, the first controller unit160and the second controller unit180are described in further detail below.

Regarding the first pumping unit110, the first initialization unit113may be embodied as a metal oxide semiconductor (MOS) transistor ML1in which a first terminal is applied the initial voltage Vin, a second terminal is connected to the first boosting node BL, and a gate (third terminal) is supplied a signal output from the first enable control unit165. The MOS transistor ML1may be an NMOS transistor. The first boosting unit115may be embodied as a capacitor CL1in which the first input signal Ø1is supplied to one terminal and the other terminal is connected to the first boosting node BL. The first transmission unit117may be embodied as a MOS transistor ML2in which a first terminal is connected to the first transmission control unit162, a second terminal is connected to the output node Vout, and a gate is connected to the second boosting node BR. The MOS transistor ML2may be a PMOS transistor.

Regarding the second pumping unit140, the second initialization unit143may be embodied as a MOS transistor MR1in which a first terminal is applied the initial voltage Vin, a second terminal is connected to the second boosting node BR, and a gate is supplied a signal output from the second enable control unit185. The MOS transistor MR1may be an NMOS transistor. The second boosting unit145may be embodied as a capacitor CR1in which the second input signal Ø2is supplied to one terminal and the other terminal is connected to the second boosting node BR. The second transmission unit147may be embodied as a MOS transistor MR2in which a first terminal is connected to the output node Vout, a second terminal is connected to the second transmission control unit182, and a gate is connected to the first boosting node BL. The MOS transistor MR2may be a PMOS transistor.

Lastly, the first controller unit160and the second controller unit180are described. The first transmission control unit162may be embodied as a MOS transistor ML3in which a first terminal is connected to the first boosting node BL, a second terminal is connected to the first transmission unit117and a gate is supplied the first control signal TCO. The second transmission control unit182may be embodied as a MOS transistor MR3in which a first terminal is connected to the second transmission unit147, a second terminal is connected to the second boosting node BR and a gate is supplied the first control signal TCO.

The first enable control unit165may be embodied as a MOS transistor ML0and a capacitor CL0. In the MOS transistor ML0, a first terminal is applied an initial voltage Vin, a second terminal is connected to (i) an output node N1of the first enable control unit165and (ii) the gate of the MOS transistor ML1of the first initialization unit113, and a gate is connected to the first boosting node BL. The MOS transistor ML0may be an NMOS transistor. The second control signal Ø1A is supplied to one terminal of the capacitor CL0and the other terminal of the capacitor CL0is connected to the second terminal of the MOS transistor ML0.

The second enable control unit185may include a MOS transistor MR0and a capacitor CR0. In the MOS transistor MR0, a first terminal is supplied the initial voltage Vin, a second terminal is connected to (i) an output node N2of the second enable control unit185and (ii) the gate of the MOS transistor MR1, and a gate is connected to the second boosting node BR. The MOS transistor MR0may be an NMOS transistor. The third control signal Ø2A is supplied to one terminal of the capacitor CR0and the other terminal of the capacitor CR0is connected to the second terminal of the MOS transistor MR0.

In an another example embodiment, the semiconductor device100may further include a control signal generation unit (not shown) that generates first through third control signals TCO, Ø1A, and Ø2A. An embodiment of the control signal generation unit will be described later with reference toFIGS. 4 through 5B.

FIG. 2Ais a waveform diagram of signals of the semiconductor device100ofFIG. 1, according to an example embodiment.

Operation of the semiconductor device100when the phase of the first input signal Ø1is opposite to that of the second input signal Ø2is described with reference toFIGS. 1 and 2A. Before time t1, a first input signal Ø1, a first control signal TCO and a third control signal Ø2A are in the second logic state and a second input signal Ø2and a second control signal Ø1A are in the first logic state. In this case, the MOS transistors ML1, ML3, MR2, MR3, and MR0are turned on and the MOS transistors ML0, ML2, and MR1are turned off. Thus the capacitor CL1is charged with electric charges until a voltage of the capacitor CL1, i.e., a voltage of the first boosting node BL, is equal to the initial voltage Vin. Such an operation of equalizing the voltage of the capacitor CL1with the initial voltage Vin is referred to as the initialization operation. Similarly, the second enable control unit185performs the initialization operation, and thus a voltage of the output node N2of the second enable control unit185becomes equal to the initial voltage Vin.

At the time t1, the first control signal TCO is in the first logic state and the second control signal Ø1A is in the second logic state. Thus the MOS transistor ML1is turned off after the time t1.

In a time interval between times t2and t3, transition of the first input signal Ø1and the second input signal Ø2occur. In the time interval between the times t2and t3, the first control signal TCO is in the first logic state and the second and third control signals Ø1A and Ø2A are in the second logic state. The MOS transistors ML1, ML3, MR1, and MR3are turned off and no electric charges move from the first boosting node BL and the second boosting node BR to a node to which the initial voltage Vin is to be applied. Also, no electric charges move from the output node Vout to the first boosting node BL and the second boosting node BR. Thus there is no leakage current generated in the time interval where the transition of the first input signal Ø1and the second input signal Ø2occur, thereby preventing a pumping loss and a short-circuit loss from occurring. Furthermore, in a time interval between times t1to t4, MOS transistors ML1, ML3, MR1, and MR3are turned off and thus the semiconductor device100does not perform a normal charge pumping operation.

Conventionally, the pumping loss and short-circuit loss may occur due to the leakage current in the time interval where the transition of the first input signal Ø1and the second input signal Ø2occur. For example, a conventional semiconductor device may be assumed to include a power supply voltage VDD, but not include either the first controller unit160or the second controller unit180(the conventional semiconductor device not illustrated). Pumping loss and short circuit loss may occur in such a conventional semiconductor device. The pumping loss and short circuit loss phenomena are discussed in the context of the conventional semiconductor device.

Pumping loss occurs in a conventional semiconductor when electric charges in the capacitors CL1and CR1move to the initial voltage Vin node rather than the output node Vout. A more detailed explanation of pumping loss is provided. A conventional semiconductor device may have the initial voltage Vin be equal to the power supply voltage VDD and the first input signal Ø1and the second input signal Ø2in the first logic state. Since a conventional semiconductor device lacks either the first controller unit160or the second controller unit180, the MOS transistor ML1is turned on when a voltage that is equal to or greater than the sum of the power supply voltage VDD and a threshold voltage Vth of the MOS transistors ML1is applied to a gate thereof. The MOS transistor MR1is turned on when a voltage that is equal to or greater than the sum of the power supply voltage VDD and a threshold voltage Vth of the MOS transistors MR1is applied to a gate thereof. When the first input signal Ø1of the conventional semiconductor device transits from the second logic state to the first logic state, the voltage of the first boosting node BL changes from VDD to 2VDD. Also, when the second input signal Ø2of the conventional semiconductor device transits from the first logic state to the second logic state, the voltage of the first boosting node BL changes from 2VDD to VDD. Thus, during a time interval of such a transition, in which the first input signal Ø1and the second input signal Ø2have a voltage between VDD+Vth and 2VDD−Vth, the conventional semiconductor device operates with the first input signal Ø1and the second input signal Ø2in the first logic state. That is, in the above time interval, the MOS transistors ML1and MR1are turned on and the MOS transistors ML2and MR2are turned off. Accordingly, electric charges in the capacitors CL1and CR1move to a node to which the initial voltage Vin is applied rather than the output node Vout, thereby causing discharging of capacitors CL1and CR1. Such a phenomenon is referred to as the pumping loss.

However, the semiconductor device100according to an example embodiment addresses the above discussed pumping loss that occurs in the conventional semiconductor device. More specifically, in the semiconductor device100, MOS transistors ML1, ML3, MR1, and MR3are turned off during the time interval between times t1and t4, which include the time interval where the pumping loss occurs. Thus, the semiconductor device100prevents the pumping loss from occurring.

On the other hand, short-circuit loss occurs in the conventional semiconductor device when electric charges stored in a capacitor connected to the output node Vout move toward the nodes BL and BR. A more detailed explanation of short-circuit loss is provided. In the time interval where transition of the first input signal Ø1and the second input signal Ø2occur, either (i) the MOS transistors ML1and ML2or (ii) the MOS transistors MR1and MR2are concurrently turned on. The output node Vout of a conventional semiconductor device is generally connected to a capacitor and thus the capacitor is charged with electric charges moving to the output node Vout. During the time interval where either (i) the MOS transistors ML1and ML2or (ii) the MOS transistors MR1and MR2are concurrently turned on, the electric charges stored in the capacitor connected to the output node Vout moves toward the nodes BL and BR. The flow of charge from the capacitor connected to Vout causes a discharging of the capacitor. Such a phenomenon is referred to as the short-circuit loss.

However, the semiconductor device100according to an example embodiment addresses the above discussed short circuit loss that occurs in the conventional semiconductor device. Like the conventional semiconductor device, the semiconductor device100may be connected to a capacitor and thus the capacitor is charged with electric charges moving to the output node Vout. However, in the semiconductor device100, MOS transistors ML1, ML3, MR1, and MR3are turned off during the time interval between t1and t4, which include the time interval where the short-circuit loss occurs. Thus, the example embodiment prevents the short-circuit loss from occurring.

Returning to semiconductor device100, in a time interval between times t4and t5, the semiconductor device100normally performs charge pumping. The first input signal Ø1and the third control signal Ø2A are in the first logic state. The second input signal Ø2, the first control signal TCO and the second control signal Ø1A are in the second logic state. Thus, the MOS transistors ML0, ML2, ML3, MR1, and MR3are turned on and the MOS transistors ML1, MR0, and MR2are turned off. In this case, since the first input signal Ø1is in the first logic state, the voltage of the first boosting node BL is boosted to the sum of the initial voltage Vin and the voltage of the first input signal Ø1. Also, since the transistors ML3and ML2are turned on, the voltage of the first boosting node BL is applied to the output node Vout. Such an operation of boosting a voltage and outputting the boosted voltage is referred to as voltage boosting. In a time interval between times t3and t4, the following occur: (i) the first pumping unit110and the second enable control unit185perform voltage boosting; and (ii) the second pumping unit140and the first enable control unit165perform the initialization operation. For example, if the initial voltage Vin is equal to the power supply voltage VDD and the first input signal Ø1and the second input signal Ø2have the power supply voltage VDD when they are in the first logic state, both the first boosting node BL and the output node N2of the second enable control unit185have a voltage 2VDD.

At the time t5, the first control signal TCO is in the first logic state and the third control signal Ø2A is in the second logic state. Thus, the MOS transistors MR1, MR3, and ML3are turned off after the time t4.

During a time interval between times t6and t7, the logic states of the first input signal Ø1and the second input signal Ø2transition to states opposite to the logic state transition undertaken during the time interval between t2and t3. In the time interval between times t6and t7, the first control signal TCO is in the first logic state and the second and third control signals Ø1A andØ2A are in the second logic state as in the time interval between times t2and t3. Thus, the MOS transistors ML1, ML3, MR1, and MR3are turned off. Therefore, no electric charges may move from (i) the first boosting node BL and (ii) the second boosting node BR, to a node to which the initial voltage Vin is applied. Also, no electric charges may move from the output node Vout to (i) the first boosting node BL and (ii) the second boosting node BR. Accordingly, no leakage current is generated during the time interval where transition of the first input signal Ø1and the second input signal Ø2occur, thereby preventing the pumping loss and the short-circuit loss from occurring. As described above, in this case, the MOS transistors ML1, ML3, MR1, and MR3are also turned off during the time interval between the times t5and t8. That is, the MOS transistors ML1, ML3, MR1, and MR3are turned off during a time interval where the pumping loss and the short-circuit loss occur, thereby preventing the pumping loss and the short-circuit loss from occurring.

After the time t8, the semiconductor device100may perform charge pumping again. More specifically, (i) the second input signal Ø2and the second control signal Ø1A may be in the first logic state, and (ii) the first input signal Ø1, the first control signal TCO and the third control signal Ø2A may be in the second logic state. In such a situation, the MOS transistors ML1, ML3, MR0, MR2, and MR3are turned on and the MOS transistors ML0, ML2, and MR1are turned off. Thus, the second pumping unit140and the first enable control unit165perform voltage boosting, and the first pumping unit110and the second enable control unit185perform the initialization operation.

As illustrated inFIG. 2A, when the first input signal Ø1has a phase opposite to that of the second input signal Ø2, the leakage current is generated during the transition time intervals OV_T1and OV_T2of the first input signal Ø1and the second input signal Ø2, thereby causing the pumping loss and the short-circuit loss. However, according to the illustrated example embodiment, during the transition time intervals OV_T1and OV_T2, the MOS transistors ML1, ML3, MR1, and MR3are turned off, and thus, there is no leakage current generated. The absence of leakage current prevents the pumping loss and the short-circuit loss from occurring.

FIG. 2Bis a waveform diagram of signals of the semiconductor device100ofFIG. 1, according to another example embodiment. Referring toFIGS. 1 through 2B,FIG. 2Billustrates a case where the phase of a first input signal Ø1is not opposite to that of a second input signal Ø2, unlike inFIG. 2A. That is, referring toFIG. 2B, the first input signal Ø1and the second input signal Ø2are in the same logic state in time intervals OV_H and OV_L.

The first input signal Ø1and the second input signal Ø2illustrated inFIG. 2Bmay not be used in a conventional charge pump. In a conventional charge pump, the first input signal Ø1and the second input signal Ø2illustrated inFIG. 2Bmay cause pumping loss, output loss, and/or short-circuit loss. Pumping loss may occur in the time interval OV_H where both the first input signal Ø1and the second input signal Ø2are in the first logic state. Output loss may occur in the time interval OV_L where both the first input signal Ø1and the second input signal Ø2are in the second logic state. Also, short-circuit loss may occur in a time interval where transition of the first input signal Ø1and the second input signal Ø2occur.

Output loss refers to the unintended charging of the capacitors CL1and CR1in the semiconductor device100. For example, the semiconductor device100may be assumed to not include the first controller unit160and the second controller unit180. In such an conventional semiconductor device, if both the first input signal Ø1and the second input signal Ø2are in the second logic state, then (i) the MOS transistors ML1and MR1are turned off, (ii) the MOS transistors ML2and MR2are turned on, and (iii) electric charges charged in a capacitor of the output node Vout move toward the nodes BL and BR. This causes charging of the capacitors CL1and CR1with the electric charges. Such a phenomenon is referred to as the output loss.

However, in the semiconductor device100according to an example embodiment, the pumping loss, the output loss and the short-circuit loss may not occur. This remains true even if the first input signal Ø1and the second input signal Ø2illustrated inFIG. 2Bare used. A more detailed explanation is provided.

Before time t1inFIG. 2B, the semiconductor device100may operate similar to the corresponding time before t1illustrated inFIG. 2A(initialization operation). Briefly, the semiconductor device100operates similar to the time before t1if the second control signal Ø1A is in first logic state. Since operation of the semiconductor device100before time t1is similar inFIGS. 2A and 3B, further description regarding the time before t1is not be provided.

Time interval OV_H is in a time interval between times t1and t2. In the time interval OV_H both the first input signal Ø1and the second input signal Ø2are in the first logic state. In addition, in the time interval OV_H, (i) the first input signal Ø1and the second input signal Ø2are in the first logic state, and (ii) a first control signal TCO, a second control signal Ø1A and a third control signal Ø2A are in the second logic state. Thus, the MOS transistors ML1, ML2, MR1, and MR2may be turned off and the MOS transistors ML0, ML3, MR0, and MR3may be turned on. Since the MOS transistors ML1, ML2, MR1, and MR2are turned off, no electric charges may move (i) from the first boosting node BL and the second boosting node BR to a node to which initial voltage Vin is applied, and (ii) from the output node Vout to the first boosting node BL and the second boosting node BR. Accordingly a leakage current is not generated in the time interval OV_H in which both the first input signal Ø1and the second input signal Ø2are in the first logic state, thereby preventing the pumping loss and the short-circuit loss from occurring.

In a time interval between times t2and t3inFIG. 2B, the semiconductor device100performs a charge pumping operation similar to the charge pumping operation described inFIG. 2Awith reference to the time interval between the times t4and t5. More specifically, charge pumping may be performed in a time interval in which (i) the third control signal Ø2A is in the first logic state and (ii) the first control signal TCO is in the second logic state. Since charge pumping has been specifically described above with reference toFIG. 2A, further description regarding the time interval between the times t4and t5is not be provided.

A time interval between times t3and t4is the time interval OV_L, in which both the first input signal Ø1and the second input signal Ø2are in the second logic state. In the time interval OV_L, (i) the first input signal Ø1and the second input signal Ø2are in the second logic state and (ii) the first control signal TCO is in the first logic state. Thus, the MOS transistors ML3and MR3are turned off. Since both the MOS transistors ML3and MR3are turned off in the time interval OV_L, no electric charges move from the output node Vout to the first boosting node BL and the second boosting node BR. Accordingly, no leakage current is generated in the time interval OV_L since both the first input signal Ø1and the second input signal Ø2are in the second logic state. Lack of the leakage current prevents the output loss from occurring.

FIG. 3is a circuit diagram of a semiconductor device300for performing charge pumping, according to another example embodiment. Referring toFIGS. 1 and 3, the semiconductor device300includes a first pumping unit310, a second pumping unit340, a controller370and a bulk voltage maintaining unit350. The controller370includes a first controller unit360and a second controller unit380. The operations and constructions of the first pumping unit310, the second pumping unit340, the first controller unit360and the second controller unit380ofFIG. 3are respectively similar to those of the first pumping unit110, the second pumping unit140, the first controller unit160and the second controller unit180ofFIG. 1.

As described above, the MOS transistors ML2, ML3, MR2, and MR3that respectively constitute the first transmission unit117, the second transmission unit147, the first transmission control unit162and the second transmission control unit182illustrated inFIG. 1, may be embodied as PMOS transistors. However, PMOS transistors may require a way to prevent bulk forward bias phenomenon and the latch-up phenomenon from occurring. For example, bulk terminals of the PMOS transistors are directly connected to the output node Vout. When the PMOS transistors have a high source voltage and a low bulk voltage, a bulk forward bias phenomenon and a latch-up phenomenon may occur. Thus in order to solve such problems of a PMOS transistor, the semiconductor device300further includes the bulk voltage maintaining unit350to increase the bulk voltages of the PMOS transistors ML2, ML3, MR2, and MR3to a desired (or, alternatively, a predetermined) level and maintain the increased voltage, thereby preventing the bulk forward bias phenomenon and the latch-up phenomenon from occurring.

The bulk voltage maintaining unit350includes a plurality of PMOS transistors ML4, ML5, MR4, and MR5. Regarding PMOS transistor ML5, a first boosting node BL is connected to a first terminal of the PMOS transistor ML5and the first control signal TCO is supplied to a gate of the PMOS transistor ML5. Regarding PMOS transistor ML4, the first terminal and gate of the PMOS transistor ML4are respectively connected to a second terminal of a PMOS transistor ML5and a second boosting node BR. Regarding PMOS transistor MR4, a first terminal and gate of a PMOS transistor MR4are respectively connected to a second terminal of the PMOS transistor ML4and the first boosting node BL. Regarding PMOS transistor MR5, a first terminal and a second terminal of the PMOS transistor MR5are respectively connected to the second terminal of the PMOS transistor MR4and the second boosting node BR, and the first control signal TCO is supplied to a gate of the PMOS transistor MR5. A node between the PMOS transistor ML4and the PMOS transistor MR4is connected to the bodies of the PMOS transistors ML2, ML3, ML4, ML5, MR2, MR3, MR4, and MR5.

FIG. 4is a circuit diagram of a control signal generation unit400that generates the first through third control signals TCO, Ø1A, and Ø2A illustrated inFIGS. 1 through 3, according to an example embodiment. The control signal generation unit400includes a first operation unit410, a second operation unit430and a third operation unit450. The first operation unit410generates the first control signal TCO from a first initial input signal Ø1_IN and a second initial input signal Ø2_IN. The second operation unit430generates a first input signal Ø1by delaying the first initial input signal Ø1_IN, and generates the second control signal Ø1A from the first initial input signal Ø1_IN. The third operation unit450generates a second input signal Ø2by delaying the second initial input signal Ø2_IN, and generates the third control signal Ø2A from the second initial input signal Ø2_IN.

The first operation unit410includes an OR-NAND logic circuit417and a control signal boosting unit415. The second operation unit430includes a first input signal generation unit433, a first delayer435and a first NOR gate437. The third operation unit450includes a second input signal generation unit453, a second delayer455and a second NOR gate457. The operations of the first through third operation units410,430, and450are described in further detail with reference toFIGS. 5A and 5B.

FIG. 5Ais a waveform diagram of signals of the control signal generation unit400ofFIG. 4, according to an example embodiment.FIG. 5Bis a waveform diagram of signals of the control signal generation unit400ofFIG. 4, according to another example embodiment.

FIG. 5Aillustrates a case where the phase of a first input signal Ø1is opposite to that of a second input signal Ø2. More specifically, the phase of a first initial input signal Ø1_IN is opposite to that of a second initial input signal Ø2_IN.FIG. 5Billustrates a case where the phase of the first input signal Ø1is not opposite to that of the second input signal Ø2. More specifically, the phase of the first initial input signal Ø1_IN is not opposite to that of the second initial input signal Ø2_IN.

Referring toFIGS. 4 through 5B, the first input signal generation unit433may delay the first initial input signal Ø1_IN by a first time Δt1and outputs the first input signal Ø1. The first delayer435may delay the first input signal Ø1by a second time Δt2and outputs a first delayed signal Ø1_S. The first input signal generation unit433and/or the first delayer435may both be embodied with an inverter chain, but further embodiments are not limited thereto. That is, if signals are delayed using other delay units, it is possible to obtain the same effects. A first NOR gate437of the first input signal generation unit433performs a NOR operation on the first initial input signal Ø1_IN and the first delayed signal Ø1_S and outputs a second control signal Ø1A. The second operation unit430makes it possible to generate the second control signal Ø1A with a phase opposite to the phase of the first input signal Ø1. Also, the second control signal Ø1A may have a time interval during the second logic state that is wider than time interval of the first input signal Ø1during the first logic state.

The second input signal generation unit453delays the second initial input signal Ø2_IN by the first time Δt1and outputs the second input signal Ø2. The second delayer455delays the second input signal Ø2by the second time Δt2and outputs a second delayed signal Ø2_S. The second input signal generation unit453and the second delayer455may both be embodied with an inverter chain similar to the first input signal generation unit433and the first delayer435. Further embodiments are not limited the examples described above. The first input signal generation unit433and the second input signal generation unit453may delay signals by the first time Δt1and the first delayer435and the second delayer455may also delay signals by the second time Δt2. The second NOR gate457performs the NOR operation on the second initial input signal Ø2_IN and the second delayed signal Ø2_S and outputs a third control signal Ø2A. The third operation unit450makes it possible to generate the third control signal Ø2A with a phase opposite to the phase of the second input signal Ø2. Also, the third control signal Ø2A may have a time interval during the first logic state that is narrower than the time interval of the second input signal Ø2during the second logic state.

The OR-NAND logic circuit417includes two OR gates and a NAND gate. The OR-NAND logic circuit417performs an OR operation on the first initial input signal Ø1_IN and the second delayed signal Ø2_S. The OR-NAND logic circuit417also performs an OR operation on the second initial input signal Ø2_IN and the first delayed signal Ø1_S. Thereafter, the OR-NAND logic circuit417performs a NAND operation based on the results of the two OR operations.

The control signal boosting unit415boosts the voltage of an output signal TCI of the OR-NAND logic circuit417and then outputs the first control signal TCO. The control signal boosting unit415illustrated inFIG. 4is an example embodiment, and further embodiments are not limited to the structure illustrated inFIG. 4. For example, various circuits may be used as the control signal boosting unit415as long as they can boost the voltage of the output signal TCI of the OR-NAND logic circuit417and output the first control signal TCO. As described above, the MOS transistor ML1and the MOS transistor MR1may be turned on when a voltage that is equal to or greater than the sum of the power supply voltage VDD and the threshold voltage Vth of each of the MOS transistors ML1and MR1is applied to gates of the MOS transistor ML1and the MOS transistor MR1. Similarly, the MOS transistor ML3and MOS transistor MR3may be turned on when a voltage that is less than or equal to the sum of the power supply voltage VDD and the threshold voltage Vth of each of the MOS transistors ML3and MR3is applied to the gates of the MOS transistor ML3and MOS transistor MR3. Thus when the first control signal TCO is logic high, the voltage of the first control signal TCO may be greater than a voltage 2VDD−Vth. Also, when the first control signal TCO is logic low, the voltage of the first control signal TCO may be lower than a voltage 2VDD+Vth. The first operation unit410makes it possible to generate the first control signal TCO (i) in the first logic state during a time interval in which the first input signal Ø1and the second input signal Ø2are in the same logic state, and (ii) in the second logic state during a time interval in which the first input signal Ø1and the second input signal Ø2are in different logic states.

If the phase of the first input signal Ø1is not opposite to that of the second input signal Ø2, the first control signal TCO may be in the second logic state in a time interval Δt3in which the first input signal Ø1and the second input signal Ø2are in the first logic state, as illustrated inFIG. 5B. Since both the first input signal Ø1and the second input signal Ø2are in the first logic state in this case (as discussed with regard toFIG. 1), both the transistors ML2and MR2are turned off, and thus, the leakage current is not generated in a direction from the output node Vout to the first and second boosting nodes BL and BR. Accordingly, even if the first control signal TCO is in the second logic state, the pumping loss does not occur.

An example embodiment of the control signal generation unit400and the signals generated by the control signal generation unit400have been described above. Further embodiments are not limited to generating the first through third control signals TCO, Ø1A, and Ø2A by using the control signal generation unit400ofFIG. 4. That is, the first through third control signals TCO, Ø1A, and Ø2A may be generated as illustrated inFIGS. 2A and 2Busing another device.

While example embodiments are provided for illustrative purposes, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the following claims.