Read source line compensation in a non-volatile memory

Non-volatile memory circuits according to the present invention provide a reference memory having multiple reference cells that are shared among a group of sense amplifiers through an interconnect conductor line. The higher number of reference cells for each reference memory generates a greater amount of electrical current for charging multiple source lines. The multiple source lines are coupled to the interconnect conductor bar for capacitance matching with a source line coupled to a memory cell in a main memory array. After a silicon wafer out, measurements to the capacitance produced by the source line in the main memory array and the capacitance produced by the source line in the reference array are taken for an optional trimming. A further calibration in capacitance matching is achieved by trimming one of the source lines that is coupled to the interconnect conductor bar and the reference memory, either by cutting a portion of the source line or adding a portion to the source line.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates generally to integrated-circuit memory arrays, and in particular, to adjusting read source line coupled to a reference array for capacitance matching with a memory array.

2. Description of Related Art

Electrically programmable and erasable non-volatile memory technologies based on charge storage structures known as Electrically Erasable Programmable Read-Only Memory (EEPROM) and flash memory are used in a variety of modern applications. A flash memory is designed with an array of memory cells that can be independently programmed and read. Sense amplifiers in a flash memory are used to determine the data value or values stored in a non-volatile memory. In a typical sensing scheme, an electrical current through the memory cell being sensed is compared to a reference current by a current sense amplifier.

A number of memory cell structures are used for EEPROM and flash memory. As the dimensions of integrated circuits shrink, greater interest is arising for memory cell structures based on charge trapping dielectric layers, because of the scalability and simplicity of the manufacturing processes. Memory cell structures based on charge trapping dielectric layers include structures known by the industry names NROM, SONOS, and PHINES, for example. These memory cell structures store data by trapping charge in a charge trapping dielectric layer, such as silicon nitride. As negative charge is trapped, the threshold voltage of the memory cell increases. The threshold voltage of the memory cell is reduced by removing negative charge from the charge trapping layer.

NROM devices use a relatively thick bottom oxide, e.g. greater than 3 nanometers, and typically about 5 to 9 nanometers, to prevent charge loss. Instead of direct tunneling, band-to-band tunneling induced hot hole injection BTBTHH can be used to erase the cell. However, the hot hole injection causes oxide damage, leading to charge loss in the high threshold cell and charge gain in the low threshold cell. Moreover, the erase time must be increased gradually during program and erase cycling due to the hard-to-erase accumulation of charge in the charge trapping structure. This accumulation of charge occurs because the hole injection point and electron injection point do not coincide with each other, and some electrons remain after the erase pulse. In addition, during the sector erase of an NROM flash memory device, the erase speed for each cell is different because of process variations (such as channel length variation). This difference in erase speed results in a large Vt distribution of the erase state, where some of the cells become hard to erase and some of them are over-erased. Thus the target threshold Vt window is closed after many program and erase cycles and poor endurance is observed. This phenomenon will become more serious as the technology keeps scaling down.

A typical flash memory cell structure positions a tunnel oxide layer between a conducting polysilicon tunnel oxide layer and a crystalline silicon semiconductor substrate. The term “substrate” refers to a source region and a drain region separated by an underlying channel region. A flash memory read can be executed by a drain sensing or a source sensing. For source side sensing, one or more source lines are coupled to source regions of memory cells for reading current from a particular memory cell in a memory array.

FIG. 1is a block diagram illustrating a conventional source sensing memory circuit100with a main memory array120coupled to multiple reference mini-arrays140,141,142,143,144and146through a Y-pass gate130in a non-volatile memory with 1C:1C source side sensing scheme. The 1C:1C ratio denotes a single memory cell in the main memory array120as opposed to a single reference cell in a specific reference array. Sixty-four sense amplifiers SA0110, SA1111, . . . SA31112, SA32113, . . . SA62114and SA63115are typically required to perform a read operation. Each sense amplifier in the memory circuit100is associated with a reference cell in a particular reference mini-array and a source line. The specific connections are described as follows. The sense amplifier110receives a first input from a source line160connected to a memory cell121and a second input from a source line170connected to a reference cell150. The sense amplifier111receives a first input from a source line161connected to a memory cell122and a second input from a source line171connected to a reference cell151. The sense amplifier112receives a first input from a source line162connected to a memory cell123and a second input from a source line172connected to a reference cell152. The sense amplifier113receives a first input from a source line163connected to a memory cell124and a second input from a source line173connected to a reference cell153. The sense amplifier114receives a first input from a source line164connected to a memory cell125and a second input from a source line174connected to a reference cell154. The sense amplifier115receives a first input from a source line165connected to a memory cell126and a second input from a source line175connected to a reference cell155. A shortcoming of the memory circuit100is that the layout area will be large because each sense amplifier is associated with a particular reference mini-array and a particular source line coupled to the reference mini-array.

FIG. 2is a block diagram illustrating another conventional source sensing memory circuit200with the main memory array120coupled to shared reference mini-arrays210and220in the non-volatile memory with a 1C:1C source side sensing scheme. Each reference mini-array is shared among thirty-two sense amplifiers by an interconnect conductor bar. The reference mini-array210includes a reference cell211connected to a reference metal bit line212, which in turn is connected to an interconnect conductor bar230, which is in turn connected to a source line250and the first thirty-two sense amplifiers, SA0110, SA1111, . . . SA31112. The reference mini-array220includes a reference cell221connected to a reference metal bit line222, which is in turn connected to an interconnect bar240, which in turn is connected to a source line260and the next thirty-two sense amplifiers, SA32113, SA62114, . . . SA63115. The interconnect conductor bars230and240tend to be lengthy, typically longer than 1000 μm. Although the interconnect bars230and240provide the backbone for sharing a reference mini-array between thirty-two sense amplifiers, the addition of an interconnect bar and one additional metal line for connecting between each sense amplifier and the interconnect conductor bar contribute to an increase in capacitance to a source line coupled to a reference mini-array, producing undesirable capacitance mismatching between source lines in a main memory array cell and a mini-array reference cell, as well as inducing margin loss with a read high Vt or a read low Vt.

Therefore, there is a need for a non-volatile memory that provides source side sensing in which the dimension of the layout area is reduced while compensating for capacitance mismatching arising between source lines of a memory cell in the main memory array and reference cells in a reference mini-array.

SUMMARY OF THE INVENTION

Non-volatile memory circuits according to the present invention provide a reference memory having multiple reference cells that are shared among a group of sense amplifiers through an interconnect conductor line. The higher number of reference cells for each reference memory generates a greater amount of electrical current for charging multiple source lines. The multiple source lines are coupled to the interconnect conductor bar for capacitance matching with a source line coupled to a memory cell in a main memory array. After a silicon wafer out, measurements of the capacitance produced by the source line in the main memory array, and the capacitance produced by the source line in the reference array, are taken for an optional trimming. A further calibration in capacitance matching is achieved by trimming one of the source lines that is coupled to the interconnect conductor bar and the reference memory, either by cutting a portion of the source line or adding a portion to the source line.

Broadly stated, a non-volatile memory structure, comprises an interconnect conductor bar; a main memory having a first memory cell; a first reference array having two or more reference memory cells, the two or more reference memory cells connected to a reference conductor line; a first sense amplifier having a first input coupled to a first conductor bit line connected to the first memory cell in the main memory, and a second input coupled to the interconnect conductor bar and the reference conductor line in the two or more reference memory cells; and at least two source lines coupled to the interconnect conductor bar, the combination of the at least two source lines, the interconnect conductor bar, and the reference conductor line providing capacitance substantially matching to the first conductor bit line from the first memory cell in the main memory array.

In a first embodiment, a memory circuit with a 1C:2C source sensing scheme employs two reference arrays where each reference array includes two reference cells and two source lines. Having two reference cells in each reference array doubles the amount of cell current charged to the two source lines. The addition of the second source line coupled to a reference array keeps the ratio of metal bit line to source line coupled to a main memory array, matched well. Each reference array is shared among thirty-two sense amplifiers through an interconnect conductor bar. A pair of source lines are coupled to the interconnect conductor bar and a reference array to provide capacitance matching to a source line connected to a memory cell.

In a second embodiment, a trimming option is available after silicon wafer out for adjustment of a source line coupled to a reference array in the memory circuit with a 1C:2C source sensing scheme. After silicon wafer out, memory circuits are placed in test mode to measure the real source line differential between the source line from a main memory cells and the source line from reference memory cells. One of the source lines coupled to the reference array has several segments in the top portion of the source lines that can be cut by using a focused ion beam for reducing capacitance. If more capacitance is required on the reference array side, additional metal segments can be added to the one of the source lines coupled to the reference array.

In a third embodiment, a memory circuit with a 1C:3C source sensing scheme employs two reference arrays where each reference array includes three reference cells and three source lines. Three reference cells in each reference array triple the amount of cell current charged to the three source lines. The addition of the second and third source lines coupled to a reference array are to keep the ratio of metal bit line matched well with a source line coupled to a main memory array. Each reference array is shared among thirty-two sense amplifiers through the interconnect conductor bar. In this embodiment, one of the source lines coupled to the reference memory is also adjustable after the silicon wafer out, to reduce or increase the amount of capacitance on one of the source lines coupled to a reference array.

Advantageously, the present invention reduces the physical footprint in a layout area on an integrated circuit memory chip by sharing reference memories between sense amplifiers. The present invention further advantageously provides a flexible technique to match capacitance coupling to a sense amplifier with the option to trim, either by cutting or adding one or more segments in a source line among several source lines coupled to a reference memory.

The structures and methods of the present invention are disclosed in the detailed description below. This summary does not purport to define the invention. The invention is defined by the claims. These and other embodiments, features, aspects, and advantages of the invention will become better understood with regard to the following description, appended claims and accompanying drawings.

DETAILED DESCRIPTION OF EMBODIMENTS OF THE INVENTION

Referring now toFIG. 3, there is shown a simplified architectural diagram illustrating a non-volatile memory integrated circuit according to an embodiment of the present invention. The non-volatile memory integrated circuit300includes a memory array310implemented using localized charge trapping memory cells, on a semiconductor substrate. A row decoder320is coupled to a plurality of wordlines322arranged along rows in the memory array310. A column decoder330is coupled to a plurality of bitlines332arranged along columns in the memory array310. Addresses are supplied on bus334to column decoder330and row decoder320. Sense amplifiers and data-in structures in block340are coupled to the column decoder330via data bus342. Data is supplied via the data-in line344from input/output ports on the integrated circuit300, or from other data sources internal or external to the integrated circuit300, to the data-in structures in block340. Data is supplied via the data-out line346from the sense amplifiers in block340to input/output ports on the integrated circuit300, or to other data destinations internal or external to the integrated circuit300. A bias arrangement state machine350controls the application of bias arrangement supply voltages360, such as for the erase verify and program verify voltages, the first and second bias arrangements for programming and lowering the threshold voltage of the memory cells, and the third bias arrangement to change a distribution of charge in the charge trapping structure of a memory cell.

InFIG. 4, there is shown a simplified circuit diagram illustrating a first embodiment of a source sensing memory circuit400in a non-volatile memory with a 1C:2C source sensing scheme. In the 1C:2C source sensing scheme configuration, the ratio employs two reference memory cells in a reference array to one memory cell in a main memory array410. The reference mini-array440includes two reference cells441and442relative to a memory cell411, a memory cell412, or a memory cell413in the main memory array410. The reference mini-array450includes two reference cells451and452relative to a memory cell414, a memory cell415, or a memory cell416in the main memory array410.

There are a total of sixty-four sense amplifiers in the memory circuit100. The first thirty-two sense amplifiers, SA0430, SA1431. . . SA31432, share a first reference array440by coupling to a first interconnect conductor bar470, which in turn couples to source lines475and476. The next thirty-two sense amplifiers, SA32433, SA62434. . . SA63435, share a second reference array450by coupling through a second interconnect conductor bar480, which in turn couples to source lines485and486. The sense amplifiers SA0430, SA1431. . . SA63435may be implemented using a wide variety of differential sense amplifiers known to a person of skill in the art. The first interconnect conductor bar470provides a connection means to the first thirty-two sense amplifiers, but simultaneously contributes additional capacitance. To compensate for the increase in capacitance induced by the first interconnect conductor bar470, two sources lines475and476are connected to the first interconnect conductor bar470. The source lines485and486compensate for capacitance mismatching with the addition of the second interconnect conductor bar480.

The first sense amplifier SA0430has a first input coupled to a source line460connected to the memory cell411through a Y-pass gate420and a second input coupled to the first interconnect conductor bar470, which is coupled to reference cells441,442and source lines475,476. The source lines475and476couple to the interconnect conductor bar470through the Y-pass gate420. The second sense amplifier Sa1431has a first input coupled to a source line461connected to the memory cell412and a second input coupled to the first interconnect conductor bar470, which couples to reference cells441,442and source lines475,476. The thirty-first sense amplifier SA31432has a first input coupled to a source line462connected to the memory cell413and a second input coupled to the first interconnect conductor bar470, which couples to reference cells441,442and source lines475,476. The thirty-second sense amplifier SA32433has a first input coupled to a source line463connected to the memory cell414and a second input coupled to the first interconnect conductor bar470, which couples to reference cells441,442and source lines475,476. The sixty-third sense amplifier SA62434has a first input coupled to a source line464connected to the memory cell415and a second input coupled to the first interconnect conductor bar470, which couples to reference cells441,442and source lines475,476. The sixty-fourth sense amplifier SA63435has a first input coupled to a source line465connected to the memory cell416and a second input coupled to the first interconnect conductor bar470, which couples to reference cells441,442and source lines475,476.

One of the sense amplifiers compares two voltages to determine capacitance matching. For example, the sense amplifier SA1431compares a first voltage from a source side metal bit line461in a main memory array to source lines475,476from a reference array. The variables that affect source side sensing can be represented by the following the mathematical equation: Q=CV=IT, where the symbol Q denotes charge in capacitance, the symbol C denotes a bit line capacitance, the symbol V denotes the voltage change, the symbol I denotes the cell current, and the symbol T denotes the charging time. The first voltage from the source side metal bit line461and the second voltage from the source side metal bit line475,476are stored within Tsensing. If variables C and T are fixed, then the variable V will be proportional to the variable I. Consequently, the voltage difference between the source side metal bit line461and the source side metal bit lines475,476indicates the difference in the main memory cell current and the reference memory cell current. By controlling the reference memory cell current, it will determine the value of the voltage threshold, Vt, to be high/low or logic 1/logic 0.

When the process variation is significant, the ratio of the capacitance component will change, resulting in a capacitance mismatching between the source side metal bit line461in the main memory and the source side metal bit lines475,476in the reference memory. This is turn creates a difference in the build voltage between the source side metal bit line461in the main memory array and the source side metal bit lines475,476from a reference array. The read operation will fail if the voltage differential between the source side metal bit line461and the source side metal bit lines475,476is smaller than the design specification. Therefore, it is significant to produce capacitance matching in compensating for the process variation.

FIG. 5is a simplified circuit diagram illustrating a second embodiment of a source sensing memory circuit500in a non-volatile memory with a 1C:2C source side sensing scheme where one of the source lines can be trimmed. The source sensing circuit500is manufactured as part of a memory chip on a dice of a wafer. Each die can be put in a test mode to measure the real source line tracking performance. If result of the measurement produces capacitance mismatching which requires adjustment, a source line476bin the pair of sources lines475and476bis trimmed to a desirable length by using focused ion beam (FIB) trimming, thereby reducing the length of the source line476b.

FIG. 6, is a simplified circuit diagram illustrating a third embodiment of a source sensing memory circuit600in a non-volatile memory with a 1C:3C source side sensing scheme where one of the source lines can be trimmed. In the embodiment, the capacitance ratio of a metal bit line from the memory connected to a first input of a sense amplifier indicates that three source lines are required for suitable capacitance matching. A first reference array610has three reference memory cells611,612, and613that correspond to one memory cell, e.g. the memory cell412, in the main memory array410. The reference array610couples to the interconnect conductor bar470and three source lines630,631and632. A second reference array620includes three reference memory cells621,622and623that correspond to a memory cell, e.g. the memory cell414, in the main memory array410. The reference array620couples to the interconnect conductor bar480and three source lines640,641and642. In this embodiment, the source line632is trimmed after measurement has been taken for capacitance mismatching after a silicon wafer out. The source line642is also trimmed after measurement has been taken for capacitance mismatching after the silicon wafer out.

Turning now toFIG. 7, there is shown a flow chart illustrating the process700for adjusting a source line in a plurality of source lines coupled to a reference array in a non-volatile to attain capacitance matching between metal bit lines from the main memory array and the reference array. At step710, non-volatile memory circuits on dice of a silicon wafer have been manufactured. After putting the integrated circuit chips in test mode, at step720, one measurement is taken of the capacitance of the metal bit line from a main memory array (Ccell bl) and another measurement is taken on the capacitance of the metal bit line from a reference array (Crefcell bl). At step730, the measurement value of the metal bit line capacitance from a main memory array is compared to the measurement value of the metal bit line capacitance from a reference array to determine if there is matching capacitance. If the metal bit line capacitance from the main memory array does not match the metal bit line capacitance from the reference array, at step740, the focused ion beam technique is used to adjust a source line in a plurality of source lines coupled to a reference mini-array by either cutting one or more segments from the source line, or adding one or more segments to the source line. If the result produces a capacitance mismatching because the metal bit line capacitance from the reference array is greater than the metal bit line capacitance from the main memory array, the process700cuts one or more segments in the top portion of a source line in the multiple source lines coupled to the reference array by using a focused ion beam. However, if the result produces a capacitance mismatching because the metal bit line capacitance from the reference array is less than the metal bit line capacitance from the main memory array, the process700adds one or more segments to the top portion of a source line in the multiple source lines coupled to the reference array by using a focused ion beam. If the process700determines at step730that there is capacitance matching between the metal bit line from the main memory array and the metal bit line from the reference array, the process700is completed at step750.

At step760, the measurement value of the metal bit line capacitance from the main memory array is once again compared to the measurement value of the metal bit line capacitance from the reference array. The measurement value of the metal bit line capacitance from a main memory array is compared at step770to the measurement value of the metal bit line capacitance from a reference array to determine whether there is a matching capacitance. If the metal bit line capacitance from the main memory array does not match the metal bit line capacitance from the reference array, the process700routes to step740. If the metal bit line capacitance from the main memory array matches the metal bit line capacitance from the reference array, the mask is modified before returning to the initial step710.

FIG. 8is a block diagram illustrating the source side trimming800in a non-volatile memory for capacitance matching in a 1C:2C source side sensing scheme. The total amount of capacitance in the source line trimming800includes the first source line475, the second source line476, the interconnect conductor bar470and other parasitic capacitance such as junction capacitance and gate capacitance. The top portion of the second source line476is cut into five segments476-1,476-2,476-3,476-4and476-5. The total capacitance on the source side can be reduced by trimming one or more of the five segments476-1,476-2,476-3,476-4and476-, but can also be increased by connecting additional metal to the second source line476.

FIG. 9Ais a more detailed block diagram illustrating a source sensing memory circuit900that corresponds to the second embodiment of the present invention as shown inFIG. 5. The interconnect conductor bar470and source lines475,476bon the metal bit line on the reference array source side910are further depicted inFIG. 9B. The interconnect conductor bar470is connected to all sense amplifiers on the reference memory. The source lines475and476bare connected to an array for source sensing charging capacitance, as shown by the symbol RMBL2inFIG. 10.

FIG. 10shows a more detailed schematic diagram of a reference mini-array1000in a non-volatile memory with 1C:2C sensing scheme. The reference mini-array1000comprises a matrix of reference cells in which reference cells1010and1012are selected for implementing the 1C:2C sensing scheme. Alternatively, a third reference cell can be selected for implementing a 1C:3C sensing scheme. The selection of the reference cells1010and1012is made by a pair of select lines RSEL01020and RSEL11022. The gate voltage to the reference cells1010and1012is supplied from a signal line RWL1030. The reference cells1010and1012are connected a source line RMBL21040for external connection to an interconnect conductor bar. In this embodiment, source lines RMBL01042, RMBL41044and RMBL61046have been left floating. Similarly, drain signals RMBL11050, RMBL31052, RMBL51054and RMBL71056have also been left floating in this configuration.

The term “source line” as used in the specification refers to elements related to a source line, including a metal bit line, a local bit line and a bit line transistor (BLT) contact junction number. A large amount of capacitance in a source line derives from a metal bit line.

The invention has been described with reference to specific exemplary embodiments. Various modifications, adaptations, and changes may be made without departing from the spirit and scope of the invention. For example, one of ordinary skill in the art should recognize that additional reference memory cells in a reference array can be added to construct a 1C:MC configuration. Correspondingly, the number of source lines coupled to the reference memory can be increased to N, where M and N could be the same or different integer numbers. Accordingly, the specification and drawings are to be regarded as illustrative of the principles of this invention rather than restrictive, the invention is defined by the following appended claims.