Method for forming high density nonvolatile memories with high capacitive-coupling ratio

A method for fabricating a high speed and high density nonvolatile memory cell is disclosed. First, a semiconductor substrate with defined field oxide and active region is prepared. A stacked silicon oxide/silicon nitride layer is deposited and then the tunnel oxide region is defined. A thick thermal oxide is grown on the non-tunnel region. After removing the masking silicon nitride layer, the source and drain are formed by an ion implantation and a thermal annealing. The pad oxide film is etched back, and a metal silicide film is formed and then stripped. A topography of the doped substrate region is then made rugged. Thereafter, a thin oxide is grown on the rugged doped substrate region to form a rugged tunnel oxide. Finally, the floating gate, the interpoly dielectric, and the control gate are sequentially formed, and the memory cell is finished.

FIELD OF THE INVENTION
 The present invention relates to a method for fabricating a nonvolatile
 memory cell, and more especially, to a method for fabricating rugged
 tunnel oxide with high electron injection efficiency and a large
 charge-to-breakdown for low power nonvolatile memory.
 BACKGROUND OF THE INVENTION
 Nonvolatile memories, including mask read-only memories (Mask ROM),
 programmable ROM (PROM), erasable programmable ROM (EPROM), electrically
 erasable programmable ROM (EEPROM or E.sup.2 PROM) and flash memories,
 retain their memory data whenever the power is turned off, and have wide
 applications in the computer and electronic industry. In recent years, the
 markets of the portable computers and telecommunications have developed
 rapidly and have become a major driving force in the design and technology
 of the semiconductor integrated circuit. As stated by A. Bergemont, et
 al., in "Low Voltage NVG.TM.: A New High Performance 3 V/5 V Flash
 Technology for Portable Computing and Telecommunications Application",
 IEEE Trans. Electron Devices Vol. 43, p. 1510 (1996), there is a great
 need for low power, high density, and electrically re-writable nonvolatile
 memories. That is, the memories programmable and erasable as EPROM,
 E.sup.2 PROM or flash memories are required for the aforementioned systems
 to store operating systems or application software.
 The basic storage cell of these programmable and erasable memories contains
 a double polysilicon storage transistor with a floating gate isolated in
 silicon dioxide and capacitively coupled to a second control gate which is
 stacked above it. The E.sup.2 PROM cell further comprises an access, or
 select, transistor. These memories execute the programming and erasure by
 charging or discharging their floating gates. For example, the EPROM is
 programmed by hot electron injection at the drain to selectively charge
 the floating gate and erased by discharging the floating gate with
 ultraviolet light or X-ray, which the latter has never been commercially
 applied for this purpose. The E.sup.2 PROM and most of the flash memories
 are programmed by hot electron injection or cold electron tunneling named
 Fowler-Nordheim tunneling, and erased mostly by Flower-Nordheim tunneling
 from the floating gate to the source, with the control gate ground.
 Flower-Nordheim tunneling, or cold electron tunneling, is a
 quantum-mechanical effect, which allows the electrons to pass through the
 energy barrier at the silicon-silicon dioxide interface at a lower energy
 than required to pass over it. H. Shirai, et al., stated in their paper "A
 0.54 .mu.m.sup.2 Self-Aligned, HSG Floating Gate Cell for 256 Mbit Flash
 Memories", IEDM Tech. Dig. Vol. 95, p. 653 (1995) that, because of its low
 current consumption, the Fowler-Nordheim program/erase scheme becomes
 indispensable for low power operation of the E.sup.2 PROM and flash
 memories. However, the Fowler-Nordheim program/erase scheme requires high
 voltage applied to control gate of the memory cell. This high voltage is
 needed for inducing a large reversible electric field to the thin oxide
 that separates the floating gate from the substrate. Therefore, to lower
 the control gate bias, the memory cell must have a high
 capacitive-coupling ratio structure.
 Y. S. Hisamune, et al., propose a method for fabricating a flash memory
 cell with contactless array and high capacitive-coupling ratio in "A High
 Capacitive-Coupling Ratio Cell for 3 V-Only 64 Mbit and Future Flash
 Memories", IEDM Tech. Dig. Vol. 93, p. 19 (1993). However, this method
 achieves high capacitive-coupling ratio with four times polysilicon
 deposition and has a complex fabrication. In addition, this cell structure
 makes it difficult to scale the size down and increase the integration of
 the memory due to its short tunnel oxides. Furthermore, as mentioned by C.
 J. Hegarty, et al., in "Enhanced Conductivity and Breakdown of Oxides
 Grown on Heavily Implanted Substrates", Solid-State Electronics, Vol. 34,
 p. 1207 (1991), it is also difficult to fabricate a thin tunnel oxide on
 the heavily doped substrate with a high electron injection efficiency and
 a large charge-to-breakdown for low power nonvolatile memories. Thus, to
 reach high capacitive-coupling ratio, high electron injection efficiency
 and a large charge-to-breakdown with a simple manufacture is the subject
 of high density and low power nonvolatile memories today.
 SUMMARY OF THE INVENTION
 A method for fabricating a nonvolatile memory cell with rugged tunnel oxide
 is disclosed. First, the field oxide is formed, the active region is
 defined, and a semiconductor substrate is prepared. A stacked silicon
 oxide/silicon nitride layer is deposited on the substrate and then the
 tunnel oxide region is defined by a standard photolithography process
 followed by an anisotropic etching. A high temperature steam oxidation
 process is used to grow a thick thermal oxide on the non-tunnel region.
 After removing the masking silicon nitride layer, the phosphorus ions are
 implanted to form the doped regions and serve as source and drain, then a
 thermal annealing is performed to recover the implantation damage and to
 drive in the doped ions. Next, the pad oxide film is etched back, and a
 metal silicide film is formed and then stripped. A rugged topography of
 the doped substrate region is then formed. Thereafter, a thin oxide is
 grown on the rugged doped substrate region to form a rugged tunnel oxide.
 Finally, the first n+ doped polysilicon film which serves as the floating
 gate, the interpoly dielectric such as NO or ONO, and the second n+ doped
 polysilicon film which serves as the control gate are sequentially formed,
 and the memory cell is finished.

DESCRIPTION OF THE PREFERRED EMBODIMENT
 The present invention proposes a simple method to fabricate a nonvolatile
 memory cell with high capacitive-coupling ratio. The method described here
 includes many process steps well known in the art like photolithography,
 etching or chemical vapor deposition (CVD) which are not discussed in
 detail. In addition, the present invention utilize a method for forming a
 rugged tunnel oxide to attain high electron injection efficiency and a
 large charge-to-breakdown for low power nonvolatile memories.
 Referring to FIG. 1, a single crystal silicon substrate 2 with a &lt;100&gt;
 crystallographic orientation is provided. A silicon oxide layer 4 is
 formed on the surface of the substrate 2. In addition to a pad oxide for
 the oxidation mask, the silicon oxide layer 4 can be used to act as a
 sacrificial oxide to prevent the channel effect during the later ion
 implantation. This pad oxide layer 4 has a thickness of about 40-300
 angstroms, and can be grown by using thermal oxidation at a temperature of
 about 800-1100.degree. C., or using low pressure chemical vapor deposition
 (LPCVD) at a temperature of about 400-750.degree. C. Next, a thick silicon
 nitride layer 6 is deposited, for example, using a LPCVD process at a
 temperature of about 700-800.degree. C., on the pad oxide layer 4 to serve
 as an oxidation mask.
 The field oxide (FOX) pattern is now defined using a conventional manner of
 photolithography including photoresist coating, exposure, and development
 processes, and then a dry etching is carried out to etch the thick silicon
 nitride layer 6 and the pad oxide layer 4. After photoresist is removed
 and wet cleaned, a thermal oxidation in an oxygen steam environment is
 performed, and the thick field oxide regions 8 are grown with a thickness
 of about 3000-8000 angstroms to provide isolation between active regions
 on the substrate 2. Then, the silicon nitride layer 6 is optionally
 removed, and a new silicon nitride layer 10 is created over the substrate
 2.
 Turning next to FIG. 2, another photolithography process is used to define
 the tunnel oxide region. An etching step follows to selectively etch the
 silicon nitride layer 10 but not the pad oxide layer 4 and expose a
 portion of the pad oxide layer 4 which defines the non-tunnel region on
 the active region. This selectivity can be reached by a dry etching
 process using NF.sub.3 as the plasma source or by a wet etching process
 using hot phosphoric acid as the etching solution. It is noted that the
 wet etching will cause the undercut. A high temperature steam oxidation is
 then performed at a temperature of about 800-1100.degree. C. to grow a
 thick thermal oxide 12 on the non-tunnel region, as shown in FIG. 3. This
 thermal oxide 12 has a thickness of about 300-2500 angstroms, and can
 raise the capacitive-coupling ratio of the memory cell.
 Turning next to FIG. 4, the masking silicon nitride film 10 is removed by
 wet etching with hot phosphoric acid. An n+ ion implantation is performed
 to implant appropriate impurity ions through the silicon oxide layer 4,
 but not the thick oxide 12, into the substrate 2 to form doped substrate
 region 14 and serve as the source and drain. The implanted ions can be
 phosphorus ions, arsenic ions or antimony ions. The implantation energy
 and dosage are respectively about 0.5-150 keV and about 5.times.10.sup.14
 -5.times.10.sup.16 atoms/cm.sup.2. During the ion implantation, the
 silicon oxide layer 4 act as a buffer to prevent the substrate 2 from
 damage and to prevent the doped ions from channel effect. The substrate 2
 is then thermal annealed to recover the implantation damage by a
 preferable method as rapid thermal processing (RTP) at a temperature of
 about 800-1150.degree. C. The dopants are activated and driven in to form
 the best distribution profile at this step, as shown in FIG. 5. The
 silicon oxide 4 is now removed, with a suitable etchant such as buffered
 oxide-etching (BOE) solution or diluted solution of hydrofluoric acid
 (HF).
 Next, a sacrificial metal silicide film 16 is formed over the doped regions
 14 of the substrate 2. For one embodiment, the sacrificial metal silicide
 film 16 can be formed by metal deposition, such as sputtering, followed by
 a thermal process, such as high temperature annealing or rapid thermal
 processing (RTP). A metal such as titanium (Ti), tungsten (W), tantalum
 (Ta), Nickel (Ni), molybdenum (Mo), cobalt (Co), and so on, can be used as
 the material of precursory metal. The deposition process of precursory
 metal can be chosen to be either blanket or selective deposition, for
 example, blanket tungsten deposition or selective tungsten deposition.
 FIG. 6 illustrates a cross-sectional view of the substrate after a silicide
 forming with selective metal deposition. The embodiment with blanket metal
 deposition will have the same situation and produce the same topography
 right above the exposed substrate region 14. As illustrated in FIG. 6, a
 rugged interface between silicon and silicide can be formed under a
 suitable process condition, such as a certain substrate temperature
 (depending on the precursory metal used) during annealing.
 Thereafter, the sacrificial metal silicide film 16 is stripped by a
 suitable etching process. The etching recipe should be applied depending
 on the metal precursor used. For one embodiment, a wet etching is used,
 and NH.sub.4 OH/H.sub.2 O.sub.2 /H.sub.2 O solution can be applied to act
 as the etchant for etching WSi.sub.2, TiSi.sub.2, and CoSi.sub.2. After
 the sacrificial metal silicide film 16 is stripped, the doped substrate
 region 14 is then exposed with rugged surface as shown in FIG. 7.
 Referring to FIG.8, a thin oxide layer 18 is now formed on the rugged doped
 region 14. The thin oxide layer 18 can be formed by thermal oxidation
 performed in a dry oxygen ambience at a temperature of about
 750-1050.degree. C., or by a chemical vapor deposition (CVD).
 Alternatively, a nitridation followed by a re-oxidation can be applied to
 form this oxide layer 18. With underlying rugged surface of the doped
 substrate region, a rugged tunnel oxide 18 is then formed, and a rugged
 Si/SiO.sub.2 interface is obtained. As mentioned by S. L. Wu et al., in
 "Characterization of Thin Textured Tunnel Oxide Prepared by Thermal
 Oxidation of Thin Polysilicon Film on Silicon", IEEE Trans. Electron
 Devices, Vol. 43, p. 287 (1996), this rugged interface will result in
 localized high electric field and subsequently enhance the electron
 injection from the substrate 2 into oxide. Thus, the rugged tunnel oxide
 exhibits higher electron-injection efficiency, a significantly lower
 charge trapping rate, and a large charge-to-breakdown in comparison with
 the conventional tunnel oxide.
 Next, referring to FIG. 9, the conductive layer 20 is deposited on the
 substrate 2 preferably with a material of doped or in-situ doped n+
 polysilicon by using a conventional LPCVD. A standard photolithography
 process is used to define the floating gate pattern. An anisotropic
 etching with Cl.sub.2, HBr or SiCl.sub.4 as the plasma source is then
 carried out to etch the conductive layer, thereby the floating gate 20 is
 formed on the active region and a portion of the field oxide region.
 The ultra-thin interpoly dielectric (IPD) layer 22 deposited on the surface
 of the floating gate 20 is shown in FIG. 10. This interpoly dielectric
 layer 22 can be a material of a double film of silicon nitride and silicon
 oxide (NO), a triple film of silicon oxide, silicon nitride and silicon
 oxide (ONO), or any other high dielectric constant film such as tantalum
 pentoxide (Ta.sub.2 O.sub.5) or barium strontium titanate (BST). Finally,
 referring to FIG. 11, another conductive layer formed of doped or in-situ
 doped n+ polysilicon is deposited and patterned on the interpoly
 dielectric layer 22 to serve as the control gate 24. Thus, the nonvolatile
 memory cell with rugged tunnel oxide is finished according to the present
 invention.
 As is understood by a person skilled in the art, the foregoing preferred
 embodiments of the present invention are illustrative of the present
 invention rather than limiting of the present invention. They are intended
 to cover various modifications and similar arrangements included within
 the spirit and scope of the appended claims, the scope of which should be
 accorded the broadest interpretation so as to encompass all such
 modifications and similar structure.