A transistor circuit outputs a drive current in accordance with a data signal. An OLED that is connected to the transistor circuit emits light with luminance corresponding to the drive current. A discharge transistor, when the OLED does not emit the light, is turned on to connect a discharge feeder line to a node at which the transistor circuit is connected to the OLED. An absolute value of a threshold voltage of the discharge transistor is lower than an absolute value of a threshold voltage of a drive transistor in the transistor circuit. When the data signal indicates zero, the discharge transistor can cause a flow of the drive current from the transistor circuit to bypass the OLED.

BACKGROUND

1. Technical Field

The present invention relates to a pixel circuit, an electro-optical device, and an electronic apparatus.

2. Related Art

To date, various electro-optical devices that include light emitting elements such as organic light emitting diodes (OLEDs) have been proposed. An electro-optical device of this type typically has pixel circuits in relation to pixels of an image to be displayed. These pixel circuits are disposed at the intersections of scan lines and data lines and each include a light emitting element and a transistor circuit. This transistor circuit supplies the light emitting element with a drive current whose magnitude is proportional to a data signal that indicates luminance of a corresponding light emitting element.

SUMMARY

Pixel circuits, as described above, usually need to create clear black images. For that purpose, when the data signal indicates zero, the transistor circuit in a pixel circuit has to completely stop supplying the drive current to the light emitting element so that the light emitting element does not emit light.

When no drive current is supplied to the light emitting element, however, a leakage current may still flow from the transistor circuit to the light emitting element. As a result, the light emitting element might emit weak light, causing the so-called black floating, which is a phenomenon in which a black image is not created clearly.

JP-A-2010-243560 discloses a technique for discharging electric charge from the connection node between a transistor circuit and a light emitting element when the light emitting element does not emit light. JP-A-2013-088611 discloses a technique for suppressing an occurrence of the black floating, in which a bypass element is provided between a reference potential line and an end of a light emitting element which is closer to a transistor circuit. When the light emitting element does not emit light, a leakage current flows from the transistor circuit to this bypass element.

Unfortunately, the former technique may fail to address the problem associated with the black floating, because pixel circuits in micro displays and other related displays have small-capacitance light emitting elements. While such a light emitting element is not emitting light, electric charge may be excessively accumulated in the capacitance of the light emitting element, and as a result the leakage current might flow through the light emitting element, causing the black floating. Furthermore, both of the above techniques are intended to cause the flow of a leakage current from the transistor circuit to bypass the light emitting element when the light emitting element does not emit light. However, the techniques may fail to suppress an occurrence of the black floating effectively when the light emitting element emits light.

An advantage of some aspects of the invention is that a pixel circuit, an electro-optical device, and an electronic apparatus are all effective in suppressing an occurrence of the black floating.

A pixel circuit according to a first aspect of the invention includes: a transistor circuit that outputs a drive current in accordance with a data signal; a light emitting element that is connected to the transistor circuit and emits light with luminance corresponding to the drive current; and a discharge section that, when the data signal indicates zero, causes a flow of the drive current to bypass the light emitting element.

According to this aspect, when the data signal indicates zero, the discharge section stops the drive current output from the transistor circuit from flowing to the light emitting element. Thus, this configuration is effective in suppressing an occurrence of the black floating.

It is preferable that the transistor circuit include a drive transistor that generates the drive current in accordance with the data signal. It is preferable that the discharge section include a discharge transistor that, when the light emitting element does not emit the light, is turned on to connect a discharge feeder line to a node at which the transistor circuit is connected to the light emitting element. It is preferable that an absolute value of a threshold voltage of the discharge transistor be lower than an absolute value of a threshold voltage of the drive transistor.

According to this aspect, the absolute value of the threshold voltage of the discharge transistor is set to be lower than the absolute value of the threshold voltage of the drive transistor. In this case, when the data signal indicates zero, the discharge transistor in an off state can drive a current that is larger in amount than the drive current output from the transistor circuit. Thus, this configuration is more effective in suppressing an occurrence of the black floating.

It is preferable that the discharge transistor have a shorter channel length than that of the drive transistor.

According to this aspect, when the data signal indicates zero, the discharge transistor in an off state can drive a current that is larger in amount than the drive current output from the transistor circuit. Thus, this configuration is more effective in suppressing an occurrence of the black floating.

It is preferable that the drive transistor be a P-channel transistor and that the discharge transistor be an N-channel transistor.

According to this aspect, the current output from the transistor circuit flows into the p well of the N-channel discharge transistor through its drain. By the amount of this current, the amount of a current bypassing the light emitting element and flowing through the discharge section can be increased. Thus, this configuration is more effective in suppressing an occurrence of the black floating.

It is preferable that a drain of the discharge transistor which is connected to the light emitting element have a wider area than that of a source of the discharge transistor.

According to this aspect, a larger amount of current can flow from the drain into the p well of the discharge transistor. Thus, this configuration is more effective in suppressing an occurrence of the black floating.

It is preferable that the transistor circuit include a light emission control transistor connected between the drive transistor and the light emitting element. It is preferable that the light emission control transistor be a P-channel transistor. It is preferable that a drain of the discharge transistor have a wider area than a total area of a drain and source of the light emission control transistor.

According to this aspect, the leakage current that flows from the n well to source of the P-channel light emission control transistor and the leakage current that flows from the n well to drain of the P-channel light emission control transistor through the pn junction are added to the current output from the transistor circuit. In addition, the area of the drain of the N-channel discharge transistor is set to be larger than the total area of the drain and source of the light emission control transistor. In this case, the current flowing from the drain into the p well of the discharge transistor is larger in amount than the leakage current flowing from the n well to the source and drain of the light emission control transistor through the pn junction. Thus, this configuration is more effective in suppressing an occurrence of the black floating.

It is preferable that the transistor circuit include a drive transistor that generates the drive current in accordance with the data signal. It is preferable that the discharge section include a discharge transistor that, when the light emitting element does not emit the light, is turned on to connect a discharge feeder line to a node at which the transistor circuit is connected to the light emitting element. It is preferable that the drive transistor be an enhancement type transistor and that the discharge transistor be a depletion type transistor.

According to this aspect, the drive transistor is an enhancement type transistor, and the discharge transistor is a depletion type transistor. When the data signal indicates zero, the discharge transistor in an off state can drive a current that is larger in amount than the drive current output from the transistor circuit. Thus, this configuration is more effective in suppressing an occurrence of the black floating.

An electro-optical device according to a second aspect includes the pixel circuit according to one of the above aspects.

According to this aspect, this configuration is effective in suppressing the black floating from occurring in the electro-optical device.

An electronic apparatus according to a third aspect includes the above electro-optical device. Examples of the electronic apparatus include a head mount display and a projector.

A pixel circuit according to a fourth aspect includes a transistor circuit that outputs a drive current in accordance with a data signal; a light emitting element that is connected to the transistor circuit and emits light with luminance corresponding to the drive current, the light emitting element; and in a light emission period, a discharge section that causes a flow of a part of the drive current.

A pixel circuit according to a fifth aspect includes: a transistor circuit that outputs a drive current in accordance with a data signal; a light emitting element that is connected to the transistor circuit and emits light with luminance corresponding to the drive current; and a discharge transistor that is turned off to cause a flow of a part of the drive current.

DESCRIPTION OF EXEMPLARY EMBODIMENTS

First Embodiment

FIG. 1is a perspective view of a configuration of an electro-optical device1according to a first embodiment of the invention. As an example, the electro-optical device1may be a micro display device in a head mount display (HMD) which displays images. As another example, the electro-optical device1may be an organic EL device in which a plurality of pixel circuits and drive circuits that drive the pixel circuits are mounted on a silicon substrate. Each pixel circuit has an organic light emitting diode (OLED), which is an example of a light emitting element.

The electro-optical device1includes a display panel10and a control circuit3. The display panel10is mounted in a casing72having a frame and an opening in a display section. This display panel10is connected to an end of a flexible printed circuit (FPC) substrate74. The control circuit3is mounted on the FPC substrate74by means of a chip on film (COF) technique. This control circuit3may be implemented using a semiconductor chip. The control circuit3is connected to an unillustrated upstream circuit through a plurality of terminals76.

FIG. 2is a block diagram illustrating a configuration of the electro-optical device1. As described above, the display panel10and the control circuit3are mounted in the electro-optical device1.

The upstream circuit supplies digital image data Vdata and a synchronizing signal to the control circuit3; the image data Vdata and the synchronizing signal are synchronized together. The image data Vdata may be, for example 8-bit data that specifies gradation levels of the pixels in an image to be displayed on the display panel10by a display section100(described later). The synchronizing signal may contain a vertical synchronizing signal, a horizontal synchronizing signal, and a dot clock signal.

The control circuit3generates various control signals on the basis of the synchronizing signal and supplies these control signals to the display panel10. More specifically, the control circuit3supplies control signals Ctr, a positive logic control signal Gref, and a negative logic control signal /Gini, control signals Sel(1), Sel(2), and Sel(3), /Sel(l), /Sel(2), and /Sel(3). The positive logic control signal Gref is equivalent to the logical inversion of the negative logic control signal /Gini. The control signal Sel(1) is equivalent to the logical inversion of the control signal /Sel(l). The control signal Sel(2) is equivalent to the logical inversion of the control signal /Sel(2). The control signal Sel(3) is equivalent to the logical inversion of the control signal /Sel(3). Each control signal Ctr contains a plurality of signals, including a pulse signal, a clock signal, and an enable signal. Hereinafter, the control signals Sel(l), Sel(2), and Sel(3) may be collectively referred to as the control signals Sel. Likewise, the control signals /Sel(l), /Sel(2), and /Sel(3) may be collectively referred to as the control signals /Sel.

The control circuit3includes a voltage generating circuit. This voltage generating circuit applies various electric potentials to the display panel10. More specifically, the control circuit3applies a potential Vorst, an initial potential Vini, and a potential Vref to the display panel10.

The control circuit3generates an analog image signal Vid on the basis of the image data Vdata. More specifically, the control circuit3has a lookup table in which a potential indicated by the image signal Vid is related to luminance of the light emitting elements in the display panel10; the light emitting elements may be OLEDs130that will be described later. The control circuit3refers to the lookup table and then generates the image signal Vid indicating a potential related to the luminance of the light emitting elements which is specified by the image data Vdata. Then, the control circuit3supplies the image signal Vid to the display panel10.

As illustrated inFIG. 2, the display panel10includes the display section100, a data transfer line drive circuit5, and a scan line drive circuit20.

In the display section100, a plurality of pixel circuits110are arranged in a matrix fashion and in relation to the pixels of an image to be displayed. More specifically, in the display section100, m rows of scan lines12extend along the short side of the page ofFIG. 2, and 3n columns of data lines14extend along the long side of the page. Out of these data lines14, three data lines14make each group. The scan lines12and the data lines14are electrically isolated from each other. At the intersections between the scan lines12and the data lines14are the pixel circuits110provided. In this embodiment, thus, the pixel circuits110are arranged in the form of a matrix with m rows and 3n columns.

Each of the numbers m and n may be any natural number. To differentiate the individual rows in the matrices of the scan lines12and the pixel circuits110, the rows may be referred to below as the first, second, third . . . (m−1)th, and m-th rows in the order from the upper side of the page ofFIG. 2. Likewise, to differentiate the individual columns in the matrices of the data lines14and the pixel circuits110, the columns may be referred to below as the first, second, third . . . (3n−1)th, and (3n)th columns in the order from the left side of the page ofFIG. 2. For example, if any one of the groups made by the data lines14is denoted by a j-th group (j is any integer ranging from 1 to n), this j-th group contains the data lines14of (3j−2)th, (3j−1)th, and 3j-th columns.

Three pixel circuits110are provided at the intersections between a single scan line12and three data lines14in the same group. These pixel circuits110are related to three colors, namely, red, green, and blue and each form a dot of a color image to be displayed. In this embodiment, the OLEDs130emit red light, green light, and blue light, forming a single color dot in an additive color manner.

In this embodiment, along the data lines14are provided feeder lines16, which serve as discharge feeder lines for individual columns. The control circuit3applies the potential Vorst to all the feeder lines16as a discharge potential. In addition, each column is provided with a capacitor50. More specifically, first ends of the capacitors50are connected to the corresponding data lines14, whereas second ends of the capacitors50are connected to the corresponding feeder lines16. In short, each capacitor50functions as a second capacitor that retains a potential of a corresponding data line14.

Each capacitor50preferably has a structure in which an insulator or a dielectric is formed between wires of a data line14and a feeder line16.

Referring toFIG. 2, as an example, the capacitors50are provided outside the display section100. As an alternative example, the capacitors50may be provided either inside the display section100or from the inside to outside of the display section100. The capacitance of each capacitor50may be denoted by Cdt, which is not described inFIG. 2.

The data transfer line drive circuit5includes a demultiplexer30, a data transfer circuit40, and a data signal supply circuit70. The data signal supply circuit70outputs data signals Vd(1), Vd(2) . . . Vd(n) to first, second . . . n-th blocks, respectively, in accordance with selection timings of the demultiplexer30. Each of the data signals Vd(1), Vd(2) . . . Vd(n) indicates a potential ranging from a minimum potential Vmin to a maximum potential Vmax.

The scan line drive circuit20sequentially selects the plurality of pixel circuits110arranged in a matrix fashion and controls the operations of these pixel circuits110. The scan line drive circuit20repeatedly sequentially selects the pixel circuits110row by row. More specifically, the scan line drive circuit20generates scan signals used to sequentially scan the scan lines12over a frame period1F, in accordance with a control signal Ctr. The frame period1F corresponds to a period over which the electro-optical device1displays a frame of an image. For example, if the vertical synchronizing signal contained in the synchronizing signal has a frequency of 120 Hz, the frame period1F is approximately 8.3 ms, which is equivalent to one period of the vertical synchronizing signal. Hereinafter, scan signals supplied to the scan lines12on the first, second, third . . . (m−1)th, and m-th rows may be denoted by Gwr(1), Gwr(2), Gwr(3) . . . Gwr(m−1), and Gwr(m), respectively. In addition, the scan line drive circuit20causes each pixel circuit110to perform a current value setting operation and a light emitting operation. In the current value setting operation, each pixel circuit110sets a value of a drive current to be supplied to the OLED130within the frame period1F between when a pixel circuit110is selected and this pixel circuit110is selected again. In the light emitting operation, each pixel circuit110supplies a current to the OLED130with an emission of light.

To control the operations of the pixel circuits110described above, the scan line drive circuit20generates, in addition to the scan signals Gwr(1) to Gwr(m), various control signals for respective rows in synchronization with the scan signals. Then, the scan line drive circuit20supplies the generated control signals to the display section100. It should be noted that these control signals are not illustrated inFIG. 2.

The demultiplexer30includes a plurality of groups of transmission gates34provided on the respective columns. The demultiplexer30sequentially supplies data signals to the three rows in each group.

The transmission gates34on the (3j−2)th, (3j−1)th, and (3j)th columns which belong to the j-th group have a common input terminal to which the data signal Vd(j) is to be supplied.

When the control signal Sel(1) is at the H level, in other words, when the control signal /Sel(1) is at the L level, the transmission gate34on the leftmost column, or on the (3j−2)th column, in the j-th group is turned on to conduct electricity. Likewise, when the control signal Sel(2) is at the H level, in other words, when the control signal /Sel(2) is at the L level, the transmission gate34on the central column, or the (3j−1)th column, in the j-th group is turned on to conduct electricity. When the control signal Sel(3) is at the H level, in other words, when the control signal /Sel(3) is at the L level, the transmission gate34on the rightmost row, or the 3j-th row, in the j-th group is turned on to conduct electricity.

The data transfer circuit40includes a capacitor44, a P-channel metal oxide semiconductor (MOS) transistor45, and an N-channel MOS transistor43on each column. The data transfer circuit40shifts the potentials of the data signals output from the output terminals of the transmission gates34on the respective columns. A first end of each capacitor44is connected to both the data line14and the drain node of the P-channel MOS transistor45on a corresponding column, whereas a second end of each capacitor44is connected to both the output terminal of the transmission gate34and the drain node of the N-channel MOS transistor43on the corresponding column. In short, each capacitor44functions as a first capacitor having an end connected to the corresponding data line14. The capacitance of each capacitor44is denoted by Crf1, which is not described inFIG. 2.

The source nodes of the P-channel MOS transistors45on the respective columns are connected to the feeder line61through which the potential Vini is applied as the initial potential, whereas the gate nodes of the P-channel MOS transistors45on the respective rows are supplied with the control signal /Gini. Thus, the P-channel MOS transistors45electrically connect the data lines14to the feeder line61when the control signal /Gini is at the L level and electrically disconnect the data lines14from the feeder line61when the control signal /Gini is at the H level.

The source nodes of the N-channel MOS transistors43on the respective columns are connected to a feeder line62through which the potential Vref is applied as a predetermined potential, whereas the gate nodes of the N-channel MOS transistors43on the respective rows are supplied with the control signal Gref. In short, the N-channel MOS transistors43electrically connect the second ends, or nodes h, of the capacitors44to a feeder line62when the control signal Gref is at the H level and electrically disconnect the nodes h of the capacitors44from the feeder line62when the control signal Gref is at the L level.

For the sake of convenience, in this embodiment, the scan line drive circuit20, the demultiplexer30, and the data transfer circuit40are separated from one another; however, the scan line drive circuit20, the demultiplexer30, and the data transfer circuit40may be integrated to constitute a single drive circuit that drives the pixel circuits110.

Next, the pixel circuits110will be described below with reference toFIG. 3. All the pixel circuits110have substantially the same electrical configuration. Therefore, the pixel circuit110on the i-th row and the (3j−2)th column which is positioned on the leftmost column in the J-th group is taken as an example and will be described below. The number i is used to designate a row on which any array of pixel circuits110are arranged. The number i may be any integer ranging from 1 to m.

As illustrated inFIG. 3, the pixel circuit110includes P-channel MOS transistors121to125, the OLED130, and a capacitor132. The pixel circuit110is supplied with the scan signal Gwr(i) and control signals Gel(i), Gcmp(i), and Gorst(i). The scan signal Gwr(i) and the control signals Gel(i), Gcmp(i), and Gorst(i) are supplied from the scan line drive circuit20to the pixel circuits110on the i-th row. Thus, the scan signal Gwr(i) and the control signals Gel(i), Gcmp(i), and Gorst(i) are supplied not only to the pixel circuit110on the i-th row and the (3j−2)th column but also to the other pixel circuits110on the i-th row.

In the pixel circuit110on the i-th row and the (3j−2)th column, the gate node of the P-channel MOS transistor122is connected to the scan line12on the i-th row. In addition, one of the drain and source nodes of the P-channel MOS transistor122is connected to the data line14on the (3j−2)th column, whereas the other of the drain and source nodes of the P-channel MOS transistor122is connected to a gate node g of the P-channel MOS transistor121, a first end of the capacitor132, and the drain node of the P-channel MOS transistor123. This P-channel MOS transistor122serves as a current value setting transistor that sets a value of a current to be driven by the P-channel MOS transistor121by supplying the data signal received through the data line14to the gate node of the P-channel MOS transistor121. The gate node of the P-channel MOS transistor121is denoted by g so as to be differentiable from other nodes.

The P-channel MOS transistor121serves as a drive transistor that generates a drive current to be supplied to the OLED130. The source node of the P-channel MOS transistor121is connected to the feeder line116, whereas the drain node of the P-channel MOS transistor121is connected to both the source nodes of the P-channel MOS transistor123and the P-channel MOS transistor124. Through the feeder line116, a potential Vel is applied to the pixel circuit110; the potential Vel corresponds to the high potential of the supply voltage.

The P-channel MOS transistor123serves as an offset transistor that offsets the threshold voltage of the P-channel MOS transistor121. The drain node of the P-channel MOS transistor123is connected to the data line14. The gate node of the P-channel MOS transistor123is supplied with the control signal Gcmp(i).

The gate node of the P-channel MOS transistor124is supplied with the control signal Gel(i), whereas the drain node of the P-channel MOS transistor124is connected to both the source node of the P-channel MOS transistor125and the anode of the OLED130. The P-channel MOS transistor124is provided on a path along which the drive current is to be supplied to the OLED130. This P-channel MOS transistor124serves as a light emission control transistor that controls a light emission period of the OLED130. More specifically, the P-channel MOS transistor124is turned on to cause the OLED130to emit light and turned off to stop the OLED130from emitting the light.

The P-channel MOS transistors121to124described above constitute a transistor circuit120that supplies the drive current to the OLED130.

The gate node of the P-channel MOS transistor125is supplied with the control signal Gorst(i) for the i-th row, whereas the drain node of the P-channel MOS transistor125is connected to the feeder line16on the (3j−2)th column and kept at the potential Vorst. This P-channel MOS transistor125serves as a discharge transistor that is turned on to connect the anode of the OLED130to the feeder line16when the OLED130does not emit light. The P-channel MOS transistor125, which serves as the discharge transistor in this embodiment, functions as a “discharge section” herein, which causes the flow of the drive current output from the transistor circuit120to bypass the OLED130when the data signal indicates zero during the light emission period.

A second end of the capacitor132is connected to the feeder line116. Thus, the capacitor132maintains a voltage between the source and drain of the P-channel MOS transistor121. When the capacitance of the capacitor132is denoted by Cpix, a capacitance Cdt of each capacitor50, a capacitance Crf1of each capacitor44, and the capacitance Cpix of the capacitor132are set so as to satisfy the relationship:
Cdt>Crf1>>Cpix  (1).
In short, the capacitance Cdt is set to be larger than the capacitance Crf1, and the capacitance Cpix is set to be much smaller than the capacitances Cdt and Crf1.

The capacitor132may be implemented using a parasitic capacitance at the gate node g of the P-channel MOS transistor121. Alternatively, the capacitor132may be implemented using a capacitance between different conducting layers formed on a silicon substrate with an insulating layer therebetween.

In this embodiment, the electro-optical device1is formed on the silicon substrate. Therefore, a substrate potential of the P-channel MOS transistors121to125is the potential Vel.

The anode of the OLED130corresponds to a pixel electrode provided uniquely in each pixel circuit110. The cathode of the OLED130corresponds to a common electrode118shared by all the pixel circuits110. This cathode is kept at a potential Vct, which corresponds to the low potential of the supply voltage.

The OLED130is an element having a structure in which a white organic EL layer is formed between an anode and a light transmissive cathode on the silicon substrate. In addition, the surface of the OLED130on the cathode side from which light is to be output is covered with a red, green, or blue color filter.

When a current flows from the anode to cathode of the OLED130described above, holes injected from the anode are recoupled to electrons injected from the cathode in the organic EL layer, thereby generating exciton. As a result, the OLED130emits white light. This white light passes through the cathode positioned opposite the silicon substrate or the anode, and then is changed into red light, green light, or blue light by the color filter. After that, the resultant light is observed by a viewer.

The configuration in this embodiment, when the P-channel MOS transistor125is turned off during the light emission period, allows a large amount of off-state current Ioff_orst to flow through the P-channel MOS transistor125that serves as the discharge transistor. This configuration is effective in suppressing the black floating from occurring when the electro-optical device1displays a black image. Details of the configuration will be described below.

When the OLED130emits light, the data signal indicating zero, which is an instruction of displaying a back image, is supplied to the pixel circuit110. In response, a gate-source voltage Vgs corresponding to the threshold voltage of the P-channel MOS transistor121is applied to the P-channel MOS transistor121, as will be described later. As a result, the P-channel MOS transistor121operates in the subthreshold region. Thus, a current I120output from the transistor circuit120contains a drain current Ids of the P-channel MOS transistor121operating in the subthreshold region.

The current I120output from the transistor circuit120may also contain other currents.FIG. 4is a cross-sectional view of a configuration of the P-channel MOS transistors124and125in this embodiment. As illustrated inFIG. 4, each transistor in the pixel circuit110has a shallow trench isolation (STI) structure. A source124S and drain124D of the P-channel MOS transistor124are formed in an n well to which the highest potential VEL is to be applied. In this structure, the P-channel MOS transistor124generates leakage currents IL124aand IL124b. The leakage current IL124aflows from the n well at the potential VEL to the source124S through the pn junction therebetween; the leakage current IL124bflows from the n well at the potential VEL to the drain124D through the pn junction. Likewise, the P-channel MOS transistor121generates a leakage current IL121; the P-channel MOS transistor123generates a leakage current IL123. In short, when the data signal indicates zero, the current I120output from the transistor circuit120contains the drain current Ids of the P-channel MOS transistor121operating in the subthreshold region, as well as the leakage current IL121generated in the P-channel MOS transistor121, the leakage current IL123generated in the P-channel MOS transistor123, and the leakage currents IL124aand IL124bgenerated in the transistor124.

As illustrated inFIG. 4, the P-channel MOS transistor125also generates a leakage current IL125flowing from the n well at the potential VEL to the drain125D. In this structure, the drain125D of the P-channel MOS transistor125is connected to the drain124D of the P-channel MOS transistor124by a metal wire M54, which is connected to the anode of the OLED130(seeFIG. 3). In some instances, in addition to the current output from the transistor circuit120, the leakage current IL125of the P-channel MOS transistor125may flow to the OLED130unless any measures are taken.

In this embodiment, however, when the data signal indicates zero, the off-state current Ioff_orst generated in the P-channel MOS transistor125in the off state is set to be larger in amount than the sum (I120+IL125) of the current I120output from the transistor circuit120and the leakage current IL125of the P-channel MOS transistor125itself.

By setting the off-state current Ioff_orst in this manner, all the current I120output from the transistor circuit120can be caused to flow to the feeder line16through the P-channel MOS transistor125when the data signal indicates zero while the OLED130is emitting light. In this way, an occurrence of the black floating is suppressed.

To set the off-state current Ioff_orst to be larger in amount than the sum of the leakage currents I120and IL125, this embodiment takes the following measures.

In this embodiment, the absolute value of the threshold voltage of the P-channel MOS transistor125serving as the discharge transistor is set to be smaller than that of the P-channel MOS transistor121serving as the drive transistor. By setting both threshold voltages in this manner, the off-state current Ioff_orst can be increased.

FIG. 5is a graph showing current characteristics of the P-channel MOS transistor121serving as the drive transistor and the P-channel MOS transistor125serving as the discharge transistor. In this example, the P-channel MOS transistor125has a lower threshold voltage than that of the P-channel MOS transistor121. In the graph ofFIG. 5, the horizontal axis represents gate-source voltages Vgs of the P-channel MOS transistors121and125; the vertical axis represents the logarithmic values of the drain currents of the P-channel MOS transistors121and125. The gate-source voltage of the P-channel MOS transistor125is set to 0 V over the light emission period. When the data signal indicates zero during the light emission period, the gate-source voltage Vgs equivalent to the threshold voltage Vth is applied to the P-channel MOS transistor121. Therefore, as can be found fromFIG. 5, the horizontal axes related to the gate-source voltages Vgs of the P-channel MOS transistors121and125are shifted from each other at the point where the gate-source voltage Vgs of the P-channel MOS transistor125becomes 0 V, so that the gate-source voltage Vgs of the P-channel MOS transistor121equals the threshold voltage Vth.

The graph ofFIG. 5demonstrates that, when the threshold voltage of the P-channel MOS transistor125is lowered, the off-state current Ioff_orst generated in the P-channel MOS transistor125in the off state (Vgs=0 V) during the light emission period is larger than the current Ids (Vth) driven by the P-channel MOS transistor121in the subthreshold region.

As needed, the P-channel MOS transistor121may be an enhancement type transistor having a negative threshold voltage, and the P-channel MOS transistor125may be a depletion type transistor having a positive threshold voltage. In this case, the P-channel MOS transistor125can drive a larger amount of current when its gate-source voltage Vgs is 0 V. Thus, this configuration is more effective in suppressing an occurrence of the black floating.

In this embodiment, as illustrated inFIG. 6, a channel length L125between a source125S and the drain125D of the P-channel MOS transistor125is set to be shorter than a channel length L121between a source121S and the drain121D of the P-channel MOS transistor121. By setting the channel lengths L125and L121in this manner, the threshold voltage of the P-channel MOS transistor125can be lowered due to the short channel effect. As a result, the off-state current Ioff_orst generated in the P-channel MOS transistor125in the off state (Vgs is 0 V) can be increased. The above-described configurations are those employed by this embodiment.

Next, an operation of the electro-optical device1in this embodiment will be described below.FIG. 7is a timing chart of the operation of the electro-optical device1. As indicated by this timing chart, the scan signals Gwr(1) to Gwr(m) are sequentially switched to the L level during the frame period1F. The scan lines12on the first to m-th rows are thereby sequentially scanned. The time interval between the selections of one and the next one of the plurality of scan lines12corresponds to a horizontal scanning period1H. In this example, the frame period1F contains an m number of horizontal scanning periods1H.

Over every horizontal scanning period1H, the pixel circuits110on each row perform the same operation. For this reason, a description will be given below regarding only the case where the pixel circuit110on the i-th row and the (3j−2)th column operates over the horizontal scanning period1H in which the scan line12on the i-th row is horizontally scanned.

In this embodiment, a cycle of an initialization period, an offset period, a write period, and a light emission period is generated within the frame period1F. InFIG. 7illustrates a first cycle of (b) the initialization period, (c) the offset period, (d) the write period, and (a) the light emission period within the frame period1F.

The time interval between the start of the initialization period and the end of the write period corresponds to a current value setting period, in which each pixel circuit110on the selected scan line12sets a value of its drive current. In this example, the current value setting period contains the initialization period, the offset period, and the write period; however, the current value setting period may have any other configuration. Within the horizontal scanning period (1H), the periods other than the current value setting period corresponds to transition periods. In this embodiment, the scan line drive circuit20causes the OLEDs130to transit between the light emission state and the light non-emission state over the transition periods, in order to adjust luminance of the entire screen.

FIG. 8illustrates an operating state of the pixel circuit110on the i-th row and the (3j−2)th column over the (a) light emission period.FIG. 9illustrates an operating state over the (b) initialization period.FIG. 10illustrates an operating state over the (c) offset period.FIG. 11illustrates an operating state over the (d) write period. In each ofFIGS. 8 to 11, the current routes in the pixel circuit110which are regarded as being important for the explanation of its operation are indicated by thick lines.

Light Emission Period

As described above, the initialization period, the offset period, and the write period constitute the current value setting period. In this current value setting period, each pixel circuit110operates in such a way that the OLED130emits light of an appropriate luminance according to the data signal over the light emission period. To understand the operations of the pixel circuit110in the initialization, offset, and write periods, it is necessary to understand an operation of the pixel circuit110in the light emission period. For this reason, the operation of the pixel circuit110in the light emission period will be described first.

As illustrated inFIG. 7, the scan signal Gwr(i) is at the H level over the light emission period in which the pixels on the i-th row emit light. In addition, the control signal Gel(i) is at the L level, and the control signals Gorst(i) and Gcmp(i) are at the H level.

In the pixel circuit110on the i-th row and the (3j−2) column, as illustrated inFIG. 8, the P-channel MOS transistor124is turned on, and the P-channel MOS transistors122,123, and125are turned off. As a result, the P-channel MOS transistor121supplies the OLED130with the current Ids according to the gate-source voltage Vgs.

Over the light emission period, in this embodiment, the gate-source voltage Vgs of the P-channel MOS transistor121is shifted from its threshold voltage in accordance with the potential of the data signal, as a result of the operations in the initialization, offset, and write periods, details of which will be described later. Thus, with its threshold voltage offset, the P-channel MOS transistor121supplies the OLED130with a current according to a gradation level over the light emission period.

When the data signal indicates zero, which instructs a black display, during the light emission period, the gate-source voltage Vgs of the P-channel MOS transistor121becomes equal to its threshold voltage. As a result, the transistor circuit120outputs the current I120containing the drain current of the P-channel MOS transistor121operating in the subthreshold region and the leakage currents of the P-channel MOS transistors121and123. Simultaneously, the P-channel MOS transistor125also generates a leakage current. In this embodiment, however, the off-state current Ioff_orst that exceeds the total of the current I120output from the transistor circuit120and the leakage current of the P-channel MOS transistor125flows through the P-channel MOS transistor125. Thus, no current flows through the OLED130upon the display of the black display. Consequently, this embodiment is effective in suppressing an occurrence of the black floating.

Initialization Period

When the scan line12on the i-th row is horizontally scanned, the initialization period (b) comes first. Over this initialization period, the scan signal Gwr(i) is at the H level. In addition, the control signal Gel(i) and Gcmp(i) are the at H level, and the control signal Gorst(i) is at the L level.

In the pixel circuit110on the i-th row and the (3j−2) column, as illustrated inFIG. 9, the P-channel MOS transistor124is turned off, and the P-channel MOS transistors122,123, and125are turned on. As a result, no current flows along the route from the P-channel MOS transistor121to the OLED130, and the anode of the OLED130is reset to the potential Vorst.

As described above, the OLED130has the configuration in which the organic EL layer is formed between the anode and the cathode. Therefore, between the anode and the cathode is a parasitic capacitance Coled present, as indicated by the broken line inFIG. 9. While the current is flowing through the OLED130during the light emission period, the voltage between the anode and cathode of the OLED130is maintained by the parasitic capacitance Coled. In this embodiment, however, this voltage is reset in response to the turn-on of the P-channel MOS transistor125over the initialization period. This scheme reduces the influence of the voltage maintained by the parasitic capacitance Coled on the OLED130when the current next flows through the OLED130during the following light emission period.

For example, if the voltage between the anode and cathode of the OLED130is not reset, when the display panel10changes from a high-luminance state into a low-luminance state, a high voltage may be maintained between the anode and cathode of the OLED130. Thus, even when the P-channel MOS transistor121attempts to supply a small amount of current to the OLED130, an overcurrent may flow through the OLED130, hindering the display panel10from entering the low-luminance state. In this embodiment, however, the potential at the anode of the OLED130is reset in response to the turn-on of the P-channel MOS transistor125; therefore, a color production of the electro-optical device1can be enhanced when the display panel10is in the low-luminance state.

In this embodiment, the difference between the potential Vorst and the potential Vct at the common electrode118is set to be lower than the threshold voltage of the OLED130. Therefore, the OLED130is maintained in an off state, or in a light non-emission state, over the initialization period as well as over the following offset and write periods.

Over the initialization period, the control signal /Gini is at the L level, and the control signal Gref is at the H level. In response, the P-channel MOS transistors43and45in the data transfer circuit40are turned on, as illustrated inFIG. 9. As a result, the data line14connected to a first end of the capacitor44is reset to the potential Vini, and a node h at a second end of the capacitor44is reset to the potential Vref.

In this embodiment, the potential Vini is set such that the difference (Vel−Vini) between the potential Vel and the potential Vini exceeds the absolute value |Vth| of the threshold voltage Vth of the P-channel MOS transistor121. In this case, the threshold voltage Vth of the P-channel MOS transistor121has a negative value relative to the potential at the source node. Thus, for the purpose of helping an understanding of the magnitude relationship, the threshold voltage is represented by an absolute value |Vth|.

In this embodiment, the potential Vref is set such that the potential at the node h increases during the following the write period, relative to the potentials that the data signals Vd(1) to Vd(n) may have. As an example, the potential Vref may be set to be lower than the minimum voltage Vmin.

Offset Period

While the scan line12on the i-th row is being horizontally scanned, the offset period (c) comes after the initialization period (b). Over this offset period, the scan signal Gwr(i) and the control signal Gcmp(i) are switched to the L level. The control signal Gref is kept at the H level. The control signal /Gini is switched to the H level.

As a result, as illustrated inFIG. 10, in the data transfer circuit40, the N-channel MOS transistor43is turned on, and the P-channel MOS transistor45is turned off. The node h is thereby fixed at the potential Vref. In the pixel circuit110on the i-th row and the (3j−2) column, the P-channel MOS transistor122is turned on. In response, the gate node g gets electrically connected to the data line14. The gate node g is set to the potential Vini at the initial stage of the offset period.

During the offset period, the P-channel MOS transistor123is turned on. The gate node g of the P-channel MOS transistor121thereby gets connected to the drain node of the P-channel MOS transistor121through the P-channel MOS transistors122and123, making a diode connection. As a result, the drain current flows through the P-channel MOS transistor121, charging the gate node g and the data line14. More specifically, the current flows along the route on which the feeder line16, the P-channel MOS transistors121and123, the data line14on the (3j−2) column, the P-channel MOS transistor122, and the gate node g are disposed in this order. In this case, the potential on the data line14and at the gate node g that have gotten interconnected in response to the turn-on of the P-channel MOS transistor121increases from the potential Vini.

However, the current is less likely to flow along the above route as the potential at the gate node g becomes closer to the potential (Vel−|Vth|). Before the offset period ends, the potential on the data line14and at the gate node g is saturated to the potential (Vel−|Vth|). In this case, the capacitor132maintains the threshold voltage |Vth| of the P-channel MOS transistor121at the final stage of the offset period.

Write Period

After the initialization period has ended, the write period (d) comes. Over this write period, the control signal Gcmp(i) is at the H level, and the diode connection made by the P-channel MOS transistor121is thereby broken off. In addition, the control signal Gref is at the L level, and the N-channel MOS transistor43is thereby turned off. As a result, the route from the data line14on the (3j−2) column to the gate node g of the pixel circuit110on the i-th row and the (3j−2) column electrically floats. However, this route is kept at the potential (Vel−|Vth|) by the capacitors50and132.

Over the write period, the control circuit3sequentially changes the potentials of the data signals Vd(j) into potentials according to gradation levels of the pixels on the i-th row and the (3j−2) column, the i-th row and the (3j−1) column, and the i-th row and the 3j-ith column. In response to the change in the potentials of the data signals, the control circuit3sequentially switches the control signals Sel(1), Sel(2), and Sel(3) to the H level in an exclusive manner. In this case, the control circuit3also outputs the control signals /Sel(1), /Sel(2), and /Sel(3), which are equivalent to the logical inversions of the control signals Sel(1), Sel(2), and Sel(3), respectively that are not illustrated inFIG. 7. As a result, in the demultiplexers30, the transmission gates34on the leftmost, central, and the rightmost columns in each group are turned on in this order.

When the transmission gate34on the leftmost column in a certain group is turned on in response to the control signals Sel(1) and /Sel(1), the potential Vref at the node h connected to the second end of the capacitor44which has been fixed over the initialization and offset periods is changed into the potential of the data signal Vd(j), namely, a potential according to the gradation level of the pixel on the i-th row and the (3j−2) column, as illustrated inFIG. 11. In this case, the variation in the potential at the node h is denoted by ΔV, and the changed potential is denoted by (Vref+ΔV).

The gate node g connected to the first end of the capacitor44through the data line14increases to a potential (Vel−|Vth|+k1·ΔV), which is the sum of the potential (Vel−|Vth|) that has been set during the offset period and the product of a capacitance ratio k1and the variation in the potential at the node h. In this case, if the voltage Vgs of the P-channel MOS transistor121is expressed by an absolute value, the voltage Vgs can be (|Vth|−k1·ΔV), which is the difference between the threshold voltage |Vth| and the increased amount of the potential at the gate node g.

The capacitance ratio k1can be expressed by Crf1/(Cdt+Crf1). Strictly speaking, it is necessary to consider the capacitance Cpix of the capacitor132. However, this capacitance Cpix may be ignored, because the capacitance Cpix is set to be sufficiently smaller than each of the capacitances Crf1and Cdt.

After the write period for the i-th row has ended and the scan line12on the i-th row has been horizontally scanned, the light emission period comes. Over the light emission period, as described above, the control signal Gel(i) is set to the L level. In the pixel circuit110, the P-channel MOS transistor124on the i-th row and the (3j−2) column is thereby turned on. In this case, the gate-source voltage Vgs of the P-channel MOS transistor121is expressed by (|Vth|−k1·ΔV). Therefore, as explained with reference toFIG. 5, the current according to the gradation level is supplied to the OLED130with the threshold voltage of the P-channel MOS transistor121offset.

The above operation is being performed concurrently by not only the pixel circuit110on the i-th row and the (3j−2) column but also the pixel circuits110on the i-th row and other columns while the scan line12is being horizontally scanned. In fact, this operation is sequentially performed on the scan lines12on the i-th row (i=1, 2, 3 . . . (m−1), and m) over one frame period. Furthermore, the operation is repeated in units of frame periods.

According to this embodiment, a potential range ΔVgate of a gate node g is narrower than a potential range ΔVdata of a data signal; the potential range ΔVgate is a range in which the potential at the gate node g varies, and the potential range ΔVdata is a range in which the potential of the data signal varies. This configuration makes it possible to apply a voltage considering a gradation level between the gate and source of a P-channel MOS transistor121without the need to finely adjust the data signal. Consequently, it is possible to control currents supplied to OLEDs130with great precision even when the OLEDs130are mounted in tiny pixel circuits110each in which the supplied current is sensitive to a variation in a gate-source voltage Vgs of the P-channel MOS transistor121.

As indicated by the broken line inFIG. 3, in fact, a parasitic capacitance Cprs is present between a data line14and a gate node g of the P-channel MOS transistor121in each pixel circuit110. When the potential on the data line14largely fluctuates, this fluctuation may be transferred to the gate node g through the capacitance Cprs, thereby causing a lowered display quality such as crosstalk or uneven luminance. This parasitic capacitance Cprs influences a pixel circuit110more significantly as the pixel circuit110is smaller in size.

This embodiment, however, can reduce the influence of the parasitic capacitance Cprs by setting the potential variation range of the data line14to be narrower than the potential range ΔVdata of the data signal.

The write period ends in response to the timing at which the scan signal Gwr(i) is switched to the H level. The time interval between the end of the write period for the scan line12on the i-th row and the start of the initialization period for the scan line12on the (i+1)th row corresponds to a transition period. In this embodiment, the scan line drive circuit20switches the control signals Gorst(i) and Gel(i) for the pixel circuits110on any scan line12to the H and L levels, respectively, within the transition period. In response, the pixel circuits110connected to this scan line starts the light emission period. Likewise, the scan line drive circuit20switches the control signals Gorst(i) and Gel(i) for the pixel circuits110on any scan line12to the L and H levels, respectively, within the transition period. In response, the pixel circuits110connected to this scan line ends the light emission period.

FIG. 7illustrates the example in which the pixel circuits110on the i-th row start the light emission period within the transition period following the write period. In this example, the scan line drive circuit20switches the control signals Gorst(i) and Gel(i) for the pixel circuits110along the scan line12on the i-th row to the H and L levels, respectively. Furthermore,FIG. 7also illustrates the examples in which the pixel circuits110along the scan line12on an ia-th row, which differs from the i-th row, start the light emission period and in which the pixel circuits110along the scan line12on an ib-th row, which differs from the i-th and ia-th rows, ends the light emission period. Each pixel circuit110operates over the light emission period in the above-described manner.

According to this embodiment, when a pixel circuit110creates a black image during a light emission period, a transistor circuit120outputs a current that equals the sum of a drain current Ids driven by a P-channel MOS transistor121in accordance with the gate-source voltage equivalent to the threshold voltage, a leakage current IL121of the P-channel MOS transistor121, a leakage current IL123of a P-channel MOS transistor123, and leakage currents IL124aand IL124bof the P-channel MOS transistor124. In addition, a P-channel MOS transistor125outputs a leakage current IL125from its n well through a connection node between the P-channel MOS transistor125and an OLED130. However, during the light emission period for the pixel circuit110, these output currents bypass the OLED130and flows to a feeder line16as an off-state current Ioff_orst of the P-channel MOS transistor125. Consequently, this embodiment is effective in suppressing the black floating from occurring when each pixel circuit110creates a black image.

Second Embodiment

FIG. 12is a circuit diagram illustrating a configuration of a pixel circuit110′ in an electro-optical device according to a second embodiment of the invention. In this embodiment, instead of the P-channel MOS transistor125in the foregoing first embodiment, an N-channel MOS transistor125′ is used. The gate of this N-channel MOS transistor125′ is supplied with a signal equivalent to the logical inversion of the signal supplied to the gate of the P-channel MOS transistor125. Other configurations of the pixel circuit110′ are substantially the same as those of each pixel circuit110.

FIG. 13is a cross-sectional view of a configuration of a P-channel MOS transistor124and the N-channel MOS transistor125′ in the pixel circuit110′. As illustrated inFIG. 13, a drain125D′, formed of an N-type diffusion layer, of the N-channel MOS transistor125′ which is connected to the anode of an OLED130is formed in a p well to which a lowest potential VCT is to be applied. In this configuration, no leakage current flows from the drain125D′ of the N-channel MOS transistor125′ to the outside. Conversely, a leakage current IL125′ flows from the drain125D′ to the p well. In this embodiment, when the OLED130does not emit light, an off-state current Ioff_orst flows through the N-channel MOS transistor125′. The off-state current Ioff_orst equals the sum of a channel current flowing from the drain to source of the N-channel MOS transistor125′ in the off state and the leakage current IL125′ flowing from the drain125D′ to the p well. This off-state current Ioff_orst is set to be larger than a current I120that is output from a transistor circuit120upon the display of a black image.

Similar to the foregoing first embodiment, this embodiment is effective in suppressing the black floating from occurring when each pixel circuit110creates a black image. In this embodiment, the leakage current flowing from the drain125D′ to the p well is added to the off-state current Ioff_orst. Therefore, the leakage current flowing from the source to drain of the N-channel MOS transistor125′ in the off state is decreased by an amount corresponding to the leakage current flowing from the drain125D′ to the p well. Consequently, for example, it is possible to easily control the threshold of the N-channel MOS transistor125′.

To enhance the effect of this embodiment, as an example ofFIG. 14, the drain125D′ of the discharge transistor125′ which is connected to the OLED130preferably has a smaller area than that of a source125S′ of the discharge transistor125′. By widening the area of the drain125D′, the leakage current IL125′ can be increased.

As an example ofFIG. 15, the area of the drain125D′ of the N-channel MOS transistor125′ is preferably larger than the total area of a drain124D and source124S of the P-channel MOS transistor124. The P-channel MOS transistor124switches and controls the flow of the drive current that the P-channel MOS transistor121supplies to the OLED130. Therefore, the P-channel MOS transistor124is usually designed to have a large channel width so as not to affect the current flow. However, a larger channel width may result in a larger total area of the drain124D and the source124S, thereby generating larger amounts of leakage currents IL124aand IL124b. To decrease these leakage currents, the area of the drain125D′ of the N-channel MOS transistor125′ is preferably designed to be larger than the total area of the drain124D and source124S of the P-channel MOS transistor124. By designing the area of the drain125D′ in this manner, the leakage current IL125′ that exceeds the sum of the leakage currents IL124aand IL124bgenerated in the P-channel MOS transistor124is caused to flow from the drain125D′ to the p well in the P-channel MOS transistor125. This configuration can help suppress an occurrence of the black floating.

Modification

The invention is not limited to the foregoing first and second embodiments, and thus various modifications are possible. Some examples of such modifications will be described below. It should be noted that some of these examples may be combined as appropriate.

First Modification

Although both of the pixel circuit110in the foregoing first embodiment and the pixel circuit110′ in the foregoing second embodiment include an OLED as an electro-optic element, the electro-optic element may be any light emitting element that emits light of luminance proportional to a driven current. As an alternative example, the light emitting element may be an inorganic light emitting diode or other light emitting diode (LED).

Second Modification

in the foregoing first and second embodiments and the first modification, the data transfer circuit40transfers electric charge to the pixel circuits110, thereby writing data into the pixel circuits110. However, there is no limitation on a method of writing data into the pixel circuits110. Although each pixel circuit110is provided with the five transistors in the foregoing first and second embodiments and the first modification, each pixel circuit110does not necessarily have to be provided with the P-channel MOS transistor123. In short, each pixel circuit110only has to be provided with the P-channel MOS transistors121,122, and124that serve as drive, write, and light emission control transistors, respectively.

Application Example

Next, a description will be given below of an electronic apparatus according to an application example which employs the electro-optical device1according to any one of the first and second embodiments and the first and second modifications. The electro-optical device1is intended to display a high-resolution image with small-sized pixels. A head mount display (HMD) is employed as an example of the electronic apparatus and will be described below.

FIG. 16is a schematic view of an HMD200that employs the electro-optical device according to one of the first and second embodiments and the first and second modifications. As illustrated inFIG. 16, the HMD200includes a front frame210, a pair of side frames220, an optical panel250, circuit covers230, and an electro-optical device270. The front frame210is to be positioned in front of a user's head. The pair of side frames220is connected to both ends of the front frame210and to be positioned on both sides of the user's head. The optical panel250is fixed to the front frame210and aims to cover the user's eyes. The circuit covers230are fixed to the respective side frames220. The electro-optical device270adjusts the luminance of the screen by using the function described in the first and second embodiments and the first and second modifications.

The electro-optical device270in this application example includes a pair of display panels DI1and DI2. Furthermore, the electro-optical device270includes a pair of adjusters51and52to adjust a light emission period in the manner described in the first embodiment.

The pair of display panels DI1and DI12is mounted on the optical panel250so as to be positioned in front of the user's left eye and right eye, respectively. The pair of display panels DI1and DI12emits light through the optical panel250. The user is expected to view the light from the display panel DI1with the left eye and the light from the display panel DI2with the right eye.

In the HMD200, the adjuster51is operably disposed on one of the pair of side frames220, whereas the adjuster52is operably disposed on the other of the pair of side frames220. In addition, a control circuit3is mounted in one of the circuit covers230which is fixed to a corresponding one of the pair of side frames220, whereas a power supply circuit DC is mounted in the other of the circuit covers230. It should be noted that these arrangements may be modified as appropriate.

FIG. 17is a schematic view of a projector that employs the electro-optical device according to one of the first and second embodiments and the first and second modifications. As illustrated inFIG. 17, the projector300includes a housing350, an electro-optical device370, a dichroic prism310, and a projection lens320.

The electro-optical device370includes three display panels DI1, DI2, and DI3. Furthermore, the electro-optical device370includes adjusters51and52, a power supply circuit DC, and a controller CP.

The display panels DI1, DI2, and DI3are disposed inside the housing350. Each of the display panels DI1, DI2, and DI3has arrays of color pixels. In this example application, the display panel DI1displays a red image; the display panel DI2displays a green image; and the display panel DI3displays a blue image. Each of the display panels DI1, DI2, and DI3has a display section. These display sections are disposed adjacent to one another with their emission light beams forming approximately 90 degrees with one another. In this example application, the display panel DI1is disposed adjacent to the display panel DI2; the display panel DI2is disposed adjacent to the display panel DI3; and the display panel DI1is disposed opposite the display panel DI3.

The dichroic prism310is disposed surrounded by the display panels DI1, DI12, and DI3. The dichroic prism310has side surfaces that the light beams are to enter. These side surfaces are disposed opposite the display panels DI1, DI2, and DI3. In addition, the dichroic prism310has a side surface from which a light beam is to be output. This side surface is disposed opposite the projection lens320. The light beam is output from the inside to outside of the housing350through the projection lens320. The projection lens320may be composed of either a single lens or a plurality of lenses.

The adjusters51and52are operably disposed on the exterior of the housing350to adjust the light emission period in the manner described in the first embodiment. Upon operation, the projector300mixes the red light beam from the display panel DI1, the green light beam from the display panel DI2, and the blue light beam from the display panel DI3to make a mixed color light beam. Then, the projector300projects this mixed color light beam onto a screen330. It should be noted that the screen330may be either of a light transmissive or light reflective type.

In this example application, the display panels DI1, DI2, and DI13emit specific color light beams, namely, red, green, and blue light beams, respectively. Alternatively, the display panels DI1, DI12, and DI13may emit any other color light beams.

In this example application, the display panel DI1displays a red image; the display panel DI12displays a green image; and the display panel DI3displays a blue image. However, the display panels DI1, DI12, and DI13do not necessarily have to display images. Alternatively, the display panel DI1may be a red light source; the display panel DI12may be a green light source; and the display panel DI3may be a blue light source. In this case, liquid crystal panels or other optical panels are disposed in front of the display panels DI1, DI2, and DI3. The display panels DI1, DI2, and DI13emit light beams to such optical panels, which then display images on the basis of the light beams.

The electro-optical device1described above is applicable to not only the HMD200but also an electronic viewfinder for video cameras or digital cameras with interchangeable lenses, as well as an information display section for portable information processing devices such as tablets, wristwatches, and projectors.

The entire disclosure of Japanese Patent Application No. 2017-047109, filed Mar. 13, 2017 is expressly incorporated by reference herein.