Semiconductor device with polymer-based insulating material and method of producing thereof

A semiconductor device includes a semiconductor substrate having a first main surface and a metal structure above the first main surface. The metal structure has a periphery region that includes a transition section along which the metal structure transitions from a first thickness to a second thickness less than the first thickness. A polymer-based insulating material contacts and covers at least the periphery region of the metal structure. A thickness of the polymer-based insulating material begins to increase on a first main surface of the metal structure that faces away from the semiconductor substrate and continues to increase in a direction towards the transition section. An average slope of a surface of the polymer-based insulating material which faces away from the semiconductor substrate, as measured with respect to the first main surface of the metal structure, is less than 60 degrees along the periphery region of the metal structure.

BACKGROUND

Power MOSFETs (metal-oxide semiconductor field-effect transistors) are widely used in many types of applications, some of which require fast switching speeds. To accommodate fast switching speeds, power MOSFETs may have gate finger structures that more uniformly distribute the gate signal to individual transistor cells. However, the gate finger structures run over the active cell field and have considerable topology levels. The topology levels of the gate finger structures create additional stress in all layers involved, which can be discharged into cracks that present a reliability risk.

Thus, there is a need for an improved power MOSFET design with reduced topology levels around gate finger and other type of metal structures.

SUMMARY

According to an embodiment of a semiconductor device, the semiconductor device comprises: a semiconductor substrate having a first main surface; a metal structure above the first main surface of the semiconductor substrate, the metal structure having a periphery region that includes a transition section along which the metal structure transitions from a first thickness to a second thickness less than the first thickness; and a polymer-based insulating material in contact with and covering at least the periphery region of the metal structure, wherein a thickness of the polymer-based insulating material begins to increase on a first main surface of the metal structure that faces away from the semiconductor substrate and continues to increase in a direction towards the transition section of the metal structure, wherein an average slope of a surface of the polymer-based insulating material which faces away from the semiconductor substrate, as measured with respect to the first main surface of the metal structure, is less than 60 degrees along the periphery region of the metal structure.

According to another embodiment of a semiconductor device, the semiconductor device comprises: a semiconductor substrate having a first main surface; a first electrically conductive structure above the first main surface of the semiconductor substrate, the first electrically conductive structure having a region; a polymer-based insulating material in contact with and covering at least the region of the first electrically conductive structure, wherein a thickness of the polymer-based insulating material begins to increase on a first main surface of the first electrically conductive structure that faces away from the semiconductor substrate, wherein an average slope of a surface of the polymer-based insulating material which faces away from the semiconductor substrate, as measured with respect to the first main surface of the first electrically conductive structure, is less than 60 degrees along the region of the first electrically conductive structure; and a second electrically conductive structure above the polymer-based insulating material.

According to an embodiment of a method of producing a semiconductor device, the method comprises: forming a metal structure above a first main surface of a semiconductor substrate, the metal structure having a periphery region that includes a transition section along which the metal structure transitions from a first thickness to a second thickness less than the first thickness; forming a polymer-based insulating material on at least the periphery region of the metal structure; varying a degree of polymer cross-linking within the polymer-based insulating material along the periphery region of the metal structure, such that the degree of the polymer cross-linking increases with increasing thickness of the polymer-based insulating material; and after varying the degree of the polymer cross-linking, curing the polymer-based insulating material.

According to another embodiment of a semiconductor device, the semiconductor device comprises: a semiconductor substrate having a first main surface; a metal structure above the first main surface of the semiconductor substrate, the metal structure having a periphery region that includes a transition section along which the metal structure transitions from a first thickness to a second thickness less than the first thickness; and a polymer-based insulating material in contact with and covering at least the periphery region of the metal structure, wherein a thickness of the polymer-based insulating material begins to increase on a first main surface of the metal structure that faces away from the semiconductor substrate and continues to increase in a direction towards the transition section of the metal structure, wherein the polymer-based insulating material has undulations over the transition section of the metal structure.

DETAILED DESCRIPTION

Described herein are embodiments of semiconductor devices with reduced topology levels around metal structures. According to embodiments described herein, an electrically conductive structure formed above a semiconductor substrate has a periphery region that includes a transition section along which the electrically conductive structure transitions from a first thickness to a second thickness less than the first thickness. A polymer-based insulating material which contacts and covers at least the periphery region of the electrically conductive structure has a thickness that begins to increase on a surface of the electrically conductive structure that faces away from the semiconductor substrate and continues to increase in a direction towards the transition section of the electrically conductive structure. The average slope of the surface of the polymer-based insulating material which faces away from the semiconductor substrate is less than 60 degrees along the periphery region of the electrically conductive structure. Such a sloped surface for the polymer-based insulating material reduces the topology levels in this region of the device. Reducing or flattening the thickness transition of the polymer-based insulating material above the periphery region of the electrically conductive structure eases the topology levels of any overlying layer such as a power metallization layer or layer stack, reducing the likelihood of cracks forming in this region of the device.

Described next, with reference to the figures, are exemplary embodiments of techniques for reduced topology levels around metal structures of a semiconductor device.

FIG.1Aillustrates a top plan view of an embodiment of a semiconductor device100.FIG.1Billustrates a cross-sectional view of the semiconductor device100along the line labelled A-A′ inFIG.1A.

The semiconductor device100includes a semiconductor substrate102having a first main surface104and a second main surface106opposite the first main surface104. The semiconductor substrate102may include one or more of a variety of semiconductor materials that are used to form semiconductor devices such as power MOSFETs, IGBTs, SiC transistors, etc. For example, the semiconductor substrate102may include silicon (Si), silicon carbide (SiC), germanium (Ge), silicon germanium (SiGe), gallium nitride (GaN), gallium arsenide (GaAs), and the like. The semiconductor substrate102may be a bulk semiconductor material or may include one or more epitaxial layers grown on a bulk semiconductor material. The semiconductor substrate102may include device cells such as transistor and/or diode cells in an active cell field. The active cell field is not shown inFIGS.1A and1Bto emphasize other features of the semiconductor device100, but may include planar and/or trench device cells as is well understood in the art.

The semiconductor substrate102may be attached to a support substrate108at the second main surface106of the semiconductor substrate102. The support substrate108may be a lead frame, a circuit board such as a PCB (printed circuit board), a DBC (direct bonded copper) substrate, an AMB (active metal brazed) substrate, an IMS (insulated metal substrate), etc. The semiconductor substrate102may be encapsulated in a molding compound110.

The semiconductor device100further includes a first electrically conductive structure112formed above the first main surface104of the semiconductor substrate102and separated from the semiconductor substrate102by at least one insulating layer114. The first electrically conductive structure112may be a metal structure of a metallization layer or layer stack and may comprise a metal or metal alloy such as Cu, Al, AlCu, etc. The first electrically conductive structure112has a periphery region116that includes a transition section118along which the first electrically conductive structure112transitions from a first thickness ‘T1’ to a second thickness ‘T2’ less than the first thickness T1. As shown in the enlarged view ofFIG.1B, the first electrically conductive structure112may transition to a second thickness T2of zero in the transition section118.

In one embodiment, the semiconductor device100is a power transistor and the first electrically conductive structure112includes first metal structures120which are at a source potential and laterally separated from a second metal structure which is at a second potential that is different from the source potential. For example, the second metal structure may be a gate metallization structure that is at a gate potential. The gate metallization structure may include a gate pad122, a gate runner124extending from the gate pad122and running along one or more outer sides of the first electrically conductive structure112, and gate fingers126running between the first metal structures120which are at source potential. In another example, the second metal structure may be a sensor line128extending from a sensor pad130. In this example, the second metal structure is at a potential of a sense signal. The gate pad122/sensor pad130of the semiconductor device100may be electrically connected to a lead132by an electrical conductor134such as a wire bond, wire ribbon, etc.

In each case, the semiconductor device100further includes a polymer-based insulating material136in contact with and covering at least the periphery region116of the first electrically conductive structure112. InFIG.1B, the polymer-based insulating material136also is in contact with and covers the gate fingers126/sensor line128of the first electrically conductive structure112. In one embodiment, the polymer-based insulating material132is formed by forming one or more polyimide layers on the periphery region116of the first electrically conductive structure112. The molding compound110and the polymer-based insulating material138are not shown inFIG.1Ato provide an unobstructed view of the underlying structures.

The polymer-based insulating material136separates an overlying metallization layer or layer stack138from the underlying gate fingers126/sensor line128to ensure that the first metal structures120of the first electrically conductive structure112are electrically isolated from the gate fingers126/sensor line128. The overlying metallization layer or layer stack138contacts the first electrically conductive structure112outside the periphery region116of the first electrically conductive structure112where the polymer-based insulating material136is not present. A metal clip140such as a Cu clip may be attached to the overlying metallization layer or layer stack138via solder or other suitable joining material142to electrically connect the first metal structures120of the first electrically conductive structure112to a corresponding lead or leads144.

In one embodiment, the first electrically conductive structure112comprises AlCu, the overlying metallization layer or layer stack138comprises a Cu layer and a Cu diffusion barrier such as WTi on which the Cu layer is formed, and the polymer-based insulating material136separates the overlying metallization layer or layer stack138from the underlying AlCu gate fingers126/sensor line128. In another embodiment, the first electrically conductive structure112and the overlying metallization layer or layer stack138both comprise the same material such as Cu, Al, AlCu, etc.

In each case, the thickness ‘T_poly’ of the polymer-based insulating material136begins to increase on the main surface146of the first electrically conductive structure112that faces away from the semiconductor substrate102and continues to increase in a direction (x direction inFIG.1B) towards the transition section118of the first electrically conductive structure112. InFIG.1B, this means that the thickness T_poly of the polymer-based insulating material136begins to increase along the periphery region116of the first electrically conductive structure112in a lateral direction heading toward the gate fingers126/sensor line128.

The average slope ‘α1’ of the surface148of the polymer-based insulating material136which faces away from the semiconductor substrate102, as measured with respect to the first main surface146of the first electrically conductive structure112, is less than 60 degrees, less than 45 degrees, less than 35 degrees, or even less than 20 degrees along the periphery region116of the first electrically conductive structure112. Such reduced topology levels above the periphery region116of the first electrically conductive structure112flatten the profile of the overlying layer(s) including the overlying metallization layer or layer stack138and reduce or altogether avoid stress and crack risk in this region of the semiconductor device100.

Conventional photolithographic processing techniques would have yielded a much steeper profile for the polymer-based insulating material136along the periphery region116of the first electrically conductive structure112. As indicated by the dashed curve in the enlarged view ofFIG.1B, if formed by conventional photolithographic processing techniques, the average slope ‘α2’ of the surface148of the polymer-based insulating material136which faces away from the semiconductor substrate102, as measured with respect to the first main surface146of the first electrically conductive structure112, would have been greater than 60 degrees, e.g., 70 degrees or larger along the periphery region116of the first electrically conductive structure112. This means that the overlying metallization layer or layer stack138would have the same steep profile in this region of the semiconductor device100, which can lead to cracks and related reliability issues. For example, the first electrically conductive structure112may include a thin WTi diffusion barrier which is prone to microcracks if the average slope α2 of the thin WTi diffusion barrier is greater than 60.

Described next are embodiments of flattening the profile of the polymer-based insulating material136along the periphery region116of the first electrically conductive structure112, so that the average slope α1 of the polymer-based insulating material136is less than 60 degrees, less than 45 degrees, less than 35 degrees, or even less than 20 degrees along the periphery region116of the first electrically conductive structure112.

FIG.2illustrates a top plan view of an embodiment of a photolithographic mask200used in forming the polymer-based insulating material136in a region where the topology/step profile of the polymer-based insulating material136is to be reduced or flattened. According to this embodiment, the photolithographic mask200has a grayscale zone202with stripes204for lithographically processing a polymer starting material206. The stripes204may have equal or different dimensions with equal or different spacing between the stripes204.

Lithographic processing of the polymer starting material206using the photolithographic mask200with the grayscale zone202yields the polymer-based insulating material136. The grayscale zone202varies the degree of polymer cross-linking within the polymer-based insulating material136along the periphery region116of the first electrically conductive structure112, such that the degree of the polymer cross-linking increases with increasing thickness of the polymer-based insulating material136.

In general, any type of polymer starting material206that yields a polymer-based dielectric or passivation layer may be used. For example, the polymer starting material206may be polyimide, epoxy, PBO (polybenzoxazole), imide, etc. For positive tone materials such as PBO, the polymer starting material206remains where not exposed to light to form the polymer-based insulating material136. For negative tone materials such as imide, the polymer starting material206remains where exposed to light to form the polymer-based insulating material136. The pattern of the grayscale zone202may be inverted depending on whether a negative or positive tone polymer starting material206is used.

After grayscale lithographic processing with the photolithographic mask200, the resulting polymer-based insulating material136may have undulations with a wavelike form which correspond to the grayscale zone202of the photolithographic mask200. The undulations have a similar shape, periodicity, spacing, etc. as that of the stripes204included in the grayscale zone202of the photolithographic mask200.

The grayscale lithography processing may be applied to a region with increasing thickness of the polymer-based insulating material136. For example, the undulations may be formed in the polymer-based insulating material136along the periphery region116of the first electrically conductive structure112. The undulations yield a less steep increase (α1<α2) in the average slope α1 of the polymer-based insulating material136in a region aligned with of the grayscale zone202of the photolithographic mask200. The undulations are not produced outside the grayscale zone202.

FIG.3illustrates additional embodiments of the grayscale zone202of the photolithographic mask200used in forming the polymer-based insulating material136in a region where the topology/step profile of the polymer-based insulating material136is to be reduced or flattened. Instead of stripes204as shown inFIG.2, the grayscale zone202may instead have other geometric shapes300such as pixel-like structures which may vary in size, shape and/or spacing with increasing thickness of the polymer-based insulating material136to yield the desired undulation profile. The resulting undulations formed in the polymer-based insulating material136using the photolithographic mask200have a similar shape, periodicity, spacing, etc. as that of the geometric shapes300included in the grayscale zone202of the photolithographic mask200.

FIG.4shows part of a grayscale zone202of the photolithographic mask200. According to this embodiment, the dimensions (x, y parameters inFIG.4) of the geometric shapes204/300and the spacing (sx, sy parameters inFIG.4) between rows and columns of the geometric shapes204/300may vary with increasing thickness of the polymer-based insulating material136to yield the desired undulation profile. For example, the area of the geometric shapes204/300may be in a range of 1 to 5 um. The spacing may vary from 50% to 95% of the size of the largest geometric shape204/300. In another example, the area of the geometric shapes204/300may be ½ thickness or less (to almost zero) of the polymer starting material206. The size and spacing of the geometric shapes204/300may depend on the type of illuminated light to which the polymer starting material206is exposed as part of the grayscale lithographic processing. The geometric shapes204/300may be stripes, rectangles, pixels, trapezoids, triangles, etc. The geometric shapes204/300may have a meandering layout if the underlying topology meanders, e.g., corners, rounded/radius, etc.

In one embodiment, the photolithographic mask200shown inFIGS.2,4and5is formed by sputtering a chromium layer on a glass substrate and etching the shapes204/300into the chromium layer. In another embodiment, the photolithographic mask200shown inFIGS.2through4is formed by sputtering a plurality of chromium layers of different thicknesses on a glass substrate.

FIGS.5A through5Eillustrate partial cross-sectional views during different stages of an embodiment of a method of producing the semiconductor device100, by applying grayscale lithography to a region of the polymer-based insulating material136with increasing thickness using the photolithographic mask200having the grayscale zone202.FIGS.6A through6Eshow the same partial cross-sectional views asFIGS.5A through5E, respectively, but without the use of grayscale lithographic processing.

FIG.5Ashows the polymer starting material206applied to an underlying layer500. The underlying layer500may correspond to the first electrically conductive structure112described herein, but is illustrated simplistically to emphasize the grayscale lithographic processing of the polymer starting material206using the photolithographic mask200. The photolithographic mask200includes a grayscale zone202with stripes204or other geometric shapes300, as previously described herein. The photolithographic mask200is illustrated for a negative tone polymer starting material206but the pattern of the grayscale zone202may be reversed for a positive tone polymer starting material206. The photolithographic mask200is illuminated with light502. A first region504of the photolithographic mask200outside the grayscale zone202allows the light502to pass unimpeded to the polymer starting material206. A second region506of the photolithographic mask200outside the grayscale zone202prevents the light502from reaching the polymer starting material206.

The shapes204/300in the grayscale zone202of the photolithographic mask200block some but not all of the light502from reaching the polymer starting material206. In one embodiment, the size of the geometric shapes204/300is in a range of a sub-resolution of the polymer starting material206. For example, in the case of polyimide as the polymer-based insulating material136, polyimide has a resolution greater than 5 μm and the size of the geometric shapes204/300in the grayscale zone202of the photolithographic mask200may be less than 5 μm. By applying grayscale lithography to the polymer starting material206using the photolithographic mask200with the grayscale zone202, the polymer starting material206has a first region508which is fully exposed, a second region510which is partly exposed, and a third region512which has no exposure to the light502.

In the first region508of the polymer starting material206, the polymer starting material206fully reacts with the light502and cross-links the polymer structure in between and to make the polymer structure stable to later dissolution by a developer. Less exposure and less cross-linking between polymers occurs in the second region510of the polymer starting material206. No cross-linking occurs in the third region512of the polymer starting material206, which allows for subsequent fully developed wash away of the polymer. InFIGS.5A through6E, the polymers are indicated by squiggly lines and the cross-links by vertical lines which extend between polymers or between the polymer starting material206and the underlying layer500.

In contrast,FIG.6Ashows that the non-grayscale lithographic processing uses a photolithographic mask514that only has a first region516that allows the light502to pass unimpeded to the polymer starting material206and a second region518that prevents the light502from reaching the polymer starting material206. The photolithographic mask514inFIG.6Adoes not have a grayscale zone. Accordingly, the polymer starting material206inFIG.6Aonly has a first region520which is fully exposed and a second region522which has no exposure to the light502. The polymer starting material206inFIG.6Adoes not have a region with partial exposure to the light502.

FIG.5Bshows a first spray step during which a first developer solution524that acts as a solvent is applied to the polymer starting material206and washes away each part of the polymer starting material206which is not cross-linked. Accordingly, the third region512of the polymer starting material206has very fast development. Less development occurs in the second region510of the polymer starting material206, and little or no development occurs in the first region508of the polymer starting material206.

In contrast,FIG.6Bshows that the process which does not employ grayscale lithographic processing yields one region522of the polymer starting material206with very fast development and another region520with little or no development, with no intermediary region of development therebetween.

FIG.5Cshows a second spray step during which a second developer solution526is applied to the polymer starting material206to complete the washing away of all non-crosslinked polymer material.

FIG.5Dshows the structure after the second spray step with a first region528where the polymer starting material206is completely removed, a second region530where the polymer starting material206is partly removed and therefore has a reduced thickness in this region530, and a third region532where the fully crosslinked polymer starting material206remains intact with a greater thickness than in the second region530.

In contrast,FIGS.6C and6Dshow that the process which does not employ grayscale lithographic processing yields a first region534where the polymer starting material206is completely removed and a second region536where the fully crosslinked polymer starting material206remains intact, with no intermediary thickness region therebetween.

FIG.5Eshows a curing step during which further cross linking of the remaining polymer structure occur, driving out remaining solvent from the polymer structure and forming the polymer-based insulating material136. The structure may be cured in an oven, by UV light, etc. depending on the type of polymer starting material206used. Shrinkage of the polymer structure occurs during the curing as indicated by the arrows inFIG.5B, resulting in a certain slope profile. The structure may be subjected to a plasma process after curing to remove some of the surface topology/roughness. For example, the grey scale region of the polymer-based insulating material136with increasing thickness may be smooth or have surface topology/roughness, depending on subsequent processing. A different process may be applied to intentionally roughen the surface of the polymer-based insulating material136, e.g., to enhance adhesion by the molding compound110shown inFIG.1B.

The grayscale lithographic processing shown inFIGS.5A through5Eyields an average slope α1 of the surface148of the polymer-based insulating material136which faces away from the underlying layer500that is less than 60 degrees, less than 45 degrees, less than 35 degrees, or even less than 20 degrees in a region of increasing thickness for the polymer-based insulating material136.

In contrast,FIG.6Eshows that the process which does not employ grayscale lithographic processing yields an average slope α2 greater than 60 degrees in a region of increasing thickness for the polymer-based insulating material136. The steeper sloped profile inFIG.6Earises because the photolithographic mask514used inFIGS.6A through6Edoes not yield an intermediary region for the polymer-based insulating material136having a more gradual thickness increase. Instead, the thickness transition is much more abrupt inFIG.6Ewhich can lead to crack formation in a metallization layer or layer stack to be formed above the polymer-based insulating material136.

The method shown inFIGS.5A through5Evaries the degree of cross-linking from the edge transition of the polymer-based insulating material136inward. The cross-linking variation may be applied in any region where the polymer-based insulating material136crosses a topology step. For example, the cross-linking variation may be applied in a region that includes gate fingers and/or a sensor line that are isolated from source potential. Separately or in combination, the cross-linking variation may be applied to a gate pad edge termination and/or any pads in general. Separately or in combination, the cross-linking variation may be applied to dicing edge of semiconductor chips (dies) where the chips are singulated. The grayscale lithography embodiments described herein may provide energy saving and mitigation of energy use, by improving power MOSFET reliability. The improved reliability allows for a durable use of the power MOSFET, e.g., in a solar cell. A durable use means sustainability and therefore, energy use is mitigated by using the grayscale lithography embodiments described herein.

Example 1. A semiconductor device, comprising: a semiconductor substrate having a first main surface; a metal structure above the first main surface of the semiconductor substrate, the metal structure having a periphery region that includes a transition section along which the metal structure transitions from a first thickness to a second thickness less than the first thickness; and a polymer-based insulating material in contact with and covering at least the periphery region of the metal structure, wherein a thickness of the polymer-based insulating material begins to increase on a first main surface of the metal structure that faces away from the semiconductor substrate and continues to increase in a direction towards the transition section of the metal structure, wherein an average slope of a surface of the polymer-based insulating material which faces away from the semiconductor substrate, as measured with respect to the first main surface of the metal structure, is less than 60 degrees along the periphery region of the metal structure.

Example 2. The semiconductor device of example 1, wherein the average slope of the polymer-based insulating material is less than 45 degrees.

Example 3. The semiconductor device of example 1, wherein the average slope of the polymer-based insulating material is less than 35 degrees.

Example 4. The semiconductor device of example 1, wherein the average slope of the polymer-based insulating material is less than 20 degrees.

Example 5. The semiconductor device of any of examples 1 through 4, wherein the semiconductor device is a power transistor, wherein the metal structure is at a source potential and laterally separated from an additional metal structure which is at a second potential that is different from the source potential, and wherein the polymer-based insulating material covers the additional metal structure.

Example 6. The semiconductor device of any of examples 1 through 5, wherein the polymer-based insulating material is a polyimide.

Example 7. The semiconductor device of any of examples 1 through 6, wherein the polymer-based insulating material has undulations over the transition section of the metal structure.

Example 8. A semiconductor device, comprising: a semiconductor substrate having a first main surface; a first electrically conductive structure above the first main surface of the semiconductor substrate, the first electrically conductive structure having a region; a polymer-based insulating material in contact with and covering at least the region of the first electrically conductive structure, wherein a thickness of the polymer-based insulating material begins to increase on a first main surface of the first electrically conductive structure that faces away from the semiconductor substrate, wherein an average slope of a surface of the polymer-based insulating material which faces away from the semiconductor substrate, as measured with respect to the first main surface of the first electrically conductive structure, is less than 60 degrees along the region of the first electrically conductive structure; and a second electrically conductive structure above the polymer-based insulating material.

Example 9. The semiconductor device of example 8, wherein the semiconductor device is a power transistor, wherein the first electrically conductive structure is at a source potential, and wherein the second electrically conductive structure contacts the first electrically conductive structure outside the region of the first electrically conductive structure that is in contact with and covered by the polymer-based insulating material.

Example 10. The semiconductor device of example 8 or 9, wherein the polymer-based insulating material is a polyimide.

Example 11. A method of producing a semiconductor device, the method comprising: forming a metal structure above a first main surface of a semiconductor substrate, the metal structure having a periphery region that includes a transition section along which the metal structure transitions from a first thickness to a second thickness less than the first thickness; forming a polymer-based insulating material on at least the periphery region of the metal structure; varying a degree of polymer cross-linking within the polymer-based insulating material along the periphery region of the metal structure, such that the degree of the polymer cross-linking increases with increasing thickness of the polymer-based insulating material; and after varying the degree of the polymer cross-linking, curing the polymer-based insulating material.

Example 12. The method of example 11, wherein varying the degree of the polymer cross-linking comprises: applying grayscale lithography to a region with increasing thickness of the polymer-based insulating material.

Example 13. The method of example 12, wherein applying the grayscale lithography to the region with increasing thickness of the polymer-based insulating material comprises: forming a photolithographic mask on the polymer-based insulating material, the photolithographic mask comprising a grayscale zone disposed over the region with increasing thickness of the polymer-based insulating material and having a plurality of shapes; and directing light towards the photolithographic mask, wherein the plurality of shapes in the grayscale zone of the photolithographic mask block some of the light from reaching the region with increasing thickness of the polymer-based insulating material.

Example 14. The method of example 13, wherein at least one of a size of the shapes in the grayscale zone of the photolithographic mask or a spacing between the shapes in the grayscale zone of the photolithographic mask varies with increasing thickness of the polymer-based insulating material.

Example 15. The method of example 14, wherein the size of the shapes is in a range of a sub-resolution of the polymer-based insulating material.

Example 16. The method of any of examples 13 through 15, wherein forming the photolithographic mask comprises: sputtering a chromium layer on a glass substrate; and etching the shapes into the chromium layer.

Example 17. The method of any of examples 13 through 15, wherein forming the photolithographic mask comprises: sputtering a plurality of chromium layers of different thicknesses on a glass substrate.

Example 18. The method of any of examples 11 through 17, wherein the semiconductor device is a power transistor, wherein the metal structure is at a source potential and laterally separated from an additional metal structure which is at a second potential that is different from the source potential, and wherein the polymer-based insulating material covers the additional metal structure.

Example 19. The method of example 18, further comprising: forming a metallization layer or layer stack over the metal structure and over the additional metal structure, wherein the metallization layer or layer stack contacts the metal structure, wherein the additional metal structure is insulated from the metallization layer or layer stack by the polymer-based insulating material.

Example 20. The method of any of examples 11 through 19, wherein forming the polymer-based insulating material comprises: forming one or more polyimide layers on the periphery region of the metal structure.

Example 21. A semiconductor device, comprising: a semiconductor substrate having a first main surface; a metal structure above the first main surface of the semiconductor substrate, the metal structure having a periphery region that includes a transition section along which the metal structure transitions from a first thickness to a second thickness less than the first thickness; and a polymer-based insulating material in contact with and covering at least the periphery region of the metal structure, wherein a thickness of the polymer-based insulating material begins to increase on a first main surface of the metal structure that faces away from the semiconductor substrate and continues to increase in a direction towards the transition section of the metal structure, wherein the polymer-based insulating material has undulations over the transition section of the metal structure.

Example 22. The semiconductor device of example 21, wherein the semiconductor device is a power transistor, wherein the metal structure is at a source potential and laterally separated from a gate finger or a sensor line which is at a different potential than the source potential, and wherein the polymer-based insulating material covers the gate finger or sensor line.

Example 23. The semiconductor device of example 21 or 22, wherein the polymer-based insulating material is a polyimide.