Passive power factor correction circuit, electronic device applying the same and operation methods thereof

A passive power factor correction circuit includes: a DC capacitor and an input capacitor, coupled to a rectifying circuit and charged by a DC voltage from the rectifying circuit; an output capacitor, coupled to a load; first diode and a second diode, coupled to the input capacitor and the output capacitor; and an inductor, coupled to the load, the input capacitor and the output capacitor. Charging into and discharging from the DC capacitor are completed within a half cycle of an input AC voltage.

This application claims the benefit of Taiwan application Serial No. 101131025, filed Aug. 27, 2012, the disclosure of which is incorporated by reference herein in its entirety.

TECHNICAL FIELD

The disclosed embodiments relate to a passive power factor correction circuit, an electronic device applying the same, and operation methods thereof.

BACKGROUND

Due to an output filter capacitor, a substantial amount of harmonic distortion exists in an input current of a conventional bridge rectifying circuit. The harmonic distortion leads a low power factor and severe current total harmonic distortion that undesirably affect an input power. Therefore, power factor correction needs to be performed on a conventional bridge rectifying circuit.

Based on whether active switch elements are included, power factor correction circuits are categorized into two types—a passive type and an active type.

An active power factor correction circuit yields a power factor of above 0.99 and has current total harmonic distortion of less than 10%. An active power factor correction circuit further has a wide-range input voltage, a stable output voltage and small magnetic components as well as being unaffected by output power change.

In order to reduce electromagnetic interference of high-frequency components, a switching frequency of an active switch in a low-frequency power factor correction circuit is twice of the market-electricity frequency. Through changes in a cut-off time and a conduction time of a power switch, a low-frequency power factor correction circuit renders a quite satisfactory power factor. A low-frequency power factor correction circuit is advantaged by having high efficiency and simple control, requiring no high-speed power elements, and being high-frequency electromagnetic interference-free. For inverter-based household appliances, a low-frequency power factor correction circuit effectively improves the power factor and reduces current total harmonic distortion.

Although having a power factor lower than that of an active power factor correction circuit, a passive power factor correction circuit is still capable of increasing the power factor of a circuit to 0.7 to 0.9 and reducing current total harmonic distortion to below 50%. In addition, a passive power factor correction circuit, having advantages of requiring no active switch elements as well as being simple in circuit structure, low in cost and electromagnetic interference-free as it does not contain any active switch elements, is prevalent in medium-power and small-power electronic apparatuses.

SUMMARY

The disclosure is directed to a passive power factor correction circuit, an electronic device applying the same, and operation methods thereof.

According to an exemplary embodiment of the disclosure, a passive power factor correction circuit is provided. The passive power factor correction circuit includes a DC capacitor, an input capacitor, an output capacitor, a first diode, a second diode and an inductor. The DC capacitor is coupled to a rectifying circuit, and charged by a DC voltage from the rectifying circuit. The input capacitor is coupled to the rectifying circuit, and charged by the DC voltage from the rectifying circuit. The output capacitor is coupled to a load. The first diode is coupled to the input capacitor and the output capacitor. The second diode is coupled to the input capacitor and the output capacitor. The inductor is coupled to the load, the input capacitor and the output capacitor. Charging into and discharging from the DC capacitor are within a half cycle of an input AC voltage.

According to another exemplary embodiment of the disclosure, an electronic device is provided. The electronic device includes: a filter, a rectifying circuit, a passive power factor correction circuit and a load. The filter is for filtering an input AC voltage. The rectifying circuit is coupled to the filter and for rectifying the filtered input AC voltage to a DC voltage. The passive power factor correction circuit is coupled to the rectifying circuit. The load is driven by the passive power factor correction circuit. The passive power factor correction circuit includes: a DC capacitor, an input capacitor, an output capacitor, a first diode, a second diode, and an inductor. The DC capacitor is coupled to the rectifying circuit, and charged by the DC voltage from the rectifying circuit. The input capacitor is coupled to the rectifying circuit and charged by the DC voltage from the rectifying circuit. The output capacitor is coupled to the load. The first diode is coupled to the input capacitor and the output capacitor. The second diode is coupled to the input capacitor and the output capacitor. The inductor is coupled to the load, the input capacitor and the output capacitor. Charging into and discharging from the DC capacitor are within a half cycle of the input AC voltage.

According to an alternative exemplary embodiment of the disclosure, an operation method of a passive power factor correction circuit and an operation method of an electronic device are provided. The operation method is applicable to the above passive power factor correction circuit and/or the above electronic device. An input AC voltage is filtered and rectified into a DC voltage. An operating mode of the passive power correction circuit is determined according to the DC voltage. Under a first operating mode, the DC voltage charges the DC capacitor, the inductor and the output capacitor. Under a second operating mode, the DC voltage charges the DC capacitor, the input capacitor, the inductor and the output capacitor. Under a third operating mode, the DC voltage terminates charging the DC capacitor and the input capacitor, and the DC voltage and a voltage across the DC capacitor charge the output capacitor via the inductor. Under a fourth operating mode, the second diode is conducting such that the input capacitor charges the inductor and the output capacitor via the second diode.

DETAILED DESCRIPTION

A passive power factor correction circuit according to one embodiment at least includes multiple capacitors, multiple diodes and at least one inductor. In the passive power factor correction circuit according to one embodiment of the disclosure, charging into and discharging from a capacitor are completed within a half cycle of an input AC voltage. At the beginning of the half cycle, the input voltage charges the capacitor. Before the half cycle ends, electric energy stored in the capacitor is transmitted and released to a load. Accordingly, not only a conduction time of the diodes is increased but also conduction current is reduced, so that a power factor of a circuit is improved and undesirable effects of the capacitor on the power factor of the circuit are also mitigated.

FIG. 1shows a circuit schematic diagram of an electronic device according to one embodiment. As shown inFIG. 1, the passive power factor correction circuit receives a DC voltage Vdcgenerated from filtering and rectifying an input AC voltage Vac.

A filter filters the input AC voltage Vac. A rectifying circuit110is coupled to the filter, and rectifies the filtered input AC voltage Vacto the DC voltage Vdc. The filter includes an inductor Lrand a capacitor Cr. The inductor Lris coupled to the input AC voltage Vac, the capacitor Crand the rectifying circuit110. The capacitor Cris coupled to the inductor Lrand the rectifying circuit110.

The passive power factor correction circuit, coupled to the rectifying circuit110, includes a DC capacitor Cdc, an input capacitor C1, a first diode D1and a second diode D2, an inductor L, and an output capacitor C2. The passive power factor correction circuit may drive a load120.

After filtering the input AC voltage Vacand rectifying the filtered input AC voltage Vacby the rectifying circuit110(e.g., a bridge rectifier), the DC voltage Vdchaving double-frequency components is obtained.

The DC capacitor Cdcis coupled to the rectifying circuit110, and, is for example, coupled in parallel to the rectifying circuit110. The DC capacitor Cdcis further coupled to the input capacitor C1, the first and second diodes D1and D2, the inductor L, the output capacitor C2and the load120.

During operations, the DC capacitor Cdcmay be directly charged by the DC voltage Vdc. Electric energy stored in the DC capacitor Cdcmay charge the inductor L and the capacitor C2.

The input capacitor C1is coupled to the rectifying circuit110, the DC capacitor Cdc, the first and second diodes D1and D2, and the inductor L. During operations, the input capacitor C1may be directly charged by the DC voltage Vdc. Further, the electric energy stored in the input capacitor C1may charge the inductor L and the output capacitor C2via the second diode D2. The input current gradually diminishes as the energy is released from the input capacitor C1.

The first diode D1is coupled to the input capacitor C1, the output capacitor C2, the second diode D2, the inductor L and the load120. When the first diode D1is conducted, the input capacitor C1and the output capacitor C2may be charged by the DC voltage Vdc.

The second diode D2is coupled to the rectifying circuit110, the DC capacitor Cdc, the input capacitor C1, the output capacitor C2, the first diode D1and the load120. When the second diode D2is conducted, the electric energy stored in the input capacitor C1may charge the output capacitor C2and the inductor L.

The inductor L is coupled to the rectifying circuit110, the DC capacitor Cdc, the input capacitor C1, the first diode D1, the output capacitor C2and the load120. The inductor L may be charged by the DC voltage Vdc, the DC capacitor Cdc, and/or the input capacitor C1.

The output capacitor C2is coupled to the rectifying circuit110, the DC capacitor Cdc, the first and second diodes D1and D2, the inductor L and the load120. The output capacitor C2may be charged by the DC voltage Vdc, the DC capacitor Cdc, and/or the input capacitor C1.

To clearly explain operation principles of a passive power factor correction circuit according to one embodiment of the disclosure, in the description below, assume that all circuit elements are ideal, and a capacitance value of the output capacitor C2is large enough to maintain an output voltage VOapproximate to a constant value. Further, assume that the load120is a pure resistor, for example. An operating mode of the passive power factor correction circuit may be determined according to the DC voltage Vdc. Details of operation principles of a passive power factor correction circuit according to one embodiment of the disclosure are as described below.

FIG. 2shows an equivalent circuit and signal waveforms of a passive power factor correction circuit under an operating mode1according to one embodiment of the disclosure.

The DC voltage Vdcincreases as the input AC voltage Vacincreases until the DC voltage Vdcis greater than a voltage across the DC capacitor Cdcand is also greater than a sum of a voltage across the output capacitor C2and a voltage VLof the inductor L. Under such conditions, the DC voltage Vdccharges the DC capacitor Cdc, the inductor L and the output capacitor C2.

When the passive power factor correction circuit is under the operating mode1, status equations thereof are as shown below, where Vmis a peak value of the input AC voltage Vac, VOis an output voltage, iLis an inductor current, idis an output current having been rectified by the rectifying circuit110, and R is an impedance value of the load120:

When the DC voltage Vdccontinues increasing to the sum of a voltage VC1across the input capacitor C1and the voltage across the output capacitor C2, the passive power factor correction circuit enters an operating mode2.

FIG. 3shows an equivalent circuit and signal waveforms of a passive power factor correction circuit under an operating mode2according to one embodiment of the disclosure.

When the DC voltage Vdcincreases to the sum of the voltage VC1across the input capacitor C1and the voltage across the output voltage C2, the DC voltage Vdccharges the input capacitor C1and the output capacitor C2via the first diode D1. At this point, the DC voltage Vdccharges the DC capacitor Cdc, the input capacitor C1, the inductor L and the output capacitor C2, with the equivalent circuit and current paths as shown inFIG. 3.

When the passive power factor correction circuit is under the operating mode2, status equations thereof are as shown below:

As the input AC voltage Vacdecreases after having reached a maximum value, the DC voltage Vdcalso decreases as the input AC voltage Vacdecreases. Therefore, the DC voltage Vdcbecomes smaller than the sum of the voltage VC1across the input capacitor C1and the voltage across the output voltage C2. At this point, the passive power factor correction circuit enters an operating mode3.

FIG. 4shows an equivalent circuit and signal waveforms of a passive power factor correction circuit under an operating mode3according to one embodiment of the disclosure.

As the input AC voltage Vacdecreases after having reached a maximum value, the DC voltage Vdcalso decreases as the input AC voltage Vacdecreases. Therefore, when the DC voltage Vdcis smaller than the sum of the voltage VC1across the input capacitor C1and the voltage across the output voltage C2, the DC voltage Vdcstops charging the DC capacitor Cdcand the input capacitor C1. At this point, the DC voltage Vdcand a voltage across and the DC capacitor Cdcpass through the inductor L to charge the output capacitor C2, with the equivalent circuit and current paths as shown inFIG. 4.

It is observed fromFIG. 4that, from a perspective of discharging paths, since the DC capacitor Cdc(which is currently discharging) and the output capacitor C2may be regarded as being coupled in series (the output capacitor C2discharges into the load120), the passive power factor correction circuit under the operating mode3may be regarded as in “series discharge”.

When the passive power factor correction circuit is under the operating mode3, status equations thereof are as shown below:

When the DC voltage Vdcis smaller than the voltage Vc1across the input capacitor C1, the passive power factor correction circuit enters an operating mode4.

FIG. 5shows an equivalent circuit and signal waveforms of a passive power factor correction circuit under an operating mode4according to one embodiment of the disclosure.

When the DC voltage Vdcis smaller than the voltage Vc1across the input capacitor C1, and the voltage Vc1across the input capacitor C1is greater than the sum of the voltage across the output capacitor C2and the voltage VLof the inductor L, the second diode D2is conducted such that the input capacitor C1charges the inductor L and the output capacitor C2via the second diode D2.

It is observed fromFIG. 5that, from a perspective of discharging paths, since the DC capacitor Cdc(which is currently discharging) and the input capacitor C1may be regarded as being coupled in parallel, the passive power factor correction circuit under the operating mode4may be regarded as in “parallel discharge”.

Therefore, according to one embodiment of the disclosure, within a half cycle (i.e., the operating mode1to the operating mode4) of the input AC voltage Vac, the passive power factor correction circuit changes from series discharge to parallel discharge to thereby eliminating ripples.

When the voltage across the DC capacitor Cdcis smaller than the sum of the voltage across the output capacitor C2and the voltage VLof the inductor L, the passive power factor correction circuit completes one charge-discharge cycle of the DC capacitor Cdc(i.e., a half cycle of the input AC voltage Vac).

When the passive power factor correction circuit is under the operating mode4, status equations thereof are as shown below:

It is concluded from the above descriptions that, before a half of an operating cycle of the input AC voltage ends, the electric energy stored in the DC capacitor Cdcis transferred and discharged to the load120. Therefore, it is seen from the above waveforms that, the input power may charge the DC capacitor Cdcat the beginning of a second half of the operating cycle of the input AC voltage. Not only the conduction time of the rectifying diodes can be increased but also the conduction current is decreased, so that the power factor of the circuit is improved and undesirable effects of the capacitor on the power factor of the circuit are also mitigated.

According to another embodiment of the disclosure, an electronic device is provided. The electronic device includes the above passive power factor correction circuit, a filter, a rectifying circuit and a load. Details of the electronic device can be referred to in the above descriptions, and shall be omitted herein.

According to another embodiment of the disclosure, an operation method of a passive power factor correction circuit is provided. According to yet another embodiment of the disclosure, an operation method of an electronic device is provided. An input AC voltage is filtered and rectified to obtain a DC voltage. An operating mode of the passive power factor correction circuit is determined according to the DC voltage. Details of determining the operating mode of the passive power factor correction circuit can be referred to in the above descriptions, and shall be omitted herein. Further, operation details of the passive power factor correction circuit under different operating mode are also as described above, and shall be omitted herein.

In a passive power factor correction factor according to one embodiment of the disclosure, the input power or the input voltage can be changed by changing the conduction time of the circuit, and the output power or the output voltage can be changed by changing the frequency of the input AC voltage. The time constants can be changed by changing the capacitance values of the capacitors, so that the charging/discharging time of the capacitors can be a desired value. The time constants can be changed by changing the inductance value of the inductor, so that the charging/discharging time of the inductor can be a desired value.

It is demonstrated by descriptions of the embodiments that, the passive power factor correction circuit is unlikely affected by the input voltage, the frequency of the input voltage and the output power, and is thus capable of maintaining a highly satisfactory power factor correction effect.

The passive power factor correction circuit according to one embodiment of the disclosure features high efficiency (e.g., 95.5%), a high power factor (e.g., 0.92), a high resource recycle rate and a long lifespan.

As the passive power factor correction circuit according to one embodiment of the disclosure does not include active switch elements, electromagnetic interference resulted by active switch elements can be mitigated.

Further, as the passive power factor correction circuit according to one embodiment of the disclosure does not include electrolytic capacitors, a lifecycle of the circuit can be prolonged.