Method of manufacturing semiconductor device and semiconductor device

To provide a semiconductor device having a reduced size and thickness while suppressing deterioration in reliability. After a semiconductor wafer is ground at a back surface thereof with a grinding material into a predetermined thickness, the resulting semiconductor wafer is diced along a cutting region to obtain a plurality of semiconductor chips. While leaving grinding grooves on the back surface of each of the semiconductor chips, the semiconductor chip is placed on the upper surface of a die island via a conductive resin paste so as to face the back surface of the semiconductor chip and the upper surface of the die island each other. The die island has, on the upper surface thereof, a concave having a depth of from 3 μm to 10 μm from the edge of the concave to the bottom of the concave.

CROSS-REFERENCE TO RELATED APPLICATIONS

The disclosure of Japanese Patent Application No. 2012-046330 filed on Mar. 2, 2012 including the specification, drawings, and abstract is incorporated herein by reference in its entirety.

BACKGROUND

The present invention relates to a method of manufacturing a semiconductor device and a semiconductor device, in particular, to a technology effective when applied to a semiconductor device having a package structure in which an external terminal electrically coupled to the back surface of a semiconductor chip and an external terminal electrically coupled to a bonding pad formed on the surface of the semiconductor chip are exposed from the lower surface of a resin molding.

For example, Japanese Patent Laid-Open No. 2007-324523 (Patent Document 1) discloses a method of sintering a metal paste composed of metal powders and an organic solvent and applied to a semiconductor chip to obtain sintered powder metal, mounting a Ni plate on the semiconductor chip, heating and applying a pressure to them to bond the semiconductor chip and the Ni plate.

Japanese Patent Laid-Open No. 2004-126622 (Patent Document 2) discloses a technology of mounting, in high density, light emitting diodes each equipped with a plurality of electrodes provided on a substrate with a space therebetween, a plurality of light emitting diodes provided on the electrodes, respectively, via a conductive adhesive, and an insulating layer provided on the substrate so as to surround the conductive adhesive with the insulating layer, wherein the insulating layer is made of a material having poor wettability to the conductive adhesive.

Japanese Utility Model Laid-Open No. 59357/1988 (Patent Document 3) discloses a light emitting diode having a rough back surface and an ohmic electrode provided on a portion of the rough surface and firmly bonded, on the back surface side, to a base via a conductive adhesive.

SUMMARY OF THE INVENTION

With a reduction in size and thickness of electronic devices, a semiconductor device (semiconductor package) mounted on electronic devices is also required to have a reduced size and reduced thickness.

The present inventors have therefore studied for realizing a reduction in size and thickness of semiconductor devices by using electroplating with a base material made of a metal as a mother substrate to form external terminals (leadframe, lead, terminal, metal plate, and conductive pattern).

Described specifically, the present inventors have studied the structure in which die islands and a plurality of electrode terminals (electrodes) serving as external terminals are formed by electroplating; a semiconductor chip is placed on the upper surface of the die island while facing the upper surface of the die island and the back surface of the semiconductor chip; and the plurality of electrode terminals and a plurality of bonding pads (electrode pads, surface electrodes) formed on the surface of the semiconductor chip are electrically coupled via a plurality of conductive members, respectively.

As a result of investigation by the present inventors, semiconductor devices having such a structure have however various technical problems which will be described below.

The upper surface of the die island and the back surface of the semiconductor chip are electrically coupled via a conductive resin paste. It has been elucidated that the deficiency or excess of the conductive resin paste causes a trouble, leading to the formation of a semiconductor device having deteriorated reliability.

The supply amount of the conductive resin paste has conventionally been controlled by regulating a discharge pressure and discharge time of the conductive resin paste. It is however difficult to supply a constant amount of the conductive resin paste only by using this method. When the amount of the conductive resin paste exceeds an appropriate supply amount, for example, the conductive resin paste runs along the side surface of a die island and inevitably protrudes from the lower surface (back surface) of a resin molding for sealing the semiconductor chip, the die island, and the like. When the amount of the conductive resin paste is below the appropriate supply amount, on the other hand, the semiconductor chip is separated from the upper surface of the die island due to the lack of wetting.

The present invention therefore provides a technology capable of avoiding the above-mentioned troubles such as protrusion of the conductive resin paste to the lower surface of the resin molding or peeling of the semiconductor chip by adjusting the spreading of the conductive resin paste to be used for coupling between the upper surface of the die island and the back surface of the semiconductor chip.

An object of the invention is to provide a technology capable of manufacturing a semiconductor device having a reduced size and thickness without deteriorating the reliability of the semiconductor device.

The above-mentioned and the other objects and novel features of the invention will be apparent from the description herein and accompanying drawings.

An embodiment of a typical invention, among inventions disclosed herein, will next be described simply.

In this embodiment, there is provided a method of manufacturing a semiconductor device including the following steps. After the second main surface of a semiconductor wafer is ground with a grinding material and the semiconductor wafer is thinned while leaving a grinding groove on the second main surface, the semiconductor wafer is diced along a cutting region while leaving the grinding groove on the second main surface of the semiconductor wafer to obtain semiconductor chips. Separately, a mother substrate having thereon a die island and a plurality of electrode terminals placed around the die island and having a plurality of chip mounting regions is provided. The die island has, on the upper surface thereof, a concave and this concave has a depth of from 3 μm to 10 μm from the edge to the bottom of the concave. While leaving the grinding groove on the back surface of the semiconductor chip, the semiconductor chip is placed on the upper surface of the die island via a conductive resin paste so that the back surface of the semiconductor chip and the upper surface of the die island face each other. Then, a plurality of bonding pads of the semiconductor chip and a plurality of electrode terminals on the mother substrate are electrically coupled via a plurality of conductive members, respectively. A resin molding is then formed to encapsulate therewith the semiconductor chip, the plurality of conductive members, a portion of the die island, a portion of each of the electrode terminals, and the upper surface of the mother substrate. The mother substrate is separated from the resin molding and the lower surface of the die island and the lower surface of the electrode terminals are exposed from the resin molding.

In this embodiment, there is also provided a resin molded semiconductor device. The semiconductor device has a die island; a semiconductor chip having a surface, a plurality of bonding pads formed on the surface, and a back surface on the side opposite to the surface, and being placed on the upper surface of the die island so that the back surface of the semiconductor chip and the upper surface of the die island face each other; a plurality of electrode terminals; a plurality of conductive members for electrically coupling the plurality of bonding pads and the upper surfaces of the plurality of electrode terminals, respectively; and a resin molding. The back surface of the semiconductor chip is coupled to the upper surface of the die island via a conductive resin paste while having a plurality of visible grinding grooves on the back surface of the semiconductor chip; the lower surface of the die island and the lower surface of the plurality of electrode terminals are exposed from the resin molding; and the upper surface of the die island has a concave having a depth of from 3 μm to 10 μm from the edge to the bottom of the die island.

Advantage available by one typical embodiment of the invention disclosed herein will next be described briefly.

An object of the invention is to provide a technology capable of providing a semiconductor device having a reduced size and reduced thickness without deteriorating the reliability of the semiconductor device.

DETAILED DESCRIPTION

In the following embodiment, a description will be made after divided into a plurality of sections or embodiments if necessary for convenience sake. They are not independent from each other, but in a relation such that one is a modification example, details, a complementary description, or the like of a part or whole of the other one unless otherwise specifically indicated.

And, in the below-described embodiments, when a reference is made to the number of elements (including the number, value, amount, range, or the like), the number is not limited to a specific number but may be greater than or less than the specific number, unless otherwise specifically indicated or principally apparent that the number is limited to the specific number. Further, in the below-described embodiments, it is needless to say that the constituting elements (including element steps or the like) are not always essential unless otherwise specifically indicated or principally apparent that they are essential. Similarly, in the below-described embodiments, when a reference is made to the shape, positional relationship, or the like of the constituting elements, that substantially approximate or similar to it is also embraced unless otherwise specifically indicated or principally apparent that it is not. This also applies to the above-described value and range.

In the drawings used in the below-described embodiment, some plan views may be hatched in order to facilitate viewing of them. In the below-described embodiments, the term “wafer” mainly means a Si (silicon) single crystal wafer, but the term “wafer” means not only it but also an SOI (silicon on insulator) wafer, an insulating film substrate for forming an integrated circuit thereover, or the like. The shape of the wafer is not limited to circular or substantially circular, but it may be square, rectangular or the like.

The symbol “# (mesh)” used in the following embodiment indicates the roughness of a grinding material and the numeral following it means the size of abrasive grains on the surface of the grinding material (refer to “JIS R 6001 Bonded abrasive grain sizes”). When measurement is made according to the electrical resistance testing method, for example, #360 means a grinding material having the maximum grain size of 86 μm or less and the grain size of about 35.0 μm at 50% point of cumulative height; and for example #2000 means a grinding material having the maximum grain size of 19 μm or less and the grain size of about 6.7 μm at 50% point of cumulative height.

In the following embodiment, the term “diamond wheel” is a grinding wheel having diamond abrasive grains distributed uniformly therein for grinding a workpiece (semiconductor wafer) and it embraces a two-layer structure comprised of a base not containing diamond abrasive grains and an abrasive layer containing diamond abrasive grains. The diamond wheel having a two layer structure may be either a wheel whose abrasive layer portion forms a continuous loop or a wheel whose abrasive layer portion is attached with chips at intervals (segment type).

And, in all the drawings for describing the below-described embodiment, members of a like function will be identified by like reference numerals in principle and overlapping descriptions will be omitted. Hereafter, the embodiment of the invention will be described in detail based on drawings.

Embodiment

Semiconductor Device

The semiconductor device according to the embodiment of the invention will be described referring toFIGS. 1 to 3.FIG. 1is a fragmentary plan view of a semiconductor device through a resin molding member on the surface side;FIG. 2is a fragmentary plan view of the back surface (mounting surface) side of the semiconductor device; andFIG. 3is a fragmentary cross-sectional view of the semiconductor device taken along the line A-A′ ofFIG. 1.

A semiconductor device (semiconductor package)1is comprised of a semiconductor chip2, a die island (first electrode plate)3ahaving thereon the semiconductor chip2and serving as an external terminal, a plurality of electrode terminals (second electrode plates, electrodes)3bprovided at the periphery of the semiconductor chip2and serving as an external terminal, and a plurality of conductive members5for electrically coupling a plurality of bonding pads (electrode pads, surface electrodes)4provided on the surface of the semiconductor chip2and the plurality of electrode terminals3b. In the present embodiment, a semiconductor device having 5 pins of external terminals (1 pin of the die island3aand 4 pins of the electrode terminals3b) is shown as an example.

The semiconductor chip2has a surface and a back surface which is on the side opposite to that of the surface. The semiconductor chip2has, on the surface side thereof, for example, an integrated circuit comprised of a plurality of semiconductor elements, a multilayer wiring layer obtained by stacking a plurality of insulating layers and a plurality of wiring layers, and a surface protecting film formed so as to cover the multilayer wiring layer.

The plurality of bonding pads4provided on the surface of the semiconductor chip2is comprised of wirings (for example, aluminum (Al)) of the uppermost layer, among multilayer wirings (not illustrated) formed on the integrated circuit and they are exposed from an opening portion (not illustrated) formed in a surface protecting film (not illustrated) for protecting the integrated circuit.

The back surface of the semiconductor chip2and the upper surface (surface) of the die island3aface each other and the semiconductor chip2is placed on the upper surface of the die island3avia a conductive resin paste6. The conductive resin paste6is made of, for example, silver (Ag). The semiconductor chip2has on the back surface thereof a number of grinding grooves, some of which can be visually recognized.

The die island3aand the plurality of electrode terminals3beach have an upper surface (a surface) and a lower surface (back surface, mounting surface) on the side opposite to the upper surface. The die island3aand the plurality of electrode terminals3bare films (aggregate of metal particles) formed (deposited) by plating. More specifically, a nickel (Ni) film is deposited on a gold (Au) film and a silver (Ag) film is deposited on this nickel (Ni) film. The gold (Au) film has a thickness of, for example, 0.1 μm, the nickel (Ni) film has a thickness of, for example, 60 μm, and the silver (Ag) film has a thickness of, for example, 3 μm. Instead of the silver (Ag) film, a gold (Au) film may be formed on the nickel (Ni) film. The vertical (first direction) and horizontal (second direction orthogonal to the first direction) sizes of the die island3when viewed from the top are smaller than those of the semiconductor chip2when viewed from the top and the semiconductor chip2covers the entire upper surface of the die island3a.

Moreover, portions (upper surface and side surface) of the semiconductor chip2, a portion (side surface) of the die island3a, portions (upper surface and side surface) of each of the plurality of electrode terminals3b, and the plurality of conductive members5are sealed with a resin molding (molding)7. From the lower surface (back surface) of the resin molding7, however, the other portion (lower surface) of the die island3aand the plurality of electrode terminals3bare exposed.

As described above, the back surface of the semiconductor chip2and the upper surface of the die island3aface each other and the semiconductor chip2is placed on the upper surface of the die island3avia the conductive resin paste6. The die island3ahas an upper surface not flat but having a concave (recess)8at the center portion thereof. The concave8is a region (reservoir region) where the conductive resin paste6gathers. The depth of the concave8from its edge to the bottom (a difference between a distance (corresponding to L1inFIG. 3) from the back surface of the semiconductor chip2to the upper surface of the die island3afarthest from the back surface of the semiconductor chip2and a distance (corresponding to L2inFIG. 3) from the back surface of the semiconductor chip2to the upper surface of the die island3aclosest from the back surface of the semiconductor chip2) is, for example, from 3 μm to 10 μm. By providing this concave8on the upper surface of the die island3aand forming a grinding groove on the back surface of the semiconductor chip2, lack of wettability with the conductive resin paste6can be overcome and dripping of the conductive resin paste6to the side surface of the die island3acan be prevented. Such effects will be described in detail in the manufacturing method of a semiconductor device which will be described later. The above-mentioned concave8is also formed at the center portion of the upper surface of the plurality of electrode terminals3b.

The distance (corresponding to L2inFIG. 3) from the back surface of the semiconductor chip2to the upper surface of the die island3aclosest to the back surface of the semiconductor chip2is, for example, from 5 μm to 8 μm. This distance is not limited to it, because it is determined, depending on the grain size of a filler contained in the conductive resin paste6.

<Manufacturing Method of Semiconductor Device>

Next, a manufacturing method of a semiconductor device having 5 pins of external terminals according to First Embodiment of the invention will next be described in the order of steps while referring toFIGS. 4 to 27.

FIG. 4is a fragmentary top view of a semiconductor wafer in a wafer providing step;FIG. 5is a schematic view of a back grinding apparatus to be used for the manufacture of the semiconductor device;FIG. 6is a fragmentary view of the back surface of the semiconductor wafer in a back grinding step;FIG. 7is a fragmentary top view of the semiconductor wafer in a wafer dicing step;FIGS. 8 to 19are views for describing a die bonding step, in whichFIG. 8is a fragmentary top view of a mother substrate,FIG. 9is a fragmentary cross-sectional view of the mother substrate,FIG. 10is a flow chart for describing a manufacturing method of a mother substrate having a plurality of external terminals (a die island and electrode terminals),FIGS. 11 to 18are fragmentary cross-sectional views of the mother substrate in each manufacturing step for describing the manufacturing method of the mother substrate having the plurality of external terminals (a die island and electrode terminals), andFIG. 19is a fragmentary cross-sectional view of the mother substrate in a die bonding step;FIG. 20is a fragmentary cross-sectional view of the mother substrate in a conductive resin paste baking step;FIG. 21is a fragmentary cross-sectional view of the mother substrate in a wire bonding step;FIG. 22is a fragmentary cross-sectional view of the mother substrate in a molding step;FIG. 23is a fragmentary cross-sectional view of the mother substrate in a mother substrate peeling step;FIG. 24is a fragmentary cross-sectional view of the mother substrate in a laser marking step;FIG. 25is a fragmentary cross-sectional view of the mother substrate in a package dicing step;FIG. 26is a fragmentary cross-sectional view of the mother substrate in a dicing sheet removing step; andFIG. 27is a flow chart for describing the method of manufacturing a semiconductor device.

Here, a method of manufacturing a semiconductor device having 5 pins of external terminals (1 pin of a die island and 4 pins of electrode terminals) will be described, but the invention is not limited thereto but can also be applied to a method of manufacturing a semiconductor device having, for example, 2 pins of external terminals or 7 pins of external terminals.

First, as shown inFIG. 4, a semiconductor wafer10is provided. The semiconductor wafer10is made of single crystal silicon and has a diameter of, for example, 200 mm or 300 mm and thickness (first thickness) of, for example, 0.7 mm or greater (thickness at the time when provided for manufacturing steps). The semiconductor wafer10has a first main surface (surface)10x, a plurality of chip regions CA partitioned in matrix on the first main surface10x, cutting regions (scribe regions, dicing regions, dicing lines) DL formed between two adjacent chip regions CA among the plurality of chip regions CA, and a second main surface (back surface) on the side opposite to the first main surface10x.

Each chip region CA on the first main surface10xof the semiconductor wafer10has an integrated circuit comprised of a plurality of semiconductor elements, a multilayer wiring layer obtained by stacking a plurality of insulating layers and a plurality of wiring layers, and a surface protecting film formed to cover the multilayer wiring layer, though not limited to it. The insulating layer is made of, for example, a silicon oxide film. The wiring layer is made of a metal film, for example, aluminum (Al), tungsten (W), or copper (Cu). The surface protecting film is made of a multilayer film obtained by stacking an inorganic insulating film such as silicon oxide film or silicon nitride film and an organic insulating film. In each chip region CA on the first main surface10xof the semiconductor wafer10, a plurality of bonding pads (electrode pads, surface electrodes)4electrically coupled to the plurality of semiconductor elements are placed along each side of each chip region CA. The bonding pads4are each made of a wiring of the uppermost layer of the multilayer wiring layers and exposed by an opening portion formed corresponding to the bonding pad4in the surface protecting film.

Next, the semiconductor wafer10is thinned to a predetermined thickness (second thickness) by grinding the second main surface of the semiconductor wafer10with a grinding material.

For the grinding of the second main surface of the semiconductor wafer10, for example, a back grinding apparatus12as shown inFIG. 5is used. This back grinding apparatus12is equipped with a chuck table13which rotates with the semiconductor wafer10thereon and a wheel15for holding therewith a grinding material14above the position opposite to the upper surface of the chuck table13.

First, a protecting tape (back grinding tape)11for covering the integrated circuit is attached to the semiconductor wafer10on the side of the first main surface10x.

Next, the semiconductor wafer10is placed on the upper surface of the chuck table13via the protecting tape11while facing the upper surface of the chuck table13of the back grinding apparatus12and the first main surface10xof the semiconductor wafer10each other.

Next, the chuck table13is rotated and the wheel15for holding the grinding material (for example, diamond wheel)14is rotated. Under such a state, a second main surface10yof the semiconductor wafer10is ground using the grinding material14by the rotation movement of the chuck table13and the rotation movement of the wheel15while supplying slurry to the second main surface10yof the semiconductor wafer10. By this grinding, the thickness of the semiconductor wafer10is reduced to a predetermined finished thickness (second thickness) and moreover, many grinding grooves are left on the second main surface10y. Some of the grinding grooves can be visually recognized. The grinding material14used in this grinding has roughness of, for example, from #320 to #4000, of which a roughness range with #2000 as a center is preferred. The finished thickness (second thickness) of the semiconductor wafer10is, for example, from 0.1 mm to 0.3 mm.

After that, the semiconductor wafer10is cleaned to remove the abrasive grains and contaminants attached to the second main surface10yof the semiconductor wafer10.

FIG. 6is a fragmentary plan view for describing the second main surface10yof the semiconductor wafer10after grinding. Many grinding grooves16, some of which are visible, have remained in the second main surface10yof the semiconductor wafer10. For example when the second main surface10yof the semiconductor wafer10is ground with the grinding material14with roughness of #2000, the roughness of the second main surface10yis, for example, about 0.2 μm in terms of the maximum height Ry (sum of the height of the highest summit and the depth of the deepest valley from the average line of a standard length portion sampled from the roughness curve in the direction thereof).

In the present embodiment, the semiconductor wafer10is thinned to a predetermined finished thickness (second thickness) and at the same time, many grinding grooves16are left in the second main surface10yby single grinding. It is also possible to conduct grinding twice, that is, first grinding (rough grinding) to reduce the thickness of the semiconductor wafer10to a thickness near the finished thickness (second thickness) and second grinding (finish grinding) for leaving many grinding grooves16intentionally. Described specifically, the semiconductor wafer10is ground into a thickness near the finish thickness (second thickness) with a rough grinding material (for example, from #320 to #360)14in the first grinding (rough grinding), followed by second grinding (finish grinding) using a grinding material (for example, from #500 to #4000) finer than the grinding material used in the first grinding (rough grinding). This makes it possible to decrease the time necessary for grinding and at the same time, leave the desired number of grinding grooves16having a desired depth.

The grinding grooves16which have been left in the second main surface10yof the semiconductor wafer10are left without removing the grinding grooves16in the second main surface10yof the semiconductor wafer10by using, for example, spin etch or CMP (Chemical Mechanical Polishing).

Next, as shown inFIG. 7, a circular frame17with a dicing tape attached thereto in advance is provided and the semiconductor wafer10is bonded to the upper surface of this dicing tape with the first main surface10xof the semiconductor wafer10up. Then, the semiconductor wafer10is diced vertically and horizontally along the cutting region DL by using an ultrathin circular dicing blade18having diamond fine grains attached thereto. The semiconductor wafer10is diced into individual semiconductor chips2. Even after individualization, the semiconductor chips2are fixed onto the frame17with the dicing tape so that they are still aligned in order.

Then, the dicing tape is exposed to ultraviolet rays from the lower surface side thereof to reduce the adhesion of the adhesive layer and facilitate peeling of each of the semiconductor chips2from the dicing tape.

[P4-1: Base Material Providing Step]

Next, as shown inFIG. 8, a mother substrate (substrate, base material, matrix)19is provided. The mother substrate19is made of a conductive member, for example, stainless (SUS430) or copper (Cu) and it is a multi-chip substrate in which regions (chip mounting regions DIA) each having one semiconductor chip2have been arranged in matrix form.FIG. 8shows a mother substrate19having three blocks, each block comprised of a plurality of chip mounting regions DIA. The mother substrate19has a thickness of, for example, 0.15 mm.

The mother substrate19has, at the center of one of the chip mounting regions DIA on the upper surface (surface, chip mounting surface) thereof, one pin of die island (first electrode plate)3aand, at the periphery thereof, a plurality (four pins in this embodiment) of electrode terminals (second electrode plates, electrodes)3b.

As shown inFIG. 9, the die island3aand the electrode terminals3bare each comprised of a film stack obtained by successively stacking a gold (Au) film, a nickel (Ni) film, and a silver (Ag) or gold (Au) film one after another in this order, for example, by electroplating and they have a mushroom-like shape with the nickel (Ni) film being canopied. Although the upper surfaces (the surfaces) of the die island3aand the electrode terminals3bare at positions higher than the upper surface of the mother substrate19, the die island3aand the electrode terminals3bcan be formed, by electroplating, with a thickness not greater than about half of the thickness of a lead made of a portion of a leadframe formed by patterning a conductive substrate (metal plate). In addition, the die island3aand the electrode terminals3beach having a mushroom-like shape can be expected to have an anchor effect of the die island3aand the electrode terminals3bin a molding step P7, that is, a manufacturing step conducted later. The thicknesses of the gold (Au) film, the nickel (Ni) film, and the silver (Ag) or gold (Au) film constituting the die island3aand the electrode terminals3bare, for example, 0.1 μm or greater, from 50 to 80 μm, and 2.5 μm or greater, respectively.

Next, a method of manufacturing the mother substrate19having thereon the die island3aand the electrode terminals3bwill be described referring toFIGS. 10 to 18.FIG. 10is a flow chart for describing the method of manufacturing the mother substrate19having thereon the die island3aand the electrode terminals3b; andFIGS. 11 to 18are fragmentary cross-sectional views of the mother substrate in each manufacturing step for describing the method of manufacturing the mother substrate19having the die island3aand the electrode terminals3b.

P4-1(1): Resist Applying Step to Exposure Step

As shown inFIG. 11, after application of a resist film20onto the upper surface of the mother substrate19, the resist film20is exposed to ultraviolet rays via a film mask21having a predetermined pattern. Similarly, after application of a resist film22onto a lower surface (back surface) on the side opposite to the upper surface of the mother substrate19, the resist film22is exposed to ultraviolet rays via a film mask23having a predetermined pattern.

As shown inFIG. 12, after removal of the film masks21and23, development treatment is given to pattern the resist film20applied to the upper surface of the mother substrate19and the resist film22applied to the lower surface of the mother substrate19. In the resist film20applied onto the upper surface of the mother substrate19, a die-island hole24afor forming the die island3atherein and an electrode-terminal hole24bfor forming the electrode terminal3btherein are formed. In addition, a guide hole25is formed in the resist film22applied onto the lower surface of the mother substrate19. The die-island hole24ais formed so that the vertical (first direction) and horizontal (second direction) sizes of it, when viewed from the top, are smaller than the vertical (first direction) and horizontal (second direction) sizes of the semiconductor chip2when viewed from the top.

As shown inFIG. 13, by etching with the resist film20as a mask, a trench26is formed in the mother substrate19exposed from the bottoms of the die-island hole24aand the electrode-terminal hole24b. The trench has a depth of, for example, about 3 μm.

As shown inFIG. 14, after the surface of the resist film22formed on the lower surface of the mother substrate19is covered with a protecting film27, a gold (Au) film3A is formed (deposited) by electroplating on the bottoms of the die-island hole24aand the electrode-terminal hole24b, each formed on the upper surface of the mother substrate19. The gold (Au) film3A has a thickness of, for example, 0.1 μm. In order to prevent the die island3aor the electrode terminal3bfrom remaining on the side of the mother substrate19when the mother substrate19is peeled from a resin molding7in a mother substrate peeling step P8 which will be conducted later, a film33may be formed, prior to the formation of the gold (Au) film3A, on the bottoms of the die-island hole24aand the electrode-terminal hole24b, each formed on the upper surface of the mother substrate19.

As shown inFIG. 15, a nickel (Ni) film3B is formed (deposited) by electroplating so as to be brought into contact with the gold (Au) film3A in the die-island hole24aand the electrode-terminal hole24b, each formed on the upper surface of the mother substrate19. This nickel (Ni) film3B is formed not only in the die-island hole24aand in the electrode-terminal hole24bbut also spreads over the surface of the resist film20so that it has a mushroom-like shape with an overhang (a canopied site). This nickel (Ni) film3B has a thickness of, for example, about 60 μm.

A concave (recess)8is then formed at the center portion of the upper surface of the nickel (Ni) film3B formed in the die-island hole24a. The depth from the edge of the concave8to the bottom of the concave8is, for example, from 3 μm to 10 μm. Similarly, a concave8having a depth of, for example, from 3 μm to 10 μm is also formed at the center portion of the upper surface of the nickel (Ni) film3B formed in the electrode-terminal hole24b.

As shown inFIG. 16, a silver (Ag) film (or a gold (Au) film)3C is formed (deposited) by electroplating along the surface shape of the nickel (Ni) film3B formed on the upper surface of the mother substrate19and in contact with the surface of the nickel (Ni) film3B. The thickness of the silver (Ag) film (or gold (Au) film)3C is, for example, 3 μm. In the present embodiment, the gold (Au) film3A, the nickel (Ni) film3B, and the silver (Ag) film (or gold (Au) film)3C formed by electroplating are described above, but they may be formed by electroless plating. In consideration of the forming rate (deposition rate) of these platings, electroplating is preferred.

As shown inFIG. 17, after removal of the protecting film27from the surface of the resist film22formed on the lower surface of the mother substrate19, the mother substrate19is etched with the resist film22as a mask, by which an outer frame28of the mother substrate19corresponding to the guide hole25formed in the resist film22is formed.

As shown inFIG. 18, by removing the resist films20and22and removing also an extra portion of the mother substrate19, the mother substrate19having the die island3aand the electrode terminals3bis substantially completed.

The die island3ahas an upper surface not flat but having a concave (recess)8at the center portion of the die island. The depth from the edge of the concave8to the bottom of the concave8is, for example, from 3 μm to 10 μm. Moreover, the vertical (first direction) and horizontal (second direction) sizes of the die island3awhen viewed from the top are smaller than the vertical (first direction) and horizontal (second direction) sizes of the semiconductor chip3when viewed from the top.

Next, as shown inFIG. 19, after the surface of the semiconductor chip2is adsorbed and supported by a cylindrical collet29, the semiconductor chip2is released from the dicing tape and picked up. The semiconductor chip2thus picked up is transported to the die island3aon the upper surface of the mother substrate19.

Next, a conductive resin paste6is added dropwise onto the upper surface of the die island3a. The conductive resin paste6is, for example, a silver (Ag) paste and it has a viscosity of, for example, from 10 Pa·s to 20 Pa·s (5 rpm). Then, the upper surface of the die island3aand the back surface of the semiconductor chip2are faced each other and the semiconductor chip2is placed on the upper surface of the die island3avia the conductive resin paste6. A load is applied to the semiconductor chip2to fix the semiconductor chip2.

Here, the semiconductor chip2is placed on the upper surface of the die island3avia the conductive resin paste6with many grinding grooves16on the back surface of the semiconductor chip2so that the wettability with the conductive resin paste6is improved due to capillary action compared with that when the semiconductor chip2has no grinding groove16on the back surface thereof. As a result, the conductive resin paste6tends to be delivered to the periphery of the semiconductor chip2, particularly, to the corner portions thereof, leading to resolution of the lack of wettability with the conductive resin paste6.

The conductive resin paste6runs along many grinding grooves16on the back surface of the semiconductor chip2and turns around the side surface of the semiconductor chip2. The conductive resin paste6then spreads over the side surface of the semiconductor chip2due to surface tension. As a result, dipping of the conductive resin paste6along the side surface of the die island3acan be prevented.

In addition, the die island3ahas an upper surface not flat but having a concave8which will be a reservoir region of the conductive resin paste6. Due to the collecting force of this concave8, the conductive resin paste6added dropwise to the upper surface of the die island3agathers in the concave8and a portion of the paste overflowing from this concave8is uniformly spilt outside the concave8. Therefore, even if a supply amount of the conductive resin paste6added dropwise to the upper surface of the die island3avaries, the conductive resin paste6spreads uniformly and a spreading range is stable. In addition to the improvement in the wettability with the conductive resin paste6brought by many grinding grooves16on the back surface of the semiconductor chip2, absence of sites along which a large amount of the conductive resin paste6flows further prevents the dripping of the conductive resin paste6to the side surface of the die island3a.

It is possible to increase the viscosity of the conductive resin paste6to suppress spreading of it and thereby prevent the dripping of the conductive resin paste6to the side surface of the die island3a. An increase in the viscosity however disturbs spreading of the conductive resin paste6, which may prevent the uniform formation of the conductive resin paste6on the back surface of the semiconductor chip2and cause adhesion failures between the semiconductor chip2and the die island3a.

Next, as shown inFIG. 20, heat treatment is given to the mother substrate19having the plurality of semiconductor chips2attached thereto. This heat treatment accelerates the curing reaction of the conductive resin paste6to enhance the adhesion between the semiconductor chip2and the die island3a.

Next, as shown inFIG. 21, the plurality of bonding pads4placed at the edges of the surface of the semiconductor chip2and the plurality of electrode terminals3bformed at the periphery of the die islands3aon the upper surface of the mother substrate19are electrically coupled through a plurality of conductive members5, respectively, for example, by nail head bonding (ball bonding), a method using ultrasonic vibration and thermocompression bonding in combination. As the conductive member5, for example, a wire (gold (Au) wire) is used. More specifically, the end of the wire is melted into a ball by arc discharge under surface tension. By using a capillary (a cylindrical coupling jig), the ball is bonded to the upper surface of the bonding pad4and the upper surface of the electrode terminal3bby thermocompression bonding while applying ultrasonic vibration of, for example, 120 kHz.

A forward bonding process (a process of coupling the bonding pad4of the semiconductor chip2and a portion of the wire, followed by coupling the electrode terminal3band the other portion of the wire) is mainly used, but a reverse bonding process (a process of coupling the electrode terminal3band a portion of the wire, followed by coupling the bonding pad4of the semiconductor chip2and the other portion of the wire) may be used instead.

Next, as shown inFIG. 22, one resin molding (molded body)7is formed by setting the mother substrate19having thereon the plurality of semiconductor chips2in a metal molding machine, pouring a sealing resin which has been liquefied by heating into the metal molding machine while applying a pressure, and encapsulating the upper surface side of the mother substrate19with a sealing resin. Then, heat treatment (post cure baking) is conducted, for example, at 175° C. for 5 hours, by which portions (upper surface and side surface) of the plurality of semiconductor chips2, a portion (side surface) of the plurality of die islands3a, portions (upper surface and side surface) of the plurality of electrode terminals3b, and the plurality of conductive members5are enclosed in the resin molding7which covers the upper surface side of the mother substrate19. The resin molding7has a thickness of, for example, 400 μm. The resin molding7is made of an epoxy-based thermosetting insulating resin containing, for example, a phenolic curing agent, a silicone rubber, and many fillers (for example, silica).

Next, as shown inFIG. 23, the mother substrate19is peeled from the resin molding7while folding it. As a result, the other portions (lower surface, back surface, mounting surface) of the plurality of die islands3aand the plurality of electrode terminals3bare exposed from the lower surface (back surface) of the resin molding7.

Next, as shown inFIG. 24, the upper surface of the resin molding7is marked with a product name and the like by using laser30.

Next, as shown inFIG. 25, a dicing sheet31is provided. The dicing sheet31has, on the upper surface thereof, an adhesive layer32. The adhesive layer32is, for example, an acrylic UV-curing type pressure-sensitive adhesive. Next, the resin molding7covering therewith portions (upper surface and side surface) of the plurality of semiconductor chips2, a portion (side surface) of the plurality of die islands3a, portions (upper surface and side surface) of the plurality of electrode terminals3b, and the plurality of conductive members5is fixed to the upper surface of the dicing sheet31with the adhesive layer32.

Next, with an ultrathin disk-shaped cutter (dicing blade) attached with, for example, diamond abrasive grains, the resin molding7is diced vertically (first direction) and horizontally (second direction) from the lower surface side of the resin molding7along a scribe region. At the same time, the adhesive layer32is also diced vertically (first direction) and horizontally (second direction) along the scribe region. The resin molding7is diced into individual semiconductor devices (semiconductor packages)1, but even after individualization, the semiconductor devices1are kept aligned because they are fixed by the dicing sheet31.

Next, the semiconductor device1is cleaned to remove dusts generated during the dicing of the resin molding7and the adhesive layer32.

Next, the dicing sheet31is exposed to ultraviolet rays from the lower surface side of the sheet to reduce the adhesion of the adhesive layer32. This facilitates peeling of each of the semiconductor devices1from the dicing sheet31. This dicing sheet31is made of an UV-permeable material so that it permits permeation of ultraviolet rays.

Next, as shown inFIG. 26, the dicing sheet31is removed to obtain individual semiconductor devices1. From the lower surface of the resin molding7of the semiconductor device1, lower surfaces (back surfaces, mounting surfaces) of each of the die island3aand the plurality of electrode terminals3bare exposed.

<Selecting Step P14 and Visual Inspection Step P15>

Next, from the semiconductor devices thus obtained, those conforming to the product standards are selected and after final visual inspection, finished products (semiconductor devices1) are obtained.

Next, the products (semiconductor devices1) are housed in recesses formed in advance in a carrier tape. Then, the carrier tape is, for example, wound around a reel. The reel is put in a moistureproof bag and the semiconductor devices are shipped in this state.

Thus, according to the present embodiment, the semiconductor chip2is placed on the upper surface of the die island3avia the conductive resin paste6with many grinding grooves16left on the back surface of the semiconductor chip2so that the wettability with the conductive resin paste6is improved, leading to resolution of the lack of wettability.

In addition, the conductive resin paste6runs along many grinding grooves16on the back surface of the semiconductor chip2and the conductive resin paste6turns around the side surface of the semiconductor chip2. The conductive resin paste6then spreads over the side surface of the semiconductor chip2due to surface tension.

Moreover, the concave8serving as a reservoir region of the conductive resin paste6is provided at the center portion of the upper surface of the die island3aso that the conductive resin paste6spreads uniformly and a spreading range of it becomes stable.

The lack of wettability with the conductive resin paste6can therefore be overcome and at the same time, dripping of the conductive resin paste6along the side surface of the die island3acan be prevented.

Such measures prevent easy release of the semiconductor chip2from the die island3aand protrusion of the conductive resin paste6from the lower surface of the resin molding7after running along the side surface of the die island3a, making it possible to suppress deterioration of the reliability of the semiconductor device1.

Modification Example

In the above-mentioned embodiment, the invention is applied to the semiconductor device1having 5 pins of external terminals (1 pin of the die island3aand 4 pins of the electrode terminals3b), but the invention can be applied not only to it.

An application example of the invention to a semiconductor device having 2 pins of external terminals will next be described referring toFIGS. 28 and 29.FIG. 28is a fragmentary plan view showing the back surface (mounting surface) side of a semiconductor device having 2 pins of external terminals (1 pin of a die island and 1 pin of an electrode terminal); andFIG. 29is a fragmentary cross-sectional view of the semiconductor device taken along the line B-B′ ofFIG. 28.

As shown inFIGS. 28 and 29, a semiconductor device (semiconductor package)51having 2 pins of external terminals is comprised of a semiconductor chip52, a die island (first electrode plate)53ahaving thereon the semiconductor chip52and serving as an external terminal, and an electrode terminal (second electrode plate, electrode)53bplaced apart from the die island53aand serving as an external terminal. The back surface of the semiconductor chip52and the upper surface (surface) of the die island53aface each other and the semiconductor chip52is placed on the upper surface of the die island53avia a conductive resin paste56. In addition, a bonding pad (electrode pad, surface electrode)54placed on the surface of the semiconductor chip52and the electrode terminal53bare electrically coupled to each other through a conductive member55.

Moreover, portions (upper surface and side surface) of the semiconductor chip52, a portion (side surface) of the die island53a, portions (upper surface and side surface) of the electrode terminal53b, and the conductive member55are sealed with a resin molding (molded body)57. From the lower surface (back surface) of the resin molding57, however, the other portions (lower surface (back surface, mounting surface)) of the die island53aand the electrode terminal53bare exposed.

Similar to the semiconductor device (semiconductor package)1having 5 pins of external terminals according to the above-mentioned embodiment, the die island53ahas an upper surface not flat but equipped with a concave (recess)58at the center portion thereof. The concave58is a region (reservoir region) where the conductive resin paste56gathers. In addition, the semiconductor chip52is placed on the upper surface of the die island53awith many grinding grooves being left unremoved on the back surface of the semiconductor chip52. Such a structure makes it possible to prevent lack of wettability with the conductive resin paste56and dripping of the conductive resin paste56along the side surface of the die island53a.

The invention made by the present inventors has been described above in detail based on embodiments. It should however be borne in mind that the invention is not limited to or by them but can be modified without departing from the scope of the invention.

The invention can be applied to a semiconductor device in which a semiconductor chip is placed on the upper surface of an external terminal (die island) formed by electroplating via a conductive resin paste while facing the back surface of the semiconductor chip and the upper surface of the external terminal each other.