SIC power DMOSFET with self-aligned source contact

An intermediate product in the fabrication of a MOSFET, including a silicon carbide wafer having a substrate and a drift layer on said substrate, said drift layer having a plurality of source regions formed adjacent an upper surface thereof; a first oxide layer on said upper surface of said drift layer; a plurality of polysilicon gates above said first oxide layer, said plurality of polysilicon gates including a first gate adjacent a first of said source regions; an oxide layer over said first source region of greater thickness than said first oxide layer; and, an oxide layer over said first gate of substantially greater thickness than said oxide layer over said first source region.

BACKGROUND OF THE INVENTION

This invention relates generally to semiconductor field effect transistors, and more particularly to field effect transistors having self-aligned source contacts.

The metal oxide semiconductor field effect transistor (MOSFET) is a device used to amplify or switch electronic signals. Power MOSFETs are well known for their ability to carry large currents in the on-state while withstanding large breakdown voltages in the off-state. In such devices, current flow between source and drain regions in a semiconductor substrate is controlled by a voltage applied to a gate electrode that is separated from the semiconductor surface by an insulator, typically silicon dioxide. In an n-type enhancement MOSFET, for example, a positive bias on the gate causes a surface inversion layer—or channel—to form in a p-type region under the gate oxide and thereby creates a conductive path between source and drain. The application of a positive drain voltage then produces current flow between drain and source. Lateral and vertical power MOSFET structures in silicon have been explored over the years, the former type having the drain, gate and source terminals on the same surface of the silicon wafer, the latter type having the source and drain on opposite surfaces of the wafer. Several different types of vertical power MOSFETs have been proposed, including the double-diffused MOSFET (DMOSFET) and the trench-gate or UMOSFET. These and other power MOSFETs are described in a textbook by B. Jayant Baliga entitled Power Semiconductor Devices, PWS Publishing Co. (1996), the disclosure of, which is hereby incorporated herein by reference.

Although silicon has been the material of choice for many semiconductor applications, its fundamental electronic structure and characteristics prevent its utilization beyond certain parameters. Thus, interest in power MOSFET devices has turned from silicon to other materials, including silicon carbide. SiC power switching devices have significant advantages over silicon devices, including faster switching speed, lower specific on-resistance and thus lower power losses. SiC has a breakdown electric field that is an order of magnitude higher than that of silicon, which allows for a thinner drift region and thus a lower drift region resistance.

In power DMOSFETs, an important performance parameter is the specific on-resistance (RON,SP), which is defined as the product of the resistance when the device is in the “on”, or highly conducting, state (low VDS), times the area of the device (units are Ω-cm2or mΩ-cm2). Thus it is important to minimize both the resistance and the area of the device. For DMOSFETs in the blocking voltage regime of below about 600-1800V, a significant component of the total resistance is the resistance of the source contacts. Larger-area source contacts obviously have lower resistance, but increasing the contact area increases the total area of the device, and hence RON,SP. It is important to find ways to reduce the source contact resistance without increasing the area of the device.

In a conventional DMOSFET, the source contact is defined by photolithography, and the source contact must be separated from the edge of the gate by sufficient distance so that the source contact and gate cannot touch even under worst-case misalignment of the source contact mask. In addition, the actual functional area of the source contact is determined by the overlap of the source contact metal and the N+ implant that forms the source region in the semiconductor. Since the N+ implant is defined by a separate mask, relative misalignment of the source contact mask and the N+ implant mask can reduce the functional area of the source contact, thereby increasing source resistance and degrading performance.

It is desired to produce DMOSFETs and related devices wherein misalignments of source contact and gate are reduced or eliminated.

SUMMARY OF THE INVENTION

The present invention provides high voltage power MOSFETs, with self-aligned source contacts and a method for making the same.

An intermediate product in the fabrication of a MOSFET, including a silicon carbide wafer having a substrate and a drift layer on said substrate, said drift layer having a plurality of source regions formed adjacent an upper surface thereof; a first oxide layer on said upper surface of said drift layer; a plurality of polysilicon gates above said first oxide layer, said plurality of polysilicon gates including a first gate adjacent a first of said source regions; an oxide layer over said first source region of greater thickness than said first oxide layer; and, an oxide layer over said first gate of substantially greater thickness than said oxide layer over said first source region.

These and other aspects and advantages of the present invention will become more apparent upon reading the following detailed description of preferred embodiments in conjunction with the accompanying drawings.

DESCRIPTION OF PREFERRED EMBODIMENTS

For the purpose of promoting an understanding of the principles of the invention, reference will now be made to the embodiments illustrated in the drawings and specific language will be used to describe the same. It will nevertheless be understood that no limitation of the scope of the invention is thereby intended, and that alterations and further modifications in the illustrated device and further applications of the principles of the invention as illustrated therein are contemplated as would normally occur to one skilled in the art to which the invention relates. As shown in the Figures, the sizes of some layers or regions are exaggerated to better illustrate the general structures of the present invention, and actual sizes—often with thicknesses of 50 nm—are either specified or are understood by persons of skill in the art to be other than that shown in the Figures.

It is desired in power DMOSFETs to have a low specific on-resistance (RON,SP), which is defined as the product of the resistance when the device is in the “on”, or highly conducting, state (low VDS), times the area of the device (units are Ω-cm2or mΩ-cm2). It is therefore important to minimize both the resistance and the area of the device. For DMOSFETs with blocking voltage below about 1800V, a significant component of the total resistance is the resistance of the source contacts. While larger-area source contacts obviously have lower resistance, they conversely increase the total area of the device, and hence RON,SP.

Referring toFIG. 1, there is shown one cell region10of a perfectly aligned, conventional DMOSFET11. In DMOSFET11, the source contact13is defined by photolithography, and source contact13must be separated from the edge of the gate14by sufficient distance X so that source contact13and gate14cannot touch even under worst-case misalignment of the source contact mask. In addition, the actual functional area of the source contact is determined by the overlap A of the source contact metal13and the N+ implant15that forms the source region in the semiconductor. Since the N+ implant15is defined by a separate mask, relative misalignment of the source contact mask and the N+ implant mask can reduce the functional area of the source contact, thereby increasing source resistance and degrading performance. A worst-case mask misaligned is shown inFIG. 2where the Ni metal for the source contact13′ has been misaligned to the right and the P+ implant17for the P+ base contact18has been misaligned to the left. The resulting overlap B of Ni metal and N+ implant has been reduced almost to zero, resulting in a very large contact resistance for this part of the device. Another drawback of this approach is the alignment tolerance (spacing X) that must be built into the MOSFET design to ensure that the source metal13never comes into contact with gate14under worst-case misalignment. That is, if the MOSFET design parameters require that source metal13never gets closer to gate14than spacing Y, even under a worst-case mask misalignment (as shown inFIG. 2), then the target mask alignment must be performed with a spacing X. The necessary additional spacing (which is the difference between X and Y) unduly increases the area of the cell, and thus increases RON,SP. Both these problems—increased contact resistance at reduced area overlap B from mask misalignment and increased cell width to ensure adequate spacing Y—are eliminated in the present invention by negating the opportunity for misalignment of source contact metal and gate.

Referring toFIG. 3, there is shown one cell region20of a double-diffused, power metal-oxide-semiconductor field effect transistor (DMOSFET)21in accordance with the present invention. While this and other embodiments presented herein are directed to power DMOSFETs and method for making the same, the present invention is believed to be applicable in varying degrees to other MOSFET designs or similar semiconductor geometry having a source and a gate where it is desirable to place the source and gate as close together as possible and/or to minimize or reduce mask misalignment errors relating to positionment of the gate and source. Such other MOSFETs contemplated by the present invention include, but are not limited to, other vertical MOSFETS, e.g., VMOSFETs and UMOSFETs, as well as lateral DMOSFETs.

DMOSFET21includes a substrate23and a number of semiconductor layers and implants formed on or in the substrate23up through top surface28, collectively referred to as the substrate body22. The fabrication of substrate body22, and variations thereof, can be accomplished in a variety of ways well known in the art and not substantially discussed herein. Substrate23and the layers and implants are formed from silicon-carbide and doped with N-type or P-type impurities as shown inFIG. 3and described herein. In addition to the embodiments described, alternative embodiments are contemplated wherein the compositions and configurations of the layers and implants, of the impurity concentrations, and of the method and timing of impurity doping and implant creation differs from that described herein and is in any manner suitable for the intended MOSFET task. Substrate23is heavily doped with N-type impurities to an “N+” concentration. Formed atop substrate23is drift layer24, which is lightly doped to an “N−” concentration. Atop drift layer24is formed a current spreading epilayer (CSL)25, which is more heavily doped than drift layer24, but not as heavily doped as substrate23. Alternative embodiments are contemplated wherein there is no separately formed CSL layer, and the drift layer24extends all the way to the top SiC surface28. Formed in the top of the current spreading layer25is a P well29. The conductivity types may alternatively be the opposite of those described above. That is, both n-channel and p-channel devices are contemplated as part of the present invention.

It should be understood that the semiconductor device (MOSFET21) ofFIG. 3may be a single “transistor cell” and that a completely fabricated transistor device may include any number of such semiconductor devices or cells. As such, the present description relating to cell region20is with the understanding that the description is applicable to all semiconductor devices that form a larger, fabricated transistor device. For example, the fabricated transistor device may include any number of doped semiconductor wells29depending on the number of semiconductor cell regions20included therein. In addition, the present embodiment is directed to an interdigitated finger array (as shown inFIG. 10and described herein), but alternative embodiments are contemplated wherein the number, alignment and interconnection of cell regions20may be arranged in a hexagonal cellular array, sometimes referred to as a HEXFET.

Formed within P well29are two heavily doped N+ implant source regions31and32on opposing sides of a heavily doped, central implant P+ base33, as shown. N+ implant source regions31and32are heavily doped with N-type impurities to an “N+” concentration, and P+ base33is heavily doped with P-type impurities to an “P+” concentration. N+ implants31and32comprise the two sources of the cell region20of MOSFET21, and P+ base33provides ohmic contact to P well29. The upper surfaces of P+ base33, of N+ implants31and32, of P well29and of CSL epilayer25(or of drift layer24if there is no separate CSL epilayer25) are coplanar and together form the upper surface28of substrate body22.

Referring toFIGS. 3 and 4,FIG. 4is a view of MOSFET21shifted one half cell width laterally from the view ofFIG. 3. Formed atop upper substrate surface28and centered over the left end36of one P well29and the right end37of an immediately adjacent P well29is a polycrystalline silicon (polysilicon) gate38that is surrounded along its top, bottom, left and right sides by an insulating layer of silicon dioxide41. Formed atop P+ base33is a Ti/Al contact metal43, and a Ni contact metal44is formed atop Ti/Al contact metal43. An Ni ohmic contact metal45is formed over the entire MOSFET21, overlapping the polysilicon gate38, but insulated from it by the thick oxide layer41on the top and sides thereof.

Because gate38is completely surrounded by insulating oxide layer41, its positionment relative to source contacts31and32is much less critical, and it cannot detrimentally come in contact with any portion of the Ni metal contact45due to any mask misalignment during processing. Gate38is centered over the JFET region48defined in CSL epilayer25between the facing ends36and37of adjacent P wells29. Ni ohmic contact metal45extends over and contacts with the MOSFET21sources (N+ implants)31and32, as well as Ti/Al and Ni metals43and44, respectively. Once gate38and Ti/Al and Ni metals are formed atop surface28, the deposition of Ni metal contact45over the entire MOSFET21(which is later followed by selective etching to expose and access one portion of commonly connected gates38) makes conformal, direct and self-aligning contact with the Ti/Al and Ni metals43and44and, most importantly, with N-source implants31and32. A Ti/Au layer53is then formed atop Ni metal contact45, and thus over all of Ni metal contact45.

Referring toFIG. 5, MOSFET21is there shown as an intermediate semiconductor product58with all substrate, layers and doping fabricated up through top SiC surface28(which together constitute substrate body22), an oxidation layer59, a 4000 Å thick layer66of polysilicon formed across oxidation layer59, and application of gate mask62atop polysilicon layer66in preparation for etching away a portion of polysilicon layer66to create gates38. The fabrication of intermediate semiconductor product58, as shown inFIG. 5, can be accomplished in a variety of ways well known in the art. In one embodiment, six quarter wafers were processed to produce DMOSFETs in accordance with the present invention, the processing sequence for which is summarized in Appendix I. A detailed run sheet (including materials, temperatures, pressures, times, and chemicals), with slight modifications to the sequence in Appendix I, is provided in Appendix II. The method set forth in Appendix I (through step “m”) and Appendix II (through step15and into step16) represents one method, with some alternative processing steps, for fabricating the intermediate semiconductor product58ofFIG. 5.

These steps to fabricate intermediate semiconductor product58include growing the 50 nm thick silicon lower gate oxide layer59on top of the entire surface28of the SiC substrate body22by thermal oxidation in a pyrogenic oxidation system at 1150° C. for 2.5 hours. This is followed by deposition of a 4000 Å (or alternatively 5000 A, as indicated in Appendix II) layer of polysilicon66atop oxide layer59. Application of gate mask62atop the polysilicon slab66, followed by RIE (Reactive Ion Etch) (Step “m” of Appendix I and step16a(the third a) of Appendix II) removes the polysilicon within the mask outline and down to the gate oxidation layer59, thus creating gates38. Removal of the gate mask reveals the intermediate semiconductor product58ashown inFIG. 6.

The next procedures include applying ohmic contacts to the source and P+ base and taking advantage of the fact that polysilicon forms a much thicker Si02layer than does SiC when thermally oxidized at temperatures in the 850-1000° C. range. The Si02is then removed over the SiC by a short oxide etch, without using a photomask to define the area where the oxide is removed and expose the N+ implants31and32and the P+ base33. Because it is much thicker, the oxide over the polysilicon gate is not completely removed during this process and forms an insulating layer over and around the polysilicon gate38. DMOSFET21may include the use of a segmented P+ contact to the P+ base, as described U.S. Pat. No. 7,498,633, which is hereby incorporated by reference herein, and as already demonstrated experimentally (see, for example, A. Saha and J. A. Cooper, “A 1200V 4H—SiC Power DMOSFET with Ultra-low On-Resistance,” IEEE Transactions on Electron Devices, 54, 2786-2791, October 2007 and A. Saha and J. A. Cooper, “Optimum Design of Short-Channel 4H—SiC Power DMOSFETs,” Materials Science Forum, 527-529, 1269-1272, 2006, both of which are hereby incorporated by reference herein). Because the P+ contact only occurs in certain spots along the length of the source fingers, typically occupying around 10-15% of the finger length, the vast majority of the source fingers have no P+ contact, and the full area is available for use as N+ source contact.

Referring toFIG. 7, after the ion etch creates gates38, an oxidation layer68is grown over the entire upper surface of intermediate semiconductor product58a(Appendix II, step16, the third step “d”: Dry oxidation for 6 hrs. at 1000 C in tube7, then wet oxidation for 4.5 hrs at 950 C and then dry oxidation for 2 hrs at 950 C) to produce intermediate semiconductor product58b. Oxidation layer59grown from the SiC surface28is about 50 nm thick. The foregoing oxidation growing step16dgrows oxidation on the polysilicon gates38about ten times faster or more than on the SiC substrate (on which there is already about a 50 nm oxidation layer59). Consequently, oxidation layer68on top and on the sides of each gate38has grown to about 500 nm thick (at69), while only about 10 nm or less of oxidation are added to upper substrate surface28(at70). It is also noted that formation of the roughly 50 nm lower gate oxidation layer59was conducted at a temperature of about 1150° C. for several hours—a slow oxidation. The later oxidation of both the polysilicon gates38and SiC substrate was conducted at lower temperatures—dry oxidation at 1000° C. for 6 hrs., wet oxidation at 950° C. for 4.5 hrs., and then dry oxidation for 2 hrs. at 950° C. The SiC only grew another 10 nm or less compared to the roughly 500 nm oxide growth on the polysilicon gate38. At this stage then, oxide layer68is about 500 nm thick on the top and sides of gates38, but only about 60 nm thick or less on the SiC substrate therebetween. A short oxide etch is then applied long enough to completely remove the thin oxide layer (comprising previously formed layers59and70) over substrate surface28and between gates38, which exposes N+ and P+ implants31,32and33and thus still leaves a very thick insulating oxide layer69on the top and sides of gates38. The resulting intermediate semiconductor product58cis shown inFIG. 8. Ohmic contact to P well29is then provided by creating Ti/Al and Ni contact metals43and44, respectively, via E-beam evaporation of Ti/Al/Ni (to thicknesses of 100 A/500 A/200 A, respectively) to the now exposed P+ contact33, as shown inFIG. 3.

A thickness of Ni contact metal45is then deposited, without masking, over the entire surface of intermediate semiconductor product58cvia E-beam evaporation, which creates a conformal Ni layer in ohmic contact with N+ source implants31and32and with the just deposited Ti/Al/Ni contact metals43and44. The thick insulating layer of SiO2 electrically insulates polysilicon gates38from Ni contact metal45. Note that the area of the functional source contact is not determined by the alignment of any masking levels and is not subject to random misalignments during processing. Instead, it is totally determined by the spacing between adjacent polysilicon gates and is, in fact, self-aligned to the gate level, being separated by the thickness of the oxide layer covering the gate. This eliminates the alignment tolerance (X or Y inFIGS. 1 and 2), thus reducing the cell area and the specific on-resistance.

Final steps include E-beam evaporation of a 2000 Å Ni metal contact layer75on the backside of the intermediate semiconductor product58, a contact anneal to activate the P- and N-type contacts, and E-beam evaporation of a Ti/Al layer (at thicknesses of 150 Å/7000 Å, respectively) over the entire semiconductor product58, which then constitutes the finished DMOSFET21. The contact anneal forms an alloy between the Ni metal45and N+ source implants31and32and between the Ti/Al metal43and P+ implant, upon which step they become “ohmic”. The Ti/Au metal top layer53provides a lower contact resistance than would the subjacent Ni metal layer.

The primary processing steps described herein are accompanied by numerous secondary steps (such as “RCA clean (right before gate oxidation)” and “DI rinse: 6 times”), all of which are listed recited in Appendix II. Alternative embodiments are contemplated wherein the secondary steps (and even certain of the primary steps) can be performed in ways other than recited, with materials, solutions and concentrations other than recited, and for times and under temperatures and conditions other than recited, so long as the gate and substrate source (or other ohmic contact materials) react to form, create or grow an insulation layer (such as SiO2) sufficiently faster, larger and/or with more insulating capacity at the gate surface than at the substrate surface and that will therefore be uniformly removable at a rate which will remove all such formed, created or grown layer substantially or entirely completely from the substrate surface and leave a sufficiently insulative layer around the gate.

FIG. 9shows the layout of a 10 A DMOSFET having an active area of 0.06 cm2. For this device, a current of 10 A would correspond to a current density of 167 A/cm2. The FET consists of a top half and a bottom half. The bonding pad for the polysilicon gate runs horizontally across the center of the chip, and polysilicon fingers run upward and downward from this pad. Source bonding pads run horizontally along the top and bottom, and Ni source fingers run downward from the top pad and upward from the bottom pad. The source fingers are interdigitated between gate fingers. The active areas between bonding pads are covered with top metal that connects with the source bonding pads (metal not shown). The alignment marks along the periphery of the chip constitute the saw-apart grid, and are destroyed when the die are sawed apart for packaging. The center-to-center spacing between adjacent die is 3.2768 mm.

The gate dielectric described above may be used in conjunction with a short-channel DMOSFET structure, with channel lengths of 0.5 μm or less, such as described in the following paper and patent application, which are hereby incorporated by reference: M. Matin, A. Saha, and J. A. Cooper, Jr., “A Self-Aligned Process for High Voltage, Short-Channel Vertical DMOSFETs in 4H—SiC,” IEEE Transactions on Electron Devices, Vol. 51, No. 10, pp. 1721 1725, October, 2004; and patent application Ser. No. 10/821,613, filed Apr. 9, 2004. These references also disclose examples of doping concentrations and other characteristics suitable for a power DMOSFET according to the present invention.

In addition to or instead of such a short-channel structure, a current spreading layer and/or segmented p+ base contacts may be employed, such as described in U.S. Pat. No. 7,498,633 to Cooper et al., hereby incorporated by reference. The present invention also contemplates various combinations of one or more of such design features with a high-k gate dielectric as disclosed in the U.S. patent application Ser. No. 12/429,153, filed Apr. 23, 2009, entitled Silicon Carbide Power MOSFET With Improved Gate Dielectric, filed in the names of James A. Cooper and Peide Ye.