Transistor structure

A transistor structure is provided in the present invention. The transistor structure includes: a substrate comprising a N-type well, a gate disposed on the N-type well, a spacer disposed on the gate, a first lightly doped region in the substrate below the spacer, a P-type source/drain region disposed in the substrate at two sides of the gate, a silicon cap layer covering the P-type source/drain region and the first lightly doped region and a silicide layer disposed on the silicon cap layer, and covering only a portion of the silicon cap layer.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a method of manufacturing a semiconductor device, and a semiconductor structure thereof for improving short channel effect and drain induced barrier lowering, and more particularly, to a method of manufacturing MOS transistors, and a MOS structure thereof that improves short channel effect and drain induced barrier lowering.

2. Description of the Prior Art

For decades, chip manufacturers have made metal-oxide-semiconductor (MOS) transistors faster by making them smaller. As the semiconductor processes advance to the very deep sub micron era such as 65-nm node or beyond, how to increase the driving current for MOS transistors has become a critical issue.

To attain higher performance of a semiconductor device, attempts have been made to use a strained silicon (Si) layer for increasing the mobility of electrons or holes. For example, taking advantage of the lattice constant of SiGe layer being different from that of Si, a strain occurs in the silicon layer growing on the SiGe layer. Since SiGe has a larger lattice constant than Si, the band structure of Si is altered, thereby increasing the mobility of the carriers.

Other attempts have been made to use germanium embedded in a predetermined source/drain region formed by selective epitaxial growth as a compressive strained silicon film to enhance electron mobility in a PMOS transistor, after a gate is formed. An SiGe layer deposited into the predetermined source/drain region often increases the mobility of electron holes of PMOS, but will simultaneously decrease the electron mobility of an NMOS and reduce the efficiency of the transistor. Therefore, during SiGe layer formation, NMOS is usually covered by a silicon nitride layer serving as a mask. After the SiGe layer is formed, the silicon nitride layer will be removed by hot phosphoric acid. However, the surface of the substrate where the predetermined source/drain region of NMOS is disposed will be corroded by hot phosphoric acid. The interface between the gate dielectric layer and the substrate is taken as a reference. The baseline of corroded substrate becomes lower than the aforesaid interface. Therefore, after the implantation process to form a source/drain region, the p/n junction will become deeper than a predetermined depth. As a result, short channel effect and drain induced barrier lowering (DIBL) effect will occur.

Therefore, there is still a need for a MOS transistor device and a method of manufacturing the same to improve problems mentioned above.

SUMMARY OF THE INVENTION

It is therefore an objective of the present invention to provide a method of fabricating MOS transistors to solve the lowering of the baseline where the predetermined source/drain region of NMOS is disposed after removing a mask.

According to a preferred embodiment of the present invention, a method of fabricating method of fabricating transistors comprises the following steps. First, a substrate comprising a first type well and a second type well is provided. Then, a first gate on the first type well and a second gate on the second type well are formed respectively. After that, a third spacer is formed on the first gate. Later, an epitaxial layer is formed in the substrate at two sides of the first gate. Next, a fourth spacer is formed on the second gate. Subsequently, a silicon cap layer is formed to cover the epitaxial layer, and the surface of the substrate at two sides of the second gate. Then, a first source/drain region is formed in the substrate at two sides of the first gate. Finally, a second source/drain region is formed in the substrate at two sides of the second gate.

According to another preferred embodiment of the present invention, a transistor structure A semiconductor structure, comprising: a substrate comprising a N-type well, a first gate disposed on the N-type well, a first spacer disposed on the gate, a first lightly doped region in the substrate below the spacer, an P-type source/drain region disposed in the substrate at two sides of the first gate, a first silicon cap layer covering the P-type source/drain region and the first lightly doped region and a silicide layer disposed on the first silicon cap layer, and covering only a portion of the first silicon cap layer.

The feature of the present invention is that, after forming the epitaxial layer, a silicon cap layer is formed at two sides of the gate of NMOS and PMOS respectively. In other words, the silicon cap layer is formed on the surface of the source/drain region of the NMOS and PMOS. The silicon cap layer can level up the baseline of the source/drain region of the NMOS after the mask is removed. In this way, the short channel effect and the drain induced barrier lowering effect can be prevented because the depth of the p/n junction is maintained at a predetermined depth. Furthermore, the epitaxial layer will become a spacer of the NMOS after the epitaxial layer is formed.

DETAILED DESCRIPTION

FIG. 1throughFIG. 9are schematic cross-section view diagrams showing the means of fabricating transistors according to the present invention.

As shown inFIG. 1, first, a substrate10comprising a first type well12and a second type well14are provided. The substrate10also includes a top surface11. The first type well12may be an N type or P type, and the second type well14may be a P type or N type. The following illustration will take the first type well12as an N type well, and the second type well14as a P type well. In other words, a PMOS will be formed on the first type well12and a NMOS will be formed on the second type well14. In addition, a shallow trench isolation (STI)15is disposed between the first type well12and the second type well14, and around the first type well12and the second type well14within the substrate10.

Next, a first gate16and a second gate18are formed on the first type well12and the second type well14, respectively. The first gate16includes a first dielectric layer20positioned on the substrate10and a first conductive layer22positioned on the first dielectric layer20. The second gate18includes a second dielectric layer28positioned on the substrate10, a second conductive layer30positioned on the second dielectric layer28. After the first gate16and the second gate18are formed, a first cap layer24and the second cap layer32are formed on the first conductive layer22, and on the second conductive layer30. Then, a first spacer26is formed on the sidewalls of the first dielectric layer20, the first conductive layer22and the first cap layer24, and a second spacer34is formed on the sidewalls of the second dielectric layer28, the second conductive layer30and the second cap layer32. Generally, the first dielectric layer20and the second dielectric layer28are composed of silicon dioxide, or a material with a high dielectric constant that is greater than 4. The first conductive layer22and the second conductive layer30are composed of doped polysilicon, or a metal with specific work function. The first cap layer24and the second cap layer32are composed of silicon nitride. The first cap layer24and the second cap layer32can be formed optionally. The first spacer26and the second spacer34are masks for forming lightly doped regions of the drain/source regions later. After the lightly doped regions are formed, the spacers may be kept in the structure or removed. Next, the first gate16and first spacer26are taken as a mask to form a first lightly doped region36in the substrate10at two sides of the first gate16. After the formation of the first lightly doped region36, a first distance D1which is the shortest distance between first lightly doped region36and the first gate16is defined. According to a preferred embodiment of the present invention, the first distance D1is zero. Therefore, the first distance D1is shown as a dot inFIG. 1.

After that, as shown inFIG. 2, a mask layer40is formed to cover the first type well12, the second type well14, the first gate16, the first spacer26, the second gate18and the second spacer34conformally. Then, a third spacer38is formed around the first spacer26by removing the mask layer40partly, and the remaining mask layer40covers the second type well14, the second gate18, the second spacer34and the second cap layer32. The detailed method of forming the third spacer38and the mask layer40may includes the following steps. First, a silicon nitride layer is formed to cover the first type well12, the second type well14, the first gate16, and the second gate18. Then, a patterned photoresist (not shown) is formed to cover the second type well14and the second gate18. After that, the silicon nitride layer not covered by the patterned photoresist is removed by an etching process to form the third spacer38. Finally, as shown inFIG. 3, the patterned photoresist is removed. The silicon nitride layer originally covered by the patterned photoresist becomes the mask layer40.

Please still refer toFIG. 3. Next, an epitaxial layer42is formed in the substrate10at two sides of the first gate16. According to a preferred embodiment of the present invention, the epitaxial layer42includes only a SiGe epitaxial layer44. According to another preferred embodiment of the present invention, the epitaxial layer42includes both a SiGe epitaxial layer44and a silicon cap layer46formed on the SiGe epitaxial layer44, as shown inFIG. 3. The silicon cap layer46may be single crystalline silicon. In the following description, the epitaxial layer42will be shown as including both the SiGe epitaxial layer44and the silicon cap layer46. Preferably, the SiGe epitaxial layer44can be formed by an embedded Silicon Germanium (e-SiGe) process. For example, the mask layer40, the first gate16, the first spacer26, the first cap layer24and the third spacer38are taken as a mask to form two recesses at two sides of the third spacer38by an etching process. After that, silicon-containing gas and germanium-containing gas flow into the chamber and the SiGe epitaxial layer44grows in the two recesses. According to another preferred embodiment, the germanium-containing gas is turned off when the SiGe epitaxial layer44reaches a predetermined height. Then, the silicon cap layer46consisting of the single crystalline silicon can be formed on the SiGe epitaxial layer44. The thickness of the silicon cap layer46can be adjusted according to product design, and the silicon cap layer46can even be omitted according to different requirements. Additionally, the concentration of germanium in the SiGe epitaxial layer44can be controlled to form a gradient in the SiGe epitaxial layer44.

As shown inFIG. 4, after the embedded Silicon Germanium (e-SiGe) process is finished, a patterned photoresist (not shown) is formed to cover the first type well12, the first gate16and the third spacer38. Then, the mask layer40is etched partly to form a fourth spacer48around the second spacer34. Next, the patterned photoresist is removed. According to another preferred embodiment of forming the fourth spacer48, the method includes the following steps. First, the third spacer38and the mask layer40are removed completely. Next, as shown inFIG. 5, a material layer50is covered on the second type well14, the first type well12, the first gate16, the first spacer26, the second gate18and the second spacer34conformally. As shown inFIG. 6, a part of the material layer50is removed to form a seventh spacer52and the fourth spacer48. The process of forming spacers only demonstrates the preferred embodiment of the present invention. Other modifications and alterations may be made by those skilled in the technology without departing from the spirit of the invention.

The following processes continue on from the process inFIG. 4, i.e. in the following, the processes shown inFIG. 5andFIG. 6have not been performed.

As shown inFIG. 7, a silicon cap layer54and a silicon cap layer53are formed on the surface of the silicon cap layer46and the surface of the substrate10at two sides of the second gate18, respectively. More specifically, the silicon cap layer54is formed on the predetermined source/drain region in the first type well12. The silicon cap layer53is formed on the predetermined source/drain region in the second type well14. The silicon cap layer54can be single crystalline silicon. At this point, a second distance D2which is the shortest distance between the silicon cap layer54and the first gate16is defined. The silicon cap layers53/54can be formed by using the same method as that used by the epitaxial layer42. The silicon cap layers53/54can even be formed by putting the substrate10into the same chamber as used by the epitaxial layer42, and turning on the silicon-containing gas again to form the silicon cap layers53/54. According to a preferred embodiment of the present invention, the thickness of the silicon cap layer53and the thickness of the silicon cap layer54can both be range from 50 to 150 angstroms. In addition, since the silicon cap layer54is formed on the silicon cap layer46, the total thickness of the silicon cap layer46plus the silicon cap layer54is greater than the silicon cap layer53. In other words, the thickness of the double silicon cap layers (silicon cap layer46plus silicon cap layer54) on the SiGe epitaxial layer44is greater than the thickness of the single silicon cap layer53on the second type well14. As shown inFIG. 7, it is note worthy that the first distance D1is shorter than the second distance D2.

As shown inFIG. 8, a patterned photoresist (not shown) covers the first type well12. The patterned photoresist, the second spacer34, the fourth spacer48and the second gate18are taken as masks to perform an implantation process. After the implantation process, a second lightly doped region56is formed in the substrate10at two sides of the second gate18. More specifically, because the second spacer34is taken as the mask to form the second lightly doped region56, the second lightly doped region56will form in the substrate10which does not overlap with the second spacer34. Now, a third distance D3which is the shortest distance between the second lightly doped region56and the second gate18is defined. Please still referFIG. 8, the first distance D1is shorter than the third distance D3. Then, a fifth spacer58and a sixth spacer60are formed on the sidewalls of the third spacer38and the fourth spacer48, respectively. After that, the first cap layer24and the second cap layer32are removed to expose the first conductive layer22and the second conductive layer30. Subsequently, a P-typed first source/drain region62is formed in the substrate10at two sides of the first gate16, and an N-typed second source/drain region64is formed in the substrate10at two sides of the second gate18. At this point, the PMOS66and NMOS68of the present invention are completed. The fabricating sequence of the first source/drain region62and the second type source/drain region64can be exchanged. Additionally, the first source/drain region62may only partly overlap with the epitaxial layer42.

As show inFIG. 9, a salicide process is performed to transform at least part of the exposed first conductive layer22, part of the exposed second conductive layer30, and part of the silicon cap layers53/54to become silicide layers55. One may notice that the top surface57of the silicide layer55is more elevated than the top surface11of the substrate10. After that, other fabricating processes such as forming a contact etch stop layer (CESL), a dual stress liner (DSL), or other stress memorization technology (SMT) can also be applied to the present invention to increase the performance of the MOS. Then, an inter circuit process can be performed on the PMOS and NMOS: for example, forming an inter layer dielectric covering the PMOS66and NMOS68. Next, contact plugs can be formed in the inter layer dielectric to contact the first gate16, the second gate18, the first source/drain doped region62and the second source/drain doped region64. In addition, the present invention can also be applied to the embedded silicon carbon (e-SiC) to improve the performance of the NMOS. For example, when performing the process shown inFIG. 2, the SiGe epitaxial layer is replaced with a SiC epitaxial layer.

In the process mentioned above, at least part of the mask layer40will be removed after the epitaxial layer42is formed. After removing part of the mask layer40, the top surface11of the substrate10at two sides of the second gate18is also etched. Therefore, by taking the interface of the second dielectric layer28and the top surface11of the substrate10as reference, the baseline of the top surface11of the substrate10at two sides of the second gate18is leveled down. The feature of the present invention is that the silicon cap layer54is formed on the two sides of the first gate16and the silicon cap layer53is formed at two sides of the second gate18. In other words, the silicon cap layers53/54are formed on the source/drain doped regions of the PMOS66and NMOS68, respectively. For the NMOS68, the silicon cap layer53can refill the region of the substrate10that is etched along with the mask layer40. In other words, the baseline of the substrate10at two sides of the second gate18is leveled up. The short channel effect and drain induced barrier lowering effect can be prevented because the p/n junction is maintained at a predetermined depth. For the PMOS66, the silicon cap layer54is primarily for the formation of the silicide layer55. In addition, after the epitaxial layer42is formed, the mask layer40can be used as a spacer of the NMOS68.

FIG. 10shows a schematic cross-section view diagram of a transistor structure for improving short channel effect and drain induced barrier lowering according to the present invention.

As shown inFIG. 10, the NMOS168of the present invention includes: a substrate100comprising a P-type well114, a gate118disposed on the P-type well114, a spacer150disposed on the gate118, a lightly doped region156disposed in the substrate100below the spacer150, an N-type source/drain region164disposed in the substrate100at two sides of the gate118, a silicon cap layer154covering the N-type source/drain region164and a silicide layer155disposed on the silicon cap layer154. The gate118includes a dielectric layer128positioned on the substrate100and a conductive layer130positioned on the dielectric layer128. In addition, the spacer150is a composite and the spacer150includes spacers134/148/160positioned on the sidewall of the gate118. Furthermore, the thickness of the silicon cap layer154is 50 to 150 angstroms, and the silicon cap layer154consists of single crystalline silicon. Moreover, the surface of the silicide layer155is more elevated than the interface between the dielectric layer128and the substrate100.

As a result, the feature of the present invention is that a silicon cap layer154is at the source/drain region164of the NMOS168. Therefore, the short channel effect and drain induced barrier lowering effect can be improved.