Method of fabricating semiconductor device

A method of fabricating a semiconductor device, in which an interference effect between word lines is substantially reduced or eliminated, includes forming a plurality of gate patterns on a substrate; forming a first insulating layer between the gate patterns, the first insulating layer filling a region between the gate patterns; etching the first insulating layer to remove a portion of the first insulating layer to a predetermined depth; and forming a second insulating layer on the gate patterns and the first insulating layer. A low-dielectric-constant material is formed between the gate patterns.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims the benefit of Korean Patent Application No. 10-2010-0060660 filed on Jun. 25, 2010 in the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference.

BACKGROUND

The inventive concept relates to a method of fabricating a semiconductor device, and more particularly, to a method of fabricating a semiconductor device by which an interference effect between word lines is substantially reduced or eliminated.

As semiconductor devices have become increasingly highly integrated, a width of an insulation layer decreases. As a result, a distance or interval between adjacent word lines and a distance or interval between adjacent floating gates also decrease. As a result, an interference effect occurs between the word lines and the floating gates, deepening a cell threshold voltage (Vth) shift and thus degrading the reliability of the semiconductor device.

SUMMARY

The inventive concept provides a method of fabricating a semiconductor device, by which an interference effect between word lines is substantially reduced or eliminated.

According to an aspect of the inventive concept, there is provided a method of fabricating a semiconductor device, the method including forming a plurality of gate patterns on a substrate, forming a first insulating layer between the gate patterns, the first insulating layer filing a region between the gate patterns, etching the first insulating layer to remove a portion of the first insulating layer to a predetermined depth, and forming a second insulating layer on the gate patterns and the first insulating layer, in which a low-dielectric-constant material is formed between the gate patterns.

In some exemplary embodiments, the low-dielectric-constant material may be air in an air gap. The air gap may be formed during the forming of the second insulating layer, and the air gap may directly contact the second insulating layer.

In some exemplary embodiments, the low-dielectric-constant material may include a material selected from the group consisting of air, hydrogen silsesquioxane (HSQ), methyl silsesquioxane (MSQ), amorphous floro-carbon (a-C:F), SiOF, SiOC, porous SiO2, and a combination thereof.

In some exemplary embodiments, each of the gate patterns may include at least a first conductive layer pattern and a second conductive layer pattern on the first conductive layer pattern, and the air gap may be formed between adjacent second conductive layer patterns of adjacent gate patterns.

In some exemplary embodiments, the air gap may be further formed between adjacent first conductive layer patterns of adjacent gate patterns.

In some exemplary embodiments, portions of the first insulating layer formed at sidewalls of the first conductive layer pattern may be spaced apart by a first distance defined by the air gap, and the method may further include etching the first insulating layer such that the portions of the first insulating layer formed at the sidewalls of the first conductive layer pattern are spaced apart by a second distance larger than the first distance.

In some exemplary embodiments, the air gap may directly contact the first conductive layer pattern.

In some exemplary embodiments, the method may further include, between the etching of the first insulating layer and the forming of the second insulating layer, forming a third insulating layer on sidewalls of the second conductive layer pattern and the first insulating layer and sequentially etching the third insulating layer and the first insulating layer.

In some exemplary embodiments, the method may further include, after the sequential etching of the third insulating layer and the first insulating layer, forming a fourth insulating layer on the first insulating layer and the sidewalls of the second conductive layer pattern, and sequentially etching the fourth insulating layer and the first insulating layer.

In some exemplary embodiments, the third insulating layer may have an etching selectivity with respect to the first insulating layer, the third insulating layer may include a center portion and a spacer positioned at both sides of the center portion, and the sequential etching of the third insulating layer and the first insulating layer may include etching the center portion of the third insulating layer and etching the first insulating layer using the spacer as a mask.

In some exemplary embodiments, the forming of the gate patterns may include sequentially forming a first conductive layer and a second conductive layer on the substrate, and forming the first conductive layer pattern and the second conductive layer pattern by patterning the second conductive layer and the first conductive layer.

In some exemplary embodiments, the method may further include forming a blocking insulating layer between the first conductive layer and the second conductive layer, in which the gate patterns are formed by patterning the second conductive layer, the blocking insulating layer, and the first conductive layer.

In some exemplary embodiments, the second conductive layer may be formed by depositing a plurality of layers made of a material selected from the group consisting of a polysilicon layer, a metal layer, a nitride of the metal layer, a silicide of the metal layer, and a combination thereof.

In some exemplary embodiments, the second insulating layer may have a low step coverage.

According to another aspect of the inventive concept, there is provided a method of fabricating a semiconductor device, the method including forming a plurality of gate patterns in a cell region and a peripheral region of a substrate, each of the gate patterns including at least a first conductive layer pattern and a second conductive layer pattern on the first conductive layer pattern, forming a first insulating layer between the gate patterns, the first insulating layer filling a region between the gate patterns, forming a mask layer on the gate patterns and the first insulating layer, removing a portion of the mask layer to pattern the mask layer, the portion of the mask layer being positioned on the first insulating layer formed in the cell region, etching the first insulating layer to remove a portion of the first insulating layer exposed by the mask layer, the portion of the first insulation layer being removed to a predetermined depth, and forming a second insulating layer on the gate patterns and the first insulating layer, in which a low-dielectric-constant material is formed between the second insulating layer and the first insulating layer.

In some exemplary embodiments, the low-dielectric-constant material may include a material selected from the group consisting of air in an air gap, hydrogen silsesquioxane (HSQ), methyl silsesquioxane (MSQ), amorphous floro-carbon (a-C:F), SiOF, SiOC, porous SiO2, and a combination thereof.

In some exemplary embodiments, forming the mask layer may include forming a negative photoresist layer on the gate patterns and the first insulating layer.

In some exemplary embodiments, during the etching of the first insulating layer, a portion of the first insulating layer in the peripheral region may not be etched due to a portion of the mask layer formed in the peripheral region.

According to another aspect of the inventive concept, there is provided a method of fabricating a semiconductor device, the method including forming a plurality of gate patterns in a cell region and a peripheral region of a substrate, each of the gate patterns including at least a first conductive layer pattern and a second conductive layer pattern on the first conductive layer pattern, forming a first insulating layer which fills a region between the gate patterns, etching the first insulating layer to a predetermined depth, forming a third insulating layer at sidewalls of the second conductive layer pattern and the first insulating layer, sequentially etching the third insulating layer and the first insulating layer, and forming a second insulating layer on the gate patterns and the first insulating layer, in which an air gap is formed between the second insulating layer and the first insulating layer.

In some exemplary embodiments, the third insulating layer may have an etching selectivity to the first insulating layer, the third insulating layer may include a center portion and a spacer positioned at both sides of the center portion, and the sequential etching of the third insulating layer and the first insulating layer may include etching the center portion of the third insulating layer and etching the first insulating layer using the spacer as a mask.

According to another aspect of the inventive concept, there is provided a method of fabricating a semiconductor device, the method comprising: forming a plurality of gate patterns on a substrate, each gate pattern comprising at least a first conductive layer pattern and a second conductive layer pattern on the first conductive layer pattern; forming a first insulating layer filling a region between the gate patterns; etching the first insulating layer to a predetermined depth; forming a second insulating layer on the first insulating layer and sidewalls of the second conductive layer pattern, wherein the second insulating layer has an etching selectivity with respect to the first insulating layer, the second insulating layer comprising a center portion and a spacer positioned at both sides of the center portion; sequentially etching the second insulating layer and the first insulating layer; forming a third insulating layer on the gate patterns and the first insulating layer, wherein a low-dielectric-constant material is formed between adjacent second conductive layer patterns of adjacent gate patterns.

In some exemplary embodiments, the sequential etching of the second insulating layer and the first insulating layer comprises: etching the center portion of the second insulating layer; and etching the first insulating layer using the spacer as a mask.

In some exemplary embodiments, the low-dielectric-constant material comprises a material selected from the group consisting of air, hydrogen silsesquioxane (HSQ), methyl silsesquioxane (MSQ), amorphous floro-carbon (a-C:F), SiOF, SiOC, porous SiO2, and a combination thereof.

In some exemplary embodiments, the second conductive layer is formed by depositing a plurality of layers made of a material selected from the group consisting of a polysilicon layer, a metal layer, a nitride of the metal layer, a silicide of the metal layer, and a combination thereof.

In some exemplary embodiments, the semiconductor device comprises a semiconductor memory device.

In some exemplary embodiments, the semiconductor device comprises a controller for controlling a semiconductor memory device.

DETAILED DESCRIPTION OF THE EMBODIMENTS

Hereinafter, exemplary embodiments of the inventive concept will be described with reference to the accompanying drawings.

The terms used herein are for purposes of illustrating and describing the inventive concept only and should not be construed to limit the meaning or the scope of the inventive concept. As used in this specification, a singular form may, unless indicating a particular case in terms of the context, include a plural form. Also, the expressions “comprise” and/or “comprising” used in this specification neither define the mentioned shapes, numbers, steps, operations, members, elements, and/or groups of these, nor exclude the presence or addition of one or more other different shapes, numbers, steps, operations, members, elements, and/or groups of these, or addition of these. The term “and/or” used herein includes any and all combinations of one or more of the associated listed items.

As used herein, terms such as “first,” “second,” etc. are used to describe various members, components, regions, layers, and/or portions. However, it is obvious that the members, components, regions, layers, and/or portions should not be defined by these terms. The terms do not mean a particular order, up and down, or superiority, and are used only for distinguishing one member, component, region, layer, or portion from another member, component, region, layer, or portion. Thus, a first member, component, region, layer, or portion which will be described may also refer to a second member, component, region, layer, or portion, without departing from the scope of the inventive concept.

Hereinafter, exemplary embodiments of the inventive concept will be described with reference to the attached drawings which schematically illustrate the embodiments of the inventive concept. In the drawings, for example, according to the manufacturing technology and/or tolerance, variations from the illustrated shape may be expected. Thus, the exemplary embodiments of the inventive concept must not be interpreted to be limited by a particular shape that is illustrated in the drawings and must include a change in the shape occurring, for example, during manufacturing.

FIGS. 1 through 4are schematic cross-sectional views illustrating a method of fabricating a semiconductor device according to some exemplary embodiments of the inventive concept.

Referring toFIG. 1, in some exemplary embodiments, a tunneling insulating layer105is formed on a substrate100. The substrate100may be a semiconductor substrate, and may include, for example, one of silicon, a silicon-on-insulator, silicon-on-sapphire, germanium, silicon-germanium, and gallium-arsenide. In some exemplary embodiments, the tunneling insulating layer105may be formed by depositing a plurality of layers, each made of a material selected from the group consisting of silicon oxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiON), hafnium oxide (HfO2), hafnium silicon oxide (HfSixOy), aluminum oxide (Al2O3), zirconium oxide (ZrO2), and a combination thereof.

Thereafter, in some exemplary embodiments, a plurality of gate patterns130is formed on the tunneling insulating layer105. In some exemplary embodiments, each of the gate patterns130may include a first conductive layer pattern110, a blocking insulating layer115, a second conductive layer pattern120, and a capping insulating layer125, formed in a stacked configuration as illustrated inFIG. 1.

In some exemplary embodiments, the first conductive layer pattern110may include polysilicon doped with impurities. More specifically, in these exemplary embodiments, polysilicon may be deposited on the tunneling insulating layer105by, for example, chemical vapor deposition (CVD), e.g., low-pressure CVD (LPCVD) using SiH4or Si2H6and PH3gas, and is doped with impurities, thus forming the first conductive layer pattern110.

In some exemplary embodiments, the blocking insulating layer115may be structured such that a lower dielectric layer, a high-dielectric-constant layer, and an upper dielectric layer are sequentially formed on the first conductive layer pattern110. For example, the lower dielectric layer and the upper dielectric layer may include silicon oxide layers. When the lower dielectric layer and the upper dielectric layer are silicon oxide layers, they may have the same material and internal structure as each other, and each may be a single layer including one or more of SiO2, carbon-doped SiO2, fluorine-doped SiO2, or porous SiO2. In some exemplary embodiments, the silicon oxide layers may be, for example, high temperature oxide (HTO) layers formed by high-temperature oxidation using SiH2Cl2and H2O gases having superior pressure-resistance and time dependent dielectric breakdown (TDDB) characteristics as source gases. However, this is merely an illustrative example, and the inventive concept is not limited to this example.

In some exemplary embodiments, the high-dielectric-constant layer may be or may include a silicon nitride layer or a metal oxide layer having a higher dielectric constant than that of the silicon nitride layer. The metal oxide layer may be formed, for example, by depositing a plurality of layers made of a material selected from the group consisting of aluminum oxide (Al2O3), tantalum oxide (Ta2O3), titanium oxide (TiO2), yttrium oxide (Y2O3), zirconium oxide (ZrO2), zirconium silicon oxide (ZrSixOy), hafnium oxide (HfO2), hafnium silicon oxide (HfSixOy), lanthanum oxide (La2O3), lanthanum aluminum oxide (LaAlO), lanthanum hafnium oxide (LaHfO), hafnium aluminum oxide (HfAlO), praseodymium oxide (Pr2O3), and/or a combination thereof

In some exemplary embodiments, the second conductive layer pattern120may include at least one of impurity-doped polysilicon, metal, metal nitride, metal silicide, and a combination thereof. More specifically, in some exemplary embodiments, the second conductive layer pattern120may be formed by depositing a plurality of layers made of a material selected from the group consisting of a polysilicon layer, a metal layer composed of aluminum (Al), gold (Au), beryllium (Be), bismuth (Bi), cobalt (Co), hafnium (Hf), indium (In), manganese (Mn), molybdenum (Mo), nickel (Ni), lead (Pb), palladium (Pd), platinum (Pt), rhodium (Rh), rhenium (Re), ruthenium (Ru), tantalum (Te), titanium (Ti), tungsten (W), zinc (Zn), or zirconium (Zr), a nitride thereof, a silicide thereof, and a combination thereof. However, layered structure and material of the second conductive layer pattern120are merely examples and the inventive concept is not limited to these examples.

In some exemplary embodiments, a first insulating layer140is formed between the gate patterns130. The first insulating layer140may be formed of a material having an etching selectivity with respect to the capping insulating layer125. For example, the capping insulating layer125may be made of silicon nitride, and the first insulating layer140may be made of silicon oxide having an etching selectivity with respect to the capping insulating layer125.

Referring toFIG. 2, in some exemplary embodiments, the first insulating layer140is etched between gate patterns130to a predetermined depth d1defined perpendicular to the substrate100. A recess etched to the predetermined depth d1may be positioned at a depth that is within the second conductive layer pattern120. That is, in some exemplary embodiments, the predetermined depth d1may be smaller than a thickness of the second conductive layer pattern120. More specifically, in each gate pattern130including the capping insulating layer125and the second conductive layer pattern120, the predetermined depth d1may be smaller than a sum of a thickness of the capping insulating layer125and the thickness of the second conductive layer pattern120. Thus, an air gap (160ofFIG. 3) may be formed between adjacent second conductive layer patterns120.

Referring toFIG. 3, a second insulating layer150is formed on the gate patterns130and the first insulating layer140. In this case, the air gap160may be formed or captured between the first insulating layer140and the second insulating layer150. In some exemplary embodiments, to form the air gap160smoothly by means of deposition of the second insulating layer150, the second insulating layer150may be formed of a material having a low step coverage. In some exemplary embodiments, the material may be, for example, tetra ortho silicate glass (O3-TEOS) or undoped silicate glass (USG). The deposition speed of the second insulating layer150and bias power and direction may be adjusted so that the second insulating layer150may have a low step coverage.

In some exemplary embodiments, a low-dielectric-constant material, instead of the air gap160, may be formed between the first insulating layer140and the second insulating layer150. In this case, the low-dielectric-constant material may be formed on the first insulating layer140, and the second insulating layer150may be formed on the low-dielectric-constant material. The low-dielectric-constant material may be or may include a material selected from the group consisting of the air gap160, hydrogen silsesquioxane (HSQ), methyl silsesquioxane (MSQ), amorphous floro-carbon (a-C:F), SiOF, SiOC, porous SiO2, and a combination thereof.

Referring toFIG. 4, in some exemplary embodiments, planarization is performed on the second insulating layer150. The planarization may be performed using a chemical mechanical polishing (CMP) process, an etch-back process, or a combination of the CMP process and the etch-back process.

FIGS. 5 and 6are schematic cross-sectional views illustrating a method of fabricating a semiconductor device according to some exemplary embodiments of the inventive concept. The method shown inFIGS. 5 and 6is a partial modification of the method shown inFIGS. 1 through 4. Detailed description of like features and elements will not be repeated.

Referring toFIG. 5, in these exemplary embodiments, the first insulating layer140is etched to a predetermined depth d2defined perpendicular to the substrate100. A recess etched to the predetermined depth d2may be positioned under the second conductive layer pattern120and on the first conductive layer pattern110. That is, the predetermined depth d2may be larger than the thickness of the second conductive layer pattern120and smaller than a sum of the thickness of the second conductive layer pattern120and the thickness of the first conductive layer pattern110. More specifically, in these exemplary embodiments, in each gate pattern130including the capping insulating layer125and the second conductive layer pattern120, the predetermined depth d2may be larger than a sum of the thickness of the capping insulating layer125and the thickness of the second conductive layer pattern120. The predetermined depth d2may be smaller than a sum of the thickness of the capping insulating layer125, the thickness of the second conductive layer pattern120, and the thickness of the first conductive layer pattern110.

Referring toFIG. 6, the second insulating layer150is formed on the gate patterns130and the first insulating layer140, and is then planarized. Thus, the air gap160may be formed between adjacent second conductive layer patterns120and adjacent first conductive layer patterns110.

FIGS. 7 through 12are schematic cross-sectional views illustrating a method of fabricating a semiconductor device according to some exemplary embodiments of the inventive concept. The method shown inFIGS. 7 through 12is a partial modification of the method shown inFIGS. 1 through 4. Detailed description of like features and elements will not be repeated.

Referring toFIG. 7, the first insulating layer140is etched to a predetermined depth defined perpendicular to the substrate100. In these exemplary embodiments, the predetermined depth may be smaller than the thickness of the second conductive layer pattern120. As previously described, in each gate pattern130including the capping insulating layer125and the second conductive layer pattern120, the predetermined depth may be smaller than the sum of the thickness of the capping insulating layer125and the thickness of the second conductive layer pattern120. By etching the first insulating layer140, sidewalls of the capping insulating layer125and the second conductive layer pattern120may be exposed.

Referring toFIGS. 8 and 9, a third insulating layer142is formed on the first insulating layer140. The third insulating layer142may be formed of a material having a superior step coverage. The material of the third insulating layer142may have the same etching selectivity as that of the first insulating layer140. In some exemplary embodiments, the material may be, for example, a furnace-deposited oxide layer such as a HTO layer. By depositing the third insulating layer142having a superior step coverage, the third insulating layer142may be formed on the sidewalls of the second conductive layer pattern120and the sidewalls and top surface of the capping insulating layer125. Thereafter, the third insulating layer142and the first insulating layer140are sequentially etched. As a result, a recess deeper than the recess formed to the predetermined depth by the previous etching may be formed, and damage of the second conductive layer pattern120may be prevented by the third insulating layer142during etching.

Referring toFIGS. 10 and 11, in some exemplary embodiments, to form a recess deeper than the recess formed by the etching shown inFIGS. 8 and 9, an additional etching process may be performed. The additional etching process is similar to the etching performed inFIGS. 8 and 9. That is, a fourth insulating layer144having a superior step coverage is formed on the first insulating layer140, the sidewall of the second conductive layer pattern120, and the sidewall of the capping insulating layer125, and the fourth insulating layer144and the first insulating layer140are sequentially etched.

Referring toFIG. 12, the second insulating layer150is formed on the gate patterns130and the first insulating layer140, and then is planarized. Thus, the air gap160may be formed between adjacent second conductive layer patterns120and between adjacent first conductive layer patterns110, and the air gap160may directly contact the second conductive layer pattern120.

FIGS. 13 through 15are schematic cross-sectional views illustrating a method of fabricating a semiconductor device according to some exemplary embodiments of the inventive concept. The method shown inFIGS. 13 through 15is a partial modification of the method shown inFIGS. 7 through 12. Detailed description of like features and elements will not be repeated.

Referring toFIG. 13, the first insulating layer140is etched to a predetermined depth as shown inFIG. 7. As mentioned above, by etching the first insulating layer140, the sidewalls of the capping insulating layer125and the second conductive layer pattern120may be exposed.

Referring toFIG. 14, the capping insulating layer125may be removed and silicidation is performed on the exposed second conductive layer pattern120. For example, in some exemplary embodiments, for the silicidation, the second conductive layer pattern120may be formed of polysilicon on which refractory metal such as cobalt (Co) or titanium (Ti) is deposited. Thereafter, the refractory metal formed on the first insulating layer140is removed, and the refractory metal formed on the second conductive layer pattern120is thermally treated, thus forming a polycide300contacting the second conductive layer pattern120. Through the silicidation, the resistance of the second conductive layer pattern120may be reduced.

Referring toFIG. 15, the air gap160is formed by performing a process similar to that shown inFIGS. 8 through 12. Since a process of forming the air gap160and a process of forming the polycide300may be consecutively performed, an interference effect between word lines may be improved and at the same time, the electric resistance of the word lines may be reduced.

FIGS. 16 through 24are schematic cross-sectional views illustrating a method of fabricating a semiconductor device according to some exemplary embodiments of the inventive concept. The method shown inFIGS. 16 through 24is a partial modification of the method shown inFIGS. 1 through 4. Detailed description of like features and elements will not be repeated.

Referring toFIG. 16, in some exemplary embodiments, the plurality of gate patterns130is formed in a cell region C, and at least one gate pattern130ais formed in a peripheral region P. As described above, in some exemplary embodiments, each of the gate patterns130in the cell region C may include at least the first conductive layer pattern110, the blocking insulating layer115, the second conductive layer pattern120, and the capping insulating layer125, and the gate pattern130ain the peripheral region P may include at least the first conductive layer pattern110a, the blocking insulating layer115a, the second conductive layer pattern120a, and the capping insulating layer125a. In each gate pattern130in the cell region C, the first conductive layer pattern110may be electrically separated from the second conductive layer pattern120by the blocking insulating layer115so that the gate pattern130may operate as a flash memory cell. In the gate pattern130aon the peripheral region P, the first conductive layer pattern110amay be electrically connected to, rather than being electrically separated from, the second conductive layer pattern120aby the blocking insulating layer115a.

Referring toFIGS. 17 and 18, in some exemplary embodiments, a mask layer200is formed on the first insulating layer140and the capping insulating layer125(and the capping insulating layer125a) in the cell region C and the peripheral region P. The mask layer200may include a mask insulating layer210and a photoresist layer220formed on the mask insulating layer210.

Thereafter, the photoresist layer220in the cell region C is exposed to light and developed, thus forming a photoresist pattern220aon the mask insulating layer210. The photoresist pattern220amay be formed to selectively cover the mask insulating layer210in correspondence with the capping insulating layer125. In addition, the photoresist pattern220amay be formed to cover the mask insulting layer210corresponding to the peripheral region P. The mask insulating layer210is then selectively etched using the photoresist pattern220aas an etch mask. The mask layer200disposed on the first insulating layer140in the cell region C is removed, such that the first insulating layer140may be exposed by the mask layer200.

Referring toFIG. 19, the first insulating layer140exposed by the mask layer200is etched to a predetermined depth. The mask layer200may function as an etch mask for etching the first insulating layer140. In some exemplary embodiments, the mask layer200formed in the peripheral region P may not be removed, and thus the gate pattern130aand the first insulating layer140in the peripheral region P may not be affected by the etching process. That is, in this case, the etching process and subsequent etching processes affect the first insulating layer140in the cell region C.

In some exemplary embodiments, the photoresist layer220included in the mask layer200may be a negative photoresist layer in which a structure of a light-irradiated region is reinforced and thus a portion that has not been exposed to light is removed during development. With the negative photoresist layer220, a uniform recess feature may be obtained during etching of the first insulating layer140.

Referring toFIGS. 20 through 22, in some exemplary embodiments, the third insulating layer142is formed on the first insulating layer140. The third insulating layer142may be formed of a material having an excellent step coverage. In some exemplary embodiments, the material may be, for example, a furnace-deposited oxide layer such as a HTO layer. As in the embodiments illustrated inFIGS. 7 through 12, the material of the third insulating layer142may have the same etching selectivity as that of the first insulating layer140. The third insulating layer142and the first insulating layer140are then sequentially etched. Thus, a recess deeper than the recess formed to the predetermined depth by the previous etching process may be formed.

In some exemplary embodiments, the material of the third insulating layer142may have an etching selectivity different from that of the first insulating layer140. In this case, the third insulating layer142may function as an etching mask for etching the first insulating layer140. The third insulating layer142may include a center portion250aand a spacer250bat both sides of the center portion250a. To etch the first insulating layer140, the center portion250aof the third insulating layer142is etched. In some exemplary embodiments, anisotropic etching may be applied to the third insulating layer142to etch only the center portion250awithout etching the spacer250b. Thereafter, the first insulating layer140can be additionally etched using the spacer250bas a mask. According to the exemplary embodiments of the inventive concept, with the spacer250bhaving an etching selectivity to the first insulating layer140, the sidewalls of each gate pattern130are prevented from being damaged during etching of the first insulating layer140.

Referring toFIGS. 23 and 24, the mask layer200in the cell region C and the peripheral region P is removed through ashing and/or strip processes. Thereafter, the second insulating layer150having a low step coverage is formed on the gate patterns130and the gate pattern130aand the first insulating layer140. The second insulating layer150is then planarized. Thus, the air gap160is formed between the first insulating layer140and the second insulating layer150. As described above, in some exemplary embodiments, other materials having low dielectric constants, instead of the air gap160, may also be formed between the first insulating layer140and the second insulating layer150.

FIGS. 25 and 26are schematic cross-sectional views illustrating a method of fabricating a semiconductor device according to some exemplary embodiments of the inventive concept. The method shown inFIGS. 25 and 26is a partial modification of the method shown inFIGS. 13 through 21. Detailed description of like features and elements will not be repeated.

Referring toFIGS. 25 and 26, in some exemplary embodiments, before the ashing and/or strip processes are performed on the mask layer200inFIG. 20, a lower portion of the first insulating layer140in the cell region C can be additionally etched. If portions of the first insulating layer140formed at sidewalls of the first conductive layer pattern110are spaced apart by a first interval W1, additional etching of the lower portion of the first insulating layer140may result in their being spaced apart by a second interval W2, which is larger than the first interval W1. In some exemplary embodiments, the additional etching may be dry etching and/or wet etching.

FIGS. 27 and 28are schematic cross-sectional views illustrating a method of fabricating a semiconductor device according to some exemplary embodiments of the inventive concept. The method shown inFIGS. 27 and 28is a partial modification of the method shown inFIGS. 22 and 23. Detailed description of like features and elements will not be repeated.

Referring toFIGS. 27 and 28, the lower portion of the first insulating layer140is further etched, such that the first insulating layer140at the sidewalls of the first conductive layer pattern110is removed. As a result, the first conductive layer pattern110is exposed. In this case, the air gap160formed between the first insulating layer140and the second insulating layer150may directly contact the first conductive layer pattern110.

FIG. 29is a schematic block diagram illustrating a card1000including a semiconductor device fabricated by a method of fabricating a semiconductor device according to some exemplary embodiments of the inventive concept.

Referring toFIG. 29, in some exemplary embodiments, the card1000may include a controller1010and a memory1020. The controller1010and the memory1020may be disposed to exchange electric signals. For example, when the controller1010issues a command, the memory1020may transmit data to the controller1010in response to the command. The memory1020may include a semiconductor device fabricated by a method of fabricating a semiconductor device according to one of the exemplary embodiments of the inventive concept described herein in detail. In some exemplary embodiments, the semiconductor device may be disposed in a “NAND” or “NOR” architecture memory array corresponding to logic gate design. In some exemplary embodiments, the memory array is composed of a plurality of rows and a plurality of columns which constitute one or more memory array banks. The memory1020may include such a memory array or a memory array bank. To drive the memory array bank, the card1000may further include a row decoder, a column decoder, input/output (I/O) buffers, and/or a control register. The card1000may be used in various types of card configurations, for example, a memory stick card, a smart media (SM) card, a secure digital (SD) card, a mini SD card, or a multimedia card (MMC).

FIG. 30is a schematic block diagram illustrating a system1100including a semiconductor device fabricated by a method of fabricating a semiconductor device according to some exemplary embodiments of the inventive concept described herein in detail.

Referring toFIG. 30, in some exemplary embodiments, the system1100may include a controller1110, an input/output (I/O) device1120, a memory1130, a memory1130, and an interface1140. The system1100may be, for example, a mobile system or a system for transmitting or receiving information. Examples of the mobile system may include a personal digital assistant (PDA), a portable computer, a web tablet, a wireless phone, a mobile phone, a digital music player, or a memory card. The controller1110may execute a program and control the system1100. The controller1110may be, for example, a microprocessor, a digital signal processor (DSP), a microcontroller, or other similar device. The I/O device1120may be used to input or output data of the system1100. In some exemplary embodiments, the system1100may be connected with an external device, e.g., a personal computer (PC) or a network, to exchange data with the external device by using the I/O device1120. The I/O device1120may be, for example, a keypad, a keyboard, or a display device. The memory1130may store codes and/or data for operating the controller1110, and/or store data processed by the controller1110. The memory1130may include a semiconductor device fabricated by a method of fabricating a semiconductor device according to one of the exemplary embodiments of the inventive concept described herein in detail. The interface1140may be a data transmission path between the system1100and external devices. The controller1110, the I/O device1120, the memory1130, and the interface1140may communicate with each other through a bus1150. The system1100may be used, for example, for a mobile phone, an MP3 player, a navigation system, a portable multimedia player (PMP), a solid state disk (SSD), or household appliances.

While the inventive concept has been particularly shown and described with reference to exemplary embodiments thereof, it will be understood that various substitutions, modifications, and changes in form and details may be made therein without departing from the spirit and scope of the following claims.