Method and circuit for implementing enhanced eFuse sense circuit

A method and circuit for implementing an eFuse sense amplifier, and a design structure on which the subject circuit resides are provided. A sensing circuit includes a pair of cross-coupled inverters, each formed by a pair of series connected P-channel field effect transistors (PFETs) and an N-channel field effect transistor (NFET). A first pull-up resistor is coupled between a positive voltage supply rail and a first sensing node of the sensing circuit. A second pull-up resistor is coupled between a positive voltage supply rail and a second sensing node of the sensing circuit. A first bitline is coupled to the first sensing node of the sensing circuit and a second bitline coupled to the second sensing node of the sensing circuit. One of a respective reference resistor and a respective eFuse cell is selectively coupled to the first bitline and the second bitline.

FIELD OF THE INVENTION

The present invention relates generally to the data processing field, and more particularly, relates to a method and circuit for implementing an enhanced eFuse sense amplifier, and a design structure on which the subject circuit resides.

DESCRIPTION OF THE RELATED ART

Electronic Fuses (eFuses) are currently used to configure elements after the silicon masking and fabrication process. These fuses typically are used to configure circuits for customization or to correct silicon manufacturing defects and increase manufacturing yield.

In very large scale integrated (VLSI) chips, it is common to have fuses, such as eFuses that can be programmed for various reasons. Among these reasons include invoking redundant elements in memory arrays for repairing failing locations or programming identification information.

As used in the following description and claims, it should be understood that the term eFuse means a non-volatile storage element that includes either an antifuse, which is a programmable element that provides an initial high resistance and when blown provides a selective low resistance or short circuit; or a fuse, which is a programmable element that provides an initial low resistance and when blown provides a selective high resistance or open circuit.

U.S. patent application Ser. No. 11/622,519 filed Jan. 12, 2007 discloses a sense amplifier illustrated inFIG. 1, which provided improvements over many prior art arrangements.

Referring toFIG. 1, there is shown a prior art sense amplifier100used for sensing an electronic fuse, or eFuse102to determine if the fuse102is a logical “0” or logical “1”. The fuse102stores information by electrically changing the resistance of a polysilicon resistor. Sense amplifier100includes true and complement sensing nodes respectively labeled S_T and S_C. A first precharge P-channel field effect transistor (PFET)104is connected between a positive voltage supply rail VDD and the true sensing node S_T that is connected via a pair of series connected N-channel field effect transistor (NFETs)106,108to the eFuse102. A second precharge P-channel field effect transistor (PFET)110is connected between the positive voltage supply rail VDD and the complement sensing node S_C that is connected via a pair of series connected N-channel field effect transistor (NFETs)112,114to a reference resistor116.

Sense amplifier100includes a pair of cross-coupled inverters connected to the true and complement sensing nodes S_T and S_C, as shown. A PFET120and an NFET122, and a PFET124and an NFET126respectively form the cross-coupled inverters. A pull-up PFET128connects PFETs120,124to the positive voltage supply rail VDD and a pull-down NFET130connects NFETs122,126to ground. The eFuse102and reference resistor116are connected to a common node labeled FSOURCE and a connected via a pair of series connected N-channel field effect transistor (NFETs)140,142to ground. A fuse programming circuit coupled to the eFuse102includes a NAND gate150receiving two inputs, BLOW_FUSE, FUSE_SOLUTION and providing an output applied to an inverter152, and a pair of series connected N-channel field effect transistor (NFETs)154,156connected between the eFuse102to ground.

When an eFuse is blown the final resistance of the eFuse has a distribution depending upon how well electromigration has occurred. How well electromigration occurs depends upon the amount voltage across the eFuse and amount of current through the eFuse.

Due to process, voltage, and current variation typically when an eFuse does not blow correctly results in a resistance, which is lower than expected. This lower resistance causes a problem in the ability to accurately sense if an eFuse is blown or not. Lower resistance of a blown eFuse is also a reliability concern.

In order to determine the state of an eFuse, an improved sense amplifier circuit is needed that will be able to determine if an eFuse is in its high resistance state or if it is in its low resistance state. As technology has advanced the difference between the low resistance state and the high resistance state has reduced. Due to this reduction in resistance delta it has become more and more difficult to determine a programmed eFuse from and unprogrammed eFuse. To help mitigate this issue differential sense amplifiers have been incorporated into the eFuse design. However, known sense amplifiers are not without their own weaknesses and have several sensitivities to process variation.

A need exists for a circuit for implementing an enhanced eFuse sense amplifier. It is desirable to provide such an enhanced eFuse sense amplifier that limits sensitivities to process variation and accurately determines a high resistance state or low resistance state of an eFuse.

SUMMARY OF THE INVENTION

Principal aspects of the present invention are to provide a method and circuit for implementing an enhanced eFuse sense amplifier, and a design structure on which the subject circuit resides. Other important aspects of the present invention are to provide such a method and circuit for implementing an enhanced eFuse sense amplifier substantially without negative effect and that overcome many of the disadvantages of prior art arrangements.

In brief, a method and circuit for implementing an eFuse sense amplifier, and a design structure on which the subject circuit resides are provided. A sensing circuit includes a pair of cross-coupled inverters. Each of the pair of cross-coupled inverters is formed by a pair of series connected P-channel field effect transistors (PFETs) and an N-channel field effect transistor (NFET). A first pull-up resistor is coupled between a positive voltage supply rail and a first sensing node of the sensing circuit. A second pull-up resistor is coupled between a positive voltage supply rail and a second sensing node of the sensing circuit. A first bitline is coupled to the first sensing node of the sensing circuit and a second bitline coupled to the second sensing node of the sensing circuit. One of a respective reference resistor and a respective eFuse cell is selectively coupled to the first bitline and the second bitline.

In accordance with features of the invention, the method and circuit for implementing the enhanced eFuse sense amplifier provides improved tolerance to process variation, and reduces voltage threshold (Vt) scatter effect in the sense amplifier. The pair of series connected P-channel field effect transistors (PFETs) and the N-channel field effect transistor (NFET) are body-contacted devices. The first bitline and second bitline are balanced on each side of the sensing circuit reducing capacitive coupling and balancing leakage currents on the bitlines.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

In accordance with features of the invention, a method and a circuit for implementing an enhanced eFuse sense amplifier are provided. The novel eFuse sense amplifier is arranged to limit the affect of process variation, Vt scatter, eFuse pre-blow resistance, and post-blow resistance on the sense amplifier.

Having reference now to the drawings, inFIG. 2A, there is shown an exemplary sense amplifier generally designated by the reference character200in accordance with the preferred embodiment.

Sense amplifier200includes a respective pull-up resistor202connected between a positive voltage supply rail VDD and a respective even and odd bitline BL0, BL1. The pull-up resistors202replace the precharge PFETs104,110of the prior art sense amplifier100in order to eliminate the Vt scatter, process sensitivity, and VDD sensitivity introduced by the precharge PFETs. The pull-up resistors202have a tighter tolerance to process variation then a PFET. The pull-up resistors202also react linearly to VDD changes while the PFETs strength has an exponential relationship to VDD, and of course resistors do not have any Vt scatter as do PFETs.

Sense amplifier200includes a respective transmission gate defined by a parallel connected pair of series connected P-channel field effect transistors (PFETs)204,206and pair of series connected N-channel field effect transistors (NFETs)208,209connected to the respective even and odd bitline BL0, BL1and a respective sensing node SA0, SA1of a sensing circuit210.

In accordance with features of the invention, the full transmission gate provided in the novel eFuse sense amplifier200improves the voltage head room at lower VDD operation with PFETs204,206passing a high voltage into the sensing circuit210. The transmission gate feeding into the sense amp was split into the series connected PFETs204,206, and NFETs208,209in order to reduce the sensitivity to Vt scatter and to reduce the speed that the signal from the bit line is able to go into the sensing circuit210by adding resistance into the path. Reducing how quickly the sensing circuit210reacts to voltage differentials on the bit lines proved critical as it substantially eliminated sensitivity to capacitive coupling when the sensing circuit210is turned on.

Sense amplifier200includes a programmable reference resistor circuit211connected to the even and odd bitline BL0, BL1on each side of the sensing circuit210. As shown inFIGS. 2A and 2B, a respective reference select signal is applied to a gate input of a respective select NFET212connected between ground and a respective reference resistor214connected to the respective even and odd bitline BL0, BL1. Each of the respective NFETs212receives a respective gate input RL0, or RL1, as shown. Each programmable reference resistor circuit211advantageously includes a plurality of reference resistors as shown inFIG. 3A, each having predetermined different resistance values. The respectively activated NFET212selects a particular reference resistor214having a predetermined reference resistor value, such as 1K ohm, 2K ohm, 4K ohm and 5K ohm.

Sensing circuit210includes a header PFET216connected between the voltage supply VDD and a pair of cross-coupled inverters connected to the sensing nodes SA0, SA1, as shown. A pair of series connected PFETs218,220and an NFET222, and a pair of series connected PFET224,226and an NFET228respectively form the cross-coupled inverters. Sensing circuit210includes a pull-down NFET230connecting NFETs222,228to ground. A respective inverter232,234coupled to the respective sensing node SA0, SA1drives a respective output OUT0, OUT1of the sense amplifier100.

In accordance with features of the invention, the PFETs218,220,224,226and NFETs222,228are body-contacted devices for removing SOI history effect from Vt-mismatch issue. Respective PFETs218, and PFETs220,224,226are stacked enabling more robust function over Vt-variation effects.

Referring also toFIG. 2B, there is shown an exemplary eFuse array250of a 64-bit column of eFuse cells0-63,252with the eFuse sense amplifier200ofFIG. 2Ain accordance with the preferred embodiment. The eFuse array250of a 64-bit column of fuse cells0-63,252is balanced bitlines BL0, BL1on each side of the sense amplifier200, with 32 even fuse cells252per bitline BL0from fuse cell0,252to fuse cell62,303, and 32 odd fuse cells252per bitline BL1from fuse cell1,252to fuse cell63,252.

Each fuse cell252includes an eFuse254connected to the respective one of the even and odd bitlines BL0, BL1and connected via a respective NFET256to ground. A respective wordline input WL0-WL63is applied to a gate input of each NFET256.

In accordance with features of the invention, the bit lines BL0, BL1attached to the sense amplifier200are balanced with respect to each other. On each side of the sense amplifier200there is 32 eFuse cells and all of the programmable reference resistors214. This also reduces otherwise capacitive coupling when the sense amplifier200turns on because substantially equal capacitances is provided on both sides of the sense amplifier200. This additionally balances the leakage currents pulling on the bit lines BL0, BL1.

Referring also toFIGS. 3A and 3B, there is shown an exemplary arrangement300of the eFuse sense amplifier circuit200and the eFuse array250with fuse blow and control testing circuits in accordance with the preferred embodiment.

Referring now toFIG. 3A, a pair of macro enable fuse blow and control testing signals MENB_P and PRG_P is respectively applied to a string of inverters302,304,306,308and310,312,314,316. A macro enable vertical signal MENB_P_VERT is provided at the output of inverter304and the testing signal MENB_P is provided at the output of inverter308. The testing signal PRG_P output of inverter316is applied to an input of a NAND gate318with a fuse blow control signal DIN applied to another input of NAND gate318. An inverted fuse blow signal BLOW_B is provided at the output of NAND gate318and is inverted by an inverter320providing fuse blow signal BLOW. A sense mode control-testing signal SM_P is applied to a string of inverters322,324,326,328, and330with a vertical signal SMB_P_VERT is provided at the output of inverter324. An inverted sense mode control testing signal SM_P at the output of inverter330is applied to a first input of a NAND gate332, with a second input connected to inverted fuse blow signal BLOW_B. An inverter334inverts the output of NAND gate332.

A parallel-connected PFET336and NFET338, and a parallel-connected PFET340and NFET342are connected between a program voltage supply rail VPRG and a respective bitline BL0, BL1. The fuse blow signal BLOW is applied to the gate input of PFETs336,340, and inverted fuse blow signal BLOW_B is applied to the gate input of NFETs338,342. The inverted output of NAND gate332at the output of inverter334is applied to a gate input of a pair of NFETs344,346connected between a respective bitline BL0, BL1and ground.

FIG. 3Aillustrates the eFuse array250of a 64-bit column of eFuse cells0-63,252, balanced between the respective bitlines BL0, BL1, with each even an odd eFuse cells receiving a respective wordline input WL<0>-WL <63>. The even and odd programmable reference resistor circuits211each includes a plurality of reference resistors352,354,356,358, with an associated reference resistor select NFET212receiving a respective gate input and controlled by REF_ODD<0:3> and REF_EVEN<0:3>, as shown.

In accordance with features of the invention, the plurality of selectable reference resistors352,354,356,358allow tuning of the sense function of the sense amplifier200. This allows changing the divider resistance that the selected eFuse254is compared against. The plurality of selectable reference resistors352,354,356,358provides additional robustness for the sense amplifier200.

Referring now toFIG. 3B, a sense amplifier200is shown connected between the respective bitlines BL0, BL1at the connection points360,362. InFIG. 3B, the sense amplifier200includes the same reference numerals as used inFIG. 2A. A macro enable control signal MEMB_N is generated with a respective series connected PFETs364and NFET365, and PFET366and NFET367is connected between the program voltage supply rail VPRG and ground with cross connected gates of PFETs364,366. A NAND gate369having inputs MENB_P_VERT and SM_P_VERT provides an output applied to a gate of NFET365and inverted by an inverter370and applied to a gate of NFET367. The macro enable control signal MEMB_N is applied to a gate input of a header PFET368. The header PFET368is connected between the pull-up resistors202of the sense amplifier200and the voltage supply rail VDD.

The NSET_P signal and control signal MENB_P_VERT are applied to respective inputs of a NAND gate372. The output of NAND gate372is applied to a pair of series connected inverters373,374to provide an inverted signal NSET and the output of inverter373is applied to a pair of series connected inverters375,377to provide a signal NSET, which are applied to the respective transmission gate NFETs208,209and PFETs204,206on each side SA0, SA1of the sensing circuit210. The NSET signal is applied to the footer NFET230of the sense amplifier200.

A data output DOUT of the sense amplifier200is provided with the first side SA0of the sensing circuit210providing an input to a NAND gate378with a second input of the NSET signal applied to the NAND gate378. The output of the NAND gate378is applied to an input of a NAND gate379. The second side SA1of the sensing circuit210provides an input to a NAND gate380with a second input of the NSET signal applied to the NAND gate380. The output of the NAND gate380is applied to an input of a NAND gate381. The respective outputs of NAND gates379,381are applied to a NAND gate382. A string of series connected inverters383,384,385are connected to the output of the NAND gate382providing the data output DOUT.

As shown inFIG. 3B, the PSET_N signal and control signal MENB_P_VERT are applied to respective inputs of an OR gate386. The output of OR gate386is applied to an inverter387providing the PSET signal applied to the header PFET216of the sensing circuit210.

A logic built in self test (LBIST) input signal LBIST_T is coupled by a pair of series connected inverters388,389to an exclusive-OR gate390, with an address signal ADDR <0> coupled by a string of series connected inverters391,392,393,394to a second input of the exclusive OR gate390. The output of exclusive-OR gate390is applied to the second input of the NAND gate379and the second input of the NAND gates381. The input signal LBIST_T is used to force an output multiplexer function of sense amplifier200into the compliment state. This allows the testing of all the down stream logic because both true and compliment states can be read. This also allows the testing of all upstream logic by forcing both states into the logic stream.

FIG. 4illustrates an exemplary organization of the array structure400. The eFuses254are oriented into an array structure400. The array structure400improves the cell to peripheral circuits area ratio. The array structure400allows the sense amplifier200to be shared by multiple eFuse cells252instead of having one sense amplifier per eFuse cell.

FIGS. 5 and 6illustrate testing operation of the eFuse sense amplifier200as shown inFIGS. 2A,2B,3A, and3B in accordance with the preferred embodiment.

Referring toFIG. 5, the input signals WL0and RL1go high to select the eFuse254coupled to bitline BL0and a particular reference resistor214. Then PSET_N signal as shown inFIGS. 2A,2B, which is applied to header PFET216falls, turning on PFET216and the sense amplification process commences. The header PFET216is turned off with PSET_N signal ON and the transmission gate PFETs204,206and NFETs208,209are turned on with the NSET_P signal OFF, then are turned off with the NSET_P signal ON.

Referring toFIG. 6, the input signals RL0and RL1go high to select the reference resistor214coupled to the respective bitlines BL0, BL1for forcing sensing circuit210to 0 and 1. A reference resistor for one side of the sensing circuit210is selected as the highest reference resistor available. A reference resistor for one side of the sensing circuit210is selected as the lowest reference resistor available. PSET signal as shown inFIGS. 3A,3B, which is applied to header PFET216falls, turning on PFET216and the testing sense amplification process commences. The header PFET216is turned off with PSET signal ON and the transmission gate PFETs204,206and NFETs208,209are turned on with the NSET signal OFF, then are turned off with the NSET signal ON.

FIG. 7shows a block diagram of an example design flow700. Design flow700may vary depending on the type of IC being designed. For example, a design flow700for building an application specific IC (ASIC) may differ from a design flow700for designing a standard component. Design structure702is preferably an input to a design process704and may come from an IP provider, a core developer, or other design company or may be generated by the operator of the design flow, or from other sources. Design structure702comprises circuit200,250,300in the form of schematics or HDL, a hardware-description language, for example, Verilog, VHDL, C, and the like. Design structure702may be contained on one or more machine readable medium. For example, design structure702may be a text file or a graphical representation of circuit100. Design process704preferably synthesizes, or translates, circuit200,250,300into a netlist706, where netlist706is, for example, a list of wires, transistors, logic gates, control circuits, I/O, models, etc. that describes the connections to other elements and circuits in an integrated circuit design and recorded on at least one of machine readable medium. This may be an iterative process in which netlist706is resynthesized one or more times depending on design specifications and parameters for the circuit.

Design process704may include using a variety of inputs; for example, inputs from library elements708which may house a set of commonly used elements, circuits, and devices, including models, layouts, and symbolic representations, for a given manufacturing technology, such as different technology nodes, 32 nm, 45 nm, 90 nm, and the like, design specifications710, characterization data712, verification data714, design rules716, and test data files718, which may include test patterns and other testing information. Design process704may further include, for example, standard circuit design processes such as timing analysis, verification, design rule checking, place and route operations, and the like. One of ordinary skill in the art of integrated circuit design can appreciate the extent of possible electronic design automation tools and applications used in design process704without deviating from the scope and spirit of the invention. The design structure of the invention is not limited to any specific design flow.

Design process704preferably translates an embodiment of the invention as shown inFIGS. 2A,2B,3A and3B along with any additional integrated circuit design or data (if applicable), into a second design structure720. Design structure720resides on a storage medium in a data format used for the exchange of layout data of integrated circuits, for example, information stored in a GDSII (GDS2), GL1, OASIS, or any other suitable format for storing such design structures. Design structure720may comprise information such as, for example, test data files, design content files, manufacturing data, layout parameters, wires, levels of metal, vias, shapes, data for routing through the manufacturing line, and any other data required by a semiconductor manufacturer to produce an embodiment of the invention as shown inFIGS. 2A,2B,3A and3B. Design structure720may then proceed to a stage722where, for example, design structure720proceeds to tape-out, is released to manufacturing, is released to a mask house, is sent to another design house, is sent back to the customer, and the like.