Adjusting refresh rate during self-refresh state

Methods, systems, and devices for adjusting a refresh rate during a self-refresh state are described. A memory system may enter a self-refresh state and execute a first set of refresh operations on a set of rows of memory cells at the memory system according to a first rate. The memory system may determine, based on executing the first set of refresh operations, that a counter associated with the set of refresh operations satisfies a threshold for a second time while the memory system is in the self-refresh state. In response to the counter satisfying the threshold for the second time, a flip-flop circuit at the memory system may modify an output of the flip-flop circuit and the memory system may decrease the rate for executing the refresh operations to a second rate based on the modified output of the flip-flop circuit.

FIELD OF TECHNOLOGY

The following relates to one or more systems for memory, including adjusting a refresh rate during a self-refresh state.

BACKGROUND

Memory systems are widely used to store information in various electronic devices such as computers, user devices, wireless communication devices, cameras, digital displays, and the like. Information is stored by programming memory cells within a memory system to various states. For example, binary memory cells may be programmed to one of two supported states, often denoted by a logic 1 or a logic 0. In some examples, a single memory cell may support more than two states, any one of which may be stored. To access the stored information, a component may read (e.g., sense, detect, retrieve, identify, determine, evaluate) a stored state in the memory system. To store information, a component may write (e.g., program, set, assign) the state in the memory system.

DETAILED DESCRIPTION

A memory system may perform refresh operations on one or more rows of memory cells at the memory system, which may improve a reliability of data stored by the corresponding rows of memory cells. To perform a refresh operation, a memory system may execute a read operation on a row of memory cells to detect data stored by that row and subsequently perform a write operation on the same row of memory cells to rewrite the data to the row of memory cells. In some cases, the memory system may execute refresh operations in response to receiving one or more refresh commands from a host system. Additionally, or alternatively, the memory system may execute refresh operations based on internally-generated refresh commands. For example, the memory system may enter a self-refresh state and execute refresh operations (e.g., in response to internally-generated refresh commands) on the rows of memory cells according to a refresh rate.

In some cases, a power consumption of the memory system operating in the self-refresh state may be based on the refresh rate. For example, the memory system may consume more power executing refresh operations according to a higher rate as compared to executing refresh operations according to a lower rate. However, performing refresh operations at a lower rate may lead to decreased reliability. In some cases, the memory system may be able to conserve power by switching between a higher refresh rate and a lower refresh rate. Thus, the memory system may perform some refresh operations at a higher rate and once reliability has been established switch to a lower refresh rate to conserve power. However, some memory systems may not provide for transitioning between refresh rates while in the self-refresh state.

Accordingly, the techniques as described herein provide for decreasing a power consumption associated with executing refresh operations in a self-refresh state while maintaining a reliability associated with the self-refresh state. Specifically, the memory system may enter a self-refresh state and begin executing refresh operations according to a first refresh rate (e.g., a relatively fast refresh rate). Once the memory system determines that each row of memory cells at the memory system is refreshed according to the first refresh rate, the memory system may decrease the refresh rate to a second, slower, refresh rate. Thus, the memory system may refresh each row of memory cells at the memory system according to a relatively fast refresh rate, which may preserve a reliability of data stored in the rows of memory cells. Additionally, the memory system may decrease a rate of executing refresh operations in the self-refresh state, which may decrease a power consumption of the memory system while in the self-refresh state (e.g., as compared to a memory system executing refresh operations in the self-refresh state according to a higher rate).

The memory system may rely on circuitry associated with a counter to determine whether each row of memory cells in the memory system have been refreshed according to the first, faster rate while in the self-refresh state (e.g., prior to decreasing the refresh rate to the second, slower refresh rate). For example, the memory system may include a counter, where a value of the counter indicates one of the rows of memory cells in the memory system and a refresh circuit of the memory system executes refresh operations on rows of memory cells based on corresponding values of the counter. For example, the refresh circuit may detect the value of the counter and identify one of the rows of memory cells indicated by the value of the counter. Then, the refresh circuit may execute a refresh operation at the indicated row of memory cells, increment the counter, and execute a next refresh operation on a next row of memory cells (e.g., based on the incremented value of the counter indicating the next row of memory cells).

In some cases, the value of the counter may satisfy a threshold and the memory system may reset the counter. For example, if a value of the counter indicates a last row of memory cells in the memory system (e.g., a row of memory cells associated with a larger value of the counter than other rows of memory cells at the memory system), the value of the counter may satisfy the threshold and the memory system may reset the counter to a value indicating a first row of memory cells in the memory system (e.g., a row of memory cells associated with a smaller value of the counter than other rows of memory cells at the memory system). The memory system may include circuitry (e.g., including two flip-flop circuits) that outputs a signal indicating for the memory system to decrease the refresh rate in response to detecting a second instance of resetting the counter while the memory system is in the self-refresh state. In some cases, outputting signaling indicating for the memory system to decrease the refresh rate after resetting the counter twice may ensure that each row of memory cells at the memory system is refreshed at least once prior to decreasing the refresh rate while operating in a refresh state.

Features of the disclosure are initially described in the context of systems and memory devices as described with reference toFIGS.1and2. Features of the disclosure are described in the context systems, timing diagrams, and circuitry as described with reference toFIGS.3through6. These and other features of the disclosure are further illustrated by and described with reference to an apparatus diagram and a flowchart that relate to adjusting a refresh rate during a self-refresh state as described with reference toFIGS.7and8.

FIG.1illustrates an example of a system100that supports adjusting a refresh rate during a self-refresh state in accordance with examples as disclosed herein. The system100may include a host system105, a memory system110, and a plurality of channels115coupling the host system105with the memory system110. The system100may include one or more memory systems110, but aspects of the one or more memory systems110may be described in the context of a single memory system (e.g., memory system110).

The system100may include portions of an electronic device, such as a computing device, a mobile computing device, a wireless device, a graphics processing device, a vehicle, or other systems. The memory system110may be a component of the system100that is operable to store data for one or more other components of the system100. In some cases, the memory system110may be referred to as a memory device.

Portions of the system100may be examples of the host system105. The host system105may be an example of a processor (e.g., circuitry, processing circuitry, a processing component) within a device that uses memory to execute processes. In some examples, the host system105may refer to the hardware, firmware, software, or any combination thereof that implements the functions of an external memory controller120.

A memory system110may be an independent device or a component that is operable to provide physical memory addresses space that may be used or referenced by the system100. In some examples, a memory system110may be configurable to work with one or more different types of host systems. The memory system110may be operable to store data for the components of the host system105. In some examples, the memory system110(e.g., operating as a secondary-type device to the host system105, operating as a dependent-type device to the host system105) may respond to and execute commands provided by the host system105through the external memory controller120.

The host system105may include one or more of an external memory controller120, a processor125, a basic input/output system (BIOS) component130, or other components such as one or more peripheral components or one or more input/output controllers. The components of the host system105may be coupled with one another using a bus135. The processor125may be operable to provide functionality (e.g., control functionality) for the system100or the host system105. The BIOS component130may be a software component that includes a BIOS operated as firmware, which may initialize and run various hardware components of the system100or the host system105. The BIOS component130may also manage data flow between the processor125and the various components of the system100or the host system105.

The memory system110may include a device memory controller155and one or more memory devices160(e.g., memory chips, memory dies) to support a capacity (e.g., a desired capacity, a specified capacity) for data storage. Each memory device160(e.g., memory device160-a, memory device160-b, memory device160-N) may include a local memory controller165(e.g., local memory controller165-a, local memory controller165-b, local memory controller165-N) and a memory array170(e.g., memory array170-a, memory array170-b, memory array170-N). A memory array170may be a collection (e.g., one or more grids, one or more banks, one or more tiles, one or more sections, one or more rows) of memory cells, with each memory cell being operable to store one or more bits of data. A memory system110including two or more memory devices160may be referred to as a multi-die memory or a multi-die package or a multi-chip memory or a multi-chip package.

The device memory controller155may include components (e.g., circuitry, logic) operable to control operation of the memory system110. The device memory controller155may include hardware, firmware, or instructions that enable the memory system110to perform various operations and may be operable to receive, transmit, or execute commands, data, or control information related to the components of the memory system110. The device memory controller155may be operable to communicate with one or more of the external memory controller120, the one or more memory devices160, or the processor125. In some examples, the device memory controller155may control operation of the memory system110described herein in conjunction with the local memory controller165of the memory device160.

In some examples, the memory system110may communicate information (e.g., data, commands, or both) with the host system105. For example, the memory system110may receive a write command indicating that the memory system110is to store data received from the host system105, or receive a read command indicating that the memory system110is to provide data stored in a memory device160to the host system105, among other types of information communication. For example, the memory system110may receive a refresh command from the host system105indicating that the memory system110is to execute a refresh operation at the memory devices160.

A local memory controller165(e.g., local to a memory device160) may include components (e.g., circuitry, logic) operable to control operation of the memory device160. In some examples, a local memory controller165may be operable to communicate (e.g., receive or transmit data or commands or both) with the device memory controller155. In some examples, a memory system110may not include a device memory controller155, and a local memory controller165or the external memory controller120may perform various functions described herein. As such, a local memory controller165may be operable to communicate with the device memory controller155, with other local memory controllers165, or directly with the external memory controller120, or the processor125, or any combination thereof.

The external memory controller120may be operable to enable communication of information (e.g., data, commands, or both) between components of the system100(e.g., between components of the host system105, such as the processor125, and the memory system110). The external memory controller120may process (e.g., convert, translate) communications exchanged between the components of the host system105and the memory system110. In some examples, the external memory controller120, or other component of the system100or the host system105, or its functions described herein, may be implemented by the processor125. Although the external memory controller120is depicted as being external to the memory system110, in some examples, the external memory controller120, or its functions described herein, may be implemented by one or more components of a memory system110(e.g., a device memory controller155, a local memory controller165) or vice versa.

The components of the host system105may exchange information with the memory system110using one or more channels115. Each channel115may include one or more signal paths (e.g., a transmission medium, a conductor) between terminals associated with the components of the system100. Channels115(and associated signal paths and terminals) may be dedicated to communicating one or more types of information. For example, the channels115may include one or more command and address (CA) channels186, one or more clock signal (CK) channels188, one or more data (DQ) channels190, one or more other channels192, or any combination thereof. In some examples, signaling may be communicated over the channels115using single data rate (SDR) signaling or double data rate (DDR) signaling. In SDR signaling, one modulation symbol (e.g., signal level) of a signal may be registered for each clock cycle (e.g., on a rising or falling edge of a clock signal). In DDR signaling, two modulation symbols (e.g., signal levels) of a signal may be registered for each clock cycle (e.g., on both a rising edge and a falling edge of a clock signal).

The memory system110may perform refresh operations at the memory arrays170of the memory system110. To perform a refresh operation, the memory system110(e.g., the device memory controller155, a local memory controller165) may execute a read operation on a row of memory cells at a memory array170to detect data stored by that row. Additionally, the memory system110may then perform a write operation on the same row of memory cells at the memory array170to rewrite the data to the row of memory cells. In some cases, the memory system110may execute refresh operations in response to receiving one or more refresh commands from the host system105(e.g., via the CA channel186). Additionally, or alternatively, the memory system110may execute refresh operations based commands generated by a controller of the memory system (e.g., the device memory controller155, a local memory controller165). For example, the memory system110may enter a self-refresh state and execute refresh operations (e.g., in response to internally-generated refresh commands) on the rows of memory cells in one or more memory arrays170according to a refresh rate. Additionally, or alternatively, the memory system110may cause one or more memory devices160to enter into a self-refresh state. Here, each memory device160in the self-refresh state may execute refresh operations on the rows of memory cells in a memory array170at the memory device160.

In some cases, a power consumption of the memory system110operating in the self-refresh state may be based on the refresh rate. For example, the memory system110may consume more power executing refresh operations according to a higher rate as compared to executing refresh operations according to a lower rate. In some cases, however, decreasing a rate associated with executing refresh operations may result in a decreased reliability of data stored in the rows of memory cells in the memory system110(e.g., an increase in one or more errors in the data). That is, upon entering the self-refresh state, a reliability of data stored in each row of memory cells may decrease as an amount of time between entering the self-refresh state and refreshing the corresponding row of memory cells increases. Thus, in cases that the memory system110enters the self-refresh state and executes refresh operations according to a relatively slow refresh rate, some rows of memory cells at the memory system may not be refreshed for a correspondingly large amount of time. Here, a reliability of data stored in those rows of memory cells may decrease.

Accordingly, the techniques as described herein provide for decreasing a power consumption associated with executing refresh operations in a self-refresh state while maintaining a reliability associated with the self-refresh state. Specifically, the memory system110may enter a self-refresh state and begin executing refresh operations (e.g., at a row of a memory array170) according to a first refresh rate (e.g., a relatively fast refresh rate). Specifically, the memory system110may include a counter, where a value of the counter indicates a row of memory cells in the memory system110to be refreshed and a refresh circuit of the memory system110executes refresh operations on rows of memory cells based on corresponding values of the counter. For example, the refresh circuit may detect the value of the counter and identify one of the rows of memory cells indicated by the value of the counter. Then, the refresh circuit may execute a refresh operation at the indicated row of memory cells, increment the counter, and execute a next refresh operation on a next row of memory cells (e.g., based on the incremented value of the counter indicating the next row of memory cells).

In some cases, the value of the counter may satisfy a threshold and the memory system110may reset the counter. That is, when a value of the counter indicates a last row of memory cells in the memory system110(e.g., a row of memory cells associated with a larger value of the counter than other rows of memory cells at the memory system110), the value of the counter may satisfy the threshold and the memory system110may reset the counter to a value indicating a first row of memory cells in the memory system110(e.g., a row of memory cells associated with a smaller value of the counter than other rows of memory cells at the memory system110). The memory system110may include circuitry (e.g., including two flip-flop circuits) that outputs a signal indicating for the memory system110to decrease the refresh rate in response to detecting a second instance of resetting the counter while the memory system110is in the self-refresh state. In some cases, outputting signaling indicating for the memory system110to decrease the refresh rate after resetting the counter twice may ensure that each row of memory cells at the memory system110is refreshed at least once prior to decreasing the refresh rate.

Thus, the memory system110may refresh each row of memory cells at the memory system110according to a relatively fast refresh rate, which may preserve a reliability of data stored in the rows of memory cells. Additionally, the memory system110may decrease a rate of executing refresh operations in the self-refresh state, which may decrease a power consumption of the memory system110while in the self-refresh state (e.g., as compared to a memory system110executing refresh operations in the self-refresh state according to a higher rate).

FIG.2illustrates an example of a memory device200that supports adjusting a refresh rate during a self-refresh state in accordance with examples as disclosed herein. The memory device200may be an example of the memory devices160described with reference toFIG.1. In some examples, the memory device200may be referred to as a memory chip, a memory die, or an electronic memory apparatus. The memory device200may include one or more memory cells205that may be programmable to store different logic states (e.g., programmed to one of a set of two or more possible states). For example, a memory cell205may be operable to store one bit of information at a time (e.g., a logic 0 or a logic 1). In some examples, a memory cell205(e.g., a multi-level memory cell) may be operable to store more than one bit of information at a time (e.g., a logic 00, logic 01, logic 10, a logic 11). In some examples, the memory cells205may be arranged in an array, such as a memory array170described with reference toFIG.1.

In some examples, a memory cell205may store a charge representative of the programmable states in a capacitor. DRAM architectures may include a capacitor that includes a dielectric material to store a charge representative of the programmable state. In other memory architectures, other storage devices and components are possible. For example, nonlinear dielectric materials may be employed. The memory cell205may include a logic storage component, such as capacitor230, and a switching component235(e.g., a cell selection component). The capacitor230may be an example of a dielectric capacitor or a ferroelectric capacitor. A node of the capacitor230may be coupled with a voltage source240, which may be the cell plate reference voltage, such as Vpl, or may be ground, such as Vss.

The memory device200may include access lines (e.g., word lines210, digit lines215) arranged in a pattern, such as a grid-like pattern. An access line may be a conductive line coupled with a memory cell205and may be used to perform access operations on the memory cell205. References to access lines, row lines, column lines, word lines, digit lines, or bit lines, or their analogues, are interchangeable without loss of understanding. Memory cells205may be positioned at intersections of the word lines210and the digit lines215.

Operations such as reading and writing may be performed on the memory cells205by activating access lines such as a word line210or a digit line215. By biasing a word line210and a digit line215(e.g., applying a voltage to the word line210or the digit line215), a single memory cell205may be accessed at their intersection. The intersection of a word line210and a digit line215in a two-dimensional or in a three-dimensional configuration may be referred to as an address of a memory cell205. Activating a word line210or a digit line215may include applying a voltage to the respective line.

Accessing the memory cells205may be controlled through a row decoder220, or a column decoder225, or any combination thereof. For example, a row decoder220may receive a row address from the local memory controller260and activate a word line210based on the received row address. A column decoder225may receive a column address from the local memory controller260and may activate a digit line215based on the received column address.

Selecting or deselecting the memory cell205may be accomplished by activating or deactivating the switching component235using a word line210. The capacitor230may be coupled with the digit line215using the switching component235. For example, the capacitor230may be isolated from digit line215when the switching component235is deactivated, and the capacitor230may be coupled with digit line215when the switching component235is activated.

The sense component245may be operable to detect a state (e.g., a charge) stored on the capacitor230of the memory cell205and determine a logic state of the memory cell205based on the stored state. The detected logic state of the memory cell205may be provided as an output of the sense component245(e.g., to an input/output255), and may indicate the detected logic state to another component of a memory device (e.g., a memory system110) that includes the memory device200.

The local memory controller260may control the accessing of memory cells205through the various components (e.g., row decoder220, column decoder225, sense component245). The local memory controller260may be an example of the local memory controller165described with reference toFIG.1. In some examples, one or more of the row decoder220, column decoder225, and sense component245may be co-located with the local memory controller260. The local memory controller260may be operable to receive one or more of commands or data from one or more different memory controllers (e.g., an external memory controller120associated with a host system105, another controller associated with the memory device200), translate the commands or the data (or both) into information that can be used by the memory device200, perform one or more operations on the memory device200, and communicate data from the memory device200to a host (e.g., a host system105) based on performing the one or more operations.

The local memory controller260may generate row signals and column address signals to activate the target word line210and the target digit line215. The local memory controller260also may generate and control various signals (e.g., voltages, currents) used during the operation of the memory device200. The local memory controller260may be operable to perform one or more access operations on one or more memory cells205of the memory device200. Examples of access operations may include a write operation, a read operation, a refresh operation, a precharge operation, or an activate operation, among others. In some examples, access operations may be performed by or otherwise coordinated by the local memory controller260in response to various access commands (e.g., from a host system105). The local memory controller260may be operable to perform other access operations not listed here or other operations related to the operating of the memory device200that are not directly related to accessing the memory cells205.

The local memory controller260may be operable to perform a write operation (e.g., a programming operation) on one or more memory cells205of the memory device200. During a write operation, a memory cell205of the memory device200may be programmed to store a desired state (e.g., logic state, charge state). The local memory controller260may identify a target memory cell205on which to perform the write operation. The local memory controller260may identify a target word line210and a target digit line215coupled with the target memory cell205(e.g., an address of the target memory cell205). The local memory controller260may activate the target word line210and the target digit line215(e.g., applying a voltage to the word line210or digit line215) to access the target memory cell205. The local memory controller260may apply a signal (e.g., a write pulse, a write voltage) to the digit line215during the write operation to store a specific state (e.g., charge) in the capacitor230of the memory cell205. The signal used as part of the write operation may include one or more voltage levels over a duration.

The local memory controller260may be operable to perform a read operation (e.g., a sense operation) on one or more memory cells205of the memory device200. During a read operation, the state (e.g., logic state, charge state) stored in a memory cell205of the memory device200may be evaluated (e.g., read, determined, identified). The local memory controller260may identify a target memory cell205on which to perform the read operation. The local memory controller260may identify a target word line210and a target digit line215coupled with the target memory cell205(e.g., the address of the target memory cell205). The local memory controller260may activate the target word line210and the target digit line215(e.g., applying a voltage to the word line210or digit line215) to access the target memory cell205. The target memory cell205may transfer a signal (e.g., charge, voltage) to the sense component245in response to biasing the access lines. The sense component245may amplify the signal. The local memory controller260may activate the sense component245(e.g., latch the sense component) and compare the signal received from the memory cell205to a reference (e.g., the reference250). Based on that comparison, the sense component245may determine a logic state that is stored on the memory cell205.

The local memory controller260may be operable to perform a refresh operation on one or more memory cells205of the memory device200. During a refresh operation, the state (e.g., logic state, charge state) stored in a row of memory cells205of the memory device200may be evaluated. The local memory controller260may identify a target row (e.g., a target word line210) based on a value of a counter (e.g., that is included in the local memory controller260, that is coupled with the local memory controller260) indicating the target row. Additionally, or alternatively, the local memory controller260may identify the target row based on receiving a command from another controller (e.g., a device memory controller as described with reference toFIG.1). In either example, the local memory controller260may activate the target word line210to access the memory cells205corresponding to the target word line210, the memory cells205may transfer signals to the sense component245, and the sense component245may determine the logic states stored on the memory cells205corresponding to the target word line210. Then, the local memory controller260may perform a write operation on the target word line210to write the data (e.g., the logic states stored on the memory cells205corresponding to the target word line210determined by the sense component245during the read operation) to the target word line210. The local memory controller260may then activate the target word line210and apply signals to the digit lines215to store the data in the capacitors230of the memory cells205corresponding to the target word line210. In some instances (e.g., in instances that the local memory controller260identifies the target word line210for the refresh operation based on a value of the counter), the local memory controller260may increment the value of the counter based on executing the refresh operation on the target word line210.

In some cases, the memory device200may execute refresh operations on the word lines210while in a self-refresh state. Specifically, the memory device200may enter a self-refresh state and begin executing refresh operations at each row of memory cells205(e.g., corresponding to a word line210) of the memory device200according to a first refresh rate (e.g., a relatively fast refresh rate). Once the local memory controller260determines that each row of memory cells205at the memory device200is refreshed according to the first refresh rate, the local memory controller260may decrease the refresh rate to a second, slower, refresh rate. In some cases, the local memory controller260may determine that each row of memory cells205at the memory device200is refreshed according to the first refresh rate using circuitry coupled with a counter, where a value of the counter indicates one of the rows of memory cells205and the local memory controller260executes refresh operations on the indicated row of memory cells205. In some cases, the value of the counter may satisfy a threshold and the local memory controller260may reset the counter. The memory device200(or a memory system including the memory device200) may include circuitry that outputs a signal indicating for the local memory controller260to decrease the refresh rate in response to detecting a second instance of resetting the counter while the memory device200is in the self-refresh state.

In some cases, outputting signaling indicating for the memory system to decrease the refresh rate after resetting the counter twice may ensure that each row of memory cells at the memory system is refreshed at least once prior to decreasing the refresh rate. Thus, the local memory controller260may refresh each row of memory cells205according to a relatively fast refresh rate, which may preserve a reliability of data stored in the rows of memory cells205. Additionally, the local memory controller260may decrease a rate of executing refresh operations in the self-refresh state, which may decrease a power consumption of the memory device200while in the self-refresh state (e.g., as compared to a memory device200executing refresh operations in the self-refresh state according to a higher rate).

FIG.3illustrates an example of a system300that supports adjusting a refresh rate during a self-refresh state in accordance with examples as disclosed herein. The system300may include aspects of the system and memory system as described with reference toFIGS.1and2. For example, the host system305, the memory system310, and the memory device360may be examples of the host system, memory system, and memory systems as described with reference toFIGS.1and2. The memory system310may additionally include a refresh circuit315, a refresh rate circuit320, and a counter325. In some cases, one or more of the refresh circuit315, the refresh rate circuit320, and the counter325may be implemented by a controller (e.g., a device memory controller, a local memory controller) as described with reference toFIGS.1and2. Additionally, or alternatively one or more of the refresh circuit315, the refresh rate circuit320, and the counter325may be implemented by circuitry that is distinct from a controller.

The memory system310may include one or more memory devices360(e.g., a memory array, a memory die). The memory device360may include a set of rows of memory cells330, where each row of memory cells330is configured to store a set of data at the memory device360. In some cases, the memory system310(e.g., via the refresh circuit315) may execute a refresh operation on a row of memory cells330. For example, the refresh circuit315may initiate a read operation at the row of memory cells330(e.g., to determine a set of data stored by the row of memory cells330). Then, the refresh circuit315may initiate a write operation at the row of memory cells330(e.g., to store the set of data determined during the read operation at the row of memory cells).

In some instances, the refresh circuit315may execute refresh operations on the rows of memory cells330in response to a command received from the host system305. That is, the host system305may transmit one or more commands indicating for the memory system310to execute one or more refresh operations. In some examples, the memory system310executing refresh operations in response to commands from the host system305may correspond to the memory system310operating in an automatic refresh state. Here, the automatic refresh state of the memory system310may correspond to a refresh rate (e.g., a preconfigured refresh rate, a predefined refresh rate, a refresh rate indicated by the host system305).

In addition to executing refresh operations in response to receiving a command from the host system305, the memory system310may execute refresh operations in response to internally-generated refresh commands. For example, the memory system310may enter a self-refresh state where the memory system310generates refresh commands and executes refresh operations without receiving commands from the host system305. In some cases, the memory system310may enter the self-refresh state in response to receiving a command from the host system305. Additionally, or alternatively, the memory system310may enter the self-refresh state based on an internally-generated command to enter the self-refresh state (e.g., from an automatic refresh state). In the self-refresh state, the refresh circuit315may generate a refresh command to execute a refresh operation on one of the rows of memory cells330.

The refresh circuit315may execute refresh operations on rows of memory cells330at the memory system310based on values of the counter325. For example, the refresh circuit315may detect the value of the counter325and identify one of the rows of memory cells330indicated by the value of the counter325. In some cases, the value of the counter325may correspond to an index of a row of memory cells330at the memory system310. Then, the refresh circuit315may execute a refresh operation at the indicated row of memory cells330, increment the counter325, and execute a next refresh operation on a next row of memory cells330(e.g., based on the incremented value of the counter325indicating the next row of memory cells330). For example, in a case that a first value of the counter325indicates the row of memory cells330-a, the refresh circuit315may execute a refresh operation on the row of memory cells330-a, increment the counter325(e.g., output signaling to the counter325indicating that a refresh operation occurred at the memory system310which may cause the counter325to increment the value of the counter325), and execute another refresh operation on the row of memory cells330-bindicated by the incremented value of the counter325.

In cases that the value of the counter325indicates a last row of memory cells330-cstoring data at the memory system310(e.g., a row of memory cells330-aassociated with a larger value than other rows of memory cells330at the memory system310), the counter325may roll over or reset a value of the counter325. In some cases, the memory system310may reset the value of the counter325in response to determining that the counter325is in an overflow condition (e.g., a value of the counter325satisfies a threshold). That is, the counter325may be associated with a threshold value (e.g., a maximum value). In cases that the value of the counter325satisfies the threshold, the memory system310may reset the value of the counter325. In some cases, the threshold may correspond to a maximum quantity of rows of memory cells330associated with the memory system310. After resetting the counter325, the value of the counter325may indicate a first row of memory cells330-aat the memory system310(e.g., a row of memory cells330-aassociated with a smaller value than other rows of memory cells330at the memory system310).

The refresh circuit315may initiate refresh operations on the rows of memory cells330(e.g., by generated refresh commands and executing the commands on a corresponding row of memory cells330) according to a refresh rate. In some cases, the refresh rate may correspond to a periodicity, rate, time period, or frequency for executing a refresh operation on one of the rows of memory cells330. Additionally, or alternatively, the rate may indicate a periodicity, rate, time period, or frequency for refreshing each of the rows of memory cells330at the memory system310. The refresh rate for executing refresh operations during the self-refresh state may be indicated to the refresh circuit315by the refresh rate circuit320. For example, the refresh rate circuit320may communicate signaling, to the refresh circuit315, indicating the refresh rate for executing refresh operations during the self-refresh state.

A refresh rate may impact the performance of the memory system. If the refresh rate is relatively fast, the memory system may use more power as it is frequently refreshing the state stored by memory cells. If the refresh is relatively slow, the memory system may experience additional errors because the state stored on the memory cells may deteriorate before the refresh operation is performed. In some cases, it may be useful to have a configurable refresh rate to mitigate the potential for errors in the data and to conserve power.

In some cases, the refresh rate circuit320may indicate, to the refresh circuit315, one of two or more possible refresh rates for executing refresh operations in the self-refresh state. For example, the refresh rate circuit320may output a signal corresponding to a low voltage state indicating the first refresh rate and may output a signal corresponding to a high voltage state indicating the second refresh rate. Here, the two possible refresh rates may be preconfigured or predefined (e.g., during a manufacturing of the memory system310, by the host system305). Additionally, or alternatively, the refresh rate circuit320may indicate, to the refresh circuit315, a refresh rate from more than two possible refresh rates for executing refresh operations in the self-refresh state. For example, the memory system310may be configured with a set of possible refresh rates (e.g., during a manufacturing of the memory system310, by the host system305). Then, the refresh rate circuit320may indicate one of the set of possible refresh rates to the refresh circuit315for executing refresh operations.

When the memory system310enters the self-refresh state, the memory system310may initially execute refresh operations according to a first, higher rate. For example, the refresh circuit315may execute a first set of refresh operations on the rows of memory cells330according to the first, higher rate. In this example, the refresh rate circuit320may output signaling to the refresh circuit315indicating for the refresh circuit315to execute refresh operations on the rows of memory cells330according to the first, higher rate. In some cases, the first, higher rate of executing refresh operations during the self-refresh state may be a same rate of executing refresh operations in response to refresh commands received from the host system (e.g., when the memory system310is in an automatic refresh state). For example, the memory system310may execute the first set of refresh operations to refresh each of the rows of memory cells330at the memory system310within 64 milliseconds (ms).

In some cases, the memory system310may decrease the rate of executing refresh operations while in the self-refresh state after executing a refresh operation on each of the rows of memory cells330at the memory system310. For example, the refresh rate circuit320may determine whether each of the rows of memory cells330have been refreshed according to the first, higher refresh rate. In cases that each of the rows of memory cells330have not been refreshed according to the first, higher refresh rate since the memory system310entered the self-refresh state, the refresh rate circuit320may output signaling to the refresh circuit315indicating for the refresh circuit315to execute the refresh operations on the rows of memory cells330according to the first, higher refresh rate. Additionally, in cases that each of the rows of memory cells330have been refreshed according to the first, higher refresh rate since the memory system310entered the self-refresh state, the refresh rate circuit320may output signaling to the refresh circuit315indicating for the refresh circuit315to execute the refresh operations on the rows of memory cells330according to a second, slower refresh rate.

In some cases, when executing refresh operations in the self-refresh state according to the second, slower refresh rate, the memory system310may execute a second set of refresh operations to refresh each of the rows of memory cells330at the memory system310within a larger time interval (e.g., 5 ms, 2 seconds). Additionally, or alternatively, the refresh rate circuit320may select the second, slower refresh rate based on a temperature of the memory system310. For example, in cases that a temperature of the memory system310is relatively low, the refresh rate circuit320may select a relatively slow second refresh rate (e.g., refreshing each of the rows of memory cells330within 2 seconds). In another example, in cases that a temperature of the memory system310is relatively high, the refresh rate circuit320may select a relatively fast second refresh rate (e.g., refreshing each of the rows of memory cells330within 5 ms).

The refresh rate circuit320may include circuitry configured to determine whether each of the rows of memory cells330have been refreshed according to the first, higher refresh rate since the memory system310entered the self-refresh state. In one example, the refresh rate circuit320may determine whether each of the rows of memory cells330have been refreshed based on comparing a value of the counter325when the memory system310initially entered the self-refresh state and a value of the counter325after executing each of the refresh operations while in the self-refresh state. Here, the refresh rate circuit320may determine that each of the rows of memory cells330have been refreshed when the value of the counter325when the memory system310initially entered the self-refresh state and the value of the counter325after executing a set of refresh operations are the same. That is, the value of the counter325may be the same as an initial value of the counter325when the counter325indicates for a row of memory cells330to be refreshed for a second time after entering the self-refresh mode.

In another example, the refresh rate circuit320may determine whether each of the rows of memory cells330have been refreshed based on comparing an initial address associated with a first row of memory cells330refreshed when the memory system310entered the self-refresh rate with an address of a row of memory cells330currently being refreshed by the memory system310. For example, the refresh rate circuit320may include one or more latches configured to store a row address corresponding to the row of memory cells330initially refreshed when the memory system310entered the self-refresh state. Additionally, the refresh rate circuit320may include an address comparator circuit configured to compare the row address stored by the one or more latches with a row address associated with a row of memory cells330currently being refreshed by the memory system310. Here, the refresh rate circuit320may determine that each of the rows of memory cells330have been refreshed when the row address corresponding to the row of memory cells330currently being refreshed is the same as the row address stored in the one or more latches at the refresh rate circuit320. That is, the row address corresponding to the row of memory cells330currently being refreshed may be the same as the initial row of memory cells330being refreshed when the memory system310entered the self-refresh state when the each of the rows of memory cells330has been refreshed once since the memory system310entered the self-refresh state.

In another example, the refresh rate circuit320may determine whether each of the rows of memory cells330have been refreshed based on initiating a counter at the refresh rate circuit320upon entering the self-refresh state. Here, the refresh rate circuit320may include a counter and when the memory system310enters the self-refresh state, the refresh rate circuit320may reset the counter (e.g., initialize the value of the counter to ‘0’) at the refresh rate circuit320. Then, the refresh rate circuit320may increment the value of the counter at the refresh rate circuit320in response to the refresh circuit315executing each of the refresh operations while in the self-refresh state. In one example, the refresh rate circuit320may compare the value of the counter at the refresh rate circuit320to a threshold that is based at least in part on a quantity of rows of memory cells330at the memory system310. For example, the threshold may be equal to or greater than the quantity of rows of memory cells330at the memory system310. When the refresh rate circuit320determines that the counter at the refresh rate circuit320exceeds the threshold, the refresh rate circuit320may determine that each of the rows of memory cells330have been refreshed at least once while the memory system310is in the self-refresh state. In another example, the counter may be associated with a threshold value (e.g., a maximum value). In cases that the value of the counter satisfies the threshold, the memory system310may detect an overflow condition of the counter and reset the value of the counter. Here, the refresh rate circuit320may determine that each of the rows of memory cells330have been refreshed at least once while the memory system310is in the self-refresh state based on detecting the overflow condition of the counter.

In another example, the refresh rate circuit320may determine whether each of the rows of memory cells330have been refreshed based on whether or not a value of the counter325has satisfied a threshold twice since the memory system310enters a self-refresh state. That is, the refresh rate circuit320may detect each instance of a value of the counter325satisfying the threshold (e.g., and subsequently resetting or rolling over the counter325). In response to determining that the value of the counter325satisfies the threshold a second time while the memory system310is in the self-refresh state, the refresh rate circuit may determine that each of the rows of memory cells330has been refreshed at least one time while the memory system310is in the self-refresh state. That is, when the memory system310enters the self-refresh state, the counter325may indicate a row of memory cells330based on a previously-executed refresh operation and therefore may not indicate a first row of memory cells330-awhen the memory system310initially enters the self-refresh state. As such, when a value of the counter325satisfies the threshold (e.g., and refreshes or rolls over to an initial value), there may be remaining rows of memory cells330that the refresh circuit315has not refreshed according to the first, higher refresh rate while in the self-refresh state. Therefore, the refresh rate circuit320signaling to the refresh circuit315to decrease the refresh rate in response to determining that the value of the counter325has satisfied a threshold for a second time since the memory system310enters the self-refresh state may ensure that each of the rows of memory cells330is refreshed at least once according to the first, higher refresh rate.

In response to receiving signaling from the refresh rate circuit320indicating to decrease the rate of executing refresh operations in the self-refresh state, the refresh circuit315may execute refresh operations on the rows of memory cells330according to the second, slower refresh rate. The refresh circuit315may continue executing refresh operations on the rows of memory cells330according to the second, slower refresh rate until the memory system310exits the self-refresh state. In some cases, the memory system310may exit the self-refresh state prior to the refresh rate circuit320indicating to decrease the rate of executing refresh operations. For example, the memory system310may exit the self-refresh state prior to the refresh rate circuit320determining that each of the rows of memory cells330have been refreshed according to the first, higher refresh rate. Here, the memory system310may exit the self-refresh state without the refresh circuit315switching from the first, faster refresh rate to the second, slower refresh rate.

FIG.4illustrates an example of a timing diagram400that supports adjusting a refresh rate during a self-refresh state in accordance with examples as disclosed herein. The timing diagram400may include aspects of the systems and memory devices as described with reference toFIGS.1through3. For example, a memory system (or in some cases, a memory device or a memory die) may implement the timing diagram400when entering and exiting a self-refresh state. In the example of the timing diagram400, the memory system may initially be in an automatic refresh state, may enter into a self-refresh state (e.g., at425), and may exit the self-refresh state (e.g., at435). The timing diagram400may illustrate an example set of operations performed by the memory system with respect to a clock signal405of the memory system or memory device.

At410, the memory system may perform an activation operation to activate one or more rows of memory cells at the memory system. For example, the memory system may apply a voltage to one or more access lines of the memory system (e.g., to access the corresponding rows of memory cells at the memory system). At415, the memory system may perform a write operation on the one or more rows of memory cells (e.g., activated at410). In some cases, the memory system may perform the activate and write operations at410and415, respectively, in response to a command received from a host system. Additionally, or alternatively, the memory system may perform the activate and write operations at410and415, respectively, in response to an internally-generated command (e.g., by a controller at the memory system). At420, the memory system may perform a precharge operation on the one or more rows of memory cells at the memory system. Here, the memory system may release data from a buffer (e.g., a write buffer) and deactivate the one or more rows of memory cells at the memory system (e.g., based on executing the write operation on the one or more rows of memory cells at the memory system at410).

In some cases, a reliability of the data stored in the one or more rows of memory cells during an execution of the write operation at415may be based on a time between415(e.g., executing the write operation) and420(e.g., executing the precharge operation). In some cases, a longer duration between the write operation at415and the precharge operation at420may improve a reliability of data stored during the write operation at415. Additionally, in cases that the time between415and420is shorter, the reliability of the data stored during the write operation at415may lessen. Here, executing a refresh operation on the one or more rows of memory cells (e.g., that were written to during the write operation at415) may increase the reliability of those one or more rows of memory cells.

At425, the memory system may enter the self-refresh state. For example, prior to425the memory system may execute refresh operations on rows of memory cells at the memory system in response to receiving commands (e.g., from a host system). At425, the memory system may enter the self-refresh state and begin executing refresh operations in response to internally-generated commands. Additionally, or alternatively, the memory system may decrease a power supply to one or more components of the memory system upon entering the self-refresh state. Thus, entering the self-refresh state may correspond to a decrease in power consumption of the memory system as compared to a power consumption prior to entering the self-refresh state at425.

The memory system may initially execute refresh operations according to a first, higher rate upon entering the self-refresh state at425. In some cases, the memory system may execute the refresh operations at a same rate of executing refresh operations in response to refresh commands received from the host system (e.g., prior to the memory system entering the self-refresh state at425). For example, the memory system may begin executing refresh operations at425to refresh each of the rows of memory cells at the memory system within 64 ms. In some cases, executing a refresh operation on each row of memory cells at the memory system may improve a reliability of data stored by the rows of memory cells. For example, one or more rows of memory cells may be associated with a decreased reliability prior to executing the refresh operation on the rows of memory cells (e.g., due to being written to at415in cases where a time between the write operation at415and the precharge operation at420is relatively short). Here, executing the refresh operations on those rows of memory cells may improve a reliability of the data stored by the rows of memory cells.

At430, the memory system may decrease the refresh rate from the first, faster refresh rate to a second, slower refresh rate. That is, at430the memory system may decrease the rate of executing refresh operations while in the self-refresh state after executing refresh operations on each of the rows of memory cells at the memory system according to the first, faster refresh rate. For example, at430the memory system may determine that each of the rows of memory cells at the memory system has been refreshed according to the first, faster refresh rate since entering the self-refresh state at425. In some cases, the memory system may determine that each of the rows of memory cells has been refreshed according to the first, faster refresh rate based on determining that a value of a counter at the memory system (e.g., indicating a row of memory cells for executing a refresh operation) has satisfied a threshold value two times since the memory system enters the self-refresh state at425. A refresh rate circuit may then decrease the refresh rate to the second, slower refresh rate in response to the determination. In some cases, executing refresh operations according to the first, higher refresh rate prior to decreasing a refresh rate may improve a reliability of the rows of memory cells at the memory system (e.g., as compared to entering the self-refresh state and initially executing refresh operations according to the second, slower refresh rate).

In the example of the timing diagram400, the memory system determines that each of the rows of memory cells have been refreshed according to the first, higher refresh rate while in the self-refresh state. In some other examples, a memory system may not determine that each of the rows of memory cells have been refreshed according to the first, higher refresh rate prior to exiting the self-refresh state. Here, the memory system may not decrease the rate for executing refresh operations while in the self-refresh state (e.g., may refrain from decreasing the rate for executing the refresh operations based on determining that each of the rows of memory cells have not been refreshed according to the first, higher refresh rate) and may exit the self-refresh state prior to decreasing the refresh rate.

In some cases, when executing refresh operations in the self-refresh state according to the second, slower refresh rate (e.g., after430), the memory system may execute refresh operations to refresh each of the rows of memory cells at the memory system within a larger time (e.g., as compared to a time associated with refreshing each of the rows of memory cells at the memory system according to the first, faster refresh rate).

At435, the memory system may exit the self-refresh state (e.g., and enter an automatic refresh state). That is, at435the memory system may stop generating commands to refresh rows of memory cells at the memory system and may begin executing refresh operations in response to commands received from a host system. As part of exiting the self-refresh state, the memory system may disable or reset circuits of the self-refresh state (e.g., circuits related to the refresh rate circuit and refresh circuit).

FIG.5illustrates an example of a circuitry500that supports adjusting a refresh rate during a self-refresh state in accordance with examples as disclosed herein. The circuitry500may include aspects of the memory system as described with reference toFIGS.1through4. For example, the refresh rate circuit520, the refresh circuit515, and the counter525may be examples of the refresh rate circuit320, the refresh circuit315, and the counter325, respectively, as described with reference toFIG.3. In some cases, the refresh rate circuit520, the refresh circuit515, and the counter525may be implemented by a controller (e.g., a device memory controller, a local memory controller) as described with reference toFIGS.1and2. Additionally, or alternatively, one or more of the refresh circuit515, the refresh rate circuit520, and the counter525may be implemented by circuitry that is distinct from a controller.

The refresh rate circuit520may include two flip-flop circuits505that each include data inputs530, clock inputs535, enable inputs540, and outputs545. In some cases, the flip-flop circuits505may be examples of D flip-flop with enable circuits. For example, the flip-flop circuits505may be disabled (e.g., the flip-flop circuits505may reset values of the signals570output from the flip-flop circuits505and may not propagate signals from the data inputs530to the outputs545) when the signal565applied to the enable inputs540is a first value. Additionally, the flip-flop circuits505may be enabled when the signal565applied to the enable inputs540is a second value (e.g., different from the first value). Additionally, the flip-flop circuits505may be gated. That is, the flip-flop circuits505may refrain from propagating signals555from the data inputs530to the outputs545based on the signals560applied to the clock inputs535. For example, the flip-flop circuits505may propagate signals555from the data inputs530to the outputs545synchronously (e.g., in response to a rising edge of the signal560applied to the clock inputs535, in response to the signal560being a value such as a high voltage or a low voltage). Thus, the flip-flop circuits505may refrain from propagating signals555from the data inputs530to the outputs545unless a signal565applied to the enable input540enables the flip-flop circuits505and a condition of the signal560applied to the clock input535is satisfied).

Two flip-flop circuits505may be used to adjust refresh rates to ensure that every memory cell gets refreshed at least once before slowing down the refresh rate. When a memory system first enters a self-refresh mode, there are possible scenarios where errors may develop in stored data if the memory cell storing the data are not refreshed relatively quickly. The combination of both flip-flop circuits may ensure that memory cells get refreshed at least once before the refresh rate is reduced (e.g., to conserve power).

The enable inputs540of the flip-flop circuits505may be coupled with the voltage circuit580. In some cases, the voltage circuit580may include a voltage supply and a switching component. Additionally, or alternatively, the voltage circuit580may by implemented by a controller of the memory system. In some cases, the voltage circuit580may apply a signal565to the enable inputs540of the flip-flop circuits to enable the flip-flop circuits505in response to the memory system entering a self-refresh state. For example, in response to entering the self-refresh state, the voltage circuit580may adjust a value of the signals565(e.g., from a first value to a second value) to enable the flip-flop circuits505. Additionally, in response to the memory system exiting the self-refresh state, the voltage circuit580may adjust the value of the signals565(e.g., from the second value to the first value) to disable the flip-flop circuits505. In some cases, upon being disabled, the flip-flop circuits505may reset values of the signals570to a preconfigured value.

The data input530-aof the flip-flop circuit505-amay be coupled with a voltage supply550. As such, the signal555applied to the data input530-aof the flip-flop circuit505-amay be a constant value (e.g., corresponding to the voltage supplied by the voltage supply550, VDD). Additionally, the data input530-bof the flip-flop circuit505-bmay be coupled with the output545of the flip-flop circuit505-avia the delay circuit510. The delay circuit510may delay changes in a value of the signal570-afrom propagating to the data input530-b. In one example, the delay circuit510may include a first inverter575-aand a second inverter575-b. The first inverter575-amay invert a value of the signal570-aand the second inverter575-bmay perform a second inversion that reverts the value to the signal570-a. Thus, a value of the signal555-bapplied to the data input530-bof the flip-flop circuit505-bmay be a same value as the signal570-a(e.g., after the delay). The clock inputs535of the flip-flop circuits505may be coupled with the counter525(or, in some cases, with circuitry that output the signals560based on a value of the counter525). In some cases, the counter525may indicate a row of memory cells for the refresh circuit515to refresh. When a value of the counter525satisfies a threshold, the counter525may adjust a value of the signals560applied to the clock inputs535of the flip-flop circuits505(e.g., from a first value to a second value). Additionally, in cases that the value of the counter525fails to satisfy the threshold, the counter525may adjust the value of the signals560from the second value to the first value. Thus, the signal560may be a first value in cases that the value of the counter525does not satisfy the threshold and may be a second value in cases that the value of the counter525does satisfy the threshold.

The signal570-bpropagated from the output545-bof the flip-flop circuit505-bmay indicate a refresh rate to the refresh circuit515. For example, when the memory system initially enters a self-refresh state, the signal570-bmay be a first value indicating for the refresh circuit515to execute refresh operations according to a first, faster refresh rate. Additionally, when the signal570-bis changed from the first value to a second value, the signal570-bmay indicate, to the refresh circuit515, to execute refresh operations according to a second, slower refresh rate.

When a value of the counter525satisfies the threshold for a first time since the memory system enters the self-refresh state, the signal560applied to the clock inputs535may be adjusted (e.g., from a first value to a second value). In some cases, the signal560-achanging from the first value to the second value may cause the flip-flop circuit505-ato propagate the signal555-a(e.g., the VDD applied to the data input530-aby the voltage supply550) to the output545-a. Thus, the signal570-amay change from a first value to a second value (e.g., to the voltage VDD) in response to the value of the counter525satisfying the threshold for the first time. In some cases, when the signal560-bapplied to the clock input535-bis adjusted in response to the value of the counter525for the first time since entering the self-refresh state, the value of the signal555-bmay be set to an initial value, which may the same as the value of the signal570-boutput from the flip-flop circuit505-b. Thus, the flip-flop circuit505-bmay not adjust the signal570-bof the output545-bof the flip-flop circuit505-bin response to the counter525satisfying the threshold for the first time.

The memory system may reset the counter525(e.g., may roll over the counter525) after the value of the counter525satisfies the threshold. For example, the refresh circuit515may execute a refresh operation at a row indicated by the value of the counter525that satisfies the threshold. Then the counter may reset the value of the counter525to an initial value. In response to resetting the value of the counter525(e.g., rolling over the counter525), the signal560applied to the clock inputs535may be adjusted (e.g., from the second value to the first value). In some cases, the delay circuit510may delay the change of the signal570-ato the signal555-bapplied to the data input530-bof the flip-flop circuit505-buntil after the signal560applied to the clock inputs535is adjusted (e.g., to the first value in response to resetting the counter525). Thus, the flip-flop circuit505-bmay refrain from propagating the signal555-bfrom the data input530-bto the output545-bbased on the signal560-bbeing the first value (e.g., until the signal560-bchanges from the first value to the second value again).

When the value of the counter525satisfies the threshold for a second time after the memory system enters the self-refresh state, the signal560applied to the clock inputs535may be adjusted (e.g., from the first value to the second value). When the clock input535-bchanges, the flip-flop circuit505-bmay propagate the signal555-bapplied to the data input530-bto the output545-b. Thus, the value of the signal570-bmay be adjusted from a first value to a second value (e.g., indicating for the refresh circuit515to decrease a rate for executing refresh operations). In some cases, the refresh circuit515may decrease the refresh rate by skipping instances of self-refresh, thus extending the time between refreshing rows of the memory array. In other cases, the refresh circuit515may decrease the refresh rate by extending the oscillator time.

FIG.6illustrates an example of a timing diagram600for the circuitry500that supports adjusting a refresh rate during a self-refresh state in accordance with examples as disclosed herein. The timing diagram600may include aspects of the memory system as described with reference toFIGS.1through5. For example, the clock signal610and the enable input signal615may be examples of the signals560applied to the clock inputs of the flip-flop circuits and the signals565applied to the enable inputs of the flip-flop circuits, respectively, as described with reference toFIG.5. Additionally, the flip-flop circuits605-aand605-bmay be examples of the flip-flop circuits505-aand505-b, respectively, as described with reference toFIG.5. The data input620may be an example of the signal555-aapplied to the data input of the flip-flop circuit505-a, the output625may be an example of the signal570-aoutput from the flip-flop circuit505-a, the data input630may be an example of the signal555-bapplied to the data input of the flip-flop circuit505-b, and the output635may be an example of the signal570-boutput from the flip-flop circuit505-bas described with reference toFIG.5.

The data input620may be coupled with the voltage supply550, which may produce a voltage VDD. Additionally, the output625, the data input630, and the output635may be initialized to a preconfigured voltage (e.g., V0). In some cases, there may be a slight time delay between the signal transition from a first voltage to a second voltage, therefore the signal transitions shown inFIG.6may not be instantaneous.

At time640, the memory system may enter the self-refresh state and accordingly the enable input signal615may change from a first voltage V2 to a second voltage V3. In some cases, the enable input signal615changing to the voltage V3 may enable the flip-flop circuits605(e.g., to propagate signals from the data inputs to the outputs of the flip-flop circuits605).

At time645, the clock signal610may transition from a first voltage V0 to a second voltage V1 in response to the counter525satisfying a threshold for a first time since the memory system enters the self-refresh state at time640. For example, the memory system may determine that the counter525is in an overflow condition. Additionally, or alternatively, the memory system may determine that a value of the counter525exceeds a maximum quantity of rows of memory cells in the memory system. In either example, the memory system may determine that a value of the counter525satisfies the threshold and the clock signal610may transition in response to the value of the counter525satisfying the threshold. In some cases, the transition of the clock signal610from the voltage V0 to the voltage VDD may trigger the flip-flop circuit605-ato propagate the value of the data input620to the output625. Accordingly, the output625may transition from a first voltage V0 to a second voltage VDD.

At time650, the counter525may roll over (e.g., the counter525may reset a value of the counter from a maximum value of the counter525to a minimum value of the counter525). In response to resetting the counter (e.g., to a value that fails to satisfy the threshold), the clock signal610may transition from the voltage V1 to the voltage V0.

In between the time645and the time655, the output625may propagate through the delay circuit510causing the data input630to transition from a first voltage V0 to V1. In some cases, propagating the output625through the delay circuit510to the data input630may occur after the time650, when the clock signal610changes to the voltage V0. In some cases, the flip-flop circuit605-bmay refrain from propagating the value of the data input630to the output635based on the clock signal610being set to V0.

At time655, the clock signal610may transition from the first voltage V0 to the second voltage V1 in response to the counter525satisfying the threshold for a second time since the memory system enters the self-refresh state at time640. In some cases, the transition of the clock signal610from the voltage V0 to the voltage V1 may trigger the flip-flop circuit605-bto propagate the value of the data input630to the output635. Accordingly, the output635may transition from the first voltage V0 to the second voltage VDD. When the output635reaches the voltage level VDD the refresh circuit515may decrease the rate of refresh operations performed on the rows of memory cells.

At660, the counter525may roll over (e.g., the counter525may reset a value of the counter from a maximum value of the counter525to a minimum value of the counter525). In response to resetting the counter (e.g., to a value that fails to satisfy the threshold), the clock signal610may transition from the voltage V1 to the voltage V0.

At time665, the memory system may exit the self-refresh state. In response to exiting the self-refresh state, the enable input signal615may transition from the second voltage level V3 to the first voltage level V2. The transition of the enable input signal615from the second voltage level V3 to the first voltage level V2 may trigger the flip-flop circuits605to reset. When the flip-flop circuits605reset, the output625and the output635may each transition from the voltage VDD to the voltage V0.

Although the timing diagram600illustrates the data input620, the output625, the data input630, and the output635changing in relation to the rising edge of the clock signal610(e.g., transition from V0 to V1), in other implementations the inputs and outputs may change in relation to the falling edge of the clock signal610(e.g., transition from V1 to V0). Similarly, while the timing diagram600shows the enable input signal615triggering the flip-flop circuits605to reset on a falling edge (e.g., transition from V3 to V2), in other implementations the enable input signal615may trigger the flip-flop circuits605on a rising edge (e.g., a transition from V2 to V3).

FIG.7shows a block diagram700of a memory system720that supports adjusting a refresh rate during a self-refresh state in accordance with examples as disclosed herein. The memory system720may be an example of aspects of a memory system as described with reference toFIGS.1through6. The memory system720, or various components thereof, may be an example of means for performing various aspects of adjusting a refresh rate during a self-refresh state as described herein. For example, the memory system720may include a refresh operation executor725, a threshold component730, a first flip-flop circuit component735, a counter component740, a second flip-flop circuit component745, a refresh rate component750, a clock component755, an enable component760, a self-refresh state component765, or any combination thereof. Each of these components may communicate, directly or indirectly, with one another (e.g., via one or more buses).

The refresh operation executor725may be configured as or otherwise support a means for executing, while in a self-refresh state, a plurality of refresh operations on a plurality of rows of memory cells at a memory system according to a first rate for executing refresh operations. The threshold component730may be configured as or otherwise support a means for determining, based at least in part on executing a first subset of the plurality of refresh operations, that a counter associated with the plurality of refresh operations on the plurality of rows of memory cells satisfies a threshold a first time. The first flip-flop circuit component735may be configured as or otherwise support a means for modifying a first output of a first flip-flop circuit at the memory system from a first value to a second value based at least in part on determining that the counter satisfies the threshold the first time. The counter component740may be configured as or otherwise support a means for resetting the counter based at least in part on determining that the counter satisfies the threshold. In some examples, the threshold component730may be configured as or otherwise support a means for determining, after resetting the counter, that the counter satisfies the threshold a second time based at least in part on executing a second subset of the plurality of refresh operations. The second flip-flop circuit component745may be configured as or otherwise support a means for modifying a second output of a second flip-flop circuit at the memory system from the first value to the second value based at least in part on modifying the first output of the first flip-flop circuit to the second value and determining that the counter satisfies the threshold the second time. The refresh rate component750may be configured as or otherwise support a means for decreasing a rate for executing refresh operations in the self-refresh state from the first rate to a second rate based at least in part on modifying the second output of the second flip-flop circuit.

In some examples, to support modifying the first output of the first flip-flop circuit, the first flip-flop circuit component735may be configured as or otherwise support a means for coupling a data input of the first flip-flop circuit with a voltage supply based at least in part on entering the self-refresh state. In some examples, to support modifying the first output of the first flip-flop circuit, the clock component755may be configured as or otherwise support a means for applying a first signal to a clock input of the first flip-flop circuit based at least in part on determining that the counter satisfies the threshold the first time. In some examples, to support modifying the first output of the first flip-flop circuit, the second flip-flop circuit component745may be configured as or otherwise support a means for outputting a second signal from the first flip-flop circuit based at least in part on applying the first signal to the clock input of the first flip-flop circuit while the data input of the first flip-flop circuit is coupled with the voltage supply.

In some examples, to support modifying the second output of the second flip-flop circuit, the second flip-flop circuit component745may be configured as or otherwise support a means for applying the second signal to a data input of the second flip-flop circuit based at least in part on outputting the second signal from the first flip-flop circuit. In some examples, to support modifying the second output of the second flip-flop circuit, the clock component755may be configured as or otherwise support a means for applying the first signal to a clock input of the second flip-flop circuit based at least in part on determining that the counter satisfies the threshold the second time. In some examples, to support modifying the second output of the second flip-flop circuit, the second flip-flop circuit component745may be configured as or otherwise support a means for outputting a third signal from the second flip-flop circuit based at least in part on applying the first signal to the clock input of the second flip-flop circuit while applying the second signal to the data input of the second flip-flop circuit, where decreasing the rate for executing the refresh operations in the self-refresh state is based at least in part on outputting the third signal from the second flip-flop circuit.

In some examples, the clock component755may be configured as or otherwise support a means for applying a first signal to a clock input of the second flip-flop circuit based at least in part on determining that the counter satisfies the threshold the first time. In some examples, the second flip-flop circuit component745may be configured as or otherwise support a means for refraining from modifying the second output of the second flip-flop circuit in response to the applying the first signal to the clock input of the second flip-flop circuit based at least in part on a signal at a data input of the second flip-flop circuit being unchanged.

In some examples, the second flip-flop circuit component745may be configured as or otherwise support a means for applying, with a delay, the second value output by the first flip-flop circuit to the data input of the second flip-flop circuit based at least in part on modifying the first output of the first flip-flop circuit, where modifying the second output of the second flip-flop circuit is based at least in part on applying the second value output by the first flip-flop circuit to the data input of the second flip-flop circuit.

In some examples, the enable component760may be configured as or otherwise support a means for applying a signal to an enable input of the first flip-flop circuit while in the self-refresh state, where modifying the first output of the first flip-flop circuit is based at least in part on applying the signal to the enable input of the first flip-flop circuit.

In some examples, the self-refresh state component765may be configured as or otherwise support a means for exiting the self-refresh state based at least in part on decreasing the rate for executing refresh operations. In some examples, the enable component760may be configured as or otherwise support a means for refraining from applying the signal to the enable input of the first flip-flop circuit based at least in part on exiting the self-refresh state.

In some examples, the enable component760may be configured as or otherwise support a means for applying a signal to an enable input of the second flip-flop circuit based at least in part on entering the self-refresh state, where modifying the second output of the second flip-flop circuit is based at least in part on applying the signal to the enable input of the second flip-flop circuit.

In some examples, the self-refresh state component765may be configured as or otherwise support a means for exiting the self-refresh state based at least in part on decreasing the rate for executing refresh operations. In some examples, the enable component760may be configured as or otherwise support a means for refraining from applying the signal to the enable input of the second flip-flop circuit based at least in part on exiting the self-refresh state.

In some examples, the counter component740may be configured as or otherwise support a means for incrementing the counter based at least in part on executing each of the first subset of the plurality of refresh operations, where determining that the counter satisfies the threshold the first time is based at least in part on incrementing the counter. In some examples, the counter component740may be configured as or otherwise support a means for incrementing the counter after resetting the counter based at least in part on executing each of the second subset of the plurality of refresh operations, where determining that the counter satisfies the threshold the second time is based at least in part on incrementing the counter.

In some examples, each value of the counter indicates an address associated with one of the plurality of rows of memory cells. In some examples, executing the plurality of refresh operations on the plurality of rows of memory cells is based at least in part on the counter indicating a plurality of addresses associated with each of the plurality of rows of memory cells.

In some examples, the refresh operation executor725may be configured as or otherwise support a means for executing a second plurality of refresh operations on the plurality of rows of memory cells according to the second rate based at least in part on decreasing the rate for executing refresh operations in the self-refresh state.

In some examples, to support determining that the counter associated with performing refresh operations satisfies the threshold, the threshold component730may be configured as or otherwise support a means for determining that the counter is in an overflow condition.

In some examples, to support determining that the counter associated with performing refresh operations satisfies the threshold, the threshold component730may be configured as or otherwise support a means for determining that the counter exceeds a maximum quantity of rows associated with the memory system.

In some examples, the self-refresh state component765may be configured as or otherwise support a means for entering the self-refresh state. In some examples, the threshold component730may be configured as or otherwise support a means for determining an index of a row on which self-refresh operations are performed in response to entering the self-refresh state, where the threshold is based at least in part on the index of the row.

FIG.8shows a flowchart illustrating a method800that supports adjusting a refresh rate during a self-refresh state in accordance with examples as disclosed herein. The operations of method800may be implemented by a memory system or its components as described herein. For example, the operations of method800may be performed by a memory system as described with reference toFIGS.1through7. In some examples, a memory system may execute a set of instructions to control the functional elements of the device to perform the described functions. Additionally, or alternatively, the memory system may perform aspects of the described functions using special-purpose hardware.

At805, the method may include executing, while in a self-refresh state, a plurality of refresh operations on a plurality of rows of memory cells at a memory system according to a first rate for executing refresh operations. The operations of805may be performed in accordance with examples as disclosed herein. In some examples, aspects of the operations of805may be performed by a refresh operation executor725as described with reference toFIG.7.

At810, the method may include determining, based at least in part on executing a first subset of the plurality of refresh operations, that a counter associated with the plurality of refresh operations on the plurality of rows of memory cells satisfies a threshold a first time. The operations of810may be performed in accordance with examples as disclosed herein. In some examples, aspects of the operations of810may be performed by a threshold component730as described with reference toFIG.7.

At815, the method may include modifying a first output of a first flip-flop circuit at the memory system from a first value to a second value based at least in part on determining that the counter satisfies the threshold the first time. The operations of815may be performed in accordance with examples as disclosed herein. In some examples, aspects of the operations of815may be performed by a first flip-flop circuit component735as described with reference toFIG.7.

At820, the method may include resetting the counter based at least in part on determining that the counter satisfies the threshold. The operations of820may be performed in accordance with examples as disclosed herein. In some examples, aspects of the operations of820may be performed by a counter component740as described with reference toFIG.7.

At825, the method may include determining, after resetting the counter, that the counter satisfies the threshold a second time based at least in part on executing a second subset of the plurality of refresh operations. The operations of825may be performed in accordance with examples as disclosed herein. In some examples, aspects of the operations of825may be performed by a threshold component730as described with reference toFIG.7.

At830, the method may include modifying a second output of a second flip-flop circuit at the memory system from the first value to the second value based at least in part on modifying the first output of the first flip-flop circuit to the second value and determining that the counter satisfies the threshold the second time. The operations of830may be performed in accordance with examples as disclosed herein. In some examples, aspects of the operations of830may be performed by a second flip-flop circuit component745as described with reference toFIG.7.

At835, the method may include decreasing a rate for executing refresh operations in the self-refresh state from the first rate to a second rate based at least in part on modifying the second output of the second flip-flop circuit. The operations of835may be performed in accordance with examples as disclosed herein. In some examples, aspects of the operations of835may be performed by a refresh rate component750as described with reference toFIG.7.

In some examples, an apparatus as described herein may perform a method or methods, such as the method800. The apparatus may include features, circuitry, logic, means, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor), or any combination thereof for performing the following aspects of the present disclosure:Aspect 1: A method, apparatus, or non-transitory computer-readable medium including operations, features, circuitry, logic, means, or instructions, or any combination thereof for executing, while in a self-refresh state, a plurality of refresh operations on a plurality of rows of memory cells at a memory system according to a first rate for executing refresh operations; determining, based at least in part on executing a first subset of the plurality of refresh operations, that a counter associated with the plurality of refresh operations on the plurality of rows of memory cells satisfies a threshold a first time; modifying a first output of a first flip-flop circuit at the memory system from a first value to a second value based at least in part on determining that the counter satisfies the threshold the first time; resetting the counter based at least in part on determining that the counter satisfies the threshold; determining, after resetting the counter, that the counter satisfies the threshold a second time based at least in part on executing a second subset of the plurality of refresh operations; modifying a second output of a second flip-flop circuit at the memory system from the first value to the second value based at least in part on modifying the first output of the first flip-flop circuit to the second value and determining that the counter satisfies the threshold the second time; and decreasing a rate for executing refresh operations in the self-refresh state from the first rate to a second rate based at least in part on modifying the second output of the second flip-flop circuit.Aspect 2: The method, apparatus, or non-transitory computer-readable medium of aspect 1 where modifying the first output of the first flip-flop circuit includes operations, features, circuitry, logic, means, or instructions, or any combination thereof for coupling a data input of the first flip-flop circuit with a voltage supply based at least in part on entering the self-refresh state; applying a first signal to a clock input of the first flip-flop circuit based at least in part on determining that the counter satisfies the threshold the first time; and outputting a second signal from the first flip-flop circuit based at least in part on applying the first signal to the clock input of the first flip-flop circuit while the data input of the first flip-flop circuit is coupled with the voltage supply.Aspect 3: The method, apparatus, or non-transitory computer-readable medium of aspect 2 where modifying the second output of the second flip-flop circuit includes operations, features, circuitry, logic, means, or instructions, or any combination thereof for applying the second signal to a data input of the second flip-flop circuit based at least in part on outputting the second signal from the first flip-flop circuit; applying the first signal to a clock input of the second flip-flop circuit based at least in part on determining that the counter satisfies the threshold the second time; and outputting a third signal from the second flip-flop circuit based at least in part on applying the first signal to the clock input of the second flip-flop circuit while applying the second signal to the data input of the second flip-flop circuit, where decreasing the rate for executing the refresh operations in the self-refresh state is based at least in part on outputting the third signal from the second flip-flop circuit.Aspect 4: The method, apparatus, or non-transitory computer-readable medium of any of aspects 1 through 3, further including operations, features, circuitry, logic, means, or instructions, or any combination thereof for applying a first signal to a clock input of the second flip-flop circuit based at least in part on determining that the counter satisfies the threshold the first time and refraining from modifying the second output of the second flip-flop circuit in response to the applying the first signal to the clock input of the second flip-flop circuit based at least in part on a signal at a data input of the second flip-flop circuit being unchanged.Aspect 5: The method, apparatus, or non-transitory computer-readable medium of aspect 4, further including operations, features, circuitry, logic, means, or instructions, or any combination thereof for applying, with a delay, the second value output by the first flip-flop circuit to the data input of the second flip-flop circuit based at least in part on modifying the first output of the first flip-flop circuit, where modifying the second output of the second flip-flop circuit is based at least in part on applying the second value output by the first flip-flop circuit to the data input of the second flip-flop circuit.Aspect 6: The method, apparatus, or non-transitory computer-readable medium of any of aspects 1 through 5, further including operations, features, circuitry, logic, means, or instructions, or any combination thereof for applying a signal to an enable input of the first flip-flop circuit while in the self-refresh state, where modifying the first output of the first flip-flop circuit is based at least in part on applying the signal to the enable input of the first flip-flop circuit.Aspect 7: The method, apparatus, or non-transitory computer-readable medium of aspect 6, further including operations, features, circuitry, logic, means, or instructions, or any combination thereof for exiting the self-refresh state based at least in part on decreasing the rate for executing refresh operations and refraining from applying the signal to the enable input of the first flip-flop circuit based at least in part on exiting the self-refresh state.Aspect 8: The method, apparatus, or non-transitory computer-readable medium of any of aspects 1 through 7, further including operations, features, circuitry, logic, means, or instructions, or any combination thereof for applying a signal to an enable input of the second flip-flop circuit based at least in part on entering the self-refresh state, where modifying the second output of the second flip-flop circuit is based at least in part on applying the signal to the enable input of the second flip-flop circuit.Aspect 9: The method, apparatus, or non-transitory computer-readable medium of aspect 8, further including operations, features, circuitry, logic, means, or instructions, or any combination thereof for exiting the self-refresh state based at least in part on decreasing the rate for executing refresh operations and refraining from applying the signal to the enable input of the second flip-flop circuit based at least in part on exiting the self-refresh state.Aspect 10: The method, apparatus, or non-transitory computer-readable medium of any of aspects 1 through 9, further including operations, features, circuitry, logic, means, or instructions, or any combination thereof for incrementing the counter based at least in part on executing each of the first subset of the plurality of refresh operations, where determining that the counter satisfies the threshold the first time is based at least in part on incrementing the counter and incrementing the counter after resetting the counter based at least in part on executing each of the second subset of the plurality of refresh operations, where determining that the counter satisfies the threshold the second time is based at least in part on incrementing the counter.Aspect 11: The method, apparatus, or non-transitory computer-readable medium of any of aspects 1 through 10 where each value of the counter indicates an address associated with one of the plurality of rows of memory cells and executing the plurality of refresh operations on the plurality of rows of memory cells is based at least in part on the counter indicating a plurality of addresses associated with each of the plurality of rows of memory cells.Aspect 12: The method, apparatus, or non-transitory computer-readable medium of any of aspects 1 through 11, further including operations, features, circuitry, logic, means, or instructions, or any combination thereof for executing a second plurality of refresh operations on the plurality of rows of memory cells according to the second rate based at least in part on decreasing the rate for executing refresh operations in the self-refresh state.Aspect 13: The method, apparatus, or non-transitory computer-readable medium of any of aspects 1 through 12 where determining that the counter associated with performing refresh operations satisfies the threshold includes operations, features, circuitry, logic, means, or instructions, or any combination thereof for determining that the counter is in an overflow condition.Aspect 14: The method, apparatus, or non-transitory computer-readable medium of any of aspects 1 through 13 where determining that the counter associated with performing refresh operations satisfies the threshold includes operations, features, circuitry, logic, means, or instructions, or any combination thereof for determining that the counter exceeds a maximum quantity of rows associated with the memory system.Aspect 15: The method, apparatus, or non-transitory computer-readable medium of any of aspects 1 through 14, further including operations, features, circuitry, logic, means, or instructions, or any combination thereof for entering the self-refresh state and determining an index of a row on which self-refresh operations are performed in response to entering the self-refresh state, where the threshold is based at least in part on the index of the row.

An apparatus is described. The following provides an overview of aspects of the apparatus as described herein:Aspect 16: An apparatus, including: a memory system including a plurality of rows of memory cells; a refresh circuit configured to execute, while the memory system is in a self-refresh state, a plurality of refresh operations on the plurality of rows of memory cells according to a first rate for executing refresh operations or a second rate for executing refresh operation; a counter configured to count a quantity of refresh operation performed on the plurality of rows of memory cells; and a refresh rate circuit configured to determine that the counter associated with the plurality of refresh operations on the plurality of rows of memory cells satisfies a threshold and decreasing a rate for executing the plurality of refresh operations from the first rate to the second rate based at least in part on determining that the counter satisfies the threshold.Aspect 17: The apparatus of aspect 16, where the refresh rate circuit further includes: a first flip-flop circuit including a first data input, a first enable input, a first clock input, and a first output, the first data input coupled with a voltage supply, the first flip-flop circuit configured to modify the first output of the first flip-flop circuit from a first value to a second value based at least in part on determining that the counter satisfies the threshold a first time; and a second flip-flop circuit a second data input, a second enable input, a second clock input, and a second output, the second data input coupled with the first output of the first flip-flop circuit, the second flip-flop circuit configured to modify the second output of the second flip-flop circuit from the first value to the second value based at least in part on modifying the first output of the first flip-flop circuit to the second value and determining that the counter satisfies the threshold a second time.Aspect 18: The apparatus of aspect 17, where the refresh rate circuit further includes: a delay circuit coupled with the first output of the first flip-flop circuit and the second data input of the second flip-flop circuit, the delay circuit configured to delay an application of the second value to the second data input of the second flip-flop circuit.Aspect 19: The apparatus of any of aspects 17 through 18, where: a first signal is applied to the first enable input of the first flip-flop circuit and the second enable input of the first flip-flop circuit based at least in part on the memory system operating in the self-refresh state; and a second signal is applied to the first clock input of the first flip-flop circuit and the second clock input of the second flip-flop circuit based at least in part on the counter satisfying the threshold.

The terms “electronic communication,” “conductive contact,” “connected,” and “coupled” may refer to a relationship between components that supports the flow of signals between the components. Components are considered in electronic communication with (e.g., in conductive contact with, connected with, coupled with) one another if there is any electrical path (e.g., conductive path) between the components that can, at any time, support the flow of signals (e.g., charge, current voltage) between the components. At any given time, a conductive path between components that are in electronic communication with each other (e.g., in conductive contact with, connected with, coupled with) may be an open circuit or a closed circuit based on the operation of the device that includes the connected components. A conductive path between connected components may be a direct conductive path between the components or the conductive path between connected components may be an indirect conductive path that may include intermediate components, such as switches, transistors, or other components. In some examples, the flow of signals between the connected components may be interrupted for a time, for example, using one or more intermediate components such as switches or transistors.

A switching component (e.g., a transistor) discussed herein may represent a field-effect transistor (FET), and may comprise a three-terminal component including a source (e.g., a source terminal), a drain (e.g., a drain terminal), and a gate (e.g., a gate terminal). The terminals may be connected to other electronic components through conductive materials (e.g., metals, alloys). The source and drain may be conductive, and may comprise a doped (e.g., heavily-doped, degenerate) semiconductor region. The source and drain may be separated by a doped (e.g., lightly-doped) semiconductor region or channel. If the channel is n-type (e.g., majority carriers are electrons), then the FET may be referred to as a n-type FET. If the channel is p-type (e.g., majority carriers are holes), then the FET may be referred to as a p-type FET. The channel may be capped by an insulating gate oxide. The channel conductivity may be controlled by applying a voltage to the gate. For example, applying a positive voltage or negative voltage to an n-type FET or a p-type FET, respectively, may result in the channel becoming conductive. A transistor may be “on” or “activated” when a voltage greater than or equal to the transistor's threshold voltage is applied to the transistor gate. The transistor may be “off” or “deactivated” when a voltage less than the transistor's threshold voltage is applied to the transistor gate.

For example, the various illustrative blocks and modules described in connection with the disclosure herein may be implemented or performed with a processor, such as a DSP, an ASIC, an FPGA, discrete gate logic, discrete transistor logic, discrete hardware components, other programmable logic device, or any combination thereof designed to perform the functions described herein. A processor may be an example of a microprocessor, a controller, a microcontroller, a state machine, or any type of processor. A processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration).