Display device

An embodiment of the present disclosure relates to a display device allowing minimizing repetitive transmissions and receptions of identical pieces of image data so as to reduce power consumption due to the repetitive transmissions and receptions of identical pieces of image data.

CROSS REFERENCE TO RELATED APPLICATION

This application claims priority from Republic of Korea Patent Application No. 10-2019-0096770, filed on Aug. 8, 2019, which is hereby incorporated by reference in its entirety.

BACKGROUND

1. Field of Technology

The present disclosure relates to a display device minimizing repetitive transmissions and receptions of identical pieces of image data.

2. Description of the Prior Art

A display device may comprise a panel, a source driver for driving the panel, and a timing controller for controlling the drive of the source driver. A panel comprises a plurality of pixels forming rows and columns that are disposed side by side in a horizontal direction and in a vertical direction so that the plurality of pixels are placed on the panel in a form of a matrix. A row formed by the plurality of pixels when they are disposed in the horizontal direction may also be referred to as a line.

A source driver may simultaneously drive the plurality of pixels in one line. The plurality of pixels in one line may respectively receive image signals from the source driver through data lines disposed in the vertical direction. The plurality of pixels may display images according to these image signals.

A timing controller may transmit drive control data and image data to the source driver. The timing controller may control timing for the source driver to drive the panel using the drive control data. The source driver may receive image data and generate image signals for driving the panel from the image data.

The process of transmitting image data (image signals) from the timing controller to the panel is equally carried out even when image data of a certain line is identical to image data of a subsequent line. That is, even though pieces of image data of two lines are identical, the identical pieces of image data are repeatedly transmitted. The repetitive transmissions of the multiple pieces of identical image data may cause unnecessary transactions and this may lead to an increase of power consumption and electro-magnetic interference (EMI) of a display device.

SUMMARY

In this background, an aspect of the present disclosure is to provide a technology for re-supplying image data of a previous line to a subsequent line when two pieces of image data of sequentially driven two lines are identical.

Another aspect of the present disclosure is to provide a technology for re-supplying image data of a previous group when multiple pieces of image data of two groups, each comprising a plurality of lines, are identical.

Still another aspect of the present disclosure is to provide a technology in which a re-supply of image data of a previous line or a previous group is carried out by a relevant source driver among a plurality of them.

Still another aspect of the present disclosure is to provide a technology in which a re-supply of image data of a previous line or a previous group is carried out by controlling latches and switches.

To this end, according to an aspect, there is provided a source driver comprising: a drive control circuit to receive a data packet, including a control block and a data block, and to generate a control signal according to the control block; and a latch circuit, comprising a first latch and a second latch, to output image data stored in the first latch or the second latch according to the control signal, wherein, in a case when first image data outputted to a first line is identical to second image data outputted to a second line, data included in the control block commands the second line to reuse the first image data and the data block does not include the second image data.

In the source driver, the data block may embed a clock therein.

In the data block, a part, into which image data is inserted, may have logical levels of 0 only or 1 only or any data.

The source driver may comprise a serial-parallel converting circuit to convert image data received in series into image data in parallel and to output it to the latch circuit; and a clock control circuit to deactivate the serial-parallel converting circuit by masking a clock inputted into the serial-parallel converting circuit according to the control signal.

In the source driver, the latch circuit may comprise a switch connecting the first latch and the second latch and open the switch according to the control signal. The second latch may store the first image data in a first time section where the first line is driven and output the first image data to the second line in a second time section where the second line is driven.

According to another aspect, there is provided a source driver comprising: a drive control circuit to receive a plurality of data packets, each including a control block and a data block and to generate control signals according to the control blocks; and a latch circuit, comprising a first latch and a second latch, to output image data stored in the first latch or the second latch according to the control signals, wherein, in a case when image data for a first group comprising a first line and a second line is identical to image data for a second group comprising a third line and a fourth line, data included in the control block commands the second group to reuse the image data for the first group and the data block does not include the image data for the second group.

In the source driver, the plurality of data packets may include a first data packet comprising a first control block including data to command the third line to reuse image data for the first line and a first data block, and a second data packet comprising a second control block including data to command the fourth line to reuse image data for the second line and a second data block, the drive control circuit may generate a first control signal according to the first control block and a second control signal according to the second control block, and the latch circuit may output the image data for the first line to the third line according to the first control signal and the image data for the second line to the fourth line according to the second control signal.

In the source driver, the latch circuit may comprise a first switch connected with the first latch and a second switch connected with the second latch and output the image data for the first group to the second group by alternately closing the first switch and the second switch.

In the source driver, the first switch may close, the second switch may be connected between the first latch and the second latch so that an output from the second latch may be inputted into the first latch, and the latch circuit may supply image data for the first group to the second group according to the opening or the closing of the second switch.

In the source driver, the first and the second data blocks may respectively embed clocks therein.

In the first and the second data blocks, parts, into which image data is inserted, may have logical levels of 0 only or 1 only or any data.

According to another aspect, there is provided a display device comprising: a panel comprising a plurality of pixels disposed to form lines, the panel being divided into a plurality of areas, each including a first line and a second line; a plurality of source drivers to respectively drive the plurality of areas of the panel; and a timing controller to generate a data packet comprising a control block and a data block for each area and to transmit the data packet to a corresponding source driver, wherein, in a case when first image data outputted to the first line is identical to second image data outputted to the second line in each area, data included in the control block commands the second line to reuse the first image data and the data block does not include the second image data.

In the display device, each source driver may comprise a latch circuit, comprising a first latch and a second latch, to output the first image data to the second line according to a control signal generated on the basis of the control block by the first and the second latches.

In the display device, the timing controller may embed a clock in the data block.

In the data block, a part, into which image data is inserted, may have logical levels of 0 only or 1 only or any data.

In the display device, in a case when image data of a first group including a first line and a second line is identical to image data of a second group including a third line and a fourth line in each area, the timing controller may generate a plurality of data packets for the respective areas, each comprising a control block including data to command the second group to reuse image data for the first group and a data block not including image data, and transmit the plurality of data packets respectively to the corresponding source drivers.

As described above, the present disclosure allows reducing power consumption of a display device by minimizing unnecessary interface transactions due to multiple pieces of identical image data.

In addition, the present disclosure allows reducing EMI due to the unnecessary interface transactions.

DETAILED DESCRIPTION

FIG. 1is a configuration diagram of a display system according to an embodiment.

Referring toFIG. 1, a display device10may comprise a panel11, a source driver12, a gate driver13, and a timing controller14.

On the panel11, a plurality of data lines DL and a plurality of gate lines GL may be disposed and a plurality of pixels P may also be disposed. The plurality of pixels P may be disposed side by side, in a horizontal direction H, and in a vertical direction V so as to form a square shape as a whole. Since this square shape is similar to a matrix shape, a set of a plurality of pixels P arranged in the horizontal direction H or a horizontal line that the plurality of pixels P form may be referred to as a row or a line, and a set of a plurality of pixels P arranged in the vertical direction V or a vertical line that the plurality of pixels P form may be referred to as a column.

The gate driver13may supply scan signals, such as turn-on voltages or turn-off voltages, through the gate lines GL. When a scan signal of a turn-on voltage is supplied to a pixel P, the pixel P is connected with a data line DL, whereas, when a scan signal of a turn-off voltage is supplied to a pixel P, the pixel P is disconnected from the data line DL.

The source driver12may supply data voltages through the data lines DL. A data voltage supplied through a data line DL may be supplied to a pixel P connected with the data line DL according to a scan signal.

The timing controller14may supply various control signals to the gate driver13and the source driver12. The timing controller14may generate a gate control signal GCS to initiate a scan according to a timing for each frame and transmit the gate control signal GCS to the gate driver13. The timing controller14may convert image data inputted from outside into image data RGB in a data format used in the source driver12and transmit the converted image data RGB to the source driver12. In addition, the timing controller14may transmit a data control signal DCS to control the source driver12to supply a data voltage to each pixel P at an appropriate timing.

FIG. 2is a diagram illustrating a conventional data packet.

FIG. 2shows logical levels of image data RGB displayed by pixels of the panel11and data packets including image data RGB.

The timing controller may transmit image data RGB to the source driver and the source driver may generate a data voltage corresponding to the image data RGB and transmit the data voltage to the panel11. In the panel11, greyscale values of 0 to 255 may be outputted to the pixels P using the data voltages. For example, greyscale values (255, 0, 255, 0, 255) may be outputted to a first line201, greyscale values (255, 0, 255, 0, 255) may be outputted to a second line202, greyscale values (255, 255, 0, 255, 255) may be outputted to a third line203, greyscale values (0, 255, 255, 255, 0) may be outputted to a fourth line204, and greyscale values (255, 0, 255, 0, 255) may be outputted to a fifth line205. In the figures of the present disclosure, a black pixel may have a greyscale value of 0 and a white pixel may have a greyscale value of 255.

The timing controller may put image data RGB in a data packet comprising a series of pieces of data and transmit it. The data packet may comprise a control block including a command for controlling the drive of the source driver and a data block including image data RGB. For example, a first data packet PACKET_1for driving the first line201of the panel11may comprise a plurality of control blocks CTR1, CTR2and a data block DATA.

Here, even when image data RGB for a current line is identical to image data RGB for a previous line, the source driver may newly receive image data RGB for the current line, which is identical to image data RGB for the previous line, from the timing controller and drive the panel using the newly received image data RGB. For example, greyscale values outputted to the first line201and the second line202of the panel11may identically be (255, 0, 255, 0, 255). In this case, the timing controller may transmit a second data packet PACKET_2including image data RGB, identical to image data RGB of a first data packet PACKET_1, outputted to the first line201, to the source driver for the drive of the second line202. The source driver drives the second line202using the image data RGB identical to the image data RGB for the first line201. That is, the source driver may output the image data RGB identical to the image data RGB for the first line201to the second line202.

Such an additional data transmission-reception transaction, in other words, an operation, in which the timing controller re-generates image data RGB identical to that for a previous line and the source driver drives the panel11using the same image data RGB, may be unnecessary. Such an unnecessary operation may increase current consumption (power consumption) of a display device and cause electro-magnetic interference (EMI) due to such a transmission-reception.

FIG. 3is a configuration diagram of a timing controller and a source driver according to an embodiment.

Referring toFIG. 3, the timing controller14may comprise a comparator310and a timing control circuit320and the source driver12may comprise a drive control circuit330, a serial-parallel converting circuit340, a latch circuit350, a digital-analog converting circuit (DAC)360, and a buffer370.

The comparator310may determine whether image data for a previous line of the panel is identical to image data for a current line thereof. For example, in a case when image data RGB for the first line201is identical to image data RGB for the second line202as shown inFIG. 2, the comparator310may determine that image data for a previous line is identical to image data for a current line. The comparator310may transmit a result of determination to the timing control circuit320.

The comparator310may respectively compare bits of two pieces of image data. For example, the comparator310may determine if two pieces of image data are identical to each other by applying an exclusive OR operation to bits.

The timing control circuit320may generate a data packet based on a result of determination of the comparator310. A data packet may comprise a control block and a data block. The timing control circuit320may include, in the control block, data for controlling the source driver12to supply again image data, already supplied to a previous line, to a current line, and no data in the data block. A data packet generated by the timing controller14, in a case when multiple pieces of image data of multiple lines are identical, will be specifically described later.

The drive control circuit330may receive a data packet from the timing control circuit320.

The drive control circuit330may generate a control signal using the received data packet and control the latch circuit350by the control signal. The drive control circuit330may generate the control signal on the basis of data included in the data packet. The control signal may include information of controlling the latch circuit350to supply again image data, already supplied to a previous line, to a current line. The control signal may further include a clock transferred to the latch circuit350.

For example, the drive control circuit330may stop or maintain the drive of the latch circuit350by adjusting a clock of a control signal transferred to the latch circuit350. The latch circuit350, which has received the control signal, may be set to supply again image data, already supplied to a previous line, to a current line, store the image data for a previous line, and re-supply the image data to a current line.

In a case when the latch circuit350includes a switch connecting a plurality of latches, the drive control circuit330may stop or maintain the drive of the latch circuit350by controlling the opening and the closing of the switch by a control signal. The switch of the latch circuit350, which has received the control signal, may be set to supply again image data, already supplied to a previous line, to a current line, and the plurality of latches of the latch circuit350may store the image data for a previous line, and re-supply the image data to a current line.

The drive control circuit330may include, in a control signal, a clock transferred to the DAC360and the buffer370. The drive control circuit330may control the operation of the DAC360and the buffer370by adjusting the clock.

The serial-parallel converting circuit340may receive image data transmitted from the timing controller14by the drive control circuit330and convert the image data in a serial form into a parallel form.

The latch circuit350may latch image data. The latch circuit350may temporarily store image data, and then, output it to the DAC360. Specifically, the latch circuit350may comprise a first latch and a second latch. The first latch may temporarily store image data, and then, output it to the second latch according to a clock of a control signal. The second latch may receive the image data from the first latch, temporarily store it, and then, output it to the DAC360according to the clock of the control signal.

The DAC360may receive image data from the latch circuit350. The DAC360may generate an analog image signal by converting the image data. The DAC360may select a greyscale voltage corresponding to image data received from the second latch, among greyscale voltages of 0 to 255 generated from a gamma reference voltage inputted from outside, and output the greyscale voltage to the buffer370. The analog image signal may be the selected greyscale voltage or a data voltage supplied to a data line.

The buffer370may receive an analog image signal from the DAC360. The buffer370may amplify the analog image signal and supply it to a data line.

FIG. 4is a diagram illustrating a data packet according to an embodiment.

In a case when there are adjacent two lines having identical pieces of image data RGB, the timing controller14may control the source driver12to output again a data voltage, already outputted to a previous line, to a current line.

FIG. 4shows structures of data packets generated by the timing controller14in a case when image data RGB for a previous line is identical to image data RGB for a current line. When the timing controller14compares image data RGB for a current line with image data RGB for a previous line and determines that they are identical, the timing controller14may generate a data packet including a command to re-use image data RGB for the previous line without newly transmitting image data RGB.

Supposing that, for example, the panel11displays an image as shown inFIG. 2in a first through a fifth lines of pixels P, greyscale values of image data for the first line201and for the second line202may identically be (255, 0, 255, 0, 255). The timing controller14may include image data RGB for the first line201in a data block DATA to generate a first data packet PACKET_1and transmit the first data packet PACKET_1to the source driver12.

Subsequently, the timing controller14may compare the image data RGB for the second line202with the image data RGB for the first line201before transmitting the image data RGB for the second line202to the source driver12. Since the greyscale values of the image data RGB for the first line201and the second line202are identically (255, 0, 255, 0, 255), the comparator310of the timing controller14may determine that the two pieces of the image data RGB are identical.

The timing control circuit of the timing controller may generate a second data packet PACKET_2according to the aforementioned determination. The timing control circuit may not include the image data RGB for the second line202, which is identical to the image data RGB for the first line, in a data block DATA. The data block DATA may have logical levels of 0 only or 1 only. Or, the data block DATA may have any other data in an arbitrary format.

The timing control circuit may include, in control blocks CTR1, CTR2, command data to re-apply the image data RGB for the first line201to the panel. That is, the command data may comprise information of re-supplying the image data RGB for the first line201to the second line202because the image data RGB for the second line202is identical to the image data RGB for the first line201.

When the comparator determines that the image data RGB for the second line202is different from the image data RGB for the first line201, the timing control circuit may include data different from the image data for the first line201in the data block DATA. The timing control circuit may not include, in the control blocks CTR1, CTR2, command data to re-apply image data RGB for the first line201to the panel. That is, data included in the control blocks CTR1, CTR2may comprise information of supplying image data RGB included in the second data packet PACKET_2to the second line202because the image data RGB for the second line202is different from the image data RGB for the first line201.

FIG. 5is a diagram of a first example illustrating a control block and a data block of a data packet according to an embodiment.

FIG. 5illustrates, according to a first example, in an upper portion, a control block and a data block of a data packet in a case when image data for a previous line and image data for a current line are not identical, and in a lower portion, the control block and the data block of the data packet in a case when image data for a previous line and image data for a current line are identical.

A control block CTR of a data packet may include data for controlling the drive of the source driver. The data may include command data CMD to control the source driver to re-supply image data, already supplied to a previous line, to a current line.

A data block DATA of a data packet may include image data RGB and a clock ECK. The image data RGB may be converted into an analog image signal (a data voltage) and outputted to a pixel P of the panel. A clock ECK, which is a digital signal to synchronize the source driver, may be embedded in a data block DATA together with image data RGB, without being included in a separate block, and transmitted to the source driver.

When image data for a previous line is not identical to image data for a current line, the timing controller may generate a data packet in which a clock ECK and image data RGB are included in a data block DATA as shown in the upper portion.

On the contrary, when image data for a previous line is identical to image data for a current line, the timing controller may only include a clock ECK without image data RGB in a data block DATA as shown in the lower portion. Additionally, the timing controller may include, in the control block CTR, a command to supply again image data for a previous line to a current line. The timing controller may generate a data packet from which image data RGB is excluded.

FIG. 6is a diagram of a second example illustrating a control block and a data block of a data packet according to an embodiment.

FIG. 6illustrates, according to a second example, in an upper portion, a control block and a data block of a data packet in a case when image data for a previous line and image data for a current line are not identical, and, in a lower portion, the control block and the data block of the data packet in a case when image data for a previous line and image data for a current line are identical.

Differently fromFIG. 5, a data block DATA of a data packet may not include a clock ECK. The timing controller may include a clock in a separate block exclusive for the clock without embedding the clock in the data block.

Accordingly, when image data for a previous line is not identical to image data for a current line, the timing controller may generate a data packet including image data RGB without a clock in a data block DATA as shown in the upper portion.

On the contrary, when image data for a previous line is identical to image data for a current line, the timing controller may exclude a clock and image data RGB from the data block. Additionally, the timing controller may include a command CMD to re-supply image data for a previous line to a current line in the control block CTR. In this way, the timing controller may generate a data packet from which image data RGB is excluded.

FIG. 7is a diagram illustrating a first example of controlling a latch to supply image data of a previous line according to an embodiment.

Referring toFIG. 7, according to a first example, the source driver may output image data RGB for a previous line to a current line by controlling the latch circuit350. The latch circuit350may comprise a first latch751and a second latch752.

The drive control circuit330may control states of the first latch751and the second latch752to repeatedly output image data RGB for a previous line to a current line. The first latch751and the second latch752may repetitively output a bit value of image data RGB for a pixel located in a previous line of a certain column (channel) to a pixel located in a current line of the same column (channel).

For example, greyscale values of (0, 255, 255, 255, 0) may be outputted to a first line601and greyscale values of (255, 0, 255, 0, 255) may be outputted to a second to a fifth lines602,603,604,605. Since pieces of image data RGB for the second to fifth lines602,603,604,605are identical, the source driver may repetitively supply image data RGB for the second line602to the third line through the fifth line603,604,605. Taking a column (for example, a second column) as an example as shown in an area A marked in a dotted line, greyscale values of (255, 0, 0, 0, 0) may be outputted respectively to the first line through the fifth line of the second column. The latch circuit350assigned to the second column (the second channel) A may repetitively output a greyscale value of 0, corresponding to image data RGB for the second line602, to the third line through the fifth line603,604,605in the same column.

The drive control circuit330may control the second latch752to repetitively output image data RGB for a previous line to a current line by adjusting a clock supplied to the first latch751and the second latch752. For example, the second latch752may store image data RGB regarding the greyscale value of 0 outputted in the second line602of the second column A. Since a greyscale value for a pixel comprises 8 bits (a first to an eighth bits), the second latch752may store values of 8 bits. As an example, the second latch752may store image data RGB regarding the greyscale value of 0. The second latch752may output the stored image data RGB regarding the greyscale value of 0 according to a control signal generated by the drive control circuit330.

Specifically, the drive control circuit330may receive a data packet from the timing controller and generate a control signal according to data included in a control block of the data packet. The control signal may comprise a first latch clock CLK_L1for driving the first latch751and a second latch clock CLK_L2for driving the second latch752. The drive control circuit330may transfer the first latch clock CLK_L1including a storage signal to the first latch751and the second latch clock CLK_L2including a storage signal to the second latch752. The first latch751may store existing image data RGB without newly receiving any image data RGB (the first latch751in a storing state is represented by shade). Since the second to the fifth lines602,603,604,605have the same image data RGB to be inputted, the first latch751may not newly receive any image data RGB from the drive control circuit330, and thus, no new data may be stored in the first latch751.

The second latch752as well may store only existing image data RGB without newly receiving any image data RGB (the second latch752in a storing state is represented by shade). In this figure, the stored existing image data RGB may be image data RGB regarding the greyscale value of 0 of the second line602in the second column. The second latch752may output the image data RGB, regarding the greyscale value of 0 of the second line602in the second column, to the third to the fifth lines603,604,605of the second column.

According to the first example, the latch circuit350may re-supply image data RGB for the second line602to the third to the fifth lines603,604,605in each of a first to a fifth columns (channels). The latch circuits350for the first, third, and fifth columns (channels) may respectively output repeatedly image data RGB corresponding to a greyscale value of 255 and the latch circuits350for the second and the fourth columns (channels) may respectively output repeatedly image data RGB corresponding to a greyscale value of 0. The source driver may repeatedly output image data RGB for a previous line to a current line without newly receiving the same image data RGB in every column (channel).

FIG. 8is a diagram illustrating a second example of controlling a latch to supply image data of a previous line according to an embodiment.

Referring toFIG. 8, according to a second example, the source driver may output again image data RGB for a previous line to a current line by controlling a latch circuit850. The latch circuit850may comprise a first latch751, a second latch752, a first switch801, and a second switch802.

The first switch801may be connected with the first latch751so as to control the transmission of image data RGB to the first latch751. The drive control circuit330may control the first switch801by a first switching signal CTR_SW1. The first switch801may open or close according to the first switching signal CTR_SW1.

The second switch802may be connected between the first latch751and the second latch752so as to control the transmission of image data RGB from the first latch751to the second latch752. The drive control circuit330may control the second switch802by a second switching signal CTR_SW2. The second switch802may open or close according to the second switching signal CTR_SW2.

The drive control circuit330may repeatedly output image data RGB for a previous line to a current line by controlling the on-off of the first switch801and the second switch802. The first latch751and the second latch752may repeatedly output a bit value of image data RGB of a pixel located in a previous line of a certain column (channel) to a pixel located in a current line of the same column (channel).

For example, in a case when greyscale values of (255, 0, 0, 0, 0) are respectively outputted to the first line601to the fifth line605of a second column in an area A marked by a dotted line, a latch circuit850assigned to the second column (the second channel) A may repeatedly output the greyscale value of 0, which corresponds to image data RGB for the second line602of the second column, to the third line through the fifth line603,604,605of the same column.

The drive control circuit330may control the latch circuit850such that the second latch752repeatedly outputs image data RGB for a previous line to a current line by controlling control signals supplied to the first switch801and the second switch802.

For example, the second latch752may store image data RGB regarding the greyscale value of 0 outputted to the second line602of the second column A Since a greyscale value of a pixel comprises 8 bits (a first to an eighth bits), the second latch752may store values of the 8 bits. In this figure, the second latch752may store image data RGB regarding the greyscale value of 0. The second latch752may output image data RGB regarding the greyscale value of 0 stored according to a control signal generated by the drive control circuit330.

Specifically, the drive control circuit330may receive a data packet from the timing controller and generate a control signal according to data included in a control block of the data packet. A control signal may comprise a first latch clock CLK_L1for driving the first latch751, a second latch clock CLK_L2for driving the second latch752, a first switching signal CTR_SW1for driving the first switch801, and a second switching signal CTR_SW2for driving the second switch802. The drive control circuit330may open the second switch802using the second switching signal CTR_SW2. Then, the first latch751may not output stored image data RGB to the second latch752and the second latch752may maintain the image data RGB for the second line602without being updated. In this way, the second latch752may repeatedly output image data RGB, regarding the greyscale value of 0 of the second line602, to the third line to the fifth line603,604,605.

In addition, the drive control circuit330may block image data RGB from being inputted into the first latch751by opening the first switch801using the first switching signal CTR_SW1.

According to the second example, the latch circuit850may re-supply image data RGB for the second line602to the third through the fifth lines603,604,605in each of a first to a fifth columns (channels). The latch circuits850for the first, third, and fifth columns (channels) may respectively repeatedly output image data RGB corresponding to a greyscale value of 255 and the latch circuits850for the second and the fourth columns (channels) may respectively output repeatedly image data RGB corresponding to a greyscale value of 0. The source driver may repeatedly output image data RGB for a previous line to a current line without newly receiving the same image data RGB in every column (channel).

FIG. 9is a diagram illustrating a data packet according to another embodiment.

In a case when image data RGB varies in every line but the variation is repeated in every certain number of lines, the timing controller may control the source driver to re-output image data for a plurality of previous lines to a plurality of current lines.

FIG. 9shows data packets generated by the timing controller in a case when image data RGB of a plurality of previous lines is identical to image data RGB for a plurality of subsequent lines. When the timing controller compares image data RGB for a plurality of previous lines with image data RGB for a plurality of subsequent lines and determines that they are identical, it may generate a plurality of data packets including commands to re-use image data RGB of a plurality of previous lines for a plurality of subsequent lines. The timing controller may not include image data RGB in the plurality of data packets.

For example, supposing that greyscale values of (255, 0, 255, 0, 255) and (0, 255, 0, 255, 0) are alternately outputted respectively to pixels in a first to a sixth lines901,902,903,904,905,906of the panel11, the greyscale values of image data for a third line and a fourth line903,904and the greyscale values of image data for a first line and a second line901,902may identically be (255, 0, 255, 0, 255/0, 255, 0, 255, 0). The greyscale values of image data for a fifth and a sixth lines and the greyscale values of image data for the first line and the second line901,902may identically be (255, 0, 255, 0, 255/0, 255, 0, 255, 0). The timing controller may generate a first data packet PACKET_1including image data RGB for the first line901in a data block DATA to transmit it to the source driver and generate a second data packet PACKET_2including image data RGB for the second line902in a data block DATA to transmit it to the source driver.

The timing controller may compare image data RGB for the third line and the fourth line903,904with image data RGB for the first line and the second line901,902before transmitting the image data RGB for the third line and the fourth line903,904to the source driver. Since the greyscale values for the third line and the fourth line903,904belonging to a second group and those for the first line and the second line901,902belonging to a first group are identically respectively (255, 0, 255, 0, 255/0, 255, 0, 255, 0), the comparator of the timing controller may determine that the two pieces of image data RGB for the lines respectively belonging to the two groups are identical.

The timing controlling circuit of the timing controller may generate a third data packet PACKET_3according to the aforementioned determination. The timing controlling circuit may not include, in a data block DATA, the image data RGB for the third line903, which is identical to the image data RGB for the first line901. The data block DATA may have logical levels of 0 only or 1 only. Or, the data block DATA may include any other data in an arbitrary format.

The timing controlling circuit may include, in control blocks CTR1, CTR2, command data to re-output image data RGB for the first line901to the third line903. That is, the command data may comprise information that, since the image data RGB for the third line903is identical to the image data RGB for the first line901, the image data RGB for the first line901is re-supplied to the third line903. The timing controlling circuit may or may not include a clock in a data block.

The timing controlling circuit of the timing controller may generate a fourth data packet PACKET_4according to the aforementioned determination. The timing controlling circuit may not include, in a data block DATA, image data RGB for the fourth line904, which is identical to image data RGB for the second line902. The data block DATA may have logical levels of 0 only or 1 only. Or, the data block DATA may include any other data in an arbitrary format.

The timing controlling circuit may include, in control blocks CTR1, CTR2, command data to re-output image data RGB for the second line902to the fourth line904. That is, the command data may comprise information that, since the image data RGB for the fourth line904is identical to the image data RGB for the second line902, the image data RGB for the second line902is re-supplied to the fourth line904. The timing controlling circuit may or may not include a clock in a data block.

If the comparator determines the image data RGB for the first line and the second line901,902is different from the image data RGB for the third line and the fourth line903,904, the timing controlling circuit may include, in the data block DATA of the third data packet PACKET_3, data different from image data RGB for the first line201. In addition, the timing controlling circuit may not include, in the control blocks CTR1, CTR2of the third data packet PACKET_3, command data to re-output the image data RGB for the first line901to the third line903of the panel11. That is, the data included in the control blocks CTR1, CTR2of the third data packet PACKET_3may comprise information that, since the image data RGB for the third line903is different from the image data RGB for the first line901, the image data RGB included in the third data packet PACKET_3is supplied to the third line903.

In addition, if the comparator determines the image data RGB for the first line and the second line901,902is different from the image data RGB for the third line and the fourth line903,904, the timing controlling circuit may include, in the data block DATA of a fourth data packet PACKET_4, data different from the image data RGB for the second line902. In addition, the timing controlling circuit may not include, in the control blocks CTR1, CTR2of the fourth data packet PACKET_4, command data to re-output the image data RGB for the second line902to the fourth line904of the panel11. That is, the data included in the control blocks CTR1, CTR2of the fourth data packet PACKET_4may comprise information that, since the image data RGB for the fourth line904is different from the image data RGB for the second line902, the image data RGB included in the fourth data packet PACKET_4is supplied to the fourth line904.

FIG. 10is a diagram illustrating a first example of controlling a latch to supply image data of a previous line according to another embodiment.

Referring toFIG. 10, the source driver may re-output image data RGB for a plurality of previous lines to a plurality of subsequent lines by controlling a latch circuit1050according to a first example. The latch circuit1050may comprise a first latch1051, a second latch1052, a first switch1001, and a second switch1002.

The first switch1001may be connected with the second switch1002so that image data RGB stored in the first latch1051is outputted to the DAC. The drive control circuit330may control the first switch1001using a first switching signal CTR_SW1. The first switch1001may open or close according to the first switching signal CTR_SW1.

The second switch1002may be connected between the first switch1001and the second latch1052so as to control the output of image data RGB from the second latch1052. The drive control circuit330may control the second switch1002using a second switching signal CTR_SW2. The second switch1002may open or close according to the second switching signal CTR_SW2.

The drive control circuit330may repeatedly output image data RGB for a plurality of previous lines to a plurality of current lines by controlling the states of the first latch1051and the second latch1052and the on-offs of the first switch1001and the second switch1002. The first latch1051and the second latch1052may repeatedly output bit values (0 or 1), of image data RGB for a plurality of pixels located in a plurality of previous lines of a certain column (channel), to a plurality of pixels located in a plurality of subsequent lines of the same column (channel).

For example, greyscale values of (255, 0, 255, 0, 255, 0) may be outputted respectively to a first line901to a sixth line906of a first column, a third column, and a fifth column, and greyscale values of (0, 255, 0, 255, 0, 255) may be outputted respectively to a first line901to a sixth line906of a second column and a fourth column. The latch circuit1050assigned to the first column (the first channel, a dotted line area) B may repeatedly output image data RGB, corresponding to the greyscale values for the first line and the second line901,902of the first column, to the third to the sixth lines903,904,905,906of the same column.

The drive control circuit330may control the latch circuit1050such that the first latch1051and the second latch1052repeatedly output image data RGB, regarding greyscale values for a plurality of previous lines, to a plurality of subsequent lines by controlling control signals supplied to the first latch1051, the second latch1052, the first switch1001, and the second switch1002.

Specifically, the drive control circuit330may receive a plurality of data packets corresponding to the first to the sixth lines901,902,903,904,905,906from the timing controller and generate control signals according to data included in control blocks of the plurality of data packets. A control signal may comprise a first latch clock CLK_L1for driving the first latch1051, a second latch clock CLK_L2for driving the second latch1052, a first switching signal CTR_SW1for driving the first switch1001, and a second switching signal CTR_SW2for driving the second switch1002. The drive control circuit330may control the first and the second latches1051,1052to store image data RGB by the first and the second latch clocks CLK_L1, CLK_L2. The drive control circuit330may alternately perform the opening and closing of the first switch1001using the first switching signal CTR_SW1and the opening and closing of the second switch1002using the second switching signal CTR_SW2. The first latch1051may output stored image data RGB when the first switch1001closes and the second switch1002opens, whereas the second latch1052may output stored image data RGB when the second switch1002closes and the first switch1001opens.

For example, the second latch1052may store image data RGB regarding the greyscale value of 255 of the first line901in the first column B by the second latch clock CLK_L2(the second latch1052in a storing state is represented by shade). The first latch1051may store image data RGB regarding the greyscale value of 0 of the second line902in the first column B by the first latch clock CLK_L1(the first latch1051in a storing state is represented by shade). Since the second latch1052does not newly receive any data, image data RGB of the first latch1051may not be transferred to the second latch1052. Then, when the second switch1002closes and the first switch1001opens, the second latch1052may output image data RGB regarding the greyscale value of 255 to the first line901of the first column B. When the first switch1001closes and the second switch1002opens, the first latch1051may output image data RGB regarding the greyscale value of 0 to the second line902of the first column B. Then, when the second switch1002closes and the first switch1001opens again, the second latch1052may output image data RGB regarding the greyscale value of 255 to the third line903of the first column B. When the first switch1001closes and the second switch1002opens, the first latch1051may output image data RGB regarding the greyscale value of 0 to the fourth line904of the first column B The latch circuit1050may perform the same operation for the fifth and the sixth lines905,906of the first column B.

According to a first example, the latch circuit1050may re-supply image data RGB of the first line and the second line901,902to the third through the sixth lines903,904,905,906in each of a first through a fifth columns (channels). The latch circuits1050for the first, third, and fifth columns (channels) may repeatedly output image data RGB respectively corresponding to the greyscale values of (255, 0) and the latch circuits1050for the second and the fourth columns (channels) may repeatedly output image data RGB respectively corresponding to the greyscale values of (0, 255). The source driver may repeatedly output image data RGB for a plurality of previous lines to a plurality of subsequent lines without newly receiving the same image data RGB in every column (channel).

FIG. 11is a diagram illustrating a second example of controlling a latch to supply image data of a previous line according to another embodiment.

Referring toFIG. 11, the source driver may re-output image data RGB for a plurality of previous lines to a plurality of subsequent lines by controlling a latch circuit1150according to a second example. The latch circuit1150may comprise a first latch1151, a second latch1152, and a switch1101.

The switch1101may be connected with the first latch1151and the second latch1152so that the output from the second latch1152may be inputted to the first latch1151. The switch1101may be connected between the first latch1151and the second latch1152so that the first latch1151and the second latch1152may circulate image data RGB and output it to the DAC. The drive control circuit330may control the switch1101by a switching signal CTR_SW. The switch1101may open or close according to the first switching signal CTR_SW.

The drive control circuit330may repeatedly output image data RGB for a plurality of previous lines to a plurality of current lines by controlling the states of the first latch1151and the second latch1152and the on-off of the switch1101. The first latch1151and the second latch1152may repeatedly output bit values (0 or 1), of image data RGB for a plurality of pixels located in a plurality of previous lines of a certain column (channel), to a plurality of pixels located in a plurality of subsequent lines of the same column (channel).

For example, in a case when greyscale values are outputted to the panel11as shown inFIG. 10, the latch circuit1150, assigned to the first column (the first channel, the dotted line area) B, may repeatedly output image data RGB corresponding to the greyscale values of the first line and the second line901,902in the first column to third to the sixth lines903,904,905,906of the same column.

The drive control circuit330may control the latch circuit1150such that the first latch1151and the second latch1152repeatedly output image data RGB, regarding greyscale values for a plurality of previous lines, to a plurality of subsequent lines by controlling control signals supplied to the first latch1151, the second latch1152, and the switch1101.

Specifically, the drive control circuit330may receive a plurality of data packets corresponding to the first to the sixth lines901,902,903,904,905,906from the timing controller and generate control signals according to data included in control blocks of the plurality of data packets. A control signal may comprise a first latch clock CLK_L1for driving the first latch1151, a second latch clock CLK_L2for driving the second latch1152, and a switching signal CTR_SW for driving the switch1101. The drive control circuit330may control, using the first and the second latch clocks CLK_L1, CLK_L2, the first and the second latches1151,1152to circulate image data RGB between them and output it to the DAC.

The drive control circuit330may control the first latch1151to operate in an enabled state by supplying the first latch clock CLK_L1to the first latch1151. In an enabled state, the first latch1151may operate differently from the storing state. In the enabled state, the first latch1151may not store image data RGB and newly receive image data RGB and output it. The drive control circuit330may enable the second latch1152by supplying the second latch clock CLK_L2to the second latch1152. Then, the second latch1152as well may not store image data RGB and newly receive image data RGB and output it. When the drive control circuit330closes the switch1101by the switching signal CTR_SW, the second latch1152may output second image data, which has been stored therein, simultaneously to the first latch1151and to the DAC through a feedback path to which the switch1101is connected. The first latch1151may output first image data, which has been stored therein, to the second latch1152, receive second image data from the second latch1152, and output the inputted second image data to the second latch1152. The second latch1152may receive the first image data from the first latch1151and output the inputted first image data simultaneously to the first latch1151and to the DAC through the feedback path. When the drive control circuit330opens the switch1101by the switching signal CTR_SW, the drive control circuit330may stop the circulation of image data RGB between the first and the second latches1151,1152.

For example, the second latch1152may receive image data RGB, regarding the greyscale value of 255 of the first line901in the first column B, from the first latch1151in the enabled state by the second latch clock CLK_L2. The first latch1151may receive image data RGB regarding the greyscale value of 0 of the second line902in the first column B in the enabled state by the first latch clock CLK_L1.

When the switch1101closes, the second latch1152may output the image data RGB regarding the greyscale value of 255 of the first line901in the first column B and the first latch1151may output the image data RGB regarding the greyscale value of 0 to the second latch1152at the same time of receiving the image data RGB regarding the greyscale value of 255 from the second latch1152. The second latch1152may receive the image data RGB regarding the greyscale value of 0 from the first latch1151.

In addition, the second latch1152may output the image data RGB regarding the greyscale value of 0 of the second line902in the first column B and the first latch1151may output the image data RGB regarding the greyscale value of 255 to the second latch1152at the same time of receiving the image data RGB regarding the greyscale value of 0 from the second latch1152. The second latch1152may receive the image data RGB regarding the greyscale value of 255 from the first latch1151.

The second latch1152may output the image data RGB regarding the greyscale value of 255 of the third line903in the first column B and the first latch1151may output the image data RGB regarding the greyscale value of 0 to the second latch1152at the same time of receiving the image data RGB regarding the greyscale value of 255 from the second latch1152. The second latch1152may receive the image data RGB regarding the greyscale value of 0 from the first latch1151.

The second latch1152may output the image data RGB regarding the greyscale value of 0 of the fourth line904in the first column B and the first latch1151may output the image data RGB regarding the greyscale value of 255 to the second latch1152at the same time of receiving the image data RGB regarding the greyscale value of 0 from the second latch1152. The second latch1152may receive the image data RGB regarding the greyscale value of 255 from the first latch1151.

The latch circuit1150may perform the same operation for the fifth and the sixth lines905,906of the first column B.

When the switch1101opens, image data RGB does not circulate between the first and the second latches1151,1152, the first and the second latches1151,1152may be in the storing state, in which the first and the second latches1151,1152store image data RGB, by the first and the second latch clocks CLK_L1, CLK_L2.

According to a second example, the latch circuit1150may re-supply image data RGB of the first line and the second line901,902to the third to the sixth lines903,904,905,906in each of a first to a fifth columns (channels). The latch circuits1150for the first, third, and fifth columns (channels) may repeatedly output image data RGB respectively corresponding to the greyscale values of (255, 0) and the latch circuits1150for the second and the fourth columns (channels) may repeatedly output image data RGB respectively corresponding to the greyscale values of (0, 255). The source driver may repeatedly output image data RGB for a plurality of previous lines to a plurality of subsequent lines without newly receiving the same image data RGB in every column (channel).

FIG. 12is a diagram illustrating a plurality of source drivers to separately drive a plurality of areas of a panel and a timing controller to drive the plurality of source drivers according to another embodiment.

Referring toFIG. 12, a display device1200may comprise a timing controller14, a plurality of source drivers1212-1,1212-2,1212-3, and a panel1211comprising a plurality of areas.

The panel1211may be divided into a plurality of areas including area1, area2, and area3. The panel1211is not required to be divided in terms of hardware, but may be divided in terms of software. Each area may comprise a plurality of pixels disposed in a form of a matrix so as to have a plurality of lines (rows) and channels (columns) comprising pixels.

Each of the plurality of source drivers1212-1,1212-2,1212-3may independently drive each area of the panel1211. A first source driver1212-1may independently drive pixels belonging to area1. The first source driver1212-1may supply data voltages corresponding to image data to the pixels by channel in area1. A second source driver1212-2may independently drive pixels belonging to area2. The second source driver1212-2may supply data voltages corresponding to image data to the pixels by channel in area2. A third source driver1212-3may independently drive pixels belonging to area3. The third source driver1212-3may supply data voltages corresponding to image data to the pixels by channel in area3.

In a case when image data for a previous line is identical to image data for a current line, each of the plurality of source drivers1212-1,1212-2,1212-3may supply a data voltage corresponding to image data for a previous line to a current line in the corresponding area. For example, in a case when image data for a first line is identical to image data for a second line in area1, the first source driver1212-1may re-supply a data voltage corresponding to the image data for the first line to the second line. The second source driver1212-2and the third source driver1212-3may perform the same operation respectively in area2and area3. The plurality of source drivers1212-1,1212-2,1212-3may separately perform this operation.

In a case when image data for a plurality of previous lines is identical to image data for a plurality of subsequent lines, each of the plurality of source drivers1212-1,1212-2,1212-3may also re-supply data voltages corresponding to image data for the plurality of previous lines to the plurality of subsequent lines in the respective areas. For example, in a case when image data for a first line and a second line is identical to image data for a third line and a fourth line in area1, the first source driver1212-1may re-supply data voltages corresponding to image data for the first line and the second line to the third line and the fourth line. The second source driver1212-2and the third source driver1212-3may perform the same operation respectively in area2and area3. The plurality of source drivers1212-1,1212-2,1212-3may separately perform this operation.

The timing controller14may separately control each of the plurality of source drivers1212-1,1212-2,1212-3. The timing controller14may control the first source driver1212-1by transmitting a first data packet, control the second source driver1212-2by transmitting a second data packet, and control the third source driver1212-3by transmitting a third data packet. The timing controller14may separately transmit each of the first to the third data packets.

When the timing controller14determines image data for a previous line is identical to image data for a current line, the timing controller14may generate a data packet including command data to repeatedly output image data for a previous line to a current line and transmit it to the plurality of source drivers1212-1,1212-2,1212-3. Each of the plurality of source drivers1212-1,1212-2,1212-3may re-supply a data voltage corresponding to image data for a previous line to a current line in each of area1to area3according to the data packet.

When the timing controller14determines image data for a plurality of previous lines is identical to image data for a plurality of current lines, the timing controller14may generate a data packet including command data to repeatedly output image data for a plurality of previous lines to a plurality of current lines and transmit it to the plurality of source drivers1212-1,1212-2,1212-3. Each of the plurality of source drivers1212-1,1212-2,1212-3may re-supply data voltages corresponding to image data for a plurality of previous lines to a plurality of current lines in each of area1to area3according to the data packet.

Although an embodiment of the present disclosure describes a display device1200comprising three source drivers respectively driving three areas of a panel, the present disclosure is not limited to this, but the numbers of source drivers and areas of a panel may increase or vary.

FIG. 13is a configuration diagram of a timing controller and a source driver according to still another embodiment.

Referring toFIG. 13, a source driver1312may further comprise a clock control circuit1310.

The clock control circuit1310may mask a clock to deactivate a component receiving the clock. For example, the clock control circuit1310may deactivate a serial-parallel converting circuit340by masking (deactivating) a clock inputted from a drive control circuit330into the serial-parallel converting circuit340.

In a case when image data for a previous line is identical to image data for a current line and the source driver1312does not newly receive image data, a latch circuit350may repeatedly supply image data, and thus, the serial-parallel converting circuit340may not necessarily be activated. The drive control circuit330may control the clock control circuit1310to deactivate the serial-parallel converting circuit340using a control signal so as to reduce power consumption due to the serial-parallel converting circuit340. An embodiment of the present disclosure allows reducing total power consumption of a display device by reducing power consumption due to unnecessary functions.

The clock control circuit1310may stop masking operation for a clock to activate a component receiving the clock.