Epitaxial structure of semiconductor device and manufacturing method thereof

An epitaxial structure of semiconductor device includes a substrate, a recess, a first epitaxial layer, a second epitaxial layer, and a third epitaxial layer. The recess is formed in the substrate and disposed near a surface of the substrate, wherein the recess has a recess depth. The first epitaxial layer is disposed on surfaces of a sidewall and a bottom of the recess. The second epitaxial layer is disposed on the surface of the first epitaxial layer, wherein the Ge concentration of the second epitaxial layer is greater than the Ge concentration of the first epitaxial layer. The third epitaxial layer is disposed on the surface of the second epitaxial layer, wherein the Ge concentration of the third epitaxial layer is greater than the Ge concentration of the second epitaxial layer, and the depth of the third epitaxial layer is about ½ to about ¾ of the recess depth.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to an epitaxial structure of semiconductor device and a manufacturing method thereof, more particularly, to an epitaxial structure of semiconductor device with improved strain effect and a manufacturing method thereof.

2. Description of the Prior Art

The semiconductor integrated circuit (IC) industry has experienced rapid growth. In the course of IC evolution, strained source/drain features have been implemented using epitaxial (EPI) semiconductor materials to enhance carrier mobility and improve device performance. For example, when forming a metal-oxide-semiconductor field effect transistor (MOSFET), silicon germanium (SiGe) may be epitaxially grown to form source and drain features. Various techniques directed at shapes, configurations, and materials of these source and drain features have been implemented to further improve transistor device performance. Although many approaches have been developed for their intended purposes, they have not been entirely satisfactory in all respects. For example, in a conventionally formed SiGe bulk structure, the Ge concentration in Ge region is not as high as expectation, and the Ge region with higher concentration has a certain distance to channel region.

SUMMARY OF THE INVENTION

It is one of the objectives of the present invention to provide an epitaxial structure and manufacturing method thereof, wherein the formed epitaxial structure has improved distribution and arrangement of Ge region with high concentration.

According to an embodiment of the present invention, an epitaxial structure of semiconductor device is provided. The epitaxial structure of semiconductor device includes a substrate, a recess, a first epitaxial layer, a second epitaxial layer, and a third epitaxial layer. The recess is formed in the substrate and disposed near a surface of the substrate, wherein the recess has a recess depth. The first epitaxial layer is disposed on surfaces of a sidewall and a bottom of the recess. The second epitaxial layer is disposed on the surface of the first epitaxial layer, wherein the germanium (Ge) concentration of the second epitaxial layer is greater than the Ge concentration of the first epitaxial layer. The third epitaxial layer is disposed on the surface of the second epitaxial layer, wherein the Ge concentration of the third epitaxial layer is greater than the Ge concentration of the second epitaxial layer, and the depth of the third epitaxial layer is about ½ to about ¾ of the recess depth.

According to an embodiment of the present invention, a manufacturing method of an epitaxial structure is further provided. The manufacturing method includes providing a substrate, wherein a recess is disposed in the substrate near a surface of the substrate; forming a first epitaxial layer on surfaces of a sidewall and a bottom of the recess; forming a second epitaxial layer on a surface of the first epitaxial, wherein a germanium (Ge) concentration of the second epitaxial layer is greater than a Ge concentration of the first epitaxial layer; performing an etching back process to remove a portion of the second epitaxial layer to form a cave in the recess; and forming a third epitaxial layer in the cave, wherein a Ge concentration of the third epitaxial layer is greater than the Ge concentration of the second epitaxial layer.

Base on the disclosure of the present invention, it is an advantage that a cave is formed before forming the third epitaxial layer with high Ge concentration such that the sequentially formed third epitaxial layer can fill the cave to have a large top area and is arranged adjacent to the channel region, which efficiently improve the strain effect.

DETAILED DESCRIPTION

To provide a better understanding of the present invention to the skilled users in the technology of the present invention, preferred embodiments will be detailed as follows. The preferred embodiments of the present invention are illustrated in the accompanying drawings with numbered elements to elaborate on the contents and effects to be achieved.

Please refer toFIG. 1toFIG. 6andFIG. 9.FIG. 1toFIG. 6are schematic diagrams illustrating the manufacturing method of an epitaxial structure according to a first embodiment of the present invention, which also illustrate the cross-sectional views of the epitaxial structure.FIG. 9is a schematic diagram illustrating the process flow of the manufacturing method of an epitaxial structure according to the present invention. First, as shown inFIG. 1andFIG. 9, the step S1is performed to provide a substrate100, wherein a recess102is disposed in the substrate100near the surface100aof the substrate100. The substrate100may be a semiconductor substrate (such as a silicon substrate), a silicon containing substrate (such as a silicon carbide substrate), an III-V group-on-silicon (such as GaN-on-silicon) substrate, a graphene-on-silicon substrate, a silicon-on-insulator (SOI) substrate or an epitaxial layer containing substrate, but not limited thereto. The formation of the recess102may comprise one or more etching process, including but not limited to a dry process such as a plasma etching process, a wet etching process, or a combination of both. For example, an etchant such as carbon tetrafluoride (CF4), HF, tetramethylammonium hydroxide (TMAH), or combinations of thereof, or the like may be used to perform the wet etch process, so as to form the recess102. The formed recess102has a recess depth D1which is, but not limited to, about 500-1000 angstroms in this embodiment.

In addition, two gate structures104are selectively formed on the surface100aof the substrate100, wherein each of the gate structures104includes a gate insulating layer1041disposed on the surface100aof the substrate100, a gate portion1042disposed above the dielectric layer1041, and a spacer1043surrounding the gate portion1042. In this embodiment, the recess102is formed in the source/drain region near the gate structures104. More specifically, the formed recess102is disposed between the two adjacent gate structures104. The gate insulating layer1041may be composed of dielectric material such as oxides or nitrides, but not limited thereto. The gate insulating layer1041could also be composed of pad oxide or a high-k dielectric layer composed of HfSiO, HfSiON, HfO, LaO, LaAlO, ZrO, ZrSiO, or HfZrO. The gate portion1042may be a silicon layer including an amorphous silicon layer, a polysilicon layer, a single silicon layer with doped silicon layer, or a composite silicon layer with combination of aforementioned silicon layers. The gate portion1042may also include metal materials or be composed of metal layer and other functional or optional layers (not shown), such as work function layer(s) and barrier layer(s). In addition, a cap layer (not shown) may be selectively disposed on the gate portion1042. The spacer1043can be a single layer or a composite layer, which may be composed of high temperature oxide (HTO), silicon nitride, silicon oxide or silicon nitride (HCD-SiN) formed by hexachlorodisilane (Si2Cl6), but not limited thereto.

Next, the step S2is performed to form a first epitaxial layer106on surfaces of the sidewall and the bottom of the recess102. The first epitaxial layer106has a low Ge concentration, which is less than and equal to 30%, or less than and equal to 25%. The Ge concentration of the whole first epitaxial layer106may be substantially fixed to a certain value or to a certain range uniformly, such as ranging from 25% to 30%, but not limited thereto. However, the first epitaxial layer106may have a gradient Ge concentration upwardly increased. For example, the Ge concentration of the first epitaxial layer106may be upwardly increased from about 0% to about 30%. A selective epitaxial growth (SEG) process may be carried out to form the first epitaxial layer106. The SEG process may include, but not limited to, a low pressure chemical vapor deposition (LPCVD) process. For example, the SEG process can use dichlorosilane (SiH2Cl2, DCS) as a silicon source, germane (GeH4) as a germanium source, HCl or Cl2as an etchant to provide selectivity during the deposition and hydrogen (H2) as a carrier gas, so as to control selective growth. However, in other embodiments, deposition and etching processes may be separately and independently performed in separate processing steps.

Sequentially, as shown inFIG. 9andFIG. 2, the step S3is executed to form a second epitaxial layer108on the surface of the first epitaxial layer106. The second epitaxial layer108is a bulk epitaxial layer and is directly in contact with the first epitaxial layer106, and the bottom boundary106aof the first epitaxial layer106and the second epitaxial layer108is positioned around ⅔ of the recess depth D1as an example. The second epitaxial layer108formed in the step S3of forming the second epitaxial layer108substantially fills the recess102. The Ge concentration of the second epitaxial layer108is greater than the Ge concentration of the first epitaxial layer106. It should be noted that second epitaxial layer106has a gradient Ge concentration upwardly increased. Preferably, the Ge concentration of the second epitaxial layer108is greater than about 30% and less than about 45% or about 40%. For example, the second epitaxial layer108may include at least three portions according to different ranges of Ge concentration: the first portion1081, the second portion1082, and the third portion1083, but not limited thereto. The first portion1081has a Ge concentration ranges from about 30% to about 35% and is positioned on the surface of the first epitaxial layer106. The second portion1082has a Ge concentration ranges from about 35% to about 40% and is positioned on the surface of the first portion1081. The third portion1083has a Ge concentration ranges from about 40% to about 45% and is positioned on the surface of the second portion1082. Specifically, the first portion1081, the second portion1082, and the third portion1083are arranged as a part of three concentric circles, which means the first portion1081surrounds the lower side of the second portion1082, and the second portion1082surrounds the lower side of the third portion1083. The formation of the second epitaxial layer108can include a SEG process, which may adopt the same precursor, material source, and etchant and other process parameters as the formation of the first epitaxial layer106. It should be noted that since the Ge concentration of the second epitaxial layer108is increased gradient, the flow ratio of the source of Ge to the source of Si may be advanced by steps, for instance. In various embodiments, the second epitaxial layer108has a linear distribution of Ge concentration, wherein the boundaries between the first, second, and third portions1081,1082, and1083cannot be clearly defined.

Then, referring toFIG. 3andFIG. 9, the step S4is executed to perform an etching back process114to remove a portion of the second epitaxial layer108in order to form a cave116in the recess102. In this embodiment, the sectional cross-sectional profile of the cave116preferably is a V-shaped structure, but not limited thereto. The etching back process114includes a dry etching process, a wet etching process, or combination thereof. In addition, the etching back process114is controlled and tuned to ensure removal of the certain portion of the second epitaxial layer108in order to obtain a preferable shape of the cave116. For example, etching parameters of the dry and/or wet etching processes can be tuned, such as etchants, etching temperature, etching solution concentration, etching pressure, source power, RF bias voltage, RF bias power, etchant flow rate, and other suitable parameters. In this embodiment, the etching back process114is a dry etching process that uses a chlorine-containing gas, such as HCl, Cl2, other chlorine-containing gases, or a combination thereof. However, other etchant may also be used in the dry etching process, such as a fluorine-containing gas (such as HF, NF3, SF6, CF4, other fluorine-containing gases, or combinations thereof), a silicon-containing gas (such as DCS, SiCH3, other silicon-containing gas, or a combination thereof), other gas, or a combination thereof. In a preferred embodiment, HCl is used as the etchant because of that HCl may be also used during the SEG processes in the formation of the first epitaxial layer106and the formation of the second epitaxial layer108, such that the etching back process114can be in-situ performed with the aforementioned SEG processes, in the same chamber of forming the epitaxial layers. Preferably, the etching back process114is continuously executed until the opening fringe of the cave116(as marked by the dotted circles) is close to the opening fringe of the recess102, which means the top opening of the cave116reaches the gate structures104and close to the channel regions below the gate structures104. Alternatively, the etching back process114can be continuously carried out until the depth D3of the cave116reaches about ½ of the recess depth D1to about ¾ of the recess depth D1, wherein the depth D3of the cave116can be defined by the distance of the lowest point of the V-shaped structure and the top surface100aof the substrate100. It should be noted that the third portion1083of the second epitaxial layer108is substantially removed and the upper part of the second portion1082and the first portion1081of the second epitaxial layer108near the gate structures104are also removed in the etching back process114. The remained second epitaxial layer is numbered as108′, composed of the residual first portion1081and second portion1082.

Then, as shown inFIG. 4andFIG. 9, the step S5is performed to form a third epitaxial layer118in the cave116, wherein the Ge concentration of the third epitaxial layer118is greater than the Ge concentration of the second epitaxial layer108. Preferably, the third epitaxial layer118fully fills the cave116and has a fixed high Ge concentration ranges from about 40% to about 45%. The composition concentration of the third epitaxial layer118may be uniform in this embodiment. The formation method and parameters of the third epitaxial layer118may be referred to the aforementioned paragraphs of the formation of the first epitaxial layer106and the second epitaxial layer108, thus redundant description will not be repeated herein. After the formation of the third epitaxial layer118, the manufacture of the epitaxial structure110of semiconductor device according to the present invention is completed. Therefore, the epitaxial structure110of semiconductor device according to the present invention includes a substrate100, a recess102, a first epitaxial layer106, a second epitaxial layer108′, and a third epitaxial layer118. The recess102is formed in the substrate100and disposed near the surface100aof the substrate, wherein the recess102has a recess depth D1. The first epitaxial layer106is disposed on surfaces of the sidewall and the bottom of the recess102. The second epitaxial layer108′ is disposed on the surface of the first epitaxial layer106, wherein the Ge concentration of the second epitaxial layer108′ is greater than the Ge concentration of the first epitaxial layer106. In addition, the third epitaxial layer118is disposed on the surface of the second epitaxial layer108′, wherein the Ge concentration of the third epitaxial layer118is greater than the Ge concentration of the second epitaxial layer108′, and the depth D3of the third epitaxial layer118is about ½ to about ¾ of the recess depth D1.

According to the present invention, since the third epitaxial layer118with the highest and fixed Ge concentration fully fills the cave116, the boundary108abetween the top portion of the third epitaxial layer118and the second epitaxial layer108is close to the opening fringe of the recess102. Therefore, the third epitaxial layer118with high Ge concentration has a large top area covering a portion of the substrate100that is positioned between the gate structures104and is in contact with the channel region positioned below the gate structures104, such that the strain of channel can be effectively improved. In addition, since most part of the third epitaxial layer118is deposited on the second portion1082with a medium range of Ge concentration, not the first portion1081of the second epitaxial layer108, the third epitaxial layer118with high Ge concentration can be formed with good crystalline structure, without dislocation and stacking fault. Moreover, the V-shaped cave116also provides an advantage to further avoid dislocation when depositing the third epitaxial layer118.

In addition, after the formation of the third epitaxial layer118of the present invention, a SiGe cap layer and a doped silicon cap (Si-cap) layer may be further formed on the third epitaxial layer118. Referring toFIG. 5, the SiGe cap layer122is deposited on the third epitaxial layer118, wherein the Ge concentration of the SiGe cap layer122may be decreased upwardly in gradient from about 40% or 45% to about 0%, for instance. In this situation, the SiGe cap layer122may have a linear distribution of Ge concentration from bottom to top. Then, as shown inFIG. 6, a Si-cap layer124is formed to cover the SiGe cap layer122, wherein the Si-cap layer124may be doped with dopants such as boron. The SiGe cap layer122and the Si-cap layer124may be deposited through CVD processes, but not limited thereto. After the formation of the Si-cap layer124, other fabrication processes of semiconductor device may be further performed.

The epitaxial structure of semiconductor device of the present invention and the manufacturing method thereof are not limited by the aforementioned embodiment, and may have other different preferred embodiments. To simplify the description, the identical components in each of the following embodiment are marked with identical symbols. For making it easier to compare the difference between the embodiments, the following description will detail the dissimilarities among different embodiments and the identical features will not be redundantly described.

Please refer toFIG. 7andFIG. 8.FIG. 7andFIG. 8are schematic diagrams illustrating the manufacturing method of an epitaxial structure according to a second embodiment of the present invention, whereinFIG. 7shows the profile of the epitaxial structure following the process illustrated inFIG. 2. As shown inFIG. 7, this embodiment is different from the first embodiment in that the cave116′ formed during the etching back process (not shown inFIG. 7andFIG. 8) has a profile of U-shaped structure in sectional view. The depth D4of the U-shaped cave116′ is about ½ to about ¾ of the recess depth102. With reference toFIG. 8, after forming the cave116′, the third epitaxial layer118is deposited to fully fill the cave116′, and the SiGe cap layer122and the Si-cap layer may be optionally formed on the third epitaxial layer118. Therefore, the third epitaxial layer118of the epitaxial structure110in the second embodiment of the present invention has a U-shaped boundary. Similarly, the top part of the third epitaxial layer118has a large area near the channel region, and the strain effect can also be improved.

To summarize, the present invention provides an epitaxial structure of semiconductor and a manufacturing method thereof that can improve the strain effect for the cannel region by the way of forming a cave after the deposition of SiGe bulk with a gradient Ge concentration and filling the cave with the third epitaxial layer having fixed high Ge concentration. As a result, the third epitaxial layer has a large top area and is very close to the channel region located below the gate structures, so as to gain the expected strain effect. In addition, since the etchant of the etching back process that forms the cave can adopt HCl and/or Cl2which may be already used in the deposition process of epitaxial process, the etching back process may be in-situ performed with the deposition process of epitaxial layers. Accordingly, the total fabrication process is very simple without extra process cost and procedures in comparison with prior-art process.