Method and system for mitigating risk of electrostatic discharge for a system on chip (SOC)

Aspects of a method and system for mitigating risk of electrostatic discharge in a system on chip are provided. In this regard, for an IC comprising a plurality of portions electrically isolated from one another within the IC, ESD current may be routed via one or more paths within and/or on a package to which the IC is bonded. The one or more paths may electrically couple two or more of the portions of the IC. The one or more paths may have low impedance at DC and high impedance at one or more frequencies utilized in the integrated circuit. One of the portions of the IC may be a ground plane for RF circuitry. One of the portions of the IC may be a ground plane for digital circuitry. The one or more paths may be fabricated in one or more metal layers of said package.

FIELD OF THE INVENTION

Certain embodiments of the invention relate to integrated circuits. More specifically, certain embodiments of the invention relate to a method and system for mitigating risk of electrostatic discharge in a system on chip (SoC).

BACKGROUND OF THE INVENTION

Electrostatic discharge (ESD) is the rapid transfer of electric charge between two objects. ESD often results from two objects of different electric potentials being brought into sufficient proximity of one another. An ESD event can critically and irreparably damage integrated circuits. For example, an ESD event may result in dielectric breakdown and/or fusing in one or more circuit elements, often resulting in permanently shorted and/or permanently open circuits. systems with some aspects of the present invention as set forth in the remainder of the present application with reference to the drawings.

BRIEF SUMMARY OF THE INVENTION

A system and/or method is provided mitigating risk of electrostatic discharge in a system on chip (SoC), substantially as shown in and/or described in connection with at least one of the figures, as set forth more completely in the claims.

DETAILED DESCRIPTION OF THE INVENTION

Certain embodiments of the invention may be found in a method and system for mitigating risk of electrostatic discharge in a system on chip (SoC). In various exemplary embodiments of the invention, for an IC comprising a plurality of portions electrically isolated from one another within the IC, ESD current may be routed via one or more paths within and/or on a package to which the IC is bonded. The one or more paths may electrically couple two or more of the portions of the IC. The one or more paths may have low impedance at DC and high impedance at one or more frequencies utilized in the IC. One of the portions of the IC may be a ground plane for RF circuitry. One of the portions of the IC may be a ground plane for digital circuitry. The one or more paths may be selected based on the one or more frequencies utilized in the IC. The one or more paths may be selected based on a maximum tolerable resistance of the one or more paths. The maximum tolerable resistance may be determined based on a minimum voltage and/or current which the packaged integrated circuit may be expected to tolerate without damage. The one or more paths may be selected based on a minimum tolerable inductance of the one or more paths. The minimum tolerable inductance may be determined based on the one or more frequencies utilized in the integrated circuit. The one or more paths may comprise one or more turns. The one or more paths may be fabricated in one or more metal layers of the IC package.

FIG. 1Ais diagram illustrating an exemplary integrated circuit, in connection with an embodiment of the invention. Referring toFIG. 1A, the integrated circuit (IC)102may comprise an RF portion104and a digital portion106which share a ground plane108.

The RF portion104may comprise suitable logic, circuitry, and/or code that may be operable to process analog signals. In various exemplary embodiments of the invention, the RF portion104may comprise one or more amplifiers, mixers, filters, and analog to digital converters.

The digital portion106may comprise suitable logic, circuitry, and/or code that may be operable to process digital signals. In various exemplary embodiments of the invention, the digital portion106may comprise one or more baseband processors, digital signal processors (DSP), and memory elements.

In operation, the digital circuitry106may switch rapidly between at or near a negative voltage rail and at or near a positive voltage rail. This behavior may provide substantial noise margin for the digital circuitry106, but the sharp signal transitions of the digital circuitry106may also generate significant amounts of noise. Consequently, the RF circuitry104, which may be more susceptible to noise due, for example, to low signal amplitudes, may be negatively impacted by the noise from the digital circuitry106. In this regard, noise from the digital circuitry106may be coupled into the RF circuitry104via the ground plane108.

FIG. 1Bis a diagram illustrating an exemplary integrated circuit, in connection with an embodiment of the invention. Referring toFIG. 1B, the IC122may comprise an RF portion104, a digital portion106, an RF ground plane124, and a digital ground plane126.

The IC122may be similar to the IC102described with respect toFIG. 1Awith the difference being that the common ground108of the IC102may be replaced with separate ground planes124and126for the RF portion104and the digital portion106, respectively.

In operation, the electrical isolation between the RF ground plane124and the digital ground plane126may reduce the amount of noise coupled from the digital portion106to the RF portion104. However, the electrical isolation between the RF ground plane124and the digital ground plane126may result in a voltage differential arising between separate portions of the IC122and/or between portions of the IC122and external circuits and/or objects. Accordingly, the IC122may be more susceptible to an ESD event than the IC102ofFIG. 1A.

FIG. 1Cis a diagram of an exemplary integrated circuit, in accordance with an embodiment of the invention. Referring toFIG. 1C, there is shown an IC142, bonded to an IC package144. The IC142may be similar to the IC122described with respect toFIG. 1B, with the difference being that the RF ground plane124and the digital ground plane126in the IC142may be electrically coupled via an ESD risk mitigating connection146within and/or on the IC package144.

In operation, the connection146may provide a low impedance DC path between the RF ground plane124and the digital ground plane126while simultaneously providing a high impedance AC path between the RF ground plane124and the digital ground plane126. The low DC impedance of the connection146may prevent or reduce a difference in electric potential which may develop between separate portions of the IC142and/or between portions of the IC142and external circuits and/or objects. The high AC impedance of the connection146may prevent or reduce noise coupled between the RF portion104and the digital portion106.

Fabricating the connection146in the IC package144may enable efficiently realizing a relatively high inductance and low resistance. In this regard, realizing the connection146in the IC package144may be less costly, in terms of space and/or dollars, than implementing the connection146on-chip or as an external component. Additionally, fabricating the connection146in the IC package144may enable tighter control of tolerances as compared to, for example, a discrete component. Furthermore, fabricating the connection in the IC package144may prevent the need to have two pins of the package144dedicated for coupling the RF ground plane124and the digital ground plane126externally.

AlthoughFIG. 1Cdepicts the connection146electrically coupling an RF ground124and a digital ground plane126, the invention is not so limited. In this regard, the connection146may be utilized to electrically couple any two portions of an integrated circuit between which low DC impedance and high AC impedance may be desirable.

FIG. 2Aillustrates a cross section of an exemplary IC bonded to a package comprising a connection for mitigating the risk of an ESD event, in accordance with an embodiment of the invention. Referring toFIG. 2Athere is shown an IC202comprising an RF ground plane204and a digital ground plane206. The IC202may be bonded to an IC package228via a plurality of bond wires208. The bond wires208may be coupled to one or more metal layers210of the IC package228by a layer of nickel plating230and a layer of gold plating232. The various metal layers210may be interconnected by one or more vias222and/or plated through holes (PTH)218. The IC package228may be communicatively coupled to one or more external components by one or more solder balls226. The RF ground plane204and the digital ground plane206may be electrically coupled by an ESD mitigating connection220realized in one or more of the metal layers210. The ESD mitigating connection220may comprise one or more bond wires208, vias222, plated through holes218, and/or traces224in the metal layers210

The IC202may be similar to or the same as the IC142described with respect toFIG. 1C. The RF ground plane204may be similar to or the same as the RF ground plane124described with respect toFIGS. 1A-1C. The digital ground plane206may be similar to or the same as the digital ground plane126described with respect toFIGS. 1A-1C. The IC package228may be similar to or the same as the IC package144described with respect toFIG. 1C. Although, the package228comprises four metal layers, the invention is not so limited and any number of metal layers may be present in the IC package.

In operation, the inductance of the connection220may provide noise isolation between the RF ground plane204and the digital ground plane206. Fabricating the connection220in the IC package228, as opposed to in the IC202, may enable a higher inductance connection and may thus improve noise isolation between RF circuitry and digital circuitry. Additionally, placing the connection220in the package228may enable the connection220to be physically closer to, for example, chassis or earth ground. In this regard, in the event of an ESD event, large currents may be diverted away from the IC202.

In the exemplary embodiment of the invention depicted inFIG. 2A, the connection220comprises a single path from the digital GND206to the RF GND294, however the invention is not so limited. In this regard, the connection220may comprise a plurality of paths which may be realized in the one or more metal layers210of the IC package228. Additionally, in various embodiments of the invention, the paths may be selected via more switching elements (not shown) in the IC202and/or within and/or on the package228. Selecting different paths may enable configuring an inductance and/or resistance of the connection220. Accordingly, the paths may be configured to adjust the inductance and/or resistance of the connection220based on one or more frequencies utilized by one or more circuits of the IC202.

FIG. 2Bis a diagram illustrating an ESD mitigating connection comprising a plurality of paths selectable via one or more switching elements, in accordance with an embodiment of the invention. Referring toFIG. 2Bthere is shown an ESD connection220comprising paths2541, . . . ,254N. A first end of each of the paths254may be coupled to the digital GND206via a switch252. A second end of each of the paths254may be coupled to the RF GND206. Each of the paths2541, . . . ,254Nmay comprise, for example, one or more bond wires, one or more vias in the IC or the package, one or more PTH in the IC package, and/or one or more traces in the metal layers of the IC package.

In operation, the switches2521, . . . ,252Nmay be configured to select one or more of the paths2541, . . . ,254N. In this regard, the inductance and/or resistance of the connection220may vary based on the configuration of the switches2521, . . . ,252N. In various exemplary embodiments of the invention, one or more of the paths2541, . . . ,254Nmay be selected based on a mode of operation of the IC. In various exemplary embodiments of the invention, one or more of the paths2541, . . . ,254Nmay be selected based on a desired inductance and/or resistance of the connection220. For example, the paths may be configured based on a maximum tolerable resistance of the connection220which may provide acceptable ESD protection and/or based on a minimum tolerable inductance of the connection220which may provide acceptable noise isolation. In regards to ESD, the maximum resistance may be determined based on, for example, a minimum transient voltage and/or current which the IC202may be expected to withstand. In regards to noise, frequencies utilized within the IC202may determine sensitive and/or noisy frequencies.

FIG. 3illustrates an exemplary layout of a path in an IC package for electrically coupling two portions of an IC to mitigate ESD risk, in accordance with an embodiment of the invention. Referring toFIG. 3, the path302may comprise an exemplary realization of the connection220described with respect toFIG. 2. In various embodiments of the invention, the path302may be the sole path of an ESD mitigating connection or may be one or a plurality of paths of an ESD mitigating connection. Although the exemplary path302comprises a single trace304, via222a, and via222b, the invention is not so limited. For example, other exemplary paths may comprise other components such as additional traces, one or more plated through holes, additional vias, and/or one or more bond wires or solder bumps. In this regard, a size, a shape, and/or components of the path302may be based on desired inductance, capacitance, and/or resistance of the path302. Additionally, the size, shape, and/or components of the path302may be based on available space in an IC package in which the path302is fabricated. In various embodiments of the invention, the path302may comprise one or more turns to increase its inductance.

FIG. 4is a flow chart illustrating mitigation of an ESD event via a connection in an IC package, in accordance with an embodiment of the invention. Referring to FIG.4, the exemplary steps may begin with step402when a charge imbalance may develop between a packaged IC and its surroundings. Subsequent to step402, the exemplary steps may advance to step404. In step404, an electrostatic discharge may occur when the IC package touches it surroundings or when the imbalance becomes large enough to arc. The ESD may suddenly cause a large amount of current to flow between the surroundings and the IC as the charge seeks a ground path. Subsequent to step404, the exemplary steps may advance to step406. In step406, the ESD current may be routed to ground via an ESD mitigating connection fabricated in the IC package. In this manner, the ESD current may be routed to ground without traversing and/or damaging the IC.

FIG. 5is a flow chart illustrating exemplary steps for selecting one or more paths for an ESD mitigating connection, in accordance with an embodiment of the invention. Referring toFIG. 5, the exemplary steps may begin with step502when one or more frequencies utilized in an IC may be measured and/or otherwise determined. Subsequent to step502, the exemplary steps may advance to step504. In step504, a desired inductance and/or resistance of an ESD mitigating connection may be determined based on the frequencies determined in step502. Subsequent to step504, the exemplary steps may advance to step506. In step506, one or more switches, such as the switches252described with respect toFIG. 2B, may be configured to select one or more paths to achieve (within a tolerance) the inductance and/or resistance determined in step504.

Exemplary aspects of a method and system for mitigating risk of electrostatic discharge in a system on chip are provided. In an exemplary embodiment of the invention, for an IC202comprising a plurality of portions electrically isolated from one another within the IC, ESD current may be routed via one or more paths254within and/or on a package228to which the IC202is bonded. The one or more paths254may electrically couple two or more of the portions of the IC. The one or more paths254may have low impedance at DC and high impedance at one or more frequencies utilized in the IC202. One of the portions of the IC202may be a ground plane204for RF circuitry. One of the portions of the IC may be a ground plane206for digital circuitry. The one or more paths254may be selected based on the one or more frequencies utilized in the IC202. The one or more paths254may be selected based on a maximum tolerable resistance of the one or more paths254. The maximum tolerable resistance may be determined based on a minimum voltage and/or current which the packaged integrated circuit may be expected to tolerate without damage. The one or more paths254may be selected based on a minimum tolerable inductance of the one or more paths254. The minimum tolerable inductance may be determined based on the one or more frequencies utilized in the integrated circuit202. The one or more paths254may comprise one or more turns. The one or more paths254may be fabricated in one or more metal layers210of the package228.