Memory system and method for operating a memory system

A memory system, in particular a buffered memory system, e.g., a fully buffered memory system, a method for operating a memory system, and a device for use with a memory system is disclosed. The memory system may include a first buffered memory module, and a second buffered memory module, wherein the first and the second buffered memory modules are adapted to be accessed in parallel. According to a further embodiment of the invention, a device is provided which is adapted to map consecutive accesses to the first or the second memory module to a parallel access of both the first and the second memory module.

BACKGROUND

The invention relates to a memory system, in particular a buffered memory system, e.g., a fully buffered memory system, a method for operating a memory system, and a device for use with a memory system.

In the case of conventional memory devices, in particular conventional semiconductor memory devices, one differentiates between functional memory devices (e.g., PLAs, PALs, etc.), and table memory devices, e.g., ROM devices (ROM=Read Only Memory—in particular PROMs, EPROMs, EEPROMs, flash memories, etc.), and RAM devices (RAM=Random Access Memory—in particular e.g., DRAMs and SRAMs).

A RAM device is a memory for storing data under a predetermined address and for reading out the data under this address later. In the case of SRAMs (SRAM=Static Random Access Memory), the individual memory cells consist e.g., of few, for instance 6, transistors, and in the case of DRAMs (DRAM=Dynamic Random Access Memory) in general only of one single, correspondingly controlled capacitive element.

In many applications, several DRAMs are arranged on a single, separate memory module, e.g., a separate memory card. Further, several of such memory modules—each having several DRAMs—may be connected to a respective microprocessor or memory controller via a bus system. However, the higher the number of memory modules/DRAMs connected to the microprocessor/memory controller, and the higher the data rate, the worse the quality of the signals exchanged between the memory modules/DRAMs, and the microprocessor/memory controller.

For this reason, “buffered” memory modules are used, e.g., registered DIMMs. Buffered memory modules include—in addition to several DRAMs—one or several buffer components, receiving the signals from the microprocessor/memory controller, and relaying them to the respective DRAM (and vice versa). Hence, the respective memory controller only needs to drive one capacitive load per DIMM on the bus.

To further enhance the data rate, and/or the number of memory modules which may be connected to a respective microprocessor/memory controller, FBDIMMs (Fully Buffered DIMMs) are used.

FIG. 1illustrates a memory system1with FBDIMMs2a,2b,2c(Fully Buffered DIMMs). In the memory system1illustrated inFIG. 1, up to eight memory cards/FBDIMMs2a,2b,2cper channel may be connected to a microprocessor/memory controller4. Each FBDIMM2a,2b,2cincludes a buffer component5a,5b,5c, and several DRAMs3a,3b,3c(for sake of simplicity, inFIG. 1only one DRAM per memory card/FBDIMM2a,2b,2cis illustrated). The FBDIMMs2a,2b,2cmay e.g., be plugged into corresponding sockets of a motherboard, which e.g., also includes the above microprocessor/memory controller4.

As is illustrated inFIG. 1, the microprocessor/memory controller4may be connected to a first FBDIMM2aof the FBDIMMs2a,2b,2cvia a first bus6a, having a first channel (“South-bound channel” (SB channel)), and a second channel (“north-bound channel” (NB channel)). The SB channel of the bus6ais used to send respective address, command, and data signals from the microprocessor/memory controller4to the buffer component5aof the first FBDIMM2a. Correspondingly similar, the NB channel of the bus6ais used to send respective signals from the buffer component5aof the first FBDIMM2ato the microprocessor/memory controller4.

As is further illustrated inFIG. 1, the first FBDIMM2aof the FBDIMMs2a,2b,2cis connected to a second FBDIMM2bof the FBDIMMs2a,2b,2cvia a second bus6b, which just as the bus6aincludes a first channel (“south-bound channel” (SB channel)), and a second channel (“north-bound channel” (NB channel)), and the second FBDIMM2bof the FBDIMMs2a,2b,2cis connected to a third FBDIMM via a third bus6c(also having a first channel (“south-bound channel” (SB channel)), and a second channel (“north-bound channel” (NB channel)), etc., etc.

The FBDIMMs2a,2b,2cwork according to the “daisy chain” principle. The buffer component5aof the first FBDIMM2aof the FBDIMMs2a,2b,2crelays the respective address, command, and data signals received via the “south-bound channel” of the first bus6afrom the microprocessor/memory controller4—where required after a respective re-generation—via the “south-bound channel” of the second bus6bto the buffer component5bof the second FBDIMM2b. Correspondingly similar, the buffer component5bof the second FBDIMM2bof the FBDIMMs2a,2b,2crelays the respective address, command, and data signals received via the “south-bound channel” of the second bus6bfrom the first FBDIMM2a—where required after a respective re-generation—via the “south-bound channel” of the third bus6cto the buffer component5cof the third FBDIMM2c, etc., etc.

Correspondingly inversely, the buffer component5bof the second FBDIMM2bof the FBDIMMs2a,2b,2crelays the respective signals received via the “north-bound channel” of the third bus6cfrom the above third FBDIMM—where required after a respective re-generation—via the “north-bound channel” of the second bus6bto the buffer component5aof the first FBDIMM2a, and the buffer component5aof the first FBDIMM2aof the FBDIMMs2a,2b,2crelays the respective signals received via the “north-bound channel” of the second bus6bfrom the above second FBDIMM2b—where required after a respective re-generation—via the “north-bound channel” of the first bus6ato the microprocessor/memory controller4.

As is further illustrated inFIG. 1, each DRAM3a,3b,3cis connected to the corresponding buffer component5a,5b,5cvia a bus7a,7b,7c, e.g., a respective stub-bus.

Each buffer component5a,5b,5cknows its position in the above daisy chain. Which of the FBDIMMs2a,2b,2cis being accessed at a certain time by the memory controller4may e.g., be determined in the respective buffer component5a,5b,5cby comparing memory module identification data stored there (e.g., an “ID number”) with identification data sent by the memory controller4via the above buses6a,6b,6c. In conventional systems1, only one of the FBDIMMs2a,2b,2cmay be accessed at a certain time, i.e., no parallel access of FBDIMMs is possible.

The buffer component5a,5b,5cof an accessed FBDIMM2a,2b,2cdoes not only relay the received address, command, and data signals via a respective south-bound channel of one of the buses6a,6b,6cto the next buffer component in the daisy chain (as explained above), but also relays the signals (where appropriate, in converted form) via the above stub-bus7a,7b,7cto the DRAMs3a,3b,3cprovided on the accessed FBDIMM2a,2b,2c. Further, signals received by a respective buffer component5a,5b,5cvia the above stub-bus7a,7b,7cfrom an accessed DRAM3a,3b,3care relayed (where appropriate, in converted form) via a respective north bound channel of one of the buses6a,6b,6cto the previous buffer component in the daisy chain (or—by the buffer component5aof the first the FBDIMM2a—to the memory controller4).

As is illustrated inFIG. 1, the stub-buses7a,7b,7con the FBDIMMs2a,2b,2c, and the north bound channels of the buses6a,6b,6cmay e.g., comprise a data bandwidth of 144 bits per DRAM clock period, and the south bound channels of the buses6a,6b,6ce.g., a data bandwidth of only 72 bits per DRAM clock period, leading to a 1:2 write to read ratio, reflecting statistics in typical memory access patterns.

However, in a system corresponding to the memory system1illustrated inFIG. 1, a faster memory controller4, faster buses6a,6b,6cand7a,7b,7c, and faster buffer components5a,5b,5cstill might not lead to an increased overall performance.

For these or other reasons, there is a need for the present invention.

SUMMARY

The present invention provides a memory system. According to one embodiment of the invention, the memory system includes a first buffered memory module, and a second buffered memory module, wherein the first and the second buffered memory modules are adapted to be accessed in parallel. According to another embodiment of the invention, a device is provided which is adapted to map consecutive accesses to a first or a second buffered memory module to a parallel access of both the first and the second memory module.

DETAILED DESCRIPTION

FIG. 2illustrates a memory system11with buffered memory modules12a,12b,12caccording to an embodiment of the present invention.

As is illustrated inFIG. 2, several, e.g., more than three, seven, or fifteen, e.g., up to eight memory modules12a,12b,12c, e.g., respective memory cards/FBDIMMs (Fully Buffered DIMMs)12a,12b,12cper channel may be connected to a memory controller14. The memory controller14in turn may be connected via one or several buses to one or several microprocessors (not shown). For sake of simplicity,FIG. 2only depicts one single channel. The system11may comprise more than the one channel illustrated inFIG. 2, e.g., more than two or four channels, each having—just as the channel illustrated in FIG.2—several, e.g., more than three, seven, or fifteen, e.g., up to eight memory modules/FBDIMMs (Fully Buffered DIMMs).

Each FBDIMM12a,12b,12cincludes one or several buffer components15a,15b,15c, and one or several RAM devices13a,13b,13c, in particular e.g., DRAMs or SRAMs, here: SDRAMs, e.g., more than three, seven, or fifteen, for instance eight DRAMs (for sake of simplicity, inFIG. 2only one DRAM per memory card/FBDIMM12a,12b,12cis illustrated).

Each DRAM may e.g., have a storage capacity of e.g., 128 MBit, 256 MBit, 512 MBit, 1 GBit, 2 Gbit, etc. (or more); the total storage capacity provided by a corresponding FBDIMM12a,12b,12cdepends on the number of DRAMs provided on a FBDIMM, and on the storage capacity of the individual DRAMs, and is, for instance, 1 GByte, 2 GByte, etc. (or more).

The FBDIMMs12a,12b,12cmay e.g., be plugged into corresponding sockets of a motherboard, which e.g., may also include the above memory controller14, and/or the above microprocessor(s).

As is illustrated inFIG. 3, and as will be described in further detail below, and other than in conventional memory systems such as e.g., illustrated inFIG. 1, with the memory system11illustrated inFIG. 2, several of the FBDIMMs12a,12b,12c—e.g., two or more of the FBDIMMs12a,12b,12cof one single channel—may be accessed by the above memory controller14/microprocessor(s) at one and the same time—in other words, a parallel (read and/or write) access of FBDIMMs12a,12b,12cis possible.

In particular, for example, at one and the same time/in parallel, a “read” access might be carried out on two or more of the FBDIMMs12a,12b,12c.

Correspondingly similar, for example, a “write” access might be carried out on two or more of the FBDIMMs12a,12b,12cat one and the same time/in parallel.

As is illustrated inFIG. 2, the memory controller14may be connected to a first FBDIMM12a(“DIMM1”) of the FBDIMMs12a,12b,12cvia a first bus16aprovided on the above motherboard, having a first channel (“south-bound channel” (SB channel)), and a second channel (“north-bound channel” (NB channel)). The SB channel of the bus16ais used to send respective address, command, and data signals from the memory controller14(and/or the above microprocessor(s)) to the buffer component15aof the first FBDIMM12a. Correspondingly similar, the NB channel of the bus16ais used to send respective signals from the buffer component15aof the first FBDIMM12ato the memory controller14(and/or the above microprocessor(s)).

As is further illustrated inFIG. 2, the first FBDIMM12aof the FBDIMMs12a,12b,12cis connected to a second FBDIMM12b(“DIMM2”) of the FBDIMMs12a,12b,12cvia a second bus16b, which just as the bus16aincludes a first channel (“south-bound channel” (SB channel)), and a second channel (“north-bound channel” (NB channel)), and the second FBDIMM12bof the FBDIMMs12a,12b,12cis connected to a third FBDIMM via a third bus16c(also having a first channel (“south-bound channel” (SB channel)), and a second channel (“north-bound channel” (NB channel)), etc., etc.

According toFIG. 2, the memory system11in addition to the above FBDIMMs12a,12b,12c, and the memory controller14includes a clock device20, and a system clock generator21. The clock device20generates a central clock signal, which is provided via respective lines20a,20bto the memory controller14, and the system clock generator21. The system clock generator14—from the central clock signal generated by the clock generator20—generates respective individual clock signals for the memory controller14, and each of the FBDIMMs12a,12b,12c(which are provided via respective individual lines21a,21b,21c,21dfrom the system clock generator21to the memory controller14, the first FBDIMM12a, the second FBDIMM12b, etc.). The timing of the clock signals provided by the system clock generator21on the above lines21a,21b,21c,21dmight be such that respective positive/negative flanks of the clock signals might occur at identical points of time, or might be slightly offset from one another, still defining—as is illustrated in FIG.3—for the whole memory system11, i.e., each of the FBDIMMs12a,12b,12c, as well as the memory controller14a unique common timing scheme (defining subsequent unique common clock periods A, B, C, D, E, F, G, etc., etc. for each of the FBDIMMs12,12b,12c, as well as the memory controller14, i.e., the whole system11, each of the clock periods A, B, C, D, E, F, G, etc., etc. lasting a corresponding clock cycle time 1 tCK). Many other ways of generating/providing respective clock signals and/or a unique common timing scheme are also possible. For instance, the memory controller14might generate a clock signal, which is provided to the first FBDIMM12a, from where the clock signal—where required after a respective re-generation—is provided to the second FBDIMM12b, and from the second FBDIMM12bto the third FBDIMM, etc., etc.

The FBDIMMs12a,12b,12cwork according to the “daisy chain” principle. The buffer component15aof the first FBDIMM12aof the FBDIMMs12a,12b,12crelays the respective address, command, and data signals received via the “south-bound channel” of the first bus16afrom the microprocessor/memory controller14—where required after a respective re-generation—via the “south-bound channel” of the second bus16bto the buffer component15bof the second FBDIMM12b. Correspondingly similar, the buffer component15bof the second FBDIMM12bof the FBDIMMs12a,12b,12crelays the respective address, command, and data signals received via the “south-bound channel” of the second bus16bfrom the first FBDIMM12a—where required after a respective regeneration—via the “south-bound channel” of the third bus16cto the buffer component15cof the third FBDIMM12c, etc., etc.

Correspondingly inversely, the buffer component15bof the second FBDIMM12bof the FBDIMMs12a,12b,12crelays the respective signals received via the “north-bound channel” of the third bus16cfrom the above third FBDIMM—where required after a respective re-generation—via the “north-bound channel” of the second bus16bto the buffer component15aof the first FBDIMM12a, and the buffer component15aof the first FBDIMM12aof the FBDIMMs12a,12b,12crelays the respective signals received via the “north-bound channel” of the second bus16bfrom the above second FBDIMM12b—where required after a respective re-generation—via the “north-bound channel” of the first bus16ato the microprocessor/memory controller14.

As will be described in further detail below, the memory controller14, and each of the buffer components15a,15b,15csend out the above signals (data, and/or address, and/or command signals) on the respective “south-bound” and “north bound” channels of the above buses16a,16b, and16cwith respect to the timing provided by the above unique common timing scheme of the memory system11as defined by the above clock signals provided by the system clock generator21on the above lines21a,21b,21c,21d(i.e., with respect to the unique common clock periods A, B, C, D, E, F, G, etc., defined by the clock signals, and as illustrated inFIG. 3).

As is further illustrated inFIG. 2, and correspondingly similar as is the case in conventional memory systems, each of the RAM devices, in particular e.g., DRAMs or SRAMs, here: SDRAMs13a,13b,13cprovided on the above FBDIMMs12a,12b,12cis connected to the corresponding buffer component(s)15a,15b,15cprovided on a respective FBDIMM12a,12b,12cvia a bus17a,17b,17c, e.g., a respective stub-bus.

According toFIG. 2, the stub-buses17a,17b,17con the FBDIMMs12a,12b,12c, and the south bound channels of the buses16a,16b,16cmay e.g., include the same data bandwidth, e.g., a data bandwidth of 144 bits per DRAM clock period. Further, the north bound channels of the buses16a,16b,16cmight e.g., include a higher data bandwidth as the south bound channels, and the stub-buses17a,17b,17con the FBDIMMs12a,12b,12c, e.g., two times the data bandwidth of the south bound channels and the stub-buses17a,17b,17c, e.g., a data bandwidth of 288 bits per DRAM clock period.

Each buffer component15a,15b,15cof the FBDIMMs12a,12b,12cknows its position in the above daisy chain. Which of the FBDIMMs12a,12b,12cis being accessed at a certain time by the memory controller14may e.g., be determined in the respective buffer component15a,15b,15cby comparing memory module identification data stored there (e.g., an “ID number”) with identification data sent by the memory controller14via the above buses16a,16b,16c, e.g., via one or several separate address and/or command lines of the above buses16a,16b,16c.

As the above, with the memory system11illustrated inFIG. 2, several of the FBDIMMs12a,12b,12c—e.g., two or more of the FBDIMMs12a,12b,12cof one single channel—may be accessed by the above memory controller14/microprocessor(s) at one and the same time—in other words, a parallel (read and/or write) access of FBDIMMs12a,12b,12cis possible.

For example, as is illustrated inFIG. 3, to carry out two or more parallel “read” accesses on two or more of the FBDIMMs12a,12b,12cin parallel, the two or more FBDIMMs12a,12b,12cto be accessed in parallel (e.g., the first FBDIMM12a(“DIMM1”), and the second FBDIMM12b(“DIMM2”)) are activated at the same time by respective “Activate” Commands ACT1, ACT2being sent out by the memory controller14on the above south bound channels of the buses16a,16b,16cin parallel (i.e., on one and the same common clock period of the above clock periods A, B, C, D, E, F, G (here: e.g., the clock period B)).

Together with the above “Activate” Commands ACT1, ACT2—e.g., also at the above clock period B—, “ID numbers” identifying the FBDIMMs12a,12b,12cto be accessed in parallel may be sent out by the memory controller14on the above south bound channels of the buses16a,16b,16c(here e.g., a first ID number to identify the first FBDIMM12a(“DIMM1”), and a second ID number to identify the second FBDIMM12b(“DIMM2”) to be accessed in parallel to the first FBDIMM12a).

As the above, the buffer components15a,15b,15cof the FBDIMMs12a,12b,12cdetermine whether or not they are accessed at a certain time by comparing the ID number stored there with the ID number sent out by the memory controller14.

After a certain buffer component15a,15b,15c(here: the buffer component15aof the first FBDIMM12a, and the buffer component15bof the second FBDIMM12b) has determined that the corresponding FBDIMM12a,12b,12cis to be accessed, the corresponding buffer component (here: e.g., the buffer component15aof the first FBDIMM12a, and the buffer component15bof the second FBDIMM12b) does not only relay the address, command, and data signals received via a respective south-bound channel of one of the buses16a,16b,16cto the next buffer component in the daisy chain (as explained above), but also relays the signals (where appropriate, in converted form) via the above stub-buses (here: the stub-bus17aof the first FBDIMM12a, and the stub-bus17bof the second FBDIMM12b) to the RAMs (here: the RAMs13a,13b) provided on the accessed FBDIMMs (here: the FBDIMMs12a,12b)).

As is further illustrated inFIG. 3, a predetermined time Δt_ACT after the above “Activate” Commands ACT1, ACT2, respective “read” commands RD1, RD2are sent out by the memory controller14on the above south bound channels of the buses16a,16b,16cin parallel (i.e., on one and the same common clock period of the above clock periods A, B, C, D, E, F, G (here: e.g., the clock period D, i.e., one clock cycle time 1 tCK after the “Activate” Commands ACT1, ACT2)).

Together with and/or after the above “read” Commands RD1, RD2respective row and/or column addresses may be sent out by the memory controller14on the above south bound channels of the buses16a,16b,16c(here e.g., a first row and/or column address for the first FBDIMM12a(“DIMM1”), and a second row and/or column address for the second FBDIMM12b(“DIMM2”)). The addresses for the first and second FBDIMM12a,12bmay e.g., be sent out one after the other, i.e., on different clock periods, or preferably at the same or corresponding clock periods (e.g., the row addresses for the first and second FBDIMMs12a,12bat a first clock period, and the column addresses for the first and second FBDIMMs12a,12bat a second, subsequent clock period).

In response to the “read” Commands RD1, RD2, and the above row and/or column addresses the buffer components15a,15bof the accessed FBDIMMs12a,12b—correspondingly similar as in conventional memory systems—by sending out respective command and address signals on the above stub-buses17a,17bcarry out a respective “READ” access on a respective RAM (here: the RAM13a, and the RAM13b) of the FBDIMMs12a,12b. In response, the data is read out from the RAMs13a,13b(here: the data DQ1,0, DQ1,1, DQ1,2, DQ1,3from the RAM13a, and the data DQ2,0, DQ2,1, DQ2,2, DQ2,3from the RAM13b), and is sent from the RAMs13a,13bvia the respective stub-bus17a,17bto the respective buffer component (here: the buffer components15a,15b). As can be seen inFIG. 3, the reading out of the data on both the FBDIMM12aand the FBDIMM12bmay be performed in parallel a predetermined time Δt_RD after the above “read” Commands RD1, RD1are sent out by the memory controller14(i.e., starting on one and the same common clock period of the above common clock periods A, B, C, D, E, F, G (here: e.g., the clock period F, i.e., one clock cycle time 1 tCK after the “read” Commands RD1, RD2)). As can be further seen inFIG. 3, the reading out of the data (here: the data DQ1,0, DQ1,1, DQ1,2, DQ1,3, and the data DQ2,0, DQ2,1, DQ2,2, DQ2,3) may occur in a time-multiplexed fashion, lasting several cycle times 1 tCK (here: two cycle times 1 tCK, i.e., a time period ΔT).

Typical memory access patterns of typical programs executed on the above processor(s) connected with the memory controller14frequently lead to a consecutive access of adjacent or nearby memory locations (e.g., memory cells belonging to one single row of memory cells of one single RAM located on one single FBDIMM).

In one embodiment of the invention, the memory controller14may map such consecutive accesses to adjacent or nearby memory locations of one single RAM located on one single FBDIMM (or more generally: consecutive accesses to one single FBDIMM) to accesses of different RAMs located on different FBDIMMs.

In one embodiment, consecutive read (and/or write) accesses to adjacent or nearby memory locations of one single RAM located on one single FBDIMM (or consecutive read (and/or write) accesses to one single FBDIMM) may be mapped by the memory controller14into the above parallel (read and/or write) accesses to two or more different FBDIMMs12a,12b,12cdescribed above (e.g., in connection withFIG. 3).

For this purpose, appropriate physical address mapping and/or scheduling techniques may be used by the memory controller14.

For example, if the processor(s) issues consecutive read (and/or write) accesses to adjacent or nearby memory locations of one single RAM located on one single FBDIMM (or consecutive read (and/or write) accesses to one single FBDIMM), parts of the respective row and/or column address used by the processor(s) to specify a respective memory cell on one single RAM (or parts of any other address used to specify a memory cell on one single FBDIMM) may be used by the memory controller14as the above “ID number” (or part of the above ID number) instead, sent out by the memory controller14on the above south bound channels of the buses16a,16b,16cto identify the respective FBDIMM or FBDIMMs12a,12b,12cto be accessed. In one embodiment, the least significant bit or bits of the above address, e.g., row and/or column address may be used for this purpose (e.g., the one, two, or three least significant bits of the address).

Thereby it is ensured that consecutive read (and/or write) accesses to adjacent or nearby memory locations of one single RAM or one single FBDIMM are mapped by the memory controller14into accesses to different FBDIMMs (which as the above preferably are carried out in parallel).

Alternatively or additionally, a scheduling technique may be employed in the memory controller which avoids consecutive accesses to one single FBDIMM.

Hence, if according to the commands issued by the processor(s) consecutive read (and/or write) accesses to adjacent or non-adjacent memory locations of one single RAM or one single FBDIMM are to be performed, a re-scheduling is performed by the memory controller14. For instance, even if according to the commands issued by the processor(s) e.g., first an access to a first FBDIMM12ais to be performed, then again an access to the first FBDIMM12a(referring to the same, i.e. a first, or a different RAM (or to adjacent, or non-adjacent memory locations)), and afterwards an access to a second FBDIMM12b, and then again an access to the second FBDIMM12b(referring to the same, i.e. a first, or a different RAM (or to adjacent, or non-adjacent memory locations)), the memory controller14performs a re-scheduling such that e.g., first a first parallel access to both the first and the second FBDIMM12aand12bis performed (e.g., to the above first RAMs), and thereafter a second parallel access again to both the first and the second FBDIMM12aand12b(e.g., again to the above first, or to the above different RAMs). For this purpose the memory controller14in a first process determines whether or not consecutive accesses refer to one single FBDIMM, and—if it is determined that consecutive accesses refer to one single FBDIMM—in a second process performs a respective re-scheduling to avoid consecutive accesses to one single FBIMM, e.g., by performing the above parallel access to different FBDIMMs, instead.

The above parallel (read and/or write) access in a further variant of the invention may also be used to mimic RAM burst accesses with higher I/O speed and longer burst length than provided for by the RAMs13a,13b,13con the FBDIMMs12a,12b,12c.

A burst read or write access of the processor(s) to one single RAM of one single FBDIMM and referring to a first burst length may be mapped by the memory controller into the above parallel read or write access to two different RAMs on two different FBDIMMs described above (e.g., in connection withFIG. 3) with a second, different burst length (e.g., half the burst length as specified by the processor(s)).