Amplifier with charge-pump generated local supplies

An amplifier system includes a follower-type output stage that is driven by a pre-driver circuit. The follower-type output stage that is operated from VCC and GND (or VEE) power supplies. The pre-driver circuit for the follower output stage is operated from local power supplies corresponding to VHI and VLO. A charge-pump circuit generates the VHI power-supply such that VHI is above VCC. Another charge-pump circuit generates the VLO power-supply such that VLO is below GND (or VEE). The output stage delivers current to a load from the VCC and GND (or VEE) power supplies such that the output stage has increased power efficiency.

FIELD OF THE INVENTION

The present invention is generally related to amplifiers that include follower-type output stages. More particularly, the present invention relates to generating increased local power-supply rails via a charge-pump circuit such that a pre-driver circuit has increased drive range for a follower-type output stage in an amplifier.

BACKGROUND OF THE INVENTION

Computer systems are often connected to a communication network via telephone lines. A popular means for connecting computer systems to a network is over a digital subscribed line (DSL). DSLs come in many varieties including asymmetric (ADSL), symmetric (SDSL), rate-adaptive (RADSL), and very high bit-rate (VDSL).

The DSL shares the same physical wire as a common telephone line. The telephone wire is a twisted pair of copper wires, which has a maximum signal bandwidth from 300 kHz-10 MHz., depending on the length of the line. Since a typical voice communication requires only a portion of the total bandwidth (e.g., around 4 kHz) available on the telephone line, the additional unused bandwidth is available on the line for the DSL communication without interfering with telephone communication.

A subscriber device such as a computer communicates with a service provider via a DSL modem. The DSL modem is physically connected between the subscriber device and the telephone wire, and includes a DSL line driver. The DSL line driver includes a power amplifier that delivers a signal to the telephone line.

SUMMARY OF THE INVENTION

Briefly stated, the present invention is related to an amplifier system includes a follower-type output stage that is driven by a pre-driver circuit. The follower-type output stage that is operated from VCC and GND (or VEE) power supplies. The pre-driver circuit for the follower output stage is operated from local power supplies corresponding to VHI and VLO. A charge-pump circuit generates the VHI power-supply such that VHI is above VCC. Another charge-pump circuit generates the VLO power-supply such that VLO is below GND (or VEE). The output stage delivers current to a load from the VCC and GND (or VEE) power supplies such that the output stage has increased power efficiency. The output stage may be implemented in any technology such as FET transistors and/or BJT transistors.

A more complete appreciation of the present invention and its improvements can be obtained by reference to the accompanying drawings, which are briefly summarized below, the following detail description of presently preferred embodiments of the invention, and the appended claims.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

Throughout the specification, and in the claims, the term “connected” means a direct electrical connection between the things that are connected, without any intermediate devices. The term “coupled” means either a direct electrical connection between the things that are connected, or an indirect connection through one or more passive or active intermediary devices. The term “circuit” means either a single component or a multiplicity of components, either active or passive, that are coupled together to provide a desired function.

The present invention is related to a driver amplifier for a DSL. The driver amplifier includes two charge-pumps that are arranged to provide local power supplies. The local power supplies are used in a level shifting circuitry that is coupled to the output stage. The resulting driver amplifier has a signal swing that is within a VCE(SAT) of the power-supply rails (or VDS(SAT)), has reduced quiescent current, and low distortion.

In one example, the output stage of the driver amplifier is connected between 12V and ground. For this example, the charge-pumps are arranged to provide local power supplies that are at +15V and −3.3V such that near rail-to-rail output levels are achieved with low overheard loss. The first charge-pump transfers charge from a 3.3V supply to generate the +15V supply, while the second charge-pump transfers charge from the 3.3V supply to generate the −3V supply. The charge-pump circuitry can be implemented in an integrated circuit such as a 3V CMOS process.

Although many of the examples that follow below are described as operating from a ground power supply rail (GND), another low power supply rails may be employed. For example, a VEE power supply may be used in place of the GND power supply for the output stage. Also, another power supply other than 3.3V may be employed for the charge-pump. For example, a VDD power supply may be used for the charge-pump with an operating voltage of 2.5V, 3.3V, or 5V. The VDD power supply voltage is selected based on the limits on the semiconductor process for the driver amplifier, and the design of the pre-driver circuit.

Operating Environment

FIG. 1is a schematic diagram (100) of a system application of the driver amplifier that is configured in accordance with the present invention. The system includes two input coupling capacitors (CIN1, CIN2), a DSL driver system (110), two terminating resistors (R16, R17), a transformer (T1), a telephone line, and a load (ZL). DSL driver system110includes two biasing resistors (R11, R12), gain setting resistors (R13, R14, R15), and two driver amplifiers (A1, A2).

Capacitors CIN1and CIN2are arranged to couple an AC input signal (INP, INN) to the non-inverting input terminals of driver amplifiers A1and A2. Resistors R11and R12are arranged to provide a DC bias voltage (VCC/2) to the non-inverting input terminals of driver amplifiers A1and A2. Amplifiers A1and A2are arranged in a bridged amplifier configuration, where resistors R13through R15set the gain for the bridged amplifier. Although the system illustrated inFIG. 1includes gain setting resistors R13-R15, resistors R13-R15may be eliminated when the gain is internally set in the amplifiers (A1, A2).

Resistors R16and R17couple the output of the bridged amplifier to the primary coil of transformer T1, where the values associated with resistors R16and R17determine the termination impedance of the amplifiers. The secondary coil of the transformer is coupled to a twisted pair line such as a telephone line. The twisted pair line is terminated by a remote line termination, as represented by load ZL. In one example, the termination impedance (load ZL) corresponds to 100 ohms.

Driver Amplifier Overview

FIG. 2is a schematic diagram (200) of a driver amplifier system that is arranged in accordance with the present invention. The driver amplifier system includes an amplifier portion (220) and a charge-pump portion (230). Amplifier portion220includes an amplifier (AMP), a high level-shift driver (DP), a low level-shift driver (DN), and a follower-type output stage (210). Charge-pump portion230includes an oscillator circuit (OSC), an inverting driver (IDRV), a high charge-pump circuit (PUMPH), a low charge-pump circuit (PUMPL), and four capacitors (C1-C4).

Amplifier AMP is configured to provide an intermediate signal to node N21in response to a differential input signal that is applied to INN and INP. Driver DP is configured to provide a high drive signal to node N22in response to the intermediate signal at node N21. Driver NP is configured to provide a low drive signal to node N23in response to the intermediate signal at node N21. Follower-type output stage210is configured to provide an output signal between terminals OUT and GND in response to the high and low drive signals. In one example, follower-type output stage210includes an n-type field effect transistor (NFET) and a p-type field effect transistor (PFET) that are configured as a common source output stage that is responsive to the high and low drive signals. In another example, follower-type output stage210includes an n-type bipolar junction transistor (NPN BJT) and a p-type bipolar junction transistor (PNP BJT) that are configured as a common emitter output stage that is responsive to the high and low drive signals. Drivers DP and NP may be separate circuits or combined into a single pre-driver circuit.

Capacitor C1is coupled between node N25and VHI. Capacitor C2is coupled between node N27and VCC. Capacitor C3is coupled between node N25and node N26. Capacitor C4is coupled between VLO and GND. PUMPL is coupled to node N25, N26and VLO. PUMPH is coupled to node N25, N27and VHI. Oscillator OSC is coupled to node N24. Inverting driver IDRV is coupled between node N24and node N25.

In operation, oscillator OSC is configured to provide a clock signal (CLK) at node N24. Inverting driver IDRV is configured to provide a charging signal to node N25in response to the clock signal (CLK). The charge-pump circuits are arranged to generate voltages for VHI and VLO in response to the charging signal at node N25. The charge-pump circuits will be described in further detail with respect toFIGS. 3A-3C.

Power-supply connections are shown at key points inFIG. 2. As shown, the amplifier (AMP) and the follower-type output stage (210) are operated from power-supply rails VCC and GND. However, the pre-driver circuit (driver circuits DP and DN are operated from VHI and VLO such that the drive signals at nodes N22and N23have maximum signal swing to provide near rail-to-rail performance in the output stage. Since oscillator circuit OSC and inverting driver circuit IDRV are operated from power-supply rails VDD and GND, an integrated circuit solution is possible. In one example, VDD is +3.3V, VCC is +12V, and VHI and VLO correspond to +15V and −3.0V, respectively.

FIG. 3Ais a schematic diagram (310) that illustrates the operation of a high charge-pump circuit that is arranged in accordance with the present invention. The high charge-pump circuit includes two capacitors (C1, C2), and two switching circuits (SW1, SW2).

Capacitor C1is coupled between the common terminals on switching circuits SW1and SW2. Capacitor C2is coupled between VHI and VCC. Switching circuit SW1is coupled to VDD at a first terminal, VHI at a second terminal, and CTL at a control terminal. Switching circuit SW2is coupled to GND at a first terminal, VCC at a second terminal, and CTL at a control terminal.

The operation of the high charge-pump circuit is described with respect to the timing diagram (320) that is illustrated inFIG. 3B. As shown in the figure, control signal CTL cycles between a state where switching circuits SW1and SW2are in the first position (A), and a state where switching circuits SW1and SW2are in a second position (B). The first position (A) corresponds to a charging phase, while the second position (B) corresponds to a charge-redistribution phase.

In operation, capacitor C1stores a voltage (VC1) corresponding to VDD-GND when switching circuits SW1and SW2are in the first position (A). Thus, capacitor C1charges up to VDD such that a charge is stored on capacitor C1that corresponds to VDD*C1. Capacitor C1and C2are coupled together in parallel between VHI and VCC while switching circuits SW1and SW2are in the second position (J3). Charge is redistributed between capacitors C1and C2such that the final voltage on capacitor C1and C2are the same. Since C2is referenced to VCC, the voltage on the top plate of capacitor C2will increase above VCC by an amount that is determined according to the charge redistribution between C1and C2. Assuming that capacitor C2initially has no charge stored therein, the voltage associated with capacitor C2is given by: VHI=VDD/(1+[C2/C1])+VCC. When C2has a capacitance value that is much less than C1, VHI=VDD+VCC. After capacitor C2has some stored some charge, VHI−{VDD/(1+[C2/C1])}+{VC2/(1+[C1/C2])}.

In a non-ideal condition, a load (not shown) draws a high load current (ILOADH) from VHI as shown by the changes in VC2. Also, their may be an appreciable non-ideal resistance associated with switching circuits SW1and SW2that results in an RC time-constant that is associated with the charging of capacitor C1, and the charge transfer associated with C2(see VC1, VC2inFIG. 3B). Furthermore, the switching circuits may have appreciable parasitic capacitances between the output and control terminals that will reduce the output voltage. However, the voltage associated with VHI is “refreshed” periodically in response to CTL such that the steady-state value of VHI will approach VCC+VDD.

FIG. 3Cis a schematic diagram (330) that illustrates the operation of a low charge-pump circuit that is arranged in accordance with the present invention. The low charge-pump circuit includes two capacitors (C3, C4), and two switching circuits (SW3, SW4).

Capacitor C3is coupled between the common terminals on switching circuits SW3and SW4. Capacitor C4is coupled between GND and VLO. Switching circuit SW3is coupled to VDD at a first terminal, GND at a second terminal, and CTL at a control terminal. Switching circuit SW4is coupled to GND at a first terminal, VLO at a second terminal, and CTL at a control terminal.

The operation of the low charge-pump circuit is described with respect to the timing diagram (320) that is illustrated inFIG. 3B. As shown in the figure, control signal CTL cycles between a state where switching circuits SW3and SW4are in the first position (A), and a state where switching circuits SW3and SW4are in a second position (B).

In operation, capacitor C3stores a voltage (VC3) corresponding to VDD−GND when switching circuits SW3and SW4are in the first position (A). Thus, capacitor C3charges up to VDD such that a charge is stored on capacitor C3that corresponds to VDD*C3. Capacitors C3and C4are coupled together in parallel between GND and VLO while switching circuits SW3and SW4are in the second position (B). Charge is redistributed between capacitors C3and C4such that the final voltage on capacitors C3and C4are the same. Since C4is referenced below GND, the voltage on the bottom plate of capacitor C4will decrease below GND by an amount that is determined according to the charge redistribution between capacitors C3and C4. Assuming that capacitor C4does not initially have any stored charge, the voltage associated with capacitor C4is given by: VLO=GND−VDD/(1+[C4/C3]). When C4has a capacitance value that is much less than C3, VLO=GND−VDD. After capacitor C4has stored charge, VLO=GND−{VDD/(1+[C4/C3])}−{VC4/(1+[C3/C4])}.

In a non-ideal condition, a load current (ILOADL) causes VLO to gradually change over time. Also, their may be an appreciable non-ideal resistance associated with switching circuits SW3and SW4that results in an RC time-constant that is associated with the charging of capacitor C3(see VC1inFIG. 3B), and the charge transfer associated with C4. However, the voltage associated with VLO is “refreshed” periodically in response to CTL such that the stead-state value of VHI approaches VCC+VDD.

The voltages associated with the local power supply will be slightly reduced to non-ideal switching circuits and other parasitic elements in the circuit. For example, the non-ideal switching circuits include a non-zero “on” resistance when the switching circuits are operated in a closed-circuit state. Moreover, the switching circuits also include non-ideal capacitances that are lumped to critical nodes in the circuit (e.g., parasitic capacitances that are coupled to VHI and VLO). These parasitic capacitances and resistances result in reduction to VHI such as: VHI=VCC+VDD−delta V, where delta V is a small error that is related to switch resistance and parasitic capacitance. Similarly, VLO=VEE−VDD+delta V, where VDD is a power-supply voltage for the charge-pump circuit, and delta V is a small error that is related to switch resistance and parasitic capacitance.

FIG. 4is a schematic diagram that illustrates an example charge-pump circuit (400) that includes facilities for high and low power-supply generation. The charge-pump circuit (400) includes six capacitors (C41-C46), and six inverter circuits (I1-I6).

Inverter circuit I1includes an input that is coupled to CLK, and an output that is coupled to node N41. Inverter circuit I2includes an input that is coupled to node N41, and an output that is coupled to node N42. Inverter circuit I3includes an input that is coupled to node N43, and an output that is coupled to node N44. Inverter circuit I4includes an input that is coupled to node N44, and an output that is coupled to node N43. Inverter circuit I5includes an input that is coupled to node N45, and an output that is coupled to node N45. Inverter circuit I6includes an input that is coupled to node N46, and an output that is coupled to node N45. Capacitor C41is coupled between node N43and node N41. Capacitor C42is coupled between VHI and VCC. Capacitor C43is coupled between node N41and node N45. Capacitor C43is coupled between node N44and node N42. Capacitor C44is coupled between GND and VLO. Capacitor C45is coupled between node N44and node N42. Capacitor C46is coupled between node N42and node N46. Inverter circuits I1and I2are operated from power-supply rails VDD and GND. Inverter circuits I3and I4are operated from power-supply rails VHI and VCC. Inverter circuits I5and I6are operated from power-supply rails GND and VLO.

The inverter circuits are arranged to cooperate with the capacitors to generate the power-supply rails for VHI and VLO. Inverter circuits I2, I3, and I5are strong inverting stages that have higher drive/gain capabilities than inverter circuits I1, I4, and I6. The stronger inverter circuits skew delay paths so that the capacitors are charged in a break before make operation.

Capacitor circuits C41and C43are arranged to provide isolation between the inverter circuits so that the DC levels for inverter I3/I4and I5/I6are shifted with respect to the DC levels for inverters I1/I2. Transient signals (e.g., a narrow pulse or spike) are transferred through capacitors C41and C43such that inverter circuits I3and I5change output states at each transition in the clock signal. Inverter circuit I4provides a DC biasing for inverter circuit I3so that the input range of inverter circuit I3is bounded by VCC and VHI. Similarly, inverter circuit I6provides a DC biasing for inverter circuit I5so that the input range of inverter circuit I5is bounded by VLO and GND. Inverter circuits I4and I6are also arranged to provide positive feedback to inverter circuits I3and I5, respectively so that the operating conditions of those inverters track changes in the clock signal.

Capacitor C45is a charge transfer capacitor that is configured to transfer charge for the high charge-pump circuit. For example, capacitor C45includes a top plate that is coupled to VCC through inverter circuit I3, and a bottom plate that is coupled to GND through inverter circuit I2when the clock signal transitions from high to low. This condition corresponds to the charging phase, where the output of inverter circuit I4is maintained at VHI and capacitor C45stores a voltage corresponding to VCC−GND. At the next transition in the clock signal (low to high), the bottom plate of capacitor C45is coupled to VDD through inverter circuit I2and the top plate of capacitor C45is coupled to VHI through inverter circuit I3. This condition corresponds to a charge redistribution phase, where the charge stored on capacitor C45is transferred to capacitor C42such that VHI corresponds to VCC+VDD at steady-state.

Capacitor C46is a charge transfer capacitor that is configured to store charge for the low charge-pump circuit. For example, capacitor C46includes a top plate that is coupled to VDD through inverter circuit I2, and a bottom plate that is coupled to GND through inverter circuit I5when the clock signal transitions from low to high. This condition corresponds to the charging phase, where the output of inverter circuit I6is maintained at VLO and capacitor C46stores a voltage corresponding to VDD−GND. At the next transition in the clock signal (high to low), the top plate of capacitor C46is coupled to GND through inverter circuit I2and the bottom plate of capacitor C46is coupled to VLO through inverter circuit I5. This condition corresponds to a charge redistribution phase, where the charge stored on capacitor C46is transferred to capacitor C44such that VLO corresponds to GND−VDD at steady-state.

Example Amplifier Circuit

Transistor XBP and resistor RBP are arranged to operate as a first current source that is biased by BIASP. Transistor XBN and resistor RBN are arranged to operate as a second current source that is biased by BIASN. Transistors XIN1and XIP1are configured to cooperate with the first and second current source to operate as input followers in the amplifier circuit that operate from the VCC and GND supply rails. Transistors XIN2and XIP2cooperate with the input followers to provide current signals I51and I52, which are responsive to INP and INM.

Transistors X52A-X52D and resistors R52A-R52C are configured to operate as a first current mirror circuit (i.e., a Wilson-type current mirror circuit) that operates from the VHI supply rail. Transistors X53A-X53D and resistors R53A-R53C are configured to operate as a second current mirror circuit (i.e., a Wilson-type current mirror circuit) that operates from the VLO supply rail. The current mirror circuits receive current signals I51and I52via transistors X52A and X53A, respectively. The output of the current mirror circuits are combined through resistor R54, which is series connected between the outputs of transistors X52D and X53D. Capacitors C51and C52are coupled between the input of the current mirror circuits and their respective outputs to frequency-compensate the amplifier.

The amplifier includes a triple emitter follower class AB output stage. Transistors X54is biased by current from transistor X52C in the first current mirror circuit such that transistor X54operates as a first emitter follower circuit for the high drive side of the amplifier. Transistor XDN1is a diode-connected transistor that is in series with transistor X54for class AB operation. The high drive output of the first emitter follower circuit is provided as intermediate high drive signal S1. Transistors X55is biased by current from transistor X53C in the second current mirror circuit such that transistor X55operates as a first emitter follower circuit for the low drive side of the amplifier. Transistor XDP1is a diode-connected transistor that is in series with transistor X55for class AB operation. The low drive output of the first emitter follower circuit is provided as intermediate low drive signal S2. Resistor R54helps reduce the operating current in the class AB output stage.

Transistor X56is arranged to provide high drive signal S3in response to intermediate drive signal S1, where transistor X56is part of a second emitter follower for the high drive side of the output stage. Transistor X57is arranged to provide low drive signal S4in response to intermediate drive signal S2, where transistor X57is part of the second emitter follower for the low drive side of the output stage. Transistors XDN2and XDP2are diode-connected devices that are arranged to provide class AB operation for the output stage. The class AB signals are provided to the third emitter follower, which corresponds to transistors XFN and XFP.

Amplifier circuit500includes all of the functionality that was described with respect to circuit220. The first and second emitter follower circuits are operated from the VHI and VLO supply rails, similar to the pre-driver circuit (drivers DP and DN) that are described inFIG. 2. The collectors of transistors XFN and XFP are coupled to VCC and GND, similar to follower output stage210. Since the third emitter follower provides the output signal to the load (seeFIG. 2), the current that is delivered to the load is provided from the VCC and GND supplies. VHI and VLO are local power supplies that are used in the amplifier to generate signals S3and S4.

For maximum power efficiency, the output swing should be within a VCE(SAT) of each supply rail (VCC and GND). The base voltage of transistor XFN should swing to VCC−VCE(SAT)+VBE (e.g., 12V −0.3V+0.8V=12.6V). Taking into account the VBE of X56, and the voltage drop from X52C and R52C, it can be shown that VHI must be larger than VCC+2VBE+ΔV=VCC+1.7V, which corresponds to approximately 13.7V for a VCC of 12V.

Similarly, the VLO supply must account for the headroom requirements of transistor XFP for maximum power efficiency. VLO should be lower than VCC by an amount that allows the PNP emitter-followers to swing within a VCE(SAT) of GND. It can be shown that VLO must be less than GND−2VBE−ΔV, which roughly corresponds to −1.7V for a GND voltage of 0V.

The power-supply requirements for VLO and VHI are determined by the current requirements for the class AB stage in the amplifier. Although the pre-driver circuit in the amplifier is operated from VHI and VLO, the final follower output stage in the amplifier is operated from VCC and GND (or VEE when GND is non-zero). Since the final output stage is not operated from the charge-pump supply, the sizes associated with the charge-pump local power-supply capacitors (e.g., C2and C4inFIG. 2) are somewhat independent of the load current (except for the base current in a bipolar design).

The drive levels for proper operation of the output stage are determined by the power supply levels and the saturation requirements of the transistors. The output stage illustrated inFIG. 5includes a BJT output stage as represented by XFN and XFP. The high drive signal to XFP must swing to (VCC−VCE1(SAT)+VBE1), where VCE1(SAT) and VBE1correspond to saturation and base-emitter voltages that are associated with the XFP. Similarly, the low drive signal to XFN must swing to (VEE−VCE2(SAT)+VBE2), where VCE2(SAT) and VBE2correspond to saturation and base-emitter voltages that are associated with the XFN.

The drive level requirements of the output stage are slightly different for a FET based implementation (seeFIG. 2). For example, the high drive signal must swing to (VCC−VDS1(SAT)+VT1+VOD1), where VOD1is the minimum overdrive required by the high driver for saturation. Similarly, the low drive signal must swing to (VEE−VDS2(SAT)+VT2+VOD2), where VOD2is the minimum overdrive required by the low driver for saturation.

Although amplifier system500is illustrated as a bipolar transistor design, the same type of design may be employed in a FET type of implementation. For a FET implementation, the only current required by the gates of the follower output stage (e.g., see NF and PF inFIG. 2) are transient currents that are required to charge and discharge the gates of the FET devices. Thus, for a FET amplifier implementation the capacitors that are required by the charge-pump may be integrated on-chip. Moreover, by isolating the follower output stage current from the amplifier current, the overall power consumption in the amplifier is reduced when compared to other designs such as open collector or open drain outputs.