Nonvolatile memory device, memory system, and read method thereof

A non-volatile memory device performs a read operation for compensating for coupling due to an adjacent memory cell. With the read operation of the non-volatile memory device, the coupling effect included in a read result of the selected memory cell is compensated on the basis of a program state of an adjacent memory cell adjacent to the selected memory cell. Toward this end, a read operation for the adjacent memory cell is selectively performed before the selected memory cell is read. Upon sensing of data from the selected memory cell, one or more read operations for the selected memory cell are performed according to the program state of the adjacent memory cell with a read voltage being changed in level depending on the program state of the adjacent memory cell.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims the benefits, under 35 U.S.C. §119, of Korean Patent Application No. 10-2010-0118953 filed Nov. 26, 2010, the entirety of which is incorporated by reference herein.

BACKGROUND

Exemplary embodiments relate to a semiconductor memory device, and more particularly, relate to a non-volatile memory device, a memory system, and a read method thereof.

2. Description of the Related Art

Semiconductor memory devices may be generally classified into volatile memory devices and non-volatile memory devices. Volatile memory devices may lose stored contents when a supply of power is removed therefrom, while non-volatile memory devices may retain stored contents even when a supply of power is removed therefrom. Non-volatile memory devices may be formed of various types of memory cell transistors. Non-volatile memory devices may include flash memory device, ferroelectric random access memory (FRAM) devices, magnetic RAMs (MRAMs), phase change RAMs (PRAMs), or the like.

As one type of non-volatile memory device, flash memory devices, may be divided into NOR type flash memory devices and NAND flash memory devices according to connection relationships of memory cells and bit lines. NOR flash memory devices may have a structure wherein two or more memory cell transistors are connected to one bit line in parallel. Accordingly, NOR flash memory devices may have an excellent random access time characteristic. On the other hand, NAND flash memory devices may have a structure wherein two or more memory cells are connected to one bit line in series. This structure is called a cell string structure. One cell string may require one bit line contact. Accordingly, NAND flash memory devices may have an excellent device integration characteristic.

Memory cells of a flash memory device may be determined to be ON cells or OFF cells according to a threshold voltage distribution. An ON cell may represent an erased cell, and an OFF cell may represent a programmed cell. A programmed memory cell may have one threshold voltage belonging to one of a plurality of threshold voltage distributions each corresponding to N program states (or, programmed data values) (N being an integer of 1 or more).

At programming, a coupling effect may occur between selected memory cell and adjacent memory cell. The coupling effect may make a threshold voltage distribution corresponding to the selected memory cell become wide and a margin between adjacent threshold voltage distributions become narrow. Such a coupling effect may be called “electric field coupling” or “F-poly coupling”. If a variation of the threshold voltage distribution corresponding to the selected memory cell and a reduction of the margin between adjacent threshold voltage distributions are caused due to the coupling effect, it is impossible to reliably read data from memory cells. This problem may increase in proportion to an increase in the number of data bits being stored per cell.

SUMMARY

One object of embodiments of the inventive concept is directed to improving the reliability of data by compensating for the coupling effect between memory cells.

Another object of embodiments of the inventive concept is directed to improving speed up an operating speed.

One aspect of embodiments of the inventive concept is directed to providing a method of reading data from a selected memory cell of a non-volatile memory device. The method comprises sensing data stored in an adjacent memory cell which is adjacent to the selected memory cell; temporarily storing the sensed data of the adjacent memory cell; sensing data stored in the selected memory cell at least once, wherein the sensing is based on the temporarily stored data of the adjacent memory cell; and temporarily storing the sensed data of the selected memory cell, wherein the stored data of the adjacent memory cell is temporarily stored up to a point of time of when sensing a second adjacent memory cell which is adjacent to a second selected memory cell from which data is to be read.

In one or more embodiments, the selected memory cell stores at least two bits of data each accessed according to a page address, and wherein the sensing data stored in the selected memory cell includes sensing first one of the bits of data of the selected memory cell.

In one or more embodiments, the method further comprises sensing a second one of the bits of data of the selected memory cell based on the sensed data of the adjacent memory cell; and temporarily storing the sensed second bit of data of the selected memory cell.

In one or more embodiments, the method further comprises outputting the sensed first bit of data of the selected memory cell, wherein sensing the second bit of data of the selected memory cell and temporarily storing the sensed second data of the selected memory cell are performed before outputting the sensed first data of the selected memory cell.

In one or more embodiments, the stored second data of the selected memory cell is maintained until a read operation on the second data is requested.

In one or more embodiments, sensing the data stored in the selected memory cell comprises applying a read voltage to a selected word line at least once.

In one or more embodiments, the read voltage has a first voltage level that is determined according to a first threshold voltage distribution of the selected memory cell when the selected memory cell does not experience coupling of voltage due to the adjacent memory cell; and a second voltage level that is determined according to a second threshold voltage distribution of the selected memory cell when the selected memory cell experiences the coupling of voltage due to the adjacent memory cell.

In one or more embodiments, the first voltage level is less than the second voltage.

In one or more embodiments, sensing the data stored in the adjacent memory cell comprises determining whether a program state of the adjacent memory cell is a program state which imposes a coupling effect upon the selected memory cell.

In one or more embodiments, temporarily storing the sensed data of the adjacent memory cell comprises storing information indicating whether a program state of the adjacent memory cell is a program state which imposes the coupling effect upon the selected memory cell.

In one or more embodiments, a reading operation is performed for the non-volatile memory device in a sequential manner corresponding to a sequential increase of a page address.

Another aspect of embodiments of the inventive concept is directed to providing a non-volatile memory device. The non-volatile memory device comprises a memory cell array including a selected memory cell connected with a selected word line and an adjacent memory cell connected to a word line adjacent to the selected word line; a data input/output circuit configured to read data of the selected memory cell and the adjacent memory cell and to temporarily store the read data of the selected memory cell and the adjacent memory cell; and control logic configured to control the data input/output circuit to perform at least one read operation on the selected memory cell based on the data of the adjacent memory cell temporarily stored in the data input/output circuit, wherein the data input/output circuit retains the temporarily stored data of the adjacent memory cell until a read operation of a second selected memory cell is being executed to read the second selected memory cell.

In one or more embodiments, the selected memory cell stores at least two bits of data each accessed according to a page address, and wherein the control logic controls the data input/output circuit to read first data and second data of the selected memory cell based on the temporarily stored data of the adjacent memory cell and to temporarily store the read first data and second data.

In one or more embodiments, the data input/output circuit retains the second data until a read operation for the second data of the selected memory cell is requested.

In one or more embodiments, the non-volatile memory device further comprises a voltage generator configured to apply a read voltage to the selected word line and the adjacent word line.

In one or more embodiments, the voltage generator generates different read voltages for reading data stored in the selected memory cell once or several times, under a control of the control logic.

In one or more embodiments, each of the different read voltages has one of a first voltage level that is determined according to a first threshold voltage distribution of the selected memory cell when the selected memory cell does not experience coupling due to the adjacent memory cell; and a second voltage level that is determined according to a second threshold voltage distribution of the selected memory cell when the selected memory cell experiences the coupling due to the adjacent memory cell.

In one or more embodiments, the data input/output circuit temporarily stores data indicating whether a program state of the adjacent memory cell is a program state that imposes a coupling effect upon the selected memory cell.

In one or more embodiments, the memory cell array comprises a substrate and a plurality of cell strings provided on the substrate, wherein each of the plurality of cell strings includes a plurality of cell transistors stacked in a direction perpendicular to the substrate.

Still another aspect of embodiments of the inventive concept is directed to providing a memory system which comprises a non-volatile memory device; and a controller configured to control the non-volatile memory device according to a request of a host device. The non-volatile memory device comprises: a memory cell array including a selected memory cell and a memory cell adjacent to the selected memory cell, the selected memory cell storing at least two bits of data each accessed according to a page address; a data input/output circuit configured to read data of the selected memory cell and the adjacent memory cell and to temporarily store the read data of the selected memory cell and the adjacent memory cell; and control logic configured to control the data input/output circuit to perform one or more read operations on the selected memory cell based on the data of the adjacent memory cell temporarily stored in the data input/output circuit. The data input/output circuit retains the temporarily stored data of the adjacent memory cell until a read operation of another selected memory cell is being executed to read the other selected memory cell. The control logic controls the data input/output circuit to read first data and second data of the selected memory cell based on the temporarily stored data of the adjacent memory cell, and to temporarily store the read first and second data.

Still another aspect of embodiments of the inventive concept is directed to providing a method of reading data from a selected memory cell of a memory device having a plurality of memory cells. The method comprises: sensing data stored in an adjacent memory cell which is adjacent to the selected memory cell; selecting a voltage level for a first read voltage, including selecting a first voltage level when the sensed data of the adjacent memory cell has a first state, and selecting a second voltage level different from the first voltage level when the sensed data of the adjacent memory cell has a second state different from the first state; applying the first read voltage having the selected voltage level to the selected memory cell; and reading first data from the selected memory cell in response to the first read voltage having the selected voltage level.

DETAILED DESCRIPTION

FIG. 1is a block diagram of a non-volatile memory device100according to an exemplary embodiment of the inventive concept. Below, the inventive concept will be exemplarily described under the assumption that a non-volatile memory device may be a NAND flash memory device. But, it is well understood that the non-volatile memory device is not limited to the NAND flash memory device. That is, a non-volatile memory device and its operating characteristic being described below may be applied to non-volatile memory devices such as a NAND flash memory device, a NOR flash memory device, a phase-change RAM (PRAM), a ferroelectric RAM (FRAM), a magnetic RAM (MRAM), etc. and various types of flash memory devices regardless of charge storing layer structure.

A read operation of a flash memory device100according to an exemplary embodiment of the inventive concept may remove the coupling effect included in a read result of a selected memory cell, based on a program state of a memory cell (hereinafter, referred to as an “adjacent memory cell”) adjacent to the selected memory cell. For this, a read operation on the adjacent memory cell may be selectively carried out prior to reading data from the selected memory cell. Upon sensing of data from the selected memory cell, one or more read operations may be performed according to the program state of the adjacent memory cell, with a read voltage during each read operation being changed in level when the program state of the adjacent memory cell may cause coupling to the selected memory cell from a level that would be applied when the adjacent memory cell does not cause coupling to the selected memory cell.

Referring toFIG. 1, flash memory device100may include a memory cell array110, a row decoder120, a data input/output circuit130, an input/output buffer140, control logic150, and a voltage generator160.

Memory cell array110may store data and include a plurality of memory blocks BLK0to BLKn. Each of the plurality of memory blocks BLK0to BLKn may be formed of a plurality of pages each having a plurality of memory cells. With this structural characteristic, flash memory device100may perform read and program operations by the page and an erase operation by the block.

Row decoder120may be connected with memory cell array110via a plurality of word lines (WLs). Row decoder120may select a word line of memory cell array110according to a received row address. Row decoder120may transfer word line voltages from voltage generator160to a selected word line. For example, during a programming operation, row decoder120may transfer a program voltage Vpgm or a program verify voltage Vvfy from voltage generator160to the selected word line, and may transfer a pass voltage Vpass therefrom to unselected word lines. At reading, row decoder120may transfer a selection read voltage Vrd from voltage generator160to a selected word line and a non-selection read voltage Vread therefrom to unselected word lines.

Data input/output circuit130may include a plurality of data input/output circuits130_0to130_m, which are connected to a plurality of corresponding bit lines BL0to BLm. Data input/output circuit130may operate as a write driver or as a sense amplifier according to a mode of operation. For example, during a read operation, data input/output circuit130may read data stored in a selected memory cell via a bit line. During a programming operation, data input/output circuit130may program input data in a selected memory cell. Data input/output circuit130may operate responsive to the control of control logic150.

A read operation executed by data input/output circuit130may include a read operation (also called a normal read operation) and a program verify operation (also called a verify read operation). The program verify operation may be carried out to be identical to the read operation except read data is not provided or output from flash memory device100. The read operation may be performed with respect to memory cells connected with a selected word line, in units of one or more pages.

Input/output buffer140may temporarily store an address, data, and a command received via input/output pins. Input/output buffer140may transfer the stored address to an address register (not shown), the stored data to data input/output circuit130, and the stored command to a command register (not shown). During a read operation, input/output buffer140may transfer data from data input/output circuit130to an external device.

Control logic150may control an overall operation of flash memory device100in response to a command and a control signal from an external device (e.g., a host, a memory controller, a memory interface, or the like). For example, control logic150may control read, program (or write), and erase operations of flash memory device100. For the read, program (or write), and erase operations, control logic150may control voltage generator160to generate a bias voltage.

A read operation according to an exemplary embodiment of the inventive concept may be carried out by control logic150, data input/output circuit130, and voltage generator160. That is, control logic150may control data input/output circuit130and voltage generator160according to the read operation of the inventive concept. With the read operation executed under the control of control logic150, data may be first read out from an adjacent memory cell of a selected memory cell. Upon sensing of data from the selected memory cell, control logic150may control voltage generator160such that a read voltage having a voltage level among a first voltage level Vrd_a and a second voltage level Vrd_b, which are different from each other, is provided to a selected word line according to a program state of the adjacent memory cell. That is, during a read operation, control logic150may control data input/output circuit130and voltage generator160such that the selected memory cell is sensed by a read voltage having one of two different levels, respectively, which are selected depending on the program state of the adjacent memory cell.

As understood from the above description, a read operation may be exactly performed even though a threshold voltage distribution corresponding to a selected memory cell is changed due to the electric field coupling or F-poly coupling caused by an adjacent memory cell. Also, since a program state of the adjacent memory cell is temporarily stored by data input/output circuit130, it is possible to shorten a time needed for a read operation of a selected memory cell.

FIG. 2is an equivalent circuit diagram of a memory cell array illustrated inFIG. 1. InFIG. 2, there is exemplarily illustrated one memory block BLKn included in memory cell array110inFIG. 1.

The memory block BLKn may include a plurality of cell strings each connected with a plurality of bit lines BL0to BLm. Each of the cell strings may include a plurality of memory cells connected between a corresponding bit line and a common source line CSL. For example, a cell string may include a plurality of memory cells M0_0to Mi+1_0connected between a corresponding bit line BL0and the common source line CSL. Each cell string may further include a string select transistor SST connected with a string select line SSL and a ground select transistor GST connected with a ground select line GSL. In each cell string, the string select transistor SST is connected with a corresponding bit line, and the ground select transistor GST is connected with the common source line CSL.

Memory cells connected with each of word lines WL0to WLi+1 may constitute a page. For example, memory cells M0_0to M0_m connected with the word line WL0may constitute one page. In case of a multi-level cell (MLC) storing n-bit data (n being an integer of 2 or more), memory cells connected with one word line may constitute plural pages. If page addresses are scrambled, the page order may be different from a word line order. A page may represent the unit of a read or program operation. Accordingly, a read or program operation may be carried out according to a page order.

The term “an adjacent memory cell” may be used as a descriptive term. An adjacent memory cell may include a memory cell which is connected with a word line (hereinafter, referred to as an adjacent word line) adjacent (or immediately adjacent) to a selected memory cell. The adjacent memory cell may be a memory cell being programmed following a selected memory cell and may affect a threshold voltage of the selected memory cell.

It is assumed that a memory cell Mi_0is a selected memory cell. With this assumption, a word line WLi connected with the selected memory cell Mi_0may be a selected word line, and a word line adjacent (e.g., immediately adjacent) to the selected word line WLi may be an adjacent word line WLi+1. Among memory cells connected with the adjacent word line WLi+1, a memory cell Mi+1_0may be a memory cell which is adjacent (e.g., immediately adjacent) to the selected memory cell Mi_0, is programmed following the selected memory cell Mi_0, and affects a threshold voltage of the selected memory cell.

A threshold voltage of the selected memory cell may be affected according to a program state (or, a threshold voltage) of the adjacent memory cell. For example, a threshold voltage of the selected memory cell may be increased or decreased unintentionally due to the electric field coupling or F-poly coupling caused between the selected memory cell and the adjacent memory cell. This will be more fully described with reference toFIGS. 3 and 4.

FIGS. 3 and 4are diagrams for describing the electric field coupling caused between adjacent memory cells.

For ease of description, inFIG. 3, there are exemplarily illustrated threshold voltage distributions of multi-level cells each storing 2-bit data. But, it is well understood that the inventive concept may be applied to multi-level cells each storing 3 or more bits of data. In the case of a multi-level cell storing 2-bit data, the 2-bit data may be formed of lower page data and upper page data which may be stored therein independently.

If one memory cell stores 2-bit data, it may have a threshold voltage in one of four threshold voltage distributions E, P1, P2, and P3. Each of the threshold voltage distributions E, P1, P2, and P3may correspond to any one of the possible data states, that is, data ‘11’, data ‘01’, data ‘00’, and data ‘10.’ For example, a threshold voltage distribution E representing an erase state may correspond to data ‘11,’ a threshold voltage distribution P1representing a program state may correspond to data ‘01,’ a threshold voltage distribution P2representing another program state may correspond to data ‘00,’ and a threshold voltage distribution P3representing yet another program state may correspond to data ‘10.’

Herein, correspondence between threshold voltage distributions E, P1, P2, and P3and data states ‘11’, ‘01’, ‘00’, and ‘10’ is not limited to this disclosure. The correspondence between threshold voltage distributions and data states may be changed variously according to a memory design.

InFIG. 3, solid lines E_0to P3_0may represent threshold voltage distributions which are formed within a given threshold voltage window. In this case, threshold voltage distributions P1_0and P2_) may be formed with a predetermined margin MG0. InFIG. 3, dotted lines E_1to P3_1and E_2to P3_2may represent threshold voltage distributions shifted when coupling is generated according to program state(s) of one or more adjacent memory cells.

InFIG. 4, it is assumed that a memory cell Mi_0is connected with a word line WLi and is programmed to have one of four states E, P1, P2, and P3. Further, it is assumed that a memory cell Mi+1_0is connected with a word line WLi+1 and is programmed to have one of four states E, P1, P2, and P3. The word line WLi+1 may be an adjacent (e.g., immediately adjacent) word line placed above the word line WLi. If a program operation is carried out according to a page order, the memory cell Mi_0connected with the word line WLi may be programmed, and then the memory cell Mi+1_0connected with the word line WLi+1 may be programmed.

When the memory cell Mi+1_0is programmed, charges may be accumulated on its floating gate. This means that a threshold voltage of the memory cell Mi+1_0increases. At this time, a potential of a floating gate of the previously programmed memory cell Mi_0may be increased due to the coupling with the floating gate of the memory cell Mi+1_0. The increased potential of the floating gate of the memory cell Mi_0may be maintained even after programming of the memory cell Mi+1_0is completed.

The coupling imposed on the memory cell Mi_0may be caused from all adjacent memory cells which are placed in the word line direction or the bit line direction of the memory cell Mi_0. A threshold voltage of the programmed memory cell Mi_0may be increased due to the coupling. That is, threshold voltage distributions may be widened as illustrated by the dotted lines E_1to P3_1and E_2to P3_2inFIG. 3. As threshold voltage distributions are widened due to the coupling, the margin between adjacent threshold voltage distributions may be reduced from MG0to MG2. This means that the error probability is increased for a sensing operation.

The more there is a variation of program states of adjacent memory cells, the more there may be a variation of a threshold voltage distribution due to the coupling. For example, the solid lines E_0to P3_0may represent threshold voltage distributions when adjacent memory cells have an erase state E. That is, when adjacent memory cells have an erase state E, the nearby coupling may be minimal or nil. The dotted lines E_1to P3_1may represent threshold voltage distributions when adjacent memory cells have a program state P2. Here, the coupling may be relatively small. On the other hand, the dotted lines E_2to P3_2may represent threshold voltage distributions when adjacent memory cells have a program state P1or a program state P3. That is, when adjacent memory cells are programmed to have a program state P1or a program state P3, the coupling may be greater.

With an exemplary embodiment of the inventive concept, the coupling effect included in a read result of selected memory cells may be counteracted according to a program status of adjacent memory cells. For this, a read operation on adjacent memory cells may be carried out prior to read data from selected memory cells. Upon sensing of data from the selected memory cells, one or more read operations may be performed according to the program status of the adjacent memory cells, with a read voltage being changed in level when the program state of the adjacent memory cells is one that causes coupling to the selected memory cells, from the level that would be employed when the program state of the adjacent memory cells is one that does not cause coupling to the selected memory cells.

FIG. 5is a block diagram of a data input/output circuit of a non-volatile memory device according to an exemplary embodiment of the inventive concept. Referring toFIG. 5, a data input/output circuit130may include a plurality of data input/output circuits130_0to130_m each corresponding to bit lines BL0to BLm. The data input/output circuits130_0to130_m may be configured to be the same as one another. The data input/output circuits130_0to130_m may be configured as follows.

Data input/output circuits130_0to130_m may each include a precharge circuit131and a data latch circuit132.

For of the input/output circuits130_0to130_m, the corresponding precharge circuit131is connected with the corresponding bit line and the corresponding data latch circuit132. During a reading operation, precharge circuit131may precharge the corresponding bit line with a predetermined voltage in response to a control signal PRE. Precharge circuit131may be formed of a transistor which provides a precharge voltage to the corresponding bit line.

Each data latch circuit132may be connected to the corresponding bit line. Data latch circuit132may include a plurality of data latches. The number of data latches in data latch circuit132may differ according to the number of bits-per-cell. During a read operation, data latch circuit132may sense data stored in a memory cell and store the sensed result in one or more data latches in response to a corresponding latch control signal LCH.

A precharge operation may be carried out before a sensing operation which is executed with respect to a memory cell connected with a selected bit line. After the precharge operation of the selected bit line, a precharged voltage of the selected bit line may vary according to a data value programmed in a selected memory cell during a predetermined sensing period. After the predetermined sensing period, data latch circuit132may sense a voltage of a sensing node (placed between a precharge circuit and a data latch circuit) and store the sensed result in one or more data latches.

As described above, data latch circuit132may include a plurality of data latches. At least one of data latches included in each of data input/output circuits130_0to130_m may be used to sense a selected memory cell and store the sensed result. Among remaining data latches included in each of data input/output circuits130_0to130_m, at least one data latch may be used to sense an adjacent memory cell and store the sensed result.

Data of an adjacent memory cell stored in one or more data latches may be used to adjust an applied read voltage level upon sensing of data from a selected memory cell. Thus, it is possible to compensate for the coupling effect imposed on the selected memory cell according to a program state of the adjacent memory cell.

FIG. 6is a flowchart for describing a read operation according to the first embodiment of the inventive concept. A read operation according to the first embodiment of the inventive concept will be described under the assumption that a memory cell is a multi level cell storing 2-bit data. In this case, data of memory cells connected with one word line may be formed into two pages, that is, a lower page and an upper page. Further, it is assumed that read and program operations are executed according to a page order. Below, a page to be read will be referred to as a selected page.

In step S100, it may be determined whether a flash memory device is set to perform a coupling compensation read operation. Setting up of the flash memory device may be made in a memory fabricating process and changed by a request of a user.

If the flash memory device is not set to perform a coupling compensation read operation, the method proceeds to step S150, in which a general or normal read operation is performed with respect to a selected page of a selected word line. In step S140, data of the selected memory cell stored in one or more data latches may be provided to an external device.

If the flash memory device is set to perform a coupling compensation read operation, a read operation of the selected memory cell may be performed according to the coupling compensation read method, which will be more fully described in the following steps S110to S140.

In step S110, a read operation for an adjacent memory cell connected with an adjacent word line may be performed prior to a read operation for the selected memory cell. As described above, data stored in memory cells of a word line may be formed of two pages. Accordingly, if a read operation of the adjacent memory cell is performed, lower page data and upper page data of adjacent memory cells may be stored in one or more data latches, respectively. In step S120, the program state of the adjacent memory cell may be determined according to data stored in the one or more data latches (that is, whether the adjacent memory cell is programmed). The selected memory cell may experience the coupling only when the adjacent memory cell is programmed. Thus, if the adjacent memory cell is not programmed (e.g., if adjacent memory cells in the adjacent word line all are not programmed), the method proceeds to step S150, in which a general read operation is carried out on the selected memory cell.

If the adjacent memory cell is programmed (e.g., if at least one of adjacent memory cells in the adjacent word line is programmed), the method proceeds to step S130, in which the selected page of the selected word line is read according to the coupling compensation read method, which is different from the general read method. With the coupling compensation read method, one or more read operations may be carried out with a read voltage of the selected word line being changed in level from the level that would be employed in the general or normal read operation at step S150. The coupling compensation read method will be more fully described below with respect toFIGS. 7 and 8. Afterwards, data of the selected memory cell read according to the coupling compensation read method may be provided to the external device via input/output buffer140.

FIGS. 7 and 8are diagrams for describing a read operation according to the first embodiment of the inventive concept. InFIGS. 7 and 8, there are illustrated read voltage levels according to an operation described in step S110ofFIG. 6and a coupling compensation read operation described in step S130ofFIG. 6. In particular,FIG. 7shows read voltage levels that may be applied when lower (LSB) page data of a selected memory cell is read in a coupling compensation read manner.FIG. 8shows read voltage levels that may be applied when upper (MSB) page data of the selected memory cell is read in the coupling compensation read manner.

During a read operation for adjacent memory cells, an adjacent word line may be supplied with read voltages Vrd1, Vrd2, and Vrd3for reading LSB page data and MSB page data. An order of applying the read voltages Vrd1, Vrd2, and Vrd3may be determined sequentially in an ascending order, that is, from a lower voltage to a higher voltage. Alternatively, the read voltage Vrd2for reading LSB page data of the adjacent memory cells may be firstly applied to the adjacent word line, and then the read voltages Vrd1and Vrd3for reading MSB page data of the adjacent memory cells may be applied to the adjacent word line. A program state of the adjacent memory cells may be determined by sensing data from the adjacent memory cells with the read voltages Vrd1, Vrd2, and Vrd3being applied to the adjacent word line.

Upon reading LSB page data of the selected memory cell, a read voltage Vrd2having either the first voltage level Vrd2_a or the second voltage level Vrd2_b, which are different than each other, may be applied to the selected word line according to a program state of the adjacent memory cell. A read operation may be carried out whenever the read voltage Vrd having one of the first and second voltage levels Vrd2_a and Vrd2_b, respectively, is applied to the selected word line. If one or more read operations are performed with a read voltage level changed, a read margin may be maintained although a threshold voltage of the selected memory cell is shifted due to the coupling. Accordingly, the data reliability may be improved.

The first and second voltage levels Vrd2_a and Vrd2_b may be determined, respectively, considering the case where the selected memory cell experiences the coupling due to the adjacent memory cell, and the case where the selected memory cell does not experience the coupling due to the adjacent memory cell. That is, the first voltage level Vrd2_a may be determined considering a threshold voltage distribution NCP of the selected memory cell when the selected memory cell does not experience the coupling due to the adjacent memory cell. The second voltage level Vrd2_b may be determined considering a threshold voltage distribution CP of the selected memory cell when the selected memory cell experiences the coupling due to the adjacent memory cell. Accordingly, the second voltage level Vrd2_b may be greater than the first voltage level Vrd2_a.

Upon reading MSB page data of the selected memory cell, read voltages Vrd1(having possible voltage levels Vrd1_a or Vrd1_b) and Vrd3(having possible voltage levels Vrd3_a or Vrd3_b) may be applied sequentially to the selected word line according to a program state of the adjacent memory cell. A read operation may be carried out whenever the read voltages Vrd1and Vrd3are applied to the selected word line, respectively. The voltage levels Vrd1_a and Vrd3_a may be determined considering a threshold voltage distribution of the selected memory cell when the selected memory cell does not experience the coupling due to the adjacent memory cell. The voltage levels Vrd1_b and Vrd3_b may be determined considering a threshold voltage distribution of the selected memory cell when the selected memory cell experiences the coupling due to the adjacent memory cell.

With the above-described read procedure, a read operation of an adjacent memory cell may be carried out prior to read a selected memory cell. That is, a read operation of the adjacent memory cell may be carried out prior to reading LSB page data of the selected memory cell. A read operation of the adjacent memory cell may be carried out prior to reading MSB page data of the selected memory cell. As a result, a read margin may be maintained although a threshold voltage of the selected memory cell is shifted due to the coupling. Accordingly, the data reliability may be improved.

FIG. 9is a flowchart for describing a read operation according to a second embodiment of the inventive concept. A read operation according to the second embodiment of the inventive concept will be described under the assumption that a memory cell is a multi level cell storing 2-bit data. In this case, data of memory cells connected with one word line may be formed into two pages, that is, a lower page and an upper page. Further, it is assumed that read and program operations are executed according to a page order. Below, a page to be read will be referred to as a selected page.

In step S200, it may be determined whether a flash memory device is set to perform a coupling compensation read operation. Setting up of the flash memory device may be made in a memory fabricating process and changed by a request of a user.

If the flash memory device is not set to perform a coupling compensation read operation, the method proceeds to step S290, in which a general read operation is performed with respect to a selected page of a selected word line. In step S280, data of the selected memory cell stored in one or more data latches may be provided to an external device.

If the flash memory device is set to perform a coupling compensation read operation, a read operation of the selected memory cell may be performed according to the coupling compensation read method, which will be more fully described in the following steps S210to S280.

First of all, in step S210, it may be determined whether data of the selected memory cell is stored in one or more data latches. The coupling compensation read operation may be carried out according to whether data of the selected memory cell is stored in one or more data latches. If data of the selected memory cell is stored in one or more data latches, the method proceeds to step S280without execution of a read operation. In step S280, data of the selected memory cell stored in the one or data latches may be provided to an external device.

If data of the selected memory cell is not stored in one or more data latches, the method proceeds to step S220, in which a read operation for the adjacent memory cell connected with the adjacent word line is performed prior to read the selected memory cell. As described above, data in memory cells of a word line may be formed of two pages. Accordingly, if a read operation for the adjacent memory cell is performed, LSB and MSB page data thereof may be stored in data latches, respectively.

Data of the adjacent memory cell stored in the data latch(es) may be maintained until there is carried out a read operation for another adjacent memory cell which is performed prior to reading another selected memory cell, in step S230. Alternatively, data of the adjacent memory cell stored in the data latch(es) may be maintained until a read operation for an unselected page of the selected word line is carried out. As a result, it is possible to reduce the number of read operations for the adjacent memory cell since data of the adjacent memory cell is referred to as occasion demands.

In step S240, a program state of the adjacent memory cell may be determined based on the data stored in the data latch(es). The selected memory cell may experience the coupling only when the adjacent memory cell is programmed. Accordingly, if the adjacent memory cell is not programmed (or, if all adjacent memory cells in the adjacent word line are not programmed), data of the selected memory cell may be read according to the general read manner in step S290.

If the adjacent memory cell is programmed (or, if any one or more of the adjacent memory cells in the adjacent word line is programmed), in step S250data of the selected memory cell may be read according to the coupling compensation read manner. That is, the selected page of the selected word line may be read via the coupling compensation read operation. The coupling compensation read operation of the selected page may include performing one or more read operations which use different read voltages, respectively. Each of these read voltages may have a different voltage level in a coupling compensation read operation than they would have in the normal or general read operation where the adjacent memory cells do not cause coupling to the selected memory cell That is, as described inFIGS. 7 and 8, one or more read operations for the selected page may be carried out using one or more read voltages which have voltage levels that are each determined according to whether the selected memory cell experiences the coupling due to the adjacent memory cell or not.

After the selected page is read and stored in one or more data latches, in step S260an unselected page of the selected word line may be read via the coupling compensation read operation. This may be carried out referring to data of the adjacent memory cell stored in step S230. If the unselected page of the selected word line is read, in step S270, data of the unselected page may be stored in and maintained by one or more data latches. The data of the unselected page stored in the data latch(es) may be provided to an external device via input/output buffer140upon a following read request on the unselected page.

After data for a read operation (i.e., a read operation on an unselected page of the selected word line) being expected following the read operation on the selected page is prepared, in step S280, data of the selected memory cell stored in the data latch(es) may be provided to an external device via input/output buffer140.

With the second embodiment of the inventive concept, a read operation for an adjacent memory cell may be carried out before a selected memory cell is read. Data read from the adjacent memory cell may be retained for a predetermined time period. A coupling compensation read operation may be performed to read a selected page (e.g., a lower page) of the selected memory cell, based on the data of the adjacent memory cell. Further, there may be made a coupling compensation read operation on an unselected page (e.g., an upper page) of the selected memory cell which is expected to be requested later. At this time, reference may be made to data of the adjacent memory cell stored in data latches. Data of the unselected page (e.g., an upper page) of the selected memory cell may be maintained for a predetermined time period. The data of the unselected page may be provided to an external device upon a read request on the unselected page (e.g., an upper page).

As understood from the above description, although a threshold voltage of a selected memory cell is shifted due to the coupling, a read margin may be maintained. This means that the data reliability is improved. Further, the number of read operations that are performed for an adjacent memory cell may be reduced, and a read speed may be improved since data to be requested later is prepared in advance.

FIG. 10is a diagram for describing a read operation according to the second embodiment of the inventive concept. InFIG. 10, there is illustrated a table of data stored in data latches DL0to DL4when a coupling compensation read operation is carried out. Further, inFIG. 10, there is illustrated a manner of scrambling page addresses in the event that a memory cell is a multi level cell (MLC) storing 2 bits of data. It is assumed that a read operation is performed in a page order with all pages being programmed.

If a read operation of a page P0commences, first of all, data may be read from adjacent memory cells connected with an adjacent word line WL1. Lower (LSB) page data of the adjacent memory cells are stored in data latch(es) DL0, and upper (MSB) page data of the adjacent memory cells are stored in data latch(es) DL1.

A selected page P0of the selected word line WL0may be read according to a coupling compensation read manner based on a program state of the adjacent memory cells stored in the data latch(es) DL0and DL1. Read data of the selected page may be stored in data latch(es) DL4.

Then, an unselected page P2of the selected word line WL0may be read according to a coupling compensation read manner based on a program state of the adjacent memory cells as indicated by the data stored in the data latches DL0and DL1. Data of the adjacent memory cells stored in the data latches DL0and DL1may be retained continuously. Data of the unselected page P2may be stored in data latches DL3. Afterwards, data of the selected page P0stored in the data latches DL4may be provided to an external device via input/output buffer140.

After the page data P0is output, a read operation of a page P1may be carried out sequentially. If a read operation of the page P1is performed, data may be read out from memory cells connected with an adjacent word line WL2. Likewise, LSB page data of adjacent memory cells in the adjacent word line WL2may be stored in the data latch(es) DL0, and MSB page data thereof may be stored in the data latch(es) DL1.

Data of the selected page P1in the selected word line WL1may be read according to the coupling compensation read manner, based on a program state of the adjacent memory cell as indicated by the data stored in the data latches DL0and DL1. The read data of the selected page P1may be stored in the data latch(es) DL4.

Afterwards, data of an unselected page P4in the selected word line WL4may be read according to the coupling compensation read manner, based on a program state of the adjacent memory cells as indicated by the data stored in the data latches DL0and DL1. The data of the adjacent memory cells stored in the data latches DL0and DL1may be maintained. Data of the unselected page P4may be stored in data latch(es) DL2. Afterwards, data of the selected page P1stored in the data latch(es) DL4may be provided to the external device via input/output buffer140.

After data of the page P1is output, a read operation of a page P2may be performed sequentially. If the read operation of the page P2is performed, data of the selected page P2stored in the data latch(es) DL3may be shifted into the data latch(es) DL4. The data of the selected page P2stored in the data latch(es) DL4may be provided to the external device via input/output buffer140. Alternatively, the data of the selected page P2stored in the data latch(es) DL3may be provided to the external device via input/output buffer140.

A read operation for the pages which follow may be carried out according to the above-described manner. With the second embodiment of the inventive concept, although a threshold voltage of a selected memory cell is shifted due to the coupling, a read margin may be maintained. This means that the data reliability is improved. Further, the number of read operations that are performed for an adjacent memory cell may be reduced, and a read speed may be improved since data to be requested later is prepared.

FIG. 11is a diagram for describing a read operation according to a third embodiment of the inventive concept. InFIG. 11, there is illustrated a table of data stored in data latches DL0to DL3when a coupling compensation read operation is carried out. A read operation according to the third embodiment of the inventive concept may be identical to a read operation according to the second embodiment of the inventive concept except for a method of storing data of an adjacent memory cell in data latches.

As described inFIG. 3, a variation of a threshold voltage of a selected memory cell due to the coupling may increase as a variation of a program state of an adjacent memory cell becomes large. For example, in a case where a memory cell is programmed to a target program state from any program state, the largest coupling effect may be caused when an adjacent memory cell is programmed to a target program state P1or P3.

With a read method of the third embodiment of the inventive concept, instead of storing data of an adjacent memory cell in data latches, there may be stored whether a program state of the adjacent memory cell is a program state forcing the largest coupling effect to a selected memory cell. For example, one or more data latches may store data indicating whether a program state of the adjacent memory cell is a program state P1or a program state P3. Data of a selected page may be read according to a coupling compensation read method, as described inFIG. 9, when a program state of the adjacent memory cell is a program state P1or a program state P3. With a read method of the third embodiment of the inventive concept, it is possible to reduce the number of data latches needed for the coupling compensation read operation.

FIG. 12is a flowchart for describing a read operation according to a fourth embodiment of the inventive concept.

A read operation according to the fourth embodiment of the inventive concept will be described under the assumption that a memory cell is a multi level cell storing 2-bit data. In this case, data of memory cells connected with one word line may be formed into two pages, that is, a lower page and an upper page. Further, it is assumed that read and program operations are executed according to a page order. Below, a page to be read will be referred to as a selected page.

In step S300, it may be determined whether a flash memory device is set to perform a coupling compensation read operation. Setting up of the flash memory device may be made in a memory fabricating process and changed by a request of a user.

If the flash memory device is not set to perform a coupling compensation read operation, the method proceeds to step S370, in which a general read operation is performed with respect to a selected page of a selected word line. In step S360, data of the selected memory cell stored in a data latch may be provided to an external device.

If the flash memory device is set to perform a coupling compensation read operation, a read operation of the selected memory cell may be performed according to the coupling compensation read method, which will be more fully described in the following steps S310to S360.

First of all, in step S310, it may be determined whether data of the selected memory cell is stored in one or more data latches. If data of the selected memory cell is stored in the data latch(es), the method proceeds to step S340without execution of a read operation for the adjacent memory cell. In step S340, it may be determined whether the adjacent memory cell is programmed.

If data of the selected memory cell is not stored in the data latch(es), the method proceeds to step S320, in which a read operation for the adjacent memory cell connected with the adjacent word line is performed prior to read the selected memory cell. As described above, data in memory cells of a word line may be formed of two pages. Accordingly, if a read operation for the adjacent memory cell, LSB and MSB page data thereof may be stored in data latches, respectively.

As indicated in step330, data of the adjacent memory cell stored in the data latch may be maintained until there is carried out a read operation for all unselected pages of the selected word line. As a result, it is possible to reduce the number of read operations for the adjacent memory cell since data of the adjacent memory cell is referred to as occasion demands.

In step S340, a program state of the adjacent memory cell may be determined based on data stored in the data latch(es). The selected memory cell may experience the coupling only when the adjacent memory cell is programmed. Accordingly, if the adjacent memory cell is not programmed (or, if all adjacent memory cells in the adjacent word line are not programmed), data of the selected memory cell may be read according to the general or normal read operation in step S370.

If the adjacent memory cell is programmed (or, if any one or more of the adjacent memory cells in the adjacent word line is programmed), in step S350data of the selected memory cell may be read according to the coupling compensation read operation as described above. That is, the selected page of the selected word line may be read via the coupling compensation read operation. The coupling compensation read operation of the selected page may include performing one or more read operations which use different read voltages, respectively. Each of these read voltages may have a different voltage level in a coupling compensation read operation than they would have in the normal or general read operation where the adjacent memory cells do not cause coupling to the selected memory cell. That is, as described inFIGS. 7 and 8, one or more read operation for the selected page may be carried out using one or more voltage levels which are determined according to whether the selected memory cell experiences the coupling due to the adjacent memory cell or not. In step S360, data of the selected memory cell stored in the data latch(es) may be provided to the external device via input/output buffer140.

With the fourth embodiment of the inventive concept, a read operation for an adjacent memory cell may be carried out before a selected memory cell is read. Data read from the adjacent memory cell may be retained for a predetermined time period. For example, the read data of the adjacent memory cell may be retained until there is performed a read operation on all unselected pages of the selected memory cell which is expected to be requested later.

As understood from the above description, although a threshold voltage of a selected memory cell is shifted due to the coupling, a read margin may be maintained. This means that the data reliability is improved. Further, the number of read operations that are performed for an adjacent memory cell may be reduced since retained data of the adjacent memory cell is referred at a read operation to be requested later. As a result, a read speed may be improved.

FIG. 13is a diagram for describing a read operation according to the fourth embodiment of the inventive concept. InFIG. 13, there is illustrated a table of data stored in data latches DL0to DL4when a coupling compensation read operation is carried out. Further, inFIG. 10, there is illustrated a manner of scrambling page addresses in the event that a memory cell is a multi level cell MLC storing 2 bits of data. It is assumed that a read operation is performed in a page order with all pages being programmed.

If a read operation of a page P0commences, first of all, data may be read from adjacent memory cells connected with an adjacent word line WL1. Lower (LSB) page data of the adjacent memory cells are stored in data latch(es) DL2, and upper (MSB) page data of the adjacent memory cells are stored in data latch(es) DL3.

A selected page P0of the selected word line WL0may be read according to a coupling compensation read operation based on a program state of the adjacent memory cells stored in the data latches DL2and DL3. Read data of the selected page may be stored in data latch(es) DL4. Afterwards, data of the selected page P0stored in the data latches DL4may be provided to an external device via an input/output buffer140.

After the page data P0is output, a read operation of a page P1may be carried out sequentially. If a read operation of the page P1is performed, data may be read out from memory cells connected with an adjacent word line WL2. Likewise, LSB page data of adjacent memory cells in the adjacent word line WL2may be stored in the data latch(es) DL0, and MSB page data thereof may be stored in the data latch(es) DL1.

Data of the selected page P1in the selected word line WL1may be read according to the coupling compensation read operation, based on a program state of the adjacent memory cell stored in the data latches DL2and DL3. The read data of the selected page P1may be stored in the data latch(es) DL4. Afterwards, data of the selected page P1stored in the data latch(es) DL4may be provided to the external device via input/output buffer140.

After data of the page P1is output, a read operation of a page P2may be performed sequentially. If the read operation of the page P2is performed, data may not be read from memory cells of an adjacent word line WL1. The reason is that data of adjacent memory cells connected with the adjacent word line WL1remains stored in one or more data latches after data of the page P0is read according to the coupling compensation read operation. Thus, data of the selected page P2may be read according to the coupling compensation read operation, based on the retained program state of the adjacent memory cell. The read data of the selected page P2may be stored in data latch(es) DL4. Afterwards, data of the selected page P1stored in the data latch(es) DL4may be provided to the external device via input/output buffer140.

With the fourth embodiment of the inventive concept, although a threshold voltage of a selected memory cell is shifted due to the coupling, a read margin may be maintained. This means that the data reliability is improved. Further, the number of read operations that are performed for an adjacent memory cell may be reduced since retained data of an adjacent memory cell is referred at a read operation to be requested later. Accordingly, a read speed may be improved.

FIG. 14is a block diagram of a memory cell array100inFIG. 1according to another embodiment of the inventive concept.

Referring toFIG. 14, memory cell array110may include a plurality of memory blocks BLK1to BLKn, each of which has a 3D structure (or, a vertical structure). For example, each memory block BLK may include structures extending along the first to third directions as indicated inFIG. 14. For example, each memory block BLK may include a plurality of NAND strings NS extended along the second direction. For example, a plurality of NAND strings NS may extend along the first and third directions.

Each NAND string NS may be coupled with a bit line BL, at least one string selection line SSL, at least one ground selection line GSL, word lines WL, at least one dummy word line DWL, and a common source line CSL. That is, each memory block may be coupled with a plurality of bit lines BL, a plurality of string selection lines SSL, a plurality of ground selection lines GSL, a plurality of word lines WL, a plurality of dummy word lines DWL, and a common source line CSL. The memory blocks BLK1to BLKn will be more fully described with reference toFIG. 15.

FIG. 15is a perspective view of one of the memory blocks BLKi inFIG. 14, andFIG. 16is a cross-sectional view taken along a line I-I′ of memory block BLKi inFIG. 15. Referring toFIGS. 15 and 16, a memory block BLKi includes structures that extend in the first to third directions as indicated inFIG. 15.

First, a substrate111is provided. Exemplarily, substrate111may include a silicon material to which a first type impurity is injected. For example, substrate111may include a silicon material to which a p-type impurity is injected. As an example, substrate111may be a p-type well (or, a pocket p well). For example, substrate111may further include an n-type well which surrounds the p-type well. Hereinafter, it is assumed that substrate111is p-type silicon. However, substrate111is not limited thereto.

A plurality of doping regions311to314extending in the first direction may be provided to substrate111. For example, a plurality of doping regions311to314may have a second type of impurity different from that of substrate111. For example, doping regions311to314may have an n-type impurity, respectively. Hereinafter, it is assumed that first to fourth doping regions311to314are n-type regions. However, first to fourth doping regions311to314are not limited thereto.

In a region on substrate111between first and second doping regions311and312, a plurality of insulating materials112each extending in the first direction may be sequentially provided in the second direction. For example, the plurality of insulating materials112and substrate111may be formed to be separated by a predetermined distance in the second direction. For example, insulating materials112may be separated from each other by a predetermined distance in the second direction. Exemplarily, insulating materials112may include an insulating material such as silicon oxide.

In the region on substrate111between first and second doping regions311and312, a plurality of pillars113may be provided which are sequentially disposed in the first direction and pass through insulating materials112in the second direction. Exemplarily, pillars113may be disposed on substrate111and separated therefrom through insulating materials112, respectively.

Exemplarily, each of pillars113may be formed of a plurality of materials. For example, surface layer114of each pillar113may include a silicon material having the first type. For example, surface layer114of each pillar113may include a silicon material which is doped by same type as substrate111. Hereinafter, it is assumed that surface layer114of each pillar113includes p-type silicon. However, surface layer114of each pillar113is not limited thereto.

Inner layer115of each pillar113may be formed of an insulating material. For example, inner layer115of each pillar113may be filled by an insulating material such as silicon oxide.

In a region between first and second doping regions311and312, an insulation layer116may be provided along the exposed surface of substrate11, insulating materials112, and pillars113. For example, the thickness of insulation layer116may be less than half a distance between insulating materials112. That is, a region where a material other than insulating materials112and insulation layer116may be disposed, may be provided between a portion of insulation layer116provided next to a lower surface of the first insulating material among insulating materials112and a portion of insulation layer116provided next to an upper surface of the second insulating material, and beneath the first insulating material.

In the region between first and second doping regions311and312, conductive materials211to291may be provided onto an exposed surface of insulation layer116. For example, conductive material211extending in the first direction may be provided between substrate111and insulating material112adjacent to substrate111. More specifically, conductive material211extending in the first direction may be provided between substrate111and insulation layer116of the lower surface of insulating material112adjacent to substrate111.

A conductive material extending in the first direction may be provided between: (1) a portion of insulation layer116disposed next to an upper surface of a specific insulating material among insulating materials112, and (2) a portion of insulation layer116disposed next to a lower surface of an insulating material disposed above the specific insulating material. Exemplarily, conductive materials221to281extended in the first direction may be provided between insulating materials112. Exemplarily, first conductive materials211to291may be metal materials. Exemplarily, conductive materials211to291may be conductive materials such as polysilicon.

The same structure as first and second doping regions311and312may be provided between second and third doping regions312and313. Between second and third doping regions312and313, exemplarily, there may be provided insulating materials112extending in the first direction, pillars113sequentially disposed in the first direction and passing through insulating materials112in the third direction, insulation layer116on insulating materials112and exposed surfaces of pillars113, and conductive materials212to292extending in the first direction.

The same structure as a structure on first and second doping regions311and312may be provided between third and fourth doping regions313and314. Between third and fourth doping regions313and314, exemplarily, there may be provided insulating materials112extending in the first direction, pillars113sequentially disposed in the first direction and passing through insulating materials112in the third direction, insulation layer116on insulating materials112and the exposed surfaces of pillars113, and conductive materials213to293extending in the first direction.

Drains320may be provided onto pillars113, respectively. Exemplarily, drains320may be silicon materials that are doped in a second type. For example, drains320may be silicon materials that are doped in an n-type. Hereinafter, it is assumed that drains320may include n-type silicon. However, drains320are not limited thereto. Exemplarily, the width of each of drains320may be greater than that of a corresponding pillar113. For example, each drain320may be provided in a pad shape on the upper surface of a corresponding pillar113.

Conductive materials331to333extending in the third direction may be provided onto drains320. Conductive materials331to333may be sequentially disposed in the first direction. Conductive materials331to333may be connected to drains320of corresponding regions, respectively. Exemplarily, drains320and the conductive material extending in the third direction may be connected through contact plugs. Exemplarily, conductive materials331to333extending in the third direction may be metal materials. Exemplarily, conductive materials331to333may be conductive materials such as polysilicon.

InFIGS. 15 and 16, each pillar113may form a string together with adjacent ones among conductive lines211to291,212to292and213to293extending in the first direction. For example, each pillar113may form a NAND string NS together with adjacent ones among conductive lines211to291,212to292and213to293extending in the first direction. The NAND string NS may include a plurality of transistor structures TS. The transistor structure TS will be described below in more detail with reference toFIG. 17.

FIG. 17is a cross section view of a transistor structure TS inFIG. 16.

Referring toFIGS. 15 to 17, an insulation layer116may include first to third sub-insulation layers117to119. For example, first sub-insulation layer117adjacent to a pillar113may include a thermal oxide layer. For example, second sub-insulation layer118may include a nitride layer or metal oxide layer (e.g., an aluminum oxide layer or a hafnium oxide layer). Exemplarily, third sub-insulation layer119adjacent to conductive material233extending in the first direction may be formed as a single layer or a multi-layer. Third sub-insulation layer119may be a high dielectric layer (e.g., an aluminum oxide layer or a hafnium oxide layer) having a higher dielectric constant than first and second sub-insulation layers117and118. Exemplarily, first to third sub-insulation layers117to119may form an oxide-nitride-oxide (ONO) structure.

Conductive material233may serve as a gate (or a control gate). Third sub-insulating layer119adjacent to conductive material233may serve as a blocking insulation layer. Second sub-insulation layer118may serve as a charge storage layer. For example, second sub-insulation layer118may serve as a charge trap layer. First sub-insulation layer117adjacent to pillar113may serve as a tunneling insulation layer, and p-type silicon of pillar113may serve as a body. That is, gate (or, control gate)233, blocking insulation layer119, charge storage layer118, tunneling insulation layer117, and body114may form a transistor (or, a memory cell transistor structure). Hereinafter, the p-type silicon of pillar113may be referred to as a second-direction body.

A memory block BLKi may include a plurality of pillars113. That is, the memory block BLKi may include a plurality of NAND strings NS. In more detail, the memory block BLKi may include a plurality of NAND strings NS extending in the second direction (or a direction vertical or perpendicular to the substrate).

Each NAND string NS may include a plurality of transistor structures TS that are arranged in the second direction. At least one of the transistor structures TS of each NAND string NS may serve as a string selection transistor SST. At least one of the transistor structures TS of each NAND string NS may serve as a ground selection transistor GST.

Gates (or control gates) correspond to conductive materials211to291,212to292and213to293that extend in the first direction. That is, the gates (or the control gates) may extend in the first direction and form word lines and at least two selection lines (e.g., at least one string selection line SSL and at least one ground selection line GSL). Conductive materials331to333extending in the third direction each may be connected to one end of a group of the NAND strings NS. Exemplarily, conductive materials331to333extending in the third direction may serve as bit lines BL. That is, in one memory block BLKi, a plurality of NAND strings may be connected to one bit line BL (e.g., BL1, BL2, BL3, etc.).

Second-type doping regions311to314extending in the first direction may be provided at the other ends of the NAND strings NS. The second-type doping regions311to314extending in the first direction may serve as the common source line CSL.

In summary, the memory block BLKi may include a plurality of NAND strings that are extending in a direction (i.e., the second direction) vertical or perpendicular to substrate111, and serves as a NAND flash memory block (e.g., a charge trapping type) where the plurality of NAND strings NS may be connected to one bit line BL.

FIGS. 15 to 17were described under the assumption conductive lines211to291,212to292and213to293are formed in nine layers. However, the layer number of conductive lines211to291,212to292and213to293extending in the first direction is not limited thereto. For example, the conductive lines may be formed in eight layers, sixteen layers, or more layers. That is, one NAND string may include 8, 16, or more transistors.

FIGS. 15 to 17were described under the assumption that three NAND strings NS are connected to one bit line BL. But, the inventive concept is not limited thereto. Exemplarily, the memory block BLKi may be formed such that m NAND strings NS are connected to one bit line BL. In this case, the number of conductive materials211to291,212to292and213to293extending in the first direction and the number of common source lines311to314may be adjusted in proportion to the number of NAND strings NS connected to one bit line BL.

FIGS. 15 to 17were described under the assumption that three NAND strings NS are connected to one conductive material extending in the first direction. But, it is well understood that the inventive concept is not limited thereto. For example, n NAND strings NS may be connected to one conductive material. In this case, the number of bit lines may be controlled in proportion to the number of NAND strings NS that are connected to one conductive material extending in the first direction.

FIG. 18is an equivalent circuit diagram of a memory block described inFIGS. 15 to 17.

Referring toFIGS. 15 to 18, NAND strings NS11to NS31may be provided between the first bit line BL1and a common source line CSL. The first bit line BL1may correspond to conductive material331extending in the third direction. NAND strings NS11, NS22and NS32may be provided between the second bit line BL2and the common source line CSL. The second bit line BL2may correspond to conductive material332extending in the third direction. NAND strings NS13, NS23and NS33may be provided between the third bit line BL3and the common source line CSL. The third bit line BL3may correspond to conductive material333extending in the third direction.

A string selection transistor SST of each NAND string NS may be connected to a corresponding bit line BL. A ground selection transistor GST of each NAND string NS may be connected to the common source line CSL. In each NAND string NS, memory cells MC may be provided between the string selection transistor SST and the ground selection transistor GST.

Hereinafter, NAND strings NS may be defined by the row and by the column. The NAND strings NS connected to one bit line in common may form one column. For example, the NAND strings NS11to NS31connected to the first bit line BL1may correspond to the first column. The NAND strings NS12to NS32connected to the second bit line BL2may correspond to the second column. The NAND strings NS13to NS33connected to the third bit line BL3may correspond to the third column.

The NAND strings connected to one string selection line SSL may form one row. For example, the NAND strings NS11to NS13connected to the first string selection line SSL1may form the first row. The NAND strings NS21to NS23connected to the second string selection line SSL2may form the second row. The NAND strings NS31to NS33connected to the third string selection line SSL3may form the third row.

In each NAND string NS, a height may be defined. Exemplarily, in each NAND string NS, a memory cell MC1adjacent to the ground selection transistor GST may be defined to have a height of 1. In each NAND string NS, a height of a memory cell may increase as it becomes close to the string selection transistor SST. In each NAND string NS, a memory cell MC7adjacent to the string selection transistor SST may be defined to have a height of 7.

The string selection transistors SST of the NAND strings NS in the same row may share the sting selection line SSL. The string selection transistors SST of the NAND strings NS in different rows may be connected with different sting selection lines SSL1, SSL2, and SSL3.

In each NAND string in the same row, memory cells having the same height may share a word line WL. Word lines WL connected with memory cells MC of NAND strings NS placed in different rows and having the same height may be connected in common. In each NAND string in the same row, dummy memory cells DMC having the same height may share a dummy word line DWL. Dummy word lines DWL connected with dummy memory cells DMC of NAND strings NS placed in different rows and having the same height may be connected in common.

In an exemplary embodiment, word lines WL or dummy word lines DWL may be connected in common at a layer where conductive materials211to291,212to292, and213to293extending in the first direction are provided. For example, conductive materials211to291,212to292, and213to293extending in the first direction may be connected at an upper layer via contacts. Conductive materials211to291,212to292, and213to293extending in the first direction may be connected in common at the upper layer.

Ground selection transistors GST of NAND strings NS in the same row may share a ground selection line GSL. Ground selection transistors GST of NAND strings NS in different rows may share a ground selection line GSL. That is, NAND strings NS11to NS13, NS21to NS23, and NS31to NS33may be connected in common with the ground selection line GSL.

The common source line CSL may be connected to NAND strings NS in common. For example, first to fourth doping regions311to314may be connected at an active region on substrate111. In other words, first to fourth doping regions311to314may be connected to an upper layer via contacts so as to be connected in common at the upper layer.

As illustrated inFIG. 18, the word lines WL having the same depth may be connected in common. Accordingly, when a specific word line WL is selected, all NAND strings NS connected to the specific word line WL may be selected. The NAND strings NS of different rows may be connected to different string selection lines SSL. Therefore, by selecting the string selection lines SSL1to SSL3, NAND strings NS in an unselected row among NAND strings NS connected to the same word line WL may be separated from bit lines BL1, BL2, and BL3. That is, a row of NAND strings NS may be selected by selecting the string selection lines SSL1to SSL3. NAND strings in the selected row may be selected by the column by selecting the bit lines BL1to BL3.

Each NAND string NS may include a dummy memory cell DMC. First to third memory cells MC1to MC3may be provided between the dummy memory cell DMC and the ground selection line GSL. Fourth to sixth memory cells MC4to MC6may be provided between the dummy memory cell DMC and a string selection line SSL. Memory cells MC in each NAND string may be divided into memory cell groups on the basis of the dummy memory cell DMC. A memory cell group including memory cells (e.g., MC1to MC3) close to the ground selection transistor GST may be called a lower memory cell group, and a memory cell group including memory cells (e.g., MC4to MC6) close to the string selection transistor SST may be called an upper memory cell group.

FIG. 19is a block diagram of a user device1000including a non-volatile memory device according to exemplary embodiments of the inventive concept.

Referring toFIG. 19, user device1000may include a data storage device1100and a host1500. Data storage device1100may be a solid state drive (hereinafter, referred to as SSD). SSD1100may include an SSD controller1200, a buffer memory device1300, and a storage media1400. SSD1100may further include an auxiliary power supply having super capacitors. The auxiliary power supply may supply a power to SSD1100so as to be ended normally upon sudden power-off.

SSD1100may operate in response to an access request of host1500. That is, SSD controller1200may be configured to access storage media1400in response to a request from host1500. For example, SSD controller1200may be configured to control read, write, and erase operations of storage media1400. Buffer memory device1300may temporarily store data to be stored in storage media1400. Further, buffer memory device1300may temporarily store data read out from storage media1400. Data stored in buffer memory device1300may be sent to storage media1400or host1500according to the control of SSD controller1200.

SSD controller1200may be connected with storage media1400via a plurality of channels CH0to CHn. Each channel may be connected with a plurality of non-volatile memory devices. For example, a channel CH0is connected with a plurality of non-volatile memory devices NVM00to NVM0i. A plurality of non-volatile memory devices may share a corresponding channel. Storage media1400may be formed of a NAND flash memory device according to an exemplary embodiment of the inventive concept. But, it is well understood that storage media1400is not limited to a NAND flash memory device. For example, storage media1400may be formed of one of non-volatile memory devices such as a NOR flash memory device, a phase-change RAM (PRAM), a ferroelectric RAM (FRAM), a magnetic RAM (MRAM), and the like.

During a read operation, storage media1400of data storage device1100may perform a coupling compensation read operation. That is, the coupling effect included in a read result of a selected memory cell may be removed on the basis of a program state of a memory cell adjacent to the selected memory cell. For this, a read operation on the adjacent memory cell may be carried out prior to reading data from the selected memory cell. Upon sensing of data from the selected memory cell, one or more read operations may be performed, with one or more read voltages each having a selected voltage level which is selected according to the program state of the adjacent memory cell. As a result, it is possible to improve the reliability of data storage device1100by utilizing storage media1400.

FIG. 20is a block diagram of another user device including a non-volatile memory device according to exemplary embodiments of the inventive concept.

Referring toFIG. 20, a memory system2000may include a memory controller2200and one or more non-volatile memory devices2900.

Memory controller2200may be connected to a host2100and non-volatile memory devices2900. Memory controller2200may be configured to access non-volatile memory devices2900in response to a request from host2100. For example, memory controller2200may be configured to control read, write, and erase operations of non-volatile memory devices2900. Memory controller2200may be configured to provide an interface between non-volatile memory devices2900and host2100. Memory controller2200may be configured to drive firmware for controlling non-volatile memory devices2900.

Memory controller2200may include constituent elements such as a random access memory (RAM)2600, a central processing unit (CPU)2400, a host interface2300, an error check and correction (ECC) block2700, a memory interface (UF)2500, and the like. RAM2600may be used as a working memory of CPU2400. CPU2400may control an overall operation of memory controller2200.

Host interface2300may employ one or more protocols for exchanging data between host2100and memory controller2200. For example, memory controller2200may be configured to communicate with an external device (e.g., a host) via the various interface protocols such as an USB (Universal Serial Bus) protocol, an MMC (Multimedia Card) protocol, a PCI (Peripheral Component Interconnection) protocol, a PCI-E (PCI-Express) protocol, an ATA (Advanced Technology Attachment) protocol, an SATA (Serial ATA) protocol, an SCSI (Small Computer Small Interface) protocol, an ESDI (Enhanced Small Disk Interface) protocol, an IDE (Integrated Drive Electronics) protocol, and the like.

ECC block2700may be configured to detect and correct errors of data read out from non-volatile memory devices2900. ECC block2700may be provided as an element of memory controller2200. In another embodiment, ECC block2700may be provided as an element of each of non-volatile memory devices2900. Memory interface2500may provide an interface between non-volatile memory devices2900and memory controller2200.

It is well understood that constituent elements of memory controller2200are not limited to this disclosure. For example, memory controller2200may further include a read only memory (ROM) which stores code data needed for initial booting and data for interfacing with host2100.

Memory controller2200and non-volatile memory device2900may be integrated in one semiconductor device. Memory controller2200and non-volatile memory device2900may be configured to form a memory card. Memory controller2200and non-volatile memory device2900may be configured to form a PCMCIA (personal computer memory card international association) card, a CF (compact flash) card, a SM (smart media) card, memory stick, an MMC (multimedia card) (RS-MMC, MMCmicro, etc.), SD (secure digital) (miniSD, microSD, etc.) card, a UFS (universal flash storage) card, and the like.

In some embodiments, memory controller2200and non-volatile memory devices2900may be applied to a solid state drive (SSD), a computer, portable computer, an Ultra Mobile PC (UMPC), a workstation, a net-book, a PDA, a web tablet, a wireless phone, a mobile phone, a smart phone, an e-book, a PMP (portable multimedia player), a digital camera, a digital audio recorder/player, a digital picture/video recorder/player, a portable game machine, a navigation system, a black box, a 3-dimensional television, a device capable of transmitting and receiving information at a wireless circumstance, one of various electronic devices constituting home network, one of various electronic devices constituting a computer network, one of various electronic devices constituting a telematics network, a radio frequency identification (RFID) device, or one of various electronic devices constituting a computing system.

In another embodiment, non-volatile memory devices2900or memory controller2200may be packaged using various types of packages. For example, non-volatile memory devices2900or memory system2000may be packed using packages such as PoP (Package on Package), Ball grid arrays (BGAs), Chip scale packages (CSPs), Plastic Leaded Chip Carrier (PLCC), Plastic Dual In-Line Package (PDIP), Die in Waffle Pack, Die in Wafer Form, Chip On Board (COB), Ceramic Dual In-Line Package (CERDIP), Plastic Metric Quad Flat Pack (MQFP), Thin Quad Flatpack (TQFP), Small Outline (SOIC), Shrink Small Outline Package (SSOP), Thin Small Outline (TSOP), Thin Quad Flatpack (TQFP), System In Package (SIP), Multi Chip Package (MCP), Wafer-level Fabricated Package (WFP), Wafer-Level Processed Stack Package (WSP), and the like.

During a read operation, non-volatile memory device2900of memory system2000may perform a coupling compensation read operation. That is, the coupling effect included in a read result of a selected memory cell may be compensated on the basis of a program state of a memory cell adjacent to the selected memory cell. For this, a read operation on the adjacent memory cell may be carried out prior to read data from the selected memory cell. Upon sensing of data from the selected memory cell, one or more read operations may be performed according to the program state of the adjacent memory cell, with a read voltage being changed in level when the program state is one that causes coupling to the selected memory cell, from the level that would be employed in the normal or general read operation where the adjacent memory cells do not cause coupling to the selected memory cell. As a result, it is possible to improve the reliability of memory system2000by utilizing non-volatile memory devices2900.

FIG. 21is a block diagram of a computer system3000including a data storage device such as the data storage device illustrated inFIG. 19.

Computer system3000may include a network adaptor3100, a CPU3200, a data storage device3300, a RAM3400, a ROM3500, and a user interface3600which are electrically connected to a system bus3700.

Network adaptor3100may provide an interface between computer system3000and external networks. CPU3200may control an overall operation for driving an operating system and an application program which are resident in RAM3400. Data storage device3300may store data needed for computer system3000. For example, data storage device3300may store an operating system for driving computer system3000, an application program, various program modules, program data, user data, and the like.

RAM3400may be used as a working memory of computer system3000. Upon booting, the operating system, the application program, the various program modules, and program data needed to drive programs and various program modules read out from data storage device3300may be loaded on RAM3400. ROM3500may store a basic input/output system (BIOS) which is activated before the operating system is driven upon booting. Information exchange between computer system3000and a user may be made via user interface3600, which may include, for example, a display device, a keyboard, a touch screen, and/or a navigation device such as a mouse.

In addition, computer system3000may further include a battery, a modem, and the like. Although not shown inFIG. 21, computer system3000may further include an application chipset, a camera image processor (CIS), a mobile DRAM, and the like.