High resolution capacitor

A first trimming capacitor having a first terminal and a second terminal is coupled in parallel between a first terminal and a second terminal of a first capacitor. The first trimming capacitor comprises a first plurality of switched capacitors having different capacitances coupled in parallel. Each of the switched capacitors comprises a switch capacitor and a switch coupled in series. In an illustrative application the first capacitor and the first trimming capacitor are coupled between an output terminal of an operational amplifier (op-amp) and an inverting input terminal of the op-amp. A second capacitor and a second trimming capacitor similar to the first capacitor and the first trimming capacitor are coupled between an input and the inverting input terminal of the op-amp.

BACKGROUND

High accuracy analog circuits often require very accurate capacitors. Examples of such requirements are found in switched capacitor circuits used in filters and analog-to-digital converters (ADC). For example, to achieve resolutions such as 14-bit resolution in an ADC, a circuit would require matching of (½^14)*100%=0.006% between two capacitors. The inventors are not aware of such designs in the prior art.

SUMMARY

The present invention is a high resolution capacitor. In an illustrative embodiment, two such capacitors can be matched to within 0.006%.

In an illustrative embodiment, a first trimming capacitor having a first terminal and a second terminal is coupled in parallel between a first terminal and a second terminal of a first capacitor. The first trimming capacitor comprises a first plurality of switched capacitors having different capacitances coupled in parallel between the first and second terminals of the first trimming capacitor. Each of the switched capacitors comprises a switch capacitor and a switch coupled in series with the switch capacitor coupled to the first terminal and the switch coupled to the second terminal.

In an illustrative application, the first capacitor and the first trimming capacitor are coupled between an output terminal of an operational amplifier (op-amp) and an inverting input terminal of the op-amp with the first terminal of the capacitors being coupled to the output terminal of the op-amp and the second terminal being coupled to the inverting input terminal. A second capacitor and a second trimming capacitor similar to the first capacitor and the first trimming capacitor are coupled between an input and the inverting input terminal with the second terminal of the second capacitors being coupled to the inverting input terminal.

Numerous variations may be practiced in the preferred embodiment.

DETAILED DESCRIPTION

FIG. 1is a schematic diagram of a conventional op-amp circuit100in which the invention may be practiced. Circuit100comprises an op-amp110having an inverting input terminal112, a non-inverting input terminal114and an output terminal116. A first capacitor120is coupled between an input105and inverting input terminal112with a first terminal122coupled to input105and a second terminal124coupled to the inverting input terminal112. A second capacitor130is coupled between output terminal116and inverting input terminal112with a first terminal132coupled to output terminal116and a second terminal134coupled to inverting input terminal112. Parasitic capacitance between the inverting input terminal112and ground is represented by capacitor140. The non-inverting input terminal114is AC grounded. As will be recognized by those skilled in the art, inverting input terminal112is at virtual ground.

The ideal gain of the circuit ofFIG. 1is:
Vout/Vin=C1/C2  (1)
where C1 is the capacitance of capacitor120and C2 is the capacitance of capacitor130. Equation (1) neglects the open loop gain Av1 of the op-amp and the parasitic capacitance Cin of capacitor140. Accounting for these matters, the gain of the circuit ofFIG. 1is:
Vout/Vin=C1/(C2+(C2+C1+Cin)/Av1)  (2)
where the values are as defined above.

FIG. 2is a schematic diagram of an illustrative embodiment of the invention in an op-amp circuit200. Circuit200comprises an op-amp210having an inverting input terminal212, a non-inverting input terminal214and an output terminal216. A first capacitor220is coupled between an input205and inverting input terminal212with a first terminal222coupled to the input and a second terminal224coupled to the inverting input terminal212. A second capacitor230is coupled between output terminal216and inverting input terminal212with a first terminal232coupled to output terminal216and a second terminal234coupled to inverting input terminal212. Parasitic capacitance between the inverting input terminal212and ground is represented by capacitor240. The non-inverting input terminal214is AC grounded. These elements are the same as the corresponding elements ofFIG. 1and bear the same numbers increased by100.

In addition, a first trimming capacitor260is coupled in parallel to capacitor220and a second trimming capacitor270is coupled in parallel to second capacitor230. The first trimming capacitor has first and second terminals262,264with the first terminal262being coupled to input205and the second terminal264being coupled to the inverting input terminal212. The second trimming capacitor270has first and second terminals272,274with the first terminal272being coupled to the output terminal216and the second terminal274being coupled to the inverting input terminal212.

Each trimming capacitor260,270comprises a plurality of switched capacitors having different capacitances that are coupled in parallel between the first and second terminals of the trimming capacitor. One such trimming capacitor is illustrated inFIG. 3as capacitor300. Trimming capacitor300comprises a plurality of switched capacitors310-1,310-2,310-nhaving different capacitances that are coupled in parallel between the first and second terminals302,304of the trimming capacitor. Further each switched capacitor comprises a switch capacitor320-1,320-2,320-nand a switch322-1,322-2,322-nconnected in series with the capacitor coupled to the first terminal302and the switch coupled to the second terminal304.

Illustratively, there are six switch capacitors320-1to320-6and six switches322-1to322-6in each trimming capacitor260,270; and the capacitance of switch capacitors320-1to320-6are 0.03, 0.06, 0.12, 0.24, 0.48 and 0.96 femtoFarads (ff), respectively. By selective operation of switches322-1to322-6, the capacitance of one of the trimming capacitors can be varied in 0.03 ff increments from 0.00 ff if no switches are conducting up to 1.89 ff if all switches are conducting.

Advantageously, each trimming capacitor260,270is independently controlled so as to achieve any trimming capacitance value in the range from 0.00 ff to 1.89 ff. Thus, the difference between the capacitances generated by the two trimming capacitors can range from +1.89 ff to −1.89 ff. Since the trim structures are identical, any parasitic generated by these structures should cancel out.

Trimming capacitors with other numbers of switched capacitors can also be used in the practice of the invention. To provide a linear distribution of trimming capacitance values over the entire range of trimming capacitance values, each of the switched capacitors should have a different capacitance and the capacitances of the different circuits should differ by a factor of two. Thus, if the first switched capacitor has a capacitance of C, the second switched capacitor should have a capacitance that is approximately C×2, a third switched capacitor should have a capacitance that is approximately C×22, and so on, with a Nth switched capacitor having a capacitance that is approximately C×2(N-1).

FIG. 4depicts a structure400suitable for implementing a switch capacitor. Structure400comprises a flat insulating substrate410on which are formed first, second and third non-overlapping conducting layers420,430and440. Advantageously, structure400may be formed by depositing a continuous, substantially planar, conducting layer such as a layer of a metal such as aluminum or copper on substrate410and then using conventional photolithographic processes to define the patterns of the conducting layers depicted inFIG. 4.

As will be apparent, layers420,430and440are inter-digitated with finger regions422extending from a base region424of layer420between finger regions432and442that extend from base regions434and444of layers430and440. Illustratively, layer420forms one plate of the capacitor and layers430and440form a second plate of the capacitor. If desired, the spacing between adjacent finger regions of different plates of the capacitor can be at the minimum dimension allowed for the technology used to form the metal layers on substrate410. Similarly, the width of the finger regions can be limited to approximately the minimum width achievable with the technology used to form the layers. At the time of filing this application, such minimum widths were on the order of 20 to 30 nanometers (nm).

As shown by the dashed horizontal and vertical lines inFIG. 4, capacitor structure400is made of six substantially identical cells. When the spacing between the finger regions is approximately 20 nm, the capacitance of a single cell can be approximately 0.03 femtoFarads. All six cells may be coupled together to form a single capacitor having a capacitance of approximately six times the capacitance of a single cell by electrically connecting layers430and440. Capacitors with smaller capacitances can be formed by coupling together fewer than six cells. Capacitors with larger capacitances can be formed using more cells.

As a result, available technology makes it possible to form a capacitor having a configuration such as that depicted inFIG. 4with a capacitance less than 0.03 ff.

A further concern is that parasitics added by the trimming switches322-1to322-nmight swamp the fine resolution of the switched capacitor. However, the switches and their parasitics are placed at the virtual ground of the operational amplifier. As a result, the parasitic are hidden for capacitors220and230Another concern is that parasitic loading can make the closed loop gain non-ideal. However, as shown in Equation (2) above, the parasitic capacitance Cin is reduced by the open loop gain Av1.

FIG. 5is a flowchart depicting a method for trimming capacitors such as might be used with an operational amplifier (op-amp). In step510, a plurality M of switched capacitors is coupled between a first terminal and a second terminal of a first capacitor that is coupled between an input of the op-amp and an inverting input terminal of the op-amp. A first switched capacitor has a first capacitance C, a second switched capacitor has a second capacitance that is approximately C×2, a third switched capacitor has a third capacitance that is approximately C×22, and so on, with a Mth switched capacitor having a capacitance that is approximately C×2(M-1). As a result, the trimming capacitance coupled between the first and second terminals of the first capacitor can range between zero and the sum of the first through Mth capacitances in increments of the first capacitance.

In step520, a plurality N of switched capacitors is coupled between a first terminal and a second terminal of a first capacitor that is coupled between an output of the op-amp and an inverting input terminal of the op-amp. A first switched capacitor has a first capacitance C, a second switched capacitor has a second capacitance that is approximately C×2, a third switched capacitor has a third capacitance that is approximately C×22, and so on, with a Nth switched capacitor having a capacitance that is approximately C×2(N-1). As a result, the trimming capacitance coupled between the first and second terminals of the second capacitor can range between zero and the sum of the first through Nth capacitances in increments of the first capacitance.

In step530, the first capacitor is trimmed by selectively switching the switched capacitors of the plurality M of switched capacitors to provide a trimming capacitance between the first and second terminals of the first capacitor that can range between zero and the sum of the capacitances of the plurality M of switched capacitors in increments of the first capacitance; and in step540the second capacitor is trimmed by selectively switching the switched capacitors of the plurality of N switched capacitors to provide a trimming capacitance between the first and second terminals of the second capacitor that can range between zero and the sum of the capacitances of the plurality N of switched capacitances in increments of the first capacitance.

As will be apparent to those skilled in the art, numerous variations may be practiced within the spirit and scope of the present invention.