Method for forming an integrated semiconductor circuit arrangement

Methods for forming an integrated semiconductor circuit arrangement are disclosed. In one embodiment, a semiconductor circuit with a first semiconductor circuit region and with a second semiconductor circuit region is formed in each case in a semiconductor material region. A first metallization layer is applied to the structure thus obtained. A protective material region is then formed. A second metallization layer is subsequently applied, which is then also patterned. Afterward, the first metallization layer together with the protective material region is then patterned.

CROSS-REFERENCE TO RELATED APPLICATIONS

This Utility patent application claims priority to German Patent Application No. DE 10 2004 026 232.2, filed on May 28, 2004, which is incorporated herein by reference.

FIELD OF THE INVENTION

The invention relates to a method for forming an integrated semiconductor circuit arrangement.

BACKGROUND

In many integrated semiconductor circuit arrangements, different semiconductor circuit regions are formed in the region of a semiconductor material. These different semiconductor circuit regions provide different functions during operation of the integrated semiconductor circuit arrangement. Therefore, these semiconductor circuit regions are generally also constructed and patterned differently. These different structures also have to be taken into consideration in the context of the respective fabrication process.

It is thus provided, by way of example, that the different semiconductor circuit regions of the integrated semiconductor circuit arrangement are formed with different contacts with regard to their contact-connection among one another or else externally. These contacts may differ for example with regard to the layer thickness of the materials used for the contacts, in particular of the metallizations used.

Since, by way of example, control circuit arrangements or logic circuits have a relatively low power consumption, for the formation of contacts in circuit arrangements of this type a comparatively small layer thickness suffices for the metallization layer provided and is expedient with regard to miniaturization and high packing density in this circuit region.

In addition to the contacts, the wiring interconnects represent essential elements of a logic metallization. In particular, the width and the spacing of the interconnects are among the crucial factors for the packing density that can be achieved.

On the other hand, specific other circuit regions may exhibit a comparatively quite high electrical power consumption which is correspondingly also imparted by contacts that are to be dimensioned more generously and metallization layers made correspondingly thicker. When forming the metallizations necessary for ensuring the respective layer thicknesses and functionalities, the functionality of the respectively underlying structures must remain unimpaired. However, this cannot always be ensured to a sufficient extent in the case of conventional patterning methods and in particular in the case of the respective process steps for forming different metal layer thicknesses.

SUMMARY

Embodiments of the invention provide methods for forming an integrated semiconductor circuit arrangement. In one embodiment, a semiconductor circuit with a first semiconductor circuit region and with a second semiconductor circuit region is formed in each case in a semiconductor material region. A first metallization layer is applied to the structure thus obtained. A protective material region is then formed. A second metallization layer is subsequently applied, which is then also patterned. Afterward, the first metallization layer together with the protective material region is then patterned.

DETAILED DESCRIPTION

The object on which the invention is based is to demonstrate a possibility that enables sensors of this type to be integrated into a trench transistor as effectively as possible.

In order to achieve the object the invention provides a trench transistor in accordance with patent claim1. Advantageous refinements and developments of the concept of the invention are found in the subclaims.

The trench transistor according to the invention has a cell array, in which a plurality of cell array trenches and a plurality of mesa zones arranged between the cell array trenches are provided. Furthermore, the trench transistor has a semiconductor functional element serving as a sensor, which is formed in one of the mesa zones. The trench transistor is configured such that it is possible to generate, in the operating state of said trench transistor, vertically oriented current flows that permeate (at least some of the) mesa zones, and horizontally oriented current flows that permeate the semiconductor functional element. A current flow guiding structure is provided in the mesa zone in which the semiconductor functional element is formed, said structure being formed at least partly below the semiconductor functional element and being configured such that vertically oriented current flows out of the semiconductor functional element or into the semiconductor functional element are made more difficult and horizontally oriented current flows through the semiconductor functional element are promoted.

The current flow guiding structure makes it possible to suppress parasitic current flows between the semiconductor functional element and a drain terminal zone of the trench transistor. In this way, the horizontally oriented current flows that permeate the semiconductor functional element and that represent a measure of the parameter to be measured, for example the temperature, can be determined in an uncorrupted manner whereby the accuracy of the parameter measurement can be improved.

The semiconductor functional element is preferably a transistor, but may also be any other semiconductor functional element, for example a diode or a resistor.

In one preferred embodiment, the semiconductor functional element is a MOS-transistor having a source zone of a first doping type, a body zone of a second doping type and a drain zone of the first doping type. The source zone and the drain zone are spaced apart horizontally from one another and connected to one another by the body zone. In this embodiment, at least one of the electrodes that are provided within the cell array trenches adjacent to the semiconductor functional element serves as a gate electrode in order to induce a channel in the body zone of the MOS transistor.

In a further preferred embodiment, the semiconductor functional element is realized as a bipolar transistor having an emitter zone of a first doping type, a base zone of a second doping type and a collector zone of the first doping type. The emitter zone is horizontally spaced apart from the collector zone; furthermore, the emitter zone and the collector zone are connected to one another by the base zone.

The current flow guiding structure may be a highly doped semiconductor layer, by way of example. If the semiconductor functional element is formed as a transistor, the second doping type would have to be chosen as the doping type of the semiconductor layer. Furthermore, the semiconductor layer should directly adjoin the body zone/base zone. However, it is also possible to bury the semiconductor layer in a manner spaced apart from the body zone/base zone within the mesa zone.

The current flow guiding structure should preferably cover the entire cross-sectional area of the mesa zone below the semiconductor functional element in order to enable parasitic current flows to be suppressed as well as possible. However, the invention is not restricted thereto; by way of example, semiconductor layers with cutouts are also conceivable.

The semiconductor functional element may be arranged at an arbitrary location within the cell array. By way of example, it is possible to arrange the semiconductor functional element between two active cell array trenches. As an alternative thereto, it is possible to arrange the semiconductor functional element between deactivated cell array trenches at the edge of the cell array. The positioning of the semiconductor functional element within the trench transistor depends greatly on what parameter is intended to be measured. Thus, the semiconductor functional element would advantageously have to be positioned centrally in the cell array if the temperature of the cell array is intended to be measured as accurately as possible.

The semiconductor functional element may be completely enclosed with trenches. By way of example, the semiconductor functional element may be laterally delimited by the cell array trenches, the cell array trenches in front of and behind the semiconductor functional element being connected to one another by additional transverse trenches, thus giving rise to a closed trench ring around the semiconductor functional element.

The invention can particularly advantageously be applied to dense trench transistors, that is to say to trench transistors whose trenches are very close to one another (i.e., whose mesa zone widths are small). In one preferred embodiment, the semiconductor functional element serves as a temperature sensor for measuring the temperature of the cell array. Further application possibilities would be current intensity sensors, voltage sensors and the like.

Structurally and/or functionally similar or equivalent elements and structures are designated by the same reference symbols hereinafter. A corresponding detailed description is not repeated each time these reference symbols occur.

FIG. 1is a schematic flowchart demonstrating the sequence of individual method steps of an embodiment of the methods according to the invention for forming an integrated semiconductor circuit arrangement.

A first step S1, A involves firstly forming or providing a semiconductor material region20or a fundamental semiconductor structure with a first semiconductor circuit region31and a second semiconductor circuit region32. Afterward, a first metallization layer50is then formed on the given structure in a second step S2, B. A third step S3, C, which is critical for the invention, then involves forming a protective material region60with one or with a plurality of electrically conductive materials. A process section D then follows, in which a second material layer is formed in a first substep S4aand is then patterned in a second substep S4b, a second metal material being used. During the patterning of the second metallization layer70, care must be taken to ensure that the protective material region60is not patterned concomitantly. The patterning of the protective material region60is effected simultaneously with the patterning of the first metallization layer50in a subsequent fifth step S5, E.

The sequence ofFIGS. 1ato1helucidates in greater detail a first preferred embodiment of the method according to the invention for forming an integrated semiconductor circuit arrangement. In this method, it is critical that firstly a planarizing first layer62and then the actual protective layer61are applied during the formation of the protective material region60.

FIG. 1aillustrates a sectional side view of a structure such as is obtained as an intermediate stage during the method according to the invention for forming an integrated semiconductor circuit arrangement in accordance with this embodiment. A first semiconductor circuit region31, here for example a logic circuit, and a second semiconductor circuit region32, here for example a power circuit, are formed and provided in a semiconductor material region20. First and second contact locations33and34of the first semiconductor circuit region31and of the second semiconductor region32, respectively, are formed in the region of the surface20aor in the surface region20aof the semiconductor material region20, and are formed and provided for external contact-connection or for connection to one another via interconnects. This structure is adjoined by an intermediate oxide layer40, ZWOX that covers and/or partly embeds it, the first and second contact locations33and34, respectively, remaining free of the intermediate oxide40, ZWOX. A first metallization layer50made of a first metal material53is then formed onto this structure, in particular in an essentially conformal manner. In this case, the contact structures42or cutouts42above the first and second contact locations33,34, respectively, are filled. These contact structures, cutouts or depressions42are indicated as lateral double arrows inFIG. 1aabove the first and second contact locations33and34, respectively.

In the transition to the intermediate stage illustrated inFIG. 1b, firstly a planarization layer62with a planar surface region62ais then formed in order to produce the protective material region60that is to be provided in accordance with the invention, as a result of which the surface topography of the structure fromFIG. 1aand in particular the depressions and/or cutouts formed there above the first and second contact locations33and34, respectively, are filled with the material of the planarization layer62.

In the transition to the intermediate state shown inFIG. 1c, the planarization layer62is then thinned, giving rise to a planarization layer62′ of reduced layer thickness with a pulled-back surface62a′, but the contact structures, cutouts or depressions42, in particular above the first and second contact locations33and34, remain filled in the process. In this way, the structure shown inFIG. 1cexhibits a surface topography that is planarized with respect to the preceding structures.

In the transition to the intermediate state shown inFIG. 1d, a protective material layer61with an at least partly planar surface region61ais then deposited conformally on the structure fromFIG. 1c.

In the transition to the intermediate state shown inFIG. 1e, a second metallization layer70with a second metallization material73is then formed on the surface61aof the structure fromFIG. 1d.

The second metallization layer70with the second metal material73has a surface region70a,73athat is formed likewise partly or locally in planar fashion.

In the transition to the intermediate state ofFIG. 1f, the structure fromFIG. 1eis patterned in such a way that the second semiconductor circuit region32illustrated on the left-hand side inFIG. 1f, namely the power circuit here, remains covered, while the first semiconductor circuit region31illustrated on the right-hand side of the illustration inFIG. 1f, namely the logic circuit here, is essentially freed of the second metallization layer70or the second metal material73.

What is not illustrated here is that so-called logic bonding pads that may serve for the external contact-connection may remain covered by the second metal material73. All that is important is that, in the region of the first semiconductor circuit region31, that is to say the logic circuit, the corresponding contact structures42above the contact locations33of the first semiconductor circuit region31are not reinforced by the second metallization layer70and the second metal material73.

In the transition to the intermediate state shown inFIG. 1g, the first metallization layer50comprising the first metal material53is then patterned, thus giving rise to first contacts51and also wiring interconnects55formed from said first metal material53in the region of the first semiconductor circuit region31, that is to say the logic circuit, as is illustrated inFIG. 1g. At the same time as the patterning of the first metallization layer50in the region of the first semiconductor circuit region31, the protective material layer61is also concomitantly patterned in such a way that the regions of the first contacts51remain covered by it.

During the patterning of the first metallization layer50in the region of the first semiconductor circuit region31, the first metal material53in the region of the second semiconductor circuit region32remains untouched, that is to say that it is not concomitantly patterned.

In the transition to the intermediate state illustrated inFIG. 1h, the structure fromFIG. 1gis then embedded in a passivation layer and/or in an imide layer90in the region of the first semiconductor circuit region31and partly also in the region of the second semiconductor circuit region32. It is also conceivable for the second semiconductor circuit region32to be completely embedded.

What is critical in the case of the embodiment illustrated byFIGS. 1ato1his that the protective material region60is formed by firstly applying a planarization layer62and then covering it by a protective material layer61.

By contrast, the embodiment of the method according to the invention in accordance with the sequence ofFIGS. 2ato2hshows the opposite procedure, with the result that, in the embodiment described byFIGS. 2ato2h, the protective material region60is formed by firstly applying the protective material layer61on the fundamental structure and then applying the planarization layer60.

Proceeding from the structure which is shown inFIG. 2aand corresponds to the structure shown inFIG. 1aof the exemplary embodiment described above, in the transition to the intermediate state shown inFIG. 2b, firstly the protective material layer61of the protective material region60is formed ideally in conformal fashion.

In the transition to the intermediate state shown inFIG. 2c, firstly the planarization material layer62is then formed, so that cutouts and depressions42, in particular above the first and second contact locations33and34, are filled, and then, in the transition to the intermediate stage shown inFIG. 2d, said layer is converted by etching-back into a reduced planarization material layer62′ with the surface62a′ having been brought back, but the cutouts and depressions42of the previously obtained structure remain filled, thus resulting in a planarized or smoothed surface topography in the structure fromFIG. 2d.

The procedure then once again effects, in a manner analogous to the embodiment described above, the application and patterning of the second metallization layer70, as is shown inFIGS. 2eand2f, with a subsequent patterning of the first metallization layer50and the corresponding passivation, as is shown inFIGS. 2gand2h. The sequence of the processes ofFIGS. 2eto2hthus corresponds approximately to the sequence of the processes ofFIGS. 1eto1hof the embodiment described above.

The sequence ofFIGS. 3ato3dshows that a planarization is not absolutely necessary in accordance with the present invention. In the case of the structure illustrated inFIG. 3a, a protective material layer61of the protective material region60has been applied directly to the continuous first metallization layer50made of the first metal material53.

Instead of a planarization layer62then to be applied, the second metallization layer70made of the second metal material73is then formed directly and is then patterned, in the transition to the intermediate stage fromFIG. 3b, in such a way that a reinforcement of the metallization layers results above the second contact locations34of the second semiconductor circuit region32, that is to say in the region of the power circuit, and the first semiconductor circuit31is freed of the second metallization layer70in its surface region.

In the transition to the intermediate stage shown inFIG. 3c, the first metallization layer50is then patterned, to be precise once again together with the protective material layer61provided thereon, so that the first contacts51arising in this case remain covered by the protective material layer61; this also holds true for the correspondingly arising wiring interconnects55.

In the transition to the intermediate stage shown inFIG. 3d, firstly a passivation is then effected by conformal formation of a passivation layer100with a surface100a, the first semiconductor circuit region31, the transition to the second semiconductor circuit region32and also parts of the second semiconductor circuit region32being covered. Finally, embedding in an imide layer90is effected. It is also conceivable for the entire second semiconductor circuit region32to be embedded.

Furthermore, it is also conceivable to use a single combined conductive and planarizing protective layer60which does not have to be etched back, in accordance withFIG. 4.