Pixel array of ultraviolet light emitting devices

Embodiments of the invention include a first semiconductor layer grown over a growth substrate and a plurality of pixels grown on the first semiconductor layer, each pixel including an active layer disposed between an n-type region and a p-type region. Trenches isolate individual pixels and form at least one sidewall for each pixel. A first metal layer in direct contact with the p-type region is disposed on a top surface of each pixel. A second metal layer in direct contact with the n-type region is disposed on a bottom surface of a trench adjacent to each pixel. An insulating layer electrically isolating the first and second metal layers is disposed on the sidewall of each pixel and is substantially conformal to the sidewall.

BACKGROUND

Description of Related Art

The bandgap of III-nitride materials, including (Al, Ga, In)—N and their alloys, extends from the very narrow gap of InN (0.7 eV) to the very wide gap of AlN (6.2 eV), making III-nitride materials highly suitable for optoelectronic applications such as light emitting diodes (LEDs), laser diodes, optical modulators, and detectors over a wide spectral range extending from the near infrared to the deep ultraviolet. Visible light LEDs and lasers can be obtained using InGaN in the active layers, while ultraviolet (UV) LEDs and lasers require the larger bandgap of AlGaN.

Visible spectrum LEDs based on InGaN and AlInGaP systems have reached maturity and are now in mass production. However, the development of UV LEDs is still hampered by a number of difficulties involving basic material properties of AlGaN alloys, especially those with high Al content. Compared to LEDs in the visible spectral range with external quantum efficiency (EQE, the ratio of extracted photons to injected electron-hole pairs) of more than 50%, deep UV LEDs, such as those emitting below 300 nm, have an EQE of only up to 1%.

UV LEDs with emission wavelengths in the range of 230-350 nm are expected to find a wide range of applications, most of which are based on the interaction between UV radiation and biological material [Khan et al., 2008]. Typical applications include surface sterilization, water purification, medical devices and biochemistry, light sources for ultra-high density optical recording, white lighting, fluorescence analysis, sensing, and zero-emission automobiles. Although under extensive research for many years, UV LEDs, especially those emitting below 300 nm, remain extremely inefficient when compared to their blue and green counterparts. For example, Hirayama et al. recently reported 10.5 mW single-chip LED operation at 282 nm and peak EQE of 1.2% [Hirayama et al., 2009].

Poor current spreading has been one of the major stumbling blocks to obtaining high efficiency deep UV LEDs, due to difficulties in achieving highly conductive yet sufficiently thick n-type AlGaN bottom cladding layers with high Al content. In 2004, Adivarahan et al. proposed a “micro-pixel” LED. The device consists of a 10×10 micro-pixel LED array, with each pixel being a circular mesa of diameter 26 μm. The total physical dimension of the device is 500 μm×500 μm. Since the lateral distance for electron migration before its recombination with a hole is significantly reduced using such geometry, the differential resistance of the device is lowered to 9.8Ω, as compared to standard square geometry LEDs based on the same epitaxial layers with differential resistances from 40 to 14.4Ω [Adivarahan et al., 2004]. Also in 2004, Kim et al. investigated the trade-off between mesa size and output power of circular-geometry deep UV LEDs, and found that without obtaining more conductive n-type and p-type AlGaN cladding layers, the optimized diameter for circular-disk deep UV LED is limited to about 250 μm [Kim et al., 2004].

DETAILED DESCRIPTION

Though the devices described herein are III-nitride devices, devices formed from other materials such as other III-V materials, II-VI materials, Si are within the scope of embodiments of the invention. The active layers of the devices described herein may be configured to emit UV A (peak wavelength between 340 and 400 nm), UV B (peak wavelength between 290 and 340 nm), or UV C (peak wavelength between 210 and 290 nm) radiation.

FIG. 1illustrates an array of UV LED pixels formed on a single substrate, according to embodiments of the invention.FIG. 2illustrates four of the pixels ofFIG. 1in more detail.FIG. 3is a cross sectional view of one of the pixels.

As illustrated inFIG. 1, an array of pixels12is formed on a single substrate. Though the pixels are arranged in a triangular array in the device ofFIG. 1, any suitable arrangement of pixels may be used. For example, the pixels12may be arranged in a hexagonal array, a square array, any other suitable array, randomly, or in any other suitable arrangement.

Though the pixels12are round inFIG. 1, the pixels in any of the devices described herein may be hexagonal, square, rectangular, or any other suitable shape. Though the pixels12inFIG. 1are all the same size and shape, this is not required. Pixels in different parts of the device may have different sizes and/or different shapes.

FIG. 1illustrates the top of the device. The device may be mounted in a flip chip orientation, such that radiation emitted by each pixel is extracted from the device through the bottom of the device, i.e. the surface of the device opposite the surface illustrated inFIG. 1.FIG. 1illustrates a p-contact pad10, which is formed on top of the pixels12, and an n-contact pad20which is located on one edge of the region where the pixels12are formed. The p-contact pad10is electrically connected to the p-type region of each pixel12. The n-contact pad20is electrically connected to the n-type region of each pixel12. Electrical and/or physical interconnects such as, for example, solder pads, may be formed in these regions, then used to electrically and physically connect the device to any suitable structure such as, for example, a mount or a printed circuit board.

FIG. 3is a cross section of one pixel12. The device may be formed by growing a semiconductor structure15on a growth substrate14. One example of a semiconductor structure15is described below. Any suitable semiconductor structure15may be used. Embodiments of the invention are not limited to the semiconductor structure described below.

The substrate material should be capable of supporting the epitaxial growth of III-nitrides including AlGaN, and should have high transmission for UV light so that light can be extracted from the bottom of the device through the growth substrate. Suitable substrates include sapphire, c-sapphire, a-sapphire, m-sapphire, r-sapphire, AlN, c-AlN, a-AlN, m-AlN, r-AlN, Si, (001) Si, (111) Si, SiC, c-SiC, a-SiC, m-SiC, r-SiC, ZnO, c-ZnO, a-ZnO, m-ZnO, r-ZnO, and manufactured substrates. The surfaces of the substrate can be smooth, or either surface can be textured to improve light extraction. Sapphire substrates may be nitridated by exposure to ammonia or plasma-activated nitrogen prior to growth of a buffer layer.

The semiconductor structure15may be grown by any suitable technique including, for example, epitaxy, vapor phase epitaxy, chemical vapor deposition, metal organic chemical vapor deposition, or molecular beam epitaxy. A buffer layer (not shown) may be grown directly onto the substrate and may contain polycrystalline or non-single crystalline structure (i.e., substantially crystalline material containing some defects or boundaries). The purpose of the buffer layer is to establish a quasi-nitride substrate on which the III-nitride film can be grown under compressive stress with reduced density of threading dislocations and high crystalline quality. The buffer layer can be any III-nitride material, such as AlN, GaN, AlGaN, InAlGaN, or mixtures thereof. AlN is a preferred material for the buffer layer. The buffer layer can have a thickness ranging from about 10 nm to 100 microns. The buffer layer may be somewhat thick compared to visible light LEDs so as to prevent cracking of AlGaN deposited on the buffer layer. The thickness of the buffer layer may be in the range from about 1 micron to about 5 microns. Optionally, a plurality of buffer layers can be used, e.g., 2-3 superimposed buffer layers of the same or different materials, instead of a single buffer layer. High growth temperature for the buffer layer is desired in order to produce good quality AlN epitaxial layers. The temperature range for AlN growth should be in the range of 700° C. to 1200° C. across different epitaxial growth tools.

An n-type region16is grown over the buffer layer. The n-type region16may include multiple layers of different composition, dopant concentration, and thickness. The n-type region16may include at least one AlaGa1-aN film doped n-type with Si, Ge and/or other suitable n-type dopants. The n-type region may have a thickness from about 100 nm to about 10 microns and is grown directly on the buffer layer(s). The doping level of Si in the n-type region16may range from 1×1016cm−3to 1×1021cm−3. Depending on the intended emission wavelength, the AlN mole fraction “a” in the formula may vary from 0% for devices emitting at 360 nm to 100% for devices designed to emit at 200 nm. The n-type AlGaN film can also be configured as a multilayer containing a variety of possible AlGaN layer stacks and stack combinations, including, but not limited to n-AlGaN layers doped at different silicon concentrations and their combinations. The use of a multilayer of n-AlGaN can improve lateral conductivity. In a typical embodiment, a three-layer stack structure is used consisting of n-type AlaGa1-aN layer doped with silicon to have free electron concentrations of 1×1017cm−3, 5×1018cm−3, and 1×1019cm−3, with corresponding thicknesses of 1 μm, 500 nm, and 300 nm, respectively. Alternatively, n-type region16can be doped with gradiently increasing or decreasing Si dopant concentration from, for example, 1×1016cm−3to 1×1021cm−3; or it can have a fixed Si dopant concentration but an AlN mole fraction varying from one layer to the next, within the range from 0.0001 to 0.9999. The n-contact metal layers, described below, preferably are formed on the n-AlGaN layer with the highest Si doping. Indium also can be incorporated in the n-AlGaN layer to improve structural quality of the layers and/or to provide strain relief. The total thickness of the n-type region may be in the range from about 500 nm to about 4 microns. All n-type layers described above may be grown under excess Ga conditions, as described in more detail in US 2014/0103289, which is incorporated herein by reference.

An active region18is grown over the n-type region16. The active region may be either a single quantum well or multiple quantum wells (MQWs) separated by barrier layers. The quantum well and barrier layers contain AlxGa1-xN/AlyGa1-yN, wherein 0<x<y<1, x represents the AlN mole fraction of a quantum well layer, and y represents the AlN mole fraction of a barrier layer. The MQWs start with a first barrier layer Aly1Ga1-y1N (0<y1<1) on top of the n-type region16, where y1 can have the same, lower, or higher AlN mole fraction than the portion of the n-type region16closest to the active region18, and the thickness of the first barrier layer is from about 0.1 nm to about 100 nm. On top of first barrier layer, a quantum well layer of Alx1Ga1-x1N is grown, with lower AlN mole fraction than the barrier layer; the thickness of the quantum well layer is from about 0.1 nm to about 100 nm. On top of the quantum well layer, another Aly2Ga1-y2N layer is grown as the second barrier layer. The second barrier layer has a higher AlN mole fraction than the quantum well layer, so as to provide quantum confinement (0<x1<y2<1). Y2 can be equal to or less than y1. The thickness of the second barrier is from about 0.1 nm to about 100 nm. In general the last barrier layer is thicker than the first barrier layer. The active region18may be grown using excess Ga.

A p-type region22is grown over the active region18. Like the n-type region16, the p-type region22may include multiple layers of different composition, dopant concentration, and thickness. The p-type region22may include an electron blocking layer (EBL) adjacent to active region18. The EBL may have a band gap greater than the barrier layers in active region18. The EBL is grown with a thickness in the range from about 1 nm to about 30 nm. The EBL may prevent electrons injected from the n-type region16into the active region18from reaching the p-side of the LED structure. The EBL may be doped p-type or may be undoped, and may be AlGaN or AlN. Following the electron blocking layer, the p-type region22includes one or more p-type doped (e.g. Mg-doped) AlGaN layers. The AlN mole fraction can range from 0 to 100%, and the thickness of this layer or multilayer can range from about 2 nm to about 100 nm (single layer) or to about 500 nm (multilayer). A multilayer used in this region can improve lateral conductivity. The Mg doping level may vary from 1×1016cm−3to 1×1021cm−3. In one embodiment the AlN mole fraction of an AlGaN layer in the p-type region22is half that of the EBL. In another embodiment, p-type region22includes an EBL, a p-type AlGaN layer, and a p-type GaN contact layer. In some embodiments, p-type region22includes alternating p-AlGaN and p-GaN layers. A Mg-doped GaN contact layer may be grown last in p-type region22. The Mg doping level can vary from 1×1016cm−3to 1×1021cm−3. P-type region22may be grown with excess Ga.

The semiconductor structure15is etched to form pixels12. In the region between pixels, the p-type region22and the active region18are etched away to form trenches that reveal a surface of the n-type region16. The sidewall or sidewalls12aof the pixel may be vertical or sloped with an acute angle relative to a major plane of the growth substrate, as illustrated inFIG. 3. The angle12bof the sidewall12arelative to a normal to a major surface of the semiconductor structure15may be at least 30° in some embodiments and no more than 60° in some embodiments. The height38of each pixel may be at least 0.1 micron in some embodiments, not more than 5 microns in some embodiments, at least 0.5 micron in some embodiments, not more than 2 microns in some embodiments, and 1 micron in some embodiments. The width39at the top of each pixel may be at least 5 microns in some embodiments, no more than 50 microns in some embodiments, at least 15 microns in some embodiments, and no more than 25 microns in some embodiments. The width37at the bottom of each pixel may be at least 5 microns in some embodiments, no more than 50 microns in some embodiments, at least 15 microns in some embodiments, and no more than 25 microns in some embodiments. The width39may be at least 80% of the width37in some embodiments, at least 85% of the width37in some embodiments, at least 90% of the width37in some embodiments, and no more than 100% of the width37in some embodiments. The pixels may be shaped as truncated pyramids or cones, as illustrated herein, though this is not required and any suitable shape may be used.

Before or after etching semiconductor structure15to form pixels12, a p-contact24is deposited and patterned, such that p-contact24is disposed on the top of each pixel12. P-contact24may be a single or multiple metal layers. The p-contact24may include one or more metal layers that form an ohmic contact, and one or more metal layers that form a reflector. One example of a suitable p-contact24includes a Ni/Ag/Ti multi-layer contact.

An n-contact28is deposited and patterned, such that n-contact28is disposed on the substantially flat surface of the n-type region16between the pixels12, which was exposed by etching the pixels12. The n-contact28may include a single or multiple metal layers. The n-contact28may include, for example, an ohmic n-contact30in direct contact with the n-type region16, and an n-trace metal layer32formed over the ohmic n-contact30. The ohmic n-contact30may be, for example, a V/Al/Ti multi-layer contact. The n-trace metal32may be, for example, a Ti/Au/Ti multi-layer contact.

The n-contact28and the p-contact24are electrically isolated by a dielectric layer34. Dielectric layer34may be any suitable material such as, for example, one or more oxides of silicon, and/or one or more nitrides of silicon, formed by any suitable method. Dielectric layer34covers n-contact28. Openings formed in dielectric layer34expose p-contact24. Dielectric layer34may extend over the edges of p-contact24as illustrated inFIG. 3, though this is not required. Dielectric layer34does not completely fill the trench between pixels, as illustrated by cross section46which is taken through the pixels in a plane parallel to the growth surface of the substrate, and includes the semiconductor structure15, the dielectric layer34formed on the sidewall of the pixel in the trench between pixels, and the p-trace metal36(described below) formed on the dielectric layer34. Rather, dielectric layer34substantially conformally coats the sidewall(s)12aof each pixel12. For example, the thickness of dielectric layer34over the sidewall may vary less than 50% from an average thickness in some embodiments, less than 20% in some embodiments, and less than 10% in some embodiments. The average thickness34aof dielectric layer34over the sidewall12amay be at least 0.1 micron in some embodiments, not more than 1 micron in some embodiments, at least 0.3 micron in some embodiments, not more than 0.7 micron in some embodiments, and 0.5 micron in some embodiments.

A p-trace metal36is formed over the top surface of the device, and substantially conformally covers the entire top surface. The p-trace metal36electrically connects to the p-contact24in the openings formed in dielectric layer34. The p-trace metal36extends over n-contact28(in a plane parallel to the growth direction), but is electrically isolated from n-contact28by dielectric layer34. The p-trace metal36may be a single metal layer or a multi-layer structure, formed by any suitable technique such as, for example, evaporation. The layer of p-trace metal36that is closest to p-contact24may be a diffusion barrier that prevents or reduces electromigration of metals in the p-contact24, particularly silver if silver is used as a reflector in p-contact24. The layer of p-trace metal36furthest from p-contact24may be selected to adhere to interconnects (such as, for example, solder) used to connect the device to a mount. Examples of suitable multi-layer p-trace metals include Ti/Pt/Au, Ti/Pt/Au/Pt/Au, and Ti/Pt/Au/Ti/Cr/Au.

As described above and illustrated inFIG. 3, the p-trace metal36does not fill the trench between pixels, but conformally coats the sidewall12aof each pixel. For example, the thickness of the p-trace metal36over the sidewall may vary less than 50% from an average thickness in some embodiments, less than 20% in some embodiments, and less than 10% in some embodiments. The average thickness of the p-trace metal36over the sidewall12amay be at least 0.1 micron in some embodiments, not more than 1 micron in some embodiments, at least 0.3 micron in some embodiments, not more than 0.7 micron in some embodiments, and 0.5 micron in some embodiments.

FIG. 2is a top view of four of the pixels illustrated inFIG. 1. The p-trace metal36, which covers the entire surface, is omitted for clarity. The p-contact24is smaller than and substantially concentric with the edge26of the mesa that forms each pixel12. The n-contact28is disposed in the region between the pixels12. Except for openings in the n-contact28to accommodate the pixels, the n-contact28forms a continuous sheet, which extends to the edge of the device into n-contact pad20, illustrated inFIG. 1. The n-contact28and p-contact24are electrically isolated by dielectric layer34, which extends over the sidewalls of each pixel, as illustrated inFIG. 3.

FIG. 4illustrates a region between two pixels12. As described above, both dielectric layer34and p-trace metal36are substantially conformal layers, which do not fill the trench between the pixels.FIG. 4illustrates an interconnect40disposed over the device. The interconnect40is used to electrically and mechanically connect the device to another structure. Solder is often used as interconnect40but any suitable material may be used. Interconnect40covers the tops of each pixels, and also fills the trench42between pixels, such that the top and sidewall(s) of each pixel are surrounded by interconnect40. For example, cross section44is taken through the pixels, in a plane parallel to the growth surface of the substrate (not shown inFIG. 4). Cross section44passes through the pixels12, dielectric layer34, p-trace metal36, and interconnect40, all three of which are disposed in the trench between pixels12. Interconnect40is typically a thermally conductive material. Accordingly, disposing the interconnect40adjacent the sidewall(s) of pixel12allows heat to be extracted laterally from the semiconductor structure, as illustrated by arrows52, instead of just vertically from the semiconductor structure, as illustrated by arrow50.

Forming a device with pixels, instead of a device with a single, large area active region, increases the surface area of the device, which may improve heat extraction from the device. Modeling of heat extraction from the device suggests that when the pixel height (i.e., the height of the semiconductor material in each pixel) is at least 10% of the pixel radius at the top of the pixel, heat extraction from the device may increase at least 20% over a device with a single, large area active region. As the pixel height increases relative to the radius of the pixel, heat extraction may further improve.

As illustrated inFIG. 4, in the bottom of the trench between pixels12, on a substantially flat surface of the n-type region, the p-trace metal36, dielectric layer34, and n-contact28are stacked on the n-type region. The stack is illustrated in more detail inFIG. 5. The stack forms a capacitor13, which may protect the device from electrostatic discharge.

Each of n-contact28, dielectric layer34, and p-trace metal36may be substantially planar in the region that forms the capacitor13, such that the capacitor behaves as a parallel plate capacitor. The average thickness48of dielectric layer34between n-contact28and p-trace metal34may be at least 0.1 micron in some embodiments, not more than 1 micron in some embodiments, at least 0.3 micron in some embodiments, not more than 0.7 micron in some embodiments, and 0.5 micron in some embodiments.

The pixel12and the capacitor13illustrated in cross section inFIG. 4are connected in parallel, as illustrated in the circuit diagram shown inFIG. 9. Serial resistance of the circuit illustrated inFIG. 9may be 100 ohm at steady-state operating drive current. Series resistance of the circuit may be greater than 100,000 ohm during turn-on of the circuit. The behavior of the circuit illustrated inFIG. 9may be modeled by the human body model (HBM) circuit, a standard and well established model to study electrostatic discharge performance in a circuit. The human body model circuit is illustrated inFIG. 10. HBM modeling indicates that during turn-on of the pixel12, capacitor13may reduce peak current through the pixel12by two orders of magnitude, from 2.5 A down to 19 mA under 100,000 ohm series resistance for the circuit ofFIG. 9. Under operating drive current, the capacitor13has minimal effect.

In the embodiments illustrated inFIGS. 3 and 4, the etch that forms the pixels terminates on the n-type region16. In the embodiments illustrated inFIGS. 6 and 7, the etch may remove the entire n-type region, such that it terminates on an insulating layer, such as a buffer layer grown before n-type region16, or on the substrate14. In some embodiments, the etch may even remove part of the substrate14. The etches that form the pixels inFIGS. 6 and 7are therefore deeper than the etches that form the pixels inFIGS. 3 and 4, which may allow the pixels ofFIGS. 6 and 7to have steeper sidewalls than the pixels illustrated inFIGS. 3 and 4. Steeper sidewalls may increase the amount of light that escapes each pixel through the sidewalls, by reducing total internal reflection. For example, the angle12bof the sidewall in the device ofFIG. 3may be at least 30° in some embodiments and no more than 60° in some embodiments, as described above. The angle80of the sidewall in the device of eitherFIG. 6orFIG. 7may be, for example, at least 10° in some embodiments and no more than 60° in some embodiments.

In the structure illustrated inFIG. 6, a single etch forms the pixels12. Between the pixels, the entire n-type region is removed. The etch to form the pixels may terminate on the substrate14, as illustrated inFIG. 6, or on an insulating layer such as a buffer layer, or a single crystal layer grown before the n-type region16that is not intentionally doped.

The n-contact28may be formed on the side wall60of the n-type region16. For electrical isolation, n-contact28does not cover the entire side wall of the pixel12; rather, n-contact28terminates before the sidewall64of active region18. N-contact28may extend over the exposed region62of substrate between the pixels12, though this is not required.

In the structure illustrated inFIG. 7, the pixels12are formed in two etching processes, such that two mesas are formed. In one etching process, the semiconductor material between pixels12is removed. This etch may terminate on an insulating layer, such as a buffer layer grown before n-type region16, or the substrate14. In the other etching process, at the top of the pixel, a portion of the p-type region22and active region18are removed to expose a portion76of the n-type region. The exposed portion76of the n-type region may surround the remaining portion of the active region18and p-type region22, though this is not required. The n-contact28is formed on the exposed portion76of the n-type region. The n-contact28may extend over the edge70of the n-type region16and on to the sidewall78of the pixel12, though this is not required. A metal layer75may be disposed on the n-contact28, over the sidewalls of the pixel, and in the region between the pixels12, for example on the surface of the substrate14(or whichever surface is exposed by the etching process described above). Metal layer75may be the same material as n-contact28, or a different material. In some embodiments, n-contact28includes Al and the metal layer75includes Au. The metal layer75may extend to the side of the chip to form an n-pad for soldering, as illustrated inFIG. 1.

FIG. 8is a top view of the pixel illustrated inFIG. 7. The p-contact24is at the center of the figure, disposed on a first mesa. The edge of the top of the first mesa is defined by ring72. The diameter of the first mesa (ring72) may be at least 5 microns in some embodiments, no more than 30 microns in some embodiments, at least 10 microns in some embodiments, and no more than 20 microns in some embodiments. The bottom of the first mesa is defined by ring73. The n-contact28is disposed on a second mesa, the top of which is defined by rings73and70. The bottom of the second mesa is defined by ring74. The diameter of the second mesa (ring70) is at least 12 microns greater than the diameter of the first mesa, in some embodiments. The diameter of the second mesa may be at least 15 microns in some embodiments, no more than 45 microns in some embodiments, at least 20 microns in some embodiments, and no more than 30 microns in some embodiments. Larger second mesas may improve light extraction from the pixel. Both the first and second mesas have sloped sidewalls, such that the bottom of each mesa is wider than the top.

Having described the invention in detail, those skilled in the art will appreciate that, given the present disclosure, modifications may be made to the invention without departing from the spirit of the inventive concept described herein. In particular, different features and components of the different devices described herein may be used in any of the other devices, or features and components may be omitted from any of the devices. Therefore, it is not intended that the scope of the invention be limited to the specific embodiments illustrated and described.