Cluster system for eliminating barrier overhang

A cluster tool is disclosed that can increase throughput of a wafer fabrication process by facilitating removal of barrier overhang in contact holes of contact film stacks. Individual chambers of the cluster tool provide for deposition of barrier material onto a semiconductor structure, depositing over with an amorphous carbon film (ACF), etching back the ACF, and etching a corner region of the contact hole. Removal of the barrier overhang improves the quality of metal fill-in of the contact hole. An expectedly ensuing feature entails a technique in which filling-in of the contact hole with a metal such as tungsten can be achieved with attenuated or eliminated adverse consequence.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates generally to semiconductor fabrication methods and, more particularly, to a system for fabricating contact holes.

2. Description of Related Art

Integrated circuit devices typically are composed of layers of semiconductor and insulating material modified using known manufacturing methods to form active and other microstructures such as gates, drains, sources and the like. These microstructures then are interconnected with conducting material in order to provide the desired functionalities of a given integrated circuit. The interconnecting may be achieved using contact holes filled with a highly conductive metal. Known manufacturing methods have been devised to achieve the required interconnections.

Conducting metal in a contact hole must be isolated from the surrounding integrated circuit material. Failure to isolate properly the conducting metal from those surrounding materials may result in intermixing of the conducting metal and the other materials or their functionalities due to, for example, diffusion in one direction and/or the other. These undesired diffusion processes tend to degrade performance of the integrated circuit and to result in lower yields. In order to provide proper isolation between the different classes of material, a thin layer of barrier material is often disposed between the conducting metal and the surrounding material, e.g., by way of lining the contact hole with barrier material as a step in the fabrication process.

Creating a conducting path through a contact hole in the integrated circuit material can involve at least two steps, one being to deposit a thin film of barrier material that lines the contact hole and the other being to fill the lined contact hole with conducting material.

As contact hole sizes become smaller, slight variations in the process of depositing the film of barrier material can become more important. For example, an overhang profile may result that may partially occlude an opening to a contact hole, thereby impeding metal fill-in of the contact hole and producing imperfections such as voids and/or seams in the conducting metal fill-in. These imperfections can degrade reliability, reduce yields, and increase manufacturing costs of the integrated circuits.

A need thus exists in the prior art for a method of eliminating barrier material overhang that can result in incomplete fill-in of contact holes in an integrated circuit. A further need exists for apparatus to implement the method in fashions which are reliable yet rapid.

SUMMARY OF THE INVENTION

The present invention addresses these needs by providing a cluster tool for metal fill-in of contact holes in integrated circuits. The cluster tool herein disclosed comprises, according to one embodiment, a first chamber for depositing barrier material. The first chamber may comprise a radio-frequency physical vapor deposition (RF PVD) chamber that, further, may be adapted to deposit metal for a damascene metal gate. According to another embodiment, the first chamber comprises a chemical vapor deposition (CVD) chamber. The first chamber, in typical embodiments, is made to deposit one or more of titanium, titanium nitride, and aluminum. The cluster tool further comprises, according to the embodiments, a second chamber for fill-in of (e.g., via deposition) an amorphous carbon film (ACF), and a third chamber for performing etchback of the ACF and barrier-material corner etch.

One aspect of the invention can comprise a method for ultra metal fill-in of a contact hole, an implementation of which may include etching to form a contact hole followed by depositing a barrier material within the contact hole. The barrier material is deposited to form a thin layer covering surfaces of the contact hole, whereby the depositing may undesirably result in formation of an overhang that partially occludes an opening of the contact hole. The implementation continues by coating, e.g., depositing over the contact hole with an ACF, etching back the ACF to expose the overhang (e.g., the barrier overhang), and etching to remove the barrier overhang. The ACF then may be stripped. The depositing may comprise depositing titanium, titanium nitride, or aluminum. Elimination of the barrier overhang may facilitate fill-in of the contact hole with conducting metal, thereby increasing reliability and yield of integrated circuit wafer fabrication processes.

While the apparatus and method has or will be described for the sake of grammatical fluidity with functional explanations, it is to be expressly understood that the claims, unless indicated otherwise, are not to be construed as limited in any way by the construction of “means” or “steps” limitations, but are to be accorded the full scope of the meaning and equivalents of the definition provided by the claims under the judicial doctrine of equivalents.

Any feature or combination of features described or referenced herein are included within the scope of the present invention provided that the features included in any such combination are not mutually inconsistent as will be apparent from the context, this specification, and the knowledge of one skilled in the art. In addition, any feature or combination of features described or referenced may be specifically excluded from any embodiment of the present invention. For purposes of summarizing the present invention, certain aspects, advantages and novel features of the present invention are described or referenced. Of course, it is to be understood that not necessarily all such aspects, advantages or features will be embodied in any particular implementation of the present invention. Additional advantages and aspects of the present invention are apparent in the following detailed description and claims that follow.

DETAILED DESCRIPTION OF THE PRESENTLY PREFERRED EMBODIMENTS

Embodiments of the invention are now described and illustrated in the accompanying drawings, instances of which are to be interpreted to be to scale in some implementations while in other implementations, for each instance, not. In certain aspects, use of like or the same reference designators in the drawings and description refers to the same, similar or analogous components and/or elements, while according to other implementations the same use should not. According to certain implementations, use of directional terms, such as, top, bottom, left, right, up, down, over, above, below, beneath, rear, and front, are to be construed literally, while in other implementations the same use should not. The present invention may be practiced in conjunction with various integrated circuit fabrication and other techniques that are conventionally used in the art, and only so much of the commonly practiced process steps are included herein as are necessary to provide an understanding of the present invention. The present invention has applicability in the field of semiconductor devices and processes in general. For illustrative purposes, however, the following description pertains to a cluster tool for metal fill-in and a related method of manufacture.

Referring more particularly to the drawings,FIG. 1Ais an illustration of a portion of a prior art integrated circuit structure100that includes undulations in the form of a plurality of contact holes120formed in an oxide layer110of an integrated circuit. A depth111of the contact holes120may range from about 400 nm to about 800 nm with a typical value being about 600 nm. The contact holes120may be separated by a distance112that may range from about 20 nm to about 40 nm with a preferred separation of about 30 nm. Each of the contact holes120may have a transverse diameter ranging from about 40 nm to about 60 nm, diameters normally being about 50 nm. The contact holes120may be fabricated using known methods including, as an example, patterning an upper surface of integrated circuit material, e.g., the oxide layer110, and etching with fluorine base chemistry.

FIG. 1Bis a magnified view of a region A outlined with phantom lines inFIG. 1Aof a typical contact hole120in the prior art integrated circuit structure100. (Note: The contact hole120illustrated inFIG. 1Band subsequent figures is shown as having a rectangular cross-section, although the true shape of the contact hole120may or may not include a taper or other desired cross-section as suggested inFIG. 1A.) A barrier layer130may be deposited over the integrated circuit structure ofFIG. 1A, which barrier layer130tends to line the contact holes120, as illustrated inFIG. 1B. Subsequent to deposition of the barrier layer130, a layer of conducting metal, e.g., tungsten,140may be deposited with the consequence of filling the contact hole120. Methods of the prior art may introduce a barrier overhang135that may undesirably constrict or partially occlude the opening to the contact hole120as illustrated inFIG. 1B. The barrier overhang135reduces the available cross-section122of the contact hole120from a desired width that may range from about 10 nm to about 30 nm to a problematic width of about 20 nm. When the contact hole120is filled with conducting metal (e.g., tungsten)140, an imperfection such as a seam, a gap or, in the present example, a void150may form in the tungsten. The illustrated void150may have a width151that can vary from about 20 nm to about 40 nm, which may adversely affect a value of conductance of a contact formed through the contact hole120, thereby degrading the performance of the integrated circuit.

FIG. 2Ashows a contact hole120formed through one or more layers of an integrated circuit structure, which may be similar to that illustrated inFIG. 1A, at an intermediate stage of a sequence of processing steps. The one or more layers may comprise, for example, a multi-layer film stack formed over a substrate. Although the substrate preferably comprises a silicon substrate, in alternative embodiments the substrate can comprise materials such as gallium nitride (GaN), gallium arsenide (GaAs), or other materials commonly recognized as suitable semiconductor materials to those skilled in the art. The one or more layers in this example are represented by a dielectric (e.g., an oxide) layer110.

Dimensions of the contact hole120may be similar to those as would occur in the above with reference toFIGS. 1A and 1B. For instance, a depth111of the contact holes120may range from about 400 nm to about 800 nm with a typical value being about 600 nm. The contact holes120may be separated by a distance112that may range from about 20 nm to about 40 nm with a preferred separation being about 30 nm. Each contact hole may have a transverse diameter ranging from about 40 nm to about 60 nm, with diameters normally being about 50 nm. The contact hole(s)120may be fabricated using known methods including, as an example, patterning an upper surface of integrated circuit material, e.g., the oxide layer110, and etching with fluorine base chemistry.

The contact hole120ofFIG. 2Ahas been overlaid with a thin film/layer of barrier material130such as titanium nitride (TiN) or Ti. In the illustrated embodiment, TiN may be selected for deposition as the barrier material, it being a hard, dense, refractory material which can provide benefits such as high electrical conductivity. In modified embodiments, the barrier layer130may comprise other compositions (e.g., composites/materials with similar properties) which may be recognized by those skilled in the art in view of this disclosure as suitable, a few being, without limitation, one or more of tantalum nitride (TaN), wolfram nitride (WN), molybdenum nitride (MoN), and Ti/TiN, deposited by, for instance, chemical vapor deposition (CVD). The term Ti/TiN may refer to either a titanium layer which has been annealed in a nitrogen atmosphere to at least partially convert the titanium to TiN, or a thin titanium layer on which is deposited a thin TiN layer by a separate process step. According to certain aspects of the invention, the barrier layer130can be formed using known techniques to thicknesses ranging, typically, from about 5 nm to about 30 nm, with an exemplary dimension being about 20 nm.

As shown in the diagram, a barrier overhang135in the barrier layer130may distort or partially occlude the opening to the contact hole120. This occlusion may prevent complete fill-in of a conducting metal (e.g., tungsten) as described above in relation toFIG. 1B. According to a feature of the present invention, structure and steps are utilized to attenuate adverse consequences which may result from the barrier overhang135, whereby there may be facilitated a more complete fill-in of the contact hole120with the tungsten.

Pursuant to this feature of enabling better fill in, the contact hole120shown inFIG. 2Amay, as a next processing step, be filled with another material such as a dielectric. In implementations such as that illustrated inFIG. 2B, the dielectric may take the form of a layer160formed, for example, of amorphous carbon film (ACF). The ACF160may substantially fill the contact hole120and may (in exemplary embodiments) overlay top surfaces of the dielectric layer110.

Succeeding processing steps may include an etchback that removes an upper portion of the ACF160as illustrated inFIG. 2C. A lower portion161of the ACF may remain after this step to protect the bottom of the contact hole120. Etchants employed to remove the upper portion of ACF160may comprise, as examples, O2or H2/N2. According to one instance of the etchback, the structure ofFIG. 2Bmay be bombarded with particles, e.g., argon, to remove a surface/upper portion of the ACF160as illustrated inFIG. 2C. The etchback, and/or another step thereof, may in certain implementations, remove ACF160so as to expose the barrier overhang135and/or may reduce a surface thickness of exposed parts of the barrier layer so that the thickness of the barrier layer170inFIG. 2Dmay (in certain implementations) be less than the corresponding thickness thereof inFIG. 2Band/orFIG. 2C. A lower portion161/162of the ACF layer may be retained after the etchback, the retained portion acting to protect a bottom of the contact hole120during ensuing processing.

Subsequent to the etchback, an etch step using etchants such as Cl2or BCl3may be performed to remove the barrier overhang135, a residual amount162of the ACF continuing to be present to protect the bottom of the contact hole120as illustrated inFIG. 2D. The remaining ACF162may be removed by a dry or wet strip process such as, respectively, via O2ash or backend solvent for metal clean, a result of the strip process being illustrated inFIG. 3, thereby preparing the contact hole120for deposition of tungsten.

The contact hole120may then be filled with a highly conducting metal, examples of which may include aluminum, tungsten, copper, and/or an alloy of a combination of the aforesaid and other trace elements. A typical implementation can comprise the deposition of tungsten180as illustrated inFIG. 4. In cases where the tungsten may exhibit a tendency to peel back, the barrier layer130may assist as an adhesive layer for preventing peeling or loosening of the tungsten. The barrier layer130as applied over the sidewalls and bottom of the contact hole120hence can assure adhesion of the tungsten, and, further, may aid in preventing spiking and/or electromigration. Importantly, in accordance with a key advantage of the discovered technique described herein, the fill-in (e.g., with tungsten) is substantially uniform and free of voids, seams, gaps or other defects

FIG. 7is a flow diagram describing an implementation of a method of the present invention. According to the illustrated activity, a semiconductor structure having at least one contact hole is provided at step510.FIG. 1Aillustrates a collection of such contact holes120. A barrier material layer, which may be formed for example as above, is deposited at step520. The result of this depositing may appear as depicted in the cross-section of a contact hole120illustrated inFIG. 2A, which depicts a barrier layer130lining the contact hole120while undesirably exhibiting a barrier overhang135. At step530, and with reference toFIG. 2B, an ACF is deposited over the contact hole120.

At step540an etchback of the ACF160is performed. This etchback, which may employ etchants as mentioned above, may remove, for instance, an upper portion of the ACF160(FIG. 2B). A mechanism of the etchback according to featured implementations of the invention is the exposing of the barrier overhang at top corners of the contact hole120, as illustrated inFIG. 2C. A lower portion161of the ACF may remain to protect the bottom of the contact hole120.

Subsequently, at step550, an etch is performed using, e.g., etchants as noted above, to attenuate and/or remove (e.g., eliminate) operationally-compromising parts of the barrier layer130, such as the barrier overhang135, whereby removal of the portions of the barrier layer130may leave a thinner barrier layer170on a surface of the structure as depicted inFIG. 2D. That is, the thickness of the barrier layer170may be less than the thickness of the barrier layer130shown inFIG. 2C. (The thickness may be measured in a direction perpendicular to a surface of the integrated circuit structure100.) For example, the etch at step550may result in a thickness of the barrier layer170ranging from about 0 nm to about 20 nm with a typical value being about 10 nm, whereas in comparison the thickness of the barrier layer130may range from about 5 nm to about 30 nm, normally about 20 nm. An additional amount of the lower portion161of the ACF (FIG. 2C) may be removed at step550leaving a reduced ACF portion162that continues to protect the bottom of the contact hole120.

The reduced ACF portion162may be stripped at step560using a dry/wet process, thereby leaving the contact hole120with a substantially reduced barrier overhang or, preferably, with no barrier overhang, as illustrated inFIG. 3and, as shown inFIG. 4, suitable for fill-in with tungsten180.

In accordance with the preceding, subsequent metal fill-in of the contact hole, cf.563, can be associated with (e.g., enabled with) a reduced incidence and degree of defect as a consequence of the barrier overhang removal. That is, the expectedly ensuing step563according to the invention, entailing a technique in which filling-in of the contact hole with a metal such as tungsten is facilitated, can be achieved with attenuated or eliminated adverse consequence. In instances where the thickness of the barrier layer170is zero after the etch at step550, a second barrier layer may be deposited in order to avoid poor adhesion during metal fill-in at step563.

A further aspect of the invention may include a single cluster tool adapted to implement the method outlined above with reference toFIG. 7. Cluster tools, which may be employed to increase throughput of a wafer fabrication process, are known components of manufacturing facilities. According to one embodiment of the present invention, a cluster tool300, as illustrated schematically inFIG. 5, comprises three or more integrated chambers, each being collocated with a single, shared main platform and each being adapted to perform particular steps of implementations of methods of the invention as set forth herein

For example, with reference toFIG. 2A, a load/lock chamber301is adapted to receive a wafer to be processed according to the present invention, and a transfer module303may facilitate transfer of the wafer to a plurality of (e.g., three) chambers, wherein processing may be sequentially performed. In the illustrated embodiment, a first chamber310of the cluster tool300is adapted to perform deposition of a barrier layer130, the barrier material comprising Ti, TiN, or Al, as examples. This deposition may correspond, for example, to the deposition performed at step520of the implementation described inFIG. 7. Examples of deposition processes which may deposit the barrier material include radio-frequency physical vapor deposition (RF PVD) or the above-mentioned CVD. It should be noted that the RF PVD chamber also may be used or usable to deposit metal in a process of forming a damascene metal gate.

A second chamber320of the cluster tool300is configured to deposit an ACF160, as illustrated inFIG. 2B. A third chamber330may be employed to etch back the ACF160and to perform an etch of the barrier material overhang (e.g., barrier-material corner)135as illustrated inFIGS. 2A, 2B and 2C. As described above relative to respective steps540and550(FIG. 7) of the implementation, etches performed in the third chamber330following the mentioned prior processing by and within the cluster tool can have an effect of eliminating the barrier overhang135of the barrier material.

An alternative embodiment of a cluster tool400, according to the present invention, may comprise four chambers as illustrated inFIG. 6. This embodiment comprises load/lock chamber401and a transfer module403that may be similar or identical to the respective load/lock chamber301and transfer module303described above with reference toFIG. 5. The embodiment further comprises a first chamber410dedicated to a deposition process comprising RF PVD. A second chamber420implements a CVD process. Remaining chambers430and440may be similar or identical to respective chambers320and330described above with reference toFIG. 5.

Although the disclosure herein refers to certain illustrated embodiments, it is to be understood that these embodiments have been presented by way of example rather than limitation. For example, the invention may be applied to other processes at mid-end-of-line (MEOL) or front-end-of-line (FEOL) stages of wafer fabrication that can benefit from a CVD chamber, an ashable amorphous carbon gap-fill (e.g., coating) chamber and an amorphous carbon etchback and corner etch chamber. The intent accompanying this disclosure is to have such embodiments construed in conjunction with the knowledge of one skilled in the art to cover all modifications, variations, combinations, permutations, omissions, substitutions, alternatives, and equivalents of the embodiments, to the extent not mutually exclusive, as may fall within the spirit and scope of the invention as limited only by the appended claims.