Method and apparatus for inhibiting a predecoder when selecting a redundant row line

A circuit is provided for replacing a defective signal path (94) of a plurality of like signal paths with a redundant signal path (95, 96). A redundant decoder (72) is programmable to respond to a plurality of predetermined addressing signals (RFn) that normally operate to address the defective signal path (94, ROWL1R and ROWLIL). The redundant decoder is operable to generate a disable signal (RREN) in response to the predetermined addressing signals (RFn) and also is operable to select a redundant signal path (95, 96) in response thereto. A decoding circuit (70, 74) normally decodes selected ones of a plurality of addressing signals (RFn) and selects at least one of a plurality of signal paths in response thereto. The decoding circuit (70, 74) is coupled to the redundant decoder (72) for receiving the disable signal (RREN) therefrom. In response to receiving this disable signal (RREN) the decoding circuit (70, 74) will not decode the preselected addressing signals (RFn).

TECHNICAL FIELD OF THE INVENTION 
The present invention relates in general to the selection of redundant row 
lines, and more particularly relates to a method and apparatus for 
deselecting a defective row line and selecting a redundant row line using 
a programmable redundant row redundant decoder. 
BACKGROUND OF THE INVENTION 
New and different types of DRAM array architecture as well as tighter 
design specifications for integrated circuit chip size require new designs 
for implementing redundant row lines and the circuits for enabling them. 
The provision of redundant row lines allows faulty word lines to be 
replaced in order to repair the DRAM to a sellable status. 
One conventional row redundancy method is to blow a fuse between a bad word 
line and its respective decoder circuit, thus disabling the faulty word 
line. Fuses are also blown in a redundant decoder in order to program the 
redundant decoder to connect a redundant word line to a global drive/boot 
signal line when the redundant address is selected. This replaces the bad 
word line or row line with a redundant word line. A disadvantage of this 
conventional method is that each word line must have a fuse located 
between it and its row decoder. This can take up large amounts of space 
and may not even be possible to implement on chips with small row pitches. 
This method is however efficient since only the bad word line is replaced 
and not several other good word lines along with it. 
Other conventional methods of enabling redundant row lines and disabling 
faulty word lines will be discussed below, but may be briefly reviewed 
here. In order to program a redundant row line according to another 
method, a fuse is blown in the normal decoder to disable it and all word 
lines connected to it. Fuses are then blown in a redundant decoder to 
program it to replace the decoder and its bad word line. Although only one 
fuse is needed for every four word lines, this method is relatively 
inefficient in replacing bad word lines since one bad word line will cause 
three other good word lines to be replaced in addition to itself. 
A third conventional method is to blow fuses in a redundant decoder in 
order to program it to the address of the bad word line. Then, once this 
redundant decoder detects the redundant address, it completely disables a 
global drive/boot signal generator that would drive the bad word line 
through a decoder, and enables a redundant drive/boot generator which then 
drives a redundant word line through the redundant decoder. Therefore, the 
replaced word line does not become active since the normal drive/boot 
generator is disabled for this cycle. Although this method does not need a 
fuse for each word line or even for each row decoder, it is 
disadvantageous in that a separate redundant drive/boot generator is 
required in the peripheral area of the chip. In view of the drawbacks of 
each of these conventional methods, a need has arisen for a redundancy 
scheme that will have the capability of replacing a single word line but 
nonetheless does not require a fuse for each row or an additional 
drive/boot signal generator. 
SUMMARY OF THE INVENTION 
One aspect of the invention comprises a circuit for replacing a defective 
signal path of a plurality of like signal paths with a redundant signal 
path. The circuit comprises a redundant decoder programmable for 
responding to a plurality of predetermined addressing signals 
corresponding to the defective signal path. The redundant decoder is 
operable to generate a disable signal and to select a redundant signal 
path in response to the predetermined addressing signals. A decoding 
circuit for decoding selected ones of a plurality of addressing signals 
and selecting at least one of a plurality of signal paths in response 
thereto is provided, and is coupled to the redundant decoder for receiving 
the disable signal. The decoding circuit signal will fail to decode the 
predetermined addressing signals in response to receiving the disable 
signal. 
In another aspect of the invention, the decoding circuit includes a local 
predecoder and a bank of decoders. The bank of decoders are coupled to the 
local predecoder with a plurality of local predecoder lines. The local 
predecoder is coupled to the redundant decoder by the disable signal, and 
becomes disabled by being blocked from selecting one of the local 
predecoder lines in connecting a global signal source to the decoders. 
In a further aspect of the invention, the redundant decoder comprises a 
plurality of addressing transistors. Each of the transistors is operable 
by receipt of a respective addressing signal to couple a node to a supply 
of a first voltage. Each addressing transistor is coupled to the node 
through an isolation device. The redundant decoder is programmed by 
causing selected ones of the isolation devices to isolate respective 
transistors from the node. Then, when a set of addressing signals is 
received by the redundancy decoder which corresponds to the defective 
signal path, the addressing transistors will be unable to couple the node 
to the supply of the first voltage. The node therefore remains at a second 
voltage, which causes circuitry coupled to it to both generate the disable 
signal and to connect a redundant row line to the global signal source. 
One advantage of the invention is that the use of fuses for each word line 
or row decoder is avoided. Only one global signal source such as a 
drive/boot signal generator need be provided. The present invention 
nevertheless allows the replacement of a single bad word line with a 
single redundant word line, thereby having optimum redundancy efficiency. 
In a preferred embodiment, each redundant decoder is capable of replacing 
two defective word lines with two redundant word lines.

DETAILED DESCRIPTION OF THE INVENTION 
FIG. 1 illustrates one prior art redundancy circuit indicated generally at 
10. A plurality of drive/boot signal lines 12 are connected to a 
drive/boot signal generator located in a periphery of a DRAM array (not 
shown) and are further connected to a row decoder 14 and a redundant row 
decoder 16. Row decoder 14 and redundant row decoder 16 are repeated many 
times within the cell array area. Each row decoder 14 has a fuse 18 for 
disabling its operation. A plurality of row or word lines 20, 22, 24 and 
26 are connected to the row decoder 14. A plurality of redundant word 
lines 28, 30, 32 and 34 are connected to the redundant row decoder 16. 
When a bad word line such as word line 22 is discovered, the fuse 18 of the 
row decoder 14 is blown, and further fuses (not shown) within the 
redundant row decoder 16 are blown to program it to receive a particular 
set of addressing signals (not shown). The result is to replace an entire 
section 36 of the word lines 20-26 with redundant word lines 28, 30, 32 
and 34. As can be seen, this redundancy scheme is markedly inefficient, as 
three normal word lines 20, 24 and 26 are replaced along with the one 
defective word line. 
FIG. 2 is a schematic block diagram illustrating another conventional 
redundancy scheme. A single drive/boot generator 38 is connected by a 
drive/boot generator signal line 40 to one of a plurality of row decoders 
42 (one shown). Each row decoder 42 is in turn connected to four word 
lines 44, 46, 48 and 50. A redundant row decoder 52 is provided for a 
plurality of row decoders 42 (one shown). A redundant drive/boot signal 
generator line 54 connects each of the redundant row decoders 52 to a 
redundant drive/boot signal generator 56. The redundant row decoder 52 is 
further connected to a redundant word line 58. A disable line 60 connects 
each of the redundant row decoders 52 to the drive/boot signal generator 
38, while an enable line 62 couples each of the redundant row decoders 52 
to the redundant drive/boot signal generator 56. 
In the operation of this conventional redundancy scheme, fuses (not shown) 
are blown in the redundant row decoder 52 in order to program it to the 
address of a bad word line 46. Once the redundant decoder 52 detects the 
redundant address by the receipt of a set of addressing signals on a 
plurality of addressing signal lines (not shown), it will completely 
disable the standard drive/boot signal generator 38 and will enable the 
redundant drive/boot signal generator 56. A drive/boot signal therefore 
does not get transmitted through line 40, decoder 42 and to the bad word 
line 46. Instead, a redundant drive/boot signal is transmitted along line 
54 through the redundant row decoder 52 and out to the redundant word line 
58. While this second scheme replaces a single bad word line 46 with a 
redundant word line 58, it also requires a set of global disable and 
enable lines 60 and 62 and an extra drive/boot signal generator 56 which 
is used only for row redundancy. 
A schematic block diagram of a redundancy circuit according to the 
invention is shown in FIG. 3, and is indicated generally at 64. A single 
drive/boot signal generator 66 is coupled by a single RLXH line 68 to each 
of a plurality of local row predecoders 70 (one shown) and a like 
plurality of redundant decoders 72 (one shown) within the array. Each 
local row predecoder 70 is further connected to a respective plurality of 
row decoders 74 (one shown) by a plurality of local row predecoder lines 
RDD0-RDD3. Each row decoder 74 is connected to a respective plurality of 
word lines 76, 78, 80 and 82. The redundant decoder 72 is connected to one 
or more redundant word lines 84 (one shown). A disable signal line 86 is 
operable to carry a disable signal RREN from the redundant decoder 72 to a 
respective particular local row predecoder 70. 
As will be more particularly explained in conjunction with FIGS. 6, 7 and 
8, each redundant decoder 72 is capable of receiving a plurality of 
addressing signals (not shown in FIG. 3). The local row predecoder 70 and 
row decoder 74 together constitute a decoding circuit that also receives 
these same addressing signals. The addressing signals normally operate to 
select one local row predecoder within a quadrant on the chip (see FIG. 
4), one of a plurality of row decoders 74 within each decoder bank, and 
one of the four word lines 76-82 connected to each row decoder. 
When a bad word line such as word line 78 is discovered, fuses (see FIG. 
8), switches or other isolation devices can be blown or programmed within 
the redundant decoder 72 such that the redundant decoder 72 will recognize 
the set of addressing signals corresponding to the bad word line 78. In 
response to this set of addressing signals, the redundant decoder 72 will 
generate a disable signal on line 86, thereby disabling the local 
predecoder 70 from selecting one of the local predecoder lines RDD0-RDD3. 
This same recognition of the set of addressing signals actuates the 
redundant decoder 72 to connect a redundant word line 84 to the RLXH line 
68, thereby completing a redundant signal path in replace of a path 
including the bad word line 78. 
Referring now to FIG. 4, a layout of a dynamic random access memory (DRAM) 
chip is shown generally at 85. Throughout FIGS. 3-8, like characters 
identify like structure where possible. The particular layout shown is for 
a four megabit DRAM. The chip 85 includes a cell array area indicated 
generally at 83, and a pair of end peripheral areas 87 and 88 within the 
cell array area 83. 
In the illustrated embodiment, a row factor signal generator (not shown) 
and a drive/boot signal generator 66 (RLXH) are formed in the peripheral 
area 87. The size and positioning of the signal generator 66 is shown only 
schematically. The drive/boot signal generator 66 has an output connected 
to a drive/boot signal generator line 68 that runs down the middle of the 
array area 83. The row factor signal generator (not shown) has a plurality 
of row factor signal lines (not shown) that also run down the middle of 
the array area 83 so as to be substantially parallel to the drive/boot 
signal line 68. 
The array area 83 contains a plurality of DRAM memory cell arrays 89 that 
are arranged in rows and columns. In the embodiment illustrated, there are 
thirty-two arrays 89 arranged in sixteen rows and two columns, each array 
having 128K memory cells. Only the first five and the last four of the 
rows are shown, the remaining seven middle rows being similar in 
construction and indicated by dashed continuation lines. The arrays 89 are 
spaced from each other in a vertical or columnar direction by respective 
ones of a plurality of sense amplifiers 90 and in a row or horizontal 
direction by a vertical space indicated generally at 91. 
The vertical space 91 is in part occupied by a plurality of row decoder 
sections 92. The layout of the arrays 89, sense amplifiers 90 and row 
decoder banks 92 leaves a plurality of "holes" 93 that are used to lay out 
the local predecoders and row redundancy decoders described below. The 
drive/boot signal line 68 and the row factor signal lines (not shown) are 
preferably routed down the length of the chip within the vertical space 
91. 
Turning now to FIG. 5, a small detail of the layout shown in FIG. 4 is 
illustrated. The areas devoted to laying out cell arrays 89, sense 
amplifiers 90, decoder banks 92, local predecoders 70 and row redundancy 
decoders 72 are indicated by dashed lines. The row decoder banks 92 are 
preferably laid out to extend across the vertical space 91 from one cell 
array 89a in the right column to the opposite cell array 89b in the left 
column. In the illustrated embodiment, there are thirty-two row decoders 
74 in each row decoder bank 92, one such row decoder being indicated at 74 
surrounded by a dashed enclosure. Each row decoder 74 is operable to 
decode the drive/boot signal line RLXH onto two of eight word or row 
lines, four of the row lines being disposed in the cell array 89a and the 
other four row lines being disposed in the cell array 89b. Two of these 
word lines are shown at 82a, 82b. 
A local predecoder 70 is preferably laid out to be adjacent a respective 
decoder bank 92. Local predecoders 70 are laid out to use at least some of 
the space provided by "holes" 93. Each decoder bank 92 is further provided 
with a row redundancy decoder 72 that is preferably disposed in an area 
adjacent to a respective local predecoder 70 within a "hole" 93. 
The drive/boot signal (RLXH) generator line 68 is constituted by a 
relatively wide conductor strap in second metal to minimize resistance and 
preferably runs down the middle of the vertical space 91. RLXH line 68 is 
connected to each local row redundancy decoder 72 and each local 
predecoder 70 along the length of the chip, as shown schematically by the 
connection dots on line 68. 
Each of twenty row factor signal lines run generally in parallel with RLXH 
line 68 (not shown) are connected to each row redundancy decoder 72, but 
only selected ones of these row factor signal lines are connected to any 
one of the local predecoders 70 and the decoders 74. The row factor signal 
lines are connected to a particular local predecoder 70 or to a particular 
decoder 74 according to a decoding scheme described more particularly in 
conjunction with FIGS. 6 and 7. 
A plurality of local predecoder lines 94 originate within the local 
predecoder 70 and are disposed generally in parallel with the RLXH signal 
line 68. Each pair of lines 94 illustrated in FIG. 5 is actually one node, 
as shown in FIG. 6. One line of the pair is on the left hand side of the 
RLXH line 68, while the other line of the pair is on the right side. The 
local predecoder lines 94 are preferably formed in second metal where they 
are parallel to the row factor lines (not shown), and in first metal when 
they run perpendicular thereto (not shown in this schematic 
representation). Each local predecoder line 94 per bank 92 intersects and 
is connected with each decoder 74 in a respective decoder bank 92. In the 
illustrated embodiment, there are four local predecoder output nodes 94 
per bank 92 and the signals carried thereon are termed RDD0, RDD1, RDD2 
and RDD3 (see FIGS. 3, 6 and 7), with each of these signals being carried 
on two of the eight lines per bank 92. 
In the illustrated embodiment, each row redundancy decoder 72 is 
programmable to decode the drive/boot signal RLXH onto a selected two of 
four redundant row lines 95a, 95b, 96a and 96b. The redundant row lines 
95a, b and 96a, b connect to respective rows of memory cells (not shown). 
Four redundant row lines 95a, 95b and 96a, 96b are provided to replace up 
to two pairs of regular row lines 82a, 82b as needed. 
Turning now to FIG. 6, there is illustrated a detailed electrical schematic 
diagram of one of the local predecoders 70. A. plurality of selected row 
factor lines 97 are connected as inputs to the local predecoder circuit 
70. Row factor lines RF0-RF3 are connected to respective inputs of four 
NAND gates 98-101. Row factor signal lines RF0-RF3 are connected to each 
local predecoder circuit 70 on the chip. On the other hand, the identity 
of three other row factor signal input lines RFI, RFJ and RFK vary 
according to the particular local predecoder circuit 70 to which they are 
connected. According to one decoding scheme, seven row factor signal lines 
97 make connection to the inputs of any one local predecoder 70 while the 
remaining thirteen do not. 
A precharge signal RDPC is connected to a gate 102 of a P-channel 
transistor 103. The current path of transistor 103 selectively connects a 
voltage supply source such as V.sub.dd to a node 104. The current path of 
another P-channel transistor 105 is also operable to connect V.sub.dd to 
the node 104. 
The drain of an N-channel transistor 106 is connected to the node 104, 
while a source thereof is connected to the drain of a further N-channel 
transistor 107. The source of the N-channel transistor 107 is connected to 
a node 108, which in turn is connected to the drains of two N-channel 
transistors 109 and 110. The sources of N-channel transistors 109 and 110 
are connected to ground or V.sub.ss. The row factor signal line RFK is 
connected to the gate of transistor 107. The gate of transistor 109 is 
connected to signal line RFI, while the gate of transistor 110 is 
connected to signal line RFJ. The gate of transistor 106 is connected to 
the row redundancy enable signal line RREN (86). 
Node 104 serves as the input to an inverter 111. The output of inverter 111 
is connected to a node 112, which in turn is connected back to the gate of 
the P-channel transistor 105. Node 112 is also connected to second inputs 
of NAND gates 98-101. 
The outputs of NAND gates 98-101 are connected to respective nodes 113, 
114, 115 and 116. Each node 113-116 is connected to an input of a 
respective inverter 117-120. The output of each inverter 117-120 is 
connected to the source of a respective large pass gate transistor 
121-124. Each of the pass gate transistors 121-124 has a gate thereof 
connected to V.sub.dd. 
The source of each pass gate transistor 121, 122, 123 and 124 is connected 
to the gate of a respective N-channel decoding transistor 125, 126, 127 or 
128. The sources of each of the transistors 125-128 are connected to the 
drive/boot signal line 68 (RLXH). The drains of transistors 125-128 are 
connected to respective nodes 129, 130, 131 and 132. Each node 129-132 is 
connected to the source of a respective grounding transistor 133, 134, 135 
or 136. The drains of the grounding transistors 133-136 are connected to 
ground or V.sub.ss. The gates of each transistor 133-136 are connected by 
respective lines 137-140 back to respective nodes 113-116. Each node 
129-132 is connected to a respective local predecoder output line 
RDD0-RDD3. 
Turning next to FIG. 7, a detailed schematic diagram of one decoder circuit 
74 is illustrated. Decoder circuit 74 is enabled by high states of three 
row factor signals appearing on the respective gates of enabling 
transistors 142, 144 and 146 in the center of FIG. 7. The RF line 97 
connected to the gate of transistor 142 is selected from one of lines RF4 
through RF7. Similarly, the RF signal line connected to the gate of 
transistor 144 is selected from RF8 through RF11, and the row factor 
signal line 97 that is connected to the gate of transistor 146 is selected 
from RF12 through RF15. The selection as to which of these lines is 
connected to the particular decoder circuit 36 varies according to the 
identity of the particular decoder circuit 74 within the decoder section 
92 (FIG. 5). In this way, one out of the sixty-four decoders 74 within any 
two decoder sections 92 (FIG. 5) can be selected. 
A precharge signal line RDPC is connected to the gate of a P-channel 
transistor 148. The current path of transistor 148 is operable to connect 
a voltage supply V.sub.dd to a node 150. Node 150 is connected to the 
inputs of left and right inverters 152 and 154. The output of inverter 154 
is connected to a node 156, which is in turn connected back to the gate of 
a P-channel transistor 158. The current path of transistor 158 connects a 
V.sub.dd voltage supply to node 150. Node 150 is connected through lines 
160 and 162 to a node 164, and i s further connected through lines 160 and 
166 to a node 168. Node 150 is selectively connected through the current 
paths of selecting transistors 142, 144 and 146 to V.sub.ss or ground. 
Right inverter output node 156 is connected to the sources of each of four 
pass transistors 170, 172, 174 and 176. The drains of transistors 170-176 
are in turn respectively connected to lines 178, 180, 182 and 184. Lines 
178-184 are connected to the gates of respective self-booting decoding 
transistors 186, 188, 190 and 192. 
Node 164 is connected to the gate of each of four row line grounding 
transistors 194, 196, 198 and 200. Grounding transistors 194-200 are 
operable to connect respective word line nodes 202, 204, 206 and 208 to 
ground. Each row line node 202-208 is connected to a respective right 
array row line ROWL0R, ROWL1R, ROWL2R or ROWL3R. 
The decoding circuitry for the left array is similar to that for the right 
array. An output node 210 of left inverter 152 is connected to the source 
of each of a plurality of pass gate transistors 212, 214, 216 and 218. The 
drain of each of the pass gate transistors 212-218 is connected to a gate 
of a respective self-booting decoding transistor 220, 222, 224 or 226. The 
current path of each decoding transistor 220-226 connects a respective 
local predecoder output line RDD0-RDD3 to a respective left array row line 
node 228, 230, 232 or 234. The left array row lines ROWL0L, ROWL1L, ROWL2L 
and ROWL3L are connected to the respective left array row line nodes 
228-234. 
Referring next to FIG. 8, a detailed electric schematic diagram of a 
redundant decoder 72 is shown. A pair of control signals TLRC and RDPC 
operate the gates of respective P-channel transistors 250 and 252. 
Transistors 250 and 252 coact to connect a voltage supply source V.sub.dd 
to a trial node 254. Another pair of transistors 256 and 258 are operated 
by control signals RDPC and RFZ to precharge the signal node 254 through 
an alternate route. The node 254 is also connected to a plurality of fuses 
260-286 that are each programmable to isolate respective addressing 
transistors 288-314 from the node 254. Fuses 260-286 can be replaced with 
any other suitable programmable or selectable isolation device such as a 
switch. Each current path of respective transistors 288-314 is operable to 
connect the node 254 to ground if its respective fuse is intact. The gates 
of addressing transistors 288-310 are actuated by high states on 
respective addressing lines RF0-RF11. The gates of addressing transistors 
312 through 324 are actuated by high states on respective addressing lines 
RFI, RFJ, RFK, RFL, RFW, RFX and RFY. RFI-RFZ vary according to the 
placement of the particular redundant decoder 72 on the chip. 
A second addressing transistor bank is indicated generally at 326. Bank 326 
includes a trial node 328 that is precharged through either the 
combination of series-connected P-channel precharge transistors 330 and 
332, or series-connected P-channel transistor 334 and an N-channel 
transistor 336. The node 328 is connected to the ends of a plurality of 
programmable fuses 338-364, which in turn are connected to the drains of 
respective N-channel addressing transistors 366-392. An additional five 
N-channel addressing transistors 394-402 are also connected to node 328, 
as transistors 316-324 connect to node 254 in the first bank 248. 
The node 254 is connected to an inverter 404, which in turn has an output 
connected to a node 406. The node 406 is connected back to the gate of a 
P-channel transistor 408 whose current path connects V.sub.dd back to the 
node 254. The combination of the inverter 404 and the P-channel transistor 
408 therefore coact to latch a low state at node 406. 
The node 406 is also connected to the input of an inverter 410, whose 
output is connected to the current path of an N-channel pass transistor 
412. The source of the pass transistor 412 is connected to a gate 414 of a 
self-booted redundant decoding transistor 416. The drain of transistor 416 
is connected to the drive/boot signal line 68 (RLXH). The source of the 
decoding transistor 416 is connected to a node 418, in turn connected to a 
redundant row line RRWL0 (95). 
Node 406 is also connected to the gate of an N-channel pull-down transistor 
420, which has a current path operable to connect the redundant row line 
node 418 to ground. 
Node 254 is also an input to a NOR gate 424. The other input of NOR gate 
424 is the trial node 328 of the addressing transistor bank 326. The 
output of NOR gate 424 is the row redundancy line 86 (RREN). The signal 
RREN is used as one input to a NAND gate 426, whose other input is a 
control signal RCC. The output of NAND gate 426 is input into a NAND gate 
428. The second input of the NAND gate 428 is a control signal 432. The 
output 430 of NAND gate 428 is connected to a NAND gate in the next row 
redundancy decoder 72 that corresponds to NAND gate 426, thus effectively 
NANDING the RREN signals together to implement a design for test mode 
(DFT) known as row redundancy roll call. 
In the second addressing transistor bank 326, the trial node 328 is 
connected as an input into an inverter 434. The inverter 434 has an output 
connected to a node 436, which in turn is connected to the gate of 
P-channel transistor 438. Node 436 is further connected to the input of an 
inverter 440, which has an output connected to the drain of an N-channel 
pass transistor 442. The source of the transistor 442 is connected to the 
gate 444 of a second self-booted redundant decoding transistor 446. The 
drain of transistor 446 is connected to the signal line RLXH (68), while 
its source is connected to a redundant row line node 448. A pulldown 
transistor 450 is operable to pull the redundant row line node 448 down to 
ground, which is operated by the state present at node 436. 
Referring back to FIG. 6, the normal, that is, non-redundant, operation of 
the local predecoder 70 is as follows. In its normal active-cycle state, 
the signal RREN is high at node 86. If the particular local predecoder 
shown is selected through high states on a combination of RFK and one of 
RFI and RFJ, node 104 will be pulled to ground. A low state of node 104 is 
inverted to a high state at node 112, which in turn enables each of the 
NAND gates 98-101. This allows a high state on any one of the row factor 
signals RF0-RF3 to cause the output of a low state on one of the nodes 
113-116. 
Assume that RF1 has a high state on it, while RF0, RF2 and RF3 have low 
states. In this instance, the low state at node 114 is inverted by the 
inverter 118 and passed through the pass gate transistor 122 to appear as 
a high state on the gate of the predecoding transistor 126. This in turn 
connects the drive/boot signal line RLXH to the local predecoder line 
RDD1. Since node 114 is low, the pulldown transistor 134 will be off. In 
the case of RDD0, RDD2 and RDD3, the states of nodes 113, 115 and 116 are 
high, and therefore the pulldown transistors 133, 135 and 136 are actuated 
to keep the other local predecoder lines RDD0, RDD2 and RDD3 at ground. 
Referring again to FIG. 7, and continuing the example that RDD1 is selected 
to go high, a particular decoder 74 is selected by having high states on 
each of the transistors 142, 144 and 146. This will cause a low state to 
appear on node 150, equivalent to a low state at nodes 164 and 168. The 
pulldown transistors 194, 196, 198, 200 and 240-246 will be disabled. 
Meanwhile, the low state at node 150 is inverted through inverters 152 and 
154 to high states at nodes 156 and 210. These high states are passed 
through the pass gate transistors 170-176 and 212-218 to actuate 
transistors 186-200 and 220-226. Since in particular transistors 188 and 
222 are turned on, a high state on RDD1 will be passed to row line ROWL1R 
and ROWL1L. 
Suppose however that the row line consisting of ROWL1R and ROWLIL in a 
particular cell array is discovered to be defective. Referring to FIG. 8, 
fuse 262 will be blown by a programmer, as will three other fuses, such as 
fuse 272, 282 and 286, that depend on the set identity of the addressing 
signals RFn that in combination would normally address ROWL1R and ROWLIL. 
This example assumes that the address of ROWL1R as shown in FIG. 6 
corresponds to high states on RF1, RF6, RF11 and RFJ. During the cycle, 
this particular combination of addressing signals will be sent into the 
array from the peripheral area 87 (FIG. 4) to connect to transistors 290, 
300, 310 and 314, as well as NAND gate 99 (FIG. 6) and transistors 142, 
144 and 146 (FIG. 7). However, the trial node 254 will not be drawn down 
to ground, as would have been the case for a nondefective row line, but 
will instead remain at near V.sub.dd. This is because blown fuse 262, 272, 
282 and 286 have isolated the current paths of all of the addressed 
transistors 290, 300, 310 and 314. The high state on node 254 is inverted 
to a low state 406 which in turn latches a high state at node 254 by the 
action of transistor 408. The lwo state at node 406 disables the pull-down 
transistor 420, and is also inverted through the inverter 410 and passed 
by the pass gate transistor 412 to actuate the gate 414 of the N-channel 
decoding transistor 416. This allows the drive/boot signal RLXH to be 
communicated to the redundant row line RRWL0 (95). 
At the same time, a high state at node 254 is NORed by the gate 424 to 
output a low state on the RREN line 86. Returning now to FIG. 6, a low 
state on RREN disables the transistor 106, causing a high state to stay on 
node 104. The high state on node 104 is inverted to a low state on node 
112, which disables each of the NAND gates 98-101. Therefore, the decoding 
transistor 126 will be disabled, and the RLXH signal will not be 
transmitted to the line RDD1, which in turn would be passed to the 
defective word line by the defective row decoder. Instead, this defective 
word line will be kept low by the actuation of the pull-down transistor 
134 by a high state at node 114 and by its active row decoder. A low state 
at node 112 also disables the transistors 125, 127 and 128; but since the 
low state at 112 will not exist when these other lines are addressed, or 
even where other word lines which are to be driven high by RDD1 are 
addressed, only the defective row line consisting of ROWLIR and ROWLIL is 
deselected. 
In summary, a novel redundant row line decoding scheme has been described 
and illustrated that disables a local predecoder. Fuses for every row line 
or row decoder are avoided, as are the inefficient replacement of good row 
lines with redundant row lines. Further, no separate drive/boot signal 
generator is required to implement redundancy. 
While a preferred embodiment of the invention and its advantages have been 
described in the above detailed description, the invention is not limited 
thereto, but only by the spirit and scope of the appended claims.