Image pickup device, image pickup system, driving method for image pickup device, and driving method for image pickup system

In an image pickup device, in a period for which a signal value of the comparison result signal is changed in a certain AD converter among a plurality of AD converters, the signal value of the comparison result signal changes a plurality of times in another AD converter.

BACKGROUND OF THE INVENTION

Field of the Invention

The present invention relates to an image pickup device, an image pickup system, a driving method for an image pickup device, and a driving method for an image pickup system.

Description of the Related Art

As an image pickup device including an AD converter for each column (an AD converter provided for each column is hereinafter referred to as a column ADC) in a CMOS image sensor (may also referred to as a CMOS sensor) used in a recent digital camera, an image pickup device disclosed in Japanese Patent Application Laid-Open No. 2012-004727 has been known.

In the image pickup device according to Japanese Patent Application Laid-Open No. 2012-004727, the column ADCs average the results of sampling the reset level signals of the pixels a plurality of times. Thus, the image pickup device according to Japanese Patent Application Laid-Open No. 2012-004727 outputs the signal in which the lower random noise caused in the pixels and the column ADCs is reduced.

However, in the image pickup device according to Japanese Patent Application Laid-Open No. 2012-004727, an analog signal is subjected to the AD conversion a plurality of times for reducing the random noise; therefore, the AD conversion time has been long.

SUMMARY OF THE INVENTION

According to an aspect of the present invention, an image pickup device includes: a plurality of pixels arranged in a plurality of columns and each outputting a signal based on incident light; a plurality of AD converters each disposed in accordance with each column of the pixels and generating a digital signal based on the signal output from the pixel; and a control unit having a ramp signal output unit that outputs a ramp signal whose potential changes depending on time to the plurality of AD converters, wherein: each of the plurality of AD converters has a comparator that generates a comparison result signal by comparing the ramp signal and a signal output from the pixel; and in a period for which a signal value of the comparison result signal is changed by comparing the ramp signal and the signal output from the pixel in a certain AD converter among the plurality of AD converters, the signal value of the comparison result signal changes a plurality of times by comparing the ramp signal and the signal output from the pixel in another AD converter.

Another aspect of the present invention is an image pickup system including an image pickup device including: a plurality of pixels arranged in a plurality of columns and each outputting a signal based on incident light; a plurality of AD converters each disposed in accordance with each column of the pixels and generating a digital signal based on the signal output from the pixel; and a control unit having a ramp signal output unit that outputs a ramp signal whose potential changes depending on time to the plurality of AD converters, wherein: each of the plurality of AD converters has a comparator that generates a comparison result signal by comparing the ramp signal and a signal output from the pixel, and a counter that generates a count signal obtained by counting a clock signal in a period for which the comparison is made; in a period for which a signal value of the comparison result signal is changed by comparing the ramp signal and the signal output from the pixel in a certain AD converter among the plurality of AD converters, the signal value of the comparison result signal changes a plurality of times by comparing the ramp signal and the signal output from the pixel in another AD converter; the counter of the other AD converter is a counter that integrates the count signal for every comparison; the image pickup device includes an output unit that outputs the count signal integrated by the counter of the other AD converter to a signal processing unit; and the image pickup system includes the signal processing unit that generates a signal obtained by dividing the count signal integrated by the counter of the other AD converter by the number of times of changes of the signal value of the comparison result signal of the other AD converter.

Another aspect of the present invention is a driving method for an image pickup device including: a plurality of pixels arranged in a plurality of columns and each outputting a signal based on incident light; and a plurality of AD converters each disposed in accordance with each column of the pixels and generating a digital signal based on the signal output from the pixel, wherein: each of the plurality of AD converters includes a comparator that generates a comparison result signal based on comparison between a ramp signal whose potential changes depending on time and a signal output from the pixel; and in a period for which a signal value of the comparison result signal is changed by comparing the ramp signal and the signal output from the pixel in a certain AD converter among the plurality of AD converters, the signal value of the comparison result signal changes a plurality of times by comparing the ramp signal and the signal output from the pixel in another AD converter.

Yet another aspect of the present invention is a driving method for an image pickup system including an image pickup device including: a plurality of pixels arranged in a plurality of columns and each outputting a signal based on incident light; and a plurality of AD converters each disposed in accordance with each column of the pixels and generating a digital signal based on the signal output from the pixel, wherein: each of the plurality of AD converters has a comparator that generates a comparison result signal based on comparison between a ramp signal whose potential changes depending on time and signals output from the pixels, and a counter that generates a count signal obtained by counting a clock signal in a period for which the comparison is made; in a period for which a signal value of the comparison result signal is changed by comparing the ramp signal and the signal output from the pixel in a certain AD converter among the plurality of AD converters, the signal value of the comparison result signal changes a plurality of times by comparing the ramp signal and the signal output from the pixel in another AD converter; the counter of the other AD converter integrates the count signal every time the signal value of the comparison result signal of the other AD converter changes; and a signal is generated that is obtained by dividing the count signal integrated by the counter of the other AD converter by the number of times of changes of the signal value of the comparison result signal of the other AD converter.

DESCRIPTION OF THE EMBODIMENTS

Embodiments of an image pickup device are hereinafter described with reference to the drawings.

First Embodiment

FIG. 1is a diagram illustrating a structure of an image pickup device100of this embodiment. The image pickup device100includes a pixel portion101where pixels102outputting signals based on incident light are disposed in a plurality of columns and a plurality of rows, and a vertical scanning circuit104that selects and sequentially scans a pixel row for outputting signals. Moreover, the image pickup device100includes a vertical signal line103to which the signal is input from the pixel102selected by the vertical scanning circuit104, column circuits105that process the signals input from the vertical signal line103, and a column circuit control unit106that controls the column circuits. Furthermore, the image pickup device100includes a horizontal scanning circuit107that sequentially reads out the signals processed in the column circuits105by each column of the column circuits105. In addition, the image pickup device100includes a timing control unit108that controls the timing of operating the vertical scanning circuit104, the column circuit control unit106, and the horizontal scanning circuit107. Moreover, the image pickup device100includes an output unit110.

The column circuit control unit106outputs a ramp signal Vramp, a reference voltage Vref, and a clock signal CLK to each of the column circuits105. The column circuit control unit106outputs a signal clmp, a signal clmp_1st, a signal PU/D, and a signal rst_colm to each of the column circuits105. The column circuit control unit106of this embodiment corresponds to a ramp signal output unit that outputs the ramp signal Vramp.

FIG. 2Ais a diagram illustrating a structure of the pixel102. The pixel102includes a photodiode201that converts the incident light into a charge, a floating diffusion capacitor202that holds the charge, and a transistor203that outputs a signal based on the charge of the floating diffusion capacitor202. The pixel102further includes a transistor204that switches the supply and the non-supply of a power source voltage VDD to the transistor203, and a transistor205that transfers the charge of the photodiode201to the floating diffusion capacitor202. The pixel102moreover includes a transistor206that resets the charge of the floating diffusion capacitor202. To the transistor204, the transistor205, and the transistor206, a signal SEL, a signal TX, and a signal RES are respectively input sequentially from the vertical scanning circuit104. The signal output from the transistor203to the vertical signal line103through the transistor204is expressed as a signal Vpix.

FIG. 2Bis a timing chart of the operation of the pixel102. In the pixel102, a signal RES and a signal TX at a high level (hereinafter referred to as an H level) are input from the vertical scanning circuit104to the transistor206and the transistor205, respectively in a period T1. This turns on the transistor206and the transistor205, whereby the photodiode201and the floating diffusion capacitor202are reset to the potential based on the power source voltage VDD. After that, the signal SEL at the H level is input to the transistor204from the vertical scanning circuit104in a period T2, thereby turning on the transistor204. Thus, the signal Vpix becomes the reset level signal (hereinafter referred to as an N signal). Subsequently, in a period T3, the signal TX at the H level is input from the vertical scanning circuit104to the transistor205, thereby turning on the transistor205. Then, the charges accumulated in the photodiode201are transferred to the floating diffusion capacitor202. Thus, the transistor203outputs the signal based on the charges accumulated by the photodiode201and transferred to the floating diffusion capacitor202overlapping on the N signal. The signal Vpix output from the transistor203to the vertical signal line103through the transistor204on this occasion is expressed as the S signal.

FIG. 3is a diagram illustrating a structure of the column circuit105. The column circuit105includes an amplifier301, a comparator302, and a counter303. The column circuit105further includes a switch Sw1, a switch Sw2, a switch Sw3, a flipflop circuit FF1, an AND circuit AG1, an OR circuit OG1, and a clamp capacitor Cclmp. InFIG. 3, the signal input from the column circuit control unit106to the column circuit105is denoted by the same reference symbol as that ofFIG. 1. To the comparator302, the ramp signal Vramp is input through the clamp capacitor Cclmp. The ramp signal input to the comparator302is expressed as the ramp signal Vcomp. The amplifier301outputs the signal Vpix_amp obtained by amplifying the signal Vpix to the comparator302. The comparator302outputs a comparison result signal CMP representing the result of comparing the ramp signal Vcomp and the signal Vpix_amp to the switch Sw1, the switch Sw2, the flipflop circuit FF1, and the counter303. An AD converter of this embodiment includes the comparator302, the counter303, the switch Sw1, the switch Sw2, the switch Sw3, the flipflop circuit FF1, the AND circuit AG1, the OR circuit OG1, and the clamp capacitor Cclmp. The counter303is switched in regard to whether a counted value is increased or decreased by the signal PU/D. The counter303counts based on the clock signal CLK while the L-level comparison result signal CMP is input to the input terminal of the counter303that is connected to the output terminal of the comparator302through the switch Sw1. On the contrary, the counter303does not count while the H-level comparison result signal CMP is input to the input terminal.

Since the S signal is generated based on the incident light in each pixel102, the signal level of the S signal output from the pixel102is changed depending on the light quantity. Therefore, in the column circuits105, the signal level of the amplified S signals may vary.FIG. 4illustrates the operation of the column circuit105in the case where the S signal of the pixel102with the small incident light quantity is input.FIG. 5illustrates the operation of the column circuit105in the case where the S signal of the pixel102with the large incident light quantity is input.

FIG. 4is a timing chart illustrating the operation of the column circuit105illustrated inFIG. 3. The reference symbols inFIG. 4correspond to those ofFIG. 3. The switch Sw1, the switch Sw2, and the switch Sw3inFIG. 4are on at the H level and off at the L level.

First, in the period T1 inFIG. 4, the H-level signal rst_colm is input to the column circuit105. This resets the counted value of the counter303to the initial value. At the same time, the switch Sw3is turned on through the OR circuit OG1and the potential of the node connected to the comparator302of the clamp capacitor Cclmp at the reference voltage Vref.

In the period T2 inFIG. 4, the pixel row is selected by the vertical scanning circuit104and the output of the signal Vpix_amp is changed. The pixel102outputs the N signal to the amplifier301through the vertical signal line103. The amplifier301outputs the signal obtained by amplifying the N signal. The signal Vpix_amp output from the amplifier301is expressed as the AMP_N signal.

In a period T3 inFIG. 4, the column circuit105performs the AD conversion on the AMP_N signal. The period T3 inFIG. 4starts at the timing when the comparator302starts to compare the ramp signal Vcomp and the AMP_N signal. In this period, the column circuit control unit106sets the signal PU/D to be output to the counter303at the low level (hereinafter referred to as the L level). Thus, the counter303counts down the clock signal CLK in a manner that the count signal value decreases from the initial value. This counting operation of the counter303is referred to as countdown. On the contrary, the operation of the counter303counting up the clock signal CLK in a manner that the count signal value increases from the initial value is referred to as countup. Upon the start of the change in potential of the ramp signal Vramp depending on the time, the potential of the ramp signal Vcomp also changes with the same inclination as the ramp signal Vramp. At the time when the ramp signal Vcomp starts to change in potential, the comparison result signal CMP output from the comparator302is at the L level. Since the output of the AND circuit AG1is at the L level, the switch SW1is on. Therefore, the L-level comparison result signal CMP is output to the counter303through the switch Sw1. The counter303performs the count operation while the comparison result signal CMP is at the L level.

In a period T4 inFIG. 4, the potential of the ramp signal Vcomp is higher than that of the AMP_N signal. Therefore, the comparison result signal CMP is at the H level. The timing when the signal value of the comparison result signal CMP changes from the L level to the H level is the timing when the comparator302finishes comparing between the ramp signal Vcomp and the AMP_N signal. Thus, the counter303stops to count and holds the count signal at this time. On this occasion, the count signal held by the counter303is the digital signal based on the AMP_N signal.

Subsequently, in a period T5 inFIG. 4, the pixel102performs the operation of the period T3 illustrated inFIG. 2B. Thus, the pixel102outputs the S signal to the amplifier301through the vertical signal line103. The column circuit control unit106returns the ramp signal Vramp to the initial value. Thus, the ramp signal Vcomp also returns to the initial value again. Accordingly, the comparison result signal CMP is at the L level. In the period T5 inFIG. 4, however, the clock signal CLK is not output; therefore, the count signal value of the counter303does not change. Moreover, the column circuit control unit106sets the signal PU/D to the H level in the period T5 inFIG. 4and changes the counting operation of the counter303to countup. The amplifier301outputs the signal obtained by amplifying the S signal to the comparator302. The signal obtained by amplifying the S signal and output by the amplifier301is expressed as the AMP_S signal.

From a period T6 inFIG. 4, the column circuit105performs the AD conversion on the AMP_S signal. The period T6 inFIG. 4starts at the timing when the comparator302starts to compare between the ramp signal Vcomp and the AMP_S signal. The comparator302outputs the L-level comparison result signal CMP to the counter303through the switch Sw1. The counter303counts up while the comparison result signal CMP is at the L level.

In a period T7 inFIG. 4, the potential of the ramp signal Vcomp is higher than that of the AMP_S signal. Therefore, the comparison result signal CMP is at the H level. The timing when the signal value of the comparison result signal CMP changes from the L level to the H level is the timing when the comparator302finishes comparing between the ramp signal Vcomp and the AMP_S signal. Thus, the counter303stops to count and holds the count signal at this time. The count signal held by the counter303at this time corresponds to the digital signal based on the AMP_S signal. The digital signal obtained from the first AD conversion of the AMP_S signal is expressed as the DS1 signal.

On the other hand, another column circuit105, which is different from the column circuit105operating according to the timing chart ofFIG. 4, may have the larger amplitude of the AMP_S signal than in the column circuit described with reference toFIG. 4. Therefore, in the other column circuit105, the comparison between the AMP_S signal and the ramp signal Vcomp is continued even after the period T7. Accordingly, the potential keeps changing depending on the time of the ramp signal Vramp output from the column circuit control unit106.

In the column circuit105operating according to the timing chart ofFIG. 4, the amplitude of the S signal is smaller than in the other columns; therefore, the generation of the digital signal based on the AMP_S signal ends before the other column circuits105. The column circuit105operating according to the timing chart ofFIG. 4performs the second AD conversion on the AMP_S signal while the other column circuits105performs the AD conversion on the AMP_S signal.

In a period T8 inFIG. 4, the column circuit control unit106sets the signal clmp_1stand the signal clmp at the H level. Thus, the signal value of the comparison result signal CMP when the signal clmp_1sttransits from the L level to the H level is stored in the flipflop circuit FF1and moreover the signal corresponding to the signal value of the comparison result signal CMP is output from the Q terminal. In this case, the flipflop circuit FF1outputs the H-level signal.

In the column circuit105operating according to the timing chart ofFIG. 4, the comparison result signal CMP becomes the H level before the signal clmp_1sttransits from the L level to the H level. Since the signal clmp and the signal input from the flipflop circuit FF1are both at the H level, the AND circuit AG1outputs the H-level signal. Thus, the switch Sw1is turned off and the switch Sw2that operates exclusively relative to the switch Sw1is turned on. Accordingly, the signal output from the Q terminal of the flipflop circuit FF1is input to the counter303instead of the comparison result signal CMP. Note that the signal output from the Q terminal of the flipflop circuit FF1is also input to the horizontal scanning circuit107. As described below, the signal of the flipflop circuit FF1input to the horizontal scanning circuit107is used for determining whether the output unit110calculates the count signal of the counter303.

Since the signal output from the AND circuit AG1is at the H level, the signal output from the OR circuit OG1is at the H level. Therefore, the switch Sw3is turned on. Accordingly, the ramp signal Vramp is clamped again at the reference voltage Vref. This makes the ramp signal Vcomp have a potential with the initial value. The clamp capacitor Cclmp is a ramp signal processing unit that shifts the potential of the ramp signal Vcomp from the potential of the ramp signal Vramp in the period T8 inFIG. 4to the potential at the start time of the period T3 at which the ramp signal Vramp starts to change in potential. By shifting the potential of the ramp signal Vcomp by the ramp signal processing unit, the comparison result signal CMP becomes the L level. However, as described above, the output of the flipflop circuit FF1is input to the counter303instead of the comparison result signal CMP. Thus, the countup of the counter303does not start at this time.

In a period T9 inFIG. 4, the column circuit control unit106sets the signal clmp at the L level. This sets the output of the AND circuit AG1at the L level to turn off the switch Sw3. Thus, the clamp operation of the ramp signal Vramp ends, whereby the potential of the ramp signal Vcomp changes depending on the time. At the same time, the switch Sw1is turned on and the switch Sw2is turned off. Thus, the count operation of the counter303begins to be controlled by the signal value of the comparison result signal CMP. Since the comparison result signal CMP is at the L level, the counter303performs the count operation. The signal PU/D is at the H level in this period; therefore, the counter303performs the countup. As a result, the AD conversion of the AMP_S signal is conducted again. Thus, the digital signal obtained by integrating the digital signal obtained in the second AD conversion of the AMP_S signal with respect to the DS1 signal can be acquired. This digital signal is referred to as a DS2 signal below. The DS2 signal is a signal obtained by integrating the count signal based on the AMP_S signal with the DS1 signal. A plurality of digital signals based on the AMP_S signal is collectively expressed by the DS signal.

The operation in a period T10 inFIG. 4is the same as the operation in the period T7 described above.

The operation in a period T11 inFIG. 4is the same as that in the period from T8 to T10 except that the signal clmp_1stremains at the L level. In the period T11, the signal clmp_1stremains at the L level but the output of the Q terminal of the flipflop circuit FF1maintains the state changed in the period T8. Thus, even though the column circuit control unit106maintains the signal clmp_1stat the L level, the column circuit105performs the same operation as the operation in the period from T8 to T10.

After that, every time the signal clmp transits from the L level to the H level, the column circuit105repeats the operation in the period from T8 to T10. The counter303integrates the count signal value every time.

Next, the operation of the column circuit105with larger amplitude of the S signal to be input than in the column circuit105operating according to the timing chart ofFIG. 4is described with reference toFIG. 5.

InFIG. 5, the operation in the period from T1 to T6 is the same as the operation in the period from T1 to T6 ofFIG. 4. However, since the amplitude of the S signal is larger than that of the column circuit105operating according to the timing chart ofFIG. 4, the comparison result signal CMP remains at the L level in the period from T7 to T9.

In the period T8 inFIG. 5, the column circuit control unit106outputs the signal clmp_1stand the signal clmp at the H level to the column circuit105in a manner similar to the operation in the period T8 inFIG. 4. Thus, the flipflop circuit FF1stores the signal value of the comparison result signal CMP when the signal clmp_1sttransits from the L level to the H level and the Q terminal outputs the signal corresponding to the signal value of the comparison result signal CMP. In this case, the flipflop circuit FF1outputs the L-level signal.

Since the output of the flipflop circuit FF1is at the L level, the AND circuit AG1keeps outputting the L-level signal. Therefore, the switch Sw1maintains to be in the on state and the switch Sw2operating exclusively relative to the switch Sw1maintains to be in the off state. Accordingly, the comparison result signal CMP is input to the counter303subsequently. Thus, the counter303continues the countup. The AND circuit AG1outputs the signal to the switch Sw3through the OR logic gate; however, since the output of the flipflop circuit FF1and the signal rst_colm are at the L level, the switch Sw3maintains to be in the off state. Thus, the potential of the ramp signal Vcomp keeps changing depending on the time.

In the period T10 inFIG. 5, the ramp signal Vcomp outweighs the AMP_S signal. Therefore, the comparison result signal CMP is set at the H level and the counter303therefore stops to count up and holds the counted value at this time. On this occasion, the signal value of the count signal held by the counter303at this time is the digital signal based on the difference between the AMP_S signal and the AMP_N signal, i.e., the digital signal based on the signal in which the component of the N signal included in the S signal and the offset component of the column circuit105are reduced.

In the period T11 inFIG. 5, the column circuit control unit106sets the signal clmp at the H level again; however, the output of the flipflop circuit FF1maintains the state stored in the period T8. Therefore, even though the signal value of the comparison result signal CMP has changed after the period T9, the column circuit105operating according to the timing chart ofFIG. 5does not conduct the multiple AD conversions on the AMP_S signal.

After that, the digital signals are sequentially output from the counter303in each column by the horizontal scanning circuit107.

On this occasion, in regard to the column circuit105in which the output of the flipflop circuit FF1is at the H level, the digital signal is divided by the number of times n of the integration. This produces the average value of a plurality of DS signals. As a result, the random noise of the column circuit105is reduced to 1/√n, whereby the image quality can be improved. Here, when the number of times of integration is set to the m-th power of 2, the division can be made by shifting the signal of each bit lower by m bits; thus, the circuit of the signal processing can be simplified.

Since the digital signal of the column circuit105in which the output of the flipflop circuit FF1is at the L level is not subjected to the plurality of AD conversions, the output unit110outputs the digital signal out of the image pickup device100without dividing the digital signal.

In the image pickup device of this embodiment, the effect of reducing the random noise can be achieved more as the AD conversion is repeated for the AMP_S signal.

The image pickup device of this embodiment includes the column circuit105that performs the AD conversion on one analog signal a plurality of times based on the incident light in the period where the potential of the ramp signal Vramp is changed depending on the time. From another point of view, in the image pickup device of this embodiment, while the comparator302of a certain column circuit105makes the comparison, the comparator302of another column circuit105compares the same analog signal a plurality of times based on the incident light. Thus, the image pickup device of this embodiment can provide a signal with the random noise reduced while suppressing the extension of the AD conversion period.

Note that the timing at which the column circuit control unit106transits the level of the signal clmp_1stfrom the L level to the H level is decided based on the level of the S signal where the optical shot noise becomes dominant as compared to the readout noise of the column circuit105.

In this embodiment, the ramp signal Vramp generated in the column circuit control unit106is output to each column in common; on the other hand, the ramp signal Vcomp that is different for each column circuit105is input by the operation of the switch Sw3. This can reduce the number of transmission lines of the ramp signal Vramp as compared to the structure in which the ramp signal Vramp is output individually for each column. Accordingly, the deterioration in AD conversion accuracy due to the variation in resistance and capacitance between the transmission lines of the ramp signal can be suppressed. Moreover, the circuit area for the column circuit control unit106and the column circuit105can be reduced and the yield can be improved in the image pickup device.

Here, the example has been described in which the output unit110averages the plurality of DS signals. As another example, the signals may be averaged using a signal processing circuit provided outside the image pickup device. Alternatively, after the digital signal for each column is output to the outside of the image pickup device, the output of the flipflop circuit FF1of each column may be output to the outside of the image pickup device.

Second Embodiment

An image pickup device of this embodiment is described mainly on the different point from the device of the first embodiment.

A structure of the image pickup device of this embodiment is the same as that ofFIG. 1except that the signal line outputting the signal clmp_1stto the column circuit105is omitted from the column circuit control unit106.

FIG. 6illustrates a structure of the column circuit105of this embodiment. InFIG. 6, the member with the same function as that ofFIG. 3is denoted by the same reference symbol as that ofFIG. 3.

As compared to the structure ofFIG. 3, the column circuit105ofFIG. 6is different in that the CK of the flipflop circuit FF1is connected to the transmission line that transmits the signal clmp and that the column circuit105further includes a counter701and a Buf counter702.

The counter701is a third counter that counts the number of times of integrating the digital signals based on the AMP_S signal.

The column circuit control unit106outputs the signal rst_colm common to the counter303to the counter701. Therefore, the count signals are reset at the same time in the counter303and in the counter701. The clock line of the countup of the counter701is connected to the node common to the D terminal of the flipflop circuit FF1. Therefore, every time the output of the comparison result signal CMP is changed, the count signal of the counter701is increased by one.

The Buf counter702counts up from 0, the initial value, every time the AD conversion based on the same incident light is repeated n times (n is an integer of 2 or more). The n-th AD conversion may not finish at the timing when the change in potential of the ramp signal Vramp depending on the time ends. In this case, the process is performed that returns the count signal, where the count operation has advanced to the middle of the n-th AD conversion, to the signal value of the count signal obtained in the (n−1)-th AD conversion. Specifically, the count signal of only the n-th conversion held by the Buf counter702is subtracted from the count signal obtained by integrating the signals from the conversions up to the middle of the n-th conversion held by the Buf counter303. Therefore, the image pickup device of this embodiment has the Buf counter702that holds the count signal obtained by the column circuit105in the n-th AD conversion only. In other words, the Buf counter702is the second counter that counts the next comparison clock signal CLK after resetting the count signal generated from the previous comparison.

The Buf counter702resets the count signal to the initial value when the comparison result signal CMP is set to the H level.

FIG. 7is a diagram for describing the operation of the image pickup device of this embodiment.FIG. 7illustrates the operation of the column circuit105that compares the analog signals based on the same incident light a plurality of times in a period from when the potential of the ramp signal Vramp starts to change depending on the time to when the change ends.

The operation inFIG. 7is different from that inFIG. 4in that the signal clmp_1stis omitted and the operations of the counter701and the Buf counter702are added.

The flipflop circuit FF1stores the signal value of the comparison result signal CMP every time the level of the signal clmp transits from the L level to the H level. However, in the operation ofFIG. 7, the comparison result signal CMP is at the H level at the timing where the level of the signal clmp transits from the L level to the H level. Therefore, the operation inFIG. 7is the same as that inFIG. 4except the operations of the additional components, the counter701and the Buf counter702.

The counter701increases the signal value of the count signal by one when the comparison result signal CMP is set to the H level. The Buf counter702resets the count signal when the comparison result signal CMP is set to the H level. The counter701starts to count up at the same time as when the counter303starts to count up.

FIG. 8is a timing chart illustrating the operation of the column circuit105with the larger amplitude of the S signal than in the column circuit105operating according toFIG. 7.

The column circuit control unit106sets the signal clmp at the H level in the period T8 and at this time, the comparison result signal CMP remains at the L level. Therefore, the output of the AND circuit AG1remains at the L level and the on/off state of the switch Sw1, the switch Sw2, and the switch Sw3do not change either. Thus, the potential of the ramp signal Vcomp keep changing depending on the time and the counter303continues to count up. This state similarly applies to the period T9.

In the operation inFIG. 8, the counter701increases the signal value of the count signal by one when the comparison result signal CMP is set to the H level. The Buf counter702resets the count signal when the comparison result signal CMP is set to the H level. The counter701starts to count up at the same time as the start of the countup of the counter303.

Here, description is made of the case in which the column circuit control unit106ends the change in potential of the ramp signal Vramp depending on the time in a period T14. The column circuit control unit106stops the output of the clock signal CLK at the same time as the end of the change in potential of the ramp signal Vramp depending on the time. At this time, the countup of the counter303and the Buf counter702stops in the column circuits105in which the comparison result signal CMP remains at the L level in the n-th AD conversion, and the count signal at this time is held in each. On this occasion, the counted value of the counter303holds the count signal obtained by integrating the count signals until the period T13 and the count signal in the middle of the n-th AD conversion. On the other hand, the Buf counter702holds the count signal in the middle of the n-th AD conversion. The horizontal scanning circuit107reads out the count signal held by the counter303and the count signal held by the Buf counter702. The output unit110generates the differential signal obtained by subtracting the count signal held by the Buf counter702from the count signal held by the counter303. In addition, the horizontal scanning circuit107reads out the count signal held by the counter701. Then, the output unit110divides the generated differential signal by the signal value of the count signal held by the counter701. Thus, even in the case where the n-th AD conversion ends on its way, the count signals obtained up to the (n−1)-th AD conversion can be averaged in the image pickup device of this embodiment.

In this manner, as compared to the image pickup device of the first embodiment, the image pickup device of this embodiment can deal with the case in which the AD conversion ends on its way. Thus, in the image pickup device of this embodiment, the degree of freedom in setting the number of times of performing the AD conversion on the analog signal based on the same incident light can be improved.

Note that in this embodiment, the pixel102outputs the N signal before the S signal; however, the order may be the opposite. In this case, the number of times of performing the AD conversion on the N signal may be set based on the number of times of performing the AD conversion on the S signal. In this case, the random noise included in the digital signal based on the N signal can be reduced by averaging the plurality of digital signals based on the N signal.

In this embodiment, the output unit110obtains the difference between the count signals of the counter701and the Buf counter702, and divides the difference by the count signal value of the counter701. In another example, a signal processing unit900provided outside the image pickup device may perform this operation.FIG. 9, which illustrates this example, is a diagram of an image pickup system having the image pickup device100and the signal processing unit900. The output unit110outputs the count signals of the counter701, the Buf counter702, and the counter303in each column to the signal processing unit900. The signal processing unit900includes a subtracter901and a divider902. To the subtracter901, the count signals of the counter303and the count signal of the Buf counter702are input. The subtracter901generates a differential signal by subtracting the count signal of the Buf counter702from the count signal of the counter701. Then, the subtracter901outputs the differential signal to the divider902. The count signal of the counter701is further input to the divider902. The divider902divides the differential signal input from the subtracter901by the count signal of the counter701. Thus, the signal processing unit900can average the count signals obtained in the AD conversion up to the (n−1)-th time.

Third Embodiment

Description is made of the different point from the first embodiment.

In this embodiment, the column circuit control unit106outputs the ramp signal Vramp and a ramp signal Vramp2, whose amount of change in potential depending on time is different, to the column circuits105. The other structure of the image pickup device is the same as that ofFIG. 1.

FIG. 10illustrates the structure of the column circuit105of this embodiment. The ramp signal Vramp2is a ramp signal whose amount of change in potential per unit time is ½ of that of the ramp signal Vramp. Each of the column circuits105has a switch Sw4corresponding to a ramp signal selecting unit that selects one of the ramp signal Vramp and the ramp signal Vramp2as the ramp signal to be output to the clamp capacitor Cclmp. The switch Sw4is controlled by the output of the Q terminal of the flipflop circuit FF1. The switch Sw4outputs the ramp signal Vramp to the clamp capacitor Cclmp while the output of the Q terminal of the flipflop circuit FF1is at the L level. On the other hand, the switch Sw4outputs the ramp signal Vramp2to the clamp capacitor Cclmp while the output of the Q terminal of the flipflop circuit FF1is at the H level.

FIG. 11is a timing chart illustrating the operation of the image pickup device of this embodiment. Description is made of the different point from the timing chart ofFIG. 4.

The operation in the period from T1 to T7 inFIG. 11is the same as that in the period from T1 to T7 inFIG. 4.

When the output of the Q terminal of the flipflop circuit FF1has become the H level at the start of the period T8 inFIG. 11, the switch Sw4switches the signal to be output to the clamp capacitor Cclmp from the ramp signal Vramp to the ramp signal Vramp2. Thus, the amount of change in potential per unit time of the ramp signal Vcomp to be input to the comparator302in the period T9 is halved relative to the amount of change in potential per unit time of the ramp signal Vcomp in the period T6. By the use of the ramp signal Vramp2for the comparison in the period T9, the resolution of the digital signal based on the AMP_S signal that is obtained in the second or later AD conversion can be improved to be higher than the resolution of the digital signal obtained in the first AD conversion. In the image pickup device, the noise compositions of the pixel102and the column circuit105become larger relatively as the amount of incident light is decreased; therefore, the S/N ratio of the digital signal is deteriorated. In the image pickup device, however, the deterioration in S/N ratio of the digital signal can be suppressed by performing the AD conversion on the AMP_S signal based on the S signal of the low-luminance pixel102with the high resolution.

This embodiment has described the example in which the ramp signal Vramp2is used in the second or later AD conversion of the AMP_S signal based on the same incident light; however, in another example, the ramp signal Vramp and the ramp signal Vramp2may be switched and used as the ramp signal to be used in the second or later AD conversion in accordance with the amplitude of the AMP_S signal. For example, in the case of putting priority on the reduction of the random noise, the ramp signal Vramp may be used for increasing the number of times of the AD conversion as much as possible. In the case of putting priority to the higher S/N ratio at the low luminance, the ramp signal Vramp2may be used.

Fourth Embodiment

Description is made of an embodiment in which the image pickup device according to the first to third embodiments is applied to an image pickup system. The image pickup system corresponds to a digital still camera, digital camcorder, a surveillance camera, or the like.FIG. 12is a schematic diagram of the case in which the image pickup device is applied to the digital still camera as an example of the image pickup system.

InFIG. 12, the image pickup system includes a lens152for focusing an optical image of a subject on an image pickup device154, a barrier151for protecting the lens152, and a diaphragm153for varying the quantity of light transmitting through the lens152. The lens152and the diaphragm153correspond to an optical system that guides the light to the image pickup device154. The image pickup system further includes an output signal processing unit155processing an output signal to be output from the image pickup device154.

The output signal processing unit155includes a digital signal processing unit, and corrects or compresses a signal output from the image pickup device154as necessary and then outputs the signal. The output signal processing unit155herein referred to corresponds to the output signal processing unit of the image pickup system described in the first embodiment.

The image pickup system moreover includes a buffer memory unit156for storing image data temporarily, and a storage medium control interface unit158for recording the data in the recording medium or reading out the data from the recording medium. The image pickup system further includes a recording medium159that is detachable, such as a semiconductor memory, for recording the image data therein or reading out the data therefrom. In addition, the image pickup system includes an external interface unit157for communicating with an external computer or the like, an overall control/calculation unit1510for performing various calculations and controlling the entire digital still camera, and the image pickup device154. The image pickup system includes a timing generation unit1511for outputting various timing signals to the output signal processing unit155. The timing signals and the like may be input from the outside, and the image pickup system may include at least the image pickup device154, and the output signal processing unit155that processes the output signal output from the image pickup device154. In the case of the image pickup device illustrated inFIG. 4, the output signal processing unit155can process a focus detection signal. Moreover, the output signal processing unit155can generate the image from the digital signal based on A+B signal.

As thus described, the image pickup system of this embodiment can perform the image pickup operation by applying the image pickup device154.

The output signal processing unit155may have the signal processing unit900described in the second embodiment.

Note that this specification has described the example in which the column circuit105has the amplifier301; however, the present invention is not limited to this example. In other words, the signal output from the pixel102may be input to the comparator302without being amplified.

In this specification, description has been made based on the case in which the column circuit control unit106generates the ramp signal whose potential changes in the slope-like shape; however, the present invention is not limited thereto. In another example, the column circuit control unit106may generate the ramp signal whose potential changes in a step-like shape. The ramp signal whose potential changes in a step-like shape is also the ramp signal whose potential changes over the time.

The above embodiment merely illustrates the specific example of the present invention, and the technical scope of the present invention is not limited thereby. In other words, various modifications can be made without departing from the technical thought and principal features of the present invention.

According to the present invention, the image pickup device in which the random noise included in the signal output from the image pickup device is reduced while the extension of the AD conversion period is suppressed can be provided.

This application claims the benefit of Japanese Patent Application No. 2013-248032, filed Nov. 29, 2013, which is hereby incorporated by reference herein in its entirety.