SEMICONDUCTOR PACKAGE WITH HYBRID MOLD LAYERS

According to various examples, a device is described. The device may include a first package substrate. The device may also include a first mold layer with a first thickness. The device may also include a second mold layer with a second thickness proximal to the first mold layer. The second thickness may be larger than the first thickness. The first mold layer may include a plurality of first interconnects coupled to the first package substrate. The second mold layer may include a plurality of second interconnects configured to couple the first package substrate to a printed circuit board.

BACKGROUND

Conventional semiconductor packages have stacked dynamic random access memory (DRAM) coupled to semiconductor package substrates to increase DRAM bandwidth density to meet next-generation computing system requirements. An increase in the numbers of DRAM devices on the central processing unit (CPU), graphic processing unit (GPU), System-On-Chip (SOC) packages and/or printed circuit board (PCB) may lead to form-factor (i.e., footprint) expansion through additional package and/or platform real-estate requirements, which may prohibit device miniaturization.

Existing solutions to solve the above-mentioned problems include real-estate expansion to house additional DRAM memory devices for performance scaling, DRAM package form-factor miniaturization, alternative memory architecture e.g., high-bandwidth memory (HBM) with advanced packaging solution e.g., 2.5D silicon bridge interconnects for memory bandwidth scaling.

However, these existing solutions may lead to form-factor expansion i.e., bulky devices, device reliability trade-off with reduced solder joint geometry, constrained silicon interposer real-estate for memory device scaling i.e. limited to 3D stacked integrated circuit architecture, electrical and/or mechanical challenges associated with the through silicon via (TSV) interconnects e.g., high-resistance electrical path, signal crosstalk, signal return and insertion losses.

DETAILED DESCRIPTION

The following detailed description refers to the accompanying drawings that show, by way of illustration, specific details and aspects in which the present disclosure may be practiced. These aspects are described in sufficient detail to enable those skilled in the art to practice the present disclosure. Various aspects are provided for the present devices, and various aspects are provided for the methods. It will be understood that the basic properties of the devices also hold for the methods and vice versa. Other aspects may be utilized and structural, and logical changes may be made without departing from the scope of the present disclosure. The various aspects are not necessarily mutually exclusive, as some aspects can be combined with one or more other aspects to form new aspects.

An advantage of the present disclosure may include device form-factor miniaturization through reduction of the total package and/or printed circuit board real-estate required e.g., overlapping sections between CPU/GPU/SOC package and the DRAM memory packages

An advantage of the present disclosure may include improved signal latency between CPU/GPU/SOC and DRAM memory devices through reduced channel interconnects length and/or impairments, thus allowing memory bin-speed scaling.

An advantage of the present disclosure may include improved power delivery network (PDN) and power integrity through smaller loop inductance by avoiding extensive power (Vcc) and ground (Vss) electrical paths through the CPU/GPU/SOC package substrate.

An advantage of the present disclosure may include increased device integration e.g., integration of RFIC devices adjacent to compute die(s) e.g., CPU/GPU/SOC for improved functionality and performance scaling.

These and other aforementioned advantages and features of the aspects herein disclosed will be apparent through reference to the following description and the accompanying drawings. Furthermore, it is to be understood that the features of the various aspects described herein are not mutually exclusive and can exist in various combinations and permutations.

The present disclosure generally relates to a device. The device may include a first package substrate. The device may also include a first mold layer with a first thickness. The device may also include a second mold layer with a second thickness proximal to the first mold layer. The second thickness may be larger than the first thickness. The first mold layer may include a plurality of first interconnects coupled to the first package substrate. The second mold layer may include a plurality of second interconnects configured to couple the first package substrate to a printed circuit board.

The present disclosure generally relates to a method of forming a device. The method may include providing a first package substrate. The method may include forming a first mold layer with a first thickness. The method may include forming a plurality of first interconnects of the first mold layer for coupling to the first package substrate. The method may include forming a second mold layer with a second thickness proximal to the first mold layer. The second thickness may be larger than the first thickness. The method may include forming a plurality of second interconnects of the second mold layer for coupling the first package substrate to a printed circuit board.

The present disclosure generally relates to a computing device. The computing device may include a printed circuit board. The computing device may include a device coupled to the printed circuit board. The device may include a first package substrate. The device may also include a first mold layer with a first thickness. The device may also include a second mold layer with a second thickness proximal to the first mold layer. The second thickness may be larger than the first thickness. The first mold layer may include a plurality of first interconnects coupled to the first package substrate. The second mold layer may include a plurality of second interconnects configured to couple the first package substrate to the printed circuit board.

To more readily understand and put into practical effect, the present device, computing device, method, and other particular aspects will now be described by way of examples and not limitations, and with reference to the figures. For the sake of brevity, duplicate descriptions of features and properties may be omitted.

FIG. 1Ashows a cross-sectional view of a semiconductor package according to an aspect of the present disclosure.FIG. 1Bshows a top view of the semiconductor package according to an aspect of the semiconductor package shown inFIG. 1A.

In an aspect of the present disclosure, a semiconductor package100is shown inFIGS. 1A and 1B. The semiconductor package100may be a device. The semiconductor package100may be a stacked semiconductor package like a 2.5D or a 3D semiconductor package.

In an aspect of the present disclosure, the semiconductor package100may include a first package substrate128and/or a second package substrate102.

In an aspect of the present disclosure, the semiconductor package100may include a package substrate102. The first package substrate128and/or the second package substrate102may include contact pads, electrical interconnects, routings, and other features, which are not shown in any of the present figures. The first package substrate128and/or the second package substrate102may have one or more rigid core layers for improved structural stability or a coreless substrate package for a reduced form factor.

In an aspect of the present disclosure, the semiconductor package100may include a plurality of solder balls104. The second package substrate102may be connected to a printed circuit board (i.e., a motherboard)101through the plurality of solder balls104. In an aspect, the plurality of solder balls104may provide an electrical connection between the second package substrate102, and the printed circuit board101.

In an aspect of the present disclosure, the semiconductor package100may include an interposer106. The interposer106may be an electrical routing interface between one connection and another. The purpose of the interposer106may be to redistribute a connection to a wider pitch or to reroute a connection to a different connection. The interposer106may be an active interposer (i.e., comprising one or more transceiver devices) or a passive interposer (i.e., without transceiver devices). The interposer108may be a silicon interposer, a ceramic interposer, or an organic interposer.

In an aspect of the present disclosure, the semiconductor package100may include a plurality of package bumps108disposed on the second package substrate102. In an aspect, the plurality of package bumps108may be controlled collapse chip connection (C4) bumps.

In an aspect of the present disclosure, an underfill layer (not shown) may be deposited to cover, and to protect the plurality of package bumps108in a conventional manner. The underfill layer may be provided to enhance the mechanical reliability of the plurality of package bumps108. The underfill layer may be provided using either a conventional underfilling process or a no-flow underfilling process to reduce the effects of thermal expansion and reduce the stress and strain on the plurality of package bumps108.

In an aspect of the present disclosure, the interposer106may be disposed on the second package substrate102. In an aspect, the interposer106may be connected to the second package substrate102through the plurality of package bumps108. The plurality of package bumps108may also provide an electrical connection between the interposer106, and the second package substrate102.

In an aspect of the present disclosure, the interposer106may include a plurality of through silicon vias (TSVs)110. In an aspect, the plurality of package bumps108may be disposed below the plurality of TSVs110. In an aspect, the plurality of package bumps108may provide an electrical connection between the plurality of TSVs110, and the second package substrate102.

In an aspect of the present disclosure, the semiconductor package100may include at least one semiconductor die112. In an aspect, the at least one semiconductor die112may be made from any suitable semiconductor, such as silicon or gallium arsenide. As used herein, the term semiconductor die112may also cover a chip or a set of chiplets, e.g., a system-on-chip (SOC), a platform controller hub (PCH)/chipset, a memory controller, a field programmable gate array (FPGA) device, a central processing unit (CPU), or a graphic processing unit (GPU).

In an aspect of the present disclosure, the at least one semiconductor die112may be disposed on the interposer106. In an aspect of the present disclosure, a plurality of solder bumps114may be disposed on the interposer106. The plurality of solder bumps114may be disposed on an interposer chiplet surface of the interposer106. The plurality of solder bumps114may provide an electrical connection between the plurality of TSVs110, and the at least one semiconductor die112. In an aspect, the plurality of TSVs110may be configured to facilitate signal transmission and/or power delivery between the second package substrate102, and the semiconductor die112.

In an aspect of the present disclosure, the at least one semiconductor die112may pass signals and/or power to another semiconductor die112through a redistribution layer (RDL)120on the interposer106. In an aspect, the RDL120may include a plurality of conductive traces interleaving with a plurality of dielectric layers. In further aspects, the RDL120is coupled to the plurality of TSVs110within the interposer106.

In an aspect of the present disclosure, the semiconductor package100may include hybrid mold layers. The hybrid mold layers may be at least two mold layers of different thicknesses.

In an aspect of the present disclosure, the semiconductor package100may include a first mold layer116. In an aspect, the first mold layer116may be or may include an epoxy polymer resin. A silica filler may be disposed within the first mold layer116. In an aspect, the first mold layer116may have a first thickness. The first thickness may be between 20 μm to 100 μm.

In an aspect of the present disclosure, the semiconductor package100may include a second mold layer118. In an aspect, the second mold layer118may have a second thickness. The second thickness may be between 200 μm to 700 μm. In an aspect, the second thickness is larger than the first thickness. In an aspect, the second mold layer118may be proximal to the first mold layer116, for example, adjacent to the first mold layer116. In an aspect, the first mold layer116and the second mold layer118may be touching each other, i.e., without a space between them or contiguous. In an aspect, the first mold layer116and the second mold layer118may form an integral portion.

In another aspect, there may be a space between the first mold layer116and the second mold layer118. An electrical device (e.g., RFIC) may be disposed in the space between the first mold layer116and the second mold layer118.

In an aspect of the present disclosure, the first mold layer116may include a plurality of first interconnects121. The plurality of first interconnects121may extend through the first thickness of the first mold layer116. The plurality of first interconnects121may have a first end coupled to the first package substrate128. The plurality of first interconnects121may have a second end coupled to the second package substrate102.

In an aspect, at least a portion of the first package substrate128may overlap the second package substrate102to form an overlapped region. In an aspect, the plurality of first interconnects121are configured to couple the first package substrate128to the second package substrate102in the overlapped region. In an aspect, the plurality of first interconnects121are configured for direct electrical connection to the second package substrate102i.e., a direct electrical connection between the first package substrate128and the second package substrate102through the plurality of first interconnects121.

In an aspect of the present disclosure, the second mold layer118may include a plurality of second interconnects122. The plurality of second interconnects122may extend through the second thickness of the second mold layer118. The plurality of second interconnects122may have a first end coupled to the first package substrate128. The plurality of second interconnects122may have a second end coupled to the printed circuit board101. In an aspect, the plurality of second interconnects122are configured for direct electrical connection to the printed circuit board101i.e., a direct electrical connection between the first package substrate128and the printed circuit board101through the plurality of second interconnects122.

In an aspect, the first interconnects121and the second interconnects122may be heterogeneous or hybrid interconnects.

In an aspect of the present disclosure, each first interconnect of the plurality of first interconnects121may have a first diameter and each second interconnect of the plurality of second interconnects122may have a second diameter larger than the first diameter. The first diameter may be between 20 μm to 100 μm. The second diameter may be between 200 μm to 500 μm.

In an aspect, the plurality of first interconnects121may include metal-plated vias e.g. copper-plated vias, solder-composites vias e.g., tin-silver composites vias or an array of metal pillars and/or pins. Each first interconnect of the plurality of first interconnects121may have a pitch geometry ranging in between 30 μm to 200 μm.

In an aspect, the plurality of second interconnects122may include metal-plated vias e.g. copper-plated vias, solder-composites vias or an array of metal pillars and/or pins. Each second interconnect of the plurality of second interconnects122may have a pitch geometry ranging in between 250 μm to 700 μm.

In an aspect of the present disclosure, the plurality of second interconnects122may have an electrical property e.g., metal conductivity, that may be different from the plurality of first interconnects121.

In an aspect of the present disclosure, the plurality of first interconnects121may be configured to facilitate signal transmission between the second package substrate102and the first package substrate128. For example, the plurality of first interconnects121may be configured to facilitate data signal transmissions such as electrical signal transmissions of double data-rate (DDR) memory (at 6.4 GT/s and/or beyond) and/or radio frequency (RF) signals (at 77 GHz and/or beyond).

In an aspect, the plurality of second interconnects122may be configured to facilitate power delivery and/or reference voltage from the printed circuit board101to the first package substrate128. For example, the plurality of second interconnects122may be configured to facilitate power delivery e.g., a power supply voltage (Vcc) and to facilitate reference voltage connection e.g., a ground reference voltage (Vss) for a signal current return path.

In an aspect of the present disclosure, a plurality of first solder bumps124may be disposed below the plurality of first interconnects121. In an aspect, the plurality of first solder bumps124may provide an electrical connection between the plurality of first interconnects121, and the second package substrate102.

In an aspect of the present disclosure, a plurality of second solder bumps126may be disposed below the plurality of second interconnects122. In an aspect, the plurality of second solder bumps126may provide an electrical connection between the plurality of second interconnects122, and the printed circuit board101.

In an aspect of the present disclosure, each first solder bump of the plurality of first solder bumps124has a first diameter and each second solder bump of the plurality of second solder bumps126has a second diameter larger than the first diameter. In an aspect, the plurality of solder balls104has a third diameter equivalent to the second diameter.

In an aspect of the present disclosure, at least one memory device130may be coupled to the first package substrate128. The at least one memory device130may be a DRAM. In an aspect, at least one memory device130may be coupled to the first interconnects121and the second interconnects122through a plurality of metal routing layers and vias.

In an aspect, the first package substrate128, the first mold layer116, the second mold layer118and the memory device130together form a first memory platform150, which is located at a first end of the second substrate102as shown inFIG. 1A. In another aspect, a second memory platform160, which a mirror image of the first memory platform150is located at a second end of the second substrate102opposite the first end of the second substrate102and the interposer106may be positioned between the first memory platform150and the second memory platform160.

In an aspect of the present disclosure, the at least one memory device130and/or the first package substrate128may communicate with the second package substrate102and/or at least one semiconductor die112through one or more routing traces170or embedded bridge132to facilitate higher interconnect density. In an aspect, the embedded bridges132or routing traces170may be in the second package substrate102. The plurality of first interconnects121may be electrically coupled to the embedded bridge132or the routing traces170. In an aspect, the first mold layer116may extend across a portion of the one or more embedded bridges132.

FIG. 2shows a flow chart illustrating a method of forming a semiconductor package according to an aspect of the present disclosure.

As shown inFIG. 2, there may be a method200of forming a device. In the method200, a first operation202may include providing a first package substrate. A second operation204may include forming a first mold layer with a first thickness. A third operation206may include forming a plurality of first interconnects in the first mold layer for coupling to the first package substrate. A fourth operation208may include forming a second mold layer with a second thickness proximal to the first mold layer. The second thickness may be larger than the first thickness. A fifth operation210may include forming a plurality of second interconnects in the second mold layer for coupling the first package substrate to a printed circuit board.

It will be understood that the above operations described above relating toFIG. 2are not limited to this particular order. Any suitable, modified order of operations may be used.

FIG. 3shows a cross-sectional view of a semiconductor package according to an aspect of the present disclosure.

In an aspect of the present disclosure, a semiconductor package300is shown inFIG. 3. The semiconductor package300may be a device. The semiconductor package300may be a stacked semiconductor package like a 2.5D or a 3D semiconductor package.

In an aspect of the present disclosure, the semiconductor package300may include a first package substrate328and/or a second package substrate302.

In an aspect of the present disclosure, the semiconductor package300may include a package substrate302. The first package substrate328and/or the second package substrate302may include contact pads, electrical interconnects, routings, and other features, which are not shown in any of the present figures. The first package substrate328and/or the second package substrate302may have one or more rigid core layers for improved structural stability or a coreless substrate package for a reduced form-factor. In other aspects, the first package substrate328and/or the second package substrate302may be part of a larger substrate that supports additional semiconductor packages, and/or components.

In an aspect of the present disclosure, the semiconductor package300may include a plurality of solder balls304. The second package substrate302may be connected to a printed circuit board (i.e., a motherboard)301through the plurality of solder balls304. In an aspect, the plurality of solder balls304may provide an electrical connection between the second package substrate302, and the printed circuit board.

In an aspect of the present disclosure, the semiconductor package300may include at least one semiconductor die312. In an aspect, the at least one semiconductor die312may be made from any suitable semiconductor, such as silicon or gallium arsenide. As used herein, the term semiconductor die312may also cover a chip or a set of chiplets, e.g., a system-on-chip (SOC), a platform controller hub (PCH)/chipset, a memory device, a field programmable gate array (FPGA) device, a central processing unit (CPU), or a graphic processing unit (GPU).

In an aspect of the present disclosure, the at least one semiconductor die312may be disposed on the second package substrate302. In an aspect, a plurality of solder bumps314may be disposed on the second package substrate302. The plurality of solder bumps314may be disposed on a surface of the second package substrate302. The plurality of solder bumps314may provide an electrical connection between the second package substrate302, and the at least one semiconductor die312. In an aspect, the plurality of solder bumps314may be configured to facilitate signal transmission and/or power delivery between the second package substrate302, and the semiconductor die312.

In an aspect of the present disclosure, the semiconductor package300may include hybrid mold layers. The hybrid mold layers may be at least two mold layers of different thicknesses.

In an aspect of the present disclosure, the semiconductor package300may include a first mold layer316. In an aspect, the first mold layer316may be or may include an epoxy polymer resin. A silica filler may be disposed within the first mold layer316. In an aspect, the first mold layer316may have a first thickness. The first thickness may be between 20 nm to 100 μm.

In an aspect of the present disclosure, the semiconductor package300may include a second mold layer318. In an aspect, the second mold layer318may have a second thickness. The second thickness may be between 200 nm to 700 μm. In an aspect, the second thickness is larger than the first thickness. In an aspect, the second mold layer318may be proximal to the first mold layer316. In another aspect, there may be a space between the first mold layer316and the second mold layer318.

In an aspect, an electrical device334(e.g., a silicon device such as a RFIC) may be disposed in the space between the first mold layer316and the second mold layer318. In an aspect, the electrical device334is electrically coupled on a first side to the first package substrate328and coupled on a second side to a heat spreader340. The heat spreader340may be disposed on the printed circuit board301. The heat spreader340may be a heat slug.

In an aspect, a plurality of electrical bumps336may be disposed on the first side of the electrical device334. The plurality of electrical bumps336may provide a connection between the first package substrate328, and the electrical device334.

In an aspect, a plurality of antennas338(e.g., phase array antennas (PAAs)) may be disposed on the first package substrate328. In an aspect, the plurality of antennas338may be for facilitating RF signal transmission and reception.

In an aspect, reduced signal latency and electrical losses between RFIC and the at least one semiconductor die312e.g., a central processing unit (CPU) or a system-on-chip (SOC) may be achieved through the first interconnects321. Improved channel impedance matching may be achieved through reduced interconnect geometry and undesired routing transitions.

In an aspect of the present disclosure, the first mold layer316may include a plurality of first interconnects321. The plurality of first interconnects321may extend through the first thickness of the first mold layer316. The plurality of first interconnects321may have a first end coupled to the first package substrate328. The plurality of first interconnects321may have a second end coupled to the second package substrate302.

In an aspect, at least a portion of the first package substrate328may overlap the second package substrate302to form an overlapped region. The first mold layer316may be positioned between the first package substrate328and second package substrate302in the overlapped region. In an aspect, the plurality of first interconnects321are configured to couple the first package substrate328to the second package substrate302in the overlapped region. In an aspect, the plurality of first interconnects321may be configured for direct electrical connection to the second package substrate302i.e., a direct electrical connection between the first package substrate328and the second package substrate302through the plurality of first interconnects321.

In an aspect of the present disclosure, the second mold layer318may include a plurality of second interconnects322. The plurality of second interconnects322may extend through the second thickness of the second mold layer318. The plurality of second interconnects322may have a first end coupled to the first package substrate328. The plurality of second interconnects322may have a second end coupled to the printed circuit board301. In an aspect, the second mold layer318may be positioned between the first package substrate328and the printed circuit board301. In an aspect, the plurality of second interconnects322are configured for direct electrical connection to the printed circuit board301i.e., a direct electrical connection between the first package substrate328and the printed circuit board301through the plurality of second interconnects322.

In an aspect, the first interconnects321and the second interconnects322may be heterogeneous or hybrid interconnects.

In an aspect of the present disclosure, each first interconnect of the plurality of first interconnects321may have a first diameter and each second interconnect of the plurality of second interconnects322may have a second diameter larger than the first diameter. The first diameter may be between 20 μm to 100 μm. The second diameter may be between 200 μm to 500 μm.

In an aspect, the plurality of first interconnects321may include metal-plated vias e.g. copper-plated vias, solder-composites vias e.g., tin-silver composites vias or an array of metal pillars and/or pins. Each first interconnect of the plurality of first interconnects321may have a pitch geometry ranging in between 30 μm to 200 μm.

In an aspect, the plurality of second interconnects322may include metal-plated vias e.g. copper-plated vias, solder-composites vias or an array of metal pillars and/or pins. Each second interconnect of the plurality of second interconnects322may have a pitch geometry ranging in between 250 μm to 700 μm.

In an aspect of the present disclosure, the plurality of second interconnects322may have an electrical property e.g., metal conductivity, that may be different from the plurality of first interconnects321.

In an aspect of the present disclosure, the plurality of first interconnects321may be configured to facilitate signal transmission between the second package substrate302and the first package substrate328. For example, the plurality of first interconnects321may be configured to facilitate data signal transmissions such as electrical signal transmissions of double data-rate (DDR) memory (at 6.4 GT/s and/or beyond) and/or radio frequency (RF) signals (at 77 GHz and/or beyond).

In an aspect, the plurality of second interconnects322may be configured to facilitate power delivery from the printed circuit board301to the first package substrate328. For example, the plurality of second interconnects322may be configured to facilitate power delivery e.g., a power supply voltage (Vcc) and to facilitate reference voltage connection e.g., a ground reference voltage (Vss) for a signal current return path.

In an aspect of the present disclosure, a plurality of first solder bumps324may be disposed below the plurality of first interconnects321. In an aspect, the plurality of first solder bumps324may provide an electrical connection between the plurality of first interconnects321, and the second package substrate302.

In an aspect of the present disclosure, a plurality of second solder bumps326may be disposed below the plurality of second interconnects322. In an aspect, the plurality of second solder bumps326may provide an electrical connection between the plurality of second interconnects322, and the printed circuit board301.

In an aspect of the present disclosure, each first solder bump of the plurality of first solder bumps324has a first diameter and each second solder bump of the plurality of second solder bumps326has a second diameter larger than the first diameter. In an aspect, the plurality of solder balls304has a third diameter equivalent to the second diameter.

In an aspect of the present disclosure, the first package substrate328may communicate with the second package substrate302and/or at least one semiconductor die312through one or more routing traces370or embedded bridge (not shown) to facilitate higher interconnect density. In an aspect, the one or more routing traces370or embedded bridge may be in the second package substrate302. The plurality of first interconnects321may be electrically coupled to the one or more routing traces370or embedded bridge. In an aspect, the first mold layer316may extend across a portion of the one or more routing traces370or embedded bridges (similar toFIG. 1B).

In an aspect of the present disclosure, a metal shield342may be disposed on the second package substrate302. The metal shield342may be a heat sink, a heat spreader, or a conductive casing. The metal shield342may be coupled to the second package substrate302through adhesive344. In an aspect, the metal shield342may be disposed over the at least one semiconductor die312. The metal shield342may be configured for thermal dissipation and/or electrical shielding of the at least one semiconductor die312, for example, from the electrical device334and/or the plurality of antennas338.

FIGS. 4A through 41show cross-sectional views directed to an exemplary process flow for a method of forming a semiconductor package according to an aspect of the present disclosure.

As shown inFIG. 4A, a memory device430may be disposed on a first package substrate428. A first mold layer416may be formed on the first package substrate428through a compression (i.e., thermal compression), injection and/or a transfer molding process.

As shown inFIG. 4B, a plurality of first interconnect openings446may be formed in the first mold layer416using mechanical drilling, laser drilling, milling and/or etching process.

As shown inFIG. 4C, a plurality of first interconnects421may be formed in the plurality of first interconnect openings446using an electroplating process, a solder paste printing and/or a coating process.

As shown inFIG. 4D, a second mold layer418may be formed on the first mold layer416through a compression (i.e., thermal compression), injection and/or a transfer molding process. In an aspect, the second mold layer418may include an electrical property e.g., a dielectric constant, or a dielectric loss tangent etc. equivalent to the first mold layer416. In other aspect, the second mold layer418may include an electrical property e.g., a dielectric constant, or a dielectric loss tangent etc different than the first mold layer416.

As shown inFIG. 4E, a plurality of second interconnect openings448may be formed in the second mold layer418using mechanical drilling, laser drilling, milling and/or etching process.

As shown inFIG. 4F, a plurality of second interconnects422may be formed in the plurality of second interconnect openings448using an electroplating process, a solder paste printing and/or a coating process. A plurality of first solder bumps424may be formed on the plurality of first interconnects421using surface solder plating.

As shown inFIG. 4G, a prefabricated structure450including a second package substrate402, an interposer406, and at least one semiconductor die412may be attached to the structure ofFIG. 4Fthrough a surface mounting and/or solder reflow process.

As shown inFIG. 4H, a plurality of second solder bumps426may be formed on the plurality of second interconnects422using surface mounting and/or solder reflow process. A plurality of solder balls404may be formed on the second package substrate402using surface mounting and/or solder reflow process.

As shown inFIG. 41, the flipped structure ofFIG. 4Hmay be attached to a printed circuit board401through a surface mounting and/or solder reflow process.

It will be understood that the exemplary process described above relating toFIGS. 4A through 41are not limited to this particular order. Any suitable, modified order of operations may be used.

Aspects of the present disclosure may be implemented into a system using any suitable hardware and/or software.

FIG. 5schematically illustrates a computing device500that may include a semiconductor package as described herein, in accordance with some aspects.

As shown inFIG. 5, the computing device500may house a board such as a motherboard502. The motherboard502may include a number of components, including but not limited to a processor504and at least one communication chip506. The processor504may be physically and electrically coupled to the motherboard502. In some implementations, the at least one communication chip506may also be physically and electrically coupled to the motherboard502. In further implementations, the communication chip506may be part of the processor504.

The communication chip506may enable wireless communications for the transfer of data to and from the computing device500. The term “wireless” and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a non-solid medium. The term does not imply that the associated devices do not contain any wires, although in some aspects they might not. The communication chip506may implement any of a number of wireless standards or protocols, including but not limited to Institute for Electrical and Electronics Engineers (IEEE) standards including Wi-Fi (IEEE 502.11 family), IEEE 502.16 standards (e.g., IEEE 502.16-2005 Amendment), Long-Term Evolution (LTE) project along with any amendments, updates, and/or revisions (e.g., advanced LTE project, ultra-mobile broadband (UMB) project (also referred to as “3GPP2”), etc.). IEEE 502.16 compatible BWA networks are generally referred to as WiMAX networks, an acronym that stands for Worldwide Interoperability for Microwave Access, which is a certification mark for products that pass conformity and interoperability tests for the IEEE 502.16 standards.

The communication chip506may also operate in accordance with a Global System for Mobile Communication (GSM), General Packet Radio Service (GPRS), Universal Mobile Telecommunications System (UMTS), High Speed Packet Access (HSPA), Evolved HSPA (E-HSPA), or LTE network. The communication chip506may operate in accordance with Enhanced Data for GSM Evolution (EDGE), GSM EDGE Radio Access Network (GERAN), Universal Terrestrial Radio Access Network (UTRAN), or Evolved UTRAN (E-UTRAN). The communication chip506may operate in accordance with Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Evolution-Data Optimized (EV-DO), derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond. The communication chip506may operate in accordance with other wireless protocols in other aspects.

The computing device500may include a plurality of communication chips506. For instance, a first communication chip506may be dedicated to shorter range wireless communications such as Wi-Fi and Bluetooth and a second communication chip506may be dedicated to longer range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others.

EXAMPLES

Example 1 may include a device including a first package substrate. The device may include a first mold layer with a first thickness. The device may include a second mold layer with a second thickness proximal to the first mold layer. The second thickness may be larger than the first thickness. The first mold layer may include a plurality of first interconnects coupled to the first package substrate. The second mold layer may include a plurality of second interconnects configured to couple the first package substrate to a printed circuit board.

Example 2 may include the device of example 1 and/or any other example disclosed herein in which the device further includes a second package substrate, wherein at least a portion of the first package substrate overlaps the second package substrate to form an overlapped region, and wherein the plurality of first interconnects are configured to couple the first package substrate to the second package substrate in the overlapped region.

Example 3 may include the device of example 2 and/or any other example disclosed herein in which the first mold layer is positioned between the first package substrate and second package substrate in the overlapped region, and the plurality of first interconnects are configured for direct electrical connection to the second package substrate, in which the second mold layer is positioned between the first package substrate and the printed circuit board, and the plurality of second interconnects are configured for direct electrical connection to the printed circuit board.

Example 4 may include the device of example 1 and/or any other example disclosed herein in which each first interconnect of the plurality of first interconnects has a first diameter and each second interconnect of the plurality of second interconnects has a second diameter larger than the first diameter.

Example 5 may include the device of example 2 and/or any other example disclosed herein in which the plurality of first interconnects are configured to facilitate signal transmission between the second package substrate and the first package substrate, and in which the plurality of second interconnects are configured to facilitate power delivery from the printed circuit board to the first package substrate.

Example 6 may include the device of example 1 and/or any other example disclosed herein in which the device further includes a space between the first mold layer and the second mold layer, in which the device further includes an electrical device disposed in the space, in which the electrical device is electrically coupled on a first side to the first package substrate and coupled on a second side to a heat spreader disposed on the printed circuit board.

Example 7 may include the device of example 6 and/or any other example disclosed herein in which the electrical device is a radio-frequency integrated circuit (RFIC), and in which the device further includes a plurality of antennas disposed on the first package substrate configured for signal connection with the RFIC.

Example 8 may include the device of example 6 and/or any other example disclosed herein in which the device further includes at least one semiconductor die disposed on the second package substrate, and in which the device further includes a metal shield disposed over the at least one semiconductor die configured for thermal dissipation and/or electrical shielding of the at least one semiconductor die from the electrical device.

Example 9 may include the device of example 3 and/or any other example disclosed herein in which the device further includes a first memory platform comprising at least one memory device coupled to a top surface of the first package substrate and the first mold layer and second mold layer attached to a bottom surface of the first package substrate located at a first end of the second substrate, and a second memory platform located at a second end of the second substrate opposite the first end of the second substrate.

Example 10 may include a method including providing a first package substrate, forming a first mold layer with a first thickness, forming a plurality of first interconnects in the first mold layer for coupling to the first package substrate, forming a second mold layer with a second thickness proximal to the first mold layer, wherein the second thickness may be larger than the first thickness, and forming a plurality of second interconnects in the second mold layer for coupling the first package substrate to a printed circuit board.

Example 11 may include the method of example 10 and/or any other example disclosed herein in which the method further includes providing a second package substrate, wherein at least a portion of the first package substrate overlaps the second package substrate to form an overlapped region, and wherein the plurality of first interconnects are configured to couple the first package substrate to the second package substrate in the overlapped region.

Example 12 may include the method of example 11 and/or any other example disclosed herein in which the first mold layer is positioned between the first package substrate and second package substrate in the overlapped region, and the plurality of first interconnects are configured for direct electrical connection to the second package substrate, in which the second mold layer is positioned between the first package substrate and the printed circuit board, and the plurality of second interconnects are configured for direct electrical connection to the printed circuit board.

Example 13 may include the method of example 11 and/or any other example disclosed herein in which each first interconnect of the plurality of first interconnects has a first diameter and each second interconnect of the plurality of second interconnects has a second diameter larger than the first diameter.

Example 14 may include the method of example 11 and/or any other example disclosed herein in which the plurality of first interconnects are configured to facilitate signal transmission between the second package substrate and the first package substrate, and wherein the plurality of second interconnects are configured to facilitate power delivery from the printed circuit board to the first package substrate.

Example 15 may include the method of example 10 and/or any other example disclosed herein in which the method further includes forming a space between the first mold layer and the second mold layer, disposing an electrical device in the space, wherein the electrical device is electrically coupled on a first side to the first package substrate and coupled on a second side to a heat spreader disposed on the printed circuit board.

Example 16 may include the method of example 15 and/or any other example disclosed herein in which the method further includes disposing a plurality of antennas disposed on the first package substrate, wherein the electrical device is a radio-frequency integrated circuit (RFIC) and the plurality of antennas are configured for signal connection with the RFIC.

Example 17 may include the method of example 15 and/or any other example disclosed herein in which the method further includes disposing at least one semiconductor die on the second package substrate, and disposing a metal shield over the at least one semiconductor die for thermal dissipation and/or electrical shielding of the at least one semiconductor die from the electrical device.

Example 18 may include the method of example 10 and/or any other example disclosed herein in which the method further includes coupling at least one memory device to the first package substrate.

Example 19 may include a computing device including a printed circuit board, and a device coupled to the printed circuit board. The device may include a first mold layer with a first thickness. The device may include a second mold layer with a second thickness proximal to the first mold layer. The second thickness may be larger than the first thickness. The first mold layer may include a plurality of first interconnects coupled to the first package substrate. The second mold layer may include a plurality of second interconnects configured to couple the first package substrate to the printed circuit board.

Example 20 may include the computing device of example 19 and/or any other example disclosed herein in which the computing device further includes a second package substrate, wherein at least a portion of the first package substrate overlaps the second package substrate to form an overlapped region, and wherein the plurality of first interconnects are configured to couple the first package substrate to the second package substrate in the overlapped region.

These and other advantages and features of the aspects herein disclosed will be apparent through reference to the following description and the accompanying drawings. Furthermore, it is to be understood that the features of the various aspects described herein are not mutually exclusive and can exist in various combinations and permutations.

It will be understood that any property described herein for a specific package or device may also hold for any package or device described herein. It will also be understood that any property described herein for a specific method may hold for any of the methods described herein. Furthermore, it will be understood that for any device, package, or method described herein, not necessarily all the components or operations described will be enclosed in the device, package, or method, but only some (but not all) components or operations may be enclosed.

The term “comprising” shall be understood to have a broad meaning similar to the term “including” and will be understood to imply the inclusion of a stated integer or operation or group of integers or operations but not the exclusion of any other integer or operation or group of integers or operations. This definition also applies to variations on the term “comprising” such as “comprise” and “comprises”.

The term “coupled” (or “connected”) herein may be understood as electrically coupled or as mechanically coupled, e.g., attached or fixed or attached, or just in contact without any fixation, and it will be understood that both direct coupling or indirect coupling (in other words: coupling without direct contact) may be provided.

While the present disclosure has been particularly shown and described with reference to specific aspects, it should be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the scope of the present disclosure as defined by the appended claims. The scope of the present disclosure is thus indicated by the appended claims and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced.