Delaying hot block garbage collection with adaptation

Memory systems may include a memory storage, and a controller suitable for measuring a write amplification (WA) value of a first, current window, comparing the WA value for the first window with a previous WA value for a previous window, and calculating and setting a value of a ratio threshold based on the comparison of the WA value for the current window threshold to the WA value of the previous window threshold.

BACKGROUND

Exemplary embodiments of the present disclosure relate to a memory system and an operating method thereof.

2. Description of the Related Art

The computer environment paradigm has shifted to ubiquitous computing systems that can be used anytime and anywhere. Due to this fact, the use of portable electronic devices such as mobile phones, digital cameras, and notebook computers has rapidly increased. These portable electronic devices generally use a memory system having memory devices, that is, a data storage device. The data storage device is used as a main memory device or an auxiliary memory device of the portable electronic devices.

Data storage devices using memory devices provide excellent stability, durability, high information access speed, and low power consumption, since they have no moving parts. Examples of data storage devices having such advantages include universal serial bus (USB) memory devices, memory cards having various interfaces, and solid state drives (SSD).

Separating hot and cold data via garbage collection processes is desired for the improved effectiveness and lifespan of flash memory products, and thus improved methods of doing so are needed.

SUMMARY

Aspects of the invention include memory systems. The memory systems may include a memory storage, and a controller suitable for measuring a write amplification (WA) value of a first, current window, comparing the WA value for the first window with a previous WA value for a previous window, and calculating and setting a value of a ratio threshold based on the comparison of the WA value for the current window threshold to the WA value of the previous window threshold.

Further aspects of the invention include methods. The methods may include measuring, with a controller, a write amplification (WA) value of a first, current window, comparing, with the controller, the WA value for the first window with a previous WA value for a previous window, and calculating and setting, with the controller, a value of a ratio threshold based on the comparison of the WA value for the current window threshold to the WA value of the previous window threshold.

Additional aspects of the invention include memory devices. The memory devices may include a memory storage, and a controller configured to measure a write amplification (WA) value of a first, current window, compare the WA value for the first window with a previous WA value for a previous window, and calculate and set a value of a ratio threshold based on the comparison of the WA value for the current window threshold to the WA value of the previous window threshold.

DETAILED DESCRIPTION

The invention can be implemented in numerous ways, including as a process; an apparatus; a system; a composition of matter; a computer program product embodied on a computer readable storage medium; and/or a processor, such as a processor suitable for executing instructions stored on and/or provided by a memory coupled to the processor. In this specification, these implementations, or any other form that the invention may take, may be referred to as techniques. In general, the order of the steps of disclosed processes may be altered within the scope of the invention. Unless stated otherwise, a component such as a processor or a memory described as being suitable for performing a task may be implemented as a general component that is temporarily suitable for performing the task at a given time or a specific component that is manufactured to perform the task. As used herein, the term ‘processor’ refers to one or more devices, circuits, and/or processing cores suitable for processing data, such as computer program instructions.

FIG. 1is a block diagram schematically illustrating a memory system10in accordance with an embodiment of the present invention.

ReferringFIG. 1, the memory system10may include a memory controller100and a semiconductor memory device200.

The memory controller100may control overall operations of the semiconductor memory device200.

The semiconductor memory device200may perform one or more erase, program, and read operations under the control of the memory controller100. The semiconductor memory device200may receive a command CMD, an address ADDR and data DATA through input/output lines. The semiconductor memory device200may receive power PWR through a power line and a control signal CTRL through a control line. The control signal may include a command latch enable (CLE) signal, an address latch enable (ALE) signal, a chip enable (CE) signal, a write enable (WE) signal, a read enable (RE) signal, and so on.

The memory controller100and the semiconductor memory device200may be integrated in a single semiconductor device. For example, the memory controller100and the semiconductor memory device200may be integrated in a single semiconductor device such as a solid state drive (SSD). The solid state drive may include a storage device for storing data therein. When the semiconductor memory system10is used in an SSD, operation speed of a host (not shown) coupled to the memory system10may remarkably improve.

The memory controller100and the semiconductor memory device200may be integrated in a single semiconductor device such as a memory card. For example, the memory controller100and the semiconductor memory device200may be integrated in a single semiconductor device to configure a memory card such as a PC card of personal computer memory card international association (PCMCIA), a compact flash (CF) card, a smart media (SM) card, a memory stick, a multimedia card (MMC), a reduced-size multimedia card (RS-MMC), a micro-size version of MMC (MMCmicro), a secure digital (SD) card, a mini secure digital (miniSD) card, a micro secure digital (microSD) card, a secure digital high capacity (SDHC), and a universal flash storage (UFS).

For another example, the memory system10may be provided as one of various elements including an electronic device such as a computer, an ultra-mobile PC (UMPC), a workstation, a net-book computer, a personal digital assistant (PDA), a portable computer, a web tablet PC, a wireless phone, a mobile phone, a smart phone, an e-book reader, a portable multimedia player (PMP), a portable game device, a navigation device, a black box, a digital camera, a digital multimedia broadcasting (DMB) player, a 3-dimensional television, a smart television, a digital audio recorder, a digital audio player, a digital picture recorder, a digital picture player, a digital video recorder, a digital video player, a storage device of a data center, a device capable of receiving and transmitting information in a wireless environment, one of electronic devices of a home network, one of electronic devices of a computer network, one of electronic devices of a telematics network, a radio-frequency identification (RFID) device, or elements devices of a computing system.

FIG. 2is a detailed block diagram illustrating a memory system in accordance with an embodiment of the present invention. For example, the memory system ofFIG. 2may depict the memory system10shown inFIG. 1.

Referring toFIG. 2, the memory system10may include a memory controller100and a semiconductor memory device200. The memory system10may operate in response to a request from a host device, and in particular, store data to be accessed by the host device.

The host device may be implemented with any one of various kinds of electronic devices. In some embodiments, the host device may include an electronic device such as a desktop computer, a workstation, a three-dimensional (3D) television, a smart television, a digital audio recorder, a digital audio player, a digital picture recorder, a digital picture player, a digital video recorder and a digital video player. In some embodiments, the host device may include a portable electronic device such as a mobile phone, a smart phone, an e-book, an MP3 player, a portable multimedia player (PMP), and a portable game player.

The memory device200may store data to be accessed by the host device.

The controller100may control storage of data in the memory device200. For example, the controller100may control the memory device200in response to a request from the host device. The controller100may provide the data read from the memory device200, to the host device, and store the data provided from the host device into the memory device200.

The controller100may include a storage unit110, a control unit120, the error correction code (ECC) unit130, a host interface140and a memory interface150, which are coupled through a bus160.

The storage unit110may serve as a working memory of the memory system10and the controller100, and store data for driving the memory system10and the controller100. When the controller100controls operations of the memory device200, the storage unit110may store data used by the controller100and the memory device200for such operations as read, write, program and erase operations.

The storage unit110may be implemented with a volatile memory. The storage unit110may be implemented with a static random access memory (SRAM) or a dynamic random access memory (DRAM). As described above, the storage unit110may store data used by the host device in the memory device200for the read and write operations. To store the data, the storage unit110may include a program memory, a data memory, a write buffer, a read buffer, a map buffer, and so forth.

The control unit120may control general operations of the memory system10, and a write operation or a read operation for the memory device200, in response to a write request or a read request from the host device. The control unit120may drive firmware, which is referred to as a flash translation layer (FTL), to control the general operations of the memory system10. For example, the FTL may perform operations such as logical to physical (L2P) mapping, wear leveling, garbage collection, and bad block handling. The L2P mapping is known as logical block addressing (LBA).

The ECC unit130may detect and correct errors in the data read from the memory device200during the read operation. The ECC unit130may not correct error bits when the number of the error bits is greater than or equal to a threshold number of correctable error bits, and may output an error correction fail signal indicating failure in correcting the error bits.

In some embodiments, the ECC unit130may perform an error correction operation based on a coded modulation such as a low density parity check (LDPC) code, a Bose-Chaudhuri-Hocquenghem (BCH) code, a turbo code, a turbo product code (TPC), a Reed-Solomon (RS) code, a convolution code, a recursive systematic code (RSC), a trellis-coded modulation (TCM), a Block coded modulation (BCM), and so on. The ECC unit130may include all circuits, systems or devices for the error correction operation.

The host interface140may communicate with the host device through one or more of various interface protocols such as a universal serial bus (USB), a multi-media card (MMC), a peripheral component interconnect express (PCI-E), a small computer system interface (SCSI), a serial-attached SCSI (SAS), a serial advanced technology attachment (SATA), a parallel advanced technology attachment (PATA), an enhanced small disk interface (ESDI), and an integrated drive electronics (IDE).

The memory interface150may provide an interface between the controller100and the memory device200to allow the controller100to control the memory device200in response to a request from the host device. The memory interface150may generate control signals for the memory device200and process data under the control of the CPU120. When the memory device200is a flash memory such as a NAND flash memory, the memory interface150may generate control signals for the memory and process data under the control of the CPU120.

The memory device200may include a memory cell array210, a control circuit220, a voltage generation circuit230, a row decoder240, a page buffer250, a column decoder260, and an input/output circuit270. The memory cell array210may include a plurality of memory blocks211and may store data therein. The voltage generation circuit230, the row decoder240, the page buffer250, the column decoder260and the input/output circuit270form a peripheral circuit for the memory cell array210. The peripheral circuit may perform a program, read, or erase operation of the memory cell array210. The control circuit220may control the peripheral circuit.

The voltage generation circuit230may generate operation voltages having various levels. For example, in an erase operation, the voltage generation circuit230may generate operation voltages having various levels such as an erase voltage and a pass voltage.

The row decoder240may be connected to the voltage generation circuit230, and the plurality of memory blocks211. The row decoder240may select at least one memory block among the plurality of memory blocks211in response to a row address RADD generated by the control circuit220, and transmit operation voltages supplied from the voltage generation circuit230to the selected memory blocks among the plurality of memory blocks211.

The page buffer250is connected to the memory cell array210through bit lines BL (not shown). The page buffer250may precharge the bit lines BL with a positive voltage, transmit/receive data to/from a selected memory block in program and read operations, or temporarily store transmitted data, in response to a page buffer control signal generated by the control circuit220.

The column decoder260may transmit/receive data to/from the page buffer250or transmit/receive data to/from the input/output circuit270.

The input/output circuit270may transmit, to the control circuit220, a command and an address, transmitted from an external device (e.g., the memory controller100), transmit data from the external device to the column decoder260, or output data from the column decoder260to the external device, through the input/output circuit270.

The control circuit220may control the peripheral circuit in response to the command and the address.

FIG. 3is a circuit diagram illustrating a memory block of a semiconductor memory device in accordance with an embodiment of the present invention. For example, a memory block ofFIG. 3may be the memory blocks211of the memory cell array200shown inFIG. 2.

Referring toFIG. 3, the memory blocks211may include a plurality of cell strings221coupled to bit lines BL0to BLm−1, respectively. The cell string of each column may include one or more drain selection transistors DST and one or more source selection transistors SST. A plurality of memory cells or memory cell transistors may be serially coupled between the selection transistors DST and SST. Each of the memory cells MC0to MCn−1may be formed of a multi-level cell (MLC) storing data information of multiple bits in each cell. The cell strings221may be electrically coupled to the corresponding bit lines BL0to BLm−1, respectively.

In some embodiments, the memory blocks211may include a NAND-type flash memory cell. However, the memory blocks211are not limited to the NAND flash memory, but may include NOR-type flash memory, hybrid flash memory in which two or more types of memory cells are combined, and one-NAND flash memory in which a controller is embedded inside a memory chip.

FIG. 4is a diagram of an example system40according to aspects of the invention. The system40includes a DRAM400portion and a memory402portion. The DRAM portion400may include an LBA table410for mapping LBA addresses and a controller404, such as the controllers described above. The DRAM400portion may be a volatile memory and may be in communication with the memory portion402. The memory portion402may be a non-volatile memory portion. The memory portion402may include a plurality of memory blocks (e.g., or memory super blocks), as well as an open block for host writes430and an open block for garbage collection (GC)440.

A simple method for choosing garbage collection (GC) victim blocks that achieves the effect of hot and cold data separation has been disclosed in U.S. application Ser. No. 15/152,352 entitled “DATA SEPARATION BY DELAYING HOT BLOCK GARBAGE COLLECTION”, the contents of which are disclosed by reference herein. In the method, two candidate victim blocks are identified for each instance of GC. The first candidate is the block with the minimum number of valid pages among all the closed blocks in a drive, while the second candidate is the block with the minimum number of valid pages among only the M oldest closed blocks in the drive, where M denotes the size of the pool of oldest closed blocks. The method then computes the valid page ratio of the number of valid pages of the second candidate to that of the first candidate and compares it against a ratio threshold k. If the valid page ratio is larger than k, the first candidate is selected as the final victim block. Otherwise, the second candidate is selected.

The parameters M and k may be jointly optimized for a given over-provisioning (OP) value and traffic pattern. Although the amount of OP is fixed ahead of time when a drive is first designed, the traffic pattern, unfortunately, may not be known in advance, and the traffic pattern may also be time-varying. Thus, pre-determined values for M and k are often suboptimal for the actual traffic pattern seen by a drive, which inevitably results in a higher write amplification (WA) value.

To mitigate the aforementioned problem, an adaptive algorithm that periodically adjusts the value of k to lower WA is disclosed herein. Instead of trying to adjust both the values of k and M together, the invention adapts the value of k while M remains fixed at a pre-determined value. This is because formulating an algorithm to adapt both parameters together is very difficult. In addition, WA is more sensitive to changes in k than M, which means changing the value of k is more effective in lowering WA than changing the value of M. Note that the proposed algorithm does not assume any a priori knowledge of the traffic pattern, which may be time-varying.

Referring toFIG. 5, a flowchart50of steps for adjusting a ratio threshold K are shown. At step500, a WA value is measured for a current window. At step502, a WA value for the current window is compared with a WA value of a previous window. At step504, the value of the ratio threshold K is calculated and set based on the comparison of the WA value of the current window to the WA value of the previous window.

An adaptive algorithm without the aid of a priori or side information adjusts the value of a parameter by periodically increasing or decreasing its value by a small amount according to some feedback metric. The proposed algorithm described in this disclosure follows the same approach. The feedback metric used in the proposed algorithm is the difference between two WA values measured in two consecutive time windows. Based on the difference, the algorithm determines the direction of the adjustment, i.e., whether to increase or decrease the value of k, as well as the magnitude of the adjustment.

In one embodiment, a WA value is recorded for every window of N drive writes. WAcurrand WAprevdenote the WA value measured over the most recent time window and the second most recent time window, respectively. If WAcurris less than WAprev, whatever the direction of adjustment chosen last is deemed correct as a lower WA is obtained after the last adjustment. Therefore, the direction will remain unchanged for the next adjustment. Otherwise, the opposite direction is chosen. For the magnitude of the adjustment, it is set proportional to the magnitude of the difference in the WA values, i.e., |WAprev−WAcurr|. This procedure is then repeated at the end of each new time window.

An example algorithm is shown schematically below.

Repeat at the end of every N drive writes:

Compute WAcurrfor the most recent window of N drive writes.

If WAprev!=0

If (WAprev−WAcurr)<0, set dir=−dir.

If k<klower_limit, set k=klower_limit.

In the algorithm, kinitialand klower_limitdenote the initial value and the lower limit of k, respectively; dir is a binary variable that denotes the direction of adjustment, where 1 and −1 represents increasing and decreasing the value of k, respectively; and μ denotes the proportionality constant for the magnitude of the adjustment. Note that the purpose of having klower_limitis to prevent k from becoming too small, which may lead to higher WA values for some traffic patterns.

Implementation of the algorithm is relatively straightforward as the computations involved in the algorithm are quite simple. Moreover, since the algorithm is only run at the end of every N drive writes, where N can be any real number, the overhead in using the algorithm is low.

An example simulation is described below. The values of the drive parameters used in the simulations are:

Number of user blocks=1790;

Number of blocks in free block pool=16;

Also, M is fixed at 1000. The values of the parameters are set as:

FIG. 6is a graph600showing the relationship between cumulative WA after 500 drive writes and the percentage of hot data in a traffic pattern for a fixed OP value of 11.73%. Lower WA values are obtained by using the proposed adaptive algorithm for traffic patterns with hot data ranging from 1% to 30%, with the largest improvements seen between 1% and 10%. These results show that the proposed adaptive algorithm is most effective for traffic patterns with a small percentage of hot data.

FIG. 7andFIG. 8are graphs70and80illustrating the variations of WA values as a function of time for the traffic patterns with 1% and 10% of hot data, respectively. In the figures, time is measured in terms of the number of drive writes. The top graph700,800in each figure shows the variations of windowed WA values, where the window size is 1 drive write, while the bottom graphs702,802shows the variations of cumulative WA values. The figures show that the WA values with adaptation are consistently lower than the WA values without adaptation.