Apparatus and methods for controlling output of clock signal and systems including the same

An apparatus for controlling data exchange with a memory device includes an interface configured to receive an arbitration signal indicating when the apparatus has use of a shared bus and an interface to the memory device configured to provide a clock signal to the memory device that synchronizes data exchange between the apparatus and the memory device. A selection circuit selectively supplies the clock signal to the memory device responsive to the arbitration signal.

CROSS-REFERENCE TO RELATED PATENT APPLICATIONS

This application is related to and claims priority from Korean Patent Application No. 10-2005-0115738, filed on Nov. 30, 2005, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety.

BACKGROUND OF THE INVENTION

The present invention relates to a control apparatus and method, and more particularly, to an apparatus and method for controlling supply of a clock signal to a memory device.

FIG. 1is a block diagram of a system10including a memory device40and a conventional controller20.FIG. 2is a timing diagram of signals output from a master that interfaces with the memory device40illustrated inFIG. 1. Referring toFIGS. 1 and 2, the system10includes a controller20, the memory device40, a first host50and a second host52.

The controller20includes first through fourth masters22,24,26, and28, an arbiter30, a first slave32, a second slave34, and a bus36. It is assumed for purposes of this description that the first slave32is a data random-access memory (RAM) that stores data exchanged with the third master26, and the second slave34is a data RAM that stores data exchanged with the fourth master28.

As the first through fourth masters22,24,26, and28share the bus36in the controller20, they may access the bus36according to a priority protocol controlling use or ownership of the bus36. The arbiter30arbitrates the priority of use of the bus36between the first through fourth masters22,24,26, and28according to a specified method or protocol, such as a fixed priority method or a round-robin method. Accordingly, while one of the first through fourth masters22,24,26, and28uses the bus36, the other masters must wait for some time period until they obtain priority to use of the bus36.

If the first host50exchanges a large amount of data, e.g., 2 KB of data, with the memory device40through the third master26, the first slave32, and the second master24using the bus36, the second master24may need to use/control the bus36for a long period of time. Also, when the second host52exchanges a large amount of data with the memory device40via the fourth master28, the second slave34, and the second master24using the bus36, the second master24may also need to use/control the bus36for a long period of time.

However, when a master (e.g., the first master22) having higher priority than the second master24requests the arbiter30allow it to use/control the bus36and uses the bus36, the second master24must wait for a period of time until the first master22loses the ownership of the bus36. That is, when a master (e.g., the first master22) having higher priority than the second master24requests the use of the bus36, the second master24generally stores a predetermined address ADD of currently transmitted data A, B, . . . , C in a predetermined storage device, transfers the ownership of the bus36to the first master22, and waits for a period of time until the higher priority master loses the ownership of the bus36.

Referring toFIG. 2, when the second master24regains the ownership of the bus36, the second master24of the controller20and the memory device40generally must be reset to transmit the remaining data D, E, . . . , G. Then, the second master24may transmit the address following the address of the already transmitted data (e.g., data C) to the memory device40, and exchange the remaining data D, E, . . . , G with the memory device40. As a result, the data transmission performance (efficiency) between the second master24of the controller20having the first through fourth22,24,26, and28, and the memory device40may be significantly lowered.

Also, even if data cannot be exchanged between the second master24of the controller20and the memory device40(for example, when the second master24loses the ownership of the bus36), the second master24typically continuously supplies a clock signal CLK to the memory device40, which may cause unnecessary consumption of power in the second master24and the memory device40.

SUMMARY OF THE INVENTION

Embodiments of an apparatus for controlling data exchange with a memory device includes an interface configured to receive an arbitration signal indicating when the apparatus has use of a shared bus and an interface to the memory device configured to provide a clock signal to the memory device that synchronizes data exchange between the apparatus and the memory device. A selection circuit selectively supplies the clock signal to the memory device responsive to the arbitration signal.

In some embodiments, the apparatus further includes a delay logic configured to receive an input clock signal and to delay the input clock signal to generate the clock signal to the memory device. The selection circuit is configured to receive a DC-level signal input via a first input terminal and the delayed input clock signal via a second input terminal and to supply a selected one of the DC-level signal input or the delayed input clock signal to the memory device responsive to the arbitration signal. The memory device may be a logic-embedded NAND flash memory.

In other embodiments, the apparatus further includes a mode information storage circuit that stores an indication of a current data transfer mode and a selection signal generation circuit that receives the arbitration signal and a signal from the mode information storage circuit indicating the current data transfer mode and generates a selection signal based on a logic combination of the received signals. The selection circuit is configured to supply a selected one of a DC-level signal and the clock signal to the memory device responsive to the selection signal from the selection signal generation circuit. The memory device may be a NAND flash memory core, a NOR interface, and an SRAM buffer.

In further embodiments, a controller includes a bus and a first master coupled to the bus and a second master coupled to the bus. The second master is communicatively coupled to an external semiconductor device and is configured to selectively supply a clock signal to the semiconductor device, that synchronizes data exchange with the semiconductor device, responsive to an arbitration signal associated with the bus. An arbiter coupled to the bus is configured to arbitrate ownership of the bus between the first and second masters and to generate the arbitration signal to communicate ownership of the bus. The second master may supply the clock signal to the semiconductor device responsive to a first state of the arbitration signal indicating the second master has ownership of the bus or a DC-level signal to the semiconductor device responsive to a second state of the arbitration signal indicating the second master does not have ownership of the bus.

In other embodiments, the second master includes a selection circuit. The selection circuit includes a first input terminal that receives the DC-level signal, a second input terminal that receives the clock signal and an output terminal. The selection circuit is configured to output one of the DC-level signal and the clock signal via the output terminal responsive to the arbitration signal.

In yet other embodiments, the second master includes a mode information storage circuit that stores an indication of a current data transfer mode. A selection signal generation circuit of the second master receives the arbitration signal and a signal from the mode information storage circuit indicating the current data transfer mode and generates a selection signal based on a logic combination of the received signals. A selection circuit of the second master receives the DC-level signal and the clock signal and selectively outputs the DC-level signal or the clock signal responsive to the selection signal from the selection signal generation circuit. The second master may further include a clock signal generator that generates the clock signal.

In further embodiments, the second master includes a mode information storage circuit that stores an indication of a current data transfer mode, wherein the current transfer mode comprises a synchronous data transfer mode or an asynchronous data transfer mode. A selection signal generation circuit receives the arbitration signal and a signal from the mode information storage circuit indicating the current data transfer mode and generates a selection signal based on a logic combination of the received signals. A delay circuit receives an input clock signal and delays the input clock signal for a predetermined time to generate the clock signal. A selection circuit receives the DC-level signal and the delayed input clock signal from the delay circuit and selectively outputs the DC-level signal of the delayed input clock signal responsive to the selection signal from the selection signal generation circuit.

In other embodiments, systems are provided including controllers as described above in combination with the semiconductor device. The semiconductor device is configured to communicate data with the controller in synchronization with the clock signal from the controller.

In yet further embodiments, a system includes a memory device and a controller. The controller includes a shared bus and a plurality of masters coupled to the shared bus. A first one of the masters is configured to selectively supply a clock signal of a DC-level signal to the memory device to synchronize data transfer between the first master and the memory device in a synchronous data transfer mode responsive to an arbitration signal indicating when the first master has ownership of the shared bus. The system further includes an arbiter that is configured to arbitrate ownership of the shared bus among the plurality of masters and to generate the arbitration signal to communicate ownership of the shared bus.

In other embodiments, the first master supplies the clock signal to the memory device when the first master has ownership of the bus, and the DC-level signal to the memory device when the first master does not have ownership of the bus. The memory device may be configured to maintain data, which is to be transmitted to the first master, responsive to the DC-level signal and then transmit the maintained data responsive to later receipt of the clock signal.

In further embodiments, methods of supplying a clock signal from a controller coupled to a shared resource to a memory device are provided. The clock signal is used for synchronizing data transfer between the controller and the memory device. The method includes supplying a DC-level signal from the controller to the memory device when the controller does not have ownership of the shared resource. Data that is to be transferred from the memory device is held responsive to supplying the DC-level signal. The clock signal is supplied to the memory device when the controller regains the ownership of the internal resources. The held data is transferred from the memory device responsive to supplying of the clock signal.

DETAILED DESCRIPTION OF THE INVENTION

The invention is described more fully hereinafter with reference to the accompanying drawings, in which embodiments of the invention are shown. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will filly convey the scope of the invention to those skilled in the art. In the drawings, the size and relative sizes of layers and regions may be exaggerated for clarity.

Embodiments of the present invention will now be further described with reference toFIGS. 3-7.FIG. 3is a block diagram illustrating a system100having a memory device130and a controller110according to some embodiments of the present invention. As shown inFIG. 3, the system100includes a controller110, a memory device (or integrated circuit device)130and a host140. The system100may be used, for example, with a handset (e.g., a mobile communication device), a digital television (TV), a digital camera, a global positioning system (GPS) device, a memory card, etc. The memory card may be, for example, a secure digital (SD) card or a multimedia card (MMC).

The controller110exchanges predetermined data with the memory device130under control of the host140. The illustrated controller110includes a plurality of masters, illustrated as first through third masters112,114, and116inFIG. 3, a bus118, an arbiter120, a first slave122, and a second slave124. The bus118is an example of a shared internal resource.

The first master112may be implemented as a micro control unit (MCU) that controls the overall operations of the controller110, the second master114may be implemented as a master that interfaces with the memory device130and the third master116may be implemented as a master that interfaces with the host140. The second master114supplies control signals CLK, for example, signals /AVD, /CE as illustrated inFIG. 6, to the memory device130.

The first through third masters112,114, and116share the bus118. The arbiter120determines (or arbitrates) priority to use the bus118among the first through third masters112,114, and116. Aspects of implementation of a bus request signal and a bus grant signal exchanged between each of the first through third masters112,114, and116, and the arbiter120for bus control that are conventional will not be further described herein except as required to fully explain exemplary embodiments of the present invention.

For purposes of explanation herein, it is assumed that the first master112has higher priority of use of the bus118than the other masters114and116. The first slave122may be a data storage device that stores firmware and predetermined data. The first slave122may store data that it exchanges with the first master112under control of the first master112. The second slave124may be a data storage device that stores data exchanged between the second and third masters114and116. The second master114may exchange data with the memory device130. The third master116may exchange data with the host140. Data exchanged between the host140and the memory device130may be temporarily stored in the second slave124. Thus, the second slave124may act as a buffer.

The memory device130may include, for example, a NAND flash memory core, a NOR interface logic and/or an SRAM buffer. In some embodiments, the memory device130may be a logic-embedded NAND flash memory, such as OneNAND™ manufactured by Samsung Electronics. If the memory device130is OneNAND™, the operations and construction of the memory device130are disclosed in the specifications thereof.

The memory device130may be implemented as a chip having a NAND flash memory, a controller logic, a buffer RAM and a hardware ECC. Also, the memory device130may be a non-volatile memory device having a NAND flash memory as a core.

When the first master112having higher priority than the second master114requests the use of the bus118while the second master114is exchanging data with the memory device130and the second slave124via the bus118, the second master114sets a level of a clock signal CLK to the memory device130and second slave124to “low (or, 0)” or “high (or, 1)” during the period where data transmission is to be discontinued (a data hold period shown inFIG. 6). In other words, the second master114intercepts (cuts off) the supply of the clock signal CLK to the memory device130. Thus, data C or H that is output (or will be output) from the second master114to the memory device130or vice versa is maintained (or held) by the second master114or the memory device130as illustrated inFIG. 6.

When the second master114regains the ownership of the bus118, it resumes supply of a normally toggled clock signal CLK to the memory device130. Accordingly, the second master114and the memory device130can continue to exchange data with each other in synchronization with the clock signal CLK.

FIG. 4is a block diagram of the second master114illustrated inFIG. 3according to some embodiments of the present invention.FIG. 6is a timing diagram of signals output from a master, such as that shown inFIG. 3throughFIG. 5, according to some embodiments of the present invention. Referring toFIGS. 3 and 4, the second master114includes a mode information storage circuit210, a selection signal generation circuit220, and a selection circuit226. In some embodiments, the second master114may further include a delay logic224.

The mode information storage circuit210stores information regarding an asynchronous data transfer mode or a synchronous data transfer mode. The mode information storage circuit210may be, for example, a special function register (SFR) as shown inFIG. 4.

In some exemplary embodiments, data of “0” is input to the mode information storage circuit210in the asynchronous data transfer mode, and data of “1” is input to the mode information storage circuit210in the synchronous data transfer mode. That is, a mode selection signal MODE_SEL input to the second master114has a value of “0” or “1”.

In the asynchronous data transfer mode, the second master114and the memory device130exchange data that is not synchronized with the clock signal CLK supplied to the memory device130. The synchronous data transfer mode indicates a mode where the second master114and the memory device130exchange data that is synchronized with the clock signal CLK supplied to the memory device130.

If the second master114has the ownership of the bus118, the arbiter120supplies a first arbitration signal (e.g., an arbitration signal GRANT that is at a high level or a logic “1”) to the second master114. However, when the second master114does not have the ownership of the bus118, the arbiter120supplies a second arbitration signal (e.g., an arbitration signal GRANT that is at a low level or a logic “0”) to the second master114.

The selection signal generation circuit220receives one of the first and second arbitration signals, and a signal from the mode information storage circuit210, and generates a selection signal SEL from a logic combination of the received signals. The selection signal generation circuit220may be, for example, an AND gate222as shown inFIG. 4.

If the second master114has the ownership of the bus118in synchronous data transfer mode, the selection signal SEL output from the selection signal generation circuit220is at a high level or a logic “1”. The selection circuit226receives a signal having a DC-level via a first input terminal (“0”) and a clock signal CLK via a second input terminal (“1”), and supplies the DC-level or the clock signal CLK to the memory device130, based on the selection signal SEL received from the selection signal generation circuit220. The selection circuit226may be, for example, a multiplexer as shown inFIG. 4.

The DC-level signal has a low level (a logic “0” or a ground voltage level), or a high level (a logic “1” or a supply voltage level). However, the DC-level signal in some embodiments has the low level, which may reduce the consumption of power in the second master114.

The second master114may further include the delay logic224that delays a clock signal CLK for a predetermined length of time. That is, the delay logic224receives a system clock signal SYS_CLK, and delays it for a predetermined time to generate the clock signal CLK. The delay logic224may allow data to be more easily exchanged between the second master114and the memory device130by adjusting a line delay between the second master114and the memory device130.

Referring now toFIG. 6, when the second master114has the ownership of the bus118in the synchronous data transfer mode, the second master114supplies the normal clock signal CLK to the memory device130. The data A, B, C, D, E, G, H, I, and J are supplied to the second master114in synchronization with a rising edge of the clock signal CLK. InFIG. 6, /AVD denotes address valid detect. During a synchronous read operation, while /AVD remains low for a clock cycle, all of the addresses are latched at a rising edge of the clock signal CLK. /CE denotes a chip enable signal.

When the second master114loses the ownership of the bus118in the synchronous data transfer mode, the second master114supplies the DC-level signal to the memory device130. As illustrated inFIG. 6, while the DC-level signal is supplied to the memory device130, the data C and/or H that is output (or will be output) from the second master114to the memory device130or vice versa, is maintained at a constant logic level until the second master114regains the ownership of the bus118. In other words, the data C and/or H are held. In other words, while the second master114does not use the bus118, it does not supply the clock signal CLK to the memory device130, which may greatly reduce the consumption of power in the second master114and/or the memory device130.

FIG. 5is a block diagram of the second master114according to further embodiments of the present invention. Referring toFIG. 5, the illustrated embodiments differ from those ofFIG. 4discussed above in that the second master114further includes a clock signal generator300that generates a clock signal SYS_CLK.

Referring toFIGS. 5 and 6, when the second master114has the ownership of the bus118in the synchronous data transfer mode, it supplies a normal clock signal CLK to the memory device130ofFIG. 3. However, when the second master114loses the ownership of the bus118in the synchronous data transfer mode, the second master114supplies a DC-level signal to the memory device130. If the second master114regains the ownership of the bus118in the synchronous data transfer mode, the second master114supplies the normal clock signal CLK to the memory device130.

Although not shown, the second master114in some embodiments includes a direct memory access (DMA). A method of setting the DMA will now be described. First, an address of the second slave124at which data will be read or write is written to an initial address register (not shown) of the second master114. An address of the memory device130at which data will be read or write is written to a memory device initial address register (not shown) of the second master114. The size of data to be transmitted is written to a data counter register (not shown) of the second master114, using the DMA, a direction of data transmission (a write/read operation) is set in a control register (not shown) of the second master114, a synchronous read/write operating latency is set, and the DMA is executed.

FIG. 7is a flowchart illustrating a method of outputting a clock signal according to some embodiments of the present invention. Referring toFIGS. 3 through 7, a method of supplying the clock signal CLK will now be described. In the synchronous data transfer mode (or in a synchronous burst read/write mode), data is transmitted from the memory device130to the controller110or vice versa, in synchronization with the clock signal CLK (S101). In the synchronous data transfer mode, the second master114determines whether the second master114has the ownership of the bus118, based on one of first and second arbitration signals received from the arbiter120(S120). If the second master114has the ownership of the bus118, the second master114supplies the normal clock signal CLK to the memory device130(S140). However, if the second master114loses the ownership of the bus118in the synchronous data transfer mode (S120), the second master114supplies a DC-level signal to the memory device130(S130). The second master114may effectively exchange a large amount of data with the memory device130by continuously performing operations S120, S130, and S140.

As described above, a controller according to some embodiments of the present invention controls a clock signal, prevents the clock signal from being supplied to a memory device when data transmission is not allowed in the synchronous data transfer mode and may thereby intercept an unnecessary operation of the memory device. As the supply of the clock signal to the memory device is blocked, it may be possible to reduce unnecessary consumption of power in the controller and the memory device, based on the toggled clock signal.

In some embodiments, even if a situation that interrupts data transmission occurs during transmission of the data to the memory device and then ends, there is no need to reset the controller and/or a system including the controller, which may limit or even prevent degradation of the performances of the controller and the system. Some embodiments of the present invention provide a controller and method for preventing a clock signal from being supplied to a memory device when the controller cannot transmit data to the memory device, and a system including the controller.