Memory command interleaving

Various embodiments described herein provide for grouping read-modify-writes (RMWs) such that multiple RMW command sequences can be executed (or rearranged in the command queue) in an interleaved manner rather than being executed in order. In particular, various embodiments described herein split the read and write components (commands) of multiple RMW command sequences, group the read components in the command queue to execute consecutively, and group the write components in the command queue to execute consecutively.

TECHNICAL FIELD

Embodiments described herein relate to memory and, more particularly, to systems, methods, devices, and instructions for interleaving memory commands of memory transactions, such as a read-modify-write transaction.

BACKGROUND

Memory controllers are generally circuits dedicated to controlling and managing the flow of data written to and read from one or more memory devices. They may be suitably formed as separate devices or integrated with a central processing unit or other main controller, and serve the memory storage and access needs of various software application operations. Memory controllers implement the logic to read from and write to various types of memory devices, examples of which include dynamic random access memory (DRAM), as well as electrically programmable types of non-volatile memory such as flash memory, and the like.

To minimize the consequences of data corruption due to random sources of error, various error checking measures for detection and/or correction are employed in the art for the storage and retrieval of data from memory devices. One example of the various known measures is the use of an Error Correcting Code (ECC) feature for detection or correction of error in data words read from one or more memory devices. An ECC feature is usually used in memory controllers for computing devices that are particularly vulnerable to data corruption, or for computing devices involved in high data rate or other applications where substantial immunity to data corruption is particularly important. ECC features generally involve adding redundant ECC bits to a transmitted data segment (e.g., transmitted to a memory device) according to a predetermined code (of a selected ECC format). These ECC bits are of parity-type and permit the data segment to be properly recovered at the receiving end (by a receiving/recovery method suitably configured for the given ECC format), even if certain correctable errors were introduced in the transmission or storage of that data segment. The degree to which the errors are correctable would depend on the relevant properties of the particular code being used.

Memory controllers generally transmit, receive, and store data words, and a data word format may be defined by a multiple number of bytes. The multiple data bytes of each data word may be stored in a memory device formed by a plurality of integrated circuit chips, and each data byte may be stored in a different selectable chip of the memory device at the same relative address within each selectable chip.

Some memory controllers are configured for storage of such ECC-protected data according to a sideband ECC storage scheme (or format). A sideband scheme for storing ECC and data bits usually provides for an additional chip (e.g., an ECC chip) in which the ECC byte associated with a given data word's data bytes is exclusively stored. The data word's ECC byte is then stored much like its data bytes—at the same intra-chip address as those data bytes, but in its dedicated sideband ECC chip. For example, in some ECC-protected memory controller applications, a data word may be defined by 72 total bits, segmented into eight 8-bit data bytes and one 8-bit ECC byte (one ECC bit for each of the eight 8-bit data bytes). For such an example (a 72-bit data word formed by 8 data bytes plus 1 ECC byte), the data word is stored across nine selectable chips—eight selectable chips for the data bytes and one selectable chip for the associated ECC byte. Under the sideband ECC storage scheme, memory transactions for reading and writing data to and from memory devices contemplate and support sideband storage of ECC bytes with their associated data bytes (e.g., data words).

Other memory controllers may use a non-sideband ECC memory storage scheme, such as an ECC storage scheme (or format) where ECC-protected bytes are stored inline (along) with their ECC bytes in one or more of chips available on a given memory device. For example, under an inline ECC storage scheme, a portion of the memory storage locations available on a chip of a memory device may be allocated for primary data bytes and the remainder allocated for ECC bytes so that the ECC bytes are stored inline with the primary data bytes. Additionally, a memory controller implementing an inline ECC storage scheme may adapt a memory transaction for inline storage configurations, where different portions of given data words are stored at different intra-chip addresses. In this way, available memory device chips may be shared for data and ECC bit storage according to a wide range of memory space configurations depending on such factors as data word size, the number and layout of available storage cells, and the like. An inline ECC storage scheme may be utilized when ECC protection for memory transactions exists but a memory device is not adequately equipped or configured to support sideband storage of ECC bytes. For example, an inline ECC storage scheme (or feature) can provide ECC protection similar to a sideband ECC memory storage scheme without the sideband ECC memory storage scheme's need to widen the memory data path between a memory controller and a memory device to communicate ECC on dedicated pins alongside memory data (e.g., a 9-byte wide memory interface where 8 bytes of the memory are data and 1 byte is the ECC for the 8 bytes of data).

DETAILED DESCRIPTION

Relative to a memory burst transaction, misaligned and undersized writes are typically converted by a memory controller to cause a read-modify-write command sequence (hereinafter, RMW), which can be a significant hindrance to performance of a memory system. Generally, a RMW requires a memory read from a memory, the read data is stored, the write data is merged, and then the new merged write data is written back to the memory. RMW can be further complicated when coupled with error checking data (e.g., ECC data) since error checking data would be calculated on the merged data. Based on the performance factor of turnaround between read operations to write operations, tWTR (write to read turn-around) for conventional random access memory (e.g., DRAM) can be very large for RMWs (e.g., on the order of 15 ns), and in future memories, the tWTR delay is projected to increase (e.g., by 3 times, also referred to as 3×tWTR).

Furthermore, compared to memory that use a sideband storage scheme for error checking data (e.g., ECC data), memory operations for memory that store primary data inline with error checking data may generate more RMW traffic, particularly due to the additional memory operations used for the inline-stored error checking data. For example, for a memory that uses an inline storage scheme for error checking data, a write command may necessitate either an RMW for error checking data (e.g., RMW ECC transaction) or a masked write command since the associated ECC may not be an entire memory burst, while a RMW for primary data will also result in an RMW for error checking data.

Various embodiments described herein can reduce or avoid the turnaround delay (e.g., tWTR) between read operations to write operations for multiple RMWs, and can increase memory bus utilization over traditional memory systems.

According to some embodiments, RMWs are grouped such that multiple RMWs can be executed (or rearranged in the command queue) in an interleaved manner (e.g., RRRWWW) rather than being executed in order (e.g., order in which they are generated and placed in a command queue—RWRWRW). In particular, various embodiments described herein split the read and write components (commands) of multiple RMWs, group the read components in the command queue to execute consecutively, and group the write components in the command queue to execute consecutively. Doing so can allow several RMWs to be executed as groups of read commands followed by groups of write commands, which can minimize the bus turnaround occurrences and effectively reduce the inefficiency associated with tWR. This is unlike traditional memory systems and controllers, which cause RMW transactions to be run in order and do not permit interleaving of RMW transactions.

Since the read and write of a given RMW operates on the same data, various embodiments store (and thus utilize storage for) multiple commands worth of data. According to some embodiments, a read-modify-write (RMW) buffer from a plurality of RMW buffers (e.g., 8 to 16 RMW buffers) is allocated for each RMW write command in the group of write commands (or alternatively for each RMW read command in the group of read commands) in the command queue.

Additionally, for a memory that uses an inline storage scheme for error checking data (e.g., ECC data), an embodiment may store (and thus utilize storage for) multiple commands worth of error checking data (e.g., ECC data). According to some embodiments, an error checking data buffer from a plurality of error checking data buffers (e.g., 8 to 16 error checking data buffers) is allocated for each error checking data (e.g., ECC) write command in the group of write commands (or alternatively for each error checking data (e.g., ECC) read command in the group of read commands) in the command queue.

Furthermore, various embodiments described herein use a watermarking technique or mechanism to track the number of RMWs that are currently in a command queue, which can permit an embodiment to maximize the interleaving while also adhering to a limitation of the storage available to a particular memory system (e.g., limited availability of RMW buffers, error checking data buffers, or both). For instance, some embodiments allow N RMWs to be interleaved, where N is the number of RMW buffers available for use. The N number of RMW buffers may be configured by a user and may be adjusted to optimize the trade-off between storage area and performance. For some embodiments, if N is exceeded, a watermark (also referred to as a RMW watermark) is used to start a new group of interleaved transactions, thereby ensuring that the RMW buffers are not overflowed and continue to perform optimally.

For a memory that uses an inline storage scheme for error checking data (e.g., ECC data), some embodiments include management of RMW buffers and error checking data buffers to prevent over-allocation of resources for read-modify-write interleaving (e.g., the maximum number of interleaved RMWs exceeding the number of RMW buffers available). For some embodiments, RMW buffers are dedicated for storing primary data and error checking data buffers are dedicated for storing error checking data for the primary data.

For some embodiments, to support read-modify-write interleaving (e.g., for both primary data and error checking data commands), a memory controller limits the number of concurrent RMWs within interleaved groups to prevent over-allocation of the limited resources (e.g., buffers). Some embodiments count the number of RMW-write commands (or RMW-read commands) in the current RMW group and set a watermark (e.g., watermark bit) when a limit is reached. For some embodiments, the number of RMWs for primary data that can be in progress at a given time is limited by the number of RMW buffers. Additionally, where a memory uses an inline configuration for storing error checking data with primary data, the number of RMWs for error checking data that can be in progress at a given time can be limited by the number of error checking data (e.g., ECC) buffers. For a memory that uses an inline configuration for storing error checking data with primary data, each primary data RMW may result in an error checking data RMW.

For RMW interleaving, primary data fetched by a RMW-read command may be stored in one of the RMW buffers until the associated RMW-write command is executed. Once stored to a RMW buffer, write data for the RMW may be merged with the primary data stored in the RMW buffer, and the RMW-write command may be executed. The number of error checking data (e.g., ECC) RMWs may be limited programmatically to limit the number of error checking data buffers that can be allocated to RMWs.

According to some embodiments, a counter is used to track (e.g., sum) the total number of RMWs (e.g., specifically, RMW-write commands) to determine if a maximum number of interleaved RMWs supported (e.g., by the number of RMW buffers) has been reached or exceeded. For a memory that stores error checking data inline with primary data, the counter may count error checking data (e.g., ECC) RMW-write commands, which may be beneficial for embodiments where an error checking data RMW-write command may exist without a primary data RMW-write command but not the other way around. For a memory that uses non-inline configuration for storing error checking data (e.g., sideband configuration), the counter may count primary data RMW-write commands.

For some embodiments, if a maximum number of interleaved RMWs has been reached or exceeded, a RMW watermark (e.g., watermark bit) is set for entries currently in a command queue for RMW commands (e.g., for all RMW-write command entries currently in the command queue). For various embodiments, a watermark is set for all entries in a command queue since the RMW commands may be executed out-of-order.

According to some embodiments, a watermark is set (e.g., watermark bit is set with respect to an entry in a command queue) when a new RMW command sequence is being placed. In this way, the maximum condition can be resolved prior to a next RMW command sequence being placed rather than immediately setting the watermark when the next RMW command sequence may not follow immediately. Additionally, for some embodiments, the count is when an RMW-read command of a given RMW is being placed, given that the RMW-read command precedes a RMW-write command of the given RMW.

According to some embodiments, a watermark bit is included by each entry in a command queue for use by RMW interleaving operations as described herein. A watermark bit may be set for a given entry in the command queue having an RMW-command (e.g., RMW-write command for primary data or error checking data) when an embodiment detects that a maximum number of interleaved RMW (e.g., RMW-write commands) has been reached or exceeded. The watermark bit of the given entry in the command queue may be cleared when the associated command (e.g., RMW write command for primary data or error checking data) is popped for execution.

Though various embodiments are described herein with respect to memory that store primary data inline with error checking data (e.g., ECC data), other embodiments enable interleaving of RMWs for memory that use a non-inline configuration for error checking data (e.g., memory that use sideband storage of error checking data).

As used herein, for a given RMW command sequence, a RMW-read command refers to a read command of the given RMW command sequence and a RMW-write command refers to a write command of the given RMW command sequence. A primary data RMW may refer to a RMW command sequence that operates on primary data stored on a memory, while an error checking data (e.g., ECC) RMW may refer to a RMW command sequence that operates on error checking data stored on a memory (e.g., error checking data stored inline with primary data as described herein). Accordingly, a primary data RMW-read command refers to a read command in a RMW command sequence for primary data, a primary data RMW-write command refers to a write command in a RMW command sequence for primary data, an error checking data (e.g., ECC) RMW-read command refers to a read command in a RMW command sequence for error checking data (e.g., ECC), and an error checking data (e.g., ECC) RMW-write command refers to a write command in a RMW command sequence for error checking data (e.g., ECC).

As used herein, primary data may refer to data that is stored or will be stored on a memory and that is intended to be checked or protected by error checking data. Error checking data for primary data can include ECC data.

As used herein, inline primary data addresses refer to memory addresses of a memory that correspond to those segments of the memory that store primary data on the memory. Inline error checking data addresses refer to memory addresses of a memory that correspond to those segments of the memory that store error checking data on the memory.

As used herein, an error checking data address range (e.g., ECC address range) may include all inline error checking data addresses associated with (e.g., that map to) a primary data memory transaction with respect to a range of inline primary data addresses on a memory. For example, an ECC address range with respect to a memory may include all inline error checking data addresses that correspond to error checking data, on the memory, associated with a plurality of primary data memory burst transactions. For instance, with a primary data-to-ECC ratio of 8 to 1, an ECC address range may be associated with a single memory burst worth of ECC data on a memory that covers8memory bursts worth of primary data on the memory.

As used herein, an error checking data address range boundary determines when one error checking data address range ends and another error checking data address range begins.

As used herein, an error checking data buffer (e.g., ECC data buffer) may comprise a single storage element that will store a single memory burst reading of error checking data (e.g., ECC data) stored on a memory. For example, the data size of an electronic checking data buffer would be 32 bytes where a single memory burst reading of error checking data results in 32 bytes of electronic checking data being read from the memory. Some embodiments use a plurality of error checking data buffers, where each error checking data buffer may be managed independently.

As used herein, a memory burst command/operation (or burst mode memory command/operation) may refer to a command/operation that results in repetitious transmission of data a predetermined number of times to result in a memory data path width (DP) times burst length (BL) worth of data, without need to transmit each piece of data in a separate transaction (e.g., a single memory burst read command for a typical central processing unit (CPU) fetches a cache line worth of data). For example, where a memory burst command/operation has a burst length of 16 (BL=16) and a 16-bit data path width (DP=16), a single burst command will result in transmission of 256-bits (32 bytes) of data by a single memory transaction, rather than multiple separate memory transactions (e.g., 16 separate 16-bit memory transactions). Accordingly, a memory burst read command/operation performed with respect to a memory can result in the reading (e.g., fetching) of a predetermined number of data words stored on the memory, and a memory burst write command/operation performed with respect to a memory can result in the writing of a predetermined number of data words to the memory. A data word can include a predetermined number of bytes (e.g., 8 bytes for a 64-bit data word).

Reference will now be made in detail to embodiments of the present disclosure, examples of which are illustrated in the appended drawings. The present disclosure may, however, be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein.

FIG. 1is a block diagram illustrating an example electronic device100that includes a memory controller106with error checking data caching, in accordance with various embodiments. The electronic device100may comprise any electronic device that uses a memory and a processor, such as a CPU or a graphics processing unit (GPU). For instance, the electronic device100may comprise, without limitation, a computer (e.g., a server computer, a client computer, a personal computer (PC), a tablet computer, a laptop computer, a netbook), a set-top box (STB), a personal digital assistant (PDA), an entertainment media system, a cellular telephone, a smart phone, a mobile device, a wearable device (e.g., a smart watch), a smart home device (e.g., a smart appliance), other smart devices, a web appliance, a network router, a network switch, a network bridge, or any electronic device capable of executing instructions with respect to a memory.

As shown, the electronic device100includes a memory102, a memory datapath104, and the memory controller106, which performs error checking data caching operations, in accordance with various embodiments. Any one or more of the components described may be implemented using hardware (e.g., one or more circuits) alone or a combination of hardware and software. Moreover, any two or more components of the electronic device100may be combined into a single component, and the functions described herein for a single component may be subdivided among multiple components.

To avoid obscuring illustrated embodiments with unnecessary detail, various functional components that are not germane to conveying an understanding of the illustrated embodiments have been omitted fromFIG. 1. Various additional functional components may be supported by the electronic device100to facilitate additional functionality that is not specifically described herein.

The memory102comprises one or more memory cells or memory devices, each of which may comprise some form of random access memory (RAM), such as Dynamic Random-Access Memory (DRAM) or Static Random-Access Memory (SRAM). The memory102may be packaged as a single in-line memory module (SIMM) or a dual in-line memory module (DIMM) that can be plugged into an electronic device including an appropriate socket. For some embodiments, the memory102comprises Double Data Rate (DDR) Synchronous Dynamic Random-Access Memory (SDRAM), such as Double Data Rate 3 (DDR3), Double Data Rate 4 (DDR4), Low Power Double Data Rate 3 (LPDDR3), or Low Power Double Data Rate 4 (LPDDR4).

The memory datapath104comprises one or more electronic signal paths coupling together the memory102and the memory controller106(e.g., individual lines between pins of the memory102and the memory controller106) such that data, address, command, control, clock, and other information can be carried between the memory102and the memory controller106. For example, the memory datapath104may comprise an interconnect, such as a link or a bus. Accordingly, the memory datapath104may carry one or more electronic signals between the memory102and the memory controller106. Among the electronic signals carried, the memory datapath104may carry one or more data signals for data to be written to, or read from, the memory102(e.g., a memory device of the memory102). Additionally, the memory datapath104may carry one or more control signals, which can facilitate writing data to, or reading data from, the memory102(e.g., a memory device of the memory102).

The memory controller106manages exchange of data to and from the memory102via the memory datapath104. To facilitate this, the memory controller106may exchange data, address, command, control, clock, and other information with the memory102over the memory datapath104.

As shown, the memory controller106includes a command queue component110and buffers112. The command queue component110may store a plurality of memory commands (generated by the memory controller106) for timely execution by the memory controller106. Each of the buffers112may comprise a register or SRAM. Each of the buffers112may have a buffer identifier (ID), and may be managed independently of each other.

According to some embodiments, the buffers112include a plurality of RMW buffers, which are used for RMW interleaving operations as described herein. In particular, for some embodiments, the RMW buffers of the buffers112are used to interleave RMW command sequences operating on primary data stored on the memory102.

According to some embodiments, where primary data is stored in line with error checking data on the memory102, the buffers112include a plurality of error checking data (e.g., ECC) buffers, which are used for interleaving RMW command sequences operating on error checking data stored on the memory102. To implement inline storage of primary data with error checking data on the memory102, the memory controller106may use split addressing to generate memory commands for memory transactions with respect to the memory102, and thereby cause primary data to be stored inline with error checking data generated for the primary data on the memory102. With the inline storage configuration, the primary data may be stored on the memory102at a range of inline data addresses, and the error checking data may be stored on the memory102at a range of inline error checking data addresses, where the range of inline primary data addresses does not overlap with (is disjointed with respect to) the range of inline error checking data addresses.

According to various embodiments, the memory controller106facilitates interleaving of RMWs by placing commands in the command queue maintained by the command queue component110and by managing RMW buffers of the buffers112. For instance, when a new RMW command sequence (for primary data or error checking data) is ready for placement by the memory controller106on the command queue, the memory controller106can analyze the command queue for RMW command sequences. Based on the analysis of the command queue, the memory controller106may place, in the command queue, a read command of the new RMW command sequence as part of a read-modify-write (RMW) group of consecutive read commands, and place, in the command queue, a write command of the new RMW command sequence as part of a RMW group of consecutive write commands. With respect to placement, the RMW group consecutive read commands may be placed in the command queue to execute prior to the RMW group of consecutive write commands.

In particular, analyzing the command queue (maintained by the command queue component110) for read-modify-write command sequences can comprise the memory controller106determining whether a predetermined maximum number of read-modify-writes has been reached or exceeded. Accordingly, the memory controller106may place the read command of the new RMW command sequence as part of the read-modify-write group of consecutive read commands and place the write command of the new RMW command sequence as part of the read-modify-write group of consecutive write commands, in response to determining that the predetermined maximum number of read-modify-writes has been reached or exceeded. Additionally, the memory controller106may allocate a RMW buffer, from the buffers112, for the read command of the new RMW command sequence in response to determining that the predetermined maximum number of read-modify-writes has been reached or exceeded, which the read command may then utilize during its subsequent execution. According to some embodiments, the memory controller106may allocate a RMW buffer, from the buffers112, for each read command in the read-modify-write group of consecutive read commands.

For some embodiments, where primary data is stored inline with error checking data on the memory102, a primary data RMW command sequence is accompanied by an error checking data RMW command sequence. Accordingly, the memory controller106may allocate an error checking data buffer, from the buffers112, for the error checking data RMW command sequence (e.g., a read command of error checking data RMW command sequence) in response to determining that the predetermined maximum number of read-modify-writes has been reached or exceeded.

In response to determining that the predetermined maximum number of read-modify-writes has been reached or exceeded, the memory controller106may set a watermark bit in the command queue maintained by the command queue component110. In particular, the memory controller106may set a watermark bit with respect to an entry in the command queue associated with at least a last write command (e.g., all last write commands) in the read-modify-write group of consecutive write commands. For embodiments where primary data is stored inline with error checking data on the memory102, and a primary data RMW command sequence is accompanied by an error checking data RMW command sequence, the watermark may be set with respect to both primary data RMW-write commands and error checking data RMW-write commands.

The memory controller106may determine whether the predetermined maximum number of read-modify-writes has been reached or exceeded based on a counter that the memory controller106maintains for tracking a number of write commands in the read-modify-write group of consecutive write commands. For embodiments where primary data is stored inline with error checking data on the memory102, and a primary data RMW command sequence is accompanied by an error checking data RMW command sequence, the counter maintained by the memory controller106may track primary data RMW-write commands (rather than error checking data RMW-write commands) in the read-modify-write group of consecutive write commands.

In response to determining that the predetermined maximum number of read-modify-writes has been reached or exceeded, the memory controller106may place a subsequent RMW command sequence in the command queue maintained by the command queue component110such that the subsequent RMW command sequence executes after execution of the read-modify-write group of consecutive write commands. For some embodiments, the memory controller106does this by placing the subsequent RMW command sequence in the command queue behind a last entry in the command queue having a set watermark bit.

For new RMW command sequences that occur while the predetermined maximum number of read-modify-writes remains reached or exceeded, the new RMW command sequences may be split into their read and write components and grouped into a new RMW group of consecutive read commands and a new RMW group of consecutive write commands that are placed behind a last entry in the command queue having a set watermark bit. Accordingly, in response to determining that the predetermined maximum number of read-modify-writes has been reached or exceeded, the memory controller106may: place, in the command queue, a read command of a new RMW command sequence as part of a second group of consecutive read commands that is behind a last entry in the command queue having a set watermark bit; and place, in the command queue, a write command of the new RMW command sequence as part of a second group of consecutive write commands that is also behind the last entry in the command queue having the set watermark bit.

FIG. 2is a schematic diagram illustrating an example memory system200that includes an example memory controller204with interleaving of RMW command sequences, in accordance with some embodiments. As shown, the memory controller204can serve to provide control of a memory208(formed by one or more memory devices of any suitable type and configuration known in the art), which can support processing of a master control operation by a master controller (not shown). The memory controller204may communicate with a master controller through one or more user interface ports202, and with the memory device(s) of the memory208through a physical interface (PHY)206, which may be configured with a suitable interface standard known in the art for the memory208.

The memory system200illustrated inFIG. 2may be implemented in any known form, depending on the particular requirements of an intended application. For instance, the memory system200may be realized by discretely interconnected subsystems, or sufficiently integrated in the form of a system-on-chip (SOC) or the like, depending on the particular requirements of the intended application. As the user interface ports202, the PHY206, and the memory208may be of any suitable type and configuration known in the art, subject to the particular requirements of a given application, no further description is needed for description of features relating to the memory system200.

InFIG. 2, the memory system200includes a command control portion220, an error control portion222, and a data control portion224. In some embodiments, the data control portion224includes one or more digital circuits that implement functional logic to carry out a plurality of primary data access operations/commands on the memory208. Such primary data access operations/commands may include, without limitation, read, write, masked write, and RMW operations/commands conducted on selectively addressed storage locations defined in the memory208. The primary data access operations may include control of additional functions for proper interface with the particular type of memory device(s) employed in the memory208.

For some embodiments, the error control portion222includes one or more digital circuits that implement functional logic for detecting and correcting errors in data segments as stored in memory208. The error control portion222can include execution of error checking data processing, such as ECC processing of predetermined code format (e.g., a format of SECDED type), to detect errors in a corrupted primary data segment read from the memory208. The error control portion222is configured to correct the primary data segment read from the memory208having an error that is correctable with the given error checking data (e.g., ECC), and report (e.g., for the master control operation) those primary data segment errors which are detected but are not correctable with the given error checking data. The error control portion222can also provide intermediate storage of error checking data (e.g., ECC) bytes generated or read in association with primary data bytes during the execution of various primary data access operations, for cooperative transmission with their primary data bytes either to the PHY206(for writing operations) or error-checking of retrieved primary data for return to the user interface ports202(for reading operations).

The command control portion220may be coupled to both the error control and data control portions222,224. For some embodiments, the command control portion220includes one or more digital circuits that implement functional logic for generating commands to actuate various primary data access operations of the data control portion224. The command control portion220may include one or more suitable units for carrying out memory access operations responsive to memory transactions of user applications involving error checking data-protected data words. For example, where inline storage of error checking data is implemented, the command control portion220may include address translation and command translation functions involved in adaptively splitting the memory addressing of error checking data (e.g., ECC data) and primary data, which facilitates inline storage of primary data with associated error checking data.

As shown, the command control portion220includes a RMW interleaving logic230that implements RMW interleaving operations described herein. In particular, during placement of RMW command sequences by the command control portion220in a command queue (not shown), the RMW interleaving logic230can cause the command control portion220to split the read and write components of a RMW command sequences, group the read components in the command queue to execute consecutively, and group the write components in the command queue to execute consecutively.

FIG. 3is a diagram illustrating an example command queue302, example error checking data buffers304, and example RMW buffers306of a memory system that stores primary data inline with error checking data and that interleaves RMW command sequences, in accordance with some embodiments. As shown, with respect to the command queue302, the memory system maintains a count (CNT)310of RMW-write commands in a current RMW group in the command queue302, a watermark (WM) bit312for each entry of the command queue302, and a mask bit (MASK)314for each entry of the command queue302. As also shown, the command queue302has a depth of 16 commands and the error checking data buffers304includes 8 buffers.

The contents of the command queue302and the error checking data buffers304reflect operation of the memory system, using RMW interleaving of an embodiment described herein, based on a maximum RMW limit of 4 and the following incoming command order: RD0 (read #0), RD1, WR0 (write #0), WR1, RMW0 (read-modify-write #0), RMW1, RD2, RD3, RD4, WR2, WR3, WR4, RMW2, RMW3, RMW4, RD5, RD6, WR5, and WR6. In summary, during operation of the memory system, commands RD0 and RD1 pass through the command queue302, are selected for execution, and cause allocation of error checking data buffers from error checking data buffers304. Commands WR0 and WR1 pass through the command queue302, are selected for execution, and cause allocation of error checking data buffers from error checking data buffers304.

Command sequences RMW0 and RMW1 are split and their read and write commands grouped in the command queue302(first RMW group of consecutive read commands and first RMW group of consecutive write commands); RMW buffers from the RMW buffers306are allocated for each of RMW-R0 and RMW-R1; and RMW-R0 and RMW-R1 are placed ahead of the first RMW group of consecutive write commands (i.e., RMW-W0 and RMW-W1) in the command queue302. Eventually, commands RMW-R0 and RMW-R1 pass through the command queue302and are selected for execution, which causes allocation of error checking data buffers from error checking data buffers304.

Commands RD2, RD3, and RD4 are placed in the command queue302behind RMW-R0 and RMW-R1. Eventually, commands RD2 and RD3 pass through the command queue302, are selected for execution, and allocated error checking data buffers from error checking data buffers304, thereby leaving RD4 currently at the top of the command queue302.

Commands WR2, WR3, and WR4 are placed in the command queue302behind RMW-W1 due to read/write ordering rules to minimize bus turn-arounds.

Command sequences RMW2 and RMW3 are split and their read and write commands grouped in the command queue302(first RMW group of consecutive read commands and first RMW group of consecutive write commands), and the watermark bit associated with RMW-W3 is set based on the maximum number of interleaved RMW being reached (i.e., CNT=0 since the group of RMW-R2 and RMW-R3 reserve the last two error checking data RMW buffers). Commands RMW-R2 and RMW-R3 are placed in the command queue302behind R4 due to read/write ordering rules to minimize bus turn-arounds, and RMW-W2 and RMW-W3 are placed behind W4 for the same reason.

Command sequence RMW4 is split and its read and write commands grouped in the command queue302(second RMW group of consecutive read commands and second RMW group of consecutive write commands). Command RMW-R4 cannot be placed behind RMW-R3 because the RMW buffers306have been fully allocated. Accordingly, RMW-R4 is placed behind RMW-W3 since it cannot be placed in the first RMW group of consecutive reads, it is placed behind the group of writes.

Commands RD5 and RD6 are be placed in the command queue302as part of the second RMW group of consecutive read commands, and commands WR5 and WR6 are be placed in the command queue302as part of the second RMW group of consecutive write commands.

FIG. 4is a flow diagram illustrating an example method400for interleaving RMW command sequences, in accordance with various embodiments. For some embodiments, the method400is performed by a memory controller of a memory system, such as the memory controller106described above with respect toFIG. 1. Though the steps of method400may be depicted and described in a certain order, the order in which the steps are performed may vary between embodiments. For example, a step may be performed before, after, or concurrently with another step. Additionally, the components described below with respect to the method400are merely examples of components that may be used with the method400, and other components may also be used in some embodiments.

As shown inFIG. 4, the method400begins at operation402, with the memory controller106evaluating placement of a RMW command sequence in a command queue maintained by the command queue component110, where evaluating placement of the RMW command sequence comprises determining whether a predetermined maximum number of read-modify-writes has been reached or exceeded. In particular, for some embodiments, determining whether the predetermined maximum number of read-modify-writes has not been reached or exceeded (at operation402) comprises determining whether the predetermined maximum number of read-modify-writes has not been reached or exceeded beyond any entry in the command queue that has a watermark bit set. The memory controller106may determine whether the predetermined maximum number of read-modify-writes has been reached or exceeded is based on a counter that tracks a number of write commands in the read-modify-write group of consecutive write commands. In particular, where a memory stores primary data inline with error checking data, the counter may track the number of primary data RMW-write commands in the read-modify-write group of consecutive write commands.

At decision operation404, in response to determining that the predetermined maximum number of read-modify-writes has not been reached or exceeded (at operation402), the method400continues to operation406. As noted above with respect to operation402, determining whether the predetermined maximum number of read-modify-writes has not been reached or exceeded may comprise determining whether the predetermined maximum number of read-modify-writes has not been reached or exceeded beyond any entry in the command queue that has a watermark bit set.

At operation406, the method400continues with the memory controller106placing, in the command queue, a first read command of the RMW command sequence as part of a read-modify-write group of consecutive read commands in the command queue. According to various embodiments, at operation406, the read-modify-write group of consecutive read commands in the command queue is placed behind all entries in the command queue that have a watermark bits set.

At operation408, the method400continues with the memory controller106placing, in the command queue, a first write command of the RMW command sequence as part of a read-modify-write group of consecutive write commands. According to various embodiments, at operation408, the read-modify-write group of consecutive write commands is placed in the command queue behind the read-modify-write group of consecutive read commands in the command queue.

For some embodiments, the memory controller106causes primary data to be stored inline with error checking data (generated for the primary data) on the memory component102using split addressing for memory transactions, where the primary data is stored on the memory at a range of inline primary data addresses and the error checking data is stored on the memory at a range of inline error checking data addresses. Based on a requested memory transaction, the memory controller106generates a first RMW command sequence for particular primary data and a second RMW command sequence for particular error checking data, where the particular error checking data is generated for the particular primary data. Accordingly, at operation406, the memory controller106may place, in the command queue, a first read command of the first RMW command sequence and a second read command of the second RMW command sequence as part of a read-modify-write group of consecutive read commands in the command queue. Additionally, at operation408, the memory controller106may place, in the command queue, a first write command of the first RMW command sequence and a second write command of the second RMW command sequence as part of a read-modify-write group of consecutive write commands.

At operation410, the method400continues with the memory controller106allocating a read-modify-write buffer for the RMW command sequence.

At decision operation404, in response to determining that the predetermined maximum number of read-modify-writes has been reached or exceeded (at operation402), the method400continues to operation412. At operation412, the method400continues with the memory controller106setting a watermark bit in the command queue. The memory controller106may set the watermark bit with respect to an entry in the command queue associated with at least a last write command in the read-modify-write group of consecutive write commands. According to various embodiments, the command queue can comprise two or more watermark bits that are set and, accordingly, setting a watermark bit in the command queue at operation412may represent a new watermark bit being set in the command queue.

At operation416, the method400continues with the memory controller106placing the RMW command sequence in the command queue such that the RMW command sequence executes after execution of the read-modify-write group of consecutive write commands In particular, the memory controller106may place the RMW command sequence in the command queue behind at least a last entry in the command queue having a watermark bit that is set. According to some embodiments, performing operation416comprises performing operations similar to one or more of operations406through408.

FIG. 5is a block diagram illustrating components of a machine500, according to some example embodiments, able to read instructions from a machine-readable medium (e.g., a machine-readable storage medium) and perform any one or more of the methodologies discussed herein. Specifically,FIG. 5shows a diagrammatic representation of the machine500in the example form of a system, within which instructions502(e.g., software, a program, an application, an applet, an app, a driver, or other executable code) for causing the machine500to perform any one or more of the methodologies discussed herein may be executed. For example, the instructions502include executable code that causes the machine500to execute the method400. In this way, these instructions502transform the general, non-programmed machine500into a particular machine programmed to carry out the described and illustrated method400in the manner described herein. The machine500may operate as a standalone device or may be coupled (e.g., networked) to other machines.

By way of non-limiting example, the machine500may comprise or correspond to a computer (e.g., a server computer, a client computer, a personal computer (PC), a tablet computer, a laptop computer, or a netbook), a mobile device, or any machine capable of executing the instructions502, sequentially or otherwise, that specify actions to be taken by the machine500. Further, while only a single machine500is illustrated, the term “machine” shall also be taken to include a collection of machines500that individually or jointly execute the instructions502to perform any one or more of the methodologies discussed herein.

The machine500may include processors504, memory506, a storage unit508, and I/O components510, which may be configured to communicate with each other such as via a bus512. In an example embodiment, the processors504(e.g., a central processing unit (CPU), a reduced instruction set computing (RISC) processor, a complex instruction set computing (CISC) processor, a graphics processing unit (GPU), a digital signal processor (DSP), an application specific integrated circuit (ASIC), a radio-frequency integrated circuit (RFIC), another processor, or any suitable combination thereof) may include, for example, a processor514and a processor516that may execute the instructions502. The term “processor” is intended to include multi-core processors504that may comprise two or more independent processors (sometimes referred to as “cores”) that may execute instructions contemporaneously. AlthoughFIG. 5shows multiple processors, the machine500may include a single processor with a single core, a single processor with multiple cores (e.g., a multi-core processor), multiple processors with a single core, multiple processors with multiple cores, or any combination thereof.

The memory506(e.g., a main memory or other memory storage) and the storage unit508are both accessible to the processors504such as via the bus512. The memory506and the storage unit508store the instructions502embodying any one or more of the methodologies or functions described herein. The instructions502may also reside, completely or partially, within the memory506, within the storage unit508, within at least one of the processors504(e.g., within the processor's cache memory), or any suitable combination thereof, during execution thereof by the machine500. Accordingly, the memory506, the storage unit508, and the memory of the processors504are examples of machine-readable media.

Communication may be implemented using a wide variety of technologies. The I/O components510may include communication components522operable to couple the machine500to a network524or devices526via a coupling528and a coupling530respectively. For example, the communication components522may include a network interface component or another suitable device to interface with the network524. In further examples, the communication components522may include wired communication components, wireless communication components, cellular communication components, near field communication (NFC) components, Bluetooth® components (e.g., Bluetooth® Low Energy), Wi-Fi® components, and other communication components to provide communication via other modalities. The devices526may be another machine or any of a wide variety of peripheral devices.

Modules, Components and Logic

Electronic Apparatus and System

Example embodiments may be implemented in digital electronic circuitry, in computer hardware, firmware, or software, or in combinations of them. Example embodiments may be implemented using a computer program product, for example, a computer program tangibly embodied in an information carrier, for example, in a machine-readable medium for execution by, or to control the operation of, data processing apparatus, for example, a programmable processor, a computer, or multiple computers.

FIG. 6is a diagram illustrating one possible design process flow for generating a circuit, including embodiments to implement a memory controller that supports interleaving of RMW command sequences as described herein, and in various embodiments, to integrate the memory controller with a larger integrated circuit comprising different design blocks. As illustrated, the overall design flow600includes a design phase610, a device fabrication phase620, a design verification phase630, and a device verification phase640. The design phase610involves an initial design input operation601where the basic elements and functionality of a device are determined, as well as revisions based on various analyses and optimization of a circuit design. This design input operation601is where instances of an EDA circuit design file are used in the design and any additional circuitry is selected. The initial strategy, tactics, and context for the device to be created are also generated in the design input operation601, depending on the particular design algorithm to be used.

In some embodiments, following an initial selection of design values in the design input operation601, timing analysis and optimization according to various embodiments occurs in an optimization operation611, along with any other automated design processes. One such process may be the automated design of a partitioned root search for error locator polynomial functions in RS FEC decoding. As described below, design constraints for blocks of a circuit design generated with design inputs in the design input operation601may be analyzed using hierarchical timing analysis, according to various embodiments. While the design flow600shows such optimization occurring prior to a layout instance612, such hierarchical timing analysis and optimization may be performed at any time to verify operation of a circuit design. For example, in various embodiments, constraints for blocks in a circuit design may be generated prior to routing of connections in the circuit design, after routing, during register transfer level (RTL) operations, or as part of a final signoff optimization or verification prior to a device fabrication operation622.

After design inputs are used in the design input operation601to generate a circuit layout, and any optimization operations611are performed, a layout is generated in the layout instance612. The layout describes the physical layout dimensions of the device that match the design inputs. This layout may then be used in the device fabrication operation622to generate a device, or additional testing and design updates may be performed using designer inputs or automated updates based on design simulation632operations or extraction, 3D modeling and analysis644operations. Once the device is generated, the device can be tested as part of device test642operations, and layout modifications generated based on actual device performance.

As described in more detail below, design updates636from the design simulation632, design updates646from the device test642or the 3D modeling and analysis644operations, or the design input operation601may occur after an initial layout instance612is generated. In various embodiments, whenever design inputs are used to update or change an aspect of a circuit design, a timing analysis and optimization operation611may be performed.

Although an overview of the inventive subject matter has been described with reference to specific example embodiments, various modifications and changes may be made to these embodiments without departing from the broader scope of embodiments of the present disclosure.

As used herein, the term “or” may be construed in either an inclusive or exclusive sense. The terms “a” or “an” should be read as meaning “at least one,” “one or more,” or the like. The use of words and phrases such as “one or more,” “at least,” “but not limited to,” or other like phrases shall not be read to mean that the narrower case is intended or required in instances where such broadening phrases may be absent.