Memory device and method for fabricating the same

A method for fabricating a memory device is provided. The method includes forming a bottom electrode layer over a substrate; forming a buffer layer over the bottom electrode layer; performing a surface treatment to a top surface of the buffer layer; depositing a resistance switch layer over the top surface of the buffer layer after performing the surface treatment; forming a top electrode over the resistance switch layer; and patterning the resistance switch layer into a resistance switch element below the top electrode.

BACKGROUND

In integrated circuit (IC) devices, resistive random access memory (RRAM) is an emerging technology for next generation non-volatile memory devices. RRAM is a memory structure including an array of RRAM cells each of which stores a bit of data using resistance values, rather than electronic charge. Particularly, RRAM cell includes a resistance switch layer, the resistance of which can be adjusted to represent logic “0” or logic “1.”

DETAILED DESCRIPTION

Resistive random-access memory (RRAM) devices have a bottom electrode that is separated from an overlying top electrode by a dielectric data storage layer having a variable resistance. RRAM devices are configured to store data based on a resistive state of the dielectric data storage layer. For example, the dielectric data storage layer may have a high resistance state associated with a first data state (e.g., a ‘0’) or a low resistance state associated with a second data state (e.g., a ‘1’).

During operation of an RRAM device, bias voltages are applied to the bottom and top electrodes to reversible change a resistive state of the dielectric data storage layer. The bias voltages change the resistive state of the dielectric data storage layer by controlling the movement of oxygen between the electrodes and the dielectric data storage layer to either form or break conductive filaments extending through the dielectric data storage layer. For example, a first set of bias voltages may induce conductive paths/filaments (e.g., chains of oxygen vacancies) to form across the dielectric data storage layer to achieve a low resistance state, while a second set of bias voltages may break conductive paths/filaments within the dielectric data storage layer to achieve a high resistance state.

It has been appreciated that when forming a conductive filament to achieve a low resistive state, the bias voltages may cause oxygen from the dielectric data storage layer to move to deep within a top electrode and/or within an overlying layer. However, if oxygen moves far away from the dielectric data storage layer, it can be difficult to pull the oxygen back to dielectric data storage layer to subsequently break the conductive filament. As an RRAM device is operated over many cycles, the amount of oxygen moved to deep within the top electrode and/or the overlying layer increases, which in turn will damage the dielectric data storage layer and result in hard reset bit (HRB) issue, eventually leading to RRAM failure.

Embodiments of the present disclosure relates to a RRAM device having a dielectric data storage layer formed over a treated surface, in which the treated surface has an increased amount of oxide vacancies. By increasing the amount of oxide vacancies of the surface, the amount of oxide vacancies in the dielectric data storage layer is increased, such that the oxygen can be kept close to the dielectric data storage layer and a reliability of the RRAM device can be improved.

A RRAM device and the method of forming the same are provided in accordance with various exemplary embodiments. The intermediate stages of forming the RRAM device are illustrated. The variations of the embodiments are discussed. Throughout the various views and illustrative embodiments, like reference numbers are used to designate like elements.

FIGS.1-8illustrate various stages in the formation of a memory device according to some embodiments of the present disclosure. The illustration is merely exemplary and is not intended to limit beyond what is specifically recited in the claims that follow. It is understood that additional operations may be provided before, during, and after the operations shown byFIGS.1-8, and some of the operations described below can be replaced or eliminated for additional embodiments of the method. The order of the operations/processes may be interchangeable.

FIG.1illustrates a semiconductor substrate having transistors and one or more metal/dielectric layers110thereon. The semiconductor substrate may be a silicon substrate. Alternatively, the substrate may include another elementary semiconductor, such as germanium; a compound semiconductor including silicon carbide; an alloy semiconductor including silicon germanium; or combinations thereof. In some embodiments, the substrate is a semiconductor on insulator (SOI) substrate. The substrate may include doped regions, such as p-wells and n-wells. The transistors are formed by suitable transistor fabrication processes and may be a planar transistor, such as polysilicon gate transistors or high-k metal gate transistors, or a multi-gate transistor, such as fin field effect transistors. After the transistors are formed, one or more metal/dielectric layers110of a multi-level interconnect (MLI) is formed over the transistors.

The metal/dielectric layer110includes one or more conductive features112embedded in an inter-layer dielectric (ILD) layer114. The ILD layer114may be silicon oxide, fluorinated silica glass (FSG), carbon doped silicon oxide, tetra-ethyl-ortho-silicate (TEOS) oxide, phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), Black Diamond® (Applied Materials of Santa Clara, Calif.), amorphous fluorinated carbon, low-k dielectric material, the like or combinations thereof. The conductive features112may be aluminum, aluminum alloy, copper, copper alloy, titanium, titanium nitride, tantalum, tantalum nitride, tungsten, cobalt, the like, and/or combinations thereof. The substrate may also include active and passive devices, for example, underlying the metal/dielectric layers110. These further components are omitted from the figures for clarity.

Bottom electrode vias (BEVA)130are formed in the dielectric layer120. An exemplary formation method of the BEVAs130includes etching an opening O1in the dielectric layer120and exposing a portion of the conductive feature112, and filling the opening O1with suitable conductive materials, thereby forming the BEVA130. In some embodiments, after filling the opening O1with the materials, a planarization process, such as a chemical-mechanical polish (CMP) process, is performed to remove excess conductive materials outside the opening O1. In some embodiments, the BEVA is electrically connected to an underlying electrical component, such as a transistor, through the conductive feature112.

In some embodiments, the BEVA130is a multi-layered structure and includes, for example, a diffusion barrier layer and a filling metal filling a recess in the diffusion barrier layer. In some embodiments, the diffusion barrier layer is a titanium nitride (TiN) layer or a tantalum nitride (TaN) layer, which can act as a suitable barrier to prevent metal diffusion. Formation of the diffusion barrier layer may be exemplarily performed using CVD, PVD, ALD, the like, and/or a combination thereof. In some embodiments, the filling metal is titanium (Ti), tantalum (Ta), platinum (Pt), ruthenium (Ru), tungsten (W), aluminum (Al), copper (Cu), TiN, TaN, the like, and/or combinations thereof. Formation of the filling metal may be exemplarily performed using CVD, PVD, ALD, the like, and/or a combination thereof.

A bottom electrode stack layer140is then formed over the BEVA130and over the dielectric layer120, so that the bottom electrode stack layer140extends along a top surface of the BEVA130and top surfaces of the dielectric layer120. The bottom electrode stack layer140can be a single-layered structure or a multi-layered structure. For example, the bottom electrode stack layer140includes a first electrode layer142, a second electrode layer144over the first electrode layer142, and a buffer layer146over the second electrode layer144.

In some embodiments, the first electrode layer142may include titanium (Ti), tantalum (Ta), platinum (Pt), ruthenium (Ru), tungsten (W), aluminum (Al), copper (Cu), TiN, TaN, the like, and/or a combination thereof. Formation of the first electrode layer142may be exemplarily performed using CVD, PVD, ALD, the like, and/or a combination thereof.

In some embodiments, the second electrode layer144is formed over the first electrode layer142. The second electrode layer144may include a material different from that of the first electrode layer142. For example, the second electrode layer144may include Ru, Ti, W, Ni, Al, Pd, Co, or the combination thereof. In some embodiments, the second electrode layer144may be more inactive than the first electrode layer142. For example, the second electrode layer144may be more inert to oxygen than the first electrode layer142is. In some embodiments, the second electrode layer144may include noble metals, while the first electrode layer142may include non-noble metals. For example, the second electrode layer144may include Ru, Pd, or the like, and the first electrode layer142may include Ti, Ta, Al, W, TiN, TaN or the like. The second electrode layer144may be deposited by ALD. Alternatively, the second electrode layer144is deposited by an electroless plating process or other suitable process.

In some embodiments, the buffer layer146is formed over the second electrode layer144. The buffer layer146may include a material different from that of the second electrode layer144. In some embodiments, the buffer layer146may be more active than the second electrode layer144. For example, in some embodiments, the buffer layer146may include non-noble metals, while the second electrode layer144may include noble metals. For example, the buffer layer146may include tantalum, TaN, or the combination thereof. The buffer layer146may deposited by ALD. Alternatively, the buffer layer146is deposited by an electroless plating process or other suitable process. The buffer layer146may have a thickness in a range of about 5 angstroms to about 20 angstroms. If the thickness of the buffer layer146is greater than about 20 angstroms, a forming voltage for triggering the RRAM device may be too large to be bear by the gate oxide of a logic device, which derives the demands of high voltage logic devices, which may occupy more chip area. If the thickness of the buffer layer146is less than about 5 angstroms, the subsequent surface treatment performed to the top surface146T of the buffer layer146may not make the top surface146T include defects, which in turn will fail the improvement on the cycling of the resistance switch layer150(referring toFIG.3) to be formed.

Reference is made toFIG.2. A surface treatment is performed to a top surface146T of the buffer layer146by inducing a gas or plasma to the top surface146T of the buffer layer146. The gas or plasma may include oxide-containing gas or nitrogen-containing gas. For example, the gas or plasma may include O2or N2O. In some embodiments, the surface treatment may be performed in ex-situ chamber after the formation of the buffer layer146. After the surface treatment, the top surface146T of the buffer layer146may include defects, such as dangling bonds or oxide vacancies. In other word, the surface treatment may create oxide vacancies over a top surface of the bottom electrode stack layer140.

In some embodiments, the surface treatment may turn a top portion of the buffer layer146adjoining the top surface146T into a metal-containing compound layer. For example, the surface treatment may oxidize a top portion of the buffer layer146adjoining the top surface146T. The oxidized top portion of the buffer layer146may referred to as a metal-containing oxide layer146P hereinafter. The metal-containing oxide layer146P may have a same metal as that included in the buffer layer146. The metal included in the metal-containing oxide layer146P and the buffer layer146may be a non-noble metal. For example, while the buffer layer146include tantalum or TaN, the metal-containing oxide layer146P may include TaO. A thickness of the metal-containing oxide layer146P may be several angstroms, for example, in a range from about 3 angstroms to about 8 angstroms. In some embodiments, the metal-containing oxide layer146P is observable by TEM and/or EDX analysis. Sometimes, in alternative embodiments, the metal-containing oxide layer146P may be too thinned to be observed.

In some embodiments, the surface treatment using the oxide-containing gas (e.g., O2) is performed in a chemical vapor deposition (CVD) chamber with a power ranging from about 5 W to about 800 W and a time duration ranging from about 3 seconds to about 50 seconds. If the power is greater than about 800 W or the time duration is greater than about 50 seconds, the resistance switch layer150(referring toFIG.3) to be formed may have leakage issues, which may fail the RRAM device. If the power is less than about 5 W or the time duration is less than about 3 seconds, the cycling of the resistance switch layer150(referring toFIG.3) to be formed may not be effectively improved.

In some embodiments, the surface treatment using the nitrogen-containing gas (e.g., N2O) is performed in a chemical vapor deposition (CVD) chamber with a power ranging from about 5 W to about 600 W and a time duration ranging from about 3 seconds to about 50 seconds. If the power is greater than about 600 W or the time duration is greater than about 50 seconds, the resistance switch layer150(referring toFIG.3) to be formed may have leakage issues, which may fail the RRAM device. If the power is less than about 5 W or the time duration is less than about 3 seconds, the cycling of the resistance switch layer150(referring toFIG.3) to be formed may not be effectively improved.

Reference is made toFIG.3. A resistance switch layer150, a capping layer160, a top electrode layer170, and a hardmask layer180are subsequently formed on the top surface146T. In some embodiments where the metal-containing oxide layer146P is observable, the resistance switch layer150may be in contact with the metal-containing oxide layer146P. The deposited resistance switch layer150may be spaced apart from the buffer layer146of the bottom electrode stack layer140by the metal-containing oxide layer146P. In some embodiments where the metal-containing oxide layer146P is unobservable, the resistance switch layer150may be in contact with the buffer layer146. The resistance switch layer150includes a material having a variable resistance configured to undergo a reversible phase change between a high resistance state and a low resistance state. For example, the resistance switch layer150may include high-k dielectric films. In some embodiments, the resistance switch layer150is a metal oxide, which may be hafnium oxide, zirconium oxide, aluminum oxide, nickel oxide, tantalum oxide, titanium oxide, and other oxides used as a resistance switch layer. The metal oxide may have a non-stoichiometric oxygen to metal ratio. Depending on the method of deposition, the oxygen to metal ratio and other process conditions may be tuned to achieve specific resistance switch layer150properties. For example, a set of conditions may yield a low ‘forming’ voltage and another set of conditions may yield a low ‘read’ voltage. The metal oxide may be deposited. In some embodiments, the metal oxide is a transition metal oxide. In other embodiments, the resistance switch layer is a metal oxynitride.

The resistance switch layer150may be formed by a suitable technique, such as atomic layer deposition (ALD) with a precursor containing a metal and oxygen. Other chemical vapor deposition (CVD) techniques may be used. In another example, the resistance switch layer150may be formed by a physical vapor deposition (PVD), such as a sputtering process with a metallic target and with a gas supply of oxygen and optionally nitrogen to the PVD chamber. In yet another example, the resistance switch layer150may be formed by an electron-beam deposition process.

In some cases, when a formed RRAM device is operated over many cycles, oxygen may move far away from the resistance switch layer150, and it can be difficult to pull the oxygen back to the resistance switch layer150to subsequently break the conductive filament, which in turn will damage the dielectric data storage layer and result in hard reset bit (HRB) issue, eventually leading to RRAM failure.

In some embodiments of the present disclosure, by increasing the amount of oxide vacancies of the surface146T where the resistance switch layer150is formed on, the amount of oxide vacancies in the resistance switch layer150is increased. Through the configuration, when a formed RRAM device is operated, it can be easier to pull the oxygen back to the resistance switch layer150to subsequently break the conductive filament, and therefore improving the reliability of the RRAM device.

In various embodiments, the capping layer160over the resistance switch layer150is a metal, for example, titanium, hafnium, platinum, ruthenium or tantalum. In some embodiments, the capping layer may include hafnium oxide, aluminum oxide, tantalum oxides, other metal oxidation composite layers, or the combination thereof. The capping layer160may be deposited using a PVD process, a CVD, or an ALD process.

The top electrode layer170may be metal, metal-nitride, doped polysilicon or other suitable conductive material. For example, the top electrode layer170may be tantalum nitride, titanium nitride, titanium, tantalum or platinum. The top electrode layer170may single or bilayer. The top electrode layer170may be formed by PVD, CVD, ALD, or other suitable technique. Alternatively, the top electrode layer170includes other suitable conductive material to electrically connect the device to other portion of an interconnect structure for electrical routing. In some embodiments, the capping layer160and the top electrode layer170may be formed of the same material, but using different processes so as to vary a specific material property. In other embodiments, the capping layer160is a metal and the top electrode layer170is a metal nitride, for example, the capping layer160may be titanium and the top electrode layer170may be a tantalum nitride.

The hardmask layer180may be made of silicon nitride, silicon carbide, or other composite dielectric layers. In some embodiments, a silicon oxynitride is used. Silicon oxynitride has a good etch selectivity against the bottom electrode metal. Other hardmask material including silicon carbide, carbon-doped silicon nitride, or silicon nitride may be used.

Reference is made toFIG.4. The hardmask layer180, the top electrode layer170, and the capping layer160(referring toFIG.3) are patterned into a hardmask182, a top electrode172, a capping layer162, respectively. The patterning process may include a photolithography operation where a photoresist is deposited over the hardmask layer180(referring toFIG.3), a pattern is defined by exposing photoresist to a radiation, and developing the photoresist to create a photoresist pattern. The photoresist pattern is then used as an etch mask to protect desired portions of the hardmask layer180(referring toFIG.3). The hardmask layer180(referring toFIG.3) may then be patterned using an etching operation. In some embodiments, an etchant used to pattern the hardmask layer180(referring toFIG.3) includes an etching chemistry including gases of CF4, CH2F2and/or other chemicals. The photoresist mask is removed after the patterning. In some embodiments, the photoresist mask can be removed by adding oxygen to the etchant. Subsequently, the hardmask182is used as an etchmask to pattern the top electrode layer170and the capping layer160. In some embodiments, an etchant is applied to etch an exposed portion of the top electrode layer170and the capping layer160that is not covered by the hardmask182. The etch process stops when the resistance switch layer150is reached. Techniques are available to detect the end of etching when a new material layer is reached so as to reduce the amount of over etching.

Reference is made toFIG.5. A spacer layer190is deposited over the hardmask182and the resistance switch layer150. The spacer layer190may be made of silicon nitride, silicon oxynitride, and silicon oxide. The spacer layer190may be formed by conformally coating a spacer material covering the top and sidewalls of the top electrode172and the capping layer162.

Reference is made toFIG.6. An anisotropic etch process is performed to remove horizontal portions of the spacer layer190(referring toFIG.5), and remain vertical portions of the spacer layer190, thereby forming the spacer192. The spacer192surrounds the hardmask182, the top electrode172, and the capping layer162, and thus protects them against subsequent etch operations. The height and width of the spacer192after etching may be tuned by adjusting deposition and etching parameters.

According to various embodiments, the spacer etching is performed without patterning using a patterned mask because the shape of the conformal spacer material can be etched to form the spacer192. However, other spacer shapes may be formed by patterning the spacer material using a patterned mask. If a patterned mask is used, the spacer192may be formed of suitable shapes. For example, the spacer192may include a portion over the hardmask182and the top corners of the hardmask182so as to further protect the memory structure during bottom electrode etch.

Then, reference is made toFIG.7. The resistance switch layer150, the metal-containing oxide layer146P, the buffer layer146, the second electrode layer144, and the first electrode layer142(referring toFIG.6) are patterned into a resistance switch element152, a metal-containing oxide portion146P′, a buffer element146′, a second electrode144′, and a first electrode142′, respectively. The spacer192and the hardmask182are used as an etch mask to remove portions of the resistance switch layer150, the buffer layer146, the second electrode layer144, and the first electrode layer142(referring toFIG.6). In some embodiments, the buffer element146′, the second electrode144′, and the first electrode142′ in combination may be referred to as a bottom electrode140′. Through the operations, a memory structure MS is formed, and the memory structure MS includes the bottom electrode140′, the metal-containing oxide portion146P′ over the bottom electrode140′, the resistance switch element152over the metal-containing oxide portion146P′, the capping layer162over the resistance switch element152, the top electrode172over the capping layer162, and the hardmask182over the top electrode172.

In the present embodiments, the bottom electrode stack layer140(referring toFIG.6) is patterned into the bottom electrode140′ after patterning the resistance switch layer150and the top electrode layer170(referring toFIG.5) into the resistance switch element152and the top electrode172. In some alternative embodiments, the bottom electrode stack layer140(referring toFIG.5) may be patterned into the bottom electrode140′ prior to patterning the resistance switch layer150and the top electrode layer170(referring toFIG.5) into the resistance switch element152and the top electrode172. For example, the bottom electrode stack layer140(referring toFIG.5) may be patterned into the bottom electrode140′, and then the resistance switch layer150and the top electrode layer170(referring toFIG.5) are deposited over the bottom electrode140′ in some embodiments.

Reference is made toFIG.8. An inter-layer dielectric layer200is deposited over the memory structure MS and the metal/dielectric layer110using suitable deposition techniques. The inter-layer dielectric layer200may be silicon oxide, extreme or extra low-k silicon oxide such as a porous silicon oxide layer, or other commonly used inter-layer dielectric material. After the formation of the inter-layer dielectric layer200, a top electrode via2000are etched in the inter-layer dielectric layer200to expose a top electrode172. Subsequently, the top electrode via2000is filled with a conductive feature210, such as a metal. The filling may also include one or more liner and barrier layers in addition to a metal conductor. The liner and/or barrier may be conductive and deposited using CVD or PVD. The metal may be deposited using PVD or one of the plating methods, such as electrochemical plating. After the filling, a planarization process, such as chemical mechanical polishing (CMP), is performed to remove excess conductive feature210.

In some embodiments of the present disclosure, the surface treatment to the surface146T may increase the amount of oxide vacancies in the resistance switch element152thereby improving a reliability of the memory structure MS. In some embodiments, the surface treatment to the surface146T may further enlarge the difference between currents measured at the first data state (e.g., a ‘0’) and the second data state (e.g., a ‘1’), which in turn may improve the operation window of the memory device.

FIG.9is a cross-sectional view of a memory device in accordance with some embodiments of the present disclosure. The details of the present embodiments are similar to that of the embodiments ofFIGS.1-8, except the configuration of the bottom electrode140′. In the present embodiments, the bottom electrode140′ may not include the second electrode144′. For example, in the present embodiments, a bottom surface of the buffer element146′ is directly in contact with a top surface of the first electrode142′. Other details of the present embodiments are similar to those described above, and therefore not repeated herein.

FIG.10is a cross-sectional view of a memory device in accordance with some embodiments of the present disclosure. The configuration of the present embodiments are similar to that of the embodiments ofFIGS.1-8, except that the surface treatment performed to the top surface146T of the buffer layer146(referring toFIG.1) may not form a observable metal-containing oxide portion. That is, the formed memory structure MS may not include an observable metal-containing oxide portion that has a same metal as that included in the buffer element146′ between the buffer element146′ of the bottom electrode140′ and the resistance switch element152. For example, in the present embodiments, a bottom surface of the resistance switch element152is directly in contact with a top surface of the buffer element146′, without a TaO layer therebetween. Other details of the present embodiments are similar to those described above, and therefore not repeated herein.

FIGS.11-17illustrate various stages in the formation of a memory device according to some embodiments of the present disclosure. The configurations of the present embodiments are similar to that of the embodiments ofFIGS.1-8, except the shapes of the stacked layers. For example, the stacked layers have a recess profile corresponding to the openings O1in the dielectric layer120. The illustration is merely exemplary and is not intended to limit beyond what is specifically recited in the claims that follow. It is understood that additional operations may be provided before, during, and after the operations shown byFIGS.11-17, and some of the operations described below can be replaced or eliminated for additional embodiments of the method. The order of the operations/processes may be interchangeable.

FIG.11illustrates a semiconductor substrate102having transistors and one or more metal/dielectric layers110thereon. The semiconductor substrate102may be a silicon substrate. Alternatively, the substrate102may include another elementary semiconductor, such as germanium; a compound semiconductor including silicon carbide; an alloy semiconductor including silicon germanium; or combinations thereof. In some embodiments, the substrate102is a semiconductor on insulator (SOI) substrate. The substrate102may include doped regions, such as p-wells and n-wells. The transistors are formed by suitable transistor fabrication processes and may be a planar transistor, such as polysilicon gate transistors or high-k metal gate transistors, or a multi-gate transistor, such as fin field effect transistors. After the transistors are formed, one or more metal/dielectric layers110of a multi-level interconnect (MLI) is formed over the transistors. The metal/dielectric layer110includes one or more conductive features112embedded in an inter-layer dielectric (ILD) layer114.

In the present embodiments, a dielectric layer120is formed on the metal/dielectric layer110, and an opening O1is etched in the dielectric layer120to expose a portion of the conductive feature112in the metal/dielectric layer110. The dielectric layer120may include suitable dielectric material, such as silicon oxide.

Subsequently, a bottom electrode stack layer140is deposited over the dielectric layer120and filling the opening O1. In some embodiments, the bottom electrode stack layer140can be a single-layered structure or a multi-layered structure. For example, the bottom electrode stack layer140includes a diffusion barrier layer141, a first electrode layer142over the diffusion barrier layer141, a second electrode layer144over the first electrode layer142, and a buffer layer146over the second electrode layer144.

In some embodiments, the diffusion barrier layer141is a titanium nitride (TiN) layer or a tantalum nitride (TaN) layer, which can act as a suitable barrier to prevent metal diffusion. Formation of the diffusion barrier layer141may be exemplarily performed using CVD, PVD, ALD, the like, and/or a combination thereof.

In some embodiments, the second electrode layer144may include Ru, Ti, W, Ni, Al, Pd, or Co, or the combination thereof. In some embodiments, the second electrode layer144may be more inactive than the first electrode layer142. For example, the second electrode layer144may be more inert to oxygen than the first electrode layer142is. In some embodiments, the second electrode layer144may include noble metals, while the first electrode layer142may include non-noble metals. For example, the second electrode layer144may include Ru, Pd, or the like, and the first electrode layer142may include Ti, Ta, Al, W, TiN, TaN or the like. The second electrode layer144may be deposited by ALD. Alternatively, the second electrode layer144is deposited by an electroless plating process or other suitable process.

In some embodiments, the buffer layer146is formed over the second electrode layer144. In some embodiments, the buffer layer146may be more active than the second electrode layer144. For example, in some embodiments, the buffer layer146may include non-noble metals, while the second electrode layer144may include noble metals. For example, the buffer layer146may include tantalum, TaN, or the combination thereof. The buffer layer146may deposited by ALD. Alternatively, the buffer layer146is deposited by an electroless plating process or other suitable process.

In the present embodiments, the diffusion barrier layer141, the first and second electrode layer142and144, and the buffer layer146of the bottom electrode stack layer140have profiles conforming to the opening O1in the dielectric layer120. For example, each of the diffusion barrier layer141, the first and second electrode layer142and144, and the buffer layer146has a first portion in the opening O1in the dielectric layer120and a second portion over a top surface of the dielectric layer120. In other word, each of the diffusion barrier layer141, the first and second electrode layer142and144, and the buffer layer146has a recess above the opening O1in the dielectric layer120.

Reference is made toFIG.12. A surface treatment is performed to a top surface146T of the buffer layer146by inducing a gas or plasma to the top surface146T of the buffer layer146. The gas or plasma may include oxide-containing gas or nitrogen-containing gas. For example, the gas or plasma may include O2or N2O. In some embodiments, the surface treatment may be performed in ex-situ chamber after the formation of the buffer layer146. After the surface treatment, the top surface146T of the buffer layer146may include defects, such as dangling bonds or oxide vacancies. In other word, the surface treatment may create oxide vacancies over a top surface of the bottom electrode stack layer140.

In some embodiments, the surface treatment may oxidize a top portion of the buffer layer146adjoining the top surface146T. The oxidized top portion of the buffer layer146may referred to as a metal-containing oxide layer146P hereinafter. The metal-containing oxide layer146P may have a same metal as that included in the buffer layer146. For example, while the buffer layer146include tantalum or TaN, the metal-containing oxide layer146P may include TaO. In the present embodiments, the metal-containing oxide layer146P may has a profile conforming to the opening O1in the dielectric layer120. For example, the metal-containing oxide layer146P has a first portion in the opening O1in the dielectric layer120and a second portion over the top surface of the dielectric layer120. In other word, the metal-containing oxide layer146P has a recess above the opening O1in the dielectric layer120. In some embodiments, a bottom surface of the metal-containing oxide layer146P is higher than a top surface of the dielectric layer120.

Reference is made toFIG.13. A resistance switch layer150, a capping layer160, a top electrode layer170, and a hardmask layer180are subsequently formed on the top surface146T. In some embodiments, the resistance switch layer150is a metal oxide, which may be hafnium oxide, zirconium oxide, aluminum oxide, nickel oxide, tantalum oxide, titanium oxide, and other oxides used as a resistance switch layer. The metal oxide may have a non-stoichiometric oxygen to metal ratio. Depending on the method of deposition, the oxygen to metal ratio and other process conditions may be tuned to achieve specific resistance switch layer150properties. For example, a set of conditions may yield a low ‘forming’ voltage and another set of conditions may yield a low ‘read’ voltage. In some embodiments of the present disclosure, by increasing the amount of oxide vacancies of the surface146T where the resistance switch layer150is formed on, the amount of oxide vacancies in the resistance switch layer150is increased, thereby improving a reliability of the RRAM device to be formed. Other details regarding the formation of these layers are similar to those illustrated above, and therefore not repeated herein.

Reference is made toFIG.14. The hardmask layer180, the top electrode layer170, and the capping layer160(referring toFIG.13) are patterned into a hardmask182, a top electrode172, a capping layer162, respectively. The patterning process may include suitable photolithography and etching operations. Other details regarding the patterning process are similar to those illustrated above, and therefore not repeated herein.

Reference is made toFIG.15. A spacer192is formed to surrounds the hardmask182, the top electrode172, and the capping layer162, and thus protects them against subsequent etch operations. The spacer192may be made of silicon nitride, silicon oxynitride, and silicon oxide. Formation of the spacer192may include depositing a spacer layer over the structure ofFIG.14, and then removing portions of the spacer layer by anisotropic etching process. Other details regarding the formation of the spacer192are illustrated above, and therefore not repeated herein.

Reference is made toFIG.16. The resistance switch layer150, the metal-containing oxide layer146P, the buffer layer146, the second electrode layer144, the first electrode layer142, and the diffusion barrier layer141(referring toFIG.15) are patterned into a resistance switch element152, a metal-containing oxide portion146P′, a buffer element146′, a second electrode144′, a first electrode142′, and a diffusion barrier layer141′, respectively. The spacer192and the hardmask182are used as an etch mask to remove portions of the resistance switch layer150, the buffer layer146, the second electrode layer144, the first electrode layer142, and the diffusion barrier layer141(referring toFIG.15). In some embodiments, the buffer element146′, the second electrode144′, the first electrode142′, and the diffusion barrier layer141′ in combination may be referred to as a bottom electrode140′. Through the operations, a memory structure MS is formed, and the memory structure MS includes the bottom electrode140′, the resistance switch element152, the capping layer162, the top electrode172, and the hardmask182.

In the present embodiments, the bottom electrode140′ has a via portion140VP in the dielectric layer120and a top portion140TP over a top surface of the dielectric layer120. The metal-containing oxide portion146P′ has a first portion P1over the via portion140VP of the bottom electrode140′ and a second portion P2over the top portion140TP of the bottom electrode140′, and a top surface of the second portion P2of the metal-containing oxide portion146P′ is higher than a top surface of the first portion P1of the metal-containing oxide portion146P′. In some embodiments, a bottom surface of the first portion P1of the metal-containing oxide portion146P′ is higher than a top surface of the dielectric layer120.

Reference is made toFIG.17. An inter-layer dielectric layer200is deposited over the memory structure MS and the metal/dielectric layer110using suitable deposition techniques. After the formation of the inter-layer dielectric layer200, a top electrode via2000is etched in the inter-layer dielectric layer200to expose a top electrode172. Subsequently, the top electrode via2000is filled with a conductive feature210, such as a metal. The filling may also include one or more liner and barrier layers in addition to a metal conductor. A metal/dielectric layer230may be formed over the memory structure MS, and the metal/dielectric layer230may include one or more conductive features232embedded in an inter-layer dielectric (ILD) layer234. Other details of the present embodiments are similar to those illustrated above, and therefore not repeated herein.

FIG.18is a cross-sectional view of a semiconductor device in accordance with some embodiments of the present disclosure. The semiconductor device includes a logic region900and a memory region910. Logic region900may include circuitry, such as an exemplary logic transistor902, for processing information received from the memory structures MS in the memory region910and for controlling reading and writing functions of the memory structures MS. In some embodiments, the memory structures MS may be similar to those shown above.

As depicted, the semiconductor device is fabricated using four metallization layers, labeled as M1through M4, with four layers of metallization vias or interconnects, labeled as V1through V4. Other embodiments may contain more or fewer metallization layers and a corresponding more or fewer number of vias. Logic region900includes a full metallization stack, including a portion of each of metallization layers M1-M4connected by interconnects V2-V4, with the interconnect V1connecting the stack to a source/drain contact of logic transistor902. The memory region910includes a full metallization stack connecting memory structures MS to transistors912in the memory region910, and a partial metallization stack connecting a source line to transistors912in the memory region910. Memory structures MS are depicted as being fabricated in between the top of the metallization layer M3and the bottom of the metallization layer M4. Also included in semiconductor device is a plurality of ILD layers. Five ILD layers, identified as ILD0through ILD4are depicted inFIG.18as spanning the logic region900and the memory region910. The ILD layers may provide electrical insulation as well as structural support for the various features of the semiconductor device during many fabrication process steps.

Based on the above discussions, it can be seen that the present disclosure offers advantages. It is understood, however, that other embodiments may offer additional advantages, and not all advantages are necessarily disclosed herein, and that no particular advantage is required for all embodiments. One advantage is that the amount of oxide vacancies in the resistance switch layer is increased by the surface treatment to its underlying layer (e.g., the bottom electrode), such that it can be easier to pull the oxygen back to the resistance switch layer to subsequently break the conductive filament, thereby improving the cycle reliability of the RRAM device. Another advantage is that the surface treatment further enlarges the difference between currents measured at the first data state (e.g., a ‘0’) and the second data state (e.g., a ‘1’), which in turn may improve the operation window of the memory device. In some embodiments, the surface treatment to the underlying layer may form an observable metal-containing oxide portion.

According to some embodiments of the present disclosure, a method for fabricating a memory device is provided. The method includes forming a bottom electrode layer over a substrate; forming a buffer layer over the bottom electrode layer; performing a surface treatment to a top surface of the buffer layer; depositing a resistance switch layer over the top surface of the buffer layer after performing the surface treatment; forming a top electrode over the resistance switch layer; and patterning the resistance switch layer into a resistance switch element below the top electrode.

According to some embodiments of the present disclosure, a method for fabricating a memory device is provided. The method includes forming a bottom electrode layer over a substrate; turning a top portion of the bottom electrode layer into a metal-containing oxide layer by introducing an oxide-containing gas to the top portion of the bottom electrode layer; depositing a resistance switch layer over the metal-containing oxide layer; forming a top electrode over the resistance switch layer; and patterning the resistance switch layer into a resistance switch element over the metal-containing oxide layer.

According to some embodiments of the present disclosure, a memory device includes a bottom electrode, a buffer element, a metal-containing oxide portion, a resistance switch element, and a top electrode. The buffer element is over the bottom electrode. The metal-containing oxide portion is over the buffer element, in which the metal-containing oxide portion has a same metal material as that of the buffer element. The resistance switch element is over the metal-containing oxide portion. The top electrode is over the resistance switch element.