Wafer test method utilizing conductive interposer

A wafer test method is performed for a wafer prior to forming bumps on the wafer, using a conductive interposer having one side with test pads and the other side with test bumps electrically connected to the test pads. The conductive interposer is mounted on the wafer having a plurality of chips, wherein the test bumps are in electrical contact with bond pads on active surfaces of the chips. Test probes are used to contact the test pads to perform tests for the chips. This wafer test method is beneficially performed prior to forming bumps on the wafer, such that the prior-art drawback of damaging bumps on the wafer by contacting test probes with the bumps on the wafer can be eliminated, and the conductive interposer mounted on the wafer prevents the test probes from physical contact with the bond pads on the chips, thereby not damaging the bond pads.

FIELD OF THE INVENTION

The present invention relates to wafer test methods, and more particularly, to a method for testing a wafer performed prior to forming bumps on the wafer.

BACKGROUND OF THE INVENTION

Semiconductor package is a resin-encapsulated structure incorporated with at least one integrated circuit component such as semiconductor chip that is enclosed by an encapsulating resin for protection. A chip carrier (e.g. substrate, lead frame, etc.) is usually employed to mount and electrically connect the semiconductor chip. A conventional electrical connection is achieved by using a plurality of conductive bonding wires (such as gold wires) to interconnect an active surface of the chip and the chip carrier, and the bonding wires are also encapsulated by the encapsulating resin. However, the bonding wires possess predetermined length and loop height, such that they occupy a certain extent of surface area on the chip carrier; further, an encapsulation body formed by the encapsulating resin is required having a height larger than the loop height to completely enclose the bonding wires and prevent the bonding wires from exposure that may damage the electrical performance of the bonding wires, such that the package size is hardly reduced. Accordingly, a flip-chip package is developed, characterized in pre-forming a plurality of bumps on the active surface of the chip for electrical connection, and allowing the chip to be mounted on and electrically connected to the chip carrier by the bumps. Unlike the bonding wires, the use of bumps, not having the concern of length and loop height, can effectively reduce the package size.

During fabrication of a flip chip, normally when a wafer comprising a plurality of chips is fabricated, a bumping process is performed using conventional screen printing technology to deposit tin-lead alloy at bond pads formed on active surfaces of the chips, and the tin-lead alloy is reflowed to form bumps. Then, the chips of the wafer are required subject to electrical tests to examine the quality and functionality of the chips, so as to figure out inferior chips having defective quality and functions. After the wafer undergoes a singulation process to separate apart the chips, the inferior chips are discarded, only allowing the chips passing the tests to be subject to subsequent fabrication processes.

The above electrical tests can be performed before and after forming the bumps on the wafer; the former is shown inFIGS. 6A and 6B. InFIG. 6A, test probes2directly contact bond pads13formed on the wafer1to perform the tests. InFIG. 6B, after the tests, a UBM (under bump metallurgy) structure15is formed respectively on the bond pads13to allow a bump14to be formed on each UBM structure15. However, this test method undesirably causes a notch on or damage to the bond pads13(FIG. 6A) or the UBM structure15by direct contact of the test probes2. When the notched UBM structure15is connected with the bump14, a void trapped with air would form at the notch and easily leads to popcorn effect thereby degrading the reliability of fabricated products.

Therefore, the more commonly used method is to perform the tests after the bumping process; as shown inFIG. 6C, the test probes2directly contact the bumps14on the wafer to carry out the electrical tests on the chips10. However, this method easily damages the bumps14and thus affects yield of subsequent chip packaging.

Moreover, U.S. Pat. No. 6,429,532 discloses a special arrangement of bond pads including a plurality of test bond pads that are electrically connected to bond pads formed with bumps, such that test probes contact the test bond pads to perform tests. However, this bond-pad arrangement requires additional surface area on the wafer for disposing the test bond pads, thereby not favorable for size miniaturization.

In addition, U.S. Pat. No. 5,661,042 discloses the use of an anisotropic conductive film (ACF) as a conductive medium between the wafer and the test probes, to allow an electrical current to flow through the ACF for performing the wafer tests. However, this technology is defective that the ACF has high conductive resistance and is only suitable for mediating the current but not for test performance; further, the ACF has short contact lifetime (about 50 times) and cannot be used repeatedly, and the ACF is expensively fabricated, thereby undesirably increasing the fabrication costs.

Therefore, the problem to be solved herein is to provide a wafer test method carried out before forming bumps on the wafer, which would not damage bond pads on the wafer and not increase fabrication costs.

SUMMARY OF THE INVENTION

An objective of the present invention is to provide a wafer test method by which a conductive interposer is mounted on a wafer before forming bumps on the wafer, to allow test probes to contact the conductive interposer and perform tests for the wafer.

Another objective of the invention is to provide a wafer test method by which the conductive interposer mounted on the wafer for performing the wafer tests would not damage bond pads on the wafer.

A further objective of the invention is to provide a wafer test method by which the conductive interposer mounted on the wafer for performing the wafer tests is cost-effectively fabricated and can be used repeatedly, thereby not requiring the use of an expensive anisotropic conductive film (ACF) and not increasing the fabrication costs.

In accordance with the foregoing and other objectives, the present invention proposes a wafer test method, comprising the steps of: providing a wafer integrally formed of a plurality of chips, each of the chips having an active surface and an opposite inactive surface, with a plurality of bond pads formed on the active surface; preparing a conductive interposer having a first surface and an opposite second surface, wherein the first surface is formed with a plurality of test pads, and the second surface is formed with a plurality of test bumps electrically connected to the test pads, the test bumps corresponding to the bond pads of the chips, and mounting the conductive interposer on the wafer such that the test bumps are in electrical contact with the bond pads to electrically connect the conductive interposer to the chips; and using test probes to contact the test pads of the conductive interposer to perform tests for the chips of the wafer.

Therefore, the wafer test method according to the invention is carried out for a fabricated wafer prior to forming bumps on the wafer, using a conductive interposer having one side with test pads and the other side with test bumps electrically connected to the test pads. The conductive interposer is mounted on the wafer comprising a plurality of chips, wherein the test bumps are in electrical contact with bond pads formed on active surfaces of the chips. Then, test probes are used to contact the test pads to perform tests for the chips. This wafer test method is beneficially performed prior to forming bumps on the wafer, such that the prior-art drawback of damaging bumps on the wafer by contacting test probes with the bumps on the wafer can be eliminated, and the conductive interposer mounted on the wafer prevents the test probes from physical contact with the bond pads on the chips, thereby not causing damage to the bond pads. Moreover, compared to the prior art using test probes to directly contact bond pads on the wafer, the use of the conductive interposer according to the invention allows moderate contact and increase in contact area between the conductive interposer and the bond pads on the wafer, such that the wafer tests can be more accurately and precisely performed. In addition, compared to using an expensive anisotropic conductive film (ACF) having high resistance and short contact lifetime, the conductive interposer according to the invention is more cost-effectively fabricated and can be used repeatedly, thereby reducing the overall fabrication costs.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

As shown inFIG. 1A, a wafer test method proposed by the present invention is first to prepare a wafer1integrally formed of a plurality of chips10, wherein each of the chips10has an active surface11and an opposite inactive surface12, and a plurality of bond pads13are formed on the active surface11of each chip10. The wafer1is fabricated by conventional technology, thereby not further detailed herein.

Referring toFIG. 1B, the next step is to mount a conductive interposer3on the wafer1and electrically connect the conductive interposer3to the chips10. The conductive interposer3has a first surface31and an opposite second surface32, wherein the first surface31is formed with a plurality of test pads33thereon, and the second surface32is formed with a plurality of test bumps34electrically connected to the test pads33, the test bumps34corresponding to the bond pads13of the chips10(one is shown), such that the test bumps34are in electrical contact with the bond pads13to electrically connect the conductive interposer3to the chips10.

Referring toFIG. 1C, the conductive interposer3is composed of a plurality of interposer units30, and edges of the conductive interposer3are supported by a frame4that abuts against the wafer (not shown) to position the conductive interposer3on the wafer.

Finally, referring toFIG. 1D, when the conductive interposer3is electrically connected to the chips10, the chips10are readily subject to electrical tests. Test probes2used to contact the test pads33on the first surface31of the conductive interposer3. As the test bumps34are in electrical contact with the bond pads11of the chips10, the electrical tests can be performed by the test probes2contacting the test pads33to examine the quality and functionality of the chips, such that failed chips with defective quality or functions can be collected and discarded, only allowing good chips passing the tests to undergo subsequent fabrication processes.

The above conductive interposer3can be fabricated by the processes shown inFIGS. 2A to 2D.

As shown inFIG. 2A, it is first to prepare a core35, which is a thin film or a substrate made of an organic material such as epoxy resin, polyimide resin, BT (bismaleimide triazine) resin, or FR4 resin. A copper foil (not shown) may be respectively pre-deposited on a first surface350and a second surface351of the core35.

Then, a plurality of vias36are formed through the core35. Conventional electroless plating and electrolytic plating processes are in turn performed to deposit a copper layer37respectively on the first and second surface350,351of the core35and on walls of the vias36, allowing the vias36plated with the copper layer37to form conductive vias36(designated by the same reference numeral as the vias36). The first surface350of the core35corresponds to the first surface31of the conductive interposer3, and the second surface351of the core35corresponds to the second surface32of the conductive interposer3.

Referring toFIG. 2B, a conventional patterning process is performed to subject the copper layer37on the first and second surfaces350,351of the core35to form a plurality of conductive traces38and allow the conductive traces38on the first and second surfaces350,351of the core35to be electrically interconnected by the conductive vias36.

Then, referring toFIG. 2C, a solder mask39such as resist dry film is applied respectively over the conductive traces38on the first and second surfaces350,351of the core35. A plurality of openings390are formed through the solder mask39for exposing predetermined portions of the conductive traces38via the openings390. The exposed portions of the conductive traces38on the first surface350of the core35form test pads33, and the exposed portions of the conductive traces38on the second surface351of the core35subsequently form test bumps (not shown).

Finally, referring toFIG. 2D, a plurality of test bumps34such as gold bumps are formed at the exposed portions of the conductive traces38on the second surface351of the core35, so as to allow the test bumps34to be electrically connected to the test pads33through the corresponding conductive traces38and conductive vias36.

Therefore, the wafer test method according to the invention is carried out for a fabricated wafer prior to forming bumps on the wafer, using a conductive interposer having one side with test pads and the other side with test bumps electrically connected to the test pads. The conductive interposer is mounted on the wafer comprising a plurality of chips, wherein the test bumps are in electrical contact with bond pads formed on active surfaces of the chips. Then, test probes are used to contact the test pads to perform tests for the chips. This wafer test method is beneficially performed prior to forming bumps on the wafer, such that the prior-art drawback of damaging bumps on the wafer by contacting test probes with the bumps on the wafer can be eliminated, and the conductive interposer mounted on the wafer prevents the test probes from physical contact with the bond pads on the chips, thereby not causing damage to the bond pads. Moreover, compared to the prior art using test probes to directly contact bond pads on the wafer, the use of the conductive interposer according to the invention allows moderate contact and increase in contact area between the conductive interposer and the bond pads on the wafer, such that the wafer tests can be more accurately and precisely performed. In addition, compared to using an expensive anisotropic conductive film (ACF) having high resistance and short contact lifetime, the conductive interposer according to the invention is more cost-effectively fabricated and can be used repeatedly, thereby reducing the overall fabrication costs.

FIG. 3shows another example of the conductive interposer3. This conductive interposer3mounted on the wafer1allows the bond pads13on the chip10to be redistributed to alter or increase their pitch d. In particular, when the bond pads13on the chip10are arranged in high density i.e. having a small pitch d, test probes (not shown) having a corresponding small pitch are required to perform the wafer tests. However, the small-pitch test probes (currently down to a pitch of about 30 μm) are very expensively made, not favorable for reduction of fabrication costs. This problem can be solved by using the conductive interposer3having one side with test pads33and the other side with test bumps34, wherein the test bumps34are electrically connected to the test pads33by conductive traces38and conductive vias36. As a result, the redistribution technique can be performed through the conductive traces38and conductive vias36to alter or increase the pitch D for the test pads33, such that test probes can easily and accurately recognize and contact the test pads33to perform the wafer tests, thereby not having to concern the pitch limitation of test probes and undesirable increase in fabrication costs.

The above conductive interposer3adapted to alter the pitch of bond pads13by redistribution is also suitable for allowing the use of test probes (not shown) for testing peripheral pads to perform tests for a chip10′ having an array of bond pads13, as shown inFIG. 4, or the use of test probes (not shown) for testing array-arranged pads to perform tests for a chip10″ having peripheral bond pads, as shown inFIG. 5. Referring toFIG. 4, the test bumps34on the second surface32of the conductive interposer3correspond to and contact the array-arranged bond pads13on the chip10′, and are redistributed to peripheral test pads33on the first surface31of the conductive interposer3by corresponding conductive traces38and conductive vias36, such that the test probes for testing peripheral pads can be used to perform tests for the chip10′. Similarly, referring toFIG. 5, the peripheral bond pads13on the chip10″ are in contact with peripheral test bumps34on the second surface32of the conductive interposer3, and the test bumps34are redistributed to array-arranged test pads33on the first surface31of the conductive interposer3by corresponding conductive traces38and conductive vias36, such that the test probes for testing array-arranged pads can be used to perform tests for the chip10″.