Storage device having a controller that communicates with each of two memories through separate interfaces

A storage device includes a first memory device including a plurality of first memory cells, a second memory device including a plurality of second memory cells having the same type as the plurality of first memory cells, and a controller that communicates with the first memory device through a first memory interface and communicates with the second memory device through a second memory interface having an operating speed higher than an operating speed of the first memory interface.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims priority under 35 U.S.C. § 119 to Korean Patent Application Nos. 10-2018-0114090 filed on Sep. 21, 2018, and 10-2019-0002343 filed on Jan. 8, 2019, in the Korean Intellectual Property Office, the disclosures of which are incorporated by reference herein in their entireties.

BACKGROUND

Embodiments of the disclosure described herein relate to an electronic device, and more particularly, relate to a storage device.

Nowadays, an artificial intelligence (AI) function is being utilized in various fields. For example, in various electronic devices such as a personal computer, a notebook, a tablet, a smartphone, and a digital camera, the artificial intelligence function may be utilized for various functions such as voice recognition and image classification. In general, the artificial intelligence function accompanies a lot of calculations. To implement a lot of calculations, a calculation circuit of a faster operating speed and a high-capacity high-speed memory for processing data are required. According to the related art, the artificial intelligence function has been supported by using a separate data center or a separate server which includes a circuit supporting a high-speed calculation and a high-capacity high-speed memory.

However, the way to use the separate data center causes an increase in costs due to the use of the data center and a delay due to data transmission/reception over a network.

SUMMARY

Embodiments of the disclosure provide a storage device having an improved performance and reduced costs.

According to an example embodiment, a storage device includes a first memory device including a plurality of first memory cells, a second memory device including a plurality of second memory cells having the same type as the plurality of first memory cells, and a controller that communicates with the first memory device through a first memory interface and communicates with the second memory device through a second memory interface having an operating speed higher than an operating speed of the first memory interface.

According to an example embodiment, a storage device includes a first controller that communicates with an external device through a host interface, a first memory device that includes a plurality of first memory cells and communicates with the first controller through a first channel of a first memory interface, a second memory device that includes a plurality of second memory cells having the same type as the plurality of first memory cells, and a second controller that communicates with the first controller through a second channel of the first memory interface and is connected with the second memory device through a second memory interface.

According to an example embodiment, a storage device includes a first memory device including a plurality of first NAND flash memory cells, a second memory device including a plurality of second NAND flash memory cells, and a controller that communicates with the first memory device through a first memory interface and communicates with the second memory device through a second memory interface having a larger input/output bandwidth than the first memory interface.

According to an example embodiment, a storage device includes a first nonvolatile memory, a second nonvolatile memory, a first controller, and a second controller. The first controller accesses a first memory location within the first nonvolatile memory by communicating a first memory-access command to the first nonvolatile memory. The second controller uses weight information stored in the second nonvolatile memory to execute an operation on first data communicated by the first controller.

DETAILED DESCRIPTION

Below, embodiments of the disclosure may be described in detail and clearly to such an extent that an ordinary one in the art easily implements the disclosure.

The terms “unit”, “module”, etc. to be used in the specification or function blocks illustrated in drawings may be implemented in the form of software, hardware, or a combination thereof.

FIG.1is a block diagram illustrating a computing system according to an embodiment of the disclosure. Referring toFIG.1, a computing system10may include a host11and a storage device100. In an example embodiment, the computing system10may be one of computing devices, which perform various calculation functions, such as a personal computer (PC), a tablet PC, a digital camera, and a smartphone.

The host11may perform various operations necessary for the computing system10to operate. In an example embodiment, the host11may be a central processing unit (CPU) or an application processor (AP) which performs overall operations of the computing system10. The host11may communicate with the storage device100through a host interface. The host11may store data in the storage device100or may read data stored in the storage device100.

In an example embodiment, the host11may provide data (hereinafter referred to as “special data SDT”) for performing a machine learning (ML) function to the storage device100. For example, as described above, the host11may be configured to perform overall operations of the computing system10. While the host11operates, a special operation (e.g., voice recognition, image classification, image recognition) associated with specific data SDT may be required. In this case, the host11may provide the special data SDT to the storage device100.

In an example embodiment, the special data SDT may not be stored in the storage device100in a nonvolatile form. The special data SDT may include voice data, image data, or a specific type of data, based on a kind of a special operation to be performed by a second controller130.

The storage device100may selectively perform any one of a normal operation and the special operation (e.g., a machine learning operation) under control of the host11. In an example embodiment, the normal operation may indicate an operation of storing user data UDT in a first memory120or reading the user data UDT stored in the first memory120, under control of the host11. Alternatively, the normal operation may indicate various operations performed by a typical storage device, such as a read operation, a write operation, an erase operation, a physical erase operation, a device reset operation, and an initialization operation. That is, the normal operation may indicate an operation which is performed by the typical storage device under control of the host11. The special operation may indicate an artificial intelligence operation or a machine learning operation, which is based on an artificial intelligence function (e.g., a convolutional neural network or a deep neural network), such as voice recognition image classification, and image identification.

In other words, in the case where the storage device100performs the normal operation under control of the host11, the storage device100may store the user data UDT received from the host11, may transmit the stored user data UDT to the host11, or may perform any other normal operations (e.g., a device reset operation, an initialization operation, a power-down operation, and a power-up operation). In the case where the storage device100performs the special operation under control of the host11, the storage device100may receive the special data SDT from the host11, may perform a special operation on the special data SDT, and may transmit result data RDT including a result of the special operation to the host11.

The storage device100may include a first controller110, the first memory device120, the second controller130, and a second memory device140. The first controller110may control overall operations of the storage device100. The first controller110may include an input/output (I/O) router111. The input/output router111may determine whether a request received from the host11is associated with the normal operation or is associated with the special operation, and may provide information (e.g., the user data UDT or the special data SDT) received from the host11to the first memory120or the second controller130based on a result of the determination.

For example, in the case where a request associated with the normal operation is received from the host11, the input/output router111may determine input data received together with the request as the user data UDT, and may transmit the received user data UDT to the first memory device120through a normal channel CH_n. In the case where a request associated with the special operation is received from the host11, the input/output router111may determine input data received together with the request as the special data SDT, and may transmit the received special data SDT to the second controller130through a dedicated channel CH_d. In an example embodiment, the input/output router111may be configured to transmit the special data SDT to the first memory device120, and the first memory device120may be configured to store the special data SDT.

In an example embodiment, a first memory interface IF1may include a plurality of channels, and any one of the plurality of channels may be the normal channel CH_n, and any other channel thereof may be the dedicated channel CH_d. In an example embodiment, the plurality of channels included in the first memory interface IF1may indicate communication paths which are driven independently of each other, and the plurality of channels may communicate with devices which are respectively connected to the channels based on the same communication manner.

In an example embodiment, based on various information (e.g., address information, logical unit information, and command information) from the host11, the input/output router111may determine whether a request received from the host11is associated with the normal operation or is associated with the special operation, or may determine whether input data received from the host11are the user data UDT or are the specific data SDT.

The first memory device120may perform the normal operation under control of the first controller110through the normal channel CH_n. For example, the first memory device120may receive the user data UDT from the first controller110through the normal channel CH_n and may store or program the received user data UDT.

The second controller130may perform the special operation under control of the first controller110through the dedicated channel CH_d. For example, the second controller130may be configured to support a machine learning function such as voice recognition, image classification, or image identification. The second controller130may receive the special data SDT from the first controller110through the dedicated channel CH_d and may perform a special operation on the received special data SDT. The second controller130may provide the result data RDT including a result of the special operation to the first controller110through the dedicated channel CH_d under control of the first controller110.

In an example embodiment, the second controller130may perform the above-described special operation by using a weight WT stored in the second memory device140through a second memory interface IF2. For example, the second controller130may require weight (WT) information for performing the supported special operation. In the case where the special operation is performed, the second controller130may perform the above-described special operation based on the weight WT stored in the second memory device140. In an example embodiment, the second controller130may be an accelerator hardware for the machine learning functions.

In an example embodiment, the first and second memory devices120and140may be respectively implemented with memory devices of the same type. For example, the first and second memory devices120and140may include NAND flash memory cells or a charge trap flash (CTF) cells and may operate at different operating speeds.

In an example embodiment, each of the first and second memory devices120and140may be a NAND flash memory device, but the disclosure is not limited thereto. For example, each of the first and second memory devices120and140may be any one of nonvolatile memory devices such as a flash memory, a phase-change random access memory (PRAM), a magnetic RAM (MRAM), a resistive RAM (RRAM), etc. Alternatively, an operating speed of the second memory device140may be higher than an operating speed of the first memory device120. In an example embodiment, the second memory device140may be a high-speed memory such as a dynamic random-access memory (DRAM).

In an example embodiment, each of the first controller110, the first memory device120, the second controller130, and the second memory device140may be implemented with a separate semiconductor device, a separate semiconductor chip, a separate semiconductor die, or a separate semiconductor package. Alternatively, a part of the first controller110, the first memory device120, the second controller130, and the second memory device140may be implemented with one semiconductor device, one semiconductor chip, one semiconductor die, or one semiconductor package. For example, the second controller130and the second memory device140may be implemented with one semiconductor package, and the second controller130and the second memory device140may be connected to each other through a high-speed signal line (e.g., a through silicon via (TSV)) within the semiconductor package.

In an example embodiment, the normal channel CH_n between the first controller110and the first memory device120and the dedicated channel CH_d between the first controller110and the second controller130may be channels included in the first memory interface IF1. That is, each of the first memory device120and the second controller130may communicate with the first controller110based on the same interface. In an example embodiment, the first memory interface IF1may be a NAND interface, but the disclosure is not limited thereto.

In an example embodiment, the second controller130and the second memory device140may communicate based on the second memory interface IF2different from the first memory interface IF1. The second memory interface IF2may be an interface which supports a higher operating speed than the first memory interface IF1. For example, the amount of data which the second memory interface IF2transmits per time may be greater than the amount of data which the first memory interface IF1transmits per time. Alternatively, a bandwidth of the second memory interface IF2may be wider than a bandwidth of the first memory interface IF1. That is, the second controller130may read the weight WT stored in the second memory device140at a high speed.

As described above, the storage device100according to an embodiment of the disclosure may support the machine learning function. As such, because the burden on an operation of the host11may decrease or a separate data center is not used, a storage device having an improved performance and reduced costs is provided.

FIG.2is a block diagram illustrating the first controller110ofFIG.1. Referring toFIG.2, the first controller110may include the input/output router111, a processor112, an SRAM113, a ROM114, a host interface circuit115, and a first memory interface circuit116.

The input/output router111may determine whether a request (or data) provided from the host11is associated with the normal operation or is associated with the special operation. A determination operation of the input/output router111will be more fully described with reference to the following drawings.

The processor112may perform overall operations of the first controller110. The SRAM113may be used as a working memory or a buffer memory of the first controller110. The ROM114may store a variety of information, which is necessary for the first controller110to operate, in the form of firmware. In an example embodiment, the input/output router111may be implemented in the form of software, hardware, or a combination thereof. In the case where the input/output router111is implemented in the form of software, a program code or an instruction for performing an operation of the input/output router111may be stored in the SRAM113and may be executed by the processor112. In an example embodiment, an operation of the input/output router111may be performed by a flash translation layer (FTL) (not illustrated).

The first controller110may communicate with the host11through the host interface circuit115. In an example embodiment, the host interface circuit115may be based on at least one of various interfaces such as a double data rate (DDR) interface, a low-power DDR (LPDDR), a universal serial bus (USB) interface, a multimedia card (MMC) interface, a peripheral component interconnection (PCI) interface, a PCI-express (PCI-e) interface, an advanced technology attachment (ATA) interface, a serial-ATA (SATA) interface, a parallel-ATA (PATA) interface, a small computer small interface (SCSI) interface, an enhanced small disk interface (ESDI), an integrated drive electronics (IDE) interface, a mobile industry processor interface (MIPI), a nonvolatile memory-express (NVM-e) interface, and a universal flash storage (UFS) interface.

The first controller110may communicate with the first memory device120and the second controller130through the first memory interface circuit116. In an example embodiment, the first memory interface circuit116may be based on a NAND interface. The first controller110may communicate with the first memory device120through the normal channel CH_n of the first memory interface circuit116and may communicate with the second controller130through the dedicated channel CH_d of the first memory interface circuit116. The first memory interface circuit116may output data received from the host11through any one of the normal channel CH_n and the dedicated channel CH_d, based on a determination result of the input/output router111.

In an example embodiment, the first controller110may use a program command in order to transmit the user data UDT to the first memory device120or transmit the special data SDT to the second controller130. That is, the first controller110may transmit the program command and the user data UDT to the first memory device120through the normal channel CH_n. The first controller110may transmit the program command and the special data SDT to the second controller130through the dedicated channel CH_d.

FIG.3is a block diagram illustrating a second controller ofFIG.1. Referring toFIGS.1and3, the second controller130may include a controller interface circuit131, a machine learning core132, a second memory interface circuit133, and an ECC engine134.

The second controller130may communicate with the first controller110through the controller interface circuit131. For example, the controller interface circuit131may communicate with the first memory interface circuit116of the first controller110through the dedicated channel CH_d. In an example embodiment, through the dedicated channel CH_d, the controller interface circuit131may receive the special data SDT from the first memory interface circuit116or may transmit the result data RDT to the first memory interface circuit116.

The machine learning core132may perform the special operation on the special data SDT received from the controller interface circuit131. In an example embodiment, the machine learning core132may perform the special operation on the special data SDT by using the weight WT stored in the second memory device140.

For example, the second memory interface circuit133may read the weight WT from the second memory device140under control of the machine learning core132. An error of the weight WT may be corrected by the ECC engine134, and the error-corrected weight WT′ may be provided to the machine learning core132. The machine learning core132may perform the special operation on the special data SDT by using the error-corrected weight WT′.

Below, to describe a technical feature of the disclosure easily, it is assumed that the special operation to be performed by the machine learning core132is a voice recognition operation. That is, the special data SDT provided from the host11may be voice data, and the machine learning core132may perform the special operation (i.e., the voice recognition operation) on the special data SDT and may output the result data RDT. In this case, the result data RDT may be text data corresponding to the voice data.

The machine learning core132may include a feature extracting module132a, an acoustic model132b, and a decoding module132c. The feature extracting module132amay perform a feature extracting operation on the received special data SDT and may provide information of a frame unit to the acoustic model132b. The acoustic model132bmay perform voice recognition on the information of the frame unit by using the error-corrected weight WT′. The decoding module132cmay receive a voice recognition result from the acoustic model132band may output the result data RDT (i.e., text data) corresponding to the received voice recognition result. In an example embodiment, the above-described operation of the machine learning core132may be based on an artificial intelligence algorithm such as a machine learning algorithm or a neural network algorithm. In an example embodiment, the machine learning core132may include at least one multiply accumulate (MAC) unit to perform the above-described special operation. That is, the machine learning core132may be configured to perform the above-described special operation by performing a MAC operation on the above-described weight WT and the information of the frame unit through the at least one MAC.

In an example embodiment, it is assumed that the frame unit is 10 ms and the weight WT used in the acoustic model132bhas a size of 100 MB. According to this assumption, for the machine learning core132to normally perform the special operation (i.e., the voice recognition operation), the weight WT of 100 MB may be provided to the acoustic model132bevery 10 ms. That is, the second controller130may read the weight WT of 100 MB from the second memory device140every 10 ms. To this end, the second memory interface circuit133may be implemented with a high-speed interface.

For example,FIG.4is a diagram illustrating the first memory interface circuit116of the first controller110and the second memory interface circuit133of the second controller130. As illustrated inFIG.4, the first memory interface circuit116may be implemented with a typical NAND interface, but the disclosure is not limited thereto.

For example, the first memory interface circuit116may provide a chip enable signal CE, an address latch enable signal ALE, a command latch enable signal CLE, a write enable signal WE/, and a read enable signal RE/ to the first memory device120or the second controller130, and may exchange data signals DQ[1:i] (“i” being an integer greater than 1) and a data strobe signal DQS with the first memory device120or the second controller130. In an example embodiment, inFIG.4, signals associated with the first memory interface circuit116may be a signal configuration corresponding to one channel (e.g., any one of the normal channel CH_n and the dedicated channel CH_d). The first memory device120or the second controller130may receive the user data UDT or the special data SDT from the first controller110through the signal configuration illustrated inFIG.4.

The second memory interface circuit133may transmit the chip enable signal CE, the address latch enable signal ALE, the command latch enable signal CLE, the write enable signal WE/, and the read enable signal RE/ to the second memory device140, and may exchange data signals DQ[1:k] (“k” being an integer greater than “1”) and the data strobe signal DQS with the second memory device140. In this case, the number of data signals DQ[1:k] of the second memory interface circuit133may be more than the number of data signals DQ[1:i] of the first memory interface circuit116. In other words, a data input/output bandwidth of the second memory interface circuit133may be greater than a data input/output bandwidth of the first memory interface circuit116. Accordingly, an operating speed of the second memory interface circuit133may be higher than an operating speed of the first memory interface circuit116. As such, the second controller130may read the weight WT from the second memory device140at a high speed.

The configurations of the first and second memory interface circuits116and133described with reference toFIG.4is exemplary, and the disclosure is not limited thereto. The first and second memory interface circuits116and133may be implemented differently from the signal configuration illustrated inFIG.4.

FIGS.5A to5Dare block diagrams illustrating a first memory device and a second memory device ofFIG.1.FIG.6is a circuit diagram illustrating a memory block included in first and second memory devices ofFIGS.5A to5D.

Referring toFIGS.1,4, and5A, the first memory device120may include first and second planes PL1and PL2and an input/output circuit121. Each of the first and second planes PL1and PL2may include a plurality of memory blocks. The input/output circuit121may be connected with the first and second planes PL1and PL2and may exchange data with an external device (e.g., the first controller110) through a plurality of data lines DQ1to DQi (“i” being an integer greater than 1). For example, the input/output circuit121may include a plurality of data signal pins respectively connected with the plurality of data lines DQ1to DQi.

Referring toFIGS.1,4, and5B, the second memory device140may include a plurality of planes PL1to PLn (“n” being an integer greater than 1) and an input/output circuit141. Each of the plurality of planes PL1to PLn may include a plurality of memory blocks. The input/output circuit141of the second memory device140may be connected with the plurality of planes PL1to PLn and may exchange data with an external device (e.g., the second controller130) through a plurality of data lines DQ1to DQk (“k” being an integer greater than “i”). For example, the input/output circuit141may include a plurality of data signal pins respectively connected with the plurality of data lines DQ1to DQk.

As illustrated inFIGS.5A and5B, the number of planes included in the second memory device140may be more than the number of planes included in the first memory device120. In an example embodiment, a plane may mean a set of memory blocks sharing the same bit lines. That is, memory blocks included in one plane may share the same bit lines.

In an example embodiment, the number of data signal pins (i.e., the number of DQ pins) of the second memory device140may be more than the number of data signal pins (i.e., the number of DQ pins) of the first memory device120. Alternatively, the number of data lines of the second memory device140may be more than the number of data lines of the first memory device120. That is, the second memory device140may exchange data with the external device at a higher speed than the first memory device120.

In an example embodiment, because the number of planes of the second memory device140is more than the number of planes of the first memory device120, layouts of DQ signal pins of the first and second memory devices120and140may be different from each other. For example, as illustrated inFIG.5C, DQ signal pins (i.e., DQ pads) DQ1to DQi of the first memory device120may be arranged in an edge area EDGE of the first memory device120. In contrast, DQ signal pins (i.e., DQ pads) DQ1to DQk of the second memory device140may be arranged in a center area CENTER of the second memory device140. As the DQ signal pins DQ1to DQk of the second memory device140are arranged in the center area CENTER of the second memory device140, a physical distance between the DQ signal pins DQ1to DQk and the plurality of planes PL1to PLn may decrease, thus making a high-speed operation of the second memory device140possible.

In an example embodiment, as illustrated inFIG.5D, a second memory device140-1may further include a multiply accumulate (MAC) module142. The MAC module142may be configured to perform a MAC operation on the weight WT stored in the second memory device140-1and to output a result of the MAC operation through the plurality of data lines DQ1to DQk. For example, as described with reference toFIG.3, the machine learning core132of the second controller130may be configured to perform the MAC operation on the weight WT. In this case, in the case where the second memory device140-1outputs the result of the MAC operation performed on the weight WT, the burden on the MAC operation to be performed by the second controller130may decrease. That is, based on a way to implement the storage device100, a MAC module may be included in the second memory device140or may be included in the second controller130.

In an example embodiment, a plurality of memory blocks constituting planes included in the first and second memory devices120and140may include memory cells of the same cell type (e.g., CTF memory cells). For example, the memory blocks constituting the planes included in the first and second memory devices120and140may be implemented to be similar to a memory block BLK illustrated inFIG.6.

In an example embodiment, a memory block of a three-dimensional structure will be described with reference toFIG.6, but the disclosure is not limited thereto. A memory block according to the disclosure may have a two-dimensional memory block structure. In an example embodiment, the memory block BLK illustrated inFIG.6may be a physical erase unit of the first and second memory devices120and140. However, the disclosure is not limited thereto. For example, an erase unit may be changed to a page unit, a word line unit, a sub block unit, etc.

Referring toFIG.6, a memory block BLK may include a plurality of cell strings CS11, CS12, CS21, and CS22. The plurality of cell strings CS11, CS12, CS21, and CS22may be arranged along a row direction and a column direction to form rows and columns.

Each of the plurality of cell strings CS11, CS12, CS21, and CS22includes a plurality of cell transistors. For example, each of the cell strings CS11, CS12, CS21, and CS22may include string selection transistors SSTa and SSTb, a plurality of memory cells MC1to MC8, ground selection transistors GSTa and GSTb, and dummy memory cells DMC1and DMC2. In an example embodiment, each of the plurality of cell transistors included in the cell strings CS11, CS12, CS21, and CS22may be a charge trap flash (CTF) memory cell.

In each cell string, the plurality of memory cells MC1to MC8may be serially connected and may be stacked in a direction perpendicular (i.e., in a height direction) to a plane defined by the row direction and the column direction. The string selection transistors SSTa and SSTb may be serially connected, and the serially connected string selection transistors SSTa and SSTb may be interposed between the memory cells MC1to MC8and a bit line BL1, BL2. The ground selection transistors GSTa and GSTb may be serially connected and may be interposed between the memory cells MC1to MC8and a common source line CSL.

In an example embodiment, in each cell string, the first dummy memory cell DMC1may be interposed between the memory cells MC1to MC8and the ground selection transistors GSTa and GSTb. In an example embodiment, the second dummy memory cell DMC2may be disposed between the memory cells MC1to MC8and the string selection transistors SSTa and SSTb.

The ground selection transistors GSTa and GSTb of the cell strings CS11, CS12, CS21, and CS22may be connected in common to a ground selection line GSL. In an example embodiment, ground selection transistors in the same row may be connected to the same ground selection line, and ground selection transistors in different rows may be connected to different ground selection lines. For example, the first ground selection transistors GSTa of the cell strings CS11and CS12in the first row may be connected to a first ground selection line, and the first ground selection transistors GSTa of the cell strings CS21and CS22in the second row may be connected to a second ground selection line.

In an example embodiment, although not illustrated inFIG.6, ground selection transistors provided at the same height from a substrate (not illustrated) may be connected to the same ground selection line, and ground selection transistors provided at different heights may be connected to different ground selection lines.

Memory cells of the same height from the substrate or the ground selection transistors GSTa and GSTb are connected in common to the same word line, and memory cells of different heights therefrom are connected to different word lines. For example, the memory cells MC1to MC8of the cell strings CS11, CS12, CS21, and CS22may be connected to first to eighth word lines WL1to WL8, respectively.

String selection transistors, which belong to the same row, from among the first string selection transistors SSTa of the same height are connected to the same string selection line, and string selection transistors belonging to different rows are connected to different string selection lines. For example, the first string selection transistors SSTa of the cell strings CS11and CS12in the first row may be connected in common to the string selection line SSL1a, and the first string selection transistors SSTa of the cell strings CS21and CS22in the second row may be connected in common to the string selection line SSL2a.

Likewise, second string selection transistors, which belong to the same row, from among the second string selection transistors SSTb at the same height may be connected to the same string selection line, and second string selection transistors in different rows may be connected to different string selection lines. For example, the second string selection transistors SSTb of the cell strings CS11and CS12in the first row may be connected in common to a string selection line SSL1b, and the second string selection transistors SSTb of the cell strings CS21and CS22in the second row may be connected in common to a string selection line SSL2b.

In an example embodiment, dummy memory cells of the same height are connected with the same dummy word line, and dummy memory cells of different heights are connected with different dummy word lines. For example, the first dummy memory cells DMC1are connected to a first dummy word line DWL1, and the second dummy memory cells DMC2are connected to a second dummy word line DWL2.

In an example embodiment, the memory block BLK illustrated inFIG.6is only an example. The number of cell strings may increase or decrease, and the number of rows of cell strings and the number of columns of cell strings may increase or decrease depending on the number of cell strings. Also, in the memory block BLK, the number of cell transistors (GST, MC, DMC, SST, etc.) may increase or decrease, and a height of the memory block BLK may increase or decrease depending on the number of cell transistors (GST, MC, DMC, SST, etc.). In addition, the number of lines (GSL, WL, DWL, SSL, etc.) connected with cell transistors may increase or decrease as the number of cell transistors increases or decreases

FIG.7is a flowchart illustrating an operation of a storage device ofFIG.1. Below, to describe a technical idea of the disclosure easily, it is assumed that the storage device100receives a write request and data from the host11. However, the disclosure is not limited thereto.

Referring toFIGS.1and7, in operation S111, the storage device100may receive the write request and input data from the host11. For example, the host11may transmit the write request to the storage device100in order to transmit the input data (e.g., user data or special data) to the storage device100.

In operation S112, the storage device100may determine whether the received write request is associated with the special operation. For example, the input/output router111of the first controller110in the storage device100may determine whether the received write request is associated with the normal operation or is associated with the special operation, based on address information corresponding to the received write request, logical unit information, or attributes of the write request. Operation S112will be more fully described with reference toFIGS.8A to8D.

When the received write request is not associated with the special operation (i.e., the received write request is associated with the normal operation), in operation S113, the storage device100may perform a write operation (or a program operation) on the first memory device120through the normal channel CH_n. For example, the first controller110may transmit the received input data (i.e., the user data UDT) to the first memory device120in response to the write request received from the host11and the first memory device120may perform the program operation on the received user data UDT.

In operation S114, the storage device100may transmit a result of the write request to the host11. For example, the first controller110may receive a result (e.g., a program pass/fail) of the program operation of the first memory device120and may transmit information corresponding to the received result to the host11as a response to the write request. In an example embodiment, in the case where the result of the program operation of the first memory device120indicates the program fail, the storage device100may again perform the program operation on the user data UDT.

When the determination result of operation S112indicates that the received write request is associated with the special operation, in operation S115, the storage device100may transmit the input data (i.e., the special data SDT) to the second controller130through the dedicated channel CH_d.

In operation S116, the storage device100may perform the special operation on the special data SDT by using the weight WT stored in the second memory device140. For example, the second controller130may read the weight WT from the second memory device140through the second memory interface IF2and may perform the special operation on the special data SDT provided through the dedicated channel CH_d of the first memory interface IF1by using the read weight WT.

In an example embodiment, as described above, the first controller110may use the program command in order to provide the special data SDT to the second controller130. That is, the second controller130may receive the program command and the special data SDT from the first controller110through the dedicated channel CH_d and may perform the special operation on the received special data SDT in response to the received program command, but the disclosure is not limited thereto.

In operation S117, the storage device100may transmit a response to the host11. For example, in the case where the second controller130completes the special operation, the first controller110of the storage device100may transmit a response to the received write request to the host11.

In operation S118, the storage device100may receive a read request for the special operation from the host11. For example, in response to the response (i.e., a response indicating completion of the special operation) from the storage device100, the host11may transmit the read request for reading the result data RDT associated with the special operation to the storage device100. In an example embodiment, the read request of operation S118may include dedicated address information, dedicated logical unit information, etc. for accessing the second controller130which will be described with reference toFIGS.8A to8D, or may be a dedicated read request.

In operation S119, the storage device100may transmit the result (i.e., the result data RDT) of the special operation to the host11in response to the received read request.

FIGS.8A to8Dare diagrams for describing a determination operation of operation S112ofFIG.5. Components which are unnecessary to describe the technical idea of the disclosure are omitted for a brief description. In an example embodiment, embodiments illustrated inFIGS.8A to8Dare exemplary, but the disclosure is not limited thereto.

Referring toFIG.8A, the host11may include a host application11aand a device driver11b. The host application11amay include an operating system or various application programs which are driven on the host11.

The device driver11bmay be configured to access the storage device100in response to a request of the host application11a. For example, the device driver11bmay be configured to convert information provided from the host application11ato information capable of being identified by the storage device100, such that an operation requested by the host application11amay be performed on the storage device100or to manage the information provided from the host application11a. In an example embodiment, dedicated address information, dedicated logical unit information, a dedicated request, etc. described with reference toFIGS.8B to8Dmay be converted or managed by the device driver11b.

Referring toFIGS.1,8A, and8B, the host11may recognize a storage area of the storage device100as illustrated inFIG.8B. For example, a storage space of the storage device100may include a user area and a dedicated area. The user area may correspond to a space of the storage device100in which the user data UDT may be stored and the dedicated area may correspond to a separate space determined in advance or a virtual space.

The host11, in detail, the host application11aof the host11may perform an access to the user area of the storage device100. That is, the host application11amay perform an operation on the user area of the storage device100such as an operation of writing data, reading data, or erasing data.

In contrast, the device driver11bof the host11may recognize the user area and the dedicated area of the storage device100. In the case where the host application11arequests the normal operation (e.g., an operation of reading user data or an operation of writing user data) from the storage device100, the device driver11bmay transmit a request including a normal address of the user area to the storage device100. In this case, the storage device100may perform the normal operation on an area corresponding to the received normal address among the user area.

In the case where the host application11arequests the special operation, the device driver11bmay transmit a request including a dedicated address of the dedicated area to the storage device100. In this case, the storage device100may perform the special operation in response to the dedicated address included in the received request. That is, the first controller110of the storage device100may provide the second controller130with input data (i.e., the special data SDT) corresponding to the request having the dedicated address.

Referring toFIGS.1,8A, and8C, the storage area of the storage device100may be divided into a plurality of logical units. In an example embodiment, the logical unit may indicate an externally addressable, independent, or processing entity which may independently process a request from the host11.

The host application11amay recognize the storage space of the storage device100as first to n-th logical units. In contrast, the device driver11bmay recognize the storage space of the storage device100as the first to n-th logical units and a dedicated logical unit.

As in the description given with reference toFIG.8B, in the case where the host application11arequests the normal operation of the storage device100, the device driver11bmay transmit a request including information about any one of the first to n-th logical units to the storage device100. In response to the request including information about any one of the first to n-th logical units, the storage device100may perform the normal operation on the one logical unit.

In the case where the host application11arequests the special operation, the device driver11bmay transmit a request including information about the dedicated logical unit to the storage device100. The storage device100may perform the special operation in response to the request including the information about the dedicated logical unit.

Referring toFIGS.1,8A, and8D, the device driver11bmay transmit a request for the normal operation and a request for the special operation to the storage device100so as to be distinguished explicitly. For example, in the embodiments described with reference toFIGS.8B and8C, the device driver11bmay issue a request for the special operation by adding information about a dedicated address or information about a dedicated logical unit to a normal write command.

In contrast, in the embodiment illustrated inFIG.8D, the device driver11bmay issue the request for the special operation explicitly distinguished from the request for the normal operation. That is, in the case where a write request WR RQ is received from the device driver11b, the input/output router111of the storage device100may provide the received write request WR RQ to the first memory device120. In the case where a special operation request SP RQ explicitly distinguished from the write request WR RQ is received from the device driver11b, the input/output router111may provide the received special operation request SP RQ to the second controller130.

In an example embodiment, the special operation request SP RQ may be a request defined by a protocol between the host11and the storage device100, one of commands defined by the protocol, a reserved command, or a vendor specific command. Alternatively, the special operation request SP RQ may be issued by setting a specific value to a reserved field of a special request or command.

The configurations described with reference toFIGS.8A to8Dare examples for describing the technical idea of the disclosure easily, and the disclosure is not limited thereto. Various ways to distinguish the normal operation and the special operation may be used in compliance with a protocol determined in advance between the host11and the storage device100.

The embodiments are described with reference toFIGS.8A to8Das the device driver11bof the host11performs management for distinguishing the normal operation and the special operation, but the disclosure is not limited thereto. For example, the host application11aof the host11may be configured to perform the above-described operation of the device driver11b.

FIGS.9A and9Bare flowcharts illustrating operations of a host and a storage device ofFIG.1in detail. The normal operation of the storage device100will be described with reference toFIG.9A, and the special operation of the storage device100will be described with reference toFIG.9B. Components which are unnecessary to describe the technical idea of the disclosure are omitted for a brief description.

Referring toFIGS.1,7, and9A, in operation S111-1, the host11may transmit a write request to the first controller110together with data (i.e., the user data UDT) for the purpose of writing the data in the storage device100. For example, the host11may transmit the write request to the first controller110together with the data, based on a way to communicate with the storage device100in compliance with a protocol determined in advance. In this case, as described with reference toFIGS.8A to8D, the write request may be a normal write request, may include normal address information, or may include information about any one of the first to n-th logical units.

In operation S113-1, the first controller110may transmit a write command WR CMD and data to the first memory device120in response to the received write request. For example, in the case where the received write request is associated with the normal operation, the first controller110may transmit the write command WR CMD and the data to the first memory device120through the normal channel CH_n of the first memory interface IF1, in response to the received write request.

In operation S113-2, the first memory device120may perform the program operation (i.e., the write operation) on the received data in response to the received write command WR CMD. In operation S113-3, the first controller110may receive information about a result (i.e., a program pass/fail PGM P/F) of the program operation from the first memory device120. In operation S114, the first controller110may transmit a response to the write request to the host11.

Although not illustrated in drawings, in the case where the result of the program operation received in operation S113-3indicates the program fail, the first controller110may transmit a command for redoing the program operation to the first memory device120.

In an example embodiment, the first controller110may transmit a response to the host11before directly writing the data received in operation S111-1in the first memory device120. For example, the first controller110may transmit a response to the host11after storing the above-described data in a separate buffer memory. Afterwards, the first controller110may program the data stored in the separate buffer memory in the first memory device120. Operations S111-1through S114may constitute a write transaction.

In operation S120, the host11may transmit a read request to the storage device100for the purpose of reading data (e.g., user data UDT) stored in the storage device100. In operation S121, the first controller110may transmit a read command RD CMD to the first memory device120in response to the read request. In operation S122, the first controller110may receive read data from the first memory device120. In operation S123, the first controller110may transmit the read data to the host11. In an example embodiment, the read data may be data corresponding to address information included in the read request received in operation S120. Operations S120through S123may constitute a read transaction.

Referring toFIGS.1,7, and9B, in operation S111-2, the host11may transmit a write request and data to the first controller110for the purpose of performing the special operation. In this case, as described with reference toFIGS.8B and8C, the write request may include information about a dedicated address or information about a dedicated logical unit. Alternatively, as described with reference toFIG.8D, the write request may be a request (i.e., a special request SP RQ ofFIG.8D) explicitly distinguished from the normal write request.

In operation S115, the first controller110may transmit the received data (i.e., the special data SDT) to the second controller130through the dedicated channel CH_d of the first memory interface IF1. In an example embodiment, the first controller110may use a program command in order to transmit the received data to the second controller130.

In operation S116-1, the second controller130may read the weight WT from the second memory device140through the second memory interface IF2. In operation S116-2, the second controller130may perform the special operation on the received data (i.e., the special data SDT) by using the read weight WT. In operation S116-3, the second controller130may determine whether the special operation is completed. When the special operation is not completed, the second controller130performs operation S116-1. That is, as described with reference toFIG.3, the second controller130may read the weight WT from the second memory device140and may repeatedly perform the special operation on the received data in the unit of a frame, based on the read weight WT.

When the special operation is completed, the second controller130may transmit, in operation S116-4, a result of the special operation (i.e., a special operation pass/fail SP P/F) under control of the first controller110. In an example embodiment, the first controller110may read the result of the special operation from the second controller130through a status read operation.

In operation S117, the first controller110may transmit a response to the write request of operation S111-2to the host11. In operation S118, the host11may transmit a read request for reading the result (i.e., the result data RDT) of the special operation to the first controller110in response to the response of operation S117. In operation S119-1, the first controller110may transmit the read command RD CMD to the second controller130. In operation S119-2, the second controller130may transmit the result data RDT to the first controller110in response to the read command RD CMD. In operation S119-3, the first controller110may transmit the result data RDT to the host11.

In an example embodiment, as in the description given with reference toFIGS.8A to8D, the read request of operation S118may include information about a dedicated address or information about a dedicated logical unit or may be a request explicitly distinguished from the normal read request.

In an example embodiment, before the read request of operation S118is received, the first controller110may in advance perform operation S119-1and operation S119-2.

As described above, the storage device100according to an embodiment of the disclosure may perform the normal operation (e.g., an operation of reading, writing, or erasing user data) and the special operation (e.g., voice recognition, image classification, or image identification). Accordingly, because the burden on an operation of a host or the use of a data center for performing the special operation (e.g., an operation based on machine learning or artificial intelligence) decreases, a storage device having an improved performance and reduced costs is provided.

FIG.10is a flowchart illustrating an operation of a storage device ofFIG.1. Referring toFIGS.1and10, the storage device100may perform operation S121to operation S126. Operation S121to operation S126may be similar to operation S111to operation S116ofFIG.5, and thus, additional description will be omitted to avoid redundancy.

In operation S127, the storage device100may transmit a response including a result of the special operation to the host11. For example, the storage device100may transmit the response to the write request of operation S121to the host11in the unit of a packet. In this case, the result of the special operation (i.e., the result data RDT) may be included in the above-described response. The host11may receive the response in which the result data RDT are included and may check the result of the special operation based on the received result data RDT, without an additional read operation.

FIG.11is a block diagram illustrating a storage device according to an embodiment of the disclosure. Below, for convenience of description, additional description associated with the above-described embodiments will be omitted to avoid redundancy.

Referring toFIG.11, a storage device200may include a first controller210, a first memory device220, and a second memory device240. The first controller210may communicate with a host21. The first controller210may communicate with the first memory device220storing the user data UDT through the first memory interface IF1and may communicate with the second memory device240storing the weight WT through the second memory interface IF2. In an example embodiment, an operating speed of the second memory interface IF2may be higher than an operating speed of the first memory interface IF1. The first and second memory devices220and240may include memory cells of the same type as described above. The number of data pins included in the first memory device220may be different from the number of data pins included in the second memory device240. The first and second memory devices220and240are described with reference toFIGS.1to6, and thus, additional description will be omitted to avoid redundancy.

In an example embodiment, the first controller210may include a second controller230. The first controller110and the second controller130described with reference toFIG.1may be implemented with a separate semiconductor device, a separate semiconductor die, a separate semiconductor chip, or a separate semiconductor package, but the second controller230ofFIG.9may be included within the first controller210. Alternatively, the first controller210and the second controller230ofFIG.9may be implemented with one semiconductor device, one semiconductor chip, one semiconductor die, or one semiconductor package.

FIG.12is a block diagram illustrating a controller ofFIG.11. Referring toFIGS.11and12, the first controller210may include an input/output router211, a processor212, an SRAM213, a ROM214, a host interface circuit215, a first memory interface circuit216, a second memory interface circuit217, and a machine learning core230(the machine learning core230may correspond to the second controller230).

The input/output router211, the processor212, the SRAM213, the ROM214, the host interface circuit215, and the first memory interface circuit216are described with reference toFIG.2, and thus, additional description will be omitted to avoid redundancy.

Unlike the first controller110ofFIG.2, the first controller210ofFIG.12may further include the machine learning core230and the second memory interface circuit217. That is, in response to a request for the special operation received from the host21, the first controller210ofFIG.12may read the weight WT from the second memory device240through the second memory interface circuit217and may perform the special operation by using the read weight WT.

In an example embodiment, as described above, the first memory interface circuit216may be a circuit for supporting a NAND flash interface, and the second memory interface circuit217may be a circuit for supporting a high-speed interface. In other words, an operating speed of the second memory interface circuit217may be higher than an operating speed of the first memory interface circuit216.

FIG.13is a flowchart illustrating an operation of a storage device ofFIG.11. For a brief description, it is assumed that a write request received from the host21is a request for the special operation.

Referring toFIGS.11and13, in operation S211, the host21may transmit a write request and data to the first controller210. For example, to perform the special operation, the host21may transmit a write request including information about a dedicated address or information about a dedicated logical unit or a special request explicitly distinguished from the normal write request to the first controller210.

In operation S212, the first controller210may read the weight WT from the second memory device240through the second memory interface IF2in response to the received write request (i.e., a write request for the special operation). In operation S213, the first controller210may perform the special operation on the received data (i.e., the special data SDT) by using the weight WT. In operation S214, the first controller210may determine whether the special operation is completed; when the special operation is not completed, the first controller210performs operation S212.

When the special operation is completed, in operation S215, the first controller210may transmit a response to the host21. In operation S216, the host21may transmit a read request to the first controller210in response to the received response. In operation S217, the first controller210may transmit the result data RDT to the host21in response to the read request.

Although not illustrated in drawings, the first controller210may transmit a response including the result data RDT to the host21as a response to the write request for the special operation. In this case, a read request for reading the result data RDT from the host21may be omitted.

FIG.14is a block diagram illustrating a storage device according to an embodiment of the disclosure. Referring toFIG.14, a storage device300may include a first controller310, a first memory device320, a second controller330, a second memory device340, and a third memory device350. The first controller310may communicate with a host31and may include an input/output (I/O) router311. The first controller310, the first memory device320, the second controller330, and the second memory device340are described above, and thus, additional description will be omitted to avoid redundancy.

The storage device300ofFIG.14may further include the third memory device350. The third memory device350may include reference data RFDT for the special operation and may communicate with the second controller330based on a third memory interface IF3.

In an example embodiment, the third memory interface IF3may be an interface based on a communication manner different from the second memory interface IF2. The second memory interface IF2may be a communication manner optimized for a sequential data read operation, and the third memory interface IF3may be a communication manner optimized for a random data read operation. For example, as described with reference toFIG.3, in the case where the special operation to be performed by the machine learning core230is a voice recognition operation, the reference data RFDT may be data associated with word information for converting an operation result from the acoustic model132bto a text. In this case, the reference data RFDT may be used by the decoding module132cdescribed with reference toFIG.3. In this case, the decoding module132cmay require an operation of randomly reading partial data of the reference data RFDT. In other words, by implementing the third memory interface IF3based on the communication manner optimized for the random data read operation, the random read performance on the reference data RFDT stored in the third memory device350may be optimized.

In an example embodiment, the first, second, and third memory devices320,340, and350may be implemented with a NAND flash memory device. That is, the first, second, and third memory devices320,340, and350may be implemented with a memory device including memory cells (e.g., NAND flash memory cells or CTF cells) of the same type as the memory devices described with reference toFIGS.5A to6.

Alternatively, at least one of the first, second, and third memory devices320,340, and350may be a memory device of a different kind. For example, the first memory device320may be a memory device appropriate for high-capacity implementation, the second memory device340may be a memory device appropriate for a sequential read operation, and the third memory device350may be a memory device appropriate for a random read operation. Alternatively, the first and second memory devices may be implemented with a NAND flash memory and the third memory device340may be implemented with a random-access memory.

FIG.15is a block diagram illustrating a storage device according to an embodiment of the disclosure. Referring toFIG.15, a storage device500may include a first controller510, a first memory device520, a second controller530, and a second memory device540. The first controller510may communicate with a host51. The components of the storage device500are described above, and thus, additional description will be omitted to avoid redundancy.

Unlike the above embodiments, in the embodiment ofFIG.15, the first controller510may be configured to access the second memory device540. For example, the first controller510may provide a command for accessing the second memory device540to the second controller530through the dedicated channel CH_d and the second controller530may perform an access operation on the second memory device540in response to the received command and may provide a result of the access operation to the first controller510through the dedicated channel CH_d. Here, the access operation may be different from the special operation. For example, the access operation on the second memory device540may be an operation such as a write operation, a read operation, or an erase operation on the second memory device540.

In an example embodiment, the first controller510may communicate with the second memory device540through a second normal channel CH_n2. For example, the first controller510may perform the normal operation on the first memory device520through a first normal channel CH_n1and may provide the special data SDT to the second controller530through the dedicated channel CH_d. In this case, the first controller510may be configured to perform the normal operation on the second memory device540, in which the weight WT is stored, through the second normal channel CH_n2. In an example embodiment, the first controller510may be configured to manage the weight WT stored in the second memory device540through the second normal channel CH_n2.

FIG.16is a block diagram illustrating a storage device according to an embodiment of the disclosure. Referring toFIG.16, a storage device600may include a first controller610, a first memory device620, a second controller630, and a second memory device640. The first controller610may communicate with a host61. The components of the storage device600are described above, and thus, additional description will be omitted to avoid redundancy.

Unlike the above embodiments, the first controller610may communicate with the first memory device620through the first memory interface IF1and may communicate with the second controller630through a third memory interface IF3different from the first memory interface IF1. That is, in the above embodiments, a first controller may communicate with a second controller by using a specific channel included in the first memory interface IF1; however, in the embodiment ofFIG.16, the first controller610may further include a separate interface (i.e., the third memory interface IF3) for communicating with the second controller630.

FIGS.17A to17Dare block diagrams illustrating a configuration of a storage device according to an embodiment of the disclosure. For brevity of illustration and for convenience of description, a part of storage devices1000a,1000b,1000c, and1000dis illustrated, but the disclosure is not limited thereto.

Referring toFIG.17A, the storage device1000amay include a first controller1100a, a plurality of nonvolatile memory devices NVM, a second controller1200a, and a second memory device1300a.

The first controller1100amay be connected with the plurality of nonvolatile memory devices NVM through first to third channels CH_n1to CH_n3. The first controller1100amay be configured to control the first to third channels CH_n1to CH_n3, independently. In an example embodiment, the plurality of nonvolatile memory devices NVM connected respectively with the first to third channels CH_n1to CH_n3may be recognized as a user area (refer toFIG.6B) by an external device (e.g., a host). That is, the first controller1100amay perform the normal operation on the plurality of nonvolatile memory devices NVM through the first to third channels CH_n1to CH_n3.

The first controller1100amay communicate with the second controller1200athrough a first dedicated channel CH_d1. The second controller1200amay communicate with the second memory device1300aincluding the weight WT through a separate interface.

In an example embodiment, the nonvolatile memory devices NVM connected to the same normal channel may share the same input/output signal lines (e.g., DQ lines). That is, the first to third normal channel CH_n1to CH_n3may be distinguished in the unit of input/output lines. The first controller1100amay select or control the plurality of nonvolatile memory devices NVM respectively by controlling a chip enable signal of each of the plurality of nonvolatile memory devices NVM.

Referring toFIG.17B, the storage device1000bmay include a first controller1100b, a plurality of memory devices NVM, a second controller1200b, and a second memory device1300b.

The first controller1100bmay individually communicate with the plurality of nonvolatile memory devices NVM through the first to third channels CH_n1to CH_n3and a first dedicated channel CH_d1. The second controller1200bmay communicate with the first controller1100bthrough the first dedicated channel CH_d1and may communicate with the second memory device1300bincluding the weight WT through a separate interface.

In an example embodiment, as illustrated inFIG.17B, a plurality of nonvolatile memory devices NVM may be connected to the first dedicated channel CH_d1. In this case, the first controller1100bmay perform the normal operation on the plurality of nonvolatile memory devices NVM connected with the first dedicated channel CH_d1by controlling a chip enable signal. Also, the first controller1100bmay communicate with the second controller1200bconnected with the first dedicated channel CH_d1by controlling a chip enable signal.

For example, in the case where the first controller1100bcontrols any one of the plurality of nonvolatile memory devices NVM connected with the first dedicated channel CH_d1, the first controller1100bmay control the one nonvolatile memory device by selecting or activating a chip enable signal of the one nonvolatile memory device and not selecting or deactivating chip enable signals of the remaining devices (e.g., the remaining nonvolatile memory devices and the second controller1200b).

Also, in the case where the first controller1100bcommunicates with the second controller1200bconnected with the first dedicated channel CH_d1, the first controller1100bmay communicate with the second controller1200bby not selecting or deactivating all chip enable signals of the plurality of nonvolatile memory devices NVM connected with the first dedicated channel CH_d1and selecting or activating a chip enable signal of the second controller1200b.

Referring toFIG.17C, a storage device1000cmay include a first controller1100c, a plurality of memory devices NVM, a second controller1210c, a second memory device1310c, a third controller1220c, and a third memory device1320c.

The first controller1100cmay be connected with the plurality of nonvolatile memory devices NVM through first and second normal channels CH_n1to CH_n2. The first controller1100cmay be connected with the second controller1210cthrough the first dedicated channel CH_d1and may be connected with the third controller1220cthrough the second dedicated channel CH_d2. The second controller1210cmay be connected with the second memory device1310cthrough a separate interface, and the third controller1220cmay be connected with the third memory device1320cthrough a separate interface.

In an example embodiment, the second and third controllers1210cand1220cmay be configured to perform different special operations. For example, the second controller1210cmay perform a first special operation of performing voice recognition on voice data from an external device (e.g., a host) by using a weight stored in the second memory device1310cand outputting text information as result data. The third controller1220cmay perform a second special operation of performing image classification on image data from the external device by using a weight stored in the third memory device1320cand outputting information about the image classification as result data. In response to a request of the external device, the first controller1100cmay communicate with the second controller1210cor the third controller1220cto perform a special operation corresponding to the request of the external device.

Referring toFIG.17D, a storage device1000dmay include a first controller1100d, a plurality of memory devices NVM, a second controller1210d, a second memory device1310d, a third controller1220d, and a third memory device1320d.

The first controller1100dmay communicate with the plurality of nonvolatile memory devices NVM through the first to third channels CH_n1to CH_n3. The first controller1100dmay communicate with the second controller1210dand the third controller1220dthrough the first dedicated channel CH_d1. The second controller1210dmay be connected with the second memory device1310dthrough a separate interface, and the third controller1220dmay be connected with the third memory device1320dthrough a separate interface.

In the embodiment ofFIG.17C, the first controller1100ccommunicates with the second and third controllers1210cand1220cby using the first and second dedicated channels CH_d1and CH_d2; however, in the embodiment ofFIG.17D, the first controller1100dmay communicate with the second and third controllers1210dand1220dthrough the first dedicated channel CH_d1(i.e., one channel). In this case, the first controller1100dmay individually communicate with the second and third controllers1210dand1220dby controlling a chip enable signal of each of the second and third controllers1210dand1220d.

As described above, a storage device according to an embodiment of the disclosure may include a second controller configured to perform a special operation. A first controller may be configured to communicate with nonvolatile memory devices through a first memory interface normal channel and to communicate with the second controller through a first memory interface dedicated channel.

FIG.18is a block diagram illustrating a computing system according to an embodiment of the disclosure. Referring toFIG.18, a computing system2000may include a host2100, a first storage device2210, and a second storage device2220. The host2100may communicate with the first storage device2210through a first host channel CH_h1and may communicate with the second storage device2220through a second host channel CH_h2. In an example embodiment, the first and second host channels CH_h1and CH_h2may be a communication channel based on the same interface.

The first storage device2210may include a controller2211and memory devices2212and2213. The first storage device2210may perform a normal storage operation (i.e., an operation of reading, writing, or erasing user data) under control of the host2100.

The second storage device2220may include a first controller2221, a second controller2222, and a memory device2223. The second storage device2220may perform the special operation under control of the host2100. In an example embodiment, the second storage device2220may be a storage device including a machine learning function described with reference toFIGS.1to17or may operate based on an operating method described with reference toFIGS.1to17.

FIG.19is a block diagram illustrating a mobile system to which a storage device according to the disclosure is applied. Referring toFIG.19, a mobile system3000may include an application processor3100, a network module3200, a system memory3300, a storage device3400, an image sensor3500, a display device3600, and a user input/output device3700. In an example embodiment, the mobile system3000may be a portable computing system such as a smartphone, a tablet personal computer (PC), or a notebook.

The application processor3100(e.g., an application processor (AP)) may control overall operations of the mobile system3000. The network module3200may provide wireless or wired communication with an external device (e.g., a base station, a server, or any other mobile device). The system memory3300may be used as a working memory or a buffer memory of the mobile system3000. In an example embodiment, the system memory3300may be a memory (e.g., a DRAM) supporting a high-speed operation.

The storage device3400may be used as a high-capacity storage medium for storing various information used in the mobile system3000. In an example embodiment, the storage module3400may be a storage device including a machine learning function described with reference toFIGS.1to18and may communicate with the application processor3100based on an operating method described with reference toFIGS.1to18.

The display device3600may be a device displaying information processed by the application processor3100to a user. The image sensor3500may be a device collecting image information associated with an external subject. The user input/output device3700may be a device which receives a command from a user or provides information, such as a microphone, a speaker, a keypad, or a touch screen display.

According to the disclosure, a storage device may perform a special operation in response to a request of a host. Accordingly, because the burden on various operations of a host or the use of a data center required to perform the special operation decreases, the storage device having an improved performance and reduced costs and an operating method thereof are provided.