Semiconductor device having trench capacitor and method for manufacturing the same

A semiconductor device having a trench capacitor is provided, which includes a semiconductor substrate having a trench formed thereon, in which the semiconductor substrate serves as a first bottom plate; a first conductive structure formed in the trench, in which a bottom of the first conductive structure is electrically connected to the semiconductor substrate to serve as a second bottom plate; a first dielectric layer formed on the sidewall of the trench; a second conductive structure isolatedly formed around the first conductive structure to serve as a top plate; a second dielectric layer formed between the first conductive structure and the second conductive structure to isolate the first conductive structure and the second conductive structure; and a third conductive structure formed on the semiconductor substrate and electrically connected to the second conductive structure.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT The preferred embodiment of this invention is described below together with FIGS. 1 ˜ 8 and FIG. 9 . Referring to FIG. 1, a semiconductor substrate 100 is provided to serve as a bottom plate, in which the semiconductor substrate 100 is single crystalline silicon having a conductive dopant such as n-type or p-type dopant. Instead of the semiconductor substrate 100 , another conductive layer can be used as an initial layer. The following steps may proceed. An etching stop layer 140 , which is a material such as Si3N4, is formed on the semiconductor substrate 100 to serve as a stop layer of chemical mechanical polishing or etching in the sequential steps. Thereafter, the semiconductor substrate 100 is selectively etched to form a cylindrical trench 120 by photolithography and etching. Referring to FIG. 2, a SiO 2 layer 160 is deposited on the area, i.e., the sidewall and the bottom, except the center of the trench 120 using low pressure chemical vapor deposition (LPCVD) in the presence of tetra-ethyl-ortho-silicate (TEOS). The SiO 2 layer 160 is extended to the upper surface of the semiconductor substrate 100 . Referring to FIG. 3 , the SiO 2 layer located on the bottom of the trench 120 is removed by anisotropic etching to expose the semiconductor substrate 100 at the center DC of the trench 120 . Referring to FIG. 4, a conductive layer 180 , poly-silicon, is formed using in-situ doping LPCVD in the presence of SiH 4 . The dopant used here has the same conductivity as that of the semiconductor substrate 100 . Referring to FIG. 5 , the conductive layer 180 outside of the trench 120 is removed by CMP and etching back to form a conductive structure 180 a whose height is less than that of the trench 120 . At the same time, the SiO 2 layer 160 on the semiconductor substrate 100 is also removed. The conductive structure is used as a bottom plate of the trench capacitor. It should be noted that the bottom plate is constituted by the semiconductor substrate 100 and the conductive structure 180 a in this embodiment. Next, referring to FIG. 5 and FIG. 6 , the SiO 2 160 left on the sidewall of the trench 120 is removed using buffered oxide etchant (BOE) such as that including HF. A substantially conformal dielectric layer 200 is formed on the sidewall of the trench 120 and the conductive structure 180 a by chemical vapor deposition. The dielectric layer 200 includes the dielectric layer 200 ′ formed on the sidewall of the trench and the dielectric layer 200 ″ formed on the conductive structure 180 a . The dielectric layer 200 can be SiO 2 /Si 3 N 4 /SiO 2 or Si 3 N 4 /SiO 2 and has a thickness of about 45˜50 &angst;. Instead of the above-described material, the dielectric layer 200 can be additional materials such as Ta 2 O 5 and others. Referring to FIG. 7, a conductive layer 240 , which is a material such as poly-silicon, is formed using in-situ doping LPCVD in the presence of SiH 4 . The conductive layer 240 is filled between the dielectric layer 200 ′ and the dielectric layer 200 ″ to serve as the top plate. Referring to FIG. 8, a part of the conductive layer 240 is removed by CMP to remain a conductive structure 240 a , which is formed around the conductive structure 180 a and between the dielectric layer 200 ′ and the dielectric layer 200 ″. Then, a sidewall isolator 260 is formed on the top of the trench 120 by depositing and etching back a layer of SiO 2 . A conductive structure 280 , which is a material such as poly-silicon, is formed on the semiconductor substrate 100 by using CVD. The purpose of forming the sidewall isolator 260 is to prevent the conductive structure 180 and the semiconductor substrate 100 from short-circuiting. Accordingly, a semiconductor device having a trench capacitor fabricated by the above process includes a semiconductor substrate 100 , which serves as a part of the bottom plate of the capacitor, having a cylindrical trench 120 ; a cylindrical conductive structure 180 a formed in the trench 120 , in which the bottom of the cylindrical conductive structure 180 a is electrically connected to the semiconductor substrate 100 to serve as another part of the bottom plate; a dielectric layer 200 ′ formed on the sidewall of the trench 120 ; a ring-shaped conductive structure 240 a , isolatedly formed around the conductive structure 180 a , for serving as the top plate; a dielectric layer 200 ″, formed between the conductive structure 180 a and the conductive structure 240 a , for isolating the two conductive structures 180 a and 240 a ; and a third conductive structure 280 formed on the semiconductor substrate 100 and electrically connected to the conductive structure 240 a. Referring to FIG. 9 , the symbol C 1 indicates the first capacitor which is constituted by the semiconductor substrate 100 , the dielectric layer 200 ′ and the conductive structure 240 a , and the symbol C 2 indicates the second capacitor which is constituted by the conductive structure 180 a , the dielectric layer 200 ″ and the conductive structure 240 a . The capacitance is increased since the first capacitor C 1 and the second capacitor C 2 are connected in parallel. The symbol T in FIG. 9 indicates a MOS transistor. The drain of the transistor T is connected to the conductive structure 240 a through the third conductive structure 280 . The source of the transistor T is connected to the bit line BL, and the gate of the transistor T is connected to the word line WL. According to the present invention, the semiconductor device having a trench capacitor can be provided with an improved storage capacitance when the trench has a predetermined depth. Finally, while the invention has been described by way of example and in terms of the preferred embodiment, it is to be understood that the invention is not limited to the disclosed embodiments. On the contrary, it is intended to cover various modifications and similar arrangements as would be apparent to those skilled in the art. Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.