Access request selecting circuit

An access request selecting circuit for selectively accepting access request signals produced from a plurality of access request sources. Different series of recurrent time intervals are assigned to the access request sources. When a memory request signal is supplied from an access request source in a series of recurrent time intervals which are assigned to the access request source such a memory request signal is accepted. At this time, if an attendant signal produced in association with the memory request signal is supplied, this attendant signal is also accepted.

BACKGROUND OF THE INVENTION 
1. Field of the Invention 
The present invention relates to an access request selecting circuit for 
selectively accepting one by one access request signals produced from a 
plurality of access request sources. 
2. Description of the Prior Art 
The usage of, a dynamic type MOS memory element is increasing and is widely 
being used as a memory element for a memory unit. Under the circumstances, 
even the memory unit belonging to a data processing system of a relatively 
smaller capacity needs a selector circuit which is capable of selectively 
accepting an address signal issued by a processor unit or basic processing 
unit (BPU) and refresh address signal in order that requests for 
refreshing operation for maintaining information stored in the memory 
elements may be processed in addition to the access request from the basic 
processor unit (BPU). In the case of a data processing system of a large 
capacity, incorporating a plurality of processors, a selector circuit is 
required which is additionally capable of discriminating the input signals 
such as address signals, store data or the like which are issued by any 
specific processor in processing the access requests from the plurality of 
the processors. It is known to provide a storage control unit (SCU) in 
place of the selector circuit for the memory device. However, the system 
in which the selector circuit or a part thereof is provided for the memory 
unit is more frequently adopted for the reasons mentioned below. One of 
the reasons is that there are a great number of interleaves to the memory 
unit in the processing system of a large or very large capacity, resulting 
in that the logical quantities to be processed are increased to an amount 
which is beyond the processing capability of the storage control unit or 
otherwise require an extremely large scale storage control unit which will 
render the data processing system to be poor in flexibility and thus 
reduce the utility of the processing unit as the general purpose data 
processor for use in various data processing systems of different 
capacities. For example, considering only the store data, the selector 
circuit is required to have a capacity corresponding to 128 bytes in the 
case of interleaves of 16 ways on the eight-byte base. The second reason 
can be seen in the fact that the memory unit is usually provided with a 
register for holding addresses, store data or the like transmitted from 
access sources such as the storage control unit, which register may serve 
also as a register for holding the input signals selected by the selector 
circuit. In contrast, when the selector circuit is provided in the storage 
control unit, a further register has to be incorporated in the storage 
control unit for holding the input signals selected by the selector 
circuit in addition to the register which is provided in the memory unit, 
involving an increased number of gate stages as well as an increased 
quantity of hardware. The primary reason why the register is commonly 
incorporated in the memory unit is that the cycle time of the memory unit 
is five to ten times as long as that of the access source such as the 
storage control unit. If the storage control unit itself has to hold 
addresses, updating of the addresses will be impossible and therefore 
another access thereto will be also impossible until completion of one 
cycle of memory operation. Thus, by supplying addresses to memory elements 
so that they are held in the memory elements, the storage control unit is 
allowed to update the addresses and access different areas of the memory 
unit successively. Further, the increased storage capacity of the 
individual memory devices owing to the possibility of implementing the 
semiconductor memory device with a high density as is typical in the case 
of the dynamic type MOS memory has paved the way for incorporating the 
selector circuit in the memory unit in view of the fact that the increased 
storage capacity of the individual memory device allows the logical 
control quantities for the memory unit to be increased without being 
accompanied by any appreciable disadvantages. More specifically, when the 
individual memory devices are of a small storage capacity, the logical 
control quantities for the whole memory unit will become increased as 
compared with the overall available storage capacity, involving a 
correspondingly disadvantageous lessened efficiency. However, the memory 
device imparted with an increased storage capacity can evade such a 
shortcoming and make it possible to incorporate the selector circuit in 
the memory unit with a substantially same effect as the one combined with 
the storage control unit. 
It should however be mentioned that incorporation of the selector circuit 
for selectively discriminating only the input signals such as address 
signal and the like from the access source the access request of which is 
accepted from those incoming from other access sources brings about a 
problem that the access time to the memory unit is increased. In the 
hitherto known system, the input signal such as the address signal which 
is in company with the access request is allowed to be received or 
utilized in the memory unit only after the selector circuit has been 
enabled by a selector gating signal which is produced in response to the 
access request. 
FIG. 1 illustrates schematically known arrangement of a typical selector 
circuit which is combined with access sources constituted by a processing 
unit or BPU and a refresh request source, and FIG. 2 illustrates a 
signal-timing diagram to illustrate operation of the selector circuit 
shown in FIG. 1. In these figures, reference numeral 1 denotes a 
synchronizing circuit for synchronizing the fresh request, 2 and 3 denote 
AND gates, 4 and 5 denote flip-flops, 6 and 7 denote inverters, 8 denotes 
a selecting circuit and 9 denotes an address register, while 10 represents 
the access request from BPU, 11 represents a synchronizing clock signal, 
12 represents a refresh request signal, 13 represents an output signal 
from the synchronizing circuit 1, 14 represents a BPU select signal, 15 
represents a refresh select signal, 18 represents an address signal from 
the BPU, 19 represents a refresh address signal, 20 represents an address 
signal selected by the selecting circuitry 8, and 21 represents the output 
signal from the address register. Referring to FIG. 1, the time at which 
the access request 10 is supplied is limited to time points indicated by 
inverted triangular marks (.gradient.) shown in FIG. 2 by the timing of a 
clock (not shown) at which the access request is issued by the BPU. The 
refresh request signal 12 is so synchronized by the synchronizing circuit 
1 that the signal 12 is out of phase relative to the access request 10 by 
180.degree.. In other words, the time at which the synchronized refresh 
request signal 13 is generated is limited to the time points indicated by 
triangular marks (.DELTA.) in FIG. 2. In the case of the illustrated 
circuit arrangement, the synchronizing circuit 1 is constituted by two 
stages of flip-flops in order to prevent the request signal from being 
fetched in an uncertain state. At the time point indicated by the second 
triangle mark (.DELTA.) as counted from the left, the first flip-flop 
stage is set, while the second flip-flop stage is set at the time point 
indicated by the third triangle mark (.DELTA.), whereupon the refresh 
request signal is produced. 
The access request signal 10 and the refresh request signal 13 which are 
produced at a phase angle of 180.degree. relative to each other are fed to 
the flip-flops 4 and 5 through the AND gates 2 and 3, respectively. Since 
the access request signal is out of phase with the synchronized refresh 
request signal 13 by 180.degree., it will never occur that both the 
flip-flops 4 and 5 are set simultaneously, but either the flip-flop 4 or 5 
is set in dependence on which of the associated AND gates 2 and 3 receives 
the request signal 10 or 13 at an earlier time. In the illustration of 
FIG. 2, it is assumed that the access request 10 has been accepted 
earlier. When the flip-flops 4 or 5 (flip-flop 4 in the illustrated case) 
is thus set, the AND gates 2 and 3 are blocked by the signals 16 and 17, 
whereby the other request 13 is inhibited from being set in the associated 
flip-flop 5. Further, the selecting circuit 8 is enabled by the select 
signal 14 or 15 (signal 14 according to the above assumption) to select 
the address signal 18 from the BPU or the refresh address signal 19 (the 
address signal 18 in the illustrated case). The selected address signal 18 
is then placed in the address register 9. As will be appreciated, it is 
impossible with the illustrated circuit arrangement to place the address 
signal 18 from the BPU in the address register 9 until the select signal 
14 has been input to the selecting circuit 8 in response to the reception 
of the access request signal 10. 
FIG. 3 illustrates another example of a known selector circuit for a memory 
unit. In this case, it is assumed that the access source is constituted by 
a pair of storage control units which will hereinafter be referred to as 
SCUA and SCUB, respectively, to distinguish them from each other. It is 
further assumed that the generation of the access requests to the memory 
unit from the control units SCUA and SCUB is so sequenced that both the 
access requests are not simultaneously issued. Further, the units SCUA and 
SCUB are so controlled that the access requests are held by these units 
when the memory unit is being used. The access requests are then 
dispatched when the memory unit is free of use. FIG. 4 illustrates a 
signal-timing diagram to illustrate operation of the circuit arrangement 
illustrated in FIG. 3. In the figures, 40 and 41 denote flip-flops for 
temporarily holding the access requests from SCUA and SCUB, respectively, 
42 denotes an OR gate, 43 denotes an AND gate, 44 and 45 represent the 
access request signals from the SCUA and SCUB, respectively, and 48 and 49 
represent address signals issued from the SCUA and SCUB, respectively. 
Referring to FIG. 3, the access request signal 44 or 45 transmitted from 
the SCUA or SCUB is set in the flip-flop 40 or 41 under the timing of a 
clock pulse T2. Of course, the control is so made in the SCUA and SCUB 
that both the access requests 44 and 45 are not issued simultaneously. 
Consequently, it will never occur that both the flip-flops 40 and 41 are 
simultaneously set, but either the flip-flop 40 or 41 is selectively set 
in dependence on whether the access request 44 or 45 is generated. The 
illustration shown in FIG. 4 is based on the assumption that the access 
request 44 is issued from the SCUA. When the flip-flop 40 (or 41) is set, 
the signal 46 (or 47) which is the output of flip-flop 40 (or 41) opens 
the selecting circuit 8 thereby to gate selectively the address signal 48 
from the SCUA (or the address signal 49 from SCUB) to the address register 
9 as indicated at 20. Since the OR gate 42 produces an output in response 
to the previously described signal 46 (or 47) at that time, the output 
signal 20 from the selecting circuit 8 is placed in the address register 9 
in timing with a clock pulse T3 under the control of the AND gate 43. When 
the clock signal T2 is produced in the second cycle 2, the access request 
44 (or 45) is reset to logic "0", resulting in that both the previously 
described signals 46 and 47 are also logic "0". Consequently, the OR gate 
42 is blocked, whereby the up-dating of the contents in the address 
register 9 is inhibited. As will be understood, in the case of the circuit 
arrangement shown in FIG. 3, the address signal 48 can be accepted during 
a time interval between the clock or time point T2 at which the access 
request 44 is placed in the flip-flop 40 and the time point T3 at which 
the address signal 48 is set in the address register 9. 
As will be appreciated from the foregoing elucidation, in the known 
selector circuit control of selection of input signals such as address 
signals produced in association with access request signals such as memory 
request signals is effected after it is determined which of the memory 
request signals is selected. Thus, acceptance of an input signal such as 
an address signal associated with the memory request signal is delayed, 
which causes an undesirable increase of the access time. More 
particularly, a loss in the access time is involved in the interval 
between the reception of the access request 10 and the supply of the 
select signal 14 to the selecting circuit 8 in the case of the selector 
circuit shown in FIG. 1, and between the time points T2 and T3 in the case 
of the circuit shown in FIG. 3. Further, in the case of the circuit of 
FIG. 3 when the access requests 44 or 45 issued from the storage control 
units SCUA or SCUB and transferred in phase with the address signal 48 or 
49, respectively, the selecting circuit 8 is not enabled until the select 
signal 46 or 47 has been generated, as the result of which the time for 
receiving the address signal 48 or 49 is reduced. Consequently, the 
duration of the input signal 20 to the address register 9 becomes shorter 
than that of the access request signal 44 or 45, whereby the margin of 
timing for the transfer of the signal such as address signal from the 
storage control unit to the memory unit is undesirably decreased. 
SUMMARY OF THE INVENTION 
An object of the present invention is to eliminate the difficulties of the 
known selector circuits described above and provides an improved memory 
apparatus which can be operated at a high speed with an enhanced 
reliability. 
An access request selecting circuit in accordance with the invention for 
selectively accepting one by one access request signals produced from a 
plurality of access request sources includes a circuit for assigning 
recurrent time intervals to individual access request sources; a first 
access request taking circuit coupled to said time interval assigning 
circuit so that for a series of recurrent time intervals only an access 
request signal produced from that access request source to which said 
series of recurrent time intervals are assigned is accepted; and a second 
access request taking circuit coupled to said time interval assigning 
circuit so that an attendant signal produced by said second access request 
source in association with said access request signal is accepted 
independently of the operation of said first access request taking 
circuit.

DESCRIPTION OF THE PREFERRED EMBODIMENTS 
Now, the invention will be described in detail in conjunction with 
exemplary embodiments thereof. FIG. 5 illustrates a selector circuit which 
corresponds to the one described hereinbefore in connection with FIG. 1 
and to which the invention is applied, and FIG. 6 illustrates a 
signal-timing chart for illustrating operation of the circuit shown in 
FIG. 5. In the figures, reference numeral 22 denotes a NOR/OR gate, 23 
denotes a delay circuit, 24 denotes an Exclusive-OR gate, 25 denotes an OR 
gate, 26 denotes an AND gate, 27 and 28 represent a processing unit or BPU 
select signal and a refresh request select signal, respectively, 29 a 
timing signal, 30 a signal for inhibiting the timing signal 29, and 31 
represents a trigger signal for an address register 9. Other reference 
numerals same as those used in FIG. 1 denote or represent the same or 
equivalent items. In FIG. 5, after the access request 10 or the 
synchronized refresh request is issued, the AND gates 2 and 3 are blocked 
by the signals 17 and 16, respectively, whereby either the request 13 or 
10 which has not yet been set is inhibited in the same manner as described 
hereinbefore in conjunction with FIG. 1. However, in contrast to the 
circuit arrangement shown in FIG. 1 where the selecting circuit 8 is 
enabled or opened by the signal 14 or 15, the selecting circuit 8 of the 
arrangement shown in FIG. 5 is enabled by the select signal 27 or 28 which 
is constantly applied thereto from a clock 11 through the NOR/OR gate 22 
independently from the access request signal 10 or the refresh request 
signal 12. More specifically, the select signal 27 is previously generated 
from the clock 11 at the time points at which the access request 10 is 
supplied (refer to the inverted triangular marks in FIG. 6), while the 
select signal 28 is previously produced as derived from the clock 11 at 
the time points at which the synchronized refresh request signal 13 is 
generated (refer to the triangular marks in FIG. 6). The clock 11 is 
further used to enable the delay circuit 23 and the Exclusive-OR circuit 
24 to thereby generate a timing signal 29. This timing signal 29 is such 
that the delay circuit 23 generates a pulse having a width large enough to 
trigger the register 9 and that the gate 26 is opened by the Exclusive-OR 
circuit 24 with the timing represented by symbols (.gradient.) and 
(.DELTA.). Additionally, in order to hold in the address register 9 the 
address signal 18 or refresh address signal 19 which is received through 
the selecting circuit 8 simultaneously with the access request signal 10 
or refresh request signal 13, the inhibit signal 30 is derived from the 
signal 14 or 15 through the NOR gate 25 to block the AND gate 26 for 
inhibiting the timing signal 29. Assuming now that the access request 10 
is selected, as is illustrated in FIG. 6, the selecting circuit 8 will 
then select the address signal 18 supplied from the BPU, because the 
select signal 27 is logic "1" when the access request is produced. 
Consequently, the address signal 18 makes appearance at the output of the 
selecting circuit 8. Simultaneously with the placing of the access request 
10 in the flip-flop 4, the output signal from the selecting circuit 8 is 
set in the address register 9 under the control of the trigger signal 31. 
When the flip-flop 4 is thus set, the inhibit signal 30 derived from the 
signal 14 for inhibiting the timing signal 29 becomes logic "1", causing 
thereby the trigger signal 31 to be logic "0". As the consequence, the 
contents in the address register 9 is prevented from being updated, 
whereby the address signal 18 is held by the address register 9. In this 
manner, it is possible with the circuit arrangement shown in FIG. 5 and 
described above to set or place the address signal 18 supplied from the 
BPU in the address register 9 simultaneously with the reception of the 
access request signal 10, as is apparent from FIG. 6. 
FIG. 7 illustrates another embodiment of the invention applied to the 
hitherto known memory access selection control circuit described 
hereinbefore in conjunction with FIG. 3. FIG. 8 is a signal-timing diagram 
of the arrangement illustrated in FIG. 7. FIG. 9 illustrates schematically 
a typical access control circuit for the access sources having access to 
the memory unit which circuit is employed in the arrangement shown in FIG. 
7. FIG. 10 illustrates a signal-timing diagram of the access control 
circuit shown in FIG. 9. Referring to FIGS. 7 and 8, reference numeral 50 
denotes a NOR/OR gate, 51, 52 and 53 denote flip-flops, 54 denotes an 
inverter, 55 denotes a clock, 56 and 57 represent a SCUA select signal and 
a SCUB select signal, respectively, 58 represents the output signal of the 
OR gate 42, 59 represents a trigger inhibiting signal, and 60 represents a 
trigger signal. In FIGS. 9 and 10, reference numeral 70 denotes an 
oscillator, 71, 74, 81 and 84 denote AND gates, 72, 73, 75, 82, 83 and 85 
denote flip-flops, 75 and 85 denote registers, 76 and 86 represent clocks, 
77 and 87 represent output signals from the AND gates 71 and 81, 
respectively, and 78 and 88 represent a SCUA-busy signal and a SCUB-busy 
signal. In FIGS. 7 and 9, T.sub.0 -T.sub.3 represent clock signals 
produced from the output of the oscillator 70 illustrated in FIG. 9. Clock 
T.sub.0 is such a signal at 55 in FIG. 8 while clocks T.sub.1 -T.sub.3 are 
generated in synchronism with T.sub.1 -T.sub.3 shown on the top of FIGS. 8 
and 10. Referring to FIG. 9, in the storage control units SCUA and SCUB, 
the flip-flops 72 and 82 are set by the clock signals 76 and 86, 
respectively, which are out of phase with each other by 180.degree., 
whereby the access request signals 44 and 45 are issued. By taking 
advantage of the phase difference of 180.degree., it is first ascertained 
that the memory unit is not being used by the counterpart SCU by 
exchanging the busy signals 78 and 88 between the SCUA and SCUB and 
thereafter the access request signal 44 or 45 is issued. As can be seen 
from FIG. 10, the access request signal 44 from the SCUA is issued at the 
time points marked by the inverted triangular symbols (.gradient.), while 
the access request signal 45 from the SCUB is produced at the time points 
marked by triangles (.DELTA.). The phase difference between these access 
request signals 44 and 45 is equal to 180.degree.. In the case where the 
memory unit is not being used and thus accessible by the storage control 
unit SCUA or SCUB, the address signal accompanying the access request is 
set in the register 75 or 85 from the output 77 or 87 of the AND gate 71 
or 81 to thereby update the address signal 48 or 49 to be supplied to the 
memory unit, in addition to the flip-flop 72 or 82 being set. FIG. 10 is 
based on the assumption that the access request 44 is issued by the SCUA. 
In the circuit arrangement shown in FIG. 7, the operation carried out 
until the flip-flop 40 or 41 has been set with the clock T2 in response to 
the reception of the access request 44 or 45 is same as in the circuit 
arrangement shown in FIG. 3. However, in contrast to the circuit of FIG. 3 
where the selecting circuit 8 is enabled by the signal 46 or 47, which 
respectively are the outputs of the flip-flops 40 and 41 the selecting 
circuit 8 of FIG. 7 is enabled by the select signal 56 or 57 which is 
constantly and repeatedly issued as derived from the clock signal 55 from 
the oscillator 70 through the NOR/OR gate 50 and the flip-flop 51 or 52, 
independently from the issuance of the access request signal 44 or 45. In 
other words, the select signal 56 is previously produced as derived from 
the clock 55 at the time points at which the access request 44 makes 
appearance and which is marked by the inverted triangles (.gradient.), 
while the select signal 57 is produced in a similar manner at the time 
points at which the access request 45 is supplied and which is marked by 
the triangular symbol (.DELTA.). When both of the flip-flops 40 and 41 are 
set, the trigger inhibiting signal 59 is reset to logic level "1", thereby 
to allow the trigger signal 60 for the flip-flops 40 and 41 and the 
address register 9 to be repeatedly generated for every clock signal T2. 
When when the flip-flop 40 or 41 is set upon reception of the access 
request 44 or 45, the trigger inhibiting signal 59 is reset to logic "0" 
by the previously described signal 46 or 47 through the OR gate 42, 
flip-flop 53 and the inverter 54, whereupon the AND gate 43 is blocked and 
thence the trigger signal 60 is reset to logic "0". The address register 9 
is then inhibited from being updated. Thus, the address signal 48 or 49 
which has been received simultaneously with the reception of the access 
request 44 or 45 and placed in the address register 9 through the 
selecting circuit 8 is held as it is. Accordingly, in the case of the 
embodiment now being described, it is possible to set the address signal 
48 supplied from the SCUA in the address register 9 at the timing of the 
clock signal T2 simultaneously with the reception of the access request 
signal 44 issued from the SCUA. Further, by virtue of such arrangement 
that the select signal 56 or 57 can be previously generated, the margin of 
timing for transferring the access request 44 or 45 and the address 48 or 
49 from the SCUA or SCUB even in the same phase can be selected to be 
large without giving adverse influence to the address signal 48 or 49 as 
is in the case of the known circuit arrangement illustrated in FIG. 3. In 
the foregoing, only the address signal has been described as the input 
signal supplied in company with the access request. However, it will 
readily be understood that the input signal may of course include an 
operation mode command signal, data to be stored and the like which are 
sent to the memory unit together with the access request. Besides, the 
invention can equally be applied to the case where three or more access 
sources are present. In the case of three access sources, the phase 
difference of the clock signals allotted to the access requests from the 
individual access sources is selected equal to 120.degree. as shown in 
FIG. 11, wherein the access requests from the three sources are scanned 
sequentially with equal interval. It goes without saying that the 
invention can be applied to the system where four or more access sources 
are provided through corresponding modifications which fall within the 
scope of the invention. Furthermore, the invention can be applied also to 
the case where the access sources issue the respective access requests at 
different frequencies, so far as the scanning of the access requests is 
carried out periodically. For example, the invention can be applied also 
to the signal sequence illustrated in FIG. 12 in which different access 
requests B and C are issued once while access request A is issued twice in 
the meantime. 
As will be appreciated from the foregoing description, the invention 
provides an access request selecting circuit for selectively accepting 
access request signals from a plurality of access request sources, in 
which a high speed operation is assured for a memory apparatus by virtue 
of the arrangement that delay of acceptance of input signals associated 
with memory request signals can be suppressed.