Nonvolatile memory device that stores data from completed write requests on a power abnormality

According to an embodiment, a memory device includes a nonvolatile memory, a controller, and power storage. The controller is configured to receive, from a host device, a write request for writing data into the nonvolatile memory, and then, write the data based on the write request. The power storage is configured to store power supplied from a power supply. The controller writes, when abnormality in power supplied from the power supply to the memory device is detected, the data based on the write request that has already been received, using the power supplied from the power storage.

CROSS-REFERENCE TO RELATED APPLICATION

This application is based upon and claims the benefit of priority from Japanese Patent Application No. 2015-060811, filed on Mar. 24, 2015; the entire contents of which are incorporated herein by reference.

FIELD

Embodiments described herein relate generally to a memory device, a semiconductor device, and an information processing device.

BACKGROUND

Suppose that a failure occurs in a computer system that uses, as a main memory, a byte-addressable nonvolatile memory, such as an MRAM, a PCM, or memristors, that can be directly connected to a memory bus of a processor. In that case, in order to be capable of continuing processing from a consistent state immediately before the failure occurred, the computer system needs to ensure ordering (property of orderliness) and atomicity (property of not stopping writing halfway) of writing into the nonvolatile memory performed by a computer program executed on the processor.

For example, a technique for ensuring the atomicity is known in which a capacitor is provided to ensure that a memory controller connected to a CPU (memory controller of a host device, from another point of view) completes the writing of data into the nonvolatile memory when power supply is lost.

With increases in operation speed of memories, recent years have seen the development of memory devices (such as Hybrid Memory Cube (HMC) and QuickPath Interconnect (QPI) memory devices) each provided thereon with a controller for writing of data into the memory. The memory controller of the processor (memory controller of the host device) connected to each of such memory devices recognizes that the writing of data is completed when transmission of the data (transmission of the writing target data) to the memory device is completed.

The writing target data that has been transmitted to the memory device is, however, written into the memory further via the controller of the memory device, so that the writing target data has not necessarily reached memory cells in the memory at the time when the memory controller of the processor recognizes that the writing of the data is completed. If power supply abnormality occurs (abnormality in power supplied from the power supply occurs) at this moment, a problem occurs in that the data currently being written is lost, or a problem occurs in that incomplete data is written, so that the atomicity cannot be ensured.

DETAILED DESCRIPTION

According to an embodiment, a memory device includes a nonvolatile memory, a controller, and power storage. The controller is configured to receive, from a host device, a write request for writing data into the nonvolatile memory, and then, write the data based on the write request. The power storage is configured to store power supplied from a power supply. The controller writes, when abnormality in power supplied from the power supply to the memory device is detected, the data based on the write request that has already been received, using the power supplied from the power storage.

The following describes in detail embodiments of a memory device, a semiconductor device, and an information processing device according to the present invention, with reference to the accompanying drawings.

First Embodiment

The following describes the outline of a first embodiment before explaining the specific details thereof. As described above, a memory controller of a processor (memory controller of a host device) connected to a memory device provided thereon with a controller recognizes that the writing of data is completed when transmission of the data (transmission of the writing target data) to the memory device is completed. The writing target data that has been transmitted to the memory device is, however, written into the memory further via the controller of the memory device, so that the writing target data has not necessarily reached memory cells in the memory at the time when the memory controller of the processor recognizes that the writing of the data is completed. If power supply abnormality occurs at this moment, the problem occurs in that the data currently being written is lost, or the problem occurs in that incomplete data is written.

In addition, interfaces, such as Hybrid Memory Cube (HMC), each for connecting a latest memory device to a processor (here, including a processor core (CPU) and a memory controller) are provided with write requests for data of a plurality of different data sizes, such as 4, 8, 16, 32, and 64 bytes, and can use a different write request according to a command of the processor. The length of the entire write request varies depending on the size of data to be written. The write request is forwarded over a plurality of clock cycles from the processor to the memory device. The size of the write request issued by the processor is normally often set to the same size as that of a cache line (for example, to 64 bytes). In the case of forwarding the write request over a plurality of clock cycles as described above, if the power supply abnormality occurs while the write request is forwarded, the write request may stop being forwarded halfway, or the transmitted information may have an incorrect value. In such a case, the controller (controller of the memory device) should not write data based on the write request that is received halfway. Moreover, even in the case of forwarding the information constituting the write request in parallel from the processor to the memory device, for example, in one clock cycle, the information may fail to be correctly forwarded if the power supply abnormality occurs.

In the present embodiment, after receiving the write request from the memory controller of the processor serving as the host device, the controller of the memory device temporarily stores the received write request in a volatile buffer memory, and, if the entire write request has been correctly received, writes the entire write request into a nonvolatile memory. The controller of the memory device determines whether the entire write request has been correctly received by determining whether information having a size corresponding to that of the write request is received. The size of data of the write request is obtained by referring to the head part (header) of the write request, and the length of the entire write request is obtained based on the obtained size, so that the controller of the memory device can determine whether the entire write request has been correctly received by determining whether the write request having the obtained length is successfully received. Moreover, if, for example, the write request includes a checking code, such as a CRC, the controller of the memory device may use the checking code to check whether the information includes any error. In addition, the controller of the memory device may combine various checking schemes to determine whether the write request has been correctly received.

In the present embodiment, if the abnormality in the power supplied from the power supply to the memory device is detected, the controller of the memory device does not write the data included in the write request currently being received from the processor into the nonvolatile memory. If the controller of the memory device has already received the write request (has already fully received the write request), the controller of the memory device writes data based on the already received write request, using power supplied from power storage for storing the power supplied from the power supply. This operation can ensure the atomicity.

The following describes the specific details of the present embodiment with reference to the accompanying drawings.

FIG. 1is a diagram illustrating an example of the hardware configuration of an information processing device1of the present embodiment. The information processing device1can be constituted by, for example, a server, a personal computer (PC), a mobile information terminal (including a portable tablet computer), or a mobile phone. As illustrated inFIG. 1, the information processing device1of the present embodiment includes a processor10, a memory device20, and a power supply30. In the example ofFIG. 1, the memory device20has one port for accessing that is connected to the processor10, but is not limited to this configuration. The power supply30is a device for supplying power to the information processing device1, and supplies the power to each of the processor10and the memory device20.

The processor10is an example of the host device, and includes a processor core (also called a central processing unit (CPU))11, a cache memory12, and a memory controller13.

In a procedure in which a computer program executed by the processor core11writes data into the memory device20, writing target data is first written into the cache memory12. To write the data written in the cache memory12into the memory device20, the memory controller13issues a write request to the memory device20at an appropriate timing. The write request in the present embodiment includes at least the writing target data and address information indicating a location in a nonvolatile memory21of the memory device20into which the writing target data is to be written. To read data from the memory device20, the memory controller13issues a read request according to a command from the processor core11. The read request in the present embodiment includes at least address information indicating a location in the nonvolatile memory21of the memory device20in which the reading target data is stored. In the following description, the write request and the read request will be called simply the “request”, when not distinguished, in some cases.

The following describes the configuration of the memory device20. As illustrated inFIG. 1, the memory device20includes the nonvolatile memory21, a controller22, power storage23, and a rectifying device (diode in this example)31. The memory device20can be considered to be an example of the semiconductor device.

In the present embodiment, the nonvolatile memory21is constituted by a magnetoresistive random access memory (MRAM), but is not limited to this constitution. The nonvolatile memory21may be, for example, a phase-change memory (PCM), a resistive random access memory (ReRAM), a ferroelectric random access memory (FeRAM), or memristors, or may also be an NVDIMM that combines a dynamic random access memory (DRAM) with a NAND flash memory. The nonvolatile memory21may alternatively be a DRAM or an SRAM backed up by a battery.

FIG. 2is a diagram illustrating an example of the schematic configuration of the nonvolatile memory21in the present embodiment. As illustrated inFIG. 2, the nonvolatile memory21includes a nonvolatile memory cell array201and a row buffer (page buffer)202that is a volatile memory.

Although no details are illustrated, a plurality of word lines extending in the row direction (in the right-left direction ofFIG. 2) and a plurality of bit lines extending in the column direction (in the up-down direction ofFIG. 2) are arranged in the nonvolatile memory cell array201, and the nonvolatile memory cell array201includes a plurality of memory cells arranged in a matrix corresponding to intersections between the word lines and the bit lines. Also, although no details are illustrated, the nonvolatile memory cell array201includes, for example, a circuit for controlling the voltage of each of the word lines and a circuit for controlling the voltage of each of the bit lines, both under the control of the controller22. The configuration described above can employ various known configurations. In this example, the data size of a plurality of memory cells connected to one word line is called a “page”. The row buffer202temporarily stores data for one page corresponding to a word line selected at the time of data writing or data reading. In the present embodiment, data is written into the nonvolatile memory21or read from the nonvolatile memory21through the row buffer202, which is the same as a known method.

The description will be continued referring back toFIG. 1. After receiving the write request requesting the writing of the data into the nonvolatile memory21from the memory controller13of the processor10, the controller22writes the data based on the write request. Also, after receiving the read request requesting the reading of the data from the nonvolatile memory21from the memory controller13of the processor10, the controller22reads the data based on the read request.

If the abnormality in the power supplied from the power supply30to the memory device20is detected, the controller22of the present embodiment writes the data based on the already received write request, using the power supplied from the power storage23for storing the power supplied from the power supply30. From another point of view, the controller22can be considered to write the data based on the already received write request, using the power supplied from the power storage23for storing the power supplied from the power supply30if the abnormality in the power supplied from the power supply30to the “semiconductor device” is detected. The controller22can also be considered to write the data based on the already received write request, using the power supplied from the power storage23for storing the power supplied from the power supply30if the abnormality in the power supplied from the power supply30to the “information processing device1” is detected.

The controller22of the present embodiment monitors the voltage of the power supplied from the power supply30to the memory device20, and determines (recognizes) that the abnormality has occurred if the voltage drops to or below a threshold. Specifically, the controller22writes the data based on the already received write request, using the power supplied from the power storage23for storing the power supplied from the power supply30if the voltage of the power supplied from the power supply30to the memory device20drops to or below the threshold. From another point of view, the controller22can be considered to write the data based on the already received write request, using the power supplied from the power storage23for storing the power supplied from the power supply30if the voltage of the power supplied from the power supply30to the “semiconductor device” drops to or below the threshold. The controller22can also be considered to write the data based on the already received write request, using the power supplied from the power storage23for storing the power supplied from the power supply30if the voltage of the power supplied from the power supply30to the “information processing device1” drops to or below the threshold.

If the abnormality in the power supplied from the power supply30to the memory device20is detected, the controller22of the present embodiment stops receiving the write request. In addition, if the abnormality in the power supplied from the power supply30to the memory device20is detected, the controller22does not write the data based on the write request currently being received from the memory controller13of the processor10. Details of the controller22of the present embodiment will be described later.

The power storage23stores the power supplied from the power supply30. The amount of the power stored by the power storage23is an amount of power required for at least completing the writing into the nonvolatile memory21based on the write request received by the memory device20from the memory controller13of the processor10serving as the host device even when the power supply30has stopped supplying the power. In the present embodiment, the power storage23is constituted by a capacitor, but is not limited to this constitution. The power storage23may be constituted by, for example, a battery. The point is that the power storage23only needs to be a device that can hold the power from the power supply30. In the example ofFIG. 1, the power supplied from the power supply30to the memory device20is supplied to each of the nonvolatile memory21, the controller22, and the power storage23, via the rectifying device31. The operation of the rectifying device31can prevent the power stored in the power storage23from leaking out of the memory device20when the voltage has dropped. In the present embodiment, if the voltage of the power supplied from the power supply30to the memory device20drops to or below the threshold, the output voltage of the power storage23exceeds the voltage of the power supplied from the power supply30, and the power stored in the power storage23is supplied to each of the nonvolatile memory21and the controller22. The power may be switched to be supplied from the power storage23to the nonvolatile memory21and the controller22when the voltage of the power supplied from the power supply30has dropped as illustrated in the example ofFIG. 1, or may be switched to be supplied from the power storage23to the nonvolatile memory21and the controller22in addition to the power from the power supply30when the power supply30does not supply a sufficient amount of power.

FIG. 3is a diagram illustrating an example of the detailed hardware configuration of the memory device20. As illustrated inFIG. 3, the controller22includes a detector210, a receiver211, a first determiner212, a second determiner213, a first writer214, a buffer memory215, a write controller216, a second writer217, a third determiner218, and a reader219. These components are each constituted by a semiconductor circuit, and may be provided independent of each other, or provided such that any two or more components are integrated.

The detector210detects the abnormality in the power supplied from the power supply30to the memory device20. More specifically, the detector210monitors the power supplied from the power supply30to the memory device20, and determines that the abnormality has occurred if the voltage of the power supplied from the power supply30drops to or below the threshold. After detecting the abnormality in the power supplied from the power supply30to the memory device20, the detector210notifies each of the receiver211and the second determiner213that the abnormality has occurred. The method for detecting the abnormality in the power supplied from the power supply30to the memory device20is not limited to the method in which the detector210measures the voltage of the power supplied from the power supply30to the memory device20, but may be, for example, a method in which the detector210receives a signal indicating the abnormality in the power from an external device, such as the power supply30or the processor10.

The receiver211receives the request (the write request or the read request) from the memory controller13of the processor10. The controller22of the present embodiment receives the request (the write request or the read request) over a plurality of clock cycles. Hence, the receiver211can be considered to sequentially receive a plurality of pieces of information constituting the request (called “request information” in some cases in the following description) from the memory controller13. In the present embodiment, if the notification of the abnormality occurrence is received from the detector210, the receiver211stops receiving the subsequent request (request information).

The first determiner212determines whether the request information received by the receiver211corresponds to a write request or a read request. Various methods can be considered to make this determination. For example, if the request information corresponding to the header of the request has a format including command information for identifying the type of a command (for identifying whether the command is the write request or the read request), the first determiner212refers to the command information included in the request information corresponding to the header of the request received by the receiver211, and thus can determine whether the request information and certain pieces of request information subsequent thereto correspond to the write request or the read request.

The second determiner213determines whether the entire write request has been correctly received. In the present embodiment, whether the entire write request has been correctly received can be determined based on whether a request information group having a data size (predetermined data size) of the entire write request (request information group constituting the write request) has been received. That is, if the total size of the request information group corresponding to the write request received by the receiver211over a plurality of clock cycles reaches the predetermined data size, the second determiner213can determine that the entire write request has been correctly received. Moreover, if, for example, the write request includes a checking code, such as the CRC, the second determiner213may use the checking code to check whether the information includes any error. In addition, the second determiner213may combine various checking schemes to determine whether the write request has been correctly received.

If the second determiner213determines that the write request has been received (determines that the entire write request has been correctly received), the second determiner213commands the first writer214to write write information corresponding to the received write request (in other words, the write request that has been fully received) into the buffer memory215.

In the present embodiment, if the second determiner213receives the notification of the abnormality occurrence from the detector210, the second determiner213discards the write request currently being received from the memory controller13of the processor10. Specifically, if the total size of the already received request information group corresponding to the write request has not reached the predetermined data size when the second determiner213receives the notification of the abnormality occurrence from the detector210, the second determiner213discards the already received request information group. This operation prevents the memory device20from being brought into an inconsistent state in which only a part of the writing target data is written (state in which the writing stops halfway in the process).

After being commanded by the second determiner213, the first writer214writes the write information corresponding to the fully received write request into the buffer memory215. The write information includes at least the writing target data and the address information indicating the location in the nonvolatile memory21into which the writing target data is to be written. In this example, the first writer214writes the write request itself as the write information into the buffer memory215, but the write information is not limited to the write request itself.

After writing the write information corresponding to the fully received write request (the write request itself, in this example) into the buffer memory215, the first writer214notifies the write controller216of information indicating that the write information has been written into the buffer memory215, in addition to information indicating the location in the buffer memory215into which the write information has been written (hereinafter, called “buffer location information” in some cases). After receiving this notification, the write controller216commands the second writer217to write the data based on the write request written in the location in the buffer memory215indicated by the buffer location information given by the first writer214.

After receiving the write command from the write controller216, the second writer217reads the write information written in the location in the buffer memory215indicated by the buffer location information (included in the write command, in this example) received from the write controller216, and writes the data based on the read-out write information. As described above, the write information includes the address information indicating the location in the nonvolatile memory21into which the writing target data is to be written. In this example, the higher part of the address information serves as a row address indicating any one of the word lines, and the lower part of the address information serves as a column address indicating any one of the bit lines. The second writer217performs control in which data of one page (page data) corresponding to a word line indicated by the row address in the higher part of the address information included in the write information read from the buffer memory215is read out into the page buffer202. Then, the second writer217controls the voltage supplied to the bit line indicated by the column address in the lower part of the address information so as to write the data (data corresponding to the writing target data included in the write request) to the page data in the page buffer202. The second writer217writes the page data to which the data is written back to the memory cells connected to the word line indicated by the row address, and thus completes the writing into the nonvolatile memory21.

In short, the controller22of the present embodiment further includes the buffer memory215for temporarily storing information, and the controller22stores writing target data included in the write request received from the memory controller13of the processor10in the buffer memory215, and then, writes the data based on the writing target data stored in the buffer memory215.

The description will be continued with reference toFIG. 3. The third determiner218determines whether the entire read request has been correctly received. The method of this determination is basically the same as the method of determining whether the entire write request has been correctly received. If the third determiner218determines that the read request has been received, the third determiner218commands the reader219to read the data corresponding to the received read request (fully received read request).

After receiving the read command from the third determiner218, the reader219reads the data stored in the location in the nonvolatile memory21indicated by the address information included in the read request (included in the read command, in this example) received from the third determiner218, and sends the read-out data as a response (reply) to the memory controller13of the processor10.

FIG. 4is a flowchart illustrating an operation example of the controller22when the request information has been received from the memory controller13of the processor10. First, the receiver211receives the request information (Step S1). Then, the first determiner212determines whether the request information received at Step S1corresponds to a write request (Step S2).

If the request information received at Step S1described above corresponds to a write request (Yes at Step S2), the second determiner213determines whether the entire write request has been correctly received (Step S3). If the entire write request has been correctly received (Yes at Step S3), the second determiner213commands the first writer214to write the write information corresponding to the received write request into the buffer memory215. After being commanded by the second determiner213, the first writer214writes the write information corresponding to the fully received write request into the buffer memory215(Step S4). After writing the write information corresponding to the fully received write request into the buffer memory215, the first writer214notifies the write controller216of the information indicating that the write information has been written into the buffer memory215, in addition to the buffer location information. After receiving this notification, the write controller216commands the second writer217to write the data based on the write information written in the location in the buffer memory215indicated by the buffer location information given by the first writer214(Step S5). After receiving the write command from the write controller216, the second writer217writes the data into the nonvolatile memory21(Step S6).

FIG. 5is a flowchart illustrating an example of the detailed operation at Step S6. As illustrated inFIG. 5, the second writer217first receives the write command from the write controller216(Step S11). The second writer217then reads the write information written in the location in the buffer memory215indicated by the buffer location information (included in the write command, in this example) received from the write controller216(Step S12). The second writer217then write the data based on the write information read at Step S12(Step S13).

The description will be continued referring back toFIG. 4. If, at Step S2described above, the request information received at Step S1does not correspond to a write request (No at Step S2), in other words, if the request information received at Step S1corresponds to a read request, the third determiner218determines whether the entire read request has been correctly received (Step S7). If the entire read request has been correctly received (Yes at Step S7), the third determiner218commands the reader219to read the data corresponding to the received read request (Step S8). After receiving the read command from the third determiner218, the reader219reads the data from the nonvolatile memory21(Step S9). More specifically, the reader219reads the data stored in the location in the nonvolatile memory21indicated by the address information included in the read request (included in the read command, in this example) received from the third determiner218, and sends the read-out data as a response (reply) to the memory controller13of the processor10.

The following describes, usingFIG. 6, an operation example of the controller22when the controller22(detector210) has detected the abnormality in the power supplied from the power supply30to the memory device20. The flowchart ofFIG. 6assumes that the voltage of the power supplied from the power supply30to the memory device20has dropped to or below the threshold, and, as a result, the detector210has detected that the abnormality in the power has occurred and has notified each of the receiver211and the second determiner213that the abnormality has occurred. Because the voltage of the power supplied from the power supply30to the memory device20has dropped to or below the threshold, the state of the power of the memory device20has been switched to the state in which the power stored in the power storage23is supplied to each of the nonvolatile memory21and the controller22.

After receiving the notification of the abnormality occurrence from the detector210, the receiver211stops receiving the subsequent request (request information) (Step S21). Also, after receiving the notification of the abnormality occurrence from the detector210, the second determiner213determines whether any write request is currently being received from the memory controller13of the processor10(Step S22). If any write request is currently being received from the memory controller13of the processor10(Yes at Step S22), the second determiner213discards the write request currently being received (Step S23).

If, instead, the write request has already been fully received when the detector210detects the abnormality, the power supplied from the power storage23is used to write the data based on the already fully received write request. If the power storage23is constituted by a capacitor as in the present embodiment, the capacity of the capacitor is set to a value that allows the capacitor to store the amount of power required for at least writing the data based on the already received write request when the abnormality has occurred in the power supplied from the power supply30to the memory device20. The capacity of the capacitor may be set, for example, to a value that allows the capacitor to store an amount of power allowing processing of all write requests that can be held in the buffer memory215.

As described above, if the abnormality in the power supplied from the power supply30to the memory device20is detected, the controller22of the memory device20uses the power supplied from the power storage23to write the data based on the already received write request. That is, if the abnormality occurs in the power supplied from the power supply30to the memory device20, the power supplied from the power storage23can be used to complete the writing based on the already fully received write request. As a result, according to the present embodiment, the atomicity can also be ensured with the configuration in which the memory device20is provided with the controller22.

First Modification of First Embodiment

The memory device20may have, for example, a configuration including a plurality of access ports.

For example, connecting the memory device20to the processor10via a plurality of access ports can increase the data transfer capacity. For example, the memory device20may include two access ports, as illustrated inFIG. 7. The bandwidth of the data transfer can be doubled by connecting the memory device20to the processor10using the two access ports in this way.

Alternatively, for example, the memory device20can be connected to a plurality of processors10. For example, as illustrated inFIG. 8, two processors10aand10bcan be connected to the memory device20having two access ports. This example allows the processors10aand10bto share data with each other.

The configuration may, for example, be such that the memory device20is connected to the processor10and another memory device (hereinafter, called a “second memory device200”), and forwards the write request from the processor10to the second memory device200as needed. The configuration may be such that the memory device20is connected to the second memory device200as illustrated inFIG. 9, and, if the controller22of the memory device20receives, from the memory controller13of the processor10, a second write request requesting writing of data into the second memory device200, the controller22forwards the second write request to the second memory device200.

In the case of the cascade connection as illustrated inFIG. 9, the processor10recognizes that the writing is completed when the write request has been fully transmitted to the memory device20directly connected to the processor10. Hence, the memory device20that has received the second write request to be forwarded to the second memory device200forwards the second write request to the second memory device200using the power from the power storage23even if the abnormality occurs in the power supplied from the power supply30to the memory device20.

That is, in the example ofFIG. 9, if the abnormality in the power supplied from the power supply30to the memory device20is detected, the controller22of the memory device20uses the power supplied from the power storage23to forward the already received second write request to the second memory device200.

The configuration can, for example, be such that the second memory device200is connected to a second processor100(an example of a second host device) other than the processor10, as illustrated inFIG. 10. The basic configuration of the second processor100is the same as the configuration of the processor10. In this example, the controller22of the memory device20receives, from the second memory device200, a third write request through which the second processor100requests writing of data into the nonvolatile memory21, and then, writes the data based on the third write request. The controller22receives, from the second memory device200, a second read request through which the second processor100requests reading of data from the nonvolatile memory21, and then, reads the data corresponding to the second read request. In this example, as illustrated inFIG. 11, the memory device20includes two access ports (an access port for the processor10and an access port for the second memory device200). In the example ofFIG. 11, the memory device20can accept requests from both the processor10and the second memory device200.

The configuration ofFIGS. 10 and 11complicates the operation of the memory device20when the abnormality in the power supplied from the power supply30to the memory device20is detected. That is explained as follows: after detecting the abnormality in the power, the memory device20stops receiving the write request from the processor10; then, if the request already received at that moment is a write request requesting writing of data into the memory device20, the memory device20needs to write the data based on the write request; or, if the request is a write request (second write request) requesting writing of data into the other memory device (second memory device200), the memory device20needs to surely complete forwarding the request to the other memory device. In addition, if the memory device20detects the abnormality in the power, the memory device20needs to stop receiving the request from the processor10directly connected to the memory device20. However, if a request (the third write request or the second read request, in this example) already received at that moment by the other memory device (second memory device200, in this example) from the other processor (second processor100, in this example) is forwarded to the memory device20, the memory device20needs to surely receive the request.

Accordingly, in this example, if any third write request is currently being received from the second memory device200when the abnormality in the power supplied from the power supply30to the memory device20is detected, the controller22of the memory device20uses the power supplied from the power storage23to continue receiving the third write request from the second memory device200. The controller22then uses the power supplied from the power storage23to write the data based on the third write request that has been fully received.

FIG. 12is a flowchart illustrating an operation example of the controller22when the controller22(detector210) in the configuration ofFIGS. 10 and 11has detected the abnormality in the power supplied from the power supply30to the memory device20. The flowchart ofFIG. 12assumes that the voltage of the power supplied from the power supply30to the memory device20has dropped to or below the threshold, and, as a result, the detector210has detected that the abnormality in the power has occurred. Because the voltage of the power supplied from the power supply30to the memory device20has dropped to or below the threshold, the state of the power of the memory device20has been switched to the state in which the power stored in the power storage23is supplied to each of the nonvolatile memory21and the controller22.

First, the detector210commands the receiver211to stop receiving the request from the processor10. After receiving the command, the receiver211stops receiving the subsequent request from the processor10(Step S31). The detector210then queries the second determiner213to determine whether any request is currently being received from the second memory device200(Step S32). Various methods can be considered to determine whether the request received by the receiver211is a request transmitted from the processor10or a request forwarded from the second memory device200. For example, when the memory device20is initialized, a setting is made as to whether each of the access ports is connected to the processor10or the second memory device200, and the determination can be made as to whether the received request is the request from the processor10or the request from the second memory device200, according to which of the access ports has received the request. The configuration may, for example, be such that the request includes flag information indicating whether the processor10has transmitted the request, or the second memory device200has forwarded the request.

If no request is currently being received from the second memory device200(No at Step S32), the detector210commands the receiver211to stop receiving the request from the second memory device200. After receiving the command, the receiver211stops receiving the subsequent request from the processor10(Step S33).

If, instead, any request is currently being received from the second memory device200(Yes at Step S32), the detector210commands the receiver211to continue receiving the request from the second memory device200. After receiving the command, the receiver211continues receiving the request from the second memory device200(Step S34). After the receiver211receives the request information (information constituting the request) from the second memory device200(Step S35), the first determiner212determines whether the request information received at Step S1corresponds to the third write request (Step S36). The method of this determination is the same as the method described above in the first embodiment. Processing details of subsequent Steps S37to S43are the same as the processing details of Steps S3to S9ofFIG. 4, so that detailed description thereof will not be made. If, at Step S37ofFIG. 12, the entire third write request is determined to have been correctly received (Yes at Step S37), or if, at Step S41ofFIG. 12, the entire second read request is determined to have been correctly received (Yes at Step S41), the subsequent request (request information) from the second memory device200may stop being received.

The same problem as the above described problem lies, for example, in a configuration in which the memory device20is not directly connected to the processor10, and receives the request (the write request or the read request) from the processor10via the second memory device200, as illustrated inFIG. 13. That is, if, when the abnormality in the power is detected, the request (the write request or the read request) to the memory device20is forwarded that has already been received by the second memory device200from the processor10, the memory device20needs to surely receive the request.

With the configuration ofFIG. 13, the controller22of the memory device20receives, from the second memory device200connected to the memory device20, the write request through which the processor10(an example of the host device) requests the writing of the data into the nonvolatile memory21, and then, writes the data based on the write request. If the abnormality in the power supplied from the power supply30to the memory device20is detected, the controller22uses the power supplied from the power storage23to write the data based on the already received write request, and, if any write request is currently being received from the second memory device200, the controller22uses the power supplied from the power storage23to continue receiving the write request from the second memory device200.

In the above-described way, even in the case of using a combination of a plurality of memory devices, when one or more processors connected to any of the memory devices transmits (or transmit) a write request (or write requests) (including the second write request and the third write request described above) to any of the memory devices before the abnormality in the power occurs, the write request (or write requests) can be guaranteed to be forwarded to a target memory device (or target memory devices) without fail, and the data based on the write request (or write requests) can be guaranteed to be written.

Second Modification of First Embodiment

The configuration may, for example, be such that the power storage23and the rectifying device31are provided outside the memory device20, as illustrated inFIG. 14. In short, the configuration may be such that the memory device20includes the above-described nonvolatile memory21and the above-described controller22, and, if the abnormality in the power supplied from the power supply30to the memory device20is detected, the above-described controller22writes the data based on the already received write request, using the power supplied from the power storage23for storing the power supplied from the power supply30. From another point of view, the configuration may be such that the semiconductor device includes the above-described nonvolatile memory21and the above-described controller22, and, if the abnormality in the power supplied from the power supply30to the semiconductor device is detected, the controller22writes the data based on the already received write request, using the power supplied from the power storage23for storing the power supplied from the power supply30. The configuration may also be such that the information processing device1includes the above-described processor10, the above-described nonvolatile memory21, and the above-described controller22, and, if the abnormality in the power supplied from the power supply30to the information processing device1is detected, the controller22writes the data based on the already received write request, using the power supplied from the power storage23for storing the power supplied from the power supply30.

In the example ofFIG. 14, the configuration can be considered to be such that the memory device20includes the above-described nonvolatile memory21and the above-described controller22, and, if the voltage of the power supplied from the power supply30to the memory device20drops to or below the threshold, the above-described controller22writes the data based on the already received write request, using the power supplied from the power storage23for storing the power supplied from the power supply30. From another point of view, the configuration can be considered to be such that the semiconductor device includes the above-described nonvolatile memory21and the above-described controller22, and, if the voltage of the power supplied from the power supply30to the semiconductor device drops to or below the threshold, the controller22writes the data based on the already received write request, using the power supplied from the power storage23for storing the power supplied from the power supply30. The configuration can also be considered to be such that the information processing device1includes the above-described processor10, the above-described nonvolatile memory21, and the above-described controller22, and, if the voltage of the power supplied from the power supply30to the information processing device1drops to or below the threshold, the controller22writes the data based on the already received write request, using the power supplied from the power storage23for storing the power supplied from the power supply30.

Third Modification of First Embodiment

A case can be considered in which the memory device20includes therein a plurality of dies or chips of the nonvolatile memories21, as in the case of, for example, an HMC memory device. Hence, the configuration may be such that the memory device20includes a plurality of the nonvolatile memories21, as illustrated inFIG. 15. Although the example ofFIG. 15does not illustrate the third determiner218and the reader219for convenience of layout, the configuration is the same as that of the first embodiment described above, except in that a plurality of the nonvolatile memories21are provided, and a plurality of the second writers217are provided corresponding to the nonvolatile memories21on a one-to-one basis.

For example, after writing the write information corresponding to the fully received write request (the write request itself, in this example) into the buffer memory215, the first writer214can notify the write controller216of information indicating that the write information has been written into the buffer memory215, in addition to the buffer location information indicating the location in the buffer memory215into which the write information has been written and nonvolatile memory information indicating one of the nonvolatile memories21corresponding to the write request (one of the nonvolatile memories21identified by the address information included in the write request). After receiving this notification, the write controller216can command one of the second writers217corresponding to the nonvolatile memory21indicated by the nonvolatile memory information given by the first writer214to write the data based on the write information written in the location in the buffer memory215indicated by the buffer location information given by the first writer214.

Moreover, instead of being provided with the common buffer memory215, the memory device20may be provided with a plurality of the buffer memories215corresponding to the nonvolatile memories21on a one-to-one basis (corresponding to the second writers217on a one-to-one basis, from another point of view). With this configuration, the first writer214may write the write information corresponding to the fully received write request (the write request itself, in this example) into one of the buffer memories215corresponding to one of the nonvolatile memories21identified by the address information included in the write request, and may then notify corresponding one of the write controllers216of information indicating that the write information has been written into the buffer memory215, in addition to the buffer location information indicating the location in the buffer memory215into which the write information has been written.

The number of the access ports included in the memory device20illustrated inFIG. 15may be one or two or more, or may be set to any value.

FIG. 16is a schematic diagram illustrating an example of a packaging method of the memory device20of the present modification. This packaging method is a method in which a plurality of silicon dies of the nonvolatile memories21and a silicon die of the controller22are connected using a technology, such as a TSV technology, and sealed in a package, as in the case of the HMC memory device. A modification of this packaging method may be used in which the silicon dies of the nonvolatile memories21and the silicon die of the controller22are connected on a silicon interposer to be formed as the 2.5D-packaged memory device20. While the example ofFIG. 16illustrates a configuration in which the memory device20incorporates the power storage23, the power storage23may be provided external to the memory device20, as illustrated inFIG. 17.

FIG. 18is a schematic diagram illustrating still another example of the packaging method of the memory device20. This packaging method is a method in which the controller22and the nonvolatile memories21(the number of the nonvolatile memories21may be plural, as in the present modification, or one, as in the first embodiment described above) are integrated in one silicon die, and the silicon die is sealed in one package. The silicon die ofFIG. 18can be housed alone in the package to be put into operation as the memory device20, or the silicon die and the power storage23can be housed in the package to be put into operation as the memory device20, as illustrated inFIG. 19.

The packaging method of the memory device20is not limited to the above-described examples, but various packaging methods can be used. The packaging method of the memory device20can employ, for example, a method in which one or more chips of the nonvolatile memories21and a chip of the controller22are mounted on a printed circuit board.

Second Embodiment

The following describes a second embodiment. Description will be omitted for parts common to those in the first embodiment described above, where appropriate.FIG. 20is a diagram illustrating an example of the detailed hardware configuration of the memory device20of the present embodiment. As illustrated inFIG. 20, the controller22differs from that of the first embodiment described above in further including a nonvolatile cache memory222, and in including a third writer221and a fourth writer223, instead of the second writer217described above.

The write request received by the controller22becomes permanent when written, not into the nonvolatile memory21, but into the higher-speed nonvolatile cache memory222. In the present embodiment, if the second determiner213determines that the entire write request has been correctly received, the second determiner213commands the first writer214to write the write information corresponding to the received write request (in this example, the write request itself, but not limited thereto) into the buffer memory215.

After being commanded by the second determiner213, the first writer214writes the write information corresponding to the fully received write request into the buffer memory215. After writing the write information corresponding to the fully received write request into the buffer memory215, the first writer214notifies the write controller216of information indicating that the write information has been written into the buffer memory215, in addition to the buffer location information indicating the location in the buffer memory215into which the write information has been written.

After receiving the notification from the first writer214, the write controller216commands the third writer221to write the write information written in the location in the buffer memory215indicated by the buffer location information given by the first writer214into the nonvolatile cache memory222.

After receiving the write command from the write controller216, the third writer221reads the write information written in the location in the buffer memory215indicated by the buffer location information (included in the write command, in this example) received from the write controller216. The third writer221then writes the read-out write information (the write request itself, in this example) into the nonvolatile cache memory222.

The fourth writer223writes the data based on the write information written in the nonvolatile cache memory222(into the nonvolatile memory21) at an appropriate time.

In the same way as in the first embodiment described above, after receiving the notification of the abnormality occurrence from the detector210, the receiver211stops receiving the subsequent request. Also, after receiving the notification of the abnormality occurrence from the detector210, the second determiner213determines whether any write request is currently being received from the memory controller13of the processor10. If any write request is currently being received from the memory controller13of the processor10, discards the write request currently being received. If, instead, the write request has already been fully received when the detector210detects the abnormality, the power supplied from the power storage23is used to write the write information corresponding to the already fully received write request into the nonvolatile cache memory222.

The above is summarized as follows: the memory device20of the present embodiment includes the above-described nonvolatile cache memory222, the controller22, and the power storage23for storing the power supplied from the power supply30, where the controller22receives, from the memory controller13of the processor10, the write request requesting the writing of the data into the nonvolatile memory21, and then writes the write information corresponding to the write request into the nonvolatile cache memory; and, if the abnormality in the power supplied from the power supply30to the memory device20is detected, the controller22uses the power supplied from the power storage23to write the write information corresponding to the already received write request into the nonvolatile cache memory222. From another point of view, the configuration can be considered to be such that the semiconductor device includes the above-described nonvolatile cache memory222, the above-described controller22, and the power storage23for storing the power supplied from the power supply30, and, if the abnormality in the power supplied from the power supply30to the “semiconductor device” is detected, the controller22uses the power supplied from the power storage23to write the write information corresponding to the already received write request into the nonvolatile cache memory222. The configuration can also be considered to be such that the information processing device1includes the above-described processor10, the above-described nonvolatile cache memory222, the above-described controller22, and the power storage23for storing the power supplied from the power supply30, and, if the abnormality in the power supplied from the power supply30to the “information processing device1” is detected, the controller22uses the power supplied from the power storage23to write the write information corresponding to the already received write request into the nonvolatile cache memory222.

The configuration can also be considered to be such that the memory device20of the present embodiment includes the above-described nonvolatile cache memory222, the above-described controller22, and the power storage23for storing the power supplied from the power supply30, and, if the voltage of the power supplied from the power supply30to the memory device20drops to or below the threshold, the controller22uses the power supplied from the power storage23to write the write information corresponding to the already received write request into the nonvolatile cache memory222. From another point of view, the configuration can be considered to be such that the semiconductor device includes the above-described nonvolatile cache memory222, the above-described controller22, and the power storage23for storing the power supplied from the power supply30, and, if the voltage of the power supplied from the power supply30to the “semiconductor device” drops to or below the threshold, the controller22uses the power supplied from the power storage23to write the write information corresponding to the already received write request into the nonvolatile cache memory222. The configuration can also be considered to be such that the information processing device1includes the above-described processor10, the above-described nonvolatile cache memory222, the above-described controller22, and the power storage23for storing the power supplied from the power supply30, and, if the voltage of the power supplied from the power supply30to the “information processing device1” drops to or below the threshold, the controller22uses the power supplied from the power storage23to write the write information corresponding to the already received write request into the nonvolatile cache memory222.

Also in the present embodiment, if the abnormality in the power supplied from the power supply30to the memory device20is detected, the controller22of the memory device20uses the power supplied from the power storage23to write the write information corresponding to the already received write request into the nonvolatile cache memory222. That is, even if the abnormality occurs in the power supplied from the power supply30to the memory device20, the power supplied from the power storage23can be used to complete writing the write information corresponding to the already fully received write request to the nonvolatile cache memory222, so that the atomicity can be ensured.

Modification of Second Embodiment

The configuration may, for example, be such that the power storage23and the rectifying device31are provided outside the memory device20, as illustrated inFIG. 21. In short, the configuration may be such that the memory device20includes the above-described nonvolatile cache memory222and the above-described controller22, and, if the abnormality in the power supplied from the power supply30to the memory device20is detected, the controller22writes the write information corresponding to the already received write request into the nonvolatile cache memory222, using the power supplied from the power storage23for storing the power supplied from the power supply30. From another point of view, the configuration may be such that the semiconductor device includes the above-described nonvolatile memory21and the above-described controller22, and, if the abnormality in the power supplied from the power supply30to the “semiconductor device” is detected, the controller22writes the write information corresponding to the already received write request into the nonvolatile cache memory222, using the power supplied from the power storage23for storing the power supplied from the power supply30. The configuration may also be such that the information processing device1includes the above-described nonvolatile memory21and the above-described controller22, and, if the abnormality in the power supplied from the power supply30to the “information processing device1” is detected, the controller22writes the write information corresponding to the already received write request into the nonvolatile cache memory222, using the power supplied from the power storage23for storing the power supplied from the power supply30.

In the example ofFIG. 21, the configuration can also be considered to be such that the memory device20includes the above-described nonvolatile memory21and the above-described controller22, and, if the voltage of the power supplied from the power supply30to the memory device20drops to or below the threshold, the above-described controller22writes the write information corresponding to the already received write request into the nonvolatile cache memory222, using the power supplied from the power storage23for storing the power supplied from the power supply30. From another point of view, the configuration can be considered to be such that the semiconductor device includes the above-described nonvolatile memory21and the above-described controller22, and, if the voltage of the power supplied from the power supply30to the “semiconductor device” drops to or below the threshold, the controller22writes the write information corresponding to the already received write request into the nonvolatile cache memory222, using the power supplied from the power storage23for storing the power supplied from the power supply30. The configuration can also be considered to be such that the information processing device1includes the above-described nonvolatile memory21and the above-described controller22, and, if the voltage of the power supplied from the power supply30to the “information processing device1” drops to or below the threshold, the controller22writes the write information corresponding to the already received write request into the nonvolatile cache memory222, using the power supplied from the power storage23for storing the power supplied from the power supply30.

Moreover, the configuration may, for example, be such that the nonvolatile cache memory222is provided external to the controller22, as illustrated inFIG. 22, or such that an integrated assembly of the controller22, the power storage23, and the rectifying device31is provided independent of the nonvolatile memory21, as illustrated inFIG. 23.

Third Embodiment

The following describes a third embodiment. Description will be omitted for parts common to those in each of the embodiments described above, where appropriate.

FIG. 24is a diagram illustrating an example of the detailed hardware configuration of the memory device20of the present embodiment. As illustrated inFIG. 24, the controller22includes the detector210, the receiver211, an analyzer231, a transmitter232, the buffer memory215, a writer233, and the reader219. These components are each constituted by a semiconductor circuit, and may be provided independent of each other, or provided such that any two or more components are integrated. The memory device30of the present embodiment may be connected to the processor10serving as a host device, as in the case of the memory device20ofFIG. 1, or may be connected to another memory device serving as a host device (memory device20ofFIG. 9), as in the case of the second memory device200ofFIG. 9. In the following description of the present embodiment, operations will be described in the case in which the memory device is connected to the processor10serving as a host device. However, the operations are also the same when the memory device is connected to another memory device serving as a host device.

The detector210detects the abnormality in the power supplied from the power supply30to the memory device20. More specifically, the detector210monitors the power supplied from the power supply30to the memory device20, and determines that the abnormality has occurred if the voltage of the power supplied from the power supply30drops to or below the threshold. After detecting the abnormality in the power supplied from the power supply30to the memory device20, the detector210notifies the analyzer231that the abnormality has occurred, through a signal line informing that the abnormality has been detected. The method for detecting the abnormality in the power supplied from the power supply30to the memory device20is not limited to the method in which the detector210measures the voltage of the power supplied from the power supply30to the memory device20, but may be, for example, a method in which the detector210receives a signal indicating the abnormality in the power from an external device, such as the power supply30or the processor10. What is detected by the detector210is the fact that a situation has occurred in which the memory device20cannot continue a normal operation. The notification of the abnormality occurrence from the detector210to the analyzer231is a command for the memory device20to stop receiving a new write request from the processor10, and also a command to write the data based on the already received write request into the nonvolatile memory, using also the power stored in the power storage23if the power supplied from the power supply30alone is not sufficient to write the data.

The receiver211receives the request (the write request or the read request) from the memory controller13of the processor10. The controller22of the present embodiment receives the request (the write request or the read request) over a plurality of clock cycles. Hence, the receiver211can be considered to sequentially receive, from the memory controller13, respective fragments of information (request information) obtained by dividing the entire request into units each transmittable in one clock cycle. The analyzer231receives the request (or the fragments of information constituting the request) received by the receiver211, and performs an analysis and necessary processing on the request. To absorb a difference in operation timing between the receiver211and the analyzer231, a first-in-first-out (FIFO) queue is preferably provided that takes in the request (or the fragments of information constituting the request) received by the receiver211in the order received, and the analyzer231is preferably packaged so as to receive the request (or the fragments of information constituting the request) from the FIFO queue.

The transmitter232sends data read from the nonvolatile memory21based on the read request, as a result of reading, back to the memory controller13of the processor10. A plurality of read requests are also provided that have different data sizes, such as 4, 8, 16, 32, and 64 bytes, so that transmitter232sends data having a length corresponding to each of the data sizes, as the result of reading, back to the processor10serving as the host device. The return of a result of processing of a received request, such as the result of reading corresponding to the read request, is generally called a response.

The general formats of the request and the response of the present embodiment have structures, for example, as illustrated inFIGS. 25 and 26.FIG. 25is a diagram illustrating an example of the structure of the request. In the example ofFIG. 25, the request includes fields of COMMAND, TAG, ADDRESS, DATA, and CRC. The COMMAND field is for information indicating whether the request is a write request or a read request and how many bytes the data length is. The TAG field is for a tag indicating a number for associating the request with the response. The result of reading corresponding to the read request having the tag with a certain number has a tag with the same number as that of the read request. The ADDRESS field is for information indicating a location of data to be read or written in the nonvolatile memory21. The DATA field is for the data to be written in the write request. The length of the DATA field depends on the data size of the write request specified by the COMMAND. The request of the read request does not include the DATA field. The CRC (standing for cyclic redundancy code) field is for information for checking whether the entire request is correctly transmitted.

FIG. 26is a diagram illustrating an example of the structure of the response. In the example ofFIG. 26, the response includes fields of COMMAND, TAG, DATA, and CRC. The COMMAND field is for information indicating how many bytes are included in the read request corresponding to this response serving as a result of reading. The TAG field is for information indicating to which request this response corresponds. The DATA field is for the read-out data. The CRC field is for information for checking whether the entire response is correctly transmitted.

FIG. 27illustrates an example of a 64-byte write request. The COMMAND field has information indicating that the request is a 64-byte write request. The TAG field specifies nothing (represented as “-”, in this example) because this write request requires no response. The ADDRESS to which the data is to be written is “108A0”, and the data to be written is “8F 42 . . . 0B 9D”.

FIG. 28illustrates an example of a 64-byte read request. The COMMAND field has information indicating that the request is a 64-byte read request. The TAG field is set to “7”. The address from which the data is to be read is “21B498”.FIG. 29illustrates an example of a response of a result of reading corresponding to the read request. The COMMAND field has information indicating that the response is a result of reading corresponding to the 64-byte read request. The TAG field is set to “7”, which is the same as the value in the corresponding read request. The DATA field has “48 BD . . . 53 A4” as the read-out data.

The example exhibited here illustrates the case in which the write request involves no response of a result of writing corresponding thereto. However, in the same way as in the case of the read request, the response of the result of writing can easily be made to the write request to inform that the writing has ended (or, the write request has been received).

The analyzer231ofFIG. 24analyzes the request received by the receiver211from the processor10, and determines whether the request is a read request or a write request. If the request is a read request, the analyzer231commands the reader219to perform the reading processing, or, if the request is a write request, the analyzer231stores the data (writing target data) included in the write request in the buffer memory215, and then, commands the writer233to write the data.

FIG. 30is a flowchart illustrating an example of the detailed operation of the analyzer231. The following describes the operation of the analyzer231, based onFIG. 30. First, the analyzer231receives the COMMAND field of the request received by the receiver211from the processor10(Step S50). At this moment, the analyzer231extracts the COMMAND field from the first request if the receiver211has already received (and pushed into the FIFO queue) one or more requests. If the receiver211has received no request from the processor10(if the FIFO queue is empty), the analyzer231waits until the receiver211starts receiving a new request. After the receiver211has started receiving the request and has received at least the COMMAND field, the analyzer231receives the COMMAND field, and proceeds the processing even before the entire request is finished being received. The analyzer231may receive, from the receiver211, other fields (such as the TAG field) together with the COMMAND field, instead of receiving the COMMAND field independently.

Then, the analyzer231checks whether an abnormality signal is transmitted from the detector210(Step S51). If an abnormality signal is transmitted from the detector210(Yes at Step S51), the analyzer231does not process a new subsequent request, so that the analyzer231receives the entire request from the receiver211, skips the entire request without processing it (Step S52), and returns the process to Step S50. If an abnormality signal is not transmitted from the detector210(No at Step S51), the analyzer231receives the TAG field and the ADDRESS field of the request from the receiver211(Step S53). Also at this moment, the receiver211need not have received the entire request, but only needs to have received respective fragments of information corresponding to at least the TAG field and the ADDRESS field. The analyzer231then determines whether the command of the COMMAND field received previously is a write request or a read request (Step S54). If the command is a read request (No at Step S54), the analyzer231determines whether a CRC check is successful (Step S55). If the request is not correctly received (No at Step S55), the analyzer231ignores the request, and returns the process to Step S50. If the CRC check indicates that the request is correctly received (Yes at Step S55), the analyzer231passes the information of the COMMAND, the TAG, and the ADDRESS fields of the request to the reader219to command it to perform the reading processing (Step S56). The CRC check can be made using a method in which the analyzer231receives the CRC field from the receiver211, and the analyzer231performs calculation based on the information in the other fields of the request to check the CRC. The CRC check is preferably made as follows: the receiver211calculates a CRC while receiving the request, compares it with the last received CRC field, and notifies the analyzer231of the result of the check.

If, at Step S54described above, the command is a write request (Yes at Step S54), the analyzer231first allocates a data storage area in the buffer memory215(Step S57). The data storage area is an area in the buffer memory215for temporarily storing the data in the DATA field of the write request. Referring to the command reveals how many bytes of data are to be transmitted, so that the analyzer231allocates an area that can store data of that size. The analyzer231then receives the DATA field of the request from the receiver211(Step S58). The analyzer231then writes the data contained in the DATA field into the data storage area in the buffer memory215allocated at Step S57(Step S59). At this moment, the analyzer231can receive the entire DATA field at a time if the receiver211has received the entire DATA field of the request from the processor10. If, however, the receiver211is currently receiving the request, the analyzer231will receive only a part of the DATA field that has been received by that moment. Therefore, the analyzer231determines whether the entire DATA field of the request has been received from the receiver211(Step S60). If the entire DATA field has not been received (No at Step S60), the analyzer231returns the process to Step S58, and continues receiving the remaining part of the DATA field and writing the data into the data storage area. If the entire DATA field has been received (Yes at Step S60), the analyzer231then makes the CRC check, and determines whether the CRC check is successful (Step S61). If the entire request is confirmed to have been correctly received (Yes at Step S61), the analyzer231passes the information of the COMMAND and the ADDRESS fields of the request and information on the data storage area (addresses of the data storage area allocated in the buffer memory215) to the writer233to command it to perform the writing processing (Step S62). If, as a result of the CRC check, the entire request has not been correctly received (No at Step S61), the analyzer231ignores the request, and returns the process to Step S50.

If a failure, such as the power supply abnormality, occurs, the remaining part of the request may fail to be transmitted while the receiver211has received only up to a part of the request. Therefore, if the power supply abnormality occurs while the analyzer231is operating based on the flowchart illustrated inFIG. 30, the analyzer231stops to receive any of the fields of the request from the receiver211. As a result, if abnormality occurs, for example, in the power supply, a new subsequent request is prevented from being received and processed.

The description will be continued referring back toFIG. 24. Based on the command from the analyzer231, the reader219ofFIG. 24reads the data from the nonvolatile memory21, and sends the data back to the processor10. The flowchart ofFIG. 31illustrates an example of the detailed operation of the reader219. The following describes the operation of the reader219, based onFIG. 31. As illustrated inFIG. 31, the reader219first receives, from the analyzer231, the information of the COMMAND, the TAG, and the ADDRESS fields included in the read request (Step S70). The reader219then reads the data having a length (size) specified in the command, from a location in the nonvolatile memory21specified by the address (Step S71). The reader219then commands the transmitter232to send back the read-out data as the response of the result of reading (Step S72). In this case, based on the information in the COMMAND field received from the analyzer231, the reader219selects a command for the response to be sent back, and passes, to the transmitter232, the command for the response, the information in the TAG field received from the analyzer231, and the data read from the nonvolatile memory21, as information constituting the response. After sending back the response of the result of reading, the reader219returns the process to Step S70.

The description will be continued referring back toFIG. 24again. Based on the command from the analyzer231, the writer233ofFIG. 24writes the data into the nonvolatile memory21. The flowchart ofFIG. 32illustrates an example of the detailed operation of the writer233. The following describes the operation of the writer233, based onFIG. 32. As illustrated inFIG. 32, the writer233first receives, from the analyzer231, the information of the COMMAND and the ADDRESS fields included in the write request and the information on the data storage area (addresses of the data storage area in the buffer memory215) (Step S80). The writer233then reads the data having a write data length (size) specified in the command, from the data storage area in the buffer memory215, and writes the data to a location in the nonvolatile memory21specified by the address (Step S81). The process then returns to Step S80.

FIG. 24illustrates a case in which separate signal lines are used, one being a signal line through which the receiver211receives the request from the processor10, and the other being a signal line through which the transmitter232transmits the response to the processor10. In this way, the signal lines for transmission and reception are often provided independent from each other to transmit and receive data at a high speed. Another method of transmission and reception may be employed in which a signal line is commonly used for transmission and reception, and the direction of signal flow is switched between a transmission mode and a reception mode.

As described above, also in the present embodiment, if the abnormality in the power supplied from the power supply30to the memory device20is detected, the controller22of the memory device20uses the power supplied from the power storage23to write the data based on the already received write request. That is, even if the abnormality occurs in the power supplied from the power supply30to the memory device20, the power supplied from the power storage23can be used to complete the writing based on the already fully received write request. In addition, incomplete data based on the write request that is not fully received can be prevented from being written. As a result, according to the present embodiment, the atomicity can also be ensured with the configuration in which the memory device20is provided with the controller22.

Modification of Third Embodiment

A nonvolatile memory, for example, may be used as the buffer memory215. While a volatile memory is used as the buffer memory215in the configuration of the third embodiment describe above, a nonvolatile memory (called a “nonvolatile buffer memory234”, in this example) may be used, for example, as illustrated inFIG. 33. Using the nonvolatile buffer memory234in this way can prevent the write data temporarily recorded in the nonvolatile buffer memory234from being lost even if the power supply failure occurs. As a result, even when the power supply failure occurs before the writing into the nonvolatile memory21is completed corresponding to the write request received by the memory device20, the data to be written has been recorded in the data storage area in the nonvolatile buffer memory234, and is thereby not lost. The data recorded in the data storage area in the nonvolatile buffer memory234only needs to be written into the nonvolatile memory21when the power is turned on next time. At least the information in the ADDRESS field needs to be recorded, in addition to the information in the DATA field of the write request, in the data storage area of this example. This is because it is necessary to identify the location (address) in the nonvolatile memory21into which the data in the data storage area is to be written after recovery from the failure. If the length (size) of the data to be written can be obtained from management data of the data storage area, the length of the data need not be additionally recorded in the data storage area. Otherwise, the data length or information indicating it (such as the information in the COMMAND field) is additionally recorded in the data storage area.

Fourth Embodiment

The following describes a fourth embodiment. Description will be omitted for parts common to those in each of the embodiments described above, where appropriate.

FIG. 34is a diagram illustrating an example of the detailed hardware configuration of the memory device20of the present embodiment. The configuration is basically the same as that of the third embodiment describe above, but is a two-port configuration including two such transmitters232and two such receivers211. Accordingly, two such analyzers231and two such readers219are included. The memory device20of the present embodiment may be connected to the processor10serving as the host device through a plurality of channels as illustrated inFIG. 7, or may be connected to a plurality of processors (the processors10aand10bofFIG. 8) serving as host devices as illustrated inFIG. 8. As in the case of the memory device20ofFIG. 9, the memory device20can be connected, via one port thereof, to the processor10serving as the host device, and connected, via the other port thereof, to another memory device (second memory device200ofFIG. 9) while serving as another host device. In addition, as in the case of the memory device20ofFIG. 10, the memory device20can be connected, via one port thereof, to the processor10serving as the host device, and connected, via the other port thereof, to another memory device (second memory device200ofFIG. 9) to serve as another host device together with the other memory device.

In the hardware configuration of the memory device20of the present embodiment illustrated inFIG. 34, the operations of the detector210, the buffer memory215, and the writer233are the same as those of the third embodiment illustrated inFIG. 24. The present embodiment differs from the third embodiment by including the two transmitters232, the two receivers211, the two analyzers231, and the two readers219, where these pairs of units include first and second transmitters232aand232b, first and second receivers211aand211b, first and second analyzers231aand231b, and first and second readers219aand219b, respectively. This configuration involves partial differences in the operations of the analyzers231. These components are each constituted by a semiconductor circuit, and may be provided independent of each other, or provided such that any two or more components are integrated.

The general formats of the request and the response of the present embodiment have structures, for example, as illustrated inFIGS. 35 and 36. The structures differ from those of the request and the response of the third embodiment illustrated inFIGS. 25 and 26by each including a field for routing information. The routing information is information for determining to which memory device20or host device (processor10) the request or the response has been transmitted. For example, a unique number can be given to each host device and each of such memory devices20to use the number as the routing information. For example, in the case of the HMC memory device, a cube ID included in the request and a source link ID included in the response correspond to the routing information of the present embodiment.

FIG. 37illustrates an example of the 64-byte write request. This example includes “1”, as the routing information, in addition to the example ofFIG. 27.FIG. 38illustrates an example of the 64-byte read request. This example includes “1”, as the routing information, in addition to the example ofFIG. 28. The routing information “1” represents, for example, a certain memory device.FIG. 39illustrates an example of the response of the result of reading corresponding to this read request. This example includes “0”, as the routing information, in addition to the example ofFIG. 29. The routing information “0” represents, for example, a host device connected to one of the memory devices20.

The example exhibited here illustrates the case in which the write request involves no response of a result of writing corresponding thereto. However, in the same way as in the case of the read request, the response of the result of writing can easily be made to the write request to inform that the writing has ended (or, the write request has been received).

Each of the analyzers231ofFIG. 34analyzes a request received by corresponding one of the receivers211from a host device, and determines whether the request is a read request or a write request. If the request is a read request, the analyzer231commands corresponding one of the readers to perform the reading processing, or, if the request is a write request, the analyzer231stores the data included in the write request in the buffer memory215, and then, commands the writer233to write the data.

FIG. 40is a flowchart illustrating an example of the detailed operation of each of the first and second analyzers231aand231b. The following describes the operation of the first analyzer231a(second analyzer231b), based onFIG. 40. First, the first analyzer231a(second analyzer231b) receives the routing information field of the request or response received by the first receiver211a(second receiver211b) from one of the processors10serving as a host device or one of the other memory devices20(Step S90). At this moment, the first analyzer231a(second analyzer231b) extracts the routing information field from the first request or response if the first receiver211a(second receiver211b) has already received (and pushed into the FIFO queue) one or more requests or responses. If the first receiver211a(second receiver211b) has received no request or response from the host device or the other memory device20(if the FIFO queue is empty), the first analyzer231a(second analyzer231b) waits until the first receiver211a(second receiver211b) starts receiving a new request or response. After the first receiver211a(second receiver211b) has started receiving the request or response and has received at least the routing information field, the first analyzer231a(second analyzer231b) receives the routing information field, and proceeds the processing even before the entire request or response is finished being received. The first analyzer (second analyzer) may receive, from the first receiver211a(second receiver211b), other fields (such as the COMMAND field) together with the routing information field, instead of receiving the routing information field independently.

Then, the first analyzer231a(second analyzer231b) checks whether the routing information in the routing information field received at Step S90specifies the transmission destination to be the local memory device20(Step S91). The routing information for specifying the local memory device20may be set to a fixed value in advance, or may be settable to a value in a register for control. The first analyzer231a(second analyzer231b) can determine whether the transmission destination is the local memory device20by comparing the value with that in the routing information field. If the routing information specifies another memory device20(No at Step S91), the first analyzer231a(second analyzer231b) receives the entire request or response, and commands the second transmitter232b(first transmitter232a) to forward it (Step S92). The process then returns to Step S90.

If the routing information specifies the transmission destination to be the local memory device (Yes at Step S91), the first analyzer231a(second analyzer231b) receives the COMMAND field from the first receiver211a(second receiver211b) (Step S93). Also at this moment, the first receiver211a(second receiver211b) need not have received the entire request, but only needs to have received fragmentary information corresponding to at least the COMMAND field. If the first receiver211a(second receiver211b) has not received the fragmentary information corresponding to the COMMAND field, the first analyzer231a(second analyzer231b) waits until the first receiver211a(second receiver211b) receives the fragmentary information corresponding to the COMMAND field.

Then, the first analyzer231a(second analyzer231b) checks whether the abnormality signal is transmitted from the detector210(Step S94). If the abnormality signal is transmitted from the detector210(Yes at Step S94), the first analyzer231a(second analyzer231b) does not process a new subsequent request, so that the first analyzer231a(second analyzer231b) receives the entire request from the first receiver211a(second receiver211b), skips the entire request without processing it, and returns the process to Step S90. If the abnormality signal is not transmitted from the detector210(No at Step S94), the first analyzer231a(second analyzer231b) receives the TAG field and the ADDRESS field of the request from the first receiver211a(second receiver211b) (Step S96). Also at this moment, the first receiver211a(second receiver211b) need not have received the entire request, but only needs to have received fragmentary information corresponding to at least the TAG field and the ADDRESS field. If the first receiver211a(second receiver211b) has not received the fragmentary information corresponding to the TAG field and the ADDRESS field, the first analyzer231a(second analyzer231b) waits until the first receiver211a(second receiver211b) receives the fragmentary information corresponding to the TAG field and the ADDRESS field. The first analyzer231a(second analyzer231b) then determines whether the command of the COMMAND field received previously is a write request or a read request (Step S97). If the command is a read request (No at Step S97), the first analyzer231a(second analyzer231b) determines whether a CRC check is successful (Step S98). If the request is not correctly received (No at Step S98), the first analyzer231a(second analyzer231b) ignores the request, and returns the process to Step S90. If the CRC check indicates that the request is correctly received (Yes at Step S98), the first analyzer231a(second analyzer231b) passes the information of the COMMAND, the TAG, and the ADDRESS fields of the request to the first reader219a(second reader219b) to command it to perform the reading processing (Step S99). The CRC check can be made using a method in which the first analyzer231a(second analyzer231b) receives the CRC field from the first receiver211a(second receiver211b), and the first analyzer231a(second analyzer231b) performs calculation based on the information in the other fields of the request to check the CRC. The CRC check is preferably made as follows: the first receiver211a(second receiver211b) calculates a CRC while receiving the request, compares it with the last received CRC field, and notifies the first analyzer231a(second analyzer231b) of the result of the check.

If, at Step S97described above, the command is a write request (Yes at Step S97), the first analyzer231a(second analyzer231b) first allocates the data storage area in the buffer memory215(Step S100). The data storage area is an area in the buffer memory215for temporarily storing the data in the DATA field of the write request. Referring to the command reveals how many bytes of data are to be transmitted, so that the first analyzer231a(second analyzer231b) allocates an area that can store data of that size. The first analyzer231a(second analyzer231b) then receives the DATA field of the request from the first receiver211a(second receiver211b) (Step S101). The first analyzer231a(second analyzer231b) then writes the data contained in the DATA field into the data storage area in the buffer memory215allocated at Step S100(Step S102). At this moment, the first analyzer231a(second analyzer231b) can receive the entire DATA field at a time if the first receiver211a(second receiver211b) has received the entire DATA field of the request from the host device or the other memory device20. If, however, the first receiver211a(second receiver211b) is currently receiving the request, the first analyzer231a(second analyzer231b) will receive only a part of the DATA field that has been received by that moment. Therefore, the first analyzer231a(second analyzer231b) determines whether the entire DATA field of the request has been received from the first receiver211a(second receiver211b) (Step S103). If the entire DATA field has not been received (No at Step S103), the first analyzer231a(second analyzer231b) returns the process to Step S101, and continues receiving the remaining part of the DATA field and writing the data into the data storage area. If the entire DATA field has been received (Yes at Step S103), the first analyzer231a(second analyzer231b) then performs the CRC check, and determines whether the CRC check is successful (Step S104). If the entire request is confirmed to have been correctly received (Yes at Step S104), the first analyzer231a(second analyzer231b) passes the information of the COMMAND and the ADDRESS fields of the request and the information on the data storage area (addresses of the data storage area allocated in the buffer memory) to the writer233to command it to perform the writing processing (Step S105). If, as a result of the CRC check, the entire request has not been correctly received (No at Step S104), the first analyzer231a(second analyzer231b) ignores the request, and returns the process to Step S90.

If a failure, such as the power supply abnormality, occurs, the remaining part of the request or response may fail to be transmitted while the first receiver211a(second receiver211b) has received only up to a part of the request. Therefore, if the power supply abnormality occurs while the first analyzer231a(second analyzer231b) is operating based on the flowchart illustrated inFIG. 40, the first analyzer231a(second analyzer231b) stops to receive any of the fields of the request from the first receiver211a(second receiver211b). As a result, if abnormality occurs, for example, in the power supply, a new subsequent request from the host device is prevented from being received and processed.

Based on the command from the first analyzer231aand the second analyzer231b, the first reader219aand the second reader219bofFIG. 34each read the data from the nonvolatile memory21and send the data back to the host device or the other memory device20. The flowchart ofFIG. 41illustrates an example of the detailed operation of the first reader219a(second reader219b). The following describes the operation of the first reader219a(second reader219b), based onFIG. 41. The first reader219a(second reader219b) first receives, from the first analyzer231a(second analyzer231b), the information of the COMMAND, the TAG, and the ADDRESS fields included in the read request (Step S110). The first reader219a(second reader219b) then reads the data having a length (size) specified in the COMMAND, from a location in the nonvolatile memory21specified by the ADDRESS (Step S111). The first reader219a(second reader219b) then commands the first transmitter232a(second transmitter232b) to send back the read-out data as the response of the result of reading (Step S112). In this case, based on the information in the COMMAND field received from the first analyzer231a(second analyzer231b), the first reader219a(second reader219b) selects a command for the response to be sent back, and passes, to the first transmitter233a(second transmitter233b), the command for the response, the information in the TAG field received from the first analyzer231a(second analyzer231b), and the data read from the nonvolatile memory21, as information constituting the response. After sending back the response of the result of reading, the first reader219a(second reader219b) returns the process to Step S110.

Based on the command from the analyzers231, the writer233ofFIG. 34writes the data into the nonvolatile memory21. The flowchart ofFIG. 42illustrates an example of the detailed operation of the writer233. The operation of the writer233will be described based onFIG. 42. The writer233first receives, from the first analyzer231a(second analyzer231b), the information of the COMMAND and the ADDRESS fields included in the write request and the information on the data storage area (addresses of the data storage area in the buffer memory) (Step S120). The writer233then reads the data having a write data length (size) specified in the COMMAND, from the data storage area in the buffer memory, and writes the data to a location in the nonvolatile memory specified by the ADDRESS (Step S121). The process then returns to Step S120.

FIG. 34illustrates a case in which separate signal lines are used, one being a signal line through which the first receiver211a(second receiver211b) receives the request from the host device or the other memory device20, and the other being a signal line through which the first transmitter232a(second transmitter232b) transmits the response to the host device or the other memory device20. In this way, the signal lines for transmission and reception are often provided independent from each other to transmit and receive data at a high speed. Another method of transmission and reception may be employed in which a signal line is commonly used for transmission and reception, and the direction of signal flow is switched between the transmission mode and the reception mode.

While the configuration illustrated inFIG. 34includes two ports (signal lines for transmitting and receiving signals), the number of ports can easily be increased to three. In that case, the controller22stores management information that indicates which of the transmitters232should transmit the request or response if the destination of the request or response received by either of the receivers211turns out to be not the local memory device20as a result of reference to the number serving as the routing information of the request or response. Each of the analyzers231forwards the request or response from appropriate one of the transmitters232, with reference to the information.

In the above-described way, even in the case of using a combination of the memory devices20and the processors10, when one or more of the processors10(host devices) connected to any of the memory devices20transmits (or transmit) a write request (or write requests) to any of the memory devices20before the abnormality in the power occurs, the write request (or write requests) can be guaranteed to be forwarded to the target memory device20(or target memory devices20) without fail, and the data based on the write request (or write requests) can be guaranteed to be written. In addition, incomplete data based on the write request that is not fully received can be prevented from being written, and the request or response can be continued to be forwarded to or from the other memory device.

Modification of Fourth Embodiment

In the fourth embodiment illustrated inFIG. 34, the first reader219aand the second reader219bare separately provided. The readers219may, however, be integrated into one unit, and configured to receive commands for the reading processing from both the first analyzer231aand the second analyzer231b. In this case, the reader219is connected to both the first transmitter232aand the second transmitter232b, and, when either of the first analyzer231aand the second analyzer231bcommands the reader219to perform the reading processing, the analyzer231passes thereto information for determining which of the first transmitter232aand the second transmitter232bshould send back the response of the result of reading.

The embodiments and the modifications thereof described above can be combined in any desired manner.