Power supply unit for supplying power to an on-board electrical network of a vehicle

The invention relates to a power supply unit (3) for supplying power to an on-board electrical network of a vehicle, including: at least two DC-to-DC converters (9A, 9B) which are interleaved and reversible between an opera-ting mode for lowering voltage and an operating mode for raising voltage, the converters (9A, 9B) being intended for being connected to a power storage device (ST2) and being capable of supplying current to the on-board network; and a switch (K) enabling a power source (STI) to supply power to the on-board network when the switch (K) is in a first state, and enabling the power storage device (ST2) to supply power to the on-board network when the switch (K) is in a second state. The unit is characterized in that the converters (9A, 9B) are variable-frequency converters, and in that the power supply unit (3) also includes a synchronization unit (200) configured such as to synchronize the operation of the converters (9A, 9B) operating at variable frequencies and the current generation of the converters.

CROSS-REFERENCE TO RELATED APPLICATIONS

BACKGROUND

The present invention relates in general manner to a power supply unit for supplying an on-board network of a vehicle.

Units for supplying an on-board network of a vehicle with electrical energy existing in the automotive industry include interlaced multi-phase converters working at a fixed frequency (e.g. 150 kHz for each phase). For example, the document FR2970094 describes a unit for supplying electrical energy in an on-board network including a plurality of interlaced converters also working at a fixed frequency.

However, for such a unit, the conducted and radiated emissions are present on a narrow spectrum in radio frequency and filters are thus necessary to meet EMI standards required for the components of a vehicle.

In addition, the converters operating at a fixed frequency do not maintain the stability of the control function for a duty cycle higher than 50% and this limits the output power of the converters and of the unit.

In addition, these interlaced fixed frequency converters, by principle, need to have a minimum duty cycle of minimal control (e.g. 1%) to keep the phase-lock loop stability of the output voltage. This principle involves consuming, at minimum, a load current of a few amperes, which implies poor performance.

In addition, variations in the input voltage of the unit are not taken into account by the regulator of the unit so that the unit operation may become unstable.

BRIEF SUMMARY

An objective of the present invention is to address the above mentioned issues and, in particular, to provide a power supply unit to supply the on-board network of a vehicle with electrical energy that can provide the required output power in a stable fashion and that does not require filters to eliminate the narrow emission of radio frequency in order to meet the required EMI standards.

In that respect, one aspect of this invention involves providing a power supply unit to supply an on-board network of a vehicle with electrical energy, comprising:

At least two current converters DC/DC interlaced and reversible between a step-down/step-up voltage mode, the converters being intended to be subsequently connected to an electrical energy storage device and able to provide a current to the on-board network;

A switch allowing the electric power source to supply the on-board network when the switch is in a first state, and allowing the electric energy storage device to supply the on-board network when the switch is in a second state,

Characterized in that the converters are variable frequency converters and that the supplying unit further comprises a synchronizing device configured to synchronize the operation of the converters operating at variable frequencies and the current generation of the converters.

Such a device synchronizes the operation of a plurality of DC/DC converters working with variable frequency across the operating frequency range. The converters can operate with interlacing regardless of the working frequency of the converters (for example, within a range of 4 kHz to 40 kHz) and maintain the stability of the control function for a duty cycle higher than 50%. Additionally, conducted and radiated emissions are presented on a wide spectrum in radio frequency and filters are no longer required to meet the required EMI standards.

Advantageously, the synchronizing unit comprises:

Means for receiving a switching signal generated by each of the converters;

Means for detecting a type of transition of the received switching signals;

Means for generating a synchronization signal when a transition is detected; and

Means for providing the synchronization signal to one of the converters, the means being configured to provide the synchronization signal to a different converter in sequence each time a transition is detected.

A particularly interesting application is that it further includes synchronization starter means able to provide a synchronization signal to a predetermined converter.

Advantageously, the synchronization starter means include means for receiving a value of a current flowing through the inductance of a converter among converters and means for generating a synchronization starter signal when the value of said current reaches a predetermined value.

Advantageously, the means for receiving include a differentiating circuit for processing the switching signal received from each of the converters.

Advantageously, the means to detect a transition of the switching signals include an OU circuit.

Advantageously, the means to generate a synchronization signal when a transition is detected include a D flip-flop (toggle)

Advantageously, it includes the electric energy storage device.

According to a second aspect, the present invention relates to a system comprising the unit as described above, an electrical energy source linked to the unit, and an on-board network connected to the unit, including a calculator and at least one power consuming device.

According to a third aspect, the present invention relates to a motor vehicle comprising a unit as defined above or a system as defined above.

DESCRIPTION

FIG. 1illustrates a system1according to the present invention which includes a power supply unit3for supplying electrical energy to an on-board network according to the present invention, an electric ST1power source, and the on-board entertainment network (RDB) of a vehicle. The unit3is connected to the source of electrical energy ST1via a first terminal B1and the RDB on-board network via a second terminal B2. The electric power source is, for example, a battery such as an electrochemical battery or a supercapacitor. The RDB comprises a calculator5and at least one power consumer device7.

The unit3comprises an electrical energy storage device ST2and a bypass switch K connected to the source of electrical energy ST1via the first terminal B1and connected to the RDB via the second terminal B2. The calculator5is further configured to lock the bypass switch K of unit3in order to supply the on-board network in electrical energy and charge the electric energy storage device ST2. The calculator5is configured to open the K bypass switch to supply the on-board RDB in electrical energy through the electrical energy storage device ST2.

A diode D1is arranged in parallel with the bypass switch K. The anode of diode D1is connected to the first terminal B1and the cathode of diode D1is connected to the second terminal B2.

The calculator5is configured to generate a BY-PASS signal and provide it to the K bypass switch to close or open the bypass switch K.

Calculator5is further configured to generate a binary signal SENS (DIRECTION) and to provide it to unit3.

Unit3is capable of receiving the DIRECTION signal and configures the unit3in step-down voltage mode or step-up voltage mode according to the value of the DIRECTION signal. When the bypass switch K is closed, the calculator5provides a direction signal having a value (e.g., 0V) showing that a configuration in step-down voltage mode is to be implemented, and when the bypass switch K is opened, the calculator5provides a DIRECTION signal having a value (e.g. 5V) indicating that a configuration in step-up voltage mode is to be implemented.

Unit3further comprises two interlaced converters9A,9B. Each converter9A,9B is reversible between an operating step-down and step-up voltage operating mode, and works with variable frequency. Each converter is a converter operating at variable frequency and each converter is controlled in current and voltage. Both converters9A,9B are connected in parallel. They are running in synchronized variable frequency self-oscillation mode.

Unit3further comprises a controller11, a generator13and a modulator15. The controller11outputs a control voltage VREG OUT serving as reference voltage for the voltages VL1and VL2image of the IL1and IL2currents of the converters9A,9B. Control in current IL1and IL2is realized by the generator13.

Unit3as illustrated inFIG. 1includes the electrical energy storage device ST2. The electrical energy storage device ST2is electrically connected on one side to the grounding device M and on the other side to a third terminal B3. Alternatively, unit3does not include the electrical energy storage device ST2but it is then connected to an external electrical energy storage device through a terminal (not shown) of the unit3.

Converter9A comprises an inductance17A, a first switch19A, and a second switch21A, where switches19A and21A form a half bridge. Converter9B comprises an inductance17B, a first switch19B, and a second switch21B, where switches19B and21B form a half bridge. The first switch19A and the second switch21A are adapted to respectively receive an HS-1and LS-1driving signal from generator13for controlling the switches19A and21A to generate a current through the inductance17A. First switch19B and second switch21B are respectively capable of receiving a control signal HS-2and LS-2from generator13in order to drive switches19B and21B in order to generate a current through the inductance17B.

Each switch19A or19B is electrically connected on one side to the first terminal B1through the switch K and on the other side in series with the inductance17A or17B which is connected to the other side to the third terminal B3and the electric energy storage device ST2. Each switch21A or21B is electrically connected at one end between the switch19A,19B and the inductance17A,17B and on the other side to the grounding device M.

Generator13is adapted to receive the DIRECTION signal and adopt the configuration of a step-down mode converter when the value of the DIRECTION signal is equal to 0V (a 0 logic level). In this case, the K bypass switch is closed and the third terminal B3is a voltage output terminal of the converter and the first terminal B1is a voltage input terminal of the converter.

Generator13is further adapted to adopt the configuration of a step-up mode converter when the value of the DIRECTION signal is equal to 5V (a 1 logic level). In this case, the K bypass switch is open and the third terminal B3is a voltage input terminal of the converter and the second terminal B2is a voltage output terminal of the converter.

Controller11provides a regulated voltage VREG OUT of the current through the inductances17A,17B to generator13. Controller11includes a first controller23for the step-down mode operation and a second controller25for the step-up mode operation. Controller11further comprises a selection device27adapted to select a control voltage VREG ELEVATEUR (STEP-UP) supplied by the first controller23or a control voltage VREG ABAISSEUR (STEP-DOWN) supplied by the second controller25according to the value of the DIRECTION signal. The selection device27is adapted to provide VREG STEP-DOWN voltage control or VREG STEP-UP voltage control (voltage control VREG OUT) to the generator13.

Modulator15is configured to provide an AC voltage signal at a predetermined frequency to controller11.

Each converter9A or9B includes means29A,29B respectively to provide a voltage VL1and VL2(an image of the current IL1and IL2) representative of the current IL1and IL2respectively flowing through the inductance17A and17B to the generator13. Means29A and29B comprise a linear current/voltage converter of R increase to convert a sampling of IL1or IL2current through the inductance17A,17B into a voltage VL1, VL2.

Unit3further comprises filtering capacitors C1, C2and C3and an inductance31connected to the converters9A,9B. Converters9A,9B are filtered from one side by the filtering capacitors C2, C3and the inductance31and on the other side by the filtering capacitor C1.

As illustrated inFIG. 1, converters9A,9B are connected at one end to the electrical power source ST1via the switch K and the first terminal B1, and on the other side to the second electrical energy storage device ST2through the third terminal B3.

Unit3allows to provide power to the on-board network and to recharge the energy storage device ST2simultaneously (converters operating in step-down mode). Unit3also allows making energy recovery on the energy storage device ST2and return it to the on-board network (converters operating in voltage step-up mode).

Generator13of the present invention is illustrated inFIG. 2. Generator13realizes, on the one hand, a current control IL1and IL2by the generation of duty cycles (duty cycle1and duty cycle2) in synchronism, and secondly the generation of the LS-1, LS-2, HS-1HS-2driving signals of switches19A,21A,19B,21B by controllers SD1, SD2.

Generator13is adapted to receive the control voltage VREG OUT from controller11, DIRECTION signal provided by calculator5, and VL1and VL2voltage representative of the current Inand IL2respectively flowing through inductance17A and inductance17B of the means29A,29B. Generator13is adapted to generate the HS-1LS1and HS-2LS2driving signals.

Generator13comprises a synchronizing device200, a first generator213A, and a second generator213B, for example, a comparator for hysteresis, for generating a switching signal for driving the switches of the converters9A,9B to generate a current through the inductances17A,17B.

Generator13further comprises a first adder219A, a second adder219B, a first controller SD1, a second controller SD2, a first current generation stopping device DA1, a second current generation stopping device DA2and an AND gate (or blocking door)220.

The AND gate220is adapted to receive a synchronization starter signal START SYNCRQ of the synchronizing device200and the duty cycle (duty cycle2) generated by the second hysteresis comparator213B. The output signal of the AND gate220is supplied to the second controller SD2.

The hysteresis comparator213A is connected to the switches19A,21A of the converter9A through the controller SD1for transmitting a switching signal to the closing and opening of the switch19A or21A for generating a current in17A inductance. The hysteresis comparator213B is connected to the switches19B,21B of converter9B via controller SD2for transmitting a switching signal to the closing and opening of the switch19B or21B to generate a current in the inductance17B.

The hysteresis comparator213A receives at its inverting input the voltage VL1representative of the current IL2across the inductance17A and at its non-inverting input of the regulating voltage VREG OUT provided by the controller11. The hysteresis comparator213B receives to its inverting input the voltage VL2representative of the current IL2flowing through the inductance17B and at its non-inverting input the regulated voltage VREG OUT supplied by the controller11.

Each adder219A,219B is adapted to add a synchronization signal supplied by the synchronizing device200to the value of the VREG OUT control voltage supplied by the controller15. The adder219A is adapted to provide the result to the non-inverting input of hysteresis comparator213A and adder219B is adapted to provide the result to the non-inverting input of hysteresis comparator213B.

The synchronizing device200according to the present invention is illustrated in detail inFIG. 3A.

The synchronizing device200is adapted to receive the switching signal from the hysteresis comparator213A to a first input terminal2b1and to receive the switching signal from the hysteresis comparator213B to a second input terminal2b2.

The synchronizing device200comprises receiving means for receiving the switching signal generated by each of the converters. The receiving means include a differentiating circuit221A and a shaping circuit223A for receiving and processing the switching signal provided by the hysteresis comparator213A, and a differentiating circuit221B and a shaping circuit223B for receiving and processing the switching signal provided by the hysteresis comparator213B.

The synchronizing device200further comprises means for detecting a type of transition of the received switching signal. The means for detecting a transition type include an OR circuit225.

The differentiating circuit221A is connected on one side to the first terminal2b1and on the other side to the shaping circuit223A. The223A shaping circuit is also connected to an input of the OR circuit. Differentiating circuit221B is connected on one side to the first terminal2b2and on the other side to the shaping circuit223B. Shaping circuit223B is connected to the other input of the OR circuit.

The synchronizing device200further comprises means for generating a synchronization signal when a transition is detected and means for providing the synchronization signal to one of the adders219A,219B.

The means for generating a synchronization signal when a transition is detected include a D227flip-flop (toggle).

The output of the OR circuit is connected to a clock (CLK) input of the D flip-flop. A Q output of the D flip-flop is connected to a resistor R1(for example, 200K)) and the complemented output Q (Qbarre) of the D flip-flop is connected to a resistor R2(for example, 200k0). The other input D of the D flip-flop is connected to the complemented output Q (Qbarre) and resistor R1.

The resistor R1is also connected to a first output terminal2S1and the resistor R2is connected to a second output terminal of the2S2device200.

The D flip-flop is adapted to alternately generate a synchronization signal at the Q output and a synchronization signal at the complemented output of Q (Qbarre) every time the CLK clock receives an input of the OR circuit.

The means for providing the synchronization signal to one of the adders219A,219B include the D flip-flop, the resistor R1connected to the first output terminal S1and the resistor R2connected to the second output terminal S2.

The synchronizing device3receives in input switching output signals of each hysteresis comparator213A,213B. The switching signals are pulse-width modulated signals (PWM) and the intensity of the current generated in the inductances17A,17B is determined by the duty cycle of these signals.

Each transition of the switching output signal of comparator213A is processed by the differentiating circuit221A and223A, the shaping circuit and supplied to the input of the OR circuit. Each transition in the output switching signal of the comparator213bis processed by the differential circuit221B and the shaping circuit223B and supplied to the other input of the OR circuit.

Only positive transitions are taken into account by the OR circuit225and are supplied to the input clock CLK of the D flip-flop. The D flip-flop alternates the Q and Qbarre output states at each positive transition on its clock CLK input received from the OR circuit. A synchronization signal (e.g., a signal of +5V) is produced alternately at the Q and Qbarre outputs. A synchronization signal is thus provided to a different adder219A or219B (through the resistors R1, R2) and in a sequential order (for example,219A,219B,219A,219B . . . ) whenever positive transition is detected by the OR circuit (in the case where the unit3consists of three converters9A,9B and9C, the order is for example,219A,219B,219C,219A,219B,219C . . . ).

The synchronization signal is supplied to the adder219A or the adder219B through the resistor R1or R2. The adder219A or219B adds the value of the regulated voltage VREG OUT to the synchronization signal (for example, a voltage of +290 mV). The result is supplied to the non-inverting input of hysteresis comparator for changing the magnitude of the hysteresis of the comparator.

A voltage of 0V is supplied to another adder and the hysteresis comparator connected to the other adder receives only the value of the regulated voltage VREG OUT at its non-inverting input.

The alternative supply of the synchronizing signal to the adder219A and adder219B in order to change the magnitude of the hysteresis of the comparator when a positive transition is detected by the OR circuit synchronizes the operation of the converters9A and9B operating at variable frequencies to synchronize the current generation inductances17A,17B by the converters9A,9B.

The synchronizing device200further comprises a synchronization starter device231to ensure proper synchronization of the duty cycle1and duty cycle2signals. The synchronizing unit200is adapted to provide a synchronization signal to a predetermined converter.

The synchronization of the starter device231comprises a comparator232, a linear converter current/voltage gain A and a shaping circuit233(for example, a resistor-capacitor circuit (RC circuit)) suitable for preventing a simultaneous starting of the two synchronization converters9A,9B connected on one side to the non-inverting input of comparator232and the other side to an input terminal2b3via the linear current converter/voltage gain of R. Unit231comprises in addition a reference voltage source VREF(for example, a fixed voltage of 2.5V) connected to the inverting input of comparator232. The output of comparator232is connected to a reset input CLR of the D flip-flop

Unit231ensures proper synchronization starts. It is configured to generate a synchronization starter signal START SYNCHRO.2b3input terminal receives the value of the current IL1(or IL2) (an image of the current IL1(or IL2)) passing through the inductance17A (or inductance17B) in the supply of a converter9A or9B or unit3.

The image of the current flowing in the inductance17A (VL1) is filtered by the RC circuit and compared by the comparator232, to the value of the reference voltage VREF. The comparator232generates as output the synchronization starter signal SYNC START. This signal is sent to the reset input CLR of flip-flop227to reset the output of flip-flop227and the AND gate220via an output terminal2S3.

When starting unit3, only the converter generates a9A current. When the current IL1is less than a predetermined value (for example, a low value <3 Amps), the SYNC START signal output of the comparator232remains at 0V and requires resetting the D flip-flop so that a synchronization signal (e.g., a signal of +5V) is produced at the Q output and a 0V signal is produced at the Qbarre output. A synchronization signal is thus supplied to the adder219A through the first output terminal251. The D flip-flop is thus able to always supply a synchronization signal to a predetermined output terminal (2S1) when it receives a START SYNC signal having a value of 0V. Thus the output2S1of the synchronizing device200is initialized to a positive voltage (e.g. +290 mV) and the output2S2is initialized to a zero voltage.

Furthermore, the AND gate220does not provide the duty cycle signal to the second controller SD2when it receives a SYNC START signal having a value of 0V.

When the IL1current exceeds this predetermined value (3 Amps), the synchronization starter signal START SYNCHRO is starting, for example, at a 5V value, so that a reset is not imposed on the D flip-flop and the AND gate220provides the duty cycle signal2to the second controller SD2. The D flip-flop becomes fully operational and the signals supplied to the output terminals2S1and2S2outputs are in alternate (as shown above) and perform the voltage offset by means of adders219A and219B. For example, unit200provides a synchronizing signal at output2S2when a positive transition is detected by the OR circuit (and then at the output2S1,2S2,2S1,2S2. . . ). Proper synchronization of duty cycle1and duty cycle2is thus achieved.

FIG. 3Billustrates the operation of the synchronization starter device231.

FIG. 4illustrates an implementation of the synchronizing device200.

FIG. 5illustrates the value of the current Inflowing through the inductance17A and the value of the current IL1through the inductance17B when converters9A and9B operate in step-down voltage mode.FIG. 5shows that the current generation IL1and IL2is synchronized and that the system1provides a stable VST2output voltage and charges the energy storage device ST2to a requested value of 12V.FIG. 6shows an effective current of3in the energy storage device ST2.

FIG. 7illustrates the effect of a failure of the synchronization of converters DC/DC step-down voltage mode. There is no full stop of all converters at the moment of the breakdown and the effective current in the energy storage device ST2is doubled (6A).FIG. 8illustrates a synchronization failure of 2 minutes. The two step-down converters operate during the outage without interlacing. After the disappearance of the failure, the converters are synchronized after a period of time (0.6 minute inFIG. 8).

FIG. 9illustrates the value of the current IL1flowing through the inductance17A and the value of the current IL2flowing through the inductance17B when converters9A and9B operate in a step-up voltage mode.FIG. 9shows that the generation of current IL1and IL2is synchronized and that the system1provides a stable output voltage VRDB up to the requested value of 13V.

FIG. 10illustrates the hysteresis signal, the output values of Q and Qbarre, the inductance value L1of17A, the inductance value L2of17B and the currents in the inductances L1(17A), L2(17B) when the value of the inductance L1(17A) is equal to the value of the inductance L2(17B).

FIGS. 11 and 12illustrate the hysteresis signals, the output values of Q and Qbarre, the inductance value L1of (17A), the inductance value L2of (17B) and the currents in the inductances L1(17A), L2(17B) during a deflection of the inductance L1(17A) to the inductance L2(17B) (L1L2=150%). These figures show that inductive component deviation +50% (self-switching) does not shut synchronism.

FIGS. 13 and 15illustrate the hysteresis signals, the output values of Q and Qbarre, the inductance value L1(17A), the inductance value L2(17B) and the currents in the inductances L1, L2in a deflection of the inductance L1to the inductance L2(L2=L1−150%). These figures show that inductive component deviation of −50% did not shut synchronism.

The present invention thus provides a synchronizing device200for synchronizing the operation of a plurality of current converters DC/DC variable frequency throughout the converters operating frequency range. Step-down or step-up converters can operate with interlace regardless of the operating frequency converter (for example, in a range of 4 kHz to 40 kHz). In addition, a synchronization operation failure does not result in the forced shutdown of all converters. They then work on their own respective frequency. In addition, a strong drift of the inductive component (+/−50%) (self-switching) does not stops the synchronism. Thus, it is not useful to perform numerical calculations for synchronization correcting the excesses of components of the converters. Furthermore, the present invention reduces the ripple current effect in the filtering capacity.

The SD1and SD2controllers according to the present invention are illustrated in detail inFIG. 15.

The SD1controller is adapted to receive the switching signal (duty cycle1) at the output of comparator213A, the DIRECTION signal provided from the calculator5, and the VL1voltage, representative of the IL1current flowing through the inductance17A of the29A means. SD1controller is adapted to generate HS-1and LS-1control signals.

The SD2controller is adapted to receive the switching signal (duty cycle2) at the output of the213B comparator, the DIRECTION signal provided by calculator5, and the representative VL2voltage of the IL2current flowing through the17B inductance of the29B means. SD2controller is adapted to generate the HS-2and LS-2control signal.

Each controller SD1or SD2functions as a driven diode and allows a high duty cycle (>50%) without instability.

Each SD1or SD2controller includes a334comparator, a335inverter, an AND logic gate having two336inputs, an AND logic gate having three337inputs,338means for providing a reset signal (RESET), signal retarders339,340, a first switch341and second switch342.

The first switch341and the second switch342are adapted to receive the DIRECTION signal and suitable for transferring a switching signal to the signal from synchronization339and the signal340according to the synchronization value of the DIRECTION signal. For example, when the value of the DIRECTION signal is equal to 0V (a logic 0 level and step-down voltage mode), a switching signal emitted from336is transferred to signal retarder339through terminal P2, and fed to switch19of the converter. A switching signal emitted from337is transferred to signal retarder340through terminal P2and fed to switch21. When the value of the DIRECTION signal is equal to 5V (a logic 1 level and step-up voltage mode), a switching signal emitted from336is transferred to signal retarder340through terminal P1, and fed to switch21of the converter. A switching signal emitted from337is transferred to the signal retarder339through terminal P1and fed to switch19.

The means338in order to provide a reset signal to impose a state 0 on LS1and HS1outputs of the signal retarders339,340when the output of the means338is 0 during the initialization phase of the internal power supply (+5V for example). In this case, switches19and21are open.

Comparator334compares the value VL1to a reference voltage REF (for example, 0.5V corresponding to IL1(or IL2)=2 A). If this current is less than 2 Amps, then the switch21opens and does not let a negative IL through when DIRECTION=0, then the switch19opens and does not let the negative IL current when DIRECTION=5V. Signals retarders339,340prohibit the simultaneous conduction of both switches19and21.

Each controller SD1, SD2offers an on-state impedance with a much lower passing state than that of a passive diode and thus improves converter efficiency and limits its thermal heating. Moreover, it allows keeping the stability of the control to a greater than 50% duty cycle.

The first power generation stopping device DA1of generator13, according to another aspect of the present invention is illustrated in detail inFIG. 16. The second power generation stopping device DA2is identical to first current generation stopping device DA1.

The power generation stopping device DA1is able to change the value of the voltage applied to the inverting input of the comparator with hysteresis213A in order to stop the switching of the switch and the generation of the current IL through the inductance.

The power generation stopping device DA1is arranged between the inverting input of comparator213A and the means29supplying a voltage VL representative of the current passing through the inductance.

The current generation stopping device DA1includes an adder417and means419providing a fraction of a general supply voltage (e.g. Vcc=+5V) of the device3. The means419for providing a fraction of the general supply voltage comprise, for example, a divider bridge of two resistors.

The adder417is connected to the inverting input of the comparator and is adapted to add an offset voltage, which is the fraction (for example 0.5V) of the general voltage supply, to the voltage VL1representative of current flowing through the inductance.

The adder417supplies the result to the inverting input of the comparator. The resulting voltage produced at the inverting input of the comparator is equal to (R×IL1)+0.5 V. When the voltage VREG OUT is less than this resulting voltage (R×IL1)+0.5 V, the comparator goes to the low state (0 volts), generating the stop of the converter switch.

FIG. 17ashows the default converters known in the prior art that did not properly stop when the control voltage VREG OUT reached a value close to 0V. When VREG OUT reaches a value close to 0V, current IL1is always produced by the inductance. The current does not cancel itself and the converter still works when the desired operation is a final stop. The control system is unstable.

In contrast,FIG. 17bshows the improvement provided by the present invention which properly stopped when VREG OUT reaches a value close to 0V (current IL1=0) because the current is canceled by the application of the offset voltage by the current generating stopping device DA1. The control system is now stable.

FIG. 18illustrates an exemplary application of the power generation stopping device DA1.

The first controller23for the step-down mode of the voltage regulator11, according to another aspect of the present invention is illustrated in detail inFIG. 19.

The first controller23is adapted to receive a voltage feedback signal from an output voltage VST2converters (feedback), a pro-action signal voltage from an input voltage VRDB(feedforward) and a Vconsigne-ST2reference signal. The first controller23is adapted to determine a control voltage value VREG ABAISSEUR (STEP-DOWN) from the value of the output voltage VS12, of the value of the voltage VRDBof entry and the value of Vconsigne-ST2reference signal. The control voltage VREG ABAISSEUR (STEP-DOWN) is supplied to the selection device27which is adapted to select the control voltage VREG ABAISSEUR (STEP-DOWN) when the value of the DIRECTION signal is equal to 0V (a logic level of 0 and step-down mode of operation). Then, the selection device27provides the control voltage VREG ABAISSEUR (STEP-DOWN) (control voltage VREG OUT) to the generator13to regulate the current flowing through the inductances17A,17B to the value of the control voltage VREG ABAISSEUR (STEP-DOWN).

The first controller23includes an adder515, attenuating means517, a proportional-integral corrector (PI)519, a comparison device521, means for providing a reference voltage VconsigneST2523and a voltage limiter524.

The adder515is adapted to perform a subtraction of the reference voltage Vconsigne-ST2to a fraction of the output voltage VS12(feedback) provided by the attenuating means517. The output error of the adder515is corrected by the Proportional-Integral corrector (PI)519.

The comparison device521is adapted to compare the voltage from the proportional-integral corrector (PI)519and the reference voltage Vconsigne2provided by the means for providing a reference voltage523and it is adapted to copy, at the output, the minimum value of the two voltages and to supply this voltage to the voltage limiter524as VREG0voltage regulation.

The means for providing a reference voltage523are able to provide Vconsigne2voltage which is an internal control voltage to limit the high voltage output of the comparison device521to the value Vconsigne2

The first controller23further includes processing means525to convert the value of the input voltage VRDB(feedforward), a proportional-integral corrector527(first-order temporal filter) and a voltage limiter529.

The processing means525are capable of converting the value of the input voltage VRDBas, for example, a linear or logarithmic law or by the use of a table in order to amplify a reduction in the value of the input voltage VRDB. The processing means525amplify a reduction in the value of the input voltage VRDBso that a value of the input voltage VRDBtransformed at output of processing means525quickly becomes a zero voltage.

For example, when the value of the input voltage VRDBdecreases from a maximal value of 13V to a 7V value, the value of the input voltage VRDBis transformed and at output of processing means525decreases by a maximum value of 4V to an 0V value.

The processing means525are able to provide the value of the input voltage VRDBtransformed to the Proportional-Integral corrector527. The Proportional-Integral corrector527is able to perform temporal filtering (e.g. 10 μs) and to provide the transformed input voltage VRDBto the voltage limiter524.

The voltage limiter524is configured to provide the transformed input voltage VRDB(provided by the proportional-integral corrector527) to the selection device27(VREG ABAISSEUR (STEP-DOWN)=input voltage VRDBtransformed).

The voltage limiter524is further configured to provide the control voltage VREG0(supplied by the comparison device521) to the selection device27(VREG ABAISSEUR (STEP-DOWN)=VREG0) if the value of the VREG0control voltage is lower than the value of the input voltage VRDBtransformed. Thus, the maximum output voltage VHIGHof the voltage limiter524is limited to the value of the transformed input voltage VRDBprovided by the proportional-integral corrector527.

For example, if VREG0is equal to 4V and the input voltage is equal to input voltage VRDBtransformed, then the maximum voltage of the voltage limiter is equal to 0V and VREG ABAISSEUR (STEP-DOWN) is equal to 0V. If VREG0is equal to 4V and the transformed input voltage VRDBis equal to 2V, then the maximum voltage of the voltage limiter is equal to 2V and VREG ABAISSEUR (STEP-DOWN) is equal to 2V. If VREG0is equal to 3V and the transformed input voltage VRDBis equal to 3V, then the maximum voltage of the voltage limiter is equal to 4V and VREG ABAISSEUR (STEP-DOWN) is equal to 3V.

FIG. 20illustrates an exemplary analog implementation of the first controller23according to the present invention. However, a digital electronics implementation is also possible.

FIG. 21shows the current IL1flowing through the inductance17A of the convertor9A during operation of the converter in step-down voltage mode. The input voltage value VRDBconverter is 13V and the converter increases the value of VREG STEP-DOWN to load the storage deviceST2of a 0V value to a value of 12V. At this value of 12V, the regulator lowers VREG ABAISSEUR (STEP-DOWN) to 0V. The converter stops and IL1is equal to 0 A.

FIG. 22illustrates the case where the value of the input voltage of the converter VRDBdecreases. When the value of the input voltage of the converter VRDBgoes from 13V to 7V this fall of the VRDBis amplified by the first controller23to quickly reduce the value of VREG ABAISSEUR (STEP-DOWN) which becomes zero when VRDB=7V.

The unit3of the present invention allows to quickly reduce operating converters9A,9B when the input voltage VRDBchanges significantly thus avoiding unstable control and interference in a safe function of a vehicle due to the input voltage drop VRDBcaused by the unit.

The unit3according to the present invention thus comprises a first controller23in which reference signals Vconsigne-ST2and Vconsigne2are processed, a voltage feedback signal of the output voltage and a voltage proaction signal of the input voltage. The input voltage voltage pro-action signal affects the converters regulation law and those are regulated in voltage and current. The switching frequency of the switches is not fixed because each converter is self-oscillating and controlled by the value of the peak current through the inductance17A or17B and by the fixed voltage hysteresis in the hysteresis comparator213A,213B. The converters are working at variable but low frequencies and below 40 kHz.

The second controller25for the voltage step-up mode, according to another aspect of the present invention is illustrated in detail inFIG. 23.

The second controller25is adapted to receive an output voltage feedback signal VRDBof the converters (feedback), a pro-action signal in a voltage VST2input voltage (feedforward) and a Vconsigne-RDBreference signal. The second regulator25is able to determine a control voltage value VREG ELEVATEUR (STEP-UP) from the value of the output voltage VRDB, the value of the input voltage VST2and of the value of the reference signal Vconsigne-RDB. The control voltage VREG ELEVATEUR (STEP-UP) is supplied to the selection device27which is adapted to select the control voltage VREG ELEVATEUR (STEP-UP) when the value of the DIRECTION signal is equal to 5V (logic level 1 and step-up voltage operating mode). Then, the selection device27provides the control voltage VREG ELEVATEUR (STEP-UP) (control voltage VREG OUT) to the generator13to regulate the current flowing through the inductances17A,17B to the value of the regulated voltage VREG ELEVATEUR (STEP-UP).

The second controller25comprises a first adder615, the first attenuating means617, a first Proportional-Integral corrector (PI)619, means for providing a second reference voltage Vconsigne2621, a second adder627, means for providing a third reference voltage Vconsigne3629, the second means of attenuation631, a second Proportional-Integral corrector (PI)633, a current generation stopping device635, a comparison device637and a control device641.

The first adder615is able to perform a subtraction of the reference voltage Vconsigne-RDBto a fraction of the output voltage VRDB(feedback) provided by the first attenuating means617. The error output from the first adder615is corrected by the first Proportional-Integral corrector (PI)619and the result represented by a value of a voltage regulation VREG0is supplied to the comparison unit637. The first Proportional-Integral corrector (PI) is619, for example, a first order filter with a g2gain.

The first current generation stopping device635is adapted to receive the voltage pro-action signal VST2the input voltage and generating an SA current generation stop signal in the inductances when the value of the voltage pro-action signal reaches a predetermined non-zero value. The current generation stopping device635is adapted to compare the value of the input voltage VST2to a predetermined internally fixed value VL (for example, 4V). The current generation stopping device635is configured to provide a zero voltage 0V (stop signal of SA current generation in the inductances) to the comparison device637when the value of the VST2input voltage is equal or below this predetermined VL value. The current generation stopping device635does not provide a signal to the comparison device637when the value of the input voltage VST2is greater than the predetermined value VL.

The comparison device637is adapted to receive and compare the SA current generation stop signal, the voltage (VREG0) issued of the first Proportional-Integral corrector (PI)619and the reference voltage Vconsigne2provided by the means for providing a second reference voltage621, to copy at the output the minimum value of the three voltages and to supply this voltage to the controller641as VREG1control voltage. The value of the control voltage VREG1is 0V when the SA of the current generation stop signal is received by the comparison unit637.

The means for providing a second reference voltage621are adapted to provide a Vconsigne2voltage which is an internal control voltage to limit the high voltage output of the comparison device637to this Vconsigne2reference value (for example, 4V).

The second controller25comprises means for processing the input voltage value VST2suitable for transforming a decrease in the value of the VST2input voltage into an increasing control voltage Vhigh. The second adder627is able to perform a subtraction of the third reference voltage Vconsigne3to a fraction of the input voltage VST2(feedforward) supplied by the second attenuating means631. The output result of the second adder627is processed by the second Proportional-Integral corrector (PI)633and the processed signal Vhighis supplied to the control unit641.

The means for providing a third reference voltage629are able to provide a Vconsigne3voltage which is an internal control voltage (e.g., 2V).

The second Proportional-Integral corrector (PI)633is, for example, a first order filter with a gain g1. The second Proportional-Integral corrector (PI)633is able to transform the output result of the second adder627according to a decreasing linear law to provide a VHIGHprocessed signal (and a control voltage VREG ELEVATEUR (STEP-UP)) which decreases when the value of the output result of the second adder627(and the value of the input voltage VST2) increases. The second Proportional-Integral corrector (PI)633is thus able to provide the control device641a VHIGHprocessed signal which linearly increases when the value of the input voltage VST2decreases.

FIG. 24illustrates an example of a transfer function of the second Proportional-Integral corrector (PI)633.

The control unit641is configured to provide the VHIGHprocessed signal (provided by the second Proportional-Integral corrector633) to the selecting device27(VREG ELEVATEUR (STEP-UP)=Vhigh).

The controller641is further configured to provide the control voltage VREG1(by the comparison device637) to the selecting unit27(VREG=ELEVATEUR (STEP-UP)=VREG1) if the value of the control voltage VREG1is less the value of the VHIGHprocessed signal.

Thus, the maximum voltage output of the control unit641is limited to the value of the VHIGHprocessed signal provided by the second Proportional-Integral corrector633. When the SA current generation stop signal in the inductances17A,17B (0V) is received by the controller641, via the comparison means637, the controller641provides a control voltage VREG of 0V to the selection device27to stop the generation of the current through inductances17A,17B.

FIG. 25illustrates an analog realization of the second controller25according to the present invention. However, a digital electronics implementation is also possible.

FIG. 26illustrates the current IL1flowing through the inductance17A of the converter9A when the input voltage VST2decreases. The input voltage value of the convertor VST2decreases of a value worth 12.5V to 4V. During the reduction of the value of VST2, converter9A increases the current IL1flowing through the inductance17A (and the value of VREG ELEVATEUR (STEP-UP)) to stabilize the output voltage VRDBto 13V. When the value of the input voltage VST2reaches 4V, the current generation stopping device635generates a current generation stop signal17A in the inductance and the second controller25sets the value of VREG ELEVATEUR (STEP-UP) to 0V. The converter stops and IL1is equal to 0 A.

The converters of the unit3of the present invention change the VRDBoutput voltage and output power in a linear manner when the value of the input voltage VST2decreases and to maintain an output voltage VRDBgreater than or equal to a predetermined value (e.g., 12V). It allows in this way to provide an output voltage VRDBsubstantially constant. The unit3allows moreover stopping the current generation through the inductances17A,17B before the value of the input voltage VST2reaches a value where the operation of the converter becomes unstable and their performance becomes severely degraded.

The unit3according to the present invention comprises a second regulator25in which the reference signals Vconsigne-RDBVconsigne25and Vconsigne3, a voltage feedback signal from the output voltage, and a pro-action signal voltage of the input voltage. The voltage pro-action signal of the input voltage affects the converters regulation law, and converters are then regulated in voltage and current. The switching frequency of the switches is not fixed because the converters are self-oscillating and controlled by the value of the peak current through the inductances17A,17B and the fixed voltage hysteresis in the hysteresis comparators213A,213B. The variable frequency converters are working at variable but low frequency and in any case below 40 kHz.

The selection device27, according to another aspect of the present invention is illustrated in detail inFIG. 27.

The selection device27adapted to receive the control voltage VREG ELEVATEUR (STEP-UP) supplied by the first controller23, the control voltage VREG ABAISSEUR (STEP-DOWN) supplied by the second regulator25, the DIRECTION signal and the alternating FM voltage signal having a predetermined frequency and supplied by the modulator15. The selection device27is further adapted to provide the control voltage VREG ABAISSEUR (STEP-DOWN) or control voltage VREG ELEVATEUR (control voltage VREG OUT) to the generator13.

The selection device27includes a switch701, an adder702and a protective device703.

The switch701is adapted to receive the DIRECTION signal, the control voltage VREG ABAISSEUR (STEP-DOWN) and the control voltage VREG ELEVATEUR (STEP-UP). It is adapted to select the control voltage VREG ELEVATEUR (STEP-UP) when the value of the DIRECTION signal is equal to 5V (logical level 1 level and step-up operation voltage mode) and provide the control voltage VREG ELEVATEUR (STEP-UP) to the adder702. The switch701is also capable of selecting the control voltage VREG ABAISSEUR (STEP-DOWN) when the value of the DIRECTION signal is equal to 0V (logic level 0 and step-down operation mode) and provide the regulation voltage VREG ABAISSEUR (STEP-DOWN) to the adder702.

The adder702, according to another aspect of the present invention is adapted to perform an addition of the FM alternating voltage signal having a predetermined frequency to the control voltage VREG ELEVATEUR (STEP-UP) or control voltage VREG

ABAISSEUR (STEP-DOWN). The result, representing a value of a control voltage modulated by the FM signal, is provided to the protective device703.

The FM signal generated by the modulator15may be an AC signal from a conventional generator such as a square or triangle sine wave generator, or from a table. The amplitude of the signal is weak vis-a-vis that of VREG ELEVATEUR (STEP-UP) or VREG ABAISSEUR (STEP-DOWN), for example, 100 to 300 mV, and the frequency of the FM signal is a low frequency, for example, a 100 Hz to 1 kHz. The adder702allows modulation of the control voltage VREG OUT allowing alternately varying the reference current IL1and IL2in this modulation frequency imposed by the FM signal. The frequency of the duty cycle1and of the duty cycle2is then modulated by the low frequency modulator15. The modulator15(as well as the selection device27and the generator13) makes it possible to generate duty cycles (HS-1LS-1, HS-2, LS-2) at variable frequency and with a large broadband. The conducted and radiated emissions are presented on a broader spectrum in radio frequency so that compliance with requirements is easier to achieve.

As illustrated inFIG. 27, the protection device703includes a voltage limiter719to provide the generator voltage regulation13VREG OUT.

The protection device703according to another aspect of the present invention is able to limit a change in the value generating a current flowing through the converters for a predetermined duration when a change of direction of operation is detected in order to assure the thermal protection of the converters. It is further adapted to detect a feeding process of the converters and to limit a change in the value generating a current flowing through the converters for a predetermined duration when the feeding process is detected

The protection device703further comprises a generator721electrically connected to a capacitor C4through the intermediary of a node N1, and switches S7and S8. The generator721includes a voltage source722A and722B and a power generator. Each switch S7, S8is electrically connected on one side to node N1(between the generator721and capacitor C4) and on the other side to the grounding device M. The voltage limiter719is connected electrically to node N1by assistance of an amplifier723.

The voltage limiter719is also capable of receiving the result (control voltage VREGA) of (addition of AC voltage signal FM voltage VREG LIFT regulation or voltage VREG regulation made by BUCK the adder702.

The switch S7is capable of receiving the RESET signal at a power setting of the unit3and close the switch S7when the signal is received. A725device is capable of receiving the DIRECTION signal when changing the step-down voltage mode to the step-up voltage mode (or vice versa), and detect a rising or falling edge of the DIRECTION signal to close the switch S8(through an SW signal).

In one application of the present invention, the converter1includes means to detect a reverse current flowing in inductances inductance17A,17B and close the reversing switch S8when the current is detected.

The generator721loads in current capacitor C4. The voltage at the terminals of C4is equal to 0 if the switch S7is closed, that is to say, during a time to RESET (alarm of the internal power supplies) or if the switch S8is closed, that is to say, each positive transition and negative DIRECTION signal detected by the unit725.

Next, the voltage across C4rises, for example, linearly (or other function) until the limit of VLimit(e.g. +4V) during a transition time established by the values of the capacity of the C4and the current i supplied by the power generator722B, for example 0.2 minutes.

This voltage is copied by the amplifier723with a gain of 1 and provided as a reference voltage VREFto the voltage limiter719.

The voltage limiter719is configured to provide this voltage reference amount 0V until the limit value VLimitof the generator13(VREG OUT0at the VLimit).

Thus, the maximum voltage of the voltage limiter719can take the following values:

0V during a power-up;

0 to 4V after a mode change during the transition time (e.g. 0.2 mn); and VLimit=4V permanent if a RESET or DIRECTION signal is not received.

The voltage limiter719is further configured to provide the regulation voltage VREGA supplied by the adder702to the generator13(VREG=VREGA OUT) if the value of the VREGA regulation voltage is lower than the value of the reference voltage VREF.

For example, if VREGA is equal to 4V and the reference voltage VREF is equal to 0V, then the maximum voltage of the voltage limiter is equal to 0V and VREG OUT is equal to 0V. If VREGA is equal to 4V and the reference voltage VREF is equal to 2V, then the maximum voltage of the voltage limiter is equal to 2V and VREG OUT is equal to 2V. If VREGA is equal to 3V and the reference voltage VREF is equal to 4V, then the maximum voltage of the voltage limiter is equal to 4V and VREG OUT is equal to 3V.

FIG. 28illustrates an exemplary application of the controller according to the present invention.FIG. 29illustrates an application of the protective device703according to the present invention.

FIG. 30illustrates the evolution of the current through the inductances following a change of converter operation. When the DIRECTION signal changes from 0V to 5V signaling a change in the mode of operation, the VREG OUT voltage regulation is limited by the voltage limiter719and takes the value of 0V. VREG OUT regulating voltage gradually increases from this value of 0V to VLimit(for example, 4V) for a predetermined time. The direction of flow of the current IL is reversed but the value of current IL does not increase abruptly and increases depending on the value of the voltage VREG1regulation.

This prevents an abrupt temperature rise in the electronic components of each converter and the transient power loss of the switches is limited to a predefined value, this value being determined by the generator721and the capacitor C4.

The continuous power dissipation is limited by the value of VLimitand gradient transient junction temperature is limited to a predefined value compatible with and reliability targets and sustainability of semiconductor converters components.

The means29A,29B respectively allow to provide a voltage VL1and a voltage VL2(an image of the current IL1and IL2) representative of the current IL1and IL2respectively through the inductance17A and inductance17B as illustrated inFIG. 31.

The means29A and29B are identical and configured to determine an absolute value of a voltage VL.

The29A converter means comprises a linear current/voltage gain A, an amplifier831of gain1, a tracking peak detector833A, a −1 amplifier gain835A, a peak detector837A and a switch839A.

The29A converter means comprises the linear current/R voltage gain in order to convert a sampling of the current IL1flowing through the inductance17A in a VL1voltage. An image of the current IL1is thus produced. We have at output of the linear converter current/voltage gain R a voltage equal to V=R×IL1.

However, this voltage is positive or negative depending on the direction of operation of the converters (step-down or step-up voltage).

A positive voltage is processed by the +1 gain amplifier831A and the peak detector833A. A negative voltage is processed the −1 amplifier835A and the peak detector837A. The switch839A is capable of receiving the DIRECTION signal and a position A or B of the switch839A is changed for each positive and negative transition of the DIRECTION signal detected by the switch839A.

Taking for example R=0.060 ohm, IL1=50 A and DIRECTION=1 then V at the output of the tracking peak detector833A=0.06×50×1×1=3.0V, at the output of the tracking peak detector837A=(0.06×50)×0×−1=0V and then the output of the switch839A=the output voltage of the tracking peak detector833A=3.0V.

Taking for example R=0.060 ohm, and IL1=−50 A DIRECTION=0, then V at the output of the tracking peak detector833A=0.06×−50×0=0V, in output of the tracking peak detector837A=(0.06×−50)×−1×1=3.0V and then the output of the switch839A=voltage output of the tracking peak detector837A=3.0V.

In a change of direction of operation of the converters (lower voltage to voltage step-up), the IL1and IL2decrease towards 0 A and change value and then increase to wait for their set values.29A and29B means make it possible to obtain at the output of the switch839A the positive value or null value of the VL1voltage of the representative of the current IL1across the inductance17A and at the output of the switch839B the positive or null value of the VL2voltage of the representative current IL2through the inductance17B.

FIG. 32illustrates the operation of the system shown inFIG. 1when starting converters operating in step-down mode. VREG OUT voltage rises from a 0V value to a 4V value 200 μs. The value of the VRDB voltage is 13V and the energy storage device ST2will charge from a0V value to a 12V value. The currents IL1and IL2rise from a 0 A value to a 75 A value dependent on the reference voltage VREG OUT.

FIG. 33illustrates the operation of the system shown inFIG. 1when stopping converters operating in step-down mode. VREG OUT voltage decreases from a 4V value to a value of 0V due to the end of charging the energy storage device ST2and the voltage applied by the stopping devices DA1, DA2. The value of the VRDB voltage is 13V and the energy storage device ST2is charged to a 12.4V value. The IL1and IL2current decrease of a value of 75 A to 0 A value in accordance with the reference voltage VREG OUT.

FIG. 34illustrates the operation of the system shown inFIG. 1when starting converters operating in voltage STEP-UP mode. VREG OUT voltage rises from a 0V value to a 1.5V value. The value of the VRDB voltage is 13V and the energy storage device ST2experiences a discharge from a 12.4V to a 4V value.

FIG. 35illustrates the operation of the system shown inFIG. 1when stopping converters operating in voltage step-up mode. VREG OUT voltage decreases from a 4V value to a value of 0V due to the end of discharge of the energy storage device ST2and the voltage applied by the stopping devices DA1, DA2. The value of the VRDB voltage is 13V and the energy storage device ST2ends its discharge at a 4V value. The IL1and IL2currents decrease in value from −75 A to a 0 A value based on the reference voltage VREG OUT.

FIG. 36illustrates the effect of pro-action signal when powered during operation of the system shown inFIG. 1when such converters operate in voltage step-down mode (charging of the energy storage device ST2). The voltage VRDBdrops from a value of 13V to a value of 7V and then increases back to a 13V value. VREG OUT voltage decreases from a 4V value to a 0V value because of the effect of pro-action voltage signal and the voltage applied by the stopping devices DA1, DA2. The IL1and IL2currents decrease of 75 A towards a 0 A value depending on the reference voltage VREG OUT.

FIG. 37illustrates an exemplary application of the feeding device3according to the present invention.

It will be understood that various modifications and/or improvements obvious to those skilled in the art can be made to various applications of the invention described herein without departing from the scope of the invention defined by the appended claims.

For example, the system may include more than two converters and the synchronizing device can synchronize more than two converters.