Radar apparatus and method

A radar system (300) and a method of operating the radar system is disclosed, the radar system (300) comprising: a first IC (310), arranged to receive a reference clock signal (380) and configurable to generate a common local oscillator signal (400) based on the reference clock signal (380); a second IC (320), arranged to receive the common local oscillator signal (400) from the first IC (310); and a controller (350), adapted to detect a fault in the first IC (310), and configured, upon detection of a fault in the first IC (310), to send at least one signal to the second IC (320) for reconfiguring the second IC (320) from a slave mode to a master mode; wherein, when operating in the slave mode, the second IC (320) is configured to use the common local oscillator signal (400) generated by the first IC (310), and, when operating in the master mode, said second IC (320) is configured to use an internally-generated local oscillator signal. The second IC (310) may be configured to receive the reference clock signal (380), wherein the internally-generated local oscillator signal is based on the reference clock signal (380).

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims the priority under 35 U.S.C. § 119 of European Patent application no. 18150105.7, filed on 2 Jan. 2018, the contents of which are incorporated by reference herein.

FIELD OF THE INVENTION

The present invention relates to a radar system and a method of operating a radar system. In particular, but not exclusively, the invention relates to a radar system configured, on detection of a fault in a first IC of the radar system, to reconfigure a second IC of the radar system from a slave mode to a master mode, thereby maintaining at least limited functionality of the radar system.

BACKGROUND OF THE INVENTION

Autonomous driving functionality demands an extremely high level of safety in an extremely reliable system, and depends on sensors to obtain information about the surrounding environment. Radar sensors can operate in all weather conditions and allow detection of objects in conditions in which vision-based sensors fail. This capability enables radar to become the safety backbone in an autonomous car.

To enable a radar sensor to become the dominant sensor type and to build the safety backbone for autonomous cars, high angular resolution, target separation and object classification is required. Angular resolution and/or SNR may be increased by cascading multiple radar transceivers and/or radar chipsets (a combination of dedicated receiver and/or transmitter chips) to increase the number of physical receiver and/or transmitter channels.

To enable cascading (both coherent and non-coherent), one of the transceivers (and/or radar chipsets) is assigned as master and the other chips as slaves. The master provides the local oscillator (LO) signal and controls the slave chips in terms of timing. A failure in the master chip causes a full failure of all the slave chips because the timing control signals and/or the LO signal to the slaves are no longer provided.

This in turn causes a full malfunction of the radar sensor.

SUMMARY OF THE INVENTION

Aspects of the invention are set out in the accompanying claims. Combinations of features from the dependent claims may be combined with features of the independent claims as appropriate and not merely as explicitly set out in the claims.

According to a first aspect of the invention, there is provided a radar system comprising:

a first IC, arranged to receive a reference clock signal and configurable to generate a common local oscillator signal based on said reference clock signal;

a second IC, arranged to receive the common local oscillator signal from the first IC; and

a controller, adapted to detect a fault in said first IC, and configured, upon detection of a fault in said first IC, to send at least one signal to said second IC for reconfiguring said second IC from a slave mode to a master mode;

wherein, when operating in said slave mode, said second IC is configured to use the common local oscillator signal generated by the first IC, and, when operating in said master mode, said second IC is configured to use an internally-generated local oscillator signal.

The present invention may thereby enable the radar system, for example a cascaded system such as an array in which the first IC normally operates as a master and the second IC normally operates as one of a number of slave ICs, to maintain at least a minimum level of functionality even when a fault is detected in the first IC. This is particularly important for radar sensors critical for safe operation of autonomous vehicles.

The second IC may be configured to receive said reference clock signal, wherein said internally-generated local oscillator signal is based on said reference clock signal.

This may enable the second IC to operate in master mode even when the detected fault interrupts the distribution of a common clock signal to the second IC, for example a common clock signal generated by the first IC.

The reference clock signal may be derived from a crystal oscillator.

The controller may be configured, upon detection of a fault in said first IC, to disable said first IC.

In some embodiments, the radar system comprises a plurality of further ICs, each arranged to receive the common local oscillator signal from the first IC, wherein said second IC is a selected one of said plurality of further ICs.

Each of said further ICs may be arranged to receive said reference clock signal.

The controller may be configured, upon detection of a fault in said first IC, to disable each of said further ICs other than said second IC.

The controller may be adapted to detect a fault in said second IC, and may be configured, upon detection of a fault in said second IC, to send at least one signal to a different selected one of said plurality of further ICs for reconfiguring said different selected one of said plurality of further ICs from said slave mode to said master mode.

The controller may be adapted to detect a fault in said first IC by receiving an error signal from said first IC.

The controller may be adapted to detect a fault in said first IC by detecting an irregularity in radar data obtained using said first IC.

In some embodiments, each of said first IC and said second IC is a respective transceiver. In other embodiments, each of said first IC and said second IC are comprised in a respective one of a transceiver chipset, a receiver chipset or a transmitter chipset.

In some embodiments, said first IC is configurable to generate a common clock signal based on said reference clock signal, wherein said second IC is adapted, when operating in said slave mode, to receive said common clock signal generated by said first IC.

In some embodiments, said first IC is configurable to generate timing control signals based on said reference clock signal, wherein said second IC is adapted, when operating in said slave mode, to receive said timing control signals from said first IC.

The first and second ICs may be identical in structure and/or functionality. The further ICs may be identical to each other in structure and/or functionality.

According to a second aspect of the present invention, there is provided a reconfigurable integrated circuit, selectively configurable for use as said first IC or said second IC in the radar system defined above.

According to a third aspect of the present invention there is provided a method of operating a radar system, the radar system comprising: a first IC arranged to receive a reference clock signal and configurable to generate a common local oscillator signal based on said reference clock signal, a second IC arranged to receive the common local oscillator signal from the first IC, the second IC being selectively configurable for operation in a slave mode, in which said second IC is configured to use the common local oscillator signal output by the first IC, and for operation in a master mode, in which said second IC is configured to use an internally-generated local oscillator signal; the method comprising:

detecting a fault in said first IC, and, on detection of said fault in said first IC, sending at least one signal to said second IC for reconfiguring said second IC from said slave mode to said master mode.

According to a fourth aspect of the present invention there is provided a control system for an autonomous vehicle, the control system comprising a radar system as defined above.

The control system may include a data processing system configured to provide at least one of an electronic brake assist system, a blindspot detection system, a rear cross traffic alert system, and a cruise control system, based on data received from the radar system.

DETAILED DESCRIPTION

FIG. 1shows an example configuration of a cascaded multiple-chip radar sensor system100, for example an array sensor, useful for understanding the present invention. The system100comprises a master transceiver110in the form of a master integrated circuit (IC), a number of slave transceivers120,130,140in the form of slave ICs (of which three are shown inFIG. 1), a controller in the form of a main computing unit (MCU)150, and a crystal oscillator160. Typically, each IC110,120,130,140includes multiple operational transmit (TX) ports and multiple receiver (RX) ports (not shown).

The crystal oscillator160generates a reference clock signal180(XTAL1, XTAL2) for the master IC110. As an example, the reference clock signal180may be a differential signal having a frequency of 60 MHz.

The master IC110generates a common local oscillator (LO) signal200, which is output from an LO output port200aof the master IC110. The common LO signal200is distributed via power splitters/dividers200bto respective LO input ports200cof the master IC110and slave ICs120,130,140, and is used for the transmit (TX) amplifiers and receiver (RX) mixers (not shown inFIG. 1) of the ICs110,120,130,140. In practice, the path lengths from the LO output port200ato each LO input port200care aligned to avoid phase differences. The common LO signal200may have a frequency of, for example, 38 GHz.

The master IC110also generates a common clock signal210(MS_CLKn, MS_CLKp), used as a time base for synchronization of the sampling moments on the ADCs on the master and slave ICs. As an example, the common clock signal may be a differential signal having a frequency of 240 MHz.

Both the common LO signal200and the common clock signal210are derived from the reference clock signal180received by the master IC110from the crystal oscillator160.

The master IC110also transmits timing control signals (not shown) to the slave ICs120,130,140, for example for triggering timing engines within the slave ICs.

The MCU150is connected to the master and slave ICs110,120,130,140by SPI (serial peripheral interface) control lines220and digital lines230, for example using CSI-2 or LVDS formats, for receiving data from the master and slave ICs110,120,130,140. The MCU150may comprise digital signal processing (DSP) functionality and may comprise field programmable gate arrays (FPGA). The MCU150is also connected to the master and slave ICs110,120,130,140by RFS (Radar Frame Start) control lines240for triggering the start of a data acquisition sequence.

In the event of a failure of the master IC110in the radar system100, the whole system100will fail since the common local oscillator signal200and the common clock signal210will not be distributed to the slave ICs120,130,140.

FIG. 2shows an example configuration of a multiple-chip radar sensor system300according to an embodiment of the present invention. The system300comprises a first integrated circuit (IC)310in the form of a first transceiver, and a number of further ICs320,330,340in the form of further transceivers (of which three are shown inFIG. 2), a controller in the form of a main computing unit (MCU)350, and a crystal oscillator360. Typically, each IC310,320,330,140includes multiple operational transmit (TX) ports and multiple receiver (RX) ports (not shown).

The crystal oscillator360generates a reference clock signal380(XTAL1, XTAL2) which is distributed to each of the first and further ICs310,320,330,340. As an example, the reference clock signal380may be a differential signal having a frequency of 60 MHz.

As in the previous example, the MCU350is connected to the transceivers310,320,330,340by SPI (serial peripheral interface) control lines420and digital lines430, for example using CSI-2 or LVDS formats, for receiving data from the transceivers310,320,330,340. The MCU350may comprise digital signal processing (DSP) functionality and may comprise field programmable gate arrays (FPGA). The MCU350is also connected to the transceivers310,320,330,340by RFS (Radar Frame Start) control lines440for triggering the start of a data acquisition sequence.

The radar system300differs from the system100of the previous example in that the MCU350is also connected to each of the transceivers310,320,330,340by a master/slave control line450. This control line450is used for enabling a master mode or a slave mode of operation in each transceiver. The master/slave control line450may connect to a GPIO input of the respective transceiver310,320,330,340.

The first transceiver310is operable as a master IC for the system300. When operating as master IC, the first transceiver310is configured to generate a common local oscillator (LO) signal400and a common clock signal410(MS_CLKn, MS_CLKp), each derived from the reference clock signal380received by the first transceiver310from the crystal oscillator360. The common LO signal400may be output from an LO output port400aof the first transceiver310and distributed via power splitters/dividers400bto respective LO input ports400cof the first transceiver310and further transceivers320,330,340to be used for the transmit (TX) amplifiers and receiver (RX) mixers (not shown inFIG. 2) of the transceivers310,320,330,340. In practice, the path lengths from the LO output port400ato each LO input port400care aligned to avoid phase differences. The common LO signal400may have a frequency of, for example, 38 GHz. The common clock signal410is used as a time base for synchronization of the sampling moments on the ADCs on the transceivers310,320,330,340. As an example, the common clock signal may be a differential signal having a frequency of 240 MHz. When operating as master IC, the first transceiver310also transmits timing control signals (not shown) to the further transceivers320,330,340, for example for triggering timing engines within the further ICs.

The further transceivers320,330,340are operable in a slave mode as slave ICs, so that they may be cascaded with the first transceiver310operating as master IC. When operating in the slave mode, the further transceivers320,330,340are configured to use the common local oscillator signal400received at their respective LO input ports400cfrom the first transceiver310. When operating in slave mode, the further transceivers320,330,340are also configured to use the common clock signal410received from the first transceiver310.

However, the further transceivers320,330,340are also reconfigurable for operation in a master mode. The further transceivers320,330,340are configured, when operating in the master mode, to use an internally-generated LO signal derived from the reference clock signal380received directly from the crystal oscillator360, instead of using the common LO signal400received at its respective LO input port400c. The further transceivers320,330,340are also configured, when operating in the master mode, to use a local clock signal derived internally from the reference clock signal380, instead of using the common clock signal410received from the first transceiver310.

The first transceiver310and further transceivers320,330,340may be ICs identical to each other in structure and functionality, with each transceiver310,320,330,340being selectively configurable to operate in a master mode or a slave mode. The initial configuration of each transceiver310,320,330,340may be preset or may programmed by the MCU350via the master/slave control line450during initialisation of the system300. In other embodiments, the first transceiver310may be permanently configured in master mode, for example by connection of a GPIO input to an address ball. Importantly, the further transceivers320,330,340are reconfigurable by the MCU350via the master/slave control line450to operate in the master mode following initial configuration in the slave mode.

FIG. 2illustrates the radar system300in an initial configuration, in which the first transceiver310is configured to operate as a master IC, and the further transceivers320,330,340are each configured to operate in the slave mode and thereby operate as slave ICs. This configuration may be used for normal operation of the radar system300. The slave ICs320,330,340are configured to use the common LO signal400and common clock signal410received from the master IC310.

The MCU350includes fault detection functionality for detecting a fault in the first transceiver310or further transceivers320,330,340, for example a fault in an internal phase locked loop (PLL) of one of the transceivers. The MCU350may be configured to detect a fault in any one of the transceivers310,320,330,340by receiving an error signal forwarded from the respective transceiver on detection of an internal fault. For example, each transceiver310,320,330,340may be configured to perform a self-test (e.g. to check if the PLL is locked and/or if a transmitted frequency is correct) and to forward an error signal or interrupt signal to the MCU350if the self-test results in a fail. Alternatively, or in addition, the MCU350may be programmed to detect some errors directly, for example the MCU350may be configured to detect an irregularity in radar data obtained using a particular transceiver, such as an irregularity in an FFT of the radar data, and to interpret such an irregularity as an indication of a fault.

Upon detection by the MCU350of a fault or failure of the first transceiver310of the radar system300, during operation in the initial configuration described above with reference toFIG. 2, the MCU350sends a signal or signals to a second transceiver320, via the master/slave control line450, the second transceiver320being one of the further transceivers320,330,340described above, for reconfiguring the second transceiver320from slave mode to master mode. Following reconfiguration to operate in the master mode, the second transceiver320uses a local, internally-generated LO and a local clock signal, each derived from the reference clock signal380received directly from the crystal oscillator360. However, the local LO signal generated by the second transceiver320is not output since there is no provision in the present embodiment for distribution of an LO signal from the second transceiver320to the other transceivers330,340.

Reconfiguration of the second transceiver320may be digitally controlled by the MCU350, wherein the second transceiver320automatically implements automatically the reconfiguration process on receipt of a control signal from the MCU350, via the master/slave control line450indicating reconfiguration from the slave mode to the master mode. Alternatively, the MCU350may send multiple commands to the second transceiver320to implement respective multiple steps of the reconfiguration process. For example, the reconfiguration process may require steps such as switching on an internal PLL of the second transceiver320for generating a local LO signal, switching the LO signal source from the LO input400cof the second transceiver320to the local, internally-generated LO signal, and switching the clock signal source from the common clock signal410to an internally-generated local clock signal. The reconfiguration of the second transceiver320may be performed by changing the states of various internal switching devices of the second transceiver320.

Following detection of a fault in the first transceiver, the MCU350also disables the first transceiver310, the circuitry for distribution of the common LO signal400, and the further transceivers330,340other than the second transceiver320. As a result, the radar system300is reconfigured to the configuration shown inFIG. 3. InFIG. 3, the parts of the system labelled310,330,340,400,400a,400b,400c, LO_IN and LO_OUT are inactive.

In the radar system300reconfigured as shown inFIG. 3, the second transceiver320operates as a standalone transceiver, thereby enabling the radar system300to provide a minimal level of functionality even in the event of a fault in the first transceiver310. This configuration of the system300, shown inFIG. 3, may therefore be referred to as a ‘fail functional’ configuration.

In other embodiments, the remaining further transceivers330,340may also be reconfigured to operate in master mode in the same way as the second transceiver320, to provide an alternative fail functional configuration. However, without any provision for sharing a common LO signal, they each operate in a standalone manner using their respective internally-generated LO signal derived from the reference clock signal380from the crystal oscillator360.

If the MCU350detects a fault in one of the further transceivers320,330340during normal operation of the radar system300in the initial configuration shown inFIG. 2, the MCU350disables the faulty transceiver but does not reconfigure any of the other transceivers310,320,330,340. However, upon detection of a fault in the second transceiver320during operation of the system300in the fail functional configuration shown inFIG. 3, the MCU350sends a signal to a third transceiver330, the third transceiver330being one of the further transceivers330,340other than the second transceiver320, for reconfiguring the third transceiver330from slave mode to master mode, and disables the faulty second transceiver320. In this way, the system300may continue to operate in a further fail functional configuration.

The radar system300shown inFIGS. 2 and 3includes three further transceivers320,330,340, each configured to receive the reference clock signal380from the crystal oscillator360and each configured for control via the master/slave control line450such that the MCU350may reconfigure any of the further transceivers320,330,340between slave and master modes. As a result, the MCU350may select any one of the further transceivers320,330,340as the second transceiver for standalone operation following detection of a fault in the first transceiver310. In other embodiments of the invention, the radar system may include any number, equal to or greater than one, of such further transceivers320,330,340. The number provided may depend on the degree of redundancy required. In some embodiments of the invention, the radar system may also include a number of slave transceivers which are not configured for standalone operation, for example, not configured to receive the reference clock signal380. In other embodiments, all the slave transceivers of the radar system may be configured for reconfiguration between slave and master modes.

The radar system300described above includes ICs in the form of integrated transceivers310,320,330,340. However, in other embodiments of the invention, the ICs of the radar system may be provided by chipsets. The chipsets may be transceiver, transmitter or receiver chipsets.

FIG. 4illustrates a method of operation of the radar system300shown inFIGS. 2 and 3.

In a first step500, the MCU350sends a signal via the master/control line450to initialise the system300for normal operation by configuring the first transceiver310in master mode and the further transceivers320,330,340in slave mode. This step may be optional if the initial configurations of the transceivers are preset.

In a next step510, the radar system300operates normally in the initial configuration. The radar system300operates as a cascasded system with the first transceiver310as master and the further transceivers320,330,340as slaves. The further transceivers320,330,340use the common LO signal400and common clock signal410received from the first transceiver310.

In a next step520, the MCU350monitors for faults in the first transceiver310. If no fault is detected, the method returns to step510. If a fault is detected, for example by receiving an error signal from the first transceiver310, the method proceeds to step530.

At step530, the MCU350disables the first transceiver310. This step may be optional, for example if the first transceiver310automatically deactivates on detection of an internal fault.

In a next step540, the MCU350sends a signal to the second transceiver320instructing reconfiguration of the second transceiver320from slave mode to master mode. On receipt of this signal, the second transceiver320automatically reconfigures such that it uses an internally-generated local LO signal derived from the reference clock signal380received directly from the crystal oscillator360.

In a next step550, the MCU350disables the other further transceivers330,340(not including the second transceiver320). This step is optional.

In a next step560, the radar system300operates in a fail functional configuration. The second transceiver320uses an internally-generated local LO signal derived from the reference clock signal380.

In a next step570, the MCU350monitors for faults in the second transceiver320. If no fault is detected, the method returns to step560. If a fault is detected, for example by receiving an error signal from the second transceiver320, the method proceeds to step580.

At step580, the MCU350disables the second transceiver320. This step may be optional, for example if the second transceiver320automatically deactivates on detection of an internal fault.

In a next step590, the MCU350sends a signal to the third transceiver330instructing reconfiguration of the third transceiver330from slave mode to master mode and/or to enable the third transceiver330. On receipt of this signal, the third transceiver330automatically reconfigures such that it uses an internally-generated local LO signal derived from the reference clock signal380received directly from the crystal oscillator360.

In a next step600, the radar system300operates in a further fail functional configuration. The third transceiver330uses an internally-generated LO signal derived from the reference clock signal380.

Although particular embodiments of the invention have been described above, it will be appreciated than many modifications, including additions and/or substitutions, may be made within the scope of the appended claims.