SUBSTRATE ARRAY FOR PACKAGING INTEGRATED CIRCUITS

A method for packaging integrated circuits includes providing a substrate array having (i) multiple individual substrates, each of which has bottom contact pads and corresponding conductive traces and (ii) plating busses located between adjoining ones of the substrates and electrically connected to the bottom contact pads by way of the traces. The method further includes (i) forming slots in the substrate array by removing portions of the plating busses connected to the traces while leaving corner attachment zones connecting adjacent individual substrates, (ii) attaching and electrically connecting dies to the substrates, (iii) encapsulating the dies, (iv) electrically and functionally testing the assemblies, and then, after the testing, (v) singulating the assemblies, which yields individual IC devices corresponding to the individual substrates.

BACKGROUND

The present invention relates to integrated circuit (IC) packaging and, more particularly, to substrates for packaging integrated circuits.

FIG. 1Ais a bottom view of a conventional substrate array100comprising eighteen individual substrates101and a perimeter zone102.FIG. 1Bis an enlargement of a detail area103ofFIG. 1A, which comprises four of the substrates101.FIG. 1Cis an enlarged side cross-sectional view of a sub-assembly104comprising one of the substrates101ofFIG. 1Balong cut line Z-Z, showing the sub-assembly104after die attaching, wire bonding, and encapsulation steps, but before singulation.

The substrate array100may be used in the packaging of eighteen corresponding ball grid array (BGA) ICs. The substrate array100comprises a substrate material105, which may be, for example, a bismaleimide-triazine (BT) resin. The substrate material105provides structure for holding in place the below-described components of the substrate array100. Each individual substrate101comprises a plurality (sixty-four are shown) of metal bottom contact pads106, each connected by a corresponding conductive metal trace107to a nearby plating bus108. The plating busses108border each of the individual substrates101. In other words, each individual substrate101is separated from the adjoining individual substrates101and/or the perimeter zone102by a plating bus108. Each individual substrate101also comprises top contact pads109and vias and/or traces (not shown) within the substrate material105, which interconnect the top contact pads109and some of the bottom contact pads106.

The top contact pads109, the bottom contact pads106, and the interconnecting vias/traces typically comprise copper. During the manufacturing of the substrate array100, the bottom contact pads106may be electroplated with, for example, nickel and/or gold (not shown). The plating busses108are used to provide electricity to the bottom contact pads106for the electroplating process. After electroplating, dies110are attached, on the top side, to corresponding individual substrates101and are electrically connected to the top contact pads109with corresponding bond wires111. Following the wire bonding step, the top side of the substrate array100—including the dies110and the bond wires111—is encapsulated in an encapsulant113, which typically comprises an epoxy molding compound.

Following encapsulation, singulation is performed, where a saw is used to cut apart the sub-assemblies104of the substrate array100. The saw grinds away the parts of the sub-assemblies104outside of cut lines112, shown inFIG. 1C. The singulation removes the plating busses108, as well as the adjoining ends of the conductive (electroplated) traces107. Note that, prior to singulation, the bottom contacts pads106are shorted together by the plating busses108, but afterwards, they are no longer shorted together by the plating busses108(although select subsets of the bottom contact pads106may be shorted together by other components of the sub-assemblies104, e.g., by the traces and/or vias within the individual substrate101). Consequently, certain electrical and/or functional tests can be performed only after singulation, when the bottom contacts pads106are no longer externally shorted together.

As is appreciated by a person of ordinary skill in the art, bulk testing of the entire substrate array100, also known as strip testing, is more efficient than individual testing of singulated sub-assemblies104. Strip testing of the die-attached, wire-bonded, and encapsulated substrate array100may be done by performing a half-cut step, after encapsulation, which grinds away the plating busses108and the corresponding substrate material105up to the encapsulant113. However, this structurally weakens the substrate array100, which makes handling of the substrate array100more difficult and increases the likelihood of damage to its components.

DETAILED DESCRIPTION

Detailed illustrative embodiments of the present invention are disclosed herein. However, specific structural and functional details disclosed herein are merely representative for purposes of describing example embodiments of the present invention. Embodiments of the present invention may be embodied in many alternative forms and should not be construed as limited to only the embodiments set forth herein. Further, the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of example embodiments of the invention.

As used herein, the singular forms “a,” “an,” and “the,” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It further will be understood that the terms “comprises,” “comprising,” “has,” “having,” “includes,” and/or “including” specify the presence of stated features, steps, or components, but do not preclude the presence or addition of one or more other features, steps, or components. It also should be noted that, in some alternative implementations, the functions/acts noted may occur out of the order noted in the figures.

In one embodiment, the present invention provides a method for packaging integrated circuit (IC) devices, including (i) providing a substrate array, wherein the substrate array comprises a top side, a bottom side, a plurality of individual substrates, wherein each individual substrate comprises a plurality of bottom contact pads and corresponding conductive traces on the bottom side, and plating busses on the bottom side between adjoining substrates, and that are electrically connected to the bottom contact pads by way of the corresponding traces, and (ii) forming slots in the substrate array by removing portions of the plating busses connected to the traces while leaving corner attachment zones connecting adjacent substrates. In one embodiment, after an electroplating step and before an encapsulation step, slots are cut into the substrate array to remove portions of the plating busses sufficient to open shorts between the bottom contact pads. During encapsulation, the slots are filled with encapsulant, which provides structural strength to the substrate array during strip testing.

In another embodiment, the present invention provides a substrate array having a top side and a bottom side, where the substrate array comprises an array of adjacent individual substrates. Each substrate comprises a plurality of bottom contact pads and corresponding conductive traces on the bottom side. The substrates are separated from adjacent substrates by slots formed by removing a corresponding portion of a plating bus on the bottom side, the portion having been previously connected to the conductive traces, The substrates are connected to one or more adjacent substrates by corner attachment zones comprising remains of the plating busses.

Referring now toFIGS. 2A-2C,FIG. 2Ais a bottom view of a substrate array200, which comprises a plurality (eighteen shown) individual substrates201and a perimeter zone202, in accordance with one embodiment of the present invention.FIG. 2Bis an enlargement of a detail area203ofFIG. 2A, which comprises four of the substrates201.FIG. 2Cis an enlarged side cross-sectional view along cut line Z-Z ofFIG. 2B, which shows a cross-section of an individual substrate201as well as part of an adjacent substrate201.

Components of the substrate array200that are substantially similar to corresponding components of the conventional substrate array100ofFIG. 1Aare similarly labeled, but with a different prefix. For example, the substrates201are formed of substrate material205, which is the same as the substrate material105shown inFIGS. 1B and 1C.

The substrate array200has slots221, which are elongated openings bordering the individual substrates201. The slots221may be formed by, for example, punching, laser cutting, or sawing the substrate array200following electroplating of the substrate array200. The slot forming removes the segments of plating busses208that were used to short together bottom contact pads206for the electroplating process, as well as adjacent portions of conductive traces207. Hence, the slot-forming electrically isolates both (i) adjacent individual substrates201from each other and (ii) the bottom contact pads206from each other. This will allow the performance of functional electrical tests following the below-described die attachment and electrical connection, which conventionally would have required device singulation first.

Note that the slot-forming process leaves in place corner-attachment zones220, which connect the corners of adjacent substrates201and which have remnants of the plating busses208. Also note that, during the electroplating process—i.e., prior to the slot forming—top contact pads209along with the bottom contact pads206may also receive electricity from the plating busses208by way of the via/traces (not shown) in the substrate material205. Alternatively, the top contact pads209may be connected by top-layer traces (not shown) to top-layer plating busses (not shown). The slot-forming process would also remove segments of these top-layer traces—similar to the above-described segment removal for the plating busses208—to open the top-layer shorts between the top contact pads209. Following the slot-forming step, corresponding dies are attached and electrically connected to the individual substrates201, as described below.

FIG. 3Ais a bottom view of an assembly325, which comprises the substrate array200ofFIG. 2A, following the attachment and electrical connection to the top sides of the individual substrates201of (eighteen) corresponding semiconductor dies310.FIG. 3Bis an enlargement of a detail area303ofFIG. 3A.FIG. 3Cis an enlarged side cross-sectional view along cut line Z-Z ofFIG. 3B, which shows a cross section of a sub-assembly330as well as part of an adjacent sub-assembly330, where each sub-assembly330comprises a corresponding individual substrate201.

The die310may be attached to the corresponding substrate201using a suitable die attach material (not shown). The die310is then electrically connected to the corresponding substrate201with bond wires311, which connect die contact pads (not shown) on an active surface of the die310to corresponding top contact pads209. Following the die attachment and wire bonding, a removable tape is applied to the bottoms of the slots221, as described below, in order to control the flow of encapsulant in a subsequent encapsulation step.

FIG. 4Ais a bottom view of an assembly441, which comprises the assembly325ofFIG. 3A, following the attachment of a removable tape440.FIG. 4Bis an enlargement of a detail area403ofFIG. 4A.FIG. 4Cis an enlarged side cross-sectional view along cut line Z-Z ofFIG. 4B, which shows a cross section of a sub-assembly330as well as part of an adjacent sub-assembly330.

The tape440may be a pressure-sensitive adhesive tape with an acrylic core, as such are known by those of skill in the art of IC assembly. The tape440is used to prevent leakage onto the bottom of the substrate array200of a below-described encapsulant, used in a subsequent encapsulation step.

FIG. 5Ais a bottom view of an assembly550, which comprises the assembly441ofFIG. 4A, following encapsulation of the assembly441.FIG. 5Bis an enlargement of a detail area503ofFIG. 5A, which comprises four sub-assemblies530.FIG. 5Cis an enlarged side cross-sectional view along cut line Z-Z ofFIG. 5B, which shows a cross section of the sub-assembly530as well as part of an adjacent sub-assembly530, where each sub-assembly530comprises a corresponding sub-assembly330ofFIG. 4C.

In the encapsulation of the assembly441, an encapsulant513, e.g., an epoxy molding compound, is applied to encapsulate the assembly441, including the sub-assemblies330, which include corresponding individual substrates201, attached dies310, and bond wires311. Note that the encapsulant513fills in the spaces of the slots221in the substrate array200. This provides enhanced structural support to the assembly550.

Following the encapsulation step, electrical tests are performed on the sub-assemblies530of the assembly550using devices capable of simultaneously testing all of the sub-assemblies530. This allows for faster and more-efficient testing of the sub-assemblies530. The electrical tests may include, for example, functional tests—testing the operation of the die—and open/short tests—testing proper component interconnections.

Note that, aside from providing structural support and supporting the electrical isolation of both (i) adjacent sub-assemblies530from each other and (ii) the bottom contact pads206from each other, the encapsulant513also protects the die310and bond wires311during the testing setup and the testing itself from, for example, physical damage and chemical contamination. Consequently, functional tests of the dies310that conventionally would have required the singulation of the sub-assemblies530may be performed concurrently. After the tape440is removed and the strip tests are performed, singulation is performed, where the assembly550is cut along cut lines (not shown) corresponding to the original plating busses208to form the below-described individual IC devices.

FIG. 6Ais a bottom view of a singulated IC device660corresponding to a sub-assembly530ofFIG. 5B.FIG. 6Bis an enlarged side cross-sectional view of the IC device660ofFIG. 6Aalong the cut line Z-Z. The sides of the IC device660are mostly made up of the encapsulant513, which helps protect the components of the IC device660and, furthermore, covers up the sides of the electroplating traces207, which in conventional BGA packages may be left exposed. Following the singulation step, conductive balls (not shown) may be attached to the bottom contact pads206using, for example, a soldering technique. Note that, alternatively, the conductive balls may be attached prior to singulation.

An embodiment of the invention has been described where the tape440is applied after wire bonding. The invention is not, however, so limited. In some alternative embodiments, the tape440is applied after the slot-forming and before the die attachment. In some alternative embodiments, the tape440is applied after the die attachment and before the wire bonding.

An embodiment of the invention has been described where the tape440covers the entirety of the substrate array200. The invention is not, however, so limited. In some alternative embodiments, narrower tape bands are used that cover up at least the slots221and adjoining areas, so as to prevent leakage of the encapsulant onto and consequent contamination of the bottom contact pads206, but that do not cover the entirety of the substrate array200.

An embodiment of the invention has been described where the dies310are die-attached and wire-bonded to the individual substrates201to form wire-bonded BGA packages. The invention is not, however, so limited. In some alternative embodiments, dies are flip-chip attached and electrically connected to the corresponding individual substrates using conductive balls to generate flip-chip BGA packages. As would be appreciated by a person of skill in the art, the packaging of a flip-chip BGA package may include some variations, such as for example, (i) using different patterns for the top contact pads209and the vias/traces within the individual substrate201and (ii) using an underfill between the die and the individual substrate201.

An embodiment of the invention has been described where the tape440is removed before the performance of the strip tests. The invention is not, however, so limited. In some alternative embodiments that use narrow tape which does not cover the bottom contact pads206, the tape440does not need to be removed for electrical testing. In some other alternative embodiments, the strip-testing equipment may pierce through the tape440to contact the bottom contacts pads206with the tape440in place.

An embodiment of the invention has been described where each individual substrate201adjoins both other individual substrates201and the perimeter zone202. The invention, however, is not so limited. In some alternative embodiments, some individual substrates adjoin only other individual substrates and do not adjoin the perimeter zone. In some alternative embodiments, some individual substrates adjoin only the perimeter zone and do not adjoin other individual substrates.

Reference herein to “one embodiment” or “an embodiment” means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the invention. The appearances of the phrase “in one embodiment” in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments necessarily mutually exclusive of other embodiments. The same applies to the term “implementation.” As used in this application, unless otherwise explicitly indicated, the term “connected” or “electrically connected” is intended to cover both direct and indirect connections between elements.

Although the steps in the following method claims are recited in a particular sequence with corresponding labeling, unless the claim recitations otherwise imply a particular sequence for implementing some or all of those steps, those steps are not necessarily intended to be limited to being implemented in that particular sequence.