Semiconductor device and semiconductor logic circuit device

A semiconductor device includes two Dt-MOS transistors each having insulation regions respectively under the source and drain regions, the two Dt-MOS transistors sharing a diffusion region as a source region of one Dt-MOS transistor and a drain region of the other Dt-MOS transistor, wherein the insulation regions have respective bottom edges located lower than bottom edges of respective body regions of the Dt-MOS transistors, and wherein the bottom edges of the respective body regions are located deeper than respective bottom edges of the source and drain regions of the Dt-MOS transistors.

FIELD

The embodiments described herein relate to a semiconductor device that uses a dynamic threshold MOS transistor (referred to hereinafter as Dt-MOS transistor).

BACKGROUND

A Dt-MOS transistor is a MOS transistor having a gate electrode connected to a semiconductor layer or well region in which a channel region is formed. Thus, an input signal is applied simultaneously to the gate electrode and the semiconductor layer or the well layer in which the channel region is formed. A Dt-MOS transistor is characterized by low threshold voltage and is yet capable of realizing low OFF-current and large ON-current. Thus, a Dt-MOS transistor is thought suitable for low power consumption operation under low supply voltage. The semiconductor layer or the well region in which the channel region is formed is called “body”.

PRIOR ART REFERENCES

Patent References

SUMMARY

In an aspect, there is provided a semiconductor device including two Dt-MOS transistors each having insulation regions respectively under the source and drain regions, the two Dt-MOS transistors sharing a diffusion region as a source region of one Dt-MOS transistor and a drain region of the other Dt-MOS transistor, wherein the insulation regions have respective bottom edges located lower than bottom edges of respective body regions of the Dt-MOS transistors, and wherein the bottom edges of the respective body regions are located deeper than respective bottom edges of the source and drain regions of the Dt-MOS transistors.

DESCRIPTION OF EMBODIMENT

First Embodiment

FIG. 1is a diagram explaining the principle of a general Dt-MOS transistor10whileFIG. 2is a graph representing the operational characteristic of the Dt-MOS transistor10ofFIG. 1.

Referring toFIG. 1, the exemplary Dt-MOS transistor10is an n-channel MOS transistor and is formed on a silicon substrate11in which a p-type well11P is formed. The p-type well11P includes a source region11S and a drain region11D doped to n-type. Further, on the silicon substrate11, there is formed a gate electrode13of an n-type polysilicon over a channel region11C between the source region11S and the drain region11D via a gate insulation film12.

In the Dt-MOS transistor10ofFIG. 1, the gate electrode13is further connected to the p-type well11P, and hence to the body, electrically, and the signal voltage applied to the gate electrode13is applied also to the body11P. As a result, the signal voltage functions to decrease the threshold voltage of the Dt-MOS transistor10, and the operational characteristic of the Dt-MOS transistor10approaches the operational characteristic of a MOS transistor of low threshold voltage with increase of the signal voltage. Thus, the Dt-MOS transistor10switches ON with a low signal voltage.

On the other hand, in the case the signal voltage is low such as 0V or near 0V, the potential of the body11P becomes 0V or near 0V, and the operational characteristic of the Dt-MOS transistor10approaches the operational characteristic of the MOS transistor having a high threshold voltage. Thus, the threshold voltage of the Dt-MOS transistor10is not different from that of an ordinary n-channel MOS transistor having a high threshold voltage, and as a result, the Dt-MOS transistor10shows a switch OFF operation characterized by low OFF current or leakage current as represented inFIG. 2.

With such a Dt-MOS transistor, it should be noted that a junction part11J between the source region11S and the body11P indicated by a circle inFIG. 1is subjected to forward biasing, and because of this, it is not possible to apply a large supply voltage between the source region11S and the drain region11D. In the case a silicon substrate is used for the substrate11, there is imposed a constraint that the supply voltage has to be set to 0.7V or lower in correspondence to a built-in potential of a silicon p/n junction.

Further, it should be noted that the foregoing explanation holds also in the case of a p-channel MOS transistor in which the p-type and the n-type are reversed.

When such a Dt-MOS transistor is formed on an ordinary silicon substrate sliced out from a monocrystalline silicon ingot (referred to hereinafter as “silicon bulk substrate”), there arises a problem of increase of source or drain leakage current. Further, there arises a problem of increase of junction capacitance between the source region or drain region and the body. Such increase of junction capacitance affects the time constant and invites the problem of decrease of operational speed of the Dt-MOS transistor. Thus, conventional Dt-MOS transistors have been formed generally on an SOI substrate (Non-Patent Reference 1). The characteristic ofFIG. 2is of a Dt-MOS transistor described in Non-Patent Reference 2, which in turn is formed on an SOI substrate.

However, contrary to a simple, stand-alone Dt-MOS transistor, many semiconductor devices are required to be constructed in the form of integrated circuit, in which not only the Dt-MOS transistors that perform the dynamic threshold operation but also various other transistors are integrated on the same substrate as in the case of SoC (system-on-chip), in which a whole system is mounted on a single substrate. Such transistors may include those which should not perform the dynamic threshold operation as in the case of the input/output transistors or the transistors for analog applications.

In such a case, it would become necessary to fix the body potential with these transistors, by individually providing contacts for grounding the body, or the like. However, such a construction invites the problem of decrease of integration density and complexity of fabrication process, in addition to the increase of cost with the use of expensive SOI substrate. Further, there arises a problem that the potential of the body cannot follow the change of the input signal in case there is supplied a high-frequency signal as the input signal.

Further, in the case a Dt-MOS transistor is formed on an SOI substrate, the thickness of the silicon film11P constituting the body becomes too thin and there is caused a problem of increase of the resistance of the body, which in turn leads to the decrease of the operational speed of the transistor caused by the time constant effect.

Conventionally, there have been made attempts to form a Dt-MOS transistor on a silicon bulk substrate. For example, Non-Patent Reference 2 proposes a structure that forms the source region and the drain region on the device isolation structure in the form of so-called elevated source/drain structure for decreasing the junction capacitance between the source or drain region and the body while avoiding the increase of device area at the same time.

However, with this conventional structure, although it is possible to solve the problem of increase of source leakage current or increase of junction capacitance, there is caused the problem of narrowing of the current path between the body and the source region or the drain region, which in turn leads to the problem of increase of the source resistance. Further, because the gate electrode is formed adjacent to the source region or drain region via an insulation film with such a structure, there arises a problem of increase of parasitic capacitance between the gate electrode and the source region or the drain region. Further, there is a problem that the fabrication process becomes complex.

Hereinafter, a semiconductor logic circuit device20according to a first embodiment that uses a Dt-MOS transistor will be explained.

FIG. 3is an equivalent circuit diagram of the semiconductor logic circuit device20of the first embodiment andFIG. 4is a plan view diagram representing the layout thereof. Further,FIGS. 5-9are cross-sectional diagrams respectively representing cross-sections taken along a line A-A′, B-B′, C-C′, D-D′ and E-E′ ofFIG. 4.

As can be seen from the equivalent circuit diagram ofFIG. 3, the semiconductor logic circuit device20is a dual input NAND device and is formed of two p-channel MOS transistors PMOS1and PMOS2connected parallel with each other and two n-channel MOS transistors NMOS1and NMOS2connected in series thereto. In the present embodiment, these p-channel MOS transistors PMOS1and PMOS2and n-channel MOPS transistors NMOS1and NMOS2are formed on a silicon bulk substrate21doped to p−-type (reference should be made toFIGS. 5-9).

The p-channel MOS transistors PMOS1and PMOS2thus connected parallel have respective sources connected commonly to a power supply Vcc. Further, the p-channel MOS transistors PMOS1and PMOS2connected parallel have respective drains connected commonly to a drain D of the n-channel MOS transistor NMOS1. Further, the n-channel MOS transistor NMOS1has a source connected to a drain D of the n-channel MOS transistor NMOS2and the n-channel MOS transistor NMOS2has a source S connected to the ground power supply GND.

Further, a first input signal IN1is supplied to the respective gate electrodes of the p-channel MOS transistor PMOS2and the n-channel MOS transistor NMOS1, and a second input signal IN2is supplied to the respective gate electrodes of the p-channel MOS transistor PMOS1and the n-channel MOS transistor NMOS2. Further, a logic output signal is obtained at a node N where the drains D of the p-channel MOS transistors PMOS1and PMOS2are connected to the drain D of the n-channel MOS transistor NMOS1.

Next, referring to the plan view diagram ofFIG. 4, it can be seen that the silicon bulk substrate21is defined with a first device region21A and a second device region21B by a device isolation region21I of the STI structure, wherein the device region21A is formed with the n-channel MOS transistor NMOS1with the gate electrode provided by a polysilicon pattern21G1and the n-channel MOS transistor NMOS2with the gate electrode provided by a polysilicon pattern21G2.

The polysilicon patterns21G1and21G2extend further into the device region21B, in which the p-channel MOS transistors PMOS2and PMOS1are formed with the polysilicon patterns21G1and21G2as the respective gate electrodes.

The polysilicon pattern21G1is connected electrically to the device regions21A and21B respectively at the via-contacts VC1and VC2. Likewise, the polysilicon pattern21G2is connected electrically to the device regions21A and21B respectively at the via-contacts VC3and VC4. With this, the n-channel MOS transistors NMOS1and NMOS2and the p-channel MOS transistors PMOS1and PMOS2all perform the dynamic threshold operation explained previously with reference toFIG. 2.

Further, it should be noted that the p-channel MOS transistor PMOS1shares the drain thereof with the drain of the p-channel MOS transistor PMOS2. Likewise, the n-channel MOS transistor NMOS1shares the source thereof with the drain of the n-channel MOS transistor NMOS2. As a result of such a construction, it becomes possible to decrease the device area of the semiconductor logic circuit device20as compared with the case in which the p-channel MOS transistors PMOS1and PMOS2and the n-channel MOS transistors NMOS1and NMOS2are formed in the respective device regions that are formed with mutual separation by the device isolation structure.

Further, while it is not visible in the plan view ofFIG. 4, there is also formed a via-contact VC5supplied with the input signal A in the polysilicon pattern21G1on the device isolation region21I at the location between the device regions21A and21B (Reference should be made toFIG. 7). Similarly, the polysilicon pattern21G2is formed with a via-contact VC6supplied with the input signal B on the device isolation region21I at the location between the device regions21A and21B.

Further, in order to construct the circuit ofFIG. 3, the device region21B is formed with via-contacts VC7and VC8for supplying the power supply voltage Vcc to the respective sources S of the p-channel MOS transistors PMOS1and PMOS2from respective power supply patterns PW1and PW2, and the common drain region D of the p-channel MOS transistors PMOS1and PMOS2is connected to a via-contact VC10provided to the drain D of the n-channel MOS transistor NMOS1by way of a via-contact VC9and a wiring pattern WP. Further, the source region of the n-channel MOS transistor NMOS2is connected to the ground GND via a via-contact VC11and a ground pattern GD1, and the output of the semiconductor logic circuit20is obtained on the wiring pattern WP.

In the plan view ofFIG. 4, it can be seen that there is formed an insulation pattern SB1in the device region21A so as to isolate the via-contacts VC1and VC3from each other and further from the via-contacts VC10and VC11. The insulation pattern SB1works as a silicide block structure, and thus, the problem of short circuit between the via-contact VC1and any of the via-contacts VC3, VC10and VC11is avoided successfully even in the case there is formed a silicide layer (not illustrated) in the device region21A. Likewise, as a result of the formation of the insulation pattern SB1, the problem of short circuit between the via-contact VC3and any of the via-contacts VC1, VC10and VC11is successfully avoided even in the case there is formed a silicide layer (not illustrated) in the device region21A.

Similarly, in the plan view ofFIG. 4, it can be seen that there is formed another insulation pattern SB2in the device region21B so as to isolate the via-contacts VC2and VC4from each other and further from the via-contacts VC7and VC8. The insulation pattern SB2, too, works as a silicide block structure, and thus, the problem of short circuit between the via-contact VC2and any of the via-contacts VC4, VC7and VC8is avoided successfully even in the case there is formed a silicide layer (not illustrated) in the device region21B. Likewise, as a result of the formation of the insulation pattern SB2, the problem of short circuit between the via-contact VC4and any of the via-contacts VC2, VC7and VC8is successfully avoided even in the case there is formed a silicide layer (not illustrated) in the device region21B.

The insulation patterns SB1and SB2can be formed at the time of formation of the sidewall insulation films to the polysilicon patterns21G1and21G2by adding a mask process.

FIG. 5is a cross-sectional view taken along a line A-A′ in the plan view ofFIG. 4.

Referring toFIG. 5, the device region21A is formed with a deep n-type well21DNW, wherein the surface part of the n-type well21DNW is formed with a shallow p-type well21PW constituting the body21BY1and21BY2of the n-channel MOS transistors NMOS1and NMOS2respectively in correspondence to the part right underneath the gate electrode23G1N formed by the polysilicon pattern21G1and doped to n-type and in correspondence to the part right underneath the gate electrode23G2N formed of the polysilicon pattern21G2and doped to n-type.

Further, there are formed p-type channel dope regions21NVT1and21NVT2respectively in correspondence to the surface part of the p-type bodies21BY1and21BY2, and hence respectively in correspondence to the channel region CH1of the MOS transistor NMOS1right underneath the gate electrode23G1and the channel region CH2of the MOS transistor NMOS2right underneath the gate electrode23G2N, for the purpose of threshold control, wherein the channel dope regions21NVT1and21NVT2are formed as a part of a p-type injection region21NVT. Here, it should be noted that the function of the channel dope regions21NVT1and21NVT2may be provided by the p-type well21PW that constitutes the body21BY1and21BY2.

As represented inFIG. 4, the polysilicon pattern21G1constituting the gate electrode23G1N is connected electrically to the body21BY1at the via-contact VC1, and as a result, the input signal IN1applied to the gate electrode23G1N is applied also to the body21BY1simultaneously. Thus, the n-channel MOS transistor NMOS1performs the dynamic threshold operation. Similarly, the polysilicon pattern21G2constituting the gate electrode23G2N is connected electrically to the body21BY2at the via-contact VC3, and as a result, the input signal IN2applied to the gate electrode23G2N is applied also to the body21BY2simultaneously. Thus, the n-channel MOS transistor NMOS2performs the dynamic threshold operation explained previously with reference toFIG. 2, for example.

The gate electrodes21G1N and21G2N are formed on the silicon bulk substrate21respectively via gate insulation films22Ox1and22Ox2, and in the deep well21DNW, there are formed an n-type diffusion region21DN1constituting the drain of the n-channel MOS transistor NMOS1at a first side of the channel region CH1. Further, there is formed an n-type diffusion region21SN1constituting the source of the n-channel MOS transistor NMOS1at a side opposite to the diffusion region21DN1across the channel region CH1.

Similarly, the deep well21DNW is formed with an n-type diffusion region21DN2constituting the drain of the n-channel MOS transistor NMOS2at a first side of the channel region CH2, and there is further formed an n-type diffusion region21SN2constituting the source of the n-channel MOS transistor NMOS2at the side opposite to the n-type diffusion region21DN2across the channel region CH2. Here, the n-type diffusion region21SN1and the n-type diffusion reaction21DN2are actually formed by the same n-type diffusion region, and because of this, it is possible with the present embodiment to reduce the area occupied by the semiconductor logic circuit20as explained previously.

Further, in the structure ofFIG. 5, it should be noted that there are formed insulation regions21I1,21I2and21I3of a silicon oxide film right underneath the n-type diffusion region21DN1, the n-type diffusion region21SN1, and hence the n-type diffusion region21DN2, and the n-type diffusion region21SN2, respectively.

It should be noted that the insulation region21I1continues to the adjacent device isolation region21I, while the insulation region21I3continues to the adjacent device isolation region21I. Further, the insulation regions21I1,21I2and21I3are formed such that the respective bottom edges are located at a depth deeper than the bottom edge of the shallow p-type well21PW constituting the bodies21BY1and21BY2. As a result, the bodies21BY1and21BY2are eclectically isolated with each other, and there occurs no interference between the input signals IN1and IN2.

Further, it should be noted that the bottom edges of the n-type diffusion regions21DN1,21SN1and hence21DN2, and21SN2are formed such that the respective bottom edges are located at a depth shallower than the bottom edge of the shallow p-type well21PW. As a result, there is no risk that these n-type diffusion regions cause a short circuit with the n-type well21NW underneath.

Further, with the construction ofFIG. 5, it can be seen that there are laminated interlayer insulation films23and24over the silicon bulk substrate21, and the via-contact VC10is formed to penetrate through the interlayer insulation films23and24and makes a contact with the diffusion region21DN1. Similarly, the via-contact VC11makes a contact with the diffusion region21SN2after penetrating through the interlayer insulation films23and24. The via-contact VC10is contacted with the wiring pattern WP formed on the interlayer insulation film, and the via-contact VC11is connected with the wiring pattern GD1, which in turn is formed on the interlayer insulation film24in connection with the ground voltage supply GND.

FIG. 6is a cross-sectional view taken along a line B-B′ in the plan view ofFIG. 4.

Referring toFIG. 6, there is formed a shallow n-type well21NW constituting the respective bodies21BY4and21BY3of the p-channel MOS transistors PMOS2and PMOS2in the surface part of the device region21B respectively right underneath the p-doped gate electrode23G2P constituted by the polysilicon pattern21G1and right underneath the p-doped gate electrode21G1P constituted by the polysilicon pattern21G2.

Further, there are formed n-type channel dope regions21PVT1and21PVT2respectively in correspondence to the surface part of the n-type bodies21BY3and21BY4, and hence respectively in correspondence to the channel region CH3of the MOS transistor PMOS1right underneath the gate electrode23G1P and the channel region CH4of the MOS transistor PMOS2right underneath the gate electrode23G2P, for the purpose of threshold control, wherein the channel dope regions21PVT1and21PVT2are formed as a part of a n-type injection region21PVT. Here, it should be noted that the function of the n-type channel dope regions21PVT1and21PVT2may be provided by the n-type well21NW that constitutes the bodies21BY3and21BY4.

As represented inFIG. 4, the polysilicon pattern21G1constituting the gate electrode23G2P is connected electrically to the body21BY4at the via-contact VC2, and as a result, the input signal IN1applied to the gate electrode23G2P is applied also to the body21BY4simultaneously. Thus, the p-channel MOS transistor PMOS2performs the dynamic threshold operation. Similarly, the polysilicon pattern21G2constituting the gate electrode23G1P is connected electrically to the body21BY3at the via-contact VC4, and as a result, the input signal IN2applied to the gate electrode23G1P is applied also to the body21BY3simultaneously. Thus, the p-channel MOS transistor PMOS1performs the dynamic threshold operation explained previously with reference toFIG. 1, for example.

The gate electrodes21G2P and21G1P are formed on the silicon bulk substrate21respectively via gate insulation films22Ox3and22Ox4, and in p-type silicon bulk substrate21, there is formed a p-type diffusion region21SP2constituting the drain of the p-channel MOS transistor PMOS2at a first side of the channel region CH4. Further, there is formed a p-type diffusion region21DP2constituting the source of the p-channel MOS transistor PMOS2at a side opposite to the diffusion region21SP2across the channel region CH4.

Similarly, the p-type diffusion region21DP1is formed in the p-type silicon bulk substrate21constituting the drain of the p-channel MOS transistor PMOS1at a first side of the channel region CH3, and there is further formed a p-type diffusion region21SP1constituting the source of the p-channel MOS transistor PMOS1at the side opposite to the p-type diffusion region21DP1across the channel region CH3. Here, the p-type diffusion region21DP2and the p-type diffusion region21DP1are actually formed of the same p-type diffusion region, and the via-contact VP9ofFIG. 4is connected to these. Thus, by constituting the p-type diffusion region21DP2and the p-type diffusion region21DP1by the same p-type diffusion region, it becomes possible with the present embodiment to reduce the area occupied by the semiconductor logic circuit as explained before.

The via-contact VP9extends through the interlayer insulation films23and24and is connected to the wiring pattern WP formed on the interlayer insulation film24.

In the structure ofFIG. 6, it should be noted that there are formed insulation regions21I4,21I5and21I6of a silicon oxide film right underneath the p-type diffusion region21SP1, the p-type diffusion region21DP1, and hence the p-type diffusion region21DP2, the n-type diffusion region21SP1, respectively.

The insulation region21I4continues to the adjacent device isolation region21I, and the insulation region21I6also continues to the adjacent device isolation region21I. Further, the insulation regions21I3,21I4and21I5are formed such that the respective bottom edges are located at a depth deeper than the bottom edge of the shallow n-type well21NW constituting the bodies21BY3and21BY4. As a result, the bodies21BY3and21BY4are eclectically isolated with each other, and there occurs no interference between the input signals IN1and IN2.

Further, it should be noted that the bottom edges of the p-type diffusion regions21SP1,21DP1and hence21DP2, and21SP2are formed such that the respective bottom edges are located at a depth shallower than the bottom edge of the shallow well21NW. As a result, there is no risk that these p-type diffusion regions cause a short circuit with the p-type silicon bulk substrate21underneath.

Further, in the construction ofFIG. 6, the via-contact VC1makes a contact with the diffusion region21SP2after passing through the interlayer insulation films23and24. Similarly, the via-contact VC8makes a contact with the diffusion region21SP1after penetrating through the interlayer insulation films23and24. The via-contact VC7is contacted with the power supply pattern PW1formed on the interlayer insulation film24, and the via-contact VC8is contacted with the power supply pattern PW2on the interlayer insulation film24.

FIG. 7shows the cross-section of the semiconductor logic circuit20taken along a line C-C′ ofFIG. 4.

Referring toFIG. 7, it can be seen that the shallow p-type well21PW including therein the channel dope region NVT1is formed right underneath the gate electrode23G1N constituted by a part of the polysilicon pattern21G1, and the shallow p-type well21PW is formed with a p-type region21P+ of high concentration for ohmic connection in correspondence to the part of the polysilicon pattern21G1that constitutes the gate electrode23G1N in the device region21A. Further, the interlayer insulation film23is formed with an opening23A exposing the p-type region21P+ and the end of the gate electrode23G1N, and the gate electrode23G1N is connected to the shallow well21PW by filling the opening21A with a via contact VC1formed of a metal plug.

Similarly, the shallow n-type well21NW including therein the channel dope region PVT2is formed right underneath the gate electrode23G2P constituted by a part of the polysilicon pattern21G1in the device region21B, and the shallow n-type well21NW is formed with an n-type region21N+1 of high concentration for ohmic connection in correspondence to the part of the polysilicon pattern21G1that constitutes the end part of the gate electrode23G2P in the device region21B. Further, in the interlayer insulation film23, there is formed an opening23B exposing the n+-type ohmic region21N+1 and the foregoing end part of the gate electrode23G1P, and the gate electrode23G2P is connected to the shallow well21NW via the n+-type ohmic region21N+1 by filling the opening23B with the via-contact VC2of a metal plug.

As a result, the p-channel MOS transistor PMOS1and the n-channel MOS transistor NMOS2perform the dynamic threshold operation respectively.

The polysilicon pattern21G1is formed with a contact hole23C in the interlayer insulation film23in correspondence to the device isolation region21I between the device region21A and the device region21B, and the signal wiring pattern24A formed on the interlayer insulation film23and supplied with the signal IN1is connected to the polysilicon pattern21G1electrically by filling the contact hole21C by the via-contact VC5of a metal plug. While not illustrated, the polysilicon pattern21G1is formed with a low-resistance silicide layer thereon, and thus, there arises no such a problem as increase of electric resistance at the part of the polysilicon pattern21G1where the gate electrode23G1N doped to the n-type and the gate electrode23G1P doped to the p-type are connected. In the plan view ofFIG. 4, it should be noted that the via-contact CV5, being formed right underneath the wiring pattern WP formed on the interlayer insulation film24, is not illustrated.

FIG. 8shows the cross-section of the semiconductor logic circuit20taken along a line D-D′ ofFIG. 4.

Referring toFIG. 8, it can be seen that the shallow p-type well21PW including therein the channel dope region NVT2is formed right underneath the gate electrode23G2N constituted by a part of the polysilicon pattern21G2, and the shallow p-type well21PW is formed with a p-type region21P+2 of high concentration for ohmic connection in correspondence to the part of the polysilicon pattern21G2that constitutes the gate electrode23G2N in the device region21A. Further, in the interlayer insulation film23, there is formed an opening23A exposing the p type ohmic region21P+2 and the foregoing end part of the gate electrode23G2N, and the gate electrode23G2N is connected to the shallow well21PW via the p-type ohmic region21P2by filling the opening23A with the via-contact VC3of a metal plug.

Similarly, the shallow n-type well21NW including therein the channel dope region PVT2is formed right underneath the gate electrode23G2P constituted by a part of the polysilicon pattern21G1in the device region21B, and the shallow n-type well21NW is formed with an n-type region21N+1 of high concentration for ohmic connection in correspondence to the part of the polysilicon pattern21G1that constitutes the end part of the gate electrode23G2P in the device region21B. Further, in the interlayer insulation film23, there is formed an opening23E exposing the n-type ohmic region21N+2 and the foregoing end part of the gate electrode23G1P, and the gate electrode23G1P is connected to the shallow well21NW via the n-type ohmic region21N+2 by filling the opening23E with the via-contact VC4of a metal plug.

As a result, the p-channel MOS transistor PMOS1and the n-channel MOS transistor NMOS2perform the dynamic threshold operation respectively.

The polysilicon pattern21G2is formed with a contact hole23F in the interlayer insulation film23in correspondence to the device isolation region21I between the device region21A and the device region21B, and the signal wiring pattern24B formed on the interlayer insulation film23and supplied with the signal IN2is connected to the polysilicon pattern21G2electrically by filling the contact hole23F by the via-contact VC6of a metal plug. While not illustrated, the polysilicon pattern21G2is formed with a low-resistance silicide layer thereon, and thus, there arises no such a problem as increase of electric resistance at the part of the polysilicon pattern21G2where the gate electrode23G2N doped to the n-type and the gate electrode23G2P doped to the p-type are connected.

FIG. 9is a cross-sectional view taken along a line E-E′ in the plan view ofFIG. 4.

Referring toFIG. 9, it can be seen that the wiring pattern WP extends on the interlayer insulation film24while bridging over the via-contact VC5formed on the polysilicon pattern21G1and the signal wiring pattern24A and is connected to the p-type diffusion region21DP1via the via-contact VC9and further to the n-type diffusion region21DN1via the via-contact VC10.

Further, in the cross-sectional diagram ofFIG. 9too, it can be seen that the insulation region21I5of a silicon oxide film is formed right underneath the n-type well21NW and the p-type diffusion region21DP, and hence the p-type diffusion region21DP2formed therein and that the insulation region21I1of a silicon oxide film is formed right underneath the p-type well21PW and the n-type diffusion region21DN1formed therein.

With the semiconductor logic circuit device20of such a construction, the gate electrode21G1N of the n-channel MOS transistor NMOS1shown inFIG. 5is electrically connected to the body21BY1formed of the p-type well21PW and extending right underneath the channel region21CH1by the via-contact VC1and the p-type ohmic region21P+1 as shown inFIG. 7, and because of this, the n-channel MOS transistor NMOS1becomes a Dt-MOS transistor that performs a low voltage operation and shows a dynamic threshold operation explained inFIG. 2characterized by low Off current and large On current.

Further, with the semiconductor logic circuit device20of such a construction, the gate electrode23G2N of the n-channel MOS transistor NMOS2shown inFIG. 5is electrically connected to the body21BY2formed of the p-type well21PW and extending right underneath the channel region21CH2by the via-contact VC3and the p-type ohmic region21P+2 as shown inFIG. 8, and because of this, the n-channel MOS transistor NMOS2also becomes a Dt-MOS transistor that performs a low voltage operation and shows a dynamic threshold operation explained inFIG. 2characterized by low Off current and large On current.

Further, with the semiconductor logic circuit device20of such a construction, the gate electrode23G1P of the p-channel MOS transistor PMOS1shown inFIG. 6is electrically connected to the body21BY3formed of the n-type well21NW and extending right underneath the channel region21CH3by the via-contact VC4and the n-type ohmic region21N+2 as shown inFIG. 8, and because of this, the p-channel MOS transistor PMOS1becomes a Dt-MOS transistor that performs a low voltage operation and shows a dynamic threshold operation explained inFIG. 2characterized by low Off current and large On current.

Further, with the semiconductor logic circuit device20of such a construction, the gate electrode23G2P of the p-channel MOS transistor PMOS2shown inFIG. 6is electrically connected to the body21BY4formed of the n-type well21NW and extending right underneath the channel region21CH4by the via-contact VC2and the n-type ohmic region21N+1 as shown inFIG. 7, and because of this, the p-channel MOS transistor PMOS2becomes a Dt-MOS transistor that performs a low voltage operation and shows a dynamic threshold operation explained inFIG. 2characterized by low Off current and large On current.

In the n-channel MOS transistor NMOS1, in which the insulation regions21I2and21I1of a silicon oxide film are formed respectively right underneath the n-type diffusion region21SN1constituting the source region thereof and the n-type diffusion region21DN1constituting the drain region thereof, the junction capacitance associated with these diffusion regions are reduced, and improvement is attained in the operational speed while decreasing the junction leakage current at the same time.

Similarly, in the n-channel MOS transistor NMOS2, in which the insulation regions21I3and21I2of a silicon oxide film are formed respectively right underneath the n-type diffusion region21SN2constituting the source region thereof and the n-type diffusion region21DN2constituting the drain region thereof, the junction capacitance associated with these diffusion regions are reduced, and improvement is attained in the operational speed while decreasing the junction leakage current at the same time.

Thereby, it should be noted that the bottom edge of the p-type well21PW constituting the body21BY1and the body21BY2is formed at a depth not exceeding the bottom edge of the insulation regions21I1-21I3. Because of this, the body21BY1and the body21BY2are isolated electrically, and there occurs no interference between the input signal IN1and the input signal IN2. Further, because the bottom edges of the n-type diffusion regions21DN1,21SN1,21DN2and21SN2are formed at a level shallower than the bottom edge of the p-type well21PW, there occurs no short circuit between these diffusion regions and the underlying deep n-type well21DNW.

In the n-channel MOS transistor PMOS1, in which the insulation regions21I4and21I5of a silicon oxide film are formed respectively right underneath the p-type diffusion region21SP1constituting the source region thereof and the p-type diffusion region21DP1constituting the drain region thereof, the junction capacitance associated with these diffusion regions are reduced, and improvement is attained in the operational speed while decreasing the junction leakage current at the same time.

Similarly, in the p-channel MOS transistor PMOS2, in which the insulation regions21I6and21I5of a silicon oxide film are formed respectively right underneath the p-type diffusion region21SP2constituting the source region thereof and the p-type diffusion region21DP2constituting the drain region thereof, the junction capacitance associated with these diffusion regions are reduced, and improvement is attained in the operational speed while decreasing the junction leakage current at the same time.

Thereby, it should be noted that the bottom edge of the n-type well21NW constituting the body21BY3and the body21BY4is formed at a depth not exceeding the bottom edge of the insulation regions21I4-21I6, and because of this, the body21BY3and the body21BY4are isolated electrically. Thus, there occurs no interference between the input signal IN1and the input signal IN2. Further, because the bottom edges of the p-type diffusion regions21DP1,21SP1,21DP2and21SP2are formed at a level shallower than the bottom edge of the p-type well21NW, there occurs no short circuit between these diffusion regions and the underlying p-type well silicon bulk substrate21.

As explained previously with reference toFIG. 4, the n-channel MOS transistor NMOS1shares the source diffusion region21SN1with the drain region21DN2of the n-channel MOS transistor NMOS2in the device region21A, and because of this, it becomes possible to dispose the MOS transistors NMOS1and NMOS2with a close mutual distance. Thus, it becomes possible to reduce the area of the device region21A.

Similarly, in the device region21B, too, the p-channel MOS transistor PMOS1is constructed to share the drain diffusion region21DP1thereof with the drain region21DP2of the p-channel MOS transistor PMOS2, and because of this, it becomes possible to dispose the MOS transistors PMOS1and PMOS2with a close mutual separation. Thus, it becomes possible to reduce the area of the device region21B.

Further, with the semiconductor logic circuit device20of such a construction, it becomes possible to integrate a Dt-MOS transistor with an ordinary MOS transistor not having a Dt-MOS transistor structure on the same semiconductor bulk substrate, without changing the construction of the ordinary MOS transistor such as forming a via-contact for fixing the body voltage.

Further, according to the present embodiment, it will be noted that there is formed no insulation region such as the insulation region21I1-21I8right underneath the polysilicon pattern21G1as represented in the cross-sectional diagram ofFIG. 7orFIG. 8. Because of this, the depth of the body is not restricted by the insulation region of silicon oxide film in any of the foregoing n-channel MOS transistors NMOS1and NMOS2and the p-channel MOS transistors PMOS1and PMOS2, and it becomes possible to reduce the electric resistance of the bodies21BY1-21BY2to which the input signals are applied. Thus, it becomes possible to improve the operational speed of these transistors.

Next, fabrication process of the semiconductor logic circuit20will be explained.

InFIG. 10A, the left side part of the broken line represents the cross-sectional diagram along the line A-A′ ofFIG. 4, while the right side part represents the cross-sectional diagram taken along the line B-B′ ofFIG. 4. The same applies to the subsequent drawings.

Referring toFIG. 10A, there is provided a p-type monocrystalline silicon bulk substrate21of a (100) surface orientation such that the device regions21A and21B are defined by the device isolation region21I of STI type having a bottom edge at the depth of 200 nm-400 nm, for example, and a resist pattern R1is formed thereon so as to cover the device region21B. Further, while using the resist pattern R1as a mask, phosphorus (P) is introduced into the silicon bulk substrate21by an ion implantation process conducted under the acceleration voltage of 400 keV-2 MeV with a dose of 2×1012cm−2-1×1014cm−2. With this, the deep n-type well21DNW is formed with a depth deeper than the bottom edge of the device isolation region21I.

Further, while using the same resist pattern R1as a mask, an ion implantation of boron (B) is conducted into the silicon bulk substrate21under the acceleration voltage of 5 keV-20 keV and the dose of 1×1012cm−2-5×1013cm−2. With this, there are formed a shallow p-type well21PW and further a p-type injection region NVT for channel doping of the n-channel MOS transistors NMOS1and NMOS2in the surface part of the silicon bulk substrate21with a bottom edge at the depth of 30 nm-100 nm, which is shallower than the bottom edge of the device isolation region21I (a typical source/drain region has a thickness of about 20 nm-60 nm, and a buried layer has a thickness of 30 nm-150 nm. Thus, it is adjusted such that the well depth is included in the depth range of the buried layer). In the example ofFIG. 10A, it is illustrated that the p-type injection region NVT is formed at the surface part of the p-type well21PW. However, as explained previously, it is possible to use the p-type well21PW also as the p-type injection region NVT.

Referring toFIG. 10B, the device region21A is covered by another resist pattern R2after the step ofFIG. 10A, and ion implantation of arsenic (As) is conducted into the silicon bulk substrate21while using the resist pattern R2as a mask under the acceleration voltage of 20 keV-120 keV and the dose of 1×1012cm−2-5×1013cm−2, such that there is formed a shallow n-type well and an n-type injection region PVT for channel doping of the p-channel MOS transistors PMOS1and PMOS2with a depth of the bottom edge of 30 nm-50 nm, which is shallower than the bottom edge of the device isolation region21I (a typical source/drain region has a thickness of about 20 nm-60 nm and a buried layer has a thickness of 30-150 nm. Thus, it is adjusted that such that the well depth is within the depth range of the buried layer). In the example ofFIG. 10B, too, it is illustrated that the n-type injection region PVT is formed at the surface part of the n-type well21NW. However, as explained previously, it is possible to use the n-type well21NW also as the n-type injection region PVT.

Referring toFIG. 10C, there are formed, after the step ofFIG. 10B, the polysilicon patterns21G1and21G2in the device region21A shown at the left side of the broken line via respective gate insulation films22Ox1and22Ox2. With this, it can be seen that the polysilicon patterns21G1and21G2are formed also in the device region21B at the right side of the broken line ofFIG. 10Cvia the respective gate insulation films22Ox3and22Ox4. Here, it should be noted that the polysilicon patterns21G1and21G2are formed by patterning a polysilicon film while using a hard mask pattern210M of a silicon oxide film or a silicon nitride film as a mask. The hard mask pattern210M is left on the polysilicon patterns21G1and21G2until the steps ofFIGS. 10M and 10Nas will be explained later.

The polysilicon patterns21G1and21G2have sidewall insulation films sw of a silicon oxide film or a silicon nitride film of the thickness of 5-20 nm on the respective sidewall surfaces, wherein it should be noted that, in the step ofFIG. 10C, ion implantation of As is conducted in the device region21A while using the polysilicon patterns21G1and21G2as a mask while using the acceleration voltage of 1 keV-5 keV and the dose such as 1×1013cm−2-2×1015cm−2to form the n-type diffusion regions21a-21cconstituting the source/drain extension regions on the surface of the silicon bulk substrate21that constitutes the device region21A, such that the n-type diffusion region21bis located between the polysilicon patterns21G1and21G2and that the n-type diffusion region21ais located at an outer side of the polysilicon pattern21G1with regard to the n-type diffusion region21band the n-type diffusion region21cis located at an outer side of the polysilicon pattern21G2with regard to the n-type diffusion region21b. When forming the n-type diffusion regions21a-21c, the device region12B is covered by a resist pattern not illustrated.

Further, in the step ofFIG. 10C, B is introduced into the device region21B by an ion implantation process under the acceleration voltage of 0.1 keV-1 keV and the dose such as 1×1012cm−2-2×1015cm−2while using the polysilicon patterns21G1and21G2as a mask to form the p-type diffusion regions21d-21fconstituting the source/drain extension regions on the surface of the silicon bulk substrate constituting the device region21B, such that the p-type diffusion region21eis located between the polysilicon patterns21G1and21G2and such that the p-type diffusion region21dis located at an outer side of the polysilicon pattern21G1as compared with the p-type diffusion region21eand the p-type diffusion region21fis located at an outer side of the polysilicon pattern21G2as compared with the p-type diffusion region21e. When forming the p-type diffusion regions21d-21f, the device region12A is covered by a resist pattern not illustrated.

Referring toFIG. 10D, it can be seen that the deep n-type well21DNW is formed in the silicon bulk substrate21in correspondence to the device region21A and that the polysilicon pattern21G1extends from the device region21A to the device region21B across the device isolation region21I dividing the device region21A and the device region21B. Further, in the device region21A, it can be seen that the gate insulation film22Ox1is interposed between the surface of the silicon bulk substrate21and the polysilicon pattern21G1and that the gate insulation film22Ox2is interposed between the surface of the silicon bulk substrate21and the polysilicon pattern21G2in the device region21B. Further, the both ends of the polysilicon pattern21G1are covered by the sidewall insulation films identical with the sidewall insulation film sw. Further, while not illustrated, a structure similar to that ofFIG. 10Dis formed also in the cross-section along the line D-D′ ofFIG. 4.

FIG. 10Eis a cross-sectional diagram taken along the lines A-A′ and B-B′ ofFIG. 10A, whileFIG. 10Fis a cross-sectional diagram taken along the line C-C′ ofFIG. 4and showing the process ofFIG. 10E.

Referring toFIG. 10E, there are formed an outer sidewall insulation films SW of a silicon oxide film or a silicon nitride film on the polysilicon patterns21G1and21G2after the steps ofFIGS. 10C and 10Dso as to cover the sidewall insulation films sw by a deposition of a silicon oxide film or silicon nitride film of the thickness of 20 nm-50 nm followed by an etchback process. As a result, the outer sidewall insulation films SW are formed to cover the inner sidewall insulation films sw also at the end parts of the polysilicon pattern21G1as represented inFIG. 10F. Further, while not illustrated, a structure similar to that ofFIG. 10Dis formed also in the cross-section taken along the line D-D′ ofFIG. 4. With the present embodiment, the insulation patterns SB1and SB2constituting the silicide block as explained previously with reference toFIG. 4are formed simultaneously to the sidewall insulation films SW so as to extend laterally from the respective polysilicon patterns21G1and21G2, by adding a mask process to the etchback process ofFIGS. 10E and 10Ffor forming the sidewall insulation films SW.

Referring toFIG. 10G, the surface of the silicon bulk substrate21is subjected to a dry etching process conducted by an RIE method after the step ofFIGS. 10E and 10Fwhile using the sidewall insulation films SW and the polysilicon patterns21G1and21G2covered with a hard mask pattern21OM as a mask, and there are formed trenches T1, T2and T3exceeding the bottom edge of the p-type well21PW and reaching the deep n-type well21DNW in the device region21A, such that the trench T2is located between the polysilicon patterns21G1and21G2and such that the trench T1is located at an outer side of the polysilicon pattern21G1with regard to the trench T2and the trench T3is located at an outer side of the polysilicon pattern21G2with regard to the trench T2.

As a result of such formation of the trenches T1-T3in the device region21A, the shallow p-type well21PW is split into the first body region21BY1and the second body region21BY2as represented inFIG. 10G. Likewise, the p-type injection region NVT thereon is split into the channel dope region NVT1on the body21BY1and the channel dope region NVT2on the body21BY2.

At the same time, in the device region21B, there are formed trenches T4, T5and T6exceeding the bottom edge of the n-type well21NW by the dry etching process, such that the trench T5is located between the polysilicon patterns21G1and21G2and that the trench T4is located at an outer side of the polysilicon pattern21G1with regard to the trench T5and the trench T6is formed at an outer side of the polysilicon pattern21G2with regard to the trench T5. As an example, the trenches T1-T6may be formed with a depth of 70 nm from the surface of the silicon bulk substrate21.

As a result of such formation of the trenches T4-T6in the device region21B, the shallow n-type well21NW is split into the third body region21BY3and the fourth body region21BY4as represented inFIG. 10G. Likewise, the n-type injection region PVT thereon is split into the channel dope region PVT1on the body21BY3and the channel dope region PVT2on the body21BY4.

Further, at the time of the step ofFIG. 10G, the silicon bulk substrate21is subjected also to a dry etching process at the both ends of the polysilicon pattern21G1with the hard mask pattern210M covering the polysilicon pattern21G1and the sidewall insulation films SW serving as a self-alignment mask, and as a result, there is formed a trench T7in the device region21A in correspondence to the end part of the polysilicon pattern21G1and there is further formed a trench T8in the device region21B in correspondence to the end part of the polysilicon pattern21G2, with a depth identical with the depth of the trenches T1-T6.

While explanation is omitted, a similar structure toFIG. 10His formed also in the cross-section D-D′ ofFIG. 4.

FIG. 10Iis a cross-sectional diagram taken along the lines A-A′ and B-B′ ofFIG. 10A, whileFIG. 10Jis a cross-sectional diagram taken along a line C-C′ ofFIG. 4for showing the process ofFIG. 10I.

Referring toFIG. 10I, a silicon oxide film is deposited on the structure ofFIG. 10Gafter the step ofFIGS. 10G and 10Hby a film forming method such as a reactive sputtering process that has anisotropy and causes preferential deposition in the direction perpendicular to the substrate surface, such that the insulation regions21I1,21I2,21I3,21I4,21I5and21I6noted before are formed respectively on the bottom of the trenches T1, T2, T3, T4, T5and T6, with a thickness of 20 nm-50 nm, for example, in such a manner that the top edges thereof exceed the bottom edge of the shallow p-type well21PW, and hence the bottom edge of the body21BY1, and further the bottom edge of the shallow n-type well21NW, and hence the bottom edge of the body21BY3. Thereby, the thickness of the insulation regions21I1,21I2,21I3,21I4,21I5and21I6is set to a thickness that exceeds the bottom edges of the shallow p-type well21PW and the shallow n-type well21NW even after the etching process to be explained below with reference toFIGS. 10K and 10Lis conducted.

With the formation of the insulation regions21I1,21I2,21I3,21I4,21I5and21I6, the insulation regions21I9and21I10explained previously with reference toFIG. 8are formed also in the cross-section ofFIG. 10Jin the manner to fill the trenches T7and T8with the thickness exceeding the bottom edges of the shallow p-type well21PW, and hence the body21BY1, and also the n-type well21NW, and hence the body21BY3.

While the details are omitted, a structure similar to that ofFIG. 10Jis formed also in the cross-section D-D′, and thus, the insulation region21I9is formed in the device region21A in correspondence to the end of the polysilicon pattern21G2and the insulation region21I10is formed in the device region21B in correspondence to the end of the polysilicon pattern21G2.

Further, with the formation of the insulation regions21I1-21I10, there is formed a silicon oxide film21O on the polysilicon patterns21G1and21G2so as to cover the sidewall insulation films SW and further the hard mask patterns21OM. A similar silicon oxide film21O is formed also on the device isolation structure21I.

In the step ofFIGS. 10I and 10J, it is also possible to form the insulation regions21I1-21I10by ion implantation of oxygen followed by a thermal annealing process as will be explained later with reference to embodiments.

In the process ofFIGS. 10K and 10L, the structure represented inFIGS. 10I and 10Jis immersed into a HF etchant for a short time, and the silicon oxide film deposited at the time of formation of the insulation regions21I1-21I10is removed from the exposed sidewall surfaces, circled by broken lines inFIGS. 10K and 10L, of the partially filled trenches T1-T8by a wet etching process. As a result, a fresh silicon surface is exposed.

In the wet etching process ofFIG. 10KandFIG. 10L, the silicon oxide film constituting the insulation regions21I1,21I2,21I3,21I4,21I5and21I6also experiences etching. However, the film thickness loss for these insulation regions21I1,21I2,21I3,21I4,21I5and21I6can be made negligible by conducting the immersion into the HF etchant for only a short time. Anyway, the insulation regions21I1,21I2,21I3,21I4,21I5and21I6are formed so as to exceed the bottom edge of the shallow p-type well21PW and hence the bodies21BY1and21BY2of p-type in the device region21A or the bottom edge of the shallow n-type well21NW and hence the bodies21BY3and21BY4in the device region21B even after the wet etching process ofFIGS. 10K and 10Las explained previously.

Referring toFIGS. 10M and 10N, there is conducted a lateral epitaxial growth of a monocrystalline silicon epitaxial layer21epafter the step ofFIGS. 10K and 10Lin the trenches T1-T8by starting from the silicon surface of the monocrystalline silicon bulk substrate21exposed at the sidewall surfaces of the trenches T1-T8at the substrate temperature of 700° C.-800° C., and with this, the trenches T1-T8are filled.

It should be noted that in the step ofFIGS. 10M and 10N, these monocrystalline silicon epitaxial layer21epis not yet doped to any of the p-type or n-type. In the step ofFIGS. 10M and 10N, illustration of formation of the epitaxial layer21epis omitted as the formation thereof in the trenches T9and T10is the same as in the case of the cross-sectional diagram ofFIG. 10N.

While it is illustrated in the step ofFIGS. 10M and 10Nthat the top surface of the respective silicon epitaxial layers are coincident to the top surface of the silicon bulk substrate21, it is also possible to form these monocrystalline silicon epitaxial layers to have the top surface exceeding the top surface of the silicon bulk substrate21. In such a case, there may be formed facets in the respective silicon epitaxial layers by Si crystal surfaces as represented inFIGS. 11A and 11B. However, no problem is caused with this.

Further, it is possible to set the extending direction of the polysilicon patterns21G1and21G2formed on the monocrystalline silicon bulk substrate of the (100) surface orientation to the <100> direction in anticipation of such a growth of the monocrystalline silicon epitaxial layer21ep, such that the sidewall surfaces of the trenches T1-T10expose the Si (100) surface.

Further, while not illustrated, it is also possible to form a monocrystalline SiC epitaxial layer, characterized by a lattice constant smaller than that of Si that constitutes the silicon bulk substrate21particularly in the device region21A in place of the monocrystalline silicon epitaxial layer21epand attain improvement of the operational speed of the n-channel MOS transistors NMOS1and NMOS2by applying a uniaxial tensile stress to the channel regions of these transistors.

Further, it is also possible to form a monocrystalline SiGe epitaxial layer of larger lattice constant than the silicon bulk substrate21in the device region21B in place of the monocrystalline silicon epitaxial layer21epand attain improvement of the operational speed of the p-channel MOS transistors PMOS1and PMOS2by applying a uniaxial compressive stress to the channel region of these MOS transistors.

Further, it is possible to reduce the temperature of the epitaxial growth in each of the trenches T1-T10by forming a monocrystalline SiGe mixed crystal layer in place of the monocrystalline silicon epitaxial layer21epwith a Ge concentration that does not affect the channel stress of the n-channel MOS transistors NMOS1, NMOS2and the p-channel MOS transistors PMOS1and PMOS2.

FIG. 10Ois a cross-sectional diagram taken along the lines A-A′ and B-B′ ofFIG. 10AwhileFIG. 10Pis a cross-sectional diagram taken along the line C-C′ ofFIG. 4for showing the process of FIG.10O.

Referring toFIGS. 10O and 10P, the silicon oxide film21O is removed together with the underlying hard mask pattern21OM by a wet etching process, for example, after the step ofFIGS. 10L and 10M, and a p-type impurity element such as B is introduced into the entirety of the device region21A by ion implantation while using the ion injection mask M1illustrated inFIG. 12A. With this, the entirety of the monocrystalline silicon epitaxial layer21epin the device region21A including a part of the polysilicon patterns21G1and21G2is doped to the p-type with a concentration similar to that of the p-type well. Next, as represented inFIG. 12B, an n-type impurity element such as As or P is introduced into the entirety of the device region21B by ion implantation while using an ion implantation mask M2illustrated inFIG. 12B, and the entirety of the monocrystalline silicon epitaxial layer21epin the device region21B is doped to the n-type with a concentration similar to that of the n-type well21NW.

Further, in the step ofFIGS. 10O and 10P, an n-type impurity element such as As or P is introduced into the monocrystalline silicon epitaxial layer21epat both lateral sides of the polysilicon patterns21G1and21G2in the device region21A while using an ion implantation mask M3illustrated inFIG. 12Cwith high concentration, and with this, the silicon monocrystalline regions21DN1and21SN1, and hence the silicon monocrystalline region21DN2, and further the silicon monocrystalline region21SN2are doped to the n+-type. In the case P is introduced, the ion implantation process may be conducted under the acceleration voltage of 10 keV for example with the dose of about 6×1015cm−2, while in the case As is introduced, the ion implantation process may be conducted under the acceleration voltage of 10 keV for example with the dose of about 6×1015cm−2.

In the step ofFIGS. 10O and 10P, it should be noted that the ion implantation of the same n-type impurity element takes place also in the part of the monocrystalline epitaxial layer21eof the device region21B in the vicinity of the tip end part of the polysilicon patterns21G1and21G2at the same time, and as a result, the ohmic regions21N+1 and21N+2 doped to the n+-type are formed similarly to the diffusion regions21SN1,21DN1,21SN2and21DN2. It should be noted that the ohmic regions21N+1 and21N+2 are isolated electrically as can be seen from the shape of the mask M3ofFIG. 12C, and because of this, there occurs no electrical interference between the bodies21BY1and21BY2in the device region21A.

Further, with the foregoing ion implantation, the part of the polysilicon patterns21G1and21G2extending through the device region21A is doped to the n+-type, and with this, the n-type polysilicon gate electrodes23G1N and23G2N of the n-channel MOS transistors NMOS1and NMOS2are formed.

FIG. 10Qis a cross-sectional diagram taken along the lines A-A′ and B-B′ ofFIG. 10AwhileFIG. 10Ris a cross-sectional diagram taken along the line C-C′ ofFIG. 4for showing the process ofFIG. 10Q.

Referring toFIG. 10Q, a p-type impurity element such as B is introduced into the device region21B after the step ofFIGS. 10O and 10Pwith high concentration while using an ion implantation mask M4shown inFIG. 12D, and with this, the silicon monocrystalline regions21SP2and21DP2, and hence the silicon monocrystalline region21DP1, and further the silicon monocrystalline region21SP1are doped to the p+-type. The foregoing ion implantation may be conducted for example under the acceleration voltage of 3 keV and the dose of about 5×1015cm−2.

In the step ofFIGS. 10Q and 10R, it should be noted that the ion implantation of the same p-type impurity element takes place also in the device region21A in the vicinity of the tip end part of the polysilicon patterns21G1and21G2at the same time, and as a result, the ohmic regions21P+1 and21P+2 doped to the p+-type are formed similarly to the diffusion regions21SP1,21DP1,21SP2and21DP2. It should be noted that the ohmic regions21P+1 and21P+2 are isolated electrically as can be seen from the shape of the mask M4ofFIG. 12D, and because of this, there occurs no electrical interference between the bodies21BY3and21BY4in the device region21B.

Further, with the foregoing ion implantation, the part of the polysilicon patterns21G1and21G2extending through the device region21B is doped to the p+-type, and with this, the p-type polysilicon gate electrodes23G1P and23G2P of the p-channel MOS transistors PMOS1and PMOS2are formed.

It should be noted that the process ofFIGS. 10Q and 10Rcan be conducted before the process ofFIGS. 10O and 10P.

Referring toFIGS. 12A and 12B, it can be seen that the device regions21A and21B are defined on the silicon bulk substrate21by the device isolation region21I, and the polysilicon patterns21G1and21G2extend from the device region21A to the device region21B while crossing the intervening device isolation region21I.

Further, in the device region21A, there is formed a depression continuously surrounding the polysilicon patterns21G1and21G2by the trenches T1-T3and the trenches T7and T9formed in the process ofFIGS. 10I and 10J, wherein the depression is filled, after being formed with the insulation regions21I1-21I10at the bottom thereof in the process ofFIGS. 10K and 10L, with the monocrystalline silicon regions21DN1and21SN1, and hence21DN2, and21SN2, continuously as a result of the lateral epitaxial growth in the process ofFIGS. 10M and 10N.

Likewise, in the device region21B, there is formed a depression continuously surrounding the polysilicon patterns21G1and21G2by the trenches T4-T6and the trenches T8and T10formed in the process ofFIGS. 101 and 10J, wherein the depression is filled, after being formed with the insulation regions21I1-21I10at the bottom thereof in the process ofFIGS. 10K and 10L, with the monocrystalline silicon regions21SP1and21DP1, and hence21DP2, and21SP2, continuously as a result of the lateral epitaxial growth in the process ofFIGS. 10M and 10N.

Thus, in the process ofFIGS. 10O and 10P, an ion implantation process of the n-type impurity element is conducted via the mask M3after a preliminary ion implantation process using the masks M1and M2, and the part of the monocrystalline silicon regions21DN1,21SN1, and hence21DN2, and21SN2and the part of the polysilicon patterns21G1and21G2extending through the device region21A, and further the ohmic regions21N+1 and21N+2 of the device region21B are doped to the n+-type similarly to the diffusion regions21SN1,21DN1,21DN2and21SN2.

Further, in the process ofFIGS. 10Q and 10R, an ion implantation of the p-type impurity element is conducted through the mask M4, and as a result, the part of the monocrystalline silicon regions21SP1,21DP1and hence21DP2, and21SP2and the part of the polysilicon patterns21G1and21G2extending through the device region21B and further the ohmic regions21P+1 and21P+2 in the device region21A are doped to the p+-type similarly to the diffusion regions21SP1,21DP1,21DP2and21SP2.

FIG. 10Sis a cross-sectional diagram taken along the same cross-sections A-A′ and B-B′ of FIG.10A whileFIG. 10Tis a cross-sectional diagram taken along the line C-C′ ofFIG. 4during the process ofFIG. 10S.

Referring toFIGS. 10S and 10T, there is formed, after the process ofFIGS. 10Q and 10R, a silicide layer25of nickel silicide, for example, on the exposed surfaces of the polysilicon patterns21G1and21G2, on the exposed surfaces of the monocrystalline silicon regions21DN1,21SN1, and hence21DN2, and21SN2, on the exposed surfaces of the monocrystalline silicon regions21SP1,21DP1, and hence21DP2, and21SP2, and further on the exposed surfaces of the n+-type ohmic regions21N+1 and21N+2 and on the exposed surfaces of the p+-type ohmic regions21P+1 and21P+2, by an ordinary salicide process.

Further, in the process ofFIGS. 10U and 10V, conducted subsequent to the process ofFIGS. 10S and 10T, formation of the interlayer insulation film23is conducted over the silicon bulk substrate21so as to cover the gate electrodes23G1N,23G2N,23G1P and23G2P, and formation of the openings23A and23B explained previously is conducted in the interlayer insulation film23as illustrated inFIG. 10Vsuch that the p+-type ohmic region21P+1 and the n+-type ohmic region21N+1 are exposed. Similarly, the openings23D and23E explained previously are formed also in the cross-section taken along the lines D-D′ so as to expose the p+-type ohmic region21P+2 and the n+-type ohmic region21N+2. Reference should be made to the cross-sectional diagram ofFIG. 8.

Further, in the cross-sectional diagram ofFIG. 10V, it can be seen that the contact hole23C is formed in the interlayer insulation film23on the device isolation insulation film21I between the device regions21A and21B for the signal IN1in correspondence to the polysilicon pattern21G1. Further, while not illustrated, the contact hole23F for the signal IN2is formed over the device isolation insulation film21I between the device regions21A and21B in correspondence to the polysilicon pattern21G2. Reference should be made to the cross-sectional diagram ofFIG. 8.

Further, by filling the openings23A-23C with a metal plug of tungsten, for example, formation of the via-contacts VC1, VC2and VC5explained with reference toFIG. 7is attained. Similarly, by filling the openings23D-23F with a metal plug of tungsten, for example, formation of the via-contacts VC3, VC4and VC6explained with reference toFIG. 8is attained.

Further, after formation of the signal wiring patterns24A and24B as necessary, the interlayer insulation film24is formed on the structure ofFIGS. 10U and 10V. Further, after formation of the via-contacts VC7-VC11, the semiconductor logic circuit device20having the cross-section ofFIGS. 5-9and the layout explained with reference toFIG. 4is obtained.

In the aforementioned fabrication process of the semiconductor logic circuit20, it should be noted that the processes ofFIGS. 10A-10FandFIGS. 10O-10Rare identical to the fabrication process of ordinary, non-dynamic threshold MOS transistors. Thus, according to the present embodiment, it becomes possible to form MOS transistors performing non-dynamic threshold operation on the same semiconductor bulk substrate simultaneously to the semiconductor logic circuit device20. Thereby, as noted previously, there is no need of changing the construction of the ordinary MOS transistors, when forming the MOS transistors performing non-dynamic threshold operation, such as providing a contact hole for fixing the body potential.

Thus, as represented inFIG. 13A, it is possible to integrate easily a CMOS device40, for example, on the same silicon bulk substrate on which the semiconductor logic circuit device20ofFIG. 4is formed.

Referring toFIG. 13A, it can be seen that the NAND circuit20explained previously with reference toFIG. 4is formed on the device regions21A and21B, wherein device regions41and41B are defined on the same silicon bulk substrate21by the device isolation region21I, and the polysilicon pattern21G3extends from the device region41A to the device region41B over the device isolation region21iintervening between the device regions41A and41B.

The polysilicon pattern21G3is doped to n+-type in the device region41A and constitutes the gate electrode of the n-channel MOS transistor NMOS3. Thus, in the device region41A, there are formed a source SN and a drain DN by n+-type diffusion regions at both lateral sides of the polysilicon pattern21G3, wherein the source SN is connected to the ground power supply GND via a via-contact VC16and a ground wiring pattern GD2.

Similarly, the polysilicon pattern21G3is doped to p+-type in the device region41B and constitutes the gate electrode of the p-channel MOS transistor PMOS3. Thus, in the device region41A, there are formed a source SP and a drain DP by p+-type diffusion regions at both lateral sides of the polysilicon pattern21G3, wherein the source SP is connected to the power supply Vcc via a via-contact VC14and a ground wiring pattern PW3. Further, the drain DP of the p-channel MOS transistor PMOS3is connected to the drain of the n-channel MOS transistor NMOS3via a via-contact VC13, a local wiring pattern WP2and a via-contact VC15, wherein the n-channel MOS transistor NMOS3and the p-channel MOS transistor pMOS3constitutes the CMOS device40.

In each of the n-channel MOS transistor NMOS3an the p-channel MOS transistor PMOS3, the gate electrode is not connected to the body and the MOS transistor performs a non-dynamic threshold operation.

Thus, with the present embodiment, it becomes possible to integrate easily a circuit that uses a Dt-MOS transistor and a circuit that uses a non Dt-MOS transistor on the same substrate while using a silicon bulk substrate.

Further, while not illustrated, it is also possible to construct the n-channel MOS transistor NMOS2and the p-channel MOS transistor PMOS3constituting the CMOS device40to have a Dt-MOS construction in the construction ofFIG. 13A. In this case, the gate electrode21G3of the n-channel MOS transistor NMOS3is merely connected to the body thereof by a via-contact. Likewise, the gate electrode of the p-channel MOS transistor PMOS3is merely connected to the body thereof by a via-contact.

In the present embodiment, the depth of the bottom edge of the p-type well21PW and the depth of the bottom edge of the n-type well21NW are not necessarily coincident but may be changed with each other. Further, while the insulation regions21I1-21I10inevitably have the same depth with the process ofFIGS. 10A-10V, it is possible to change the depth of the insulation regions21I1-21I10between the device regions21A and21B when the insulation regions21I1-21I10are formed by ion implantation of oxygen as will be explained later with reference to other embodiments, by way of changing the acceleration voltage of the oxygen ions between the device regions21A and21B.

FIG. 13Brepresents the plan view of a single n-channel Dt-MOS transistor used with the semiconductor logic integrated circuit20in the present embodiment, whileFIG. 13Crepresents a cross-sectional diagram of the MOS transistor ofFIG. 13Btaken along a line X-X′.

Referring toFIGS. 13B and 13C, there is formed a deep n-type well41DNW under the device region41NMOS defined with a device isolation structure41I, which corresponds to the device isolation structure21I, in correspondence to the deep n-type well21DNW, and there is formed a p-type well41PW above the deep n-type well41DNW right underneath the polysilicon pattern41G that corresponds to the polysilicon pattern21G1and constitutes the gate electrode of the re-channel MOS transistor40, in such a manner to extend along the polysilicon pattern41G. Further, a channel dope region NVT of p-type is formed in the surface of the p-type well41PW. The gate electrode41G is formed on the device region41NMOS via a gate insulation film41Gox.

In the device region41NMOS, there are formed a source diffusion region of n+-type and a drain diffusion region of n+-type at a first side and an opposite side of the gate electrode41G while using a Mask1represented inFIG. 13Bas an ion implantation mask, wherein the source and drain regions are formed with a source contact S and a drain contact D, respectively. Further, the gate electrode41G is doped to n+-type in the device region41NMOS. According to the present embodiment, the n-channel MOS transistor has an insulation pattern not illustrated similar to the insulation patterns21I1-21I3right underneath the source diffusion region and the drain diffusion region similarly to the n-channel MOS transistors NMOS1or NMOS2of which cross-section was represented previously inFIG. 5, and the source diffusion region and the drain diffusion region are formed epitaxially by a regrowth process on such insulation patterns.

Meanwhile, with the present embodiment, the device region41NMOS defined by the device isolation region41I has an extension part41exin a part thereof, wherein a head part41Gh of the gate electrode41G is formed on the extension part41exso as to cover the extension part41expartially via the gate insulation film41Gox.

Further, the head part41Gh of the gate electrode41G and the extension part41exare doped to the p+-type by using a MASK2represented inFIG. 13Bas an ion implantation mask.

Underneath the extension part41ex, there is formed an insulation pattern41isimilar to the insulation patterns21I7-21I10of the previous embodiment in continuation with the device isolation structure21I, and the epitaxial layer of silicon formed on the insulation pattern41iby a regrowth process constitutes the extension part41ex.

Further, there is formed a silicide layer45on the surfaces of the polysilicon pattern41G and the source/drain diffusion regions in the device region41NMOS and further on the surface of the extension part41ex, and the gate electrode41G is connected to the extension part41exby a via-plug VC.

With the present embodiment, the silicide layer45sformed on the extension region41exis isolated from the silicide layer45formed on the surface of the device region41NMOS by the head part41Gh of the polysilicon pattern41G, and it becomes possible to avoid the short circuit between the via-contact VC and the source diffusion region or drain diffusion region without forming the silicide block patterns SB1or SB2of the previous embodiment.

Further, it is possible to form a p-channel Dt-MOS transistor similarly. In this case, however, the deep n-type well41DNW is not used. The construction of the p-channel Dt-MOS transistor would be obvious from the explanation of the explanation of previous embodiments made with reference toFIGS. 13B and 13CandFIGS. 10A-10C, and thus, further explanation will be omitted.

FIG. 13Dis a plan view diagram showing the layout of an inverter60that uses the n-channel Dt-MOS transistor41ofFIGS. 13B and 13Cand a corresponding p-channel Dt-MOS transistor, whileFIG. 13Erepresents a cross-sectional diagram taken along a line Y-Y′ ofFIG. 13D.

Referring toFIGS. 13D and 13E, the inverter60comprises an n-channel Dt-MOS transistor NMOS of the construction similar to that of the re-channel Dt-MOS transistor NMOS1or NMOS2ofFIG. 5and a p-channel Dt-MOS transistor PMOS of the construction similar to that of the p-channel Dt-MOS transistor PMOS1or PMOS2ofFIG. 6, wherein the re-channel Dt-MOS transistor NMOS is formed in a device region61A defined on the silicon substrate21by the device isolation region21while the p-channel Dt-MOS transistor PMOS is formed in a device region61B defined on the silicon substrate21by the device isolation region21I.

The device region61A has an extension part61Aex in a part thereof, while the device region61B has an extension part61Bex in a part thereof, wherein the extension parts61Aex and61Bex are connected with each other, and thus, the device region61A and the device region61B forms a single active region. The device region61A, including the extension part61Aex, is formed with a deep n-type well61DNW in a lower part thereof in correspondence to the deep n-type well21DNW.

On the device region61A, there extends a polysilicon gate electrode61G1via a gate insulation film61Gox1including the extension part61Aex, and there extends a p-type well61PW right underneath the polysilicon gate electrode61G1in correspondence to the p-type well21PW. Similarly, there extends a polysilicon gate electrode61G2on the device region61B via a gate insulation film61Gox2including the extension part61Bex, and there extends an n-type well61NW right underneath the polysilicon gate electrode61G2in correspondence to the p-type well21NW.

Further, similarly to the previous embodiments, there is formed a channel dope region NVT on the surface of the p-type well61PW for the re-channel MOS transistor NMOS, and there is further formed a channel dope region PVT on the surface of the n-type well61NW for the p-channel MOS transistor PMOS.

With the inverter60of the present embodiment, there is formed an insulation pattern61isimilar to the insulation patterns21I7-21I10of the previous embodiment underneath the extension parts61Aex and61Bex in continuation, wherein there is formed an epitaxial layer of silicon on the insulation pattern61iby a regrowth process to form the extension parts61Aex and61Bex. Thereby, the silicon epitaxial layer is doped to the p+-type in the extension part61Aex to form an ohmic contact region61P+ and further to the n+-type in the extension part61Bex to form an ohmic contact region61N+.

The polysilicon gate electrodes61G1and61G2have respective surfaces formed with a silicide layer65, wherein the silicide layer65is formed also on the surface of the ohmic contact regions61P+ and61N+ continuously from the ohmic contact region61+ to the ohmic contact region61N+. Further, a via-plug61inis formed on the ohmic contact regions61P+ and61N+ so as to bridge between the gate electrodes61G1and61G2.

Thus, by supplying an input voltage signal to the via-plug61inand connecting the drain region D of the p-channel Dt-MOS transistor PMOS to the drain region D of the n-channel Dt-MOS transistor NMOS via a wiring pattern61WR and further supplying a supply voltage Vcc to the source region S of the p-channel MOS transistor PMOS by a power wiring patter61PWR and by grounding the drain region D of the n-channel MOS transistor NMOS as represented inFIG. 13D, the device ofFIG. 13Doperates as an inverter.

In the present embodiment, too, the silicide layer65formed on the ohmic contact regions61P+ and61N+ is isolated from the silicide layer formed on the source region S or drain region D of the device region61A or from the silicide layer formed on the source region S or drain region D of the device region61B by the gate insulation film61Gox1right underneath the polysilicon gate electrode61G or the gate insulation film61Gox2right underneath the polysilicon gate electrode61G2, and thus, there is no need of forming the silicide block pattern SB1or SB2as in the previous embodiment.

Further,FIG. 13Fshows the construction of a dual input NAND device80that uses an inverter structure ofFIGS. 13D and 13Eaccording to a modification of the dual input NAND device40ofFIG. 4. InFIG. 13, those parts explained before are designated by the corresponding reference numerals and the description thereof will be omitted.

In the modification ofFIG. 13F, there are provided two polysilicon patterns21G1A and21G1B in place of the polysilicon pattern21G1ofFIG. 4. Further, there are used two polysilicon patterns21G2A and21G2B in place of the polysilicon pattern21G2.

Thereby, it should be noted that with the present embodiment, the cross-section taken along the lines Z1-Z1′ or Z2-Z2′ inFIG. 13Fhas a structure similar to that of the cross-section ofFIG. 13E, and thus, the via-contact VC5constitute the first signal input terminal and at the same time connects the polysilicon patterns21G1A and21G1B respectively to the p-type ohmic region21P+1 and to the n-type ohmic region21N+1. Similarly, the via-contact VC6constitutes the second input terminal and at the same time connects the polysilicon patterns21G2A and21G2B respectively to the p-type ohmic region21P+2 and to the n-type ohmic region21N+2. With this, the present embodiment eliminates the via-contacts VC1-VC2inFIG. 4.

Further, with the present modification, there is no need of forming the silicide block patterns SB1and SB2as in the embodiment ofFIG. 4.

As a result, it becomes possible according to the present modification to reduce the area of the dual input NAND device ofFIG. 4.

Second Embodiment

While the first embodiment has formed the insulation regions21I1-21I10in the silicon bulk substrate21by forming a trench and depositing a silicon oxide film in the trench thus formed, it is also possible to form the insulation regions21I1-21I10by way of ion implantation of oxygen ions as will be explained below.

FIG. 14Acorresponds to the process ofFIGS. 10C and 10Dnoted previously, wherein the present embodiment forms a cover film21M blocking injection of oxygen ions on the surface of the polysilicon patterns21G1and21G2in place of the hard mask pattern21OM by a tungsten (W) film for example with a thickness of 30 nm-50 nm.

Further, in the step ofFIG. 14B, oxygen ions O+ are introduced into the structure ofFIG. 14Aby an ion implantation process while using the cover film21M as a mask under the acceleration voltage of 10 kev-60 keV and a dose of 1×1016cm−2or more to form oxygen doped regions21J1-21J6in correspondence to the insulation regions21I1-21I6. While not illustrated, similar oxygen doped regions are formed also in correspondence to other insulation regions21I7-21I10. The depth of the oxygen doped regions21J1-21J6can be controlled by the acceleration voltage, and thus, it becomes possible to control the top edge of the oxygen doped regions21J1-21J6at the depth of 27 nm by using an acceleration voltage of 10 keV, for example. Further, in the case of using the acceleration voltage of 60 keV, it is possible to control the top edge of the oxygen doped regions21J1-21J6at the depth of 140 nm.

Further, by conducting a rapid thermal annealing (RTA) process to the structure thus introduced with the oxygen ions at the temperature of 1050° C. or by conducting a millisecond thermal annealing (MSA) process with an energy of 20 mJ/cm2 or more, the introduced oxygen atoms are caused to react with Si atoms, and the oxygen doped regions21J1-21J6are converted respectively to the insulation regions21I1-21I6of silicon oxide film. The insulation regions21I7-21I10are formed similarly.

Next, in the step ofFIG. 14C, the cover film21M is removed and the structure shown inFIG. 14Cis obtained. Thus, by conducting the process ofFIGS. 10O and 10Pand thereafter to this structure, it becomes possible to fabricate the semiconductor logic circuit20ofFIG. 4.

Third Embodiment

FIGS. 15A-15Drepresent a third embodiment. It should be noted thatFIGS. 15A-15Drepresent the process that follow the process ofFIGS. 10G and 10Hand replace the process ofFIGS. 10I-10N.

Referring toFIG. 15A, the present embodiment forms a layer21Ge, which is a consecutive stack of a SiGe mixed crystal layer, a Ge layer and a SiGe mixed crystal layer formed in the lower part of the trenches T1-T8after the process ofFIGS. 10G and 10H, by a sputtering process or CVD process, with such a thickness, such that the top edge of the layer21G2exceeds the top edge of the p-type well21PW or the n-type well21NW. The layer21Ge thus formed allows easy formation of a silicon epitaxial layer thereon in view of the fact that there exists a SiGe mixed crystal layer between the underlying silicon substrate and the Ge layer and that the SiGe mixed crystal layer is formed further on the Ge layer.

InFIG. 15A, it should be noted that the re-channel MOS transistor NMOS1represents a part of the A-A′ cross-section inFIG. 4while the p-channel MOS transistor PMOS1represents a part of the B-B′ cross-section inFIG. 4.

Next, in the step ofFIG. 15B, the present embodiment forms the monocrystalline silicon epitaxial layer21epon the layer21Ge by an epitaxial growth process. It should be noted that the formation of the monocrystalline silicon epitaxial layer21epcan be conducted under the condition explained previously with reference toFIGS. 10M and 10N.

Next, in the step ofFIG. 15C, the present embodiment forms an opening21eoin the monocrystalline silicon epitaxial layer21epin each of the device regions21A and21B so as t expose the Ge layer the underlying layer21Ge, and the silicon bulk substrate21is annealed in an oxygen ambient at the temperature of 600°. As a result, the Ge layer constituting the layer21Ge is vaporized in the form of GeO and is expelled to the outside of the system from the opening21eo.

As a result, there is formed a space21V underneath the monocrystalline silicon epitaxial layer21epin the present embodiment as represented inFIG. 15Din place of the insulation regions21I1-21I10of the previous embodiments. The space21V thus formed exhibits an insulation function similar to those of the insulation regions21I1-21I10, except that, because of the specific dielectric constant of 1.0, the space21V provides preferable effects of further reduced parasitic capacitance and further improved operational speed for the n-channel MOS transistors NMOS1and NMOS2and the p-channel MOS transistor PMOS1and PMOS2.

InFIG. 15D, the layer21Ge remaining in the structure corresponds to the SiGe mixed crystal layer contained in the stacked structure.

Fourth Embodiment

FIG. 16is a plan view diagram representing the construction of a logic integrated circuit device according to a fourth embodiment. InFIG. 16, those parts explained before are designated by the same reference numerals and the description thereof will be omitted.

Referring toFIG. 16, the semiconductor logic circuit device60according to the present embodiment is an NOR circuit device and has the construction in which the device regions21A and21B are exchanged and the n-channel MOS transistor NSMO1and the p-channel MOS transistor PMOS2are exchanged and the n-channel MOS transistor NMOS2and the p-channel MOS transistor PMOS1are exchanged in the construction ofFIG. 4. In the present embodiment, too, the n-channel MOS transistor NMOS1and the re-channel MOS transistor NMOS2, and the p-channel MOS transistor PMOS1and the p-channel MOS transistor PMOS2are Dt-MOS transistors and are formed on a silicon bulk substrate.

Other constructions and advantages are as explained in the first embodiment and further explanation will be omitted.

Fifth Embodiment

The present invention should not be limited to those explained with first through fourth embodiments.

For example, the construction ofFIG. 4in which the n-channel MOS transistors NMOS1and NMOS2of the Dt-MOS construction are connected in series, or the construction ofFIG. 16in which the p-channel MOS transistors PMOS1and PMOS2of the Dt-MOS construction are connected in series, can be used independently as a semiconductor device such as a transfer gate, for example.

FIG. 17represents an equivalent circuit diagram of a transfer gate formed by these Dt-MOS transistors NMOS1and NMOS2.

Referring toFIG. 17, it becomes possible to transfer a signal such as electric charge from one end to the other end in the Dt-MOS transistors NMOS1and NMOS2by supplying control signals C1and C2to the respective gate electrodes consecutively. Further, a similar transfer gate can be realized also by using Dt-MOS transistors PMOS1and PMOS2.