Resistance change memory device and associated methods

According to one embodiment, a memory device includes a resistance change memory element to which one of a low-resistance state and a high-resistance state is allowed to be set in accordance with a write current, a first transistor including a first gate, and causing a current to flow through the resistance change memory element in a first write period, a voltage holding section holding a first voltage applied to the first gate in the first write period, and a second transistor including a second gate, in which the first voltage held in the voltage holding section is applied to the second gate, thereby causing a current to flow through the resistance change memory element in a second write period after the first write period.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is based upon and claims the benefit of priority from Japanese Patent Application No. 2019-168649, filed Sep. 17, 2019, the entire contents of which are incorporated herein by reference.

FIELD

Embodiments described herein relate generally to a memory device.

BACKGROUND

A memory device in which a resistance change memory element such as a magnetoresistive element is integrated on a semiconductor substrate has been proposed.

DETAILED DESCRIPTION

In general, according to one embodiment, a memory device includes: a first resistance change memory element to which one of a first low-resistance state and a first high-resistance state is allowed to be set in accordance with a write current; a first transistor including a first gate, a first source and a first drain and causing a current to flow through the first resistance change memory element in a first write period; a voltage holding section holding a first voltage applied to the first gate in the first write period; and a second transistor including a second gate, a second source and a second drain, in which the first voltage held in the voltage holding section is applied to the second gate, thereby causing a current to flow through the first resistance change memory element in a second write period after the first write period.

Embodiments will be described below with reference to the accompanying drawings.

First Embodiment

FIG. 1is schematic diagram showing a configuration of a memory device, namely, a semiconductor integrated circuit device according to a first embodiment.

The memory device shown inFIG. 1includes a memory cell array area10, a local word line (LWL) selection circuit20, a bit line (BL) selection circuit30, a global word line (GWL) selection circuit40, a first transistor51, a second transistor52and a voltage holding section53.

FIG. 2is a schematic bird's eye view showing a basic configuration of the memory cell array area10.

As shown inFIG. 2, the memory cell array area10includes a plurality of memory cells MC, a plurality of word lines WL and a plurality of bit lines BL. Each of the memory cells MC is connected between its corresponding word line WL and its corresponding bit line BL. Applying a predetermined voltage between a word line WL connected to a target memory cell MC and a bit line BL connected to the target memory cell MC to cause a predetermined current to flow makes it possible to write data to the target memory cell MC and read data therefrom. Each of the memory cells MC includes a magnetoresistive element (resistance change memory element)101and a selector (switching element)102connected in series to the magnetoresistive element (resistance change memory element)101.

In the example shown inFIG. 2, the bit lines BL are provided on the upper-layer side of the word lines WL, but they may be provided on the lower-layer side of the word lines WL. In the example shown inFIG. 2, the selector102is provided on the upper-layer side of the magnetoresistive element101, but it may be provided on the lower-layer side of the magnetoresistive element101.

Returning toFIG. 1, the LWL selection circuit20selects a word line WL connected to a target memory cell MC, and the BL selection circuit30selects a bit line BL connected to a target memory cell MC. When a voltage is applied between the selected word line WL and the selected bit line BL to cause a predetermined current to flow, data is written to the target memory cell MC and data is read therefrom, as described above.

The GWL selection circuit40selects a target one from among a plurality of LWL selection circuits20.

FIG. 3is a schematic cross-sectional view showing an exemplary configuration of the magnetoresistive element (resistance change memory element) included in a memory cell MC. Note that the magnetoresistive element is also referred to as a magnetic tunnel junction (MTJ) element.

As shown inFIG. 3, the magnetoresistive element101includes a storage layer (first magnetic layer)101a, a reference layer (second magnetic layer)101b, and a tunnel barrier layer (nonmagnetic layer))101cprovided between the storage layer101aand the reference layer101b.

The storage layer101ais formed of a ferromagnetic layer having a variable magnetization direction. The reference layer101bis formed of a ferromagnetic layer having a fixed magnetization direction. The tunnel barrier layer101cis a nonmagnetic layer formed of an insulating material. Note that the variable magnetization direction means that the magnetization direction changes with a predetermined write current and the fixed magnetization direction means that the magnetization direction does not change with a predetermined write current.

When the magnetization direction of the storage layer101ais parallel to that of the reference layer101b, the magnetoresistive element101is brought into a low-resistance state. When the magnetization direction of the storage layer101ais antiparallel to that of the reference layer101b, the magnetoresistive element101is brought into a high-resistance state. The magnetoresistive element101can thus store binary data in accordance with the resistance state (low-resistance state and high-resistance state). The resistance state (low-resistance state and high-resistance state) of the magnetoresistive element101can be set in accordance with the direction of a write current that flows through the magnetoresistive element101. In other words, the resistance state is set to vary between the case where current flows from the storage layer101atoward the reference layer101band the case where current flows from the reference layer101btoward the storage layer101a.

The example shown inFIG. 3is directed to a bottom-free magnetoresistive element in which the storage layer101ais located on the lower-layer side than the reference layer101b, but a top-free magnetoresistive element in which the storage layer101ais located on the upper-layer side than the reference layer101bmay be used. The magnetoresistive element may further include a shift canceling layer to cancel a magnetic field to be applied to the storage layer101afrom the reference layer101b.

FIG. 4is a schematic diagram showing current-voltage characteristics of the selector (switching element)102included in a memory cell MC. As the selector102, for example, a two-terminal switching element having a switching function may be used.

If a voltage to be applied between two terminals is less than a threshold value, the switching element is in a “high-resistance” state, e.g., in an electrically non-conductive state. If a voltage to be applied between two terminals is equal to or greater than a threshold value, the switching element is in a “low-resistance” state, e.g., in an electrically conductive state.

As shown inFIG. 4, the selector102has bidirectional (positive and negative directions), mutually symmetric current-voltage characteristics. For example, in the current-voltage characteristic in the positive direction, when a voltage between two terminals of the selector102increases and reaches a predetermined voltage V1, the selector102is turned on, the voltage between the two terminals shifts to V2, and the current increases sharply. The same holds true for the current-voltage characteristics in the negative direction. Note that the selector102may not necessarily have symmetric current-voltage characteristics.

Applying a voltage between a word line WL and a bit line BL to turn on the selector102makes it possible to write data to the magnetoresistive element (resistance change memory element)101and read data therefrom.

Returning toFIG. 1, the first transistor51is an NMOS transistor whose gate and drain are diode-connected, and functions as a current-voltage conversion transistor (I-V conversion transistor). A constant-current source61is connected to the first transistor51to cause a constant current to flow through the first transistor51. More specifically, during a first write period, the current supplied from the constant-current source61to the first transistor51is supplied to a selected memory cell MC through the GWL selection circuit40, global word line GWL, LWL selection circuit20and word line WL. During the first write period, therefore, a common current flows through the first transistor51and the magnetoresistive element101and selector102in the selected memory cell MC.

The voltage holding section53holds a first voltage applied to the gate of the first transistor51during the first write period. As described above, a constant current flows between the drain and source of the first transistor51during the first write period. At this time, a switch62is closed, and the voltage holding section53holds the first voltage applied to the gate of the first transistor51.

The voltage holding section53is configured by a capacitor provided at a wiring (gate-to-gate wiring) between the gate of the first transistor51and that of the second transistor52. That is, as the capacitor of the voltage holding section53, a capacitor element can be provided between the gate-to-gate wiring and the ground, and parasitic capacitance of the gate-to-gate wiring can be used. The gate capacitance of the transistor may also be used together with them.

The second transistor52is an NMOS transistor and functions as a clamp transistor in which the first voltage held in the voltage holding section53is applied to the gate and the voltage of the source is clamped based on the voltage applied to the gate during a second write period after the first write period. Specifically, during the second write period, the current supplied to the second transistor52is supplied to a selected memory cell MC through the transistor63, global bit line GBL, BL selection circuit30and bit line BL. That is, during the second write period, a common current flows through the second transistor52and the magnetoresistive element101and selector102in the selected memory cell MC.

FIG. 5is a diagram showing details of a write operation during the first write period.

During the first write period, the switch62is in an on state, the transistor63is in an off state, a transistor64is in an on state, a transistor65is in an off state and a transistor66is in an on state. Accordingly, current I1is supplied from the constant current source61to the magnetoresistive element in a selected memory cell MC through the first transistor51, transistor66and word line WL and then flows to the ground through the bit line BL and the transistor64. In addition, the voltage applied to the gate of the first transistor51is held in the voltage holding section53.

During the first write period, the magnetoresistive element in the memory cell MC is maintained in a low resistance state. Specifically, before the first write period, data is written in advance such that the magnetoresistive element is brought into a low-resistance state. During the first write period, the direction of the current I1flowing through the first transistor51and the magnetoresistive element coincides with that of current flowing through the magnetoresistive element when the magnetoresistive element is set in a low-resistance state. During the first write period, the magnitude of the current I1flowing through the first transistor51and the magnetoresistive element corresponds to that of current which should flow through the magnetoresistive element when the magnetoresistive element is set in a high-resistance state. The magnitude of the current I1flowing through the magnetoresistive element is equal to that of the current which should flow through the magnetoresistive element when the magnetoresistive element is set in a high-resistance state, but the direction of flow of the current I1coincides with that of the current flowing through the magnetoresistive element when the magnetoresistive element is set in a low-resistance state. During the first write period, therefore, the magnetoresistive element is maintained in a low-resistance state.

FIG. 6is a diagram showing details of a write operation during the second write period.

During the second write period, the switch62is in an off state, the transistor63is in an on state, the transistor64is in an off state, the transistor65is in an on state and the transistor66is in an off state. The voltage held in the voltage holding section53is applied to the gate of the second transistor52. Accordingly, current I2is supplied from a predetermined power supply to the magnetoresistive element in a selected memory cell MC through the second transistor52, transistor63and bit line BL and then flows to the ground through the word line WL and the transistor65.

As described above, during the second write period, the voltage held in the voltage holding section53is applied to the gate of the second transistor52. The level of the voltage held in the voltage holding section53is the same as that of the voltage applied to the gate of the first transistor51during the first write period. In addition, the first and second transistors51and52have the same current-voltage characteristics, and the selector connected in series to the magnetoresistive element has a bidirectionally symmetrical current-voltage characteristics. In the initial stage of the second write period, the magnetoresistive element in the memory cell MC is maintained in a low-resistance state as during the first write period. In the initial stage of the second write period, therefore, the magnitude of the current I2flowing through the second transistor52and the magnetoresistive element is equal to that of the current I1flowing through the first transistor51and the magnetoresistive element during the first write period. However, the direction of the current I1flowing through the first transistor51and the magnetoresistive element during the first write period is opposite to that of the current I2flowing through the second transistor52and the magnetoresistive element during the second write period. As has been described, the magnitude of the current I1flowing through the magnetoresistive element during the first write period is equal to that of current which should flow through the magnetoresistive element when the magnetoresistive element is set in a high-resistance state. The direction of the current I2flowing through the magnetoresistive element during the second write period coincides with that of current flowing through the magnetoresistive element when the magnetoresistive element is set in a high-resistance state. During the second write period, therefore, the magnetoresistive element shifts from the low-resistance state to the high-resistance state.

As can be seen from the above description, during the second write period, the source voltage of the second transistor52, which is clamped by the second transistor52, is applied to a memory cell MC, and the magnetoresistive element is set in a high-resistance state. After the magnetoresistive element is set in the high-resistance state during the second write period, the current flowing through the second transistor52and the magnetoresistive element decreases, and the source voltage clamped by the second transistor52is maintained. Since, furthermore, the selector connected in series to the magnetoresistive element is in an on state, an almost constant voltage is applied to the selector. Therefore, even after the magnetoresistive element shifts from the low-resistance state to the high-resistance state, the voltage applied to the magnetoresistive element is maintained at a constant value without increasing.

As described above, in the first embodiment, the voltage applied to the gate of the first transistor51during the first write period is held in the voltage holding section53, and the voltage held in the voltage holding section53is applied to the gate of the second transistor52during the second write period. Performing the write operation as described above makes it possible to perform a constant-voltage write to the magnetoresistive element (resistance change memory element) during the second write period. When a constant-current write is performed instead of the constant-voltage write, a high voltage is applied to the magnetoresistive element when the magnetoresistive element shifts from the low-resistance state to the high-resistance state, which may adversely affect the reliability of the magnetoresistive element and the like. In the first embodiment, the above constant-voltage write makes it possible to reduce adverse effects on the magnetoresistive element when a write operation is performed to set the magnetoresistive element in the high-resistance state and to perform an appropriate write to the magnetoresistive element.

Since, furthermore, the foregoing constant-voltage write can be performed using the first and second transistors51and52in the first embodiment, a large-scale circuit such as an operational amplifier need not be used. A constant-voltage write can thus be performed by a small circuit scale. Accordingly, for example, a write circuit can be placed to correspond to the memory cell array area10. As shown inFIG. 1, for example, the second transistor52can be placed to correspond to the memory cell array area10. It is therefore possible to suppress IR drop, RC delay and the like in a write pass and thus perform a reliable write operation at high speed.

Second Embodiment

Next is a description of a second embodiment. Note that the basic matters of the second embodiment are similar to those of the foregoing first embodiment and thus their descriptions will be omitted.

FIG. 7is schematic diagram showing a configuration of a memory device (semiconductor integrated circuit device) according to the second embodiment. Note that components like those shown inFIG. 1are denoted by like reference numerals and reference symbols.

In the foregoing first embodiment, an NMOS transistor is used for each of the first and second transistors51and52. In the second embodiment, however, a PMOS transistor is used for each of the first and second transistors51and52. Thus, the write direction of the second embodiment is opposite to that of the first embodiment during both the first and second write periods.

Specifically, in the second embodiment, the current supplied to the magnetoresistive element (resistance change memory element) flows through the first transistor51during the first write period, and the current supplied to the magnetoresistive element flows through the second transistor52during the second write period. The other basic operations are similar to those of the first embodiment and thus their descriptions will be omitted.

As described above, the basic configuration and basic operation of the second embodiment are similar to those of the first embodiment, and advantageous effects similar to those of the first embodiment can be obtained from the second embodiment.

Third Embodiment

Next is a description of a third embodiment. Note that the basic matters of the third embodiment are similar to those of the foregoing first embodiment and thus their descriptions will be omitted.

FIG. 8is schematic diagram showing a configuration of a memory device (semiconductor integrated circuit device) according to the third embodiment. Note that components like those shown inFIG. 1are denoted by like reference numerals and reference symbols.

In the third embodiment, a first switch71is provided between the gate (first gate) and drain (first drain) of the first transistor51, and a second switch72is provided between the gate (second gate) and drain (second drain) of the second transistor52. With this configuration, each of the first and second transistors51and52can have different functions.

FIG. 9is a schematic bird's eye view showing a basic configuration of the memory cell array area10of the third embodiment.

As shown inFIG. 9, in the third embodiment, two memory cells MC1and MC2are provided at corresponding positions in the memory cell array area10. Specifically, a first memory cell MC1is provided between a word line WL and a first bit line BL, and a second memory cell MC2is provided between the word line WL and a second bit line BL2. The basic configuration of each of the memory cells MC1and MC2is similar to that of the memory cell MC of the first embodiment. The first memory cell MC1includes a first magnetoresistive element (first resistance change memory element)111and a first selector (first switching element)112, and the second memory cell MC2includes a second magnetoresistive element (second resistance change memory element)121and a second selector (second switching element)122. The basic configuration of each of the magnetoresistive elements (resistance change memory elements)111and121is similar to that of the magnetoresistive element (resistance change memory element)101of the first embodiment, and the basic configuration of each of the selectors (switching elements)112and122is also similar to that of the selector (switching element)102of the first embodiment 1.

As shown inFIG. 9, in the third embodiment, the first bit line BL1is provided on the upper-layer side of a word line WL and the second bit line BL2is provided on the lower-layer side of the word line WL. The order in which the storage layer, tunnel barrier layer and reference layer are stacked one on another in the first magnetoresistive element111is the same as the order in which the storage layer, tunnel barrier layer and reference layer are stacked one on another in the second magnetoresistive element121. It is thus necessary to make the current direction of a write circuit in the first magnetoresistive element111and that of the write circuit in the second magnetoresistive element121opposite to each other. In the third embodiment, therefore, the first and second switches71and72are provided to perform the following operations.

In the third embodiment, the switch71is closed and the switch72is open during the first and second write periods. That is, the first transistor (NMOS transistor)51functions as a current-voltage conversion transistor (I-V conversion transistor) with a diode connection, and the second transistor52(NMOS transistor) functions as a clamp transistor. Thus, an operation similar to that of the first embodiment described above is performed during the first and second write periods. As a result, data is written to the magnetoresistive element in the selected memory cell MC. Specifically, data is written to the first magnetoresistive element111in the first memory cell MC1.

In the third embodiment, the switch71is open and the switch72is closed during a third write period and a fourth write period after the third write period. Therefore, unlike during the first and second write periods, the second transistor52functions as a current-voltage conversion transistor with a diode connection, and the first transistor51functions as a clamp transistor.

Below is a specific description of an operation to be performed during the third and fourth write periods.

During the third write period, a current common to the current supplied from the constant current source61to the second transistor52flows through the second magnetoresistive element121and second selector122in a selected memory cell MC2. More specifically, the current supplied from the constant current source61to the second transistor52is supplied to the second magnetoresistive element121in the selected second memory cell MC2through the transistor63, global bit line GBL, BL selection circuit30and bit line BL. The current supplied to the second magnetoresistive element121flows to the ground through the word line WL, LWL selection circuit20, global word line GWL, GWL selection circuit40and transistor65. As a result, data is written to the second magnetoresistive element121in the second memory cell MC2. In addition, the voltage applied to the gate of the second transistor52is held in the voltage holding section53.

The basic write principle in the third write period is similar to that in the first write period described in the first embodiment. That is, write is performed in advance such that the second magnetoresistive element121is brought into a low-resistance state before the third write period. During the third write period, the direction of current flowing through the second transistor52and the second magnetoresistive element121coincides with that of current flowing through the second magnetoresistive element121when the second magnetoresistive element121is set in a low-resistance state. Also, during the third write period, the magnitude of current flowing through the second transistor52and the second magnetoresistive element121corresponds to that of current which should flow through the second magnetoresistive element121when the second magnetoresistive element121is set in a high-resistance state. During the third write period, therefore, the second magnetoresistive element121is maintained in a low-resistance state.

During the fourth write period, the voltage held in the voltage holding section53is applied to the gate of the first transistor51. Accordingly, a current common to the current supplied from the constant current source61to the first transistor51flows through the second magnetoresistive element121and second selector122in the selected second memory cell MC2. More specifically, the current supplied from the constant current source61to the first transistor51is supplied to the second magnetoresistive element121in the selected second memory cell MC2through the GWL selection circuit40, global word line GWL, LWL selection circuit20and word line WL. The current supplied to the second magnetoresistive element121flows to the ground through the bit line BL, BL selection circuit30, global bit line GBL and transistor64. As a result, data is written to the second magnetoresistive element121in the selected second memory cell MC2.

The basic write principle in the fourth write period is similar to that in the second write period described in the first embodiment. That is, in the initial stage of the fourth write period, the second magnetoresistive element121is maintained in a low-resistance state, and the magnitude of current flowing through the first transistor51and the second magnetoresistive element121is equal to that of current flowing through the second transistor52and the second magnetoresistive element121during the third write period. However, the direction of current flowing through the second transistor52and the second magnetoresistive element121during the third write period is opposite to that of current flowing through the first transistor51and the second magnetoresistive element121during the fourth write period. During the fourth write period, therefore, the second magnetoresistive element121shifts from the low-resistance state to the high-resistance state.

During the fourth write period, the source voltage clamped by the first transistor51is applied to the second memory cell MC2in the same manner as described in the first embodiment, and the voltage applied to the second magnetoresistive element121is maintained at a constant value without increasing even after the second magnetoresistive element121shifts from the low-resistance state to the high-resistance state.

As described above, the basic configuration and basic operation of the third embodiment are similar to those of the first embodiment, and advantageous effects similar to those of the first embodiment can be obtained from the third embodiment.

Furthermore, in the third embodiment, the first and second switches71and72make it possible to cause the first and second transistors51and52to have different functions. Two memory cells MC are therefore connected to a common word line WL and, in other words, even when two magnetoresistive elements (resistance change memory elements)111and121are connected to a common word line WL, appropriate write can be performed.

In the first, second and third embodiments, a magnetoresistive element in which different resistance states (low-resistance and high-resistance states) are set according to a direction in which a write current flows is used as a resistance change memory element, but a resistance change memory element in which different resistance states (low-resistance and high-resistance states) are set in the same write direction can also be used. For example, a phase change memory (PCM) element can be used as a resistance change memory element.