Method of storing data in non-volatile memory having multiple planes, non-volatile memory controller therefor, and memory system including the same

A method of controlling a non-volatile memory device having multiple planes including receiving write requests from a host, the write requests each including a logical address, a write command, and a data set; storing the data sets at an address of a buffer; storing the buffer address in a mapping table that maps addresses of the buffer to the multiple planes; sequentially transmitting the data sets stored at respective buffer addresses to page buffers, respectively, of the planes corresponding to the buffer addresses according to the mapping table; and programming in parallel at least two data sets stored in respective page buffers to memory cells of the non-volatile memory device.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims priority under 35 U.S.C. §119(a) from Korean Patent Application No. 10-2011-0143370 filed on Dec. 27, 2011, the disclosure of which is hereby incorporated by reference in its entirety.

BACKGROUND

Embodiments of the inventive concepts relate to a semiconductor memory device, and more particularly, to a memory controller for controlling a non-volatile memory device, a memory system including the same, and a program control method thereof.

Memory devices are classified into volatile memory devices and non-volatile memory devices. Volatile memory devices include dynamic random access memory (DRAM) and static random access memory (SRAM). Non-volatile memory devices include flash memory, electrically erasable programmable read-only memory (EEPROM), and resistive memory.

A non-volatile memory device, for example, a flash memory device, is designed in a multi-plane type in order to increase a storage capacity. A multi-plane type non-volatile memory device includes a plurality of planes, each of which includes a plurality of memory blocks.

A host may request a non-volatile memory device to perform a read operation, a program operation, and an erase operation. When the program operation is requested, logical addresses corresponding to data to be programmed may be sequential in some occasions but may not be sequential in other occasions. For instance, when data at independent areas in the host are requested to be programmed, logical addresses may not be sequential.

When logical addresses of data are sequential, programming time can be shortened by using a multi-plane operation allowing the simultaneous programming of pages respectively corresponding to the sequential logical addresses, one in each plane.

However, when the multi-plane operation is used for data whose logical addresses are not sequential, it is relatively hard to shorten the programming time. Further, an amount of data the memory controller has to write in relation to the amount of data that the host has to write known as a write amplification factor (WAF) increases.

SUMMARY

According to some embodiments of the inventive concepts, there is provided a method of controlling a non-volatile memory device including multiple planes. The method includes receiving a write request from a host, the write request including a data set; storing the data set at an buffer address; storing the buffer address in a mapping table, the mapping table configured to map the buffer addresses to the multiple planes, and the buffer address corresponding to where the data set is stored; sequentially transmitting data sets stored at respective buffer addresses to page buffers of the planes corresponding to the buffer addresses according to the mapping table; and programming in parallel at least two data sets stored in respective page buffers to memory cells of the non-volatile memory device.

The data sets programmed in parallel may not have sequential logical addresses.

The number of the multiple planes may be at least two.

The write request may be a random write request.

According to other embodiments of the inventive concepts, there is provided a method of controlling a non-volatile memory device including multiple planes. The method includes the operations of storing, in a buffer, a data of as many valid pages as a number of the multiple planes from the non-volatile memory device; storing a buffer address in a mapping table, the buffer address corresponding to where the data of each valid page is stored, the mapping table configured to map the buffer address to each of the planes; and performing a multi-plane program operation on the data of the valid page stored at each buffer address according to the mapping table.

The performing the multi-plane program operation may include sequentially transmitting the data of the valid pages from the buffer to page buffers, respectively, of the respective planes; and simultaneously programming the data in the page buffers based on a physical address assocated with the data.

According to further embodiments of the inventive concepts, there is provided a memory system including a buffer memory; a non-volatile memory device including multiple planes; and a memory controller configured to receive a plurality of write requests, each write request including a logical address, a write command, and a data set from a host, store the data sets in the buffer memory in response to the write request, the data sets having logical addresses that are not sequential and perform a multi-plane program operation to program the data sets stored in the buffer memory to the non-volatile memory device when the number of the data set stored in the buffer memory is at least a desired (or, alternatively a predetermined) number of multiple planes.

The data sets subjected to the multi-plane program operation may not be sequential.

The memory controller may include a mapping table including buffer address information corresponding to each of the multiple planes.

According to further embodiments of the inventive concepts, there is provided a memory controller configured to control a non-volatile memory device. The memory controller includes a buffer memory configured to store data sets received from a host; and a central processing unit (CPU) configured to control the non-volatile memory device to perform a multi-plane program operation to program the data sets stored in the buffer memory in the non-volatile memory device, in response to a write request, the write request including a logical address and a data set from the host.

Here, the data sets subjected to the multi-plane program operation have logical addresses that are not sequential.

According to another example embodiments, there is provided a method of controlling a non-volatile memory device via a memory controller. The non-volatile memory device having multiple planes, each plane including a page buffer. The memory controller including a buffer memory configured to store a plurality of data sets having non-sequential logical addresses. The method including receiving, at the memory controller, a plurality of write requests, each write request including a logical address and a data set of the plurality of data sets; storing each of the data sets at an address of the buffer memory; sequentially transmitting a number of data sets of the plurality of data sets less than or equal to a number of the planes, from the address of the buffer memory to the page buffer of a plane according to a mapping table, the mapping table mapping the addresses of the buffer memory to the planes; and programming, in parallel, the plurality of data sets from the page buffer to memory cells of the non-volatile memory device according to a physical address corresponding to the logical address associated with the data set.

DETAILED DESCRIPTION OF THE EMBODIMENTS

FIG. 1is a block diagram of a host10and a memory system20according to some embodiments of the inventive concepts.FIG. 2is a detailed block diagram of a memory controller100illustrated inFIG. 1.

Referring toFIG. 1, the memory system20connected to the host10includes a memory controller100and at least one non-volatile memory device200. The memory system20may be any system that includes non-volatile memory.

The memory controller100generates an address and a command (e.g., a program command, a read command, or an erase command) to control the operation (e.g., a program operation, a read operation, or an erase operation) of the non-volatile memory device200(e.g., a flash memory device). The program and read operations may be performed in units of pages. The erase operation may be performed in units of blocks.

The memory controller100outputs the command CMD for controlling the operation of the non-volatile memory device200to the non-volatile memory device200.

The non-volatile memory device200performs an operation in response to the command CMD and sends a result of the operation to the memory controller100. The non-volatile memory device200is connected with the memory controller100through an input/output (I/O) pin through which a command CMD, data DATA, an address signal ADD, a status signal and so on may be transceived. Hereinafter, the description of the embodiments of the present invention will be made mainly regarding the program operation.

The memory controller100and the non-volatile memory device200may be packaged in separate packages, respectively, or in a single package.

Referring toFIG. 2, the memory controller100may include a buffer memory110, a mapping table120, a central processing unit (CPU)140, a host interface150, a timer160, and a non-volatile memory interface170.

The buffer memory110may be used as an operation memory of the CPU140. The buffer memory110may also store data that the host10requests the non-volatile memory device200to program. The buffer memory110may be implemented by DRAM or SRAM.

The mapping table120stores buffer address information of the buffer memory110mapped to a plane of the non-volatile memory device200. For instance, when the non-volatile memory device200has a four-plane architecture, as shown inFIG. 11the mapping table120may store a buffer address BufAdd#A corresponding to a first plane Plane0, a buffer address BufAdd#C corresponding to a second plane Plane1, a buffer address BufAdd#B corresponding to a third plane Plane2, and a buffer address BufAdd#D corresponding to a fourth plane Plane3.

The mapping information may be updated every time when data received from the host10is stored in the buffer memory110. The mapping table120is separately illustrated in the drawings, but it may be implemented in the DRAM or SRAM. That is, the mapping table120may be implemented in the buffer memory110.

The CPU140may control data transmission through a bus180among the buffer memory110, the host interface150, the timer160, and the non-volatile memory interface170. The CPU140may also drive a flash translation layer (FTL).

The FTL may keep the mapping information between a logical address in a virtual block device (e.g., a host) and a physical address in a non-volatile memory device, and when a program or read operation is requested with respect to a particular logical address, it may translate the logical address into a physical address using the mapping information. Especially, when a program operation that changes data at a particular logical address is requested, the FTL may electrically erase a physical address corresponding to the logical address and then rewrite the physical address or remap the logical address to a different physical address.

The host interface150may interface the host10and the memory controller100for data transmission according to a protocol of the host10connected to the memory system20.

The timer160provides the CPU140time information necessary for the operation of the memory controller100. The non-volatile memory interface170may interface the non-volatile memory device200and the memory controller100for data transmission.

The memory controller100may also include an error correction code (ECC) block (not shown). The ECC block may detect and correct errors in data read from the non-volatile memory device200.

FIG. 3is a block diagram of the host10and the memory system20according to other embodiments of the inventive concepts. Referring toFIG. 3, a buffer memory110′ may be implemented to be separated from the memory controller100. Only one non-volatile memory device200is illustrated inFIG. 1, but a plurality of non-volatile memory devices200may be connected to the memory controller100in the embodiments illustrated inFIG. 3.

FIG. 4is a block diagram of the structure of the memory system20illustrated inFIG. 1according to some embodiments of the inventive concepts. Referring toFIG. 4, the non-volatile memory device200may include a plurality of memory elements200-1.FIG. 4shows the embodiments in which the non-volatile memory device200has a 4-channel 8-bank structure, but the inventive concepts are not restricted to the current embodiments.

In the memory system20illustrated inFIG. 4, the memory controller100and the non-volatile memory device200are connected through four channels A, B, C, and D. Eight flash memory elements CA0through CA7, CB0through CB7, CC0through CC7, or CD0through CD7are connected to a corresponding one of the channels A, B, C, and D. However, it is apparent that the numbers of channels and banks may be changed. Here, a bank is a group of memory elements positioned at the same offset in different channels.

Each of the flash memory elements200-1has 2-plane architecture in the embodiments illustrated inFIG. 4, but the inventive concepts are not restricted to the current embodiments. The number of planes may be changed.

FIG. 5is a detailed block diagram of the non-volatile memory device200illustrated inFIG. 1. When the non-volatile memory device200includes a plurality of memory elements200-1as shown inFIG. 4, each of the plurality of memory elements200-1may be implemented as shown inFIG. 5.

FIG. 6Ais a diagram of a memory cell array210illustrated inFIG. 5according to some embodiments of the inventive concepts.FIG. 6Bis a diagram of the memory cell array210illustrated inFIG. 5according to other embodiments of the inventive concepts.

Referring toFIG. 5, the non-volatile memory device200includes a memory cell array210and an access circuit212.

The memory cell array210includes NAND memory cell strings respectively connected to bit lines. Each of the NAND memory cell strings includes a plurality of non-volatile memory cells connected in series to one another. Each NAND memory cell string may be laid out (or embodied) on one plane (or layer) in two dimensions as illustrated inFIG. 6A. Alternatively, the memory cell array210may be implemented in three dimensions, as illustrated inFIG. 6B, using a wafer stack, a chip stack, or a cell stack.

Referring toFIGS. 6A and 6B, the NAND memory cell string includes the non-volatile memory cells connected in series between a string selection transistor ST1connected to one of the bit lines and a ground selection transistor ST2connected to a common source line (CSL).

A gate of the string selection transistor ST1is connected to a string selection line (SSL). Gates of the respective non-volatile memory cells are connected to a plurality of word lines WL1through WLn, respectively. A gate of the ground selection transistor ST2is connected to a ground selection line (GSL). Each NAND memory cell string is connected to one of page buffers221-11through211-1mor221-1through221-m. The number of word lines WL1through WLn may vary with different embodiments.

The non-volatile memory cells included in the NAND memory cell strings may be implemented using flash electrically erasable programmable read-only memory (EEPROM) which can store one or more bits.

Accordingly, each of the non-volatile memory cells may be embodied by a NAND flash memory cell storing at least one bit, e.g., a single level cell (SLC) or a multi-level cell (MLC).

The access circuit212accesses the memory cell array210to perform a data access operation, e.g., a program operation, a read operation, or an erase operation, according to a command (or command sets) and an address received from an outside, e.g., the memory controller100. The access circuit212includes a voltage generator240, a row decoder250, a control logic260, a column decoder270, a page buffer and sense amplifier (S/A) block220, a Y-gating circuit230, and an I/O block280.

The voltage generator240may generate a voltage necessary for a data access operation in response to a control signal generated by the control logic260. The voltage generator240generates a program voltage and a program-verify voltage necessary to perform the program operation, generates a plurality of read voltages necessary to perform the read operation, generates an erase voltage and an erase-verify voltage necessary to perform the erase operation, and output the voltages necessary for each of the operations to the row decoder250.

The control logic260controls the overall operation of the access circuit212in response to the command CMD output from the memory controller100. The control logic260may control memory read state information to be sensed during a memory read operation and data that has been read to be output to the memory controller100.

Under the control of the control logic260, the column decoder270decodes a column address YADD and outputs a plurality of select signals to the Y-gating circuit230.

The page buffer and S/A block220includes a plurality of page buffers PB. The page buffers PB are respectively connected with a plurality of bit lines.

Each of the page buffers PB may operate as drivers that temporarily store data read from the memory cell array210in the read operation according to the control of the control logic260. Each page buffer PB may also operate as an S/A which senses and amplifies a voltage of each bit line during the read operation according to the control of the control logic260.

The Y-gating circuit230may control transmission of data between the page buffer and S/A block220and the I/O block280in response to the select signals received from the column decoder270.

The I/O block280may transmit data from an outside to the Y-gating circuit230or transmit data from the Y-gating circuit230to the memory controller100through a plurality of I/O pins (or a data bus).

FIG. 7Ais a block diagram showing the memory cell array210illustrated inFIG. 5in multi-plane units according to some embodiments of the inventive concepts.FIG. 7Bis a block diagram showing the memory cell array210illustrated inFIG. 5in multi-plane units according to other embodiments of the inventive concepts.

Referring toFIG. 7A, the memory cell array210includes multiple planes. Here, the multiple planes refer to at least two planes. The memory cell array210may be divided into a plurality of memory blocks210-31, i.e., BLOCK0through BLOCKk (where “k” is a natural number greater than 0). In the embodiments illustrated in FIG.7A, the non-volatile memory blocks210-31are uniformly distributed to four memory planes210-1,210-2,210-3, and210-4. Each of the memory blocks210-31includes a plurality of pages210-21.

Page buffers220-1through220-4are respectively provided for the planes210-1through210-4, so that one memory block220-31or one page220-21is selected from each of the planes210-1through210-4and a maximum of “n” memory blocks220-31or pages220-21are subjected to the erase operation or the program/read operation. The “n” memory blocks220-31respectively have unique memory block numbers 0, 1, 2, . . . , n−1, so that the memory blocks210-31can be individually selected and erased electrically. Each page210-21can be individually selected by an address and programmed or read.

The size of memory blocks and pages may vary with NAND flash products. For instance, when a flash memory has a total capacity of 16 Mbytes, a memory block size of 16 Kbytes, and a page size of 512 bytes, it is comprised of 1024 memory blocks, each of which is comprised of 32 pages.

A non-volatile memory device includes 4096 memory blocks distributed to four planes and each memory block includes 32 pages in the current embodiments, but the inventive concepts are not restricted to the current embodiments. A non-volatile memory device having a different multi-plane architecture as shown inFIG. 7Bmay be used.

Referring toFIGS. 7A and 7B, the plane210-1includes at least one memory array and a page buffer220-1positioned at an end of the memory array. The page buffer220-1stores data of a single page210-21. Each memory array has the basic structure of a non-volatile memory, a shown inFIG. 6Aor6B.

The row decoder250may be provided for each of the planes210-1through210-4.

FIG. 8is a diagram for explaining a procedure for programming data from the memory controller100to the non-volatile memory device200according to some embodiments of the inventive concepts.FIG. 9is a block diagram showing the data, which is programmed to the non-volatile memory device200illustrated inFIG. 8, in units of planes and pages.

The host10sends data of a plurality of pages210-21and a write request to the memory system20. The data may have sequential logical addresses like moving image data, but it is assumed in the embodiments that the data have unsequential or random logical addresses. In other words, the write request may be a random write request. Here, when logical addresses are unsequential or random, a series of at least two logical addresses does not have continuity. Even a series of logical addresses that have a single discontinuity thereamong is considered random.

For instance, as shown inFIG. 8, when the host10requests the memory system20to write data having logical addresses of respective independent regions LPN100, LPN110, LPN150, and LPN356, the memory system20receive the data from the host10in unsequential order. In other words, when the data is programmed to the non-volatile memory device200, the logical addresses of the data are not sequential.

The memory system20programs the data having unsequential logical addresses to the non-volatile memory device200using a multi-plane program method.

For instance, the data of LPN100, the data of LPN110, the data of LPN150, and the data of LPN356 may be programmed in parallel to Page A in a block “i” of Plane0, Page C in a block “k” of Plane2, Page B in a block “j” of Plane1, and Page D in a block “l” of Plane3, respectively, using the multi-plane program method.

It is illustrated that the memory blocks and pages in which the data are programmed are in a row inFIG. 8, but the inventive concepts are not restricted to the current embodiments. They may be in different positions in different planes.

When the host10sends the data having the unsequential logical addresses to the memory system20, the memory controller100receives the data and transmits the data to the non-volatile memory device200. At this time, the memory controller100finds a physical address corresponding to each logical address using the FTL and transmits data corresponding to the logical address to the physical address in the non-volatile memory device200.

In detail, when the memory controller100receives the data of LPN100, LPN110, LPN150, and LPN356, which have unsequential logical addresses, it stores the data in the buffer memory110temporarily. Thereafter, the memory controller100updates a buffer address of a corresponding plane in the mapping table120. In the current embodiments, it is assumed that the data received from the host10are sequentially stored in Plane0through Plane3, respectively, according to the FTL. In this case, the data of the LPN100, LPN150, LPN110, and LPN356 correspond to Plane0, Plane1, Plane2, and Plane3, respectively. Accordingly, when the data of LPN100 is stored in the buffer memory110, a buffer address of the buffer memory110, in which the data of LPN100 is stored, is stored corresponding to Plane0in the mapping table120. When the data of LPN150 is stored in the buffer memory110, a buffer address of the buffer memory110, in which the data of LPN150 is stored, is stored corresponding to Plane1in the mapping table120. In the same manner, buffer addresses for the data of LPN110 and LPN356 are stored in the mapping table120.

The logical addresses of the data are translated into physical addresses, respectively, according to the FTL. Although not shown, an address translation mapping table may be provided to convert a logical address into a physical address.

When the buffer memory110is filled with as many data as the number of multiple planes, the memory controller100sends a program request and the data to the non-volatile memory device200. The non-volatile memory device200receives the data sequentially. The non-volatile memory device200temporarily stores data for a plane corresponding to a physical address in the page buffer and S/A block220. When data for all planes (e.g., four planes in 4-plane architecture) are stored in the page buffer and S/A block220, the non-volatile memory device200respectively programs the data to pages in respective memory blocks in the respective planes at a time.

For instance, when the data of LPN100, LPN150, LPN110, and LPN356 are stored in respective page buffers in the non-volatile memory device200, the data are simultaneously programmed to the respective physical addresses. In the same manner, data of LPN548, LPN240, LPN876, and LPN187 and data of LPN858, LPN557, LPN630, and LPN241 are programmed.

FIG. 10Ais a block diagram of the structure of a memory system20′ according to other embodiments of the inventive concepts.FIG. 10Bis a schematic timing chart showing the program operation of the memory system20′ illustrated inFIG. 10A.FIG. 10Ashows a non-volatile memory device200′ that has a 1-channel 8-bank structure. Each of memory elements CA0through CA7has 4-plane architecture, as shown inFIGS. 8 and 9.

Referring toFIGS. 10A and 10B, when the memory system20′ receives a program request from the host10, a memory controller100′ may perform a program operation on first through eighth banks #0through #7sequentially.

For instance, the memory controller100′ may sequentially receive the data respectively corresponding to the logical addresses LPN100, LPN150, LPN110, and LPN356 from the host10and store the data in the buffer memory110. At this time, each datum may be stored with a physical address corresponding to its logical address according to the FTL.

A buffer address of each datum stored in the buffer memory110is also stored in the mapping table120. For instance, a buffer address of the datum having the logical address LPN100 may be stored corresponding to the first plane Plane0in the mapping table120, a buffer address of the datum having the logical address LPN150 may be stored corresponding to the second plane Plane1in the mapping table120, a buffer address of the datum having the logical address LPN110 may be stored corresponding to the third plane Plane2in the mapping table120, and a buffer address of the datum having the logical address LPN356 may be stored corresponding to the fourth plane Plane3in the mapping table120.

Accordingly, even when the data have the random logical addresses like LPN100, LPN150, LPN110, and LPN356, the data stored in the buffer memory110can be transmitted corresponding to planes, respectively, based on information stored in the mapping table120.

The data having the logical addresses LPN100, LPN150, LPN110, and LPN356 are transmitted from the buffer memory110to the first bank #0through a channel A. The non-volatile memory device CA0of the first bank #0sequentially receives the data having the logical addresses LPN100, LPN150, LPN110, and LPN356 and stores them in the page buffer and S/A block220till data for all respective planes are received in a period tDMA and then simultaneously stores the data to pages respectively having physical addresses corresponding to the respective logical addresses LPN100, LPN150, LPN110, and LPN356 in a period tPROG.

During the program operation, the channel A between the memory controller100′ and the non-volatile memory device200′ is empty, and therefore, data can be transmitted to the other banks #1through #7.

Accordingly, during the program operation tPROG of the first bank #0, the memory controller100′ may transmit a next set of data having logical addresses LPN548, LPN240, LPN876, and LPN187 to the second bank #1through the channel A.

The non-volatile memory device CA1of the second bank #1sequentially receives the data having the logical addresses LPN548, LPN240, LPN876, and LPN187 and stores them in the page buffer and S/A block220till data for all respective planes are received in the period tDMA and then simultaneously stores the data to pages respectively having physical addresses corresponding to the respective logical addresses LPN548, LPN240, LPN876, and LPN187 in the period tPROG.

Data having random logical addresses (e.g., LPN858, LPN557, LPN630, and LPN241) are programmed to the other banks #2through #7in the same manner as described above.

Thereafter, when the program operation of the first bank #0is completed, the first bank #0sequentially receives subsequent data having logical addresses LPN872, LPN178, LPN544, and LPN895 for four respective planes and stores the data in the I/O block280. When all of the data for the four respective planes are received in the period tDMA, the first bank #0simultaneously programs the data to physical addresses corresponding to the data in the period tPROG.

As described above, while a program operation is being performed on one bank (e.g., the first bank #0) in the period tPROG, data can be transmitted to another bank (e.g., the second bank #1) through a channel to which the two banks are connected.

Accordingly, a channel idle time, i.e., tPROG-tDMA occurring due to a long programming time tPROG during a program operation on multiple planes is reduced, and a channel is used efficiently. As a result, the program operation performance of the memory system20′ is increased.

FIG. 11is a detailed block diagram of the program operation illustrated inFIG. 8. Referring toFIG. 11, the memory controller100receives a program request and data to be programmed to the non-volatile memory device200from the host10and temporarily stores the data in the buffer memory110. At this time, the data may be sequentially or randomly stored in the buffer memory110, and the logical addresses of the data stored in the buffer memory110may not be sequential.

The memory controller100may convert the logical address of each datum stored in the buffer memory110into a physical address, i.e., a combination of a memory block address and a page address, using an FTL. The memory controller100acquires buffer address information of the buffer memory110with respect to each plane using the mapping table120. Mapping information between a buffer address and a plane may be updated in the mapping table120every time when a datum is stored in the buffer memory110.

In some embodiments, each datum that has acquired the buffer address is sequentially transmitted to a page buffer (not shown) of a plane corresponding to the buffer address and is temporarily stored in the page buffer until data for all of the planes, respectively, are stored in corresponding page buffers, respectively. When data for all four planes are stored in the respective page buffers, the non-volatile memory device200simultaneously stores the data in memory cells corresponding to the memory block addresses and the page addresses.

In other embodiments, the memory controller100may perform a multi-plane operation even when the memory system20operates using write-through. The write-through is an operation of storing data immediately, so that data is stored in the non-volatile memory device200even when as many data as the number of planes are not stored in the buffer memory110.

The memory controller100may count a duration, i.e., “current time—start time” using the timer160while storing data received from the host10in the buffer memory110in order to prepare for the write-through.

When the duration exceeds a desired (or, alternatively a predetermined) time limit, even if the number of data stored in the buffer memory110is less than the number of multiple planes, the memory controller100transmits the data to the non-volatile memory device200. When each datum has been received in a corresponding plane, the non-volatile memory device200simultaneously program the data to memory cells corresponding to the memory block addresses and the page addresses.

The memory controller100and the non-volatile memory device200repeat the program operation in such a multi-plane architecture as described above according to the request of the host10.

As described above, the mapping table120manages a buffer address corresponding to each plane. Accordingly, data in the buffer memory110can be independently transmitted to page buffers of the respective planes. As a result, the data having logical addresses that are not sequential is programmed to multi-plane memory using a multi-plane operation, so that a channel between the memory controller100and the non-volatile memory device200is used efficiently. In addition, since a unit capacity of data programmed at a time is increased, the performance of the memory system20is increased without increasing a write amplification factor (WAF).

Moreover, the increase of the performance of the memory system20can be promoted during garbage collection as well as a program operation performed at the random write request of the host10. The garbage collection is a process of managing invalid pages and valid pages in order to optimize the use of the non-volatile memory device200. The garbage collection process will be described in detail with reference toFIG. 14later.

For clarity of the description, a multi-plane program operation in 4-plane architecture will be described, but the inventive concepts are not restricted thereto and can be realized in a memory system having different multi-plane architectures.

FIG. 12is a flowchart of a memory control method according to some embodiments of the inventive concepts. Referring toFIG. 12, the memory controller100receives a write request and data to be programmed to the non-volatile memory device200from the host10in operation S110. The write request may include an identifier that identifies a request as the write request, a logical address, and a count. The count indicates the amount of data (e.g., the number of pages or sectors).

The memory controller100stores the data in the buffer memory110in operation S120. The data may be a data set including at least one bit and may be a write unit, i.e., a page unit.

Next, a buffer address corresponding to a current plane is updated in the mapping table120in operation S125. In the non-volatile memory device200having the 4-plane architecture, data input to the buffer memory110may be sequentially mapped to the first to fourth planes Plane0to Plane3in the non-volatile memory device200. For instance, according to the strategy of the memory controller100, a data set received first may be mapped to Plane0, the next data set may be mapped to Plane1, and the next data set may be mapped to Plane2.

In this manner, the memory controller100receives the data to be programmed from the host10together with the write request until the buffer memory110is filled with as many data as the number of multiple planes in operation S130.

When as many data as the number of multiple planes are stored in the buffer memory110, the data in the buffer memory110are sequentially transmitted to the page buffer and S/A block220of the non-volatile memory device200with reference to the mapping table120in operations S140and S160. For instance, a data set stored at a buffer address of Plane0is transmitted to and stored in a page buffer of Plane0with reference to the mapping table120using direct memory access (DMA) in operation S140, and it is checked whether the number of data transmitted to the page buffer and S/A block220is the same as the number of planes in operation S160. When the number of data transmitted to the page buffer and S/A block220is not the same as (i.e., is less than) the number of planes, a data set stored at a buffer address of Plane1is transmitted to and stored in a page buffer of Plane1with reference to the mapping table120using DMA in operation S140.

When the page buffers of all respective planes receive data, respectively, in operation S160, the non-volatile memory device200programs in parallel the data stored in the respective page buffers to memory cells having physical addresses, which have been obtained through the FTL, in operation S170.

When the non-volatile memory device200has the 4-plane architecture, a 4-plane program operation in which pages are respectively programmed to four planes at a time is performed in operation S170.

FIG. 13Ais a flowchart of a memory control method according to other embodiments of the inventive concepts. Referring toFIG. 13A, the memory controller100receives a write request and data to be programmed to the non-volatile memory device200from the host10in operation S210. At this time, the logical addresses of the data may not be sequential.

The memory controller100stores the data in the buffer memory110in operation S230. The data may be a data set including at least one bit and may be a write unit, i.e., a page unit.

When a data set stored in the buffer memory110corresponds to Plane0, i.e., a start plane in a multi-plane program operation, the memory controller100may set a start time in operation S232. For instance, the memory controller100may activate the timer160or set the time of the timer160as a start time in response to the data set corresponding to Plane0.

The memory controller100may perform a multi-plane operation even when the memory system20operates using write-through. The write-through is an operation of storing data immediately, so that unlike in the embodiments illustrated inFIG. 12, data is stored in the non-volatile memory device200even when as many data as the number of planes are not stored in the buffer memory110.

The memory controller100may count “current time—start time” while storing data received from the host10in the buffer memory110in order to prepare for the write-through.

When the “current time—start time” exceeds a desired (or, alternatively a predetermined) time limit in operation S240, even if the number of data stored in the buffer memory110is less than the number of multiple planes, the memory controller100transmits the data to the non-volatile memory device200in operations S260and S270. When the number of data stored in the buffer memory110is the same as the number of planes within the desired (or, alternatively the predetermined) time limit in operation S250, like in the embodiments illustrated inFIG. 12as many data as the number of planes are sequentially transmitted to the non-volatile memory device200in operations S260and S270.

When the number of data stored in the page buffer and S/A block220of the non-volatile memory device200is the same as the number of data stored in the buffer memory110in operation S270, the non-volatile memory device200programs in parallel the data stored in the page buffer and S/A block220to memory cells having physical addresses, which have been obtained through the FTL, in operation S280.

A 4-plane program operation in which pages are respectively programmed to four planes at a time may be performed in operation S280.

For instance, when data for only three planes are received in the time limit, the 4-plane program operation is still performed. In this case, Plane0through Plane2may be programmed with valid data received from the host10and Plane3may be programmed with invalid data that has already been stored in a page buffer of Plane3.

FIG. 13Bis a memory control method according to further embodiments of the inventive concepts. Since the embodiments illustrated inFIG. 13Bis similar to those illustrated inFIG. 13A, differences therebetween will be mainly described.

Referring toFIG. 13B, when the “current time—start time” exceeds the desired (or, alternatively the predetermined) time limit, that is, NO in operation S240or when the number of data stored in the buffer memory110is the same as the number of multiple planes, that is, YES in operation S250, the data stored in the buffer memory110are transmitted to the page buffer and S/A block220of the non-volatile memory device200.

In the embodiments of the inventive concepts, the number of planes that the non-volatile memory device200can program data to at a time may be limited. For instance, it is assumed that the non-volatile memory device200performs a 1-plane program operation, a 2-plane program operation, and a 4-plane program operation but does not perform a 3-plane program operation.

In this case, the memory controller100calculates the maximum number of available planes from the number of data stored in the buffer memory110in operation S310. For instance, when the number of data stored in the buffer memory110is 3, the maximum number of available planes is 2. The maximum number of available planes is a maximum value among values (e.g., 1 and 2) less than the number (e.g., 3) of data stored in the buffer memory110among the numbers (e.g., 1, 2, and 4) of planes that the non-volatile memory device200can perform a program operation on simultaneously.

Next, the memory controller100sequentially transmits as many data as the maximum number of available planes from the buffer memory110to pages buffers, respectively, of the non-volatile memory device200in operations S320and S330.

Next, a multi-plane program operation is performed on planes as many as the maximum number of available planes in operation S340. For instance, two planes are subjected to a program operation at a time.

Next, the memory controller100transmits a data set remaining in the buffer memory110to a corresponding page buffer in the non-volatile memory device200in operations S350and S360and programs all remaining data in operation S370.

FIG. 14is a flowchart of a memory control method during garbage collection according to some embodiments of the inventive concepts. Since the memory control method during garbage collection is similar to the memory control method illustrated inFIG. 12, differences therebetween will be mainly described to avoid redundancy.

The memory controller100reads data of a valid page from memory in operation S410. The memory controller100stores the data of the valid page in the buffer memory110in operation S420and updates a buffer address corresponding to each plane in the mapping table120in operation S425. When data of as many valid pages as the number of multiple planes are stored in the buffer memory110, the memory controller100acquires physical address information corresponding to each valid page from the FTL and the mapping table120and sequentially transmits the data of the valid pages to the non-volatile memory device200in operation S440.

When the data of valid pages as many as the number of multiple planes are stored in the page buffer and S/A block220in operation S460, the non-volatile memory device200programs the data of the valid pages to the memory cell array210at a time in operation S470.

FIG. 15is a block diagram of a data processing system including the memory system illustrated inFIG. 1according to some embodiments of the inventive concepts.

Referring toFIG. 15, the data processing system500may be implemented as a cellular phone, a smart phone, a tablet personal computer (PC), a personal digital assistant (PDA) or a radio communication system.

The data processing system500includes the memory device200and a memory controller100controlling the operations of the memory device200. The memory controller100may control the data access operations, e.g., a program operation, an erase operation, and a read operation, of the memory device200according to the control of a processor510.

The page data programmed in the memory device200may be displayed through a display520according to the control of the processor510and/or the memory controller150.

A radio transceiver530transmits or receives radio signals through an antenna ANT. The radio transceiver530may convert radio signals received through the antenna ANT into signals that can be processed by the processor510. Accordingly, the processor510may process the signals output from the radio transceiver530and transmit the processed signals to the memory controller100or the display520. The memory controller100may program the signals processed by the processor510to the memory device200. The radio transceiver530may also convert signals output from the processor510into radio signals and outputs the radio signals to an external device through the antenna ANT.

An input device540enables control signals for controlling the operation of the processor510or data to be processed by the processor510to be input to the data processing system500. The input device540may be implemented by a pointing device such as a touch pad or a computer mouse, a keypad, or a keyboard.

The processor510may control the operation of the display520to display data output from the memory controller100, data output from the radio transceiver130, or data output from the input device540. The memory controller100, which controls the operations of the memory device200, may be implemented as a part of the processor510or as a separate chip.

FIG. 16is a block diagram of a data processing system including the memory system illustrated inFIG. 1according to other embodiments of the inventive concepts.

Referring toFIG. 16, the data processing system600may be implemented as a PC, a tablet PC, a net-book, an e-reader, a PDA, a portable multimedia player (PMP), an MP3 player, or an MP4 player.

The data processing system600includes the memory device200and a controller100, which may control the data processing operations of the memory device200. A processor210may display data stored in the memory device200through a display630according to data input through an input device620. The input device620may be implemented by a pointing device such as a touch pad or a computer mouse, a keypad, or a keyboard.

The processor610may control the overall operation of the data processing system600and the operations of the memory controller100. The memory controller100, which may control the operations of the memory device200, may be implemented as a part of the processor610or as a separate chip.

FIG. 17is a block diagram of a data processing system including the memory system illustrated inFIG. 1according to further embodiments of the inventive concepts;

Referring toFIG. 17, the data processing system700may be implemented as a memory card or a smart card. The data processing system700includes the memory device200, a memory controller100, and a card interface720.

The memory controller100may control data exchange between the memory device200and the card interface720. The card interface720may be a secure digital (SD) card interface or a multi-media card (MMC) interface, but the inventive concepts is not restricted to the current embodiments.

The card interface720may interface a host and the memory controller100for data exchange according to a protocol of the host. The card interface720may support a universal serial bus (USB) protocol and an interchip (IC)-USB protocol. Here, the card interface720may indicate a hardware supporting a protocol used by the host, a software installed in the hardware, or a signal transmission mode.

When the data processing system700is connected with the host such as a PC, a tablet PC, a digital camera, a digital audio player, a cellular phone, a console video game hardware, or a digital set-top box, the host may perform data communication with the memory device200through the card interface720and the memory controller100.

FIG. 18is a block diagram of a data processing system including the memory system illustrated inFIG. 1according to other embodiments of the inventive concepts.

Referring toFIG. 18, the data processing system800may be implemented as an image processor like a digital camera, a cellular phone equipped with a digital camera, a smart phone equipped with a digital camera, or a tablet PC equipped with a digital camera.

The data processing system800includes the memory device200and a memory controller100controlling the data processing operations, such as a program operation, an erase operation, and a read operation, of the memory device200. An image sensor820included in the data processing system800converts optical images into digital signals and outputs the digital signals to a processor810or the memory controller100. The digital signals may be controlled by the processor810to be displayed through a display830or stored in the memory device200through the memory controller100.

Data stored in the memory device200may be displayed through the display830according to the control of the processor810or the memory controller100. The memory controller100, which may control the operations of the memory device200, may be implemented as a part of the processor810or as a separate chip.

FIG. 19is a block diagram of a data processing system including the memory system illustrated inFIG. 1according to still other embodiments of the inventive concepts.

Referring toFIG. 19, the data processing system900may be implemented as a data storage system like a solid state drive (SSD).

The data processing system900includes a plurality of memory devices200, a memory controller100controlling the data processing operations of the memory devices200.

The data processing system900may be implemented as a memory module.

FIG. 20is a block diagram of a data storage apparatus including the data processing system illustrated inFIG. 19.

Referring toFIGS. 19 and 20, the data storage apparatus1000may be implemented as a redundant array of independent disks (RAID) system. The data storage apparatus1000includes a RAID controller1010and a plurality of memory modules1100-1through1100-nwhere “n” is a natural number.

Each of the memory modules1100-1through1100-nmay be the data processing system900illustrated inFIG. 19. The memory modules1100-1through1100-nmay form a RAID array. The data storage apparatus1000may be a PC or an SSD.

During a program operation, the RAID controller1010may transmit program data output from a host to at least one of the memory modules1100-1through1100-naccording to a RAID level in response to a program command received from the host. During a read operation, the RAID controller1010may transmit to the host data read from at least one of the memory modules1100-1through1100-nin response to a read command received from the host.

As described above, according to some embodiments of the inventive concepts, data having unsequential logical addresses are simultaneously programmed in a memory system, so that a channel is used efficiently without the decrease of a WAF. As a result, the performance and the lifespan of the memory system are increased.

While the inventive concepts has been particularly shown and described with reference to exemplary embodiments thereof, it will be understood by those of ordinary skill in the art that various changes in forms and details may be made therein without departing from the spirit and scope of the inventive concepts as defined by the following claims.