Integrated post-amplifier, laser driver, and controller

A telecommunications system and constituent integrated circuit that includes a post-amplifier assembly configured for communication with an optical receiver, a laser driver assembly configured for communication with the optical transmitter, and a controller assembly configured to control the post-amplifier and laser driver. The post-amplifier, the laser driver, and the controller assemblies are embodied on a single integrated circuit, thereby reducing manufacturing costs. Noise due to clock generation may be reduced by having the clock act on a transient basis, turning on when needed during the boot process, and turning off when not needed during normal operation.

BACKGROUND OF THE INVENTION

1. The Field of the Invention

The present invention relates generally to high speed transceivers. More particularly, embodiments of the present invention relate to systems and devices that integrate a post-amplifier, laser driver, and controller on the same integrated circuit, thereby resulting in reduced manufacturing costs as well as improvements in operational efficiency and functionality.

2. Background and Relevant Art

Many high speed data transmission networks rely on optical transceivers and similar devices for facilitating transmission and reception of digital data embodied in the form of optical signals. Typically, data transmission in such networks is implemented by way of an optical transmitter, such as a laser, while data reception is generally implemented by way of an optical receiver, an example of which is a photodiode.

Various other components are also employed by the optical transceiver to aid in the control of the optical transmit and receive components, as well as the processing of various data and other signals. For example, such optical transceivers typically include a driver (e.g., referred to as a “laser driver” when used to drive a laser signal) configured to control the operation of the optical transmitter in response to various control inputs. The optical transceiver also generally includes an amplifier (e.g., often referred to as a “post-amplifier”) configured to perform various operations with respect to certain parameters of a data signal received by the optical receiver. A controller circuit (hereinafter referred to the “controller”) controls the operation of the laser driver and post amplifier.

In conventional optical transceivers, the controller is implemented on a different integrated circuit (“IC”) than the laser driver and post-amplifier. Accordingly, the collection of the controller, laser driver and post-amplifier are implemented as separate chips on a printed circuit board. The controller is electrically connected through the printed circuit board with the laser driver and post-amplifier.

One drawback to such an approach, however, is that the multiple separate ICs take up a relatively large amount of space on the printed circuit board. Furthermore, there is significant expense involved with separately manufacturing each IC. In the highly competitive marketplace for telecommunication equipment, it would be advantageous to more inexpensively manufacture a device that includes the controller, laser driver, and post-amplifier.

BRIEF SUMMARY OF THE INVENTION

The foregoing problems with the prior state of the art are overcome by the principles of the present invention. The principles of the present invention may be implemented in a telecommunications system and includes an integrated circuit that includes a post-amplifier assembly configured for communication with an optical receiver, a laser driver assembly configured for communication with the optical transmitter, and a controller assembly configured to control the post-amplifier and laser driver.

The post-amplifier, the laser driver, and the controller assemblies are embodied on a single integrated circuit, thereby reducing manufacturing costs. Noise due to clock generation may be reduced by having the clock act on a transient basis, turning on when needed during the boot process, and turning off when not needed during normal operation. This noise reduction is important when these various components are integrated onto the same chip in a high speed optical transceiver since the actual data channels are in close proximity to the clock and control circuitry.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

The principles of the present invention relate to a telecommunications system and constituent integrated circuit that includes a post-amplifier assembly configured for communication with an optical receiver, a laser driver assembly configured for communication with the optical transmitter, and a controller assembly configured to control the post-amplifier and laser driver. The post-amplifier, the laser driver, and the controller assemblies are embodied on a single integrated circuit, thereby reducing manufacturing costs. Reference will now be made to the drawings to describe various aspects of example embodiments of the invention. It is to be understood that the drawings are diagrammatic and schematic representations of only such example embodiments, and are not limiting of the present invention.

Turning to the drawings,FIG. 1schematically illustrates a telecommunications system100that includes an optical transceiver integrated circuit110amongst potentially other components101.

The optical transceiver integrated circuit110operates to receive an incoming optical signal and report the signal to the other components101. Specifically, an optical receiver111receives the incoming optical signal and converts the optical signal into a corresponding electrical signal. The electrical signal is then provided to a post-amplifier112for appropriate amplification. The resulting electrical signal may then be used by, for example, a host computing system. The other components101may include the host computing system that uses the incoming signal.

The optical transceiver integrated circuit110also operates to transmit outgoing optical signals in response to instructions from a host computing system. A laser driver114properly interprets these instructions to provide an appropriate electrical signal to an optical transmitter115. The optical transmitter115converts the electrical signal into an optical signal for transmission.

The post-amplifier112and the laser driver114are controlled by a controller113, which configures the post-amplifier112and laser drivers114with appropriate settings. In some cases, the controller113may be sophisticated enough to dynamically adjust the settings for the post-amplifier112and laser driver114given changing operational circumstances.

The controller113may be integrated onto the same integrated circuit as the post-amplifier112and laser driver114. In conventional systems, this would be impracticable since the conventional controllers typically use a consistent clock signal to time its operation. Such a clock signal generates noise, which can leak into the actual signal being received and transmitted. Integrating the controller onto the same chip as the post-amplifier and laser driver would increase this noise due to the elements being brought into closer proximity. However, the present invention reduces the impact of such clock-driven noise by only using the clock during certain clock-sensitive times in the controller operation. This makes it more feasible to integrate the controller113onto the same integrated circuit as the post-amplifier and laser driver114. The optical receiver111and the optical transmitter115may also be integrated on the same integrated circuit, although this is not required. Integrating the controller113, the post-amplifier112, and the laser driver114onto the same circuit substantially reduces the manufacturing costs of the combination.

FIGS. 2A and 2Bschematically illustrate the optical transceiver integrated circuit that includes a digital core component213. The digital core component213includes a boot component221, an FSB slave component225and an FSB register array component226. FSB stands for “Finisar Serial Bus” and is a Finisar-proprietary two-wire interface. More regarding this two-wire interface is described below with respect toFIGS. 4,5A,5B, and5C. The slave component225and the register array226are labeled as FSB components because they may communicate using the FSB two-wire interface. However, the principles of the present invention are not limited to any specific manner of communication within the optical transceiver integrated circuit. The optical transceiver integrated circuit also may include a clock228.

The post-amplifier112and laser driver114are not illustrated inFIGS. 2A and 2Balthough these components may be present within the optical transceiver integrated circuit as schematically illustrated inFIG. 1. However, settings for the post-amplifier112and the laser driver114may be memory mapped using the FSB register array component226. The FSB slave component225reads data from and writes data to specified address locations within the FSB register array component226in response to specific FSB commands received from or through the boot component221. Specifically, the FSB slave component225may generate signal mem_addr to address a location within the FSB register array226, signal wr_enable to enable a write operation, and signal wr_data to specify the data to be written. In addition, the FSB slave component may read signal rd_data to read data from the specified memory address. The FSB register array226includes an XOR tree227which generates a parity_error signal if there is a parity error detected in the FSB register array. The structure and purpose of the XOR tree227will be described further below.

FIG. 2Aillustrates a configuration200A in which there is no controller external to the optical transceiver integrated circuit210A. Instead, the on-chip boot component221serves as a controller. This configuration will be frequently referred to herein as the “internal controller configuration”. In particular, the boot component221operates while the optical transceiver integrated circuit is starting up. During startup, the boot component221coordinates the proper loading of appropriate instructions from an external EEPROM234into the FSB register array226. Once the startup process completes, the post-amplifier112and the laser driver114are then controlled based on the values within the FSB register array226.

While booting in the internal controller configuration ofFIG. 2A, the boot component221is active. This state is manifested to the boot component by the signal enable_boot being high. Even in this active state, the boot component221may be temporarily disabled by asserting the signal frc_disable_boot signal high.

During the boot process (during which time which the boot component221is active and not temporarily disabled), the boot component221communicates with the memory234using the conventional I2C two-wire interface. In particular, the boot control component223of the boot component221causes the I2C master component222of the boot component221to communicate with the EEPROM memory234using the I2C -compliant clock, data, and write protect signals. The clock signal is represented inFIG. 2Aby signal SCL from the EEPROM perspective and signal twi_clk from the boot component perspective. The data signal is represented by signal SDA from the EEPROM perspective and signal twi_data from the boot component perspective. The write disable signal is represented by signal WP from the EEPROM perspective and by signal boot_busy from the boot component221perspective. The I2C two-wire interface and these corresponding signals are well-known to those of ordinary skill in the art.

Also during the boot process, the boot component221may communicate with and control the FSB slave component225using the FSB two-wire interface. In particular, the boot component221may use the boot control component223to control the FSB master component224. In response, the FSB master component224provides an appropriate clock signal fsb_clk to the FSB slave component225and the FSB register array226. Also, the FSB master component224provides a data signal fsb_data to the FSB slave component225. The fsb_clk and fsb_data signals are provided in conformity with the FSB two-wire interface described below with respect toFIGS. 4,5A,5B and5C.

The boot logic component223is configured such that when the boot component221is starting up, the appropriate data is loaded from the EEPROM234into the FSB register array226. As previously mentioned, doing so involves communication with the EEPROM234using one two-wire interface while communicating with other components (e.g., the FSB slave component225) using a different two-wire interface.

The internal controller configuration ofFIG. 2Aalso illustrates several other external components. For instance, when optional diagnostic mode FSB controller231asserts signal frc_fsb_mode, the signal frc_disable_boot signal is likewise asserted, thereby disabling the boot controller221. This allows the diagnostic mode FSB controller231to communicating straight through the boot component221and to the FSB slave component225using the FSB two-wire interface using clock signal fsb_clk and data signal fsb_data. In this configuration the diagnostic mode FSB controller231behaves as an FSB master component. Accordingly, the diagnostic mode FSB controller231may control the FSB slave component225to thereby cause appropriate diagnostics to be made on the FSB register array226.

Also, the EEPROM programming interface232may likewise assert the frc_disable_boot signal to at least temporarily disable any boot operations. The EEPROM programming interface232may then communicate with the EEPROM234using the SCL and SDA signals in accordance with the conventional I2C two-wire interface. By disabling the boot process during the EEPROM programming, the risk of contention on the clock signal SCL and data signal SDA is significantly reduced. An optional host interface to EEPROM233may also be provided to allow a host computing system to interface with the EEPROM.

Accordingly, the internal controller configuration200A ofFIG. 2Aprovides a mechanism whereby the controller may be on the same integrated circuit as the post-amplifier and laser-driver. Accordingly, there is a higher risk of clock noise being injected into the received and transmitted signal due to the close proximity of the controller to the post-amplifier and laser driver. This risk is reduced by having the oscillator228only operate when the boot controller221is actively booting the optical transceiver integrated circuit210A. The enable_boot is a static configuration signal which is active in the configuration shown inFIG. 2A. Accordingly, whatever signal is provided by the oscillator228is provided through the AND gate229in the form of clock signal boot_clk. The oscillator228is configured to provide such a clock signal during the boot process. Subsequent to the boot process, however, the oscillator228does not provide an oscillating clock signal, thereby eliminating clock noise caused by the oscillator228.

Due to certain environmental conditions, it is conceivable that the data within the FSB register array226may become corrupted. This could have a harmful effect on the post-amplifier and laser driver since the physical operation of the post-amplifier and laser driver is directly dependent upon the values within the FSB register array226. The optical transceiver integrated circuit210A has a mechanism for recovering from register array corruption even without the clock being initially on.

Specifically, each byte in the register array226has a corresponding parity bit. For each byte, the XOR tree227includes an XOR sub-tree that logically XOR's each of the bits in the byte to generate an actual byte parity bit. The actual byte parity bit will be high if the number of logical one's in the byte is odd, and low if the number of logical one's in the byte is even, regardless of whether or not the byte is corrupted.

The actual byte parity bit is XOR'ed with an ideal byte parity bit stored for each byte. The ideal byte parity bit is high if the number of logical one's in the byte should be odd absent any corruption, and low if the number of logical one's in the byte should be even absent any corruption. For each byte, the actual byte parity bit is logically XOR'ed with the ideal byte parity bit to generate a byte parity error bit. The byte parity error bit will only be high if the corresponding byte has become corrupted. The various byte parity bits may be logically OR'ed (or XOR'ed) to generate the parity_error signal inFIG. 2A. Thus, the parity_error signal will only be high if the FSB register array has experienced corruption. In response to a high parity_error signal, the boot control component223asserts the en_boot_clk signal, which activates the oscillator228to thereby reinitiates the boot process. Rebooting should then initialize the register array to appropriate values to thereby allow normal operation to proceed. Once again, after the boot process, the boot clock may be shut off to reduce noise.

The boot controller221permits the internal controller configuration ofFIG. 2Ain which the controller, the post-amplifier, and the laser driver are all on the same optical transceiver integrated circuit. However, the boot controller221may also provide flexibility to have an external controller.FIG. 2Bshows such a configuration200B in which the FSB master controller240communicates directly through the boot component221to the FSB slave component225using clock signal fsb_clk and data signal fsb_data that conform to the FSB two-wire interface. In this case, the enable_boot signal is low thereby rendering the boot clock and the boot controller inactive. Furthermore, the frc_disable signal is low. The configuration ofFIG. 2Bmay also be referred to herein as the “external controller configuration”. The FSB master component240may operate to load, monitor, and update the FSB register array226via the FSB slave component225.

The optical transceiver integrated circuit210A ofFIG. 2Amay be physically structured identically to the optical transceiver integrated circuit210B ofFIG. 2B. The difference is in the value of the enable_boot signal and possibly the frc_disable_boot signal. Alternatively, the enable_boot signal may be the same in bothFIGS. 2A and 2B, with the signal frc_disable_boot representing an override signal that enables the override configuration illustrated inFIG. 2B. Accordingly, the optical receiver integrated circuit210is flexible enough to accommodate both the internal controller configuration and the external controller configuration. Furthermore, this flexibility may be obtained by simply asserting appropriate configuration signals enable_boot and frc_disable_boot to the integrated circuit.

FIG. 3illustrates a configuration300of the core component213in further detail. The I2C master component222, the boot control component223and the FSB master component224are collectively illustrated inFIG. 3as boot state machine310. In the internal controller configuration, when the frc_disable_boot signal is low and the enable_boot signal is high, the boot state machine has access to the boot clock signal boot_clk. During the boot process, the boot state machine310operates as an FSB master component for the FSB slave component225.

Specifically, the boot state machine310pulls signal fsb_slave_mode_sel low. This causes the upper input terminal (marked “0”) of each of the multiplexers311through316to by coupled to its corresponding output terminal. The operation during this internal controller configuration will now be described in further detail with respect toFIG. 3.

The boot state machine310generates a clock signal boot_fsb_clk (out) that is derived from the boot clock signal boot_clk. This clock signal boot_fsb_clk (out) is then provided through the multiplexer311to become the FSB clock signal fsb_clk. The boot state machine310also may generate a data signal in accordance with the FSB two-wire interface and timed in accordance with the FSB clock signal. This data signal is represented by boot_fsb_do (out) passing through the multiplexer314to become signal fsb_di provided to the FSB slave component225. The FSB slave component225may transmit data back to the state machine using signal fsb_do and using output enable signal fsb_do_oe. Accordingly, the boot state machine310is fully capable of acting as an FSB master component for the FSB slave component225using the configuration illustrated inFIG. 3.

During the boot process, the boot state machine310is also capable of communicating with the EEPROM using the I2C two-wire interface. Specifically, a logical zero is asserted through the upper input terminal of the multiplexer312as signal TWI_CO. A clock signal boot_scl generated by the boot state machine310serves as the clock signal for the I2C interface. If the clock signal boot_scl is high, the clock signal is inverted to low through inverter321to provide a low signal to the upper input terminal of multiplexer313. This low signal is provided to driver322thereby isolating low signal TWI_CO from the output terminal of the driver322. Accordingly, the signal twi_clk (the actual clock signal on the clock wire to the EEPROM) is permitted to pull high through pull-up resistor323. If the clock signal boot_scl is low, the clock signal is inverted to high through inverter321to provide a high signal to the upper input of multiplexer313. This high signal is provided to driver322thereby causing the driver to pass signal TWI_CO (which is low) as the clock signal twi_clk provided to the EEPROM. This emulates an open-drain driver. Accordingly, the I2C clock signal twi_clk provided to the EEPROM follows the I2C clock signal boot_scl generated by the boot state machine310.

Similarly, from the I2C data viewpoint, a logical zero is asserted through the upper input terminal of the multiplexer315as signal TWI_DO. A data signal boot_sda generated by the boot state machine310serves as the data signal generated by the boot component221for the I2C interface with the EEPROM. If the data signal boot_sda is high, the data signal is inverted to low through inverter324to provide a low signal to the upper input of multiplexer316. This low signal is provided to driver325thereby isolating low signal TWI_DO from the output terminal of the driver325. Accordingly, the signal twi_data (the actual data signal on the data wire to the EEPROM) is permitted to pull high through pull-up resistor326. If the data signal boot_sda is low, the data signal is inverted to high through inverter324to provide a high signal to the upper input of multiplexer316. This high signal is provided to driver325thereby causing the driver to pass signal TWI_DO (which is low) as the data signal twi_data provided to the EEPROM. This emulates an open-drain driver while still maintaining the capability to directly drive the interface as desired. Accordingly, the I2C data signal twi_data provided to the EEPROM follows the I2C data signal boot_data generated by the boot state machine310. In the other direction, the boot state machine310may also monitor data on the I2C data wire. The signal twi_data is provided through the driver327as the I2C data input signal boot_sda to the boot state machine310.

In summary, during the boot process, the boot state machine310serves as an FSB master for the FSB slave component225, and as an I2C master for the external EEPROM. On the other hand, if the boot state machine310is not active (e.g., because the enable_boot signal is low, or because the frc_disable_boot signal is high), the data state machine permits off-chip components such as a controller to pass through communications through the boot component221directly to the FSB slave component225. This serves the external controller configuration model ofFIG. 2B.

In the external controller configuration mode, the boot state machine asserts the fsb_slave_mode_sel signal high. This couples the lower input terminal of the multiplexers311through316to their respective output terminals. Accordingly, the clock signal twi_clk generated by the off_chip controller passes directly through the driver328and through the multiplexer311to the FSB slave component225and FSB register array226. The driver322is off and thus the boot state machine310does not communicate any clock signals.

The data signals twi_data generated by the external controller passes through the driver327, through the multiplexer314, and to the FSB slave component225. If the FSB slave component225generates a high output enable signal fsb_do_eo, the driver325is on, and the data signal fsb_do generated by the FSB slave component225is provided through the multiplexer315and through the driver325to generate the data signal twi_data. Accordingly, in this configuration, the external controller communicates directly with the FSB slave component.

Accordingly, the principles of the present invention provide an optical transceiver integrated circuit in which the controller, the post-amplifier, and the laser driver may be integrated on the same chip with minimal noise impact. Furthermore, the optical transceiver integrated circuit is configurable either internally control the post-amplifier and laser driver, or allow an external controller to control the FSB slave component, without changing the physical structure of the optical transceiver integrated circuit. This allows users to have flexibility in choosing between a lower cost internal controller configuration, or a higher costs external controller configuration, based on the needs of the user.

It should be noted that while some embodiments of the invention are well-suited for use in conjunction with a high speed data transmission system conforming to the Gigabit Ethernet (“GigE”) physical specification, such operating environment is exemplary only and embodiments of the invention may, more generally, be employed in any of a variety of high speed data transmission systems, some of which may have line rates up to, or exceeding, 1 G, 2.5 G, 4 G, 10 G and higher bandwidth fiber channels. For example, some embodiments of the invention are compatible with the Fibre Channel (“FC”) physical specification.

Further, embodiments of the invention may be implemented in various ways. By way of example, some embodiments of the PA/LD are implemented in Small Form Factor Pluggable (“SFP”) bi-directional transceiver modules. Such transceiver modules are configured for GigE and/or FC compliance. Exemplarily, such transceiver modules are capable of transmitting and/or receiving at a wavelength of about 850 nm. Moreover, these transceiver modules can operate over a wide range of temperatures. For example, some of such transceiver modules are effective over a temperature range of about 80° C., such as from about −10° C. to about +70° C. Of course, such embodiments and associated operating parameters are exemplary only, and are not intended to limit the scope of the invention in any way. For example, the principles of the present invention may be implemented in laser transmitter/receivers of any form factor such as XFP, SFP and SFF, without restriction.

FIG. 4illustrates a schematic diagram of a data structure400of a frame of an FSB two-wire interface mentioned briefly above with respect toFIGS. 2A,2B and3. The frame400includes a preamble field401, a frame start field402, an operation field403, a device identifier field404, an optional extended field405, a basic address field406, a first bus turnaround field407, and optional bus hold field408, a data field409, an optional Cyclic Redundancy Checking (CRC) field410, a second bus turnaround field411, an optional acknowledgement field412, an optional error status field413, and a frame end field414. As will be explained in further detail below, the frame400is designed so that within any component's turn for control of the data wire, there is a guaranteed zero interspersed more frequently than the length of the preamble.

The bus turnaround fields allow for optional transfer of data wire control between the FSB master component and the FSB slave component. Accordingly, the FSB master component may be providing some of the frame, while the FSB slave component may be providing other portions of the frame. Note that while a specific ordering of fields is shown inFIG. 4, there is considerable flexibility as to the ordering of the fields without adversely affecting the functionality of the frame400as will be apparent to those of ordinary skill in the art after having reviewed this description.

FIGS. 5A,5B and5C show specific embodiments of the frame400. Some of the optional fields are included or excluded depending on the operation being performed.FIG. 5Aillustrates an example frame in which the operation is to write or read using an extended field, and using Cyclic Redundancy Checking (CRC) and acknowledgements.FIG. 5Billustrates an example frame in which the operation is to write or read without using an extended field, and using CRC and acknowledgements.FIG. 5Cillustrates an example frame in which the operation is to write or read without using an extended field, and without using CRC and acknowledgements.

SinceFIG. 5Aillustrates the most inclusive frame example, the various fields of the frame will be described in most detail with respect toFIG. 5A. The frame ofFIG. 3Aincludes 75 bits corresponding to bits74:0, regardless of whether the operation is a read operation as specified in line501A or a write operation as specified in line504A.

Line502A illustrates an asterix at time increments when the FSB master component is in control of the data wire during a read operation, and otherwise contains a period. “MOE” at the beginning of the line stands for “Master data Output Enable”. Line303A illustrates an asterix at time increments when the FSB slave component is in control of the data wire during a read operation, and otherwise contains a period. “SOE” at the beginning of the line stands for “slave data Output Enable”.

Similarly, line505A illustrates an asterix at time increments when the FSB master component is in control of the data wire during a write operation, and otherwise contains a period. Furthermore, line506A illustrates an asterix at time increments when the FSB slave component is in control of the data wire during a write operation, and otherwise contains a period. Lines307A and308A will be explained further below.

The frame begins with a preamble as represented inFIG. 5Aby the 15 bits 74:60. This preamble is an example of the preamble field401ofFIG. 4. The data wire132is left in a high impedance state. Absent any assertion on the data wire by FSB master component or any of the FSB slave component(s), the data wire is held to a logical one by a pull-up resistor (see resistor326ofFIG. 3). When the FSB master component determines that a communication is to be made with FSB slave component, the FSB master component generates a clock signal on the clock wire. At the same time, each clock cycle, the FSB master component monitors the data wire for fifteen consecutive ones. The high impedance data wire does allow for proper assertion of data on the data wire despite the presence of the pull-up resistor.

If the FSB master component is not asserting anything on the data wire during the preamble phase, then the data wire should carry a logical one if none of the FSB slave components is transmitting the remainder of a prior frame on the data wire. Alternatively, even if the FSB master component may be asserting a logical one on the data wire during at least some of the preamble, then the data wire should still be carrying the logical one during the preamble phase assuming that none of the FSB slave components is transmitting on the data wire at that time. On the other hand, the frame is designed such that neither a FSB master nor a FSB slave transmits more than fifteen consecutive logical ones in a row when transmitting none-preamble portions of the frame.

Given the above, if the FSB master component detects a logical zero on the data wire while monitoring the data wire during the preamble phase of the frame, then a FSB slave component is likely communicating on the data wire. Whether or not logical zeros are detected, the FSB master component will wait until there are fifteen cycles of logical ones on the data wire before continuing with the frame. Due to the interspersed guaranteed zeros within the frame design, it is then that the FSB master component may safely transmit on the data wire with little risk that one of the FSB slave component(s) is also communicating on the data wire.

Accordingly, even if there is an error in synchronization between the FSB master component and the FSB slave component, synchronization is reacquired as the FSB master component waits for the FSB slave component to complete its use of the data wire before proceeding. The FSB slave component also monitors the data wire for fifteen consecutive ones. Accordingly, when the FSB slave component encounters fifteen consecutive ones, the FSB slave component awaits the rest of the frame. Accordingly, since the FSB slave component is not using the data wire at the time of the preamble regardless of whether the FSB slave component had previously lost synchronization with the FSB master component, the FSB slave component should be listening for the preamble at the preamble phase of the frame. Accordingly, the FSB slave component reacquires synchronization with the FSB master component.

Therefore, the preamble is significantly shortened while further retaining error recovery from loss of synchronization. Furthermore, since the data wire is biased high due to the pull-up resistor, the FSB master component need not assert any data on the data wire during the preamble phase, thereby reducing power requirements.

Once the preamble phase is completed (i.e., the FSB master component has detected at least fifteen consecutive binary ones on the data wire), the FSB master component asserts a logical one on the data wire as represented by bit59. This turns on the output enable for the FSB master component, and maintains the data wire at the logical one for one more cycle.

The FSB master component then transmits two start of frame bits58:57which are guaranteed logical zeros. These start of frame bits are an example of the start of frame field402ofFIG. 4. After the preamble phase is complete, the FSB slave component(s) are listening for these logical zeros. When they arrive, the FSB slave component(s) understand that the two logical zeros correspond to the start of the rest of the frame, thereby attaining synchronization. Two logical zeros are provided in order to provide sufficient statistical probability that the two logical zeros do indeed represent the start of a frame.

The FSB master component then transmits three operation code bits56:54. These operation code bits are an example of the operation field403ofFIG. 4. The three operation code bits would normally permit eight unique operations to be identified. However, in order to guarantee at least one logical zero in this operation code, the number of operations represented by the three bits is six, with the other two permutations of the operation code being reserved. In the illustrated example, bit sequences011and111are reserved.

In the example, operations bits000mean a write operation without using an extended field (explained further below), but with CRC checking and acknowledgements. A frame for this operation is shown in line504B ofFIG. 5B(see bits47:45of line504B).

Operation bits001mean a write operation using an extended field, and with CRC checking and acknowledgments. A frame for this operation is shown in line504A ofFIG. 5A(see bits56:54of line504A).

Operation bits010mean a write operation without using an extended field, and without CRC checking and acknowledgments. A frame for this operation is shown in line504C ofFIG. 5C(see bits35:33of line504C).

Operations bits100mean a read operation without using an extended field, but with CRC checking and acknowledgements. A frame for this operation is shown in line501B ofFIG. 5B(see bits47:45of line501B).

Operation bits101mean a read operation using an extended field, and with CRC checking and acknowledgments. A frame for this operation is shown in line501A ofFIG. 5A(see bits56:54of line501A).

Operation bits110mean a read operation without using an extended field, and without CRC checking and acknowledgments. A frame for this operation is shown in line501C ofFIG. 5C(see bits35:33of line501C).

Note how the structure of the frame differs depending on the operation. Accordingly, the FSB master component controls which frame structure is to be used by controlling the operation code. Upon reading the operation code, the FSB slave component is configured to expect the frame structure corresponding to the operation code. Accordingly, the FSB master component may dynamically adjust the frame structure as needed. In times when bandwidth is more of a concern, the shorter and less reliable frame structure (e.g.,FIG. 5C) may be used. In times when reliability is more of a concern, the longer and more reliable frames structure (e.g.,FIGS. 5A and 5B) may be used. When further bits are needed for any reason, the frame with the extended field (e.g.,FIG. 5A) may be used. When these further bits are not needed, the frames without the extended field (e.g.,FIGS. 5B and 5C) may be used.

Referring back toFIG. 5A, after the FSB master component transmits the operation code (i.e., bits56:54), the FSB master component transmits a three bit device identifier corresponding to bits53:51. These device identifier bits are an example of the device identifier field404ofFIG. 4. The device identifier identifies which FSB slave component of the FSB slave component(s) that the FSB master component is to communicate with. Since three bits are used for the device identifier in this embodiment, there may be up to eight FSB slave components in this embodiment (or seven FSB slave components if the FSB master component is to also have an address for self-diagnostic purposes).

Until the time that the device identifier bits are provided, each of the FSB slave component(s) was monitoring the communications over the data wire. However, upon receiving the device identifier bits, the FSB slave component may identify itself as corresponding to the device identifier. The other FSB slave components, if any, may ignore the rest of the frame. Even though the other FSB slave components ignore the rest of the frame, the other FSB slave components may immediately continue monitoring the data wire for another preamble indicative of another frame being transmitted. Alternatively, the other FSB slave component may initiate such monitoring after clock signals are once again asserted on the clock wire indicating that the next frame is about to begin.

After the FSB master component asserts the device identifier bits53:51on the data wire, the FSB master component asserts eight bits50:43that correspond to an extended field. These extended bits are an example of the extended field405ofFIG. 4. In the case ofFIG. 5A, the operation code causes the FSB slave component to expect these extended bits. The FSB master component then transmits a guaranteed logical zero as bit42thereby ensuring that fifteen consecutive logical ones on the data wire means that a frame is in the preamble phase to thereby support the above-described synchronization recovery mechanism.

The extended field may include any extended bits that are useful so long as the meaning of the bits is commonly recognized by both communicating components. For example, some or all of the extended field may represent an extended address for use when communicating with FSB slave components having larger address spaces. Alternatively or in addition, some or all of the extended field may represent an extended operation code where further operation types are desired.

The FSB master component then asserts eight bits41:34that correspond to the basic address. These eight bits41:34are an example of the basic address field406ofFIG. 4. If all of the extended field represents an extended address, the FSB slave component may use all of the sixteen bits50:43and41:34to properly identify the address space that applies to the operation.

The next bit33in the frame is a first turnaround bit and represents an example of the first turnaround field407ofFIG. 4. The turnaround bits are somewhat unique in that they allow for optional exchange of control of the data wire between the FSB master component and the FSB slave component.

In the case of a write operation, the first turnaround bit33is a logical zero, indicating that control is to stay for the time being with the FSB master component. Accordingly, referring to line505A ofFIG. 5A, the FSB master component retains control of the data wire through the turnaround bit33; and referring to line506A ofFIG. 5A, the FSB slave component does not gain control of the data wire through the turnaround bit33. This retaining of control is appropriate since the FSB master component is the one that is providing that data that is the subject of a write operation initiated by the FSB master component.

On the other hand, in the case of a read operation, the first turnaround bit33is a high-z, meaning that the data wire is permitted to float at its high impedance state in which none of the FSB master component or FSB slave component is actively asserting bits on the data wire. This represents that control of the data wire has passed to the FSB slave component (see lines502A and503A ofFIG. 5A). This transfer of control is appropriate since the FSB slave component is the one that is providing that data that is the subject of a read operation initiated by the FSB master component.

In the case of a read operation, the FSB slave component then has the opportunity to pause the frame in cases in which the FSB slave component is not ready to continue at this stage. The FSB slave component asserts the bus hold bit32to a logical zero if it is not ready to continue. When ready to continue, the FSB slave component asserts a logical one if it is ready to proceed thereby given the FSB master component notice that the FSB slave component is ready to continue. This provides the FSB slave component with an option to pause the frame when the FSB slave component is not ready to continue for the time being. An additional pausing option available to the FSB slave component is described below with respect to the acknowledgement bit. In the case of a write operation, the bus hold bit32is a guaranteed logical one. The bus hold bit32is an example of the bus hold field408ofFIG. 4.

In the case of a read operation, after the FSB slave component transmits the bit hold bit32, the FSB slave component transmits the eight most significant bits followed by a guaranteed zero bit. In the case of a write operation, after the FSB master component transmits the bit hold bit32, the FSB master component transmits the eight most significant bits followed by the guaranteed zero bit. In either case, the eight most significant bits are represented by bits31:24, and the following guaranteed zero bit is represented by bit23.

In the case of a read operation, after the FSB slave component transmits the guaranteed zero bit23, the FSB slave component transmits the eight least significant bits followed by another guaranteed zero bit. In the case of a write operation, after the FSB master component transmits the guaranteed zero bit23, the FSB master component transmits the eight least significant bits followed by the other guaranteed zero bit. In either case, the eight least significant bits are represented by bits22:15, while the other guaranteed zero bit is represented by bit14. The combination of the data bits31:24and22:15are an example of the data field409ofFIG. 4.

In the case of a read operation, after the FSB slave component transmits the guaranteed zero bit14, the FSB slave component transmits eight bits of Cyclic Redundancy Checking (CRC) data corresponding to bits13:06. The CRC bits are one example of the CRC field410ofFIG. 4. Using all the bits after the start of frame bits58:57and prior to the CRC bits13:06, both the FSB master component and the FSB slave component calculate CRC data as shown in line507A. When the FSB master component receives the CRC bits13:06back from the FSB slave component, the FSB master component then compares the CRC information generated by both the FSB master component and the FSB slave component as represented by line508A. If there is a mismatch, then there has likely been an error in transmission, and the FSB master component may begin the frame again after the current frame is ended.

In the case of a write operation, after the FSB master component transmits the guaranteed zero bit14, the FSB master component transmits the CRC bits13:06. Once again, both the FSB master component and the FSB slave component calculate their CRC data. When the FSB slave component receives the CRC bits13:06from the FSB master component, the FSB slave component then compares the CRC information generated by both the FSB master component and the FSB slave component. If there is a mismatch, then there has likely been an error in transmission, and the FSB master component may begin the frame again after the current frame is ended after the FSB master component has been notified of the error. In some cases, an erroneous write operation may have catastrophic (or at least harmful) effects. For example, if the erroneous write operation was for setting a laser bias current, the laser strength could be too strong such that signal distortion occurs. Accordingly, reliable communications is important in such circumstances. The FSB slave component may elect to suppress a write operation when such an error is detected.

After the CRC bits13:06, there is a second turnaround bit05. This second turnaround bit is an example of the second turnaround field411ofFIG. 4. This turnaround operation allows control of the data wire to be given to the FSB slave component if control is not there already. This allows the FSB slave component to give reliability information back to the FSB master component.

In the case of a read operation, control of the data wire has already been passed to the FSB slave component using the first turnaround bit. Accordingly, this second turnaround bit is a logical zero indicating no change in control of the data wire. On the other hand, in the case of a write operation, control of the data wire was not previously given to the FSB slave component using the first turnaround bit. Accordingly, the data wire is allowed to float at its high impedance state indicating a transfer of control of the data wire to the FSB slave component. Accordingly, after the second turnaround bit05, the FSB slave component has control of the data wire regardless of whether the operation is a read operation or a write operation.

After the second turnaround bit05, the FSB slave component asserts an acknowledgment bit04, which is an example of the acknowledgement field412ofFIG. 4. This acknowledgement bit may represent whether or not the operation was successful. In this case, a logical one means successful completion of the operation. Had the FSB slave component been too busy to respond to the FSB master component, the FSB slave component may assert a logical zero for the acknowledgement bit04, thereby forcing the FSB master component to reinitiate the frame. Accordingly, the acknowledgment bit03, and the bit hold bit32provide a way for the FSB slave component to address the situation where it cannot respond to the request.

The FSB slave component then asserts a guaranteed zero bit03, followed by an error bit02, which is an example of the error field413ofFIG. 4. The error field may indicate whether or not there was an error in CRC checking and/or a violation of the protocol (e.g., a logical one is detected where a logical zero should occur). In the case of a read operation, the FSB master component will already be in possession of CRC data sufficient to make this determination. However, in the case of a write operation, the FSB slave component is the one that made the comparison of CRC data. Accordingly, it is at this time that the FSB slave component notifies the FSB master component of any mismatch in CRC data. A mismatch would result in the FSB master component reinitiating the frame. The presence of CRC and acknowledgment information in the frame allows for more reliable communication between the FSB master component and the FSB slave component(s).

The FSB slave component then asserts two end of frame bits01:00, which indicates the end of the frame. The first bit01is a logical one, which forces the data bus immediately to a logical one. In the second bit, the data bus is allowed to float at its high impedance state, ready for the next frame to begin. If the first bit01were a logical zero, it may take some time for the pull-up resistor to pull the data wire up to a voltage level that could be interpreted as a logical one. Accordingly, the setting of the first bit01at a logical one means that the next frame may begin sooner, thereby improving performance.

FIG. 5Billustrates an example frame in which the operation is to write or read without using an extended field, and using CRC and acknowledgements. The frame ofFIG. 5Bis similar to that described above with respect toFIG. 5A, except that the operation is to write or read without using the extended field. Accordingly, bits50:42ofFIG. 5Aare absent fromFIG. 5Band the bits are renumbered accordingly.

FIG. 5Cillustrates an example frame in which the operation is to write or read without using an extended field, and without using CRC and acknowledgements. The frame ofFIG. 5Cis similar to that described above with respect toFIG. 5A, except that the operation is to write or read without using the extended field. Accordingly, bits50:42ofFIG. 5Aare absent fromFIG. 5B. Furthermore, there is no reliability information within the frame. Hence, bits13:02ofFIG. 5Aare absence fromFIG. 5C. The absence fromFIG. 5Cof bits that are present inFIG. 5Awarrants the renumber of the remaining bits inFIG. 5C.