Semiconductor structure with reduced gate doping and methods for forming thereof

A semiconductor structure includes a substrate having a memory region and a logic region. A first p-type device is formed in the memory region and a second p-type device is formed in the logic region. At least a portion of a semiconductor gate of the first p-type device has a lower p-type dopant concentration than at least a portion of a semiconductor gate of the second p-type device. The semiconductor gates of the first and second p-type devices each have a non-zero p-type dopant concentration.

FIELD OF THE INVENTION

The present invention relates generally to semiconductor structures and methods, and more particularly to a semiconductor structure with reduced gate doping and methods for forming thereof.

RELATED ART

Increasingly lower-power semiconductor structures are needed to reduce power requirements of integrated circuits, such as memory devices. Memory devices, such as SRAMS, are typically implemented using bitcells, whose performance is a function of many parameters including semiconductor techniques used to implement the bitcells. SRAM bitcell functionality and performance, among other things, depends on the write margin of the bitcell. Higher write margin enables one to change the state of a bitcell using a lower voltage. Lower voltage correspondingly results in lower power consumption by the bitcell and thus the memory using the bitcell. However, conventional memory devices require higher voltage to perform a state change of the bitcell resulting in higher power consumption. Thus, there is a need for an improved semiconductor structure that results in a higher write margin for bitcells without degrading read performance for memory devices, such as SRAMs.

DETAILED DESCRIPTION OF THE EMBODIMENTS

In one aspect, a method for forming a semiconductor structure is provided. The method includes providing a substrate having a memory region and a logic region. The method further includes forming a first p-type device in the memory region and a second p-type device in the logic region, wherein at least a portion of a semiconductor gate of the first p-type device has a lower p-type dopant concentration than at least a portion of a semiconductor gate of the second p-type device, and wherein the semiconductor gates of the first and second p-type devices each have a non-zero p-type dopant concentration.

In another aspect, a method for forming a semiconductor structure is provided. The method includes providing a substrate having a memory region and a logic region. The method further includes forming a semiconductor gate layer over the gate dielectric layer. The method further includes patterning the semiconductor gate layer to form a first semiconductor gate in the memory region and a second semiconductor gate in the logic region, wherein at least a portion of the first semiconductor gate has a lower dopant concentration of the first conductivity type than a portion of the second semiconductor gate. The method further includes performing a diffusion-reducing implant in the memory region. The method further includes forming source/drain regions in the substrate, adjacent the first semiconductor gate.

In yet another aspect, a semiconductor structure comprising a substrate having a memory region and a logic region is provided. The semiconductor structure further includes a first p-type device in the memory region. The semiconductor structure further includes a second p-type device in the logic region, wherein at least a portion of a semiconductor gate of the first p-type device has a lower p-type dopant concentration than at least a portion of a semiconductor gate of the second p-type device, and wherein the semiconductor gates of the first and second p-type devices each have a non-zero p-type dopant concentration.

FIG. 1is a drawing of a semiconductor structure10with a memory region34and a logic region36, consistent with a process step of one embodiment of the invention. Using semiconductor processing techniques, such as ion implantation, in a p-type substrate12, p-type well regions14,18and n-type well regions16,20may be formed. The p-type well regions14,18and the n-type well regions16and20may be separated by dielectrics22,24, and26, each of which may serve as a shallow trench isolation. Different regions of semiconductor structure10may serve as memory region34and logic region36. By way of example, memory region34may include memory devices, such as SRAM bitcells, whereas logic region36may include logic devices. As part of this process step, a gate layer30may be deposited on top of a gate dielectric layer28. By way of example, gate layer30may be any suitable semiconductor material.

Still referring toFIG. 1, next, a p-type blanket implant32may be implanted into gate layer30. P-type blanket implant32may be implanted into a portion of gate layer30or the entire gate layer30. Any suitable p-type dopant, such as boron, BF2, indium, gallium, and/or other suitable dopants may be used. By way of example, the implantation energy of boron may be in a range between 5 to 15 keV. By way of example, the dosage of boron may be in a range between 1e14 atoms per square centimeter to 1e15 atoms per square centimeter. This may result in a cumulative p-type concentration in the semiconductor gate of the p-type devices in memory region34in a range of approximately 1e18 atoms per cubic centimeter to 5e19 atoms per cubic centimeter. Similar doping concentration in the semiconductor gate of p-type dopant may be achieved using other suitable techniques, such as in-situ doping during gate deposition. For example, inFIG. 1, gate layer30may be in-situ doped during gate deposition.

The dosage for the p-type dopant may be selected to provide a relatively lower doping concentration for at least portions of gate areas in p-type devices in memory region34than the doping concentration for at least portions of gate areas in p-type devices in logic region36. In particular, at least the portions of gate areas above the gate dielectric in memory region34may have a lower doping concentration than at least the portions of gate areas above the gate dielectric in logic region36. As used herein, the term “doping concentration” refers to active dopant concentration. The n-type devices corresponding to memory region34and logic region36may be doped using conventional semiconductor processing techniques. However, their doping concentration may need to be altered to account for the p-type blanket implant32. In any case, the doping concentration for gate areas for p-type devices in memory region34and for gate areas for p-type devices in logic region36may be non-zero. AlthoughFIG. 1shows both n-type and p-type well regions, embodiments of the present invention may be implemented without the p-type well regions.

FIG. 2is a drawing of a semiconductor structure ofFIG. 1with a gate layer and p-type implantation for the logic devices, consistent with a process step of one embodiment of the invention. As part of this process step, p-type devices corresponding to logic region36may be doped using p-type implant40more heavily than the p-type devices corresponding to memory region34. Alternatively, p-type devices corresponding to logic region36may be doped with the same dopant level as the p-type devices corresponding to memory region34. P-type devices in memory region34may be used as load devices or pull-up devices for a SRAM bitcell. N-type devices in memory region34may be used as latch and/or pass-gate devices for the SRAM bitcell. As shown, devices other than the p-type devices corresponding to logic region36may be masked using mask38. Although not shown, n-type devices may be doped using conventional semiconductor processing techniques.

FIG. 3is a drawing of a semiconductor structure ofFIG. 2with implantation of a diffusion-reducing implant44, consistent with a process step of one embodiment of the invention. As part of this process, semiconductor structure10may be masked using masking layer42at all places except p-type devices corresponding to memory region34. Next, diffusion-reducing implant44may be implanted into p-type devices corresponding to memory region34. Although not shown inFIG. 2, diffusion-reducing implant44may implanted into p-type devices corresponding to both memory region34and logic region36, however, p-type devices in memory region34may be subjected to higher amounts of diffusion-reducing implants. By way of example, diffusion-reducing implants44may include nitrogen, carbon, and germanium. By way of example, the implantation energy of nitrogen may be in a range between 2 to 10 keV. By way of example, the dosage of nitrogen may be in a range between 5e14 atoms per square centimeter to 5e15 atoms per square centimeter. By way of example, the implantation energy of carbon may be in a range between 5 to 10 keV. By way of example, the dosage of carbon may be in a range between 5e14 atoms per square centimeter to 5e15 atoms per square centimeter. In one embodiment, rather than performing the steps shown inFIG. 1relating to a p-type blanket implant32, mask42may be used to perform a p-type implant into p-type devices corresponding to memory region34. Diffusion-reducing implant44may be implanted either before implanting p-type implant or after implanting p-type implant.

FIG. 4is a drawing of a semiconductor structure where diffusion-reducing implant is performed at a different step than the process step ofFIG. 3, consistent with a process step of one embodiment of the invention. As shown, diffusion-reducing implant56may be implanted after gates46,48,50,52and spacers60,62,64, and66have been formed. As part of this step, using mask54p-type devices other than the ones in memory region34may be masked. Diffusion-reducing implant56may be nitrogen, carbon, or germanium and may have similar implantation energy and dosage as discussed above with respect toFIG. 3. AlthoughFIG. 4shows spacers60,62,64, and66, diffusion-reducing implant56may be implanted before these spacers are formed.

FIG. 5is a drawing of a semiconductor structure ofFIG. 4with source/drain implants, consistent with a process step of one embodiment of the invention. As part of this step, source/drain implants58may be implanted using conventional semiconductor processing techniques to form source-drain regions68,70. Source/drain regions may be formed using techniques other than implantation, such as in-situ doped epitaxial growth. This step may be performed before or after the step ofFIG. 4. After implanting source/drain implants58, source/drain implants may be performed for other devices of semiconductor structure10. Next, source/drain regions68,70may be annealed to activate the dopants. Source/drain regions68,70may be annealed using a low thermal budget anneal to minimize diffusion.

FIG. 6is a drawing of a semiconductor structure with source-drain regions and spacers formed, consistent with a process step of one embodiment of the invention. P-type devices corresponding to memory region34may have a relatively lower doping concentration for gate areas compared to the doping concentration of gate areas of p-type devices corresponding to logic region36. Additionally and/or alternatively, only the p-type devices corresponding to memory region34may have a diffusion-reducing implant, as discussed above with respect toFIG. 3or4. Lower doping concentration for gate areas in p-type devices in memory region34results in a lower on current for the semiconductor devices in memory region34, while having a minimal effect on threshold voltage. When used as the load device in a SRAM bitcell, this weaker device results in a lower voltage needed to write to the bitcell.

FIG. 7is a drawing of a semiconductor structure with a hard mask72, consistent with a process step of one embodiment of the invention. Hard mask72may be formed using conventional semiconductor processing techniques over gate layer30. By way of example, hard mask may comprise silicon nitride, silicon oxide, silicon oxy-nitride, or poly-crystalline silicon germanium, or other suitable materials and combinations thereof. This step may be performed after the steps shown inFIGS. 1,2, and3. Next, gate layer30and hard mask72may be patterned and etched to form gate areas. Then, hard mask72may be removed from gate areas, except from over the gate areas of p-type devices in memory region34. Referring toFIG. 8, this would result in the formation of a gate stack over p-type devices in memory region34having a gate78and a hard mask portion74.

FIG. 8is a drawing of a semiconductor structure with a source-drain region and spacers, consistent with a process step of one embodiment of the invention. As part of this step, source/drain implants94may be implanted using conventional semiconductor processing techniques to form source-drain regions96,98. By way of example, mask92may be used to mask n-type devices, as part of this step. Hard mask portion74may block source/drain implants94from gate78corresponding to p-type devices in memory region34. Thus, p-type devices in memory region34may have gates that do not receive dopants from the source/drain implants94. Spacers84,86,88, and90may be formed prior to source/drain implants94. Additional steps, such as halo implantation and extension implantation may be performed prior to forming spacers84,86,88, and90.

FIG. 9is a drawing of a semiconductor structure ofFIG. 8with source/drain regions and spacers, consistent with a process step of one embodiment of the invention. Hard mask portion74may be removed using conventional etching techniques.

Although the above processes and the semiconductor structure are described using exemplary lower concentration doping of p-type devices, n-type devices may also be doped with a lower concentration dopant consistent with an alternative embodiment of the invention. Thus, for example, where a SRAM uses n-type devices as load devices and p-type devices as latch devices, n-type devices corresponding to memory region34may be doped with a lower dopant concentration resulting in weaker n-type devices. The weaker n-type devices may improve the write margin of a SRAM that employs the weaker n-type devices as load devices. The p-type devices corresponding to memory region34and logic region36may be doped using conventional semiconductor processing techniques. Additionally, although the above processes and the semiconductor structure are described using planar structures, non-planar processes and semiconductor structures may also be formed using the above processes. Thus, for example, FinFETs and similar other non-planar structures may also be formed.