Variable resistance memory device with trigger circuit for set/reset write operations

A variable resistance memory device comprises a variable resistance memory cell, a switch that selectively passes a write voltage to an input terminal of the variable resistance memory cell, and a trigger circuit that controls the switch to cut off the write voltage from the input terminal upon determining that the variable resistance memory cell is programmed to a target state by detecting voltage fluctuation of the one side of variable resistance memory cell.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims priority under 35 U.S.C. §119 to Korean Patent Application No. 10-2010-0012486 filed on Feb. 10, 2010, the disclosure of which is hereby incorporated by reference in its entirety.

BACKGROUND

Embodiments of the inventive concept relate generally to electronic memory technologies. More particularly, embodiments of the inventive concept relate to nonvolatile memory devices and related methods of operation.

Semiconductor memory devices can be roughly divided into two categories according to whether they retain stored data when disconnected from power. These categories include volatile memory devices, which lose stored data when disconnected from power, and nonvolatile memory devices, which retain stored data when disconnected from power. Examples of volatile memory devices include static random access memory (SRAM) and dynamic random access memory (DRAM), and examples of nonvolatile memory devices include ferroelectric random access memory (FRAM), magnetoresistive random access memory (MRAM), phase-change random access memory (PRAM), and resistive random access memory (RRAM).

Resistive random access memory (RRAM) has the potential for high storage capacity, high performance, and low power consumption. Accordingly, extensive research is being conducted in the field of RRAM technology to improve the characteristics of RRAM devices. An RRAM device stores data using a variable resistance material layer that changes resistance according to the polarity and size of an applied electrical pulse. One type of variable resistance material layer is a colossal magnetoresistive (CMR) material layer having a perovskite structure.

RRAM and other memories using a variable resistance material layer are referred to as variable resistance memories. Variable resistance memory devices can be classified as unipolar devices and bipolar devices according to polarity of a writing pulse. In a unipolar variable resistance device, a set pulse and a reset pulse have the same polarity. As a result, unipolar variable resistance memory devices may exhibit unstable performance in the presence of a unipolar pulse.

SUMMARY

According to one embodiment of the inventive concept, a variable resistance memory device comprises a variable resistance memory cell, a switch that selectively passes a write voltage to an input terminal of the variable resistance memory cell, and a trigger circuit that controls the switch to cut off the write voltage from the input terminal of the variable resistance memory cell upon determining that the variable resistance memory cell is programmed to a target state by detecting a voltage fluctuation at the input terminal.

In certain embodiments, the variable resistance memory cell comprises a variable resistance device comprising a unipolar resistance memory material.

In certain embodiments, the switch comprises a transistor controlled by the trigger circuit.

In certain embodiments, the trigger circuit comprises a comparator that compares a voltage level of the input terminal with a reference voltage to generate a comparison result and generates a switch control signal for controlling the switch according to the comparison result.

In certain embodiments, the comparator generates the switch control signal with a logic level that causes the switch to cut off the write voltage from the input terminal upon determining that the voltage level of the input terminal is higher than the reference voltage.

In certain embodiments, the trigger circuit further comprises a first multiplexer that selects and outputs the comparison result or an inverted comparison result according to the target state, and a second multiplexer that selects and outputs an output of the first multiplexer or a row select signal to generate the switch control signal.

In certain embodiments, the first multiplexer selects the inverted comparison result where the target state is a reset state and selects the comparison result where the target state is a set state.

In certain embodiments, the comparator generates the comparison result with a high logic level where the voltage level of the input terminal is lower than the reference voltage.

In certain embodiments, the reference voltage is controlled according to a magnitude of a signal delay between the switch and the variable resistance memory cell.

In certain embodiments, the reference voltage is lowered as the magnitude of the signal delay increases.

In certain embodiments, the variable resistance memory device further comprises a bypass circuit that selectively connects the input terminal of the variable resistance memory cell to an output terminal of the variable resistance memory cell under the control of the trigger circuit.

According to another embodiment of the inventive concept, a variable resistance memory device comprises a cell array comprising a plurality of variable resistance memory cells, a read/write circuit that provides a write voltage to a selected memory cell among the plurality of variable resistance memory cells through a bit line, determines whether the selected memory cell is programmed by comparing a reference voltage to a voltage level of the bit line, and cuts off the write voltage from the bit line according to the comparison, and a reference voltage generator that generates the reference voltage with a magnitude that varies according to an address of the selected memory cell.

In certain embodiments, the reference voltage generator classifies the plurality of memory cells into a plurality of groups according to corresponding addresses and generates the reference voltage with a different magnitude for each of the plurality of groups.

In certain embodiments, the reference voltage generator generates the reference voltage with a lower magnitude for groups located farther from the read/write circuit.

In certain embodiments, the variable resistance memory device further comprises control logic that controls the reference voltage generator according to a row address of the selected memory cell to vary the magnitude of the reference voltage.

In certain embodiments, the read/write circuit comprises a transistor that selectively passes the write voltage to the bit line, and a trigger circuit that prevents the transistor from passing the write voltage to the transistor upon determining that the selected memory cell is programmed to a target state by comparing the reference voltage and the voltage level of the bit line.

According to another embodiment of the inventive concept, a method of programming a variable resistance memory device comprises applying a write voltage to an input terminal of a variable resistance memory cell, determining whether the variable resistance memory cell is programmed to a target state by detecting a voltage fluctuation at the input terminal, and cutting off the write voltage from the input terminal upon determining that the variable resistance memory cell is programmed to a target state.

In certain embodiments, determining whether the variable resistance memory cell is programmed to the target state comprises comparing a voltage level of the input terminal with a reference voltage.

In certain embodiments, the reference voltage is adjusted according to a delay required for the write voltage to reach the variable resistance memory cell.

In certain embodiments, the variable resistance memory cell comprises a unipolar variable resistance device.

DETAILED DESCRIPTION OF EMBODIMENTS

Embodiments of the inventive concept are described below with reference to the accompanying drawings. These embodiments are presented as teaching examples and should not be construed to limit the scope of the inventive concept.

FIGS. 1A and 1Bare circuit diagrams illustrating a memory cell of a variable resistance memory device.

Referring toFIG. 1A, a memory cell10comprises a variable resistance device R and a diode D. Variable resistance device R comprises a variable resistance material for storing data. Diode D is a select device (or a switching device) that supplies or cuts off a current to variable resistance device R according to bias voltages of a wordline WL and a bitline BL. Diode D is connected between variable resistance device R and wordline WL, and variable resistance device R is connected between bitline BL and diode D. However, the relative locations of variable resistance device R and diode D can be exchanged.

Although not illustrated in the drawings, variable resistance device R typically comprises a pair of electrodes and a data storage layer formed between the electrodes. The data storage layer can be formed from a bipolar resistance memory material or a unipolar resistance memory material. The bipolar resistance memory material is programmed to a set state or a reset state according to a polarity of an applied electrical pulse. The unipolar resistance memory material is programmed to a set state or a reset state by an electrical pulse having the same polarity. The unipolar resistance memory material typically comprises a unitary transition metal oxide such as NiOx or TiOx.

Diode D of memory cell10is turned on or turned off depending on a bias of wordline WL or bitline BL. Where a forward voltage of diode D is higher than a threshold voltage of diode D, diode D is turned on. Where diode D is turned on, a program current is provided to variable resistance device R.

Referring toFIG. 1B, a memory cell20comprises a variable resistance device R and a transistor NT. Variable resistance device R can be formed in the substantially same manner as variable resistance device R ofFIG. 1A. Transistor NT is turned on or off according to a bias of a wordline WL. Accordingly, transistor NT is a select device (or a switching device) that supplies or cuts off a current to variable resistance device R.

FIGS. 2A and 2Bare waveforms showing a program characteristic of a variable resistance device. In particular,FIG. 2Ais a waveform view showing a fluctuation of a voltage and a current of a variable resistance device programmed to a reset state.FIG. 2Bis a waveform view showing a fluctuation of a voltage and a current of a variable resistance device programmed to a set state.

Referring toFIG. 2A, a reset voltage is applied to a variable resistance device to program the variable resistance device to a reset state. In response to the reset voltage, the variable resistance device changes from a set state, which is a low resistance state, to the reset state, which is a high resistance state. Where the reset voltage is applied to the variable resistance device at a time of T0, a current having a waveform illustrated inFIG. 2Aflows through the variable resistance device.

The variable resistance device changes from the set state to the reset state if the reset voltage is maintained higher than a specific level for a sufficient time. For example, the variable resistance device changes to the reset state at a time of T1, and consequently, current is rapidly reduced. At time T1, the variable resistance device may be programmed to the reset state. In the drawings, a voltage peak30and a current trough40indicate a point of time where the variable resistance device is first programmed to the reset state. However, the reset voltage continues to be applied to the variable resistance device beyond that point of time.

The resistance of the variable resistance device tends to remain stable in the presence of relatively lower voltages, such as 1.0V or less. However, in the presence of the reset pulse, the resistance of the variable resistance device can fluctuate irregularly between a high resistance state and a low resistance state. This fluctuation can produce a current vibration such as that shown in a time interval T1-T2ofFIG. 2A. The instability of the variable resistance device lasts until time T2at which the reset voltage is no longer applied to the variable resistance device. Accordingly, a final resistance state of the variable resistance device can vary at time T2.

In certain embodiments of the inventive concept, during an operation for programming the variable resistance device to the reset state, the reset voltage is cut off upon reaching a point of time where voltage peak30or current peak40occurs. By cutting off the reset voltage at a point of time where voltage peak30or current peak40occurs, the variable resistance device can be stabilized to a high resistance state.

Referring toFIG. 2B, a set voltage is applied to the variable resistance device to program the variable resistance device to a set state. In response to the set voltage, the variable resistance device changes from the reset state to the set state. Where the set voltage is applied to the variable resistance device at a time of t0, current flows through the variable resistance device as illustrated inFIG. 2B.

The variable resistance device changes from the reset state to the set state if the set voltage is maintained higher than a specific level for a sufficient time. However, where the set pulse is maintained for too long, the resistance of the variable resistance device can fluctuate irregularly between a high resistance state and a low resistance state. Accordingly, a final resistance state of the variable resistance device can vary at a time t3at which the set voltage is cut off.

In certain embodiments of the inventive concept, in an operation for programming the variable resistance device to the set state, the set voltage is cut off upon reaching a point of time where a voltage peak50or a current peak60occurs. By cutting off the set voltage in this manner, the variable resistance device can be stabilized at the low resistance state.

FIG. 3is a graph illustrating a load characteristic of a variable resistance device during a program operation. More particularly,FIG. 3shows a load-line of a memory cell comprising a variable resistance device modeled as a load resistance Rloadand a cell resistance Rcell.

The load-line represents a memory cell current I as a function of a V0-V, where V0is a fixed value. Specifically, the load-line is defined by the following Equation (1).

In an operation where a memory cell having a cell resistance Rcellis programmed from a high resistance state R_high to a low resistance state R_low, cell resistance Rcellis unstable until a voltage V falls below a certain level. For example, under certain conditions, where voltage V is higher than a specific voltage V′reset, cell resistance Rcellmay return to high resistance state R_high, which can invalidate a set program operation. On the other hand, where cell resistance Rcellis programmed to high resistance state R_high and voltage V is higher than a specific voltage V′set, cell resistance Rcellcan return to low resistance state R_low. Accordingly, cell resistance Rcellcan fluctuate between the set state and the reset state until the reset voltage or the set voltage is removed. This can affect both the reliability of stored data and the life the memory cell.

FIG. 4is a block diagram illustrating a variable resistance memory device100according to an embodiment of the inventive concept.

Referring toFIG. 4, variable resistance memory device100comprises a memory cell110, a trigger circuit120, and a switch130.

In a program operation, a write voltage Vwriteis applied to a terminal SN of memory cell110and another terminal of memory cell110is connected to ground. In this example, memory cell110comprises a variable resistance device R and a diode D. However, in alternative embodiments, memory cell110can be formed by other features, such as a transistor NT and a variable resistance device R.

In response to the application of write voltage Vwrite, trigger circuit120detects a node voltage VSNformed on terminal SN of memory cell110. Trigger circuit120compares the detected node voltage VSNwith a reference voltage Vref and turns switch130on or off according to the comparison. Switch130is controlled by a switch control signal CNTL output from trigger circuit120. Write voltage Vwriteis provided to memory cell110according to whether switch130is turned on or turned off.

Trigger circuit120monitors node voltage VSNto detect a point of time at which memory cell110is first programmed and cuts off write voltage Vwriteafter the detected point of time. By cutting off write voltage Vwritein this manner, trigger circuit120prevents memory cell110from fluctuating between the set state and the reset state.

Trigger circuit120receives reference voltage Vref and control signals Mode, Set/Reset, and Yi. The control signal Mode indicates a program mode or a read mode of variable resistance memory device100. Trigger circuit120activates switch control signal CNTL in the program mode. State signal Set/Reset indicates a state to which memory cell110is to be programmed. Row select signal Yi is a signal for activating switch130in the read mode. For example, where memory cell110is to be programmed to the set state, state signal Set/Reset indicates the set state, and the mode signal indicates the program mode.

FIG. 5is a circuit diagram illustrating a variable resistance memory device100ain accordance with an embodiment of the inventive concept.

Referring toFIG. 5, variable resistance memory device100acomprises memory cell110, trigger circuit120, and a switch130a.

Memory cell110is substantially the same as memory cell110illustrated inFIG. 4. Switch130acomprises an NMOS transistor NM that is turned on or turned off by switch control signal CNTL.

Trigger circuit120comprises a differential amplifier121, an inverter INV, and multiplexers122and123. Differential amplifier121compares node voltage VSNand reference voltage Vref. Where node voltage VSNis higher than reference voltage Vref, differential amplifier121outputs a comparison signal CMP with a logic state “high” (or logic ‘1’). Where node voltage VSNis lower than reference voltage Vref, differential amplifier121outputs comparison signal CMP with a logic state “low” (or logic ‘0’).

Comparison signal CMP is transmitted to a first input of multiplexer122. Comparison signal CMP is inverted by inverter INV to be transmitted to a second input of multiplexer122. Where memory cell110is to be programmed to the set state, multiplexer122selects the first input, and where memory cell110is to be programmed to the reset state, multiplexer122selects the second input.

Multiplexer123selects an output of multiplexer122in the program mode and selects row select signal Yi in other modes, such as the read mode. The signal selected by multiplexer123is output as switch control signal CNTL. Switch control signal CNTL is provided as a gate voltage for NMOS transistor NM.

FIGS. 6A and 6Bare timing diagrams illustrating a reset program operation and a set program operation of variable resistance memory device100a. In particular,FIG. 6Aillustrates the reset program operation, andFIG. 6Billustrates the set program operation.

Referring toFIG. 6A, in an interval t0-t1, a memory cell to be programmed to the reset state is selected according to a command and an address. Then, at time t1, a selected wordline WL is biased from a floating state F to ground GND, and unselected wordlines are biased to an unselect voltage Vunsel. State signal Set/Reset is set to logic ‘0’ to select the second input of multiplexer122, and mode signal Mode is set to logic ‘0’ to indicate a program operation.

Switch control signal CNTL is output as logic ‘1’until node voltage VSNreaches reference voltage Vref. Then, comparison signal CMP is inverted at time t3where node voltage VSNreaches reference voltage Vref. In response to the inversion of comparison signal CMP, switch control signal CNTL is inverted. Where switch control signal CNTL is inverted, NMOS transistor NM is turned off. Then, write voltage Vwriteis no longer provided to memory cell110, and node voltage VSNis lowered. Because the level of node voltage VSNis lowered, memory cell110is prevented from exhibiting unstable states.

Referring toFIG. 6B, in a first interval t0-t1, a memory cell to be programmed to the set state is selected according to a command and an address. Then, at a time t1, a selected wordline WL is biased from floating state F to ground GND, and unselected wordlines are biased to an unselect voltage Vunsel. State signal Set/Reset is set to logic ‘1’ to select the first input of multiplexer122, and mode signal Mode is set to logic ‘0’ to indicate a program operation.

Switch control signal CNTL is output as logic ‘0’ until node voltage VSNreaches reference voltage Vref. Then, switch control signal CNTL is switched to logic ‘1’ to turn on NMOS transistor NM until node voltage VSNfalls below reference voltage Vref at a time t3. At time t3, comparison signal CMP is inverted, which causes switch control signal CNTL to become inverted, turning off NMOS transistor NM. Then, write voltage Vwriteis cut off from memory cell110, and a level of node voltage VSNis lowered. Because the level of node voltage VSNis lowered, memory cell110is prevented from exhibiting unstable states.

FIG. 7is a circuit diagram illustrating a variable resistance memory device200according to an embodiment of the inventive concept.

Referring toFIG. 7, variable resistance memory device200comprises a memory cell210, a trigger circuit220, and a transistor230. In contrast to the trigger circuits ofFIGS. 6A and 6B, trigger circuit220cuts off write voltage Vwriteonly where memory cell210is programmed to the set state.

Trigger circuit220comprises a differential amplifier221and a multiplexer223. Differential amplifier221compares a node voltage VSNwith a reference voltage Vref and outputs a comparison signal CMP as logic ‘0’ where node voltage VSNis lower than reference voltage Vref. Differential amplifier221outputs comparison signal CMP as logic ‘1’ where node voltage VSNis higher than reference voltage Vref.

Comparison signal CMP is transmitted to a first input of multiplexer223. Multiplexer223selects the first input during a program operation mode for writing data in memory cell210. Multiplexer223selects row select signal Yi during a read operation mode for reading data from memory cell210. Consequently, during the program operation mode, comparison signal CMP is provided as a switch control signal CNTL for controlling transistor230.

FIG. 8is a timing diagram illustrating a set program operation of the variable resistance memory device ofFIG. 7.

Referring toFIG. 8, in an interval t0-t1, a memory cell to be programmed to the reset state is selected according to a command and an address. Then, at a time t1, a selected wordline WL is biased to ground GND and unselected wordlines are biased to an unselect voltage Vunsel. Mode signal Mode is set to logic ‘0’ to indicate a program operation. Consequently, comparison signal CMP is generated as switch control signal CNTL.

Switch control signal CNTL is output as logic ‘1’ during an interval ending at a time t2in which node voltage VSNis greater than reference voltage Vref. Then, at a time t2, node voltage VSNfalls below reference voltage Vref, which causes comparison signal CMP to switch from logic ‘1’ to logic ‘0’. Accordingly, switch control signal CNTL changes to logic ‘0’ at time t2. Where switch control signal CNTL changes to logic ‘0’, transistor230is turned off, which cuts off write voltage Vwritefrom node voltage VSN. As a result, node voltage VSNis lowered to a level at which the resistance of memory cell210is stable.

FIG. 9is a circuit diagram illustrating a variable resistance memory device300according to an embodiment of the inventive concept.

Referring toFIG. 9, variable resistance memory device300comprises a memory cell310, a trigger circuit320, and a transistor330. Trigger circuit320cuts off write voltage Vwritefrom memory cell310where memory cell310is programmed to the reset state.

Trigger circuit320comprises a differential amplifier321and a multiplexer323. Differential amplifier321compares a node voltage VSNto a reference voltage Vref. Differential amplifier321outputs a comparison signal CMP as logic ‘1’ where node voltage VSNis lower than reference voltage Vref and outputs comparison signal CMP as logic ‘0’ where node voltage VSNis higher than reference voltage Vref.

Comparison signal CMP is transmitted to an input of multiplexer323. Multiplexer323selects comparison signal CMP in a program operation mode for writing data in memory cell310. Multiplexer323selects row select signal Yi in a read operation mode for reading data from memory cell310. Consequently, in the program operation mode, comparison signal CMP is provided as a switch control signal CNTL for controlling transistor330.

Switch control signal CNTL transitions to logic ‘0’ where node voltage VSNrises above reference voltage Vref. Consequently, switch control signal CNTL prevents write voltage Vwritefrom being provided to memory cell310after memory cell310is programmed to the reset state.

FIG. 10is a block diagram illustrating a variable resistance memory device400according to an embodiment of the inventive concept.

Referring toFIG. 10, variable resistance memory device400comprises a cell array410, a row decoder420, a read/write circuit430, control logic440, and a reference voltage generator450.

Cell array410comprises a plurality of memory cells arranged in rows and columns. Each of the memory cells comprises a variable resistance device and a select device. Cell array410is divided into a plurality of groups according to row addresses. Each of the plurality of groups can be constituted by memory cells connected to the same wordline or memory cells connected to a set of adjacent wordlines.

The grouping of memory cells in cell array410typically depends on a spatial distance of the memory cells from a trigger circuit435, as will be described below. As examples, memory cells in a first group411are farther from trigger circuit435than memory cells in a second group412.

Memory cells in different groups have different timing delays with respect to trigger circuit435, and node voltage VSNis applied to each selected memory cell after a delay corresponding to the group to which it belongs. Consequently, the reliability of program operations can be improved by adaptively controlling the timing of trigger circuit435according to the delay of each group unit.

Row decoder420decodes a row address Xj being input to select a row. Row decoder420selects a wordline corresponding to row address Xj to perform a program operation or a read operation.

Read/write circuit430selects a bitline corresponding to a column address Yi. In a read mode, read/write circuit430reads data of a selected memory cell connected to a selected bitline under the control of control logic440. In a program mode, read/write circuit430writes data in a selected memory cell connected to a selected bitline under the control of control logic440.

In a program mode, read/write circuit430controls a write voltage Vwriteaccording to a reference voltage Vref provided by reference voltage generator450. Read/write circuit430controls the supply of write voltage Vwriteto selected bitlines using trigger circuit435. InFIG. 10, trigger circuit435is located in read/write circuit430, but it can be arranged in other locations in alternative embodiments.

Control logic440controls read/write circuit430and reference voltage generator450according to a command CMD and an address ADDR. For example, where command CMD is a read command, control logic440controls read/write circuit430so that read/write circuit430senses data from selected memory cells and outputs the sensed data. Where command CMD is a write command, control logic440controls read/write circuit430to program selected memory cells to a set state or a reset state.

In the program mode, control logic440receives address ADDR and decodes address ADDR to detect a group in which selected memory cells are located. Typically, the group is detected according to row address Xj. Control logic440then controls reference voltage generator450to generate a reference voltage Vref corresponding to the detected group.

Then, under the control of control logic440, reference voltage generator450generates a reference voltage Vref corresponding to the group to which selected memory cells belong. For example, where selected memory cells belong to first group411, reference voltage generator450generates a first reference voltage Vref_1, and where selected memory cells belong to second group412, reference voltage generator450generates a second reference voltage Vref_2.

The level of reference voltage Vref can be varied for different groups according to corresponding bitline delays. For example, second reference voltage Vref_2can be relatively lower than first reference voltage Vref_1because memory cells in second group412are connected to trigger circuit435through a longer path having greater bitline delays.

FIG. 11is a circuit diagram illustrating an example structure of read/write circuit430and cell array410. For simplicity of illustration,FIG. 11shows a single column of cell array410.

Trigger circuit435and a transistor431are substantially the same as trigger circuit120and transistor130aillustrated inFIG. 5. However, in trigger circuit435, a reference voltage Vref for determining a turn-off time of transistor431varies according to cell groups411through414.

Where a memory cell in first group411is selected by row address Xj, reference voltage generator450generates first reference voltage Vref_1. Where a memory cell in second group412is selected by row address Xj, reference voltage generator450generates second reference voltage Vref_2. Where a memory cell in an n-th group414is selected by a row address Xj, reference voltage generator450generates an n-th reference voltage Vref n.

A distance L2between the memory cell in second group412and a sensing node SN is greater than a distance L1between the memory cell in first group411and sensing node SN, and a distance Ln between the memory cell in the n-th group414and sensing node SN is greater than distance L2. A bitline delay of the memory cell in second group412is longer than a bitline delay of the memory cell in first group411, and a bitline delay of the memory cell in n-th group414is longer than a bitline delay of the memory cell in second group412. Due to the above factors, the timing differs for supplying write voltage Vwriteto different cell groups.

Different bitline delays between cell groups can be compensated by controlling reference voltage Vref. For example, different bitline delays can be compensated for by providing a lower reference voltage to cell groups having a greater bitline delay.

FIG. 12is a block diagram illustrating a variable resistance memory device500according to an embodiment of the inventive concept.

Referring toFIG. 12, variable resistance memory device500comprises a memory cell510, a trigger circuit520, and a bypass transistor530. Trigger circuit520controls write voltage Vwriteusing a feed-forward method rather than a feed-back method as used in embodiments described above.

Memory cell510is substantially the same as the memory cells illustrated inFIGS. 4,5,7,9, and10. Trigger circuit520is similar to one of the trigger circuits illustrated inFIGS. 5,7,9, and11. However, a switch control signal CNTL generated by trigger circuit520is provided to bypass transistor530disposed at both sides of memory cell510. Bypass transistor530shunts write voltage Vwriteto ground in response to switch control signal CNTL. In particular, where trigger circuit520detects that memory cell510is programmed to a target state, trigger circuit520generates switch control signal CNTL with logic ‘1’ to turn on bypass transistor530. Then, both sides of memory cell510are connected to ground. A difference of electric potential between both sides of memory cell510is almost 0V, so memory cell510maintains a stable state.

Variable resistance memory device500can be modified in a variety of ways, such as adding an additional switch, such as switch130ofFIG. 4, to further control node voltage VSN.

FIG. 13is a circuit diagram illustrating a variable resistance memory device600according to an embodiment of the inventive concept.

Referring toFIG. 13, variable resistance memory device600comprises a cell array610, a row select circuit620, a column select circuit630, a trigger circuit640, and a bypass transistor650.

Cell array610comprises memory cells arranged in an array of four rows and four columns. The memory cells are connected to a plurality of wordlines WL1-WL4and a plurality of bitlines BL1-BL4. Each memory cell comprises a variable resistance device as a memory element.

Row select circuit620selects any of wordlines WL1-WL4in response to wordline select signals WLS1-WLS4. For instance, to select a wordline WL2, a wordline select signal WLS2is activated, and wordline WL2is connected to ground through a transistor WST2.

Column select circuit630selects any one bitline in response to bitline select signals BLS1-BLS4. Column select circuit630provides a write voltage Vwriteto a selected bitline in response to the bitline select signals BLS1-BLS4.

Trigger circuit640detects a moment where a selected memory cell is programmed and controls bypass transistor650to connect the selected memory cell to ground after the selected memory cell is programmed. Trigger circuit640can be implemented similar to any one of the trigger circuits illustrated inFIGS. 5,7,9, and11.

The embodiment ofFIG. 13can be modified in a variety of ways, including applying different reference voltages to trigger circuit640according to different row addresses as described with reference toFIGS. 10 and 11.

FIG. 14is a block diagram illustrating a computer system1000comprising a variable resistance memory device according to an embodiment of the inventive concept.

Referring toFIG. 14, computer system1000comprises a nonvolatile memory device1010, a microprocessor1020, a RAM1030, a user interface1040and a modem1050, such as a baseband chipset, that are electrically connected to a system bus1060. Nonvolatile memory device1010comprises rewritable variable resistance memory cells.

Where computer system1000is a mobile device, a battery can be provided to supply an operating voltage. Computer system1000can further comprise various additional features, such as an application chipset, a camera image processor CIS, or a mobile DRAM.

FIG. 15is a block diagram illustrating a memory system comprising a variable resistance memory device according to an embodiment of the inventive concept.

Referring toFIG. 15, the memory system comprises a memory2010and a memory controller2020electrically connected to memory2010. Memory2010can take the form of one of the variable resistance memory devices described with reference toFIGS. 4-13. Memory controller2020generates signals for controlling memory2010. For example, memory controller2020can generate command and address signals for accessing memory2010.

Memory controller2020typically comprises a memory interface, a host interface, an error correction code (ECC) circuit, a central processing unit (CPU), and a buffer memory. The memory interface provides data received from the buffer memory to memory2010or provides data read from memory2010to the buffer memory. Also, the memory interface can provide commands and addresses from an external source to memory2010.

The host interface can communicate with the external host using one of several protocols, such as universal serial bus (USB), small computer system interface (SCSI), peripheral component interconnect (PCI) express, advanced technology attachment (ATA), parallel ATA (PATA), serial ATA (SATA), or serial attached SCSI (SAS).

The ECC circuit generates error correction codes for data transmitted to memory2010and stores the generated ECC in a specific region of memory2010together with the data. The ECC circuit detects errors in data read from memory2010. Where the detected errors are in a correctable range, the ECC circuit corrects the detected error.

The CPU analyzes and processes signals received from an external host. The CPU communicates with the external host and memory2010through the host interface or the memory interface. The CPU controls write, read, and erase operations of memory2010according to firmware associated with memory2010. The buffer memory temporarily stores write data provided from the external host or data read from memory2010.

FIG. 16is a block diagram illustrating a memory card2000comprising a variable resistance memory device according to an embodiment of the inventive concept.

The memory card ofFIG. 16is the substantially same as the memory system ofFIG. 15except that memory2010and memory controller2020are mounted on memory card2000. Memory card2000can be installed in an electronic device such as a digital camera, personal media player (PMP), a mobile phone, or a notebook computer. Memory card2000can take a variety of forms, such as a multimedia card (MMC), a secure digital (SD) card, a micro SD card, a memory stick, an ID card, a PCMCIA card, a chip card, a USB card, a smart card, or a compact flash card.

FIG. 17is a block diagram illustrating an electronic system comprising a variable resistance memory device connected to a host according to an embodiment of the inventive concept.

Referring toFIG. 17, memory2010is connected to a host2100. Host2100can take various forms, such as a digital camera, a PMP, a mobile phone, or a notebook computer. Host2100provides control signals for controlling memory2010. For example, host2100can provide command and address signals for accessing memory2010. Memory2010can take the form of one of the variable resistance memory devices illustrated inFIGS. 4,5,7,9,10, and13.

FIG. 18is a block diagram illustrating a computer system comprising a memory card connected to a host according to an embodiment of the inventive concept. In this embodiment, host2100provides commands, addresses, and data to memory controller2020. In response to the signals from host2100, memory controller2020generates control signals to access memory2010.

FIG. 19is a block diagram illustrating a computer system2200comprising a variable resistance memory device connected to a CPU according to an embodiment of the inventive concept.

Referring toFIG. 19, computer system2200comprises a memory2210electrically connected to a CPU2220by a data bus. Computer system2200can take a variety of forms, such as a digital camera, a PMP, a mobile phone, a desk top computer, or a notebook computer.

FIG. 20is a block diagram of a portable system3000comprising a variable resistance memory device according to an embodiment of the inventive concept.

Referring toFIG. 20, portable system3000comprises a memory3100connected to a microprocessor3200through a bus line3600. Memory3100can be driven as a main memory of portable system3000. A battery3400provides a power supply to microprocessor3200, an input/output device3300, and memory3100through a power supply line3500

Input/output device3300receives data from an external source and provides the received data to microprocessor3200through bus line3600. Microprocessor3200processes the received data and provides the processed data to memory3100through bus line3600. Memory3100stores the data in selected memory cells. Data stored in memory3100is read by microprocessor3200and output to an external destination through input/output device3300. Because memory3100is a nonvolatile memory, it retains stored data even where battery3400is not provided to power supply line3500. In addition, memory3100can provide other advantages such as relatively high operating speed and low power consumption compared with other types of memory.

FIG. 21is a block diagram illustrating an example of a memory system comprising a variable resistance memory device according to an embodiment of the inventive concept.

Referring toFIG. 21, a memory system4100comprises a CPU4110, a synchronous DRAM (SDRAM)4120, and a SCM4130. SCM4130can be used as a data storage memory in place of a flash memory.

SCM4130has fast data access speed compared with a flash memory. For example, in a PC environment where CPU4110operates at 4 GHz, a phase change memory device, which is one type of SCM4130, can have an access speed 32 times as fast as a flash memory. Thus, memory system4100comprising SCM4130has a performance advantage compared with a memory system comprising a flash memory.

FIG. 22is a block diagram illustrating a memory system comprising a variable resistance memory device according to an embodiment of the inventive concept.

Referring toFIG. 22, a memory system4200comprises a CPU4210, an SCM4220, and a flash memory4230. In this example, SCM4220is used as a main memory in place of an SDRAM.

SCM4220has low power consumption compared with a SDRAM. Because main memory consumes a significant amount of the total power in many electronic systems, a significant amount of research is being conducted to reduce power consumption in main memories. Compared with certain DRAMs, SCM4220can reduce dynamic energy consumption by an average of 53% and energy consumption due to power loss by an average of 73%. Consequently, a memory system comprising SCM4220can reduce power consumption compared with a memory system loaded with an SDRAM.

FIG. 23is a block diagram illustrating a memory system comprising a variable resistance memory device according to an embodiment of the inventive concept.

Referring toFIG. 23, a memory system4300comprises a CPU4310and an SCM4320. SCM4320can be used as a main memory in place of an SDRAM and can be used for mass data storage memory in place of a flash memory. Memory system4300can provide various benefits, such as relatively efficient data access, power consumption, and space utilization, and reduced cost.

The above described devices and systems can be mounted by various types of packages, such as package on package (PoP), ball grid array (BGA), chip scale package (CSP), plastic leaded chip carrier (PLCC), plastic dual in-line package (PDIP), die in waffle pack, die in wafer form, chip on board (COB), ceramic dual in-line package (CERDIP), plastic metric quad flat pack (MQFP), small outline (SOIC), shrink small outline package (SSOP), thin small outline (TSOP), thin quad flatpack (TQFP), system in package (SIP), multi chip package (MCP), wafer-level fabricated package (WFP) and wafer-level processed stack package (WSP).

As indicated by the foregoing, various embodiments of the inventive concept can improve the reliability of data stored in a variable resistance memory device by preventing variable resistance memory cells from assuming unstable states. Certain embodiments can also reduce power consumption and improve the lifespan of variable resistance memory devices by reducing the amount of current that flows through the devices.

The foregoing is illustrative of embodiments and is not to be construed as limiting thereof. Although a few embodiments have been described, those skilled in the art will readily appreciate that many modifications are possible in the embodiments without materially departing from the novel teachings and advantages of the inventive concept. Accordingly, all such modifications are intended to be included within the scope of the inventive concept as defined in the claims.