Memory interface design having controllable internal and external interfaces for bypassing defective memory

An improved memory interface design is provided. In some implementations, an integrated circuit includes a first cache memory unit, a second cache memory unit located in parallel with the first cache memory unit, and a floorsweeping module configured to be able to select between the first cache memory unit and the second cache memory unit for cache requests, wherein the selection is based at least partially on the presence or absence of one or more manufacturing defects in the first cache memory unit or the second cache memory unit.

BACKGROUND

This application relates generally to electronic circuitry and more particularly to processor memory architectures and interfaces. Integrated circuits are created through a process known as semiconductor device manufacture. Semiconductor device manufacturing is a multi-step manufacturing sequence using a variety of chemical, physical, and photolithographic processing steps. As semiconductor manufacturing technology has improved, the complexity of the processing steps has increased and the feature size used on the integrated circuits has decreased. As complexity increases and feature size decreases, the number of manufacturing defects on a given integrated circuit tends to increase. The proportion of integrated circuits on a production wafer that perform properly is referred to as the yield. To the extent that a manufacturing defect causes one or more integrated circuits on a production wafer to be partially or fully non-functional, that defect adversely affects the yield. As the yield for a semiconductor production process decreases, the cost per manufactured integrated circuit increases. Techniques that increase the semiconductor production process yield are desirable.

SUMMARY

In some implementations, there is provided an integrated circuit including a first cache memory unit, a second cache memory unit located in parallel with the first cache memory unit; and a floorsweeping module configured to be able to select between one or both of the first cache memory unit and the second cache memory unit for cache requests, wherein the selection is based at least partially on the presence or absence of one or more manufacturing defects in the first cache memory unit or the second cache memory unit.

Some implementations include a defect indicator coupled to the floorsweeping module and configured to indicate the presence or absence of the one or more manufacturing defects. The defect indicator may include a plurality of production fuses. The integrated circuit may also include a graphics processing unit. The integrated circuit may also include a memory interface coupled to the first cache memory unit and the second cache memory unit. In some implementations, the memory interface may include a random access memory interface configured to communicate with a random access memory external to the integrated circuit. The integrated circuit may also include a processing core coupled to the first cache unit or the second cache unit. The first cache unit and the second cache unit may be a raster operation pipeline module. Some implementations may also include clamping circuitry capable of clamping the output of a defective cache memory unit.

Some implementations may include a method of manufacturing including first fabricating a first memory storage cluster; then fabricating a second memory storage cluster, and then fabricating selection circuitry coupled to the first memory storage cluster and the second memory storage cluster, wherein the selection circuitry is configured to be able to bypass the first memory storage cluster or the second memory cluster based on one or more indicators of a manufacturing defect. Some implementations of this aspect include corresponding computer systems, apparatus, and computer programs recorded on one or more computer storage devices, each configured to perform the actions of the methods.

Some implementations of this method may include fabricating defect indication circuitry coupled to the selection circuitry, wherein the defect indication circuitry is configured to indicate the presence of the manufacturing defect. In some implementations, fabricating the defect indication circuitry includes fabricating one or more production fuses that indicate the presence of a defect. Fabricating the first memory storage cluster may also include fabricating a cache memory. Fabricating the first memory storage cluster may include fabricating an operational unit coupled to the cache memory. Fabricating may also include fabricating an operational unit that includes a computational unit capable of graphical display calculations.

Some implementations include a system having at least two independently selectable memory clusters and an interface circuit coupled to the two independently selectable memory clusters, wherein the interface circuit is configurable to route memory requests to at least one of the memory clusters based at least partially on a defect indicator associated with one or more of the independently selectable memory clusters. Some implementations of this aspect include multiplexor circuitry coupled to the memory clusters. The two independently selectable memory clusters may also include a cache memory. The two independently selectable memory clusters can include a raster operations pipeline module. Implementations may further include one or more external storage units coupled to the interface circuit the one or more external storage units includes dynamic random access memory.

DETAILED DESCRIPTION

In a typical semiconductor manufacturing process, some percentage of manufactured integrated circuits will have manufacturing defects. A manufacturing defect within a particular portion or region of an integrated circuit can render that portion or region or, in fact, the entire integrated circuit non-functional. A non-functional integrated circuit reduces the yield from the semiconductor manufacturing process and increases the cost of both the process and the cost of each functional integrated circuit. Accordingly, it is desirable to reduce the number and frequency of defects and to develop techniques to reclaim or otherwise make functional integrated circuits that have manufacturing defects.

One technique for increasing semiconductor manufacturing yield is known as “floorsweeping.” “Floorsweeping” is a process or technique by which manufacturing defects or other errors present in integrated circuits can be disabled and/or bypassed such that the integrated circuit maintains either some or all of its designed functionality. A floorsweeping module includes circuitry that is able to implement floorsweeping on an integrated circuit. One or more of the examples set forth below advantageously enables an integrated circuit, such as a GPU or CPU, to maintain a consistently sized external memory interface despite one or more manufacturing defects within a memory cluster on an integrated circuit.

FIG. 1depicts a block diagram of an example system10, in accordance with implementations of the present disclosure. In some implementations, the system10may include an integrated circuit12and one or more external storage devices14. In some implementations, the integrated circuit12may include a graphics processor or graphics processing unit (“GPU”). In some implementations, the integrated circuit12may include multiple processing units. In some implementations, the integrated circuit includes a plurality of shader modules and/or rasterization modules.

In still other implementations, the integrated circuit12may be a general purpose processor, such as a CPU, or another form of specialized processor or processing unit, such as an application specific integrated circuit (“ASIC”). While the integrated circuit12is depicted inFIG. 1as including various subcomponents, it will be appreciated that the depiction ofFIG. 1is an example and in various implementations, additional or alternative circuit structures and components may be employed. For example, in some implementations, the integrated circuit12may include additional structures not depicted inFIG. 1. The integrated circuit12may also include multiple separate integrated circuits or components electrically coupled together.

The processing unit16may include one or more circuit components capable of processing instructions or data. For example, in one implementation, the processing unit includes one or more GPU or CPU cores. The processing unit16may also include one or more microprocessors. In various implementations, the processing unit16is able to execute one or more threads as part of a multi-thread computing system. The processing unit16may include an internal memory or cache such as a Level 1 (“L1”) cache.

Processing unit16may be coupled (“electrically connected either directly or indirectly”) to one or more internal interfaces18via a bus20. The internal interface18may provide an interface and communication path between the processing unit16and storage and/or additional computational resources on the integrated circuit12. In some implementations, the internal interface may include one or more than one switch, such as a crossbar switch. For example, the internal interface18may include main crossbar or a control signal crossbar for the integrated circuit12. An example internal interface18is described in greater detail in relation toFIG. 4. While the internal interface18is depicted inFIG. 1as two distinct boxes, this depiction is representative. In some implementations, for example, the internal interface may include a single crossbar fabric coupled to multiple groups of memory clusters22a-22n.

The bus20includes an electrical connection, either direct or indirect, between the processing unit16and the internal interface18. In various implementations, the bus20, like the other buses described below, may consist of a given number of parallel electrical pathways within the integrated circuit. Typical bus widths range from 8 bits to 128 bits, but any size bus may be selected including a single bit serial connection. In some implementations, the bus18may not be required. For example, a bus20may not be employed where the internal interface18includes a crossbar switch.

As shown inFIG. 1, the internal interface18may couple the processing unit16to a plurality of memory clusters22a-22nvia a bus24. As described in greater detail below in regard toFIG. 2, the memory clusters22a-22nmay include one or more memories, such as the cache memory, and/or one or more functional or operational components. In some implementations, the memory clusters22a-22ninclude a Level 2 (“L2”) cache capable of being used in conjunction with the processing unit16. The memory clusters22a-22nmay be arrayed in parallel electrically such that one or more of the memory clusters22a-22nmay be interfaced independently by the components of the integrated circuit12. For example, the internal interface18may be configured to access one or more of the memory clusters22a-22nwhile not accessing one or more other memory cluster22a-22n.

The memory clusters22a-22nmay be coupled to one or more external memory interfaces26via a bus28. As described in greater detail below with regard toFIG. 3, the external memory interfaces26may couple the integrated circuit12(and thus the processing unit16) to one or more of the external storage devices14a-14nvia the buses30a-30n. In various implementations, the buses30a-30nmay include one or more external contact pins or bumps that electrically carry electrical signals between the integrated circuit12and the external storage devices14a-14n. In some implementations, each of the buses30a-30nincludes a 64 bit DRAM bus, and the integrated circuit12includes four buses30(each coupled to a plurality of memory clusters22a-22n) for a total DRAM bus width of 256 bits. Advantageously, some implementations enable floorsweeping of the memory clusters22a-22nto enable the integrated circuit12to maintain the 256-bit DRAM bus width despite one or more manufacturing defects within the memory clusters22a-22n. In the way, some implementations are able to maintain a full bandwidth memory interface despite manufacturing errors that previously could reduce the bandwidth and/or memory capacity of an integrated circuit. In various other implementations, other bus widths or bus numbers may employed depending on the input/output requirements of the external storage device14.

External storages14a-14nmay include any form of physical device that is capable of storing programs or data on a temporary or permanent basis. In some implementations, the external storage14includes a random access memory, such as a dynamic random access memory (“DRAM”). In some implementations, other suitable forms of memory may be used, including SRAM, EEPROM, and/or flash memory. In some implementations, the external storages14a-14nincludes computer memory that is used as a frame buffer by the processing unit16and/or the integrated circuit12.

The integrated circuit12may also include a defect indicator32. The defect indicator32provides an indication of one or more defective or partially defective memory clusters22. In some implementations, the defect indicator32may include one or more fuses that may be blown during manufacture or testing of the integrated circuit12to indicate the presence of defects within one or more of the memory clusters22. In some implementations, the defect indicator32may include another form of indicative circuitry, such as one or more registers and/or a computer memory, such as a read-only memory (“ROM”), configured to store an indicator of one or more defective memory clusters22.

FIG. 2depicts a block diagram of an example memory cluster22in accordance with example implementations of the present disclosure. In some implementations, the memory cluster22may include an operational component40and an L2 cache component42. In some implementations, the operational component40or the L2 cache component42may be absent. For example, the memory cluster22in some implementations may not include the operational component40or may not include the L2 cache component42. Accordingly, the name “memory cluster” is not intended indicate a requirement that a memory be included within the memory cluster22a-22nalthough the L2 memory included in the memory cluster22ofFIG. 2.

The L2 cache42may include any form of semiconductor cache or semiconductor memory. As noted above, in various implementations, the L2 cache42includes an L2 cache for the processing unit16. In various implementations, the L2 cache is configured to perform a caching function for external memory. As shown, the L2 cache42may be coupled to the external memory interface26via the bus28. In some implementations, the L2 cache42may be replaced with or used in conjunction with another type of cache memory and/or another form of semiconductor computer memory.

The operational component40may include processing or computational circuitry that may receive instructions or assignments from the processing unit16. In some implementations, the operational component40includes a raster operations pipeline (“ROP”) module. The ROP module may be configured to process picture elements (“pixel”) and or texture elements (“texel”). For example, in some implementations, the operational component40may include a ROP configured to calculate pixel color and/or pixel depth values. In some implementations, the operational component40may include a cache controller.

FIG. 3shows the example external memory interface26, in accordance with example implementations of the present disclosure. The external memory interface26may include a multiplexer (“MUX”)50, a bus interface52, and cluster selection circuitry56. MUX50includes circuitry that is able to select one of several inputs or outputs and forward signals on those inputs or outputs into a single input or output. For example, in the external memory interface26, the example MUX50is able to receive signals from memory clusters22a-22nover buses28a-28n, and forward select signals from one or more of the memory clusters22a-22nto bus30. Conversely, the MUX50is able to receive signals over bus54and forward those signals to one or more of the memory clusters22a-22nover one or more of buses28a-28n. In this way, the MUX50may enable a single bus interface52to communicate with multiple memory clusters22a-22n. In some implementations, the MUX50may be replaced or supplemented by any suitable form of multiple input single output and/or multiple output single input switching. For example, in various implementations, the MUX50may be replaced by a 2-to-1 switch, an n-to-1 switch, a crossbar switch, a cross-point switch, a matrix switch, a rotary switch, and/or a crossover switch.

The MUX50may be coupled to cluster selection circuitry56. The cluster selection circuitry56may be configured to control the operation of the MUX50using one or more control signals. In this way, the cluster selection circuitry may be configured to direct the MUX50to couple the bus interface52to one or more of the buses28a-28n. For example, in some implementations, the cluster selection circuitry56may be configured to instruct the MUX50to couple the bus interface52to buses28a-28nwhich are connected to functional memory clusters28a-28nand to not couple the bus interface52to buses28a-28nthat are coupled to memory clusters that are non-functional. In further example, in some implementations having two memory clusters22aand22bcoupled to each external memory interface26and where one example memory cluster22bhas a defect rendering it non-functional, the cluster selection circuitry56may be configured to instruct the MUX50to couple the bus interface52only to the memory cluster22a. In this way, the presence of a manufacturing defect within memory cluster22bdoes not render the external memory interface26non-functional and the integrated circuit's external memory bandwidth is not degraded by the presence of the manufacturing defect within memory cluster22b.

The cluster selection circuitry56may be coupled to the defect indicator32. As described above, the cluster selection circuitry56may be configured to access the defect indicator32to determine which memory clusters22a-22n—if any—have manufacturing or other defects. In some implementations, the cluster selection circuitry56may employ other suitable techniques to determine which—if any—of the memory clusters22a-22nare non-functional.

In some implementations, the external interface26and/or the cluster selection circuitry may not be coupled to the defect indicator32. For example, as described further below, the internal interface18may be configured to bypass a defective memory cluster22a-22nby avoiding use of physical memory addresses located with the defective memory cluster. In such implementations, the external interface26would bypass the defective memory cluster22a-22nautomatically since no memory requests to that memory cluster would be generated.

The external memory interface26may also include a bus interface52, which is circuitry configured to couple the external memory interface and thus the integrated circuit12to the external storage14. In various implementations, the bus interface52may include input/output buffers, input/output drivers, termination circuitry. The bus interface52may be coupled to one or more external pins or bumps that make up the bus30. In some implementations, the external memory interface26may also include clamping circuitry capable of clamping the output from any of the memory clusters22a-22ndetermined to be defective. In some implementations, the clamping circuitry may be located elsewhere on the integrated circuit12.

The example cluster selection circuitry56may be configured to perform the example flow70set forth inFIG. 4. For example, as indicated by block72ofFIG. 4, the cluster selection circuitry56may be configured to determine one or more defective memory clusters. In some implementations, the cluster selection circuitry may be configured to determine defective memory clusters by accessing the defect indicator32. For example, the cluster selection circuitry may be configured to determine the state of one or more fuses that indicate whether one or more of the memory clusters22a-22nare defective. In still other implementations, determining the defective memory clusters as set forth in block72may involve reading or accessing another suitable indicator or storage device, such as registers or a semiconductor memory.

After determining the defective memory clusters, the flow70may include disabling access to defective memory clusters. For example, in some implementations, as described above, the cluster selection circuitry56may be configured to instruct the MUX50to disable access or stop access to and from the bus interface52for any buses28a-28nthat are coupled to memory clusters22a-22nthat are defective and/or non-functional. In some implementations, the cluster selection circuitry may be configured to disable access to the defective memory clusters by excluding the addresses within the defective memory clusters from the addressable address space. In such implementations, the defective memory clusters would be logically disabled as no memory transactions would be initiated for the memory within the defective memory cluster.

After disabling access to the defective memory clusters, the flow70next includes receiving a memory transaction from the external storages14a-14nover the bus30. In some implementations, receiving a memory transaction may include receiving stored data or instructions to be loaded into the L2 cache42within the memory cluster22a-22n.

After receiving the memory transaction, the flow70next includes routing memory transactions to one or more operative memory clusters22a-22nwithin the integrated circuit12. For example, if the external memory interface26is coupled to memory clusters22aand22bbut access to memory cluster22bwas disabled due to a defect within memory cluster22b, step78may include routing the memory transaction received from the external storage14athrough the MUX50to memory cluster22a. If multiple memory clusters22athough22nare functional, the cluster selection circuitry56and the MUX50may route the memory transaction to any of the functional memory clusters22a-22nor may employ any one of a number of memory preference or caching algorithms to determine which of multiple functional memory clusters22a-22nto route the memory transaction.

Turning next toFIG. 5, an example internal interface18in accordance with example implementations of the present disclosure is shown. The internal interface18may include a MUX50, cluster selection circuitry56, and a bus interface90. The MUX50and the cluster selection circuitry shown inFIG. 5operate substantially similar to the MUX50and the cluster selection circuitry56described above in relation toFIG. 3, except that the MUX50and cluster selection circuitry56control the interface between the processing unit16via the bus interface90and the memory clusters22a-22nrather than the connection between the external storage14and the memory clusters22a-22n. As with the cluster selection circuitry56described above in relation toFIG. 3, the cluster selection circuitry56shown inFIG. 5may be configured to execute the flow70depicted inFIG. 4. For example, the cluster selection circuitry56may be configured to: (a) determine defective memory clusters, (b) disable access to those defective memory clusters through commands sent to the MUX50, (c) receive memory transactions from bus interface90, such as memory reads or writes and/or data, and (d) to route those memory transactions to operative memory clusters22a-22n. In addition, the internal interface18may be configured to receive memory transactions from one or more of the memory clusters22a-22nover the buses24athrough24nand to communicate those memory transactions to the processing unit16over the bus20.

In some implementations, the cluster selection circuitry56and/or the internal interface18may be configured to disable access to the defective memory clusters22a-22nby excluding memory locations within the defective memory clusters from the address space addressable by the processing unit16and/or the internal interface18. While the defective memory cluster22a-22nmay remain physically connected to the internal interface18and/or the external interface26, memory transactions would not be routed to it. In this way, a defective memory can also be logically disabled by the integrated circuit12.

Turning next toFIG. 6, another example system100in accordance with example implementations of the present disclosure is shown. The system100may include an integrated circuit102, which may include a processing unit16that is coupled to memory clusters22a-22nvia one or more internal interfaces104athrough104ndescribed above in relation toFIGS. 1 and 5. However, unlike the implementation shown inFIG. 1, the internal interfaces104athrough104nare coupled to a single memory cluster22a-22n, respectively. Each memory cluster22a-22nmay be correspondingly coupled to multiple MUXs50a-50nand60a-60n. For example, in some implementations, an output from the memory cluster22amay be coupled to MUX50aand50nand the input to memory cluster22amay be coupled to MUX60a.

The MUXs50a-50nand60a-60nmay be coupled to one or more external memory interfaces106a-106n. For example, the external memory interface106amay have an input coupled to the MUX50aand its output coupled to the MUX60aand the MUX60n. As also shown inFIG. 6, each of the MUXs50a-50nand60a-60nmay receive one or more control signals enabling them to select one or more input signals to forward to memory clusters22a-22nand/or the external memory interfaces106a-106n. In some implementations, the control signal may be provided by selection circuitry, such as the cluster selection circuitry56described in regards toFIGS. 3 and 5, based on a defect indicator (not shown inFIG. 6).

As shown inFIG. 6, the external memory interfaces106a-106nare each coupled to external storages14a-14n. The system100may be configured to activate the MUXs50a-50nto selectively transmit memory transactions between the processing units16/the memory clusters22a-22nand the external storages14. In this way, the MUXs50a-50nand60a-60nand the associated control circuitry may be configured to transmit signals from more than one external memory interface106a-106nto a single memory cluster22a-22nin the event of a defect within one or more of the memory clusters22a-22n. For example, in the example system100, if the memory cluster22nis defective, the system100may be configured to control50a-50nand60a-60nsuch that memory transactions to and from both external storages14a-14nare routed through the memory cluster22a. In particular, the system100may disable50nand60nsuch that memory transactions from both external memory interface106aand external memory interface106nare routed through MUXs50aand60aand access memory cluster22a. In this way, the system100is able to maintain two active bus connections (and a corresponding external bus width) to external storages14even when memory cluster22nis defective.

FIG. 7depicts an example computing system200for implementing the integrated circuits10and/or the integrated circuit102. Of course, the integrated circuits12and102may be implemented in any desired environment. As shown, the system200includes at least one CPU201which is connected to a communication bus202. The system200also includes main memory204(for example, the storage device14). The system200also includes a graphics processor206and a display208. In some implementations, the graphics processor206may be the integrated circuit12or102. Additionally, in some implementations, the architecture and/or functionality of the various previous figures may be implemented on a system on chip or other integrated solution. For example, a CPU and GPU may be located on one integrated circuit. In some implementations, the graphics processor206may include a plurality of shader modules and/or rasterization modules. Each of the foregoing modules may even be situated on a single semiconductor.

The system200may also include a secondary storage210. The secondary storage910includes, for example, a hard disk drive and/or a removable storage drive, representing a solid state drive, a magnetic tape drive, a compact disk drive, etc. The removable storage drive reads from and/or writes to a removable storage unit in a well-known manner.

Computer programs, firmware, or computer control logic algorithms, may be stored in the main memory204and/or the secondary storage210. Such computer programs, when executed, enable the system200to perform various functions. Memory204, storage210and/or any other storage are possible examples of computer-readable media. In some implementations, the stored computer programs, firmware, or computer control logic algorithms may be configured such that when executed they perform the flow70.

In some implementations, the architecture and/or functionality of the various previous figures may be implemented in the context of the CPU201, graphics processor206, a chipset (for example, a group of integrated circuits designed to work and sold as a unit for performing related functions, etc.), and/or any other integrated circuit for that matter.

Still yet, the architecture and/or functionality of the various previous figures may be implemented in the context of a general computer system, a circuit board system, a game console system dedicated for entertainment purposes, an application-specific system, a mobile system, and/or any other desired system, for that matter. Just by way of example, the systems10,100, or200may include a desktop computer, lap-top computer, hand-held computer, mobile phone, personal digital assistant (PDA), peripheral (e.g. printer, etc.), any component of a computer, and/or any other type of logic. The architecture and/or functionality of the various previous figures and description may also be implemented in the form of a chip layout design, such as a semiconductor intellectual property (“IP”) core. Such an IP core may take any suitable form, including synthesizable RTL, Verilog, or VHDL, netlists, analog/digital logic files, GDS files, mask files, or a combination of one or more forms.