Fan-out semiconductor package

A fan-out semiconductor package includes: a semiconductor chip; an encapsulant encapsulating at least portions of the semiconductor chip; and a first connection member disposed on an active surface of the semiconductor chip and including a redistribution layer electrically connected to the connection pads of the semiconductor chip. The redistribution layer includes a line pattern having a first line portion having a first line width and a second line portion connected to the first line portion and having a second line width, greater than the first line width, a fan-in region is a projected surface of the semiconductor chip projected in a direction perpendicular to the active surface, a fan-out region is a region surrounding the fan-in region, and the second line portion at least passes through a boundary between the fan-in region and the fan-out region.

CROSS-REFERENCE TO RELATED APPLICATION(S)

This application claims benefit of priority to Korean Patent Application No. 10-2017-0023063 filed on Feb. 21, 2017 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety.

TECHNICAL FIELD

The present disclosure relates to a semiconductor package, and more particularly, to a fan-out semiconductor package in which connection terminals may extend outwardly of a region in which a semiconductor chip is disposed.

BACKGROUND

Recently, a significant recent trend in the development of technology related to semiconductor chips has been to reduce the size of semiconductor chips. Therefore, in the field of package technology, in accordance with a rapid increase in demand for small-sized semiconductor chips, or the like, the implementation of a semiconductor package having a compact size while including a plurality of pins has been demanded.

One type of package technology suggested to satisfy the technical demand as described above is a fan-out package. Such a fan-out package has a compact size and may allow a plurality of pins to be implemented by redistributing connection terminals outwardly of a region in which a semiconductor chip is disposed.

SUMMARY

An aspect of the present disclosure may provide a fan-out semiconductor package of which board level reliability is excellent.

According to an aspect of the present disclosure, a fan-out semiconductor package may be provided, in which a redistribution layer in a region in which board level reliability stress of the fan-out semiconductor package is concentrated is enhanced.

According to an aspect of the present disclosure, a fan-out semiconductor package may include: a semiconductor chip having an active surface having connection pads disposed thereon and an inactive surface opposing the active surface; an encapsulant encapsulating at least portions of the semiconductor chip; and a first connection member disposed on the active surface of the semiconductor chip and including a redistribution layer electrically connected to the connection pads of the semiconductor chip. The redistribution layer includes a line pattern having a first line portion having a first line width and a second line portion connected to the first line portion and having a second line width, greater than the first line width, a fan-in region is a projected surface of the semiconductor chip projected in a direction perpendicular to the active surface, a fan-out region is a region surrounding the fan-in region and the second line portion at least passes through a boundary between the fan-in region and the fan-out region.

According to another aspect of the present disclosure, a fan-out semiconductor package may include: a first connection member having a through-hole; a semiconductor chip disposed in the through-hole of the first connection member and having an active surface having connection pads disposed thereon and an inactive surface opposing the active surface; an encapsulant encapsulating at least portions of the first connection member and the semiconductor chip; and a second connection member disposed on the first connection member and the active surface of the semiconductor chip and including a redistribution layer electrically connected to the connection pads of the semiconductor chip. The redistribution layer includes a line pattern having a first line portion having a first line width and a second line portion connected to the first line portion and having a second line width, greater than the first line width, region R1is a projected surface of the semiconductor chip projected in a direction perpendicular to the active surface of the semiconductor chip onto one plane region in which the redistribution layer of the second connection member is formed, region R2is a projected surface of the first connection member projected in the direction perpendicular to the active surface of the semiconductor chip onto the one plane region, region R3is a projected surface of a portion of the through-hole between the semiconductor chip and the second connection member projected in the direction perpendicular to the active surface of the semiconductor chip onto the one plane region, and at least portions of the second line portion of the line pattern overlap region R3.

DETAILED DESCRIPTION

Hereinafter, exemplary embodiments in the present disclosure will be described with reference to the accompanying drawings. In the accompanying drawings, shapes, sizes, and the like, of components may be exaggerated or shortened for clarity.

Herein, a lower side, a lower portion, a lower surface, and the like, are used to refer to a direction toward a mounting surface of the fan-out semiconductor package in relation to cross sections of the drawings, while an upper side, an upper portion, an upper surface, and the like, are used to refer to a direction opposite to the direction toward a mounting surface. However, these directions are defined for convenience of explanation, and the claims are not particularly limited by the directions defined as described above.

The term “an exemplary embodiment” used herein does not refer to the same exemplary embodiment, and is provided to emphasize a particular feature or characteristic different from that of another exemplary embodiment. However, exemplary embodiments provided herein are considered to be able to be implemented by being combined in whole or in part one with another. For example, one element described in a particular exemplary embodiment, even if it is not described in another exemplary embodiment, may be understood as a description related to another exemplary embodiment, unless an opposite or contradictory description is provided therein.

Terms used herein are used only in order to describe an exemplary embodiment rather than limiting the present disclosure. In this case, singular forms include plural forms unless interpreted otherwise in context.

Electronic Device

Referring toFIG. 1, an electronic device1000may accommodate a motherboard1010therein. The motherboard1010may include chip related components1020, network related components1030, other components1040, and the like, physically or electrically connected thereto. These components may be connected to others to be described below to form various signal lines1090.

FIG. 2is a schematic perspective view illustrating an example of an electronic device.

Referring toFIG. 2, a semiconductor package may be used for various purposes in the various electronic devices1000as described above. For example, a main board1110may be accommodated in a body1101of a smartphone1100, and various electronic components1120may be physically or electrically connected to the main board1110. In addition, other components that may or may not be physically or electrically connected to the main board1110, such as a camera module1130, may be accommodated in the body1101. Some of the electronic components1120may be the chip related components, and the semiconductor package100may be, for example, an application processor among the chip related components, but is not limited thereto. The electronic device is not necessarily limited to the smartphone1100, but may be other electronic devices as described above.

Semiconductor Package

Generally, numerous fine electrical circuits are integrated in a semiconductor chip. However, the semiconductor chip may not serve as a finished semiconductor product in itself, and may be damaged due to external physical or chemical impacts. Therefore, the semiconductor chip itself may not be used, but may be packaged and used in an electronic device, or the like, in a packaged state.

Here, semiconductor packaging is required due to a difference in a circuit width between the semiconductor chip and a main board of the electronic device in terms of electrical connections. In detail, a size of connection pads of the semiconductor chip and an interval between the connection pads of the semiconductor chip are very fine, but a size of component mounting pads of the main board used in the electronic device and an interval between the component mounting pads of the main board are significantly larger than those of the semiconductor chip. Therefore, it may be difficult to directly mount the semiconductor chip on the main board, and packaging technology for buffering a difference in a circuit width between the semiconductor chip and the main board is required.

A semiconductor package manufactured by the packaging technology may be classified as a fan-in semiconductor package or a fan-out semiconductor package depending on a structure and a purpose thereof.

The fan-in semiconductor package and the fan-out semiconductor package will hereinafter be described in more detail with reference to the drawings.

Fan-in Semiconductor Package

FIGS. 3A and 3Bare schematic cross-sectional views illustrating states of a fan-in semiconductor package before and after being packaged.

FIG. 4is schematic cross-sectional views illustrating a packaging process of a fan-in semiconductor package.

Referring to the drawings, a semiconductor chip2220may be, for example, an integrated circuit (IC) in a bare state, including a body2221including silicon (Si), germanium (Ge), gallium arsenide (GaAs), or the like, connection pads2222formed on one surface of the body2221and including a conductive material such as aluminum (Al), or the like, and a passivation layer2223such as an oxide film, a nitride film, or the like, formed on one surface of the body2221and covering at least portions of the connection pads2222. In this case, since the connection pads2222are significantly small, it is difficult to mount the integrated circuit (IC) on an intermediate level printed circuit board (PCB) as well as on the main board of the electronic device, or the like.

Therefore, a connection member2240may be formed depending on a size of the semiconductor chip2220on the semiconductor chip2220in order to redistribute the connection pads2222. The connection member2240may be formed by forming an insulating layer2241on the semiconductor chip2220using an insulating material such as a photoimagable dielectric (PID) resin, forming via holes2243hopening the connection pads2222, and then forming wiring patterns2242and vias2243. Then, a passivation layer2250protecting the connection member2240may be formed, an opening2251may be formed, and an underbump metal layer2260, or the like, may be formed. That is, a fan-in semiconductor package2200including, for example, the semiconductor chip2220, the connection member2240, the passivation layer2250, and the underbump metal layer2260may be manufactured through a series of processes.

As described above, the fan-in semiconductor package may have a package form in which all of the connection pads, for example, input/output (I/O) terminals, of the semiconductor chip are disposed inside the semiconductor chip, and may have excellent electrical characteristics and be produced at a low cost. Therefore, many elements mounted in smartphones have been manufactured in a fan-in semiconductor package form. In detail, many elements mounted in smartphones have been developed to implement a rapid signal transfer while having a compact size.

However, since all I/O terminals need to be disposed inside the semiconductor chip in the fan-in semiconductor package, the fan-in semiconductor package has a large spatial limitation. Therefore, it is difficult to apply this structure to a semiconductor chip having a large number of I/O terminals or a semiconductor chip having a compact size. In addition, due to the disadvantage described above, the fan-in semiconductor package may not be directly mounted and used on the main board of the electronic device. Here, even in a case that a size of the I/O terminals of the semiconductor chip and an interval between the I/O terminals of the semiconductor chip are increased by a redistribution process, the size of the I/O terminals of the semiconductor chip and the interval between the I/O terminals of the semiconductor chip may not be sufficient to directly mount the fan-in semiconductor package on the main board of the electronic device.

FIG. 5is a schematic cross-sectional view illustrating a case in which a fan-in semiconductor package is mounted on an interposer substrate and is ultimately mounted on a main board of an electronic device.

FIG. 6is a schematic cross-sectional view illustrating a case in which a fan-in semiconductor package is embedded in an interposer substrate and is ultimately mounted on a main board of an electronic device.

Referring to the drawings, in a fan-in semiconductor package2200, connection pads2222, that is, I/O terminals, of a semiconductor chip2220may be redistributed through an interposer substrate2301, and the fan-in semiconductor package2200may be ultimately mounted on a main board2500of an electronic device in a state in which it is mounted on the interposer substrate2301. In this case, solder balls2270, and the like, may be fixed by an underfill resin2280, or the like, and an external surface of the semiconductor chip2220may be covered with a molding material2290, or the like. Alternatively, a fan-in semiconductor package2200may be embedded in a separate interposer substrate2302, connection pads2222, that is, I/O terminals, of the semiconductor chip2220may be redistributed by the interposer substrate2302in a state in which the fan-in semiconductor package2200is embedded in the interposer substrate2302, and the fan-in semiconductor package2200may be ultimately mounted on a main board2500of an electronic device.

As described above, it may be difficult to directly mount and use the fan-in semiconductor package on the main board of the electronic device. Therefore, the fan-in semiconductor package may be mounted on the separate interposer substrate and be then mounted on the main board of the electronic device through a packaging process or may be mounted and used on the main board of the electronic device in a state in which it is embedded in the interposer substrate.

Fan-out Semiconductor Package

Referring to the drawing, in a fan-out semiconductor package2100, for example, an external surface of a semiconductor chip2120may be protected by an encapsulant2130, and connection pads2122of the semiconductor chip2120may be redistributed outwardly of the semiconductor chip2120by a connection member2140. In this case, a passivation layer2150may be further formed on the connection member2140, and an underbump metal layer2160may be further formed in openings of the passivation layer2150. Solder balls2170may be further formed on the underbump metal layer2160. The semiconductor chip2120may be an integrated circuit (IC) including a body2121, the connection pads2122, a passivation layer (not illustrated), and the like. The connection member2140may include an insulating layer2141, redistribution layers2142formed on the insulating layer2141, and vias2143electrically connecting the connection pads2122and the redistribution layers2142to each other.

As described above, the fan-out semiconductor package may have a form in which I/O terminals of the semiconductor chip are redistributed and disposed outwardly of the semiconductor chip through the connection member formed on the semiconductor chip. As described above, in the fan-in semiconductor package, all I/O terminals of the semiconductor chip need to be disposed inside the semiconductor chip. Therefore, when a size of the semiconductor chip is decreased, a size and a pitch of balls need to be decreased, such that a standardized ball layout may not be used in the fan-in semiconductor package. On the other hand, the fan-out semiconductor package has the form in which the I/O terminals of the semiconductor chip are redistributed and disposed outwardly of the semiconductor chip through the connection member formed on the semiconductor chip as described above. Therefore, even in a case that a size of the semiconductor chip is decreased, a standardized ball layout may be used in the fan-out semiconductor package as it is, such that the fan-out semiconductor package may be mounted on the main board of the electronic device without using a separate interposer substrate, as described below.

FIG. 8is a schematic cross-sectional view illustrating a case in which a fan-out semiconductor package is mounted on a main board of an electronic device.

Referring to the drawing, a fan-out semiconductor package2100may be mounted on a main board2500of an electronic device through solder balls2170, or the like. That is, as described above, the fan-out semiconductor package2100includes the connection member2140formed on the semiconductor chip2120and capable of redistributing the connection pads2122to a fan-out region outside of a size of the semiconductor chip2120, such that the standardized ball layout may be used in the fan-out semiconductor package2100as it is. As a result, the fan-out semiconductor package2100may be mounted on the main board2500of the electronic device without using a separate interposer substrate, or the like.

As described above, since the fan-out semiconductor package may be mounted on the main board of the electronic device without using the separate interposer substrate, the fan-out semiconductor package may be implemented at a thickness lower than that of the fan-in semiconductor package using the interposer substrate. Therefore, the fan-out semiconductor package may be miniaturized and thinned. In addition, the fan-out semiconductor package has excellent thermal characteristics and electrical characteristics, such that it is particularly appropriate for a mobile product. Therefore, the fan-out semiconductor package may be implemented in a form more compact than that of a general package-on-package (POP) type using a printed circuit board (PCB), and may solve a problem due to the occurrence of a warpage phenomenon.

Meanwhile, the fan-out semiconductor package refers to a package technology for mounting the semiconductor chip on the main board of the electronic device, or the like, as described above, and protecting the semiconductor chip from external impacts, and is a concept different from that of a printed circuit board (PCB) such as an interposer substrate, or the like, having a scale, a purpose, and the like, different from those of the fan-out semiconductor package, and having the fan-in semiconductor package embedded therein.

A fan-out semiconductor package of which board level reliability is excellent will hereinafter be described with reference to the drawings.

FIG. 9is a schematic cross-sectional view illustrating an example of a fan-out semiconductor package.

FIG. 10is a schematic plan view illustrating a redistribution layer region ofFIG. 9.

Referring to the drawings, a fan-out semiconductor package100A according to an exemplary embodiment in the present disclosure may include a first connection member110having a through-hole110H, a semiconductor chip120disposed in the through-hole110H of the first connection member110and having an active surface having connection pads122disposed thereon and an inactive surface opposing the active surface, an encapsulant130encapsulating at least portions of the first connection member110and the semiconductor chip120, a second connection member140disposed on the first connection member110and the active surface of the semiconductor chip120, a passivation layer150disposed on the second connection member140, an underbump metal layer160disposed in openings151of the passivation layer150, and connection terminals170disposed on the passivation layer150and connected to the underbump metal layer160. The second connection member140may include a first insulating layer141adisposed on the first connection member110and the active surface of the semiconductor chip120, a first redistribution layer142adisposed on the first insulating layer141a, a first via layer143aconnecting the first redistribution layer142aand the connecting pads122of the semiconductor chip120to each other, a second insulating layer141bdisposed on the first insulating layer141a, a second redistribution layer142bdisposed on the second insulating layer141b, and a second via layer143bpenetrating through the second insulating layer141band connecting the first and second redistribution layers142aand142bto each other.

Meanwhile, recently, semiconductor packages used in mobile application products have been required to have high density, a miniature size, and a multi-function. Therefore, in accordance with gradual multi-functionalization of semiconductors, the number of required pins has increased, and sizes of the semiconductor packages have thus increased. Therefore, a semiconductor package in accord with a trend toward slimness and lightness of products such as a mobile device, a wearable device, or the like, has been demanded. Technology developed in order to satisfy such a demand is a wafer level package. The wafer level package is technology for directly mounting a chip on a wafer, and innovation such as a reduction in a thickness and a volume of a semiconductor has become possible through the wafer level package. However, an existing wafer level package has a fan-in form, such that there is a limitation in using the existing wafer level package in a chip having many input/output (I/O) terminals. Therefore, a fan-out wafer level package has been prominent as new technology.

Meanwhile, the main issue in the fan-out wafer level package technology that has been recently prominent is to improve board level reliability, for example, reliability in a temperature cycle on board (TCoB) test, a drop test, or the like. Therefore, several attempts to secure the board level reliability of the fan-out semiconductor package have been conducted. As an example of these attempts, there may be a method of changing a shape of ball pads of a redistribution layer, or the like. However, in this case, there is a problem that board level reliability of the fan-out semiconductor package in a case of forming a redistribution layer having a complicated structure including a fan-in region and a fan-out region is not effectively improved.

On the other hand, in the fan-out semiconductor package100A according to the exemplary embodiment, a reliability lifespan may be increased by partially increasing line widths of line patterns142aL of the redistribution layer142aof the second connection member140going through regions to which large stress is applied in an environment in which the board level reliability is problematic. In detail, in one plane region in which the redistribution layer142aof the second connection member140is formed, when the fan-out semiconductor package100A is projected in a direction perpendicular to the active surface of the semiconductor chip120, a projected surface of the semiconductor chip120is a fan-in region and a region surrounding the fan-in region is a fan-out region, line widths of the line pattern142aL may be designed to be increased when the line pattern142aL at least passes through a boundary between the fan-in region and the fan-out region. That is, the redistribution layer142amay include the line pattern142aL including first line portions having a first line width W1and a second line portion connected to the first line portion and having a second line width W2greater than the first line width W1. In this case, the second line portion of the line pattern142aL may at least pass through the boundary between the fan-in region and the fan-out region. In more detail, in one plane region in which the redistribution layer142aof the second connection member140is formed, when the fan-out semiconductor package100A is projected in the direction perpendicular to the active surface of the semiconductor chip120, if the projected surface of the semiconductor chip120is R1, a projected surface of the first connection member110is R2, and a projected surface of a portion of the through-hole110H between the semiconductor chip120and the first connection member110is R3, line widths of the line pattern142aL passing through a region R3and then going through regions R1and R2in the redistribution layer142amay be designed to be increased when the line pattern142aL passes through region R3. That is, the redistribution layer142amay include the line pattern142aL including the first line portion having the first line width W1and the second line portion connected to the first line portion and having the second line width W2greater than the first line width W1, and at least portions of the second line portion of the line pattern142aL may overlap region R3. Therefore, even in a case of forming the redistribution layer142ahaving a complicated structure including the fan-in region and the fan-out region, board level reliability of the fan-out semiconductor package may be effectively improved. Meanwhile, although not illustrated in detail in the drawings, line patterns142aL, or the like, may be similarly introduced into the redistribution layer142b. These line patterns142aL, or the like, may be introduced into both of the redistribution layers142aand142b.

Meanwhile, in a case in which the line pattern142aL such as electrical signal lines or power lines passes through corner portions of region R3to which the large stress is applied in the environment in which the board level reliability is problematic, even though the line pattern142aL of which the line widths W1and W2are designed as described above passes through the corner portions of region R3, a reliability lifespan may be significantly reduced. Therefore, in the fan-out semiconductor package100A according to the exemplary embodiment, dummy patterns142aD disconnected from the line pattern142aL may be disposed in corner portions of the fan-in region, more specifically, the corner portions of region R3. The dummy patterns142aD may be electrically floating patterns. Each of the dummy patterns142aD may be electrically isolated from any of the remaining patterns of the redistribution layers142aand142b, and may not be used to provide any signal or power to the semiconductor chip or to the remaining patterns of the redistribution layers142aand142b. The present disclosure is not limited thereto. For example, the dummy patterns142aD may be electrically connected to a ground (GND) patterns. The dummy patterns142aD may have a width, defined along a boundary between regions R1and R3or between regions R2and R3, greater than the line width W2. The dummy patterns142aD may extend up to corner portions of region R1and portions of region R2adjacent to the corner portions of region R3. The dummy patterns142aD may be more robust to stress than the line pattern142aL due to a metal ratio higher than that of the line pattern142aL, or the like. Meanwhile, line patterns142aL′ designed to pass through the corresponding portions among the line pattern142aL may be disposed to bypass a region occupied by the dummy patterns142aD disposed at the corner portions of the fan-in region, more specifically, the corner portions of region R3. Therefore, an influence of the stress applied to the corresponding region on the line pattern142aL′ may be significantly reduced. Meanwhile, although not illustrated in detail in the drawings, line patterns142aL, dummy patterns142aD, or the like, may be similarly introduced into the redistribution layer142b. These line patterns142aL, dummy patterns142aD, or the like, may be introduced into both of the redistribution layers142aand142b.

The respective components included in the fan-out semiconductor package100A according to the exemplary embodiment will hereinafter be described in more detail.

The first connection member110may improve rigidity of the fan-out sensor package100A depending on certain materials, and serve to secure uniformity of a thickness of the encapsulant130. When through-wirings, or the like, are formed in the first connection member110, the fan-out semiconductor package100A may be utilized as a package-on-package (POP) type package. The first connection member110may have the through-hole110H. The semiconductor chip120may be disposed in the through-hole110H to be spaced apart from the first connection member110by a predetermined distance. Side surfaces of the semiconductor chip120may be surrounded by the first connection member110. However, such a form is only an example and may be variously modified to have other forms, and the first connection member110may perform another function depending on such a form. The first connection member110may be omitted, if necessary, but it may be more advantageous in securing the board level reliability intended in the present disclosure that the fan-out semiconductor package100A includes the first connection member110.

The first connection member110may include an insulating layer111. An insulating material may be used as a material of the insulating layer111. In this case, the insulating material may be a thermosetting resin such as an epoxy resin, a thermoplastic resin such as a polyimide resin, a resin in which the thermosetting resin or the thermoplastic resin is mixed with an organic filler or is impregnated together with an inorganic filler in a core material such as a glass fiber (or a glass cloth or a glass fabric), for example, prepreg, Ajinomoto Build up Film (ABF), FR-4, Bismaleimide Triazine (BT), or the like.

The semiconductor chip120may be an integrated circuit (IC) provided in an amount of several hundreds to several millions of elements or more integrated in a single chip. In this case, the IC may be, for example, a processor chip (more specifically, an application processor (AP)) such as a central processor (for example, a CPU), a graphic processor (for example, a GPU), a field programmable gate array (FPGA), a digital signal processor, a cryptographic processor, a micro processor, a micro controller, or the like, but is not limited thereto. That is, the IC may be a logic chip such as an analog-to-digital converter, an application-specific IC (ASIC), or the like, or a memory chip such as a volatile memory (for example, a DRAM), a non-volatile memory (for example, a ROM), a flash memory, or the like. In addition, the abovementioned elements may also be combined with each other and be disposed.

The semiconductor chip120may be an IC formed on the basis of an active wafer. In this case, a base material of a body121may be silicon (Si), germanium (Ge), gallium arsenide (GaAs), or the like. Various circuits may be formed on the body121. The connection pads122may electrically connect the semiconductor chip120to other components. A material of each of the connection pads122may be a conductive material such as aluminum (Al), or the like. A passivation layer123exposing the connection pads122may be formed on the body121, and may be an oxide film, a nitride film, or the like, or a double layer of an oxide layer and a nitride layer. A lower surface of the connection pad122may have a step with respect to a lower surface of the encapsulant130through the passivation layer123. Resultantly, a phenomenon in which the encapsulant130bleeds into the lower surface of the connection pads122may be prevented to some extent. An insulating layer (not illustrated), and the like, may also be further disposed in other required positions. If necessary, a redistribution layer (not illustrated) may be further formed on the active surface of the semiconductor chip120, and bumps (not illustrated), or the like, may be connected to the connection pads122.

The encapsulant130may protect the first connection member110, the semiconductor chip120, and the like. An encapsulation form of the encapsulant130is not particularly limited, but may be a form in which the encapsulant130surrounds at least portions of the first connection member110, the semiconductor chip120, and the like. For example, the encapsulant130may cover the first connection member110and the inactive surface of the semiconductor chip120, and fill spaces between walls of the through-hole110H and the side surfaces of the semiconductor chip120. In addition, the encapsulant130may also fill at least a portion of a space between the passivation layer123of the semiconductor chip120and the second connection member140. Meanwhile, the encapsulant130may fill the through-hole110H to thus serve as an adhesive and reduce buckling of the semiconductor chip120depending on certain materials.

A material of the encapsulant130is not particularly limited. For example, an insulating material may be used as the material of the encapsulant130. In this case, the insulating material may be a thermosetting resin such as an epoxy resin, a thermoplastic resin such as a polyimide resin, a resin in which the thermosetting resin or the thermoplastic resin is mixed with an organic filler or is impregnated together with an inorganic filler in a core material such as a glass fiber (or a glass cloth or a glass fabric), for example, prepreg, ABF, FR-4, BT, or the like. Alternatively, a PID resin may also be used as the insulating material.

The second connection member140may redistribute the connection pads122of the semiconductor chip120. Several tens to several hundreds of connection pads122of the semiconductor chip120having various functions may be redistributed by the second connection member140, and may be physically or electrically connected to an external source through the connection terminals170depending on the functions. The second connection member140may include the first insulating layer141adisposed on the first connection member110and the active surface of the semiconductor chip120, the first redistribution layer142adisposed on the first insulating layer141a, the first via layer143connecting the first redistribution layer142aand the connecting pads122of the semiconductor chip120to each other, the second insulating layer141bdisposed on the first insulating layer141a, the second redistribution layer142bdisposed on the second insulating layer141b, and the second via layer143bpenetrating through the second insulating layer141band connecting the first and second redistribution layers142aand142bto each other. The first and second redistribution layers142aand142bmay be electrically connected to the connection pads122of the semiconductor chip120.

An insulating material may be used as a material of each of the insulating layers141aand141b. In this case, a photosensitive insulating material such as a PID resin may also be used as the insulating material. That is, the insulating layers141aand141bmay be photosensitive insulating layers. When the insulating layers141aand141bhas photosensitive properties, the insulating layers141aand141bmay be formed to have a smaller thickness, and fine pitches of the via layers143aand143bmay be achieved more easily. The insulating layers141aand141bmay be photosensitive insulating layers including an insulating resin and an inorganic filler. When the insulating layers141aand141bare multiple layers, the materials of the insulating layers141aand141bmay be the same as each other, and may also be different from each other, if necessary. When the insulating layers141aand141bare the multiple layers, the insulating layers141aand141bmay be integrated with each other depending on a process, such that a boundary therebetween may also not be apparent.

The redistribution layers142aand142bmay serve to substantially redistribute the connection pads122. A material of each of the redistribution layers142aand142bmay be a conductive material such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or alloys thereof. The redistribution layers142aand142bmay perform various functions depending on designs of their corresponding layers. For example, the redistribution layers142aand142bmay include ground (GND) patterns, power (PWR) patterns, signal (S) patterns, and the like. Here, the signal (S) patterns may include various signals except for the ground (GND) patterns, the power (PWR) patterns, and the like, such as data signals, and the like. In addition, the redistribution layers142aand142bmay include via pad patterns, connection terminal pad patterns, and the like.

In one plane region in which the redistribution layer142aof the second connection member140is formed, when projected in the direction perpendicular to the active surface of the semiconductor chip120, if the projected surface of the semiconductor chip120is the fan-in region and the region surrounding the fan-in region is the fan-out region, the redistribution layer142amay include the line pattern142aL of which the line widths are increased when the line pattern142aL at least passes through the boundary between the fan-in region and the fan-out region. For example, the redistribution layer142amay include the line pattern142aL including the first line portion having the first line width W1and the second line portion having the second line width W2greater than the first line width W1. In this case, the second line portion of the line pattern142aL may at least pass through the boundary between the fan-in region and the fan-out region. In other words, a line width of the line pattern142aL may be changed from the line width of the first line portion to the line width of the second line portion before the line pattern142aL passes through the boundary between the fan-in region and the fan-out region, and may be again changed from the line width of the second line portion to the line width of the first line portion after the line pattern142aL passes through the boundary between the fan-in region and the fan-out region.

In more detail, in one plane region in which the redistribution layer142aof the second connection member140is formed, when the fan-out semiconductor package100A is projected in the direction perpendicular to the active surface of the semiconductor chip120, if the projected surface of the semiconductor chip120is R1, the projected surface of the first connection member110is R2, and the projected surface of a portion of the through-hole110H between the semiconductor chip120and the first connection member110is R3, the line widths of the line pattern142aL passing through region R3and then going through regions R1and R2in the redistribution layer142amay be increased when the line pattern142aL passes through region R3. For example, the redistribution layer142amay include the line pattern142aL including the first line portion having the first line width W1and the second line portion having the second line width W2greater than the first line width W1, and at least portions of the second line portion of the line pattern142aL may overlap region R3. Therefore, even in the case of forming the redistribution layer142ahaving the complicated structure including the fan-in region and the fan-out region, the board level reliability of the fan-out semiconductor package may be effectively improved. Portions of the second line portion may be disposed in region R3, and the first line portion and the other portions of the second line portion connected to the first line portion may be disposed in regions R1and R2. The line pattern142aL may be signal lines or power lines, depending on a design. The respective line patterns142aL may be connected to the respective pad patterns142aP which may act as landing pads that respective vias, for example, the first vias143aand/or the second vias143b, are formed on. One integral pattern of the first redistribution layer141amay include first and second pad patterns142aP formed at opposite ends of the one integral pattern and having a line pattern142aL connecting the first and second pad patterns142aP to each other. The line pattern142aL of the one integral pattern having a width increasing first and then decreasing along a direction from the first pad pattern142aP to the second pad pattern142aP. An intermediate portion of the line pattern142aP having a maximum width may cross the boundary between the regions R1and R3and the boundary between the regions R2and R3. A width of the first and second pad patterns142aP may be greater than that of the other portions of the line pattern142aP connecting the intermediate portion thereof to the first and second pad patterns142aP. In a case in which the first and second pad patterns142aP have a circular shape, a diameter of the circular shape may be greater than a width W1of the other portions of the line pattern142aP connecting the intermediate portion thereof to the first and second pad patterns142aP, and the diameter of the circular shape may be less than the width W2of the intermediate portion crossing the cross the boundary between the regions R1and R3and the boundary between the regions R2and R3. No via may be formed directly on the intermediate portion crossing the boundary between the regions R1and R3having the width W2. Meanwhile, the line pattern142aL, or the like, may be similarly introduced into the redistribution layer142b. That is, the line pattern142aL, or the like, may be introduced into both of the redistribution layers142aand142b.

In one plane region in which the redistribution layer142aof the second connection member140is formed, the dummy patterns142aD disconnected from the line pattern142aL may be disposed at the corner portions of the fan-in region, more specifically, the corner portions of region R3. The dummy patterns142aD may extend up to the corner portions of region R1and the portions of region R2adjacent to the corner portions of region R3. The dummy patterns142aD may be more robust to stress than the line pattern142aL due to a metal ratio higher than that of the line pattern142aL, or the like. Meanwhile, the line pattern142aL′ designed to pass through the corresponding portions among the line pattern142aL may be disposed to bypass a region occupied by the dummy patterns142aD disposed at the corner portions of the fan-in region, more specifically, the corner portions of region R3. Therefore, an influence of the stress applied to the corresponding region on the line pattern142aL′ may be significantly reduced. The dummy patterns142aD may be electrically insulated from the line pattern142aL. Each of the dummy patterns142aD may also be formed of a conductive material such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or alloys thereof. Shapes of the dummy patterns142aD are not particularly limited, but may be several shapes such as a solid pattern shape, a hole pattern shape, and the like. Meanwhile, although not illustrated in detail in the drawings, the line pattern142aL, the dummy patterns142aD, or the like, may be similarly introduced into the redistribution layer142b. These line patterns142aL, dummy patterns142aD, or the like, may be introduced into both of the redistribution layers142aand142b.

The via layers143aand143bmay electrically connect the redistribution layers142aand142b, the connection pads122, or the like, formed on different layers to each other, resulting in an electrical path in the fan-out semiconductor package100A. A material of each of the via layers143aand143bmay be a conductive material such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or alloys thereof. Each of the via layers143aand143bmay be completely filled with the conductive material, or the conductive material may also be formed along a wall of each of the vias. In addition, each of the via layers143aand143bmay have all of the shapes known in the related art, such as a tapered shape, a cylindrical shape, and the like.

The passivation layer150may protect the second connection member140from external physical or chemical damage. The passivation layer150may have the openings151exposing at least portions of the redistribution layer142bof the second connection member140. The number of openings151formed in the passivation layer150may be several tens to several thousands. A material of the passivation layer150is not particularly limited. For example, an insulating material may be used as the material of the passivation layer150. In this case, the insulating material may be a thermosetting resin such as an epoxy resin, a thermoplastic resin such as a polyimide resin, a resin in which the thermosetting resin or the thermoplastic resin is mixed with an organic filler or is impregnated together with an inorganic filler in a core material such as a glass fiber (or a glass cloth or a glass fabric), for example, prepreg, ABF, FR-4, BT, or the like. Alternatively, a solder resist may also be used.

The underbump metal layer160may improve connection reliability of the connection terminals170to improve board level reliability of the fan-out semiconductor package100A. The underbump metal layer160may be connected to the redistribution layer142bof the second connection member140exposed through the openings151of the passivation layer150. The underbump metal layer160may be formed in the openings151of the passivation layer150by the known metallization method using the known conductive metal such as a metal, but is not limited thereto.

The connection terminals170may physically or electrically externally connect the fan-out semiconductor package100A. For example, the fan-out semiconductor package100A may be mounted on the main board of the electronic device through the connection terminals170. Each of the connection terminals170may be formed of a conductive material, for example, a solder, or the like. However, this is only an example, and a material of each of the connection terminals170is not particularly limited thereto. Each of the connection terminals170may be a land, a ball, a pin, or the like. The connection terminals170may be formed as a multilayer or single layer structure. When the connection terminals170are formed as a multilayer structure, the connection terminals170may include a copper (Cu) pillar and a solder. When the connection terminals170are formed as a single layer structure, the connection terminals170may include a tin-silver solder or copper (Cu). However, this is only an example, and the connection terminals170are not limited thereto.

The number, an interval, a disposition, or the like, of the connection terminals170is not particularly limited, and may be sufficiently modified by a person skilled in the art depending on design particulars. For example, the connection terminals170may be provided in an amount of several tens to several thousands according to the number of connection pads122, or may be provided in an amount of several tens to several thousands or more or several tens to several thousands or less. When the connection terminals170are solder balls, the connection terminals170may cover side surfaces of the underbump metal layer160extending onto one surface of the passivation layer150, and connection reliability may be more excellent.

At least one of the connection terminals170may be disposed in a fan-out region. The fan-out region is a region except for a region in which the semiconductor chip120is disposed. The fan-out package may have excellent reliability as compared to a fan-in package, may implement a plurality of input/output (I/O) terminals, and may facilitate a3D interconnection. In addition, as compared to a ball grid array (BGA) package, a land grid array (LGA) package, or the like, the fan-out package may be manufactured to have a small thickness, and may have price competitiveness.

Meanwhile, although not illustrated in the drawings, a metal thin film may be formed on a wall of the through-hole110H, if necessary, in order to dissipate heat or block electromagnetic waves. In addition, a plurality of semiconductor chips120performing functions that are the same as or different from each other may be disposed in the through-hole110H, if necessary. In addition, a separate passive component such as an inductor, a capacitor, or the like, may be disposed in the through-hole110H, if necessary. In addition, a passive component, for example, a surface mounted technology (SMT) component including an inductor, a capacitor, or the like, may be disposed on a surface of the passivation layer150, if necessary.

FIG. 11is a schematic cross-sectional view illustrating another example of a fan-out semiconductor package.

Referring to the drawing, in a fan-out semiconductor package100B according to another exemplary embodiment in the present disclosure, a first connection member110may include a first insulating layer111ain contact with a second connection member140, a first redistribution layer112ain contact with the second connection member140and embedded in the first insulating layer111a, a second redistribution layer112bdisposed on the other surface of the first insulating layer111aopposing one surface of the first insulating layer111ain which the first redistribution layer112ais embedded, a second insulating layer111bdisposed on the first insulating layer111aand covering the second redistribution layer112b, and a third redistribution layer112cdisposed on the second insulating layer111b. The first to third redistribution layers112a,112b, and112cmay be electrically connected to connection pads122. The first and second redistribution layers112aand112band the second and third redistribution layers112band112cmay be electrically connected to each other through first and second vias113aand113bpenetrating through the first and second insulating layers111aand111b, respectively.

When the first redistribution layer112ais embedded in the first insulating layer111a, a step generated due to a thickness of the first redistribution layer112amay be significantly reduced, and an insulating distance of the second connection member140may thus become constant. That is, a difference between a distance from a first redistribution layer142aof the second connection member140to a lower surface of the first insulating layer111aand a distance from the first redistribution layer142aof the second connection member140to the connection pad122of a semiconductor chip120may be lower than a thickness of the first redistribution layer112a. Therefore, a high density wiring design of the second connection member140may be easy.

A lower surface of the first redistribution layer112aof the first connection member110may be disposed on a level above a lower surface of the connection pad122of the semiconductor chip120. In addition, a distance between the first redistribution layer142aof the second connection member140and the first redistribution layer112aof the first connection member110may be greater than that between the first redistribution layer142aof the second connection member140and the connection pad122of the semiconductor chip120. Here, the first redistribution layer112amay be recessed into the insulating layer111. As described above, when the first redistribution layer112ais recessed into the first insulating layer111a, such that the lower surface of the first insulating layer111aand the lower surface of the first redistribution layer112ahave a step therebetween, a phenomenon in which a material of the encapsulant130bleeds to pollute the first redistribution layer112amay be prevented. The second redistribution layer112bof the first connection member110may be disposed on a level between an active surface and an inactive surface of the semiconductor chip120. The first connection member110may be formed at a thickness corresponding to that of the semiconductor chip120. Therefore, the second redistribution layer112bformed in the first connection member110may be disposed on the level between the active surface and the inactive surface of the semiconductor chip120.

Thicknesses of the redistribution layers112a,112b, and112cof the first connection member110may be greater than those of the redistribution layers142aand142bof the second connection member140. Since the first connection member110may have a thickness equal to or greater than that of the semiconductor chip120, the redistribution layers112a,112b, and112cmay be formed at large sizes depending on a scale of the first connection member110. On the other hand, the redistribution layers142aand142bof the second connection member140may be formed at sizes relatively smaller than those of the redistribution layers112a,112b, and112cfor thinness.

A material of each of the insulating layers111aand111bis not particularly limited. For example, an insulating material may be used as the material of each of the insulating layers111aand111b. In this case, the insulating material may be a thermosetting resin such as an epoxy resin, a thermoplastic resin such as a polyimide resin, a resin in which the thermosetting resin or the thermoplastic resin is mixed with an organic filler or is impregnated together with an inorganic filler in a core material such as a glass fiber (or a glass cloth or a glass fabric), for example, prepreg, ABF, FR-4, BT, or the like. Alternatively, a PID resin may also be used as the insulating material.

The redistribution layers112a,112b, and112cmay serve to redistribute the connection pads122of the semiconductor chip120. A material of each of the redistribution layers112a,112b, and112cmay be a conductive material such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or alloys thereof. The redistribution layers112a,112b, and112cmay perform various functions depending on designs of their corresponding layers. For example, the redistribution layers112a,112b, and112cmay include ground (GND) patterns, power (PWR) patterns, signal (S) patterns, and the like. Here, the signal (S) patterns may include various signals except for the ground (GND) patterns, the power (PWR) patterns, and the like, such as data signals, and the like. In addition, the redistribution layers112a,112b, and112cmay include via pads, wire pads, connection terminal pads, and the like.

The vias113aand113bmay electrically connect the redistribution layers112a,112b, and112cformed on different layers to each other, resulting in an electrical path in the first connection member110. A material of each of the vias113aand113bmay be a conductive material. Each of the vias113aand113bmay be completely filled with the conductive material, or the conductive material may also be formed along a wall of each of via holes. In addition, each of the vias113aand113bmay have all of the shapes known in the related art, such as a tapered shape, a cylindrical shape, and the like. When holes for the first vias113aare formed, some of the pads of the first redistribution layer112amay serve as a stopper, and it may thus be advantageous in a process that each of the first vias113ahas the tapered shape of which a width of an upper surface is greater than that of a lower surface. In this case, the first vias113amay be integrated with the pad patterns of the second redistribution layer112b. In addition, when holes for the second vias113bare formed, some of the pads of the second redistribution layer112bmay serve as a stopper, and it may thus be advantageous in a process that each of the second vias113bhas the tapered shape of which a width of an upper surface is greater than that of a lower surface. In this case, the second vias113bmay be integrated with the pad patterns of the third redistribution layer112c.

A description, or the like, of other configurations except for the abovementioned configuration overlaps that described above, and is thus omitted.

FIG. 12is a schematic cross-sectional view illustrating another example of a fan-out semiconductor package.

Referring to the drawing, in a fan-out semiconductor package100C according to another exemplary embodiment in the present disclosure, a first connection member110may include a first insulating layer111a, a first redistribution layer112aand a second redistribution layer112bdisposed on opposite surfaces of the first insulating layer111a, respectively, a second insulating layer111bdisposed on the first insulating layer111aand covering the first redistribution layer112a, a third redistribution layer112cdisposed on the second insulating layer111b, a third insulating layer111cdisposed on the first insulating layer111aand covering the second redistribution layer112b, and a fourth redistribution layer112ddisposed on the third insulating layer111c. The first to fourth redistribution layers112a,112b,112c, and112dmay be electrically connected to connection pads122. Since the first connection member110may include a larger number of redistribution layers112a,112b,112c, and112d, a second connection member140may be further simplified. Therefore, a decrease in a yield depending on a defect occurring in a process of forming the second connection member140may be suppressed. Meanwhile, the first to fourth redistribution layers112a,112b,112c, and112dmay be electrically connected to each other through first to third vias113a,113b, and113ceach penetrating through the first to third insulating layers111a,111b, and111c.

The first insulating layer111amay have a thickness greater than those of the second insulating layer111band the third insulating layer111c. The first insulating layer111amay be basically relatively thick in order to maintain rigidity, and the second insulating layer111band the third insulating layer111cmay be introduced in order to form a larger number of redistribution layers112cand112d. The first insulating layer111amay include an insulating material different from those of the second insulating layer111band the third insulating layer111c. For example, the first insulating layer111amay be, for example, prepreg including a core material, a filler, and an insulating resin, and the second insulating layer111band the third insulating layer111cmay be an ABF or a PID film including a filler and an insulating resin. However, the materials of the first insulating layer111aand the second and third insulating layers111band111care not limited thereto. Similarly, the first vias113apenetrating through the first insulating layer111amay have a diameter greater than those of second vias113band third vias113ceach penetrating through the second insulating layer111band the third insulating layer111c.

A lower surface of the third redistribution layer112cof the first connection member110may be disposed on a level below a lower surface of the connection pad122of a semiconductor chip120. In addition, a distance between a first redistribution layer142aof the second connection member140and the third redistribution layer112cof the first connection member110may be smaller than that between the first redistribution layer142aof the second connection member140and the connection pad122of the semiconductor chip120. Here, the third redistribution layer112cmay be disposed in a protruding form on the second insulating layer111b, resulting in being in contact with the second connection member140. The first redistribution layer112aand the second redistribution layer112bof the first connection member110may be disposed on a level between an active surface and an inactive surface of the semiconductor chip120. The first connection member110may be formed at a thickness corresponding to that of the semiconductor chip120. Therefore, the first redistribution layer112aand the second redistribution layer112bformed in the first connection member110may be disposed on the level between the active surface and the inactive surface of the semiconductor chip120.

Thicknesses of the redistribution layers112a,112b,112c, and112dof the first connection member110may be greater than those of the redistribution layers142aand142bof the second connection member140. Since the first connection member110may have a thickness equal to or greater than that of the semiconductor chip120, the redistribution layers112a,112b,112c, and112dmay also be formed to have large sizes. On the other hand, the redistribution layers142aand142bof the second connection member140may be formed at relatively small sizes for thinness.

A description, or the like, of other configurations except for the abovementioned configuration overlaps that described above, and is thus omitted.

FIG. 13is a schematic view illustrating board level warpage behavior of a fan-out semiconductor package.

Referring to the drawing, it may be appreciated that when a fan-out semiconductor package100′ is mounted on a board200′, warpage behavior at high temperature and warpage behavior at room temperature are different from each other. Therefore, even in a case of forming a redistribution layer having a complicated structure including a fan-in region and a fan-out region, board level reliability of the fan-out semiconductor package may be problematic. Particularly, in a region R3corresponding to a fixed region in a situation in which warpage behavior is periodically changed oppositely, the largest physical stress may be accumulated, and such a reliability problem may be largest in region R3through which the redistribution layer passes when it goes through regions R1and R2, as described above. However, in the fan-out semiconductor packages100A,100B, and100C described above, such a board level reliability problem may be effectively solved through a design of the redistribution layer of region R3.

As set forth above, according to the exemplary embodiment in the present disclosure, a fan-out semiconductor package of which board level reliability is excellent may be provided.