CMOS to ECL converter

A converter circuit for converting binary logic signals from a CMOS circuit into binary signals for an ECL circuit. Two output transistors in the converter circuit are connected in parallel between the V.sub.DD CMOS supply voltage and the output of the converter circuit. The resistance across the drain-to-source terminals of the output transistors form a voltage divider network with a pulldown resistor in the ECL circuit. In one embodiment, one of the output transistors is enabled by a logic "1" from the CMOS circuit and the other is enabled only by a logic "0". In another embodiment, one output transistor is always enabled and the other is enabled only by a logic "0" from the CMOS circuit. In both embodiments, the effective resistance across the parallel transistors is different for a logic level "1" and a logic level "0", so that the voltage at the output is also different. The aspect ratio of the output transistors is chosen in order to obtain the desired voltages at the output which correspond to the ECL logic signals.

BACKGROUND OF THE INVENTION 
The present invention relates to signal converting circuits and, more 
particularly, to a circuit for converting signals from a CMOS 
(complementary metal-oxide-semiconductor) circuit into signals for an ECL 
(emitter-coupled logic) circuit. 
Computer systems today use circuits implemented in different hardware 
technology. For example, it is not uncommon to find in one computer both 
CMOS and ECL circuits. CMOS is often used in very large chips having many 
transistors (in excess of 100,000) because of the suitability of CMOS in 
achieving the power dissipation requirements of that many transistors. 
Other smaller, but faster, chips are normally implemented in ECL. 
One problem with having circuits in one system implemented in different 
hardware technologies is that the same logic levels of the circuit signals 
are represented by different voltages. For example, in a CMOS circuit, a 
logic level "1" will typically be represented by ground (0 V) and a logic 
level "0" will typically be represented by -5 V. An ECL circuit, on the 
other hand, will typically have a logic level "1" represented by -0.98 V 
and logic level "0" represented by -1.6 V. It thus becomes necessary to 
provide a signal converter or interface when the signals from a CMOS 
circuit are provided to an ECL circuit. 
Circuits have been designed for converting CMOS logic signals into ECL 
logic signals. For example in U.S. Pat. No. 4,704,549, entitled "CMOS to 
ECL Converter-Buffer", which is assigned to the same assignee as herein, 
there is shown a circuit having MOS transistors for converting CMOS logic 
signals to ECL logic signals. One drawback of this circuit is the fact 
that the transistor that provides the ECL logic level signals at the 
output of the circuit requires a voltage in addition to the normal 
voltages (V.sub.DD and V.sub.SS) used to power CMOS devices. An external 
power source, which increases the cost of the circuit, is necessary to 
provide the additional voltage. Another drawback of the circuit disclosed 
in the aforementioned U.S. Pat. No. 4,704,549, as well as other known 
circuits, is the signal noise that sometimes arises because of the 
switching of the transistors used in such circuits. 
SUMMARY OF THE INVENTION 
There is provided, in accordance with the present invention, a converter 
circuit for converting a first set of logic signals into a second set of 
logic signals. The circuit includes first and second output transistors 
that are connected in parallel, with a first terminal of each connected to 
a power source, and with a second terminal of each connected to the output 
of the converter circuit for providing the second set of logic signals. 
The resistances across the output transistors form a voltage divider with 
the resistance of a circuit at the output which uses the second set of 
logic signals. The output transistors have control terminals connected so 
that the first output transistor is enabled in response to a first level 
signal in the first set of logic signals and the second output transistor 
is enabled in response to a second level signal in the first set of logic 
signals. The first output transistor when enabled has a different 
resistance than the second output transistor when enabled, so that one 
voltage appears at the output of the converter circuit corresponding to a 
first level signal in the second set of logic signals when the first 
output transistor is enabled and a second voltage appears at the output of 
the converter circuit corresponding to a second level signal in the second 
set of logic signals when the second output transistor is enabled. 
In the embodiments of the invention described herein, the converter circuit 
is fabricated on a CMOS device and converts signals from the CMOS device 
into signals for an external ECL device. The output transistors are 
P-channel MOS transistors, with the drain of each connected to the CMOS 
power source V.sub.DD (approximately 0 V or ground). The source of each of 
the output transistors is connected at the output of the converter circuit 
and, by way of a pulldown or termination resistor, to a termination or 
pulldown voltage source at the ECL device. The pulldown or termination 
resistor at the ECL device provides the resistance with which the output 
transistors form a voltage divider. 
Since the transistors at the output of the converter circuit are connected 
to the CMOS power source V.sub.DD, no external power source is required 
for the converter circuit other than those already required for CMOS 
devices. Also, since both of the output transistors of the converter 
circuit are connected to the same power source (V.sub.DD), and since one 
or the other of those transistors is always enabled, there is a constant 
current path at the output of the converter circuit. The constant current 
path results in only minimal noise being generated at the output of the 
converter circuit. Further, the converter circuit is fabricated with 
minimal components, which both increases speed and reduces cost. 
It is therefore an object of the present invention to provide a new and 
improved signal converter circuit. 
It is another object of the present invention to provide such a circuit for 
converting CMOS logic level signals into ECL logic level signals. 
It is yet another object of the present invention to provide such a circuit 
without the need for external power sources other than those providing the 
voltages normally required for CMOS devices. 
It is still a further object of the present invention to provide a 
converter circuit of the type just-described which generates minimal 
electrical noise and which can be fabricated with minimal cost. 
These and other objects, features, and advantages of the present invention 
will become apparent from the following description and the attached 
drawings, wherein like reference numbers indicate like parts.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
Referring now to FIG. 1, there is seen a CMOS to ECL interface or converter 
circuit 10 in accordance with the present invention. The circuit 10 
connects a CMOS logic device or circuit 12 to an ECL logic device or 
circuit 14. The binary logic signals at the output of the CMOS circuit 12 
are provided as the input V.sub.IN to the converter circuit 10. Those 
binary signals will be at approximately -5 V for a logic level "0" and at 
approximately 0 V for a logic level "1". The output V.sub.OUT of the 
converter circuit 10 will provide binary signals for the ECL circuit 14, 
at approximately -1.6 V for a logic level "0" and approximately -0.98 V 
for a logic level "1". As conventional, and as shown in FIG. 1, a 
termination or pulldown resistor R.sub.TERM is associated with the ECL 
circuit 14 and connects the ECL circuit to a termination voltage 
V.sub.TERM (approximately -2 V). 
In the preferred embodiment, the converter circuit 10 is fabricated on the 
same chip as the CMOS circuit 12. The circuit 10 is powered by the same 
voltage sources that power the CMOS circuit, namely a positive supply 
voltage V.sub.DD (which is approximately 0 V or ground) and a negative 
supply voltage V.sub.SS (which is approximately -5 V). 
The converter circuit 10 consists of two P-channel MOS output transistors 
QP1 and QP2 and a CMOS inverter 16. The CMOS inverter 16 consists of an 
N-channel MOS transistor QN1 and a P-channel MOS transistor QP3, with the 
drain of QP3 connected to V.sub.DD, the source of QN1 connected to 
V.sub.SS, and the source of QP3 and the drain of QN1 tied together to 
provide the output of the inverter 16. 
The gate of transistor QP1 is connected to the input of the circuit 10 for 
receiving the signal V.sub.IN, and the gate of the transistor QP2 is 
connected to the output of the inverter 16 (the tied source of QP3 and 
drain of QN1). The transistors QP1 and QP2 are connected in parallel, with 
the drain of each connected to V.sub.DD and the source of each connected 
together to provide the circuit output signal V.sub.OUT. 
In operation, when V.sub.IN is at a logic level "0", transistor QP1 is 
enabled and transistor QP2 is disabled. Conversely, when V.sub.IN is at a 
logic level "1", QP2 is enabled and QP1 is disabled. As will be more fully 
described shortly, the drain-to-source resistances of transistors QP1 and 
QP2 are selected during the fabrication of QP1 and QP2 so that the voltage 
level of V.sub.OUT will represent one logic level when QP1 is enabled and 
will be different and represent a second logic level when QP2 is enabled. 
The drain-to-source resistances of transistors QP1 and QP2 form a voltage 
divider with the pulldown resistor R.sub.TERM associated with the ECL 
circuit 14. The voltage divider is illustrated in FIG. 2, where the 
effective resistances across QP1 and QP2 are represented by R.sub.effQP1 
and R.sub.effQP2, respectively. When QP1 is enabled and QP2 is disabled, 
the resistance R.sub.effQP2 is essentially infinite and thus V.sub.OUT 
(which represents a logic level "0") can be calculated as follows: 
##EQU1## 
Likewise, when QP2 is enabled and QP1 is disabled, the resistance 
R.sub.QP1 is essentially infinite and thus V.sub.OUT can be calculated as 
follows: 
##EQU2## 
In a preferred embodiment of the circuit 10, the following circuit values 
have been chosen when V.sub.DD =0 V, V.sub.SS =-5 V, and when the logic 
levels "0" and "1" for the ECL logic circuit 14 are desired to be -1.6 V 
and -0.98 V, respectively. 
______________________________________ 
R.sub.effQP1 
96 Ohms 
R.sub.effQP2 
400 Ohms 
R.sub.TERM 
100 Ohms 
______________________________________ 
The effective drain-to-source resistance of each of the transistors QP1 and 
QP2 when enabled is determined during fabrication by controlling the 
channel width-to-length ratio (also known as the "aspect" ratio) of the 
transistors. This resistance can be approximated from the following 
equation: 
##EQU3## 
where ".mu." is the effective surface mobility of the electrons in the 
channel, ".epsilon." is the permittivity of the gate insulator , "t.sub.ox 
" is the thickness of the gate insulator, "W" is the width of the channel 
, "L" is the length of the channel, "V.sub.gs " is the gate-to-source 
voltage, and "V.sub.t " is the threshold voltage. For purpose of 
reference, such equation is explained in more detail in Weste, N. H. E. 
and Eshraghian, K. Principles of CMOS VLSI Design. (Reading, Mass., 
Addison-Wesley Publishing Company, 1985) p. 40-42. 
The selection of the voltage levels for the output signal V.sub.OUT in the 
circuit 10 by control of the aspect ratio of each of the transistors QP1 
and QP2 also permits one to select whether the output voltage V.sub.OUT 
will be inverted or not. That is, if the effective resistance of QP1 (when 
enabled) is greater than the effective resistance of QP2 (when enabled), 
then the output of the circuit 10 is non-inverting. Conversely, when the 
effective resistance of QP2 is greater than the effective resistance of 
QP1, then the output of the circuit 10 is inverting. 
If one uses the voltage divider rule for the circuit shown in FIG. 2, the 
voltage across the transistors QP1 and QP2 is calculated as follows: 
##EQU4## 
where R.sub.effQP is the effective resistance of the enabled one of the 
transistors QP1 and QP2. If one further combines the last-mentioned 
Equation 4 with the previously stated Equation 3 for calculating the 
effective resistance, then one can calculate the aspect ratio required for 
the transistors QP1 and QP2 by the following two equations: 
##EQU5## 
If Equation 5a is used to select the aspect ratio of transistor QP1 and 
Equation 5b is used to select the aspect ratio of transistor QP2, then the 
circuit 10 is noninverting. If, on the other hand, Equation 5b is used to 
select the aspect ratio of transistor QP1 and Equation 5a is used to 
select the aspect ratio of transistor QP2, then the output of the circuit 
10 will be inverting. 
It should be appreciated from the description thus far that the converter 
circuit 10 shown in FIG. 1 has, because of the parallel arrangement of the 
transistors QP1 and QP2, the advantage of generating minimal noise because 
of the constant current path from V.sub.DD to V.sub.TERM (one of either 
QP1 or QP2 is always enabled). A further advantage that should be 
appreciated is that the generation of the ECL logic level signals 
(V.sub.OUT) is accomplished without a power source at the CMOS circuit and 
converter circuit (which are both on the same CMOS chip) other than the 
normal CMOS supply voltages V.sub.DD or V.sub.SS. Hence, no external power 
supply for the converter circuit 10 is required. Other advantages, such as 
the minimal number components required for fabricating the converter 
circuit 10 on a CMOS chip, should also be evident. 
FIG. 3 shows a converter circuit 10A connected between a CMOS logic circuit 
12 and an ECL logic circuit 14 in the same manner as the converter circuit 
10 in FIG. 1. The converter circuit 10A is also identical in construction 
and operation to the converter circuit 10, except for the connection of a 
P-channel MOS transistor QP4 between the tied source terminals of the 
transistors QP1 and QP2 and the output of the circuit 10A. Transistor QP4 
is fabricated so that its drain-to-source current flow is clamped at a 
sufficiently low level to protect the ECL circuit 14 against voltage 
spikes originating at the supply voltage V.sub.DD. In a preferred 
embodiment, the transistor QP4 is chosen so that it reaches saturation, 
and the current through QP4 is clamped, at 1MA. 
In FIG. 4 there is seen a converter circuit 10B representing yet another 
embodiment of the present invention. Circuit 10B is connected between a 
CMOS logic circuit 12 and an ECL logic circuit 14 in the same manner as 
the converter circuit 10 in FIG. 1. Converter circuit 10B has, however, 
fewer components than the circuit 10. 
Converter circuit 10B consists of P-channel MOS transistors QP1 and QP2, 
connected in parallel between V.sub.DD and the output V.sub.OUT in the 
same manner as the converter circuit 10 in FIG. 1. However, unlike the 
embodiment of FIG. 1, QP1 has its gate connected to the supply voltage 
V.sub.SS and QP2 has its gate connected to the output of the CMOS circuit 
12. As a consequence, QP1 is always enabled; QP2 is enabled when the 
output of the CMOS circuit 12 (and V.sub.IN) is at a logic level "0" and 
is disabled when the output of the CMOS circuit 12 is at a logic level 
"1". 
In operation, when V.sub.IN is at a logic level "1", QP2 is disabled and 
the effective resistance across the parallel transistors QP1 and QP2 is 
simply the drain-to-source resistance R.sub.effQP1 of QP1. When V.sub.IN 
is at a logic level "0", both QP1 and QP2 are enabled, and the effective 
resistance across the transistors is given by the conventional formula for 
calculating the resistance of parallel resistors: 
##EQU6## 
By using the previously stated Equations 3 and 4, one can calculate the 
aspect ratio required for transistors QP1 and QP2 in FIG. 4 as follows: E1 
? 
##STR1## 
Since the effective resistance across the transistors QP1 and QP2 is lower 
when QP2 is enabled, the voltage at V.sub.OUT is greater when the input 
V.sub.IN is at a logic level "0" (enabling QP2). As a consequence, the 
circuit 10B will always invert the input V.sub.IN. 
It can thus be seen that there has been provided by the present invention 
an improved signal converter circuit that is simple in construction and 
inexpensive to produce. 
Although the presently preferred embodiments of the invention have been 
described, it will be understood that various changes may be made within 
the scope of the appended claims.