Manufacturing method for a leadless multi-chip electronic module

A leadless multi-chip electronic module with leadframe bond pads is manufactured in a manner to place small signal bond pads in a central region of the module for significantly increased reliability of solder joints between such bond pads and a substrate of the module. A linear array of parallel leadframe elements disposed in a central region of the module and bridging first and second larger IC leadframe bond pads are converted into signal bond pads by a pair of partial bottom-side saw cuts. The saw cuts run parallel to and adjacent the first and second IC bond pads to electrically isolate the leadframe elements from the IC bond pads and other bond pads. The partial saw cuts are made following encapsulation and preferably before leadframe singulation.

TECHNICAL FIELD

The present invention relates to leadless multi-chip electronic modules, and more particularly to a method of manufacturing a leadless multi-chip electronic module having improved solder joint reliability.

BACKGROUND OF THE INVENTION

A conventional leadless multi-chip electronic module is generally designated by the reference numeral10inFIGS. 1A and 1B. Referring toFIGS. 1A-1B, the module10(which may be QFN or PQFN devices, for example) comprises two or more integrated circuit (IC) chips12,14, metal leadframe bond pads16a-16dand a substrate18. Large bond pads16a,16bare provided for each IC chip12,14; and a plurality of signal bond pads16cand power bond pads16dare provided to interface the IC chips12,14to the substrate18. Terminals on the exposed face of the IC chips12and14are electrically coupled to the signal and power bond pads16cand16dby wirebonds20, as shown. A plastic or epoxy encapsulant22covers the IC chips12and14, the upper and lateral surfaces of the leadframe bond pads16a-16dand the wirebonds20, leaving only the lower surfaces of the leadframe bond pads16a-16duncovered. Following singulation of the leadframe bond pads16a-16d, their exposed lower surfaces are soldered to a set of conductor pads24formed on the inboard face18aof substrate18.

Due to leadframe layout considerations, a conventional leadless multi-chip electronic module10is generally configured with the large IC bond pads16aand16boccupying a central region of the module10, and the signal and power bond pads16cand16doccupying the peripheral or marginal region of the module10. In the illustration ofFIG. 1A, for example, the signal and power bond pads16cand16dare respectively disposed along the top and bottom edges of the module10, with the IC bond pads16aand16bdisposed in a central region between the signal and power bond pads16cand16d. While this sort of layout is desirable from a manufacturing standpoint, it can cause reliability problems in applications where the module10is used in environments subject to widely varying ambient temperatures such as occur in outdoor or vehicular systems. In such environments, the CTE (coefficient of thermal expansion) differences between the leadframe elements16a-16dand the substrate18can result in solder joint cracking, particularly in the case of small solder joints26between the substrate18and the signal bond pads16clocated at the periphery of the module10. Solder joints26located at or near the corners of the module10are particularly vulnerable to thermal-related failures.

A typical way of improving solder joint reliability is to increase the surface area of the signal bond pads16clocated at the periphery of the module10, particularly in the corners, as illustrated inFIG. 1A. However, increasing the bond pad surface area limits the pin-count of the module10, and only marginally improves the solder joint reliability. Accordingly, what is needed is a way of significantly improving the solder joint reliability of a leadless multi-chip electronic module.

SUMMARY OF THE INVENTION

The present invention is directed to a method of manufacture of leadless multi-chip electronic module with leadframe bond pads, where small signal bond pads are disposed in a central region of the module for significantly increased reliability of solder joints between such bond pads and a substrate of the module. A linear array of parallel leadframe elements disposed in a central region of the module and bridging first and second larger IC leadframe bond pads are converted into signal bond pads by a pair of partial bottom-side saw cuts parallel to and adjacent the first and second IC bond pads. The partial saw cuts remove portions of the leadframe elements adjacent the first and second IC bond pads and thereby electrically isolate the leadframe elements from the IC bond pads and other bond pads. The partial saw cuts are made following encapsulation and preferably before leadframe singulation.

DESCRIPTION OF THE PREFERRED EMBODIMENT

In general, the present invention provides a way of making a leadless multi-chip electronic module in which small leadframe bond pads subject to solder joint failure due to thermal cycle stress are positioned in a central low-stress region of the module. Larger bond pads less subject to solder joint failure due to thermal cycle stress are positioned laterally outboard of the small bond pads and support IC chips that are electrically coupled to the small bond pads.

FIGS. 2 and 3respectively depict first and second leadless multi-chip electronic modules30,32manufactured according to this invention. In each case, a set of small signal bond pads34are disposed in a linear array along an axis A between two larger IC bond pads36and38. Two large power bond pads40are placed at the lower periphery of the modules30,32as inFIG. 1A. Also as inFIG. 1A, IC chips12and14are respectively soldered to bond pads36and38, and wirebonds42electrically couple the IC chips12and14and the signal and power bond pads34and40. Since the signal bond pads34lie in low thermal stress regions of the modules30and32, they may be uniformly small in surface area as shown without sacrificing solder joint reliability.

The module32ofFIG. 3differs from the module30ofFIG. 2by the addition of large extraneous or “dummy” bond pads44in unused peripheral regions of the module. The large solder joints between the “dummy” bond pads44and the substrate18add mechanical strength to the module32by absorbing thermal-related stress that would otherwise be applied to the smaller solder joints between the signal bond pads34and the substrate18. Additionally, the solder joints between the “dummy” bond pads44and the substrate18enhance thermal transfer from the IC chips12and14to the substrate18.

According to this invention, the signal bond pads34in the central region of modules30and32are formed by a pair of bottom-side partial saw cuts of the leadframe parallel to the axis A ofFIGS. 2-3prior to soldering the leadframe bond pads34-40to the substrate18. Initially, each of the signal bond pads34is defined by a leadframe element extending substantially perpendicular to the axis A. Leadframe elements disposed between the IC bond pads36and38bridge the bond pads36and38; leadframe elements laterally outboard of the IC bond pad36extend from the IC bond pad38to another bond pad or the leadframe web. A first bottom-side partial saw cut parallel to axis A adjacent the edge of IC bond pad38removes leadframe metal to electrically isolate the leadframe elements from the IC bond pad38. A second bottom-side partial saw cut parallel to axis A adjacent the edge of IC bond pad36removes leadframe metal to electrically isolate the leadframe elements from the IC bond pad36or other leadframe components on that side of axis A. The process effectively converts the leadframe elements into the small signal bond pads34.

The above described process is illustrated inFIGS. 4A-4C, which depict cross-sectional views of the modules30and32as indicated inFIGS. 2-3. InFIG. 4A, an un-cut leadframe element is designated by the reference numeral50, and the location of axis A is designated by the reference numeral35. Preferably, the leadframe elements50are initially half-etched to form top-side notches in vertical alignment with the bottom-side partial saw cuts; this maintains the mechanical integrity of the leadframe while substantially halving the amount of leadframe metal to be removed by the partial saw cuts.FIG. 4Bdepicts the modules30and32after both of the bottom-side partial saw cuts have been performed. As illustrated, the portion of the leadframe element50not removed by the saw cuts becomes the small signal bond pad34. The same two partial saw cuts thereby convert each of the leadframe elements50into a signal bond pad34. The cross-section ofFIG. 4Cillustrates the modules30and32after soldering of the leadframe bond pads34,36,38and40to corresponding bond pads24formed on the inboard face18aof substrate18. While the solder joint52formed between signal bond pad34and the substrate bond pad24is small in size, its placement in a low-stress region of the module30or32ensures that it will be able to withstand thermal-related stresses with satisfactory reliability.

In practice, several modules are manufactured as a unitary structure and then singulated into individual electronic modules by full saw cuts, as illustrated in respect to the module30inFIG. 5. In that illustration, four modules30a,30b,30cand30dare manufactured as unitary structure, and the full saw cuts for singulation of the modules30a-30doccur along the solid lines60and62. The partial saw cuts for modules30aand30boccur along the broken lines64and66; and the partial saw cuts for modules30cand30doccur along the broken lines68and70. Preferably, the partial saw cuts are made prior to the full (singulation) saw cuts. Of course, any number of modules may be manufactured as a unitary structure, andFIG. 5is presented by way of example only.

In summary, the present invention provides a method of manufacturing leadless multi-chip electronic modules in a way that dramatically improves solder joint reliability. The partial saw cuts required to form the centrally located signal bond pads34do not significantly increase manufacturing cost, as multiple full saw cuts are already required for singulation of the modules.

While the present invention has been described with respect to the illustrated embodiments, it is recognized that numerous modifications and variations in addition to those mentioned herein will occur to those skilled in the art. For example, the number of IC chips utilized in a module manufactured according to this invention may be different than shown, the IC chips may be secured to the IC bond pads by an adhesive material, thermal vias may be utilized for improved heat transfer, and so on. Accordingly, it is intended that the invention not be limited to the disclosed embodiment, but that it have the full scope permitted by the language of the following claims.