Microelectronic devices with multiple step contacts extending to stepped tiers, and related systems and methods

Microelectronic devices include a stack structure having a vertically alternating sequence of insulative structures and conductive structures arranged in tiers. At least one stadium, of stadiums within the stack structure, comprise staircase(s) having steps provided by a group of the conductive structures. Step contacts extend to the steps of the staircase(s) of the at least one of the stadiums. Each conductive structure of the group of conductive structures has more than one of the step contacts in contact therewith at at least one of the steps of the staircase(s). Additional microelectronic devices are also disclosed, as are methods of fabrication and electronic systems.

TECHNICAL FIELD

Embodiments of the disclosure relate to the field of microelectronic device design and fabrication. More particularly, the disclosure relates to microelectronic devices (e.g., memory devices, such as 3D NAND memory devices) including contacts extending to conductive structures of a tiered stack including the conductive structures vertically alternating with insulative structures. The disclosure also relates to methods for forming such devices and to systems incorporating such devices.

BACKGROUND

Memory devices provide data storage for electronic systems. A Flash memory device is one of various memory device types and has numerous uses in modern computers and other electrical devices. A conventional Flash memory device may include a memory array that has a large number of charge storage devices (e.g., memory cells, such as non-volatile memory cells) arranged in rows and columns. In a NAND architecture type of Flash memory, memory cells arranged in a column are coupled in series, and a first memory cell of the column is coupled to a data line (e.g., a bit line). In a “three-dimensional NAND” memory device (which may also be referred to herein as a “3D NAND” memory device), a type of vertical memory device, not only are the memory cells arranged in row and column fashion in a horizontal array, but tiers of the horizontal arrays are stacked over one another (e.g., as vertical strings of memory cells) to provide a “three-dimensional array” of the memory cells. The stack of tiers vertically alternate conductive materials with insulating (e.g., dielectric) materials. The conductive materials function as control gates for, e.g., access lines (e.g., word lines) of the memory cells. Vertical structures (e.g., pillars comprising channel structures and tunneling structures) extend along the vertical string of memory cells. A drain end of a string is adjacent one of the top and bottom of the vertical structure (e.g., pillar), while a source end of the string is adjacent the other of the top and bottom of the pillar. The drain end is operably connected to a bit line, while the source end is operably connected to a source structure (e.g., a source plate, a source line). A 3D NAND memory device also includes electrical connections between, e.g., access lines (e.g., word lines) and other conductive structures of the device so that the memory cells of the vertical strings can be selected for writing, reading, and erasing operations.

One method of forming such electrical connections includes forming a so-called “staircase” structure having “steps” (or otherwise known as “stairs”) at edges (e.g., adjacent ends) of the tiers of the stack. The steps define contact regions of conductive structures of the device, such as access lines (e.g., word lines), which may be formed by the conductive materials of the tiered stack. Contact structures may be formed in physical contact with the steps to provide electrical access to the conductive structures (e.g., word lines) associated with the steps. The contact structures may be in electrical communication, via conductive routing lines, to additional contact structures that communicate to a source/drain region.

A continued goal in the microelectronic device fabrication industry is to reliably fabricate the features of microelectronic devices so that the devices function as intended, including effective electrical communication between electrically conductive features, such as contact structures and the steps formed in the tiered stack. However, this continues to present challenges, particularly as failure to accurately fabricate one contact structure may, in conventional device designs, render electrically inaccessible a corresponding conductive structure (e.g., word line) and may also render inoperable a whole group of device features.

DETAILED DESCRIPTION

Structures (e.g., microelectronic device structures), apparatuses (e.g., microelectronic devices), and systems (e.g., electronic systems), according to embodiments of the disclosure, include a stack of vertically alternating conductive structures and insulative structures arranged in tiers. A series of stadiums is formed in the tiered stack. The stadiums include staircase structures having steps defined by ends (e.g., horizontal surfaces adjacent sidewalls) of at least one of the conductive structures of the tiers of the stack and having risers defined by ends (e.g., vertical surfaces) of at least one of the conductive structures and at least one of the insulative structures of the tier. For at least some of the tiers of the stack, such as the deepest tiers of the stack, multiple steps are formed per tier (e.g., per conductive structure (e.g., per word line)) or relatively-wider and/or relatively-longer steps are formed per tier. At least one conductive “step contact” (e.g., access line contact, word line contact) extends to each step. For the tiers with multiple defined steps (or relatively-wider and/or relatively-longer defined steps), multiple step contacts are formed to be in electrical communication with the conductive structure (e.g., word line) of each such tier. Therefore, should one of the step contacts not be accurately fabricated—for example, due to challenges with fabricating step contacts that extend to the deepest tiers—an accurately-fabricated step contact extending to another portion (e.g., another step) of the tier nonetheless provides directly physical contact to and electrical communication with the conductive structure (e.g., access line, word line) of the tier. The multiple step contacts may, therefore, function as “back-up” step contacts for a particular tier of the stack, significantly lessening the likelihood of complete failure to electrically access any one conductive structure (e.g., word line) in a fabricated microelectronic device. Therefore, and where an electrical communication failure with any one tier of a stadium may otherwise exhibit as a whole-stadium failure (e.g., a stadium “read” or “write” error), including multiple step contacts per tier may significantly lessen the likelihood of such whole-stadium failures.

As used herein, the term “descending staircase” means and refers to a staircase generally exhibiting negative slope.

As used herein, the term “ascending staircase” means and refers to a staircase generally exhibiting positive slope.

As used individually herein, the terms “multiple,” “group,” and “set” each mean and refer to there being more than one of (e.g., a “plurality of”) the indicated features, and these terms may be used interchangeably. As used in combination herein (e.g., a “set of multiple,” “a group of multiple”), the terms mean and refer to there being more than one of the pluralities of the indicated features.

As used herein, the term “high-aspect-ratio” means and refers to a height-to-width (e.g., a ratio of a maximum height to a maximum width) of greater than about 10:1 (e.g., greater than about 20:1, greater than 30:1, greater than about 40:1, greater than about 50:1, greater than about 60:1, greater than about 70:1, greater than about 80:1, greater than about 90:1, greater than about 100:1).

As used herein, a feature referred to with the adjective “source/drain” means and refers to the feature being configured for association with either or both the source region and the drain region of the device that includes the “source/drain” feature. A “source region” may be otherwise configured as a “drain region” and vice versa without departing from the scope of the disclosure.

As used herein, the terms “opening,” “trench,” “slit,” “recess,” and “void” mean and include a volume extending through or into at least one structure or at least one material, leaving a gap in that at least one structure or at least one material, or a volume extending between structures or materials, leaving a gap between the structures or materials. Unless otherwise described, an “opening,” “trench,” “slit,” and/or “recess” is not necessarily empty of material. That is, an “opening,” “trench,” “slit,” or “recess” is not necessarily void space. An “opening,” “trench,” “slit,” or “recess” formed in or between structures or materials may comprise structure(s) or material(s) other than that in or between which the opening is formed. And, structure(s) or material(s) “exposed” within an opening, trench, slit, or recess is/are not necessarily in contact with an atmosphere or non-solid environment. Structure(s) or material(s) “exposed” within an opening, trench, slit, or recess may be adjacent or in contact with other structure(s) or material(s) that is/are disposed within the opening, trench, slit, or recess. In contrast, unless otherwise described, a “void” may be substantially or wholly empty of material. A “void” formed in or between structures or materials may not comprise structure(s) or material(s) other than that in or between which the “void” is formed. And, structure(s) or material(s) “exposed” within a “void” may be in contact with an atmosphere or non-solid environment.

As used herein, the terms “substrate” and “base structure” mean and include a base material or other construction upon which components, such as those within memory cells, are formed. The substrate or base structure may be a semiconductor substrate, a base semiconductor material on a supporting structure, a metal electrode, or a semiconductor substrate having one or more materials, structures, or regions formed thereon. The substrate may be a conventional silicon substrate or other bulk substrate including a semiconductive material. As used herein, the term “bulk substrate” means and includes not only silicon wafers, but also silicon-on-insulator (“SOT”) substrates, such as silicon-on-sapphire (“SOS”) substrates or silicon-on-glass (“SOG”) substrates, epitaxial layers of silicon on a base semiconductor foundation, or other semiconductor or optoelectronic materials, such as silicon-germanium (Si1-xGex, where x is, for example, a mole fraction between 0.2 and 0.8), germanium (Ge), gallium arsenide (GaAs), gallium nitride (GaN), or indium phosphide (InP), among others. Furthermore, when reference is made to a “substrate” or “base structure” in the following description, previous process stages may have been utilized to form materials, structures, or junctions in the base semiconductor structure, base structure, or other foundation.

As used herein, the terms “insulative” and “insulating,” when used in reference to a material or structure, means and includes a material or structure that is electrically insulative or electrically insulating. An “insulative” or “insulating” material or structure may be formed of and include one or more of at least one dielectric oxide material (e.g., one or more of a silicon oxide (SiOx), phosphosilicate glass, borosilicate glass, borophosphosilicate glass, fluorosilicate glass, an aluminum oxide (AlOx), a hafnium oxide (HfOx), a niobium oxide (NbOx), a titanium oxide (TiOx), a zirconium oxide (ZrOx), a tantalum oxide (TaOx), and a magnesium oxide (MgOx)), at least one dielectric nitride material (e.g., a silicon nitride (SiNy)), at least one dielectric oxynitride material (e.g., a silicon oxynitride (SiOxNy)), at least one dielectric carboxynitride material (e.g., a silicon carboxynitride (SiOxCzNy)), and/or air. Formulae including one or more of “x,” “y,” and/or “z” herein (e.g., SiOx, AlOx, HfOx, NbOx, TiOx, SiNy, SiOxNy, SiOxCzNy) represent a material that contains an average ratio of “x” atoms of one element, “y” atoms of another element, and/or “z” atoms of an additional element (if any), respectively, for every one atom of another element (e.g., Si, Al, Hf, Nb, Ti). As the formulae are representative of relative atomic ratios and not strict chemical structure, an insulative material or insulative structure may comprise one or more stoichiometric compounds and/or one or more non-stoichiometric compounds, and values of “x,” “y,” and “z” (if any) may be integers or may be non-integers. As used herein, the term “non-stoichiometric compound” means and includes a chemical compound with an elemental composition that cannot be represented by a ratio of well-defined natural numbers and is in violation of the law of definite proportions. In addition, an “insulative structure” means and includes a structure formed of and including insulative material.

As used herein, the term “sacrificial,” when used in reference to a material or structure, means and includes a material or structure that is formed during a fabrication process but which is removed (e.g., substantially removed) prior to completion of the fabrication process.

As used herein, the term “horizontal” means and includes a direction that is parallel to a primary surface of the substrate on which the referenced material or structure is located. The “width” and “length” of a respective material or structure may be defined as dimensions in a horizontal plane. With reference to the figures, the “horizontal” direction may be perpendicular to an indicated “Z” axis, may be parallel to an indicated “X” axis, and may be parallel to an indicated “Y” axis.

As used herein, the term “lateral” means and includes a direction in a horizontal plane parallel to a primary surface of the substrate on which a referenced material or structure is located and substantially perpendicular to a “longitudinal” direction. The “width” of a respective material or structure may be defined as a dimension in the lateral direction of the horizontal plane. With reference to the figures, the “lateral” direction may be parallel to an indicated “X” axis, may be perpendicular to an indicated “Y” axis, and may be perpendicular to an indicated “Z” axis.

As used herein, the term “longitudinal” means and includes a direction in a horizontal plane parallel to a primary surface of the substrate on which a referenced material or structure is located, and substantially perpendicular to a “lateral” direction. The “length” of a respective material or structure may be defined as a dimension in the longitudinal direction of the horizontal plane. With reference to the figures, the “longitudinal” direction may be parallel to an indicated “Y” axis, may be perpendicular to an indicated “X” axis, and may be perpendicular to an indicated “Z” axis.

As used herein, the term “vertical” means and includes a direction that is perpendicular to a primary surface of the substrate on which a referenced material or structure is located. The “height” of a respective material or structure may be defined as a dimension in a vertical plane. With reference to the figures, the “vertical” direction may be parallel to an indicated “Z” axis, may be perpendicular to an indicated “X” axis, and may be perpendicular to an indicated “Y” axis.

As used herein, the term “width” means and includes a dimension, along an indicated “X” axis in a horizontal plane (e.g., at a certain elevation, if identified), defining a maximum distance, along such “X” axis in the horizontal plane, of the material or structure in question.

As used herein, the term “length” means and includes a dimension, along an indicated “Y” axis in a horizontal plane (e.g., at a certain elevation, if identified), defining a maximum distance, along such “Y” axis in the horizontal plane, of the material or structure in question.

As used herein, the terms “thickness” or “thinness” are spatially relative terms that mean and include a dimension in a straight-line direction that is normal to the closest surface of an immediately adjacent material or structure that is of a different composition or that is otherwise distinguishable from the material or structure whose thickness, thinness, or height is discussed.

As used herein, the term “between” is a spatially relative term used to describe the relative disposition of one material or structure relative to at least two other materials or structures. The term “between” may encompass both a disposition of one material or structure directly adjacent the other materials or structures and a disposition of one material or structure indirectly adjacent to the other materials or structures.

As used herein, the term “proximate” is a spatially relative term used to describe disposition of one material or structure near to another material or structure. The term “proximate” includes dispositions of indirectly adjacent to, directly adjacent to, and internal to.

As used herein, the term “neighboring,” when referring to a material or structure, is a spatially relative term that means and refers to a next, most proximate material or structure of an identified composition or characteristic. Materials or structures of other compositions or characteristics than the identified composition or characteristic may be disposed between one material or structure and its “neighboring” material or structure of the identified composition or characteristic. For example, a structure of material X “neighboring” a structure of material Y is the first material X structure, e.g., of multiple material X structures, that is most proximate to the particular structure of material Y. The “neighboring” material or structure may be directly adjacent or indirectly adjacent the structure or material of the identified composition or characteristic.

As used herein, the term “consistent”—when referring to a parameter, property, or condition of one structure, material, feature, or portion thereof in comparison to the parameter, property, or condition of another such structure, material, feature, or portion of such same aforementioned structure, material, or feature—is a relative term that means and includes the parameter, property, or condition of the two such structures, materials, features, or portions being equal, substantially equal, or about equal, at least in terms of respective dispositions of such structures, materials, features, or portions. For example, two structures having “consistent” thickness as one another may each define a same, substantially same, or about the same thickness at X lateral distance from a feature, despite the two structures being at different elevations along the feature.

As used herein, the term “substantially,” when referring to a parameter, property, or condition, means and includes the parameter, property, or condition being equal to or within a degree of variance from a given value such that one of ordinary skill in the art would understand such given value to be acceptably met, such as within acceptable manufacturing tolerances. By way of example, depending on the particular parameter, property, or condition that is substantially met, the parameter, property, or condition may be “substantially” a given value when the value is at least 90.0 percent met, at least 95.0 percent met, at least 99.0 percent met, or even at least 99.9 percent met.

As used herein, the terms “on” or “over,” when referring to an element as being “on” or “over” another element, are spatially relative terms that mean and include the element being directly on top of, adjacent to (e.g., laterally adjacent to, horizontally adjacent to, longitudinally adjacent to, vertically adjacent to), underneath, or in direct contact with the other element. It also includes the element being indirectly on top of, adjacent to (e.g., laterally adjacent to, horizontally adjacent to, longitudinally adjacent to, vertically adjacent to), underneath, or near the other element, with other elements present therebetween. In contrast, when an element is referred to as being “directly on” or “directly adjacent to” another element, there are no intervening elements present.

As used herein, the terms “level” and “elevation” are spatially relative terms used to describe one material's or feature's relationship to another material(s) or feature(s) as illustrated in the figures, using—as a reference point—the lowest illustrated surface of the structure that includes the materials or features. As used herein, a “level” and an “elevation” are each defined by a horizontal plane parallel to a primary surface of the substrate or base structure on or in which the structure (that includes the materials or features) is formed. When used with reference to the drawings, “lower levels” and “lower elevations” are relatively nearer to the bottom-most illustrated surface of the respective structure, while “higher levels” and “higher elevations” are relatively further from the bottom-most illustrated surface of the respective structure.

As used herein, the term “depth” is a spatially relative term used to describe one material's or feature's relationship to another material(s) or feature(s) as illustrated in the figures, using—as a reference point—the highest illustrated surface of the structure that includes the materials or features. When used with reference to the drawings, a “depth” is defined by a horizontal plane parallel to the highest illustrated surface of the structure that includes the materials or features.

Unless otherwise specified, any spatially relative terms used in this disclosure are intended to encompass different orientations of the materials in addition to the orientation as depicted in the drawings. For example, the materials in the drawings may be inverted, rotated, etc., with the “upper” levels and elevations then illustrated proximate the bottom of the page, the “lower” levels and elevations then illustrated proximate the top of the page, and the greatest “depths” extending a greatest vertical distance upward.

As used herein, the terms “comprising,” “including,” “having,” and grammatical equivalents thereof are inclusive, open-ended terms that do not exclude additional, unrecited elements or method steps. These terms also include more restrictive terms “consisting of” and “consisting essentially of” and grammatical equivalents thereof. Therefore, a structure described as “comprising,” “including,” and/or “having” a material may be a structure that, in some embodiments, includes additional material(s) as well and/or a structure that, in some embodiments, does not include any other material(s). Likewise, a material (e.g., composition) described as “comprising,” “including,” and/or “having” a species may be a material that, in some embodiments, includes additional species as well and/or a material that, in some embodiments, does not include any other species.

As used herein, “and/or” means and includes any and all combinations of one or more of the associated listed items.

As used herein, an “(s)” at the end of a term means and includes the singular form of the term and/or the plural form of the term, unless the context clearly indicates otherwise.

As used herein, the terms “configured” and “configuration” mean and refer to a size, shape, material composition, orientation, and arrangement of a referenced material, structure, assembly, or apparatus so as to facilitate a referenced operation or property of the referenced material, structure, assembly, or apparatus in a predetermined way.

The illustrations presented herein are not meant to be actual views of any particular material, structure, sub-structure, region, sub-region, device, system, or stage of fabrication, but are merely idealized representations that are employed to describe embodiments of the disclosure.

Embodiments are described herein with reference to cross-sectional illustrations that are schematic illustrations. Accordingly, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, embodiments described herein are not to be construed as limited to the particular shapes or structures as illustrated but may include deviations in shapes that result, for example, from manufacturing techniques. For example, a structure illustrated or described as box-shaped may have rough and/or nonlinear features. Moreover, sharp angles that are illustrated may be rounded; surfaces and features illustrated to be vertical may be non-vertical, bent, and/or bowed; and/or structures illustrated with consistent transverse widths and/or lengths throughout the height of the structure may taper in transverse width and/or length. Thus, the materials, features, and structures illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the precise shape of a material, feature, or structure and do not limit the scope of the present claims.

The following description provides specific details, such as material types and processing conditions, to provide a thorough description of embodiments of the disclosed apparatus (e.g., devices, systems) and methods. However, a person of ordinary skill in the art will understand that the embodiments of the apparatus and methods may be practiced without employing these specific details. Indeed, the embodiments of the apparatus and methods may be practiced in conjunction with conventional semiconductor fabrication techniques employed in the industry.

The fabrication processes described herein do not form a complete process flow for processing apparatus (e.g., devices, systems) or the structures thereof. The remainder of the process flow is known to those of ordinary skill in the art. Accordingly, only the methods and structures necessary to understand embodiments of the present apparatus (e.g., devices, systems) and methods are described herein.

Unless the context indicates otherwise, the materials described herein may be formed by any suitable technique including, but not limited to, spin coating, blanket coating, chemical vapor deposition (“CVD”), atomic layer deposition (“ALD”), plasma enhanced ALD, physical vapor deposition (“PVD”) (e.g., sputtering), or epitaxial growth. Depending on the specific material to be formed, the technique for depositing or growing the material may be selected by a person of ordinary skill in the art.

Unless the context indicates otherwise, the removal of materials described herein may be accomplished by any suitable technique including, but not limited to, etching (e.g., dry etching, wet etching, vapor etching), ion milling, abrasive planarization, or other known methods.

In referring to the drawings, like numerals refer to like components throughout. The drawings are not necessarily drawn to scale.

With reference toFIG.1, illustrated is a microelectronic device structure100that includes a stack102(which may otherwise be referred to herein as a “stack structure” or as a “tiered stack”) of vertically alternating (e.g., vertically interleaved) insulative structures104and conductive structures106arranged in tiers108. Each tier108may include at least one insulative structure104and at least one conductive structure106. In some embodiments, each tier108includes a single one of the insulative structures104and a single one of the conductive structures106.

WhileFIG.1illustrates about sixty (60) tiers108(e.g., sixty (60) conductive structures106) in the stack102, the disclosure is not so limiting. For example, a microelectronic device structure, in accordance with embodiments of the disclosure, may include a different quantity of the tiers108(e.g., and of the conductive structures106) in the stack102. In some embodiments, the stack102includes one-hundred twenty-eight of the tiers108(and of the conductive structures106). The number (e.g., quantity) of the tiers108—and therefore of the conductive structures106—of the stack102may be within a range of from thirty-two to three-hundred or more.

The conductive structures106may be formed of and include (e.g., each be formed of and include) one or more conductive materials, such as one or more of: at least one metal (e.g., one or more of tungsten, titanium, nickel, platinum, rhodium, ruthenium, iridium, aluminum, copper, molybdenum, silver, gold), at least one alloy (e.g., an alloy of one or more of the aforementioned metals), at least one metal-containing material that includes one or more of the aforementioned metals (e.g., metal nitrides, metal silicides, metal carbides, metal oxides, such as a material including one or more of titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), titanium aluminum nitride (TiAlN), iridium oxide (IrOx), ruthenium oxide (RuOx), alloys thereof), at least one conductively-doped semiconductor material (e.g., conductively-doped silicon, conductively-doped germanium, conductively-doped silicon germanium), polysilicon, and at least one other material exhibiting electrical conductivity. In some embodiments, the conductive structures106include at least one of the aforementioned conductive materials along with at least one additional of the aforementioned conductive materials formed as a liner. Some or all of the conductive structures106may have the same (e.g., consistent) or different thicknesses (e.g., heights) as one another.

The insulative structures104may be formed of and include (e.g., each be formed of and include) at least one insulative material, such as a dielectric oxide material (e.g., silicon dioxide). In this and other embodiments described herein, the insulative material of the insulative structures104may be substantially the same as or different than other insulative material(s) of the microelectronic device structure100. Some or all of the insulative structures104may have the same (e.g., consistent) or different thicknesses (e.g., heights) as one another. In some embodiments, some of the insulative structures104(e.g., an uppermost, a lowest, and/or intermediate insulative structures104) are relatively thicker than others of the insulative structures104in the stack102.

The stack102may be provided on or over a base structure110, which may be formed of and include, for example, one or more semiconductor materials (e.g., polycrystalline silicon (polysilicon)) doped with one or more P-type conductivity chemical species (e.g., one or more of boron, aluminum, and gallium) or one or more N-type conductivity chemical species (e.g., one or more of arsenic, phosphorous, and antimony) to provide a source/drain region of the microelectronic device structure100.

In addition to the semiconductor materials and/or source/drain region, the base structure110may include other base material(s) or structure(s), such as conductive regions for making electrical connections with other conductive structures of the device that includes the microelectronic device structure100. In some such embodiments, CMOS (complementary metal-oxide-semiconductor) circuitry is included, within the base structure110, in a CMOS region below the source/drain region, which CMOS region may be characterized as a so-called “CMOS under Array” (“CuA”) region.

A series of slits or other elongate structures may extend through the stack102to divide the stack102into a series of blocks112that extend in the lateral direction (e.g., with a greater dimension (e.g., width) in the “X”-axis direction than a dimension (e.g., length) in the “Y”-axis direction). For example, a pair of slits may be formed, parallel to the “X”-axis ofFIG.1, to define the front and rear of the block112of the microelectronic device structure100illustrated inFIG.1. A longitudinally forward and/or rearward neighboring block, to the block112ofFIG.1, may be similarly structured to the block112ofFIG.1such that the illustration ofFIG.1may represent such neighboring block(s) as well. Alternatively, such neighboring blocks may have structures substantially mirrored to that of the block112ofFIG.1, reflected about the slit that separates the blocks112from one another.

Other portions of the microelectronic device structure100(e.g., portions horizontally disposed relative to the portions illustrated in, e.g.,FIG.1) may include array(s) of pillars (e.g., including channel material and memory material) extending through the stack102and to and/or into the base structure110(e.g., to and/or into a source/drain region). The pillars may effectuate the formation of strings of memory cells of a memory device (e.g., a memory device including any of the microelectronic device structures described or illustrated herein). The conductive structures106of the tiers108may be coupled to, or may form control gates of, the memory cells effectuated by the pillars. For example, each conductive structure106may be coupled to an individual memory cell of a particular string (e.g., effectuated by a particular pillar) of memory cells.

To facilitate electrical communication to particular selected conductive structures106within the stack102, conductive contact structures extend to (or from) and physically contact the conductive structures106of the tiers108. Each such conductive contact structure is positioned to physically contact a particular one of the conductive structures106at a step114(e.g., a landing area provided by an exposed upper (e.g., horizontal) surface portion of one of the conductive structures106). These conductive contact structures physically contacting the steps114may be referred to herein as “step contacts116.”

To provide the steps114of the conductive structures106, the stack102is patterned (e.g., etched) to expose, at various levels, one or more upper (e.g., horizontal) surface area portion of each conductive structure106. That is, the tiers108are selectively patterned to remove portions of otherwise-overlying tiers108to leave exposed at least one upper surface area of the conductive structure106of the next lower tier108. Each exposed area provides one of the steps114for the respective tier108(and conductive structure106).

Because individual conductive structures106in the stack102may occupy different elevations of the stack102(also referred to herein as different “tier elevations”), the steps114are formed at the various elevations of the conductive structures106, and the step contacts116extend downward to physically contact (e.g., “land on”) respective steps114. The height of an individual step contact116may be tailored according to the depth (e.g., elevation) of its respective step114. The step contacts116extending to steps114in the highest elevations of the stack102may be generally shorter than the step contacts116that extend to steps114in the lowest elevations of (deepest into) the stack102. The microelectronic device structure100may include, in each respective block112, at least one step contact116per step114and, therefore, at least one step contact116per tier108(e.g., and therefore per conductive structure106) in the stack102.

The tiers108of the stack102are patterned so that at least some of the tiers108(and, therefore, at least some of the conductive structures106) of the stack102provide multiple steps114or relatively-wider and/or relatively-longer steps114, each for landing at least one respective step contact116. Multiple step contacts116extend to each such tier108(and its conductive structure106).

In some embodiments, the tiers108connected with multiple step contacts116(and, in some embodiments, having multiple steps114) may be the deepest (e.g., lowest) tiers108of the stack102, where the step contacts116extend relatively greater vertical distances and therefore have relatively greater heights and higher aspect ratios compared to the step contacts116that extend to the higher-elevated steps114. Reliable fabrication of such high-aspect-ratio step contacts116tends to be particularly challenging, as discussed further below. Therefore, should one such step contact116be errantly fabricated in a manner that results in the step contact116not physically contacting a respective conductive structure106, the other(s) of the multiple step contacts116may nonetheless provide electrical communication to the conductive structure106, e.g., via physical connection to the other(s) of the multiple steps114of the tier108(or to another portion of the relatively-wider and/or relatively-longer step114of the tier108).

The steps114may be grouped, e.g., according to depth, in staircases having a series of the steps114. For example, one series of steps114may be formed at successively increasing tier108(and conductive structure106) depths (e.g., decreasing tier108elevations) to define a descending staircase118having generally negative slope. Elsewhere, another series of steps114may be formed at successively decreasing tier108(and conductive structure106) depths (e.g., increasing tier108elevations) to define an ascending staircase120having generally positive slope. In some embodiments, the elevation difference between neighboring steps114of the staircases (e.g., one of the descending staircases118, one of the ascending staircases120) is a “rise” or “fall” of the height of one tier108.

The staircases (e.g., the descending staircases118and the ascending staircases120) may be grouped in so-called “stadiums”122, which may be arranged in a series (e.g., first stadium124, second stadium126, third stadium128, fourth stadium130) across a width of the block112of the microelectronic device structure100. The microelectronic device structure100may include as many stadiums122within a respective block112as necessary to include at least one step114per tier108(and per conductive structure106) of the stack102.

Neighboring stadiums122may be spaced from one another by a so-called “crest”132of the stack102. The crests132may be formed by areas of the stack102where the tiers108have not been patterned. The crests132may, therefore, extend an entire height of the stack102.

Another non-patterned portion of the stack102forms a so-called “bridge”134that extends a width of the block112. The bridge134may border one of the slits that define the block112. Via the bridge134, distal portions of a given conductive structure106of a respective tier108are part of a continuous, single conductive structure106at that tier108elevation. Therefore, multiple steps114provided by a given tier108(e.g., a given conductive structure106thereof) remain in electrical communication with one another, regardless of where (e.g., laterally or longitudinally) along the block112each of the multiple steps114are provided for that tier108(e.g., for that conductive structure106).

In some embodiments, such as with the microelectronic device structure100ofFIG.1, the tiers108that include multiple steps114, and that are associated with multiple step contacts116, provide the multiple steps114within the staircases of a single stadium122, referred to herein as a “multi-step-per-tier stadium”136. At least one multi-step-per-tier stadium136within an individual block112of the stack102may be a deepest stadium122of the stack102. Thus, in the multi-step-per-tier stadiums136, each of at least some of the “stepped tiers”138of the stadium122includes multiple steps114.

As used herein, a “stepped tier” means and refers to a tier108of the stack102that defines at least one step114(e.g., at least one landing area for the conductive structure106of the tier108).

To provide the multiple steps114per stepped tier138in the multi-step-per-tier stadium136, the tiers108may be patterned to define a stadium profile having multiple staircases, at least a portion of each of which being defined in the same elevations (e.g., the same tier108levels of the stack102) as one another. Therefore, each stepped tier138providing multiple steps includes one step114in one staircase and one or more additional steps114in one or more of the additional staircase(s) of the multi-step-per-tier stadium136.

The portion ofFIG.1indicated by box140illustrates a staircase profile for the multi-step-per-tier stadium136. Alternative staircase profiles for the multi-step-per-tier stadiums136are illustrated in each ofFIG.2AthroughFIG.2D, and any one of which may replace that which is illustrated in either or both boxes140ofFIG.1(or in any other box140of microelectronic device structures illustrated in the figures).

In some embodiments, one or more pairs of opposing staircases provide the multiple staircases to provide the multiple steps114per stepped tier138of the multi-step-per-tier stadium136, such as the descending staircase118and the ascending staircase120illustrated in box140ofFIG.1,FIG.2A, andFIG.2B. As illustrated in these figures, the profile and structure of the descending staircase118may substantially mirror the profile and structure of the ascending staircase120. Thus, each stepped tier138includes one step114in the descending staircase118and one step114in the ascending staircase120.

With regard to box140ofFIG.1, a staircase landing142, to which the descending staircase118descends and from which the ascending staircase120ascends, may be provided by an upper surface of one of the insulative structures104, exposed through an opening in the lowest conductive structure106of the stepped tiers138of the respective multi-step-per-tier stadium136. Therefore, the multiple steps114of the lowest stepped tier138of the multi-step-per-tier stadium136may be to the left and right lateral sides of the staircase landing142.

With regard to box140ofFIG.2A, in some embodiments the lowest stepped tier138of a respective one of the multi-step-per-tier stadiums136may be a nonpatterned conductive structure106, such that the lowest step114of each opposing staircases (e.g., the ascending staircase120, the descending staircase118) is a shared, single lowest step202(e.g., a single exposed upper surface portion of one of the conductive structures106) to which extend multiple (e.g., two) step contacts116, rather than multiple distinct steps114as in the box140area ofFIG.1. Therefore, the lowest step202provides the lowest step114of the descending staircase118and also the lowest step114of the ascending staircase120, and the multiple step contacts116extend to this single lowest step114. The lowest step114may be relatively wider than the individual steps114in the above tier108elevations of the descending staircase118and the ascending staircase120.

While box140ofFIG.1andFIG.2Aillustrate the descending staircase118of each multi-step-per-tier stadium136as descending toward the ascending staircase120of that multi-step-per-tier stadium136, providing a “V”-shaped staircase profile across the width of the multi-step-per-tier stadium136, in other embodiments, such as that illustrated inFIG.2B, the ascending staircase120ascends toward the descending staircase118, providing an inverted “V”-shaped staircase profile. A single highest step204(e.g., a single exposed upper surface portion of one of the conductive structures106) may provide both a highest step114of the ascending staircase120and the highest step114of the descending staircase118. Multiple step contacts116may extend to this single, highest step114, which highest step114may be relatively wider than the individual steps114in the lower tier108elevations of the ascending staircase120and the descending staircase118.

While box140ofFIG.1,FIG.2A, andFIG.2Billustrate the multiple staircases configured as opposing pairs of staircases (e.g., the descending staircase118and the ascending staircase120) with substantially laterally mirrored structures and profiles, in other embodiments, the multiple staircases of the multi-step-per-tier stadium136may share substantially the same structure without lateral mirroring. For example, and with reference toFIG.2C, the multi-step-per-tier stadium136may include multiple ascending staircases120, each with substantially the same elevational profile. As another example, and with reference toFIG.2D, the multi-step-per-tier stadium136may include multiple descending staircases118, each with substantially the same elevational profile.

Accordingly, the at least one multi-step-per-tier stadium136of the microelectronic device structure100is configured with a staircase profile providing multiple steps114per at least some of the stepped tiers138, such as with multiple staircases formed through the same tier108elevations as one another. At least one step contact116extends to each step114of the multiple steps114in the multi-step-per-tier stadium136. Therefore, should one step contact116happen to fail (e.g., due to fabrication errors or other reason(s)) to provide electrical communication to its respective step114and stepped tier138, at least one other step contact116is associated with the same stepped tier138to provide the electrical communication to the conductive structure106(e.g., word line) of the stepped tier138via the same or an additional step114.

With returned reference toFIG.1, while at least one stadium122of the block112is configured as the multi-step-per-tier stadium136, one or more other stadiums122of the block112may be configured with only a single step114per stepped tier138. Such stadiums122may be referred to herein as “single-step-per-tier stadiums”144.

To provide a single step114per stepped tier138in the single-step-per-tier stadium144, the single-step-per-tier stadium144may include one or more staircases that, together, provide steps114each at a different tier108elevation. The portion ofFIG.1indicated by box146illustrates a staircase profile for the single-step-per-tier stadium144. Alternative staircase profiles for the single-step-per-tier stadium144are illustrated in each ofFIG.3AthroughFIG.3E, and any one of which may replace that which is illustrated in either or both of boxes146ofFIG.1(or in any other box146of microelectronic device structures illustrated in the figures).

In some embodiments, one or more pairs of opposing and vertically-offset staircases may provide the multiple staircases that together define the single step114per stepped tier138of the single-step-per-tier stadium144, such as the descending staircase118and the ascending staircase120illustrated in the box140of any ofFIG.1,FIG.3A,FIG.3B, andFIG.3C. Thus, one staircase is formed in tier108elevations above the tier108elevations in which at least one other staircase is formed. An offset148of multiple tiers108vertically separates the final step114of one staircase from the beginning step114of the opposing staircase. The offset148may be at least the number of tiers108(e.g., the quantity of stepped tiers138) in which lower of the pair of opposing, vertically-offset staircases is formed.

In some embodiments—such as those illustrated in box146ofFIG.1andFIG.3A—the descending staircase118descends toward the offset148and the ascending staircase120, and the ascending staircase120ascends away from the offset148and the descending staircase118. Thus, the opposing, vertically-offset staircases are generally angled toward the center of the single-step-per-tier stadium144. In other embodiments—such as those illustrated in box146ofFIG.3BandFIG.3C—the ascending staircase120ascends toward the offset148and the descending staircase118, and the descending staircase118descends away from the offset148and the ascending staircase120. Thus, the opposing, vertically-offset staircases are generally angled away from the center of the single-step-per-tier stadium144.

In some embodiments—such as those illustrated in box146ofFIG.1andFIG.3C—the descending staircase118is formed in tier108elevations above those in which the ascending staircase120is formed. In other embodiments—such as those illustrated in box146ofFIG.3AandFIG.3B—the ascending staircase120is formed in tier108elevations above those in which the descending staircase118is formed.

In some embodiments—such as that illustrated in box146ofFIG.1—the final (e.g., lowest) step114of the descending staircase118is vertically spaced, by the offset148, above the beginning (e.g., lowest) step114of the ascending staircase120. In some embodiments—such as that illustrated in box146ofFIG.3A—the final (e.g., lowest) step114of the descending staircase118is vertically spaced, by the offset148, below the beginning (e.g., lowest) step114of the ascending staircase120. In some embodiments—such as that illustrated in box146ofFIG.3B—the final (e.g., highest) step114of the ascending staircase120is vertically spaced, by the offset148, above the beginning (e.g., highest) step114of the descending staircase118. In some embodiments—such as that illustrated in box146ofFIG.3C—the final (e.g., highest) step114of the ascending staircase120is vertically spaced, by the offset148, below the beginning (e.g., highest) step114of the descending staircase118.

While box146ofFIG.1andFIG.3AthroughFIG.3Cillustrate multiple staircases configured as opposing, vertically-offset pairs with the descending staircase118and the ascending staircase120, in other embodiments, a single staircase may extend through all tier108elevations of the stepped tiers138to provide the single step114per stepped tier138in the single-step-per-tier stadiums144. For example, and with reference toFIG.3D, the single-step-per-tier stadium144may include a single ascending staircase120. As another example, and with reference toFIG.3E, the single-step-per-tier stadium144may include a single descending staircase118.

Accordingly, the at least one single-step-per-tier stadium144of the microelectronic device structure100is configured with a staircase profile providing a single step114per stepped tier138, such as with at least one staircase providing steps114at different tier108elevations of the single-step-per-tier stadium144. A single step contact116extends to each respective one of the steps114.

With continued reference toFIG.1, in embodiments in which the microelectronic device structure100includes one or more single-step-per-tier stadiums144, the single-step-per-tier stadiums144may be formed in the relatively higher elevations of the stack102, such as where the heights of the step contacts116are relatively shorter than the heights of the step contacts116that extend to the relatively lower elevations of the stack102. The relatively-shorter step contacts116may experience relatively fewer fabrication challenges, compared to fabrication challenges of the relatively-taller step contacts116, and may, therefore, be less likely to experience fabrication errors that would cause electrical communication failures with the respective conductive structures106(e.g., word lines) in the upper elevations of the stack102.

The stadiums122of the microelectronic device structure100may be arranged in a series across the width of the block112, and the staircase profiles of the stadiums122may be formed to as to provide at least one step114per tier108(e.g., per conductive structure106) of the stack102. In some embodiments, such as that illustrated inFIG.1, the depths of the stadiums122may increase with increased lateral distance across the block112. Therefore, the steps114of a first stadium124may be in tier108elevations above the steps114of a second stadium126, which may be in tier108elevations above the steps114of a third stadium128, which may be in tier108elevations above the steps114of a fourth stadium130, etc. In other embodiments, the stadiums122may not be arranged in relatively increasing or decreasing depths across the series of the block112. For example, one stadium122may be relatively deeper than laterally neighboring stadiums122, and/or one stadium122may be relatively shallower than laterally neighboring stadiums122.

In some embodiments, regardless of the order and sequence of the various stadium122depths, one or more of the relatively deeper stadiums122(e.g., the third stadium128and the fourth stadium130ofFIG.1) may be configured as the multi-step-per-tier stadiums136, while one or more relatively shallower stadiums122(e.g., the first stadium124and the second stadium126ofFIG.1) may be configured as the single-step-per-tier stadiums144. The staircase profiles of each multi-step-per-tier stadium136of the block112may be the same or different as one another, and/or the staircase profiles of each single-step-per-tier stadium144, if any, of the block112may be the same or different as one another.

WhileFIG.1illustrates a series of four stadiums122, the disclosure is not so limited. The stadiums122of the series of the block112may include additional stadiums122, e.g., in an intermediate region150or in regions laterally adjacent any of the stadiums122illustrated inFIG.1. The additional stadiums122may be either multi-step-per-tier stadiums136(e.g., with a staircase profile of any of box140ofFIG.1,FIG.2A,FIG.2B,FIG.2C, andFIG.2Dor any other staircase profile(s) configured for multiple step contacts116per stepped tier138) or single-step-per-tier stadiums144(e.g., with a staircase profile of any of box146ofFIG.1,FIG.3A,FIG.3B,FIG.3C,FIG.3D, andFIG.3E).

Accordingly, disclosed is a microelectronic device. The microelectronic device comprises a stack structure comprising a vertically alternating sequence of insulative structures and conductive structures arranged in tiers. Each of the tiers comprises at least one of the conductive structures and at least one of the insulative structures. The microelectronic device also comprises stadiums within the stack structure. At least one of the stadiums comprises two staircases having steps provided by a group of the conductive structures. Step contacts extend to the steps of the two staircases of the at least one of the stadiums. Each conductive structure of the group of conductive structures has more than one of the step contacts in contact therewith at at least one of the steps of the two staircases.

With reference toFIG.4, illustrated is the microelectronic device structure100ofFIG.1and further illustrating routing lines402formed to electrically connect the step contacts116with additional conductive contact structures (referred to herein as “through-stack contacts”404), which may be disposed within the horizontal area of the crests132of the stack102. The through-stack contacts404may extend through the height of the stack102to the base structure110(e.g., to or through a source/drain region in the base structure110, e.g., to additional routing lines or other conductive features below the stack102).

For each stepped tier138of the single-step-per-tier stadiums144, one routing line402may extend between one through-stack contact404and one step contact116. Therefore, the one (e.g., single) routing line402may electrically connect the one (e.g., single) through-stack contact404, the one (e.g., single) step contact116, and the one (e.g., single) step114(and, therefore, the one conductive structure106that provides the step114) to which the one step contact116extends. Thus, the one conductive structure106may be in shared electrical communication with the one through-stack contact404via a single (e.g., only one) electrical communication route (e.g., conductive path).

For each stepped tier138of the multi-step-per-tier stadiums136, at least one routing line402extends between one through-stack contact404and each of the multiple step contacts116that extend to the conductive structure106(e.g., to multiple steps114of the one conductive structure106) of the stepped tier138. Thus, the one conductive structure106is in electrical communication with the one through-stack contact404through multiple electrical communication routes (e.g., multiple conductive paths). In some embodiments, one or more junctions406facilitate the electrical communication between the multiple step contacts116and the single through-stack contact404. For example, one routing line402may extend between one of the multiple step contacts116and the junction406, one additional routing line402may extend between one additional of the multiple step contacts116and the junction406, and one further routing line402may extend between the junction406and the one through-stack contact404. However, the disclosure is not limited to this arrangement, and the routing lines402connecting multiple step contacts116to a respective single through-stack contact404may be otherwise configured.

With reference toFIG.5, illustrated is the microelectronic device structure100ofFIG.1andFIG.4, including a schematic illustration of the routing lines402and the through-stack contacts404ofFIG.4to more clearly illustrate the one-to-one shared electrical communication between the through-stack contacts404and the step contacts116(and therefore the steps114and conductive structures106) of the single-step-per-tier stadium144and the one-to-multiple shared electrical communication between the through-stack contacts404and the step contacts116(and therefore the steps114and conductive structures106) of the multi-step-per-tier stadiums136. The through-stack contact404are schematically represented by squares above the crests132, though the physical through-stack contact404structures may be formed and disposed within the horizontal area of the crests132, extending through the height of the stack102to and/or into a source/drain region in the base structure110(e.g., as illustrated inFIG.4).

In some embodiments, the multiple steps114provided by a respective stepped tier138—at a respective tier108elevation of the stack102—are each associated with one of multiple step contacts116that are in electrical communication with a single through-stack contact404.

Still referring toFIG.5, one or more dielectric material(s)502may substantially fill openings (e.g., trenches), referred to herein as “stadium openings” (e.g., “stadium trenches”) vertically overlying and partially defined by the stadiums122(e.g., the single-step-per-tier stadiums144, if any, and the multi-step-per-tier stadiums136) and electrically insulating the step contacts116from one another. The step contacts116vertically extend through the dielectric material(s)502of the filled stadium openings to the steps114of the stadiums122. For ease of illustration,FIG.1throughFIG.4did not illustrate the dielectric material(s)502. The dielectric material(s)502may be formed of and include any one or more insulative materials described above.

With reference toFIG.6, illustrated is the structure ofFIG.5, but wherein one of the step contacts116—a so-called “under-formed step contact”604—has been errantly fabricated (e.g., due to a fabrication error such as incomplete formation of a contact opening in which the step contact116was formed, as further discussed below), leaving a gap602between the base of the under-formed step contact604and the step114to which it was intended to extend, if fabricated correctly.

Had the under-formed step contact604been formed for one of the single-step-per-tier stadiums144(or otherwise been directed to a step114of a single-step stepped tier138), the under-formed step contact's604failure to physically contact its associated step114would inhibit electrical communication between the conductive structure106providing that step114and its associated through-stack contact404. However, for the multi-step-per-tier stadium136, the inclusion of multiple step contacts116per stepped tier138facilitates the electrical communication to the conductive structure106despite the under-formed step contact604. That is, if one of multiple step contacts116associated with a particular stepped tier138(e.g., the lowest stepped tier138of the multi-step-per-tier stadium136) happens to be formed as the under-formed step contact604, failing to physically contact the conductive structure106of the stepped tier138, one or more others of the multiple step contacts116, accurately fabricated and associated with that particular stepped tier138(e.g., the lowest stepped tier138), nonetheless provides the electrical communication to the conductive structure106.

The inclusion of multiple step contacts116(e.g., and, in some embodiments, multiple steps114) per stepped tier138for the multi-step-per-tier stadium136may significantly lessen the likelihood of failure of an electrical communication to particular conductive structures106in the multi-step-per-tier stadium136. That is, with multiple step contacts116per stepped tier138(per conductive structure106), the so-called “failure rate” of the stepped tier138(herein the “TFR”)—meaning the likelihood of being unable to electrically communicate with a particular stepped tier138(conductive structure106)—is statistically equivalent to the individual step contact's116likelihood of failing (herein the “IRF”) taken to the power of the quantity (herein “n”) of the multiple step contacts116per stepped tier138. That is, TFR=(IRF){circumflex over ( )}n.

For example, in embodiments such as that ofFIG.6, in which two step contacts116(i.e., n=2) are associated with a particular stepped tier138(and therefore a particular conductive structure106), if the likelihood of one step contact116experiencing a fabrication failure is, e.g., 10% (i.e., IRF=0.10), then the tier failure rate (TFR) (e.g., likelihood of both stepped step contacts116experiencing failure, as would be necessary to inhibit electrical communication to the particular stepped tier138(conductive structure106))—becomes 1% (i.e., TFR=(0.10){circumflex over ( )}2=0.01=1%). In another embodiment including three steps114per stepped tier138(and conductive structure106) (i.e., n=3), a 10% individual fail rate (i.e., IFR=0.10) equates to a tier (conductive structure106) failure rate (TFR) of 0.1% (i.e., TFR=(0.10){circumflex over ( )}3=0.001=0.1%).

When considered with respect to the likelihood of any one stepped tier138of a multi-step-per-tier stadium136failing, this “stadium failure rate” (herein “SFR”) may be further significantly improved due to the inclusion of multiple step contacts116(and, in some embodiments, multiple steps114) per stepped tier138of the multi-step-per-tier stadium136. Statistically, the SFR equates to the TFR multiplied by the quantity (herein “m”) of the stepped tiers138in the multi-step-per-tier stadium136, i.e., SFR=TFR×m=((IFR){circumflex over ( )}n)×m.

For example, in embodiments such as that ofFIG.6, in which one multi-step-per-tier stadium136includes five stepped tiers138(conductive structures106) (i.e., m=5), each with two steps114and associated with two step contacts116(i.e., n=2), if the likelihood of one step contact116experiencing a fabrication failure is, e.g., 10% (i.e., IFR=0.10), then the stadium failure rate (SFR) becomes 5% (i.e., SFR=((0.1){circumflex over ( )}2)×5=(0.01)×5=0.05=5%). In contrast, the SFR for single-step-per-tier stadium144statistically equates to IFR×m. Therefore, if the single-step-per-tier stadium144includes five stepped tiers138(conductive structures106) (i.e., m=5), a 10% individual failure rate (e.g., IFR=0.10), equates to an SFR of 50% (i.e., SFR=0.10×5=0.50=50%), which is a significantly greater stadium failure rate than the 5% SFR of the multi-step-per-tier stadium136example.

As illustrated inFIG.1andFIG.4throughFIG.6, the multiple step contacts116associated with a single one of the conductive structures106(e.g., providing multiple steps114) of a single one of the stepped tiers138may be step contacts116that are within a horizontal area of a common one of the stadiums122(e.g., a common multi-step-per tier stadium136). Each group (e.g., pair) of multiple step contacts116may each extend to different steps114provided by the same stepped tier138or may extend to a same step (e.g., the single lowest step202ofFIG.2A, the single highest step204ofFIG.2B) provided by the stepped tier138.

While the microelectronic device structure100ofFIG.1andFIG.4throughFIG.6include stepped tiers138that provide multiple steps114(and associated with multiple step contacts116) for at least some stepped tiers138of a single stadium122(e.g., the multi-step-per-tier stadium136), in other embodiments, the multiple steps114provided by at least one stepped tier138may be steps114of different stadiums122. Moreover, the step contacts116associated with the one stepped tier138may be step contacts116within a horizontal area of different ones of the stadiums122.

For example, and with reference toFIG.7, a microelectronic device structure700includes at least one stepped tier138(at least one conductive structure106) with multiple steps114that are each defined in a respective one of a group (e.g., a pair) of duplicate stadiums702, such as neighboring relatively-deep stadiums122. Each of the duplicate stadiums702of a respective group (e.g., a pair) may have a staircase profile with steps114provided through the same tier108elevations as each other of the duplicate stadiums702of the group so as to provide one step114of a respective stepped tier138in one of the duplicate stadiums702and to provide a multiple step114of the respective stepped tier138in one other of the duplicate stadiums702. Therefore, each of the duplicate stadiums702of a respective group (e.g., pair) of duplicate stadiums702may be at the same (e.g., common) depth(s) in the stack102as one another.

Step contacts116extend to the steps114in a one-to-one association, for example, and routing lines402(and, in some embodiments, junctions406) may electrically connect one step contact116—extending to one step114of a stepped tier138of one of the duplicate stadiums702—to a multiple step contact116—extending to a multiple step114of the stepped tier138of a multiple of the duplicate stadiums702—and to a respective one of the through-stack contacts404in a neighboring crest132.

WhileFIG.7illustrates the microelectronic device structure700with a single pair of duplicate stadiums702that together provide two steps114per stepped tier138in the lowest ten tiers108of the stack102, in other embodiments, one or more additional duplicate stadiums702may be formed with steps114(and staircases) in the same tier108elevations, so as to provide more than two duplicate stadiums702together providing more than two multiple steps114per stepped tier138. More than two step contacts116may therefore extend, to the respective stepped tier138(and conductive structure106), each within the horizontal area of one of the different duplicate stadiums702of the group of multiple duplicate stadiums702.

One or more additional groups (e.g., pairs) of duplicate stadiums702with staircase profiles in an additional group of tier108elevations may provide an additional group of multiple steps114per stepped tier138, such as in the next ten tier108elevations of the stack102(e.g., in the intermediate region150). Additional groups (e.g., pairs) of multiple step contacts116may each extend to respective stepped tiers138of the additional tier108elevations.

The staircase profile of each duplicate stadium702may be any one of the staircase profiles described above for the single-step-per-tier stadiums144, illustrated in box146inFIG.1,FIG.3A,FIG.3B,FIG.3C,FIG.3D, andFIG.3E. The staircase profiles of each of an associated group (e.g., pair) of duplicate stadiums702may have the same configuration as one another, as illustrated inFIG.7, or may be differently configured (e.g., mirrored to one another or neither mirrored nor the same) provided the tier108elevations of the steps114of one of the duplicate stadiums702are the same tier108elevations of the steps114of another of the duplicate stadiums702.

WhileFIG.7illustrates the duplicate stadiums702of a particular group (e.g., pair) as being directly neighboring stadiums122(e.g., the third stadium128and the fourth stadium130of the block112(FIG.1)), in other embodiments, one or more others of the stadiums122may be interposed between the duplicate stadiums702of the particular group (e.g., pair). Such interposed stadium122(or stadiums122) may be one or more single-step-per-tier stadiums144, one or more multi-step-per-tier stadiums136(FIG.1), or one or more duplicate stadiums702of a different group (e.g., pair) of duplicate stadiums702.

Accordingly, the microelectronic device structure700provides at least some stepped tiers138with multiple steps114—and, therefore, at least some conductive structures106associated with multiple step contacts116—wherein at least one of the multiple steps114is within a different stadium122than at least one other of the multiple steps114, and at least one of the multiple step contacts116extends to a different stadium122than the stadium122to which at least one other of the multiple step contacts116extends.

Regardless of in which horizontal stadium area, of the multiple duplicate stadiums702, the individual step contacts116of a group (e.g., pair) of multiple step contacts116extend, the grouped multiple step contacts116may share electrical communication to a common one of the through-stack contacts404, as schematically illustrated inFIG.7.

With reference toFIG.8, in some embodiments, a microelectronic device structure800may provide multiple steps114and multiple step contacts116per at least one stepped tier138(at least one conductive structure106) by providing relatively-wider and/or relatively-longer steps114of the respective conductive structure106of the stepped tier138. For example, at least one stepped tier138may include a relatively-wider and/or relatively-longer step114compared to the steps114in stadiums122not providing multiple steps114per stepped tier138, such as compared to the single-step-per-tier stadiums144. The relatively-wider and/or relatively-longer steps114may provide, effectively, the surface area of multiple steps114of the single-step-per-tier stadiums144. These relatively-wider and/or relatively-longer steps114may each be at a different one of the tier108elevations of the stepped tiers138of the stadium122, which stadium122may be referred to herein as a “multi-step-contacts-per-tier stadium”802.

The staircase profile of the multi-step-contacts-per-tier stadium802may be any one of the staircase profiles described above for the single-step-per-tier stadiums144with respect to box146ofFIG.1,FIG.3A,FIG.3B,FIG.3C,FIG.3D, andFIG.3Ebut with relatively-wider and/or relatively-longer steps114. Accordingly, for example, the staircase profile of box804ofFIG.8is substantially equivalent to the staircase profile of the single-step-per-tier stadiums144illustrated in box146ofFIG.1(and inFIG.8), but with relatively double-width steps114. Thus, in any of the above-described multi-step-per-tier stadiums136, the staircase profile illustrated in box804ofFIG.8may alternatively replace the staircase profile of any above-described box140.

Multiple step contacts116extend to at least some (e.g., each) respective multiple-sized step114of the multi-step-contacts-per-tier stadium802. The multiple step contacts116for a respective stepped tier138may be electrically connected to a same (e.g., a common) one of the through-stack contacts404via routing lines402(and, in some embodiments, the junction406).

While the microelectronic device structure800ofFIG.8illustrates only a single multi-step-contacts-per-tier stadium802, providing relatively-larger steps114and multiple step contacts116for each of the stepped tiers138in the deepest ten tier108elevations of the stack102, in other embodiments, more than one of the stadiums122in a given block112(FIG.1) may be configured as the multi-step-contacts-per-tier stadium802, and these other multi-step-contacts-per-tier stadiums802may be formed in other groups of tier108elevations in the stack102(e.g., in the intermediate region150).

In some embodiments, all tiers108and/or all stadiums122of a given block112(FIG.1) may be associated with multiple step contacts116(and, in some embodiments, multiple steps114). For example, with reference toFIG.9, each stadium122of the block112(FIG.1) may be configured as any of the multi-step-per-tier stadiums136with any of the staircase profiles of box140ofFIG.1,FIG.3A,FIG.3B,FIG.3C,FIG.3D, andFIG.3Eor as the multi-step-contacts-per-tier stadium802(FIG.8) with the staircase profile of box804ofFIG.8.

Accordingly, disclosed are a microelectronic device. The microelectronic device comprises a stack structure comprising insulative structures vertically interleaved with conductive structures and arranged in tiers. A series of stadiums is in the stack structure. At least one of the stadiums has steps at least partially defined by the conductive structures of a first group of the tiers. At least one other of the stadiums has additional steps at least partially defined by the conductive structures of a second group of the tiers. The first group of the tiers is at elevations lower than elevations of the second group of the tiers. Conductive contacts are within horizontal areas of stadiums of the series of stadiums. The conductive contacts comprise pairs of the conductive contacts and ones of the conductive contacts. Each of the pairs of the conductive contacts extend to a different one of the conductive structures of the first group of the tiers than each other of the pairs of the conductive contacts. The ones of the conductive contacts each extend to a different one of the conductive structures of the second group of the tiers than each other of the ones of the conductive contacts.

With reference toFIG.10toFIG.25, illustrated are various stages of forming a microelectronic device, such as one including the microelectronic device structure100of any ofFIG.1andFIG.4toFIG.6, the microelectronic device structure700ofFIG.7, the microelectronic device structure800ofFIG.8, and the microelectronic device structure900ofFIG.9, wherein any staircase profile illustrated in a box140in any of the drawings may be substituted for any other staircase profile illustrated in a box140or a box804ofFIG.10toFIG.25, and wherein any staircase profile illustrated in a box146in any of the drawings may be substituted for any other staircase profile illustrated in a box146ofFIG.10toFIG.25.

A stack1002(otherwise referred to herein as a “stack structure” or “tiered stack”) is formed on the base structure110, including in areas (e.g., a first stadium area1004, a second stadium area1006, a third stadium area1008, a fourth stadium area1010) in which the series of stadiums122(FIG.1) will be formed. In some embodiments, the stack1002is formed to include a vertically alternating sequence of the insulative structures104and sacrificial structures1012arranged in tiers1014. The sacrificial structures1012may be formed at elevations of the stack1002that will eventually be replaced with, or otherwise converted into, the conductive structures106(e.g.,FIG.1). In other embodiments, the stack1002may be formed to include the conductive structures106instead of the sacrificial structures1012, even without replacement or conversion, such that the stack1002may have substantially the materials of the stack102ofFIG.1. Accordingly, the stack1002is formed to include the insulative structures104and “other structures,” which other structures may be either the sacrificial structures1012or the conductive structures106.

To form the stack1002, formation (e.g., deposition) of the insulative structures104may be alternated with formation (e.g., deposition) of the other structures (e.g., the sacrificial structures1012). In some embodiments, the stack1002is formed, at this stage, to include as many tiers1014with the sacrificial structures1012as there will be tiers108(FIG.1) with conductive structures106(FIG.1) in the final structure (e.g., the microelectronic device structure100of any ofFIG.1andFIG.4throughFIG.6, the microelectronic device structure700ofFIG.7, the microelectronic device structure800ofFIG.8, the microelectronic device structure900ofFIG.9).

One or more hardmasks1016may also be included on (e.g., above) the stack1002and utilized in subsequent material-removal (e.g., etching, patterning) processes.

With reference toFIG.11, the stack1002(and the hardmask1016) is patterned to define initial stadium openings1102in the footprint (e.g., horizontal) area (e.g., the first stadium area1004, the second stadium area1006, the third stadium area1008, the fourth stadium area1010) for the stadiums122(FIG.1) to be formed. Areas of the stack1002for the crests132(FIG.1) and the bridges134(FIG.1) may not be etched so that they retain the full height of the stack1002.

As used herein, the term “stadium opening” (e.g., as in the initial stadium opening1102) means and includes an opening that includes, along the width of its base, the at least one staircase profile, such that the base of the stadium opening defines exposed surfaces1104of the sacrificial structures1012at different tier1014elevations.

Forming the initial stadium openings1102defines a staircase profile with one or more staircases (e.g., the ascending staircase120, the descending staircase118). The particular staircase profile formed in each initial stadium opening1102may be tailored according to the staircase profile of the final stadium122(FIG.1,FIG.7,FIG.8,FIG.9) to be formed. In the stadium areas where the final stadiums122do not include a vertical offset—such as with the staircase profiles of box140ofFIG.1,FIG.2A,FIG.2B,FIG.2C,FIG.2D, andFIG.9and with the staircase profiles of box146ofFIG.3DandFIG.3E—the staircase profile of the initial stadium openings1102may be substantially the staircase profile of the final stadium122(FIG.1,FIG.7,FIG.8,FIG.9) to be formed. In the stadium areas where the final stadiums122are to include the vertical offset148(FIG.1)—such as the staircase profiles of box146ofFIG.1,FIG.3A,FIG.3B,FIG.3C,FIG.7, andFIG.8and of box804ofFIG.8—the staircase profile partially defined by the initial stadium opening1102may correspond to a staircase profile of the final stadium122but without the offset148at this stage.

Each of the initial stadium openings1102may be formed, in each stadium area (e.g., the first stadium area1004, the second stadium area1006, the third stadium area1008, the fourth stadium area1010) in substantially the same uppermost tier1014elevations of the stack1002.

Forming each of the initial stadium openings1102may include a sequence of material-removal (e.g., etching) acts by which the hardmask1016is patterned to define an opening of a first width, which first-width opening is then etched to a first depth, such as a depth of the quantity (“q”) (e.g., five) of the tiers1014that are to be included in the staircase profile. Then, the hardmask1016may be trimmed to expand the opening to a second width, which second-width opening is then patterned a depth of q−1 (e.g., four) of the tiers1014. Then, the hardmask1016may be trimmed to expand the opening to a third width, which third-width opening is then patterned a depth of q−2 (e.g., three) of the tiers1014. This may be repeated until completing the profile of the ascending staircase120and the descending staircase118that are opposing and mirrored.

In embodiments in which the initial stadium opening1102is formed to define the staircase profile of box140ofFIG.1, an initial hardmask1016patterning and etching act may be at a width substantially equal to that of the staircase landing142(FIG.1), and this width may be etched to a depth extending through the sacrificial structure1012that initially defines the lowest exposed surface1104(for steps114(FIG.1)) of the staircases (e.g., the ascending staircase120and the descending staircase118). For example, the initial width may be etched to a depth of q+½ of the tiers1014that are to be included in the staircase profile.

The initial stadium openings1102may be formed substantially simultaneously for each of the stadium areas (e.g., the first stadium area1004, the second stadium area1006, the third stadium area1008, the fourth stadium area1010). In other embodiments, any of the initial stadium openings1102may be formed sequentially in whole or in part.

In the stadium areas (e.g., first stadium area1004, second stadium area1006) that are to include vertical offsets148(FIG.1) (e.g., such as for the single-step-per-tier stadiums144with the staircase profiles of box146according to any ofFIG.1,FIG.3A,FIG.3B,FIG.3C,FIG.7, andFIG.8; the duplicate stadiums702with the staircase profiles of box146ofFIG.7; and the multi-step-contacts-per-tier stadium802with the staircase profile of box804ofFIG.8), half of each stadium width may be etched to lower the staircase profile the offset148distance for that half of the stadium. For example, with regard toFIG.12, the right-half of the first stadium area1004(FIG.11) and the second stadium area1006is etched to lower the ascending staircases120the vertical offset148distance into the stack1002. This half-stadium vertical offset defines offset stadium openings1202in the first stadium area1004(FIG.11) and the second stadium area1006.

In embodiments in which others of the stadiums122to be formed have staircase profiles that do not include the vertical offset148, the staircase profiles formed in the corresponding stadium areas (e.g., the third stadium area1008, the fourth stadium area1010) may not be altered during the offsetting (e.g., in the first stadium area1004(FIG.11) and the second stadium area1006).

In embodiments in which the staircase profile of the shallowest stadium122of the block112(FIG.1) includes the offset148, forming the offset stadium openings1202completes the formation of the first stadium124as the single-step-per-tier stadium144.

For the stadium areas where the initial stadium openings1102and the offset stadium openings1202do not yet extend to their final tier1014elevations (e.g., depths) in the stack1002, these openings may be extended in a series of material-removal (e.g., etching) acts.

For example, the offset stadium opening1202in the second stadium area1006may be extended deeper into the stack1002while the initial stadium openings1102in the third stadium area1008and in the fourth stadium area1010are extended also deeper into the stack1002. As illustrated inFIG.13, this extension may complete the fabrication of the stadium122in the second stadium area1006(FIG.12) (e.g., forming the second stadium126) and form extended partial stadium openings1302in each of the third stadium area1008and the fourth stadium area1010. The extension may substantially maintain the staircase profile(s) already defined in earlier stages, though the staircase profile(s) are extended to lower elevations.

While extending at least some of the stadium openings (e.g., to form the second stadium126and the extended partial stadium openings1302of the third stadium area1008and the fourth stadium area1010), the already-completed stadium122of the first stadium124may not be altered.

The stadium opening extensions are continued deeper and deeper into the stack1002for each of the stadium areas where the staircase profiles are not yet at their final tier1014elevations (e.g., depths) in the stack1002. Therefore, with reference toFIG.14, the extensions may continue until the third stadium128is at its final depth, at which stage the fourth stadium area1010includes a further extended partial stadium opening1402. Then, the further extended partial stadium opening1402in the fourth stadium area1010is extended to complete the fourth stadium130, as illustrated inFIG.15.

After the extensions, the stadiums122define substantially their final staircase profiles with stepped tiers1502having exposed surfaces1104of the sacrificial structures1012where the stadiums122will eventually have steps114(FIG.1) defined, in part, by the conductive structures106(FIG.1) of the tiers108(FIG.1).

With reference toFIG.16, the dielectric material(s)502is(are) formed (e.g., deposited) to substantially fill each stadium opening (e.g., stadium trench) above the completed stadiums122. The hardmask1016may be re-formed above the stack1002and the dielectric material(s)502.

In embodiments in which the stack1002was formed to include sacrificial structures1012(rather than the conductive structures106), the sacrificial structures1012may be substantially removed (e.g., exhumed) and replaced with the conductive material(s) of the conductive structures106—or may be otherwise converted to the conductive material(s)—to form, as illustrated inFIG.17, the stack102with the tiers108of the conductive structures106and the insulative structures104. By this replacement process, the stadiums122then include the steps114at the conductive structures106of the stepped tiers138.

With reference toFIG.18, the hardmask1016is patterned to define openings1802in the areas where the step contacts116(FIG.1) are to be formed. In some embodiments, the openings1802defined for the step contacts116(FIG.1) to the relatively-deeper stadiums (e.g., the third stadium128and the fourth stadium130) may be formed relatively wider than the openings1802defined for the step contacts116(FIG.1) to the relatively-shallower stadiums122(e.g., the first stadium124and the second stadium126) so that, once the openings1802are extended downward through the dielectric material(s)502to their respective steps114, the bottom dimension of the openings1802will be sufficient to fabricate the step contacts116in physical contact with their respective steps114despite, e.g., tapering through the stack102.

In some embodiments, the openings1802formed in the hardmask1016are extended (e.g., etched) downward into the dielectric material(s)502in a series of etching acts across the series of stadium areas (e.g., horizontal area of the stadiums122) until the steps114are reached. For example, the dielectric material(s)502may be etched via the openings1802to form, as illustrated inFIG.19, complete contact openings1902to the steps114of the first stadium124, while forming initial partial openings1904that terminate in the dielectric material(s)502, not yet reaching their respective steps114of the deeper stadiums122(e.g., the second stadium126, the third stadium128, the fourth stadium130). The complete contact openings1902expose a portion of the steps114to which step contacts116(FIG.1) are to be formed. The initial partial openings1904do not yet expose any portion of the steps114.

With reference toFIG.20, a sacrificial material2002is formed in the complete contact openings1902(FIG.19) to form base-plugged contact openings2004. The sacrificial material2002may be formed of and include, for example, one or more polymer material(s), which may be by-product(s) of etchant(s) used to form the contact openings (e.g., the complete contact openings1902(FIG.19) and the initial partial openings1904). For example, etchant(s) may be introduced (e.g., in gaseous form) to the areas across the whole structure that are exposed through the hardmask1016. By tailoring the composition of the etchant chemistry (e.g., the relative amounts of chemical species in the etchant chemistry), the sacrificial material2002(e.g., the polymer material(s)) may exhibit a lower etch rate compared to the etch rate of the dielectric material(s)502, and the sacrificial material2002may accumulate in the complete contact openings1902(FIG.19), to form the base-plugged contact openings2004, while not substantially accumulating in (and not substantially inhibiting continued etching of the dielectric material(s)502in) not-yet completed contact openings (e.g., in the initial partial openings1904). For example, an etchant composition may comprise oxygen (O2) and carbon fluoride(s) (e.g., CxFy), and a relatively greater oxygen (O2) concentration may yield relatively less formation of the sacrificial material2002(e.g., polymer material(s)), a relatively higher carbon (C) concentration may yield relatively greater formation of the sacrificial material2002, and a relatively higher fluorine (F) concentration may yield relatively less formation of the sacrificial material2002. Therefore, the flow of the O2and the ratio of the carbon (C) and fluorine (F) (e.g., the “x” and the “y,” respectively, in CxFy) may be adjusted and/or otherwise tailored to control the relative accumulation of the sacrificial material2002in the base-plugged contact openings2004without significantly inhibiting etching of the dielectric material(s)502in the not-yet-complete contact openings (e.g., the initial partial openings1904). Accordingly, the sacrificial material2002may substantially accumulate only in the base of the complete contact openings1902(FIG.19)—where the steps114are partially exposed—and not in the initial partial openings1904—that are defined substantially only in the dielectric material(s)502. The presence of the sacrificial material2002in the base-plugged contact openings2004may inhibit etching of the conductive structures106during subsequent material-removal acts.

The initial partial openings1904are then extended downward for each of the stadiums122where the openings have not yet reached their respective steps114. The initial partial openings1904may be extended to form complete contact openings1902(FIG.19) to the second stadium126and to form extended partial openings2102toward other stadiums122(e.g., in the third stadium128and the fourth stadium130), as illustrated inFIG.21. The sacrificial material2002may, again, accumulate to form the base-plugged contact openings2004for the second stadium126, substantially without the sacrificial material2002accumulating in the extended partial openings2102, which are defined substantially wholly in the dielectric material(s)502. These extensions and sacrificial material2002formation stages are repeated for the deeper and deeper stadiums122.

Though the sacrificial material2002may be formulated and intended to form (e.g., accumulate) substantially only directly on the conductive structures106of exposed portions of the steps114in complete contact openings1902(FIG.19), in some implementations of these fabrication stages, some sacrificial material2002may inadvertently accumulate within partially-formed openings, such as in a further extended partial opening2202(FIG.22) in the not-yet completed openings toward the relatively-deeper stadiums122(e.g., the third stadium128, the fourth stadium130). This may result in a fabrication error (e.g., so-called “under etching”) that could result in formation of the under-formed step contact604illustrated inFIG.6. This fabrication error may be more likely in the deepest stadiums122(e.g., the third stadium128, the fourth stadium130) given the greater number of times these partial contact openings, of these deeper stadiums122, are exposed to the sacrificial material2002before completion of these contact openings. However, by forming multiple step contacts116(FIG.1) per stepped tier138of one or more of the stadiums122(e.g., the deepest stadiums122) most prone to these fabrication errors, the likelihood of at least one of the multiple step contacts116(FIG.1) being accurately fabricated so as to provide electrical communication to the stepped tier138is significantly increased.

Absent fabrication errors, and at least in the further extended partial openings2202not inadvertently plugged with the sacrificial material2002, further extensions of the openings forms complete contact openings1902to the remaining stadiums122, as illustrated inFIG.23.

The sacrificial material2002may be removed (e.g., etched) from the base-plugged contact openings2004to complete the formation of the complete contact openings1902for the step contacts116(FIG.1) to each of the stadiums122, as illustrated inFIG.24, with a portion of each step114exposed in the complete contact openings1902.

In some embodiments, the hardmask1016may be removed (e.g., etched, planarized) at this or later stages.

In the complete contact openings1902, the material(s) of the step contacts116are formed (e.g., deposited) to complete the formation of the step contacts116, as illustrated inFIG.25.

The through-stack contacts404(FIG.4) may be formed, such as in the crests132of the stack102, and may be formed to couple to conductive features under the stack102(e.g., CuA circuitry, string driver circuitry). The routing lines402(FIG.4) are formed to complete the electrical connections between the step contacts116and their respective through-stack contacts404to form the microelectronic device structure (e.g., the microelectronic device structure100ofFIG.1, the microelectronic device structure700ofFIG.7, the microelectronic device structure800ofFIG.8, the microelectronic device structure900ofFIG.9).

Accordingly, disclosed is a method of forming a microelectronic device. The method comprises forming a tiered stack on a base structure. The tiered stack comprises a vertically alternating sequence of insulative structures and other structures. Stadiums are formed in the tiered stack. Each of the stadiums includes one or more staircases at least partially defined by horizontal ends of some of the other structures. At least one dielectric material is formed within trenches vertically overlying the stadiums. Contact openings are formed through the at least one dielectric material. At least one pair of the contact openings vertically extends to a common one of the other structures. A conductive contact structure is formed in each of the contact openings.

FIG.26shows a block diagram of a system2600, according to embodiments of the disclosure, which system2600includes memory2602including arrays of vertical strings of memory cells adjacent microelectronic device structure(s) (e.g., microelectronic device structure100ofFIG.1andFIG.4,FIG.5, and/orFIG.6; microelectronic device structure700ofFIG.7; microelectronic device structure800ofFIG.8; microelectronic device structure900ofFIG.9). Therefore, the architecture and structure of the memory2602may include one or more device structures according to embodiments of the disclosure and may be fabricated according to one or more of the methods described above (e.g., with reference toFIG.10throughFIG.25).

The system2600may include a controller2604operatively coupled to the memory2602. The system2600may also include another electronic apparatus2606and one or more peripheral device(s)2608. The other electronic apparatus2606may, in some embodiments, include one or more of microelectronic device structures (e.g., microelectronic device structure100ofFIG.1andFIG.4,FIG.5, and/orFIG.6; microelectronic device structure700ofFIG.7; microelectronic device structure800ofFIG.8; microelectronic device structure900ofFIG.9), according to embodiments of the disclosure and fabricated according to one or more of the methods described above. One or more of the controller2604, the memory2602, the other electronic apparatus2606, and the peripheral device(s)2608may be in the form of one or more integrated circuits (ICs).

A bus2610provides electrical conductivity and operable communication between and/or among various components of the system2600. The bus2610may include an address bus, a data bus, and a control bus, each independently configured. Alternatively, the bus2610may use conductive lines for providing one or more of address, data, or control, the use of which may be regulated by the controller2604. The controller2604may be in the form of one or more processors.

The other electronic apparatus2606may include additional memory (e.g., with one or more microelectronic device structures (e.g., microelectronic device structure100ofFIG.1andFIG.4,FIG.5, and/orFIG.6; microelectronic device structure700ofFIG.7; microelectronic device structure800ofFIG.8; microelectronic device structure900ofFIG.9), according to embodiments of the disclosure and fabricated according to one or more of the methods described above). Other memory structures of the memory2602and/or the other electronic apparatus2606may be configured in an architecture other than 3D NAND, such as dynamic random access memory (DRAM), static random access memory (SRAM), synchronous dynamic random access memory (SDRAM), synchronous graphics random access memory (SGRAM), double data rate dynamic ram (DDR), double data rate SDRAM, and/or magnetic-based memory (e.g., spin-transfer torque magnetic RAM (STT-MRAM)).

The peripheral device(s)2608may include displays, imaging devices, printing devices, wireless devices, additional storage memory, and/or control devices that may operate in conjunction with the controller2604.

The system2600may include, for example, fiber optics systems or devices, electro-optic systems or devices, optical systems or devices, imaging systems or devices, and information handling systems or devices (e.g., wireless systems or devices, telecommunication systems or devices, and computers).

Accordingly, disclosed is an electronic system comprising a three-dimensional memory device, at least one processor, and at least one peripheral device. The three-dimensional memory device comprises a stack structure comprising conductive structures vertically alternating with insulative structures and arranged in tiers. A series of staircased stadiums is defined in a block of the stack structure. Pairs of step contacts extend, through dielectric material overlying at least one of the stadiums, to mutual ones of the conductive structures defining at least one step of the at least one stadium. The at least one processor is in operable communication with the three-dimensional memory device. The at least one peripheral device is in operable communication with the at least one processor.

While the disclosed structures, apparatus (e.g., devices), systems, and methods are susceptible to various modifications and alternative forms in implementation thereof, specific embodiments have been shown by way of example in the drawings and have been described in detail herein. However, the disclosure is not intended to be limited to the particular forms disclosed. Rather, the disclosure encompasses all modifications, combinations, equivalents, variations, and alternatives falling within the scope of the disclosure as defined by the following appended claims and their legal equivalents.