OPTICAL DEVICE TESTING SYSTEM

A characterization circuit for an optical device includes: an optical device, a switch, a switch driver, one or more resistors, and one or more capacitors. The switch driver is configured to receive a trigger pulse from an external pulse generator and to provide the trigger pulse to the switch, which causes the switch to be in an on state. The one or more capacitors are configured to, when the switch is in an off state, receive a charge current (e.g., with a greater than 50 nanoseconds rise time) from an external driver voltage source via the one or more resistors; and, when the switch is in the on state, discharge a current pulse (e.g., with a less than 10 nanosecond pulse width) to the optical device. The optical device is configured to receive the current pulse and to emit, based on the current pulse, an optical output pulse.

TECHNICAL FIELD

The present disclosure relates generally to an optical device testing system and to facilitate testing of an optical device using high-current pulses in a nanosecond range.

BACKGROUND

An optical device may include an array of emitters. In some applications, such as in automotive and/or light detection and ranging (LIDAR) applications, the optical device may need to produce optical output pulses with a high peak optical power.

SUMMARY

In some implementations, a characterization circuit for an optical device includes the optical device; a switch; a switch driver; one or more resistors; and one or more capacitors, wherein: the switch driver is configured to receive, via a first card edge connector trace, a trigger pulse from an external pulse generator and to provide the trigger pulse to the switch, wherein a pulse width of the trigger pulse is greater than or equal to a first threshold; the switch is configured to receive the trigger pulse from the external pulse generator and to be in an on state when receiving the trigger pulse; the switch is configured to be in an off state when not receiving the trigger pulse; the one or more capacitors are configured to, when the switch is in the off state, receive, via a second card edge connector trace, a charge current from an external driver voltage source via the one or more resistors wherein a rise time of the charge current is greater than a second threshold; the one or more capacitors are configured to, when the switch is in the on state, discharge a current pulse to the optical device, wherein a pulse width of the current pulse is less than a third threshold, wherein an average current associated with a flow of the charge current through the one or more resistors from the external driver voltage source to the one or more capacitors matches an average current associated with the flow of the current pulse through the optical device; and the optical device is configured to receive the current pulse from the one or more capacitors and to emit, based on a flow of the current pulse through the optical device, an optical output pulse.

In some implementations, an optical device testing system includes a printed circuit board (PCB) that comprises an electrical driver circuit that includes an optical device; a card edge connector; a direct current (DC) power supply; a driver voltage source; a pulse generator; and one or more testing components, wherein: the card edge connector is electrically connected to the PCB via one or more card edge connector traces of the PCB; the DC power supply is configured to provide power to the electrical driver circuit of the PCB; the driver voltage source is configured to provide a charge current to one or more capacitors of the electrical driver circuit; the pulse generator is configured to provide a trigger pulse to a field-effect transistor (FET) switch of the electrical driver circuit, wherein a pulse width of the trigger pulse is greater than or equal to 10 nanoseconds, wherein providing the trigger pulse to the FET switch causes the one or more capacitors of the electrical driver circuit to discharge a current pulse to the optical device, which causes the optical device to emit an optical output pulse, and wherein a pulse width of the current pulse is less than 10 nanoseconds; and the optical device testing system is configured to perform characterization testing of the optical device.

In some implementations, an optical device testing system includes an optical pulse generator that comprises an electrical driver circuit that includes an optical device; a direct current (DC) power supply; a driver voltage source; a pulse generator; a card edge connector; a motherboard; and an environmental chamber, wherein: the card edge connector is electrically connected to the optical pulse generator via one or more card edge connector traces of the optical pulse generator, the card edge connector is electrically connected to the motherboard, the DC power supply is electrically connected to the motherboard and is configured to provide power to the electrical driver circuit of the optical pulse generator via the motherboard, the card edge connector, and a first card edge connector trace of the one or more card edge connector traces, the driver voltage source is electrically connected to the motherboard and is configured to provide a charge current to one or more capacitors of the electrical driver circuit via the motherboard, the card edge connector, and a second card edge connector trace of the one or more card edge connector traces, wherein a rise time of the charge current is greater than 50 nanoseconds, the pulse generator is electrically connected to the motherboard and is configured to provide a trigger pulse to a switch of the electrical driver circuit via the motherboard, the card edge connector, and a third card edge connector trace of the one or more card edge connector traces, wherein a pulse width of the trigger pulse is greater than or equal to 10 nanoseconds, wherein providing the trigger pulse to the switch causes the one or more capacitors of the electrical driver circuit to discharge a current pulse to the optical device, which causes the optical device to emit an optical output pulse, and wherein a pulse width of the current pulse is less than 10 nanoseconds, the environmental chamber is configured to hold the motherboard, the card edge connector, and the optical pulse generator with the optical device within an internal portion of the environmental chamber, and the optical device testing system is configured to perform reliability stress testing of the optical device.

DETAILED DESCRIPTION

An optical device may include an array of emitters, such as a vertical cavity surface emitting laser (VCSEL) array. In some applications, such as in automotive and/or light detection and ranging (LIDAR) applications, the optical device may include hundreds of emitters that need to produce optical output pulses with a high peak optical power. Accordingly, to perform characterization and reliability testing of the optical device, electric pulses used to generate optical output pulses need to be generated at high speed (e.g., pulses with a short duration, such as less than 10 nanoseconds) and high current (e.g., pulses with a high peak current, such as greater than approximately 200 amps). This is a challenge for conventional platforms and/or methodologies that are used to test VCSEL arrays associated with data communication (datacom) applications or mobile device applications. For example, a VCSEL array associated with a datacom application typically includes a single emitter that requires an electric pulse with a current less than 10 milliamps to test the emitter. As another example, a VCSEL array associated with a mobile device application for three dimensional (3D) sensing typically includes tens to hundreds of emitters that require an electric pulse with a duration of a few milliseconds. Moreover, high speed and high current testing of an optical device for LIDAR applications is often limited by a parasitic inductance associated with a conventional testing platform (e.g., in a circuit associated with the testing platform that is configured to provide electric pulses to the optical device to test the optical device).

Further, some conventional high-speed and/or high-current systems use radio frequency (RF) techniques, such as subMiniature version A (SMA) connectors and coaxial cables for inputs and/or outputs, and/or transmission line probe principles that are built-in at test points on printed circuit boards (PCBs) for impedance matching and waveform fidelity. Typically, current sensing is done by measuring a voltage waveform of a shunt resistor. While these techniques can be used in PCBs for VCSEL array characterization, such techniques are impractical physically and cost-wise for reliability testing where a large quantity (e.g., hundreds) of samples need to be stress tested at the same time. While a goal is to test or evaluate VCSEL array chips' performance and reliability, the complexity of such conventional test platforms and/or systems poses its own reliability risks. Further, shunt resistors for current sensing are also undesirable because they add parasitic inductance to a resonance circuit. Additionally, shunt resistors may not provide accurate measurements of peak currents. A shunt resistance of 0.1 Ohm for high current is comparable to a series resistance of a high power VCSEL array, which affects driver performance.

Some implementations described herein provide a printed circuit board (PCB) that includes an electrical driver circuit. The electrical driver circuit may include an optical device, a field-effect transistor (FET) switch, a FET driver, one or more resistors, one or more inductors, and/or one or more capacitors. The FET driver may be configured to receive a trigger pulse from an external pulse generator and to provide the trigger pulse to the FET switch. The FET switch may be configured to receive the trigger pulse from the external pulse generator and to be in an on state when receiving the trigger pulse. Accordingly, the FET switch may be configured to be in an off state when not receiving the trigger pulse. The one or more capacitors may be configured to, when the FET switch is in the off state, receive a charge current from an external driver voltage source via the one or more resistors, and, when the FET switch is in the on state, discharge a current pulse to the optical device. The pulse width of the current pulse may be less than 10 nanoseconds and/or a peak current of the current pulse may be greater than or equal to 200 amps. The optical device may be configured to receive the current pulse from the one or more capacitors and to emit, based on a flow of the current pulse through the optical device, an optical output pulse. In this way, some implementations generate high speed and high current pulses that may be used to test the optical device.

Further, in some implementations, the PCB may be included in an optical device testing system. For example, the PCB may comprise one or more card edge connector traces that are configured to electrically connect the PCB with a card edge connector of the optical device testing system. In some implementations, the optical device testing system may include the driver voltage source and the pulse generator, which may respectively provide the charge current and the trigger pulse to the electrical driver circuit, as described above.

In some implementations, the optical device testing system may include one or more testing components to (e.g., a power meter, an oscilloscope, and/or a multi-meter, among other examples) and one or more processors to facilitate characterization testing of the optical device. Due to a configuration of the electrical driver circuit, the current pulse that flows through the optical device may have an average current that matches an average current of the charge current that flows through the one or more resistors and a normalized waveform (e.g., a normalized current waveform and/or a normalized voltage waveform) of the current pulse may be approximately the same as a normalized optical waveform of the optical output pulse. Accordingly, the one or more processors may obtain information from the one or more testing components related to the charge current and the optical output pulse to determine one or more electrical properties of the current pulse (e.g., a peak current of the current pulse and/or a peak voltage of the current pulse). In this way, some implementations allow characterization of a high speed, high current pulse of an optical device to be measured based on a low speed, low current charge current and/or optical properties of an optical output pulse of the optical device.

In some implementations, the optical device testing system may include a rack that holds multiple motherboards, where each motherboard may include multiple edge connectors, and where each card edge connecter may hold a PCB. In this way, multiple optical devices associated with the PCBs may be tested at the same time. Further, the optical device testing system may include an environmental chamber in which the rack may be placed to perform reliability stress testing of the multiple optical devices (e.g., in different environmental conditions).

Accordingly, by using card edge connectors and/or wires, instead of conventional SMA connectors and/or coaxial cables and transmission line probe circuits, some implementations described herein facilitate testing of high-speed operation and characterization of a VCSEL array on a PCB. This is because an inductance, a capacitance, and/or a resistance (e.g., that is parasitic or that is by design), outside a parallel LC circuit on the PCB, have a minimal impact on a resonance of the LC circuit on the PCB.

Moreover, some implementations described herein provide a method for peak current determination of the current pulse. The method may convert a measurement of average current of a low-bandwidth and/or low-peak charge current at a power supply associated with the PCB into determination of the peak parameters (i.e. current and/or waveform) of a high-speed and/or a high-current current pulse. This enables use of a card edge connector (e.g., that is usually used for DC or low-bandwidth signals). In some implementations, peak power, peak current and peak voltage (across a VCSEL diode) can be determined from a measured average power, average current, and/or voltage and optical waveforms.

In RF measurements, peak values (e.g., power, current, or voltage) of high-speed signals with square waveforms are often determined by a measured average value divided by a duty cycle. In contrast, waveforms from an ideal discharge driver have a sine waveform. Moreover, actual waveforms may deviate from a sine waveform due to a damping factor (e.g., that depends on series resistance in a resonance circuit). Peak values can be determined based on measured average values with arbitrary waveforms using processes described below.

FIGS. 1A-1Bare diagrams of an example implementation100associated with an optical device testing system described herein (e.g., the optical device testing system200described herein in relation toFIG. 2and/or the optical device testing system300described herein in relation toFIG. 3). As shown inFIGS. 1A-1B, a printed circuit board (PCB)102may include an electrical driver circuit104(e.g., that includes an optical device106to be tested), and/or one or more traces108(e.g., shown as traces108-1through108-7inFIG. 1A). The optical device106may include an array of emitters. For example, the optical device106may include a light emitting diode (LED) array, a vertical cavity surface emitting laser (VCSEL) array, and/or an edge emitting laser (EEL) array. The array of emitters may include multiple emitters, such as up to hundreds of emitters. In some implementations, the optical device106may have a series resistance when included in a circuit, such as the electrical driver circuit104.

The electrical driver circuit104may comprise a resonant capacitor discharge driver circuit and may include, for example, the optical device106, a switch110(e.g., a field-effect transistor (FET) switch), a switch driver112(e.g., a FET driver), one or more resistors114, one or more capacitors116(shown as capacitors116-1and116-2inFIG. 1A), and/or one or more inductors118. The switch110may comprise, for example, an enhanced gallium nitride FET (eGaN FET) switch or a metal-oxide-semiconductor FET (MOSFET) switch. The switch driver112may comprise, for example, an eGaN FET driver or a MOSFET driver. In some implementations, the electrical driver circuit104may comprise a plurality of resistors114(e.g., arranged in parallel), as opposed to just one resistor114, to minimize an amount of inductance associated with the one or more resistors114. Additionally, or alternatively, the electrical driver circuit104may comprise a plurality of capacitors116(e.g., arranged in parallel), as opposed to just one capacitor116, to minimize an amount of inductance associated with the one or more capacitors116. In some implementations, the inductor118may be a physical component of the electrical driver circuit104or may be a parasitic inductance of the electrical driver circuit104. As shown inFIG. 1B, the optical device106(e.g., that has a series resistance), the inductor118, and the one or more capacitors116may form a resistor-inductor-capacitor (RLC) resonance circuit.

As further shown inFIG. 1B, a direct current (DC) power supply120, such as a 5 volt (V) power supply, may be electrically connected to the electrical driver circuit104. The DC power supply120may be an external power supply (e.g., the DC power supply120may not be included in or on the PCB102) and may be electrically connected to the electrical driver circuit104via the one or more traces108(e.g., via the trace108-1as described herein). The DC power supply120may be configured to provide power (e.g., a DC power supply) to the electrical driver circuit104(e.g., to allow the electrical driver circuit104to charge the one or more capacitors116and/or to test the optical device106, as described herein).

A driver voltage source122may be electrically connected to the electrical driver circuit104. The driver voltage source122may be an external voltage source (e.g., the driver voltage source122may not be included in or on the PCB102) and may be electrically connected to the electrical driver circuit104via the one or more traces108(e.g., via the trace108-2as described herein). As shown inFIG. 1B, the driver voltage source122may be electrically connected to the one or more resistors114and the one or more capacitors116, and the driver voltage source122(e.g., when the driver voltage source122is in an on state) may be configured to provide a charge current to the one or more capacitors116(e.g., via the one or more resistors114) to charge the one or more capacitors116(e.g., when the switch110is off, as described herein). The charge current may have a peak current that is less than or equal to 1 amp (A). The charge current may have a rise time that is greater than 50 ns. The driver voltage source122may provide the charge current to the one or more capacitors116for a charge time (e.g., that is within a period of a trigger pulse, described herein). The charge time may be an amount of time needed to fully charge the one or more capacitors116.

A pulse generator124may be electrically connected to the electrical driver circuit104. The pulse generator124may be an external pulse generator (e.g., the pulse generator124may not be included in or on the PCB102) and may be electrically connected to the electrical driver circuit104via the one or more traces108(e.g., via the trace108-3as described herein). As shown inFIG. 1B, the pulse generator124may be electrically connected to the switch driver112and may be configured to provide a trigger pulse to the switch110via the switch driver112(e.g., to control whether the switch110is in an on state or an off state). A pulse width of the trigger pulse may be greater than or equal to 10 ns.

For example, when the pulse generator124is in an off state, the pulse generator may refrain from providing a trigger pulse to the switch110. Accordingly, this may cause the switch110to be in an off state and may cause the driver voltage source122to provide the charge current to the one or more capacitors116(e.g., as described above). As another example, when the pulse generator124is in an on state, the pulse generator may generate and provide, via the switch driver112, a trigger pulse to the switch110. Accordingly, this may cause the switch110to be in an on state and may cause the one or more capacitors116to discharge a current pulse to the optical device106via the inductor118(e.g., cause the RLC resonance circuit to generate and provide the current pulse to the optical device106). A pulse width of the current pulse may be less than 10 ns. In this way, a high-speed current pulse (e.g., with a pulse width less than 10 ns) may be generated using a low-speed trigger pulse (e.g., with a pulse width greater than 10 ns) to test the optical device106(e.g., to cause the optical device to emit an optical output pulse, as further described herein in relation toFIG. 2).

In some implementations, a current waveform of the current pulse may be non-square (e.g., due to a small pulse width of the current pulse). For example, the current waveform may be sinusoidal (e.g., as determined by a resonance of the RLC circuit).

In some implementations, the current pulse may have a peak current that is greater than the peak current of the charge current (e.g., the peak current of the current pulse may be greater than 1 A). In some implementations, the peak current of the current pulse may be over 100 times greater than the peak current of the charge current. For example, the peak current of the current pulse may be greater than or equal to 200 A when the peak current of the charge current is less than 1 A. Additionally, or alternatively, an average current of the charge current (e.g., when the charge current flows through the one or more resistors114from the driver voltage source122to the one or more capacitors116, such as when the switch110is in an off state), may match (e.g., may be equal to, or approximately equal to) an average current of the current pulse (e.g., when the current pulse flows through the optical device106, such as when the switch110is in an on state).

As further shown inFIG. 1A, the PCB102may include a thermistor126. The thermistor126may be electrically connected to a multi-meter (e.g., multi-meter204described herein in relation toFIG. 2), or another device, via the one or more traces108(e.g., via the trace108-4as described herein). The thermistor126may be configured to monitor a temperature of the PCB102(e.g., during testing of the optical device106). For example, the thermistor126of the electrical driver circuit104may provide, via the trace108-4, an electrical signal associated with the PCB102(e.g., where a resistance of the electrical signal indicates a temperature of the PCB102). Alternatively, a thermocouple or other device may be used to monitor the temperature.

In some implementations, the one or more traces108may be configured to allow the PCB102to electrically connect with one or more devices. For example, as shown inFIG. 1A, the trace108-1may electrically connect the electrical driver circuit104to the DC power supply120(e.g., as described above), the trace108-2may electrically connect the electrical driver circuit104to the driver voltage source122(e.g., as described above), and/or the trace108-3may electrically connect the electrical driver circuit104to the pulse generator124(e.g., as described above). As another example, the trace108-4may electrically connect the thermistor126to the multi-meter (e.g., as described above). In an additional example, the trace108-5may electrically connect an anode of the optical device106to an oscilloscope and/or the trace108-6may electrically connect a cathode of the optical device106to oscilloscope to allow the oscilloscope to monitor the anode and the cathode associated with the optical device106. In another example, the trace108-7may connect the electrical driver circuit104to a ground (e.g., ground206described herein in relation toFIG. 2).

In some implementations, the one or more traces108may be edge connector traces and may be configured to electrically connect with a card edge connector (e.g., card edge connector202described herein in relation toFIGS. 2-3) of an optical device testing system (e.g., optical device testing system200described herein in relation toFIG. 2or optical device testing system300described herein in relation toFIG. 3). Accordingly, in some implementations, the card edge connector may electrically connect the one or more traces108to the one or more devices (e.g., the DC power supply120, the driver voltage source122, the pulse generator124, the multi-meter, and/or the ground among other examples).

As indicated above,FIGS. 1A-1Bare provided as an example. Other examples may differ from what is described with regard toFIGS. 1A-1B.

FIG. 2is a diagram of an example optical device testing system200described herein. As shown inFIG. 2, the optical device testing system200may include the PCB102, a card edge connector202, the DC power supply120, the driver voltage source122, and the pulse generator124. Additionally, or alternatively, the optical device testing system200may include a multi-meter204, a ground206, an integrating sphere208, a power meter210, a spectrometer212, one or more oscilloscopes214(shown as first oscilloscope214-1and second oscilloscope214-2), a near field camera216(e.g., that is associated with a lens218), a far field camera220, and/or one or more processors222, among other examples. In some implementations, the optical device testing system200may be an optical device performance characterization system (e.g., the optical device testing system200may be configured to perform characterization testing of the of the optical device106included on the PCB102, as described herein).

The card edge connector202may be configured to physically hold the PCB102(e.g., to allow the optical device106, that is included on the PCB102, to be tested by the optical device testing system200). For example, the card edge connector202may include a recess (or other physical structure) in which the PCB102may be inserted and held by the card edge connector202. Additionally, or alternatively, the card edge connector202may be configured to electrically connect to the PCB102. For example, the card edge connector202may include one or more traces (not shown inFIG. 2) that electrically connect to the one or more traces108of the PCB102(e.g., when the PCB102is inserted in the recess of the card edge connector202). In some implementations, the card edge connector202may include a heatsink and/or a thermoelectric cooler (TEC) to transfer heat from the PCB102(e.g., when the optical device106is tested by the optical device testing system200). While the card edge connector202is described in some implementations as a card edge connector, one or more other electrical connectors (e.g., low-speed electrical connectors) may be used, such as one or more pogo-pin connectors.

As further shown inFIG. 2, the DC power supply120may be electrically connected to the card edge connector202(e.g., via an electrical contact224-1). In some implementations, the DC power supply120may provide a DC power supply (e.g., a 5 V power supply) to the card edge connector202, which may provide the DC power supply to the electrical driver circuit104of the PCB102via the trace108-1(e.g., when the PCB102is inserted into the card edge connector202). The DC power supply120may be configured to provide the DC power supply to the electrical driver circuit104to allow the electrical driver circuit104to charge or discharge the one or more capacitors116and/or to test the optical device106(e.g., as described herein in relation toFIGS. 1A-1B).

As further shown inFIG. 2, the driver voltage source122may be electrically connected to the card edge connector202(e.g., via an electrical contact224-2). In some implementations, the driver voltage source122may provide a charge current to the card edge connector202, which may provide the charge current to the electrical driver circuit104of the PCB102via the trace108-2(e.g., when the PCB102is inserted into the card edge connector202). The driver voltage source122may be configured to provide the charge current to the one or more capacitors116of the electrical driver circuit104to charge the one or more capacitors116(e.g., as described herein in relation toFIGS. 1A-1B).

As further shown inFIG. 2, the pulse generator124may be electrically connected to the card edge connector202(e.g., via an electrical contact224-3). In some implementations, the pulse generator124may provide a trigger pulse to the card edge connector202, which may provide the trigger pulse to the electrical driver circuit104of the PCB102via the trace108-3(e.g., when the PCB102is inserted into the card edge connector202). The pulse generator124may be configured to provide a trigger pulse to the switch110via the switch driver112of the electrical driver circuit104(e.g., to control whether the switch110is in an on state or an off state). Accordingly, the pulse generator124may control when the driver voltage source122provides a charge current to the one or more capacitors116of the of the electrical driver circuit104and/or when the one or more capacitors116discharge a current pulse to the optical device106included in the electrical driver circuit104to test the optical device106(e.g., as described herein in relation toFIGS. 1A-1B).

As further shown inFIG. 2, the multi-meter204(e.g., a digital multi-meter) may be electrically connected to the card edge connector202(e.g., via an electrical contact224-4). In some implementations, the thermistor126of the electrical driver circuit104may provide, via the trace108-4, an electrical signal associated with the PCB102(e.g., where a resistance of the electrical signal indicates a temperature of the PCB102) to the card edge connector202(e.g., when the PCB102is inserted into the card edge connector202), which may provide the electrical signal to the multi-meter204. The multi-meter204may be configured to determine a resistance of the electrical signal to facilitate a determination of a temperature of the PCB102.

As further shown inFIG. 2, a first oscilloscope214-1may be electrically connected to the card edge connector202(e.g., via an electrical contact224-5and an electrical contact224-6). In some implementations, an anode of the optical device106may be electrically connected, via the trace108-5and the card edge connector202, to the first oscilloscope214-1and/or a cathode of the optical device106may be electrically connected, via the trace108-6and the card edge connector202, to the first oscilloscope214-1. Accordingly, based on these connections, the first oscilloscope214-1may be configured to determine one or more voltage properties of the current pulse (e.g., when the current pulse flows through the optical device106).

As further shown inFIG. 2, the ground206may be electrically connected to the card edge connector202(e.g., via an electrical contact224-7). The ground206may be configured to provide an electrical ground for the electrical driver circuit104. For example, the electrical driver circuit104may be electrically connected, via the trace108-7and the card edge connector202, to the ground206.

In some implementations, the power meter210may be configured to determine an optical power of an optical output pulse of the optical device106, and the spectrometer212may be configured to determine spectral data associated with the optical output of the optical device106. For example, as described above, the pulse generator124may provide a trigger pulse to cause the switch110be in an on state and thereby cause the one or more capacitors116to discharge a current pulse to the optical device106, which may cause the optical device106to emit an optical output pulse. The optical output pulse may transmit to the integrating sphere208, which may include one or more optical sensor elements (e.g., that are configured to determine optical power measurements) that are connected to the power meter210and/or connected to (e.g., via multi-mode optical fibers (MMFs)) the spectrometer212. The power meter210may be configured to determine (e.g., based on data provided by the one or more optical sensor elements) an average optical power associated with the optical output pulse of the optical device106. The spectrometer212may be configured to determine (e.g., based on data provided by the one or more optical sensor elements) one or more wavelength spectra associated with the optical output pulses of the optical device106.

In some implementations, a second oscilloscope214-2may be configured to determine an optical waveform associated with the optical output of the optical device106. For example, as described above, the pulse generator124may provide a trigger pulse to cause the switch110be in an on state and thereby cause the one or more capacitors116to discharge a current pulse to the optical device106, which may cause the optical device106to emit an optical output pulse. The optical output pulse may transmit to the second oscilloscope214-2(e.g., via an MMF and a high-speed receiver), which may measure the optical output pulse to determine the optical waveform. In some implementations, the optical waveform may be non-square (e.g., because a waveform of the current pulse is non-square). For example, the optical waveform may be sinusoidal.

In some implementations, the near field camera216and the far field camera220may be configured to determine spatial characteristics and/or propagation characteristics associated with the optical output pulse of the optical device106. For example, as described above, the pulse generator124may provide a trigger pulse to cause the switch110be in an on state and thereby cause the one or more capacitors116to discharge a current pulse to the optical device106, which may cause the optical device106to emit an optical output pulse. The optical output pulse may transmit to the near field camera216, via the lens218, which may measure the optical output pulse to determine spatial characteristics and/or propagation characteristics associated with the optical output pulse in a near field. The optical output pulse may transmit to the far field camera220, which may measure the optical output pulse to determine spatial characteristics and/or propagation characteristics associated with the optical output pulse in a far field.

As further shown inFIG. 2, the optical device testing system200may include a motorized stage. The PCB102(e.g., when the PCB102is inserted into the card edge connector202), the card edge connector202, the DC power supply120, the driver voltage source122, the pulse generator124, the multi-meter204, and/or the ground206may be disposed on the motorized stage, and the motorized stage may be configured to move (e.g., laterally) to different testing regions, where an individual testing region is associated with one or more of the integrating sphere208, the power meter210, the spectrometer212, the second oscilloscope214-2, the near field camera216, and/or the far field camera220. In this way, the motorized stage may facilitate testing (e.g., sequential testing) of the optical device106by at least one of the integrating sphere208, the power meter210, the spectrometer212, the second oscilloscope214-2, the near field camera216, and/or the far field camera220as described above.

A processor222, of the one or more processors222, includes a central processing unit, a graphics processing unit, a microprocessor, a controller, a microcontroller, a digital signal processor, a field-programmable gate array, an application-specific integrated circuit, and/or another type of processing component. The processor222is implemented in hardware, firmware, or a combination of hardware and software. The one or more processors222may be connected to one or more other components of the optical device testing system200via a bus (e.g., a component that enables wired and/or wireless communication among the components of the optical device testing system200).

In some implementations, the one or more processors222may be configured to control the optical device testing system200. In some implementations, the one or more processors222may be electrically connected to and may be configured to control the DC power supply120, the driver voltage source122, and/or the pulse generator124. For example, the one or more processors222may cause the DC power supply120to provide a DC power supply to the electrical driver circuit104to allow the electrical driver circuit104to charge or discharge the one or more capacitors116and/or to test the optical device106of the electrical driver circuit104(e.g., as described herein). As another example, the one or more processors222may cause the driver voltage source122to provide a charge current to the one or more capacitors116of the electrical driver circuit104to charge the one or more capacitors116(e.g., as described herein). In an additional example, the one or more processors222may cause the pulse generator124to provide a trigger pulse to the switch110of the electrical driver circuit104(e.g., to cause the switch110to be in an on state) and thereby cause the one or more capacitors116to discharge a current pulse to the optical device106included in the electrical driver circuit104, and thereby further causes the optical device106to emit an optical output pulse (e.g., as described herein).

In some implementations, the one or more processors222may be configured to obtain test information from the multi-meter204, the power meter210, the spectrometer212, the one or more oscilloscopes214, the near field camera216, and/or the far field camera220. The test information may include, for example, one or more one or more electrical properties (e.g., a current) of the charge current, one or more electrical properties of one or more optical properties (e.g., an optical power, spectral data, an optical waveform, spatial characteristics, and/or propagation characteristics, among other examples) of the optical output pulse.

In some implementations, the one or more processors222may process the test information to determine a peak optical power associated with the optical output pulse of the optical device106, to determine a peak current associated with a flow of the current pulse through the optical device106, and/or to determine a peak voltage associated with the flow of the current pulse through the optical device106.

For example, to determine the peak optical power associated with the optical output pulse of the optical device106, the one or more processors222may process (e.g., parse) the test information to identify an average optical power and an optical waveform (e.g., with a non-square waveform, such as a sinusoidal waveform) associated with the optical output pulse of the optical device106. The one or more processors222may process the optical waveform to determine a normalized optical waveform. For example, the one or more processors222may determine a maximum value associated with the optical waveform (e.g., a maximum optical power associated with the optical waveform) and may divide the optical waveform by the maximum value to determine the normalized optical waveform. Further, the one or more processors222may determine a period associated with the normalized optical waveform and may process, based on the period associated with the normalized optical waveform, the normalized optical waveform to determine an equivalent pulse width associated with the normalized optical waveform (e.g., a pulse width that is equivalent to a pulse width of a square waveform with the same average optical power). For example, the one or more processors222may process the normalized optical waveform according to the following formula to determine the equivalent pulse width: w=∫0Tpn(t)dt, where T is the period associated with the normalized optical waveform, pn(t) is the normalized optical waveform, and w is the equivalent pulse width. Accordingly, the one or more processors222may determine, based on the equivalent pulse width, the period associated with the normalized optical waveform, and the average optical power, the peak optical power associated with the optical output pulse of the optical device106. For example, the one or more processors222may determine the peak optical power according to the following formula:

where T is the period associated with the normalized optical waveform, w is the equivalent pulse width, Pavgis the average optical power, and Ppeakis the peak optical power.

As another example, to determine the peak current associated with the flow of the current pulse (e.g., that has a non-square current waveform) through the optical device106, the one or more processors222may process (e.g., parse) the test information to identify an average current associated with a flow of the charge current through the one or more resistors114of the electrical driver circuit104(e.g., which matches an average current associated with a flow of the current pulse through the optical device106, as described above). Further, the one or more processors222may identify the optical waveform (e.g., that has a non-square waveform) associated with the optical output pulse of the optical device106and may process the optical waveform to determine the normalized optical waveform (e.g., that is approximately equivalent to a normalized current waveform of the current pulse), as described above. The one or more processors222may determine the period associated with the normalized optical waveform and may process, based on the period of the normalized optical waveform, the normalized optical waveform to determine the equivalent pulse width associated with the normalized optical waveform (e.g., that is approximately equivalent to a pulse width of the normalized current waveform), as described above. Accordingly, the one or more processors222may determine, based on the equivalent pulse width associated with the normalized optical waveform, the period associated with the normalized optical waveform, and the average current of the charge current, the peak current associated with the flow of the current pulse through the optical device106. For example, the one or more processors222may determine the peak current according to the following formula:

where T is the period associated with the normalized optical waveform, w is the equivalent pulse width associated with the normalized optical waveform, Iavgis the average current of the charge current, and Ipeakis the peak current associated with the flow of the current pulse through the optical device106.

In an additional example, to determine the peak voltage associated with the flow of the current pulse (e.g., that has a non-square current waveform) through the optical device106, the one or more processors222may process (e.g., parse) the test information to identify a voltage waveform between the anode and the cathode of the optical device106associated with the flow of the current pulse through the optical device106. The one or more processors may process (e.g., using one or more digital signal processing (DSP) techniques), the voltage waveform to remove noise and/or artifacts (e.g., that are associated with parasitic capacitance of the electrical driver circuit104) from the voltage waveform. Accordingly, the one or more processors222may process the voltage waveform to determine an average voltage associated with the flow of the current pulse through the optical device106. The average voltage from parasitic inductance is

for periodic pulses, therefore averaging the voltage waveform further removes noise and/or artifacts (e.g., that are associated with parasitic inductance of the electrical driver circuit104). Further, the one or more processors222may identify the optical waveform (e.g., that has a non-square waveform) associated with the optical output pulse of the optical device106and may process the optical waveform to determine the normalized optical waveform (e.g., that is approximately the same as a normalized voltage waveform with noise and/or artifacts removed of the current pulse), as described above. The one or more processors222may determine the period associated with the normalized optical waveform and may process, based on the period of the normalized optical waveform, the normalized optical waveform to determine the equivalent pulse width associated with the normalized optical waveform (e.g., that is approximately the same as an equivalent pulse width of the normalized voltage waveform), as described above. Accordingly, the one or more processors222may determine, based on the equivalent pulse width associated with the normalized optical waveform, the period associated with the normalized optical waveform, and the average voltage of the current pulse, the peak voltage associated with the flow of the current pulse through the optical device106. For example, the one or more processors222may determine the peak voltage according to the following formula:

where T is the period associated with the normalized optical waveform, w is the equivalent pulse width associated with the normalized optical waveform, Vavgis the average voltage of the current pulse, and Vpeakis the peak voltage associated with the flow of the current pulse through the optical device106.

In this way, because the normalized optical waveform of the optical output pulse is approximately the same as the normalized current waveform of the current pulse and the average current associated with the charge current matches the average current of the discharge current pulse, the one or more processors222may determine the peak current of the current pulse based on the normalized optical waveform and the average current associated with the charge current. Further, because the normalized optical waveform of the optical output pulse is approximately the same as the normalized voltage waveform of the current pulse, the one or more processors222may determine the peak voltage of the current pulse based on the normalized optical waveform.

FIG. 3is a diagram of an example optical device testing system300described herein. As shown inFIG. 3, the optical device testing system300may include a rack302, and one or more motherboards304. The optical device testing system300may include the DC power supply120, the driver voltage source122, the pulse generator124, and/or the ground206. A motherboard304, of the one or more motherboards304, may include a set of card edge connectors202. Each card edge connector202may be configured to physically hold and/or to electrically connect to a PCB102(e.g., in a similar manner as that described above in relation toFIG. 2). For example, the card edge connector202may include a recess to hold the PCB102and may include one or more traces that connect to one or more traces108of the PCB102(e.g., when the PCB102is inserted in the recess of the card edge connector202). In some implementations, the optical device testing system300may be configured to perform reliability stress testing of each optical device106associated with the PCBs102that are held by each of the sets of card edge connectors202that are associated with the one or more motherboards304.

In some implementations, a motherboard304, of the one or more motherboards304, may be physically connected and electrically connected to a set of card edge connectors202that are associated with the motherboard304. In some implementations, the motherboard304may be connected to the DC power supply120, the driver voltage source122, the pulse generator124, and/or the ground206(e.g., that are configured in a similar manner as that described above in relation toFIG. 2). For example, the DC power supply120may be electrically connected to a card edge connector202, of the set of card edge connectors202, to provide power to an electrical driver circuit104of a PCB102held by the card edge connector202(e.g., in a similar manner as that described above in relation toFIG. 2). As another example, the driver voltage source122may provide a charge current to one or more capacitors116of the electrical driver circuit104, and/or the pulse generator124may provide a trigger signal to a switch110of the electrical driver circuit104(e.g., in a similar manner as that described above in relation toFIG. 2). Accordingly, the motherboard304may be configured to cause the one or more capacitors116of the electrical driver circuit104to discharge a current pulse to the optical device106and thereby cause the optical device106to emit an optical output pulse.

In some implementations, the motherboard304may be configured to provide at least one clock/trigger signal to the switch110of the electrical driver circuit104to cause the one or more capacitors116of the electrical driver circuit to discharge the current pulse to the optical device106and cause the optical device106to emit the optical output pulse. In some implementations, the motherboard304may split the at least one clock/trigger signal via clock signal buffers to control multiple PCBs102associated with the set of card edge connectors202that are associated with the motherboard304. In this way, the motherboard304may cause the optical devices106of PCBs102held by the set of card edge connectors202to operate at the same time for reliability stress testing of multiple optical devices106.

In some implementations, the optical device testing system300may include an environmental chamber (not shown inFIG. 3) that is configured to hold the rack302, the one or more motherboards304, and the respective sets of card edge connectors202that hold PCBs102within an internal portion of the environmental chamber. The optical device testing system may include one or more handles306that facilitate placement of the rack302within the internal portion of the environmental chamber (e.g., the one or more handles306allow the rack302to be lifted and placed in the internal portion of the environmental chamber). In some implementations, environmental chamber may be configured to cause a temperature of the internal portion of the environmental chamber to be greater than or equal to −40 degrees Celsius and less than or equal to 125 degrees Celsius and a relative humidity to be up to 95% (e.g., less than or equal to 95%, as required by a high temperature operating life (HTOL) test, a low temperature operating life (LTOL) test, a power temperature cycling (PTC) test, a wet high temperature operating life (WHTOL) test, and/or a dew test). In this way, environmental chamber may cause the optical devices106of PCBs102held by the sets of card edge connectors202associated with the one or more motherboards304to be subject to an environmental stress test.

As indicated above,FIG. 3is provided as an example. Other examples may differ from what is described with regard toFIG. 3.

FIG. 4is a diagram of an example clock signal400described herein. As described above, a motherboard304may be configured to provide at least one clock/trigger signal. In some implementations, the motherboard304may split a control signal to provide the clock/trigger signal to a set of PCBs102via card edge connectors202associated with the motherboard304. For example, as shown inFIG. 4, the motherboard304may include a structure (e.g., a tree structure) of clock signal buffers to split a clock/trigger signal into multiple portions (e.g., four portions per clock signal buffer). In this way, the same clock/trigger signal may be provided to a plurality of PCBs102via card edge connectors202of the set of card edge connectors202.

As indicated above,FIG. 4is provided as an example. Other examples may differ from what is described with regard toFIG. 4.