Voltage mode, high accuracy battery charger

A circuit for controlling a charging parameter provided to a rechargeable battery. The circuit includes a power control circuit configured to provide a power control signal representative of a power output level of a DC source, and a control signal generating circuit configured to reduce the charging parameter provided to the battery if the power output level exceeds a predetermined power threshold level. An electronic device having such a circuit and a method is also provided. The circuit may be used with a DC source that supplies power to recharge a rechargeable battery. The DC source may have a non-fixed output voltage level such as from a controllable DC source or a variable DC source.

FIELD OF THE INVENTION

The present invention relates to power systems for electronic devices, and in particular to a power management circuit for managing and limiting an output power level provided to a rechargeable battery.

DETAILED DESCRIPTION OF EXEMPLARY EMBODIMENTS

FIG. 1depicts a voltage mode battery charger system10according to one exemplary embodiment. The system10includes a voltage mode battery charger circuit12for charging one or more batteries16using a DC source14. The DC source may be an AC/DC adapter or other power supply. Circuit12operates to control the duty cycle of the Buck converter circuit18(comprising an inductor and capacitor, as is well understood in the art) via switches20, to control the amount of charging power delivered to the battery16. As an overview, circuit12controls the duty cycle of the Buck converter18by monitoring the source current, the battery charging current (current mode) and the battery voltage (voltage mode). Battery charging current is sensed across the sense resistor (or impedance) Rsch. Instead of sensing the current through the inductor (as in conventional current mode topologies), the present invention uses a voltage mode topology by sensing the current across Rsch. In this manner, and by utilizing both battery current control and voltage, the present invention achieves more accurate charging of the battery towards the end of the charging cycle, and provides more accurate charge termination than can be achieved with conventional current mode charging topologies. The details of the system10are described below.

Essentially, the charger circuit12operates to control the duty cycle of the buck converter18by controlling the power on the compensation capacitor Ccomp38. The circuit12includes a battery current control section comprised of sense amplifier26and transconductance amplifier28, a battery voltage control section comprised of summing block30and transconductance amplifier32, and a power control section comprised of sense amplifier34and transconductance amplifier36. The battery current control section and battery voltage control section each generate signals indicative of the battery current and voltage, respectively. The power control section generates a signal indicative of the power available from the source14. Each of these sections is combined (at node60), and if any of these sections exceeds a threshold, the power delivered to the charge capacitor decreases, thereby reducing the duty cycle of the Buck converter. This operation is described in greater detail below.

The duty cycle of the Buck converter18is controlled by the comparator40, via switches20. The input of the comparator40is the voltage on the compensation capacitor (Ccomp)38and a sawtooth signal generated by the oscillator44. The output of the comparator40is a PWM signal68, whose pulse width (duty cycle) is reflected in the intersection of the amplitude of the voltage on Ccomp38and the sawtooth signal. In this sense, the duty cycle of the PWM signal thus generated is based on the voltage on the compensation capacitor38and the sawtooth signal generated by the oscillator44. “Based on”, as used herein, is to be interpreted broadly and generally means “as function of” or “related to”. The higher the amplitude of the voltage on Ccomp, the greater the duty cycle of the PWM signal68. In the exemplary embodiment, the sawtooth signal is a fixed frequency signal, and the duty cycle of the PWM is therefore adjusted by adjusting the amplitude of the voltage on Ccomp38. Ccomp38is charged by the current source42. When no signal is generated by any of the current control section, the voltage control section or the power control section, the current source charges Ccomp to maximum level, and thus the PWM is at maximum duty cycle and the Buck converter is delivering maximum charging current and voltage to the battery. Any signal generated by the current control section, the voltage control section or the power control section acts as a sink to the compensation capacitor38, thereby reducing the voltage on the compensation capacitor and thereby reducing the duty cycle of the PWM signal. In this manner, charging current is controllably delivered to the battery16. The particulars of the Buck converter18and switches20are well understood in this art, and are not important to the present invention, and may be generalized as a controllable DC/DC converter circuit.

Current Control

The current control section (circuit) includes a sense amplifier26and a transconductance amplifier28. The sense amplifier monitors the battery charging current across the sense impedance Rsch24, and generates a signal proportional to battery charge current. The transconductance amplifier28receives the output of the sense amplifier26and compares that signal with a programmed (desired) battery current signal Ich. As a general matter, the inputs of the transconductance amplifier28are voltage signals, and the output is a proportional current signal. The output of the transconductance amplifier is the current control signal62, which is proportional to the amount the battery charging current exceeds the programmed Ich. Ich is zero until the battery charging current exceeds the programmed current value Ich. The programmed value Ich is set to according to the particular battery type and requirements, for example set to charge a conventional LiIon battery, as is well understood in the art.

If the battery charging current exceeds the threshold Ich, the amplifier28generates a proportional current control signal62. Since the output of the amplifier is coupled to the negative side of the current source42(at node60), any signal generated by the amplifier28acts to sink current from the source42. In turn, this operates to reduce the voltage on Ccomp38, thereby reducing the duty cycle of the PWM signal68and reducing the charging current delivered to the battery. Since the output current control signal62is proportional to the input values, the duty cycle is dynamically adjusted as a function of battery charging current.

The current sense amplifier26may be a custom or off-the-shelf amplifier, as is readily available in the art. However, as is also understood in the art, amplifier26must provide large common mode voltage rejection. Accordingly, and referring now toFIG. 2, another aspect of the present invention is an amplifier configuration to alleviate the requirement for large common mode voltage rejection. The sense amplifier26depicted inFIG. 2includes a switch48controlled by an operational amplifier46, and gain resistors R150and R252. The amplifier26ofFIG. 2is not sensitive to common mode voltage. Rather, the switch transfers the floating differential voltage that appears across Rsch by referring it to ground and amplifying the voltage according to the gain given by R2/R1.

Voltage Control

The voltage control section (circuit) includes the summing block30and a transconductance amplifier32. In the exemplary embodiment, the summing block30includes three inputs: a high-precision reference or trim voltage Ref, a voltage set (Vset) and a voltage correction (Vcor) signal. In the exemplary embodiment, the battery16is a LiIon battery. LiIon batteries are very sensitive to overvoltage conditions, and indeed become hazardous if overcharged. Thus, the reference or trim signal Ref is accurate to within the tolerance required by the battery. For LiIon, the tolerance is on the order of +/−0.005 Volts. However, other battery types and reference voltage requirements are equally contemplated herein. Vset represents a voltage setting value, usually supplied by the manufacturer of the battery. Vcor is a correction signal that is proportional to the charging current, and is provided as a compensation signal for the particulars of the charging apparatus and for parasitic resistance associated with the battery (since battery voltage cannot be measured directly, and one must factor in parasitic resistance). Although not shown, Vcor can be obtained by tapping a voltage divider placed in parallel with the output of sense amplifier26. These three signals are summed in a weighted fashion in summing block30. For example, the output of the summing block30can be set to the reference voltage+(Vset/x)+Vcor/y); where x and y are chosen in accordance with the desired voltage setting value and correction value, respectively. Vcor and Vset need not be as accurate as the reference voltage, since their contribution is divided diminished by x and y.

The output weighted voltage signal from the summer block30may be generally deemed as a predetermined battery voltage threshold signal. The transconductance amplifier32compares the output of the summer block to the battery voltage. The output of the amplifier32is a voltage control signal64, which is proportional to the amount the battery voltage exceeds the threshold established by the summing block. As with the current control section described above, signal64is nonzero if the battery voltage exceeds the threshold determined by the summer block. Since the output of the amplifier32is coupled to the negative side of the current source42(at node60), any signal64generated by the amplifier32acts to sink current from the source. In turn, this operates to reduce the voltage on Ccomp38, thereby reducing the duty cycle of the PWM signal68and reducing the charging current delivered to the battery. Since the output64of the amplifier32is proportional to the input values, the duty cycle is dynamically adjusted to achieve a desired battery voltage.

Power Control

The power control section (circuit) includes a sense amplifier34and a transconductance amplifier36. The power control section is provided to reduce the duty cycle of the Buck converter, and thereby reduce the charging current delivered to the battery if the DC source needs to deliver more power to an active system72(e.g., portable electronic device) attached to the source. The active system is coupled in parallel to the charging system10across the sense resistor Rsac. Since the total amount of power provided by the source14is fixed, in a well-designed system the load requirements of the active system and battery charging circuit are balanced. The power control section ensures that the active system always takes priority (in terms of power requirements) by reducing the charging current to meet the demands of the active system. Accordingly, the power control section generates a power control signal66proportional to the amount of power required by the battery charger and the active system exceeds the threshold Iac_μm. Iac_μm is typically the maximum that can be delivered by the adapter source14. For example, the source14may be simultaneously supplying power to an active system (not shown) and charging current to the battery. If the portable system requires more power, charging current to the battery is accordingly reduced to meet the demands of the system. The source14is generally defined as a DC power source, as may be supplied from an AC/DC adapter. Since the output voltage level provided by the DC source14is constant, it is enough to limit the power of the DC source14by monitoring and limiting current output of the DC source.

The sense amplifier34monitors the total adapter current delivered by the source14across the sense impedance Rsac22. The total adapter (source) current includes the system current (i.e., current delivered to a portable system (not shown) connected to the source14) and the battery charger circuit12(which is a measure of the charging current divided by duty cycle of the Buck converter18). The signal across the sense resistor Rsac is a signal proportional to the total adapter current. The transconductance amplifier36receives the output of the sense amplifier34and compares that signal with a power threshold signal Iac_lim. Thus, if the signal across the sense resistor is larger than Iac_lim, this indicates that the system is requiring more power, and accordingly battery charging current is to be reduced. Of course, this limit signal may be fixed, or may be adjusted based on the dynamic power requirements of the system and/or changes in the source. The output of the transconductance amplifier is the power control signal66, which is zero until the power required by the battery charger and the active system exceeds the threshold value lac_lim.

If the power required by the battery charger and the active system exceeds the threshold lac_lim, the amplifier36generates a proportional power control signal66. Since the output of the amplifier is coupled to the negative side of the current source42(at node60), any signal generated by the amplifier36acts to sink current from the source. In turn, this operates to reduce the voltage on Ccomp38, thereby reducing the duty cycle of the PWM signal68and reducing the charging current delivered to the battery. Since the output66of the amplifier36is proportional to the input values, the duty cycle is dynamically adjusted as a function of balancing power demands between a system and the battery, and so as not to exceed a maximum power output of the DC source14.

FIG. 3depicts a timing diagram70representing the PWM signal68(bottom figure) and the intersection between the voltage on the compensation capacitor, Vccomp, and the sawtooth signal44(top figure). In the present exemplary embodiment, Vccomp is essentially a DC signal whose amplitude is moved up by the current source42, and down by either the current control signal62, the voltage control signal64or the power control signal66. In other words, the value (amplitude) of Vccomp is the sum of signals (42−(62,64and/or66)). By moving the value of Vccomp downward, the duty cycle of PWM signal is decreased.

Thus, with present invention, the duty cycle of the PWM signal can be adjusted using a differential the compensation capacitor. In the exemplary embodiments, adjusting the PWM is accomplished dynamically as a function of battery charging current, battery voltage and/or system power requirements. The topology depicted inFIG. 1is a voltage mode topology. Voltage mode topology means that the sense resistor Rsch is placed outside of the Buck converter, and thus the current across this resistor is a DC value (without ripple).

In another embodiment, a power management circuit12aas further detailed herein may be utilized to control a charging power level provided to a rechargeable battery16. To do so, the power management circuit12amay be used to control a controllable DC source directly (FIG. 4A) or a DC to DC converter (FIG. 4B) where the output voltage of the associated DC source in each embodiment may not provide a fixed output voltage level.

FIG. 4Aillustrates an electronic device400having a power management circuit12aconsistent with the invention for controlling a battery charging parameter, e.g., battery charging current and/or voltage, provided to the rechargeable battery16. In the embodiment ofFIG. 4A, this may be done by controlling an output power level of the controllable DC source404. The electronic device400may be any variety of electronic devices including a laptop computer, cell phone, personal digital assistant, and the like. Power from the controllable DC source404may be utilized to supply power to the system72, to the battery16, or some combination of both in various power supply modes. The battery16may include one or a plurality of batteries. A battery16may be a rechargeable battery of various types such as lithium-ion, nickel-cadmium, nickel-metal hydride batteries, or the like.

The controllable DC source404may be any variety of such sources known in the art, e.g., a controllable ACDC adapter that accepts AC input voltage and provides a controllable DC output voltage based on an appropriate control signal. The control signal may be provided by the power management circuit12aalong path421. The path421from the power management circuit12ato the controllable DC source404may be a separate path utilizing any variety of communication protocols known in the art. For instance, the controllable DC source404may be configured with a serial communication interface, e.g., RS232, to receive a serial control signal from the power management circuit12a. The controllable DC source404may alternatively be configured with an analog interface to accept an analog control signal. Alternatively, the separate path421may not be necessary. For instance, the control signal from the power management circuit12amay be modulated onto the power line25. In such an instance, both the power management circuit12aand the controllable DC source404are adapted with modulation/demodulation circuitry known in the art to generate the feedback control signal that is transposed onto the power line25.

The power management circuit12amay include a power control circuit471and a control signal generating circuit473. In general, the power control circuit471provides a power control signal to the control signal generating circuit473representative of an output power level of the controllable DC source404. The control signal generating circuit473may include a plurality of error amplifiers to compare signals, e.g., the power control signal, with an associated threshold level for each monitored parameter similarly to that previously detailed regarding the circuit12ofFIG. 1. For instance, the plurality of error amplifiers may be configured as an analog “wired-OR” topology such that the error amplifier that first detects a condition exceeding the associated maximum threshold level controls the command signal to the controllable adapter404. An appropriate control signal may then be communicated to the controllable DC source404, e.g., to lessen an output power parameter of the source404if a maximum threshold limit is reached.

FIG. 4Billustrates another embodiment of an electronic device400ahaving a power management circuit12aconsistent with the invention for controlling a battery charging parameter, e.g., battery charging current and/or voltage, by controlling a DC to DC converter18. The DC source406provides power to recharge the battery via the DC to DC converter18. The DC source406may have an output voltage level that varies over time. For example, the DC source406may be a solar source where the output voltage level varies with light received by the source. The DC source406may also be a fuel cell. The DC source406may also provide a fixed output voltage level that is different from one that the system anticipated. For instance, a user of the electronic device400amay utilize a fixed voltage output source of 15 volts when the electronic device400aexpects a 20 volt source. Advantageously, the power management circuit12enables maximum power to be delivered from such DC sources with variable output voltage levels as long as the maximum current output of such sources is not also exceeded.

The control signal generating circuit473may provide a control signal to the DC to DC converter18. The control signal may be a PWM signal68as previously detailed and the DC to DC converter18may be any variety of DC to DC converters known in the art. Other elements ofFIG. 4Band operation thereof are similar to those elements previously detailed regardingFIG. 4A. Hence, similar circuit elements are labeled similarly and any repetitive description of the elements or operation thereof is omitted herein for clarity.

Turning toFIG. 5A, an exemplary circuit diagram of one embodiment of the power management control circuit12ais illustrated showing details of the control signal generating circuit473. The control signal generating circuit473includes a plurality of error amplifiers36,472,28,32to compare various signals to associated threshold levels. Various elements of the control generating circuit473and operation thereof are similar to the operation of the circuit12previously detailed regardingFIG. 1. Hence, similar circuit elements are labeled similarly and any repetitive description of the elements or operation thereof is omitted herein for clarity.

Because the output of the controllable DC source404is variable and not fixed, the control signal generating circuit473may include both a current limit error amplifier36and a power limit error amplifier472. The adapter current limit error amplifier36compares a signal representative of the current output of the controllable DC source404with a current limit Iac-lim. The power limit error amplifier472compares a signal representative of the power output of the controllable DC source404with a power limit level. The control signal generating circuit473will reduce the duty cycle of the PWM control signal provided by comparator40if the current limit or power threshold limit is reached. The controllable DC source404may then be responsive to the PWM control signal to reduce its output power level in such an instance. The comparator40may be replaced by any variety of control circuits responsive to comparing the voltage on the compensation capacitor38with the sawtooth signal from oscillator44to provide any variety of control signal, e.g., an analog or digital signal, to control the output voltage of the controllable DC source.

The power control circuit471may include the sense amplifier34coupled to the sense resistor22to provide a signal representative of the current output of the controllable DC source404. The power control circuit471may further include a power conversion circuit577. The power conversion circuit577may receive the signal from the output of the sense amplifier34representative of the current output of the controllable DC source404and another signal VAD representative of the voltage output of the controllable DC source404and provide a power control signal to error amplifier472representative of the output power level of the controllable DC source404.

FIG. 5Billustrates another embodiment consistent withFIG. 4Bwhere the power management circuit12aprovides a control signal to the DC to DC converter18to control a charging parameter provided to the rechargeable battery16. The DC source406may have an output voltage level that varies over time as previously detailed regardingFIG. 4B. The control signal may be a PWM signal as previously detailed and the DC to DC converter18may be any variety of DC to DC converters known in the art. Other elements ofFIG. 5Band operation thereof are similar to those elements previously detailed regardingFIG. 5A. Hence, similar circuit elements are labeled similarly and any repetitive description of the elements or operation thereof is omitted herein for clarity.

Turning toFIG. 6, more details of an exemplary power control circuit471and power conversion circuit577ofFIGS. 5A and 5Bare illustrated for providing the current signal to error amplifier36and power signal to error amplifier472of the control signal generating circuit473. The power conversion circuit577may include classical configurations of analog or digital multiplier topologies. These approaches, however, may need trimming to achieve a desired accuracy. The power conversion circuit577may also include a ramp oscillator608, a comparator610, a multiplier612, and a filter614as further detailed herein.

In general, the power control circuit471may include the sense amplifier34that monitors the voltage drop across sense resistor22and provides an IAD signal to the noninverting input terminal of the comparator610. The IAD signal may be a DC voltage signal representative of the current from the DC source404or406. A fixed frequency sawtooth signal may then be provided to the inverting input of the comparator610by a ramp oscillator608. The output of the ramp oscillator44of the control signal generating circuit473may also be utilized to provide this signal to the comparator610. As a result, the comparator610provides an adapter current pulse width modulated signal IAD_PWM where the pulse width or duty cycle is based on the value of the IAD signal.

The multiplier612multiplies the IAD_PWM signal with a VAD signal representative of the output voltage level of the DC source404or406to obtain a power_PWM signal. The power_PWM signal may be a pulse width modulated signal having a pulse width representative of the current output of the DC source404or406and having an amplitude representative of the voltage output of the DC source404or406. As such, the power_PWM signal is representative of the instantaneous output power level of the DC source404or406. The power_PWM signal may then be input to a filter614which in turn outputs a power signal having a DC voltage level. Such a power signal output from the filter614may then be provided to the error amplifier472of the control signal generating circuit473. If the instantaneous output power level increases beyond the predetermined power threshold level, the error amplifier472would cause the comparator40provide a PWM signal to reduce a charging parameter provided to the battery. The PWM signal may be provided to the controllable DC source404or the DC to DC converter18.

The power control circuit471may also include a current control circuit606. The current control circuit606includes the sense amplifier34to provide the IAD signal to the control signal generating circuit473. The control signal generating circuit473may have an error amplifier36to accept this IAD signal and compare it to a current threshold limit. If the output current level increases beyond a predetermined current limit, the control generating circuit473would provide a control signal to reduce a charging parameter, e.g., charging current, provided to the battery16.

Turning toFIG. 7, plots of various signals over time are illustrated to further explain the operation of the power control circuit471ofFIG. 6. The two input signals received by the comparator610, or the IAD signal711and the sawtooth signal714, are illustrated in graph708. The sawtooth signal714may be a fixed frequency signal such that the intersection of the sawtooth signal714and the IAD signal711defines the pulse width or duty cycle of the resultant IAD_PWM signal716. For instance, the time interval between time t1and time t3represents one period. The IAD_PWM signal716is at a digital zero between times t1and t2and a digital one between times t2and t3. Hence, the time interval between times t2and t3defines the pulse width or duty cycle of the IAD_PWM signal716from the comparator610.

As the IAD signal711increases from the position shown in graph708, the pulse width of the resulting IAD_PWM signal716also increases. Similarly, as the IAD signal711decreases from the position shown in graph708, the pulse width of the resulting IAD_PWM signal716also decreases. The amplitude of the IAD_PWM signal716has a nominal value x.

The IAD_PWM signal716is then input to the multiplier612and multiplied by a VAD signal representative of the voltage level of the DC source404or406. As such, the output of the multiplier612or the power_PWM signal718results. The power_PWM signal718therefore has a pulse width representative of the current output level of the controllable adapter404and an amplitude y representative of the voltage output level of the controllable adapter404. The power_PWM signal718may then be input to the filter614to provide the power signal720having a constant DC power level over time. This power signal may then be input to the control signal generating circuit473, e.g., to an error amplifier472of this circuit473.

Turning toFIG. 8, a detailed circuit diagram of one embodiment of the power management circuit consistent12awithFIGS. 4A,4B,5A,5B,6and7is illustrated. The components ofFIG. 8similar to earlier detailed components ofFIG. 6are labeled similarly. Hence, any repetitive description of such components is omitted herein for clarity.

The sense amplifier34may be any variety of sense amplifiers available in the art. In the embodiment ofFIG. 8, the sense amplifier34includes a transistor MP1controlled by an operational amplifier6a, and gain resistors R1and R2. Similar to the embodiment illustrated inFIG. 2, this sense amplifier34alleviates the requirement for large common mode voltage rejection. The sense amplifier34provides the IAD signal.

The voltage sampling circuit807may include a pair of resistors R3, R4forming a voltage divider to provide a scaled down version of the output voltage of the controllable adapter to the noninverting input terminal of the operation amplifier1a. The output of the operational amplifier1amay be fed back to the inverting input terminal. Those skilled in the art will recognize a variety of voltage sampling circuits to provide the VAD signal to the multiplier612.

The multiplier612may be a power buffer which effectively shifts the amplitude of the input IAD_PWM signal to an amplitude level representative of the voltage level of the controllable adapter. As such, the power_PWM signal is provided at the output of the power buffer. The filter614may be an RC filter having a resistor coupled in series with an input to the filter and a node814. Coupled to the node814and ground may be a capacitor CF. The RC filter accepts the input power_PWM signal and provides the output power signal having a DC voltage value representative of the output power level of the DC source.

Turning toFIG. 9, another embodiment of a power management circuit12bis illustrated. The power management circuit12bincludes a presence circuit903configured to compare a voltage level of the DC source902with a selectable voltage threshold level as further detailed herein. In this way, a single power management circuit12bmay be used with a plurality of DC sources902having an associated plurality of fixed output voltage levels.

In general, the power management circuit12bincludes a control signal generating circuit905and a presence circuit903. The control signal generating circuit905may include a plurality of error amplifiers in circuit916to compare signals with an associated threshold level for each monitored parameter similar to that previously detailed regarding the circuit12ofFIG. 1. For instance, the plurality of error amplifiers may be configured as an analog “wired-OR” topology such that the error amplifier that first detects a condition exceeding the associated maximum level controls the command signal to the DC to DC converter904. The control signal generating circuit may also include PWM circuitry915similar to that detailed in circuit12ofFIG. 1that provides a PWM control signal to the DC to DC converter904. For instance, the duty cycle of the PWM control signal may be reduced to lessen an output power parameter of the DC to DC converter904if one of the error amplifiers detects a condition exceeding an associated maximum threshold level.

The control signal generating circuit905may also include selector circuitry in circuit916known in the art to provide a selector control signals to control, at least, the state of switches SW1, SW3, and SW4based on various monitored conditions and/or commands from the host power management unit (PMU)912.

The presence circuit903generally compares a voltage level of the DC source902with a selectable voltage threshold level. The DC source902may be any variety of DC sources providing a fixed output voltage level, e.g., an ACDC adapter with a fixed DC output voltage. Any plurality of DC sources may be utilized providing an associated plurality of fixed output DC voltage levels. For example, one ACDC adapter may provide a 15 volt DC output while another ACDC adapter may provide a 20 volt DC output. The selected voltage threshold level V_SEL is selected based on the expected fixed output voltage level of the particular DC source902. The selected voltage threshold level V_SEL may typically be a nominal value less than the expected output voltage level. Therefore, if the DC source is present and providing a satisfactory voltage level relative to its expected fixed voltage level, the comparison will provide a signal indicative of this case.

To perform this comparison, the presence circuit903may include a comparator931accepting a voltage signal V_DC representative of the voltage level of the DC source902at its noninverting input terminal. The comparator931may also accept the selectable voltage threshold level V_SEL at its inverting input terminal. If the voltage level of the DC source exceeds the selected threshold level, the comparator provides a digital one output signal to the control signal generating circuit905indicating that the DC source902is present and providing a satisfactory output voltage.

The selectable voltage threshold level may be selected and provided to the comparator931in a variety of ways. For instance, a selectable threshold voltage circuit932may provide the selectable threshold voltage level. Turning toFIG. 10A, the selectable threshold voltage circuit932may include a resistor network1004configured to receive a reference voltage level V_REF and provide the selected threshold voltage level V_SEL. The resistor network1004may include one or more resistors arranged in a variety of ways know in the art, e.g., a voltage divider, to achieve a desired or selected threshold voltage level. Alternatively, the resistor network1004may include at least one trimmable resistive element that is trimmable to a desired resistive value. The resistive element may be trimmed by any variety of ways known to those skilled in the art, e.g., laser trimming, such that the resistive network1002, in combination with the received reference voltage V_REF, then provides a desired threshold voltage level.

Alternatively, the selectable threshold voltage circuit932may include a memory element1006as illustrated inFIG. 10B. The memory element1006may be any variety of memory element that stores digital information such as, but not limited to, random-access memory (RAM), programmable ROM (PROM), erasable programmable ROM (EPROM), electronically erasable programmable ROM (EEPROM), dynamic RAM (DRAM), magnetic disk (e.g. floppy disk and hard drive), and optical disk (e.g. CD-ROM). The memory element1006may be a one time programmable memory element or may be able to programmed a plurality of times depending on the type of memory utilized and access to the memory element for additional programming. Once a programmed value of a desired analog threshold voltage level is stored in memory, a digital to analog converter (DAC)1008may be utilized to convert the stored digital signal into an analog voltage signal representative of the selected voltage threshold level V_SEL.

Further yet, the selected voltage threshold level V_SEL may alternatively be selected by the host PMU912via instructions provided to the power management circuit12bvia the host bus980. The host interface913of the power management circuit12bmay provide signals via the internal signal bus982to the selectable voltage threshold circuit932such that the desired threshold level may be dynamically programmable by the host PMU912.

There is thus provided a circuit for controlling a charging parameter provided to a rechargeable battery. The circuit includes a power control circuit configured to provide a power control signal representative of a power output level of a DC source, and a control signal generating circuit configured to reduce the charging parameter provided to the battery if the power output level exceeds a predetermined power threshold level.

There is thus also provided another circuit including a presence circuit configured to compare a voltage level of a DC source having a fixed output voltage level with a selectable voltage threshold level and to provide a presence signal representative of a presence of the DC source if the voltage level exceeds the selectable threshold voltage level. This circuit may also include a control signal generating circuit configured to receive at least the presence signal and further configured to provide a control signal in response to at least the presence signal.

Those skilled in the art will recognize numerous modifications to the present invention. These and all other modifications as may be apparent to one skilled in the art are deemed within the spirit and scope of the present invention, only as limited by the appended claims.