Memory device containing dual etch stop layers for selector elements and method of making the same

A refractory metal-containing etch stop layer, a ruthenium etch stop layer, and a conductive material layer can be sequentially formed over an electrode layer and a selector material layer. A sequence of anisotropic etch processes can be employed to etch the conductive material layer selective to the ruthenium etch stop layer, to etch the ruthenium etch stop layer selective to the refractory metal-containing etch stop layer, and to etch the refractory metal-containing etch stop layer within minimal overetch into the electrode layer. The selector material layer can be subsequently anisotropically etched without exposure to the plasma of etchant gases for etching the refractory metal-containing etch stop layer and the conductive material layer, which may include a fluorine-containing plasma that can damage the selector material.

FIELD

The present disclosure relates generally to the field of memory devices and specifically to a method of patterning selector elements of magnetoresistive random access memory (MRAM) memory devices using dual etch stop layers, and devices formed by the same.

BACKGROUND

Spin-transfer torque (STT) refers to an effect in which the orientation of a magnetic layer in a magnetic tunnel junction or spin valve is modified by a spin-polarized current. Generally, electric current is unpolarized with electrons having random spin orientations. A spin polarized current is one in which electrons have a net non-zero spin due to a preferential spin orientation distribution. A spin-polarized current can be generated by passing electrical current through a magnetic polarizer layer. When the spin-polarized current flows through a free layer of a magnetic tunnel junction or a spin valve, the electrons in the spin-polarized current can transfer at least some of their angular momentum to the free layer, thereby producing a torque on the magnetization of the free layer. When a sufficient amount of spin-polarized current passes through the free layer, spin-transfer torque can be employed to flip the orientation of the spin (e.g., change the magnetization) in the free layer. A resistance differential of a magnetic tunnel junction between different magnetization states of the free layer can be employed to store data within the magnetoresistive random access memory (MRAM) cell depending if the magnetization of the free layer is parallel or antiparallel to the magnetization of the polarizer layer, also known as a reference layer.

SUMMARY

According to an aspect of the present disclosure, a method of forming a memory device comprises forming a layer stack including a lower electrode layer, a selector material layer, an upper electrode layer, a refractory metal-containing etch stop layer, a ruthenium etch stop layer, a conductive material layer, and at least one memory material layer over a substrate; patterning the at least one memory material layer into a memory element; patterning the conductive material layer into a conductive pillar using the ruthenium etch stop layer as an etch stop by performing a first anisotropic etch process having a first etch chemistry that etches the conductive material layer selective to ruthenium; patterning the ruthenium etch stop layer into an ruthenium plate using the refractory metal-containing etch stop layer as an etch stop by performing a second anisotropic etch process having a second etch chemistry that etches ruthenium selective to a material of the refractory metal-containing etch stop layer; patterning the refractory metal-containing etch stop layer into refractory metal-containing etch stop plate by performing a third anisotropic etch process having a third etch chemistry that etches a material of the refractory metal-containing etch stop layer selective to a material of the upper electrode layer without etching through the upper electrode layer; and anisotropically etching the upper electrode layer, the selector material layer, and the lower electrode layer by performing additional anisotropic etch processes.

According to another aspect of the present disclosure, a memory device comprises a first electrically conductive line; a memory pillar structure comprising a lower electrode plate, a selector material plate, an upper electrode plate, a refractory metal-containing etch stop plate, a ruthenium etch stop plate, a conductive pillar, and a memory element and overlying the first electrically conductive line; and a second electrically conductive line overlying the memory pillar structure.

DETAILED DESCRIPTION

Selector elements (also known as steering elements), such as ovonic threshold switch (OTS) selector elements, are used to select an individual memory cells in an array of memory cells. In this case, each memory cell includes a series connection of a memory element and a selector element. The present inventors realized that ovonic threshold switch materials can be degraded by exposure to fluorine containing plasma an anisotropic etch process, such as a reactive ion etch process. For example, exposure to fluorine containing plasma can increase the leakage current of ovonic threshold switch materials. However, fluorine-containing plasma is effective in etching various metallic materials of the memory cell that overly the ovonic threshold switch material. The methods and structures of the embodiments of the present disclosure utilize dual etch stop layers overlying the ovonic threshold switch selector to reduce or avoid exposure to fluorine-containing plasma that can damage the ovonic threshold switch selector. Specifically, dual etch stop layers including a stack of a ruthenium etch stop layer and a refractory metal-containing etch stop layer can be used to pattern the ovonic threshold switch selector in an MRAM device without significant exposure to fluorine-containing plasma.

As used herein, a first surface and a second surface are “vertically coincident” with each other if the second surface overlies or underlies the first surface and there exists a vertical plane or a substantially vertical plane that includes the first surface and the second surface. A substantially vertical plane is a plane that extends straight along a direction that deviates from a vertical direction by an angle less than 5 degrees. A vertical plane or a substantially vertical plane is straight along a vertical direction or a substantially vertical direction, and may, or may not, include a curvature along a direction that is perpendicular to the vertical direction or the substantially vertical direction.

As used herein, a “memory level” or a “memory array level” refers to the level corresponding to a general region between a first horizontal plane (i.e., a plane parallel to the top surface of the substrate) including topmost surfaces of an array of memory elements and a second horizontal plane including bottommost surfaces of the array of memory elements. As used herein, a “through-stack” element refers to an element that vertically extends through a memory level.

Referring toFIGS. 1A-1C, an exemplary structure for forming an array of memory elements containing OTS selectors is illustrated. While the memory elements comprise MRAM elements in a cross point array configuration, other memory elements and/or other array configurations may be used.

The array includes a substrate8. The substrate8includes an insulating material layer in an upper portion, and may optionally include additional layers (not illustrated) underneath, which can include, for example, a semiconductor material layer and interconnect level dielectric layers embedding metal interconnect structures therein. In one embodiment, semiconductor devices such as field effect transistors may be provided on the semiconductor material layer, and the metal interconnect structures can provide electrically conductive paths among the semiconductor devices. The exemplary structure includes a memory array region, which is illustrated herein, and a peripheral region (not illustrated) including interconnect structures and/or peripheral devices. Memory cells are subsequently formed in the memory array region.

An optional dielectric etch stop layer18can be formed over the substrate8. The dielectric etch stop layer18includes a dielectric material that can be employed as an etch stop material portion during a subsequent anisotropic etch process. For example, the dielectric etch stop layer18can include silicon nitride or a dielectric metal oxide (such as aluminum oxide). The thickness of the dielectric etch stop layer18can be in a range from 4 nm to 40 nm, although lesser and greater thicknesses can also be employed.

A first dielectric isolation layer110can be deposited over the optional dielectric etch stop layer18. The first dielectric isolation layer110includes a dielectric material such as silicon oxide. The first dielectric isolation layer110can be formed by chemical vapor deposition. The thickness of the first dielectric isolation layer110may be in a range from 50 nm to 500 nm, although lesser and greater thicknesses can also be employed.

A photoresist layer (not shown) can be applied over the first dielectric isolation layer110, and can be lithographically patterned to form a line and space pattern. Elongated openings laterally extending along a first horizontal direction hd1and laterally spaced apart among one another along a second horizontal direction hd2can be formed in the photoresist layer. The width of each opening along the second horizontal direction hd2can be in a range from 10 nm to 50 nm, such as 15 nm to 25 nm, although lesser and greater widths can also be employed. The pitch of the line and space pattern may be in a range from 20 nm to 100 nm, such as from 30 nm to 50 nm, although lesser and greater pitches may also be employed.

The pattern in the photoresist layer can be transferred through the first dielectric isolation layer110by an anisotropic etch process. The photoresist layer can be employed as an etch mask during the anisotropic etch process. First line trenches109can be formed through the first dielectric isolation layer110. The photoresist layer can be subsequently removed, for example, by ashing.

Referring toFIGS. 2A-2C, a metallic liner layer including a metallic barrier material can be deposited in the first line trenches109and over the first dielectric isolation layer110. The metallic liner layer can include a conductive metallic barrier material such as a conductive metallic nitride material (e.g., TiN, TaN, and/or WN) and/or a conductive metallic carbide material (e.g., TiC, TaC, and/or WC). The metallic liner layer can be deposited by chemical vapor deposition or physical vapor deposition. A metallic fill material layer can be deposited over the metallic liner layer. The metallic fill material layer includes a metallic material having high electrical resistivity. For example, the metallic fill material layer can include copper, tungsten, titanium, tantalum, molybdenum, ruthenium, cobalt, or a combination thereof.

Excess portions of the metallic fill material layer and the metallic liner layer can be removed from above the horizontal plane including the top surface128of the first dielectric isolation layer110. The horizontal plane including the surface128defines the boundary between the dielectric isolation layer110and subsequently deposited layers (e.g., layer132L shown inFIGS. 3B and 3Cand described below). Each remaining portion of the metallic fill material layer comprises a first metallic fill material portion124. Each remaining portion of the metallic liner layer comprises a first metallic liner122. Each contiguous combination of a first metallic liner122and a first metallic fill material portion124constitutes a first electrically conductive line12(e.g., word line or bit line). The first electrically conductive lines12laterally extend along the first horizontal direction hd1, and are laterally spaced apart along the second horizontal direction hd2. Alternatively, the first electrically conductive lines12may be formed first over the substrate8, followed by forming the first dielectric isolation layer110between the first electrically conductive lines12.

Referring toFIGS. 3A-3C, a layer stack can be formed over the first electrically conductive lines12and he first dielectric isolation layer110. The layer stack can include, from bottom to top, including a selector layer stack13L, an etch stop layer stack14L, at least one memory material layer15L, and an optional metallic cap layer158L.

The selector layer stack13L can include, from bottom to top, a lower electrode layer132L, an optional lower metallic compound liner133L, a selector material layer134L, an optional upper metallic compound liner135L, and an upper electrode layer136L. Each of the lower electrode layer132L and the upper electrode layer136L includes at least one electrically conductive material. The at least one electrically conductive material may include a non-metallic conductive material. Exemplary non-metallic conductive materials that can be employed for the lower electrode layer132L and the upper electrode layer136L include amorphous carbon, amorphous boron-doped carbon, amorphous nitrogen-doped carbon, metal-carbon alloys or other carbon alloys, and layer stacks thereof. Each of the lower electrode layer132L and the upper electrode layer136L may be free of transition metal elements. Each of the lower electrode layer132L and the upper electrode layer136L may be deposited by chemical vapor deposition, physical vapor deposition, or atomic layer deposition. Each of the lower electrode layer132L and the upper electrode layer136L can have a respective thickness in a range from 1 nm to 10 nm, such as from 2 nm to 5 nm, although lesser and greater thicknesses may also be employed.

Each of the optional lower metallic compound liner133L and the optional upper metallic compound liner135L, if present, can include a conductive metallic compound material that can function as a diffusion barrier material. Exemplary conductive metallic compound materials that can be employed for the optional lower metallic compound liner133L and the optional upper metallic compound liner135L include conductive metallic nitride materials (such as WN, TaN, and/or TiN) and conductive metallic carbide materials (such as WC, TaC, and/or TiC). Each of the lower metallic compound liner133L and the upper metallic compound liner135L may be deposited by chemical vapor deposition, physical vapor deposition, or atomic layer deposition. Each of the lower metallic compound liner133L and the upper metallic compound liner135L can have a respective thickness in a range from 0.5 nm to 4 nm, such as from 1 nm to 2 nm, although lesser and greater thicknesses may also be employed.

The selector material layer134L includes a material that can function as a voltage-dependent switch. Generally, the selector material layer134L can include a threshold switch material which exhibits non-linear electrical behavior, such as an ovonic threshold switch material.

As used herein, an ovonic threshold switch (OTS) material is a material that does not crystallize in a low resistance state under a voltage above the threshold voltage, and reverts back to a high resistance state when not subjected to a voltage above the threshold voltage across the OTS material layer. As used herein, an “ovonic threshold switch material” refers to a material that displays a non-linear resistivity curve under an applied external bias voltage such that the resistivity of the material decreases with the magnitude of the applied external bias voltage. In other words, an ovonic threshold switch material is non-Ohmic, and becomes more conductive under a higher external bias voltage than under a lower external bias voltage.

An ovonic threshold switch material (OTS material) can be non-crystalline (for example, amorphous) in a high resistance state, and can remain non-crystalline (for example, remain amorphous) in a low resistance state during application of a voltage above its threshold voltage across the OTS material. The OTS material can revert back to the high resistance state when the high voltage above its threshold voltage is removed. Throughout the resistive state changes, the ovonic threshold switch material can remain non-crystalline (e.g., amorphous). In one embodiment, the ovonic threshold switch material can comprise layer a chalcogenide material which exhibits hysteresis in both the write and read states. The chalcogenide material may be a GeTe compound or a Ge—Se compound doped with a dopant selected from As, N, and C, such as a Ge—Se—As compound semiconductor material. The ovonic threshold switch material layer can include a selector material layer134L which contains any ovonic threshold switch material. In one embodiment, the selector material layer134L can include, and/or can consist essentially of, a GeSeAs alloy, a GeSe alloy, a SeAs alloy, a GeTe alloy, or a SiTe alloy.

In one embodiment, the material of the selector material layer134L can be selected such that the resistivity of the selector material layer134L decreases at least by two orders of magnitude (i.e., by more than a factor of 100) upon application of an external bias voltage that exceeds a critical bias voltage magnitude (also referred to as threshold voltage). In one embodiment, the composition and the thickness of the selector material layer134L can be selected such that the critical bias voltage magnitude can be in a range from 1 V to 4 V, although lesser and greater voltages can also be employed for the critical bias voltage magnitude. The thickness of the selector material layer134L can be, for example, in a range from 5 nm to 40 nm, such as 10 nm to 20 nm, although lesser and greater thicknesses can also be employed.

The etch stop layer stack14L can include, from bottom to top, a refractory metal-containing etch stop layer142L, a ruthenium etch stop layer144L, and a conductive material layer146L. The refractory metal-containing etch stop layer142L includes a refractory metal-containing material that comprises at least one refractory metal. As used herein, refractory metals refer to five transition metal elements consisting of tantalum, tungsten, rhenium, niobium, and molybdenum. The refractory metal-containing etch stop layer142L can include at least one refractory metal in an elemental form, in the form of an intermetallic alloy, or in the form of a conductive metallic compound with at least one non-metallic element (such as TaN, WN, TaC, or WC). In one embodiment, the refractory metal-containing etch stop layer142L may consist essentially of tantalum, tungsten, rhenium, niobium, molybdenum, intermetallic alloys thereof, or conductive metallic nitride materials thereof. In one embodiment, the refractory metal-containing etch stop layer142L may consist essentially of tantalum nitride. The refractory metal-containing etch stop layer142L can be deposited by physical vapor deposition or chemical vapor deposition. The thickness of the refractory metal-containing etch stop layer142L can have a thickness in a range from 2 nm to 5 nm, such as from 2 nm to 3 nm. The thickness of the refractory metal-containing etch stop layer142L is selected such that the refractory metal-containing etch stop layer142L is thick enough to function as an etch stop structure for an etch process that etches the ruthenium etch stop layer144L, and is thin enough to be etched by a timed anisotropic etch process without etching through the entire underlying upper electrode layer136L.

The ruthenium etch stop layer144L can consist essentially of ruthenium. Ruthenium can be etched in an anisotropic etch process employing chlorine-based plasma, such as a chlorine and oxygen containing plasma, and is resistant to fluorine-based plasma that can etch refractory metals and other metallic materials. Thus, ruthenium can be employed as an etch stop material for an anisotropic etch process that etches the material of the conductive material layer146L. The ruthenium etch stop layer144L can be deposited, for example, by atomic layer deposition or physical vapor deposition. The thickness of the ruthenium etch stop layer144L may be in a range from 2 nm to 5 nm, such as from 2 nm to 3 nm. The thickness of the ruthenium etch stop layer144L is selected such that the ruthenium etch stop layer144L is thick enough to function as an etch stop structure for an etch process that etches the conductive material layer146L, and is thin enough to be etched by an anisotropic etch process with minimum collateral etch into the refractory metal-containing etch stop layer142L.

The conductive material layer146L comprises, and/or consists essentially of, a material selected from an elemental metal other than ruthenium, an intermetallic alloy other than ruthenium-containing alloys, a conductive metallic nitride material, a conductive metallic carbide material, and a conductive carbon-based material. Exemplary elemental metals that can be employed for the conductive material layer146L include refractory elemental metals (such as tantalum, tungsten, rhenium, niobium, and molybdenum) and non-refractory transition metals such as titanium. Exemplary conductive metallic nitride materials include TiN, TaN, and WN. Exemplary conductive metallic carbide materials include TiC, TaC, and WC. Conductive carbon-based materials include amorphous carbon or diamond-like carbon doped with suitable dopant atoms such as nitrogen to increase the electrical conductivity. In one embodiment, the conductive material layer146L can include a tantalum-containing compound material. For example, the conductive material layer146L can consist essentially of tantalum nitride. The conductive material layer146L can be formed by physical vapor deposition or chemical vapor deposition. The thickness of the conductive material layer146L can be in a range from 20 nm to 50 nm, such as from 30 nm to 40 nm, although lesser and greater thicknesses can also be employed.

The at least one memory material layer15L includes at least one memory material that can be patterned into memory elements. In one embodiment, the at least one memory material layer15L can comprises a vertical stack of magnetic junction material layers, i.e., a stack of material layers for forming a magnetic tunnel junction (MTJ) or a spin valve for an MRAM memory cell. For example, the at least one memory material layer15L can include a stack of material layers including, from bottom to top or from top to bottom, a reference layer152L (which is also referred to as a magnetic pinned layer), a tunnel barrier layer154L, and a free layer156L, which together form an MTJ150of an STT MRAM memory cell. The thickness of the MTJ can be in a range from 10 nm to 40 nm, such as 20 nm to 30 nm.

The reference layer152L can have a fixed magnetization direction which can be a horizontal direction or a vertical direction. The reference layer152L can be formed as single ferromagnetic material layer or multiple ferromagnetic material layers that are magnetically coupled among one another to provide a same magnetization direction throughout. The reference layer152L may include a Co/Ni multilayer structure or a Co/Pt multilayer structure. In one embodiment, the reference layer152L can additionally include a thin non-magnetic layer comprised of tantalum or tungsten having a thickness in a range from 0.2 nm to 0.5 nm and a thin CoFeB layer having a thickness in a range from 0.5 nm to 3 nm. The thickness of the reference layer152L can be in a range from 2 nm to 5 nm.

Optionally, the reference layer152L may be provided in a synthetic antiferromagnet (SAF) structure that includes a hard magnetization layer (not expressly shown), an antiferromagnetic coupling layer (e.g., a Ru layer, not expressly shown), and the reference layer152L. In case the reference layer152L is provided as a component of an SAF structure, the magnetization of the hard magnetization layer and the magnetization of the magnetic pinned layer can be antiferromagnetically coupled through the antiferromagnetic coupling layer.

The tunnel barrier layer154L can include a tunnel barrier dielectric material such as magnesium oxide or aluminum oxide. The tunnel barrier layer154L can have a thickness in a range from 0.6 nm to 2 nm, such as from 0.8 nm to 1.2 nm. The tunnel barrier layer154L contacts the reference layer152L, and provides spin-sensitive tunneling of electrical currents between the reference layer152L and the free layer156L. In other words, the amount of electrical current that passes through the tunnel barrier layer154L depends on the relative alignment of magnetization between the reference layer152L and the free layer156L, i.e., whether the magnetization directions are parallel or antiparallel to each other.

The free layer156L can be formed as single ferromagnetic material layer or multiple ferromagnetic material layers that are magnetically coupled among one another to provide a same magnetization direction throughout. The thickness of the free layer156L is less than 2 nm, and preferably less than 1.5 nm, such as from 0.8 nm to 1.5 nm. For example, the free layer156L can include a CoFeB layer and/or a CoFe layer. The free layer156L can be programmed by flowing electrical current along a vertical direction either upward or downward. Additional layers (not shown) may be included in the MTJ150.

The metallic cap layer158L includes a nonmagnetic metallic material such as at least one nonmagnetic transition metal or a nonmagnetic transition metal alloy. For example, the metallic cap layer158L may include, and or may consist essentially of, Ti, V, Cr, Mn, Zr, Nb, Mo, Tc, Ru, Rh, Hf, Ta, W, Re, Os, Jr, alloys thereof, and a conductive metallic nitride or a conductive metallic carbide thereof. The metallic cap layer158L maybe deposited by physical vapor deposition or chemical vapor deposition. The thickness of the metallic cap layer158L may be in a range from 1 nm to 20 nm, such as from 2 nm to 10 nm, although lesser and greater thicknesses can also be employed.

In alternative embodiment, the at least one memory material layer15L is not limited to an MRAM memory cell layer, and can include any memory material, i.e., a material that can be programmed to have at least two different memory states. In one embodiment, the at least one memory material layer15L includes a resistive memory material. As used herein, a “resistive memory material” or a “reversibly resistance-switching material” is a material of which the resistivity can be altered by application of a voltage across the material. As used herein, a “resistive memory material layer” refers to a layer including a resistive memory material. As used herein, a “resistive memory element” refers to an element that includes a portion of a resistive memory material in a configuration that enables programming of the resistive memory material into at least two states having different values of electrical resistance

In one embodiment, the at least one memory material layer15L includes a phase change memory material to form a phase change random access memory (“PCRAM” or “PRAM”) device. As used herein, a “phase change memory material” refers to a material having at least two different phases providing different resistivity. The at least two different phases can be provided, for example, by controlling the rate of cooling from a heated state to provide an amorphous state having a higher resistivity and a polycrystalline state having a lower resistivity. In this case, the higher resistivity state of the phase change memory material can be achieved by faster quenching of the phase change memory material after heating to an amorphous state, and the lower resistivity state of the phase change memory material can be achieved by slower cooling of the phase change memory material after heating to the amorphous state

Exemplary phase change memory materials include, but are not limited to, germanium antimony telluride compounds such as Ge2Sb2Te5(GST), germanium antimony compounds, indium germanium telluride compounds, aluminum selenium telluride compounds, indium selenium telluride compounds, and aluminum indium selenium telluride compounds. These compounds (e.g., compound semiconductor material) may be doped (e.g., nitrogen doped GST) or undoped. Thus, the resistive memory material layer can include, and/or can consist essentially of, a material selected from a germanium antimony telluride compound, a germanium antimony compound, an indium germanium telluride compound, an aluminum selenium telluride compound, an indium selenium telluride compound, or an aluminum indium selenium telluride compound. In this case, the thickness of the at least one memory material layer15L can be in a range from 1 nm to 60 nm, such as from 3 nm to 40 nm and/or from 10 nm to 25 nm, although lesser and greater thicknesses can also be employed.

In another embodiment, the at least one memory material layer15L includes a barrier modulated cell memory material. For example, oxygen-vacancy-containing metal oxides displaying different electrical conductivity characteristics depending on the level of oxygen vacancies can be deposited for the at least one memory material layer15L. An oxygen-vacancy-containing metal oxide can be formed with oxygen deficiencies (e.g., vacancies), or can be annealed to form oxygen deficiencies. One of the electrodes of such a memory device can include a high work function material having a work function greater than 4.5 eV, and can be employed to provide a high potential barrier for electrons at the interface with the reversibly resistance-switching material. As a result, at moderate voltages (below one volt), a very low current will flow through the reversibly resistance-switching material. The energy barrier at the interface between the electrode and the reversibly resistance-switching material can be lowered by the presence of the oxygen vacancies (VO⋅⋅). In this case, the interface between the electrode and the reversibly resistance-switching material can provide the characteristics of a low resistance contact (Ohmic contact). The oxygen vacancies in the metal oxide of the reversibly resistance-switching material function as n-type dopants, thereby transforming the originally insulating metal oxide into an electrically insulating material having a lower resistivity (but still insulating).

When a large forward bias voltage (such as a negative voltage of about −1.5 volt that is applied to the high work function electrode with respect to the opposing electrode) is applied across the reversibly resistance-switching material, the oxygen vacancies drift toward the interface between the high energy barrier material (such as platinum or n-doped polysilicon) and the reversibly resistance-switching material, and as a result, the potential barrier at the interface between the electrode and the reversibly resistance-switching material is reduced and a relatively high current can flow through the structure. The device is then in its low resistance (conductive) state in which the reversibly resistance-switching material functions as a semiconducting material or a conductive material.

The conductive path can be broken by applying a large reverse bias voltage (such as a positive voltage of about 1.5 volt that is applied to the electrode with respect to the lower electrode) across the reversibly resistance-switching material. Under a suitable reverse bias condition, the oxygen vacancies move away from the proximity of the interface between the high work function material and the reversibly resistance-switching material. The resistivity of the reversibly resistance-switching material returns to its high resistance state. Both of the conductive and non-conductive states are non-volatile. Sensing the conduction of the memory storage element (for example, by applying a voltage around 0.5 volts) can easily determine the state of the resistive memory element.

While this specific conduction mechanism may not apply to all metal oxides, as a group, they have a similar behavior: transition from a low conductive state to a high conductive occurs state when appropriate voltages are applied, and the two states are non-volatile. Examples of other materials that can be used for the non-volatile resistive memory elements include hafnium oxide, such as HfOxwhere 1.9<x<2.1. Suitable materials for the lower electrode (e.g., word line) are any conducting material such as Ti(O)N, Ta(O)N, TiN, TiAlN, WN and TaN. Suitable materials for the electrode (e.g., local bit line) include metals and doped semiconductor with a high work function (typically >4.5 eV) capable to getter oxygen in contact with the metal oxide to create oxygen vacancies at the contact. Some examples are TaCN, TiCN, Ru, RuO2, Pt, Ti rich TiOx, TiAlN, TaAlN, TiSiN, TaSiN, IrO2and doped polysilicon. The thicknesses of the electrodes are typically 1 nm or greater. Thicknesses of the metal oxide can be generally in the range of 2 nm to 20 nm.

In yet another embodiment, the resistive memory material employed for the at least one memory material layer15L can include a filamentary metal oxide material such as nickel oxide or TiO2, in which electrically conductive filamentary paths can be formed or removed depending on the external electrical bias conditions. In this case, the at least one memory material layer15L can optionally include a first lower electrically conductive liner layer (such as a lower TiN liner) underlying a resistive memory material layer and a first upper electrically conductive liner layer (such as an upper TiN liner) overlying the resistive memory material layer.

A mask layer160L, such as an ion milling mask material layer160L can be deposited over the metallic cap layer158L, for an MRAM memory device. The ion milling mask material layer160L includes a material that may be employed as a mask material for an ion milling process to be subsequently employed. For example, the ion milling mask material layer160L may include diamond-like carbon (DLC). The thickness of the ion milling mask material layer160L may be in a range from 15 nm to 60 nm, such as from 20 m to 40 nm, although lesser and greater thicknesses can also be employed.

Referring toFIGS. 4A-4C, an optional photoresist layer (now shown) can be applied over the ion milling mask material layer160L, and can be lithographically patterned to form a two-dimensional array of discrete photoresist material portions. An anisotropic etch process can be performed to transfer the pattern of the two-dimensional array of discrete photoresist material portions through the ion milling mask material layer160L. The patterned portions of the ion milling mask material layer160L form a two-dimensional array of mask material portions160, which may be arranged as a two-dimensional periodic array such as a rectangular array. The pitch of the two-dimensional array of the mask material portions160along the second horizontal direction hd2may be the same as the pitch of the first electrically conductive lines12along the second horizontal direction hd2. The photoresist layer can be subsequently removed, for example, by ashing.

An ion milling process can be performed to remove unmasked portions of the metallic cap layer158L and the at least one memory material layer15L. The array of mask material portions160can be employed as an ion milling mask during the ion milling process. The metallic cap layer158L can be patterned into a two-dimensional array of metallic cap plates158. The at least one memory material layer15L can be patterned into an array of memory elements15. In case the at least one memory material layer15L includes a layer stack of the reference layer152L, the tunnel barrier layer154L, and the free layer156L, each memory element15can include an MTJ150comprising a layer stack of a reference layer152, a tunnel barrier layer154, and a free layer156. Each reference layer152can be a patterned portion of the reference layer152L as formed in the processing steps ofFIGS. 3A-3C. Each tunnel barrier layer154can be a patterned portion of the tunnel barrier layer154L as formed in the processing steps ofFIGS. 3A-3C. Each free layer156can be a patterned portion of the free layer156L as formed in the processing steps ofFIGS. 3A-3C. The top surface of the conductive material layer146L can be physically exposed after the ion milling process.

Each memory element15can have a pillar shape. The pillar shape can have at least one tapered sidewall due to the ion milling induced taper. In case the pillar shape has at least one tapered sidewall, the taper angle of the at least one tapered sidewall can be in a range from 1 degree to 30 degrees, such as from 3 degrees to 15 degrees, although lesser and greater taper angles can also be employed. The horizontal cross-sectional shape of each pillar structure may be circular, elliptical, rectangular, of a rounded rectangle, and/or of a two-dimensional generally curvilinear closed shaped. The at least one conductive material layer146L acts as an ion milling buffer, and may be partially recessed during the ion milling.

Referring toFIGS. 5A-5C, a first anisotropic etch process can be performed to etch the remaining unmasked portions of the conductive material layer146L. The chemistry of the first anisotropic etch process can be selected such that the first anisotropic etch process etches the material of the conductive material layer146L selective to ruthenium, i.e., selective to the material of the ruthenium etch stop layer144L. In one embodiment, the selectivity of the first anisotropic etch process relative to ruthenium may be in a range from 3 to 100, such as from 5 to 20. In other words, the ratio of the etch rate of the material of the conductive material layer146L to the etch rate of ruthenium during the first anisotropic etch process may be in a range from 3 to 100, such as from 5 to 30. In one embodiment, the first anisotropic etch process can employ a plasma of a chlorine-free etch gas. For example, if the conductive material layer146L includes a refractory metal or a refractory metal nitride (e.g., TaN), then first anisotropic etch process can employ a fluorine-based plasma generated from an etch gas that is free of chlorine. Exemplary chlorine-free etch gases include hydrofluorocarbon etch gases (CxHyFz) such as CHF3. Alternatively, if the conductive material layer146L includes doped or undoped carbon, then an oxygen plasma employed during the first anisotropic etch process. The first anisotropic etch process can include an overetch step to ensure that all unmasked portions of the conductive material layer146L are removed by the first anisotropic etch process. Thus, collateral etching of the top portions of the ruthenium etch stop layer144L may occur during the terminal portion of the first anisotropic etch process. The duration of the first anisotropic etch process can be selected such that the ruthenium etch stop layer144L is not etched all the way through by the first anisotropic etch. process. Each patterned portion of the conductive material layer146L comprises a conductive pillar146. The conductive pillars146can have a lesser taper angle than the taper angle of sidewalls of the memory elements15and can be wider (e.g., have a greater width, such as a greater diameter) than the width of the overlying MTJ150, such as greater width than the width of the tunnel barrier layer154. For example, the sidewalls of the conductive pillars146can be substantially vertical, or may have a taper angle in a range from 0.1 degree to 5 degrees.

Referring toFIGS. 6A-6C, a second anisotropic etch process can be performed to etch unmasked portions of the ruthenium etch stop layer144L. The chemistry of the second anisotropic etch process can be selected such that the second anisotropic etch process etches ruthenium selective to the material of the refractory metal-containing etch stop layer142L. In one embodiment, the selectivity of the second anisotropic etch process relative to the material of the refractory metal-containing etch stop layer142L may be in a range from 2 to 100, such as from 4 to 20. In other words, the ratio of the etch rate of ruthenium to the etch rate of the refractory metal-containing etch stop layer142L during the second anisotropic etch process may be in a range from 2 to 100, such as from 4 to 30. In one embodiment, the second anisotropic etch process can employ a plasma of a chlorine-containing etch gas. For example, the second anisotropic etch process can employ a chlorine-based plasma generated from an etch gas that includes chlorine. Exemplary chlorine-containing etch gases include Cl2and BCl3. Oxygen and/or argon may be employed during the second anisotropic etch process, such that Cl2and O2etch gases are used to etch the ruthenium etch stop layer144L. The second anisotropic etch process can include an overetch step to ensure that all unmasked portions of the ruthenium etch stop layer144L are removed by the second anisotropic etch process. Thus, collateral etching of the top portions of the refractory metal-containing etch stop layer142L may occur during the terminal portion of the second anisotropic etch process. The duration of the second anisotropic etch process can be selected such that the refractory metal-containing etch stop layer142L is not etched all the way through by the second anisotropic etch process. Each patterned portion of the ruthenium etch stop layer144L comprises a ruthenium etch stop plate144. The ruthenium etch stop plates144can have a lesser taper angle than the taper angle of sidewalls of the memory elements15. For example, the sidewalls of the ruthenium etch stop plates144can be substantially vertical, or may have a taper angle in a range from 0.1 degree to 5 degrees.

Referring toFIGS. 7A-7C, a third anisotropic etch process can be performed to etch unmasked portions of the refractory metal-containing etch stop layer142L. The chemistry of the third anisotropic etch process can be selected such that the third anisotropic etch process etches the material of the refractory metal-containing etch stop layer142L selective to the material of the upper electrode layer136L. In one embodiment, the selectivity of the third anisotropic etch process relative to the material of the upper electrode layer136L may be in a range from 1.5 to 10, such as from 2 to 5. In other words, the ratio of the etch rate of the material of the refractory metal-containing etch stop layer142L to the etch rate of the material of the upper electrode layer136L during the third anisotropic etch process may be in a range from 1.5 to 10, such as from 2 to 5. In one embodiment, the third anisotropic etch process can employ a plasma of a chlorine-free etch gas. For example, the third anisotropic etch process can employ a fluorine-based plasma generated from an etch gas that is free of chlorine. Exemplary chlorine-free etch gases include hydrofluorocarbon etch gases (CxHyFz) such as CHF3. Oxygen and/or argon may be employed during the third anisotropic etch process. The third anisotropic etch process can be a timed etch process with sufficient duration to ensure that all unmasked portions of the refractory metal-containing etch stop layer142L are removed by the third anisotropic etch process. Thus, collateral etching of the top portions of the upper electrode layer136L may occur during the terminal portion of the third anisotropic etch process. The duration of the third anisotropic etch process can be selected such that less than 10 nm, such as 1-2 nm, of the upper electrode layer136L is etched, and the upper electrode layer136L is not etched all the way through by the third anisotropic etch process to avoid damaging the underlying OTS the selector material layer134L with the fluorine plasma. Therefore, the dual etch stop layer (144L,142L) prevents the upper electrode layer136L from being etched all the way through, such that the OTS selector element layer134L is not exposed to damaging fluorine plasma used to etched layer146L. This means that the upper electrode layer136L does not have to act as an etch stop for a deep fluorine plasma etch and the upper electrode layer136L thickness may be reduced. The reduced thickness decreases the stress on the underlying layers and chance of delamination of the upper electrode layer136L during annealing steps, such as an annealing step used to improve the quality of the MTJ150.

Each patterned portion of the refractory metal-containing etch stop layer142L comprises a refractory metal-containing etch stop plate142. The refractory metal-containing etch stop plates142can have a lesser taper angle than the taper angle of sidewalls of the memory elements15. For example, the sidewalls of the refractory metal-containing etch stop plates142can be substantially vertical, or may have a taper angle in a range from 0.1 degree to 5 degrees. Each vertical stack of a refractory metal-containing etch stop plate142, a ruthenium etch stop plate144, and a conductive pillar146is herein referred to as a conductive plate stack14.

Referring toFIGS. 8A-8C, an additional anisotropic etch process can be performed to etch through unmasked portions of the selector layer stack13L. The selector layer stack13L include, from top to bottom, the upper electrode layer136L, the optional upper metallic compound liner135L, the selector material layer134L, the optional lower metallic compound liner133L, and the lower electrode layer132L. The additional anisotropic etch process can include a plurality of anisotropic etch steps including a respective etch chemistry for etching a respective material layer within the selector layer stack13L.

In an illustrative example, the upper electrode layer136L and the optional upper metallic compound liner135L may be etched by an anisotropic etch step employing an oxygen plasma if the liner135L is sufficiently thin. The selector material layer134L may be etched by an anisotropic etch step employing a plasma of a fluorine-free etch gas. In one embodiment, the fluorine-free etch gas employed for the anisotropic etch step for etching the selector material layer134L may be a plasma of a bromine-containing etch gas (such as HBr or Br2) or plasma of methane or another hydrocarbon gas. The lower electrode layer132L and the optional lower metallic compound liner133L may be etched by an anisotropic etch step employing an oxygen plasma if the liner133L is sufficiently thin.

Each patterned portion of the upper electrode layer136L comprises an upper electrode plate136. Each patterned portion of the upper metallic compound liner135L (if present) comprises an upper metallic compound plate135. Each patterned portion of the selector material layer134L comprises a selector material plate134, such as an OTS selector material plate134. Each patterned portion of the lower metallic compound liner133L comprises a lower metallic compound plate133. Each patterned portion of the lower electrode layer132L comprises a lower electrode plate132. Each vertical stack of an upper electrode plate136, an optional upper metallic compound plate135, a selector material plate134, an optional lower metallic compound plate133, and a lower electrode plate132constitute a selector element13.

Memory pillar structures (13,14,15,158) are provided over the first electrically conductive lines12. Each of the memory pillar structures (13,14,15,158) can include a selector element13, a conductive plate stack14, a memory element15, and a metallic cap plate158. The memory pillar structures (13,14,15,158) can be arranged as a periodic two-dimensional array such as a rectangular array.

Referring toFIGS. 9A-9C, the two-dimensional array of mask material portions160can be removed, for example, by ashing. At least one dielectric material can be deposited over, and between, the memory pillar structures (13,14,15,158). Excess portions of the at least one dielectric material can be removed from above the horizontal plane including the top surfaces of the memory pillar structures (13,14,15,158) by a planarization process such as a chemical mechanical planarization (CMP) process. Remaining portions of the at least one dielectric material comprises a dielectric isolation structure (172,174). The dielectric isolation structure (172,174) can include an optional dielectric liner172and a dielectric fill material portion174. The optional dielectric liner172includes a dielectric diffusion barrier material such as silicon nitride. The thickness of the dielectric liner172can be in a range from 3 nm to 10 nm, although lesser and greater thicknesses can also be employed. The dielectric fill material portion174includes a planarizable dielectric material such as undoped silicate glass or a doped silicate glass.

Referring toFIGS. 10A-10C, a second dielectric isolation layer210can be deposited over the two-dimensional array of memory pillar structures (13,14,15,158). The second dielectric isolation layer210includes a dielectric material such as silicon oxide. The second dielectric isolation layer210can be formed by chemical vapor deposition. The thickness of the second dielectric isolation layer210may be in a range from 50 nm to 500 nm, although lesser and greater thicknesses can also be employed.

A photoresist layer (not shown) can be applied over the second dielectric isolation layer210, and can be lithographically patterned to form a line and space pattern. Elongated openings laterally extending along the second horizontal direction hd2and laterally spaced apart among one another along the first horizontal direction hd1can be formed in the photoresist layer. The width of each opening along the first horizontal direction hd1can be in a range from 10 nm to 50 nm, such as 15 nm to 25 nm, although lesser and greater widths can also be employed. The pitch of the line and space pattern along the first horizontal direction hd1can be the same as the pitch of the two-dimensional array of memory pillar structures (13,14,15,158) along the first horizontal direction hd1. The pitch of the line and space pattern may be in a range from 20 nm to 100 nm, such as from 30 nm to 50 nm, although lesser and greater pitches may also be employed.

The pattern in the photoresist layer can be transferred through the second dielectric isolation layer210by an anisotropic etch process. The photoresist layer can be employed as an etch mask during the anisotropic etch process. Second line trenches can be formed through the second dielectric isolation layer210. The photoresist layer can be subsequently removed, for example, by ashing.

A metallic liner layer including a metallic barrier material can be deposited in the second line trenches and over the second dielectric isolation layer210. The metallic liner layer can include a conductive metallic barrier material such as a conductive metallic nitride material (e.g., TiN, TaN, and/or WN) and/or a conductive metallic carbide material (e.g., TiC, TaC, and/or WC). The metallic liner layer can be deposited by chemical vapor deposition or physical vapor deposition. A metallic fill material layer can be deposited over the metallic liner layer. The metallic fill material layer includes a metallic material having high electrical resistivity. For example, the metallic fill material layer can include copper, tungsten, titanium, tantalum, molybdenum, ruthenium, cobalt, or a combination thereof.

Excess portions of the metallic fill material layer and the metallic liner layer can be removed from above the horizontal plane including the top surface of the second dielectric isolation layer210. Each remaining portion of the metallic fill material layer comprises a second metallic fill material portion224. Each remaining portion of the metallic liner layer comprises a second metallic liner222. Each contiguous combination of a second metallic liner222and a second metallic fill material portion224constitutes a second electrically conductive line22(e.g., the other one of a bit line or word line). The second electrically conductive lines22laterally extend along the second horizontal direction hd2. and are laterally spaced apart along the first horizontal direction hd1. Alternatively, the second electrically conductive lines22may be formed first, followed by forming the second dielectric isolation layer210second electrically conductive lines22.

While in the prior embodiment the memory element15overlies the selector element13, embodiments are expressly contemplated herein in which the selector element13overlies a memory element15. In this case, the conductive plate stack14can overlie the memory element15and the selector element13.

Referring to all drawings and according to various embodiments of the present disclosure, a memory device is provided, which comprises: a first electrically conductive line12, a memory pillar structure (13,14,15,158) comprising a lower electrode plate132, a selector material plate134, an upper electrode plate136, a refractory metal-containing etch stop plate142, a ruthenium etch stop plate144, a conductive pillar146, and a memory element15overlying the first electrically conductive line12, and a second electrically conductive line22overlying the memory pillar structure (13,14,15,158).

In one embodiment, the refractory metal-containing etch stop plate142consists essentially of tantalum, tungsten, rhenium, niobium, molybdenum, intermetallic alloy thereof, or conductive metallic nitride thereof. In one embodiment, the conductive pillar146comprises, and/or consists essentially of, a material selected from an elemental metal, an intermetallic alloy, a conductive metallic nitride material, a conductive metallic carbide material, and a conductive carbon-based material. In one embodiment, the conductive pillar146consists essentially of tantalum nitride, undoped carbon or carbon doped with boron or nitrogen; the ruthenium etch stop plate144consists essentially of ruthenium; the refractory metal-containing etch stop plate142consists essentially of tantalum nitride, and the upper electrode plate136comprises undoped amorphous carbon or amorphous carbon doped with boron or nitrogen. In one embodiment, the conductive pillar has a thickness in a range from 20 nm to 50 nm, the ruthenium etch stop plate has a thickness in a range from 2 nm to 5 nm, the refractory metal-containing etch stop plate has a thickness in a range from 2 nm to 5 nm, and the upper electrode plate thickness ranges from 1 nm to 10 nm.

In one embodiment, the memory element15comprises a vertical magnetic tunnel junction150of a spin transfer torque (STT) magnetoresistive random access memory (MRAM) cell. The vertical magnetic tunnel junction150has a taper angle in a range from 1 degrees to 30 degrees with respective to a vertical direction.

In one embodiment, the selector material plate133comprises an ovonic threshold switch selector element. In one embodiment, the vertical magnetic tunnel junction150is narrower than the ovonic threshold switch selector element134.