THREE-DIMENSIONAL MEMORY DEVICE INCLUDING AIRGAP CONTAINING INSULATING LAYERS AND METHOD OF MAKING THE SAME

A three-dimensional memory device includes a vertical repetition of multiple instances of a unit layer stack. The unit layer stack includes, in order, an airgap-containing insulating layer, a first interfacial dielectric capping layer, a metal layer, and a second interfacial dielectric capping layer. Memory stack structures extend through the vertical repetition. Each of the memory stack structures includes a vertical semiconductor channel and a vertical stack of memory elements located at levels of the metal layers.

FIELD

The present disclosure relates generally to the field of semiconductor devices, and particularly to a three-dimensional memory device including airgap-containing insulating layers and methods of manufacturing the same.

BACKGROUND

SUMMARY

According to an aspect of the present disclosure, a three-dimensional memory device is provided, which comprises: a vertical repetition of multiple instances of a unit layer stack located over a substrate, wherein the unit layer stack comprises, in order, an airgap-containing insulating layer, a first interfacial dielectric capping layer, a metal layer, and a second interfacial dielectric capping layer; and memory stack structures extending through the vertical repetition, wherein each of the memory stack structures comprises a vertical semiconductor channel and a vertical stack of memory elements located at levels of the metal layers.

According to another aspect of the present disclosure, a method of forming a three-dimensional memory device is provided, which comprises: forming a vertical repetition of multiple instances of a unit layer stack located over a substrate, wherein the unit layer stack comprises, in order, a sacrificial material layer, a first interfacial dielectric capping layer, a metal layer, and a second interfacial dielectric capping layer; forming memory openings through the vertical repetition; forming memory opening fill structures in the memory openings, wherein each of the memory opening fill structures comprises a vertical semiconductor channel and a vertical stack of memory elements located at levels of the metal layers; and replacing instances of the sacrificial material layer within the vertical repetition with instances of an insulating layer.

DETAILED DESCRIPTION

As discussed above, the present disclosure is directed to a three-dimensional memory device including airgap-containing insulating layers and methods of manufacturing the same, the various aspects of which are described below. The embodiments of the disclosure can be employed to form various structures including a multilevel memory structure, non-limiting examples of which include semiconductor devices such as three-dimensional memory array devices comprising a plurality of NAND memory strings.

Generally, a semiconductor die, or a semiconductor package, can include a memory chip. Each semiconductor package contains one or more dies (for example one, two, or four). The die is the smallest unit that can independently execute commands or report status. Each die contains one or more planes (typically one or two). Identical, concurrent operations can take place on each plane, although with some restrictions. Each plane contains a number of blocks, which are the smallest unit that can be erased by in a single erase operation. Each block contains a number of pages, which are the smallest unit that can be programmed, i.e., a smallest unit on which a read operation can be performed.

Referring toFIG.1, an exemplary structure according to an embodiment of the present disclosure is illustrated, which can be employed, for example, to fabricate a device structure containing vertical NAND memory devices. The exemplary structure includes a substrate (9,10), which can be a semiconductor substrate. The substrate can include a substrate semiconductor layer9and an optional semiconductor material layer10. The substrate semiconductor layer9maybe a semiconductor wafer or a semiconductor material layer, and can include at least one elemental semiconductor material (e.g., single crystal silicon wafer or layer), at least one III-V compound semiconductor material, at least one II-VI compound semiconductor material, at least one organic semiconductor material, or other semiconductor materials known in the art. The substrate can have a major surface7, which can be, for example, a topmost surface of the substrate semiconductor layer9. The major surface7can be a semiconductor surface. In one embodiment, the major surface7can be a single crystalline semiconductor surface, such as a single crystalline semiconductor surface.

At least one semiconductor device700for a peripheral circuitry can be formed on a portion of the substrate semiconductor layer9. The at least one semiconductor device can include, for example, field effect transistors. For example, at least one shallow trench isolation structure720can be formed by etching portions of the substrate semiconductor layer9and depositing a dielectric material therein. A gate dielectric layer, at least one gate conductor layer, and a gate cap dielectric layer can be formed over the substrate semiconductor layer9, and can be subsequently patterned to form at least one gate structure (750,752,754,758), each of which can include a gate dielectric750, a gate electrode (752,754), and a gate cap dielectric758. The gate electrode (752,754) may include a stack of a first gate electrode portion752and a second gate electrode portion754. At least one gate spacer756can be formed around the at least one gate structure (750,752,754,758) by depositing and anisotropically etching a dielectric liner. Active regions730can be formed in upper portions of the substrate semiconductor layer9, for example, by introducing electrical dopants employing the at least one gate structure (750,752,754,758) as masking structures. Additional masks may be employed as needed. The active region730can include source regions and drain regions of field effect transistors. A first dielectric liner761and a second dielectric liner762can be optionally formed. Each of the first and second dielectric liners (761,762) can comprise a silicon oxide layer, a silicon nitride layer, and/or a dielectric metal oxide layer. As used herein, silicon oxide includes silicon dioxide as well as non-stoichiometric silicon oxides having more or less than two oxygen atoms for each silicon atoms. Silicon dioxide is preferred. In an illustrative example, the first dielectric liner761can be a silicon oxide layer, and the second dielectric liner762can be a silicon nitride layer. The least one semiconductor device for the peripheral circuitry can contain a driver circuit for memory devices to be subsequently formed, which can include at least one NAND device.

A dielectric material such as silicon oxide can be deposited over the at least one semiconductor device, and can be subsequently planarized to form a planarization dielectric layer770. In one embodiment the planarized top surface of the planarization dielectric layer770can be coplanar with a top surface of the dielectric liners (761,762). Subsequently, the planarization dielectric layer770and the dielectric liners (761,762) can be removed from an area to physically expose a top surface of the substrate semiconductor layer9. As used herein, a surface is “physically exposed” if the surface is in physical contact with vacuum, or a gas phase material (such as air).

The optional semiconductor material layer10, if present, can be formed on the top surface of the substrate semiconductor layer9prior to, or after, formation of the at least one semiconductor device700by deposition of a single crystalline semiconductor material, for example, by selective epitaxy. The deposited semiconductor material can be the same as, or can be different from, the semiconductor material of the substrate semiconductor layer9. The deposited semiconductor material can be any material that can be employed for the substrate semiconductor layer9as described above. The single crystalline semiconductor material of the semiconductor material layer10can be in epitaxial alignment with the single crystalline structure of the substrate semiconductor layer9. Portions of the deposited semiconductor material located above the top surface of the planarization dielectric layer170can be removed, for example, by chemical mechanical planarization (CMP). In this case, the semiconductor material layer10can have a top surface that is coplanar with the top surface of the planarization dielectric layer770.

The region (i.e., area) of the at least one semiconductor device700is herein referred to as a peripheral device region200. The region in which a memory array is subsequently formed is herein referred to as a memory array region100. A contact region300for subsequently forming stepped terraces of metal layers can be provided between the memory array region100and the peripheral device region200.

In one alternative embodiment, the peripheral device region200containing the at least one semiconductor device700for a peripheral circuitry may be located under the memory array region100in a CMOS under array configuration. In another alternative embodiment, the peripheral device region200may be located on a separate substrate which is subsequently bonded to the memory array region100.

Referring toFIG.2, a vertical repetition of multiple instances of a unit layer stack (31,40L,46,40U) can be formed located over the substrate (9,10). The unit layer stack (31,40L,46,40U) can comprise, in order either from bottom to top or from top to bottom, a sacrificial material layer31, a first interfacial dielectric capping layer40L, a metal layer46, and a second interfacial dielectric capping layer40U. The first interfacial dielectric capping layers40L and the second interfacial dielectric capping layers40U are herein collectively referred to as interfacial dielectric capping layers40.

Each sacrificial material layer31includes a material that can be subsequently removed selective to the material of the semiconductor material layer10, the interfacial dielectric capping layers40, and the dielectric material of a retro-stepped dielectric material portion to be subsequently formed. For example, the sacrificial material layers31may include, and/or may consist essentially of, silicon oxide, silicon nitride, organosilicate glass, or borosilicate glass. Organosilicate glass and borosilicate glass may be etched in dilute hydrofluoric acid at an etch rate that is at least 100 times, such as at least 1,000 times, the etch rate of undoped silicate glass in dilute hydrofluoric acid. Silicon nitride may be etched in hot phosphoric acid at an etch rate that is at least 10 times, such as at least 100 times, the etch rate of undoped silicate glass in hot phosphoric acid. The sacrificial material layers31may be deposited, for example, by chemical vapor deposition or ion beam deposition. For example, silicon nitride layers may be deposited by reactive ion beam deposition in which a nitrogen ion and/or noble gas ion (e.g., Ar or Kr) beam is directed onto a silicon sputtering target to deposit a silicon nitride layer over the substrate (9,10) which is positioned in the deposition chamber facing the target. Each of the sacrificial material layers31may have a thickness in a range from 10 nm to 60 nm, such as from 15 nm to 30 nm, although lesser and greater thicknesses may also be employed.

Each metal layer46includes an elemental metal or a metal alloy material. For example, the metal layers46may include, and/or may consist essentially of, a refractory metal such as molybdenum, niobium, tantalum, or tungsten, a transition metal having a high melting point such as ruthenium or cobalt, or a conductive metallic nitride material such as TiN, TaN, MoN or WN. In one embodiment, each metal layer46may comprise, and/or may consist essentially of, molybdenum. The metal layers46can be deposited by physical vapor deposition (e.g., ion beam deposition or sputtering), chemical vapor deposition or atomic layer deposition employing a molybdenum-containing precursor gas. For example, if the metal layers46comprise and/or consist essentially of molybdenum, then a non-reactive ion beam deposition process may be used to sputter molybdenum from a molybdenum sputtering target using a noble gas (e.g., argon or krypton) ion beam to deposit molybdenum layers46on the sacrificial material layers31. In one embodiment, each instance of the metal layer46may comprise molybdenum at an atomic percentage that is greater than 90%, such as from 95% to 100%. Each of the sacrificial material layers31may have a thickness in a range from 10 nm to 60 nm, such as from 15 nm to 30 nm, although lesser and greater thicknesses may also be employed.

The first interfacial dielectric capping layers40L and the second interfacial dielectric capping layers40U include a respective oxygen-free dielectric material that is different from the material of the sacrificial material layers31. In one embodiment, the first interfacial dielectric capping layers40L comprise, and/or consists essentially of, a first oxygen-free dielectric material, and the second interfacial dielectric capping layers40U comprise, and/or consist essentially of, a second oxygen-free dielectric material. In one embodiment, the first oxygen-free dielectric material and the second oxygen-free dielectric material may be oxygen-blocking dielectric barrier materials. In one embodiment, the first oxygen-free dielectric material may be selected from silicon carbide, silicon nitride, or silicon carbide nitride (i.e., silicon carbonitride), and the second oxygen-free dielectric material is selected from silicon carbide, silicon nitride, or silicon carbide nitride.

In one embodiment, the average thickness of instances of the first interfacial dielectric capping layer40L can be less than 20%, and/or can be in a range from 2% to 10%, of the average thickness of instances of the metal layer46, and the average thickness of instances of the second interfacial dielectric capping layer40U can be less than 20%, and/or can be in a range from 2% to 10%, of the average thickness of the instances of the metal layer46. In one embodiment, each of the first interfacial dielectric capping layers40L and the second interfacial dielectric capping layers40U may have a thickness in a range from 0.5 nm to 3 nm, such as from 1 nm to 2 nm, although lesser and greater thicknesses may also be employed.

The number of repetitions of the pairs of unit layer stack (31,40L,46,40U) can be in a range from 2 to 1,024, and typically from 8 to 256, although a greater number of repetitions can also be employed. The middle metal layers46function as gate electrodes (e.g., control gate electrodes/word lines. One or more top and bottom gate electrodes in the vertical repetition of the unit layer stack (31,40L,46,40U) may function as the select gate electrodes. In one embodiment, each sacrificial material layer31in the vertical repetition of the unit layer stack (31,40L,46,40U) can have a uniform thickness that is substantially invariant within each respective sacrificial material layer31.

Optionally, an insulating cap layer70can be formed over the vertical repetition of the unit layer stack (31,40L,46,40U). The insulating cap layer70includes a dielectric material that is different from the material of the sacrificial material layers31. For example, the insulating cap layer70may comprise undoped silicate glass (i.e., silicon oxide). The insulating cap layer70can be deposited, for example, by chemical vapor deposition or ion beam deposition. The insulating cap layer70can have a greater thickness than each of the sacrificial material layers31. For example, the insulating cap layer70may have a thickness in a range from 10 nm to 100 nm, such as from 30 nm to 50 nm, although lesser and greater thicknesses may also be employed.

Each metal layer46other than a topmost metal layer46within the vertical repetition of the unit layer stack (31,40L,46,40U) laterally extends farther than any overlying metal layer46within the vertical repetition of the unit layer stack (31,40L,46,40U) in the terrace region. The terrace region includes stepped surfaces of the vertical repetition of the unit layer stack (31,40L,46,40U) that continuously extend from a bottommost layer within the vertical repetition of the unit layer stack (31,40L,46,40U) to a topmost layer within the vertical repetition of the unit layer stack (31,40L,46,40U).

Each vertical step of the stepped surfaces can have the height of one or more instances of the unit layer stack (31,40L,46,40U). In one embodiment, each vertical step can have the height of a single pair of a single instance of the unit layer stack (31,40L,46,40U). In another embodiment, multiple “columns” of staircases can be formed along a first horizontal direction hd1such that each vertical step has the height of a plurality of instances of the unit layer stack (31,40L,46,40U), and the number of columns can be at least the number of the plurality of instances of the unit layer stack (31,40L,46,40U).

A retro-stepped dielectric material portion65(i.e., an insulating fill material portion) can be formed in the stepped cavity by deposition of a dielectric material therein. For example, a dielectric material such as silicon oxide can be deposited in the stepped cavity. Excess portions of the deposited dielectric material can be removed from above the top surface of the insulating cap layer70, for example, by chemical mechanical planarization (CMP). The remaining portion of the deposited dielectric material filling the stepped cavity constitutes the retro-stepped dielectric material portion65. As used herein, a “retro-stepped” element refers to an element that has stepped surfaces and a horizontal cross-sectional area that increases monotonically as a function of a vertical distance from a top surface of a substrate on which the element is present. In one embodiment, the retro-stepped dielectric material portion65may comprise undoped silicate glass.

Optionally, drain-select-level isolation structures72can be formed through the insulating cap layer70and a subset of the metal layers46located at drain select levels. The drain-select-level isolation structures72can be formed, for example, by forming drain-select-level isolation trenches and filling the drain-select-level isolation trenches with a dielectric material such as silicon oxide. Excess portions of the dielectric material can be removed from above the top surface of the insulating cap layer70.

Referring toFIGS.4A and4B, a lithographic material stack (not shown) including at least a photoresist layer can be formed over the insulating cap layer70and the retro-stepped dielectric material portion65, and can be lithographically patterned to form openings therein. The openings include a first set of openings formed over the memory array region100and a second set of openings formed over the contact region300. The pattern in the lithographic material stack can be transferred through the insulating cap layer70or the retro-stepped dielectric material portion65, and through the vertical repetition of the unit layer stack (31,40L,46,40U) by at least one anisotropic etch that employs the patterned lithographic material stack as an etch mask. Portions of the vertical repetition of the unit layer stack (31,40L,46,40U) underlying the openings in the patterned lithographic material stack are etched to form memory openings49and support openings19. As used herein, a “memory opening” refers to a structure in which memory elements, such as a memory stack structure, is subsequently formed. As used herein, a “support opening” refers to a structure in which a support structure (such as a support pillar structure) that mechanically supports other elements is subsequently formed. The memory openings49are formed through the insulating cap layer70and the entirety of the vertical repetition of the unit layer stack (31,40L,46,40U) in the memory array region100. The support openings19are formed through the retro-stepped dielectric material portion65and the portion of the vertical repetition of the unit layer stack (31,40L,46,40U) that underlie the stepped surfaces in the contact region300.

The memory openings49extend through the entirety of the vertical repetition of the unit layer stack (31,40L,46,40U). The support openings19extend through a subset of layers within the vertical repetition of the unit layer stack (31,40L,46,40U). The chemistry of the anisotropic etch process employed to etch through the materials of the vertical repetition of the unit layer stack (31,40L,46,40U) can alternate to optimize etching of the first and second materials in the vertical repetition of the unit layer stack (31,40L,46,40U). The anisotropic etch can be, for example, a series of reactive ion etches. The sidewalls of the memory openings49and the support openings19can be substantially vertical, or can be tapered.

In an illustrative example, if the sacrificial material layers31include silicon oxide and if the metal layers46include molybdenum, the anisotropic etch process may employ an etch chemistry including an etchant including SF6, CF4, NF3, Cl2, CCl4, CCl2F2, CF3Cl2, and/or HBr and optionally an oxidant (e.g., O2). For example, molybdenum may be reactively ion etched using CCl4/O2or CF4/O2, or plasma etched in NF3, or ion beam etched with argon or other noble gas. In another illustrative example, if the sacrificial material layers31include silicon nitride and if the metal layers46include molybdenum, the anisotropic etch process may employ an etch chemistry including an etchant including CxFyHz, CF4, NF3, Cl2, CCl4, CCl2F2, CF3Cl2, and/or HBr and optionally an oxidant of O2. In this case, the etch byproduct may include MoOx, MoFx, MoClx, MoOClx, CNF, FCN, CFx, SiFy, SiCly, COx, and/or COFx. In such etch chemistries, high vapor pressure etch products, such as MoF6may be formed. Use of Cl2may prevent or reduce undercutting. Avoiding formation of low-vapor-pressure molybdenum products, such as MoCl6can prevent reduction of the etch rate. Increasing the partial pressure of O2can increase the volatility of etch byproducts, and can prevent or reduce carbonation of molybdenum surfaces. If the metal layers46include a different metal, the etch chemistry may be accordingly adjusted to optimize the etch profile and the etch rate of the vertical repetition of the unit layer stack (31,40L,46,40U). The patterned lithographic material stack can be subsequently removed, for example, by ashing.

The memory openings49and the support openings19can extend from the top surface of the vertical repetition of the unit layer stack (31,40L,46,40U) to at least the horizontal plane including the topmost surface of the semiconductor material layer10. In one embodiment, an overetch into the semiconductor material layer10may be optionally performed after the top surface of the semiconductor material layer10is physically exposed at a bottom of each memory opening49and each support opening19. The overetch may be performed prior to, or after, removal of the lithographic material stack. In other words, the recessed surfaces of the semiconductor material layer10may be vertically offset from the un-recessed top surfaces of the semiconductor material layer10by a recess depth. The recess depth can be, for example, in a range from 1 nm to 50 nm, although lesser and greater recess depths can also be employed. The overetch is optional, and may be omitted. If the overetch is not performed, the bottom surfaces of the memory openings49and the support openings19can be coplanar with the topmost surface of the semiconductor material layer10.

Each of the memory openings49and the support openings19may include a sidewall (or a plurality of sidewalls) that extends substantially perpendicular to the topmost surface of the substrate. A two-dimensional array of memory openings49can be formed in the memory array region100. A two-dimensional array of support openings19can be formed in the contact region300. The substrate semiconductor layer9and the semiconductor material layer10collectively constitutes a substrate (9,10), which can be a semiconductor substrate. Alternatively, the semiconductor material layer10may be omitted, and the memory openings49and the support openings19can be extend to a top surface of the substrate semiconductor layer9.

FIGS.5A-5Hillustrate structural changes in a memory opening49, which is one of the memory openings49in the exemplary structure ofFIGS.4A and4B. The same structural change occurs simultaneously in each of the other memory openings49and in each support opening19.

Referring toFIG.5A, a memory opening49in the exemplary device structure ofFIGS.4A and4Bis illustrated. The memory opening49extends through the insulating cap layer70, the vertical repetition of the unit layer stack (31,40L,46,40U), and optionally into an upper portion of the semiconductor material layer10. At this processing step, each support opening19can extend through the retro-stepped dielectric material portion65, a subset of layers in the vertical repetition of the unit layer stack (31,40L,46,40U), and optionally through the upper portion of the semiconductor material layer10. The recess depth of the bottom surface of each memory opening with respect to the top surface of the semiconductor material layer10can be in a range from 0 nm to 30 nm, although greater recess depths can also be employed. Optionally, the metal layers46can be laterally recessed partially to form lateral recesses (not shown), for example, by an isotropic etch.

Referring toFIG.5B, a stack of layers including at least one blocking dielectric layer (501,502), a memory material layer54, and a dielectric material liner56can be sequentially deposited in the memory openings49by a respective conformal deposition process.

The at least one blocking dielectric layer (501,502) can include a single dielectric material layer or a stack of a plurality of dielectric material layers. The at least one blocking dielectric layer (501,502) can be formed employing a conformal deposition process. In one embodiment, the blocking dielectric layer (501,502) can include layer stack of a first blocking dielectric layer501and a second blocking dielectric layer502that is formed on the first blocking dielectric layer501.

In one embodiment, the first blocking dielectric layer501may comprise a dielectric metal oxide layer consisting essentially of a dielectric metal oxide. As used herein, a dielectric metal oxide refers to a dielectric material that includes at least one metallic element and at least oxygen. The dielectric metal oxide may consist essentially of the at least one metallic element and oxygen, or may consist essentially of the at least one metallic element, oxygen, and at least one non-metallic element such as nitrogen. In one embodiment, the first blocking dielectric layer501can include a dielectric metal oxide having a dielectric constant greater than 7.9, i.e., having a dielectric constant greater than the dielectric constant of silicon nitride.

Non-limiting examples of dielectric metal oxides include aluminum oxide (Al2O3), hafnium oxide (HfO2), zirconium oxide (ZrO2), lanthanum oxide (LaO2), yttrium oxide (Y2O3), tantalum oxide (Ta2O5), silicates thereof, nitrogen-doped compounds thereof, alloys thereof, and stacks thereof. The dielectric metal oxide layer can be deposited, for example, by chemical vapor deposition (CVD), atomic layer deposition (ALD), pulsed laser deposition (PLD), liquid source misted chemical deposition, or a combination thereof. The thickness of the first blocking dielectric layer501can be in a range from 1 nm to 10 nm, although lesser and greater thicknesses can also be employed. The first blocking dielectric layer501can function as a dielectric material portion that blocks leakage of stored electrical charges to control gate electrodes. In one embodiment, the first blocking dielectric layer501includes aluminum oxide. In one embodiment, the first blocking dielectric layer501can include multiple dielectric metal oxide layers having different material compositions.

The second blocking dielectric layer502can include a dielectric semiconductor compound such as silicon oxide, silicon oxynitride or a combination thereof. In one embodiment, the second blocking dielectric layer502can include silicon oxide. In this case, the second blocking dielectric layer502can be formed by a conformal deposition method such as low pressure chemical vapor deposition, atomic layer deposition, or a combination thereof. The thickness of the second blocking dielectric layer502can be in a range from 1 nm to 10 nm, although lesser and greater thicknesses can also be employed.

Subsequently, the memory material layer54can be deposited as a continuous material layer by a conformal deposition process such as a chemical vapor deposition process or an atomic layer deposition process. The memory material layer54includes a memory material, i.e., a material that can store data by selecting a state of the material. For example, the memory material layer54may include a charge storage material such as silicon nitride, polysilicon, or a metallic material, a ferroelectric material that can store information in the form of a ferroelectric polarization direction, or any other memory material that can store date by altering its electrical resistivity.

The memory material layer54can be formed as a single memory material layer of homogeneous composition, or can include a stack of multiple memory material layers. In one embodiment, the memory material layer54may comprise an insulating charge trapping material, such as one or more silicon nitride segments. The memory material layer54can be formed, for example, by chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), or any suitable deposition technique for storing electrical charges therein. The thickness of the memory material layer54can be in a range from 2 nm to 20 nm, although lesser and greater thicknesses can also be employed.

Referring toFIG.5C, an optional sacrificial cover material layer601may be deposited over the dielectric material liner56. The optional sacrificial cover material layer601includes a sacrificial material that can be subsequently removed selective to the material of the dielectric material liner56. In one embodiment, the sacrificial cover material layer601can include a semiconductor material such as amorphous silicon, or may include a carbon-based material such as amorphous carbon or diamond-like carbon (DLC). The sacrificial cover material layer601can be formed by a conformal deposition method such as low pressure chemical vapor deposition (LPCVD). The thickness of the sacrificial cover material layer601can be in a range from 2 nm to 10 nm, although lesser and greater thicknesses can also be employed. A memory cavity49′ is formed in the volume of each memory opening49that is not filled with the deposited material layers (501,502,54,56,601).

Referring toFIG.5D, the optional sacrificial cover material layer601, the dielectric material liner56, the memory material layer54, and the at least one blocking dielectric layer (501,502) overlying the insulating cap layer70are sequentially anisotropically etched employing at least one anisotropic etch process. The portions of the sacrificial cover material layer601, the dielectric material liner56, the memory material layer54, and the at least one blocking dielectric layer (501,502) located above the top surface of the insulating cap layer70can be removed by the at least one anisotropic etch process. Further, the horizontal portions of the sacrificial cover material layer601, the dielectric material liner56, the memory material layer54, and the at least one blocking dielectric layer (501,502) at a bottom of each memory cavity49′ can be removed to form openings in remaining portions thereof. Each of the sacrificial cover material layer601, the dielectric material liner56, the memory material layer54, and the at least one blocking dielectric layer (501,502) can be etched by a respective anisotropic etch process employing a respective etch chemistry, which may, or may not, be the same for the various material layers.

Each remaining portion of the sacrificial cover material layer601can have a tubular configuration. The memory material layer54can comprise a charge trapping material, a floating gate material, a ferroelectric material, or a resistive memory material that can provide at least two different levels of resistivity (such as a phase change material), or any other memory material that can store information by a change in state. In one embodiment, each memory material layer54can include a vertical stack of charge storage regions that store electrical charges upon programming. In one embodiment, the memory material layer54can be a memory material layer in which each portion adjacent to the metal layers46constitutes a charge storage region.

A surface of the semiconductor material layer10can be physically exposed underneath the opening through the sacrificial cover material layer601, the dielectric material liner56, the memory material layer54, and the at least one blocking dielectric layer (501,502). Optionally, the physically exposed semiconductor surface at the bottom of each memory cavity49′ can be vertically recessed so that the recessed semiconductor surface underneath the memory cavity49′ is vertically offset from the topmost surface of the semiconductor material layer10by a recess distance. A dielectric material liner56is located over the memory material layer54. A set of at least one blocking dielectric layer (501,502), a memory material layer54, and a dielectric material liner56in a memory opening49constitutes a memory film50, which includes a plurality of charge storage regions (as embodied as the memory material layer54) that are insulated from surrounding materials by the at least one blocking dielectric layer (501,502) and the dielectric material liner56. In one embodiment, the sacrificial cover material layer601, the dielectric material liner56, the memory material layer54, and the at least one blocking dielectric layer (501,502) can have vertically coincident sidewalls. The sacrificial cover material layer601can be subsequently removed selective to the material of the dielectric material liner56. In case the sacrificial cover material layer601includes a semiconductor material, a wet etch process employing hot trimethyl-2 hydroxyethyl ammonium hydroxide (“hot TMY”) or tetramethyl ammonium hydroxide (TMAH) can be performed to remove the sacrificial cover material layer601. Alternatively, the sacrificial cover material layer601may be retained in the final device if it comprises a semiconductor material.

Referring toFIG.5E, a semiconductor channel layer60L can be deposited directly on the semiconductor surface of the semiconductor material layer10, and directly on the dielectric material liner56. The semiconductor channel layer60L includes a semiconductor material such as at least one elemental semiconductor material, at least one III-V compound semiconductor material, at least one II-VI compound semiconductor material, at least one organic semiconductor material, or other semiconductor materials known in the art. In one embodiment, the semiconductor channel layer60L includes amorphous silicon or polysilicon. The semiconductor channel layer60L can have a doping of a first conductivity type, which is the same as the conductivity type of the semiconductor material layer10. The semiconductor channel layer60L can be formed by a conformal deposition method such as low pressure chemical vapor deposition (LPCVD). The thickness of the semiconductor channel layer60L can be in a range from 2 nm to 10 nm, although lesser and greater thicknesses can also be employed. The semiconductor channel layer60L may partially fill the memory cavity49′ in each memory opening, or may fully fill the cavity in each memory opening.

Referring toFIG.5F, in case the memory cavity49′ in each memory opening is not completely filled by the semiconductor channel layer60L, a dielectric core layer62L can be deposited in the memory cavity49′ to fill any remaining portion of the memory cavity49′ within each memory opening. The dielectric core layer62L includes a dielectric material such as silicon oxide or organosilicate glass. The dielectric core layer62L can be deposited by a conformal deposition method such as low pressure chemical vapor deposition (LPCVD), or by a self-planarizing deposition process such as spin coating.

Referring toFIG.5G, the horizontal portion of the dielectric core layer62L can be removed, for example, by a recess etch process such that each remaining portions of the dielectric core layer62L is located within a respective memory opening49and has a respective top surface below the horizontal plane including the top surface of the insulating cap layer70. Each remaining portion of the dielectric core layer62L constitutes a dielectric core62.

Referring toFIG.5H, a doped semiconductor material having a doping of a second conductivity type can be deposited within each recessed region above the dielectric cores62. The deposited semiconductor material can have a doping of a second conductivity type that is the opposite of the first conductivity type. For example, if the first conductivity type is p-type, the second conductivity type is n-type, and vice versa. The dopant concentration in the deposited semiconductor material can be in a range from 5.0×1018/cm3to 2.0×1021/cm3, although lesser and greater dopant concentrations can also be employed. The doped semiconductor material can be, for example, doped polysilicon.

Excess portions of the deposited semiconductor material having a doping of the second conductivity type and a horizontal portion of the semiconductor channel layer60L can be removed from above the horizontal plane including the top surface of the insulating cap layer70, for example, by chemical mechanical planarization (CMP) or a recess etch process. Each remaining portion of the doped semiconductor material having a doping of the second conductivity type constitutes a drain region63. Each remaining portion of the semiconductor channel layer60L (which has a doping of the first conductivity type) constitutes a vertical semiconductor channel60. The vertical semiconductor channel60is formed directly on the dielectric material liner56.

A dielectric material liner56is surrounded by a memory material layer54, and laterally surrounds a portion of the vertical semiconductor channel60. Each adjoining set of at least one blocking dielectric layer (501,502), a memory material layer54, and a dielectric material liner56collectively constitute a memory film50, which can store electrical charges or electrical polarization with a macroscopic retention time. In some embodiments, a at least one blocking dielectric layer (501,502) may not be present in the memory film50at this step, and a backside blocking dielectric layer may be subsequently formed after formation of backside recesses. As used herein, a macroscopic retention time refers to a retention time suitable for operation of a memory device as a permanent memory device such as a retention time in excess of 24 hours.

Each combination of a memory film50and a vertical semiconductor channel60within a memory opening49constitutes a memory stack structure55. The memory stack structure55is a combination of a semiconductor channel, a dielectric material liner, a plurality of memory elements as embodied as portions of the memory material layer54, and an optional at least one blocking dielectric layer (501,502). An entire set of material portions that fills a memory opening49is herein referred to as a memory opening fill structure58. An entire set of material portions that fills a support opening19constitutes a support pillar structure.

Generally, a memory opening fill structure58can be formed in each memory opening49. The memory opening fill structure58comprises an optional at least one blocking dielectric layer (501,502), a memory material layer54, an optional dielectric material liner56, and a vertical semiconductor channel60. A dielectric material liner56may laterally surround the vertical semiconductor channel60. The memory material layer54can laterally surround the dielectric material liner56.

In case a at least one blocking dielectric layer (501,502) is present in each memory opening fill structure58, the blocking dielectric layer501may be formed on a sidewall of a memory opening49, and the vertical stack of memory elements (which may comprise portions of the memory material layer54) may be formed on the at least one blocking dielectric layer (501,502). In one embodiment, the vertical stack of memory elements comprises portions of a charge storage layer (e.g., the memory material layer54) located at the levels of the metal layers46. In case a dielectric material liner56is present in each memory opening fill structure58, the dielectric material liner56may be formed on the vertical stack of memory elements. In one embodiment, the dielectric material liner56may comprise a tunneling dielectric layer. In this case, the vertical semiconductor channel60can be formed on the tunneling dielectric layer. The at least one blocking dielectric layer (501,502) laterally surrounds the charge storage layer and the tunneling dielectric layer can be located between the charge storage layer and the vertical semiconductor channel60. A vertical NAND string can be formed through each memory opening upon formation of the memory opening fill structures58.

Referring toFIG.6, the exemplary structure is illustrated after formation of memory opening fill structures58and support pillar structure20within the memory openings49and the support openings19, respectively. An instance of a memory opening fill structure58can be formed within each memory opening49of the structure ofFIGS.4A and4B. An instance of the support pillar structure20can be formed within each support opening19of the structure ofFIGS.4A and4B.

Each memory stack structure55includes a vertical semiconductor channel60and a memory film50. The memory film50may comprise a dielectric material liner56laterally surrounding the vertical semiconductor channel60, a vertical stack of charge storage regions (comprising portions of the memory material layer54located at the levels of the metal layers46) laterally surrounding the dielectric material liner56, and an optional at least one blocking dielectric layer (501,502). While the present disclosure is described employing the illustrated configuration for the memory stack structure, the methods of the present disclosure can be applied to alternative memory stack structures including different layer stacks or structures for the memory film50and/or for the vertical semiconductor channel60.

Referring toFIGS.7A and7B, a contact-level dielectric layer73can be formed over the vertical repetition of the unit layer stack (31,40L,46,40U), and over the memory opening fill structures58and the support pillar structures20. The contact-level dielectric layer73includes a dielectric material that is different from the dielectric material of the metal layers46. For example, the contact-level dielectric layer73can include silicon oxide. The contact-level dielectric layer73can have a thickness in a range from 50 nm to 500 nm, although lesser and greater thicknesses can also be employed.

A photoresist layer (not shown) can be applied over the contact-level dielectric layer73, and is lithographically patterned to form openings in areas between clusters of memory stack structures55. The pattern in the photoresist layer can be transferred through the contact-level dielectric layer73, the vertical repetition of the unit layer stack (31,40L,46,40U) and/or the retro-stepped dielectric material portion65employing an anisotropic etch to form backside trenches79, which vertically extend from the top surface of the contact-level dielectric layer73at least to the top surface of the substrate (9,10), and laterally extend through the memory array region100and the contact region300.

In one embodiment, the backside trenches79can laterally extend along a first horizontal direction (e.g., word line direction) hd1and can be laterally spaced apart among one another along a second horizontal direction (e.g., bit line direction) hd2that is perpendicular to the first horizontal direction hd1. The memory stack structures55can be arranged in rows that extend along the first horizontal direction hd1. The drain-select-level isolation structures72can laterally extend along the first horizontal direction hd1. Each backside trench79can have a uniform width that is invariant along the lengthwise direction (i.e., along the first horizontal direction hd1). Each drain-select-level isolation structure72can have a uniform vertical cross-sectional profile along vertical planes that are perpendicular to the first horizontal direction hd1that is invariant with translation along the first horizontal direction hd1. Multiple rows of memory stack structures55can be located between a neighboring pair of a backside trench79and a drain-select-level isolation structure72, or between a neighboring pair of drain-select-level isolation structures72. In one embodiment, the backside trenches79can include a source contact opening in which a source contact via structure can be subsequently formed. The photoresist layer can be removed, for example, by ashing.

A source region61can be formed at a surface portion of the semiconductor material layer10under each backside trench79by implantation of electrical dopants into physically exposed surface portions of the semiconductor material layer10. An upper portion of the semiconductor material layer10that extends between the source region61and the bottom portions of the vertical semiconductor channels60constitutes a horizontal semiconductor channel59for a plurality of field effect transistors. The horizontal semiconductor channel59is connected to multiple vertical semiconductor channels60. The horizontal semiconductor channel59contacts the source region61and a plurality of vertical semiconductor channels60.

Referring toFIGS.8A and8B, an etchant that selectively etches the material of the sacrificial material layers31selective to the materials of the metal layers46and the interfacial dielectric capping layers40can be introduced into the backside trenches79, for example, employing an etch process. Backside recesses33are formed in volumes from which the instances of the sacrificial material layer31are removed selective to the instances of the first interfacial dielectric capping layer40L, the metal layer46, and the second interfacial dielectric capping layer40U. The removal of the material of the sacrificial material layers31can be selective to the material of the retro-stepped dielectric material portion65, to the semiconductor material of the semiconductor material layer10, and optionally to the material of the outermost layer of the memory films50. In one embodiment, the removal of the material of the sacrificial material layers31can be selective to the material of the first blocking dielectric layer501. In one embodiment, the sacrificial material layers31may include silicon nitride, organosilicate glass, or borosilicate glass, and the retro-stepped dielectric material portion65can include undoped silicate glass.

The etch process that removes the material of the sacrificial material layers31selective to the metal layers46, the interfacial dielectric capping layers40, and the outermost layers of the memory films50can be a wet etch process employing a wet etch solution, or can be a gas phase (dry) etch process in which the etchant is introduced in a vapor phase into the backside trenches79. For example, if the sacrificial material layers31comprise silicon nitride, the etch process can be a wet etch process in which the exemplary structure is immersed within a wet etch tank including phosphoric acid, which etches silicon nitride selective to silicon oxide, silicon, and various other materials employed in the art. If the sacrificial material layers31comprise organosilicate glass or borosilicate glass, the etch process can be a wet etch process in which the exemplary structure is immersed within a wet etch tank including dilute hydrofluoric acid, which etches organosilicate glass or borosilicate glass at an etch rate that is at least 100 times higher than the etch rate of undoped silicate glass. The duration of the etch process and the dilution of the hydrofluoric acid can be controlled to minimize collateral etching of undoped silicate glass. The support pillar structure20, the retro-stepped dielectric material portion65, and the memory opening fill structures58provide structural support while the backside recesses33are present within volumes previously occupied by the metal layers46.

Each backside recess33can be a laterally extending cavity having a lateral dimension that is greater than the vertical extent of the cavity. In other words, the lateral dimension of each backside recess33can be greater than the height of the backside recess33. A plurality of backside recesses33can be formed in the volumes from which the sacrificial material layers31are removed. The memory openings in which the memory opening fill structures58are formed are herein referred to as front side openings or front side cavities in contrast with the backside recesses33. In one embodiment, the memory array region100comprises an array of monolithic three-dimensional NAND strings having a plurality of device levels disposed above the substrate (9,10). In this case, each backside recess33provides vertical spacing between neighboring pairs of word lines46of the array of three-dimensional NAND strings.

Each of the plurality of backside recesses33can extend substantially parallel to the top surface of the substrate (9,10). A backside recess33can be vertically bounded by a top surface of an underlying second interfacial dielectric capping layer40U and a bottom surface of an overlying first interfacial dielectric capping layer40L. In one embodiment, each backside recess33can have a uniform height throughout.

Referring toFIGS.9A and9B, an airgap-containing insulating layer32can be in each of the backside recesses33by anisotropically depositing a dielectric material and anisotropically etching portions of the deposited dielectric material from inside the backside trenches79and from above the contact-level dielectric layer73. In one embodiment, the dielectric material may comprise silicon oxide.

According to an aspect of the present disclosure, the anisotropic nature of the deposition process that deposits the silicon oxide dielectric material result formation of encapsulated airgaps32A that are enclosed by a respective solid-phase dielectric material portion32S, such as a silicon oxide portion. The combination of an encapsulated airgap32A and a solid-phase dielectric material portion32S that is formed within each backside recess33constitutes an insulating layer32, which has an effective dielectric constant that is less than the dielectric constant of the solid-phase dielectric material portions32S. In one embodiment, the anisotropic etch process can be performed such that sidewalls of the airgap-containing insulating layers32(i.e., sidewalls of the solid-phase dielectric material portion32S) that are physically exposed to the backside trenches79are vertically coincident with overlying or underlying sidewalls of the metal layers46that are physically exposed to the same backside trench79.

Generally, instances of the sacrificial material layer31within the vertical repetition of instances of the unit layer stack (31,40L,46,40U) as formed at the processing steps ofFIG.2are replaced with instances of an insulating layer, which may be instances of an airgap-containing insulating layer32. In this case, each instance of the insulating layer comprises an instance of an airgap-containing insulating layer32, which comprises a dielectric material portion (such as a solid-phase dielectric material portion32S) encapsulating an encapsulated airgap32A therein. In one embodiment, the instances of the insulating layer (such as the airgap-containing insulating layer32) are formed on outer sidewalls of the at least one blocking dielectric layer (501,502) of each of the memory films50.

A vertical repetition of instances of a modified unit layer stack is provided. The modified unit layer stack includes, in order from bottom to top or from top to bottom, an insulating layer (such as an airgap-containing insulating layer32), a first interfacial dielectric capping layer40L, a metal layer46, and a second interfacial dielectric capping layer40U. In one embodiment, memory openings49vertically extend through the vertical repetition, and memory opening fill structures58are located within the respective memory openings49. Each of the memory opening fill structures58comprises a respective set of at least one blocking dielectric layer (501,502) vertically extending through the vertical repetition (32,40L,46,40U). In one embodiment, each of the airgap-containing insulating layers32contacts a respective segment of an outer sidewall of each set of at least one blocking dielectric layer (501,502).

In one embodiment, each vertical repetition of the unit layer stack (32,40L,46,40U) can be located between a respective neighboring pair of backside trenches79that laterally extend along a first horizontal direction hd1. A plurality of memory opening fill structures58can vertically extend through a vertical repetition of the unit layer stack (32,40L,46,40U) located between a respective neighboring pair of backside trenches79. Each of the encapsulated airgaps32A within the airgap-containing insulating layers32in the vertical repetition of the unit layer stack (32,40L,46,40U) laterally surrounds each of the memory opening fill structures58vertically extending through the vertical repetition of the unit layer stack (32,40L,46,40U). In other words, each encapsulated airgaps32A may continuously extend laterally such that each encapsulated airgap32A laterally surrounds each memory opening fill structure58that extends through a same vertical repetition of the unit layer stack (32,40L,46,40U) that is located between a pair of backside trenches79.

Referring toFIG.10, an insulating material layer can be formed in the backside trenches79and over the contact-level dielectric layer73by a conformal deposition process. Exemplary conformal deposition processes include, but are not limited to, chemical vapor deposition and atomic layer deposition. The insulating material layer includes an insulating material such as silicon oxide, silicon nitride, a dielectric metal oxide, an organosilicate glass, or a combination thereof. In one embodiment, the insulating material layer can include silicon oxide. The insulating material layer can be formed, for example, by low pressure chemical vapor deposition (LPCVD) or atomic layer deposition (ALD). The thickness of the insulating material layer can be in a range from 1.5 nm to 60 nm, although lesser and greater thicknesses can also be employed.

An anisotropic etch is performed to remove horizontal portions of the insulating material layer from above the contact-level dielectric layer73and at the bottom of each backside trench79. Each remaining portion of the insulating material layer constitutes an insulating spacer74. A backside cavity is present within a volume surrounded by each insulating spacer74. A top surface of the semiconductor material layer10can be physically exposed at the bottom of each backside trench79.

A backside contact via structure76can be formed within each backside cavity. Each contact via structure76can fill a respective cavity. The contact via structures76can be formed by depositing at least one conductive material in the remaining unfilled volume (i.e., the backside cavity) of the backside trench79. For example, the at least one conductive material can include a conductive liner76A and a conductive fill material portion76B. The conductive liner76A can include a conductive metallic liner such as TiN, TaN, WN, TiC, TaC, WC, an alloy thereof, or a stack thereof. The thickness of the conductive liner76A can be in a range from 3 nm to 30 nm, although lesser and greater thicknesses can also be employed. The conductive fill material portion76B can include a metal or a metallic alloy. For example, the conductive fill material portion76B can include W, Cu, Al, Co, Ru, Ni, an alloy thereof, or a stack thereof.

The at least one conductive material can be planarized employing the contact-level dielectric layer73overlying the vertical repetition of instances of the unit layer stack (32,40L,46,40U) as a stopping layer. If chemical mechanical planarization (CMP) process is employed, the contact-level dielectric layer73can be employed as a CMP stopping layer. Each remaining continuous portion of the at least one conductive material in the backside trenches79constitutes a backside contact via structure76.

The backside contact via structure76extends through the vertical repetition of instances of the unit layer stack (32,40L,46,40U), and contacts a top surface of the source region61. If an airgap-containing insulating layer32is employed, the backside contact via structure76can contact a sidewall of the airgap-containing insulating layer32.

Referring toFIGS.11A and11B, additional contact via structures (88,86,8P) can be formed through the contact-level dielectric layer73, and optionally through the retro-stepped dielectric material portion65. For example, drain contact via structures88can be formed through the contact-level dielectric layer73on each drain region63. Word line contact via structures86can be formed on the metal layers46through the contact-level dielectric layer73, and through the retro-stepped dielectric material portion65. Peripheral device contact via structures8P can be formed through the retro-stepped dielectric material portion65directly on respective nodes of the peripheral devices.

Alternatively, the above described insulating material layer can be formed in the backside trenches79to completely fill the entire volume of a backside trench79and may consist essentially of at least one dielectric material. In this alternative embodiment, the source region61and the backside trench via structure76may be omitted, and a horizontal source line (e.g., direct strap contact) may contact an side of the lower portion of the semiconductor channel60.

Referring toFIG.12, an alternative configuration of the exemplary structure according to an embodiment of the present disclosure is illustrated, which can be derived from the exemplary structure illustrated inFIGS.8A and8Bby sequentially etching physically exposed portions of at least one blocking dielectric layer (501,502) and a memory material layer54within each memory film50. For example, a first isotropic etch process that etches the material of the first blocking dielectric layers501can be performed to isotropically etch physically exposed portions of the first blocking dielectric layers501, a second isotropic etch process that etches the material of the second blocking dielectric layers502can be performed to isotropically etch physically exposed portions of the second blocking dielectric layers502, and a third isotropic etch process that etches the material of the memory material layers54can be performed to isotropically etch physically exposed portions of the memory material layers54. In one embodiment, if the first blocking dielectric layers501comprise aluminum oxide, the first isotropic etch process may comprise a wet etch process employing a mixture of phosphoric acid, nitric acid, and acetic acid. If the second blocking dielectric layers502comprise silicon oxide, the second isotropic etch process may comprise a wet etch process employing dilute hydrofluoric acid. If the memory material layers54comprise silicon nitride, the third isotropic etch process may comprise a wet etch process employing hot phosphoric acid.

In the alternative configuration of the exemplary structure, physically exposed portions of the at least one blocking dielectric layer (501,502) within each of the memory films50can be removed around the backside recesses33. Subsequently, physically exposed portions of the memory material layer54within each of the memory films50can be removed around the backside recesses33. Remaining portions of the at least one blocking dielectric layer (501,502) and a memory material layer54comprise a vertical stack of first discrete blocking dielectric material portions that are remaining portions of the first blocking dielectric layer501, a vertical stack of second discrete blocking dielectric material portions that are remaining portions of the second blocking dielectric layer502, and a vertical stack of discrete memory material portions that are remaining portions of the memory material layer54. In one embodiment, each discrete element within the vertical stack of first discrete blocking dielectric material portions, the vertical stack of second discrete blocking dielectric material portions, and the vertical stack of discrete memory material portions may have a tubular configuration, and may comprise at least one concave annular surface, such as a pair of concave annular surfaces, that is physically exposed to a respective one of the backside recesses33. Each vertical stack of discrete memory material portions comprises a vertical stack of vertically separated memory elements within a respective one of the memory films50.

In one embodiment, the discrete memory material portions comprise a charge storage material that can store electrical charge therein. The charge storage material may comprise a dielectric material (e.g., silicon nitride regions) or a conductive material (e.g., metal, metal alloy or heavily doped polysilicon floating gates).

Referring toFIG.13, the processing steps ofFIGS.9A and9Bcan be performed to form the airgap-containing insulating layer32within each of the backside recesses33. Instances of the airgap-containing insulating layer32can be formed directly on horizontal surfaces of the discrete memory elements to vertically separate and electrically isolate the memory elements from each other. In one embodiment, each vertical stack of memory elements comprises a vertical stack of discrete charge storage material portions that can store electrical charge therein. In one embodiment, at least one discrete charge storage material portion within the vertical stack of discrete charge storage material portions comprises: an upper concave surface segment contacting a convex surface segment of a first instance of the airgap-containing insulating layer32; and a lower concave surface segment contacting a convex surface segment of a second instance of the airgap-containing insulating layer32.

In one embodiment, at least one discrete charge storage material portion within the vertical stack of discrete charge storage material portions contacts an inner sidewall of a respective blocking dielectric material portion (which may be a patterned portion of the second blocking dielectric layer502); and the blocking dielectric material portion contacts a surface segment of a first instance of the airgap-containing insulating layer32and a surface segment of a second instance of the airgap-containing insulating layer32. The airgap-containing insulating layers32may contact a vertical sidewall of the liner (e.g., tunneling dielectric)56.

Referring toFIG.14, the processing steps ofFIGS.10and11can be performed to form various contact via structures (76,88,86,8P).

Referring to all drawings and according to various embodiments of the present disclosure, a three-dimensional memory device is provided, which comprises: a vertical repetition of multiple instances of a unit layer stack comprising, in order, an airgap-containing insulating layer32, a first interfacial dielectric capping layer40L, a metal layer46, and a second interfacial dielectric capping layer40U; and memory stack structures55extending through the vertical repetition (32,40L,46,40U), wherein each of the memory stack structures55comprises a vertical semiconductor channel60and a vertical stack of memory elements located at levels of the metal layers46.

In one embodiment, each of the airgap-containing insulating layers32comprises a dielectric material portion (such as a solid-phase dielectric material portion32S) encapsulating a respective encapsulated airgap32A.

In one embodiment the three-dimensional memory device comprises a pair of backside trench fill structures (74,76) laterally extending along a first horizontal direction hd1and contacting sidewalls of the vertical repetition (32,40L,46,40U), wherein each of the memory opening fill structures58is located between the pair of backside trench fill structures (74,76).

In one embodiment, each of the encapsulated airgaps32A laterally surrounds each of the memory opening fill structures58and is located between the pair of backside trench fill structures (74,76).

In one embodiment, the first interfacial dielectric capping layer40L comprises a first oxygen-free dielectric material; and the second interfacial dielectric capping layer40U comprises a second oxygen-free dielectric material.

In one embodiment, the first oxygen-free dielectric material is selected from silicon carbide, silicon nitride, or silicon carbide nitride; and the second oxygen-free dielectric material is selected from silicon carbide, silicon nitride, or silicon carbide nitride.

In one embodiment, an average thickness of the first interfacial dielectric capping layers40L is less than 20% of an average thickness of the metal layers46; and an average thickness of the second interfacial dielectric capping layers40U is less than 20% of the average thickness of the metal layers46.

In one embodiment, each of the metal layers46comprises molybdenum at an atomic percentage that is greater than 90%. In one embodiment, each of the metal layers46consists essentially of molybdenum.

In one embodiment, the vertical stack of memory elements comprises a vertical stack of discrete charge storage material portions located at levels of the metal layers46. In one embodiment, a discrete charge storage material portion within the vertical stack of discrete charge storage material portions comprises: an upper concave surface segment contacting a convex surface segment of a first instance of the airgap-containing insulating layer32; and a lower concave surface segment contacting a convex surface segment of a second instance of the airgap-containing insulating layer32. In one embodiment, a discrete charge storage material portion within the vertical stack of discrete charge storage material portions contacts an inner sidewall of a blocking dielectric material portion (such as a patterned portion of the second blocking dielectric layer502); and the blocking dielectric material portion contacts a surface segment of a first instance of the airgap-containing insulating layer32and a surface segment of a second instance of the airgap-containing insulating layer32.

In another embodiment, the vertical stack of memory elements comprises portions of a continuous memory material layer54that continuously vertically extends through the vertical repetition (32,40L,46,40U). In one embodiment, each of the memory stack structures55comprises at least one blocking dielectric layer (501,502) vertically extending through the vertical repetition and contacting an outer sidewall of a respective memory material layer54. In one embodiment, the at least one blocking dielectric layer (501,502) comprises an outer aluminum oxide blocking dielectric layer501and an inner silicon oxide blocking dielectric layer502located between the outer aluminum oxide blocking dielectric layer501and the respective continuous memory material layer54.

The various embodiments of the present disclosure can be employed to provide a three-dimensional memory array in which metal gates (e.g., select gate electrodes and control gate electrodes/word lines) may be formed by deposition and etching instead of by replacing sacrificial material layers with the metal gates. The memory opening fill structures may be formed after the metal gates are already deposited. This simplifies the process and allows the scaling of memory opening fill structures. Furthermore, it may avoid fluorine outgassing damage to the memory opening fill structures that may result from forming the metal gates using a fluorine containing precursor gas (e.g., tungsten hexafluoride) after forming the memory opening fill structures. Furthermore, metal oxide blocking dielectric layers may be formed in the memory openings rather than in backside recesses, which permits thicker, lower resistivity metal gates to be formed.

If airgaps are formed between the metal gates, then the space between neighboring pairs of metal gates has a lower dielectric constant than the dielectric constant of the material of the solid-phase dielectric material portions. The interfacial dielectric capping layers block or reduce diffusion of oxygen atoms into the metal gates, and thus, prevent or reduce oxidation of the metal gates, which decreases the roughness of the metal gates.