System and method for extreme performance die attach

A method for fabricating semiconductor die with die-attach preforms is disclosed. In embodiments, the method includes: applying an uncured die-attach paste material to a surface of a forming substrate to form one or more die-attach preforms, the surface of the forming substrate formed from a hydrophobic material; curing the one or more die-attach preforms; performing one or more planarization processes on the one or more die-attach preforms; coupling a first surface of a semiconductor die to a handling tool; and bonding a second surface of the semiconductor die to at least one die-attach preform of the one or more die-attach preforms.

BACKGROUND

Semiconductor die-attach materials play a significant role in the reliability and thermal resistance of bonded semiconductor die used in chips and integrated circuits. Sintered silver materials have become increasingly popular die-attach materials for high-power device applications, as well as in contexts which require extremely low thermal resistance interfaces between the semiconductor die and the associated substrate. For example, sintered nano-silver films have been found to exhibit low thermal resistance and excellent adhesion.

In order to bond semiconductor die to the die-attach materials, die-attach materials are typically formed into large die-attach films. The die-attach films may be formed on top of a polymer release film, which may then be deposed on a compliant material (e.g., rubber sheet). Subsequently, the semiconductor die are pressed against the film such that the die-attach film is lightly bonded, or “tacked,” to the bottom surface of the semiconductor die. The rubber sheet may then cause the die-attach film to deform around the edges of the semiconductor die such that the edges of the semiconductor die cut the film into the shape of the semiconductor die, and the portion of the die-attach film tacked to the bottom surface of the semiconductor die is separated from the larger die-attach film. The die-attach film may be bonded to the semiconductor die using heat and pressure. When the semiconductor die is then removed from the film, the portion of the film disposed beneath the semiconductor die may adhere to the bottom surface of the semiconductor die. Subsequently, the semiconductor die including the layer of die-attach material may be coupled to a product substrate (e.g., printed circuit board (PCB), ceramic substrate, integrated circuit device, multi-chip module, and the like) by sintering the die-attach material layer.

This traditional method of coupling die-attach materials to semiconductor die suffers from multiple drawbacks. First, this traditional approach is typically only feasible with larger semiconductor die (e.g., die larger than 0.05″×0.05″). With smaller die, the force required to locally cut the film such that the film may adhere to the die and separate from the film sheet is large enough to damage the small die. Secondly, using the die edges to cut the die-attach often is not an efficient and/or reliable process. With die of all sizes, the edges of the die may not cut the die-attach film cleanly during transfer. Furthermore, many semiconductor die include non-planar circuitry and other structures on a surface of the die which may be damaged when force is applied to the top surface of the die during the die-attach transfer processes.

Therefore, there exists a need in the art for a system and method which address one or more of the shortfalls of previous approaches identified above.

SUMMARY

A method for fabricating semiconductor die with die-attach preforms is disclosed. In embodiments, the method includes: applying an uncured die-attach paste material to a surface of a forming substrate to form one or more die-attach preforms, the surface of the forming substrate formed from a hydrophobic material; curing the one or more die-attach preforms; performing one or more planarization processes on the one or more die-attach preforms; coupling a first surface of a semiconductor die to a handling tool; and bonding a second surface of the semiconductor die to at least one die-attach preform of the one or more die-attach preforms.

A method for fabricating semiconductor die with die-attach preforms is disclosed. In embodiments, the method includes: forming one or more die-attach preforms on a forming substrate; performing one or more planarization processes on the one or more die-attach preforms; forming a graphite pad on a surface of a handling tool; coupling the graphite pad to a first surface of a semiconductor die; and bonding a second surface of the semiconductor die to at least one die-attach preform of the one or more die-attach preforms, wherein the at least one die-attach preform substantially conforms to a shape and size of the second surface of the semiconductor die.

This Summary is provided solely as an introduction to subject matter that is fully described in the Detailed Description and Drawings. The Summary should not be considered to describe essential features nor be used to determine the scope of the Claims. Moreover, it is to be understood that both the foregoing Summary and the following Detailed Description are provided for example only and are not necessarily restrictive of the subject matter claimed.

DETAILED DESCRIPTION

In order to bond semiconductor die to the die-attach materials, die-attach materials are typically formed into large die-attach films. The die-attach films may be formed on top of a polymer release film, which may then be deposed on a compliant material (e.g., rubber sheet). Subsequently, the semiconductor die are pressed against the film such that the die-attach film is lightly bonded, or “tacked,” to the bottom surface of the semiconductor die. The rubber sheet may then cause the die-attach film to deform around the edges of the semiconductor die such that the edges of the semiconductor die cut the film into the shape of the semiconductor die, and the portion of the die-attach film tacked to the bottom surface of the semiconductor die is separated from the larger die-attach film. The die-attach film may be bonded to the semiconductor die using heat and pressure. When the semiconductor die is then removed from the film, the portion of the film disposed beneath the semiconductor die may adhere to the bottom surface of the semiconductor die. Subsequently, the semiconductor die including the layer of die-attach material may be coupled to a product substrate (e.g., printed circuit board (PCB), ceramic substrate, integrated circuit device, multi-chip module, and the like) by sintering the die-attach material layer.

This traditional method of coupling die-attach materials to semiconductor die suffers from multiple drawbacks. First, this traditional approach is typically only feasible with larger semiconductor die. With smaller die, the force required to locally cut the film such that the film may adhere to the die and separate from the film sheet is large enough to damage the small die. Secondly, using the die edges to cut the die-attach often is not an efficient and/or reliable process. With dies of all sizes, the edges of the die may not cut the die-attach film cleanly during transfer. Furthermore, many semiconductor die include non-planar circuitry and other structures on a surface of the die which may be damaged when force is applied to the surface of the die with those structures during the die-attach transfer processes.

Accordingly, embodiments of the present disclosure are directed to a system and method which address one or more of the shortfalls of previous approaches identified above. Embodiments of the present disclosure are directed to a method for fabricating semiconductor die with die-attach preforms. In particular, embodiments of the present disclosure are directed to a method for attaching assemblies of semiconductor die with sintered silver preforms. Additional embodiments of the present disclosure are directed to a method of fabricating semiconductor die with die-attach preforms using a handling tool including a graphite pad. Further embodiments of the present disclosure are directed to a system for fabricating semiconductor die with die-attach preforms using a handling tool.

It is contemplated herein that embodiments of the present disclosure may provide for an improved system and method for fabricating semiconductor die, chips, modules, and other devices with improved thermal and radio frequency (RF) performance. The improved system and method of the present disclosure may enable high-density chip co-location, improved semiconductor die fabrication, extreme miniaturization of semiconductor die and chips, as well as improved power and thermal characteristics.

FIG. 1illustrates a simplified block diagram view of a system100for attaching semiconductor die to a die-attach preform, in accordance with one or more embodiments of the present disclosure. The system100may include, but is not limited to, a forming substrate102, a handling tool106, one or more actuators112, a controller114including one or more processors116and a memory118. In another embodiment, the system100may include and one or more planarization tools122communicatively coupled to the controller114.

In embodiments, one or more die-attach preforms104may be formed on the forming substrate102. It is noted herein that the one or more die-attach preforms104may be formed with any material known in the art including, but not limited to, sintered silver. In this regard, the one or more die-attach preforms104may be referred to as sintered silver preforms104. However, this is not to be regarded as a limitation of the present disclosure, unless noted otherwise herein.

The handling tool106may be communicatively coupled to one or more actuators112and/or the controller114. For example, the handling tool106may include one or more heating elements108and one or more vacuum sources110communicatively coupled to the controller114.

In other embodiments, the controller114may include one or more processors116and a memory118, wherein the one or more processors116are configured to execute a set of program instructions stored in memory118, the set of program instructions configured to cause the one or more processors116to carry out various steps/functions of the present disclosure. For example, the one or more processors116may be configured to: generate one or more control signals configured to cause the one or more planarization tools122to perform one or more planarization processes on the sintered silver preforms104; generate one or more control signals configured to cause the one or more actuators112to actuate the handling tool106to couple the handling tool106to one or more semiconductor die120; generate one or more control signals configured to cause the one or more vacuum sources110to create a suction force to handle the one or more semiconductor dies120; generate one or more control signals configured to actuate the handling tool106in order to bond the semiconductor die120to one or more sintered silver preforms104; generate one or more control signals configured to cause the one or more heating elements108to generate heat to cure the sintered silver preforms104; and generate one or more control signals configured to cause the one or more actuators112to actuate the semiconductor die120including a sintered silver preform104in order to couple the semiconductor die120to a product substrate (not shown).

Each of the processes/functions carried out by the controller114and other components of system100may be further understood with reference toFIG. 2.

FIG. 2Aillustrates a flowchart of a portion of a method200for attaching semiconductor die120to a die-attach preform104, in accordance with one or more embodiments of the present disclosure.

In a step202, one or more die-attach preforms104(e.g., sintered silver preforms104) are formed on a forming substrate102. As noted previously herein, the die-attach material used to form the one or more die-attach preforms104may include any die-attach material known in the art including, but not limited to, sintered silver, gold-tin eutectic materials, and the like.

The one or more die-attach preforms104may be fabricated, printed, or otherwise formed using any technique known in the art. In embodiments, the one or more die-attach preforms104may be formed by applying uncured (e.g., wet) die-attach material paste (e.g., sintered silver paste material) to the forming substrate102. For example, a stencil may be disposed on a surface of the forming substrate102, and a wet sintered silver paste material may be applied over the stencil and forming substrate102. Subsequently, the stencil may be removed from the forming substrate102. Upon removal of the stencil, excess sintered silver paste material may be removed, and the one or more sintered silver preforms104may be formed. It is noted herein that the stencil used to facilitate die-attach preform104printing may exhibit varying shapes, sizes, and configurations.

The forming substrate102may be formed from any material known in the art including, but not limited to, ceramic materials, alumina, and the like. It is contemplated herein that the use of a mechanically hard material, such as alumina, may reduce edge rounding in subsequent steps of method200when the semiconductor die120is coupled to the die-attach preforms104. In embodiments, the forming substrate102may be configured and/or be formed from materials which facilitate removal/release of the die-attach preforms104from the forming substrate102. For example, the forming substrate102may be formed from and/or coated with a hydrophobic material in order to provide a non-stick surface to prevent the uncured (e.g., wet) die-attach material (e.g., sintered silver) from adhering to the forming substrate102. For instance, the forming substrate102may be coated with a Teflon coating or other fluoropolymer coating. The hydrophobic coating used to provide a non-stick surface of the forming substrate102may be 1-2 μm thick. It is further noted herein that the use of a non-stick surface may provide a large contact angle on the forming substrate102in order to prevent the uncured (e.g., wet) die attach material from wetting underneath a stencil and/or flowing outside the borders of cut-outs within the stencil.

It is contemplated herein that the one or more die-attach preforms104may be formed in any configuration or array known in the art. This may be further understood with reference toFIG. 3.

FIG. 3illustrates a top view of sintered silver preforms104a,104b,104c,104d, in accordance with one or more embodiments of the present disclosure.

As shown inFIG. 3, the one or more die-attach preforms104(e.g., sintered silver preforms104) may be formed on the forming substrate102in a 2×2 array. For example, a stencil including cut-outs for a 2×2 array of preforms may be disposed on the forming substrate102, applied with a wet sintered silver paste material, and subsequently removed to form the 2×2 array of sintered silver preforms104a,104b,104c,104d. In embodiments, the one or more sintered silver preforms104may be formed/fabricated for a particular shape and size of semiconductor die120. For example, the one or more sintered silver preforms104may be formed/fabricated such that they substantially conform to a shape and/or size of a selected semiconductor die120. Accordingly, in embodiments including a stencil used to form the sintered silver preforms104, the stencil may include cut-outs which substantially conform to the shape and size of a selected semiconductor die120.

In addition to enabling more efficient and reliable fabrication of semiconductor die120with die-attach layers, it has also been found that embodiments of the present disclosure may provide significant cost savings throughout the fabrication processes. Due to the fact that the die-attach preforms104may be tailored to conform to specific sizes and shapes of specified semiconductor die120, less die-attach material may be wasted, thereby decreasing the quantity of die-attach material required for a specified number of semiconductor dies120. For example, it has been found that sintered silver preforms104may be formed at a cost of approximately $0.0005 per preform104/semiconductor die120, significantly less than is feasible using traditional die-attach film approaches.

Reference will again be made toFIG. 2A. In a step204, the one or more die-attach preforms104(e.g., sintered silver preforms104) are cured (e.g., dried). Curing the die-attach preforms104may include heating and/or drying in order to form a solid, weakly-bonded material. For example, the controller114may be configured to generate one or more control signals configured to cause the heating elements108and/or heating elements external to the handling tool106(not shown) to generate heat in order to dry the sintered silver preforms104. It is noted herein that the duration and/or temperature of the curing/drying process may be dependent upon the material used to form the die-attach preforms104. For example, the die-attach preforms104may be cured at (e.g., dried) a temperature between 120-160° C. below the sintering temperature associated with the die-attach material. For example, sintered silver preforms104may exhibit a sintering temperature between 250-290° C. In this regard, the sintered silver preforms104may be cured at a temperature of approximately 120-170° C. For instance, the sintered silver preforms104may be cured at a temperature of approximately 130° C.

In a step206, one or more planarization processes are performed on the one or more die-attach preforms104(e.g., sintered silver preforms104). It is noted herein that, following curing in step204, the die-attach preforms104may typically exhibit a non-uniform thickness. This may be further understood with reference toFIG. 4.

FIG. 4illustrates a graph400depicting thicknesses of sintered silver preforms104a-104fon a Teflon-coated forming substrate102prior to planarization, in accordance with one or more embodiments of the present disclosure. In particular, graph400illustrates the non-uniform thicknesses of a plurality of sintered silver preforms104a-104ffabricated on a Teflon-coated forming substrate102. It is further noted herein, however, that graph400may also be understood to illustrate thicknesses of sintered silver preforms104a-104fon alternative and/or additional substrate surfaces configured to inhibit adhesion to the substrate102.

As may be seen in graph400, each individual sintered silver preform104a-104fmay exhibit substantial thickness fluctuations across the upper surface of the sintered silver preform104a-104f. Absent any planarization processes configured to level and flatten the surfaces of the sintered silver preforms104a-104f, the sintered silver preforms104a-104fwould not be flush and/or conform to the surface of a semiconductor die120, and would therefore may not form an adequate bond with the semiconductor die120.

In this regard, one or more planarization processes may be performed in step206in order to planarize the one or more die-attach preforms104(e.g., sintered silver preforms104a-104f). The planarization processes may be configured to remove material from the die-attach preforms104(e.g., sintered silver preforms104a-104f) in order to generate die-attach preforms104of substantially uniform thicknesses. For example, the controller114may be configured to generate one or more control signals configured to cause the one or more planarization tools122to perform one or more planarization processes on the die-attach preforms104disposed on the forming substrate102. The planarization tools122may include any planarization/machining tools known in the art including, but not limited to, precision lathes, precision mills, diamond turning machining tools, and the like.

FIG. 5illustrates a graph500depicting thicknesses of sintered silver preforms104a-104eon a Teflon-coated forming substrate102following planarization, in accordance with one or more embodiments of the present disclosure. As may be seen in graph500, the sintered silver preforms104a-104fmay exhibit substantially improved thickness uniformity following planarization, which may enable effective coupling to the semiconductor die120in subsequent steps. It is further noted herein, however, that graph500may also be understood to illustrate thicknesses of sintered silver preforms104a-104eon alternative and/or additional substrate surfaces configured to inhibit adhesion to the substrate102.

Reference will again be made toFIG. 2A. In a step208, a first surface of a semiconductor die120is coupled to a handling tool106. For example, as shown inFIG. 1, an upper surface of the semiconductor die120may be coupled to a lower surface of the handling tool106such that the handling tool106may be actuated and control the motion of the semiconductor die120.

It is contemplated herein that the semiconductor die120may be held and/or coupled to the handling tool106using any technique known in the art. For example, the semiconductor substrate120may be coupled to the handling tool106through the use of a graphite pad, vacuum suction, and the like. This may be further understood with reference toFIG. 2B.

FIG. 2Billustrates a flowchart of a portion of method200for fabricating semiconductor die120with a die-attach preform, in accordance with one or more embodiments of the present disclosure. In particular,FIG. 2Billustrates potential sub-steps of step208for coupling a semiconductor die120to a handling tool120. As noted previously herein, the semiconductor die120may be held and/or coupled to the handling tool106using any technique known in the art. In this regard, the steps illustrated in FIG.2B are provided as examples and are not to be regarded as a limitation of the present disclosure, unless noted otherwise herein.

In a step210, a graphite pad is formed on a surface of the handling tool106. The handling tool106may include any actuatable tool known in the art configured to receive and handle semiconductor materials including, but not limited to, a robot, an actuatable mechanical arm, and the like. This may be further shown and described with reference toFIGS. 6A-6B.

FIG. 6Aillustrates a bottom perspective view of a handling tool106, in accordance with one or more embodiments of the present disclosure.FIG. 6Billustrates a side perspective view of a handling tool106, in accordance with one or more embodiments of the present disclosure.

In embodiments, a graphite pad126may be formed on a surface124of the handling tool106. For example, a graphite pad126may be formed on a lower surface124of the handling tool106. The surface124of the handling tool106may be formed from any material known in the art including, but not limited to, copper materials. Additionally, as noted previously herein with respect to the forming substrate102, the surface124of the handling tool106configured to be coupled to the graphite pad126/semiconductor die120may be coated with a non-stick, hydrophobic coating (e.g., fluoropolymer coating, Teflon). Hydrophobic coatings on the surface124of the handling tool106may enable easier removal of the graphite pad126and/or semiconductor substrates120in subsequent steps.

The graphite pad126may include any graphite pad known in the art including, but not limited to, a pyrolytic graphite film. In embodiments, a graphite pad126may be fabricated by applying a metal material to a graphite sheet. For example, after cleaning a graphite sheet (e.g., pyrolytic graphite sheet), the graphite sheet may be sputtered with an adhesion metal (e.g., titanium (Ti), chromium (Cr), nickel-chromium (NiCr)) followed by a seed metal(s) (e.g., palladium (Pd), copper (Cu)) and a low-melting temperature metal (e.g., tin (Sn), indium (In)). The various materials may be applied to the graphite sheet using any technique known in the art including, but not limited to, electroplating, electroless or immersion plating, sputtering, and the like. In embodiments, graphite pad126may be sized such that it substantially conforms to a shape and/or size of a selected semiconductor die120. Any methods known in the art may be used to cut or otherwise shape the graphite pad126including, but not limited to, steel rule die, razor blades, lasers, roll die, and the like.

In embodiments, the graphite pad126may be subsequently coupled to the surface124of the handling tool106. In some embodiments, the graphite pad126may be coupled to the surface124of the handling tool106using one or more diffusion bonding processes. For example, the graphite pad126may be coupled to the surface124of the handling tool106using transient liquid phase bonding, diffusion bonding, brazing processes, or the like.

For instance, in order to carry out transient liquid phase bonding, the controller114may actuate the handling tool106via actuators112in order to bring the handling tool106and the graphite pad126into contact. Subsequently, the controller114may cause the one or more heating elements108to generate heat and may actuate the handling tool106in order to induce heat and pressure between the surface124and the graphite pad126. While using tin as a metallizing material for the graphite pad126, the temperature for transient liquid phase bonding should be within the range of approximately 250° C. and 350° C. Additionally, the bonding time required for transient liquid phase bonding may be dependent upon the materials used in forming the graphite pad126. A forming gas may be used during bonding in order to minimize oxidation of the copper surface124of the handling tool106and tin material within the graphite pad126. The resulting bond between the graphite pad126and surface124of the handling tool106will be a high-melting point alloy/metallurgical bond with a melting point within the range of approximately 450° C. and 550° C. It is noted herein that the creation of a high-melting point alloy to bond the graphite pad126to the handling tool106is important to ensure sintering temperatures of the die-attach preforms104may be achieved without breaking the bond between the graphite pad126to the handling tool106. Transient liquid phase bonding is described in further detail in U.S. Pat. No. 7,830,021 B1, filed on Sep. 6, 2005, naming Ross K. Wilcoxon, Alan P. Boone, and James R. Wooldridge as inventors which is incorporated herein by reference in the entirety.

In a step212, the graphite pad126is coupled to a first surface of the semiconductor die120. For example, the controller114may be configured to generate one or more control signals configured to cause the actuators112to actuate the handling tool106in order to bring the surface124and/or graphite pad126into contact with an upper surface of a semiconductor die120.

It is noted herein that the graphite pad126may provide a soft but compliant surface which may prevent damage (e.g., scratching, cracking, passivation) to the semiconductor die120. In particular, the compliancy of the graphite pad126may help to evenly distribute pressure and bonding forces across the upper surface of the semiconductor die120, which may reduce stress across the semiconductor die120and prevent damage to delicate chip features on the upper surface of the semiconductor die120(e.g., air bridges, PIN diodes, monolithic microwave integrated circuits (MMICs)). It is noted herein that the graphite pad126may provide an efficient pick tool surface for a wide range of semiconductor die120sizes.

Additionally, the graphite pad126may be configured to handle very high temperature bonding (e.g., greater than 500° C.) and improve heat transfer to/through the semiconductor die120from the one or more heating elements108, which is necessary for high-speed bonding processes throughout subsequent steps of method200. Furthermore, as a good high-temperature elastomer, the graphite pad126may be extremely resilient and capable of being heated and/or compressed many times without degrading. Accordingly, it is contemplated herein that the graphite pad126may be used to handle many semiconductor die120throughout a fabrication process. Subsequently, when the graphite pad126is to be removed, it has been found that the graphite pad126may be easily removed from the surface124of the handling tool106via polishing processes.

In embodiments, the graphite pad126may include one or more carve-outs configured to receive one or more structures disposed on the first surface (e.g., upper surface) of the semiconductor die120. For example, the semiconductor die120may include any number of structures and/or features on the upper surface of the semiconductor die120(e.g., air bridges, PIN diodes, monolithic microwave integrated circuits (MMICs)). In order to reduce and/or prevent pressure from being applied to these structures, and potentially damaging the structures, one or more carve-outs may be formed in the bottom surface of the graphite pad126. The one or more carve-outs may be formed using any technique known in the art including, but not limited to, steel rule die, razor blades, lasers, roll die, and the like. Accordingly, the one or more carve-outs on the lower surface of the graphite pad126may be configured to receive the one or more structures on the upper surface of the semiconductor die120in order to reduce and/or prevent pressure on the one or more structures.

In a step214, a suction force is applied through a vacuum port128disposed in the surface124of the handling tool106with the one or more vacuum sources110. For example, the controller114may generate one or more control signals configured to cause the one or more vacuum sources110to generate a suction force through a vacuum port128disposed in the surface124of the handling tool106. In this regard, the one or more vacuum sources110may be fluidically coupled to the vacuum port128via one or more lines130. One or more vacuum ports128may be distributed throughout the surface124of the handling tool106. The vacuum ports128may take on any shape or size. For example, the one or more vacuum ports128may include circular ports with 3 mm diameters.

It is noted herein that suction forces may be used to temporarily couple a semiconductor die120to the handling tool106. The suction forces may be used in addition to, or in lieu of, the graphite pad126to enable efficient and reliable handling. In embodiments where the handling tool106utilizes both a graphite pad126and suction forces to handle a semiconductor die120, the suction forces may be applied through both the vacuum port128and the graphite pad126. For example, a graphite pad126may be formed on the surface124of the handling tool106such that the graphite pad126completely or partially covers the one or more vacuum ports128. A drill or other means may then be used to remove the portions of the graphite pad126covering the one or more vacuum ports128in order to create one or more apertures within the graphite pad126. The one or more vacuum sources110may then apply a suction force through the one or more vacuum ports128and the one or more apertures within the graphite pad126.

In a step216, the first surface of the semiconductor die120is coupled to the handling tool106and/or graphite pad126via the suction force. For example, in embodiments without a graphite pad126, a suction force may be applied through the one or more vacuum ports128in order to couple the surface124of the handling tool106directly to the upper surface of the semiconductor die120. By way of another example, in embodiments with a graphite pad126, a suction force may be applied through the one or more vacuum ports128and the one or more apertures within the graphite pad126in order to couple a surface of the graphite pad126to the upper surface of the semiconductor die120.

Reference will again be made toFIG. 2A. In a step218, a second surface of the semiconductor die120is bonded to at least one die-attach preform104(e.g., sintered silver preform104). For example, the controller114may generate one or more control signals configured to cause the actuators112to actuate the handling tool106in order to bring the lower surface of the semiconductor die120into contact with an upper surface of a sintered silver preform104. In this regard, the handling tool106may apply a first pressure between the graphite pad126and the upper surface of the semiconductor die120, and a second pressure between the lower surface of the semiconductor die120and the upper surface of a sintered silver preform104.

In a step220, the semiconductor die120including a bonded sintered silver preform104is bonded to a product substrate. For example, the semiconductor die120including a sintered silver preform104bonded to the second surface of the semiconductor die120may be bonded to a product substrate120(e.g., printed circuit board (PCB), ceramic substrate, integrated circuit device, multi-chip module, and the like) using heat and pressure.

Using conventional techniques for coupling semiconductor die to die-attach films, large forces/pressures were required to be applied to the semiconductor die in order to cut the die-attach films. Conversely, due to the fact that the die-attach preforms104are already cut and sized, the forces required to couple the semiconductor die120to the die-attach preforms104may be significantly reduced, thereby preventing damage (e.g., scratching, cracking, passivation) to the semiconductor die120. These reduced forces are especially important in the context of semiconductor die120with delicate structures (e.g., air bridges, PIN diodes, monolithic microwave integrated circuits (MMICs)) which are susceptible to damage under stress. Furthermore, it is noted herein that the area of small die is not linearly proportional to the perimeter. In this regard, conventional methods for cutting die-attach films require exceedingly high forces to achieve effective cutting of the die-attach films, which may damage the small semiconductor die120. Accordingly, the reduced forces enabled by the present disclosure may prove to be extremely valuable in the context of enabling semiconductor die120of decreasing sizes.

It is noted herein that bonding with die-attach materials often requires pressure and heat. Accordingly, in some embodiments, the controller114may generate one or more control signals configured to cause the one or more heating elements108to generate heat such that heat may be applied through the surface124of the handling tool106and through the graphite pad126/semiconductor die120to the joint surface between the semiconductor die120and sintered silver preform104. As noted previously herein, the temperature required for bonding the lower surface of the semiconductor die120and the upper surface of the die-attach preform104may depend on the material of the die-attach preform104. For example, in embodiments with a sintered silver preform104, the controller114may cause the heating elements108to generate heat sufficient to raise the temperature of the sintered silver preform104to between 230° C. and 300° C. in order to bond the semiconductor die120to the sintered silver preform104.

Following bonding of a die-attach preform104(e.g., sintered silver preform104), the semiconductor die120may be coupled to a product substrate. A product substrate may include any product substrate configured to receive a semiconductor die120including, but not limited to, a ceramic substrate, a printed circuit board (PCB), an integrated circuit, a package body (e.g., quad flat no-lead (QFN) package), and the like. For example, the controller114may generate one or more control signals configured to cause the actuators112to actuate the handling tool106in order to bring a lower surface of the die-attach preform104coupled to the semiconductor die120into contact with an upper surface of a product substrate. The controller114may then generate one or more control signals configured to cause the one or more heating elements108to generate heat such that heat may be applied through the surface124of the handling tool106, graphite pad126, semiconductor die120, and die-attach preform104to the joint surface between the die-attach preform104and a surface of the product substrate. In this regard, the heating elements108may be used to sinter the die-attach preform104coupled to a semiconductor die120in order to couple the semiconductor die120to the product substrate.

In embodiments, the use of the handling tool106for handling the various components of the present disclosure may provide for improved precision tooling, flexible size options, and fabrication of high-density product substrates. In particular, the use of a handling tool106actuatable via a controller114may enable die-attach preforms104and semiconductor die120to be fabricated and/or disposed adjacent to one another, thereby enabling further miniaturization of product substrates.

Embodiments of the present disclosure are directed to a novel die-attach material, process, and tooling approach for optimal thermal and RF performance of semiconductor die120. As compared to conventional approaches, it is contemplated herein that the system100and method200of the present disclosure may enable significant improvements in automation speed and throughput, as well as improvements in performance, yield, component miniaturization, and overall cost.

It is noted herein that the one or more components of system100may be communicatively coupled to the various other components of system100in any manner known in the art. For example, the one or more processors116may be communicatively coupled to each other and other components via a wireline (e.g., copper wire, fiber optic cable, and the like) or wireless connection (e.g., RF coupling, IR coupling, data network communication (e.g., WiFi, WiMax, Bluetooth, 3G, 4G, 4G LTE, 5G and the like).

In one embodiment, the one or more processors116may include any one or more processing elements known in the art. In this sense, the one or more processors116may include any microprocessor-type device configured to execute software algorithms and/or instructions. In one embodiment, the one or more processors116may consist of a desktop computer, mainframe computer system, workstation, image computer, parallel processor, or other computer system (e.g., networked computer) configured to execute a program configured to operate the system100, as described throughout the present disclosure. It should be recognized that the steps described throughout the present disclosure may be carried out by a single computer system or, alternatively, multiple computer systems. Furthermore, it should be recognized that the steps described throughout the present disclosure may be carried out on any one or more of the one or more processors116. In general, the term “processor” may be broadly defined to encompass any device having one or more processing elements, which execute program instructions from memory118. Moreover, different subsystems of the system100(e.g., controller114, actuators112, planarization tools122, handling tool106) may include processor or logic elements suitable for carrying out at least a portion of the steps described throughout the present disclosure. Therefore, the above description should not be interpreted as a limitation on the present disclosure but merely an illustration.

The memory118may include any storage medium known in the art suitable for storing program instructions executable by the associated one or more processors116. For example, the memory118may include a non-transitory memory medium. For instance, the memory118may include, but is not limited to, a read-only memory (ROM), a random-access memory (RAM), a magnetic or optical memory device (e.g., disk), a magnetic tape, a solid-state drive and the like. It is further noted that memory118may be housed in a common controller housing with the one or more processors116. In an alternative embodiment, the memory118may be located remotely with respect to the physical location of the processors116, controller114, and the like. In another embodiment, the memory118maintains program instructions for causing the one or more processors116to carry out the various steps described through the present disclosure.