Apparatus for radiation detection in a digital imaging system

The disclosure is directed at a method and apparatus for producing a detector element. The detector element includes first and second electrodes located on opposites sides of a semiconductor layer. The first and second electrodes are staggered with respect to each other in a plane perpendicular to the semiconductor layer.

FIELD OF THE DISCLOSURE

This disclosure relates generally to digital imaging systems, and more particularly to an apparatus for radiation detection in a digital imaging system.

BACKGROUND OF THE DISCLOSURE

Traditionally, X-ray diagnostic processes record x-ray image patterns on silver halide films. These systems direct an initially uniform pattern of impinging X-ray radiation through the object to be studied, intercept the modulated pattern of X-ray radiation with an X-ray radiation intensifying screen, record the intensified pattern on a silver halide film, and chemically transform the latent pattern into a permanent and visible image called a radiograph.

Radiographs are produced by using layers of radiation sensitive materials to directly capture radiographic images as modulated patterns of electrical charges. Depending on the intensity of the incident X-ray radiation, electrical charges generated either electrically or optically by the X-ray radiation within a pixel area are quantized using a regularly arranged array of discrete solid-state radiation sensors.

Recently, there has been rapid development of large area, flat panel, digital X-ray imagers for digital radiology using active matrix technologies used in large area displays. An active matrix includes a two-dimensional array (of which, each element is called a pixel) of thin film transistors (TFTs) made with a large area compatible semiconductor material. There are two general approaches to making flat-panel x-ray detectors, direct or indirect. The direct method primarily uses a thick photoconductor film (e.g. amorphous selenium) as the X-ray to electric charge converting layer coupled directly to the active matrix. In the indirect method, a phosphor screen or scintillator (e.g. CsI, GdOS etc.) is used to convert X-rays to light photons which are then converted to electric charge using an additional pixel level light sensor fabricated with the TFT on the active matrix array.

The key challenges with fabricating a vertical photodiode are the modifications required to the TFT fabrication process specifically, thick amorphous silicon layers, specialized p-doped contact layer and a complex reactive-ion etching (RIE) sidewall etching process to prevent optical crosstalk. These challenges reduce the fabrication yield and drive up the cost of manufacture. The key challenges with fabricating a lateral MSM photoconductor include the high dark currents at higher electric fields and photoresponse non-uniformity due to a non-uniform electric field. In addition, the lateral MSM photoconductor is not space efficient leading to low effective quantum efficiency (EQE). Each of these issues degrades imager performance, which is the key reason why MSM devices are not used in industry today for large area digital X-ray imaging.

SUMMARY OF THE DISCLOSURE

The present disclosure provides a system and method for an apparatus for radiation detection in a digital imaging system. The apparatus may be seen as a photoconductive element.

In one embodiment, the photoconductive element includes a lateral Metal-Insulator-Semiconductor-Insulator-Metal (MISIM) detector element. The insulator may also be seen as a blocking layer. The MISIM detector element can be coupled to a readout circuit element e.g. through a via in a dielectric layer that sits between the detector element and the readout circuit element.

In one embodiment, the apparatus includes a semiconducting layer to absorb incident photons and two electrodes coupled to the semiconducting layer located on opposite sides of the semiconducting layer. The two electrodes are preferably staggered with respect to each other. In a practical implementation, at least one of the electrodes is electrically isolated from the semiconducting layer using an insulator, or blocking layer. The insulated contact, or electrode, which is typically under high voltage bias, maintains a low dark current even under high electric field conditions. Applying the high electric field enables the apparatus, such as the MISIM detector, element to operate at a faster speed than conventional metal-semiconductor-metal (MSM) photoconductor designs and also to increase the collection efficiency (and hence EQE) of the electron hole pairs created by the photons impinging on the semiconducting layer. The structure of the present disclosure is simpler and correspondingly less expensive to manufacture in comparison to a traditional photodiode structure. Moreover, unlike traditional MSM photoconductors, the structure of the present disclosure yields higher performance because the readout circuit element can be embedded under the MISIM detector element yielding a larger area for light absorption. Also, putting the high voltage electrode away from the TFT electronics improves reliability. Moreover, the entire photoconductive element can be realized in a large area TFT display manufacturing process, which is more reliable and easier to access than the specialized process for a PIN photodiode. These and other advantages of the aspects of the present disclosure will be understood in conjunction with the following detailed description and accompanying drawings.

Therefore, there is provided a novel apparatus for radiation detection in a digital imaging system.

DETAILED DESCRIPTION

The present disclosure relates to an apparatus for radiation detection in a digital imaging system. The apparatus may include a photoconductive element that includes a detector element, such as a metal-insulator-semiconductor-insulator-metal (MISIM) detector element. In one embodiment, the detector element is integrated with a readout circuit element for a radiography imaging system.

In a preferred embodiment, the apparatus includes a pair of electrodes located on opposite sides of a semiconductor layer, the pair of electrodes staggered with respect to each other. In one embodiment, the pair of electrodes are spaced horizontally with respect to each other and do not overlap each other in a vertical plane. In another embodiment, the pair of electrodes are staggered with respect to each other in a plane perpendicular to the semiconductor layer.

FIG. 1illustrates a general diagram of a radiographic imaging environment. As shown, an X-ray source10generates an X-ray beam, or x-rays,11that is transmitted towards an object12, e.g. a patient's hand, for imaging by a radiography detector system (RDS)14. The results of the X-ray may be viewed on a computer16. In the current embodiment, which may be seen as an indirect imaging system, the radiography detector system14includes a scintillator15. In a direct imaging system, the x-rays11generate electronic charge within the radiography detector system14and there is no need for the scintillator15.

For some radiography detector systems14, synchronization hardware18is necessary to obtain the correct timing between the X-ray source10and the radiography detector system14that is sampling the impinging X-ray beam11. In the present disclosure, the radiography detector system14includes a large area, flat panel detector based on active matrix technologies to achieve the imaging of object12.

In general, the object12to be imaged is positioned between the radiation source10and the radiography detector system14. X-rays11, which pass through the object12interact with the radiography detector system14. In indirect imaging, the x-rays11generate light photons as they pass through a phosphor screen or scintillator15, such as structured Cesium Iodide (CO, Gadolinium oxysulfide (GOS) or Calcium Tungsten Oxide (CaWO4). These indirectly generated light photons then further generate electronic charge within the radiography detector system14.

FIG. 2is a schematic diagram of the radiography detector system14. The RDS14includes an active matrix pixel array20having a two-dimensional matrix of pixel elements where electronic charges generated directly or indirectly by incident x-rays are sensed and stored. In order to access the stored charge at each pixel, gate lines21are driven typically sequentially by a row switching control22causing all pixels in one row to output their stored charge onto data lines23that are coupled to charge amplifiers24at the end of each active matrix pixel array20column. The charge amplifiers24send the pixel charge data to analog-to-digital converters (A/D's)26, where the analog signal is converted to a digital representation. The digital representation is then be stored in memory28awaiting transmission to the computer16at a time determined by the control logic29. The charge amplifiers may also perform a multiplexing function in addition to their amplifying function.

FIG. 3is a schematic diagram of one embodiment of a pixel level circuit for one pixel in the active matrix pixel array20described inFIG. 2. The active matrix pixel array20typically contains a plurality of pixels. Within each pixel is a two terminal MISIM detector element30that absorbs the incident photons and generates electronic charge. A two terminal optional capacitor32stores the converted electronic charge and a readout circuit element, usually a three electrode thin film transistor (TFT) switch34transfers the electronic charge off the pixel. One electrode of the MISIM detector element30is connected to a high potential bias terminal33that is shared with other pixels in the active matrix pixel array20and one electrode of the capacitor32is connected to a low potential ground terminal35which is also shared with other pixels in the active matrix pixel array20. The drain electrode of the TFT switch34is connected to the second electrode of the MISIM detector30and the second terminal of the capacitor32. The source electrode of the TFT34is connected to the pixel data line36, which is coupled to one of the plurality of data lines23described inFIG. 2. The gate electrode of the TFT34is connected to the pixel gate line38, which is coupled to one of the plurality of gate lines21.

Turning toFIG. 4a, a schematic diagram of a first embodiment of a MISIM detector element30with the electrodes in a staggered configuration is shown. The detector element includes a substrate layer40atop which a first contact, or electrode,42, is deposited or patterned. A first blocking layer46is deposited atop the substrate layer40encapsulating the first electrode42. A semiconductor, or semiconducting, layer44is deposited atop the first blocking layer46and then a second blocking layer47deposited atop the semiconductor layer44. As can be seen, the first and second blocking layers46and47are located on opposite surfaces of the semiconductor layer44from each other.

A second electrode48is deposited, or patterned, on to the second blocking layer47. As shown inFIG. 4a, the first and second electrodes can be seen as being on opposite sides of the semiconductor layer44. In some embodiments, the anti-reflective layer49is optional and is not necessary for operation of the MISIM detector element30. However, in indirect conversion imaging, the anti-reflective layer49enhances performance by increasing the percentage of light photons impinging on the semiconducting layer44where photons are absorbed.

As can be seen inFIG. 4a, the first and second electrodes are staggered with respect to each other in a plane perpendicular to the semiconducting layer44. In other words, with respect to the vertical detector ofFIG. 4a, the first electrode is separated horizontally from the second electrode and does not overlap the second electrode in the vertical plane. In a preferred embodiment, the first and second electrodes do not overlap each other. Either one of the blocking layers may serve a dual function as a blocking layer and an anti-reflective layer.

In the current embodiment, one of the first or second contacts is coupled to either the first or second blocking layer or both. In some embodiments, where higher dark currents and lower EQEs are acceptable, either the first46or second47blocking layers or both may be replaced with ohmic and/or Schottky contacts. Besides X-ray digital imaging, other applications of the MISIM detector element could include biometric fingerprint imaging, touch displays and gesture displays. In biometric fingerprint imaging, the MISIM detector element is preferably sensitive to optical wavelengths and near infrared (600-900 nm) for multi-spectral imaging. In this embodiment, the thickness of the semiconductor layer44is selected so that the semiconductor layer can absorb infrared wavelengths along with optical wavelengths. Alternately, the semiconductor layer44could be replaced with a material having an enhanced sensitivity to infrared such as silicon nanowires, quantum dots, or other suitable inorganic or organic semiconducting material. For touch or gesture displays, because the MISIM detector element has a straightforward fabrication process and in a preferred embodiment, is directly compatible with large area thin film electronics processing, the MISIM detector element can be integrated directly into thin film LCD, OLED and LED displays to yield a high performance, cost-effective, display-sensor pixel unit.

Turning toFIG. 4b, a schematic diagram of a second embodiment of a MISIM detector element30in a staggered configuration is shown. The detector element30includes a substrate layer40atop a first electrode42is deposited or patterned. A first blocking layer46is deposited atop the substrate layer40encapsulating the first electrode42. A semiconductor layer44is deposited atop the first blocking layer46and then a second blocking layer47is deposited atop the semiconductor layer44. As can be seen the first and second blocking layers46and47are located on opposite surfaces of the semiconductor layer44from each other.

A second electrode48is deposited, or patterned, on to the second blocking layer47, which may be encapsulated by an antireflective layer49. In the current embodiment, one of the first or second electrode is coupled to either the first or second blocking layer. In some embodiments, the anti-reflective layer49is optional and is not necessary for operation of the MISIM detector element30. However, in indirect conversion imaging, the anti-reflective layer49enhances performance by increasing the percentage of light photons impinging on the semiconducting layer44where photons are absorbed.

As with the embodiment ofFIG. 4a, the electrodes, may be seen to be staggered with respect to each other, both in the horizontal plane and the vertical plane. Again, in some embodiments, where higher dark currents and lower EQEs are acceptable, either of the blocking layers or both may be optional or can be replaced with ohmic and/or Schottky contacts.

Turning toFIG. 4c, a schematic diagram of a third embodiment of a MISIM detector element30in a staggered configuration is shown. The detector element30includes a substrate layer40atop which an anti-reflective layer49may be deposited. As discussed with respect toFIG. 4b, the anti-reflective layer49is an optional layer. Atop the ant-reflective layer (or the substrate layer if no anti-reflective layer is present), a first electrode42is deposited or patterned. A first blocking layer46is deposited atop the anti-reflective49or substrate layer40encapsulating the first electrode42. A semiconductor layer44is deposited atop the first blocking layer46and then the second blocking layer47is deposited atop the semiconductor layer44. As can be seen the first and second blocking layers46and47are located on opposite surfaces of the semiconductor layer44from each other.

A second electrode48is deposited, or patterned, on to the second blocking layer47. In the current embodiment, one of the first or second electrode is coupled to either the first or second blocking layer.

As with the embodiment ofFIG. 4a, the electrodes, may be seen to be staggered with respect to each other, both in the horizontal plane and the vertical plane. Again, in some embodiments, where higher dark currents and lower EQEs are acceptable, either of the blocking layers or both may be optional or can be replaced with ohmic and/or Schottky contacts.

FIG. 4dshows a cross-section of a fourth embodiment of the MISIM detector element30in a top electrode configuration. In this embodiment, an optical anti-reflective layer49is deposited atop a substrate layer40. A semiconductor layer44is then deposited atop the anti-reflective layer49, or the substrate layer40if there is no anti-reflective layer. A blocking layer46is then deposited on the semiconducting44. A pair of electrodes42and48are then deposited, or patterned, on the blocking layer46. The pair of electrodes can be seen as being separated horizontally from each other.

FIG. 4eshows a cross-section of a fifth embodiment of the MISIM detector30in a bottom electrode configuration. In this embodiment, first there is a pair of the patterned electrode42and48atop the substrate layer40followed by a blocking layer46, a semiconducting layer44and the optional antireflective layer49.

Dark current is a key problem with traditional MSM detectors because it reduces the detector dynamic range and image quality and is a function of the electric field applied on the bias contact48. A large electric field is necessary for charge separation of the electronic carriers generated from the impinging photons on the semiconducting layer44. If photocurrent can be maintained at a high level while dark current is reduced or alternately, a higher electric potential can be applied to the bias contact48to increase charge separation efficiency and correspondingly the photocurrent, without increasing the dark current, then a larger photo-to-dark current ratio is possible which equates to better dynamic range, higher contrast, higher quantum efficiencies and better digital images. Neither ohmic nor Schottky contacts for the bias48and sense42contacts have to date been able to achieve the dark current densities necessary for sensitive medical radiography imaging applications (around 10 pA/mm2or less). However, for less stringent applications (e.g. in the biometric fingerprint scanning or touch sensing domains), ohmic and Schottky contacts may suffice.

In one aspect of the disclosure, the present disclosure uses a staggered MISIM contact architecture coupled with blocking layers that simultaneously: (1) reduce dark current when there are no photons impinging on the semiconducting layer and (2) enable high photocurrents when photons impinge on the semiconducting layer. Insulating contacts were typically not considered viable because of the anticipated slow response times and the potential for charge build-up on the insulating layer that can lead to reliability concerns.

To achieve these two goals, in the current disclosure, the material of the blocking layers46and47is carefully selected in order to: provide a low trap density interface with the semiconducting layer, prevent or reduce injection of charge carriers to the semiconducting layer from bias and sense electrode (e.g. have wide band-gap), and to have a dielectric strength such that it can be operated in soft (reversible) breakdown during device operation repeatably when the applied bias and blocking layer46thickness are optimized to take into account both the dark conductivity and photoconductivity of the semiconducting layer44which is also a function of semiconducting layer44thickness, applied electric bias and material properties.

When photons are impinging on the semiconducting layer44thereby causing the resistivity of the semiconducting layer44to decrease, the blocking layer46operates in soft (i.e. reversible) breakdown mode allowing a vertical conduction path from bias48and sense contacts42through the blocking layer46to the semiconducting layer44. Operating in soft breakdown allows for conduction through the blocking layer46which can overcome the response time challenge while still maintaining a low dark current by limiting bias48and sense42contact injection currents. Using a blocking layer46that is too thick or with a high dielectric breakdown strength can yield poor results or alternately, choice of an incompatible blocking layer46material can yield a poor interface with the semiconducting layer44so that traps and defects cause a drop in MISIM detector30quantum efficiency.

With the embodiments ofFIGS. 4aand 4b, the staggered design is enhanced when insulating blocking contacts are employed because there is need for a high voltage to be applied to the sensor bias48contact. Putting the bias contact48further away from the TFT (i.e. on top of the semiconducting layer44while the TFT and sense contact42are on the bottom side of the semiconducting layer44thus helps improve sensor and TFT reliability and reduces any excess leakage current corrupting the sensor signal due to the bias contact48.

In experiments, it was determined that using a 450 nm amorphous silicon semiconducting layer44works well with a polyimide blocking layer46of 200 nm. The blocking layer47can also be a 200 nm polyimide blocking layer. This combination yields an interface with high EQE (above 65%) for green light. Alternately, if high external quantum efficiency is required for blue light, then, for the same amorphous silicon and polyimide material combination, the semiconducting layer44thickness may need to be reduced which requires a corresponding re-optimization of the blocking layer thickness46. If the semiconducting layer44is changed from amorphous silicon to a metal oxide like IGZO (Indium Gallium Zinc Oxide) or even polysilicon, both of which have different material properties and absorption coefficients, the choice of blocking layer material (for interface purposes), thickness and maximum bias voltage applied may be reconsidered or re-optimized via calculation prior to manufacturing. Additional improvements in EQE are possible if an optional anti-reflective layer such as amorphous silicon nitride is used on top of the semiconducting layer directly in the path of the incident photons.

Moreover, it is noted that it is possible to pattern the blocking layer46and use either insulating contacts for both the bias48and sense42contacts or alternately, use an insulating contact for just one contact (e.g. either for the bias contact48or for the sense42contact depending on the bias used).

A patterning process (e.g. of the bias48or sense42contacts or the blocking layer46) can also potentially degrade the semiconducting layer44interface because of exposure to air and chemicals during the patterning process. Typically though, as shown inFIGS. 4ato 4d, a blocking layer running across both bias48and sense42contacts provides an improved interface with the semiconductor layer44with fewer defects and traps as well as encapsulating the semiconducting layer44thus maintaining higher quantum efficiency. In an alternative embodiment, MISIM detector elements where only one of the bias48or sense42contacts is insulated may be used if careful semiconductor processing is undertaken.

Moreover, as noted, the bias48and sense42contacts, can be placed, one each on opposite sides of the semiconducting44layer as long as they are separated by a horizontal distance so that photon absorption and transport remains in the horizontal (lateral) direction. Furthermore, if bias48and sense42contacts are made using transparent materials, both the top electrode or bottom electrode configuration can detect light photons equally well from either direction. Transparent materials include, but are not limited to, aluminium, molybdenum, chromium, indium tin oxide (ITO), zinc oxide (ZnO), indium gallium zinc oxide (IGZO), and poly (3,4-ethylenedioxythiophene) polystyrene sulfonate (PEDOT:PSS).

FIG. 5ashows a bottom gate, inverted staggered thin film transistor (TFT) structure where a substrate50(e.g. glass or plastic) contains a patterned gate electrode52, followed by a gate insulator54, a semiconducting layer56and a patterned contact layer defining the source58and drain59contacts.FIG. 5bshows a top gate, inverted staggered TFT structure with the layers in a reverse configuration. Both are implementations of amorphous silicon TFTs in use by the display industry today. Similar cross-sections can be drawn for CMOS (complementary metal-oxide-semiconductor), IGZO and polysilicon transistors as understood by one skilled in the art.

The photoconductive element implementation shown in at least one ofFIGS. 6ato 6gcan be mapped onto the pixel circuit shown inFIG. 3, where the transistor gate electrode63is connected to the pixel gate line38, the source electrode61is connected to the pixel data line36(seeFIG. 3) and the bias electrodes67are connected to the bias node33. Since the MISIM detector element has an intrinsic internal capacitance between the sense66and bias67electrodes as discussed earlier, the capacitor32shown inFIG. 3is optional. MoreoverFIGS. 6ato 6gcan be mapped onto other pixel readout circuits such as active pixel sensors or photon counting circuits as would be understood by one skilled in the art.

One additional challenge with placing the TFT readout circuit element underneath the MISIM detector element is that the normal operating voltage on the bias67and/or sense66electrodes can influence TFT operation especially if a bottom gate TFT configuration is employed as is the case in at least one ofFIGS. 6ato 6g. Here, a back gate75(e.g. preferentially coupled to the gate electrode63to minimize leakage current) is included to ensure the TFT does not conduct inadvertently due to one of the electrodes on top. If a top gate TFT configuration is employed, the need for the back gate75can be mitigated since the top gate will act as an electrostatic shield and reduce the likelihood of or prevent the bias67or sense66electrodes from inadvertently biasing the TFT ON.

In the device architecture shown in at least one ofFIGS. 6ato 6g, the scintillating layer68(akin to the scintillator15) is deposited or placed on top of the MISIM detector element due to the semiconducting layer70being exposed fully to incident light from the scintillating layer68resulting in a higher absorption of incident light and thus, better EQE. If the scintillating layer68is deposited or placed on the bottom (i.e. adjacent to the glass60), then there could be a loss of spatial resolution due to the thickness of the glass60and loss in EQE if the sense and bias electrodes are opaque and block light from reaching the amorphous silicon70semiconducting layer. Also, since the photoconductive element disclosed does not use a p+ doped layer like the PIN photodiode, blue light emitting scintillating phosphors can work.

The implementation shown inFIGS. 6aand 6buses a bottom gate TFT underlying the bottom electrode and staggered electrode MISIM detector respectively. The implementation shown inFIG. 6cuses a top gate TFT and bottom electrode MISIM detector in co-planer configuration. The implementation shown inFIGS. 6dand 6euses a top gate TFT underlying the bottom electrode and staggered electrode MISIM detector respectively.FIGS. 6fand 6gshow two possible implantations of fabricating the readout circuit element on top of the MISIM detector element.FIG. 6fuses a top electrode MISIM detector and top gate TFT whereFIG. 6guses a top electrode MISIM detector and bottom gate TFT switch. It should be noted that additional implementations are possible that use a combination of either a top or bottom gate TFT switch and a top or bottom or staggered electrode MISIM detector in both co-planar or fully overlap configuration (MISIM detector over TFT or TFT over MISIM detector). Moreover, use of transparent sense66and bias67electrodes can also enable top, bottom and staggered electrode MISIM detectors to be used interchangeably with comparable performance.

FIG. 6ashows a cross-section of a photoconductor element implemented using a readout circuit element embedded physically underneath the amorphous silicon MISIM detector element. The MISIM detector element includes sense66and bias67electrodes in a comb configuration, a polyimide blocking layer71(or alternately, among others, any wide band-gap organic/nonorganic insulator such as, but not limited to, amorphous silicon nitride, amorphous silicon oxide, amorphous silicon oxynitride, benzocyclobutene (BCB), parylene, polystyrene or any n/p-type organic/non-organic blocking layer such as PTCBI, CuPc) that covers at least one of the sense66or bias67electrodes, an amorphous silicon (a-Si:H) semiconducting layer70(or alternately, molybdenum sulphide, Indium Gallium Zinc Oxide, polycrystalline silicon, amorphous selenium, mercuric iodide, lead oxide, microcrystalline silicon, nanocrystalline silicon, crystalline silicon, pentacene, PTCBI, CuPc, small molecule organic semiconductor, or polymer organic semiconductor) and an optional anti-reflective coating layer69e.g. amorphous silicon nitride (a-SiNx:H).

The readout circuit element shown employs a bottom gate amorphous silicon TFT acting as a switch. The TFT includes an amorphous silicon nitride (a-SiNx:H) gate dielectric layer72, an amorphous silicon (a-Si:H) semiconducting layer73, an a-SiNx:H74passivation layer and a doped ohmic contact layer62.

Alternately, the readout circuit element could employ a variety of active pixel sensor or photon counting pixel readout circuits. Active pixel circuits include an on-pixel preamplifier circuit in place of the TFT switch circuit34shown inFIG. 3.

The MISIM detector element has a lower intrinsic capacitance than a comparably sized PIN photodiode due to the intrinsic capacitance that arises between the sense66and bias67electrodes, which are placed further apart (e.g. 5 um) in contrast to a PIN photodiode (e.g. 1 um). In particular, the lower capacitance of the MISIM detector element (here around 0.2 pF for a 100 micron pixel) as compared to PIN photodiodes (typically around 1 pF for a 100 micron pixel) makes the combination of a MISIM detector element with an active pixel sensor readout element superior in terms of signal-to-noise ratio (SNR). The SNR improvement occurs because the input charge to voltage gain of the MISIM detector element is proportionally higher than if a PIN diode is employed due to the proportionally lower capacitance of the MISIM detector element.

Embedding the readout circuit element underneath the MISIM detector element also has the advantages of increasing or maximizing the light absorption area. This becomes more important because active pixel sensor circuits typically use more than one transistor in the readout circuit element in contrast to a switch34that requires just one TFT. Thus, embedding the readout circuit element under the MISIM detector element is beneficial to maximize performance and EQE.

The TFT drain electrode76is connected by a via64in an interlevel dielectric65to one of the sense electrodes66where the dielectric65physically separates the MISIM detector element and the readout circuit element. The dielectric can be chosen from a variety of materials including amorphous silicon nitride, amorphous silicon oxide, amorphous silicon oxynitride, polyimide, benzocyclobutene (BCB), parylene, acrylic, and polystyrene or other common inorganic or organic dielectrics.

The choice of the dielectric65is important particularly because using a MISIM detector element requires the use of potentially high voltages due to insulating contacts. A high voltage on the bias67or sense66electrodes can give rise to high vertical electric field between the TFT electrodes (e.g. back gate75, source61or drain76) leading to local breakdown of the dielectric65.

However, each material has a different dielectric strength and breakdown voltage and correspondingly requires tuning of layer thickness. This design for high voltage resilience is in addition to the traditional design process undertaken to optimize an interlevel dielectric to serve as a planarization layer and as a low-k dielectric to reduce parasitic coupling capacitance. For example, if BCB is used for the dielectric65with a breakdown voltage of 1 MV/cm, and the bias67electrodes are set to a potential of 500V, then at least 5 um of BCB are necessary to prevent accidental dielectric65breakdown. The thickness of BCB required is now well beyond the thickness used typically for an interlevel dielectric in the TFT industry. Using very thick layers of dielectric65requires overcoming integration challenges between the detector element and readout circuit element.

The amorphous silicon MISIM detector element shown inFIG. 6aworks well if the bias67and sense66electrode layers are made thin (e.g. 50-100 nm) to avoid step coverage issues for the follow-on blocking layer71and semiconducting70layers. Here, for example, a 5 um thick dielectric65layer underneath the MISIM detector element may cause a functional (EQE loss) and reliability (poor connectivity) problem if the via is made in the traditional process with steep sidewall angles. So, to allow for proper continuity and coverage, the via64in the dielectric65can have a sloped or angled sidewall. For BCB, an angle of 45 degrees or shallower was discovered to work appropriately for this task although other sidewall angles and sense66and bias67electrode thickness combinations can also work by proper design as would be understood by one skilled in the art.

FIG. 6bshows a cross section of an alternative integration of MISIM detector with underlying readout circuitry. In order to increase the reliability and decreasing the chance of dielectric65breakdown (due to the use of potentially high voltages at the bias contact), the staggered electrode configuration for MISIM detector (FIG. 4b) has been used. It should be noted that the placement of the sense66and bias electrode67is preferred to be in a way that the vertical electric field between the bias electrode and the underlying TFT is at a reduced or minimum value. In one embodiment, the sensing electrode may be used to mask-out the electric field for the underlying TFT and line. Thus, the size of the TFT, the area of the pixel, the choice of the dielectric65and its thickness, the choice of the 1stand 2ndblocking layers71and77and the thickness of the semiconducting layer (e.g. a-Si:H)70affect the width and the spacing of the sense electrodes66and bias electrodes67.FIG. 6cshows a cross-section of a photoconductor element using a co-planar implementation. The element components can be mapped to the pixel level circuit shown inFIG. 3, which includes an amorphous silicon MISIM detector element30, a capacitor32and an amorphous silicon TFT switch34. InFIG. 6c, the MISIM detector cross-section81contains bias electrodes67and sense electrodes66in a commonly known comb electrode configuration along with a polyimide blocking layer71(or alternately, among others, any wide band-gap organic/nonorganic insulator such as: amorphous silicon nitride, amorphous silicon oxide, amorphous silicon oxynitride, benzocyclobutene (BCB), parylene, polystyrene or any n/p-type organic/non-organic blocking layer such as PTCBI, CuPc), a semiconducting layer of amorphous silicon70(or alternately, one or more of molybdenum sulphide, Indium Gallium Zinc Oxide, polycrystalline silicon, amorphous selenium, mercuric iodide, lead oxide, microcrystalline silicon, nanocrystalline silicon, crystalline silicon, PTCBI, or CuPc), an amorphous silicon nitride layer72and a further amorphous silicon nitride passivation layer82. The capacitor cross-section80shows the bottom plate shared with the sense electrode66along with a top capacitor plate connected to ground78, typically a low electric potential. The capacitor dielectric in this case is amorphous silicon nitride74, and is shared with the anti-reflective layer in the MISIM detector cross-section81. The TFT cross-section79includes a source electrode61connected to the pixel data line36fromFIG. 3. Also shown is a gate electrode63connected to the pixel gate line38inFIG. 3. The drain electrode76is connected to the sense electrodes66and forms one plate of the capacitor shown in the capacitor cross-section80. For the TFT cross-section79, an amorphous silicon layer73is the active layer and this can be shared with the MISIM detector cross-section81. The TFT gate dielectric is formed by an amorphous silicon nitride layer74, which can be shared with the anti-reflective layer shown in the MISIM detector's cross-section81and the capacitor's dielectric layer.

One of the benefits of the co-planar design shown inFIG. 6callows for shared uses of multiple layers, for example, the TFT gate dielectric can serve as an anti-reflective coating for the MISIM detector30(FIG. 3). In contrast, in a PIN diode, the unique amorphous silicon PIN isolation process and the thick semiconductor layer required to absorb green photons typically precludes sharing of any layers except metal contacts. In addition, the PIN diode sidewalls need to be etched carefully and passivated to reduce excess leakage current. In the MISIM detector30(FIG. 3), because the conduction path is horizontal, the horizontal interface is primarily important. As described earlier, using the blocking layer46helps protect the interface to the semiconducting layer44. Thus, device performance remains stable in the long term even if the MISIM detector30is built in a standard TFT switch34manufacturing process. It should be noted that the co-planar design ofFIG. 6ccan also be adapted to use the staggered sensor described inFIGS. 4aand4b.

FIGS. 6dand 6eare two other possible integrations of the MISIM detector30with the TFT switch34.FIGS. 6dand 6eshows a cross section of the implantation of the top gate TFT underneath the bottom and staggered electrode MISIM detector respectively. As it is shown inFIGS. 6dand 6e, these two designs may require inter-layer metal contact in order to connect the MISIM detector30to the TFT switch.

Turning toFIG. 7, a flowchart outlining a method of detector element manufacture is shown. Initially, atop a substrate, an anti-reflective layer is deposited atop a substrate layer (700). It will be understood that this is optional depending on the design of the detector element. A first electrode is then deposited atop the substrate layer or the anti-reflective layer (702) depending on detector element design.

A first blocking layer is then deposited atop the first electrode (704). As with the anti-reflective layer, the first blocking layer may be optional depending on the design of the detector element. A semiconductor layer is then deposited on the first blocking layer or the first electrode (706).

A second optional blocking layer can then be deposited atop the semiconductor layer (708). A second electrode is then deposited atop the second blocking layer or the semiconductor layer, depending on the design of the detector element (710).

In accordance with the disclosure, the first and second electrodes are located on opposite sides of the semiconductor layer and are staggered with respect to each other in a plane perpendicular to the semiconductor layer. In a preferred embodiment, the first and second electrodes are staggered such that they do not overlap each other.

Finally, another optional anti-reflective layer may be deposited atop the second electrode (712).