PRINTED CIRCUIT BOARD

A printed circuit board includes a wiring board including a plurality of insulating layers, a plurality of wiring layers, and a plurality of via layers, a first die embedded in the plurality of insulating layers, a bridge embedded on the first die in the plurality of insulating layers, a second die mounted on the wiring board, and a third die mounted on the wiring board.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims the benefit under 35 USC 119 (a) of Korean Patent Application No. 10-2021-0170043 filed on Dec. 1, 2021 in the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference for all purposes.

TECHNICAL FIELD

The present disclosure relates to a printed circuit board having a bridge and the like for die-to-die connection, embedded therein.

BACKGROUND

As semiconductor specifications become relatively higher, the fab node is being miniaturized, while the size of the die is increasing. When the size of the die increases, costs further increase. To improve this, various package platforms are being used, such as a multi-chip package in which a block with a different fab node required for each area inside the die is designed as a separate die, to connect the dies, chiplets in which multiple dies are packaged by breaking a large die into multiple smaller dies that serve the same function, or a 3D stack in which the dies are vertically stacked up.

In recent package platforms, it has become important to reduce the size of the package and to connect the die to the die well, and also to reduce costs.

SUMMARY

An aspect of the present disclosure is to provide a printed circuit board having a bridge capable of die-to-die interconnection, embedded therein.

An aspect of the present disclosure is to provide a printed circuit board in which the size of a package may be reduced.

An aspect of the present disclosure is to provide a printed circuit board in which costs may be reduced.

An aspect of the present disclosure is to provide a printed circuit board, in which a die is embedded together with abridge in an organic substrate to reduce the size of the board and a package provided thereby, and to facilitate a die-to-die connection.

According to an aspect of the present disclosure, a printed circuit board includes a wiring board including a plurality of insulating layers, a plurality of wiring layers, and a plurality of via layers, at least one of the plurality of insulating layers including an organic insulating material; a first die embedded in the plurality of insulating layers; a bridge embedded on the first die in the plurality of insulating layers; a second die mounted on the wiring board; and a third die mounted on the wiring board.

According to an aspect of the present disclosure, a printed circuit board includes a wiring board including a plurality of insulating layers, a plurality of wiring layers, and a plurality of via layers; a first die embedded in the plurality of insulating layers; a bridge embedded on the first die in the plurality of insulating layers; a second die mounted on the wiring board; and a third die mounted on the wiring board. The first die has a thickness lower than a thickness of at least one of the second and third dies.

DETAILED DESCRIPTION

The features described herein may be embodied in different forms, and are not to be construed as being limited to the examples described herein. Rather, the examples described herein have been provided and thus, this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to one of ordinary skill in the art.

Herein, it is noted that use of the term “may” with respect to an embodiment or example, e.g., as to what an embodiment or example may include or implement, means that at least an embodiment or example exists in which such a feature is included or implemented while all examples and examples are not limited thereto.

The features of the examples described herein may be combined in various manners as will be apparent after gaining an understanding of the disclosure of this application. Further, although the examples described herein have a variety of configurations, other configurations are possible as will be apparent after gaining an understanding of the disclosure of this application.

The drawings may not be to scale, and the relative sizes, proportions, and depiction of elements in the drawings may be exaggerated for clarity, illustration, and convenience.

Electronic Device

Referring toFIG.1, an electronic device1000may accommodate a mainboard1010therein. The mainboard1010may include chip related components1020, network related components1030, other components1040, and the like, physically or electrically connected thereto. These components may be connected to other electronic components to be described below to form various signal lines1090.

Depending on a type of the electronic device1000, the electronic device1000may include other electronic components that may or may not be physically or electrically connected to the mainboard1010. These other electronic components may include, for example, a camera module1050, an antenna module1060, a display device1070, a battery1080, and the like, but are not limited thereto. For example, other electronic components may also include an audio codec, a video codec, a power amplifier, a compass, an accelerometer, a gyroscope, a speaker, a mass storage unit (for example, a hard disk drive), a compact disk (CD) drive, a digital versatile disk (DVD) drive, or the like. In addition, these other components may also include other electronic components used for various purposes depending on a type of electronic device1000, or the like.

FIG.2is a schematic perspective view illustrating an example of an electronic device.

Referring toFIG.2, the electronic device may be, for example, a smartphone1100. A motherboard1110is accommodated in the smartphone1100, and various components1120are physically and/or electrically connected to the motherboard1110. In addition, other components that may or may not be physically or electrically connected to the motherboard1110, such as a camera module1130and/or a speaker1140, may be accommodated in the electronic device. Some of the components1120may be the chip related components described above, for example, a component package1121, but are not limited thereto. The component package1121may be in the form of a printed circuit board on which electronic components including active components and/or passive components are surface-mounted. Alternatively, the component package1121may be in the form of a printed circuit board in which active components and/or passive components are embedded. On the other hand, the electronic device is not necessarily limited to the smartphone1100, and may be another electronic device as described above.

Semiconductor Package Including Organic Interposer

In general, a semiconductor chip has many micro-electric circuits integrated therein, but it cannot function as a finished semiconductor product by itself, and there is a possibility of being damaged by an external physical or chemical shock. Therefore, the semiconductor chip itself is not used as it is, but the semiconductor chip is packaged and used in electronic devices as a package.

The reason semiconductor packaging is necessary is because there is a difference in the circuit width between the semiconductor chip and the mainboard of the electronic device from the viewpoint of electrical connection. In detail, in the case of a semiconductor chip, the size of the connection pad and the interval between the connection pads are very fine, whereas in the case of a mainboard used for electronic devices, the size of the component mounting pad and the interval between the component mounting pads are much larger than the scale of the semiconductor chip. Therefore, it is difficult to directly mount the semiconductor chip on such a mainboard, and a packaging technology capable of buffering a circuit width difference between each other is required.

Hereinafter, a semiconductor package including an organic interposer manufactured by such a packaging technology will be described in more detail with reference to the drawings.

FIG.3is a cross-sectional view schematically illustrating a case in which a BGA package is mounted on a mainboard of an electronic device.

Among semiconductor chips, application specific integrated circuits (ASICs), such as graphics processing units (GPUs), have a very high price for each chip, and thus, it is very important to perform packaging with a high yield. Therefore, before the semiconductor chip is mounted, a ball grid array (BGA) substrate2210capable of rewiring thousands to hundreds of thousands of connection pads is first prepared, and expensive components such as a GPU2220are prepared. The same semiconductor chip is subsequently mounted and packaged on the BGA substrate2210using a surface mounting technology (SMT) or the like, and then finally mounted on the mainboard2110.

On the other hand, in the case of the GPU2220, it is necessary to significantly reduce a signal path with a memory such as a high bandwidth memory (HBM), and to this end, a semiconductor chip such as an HBM2240is mounted on an interposer2230and is packaged, to then be stacked on the package on which the GPU2220is mounted in the form of a package on package (POP) and used. However, in this case, there is a problem in that the thickness of the device becomes too thick, and there is a limit in minimizing the signal path as well.

FIG.4is a cross-sectional view schematically illustrating a case in which a silicon interposer package is mounted on a mainboard.

As a method for preventing the above-described problem, manufacturing a semiconductor package2310including the organic interposer may be considered using an interposer technology in which a first semiconductor chip such as the GPU2220and a second semiconductor chip such as the HBM2240are surface-mounted side by side on a silicon interposer2250and then packaged. In this case, the GPU2220and the HBM2240having thousands to hundreds of thousands of connection pads may be redistributed through the interposer2250, and may be electrically connected through a minimum path. In addition, when the semiconductor package2310including the organic interposer is re-mounted on the BGA substrate2210or the like and redistributed, the semiconductor package2310may be finally mounted on the mainboard2110. However, in the case of the silicon interposer2250, it is very difficult to form a through-silicon via (TSV) and the like, and the manufacturing cost is also considerable, which is disadvantageous in terms of large area and low costs.

FIG.5is a cross-sectional view schematically illustrating a case in which an organic interposer package is mounted on a mainboard.

As a method for preventing the above-described problem, it may be considered to use an organic interposer2260instead of the silicon interposer2250. For example, on the organic interposer2260, a first semiconductor chip such as the GPU2220and a second semiconductor chip such as the HBM2240may be surface mounted side by side and then packaged, using an interposer technology, thereby manufacturing a semiconductor package2320. In this case, the GPU2220and the HBM2240having thousands to hundreds of thousands of connection pads may be redistributed through the interposer2260, and may be electrically connected through a minimum path. In addition, when the semiconductor package2310including the organic interposer is re-mounted on the BGA substrate2210or the like and redistributed, the semiconductor package2310may be finally mounted on the mainboard2110. In addition, it may be advantageous for increasing the area and reducing costs.

On the other hand, in the case of the semiconductor package2320including the organic interposer, the semiconductor chips2220and2240are mounted on the interposer2260, and then, a package process of molding the same is performed, thereby manufacturing the semiconductor package2320. This is because, if the molding process is not performed, handling is not performed, and the connection to the BGA substrate2210may not be performed. Therefore, the rigidity is maintained through molding. However, in the case of performing the molding process, as described above, problems such as warpage, deterioration of fillability of an underfill resin, and cracks between the die and the molding material may occur due to the mismatch of the coefficient of thermal expansion (CTE) of the interposer2260and the semiconductor chips2220and2240with the molding material, or the like.

Printed Circuit Board having Bridge and Die Embedded Therein

Hereinafter, a printed circuit board having a new structure in which abridge capable of interconnecting dies and a die are embedded in a wiring board will be described with reference to the drawings.

When the printed circuit board described below is used as a BGA board of a semiconductor package, the above-described separate interposer may be omitted if necessary.

FIG.6is a cross-sectional view schematically illustrating a printed circuit board according to an example.

FIG.7is a plan view schematically illustrating a top-view of a printed circuit board according to an example.

Referring to the drawings, a printed circuit board100according to an example includes a wiring board110including a plurality of insulating layers111a,111b,111c,111dand111e,a plurality of wiring layers112a,112band112c,and a plurality of via layers113a,113band113c,a first die130embedded in the plurality of insulating layers111a,111b,111c,111dand111e,a bridge120embedded on the first die130in the plurality of insulating layers111a,111b,111c,111d,and111e,a second die140mounted on the wiring board110, and a third die150mounted on the wiring board. For example, the printed circuit board100according to an example may have a package structure.

As described above, the printed circuit board100according to an example includes the bridge120, and thus, the mounted die-to-die interconnection may be more effectively implemented. In addition, since the first die130is also embedded in the wiring board110together with the bridge120, the overall size of the printed circuit board100may be reduced. For example, by separating the first die130from the second die140and stacking the separated first die130together with the bridge120in a stacking direction to be embedded, the size of the die disposed on the wiring board110may be reduced, and, as a result, the size of the printed circuit board100may be reduced. In addition, costs may also be reduced.

In the present disclosure, the stacking direction may refer to a direction in which respective components are stacked in a cross-sectional view, for example, a direction in which the plurality of insulating layers111a,111b,111c,111dand111eare stacked, and may also refer to the thickness direction from another point of view.

On the other hand, the first to third dies130,140, and150may be electrically connected to the bridge120, respectively. For example, the first to third dies130,140, and150may be electrically connected to one or more circuit layers of the bridge120, which will be described later. Therefore, the first to third dies130,140, and150may be interconnected with each other through the bridge120. From this point of view, the first die130may be disposed face-up such that a connection pad135faces the bridge120. In addition, the first to third dies130,140and150and the bridge120may be disposed such that at least respective portions thereof overlap each other thereof on a plane. Accordingly, the first to third dies130,140and150and the bridge120may be electrically connected to each other through a minimum path.

In the present disclosure, the meaning on a cross-section may refer to a cross-sectional shape when the object is vertically cut or a cross-sectional shape when the object is viewed as a side-view. In addition, the meaning on a plane may be a shape when the object is horizontally cut, or a planar shape when the object is viewed in a top-view or a bottom-view.

On the other hand, at least one of the plurality of insulating layers111a,111b,111c,111d,and111emay include an organic insulating material. In detail, at least build-up insulating layers111band111cmay each include an organic insulating material, and in more detail, the core insulating layer111a,the build-up insulating layers111band111c,and the passivation layers111dand111emay each include an organic insulating material. For example, the wiring board110may be an organic substrate. Therefore, compared to the silicon substrate, it is possible to reduce the difficulty of the process, and it is possible to reduce costs. The organic insulating material may include an insulating resin and an inorganic filler, and if necessary, may further include a glass fiber (Glass Fiber, Glass Cloth, Glass Fabric) as a core material for warpage control, etc., but the present disclosure is not limited thereto.

Also, the first die130may be thinner than at least one of the second and third dies140and150. For example, the first die130may be thinner than the third die150. Alternatively, the first die130may be thinner than the second die140, and may be thinner than the third die150. As such, since the thickness of the first die130embedded in the wiring board110may be relatively thin, the wiring board110may be made thinner, and the difficulty of the embedding process and costs may be further reduced.

Also, the first and second dies130and140may include a logic die, and the third die150may include a memory die. For example, the first and second dies130and140may be provided by dividing one large-size logic die. In this case, instead of mounting the first die130on the wiring board110, the first die may be stacked and embedded together with the bridge120in the wiring board110. In addition, the third die150may be a stack die such as HBM in which a plurality of memory dies are stacked in a stacking direction, and may be mounted on the wiring board110rather than embedded in the wiring board110. Accordingly, the size of the printed circuit board100may be reduced, and at the same time, the thickness of the wiring board110may be reduced, and costs may be reduced. For example, high-performance ASICs, System on Chips (SoCs), or the like may be manufactured in a relatively small size and costs may be reduced.

Also, the first to third dies130,140and150and the bridge120may be connected to each other, as one set, and the set may be provided as a plurality of sets. In this case, in each set, the bridge120and the first die130may be stacked and embedded in the wiring board110respectively, and thus, the size of the printed circuit board100may be significantly reduced, compared with the case of mounting the first die on the wiring board100without embedding the first die130.

Hereinafter, the components of the printed circuit board100according to an example will be described in more detail with reference to the drawings.

The wiring board110includes the plurality of insulating layers111a,111b,111c,111d,and111e,the plurality of wiring layers112a,112b,and112c,and the plurality of via layers113a,113b,and113c.The wiring board110may have a core shape. For example, the wiring board110may include a core insulating layer111a,first wiring layers112adisposed on both surfaces of the core insulating layer111a,a first via layer113apenetrating through the core insulating layer111aand electrically connecting the first wiring layers112aon both sides, one or more first build-up insulating layers111bbuilt up on the core insulating layer111a,one or more second wiring layers112brespectively disposed on the first build-up insulating layers111b,one or more second via layers113bpenetrating through the first build-up insulating layers111b,respectively, one or more second build-up insulating layers111cbuilt up below the core insulating layer111a,one or more third wiring layers112crespectively disposed on the second build-up insulating layers111c,one or more third via layers113cpenetrating through the second build-up insulating layers111c,respectively, a first passivation layer111ddisposed on the first build-up insulating layer111b,and a second passivation layer111edisposed on the second build-up insulating layer111c.However, the present disclosure is not limited thereto, and the wiring board110may be of a coreless type if necessary.

The core insulating layer111amay function as a core layer of the wiring board110and may provide rigidity. The material of the core insulating layer111ais not particularly limited. For example, an insulating material may be used. In this case, as the insulating material, a thermosetting resin such as an epoxy resin, a thermoplastic resin such as polyimide, or a resin in which these resins are mixed with an inorganic filler such as silica or impregnated into the core material such as glass fiber together with the inorganic filler, for example, prepreg, Ajinomoto build-up film (ABF), FR-4, bismaleimide triazine (BT), or the like may be used, but the insulating material is not limited thereto. The core insulating layer111amay be introduced through a copper clad laminate (CCL). The core insulating layer111amay have a higher modulus than the build-up insulating layers111band111c,but the present disclosure is not limited thereto. The core insulating layer111amay be thicker than each of the build-up insulating layers111band111c.

The build-up insulating layers111band111cmay be introduced to both sides of the core insulating layer111afor build-up. The material of the build-up insulating layers111band111cis also not particularly limited. For example, an insulating material may be used, and as the insulating material, a thermosetting resin such as an epoxy resin, a thermoplastic resin such as polyimide, or a resin in which these resins are mixed with an inorganic filler such as silica or impregnated into the core material of the inorganic filler resin, for example, prepreg, ABF, FR-4, BT, or the like may be used, but the insulating material is not limited thereto. The build-up insulating layers111band111cmay be equally built up on both sides based on the core insulating layer111a,and thus may have the same number of layers. The detailed number of layers is not particularly limited, and may be variously changed according to design.

The passivation layers111dand111eare disposed on outermost sides of both sides of the wiring board110to protect internal components of the wiring board110. A plurality of openings exposing portions of the wiring layers112band112cmay be formed in the passivation layers111dand111e,respectively. The material of the passivation layers111dand111eis not particularly limited. For example, an insulating material may be used, and in this case, a solder resist may be used as the insulating material. However, the present disclosure is not limited thereto, and ABF or the like may be used.

The wiring layers112a,112b,and112cmay perform various functions in the wiring board110according to the design of the corresponding layers, and for example, may include a ground pattern, a power pattern, a signal pattern, and the like. In this case, the signal pattern may include various signals other than a ground pattern and a power pattern, for example, include a data signal and the like. Each of these patterns may include a line pattern, a plane pattern, and/or a pad pattern. A material for forming the wiring layers112a,112b,and112cmay be a conductive material, in detail, a metal, such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or alloys thereof. The wiring layers112a,112b,and112cmay each include an electroless plating layer (or chemical copper) and an electrolytic plating layer (or electrolytic copper).

The via layers113a,113b,and113cmay electrically connect the wiring layers112a,112b,and112cformed in different layers, and as a result, an electrical path may be formed in the wiring board110. The via layers113a,113b,and113cmay perform various functions in the wiring board110according to the design of the corresponding layer, and for example, may include a ground via, a power via, a signal via, and the like. Each of the via layers113a,113b,and113cmay include a plurality of connection vias. The connection via of each of the via layers113a,113b,and113cmay include a conductive material, in detail, a metal material, such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti) or alloys thereof. The connection vias may each include an electroless plating layer (or chemical copper) and an electrolytic plating layer (or electrolytic copper). The connection via of each of the via layers113a,113b,and113cmay be of a type filled with a conductive material, but is not limited thereto, and may be a conformal type in which a conductive material is disposed along a wall surface of a via hole. The connection vias of the first via layer113amay respectively have an hourglass shape, a cylinder shape, or the like, and the respective connection vias of the second and third via layers113band113cmay have oppositely tapered shapes.

If necessary, bump layers114and115connected to the exposed wiring layers112band112cmay be disposed on the openings of the passivation layers111dand111e,respectively. The bump layers114and115may include a plurality of bumps, each of which is comprised of a pad and a via. Solder bonding may be facilitated through the bump layers114and115. The bump layers114and115may include a conductive material, in detail, a metallic material, such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or alloys thereof. The bump layers114and115may each include an electroless plating layer (or chemical copper) and an electrolytic plating layer (or electrolytic copper).

The bridge120may provide die-to-die interconnection, and the like. The bridge120may be a silicon bridge, an organic bridge, or the like, as will be described later. Details thereof will be described later.

Each of the dies130,140, and150may be a semiconductor chip. Each semiconductor chip may include an integrated circuit (IC) in which hundreds to millions of devices are integrated in a single chip. In this case, the integrated circuit may be a logic die such as a central processor (e.g., CPU), a graphics processor (e.g., GPU), a field programmable gate array (FPGA), a digital signal processor, an encryption processor, a microprocessor, a microcontroller, an analog-to-digital converter, an application-specific IC (ASIC), or the like, but is not limited thereto. For example, the integrated circuit may be a memory die or the like, such as a volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), flash memory, and high bandwidth memory (HBM), and may be other types such as a Power Management IC (PMIC) if necessary.

Each of the dies130,140, and150may be formed based on an active wafer, and in this case, silicon (Si), germanium (Ge), gallium arsenide (GaAs) or the like may be used as a base material constituting each body. Various circuits may be formed in the body. A connection pad may be formed on each body, and the connection pad may include a conductive material such as aluminum (Al) or copper (Cu). Each of the dies130,140, and150may be a bare die. In this case, the connection pad135may be exposed on the first die130embedded in the substrate, and metal bumps145and155may be respectively disposed on the connection pads of the second and third dies140and150mounted on the substrate. If necessary, a metal bump may also be disposed on the connection pad135of the first die130. Each of the dies130,140, and150may be a packaged die. In this case, in the case of the first die130embedded in the substrate, an additional redistribution layer is formed on the connection pad135such that an outermost redistribution layer may be exposed, and an additional redistribution layer is formed on the connection pads of the second and third dies140and150mounted on the substrate, and the metal bumps145and155are disposed on the redistribution layer, respectively. If necessary, a metal bump may also be disposed on the redistribution layer additionally formed on the connection pad135of the first die130. If necessary, the first die130may have the connection pad135on the lower surface as well as the upper surface, but the configuration is not limited thereto.

The dies130,140, and150may be connected to the bridge120through connecting members171,172, and173, and/or may be mounted on the wiring board110. For example, the connection pad135of the first die130may be connected to the bridge120through the first connecting member171. Also, the first metal bump145of the second die140may be connected to the wiring board110, for example, the first bump layer114through the second connecting member172. Also, the second metal bump155of the third die150may be connected to the wiring board110, for example, the first bump layer114through the third connecting member173. The connecting members171,172, and173are each formed of a low-melting-point metal, for example, solder such as tin(Sn)-aluminum(Al)-copper(Cu), tin(Sn)-silver(Ag), or the like, but this is only an example and the material is not particularly limited thereto. The connecting members171,172, and173may be formed of a multi-layer or a single layer, respectively, and for example, when formed as a multi-layer, the connecting members171,172, and173may include a copper pillar and solder, and when formed as a single-layer, the connecting members171,172, and173may include only solder, but is not limited thereto.

FIG.8is a cross-sectional view schematically illustrating a bridge according to an example.

Referring to the drawing, a bridge120aaccording to an example may be an organic bridge and may be implemented as the bride120described above. For example, the bridge120amay have a body including an organic insulating material. Therefore, even when the bridge120ais disposed in the wiring board110, a reliability problem due to a mismatch in the coefficient of thermal expansion may hardly occur. In addition, the difficulty of the process for forming the bridge120aand costs may be reduced. For the formation of the microcircuit, a photoimageable dielectric material (PID) may be used as the organic insulating material, but is not limited thereto.

The bridge120aaccording to an example may include one or more insulating layers121, one or more circuit layers122, and one or more via layers123. The one or more circuit layers122may have a higher density than the plurality of wiring layers112a,112b,and112c.For example, the one or more circuit layers122may be high-density circuits having a smaller line/space (L/S) and/or thickness than the plurality of wiring layers112a,112b,and112c,thereby being more effective for die-to-die interconnection. In this regard, the one or more via layers123may be formed to have a finer pitch than the plurality of via layers113a,113b,and113c,thereby being easier to design with high density.

The insulating layer121may provide a body of the bridge120a.The insulating layer121may include an insulating material, and in this case, the insulating material may be a photoimageable dielectric material (PID). When a photoimageable dielectric material (PID) is used as the material of the insulating layer121, the thickness of the insulating layer121may be significantly reduced and photo-via holes may be formed, such that the circuit layer122and the via layer123may be easily designed with high density. However, the material is not limited thereto, and other organic insulating materials may be used. The number of layers of the insulating layer121is not particularly limited, and may be variously changed according to design. Boundaries of the insulating layers121may be distinctive or may be uncertain.

The circuit layer122may provide a die-to-die interconnection path. The circuit layer122may perform various functions according to the design of the corresponding layer, and may include at least a signal pattern. The circuit layer122may include a conductive material, in detail, a metallic material, such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or alloys thereof. The circuit layers122may each include an electroless plating layer (or chemical copper) and an electrolytic plating layer (or electrolytic copper). The number of circuit layers122is also not particularly limited, and may be variously changed according to design. An uppermost circuit layer122of the circuit layers122may be connected to the second wiring layer112bthrough the second via layer113bof the above-described wiring board100. A lowermost circuit layer122of the circuit layers122may be connected to the aforementioned first die130through the aforementioned first connecting member171.

The via layer123may electrically connect the circuit layers122formed in different layers, and as a result, an electrical path may be provided in the bridge120a.The via layer123may perform various functions according to the design of the corresponding layer, and may include at least a signal via. Each of the via layers123may include a plurality of connection vias. The connection vias of each of the via layers123may include a conductive material, in detail, a metallic material, such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or alloys thereof. The connection vias may each include an electroless plating layer (or chemical copper) and an electrolytic plating layer (or electrolytic copper). The connection via of each of the via layers123may be a type filled with a conductive material or a conformal type in which a conductive material is disposed along a wall surface of the via. Te respective connection vias of the via layers123may have a tapered shape in the same direction.

FIG.9is a cross-sectional view schematically illustrating a bridge according to another example.

Referring to the drawing, a bridge120baccording to another example may be in the form of a semiconductor die and may be implemented as the bride120described above. For example, the bridge120bmay be a silicon bridge. For example, the bridge120bmay have a body including silicon, and a circuit may be formed by a semiconductor process. In this case, a finer circuit may be formed in the bridge120b,which may be more advantageous for die-to-die interconnection.

The bridge120baccording to another example may include one or more insulating layers121′, one or more circuit layers122′, and one or more via layers123′. The one or more circuit layers122′ may have a higher density than the plurality of wiring layers112a,112b,and112c.For example, the one or more circuit layers122′ may be high-density circuits having a smaller line/space (L/S) and/or thickness than the plurality of wiring layers112a,112b,and112c,thereby being more effective for die-to-die interconnection. In this regard, the one or more via layers123′ may be formed to have a finer pitch than the plurality of via layers113a,113b,and113c,thereby being easier to design with high density.

The insulating layer121′ may provide the body of the bridge120b,and may include an insulating material, and the insulating material may be silicon, in more detail, silicon dioxide. In this case, since the bridge120bmay be formed by a semiconductor wafer process, the circuit layer122′ and the via layer123′ may be easily designed with high density. However, the material is not particularly limited, and other semiconductor materials may be used. The number of layers of the insulating layer121′ is not particularly limited, and may be variously changed according to design. Boundaries between the insulating layers121′ may be distinct or may be uncertain.

The circuit layer122′ may provide a die-to-die interconnection path. The circuit layer122′ may perform various functions according to the design of the corresponding layer, and may include at least a signal pattern. The circuit layer122′ may include a conductive material, in detail, a metallic material, such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or alloys thereof. The circuit layer122′ may be formed by a deposition process such as chemical vapor deposition (CVD), but is not limited thereto. The number of the circuit layers122′ is also not particularly limited and may be changed according to design. An uppermost circuit layer122′ of the circuit layers122′ may be connected to the second wiring layer112bthrough the second via layer113bof the above-described wiring board100. A lowermost circuit layer122′ of the circuit layers122′ may be connected to the aforementioned first die130through the aforementioned first connecting member171.

The via layer123′ may electrically connect the circuit layers122′ formed in different layers, and as a result, an electrical path may be provided in the bridge120b.The via layer123′ may perform various functions according to a design of the corresponding layer, and may include at least a signal via. Each of the via layers123′ may include a plurality of connection vias. The connection vias of each of the via layers123′ may have a conductive material, in detail, a metallic material, such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or alloys thereof. The connection via of each of the via layers123′ may be a through silicon via (TSV), but is not limited thereto.

As set forth above, according to an embodiment, a printed circuit board having a bridge capable of die-to-die interconnection, embedded therein, may be provided.

A printed circuit board in which the size of a package may be reduced is provided.

A printed circuit board in which costs may be reduced is provided.

In the present disclosure, the lower side, the lower portion, the lower surface, and the like are used to indicate the direction toward the mounting surface of the semiconductor package including the organic interposer, based on the cross section of the drawing for convenience, and the upper side, the upper portion, the upper surface, and the like are used in the direction opposite thereto. However, the direction is defined for convenience of description, and the scope of the claims is not particularly limited by the description of this direction.