Techniques for operating semiconductor devices

Techniques for data storage are provided. In one aspect, a method for writing one or more magnetic memory cells comprises the following steps. Data is written to one or more of the magnetic memory cells. It is detected whether there are any errors in the data written to the one or more magnetic memory cells. The data is rewritten to each of the one or more previously written magnetic memory cells in which an error is detected.

FIELD OF THE INVENTION

The present invention relates to semiconductor devices and, more particularly, to techniques for data storage in semiconductor devices.

BACKGROUND OF THE INVENTION

Certain semiconductor devices, e.g., magnetic random access memory (MRAM) devices, use magnetic memory cells to store information. Each magnetic memory cell typically comprises a submicron piece of magnetic material, e.g., having the dimensions of 300 nanometers (nm) by 600 nm in area and five nm thick.

Information is stored in such semiconductor devices as an orientation of the magnetization of a free layer in the magnetic memory cell as compared to an orientation of the magnetization of a fixed (e.g., reference) layer in the memory cell. The magnetization of the free layer may be oriented parallel or anti-parallel relative to the fixed layer, representing either a logic “1” or a “0.” The orientation of the magnetization of a given layer (fixed or free) may be represented by an arrow pointing either to the left or to the right. When the magnetic memory cell is sitting in a zero applied magnetic field, the magnetization of the magnetic memory cell is stable, pointing either left or right. The application of a magnetic field can switch the magnetization of the free layer from left to right, and vice versa, to write information to the magnetic memory cell. One of the important requirements for data storage is that the magnetization of the cell not change orientation unintentionally during the writing process or when there is a zero applied field, or only a small applied field.

Unfortunately, in practice, the magnetization of one or more magnetic memory cells may change orientation unintentionally, due, at least in part, to thermal activation. Thermal activation occurs when thermal energy from the environment surrounding a given cell overcomes an activation energy barrier so as to change the direction of magnetization of the magnetic memory cell. The occurrences of thermal activation should be minimized. The resulting error rate due to thermally activated switching is called the soft error rate (SER).

One of the objectives in designing semiconductor devices is to minimize the operating power and area consumed by the devices. These two design objectives, namely, low operating power and small area, may be achieved by devices having a low switching field to switch such devices. A low switching field uses a low switching current, which in turn uses less power. Further, lower switching currents require smaller switches, which occupy less area. Consequently, these two design objectives are consistent with one another. However, lowering switching fields often undesirably lead to an increase in the SER.

Therefore, techniques are needed for operating semiconductor devices with a low switching field, while at the same time reducing, or eliminating, the effect of soft errors.

SUMMARY OF THE INVENTION

The present invention provides techniques for data storage. In one aspect of the invention, a method for writing one or more magnetic memory cells comprises the following steps. Data is written to one or more of the magnetic memory cells. It is detected whether there are any errors in the data written to the one or more magnetic memory cells. The data is rewritten to each of the one or more previously written magnetic memory cells in which an error is detected.

DETAILED DESCRIPTION OF THE INVENTION

FIG. 1is a diagram illustrating an exemplary free layer configuration of a magnetic memory cell having two anti-parallel coupled magnetic layers. Namely, in the exemplary configuration shown inFIG. 1, a free layer may comprise at least two magnetic layers, e.g., magnetic layers102and104, anti-parallel coupled by spacer layer106. Spacer layer106may comprise a transition metal. Suitable transition metals include, but are not limited to, chromium, copper, ruthenium, rhodium, palladium, rhenium, osmium, iridium, platinum and combinations comprising at least one of the foregoing transition metals.

A magnetic memory cell having a free layer comprising two anti-parallel coupled magnetic layers is hereinafter referred to as a “toggle magnetic memory cell.” U.S. Pat. No. 6,545,906 issued to Savtchenko et al. (hereinafter “Savtchenko”), the disclosure of which is incorporated by reference herein, discloses the use of such a toggle magnetic memory cell in an MRAM device. Savtchenko describes a writing process wherein a magnetic memory cell is first read to determine its state, and then, if necessary, toggled.

As shown inFIG. 1, magnetic layers102and104have opposite directed magnetizations, as indicated by the vector arrows corresponding to each layer. As will be described in detail below, for example in conjunction with the description ofFIG. 2, the directions of magnetization of magnetic layers102and104in the states shown, e.g., “0” and “1,” are typically directed at approximately 45 degree angles with respect to the x- and y-coordinate axes, e.g., the bit line and word line, respectively, of the magnetic memory cell.

When the magnetic memory cell is switched, e.g., from a “0” state to a “1” state, or vice versa, the orientations of magnetic layers102and104reverse. Readout of a magnetic memory cell, e.g., reading the state of the cell as either a “0” or a “1,” for example, through its resistance properties, may be accomplished by tunneling into the free layer from a fixed layer of the cell. Regarding a free layer comprising multiple layers, readout of a magnetic memory cell may be accomplished by tunneling into one of the multiple layers of the free layer, e.g., magnetic layer102or104, from the fixed layer. Namely, the resistance of such a tunnel junction depends primarily on the relative orientations of magnetization of the free magnetic layer as a whole and the fixed magnetic layer.

FIG. 2is a diagram illustrating a sequence of top down views of a free layer comprising multiple magnetic layers engaged in a switching operation. For ease of illustration, the vectors representing the directions of magnetization of the two magnetic layers making up the free layer, e.g., magnetic layers102and104as inFIG. 1above, are shown as being displaced from one another with a common origin. However, these vectors actually lie substantially one on top of the other.

As mentioned above, each of the two magnetic layers making up the free layer have natural anisotropy directions that point at approximately 45 degrees to the x- and y-axes of the magnetic memory cell (as illustrated by the vector arrows corresponding to each layer) such that the natural directions the magnetization vectors point are also generally along approximately 45 degrees to the x- and y-axes of the magnetic memory cell. This orientation is shown in view202ofFIG. 2.

According to the exemplary technique illustrated inFIG. 2, as the magnetic memory cell is switched, the magnetic field along the y-axis of the magnetic memory cell Hyis first pulsed on causing the magnetic moments of the two magnetic layers making up the free layer (oriented anti-parallel to each other) to cant. This will create a net total moment, indicated by a solid black vector arrow, for the magnetic layers making up the free layer, as is shown in view204ofFIG. 2. Next, the magnetic field along the x-axis of the magnetic memory cell Hxis also pulsed on, causing the net magnetic moment of the magnetic layers making up the free layer to rotate 45 degrees, as is shown in view206ofFIG. 2. Hyis then pulsed off and the net moment of the canted magnetic layers rotates 45 degrees further, as is shown in view208ofFIG. 2. Hxis then pulsed off and the canted magnetic layers relax back to having a direction of magnetization opposite to one another, e.g., along the 45 degree anisotropy direction, as is shown in view210ofFIG. 2.

It is important to note, however, that the two magnetic layers making up the free layer now each have a direction of magnetization opposite to the original orientation of each layer, as can be seen from a comparison of view210with view202ofFIG. 2. Therefore, the magnetic memory cell has been “toggle written” by this sequence of field pulsing.

FIG. 3is a graph illustrating a deterministic representation of the magnetic field for switching a magnetic memory cell. Namely,FIG. 3illustrates the typical operating window for a magnetic memory cell undergoing toggle writing. The sequence of field pulsing, e.g., pulsing of Hxand Hy, that constitutes the write operation is illustrated by the dashed trajectory. This trajectory must transverse toggle write region/no switch region boundary302in order for the magnetic memory cell to be written.

With toggle writing, there is a probability that during the write operation, e.g., as described above in conjunction with the description ofFIG. 2above, the magnetic moments of the magnetic layers making up the free layer will spontaneously reverse, due to, for instance, normal thermally activated processes. This spontaneous reversal contributes to the soft error rate (SER). Therefore, there is some probability that after the write operation, the magnetic memory cell will end up in the wrong state. This probability may be acceptably small for large magnetic memory cells, e.g., 16 megabit memory, with high write currents, e.g., less than or equal to about 0.1 failures in ten years, but becomes unworkably large as magnetic memory cell size and write currents are reduced. The probability of errors, bit size and write currents are described, by way of example, in detail below.

According to the techniques presented herein, writing of a magnetic memory cell can be accomplished at a smaller write field and a predicted number of soft errors are accommodated by subsequently performing a checking step to detect if the magnetic memory cell was written correctly. If the magnetic memory cell was not written correctly, it is written again. Using reduced write fields, predicting soft errors and performing checking steps to detect the soft errors will be described in detail below.

A smaller write field results in a reduced activation energy barrier Eafor the magnetic memory cell during the period when the write field is applied. A reduced Eacan result in, for example, up to about three percent of the magnetic memory cells written ending up in the wrong magnetic state.

Activation energy may be approximated using a single domain model and assuming that the intrinsic anisotropy is small, e.g., less than about 50 Oersted (Oe), compared to the dipole fields:
ea=(h4−2h2sin 2a+1)1/2.   (1)
FIG. 4is a graph illustrating the Eafor an exemplary magnetic memory cell. Namely, the graph inFIG. 4shows that Eais in fact variable along the box path, which may be contrasted with the deterministic view of Eashown, for example, inFIG. 3.

In Equation 1, above, reduced units are used, as indicated by, for example, the use of eato represent unitless activation energy. For example, ea=1 is the activation energy in zero field and h=1 is the magnitude of the applied magnetic field equal to the spin flop field Hsf. Reduced units may be converted to field units or energy units using the formulas provided inFIG. 4. For example, regarding field units, Ea=ea(2HiMsN)1/2, and regarding energy units, Hx=hx(HiMsAth) and Hy=hy(HiMsAth), wherein A is the area of the memory cell, this the thickness of the memory cell, Hiis the intrinsic anisotropy of the memory cell, Msis magnetization and N is the demagnetization factor. For example, N=4π(th/b)nx, wherein b is the width of the cell and nx is the dimensionless demagnetization factor, for example, for a circle nx=0.785. The x-axis and the y-axis of the graph shown inFIG. 4are the magnetic fields from the bit line and the word line, respectively. α represents the angle from the bit line field axis. At α=π/4, Eagoes to zero at the spin flop point (hx=hy=1/√{square root over (2)}). It is to be appreciated that the bit line and word line fields are not confined to a particular orientation.

To avoid soft errors, regions of reduced Eatypically are avoided. Specifically, to make the probability of unwanted reversal of the magnetic memory cell during the write operation no greater than during the storage operation, e.g., less than about 0.1 failures over a ten year period for a given exemplary 16 megabit memory, an ea≧1 should be maintained throughout the entire write path.

A write path for switching the magnetic memory cell, indicated by dashed lines superimposed on the Eagraph ofFIG. 4, reveals that when the word line field is first turned on to hy=hbox, and the bit line field is turned on to hx=hbox, and then the word line field is turned off, and the bit line field is turned off, the lowest Eaoccurs approximately at hx=hboxand hy=hsf, or at hx=hsfand hy=hbox(as indicated by the arrows inFIG. 4). Putting these fields into Equation 1, above, provides the lowest activation energy along the write path to be approximately,
ealowest=((h2box+½)2−2√{square root over (2)}hbox+1)1/2for hbox>1/√{square root over (2)}.   (2)
Therefore, hboxshould be greater than or equal to about 1.14 in order to maintain an ea≧1. However, according to the teachings presented herein, write fields may be employed that are substantially less than 1.14 (e.g., hbox<1.14).

As can be seen fromFIG. 4, employing a write field that is less than 1.14 results in ea<1 along some portion of the write path. Therefore, there will be some probability that the storage state of the magnetic memory cell will reverse, e.g., resulting in a nonzero SER.FIG. 5is a graph illustrating Eaas a function of the write field. Namely, inFIG. 5, Equation 2 is shown plotted as a function of hbox. The Earequired to make the SER vanishingly small so as to be negligible, (an ea≧1) is shown by the dashed line inFIG. 5. An ea≧1 requires writing at a field of hbox≧1.14, as indicated by the arrow labeled “B.” For hbox<1.14, the activation energy decreases to zero around hbox=0.7. According to the teachings of the present invention, a write field as small as hbox≦0.8 may be used, as indicated by the arrow labeled “A,” which will reduce the power consumed by the magnetic memory cell.

Employing a write field of hbox≦1.14 yields a probability P of the magnetic memory cell ending up in the wrong state, e.g., failing, as,

P=1-exp⁡[-tτ⁢ⅇ-Ea/kT],(3)
wherein τ is the attempt period (which is typically about 0.5 nanoseconds), t is the length of time the bit has reduced Ea, k is Boltzmann's constant and T is the absolute temperature of the magnetic memory cell. t can be approximated as a fraction of the pulse length for which Eais substantially reduced, e.g., less than or equal to about 0.5 of the pulse length.

Combining Equations 2 and 3, above, provides a good estimate of the SER.FIG. 6is a graph illustrating the probability of soft errors as a function of the write field of a magnetic memory cell. Namely, inFIG. 6, Equation 3 is plotted as a function of the write field, normalized by a write field of hbox=1.14 that, as described above, maintains an ea≧1 (i.e., the x axis being the ratio hbox/1.14).FIG. 6shows that operating at only 65 percent of the typical write field will result in about a three percent SER. As will be described in detail below, these three percent errors are caught during a checking step wherein incorrectly written magnetic memory cells are written a second time (e.g., rewritten). Those rewritten magnetic memory cells then are checked again, and it is probable that about three percent of those rewritten magnetic memory cells will be in error (e.g., 0.09 percent of the original number of magnetic memory cells). Those three percent of incorrectly rewritten magnetic memory cells will be rewritten a third or more time. This cycle continues until all magnetic memory cells are written correctly, for example, which may entail about one in a million magnetic memory cells needing to be written five times or more, e.g., up to about ten times or more. As a result, the write current is reduced by about 35 percent, as compared to hbox=1.14, and the write time has been increased by about five times.

FIG. 7is a logical flow diagram illustrating an exemplary methodology700for writing one or more magnetic memory cells, in accordance with one aspect of the invention. In step702, addresses and data for n magnetic memory cells that are to be written are input. In step704, the stored data is read and compared to the input data. Magnetic memory cells that require toggling are then selected. In step706, those selected magnetic memory cells that require toggling are toggled, for example using a write field hbox<1.14.

In step708, the data stored in the magnetic memory cells are checked again. Namely, for at least those magnetic memory cells toggled in step706, the stored data is read and compared to the input data. Any of the magnetic memory cells toggled in step706that are in error are selected for toggling a second time. The subset of memory cells selected for toggling again will generally be substantially smaller than the set of memory cells selected in step706.

In step710, the process loops back to the toggling step, e.g., step706, if any magnetic memory cells remain that are in error. The process is continued until all cells are written correctly.

Typically, in step706about 50 percent of the magnetic memory cells are written. However, only a small fraction of the magnetic memory cells, e.g., about 0.5P, will need to be rewritten. Further, only about 0.5P2of the magnetic memory cells will need to be rewritten a second time. Therefore, in general, on the jthpass, only a fraction about 0.5Pj−1of the magnetic memory cells will need to be written. Since P<<1, in a few iterations of the process all of the magnetic memory cells selected for toggling will be correctly written.

According to the exemplary methodology illustrated inFIG. 7, the write time will be variable. Namely, in some instances all the magnetic memory cells may be written correctly on the first pass through the loop, whereas in other cases, five or six passes through the loop may be required, resulting in a longer write time.

Error correction code (ECC) may be employed in the present techniques to attain a predictable write time, as will be described in detail below, for example, in conjunction with the description ofFIG. 8. With ECC, data is stored along with two or more extra bits of data that are used to correct detected errors. For example, the use of six ECC bits for every 64 bits of data allow for the correction of single bit errors and the detection of double bit errors. Error correction and detection methodologies are known by those skilled in the art. However, while ECC can be employed to correct one error in the 64+six bits, by design ECC cannot correct two or more errors. Therefore, as will be described in detail below, ECC can be combined with the present techniques in a way that intentionally allows one write error to go by uncorrected, and only rewrites data if there are two or more write errors present.

With toggle magnetic memory cells, soft errors only affect the magnetic memory cells being toggle written. Magnetic memory cells that are not selected or that are only half selected have no significant probability of being upset by soft errors (e.g., have no SER). Therefore, errors are only produced during the write operation of the magnetic memory cells toggled.

According to the present techniques employing ECC, if one error is produced during the write operation, that error can be left uncorrected because it will be detected and corrected when the data is read out using the ECC. Thus, only if there are two or more errors, will they need to be corrected during the write operation, such as by using the exemplary methodology described above in connection withFIG. 7.

Further, in an exemplary embodiment, P is chosen to be small enough, such that the probability of having three or more errors is negligibly small, e.g., less than about 0.1 failures over a ten year period for, e.g., an exemplary 16 megabit memory, and thus essentially never encountered in practice. In this way, at most one or two errors are ever preferably encountered, and the system only has to loop back to rewrite magnetic memory cells at most once, thereby providing a well defined upper limit on the write time.

FIG. 8is a logical flow diagram illustrating an exemplary methodology800for writing one or more memory cells using ECC. In step802, the addresses and data for the n memory cells, e.g., magnetic memory cells, that are to be written are input. Based on this data, the ECC bits are computed, as in step804, while at the same time the stored data and stored ECC bits are read in, as in step806. In step808, the stored data and ECC bits are compared to the input data to determine which magnetic memory cells need to be toggled. In step810, those magnetic memory cells that need to be written are toggled. In step812, the data and ECC bits are read, and the ECC is used to determine if there are two or more errors present in the written data. In step814, if there are no errors, or if there is at most a single error, then the write operation is finished (the one error being correctable using the ECC during a read operation), as in step816. If there are two or more errors, then the system loops back, e.g., to step808, to compare the data again and determine which magnetic memory cells to re-toggle (e.g., rewrite), as previously explained.

This loop continues until there is at most one error (the write probabilities are such that there is a vanishingly small probability more than one additional loop will be required), as is described in detail below. Therefore, there is a definite predictable maximum write cycle time associated with the exemplary methodology800.

For example, if the write field is chosen to be 75 percent of hbox=1.14, then it may be determined from the exemplary graph shown inFIG. 6, that the probability of failing is about P=3×10−8. Therefore, given an exemplary 64 bit word, the chance of there being two errors, which will need to be corrected, is roughly 2×10−12. However, the probability for there being three or more errors is less than 2×10−18, which is unlikely to occur during the lifetime of typical data storage devices. Further, the probability of there being two successive write cycles with two write errors is roughly 2×10−27, which is also unlikely to occur during the lifetime of typical data storage devices.

FIG. 9is a block diagram of an exemplary hardware implementation of one or more of the methodologies of the present invention. Apparatus900comprises a computer system910that interacts with media950. Computer system910comprises a processor920, a network interface925, a memory930, a media interface935and an optional display940, connected together, for example, via a bus915. Network interface925allows computer system910to connect to a network, while media interface935allows computer system910to interact with media950, such as, but not limited to, a Digital Versatile Disk (DVD) or a hard drive.

As is known in the art, the methods and apparatus discussed herein may be distributed as an article of manufacture that itself comprises a computer-readable medium having computer-readable code means embodied thereon. The computer-readable program code means is operable, in conjunction with a computer system such as computer system910, to carry out all or some of the steps to perform one or more of the methods or create the apparatus discussed herein. For example, the computer-readable code is configured to implement a method for writing one or more magnetic memory cells, by the steps of: writing data to one or more of the magnetic memory cells; detecting whether there are any errors in the data written to the one or more magnetic memory cells; and rewriting the data to each of the one or more previously written magnetic memory cells in which an error is detected. The computer-readable medium may be a recordable medium (e.g., floppy disks, hard drive, optical disks such as a DVD, or memory cards) or may be a transmission medium (e.g., a network comprising fiber-optics, the world-wide web, cables, or a wireless channel using time-division multiple access, code-division multiple access, or other radio-frequency channel). Any medium known or developed that can store information suitable for use with a computer system may be used. The computer-readable code means is any mechanism for allowing a computer to read instructions and data, such as magnetic variations on a magnetic medium or height variations on the surface of a compact disk.

Memory930configures the processor920to implement the methods, steps, and functions disclosed herein. The memory930could be distributed or local and the processor920could be distributed or singular. The memory930could be implemented as an electrical, magnetic or optical memory, or any combination of these or other types of storage devices. Moreover, the term “memory” should be construed broadly enough to encompass any information able to be read from or written to an address in the addressable space accessed by processor920. With this definition, information on a network, accessible through network interface925, is still within memory930because the processor920can retrieve the information from the network. It should be noted that each distributed processor that makes up processor920generally contains its own addressable memory space. It should also be noted that some or all of computer system910can be incorporated into an application-specific or general-use integrated circuit.

In an alternative exemplary embodiment, memory930comprises memory array934having one or more magnetic memory cells. Memory930also comprises a write circuit932coupled to memory array934by one or more bits lines938and word lines936. Write circuit932is adapted to perform one or more of the techniques presented herein.

Optional video display940is any type of video display suitable for interacting with a human user of apparatus900. Generally, video display940is a computer monitor or other similar video display.