Power on reset circuit

A power on reset circuit, comprising: a threshold level control circuit (120) configured to set threshold level values of power on reset and power off reset; a capacitor charge and discharge circuit (130) configured to output a power on reset signal according to the threshold level values set by the threshold level control circuit; and a current bias circuit (110) configured to provide a reference current not varying with a power supply to the threshold level control circuit (120) and the capacitor charge and discharge circuit (130), comprising: a first reference current output terminal connected to the threshold level control circuit (120); a second reference current output terminal connected to the capacitor charge and discharge circuit (130); and a third reference current output terminal connected to the capacitor charge and discharge circuit (130).

FIELD OF THE INVENTION

The present invention relates to a field of control of integrated circuit, and particularly relates to a power on reset circuit.

BACKGROUND OF THE INVENTION

A power on reset circuit is substantially built in the conventional chip. There are many types of power-on reset circuits. Currently, it is most widely applied that the power on reset (POR) signal is generated by using resistance-capacitance, Schmitt triggers or inverters.

However, when the conventional power on reset circuit converts the level by using the inverter, the anti-interference ability of the conventional power on reset circuit for the power supply disturbance is relatively poor, that is to say, when the power supply jitters near converting the level by the inverter, the inverter will convert the level continually and generate a series of unstable POR signals. Such a phenomenon is called a false triggering, so that the chip cannot work normally. The circuit that uses the Schmitt trigger to convert the level has a certain anti-interference capability. However, it is difficult to set the upper and lower threshold levels of the Schmitt trigger accurately, and the threshold levels vary with the fluctuation of the power supply voltage. Therefore, it is difficult to accurately modulate threshold levels of the power on reset, so that the resulting POR signal is unstable.

SUMMARY OF THE INVENTION

Accordingly, it is necessary to provide a power on reset circuit, which can generate a stable power on reset signal.

A power on reset circuit includes:

a threshold level control circuit configured to set threshold level values of power on reset and power off reset;

a capacitor charge and discharge circuit configured to output a power on reset signal according to the threshold level values set by the threshold level control circuit; and

a current bias circuit configured to provide a reference current not varying with a power supply to the threshold level control circuit and the capacitor charge and discharge circuit, including:

a first reference current output terminal connected to the threshold level control circuit;

a second reference current output terminal connected to the capacitor charge and discharge circuit; and

a third reference current output terminal connected to the capacitor charge and discharge circuit.

According to the above power on reset circuit, the current bias circuit provides three reference currents not varying with a power supply to the threshold level control circuit and the capacitor charge and discharge circuit. Such threshold level control circuit generates accurate threshold level values by reference currents provided by the current bias circuit; the capacitor charge and discharge circuit enables the capacitor charge and discharge times to be calculated accurately by reference currents provided by the current bias circuit; in the case whether the power supply performs a quick power on operation or a slow power on operation, the capacitor charge and discharge circuit can generate a stable power on reset signal.

DETAILED DESCRIPTION OF THE EMBODIMENTS

Referring toFIG. 1, in an embodiment, a power on reset circuit includes a current bias circuit110, a threshold level control circuit120and a capacitor charge and discharge circuit130.

The current bias circuit110is configured to provide a reference current not varying with a power supply to the threshold level control circuit120and the capacitor charge and discharge circuit130. In the embodiment, the current bias circuit110includes a first reference current output terminal Ibias1, a second reference current output terminal Ibias2and a third reference current output terminal Ibias3. The first reference current output terminal Ibias1is connected to the threshold level control circuit120; the second reference current output terminal Ibias2and the third reference current output terminal Ibias3are connected to the capacitor charge and discharge circuit130.

Referring toFIG. 2, the current bias circuit110includes a first field effect transistor MN1, a second field effect transistor MN2, a third field effect transistor MN3, a fourth field effect transistor MP1, a fifth field effect transistor MP2and a sixth field effect transistor MP3.

A gate of the first field effect transistor MN1is connected to a drain thereof; the drain of the first field effect transistor MN1is externally connected to a reference current source Ibias. Sources of the first field effect transistor MN1, the second field effect transistor MN2and the third field effect transistor MN3are grounded GND; a gate of the second field effect transistor MN2is connected to the gate of the first field effect transistor MN1; a drain of the second field effect transistor MN2is connected to a drain of the fourth field effect transistor MP1; a gate of the third field effect transistor MN3is connected to the gate of the first field effect transistor MN1; a drain of the third field effect transistor MN3serves as the third reference current output terminal Ibias3. A gate of the fourth field effect transistor MP1is connected to a drain of the fourth field effect transistor MP1; a gate of the fifth field effect transistor MP2is connected to the gate of the fourth field effect transistor MP1; sources of the fourth field effect transistor MP1, the fifth field effect transistor MP2and the sixth field effect transistor MP3are connected to the power supply VDD; a drain of the fifth field effect transistor MP2serves as the second reference current output terminal Ibias2; a gate of the sixth field effect transistor MP3is connected to the gate of the fourth field effect transistor MP1; and a drain of the sixth field effect transistor MP3serves as the first reference current output terminal Ibias1.

In the embodiment, the first field effect transistor MN1, the second field effect transistor MN2and the third field effect transistor MN3are N-type field effect transistors; the fourth field effect transistor MP1, the fifth field effect transistor MP2and the sixth field effect transistor MP3are P-type field effect transistors.

The threshold level control circuit120is configured to set threshold level values of power on reset and power off reset, with reference toFIG. 3.

The threshold level control circuit includes a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a first diode D1, a second diode D2, a third diode D3, a first comparator Comp1, a second comparator Comp2, a third comparator Comp3, a first NOR gate Nor1and a second NOR gate Nor2.

The first resistor R1, the second resistor R2and the third resistor R3are connected in series between the first reference current output terminal Ibias1and the ground GND; the fourth resistor R4, the fifth resistor R5and the sixth resistor R6are connected in series between the power supply VDD and the ground GND.

A non-inverting input terminal ip of the first comparator Comp1is connected between the fourth resistor R4and the fifth resistor R5; an inverting input terminal in of the first comparator Comp1is connected between the first resistor R1and the second resistor R2; an output terminal out of the first comparator Comp1is connected to a first input terminal of the first NOR gate Nor1.

A non-inverting input terminal ip of the second comparator Comp2is connected between the second resistor R2and the third resistor R3; an inverting input terminal in of the second comparator Comp2is connected between the fourth resistor R4and the fifth resistor R5; an output terminal out of the second comparator Comp2is connected to a first input terminal of the second NOR gate Nor2.

A non-inverting input terminal ip of the third comparator Comp3and an anode of the first diode D1are connected to the first reference current output terminal Ibias1; an inverting input terminal in of the third comparator Comp3is connected between the fifth resistor R5and the sixth resistor R6; an output terminal out of the third comparator Comp3is connected to the capacitor charge and discharge circuit130; particularly, the output terminal out of the third comparator Comp3is connected to G1.

A cathode of the first diode D1is connected to an anode of the second diode D2; a cathode of the second diode D2is grounded. The third diode is connected between the inverting input terminal in of the third comparator Comp3and the ground. An output terminal of the first NOR gate Nor1is connected to a second input terminal of the second NOR gate Nor2; an output terminal of the second NOR gate Nor2is connected to a second input terminal of the first NOR gate Nor1and the capacitor charge and discharge circuit130; particularly, the output terminal of the second NOR gate Nor2is connected to G2.

Because the reference current source Ibias externally connected by the current bias circuit110is generally from the reference power supply circuit in the chip, if the power on time of the power supply VDD is less than the establishment time of the reference voltage power supply circuit in the chip, then the circuit will fail. The first diode D1and the second diode D2connected in series can ensure the capacitor charge and discharge circuit130will not generate the POR signal before the reference voltage source Ibias is established.

The capacitor charge and discharge circuit130is configured to output POR according to the threshold level values set by the threshold level control circuit120, with reference toFIG. 4.

The capacitor charge and discharge circuit includes a seventh field effect transistor MP4, a eighth field effect transistor MP5, a ninth field effect transistor MN4, a tenth field effect transistor MN5, a first capacitor C1and an inverter INV.

A source of the seventh field effect transistor MP4is connected to the power supply VDD; a drain of the seventh field effect transistor MP4is connected to a drain of the eighth field effect transistor MP5, a drain of the ninth field effect transistor MN4, a gate of the tenth field effect transistor MN5, an anode of the first capacitor C1and an input terminal of the inverter INV respectively; a gate of the seventh field effect transistor MP4is connected to G1; sources of the eighth field effect transistor MP5and the ninth field effect transistor MN4are connected to the second reference current output terminal Ibias2and the third reference current output terminal Ibias3respectively; a gate of the eighth field effect transistor MP5is connected to G2; a source and a drain of the tenth field effect transistor MN5are grounded GND; a cathode of the first capacitor C1is grounded; and an output of the inverter INV outputs POR.

The working principle of the power on reset circuit is illustrated with reference toFIG. 1toFIG. 4in the following.

The reference current source Ibias externally connected provides three reference currents not varying with the power supply VDD via the current bias circuit110. The first reference current output terminal Ibias1is connected to the first resistor R1, the second resistor R2and the third resistor R3connected in series, and then more accurate upper threshold level and lower threshold level are generate. Given that the current value output by the first reference current output terminal Ibias1is I1, the resistance values of the first resistor R1, the second resistor R2and the third resistor R3are R1, R2and R3respectively, then the upper threshold level is I1×(R2+R3) and the lower threshold level is I1×R3; that is to say, the difference between the upper threshold level and the lower threshold level is I1×R2.

It can be understood that in other embodiments, the second resistor R2and the third resistor R3connected in series can be replaced by N resistors with lower resistance values connected in series, wherein N is not less than 2; more accurate upper threshold level and lower threshold level can be obtained by finely adjusting the number of resistors connected in series. Meanwhile, the difference between threshold levels can be adjusted flexibly, which can implement the anti-interference capacity of the power supply in different chip applications.

The fourth resistor R4, the fifth resistor R5and the sixth resistor R6connected in series and cooperated with each other can implement that the power supply VDD can generate POR signals at different voltage values. For example, when resistance values of the fourth resistor R4, the fifth resistor R5and the sixth resistor R6are same, the corresponding power supply voltage are 1.5×I1×(R2+R3), 1.5×I1×R3respectively when upper threshold level and lower threshold level generate POR. Therefore, the fourth resistor R4, the fifth resistor R5and the sixth resistor R6can implement coarse adjustment of voltage values when the power supply VDD generates POR signals, and the first resistor R1, the second resistor R2and the third resistor R3can implement fine adjustment of such voltage values.

Currents output by the second reference current output terminal Ibias2and the third reference current output terminal Ibias3provided by the current bias circuit110are charge current and discharge current in the capacitor charge and discharge circuit130respectively. Current values of these two current sources can be set according to practical application situation.

In the embodiment, the current value output by the second reference current output terminal Ibias2is the double of the current value output by the third reference current output terminal Ibias3. It can be understood that in other embodiments, it only needs to make sure that the current value output by the second reference current output terminal Ibias2is an integer multiple of the current value output by the third reference current output terminal Ibias3.

Because the bias current does not vary with the power supply VDD, the charge time can be calculated accurately: T1=(V1×C1)/I2. Similarly, the discharge time can be calculated accurately: T2=2×(V1−V2)×C1/I2; wherein V1is the voltage value of the gate of the tenth field effect transistor MN5; C1is a sum of the capacitance value of the tenth field effect transistor MN5and the capacitance value of the first capacitor C1; I2is the current value output by the second reference current output terminal Ibias2; V2is the corresponding conversion level value of the inverter INV.

When the power supply VDD performs a power on operation, the voltage V3between the fourth resistor R4and the fifth resistor R5follows up in proportion; the first comparator Comp1outputs “0”; the second comparator Comp2outputs “1”; the second NOR gate Nor2outputs “0”; the eighth field effect transistor MP5is turned on; the current output by the second reference current output terminal Ibias2charges the first capacitor C1; the gate voltage of the tenth field effect transistor MN5raises; the inverter INV outputs “0”.

When the voltage V3between the fourth resistor R4and the fifth resistor R5raises to the lower threshold level, the first comparator Comp1outputs “0”; the second comparator Comp2outputs “0”; the second NOR gate Nor2outputs “0”; the current output by the second reference current output terminal IBias2continues to charge the first capacitor C1; the inverter still outputs “0”; when the voltage V3between the fourth resistor R4and the fifth resistor R5raises to the upper threshold level, the first comparator Comp1outputs “1”; the second comparator Comp2outputs “0”; the second NOR gate Nor2outputs “1”; the first capacitor C1begins to discharge; the inverter outputs “1”; the POR signal is generated.

When the power supply VDD performs a power off operation, the voltage V3between the fourth resistor R4and the fifth resistor R5begins to decrease; when the voltage V3decreases to the upper threshold level, the first comparator Comp1outputs “0”; the second comparator Comp2outputs “0”; the second NOR gate Nor2outputs “1”; the inverter INV still outputs “1”; when the voltage V3between the fourth resistor R4and the fifth resistor R5decreases to the lower threshold level, the first comparator Comp1outputs “0”; the second comparator Comp2outputs “1”; the second NOR gate Nor2outputs “0”; the inverter INV outputs “0”.

Simulated waveforms of the power on reset circuit during power on and power off are shown inFIG. 5toFIG. 8; whereinFIG. 5is a simulated waveform diagram of the power supply voltage during power on and power off in the normal case;FIG. 6is a simulated waveform diagram of the corresponding POR signal voltage;FIG. 7is a simulated waveform diagram of the power supply voltage during power on and power off when fluctuation of the power supply is 30%;FIG. 8is a simulated waveform diagram of the corresponding POR signal voltage.

When the voltage of the power supply VDD raises to 2.807V of the upper threshold level, the circuit generates the POR signal; when the voltage of the power supply VDD decreases to 1.567V of the lower threshold level, the POR signal immediately decreases to 0, which significantly improves the anti-interference capacity of the power supply voltage VDD.

As shown inFIG. 8, even if fluctuation of the power supply voltage VDD is 30%, a false triggering of the POR signal will not be generated.

For the above power on reset circuit, the current bias circuit provides three reference currents not varying with the power supply to the threshold level control circuit and the capacitor charge and discharge circuit. Such threshold level control circuit generates accurate threshold level values by reference currents provided by the current bias circuit; the capacitor charge and discharge circuit enables the capacitor charge and discharge times to be calculated accurately by reference currents provided by the current bias circuit; in the case whether the power supply performs a quick power on operation or a slow power on operation, the capacitor charge and discharge circuit can generate a stable power on reset signal.