Selective deposition and planarization for a CMOS image sensor

The present application relates to a method to simplify the scribe line opening filling processes, and to further improve the surface uniformity of the conductive pad fabrication process. A passivation layer is formed over a semiconductor substrate, and a scribe line opening is formed through the passivation layer and the semiconductor substrate. To fill the scribe line opening, a first dielectric layer is formed within the scribe line opening over the conductive pad and extending over the passivation layer. The first dielectric layer is formed by a selective deposition process such that the first dielectric layer is formed on the conductive pad at a deposition rate greater than that formed on the passivation layer.

BACKGROUND

Many modern day electronic devices include optical imaging devices (e.g., digital cameras) that use image sensors. Image sensors convert optical images to digital data that may represent the images. An image sensor may include an array of pixel sensors and supporting logic. The pixel sensors measure incident radiation (e.g., light), and the supporting logic facilitates readout of the measurements. One type of image sensor commonly used in optical imaging devices is a back-side illumination (BSI) complementary metal-oxide-semiconductor (CMOS) image sensor. BSI CMOS image sensors advantageously have low operating voltage, low power consumption, high quantum efficiency, low read-out noise, and allow random access.

DETAILED DESCRIPTION

Some complementary metal-oxide-semiconductor (CMOS) image sensors include an array of pixels sensors arranged within a semiconductor substrate of an integrated circuit (IC). An array of color filters is arranged over the pixel sensor array and buried within a light-receiving side of the IC. Burying the color filter array within the integrated circuit advantageously improves the optical performance of the image sensors. For example, one or more of cross talk, quantum efficiency, and SNR-X (i.e., minimum luminance to achieve a signal-to-noise ratio (SNR) of X, such as 10) may be improved. While burying the color filter array provides improved optical performance, integrating the buried color filter array (BCFA) process with existing CMOS image sensor processes during manufacture poses challenges. For example, a conductive pad is formed in a scribe line opening on the light-receiving side of the IC before forming the BCFA. The scribe line opening creates discontinuities on the surface of the light-receiving side of the IC. A limitation of the BCFA process is that it is dependent upon the light-receiving side of the IC having a surface that is substantially planar. Failure to have a substantially planar surface may negatively affect optical performance. To form a planar surface for the BCFA process, a series of dielectric layers are deposited over the conductive pad to fill the scribe line opening. These dielectric layers may be produced through a series of deposition and etching processes such as un-doped silicate glass (USG) deposition processes, high density plasma (HDP) sputtering processes, and resist protective oxide (RPO) deposition processes. Besides the plasma damage introduced by some of these deposition and etching processes, the depth of the scribe line opening may introduce a high aspect ratio for subsequent planarization processes. An additional photolithography process may be needed to remove or at least lower the heights of the filling dielectric layers outside of the scribe line opening. Further etching processes may also be needed before performing the BCFA process.

The present application relates to a method for integrating a conductive pad process with a BCFA process during the manufacture of an image sensor. The method simplifies the scribe line opening filling processes, eliminates damage caused by the deposition and etching processes, and further improves the surface uniformity of the conductive pad structure and associated semiconductor devices. In some embodiments, a passivation layer is formed over a semiconductor substrate and a scribe line opening is formed through the passivation layer and the semiconductor substrate. Then, a conductive pad is formed within the scribe line opening which electrically contacts a metal line of a BEOL metallization stack. To fill the scribe line opening, a first dielectric layer is formed within the scribe line opening over the conductive pad and extending over the passivation layer. The first dielectric layer is formed by a selective deposition process. The first dielectric layer is formed on the conductive pad at a deposition rate greater than that formed on the passivation layer. By utilizing the selective deposition process to fill the scribe line opening after forming the conductive pad structure, the deposition and planarization process is simplified since the selective filling process reduces the aspect ratio of the first dielectric layer before being planarized. Further, the surface uniformity is improved for subsequent BCFA formation and optical performance is advantageously improved as well.

With reference toFIG. 1, a cross-sectional view100of some embodiments of an integrated chip having a conductive pad structure is provided. The conductive pad structure includes a BEOL metallization stack102. The BEOL metallization stack102includes metal lines (e.g.106,108) electrically coupled to one another by vias112and stacked within an interlayer dielectric (ILD) layer104. The ILD layer104may be, for example, a low κ dielectric (i.e., a dielectric with a dielectric constant less than about 3.9) or an oxide. The metal lines include an upper metallization layer110. The metal lines106,108and the vias112may comprise a metal material such as aluminum copper, aluminum, germanium, copper, tungsten or some other metal. A semiconductor substrate114and an isolation region116are arranged over the BEOL metallization stack102. In some embodiments, the isolation region116abuts an upper surface118of the BEOL metallization stack102, and extends vertically therefrom into the semiconductor substrate114. The semiconductor substrate114may be, for example, a bulk semiconductor substrate such as a bulk silicon substrate, or a silicon-on-insulator (SOI) substrate. The isolation region116may be, for example, a shallow trench isolation (STI) region or an implant isolation region. A passivation layer148is disposed over the semiconductor substrate114. Though shown inFIG. 1as a single layer, the passivation layer148may be, for example, a single or multilayer dielectric film including one or more layers of an oxide such as silicon dioxide, a nitride such as silicon nitride, or a high-k dielectric (i.e., dielectric with a dielectric constant greater than about 3.9). In some embodiments, the passivation layer148includes a nitride layer arranged over a pair of oxide layers, which are stacked on opposing sides of a high-k dielectric layer (as shown and described below inFIG. 2). In other embodiments, the passivation layer148includes a nitride layer arranged over an oxide layer.

A scribe line opening120is disposed through the passivation layer148, the semiconductor substrate114, and the isolation region116. A conductive pad128is disposed within the scribe line opening120. In some embodiments, the conductive pad128includes a base region130and a protruding region132underlying the base region130. The base region130is disposed on the isolation region116, and has sidewall surfaces laterally spaced from neighboring sidewall surfaces of the semiconductor substrate114. In some embodiments, the base region130has a substantially uniform thickness. Further, in some embodiments, the base region130may have a portion of an upper surface142recessed below an upper surface124of the isolation region116. The protruding region132protrudes through a pair of line-shaped openings138in the isolation region116and the ILD layer104, to the upper metallization layer110of the metal line106. The pair of line-shaped openings138are laterally spaced apart and extend axially in parallel along a periphery of the base region130. The conductive pad128may comprise, for example, a metal, such as aluminum copper.

A first dielectric layer144is arranged over the conductive pad128, and fills the scribe line opening120. In some embodiments, the first dielectric layer144may have a substantially planar upper surface including a lightly concave upper surface134directly above the conductive pad. The first dielectric layer144may extend over the passivation layer148having a planar upper surface136directly above the passivation layer148and connected to the concave upper surface134. In some embodiments, the concave upper surface134is recessed below an upper surface126of the passivation layer148, but above an upper surface122of the semiconductor substrate114. In some embodiments, a second dielectric layer146is disposed on the concave upper surface134of the first dielectric layer144, and may have an upper surface150being substantially aligned with the planar upper surface136of the first dielectric layer144directly above the passivation layer148. In some embodiments, the first dielectric layer144and the second dielectric layer146may comprise the same or different dielectric materials, such as an oxide material. In some embodiments, as a result of forming techniques as described in following paragraphs, the first dielectric layer144may comprise an atomic percentage of silicon of from about 40% to about 50%, an atomic percentage of oxygen of from about 50% to about 60%, and an atomic percentage of nitrogen of about 0.2%. Previous filling techniques may result in a different atomic percentage rate of silicon, oxygen and nitrogen. In some embodiments, the first dielectric layer144comprises no carbon residue. In some embodiments, the second dielectric layer146comprises an un-doped silicate glass (USG) material.

With reference toFIG. 2, a cross-sectional view200of some embodiments of an integrated chip having a conductive pad structure is provided. As a non-limiting example, in some embodiments, a buffer layer212lines a scribe line opening120, and supports a conductive pad128underneath a peripheral region and a central region of the conductive pad128. The buffer layer212may include a first region lining a recessed surface of the scribe line opening120directly under the conductive pad128, a second region lining sidewall surfaces of the scribe line opening120, and a third region lining a lateral surface of the scribe line opening120between the first and second regions. The buffer layer212may be, for example, a dielectric such as silicon dioxide or some other oxide. In some embodiments, a first dielectric layer144and/or a second dielectric layer146may have upper surfaces being slightly concave or substantially planar. A passivation layer148disposed over a semiconductor substrate114may includes a first oxide layer202arranged over the semiconductor substrate114, a high-k dielectric layer204arranged over the first oxide layer202, a second oxide layer206arranged over the high-k dielectric layer204, and a nitride layer208arranged over the second oxide layer206. The first and second oxide layers202and206may be, for example, silicon dioxide. The high-k dielectric layer204may be, for example, hafnium oxide (HfO), hafnium silicon oxide (HfSiO), hafnium aluminum oxide (HfAlO), or hafnium tantalum oxide (HMO). The nitride layer208may be, for example, silicon nitride. A metal connect layer210is arranged over the passivation layer148, the first dielectric layer144, and/or the second dielectric layer146, and fills a pad opening218. The metal connect layer210may be a metal, such as, for example, copper or aluminum copper. Further, the metal connect layer210may be conformal or have a recessed upper surface214lower than upper surfaces122,126or136of the semiconductor substrate114, the passivation layer148or the dielectric layers144and146.

With reference toFIG. 3, a cross-sectional view300of some embodiments of a back-side illuminated (BSI) image sensor within which the conductive pad structure finds application is provided. The BSI image sensor includes a sensing region302, an interconnect region304, and a logic region306. The sensing region302is configured to sense incident radiation. The interconnect region304laterally surrounds the sensing region302along an edge of the BSI image sensor, and includes conductive pad structures ofFIG. 1 or 2(illustrated withFIG. 2). The conductive pad structures are laterally spaced around the sensing region302, and are configured to connect the BSI image sensor to external devices. The logic region306may laterally surround the sensing region302between the sensing region302and the interconnect region304, and includes logic devices (not shown) configured to support the operation of the BSI image sensor.

The sensing, interconnect, and logic regions302,304,306are arranged within a carrier substrate308and an IC310. The carrier substrate308may be, for example, a bulk semiconductor substrate, such as a bulk silicon substrate, or a SOI substrate. The IC310is arranged over the carrier substrate308and is bonded or attached by other techniques to the carrier substrate308through a front side312of the IC310. The IC310includes a device region314arranged between a semiconductor substrate114and a BEOL metallization stack102. The BEOL metallization stack102is arranged along the front side312of the IC310, and includes an ILD layer104and metal lines106and108stacked within the ILD layer104. Contacts320electrically couple the device region314to the metal lines106and108, and vias112electrically couple the metal lines106and108to one another. The device region314includes electronic components, such as, for example, one or more of transistors, capacitors, resistors, inductors, photodetectors, and photodiodes. Within the sensing region302, the device region314typically includes an array of pixel sensors316, such as photodetectors and/or photodiodes. Within the logic region306, the device region314typically includes transistors (not shown).

The passivation layer148lines an upper surface of the semiconductor substrate114and is not extended into a scribe line opening120. The first and second dielectric layers144and146fill in the scribe line opening120. Although not visible, the scribe line opening120may extend to have a footprint laterally surrounds the sensing region302. In some embodiments, a conductive pad128is disposed within the scribe line opening120. The conductive pad128may be coupled to a metal connect layer (not shown) disposed within a pad opening218through the first and second dielectric layers144and146. A color filter array322is buried within a passivation layer148and/or other dielectric layers (e.g. first and second dielectric layers144,146) within the sensing region302along a backside318of the semiconductor substrate114and opposed to the BEOL metallization stack102. The color filter array322corresponds to the pixel sensors316and is assigned corresponding colors or wavelengths of radiation (e.g., light). Further, the color filter array322is configured to transmit the assigned colors or wavelengths of radiation to the corresponding pixel sensors316. Typically, the color filter assignments alternate between red, green, and blue. In some embodiments, the color filter assignments alternative between red, green, and blue light of a Bayer mosaic. An array of microlenses324is arranged over the color filter array322and the pixel sensors316. The microlenses324have centers that are typically aligned with centers of the color filter array322and/or centers of the pixel sensors316. The microlenses324are configured to focus incident radiation towards the pixel sensors316and/or the color filter array322. In some embodiments, the microlenses324have convex upper surfaces configured to focus radiation towards the pixel sensors316and/or the color filter array322.

FIGS. 4-15illustrate a series of cross-sectional view showing some embodiments of an integrated chip having a conductive pad structure at various stages of manufacture.

As shown in cross-sectional view400ofFIG. 4, a semiconductor substrate114is arranged over an isolation region116and a BEOL metallization stack102. The semiconductor substrate114may comprise any type of semiconductor body (e.g., silicon/CMOS bulk, SiGe, SOI, etc.) such as a semiconductor wafer or one or more die on a wafer, as well as any other type of semiconductor and/or epitaxial layers formed thereon and/or otherwise associated therewith. In some embodiments, a plurality of semiconductor devices can be formed within and/or over the semiconductor substrate114. The isolation region116may be, for example, an STI region. The BEOL metallization stack102includes metal lines106,108stacked within an ILD layer104and electrically coupled to one another by vias112. The ILD layer104may be, for example, a low κ dielectric or an oxide. The metal lines106,108and the vias112may be, for example, a metal. In some embodiments, the isolation region116is deposited along a back side of the semiconductor substrate114. The BEOL metallization stack102is then formed over the isolation region116and the semiconductor substrate114by forming trench and via openings within the ILD layer104, which is selectively exposed to an etchant (e.g., CF4, CHF3, C4F8, HF, etc.) that etches the ILD layer104, followed by filling a conductive metal material such as copper, aluminum, tungsten, etc. into the trench and via openings. In some embodiments, a chemical mechanical polishing (CMP) process may be used to remove excess of the metal material from an upper surface of the ILD layer104. The semiconductor substrate114is then flipped over for following processes.

As shown in cross-sectional view500ofFIG. 5, a passivation layer148is formed along a front side of the semiconductor substrate114opposed to the BEOL metallization stack102. The passivation layer148may be formed as, for example, a single or multilayer dielectric film including one or more layers of oxide, nitride, and high-k dielectric. The one or more layers may be formed by sequentially depositing the layers using vapor deposition, thermal oxidation, spin coating, or any other suitable deposition technique.

As shown in cross-sectional view600ofFIG. 6, an etch process is performed into the passivation layer148and the semiconductor substrate114, through a select region overlying an upper metallization layer110, to the isolation region116(seeFIG. 6). In some embodiments, due to over etching, the isolation region116may be eroded under the select region. The etch process results in a scribe line opening120overlying the upper metallization layer110. The process for performing the etch process may include forming a photoresist layer masking regions of the semiconductor substrate114laterally surrounding the select region. Then, a first etchant602may be applied to the semiconductor substrate114of a pattern of the photoresist layer502. Thereafter, the first photoresist layer may be removed. Though not shown inFIG. 6, in some embodiments, a buffer layer (e.g. the buffer layer212shown inFIG. 2) can be conformally formed and patterned after forming the scribe line opening120.

As shown in cross-sectional view700ofFIG. 7, an etch process is performed into the isolation region116and the ILD layer104, through select regions, to form an opening to expose the upper metallization layer110. The select regions are laterally spaced apart and extend axially in parallel along the periphery of the scribe line opening120. The process for performing the etch process may include forming a second photoresist layer702masking regions of the isolation region116laterally surrounding the select regions. Further, one or more second etchants704may be applied to the isolation region116and the ILD layer104of a pattern of the second photoresist layer702. Thereafter, the second photoresist layer702may be removed.

As shown in cross-sectional view800ofFIG. 8, a conductive pad layer128′ is formed over the isolation region116, fully filling the opening formed by the etch process ofFIG. 7and partially filling the scribe line opening120. The conductive pad layer128′ may be formed of, for example, a metal, such as aluminum copper, copper, aluminum, or some other metal. In some embodiments, the conductive pad layer128′ may be formed using a plating process (e.g., an electro-plating process or an electro-less plating process) or a deposition process (e.g., chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), etc.), followed by an etch back process.

As shown in cross-sectional view900ofFIG. 9, an etch process may be performed into the conductive pad layer128′ (shown inFIG. 8) to form a conductive pad128. The etch process results in the conductive pad128having sidewall surfaces laterally spaced from neighboring sidewall surfaces of the semiconductor substrate114. Further, the conductive pad128has a pair of openings including recessed upper surfaces. The process for performing the etch process may include forming a third photoresist layer902masking regions of the conductive pad layer128′ laterally surrounding the select regions. Further, a third etchant904may be applied to the conductive pad layer128′ of a pattern of the third photoresist layer902. Thereafter, the third photoresist layer902may be removed.

As shown in cross-sectional view1000ofFIG. 10, a first dielectric layer144is formed over the passivation layer148, the isolation region116and the conductive pad128, and fills a remaining portion of the scribe line opening120. The first dielectric layer144is formed by a selective deposition process. The first dielectric layer144is formed on the conductive pad128at a deposition rate greater than that formed on the passivation layer148. In some embodiments, the first dielectric layer144is deposited on the conductive pad128and the semiconductor substrate114at deposition rates that are four times or greater than deposited on the passivation layer. In some embodiments, the first dielectric layer is formed by coating a spin on oxide material. For example, a PHPS (Per Hydro Poly Silazane) polymer is formed within the scribe line opening120(carried by a solvent) and then oxidized to form the first dielectric layer144. In some other embodiments, the first dielectric layer is formed by a sub-atmospheric chemical vapor deposition (SACVD) process. As a result, the scribe line opening120is filled seamlessly without raising a significant dielectric height outside the scribe line opening120, which would help a planarization process to be performed. In some embodiments, the selective deposition process is followed by an annealing process that derives Silane (SiH4), Ammonia (NH3) and hydrogen (H2) gases. The first dielectric layer144may be formed as, for example, an oxide, such as silicon dioxide, or some other dielectric.

As shown in cross-sectional view1100ofFIG. 11, a second dielectric layer146may be formed by depositing an un-doped silicate glass (USG) material on the first dielectric layer144. The second dielectric layer146can be formed by a deposition process (e.g., chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), etc.).

As shown in cross-sectional view1200ofFIG. 12, the second dielectric layer146is planarized by a planarization process, such as a chemical mechanical polishing (CMP) process, to remove an upper portion of the USG material. In some embodiments, a planar upper surface of the second dielectric layer146is achieved across the scribe line and peripheral regions as shown inFIG. 12. In some alternative embodiments not shown byFIG. 12, the second dielectric layer146overlying the passivation layer148is substantially removed such that only a portion of the second dielectric layer146lower than an upper surface of the passivation layer148is left, such as directly on a concave upper surface of the first dielectric layer144. In this case, an upper surface of the second dielectric layer146is substantially aligned with an upper surface of the first dielectric layer144directly above the passivation layer148.

As shown in cross-sectional view1300ofFIG. 13, a wet etch process is preformed into the second dielectric layer146and/or the first dielectric layer144to clean the work piece surfaces and to further etch back an upper surface of the first and/or second dielectric layers144and146to be substantially planar.

As shown in cross-sectional view1400ofFIG. 14, an etch process is performed into the first dielectric layer144and the second dielectric layer146through select regions overlying the conductive pad128. In some embodiments, due to over etching, the conductive pad128may be eroded under the select regions. The etch process results in a pad opening218overlying and exposing the conductive pad128. The process for performing the etch process may include forming a fourth photoresist layer1402by masking regions of the first dielectric layer144and the second dielectric layer146laterally surrounding the select regions. Further, a fifth etchant1404may be applied to the first dielectric layer144and the second dielectric layer146of a pattern of the fourth photoresist layer1402. Thereafter, the fourth photoresist layer1402may be removed.

As shown in cross-sectional view1500ofFIG. 15, a metal connect layer1502is formed over the first dielectric layer144and the second dielectric layer146and filling the pad opening218. The metal connect layer1502may be formed of, for example, a metal, such as copper or aluminum copper. Further, the metal connect layer1502may be formed using, for example, vapor deposition, spin coating, or any other suitable deposition technique. In some embodiments, the metal connect layer1502can be formed conformally. (not shown).

FIG. 16illustrates some embodiments of a method1600for manufacturing an integrated chip having a conductive pad structure. Although method1600is described in relation toFIGS. 4-15, it will be appreciated that the method1600is not limited to such structures disclosed inFIGS. 4-15, but instead may stand alone independent of the structures disclosed inFIGS. 4-15. Similarly, it will be appreciated that the structures disclosed inFIGS. 4-15are not limited to the method1600, but instead may stand alone as structures independent of the method1600. Also, while the disclosed methods (e.g., method1600) are illustrated and described below as a series of acts or events, it will be appreciated that the illustrated ordering of such acts or events are not to be interpreted in a limiting sense. For example, some acts may occur in different orders and/or concurrently with other acts or events apart from those illustrated and/or described herein. In addition, not all illustrated acts may be required to implement one or more aspects or embodiments of the description herein. Further, one or more of the acts depicted herein may be carried out in one or more separate acts and/or phases.

At1602, a passivation layer is formed over a semiconductor substrate. In some embodiments, an isolation region is deposited along a back side of the semiconductor substrate. A BEOL metallization stack is formed over the semiconductor substrate. The semiconductor substrate is then flipped over, and a passivation layer is formed along a front side of the semiconductor substrate opposing to the BEOL metallization stack. The passivation layer may be formed as, for example, a single or multilayer dielectric film including one or more layers of oxide, nitride, and high-k dielectric.FIGS. 4-5illustrate some embodiments of cross-sectional views400and500corresponding to act1602.

At1604, a scribe line opening is formed through the passivation layer and the semiconductor substrate overlying a metal line. In some embodiments, an etch process is performed into the passivation layer and the semiconductor substrate to form the scribe line opening overlying a metal line. Then, a second etch process is performed into the isolation region and the ILD layer to form an opening to expose the metal line.FIGS. 6-7illustrate some embodiments of cross-sectional views600and700corresponding to act1604.

At1606, a conductive pad is formed in the scribe line opening. In some embodiments, a conductive pad layer is formed over the isolation region, fully filling the opening formed by the second etch process and partially filling the scribe line opening. The conductive pad layer is then patterned to form a conductive pad. The etch process results in the conductive pad having sidewall surfaces laterally spaced from neighboring sidewall surfaces of the semiconductor substrate. Further, the conductive pad may have a pair of openings including recessed upper surfaces.FIGS. 8-9illustrate some embodiments of cross-sectional views800and900corresponding to act1606.

At1608, a first dielectric layer is formed over the conductive pad and fills the scribe line opening over the passivation layer. In some embodiments, the first dielectric layer is formed over the passivation layer, the isolation region and the conductive pad and fills a remaining portion of the scribe line opening. The first dielectric layer is formed by a selective deposition process. The first dielectric layer is formed on the conductive pad at a deposition rate greater than that formed on the passivation layer.FIG. 10illustrates some embodiments of a cross-sectional view1000corresponding to act1608.

At1610, a second dielectric layer is formed over the first dielectric layer and extends over the passivation layer. In some embodiments, the second dielectric layer may be formed by depositing an un-doped silicate glass (USG) material on the first dielectric layer.FIG. 11illustrates some embodiments of a cross-sectional view1100corresponding to act1610.

At1612, the second dielectric layer is planarized. In some embodiments, the second dielectric layer is planarized by a planarization process, such as a chemical mechanical polishing (CMP) process, to remove an upper portion of the second dielectric material. In some embodiments, a planar upper surface of the second dielectric layer is achieved across the scribe line region and the peripheral regions. In some alternative embodiments, the second dielectric layer overlying the passivation layer is substantially removed such that only a portion of the second dielectric layer lower than an upper surface of the passivation layer is left, such as directly on a concave upper surface of the first dielectric layer. A wet etch process is then preformed into the second dielectric layer and/or the first dielectric layer to clean the work piece surfaces and to further etch back an upper surface of the first and/or second dielectric layers to be substantially planar.FIGS. 12-13illustrate some embodiments of cross-sectional views1200and1300corresponding to act1612.

At1614, a metal connect layer is formed lining the pad opening directly above the conductive pad. In some embodiments, an etch process is performed into the first dielectric layer and the second dielectric layer to expose the conductive pad. A metal connect layer is formed over the first dielectric layer and the second dielectric layer and filling in the pad opening218.FIGS. 14-15illustrate some embodiments of cross-sectional views1400and1500corresponding to act1614.

As can be appreciated from the description above, the present disclosure provides a method for integrating a conductive pad process with a BCFA process during the manufacture of an image sensor. The method comprises forming a passivation layer over a semiconductor substrate on a light-receiving side of the contact image sensor and forming a scribe line opening through the passivation layer and the semiconductor substrate. The scribe line opening overlies and exposes a metal line of a back end of line (BEOL) metallization stack. The method further comprises forming a conductive pad within the scribe line opening, which electrically contacts the BEOL metallization stack, and forming a first dielectric layer within the scribe line opening over the conductive pad and extending over the passivation layer. The first dielectric layer is formed by a selective deposition process such that the first dielectric layer is formed on the conductive pad at a deposition rate greater than formed on the passivation layer.

In other embodiments, the present disclosure relates to a conductive pad structure of an image sensor device. The conductive pad structure comprises a semiconductor substrate arranged over a back end of line (BEOL) metallization stack and a passivation layer disposed over the semiconductor substrate. The conductive pad structure further comprises a scribe line opening disposed through the semiconductor substrate and the passivation layer and a conductive pad comprising a base region and a protruding region, the protruding region protruding from the base region into the BEOL metallization stack. The conductive pad structure further comprises a first dielectric layer filling the scribe line opening over the conductive pad, extending over the passivation layer, and having a concave upper surface directly above the conductive pad and a second dielectric layer disposed on the concave upper surface of the first dielectric layer, and having an upper surface being substantially aligned with an upper surface of the first dielectric layer directly above the passivation layer.

In yet other embodiments, the present disclosure provides a method for manufacturing a conductive pad structure of an image sensor device. The method comprises forming a passivation layer over a semiconductor substrate and forming a scribe line opening through the passivation layer and the semiconductor substrate. The scribe line opening overlies and exposes a metal line of a back end of line (BEOL) metallization stack. The method further comprises forming a conductive pad within the scribe line opening, which electrically contacts the BEOL metallization stack. The method further comprises forming a first dielectric layer within the scribe line opening over the conductive pad by a selective deposition process. The first dielectric layer is formed on the conductive pad at a deposition rate greater than the deposition rate on the passivation layer. The method further comprises forming a second dielectric layer on the first dielectric layer, performing a chemical mechanical polish (CMP) into the second dielectric layer, and performing a wet etch process into the second dielectric layer and/or the first dielectric layer to etch back an upper surface of the first and/or second dielectric layer to be substantially planar.