SEMICONDUCTOR DEVICE TRENCH TERMINATION STRUCTURE

A semiconductor device having a termination structure is provided that is useful for trench semiconductor devices, such as trench Schottky diodes. The device includes a termination structure having a primary termination trench including a first insulating layer arranged on a sidewall and bottom, and a first polysilicon region spaced apart from the sidewall and bottom by the first insulating layer; and a secondary termination trench arranged further away from the active region than the primary termination trench. The secondary termination trench includes a second insulating layer arranged on a sidewall and bottom, and polysilicon spacers separated from the sidewall and bottom by the second insulating layer. The polysilicon spacers are spaced apart and arranged on opposing ends of the secondary termination trench in an outward direction with respect to the active region, and a width of the primary termination trench is less than a width of the secondary termination trench.

CROSS REFERENCE TO RELATED APPLICATION

This application claims the benefit under 35 U.S.C. § 119(a) of European Application No. 21168358.6 filed Apr. 14, 2021, the contents of which are incorporated by reference herein in their entirety.

BACKGROUND OF THE DISCLOSURE

1. Field of the Disclosure

The present disclosure relates to a semiconductor device having a termination structure. More in particular, the present disclosure relates to a termination structure that is particularly useful for trench semiconductor devices, such as trench Schottky diodes.

2. Description of the Related Art

Semiconductor devices, such as transistors and diodes, may be subjected to relatively high voltages during operation. These semiconductor devices may be susceptible to breakdown events due to exceedingly high electric fields inside the semiconductor device due to said high voltages. In particular, breakdown can occur when a voltage applied to terminals of the semiconductor device exceeds a breakdown voltage of the device for an extended amount of time. During breakdown, the electric field may, at a position inside the device, exceed the critical electric field at that position. The value of the critical electric field depends on the material that is used. However, the resulting breakdown voltage of the device not only depends on the materials used but also on structural features of the semiconductor device. For example, metal electrodes having point like ends are more susceptible to result in premature electrical breakdown than electrodes having rounded or chamfered ends.

For some devices, the breakdown voltage can be increased through the use of trenches in the semiconductor body. This is illustrated inFIG. 1in which a planar Schottky diode1A is shown on the left, and a trench Schottky diode1B on the right. Each diode1A,1B comprises a bottom electrode2, an n+-doped silicon substrate3, an n-doped silicon drift region4, and a top electrode5. Trench Schottky diode1B additionally comprises a trench7of which a bottom and sidewall are covered by an insulating layer, such as an oxide8. Inside trench7, a polysilicon body9is arranged that is electrically isolated from drift region4by oxide8.

FIG. 1also schematically illustrates equipotential lines6during reverse operation. Regions in which the equipotential lines lie close together are regions in which the electric field is relatively high. As can be seen inFIG. 1, the equipotential lines in trench Schottky diode1B are more regularly distributed. More in particular, the electric field in the semiconductor region below contact5is less than in planar Schottky diode1A. It is noted that inside oxide8, high electric fields may exist. However, the critical electric field inside oxide8, e.g. approximately 10 MV per centimeter, is substantially higher than the critical electric field of silicon, e.g. approximately 0.3 MV per centimeter.

Typically, the semiconductor device comprises a plurality of unit cells that are regularly arranged. Within an inner region of this plurality of unit cells, the trenches are very effective in increasing the breakdown voltage. However, near the edges of the device symmetry is broken and the effectiveness of the trenches is reduced.

To address this problem, a termination structure can be included in the semiconductor device, in particular in semiconductor devices for high-voltage applications where breakdown can be a regular concern. The termination structure changes an electric field distribution inside the semiconductor device to thereby relieve critical regions of the semiconductor device at which breakdown typically occurs. In other words, the termination structure can be included to reduce electrical potential gradients in the semiconductor device similar to that shown inFIG. 1, especially at regions that are critical to the breakdown performance of the semiconductor device. Consequently, by including a termination structure in a semiconductor device, the breakdown voltage of the semiconductor device can be further improved.

A simplified top view of a semiconductor device100known in the art is shown inFIG. 2. In this figure, semiconductor device100is arranged in a semiconductor substrate having an active region110and a termination region130surrounding said active region110.

In active region110, one or more unit cells120of semiconductor device100can be arranged. Each unit cell120individually forms a portion of semiconductor device100, and all unit cells120combined form an active part of semiconductor device100. As shown inFIG. 2, unit cells120may for example be formed as parallel strips, or ‘fingers’, in active region110. However, the shape of unit cells120is not limited thereto. Unit cells120may also be formed in other shapes, such as a circular or hexagonal shape. Furthermore, the shape of each unit cell120need not be identical.

In termination region130, a termination structure140is provided to improve the breakdown voltage of semiconductor device100as explained above. Termination structure140in termination region130may, for example, laterally enclose unit cells120in active region110.

A cross-sectional view of a section of semiconductor device100is shown inFIG. 3. The cross-sectional view ofFIG. 3may, for example, correspond to a cross-section along line segment a-a′ as indicated inFIG. 2.

FIG. 3illustrates an example where semiconductor device100is a trench Schottky diode. More in particular, inFIG. 3, a unit cell120near an edge of active region110is shown. Unit cell120comprises a trench121arranged inside a semiconductor body101. An insulating layer122(e.g., an oxide material such as a thermal oxide) covers a sidewall and bottom of trench121. In addition, a polysilicon region123is arranged inside trench121, wherein polysilicon region123is separated from the sidewall and bottom of trench121by insulating layer122.

Furthermore, a Schottky metal layer103is arranged on top of semiconductor body101and trench121of unit cell120, thereby electrically contacting semiconductor body101as well as polysilicon region123. Since Schottky metal layer103is contacting semiconductor body101, a Schottky barrier is formed between said Schottky metal layer103and semiconductor body101. It should be noted that semiconductor body101may have a similar configuration as trench Schottky diode1B ofFIG. 1.

A contact metal104is arranged covering Schottky metal103to provide an external electrical contact to a terminal of the trench Schottky diode. Although not shown inFIG. 3, a second contact can be provided at a bottom of semiconductor body101to provide an external electrical contact to another terminal of the trench Schottky diode.

InFIG. 3, a dashed line is shown to indicate a border between active region110, in which unit cells120are arranged, and termination region130, in which termination structure140is arranged. As shown inFIG. 3, termination structure140comprises a termination trench141having a greater width with respect to trench121of unit cell120. An insulating layer142(e.g., an oxide material) covers a sidewall and bottom of termination trench141. Furthermore, termination trench141comprises polysilicon spacers143aand143bthat are not mutually connected but spaced apart and arranged at opposing ends inside termination trench141, in a direction outward from active region110. Polysilicon spacers143aand143bare spaced apart from a sidewall and bottom of termination trench141by insulating layer142. Polysilicon spacers143aand143bare formed by residual polysilicon material resulting from a polysilicon etching step in the manufacturing process, as will be explained further below. Furthermore, insulating layer142and insulating layer122may be identical layers formed during the same processing step.

Termination structure140further comprises another insulating layer102that covers a part of insulating layer142, polysilicon spacer143b,and partially covers polysilicon spacer143a.However, a portion of polysilicon spacer143ais left exposed by insulating layer102. Schottky metal103and contact metal104extend from active region110into termination region130, thereby at least partially covering termination trench141and being electrically connected to a portion of polysilicon spacer143athat is left exposed by insulating layer102.

Termination structure140is used to avoid high electric fields that typically occur in corner regions of termination trench141and in a region of the insulating layers near ends of contact metal104. By electrically connecting Schottky metal103and contact metal104to polysilicon spacer143a, the effective contacted region is brought closer to the active region near the corner regions of termination trench141through polysilicon spacer143a.Consequently, in reverse operation of semiconductor device100(e.g., the Schottky diode), said active region is more effectively depleted, which allows for a more favorable electric field distribution in the corner region of termination trench141. Furthermore, insulating layer102, which typically has a greater thickness than insulating layer142, is used to accommodate a high electric field occurring in termination trench141near ends of contact metal104.

In other words, by electrically contacting polysilicon143a, it is ensured that the electric field inside semiconductor device at critical regions near the edges of the plurality of unit cells in semiconductor device100is eased, thereby improving the breakdown voltage of semiconductor device100. Typically, insulating layer102has a greater thickness than insulating layer142to further isolate Schottky metal103and contact metal104from semiconductor body101inside trench141.

A manufacturing process of semiconductor device100is as follows. First, an epitaxial layer is grown on a semiconductor substrate, the semiconductor substrate and epitaxial layer together forming semiconductor body101. A trench mask is used to etch one or more trenches121, corresponding to unit cells120, and termination trench141, corresponding to termination structure140, into semiconductor body101, e.g. in the epitaxial layer. Termination trench141is made substantially wider than trench(es)121of unit cell(s)120to improve the breakdown voltage performance of semiconductor device100.

Following this, the aforementioned mask is removed, and an insulating layer, e.g. an oxide material, is thermally grown on semiconductor body101, as well as on the sidewalls and bottom of trench(es)121and termination trench141. On top of said insulating layer, a polysilicon material is deposited, implanted and diffused. Alternatively, a doped polysilicon material is deposited.

The polysilicon material is then etched back to form a polysilicon region123in trench121of unit cells120. However, due to the relatively large width of termination trench141(e.g., with respect to trench(es)121), the etch-back inside termination trench141will remove polysilicon only at the inner area of termination trench141and leave excess polysilicon material at its sidewalls. Consequently, after the etching step, trench(es)121will remain substantially filled with polysilicon material, thereby forming polysilicon region123, while only polysilicon spacers143aand143bremain as ‘residual’ polysilicon material in termination trench141. Then, an insulating layer102, e.g., an oxide material, is deposited.

After depositing insulating layer102, a contact mask is used to etch part of the deposited insulating layer in active region110to thereby expose semiconductor body101in between trenches121and in between trench121and trench141. Furthermore, part of polysilicon spacer143ais exposed. At this stage, the remaining parts of the thermally grown insulating layer respectively form insulating layer122in trench121and insulating layer142in termination trench141.

The above process is continued with a deposition, lithography and etching of Schottky metal103and contact metal104, thereby arriving at the device shown inFIG. 3. Although not shown inFIG. 3, the process may be complemented with providing a passivation layer covering semiconductor device100.

A problem associated with the termination structure shown inFIG. 3is that, in order to effectively improve the breakdown voltage of semiconductor device100, polysilicon spacer143amust be made sufficiently wide in order for contact metal104to reliably contact polysilicon spacer143a.Here, sufficiently wide means that a substantial electric field in a region in between trench121and termination trench141is prevented during normal operation for preventing breakdown performance from being adversely affected. To achieve this, the width of polysilicon spacer143ais approximately at least one fourth of the depth of the trench depth. Here, it is noted that the width of polysilicon spacer143aobtained after etching back the polysilicon material strongly depends on the amount of deposited polysilicon material prior to the etching step. In other words, the amount of deposited polysilicon material dictates the eventual width of polysilicon spacers143aand143b.However, depositing large amounts of polysilicon material has high associated costs and is therefore not desirable, in particular when considering that a substantial part of said polysilicon material is wasted in the etching process.

Additionally, after the polysilicon etching step, polysilicon spacers143aand143bwill have a slanted surface. As a result, a lithography step for Schottky metal layer103and contact metal layer104is significantly complicated due to the slanted surface and due to the relatively high resolution that is required. This may partially be alleviated by increasing the width of polysilicon spacer143a.However, doing so would again require more polysilicon material to be deposited initially, thereby resulting in higher associated manufacturing costs.

As described above, the termination structure shown inFIG. 3significantly complicates the manufacturing process of the semiconductor device. Therefore, there is a need for a termination structure design that can effectively improve the breakdown voltage of the semiconductor device while having a minimal impact on the complexity and costs associated with the manufacturing process thereof.

SUMMARY

It is an object of the present disclosure to provide a semiconductor device for which the abovementioned problems do not occur or hardly so.

This object is achieved by the semiconductor device according to claim1. The semiconductor device according to the present disclosure comprises a semiconductor body comprising an active region and a termination region laterally surrounding the active region. The semiconductor device further comprises a plurality of semiconductor device unit cells arranged in the active region, and a termination structure arranged in the termination region. Each semiconductor device unit cell comprises a unit cell trench having a unit cell insulating layer arranged on a sidewall and bottom thereof, and a unit cell polysilicon region spaced apart from the sidewall and bottom by the unit cell insulating layer.

The termination structure comprises a primary termination trench comprising a first insulating layer arranged on a sidewall and bottom thereof, and a first polysilicon region spaced apart from said sidewall and bottom by said first insulating layer. The termination structure additionally comprises a secondary termination trench arranged further away from the active region than the primary termination trench, wherein the secondary termination trench comprises a second insulating layer arranged on a sidewall and bottom thereof, and polysilicon spacers separated from said sidewall and bottom by said second insulating layer, wherein the polysilicon spacers are spaced apart and arranged on opposing ends of the secondary termination trench in an outward direction with respect to the active region. A width of the primary termination trench is less than a width of the secondary termination trench.

The semiconductor device further comprises a third insulating layer arranged to partially cover the primary termination trench and to at least partially cover the secondary termination trench. The semiconductor device further comprises a metal layer covering and contacting the semiconductor body between the unit cell trenches and the unit cell polysilicon region in the active region, covering and contacting the semiconductor body between the primary termination trench and adjacent unit cell trenches, partially covering and contacting the first polysilicon region, and at least partially covering the third insulating layer.

By including the primary termination trench, the need for contacting the polysilicon spacer in the secondary termination trench is eliminated. The width of these polysilicon spacers is therefore no longer a critical parameter, thereby enabling a reduction in the amount of polysilicon material that is deposited and etched during the manufacturing process of the semiconductor device.

In addition, it is sufficient for the metal layer to electrically contact the first polysilicon region in the primary termination trench to achieve the desired termination effect. In other words, the metal layer is no longer required to be electrically connected to the polysilicon spacer, and more in particular its inherently slanted surface, thereby easing the lithography step during the manufacturing process of the semiconductor device.

The primary termination trench and the secondary termination trench may be spaced apart at a distance at which a substantial electric field in a region of the semiconductor body in between said primary termination trench and secondary termination trench is prevented during normal operation. The Applicant has found that such a configuration improves the breakdown voltage performance of the semiconductor device.

The semiconductor body may comprise a semiconductor substrate and an epitaxial layer on top of the semiconductor substrate, wherein the unit cells and the termination structure are arranged in the epitaxial layer of the semiconductor body.

A depth of the unit cell trenches may be substantially equal to a depth of the primary termination trench and/or the secondary termination trench. Additionally or alternatively, a width of the unit cell trenches can be equal to or less than a width of the primary termination trench.

The plurality of unit cells may each and jointly form a trench Schottky diode, wherein the metal layer comprises a Schottky metal layer. The metal layer may further comprises a contact metal layer arranged on top of said Schottky metal layer. Typically, the contact metal layer is much thicker than the Schottky metal layer, for example at least 5 times thicker.

The Schottky metal layer may comprise one of iron, molybdenum, nickel, platinum, titanium, tungsten and alloys thereof. The contact metal layer may comprise one of aluminium, copper, gold, nickel, silver, titanium, tungsten, vanadium, zinc and alloys thereof. The semiconductor body may comprise an n+-doped substrate and an n-doped drift region on the substrate, or the semiconductor body may comprise a p+-doped substrate and a p-doped drift region on the substrate. In both cases, the unit trenches extend solely in the drift region.

The first insulating layer and the second insulating layer may have a substantially identical thickness, and/or the third insulating layer may have a greater thickness than the first insulating layer and/or the second insulating layer. Furthermore, a thickness of the unit cell insulating layer can be substantially equal to the thickness of the first insulating layer and/or the second insulating layer.

The metal layer may fully cover the termination structure. Alternatively, the metal layer may fully cover the primary termination trench and partially cover the secondary termination trench.

The semiconductor device may further comprise one or more further primary termination trenches, wherein each further primary termination trench is either arranged in between the primary termination trench and the secondary termination trench or is arranged further away from the active region than the secondary termination trench. The one or more further primary termination trenches may each comprise a fourth insulating layer arranged on a sidewall and bottom thereof, and a third polysilicon region spaced apart from said sidewall and bottom by said fourth insulating layer. Each of the one or more further primary termination trenches can preferably be substantially identical to the primary termination trench.

The third insulating layer may be further arranged to fully cover the further primary termination trench. Alternatively, a portion of the third insulating layer above the further primary termination trench is omitted such that the metal layer electrically contacts the fourth polysilicon region.

Hereinafter, reference will be made to the appended drawings. It should be noted that identical reference signs may be used to refer to identical or similar components.

DETAILED DESCRIPTION

InFIG. 4, a part of a cross-sectional view of a semiconductor device1according to the present disclosure is shown. In the example shown inFIG. 4, semiconductor device1is a trench Schottky diode.

Here, it is noted that the simplified top view shown inFIG. 2may also correspond to a top view of semiconductor device1. Hence, the cross-sectional view shown inFIG. 4may correspond to a cross-section taken along dotted line segment a-a′ as indicated in the top view ofFIG. 1.

Semiconductor device1comprises a semiconductor body2. InFIG. 4, a dashed line is shown that indicates a border between an active region10and a termination region30of semiconductor device1. A plurality of unit cells20, which form an active part of semiconductor device1, is arranged in active region10. Only one unit cell20is shown inFIG. 4.

Each of the plurality of unit cells20comprises a unit cell trench21arranged in semiconductor body2. A unit cell insulating layer22is arranged on a sidewall and bottom of unit cell trench21, and a unit cell polysilicon region23is arranged in unit cell trench21. More in particular, unit cell polysilicon region23is spaced apart from the sidewall and bottom of unit cell trench21by unit cell insulating layer22. The plurality of unit cells20may be functionally and structurally identical to one another, and together form a combined semiconductor device.

Active region10is covered by a metal layer comprising a Schottky metal layer3and a contact metal layer4covering said Schottky metal layer3. More in particular, the metal layer covers and contacts a top surface of semiconductor body2in between unit cell trenches21. As a result, a Schottky barrier is formed between Schottky metal layer3and semiconductor body2. Furthermore, the metal layer covers and is electrically connected to unit cell polysilicon region23. Contact metal layer4provides an electrical contact of semiconductor device1. Although not shown, another metal layer may be provided at a bottom surface of semiconductor body2to provide a further electrical contact to semiconductor device1.

Due to the electrical connection of the metal layer to semiconductor body2as well as unit cell polysilicon region(s)23, the plurality of unit cells20can each operate as a trench Schottky diode.

In termination region30, which laterally surrounds active region10, a termination structure40is arranged. Termination structure40comprises a primary termination trench41and a secondary termination trench44, wherein primary termination trench41is arranged closer to active region10than secondary termination trench44, and wherein a width of primary termination trench41is less than a width of secondary termination trench44.

Primary termination trench41comprises a first insulating layer42arranged on a sidewall and bottom thereof, and a first polysilicon region43spaced apart from said sidewall and bottom by said first insulating layer42. On the other hand, secondary termination trench44comprises a second insulating layer45arranged on a sidewall and bottom thereof, and polysilicon spacers46a,46bspaced apart from said sidewall and bottom by said second insulating layer45.

The isotropically deposited polysilicon material thickness is small in relation to the width of secondary termination trench44. As a consequence, after the polysilicon etching step, secondary termination trench44comprises residual polysilicon material in the form of polysilicon spacers46a,46bthat are spaced apart and positioned on opposing sides thereof, while the polysilicon material inside primary termination trench41, which forms first polysilicon region43, constitutes a single contiguous region, similar to unit cell polysilicon region23in unit cell trench21of the plurality of unit cells20.

Furthermore, contact metal layer4extends from active region10into termination region30and is electrically connected to first polysilicon region43of primary termination trench41in order to achieve the desired termination effect. Schottky metal layer3and contact metal layer4also cover and contact the upper surface of semiconductor body2between primary termination trench41and adjacent unit cell trench21. More in particular, first insulating layer42, unit cell insulating layer22, and second insulating layer45may be formed during the same processing step and may therefore be considered as different parts of a primary oxide layer. At the upper surface of semiconductor body2between primary termination trench41and adjacent unit cell trench21, this primary oxide layer is removed before depositing the Schottky metal layer3.

Since the metal layer is no longer required to contact polysilicon spacer46a,said polysilicon spacer46acan be left at a floating potential. This enables depositing and etching less polysilicon material during the manufacturing process, since the width of polysilicon spacer46ais no longer relevant. Additionally, a lithography step need not be performed on a slanted surface and does not require the same resolution as the lithography of the semiconductor device ofFIG. 3.

Semiconductor device1further comprises a third insulating layer5that partially covers primary termination trench41and that at least partially covers secondary termination trench44and extend above a part of the abovementioned primary oxide. This insulating layer5may be formed using deposition. InFIG. 4, third insulating layer5extends partially across the width of secondary termination trench44. However, other embodiments in which third insulating layer5extends across the entire width of secondary termination trench44are also envisaged. Third insulating layer5provides further isolation of the metal layer from semiconductor body2outside of active region10, and may have a greater thickness than first insulating layer42and second insulating layer44.

InFIG. 4, the metal layer, i.e., Schottky metal layer3and contact metal layer4, extends partially across secondary termination trench44. However, the present disclosure is not limited thereto. The metal layer could also cover the entire width of secondary termination trench44.

A depth of primary termination trench41may be identical to a depth of secondary termination trench44. Furthermore, a depth of unit cell trench21of unit cell20may also be identical to the depth of primary termination trench41and/or secondary termination trench44.

In order to achieve an improved breakdown voltage performance, primary termination trench41and secondary termination trench44are preferably spaced apart by a specific distance range. More in particular, a distance between primary termination trench41and secondary termination trench44may be such that, in operation, a substantial electric field within the region between primary termination trench41and secondary termination trench44is prevented or limited under normal operating conditions.

InFIG. 5, a cross-sectional view of an exemplary termination structure40according to another embodiment of the present disclosure is shown. For convenience, Schottky metal layer3and contact metal layer4are omitted fromFIG. 5.

FIG. 5shows a termination structure40comprising primary termination trench41, secondary termination trench44and additionally comprising a further primary termination trench47arranged in between said primary and secondary termination trench41,44. Further primary termination trench47comprises a fourth insulating layer arranged on a sidewall and bottom thereof, and a third polysilicon region spaced apart from said sidewall and bottom by said fourth insulating layer.

Further primary termination trench47may have similar or identical dimensions with respect to primary termination trench41. However, the present disclosure is not limited thereto. Further primary termination trench47may also be wider or narrower than primary termination trench41.

Although further primary termination trench47is shown as being positioned in between primary and secondary termination trench41,44inFIG. 5, it may also be arranged further away from active area10with respect to secondary termination trench44.

Furthermore, in some embodiments, termination structure may comprise a plurality of further primary termination trenches47. Each further primary termination trench47may be arranged in between primary and secondary termination trench41,44and/or may be arranged further away from active area10with respect to secondary termination trench44. As shown inFIG. 5, insulating layer5covers the entire width of further primary termination trench47. However, this need not be the case. In some embodiments, a portion of third insulating layer5may be omitted, for example by forming a through hole48, such that Schottky metal layer3can electrically contact the fourth polysilicon region of further primary termination trench47.

Next, a method of manufacturing semiconductor device1will be explained. First, an epitaxial layer is grown on a semiconductor substrate, the semiconductor substrate and epitaxial layer together forming semiconductor body2. For example, semiconductor body2could be a silicon body. A trench mask is used to etch a plurality of unit cell trenches21, corresponding to unit cells20, and to etch a primary termination trench41and a secondary termination trench44, corresponding to termination structure40, into semiconductor body2, e.g. in the epitaxial layer. If applicable, further primary trench47may be formed as well during this step.

Following this, the aforementioned mask is removed, and an insulating layer, e.g. an oxide material, is thermally grown on semiconductor body2, as well as on the sidewalls and bottom of trenches21,41,44and, if applicable, further primary trench47. On top of said insulating layer, a polysilicon material is deposited, implanted and diffused.

The polysilicon material is then etched back to form a unit cell polysilicon region23in trench21of unit cells20and, if applicable, the third polysilicon region in further primary trench47. However, the isotropically deposited polysilicon material thickness is small in relation to the width of secondary termination trench44. Consequently, after the etching step, trenches21,41will remain substantially filled with polysilicon material, thereby forming unit cell polysilicon region23, and first polysilicon region43, while only polysilicon spacers46aand46bremain as ‘residual’ polysilicon material in secondary termination trench41.

After etching back the polysilicon material, the thermal oxide layer corresponding to layers22,42, and44, will be etched inside the active region to expose the upper surface of semiconductor2between adjacent unit cell trenches21. Simultaneously, the upper surface of semiconductor body2between primary termination trench41and adjacent unit cell trench21will be exposed, whereas the remaining upper surface of semiconductor body2inside termination region30will not be exposed.

Then, an oxide layer5is deposited. A contact mask and subsequent etch is then used to etch part of deposited oxide layer5. As a result, oxide layer5completely covers the secondary termination trench44and the primary oxide in between primary termination trench41and secondary termination trench44. Oxide layer5partially covers primary termination trench41but does not cover the active region20.

The above process is continued with a deposition, lithography and etching of Schottky metal3and contact metal4, thereby arriving at the device shown inFIG. 4. Although not shown inFIG. 4, the process may be complemented with providing a passivation layer covering semiconductor device1.

In the above, the present disclosure has been explained using detailed embodiments thereof. However, it should be appreciated that the disclosure is not limited to these embodiments and that various modifications are possible without deviating from the scope of the present disclosure as defined by the appended claims.