Power-on detector, and power-on reset circuit using the same

A power-on detector includes a reference potential generation circuit which generates a reference potential, and a comparator which compares the first voltage generated on the basis of the reference potential output from the reference potential generation circuit and the potential of the first potential supply source, and the second voltage generated on the basis of the reference potential and the potential of the second potential supply source different from the potential of the first potential supply source. Power-on is detected when the potential difference between the potentials of the first and second potential supply sources upon power-on becomes larger than the sum of the first and second voltages.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2003-096691, filed Mar. 31, 2003, the entire contents of which are incorporated herein by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a power-on detector which detects power-on in a semiconductor integrated circuit device or the like, and a power-on reset circuit which initializes a register or latch circuit upon power-on.

2. Description of the Related Art

A conventional power-on detector is constituted by series-connecting a resistor and a diode or diode-connected transistor, and connecting the connection node to the input terminal of an inverter. The power-on detector generates a power-on detection signal by utilizing the fact that an output from the inverter is inverted as the power supply voltage rises upon power-on.

FIG. 1is a circuit diagram showing an arrangement example of such conventional power-on detector. The source of a p-channel MOS transistor11is connected to a power supply VDD, and the drain and gate are connected to one terminal of a resistor12. The other terminal of the resistor12is connected to ground VSS. The connection node between the drain of the MOS transistor11and one terminal of the resistor12is connected to the input terminal of a CMOS inverter15comprised of a p-channel MOS transistor13and n-channel MOS transistor14. A power-on detection signal PDS is output from the output terminal of the CMOS inverter15.

In this arrangement, when the semiconductor integrated circuit device is powered on, the potential of the power supply VDDincreases. When the potential of the power supply VDDreaches a circuit operable level, the potential at the connection node between the diode-connected MOS transistor11and resistor12becomes higher than the circuit threshold voltage of the CMOS inverter15. As a result, the output voltage (power-on detection signal PDS) of the CMOS inverter15changes to low level (“L” level). The potential of the power supply VDDfurther increases. When the potential at the connection node between the MOS transistor11and the resistor12becomes lower than the circuit threshold voltage of the CMOS inverter15, the output voltage of the CMOS inverter15is inverted to high level (“H” level), and power-on is detected.

The power-on detection level can be controlled by adjusting the resistance value of the resistor12or the channel length/channel width ratio (L/W) of each of the MOS transistors11,13, and14.

A technique of detecting power-on by the output signal PDS from the CMOS inverter15via a noise-cut low-pass filter (LPF) has also been known. The use of the low-pass filter can enhance noise resistance.

In the above-mentioned arrangement, however, the power-on detection level varies upon a change in temperature condition or variations in manufacturing process. This may result in a defective chip. For example, an onboard semiconductor integrated circuit device must normally operate within a wide temperature range of −40° C. to +125° C. A great change in temperature condition changes the threshold voltages of the MOS transistors11,13, and14. The level at which the power-on detection signal PDS is inverted greatly varies. The resistor12is generally a diffused resistor. The resistance value of the diffused resistor readily varies upon variations in manufacturing process. Such variations cannot be fully coped with by adjusting the resistance value of the resistor12or the channel length/channel width ratio of each of the MOS transistors11,13, and14.

When a semiconductor integrated circuit device incorporates a low-voltage circuit which operates around 1 V, the influence of a change in temperature difference or variations in manufacturing becomes more prominent. It becomes difficult to detect power-on.

To solve this problem, a technique of detecting power-on by using a circuit with low temperature dependency, such as a band gap reference circuit is proposed (see, e.g., Jpn. Pat. Appln KOKAI Publication Nos. 2002-43917 and H10-207580). However, no prior art can sufficiently reduce temperature dependency because an output voltage from the band gap reference circuit and a voltage prepared by resistance-dividing a power supply voltage are compared, in other words, a voltage free from temperature dependency and a voltage with temperature dependency (though temperature dependency is relatively low) are compared. Such technique is not satisfactorily applied to an onboard semiconductor integrated circuit device which is used under strict conditions.

The same problem occurs when a power-on reset circuit for initializing a register or latch circuit in a semiconductor integrated circuit device upon power-on is constituted using the above-described power-on detector. Demands have arisen for a measure against this problem.

BRIEF SUMMARY OF THE INVENTION

According to one aspect of the present invention, there is provided a power-on detector including a current generation circuit having a first output terminal and a second output terminal and configured to produce a first current and a second current from the first output terminal and the second output terminal, respectively, the first current and the second current having a low degree of temperature dependency and being substantially equal to each other, a first load element connected between the first output terminal of the current generation circuit and a first potential supply source, a current mirror circuit having a first current path and a second current path, the first current path being connected to the second output terminal of the current generation circuit, a second load element connected between the second current path of the current mirror circuit and a second potential supply source, and a first comparator having a first input terminal connected to the first output terminal of the current generation circuit, and a second input terminal connected to a connection node between the second load element and the current mirror circuit, the first comparator making comparison between (i) a first voltage obtained by causing the first current output from the first output terminal of the current generation circuit to flow to the first potential supply source by way of the first load element and (ii) a second voltage obtained by causing a current flowing from the second potential supply circuit to the second current oath of the current mirror circuit by way of the second load element, wherein power-on is detected when the second voltage becomes higher than the first voltage when a power supply is turned on.

According to another aspect of the present invention, there is provided a power-on reset circuit including a data holding circuit which holds data, a current generation circuit having a first output terminal and a second output terminal and configured to produce a first current and a second current from the first output terminal and the second output terminal, respectively, the first current and the second current having a low degree of temperature dependency and being substantially equal to each other, a first load element connected between the first output terminal of the current generation circuit and a first potential supply source, a current mirror circuit having a first current path and a second current path, the first current path being connected to the second output terminal of the current generation circuit, a second load element connected between the second current path of the current mirror circuit and a second potential supply source, a first comparator having a first input terminal connected to the first output terminal of the current generation circuit, and a second input terminal connected to a connection node between the second load element and the current mirror circuit, the first comparator making comparison between (i) a first voltage obtained by causing the first current output from the first output terminal of the current generation circuit to flow to the first potential supply source by way of the first load element and (ii) a second voltage obtained by causing a current flowing from the second potential supply circuit to the second current path of the current mirror circuit by way of the second load element, and a reset circuit which resets data held by the data holding circuit on the basis of an output signal from the first comparator, wherein the reset circuit resets data held by the data holding circuit when the second voltage becomes higher than the first voltage when a power supply is turned on.”

DETAILED DESCRIPTION OF THE INVENTION

FIG. 2is a conceptual view for explaining a power-on detector and power-on reset circuit according to the first embodiment of the present invention. A BGR (Band Gap Reference) circuit20is a reference potential generation circuit which generates a reference potential with low temperature dependency. The BGR circuit20is comprised of first, second, and third circuit units21,22, and23. The circuit unit21is a circuit which generates a current (dI/dT>0) having a positive temperature characteristic. The circuit unit22is a circuit which generates a current (dI/dT<0) having a negative temperature characteristic. The output currents of the circuit units21and22are added by the circuit unit23. As a result, the temperature characteristics of the circuit units21and22are canceled, and first and second output currents (dI/dT+dI/dT=0) substantially free from temperature dependency are generated.

The first output current of the circuit unit23is supplied to a resistor24to generate a voltage (first voltage) V1. The second output current is supplied to a current mirror circuit25. The current mirror circuit25supplies a current equal to the output current to a resistor26, generating a voltage (second voltage) V2. The voltage V1becomes substantially free from the temperature characteristic with respect to the potential of ground VSS(potential of the first potential supply source). The voltage V2becomes substantially free from the temperature characteristic with respect to the potential of a power supply VDD(potential of the second potential supply source).

The voltages V1and V2are compared by a comparator (first comparator)27to output a power-on detection signal PDS. When the sum of a voltage applied across the resistor26and a voltage applied across the resistor24exceeds the voltages of the power supplies VDDand VSS, the comparator27changes the level of the power-on detection signal PDS from the potential of ground VSSto that of the power supply VDD. The voltages across the resistors24and26are substantially free from temperature dependency, as described above. The potential to which an output (power-on detection signal PDS) from the comparator27changes is not influenced by any temperature change.

If the power-on detection signal PDS output from the comparator27is used to generate a reset signal for a data holding circuit such as a register or latch circuit, a power-on reset circuit free from any influence of a temperature change can be constituted.

FIG. 3shows an arrangement example of the circuit unit21in the circuit shown in FIG.2. This circuit comprises a differential amplifier (comparator)31for generating a positive temperature characteristic, p-channel MOS transistors32and33, a resistor34, and diodes35and36. The source of the MOS transistor32is connected to the power supply VDD; its drain, to the non-inverting input terminal (+) of the comparator31; and its gate, to the output terminal of the comparator31. The source of the MOS transistor33is connected to the power supply VDD; its drain, to the inverting input terminal (−) of the comparator31; and its gate, to the output terminal of the comparator31. The drain of the MOS transistor32is connected to one terminal of the resistor34. The anode-cathode path of the diode35is connected between the other terminal of the resistor34and ground VSS. The drain of the MOS transistor33is connected to the anode of the diode36, and the cathode of the diode36is connected to ground VSS. The diode35is larger in size than the diode36. A voltage VOUTAcontrolling a positive temperature characteristic current is output from an output terminal37connected to the output terminal of the comparator31.

FIG. 4shows an arrangement example of the circuit unit22in the circuit shown in FIG.2. This circuit comprises a differential amplifier (comparator)41for generating a negative temperature characteristic, p-channel MOS transistors42and43, a diode44, and a resistor45. The source of the MOS transistor42is connected to the power supply VDD; and its drain, to the inverting input terminal (−) of the comparator41. The gate of the MOS transistor42receives the output voltage VOUTAof the circuit unit21. The anode of the diode44is connected to the drain of the MOS transistor42; and its cathode, to ground VSS. The diode44is equal in size to the diode36. The source of the MOS transistor43is connected to the power supply VDD; its drain, to the non-inverting input terminal (+) of the comparator41; and its gate, to the output terminal of the comparator41. One terminal of the resistor45is connected to the drain of the MOS transistor43; and the other terminal, to ground VSS. A voltage VOUTBcontrolling a negative temperature characteristic current is output from an output terminal46connected to the output terminal of the comparator41.

FIG. 5shows an arrangement example of the circuit unit23in the circuit shown in FIG.2. This circuit comprises p-channel MOS transistors51-1,51-2,52-1and52-2. The source of the MOS transistor51-1is connected to the power supply VDD, and its gate receives the output voltage VOUTAof the circuit unit21. The source of the MOS transistor52-1is connected to the power supply VDD, its drain is commonly connected to the drain of the MOS transistor51-1, and its gate receives the output voltage VOUTBof the circuit unit22. The MOS transistors51-1and52-1operate as a first current source circuit which extracts a current free from any temperature characteristic from outputs from the differential amplifiers31and41. The source of the MOS transistor51-2is connected to the power supply VDD, and its sate receives the output voltage VOUTAof the circuit unit21. The source of the MOS transistor52-2is connected to the power supply VDD, its drain is commonly connected to the drain of the MOS transistor51-2, and its gate receives the output voltage VOUTBof the circuit unit22. The MOS transistors51-2and52-2operate as a second current source circuit which extracts a current free from any temperature characteristic from outputs from the differential amplifiers31and41.

One terminal of the resistor24is connected to the common drain connection node between the MOS transistors51-1and52-1; and the other terminal, to ground VSS. A potential VREFDC(reference potential or first voltage V1) which is generated by adding the output currents of the circuit units21and22and is free from temperature dependency is output from an output terminal54connected to the common drain connection node between the MOS transistors51-1and52-1.

The temperature dependency can be changed by adjusting the resistance values of the resistors34and45. In this circuit, the resistance values are so adjusted as to reduce the temperature characteristic of the potential VREFDC(reference potential or first voltage V1).

The reference potential VREFDCcan be set by the resistance value of the resistor24. The reference potential VREFDCcan be set high by increasing the resistance value of the resistor24, and low by decreasing the resistance value. The use of a variable resistor24allows freely setting the reference potential VREFDC.

FIG. 6shows an extracted part of the circuit shown in FIG.2. This circuit is a potential comparison circuit using a current source and current mirror circuit. InFIG. 6, the same reference numerals as inFIG. 2denote the same parts, and a detailed description thereof will be omitted.

The current mirror circuit25is comprised of n-channel MOS transistors28and29. The drain and gate of the MOS transistor28are connected to the output terminal of the circuit unit23(which is equivalently illustrated by current sources23A and23B in FIG.6), and the source is connected to ground VSS. The drain of the MOS transistor29is connected to the other terminal of the resistor26, its source is connected to ground VSS, and its gate is commonly connected to the gate of the MOS transistor28.

FIG. 7shows an arrangement example of the comparators (differential amplifiers)27,31, and41in the circuits shown inFIGS. 2,3,4, and6. Each comparator is comprised of p-channel MOS transistors61to64and n-channel MOS transistors65to67. The sources of the MOS transistors61and62which operate as a differential input pair are commonly connected, and their gates are respectively connected to differential input terminals68and69which operate as an inverting input terminal (−) and non-inverting input terminal (+). The drain-source path of the MOS transistor63is connected between the power supply VDDand the common source connection node between the MOS transistors61and62. The drains of the MOS transistors61and62are commonly connected to those of the MOS transistors65and66. The gates of the MOS transistors65and66are commonly connected to the drain of the MOS transistor65; and their sources, to ground VSS.

The source of the MOS transistor64is connected to the power supply VDD, its drain is connected to an output terminal70, and its gate is commonly connected to its drain and the gate of the MOS transistor63. The drain of the MOS transistor67is connected to the output terminal70; its source, to ground VSS; and its gate, to the common drain connection node between the MOS transistors62and66.

The comparator having this arrangement amplifies signals input to the differential input terminals68and69by the MOS transistors61,62,65, and66, and further amplifies the signals by the MOS transistors63,64, and67. The comparator can operate even by a low-potential input signal.

FIG. 8shows a circuit, e.g., latch circuit which is reset by the power-on reset circuit shown inFIGS. 2to7. The latch circuit is a flip-flop comprised of a 2-input NAND gate71and 3-input NAND gate72. The flip-flop latches data on the basis of signals input to a set terminal S and reset terminal R, and obtains an output signal Q. Upon power-on, the flip-flop receives the power-on detection signal PDS and is initialized.

FIG. 9shows changes along the time axis in the potential of the power supply VDDupon power-on, the level of the power-on detection signal PDS, and the voltages V1and V2. After power-on, the potential of the power supply VDDrises. On the initial stage of power-on, the voltage V2is higher than V1. When the potential of the power supply VDDreaches a circuit operable level, the voltage V1becomes higher than V2. Accordingly, the level of the power-on detection signal PDS which rises similarly to the potential of the power supply VDDis inverted from “H” level to “L” level. As the potential of the power supply VDDfurther rises, the voltage V2becomes higher than V1. The power-on detection signal PDS output from the comparator27is inverted to “H” level, and power-on is detected.

In this arrangement, the BGR circuit20is used to generate the voltages V1and V2free from temperature dependency. The voltages V1and V2are compared to generate the power-on detection signal PDS. The temperature dependency can be substantially eliminated. The circuit is constituted using a pair of MOS transistors, eliminating the influence of process variations. By controlling the resistance value of the resistor53, the power-on detection level can be freely adjusted.

FIG. 10is a circuit diagram for explaining a power-on detector and power-on reset circuit according to the second embodiment of the present invention. This circuit comprises comparators81to83, p-channel MOS transistors84to90, n-channel MOS transistors91and92, resistors93to96, and diodes97and98.

The source of the MOS transistor84is connected to a power supply VDD; its drain, to the non-inverting input terminal (+) of the comparator81; and its gate, to the output terminal of the comparator81. One terminal of the resistor93is connected to the drain of the MOS transistor84; and the other terminal, to the anode of the diode97. The cathode of the diode97is connected to ground VSS. The source of the MOS transistor85is connected to the power supply VDD; its drain, to the inverting input terminals (−) of the comparators81and82; and its gate, to the output terminal of the comparator81. The anode of the diode98is connected to the drain of the MOS transistor85; and its cathode, to ground VSS.

The source of the MOS transistor86is connected to the power supply VDD; its drain, to the non-inverting input terminal (+) of the comparator82; and its gate, to the output terminal of the comparator82. One terminal of the resistor94is connected to the drain of the MOS transistor86; and the other terminal, to ground VSS.

The source of the MOS transistor87is connected to the power supply VDD; and its gate, to the output terminal of the comparator81. The source of the MOS transistor88is connected to the power supply VDD, its drain is commonly connected to the drain of the MOS transistor87, and its gate is connected to the output terminal of the comparator82. The resistor95is connected between ground VSSand the common drain connection node between the MOS transistors87and88. The common drain connection node is connected to the inverting input terminal (−) of the comparator83.

The source of the MOS transistor89is connected to the power supply VDD; and its gate, to the output terminal of the comparator81. The source of the MOS transistor90is connected to the power supply VDD, its drain is commonly connected to the drain of the MOS transistor89, and its gate is connected to the output terminal of the comparator82. The drain and gate of the MOS transistor91are connected to the common drain connection node between the MOS transistors89and90. The source of the MOS transistor91is connected to ground VSS.

One terminal of the resistor96is connected to the power supply VDD; and the other terminal, to the drain of the MOS transistor92and the non-inverting input terminal (+) of the comparator83. The source of the MOS transistor92is connected to ground VSS; and its gate, to the gate of the MOS transistor91. A power-on detection signal is output from the output terminal of the comparator83.

The comparators81to83can reliably operate even at a low voltage around 1 V with the same arrangement as that of the circuit shown in FIG.7.

In this arrangement, the basic arrangement and operation are the same as those in the first embodiment. More specifically, a BGR circuit is used to generate voltages V1and V2free from temperature dependency. The voltages V1and V2are compared to generate the power-on detection signal PDS. The temperature dependency can be substantially eliminated. By controlling the resistance value of the resistor95and96the power-on detection level can be freely adjusted.

In the second embodiment, the MOS transistor85and diode98are shared between the comparators81and82. The output voltages VOUTAand VOUTBof the comparators81and82are respectively received by a pair of MOS transistors87and88and a pair of MOS transistors89and90. This can further reduce variations in manufacturing process.

The power-on detector having the above arrangement, and the power-on reset circuit using the power-on detector can suppress variations in power-on detection level caused by a temperature change or manufacturing variations, and can perform reliable detection operation or reset operation even at a low voltage.

In the power-on detector and power-on reset circuit according to the first and second embodiments, the conductivity types of each p-channel MOS transistor and each n-channel MOS transistor can be reversed, and the polarities of the power supplies VDDand VSScan be reversed.

As described above, according to one aspect of this invention, a power-on detector capable of suppressing variations in power-on detection level caused by a temperature change or manufacturing variations, and performing reliable detection operation even at a low voltage, and a power-on reset circuit using the power-on detector can be obtained.