High ratio current mirror with enhanced power supply rejection ratio

The PSRR (power supply rejection ratio) of a current mirror circuit is increased by cascoding the output transistor of the current mirror, and the precision of the circuit is enhanced by employing a frequency compensated gain stage utilizing a field effect transistor to drive a bipolar current output transistor.

CROSS-REFERENCE TO RELATED APPLICATION 
This application claims priority from European App'n 92830453.4, filed Aug. 
26, 1992. 
BACKGROUND AND SUMMARY OF THE INVENTION 
The present invention relates to a circuit capable of generating, starting 
from a control current, another current that is n times larger than the 
control current. 
When designing electronic circuits there is often the need of implementing 
current mirrors having a large ratio between the mirrored or output 
current and a reference or control current. Normally a current mirror is 
said to have a large ratio when it is in the order of ten. An additional 
requisite of current mirrors is to be very precise. 
A classical circuit of a current mirror is shown in FIG. 1. When a 
particularly high precision is required, a modified circuit as the one 
depicted in FIG. 2 is often used. Such a modified circuit provides for a 
certain recovery of the base current by utilizing a third transistor, N3, 
for reducing an intrinsic error of the circuit. This error arises because 
in the control branch of the current mirror circuit comprising the 
diode-configured N1 transistor, among the current contributions there will 
be one due to the base currents of the two transistors of the mirror. This 
"offset " current produces an error proportional to the mirror ratio plus 
a term given by 1/.beta.. The additional transistor N3 permits a 
substantial recovery of the base currents of the transistors N1 and N2 and 
therefore a reduction of such an intrinsic asymmetry. This solution is not 
very effective in the case of circuits that must implement a relatively 
high mirror ratio, because the error remains large. 
An operational transconductance amplifier (OTA), provided with a feedback 
loop including a transistor P, as depicted in FIG. 3, is often used in 
these cases. This circuit is capable of ensuring a high precision, even in 
the case of relatively large mirror ratios. 
On the other hand, in certain applications, for example in telephone 
circuits (and, more generally, wherever signal transmission lines are also 
used as power supply lines), i.e. where it is particularly important that 
the circuits possess a high Power-Supply-Rejection-Ratio (PSRR), the known 
current mirrors have an impedance, as measured between the supply nodes, 
which is not sufficiently high to make their behavior relatively 
insensitive to the presence of AC signals on the supply line. Such a 
drawback of the known circuits becomes more marked in current mirrors 
having a relatively high mirror ratio. Moreover, in some applications, the 
precision of a circuit made according to the known techniques, e.g. as 
depicted in FIG. 3, is yet insufficient because of the finite gain of the 
OTA. 
Note that the circuit of FIG. 3 has a somewhat different basic principle of 
operation from that of FIGS. 1 and 2: a feedback is employed for 
equalizing the voltage drops across the resistors R1 and R2. Since the 
reference current I.sub.rif is drawn across R1, and the mirrored current 
I.sub.spec across R2, the following relationship holds: 
EQU I.sub.spec =I.sub.rif R1/R2. 
An easily implementable current mirror circuit has now been devised, which 
is capable of ensuring a high degree of precision also in relatively large 
mirror ratio circuits and has a high impedance as measured across the 
supply nodes. 
Basically, the current mirror circuit provided by the present invention 
employs a field effect transistor for handling the current through a 
control terminal, e.g. a base terminal of a current output transistor, 
thus ensuring a high degree of precision of the current mirror. A 
frequency compensation of the gain stage is implemented by a feedback 
capacitance. The impedance of the circuit as measured across the supply 
nodes (PSRR) is increased by employing an additional transistor, 
functionally connected in the output branch of the current mirror circuit 
so as to form (together with the output branch transistor of the basic 
current mirror circuit), a cascode-type circuit capable of increasing the 
output impedance of the current mirror. 
The output impedance of a current mirror circuit represents a most critical 
factor in determining a high impedance as measured across the supply nodes 
of the circuit, in view of the fact that it should be divided by the 
mirror ratio. The high loop gain provided by the use of a gain stage in 
the present invention not only reduces the error (thus increasing the 
precision of the circuit), but also helps to attain a high impedance 
across the supply nodes of the current mirror circuit. In fact, because 
the control current of the current output transistor is driven by the 
field effect transistor of the gain stage, it is possible to reduce the 
current levels in the two branches of the current mirror without 
negatively affecting performance. Such a current level reduction, beside 
producing a sensible saving in power consumption and facilitating sizing 
of the components of the current mirror, further increases the impedance. 
The output impedance of the circuit, i.e. the output impedance of the 
transistor that is driven by the field effect transistor of the gain 
stage, increases. This represents a further advantage per se, because the 
output transistor of the current mirror often must drive relatively high 
currents and therefore should have a relatively low output impedance. 
The presently preferred embodiment provides a current mirror in which, like 
the circuit of FIG. 3, the mirror ratio is determined by the ratio of two 
resistors. However, the circuits of the present invention have some 
significant differences from those of FIG. 3. Not only is the complex OTA 
stage eliminated, but there are also some other notable differences. 
First, an additional amplifier stage is added to drive the output 
transistor. Second, this additional amplifier stage is preferably a 
field-effect transistor, and the output transistor is preferably bipolar. 
Third, an asymmetric configuration of bipolar transistors is used to drive 
the input of the additional amplifier stage. (In the presently preferred 
embodiment, an additional cascode transistor is interposed in only one of 
the two legs.) Fourth, a distinctive compensation capacitance 
configuration is used, as detailed below. 
This has been advantageously implemented using a BiCMOS circuit, of which 
one sample implementation is shown in FIG. 4. The additional MOS 
amplifying stage performs two beneficial functions: 
It increases the output impedance of the output transistor, which, if 
designed for carrying a relatively high output current, would have an 
intrinsically low output impedance. 
A second function of the MOS amplifying stage is to increase the loop gain 
of the circuit and to "decouple " the bipolar output transistor from the 
additional biplar cascode transistor (which would otherwise tend to 
depress the gain of the output transistor). 
The additional transistor (P5 in the example of FIG. 4) serves the 
functions of) cascoding P2, thus increasing its output impedance and b) of 
allowing a "peculiar " compensation by means of the capacitance Cc that is 
not, as customarily done, connected to the gate of M4 but to the emitter 
of P5. This has been found to significantly improve the PSRR further.

DESCRIPTION OF THE PREFERRED EMBODIMENTS 
The numerous innovative teachings of the present application will be 
described with particular reference to the presently preferred embodiment. 
However, it should be understood that this class of embodiments provides 
only a few examples of the many advantageous uses of the innovative 
teachings herein. In general, statements made in the specification of the 
present application do not necessarily delimit any of the various claimed 
inventions. Moreover, some statements may apply to some inventive features 
but not to others. 
Notably all the current mirror circuits shown in the figures provide a 
mirroring ratio that is given by the relation 
EQU I.sub.spec /I.sub.rif =R1/R2. 
With reference to FIG. 4, a current mirror circuit of the invention has a 
first control or reference branch, which comprises a biasing current 
generator N6, a first diode-connected transistor P1 and a first 
degenerating resistance R1, functionally connected between the transistor 
P1 and a supply node A of the circuit, according to a basic configuration. 
A second output branch of the current mirror comprises a biasing current 
generator N7, a second or output transistor P2 of the current mirror and a 
second degenerating resistance R2, functionally connected between the 
transistor P2 and the supply node A. 
According to such a basic current mirror configuration, to a certain 
control or reference current I.sub.rif, drawn from the connection node 
between the degeneration resistance R1 and the diode-connected transistor 
P1 of the reference branch of the mirror, corresponds a mirrored current 
I.sub.spec delivered by the circuit through the output node, which is 
represented by the connection node between the degeneration resistance R2 
and the output transistor P2 of the current mirror. 
According to the present invention, such a basic current mirror circuit is 
modified by adding a gain stage implemented with a field effect transistor 
M4, capable of driving a current output transistor P3, through which the 
mirrored current I.sub.spec produced by the current mirror circuit is 
forced. The gain stage composed of the field effect transistor M4 is 
frequency compensated by means of a feedback capacitance Cc. 
The gain stage increases the loop gain of the circuit thus increasing the 
degree of precision beyond the precision that may be achieved when using a 
buffer, as done in the prior art circuit depicted in FIG. 3 and which is 
limited by the finite gain of the buffer. The increased gain of the 
circuit also permits to reduce the current consumption because the driving 
current of the output transistor P3 is provided by the field effect 
transistor M4 and therefore the currents that flow through the two 
branches of the current mirror circuit (i.e. through P1, P2 and P5), may 
be freely designed to be relatively small, by suitably dimensioning the 
current generators N6 and N7, without negatively affecting the performance 
of the circuit. 
The impedance of the circuit, as measured between the supply node A and 
ground, is advantageously increased by employing a fifth transistor P5, 
functionally connected in the output branch of the current mirror in a way 
as to constitute together with the transistor P2 of the basic current 
mirror circuit a cascode circuit. In this case, a biasing resistance Rb 
must be introduced in the reference branch of the current mirror, as shown 
in the figure, to exclude the possibility that the transistor P2 of the 
current mirror might saturate, i.e. for ensuring the maintenance of a 
collector-emitter voltage (VCE) of the transistor P2 higher than the 
saturation voltage thereof. 
Substantially, the effect of the cascode circuit formed by the addition of 
the fifth transistor P5 is that of increasing the output impedance of the 
output transistor P2 of the current mirror, thus providing a higher 
impedance of the circuit as seen from the supply node, A. The cascoding of 
the output transistor P2 of the current mirror is particularly effective 
because the output impedance of this output transistor represents a 
determining factor for achieving a high impedance of the circuit as seen 
from the supply node. In fact, in this respect, the output impedance of 
the transistor of P2 should be divided by the mirror ratio, and in case of 
a relatively high mirror ratio this impedance may therefore be excessively 
low. Optionally, a further increase of the impedance of the circuit as 
measured across the supply nodes, may be obtained, as schematically 
depicted in FIG. 4, by introducing two further degeneration resistances R3 
and R4 between the ground node of the circuit and the biasing current 
generators N6 and N7, respectively. An even better result in terms of 
further increasing the circuit's impedance, may be obtained also by adding 
other cascode circuits in the two branches of the current mirror circuit. 
As depicted in the example of FIG. 4, a frequency compensation capacitance 
Cc is connected between the control node (base) of the current output 
transistor P3 and preferably the intermediate connection node between the 
pair of cascode-connected transistors P2 and P5, rather than to the gate 
of the gain stage transistor M4. This produces a more favorable impedance 
characteristic of the circuit versus frequency. 
One sample embodiment which has been implemented contains the following 
characteristics. It should be noted that these characteristics do not 
limit other embodiments with different characteristics. Transistors N6 and 
N7 both have emitter areas of 3.6.multidot.3.6 .mu..sup.2. Resistors R3 
and R4 have resistances of 10 .OMEGA.. The current values generated by 
transistor N6 through resistor R3 and by transistor N7 through resistor R4 
are found to be 30 .mu.A. Rb was implemented to be 16 .OMEGA.. PNP 
transistors P1, P2, and P5 were vertical transistors with isolated 
collectors. Each had an emitter area of 3.6 .multidot.3.6 .mu..sup.2. R1 
and R2 were implemented with a series-parallel combination with 
resistances of 960 .OMEGA. and 12.OMEGA. respectively. This achieves an 
80/1 mirror. MOS transistor M4 was implemented with dimensions 400/2 .mu.. 
The compensation capacitor Cc was 10 pF. PNP transistor P3 has an emitter 
area of 3.6.multidot.3.6 .mu.m.sup.2 so that it could carry up to 100 
.mu.A. 
At the most basic level, the circuits of FIGS. 3 and 4 share similar 
principles of operation: in either case a feedback is employed for 
equalizing the voltage drops across the resistors R1 and R2. Therefore in 
both cases, the following relationship holds: 
EQU I.sub.spec =I.sub.rif .multidot.R1/R2. 
Thus, the transistor P3 of FIG. 4 is approximately equivalent to the 
transistor P of FIG. 3, even though the other functions of the circuits 
are different. 
Even if, in principle, one could do without the additional amplifying stage 
(M4), a significant portion of the beneficial effects of P5 in raising the 
PSRR figure would be forfeited. M4 has two functions. One is to increase 
the output impedance of the output transistor P3, which, if designed for 
carrying a relatively high output current, would have an intrinsically low 
output impedance. A second function of M4 is to increase the loop gain of 
the circuit and to "decouple " P3 from P5 (which would otherwise tend to 
depress the gain of P5). 
On the other hand, P5 has the essential function of a) cascoding P2, thus 
increasing its output impedance and b) of allowing a "peculiar " 
compensation by means of the capacitance Cc that is not, as customarily 
done, connected to the gate of M4 but to the emitter of P5. This has been 
found to significantly improve the PSRR further. 
Thus, the joint contributions of P5 and M4 permit significant improvements 
as compared with the prior art circuit using an OTA. 
FURTHER MODIFICATIONS AND VARIATIONS 
It will be recognized by those skilled in the art that the innovative 
concepts disclosed in the present application can be applied in a wide 
variety of contexts. Moreover, the preferred implementation can be 
modified in a tremendous variety of ways. Accordingly, it should be 
understood that the modifications and variations suggested below and above 
are merely illustrative. These examples may help to show some of the scope 
of the inventive concepts, but these examples do not nearly exhaust. He 
full scope of variations in the disclosed novel concepts. 
Even though the circuit of the invention has been described in connection 
with a preferred embodiment, employing bipolar transistors of a certain 
type of conductivity with the exception of the M4 transistor of the gain 
stage (which, in the example shown, may be an n-channel MOS transistor), 
it will be evident to any skilled technician that a similar circuit may 
also be realized by employing transistors of an opposite type of 
conductivity and by inverting all the polarities. Moreover the circuit may 
also be made by employing field effect transistors in place of the bipolar 
transistors. For example, transistors P1, P2, P5, N6 and N7 may be 
replaced by MOS transistors. In such a case, the substitutes of N6 and N7 
should be "cascoded " in order to maintain a high PSRR, in view of the 
fact that a MOS transistor normally has a lower output impedance than a 
bipolar transistor. 
The ratios between P1 and P2 and between N6/R3 and N7/R4 could also be 
nonunitary, however a unit ratio is preferred because of the 
simplification of the biasing and retention of symmetry of integrated 
structures. 
As will be recognized by those skilled in the art, the innovative concepts 
described in the present application can be modified and varied over a 
tremendous range of applications, and accordingly the scope of patented 
subject matter is not limited by any of the specific exemplary teachings 
given.