LIGHT RECEIVING ELEMENT ARRAY AND MANUFACTURING METHOD THEREFOR

A light receiving element array includes a substrate and a laminated semiconductor structure that is formed on the substrate. The laminated semiconductor structure includes a light absorbing layer that is disposed above the substrate and a plurality of window layers of a first conductivity type that are formed apart from each other on the light absorbing layer. Inside the laminated semiconductor structure, there is formed, for each window layer, a first of second conductivity type region that extends into the light absorbing layer from a surface of the window layer at an opposite side to the light absorbing layer. Inside the light absorbing layer, there is formed a second of second conductivity type region that is disposed such as to surround each of the plurality of window layers in plan view and extends from a surface of the light absorbing layer at an opposite side to the substrate toward a surface of the light absorbing layer at the substrate side.

TECHNICAL FIELD

The present disclosure relates to a light receiving element array and a method for manufacturing the same.

BACKGROUND ART

Patent Literature 1 discloses a light receiving element array that includes an n-type substrate, a laminated semiconductor layer that is formed on the n-type substrate and also includes a plurality of light receiving elements. The laminated semiconductor layer is constituted of a light receiving layer that is formed on the n-type substrate and an n-type semiconductor layer that is formed on the light receiving layer. The laminated semiconductor layer has a plurality of p-type semiconductor regions in each element section area.

CITATION LIST

Patent Literature

Patent Literature 1: Japanese Patent Application Publication No. 2016-225359

The above and yet other objects, features, and effects of the present disclosure will become more apparent from the following description of the preferred embodiments made with reference to the attached drawings.

DESCRIPTION OF EMBODIMENTS

Description of Preferred Embodiments of the Present Disclosure

A preferred embodiment of the present disclosure provides a light receiving element array including a substrate and a laminated semiconductor structure that is formed on the substrate and where the laminated semiconductor structure includes a light absorbing layer that is disposed above the substrate and a plurality of window layers of a first conductivity type that are formed apart from each other on the light absorbing layer, there is formed, inside the laminated semiconductor structure, for each window layer, a first of second conductivity type region that extends into the light absorbing layer from a surface of the window layer at an opposite side to the light absorbing layer, and there is formed, inside the light absorbing layer, a second of second conductivity type region that is disposed such as to surround each of the plurality of window layers in plan view and extends from a surface of the light absorbing layer at an opposite side to the substrate toward a surface of the light absorbing layer at the substrate side.

With this arrangement, crosstalk can be reduced.

In the preferred embodiment of the present disclosure, the second of second conductivity type region extends from the surface of the light absorbing layer at the opposite side to the substrate to an intermediate thickness of the light absorbing layer.

In the preferred embodiment of the present disclosure, the second of second conductivity type region penetrates through the light absorbing layer.

A preferred embodiment of the present disclosure provides a light receiving element array including a substrate and a laminated semiconductor structure that is formed on the substrate and where the laminated semiconductor structure includes a light absorbing layer that is disposed above the substrate and a plurality of window layers of a first conductivity type that are formed apart from each other on the light absorbing layer, there is formed, inside the laminated semiconductor structure, for each window layer, a second conductivity type region that extends into the light absorbing layer from a surface of the window layer at an opposite side to the light absorbing layer, and there is formed, inside the light absorbing layer, a separating groove that is disposed such as to surround each of the plurality of window layers in plan view and extends from a surface of the light absorbing layer at an opposite side to the substrate toward a surface of the light absorbing layer at the substrate side.

With this arrangement, crosstalk can be reduced.

In the preferred embodiment of the present disclosure, the separating groove penetrates through the light absorbing layer.

In the preferred embodiment of the present disclosure, an insulating film that is formed on the light absorbing layer such as to cover the plurality of window layers and a plurality of first electrodes that are provided for each window layer and disposed on the insulating film are included and each first electrode is electrically connected to the corresponding first of second conductivity type region.

In the preferred embodiment of the present disclosure, an insulating film that is formed on the light absorbing layer such as to cover the plurality of window layers and a plurality of first electrodes that are provided for each window layer and disposed on the insulating film are included and each first electrode is electrically connected to the corresponding second conductivity type region.

In the preferred embodiment of the present disclosure, the insulating film is an antireflection film that prevents reflection of light of a wavelength set in advance.

In the preferred embodiment of the present disclosure, the first electrodes are of endless shapes in plan view.

In the preferred embodiment of the present disclosure, a second electrode that is formed on a second main surface of the substrate.

In the preferred embodiment of the present disclosure, the plurality of window layers are disposed in a matrix in plan view.

In the preferred embodiment of the present disclosure, the laminated semiconductor structure includes a buffer layer of the first conductivity type that is formed between the substrate and the light absorbing layer.

In the preferred embodiment of the present disclosure, the buffer layer has an exposed surface at a portion of a surface at an opposite side to the substrate and a third electrode is formed on the exposed surface.

In the preferred embodiment of the present disclosure, the substrate is an n-type InP substrate, the light absorbing layer is a non-doped InGaAs layer, and the window layers are n-type InP layers.

In the preferred embodiment of the present disclosure, the substrate is an n-type InP substrate, the buffer layer is an n-type InP layer, the light absorbing layer is a non-doped InGaAs layer, and the window layers are n-type InP layers.

A preferred embodiment of the present disclosure provides a method for manufacturing light receiving element array including a step of forming, on a substrate, a laminated semiconductor structure including a light absorbing layer and a plurality of window layers of a first conductivity type that are formed apart from each other on the light absorbing layer, a step of forming, inside the laminated semiconductor structure, for each window layer, a first of second conductivity type region that extends into the light absorbing layer from a surface of the window layer at an opposite side to the light absorbing layer, and a step of forming a second of second conductivity type region that is disposed such as to surround each of the plurality of window layers in plan view and extends from a surface of the light absorbing layer at an opposite side to the substrate toward a surface of the light absorbing layer at the substrate side.

With this manufacturing method, a light receiving element array by which crosstalk can be reduced can be obtained.

In the preferred embodiment of the present disclosure, the step of forming the first of second conductivity type regions and the step of forming the second of second conductivity type region are performed in the same step.

In the preferred embodiment of the present disclosure, a step of forming an insulating film on the light absorbing layer such as to cover the plurality of window layers, a step of forming, for each window layer, a first electrode, electrically connected to the first of second conductivity type region, on the insulating film, and a step of forming a second electrode on a surface of the substrate at an opposite side to the laminated semiconductor structure are further included.

Preferred embodiments of the present disclosure shall be described in detail below with reference to the attached drawings.

FIG.1Ais a plan view for describing the arrangement of a light receiving element array according to a first preferred embodiment of the present disclosure.FIG.1Bis a partially enlarged plan view showing a portion IB ofFIG.1A.FIG.2is a diagrammatic sectional view taken along line II-II ofFIG.1B.FIG.3is a diagrammatic sectional view taken along line ofFIG.1B.

In the following, a right/left direction of the sheet surface ofFIG.1Amay be referred to at times as a lateral direction and an up/down direction of the sheet surface ofFIG.1Amay be referred to at times as a longitudinal direction.

A light receiving element array1has a rectangular parallelepiped shape. In this preferred embodiment, a shape in plan view of the light receiving element array1is a square shape having two sides parallel to the lateral direction and two sides parallel to the longitudinal direction.

The light receiving element array1includes a substrate2that has a first main surface (front surface)2aand a second main surface (rear surface)2bat an opposite side thereof and a laminated semiconductor structure20that is formed on the first main surface2aof the substrate2. The laminated semiconductor structure20includes a buffer layer3of an n-type that is formed on the first main surface2aof the substrate2and a non-doped light absorbing layer4that is formed on a region of a buffer layer3front surface that excludes four corner portions. The laminated semiconductor structure20further includes a plurality of window layers5of the n-type that are formed apart from each other in a central portion region of a front surface of the light absorbing layer4and an n-type layer6that is formed on a peripheral edge portion of the front surface of the light absorbing layer4such as to surround the window layer group. The laminated semiconductor structure20further includes contact layers7of a p-type that are formed on respective window layers5and contact first p-type regions8to be described below.

Inside the laminated semiconductor structure20, there is formed, for each window layer5, the first p-type region8that extends into the light absorbing layer4from a surface of the window layer5at an opposite side to the light absorbing layer4. Inside the light absorbing layer4is formed a second p-type region9that is disposed such as to surround each of the plurality of window layers5in plan view and extends from a surface of the light absorbing layer4at an opposite side to the substrate2toward a surface of the light absorbing layer4at the substrate2side. InFIG.1B, the second p-type region9is shown with dots added for clarity.

The light receiving element array1includes an insulating film10that covers a portion of an exposed surface of the buffer layer3, an exposed surface of the light absorbing layer4, exposed surfaces of the window layer5, an exposed surface of the n-type layer6, and the contact layers7. Also, the light receiving element array1includes a plurality of first electrodes (p side electrodes)12that are provided for each window layer5and are disposed on the insulating film10.

Also, the light receiving element array1includes a second electrode (main n side electrode)13that is formed on the second main surface2bof the substrate2and a plurality of third electrodes (sub n side electrodes)14that are formed on the four corner portions of the front surface of the buffer layer3. Further, the light receiving element array1includes a plurality of bonding pads15, wirings16, and marks17and18that are formed on the insulating film10.

In the light receiving element array1, there is formed, in each region in which the window layer5is present in plan view, a light receiving element30that is constituted of a PIN type photodiode. In other words, in the light receiving element array1, the light receiving element30is formed for each first p-type region8. With this preferred embodiment, the light receiving element array1includes 16 light receiving elements30of four rows and four columns. Each light receiving element30includes the substrate2, the buffer layer3, the light absorbing layer4, the window layer5, the contact layer7, the insulating film10, the first electrode12, and the second electrode13.

In the orientation of the light receiving element array1shown inFIG.1A, the four rows shall be referred to as a first, second, third, and fourth rows from an upper side of the sheet surface ofFIG.1Aand the four columns shall be referred to as a first, second, third, and fourth columns from a left side of the sheet surface ofFIG.1A. Identification numbers are respectively assigned to the plurality of light receiving elements30, for example, as follows: 1 to 4: the first column to the fourth column of the first row; 5 to 8: the first column to the fourth column of the second row; 9 to 12: the first column to the fourth column of the third row; and 13 to 16: the first column to the fourth column of the fourth row.

In this preferred embodiment, the substrate2is constituted of an n-type InP substrate. The n-type impurity is, for example, S (sulfur) and the impurity concentration is approximately 1×1018cm−3to 5×1018cm−3. In this preferred embodiment, a thickness of the substrate2is approximately 180 μm. Here, the substrate2may instead be a semi-insulating substrate.

The buffer layer3is a buffer layer that buffers strain resulting from mismatch of a lattice constant of the light absorbing layer4formed on the buffer layer3and a lattice constant of the substrate2. In this preferred embodiment, the buffer layer3is constituted of an n-type InP layer. The n-type impurity is, for example, Si (silicon) and the impurity concentration is approximately 1×1018cm−3to 5×1018cm−3. A thickness of the buffer layer3is approximately 100 nm to 200 nm.

The light absorbing layer4has chamfered portions4aat four corner portions. An outer side surface of each chamfered portion4ais formed to an arcuate shape that projects inward in plan view. In this preferred embodiment, the light absorbing layer4is constituted of a non-doped InGaAs layer. A thickness of the light absorbing layer4is approximately 2 μm to 5 μm.

In this preferred embodiment, the window layers5are each of square shape in plan view. In this preferred embodiment, the plurality of window layers5are disposed in a matrix in plan view. More specifically, the plurality of window layers5are disposed side by side at equal intervals in the lateral direction and the longitudinal directions. In this preferred embodiment, the plurality of window layers5include 16 window layers5of four rows and four columns.

The n-type layer6has chamfered portions6aat four corner portions corresponding to the four corner portions of the light absorbing layer4. An outer side surface of each chamfered portion6ais formed to an arcuate shape that projects inward in plan view. In this preferred embodiment, the window layers5and the n-type layer6are constituted of n-type InP layers. The n-type impurity is, for example, Si (silicon) and the impurity concentration is approximately 1×1016cm−3to 5×1017cm−3. A thickness of the window layers5and the n-type layer6is approximately 0.5 μm to 1.5 μm.

The first p-type regions8are formed by Zn (zinc) being diffused into the window layers5and the light absorbing layer4from surfaces of the window layers5at an opposite side to the light absorbing layer4. The concentration of Zn is approximately 2×1018cm−3at surface layer portions of the window layers5. In this preferred embodiment, the first p-type regions8are of circular shapes in plan view. The first p-type regions8extend from the surfaces of the window layers5to an intermediate thickness of the light absorbing layer4.

The second p-type region9is formed by Zn (zinc) being diffused into the light absorbing layer4from a surface of the light absorbing layer4at an opposite side to the substrate2. The concentration of Zn is approximately 2×1018cm−3at a surface layer portion of the light absorbing layer4. The second p-type region9is formed in a lattice in plan view in a central region of the light absorbing layer4. That is, the second p-type region9is constituted, in plan view, of a plurality of first portions91that extend in the lateral direction at equal intervals in the longitudinal direction and a plurality of second portions92that extend in the longitudinal direction at equal intervals in the lateral direction and intersect with the plurality of first portions. The second p-type region9with a plurality of endless shapes (rectangular annular shapes in this example) that surround each of the respective window layers5in plan view is formed by the plurality of first portions91and the plurality of second portions92.

In this preferred embodiment, the second p-type region9extends from the surface of the light absorbing layer4to an intermediate thickness of the light absorbing layer4. Here, the second p-type region9may penetrate through the light absorbing layer4from the surface of the light absorbing layer4and reach the buffer layer3as indicated by alternate long and two short dashed lines9A inFIG.2.

In this preferred embodiment, the contact layers7are constituted of p-type InGaAs layers. The p-type impurity is, for example, Zn (zinc) and the impurity concentration is approximately 1×1019cm−3to 2×1019cm−3. A thickness of the contact layers7is approximately 100 nm. The contact layers7are of endless shapes (circular annular shapes in this example) in plan view and are formed on peripheral edge portions of front surfaces of the first p-type regions8. That is, lower surfaces of the contact layers7contact the front surfaces of the first p-type regions8.

The insulating film10covers the exposed surface of the light absorbing layer4, the exposed surfaces of the window layer5, the exposed surface of the n-type layer6, and the contact layers7. Further, the insulating film10covers portions of exposed surfaces of the respective corner portions of the buffer layer3in vicinities of the chamfered portions4aof the light absorbing layer4. Contact holes11of circular annular shapes in plan view that expose width direction intermediate portions of front surfaces of the contact layers7of circular annular shape in plan view across entire circumferences are formed in the insulating film10. Chamfered portions10aare formed at four corner portions of the insulating film10. An outer side surface of each chamfered portion10ais formed to an arcuate shape that projects inward in plan view.

In this preferred embodiment, the insulating film10is constituted of an SiN film. In this preferred embodiment, a thickness of the insulating film10is set to approximately 200 nm such as to prevent reflection of light of a wavelength of 1500 nm. That is, in this preferred embodiment, the insulating film10is an antireflection film that prevents reflection of light of a predetermined wavelength. The thickness of the insulating film10is set according to the wavelength of the light the reflection of which is to be prevented. The wavelength of the light the reflection of which is to be prevented is set in advance.

The first electrodes12are of endless shapes (circular annular shapes in this example) in plan view and are formed on the insulating film10such as to cover the contact holes11. A portion of each first electrode12enters into the contact hole11and contacts the front surface of the contact layer7inside the contact hole11. The first electrodes12are thereby electrically connected to the first p-type regions8via the contact layers7. In this preferred embodiment, the first electrodes12are each constituted of a laminated Ti/Pt/Au film in which a Ti film, a Pt film, and an Au film are laminated in that order from a lower layer.

The second electrode13is electrically connected to the buffer layer3via the substrate2. In this preferred embodiment, the second electrode13is constituted of a laminated Ti/Pt/Au film in which a Ti film, a Pt film, and an Au film are laminated in that order on the second main surface2bof the substrate2.

The third electrodes14are respectively formed on the exposed surfaces of the four corner portions of the buffer layer3. That is, the third electrodes14are electrically connected to the buffer layer3. The third electrodes14may be used to examine characteristics of the light receiving elements30in a manufacturing process of the light receiving element array1. In this preferred embodiment, the third electrodes14are each constituted of a laminated Ti/Pt/Au film in which a Ti film, a Pt film, and an Au film are laminated in that order from a lower layer.

The plurality of bonding pads15are formed on peripheral edge portions of a front surface of the insulating film10. Specifically, four each of the bonding pads15are formed respectively in edge portions corresponding to respective sides of the insulating film10. Also, the plurality of wirings16that respectively connect the first electrodes12of the plurality of light receiving elements30to respectively different bonding pads15are formed on the front surface of the insulating film10.

Further, the single first mark17of a + (plus sign) shape in plan view and the three second marks18of L shapes in plan view are formed on the front surface of the insulating film10such as to enable recognition of identification numbers of the respective light receiving elements30. In this preferred embodiment, the first mark17is formed near an upper left corner portion of the front surface of the insulating film10and the second marks are respectively formed near other three corner portions of the front surface of the insulating film10. By these marks17and18, it is made possible to recognize the identification numbers assigned to the plurality of light receiving elements30.

In this preferred embodiment, the bonding pads15, the wirings16, and the marks17and18are constituted of the same materials as the electrodes12and14. As shall be described below, the bonding pads15, the wirings16, and the marks17and18are prepared in the same step as the first electrodes12and the third electrodes14.

The light receiving element array1is used in a state where an external wiring is connected between the respective bonding pads15and the second electrode13. A power source for generating an internal electric field in the light absorbing layer4is connected to the external wiring. When light is made incident on the light absorbing layer4from upper surfaces of the light receiving elements30, electrons and holes are generated inside the light absorbing layer4. The electrons generated inside the light absorbing layer4move to the second electrode13side due to the internal electric field and the holes generated inside the light absorbing layer4move to the first electrode12side due to the internal electric field. Thereby, an electric current flows to an external circuit.

In the first preferred embodiment, the second p-type region9is formed in the light absorbing layer4such as to surround each of the plurality of window layers5(light receiving elements30) in plan view. Thereby, when light is made incident on a certain light receiving element30, the electrons and holes generated inside the light absorbing layer4of the certain light receiving element30can be suppressed from moving to an adjacent light receiving element30. Crosstalk can thereby be reduced. The crosstalk refers to a phenomenon where, due to light made incident on a certain light receiving element, an electric current leaks to an adjacent light receiving element.

FIG.4shows a light receiving element array101in which, in contrast to the light receiving element array1shown inFIG.1toFIG.3, a window layer5is formed integrally across substantially an entirety of the front surface of the light absorbing layer4and the second p-type region9is not formed inside the light absorbing layer4. Even in the light receiving element array101, the light receiving elements30are formed for each first p-type region8. InFIG.4, portions corresponding to respective portions ofFIG.2described above are indicated with the same reference signs attached as inFIG.2.

In the following, a sample of the light receiving element array101shown inFIG.4is referred to at times as a first sample. Also, a sample of the light receiving element array1shown inFIG.1toFIG.3is referred to at times as a second sample.

With each of the first sample and the second sample, an electric current (hereinafter referred to as the “first electric current I1”) that flows through a certain light receiving element30when light of 1 mW is made incident on the certain light receiving element, an electric current (hereinafter referred to as the “second electric current I2”) that flows through a light receiving element adjacent to a certain light receiving element when light of 1 mW is made incident on the certain light receiving element, and a dark current were measured. The dark current is an electric current that flows through a light receiving element when light is not made incident on the light receiving element.

FIG.5is a graph showing measurement results for the first sample andFIG.6is a graph showing measurement results for the second sample. InFIG.5andFIG.6, a straight line a represents a graph of the first current I1, a straight line b represents a graph of the second current I2, and a dot group c of circular points represents a graph of the dark current.

FromFIG.5andFIG.6, it can be understood that with the second sample, the second current is greatly lowered in comparison to the first sample. Also, if {(I2/I1)×100} is deemed to be a crosstalk characteristic [%], whereas the crosstalk characteristic was 2.32% with the first sample, the crosstalk characteristic was 0.13% with the second sample. That is, it can be understood that with the second sample, the crosstalk is greatly decreased in comparison to the first sample. It can also be understood that with the second sample, the dark current is reduced in comparison to the first sample.

FIG.7AtoFIG.7Kare sectional views for describing an example of a manufacturing process of the light receiving element array1described above and are sectional views corresponding to a section plane ofFIG.2.FIG.8AtoFIG.8Kare sectional views for describing the example of the manufacturing process of the light receiving element array1described above and are sectional views corresponding to a section plane ofFIG.3.

First, as shown inFIG.7AandFIG.8A, the buffer layer (for example, the n-type InP layer)3and the light absorbing layer (for example, the InGaAs layer)4are epitaxially grown successively on the first main surface2aof the substrate (for example, n-type InP substrate)2by, for example, an MOCVD (metal organic chemical vapor deposition) method. Further, a window material layer (for example, an n-type InP layer)41that is a material layer of the window layers5and the n-type layer6and a contact material layer (for example, p-type InGaAs layer)42that is a material layer of the contact layers are epitaxially grown successively on the light absorbing layer4by the MOCVD method. As the substrate2, that which is thicker than the thickness of the substrate2at a final stage is used.

Next, as shown inFIG.7BandFIG.8B, regions of the contact material layer42other than regions corresponding to being regions in which the first p-type regions8are to be formed are removed by photolithography and etching. Thereby, the contact material layers42remain just in regions of a window material layer41front surface in which the first p-type regions8are to be formed.

Next, as shown inFIG.7CandFIG.8C, the window material layer41is patterned by photolithography and etching. The plurality of window layers5and the n-type layer6are thereby formed on the light absorbing layer4. The plurality of window layers5are formed such as to be disposed in a matrix in the central portion region of the front surface of the light absorbing layer4. The n-type layer6is formed on the peripheral edge portion of the front surface of the light absorbing layer4excluding the four corner portions such as to surround the window layer group. The n-type layer6having the chamfered portions6aat corner portions corresponding to the four corner portions of the light absorbing layer4is thereby obtained.

Next, as shown inFIG.7DandFIG.8D, an insulating film43for masking is formed over all exposed front surfaces by a plasma CVD method, LPCVD (low pressure CVD) method, MOCVD method, sputtering method, etc.

Next, as shown inFIG.7EandFIG.8E, from the insulating film43, portions covering front surfaces (upper surfaces) of the contact material layers42and a portion covering a region of the front surface of the light absorbing layer4in which the second p-type region9is to be formed are removed by photolithography and etching. First opening portions43afor forming the first p-type regions8and a second opening portion43bfor forming the second p-type region9are thereby formed in the insulating film43.

Next, as shown inFIG.7FandFIG.8F, the insulating film43is used as a mask to make Zn diffuse into the contact material layers42, the window layers5, and the light absorbing layer4via the first opening portions43aand make Zn diffuse into the light absorbing layer4via the second opening portion43b. The first p-type regions8are thereby formed inside the window layers5and the light absorbing layer4and the second p-type region9is formed inside the light absorbing layer4. Thereafter, the insulating film43is removed.

Next, as shown inFIG.7GandFIG.8G, the contact material layers42are patterned by photolithography and etching. The contact layers7of circular annular shapes in plan view that contact the peripheral edge portions of first p-type region8front surfaces are thereby formed on the respective window layers5. The laminated semiconductor structure20that includes the buffer layer3, the light absorbing layer4, the window layers5, the n-type layer6, and the contact layers7is thereby obtained.

Next, as shown inFIG.7HandFIG.8H, the four corner portions of the light absorbing layer4are removed by photolithography and etching. The chamfered portions4aare thereby formed at the four corner portions of the light absorbing layer4.

Next, as shown inFIG.7IandFIG.8I, an insulating material film44that is a material film of the insulating film10is formed over all exposed front surfaces by the plasma CVD method, LPCVD method, MOCVD method, sputtering method, etc.

Next, as shown inFIG.7JandFIG.8J, for each window layer5, the contact hole11that exposes a portion of the contact layer7is formed in the insulating material film44by photolithography and etching. Also, from the insulating material film44on the four corner portions of the buffer layer3front surface, portions other than portions in the vicinities of the chamfered portions4aof the light absorbing layer4are removed. The insulating film10having the chamfered portions10aat the four corner portions is thereby obtained. The four corner portions of the buffer layer3front surface are thereby exposed.

Next, an electrode film that is a material film of the first electrodes12, the third electrodes14, the bonding pads15, the wirings16, and the marks17and18is formed by an electron beam vapor deposition method, sputtering method, etc., such as to cover the exposed surfaces of the corner portions of the buffer layer3and the insulating film10. The electrode film is then patterned by photolithography and etching. Thereby, the plurality of first electrodes12, the plurality of bonding pads15, the plurality of wirings16, and the plurality of marks17and18are formed on the insulating film10and the third electrodes14are respectively formed on the four corner portions of the buffer layer3as shown inFIG.7KandFIG.8K.

Lastly, film-thinning of the substrate2is performed by grinding the substrate2from the second main surface2bside. The second electrode13is then formed on the second main surface2bof the thinned substrate2. The light receiving element array1such as shown inFIG.1AtoFIG.3is thereby obtained.

FIG.9is a sectional view for describing the arrangement of a light receiving element array according to a second preferred embodiment of the present disclosure.FIG.9is a sectional view corresponding to the section plane ofFIG.2. InFIG.9, portions corresponding to respective portions ofFIG.2described above are indicated with the same reference signs attached as inFIG.2.

The light receiving element array1A shown inFIG.9differs from the light receiving element array1shown inFIG.1AtoFIG.3in the point that the second p-type region9is not formed in the light absorbing layer4, the point that a separating groove50is formed in the light absorbing layer4such as to surround the window layers5in plan view, and the point that inner surfaces (bottom surface and side surfaces) of the separating groove50are covered by the insulating film10. Structures besides the above are the same as the structures of the light receiving element array1shown inFIG.1AtoFIG.3. With the light receiving element array1A according to the second preferred embodiment, since the second p-type region9is not present, regions corresponding to the first p-type regions8of the light receiving element array1according to the first preferred embodiment shall be referred to as the p-type regions8.

Plan views of the light receiving element array1A according to the second preferred embodiment are the same asFIG.1AandFIG.1Bthat are plan views of the light receiving element array1according to the first preferred embodiment. However, since the second p-type region9is not present in the light receiving element array1A according to the second preferred embodiment, broken lines expressing the second p-type region9inFIG.1Bshould be deemed to be broken lines expressing the separating groove50. In other words, the region inFIG.1Badded with dots should be deemed to be the region in which the separating groove50is formed.

The separating groove50is formed in a lattice in plan view in the central region of the light absorbing layer4. That is, the separating groove50is constituted, in plan view, of a plurality of first portions (portions indicated by the reference sign50inFIG.9) that extend in the lateral direction at equal intervals in the longitudinal direction and a plurality of second portions (portions not appearing inFIG.9) that extend in the longitudinal direction at equal intervals in the lateral direction and intersect with the plurality of first portions. The separating groove50with a plurality of rectangular annular shapes that surround each of the respective window layers5in plan view is formed by the plurality of first portions and the plurality of second portions.

In this preferred embodiment, the separating groove50penetrates through the light absorbing layer4from the front surface of the light absorbing layer4and reaches the buffer layer3. The separating groove50may instead extend from the front surface of the light absorbing layer4to an intermediate thickness of the light absorbing layer4.

In the second preferred embodiment, the separating groove50is formed in the light absorbing layer4such as to surround each of the plurality of window layers5(light receiving elements30) in plan view. Thereby, when light is made incident on a certain light receiving element30, the electrons and holes generated inside the light absorbing layer4of the certain light receiving element30can be suppressed from moving to an adjacent light receiving element30. The crosstalk can thereby be reduced.

In the following, a sample of the light receiving element array1A shown inFIG.9is referred to at times as a third sample. With the third sample, the electric current (first electric current I1) that flows through a certain light receiving element when light of 1 mW is made incident on the certain light receiving element, the electric current (second electric current I2) that flows through a light receiving element adjacent to a certain light receiving element30when light of 1 mW is made incident on the certain light receiving element, and the dark current were measured.

FIG.10is a graph showing measurement results for the third sample. InFIG.10, a straight line a represents a graph of the first current I1, a straight line b represents a graph of the second current I2, and a dot group c of circular points represents a graph of the dark current.

FromFIG.5andFIG.10, it can be understood that with the third sample, the second current is greatly lowered in comparison to the first sample. Also, if {(I2/I1)×100} is deemed to be the crosstalk characteristic [%], whereas the crosstalk characteristic was 2.32% with the first sample, the crosstalk characteristic was 0.12% with the third sample. That is, it can be understood that with the third sample, the crosstalk is greatly decreased in comparison to the first sample. It can also be understood that with the third sample, the dark current is reduced in comparison to the first sample.

FIG.11AtoFIG.11Hare sectional views for describing an example of a manufacturing process of the light receiving element array1A described above and are sectional views corresponding to a section plane ofFIG.9.

Even in manufacturing the light receiving element array1A, the same steps as those ofFIG.7AtoFIG.7Cdescribed above are performed. When the step ofFIG.7Cends, the separating groove50that is disposed such as to surround each of the window layers5in plan view is formed in the light absorbing layer4by photolithography and etching as shown inFIG.11A.

Next, as shown inFIG.11B, the insulating film43for masking is formed over all exposed front surfaces by the plasma CVD method, LPCVD method, MOCVD method, sputtering method, etc.

Next, as shown inFIG.11C, portions covering the front surfaces (upper surfaces) of the contact material layers42are removed from the insulating film43by photolithography and etching. The opening portions43afor forming the p-type regions8are thereby formed in the insulating film43.

Next, as shown inFIG.11D, the insulating film43is used as a mask to make Zn diffuse into the contact material layers42, the window layers5, and the light absorbing layer4via the opening portions43a. The p-type regions8are thereby formed inside the window layers5and the light absorbing layer4. Thereafter, the insulating film43is removed.

Next, as shown inFIG.11E, the contact material layers42are patterned by photolithography and etching. The contact layers7of circular annular shapes in plan view that contact the peripheral edge portions of the first p-type region8front surfaces are thereby formed on the respective window layers5. The laminated semiconductor structure20that includes the buffer layer3, the light absorbing layer4, the window layers5, the n-type layer6, and the contact layers7is thereby obtained.

Next, the four corner portions of the light absorbing layer4are removed by photolithography and etching. The chamfered portions4aare thereby formed at the four corner portions of the light absorbing layer4.

Next, as shown inFIG.11F, the insulating material film44that is the material film of the insulating film10is formed over all exposed front surfaces by the plasma CVD method, LPCVD method, MOCVD method, sputtering method, etc.

Next, as shown inFIG.11G, for each window layer5, the contact hole11that exposes a portion of the contact layer7is formed in the insulating material film44by photolithography and etching. Also, from the insulating material film44on the four corner portions of the buffer layer3front surface, the portions other than the portions in the vicinities of the chamfered portions4aof the light absorbing layer4are removed. The insulating film10having the chamfered portions10aat the four corner portions is thereby obtained. The four corner portions of the buffer layer3front surface are thereby exposed.

Next, the electrode film that is the material film of the first electrodes12, the third electrodes14, the bonding pads15, the wirings16, and the marks17and18is formed by the electron beam vapor deposition method, sputtering method, etc., such as to cover the exposed portions of the front surfaces of the four corner portions of the buffer layer3and the insulating film10. The electrode film is then patterned by photolithography and etching. Thereby, the plurality of first electrodes12, the plurality of bonding pads15, the plurality of wirings16, and the plurality of marks17and18are formed on the insulating film10and the third electrodes14are respectively formed on the four corner portions of the buffer layer3as shown inFIG.11H.

Lastly, film-thinning of the substrate2is performed by grinding the substrate2from the second main surface2bside. The second electrode13is then formed on the second main surface2bof the thinned substrate2. The light receiving element array1A such as shown inFIG.19is thereby obtained.

Although with the first and second preferred embodiments described above, the light receiving element arrays1and1A each include 16 light receiving elements30, it suffices that the light receiving element arrays1and LA each include a plurality of light receiving elements and the number of light receiving elements can be set arbitrarily.

Also, although the plurality of light receiving elements30are disposed two-dimensionally, these may be disposed one-dimensionally instead.

Although the first p-type regions8are of circular shapes in plan view, these may be of polygonal shapes, such as quadrilateral shapes (square shapes, rectangular shapes, etc.), regular hexagonal shapes, etc., in plan view instead.

Also, in each of the first and second preferred embodiments described above, the respective conductivity types of the substrate2of the n-type, the buffer layer3of the n-type, the window layers5of the n-type, and the n-type layer6of the n-type and the respective conductivity types of the contact layers7of the p-type, the first p-type regions8of the p-type, and the second p-type region9of the p-type may be inverted. That is, a portion of the n-type may be made to be of the p-type and a portion of the p-type may be made to be of the n-type.

While preferred embodiments of the present disclosure were described in detail above, these are merely specific examples used to clarify the technical contents of the present disclosure and the present disclosure should not be interpreted as being limited to these specific examples and the scope of the present disclosure is limited only by the appended claims.

The present application corresponds to Japanese Patent Application No. 2021-047583 filed on Mar. 22, 2021 in the Japan Patent Office, and the entire disclosure of this application is incorporated herein by reference.