Semiconductor device having reduced thickness, electronic product employing the same, and methods of fabricating the same

A semiconductor device capable of reducing a thickness, an electronic product employing the same, and a method of fabricating the same are provided. The method of fabricating a semiconductor device includes preparing a semiconductor substrate having first and second active regions. A first transistor in the first active region includes a first gate pattern and first impurity regions. A second transistor the second active region includes a second gate pattern and second impurity regions. A first conductive pattern is on the first transistor, wherein at least a part of the first conductive pattern is disposed at a same distance from an upper surface of the semiconductor substrate as at least a part of the second gate pattern. The first conductive pattern may be formed on the first transistor while the second transistor is formed.

BACKGROUND OF THE INVENTION

1. Field of the Invention

Example embodiments relate to a semiconductor device, to an electronic product employing the same, and to methods of fabricating the same. More particularly, example embodiments relate to a semiconductor device having a reduced thickness, an electronic product employing the same, and methods of fabricating the same.

2. Description of the Related Art

Lately, to meet a demand for smaller semiconductor chips that are used for electronic products and require lower power consumption, research into reducing the size of an element constituting the semiconductor chips is being progressively carried out.

SUMMARY OF THE INVENTION

Embodiments are therefore directed to a semiconductor device, an electronic product employing the same, and to methods of fabricating the same, which substantially overcome one or more of the disadvantages of the related art.

It is therefore a feature of an example embodiment to provide a semiconductor device structure having a reduced thickness.

It is another feature of an example embodiment to provide an electronic product including a semiconductor device structure having a reduced thickness.

It is yet another feature of an example embodiment to provide a method of fabricating a semiconductor device having a reduced thickness.

At least one of the above and other features and advantages may be realized by providing a semiconductor device, including a semiconductor substrate having first and second active regions. A first transistor in the first active region of the semiconductor substrate is provided. The first transistor includes first impurity regions and a first gate pattern. A second transistor in the second active region of the semiconductor substrate is provided. The second transistor includes second impurity regions and a second gate pattern. A first conductive pattern is formed on the first transistor. At least a part of the first conductive pattern is disposed at a same distance above an upper surface of the semiconductor substrate as at least a part of the second gate pattern.

The first transistor may include the conductive first gate pattern provided in a gate trench crossing the first active region, the first impurity regions provided in the first active region at both sides of the first gate pattern, and a first gate dielectric layer provided between the first gate pattern and the gate trench.

An insulating first gate capping pattern filling the gate trench together with the first gate pattern may be further included. The first gate capping pattern may have a projection higher than the first active region above the upper surface of the substrate.

A first contact structure configured to electrically connect one of the first impurity regions to the first conductive pattern may be further included.

The second transistor may include the second gate pattern crossing the second active region, a second gate dielectric layer provided between the second gate pattern and the active region, and second impurity regions provided in the second active region at both sides of the second gate pattern. Here, the second gate pattern may include a first gate electrode and a second gate electrode, which are sequentially stacked, and the second gate electrode may be disposed at the substantially same level as the first conductive pattern.

The semiconductor device may further include a cell contact structure electrically connected to one of the first impurity regions, and a data storage element provided on the cell contact structure.

The data storage element may be disposed at a higher level than the first conductive pattern.

A conductive buffer pattern provided between the cell contact structure and the data storage element may be further included.

The data storage element may include one of a data storage material layer of a volatile memory device, and a data storage material layer of a non-volatile memory device.

A second conductive pattern disposed at a higher level than the first conductive pattern, and a second contact structure configured to electrically connect one of the second impurity regions to the second conductive pattern may be further included.

The cell contact structure and the second contact structure may have upper surfaces disposed at different levels. Alternatively, the cell contact structure and the second contact structure may have upper surfaces disposed at the substantially same level.

A connection structure configured to electrically connect the first and second conductive patterns may be further included.

According to another example embodiment, an electronic product including a semiconductor chip is provided. The semiconductor chip of the electronic product includes a semiconductor substrate having a cell array region and a peripheral circuit region. A cell transistor on the semiconductor substrate of the cell array region, and including first impurity regions and a first gate pattern may be provided. A peripheral transistor on the semiconductor substrate of the peripheral circuit region, and including second impurity regions, and a first peripheral gate electrode and a second peripheral gate electrode, which are sequentially stacked on the substrate between the second impurity regions, is provided. A cell bit line on the cell transistor of the cell array region, and having at least a part at a same distance from an upper surface of the semiconductor substrate as at least a part of the second peripheral gate electrode may be provided.

According to still another example embodiment, a method of fabricating a semiconductor device capable of having a reduced thickness is provided. The method includes preparing a semiconductor substrate having first and second active regions, forming a first transistor the first active region including a first gate pattern and first impurity regions, forming, in the second active region, a second transistor including a second gate pattern and second impurity regions, and forming a first conductive pattern on the first transistor. At least a part of the first conductive pattern is disposed at a same distance from an upper surface of the semiconductor substrate as at least a part of the second gate pattern. The first conductive pattern may be formed while the second transistor is formed.

Forming the first and second transistors and the first conductive pattern may include forming the first impurity regions in the first active region, forming a gate trench crossing the first active region, forming the first gate pattern filling at least a part of the gate trench, forming a gate conductive pattern in the second active region, forming a buffer insulating pattern on the first active region, forming a first conductive layer covering the buffer insulating pattern and the gate conductive pattern, and patterning the first conductive layer on the buffer insulating pattern, and the gate conductive pattern and the first conductive layer, which are sequentially stacked on the second active region so that the first conductive pattern may be formed on the buffer insulating pattern, and a first gate electrode and a second gate electrode, which are sequentially stacked, may be formed on the second active region.

After forming the first gate pattern, forming a first gate capping pattern to fill the gate trench together with the first gate pattern on the first gate pattern may be further included. The first gate capping pattern may have a projection at a higher level than the first active region.

The buffer insulating pattern may be formed after the gate conductive pattern is formed. Alternatively, the gate conductive pattern may be formed after the buffer insulating pattern is formed.

Before forming the first conductive pattern, forming a first contact structure configured to pass through the buffer insulating pattern, and electrically connected to one of the first impurity regions may be further included. The first conductive structure may be electrically connected to the first conductive pattern.

Forming a first interlayer insulating layer on the substrate having the first conductive pattern, forming a cell contact structure configured to pass through the first interlayer insulating layer, and electrically connected to one of the first impurity regions, and forming a data storage element on the cell contact structure may be further included.

While forming the cell contact structure, forming a peripheral contact structure configured to pass through the first interlayer insulating layer and electrically connected to one of the second impurity regions, and forming a second conductive pattern electrically connected to the peripheral contact structure on the first interlayer insulating layer may be further included.

While forming the second conductive pattern, forming a buffer pattern electrically connected to the cell contact structure on the first interlayer insulating layer may be further included.

Meanwhile, forming a second interlayer insulating layer on the first interlayer insulating layer, forming a second contact structure configured to pass through the first and second interlayer insulating layers, and electrically connected to one of the second impurity regions, and forming a second conductive pattern on the second interlayer insulating layer may be further included.

According to yet another example embodiment, a method of fabricating a semiconductor device is provided. The method includes preparing a semiconductor substrate having first and second regions. An insulating pattern is formed on the semiconductor substrate of the first region. A conductive pattern is formed on the semiconductor substrate of the second region. A conductive layer covering the conductive pattern and the insulating pattern is formed. The conductive layer and the conductive pattern are patterned, so that an interconnection is formed on the insulating pattern, and a first gate electrode and a second gate electrode, which are sequentially stacked, are formed on the semiconductor substrate of the second region.

DETAILED DESCRIPTION OF THE INVENTION

Korean Patent Application Nos. 10-2007-0094725, filed on Sep. 18, 2007, and 10-2008-0083457, filed on Aug. 26, 2008, in the Korean Intellectual Property Office, and entitled: “Semiconductor Device Having Reduced Thickness, Electronic Product Employing the Same, and Methods of Fabricating the Same,” are incorporated by reference herein in their entirety.

As used herein, the expressions “at least one,” “one or more,” and “and/or” are open-ended expressions that are both conjunctive and disjunctive in operation. For example, each of the expressions “at least one of A, B, and C,” “at least one of A, B, or C,” “one or more of A, B, and C,” “one or more of A, B, or C” and “A, B, and/or C” includes the following meanings: A alone; B alone; C alone; both A and B together; both A and C together; both B and C together; and all three of A, B, and C together. Further, these expressions are open-ended, unless expressly designated to the contrary by their combination with the term “consisting of.” For example, the expression “at least one of A, B, and C” may also include an nth member, where n is greater than 3, whereas the expression “at least one selected from the group consisting of A, B, and C” does not.

As used herein, the terms “a” and “an” are open terms that may be used in conjunction with singular items or with plural items.

A semiconductor device according to an example will be described in more detail below with reference toFIG. 1.FIG. 1illustrates a cross-sectional view of a semiconductor device according to an example embodiment.

Referring toFIG. 1, a semiconductor device may include a semiconductor substrate500, first and second transistors AT1and AT2on the semiconductor substrate500, and a first conductive pattern539apositioned on the first transistor AT1to have at least one portion at a substantially same height, e.g., above an upper surface500aof the semiconductor substrate500along a first direction, i.e., the y-axis, as a portion of a second gate pattern540of the second transistor AT2.

The semiconductor substrate500may have a first region A1, a second region A2, and an intermediate region B. The semiconductor substrate500may be a semiconductor wafer including a semiconductor material such as silicon. The first region A1may be a memory cell array region, and the second region A2may be a peripheral circuit region. The intermediate region B may correspond to a predetermined region between a first device, e.g., a cell transistor, on the first region A1, and a second device, e.g., a peripheral transistor, on the second region A2. It is noted that while the intermediate region B is illustrated inFIG. 1as an independent region between the first region A1and the second region A2, other configurations of the intermediate region B, e.g., the intermediate region B may be disposed in a memory cell array region such as the first region A1or may be disposed in a peripheral circuit region such as the second region A2, are within the scope of the present invention.

An isolation region503sdefining first and second active regions503aand503bmay be provided in the semiconductor substrate500. The isolation region503smay be a trench isolation layer. The isolation region503smay define the first active region503a, e.g., a cell active region, in the first region A1, and may define the second active region503b, e.g. a peripheral active region, in the second region A2.

The first transistor AT1may be provided in the first active region503a. The first transistor AT1may include first impurity regions518aand518bin the first active region503a, a first channel region between the first impurity regions518aand518b, a first gate dielectric layer521, and a first gate pattern524. The first transistor AT1may have a recess channel, so the first gate dielectric layer521and first gate pattern524may be sequentially stacked in a gate trench515in the first channel region. The first gate pattern524may be a cell gate electrode.

More specifically, a gate trench515may be formed in the semiconductor substrate500. The gate trench515may have a predetermined depth along a first direction, e.g., along the y-axis, from an upper surface500aof the semiconductor substrate500in a downward direction, and may cross the first active region503a. The gate trench515may extend toward the isolation region503s. The first gate pattern524may be provided in the gate trench515, so the first gate pattern524may cross the first active region503aand extend toward the isolation region503s.

For example, the first gate pattern524may partially fill the gate trench515, so a first gate capping pattern527may fill a remaining portion of the gate trench515. In other words, as illustrated inFIG. 1, the first gate pattern524and the first gate capping pattern527may be sequentially stacked on each other in the gate trench515, so an upper surface of the first gate capping pattern527may be substantially level, i.e., coplanar, with the upper surface500aof the semiconductor substrate500. The first gate capping pattern527may be formed of an insulating material layer.

The first gate dielectric layer521may be interposed between an internal wall of the gate trench515and the first gate pattern524, e.g., the first gate dielectric layer521may be on an entire internal wall of the gate trench515. The first impurity regions518aand518bmay be provided in upper regions of the first active region503a, i.e., upper surfaces of the first impurity regions518aand518bmay be substantially level with the upper surface500aof the semiconductor substrate500, at both sides of the gate trench515, i.e., the first gate capping pattern527in the gate trench515may be between the first impurity regions518aand518b.

The second transistor AT2may be provided in the second active region503b. The second transistor AT2may include second impurity regions548aand548bin the second active region503b, a second channel region between the second impurity regions548aand548b, a second gate dielectric layer506a, and a second gate pattern540. The second gate dielectric layer506aand second gate pattern540may be sequentially stacked on the second channel region. The second gate pattern540may include a lower gate electrode509gand an upper gate electrode539g, which may be sequentially stacked. An insulation second gate capping pattern542gmay be provided on the second gate pattern540.

The lower gate electrode509gand the upper gate electrode539gmay be formed of a substantially same material or of different materials. For example, the upper gate electrode539gmay be formed of a conductive material having a higher conductivity than the lower gate electrode509g, e.g., the lower gate electrode509gmay include a doped polysilicon layer and the upper gate electrode539gmay include a metal material layer such as a tungsten layer. Taking into account ohmic contact characteristics between a polysilicon layer and a metal material layer, a metal silicide layer may be interposed between the upper gate electrode539gand the lower gate electrode509g. In another example, the upper gate electrode539gand the lower gate electrode509gmay be formed of a substantially same conductive material.

The first conductive pattern539amay be provided on the first transistor AT1with a buffer insulating pattern536therebetween. The buffer insulating pattern536may be provided on the first region A1and intermediate region B of the semiconductor substrate500to cover the first transistor AT1and the first gate capping pattern527. The first conductive pattern539amay be a linear structure, e.g., a shape of a line, provided on the buffer insulating pattern536. The first conductive pattern539amay be defined as a cell bit line. At least a part of the first conductive pattern539amay be disposed at a substantially same height along the first direction, e.g., the y-axis, as at least a part of the second gate pattern540. For example, at least a part of the first conductive pattern539amay be disposed at a substantially same level, i.e., height along the y-axis above the upper surface500aof the semiconductor substrate500, as at least a part of the upper gate electrode539g. In another example, a lower surface of the first conductive pattern539amay be substantially coplanar along the xz-plane with a lower surface of the upper gate electrode539g, so distance from each of the lower surfaces of the first conductive pattern539aand the upper gate electrode539gto, e.g., the upper surface500aof the semiconductor substrate500, may be substantially equal. The first conductive pattern539amay include a substantially same conductive material and may be formed by a substantially same process as the upper gate electrode539g.

A first contact structure538pmay electrically connect one region518aof the first impurity regions518aand518bto the first conductive pattern539a. The first contact structure538pmay pass through the buffer insulating pattern536.

A first insulating capping pattern542amay be provided on the first conductive pattern539a. A first insulating spacer545amay be provided on sidewalls of the first conductive pattern539aand the first insulating capping pattern542a. A second insulating spacer545gmay be provided on sidewalls of the second gate pattern540and the second gate capping pattern542b. The first and second insulating spacers545aand545gmay include a substantially same insulating material layer formed by the same process.

A first interlayer insulating layer551covering the entire surfaces of the first and second regions A1and A2and the intermediate region B of the semiconductor substrate500may be provided. The first interlayer insulating layer551may have a planarized upper surface disposed at a higher level along the first direction, e.g., the y-axis, than upper surfaces of the first insulating capping pattern542aand the second gate capping pattern542g. Alternatively, the first interlayer insulating layer551may have a planarized upper surface disposed at a substantially same level as upper surfaces of the first insulating capping pattern542aand the second gate capping pattern542g, as illustrated inFIG. 1. A second interlayer insulating layer584may be provided on the first interlayer insulating layer551.

A second conductive pattern575may be provided on the second interlayer insulating layer584. The second conductive pattern575may be electrically connected to the first conductive patterns539avia a conductive connection structure572a. The connection structure572amay be interposed between the first and second conductive patterns539aand575, and may sequentially pass through the second interlayer insulating layer584and the first insulating capping pattern542a, as illustrated inFIG. 1.

A second contact structure572binterposed between one region548aof the second impurity regions548aand548band the second conductive pattern575may electrically connect the region548aof the second transistor AT2to the second conductive pattern575. The second contact structure572bmay include a lower contact structure571apassing through the first interlayer insulating layer551, and an upper contact structure571bpassing through the second interlayer insulating layer584. The lower contact structure571aand the upper contact structure571bmay be formed of conductive material layers formed by different processes from each other. Alternatively, the lower contact structure571aand the upper contact structure571bmay be formed of a substantially same material layer formed by a substantially same process.

The semiconductor device may further include a data storage element597on the semiconductor substrate500. The data storage element597may include first and second electrodes, and a data storage material layer provided between the first and second electrodes. The data storage element597may be disposed above one region518bof the first impurity regions518aand518bof the first transistor AT1, and may be electrically connected to the region518bvia a cell contact structure560, as illustrated inFIG. 1. The cell contact structure560may pass through the buffer insulating pattern536and through the first interlayer insulating layer551. That is, the first transistor AT1may be electrically connected to the first conductive pattern539avia the first contact structure538pand one first impurity region518a, and to the data storage element597via the cell contact structure560and the other first impurity region518b.

The data storage element597may include a data storage material layer of a volatile memory device such as DRAM, e.g., a capacitor dielectric layer, but is not limited thereto. For example, the data storage element597may include a ferroelectric material layer of FeRAM or a data storage material layer of a non-volatile memory device, e.g., a phase change material layer of PRAM. The data storage element597may be positioned at a higher level than the first conductive pattern539a, as illustrated inFIG. 1, so, along the y-axis, a distance from a lower surface of the data storage element597from the upper surface500aof the semiconductor substrate500may be larger than a distance from an upper surface of the first conductive pattern539afrom the upper surface500aof the semiconductor substrate500. At least a part of the data storage element597may be disposed at a substantially same level as or a lower level than the second conductive pattern575. For example, as further illustrated inFIG. 1, a lower portion of the data storage element597may pass through the second interlayer insulating layer584.

Arrangement of the data storage element597, first conductive pattern539a, and upper gate electrode539gas described above may minimize a distance between the data storage element597and the first transistor AT1along the first direction, e.g., the y-axis, so an overall thickness of the semiconductor device as measured along the first direction may be reduced. In other words, since the first conductive pattern539abetween the data storage element597and the first transistor AT1, i.e., the cell bit line, may be disposed at a substantially same level as the upper gate electrode539gof a peripheral circuit region, i.e., second transistor AT2, both a distance between the first conductive pattern539aand the first active region503aand a distance between the data storage element597and the first active region503amay be minimized. Accordingly, the overall thickness of the semiconductor device may be minimized, and a process margin for forming the cell contact structure560between the data storage element597and the first active region503amay be increased.

A semiconductor device according to another example embodiment will be described below with reference toFIG. 2. Referring toFIG. 2, a semiconductor device may include substantially same elements as the semiconductor device described previously with reference toFIG. 1. Substantially same elements will be indicated as elements “corresponding” to elements described previously and their detailed description will not be repeated.

Referring toFIG. 2, a semiconductor device may include a semiconductor substrate600having first and second regions D1and D2, and an intermediate region E, and first and second active regions603aand603bdefined by an isolation region603s. The semiconductor substrate600with the regions D1, D2, and E, and the active regions603aand603bdefined by the isolation region603smay be substantially the same as the semiconductor substrate500with the regions A1, A2, and B, and the active regions503aand503bdefined by the isolation region503sdescribed previously with reference toFIG. 1, respectively.

As further illustrated inFIG. 2, the semiconductor device may include first and second transistors DT1and DT2on the semiconductor substrate600. The first transistor DT1may include first impurity regions618aand618b, a first gate dielectric layer621, and a first gate pattern624, which correspond to the first impurity regions518aand518b, the first gate dielectric layer521, and the first gate pattern524ofFIG. 1, respectively. The first gate pattern624may be provided in a gate trench615corresponding to the gate trench515ofFIG. 1. The first transistor DT1may further include a first gate capping pattern627on the first gate pattern624in the gate trench615. The first gate capping pattern627may extend above an upper surface600aof the semiconductor substrate600, i.e., may have an upper surface disposed at a higher level than an upper surface of the first active region603a. The first gate capping pattern627may be formed of an insulating material.

The second transistor DT2may include second impurity regions648aand648b, a second gate dielectric layer606a, and a second gate pattern640, which correspond to the second impurity regions548aand548b, the second gate dielectric layer506a, and the second gate pattern540ofFIG. 1, respectively. The second gate pattern640may include a lower gate electrode609gand an upper gate electrode639g, which are sequentially stacked. A second gate capping pattern642gand a second insulating spacer645g, which respectively correspond to the second gate capping pattern542gand a second insulating spacer545gofFIG. 1, may be provided on the semiconductor substrate600of the second region D2.

A buffer insulating pattern636covering the isolation region603sand the first impurity regions618aand618bmay be provided on the first region D1and the intermediate region E of the semiconductor substrate600. The buffer insulating pattern636may be formed of an insulating material having an etch selectivity with respect to the first gate capping pattern627. For example, when the first gate capping pattern627includes a silicon nitride layer, the buffer insulating pattern636may include a silicon oxide layer.

As further illustrated inFIG. 2, the semiconductor device may include a first conductive pattern639a, a first insulating capping pattern642a, a first insulating spacer645a, and a first contact structure638p, which correspond to the first conductive pattern539a, the first insulating capping pattern542a, the first insulating spacer545a, and the first contact structure538pdescribed previously with reference toFIG. 1, respectively. A first interlayer insulating layer651corresponding to the first interlayer insulating layer551ofFIG. 1may be provided on the first and second regions D1and D2, and the intermediate region E of the semiconductor substrate600.

A cell contact structure660passing through the first interlayer insulating layer651and the buffer insulating pattern636, and electrically connected to one region618bof the first impurity regions618aand618bmay be provided. A portion of the first gate capping pattern627projected above the first impurity regions618aand618bmay be disposed between the cell contact structure660and the first contact structure638p, as illustrated inFIG. 2. Therefore, the projection of the first gate capping pattern627may prevent short circuiting between the cell contact structure660and the first contact structure638p. Portions of the first gate dielectric layer621may be disposed between the first gate capping pattern627and each of the cell contact structure660and the first contact structure638p.

A second contact structure672bpassing through the first interlayer insulating layer651and electrically connected to one region648aof the first impurity regions648aand648bmay be provided. The second contact structure672bmay be provided at the substantially same level as the cell contact structure660, e.g., upper surfaces of the second contact structure672band cell contact structure660may be substantially coplanar and lower surfaces of the second contact structure672band cell contact structure660may be substantially coplanar along the xz plane. The second contact structure672band the cell contact structure660may include a substantially same conductive material.

As further illustrated inFIG. 2, the semiconductor device may further include a conductive buffer pattern675band a second conductive pattern675aon the first interlayer insulating layer651. The conductive buffer pattern675bmay cover the cell contact structure660, and the second conductive pattern675amay cover the second contact structure672b. The conductive buffer pattern675band the second conductive pattern675amay be spaced apart along the x-axis, and may be disposed at a substantially same level, e.g., lower surfaces of the conductive buffer pattern675band the second conductive pattern675amay be substantially coplanar along the xz-plane. The conductive buffer pattern675band the second conductive pattern675amay be formed of a substantially same material.

A connection structure672amay be interposed through the first insulating capping pattern642ato connect the first and second conductive patterns639aand675a. For example, the first conductive pattern639a, the connection structure672a, and the second conductive pattern675amay be sequentially stacked, so the connection structure672amay be interposed between the first and second conductive patterns639aand675a, and may electrically connect the first and second conductive patterns639aand675a.

A second interlayer insulating layer684may be disposed on the first interlayer insulating layer651to surround sidewalls of the conductive buffer pattern675band of the second conductive pattern675a. For example, upper surfaces of the second interlayer insulating layer684, conductive buffer pattern675b, and second conductive pattern675amay be substantially coplanar in the xz-plane.

As further illustrated inFIG. 2, the semiconductor device may further include a data storage element697on the conductive buffer pattern675b. Accordingly, the data storage element697may be positioned at a higher level than the second conductive pattern675a, i.e., a lower surface of the data storage element697may be further from the upper surface600aof the semiconductor substrate600than an upper surface of the second conductive pattern675a. The data storage element697may correspond to the data storage element597ofFIG. 1in terms of type and components.

Methods of fabricating a semiconductor device according to example embodiments of will be described below with reference toFIG. 3-19.FIG. 3illustrates a plan view of a semiconductor device according to an example embodiments,FIGS. 4A-12Billustrate cross-sectional views of a method of fabricating a semiconductor device according to an example embodiment,FIGS. 13A-17Billustrate cross-sectional views of a method of fabricating a semiconductor device according to another example embodiment, andFIGS. 18A-19illustrate cross-sectional views of a method of fabricating a semiconductor device according to still another example embodiment.

It is noted thatFIGS. 4A,5A,6A,7A,8A,9A,10A,11A,12A,13A,14A,15A,16A,17A and18A illustrate sequential cross-sectional views along line I-I′ ofFIG. 3, andFIGS. 4B,5B,6B,7B,8B,9B,10B,11B,12B,13B,14B,15B,16B,17B,18B and19illustrate cross-sectional views along line II-II′ ofFIG. 3. InFIGS. 3-19, reference mark C represents a first region, reference mark M represents an intermediate region, and reference mark P represents a second region.

First, a method of fabricating a semiconductor device according to an example embodiment will be described below with reference toFIGS. 3, and4A-12B.

Referring to FIGS.3and4A-4B, a semiconductor device may include a semiconductor substrate1having first and second regions C and P, and an intermediate region M, and first and second active regions3aand3bdefined by an isolation region3s. The semiconductor substrate1with the regions C, P, and M, and the active regions3aand3bdefined by the isolation region3smay correspond to the semiconductor substrate500with the regions A1, A2, and B, and the active regions503aand503bdefined by the isolation region503sdescribed previously with reference toFIG. 1, respectively.

A preliminary impurity region (not shown) having a different conductivity type as compared to region C of the semiconductor substrate1may be formed in the first active region3a. For example, when the first active region3ais a P type, impurity ions may be implanted into the first active region3a, so that a preliminary impurity region (not shown) of an N-type may be formed in an upper region of the first active region3a.

A dielectric layer6and a gate conductive layer9, which may be sequentially stacked, may be formed on the semiconductor substrate1. The dielectric layer6may be formed to include at least one of a silicon oxide layer and high K dielectrics. Here, the high K dielectrics may include a dielectric material having a higher dielectric constant than a silicon oxide layer. The gate conductive layer9may be formed of a conductive material layer, e.g., a polysilicon layer.

The gate conductive layer9and the dielectric layer6on the first region C may be patterned to expose predetermined portions of first active region3aand the isolation region3s. Then, the exposed portions of the first active region3aand the isolation region3smay be etched to form a gate trench15. The gate trench15may be formed to cross the first active region3aand extend toward the isolation region3s. The gate trench15may have a smaller line width than a resolution limit of a lithography process.

The gate trench15may be formed to cross the first active region3ain the preliminary impurity region. Therefore, the preliminary impurity region may be divided into cell impurity regions spaced apart from each other by the gate trench15, i.e., the gate trench15may define cell source/drain regions18aand18b. For example, the preliminary impurity region may be divided into three cell impurity regions18aand18bby a pair of gate trenches15. If three cell impurity regions are formed, one impurity region disposed between the pair of gate trenches15may be defined as a first cell impurity region18a, and the remaining impurity regions may be defined as second impurity regions18b.

Referring toFIGS. 3,5A-5B, a cell gate dielectric layer21may be formed on the semiconductor device having the cell gate trench15. The cell gate dielectric layer21may be formed to coat an internal wall of the cell gate trench15in the first active region3a. The cell gate dielectric layer21may be formed to include at least one of a silicon oxide layer and high K dielectric layer.

A cell gate pattern24may be formed on cell gate dielectric layer21in the cell gate trench15. The cell gate pattern24may fill at least a part of the gate trench15. For example, the cell gate pattern24may partially fill the gate trench15, so an upper surface of the first active region3amay be higher than an upper surface of the cell gate pattern24along the y-axis, i.e., the upper surface of the first active region3amay be further from a bottom of the gate trench15than the upper surface of the cell gate pattern24. The cell gate pattern24at a portion crossing the cell active region3amay be defined as a cell gate electrode. The cell gate pattern24may be formed to include at least one of a metal layer, a metal nitride layer, a metal silicide layer, and a polysilicon layer. The cell source/drain regions18, the cell gate dielectric layer21, and the cell gate pattern24may constitute cell transistors CT1and CT2. That is, the cell transistors CT1and CT2may be buried channel array transistors (BCAT).

A cell gate capping pattern27filling a remaining portion of the gate trench15may be formed. The cell gate capping pattern27may be formed on the cell gate pattern24to include at least one of a silicon oxide layer, a silicon nitride layer, and a silicon oxynitride layer.

A mask pattern30may be formed on the gate conductive layer9in the second region P, so a portion of the gate conductive layer9in the first region C and the intermediate region M may be exposed by the mask pattern30. The mask pattern30may be a photoresist pattern. Alternatively, the mask pattern30may be formed of an insulating layer, e.g., a silicon oxide layer or a silicon nitride layer.

Referring to FIGS.3and6A-6B, the gate conductive layer9in the first region C and the intermediate region M may be etched using the mask pattern30as an etch mask to form a gate conductive pattern9ain the second region P. It is noted that in other embodiments, i.e., an example embodiment including a different method of fabricating the first impurity regions18aand18bas compared to the method described previously, the gate conductive pattern9amay be used to perform an ion implantation process on the substrate1to form first impurity regions, i.e., cell source/drain regions18aand18b, in the cell active region3a. It is further noted that while the first region C, the intermediate region M, and the second region P are etched, a part of the dielectric layer6, the cell gate dielectric layer21, and the cell gate capping pattern27may be etched.

Once the gate conductive pattern9ais formed, the mask pattern30may be removed. A stop layer33may be formed on a portion of the semiconductor substrate1from which the mask pattern30was removed. The stop layer33may be formed of an insulating material having an etch selectivity with respect to the isolation region3s. For example, when the isolation region3sis formed of a silicon oxide layer, the stop layer33may be formed of a silicon nitride layer. The stop layer33may be conformally formed. The stop layer33may cover the isolation region3sand the cell transistors CT1and CT2of the first region C, and may cover the gate conductive pattern9ain the second region P.

A buffer insulating layer (not shown) may be formed on the stop layer33. The buffer insulating layer may be formed of a material layer having an etch selectivity with respect to the stop layer33. For example, when the stop layer33is formed of a silicon nitride layer, the buffer insulating layer may be formed of a silicon oxide layer. The buffer insulating layer may be planarized to expose an upper surface of the stop layer33in M region and an upper surface of the gate conductive pattern9ain the second region P, so that a planarized buffer insulating pattern36may be formed on the stop layer33in the first region C.

Referring to FIGS.3and7A-7B, a capping insulating layer37may be formed on the buffer insulating pattern36. The capping insulating layer37may be formed of an insulating material such as a silicon oxide layer or a silicon nitride layer. The capping insulating layer37, the buffer insulating pattern36, and the stop layer33may be patterned to form a bit line contact hole36aexposing the first impurity region18a. For example, the bit line contact hole36amay be formed to expose the first cell impurity region18asharing the cell transistors CT1and CT2.

A first conductive layer38may be formed on the semiconductor substrate1having the bit line contact hole36a. The first conductive layer38may be formed to include at least one of a metal layer, a metal nitride layer, a metal silicide layer and a polysilicon layer. For example, the first conductive layer38may be formed to include a Ti layer, a TiN layer, and a W layer, which are sequentially stacked. Here, the W layer may fill the bit line contact hole36a, and the Ti and the TiN layers, which are sequentially stacked, may be interposed between an internal wall of the bit line contact hole36aand the W layer to function as a diffusion barrier layer.

A portion of the first conductive layer38in contact with the first impurity region18amay be formed of metal silicide. For example, a metal silicide layer may be formed on the first impurity region18a, and a metal material layer may fill the bit line contact hole36ato form the first conductive layer38. In another example, first and second may be sequentially deposited in the bit line contact hole36a, followed by an annealing process of the metal layers, so that a metal of the first metal layer may react with silicon of the first impurity region18ato form a metal silicide layer between the first conductive layer38and the first impurity region18a.

Referring to FIGS.3and8A-8B, the first conductive layer38may be processed to form a first contact structure, i.e., a bit line contact structure38p, in the bit line contact hole36a. For example, the first conductive layer38may be planarized, e.g., by a chemical mechanical polishing (CMP), to expose the stop layer33in the second region P, followed by etching of the stop layer33. In another example, the first conductive layer38may be planarized to expose the gate conductive pattern9ain the second region P. The capping layer37may be removed during the planarization process.

Next, a second conductive layer39covering the bit line contact structure38pand the exposed gate conductive pattern9amay be formed. The second conductive layer39may be formed to include at least one of a metal layer, a metal nitride layer, a metal silicide layer, and a polysilicon layer. In an example embodiment, the second conductive layer39may be formed to include a different conductive material from the gate conductive pattern9a. The second conductive layer39may be formed to include a conductive material layer having a higher electric conductivity than the gate conductive pattern9a. For example, the gate conductive pattern9amay be formed of a doped polysilicon layer, and the second conductive layer39may be formed to include a metal material layer such as a tungsten layer. Here, taking into account ohmic contact characteristics between a metal material layer such as a tungsten layer and the gate conductive pattern9a, a portion of the second conductive layer39being in contact with the gate conductive pattern9amay be formed of a metal silicide layer. In another example embodiment, the gate conductive pattern9aand the second conductive layer39may be formed of a substantially same conductive material layer.

In some example embodiments, after the buffer insulating pattern36ofFIGS. 7A and 7Bis formed, or while forming the buffer insulating pattern36, a process of exposing the gate conductive pattern9ain the second region P may be performed. For example, the buffer insulating layer36may be planarized to expose the gate conductive pattern9a, so the stop layer33in the second region P may be removed during the planarization process. In another example, after the buffer insulating layer36is planarized using the stop layer33as a planarization stop layer33in the second region P, the stop layer33in the second region P may be etched, so the buffer insulating pattern36and the stop layer33may be patterned to form the bit line contact hole36aexposing the first impurity region18a. A conductive layer filling the bit line contact hole36aand covering the buffer insulating pattern36and the gate conductive pattern9a, e.g., a conductive layer of the same material layer as the first conductive layer38, may be formed. Accordingly, the second conductive layer39and the bit line contact structure38pmay be formed to include the same material layer formed by the same process.

Referring to FIGS.3and9A-9B, a mask layer may be formed on the second conductive layer39. The mask layer may be formed to include at least one of a silicon oxide layer, a silicon nitride layer and a silicon oxynitride layer. The mask layer, the second conductive layer39, and the gate conductive pattern9amay be patterned, so that a first conductive pattern39aand a bit line capping pattern42a, which are sequentially stacked, may be formed on the first region C, and a first peripheral gate electrode9g, a second peripheral gate electrode39g, and a peripheral capping pattern42b, which are sequentially stacked on the second region P, may be formed. Accordingly, the first conductive pattern39aand the second peripheral gate electrode39gmay be simultaneously formed and may be formed of the same material layer. Further, the first conductive pattern39aand the second peripheral gate electrode39gmay be disposed substantially at the same level.

The first and second peripheral gate electrodes9gand39gmay be defined as a peripheral gate pattern40. The first conductive pattern39amay be defined as a cell bit line. The peripheral gate pattern40and the first conductive pattern39amay respectively correspond to the peripheral gate pattern540ofFIG. 1 and 640ofFIG. 2and the first conductive pattern539aofFIG. 1 and 639aofFIG. 2. The cell bit line39amay extend up to the intermediate region M. The peripheral gate pattern40may be substantially linear, and may extend on the isolation region3scrossing the peripheral active region3band defining the peripheral active region3b. Moreover, a peripheral gate dielectric layer6amay be provided between the peripheral gate pattern40and the peripheral active region3b.

A bit line spacer45amay be formed on a sidewall of the cell bit line39aand the bit line capping pattern42a, which are sequentially stacked. A peripheral gate spacer45gmay be formed on sidewalls of the peripheral gate pattern40and the peripheral gate capping pattern42g, which are sequentially stacked. The peripheral gate spacer45gand the bit line spacer45amay be formed to include at least one of a silicon nitride layer, a silicon oxynitride layer, and a silicon oxide layer.

Impurity ions may be implanted into the peripheral active region3bat both sides of the peripheral gate pattern40to be activated, so that peripheral impurity regions, i.e., peripheral source/drain regions48, may be formed. Therefore, a peripheral transistor PT1including the peripheral source/drain regions48, the peripheral gate dielectric layer6a, the peripheral gate pattern40and a channel region in the peripheral active region3bunder the peripheral gate pattern40may be formed.

Referring toFIGS. 3,10A and10B, a first interlayer insulating layer51may be formed on the semiconductor substrate1having the cell bit line39aand the peripheral transistor PT1. The first interlayer insulating layer51may be formed to have a substantially planarized upper surface. For example, an insulating material layer may be formed on the semiconductor substrate1having the cell bit line39aand the peripheral transistor PT1, and a planarization process, e.g., the CMP process, may be performed on the insulating material layer, so that the first interlayer insulating layer51having the planarized upper surface may be formed. During the planarization process for forming the first interlayer insulating layer51, the bit line capping pattern42aand the peripheral gate capping pattern42gmay be used. Therefore, while the first interlayer insulating layer51may have the planarized upper surface as illustrated inFIG. 1, it is not limited thereto, and the first interlayer insulating layer51may have a planarized upper surface so that upper surfaces of the bit line capping pattern42aand the peripheral gate capping pattern42gare exposed.

In the first region C, the first interlayer insulating layer51, the buffer insulating pattern36, and the stop layer33may be sequentially patterned, so that cell contact holes54exposing the second cell impurity regions18bout of the first and second impurity regions18aand18bof the first region C may be formed.

In some embodiments, since the cell bit line39ais disposed substantially at the same level as the second peripheral gate electrode39gof the peripheral transistor PT2, the overall thickness of the device is not increased due to the cell bit line39a. Accordingly, the cell contact holes54may be substantially formed by etching the insulating layers of thicknesses formed by forming the peripheral transistor PT1. This process may reduce an etching process time required to form the cell contact holes54, and increase an etching process margin. Further, since the cell bit line39aand the second peripheral gate electrode39gmay be simultaneously formed without any separate process for forming the cell bit line39a, the overall process time may be reduced.

Cell contact structures60filling the cell contact holes54may be formed. The cell contact structures60may be formed to include at least one of a metal layer, a metal nitride layer, a metal silicide layer, and a polysilicon layer. For example, the cell contact structures60may include a metal layer filling the cell contact holes54, and may include a diffusion barrier layer interposed between the metal layer and internal walls of the cell contact holes54. Also, a portion in contact with the second cell impurity regions18bexposed by a lower region of the cell contact structures60, i.e., the cell contact holes54, may be formed of a metal silicide layer. For example, a metal silicide layer may be formed on the second cell impurity regions18b, and a conductive material layer filling the cell contact holes54may be formed, so that the cell contact structures60may be formed. Alternatively, forming the cell contact structures60may include performing an annealing process on a metal layer and a metal nitride layer sequentially covering internal walls of the cell contact holes54, and reacting a metal element of the metal layer with a silicon element of the second cell impurity regions18bto form a metal silicide layer.

Referring toFIGS. 3,11A and11B, a second interlayer insulating layer63may be formed on the first interlayer insulating layer51. In the second region P, a peripheral contact hole66bpassing through the first and second interlayer insulating layers51and63, and exposing at least one of the peripheral impurity regions48may be formed. Moreover, in the intermediate region M, a connection via hole66apassing through the second interlayer insulating layer63and the bit line capping pattern42a, and exposing a predetermined region of the cell bit line39amay be formed.

A connection structure75afilling the connection via hole66amay be formed, and a conductive peripheral contact structure72bfilling the peripheral contact hole66bmay be formed. The connection structure75aand the peripheral contact structure72bmay be formed to include at least one of a metal layer, a metal nitride layer, a metal silicide layer, and a polysilicon layer.

The peripheral contact structure72bmay be formed to include a different conductive material from the cell contact structure60. For example; when the cell contact structure60includes a polysilicon layer, the peripheral contact structure72bmay include a metal material layer, e.g., tungsten.

A second conductive pattern75and an interconnection capping pattern78, which are sequentially stacked, may be formed on the second interlayer insulating layer63. The second conductive pattern75may cover the connection structure75aand the peripheral contact structure72b. The second conductive pattern75may be formed to include at least one of a metal layer, a metal nitride layer, and a polysilicon layer. The interconnection capping pattern78may be formed of an insulating material layer such as a silicon nitride layer. Forming the interconnection capping pattern78may be omitted.

In another example embodiment, the second conductive pattern75, the connection structure75a, and the peripheral contact structure72bmay be simultaneously formed of a conductive material. For example, a conductive material layer filling the connection via hole66aand the peripheral contact hole66band covering the second interlayer insulating layer63may be formed, and the conductive material layer may be patterned to integrally form the second conductive pattern75, the connection structure75a, and the peripheral contact structure72b.

The cell transistors CT1and the peripheral transistor PT1may be electrically connected to each other by the second conductive pattern75. More specifically, one of the peripheral impurity regions48of the peripheral transistor PT1and the cell impurity region18aof the cell transistors CT1and CT2may be electrically connected to each other through the bit line contact structure38p, the first conductive pattern39a, the connection structure75a, the second conductive pattern75and the peripheral contact structure72b. An interconnection spacer81may be formed on sidewalls of the second conductive pattern75and the interconnection capping pattern78.

Referring toFIGS. 3,12A, and12B, a third interlayer insulating layer84may be formed on the semiconductor substrate having the second conductive pattern75. The third interlayer insulating layer84may be planarized. An etch stop layer87may be formed on the third interlayer insulating layer84.

A data storage element97passing through the etch stop layer87, the third interlayer insulating layer84, and the second interlayer insulating layer63, and electrically connected to the cell contact structures60and upwardly projecting above the etch stop layer87along the y-axis, may be formed. The data storage element97may include a first electrode90, a second electrode96, and a data storage material layer93between the first and second electrodes90and96.

When a DRAM is used as an example memory device, the data storage material layer93may include a cell capacitor dielectric material of a DRAM. However, the example embodiment of the inventive concept is not limited to DRAMs, and may be used for various semiconductor devices. Accordingly, depending on characteristics of a device that the data storage material layer93requires, e.g., various data storage materials, such as a phase change material layer of a PRAM or a ferroelectric material layer of a FeRAM, may be used.

Meanwhile, while it is illustrated that the first electrode90is in the shape of a cylinder inFIG. 12A, the shape is not limited thereto, and may be embodied in different shapes depending on characteristics of a device. For example, the first electrode90may be formed in various shapes such as a pillar or a plate.

Next, referring toFIGS. 3, and13A to16B, a method of fabricating a semiconductor device according to another example embodiment of the inventive concept will be described below.

Referring toFIGS. 3,13A and13B, a semiconductor substrate100having the first region C, the second region P, and the intermediate region M may be prepared. First and second active regions103aand103b, an isolation region103s, a dielectric layer106, a gate conductive layer, a gate trench115, cell impurity regions118aand118b, a cell gate dielectric layer121, a cell gate pattern124, a cell gate capping pattern127, and cell transistors CT3and CT4, which correspond to the first and second active regions3aand3b, an isolation region3s, a dielectric layer6, the gate conductive layer9, the gate trench15, the cell impurity regions18aand18b, the cell gate dielectric layer21, the cell gate pattern24, the cell gate capping pattern27, and the cell transistors CT1and CT2, respectively, may be formed using substantially the same method as those ofFIGS. 4 and 5.

As illustrated inFIG. 13B, a mask pattern130may be formed on the gate conductive layer of the second region P, and the gate conductive layer may be etched to form a gate conductive pattern109aremaining on the second region P. In the example embodiment of the inventive concept, the cell gate capping pattern127may remain to have a portion projecting from an upper surface of the first active region103awhile the gate conductive pattern109ais formed. That is, the cell gate capping pattern127may remain to have a projection filling the cell gate pattern124and the gate trench115, and an upper surface thereof may be disposed at a higher level along the y-axis than an upper surface of the first active region103a. While the gate conductive pattern109ais formed, at least a part of the dielectric layer106and the cell gate dielectric layer121may be etched.

In other example embodiments, an ion implantation process may be performed on the substrate100where the gate conductive pattern109ais formed, so that impurity regions118aand118bmay be formed in the first active region103a.

Referring toFIGS. 3,14A and14B, the mask pattern (130ofFIG. 13B) may be removed. Then, a stop layer133may be conformally formed on the resulting structure. A buffer insulating layer may be formed on the stop layer133. The buffer insulating layer may be planarized until the stop layer133or the gate conductive pattern109aon the second region P is exposed, so that a buffer insulating pattern136may be formed. When the stop layer133remains on the gate conductive pattern109awhile the buffer insulating pattern136is formed, the stop layer133on the gate conductive pattern109amay be removed.

When the buffer insulating layer is planarized, e.g., using the CMP process, a projection of the cell gate capping pattern127on the first region C may function as a planarization stop layer. For example, when the cell gate capping pattern127is formed of a silicon nitride layer, and the buffer insulating layer is formed of a silicon oxide layer, the cell gate capping pattern127may be used as a planarization stop layer. Therefore, a dishing phenomenon in the first region C may be prevented while the planarization process is performed on the buffer insulating layer. Thus, the buffer insulating pattern136may have a planarized upper surface where the dishing phenomenon is significantly reduced.

Referring toFIGS. 3,15A and15B, the buffer insulating pattern136and an insulating material under the buffer insulating pattern136, e.g., the stop layer133, on the first active region103aof the first region C may be patterned to form a bit line contact hole136aexposing the first cell impurity region118a. A part of sidewalls of the bit line contact hole136amay be defined by the projections of the cell gate capping patterns127. Therefore, in order to form the bit line contact hole136a, a photo process margin when a photoresist pattern is formed on the buffer insulating pattern136may be increased.

A first conductive layer may be formed on the entire surface of the semiconductor substrate having the buffer insulating pattern136. The first conductive layer portion defined by the bit line contact hole136amay be defined as a first contact structure138p.

A bit line capping pattern142aand a peripheral capping pattern142bmay be formed on the first conductive layer, and the first conductive layer and the gate conductive pattern (109aofFIGS. 14A and 14B) may be sequentially etched using the bit line capping pattern142aand the peripheral gate capping pattern142bas etch masks. As a result, a first conductive pattern, i.e., a cell bit line139a, may be formed on the first region C and the intermediate region M, and a first peripheral gate electrode109gand a second peripheral gate electrode139g, which are sequentially stacked, may be formed on the second region P. The first and second peripheral gate electrodes109gand139gmay constitute a peripheral gate pattern140. Therefore, at least a part of the cell bit line139amay be formed to be disposed at a substantially same level along the y-axis as at least a part of the peripheral gate pattern140.

The cell bit line139amay cover an upper portion of the bit line contact hole136a. Therefore, the first contact structure138ain the bit line contact hole136amay be connected to the cell bit line139aand may be formed of the same material. A peripheral gate dielectric layer106amay be provided between the peripheral gate pattern140and the peripheral active region.

A bit line spacer145amay be formed on sidewalls of the cell bit line139aand the bit line capping pattern142a. A peripheral gate spacer145gmay be formed on sidewalls of the peripheral gate pattern140and the peripheral gate capping pattern142g.

Impurity ions may be implanted into the second active region103bat both sides of the peripheral gate pattern140to be activated, so that peripheral impurity regions, i.e., peripheral source/drain regions148, may be formed. Therefore, a peripheral transistor PT2including the peripheral source/drain regions148, the peripheral gate dielectric layer106a, the peripheral gate pattern140, and a channel region in the second active region103bunder the peripheral gate pattern140, may be formed.

Referring toFIGS. 3,16A and16B, a first interlayer insulating layer151may be formed on the substrate having the peripheral transistor PT2. The first interlayer insulating layer151may be formed to have a planarized upper surface. For example, an insulating material layer may be formed on the substrate having the peripheral transistor PT2, and a planarization process may be performed on the insulating material layer, so that the first interlayer insulating layer151having a planarized upper surface may be formed. The planarization process may be performed using the CMP process employing the bit line capping pattern142aand the peripheral gate capping pattern142gas planarization stop layers.

In the first region C, cell contact holes154apassing through the first interlayer insulating layer151, the buffer insulating pattern136, and the stop layer133, and exposing the second cell impurity regions118bmay be formed. Cell contact structures160afilling the cell contact holes154amay be formed.

In the second region P, a peripheral contact hole154bpassing through the first interlayer insulating layer151and exposing at least one of the peripheral impurity regions148may be formed. A peripheral contact structure filling the peripheral contact hole154bmay be formed. The cell and peripheral contact holes154aand154bmay be simultaneously formed. Also, the cell and peripheral contact structures160aand160bmay be simultaneously formed. Therefore, the cell and peripheral contact structures160aand160bmay be formed of the same conductive material.

Referring toFIGS. 3,17A and17B, in the intermediate region M, a connection via hole161passing through the bit line capping pattern42sand exposing a predetermined region of the cell bit line139amay be formed. A third conductive layer filling the connection via hole161may be formed, and the third conductive layer may be patterned, so that buffer patterns175acovering the cell contact structures160a, and a second conductive pattern175bcovering the connection via hole161and the peripheral contact structure160bmay be formed. The third conductive layer in the connection via hole161may be defined as a connection structure175p. Accordingly, the second conductive pattern175bmay be connected to the cell bit line139athrough the connection structure175p, and may be electrically connected to the peripheral transistor PT2, i.e., one of the peripheral impurity regions148, through the peripheral contact structure160b.

In another example embodiment of the inventive concept, the connection structure175pand the peripheral contact structures160aand160bmay be simultaneously formed.

In another example embodiment, the buffer patterns175aand the second conductive pattern175bmay be formed using a damascene process. For example, a second interlayer insulating layer184may be formed on the substrate having the cell and peripheral contact structures160aand160b, and holes in a damascene structure for forming the buffer patterns175aand the second conductive pattern175bmay be formed in the second interlayer insulating layer184, a conductive material layer filling the holes may be formed, and the conductive material layer may be planarized, so that the buffer patterns175aand the second conductive pattern175b, which are defined in the holes, may be formed.

An etch stop layer187covering the buffer patterns175aand the second conductive pattern175bmay be formed. Then, data storage elements197electrically connected to the buffer patterns175amay be formed on the buffer patterns175a. The data storage elements197may be used as a data storage unit of a volatile or non-volatile memory device.

Next, still another example embodiment of the inventive concept will be described below with reference toFIGS. 18A,18B and19.

Referring toFIGS. 3,18A, and18B, a semiconductor substrate200having the first region C, the second region P and the intermediate region M may be prepared as illustrated inFIGS. 4A and 4B. An isolation region203sdefining active regions203aand203bmay be provided in the semiconductor substrate200using the same method as that ofFIGS. 4A and 4B. A preliminary impurity region may be formed in the first active region203a.

A stop layer206and a buffer insulating layer209, which are sequentially stacked, may be formed on the semiconductor substrate200. The stop layer206may include a material layer having an etch selectivity with respect to the isolation region203s. The buffer insulating layer209may be formed of a single layer formed of an insulating material. Alternatively, the buffer insulating layer209may be a multilayer having different etch selectivities, i.e., different material layers. For example, the buffer insulating layer209may be formed of a first material layer, e.g., as a silicon oxide layer, and a second material layer, e.g., a polysilicon layer or a silicon nitride layer. The second material layer may be formed on the first material layer.

The buffer insulating layer209on the semiconductor substrate of the first region C may be patterned, so that an opening exposing predetermined regions of the first active region203aand the isolation region203smay be formed. Further, the first active region203aand the isolation region203s, which are exposed by the opening, may be etched, so that a gate trench215illustrated inFIG. 18Amay be formed. The preliminary impurity region may be divided by the gate trench215to form first and second impurity regions218aand218b.

A cell gate dielectric layer221and a cell gate pattern224may be sequentially formed in the cell gate trench215using the same method asFIG. 5A. Therefore, cell transistors CT5and CT6may be formed in the first active region203a.

A cell gate capping pattern227filling the remaining portion of the cell gate trench215and having a portion projecting from the upper surface of the first active region203amay be formed. The cell gate capping pattern227may be formed to include at least one of a silicon oxide layer, a silicon nitride layer and a silicon oxynitride layer.

Meanwhile, when the buffer insulating layer209includes a first material layer and a second material layer, which are sequentially stacked, the second material layer may be removed while the cell gate capping pattern227is formed or after the cell gate capping pattern227is formed.

Referring toFIGS. 3 and 19, the buffer insulating layer209and the stop layer206may be patterned to expose the second active region203of the second region P, and to form a buffer insulating pattern209aremaining on the first region P and the intermediate region M. Afterwards, a gate dielectric layer210and a gate conductive pattern211, which are sequentially stacked, may be formed on the substrate of the second region P.

The gate dielectric layer210and the gate conductive pattern211may respectively correspond to the gate dielectric layer6and106ofFIGS. 6B and 14Band a gate conductive pattern9aand109a, which are sequentially stacked on the second active region3band103bofFIGS. 6B and 14B. While a method of forming the buffer insulating pattern209a, the gate dielectric layer210and the gate conductive pattern211ofFIG. 19may be different from a method of forming the buffer insulating pattern36and136, the dielectric layer6and106and the gate conductive pattern9aand109aofFIGS. 6B and 14B, the resultant structures are similar. Therefore, the previously described elements such as the first conductive pattern39aand139a, the second conductive pattern175b, and the data storage element97and197may be formed on the semiconductor substrate having the buffer insulating pattern209a, the gate dielectric layer210and the gate conductive pattern211.

FIG. 20schematically illustrates products employing a semiconductor device according to example embodiments of the inventive concept. Referring toFIG. 20, a semiconductor chip710employing the semiconductor device according to the previously described example embodiments may be provided. For example, an integrated circuit and a data storage unit may be formed on a semiconductor wafer in a bulk state having a plurality of chip regions using the method according to the previously described example embodiments. As described above, the semiconductor wafer where the integrated circuit and the data storage unit are formed may be divided, e.g., along the y-axis, to form a plurality of semiconductor chips710. The semiconductor chip710may be formed in a package. The semiconductor chip710may be adapted for electronic products. The semiconductor chip710may function as a data storage medium. For example, the semiconductor chip710may be used as parts of an electronic product720, which requires a data storage medium, such as a digital TV, a computer, a communication device, an electronic dictionary, or a portable memory device. For example, a packaged semiconductor chip710may be installed on a board or a memory module to be adapted as a part constituting the electronic product.

According to example embodiments of the inventive concept, while a first gate electrode and a second gate electrode are sequentially stacked on a peripheral circuit region, an interconnection such as a cell bit line may be formed on a cell array region. Therefore, the interconnection may be disposed substantially at the same level, i.e., height along the y-axis above the upper surface of the substrate, as the second gate electrode of the peripheral circuit region. As a result, the overall thickness of the device may be reduced.