Series-parallel charge pump with NMOS devices

A charge pump having only NMOS devices charges a plurality of capacitors to a parallel charged voltage level by electrically connecting the capacitors in parallel between an input voltage node and a ground by activating a plurality of first NMOS transistor switches and a plurality of second NMOS transistor switches and deactivating a plurality of third NMOS transistor switches. The charge pump then generates a series capacitor output voltage level at a capacitor series output node by electrically connecting and discharging the capacitors in series between the input voltage node and the capacitor series output node by activating the third NMOS transistor switches and deactivating the first NMOS transistor switches and the second NMOS transistor switches.

BACKGROUND

Series-parallel charge pumps generally charge a set of capacitors in a parallel configuration and then cascade them together in a series configuration to discharge them. The voltage level generated on each capacitor during charging is thus stacked in series during discharging to produce a higher resulting output voltage. NMOS and PMOS transistor switches (n-type and p-type metal-oxide-semiconductor field-effect transistor (MOSFET) devices) are typically included together in conventional charge pump circuits for switching the capacitors between the parallel and series configurations.

SUMMARY

In accordance with some embodiments, a method using a charge pump with only NMOS devices includes: charging a plurality of capacitors in to a parallel charged voltage level by electrically connecting the capacitors in parallel between an input voltage node and a ground by activating a plurality of first NMOS transistor switches and a plurality of second NMOS transistor switches and deactivating a plurality of third NMOS transistor switches; and generating a series capacitor output voltage level at a capacitor series output node by electrically connecting and discharging the capacitors in series between the input voltage node and the capacitor series output node by activating the third NMOS transistor switches and deactivating the first NMOS transistor switches and the second NMOS transistor switches.

In accordance with some embodiments, a charge pump using only NMOS devices includes a plurality of capacitors, a plurality of first NMOS transistor switches, a plurality of second NMOS transistor switches, and a plurality of third NMOS transistor switches. The first NMOS transistor switches and the second NMOS transistor switches are electrically connected to the capacitors to charge the capacitors in parallel between an input voltage node and a ground when the first NMOS transistor switches and the second NMOS transistor switches are activated. The capacitors are charged to a parallel charged voltage level. The third NMOS transistor switches are electrically connected to the capacitors to generate a series capacitor output voltage level at a capacitor series output node by discharging the capacitors in series between the input voltage node and the capacitor series output node when the third NMOS transistor switches are activated. The first NMOS transistor switches and the second NMOS transistor switches are activated when the third NMOS transistor switches are deactivated. The third NMOS transistor switches are activated when the first NMOS transistor switches and the second NMOS transistor switches are deactivated.

In accordance with some embodiments, an improved charge pump includes a plurality of capacitors, a plurality of first switches, a plurality of second switches, a plurality of third switches, and a plurality of resistors. Each of the capacitors has a high voltage node and a low voltage node. The first switches and the second switches are electrically connected to the capacitors to charge the capacitors in parallel between an input voltage node and a ground when the first switches and the second switches are activated. The capacitors are charged to a parallel charged voltage level. The third switches are electrically connected to the capacitors to generate a series capacitor output voltage level at a capacitor series output node by discharging the capacitors in series between the input voltage node and the capacitor series output node when the third switches are activated. Each of the resistors corresponds to one of the capacitors and to one of the third switches. Each of the resistors is electrically connected between the high voltage node of the corresponding one of the capacitors and a gate node of the corresponding one of the third switches. A current through each resistor causes a gate-source voltage of the corresponding one of the third switches that deactivates the corresponding one of the third switches when the first switches and the second switches are activated. Each resistor pulls a gate voltage of the corresponding one of the third switches to a voltage level of the high voltage node of the corresponding one of the capacitors to activate the corresponding one of the third switches when the first switches and the second switches are deactivated.

In some embodiments, the charge pump also includes a plurality of fourth NMOS transistor switches. Each of the fourth NMOS transistor switches corresponds to one of the resistors and to one of the third NMOS transistor switches. Each of the fourth NMOS transistor switches is electrically connected to the corresponding one of the resistors at the gate node of the corresponding one of the third NMOS transistor switches. Each of the fourth NMOS transistor switches is activated to cause the current through the corresponding one of the resistors when the first NMOS transistor switches and the second NMOS transistor switches are activated. The fourth NMOS transistor switches are deactivated when the first NMOS transistor switches and the second NMOS transistor switches are deactivated.

In some embodiments, the charge pump also includes a current source, a fifth NMOS transistor switch, and a sixth NMOS transistor switch. The fifth NMOS transistor switch is electrically connected to the current source. The sixth NMOS transistor switch is electrically connected to the current source and the fifth NMOS transistor switch. The fifth NMOS transistor switch is deactivated when the first NMOS transistor switches and the second NMOS transistor switches are activated, and the fifth NMOS transistor switch is activated when the first NMOS transistor switches and the second NMOS transistor switches are deactivated. Deactivation of the fifth NMOS transistor switch causes the current source and the sixth NMOS transistor switch to generate a gate drive voltage that activates the fourth NMOS transistor switches. Activation of the fifth NMOS transistor switch prevents generation of the gate drive voltage.

DETAILED DESCRIPTION

An example circuit for an improved cascaded, series-parallel charge pump100is shown inFIG. 1, in accordance with some embodiments. The charge pump100generally includes a set of stages having several transistor switches or devices, all of which are N-type laterally diffused MOSFET (NMOS or N-type LDMOS) devices, such as the NMOS/LDMOS devices produced with the ZqFET™ technology from Silanna Semiconductor. NMOS devices typically have much less resistance and/or are much smaller than PMOS devices. The inclusion of the PMOS devices in conventional charge pumps, therefore, places certain design restrictions on the physical layout/size and operating parameters of the resulting circuit for the charge pump. On the other hand, the inclusion of only NMOS devices in the stages of the charge pump100ensures that all of the transistor switches have a relatively low resistance with a relatively small size for greater efficiency and smaller overall size for the charge pump100. Additionally, the breakdown voltage levels of the NMOS and PMOS devices in conventional charge pumps typically lead to further design restrictions or considerations, e.g., with respect to the number of stages that must be used to produce the desired output voltage, the voltage that can be put across each stage, and/or the efficiency or reliability of each stage. For the improved charge pump100, however, the NMOS devices produced with the ZqFET™ technology from Silanna Semiconductor provide a relatively high breakdown voltage that allows for a relatively large voltage across each stage of the charge pump100, thereby relieving or relaxing the affected design restrictions or considerations. Furthermore, the inclusion of both NMOS and PMOS devices in the same integrated circuit places additional requirements on the process steps of the overall manufacturing process for producing conventional charge pumps, since components of both types of devices cannot necessarily be formed in the same steps. However, using generally the same or similar NMOS devices throughout the improved charge pump100enables the devices to be manufactured in generally the same process steps. The physical layout, performance characteristics, and manufacturing processes for the improved charge pump100, therefore, enable the charge pump100to be usable in many more embodiments or applications than is typical for conventional charge pump circuits.

In some embodiments, the charge pump100generally includes first NMOS transistor switches101-104, second NMOS transistor switches105-108, capacitors109-112, resistors113-116, third NMOS transistor switches117-120, fourth NMOS transistor switches121-124, fifth and sixth NMOS transistor switches125and126, a current source127, an output diode128, an output capacitor129, an output resistor130, and an oscillator131, among other components not shown for simplicity. In some embodiments, the charge pump100includes input diodes132-135(shown in dashed lines) in place of the first NMOS transistor switches101-104. The charge pump100generally receives an input voltage Vin at an input voltage node136and produces therefrom an output voltage Vout (a charge pump output voltage level) at an output voltage node137.

The first NMOS transistor switches101-104, the second NMOS transistor switches105-108, the capacitors109-112, the resistors113-116, the third NMOS transistor switches117-120, and the fourth NMOS transistor switches121-124are configured in corresponding stages138-141, respectively. Each component in the stages138-141may be referred to as corresponding to the other components in the same stage. Additionally, each stage138-140(or the components therein) may be referred to as a previous stage (or component) with respect to the stages139-141(or the components therein), respectively; and each stage139-141(or the components therein) may be referred to as a subsequent stage (or component) with respect to the stages138-140(or the components therein), respectively.

Within each stage138-141, the capacitor109-112is electrically connected in parallel between the input voltage Vin at the input voltage node136and a ground (or a reference point for a reference voltage level) through the corresponding first NMOS transistor switch101-104and second NMOS transistor switch105-108when the first NMOS transistor switches101-104and the second NMOS transistor switches105-108are turned on or activated, as described below. Additionally, the capacitors109-112are electrically connected in series through each stage138-141from the input voltage node136to a capacitor series output node142when the third NMOS transistor switches117-120are turned on or activated, as described below.

Four stages138-141are shown in the embodiment ofFIG. 1. However, other embodiments may have any appropriate number of stages (from a first stage138, through any number of intermediate stages139and140, to a final stage141), each with corresponding components101-124therein. The number of stages in a given application may depend on the desired voltage level of the output voltage Vout, the available voltage level of the input voltage Vin, and the voltage level amount that each stage contributes to form the output voltage Vout.

Each of the capacitors109-112has a high voltage side or node (left side of each capacitor109-112as illustrated) and a low voltage side or node (right side of each capacitor109-112as illustrated). Each of the NMOS transistor switches101-108,117-124,125and126generally has a gate node (or activation node), a source node, and a drain node. Each of the resistors113-116generally has a first node (left side of each resistor113-116as illustrated) and a second node (right side of each resistor113-116as illustrated).

For each stage138-141: each of the first NMOS transistor switches101-104is electrically connected between the input voltage node136and the high voltage node of the corresponding one of the capacitors109-112, each of the second NMOS transistor switches105-108is electrically connected between the ground and the low voltage node of the corresponding one of the capacitors109-112, and the third NMOS transistor switches117-120are electrically connected in series with the capacitors109-112. Additionally, the initial third NMOS transistor switch117is electrically connected between the input voltage node136and the low voltage node of the corresponding initial capacitor109, each remaining third NMOS transistor switch118-120is electrically connected between the low voltage node of the corresponding remaining capacitor110-112and the high voltage node of the previous capacitor109-111, respectively, in the series. Furthermore, the first NMOS transistor switches101-104and the second NMOS transistor switches105-108are activated to electrically connect the capacitors109-112in parallel between the input voltage node136and the ground; and the third NMOS transistor switches117-120are activated to electrically connect the capacitors109-112in series between the input voltage node136and the capacitor series output node142.

Therefore, the source node of the corresponding first NMOS transistor switch101-104is electrically connected to the input voltage Vin at the input voltage node136. The gate node of the corresponding first NMOS transistor switch101-104and the gate node of the corresponding second NMOS transistor switch105-108are electrically connected together to a first oscillating voltage signal Vp. The drain node of the corresponding first NMOS transistor switch101-104, the high voltage node of the corresponding capacitor109-112, and the first node of the corresponding resistor113-116are electrically connected together. The low voltage node of the corresponding capacitor109-112and the drain nodes of the corresponding second NMOS transistor switch105-108and the corresponding third NMOS transistor switch117-120are electrically connected together. The second node of the corresponding resistor113-116, the gate node of the corresponding third NMOS transistor switch117-120, and the drain node of the corresponding fourth NMOS transistor switch121-124are electrically connected together. The source nodes of the corresponding second NMOS transistor switch105-108and the corresponding fourth NMOS transistor switch121-124are electrically connected to the ground. The gate node of the corresponding fourth NMOS transistor switch121-124is electrically connected to the drain nodes of the fifth and sixth NMOS transistor switches125and126, the gate node of the sixth NMOS transistor switch126, and an output node of the current source127.

Additionally, for the initial stage138, the source node of the initial third NMOS transistor switch117is electrically connected to the input voltage Vin at the input voltage node136; and the drain node of the initial first NMOS transistor switch101, the high voltage node of the initial capacitor109, and the first node of the initial resistor113are also electrically connected to the source node of the subsequent third NMOS transistor switch118in the subsequent stage139. Also, for the intermediate stages139-140, the drain node of the intermediate first NMOS transistor switch102-103, the high voltage node of the intermediate capacitor110-111, and the first node of the intermediate resistor114-115are also electrically connected to the source node of the subsequent third NMOS transistor switch119-120(of the intermediate and final stages140-141). Furthermore, for the final stage141, the drain node of the final first NMOS transistor switch104, the high voltage node of the final capacitor112, and the first node of the final resistor116are also electrically connected to an anode or input node of the output diode128.

In embodiments using the input diodes132-135, on the other hand, an anode or input node of the input diodes132-135is electrically connected in place of the source node of the corresponding first NMOS transistor switch101-104, a cathode or output node of the input diodes132-135is electrically connected in place of the drain node of the corresponding first NMOS transistor switch101-104, and the first oscillating voltage signal Vp is electrically connected only to the gate node of the corresponding second NMOS transistor switch105-108.

Additionally, an input node of the current source127is electrically connected to the input voltage Vin at the input voltage node136. The source nodes of the fifth and sixth NMOS transistor switches125and126are electrically connected to the ground. The gate node of the fifth NMOS transistor switch125is electrically connected to a second oscillating voltage signal Vn.

A cathode or output node of the output diode128is electrically connected to the output voltage node137, a high voltage node of the output capacitor129, and a first node of the output resistor130. Additionally, a low voltage node of the output capacitor129and a second node of the output resistor130are electrically connected to the ground, so that the output capacitor129and the output resistor130are electrically connected in parallel between the output voltage node137and the ground.

The oscillator131generally has a first (non-inverted) output at which it produces the first (or non-inverted or positive) oscillating voltage signal Vp and a second (inverted) output at which it produces the second (or inverted or negative) oscillating voltage signal Vn. The first oscillator output is electrically connected to the gate nodes of the first and second NMOS transistor switches101-108, and the second oscillator output is electrically connected to the gate node of the fifth NMOS transistor switch125. For embodiments that include the input diodes132-135, the first oscillator output is electrically connected only to the gate nodes of the second NMOS transistor switches105-108.

In operation, the oscillator131produces the first and second oscillating voltage signals Vp and Vn as inverted voltage signals of each other. Thus, the first and second oscillating voltage signals Vp and Vn have the same frequency, but opposite duty cycles. A first portion of each cycle or period of the first and second oscillating voltage signals Vp and Vn corresponds to a parallel charging time period, and a second portion of each cycle or period of the first and second oscillating voltage signals Vp and Vn corresponds to a series discharging time period.

During the parallel charging time period, the first and second NMOS transistor switches101-108are turned on or activated by a high voltage level of the first oscillating voltage signal Vp to electrically connect each of the capacitors109-112in parallel between the input voltage Vin at the input voltage node136(via the first NMOS transistor switches101-104) and the ground (via the second NMOS transistor switches105-108). Thus, an electrical connection is established from the input voltage Vin at the input voltage node136through each of the capacitors109-112in parallel to the ground, so that each of the capacitors109-112can be charged up to a parallel charged voltage level that depends on the voltage level of the input voltage Vin and any voltage drop across each pair of the first and second NMOS transistor switches101-108.

Also, during the parallel charging time period, the fifth NMOS transistor switch125is turned off or deactivated by a low voltage level of the second oscillating voltage signal Vn. Deactivation of the fifth NMOS transistor switch125causes the configuration of the current source127and the sixth NMOS transistor switch126to generate a gate drive bias voltage on the gate nodes of the fourth NMOS transistor switches121-124that turns on or activates the fourth NMOS transistor switches121-124. Activation of the fourth NMOS transistor switches121-124causes each of the fourth NMOS transistor switches121-124to serve as a current source to pull a current through the corresponding resistor113-116and the activated corresponding first NMOS transistor switch101-104. The resistances of the resistors113-116are selected such that the current pulled or flowed therethrough causes a voltage drop across the resistors113-116that results (due to the voltage level of the input voltage Vin and to the configuration of the capacitors109-112, the resistors113-116, and the third NMOS transistor switches117-120) in generating a gate-source voltage of the corresponding third NMOS transistor switches117-120that turns off or deactivates the third NMOS transistor switches117-120. In some embodiments, for example, about 3 V across the resistors113-116maintains the third NMOS transistor switches117-120turned off or deactivated. In this manner, the deactivated third NMOS transistor switches117-120do not affect or interfere with the parallel charging of the capacitors109-112when the first NMOS transistor switches101-104and the second NMOS transistor switches105-108are activated during the parallel charging time period.

During the series discharging time period, on the other hand, the fifth NMOS transistor switch125is turned on or activated by a high voltage level of the second oscillating voltage signal Vn. Activation of the fifth NMOS transistor switch125causes the gate node of the sixth NMOS transistor switch126as well as the gates nodes of the fourth NMOS transistor switches121-124to be pulled to the ground, so that the fourth NMOS transistor switches121-124are turned off or deactivated. Deactivation of the fourth NMOS transistor switches121-124removes the current that was being pulled through the resistors113-116during the parallel charging time period. Without the current through the resistors113-116there is no voltage drop across the resistors113-116, so the second nodes of the resistors113-116and the gate nodes of the third NMOS transistor switches117-120are pulled up to the voltage level of the first nodes of the resistors113-116, or the high voltage nodes of the capacitors109-112. In this situation, the voltage level on the gate nodes of the third NMOS transistor switches117-120causes the third NMOS transistor switches117-120to turn on or be activated. In this manner, the third NMOS transistor switches117-120are turned on or activated to electrically connect, cascade or stack the capacitors109-112in series between the input voltage Vin at the input voltage node136and the capacitor series output node142, which is (or is connected to) the high voltage node of the final capacitor112. Thus, an electrical connection is established from the input voltage Vin at the input voltage node136through each of the capacitors109-112in series to the output voltage node137, so that the capacitors109-112can be discharged in series, such that the voltage across each capacitor109-112is stacked or added in series with each other and with the input voltage Vin to produce a series capacitor output voltage level at the capacitor series output node142.

Also, during the series discharging time period, the first NMOS transistor switches101-104and the second NMOS transistor switches105-108are turned off or deactivated by a low voltage level of the first oscillating voltage signal Vp. In this manner, the first NMOS transistor switches101-104and the second NMOS transistor switches105-108do not affect or interfere with the series discharging of the capacitors109-112during the series discharging time period.

The series capacitor output voltage level at the capacitor series output node142, charges the output capacitor129in an RC circuit formed by the parallel configuration of the output capacitor129and the output resistor130. The output diode128is forward biased to allow current to flow from the capacitor series output node142to the output voltage node137during the series discharging time period when the series capacitor output voltage level is produced from the stacked voltages of the capacitors109-112in series with the input voltage Vin. The output capacitor129is thereby charged to an overall charge pump output voltage level at the output voltage node137. Additionally, the output diode128is reversed biased to prevent current flow (and unnecessary discharge of the output capacitor129) to the capacitor series output node142from the output voltage node137during the parallel charging time period, i.e., when the parallel charged voltage level (which is lower than the overall charge pump output voltage level) is generated on the capacitors109-112in parallel between the input voltage Vin and the ground.

In an ideal situation, i.e., no losses or inefficiencies, the parallel charged voltage level to which each capacitor109-112is charged during the parallel charging time period would be the same as the input voltage Vin. Thus, during the series discharging time period, with the input voltage Vin applied at the low voltage node of the initial capacitor109, the stacked voltage level at the high voltage node of the initial capacitor109would be 2×Vin, the stacked voltage level at the high voltage node of the intermediate capacitor110would be 3×Vin, the stacked voltage level at the high voltage node of the next intermediate capacitor111would be 4×Vin, and the stacked voltage level at the high voltage node of the final capacitor112(i.e., the series capacitor output voltage level and, thus, the overall charge pump output voltage level) would be 5×Vin. However, under realistic conditions, some losses or inefficiencies occur in the components, so that the parallel charged voltage level is somewhat less than the input voltage Vin, and the voltage levels at the high voltage nodes of the capacitors109-112are not simply multiples of the input voltage Vin. The overall charge pump output voltage level at the output voltage node137is, thus, somewhat less than an exact multiple of the input voltage Vin. Nevertheless, the relatively high breakdown voltage of the NMOS devices produced with the ZqFET™ technology from Silanna Semiconductor enable a relatively large voltage across each of the stages138-141or the capacitors109-112. For example, in some embodiments, the breakdown voltage can be in a range between about 3 V, 12 V, 40 V, or 50 V, so that between about 3V, 12 V, 40 V, or 50 V could potentially be stacked by each of the stages138-141or capacitors109-112to generate a relatively large overall charge pump output voltage level at the output voltage node137.

In some embodiments, operation of the charge pump100is illustrated by timing diagrams201-204shown inFIG. 2. The timing diagrams201-204were generated by a simulation of an example of the charge pump100in which the input voltage Vin was about 5 V, a clock period for the first and second oscillating voltage signals Vp and Vn was about 1 μs (frequency of 1 MHz), a clock duty cycle for the first and second oscillating voltage signals Vp and Vn was about 50%, and the NMOS transistor switches101-108,117-124,125and126were modeled with the ZqFET™ technology from Silanna Semiconductor.

The timing diagrams201-204show the voltage levels at the high voltage nodes of the capacitors109-112, respectively, for several cycles or periods of operation from a startup condition to approaching a steady state condition. Additionally, the input voltage Vin is shown by graph205(steady at about 5 V), and the resulting overall charge pump output voltage level for the output voltage Vout is shown by graph206.

The timing diagrams201-204exhibit about the same low voltage level (about 4 V or slightly higher) during a first portion of each cycle. This low voltage level generally represents the parallel charged voltage level to which each capacitor109-112is charged during the parallel charging time period.

Additionally, the timing diagrams201-204exhibit different high voltage levels during a second portion of each cycle. These high voltage levels generally represent the stacked voltage levels at the high voltage nodes of the capacitors109-112during the series discharging time period. Therefore, the high voltage level of the timing diagram201represents the stacked voltage level at the high voltage node of the capacitor109due to stacking the voltage level across the capacitor109onto the input voltage Vin at the input voltage node136; the high voltage level of the timing diagram202represents the stacked voltage level at the high voltage node of the capacitor110due to stacking the voltage level across the capacitor110onto the stacked voltage level at the high voltage node of the capacitor109; the high voltage level of the timing diagram203represents the stacked voltage level at the high voltage node of the capacitor111due to stacking the voltage level across the capacitor111onto the stacked voltage level at the high voltage node of the capacitor110; and the high voltage level of the timing diagram204represents the stacked voltage level at the high voltage node of the capacitor112due to stacking the voltage level across the capacitor112onto the stacked voltage level at the high voltage node of the capacitor111. The high voltage level of the timing diagram204, thus, also represents the series capacitor output voltage level at the capacitor series output node142.

The high voltage levels of the timing diagrams201-204exhibit a relatively steady state condition after initially rising during each cycle following the startup due to the time required to fully charge the capacitors109-112. Additionally, the resulting overall charge pump output voltage level (graph206) also exhibits a relatively steady state condition after initially rising along with the high voltage levels of the timing diagrams201-204following the startup due to the charging of the output capacitor129at the output voltage node137by the series capacitor output voltage level at the capacitor series output node142.

Due to losses or inefficiencies in the components, the overall charge pump output voltage level (graph206) remains below the high voltage level of the series capacitor output voltage level (timing diagram204). Also, the low voltage level of each timing diagram201-204is about 4 V (or slightly higher), rather than the 5 V of the input voltage Vin (graph205). Additionally, the voltage level amount that each stage138-141contributes to form the overall charge pump output voltage level for the output voltage Vout is about 3.1-3.5 V, rather than the 5 V of the input voltage Vin (graph205). Therefore, in this example, the steady state stacked voltage level at the high voltage node of the initial capacitor109(timing diagram201) is about 8.1 V, the steady state stacked voltage level at the high voltage node of the intermediate capacitor110(timing diagram202) is about 11.2 V, the steady state stacked voltage level at the high voltage node of the next intermediate capacitor111(timing diagram203) is about 14.4 V, the steady state stacked voltage level at the high voltage node of the final capacitor112(timing diagram204) is about 17.9 V, and the overall charge pump output voltage level (graph206) is about 17.2 V; thereby demonstrating the advantageous operation of the improved cascaded, series-parallel charge pump100.

In some embodiments, operation of the charge pump100is further illustrated by timing diagrams301-302shown inFIG. 3after timing diagrams201-204achieve steady state conditions. The timing diagrams301-302show the first and second oscillating voltage signals Vp and Vn, respectively, with about a 50% duty cycle. When the voltage level of the first oscillating voltage signal Vp is high and the voltage level of the second oscillating voltage signal Vn is low, the timing diagrams201-204are at about the same low voltage level (about 4 V or slightly higher), i.e., the parallel charging time period. When the voltage level of the first oscillating voltage signal Vp is low and the voltage level of the second oscillating voltage signal Vn is high, the timing diagrams201-204are at about their steady state stacked voltage level, i.e., the series discharging time period. Additionally, the overall charge pump output voltage level (graph206) is relatively steady.

Reference has been made in detail to embodiments of the disclosed invention, one or more examples of which have been illustrated in the accompanying figures. Each example has been provided by way of explanation of the present technology, not as a limitation of the present technology. In fact, while the specification has been described in detail with respect to specific embodiments of the invention, it will be appreciated that those skilled in the art, upon attaining an understanding of the foregoing, may readily conceive of alterations to, variations of, and equivalents to these embodiments. For instance, features illustrated or described as part of one embodiment may be used with another embodiment to yield a still further embodiment. Thus, it is intended that the present subject matter covers all such modifications and variations within the scope of the appended claims and their equivalents. These and other modifications and variations to the present invention may be practiced by those of ordinary skill in the art, without departing from the scope of the present invention, which is more particularly set forth in the appended claims. Furthermore, those of ordinary skill in the art will appreciate that the foregoing description is by way of example only, and is not intended to limit the invention.