Graphics processing unit with shared arithmetic logic unit

This disclosure describes a graphics processing unit (GPU) pipeline that uses one or more shared arithmetic logic units (ALUs). In order to facilitate such sharing of ALUs, the stages of the disclosed GPU pipeline may be rearranged relative to conventional GPU pipelines. In addition, by rearranging the stages of the GPU pipeline, efficiencies may be achieved in the image processing. Unlike conventional GPU pipelines, for example, an attribute gradient setup stage can be located much later in the pipeline, and the attribute interpolator stage may immediately follow the attribute gradient setup stage. This allows sharing of an ALU by the attribute gradient setup and attribute interpolator stages. Several other techniques and features for the GPU pipeline are also described, which may improve performance and possibly achieve additional processing efficiencies.

TECHNICAL FIELD

This disclosure relates to graphics processing units and, more particularly, graphics processing units that have a multi-stage pipelined configuration for processing images.

BACKGROUND

A graphics processing unit (GPU) is a dedicated graphics rendering device utilized to manipulate and display computerized graphics on a display. GPUs are built with a highly parallel structure that provides more efficient processing than typical, general purpose central processing units (CPUs) for a range of complex graphics-related algorithms. For example, the complex algorithms may correspond to representations of three-dimensional computerized graphics. A GPU may implement a number of so-called “primitive” graphics operations, such as forming points, lines, and triangles, to create complex, three-dimensional images on a display more quickly than drawing the images directly to the display with a CPU.

Vertex shading and pixel shading are often utilized in the video gaming industry to determine final surface properties of a computerized image, such as light absorption and diffusion, texture mapping, light reflection and refraction, shadowing, surface displacement, and post-processing effects. GPUs typically include a number of pipeline stages such as one or more shader stages, setup stages, rasterizer stages and interpolation stages.

A vertex shader, for example, is typically applied to image data, such as the geometry for an image, and the vertex shader generates vertex coordinates and attributes of vertices within the image data. Vertex attributes may include color, normal, and texture coordinates associated with a vertex. One or more primitive setup and rejection modules may form primitive shapes such as points, lines, or triangles, and may reject hidden or invisible primitive shapes based on the vertices within the image data. An attribute setup module computes gradients of attributes within the primitive shapes for the image data. Once the attribute gradient values are computed, primitive shapes for the image data may be converted into pixels, and pixel rejection may be performed with respect to hidden primitive shapes.

An attribute interpolator then interpolates the attributes over pixels within the primitive shapes for the image data based on the attribute gradient values, and sends the interpolated attribute values to the fragment shader for pixel rendering. Results of the fragment shader are output to a post-processing block and a frame buffer for presentation of the processed image on the display. This process is performed along successive stages of the GPU pipeline.

SUMMARY

In general, this disclosure describes a graphics processing unit (GPU) pipeline that uses one or more shared arithmetic logic units (ALUs). In order to facilitate such sharing of ALUs, the stages of the disclosed GPU pipeline may be rearranged relative to conventional GPU pipelines. In addition, by rearranging the stages of the GPU pipeline, efficiencies may be achieved in the image processing. Several other techniques and features for the GPU pipeline are also described, which may improve performance and possibly achieve additional processing efficiencies. For example, an extended vertex cache is also described for the GPU pipeline, which can significantly reduce the amount of data needed to be transferred through the successive stages of the GPU pipeline.

In one embodiment, the disclosure provides a method comprising receiving image data for an image within a GPU pipeline, and processing the image data within the GPU pipeline using a shared arithmetic logic unit for an attribute gradient setup stage and an attribute interpolator stage.

In another embodiment, this disclosure provides a device comprising a GPU pipeline that receives image data for an image and processes the image data within multiple stages, wherein the multiple stages include an attribute gradient setup stage and an attribute interpolator stage, and a shared arithmetic logic unit that performs attribute gradient setups and attribute interpolations associated with both the attribute gradient setup stage and the attribute interpolator stage.

In another embodiment, this disclosure provides a device comprising means for receiving image data for an image, means for processing the image data in an attribute gradient setup stage using a shared arithmetic logic unit, and means for processing the image data in an attribute interpolator stage using the shared arithmetic logic unit.

The techniques described herein may be implemented in hardware, software, firmware, or any combination thereof. If implemented in software, the techniques may be realized in whole or in part by a computer readable medium comprising instructions that, when executed by a machine, such as a processor, perform one or more of the methods described herein.

Accordingly, this disclosure also contemplates a computer-readable medium comprising instructions that upon execution cause a machine to receive image data for an image within a GPU pipeline, and process the image data within the GPU pipeline using a shared arithmetic logic unit for an attribute gradient setup stage and an attribute interpolator stage.

DETAILED DESCRIPTION

FIG. 1is a block diagram illustrating an exemplary device10including a graphics processing unit (GPU)14that includes a GPU pipeline18for processing computerized images. According to this disclosure, GPU pipeline18utilizes one or more shared arithmetic logic units (ALUs)15to reduce complexity of GPU14and create efficiency in the image processing. In addition, GPU pipeline may implement an extended vertex cache16in order to reduce the amount of data propagated through GPU pipeline18. As discussed in greater detail below, the stages of GPU pipeline18may be rearranged relative to conventional GPU pipelines, which may improve the process of image processing and facilitate the use of shared ALUs15. Some stages, however, may still use dedicated (unshared) ALUs like those used in stages of conventional GPU pipelines.

In the example ofFIG. 1, device10includes a controller12, GPU14and a display20. Device10may also include many other components (not shown). For example, device10may comprise a wireless communication device and display20may comprise a display within the wireless communication device. As another example, device10may comprise a desktop or notebook computer, and display20may comprise a dedicated monitor or display of the computer. Device10may also comprise a wired communication device or a device not principally directed to communication. As other examples, device10may comprise a personal digital assistant (PDA), handheld video game device, game console or television device that includes display20. In various embodiments, computerized video imagery may be obtained from a remote device or from a local device, such as a video server that generates video or video objects, or a video archive that retrieves stored video or video objects.

Controller12controls operation of GPU14. Controller12may be a specific controller for GPU14or a more general controller that controls the overall operation of device10. In accordance with the techniques described herein, GPU14includes a GPU pipeline18that implements and accesses shared ALUs15. In addition, GPU14may include an extended vertex cache16coupled to GPU pipeline18. Again, shared ALUs may create efficiency in the image processing and the incorporation of extended vertex cache16may reduce an amount of data passing through GPU pipeline18within GPU14. GPU pipeline18may be arranged in a non-conventional manner in order to facilitate the use of shared ALUs15and extended vertex cache16

GPU14receives image data, such as geometrical data and rendering commands for an image from controller12within device10. The image data may correspond to representations of complex, two-dimensional or three-dimensional computerized graphics. GPU14processes the image data to present image effects, background images, or video gaming images, for example, to a user of device10via a display20. The images may be formed as video frames in a sequence of video frames. Display20may comprise a liquid crystal display (LCD), a cathode ray tube (CRT) display, a plasma display, or another type of display integrated with or coupled to device10.

In some cases, controller12may receive the image data from applications operating within device10. For example, device10may comprise a computing device operating a video gaming application based on image data received from an internal hard drive or a removable data storage device. In other cases, controller12may receive the image data from applications operating external to device10. For example, device10may comprise a computing device operating a video gaming application based on image data received from an external server via a wired or wireless network, such as the Internet. The image data may be received via streaming media or broadcast media, which may be wired, wireless or a combination of both.

When a user of device10triggers an image effect, selects a background image, or initiates a video game, controller12receives the corresponding image data from an application and sends the image data to GPU14for image processing. GPU14processes the image data to prepare the corresponding image for presentation on display20. For example, GPU14may implement a number of primitive graphics operations, such as forming points, lines, and triangles, to create a three-dimensional image represented by the received image data on display20.

According to the techniques described herein, GPU pipeline18receives the image data for the image and stores attributes for vertices within the image data in extended vertex cache16. GPU pipeline18only passes vertex coordinates that identify the vertices, and vertex cache index values that indicate storage locations of the attributes for each of the vertices in extended vertex cache16to other processing stages along GPU pipeline18. In some embodiments, GPU pipeline18temporarily stores the vertex coordinates in extended vertex cache16. In this manner, GPU pipeline18is not clogged with the transfer of the vertex attributes between stages, and can support increased throughput, and storage buffers between stages may also be eliminated or possibly reduced in size. The vertex coordinates identify the vertices within the image data based on, for example, a four-dimensional coordinate system with X, Y, and Z (width, height, and depth) coordinates that identify a location of a vertex within the image data, and a W coordinate that comprises a perspective parameter for the image data. The vertex attributes, for example, may include color, normal, and texture coordinates associated with a vertex.

Furthermore, in accordance with this disclosure, during the processing of image data in GPU pipeline18, one or more shared ALUs15are used for different stages. As one example, a shared ALU may be used for both a triangle setup stage and a Z-Gradient setup stage. A shared lookup table for reciprocal operation may also be used in these triangle setup and Z-Gradient setup stages. As another example, a shared ALU may be used for both attribute gradient setup stage and an attribute interpolator stage. Unlike conventional GPU pipelines, the attribute gradient setup stage can be located much later in the pipeline, and the attribute interpolator stage may immediately follow the attribute gradient setup stage. This allows sharing of an ALU, and may have added benefits in that attribute gradient setups can be avoided for hidden primitives that are rejected. Conventional GPU pipelines, in contrast, typically perform attribute gradient setup prior to hidden primitive rejection, which creates inefficiency that can be avoided by the techniques of this disclosure.

GPU pipeline18within GPU14includes several stages, including a vertex shader stage, several primitive setup stages, such as triangle setup and Z-Gradient setup, a rasterizer stage, a primitive rejection sages, an attribute gradient setup stage, an attribute interpolation stage, and a fragment shader stage. More or fewer stages may be included in other embodiments. Various ones of the different stages of GPU pipelines may also be referred to as “modules” of the pipeline in this disclosure.

In any case, the various primitive setup stages and primitive rejection stages only utilize vertex coordinates to form primitives and may discard a subset of the primitives that are unnecessary for the image. Primitives are the simplest types of geometric figures, including points, lines, triangles, and other polygons, and may be formed with one or more vertices within the image data. Primitives or portions of primitives may be rejected from consideration during processing of a specific frame of the image when the primitives or the portions of primitives are invisible (e.g., located on a backside of an object) within the image frame, or are hidden (e.g., located behind another object or transparent) within the image frame. This is the purpose of a hidden primitive and pixel rejection stages.

Attribute gradient setup and attribute interpolation stages may utilize the vertex attributes to compute attribute gradient values and interpolate the attributes based on the attribute gradient values. Techniques described in this disclosure defer the computationally intensive setup of attribute gradients to just before attribute interpolation in GPU pipeline18. This allows a shared ALU to be used by both the attribute gradient setup and attribute interpolation stages. The vertex attributes may be retrieved from extended vertex cache16for attribute gradient setup as one of the last steps before attribute interpolation in GPU pipeline18. In this way, the vertex attributes are not introduced to GPU pipeline18until after primitive setup and primitive rejection, which creates efficiencies insofar as attribute gradient setup can be avoided for rejected primitives.

Moreover, by storing the attributes for vertices within the image data in extended vertex cache16, GPU pipeline18can be made more efficient. In particular, the extended vertex cache16can eliminate the need to pass large amounts of attribute data through GPU pipeline18, and may substantially eliminate bottlenecks in GPU pipeline18for primitives that include large numbers of attributes. In addition, deferring the attribute gradient setup to just before attribute interpolation in GPU pipeline18may improve image processing speed within GPU pipeline18. More specifically, deferring the attribute gradient setup within GPU pipeline18until after rejection of the subset of the primitives that are unnecessary for the image may substantially reduce computations and power consumption as the attribute gradient setup will only be performed on a subset of the primitives that are necessary for the image.

Display20may be coupled to device10either wirelessly or with a wired connection. For example, device10may comprise a server or other computing device of a wireless communication service provider, and display20may be included within a wireless communication device. In this case, as examples, display20may comprise a display within a mobile radiotelephone, a satellite radiotelephone, a portable computer with a wireless communication card, a personal digital assistant (PDA) equipped with wireless communication capabilities, or any of a variety of devices capable of wireless communication. As another example, device10may comprise a server or other computing device connected to display20via a wired network, and display20may be included within a wired communication device or a device not principally directed to communication. In other embodiments, display20may be integrated within device10.

FIG. 2is a block diagram illustrating a conventional GPU pipeline22. GPU pipeline22ofFIG. 2includes, in the following order, a command engine24, a vertex shader26, a triangle setup module28, a Z-Gradient setup module29, an attribute gradient setup module30, a rasterizer31, a hidden primitive and pixel rejection module32, an attribute interpolator34, a fragment shader36, and a post processor38. Each of the vertex shader26, triangle setup module28, Z-Gradient setup module29, attribute gradient setup module30, rasterizer31, hidden primitive and pixel rejection module32, attribute interpolator34, and fragment shader36includes a dedicated arithmetic logic unit (ALU), which are labeled as elements25A-25H respectively.

Command engine24receives an image data for an image from a controller of the device in which conventional GPU pipeline22resides. The image data may correspond to representations of complex, two-dimensional or three-dimensional computerized graphics. Command engine24passes the image data along GPU pipeline22to the other processing stages. In particular, all of the attributes and coordinates of the image data are passed from stage to stage along GPU pipeline22. Each respective stage uses its respective ALU, and if any bottlenecks occur, the image processing may be stalled at that respective stage.

FIG. 3is a block diagram illustrating a GPU14A, an exemplary embodiment of GPU14fromFIG. 1, including a GPU pipeline18A. A set of ALUs45A,55A,45B,45C,55B and45D, and an extended vertex cache16A are coupled to GPU pipeline18A. Extended vertex cache16A within GPU14A may reduce an amount of data passing through GPU pipeline18A within GPU14A. Moreover, ALUs55A and55B are shared ALUs, each of which are used by two different successive stages in the GPU pipeline18A. Notably, the stages of GPU pipeline18A are rearranged relative to conventional GPU pipeline22ofFIG. 2, which may facilitate the sharing of ALU55B by attribute gradient setup module52and attribute interpolator54. Moreover, because attribute gradient setup module52is executed after hidden primitive and pixel rejection module50, efficiencies are gained. Namely, attribute gradient setup may be avoided for any hidden or rejected primitives.

In the illustrated embodiment ofFIG. 3, GPU pipeline18A includes a command engine42, a vertex shader44, a triangle and Z-Gradient setup modules46and47, a rasterizer48, a hidden primitive and pixel rejection module50, an attribute gradient setup module52, an attribute interpolator54, a fragment shader56, and a post processor58. Again, the order of these stages is non-conventional insofar as attribute gradient setup module52follows hidden primitive and pixel rejection module50. Attribute interpolator54immediately follows attribute gradient setup module52. Triangle and Z-Gradient setup modules46and47may be collectively referred to as primitive setup modules, and some cases, other types of primitive setups may also be used.

Command engine42receives image data, which may include rendering commands, for an image from controller12of device10. The image data may correspond to representations of complex, two-dimensional or three-dimensional computerized graphics. Command engine42passes a subset of this data, i.e., information for vertices within the image data that are not included in extended vertex cache16A (“missed vertices”) to vertex shader44. Command engine42will pass vertex cache index information for missed vertices to primitive setup and rejection module46. Command engine42passes vertex cache index information for vertices within the image data that are already included in extended vertex cache16A (“hit vertices”) directly to primitive setup and rejection module46. Vertex data for hit vertices are not typically sent to vertex shader44. Initial processing of hit and missed vertices within the image data is described in more detail below.

GPU pipeline18A includes several stages, although the techniques of this disclosure may operate in pipelines with more or fewer stages than those illustrated. Vertex shader44is applied to the missed vertices within the image data and determines surface properties of the image at the missed vertices within an image data. In this way, vertex shader44generates vertex coordinates and attributes of each of the missed vertices within the image data. Vertex shader44then stores the attributes for the missed vertices in extended vertex cache16A. In this manner, the attributes need not be passed along the GPU pipeline18A, but can be accessed from extended vertex cache16A, as needed, by respective stages of the GPU pipeline18A. Vertex shader44is not applied to each of the hit vertices within the image data as vertex coordinates and attributes of each of the hit vertices may have been previously generated and stored in extended vertex cache16A.

The vertex coordinates identify the vertices within the image data (such as geometry within the image) based on, for example, a four-dimensional coordinate system with X, Y, and Z (width, height, and depth) coordinates that identify a location of a vertex within the image data, and a W coordinate that comprises a perspective parameter for the image data. The vertex attributes, for example, may include color, normal, and texture coordinates associated with a vertex. Extended vertex cache16A may be easily configured for different numbers of attributes and primitive types. Vertex cache index values that indicate storage locations within extended vertex cache16A of the vertex coordinates and attributes for both the hit and missed vertices in the image data are then placed in a buffer (not shown) positioned between command engine42and primitive setup and rejection module46.

Triangle setup46and Z-Gradient setup47are exemplary primitive setup stages, although additional primitive setup stages may also be included. A shared ALU55A is used by both triangle setup46and Z-Gradient setup47. The different stages use either vertex coordinates or vertex attributes to process a respective image. For example, triangle setup46, Z-Gradient setup47, rasterizer48, and hidden primitive and pixel rejection module50only utilize the vertex coordinates. However, attribute gradient setup module52and attribute interpolator54utilize the vertex attributes. Therefore, according to this disclosure, attribute gradient setup module52is deferred to just before attribute interpolator54in GPU pipeline18A. The vertex attributes may be retrieved from extended vertex cache16A for attribute gradient setup module52as one of the last steps in GPU pipeline18A before interpolating the attributes with attribute interpolator54. In this way, the vertex attributes are not introduced to GPU pipeline18A until after hidden primitive and pixel rejection module50, and just before attribute interpolator54, providing significant gains in efficiency.

Moreover, because attribute interpolator54immediately follows attribute gradient setup module52, these respective stages may share ALU55B. For large sized primitives, ALU55B will be utilized most for interpolation. Alternatively, when primitives are small, ALU55B will be used mostly for attribute setup. A relatively large ALU55B can promote processing speed particularly for gradient setup, although a relatively small ALU55B can reduce power consumption at a cost of performance speed in the gradient setup.

Again, by storing the vertex attributes for the vertices of image data in extended vertex cache16A, device10can eliminate a large amount of data from passing through GPU pipeline18A, which reduces the width of the internal data bus included in GPU pipeline18A. By reducing the amount of data movement, these techniques can also reduce power consumption within GPU18A. In addition, with the exception of a buffer that may be positioned between command engine42and primitive setup and rejection module46, buffers positioned between each of the processing stages may be removed from GPU pipeline18A to reduce the area of GPU14A within device10.

Primitive setup modules46and47(and possibly other types of primitive setups) receive the vertex cache index values for the attributes of each of the vertices in the image data. Primitive setup modules46and47then retrieve vertex coordinates for each of the vertices within the image data using the vertex cache index values. Primitive setup modules46and47form the respective primitives with one or more vertices within the image data. Primitives are the simplest types of geometric figures and may include points, lines, triangles, and other polygons. According to this disclosure, the triangle setup28and Z-Gradient setup29can share ALU55A in order to promote efficiency. The triangle setup28and Z-Gradient setup29may also share a lookup table for reciprocal operation for additional efficiency. A Z-Gradient refers to a difference of two Z coordinates of two neighbor pixels over a triangle in either X direction or Y direction. Z-Gradient setup is used to compute the difference of two Z values by using three original vertices' Z values of the triangle and XY coordinates.

In some cases, primitive setup modules46and47may also reject some primitives by performing scissoring and backface culling using the XY coordinates of the vertices within the image data. Scissoring and backface culling rejects primitives and portions of primitives from consideration during processing of a specific frame of the image when the primitives and the portions of primitives are invisible within the image frame. For example, the primitives and the portions of primitives may be located on a backside of an object within the image frame. Primitive setup modules46and47may request extended vertex cache16A to release storage space for the attributes associated with the rejected primitives. By only moving the primitives for the image data, the vertex coordinates associated with the primitives, and the vertex cache index values for each of the vertices within the primitives through GPU pipeline18A, device10may substantially eliminate bottlenecks in GPU pipeline18A for primitives that include large numbers of attributes.

Rasterizer48converts the primitives for the image data into pixels based on the XY coordinates of vertices within the primitives and the number of pixels included in the primitives. Hidden primitive and pixel rejection module50rejects additional hidden primitives and hidden pixels within the primitives using the early depth and stencil test based on the Z coordinates of the vertices within the primitives. If hidden primitive and pixel rejection module50rejects all pixels within a primitive, the primitive is automatically rejected. Primitives or pixels within primitives may be considered hidden, and be rejected from consideration during processing of a specific frame of the image, when the primitives or the pixels within primitives are located behind another object within the image frame or are transparent within the image frame. Hidden primitive and pixel rejection module50may request extended vertex cache16A to release storage space for the attributes associated with the rejected primitives.

Typically, a large percentage of primitives are rejected by scissoring and backface culling performed by primitive setup and rejection modules46,47, and the early depth and stencil test performed by hidden primitive and pixel rejection module50. Therefore, by deferring the attribute gradient setup stage52until after hidden primitive and pixel rejection50, computations can be eliminated for attributes associated with a subset of the primitives that are rejected as being hidden and unnecessary for the image.

Attribute gradient setup module52retrieves the vertex attributes from extended vertex cache16A using the vertex cache index values for each of the vertices within the primitives. Attribute gradient setup module52computes gradients of attributes associated with the primitives for the image data. An attribute gradient comprises a difference between the attribute value at a first pixel and the attribute value at a second pixel within a primitive moving in either a horizontal (X) direction or a vertical (Y) direction. After attribute gradient setup module52computes gradients of attributes of all vertices within a primitive for the image data, attribute gradient setup module52may request extended vertex cache16A to release storage space for the attributes of the vertices within the primitive.

Once the attribute gradient values are computed, attribute interpolator54interpolates the attributes over pixels within the primitives based on the attribute gradient values. Again, the same ALU55B is used in the attribute gradient setup stage52and the attribute interpolator stage54. The interpolated attribute values are input to fragment shader56to perform pixel rendering of the primitives. Fragment shader56determines surface properties of the image at pixels within the primitives for the image data. Results of fragment shader56are then output to post-processor58for presentation of the processed image on display20.

In some cases, vertex shader44may not be applied to missed vertices within the image data. It may be assumed that vertex coordinates and attributes of all vertices within the image data are determined external to GPU pipeline18A. Therefore, primitives formed with the missed vertices do not need vertex shader44to calculate attributes of the missed vertices. In this case, extended vertex cache16A may operate as an extended vertex buffer. Command engine42may assign vertex index values that identify storage location for the attributes within the extended vertex buffer and send the predetermined vertex coordinates and attributes of each of the vertices within the image data to the extended vertex buffer.

FIG. 4is a block diagram illustrating GPU14B, another exemplary embodiment of GPU14fromFIG. 1, including a GPU pipeline18B and an extended vertex cache16B coupled to GPU pipeline18B. In the illustrated embodiment, GPU pipeline18B includes a command engine62, a vertex shader64, a triangle set up module66, and Z-Gradient setup module67(modules66and67are collectively referred to as primitive setup modules), a rasterizer68, a hidden primitive and pixel rejection module70, an attribute gradient setup module72, an attribute interpolator74, a fragment shader76, and a post-processor78. GPU14B illustrated inFIG. 4may operate substantially similar to GPU14A illustrated inFIG. 3, except for the initial processing of vertices in the image data. The different stages utilize ALUs65A,75A,65B,65C,75B and65D respectively. Notably, ALUs75A and75B are shared for two different stages of GPU pipeline18B.

Command engine62receives image data, including geometry and rendering commands, for an image from controller12of device10. Command engine62passes the image data along GPU pipeline18B to the other processing stages. In other words, command engine62passes information for all the vertices within the image data to vertex shader64.

In the embodiment ofFIG. 4, vertex shader64is applied to all vertices within the image data. Vertex shader64is applied to the image data and determines surface properties of the image at the vertices within the image data. In this way, vertex shader64generates vertex coordinates and attributes of each of the vertices within the image data. Vertex shader64then stores only the attributes in extended vertex cache16B. Vertex shader64passes the vertex coordinates and vertex cache index values that indicate storage locations of the attributes within extended vertex cache16B for each of the vertices in the image data along GPU pipeline18B.

Since vertex shader64passes the vertex coordinates and vertex cache index values for the vertices in the image data directly to primitive setup and rejection module66, all the buffers positioned between each of the processing stages may be removed from GPU pipeline18B. Primitive setup modules66and67forms primitives with one or more vertices within the image data. These primitive setup modules66and67may share one or more ALUs. Primitive setup and rejection module66may request extended vertex cache16B to release storage space for the attributes associated with the rejected primitives.

Rasterizer68converts the primitives for the image data into pixels based on the XY coordinates of vertices within the primitives and the number of pixels included in the primitives. Hidden primitive and pixel rejection module70rejects hidden primitives and hidden pixels within the primitives using the early depth and stencil test based on the Z coordinates of the vertices within the primitives. Hidden primitive and pixel rejection module70may request extended vertex cache16B to release storage space for the attributes associated with the rejected primitives.

Attribute gradient setup module72retrieves the vertex attributes from extended vertex cache16B using the vertex cache index values for each of the vertices within the primitives. Attribute gradient setup module72computes gradients of attributes associated with the primitives for the image data. After attribute gradient setup module72computes gradients of attributes of all vertices within a primitive for the image data, attribute gradient setup module72may request extended vertex cache16B to release storage space for the attributes of the vertices within the primitive.

Once the attribute gradient values are computed, attribute interpolator74interpolates the attributes over pixels within the primitives based on the attribute gradient values by sharing one or more ALUs with the attribute gradient setup module72. The interpolated attribute values are then input to fragment shader76to perform pixel rendering of the primitives. Fragment shader76determines surface properties of the image at pixels within the primitives for the image data. Results of fragment shader76will be output to post-processor78for presentation of the processed image on display20.

FIG. 5is a flowchart illustrating an exemplary operation of processing an image within a GPU using an extended vertex cache. The operations ofFIG. 5will be described with reference to GPU14fromFIG. 1although similar techniques could be used with other GPUs. Extended vertex cache16may be created within GPU14during manufacture of device10and coupled to GPU pipeline18(80). Extended vertex cache16may be easily configured for different numbers of attributes and primitive types.

GPU14receives image data, which may include rendering commands and geometry, for an image from controller12of device10(82). The image data may correspond to representations of complex, two-dimensional or three-dimensional computerized graphics. GPU14sends the image data to GPU pipeline18to process the image for display on display20connected to device10. GPU pipeline18stores attributes for vertices within the image data in extended vertex cache16(84). In some embodiments, GPU pipeline18temporarily stores vertex coordinates for the vertices within the image data in extended vertex cache16.

GPU pipeline18then sends vertex coordinates that identify the vertices, and vertex cache index values that indicate storage locations of the attributes for each of the vertices in extended vertex cache16to other processing stages along GPU pipeline18(86). GPU pipeline18processes the image based on the vertex coordinates and the vertex cache index values for each of the vertices in the image data (88). During such processing, GPU pipeline18reuses one or more ALUs18along the GPU pipeline18(89). Specifically, according to this disclosure, a shared ALU can be used for an attribute gradient setup stage and an attribute interpolation stage. The non-conventional ordering of the GPU pipeline may facilitate the ability for the attribute gradient setup stage and the attribute interpolation stage to share an ALU.

FIG. 6is a flowchart illustrating another exemplary operation of processing an image with a GPU pipeline using shared ALUs. For purposes of explanation, the operation shown inFIG. 6will be described with reference to GPU14A fromFIG. 3although similar techniques could be used with other GPUs. Command engine42receives image data, including geometry and rendering commands, for an image and passes the image data along GPU pipeline18B. As shown inFIG. 6, vertex shader44performs vertex shading using a first ALU45A (91). Triangle setup module46performs triangle setup for any triangle primitives using a second ALU55A (92). This second ALU55A is reused by another stage insofar as Z-Gradient setup module47performs Z-Gradient setup using second ALU55A (93). Rasterizer then performs rasterizing using a third ALU45B (94).

Hidden primitive and pixel rejection module50performs an early depth/stencil test using a forth ALU45C in order to remove primitives that will not be viewable in the final image (95). Such non-viewable primitives, for example, may be covered by other objects or shapes and can be removed from the image without sacrificing any image quality. Attribute gradient setup module uses a fifth ALU55B for attribute gradient setup (96), which notably, does not occur with respect to rejected primitives. Attribute interpolator54then uses the fifth ALU55B (97), which was also used for attribute gradient setup, in order to perform any interpolations. Fragment shader56performs fragment shading (98), and post processor58performs any final post processing prior to image display (99). As noted above, an extended vertex cache16A may be implemented along GPU pipeline18A in order to reduce complexity and eliminate the need to propagate large amounts of data through the respective stages. Instead, each respective stage that needs portions of the image data can access such data stored in extended vertex cache16A.

A number of embodiments have been described. However, various modifications to these embodiments are possible, and the principles presented herein may be applied to other embodiments as well. The techniques and methods described herein may be implemented in hardware, software, and/or firmware. The various tasks of such methods may be implemented as sets of instructions executable by one or more arrays of logic elements, microprocessors, embedded controllers, or integrated processor cores. In one example, one or more such tasks are arranged for execution within a chipset that is configured to control operations of various devices of a personal communications device, such as a so-called cellular telephone.

In various examples, the techniques described in this disclosure may be implemented within a general purpose microprocessor, digital signal processor (DSP), application specific integrated circuit (ASIC), field programmable gate array (FPGA), or other equivalent logic devices. If implemented in software, the techniques may be embodied as instructions on a computer-readable medium such as random access memory (RAM), read-only memory (ROM), non-volatile random access memory (NVRAM), electrically erasable programmable read-only memory (EEPROM), FLASH memory, or the like. The instructions cause a machine, such as a programmable processor, to perform the techniques described in this disclosure.

As further examples, an embodiment may be implemented in part or in whole in a hard-wired circuit, in a circuit configuration fabricated into an application-specific integrated circuit, or as a firmware program loaded into non-volatile storage or a software program loaded from or into a data storage medium as machine-readable code, such code being instructions executable by an array of logic elements such as a microprocessor or other digital signal processing unit. The data storage medium may be an array of storage elements such as semiconductor memory (which may include without limitation dynamic or static RAM, ROM, and/or flash RAM) or ferroelectric, ovonic, polymeric, or phase-change memory, or a disk medium such as a magnetic or optical disk.

In this disclosure, various techniques have been described for processing images with a GPU using an extended vertex cache and one or more shared ALUs. The techniques may substantially eliminate bottlenecks in the GPU pipeline for primitives that include large numbers of attributes, and can promote efficient processing that substantially reduces idle time of ALUs. In addition, the techniques improve image processing speed within the GPU pipeline by deferring the attribute gradient setup to just before attribute interpolation in the GPU pipeline. More specifically, deferring the attribute gradient setup within the GPU pipeline until after rejection of a subset of the primitives that are unnecessary for the image may substantially reduce computations and power consumption as the attribute gradient setup will only be performed on a subset of the primitives that are necessary for the image. This arrangement of the stages also facilitates ALU sharing by the attribute gradient setup and attribute interpolation stages. These and other embodiments are within the scope of the following claims.