Densely spaced fins for semiconductor fin field effect transistors

A method of forming a fin-based field-effect transistor device includes forming one or more first fins comprising silicon on a substrate, forming epitaxial layers on sides of the one or more first fins, and removing the one or more first fins to form a plurality of second fins.

BACKGROUND

The present invention relates to fin field-effect transistors (finFETs), and more specifically, to densely spaced fins for semiconductor finFETs.

Field-effect transistors (FETs) generate an electric field, by a gate structure, to control the conductivity of a channel between source and drain structures in a semiconductor substrate. The source and drain structures may be formed by doping the semiconductor substrate, a channel region may extend between the source and the drain on the semiconductor substrate and the gate may be formed on the semiconductor substrate between the source and drain regions.

The size of FETs has been reduced through the use of fin-based FETs (finFETs), in which the channels of the FET are fin-shaped. Fins of a finFET use a vertical channel structure to increase the surface area of the channel exposed to the gate. As a result, the gate has a greater influence on the channel, because the gate is formed to cover multiple sides of the channel.

The continued miniaturization of electronics has required finFETs to be made continually smaller. However, the size of the fins and the spaces, or pitch, between fins is limited by the lithographic or other etching techniques used to form the fins. One technique currently used to form fins of finFET semiconductor devices is sidewall image transfer (SIT). In SIT, a sidewall spacer is formed on a sacrificial structure, such as a mandrel, which is defined in the present specification as a narrow band of material. The sacrificial material is removed, and the sidewall spacers are then used to etch fins in a silicon-based substrate. In conventional SIT processes, the width of the mandrels and the spaces between the mandrels define the pitch of the fins of the semiconductor device.

SUMMARY

According to one embodiment of the present invention, a method for forming a fin-based field-effect transistor (finFET) device includes forming one or more first fins comprising silicon on a substrate, forming epitaxial layers on sides of the one or more first fins, and removing the one or more first fins to form a plurality of second fins.

According to another embodiment of the present invention, a semiconductor device includes a silicon substrate, a plurality of epitaxially-grown fins extending from the silicon substrate, and a gate structure covering a portion of one or more of the epitaxially-grown fins to separate the fin into source/drain portions.

DETAILED DESCRIPTION

Fin-based field-effect transistors (finFET) devices are typically formed using etching processes, such as by photolithography, to form fins, and gates are formed on the fins. However, the distances between the fins are limited according to the etching processes used.

FIG. 1illustrates a cross-section of an intermediate fin field-effect transistor (finFET) device100aaccording to an embodiment of the invention. In the present specification and claims, an “intermediate” finFET device is defined as a finFET device in a stage of fabrication prior to a final stage. The finFET device100aincludes a silicon (Si) substrate101, a mandrel layer102, such as a silicon germanium (SiGe) layer102, formed on the Si substrate101, and a first hard mask layer103formed on the SiGe layer102. In one embodiment, the first hard mask layer103is made of silicon nitride (SiN). A second hard mask layer104is formed on the first hard mask layer103. In one embodiment, the second hard mask layer104is silicon dioxide (SiO2).

A mandrel layer105is formed on the second hard mask layer104. The mandrel layer105may be a silicon-based layer. A third hard mask layer106is formed on the mandrel layer105. The third hard mask layer106may be made of SiN. A sacrificial layer107is formed on the third hard mask layer106. The sacrificial layer107may be an organic planarization layer (OPL). In one embodiment, and anti-reflective coating108is formed on the sacrificial layer107. The anti-reflective coating108may be a silicon anti-reflective coating (SiARC). A patterned photoresist layer109is formed on the anti-reflective coating108. The pattern of the photoresist layer109may correspond to narrow bands, or mandrels, such that an etching process using the photoresist layer109results in mandrels being formed.

Embodiments of the invention encompass various materials and thicknesses of layers of the intermediate finFET device100a. For example, in one embodiment, the third hard mask layer106has a thickness of around 180 Angstroms (Å), the mandrel layer105has a thickness of around 1000 Å, the second hard mask layer104has a thickness of around 300 A, and the first hard mask layer103has a thickness of around 400 Å.

InFIG. 2, an intermediate fin field-effect transistor (finFET) device100bis shown having after an etch process by which the pattern of the patterned photoresist layer is transferred through the anti-reflective coating108and the sacrificial layer107so as to form mandrels110, each including a base portion110aformed of the mandrel layer105and a cap portion110bformed of the third hard mask layer106. In one embodiment, the coating108and sacrificial layer107are removed through a reactive ion etching (RIE) process, such as in a N2H2ambient atmosphere.

InFIG. 3, an intermediate fin field-effect transistor (finFET) device100cis shown on which the cap portions110bhave been removed to leave the base portion110aof the mandrels intact and free-standing. In one embodiment, the cap portions110bare removed by a wet etch process, such as using hot phosphorus.

InFIG. 4, an intermediate fin field-effect transistor (finFET) device100dis shown having a spacer layer111formed on the base portion110aof the mandrels and the second hard mask layer104. The spacer layer111is formed on the top and sides of the base portion110aof the mandrels. In one embodiment, the spacer layer111is formed of SiN. The spacer layer111may be formed by any process, including any deposition process to deposit the SiN on exposed surfaces of the base portion110aof the mandrels and the second hard mask layer104. Since the pitch between the mandrels is small (between 40-60 nm), the SiN spacer (spacer layer111) needs to be deposited with good gap fill and conformity by molecular layer deposition (MLD).

InFIG. 6, an intermediate fin field-effect transistor (finFET) device100fis shown on which an etching process has been performed to transfer the pattern of the spacers112ofFIG. 5into the layers below. In particular, the etching forms narrow bands, which may be referred to as fins112, or secondary mandrels112. The fins112include a base portion112amade of the SiGe layer102, and a cap112bmade of the first hard mask layer103.

InFIG. 7, an intermediate fin field-effect transistor (finFET) device100gis shown having spaces around the fins112filled by an oxide layer113. The filling may occur by any deposition process. In addition, a chemical-mechanical planarization (CMP) or polishing process may be performed to flatten out an upper surface of the oxide layer113and fins112.

InFIG. 8, an intermediate fin field-effect transistor (finFET) device100his shown having a sacrificial layer114formed on the oxide layer113, an anti-reflective coating layer115formed on the sacrificial layer114, and a photoresist layer116formed on the anti-reflective coating layer115. The sacrificial layer114may be an organic planarization layer (OPL). In one embodiment, the anti-reflective coating115is a silicon anti-reflective coating (SiARC). The photoresist layer116may have an opening117to define a device region. While one opening is illustrated inFIG. 8, it is understood that embodiments encompass openings of any desired shape to define semiconductor fin-based devices of any desired shapes.

InFIG. 9, an intermediate fin field-effect transistor (finFET) device100iis shown having in which an etch process has been performed to etch the sacrificial layer114and oxide layer113. In addition, the anti-reflective coating115and the photoresist layer116have been removed to expose the device region118. The fins112or secondary mandrels112are exposed in the device region118and are buried in the oxide layer113in the non-device regions. In one embodiment, the depth of the etch in the oxide layer113is controlled using a timed etch, instead of using an end-pointed RIE process.

InFIG. 10, an intermediate fin field-effect transistor (finFET) device100jis shown having the sacrificial layer114removed, such as by mechanical or chemical planarization or polishing or etching.

InFIG. 11, an intermediate fin field-effect transistor (finFET) device100kis shown in which layers of silicon119are epitaxially grown onto sides of the exposed fins112in the device region118. In one embodiment, the bases112aof the fins are made of SiGe and the epitaxial layers119are made of silicon. In one embodiment, the epitaxial layers119only grow on the SiGe portions of the fins112corresponding to the mandrel layer102ofFIG. 1, and not on the hard mask portions of the fins112corresponding to the hard mask layer103ofFIG. 1.

InFIG. 12, an intermediate fin field-effect transistor (finFET) device1001is shown having spaces around the fins112filled in with the oxide material113. The filling may occur by any deposition process.

InFIG. 13, an intermediate fin field-effect transistor (finFET) device100mis shown having the caps112bremoved from bases112aof the fins112. The removal may be by any etching process, including chemical, laser, or any other appropriate etching process.

FIG. 14illustrates an intermediate finFET device100nhaving the bases112aof the fins112removed and the oxide layer113aetched back to expose the epitaxially-grown layers119as free-standing fins. In one embodiment, the fins119extend into the oxide layer113aand are separate from each other in the oxide layer113a.

FIG. 15illustrates a fin field-effect transistor (finFET) assembly400according to an embodiment of the present invention. The finFET assembly400includes the substrate401, a first finFET device410a, a second finFET device410b, and a third finFET device410c. While only three finFET devices are illustrated for purposes of description, embodiments of the invention encompass any number of finFET devices. The first finFET device410aincludes merged source/drain (SD) regions417a, including a filling layer419a, or dielectric layer419a, formed around a fin418a, and a contact layer420aformed on the dielectric layer419a. A gate structure421ais located between the SD regions417a, and the gate structure includes a contact422a.

Similar to the first finFET device410a, the second finFET device410bincludes merged source/drain (SD) regions417b, including a filling layer419b, or dielectric layer419b, formed around a fin418b, and a contact layer420bformed on the dielectric layer419b. A gate structure421bis located between the SD regions417b, and the gate structure421bincludes a contact422b.

The third finFET device410cincludes merged source/drain (SD) regions417c, including a filling layer419c, or dielectric layer419c, formed around multiple fins418cand418d, and a contact layer420cformed on the dielectric layer419c. A gate structure421cis located between the SD regions417c, and the gate structure421cincludes a contact422c.

In embodiments of the invention, densely-spaced fins for finFET devices are formed by epitaxially growing the fins on sides of narrow bands of silicon, also referred to as mandrels, or fins. The mandrels may be formed by an SIT process, which is limited to forming fins up to a first predetermined density. By epitaxially growing fins on the mandrels and removing the mandrels, the fins may have a second density that effectively doubles that of the SIT process, or halves the pitch between fins, allowing for the fabrication of compact finFET circuitry.