Semiconductor device and manufacturing method thereof

A semiconductor package includes a semiconductor package, a cap, a seal, and microstructures. The semiconductor package includes at least one semiconductor die. The cap is disposed over an upper surface of the semiconductor package. The seal is located on the semiconductor package and between the cap and the semiconductor package. The cap includes an inflow channel and an outflow channel. The active surface of the at least one semiconductor die faces away from the cap. The cap and an upper surface of the semiconductor package define a circulation recess providing fluidic communication between the inflow channel and the outflow channel. The seal is disposed around the circulation recess. The microstructures are located within the circulation recess, and the microstructures are connected to at least one of the cap and the at least one semiconductor die.

BACKGROUND

As electronic products are continuously miniaturized, heat dissipation of the packaged semiconductor die(s) has become an important issue for packaging technology. In addition, for multi-die packages, the arrangement of the dies and the corresponding connecting elements has impact on data transmission speed among semiconductor dies and reliability of the packaged products.

DESCRIPTION OF THE EMBODIMENTS

FIG. 1AthroughFIG. 1Hare schematic cross-sectional views illustrating intermediate structures produced during a manufacturing method of a semiconductor device SD1(shown inFIG. 1H). According to some embodiments of the present disclosure, a semiconductor package100A (shown inFIG. 1D) is provided via the steps illustrated inFIG. 1AthroughFIG. 1C.

Referring toFIG. 1A, in some embodiments, semiconductor dies110,120,130are bonded to an interposer140. In some embodiments, the semiconductor die110includes a semiconductor substrate112, a plurality of contact pads114and a passivation layer116. The contact pads114may be formed on a surface of the semiconductor substrate112covered by the passivation layer116and be exposed through a plurality of openings of the passivation layer116. In some embodiments, die connectors118may be connected to the contact pads114through openings of the passivation layer116, and may be used to connect the semiconductor die110to other devices or components. In some embodiments, the surface of the semiconductor die110in which the contact pads114or the die connectors118are exposed is referred to as an active surface110a. In some embodiments, the semiconductor substrate112may be made of semiconductor materials, such as semiconductor materials of the groups III-V of the periodic table. In some embodiments, the semiconductor substrate112includes elementary semiconductor materials such as silicon or germanium, compound semiconductor materials such as silicon carbide, gallium arsenide, indium arsenide, or indium phosphide or alloy semiconductor materials such as silicon germanium, silicon germanium carbide, gallium arsenide phosphide, or gallium indium phosphide. In some embodiments, the semiconductor substrate112may include silicon on insulator (SOI) or silicon-germanium on insulator (SGOI). In some embodiments, the semiconductor substrate112includes active components (e.g., transistors or the like) and optionally passive components (e.g., resistors, capacitors, inductors, or the like) formed therein. In certain embodiments, the contact pads114include aluminum pads, copper pads, or other suitable metal pads. In some embodiments, the passivation layer116may be a single layer or a multi-layered structure, including a silicon oxide layer, a silicon nitride layer, a silicon oxy-nitride layer, a dielectric layer formed by other suitable dielectric materials or combinations thereof. In some embodiments, the die connectors118includes copper, copper alloys, or other conductive materials, and may be formed by deposition, plating, or other suitable techniques. In some embodiments, the die connectors118are prefabricated structures attached over the contact pads114. In some embodiments, the die connectors118are solder balls, metal pillars, controlled collapse chip connection (C4) bumps, micro bumps, bumps formed via electroless nickel-electroless palladium-immersion gold technique (ENEPIG), combination thereof (e. g, a metal pillar with a solder ball attached), or the like. In some embodiments, similar structural features as the ones just discussed for the semiconductor die110may be found in the other semiconductor dies of the semiconductor package100A being formed (for example, in the semiconductor dies120,130shown inFIG. 1A).

Each of the semiconductor dies110,120,130may independently be or include a logic die, such as a central processing unit (CPU) die, a graphic processing unit (GPU) die, a micro control unit (MCU) die, an input-output (I/O) die, a baseband (BB) die, or an application processor (AP) die. In some embodiments, one or more of the semiconductor dies110,120,130include a memory die such as a high bandwidth memory die. In some embodiments, the semiconductor dies110,120,130may be the same type of dies or perform the same functions. In some embodiments, the semiconductor dies110,120,130may be different types of dies or perform different functions. In some embodiments, the semiconductor die110includes a logic die, and the semiconductor dies120and130include memory dies. In some embodiments, the semiconductor dies120and130are memory stacks, including multiple chips122,132stacked on top of each other and electrically connected by the connectors124,134. When the memory dies120,130includes multiple chips122,132, each one of the chips122,132may have a structure similar to the one previously described for the semiconductor die110. An insulating layer126,136may be disposed in between adjacent chips122,132to protect the chips122,132and the connectors124,134. In some embodiments, a material of the insulating layer126,136may include a molding compound, a molding underfill, an epoxy, or a resin. In some embodiments, the semiconductor dies120,130include connectors128,138to electrically connect with other components or devices. In some embodiments, the interposer140is made of a semiconductor material, similarly to what was previously discussed with reference to the semiconductor substrate112. In one embodiment, the interposer140includes a silicon wafer.

In some embodiments, the semiconductor dies110,120,130are bonded via the connectors118,128,138to through vias142formed within the interposer140. According to some embodiments, the semiconductor dies110,120,130are disposed with the active surfaces110a,120a,130afacing the interposer140. In some embodiments, as illustrated inFIG. 1A, the through vias142may be formed in the interposer140, and extend formed on a top surface140tinto the interposer140in a thickness direction T of the interposer140without emerging on the bottom surface140b. Alternatively stated, according to some embodiments, at the manufacturing stage illustrated inFIG. 1Athe conductive vias142may be exposed on the top surface140tof the interposer140, and inserted in the interposer140for only a fraction of its thickness T. In some embodiments, a material of the through vias142includes one or more metals. In some embodiments, the metal material of the through vias142may be copper, titanium, tungsten, aluminum, the alloys, the combinations or the like. In some embodiments, passivation layers (not shown) may be formed on one or both of the top surface140tand the bottom surface140bof the interposer140. When present, the passivation layers (not shown) include a plurality of openings exposing the through vias142.

In some embodiments, after bonding the semiconductor dies110,120,130to the through vias142, an underfill150,152,154may be disposed between the semiconductor dies110,120,130and the interposer140to protect the connectors118,128,138against thermal or physical stresses and secure the electrical connection of the semiconductor dies110,120,130with the through vias142. In some embodiments, the underfill150,152,154is formed by capillary underfill filling (CUF). A dispenser (not shown) may apply a filling material (not shown) along the perimeter of the semiconductor dies110,120,130. In some embodiments, heating may be applied to let the filling material penetrate in the interstices defined by the connectors118,128,138between the semiconductor dies110,120,130and the interposer140by capillarity. In some embodiments, a curing process is performed to consolidate the underfill150,152,154. In some embodiments, as shown inFIG. 1A, multiple underfill portions150,152,154are formed, each portion150,152,154securing the connectors118,128,138of a semiconductor die110,120,130. In some alternative embodiments, a single underfill (not shown) may extend below the semiconductor dies110,120,130depending on the spacing and relative positions of the semiconductor dies110,120,130over the interposer140.

InFIG. 1Aonly three semiconductor dies110,120,130are shown on the interposer140for simplicity, but the disclosure is not limited thereto. In some embodiments, the semiconductor package being formed may include more or fewer semiconductor dies than what illustrated in FIG.1A, as well as other components (e.g., dummy dies, stress release layers, interconnect structures, support pillars, etc.). Furthermore, whilst the process is currently being illustrated for a Chip-on-Wafer-on-Substrate (CoWoS) package, the disclosure is not limited to the package structure shown in the drawings, and other types of package such as integrated fan-out (InFO) packages, package-on-packages (PoP), etc., are also meant to be covered by the present disclosure and to fall within the scope of the appended claims.

Referring toFIG. 1B, an encapsulant160is formed over the interposer140wrapping the semiconductor dies110,120,130. In some embodiments, the encapsulant160is formed by completely covering the semiconductor dies110,120,130with an encapsulation material (not shown), and then performing a planarization process (e.g., a mechanical grinding process and/or a chemical mechanical polishing step) until the backside surfaces110b,120b,130bof the semiconductor dies110,120,130are exposed. In some embodiments, the encapsulation material may be a molding compound, a molding underfill, a resin (such as an epoxy resin), or the like. In some embodiments, the encapsulation material is formed by an over-molding process. In some embodiments, the encapsulation material is formed by a compression molding process. In some embodiments, the encapsulation material may require a curing step.

In some embodiments, a temporary carrier TC having a de-bonding layer DB formed thereon is disposed on the top surface160tof the encapsulant160and on the backside surfaces110b,120b,130bof the semiconductor dies110,120,130. In some embodiments, the backside surfaces110b,120b,130bare opposite to the active surfaces110a,120a,130a. In some embodiments, the temporary carrier TC is a glass substrate, a metal plate, a plastic supporting board or the like, but other suitable substrate materials may be used as long as the materials are able to withstand the subsequent steps of the process. In some embodiments, the de-bonding layer DB includes a light-to-heat conversion (LTHC) release layer, which facilitates peeling the temporary carrier TC away from the semiconductor package when required by the manufacturing process. In some embodiments, a die attach film (not shown) may be formed over the de-bonding layer DB and be interposed between the de-bonding layer DB and the semiconductor dies110,120,130, and between the de-bonding layer DB and the encapsulant160.

InFIG. 1B&FIG. 1C, only a single package unit is shown for simplicity, however, the disclosure is not limited thereto. In some embodiments, multiple package units are formed simultaneously on the interposer140. In other words, the exemplary processes may be performed at a reconstructed wafer level, so that multiple package units are processed in the form of a reconstructed wafer RW. In some embodiments, the package structure is in a form of a reconstructed wafer RW, and the reconstructed wafer RW includes a plurality of package units. In some alternative embodiments, the package structure is in a form of a reconstructed panel, including a plurality of package units arranged in an array.

Referring toFIG. 1C, the reconstructed wafer RW may be overturned on the temporary carriage TC to work on the interposer140from its bottom surface140b. In some embodiments, a grinding process is performed on the interposer140by removing the semiconductor material from the bottom surface140bto thin the interposer140until the through vias142are exposed from the bottom surface140b. Optionally, a silicon etching process may be performed to further expose the through vias142. A passivation layer (not shown) including openings exposing the through vias142may optionally be formed on the bottom surface140bafter the thinning process. Connectors170are formed on the exposed through vias142to provide electrical connection with other components. The connectors170may be any one of the structures disclosed previously for the connectors118, or any combination thereof. In some embodiments, under-bump metallurgies (not shown) are formed on the exposed through vias142before providing the connectors170.

In some embodiments, as shown inFIG. 1C, a singulation step is performed to separate the individual package units100A, for example, by cutting through the reconstructed wafer RW along the scribing lanes SC arranged between individual package units100A. In some embodiments, adjacent packages100A may be separated by cutting through the scribing lanes SC of the reconstructed wafer RW. In some embodiments, the singulation process typically involves performing a wafer dicing process with a rotating blade and/or a laser beam. In some embodiments, the de-bonding layer DB (e.g., the LTHC release layer) is irradiated with a UV laser so that the carrier TC and the de-bonding layer DB are easily peeled off from the semiconductor packages100A. Nevertheless, the de-bonding process is not limited thereto, and other suitable de-bonding methods may be used in some alternative embodiments.

In some embodiments, as illustrated inFIG. 1D, the semiconductor package100A is bonded to a top surface200tof a substrate200via the connectors170. In some embodiments, a material of the substrate200is chosen from the same semiconductor materials listed above for the interposer140. In some embodiments, the substrate200may be a package substrate or BGA substrate including one or more active components, passive components, or a combination thereof. The active and passive components may be formed using any suitable method. The substrate200may also include interconnection structures and/or redistribution layers (not shown) to connect various components therein to form functional circuitry. In some embodiments, the substrate200may be provided for dual-side electrical connection.

In some embodiments, an underfill180may fill the interstices formed by the connectors170between the semiconductor package100A and the substrate200. In some embodiments, a material and a manufacturing method of the underfill180are similar to the materials and manufacturing methods described for the underfills150,152,154with reference toFIG. 1A, and a detailed description thereof is omitted herein.

In some embodiments, referring toFIG. 1E, an auxiliary mask M1is disposed on the substrate200covering a portion of the top surface200tsurrounding the semiconductor package100A and, optionally, a bottom surface200b. In some embodiments, the auxiliary mask M1is a pre-fabricated mask including an opening O1surrounding the area of the substrate200in which the package100A is disposed. In some alternative embodiments, the auxiliary mask M1is a protective tape that is disposed over the substrate200. In some alternative embodiments, the auxiliary mask M1is a patterned photoresist. In some embodiments, a protection jig is used as the auxiliary mask M1.

In some embodiments, a metallization precursor layer300ais conformally formed over the top surface200tof the substrate200. The metallization precursor layer300amay cover the semiconductor package100A, the underfill180, and at least the portion of the mask M1formed over the top surface200t. The metallization precursor layer300amay be formed through, for example, a sputtering process, a physical vapor deposition (PVD) process, a plating process, or the like. In some embodiments, the metallization precursor layer300aincludes, for example, copper, tantalum, titanium-copper alloys, or other suitable metallic materials. In some embodiments, the metallization precursor layer300aincludes, for example, polymers, hybrid materials or other suitable materials. In some embodiments, the formation of the metallization precursor layer300ais optional and may be skipped. Referring toFIG. 1EandFIG. 1Fsimultaneously, with the removal of the auxiliary mask M1, the portion of metallization precursor layer300adeposited over the auxiliary mask M1is also removed, leaving a metallization layer300that extends on the semiconductor package100A, the underfill180and, optionally, on a region of the substrate200immediately adjacent and surrounding the semiconductor package100A. As shown inFIG. 1F, the metallization layer300at least covers the top surface100tof the semiconductor package100A.

In some embodiments, referring toFIG. 1G, a first bonding material410and a second bonding material420may be disposed over the substrate200and the semiconductor package100A, respectively. In some embodiments, the first bonding material410may extend over the portion of the top surface200tof the substrate where the auxiliary mask M1(shown inFIG. 1E) was located during the formation of the metallization precursor layer300a(shown inFIG. 1E). That is, the first bonding material410may reach the portion of the metallization layer300extending over the substrate200around the semiconductor package100A. In some alternative embodiments, as shown inFIG. 1G, a gap G may exist between the metallization layer300and the first bonding material410. A portion of the top surface200tof the substrate200may be exposed through the gap G. A material of the first bonding material410is not particularly limited, and may be chosen as a function of the materials used for the substrate200and the cover510A (shown inFIG. 1H) of the heat dissipation system500A (shown inFIG. 1H) which the first bonding material410has to secure together. In some embodiments, a material of the first bonding material410includes thermocurable adhesives, photocurable adhesives, thermally conductive adhesive, thermosetting resin, waterproof adhesive, lamination adhesive or a combination thereof. In some embodiments, the material of the first bonding material410includes a thermally conductive adhesive. In some embodiments, the first bonding material410includes a metallic layer (not shown) with solder paste (not shown) deposited thereon. According to the type of material used, the first bonding material410may be formed by deposition, lamination, printing, plating, or any other suitable technique. In some embodiments, portions of the second bonding material420are disposed over the semiconductor package100A, on the metallization layer300(if present). Similar to what was discussed above for the first bonding material410, a material of the second bonding material420may be chosen as a function of the nature of the surfaces to be adhered, and the same materials listed for the first bonding material410may also be used for the second bonding material420. In some embodiments, the material of the second bonding material420is different from the material of the first bonding material410. In some alternative embodiments, the material of the first bonding material410is the same as the material of the second bonding material420. In some embodiments, the material of the second bonding material420includes solder paste or bonding adhesive layer. In some embodiments, the second bonding material420is provided through a printing step, for example via stencil printing.

Referring toFIG. 1H, a heat dissipation system500A is provided over the substrate200and the semiconductor package100A and the semiconductor device SD1is produced. In some embodiments, the heat dissipation system500A includes a cover510A and a seal520. In some embodiments, the cover510A includes a cap512A, and flanges514A at the periphery of the cap512A. In some embodiments, the cap512A is disposed over the semiconductor package100A and extends substantially parallel to the substrate200. The flanges514A may be located at the edge of the cap512A, and project towards the substrate200. In some embodiments, the flanges514A extend in a direction perpendicular to the plane defined by the cap512A. In some embodiments, the flanges514A and the cap512A describe a right angle at their joint, but the disclosure is not limited thereto. In some embodiments, the flanges514A are joined to the cap512A at different angles than 90 degrees. In some embodiments, the flanges514A extend towards the substrate200and surround the semiconductor package100A. In some embodiments, the flanges514A, the cap512A and the substrate200define an enclosure E1surrounding the semiconductor package100A on all sides. In some alternative embodiments, the flanges514A do not entirely enclose the semiconductor package100A. In some embodiments, as shown in the schematic top view ofFIG. 2C, the span of the cap512A extends beyond the span of the semiconductor package100A at two opposite sides, while the span of the cap512A at the other two opposite sides is located within the span of the semiconductor package100A. That is, the flanges514A may face only two opposite sides of the semiconductor package100A, leaving the other sides exposed. In some embodiments, the flanges514A reach the substrate200where the first bonding material410is disposed, and the first bonding material410secures the cover510A within the semiconductor device SD1. In some embodiments, the first bonding material410is disposed on the substrate200only where the flanges514A are expected to contact the substrate200.

In some embodiments, a span of the cap512A may exceed a span of the semiconductor package100A. In some embodiments, the span of the semiconductor package100A may entirely fall within the span of the cap512A. In some embodiments, the cap may present regions of different thickness defining one or more recesses. For example, as shown inFIG. 1H, the cap512A may present a first thickness T1when extending over the substrate200without the semiconductor package100A interposed in between, and one or more regions of different thickness (e.g., T2and T3) when extending over the semiconductor package100A. In some embodiments, a first region of thickness T2smaller than the thickness T1defines a circulation recess R1over a central portion of the semiconductor package100A, and a second region of thickness T3smaller than the thickness T1defines an annular recess R2towards the edge of the top surface100tof the semiconductor package100A. In some embodiments, the cover510A may constitute the ceiling and the walls of the circulation recess R1, and the upper surface100tof the semiconductor package100A (or the metallization layer300when included) may constitute the floor of the circulation recess R1.

In some embodiments, the circulation recess R1extends over the semiconductor dies110,120,130. In some embodiments, the circulation recess R1extends over some but not all of the semiconductor dies110,120,130included in the semiconductor package110A. In some embodiments, the circulation recess R1extends at least over a portion of the semiconductor die110,120, or130that produces the greatest amount of heat during operation of the semiconductor device SD1. In some embodiments, the cap512A includes one or more inflow/outflow channels (e.g., CH1, CH2and CH3inFIG. 1H) in fluid communication with the circulation recess R1. In some embodiments, the inflow/outflow channels CH1, CH2, CH3open in areas overlying the semiconductor dies110,120,130. In some embodiments, the other end of the one or more inflow/outflow channels CH1, CH2, and CH3may open on the top surface512tof the cap512A. In some embodiments, the inflow/outflow channels CH1, CH2, CH3may be open holes having a substantially vertical profile in the thickness direction of the cap512A, but the disclosure is not limited thereto. In some embodiments, at least a portion of one of the channels inflow/outflow CH1, CH2or CH3runs within the cap512A along a direction titled rather than vertical. In some embodiments, portions of the inflow/outflow channels CH1, CH2, CH3run parallel to the substrate200. As explained in further detail below, the inflow/outflow channels CH1, CH2, CH3may be filled by a coolant CL (shown inFIG. 1I) flowing through the circulation recess R1.

In some embodiments, the seal520is accommodated within the annular recess R2and physically contacts (or is slightly compressed by) the cap512A and the semiconductor package100A (or the metallization layer300if included). In some embodiments, the seal520is a seal ring made of a polymeric material, such as an organic resin or rubber, and provides closure and segregation for avoiding fluid leakage from the circulation recess R1. In some embodiments, the seal520may include a silicone filling.

In some embodiments, microstructures516are formed to protrude from the cap512A within the circulation recess R1towards the semiconductor package100A. In some embodiments, the microstructures516define a network of interstices in fluidic communication. In some embodiments, the microstructures516are micro-pillars extending from the cap512A to the semiconductor package100A (or the metallization layer300if included). In some embodiments, the microstructures516are parallel fins defining a serpentine path. In some embodiments, adjacent fins define micro-trenches in between. In some embodiments, the microstructures516land on the semiconductor package100A over the portions of second bonding material420. That is, the second bonding material420may be disposed or patterned so as to match the position of the microstructures516on the cover510A. In some embodiments, the microstructures516are interspersed within the circulation recess R1without interrupting the fluidic communication among the inflow and outflow channels CH1, CH2, CH3.

In some embodiments, a material of the cap512A includes a thermally conductive material. In some embodiments, the material of the cap512A includes metals or metal alloys, such as copper, aluminum, their alloys, the combinations thereof or the like. In some embodiments, the material of the cap512A includes a semiconductor material such as silicon. In some embodiments, the material of the cap512A includes polyimide, epoxy resin, acrylic resin (e.g., polymethylmethacrylate, PMMA), phenol resin, benzocyclobutene (BCB), polybenzooxazole (PBO), or any other suitable polymer-based material. In some embodiments, a material of the flanges514A may be selected from the same materials listed above for the cap512A. In some embodiments, the cap512A and the flanges514A are produced as a single piece (integrally formed). That is, the flanges514A and the cap512A may be fabricated from the same material, and no interface or clear boundary may be visible between the flanges514A and the cap512A. In some embodiments, a material of the microstructures516may be selected from the same materials listed above for the cap512A. In some embodiments, the cap512A and the microstructures516are produced as a single piece of material (integrally formed). That is, the cap512A and the microstructures516may be fabricated together from the same material, and no interface or clear boundary may be visible between the cap512A and the microstructures516.

In some embodiments, the microstructures516and the cap512A are made of a metallic material and the second bonding material420includes a solder paste. As such, the microstructures516and the cap512A may be soldered over the semiconductor package100A or the metallization layer300(if included). In such cases, a joint (shown in the inset ofFIG. 1H) is formed and includes a solder core4201(e.g., SnAg solder) sandwiched between two layers4202and4203including an intermetallic compound (e.g., Ni3Sn4) and two outer metallic layers (e.g., the metallization layer300and the microstructure516or the metallization layer300and the cap512A). That is, the first layer including the intermetallic compound4202may be disposed between the metallization layer300(or the semiconductor package100A) and the solder core4201, and the second layer including the intermetallic compound4203may be disposed between the microstructures516or the cap512A and the solder core4201. Similar solder joints (not shown) may be formed when the flanges514A are formed of a metallic material and the first bonding material410includes solder paste. However, the disclosure is not limited thereto, and different combinations of materials for the cap512A, the flanges514A and the first bonding material410or the microstructures516and the second bonding material420may be envisioned. All these combinations are meant to fall within the scope of the present disclosure and the attached claims.

A method of forming the cover510A may be selected according to the material(s) chosen for the cap512A, the flanges514A and the microstructures516. In some embodiments, the cover510A is molded, forged, 3D-printed, grown, or fabricated according to any other suitable technique. In some embodiments, the cap512A, the flanges514A and the microstructures516are fabricated separately and then assembled to produce the cover510A.

It should be noted that inFIG. 1DthroughFIG. 1H, the manufacturing of a single semiconductor device SD1was shown for simplicity, but the disclosure is not limited thereto. In some embodiments, multiple semiconductor packages100A are disposed simultaneously on the substrate200, which may be in a wafer or panel form. In other words, the exemplary processes may be performed at a reconstructed wafer/panel level, so that multiple semiconductor devices SD1are processed simultaneously in the form of a reconstructed wafer/panel. In some embodiments, a singulation step (analogous to what was described above with reference toFIG. 1D) may be performed.

FIG. 1Iis a schematic cross-sectional view illustrating an electronic device according to some embodiments of the disclosure. In the electronic device ofFIG. 1I, the semiconductor device SD1ofFIG. 1His further connected to a circuit substrate600and a fluid circulation system according to some embodiments of the disclosure. The circuit substrate600may be a motherboard, a printed circuit board, or the like. The semiconductor device SD1may be connected to the circuit substrate600via connectors610disposed on the bottom surface200bof the substrate200.

In some embodiments, as shown inFIG. 1I, the fluid circulation system includes pipes710connected to the cover510A of the heat dissipation system500A and, optionally, washers720, that secure the attachment of the pipes710to the cover510A. In other embodiments, the cover510A may be fabricated with washer(s) fitted into the inflow/outflow channels CH1, CH2, CH3for subsequent connection with pipes or tubes. In some embodiments, the pipes710and the inflow/outflow channels CH1, CH2, CH3present matching treads (not shown), so that the pipes710can be securely fastened into the inflow/outflow channels CH1, CH2, CH3, either directly or through intervening pipe connectors (not shown). In some embodiments, the pipe connectors may include one-way valves that direct the flow of the coolant CL through the circulation recess R1. The pipes710may be connected with the inflow/outflow channels CH1, CH2, CH3formed in the cover510A to allow the coolant CL to flow into the circulating recess R1of the semiconductor device SD1and remove heat generated by the semiconductor package100A during usage. As the flow direction is indicated by the arrows F ofFIG. 1I, some of inflow/outflow channels CH1, CH2, CH3may be used as outflow channels (CH1), and the remaining channels may be used as inflow channels (CH2, CH3). In some embodiments, the outflow channel(s) may be at least as large as the inflow channel(s). In some embodiments, the outflow channel(s) may be larger (has a wider opening) than the inflow channel(s). In some embodiments, the coolant CL flows into the circulating recession R1from the inflow channels CH2, CH3, flows through the microstructures516and flows out from the outflow channel CH1. In some embodiments, a stopper (not shown) may be used to seal any of the inflow/outflow channels CH1, CH2, CH3if so required by the design of the fluid circulation system. In some embodiments, the channels formed over the components of the semiconductor package100A which produce more heat during usage are used as outflow channels. For example, if the semiconductor package100A includes a logic chip and a memory chip, and the power consumption of the logic chip is generally higher than the power consumption of the memory chip, as outflow channel may be used the channel(s) formed overlying the logic chip. However, the disclosure is not limited thereto. In some alternative embodiments, the channels formed over the memory chip are used as outflow channels. In some embodiments, the coolant CL is a liquid. In some embodiments, the coolant CL is water. In some embodiments, additives are added to the water to produce a cooling fluid. Examples of additives include surfactants, corrosion inhibitors, biocides, antifreeze, and the like.

InFIG. 2Ais shown a schematic top view of the semiconductor device SD1ofFIG. 1Haccording to some embodiments of the disclosure. For the sake of clarity, only some of the components (or portions of said components) are schematically represented. Referring toFIG. 1HandFIG. 2A, in some embodiments, a span of the cover510A matches a span of the substrate200, so that the flanges514A substantially fall on the edge of the substrate200. In some alternative embodiments, the span of the substrate200may be larger than the span of the cover510A, so that the substrate200may protrude from below the cover510A when viewed from the top. In some embodiments, the seal520has an annular shape, and is disposed close to the edge of the semiconductor package100A. In some embodiments, protrusions of the cap512A extend between the seal520and the edge of the semiconductor package100A, keeping the seal520in place. The positions of the semiconductor dies110,120,130are schematically illustrated by dashed lines inFIG. 2A. In some embodiments, each inflow/outflow channel CH1, CH2, CH3opens on a different semiconductor die110,120,130, but the disclosure is not limited thereto. The cover510A includes the microstructures516formed within the area surrounded by the seal520. In some embodiments, no microstructures516are formed in correspondence of the inflow/outflow channels CH1, CH2, CH3. In one embodiment, the microstructures516includes round pillars arranged in arrays, surrounding the inflow/outflow channels CH1, CH2, CH3and are located within the span of the seal520.

InFIG. 2Bis shown a schematic top view of a semiconductor device SD2according to some embodiments of the disclosure. In some embodiments, the semiconductor device SD2may be similar to the semiconductor device SD1ofFIG. 1I, and the description of the same or similar parts will be omitted for the sake of brevity. A difference between the semiconductor device SD2ofFIG. 2Band the semiconductor device SD1ofFIGS. 2A and 1His that the semiconductor package100B of the semiconductor device SD2includes two dummy dies190A and190B disposed beside the two semiconductor dies120and130. In some embodiments, the dummy dies190A and190B act as stress dissipating structures, by avoiding the presence within the semiconductor package100B of extended areas filled by the sole encapsulant160(shown inFIG. 1B). In some embodiments, the dummy dies190A,190B are blocks of a material different from the encapsulant160. In some embodiments, a material of the dummy dies190A,190B includes a semiconductor material, similar to what was discussed above for the semiconductor substrate112with reference toFIG. 1A. In some embodiments, neither active nor passive devices are formed within the dummy dies190A,190B. In some embodiments, the material of the dummy dies190A,190B includes a conductive material, such as metals. In some embodiments, the dummy dies190A,190B may further include one or more dielectric layers.

In some embodiments, as shown inFIG. 2B, the cover510B includes more channels CH than the cover510A ofFIG. 2A. In some embodiments, an inflow/outflow channel CH is formed over each one of the semiconductor dies120and130, and the dummy dies190A,190B, and other two inflow/outflow channels CH are formed over the semiconductor die110. In some embodiments, the inflow/outflow channels CH formed over the semiconductor die110are used as outflow for the coolant CL (shown inFIG. 1I), whilst the remaining inflow/outflow channels CH are used as inflow channels. In some alternative embodiments, different channels are used for the inflow and outflow of the coolant CL. In some embodiments, one or more of the inflow/outflow channels CH illustrated inFIG. 2Bmay be omitted. For example, no inflow/outflow channels CH may be formed on top of the dummy dies190A,190B or of some of the semiconductor dies110,120, and130. In some alternative embodiments, more than one inflow/outflow channel CH may be formed for each semiconductor die110included in the semiconductor device SD2.

In some embodiments, as illustrated inFIG. 2B, secondary microstructures530may be formed on the semiconductor package100B in correspondence of the inflow/outflow channels CH. In some embodiments, the secondary microstructures530are formed in the locations in correspondence of all the inflow/outflow channels CH formed in the cover510B. In some alternative embodiments, the secondary microstructures530are formed in the locations in correspondence of only some of the inflow/outflow channels CH of the cover510B. For example, the secondary microstructures530may be formed only in correspondence of the inflow/outflow channels CH opening on the semiconductor device110. Non-limiting examples of the secondary microstructures530will be illustrated with reference toFIG. 3AthroughFIG. 3C. It should be noted that whilst the secondary microstructures530are discussed with reference to the semiconductor device SD2or the cover510B, the secondary microstructures530may be formed within all of the other disclosed semiconductor devices. For example, the secondary microstructures530may be formed on the upper surface100tof the top package100A (shown inFIG. 1H) when the semiconductor device SD1includes the cover510A.

FIG. 3AthroughFIG. 3Care schematic cross-sectional views illustrating portions of some semiconductor devices according to some embodiments of the present disclosure. The views ofFIG. 3AthroughFIG. 3Ccorrespond to the area A1shown inFIG. 1I. In some embodiments, the secondary microstructures530includes pillars531attached to the semiconductor die110(or the metallization layer300, if included) through additional bonding material422. A material of the secondary microstructures530(pillars531) may be selected from the same materials listed above for the cover510A, and the same considerations with respect to the choice of the additional bonding material422apply as well. In some embodiments, a material of the secondary microstructures530includes metals or metal alloys, and the additional bonding material422includes solder paste to form a solder joint. In some embodiments, as shown inFIG. 3B, the secondary microstructures530include metal pads532, which may be directly disposed on the semiconductor die110(or120or130) or the metallization layer300(if included) without intervening bonding material. In some embodiments, the secondary microstructures530include pillars (or fins)533protruding directly from the semiconductor die110. In some embodiments, the secondary microstructures530are pre-fabricated structures that are disposed on the underlying semiconductor die110or metallization layer300via a bonding material422before placing the cover510B. In some alternative embodiments, the secondary microstructures530are directly grown on the semiconductor die110or the metallization layer130, for example via a deposition or a plating step. In some embodiments, auxiliary masks (not shown) are used while growing the secondary microstructures530to define a pattern for the secondary microstructures530.

FIG. 3DthroughFIG. 3Fare schematic cross-sectional views illustrating portions of some semiconductor devices according to some embodiments of the present disclosure. The views ofFIG. 3DthroughFIG. 3Fcorrespond to the area A2shown inFIG. 1I. In some embodiments, the second bonding material420may include multiple portions420G,420S,420E. In some embodiments the portions of the second bonding material420may include different materials. For example, as shown inFIG. 3D, the second bonding material420may include portions420S disposed between the cap512A and the metallization layer300(or to the underlying semiconductor package if the metallization layer300is not included), and portions420G disposed within the second recess R2, between the seal ring520and the metallization layer300(or the underlying semiconductor package). In some embodiments, portions420S may include solder paste, and portions420G may include one or more graphene films. One or more microstructures516may protrude from the cap512A in the portion of the cap512A extending between the second recess R2and the inflow/outflow channel CH. That is, the circulation recess R1may extend below the cap512A towards the second recess R2, without being in fluid communication with the second recess R2. The solder portions420S may be disposed between the microstructures516and the metallization layer300, while the graphene portions420G may be disposed within the second recess R2. As shown inFIG. 3D, in some embodiments, solder portions420S are disposed between the graphene portions420G and the circulation recess R1, along a protrusion of the cap512A separating the second recess R2from the circulation recess R1. As shown inFIG. 3E, in some embodiments, solder portions420S are disposed all along the protrusions of the cap512A defining the second recess R2. The graphene portions420G may be surrounded by solder portions420S. In some embodiments, as shown inFIG. 3D, the graphene portions420G are disposed directly on the metallization layer300. In some alternative embodiments, an adhesive portion420E may be disposed between the graphene portions420G and the metallization layer300. In some embodiments, the adhesive portion420E and the overlying graphene portion420G may be collectively referred to as a graphene tape. In some embodiments, the adhesive portion420E includes an epoxy resin. That is, the adhesive portion420E, the graphene portion420G and the seal ring520may be stacked in this order on the metallization layer300within the second recess R2. In some alternative embodiments, as shown inFIG. 3F, the second recess R2may be omitted from the cap512A′. That is, the cap512A′ may define the circulation recess R1, but not the second recess R2. In these embodiments, the seal ring520(shown inFIGS. 3D and 3E) is also omitted. A solder portion420S may be disposed between the cap512A′ and the metallization layer300(or the underlying semiconductor package). That is, the second bonding material420may include the solder portion420S without including the graphene portion420G or the adhesive portion420E. In some embodiments, the solder portion420S extends substantially uninterruptedly in the contact area between the cap512A′ and the metallization layer300(or the underlying semiconductor package).

In some embodiments, the solder portions420S are provided by screen printing, and the cap (e.g.,512A) is subsequently disposed on the solder portion. In some embodiments, the graphene portion420G or the graphene tape (420G and420E) are disposed on the metallization layer300before screen printing the solder portions420S, but the disclosure is not limited thereto. In some embodiments, the solder portions420S are screen-printed on the metallization layer300before disposing the graphene portion420G or the graphene tape420G and420E. In some embodiments, the seal ring520is disposed on the graphene portion420G before placing the cap (e.g.,512A) on the metallization layer300. In some alternative embodiments, the seal ring520is embedded in the second recess R2of the cap (e.g.,512A), and the cap and the seal ring520are disposed simultaneously on the metallization layer300.

FIG. 4AthroughFIG. 4Dare schematic top views illustrating portions of some semiconductor devices according to some embodiments of the present disclosure. InFIG. 4AthroughFIG. 4Dare shown portions of the circulation recess R1including the microstructures516, however, similar considerations may be applied to all the microstructures of the present disclosure. In the views ofFIG. 4AthroughFIG. 4D, the incident flow of the coolant CL (shown inFIG. 1I) is represented by the arrows F. In some embodiments, the arrows F are oriented along a first direction X. The structure of the microstructures516is described inFIG. 4AthroughFIG. 4Dwith respect to the first direction X and a second direction Y perpendicular to X. The plane XY defined by the directions X and Y is substantially parallel to the plane of the metallization layer300or the top surface100tof the semiconductor package100A. It should be noted that whilst most of the microstructures516shown inFIG. 4AthroughFIG. 4Dare shown with a specific orientation within the plane XY, the disclosure is not limited thereto. In some embodiments, the microstructures516may be included in a tilted orientation with respect to what is shown inFIG. 4AthroughFIG. 4D.

In some embodiments, as shown inFIG. 4A, the microstructures516A have an elliptical cross section in the plane XY. In some embodiments, a first axis Lx of the microstructures516A lies parallel to the first direction X, and the second axis Ly lies parallel to second direction Ly. In some embodiments, a pitch Px in the first direction X may be defined as the distance between corresponding points of two microstructures516A having the first axis Lx lying along a first straight line, and the pitch Py in the second direction Y may be defined as the distance between corresponding points of two microstructures516A having the second axis Ly lying along a second straight line. In some embodiments, the pitch Px and the pitch Py may be optimized as a function of the dimensions of the axes Lx and Ly to fine-tune the flow F of the coolant CL (shown inFIG. 1I) over the semiconductor package100A. In some embodiments, the pitches Px, Py and the dimensions of the axes Lx, Ly may be chosen to ensure optimal heat exchange with the coolant CL.

In some embodiments, as shown inFIG. 4B, the microstructures516B have a substantially circular cross-section in the plane XY. In some embodiments, the pitch Px is defined between microstructures516B having the centers C lying on a first straight line parallel to the first direction X, and the pitch Py is defined between microstructures516B having the centers C lying on a second straight line parallel to the second direction Y. In some embodiments, the pitches Px, Py and the diameter D of the cross-section of the microstructures516B may be chosen to ensure optimal heat exchange between the semiconductor package and the coolant CL (shown inFIG. 1I).

In some embodiments, as shown inFIG. 4C, the microstructures516C have a rectangular cross section in the plane XY. In some embodiments, a first side Lx of the microstructures516C lies parallel to the first direction X, and a second side Ly lies parallel to second direction Y. In some embodiments, the first side Lx and the second side Ly may have equal length, and the microstructures516C may have a square cross-section. In some embodiments, the pitch Px in the first direction X is defined as between two microstructures516C having the first side Lx lying along a first straight line, and the pitch Py in the second direction Y is defined as between two microstructures516C having the second side Ly lying along a second straight line. In some embodiments, the pitches Px, Py and the dimensions of the sides Lx, Ly may be chosen to ensure optimal heat exchange between the semiconductor package and the coolant CL (shown inFIG. 1I).

In some embodiments, as shown inFIG. 4D, the microstructures516D have a rhombic or rhomboid cross section in the plane XY. In some embodiments, a first axis Lx of the microstructures516D lies parallel to the first direction X, and a second axis Ly lies parallel to second direction Y. In some embodiments, the first axis Lx and the second axis Ly may have equal length, and the microstructures516D may have a rhombic cross-section. In some embodiments, the pitch Px in the first direction X is defined between two microstructures516D having the first axis Lx lying along a first straight line, and the pitch Py in the second direction Y is defined between two microstructures516D having the second axis Ly lying along a second straight line. In some embodiments, the pitches Px, Py and the dimensions of the axes Lx, Ly may be chosen to ensure optimal heat exchange between the semiconductor package and the coolant CL (shown inFIG. 1I).

FIG. 5AthroughFIG. 5Care schematic cross-sectional views illustrating intermediate structures formed at various stages of a manufacturing method of a semiconductor device SD3(shown inFIG. 5C) according to some embodiments of the present disclosure. In some embodiments, the intermediate structure shown inFIG. 5Amay be obtained from the intermediate structure shown inFIG. 1Dby disposing the first bonding material410B on the substrate200and disposing a support540of the heat dissipation system500C over the first bonding material410B. In some embodiments, the support540surrounds the semiconductor package100A. In some embodiments, the support540presents a concave recess E2oriented towards the semiconductor package100A. That is, a width W of the support540measured parallel to an extending direction of the substrate200may increase for portions of the support540further away from the substrate200. In some embodiments, as shown inFIG. 5A, the width W of the support may be substantially constant closer to the substrate200, then gradually increase with increasing distance from the substrate200, and then remain substantially constant, thus resulting in a concave shape and an inclined surface540S facing the semiconductor package100A. In some alternative embodiments, the width W may increase in a discontinuous manner, and the support540may present one or more steps (not shown) facing the semiconductor package100A. In some embodiments, the support540has an annular shape, and surrounds the semiconductor package100A on all sides. In some alternative embodiments, the support540faces less than all of the sides of the semiconductor package100A. For example, if the semiconductor package100A has a rectangular shape, the support540may face three sides of the semiconductor package100A rather than four. In some embodiments, the support540may include multiple separated pieces (not shown) disposed around the semiconductor package100A. For example, the support540may include a first piece (not shown) facing a first side of the semiconductor package100A and a second piece (not shown) facing a second side of the semiconductor package100A. In some embodiments, the first side and the second side are opposite sides of the semiconductor package100A, but the disclosure is not limited thereto. In some alternative embodiments, the first side and the second side are contiguous sides of the semiconductor package100A. In some embodiments, recesses R3open on the top surface540tof the support540. In some embodiments, the recesses R3are configured to accommodate fasteners (e.g., screws, nails, and the like). In some embodiments, the recesses R3are threaded. The disclosure is not limited by the number of recesses R3formed on the top surface540tof the support. In some embodiments, a single recess R3is formed on the top surface540t. In some alternative embodiments, multiple recesses R3are formed.

Referring toFIG. 5B, in some embodiments, an auxiliary mask M2is disposed over the support540and, optionally, on the bottom surface200bof the substrate200(not shown). In some embodiments, the auxiliary mask M2includes an opening O2exposing the semiconductor package100A. In some embodiments, the opening O2further exposes at least a portion of the underfill180. In some embodiments, options similar to what was previously discussed for the auxiliary mask M1with reference toFIG. 1Emay be used for the auxiliary mask M2, and a detailed description thereof is omitted herein. In some embodiments, the metallization layer300B is formed within the opening O2of the auxiliary mask M2, covering the top surface100tof the semiconductor package100A. In some embodiments, the metallization layer300B may extend over a top portion of the underfill180, closer to the top surface100tof the semiconductor package100A. In some embodiments, the metallization layer300B does not extend in direct contact with the substrate200.

Referring toFIG. 5C, positioning of the seal520and the cover510C over the support540and the semiconductor package100A completes the semiconductor device SD3. In some embodiments, the cover510C includes a cap512C and microstructures516. Similar to what was previously discussed with reference to the cover510A, the cover510C may define the circulation recess R1over the central portion of the semiconductor package100A and the annular recess R2towards the edge of the top surface100tof the semiconductor package100A. The seal520may be disposed within the annular recess R2. The microstructures516may be located within the circulation recess R1. Channels CH for the circulation of a coolant CL (shown inFIG. 1I) may open within the cap512C in correspondence of the semiconductor package100A. In some embodiments, fastening holes FH open within the cap512C in correspondence of the recesses R3of the support540, and a fastener920(e.g., a screw, optionally secured by washers910,912) may be used to secure the cover510C to the support540. In some embodiments, other types of fasteners (e.g., nails, clamp, tape or the like) may be used to secure the cover510C to the support540. In some embodiments, the position (or the inclusion) of the recesses R3within the support540and the fastening holes FH within the cover510C may be adapted according to the type of fastener used. In some embodiments, depending on the type of fastener920used, the fastening holes FH or the recesses R3may be formed on different surfaces of the cover510C and the support540than the ones illustrated inFIG. 5C.

FIG. 6Ais a schematic cross-sectional view illustrating an electronic device according to some embodiment of the disclosure. In the electronic device ofFIG. 6A, the semiconductor device SD4is connected to a circuit substrate600and a fluid circulation system according to some embodiments of the disclosure. In some embodiments, as illustrated inFIG. 6A, the semiconductor package100C may include different components than the semiconductor packages100A,100B discussed above. For example, the semiconductor package100C may further include dummy dies190A,190B, optionally secured with bonding adhesives192A,192B. In some embodiments, the metallization layer310is optionally formed on the top surface100tof the semiconductor package100C, and does not extend beyond a perimeter of the top surface100t.

According to some embodiments, in the semiconductor device SD4, the cover510D of the heat dissipation system500D includes the cap512D and the flanges514D. A structural difference between the semiconductor device SD4and the semiconductor device SD1ofFIG. 1His that the flanges514D of the semiconductor device SD4sit on the top surface100tof the semiconductor package100C, rather than sitting on the substrate200. That is, the cover510D is secured by a bonding material430disposed towards the periphery of the semiconductor package100C. In some embodiments, the dummy dies190A,190B are disposed in at least some of the parts of the semiconductor package100C where the flanges514D land, to provide structural support.

In some embodiments, the cover510D defines the circulation recess R1together with the semiconductor package100C. In some embodiments, no annular recess R2is formed and no seal is disposed within the cover. In some embodiments, the bonding material430performs the two functions of securing the cover510D to the semiconductor package100C and sealing the circulation recess R1as the seal, to prevent the coolant CL to infiltrate or spill over the substrate200or the circuit substrate600. In some alternative embodiments, the annular recess R2is formed, and the seal is disposed therein as discussed above for the previous embodiments.

In some embodiments, at least some of the inflow/outflow channels CH formed in the cover510D reach the circulation recess R1in correspondence of the encapsulant160rather than the semiconductor dies110,120,130. For example, in the semiconductor device SD4illustrated inFIG. 6A, the inflow channel CH is disposed over the semiconductor die110, and two outflow channels CH are disposed over the portions of encapsulant160comprised between the semiconductor dies120,130and the dummy dies190A,190B. However, the disclosure is not limited thereto. In some embodiments, the number of inflow/outflow channels CH may be adjusted based on design requirements.

In some embodiments, microstructures550are secured or grown over the cover510D. In some embodiments, the microstructures550are pre-formed pillars that are secured to the cap512D in correspondence of the circulation recess R1via a bonding material440. In some embodiments, the microstructures550includes carbon nanotubes grown on or attached to the metallization layer310. In some embodiments, the carbon nanotubes may be grown on a growth substrate (not shown) and then transferred to the metallization layer310. The growth substrate may include alumina and iron. In some embodiments, organic hydrocarbon gas (e.g., acetylene) may be used as a precursor for the growth of the carbon nanotubes. A height of the carbon nanotubes may be adjusted by regulating the growth time. In some embodiments, titanium and gold may be sputtered on the carbon nanotubes before transferring to the metallization layer310. In some embodiments, the metallization layer310includes stacked metal layers to which the carbon nanotubes are transferred. In some embodiments, the metallization layer310may include stacked layers of titanium, gold and indium. The transfer may take place by pressing the growth substrate on the semiconductor package100D with the carbon nanotubes oriented towards the metallization layer310. In some embodiments, the transfer is conducted under heating and pressure. In some embodiments, the microstructures550include pillars, fins or combinations thereof. In some embodiments, the microstructures550may be coated with a thermally conductive material. In some embodiments, the coating material includes graphene. In some embodiments, the coating material includes metals such as copper or aluminum.

FIG. 6Bis a schematic cross-sectional view illustrating an electronic device according to some embodiments of the disclosure. In the electronic device ofFIG. 6B, the semiconductor device SD5is connected to a circuit substrate600and a fluid circulation system according to some embodiments of the disclosure. The semiconductor device SD5ofFIG. 6Bincludes a different type of semiconductor package(s) when compared with the semiconductor device SD4ofFIG. 6A. In some embodiments, the semiconductor package100D included in the semiconductor device SD5may be an InFO package, while a CoWoS package may be included in the semiconductor package100C ofFIG. 6A. For example, the semiconductor package100D may include a redistribution structure144for redistribution and/or interconnecting the dies. The redistribution structure144may include one or more conductive layers interspersed within one or more dielectric layers. In some embodiments, the redistribution structure144may be directly connected to the circuit substrate600(e.g., without the intermediate substrate200). However, the disclosure is not limited thereto. In some alternative embodiments, the semiconductor package100D may be connected to the circuit substrate600via an intermediate substrate (similar to the substrate200shown inFIG. 1I). Referring toFIG. 6B, in some embodiments, the flange portion514D of the cover510D rests on the semiconductor package100D.

It is understood that the disclosure of the present application is not limited by the embodiments described herein. In some alternative embodiments, a footprint of the cover510D may be larger than the footprint of the semiconductor package100D, and the flange portion514D may fall on the underlying circuit substrate600(or the intermediate substrate200, if included). It will be apparent to people skilled in the art that the disclosure is not limited by the type of package used in the semiconductor devices. For all the semiconductor devices of the present disclosure, different packages (CoWoS, InFO, PoP, etc.) may be used, according to the production and design requirements.

FIG. 7AthroughFIG. 7Gare schematic cross-sectional views illustrating intermediate structures formed at various stages of a manufacturing method of a semiconductor device SD6(shown integrated in an electronic device inFIG. 7H) according to some embodiments of the present disclosure. A precursor (not shown) of the manufacturing intermediate shown inFIG. 7Amay be obtained following a process similar to what previously described for the intermediate structure shown inFIG. 1C, optionally modified to include other components in the semiconductor package (for example, the dummy dies190A,190B and the die attaching film192A,192B). The manufacturing intermediate shown inFIG. 7Amay be obtained from said precursor by protecting the connectors170in a protective layer PL, binding a second temporary carrier TC2over the protective layer PL, overturning the reconstructed wafer RW, de-bonding the first temporary carrier TC (shown inFIG. 1C), and providing an auxiliary mask M3on the surface of the reconstructed wafer RW exposed upon removal of the temporary carrier TC. The auxiliary mask M3may be similar to the auxiliary masks M1and M2discussed above, and a detailed description thereof is omitted herein. In some embodiments, the auxiliary mask M3includes openings O3formed within the span of one of the semiconductor dies1110,1120,1130included in the reconstructed wafer RW. To more clearly illustrate certain aspects of the disclosure, in the present embodiment the semiconductor die1110includes a System on Chip (SoC) type of die, and the semiconductor dies1120,1130are memory cubes. However, the disclosure is not limited by the type of dies used for the semiconductor dies1110,1120,1130. The openings O3may expose portions of the top surface1110tof the semiconductor die1110. The openings O3may be patterned according to the type of microstructures560(shown inFIG. 7H) that are to be formed within the semiconductor die1110. When the semiconductor dies1120,1130are memory cubes, the auxiliary mask M3may completely cover the corresponding top surfaces1120t,1130t.

Referring toFIG. 7B, an auxiliary mask M4may be provided on top of the third auxiliary mask M3. The range of possible materials for the auxiliary mask M4is not particularly limited, provided that the auxiliary mask M4can be selectively etched over the auxiliary mask M3(unless a pre-fabricated rigid mask is used as auxiliary mask M4). In some embodiments, the auxiliary mask M4may be conformally disposed over the auxiliary mask M3, filling the openings O3. Depending on the type of auxiliary mask M4used, in some embodiments, the auxiliary mask M4includes openings O4aligned with the underlying openings O3. In some alternative embodiments, a profile of the auxiliary mask M4is substantially flat throughout the reconstructed wafer RW.

In some embodiments, as shown inFIG. 7C, the auxiliary mask M4is patterned, so as to reveal the top surface1110tof the semiconductor die1110through the aligned openings O3and the openings O4. During the patterning step, openings O5may be produced over the semiconductor dies1120,1130, exposing the underlying auxiliary mask M3. Referring toFIG. 7CandFIG. 7Dsimultaneously, a first etching step may be performed, during which portions of the semiconductor die1110are removed to form a first portion5601of the microstructures560. A pattern of the first portion5601of the microstructures560may follow the pattern of the openings O3. In some embodiments, during the etching step the portions of the auxiliary mask M3exposed by the openings O5of the auxiliary mask M4are removed to form openings O6within the auxiliary mask M3. In some embodiments, the openings O6expose the top surfaces1120t,1130tof the semiconductor dies1120,1130. As shown inFIG. 7D, the auxiliary mask M4may be removed, thus exposing the auxiliary mask M3. Referring toFIG. 7E, in some embodiments, a second etching step may be performed. During the second etching step, material may be removed from the portions of the semiconductor dies1110,1120,1130exposed by the auxiliary mask M3. During the second etching step, the recesses previously formed in the semiconductor die1110defining the first portions5601of the microstructures560are further deepened. In some embodiments, a second portion5602of the microstructures560may be formed in the semiconductor dies1120,1130during the second etching step. In some embodiments, the first portion5601of the microstructures560are produced during one more etching step than the second portion5602of the microstructures560, resulting in a height difference between the microstructures560of the first portion5601and the second portion5602. In some embodiments, the microstructures560formed in the semiconductor die1110are somewhat taller than the microstructures560formed in the semiconductor dies1120,1130. In some embodiments, the number of etching steps performed for each semiconductor die1110,1120or1130is adjusted according to the thickness of the semiconductor die1110,1120or1130and the desired height of the microstructures560. For example, if the semiconductor die1110,1120or1130includes stacked chips, as is the case in some memory cubes, the etching depth may be shallower than the etching depth attainable for other semiconductor systems (e.g., systems on chip).

In some embodiments, as shown inFIG. 7F, the auxiliary mask M3is removed, and the metallization layer320is conformally formed over the exposed surface of the reconstructed wafer RW. As shown inFIG. 7F, a profile of the metallization layer320over the semiconductor dies1110,1120,1130may be defined by the microstructures560formed in the semiconductor dies1110,1120,1130. In some embodiments, the distance between adjacent microstructures560is such that the metallization layer320does not completely fill the interstices in between the microstructures560. In some alternative embodiments, the metallization layer320may be omitted, and the microstructures560may be coated with a highly thermally conductive material (e.g., graphene). Referring toFIG. 7G, the reconstructed wafer RW may be overturned over a supporting frame SF1, the temporary carrier TC2(shown inFIG. 7F) and the protective layer PL (shown inFIG. 7F) may be removed, and a singulation step may be performed along the scribe lines SC to form individual semiconductor packages100E. Steps similar to the ones discussed previously for the semiconductor devices SD1to SD5may result in the semiconductor device SD6shown inFIG. 7H. Namely, the semiconductor package100E may be connected to a substrate200(shown inFIG. 7H) and a heat dissipation system500E (shown inFIG. 7H) may be attached over the semiconductor package100E.

FIG. 7His a schematic cross-sectional view illustrating a semiconductor device SD6connected to a circuit substrate600and a fluid circulation system according to some embodiments of the disclosure. In the semiconductor device SD6, the cover510E of the heat dissipation system500E includes a cap512E and microstructures516E protruding from the cap512E towards the semiconductor package100E. In some embodiments, the cap512E is directly secured on the semiconductor package100E via a bonding material450, and forms, together with the semiconductor package100E, a circulation recess R1into which the inflow and outflow channels CH of the cap512E open. In some embodiments, the bonding material430performs the two functions of securing the cap512E to the semiconductor package100E and sealing the circulation recess R1as the seal. In some embodiments, when the cover510E is assembled over the semiconductor package100E, the microstructures516E of the cover510E may be disposed within the interstices defined by the microstructures560of the semiconductor package100E. In some embodiments, portions of the cover510E and the underlying portions of the semiconductor package100E may have almost complementary profiles, so that the respective microstructures516E and560may produce interleaved patterns that articulate the flow of the coolant CL through the circulation recess R1.

FIG. 8AthroughFIG. 8Dare schematic top views of portions of the circulation recess R1of the semiconductor devices SD6according to some embodiments of the disclosure, illustrating non-limiting examples of the flow of the coolant CL (shown inFIG. 7H) through the circulation recess R1. The views of theFIG. 8AthroughFIG. 8Dmay correspond to portions of the circulation recess R1formed over any one of the semiconductor dies1110,1120, and1130. Only for convenience of illustration, inFIG. 8AthroughFIG. 8Dit is assumed that the coolant proceeds from the right side of the drawing towards the left end of the drawing (along the direction x1).

Referring toFIG. 7HandFIG. 8A, in some embodiments fins562and pillars564are formed on the semiconductor dies1110,1120, or1130as microstructures560, and fins517are present as microstructures516E on the cover510E. In some embodiments, the pillars564are aligned in columns. In some embodiments, the pillars are further aligned along rows (in a direction perpendicular to the columns). In some embodiments, the fins562reach only up to a certain height of the circulation recess R1but do not make contact with the cap512E. In some embodiments, the fins562extend continuously within the circulation recess R1along a given direction, forming micro-chambers (not shown) within the circulation recess R1that are in fluid communication through the space on top of the fins562. In some embodiments, the fins562extend parallel to each other along a second direction y1tilted with respect to the direction of the incident flow of the coolant CL. In some embodiments, the direction y1is perpendicular to the direction x1. Similarly, in some embodiments, the fins517protrude towards the semiconductor package100E without making contact with the semiconductor package100E. In some embodiments, the fins517may extend parallel to the fins562along the direction y1. In some embodiments, an extending direction of the fins517is tilted with respect to an extending direction of the fins562.

In some embodiments, as shown inFIG. 8A, a fin517of the cover510E extending along the direction y1may be disposed in between a first column of pillars564and an adjacent second column of pillars564, and a fin562of the semiconductor package100E may be further interposed between the second column of pillars564and a subsequent third column of pillars564. That is, the fins562of the semiconductor package100E and the fins517of the cover510E may be alternately disposed in between consecutive columns of pillars564of the semiconductor package100E. When the circulation recess is structured in such a manner, the flow of the coolant CL may be deviated by the columns of pillars564(arrows F1inFIG. 8A) and forced to pass below the fins517(arrows F2inFIG. 8A) and above the fins562(arrows F3inFIG. 8A).

In some embodiments, as shown inFIG. 8B, pillars564but no fins562(shown inFIG. 8A) are formed on the semiconductor package100E. In some embodiments, as shown inFIG. 8C, fins562but no pillars564(shown inFIG. 8A) are formed on the semiconductor package100E. In some embodiments, multiple columns of pillars564of the semiconductor package100E are disposed in between adjacent fins517of the cover510E. In some embodiments, the number of columns of pillars564disposed in between adjacent fins517varies throughout the circulation recess R1. In some embodiments, fins517of the cover510E are disposed in between adjacent fins562of the semiconductor package100E. In some alternative embodiments, as shown inFIG. 8C, multiple fins562of the semiconductor package100E are disposed in between adjacent fins517of the cover510E. In some embodiments (not shown), multiple fins517of the cover510E are disposed in between adjacent fins562of the semiconductor package100E. In some embodiments, the fins517and562are parallel fins extending transversely with respect to the flowing direction x1. In some embodiments, as shown inFIG. 8D, only pillars518and564are formed on the cover510E and the semiconductor package100E, respectively, but no fins. In some embodiments, the pillars564and the pillars518are aligned along columns extending in the direction y1, with columns of pillars564alternating with columns of pillars518.

FIG. 9AthroughFIG. 9Dare schematic cross-sectional views illustrating intermediate structures formed at various stages of a manufacturing method of a semiconductor device SD7(shown integrated in an electronic device inFIG. 9E) according to some embodiments of the present disclosure. In some embodiments, referring toFIG. 9A, a semiconductor wafer1100is provided having multiple semiconductor dies1110formed therein. The semiconductor dies1110may include active or passive components, and may be produced within the semiconductor wafer1100according to known die manufacturing techniques. In some embodiments, the connectors1117of the semiconductor dies1110may be embedded in a protective layer PL, and the semiconductor wafer1100may be disposed on a temporary carrier TC3. Optionally, a de-bonding layer DB may be disposed between the temporary carrier TC3and the protective layer. An auxiliary mask M5may be formed on a top surface1100tof the semiconductor wafer1100exposed by the temporary carrier TC3. The auxiliary mask M5may include a plurality of openings O7that expose portions of the top surface1100tfor each semiconductor die1110. Referring toFIG. 9AandFIG. 9B, in some embodiments, an etching step is performed to form the microstructures560according to the pattern of the openings O7of the auxiliary mask M5. In some embodiments, if the microstructures560includes fins, micro-trenches are formed in between adjacent fins. In some embodiments, the auxiliary mask M5is removed, and a metallization layer330is formed over the top surface1100tof the semiconductor wafer1100. In some embodiments, a filling material1200is disposed to fill the interstices of the microstructures560. In some embodiments, the filling material1200protects or stabilizes the microstructures560during subsequent steps of the process. Referring toFIG. 9C, the semiconductor wafer1100may be overturned on a support frame SF2, and a singulation step may be performed to produce individual semiconductor dies1100. In some embodiments, the semiconductor dies1120and1130including the microstructures560are produced following a similar process to the one just described for the semiconductor die1110, and a detailed description thereof is omitted for the sake of brevity. In some embodiments, semiconductor dies1110,1120,1130having microstructures560formed on the corresponding upper surfaces are used to produce a semiconductor package100F (shown inFIG. 9D). In some embodiments, the semiconductor package100F is formed following similar steps to the ones previously discussed with reference toFIG. 1AtoFIG. 1D. In some embodiments, if a planarization step is performed to form the encapsulant160(shown inFIG. 1B), portions of the semiconductor dies1110,1120,1130are removed. However, in such cases the planarization step is performed so as to still preserve a morphology of the microstructures560formed on the semiconductor dies1110,1120,1130(e.g., to maintain a certain height difference between the pillars564and the fins562shown inFIG. 11B). In some embodiments, the semiconductor package100F is bonded to the semiconductor substrate200(shown inFIG. 9D), and, following process steps similar to what was previously discussed for the semiconductor devices SD1to SD6, a semiconductor device SD7(shown inFIG. 9E) is formed.

FIG. 9Eis a schematic cross-sectional view illustrating an electronic device according to some embodiments of the disclosure. In the electronic device ofFIG. 9E, the semiconductor device SD7is connected to a circuit substrate600and a fluid circulation system according to some embodiments of the disclosure.FIG. 10is a schematic top view of the semiconductor device SD7according to some embodiments of the disclosure.FIG. 11AandFIG. 11Bare schematic cross-sectional views of portions of a semiconductor device SD7corresponding to the area B ofFIG. 9Eaccording to some embodiments of the disclosure. Referring simultaneously toFIG. 9E,FIG. 10andFIG. 11A, in some embodiments, the cover510F includes the cap512F disposed over the semiconductor package100F. In some embodiments, the cap512F is directly secured on the semiconductor package100F via a bonding material460and forms, together with the semiconductor package100E, a circulation recess R1including a system of circulation channels CCH1, CCH2. In some embodiments, the bonding material460is disposed between the outer edge of the cover510F and the outer edge of the semiconductor package100F. In some embodiments, the bonding material460is also disposed at a few points within the circulation recess R1in which the cover510F contacts the semiconductor package100F in between the semiconductor dies1110,1120,1130. In some embodiments, portions of the cap512F within the circulation recess R1directly contact the semiconductor packages1110,1120,1130or the metallization layer330formed thereon. Those portions of the cap512F may contact the microstructures560formed in the semiconductor dies1110,1120,1130, resulting in circulation chambers (portions of which are shown inFIG. 11AandFIG. 11B) on the upper surface of each semiconductor die1110,1120,1130. In some embodiments, each circulation chamber extends over a single semiconductor die1110,1120,1130, and has one inlet IN and one outlet OUT formed by the circulation channels CCH1and CCH2. Each circulation chamber may be delimited by the upper surface of the underlying semiconductor die1110,1120,1130(acting as floor and walls of the chamber) and a portion of the cover510F (acting as a roof) lying over the microstructures560. The microstructures560are disposed within the circulation chamber to articulate the flow of the coolant CL on top of the semiconductor dies1110,1120,1130.

In some embodiments, the cover510F includes circulation channels CCH1, CCH2, each one of which is connected with the inflow channel CH1or the outflow channel CH2from which the coolant CL enters and leave the semiconductor device SD7. In some embodiments, a single circulation channel CCH1or CCH2is connected with only one inflow channel CH1or outflow channel CH2. In some alternative embodiments, multiple inflow channels CH1converge within the same inflow circulation channel CCH1. In some embodiments, the outflow circulation channel CCH2may branch out towards multiple outflow channels CH2. In some embodiments, the circulation channels CCH1, CCH2run in a parallel fashion through the cover512F over the semiconductor dies1110,1120,1130, in a direction substantially perpendicular with respect to the inflow channel CH1and outflow channel CH2. In some embodiments, as shown inFIG. 10, the inflow circulation channel CCH1presents branching points in correspondence of each semiconductor die1110,1120,1130. Each branching point of the inflow circulation channel CCH1may form one of the inlets IN through which the coolant CL enters one of the circulation chambers of the semiconductor dies1110,1120,1130. Similarly, the outflow circulation channel CCH2may present branching points in correspondence of each semiconductor die1110,1120,1130, and these branching points may act as one of the outlets OUT through which the coolant CL leaves one of the circulation chambers of the semiconductor dies1110,1120,1130. In some embodiments, the inlets IN, the outlets OUT and the circulation chambers are structured in such a way that the coolant CL contacts most of the upper surface of a semiconductor die1110,1120, or1130. In some embodiments, as shown inFIG. 10, a given amount of coolant CL flows only within one of the circulation chambers. For example, referring toFIG. 10, the circulation recess R1within the cover510F may be designed in such a way that the coolant CL that leaves the circulation chamber on the semiconductor die1130may flow out of the outflow channel CH2without entering other circulation chambers (e.g., the ones on top of semiconductor dies1110, or1120). In the embodiments shown inFIG. 10, only one circulation chamber is formed over each semiconductor die1110,1120,1130, but the disclosure is not limited thereto. In some embodiments, the cover510F and the microstructures560may be designed so that multiple circulation chambers are formed over the same semiconductor die1110,1120,1130. In some embodiments, the inflow channel CH1, the inflow circulation channel CCH1and the inlets IN are vertically aligned, rather than distributed as shown inFIG. 10.

It should be noted the cross-sectional view ofFIG. 9Eshows features of the cover510F that would not be observable along a single cross-section of the structure shown inFIG. 10. For example, the inflow channel CH1, the outflow channel CH2, the inflow circulation channel CH1, the inlets IN and the outlets OUT would not appear in a single cross-section of the structure shown inFIG. 10. These elements are simultaneously shown inFIG. 9Eto provide a general idea of different structural aspects of the cover510F, rather than faithfully present the fluid circulation in the semiconductor device SD7.

FIG. 11AandFIG. 11Bshow cross-sectional views of a portion of a circulation chamber formed over the semiconductor device1110according to some embodiments of the disclosure. In the embodiments illustrated inFIG. 11A, only pillars564are formed as microstructures560on the semiconductor die1110, extending until physically contacting the cover512F. In the embodiments illustrated inFIG. 11B, pillars564and fins562are formed on the semiconductor die1100, and pillars518are formed on the cover512F. In one embodiment, the pillars564and fins562are patterned from the semiconductor die1100and are made of the same semiconductor material of the semiconductor die1100. In some embodiments, the pillars564may be taller and contact the cover512F, whilst the fins562may be shorter (in the thickness direction) than the pillars564, thus allowing the coolant CL (shown inFIG. 9E) to flow above. Similarly, the pillars518formed on the cover may not reach the semiconductor die1110, thus allowing the coolant CL to flow below.

FIG. 12Ashows a schematic cross-sectional view of an electronic device according to some embodiments of the disclosure. In the electronic device ofFIG. 12A, the semiconductor device SD8is connected to a fluid circulation system and to a circuit substrate600.FIG. 12Bshows a schematic top view of the semiconductor device SD8according to some embodiments of the present disclosure. Referring simultaneously toFIG. 12AandFIG. 12B, in some embodiments, the semiconductor device SD8includes a wafer-size semiconductor package100G and a wafer-size heat dissipation system500G. In some embodiments, the wafer-size semiconductor package100G has a diameter of about 4 inches or more. For example, the wafer-size semiconductor package100G may have a diameter of about 6 inches. In some cases, the wafer-size semiconductor package100G may have a diameter of about 8 inches. In some cases, the wafer-size semiconductor package100G may have a diameter of about 12 inches. The semiconductor package100G may include a reconstructed wafer structure, in which a plurality of semiconductor dies110is encapsulated in a wafer form and is interconnected through the redistribution structure144. InFIG. 12Bare shown the footprints of the semiconductor die110of the semiconductor package100G with respect to the cover510G. The wafer-size semiconductor package100G may be formed by encapsulating the semiconductor dies110with a molding compound, and forming the redistribution structure144on the active surfaces of the semiconductor dies110. In some embodiments, additional components (e.g., TIVs, dummy dies or passive devices, etc.) may be included in the wafer-size semiconductor package100G according to design requirements. In some embodiments, the wafer-size semiconductor package100G may have a substantially circular footprint. In some embodiments, each semiconductor die110included in the wafer-size package100G may independently be or include a logic die, such as a central processing unit (CPU) die, a graphic processing unit (GPU) die, a micro control unit (MCU) die, an input-output (I/O) die, a baseband (BB) die, or an application processor (AP) die. In some embodiments, one or more of the semiconductor dies110include a memory die such as a high bandwidth memory die, a memory chip stack, or the like. In some embodiments, the semiconductor dies110may be the same type of dies or perform the same functions. In some embodiments, the semiconductor dies110may be different types of dies or perform different functions. In some embodiments, the backside surfaces of the semiconductor dies110may be covered by the metallization layer310. In some embodiments, the metallization layer310may extend on the wafer-size semiconductor package110, and be disposed between the wafer-size package100G and the wafer-size heat dissipation system500G.

In some embodiments, the heat dissipation system500G includes the cover510G and microstructures550secured to the cover510G and to the semiconductor package100G. In some embodiments, the cover510G includes the cap portion512G and the flange portion514G. The flange portion514G may be located at the periphery of the cap portion512G and fall on the wafer-size semiconductor package100G (or the metallization layer310if included). In some embodiments, the footprint of the cover510G may be smaller than the footprint of the wafer-size package100G, and a peripheral portion of the package100G or the metallization layer310may be left exposed by the cover. In some alternative embodiments (not shown), edges of the wafer-size semiconductor package100G and edges of the cover510G may be aligned, and the cover510G may substantially hide the semiconductor package100G when viewed from the top. In some embodiments, the flange portion514G falls along an outer rim of the semiconductor package100G. In some embodiments, the flange portion514G contacts the semiconductor package100G or the metallization layer310over the molding compound rather than the semiconductor dies110.

In some embodiments, the wafer-size cover510G and the wafer-size package100G define the wafer-sized circulation recess R1. The cover510G includes inflow/outflow channels CH opening in the circulation recess R1, to allow flow of the coolant CL through the circulation recess R1. In some embodiments, the inflow/outflow channels CH opens over some of the semiconductor dies110. In some embodiments, there are more semiconductor dies110in the semiconductor package100G than inflow/outflow channels CH in the cover510G. In some embodiments, the number of inflow/outflow channels CH with respect to the number of semiconductor dies110may be adjusted according to design requirements.

In some embodiments, the microstructures550are disposed in the size circulation recess R1in such a manner to articulate the flow of the coolant CL through the circulation recess R1. In some embodiments, the wafer-sized circulation recess R1extends over the semiconductor dies110included in the wafer-size semiconductor package100G. In some embodiments, the circulation recess R1extends over all the semiconductor dies110included in the wafer-size semiconductor package100G. In some embodiments, the microstructures550are secured to the wafer-size semiconductor package100G (or the metallization layer310) via the bonding material420and to the cover510G via the bonding material440. In some embodiments, the microstructures550are located also in correspondence of the inflow/outflow channels CH, being secured by portions of the bonding material420. However, the disclosure is not limited thereto. In some embodiments, the other types of microstructures discussed before in the present disclosure may be used with the wafer-size semiconductor package100G.

In some embodiments, the wafer-size semiconductor package100G is bonded to a wafer-size substrate202, with backside surfaces of the semiconductor dies110facing away from the wafer-size substrate202. An underfill179may protect the connection between the wafer-size package100G and the wafer-size substrate202. In some embodiments, the wafer-size substrate202is bonded to a circuit substrate600through connectors610. In some embodiments, the wafer-size substrate202is optional, and the wafer-size package100G may be directly bonded to the circuit substrate600.

FIG. 12Cshows a schematic top-view of a semiconductor device SD9according to some embodiments of the disclosure. The semiconductor device SD9may include a panel-size semiconductor package100H and a cover510H forming a heat dissipation system. In some embodiments, the panel-size semiconductor package100H may have a polygonal shape (e.g., rectangular, square, pentagonal, hexagonal, etc.). The panel size semiconductor package100H may include multiple groups of semiconductor dies110A-110E, the footprints of which with respect to the cover510H are shown inFIG. 12C. In some embodiments, each group of semiconductor dies110A-110E may constitute a functional unit within the panel-size semiconductor package100H. Each functional unit of the panel-size semiconductor package100H may perform different functions, and include different types of semiconductor dies100A-100E independently from the other functional units. Inflow/outflow channels CH open in the cover510H to allow flow of a coolant in the circulation recess (not shown) formed between the cover510H and the panel-size semiconductor package100H. In some embodiments, an inflow/outflow channel CH may extend over multiple semiconductor dies100A-100E of a functional unit, or even span over semiconductor dies100A-100E belonging to different functional units. In some embodiments, the panel-size semiconductor package100H may be 300 mm×300 mm or larger.

In some embodiments, semiconductor packages like the wafer-size semiconductor package100G or the panel-size semiconductor package100H are referred to as large-scale semiconductor packages.

The heat dissipation system disclosed herein is rather versatile, and may be applied to different types of semiconductor packages with only minor adjustments. Furthermore, features of the specific embodiments illustrated above may be combined in multiple ways, and all these ways are meant to fall within the scope of the present disclosure and the attached claims. As a non-limiting example, in some embodiments of the disclosure the microstructures connected to the cover may be integrally formed with the cover. According to some other embodiments of the disclosure, the microstructures may be prefabricated and secured to the cover or the semiconductor package. All of the microstructures disclosed herein may be coated with a thermally conductive material (e.g., graphene) according to different embodiments of the disclosure. Also, according to some embodiments the covers that were illustrated without flanges may also include flanges. In some embodiments, the flanges may fall on the semiconductor package. In some alternative embodiments, the flanges may fall on the substrate. According to some embodiments, all the covers may be secured to the substrate via a support.

Based on the above, a semiconductor device according to the present disclosure may include a semiconductor package and a cap disposed on the semiconductor package. In some embodiments, the heat dissipation system allows flow of a coolant directly in contact with the semiconductor package, without any thermal interface material disposed in between. In some embodiments, the direct contact of the coolant with the semiconductor package ensures efficient thermal exchange, providing a cooling effect for the semiconductor package. In some embodiments, the cover and the semiconductor package define a circulation recess through which the coolant flows. Microstructures disposed within the circulation recess may articulate the flow of the coolant. In some embodiments, the microstructures may be coated with a thermally conductive material to further promote thermal exchange between the semiconductor package and the coolant.

In some embodiments of the present disclosure, a semiconductor device is provided. The semiconductor package includes a semiconductor package, a cap, a seal, and microstructures. The semiconductor package includes at least one semiconductor die. The cap is disposed over an upper surface of the semiconductor package. The seal is located on the semiconductor package and between the cap and the semiconductor package. The cap includes an inflow channel and an outflow channel. The active surface of the at least one semiconductor die faces away from the cap. The cap and an upper surface of the semiconductor package define a circulation recess providing fluidic communication between the inflow channel and the outflow channel. The seal is disposed around the circulation recess. The microstructures are located within the circulation recess, and the microstructures are connected to at least one of the cap and the at least one semiconductor die.

In some embodiments of the present disclosure, a semiconductor device is provided. The semiconductor device includes a semiconductor package, a cap and microstructures. The semiconductor package includes a first die and a second die electrically connected with each other. The cap is disposed on the semiconductor package and includes an inflow hole and an outflow hole. A circulation recess defined between the cap and the semiconductor package and communicating with the inflow hole and the outflow hole provides a fluidic path. The microstructures are disposed within the circulation recess and on the fluidic path. The microstructures include semiconductor microstructures protruded from back surfaces of the first and second semiconductor dies.

In some embodiments of the present disclosure, a manufacturing method of a semiconductor device is provided. The manufacturing method includes the following steps. A semiconductor package including laterally-encapsulated semiconductor dies is provided. Microstructures are formed by etching backside surfaces of the semiconductor dies. The semiconductor dies are connected to a substrate, so that active surfaces of the dies face the substrate. A bonding material is disposed on an upper surface of the semiconductor package. The upper surface of the semiconductor package is further away from the substrate. A cover is secured to the upper surface of the semiconductor package via the bonding material to define a circulation recess between the cover and the backside surfaces of the semiconductor dies. Microstructures are disposed within the circulation recess. The cover comprises an inflow channel and an outflow channel. The circulation recess establishes fluidic communication between the inflow channel and the outflow channel.