Memory including bipolar junction transistor select devices

An array is formed by a plurality of cells, wherein each cell is formed by a bipolar junction selection transistor having a first, a second, and a control region. The cell includes a common region, forming the second regions of the selection transistors, and a plurality of shared control regions overlying the common region. Each shared control region forms the control regions of a plurality of adjacent selection transistors and accommodates the first regions of the plurality of adjacent selection transistors as well as contact portions of the shared control region. Blocks of adjacent selection transistors of the plurality of selection transistors share a contact portion and the first regions of a block of adjacent selection transistors are arranged along the shared control region between two contact portions. A plurality of biasing structures are formed between pairs of first regions of adjacent selection transistors, for modifying a charge distribution in the shared control region below the biasing structures.

BACKGROUND

This relates to a memory including bipolar junction transistor select devices.

Phase change memories are formed by memory cells connected at the intersections of bitlines and wordlines and comprising each a memory element and a selection element.

Each memory element comprises a phase change region made of a phase change material, i.e., a material that may be electrically switched between a generally amorphous and a generally crystalline state across the entire spectrum between completely amorphous and completely crystalline states. Typical materials suitable for such an application include various chalcogenide elements. The state of the phase change materials is non-volatile, absent application of excess temperatures, such as those in excess of 150° C. for extended times. When the memory is set in either a crystalline, semi-crystalline, amorphous, or semi-amorphous state representing a resistance value, that value is retained until reprogrammed, even if power is removed. This is because the programmed value represents a phase or physical state of the material (e.g., crystalline or amorphous).

Select devices, access devices, or select elements may be formed according to different technologies, for example they can be implemented by diodes, by MOS transistors or bipolar transistors.

The collector region of a bipolar select device is formed by a buried, shared region of the substrate, overlaid by a shared base region. An emitter region and a base contact region are formed in the base region for each memory cell. Each emitter region is then connected to an own memory element, in turn connected to a bitline. The base contact is connected to a wordline through plugs extending in an insulating layer overlying the substrate. The memory cells that are adjacent in the direction of the rows of the memory array are connected to a same wordline. The memory cells that are adjacent in the direction of the columns of the memory array are connected to a same bitline.

DETAILED DESCRIPTION

FIGS. 1-4show an embodiment of the invention wherein a polysilicon region is formed between adjacent emitter regions of a bipolar junction select device to bias the underlying shared base region and thus reduce the resistance of the shared base region during programming and reading.

An array1of memory cells2is formed in a body10of monocrystalline semiconductor material including a heavily doped P-type substrate6, a P-type subcollector region7, a P-type common collector region11having a lower doping level than the subcollector region7, and shared N-type base regions12.

The subcollector region7extends above the substrate6in an epitaxial layer which also accommodates the common collector region11, and the shared base regions12. The shared base regions12are formed in active areas of the array1, delimited and electrically insulated from each other by field oxide regions13(FIGS. 3 and 4). Thus, the shared base regions12are strip-shaped and extend parallel to each other along a first direction (X-direction).

Each base region12accommodates a plurality of P+-type emitter regions14grouped in clusters or blocks of N adjacent emitter regions14(e.g., of eight or sixteen emitter regions14) in one embodiment. An N+-type base contact region15is accommodated in the base region12of each block of emitter regions14. An emitter region14, together with the respective base region12, the common collector region11and the base contact15of the block, forms a bipolar PNP select transistor50. Thus, the select transistors50comprising emitter regions14of a same block are arranged adjacent to each other in the row or x direction and share the same base contact15.

Silicide regions16may be formed on the emitter regions14and on the base contact regions15, to reduce resistivity.

Biasing structures20are formed on top of the body10, between adjacent emitter regions14as well as between the emitter regions14and the base contact15. Each biasing structure20may include a gate oxide strip30, a polysilicon strip31on the gate oxide strip30, a silicide strip32on the polysilicon strip31, and spacers33on the sides of the polysilicon strip31. The spacers33are formed (e.g., of nitride) and the polysilicon strips31are biased through a contact38, shown schematically inFIG. 2.

A dielectric region21extends over the body10and the biasing structures20. The dielectric region21may be formed by subsequently deposited layers to form the various regions therein and to include different materials.

First and second contacts22,23extend through the dielectric region21. The contacts22,23may be tungsten, covered laterally and on bottom with a barrier material (for example, Ti/TiN) (not shown).

The first contacts22extend each from an emitter region14to a storage element24, of chalcogenic material. First metal lines25, forming bit lines, extend along a second direction (Y-direction), thus transversely to the base regions12(active area strips). Each first metal line25is in contact with the storage elements24that are aligned in the Y direction, as shown inFIG. 3. The first metal lines25may be formed in a first metal level.

The second contacts23are higher than the first contacts22and extend each from a base contact region15to second metal lines26. The second metal lines26, forming word lines, extend along the first direction (X-direction), parallel to the base regions12and perpendicular to the first metal lines25. Each second metal line26is in contact with the second contacts23that are aligned in the X direction, as shown inFIG. 2. The second metal lines26may be formed in a second metal level.

Thus, each selection transistor50has its emitter region14connected to a storage element24to form a memory cell2which can be selected by biasing the first metal line25and the second metal line26connected thereto. Here, the resulting cell size may be determined substantially by the emitter region14and the respective polysilicon strip31(6F2, where F is the minimum geometry that defines the memory cell to be formed) plus the size of the shared base contact15(6F2/N). With the number of emitter regions14per block, (N), sufficiently large (e.g., eight or sixteen), the shared base contact15area may be negligible.

To manufacture the array1ofFIGS. 1-4, in one embodiment, first the field oxide regions13are formed in the semiconductor body10. Then subcollector region7, the common collector region11, and the base regions12are implanted in sequence.

Thereafter, a gate oxide layer and a polysilicon layer are deposited and defined, to form the gate oxide strips30and the polysilicon strips31, extending perpendicularly to the field oxide regions13. Then, the spacers33are formed and the emitter regions14and the base contact regions15are implanted using respective masks. In particular, the emitter mask (indicated by dash-and-dot lines55inFIG. 1) includes a plurality of elongated windows extending parallel to and between pairs of adjacent gate strips to implant blocks of emitter regions14at every Nth (e.g. eight) adjacent emitter window, no emitter implant is carried out, and instead the base contact regions15are implanted (base contact mask56inFIG. 1). Thereafter, silicide regions16,33are formed.

Then, the body10is covered by a first layer of insulating material, forming the bottom portion of the dielectric region21. Vias are formed in the first layer of insulting material. The vias are filled with a barrier layer (e.g., Ti/TiN), and with tungsten.

The process continues by forming the chalcogenic storage elements24, the first metal lines25, the upper portion of the dielectric region21, the upper portion of the second contacts23and the second metal lines26to obtain the structure shown inFIGS. 2-4.

In use, when a selection transistor50is selected for programming or reading the associated storage element24, the associated bitline (first metal line25) and the associated wordline (second metal line26) are biased. To reduce the base resistance, the polysilicon strips31of the same block are biased with a positive voltage to accumulate negative charge on the portion of the base region12below the polysilicon strips31. Thus, the resistance along the base region12between the selected base contact15and the selected emitter region14is reduced.

Thereby, the selected selection transistor50switches on without increasing the voltage drop along the base region12, in some embodiments. For example, for programming, the selected bitline may be grounded. The non-selected bitlines are biased to a low positive voltage (e.g., 0.2-0.3 V), the selected wordline is biased at Vcc (or the maximum voltage in the end device, e.g., 3 V), and the polysilicon strip31is biased at a supply voltage Vcc. For reading, the bitline25is biased at Vcc, the wordline26is grounded and polysilicon strip31is biased at Vcc.

FIGS. 5-8show embodiments wherein the polysilicon strips31are generally parallel to the base regions12. Therefore, the polysilicon strips may operate as MOS transistors during reading to deplete the portions of the base region12between adjacent emitter regions14as far as the selected selection transistor. To this end, as shown inFIG. 6, two P+ type biasing regions40are formed on the two sides of each base contact region15. The biasing regions40are connected to their own biasing line41extending parallel to the respective wordline26(shown inFIG. 6below the wordline26only for illustrative purpose) and connected through third contact lines42of suitable shape (for example, including an intermediate connecting portion formed in the first metal level).

In particular, inFIG. 5, the polysilicon strips31have a zigzag pattern around the first contacts22. Here, the emitter mask55is used to also form the biasing regions40and the base contact mask56has a window contiguous to the windows of the emitter mask55where the biasing regions40are to be formed. With this configuration, the cell size is 12F2.

InFIG. 7, each polysilicon strip31includes a rectilinear portion36and protruding fingers37. Pairs of polysilicon strips31have adjacent rectilinear portions36, arranged back-to-back, with the respective fingers37protruding in opposite directions to intersect the active areas (base regions12). Each pair of polysilicon strips31is laterally offset with respect to the adjacent pairs and every N fingers37(e.g., every eight or sixteen fingers), one finger is missing to allow arrangement of the base contact regions15, the biasing region40and the respective contacts23and42. With this configuration, the cell size is 12F2.

InFIG. 8, each polysilicon strip31comprise a rectilinear portion36with protruding fingers37. Here, the protruding fingers are formed on each side of the rectilinear portion36, with the fingers37on one side of a rectilinear portion being offset with respect to the fingers on the other side of the same rectilinear portion36by half pitch. Analogously, the facing fingers37of two adjacent polysilicon strip31are offset by half pitch. Also here, every N fingers37, one is missing to allow arrangement of the base contact regions15and the respective second contacts23. With this configuration, the cell size is 10F2.

With the embodiments ofFIGS. 5-8, during programming, a cell2is selected by suitably biasing a bitline25and a wordline26, thereby biasing the transistor50having emitter region14and base contact region connected thereto, through the respective first and second contacts22,23. Furthermore, the polysilicon strip31of the group of transistors50sharing the same base contact region15with the addressed transistor50are positively biased, to obtain the accumulation of negative charges in the underlying portion of the base region12. Thus, the resistance of the base region12is reduced.

During reading, the polysilicon strips are biased to cause them to operate as gates of standard PMOS transistors. Furthermore, the biasing region40of the same block as the addressed cell2is biased through the biasing line41operating here as a wordline. In such a situation, the biasing region40operates as a source and forms, together with the adjacent portion of the polysilicon strip and the adjacent emitter region14, a MOS transistor. Analogously, the emitter regions14along the same polysilicon strip31form a plurality of series-connected MOS transistors. The biasing of the polysilicon strip31associated with the addressed cell2with a negative voltage cause all the series-connected MOS transistors to switch on and the portion of the base region12underlying the polysilicon strip31to form a plurality of P channels, connecting the addressed biasing region40to all the emitter regions14of the same group of cells2. Thereby, a low-resistance path forms between the emitter region14of selected cell2(now acting as a drain region) and the addressed biasing region40, thus reducing the voltage drop. Therefore, the memory including the array1does not require the use of charge-pumps to boost the voltage, in some embodiments, thus, reducing the power consumption and improving the reading parallelism and the read throughput, still preserving the driving capabilities of the bipolar transistors50for programming.

Such solution, of course, uses a decoding circuit connected to the biasing lines41, which replaces the wordlines25during reading.

Turning toFIG. 9, a portion of a system500in accordance with an embodiment of the present invention is described. System500may be used in wireless devices such as, for example, a personal digital assistant (PDA), a laptop or portable computer with wireless capability, a web tablet, a wireless telephone, a pager, an instant messaging device, a digital music player, a digital camera, or other devices that may be adapted to transmit and/or receive information wirelessly. System500may be used in any of the following systems: a wireless local area network (WLAN) system, a wireless personal area network (WPAN) system, a cellular network, although the scope of the present invention is not limited in this respect.

System500includes a controller510, an input/output (I/O) device520(e.g. a keypad, display), static random access memory (SRAM)560, a memory530, and a wireless interface540coupled to each other via a bus550. A battery580is used in some embodiments. It should be noted that the scope of the present invention is not limited to embodiments having any or all of these components.

Controller510comprises, for example, one or more microprocessors, digital signal processors, micro-controllers, or the like. Memory530may be used to store messages transmitted to or by system500. Memory530may also optionally be used to store instructions that are executed by controller510during the operation of system500, and may be used to store user data. Memory530may be provided by one or more different types of memory. For example, memory530may comprise any type of random access memory, a volatile memory, a non-volatile memory such as a flash memory and/or a phase change memory including the memory array1discussed herein.

I/O device520may be used by a user to generate a message. System500uses wireless interface540to transmit and receive messages to and from a wireless communication network with a radio frequency (RF) signal. Examples of wireless interface540may include an antenna or a wireless transceiver, although the scope of the present invention is not limited in this respect.

The described embodiments may allow a reduction in the resistance along the base region12by virtue of the modified charge distribution caused by the biasing of the overlying biased polysilicon strips31. The polysilicon strips31are also useful as silicide protection regions. In the embodiments ofFIGS. 5-8, a compact hybrid selection structure may be obtained, which combines a MOSFET and a bipolar junction transistor.

Finally, it is clear that numerous variations and modifications may be made to the array and process described and illustrated herein, all falling within the scope of the invention as defined in the attached claims. For example, the same selection array may be used for selection of other storage elements, different from the chalcogenic storage elements24, or of other two- or three-terminal elements that are compatible with standard CMOS back-end processes.

Furthermore, although the base contact regions15have been indicated throughout the description and in the drawings as separate N+ type regions, more doped than the base region12, they can be absent, and the portion of the base regions12underlying the contact42form base contact portions. The term “base contact regions15” is thus intended to encompass both situations.