Compliant printed circuit semiconductor tester interface

A compliant printed circuit semiconductor tester interface that provides a temporary interconnect between terminals on integrated circuit (IC) devices being tested. The compliant printed circuit semiconductor tester interface includes at least one dielectric layer printed with recesses corresponding to a target circuit geometry. A conductive material is deposited in at least a portion of the recesses comprising a circuit geometry and a plurality of first contact pads accessible along a first surface of the compliant printed circuit. At least one dielectric covering layer is preferably applied over the circuit geometry. A plurality of openings in the dielectric covering layer are provided to permit electrical coupling of terminals on the IC device and the first contact pads. Testing electronics that to test electrical functions of the IC device are electrically coupled to the circuit geometry.

TECHNICAL FIELD

The present application relates to a high performance compliant printed circuit semiconductor tester interface that merges the long-term performance advantages of flexible circuits, with the flexibility of additive printing technology.

BACKGROUND OF THE INVENTION

Traditional printed circuits are often constructed in what is commonly called rigid or flexible formats. The rigid versions are used in nearly every electronic system, where the printed circuit board (PCB) is essentially a laminate of materials and circuits that when built is relatively stiff or rigid and cannot be bent significantly without damage.

Flexible circuits have become very popular in many applications where the ability to bend the circuit to connect one member of a system to another has some benefit. These flexible circuits are made in a very similar fashion as rigid PCB's, where layers of circuitry and dielectric materials are laminated. The main difference is the material set used for construction. Typical flexible circuits start with a polymer film that is clad, laminated, or deposited with copper. A photolithography image with the desired circuitry geometry is printed onto the copper, and the polymer film is etched to remove the unwanted copper. Flexible circuits are very commonly used in many electronic systems such as notebook computers, medical devices, displays, handheld devices, autos, aircraft and many others.

Flexible circuits are processed similar to that of rigid PCB's with a series of imaging, masking, drilling, via creation, plating, and trimming steps. The resulting circuit can be bent, without damaging the copper circuitry. Flexible circuits are solderable, and can have devices attached to provide some desired function. The materials used to make flexible circuits can be used in high frequency applications where the material set and design features can often provide better electrical performance than a comparable rigid circuit.

Flexible circuits are connected to electrical system in a variety of ways. In most cases, a portion of the circuitry is exposed to create a connection point. Once exposed, the circuitry can be connected to another circuit or component by soldering, conductive adhesive, thermosonic welding, pressure or a mechanical connector. In general, the terminals are located on an end of the flexible circuit, where edge traces are exposed or in some cases an area array of terminals are exposed. Often there is some sort of mechanical enhancement at or near the connection to prevent the joints from being disconnected during use or flexure. In general, flexible circuits are expensive compared to some rigid PCB products. Flexible circuits also have some limitations regarding layer count or feature registration, and are therefore generally only used for small or elongated applications.

Tester interface circuit boards are typically specialty versions of traditional rigid PCBs. Tester interface board are often very thick, with many layers required to provide the required connections to the tester.

One type of tester interface circuit board is a Device Under Test (DUT) or Load Board, which are typically fabricated to accept a test socket or contactor on the top surface, and have a series of land grid array pads on the under surface that mate with a field of spring probes that are mated with the tester electronics. For wafer probing applications, a similar scenario is established, where the tester interface PCB often includes a probe card assembly. In some probe applications, a space transformer is used to transition or redistribute the fine terminal pitch of the wafer probe to the larger pitch required for connection with the tester.

In general, tester interface circuits boards, space transformers, and probe cards can be very expensive compared to higher volume PCBs, and often have long lead times. In many cases, the tester interface circuit boards and probe cards are specific to a particular electrical device and cannot be used for testing other electrical devices.

BRIEF SUMMARY OF THE INVENTION

The present disclosure is directed to high performance tester interfaces made using additive printing technology. The nature of the additive printing process provides the potential for significant enhancement to traditional printed circuit techniques used to produce tester interfaces. In some embodiments, the present tester interface merges a test socket and/or probe function directly into the tester interface. Consequently, the entire tester interface is a consumable item with lower overall cost and less lead-time.

The additive printing processes enable printing of internal and/or external compliance to enhance the mechanical performance of the present compliant tester interface, as well as a host of electrical devices. Electrical devices are preferably printed on the tester interface, such as for example, ground planes, power planes, transistors, capacitors, resistors, RF antennae, shielding, filters, signal or power altering and enhancing devices, memory devices, embedded IC, and the like.

The present tester interface can be produced digitally, without tooling or costly artwork. The tester interface tester interface can be produced as a “Green” product, with dramatic reductions in environmental issues related to the production of conventional flexible circuits. By adding or arranging metallic particles, conductive inks, plating, or portions of traditional alloys, the present tester interface reduces parasitic electrical effects and impedance mismatch, potentially increasing the current carrying capacity.

The use of additive printing processes permits the material set in a given layer to vary. Traditional PCB and flex circuit fabrication methods take sheets of material and stack them up, laminate, and/or drill. The materials in each layer are limited to the materials in a particular sheet. Additive printing technologies permit a wide variety of materials to be applied on a layer with a registration relative to the features of the previous layer. Selective addition of conductive, non-conductive, or semi-conductive materials at precise locations to create a desired effect has the major advantages in tuning impedance or adding electrical function on a given layer. Tuning performance on a layer by layer basis relative to the previous layer greatly enhances electrical performance.

One embodiment is directed to a compliant printed circuit semiconductor tester interface that provides a temporary interconnect between terminals on integrated circuit (IC) devices being tested. The compliant printed circuit semiconductor tester interface includes at least one dielectric layer printed with recesses corresponding to a target circuit geometry. A conductive material is deposited in at least a portion of the recesses comprising a circuit geometry and a plurality of first contact pads accessible along a first surface. At least one dielectric covering layer is preferably applied over the circuit geometry. A plurality of openings in the dielectric covering layer are provided to permit electrical coupling of terminals on the IC device and the first contact pads. Testing electronics that to test electrical functions of the IC device are electrically coupled to the circuit geometry.

One or more compliant layers are optionally positioned to bias a plurality of the first contact pads against the terminals on the IC device. At least one electrical device can be located on the compliant printed circuit and electrically coupled to the circuit geometry. The electrical devices may include at least a portion of the testing electronics. In one embodiment, an electrical device is printed on one of the dielectric layers. The electrical device can be selected from one of shielding, near device decoupling, capacitors, transistors, resistors, filters, signal or power altering and enhancing devices, memory devices, embedded IC devices, RF antennae, and the like.

In another embodiment, a socket housing is coupled to the compliant printed circuit. The first contact pads are positioned in a socket housing recess sized to receive the IC device.

The conductive material can be one of sintered conductive particles or a conductive ink. In another embodiment, optical quality materials are deposited in at least a portion of the recesses to create one or more optical circuit geometries. One or more optical fibers can also be located in at least a portion of the recesses.

The first contact pads can optionally extend above the dielectric covering layer. The first contact pads can be probe members of a probe assembly. The compliant printed circuit can also be singulated adjacent at least one of the first contact pads.

The conductive traces in the circuit geometry are preferably substantially rectangular cross-sectional shapes. The printing technology permits a single layer to include conductive materials, non-conductive materials, and semi-conductive materials.

The compliant printed circuit can optionally extend beyond the dielectric covering layer to form an edge connector. At least one additional circuitry plane can be added to the compliant printed circuit. In another embodiment, a plurality of second contact pads accessible along a second surface of the compliant printed circuit are provided to electrically couple with the testing electronics.

The present disclosure is also directed to a method of making a compliant printed circuit semiconductor tester interface that provides a temporary interconnect between terminals on an integrated circuit (IC) device being tested. The method includes printing at least one dielectric layer with recesses corresponding to a target circuit geometry. A conductive material is printed in at least a portion of the recesses to create a circuit geometry and a plurality of first contact pads accessible along a first surface of the compliant printed circuit. At least one dielectric covering layer is preferably printed with a plurality of openings adapted to permit electrical coupling of terminals on the IC device and the first contact pads. Testing electronics is electrically coupled to test electrical functions of the IC device to the circuit geometry.

In one embodiment, pre-formed conductive trace materials are located in the recesses. The recesses are than plated to form conductive traces with substantially rectangular cross-sectional shapes. In another embodiment, a conductive foil is pressed into at least a portion of the recesses. The conductive foil is sheared along edges of the recesses. The excess conductive foil not located in the recesses is removed and the recesses are plated to form conductive traces with substantially rectangular cross-sectional shapes.

At least one electrical device is optionally printed on a dielectric layer and electrically coupled to at least a portion of the circuit geometry. Optical quality materials can be printed or deposited in at least a portion of the recesses to form optical circuit geometries. Alternatively, optical fibers can be located in the recesses.

The present compliant printed circuit tester interface can serve as a platform to add passive and active circuit features to improve electrical performance or internal function and intelligence. For example, electrical features and devices are printed onto the compliant printed circuit. The compliant printed circuit tester interface can also be configured with conductive traces that reduce or redistribute the terminal pitch, without the addition of an interposer or daughter substrate. Grounding schemes, shielding, electrical devices, and power planes can be added to the interconnect assembly, reducing the number of connections to the PCB and relieving routing constraints while increasing performance.

DETAILED DESCRIPTION OF THE INVENTION

FIG. 1is a side cross-sectional view of a method for replicating a compliant printed circuit for a semiconductor tester interface using additive processes in accordance with an embodiment of the present disclosure. Substrate50is a platform for the fabrication process, but may also be used in the finished tester interface.

One or more dielectric layers52,54are preferably printed on surface58of the substrate50to create recesses56corresponding to a desired circuit geometry. Alternatively, the recesses56can be defined by embossing, imprinting, chemical etching with a printed mask, or a variety of other techniques. A number of different materials are used as the substrate50including: polyester (PET), polyimide (PI), polyethylene napthalate (PEN), Polyetherimide (PEI), along with various fluropolymers (FEP) and copolymers. Polyimide films are the most prevalent due to their advantageous electrical, mechanical, chemical, and thermal properties.

As illustrated inFIG. 2, metalizing material is deposited in the recesses56to create conductive traces and circuit geometry62. Metalizing can be performed by printing conductive particles followed by a sintering step, by printing conductive inks, or a variety of other techniques. The resulting metalized layer is preferably plated to improve conductive properties. The circuit geometry62is preferably of copper or similar metallic materials such as phosphor bronze or beryllium-copper. The plating is preferably a corrosion resistant metallic material such as nickel, gold, silver, palladium, or multiple layers thereof.

As illustrated inFIG. 3, another dielectric or insulating layer64is applied to the circuit geometry62and the dielectric layer54. The nature of the printing process allows for selective application of dielectric layer64to leave selected portions66of the circuit geometry62expose if desired. The resulting compliant printed circuit68can potentially be considered entirely “green” with limited or no chemistry used to produce beyond the direct write materials.

The recesses56in the layers52,54,64permit control of the location, cross section, material content, and aspect ratio of the conductive traces in the circuit geometry62. Maintaining the conductive traces of the circuit geometry62with a cross-section of 1:1 or greater provides greater signal integrity than traditional subtractive trace forming technologies. For example, traditional methods take a sheet of a given thickness and etches the material between the traces away to have a resultant trace that is usually wider than it is thick. The etching process also removes more material at the top surface of the trace than at the bottom, leaving a trace with a trapezoidal cross-sectional shape, degrading signal integrity in some applications. Using the recesses56to control the aspect ratio of the conductive traces results in a more rectangular or square cross-section of the conductive traces in the circuit geometry62, with the corresponding improvement in signal integrity.

In another embodiment, pre-patterned or pre-etched thin conductive foil circuit traces are transferred to the recesses56. For example, a pressure sensitive adhesive can be used to retain the copper foil circuit traces in the recesses56. The trapezoidal cross-sections of the pre-formed conductive foil traces are then post-plated. The plating material fills the open spaces in the recesses56not occupied by the foil circuit geometry, resulting in a substantially rectangular or square cross-sectional shape corresponding to the shape of the recesses56.

In another embodiment, a thin conductive foil is pressed into the recesses56, and the edges of the recesses56acts to cut or shear the conductive foil. The process locates a portion of the conductive foil in the trenches56, but leaves the negative pattern of the conductive foil not wanted outside and above the trenches56for easy removal. Again, the foil in the trenches56is preferably post plated to add material to increase the thickness of the conductive traces in the circuit geometry62and to fill any voids left between the conductive foil and the recesses56.

The dielectric layers52,54,64may be constructed of any of a number of dielectric materials that are currently used to make sockets, semiconductor packaging, and printed circuit boards. Examples may include UV stabilized tetrafunctional epoxy resin systems referred to as Flame Retardant 4 (FR-4); bismaleimide-triazine thermoset epoxy resins referred to as BT-Epoxy or BT Resin; and liquid crystal polymers (LCPs), which are polyester polymers that are extremely unreactive, inert and resistant to fire. Other suitable plastics include phenolics, polyesters, and Ryton® available from Phillips Petroleum Company.

In one embodiment, one or more of the layer52,54,64are designed to provide electrostatic dissipation or to reduce cross-talk between the traces of the circuit geometry62. An efficient way to prevent electrostatic discharge (“ESD”) is to construct one of the layers from materials that are not too conductive but that will slowly conduct static charges away. These materials preferably have resistivity values in the range of 105to 1011Ohm-meters.

FIG. 4illustrates an alternate compliant printed circuit80in accordance with an embodiment of the present disclosure. Dielectric layer82includes openings84into which compliant material86is printed before formation of circuit geometry88. The compliant printed material86improves reliability during flexure of exposed portion90the circuit geometry88.

FIG. 5illustrates an alternate compliant printed circuit100in accordance with an embodiment of the present disclosure. Optical fibers102are located between layers104,106of dielectric material. In one embodiment, optical fibers102is positioned over printed compliant layer108, and dielectric layer110is printed over and around the optical fibers102. A compliant layer112is preferably printed above the optical fiber102as well. The compliant layers108,112support the optical fibers102during flexure. In another embodiment, the dielectric layer110is formed or printed with recesses into which the optical fibers102are deposited.

In another embodiment, optical quality materials114are printed during printing of the compliant printed circuit semiconductor tester interface100. The optical quality material114and/or the optical fibers102comprise optical circuit geometries. The printing process allows for deposition of coatings in-situ that enhance the optical transmission or reduce loss. The precision of the printing process reduces misalignment issues when the optical materials114are optically coupled with another optical structure.

FIG. 6illustrates another embodiment of a present compliant printed circuit140in accordance with an embodiment of the present disclosure. Embedded coaxial RF circuits142or printed micro strip RF circuits144are located with dielectric/metal layers146. These RF circuits142,144are preferably created by printing dielectrics and metallization geometry.

As illustrated inFIG. 7, use of additive processes allows the creation of a compliant printed circuit semiconductor tester interface160with inter-circuit, 3D lattice structures162having intricate routing schemes. Vias164can be printed with each layer, without drilling.

FIG. 8illustrates a compliant printed circuit semiconductor tester interface180with printed electrical devices182. The electrical devices182can include passive or active functional elements. Passive structure refers to a structure having a desired electrical, magnetic, or other property, including but not limited to a conductor, resistor, capacitor, inductor, insulator, dielectric, suppressor, filter, varistor, ferromagnet, and the like. In the illustrated embodiment, electrical devices182include printed LED indicator184and display electronics186. Geometries can also be printed to provide capacitive coupling188.

The electrical devices182are preferably printed during construction of the interconnect assembly100. The electrical devices182can be ground planes, power planes, electrical connections to other circuit members, dielectric layers, conductive traces, transistors, capacitors, resistors, RF antennae, shielding, filters, signal or power altering and enhancing devices, memory devices, embedded IC, and the like. For example, the electrical devices182can be formed using printing technology, adding intelligence to the compliant printed circuit semiconductor tester interface180. Features that are typically located on other circuit members can be incorporated into the flexible circuit180in accordance with an embodiment of the present disclosure.

Printing processes are preferably used to fabricate various functional structures, such as conductive paths and electrical devices, without the use of masks or resists. Features down to about 10 microns can be directly written in a wide variety of functional inks, including metals, ceramics, polymers and adhesives, on virtually any substrate—silicon, glass, polymers, metals and ceramics. The substrates can be planar and non-planar surfaces. The printing process is typically followed by a thermal treatment, such as in a furnace or with a laser, to achieve dense functionalized structures.

Ink jet printing of electronically active inks can be done on a large class of substrates, without the requirements of standard vacuum processing or etching. The inks may incorporate mechanical, electrical or other properties, such as, conducting, insulating, resistive, magnetic, semi conductive, light modulating, piezoelectric, spin, optoelectronic, thermoelectric or radio frequency.

A plurality of ink drops are dispensed from the print head directly to a substrate or on an intermediate transfer member. The transfer member can be a planar or non-planar structure, such as a drum. The surface of the transfer member can be coated with a non-sticking layer, such as silicone, silicone rubber, or Teflon.

The ink (also referred to as function inks) can include conductive materials, semi-conductive materials (e.g., p-type and n-type semiconducting materials), metallic material, insulating materials, and/or release materials. The ink pattern can be deposited in precise locations on a substrate to create fine lines having a width smaller than10microns, with precisely controlled spaces between the lines. For example, the ink drops form an ink pattern corresponding to portions of a transistor, such as a source electrode, a drain electrode, a dielectric layer, a semiconductor layer, or a gate electrode.

The substrate can be an insulating polymer, such as polyethylene terephthalate (PET), polyester, polyethersulphone (PES), polyimide film (e.g. Kapton, available from DuPont located in Wilmington, Del.; Upilex available from Ube Corporation located in Japan), or polycarbonate. Alternatively, the substrate can be made of an insulator such as undoped silicon, glass, or a plastic material. The substrate can also be patterned to serve as an electrode. The substrate can further be a metal foil insulated from the gate electrode by a non-conducting material. The substrate can also be a woven material or paper, planarized or otherwise modified on at least one surface by a polymeric or other coating to accept the other structures.

Electrodes can be printed with metals, such as aluminum or gold, or conductive polymers, such as polythiophene or polyaniline. The electrodes may also include a printed conductor, such as a polymer film comprising metal particles, such as silver or nickel, a printed conductor comprising a polymer film containing graphite or some other conductive carbon material, or a conductive oxide such as tin oxide or indium tin oxide.

Dielectric layers can be printed with a silicon dioxide layer, an insulating polymer, such as polyimide and its derivatives, poly-vinyl phenol, polymethylmethacrylate, polyvinyldenedifluoride, an inorganic oxide, such as metal oxide, an inorganic nitride such as silicon nitride, or an inorganic/organic composite material such as an organic-substituted silicon oxide, or a sol-gel organosilicon glass. Dielectric layers can also include a bicylcobutene derivative (BCB) available from Dow Chemical (Midland, Mich.), spin-on glass, or dispersions of dielectric colloid materials in a binder or solvent.

Semiconductor layers can be printed with polymeric semiconductors, such as, polythiophene, poly(3-alkyl)thiophenes, alkyl-substituted oligothiophene, polythienylenevinylene, poly(para-phenylenevinylene) and doped versions of these polymers. An example of suitable oligomeric semiconductor is alpha-hexathienylene. Horowitz, Organic Field-Effect Transistors, Adv. Mater., 10, No. 5, p. 365 (1998) describes the use of unsubstituted and alkyl-substituted oligothiophenes in transistors. A field effect transistor made with regioregular poly(3-hexylthiophene) as the semiconductor layer is described in Bao et al., Soluble and Processable Regioregular Poly(3-hexylthiophene) for Thin Film Field-Effect Transistor Applications with High Mobility, Appl. Phys. Lett. 69 (26), p. 4108 (December 1996). A field effect transistor made with a-hexathienylene is described in U.S. Pat. No. 5,659,181, which is incorporated herein by reference.

A protective layer can optionally be printed onto the electrical devices. The protective layer can be an aluminum film, a metal oxide coating, a substrate, or a combination thereof.

Organic semiconductors can be printed using suitable carbon-based compounds, such as, pentacene, phthalocyanine, benzodithiophene, buckminsterfullerene or other fullerene derivatives, tetracyanonaphthoquinone, and tetrakisimethylanimoethylene. The materials provided above for forming the substrate, the dielectric layer, the electrodes, or the semiconductor layer are exemplary only. Other suitable materials known to those skilled in the art having properties similar to those described above can be used in accordance with the present disclosure.

The ink-jet print head preferably includes a plurality of orifices for dispensing one or more fluids onto a desired media, such as for example, a conducting fluid solution, a semiconducting fluid solution, an insulating fluid solution, and a precursor material to facilitate subsequent deposition. The precursor material can be surface active agents, such as octadecyltrichlorosilane (OTS).

Alternatively, a separate print head is used for each fluid solution. The print head nozzles can be held at different potentials to aid in atomization and imparting a charge to the droplets, such as disclosed in U.S. Pat. No. 7,148,128 (Jacobson), which is hereby incorporated by reference. Alternate print heads are disclosed in U.S. Pat. No. 6,626,526 (Ueki et al.), and U.S. Pat. Publication Nos. 2006/0044357 (Andersen et al.) and 2009/0061089 (King et al.), which are hereby incorporated by reference.

The print head preferably uses a pulse-on-demand method, and can employ one of the following methods to dispense the ink drops: piezoelectric, magnetostrictive, electromechanical, electro pneumatic, electrostatic, rapid ink heating, magneto hydrodynamic, or any other technique well known to those skilled in the art. The deposited ink patterns typically undergo a curing step or another processing step before subsequent layers are applied.

While ink jet printing is preferred, the term “printing” is intended to include all forms of printing and coating, including: pre-metered coating such as patch die coating, slot or extrusion coating, slide or cascade coating, and curtain coating; roll coating such as knife over roll coating, forward and reverse roll coating; gravure coating; dip coating; spray coating; meniscus coating; spin coating; brush coating; air knife coating; screen printing processes; electrostatic printing processes; thermal printing processes; and other similar techniques.

FIG. 9illustrates an alternate compliant printed circuit semiconductor tester interface200with printed compliant material202added between circuit geometries204,206to facilitate insertion of exposed circuit geometries208,210into a receptacle or socket. The compliant material202can supplement or replace the compliance in the receptacle or socket. In one embodiment, the compliance is provided by a combination of the compliant material202and the exposed circuit geometries208,210.

FIG. 10illustrates a compliant printed circuit tester interface220with tester electronics added in accordance with an embodiment of the present disclosure. Golden devices222, field-programmable gate array (FPGA)224, logic devices226, memory devices228, and the like can be soldered to, or socketed on, the compliant printed circuit tester interface220to provide tester electronics, reducing or enhancing the tester resources. RF Wireless devices230can be added to facilitate wireless communication and data transfer between the operator, the tester interface220and the device under test.

FIG. 11is a side sectional view of a method of making a compliant printed circuit semiconductor tester interface250incorporating a connector function in accordance with an embodiment of the present disclosure. Substrate252includes a plurality of cavities254extending through dielectric layer256. The cavities254can be formed using a variety of techniques, such as molding, machining, printing, imprinting, embossing, etching, coining, and the like. Although the cavities254are illustrated as truncated cones or pyramids, a variety of other shapes can be used, such as for example, cones, hemispherical shapes, and the like.

As illustrated inFIG. 13, metalizing layer is printed in the cavities254to create contact member258and compliant layer260is printed on the dielectric layer256, followed by dielectric layer262establishing circuit geometry.

FIG. 14illustrates circuit geometries264printed as discussed above. In one embodiment, the circuit geometries264are formed by depositing a conductive material in a first state in the recesses, and then processed to create a second more permanent state. For example, the metallic powder is printed according to the circuit geometry and subsequently sintered, or the curable conductive material flows into the circuit geometry and is subsequently cured. As used herein “cure” and inflections thereof refers to a chemical-physical transformation that allows a material to progress from a first form (e.g., flowable form) to a more permanent second form. “Curable” refers to an uncured material having the potential to be cured, such as for example by the application of a suitable energy source.

Second compliant layer270is printed on exposed surfaces272of the dielectric layers262and circuit geometries264. The second compliant layer270and second dielectric layer274are selectively printed to permit printing of contact member276. Alternatively, pre-fabricated contact members276can be bonded to the circuit geometries264. As used herein, “bond” or “bonding” refers to, for example, adhesive bonding, solvent bonding, ultrasonic welding, thermal bonding, or any other techniques suitable for attaching adjacent layers to a substrate.

The dielectric layer274adjacent contact members276is optionally singulated to permit greater compliance. As used herein, “singulated” refers to slits, cuts, depressions, perforations, and/or points of weakness. In another embodiment, the compliant printed circuit semiconductor tester interface250is made in two portions and then bonded together.

FIG. 15illustrates a compliant printed circuit tester interface330with compliant structure332printed to add compliance and normal force334external to the circuit geometry336. For example, the compliant structure332can be a printed/sintering metallic spring. In another embodiment, the compliant structure332is a stamped or etched metallic, plastic, or overmolded leadframe that is added to the compliant printed circuit semiconductor tester interface330. The compliant members332can optionally be singulated in tandem with the circuit geometry336to allow for individual contact compliance.

FIG. 16illustrates a compliant printed circuit tester interface350with male contact member352in accordance with an embodiment of the present disclosure. Contact member352is preferably inserted through opening354printed in dielectric layers356,358and circuit geometry360. The resiliency of the dielectric layers356,358permits plastic deformation to permit enlarged end362to penetrate the opening354in the compliant printed circuit semiconductor tester interface350. The resilience of the dielectric layers356,358also permit the contact member360to move in all six degrees of freedom (X-Y-Z-Pitch-Roll-Yaw) to facilitate electrical coupling with first and second circuit members364,366.

FIG. 17illustrates a compliant printed circuit semiconductor tester interface370with printed compliant member372located above contact member374in accordance with an embodiment of the present disclosure. The printed compliant member372and associated contact member374is preferably singulated to promote flexure and compliance.

FIG. 18illustrates an alternate embodiment of a compliant printed circuit semiconductor tester interface380where printed compliant member382is located on circuit member384. In the illustrated embodiment, secondary printed compliant member386is located on the compliant printed circuit semiconductor tester interface380above contact member388.

FIG. 19illustrates a socket assembly400for a compliant printed circuit tester interface402in accordance with an embodiment of the present disclosure. Dielectric layer404is bonded to surface406of socket housing408so that contact members410are positioned in recess412. First circuit member414, such as an IC device, is positioned in the recess412so that the terminals416align with the contact members410.

Contact members410,418are optionally plated, either before or after the compliant printed circuit semiconductor tester interface402is installed in the socket housing408. In another embodiment, the contact members410,418are deformed, such as for example by coining or etching, to facilitate engagement with terminals414on the first circuit member414and/or terminal420on second circuit member422.

In operation, the first circuit member414, socket assembly400and the second circuit member422are compressively coupled so that contact member410electrically couples with terminal416and contact member418electrically couples with contact pad420. Compliant layer424biases the contact member410into engagement with the terminal416, while the compliant layer426biases the contact member418into engagement with the pad420. The compliant layers424,426also permit the contact members410,418to deflect and compensate for non-planarity of the terminals416or the pads418. As used herein, the term “circuit members” refers to, for example, a packaged integrated circuit device, an unpackaged integrated circuit device, a printed circuit board, a flexible circuit, a bare-die device, an organic or inorganic substrate, a rigid circuit, or any other device capable of carrying electrical current.

FIG. 20is an alternate tester interface450with additional functionality built into the compliant printed circuit452in accordance with an embodiment of the present disclosure. One or more of the layers454A,454B,454C,454D, and454E (collectively “454”) can include additional functionality, such as for example, specialty dielectrics, ground planes, power planes, shielding layers, stiffening layers, capacitive coupling features, circuitry layers, and the like. The layers454can be printed or preformed and selectively bonded or non-bonded to provide contiguous material or releasable layers.

The additional functionality can also be provided by additional electrical devices460, preferably positioned adjacent to a recess472of a socket housing468that receives the IC device464. The electrical devices460can be shielding, near device decoupling, capacitors, transistors, resistors, filters, signal or power altering and enhancing devices, memory devices, embedded IC, RF antennae, and the like. The electrical devices460can be added as discrete components or printed onto one of the layers. The electrical devices460can include passive or active functional elements. Passive structure refers to a structure having a desired electrical, magnetic, or other property, including but not limited to a conductor, resistor, capacitor, inductor, insulator, dielectric, suppressor, filter, varistor, ferromagnet, and the like.

In one embodiment, the compliant printed circuit452extends beyond a perimeter edge476of the socket housing468. In one embodiment, an extension470including a flexible circuit member can be electrically coupled to the compliant printed circuit452. In the illustrated embodiment, the compliant printed circuit452is electrically coupled to a test station466via the extension470. Alternatively, the test PCB462can be electrically coupled to the test station466.

The testing protocol can reside on the test PCB462, the test station466, or a combination thereof. Reference herein to the test PCB should be construed to encompass the test station, either coupled to the test PCB or directly to the compliant printed circuit.

In one embodiment, the electrical devices460monitor the testing of the IC device464and communicate feedback to test station466. In one embodiment, the feedback signal from the electrical devices460can cause the test station466to alter the testing protocol based on the performance of the IC device464. This can be referred to as adaptive testing. In one embodiment, the feedback signal from the electrical devices460can cause the test station466to alter the IC device464, such as for example, by altering software resident on the IC device464.

FIG. 21is a tester interface500in accordance with another embodiment of the present disclosure. The compliant printed circuit502can include multiple contacts504A,504B (collectively “504”) for each terminal506on an IC device508. The redundant contacts504can increase reliability and permit Kelvin measurements, which require two separate contact points at the terminal506of the IC device508routed to separate pads510A,510B (collectively “510”) on the test PCB512.

FIG. 22is tester interface520with common ground plane522in accordance with another embodiment of the present disclosure. Grounding contact members524,526can be coupled to a common conductive trace528in the compliant printed circuit530. The conductive trace528functions as a grounding plane522. The grounding contact members532,534can connect the ground plane522to a test PCB536.

FIG. 23is a test socket554having adjusted contact height550and lateral offset552, in accordance with an embodiment of the present disclosure.FIG. 23illustrates the adaptive capabilities of the present disclosure by showing an ability to adjust contact height550and lateral offset552of test sockets554. Increasing thickness556of one or both of the compliant layers558A,558B can permit the contact height550to be adjusted. The printing technology used to create the compliant printed circuit5260allows lateral offset552to be easily adjust. Consequently, compliant printed circuits in accordance with various embodiments of the present disclosure can be adapted for use in existing socket designs.

FIG. 24is a test socket570with relocated or rerouted contact members572A,572B (collectively “572”) in accordance with an embodiment of the present disclosure. The test socket570illustrates one of various routing options of contact members of a test socket. A compliant printed circuit574can permit the contact members572to be arranged in various configurations. In the embodiment ofFIG. 24, the compliant layer576can simultaneously bias the contact member572A toward an IC device578and the contact member572B toward the test PCB580.

FIG. 25illustrates the probe assembly600merged with a tester interface602in accordance with an embodiment of the present disclosure. Exposed portions604of the probe members606are optionally plated. In another embodiment, the probe members606are further processed, such as for example by coining or etching, to facilitate engagement with terminals608on a circuit member610. Although the present probe assembly600can be particularly well suited for probing wafer-level integrated circuits, it can be used on a variety of other circuit members, such as for example, packaged integrated circuits, unpackaged integrated circuits, printed circuit boards, flexible circuits, bare-die devices, organic or inorganic substrates, or any other device capable of carrying electrical current.

In operation, a normal force612can be applied to a top surface614of the probe assembly600so the distal ends616of the probe members606electrically couple with the terminals608on the circuit member610. The compliant layer618can compensate for non-planarity at the interface620.

FIG. 26is a cross-sectional view of an alternate probe assembly630coupled to tester interface632in accordance with an embodiment of the present disclosure. Gaps634,636are located substantially adjacent to probe members638to provide a degree of compliance. The gaps634,636decouple compliance of probe members638from dielectric layers640,642. Height644of the probe members638can be increased to reduce the chance of a bottom surface646of the dielectric layer640contacting wafer648.

FIG. 27is a cross-sectional view of an alternate probe assembly650for tester interface652with additional functional layers654A,654B,654C (collectively “654”), in accordance with an embodiment of the present disclosure. The functional layers can be, for example, specialty dielectrics, ground planes, power planes, shielding layers, stiffening layers, capacitive coupling features, circuitry layers, and the like. The layers654can be printed or preformed and selectively bonded or non-bonded to provide contiguous material or releasable layers.

In the illustrated embodiment, layers654A and654B are ground planes. Layer654C is a compliant layer that operates in either alone or in conjunction with gaps656adjacent to the probe members658to compensate for non-planarity at the interface660with the wafer662.

FIG. 28is a cross-sectional view of a probe assembly670with additional electrical devices672in accordance with embodiments of the present disclosure. The electrical devices672can be capacitors, transistors, resistors, filters, signal or power altering and enhancing devices, memory devices, an embedded IC, an RF antennae, and the like. The electrical devices672can be located on surface674or embedded in one of the layers. The probe assembly670can include an extension676, such as for example a flexible circuit member, electrically coupling conductive traces678to test station680.

The electrical devices672can be added as discrete components or printed onto one of the layers. The electrical devices672can be printed using inkjet printing technology, aerosol printing technology, or other maskless deposition techniques, as previously described. Electrical devices that are typically located on the test station680can be incorporated into the probe assembly670, improving electrical performance.

In one embodiment, the electrical devices672monitor the testing of the circuit member682and communicate feedback to the test station680. In one embodiment, a feedback signal from the electronic devices672can cause the test station680to alter the testing protocol depending on the performance of the circuit member682, referred to as adaptive testing. In one embodiment, the feedback signal from the electronic devices672can cause the test station680to alter the circuit member682, such as for example, by altering software resident on the circuit member682.

FIG. 29is a cross-sectional view of a probe assembly700with multiple layers702in accordance with an embodiment of the present disclosure. The probe assembly700can permit IC manufactures to reduce the pitch704of the terminals706on the IC devices708since the required signal routing to a test station710is performed by the probe assembly700.

FIG. 30is a cross-sectional view of a probe assembly720with coupling features722in accordance with an embodiment of the present disclosure. In one embodiment, the coupling features722can be capacitive couplings located between dielectric layers724,726. In another embodiment, the coupling features722can be optical fibers supported by the dielectric layers724,726. Optical quality materials can optionally be printed directly onto the dielectric layers724,726. The printing process can also allow for deposition of coatings in-situ that will enhance the optical transmission or reduce loss. The precision of the printing process can resolve misalignment issues when the optical fibers722are placed into a connector. In another embodiment, the coupling features722can be embedded coaxial or printed micro strip RF circuits with dielectric layers724,726. The dielectric layers724,726can be formed of metal. Any of the structures noted above, as well as the probe members728, can be created by printing dielectrics and metallization geometry.

FIG. 31illustrates tester interface750merged with compliant conductive interconnect752in accordance with an embodiment of the present disclosure. Compliant material754is printed directly on the tester interface750so through holes756are generally aligned with contact pads758. Conductive particles760are then deposited in the through holes756. Contact tips762are secured to distal surface764of the compliant material754by one or more covering layers766. Electrical devices768are optionally printed as part of the interconnect assembly752, as discussed above. As used herein, “conductive particles” refers to a plurality of free-flowing conductive elements, substantially free of binders or other non-conductive materials.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the embodiments of the present disclosure belong. Although any methods and materials similar or equivalent to those described herein can also be used in the practice or testing of the embodiments of the present disclosure, the preferred methods and materials are now described. All patents and publications mentioned herein, including those cited in the Background of the application, are hereby incorporated by reference to disclose and described the methods and/or materials in connection with which the publications are cited.

Other embodiments of the disclosure are possible. Although the description above contains much specificity, these should not be construed as limiting the scope of the disclosure, but as merely providing illustrations of some of the presently preferred embodiments of this disclosure. It is also contemplated that various combinations or sub-combinations of the specific features and aspects of the embodiments may be made and still fall within the scope of the present disclosure. It should be understood that various features and aspects of the disclosed embodiments can be combined with or substituted for one another in order to form varying modes of the disclosed embodiments of the disclosure. Thus, it is intended that the scope of the present disclosure herein disclosed should not be limited by the particular disclosed embodiments described above.