NAND flash memory programming

A programming method and memory structure for preventing punch-through in a short channel source-side select gate structure includes adjusting voltages on the selected and unselected bitlines, and the program, pass, and select gate voltages.

FIELD

The present invention relates generally to NAND memories and in particular the present invention relates to programming NAND memories.

BACKGROUND

Flash memory devices have developed into a popular source of non-volatile memory for a wide range of electronic applications. Flash memory devices typically use a one-transistor memory cell that allows for high memory densities, high reliability, and low power consumption. Changes in threshold voltage of the cells, through programming of charge storage or trapping layers or other physical phenomena, determine the data value of each cell. Common uses for flash memory include personal computers, personal digital assistants (PDAs), digital cameras, digital media players, digital recorders, games, appliances, vehicles, wireless devices, cellular telephones, and removable memory modules, and the uses for flash memory continue to expand.

Flash memory typically utilizes one of two basic architectures known as NOR flash and NAND flash. The designation is derived from the logic used to read the devices. In NOR flash architecture, a column of memory cells are coupled in parallel with each memory cell coupled to a bit line. In NAND flash architecture, a column of memory cells are coupled in series with only the first memory cell of the column coupled to a bit line.

As the performance of electronic systems employing flash memory devices increases, flash memory device performance should also increase. A performance increase includes reducing power consumption, increasing speed, and increasing the memory density. One way to accomplish these tasks is by decreasing the size of the memory array and its individual devices.

Select gates for NAND structures are typically 150-200 nanometers (nm) in length. With the increasing pressure on making devices smaller, select gate sizes are continuing to decrease. For example, commonly owned disclosure ( . . . ) describes select gate lengths of 50 mm or less. When such small distances separate gates and their underlying structures, the voltages and currents involved can break down the gaps between source and drain of cells of adjacent NAND strings, causing a large and undesirable current flow known as punch through. Typical voltages and a partial NAND memory are shown inFIG. 1.

For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for new programming methods for short channel select gate NAND memories.

DETAILED DESCRIPTION

The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of the present invention is defined only by the appended claims, along with the full scope of equivalents to which such claims are entitled.

In one embodiment of the present invention, when a short channel source-side select gate is used in a NAND memory, punch through is eliminated by varying the voltages for selected and unselected bitlines, as well as the voltages for drain select gate, pass, and program voltages. Referring toFIG. 2, a NAND memory200is shown in part. Memory200has a selected NAND string201and an unselected NAND string203. In this embodiment, the bitline202connected to the selected NAND string201is biased to approximately 1.5 volts, whereas typical select bitlines are biased to 0 volts. The bitline204connected to the unselected NAND string203is biased to approximately 3.0 volts, whereas typical unselected bitlines are biased anywhere from 1.5 to 3.3 volts. The gate of drain select gate transistor206is biased to typical drain gate bias voltage plus the additional voltage applied to the selected bitline, in this embodiment 1.5 volts.

Further, the pass voltage, that is the voltage applied to non-programming word lines to allow their cells to act as pass transistors, which is typically approximately 9 volts, is raised by the same amount, again in this embodiment 1.5 volts, and the program voltage, typically approximately 20 volts, is also raised by the same amount. Punch through is stopped by the voltage placed on the selected bitline, allowing short channel source-side select gates to be used. This allows for a reduction in the amount of die real estate used for cells, and improves cell density.

Other NAND structures that are in use or are being developed will also be amenable to use with the method described above. For example,FIG. 3shows part of a double select gate NAND memory300. Each bitline for the double select gate NAND300has two drain select gate transistors and two source select gate transistors. For the double select gate NAND structure300, selected bitline302has a voltage that is typically 0 volts. Unselected bitline304has typical voltage of 1.8 to 3.3 volts. In the embodiment shown, the voltage for selected bitline302is raised to approximately 1.5 volts, and the voltage for unselected bitline304is raised to approximately 3.0 volts. The gate of the first drain select gate transistor306is biased to typical drain gate bias voltage plus the additional voltage applied to the selected bitline, in this embodiment 1.5 volts. The gate of the second drain select gate transistor308is biased to approximately 0 volts (the approximate pass voltage for a read operation), as is the gate of the second source select gate transistor310.

Further, the pass voltage, that is the voltage applied to non-programming word lines to allow their cells to act as pass transistors, which is typically approximately 9 volts, is raised by the same amount, again in this embodiment 1.5 volts, and the program voltage, typically approximately 20 volts, is also raised by the same amount. Punch through is stopped by the voltage placed on the selected bitline, allowing short channel source-side select gates to be used. This allows for a reduction in the amount of die real estate used for cells, and improves cell density.

In another embodiment, different voltages are adjusted to eliminate punch-through in a short channel source-side select gate NAND. Referring toFIG. 4, a portion of a NAND memory400is shown. In this embodiment, the structure of the NAND400is the same or substantially similar to that of NAND200described above. However, in this embodiment, the voltages on selected and unselected bitlines402and404, respectively, remain the same as those of typical bitline voltages. The voltage of the p-well (or tub) is lowered to approximately −1.5 volts. The select gate406voltage is raised by approximately 1.5 volts. The pass and program voltages remain substantially the same in one embodiment for programming, but for an inhibit operation, the pass and program voltages are in one embodiment raised but are not required to be raised substantially. The raising of the program and pass voltages allows for better inhibit operation. The back-biasing of the p-well, accompanied by the raising of the drain select gate voltage to approximately 1.5 volts, eliminates punch through for short channel source-side select gates.

Referring toFIG. 5, the method described above with respect to back-biasing the p-well voltage while raising the drain select gate voltage applies equally well to a double NAND structure such as double NAND500. In this embodiment, the voltages applied to the selected and unselected bitlines502and504are approximately 0 and 1.5 volts, respectively. The tub or p-well voltage is biased to approximately −1.5 volts. The gate of the first drain select gate transistor506is raised by approximately 1.5 volts. The gate of the second drain select gate transistor508is biased to approximately 0 volts (the approximate pass voltage for a read operation), as is the gate of the second source select gate transistor510.

The pass and program voltages remain substantially the same in one embodiment for programming, but for an inhibit operation, the pass and program voltages are in one embodiment raised but are not required to be raised substantially. The raising of the program and pass voltages allows for better inhibit operation. The back-biasing of the p-well, accompanied by the raising of the drain select gate voltage to approximately 1.5 volts, eliminates punch through for short channel source-side select gates.

Another embodiment of the present invention is shown inFIG. 5A. In this embodiment, punch through is eliminated by managing the voltages for selected and unselected bitlines; the voltages for drain select gate, pass, and program voltages; and the well voltage. Referring toFIG. 5A, a NAND memory520is shown in part. Memory520has a selected bitline522and an unselected bitline524. In this embodiment, the voltage for the selected bitline (Vbls)522is set to approximately equal the source voltage (Vsrc), and both those voltages are set higher than the tub or p-well voltage (Vwell)532. Optionally, in addition, the unselected bitline voltage (Vblu) is set to be greater than the selected bitline voltage by approximately 2 volts. Alternatively, the selected bitline voltage is set to be greater than 0 volts but still substantially equal to the source voltage and greater than the well voltage. Still further optionally, that is with the selected bitline voltage substantially equal to the source voltage and greater than the well voltage, the well voltage is set to less than 0 volts. In all options, the pass, program, and select gate voltages (528,530, and526respectively) are raised to approximately the level of the selected bitline voltage.

In table form, the bias levels are managed as follows:

While there are many bias voltage levels that satisfy the embodiments shown inFIG. 5A, some specific embodiments are particularly amenable to use with those embodiments. For example, in one embodiment, the source voltage and the selected bitline522voltages are each approximately 1.5 volts, and the voltage of tub or p-well532is 0 volts. In another embodiment, the source voltage and the selected bitline522voltages are each approximately 1.5 volts, the voltage of tub or p-well532is 0 volts, and the unselected bitline524voltage is set to approximately 3.5 volts. In another embodiment, the source voltage and the selected bitline522voltages are each approximately equal, the voltage of tub or p-well532is 0 volts, and the selected bitline voltage is greater than 0 volts. In yet another embodiment, the source voltage and the selected bitline522voltages are substantially the same, greater than 0 volts (for example, 1 volt), the voltage of tub or p-well532is approximately −0.5 volts. It should be seen that there are any number of voltages that can be chosen to satisfy the conditions of the embodiment, and that such selections are within the scope of the invention.

As before, the voltage levels shown above with respect to NAND520apply equally well to a double select gate NAND such as NAND300or NAND500, where the gate of the first drain select gate transistor is raised to approximately the bias level of the selected bitline, the gate of the second drain select gate transistor is biased to approximately the pass voltage for a read operation, as is the gate of the second source select gate transistor.

The embodiments of the present invention allow the reduction in length of select gates from the current range of 150-200 nanometers to 50 nanometers and less. This reduction in length allows for increased density of components on a die.

FIG. 6is a functional block diagram of a memory device600, such as a flash memory device, of one embodiment of the present invention, which is coupled to a processor610. The memory device600and the processor610may form part of an electronic system620. The memory device600has been simplified to focus on features of the memory that are helpful in understanding the present invention. The memory device includes an array of memory cells630having even/odd bitline configurations such as those shown inFIGS. 2,3,4, or5and described above. The memory array630is arranged in banks of rows and columns.

An address buffer circuit640is provided to latch address signals provided on address input connections A0-Ax642. Address signals are received and decoded by row decoder644and a column decoder646to access the memory array630. It will be appreciated by those skilled in the art, with the benefit of the present description, that the number of address input connections depends upon the density and architecture of the memory array. That is, the number of addresses increases with both increased memory cell counts and increased bank and block counts.

The memory device reads data in the array630by sensing voltage or current changes in the memory array columns using sense/latch circuitry650. The sense/latch circuitry, in one embodiment, is coupled to read and latch a row of data from the memory array. Data input and output buffer circuitry660is included for bi-directional data communication over a plurality of data (DQ) connections662with the processor610, and is connected to write circuitry655and read/latch circuitry650for performing read and write operations on the memory600.

Command control circuit670decodes signals provided on control connections672from the processor610. These signals are used to control the operations on the memory array630, including data read, data write, and erase operations. The flash memory device has been simplified to facilitate a basic understanding of the features of the memory. A more detailed understanding of internal circuitry and functions of flash memories are known to those skilled in the art.

FIG. 7is an illustration of an exemplary memory module700. Memory module700is illustrated as a memory card, although the concepts discussed with reference to memory module700are applicable to other types of removable or portable memory, e.g., USB flash drives, and are intended to be within the scope of “memory module” as used herein. In addition, although one example form factor is depicted inFIG. 7, these concepts are applicable to other form factors as well.

In some embodiments, memory module700will include a housing705(as depicted) to enclose one or more memory devices710, though such a housing is not essential to all devices or device applications. At least one memory device710is a non-volatile memory having voltages applied according to the methods described above according to various embodiments of the present invention, and described above with respect toFIGS. 2,3,4, or5. Where present, the housing705includes one or more contacts715for communication with a host device. Examples of host devices include digital cameras, digital recording and playback devices, PDAs, personal computers, memory card readers, interface hubs and the like. For some embodiments, the contacts715are in the form of a standardized interface. For example, with a USB flash drive, the contacts715might be in the form of a USB Type-A male connector. For some embodiments, the contacts715are in the form of a semi-proprietary interface, such as might be found on CompactFlash™ memory cards licensed by SanDisk Corporation, Memory Stick™ memory cards licensed by Sony Corporation, SD Secure Digital™ memory cards licensed by Toshiba Corporation and the like. In general, however, contacts715provide an interface for passing control, address and/or data signals between the memory module700and a host having compatible receptors for the contacts715.

The memory module700may optionally include additional circuitry720which may be one or more integrated circuits and/or discrete components. For some embodiments, the additional circuitry720may include a memory controller for controlling access across multiple memory devices710and/or for providing a translation layer between an external host and a memory device710. For example, there may not be a one-to-one correspondence between the number of contacts715and a number of I/O connections to the one or more memory devices710. Thus, a memory controller could selectively couple an I/O connection (not shown inFIG. 7) of a memory device710to receive the appropriate signal at the appropriate I/O connection at the appropriate time or to provide the appropriate signal at the appropriate contact715at the appropriate time. Similarly, the communication protocol between a host and the memory module700may be different than what is required for access of a memory device710. A memory controller could then translate the command sequences received from a host into the appropriate command sequences to achieve the desired access to the memory device710. Such translation may further include changes in signal voltage levels in addition to command sequences.

The additional circuitry720may further include functionality unrelated to control of a memory device710such as logic functions as might be performed by an ASIC (application specific integrated circuit). Also, the additional circuitry720may include circuitry to restrict read or write access to the memory module700, such as password protection, biometrics or the like. The additional circuitry720may include circuitry to indicate a status of the memory module700. For example, the additional circuitry720may include functionality to determine whether power is being supplied to the memory module700and whether the memory module700is currently being accessed, and to display an indication of its status, such as a solid light while powered and a flashing light while being accessed. The additional circuitry720may further include passive devices, such as decoupling capacitors to help regulate power requirements within the memory module700.

CONCLUSION

A method of programming a NAND memory having a short source-side select gate has been described that includes adjusting voltages of selected bitline, unselected bitline, and drain select gate, pass, and program voltages by an equal amount to that of the selected bitline. Another method of programming a NAND memory having a short source-side select gate includes adjusting a well voltage and a drain select gate voltage to prevent punch through. Other methods are described and claimed.