Methods of indirect register access including automatic modification of a directly accessible address register

Systems and methods are provided for managing access to registers. A system may include a set of direct registers and a set of indirect registers. The indirect registers may be accessed through the direct registers, and the direct registers may provide various features to provide faster access to the indirect registers. One of the direct registers may indicate access modes for accessing the indirect registers. The access modes may include auto-increment, auto-decrement, auto-reset, and no change modes. Based on the access mode, the currently accessed address may be automatically modified after accessing the indirect register at the address.

BACKGROUND

1. Field of Invention

Embodiments of the invention relate generally to digital data processing, and, more specifically, in certain embodiments, to providing and managing registers.

2. Description of Related Art

In the field of computing, pattern recognition tasks are increasingly challenging. Ever larger volumes of data are transmitted between computers, and the number of patterns that users wish to identify is increasing. For example, spam or malware are often detected by searching for patterns in a data stream, e.g., particular phrases or pieces of code. The number of patterns increases with the variety of spam and malware, as new patterns may be implemented to search for new variants. Searching a data stream for each of these patterns can form a computing bottleneck. Often, as the data stream is received, it is searched for each pattern, one at a time. The delay before the system is ready to search the next portion of the data stream increases with the number of patterns. Thus, pattern recognition may slow the receipt of data.

Additionally, systems that perform the pattern recognition and the other associated processing may use multiple registers to store various data, such as search data, configuration parameters, status information, pattern-matching results, or the like. These “processor registers” may typically be directly available to a processing unit of the system, for example, in order to provide quick access as compared to other storage that may be accessible to the processing unit. It may be appreciated, however, that many systems include a finite addressing space for recording the physical location of various forms of memory, including main system memory (e.g., random access memory) as well as such registers. Further, certain systems, such as pattern-recognition systems, may include a large number of registers to enable configuration and operation of the system. If a system includes a large number of registers accessible by the processing unit, the remaining address space available for main system memory may be reduced and overall performance of the system may be impacted.

DETAILED DESCRIPTION OF SPECIFIC EMBODIMENTS

FIG. 1depicts an example of a system10that searches a data stream12. The system10may include a pattern-recognition processor14that searches the data stream12according to search criteria16.

Each search criterion may specify one or more target expressions, i.e., patterns. The phrase “target expression” refers to a sequence of data for which the pattern-recognition processor14is searching. Examples of target expressions include a sequence of characters that spell a certain word, a sequence of genetic base pairs that specify a gene, a sequence of bits in a picture or video file that form a portion of an image, a sequence of bits in an executable file that form a part of a program, or a sequence of bits in an audio file that form a part of a song or a spoken phrase.

Each search criterion may be constructed from one or more search terms. Thus, each target expression of a search criterion may include one or more search terms and some target expressions may use common search terms. As used herein, the phrase “search term” refers to a sequence of data that is searched for, during a single search cycle. The sequence of data may include multiple bits of data in a binary format or other formats, e.g., base ten, ASCII, etc. The sequence may encode the data with a single digit or multiple digits, e.g., several binary digits. For example, the pattern-recognition processor14may search a text data stream12one character at a time, and the search terms may specify a set of single characters, e.g., the letter “a”, either the letters “a” or “e”, or a wildcard search term that specifies a set of all single characters.

Search terms may be smaller or larger than the number of bits that specify a character (or other grapheme—i.e., fundamental unit—of the information expressed by the data stream, e.g., a musical note, a genetic base pair, a base-10 digit, or a sub-pixel). For instance, a search term may be 8 bits and a single character may be 16 bits, in which case two consecutive search terms may specify a single character.

The search criteria16may be formatted for the pattern-recognition processor14by a compiler18. Formatting may include deconstructing search terms from the search criteria. For example, if the graphemes expressed by the data stream12are larger than the search terms, the compiler may deconstruct the search criterion into multiple search terms to search for a single grapheme. Similarly, if the graphemes expressed by the data stream12are smaller than the search terms, the compiler18may provide a single search term, with unused bits, for each separate grapheme. The compiler18may also format the search criteria16to support various regular expressions operators that are not natively supported by the pattern-recognition processor14.

The pattern-recognition processor14may search the data stream12by evaluating each new term from the data stream12. The word “term” here refers to the amount of data that could match a search term. During a search cycle, the pattern-recognition processor14may determine whether the currently presented term matches the current search term in the search criterion. If the term matches the search term, the evaluation is “advanced”, i.e., the next term is compared to the next search term in the search criterion. If the term does not match, the next term is compared to the first term in the search criterion, thereby resetting the search.

Each search criterion may be compiled into a different finite state machine in the pattern-recognition processor14. The finite state machines may run in parallel, searching the data stream12according to the search criteria16. The finite state machines may step through each successive search term in a search criterion as the preceding search term is matched by the data stream12, or if the search term is unmatched, the finite state machines may begin searching for the first search term of the search criterion.

The pattern-recognition processor14may evaluate each new term according to several search criteria, and their respective search terms, at about the same time, e.g., during a single device cycle. The parallel finite state machines may each receive the term from the data stream12at about the same time, and each of the parallel finite state machines may determine whether the term advances the parallel finite state machine to the next search term in its search criterion. The parallel finite state machines may evaluate terms according to a relatively large number of search criteria, e.g., more than 100, more than 1000, or more than 10,000. Because they operate in parallel, they may apply the search criteria to a data stream12having a relatively high bandwidth, e.g., a data stream12of greater than or generally equal to 64 MB per second or 128 MB per second, without slowing the data stream. In some embodiments, the search-cycle duration does not scale with the number of search criteria, so the number of search criteria may have little to no effect on the performance of the pattern-recognition processor14.

When a search criterion is satisfied (i.e., after advancing to the last search term and matching it), the pattern-recognition processor14may report the satisfaction of the criterion to a processing unit, such as a central processing unit (CPU)20. The central processing unit20may control the pattern-recognition processor14and other portions of the system10.

The system10may be any of a variety of systems or devices that search a stream of data. For example, the system10may be a desktop, laptop, handheld or other type of computer that monitors the data stream12. The system10may also be a network node, such as a router, a server, or a client (e.g., one of the previously-described types of computers). The system10may be some other sort of electronic device, such as a copier, a scanner, a printer, a game console, a television, a set-top video distribution or recording system, a cable box, a personal digital media player, a factory automation system, an automotive computer system, or a medical device. (The terms used to describe these various examples of systems, like many of the other terms used herein, may share some referents and, as such, should not be construed narrowly in virtue of the other items listed.)

The data stream12may be one or more of a variety of types of data streams that a user or other entity might wish to search. For example, the data stream12may be a stream of data received over a network, such as packets received over the Internet or voice or data received over a cellular network. The data stream12may be data received from a sensor in communication with the system10, such as an imaging sensor, a temperature sensor, an accelerometer, or the like, or combinations thereof. The data stream12may be received by the system10as a serial data stream, in which the data is received in an order that has meaning, such as in a temporally, lexically, or semantically significant order. Alternatively, the data stream12may be received in parallel or out of order and, then, converted into a serial data stream, e.g., by reordering packets received over the Internet. In some embodiments, the data stream12may present terms serially, but the bits expressing each of the terms may be received in parallel. The data stream12may be received from a source external to the system10, or may be formed by interrogating a memory device and forming the data stream12from stored data.

Depending on the type of data in the data stream12, different types of search criteria may be chosen by a designer. For instance, the search criteria16may be a virus definition file. Viruses or other malware may be characterized, and aspects of the malware may be used to form search criteria that indicate whether the data stream12is likely delivering malware. The resulting search criteria may be stored on a server, and an operator of a client system may subscribe to a service that downloads the search criteria to the system10. The search criteria16may be periodically updated from the server as different types of malware emerge. The search criteria may also be used to specify undesirable content that might be received over a network, for instance unwanted emails (commonly known as spam) or other content that a user finds objectionable.

The data stream12may be searched by a third party with an interest in the data being received by the system10. For example, the data stream12may be monitored for text, a sequence of audio, or a sequence of video that occurs in a copyrighted work. The data stream12may be monitored for utterances that are relevant to a criminal investigation or civil proceeding or are of interest to an employer.

The search criteria16may also include patterns in the data stream12for which a translation is available, e.g., in memory addressable by the CPU20or the pattern-recognition processor14. For instance, the search criteria16may each specify an English word for which a corresponding Spanish word is stored in memory. In another example, the search criteria16may specify encoded versions of the data stream12, e.g., MP3, MPEG 4, FLAC, Ogg Vorbis, etc., for which a decoded version of the data stream12is available, or vice versa.

The pattern-recognition processor14may be hardware that is integrated with the CPU20into a single component (such as a single device) or may be formed as a separate component. For instance, the pattern-recognition processor14may be a separate integrated circuit. The pattern-recognition processor14may be referred to as a “co-processor” or a “pattern-recognition co-processor”.

FIG. 2depicts an example of the pattern-recognition processor14. The pattern-recognition processor14may include a recognition module22and an aggregation module24. The recognition module22may be configured to compare received terms to search terms, and both the recognition module22and the aggregation module24may cooperate to determine whether matching a term with a search term satisfies a search criterion.

The recognition module22may include a row decoder28and a plurality of feature cells30. Each feature cell30may specify a search term, and groups of feature cells30may form a parallel finite state machine that forms a search criterion. Components of the feature cells30may form a search-term array32, a detection array34, and an activation-routing matrix36. The search-term array32may include a plurality of input conductors37, each of which may place each of the feature cells30in communication with the row decoder28.

The row decoder28may select particular conductors among the plurality of input conductors37based on the content of the data stream12. For example, the row decoder28may be a one byte to 256 row decoder that activates one of 256 rows based on the value of a received byte, which may represent one term. A one-byte term of 0000 0000 may correspond to the top row among the plurality of input conductors37, and a one-byte term of 1111 1111 may correspond to the bottom row among the plurality of input conductors37. Thus, different input conductors37may be selected, depending on which terms are received from the data stream12. As different terms are received, the row decoder28may deactivate the row corresponding to the previous term and activate the row corresponding to the new term.

The detection array34may couple to a detection bus38that outputs signals indicative of complete or partial satisfaction of search criteria to the aggregation module24. The activation-routing matrix36may selectively activate and deactivate feature cells30based on the number of search terms in a search criterion that have been matched.

The aggregation module24may include a latch matrix40, an aggregation-routing matrix42, a threshold-logic matrix44, a logical-product matrix46, a logical-sum matrix48, and an initialization-routing matrix50.

The latch matrix40may implement portions of certain search criteria. Some search criteria, e.g., some regular expressions, count only the first occurrence of a match or group of matches. The latch matrix40may include latches that record whether a match has occurred. The latches may be cleared during initialization, and periodically re-initialized during operation, as search criteria are determined to be satisfied or not further satisfiable—i.e., an earlier search term may need to be matched again before the search criterion could be satisfied.

The aggregation-routing matrix42may function similar to the activation-routing matrix36. The aggregation-routing matrix42may receive signals indicative of matches on the detection bus38and may route the signals to different group-logic lines53connecting to the threshold-logic matrix44. The aggregation-routing matrix42may also route outputs of the initialization-routing matrix50to the detection array34to reset portions of the detection array34when a search criterion is determined to be satisfied or not further satisfiable.

The threshold-logic matrix44may include a plurality of counters, e.g., 32-bit counters configured to count up or down. The threshold-logic matrix44may be loaded with an initial count, and it may count up or down from the count based on matches signaled by the recognition module. For instance, the threshold-logic matrix44may count the number of occurrences of a word in some length of text.

The outputs of the threshold-logic matrix44may be inputs to the logical-product matrix46. The logical-product matrix46may selectively generate “product” results (e.g., “AND” function in Boolean logic). The logical-product matrix46may be implemented as a square matrix, in which the number of output products is equal the number of input lines from the threshold-logic matrix44, or the logical-product matrix46may have a different number of inputs than outputs. The resulting product values may be output to the logical-sum matrix48.

The logical-sum matrix48may selectively generate sums (e.g., “OR” functions in Boolean logic.) The logical-sum matrix48may also be a square matrix, or the logical-sum matrix48may have a different number of inputs than outputs. Since the inputs are logical products, the outputs of the logical-sum matrix48may be logical-Sums-of-Products (e.g., Boolean logic Sum-of-Product (SOP) form). The output of the logical-sum matrix48may be received by the initialization-routing matrix50.

The initialization-routing matrix50may reset portions of the detection array34and the aggregation module24via the aggregation-routing matrix42. The initialization-routing matrix50may also be implemented as a square matrix, or the initialization-routing matrix50may have a different number of inputs than outputs. The initialization-routing matrix50may respond to signals from the logical-sum matrix48and re-initialize other portions of the pattern-recognition processor14, such as when a search criterion is satisfied or determined to be not further satisfiable.

The aggregation module24may include an output buffer51that receives the outputs of the threshold-logic matrix44, the aggregation-routing matrix42, and the logical-sum matrix48. The output of the aggregation module24may be transmitted from the output buffer51to the CPU20(FIG. 1) on the output bus26. In some embodiments, an output multiplexer may multiplex signals from these components42,44, and48and output signals indicative of satisfaction of criteria or matches of search terms to the CPU20(FIG. 1). In other embodiments, results from the pattern-recognition processor14may be reported without transmitting the signals through the output multiplexer, which is not to suggest that any other feature described herein could not also be omitted. For example, signals from the threshold-logic matrix44, the logical-product matrix46, the logical-sum matrix48, or the initialization routing matrix50may be transmitted to the CPU in parallel on the output bus26.

FIG. 3illustrates a portion of a single feature cell30in the search-term array32(FIG. 2), a component referred to herein as a search-term cell54. The search-term cells54may include an output conductor56and a plurality of memory cells58. Each of the memory cells58may be coupled to both the output conductor56and one of the conductors among the plurality of input conductors37. In response to its input conductor37being selected, each of the memory cells58may output a value indicative of its stored value, outputting the data through the output conductor56. In some embodiments, the plurality of input conductors37may be referred to as “word lines”, and the output conductor56may be referred to as a “data line”.

The memory cells58may include any of a variety of types of memory cells. For example, the memory cells58may be volatile memory, such as dynamic random access memory (DRAM) cells having a transistor and a capacitor. The source and the drain of the transistor may be connected to a plate of the capacitor and the output conductor56, respectively, and the gate of the transistor may be connected to one of the input conductors37. In another example of volatile memory, each of the memory cells58may include a static random access memory (SRAM) cell. The SRAM cell may have an output that is selectively coupled to the output conductor56by an access transistor controlled by one of the input conductors37. The memory cells58may also include nonvolatile memory, such as phase-change memory (e.g., an ovonic device), flash memory, silicon-oxide-nitride-oxide-silicon (SONOS) memory, magneto-resistive memory, or other types of nonvolatile memory. The memory cells58may also include flip-flops, e.g., memory cells made out of logic gates.

FIGS. 4 and 5depict an example of the search-term cell54in operation.FIG. 4illustrates the search-term cell54receiving a term that does not match the cell's search term, andFIG. 5illustrates a match.

As illustrated byFIG. 4, the search-term cell54may be configured to search for one or more terms by storing data in the memory cells58. The memory cells58may each represent a term that the data stream12might present, e.g., inFIG. 3, each memory cell58represents a single letter or number, starting with the letter “a” and ending with the number “9”. Memory cells58representing terms that satisfy the search term may be programmed to store a first value, and memory cells58that do not represent terms that satisfy the search term may be programmed to store a different value. In the illustrated example, the search-term cell54is configured to search for the letter “b”. The memory cells58that represent “b” may store a 1, or logic high, and the memory cells58that do not represent “b” may be programmed to store a 0, or logic low.

To compare a term from the data stream12with the search term, the row decoder28may select the input conductor37coupled to memory cells58representing the received term. InFIG. 4, the data stream12presents a lowercase “e”. This term may be presented by the data stream12in the form of an eight-bit ASCII code, and the row decoder28may interpret this byte as a row address, outputting a signal on the conductor60by energizing it.

In response, the memory cell58controlled by the conductor60may output a signal indicative of the data that the memory cell58stores, and the signal may be conveyed by the output conductor56. In this case, because the letter “e” is not one of the terms specified by the search-term cell54, it does not match the search term, and the search-term cell54outputs a 0 value, indicating no match was found.

InFIG. 5, the data stream12presents a character “b”. Again, the row decoder28may interpret this term as an address, and the row decoder28may select the conductor62. In response, the memory cell58representing the letter “b” outputs its stored value, which in this case is a 1, indicating a match.

The search-term cells54may be configured to search for more than one term at a time. Multiple memory cells58may be programmed to store a 1, specifying a search term that matches with more than one term. For instance, the memory cells58representing the letters lowercase “a” and uppercase “A” may be programmed to store a 1, and the search-term cell54may search for either term. In another example, the search-term cell54may be configured to output a match if any character is received. All of the memory cells58may be programmed to store a 1, such that the search-term cell54may function as a wildcard term in a search criterion.

FIGS. 6-8depict the recognition module22searching according to a multi-term search criterion, e.g., for a word. Specifically,FIG. 6illustrates the recognition module22detecting the first letter of a word,FIG. 7illustrates detection of the second letter, andFIG. 8illustrates detection of the last letter.

As illustrated byFIG. 6, the recognition module22may be configured to search for the word “big”. Three adjacent feature cells63,64, and66are illustrated. The feature cell63is configured to detect the letter “b”. The feature cell64is configured to detect the letter “i”. The feature cell66is configured to both detect the letter “g” and indicate that the search criterion is satisfied.

FIG. 6also depicts additional details of the detection array34. The detection array34may include a detection cell68in each of the feature cells63,64, and66. Each of the detection cells68may include a memory cell70, such as one of the types of memory cells described above (e.g., a flip-flop), that indicates whether the feature cell63,64, or66is active or inactive. The detection cells68may be configured to output a signal to the activation-routing matrix36indicating whether the detection cells68are active and has received a signal from its associated search-term cell54indicating a match. Inactive features cells63,64, and66may disregard matches. Each of the detection cells68may include an AND gate with inputs from the memory cell70and the output conductor56. The output of the AND gate may be routed to both the detection bus38and the activation-routing matrix36, or one or the other.

The activation-routing matrix36, in turn, may selectively activate the feature cells63,64, and66by writing to the memory cells70in the detection array34. The activation-routing matrix36may activate feature cells63,64, or66according to the search criterion and which search term is being searched for next in the data stream12.

InFIG. 6, the data stream12presents the letter “b”. In response, each of the feature cells63,64, and66may output a signal on their output conductor56, indicating the value stored in the memory cell58connected to the conductor62, which represents the letter “b”. The detection cells56may then each determine whether they have received a signal indicating a match and whether they are active. Because the feature cell63is configured to detect the letter “b” and is active, as indicated by its memory cell70, the detection cell68in the feature cell63may output a signal to the activation-routing matrix36indicating that the first search term of the search criterion has been matched.

As illustrated byFIG. 7, after the first search term is matched, the activation-routing matrix36may activate the next feature cell64by writing a 1 to its memory cell70in its detection cell68. The activation-routing matrix36may also maintain the active state of the feature cell63, in case the next term satisfies the first search term, e.g., if the sequence of terms “bbig” is received. The first search term of search criteria may be maintained in an active state during a portion or substantially all of the time during which the data stream12is searched.

InFIG. 7, the data stream12presents the letter “i” to the recognition module22. In response, each of the feature cells63,64, and66may output a signal on their output conductor56, indicating the value stored in the memory cell58connected to the conductor72, which represents the letter “i”. The detection cells56may then each determine whether they have received a signal indicating a match and whether they are active. Because the feature cell64is configured to detect the letter “i” and is active, as indicated by its memory cell70, the detection cell68in the feature cell64may output a signal to the activation-routing matrix36indicating that the next search term of its search criterion has been matched.

Next, the activation-routing matrix36may activate the feature cell66, as illustrated byFIG. 8. Before evaluating the next term, the feature cell64may be deactivated. The feature cell64may be deactivated by its detection cell68resetting its memory cell70between detection cycles or the activation-routing matrix36may deactivate the feature cell64, for example.

InFIG. 8, the data stream12presents the term “g” to the row decoder28, which selects the conductor74representing the term “g”. In response, each of the feature cells63,64, and66may output a signal on their output conductor56, indicating the value stored in the memory cell58connected to the conductor74, which represents the letter “g”. The detection cells68may then each determine whether they have received a signal indicating a match and whether they are active. Because the feature cell66is configured to detect the letter “g” and is active, as indicated by its memory cell70, the detection cell68in the feature cell66may output a signal to the activation routing matrix36indicating that the last search term of its search criterion has been matched.

The end of a search criterion or a portion of a search criterion may be identified by the activation-routing matrix36or the detection cell68. These components36or68may include memory indicating whether their feature cell63,64, or66specifies the last search term of a search criterion or a component of a search criterion. For example, a search criterion may specify all sentences in which the word “cattle” occurs twice, and the recognition module may output a signal indicating each occurrence of “cattle” within a sentence to the aggregation module, which may count the occurrences to determine whether the search criterion is satisfied.

Feature cells63,64, or66may be activated under several conditions. A feature cell63,64, or66may be “always active”, meaning that it remains active during all or substantially all of a search. An example of an always active feature cell63,64, or66is the first feature cell of the search criterion, e.g., feature cell63.

A feature cell63,64, or66may be “active when requested”, meaning that the feature cell63,64, or66is active when some condition precedent is matched, e.g., when the preceding search terms in a search criterion are matched. An example is the feature cell64, which is active when requested by the feature cell63inFIGS. 6-8, and the feature cell66, which is active when requested by the feature cell64.

A feature cell63,64, or66may be “self activated”, meaning that once it is activated, it activates itself as long as its search term is matched. For example, a self activated feature cell having a search term that is matched by any numerical digit may remain active through the sequence “123456xy” until the letter “x” is reached. Each time the search term of the self activated feature cell is matched, it may activate the next feature cell in the search criterion. Thus, an always active feature cell may be formed from a self activating feature cell and an active when requested feature cell. The self activating feature cell may be programmed with all of its memory cells58storing a 1, and it may repeatedly activate the active when requested feature cell after each term. In some embodiments, each feature cell63,64, and66may include a memory cell in its detection cell68or in the activation-routing matrix36that specifies whether the feature cell is always active, thereby forming an always active feature cell from a single feature cell.

FIG. 9depicts an example of a recognition module22configured to search according to a first search criterion75and a second search criterion76in parallel. In this example, the first search criterion75specifies the word “big”, and the second search criterion76specifies the word “cab”. A signal indicative of the current term from the data stream12may be communicated to feature cells in each search criterion75and76at generally the same time. Each of the input conductors37spans both of the search criteria75and76. As a result, in some embodiments, both of the search criteria75and76may evaluate the current term generally simultaneously. This is believed to speed the evaluation of search criteria. Other embodiments may include more feature cells configured to evaluate more search criteria in parallel. For example, some embodiments may include more than 100, 500, 1000, 5000, or 10,000 feature cells operating in parallel. These feature cells may evaluate hundreds or thousands of search criteria generally simultaneously.

Search criteria with different numbers of search terms may be formed by allocating more or fewer feature cells to the search criteria. Simple search criteria may consume fewer resources in the form of feature cells than complex search criteria. This is believed to reduce the cost of the pattern-recognition processor14(FIG. 2) relative to processors with a large number of generally identical cores, all configured to evaluate complex search criteria.

FIGS. 10-12depict both an example of a more complex search criterion and features of the activation-routing matrix36. The activation-routing matrix36may include a plurality of activation-routing cells78, groups of which may be associated with each of the feature cells63,64,66,80,82,84, and86. For instance, each of the feature cells may include 5, 10, 20, 50, or more activation-routing cells78. The activation-routing cells78may be configured to transmit activation signals to the next search term in a search criterion when a preceding search term is matched. The activation-routing cells78may be configured to route activation signals to adjacent feature cells or other activation-routing cells78within the same feature cell. The activation-routing cells78may include memory that indicates which feature cells correspond to the next search term in a search criterion.

As illustrated byFIGS. 10-12, the recognition module22may be configured to search according to complex search criteria than criteria that specify single words. For instance, the recognition module22may be configured to search for words beginning with a prefix88and ending with one of two suffixes90or92. The illustrated search criterion specifies words beginning with the letters “c” and “l” in sequence and ending with either the sequence of letters “ap” or the sequence of letters “oud”. This is an example of a search criterion specifying multiple target expressions, e.g., the word “clap” or the word “cloud”.

InFIG. 10, the data stream12presents the letter “c” to the recognition module22, and feature cell63is both active and detects a match. In response, the activation-routing matrix36may activate the next feature cell64. The activation-routing matrix36may also maintain the active state of the feature cell63, as the feature cell63is the first search term in the search criterion.

InFIG. 11, the data stream12presents a letter “l”, and the feature cell64recognizes a match and is active. In response, the activation-routing matrix36may transmit an activation signal both to the first feature cell66of the first suffix90and to the first feature cell82of the second suffix92. In other examples, more suffixes may be activated, or multiple prefixes may active one or more suffixes.

Next, as illustrated byFIG. 12, the data stream12presents the letter “o” to the recognition module22, and the feature cell82of the second suffix92detects a match and is active. In response, the activation-routing matrix36may activate the next feature cell84of the second suffix92. The search for the first suffix90may die out, as the feature cell66is allowed to go inactive. The steps illustrated byFIGS. 10-12may continue through the letters “u” and “d”, or the search may die out until the next time the prefix88is matched.

In some embodiments, such as that illustrated inFIG. 13, the pattern-recognition processor14may be part of a device93accessed by a controller or some other device or system, such as a host computer system94. The computer system94may include, for example, a processor, such as a central processing unit (CPU)20, that accesses a memory95via a memory management unit (MMU)96. The memory95may include any suitable memory device, including, but not limited to, static random access memory (SRAM), dynamic random access memory (DRAM), or a generation of Double Data Rate (DDR) memory (e.g., DDR1, DDR2, DDR3, or DDR4). Further, the MMU96may be provided in a separate hardware component of the system94, such as a northbridge of a motherboard chipset, or may be integrated into the CPU20. Although device93is presently illustrated as separate from the computer system94, it will be appreciated that some or all of the components of the device93and the computer system94, including, but not limited to, those explicitly illustrated inFIG. 13and discussed herein, may be integrated into a single device.

As described further below, in some embodiments the pattern-recognition processor14, or the device94having the pattern-recognition processor14, may include a plurality of registers97to store information related to the pattern-recognition system described above. To facilitate reading and writing data to and from the registers97, register access logic98may manage the access to the registers97. The register access logic98may be implemented in hardware, or in any other suitable manner. In various embodiments, the registers97and/or register access logic98may be a part of the pattern recognition processor14, or may be separate from but accessible by the pattern recognition processor14.

The plurality of registers97may include registers that store matching results, counts, configuration information, control information and status, debug information, etc. Any desirable information related to the pattern recognition process described above may be stored in the registers97. The large quantity of data that may be stored in the registers97may result in a relatively large number of registers.

The MMU96may use an address map99, which includes physical memory addresses directly accessible by the CPU20, to facilitate direct access by the CPU20to various memory locations, such as within the memory95and the registers97. The address map99, however, may have a finite number of addresses that can be mapped to physical memory locations of the system94and other devices, such as device93. For instance, in some embodiments, the system94may include a 32-bit address bus that allows 232distinct addresses to be mapped to physical memory locations in the address map99. In such an embodiment, and given an address space of a fixed size, the number of addresses that may be mapped to physical locations in the memory95is inversely related to the number of addresses mapped to physical locations outside the memory95, such as in the registers97. For instance, if each address is mapped to a one-byte physical memory location, 232available addresses could be mapped to, and allow direct access by the CPU20of, 4 GB of memory. If a substantial number of addresses within the address map99were allocated to the registers97, fewer addresses would be available for mapping to the memory95, which may reduce the amount of memory95accessible to the CPU20and result in decreased performance of the system94. In some embodiments, address space of the system94and the address map99may be conserved through the indirect addressing techniques discussed below.

In accordance with certain embodiments of the present invention, a majority of the registers97may be indirectly accessible by the system94(and not included within the address space of the system94or address map99), while a specific subset of registers97may be directly accessible by, and included within the memory space of, the system94. These two types of registers may be referred to as “indirect registers” and “direct registers,” respectively. That is, in order to preserve memory address space of a processing system, such as the system94, a large number of registers may be logically and/or physically located such that they are not directly accessible by the processing unit. These registers may be of any desired size, such as 8-bit registers, 16-bit registers, 32-bit registers, 36-bit registers, 64-bit registers, or the like.

In one embodiment, the device93includes a separate address map101that may be used to facilitate access to physical locations of the registers97, and that generally provides a map to the indirect registers not included in the address map99of the system94. As discussed further below, the direct registers also allow access to the indirect registers, and can be used to funnel all requests for access to the indirect registers through the easily accessed direct registers. The direct registers allow rapid access by the system94(e.g., by the CPU20), yet restriction of the direct registers to a subset of the registers97reduces the amount of memory address space within system94used for the registers97. Additionally, in some embodiments, various techniques may speed up accesses to the indirect registers, reducing any system slowdowns caused by accessing these indirect registers. While the indirect addressing technique disclosed herein may be employed in conjunction with a pattern-recognition processor in some embodiments, such indirect addressing may also be used in other embodiments that do not include such a pattern-recognition processor.

FIG. 14illustrates a system100having direct and indirect registers of the pattern recognition processor14in accordance with an embodiment of the present invention. The system100includes a direct register set (or group)102(also referred to as a “base register set”), and an indirect register set (or group)104. The base register set102may include any number of “critical” registers, that is, those registers where direct accessibility by the system94(or some other controller, system, or device) is most desired. In the embodiment illustrated inFIG. 14, the base register set102includes six registers, although in other embodiments any number of registers may be used in the base register set102. Further, it should be appreciated that selection of the “critical” registers used in the base register set102is configurable based on the pattern recognition processor14and the system. Thus, in other embodiments, some of the registers of the base register set102inFIG. 14may be omitted and other registers may be included in the base register set102.

In the illustrated embodiment, the base register set102includes the following registers: a critical status register106; a critical control register108; a stimulus byte input register110, an indirect bank select register112; an indirect address select register114; and an indirect data in/out register116. In one embodiment, each register of the base register set102may be a 32-bit register, and may be accessible over a 32-bit address bus. Further, the registers of the register set102may be read/write registers, allowing both reads and writes. As described further below, the indirect bank select register112, the indirect address select register114, and the indirect data in/out register116aid in accessing the indirect registers104. These three registers112,114, and116may collectively be referred to as the “indirect addressing access registers.”

The critical status register106, the critical control register108, and the stimulus byte input register110provide access to functions and information that may be quickly accessed by the system94or some other controller, preventing the access delay associated with providing these functions and information via the indirect registers104. The critical control register108provides critical control bits during the pattern matching operation when speed of processing is critical. For example, such bits may include stop/run, reset, DMA start/stop, mode selection, etc. Any other critical control bits may be used in the critical control register108.

The critical status register106provides critical status information during the pattern matching operation. The status information bits stored in the register106may be “sticky” bits (updated only when explicitly requested), may be “auto-updated,” or may never be updated. Examples of status bits stored in the register106may include endian-mode, endian-ness selection, DMA mode, DMA status, status of matches, detection of matches, etc.

The stimulus-byte input register110provides storage of the data to be searched from the data stream12. Storing the data in the stimulus-byte input register110allows parallel functions to occur, speeding up operation of the pattern recognition processor14. For example, data from the data stream12can be processed at the same time as reading of indirect “match results” bank registers.

The indirect register set104may include any number of register banks118comprising one or more registers120. Various types of indirect register groups are described below. However, it should be appreciated that the groups described are merely exemplary and any other registers, register groups, and/or register banks may be included. The indirect register set104may include a flow save and restore group122, a match result and debug group124, a power-on configuration group126, and a pattern configuration group128. The flow save and restore group122may include status indicators and counter values, such as threshold counters, processed byte counters, etc. The match results and debug group124may include group logic outputs, recognition array outputs, and any other results and outputs. The power-on configuration group126includes registers identifying and configuring the pattern recognition processor14, such as device capabilities, manufacturer identification codes, system parameters, etc. Finally, the pattern configuration group128includes functions and information used with the pattern recognition process, such as recognition array state, aggregation functions, etc.

In some embodiments, accessing an indirect register may require three or more bus cycles, such as selecting a register bank, selecting an indirect register within the bank, and then writing or receiving data to or from the indirect register. In accordance with an embodiment of the present invention, however, the indirect addressing access registers112,114, and116provide a system for decreasing access time to the indirect register set104. The indirect bank select register112selects the bank118of the indirect register set104to be accessed. Each of the various banks118may be selected by a specific address value, as indicated by a bank select bus line119. In one embodiment, the indirect bank select register112may be a 32-bit register. As described in more detail below, some bits of the indirect bank select register112may be used to select the “auto-change address mode” for the selected register bank. Additionally, writing to the indirect bank select register112may automatically set the indirect address select register114to a predetermined value. In one embodiment, such writing may automatically reset the indirect address select register114to zero (e.g., 0x00000000h for a 32-bit register).

The indirect address select register114sets the specific register120to be accessed within the bank of registers selected by the indirect bank register select112, as indicated by register address bus121. In each selected bank, the registers start at a zero address. In some embodiments, because the indirect address select register114is set to zero after writing to the indirect bank select register112, the indirect address select register114may be written with the desired address after the indirect bank select register112is written. As described further below, the indirect address select register114is capable of “auto-increment,” “auto-decrement,” “auto-reset,” and “no change” modes (referred to as “auto-change address modes”) that increase performance when doing successive reads or writes to consecutive register addresses.

The indirect data in/out register116provides the write or read functionality for the indirect register set104, as indicated by the register data in/out bus123. Writing to the indirect data in/out register116writes data into the register at the address specified by the indirect bank select register112and the indirect address select register114. Reading from the indirect data in/out register116reads the register at the address specified by the combination of the indirect bank select register112and the indirect address select register114. Thus, by using the indirect bank select register112, the indirect address select register114, and the indirect data in/out register116, data may be written to or read from the indirect registers104.

Because accessing each of the indirect registers104requires accessing the registers112,114, and116, access to the indirect registers104may be appreciably slower than accessing the direct registers102. As mentioned above, to speed up access to the banks of the indirect register set104, the pattern recognition processor14and the register logic96may utilize one or more auto-change address modes. In one embodiment, the auto-change address mode may be set via one or more bits of the indirect bank select register112. These bits may be referred to as “auto change address bits.” In other embodiments, any register may be used to set and store the auto change address bits.

The auto-change address modes may include various modes to speed up access to consecutive registers of the banks118of the indirect registers104, or may include modes to quickly reset the indirect address select register114. In one embodiment, these modes may include an “auto-increment” mode, an “auto-decrement” mode, and an “auto-reset” mode. Additionally, a “no-change” mode may be selected.

In the auto-increment mode, the currently accessed register address specified by the indirect address select register114is incremented at the completion of the current indirect data in/out register bus cycle. Similarly, in the auto-decrement mode, the currently accessed register address specified by the indirect address select register114is decremented at the completion of the current indirect data in/out register bus cycle. If the auto-reset mode is selected, the indirect address select register114is set to a predetermined value (e.g., zero in an “auto-reset-to-zero” mode) at the completion of the current cycle. If the no change mode is selected, no change is made to the currently selected register address specified by the indirect address select register114at the completion of the current cycle. The auto-change address modes for the embodiment described above are summarized in Table 1.

It should be appreciated that various embodiments may include any one or more of the auto-change address modes described above. In other embodiments, any other auto-change address modes that modify a currently accessed register address may be implemented, including logical operators (such as AND, OR, XOR, and the like), HASH functions, etc.

FIGS. 15A-Cillustrate operation of the auto-increment mode of the auto-change address modes described above in accordance with an embodiment of the present invention.FIGS. 15A-Cdepict a register bank130having a plurality of registers132, such as may be included in the indirect register set104. As described above, writing to the indirect bank select register112sets the address of the desired register bank130, the auto-change address bits that indicate the auto-change address mode, and resets the indirect address select register114to a predetermined address, such as zero. Thus, to setup indirect access to the bank130and registers132, only one write cycle is needed, as opposed to separate write cycles, to first write to the indirect bank select register112, determine the auto change address mode, and then select the indirect address register114as zero, for example.

After writing to the indirect bank select register112to select the bank130, data may be written to or read from the indirect data in/out register116if the indirect register address <0> is the desired indirect register of the selected bank130. If a different indirect register needs to be accessed, then the indirect address select register114is written to with the desired register address to select a specific register. For example, as shown inFIG. 15A, a first register134of the bank130having a address of “<address>” may be selected through the indirect bank select register112and the indirect address select register114. After selecting the register134, data may be written to or read from the indirect data in/out register116.

In auto-increment mode, the current register address “<address>” set in the indirect address select register114automatically increments after writing the first register134, as illustrated by arrow136inFIG. 15B. The next write cycle writes to a second register138having a register address of “<address>+1.” Thus, the next register138is written without having to rewrite to the indirect bank select register112or the indirect address select register114. Similarly, the next write cycle, as illustrated inFIG. 15C, increments the currently selected address “<address>+1” by one, as illustrated by arrow140. The next write writes to a third register142having a register address of “<address>+2.” The writing cycles continue writing to incremented register addresses until the end of the bank130. The auto-increment mode allows bursts of accesses to successive registers134,138,142, and so on, increasing the speed of writing or reading large banks of indirect registers.

FIGS. 16A-Cillustrate operation of the auto-decrement mode of the auto-change address modes on the bank130and bank registers132in accordance with an embodiment of the present invention. As described above, writing to the indirect bank select register112sets the register bank130to be written, the auto-decrement mode via the auto-change address bits, and resets the indirect address select register114to zero (or some other predetermined value). After the indirect bank select address112is set, the indirect address select register114is set to select a specific register, such as the register146having an address of “<address>.” For example, as shown inFIG. 16A, a first register146of the bank130may be written by writing to the indirect data in/out register116. In auto-decrement mode, the current register address “<address>” automatically decrements by one address value after writing the first register146, as illustrated by arrow148inFIG. 16B. The next write cycle writes to a second register150having a register address of “<address>−1.” After this write cycle, the currently selected register address “<address>−1” is decremented by one address value, as indicated by arrow152inFIG. 15CThe next write cycle writes to a third register154having a register address of “<address>−2.”Successive write cycles continually decrement the currently selected indirect register address until the end of the bank130. As with the auto-increment mode, the auto-decrement mode provides for reading or writing data to registers132in bursts of accesses to successive registers146,150,154, and so on, increasing the speed of writing or reading large banks of registers.

The additional auto-change address modes referred to above, auto-reset mode and no change, may be used when no increment or decrement functionality is desired. For example, the no-change mode may be used if the currently accessed register is a status, interrupt, or other function having only one register in a bank, such that no burst read or writes are desired. An “auto-reset-to-zero” mode may be used when the indirect register address <0> is frequently read or written, but another indirect register is occasionally read or written.

FIG. 17depicts a process200for writing to or reading from the indirect registers104in accordance with an embodiment of the present invention. A write or read operation begins by writing the desired bank address to the indirect bank select register112(block202). In the present embodiment, writing the indirect bank select register112sets the indirect address select register114to zero, e.g., 0x00000000h for a 32-bit register (block204). The auto-change address mode is set by the dedicated auto-change address mode bits written to the indirect bank address register112(block206). As illustrated in theFIG. 17, the blocks202,204, and206occur in one write cycle, as indicated by dashed area208. That is, the write to the indirect bank select register112results in automatic execution of the blocks204and206of the process200.

The specific register address to be written, referred to as “<address>,” is written to the indirect address select register114(block210). Data is written to or read from the register at “<address>,” depending on the requested operation, via the indirect data in/out register116(block212).

The auto-change address mode received from the indirect bank select register112then determines if the currently accessed register address <address> is modified. If the auto-change address mode is auto-increment mode, as indicated by arrow214, the “<address>” of the current register address increments by one (block216). The next successive register in the selected bank is written or read (block218). If the end of the bank has not been reached (decision block220), the process200may continue to increment the current address at block216until the end of the bank. It should be appreciated that the auto-decrement mode functions similarly, except the current register address “<address>” decrements by one in block216. In one embodiment, various further actions may be taken (block222) if the end of the bank has been reached. By way of example, in one embodiment, further writing to the selected register bank may be prevented and an error condition may be indicated if another write is attempted. In other embodiments, the current address may be reset to the first address (in auto-increment mode) or last address (in auto-decrement mode) of the selected bank, the selected bank in the indirect bank select register112may be incremented or decremented (depending on the current auto-change mode), some other action may be taken, or some combination of these actions may be performed. For instance, in an auto-increment mode, once the end of a bank is reached, the indirect bank select register value may be incremented, and the indirect address select register value may be set to zero or some other value.

Alternatively, if the auto-change address mode is the return-to-zero mode as indicated by arrow224, the indirect address select register is reset to zero, e.g., 0x00000000h for a 32-bit register (block226). If the auto-change address mode is no-change, as indicated by arrow228, then no change is made to the indirect address select register (block230), e.g., the indirect address select register remains set at the current register address “<address>.”