Hall sensors with a three-dimensional structure

Structures for a Hall sensor and methods of forming a structure for a Hall sensor. The structure includes a semiconductor body having a top surface and a sloped sidewall defining a Hall surface that intersects the top surface. The structure further includes a well in the semiconductor body and multiple contacts in the semiconductor body. The well has a section positioned in part beneath the top surface and in part beneath the Hall surface. Each contact is coupled to the section of the well beneath the top surface of the semiconductor body.

BACKGROUND

The present invention relates to integrated circuits and semiconductor device fabrication and, more specifically, to structures for a Hall sensor and methods of forming a structure for a Hall sensor.

Hall sensors are common types of sensing components found in various commercial products, such as household appliances, gaming systems, construction equipment, utility meters, and motor vehicles, and are based on sensing a magnetic field. A magnetic field is a vector quantity characterized by a position-dependent field strength and a field direction. A magnetic field may exert a force on moving charged particles according to the Lorentz force law. A Hall sensor relies on the production of a voltage difference (i.e., a Hall voltage) across an electrical conductor produced by a combination of a current flowing in the conductor and a magnetic field with a field direction perpendicular to the flowing current. Conventional Hall sensors, which are planar devices, have a low sensitivity when detecting a magnetic field with a field direction that is parallel to a substrate surface on which the Hall sensor is formed.

Improved structures for a Hall sensor and methods of forming a structure for a Hall sensor are needed.

SUMMARY

According to an embodiment of the invention, a structure for a Hall sensor is provided. The structure includes a semiconductor body having a top surface and a sloped sidewall defining a Hall surface that intersects the top surface. The structure further includes a well in the semiconductor body and multiple contacts in the semiconductor body. The well has a section positioned in part beneath the top surface and in part beneath the Hall surface. Each contact is coupled to the section of the well beneath the top surface of the semiconductor body.

According to another embodiment of the invention, a method of forming a structure for a Hall sensor is provided. The method includes forming a well in a semiconductor body having a top surface and a sloped sidewall defining a Hall surface that intersects the top surface. The well has a section positioned in part beneath the top surface and in part beneath the Hall surface. The method further includes forming multiple contacts in the semiconductor body. Each contact is coupled to the section of the well beneath the top surface of the semiconductor body.

DETAILED DESCRIPTION

With reference toFIGS. 1, 2and in accordance with embodiments of the invention, a groove10is formed as a cavity or trench in a substrate12. The substrate12may be a bulk wafer composed of single-crystal semiconductor material (e.g., single-crystal silicon) and, in an embodiment, the substrate12may have lightly-doped p-type conductivity. In an embodiment, the groove10may be formed by lithography and etching processes. To that end, an etch mask14is formed over a top surface of the substrate12. The etch mask14may be a hardmask that is patterned by lithography and etching processes to define an opening of a given area at an intended location for the groove10. The groove10is etched in the substrate12using one or more etching processes with the etch mask14present. Portions of the substrate12that are not covered by the etch mask14are removed by the etching process.

The groove10in the substrate12may have a cross-sectional profile produced through a choice of etchant. In an embodiment, the groove10may have a V-shaped cross-sectional profile. For example, the etchant may be a wet chemical etchant, such as a solution containing tetramethylammonium hydroxide (TMAH), a solution containing potassium hydroxide (KOH), or a solution containing ethylene diamine and pyrocatechol (EDP). The etchant may exhibit selectivity with regard to crystal orientation of the semiconductor material of the substrate12with different etching rates occurring along different crystalline directions. The differential in the etching rates produces the shape for the groove10. For example, if the substrate12contains [100]-oriented silicon, the (100) planes etch at a significantly higher rate than the (111) planes which leads to a self-limiting etching process forming the groove10in which the vertical etch rate is significantly greater than the lateral etch rate.

The cross-sectional profile of substrate12surrounding the groove10includes sidewalls16that extend from a top surface11of the substrate12to a surface of the substrate at the groove bottom18. The sidewalls16define surfaces that are angled or sloped relative to a plane containing a top surface11of the substrate12. In an embodiment in which the substrate12contains [100]-oriented silicon having a diamond crystal lattice, the sidewalls16may be sloped relative to the plane containing the top surface11with an inclination angle of about 35° consistent with the angle of a normal to the [111] planes relative to the [100] surface normal. The sidewalls16penetrate from the top surface11of the substrate12to a given depth into the substrate12and intersect with the groove bottom18, which is laterally arranged between the opposite sidewalls16.

A surface of the substrate12, which is exposed at the groove bottom18, may be contained in a plane that is parallel to a plane containing the top surface11of the substrate12. Each of the sidewalls16intersects the surface at the groove bottom18at a corner17that extends along a lower edge of the sidewall16. The respective corners17are located along opposite sides of the groove bottom18, which extends laterally from one corner17to the opposite corner17. Each of the sidewalls16also intersects the top surface11of the substrate12at a corner15that extends along an upper edge of the sidewall16. The surface of the substrate12at the groove bottom18may be rectangular about a perimeter defined by the corners17, and the top surface11of the substrate12surrounding the entrance to the groove10may likewise have a rectangular shape about a perimeter defined by the corners15.

With reference toFIGS. 3, 4in which like reference numerals refer to like features inFIGS. 1, 2and at a subsequent fabrication stage, the etch mask14is removed, and shallow trench isolation regions20are formed that surround the groove10. The shallow trench isolation regions20may contain a dielectric material, such as silicon dioxide, that is deposited by chemical vapor deposition into trenches etched in the substrate12by a masked etching process, polished, and deglazed. The shallow trench isolation regions20are slight larger dimensionally (e.g., in length and width) than the groove10such that the corners15are surrounded by the shallow trench isolation regions20. Because of the dimensional difference, portions13of the substrate12are located as strips at the top surface11between the corners15and the shallow trench isolation regions20. The top surface11of these portions13of the substrate12may be flat and planar.

Wells22,24having conductivity types of opposite polarity are formed in the substrate12beneath the surfaces at the sidewalls16and in the portions13of the substrate12beneath the top surface11. The well22may be formed by introducing a dopant of one conductivity type by, for example, ion implantation into a portion of the substrate12beneath each sidewall16of the groove10and into the portions13of the substrate12surrounding the groove10. The well24may be formed by introducing a dopant of the opposite conductivity type by, for example, ion implantation into portions of the substrate12beneath each sidewall16and into the portions13of the substrate12surrounding the groove10. Respective patterned implantation masks may be used to define the selected locations for the wells22,24, and are stripped after each of the wells22,24is formed. In an embodiment, the well22may be formed before the formation of well24.

In an embodiment, the semiconductor material of the well22may comprise an n-type dopant (e.g., phosphorus or arsenic) effective to impart n-type conductivity, and the semiconductor material of well24may comprise a p-type dopant (e.g., boron) effective to impart p-type conductivity. Implantation conditions (e.g., kinetic energy and dose) are selected to form each of the wells22,24with a desired doping profile and concentration. In an embodiment, the wells22,24may be constituted by moderately-doped semiconductor material formed through a selection of the implantation conditions. The wells22,24, which are located beneath the top surface11, each extend to a given depth into the substrate12relative to the top surface11. In an embodiment, the wells22,24may extend to equal depths into the substrate12relative to the top surface11.

The well22includes sections26,28that extend as strips in the substrate12down the sidewalls16of the groove10and that are also located in the portions13of the substrate12. The well22also includes a section30that extends as a strip in the substrate12down the sidewalls16of the groove10and that is also located in the portions13of the substrate12at the top surface11. The section30may have larger dimensions than either of the sections26,28. The well24also includes sections32,34as strips extend down the sidewalls16of the groove10and that are also located in the portions13of the substrate12at the top surface11. The section32of well24is positioned laterally between the section26and section30of well22, and the section34of well24is positioned laterally between the section28and section30of well22.

The surface of the substrate12at the groove bottom18is masked during both implantations forming the wells22,24and therefore the portion of the substrate12beneath the groove bottom18retains its original conductivity (e.g., lightly-doped p-type conductivity). The wells22,24terminate at the corners17because the surface of the substrate12at the groove bottom18is masked during the implantations forming the wells22,24. Portions of the sidewalls16peripheral to the sections26,28may also be masked during the implantation forming the well22and during the implantation forming the well24. Therefore, the substrate12beneath these portions of the sidewalls16also retain the original conductivity of the substrate12. The wells22,24may contain moderately-doped semiconductor material.

With reference toFIGS. 5, 6in which like reference numerals refer to like features inFIGS. 3, 4and at a subsequent fabrication stage, processing continues in parallel to form respective Hall sensors on each of the sidewalls16. The subsequent discussion will address the formation of the Hall sensor on one of the sidewalls16with an understanding that another Hall sensor is being formed on the other of the sidewalls16.

A doped region36is formed in a portion of the section30of the well22, and contacts38,40are formed as discrete doped regions in the doped region36. The contacts38,40have a conductivity type of an opposite polarity from the doped region36. The doped region36and the contacts38,40are located in the portion13of the substrate12. The doped region36extends to a shallower depth into the substrate12than the well22such that a portion of the well22is retained beneath the doped region36. The contacts38,40are coupled to the portion of the well22beneath the doped region36, which in turn couples the contacts38,40with the section30of the well22beneath the sidewall16. A portion of the doped region36is positioned between the contact38and the contact40to provide electrical isolation. The doped region36has the same conductivity type but a higher dopant concentration than the sections32,34.

Contacts42,44are respectively formed as doped regions in the portions of the sections26,28of the well22that are located in the portions13of the substrate12at the top surface11. The contacts42,44have the same conductivity type as the sections26,28but with a higher dopant concentration, and are respectively coupled to the sections26,28of the well22. Contacts46,48are respectively formed as doped regions in the portions of the substrate12at the groove bottom18. Contact46couples the section26of the well22with the section30of the well22. Contact48couples the section28of the well22with the section30of the well22. The contacts46,48have the same conductivity type as the sections26,28but with a higher dopant concentration. A doped region50is also formed in the portion of the substrate12exposed at the groove bottom18. The doped region50has an opposite conductivity type from the contacts46,48.

The doped regions36,50may be formed by introducing a dopant by, for example, ion implantation at selected locations in the substrate12. A patterned implantation mask may be used to define the selected locations for the doped regions36,50and is stripped after implantation. In an embodiment in which the well22is n-type semiconductor material and the well24is p-type semiconductor material, the semiconductor material constituting the doped regions36,50may contain a p-type dopant effective to impart p-type conductivity and may be heavily doped. Implantation conditions are selected to form each of the doped regions36,50with a desired doping profile and concentration.

The contacts38,40,42,44,46,48may be formed by introducing a dopant by, for example, ion implantation at selected locations in the substrate12. A patterned implantation mask may be used to define the selected locations for the contacts38,40,42,44,46,48and is stripped after implantation. In an embodiment in which the well22is n-type semiconductor material and the well24is p-type semiconductor material, the semiconductor material constituting the contacts38,40,42,44,46,48may contain an n-type dopant effective to impart n-type conductivity and may be heavily doped. Implantation conditions are selected to form each of the doped regions36,50with a desired doping profile and concentration.

The portion of the section30of the well22beneath the sidewall16is bounded by the doped region36, the doped region50, the sections32of well24, and the section34of well24. These boundaries define a Hall surface35of a given area (e.g., length and width) at the surface of the sidewall16. The Hall surface35may extend over the full height of the sidewall16from the corner15to the corner17, and the Hall surface35has a width, w, extending from one of the sections32of well24to the opposite one of the sections34of well24. The Hall surface35is contained in a plane that is sloped with an inclination relative to the top surface11of the substrate12and that has a vertical component relative to a plane containing the top surface11of the substrate12.

In the representative embodiment, the groove10is etched in the substrate12before the wells22,24of opposite conductivity types are formed in substrate12. In an alternative embodiment, the groove10may be etched in the substrate12after the wells22,24of opposite conductivity types are formed in substrate12, followed by the formation of the doped regions36,50and the contacts38,40,42,44,46,48.

In use, a bias potential may be applied between terminals provided by the contact38and the contact44to establish a current flowing in the well22. A magnetic field with a field direction that intersects the Hall surface35at the sidewall16will produce a Hall voltage. The Hall surface35defines the sensing surface of the Hall sensor. The interaction between the current and the magnetic field generates as a potential difference that is sensed between terminals provided by the contact42and the contact40at the Hall voltage. Due to the sloping of the sidewalls16that provides a non-planar geometry, the Hall sensor may sense a magnetic field characterized by a field direction that is parallel or nearly parallel to the top surface11of the substrate12with a greater sensitivity than a conventional Hall sensor.

With reference toFIG. 7in which like reference numerals refer to like features inFIG. 5and in accordance with alternative embodiments, the Hall sensor may be formed using a semiconductor fin64projecting from the top surface11of the substrate12, instead of the groove10that is recessed relative to the top surface11of the substrate12as a cavity. The sidewalls66of the semiconductor fin64and the top surface68of the semiconductor fin64may be used to form the wells22,24, the doped regions36,50, and the contacts38,40,42,44,46,48of the Hall sensor. Similar to the sidewalls16of the groove10, the sidewalls66of the semiconductor fin64are inclined or angled relative to a plane containing the top surface11of the substrate12. A portion of the top surface11of the substrate12surrounds a base of the semiconductor fin64. The top surface68of the semiconductor fin64may be contained in a plane that is parallel to a plane of the top surface11of the substrate12. Each of the sidewalls66intersects the top surface68at a corner62that extends along an upper edge of the sidewall66. Each of the sidewalls66also intersects the top surface11of the substrate12at a corner60that extends along a lower edge of the sidewall66. The top surface68of the semiconductor fin64may be rectangular at the corners62, and the semiconductor fin64may have a similar rectangular shape at the corners62.

The Hall surface35may extend over the full height of each sidewall66from the corner15to the corner17, and the Hall surface35has a width extending from one of the sections32of well24to the opposite one of the sections34of well24. The Hall surface35is contained in a plane that is sloped with an inclination relative to the top surface68of the semiconductor fin64and that has a vertical component relative to a plane containing the top surface68of the semiconductor fin64.