Resistive memory device

The invention is notably directed to a resistive memory device comprising a control unit for controlling the resistive memory device and a plurality of memory cells. The plurality of memory cells includes a first terminal, a second terminal and a phase change segment comprising a phase-change material for storing information in a plurality of resistance states. The phase change segment is arranged between the first terminal and the second terminal. The phase change material consists of antimony. Furthermore, at least one of the dimensions of the phase change segment is smaller than 15 nanometers. Additional implementations of the resistive memory device include a related method, a related control unit, a related memory cell and a related computer program product.

BACKGROUND

The invention is directed to a resistive memory device comprising a plurality of memory cells, and a related method, a related control unit, a related memory cell, and a related computer program product.

Nanoscale memory devices, whose resistance depends on the history of the electric signals applied, could become critical building blocks in new computing paradigms, such as brain-inspired computing and memcomputing. However, there are key challenges to overcome, such as the high programming power required, noise and resistance drift.

One promising example for resistive memory devices are phase-change memory (PCM) devices. PCM is a non-volatile solid-state memory technology that exploits the reversible, thermally-assisted switching of phase-change materials, in particular chalcogenide compounds such as GST (Germanium-Antimony-Tellurium), between states with different electrical resistance. The fundamental storage unit (the “cell”) can be programmed into a number of different states, or levels, which exhibit different resistance characteristics. The s programmable cell-states can be used to represent different data values, permitting storage of information.

In single-level PCM devices, each cell can be set to one of s=2 states, a “SET” state and a “RESET” state, permitting storage of one bit per cell. In the RESET state, which corresponds to an amorphous state of the phase-change material, the electrical resistance of the cell is very high. By heating to a temperature above its crystallization point and then cooling, the phase-change material can be transformed into a low-resistance, fully-crystalline state. This low-resistance state provides the SET state of the cell. If the cell is then heated to a high temperature, above the melting point of the phase-change material, the material reverts to the fully-amorphous RESET state if rapidly cooled afterwards. In multilevel PCM devices, the cell can be set to s>2 programmable states permitting storage of more than one bit per cell. The different programmable states correspond to different relative proportions of the amorphous and crystalline phases within the volume of phase-change material. In particular, in addition to the two states used for single-level operation, multilevel cells exploit intermediate states in which the cell contains different volumes of the amorphous phase within the otherwise crystalline PCM material. Since the two material phases exhibit a large resistance contrast, varying the size of the amorphous phase within the overall cell volume produces a corresponding variation in cell resistance.

Reading and writing of data in PCM cells is achieved by applying appropriate voltages to the phase-change material via a pair of electrodes associated with each cell. In a write operation, the resulting programming signal causes Joule heating of the phase-change material to an appropriate temperature to induce the desired cell-state on cooling. Reading of PCM cells is performed using cell resistance as a metric for cell-state. An applied read voltage causes current to flow through the cell, this current being dependent on the resistance of the cell. Measurement of the cell current therefore provides an indication of the programmed cell state. A sufficiently low read voltage is used for this resistance metric to ensure that application of the read voltage does not disturb the programmed cell state. Cell state detection can then be performed by comparing the resistance metric with predefined reference levels for the s programmable cell-states.

In spite of the success of PCM technology, reducing the RESET current and increasing the cycling endurance will have significant ramifications on the application space of this technology. The RESET current typically scales inversely with the volume of phase change material that is switched. Cycling endurance can be improved if one could avoid elemental segregation and stoichiometric variations that arise during the operation of the device. Another key challenge is that of resistance drift and noise that limits the number of resistance state one can reliably store and retrieve from the memory device.

A document by Wabe W. Koelmans, Abu Sebastian, Vara Prasad Jonnalagadda, Daniel Krebs, Laurent Dellmann & Evangelos Eleftheriou, Nature Communications, 6, 2015, Article number: 8181, introduces the concept of a projected memory device, whose distinguishing feature is that an electrically conductive segment in parallel with the phase change material can reduce the effect of resistance drift and noise in the phase change material's amorphous phase on cell read operations.

Accordingly, there is a need for further improvements of resistive memory devices.

SUMMARY

According to a first aspect, the invention is embodied as a memory device comprising a control unit for controlling the memory device and a plurality of memory cells. The plurality of memory cells comprise a first terminal, a second terminal and a phase change segment comprising a phase-change material for storing information in a plurality of resistance states. The phase change segment is arranged between the first terminal and the second terminal. The phase change material consists of antimony. Furthermore, at least one of the dimensions of the phase change segment is smaller than 15 nanometers (nm).

Such an embodied memory device uses antimony (Sb) as monoatomic phase-change material. Such an embodiment avoids elemental segregation of the phase change material and may offer advantages in terms of enhanced scalability, low operating power as well as high endurance.

Embodiments of the invention may facilitate a scaling of phase-change memory cells down to very small dimensions. Furthermore, embodiments of the invention may facilitate a lower power consumption for phase-change memory as well as an increased endurance.

To facilitate or enable the formation of phase transitions of the antimony phase change material, at least one of the dimensions of the phase change segment21is chosen to be smaller than 15 nm. In this respect, the applicant has discovered that it is possible to induce phase transitions in antimony via a melt-quench process and subsequent glass transition if one of the dimensions of the phase change segment is smaller than 15 nm. The dimension that is smaller than 15 nm can be generally any suitable dimension of the phase change segment, e.g. a thickness of the phase change segment or a diameter of the phase change segment.

A possible explanation for this newly discovered effect could be that such small dimensions effect a reduced crystallization rate due to a stabilization of the amorphous phase by the interfaces with the enclosing materials as well as a reduction in the effective thermal resistance which facilitates a very fast quench process.

According to a further embodiment at least one of the dimensions of the phase change segment is smaller than 10 nm. According to a further embodiment at least one of the dimensions of the phase change segment is smaller than 5 nm. This may further improve the amorphization during the melt-quench process and the stability of the amorphous state.

According to a further embodiment, the control unit is configured to apply in a write mode write voltages as electrical programming pulses to the first terminal and the second terminal. Furthermore, the memory cells are surrounded by a thermal environment which is designed such that during the application of the electrical programming pulses the quench-rate is sufficiently high to create an amorphous phase via a melt-quench process and to prevent its re-crystallization. According to embodiments, the memory device and in particular the thermal environment of the memory device are configured such that the temperature of the memory cells approaches the ambient temperature or at least a range of 10 degrees Celsius above the ambient temperature within 12 ns after the beginning of the trailing edge of the respective programming pulse. This facilitates that the quench-rate is sufficiently high.

According to an embodiment the control unit is configured to apply in a write mode write voltages as electrical programming pulses to the first terminal and the second terminal and a slope of the trailing edge of the programming pulses is configured such that the quench-rate is sufficiently high to create an amorphous phase via the melt-quench process and to prevent its re-crystallization.

According to an embodiment, the control unit is configured to apply in a write mode write voltages as electrical programming pulse to the first terminal and the second terminal. The electrical programming pulses have a trailing edge duration of less than 12 nanoseconds (ns).

The trailing edge duration may be defined as the time period of the trailing edge. In other words, the trailing edge duration is the time that it takes to switch/change the voltage level from an upper voltage level of the programming pulses to a lower voltage level of the programming pulses.

A trailing edge duration of less than 12 ns facilitates or enables the formation of phase transitions of the antimony phase change material. According to some embodiments, the trailing edge duration is less than 8 ns. In particular, investigations of the applicant have shown that at room temperature the electrical programming pulses should preferably have such a trailing edge duration of less than 8 ns. Further investigations of the applicant have shown that at lower ambient temperatures trailing edge durations of less than 12 ns may be sufficient to facilitate or enable the formation of phase transitions. One possible reason could be the decrease in the effective quench rate.

According to further embodiments, the trailing edge duration is less than 5 ns. This may further improve the amorphization during the melt-quench process.

According to an embodiment the memory device comprises an electrically conductive segment in parallel to the phase change segment.

Such an electrically conductive segment can be configured to provide an alternate current path during the reading of information stored in the phase change segment.

Such an electrically conductive segment can reduce the effect of resistance drift in the amorphous phase on cell read operations. The electrically conductive segment provides a parallel current path between the first terminal and the second terminal, thereby facilitating a drift-resistant operation regardless of amorphous size.

According to an embodiment, the material of the electrically conducting segment is a semiconductor material such as poly-silicon, a metal such as W or a metal nitride such as TaN, TiAlN or TiN. These materials provide good electrical properties as well as ease of manufacturing.

According to an embodiment, the phase change segment and the electrically conductive segment are arranged adjacent to each other and in electrical contact with each other over substantially the whole length between the first and the second terminal.

According to a further embodiment the control unit is configured to apply in a write mode write voltages as electrical programming pulses to the first terminal and the second terminal and the phase change material is in contact with and/or enclosed by neighboring materials which are chosen in such a way that the amorphous phase of the phase change material is stabilized against re-crystallization by the neighboring materials.

A suitable selection of such neighboring materials, which are arranged adjacent to the phase change material, may inhibit the re-crystallization of the amorphous phase. According to embodiments, poly-silicon, W, or a metal nitride such as TaN, TiAlN or TiN may be used as neighboring material. According to embodiments, the neighboring material may be the material of the electrically conductive segment.

According to an embodiment, the memory cells have a cylindrical shape. Such a geometry offers advantageous options in terms of design and scalability.

According to an embodiment, the phase change segment is formed as plain cylinder of the phase change material. Furthermore, the diameter of the cylinder is less than 15 nm.

According to an embodiment, the memory cells are formed as multilayer-cylinder.

The multilayer-cylinder comprises an inner cylinder of an insulating material and an outer cylinder forming the phase change segment and comprising the phase change material. According to this embodiment, the thickness of the outer cylinder is less than 15 nm.

According to another embodiment, the memory cells have a lamellar shape and the phase change segment is formed as a lamellar having a thickness of less than 15 nm.

According to another embodiment, the memory cells are formed as multi-layer cylinder comprising an inner cylinder forming the electrically conductive segment, a central cylinder forming the phase change segment and comprising the phase change material and an outer cylinder comprising an insulating material. According to this embodiment, the thickness of the central cylinder is the dimension of less than 15 nm.

According to another embodiment, the memory cells are formed as multi-layer cylinder comprising an inner cylinder forming the phase change segment and comprising the phase change material, a central cylinder forming the electrically conductive segment and an outer cylinder comprising an insulating material. According to such an embodiment, the thickness of the inner cylinder is the dimension of less than 15 nm.

According to a further embodiment, the memory device is configured to operate at a temperature range between 10° C. and 25° C. Accordingly, the device can be operated at room temperature. This offers possibilities for mass production and avoids any additional cooling facilities.

According to a further embodiment, the device is provided for storing information in s>2 programmable resistance states. Such multi-level memory facilitates higher memory capacities and integration densities.

According to an embodiment of a second aspect, a memory cell is provided comprising a first terminal, a second terminal and a phase change segment comprising a phase-change material for storing information in a plurality of resistance states. The phase change segment is arranged between the first terminal and the second terminal and the phase change material consists of antimony. Furthermore, at least one of the dimensions of the phase change segment is smaller than 15 nanometers.

According to an embodiment of a third aspect, a method is provided for controlling a memory device according to the first aspect. The method comprises steps of applying, by the control unit, in a read mode a read voltage to the first and the second terminal for reading the resistance state. The method further comprises a step of applying, in a write mode, a write voltage as electrical programming pulse to the first and the second terminal for writing the resistance state. The electrical programming pulse has a trailing edge duration of less than 12 ns.

According to an embodiment of a fourth aspect, a control unit is provided for controlling the operation of a memory device according to the first aspect. The control unit is configured to apply in a read mode a read voltage to the first and the second terminal for reading the resistance state and in a write mode a write voltage as electrical programming pulse to the first and the second terminal for writing the resistance state. The slope of the trailing edge of the programming pulses is configured such that the quench-rate is sufficient to prevent a crystallization of the phase change material. According to an embodiment this is achieved by an electrical programming pulse with a trailing edge duration of less than 12 ns.

According to an embodiment of fifth aspect of the invention, a computer program product is provided for operating a memory device according to the first aspect. The computer program product comprises a computer readable storage medium having program instructions embodied therewith, the program instructions executable by the control unit of the memory device to cause the control unit to perform a method according to the third aspect.

Embodiments of the invention will be described in more detail below, by way of illustrative and non-limiting examples, with reference to the accompanying drawings.

DETAILED DESCRIPTION

In reference toFIGS. 1-12, some general aspects and terms of embodiments of the invention are described.

According to embodiments of the invention, a resistive memory material may be defined as a memory material whose electrical resistance can be changed by applying an electrical signal to the resistive memory material. The electrical signal may be e.g. a current flowing through the device, or an electrical voltage applied to the resistive memory device. The current and/or voltage may be e.g. applied to the resistive memory element in the form of pulses. As a result, the electrical resistance of a resistive memory element depends on the history of current that had previously flown through the device and/or the history of the electric signal that had been applied to the resistive memory element.

Resistive memory elements are based on a physical phenomenon occurring in a material that changes its resistance under action of a current or electric field. The change is usually non-volatile and reversible. Several classes of resistive memory elements are known, ranging from metal oxides to chalcogenides. Typical resistive memory elements are metal/insulator/metal structures where the metallic components serve as the electrodes and the insulator is a resistive switching material, e.g. a chalcogenide. These resistive memory elements exhibit good performance in terms of power consumption, integration density potential, retention, and endurance.

FIG. 1is a simplified schematic block diagram of a memory device10, according to an embodiment of the present invention. The device10includes a multilevel resistive memory11for storing data in one or more integrated arrays of resistive memory cells described below. Reading and writing of data to memory11is performed by a control unit12. Control unit12comprises circuitry of generally known form for programming resistive memory cells during data write operations and making read measurements for detecting cell-state during data read operations. During these operations, the control unit can address individual resistive memory cells by applying appropriate control signals to an array of word and bit lines in the resistive memory11. User input data13to device10may be subjected to some form of write-processing, such as coding for error-correction purposes, before being supplied as write signal, in particular as write voltage, to the resistive memory11. Similarly, read signals received from the resistive memory11may be processed by a read-processing module of the control unit12, e.g. for code-word detection and/or error correction, to recover the original user input data13(output as user output data15.

The resistive memory11may be embodied as a phase change memory (PCM). Accordingly the resistive memory11comprises a plurality of PCM cells as memory cells. The PCM cells of memory11may store information in s=2 or in s>2 programmable resistance states, the latter providing multilevel operation. The s programmable resistance-states correspond to different relative proportions of the amorphous and crystalline phases within the PCM material of the cell. These states may include a high-resistance, fully-amorphous RESET state, a low-resistance, fully-crystalline SET state, and a number of intermediate states corresponding to increasing size of the amorphous phase within the otherwise crystalline PCM material. The s programmable cell-states are typically defined in control unit12in terms of predetermined reference values, or ranges of values, of the resistance metric used for read detection. To program a cell in a write operation, control unit12applies a voltage to the cell via the word- and bit-lines such that the resulting programming signal sets the cell to the required state. In a read operation, a (lower) read voltage is applied to the cell and the resulting cell current is measured to obtain the resistance metric. Control unit12can then detect the programmed cell state by comparing the read metric with the aforementioned reference values.

The PCM cells of memory11comprise antimony (Sb) as phase change material, in particular pure antimony. Accordingly the PCM cells of memory11are monoatomic memory cells that utilize a monoatomic phase-change. The advantage of using Sb is that it has the potential to be scaled to ultra-small dimensions and thus very low operating power and it may offer a very high endurance, because the use of the monoatomic antimony avoids elemental segregation. As will be described below in more detail, the use of antimony as phase change material at room temperature can be facilitated according to features of embodiments of the invention.

FIG. 2is a schematic cross-sectional view of a memory cell20, according to an embodiment of the present invention. The memory cell20comprises a phase change segment21comprising Sb as PCM material for storing information in a plurality s of resistance states which correspond to the programmable cell-states. The memory cell20further comprises an electrically conductive segment22comprising an electrically conductive or in other words electrically non-insulating material. The phase change segment21and the electrically conductive segment22are arranged in parallel between a first terminal23and a second terminal24. The first terminal23and the second terminal24are coupled to the control unit12. The control unit12is adapted to apply control signals to the first terminal23and the second terminal24and to receive read-back signals from the resistive memory11. More particularly, the control unit12is configured to apply in a write mode a write voltage to the first terminal23and the second terminal24for writing one of the plurality of resistance states to the memory cell.20. The write voltage is applied in the form of voltage pulses. The voltage pulses act or serve as electrical programming pulses to program the respective resistance state of the memory cell20. Furthermore, the control unit12is configured to apply in a read mode a read voltage to the first terminal23and the second terminal24, thereby reading the respective resistance state of the memory cell20. According to the embodiment illustrated inFIG. 2, the electrical resistance of the electrically conductive segment22has a fixed value. According to other embodiments, a tunable resistance may be used.

According to further embodiments, the resistance of the electrically conductive segment22may be tunable, e.g. by applying a control signal to a third terminal (not shown).

The phase change segment21and the electrically conductive segment22are arranged in electrical contact with each other over substantially the whole length1between the first terminal23and the second terminal24. According to embodiments the resistance of the electrically conductive segment22forms a distributed resistance.

In an exemplary implementation of cell20, the first terminal23and the second terminal24may be formed of TiN.

The memory cell20is surrounded by a thermal environment28which is schematically illustrated with a dotted line. The thermal environment28represents all the components, elements, layers etc. that surround the memory cell20including the first terminal23and the second terminal24and in particular those components, elements and layers that have a thermal influence on the melt-quench process occurring in the memory cell20during its programming. The thermal environment28can according to embodiments in particular encompass inter-cell-layers and/or inter-cell components that are arranged between the memory cell20for thermal insulation and/or other purposes as well as the first terminal23and the second terminal24.

FIG. 3is a schematic illustration30, of the current/voltage (and hence resistance) characteristics of the material components of the memory cell20(shown inFIG. 2). The solid lines indicate variation of current with voltage for the Sb material of the phase change segment21(shown inFIG. 2), starting from the fully-crystalline SET state (upper curve) and also the fully-amorphous RESET state (lower curve). These two curves reflect the large (typically 3 orders of magnitude) variation in resistivity between the crystalline and amorphous phases. The dashed line36in the plot indicates the current/voltage characteristic for the electrically conductive segment22. It can be seen that, at low voltages including the cell read voltage31, the resistance of the electrically conductive segment22is between that of the amorphous and crystalline phases of the phase change segment21(shown inFIG. 2). The amorphous phase exhibits a non-linear characteristic with a threshold switching phenomenon that is field induced. At a certain threshold voltage VTH32, this phase switches to a very low “ON-state” resistance corresponding to that of the crystalline PCM material. The cell programming (write) voltage33is selected to be above this threshold voltage as indicated. At this voltage, the ON-resistance of the phase change segment21is much less than the resistance RECSof the electrically conductive segment22. Accordingly, the write-current is substantially unaffected by the presence of the electrically conductive segment22.

Based on the above principles, preferred cell arrangements are embodied such that, at the cell read voltage, the resistance RECS36of the electrically conductive segment22is chosen such that it is far from both the resistance Ramoof the fully-amorphous (RESET) state, and also the resistance Rcry38of the fully-crystalline SET state, of the PCM37material (where “far” here means far within the context of the resistance range from Rcry38to Ramo39). In general, an appropriate value for RECS in this range will depend on various factors such as the materials and dimensions of cell components, the particular characteristics of the s programmable cell states, the operating parameters (e.g. read and write voltages) of memory device10as well as desired performance criteria such as maximum acceptable error-rate. In general, however, the arrangement is preferably such that RECS>>Rcry38and RECS36<<Ramo39within the context of the aforementioned range.

Due to resistance characteristics described above, the effect of resistance drift in the amorphous phase on cell read operations can be significantly reduced. More particularly, the ratio of currents that flows through the phase change segment21and the electrically conductive segment22can be chosen by an appropriate choice of the resistance RECS36. The electrically conductive segment22provides a full parallel current path between the terminals23,24, providing drift-resistant operation regardless of amorphous size. Moreover, any residual drift effect (due to the very small current flowing through the amorphous phase) will exhibit low variability at different cell states. By choosing the resistance of the full parallel current path the very small current flowing through the amorphous phase can be tuned and it can be ensured that current through the electrically conductive segment22will dominate as desired.

In effect, the programmed resistance state of the memory cell20can be considered to be projected onto the resistance of the electrically conductive segment22in a cell read voltage31. During the low-field read process, the current bypasses the highly resistive amorphous region of the phase change segment21and flows through that part of the electrically conductive segment22that is parallel to it. Accordingly the length of the current path through the electrically conductive segment22reflects the amorphous size and hence the programmed resistance state. In other words, the electrically conductive segment22may be considered as a projection segment during the read operation. The information that is typically stored into the length of the amorphous region in the phase change segment21is in a sense projected onto the electrically conductive segment22.

It should be noted that even though the electrically conductive segment22is present during both the read and the write operation, according to embodiments the “projection” is designed to occur only during the read process. In effect, therefore, embodiments of the invention provide a decoupling of the read process and the write process.

To facilitate or enable the formation of phase transitions of the antimony phase change material, at least one of the dimensions of the phase change segment21is smaller than 15 nm. In the embodiment illustrated inFIG. 2, the thickness d of the phase change segment21is chosen as dimensions with less than 15 nm.

In this respect, investigations of the applicant have revealed the effect that it is possible to induce phase transition via the melt-quench process and subsequent glass transition if one of the dimensions of the phase change segment21, e.g. the thickness d, is not larger than 15 nm.

A possible explanation could be that such small dimensions effect a reduced crystal growth rate in view of the reduced surface area between the crystalline and amorphous phases as well as a reduction in the effective thermal resistance which facilitates a very fast quench process.

Further investigations of the applicant have confirmed that such an amorphous phase exhibits the drift behavior that is characteristic of phase change materials. Furthermore, such an amorphous phase has been found to be stable over extended periods of time.

These investigations and studies of the applicant have resulted in the conclusion that in a Sb-based memory device, at least one of the dimensions of the phase change segment21should be smaller than 15 nm.

As mentioned above, the control unit12is configured to apply in a write mode write voltages as electrical programming pulses to the first terminal23and the second terminal24.

According to embodiments, the electrical programming pulses have a trailing edge duration of less than 12 ns.

FIG. 4illustrates a graph45, depicting an example of a programming pulse40. The x-axis400denotes the time in nanoseconds (ns) and the y-axis401the voltage in V.

The electrical programming pulse40comprises a lower voltage level41, a rising edge42, an upper voltage level43and a trailing edge44. More particularly, the electrical programming pulse has an initial lower voltage level41. The initial lower voltage level41may be in particular a voltage level of zero. From the initial voltage level41the electrical programming pulse40rises during the rising edge42from the lower voltage level41to the upper voltage level43. In this example the upper voltage level may be e.g. 4.5 V. The upper voltage level43is kept for a predefined period of time, e.g. for 40 ns. Then the electrical programming pulse40declines from the upper voltage level43to the lower voltage level41during the trailing edge44.

According to embodiments, the trailing edge duration tte403may be defined as the time period/the time interval of the trailing edge44. In other words, the trailing edge duration tte403is the time that it takes to switch/change the voltage level from the upper voltage level43of the programming pulses40to the lower voltage level41of the programming pulses40.

Referring toFIG. 4, the electrical programming pulse40starts to rise at a point in time to from the lower voltage level41and reaches at a point in time t1the upper voltage level43. Accordingly the duration tre402of the rising edge42is the time period between to46and t247.

Then at a point in time t2the electrical programming pulse40starts to decline from the upper voltage level43and reaches at a point in time t349again the lower voltage level41. Accordingly the duration tte403of the trailing edge44is the time period between t248and t349.

Investigations of the applicant with respect to the quench rate have revealed that ultra-fast quench rates facilitate or enable the formation of phase transitions of the antimony phase change material. In particular, investigations of the applicant have shown that at room temperature the electrical programming pulses should have a trailing edge duration tte403of less than 8 ns. Further investigations of the applicant have shown that at lower ambient temperatures trailing edge durations of less than 12 ns may be sufficient to facilitate or enable the formation of phase transitions. One possible reason could be the decrease in the effective quench rate.

Hence according to some embodiments the trailing edge duration tte403of the electrical programming pulses should be less than 12 ns and according to other embodiments the trailing edge duration tte403should be less than 8 ns.

According to embodiments, the memory device and in particular the thermal environment of the memory cell20ofFIG. 2are configured such that the temperature of the memory cell20approaches the ambient temperature or at least a range of 10 degrees Celsius above the ambient temperature within 12 ns after the beginning of the trailing edge of the respective programming pulse, i.e. within 12 ns after t248. As an example, assuming an ambient temperature of 25 degree Celsius, the memory device is configured such that the temperature of the memory cells drop to 35 degree Celsius or less within 12 ns after t248. This facilitates that the quench-rate is sufficiently high.

FIG. 5illustrates a graph50, depicting experimental data of electrical programming pulses that have been applied to an exemplary memory cell with different trailing edge durations.

The x-axis51denotes the respective trailing edge duration tte403(shown inFIG. 4) in ns and the y-axis52the corresponding resistance in Ohm of the corresponding memory cell having antimony as phase change material. The trailing edge duration was made shorter with every next programming pulse. The results of the experiment are represented as a plot line53. The experiment was performed at room temperature with memory cells comprising an antimony phase change segment in lamellar form having a thickness of 5 nm. In parallel to the phase change segment an electrically conductive layer of TaN was provided with a thickness of 6 nm. The experiment confirms that a short trailing edge facilitates the amorphization of the antimony. More particularly, above a threshold of 10 ns there was hardly any amorphization observed, while at a trailing edge duration of 6-8 ns already a significant amorphization occurred.

FIGS. 6-11provide 3-dimensional views and associated cross sectional views of memory cells according to exemplary embodiments of the invention. As can be seen in these figures, the memory cells may have a cylindrical shape or a lamellar shape. Such shapes may facilitate advanced and efficient device manufacturing as well as dense device integration.

FIG. 6shows a 3-dimensional view of a memory cell600according to an embodiment of the invention. The memory cell600is formed as multilayer-cylinder comprising an inner cylinder625. The inner cylinder625comprises an insulating material. The memory cell600further comprises an outer cylinder626forming a phase change segment621and comprising antimony as phase change material. The outer cylinder626is formed as hollow cylinder and the thickness d of the outer cylinder626is less than 15 nm. The phase change segment621is arranged between a first terminal623and a second terminal624.

FIG. 7shows a 3-dimensional view of a memory cell700according to an embodiment of the invention. The memory cell700comprises a phase change segment721of antimony. The phase change segment721is formed as plain cylinder725of the phase change material antimony. The phase change segment721is arranged between a first terminal723and a second terminal724. The diameter d of the cylinder725establishes a dimension that is less than 15 nm.

FIG. 8shows a 3-dimensional view of a memory cell800according to an embodiment of the invention. The memory cell800has a lamellar shape and comprises a phase change segment821that is formed as a lamellar825. The lamellar825has a thickness d of less than 15 nm as dimension that is smaller than 15 nm. The phase change segment821is arranged between a first terminal823and a second terminal824.

FIG. 9shows a 3-dimensional view of a part of a memory cell900according to another embodiment of the invention. The memory cell900has also a lamellar shape and comprises a phase change segment921that is formed as a lamellar925. The lamellar925comprises a central restriction926. The lamellar925has as restricted dimension a thickness d of less than 15 nm, e.g. 3 nm. The memory cell900further comprises an electrically conductive segment922comprising an electrically conductive material. The phase change segment921and the electrically conductive segment922are arranged in parallel. The part of the memory cell900that is shown inFIG. 9is configured to be arranged between a first terminal and a second terminal which are not shown inFIG. 9.

FIG. 10ashows a 3-dimensional view of a memory cell1000according to another embodiment of the invention.FIG. 10bshows a corresponding cross sectional view. The memory cell1000is formed as multi-layer cylinder. The memory cell1000comprises an inner cylinder1022forming the electrically conductive segment. The memory cell1000further comprises a central cylinder1021forming the phase change segment1027and comprising antimony as phase change material. In addition, the memory cell1000comprises an outer cylinder1025comprising an insulating material. According to this embodiment the thickness d of the central cylinder1021is less than 15 nm and establishes a dimension of the phase change segment that is smaller than 15 nm.

The central cylinder1021and the electrically conductive segment1022are arranged in parallel between a first terminal1023and a second terminal1024. The first terminal1023and the second terminal1024are coupled to the control unit12ofFIG. 1.

FIG. 11ashows a 3-dimensional view of a memory cell1100according to another embodiment of the invention.FIG. 11bshows a corresponding cross sectional view. The memory cell1100is also formed as multi-layer cylinder. The memory cell1100comprises an inner cylinder1121forming a phase change segment1127and comprising antimony as phase change material. The memory cell1100further comprises a central cylinder1122forming the electrically conductive segment22(shown inFIG. 2). In addition, the memory cell1100comprises an outer cylinder1125comprising an insulating material. According to this embodiment the thickness d of the inner cylinder1121which corresponds to the diameter of the inner cylinder1121is less than 15 nm and establishes a dimension of the phase change segment21(shown inFIG. 2) that is smaller than 15 nm.

The inner cylinder1121and the central cylinder1122are arranged in parallel between a first terminal1123and a second terminal1124. The phase change segment1127is located within the inner cylinder1121. The first terminal1123and the second terminal1124are coupled to the control unit12ofFIG. 1.

The memory cells ofFIGS. 6-11can be fabricated using well-known material processing techniques for formation of the various elements of the cell. By way of example, the cylindrical structure may be produced by a keyhole-transfer process as described in Raoux et al., IBM J. Res. & Dev. 52(4/5), 465 (2008), (see FIG. 6 thereof). In general, however, the materials and dimensions of the cells are selected to satisfy the particular needs of the respective application.

FIG. 12shows a flow chart of method steps of a method for operating a memory device, e.g. the memory device10ofFIG. 1.

At a step1210, the method is started.

At a step1220, the control unit12checks the mode of operation, namely whether a read operation or a write operation shall be performed.

If the device10shall operate in the read mode, the control unit12applies at a step1230a read voltage to the first and the second terminal for reading the resistance state.

If the device10shall operate in the write mode, the control unit12applies at a step1240a write voltage as electrical programming pulse to the first and the second terminal and writes thereby the resistance state of the respective memory cell. To ensure that the corresponding melt-quench process is fast enough to effect an amorphization of the phase change material, the electrical programming pulse has a trailing edge duration of less than 12 ns.

At a step1250, the method stops and the memory device10may start again with step1210.

In general, the electrically conductive segment22may be formed of any suitable material. Examples of such materials include semiconductors such as silicon or germanium (with and without doping) and in particular poly-silicon and TaN as mentioned above. The first and the second terminal may be formed of any convenient electrically-conductive material, typically a metallic material (e.g. a pure metal or a metal compound, alloy or other mixture) or a doped semiconductor material such as silicon.

Moreover, the features described may be applied to single-level as well as multi-level cells.

In general, modifications described for one embodiment may be applied to another embodiment as appropriate.