ELECTRONIC PACKAGE AND MANUFACTURING METHOD THEREOF

An electronic package is provided, where a laterally diffused metal oxide semiconductor (LDMOS) type electronic structure is mounted onto a complementary metal oxide semiconductor (CMOS) type electronic element to be integrated into a chip module, thereby shortening electrical transmission path between the electronic structure and the electronic element so as to reduce the communication time between the electronic structure and the electronic element.

BACKGROUND

1. Technical Field

The present disclosure relates to a semiconductor device, and more particularly, to an electronic package having multiple chip modules and manufacturing method thereof.

2. Description of Related Art

Nowadays, terminal products for high-speed computing applications (such as autonomous driving, supercomputers, or mobile devices, etc.) are booming, and they are equipped with packaged semiconductor package elements (chips are bonded onto the packaging substrate), so that relevant terminal products can play a role and be applied to the aforementioned related fields.

Technologies currently used in the field of chip packaging include flip-chip packaging modules such as Chip Scale Package (CSP), Direct Chip Attached (DCA) package, or Multi-Chip Module (MCM) package, or technology for stacking chips into a three-dimensional integrated circuit (3D IC) chip, etc.

FIG.1is a schematic perspective view of a conventional electronic device1. As shown inFIG.1, the electronic device1includes: a circuit board10provided with a plurality of chip elements11, an electronic element16disposed on the circuit board10, a functional element12and a packaging body13.

In high-voltage power integrated circuits, a high-voltage Laterally Diffused Metal Oxide Semiconductor (LDMOS) type semiconductor chip (such as one chip specification of the chip elements11) is usually used to meet high voltage resistance, achieving power control and other requirements, so as to facilitate the design of microwave/RF power circuits.

Moreover, the Complementary Metal-Oxide-Semiconductor (CMOS) type electronic element16is matched with the LDMOS type semiconductor chip, so as to provide a higher data transmission rate for multimedia services at the same time.

However, the LDMOS type semiconductor chip and the CMOS type electronic element16are respectively placed on different positions on the surface of the circuit board10in the conventional electronic device1, so that the two types of chips need to be electrically connected by the circuits within the circuit board10, which makes the signal transmission speed between the chip elements11and the electronic element16too slow and hard to achieve the electrical performance requirements of the current end products.

Also, the chip elements11and the electronic element16occupy too much layout area on the surface of the packaging area of the circuit board10(the layout area of the packaging body13), so that the limited layout space of the circuit board10makes it hard to arrange more functional elements12, which causes a single electronic device1to be unable to meet the requirements of current terminal products, such as lightness, thinness, small size, low power consumption, high electrical performance, etc.

On the other hand, if the functional element14with other functions (such as antenna function) needs to be added, the layout area of the circuit board10needs to be enlarged, such as the area outside the packaging body13shown inFIG.1, wherein the functional element14is electrically connected to the electronic element16by a transmission line17, and the packaging body13covers the chip elements11and a portion of the transmission line17.

Therefore, there is a need for a solution that addresses the aforementioned shortcomings in the prior art.

SUMMARY

In view of the aforementioned shortcomings of the prior art, the present disclosure provides an electronic package, which comprises: an electronic element; an electronic structure disposed on and electrically connected to the electronic element, wherein the electronic element and the electronic structure are used as a chip module; at least one conductive pillar disposed on and electrically connected to the electronic element; and an encapsulation layer formed on the electronic element to cover the electronic structure and the conductive pillar.

The present disclosure further provides a method of manufacturing the electronic package, which comprises: disposing at least one electronic structure and at least one conductive pillar on an electronic element, wherein the electronic element is electrically connected to the electronic structure and the conductive pillar, and the electronic element and the electronic structure are used as a chip module; and forming an encapsulation layer on the electronic element to cover the electronic structure and the conductive pillar.

In the electronic package and manufacturing method thereof, the electronic structure is electrically connected to the electronic element via a plurality of conductive bumps. For example, the electronic structure is bonded to the conductive bumps via conductors.

In the electronic package and manufacturing method thereof, a surface of the encapsulation layer is flush with an end surface of the conductive pillar.

In the electronic package and manufacturing method thereof, an end surface of the conductive pillar is exposed from a surface of the encapsulation layer.

In the electronic package and manufacturing method thereof, the present disclosure further comprises forming at least one conductive element on the encapsulation layer, wherein the conductive element is electrically connected to the conductive pillar.

In the electronic package and manufacturing method thereof, the present disclosure further comprises forming a circuit structure on the encapsulation layer, wherein the circuit structure is electrically connected to the conductive pillar. For example, the present disclosure further comprises forming at least one conductive element on the circuit structure, wherein the conductive element is electrically connected to the circuit structure. Alternatively, the circuit structure is in a form of a single metal layer. Alternatively, the circuit structure is in contact with the electronic structure.

In the electronic package and manufacturing method thereof, the present disclosure further comprises covering around the electronic element by a packaging layer, and forming the encapsulation layer on the packaging layer to cover the electronic structure and the conductive pillar.

As can be understood from the above, the electronic package and manufacturing method thereof according to the present disclosure, the electronic structure is mainly stacked on the electronic element to closely match the electronic element. Thus, compared to the prior art, the electronic package of the present disclosure can save the placement space or placement area on the circuit board or the carrier board of the end product, so it is beneficial to the element arrangement of the circuit board or the carrier board of the end product, so that the electronic components having other functions can be further arranged on other layout areas of the circuit board or the carrier board of the end product as required.

Furthermore, since the electronic element and the electronic structure are integrated into a chip module, the electrical transmission path between the electronic element and the electronic structure is shortened, thereby reducing the communication time between the electronic element and the electronic structure. Therefore, compared to the prior art, the electronic package of the present disclosure can be more fitting with the electrical performance requirements of end products.

DETAILED DESCRIPTION

Implementations of the present disclosure are described below by embodiments. Other advantages and technical effects of the present disclosure can be readily understood by one of ordinary skill in the art upon reading the disclosure of this specification.

It should be noted that the structures, ratios, sizes shown in the drawings appended to this specification are provided in conjunction with the disclosure of this specification in order to facilitate understanding by those skilled in the art. They are not meant, in any ways, to limit the implementations of the present disclosure, and therefore have no substantial technical meaning. Without influencing the effects created and objectives achieved by the present disclosure, any modifications, changes or adjustments to the structures, ratios or sizes are construed as fall within the scope covered by the technical contents disclosed herein. Meanwhile, terms such as “above,” “first,” “second,” “one,” “a,” “an,” and the like, are for illustrative purposes, and are not meant to limit the scope implementable by the present disclosure. Any changes or adjustments made to the relative relationships, without substantially modifying the technical contents, are also to be construed as within the scope implementable by the present disclosure.

FIGS.2A to2Fare schematic cross-sectional views illustrating a method for fabricating an electronic package2in accordance with a first embodiment of the present disclosure.

As shown inFIG.2A, an electronic structure21is provided, and the electronic structure21has a first side21aand a second side21bopposing to the first side21a.

In an embodiment, the electronic structure21is an active element, such as a Laterally Diffused Metal Oxide Semiconductor (LDMOS) type semiconductor chip, the first side21aof which is provided with a plurality of conductors38for bonding conductive bumps22. For example, the first side21aof the electronic structure21has a plurality of electrode pads210for bonding the conductors38.

As shown inFIG.2B, an electronic element29is provided and disposed on a carrier board9, and a plurality of conductive pillars23are formed on the electronic element29.

The electronic element29can be an active element, a passive element, or a combination of both, wherein the active element is, for example, a semiconductor chip, and the passive element is, for example, a resistor, a capacitor, or an inductor. In an embodiment, the electronic element29is a semiconductor chip, such as a Complementary Metal-Oxide-Semiconductor (CMOS) type functional chip, which has an active surface29aand a non-active surface29bopposing to the active surface29a, and the active surface29ahas a plurality of electrode pads290thereon, and the electronic element29is arranged on the carrier board9by the non-active surface29b.

In addition, the carrier board9is, for example, a board body made of semiconductor material (such as silicon or glass), on which a release layer91(or an adhesive layer90) can be formed as required, such that the electronic element29can be disposed on the release layer91.

Also, the conductive pillars23are disposed on a portion of the electrode pads290of the electronic element29and electrically connected to the electrode pads290, and the conductive pillars23are formed by a metal material such as copper or a solder material.

As shown inFIG.2C, the electronic structure21is disposed on the active surface29aof the electronic element29by the conductive bumps22of the electronic structure21.

In an embodiment, the electronic structure21is bonded onto another portion of the electrode pads290of the electronic element29in a manner of flip-chip by the plurality of conductive bumps22to electrically connect the electrode pads290. For example, the conductive bumps22and the conductors38can be covered with a bonding layer24(such as an underfill) as required.

As shown inFIG.2D, an encapsulation layer25is formed on the release layer91of the carrier board9and on the active surface29aof the electronic element29to cover the electronic structure21, the bonding layer24and the conductive pillars23, wherein the encapsulation layer25has a first surface25aand a second surface25bopposing to the first surface25a, and the encapsulation layer25is bonded to the release layer91of the carrier board9by the first surface25a. Then, by using a flattening process, the second surface25bof the encapsulation layer25is flush with an end surface23bof each of the conductive pillars23and the second side21bof the electronic structure21, such that the end surface23bof each of the conductive pillars23and the second side21bof the electronic structure21are exposed from the second surface25bof the encapsulation layer25.

In an embodiment, the encapsulation layer25is an insulating material, such as polyimide (PI), dry film, epoxy resin, or molding compound, and can be formed on the carrier board9in a manner of lamination or molding.

Further, the flattening process uses grinding to remove a portion of the conductive pillars23, a portion of the second side21bof the electronic structure21and a portion of the encapsulation layer25.

Also, if the bonding layer24is not formed, the encapsulation layer25can cover the conductive bumps22and the conductors38.

As shown inFIG.2E, a circuit structure26is formed on the second surface25bof the encapsulation layer25, and the circuit structure26is electrically connected to the conductive pillars23and is in contact with the second side21bof the electronic structure21.

In an embodiment, the circuit structure26is in the form of a single metal layer. For example, the metal layer is made of copper and is in contact with the electronic structure21for heat dissipation.

Further, a plurality of conductive elements27, such as solder balls, may be formed on the circuit structure26.

As shown inFIG.2F, the carrier board9and the release layer91and adhesive layer90formed thereon are removed to expose the non-active surface29bof the electronic element29and the first surface25aof the encapsulation layer25, then a singulation process is performed along cutting paths S as shown inFIG.2Eto obtain the electronic package2.

In an embodiment, the electronic package2can be attached onto an electronic device (not shown) such as a circuit board via the conductive elements27in subsequent processes.

Furthermore, the electronic package2can be configured with a heat dissipation structure28, such as a heat dissipation frame, a heat dissipation fin, a heat dissipation glue or other suitable heat dissipation materials, on the first surface25aof the encapsulation layer25as required, where the heat dissipation structure28contacts the non-active surface29bof the electronic element29.

Therefore, the manufacturing method of the present disclosure integrates the CMOS (such as the electronic element29) and LDMOS (such as the electronic structure21) into a chip module2a, as shown inFIG.2C, to save the placement space or placement area on the circuit board or the carrier board of the end product. Therefore, compared to the prior art, the electronic package2of the present disclosure is beneficial to the element arrangement of the circuit board or the carrier board of the end product, such that the electronic components having other functions can be further arranged on other layout areas of the circuit board or the carrier board of the end product as required.

Furthermore, since the CMOS (such as the electronic element29) and the LDMOS (such as the electronic structure21) are integrated into a chip module2a, the electrical transmission path between the electronic element29and the electronic structure21is shortened so as to reduce the communication time between the electronic element29and the electronic structure21. Therefore, compared to the prior art, the electronic package2of the present disclosure can be more fitting with the electrical performance requirements of end products.

FIGS.3A to3Fare schematic cross-sectional views illustrating a method for fabricating an electronic package3in accordance with a second embodiment of the present disclosure. The difference between the second embodiment and the first embodiment lies in the aspect of packaging, and other manufacturing processes are roughly the same, so similarities between the two will not be provided to avoid repetitions.

As shown inFIG.3A, the processes shown inFIG.2AtoFIG.2Bare first used.

As shown inFIG.3B, a packaging layer35is formed on the release layer91of the carrier board9to cover around the electronic element29.

In an embodiment, the packaging layer35is an insulating material, such as polyimide (PI), dry film, epoxy resin, or molding compound, formed on the carrier board9in a manner of lamination or molding.

As shown inFIG.3C, the electronic structure21is disposed on the active surface29aof the electronic element29by the conductive bumps22of the electronic structure21.

As shown inFIG.3D, an encapsulation layer25is formed on the packaging layer35and on the active surface29aof the electronic element29to cover the electronic structure21, the bonding layer24and the conductive pillars23, wherein the encapsulation layer25is bonded to the packaging layer35by the first surface25athereof. Then, a flattening process is performed.

In an embodiment, the encapsulation layer25and the packaging layer35may be made of the same or different materials as required.

As shown inFIG.3E, a circuit structure26is formed on the second surface25bof the encapsulation layer25, and a plurality of conductive elements27(e.g., solder balls) are formed on the circuit structure26.

As shown inFIG.3F, the carrier board9and the release layer91and the adhesive layer90thereon are removed to expose the non-active surface29bof the electronic element29and the packaging layer35, then a singulation process is performed along the cutting paths S as shown inFIG.3Eto obtain the electronic package3. Further, the packaging layer35may be configured with a heat dissipation structure28(such as heat dissipation fins), which contacts the non-active surface29bof the electronic element29.

The present disclosure further provides an electronic package2,3, which comprises: an electronic structure21, an electronic element29, a plurality of conductive pillars23and an encapsulation layer25.

The electronic structure21is disposed on the electronic element29and electrically connected to the electronic element29, such that the electronic element29and the electronic structure21are used as a chip module2a.

The conductive pillars23are disposed on the electronic element29and electrically connected to the electronic element29.

The encapsulation layer25is formed on the electronic element29to cover the electronic structure21and the conductive pillars23.

In an embodiment, the electronic structure21is electrically connected to the electronic element29by a plurality of conductive bumps22. For example, the electronic structure21is bonded to the conductive bumps22by the conductors38.

In an embodiment, a second surface25bof the encapsulation layer25is flush with an end surface23bof each of the conductive pillars23.

In an embodiment, the end surface23bof each of the conductive pillars23is exposed from the second surface25bof the encapsulation layer25.

In an embodiment, the electronic package2,3further comprises a plurality of conductive elements27formed on the encapsulation layer25and electrically connected to the conductive pillars23.

In an embodiment, the electronic package2,3further comprises a circuit structure26formed on the encapsulation layer25and electrically connected to the conductive pillars23. Furthermore, the electronic package2,3further comprises a plurality of conductive elements27formed on the circuit structure26and electrically connected to the circuit structure26. For example, the circuit structure26is in the form of a single metal layer. Alternatively, the circuit structure26is in contact with the electronic structure21.

In an embodiment, the electronic package3further comprises a packaging layer35covering around the electronic element29, such that the encapsulation layer25is formed on the packaging layer35.

In conclusion, in the electronic package and manufacturing method thereof of the present disclosure, the electronic structure is stacked on the electronic element to closely match the electronic element, such that there is no need to redesign the circuit board in the present disclosure, the manufacturing cost may be greatly reduced and no expansion of the size of the circuit board is required, which fits the needs of miniaturization and facilitates high electrical performance.

The above embodiments are provided for illustrating the principles of the present disclosure and its technical effect, and should not be construed as to limit the present disclosure in any way. The above embodiments can be modified by one of ordinary skill in the art without departing from the spirit and scope of the present disclosure. Therefore, the scope claimed of the present disclosure should be defined by the following claims.