Method for semiconductor device fabrication

A method of forming a semiconductor device is disclosed. The method includes exposing a dummy oxide layer of a gate structure to a vapor mixture comprising NH3 and a fluorine-containing compound at a first temperature, wherein the dummy oxide layer is formed over a substrate and surrounded by a gate spacer that includes a material different from that of the dummy oxide layer. The method further includes rinsing the substrate with a solution containing de-ionized water (DIW) at a second temperature. The method may further include baking the substrate in a chamber heated to a third temperature higher than the first and second temperatures. The exposing, rinsing, and baking steps remove the dummy oxide layer thereby forming an opening in the gate spacer. The method may further include forming a gate stack having a high-k gate dielectric layer and a metal gate electrode in the opening.

BACKGROUND

One advancement implemented as technology nodes shrink, in some IC designs, has been the replacement of the typically polysilicon gate electrode with a metal gate electrode to improve device performance with the decreased feature sizes. One process of forming a metal gate stack is termed a replacement or “gate-last” process in which the final gate stack is fabricated “last” which allows for reduced number of subsequent processes, including high temperature processing, that must be performed after formation of the gate. However, there are challenges to implementing such IC fabrication processes, especially with scaled down IC features in advanced process nodes, such as N20, N16 and beyond.

DETAILED DESCRIPTION

The present disclosure is generally related to methods for semiconductor device fabrication, and more particularly to methods of removing a dummy oxide layer in a gate-last process. In a typical gate-last process for manufacturing a field effect transistor (FET), first, a dummy oxide layer and a dummy gate electrode are formed over a substrate as a placeholder for an actual gate stack. Then more features are formed over the substrate, such as source/drain regions, a gate spacer surrounding the dummy oxide layer and the dummy gate electrode, and an interlayer dielectric (ILD) layer surrounding the gate spacer. Subsequently, the dummy gate electrode is removed to form an opening in the gate spacer and to expose the dummy oxide layer through the opening. Another step is performed to remove the dummy oxide layer through the opening so as to expose the substrate for forming the actual gate stack thereon. However, problems arise when removing the dummy oxide layer with typical wet and/or dry etch processes. During a wet etch process, top portions of the ILD layer are isotropically removed leaving a plurality of recesses in the ILD layer. This is due to the use of hydrofluoric (HF) acid in the wet etch process, and the opening limits entrance of the HF acid into interior surface of the opening. Thus, less HF acid reaches bottom of the opening and more of the ILD layer reacts. During a dry (plasma) etching process, the substrate underneath the dummy oxide layer may be accidentally recessed as a result of the removal of the dummy oxide layer. The recesses in the ILD layer and/or the substrate are problematic in various respects. For example, the recesses present in the substrate may change dopant distribution in channel regions of the FET. Thus, performance characteristics such as threshold voltage and reliability may degrade. For another example, the recesses present in the ILD layer can become a receptacle of metals during subsequent processing thereby increasing the likelihood of electrical shorting and/or device failure.

U.S. Pat. No. 8,361,855 entitled “Method for Fabricating a Gate Structure” by Matt Yeh et al., the contents of which are hereby incorporated by reference in its entirety, discloses a method of removing the dummy oxide layer using a gas etching process followed by a process of heating the substrate to a high temperature, which overcomes the above shortcomings associated with typical wet and/or dry etch processes. However, in view of the continued scaling down process and increased fabrication quality target, improvements in this area are still desirable. For example, in advanced process nodes such as N20, N16, and smaller nodes, any residuals or particulates on the substrate as a result of the dummy oxide removal process might be hazardous to the IC fabrication. For example, a particulate on the bottom of a gate opening may be amplified as a bump in the actual gate stack when layers of the gate stack are subsequently formed over the particulate, causing defects in the IC. The present disclosure provides embodiments of a method of removing the dummy oxide layer substantially free of any residuals or particulates in the gate opening, while avoiding ILD/substrate recess issues associated with typical wet and/or dry etch processes.

Referring toFIG. 1, shown therein is a method100of forming a semiconductor device according to various aspects of the present disclosure. The method100is an example, and is not intended to limit the present disclosure beyond what is explicitly recited in the claims. Additional operations can be provided before, during, and after the method100, and some operations described can be replaced, eliminated, or moved around for additional embodiments of the method. The method100is described below in conjunction withFIGS. 2-10which are cross-sectional views of a device200according to various aspects of the present disclosure.

As will be shown, the device200illustrates a field effect transistor (FET) in one region of a substrate. This is provided for simplification and ease of understanding and does not necessarily limit the embodiments to any types of devices, any number of devices, any number of regions, or any configuration of structures of regions. Furthermore, the device200may be an intermediate device fabricated during processing of an IC, or a portion thereof, that may comprise static random access memory (SRAM) and/or other logic circuits, passive components such as resistors, capacitors, and inductors, and active components such as p-type FETs (PFETs), n-type FETs (NFETs), FinFETs, metal-oxide semiconductor field effect transistors (MOSFET), complementary metal-oxide semiconductor (CMOS) transistors, bipolar transistors, high voltage transistors, high frequency transistors, other memory cells, and combinations thereof.

The method100(FIG. 1) forms a gate structure220over a substrate202(FIG. 2) at operation102. Referring toFIG. 2, the substrate202is a silicon substrate in the present embodiment. Alternatively, the substrate202may comprise another elementary semiconductor, such as germanium; a compound semiconductor including silicon carbide, gallium arsenic, gallium phosphide, indium phosphide, indium arsenide, and/or indium antimonide; an alloy semiconductor including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and/or GaInAsP; or combinations thereof. In yet another alternative, the substrate202is a semiconductor on insulator (SOI).

The substrate202includes a region208that is isolated from other portions of the substrate202by isolation structures212. In an embodiment, the region208is a p-type field effect transistor region, such as an n-well in a p-type substrate, for forming a PFET. In another embodiment, the region208is an n-type field effect transistor region for forming an NFET.

The isolation structures212may be formed of silicon oxide, silicon nitride, silicon oxynitride, fluoride-doped silicate glass (FSG), a low-k dielectric material, and/or other suitable insulating material. The isolation structures212may be shallow trench isolation (STI) features. In an embodiment, the isolation structures212are STI features and are formed by etching trenches in the substrate202. The trenches may then be filled with isolating material, followed by a chemical mechanical planarization (CMP) process. Other isolation structures212such as field oxide, LOCal Oxidation of Silicon (LOCOS), and/or other suitable structures are possible. The isolation structures212may include a multi-layer structure, for example, having one or more liner layers.

The gate structure220includes a gate stack that includes a dummy oxide layer222and a dummy gate electrode layer224. The dummy oxide layer222may include a dielectric material such as silicon oxide (SiO2) or nitrogen (N) doped SiO2. The dummy oxide layer222may be formed by chemical oxidation, thermal oxidation, atomic layer deposition (ALD), chemical vapor deposition (CVD), and/or other suitable methods. For example, the dummy oxide layer222can be grown by a rapid thermal oxidation (RTO) process or in an annealing process comprising oxygen. The dummy gate electrode layer224may comprise a single layer or multilayer structure. In an embodiment, the dummy gate electrode layer224comprises poly-silicon. Further, the dummy gate electrode layer224may be doped poly-silicon with the same or different doping. The dummy gate electrode layer224may be formed by suitable deposition processes such as low-pressure chemical vapor deposition (LPCVD) and plasma-enhanced CVD (PECVD). In an embodiment, the dummy oxide layer222and the dummy gate electrode layer224are first deposited as blanket layers over the substrate202. Then the blanket layers are patterned through a process including photolithography processes and etching processes thereby removing portions of the blanket layers and keeping the remaining portions over the substrate202as the dummy oxide layer222and the dummy gate electrode layer224. In some embodiments, the gate structure220may include additional dielectric layers and/or conductive layers. For example, the gate structure220may include hard mask layers, interfacial layers, capping layers, diffusion/barrier layers, other suitable layers, and/or combinations thereof.

The gate structure220further includes a gate spacer226surrounding the dummy oxide layer222and the dummy gate electrode layer224along sidewalls thereof. The gate spacer226includes a material different from that of the dummy oxide layer222. In an embodiment, the gate spacer226includes a nitrogen-containing dielectric material, such as silicon nitride, silicon oxynitride, other nitrogen-containing dielectric material, or combination thereof. In an example, the gate spacer226includes two layers and is formed by blanket depositing a first dielectric layer as a liner layer over the device200and a second dielectric layer as a main D-shaped spacer over the first dielectric layer, and then, anisotropically etching to remove portions of the dielectric layers to form the gate spacer226as illustrated inFIG. 2. In some embodiments, the gate structure220may include a seal layer between the dummy gate stack222/224and the gate spacer226.

The method100(FIG. 1) proceeds to operation104to form source and drain regions in the substrate202adjacent to the gate structure220. The source and drain regions may be formed by a variety of processes. Referring toFIG. 3, in the present embodiment, the source and drain regions each include a lightly doped source/drain (LDD)312, a heavily doped source/drain (HDD)314, and a silicidation316.

In an embodiment, the LDD312is formed by a process that includes an etching process, a cleaning process, and an epitaxy process. For example, the etching process removes portions of the substrate202adjacent to the gate structure220thereby forming two recesses sandwiching the gate structure220; the cleaning process clean the recesses with a hydrofluoric acid (HF) solution or other suitable solution; and the epitaxy process performs a selective epitaxial growth (SEG) process thereby forming an epitaxial layer312in the recesses. The etching process may be a dry etch process, a wet etch process, or a combination thereof. In an embodiment, the SEG process is a low pressure chemical vapor deposition (LPCVD) process using a silicon-based precursor gas. Further, the SEG process may in-situ dope the epitaxial layer312with a p-type dopant for forming a PFET or an n-type dopant for forming a NFET. If the epitaxial layer312is not doped during the SEG process, it may be doped in a subsequent process, for example, by an ion implantation process, plasma immersion ion implantation (PIII) process, gas and/or solid source diffusion process, other process, or a combination thereof. An annealing process, such as a rapid thermal annealing and/or a laser thermal annealing, may be performed to activate dopants in the epitaxial layer312. In an embodiment, the HDD314may be formed by a process that includes an etch-back process and an epitaxy process. For example, the etch-back process selectively etches the epitaxial layer312to remove portions thereof with a dry etch process, a wet etch process, or combination thereof; and the epitaxy process uses a process similar to that forms the LDD312but using heavier dopants. An annealing process, such as a rapid thermal annealing and/or a laser thermal annealing, may be performed to activate dopants in the epitaxial layer314. The silicidation316may include nickel silicide (NiSi), nickel-platinum silicide (NiPtSi), nickel-platinum-germanium silicide (NiPtGeSi), nickel-germanium silicide (NiGeSi), ytterbium silicide (YbSi), platinum silicide (PtSi), iridium silicide (IrSi), erbium silicide (ErSi), cobalt silicide (CoSi), other suitable conductive materials, and/or combinations thereof. The silicidation316may be formed by a process that includes depositing a metal layer, annealing the metal layer such that the metal layer is able to react with silicon to form silicide, and then removing the non-reacted metal layer.

In various embodiments of the present disclosure, the source/drain regions312/314/316or portions thereof may be formed by a variety of other processes. For example, the source/drain regions may be formed by a halo or lightly doped drain (LDD) implantation, source/drain implantation, source/drain activation and/or other suitable processes. Furthermore, in some embodiments, portions of the source/drain regions, such as the LDD312, may be formed before the gate spacer226is formed and remaining portions of the source/drain regions are formed after the gate spacer226is formed.

The method100(FIG. 1) proceeds to operation106to form a contact etch stop layer (CESL)412and an interlayer dielectric (ILD) layer414over the gate structure220and over the substrate202(FIG. 4). Examples of materials that may be used to form the CESL412include silicon nitride, silicon oxynitride, silicon nitride with few oxygen (O) or carbon (C) elements, and/or other materials. The CESL412may be formed by PECVD process and/or other suitable deposition or oxidation processes. For example, the CESL412may include silicon nitride (e.g., SiN) formed by a PECVD mixed frequency process. The ILD layer414may include materials such as tetraethylorthosilicate (TEOS) oxide, un-doped silicate glass, or doped silicon oxide such as borophosphosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), boron doped silicon glass (BSG), and/or other suitable dielectric materials. In some embodiments, the ILD layer318may include a high density plasma (HDP) dielectric material (e.g., HDP oxide) and/or a high aspect ratio process (HARP) dielectric material (e.g., HARP oxide). The ILD layer414may be deposited by a PECVD process or other suitable deposition technique. In an embodiment, prior to the formation of the CESL412and the ILD layer414, a partial removal of the gate spacer226may be performed to reduce the thickness thereof.

The method100(FIG. 1) proceeds to operation108to planarize the CESL412and the ILD layer414to expose a top surface of the gate structure220. Referring toFIG. 5, the dummy gate electrode layer224is exposed by operation108. In an embodiment, operation108includes a chemical mechanical planarization (CMP) process.

The method100(FIG. 1) proceeds to operation110to remove the dummy gate electrode layer224from the gate structure220. The dummy gate electrode layer224can be removed with a suitable wet etch, dry (plasma) etch, and/or other processes. In an embodiment, the dummy gate electrode layer224comprises poly-silicon and the wet etch process for removal thereof includes exposure to a hydroxide solution containing ammonium hydroxide, diluted HF, deionized water, and/or other suitable etchant solutions. In another embodiment, the dummy gate electrode layer224comprises poly-silicon and the dry etch process for removal thereof may be performed under a source power of about 650 to 800 W, a bias power of about 100 to 120 W, and a pressure of about 60 to 200 mTorr, using Cl2, HBr and He as etching gases. Referring toFIG. 6, in the present embodiment, the dummy gate electrode layer224and any other layer(s) (not shown) are removed by operation110(FIG. 1) thereby forming an opening602in the gate spacer226. The opening602exposes a top surface of the dummy oxide layer222. In some embodiments, during operation110, certain regions of the IC may be covered by a hard mask layer so that those regions are protected from the etching process while the dummy gate electrode layer224is removed.

The method100(FIG. 1) proceeds to operation112to remove the dummy oxide layer222. In the present embodiment, operation112includes three sub-operations112a,112b, and112c, which are described in detail below.

In operation112a, the method100(FIG. 1) exposes the dummy oxide layer222to a vapor mixture702in a sealed gas etching chamber. Referring toFIG. 7, the device200is placed into the sealed gas etching chamber and the vapor mixture702is introduced into the chamber. The vapor mixture702reacts with the dummy oxide layer222and a portion of the ILD layer414thereby forming reaction products704aand704brespectively. The reaction process is self-limiting, in that amount of material reacted is determined by amount of the vapor mixture702introduced into the gas etching chamber. In some embodiments, the vapor mixture702comprising NH3and a fluorine-containing compound. It is believed that one of the vapor mixture components functions as a catalyst and the other component functions an etchant. In some embodiments, the fluorine-containing compound may be a compound selected from the group consisting of HF and NF3. In an embodiment, the vapor mixture702comprises NH3and HF. The vapor mixture of NH3and HF comprises a ratio of NH3to HF between about 0.1 to about 10, such as a ratio of 1 part NH3to 1 part HF by volume. Furthering this embodiment, operation112ais performed at a pressure ranging from about 10 mTorr to about 25 mTorr and at a temperature ranging from about 20° C. to about 70° C. In another embodiment, the vapor mixture702comprises NH3and NF3. The vapor mixture of NH3and NF3comprises a ratio of NH3to NF3from about 0.5 to 5, such as a ratio of 2 parts NH3to 1 part NF3by volume. Furthering this embodiment, operation112ais performed at a pressure ranging from about 2 Torr to about 4 Torr and at a temperature ranging from about 20° C. to about 70° C. In various embodiments, operation112ais performed for about 10 seconds to about 600 seconds, depending on the thickness of the dummy oxide layer222.

While the mechanism of the reaction does not affect the scope of the claims, it is believed that, in some embodiments, the reaction process is a multiple step process. For example, during a first step, a blanket adsorbed reactant film of the vapor mixture702may be formed over the top surface of the dummy oxide layer222and the surface of the dielectric layers including the gate spacer226, CESL412, and ILD layer414. During a second step, the adsorbed reactant film may react with the top surface of the dummy oxide layer222in contact therewith to form a first condensed and solid reaction product704abeneath the adsorbed reactant film, for example, according to the following formula:
6HF+NH4+SiO2→(NH4)2SiF6+H2O  (1)
The adsorbed reactant film may also react with the top surface of the ILD layer414in contact therewith to form a second condensed and solid reaction product704bbeneath the adsorbed reactant film. The adsorbed reactant film may not or less react with the surface of the gate spacer226and CESL412in contact therewith beneath the adsorbed reactant film.

In operation112b, the method100(FIG. 1) rinses the substrate202including the device200with a solution802containing de-ionized water (DIW). Referring toFIG. 8, operation112bmay be performed in a sealed wet rinsing chamber. In an embodiment, the solution802includes DIW and a chemical to form a light acidic solution. For example, the chemical may be carbon dioxide (CO2), diluted hydrochloric acid (HCl), or diluted citric acid. In an embodiment, the solution802is slightly acidic and has a pH value ranging from about 3 to about 7. This acidic solution is effective for removing chemical residues which may include an alkali residue. In another embodiment, the solution802is simply DIW. The operation112bis performed at a temperature ranging from about 20° C. to about 80° C. In various embodiments, operation112bis performed for about 10 seconds to about 600 seconds, depending on the thickness of the solid reaction products704aand704b. It is believed that the solution802and the rinsing process may partially or completely remove the adsorbed reactant film and the solid reaction products704aand704b. For example, (NH4)2SiF6, believed to comprise the solid reaction products704aand704b, can be dissolved in DIW. For example, in some embodiments, operation112bmay at least partially remove the solid reaction products704aand704boff of the substrate202. In some embodiments, operation112bmay change density of the solid reaction products704aand704bso that they become easier to remove in a subsequent baking step.

In some embodiments, the operation112bfurther includes a process of drying the substrate202after it is rinsed. In an embodiment, a spin drying process is used to dry the substrate202. For example, the substrate202is spun while it is being blown with a flow of an inert gas such as N2or other inactive gases. For example, the substrate202may be spun at a rate of about 2,500 rpm although other spin rates may be used. The centrifugal forces and the flow of the inert gas remove from the surface of the substrate202any residuals of the solution802. In another embodiment, an isopropyl alcohol (IPA) drying process is used to dry the substrate202. For example, hot vapor of IPA may be introduced into the wet rinsing chamber where the substrate202is received. The IPA displaces the solution802from the surface of the substrate202. Then the IPA evaporates during a cooling process, leaving the substrate202moisture-free.

In operation112c, the method100(FIG. 1) bakes the substrate202to a high temperature to cause sublimation of any remaining portions of the adsorbed reactant film and the solid reaction products704aand704b. Referring toFIG. 9, in embodiments, operation112cis performed in a sealed baking chamber at a pressure ranging from about 10 mTorr to about 25 mTorr. In some embodiments, the baking chamber may be heated to a temperature ranging from about 90° C. to about 200° C. In some embodiments, the substrate202is heated while a carrier gas is blown over the substrate202to remove the sublimation products from the baking chamber. In some embodiments, the carrier gas is an inert gas such as N2, He, Ar, or a mixture thereof. In various embodiments, operation112bmay be performed for about 10 seconds to about 600 seconds. The operation112cfurther cleans the substrate202in case that the operation112bhas not completely removed the reaction products and residuals from the operation112a.

In some embodiments, the operations112a,112b, and112care each performed in a separate chamber. Alternatively, the three operations may be performed in three chambers of a cluster tool. For example, the substrate202is first received in a gas etching chamber where the operation112ais performed. Subsequently, the substrate202is moved by a robot from the gas etching chamber to a wet rinsing chamber where the operation112bis performed. Finally, the substrate202is moved by a robot from the wet rinsing chamber to a baking chamber where the operation112cis performed. Using a cluster tool reduces timing gap between operations and reduces the possibility that the substrate202may be exposed and contaminated during the dummy oxide removal process.

After the operation112(FIG. 1) has completed, the dummy oxide layer222is completely removed from the gate structure220thereby forming an opening902therein (FIG. 9). The opening902is surrounded by the gate spacer226. A top surface904of the substrate202is exposed through the opening902and is substantially free of any recesses and/or residuals, achieving cleanliness for improved IC fabrication quality and circuit performance. In embodiments, a ratio of removal rates by the vapor mixture702of the dummy oxide layer222and the substrate202is greater than 100. Therefore, the method100for fabricating a gate structure creates almost no recess in the substrate202, overcoming the substrate recess issues associated with traditional dry etch processes discussed above. Meanwhile, the ILD layer414may be partially removed by the operation112because the gas etching process (operation112a) has almost no selectivity for the dummy oxide layer222and the ILD layer414. In some embodiments, the ILD layer414may lose almost the same thickness as the dummy oxide layer222does. However, that is only a small portion, e.g., less than 1%, of the ILD layer414. Therefore, the method100for fabricating a gate structure creates almost no recess in the ILD layer414, overcoming the ILD loss issues associated with traditional wet and/or dry etch process discussed above. Furthermore, the CESL412and the gate spacer226remain substantially unchanged through the operation112, maintaining a desirable profile for further gate stack formation. In an embodiment, a ratio of removal rates by the vapor mixture702of the dummy oxide layer222and the gate spacer226is greater than 2.

The method100(FIG. 1) proceeds to operation114to form a gate stack1010in the opening902. Referring toFIG. 10, in the present embodiment, the gate stack1010includes an interfacial layer1012, a dielectric layer1014, a work function metal layer1016, and a fill layer1018. The interfacial layer1012may include a dielectric material such as silicon oxide layer (SiO2) or silicon oxynitride (SiON), and may be formed by chemical oxidation, thermal oxidation, atomic layer deposition (ALD), CVD, and/or other suitable dielectric. The dielectric layer1014may include a high-k dielectric layer such as hafnium oxide (HfO2), Al2O3, lanthanide oxides, TiO2, HfZrO, Ta2O3, HfSiO4, ZrO2, ZrSiO2, combinations thereof, or other suitable material. The dielectric layer1014may be formed by ALD and/or other suitable methods. The work function metal layer1016may be a p-type or an n-type work function layer. Exemplary p-type work function metals include TiN, TaN, Ru, Mo, Al, WN, ZrSi2, MoSi2, TaSi2, NiSi2, WN, other suitable p-type work function materials, or combinations thereof. Exemplary n-type work function metals include Ti, Ag, TaAl, TaAlC, TiAlN, TaC, TaCN, TaSiN, Mn, Zr, other suitable n-type work function materials, or combinations thereof. The work function layer1016may include a plurality of layers and may be deposited by CVD, PVD, and/or other suitable process. The fill layer1018may include aluminum (Al), tungsten (W), cobalt (Co), copper (Cu), and/or other suitable materials. The fill layer1018may be formed by CVD, PVD, plating, and/or other suitable processes. The gate stack1010fills the opening902(FIG. 9) of the gate structure220. A CMP process may be performed to remove excess materials from the gate stack1010and to planarize a top surface1020of the device200. Further operations, such as contact and via formation, interconnect processing, etc., may be performed subsequently to complete the device200fabrication.

Although not intended to be limiting, one or more embodiments of the present disclosure provide many benefits to a semiconductor device and the formation thereof. For example, a semiconductor device thus formed is substantially free of defects associated with ILD oxide loss and substrate material loss in a typical gate-last formation process. For example, a FinFET device formed with embodiments of the present disclosure will have desirable fin height and will preserve oxide material in its isolation structures. For example, a FET device formed with embodiments of the present disclosure will have desirable gate profile and improved threshold voltage.

In one exemplary aspect, the present disclosure is directed to a method of forming a semiconductor device. The method includes exposing a dummy oxide layer of a gate structure to a vapor mixture comprising NH3and a fluorine-containing compound at a first temperature, wherein the dummy oxide layer is formed over a substrate and surrounded by a gate spacer that includes a material different from that of the dummy oxide layer. The method further includes rinsing the substrate with a solution containing de-ionized water (DIW) at a second temperature.

In another exemplary aspect, the present disclosure is directed to a method of forming a semiconductor device. The method includes providing a substrate, wherein the substrate includes a dummy oxide layer and a nitrogen-containing dielectric layer surrounding the dummy oxide layer. The method further includes exposing the dummy oxide layer to a vapor mixture comprising NH3and a fluorine-containing compound at a first temperature thereby converting the dummy oxide layer to a reaction product. The method further includes rinsing the substrate with a solution containing de-ionized water (DIW) at a second temperature to at least partially remove the reaction product from the substrate. The method further includes heating the substrate to a third temperature higher than the first and second temperatures to cause sublimation of the reaction product thereby forming an opening in the nitrogen-containing dielectric layer.

In another exemplary aspect, the present disclosure is directed to a method of forming a semiconductor device. The method includes forming a gate structure over a substrate, wherein the gate structure includes a dummy oxide layer, a dummy gate electrode layer over the dummy oxide layer, and a nitrogen-containing dielectric layer surrounding the dummy oxide layer and the dummy gate electrode layer. The method further includes removing the dummy gate electrode layer thereby exposing the dummy oxide layer. The method further includes exposing the dummy oxide layer to a vapor mixture comprising NH3and a fluorine-containing compound at a first temperature; rinsing the substrate with a solution containing de-ionized water (DIW) at a second temperature; and heating the substrate to a third temperature higher than the first and second temperatures, thereby forming an opening in the nitrogen-containing dielectric layer. The method further includes forming a gate stack, the gate stack at least partially occupying the opening.