Method of fabricating display device having a pixel region and a circuit region over the same substrate

A method of fabricating a display device is provided. The method includes providing a substrate having a pixel region and a circuit region located at the periphery of the pixel region. A first semiconductor layer and a second semiconductor layer are formed on the pixel region and on the circuit region, respectively. The first semiconductor layer may be selectively surface treated to increase the density of lattice defects in a surface of the first semiconductor layer.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims priority to and the benefit of Korean Patent Application No. 2004-50873, filed Jun. 30, 2004, the disclosure of which is incorporated herein by reference in its entirety.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a method of fabricating a display device and, more particularly, to a method of fabricating a display device having a thin film transistor (TFT).

2. Description of the Related Art

A flat panel device in which each unit pixel has a unit pixel driving circuit is referred to as an active matrix display device. The unit pixel driving circuit includes at least one thin film transistor (TFT) to control current or voltage applied to a pixel electrode.

The TFT includes a semiconductor layer, a gate electrode and source and drain electrodes, and is classified according to a type of the semiconductor layer. Specifically, the TFT is referred to as a polysilicon TFT when the semiconductor layer is formed of a polysilicon layer, and referred to as an amorphous silicon TFT when the semiconductor layer is formed of an amorphous silicon layer. For the polysilicon TFT, carrier mobility in a channel region is higher than that for the amorphous silicon TFT, so that a display device having a high resolution may be implemented. In addition, the high carrier mobility of the polysilicon TFT enables a pixel portion as well as a circuit portion for driving the pixel portion to be simultaneously formed on the substrate of the display device. As described above, when a display device includes a pixel portion and a circuit portion on the same substrate, a thin film transistor in the pixel portion and a thin film transistor in the circuit portion may have different specifications from each other. However, it is challenging to form the pixel TFT and the circuit TFT to have different electrical characteristics from each other on the same substrate.

SUMMARY OF THE INVENTION

The present invention, therefore, solves aforementioned problems associated with conventional devices by providing a method of fabricating a display device capable of forming a pixel TFT and a circuit TFT, which have different electrical characteristics, on one substrate.

In an exemplary embodiment of the present invention, a method of fabricating a display device is provided. The method includes providing a substrate having a pixel region and a circuit region located at the periphery of the pixel region. A first semiconductor layer and a second semiconductor layer may be formed on the pixel region and on the circuit region, respectively. The first semiconductor layer may be selectively surface treated to be increased density of lattice defects of a surface of the first semiconductor layer.

The surface treatment of the first semiconductor layer may be performed with plasma. The plasma may contain at least one material selected from a group consisting of O2, N2O, H2and inert gas.

The selective surface treatment of the first semiconductor layer may include: forming a mask pattern on the second semiconductor layer to expose the first semiconductor layer; and performing surface treatment on the exposed first semiconductor layer with the plasma. The mask pattern may be a photoresist pattern.

The method may further include: forming a gate insulating layer on the surface-treated first semiconductor layer and on the second semiconductor layer; and forming a first gate electrode and a second gate electrode on the gate insulating layer, the first and second gate electrodes overlapping the first semiconductor layer and the second semiconductor layer, respectively.

In addition, the method may further include: forming a first drain electrode coupled to the first semiconductor layer; and forming a pixel electrode coupled to the first drain electrode. Here, the method may further include: forming an organic functional layer having at least an emission layer on the pixel electrode; and forming a counter electrode on the organic functional layer.

In another exemplary embodiment of the present invention, a method of fabricating a display device is provided. The method includes providing a substrate having a pixel region and a circuit region located at the periphery of the pixel region. A first semiconductor layer and a second semiconductor layer may be formed on the pixel region and on the circuit region, respectively. The first semiconductor layer may be selectively surface treated with inert gas plasma.

DETAILED DESCRIPTION OF THE INVENTION

FIGS. 1A,1B and1C are cross-sectional views showing a method of fabricating a display device according to an embodiment of the present invention.

Referring toFIG. 1A, a substrate10having a pixel region A and a circuit region B located at the periphery of the pixel region A is provided. The pixel region A is a region where images are displayed. In the figure, a unit pixel is shown as the pixel region. The circuit region B, which is a region where circuits for driving and controlling the images displayed on the pixel region A are formed, is shown herein as one thin film transistor. Further, the substrate10may be made of glass, quartz, sapphire, single crystal silicon, or plastic.

A buffer layer13may be formed on the substrate10. The buffer layer13may be made of a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, or a stacked layer thereof.

An amorphous silicon layer may be deposited on the buffer layer13. A polysilicon layer may be formed by crystallizing the amorphous silicon layer using a solid phase crystallization (SPC) method, an excimer laser annealing (ELA) method, a sequential lateral solidification (SLS) method, or a metal induced crystallization (MIC) method. By patterning the polysilicon layer, a first semiconductor layer21and a second semiconductor layer31may be formed on the pixel region A and on the circuit region B, respectively.

Next, the first semiconductor layer21may be selectively surface-treated to increase the density of lattice defects of a surface of the first semiconductor layer21. The surface treatment of the first semiconductor layer21may be performed with plasma. The plasma may contain at least one material selected from a group consisting of O2, N2O, H2, and inert gas. The inert gas may be N2or element of group18in the periodic table. The element of group18may be He or Ar. Particles accelerated in the plasma may physically collide with the surface of the first semiconductor layer21to increase the density of the lattice defects of the surface of the first semiconductor layer21. Moreover, when reactive gas such as O2, N2O, or H2is contained in the plasma, an energy of the plasma may be controlled such that the physical collision prevails over the chemical reaction while performing the surface treatment on the first semiconductor layer21.

Specifically, selectively performing the surface treatment on the first semiconductor layer21includes forming a mask pattern99on the second semiconductor layer31to expose the first semiconductor layer21, and performing the surface treatment on the exposed first semiconductor layer21with plasma. The mask pattern99may be a photoresist pattern.

Referring toFIG. 1B, the mask pattern (99inFIG. 1a) is removed to expose the second semiconductor layer31. A gate insulating layer33is formed on the exposed second semiconductor layer31and on the surface-treated first semiconductor layer21. The gate insulating layer33may be formed by a physical vapor deposition (PVD) method or a chemical vapor deposition (CVD) method. The gate insulating layer33may be formed along the surface of the semiconductor layers21and31, and an interface between the gate insulating layer33and the first semiconductor layer21may have poor electrical characteristics compared to an interface between the gate insulating layer33and the second semiconductor layer31. The difference in electrical characteristics results in part because the surface of the first semiconductor layer21is treated with inert gas plasma and the surface of the second semiconductor layer31is not treated. In particular, the surface treatment of the first semiconductor layer21tends to increase the density of surface lattice defects in the first semiconductor layer21. The gate insulating layer33may be formed using a LPCVD, APCVD, or PECVD method, or similar method known to a skilled artisan. The gate insulating layer33may be formed of a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, or a stacked layer thereof. In addition, the gate insulating layer33may be formed to a thickness of about 800 Å to about 1500 Å.

A first gate electrode25and a second gate electrode35overlapping the first semiconductor layer21and the second semiconductor layer31, respectively, may be formed by depositing a gate conductive layer on the gate insulating layer33and patterning the gate conductive layer. An interlayer insulating layer40may be formed on the gate electrodes25and35. First contact holes exposing both ends of the first semiconductor layer21and second contact holes exposing both ends of the second semiconductor layer31may be formed in the interlayer insulating layer40. Source and drain conductive layers may be deposited on the substrate where the contact holes are formed, and then the source and drain conductive layers may be patterned to form a first source electrode27aand a first drain electrode27brespectively connected to both ends of the first semiconductor layer21through the first contact holes, and a second source electrode37aand a second drain electrode37brespectively connected to both ends of the second semiconductor layer31through the second contact holes.

The first semiconductor layer21, the first gate electrode25, and the first source and drain electrodes27aand27bform a pixel TFT. Further, the second semiconductor layer31, the second gate electrode35, and the second source and drain electrodes37aand37bform a circuit TFT. The surface lattice defect of the first semiconductor layer21and a relatively rough interface between the first semiconductor layer21and the gate insulating layer33cause trap and scattering of charges when operating the pixel TFT. Therefore, an S-factor of the pixel TFT may be larger than that of the circuit TFT. Accordingly, when the pixel TFT having the large S-factor is a driving TFT coupled to an electroluminescent (EL) element of an electroluminescent display device, a gray-scale of the EL element may be readily controlled. However, since the circuit TFT is generally used as a switching TFT, its S-factor should be small. As a result, by selectively performing the surface treatment on the first semiconductor layer21to increase the density of lattice defects on the first semiconductor layer21, a pixel TFT and a circuit TFT that have different electrical characteristics may be fabricated on one substrate.

A passivation insulating layer45may be formed on the source and drain electrodes27a,27b,37aand37b. A via hole exposing the first drain electrode27bmay be formed in the passivation insulating layer45. A pixel conductive layer may be formed on the substrate where the via hole is formed, and the pixel conductive layer may be patterned to form a pixel electrode50electrically connected to the first drain electrode27bon the passivation insulating layer45of the pixel region A through the via hole.

Referring toFIG. 1C, a pixel defining layer55having an opening that exposes at least a portion of the pixel electrode50may be formed on the pixel electrode50. An organic functional layer60having at least an emission layer may be formed on the pixel electrode50exposed in the opening. A counter electrode70may be formed on the organic functional layer60.

An exemplary example will now be described for thorough understanding of the present invention.

FABRICATION EXAMPLE 1 OF PIXEL AND CIRCUIT TFTS

An amorphous silicon layer was deposited on a substrate having a pixel region and a circuit region and the amorphous silicon layer was crystallized by an ELA method to form a polysilicon layer. The polysilicon layer was patterned to form a first semiconductor layer and a second semiconductor layer on the pixel region and the circuit region, respectively. A photoresist pattern was formed on the second semiconductor layer to expose the first semiconductor layer. The exposed first semiconductor layer is surface treated for 120 seconds under conditions of a pressure of 660 Pa, an RF power of 300 W, and amounts of 5000 sccm He and 100 sccm O2. The photoresist pattern was removed and a gate insulating layer was formed on the surface treated first semiconductor layer and the second semiconductor layer by a PECVD method. A conductive layer was deposited on the gate insulating layer and patterned, so that a first gate electrode and a second gate electrode respectively overlapping the first semiconductor layer and the second semiconductor layer were formed. An interlayer insulating layer was formed on the gate electrodes. Contact holes were formed in the interlayer insulating layer, and the conductive layer was deposited and patterned on the substrate where the contact holes were formed. Therefore, a first source electrode and a first drain electrode respectively connected to both ends of the first semiconductor layer, and a second source electrode and a second drain electrode respectively connected to both ends of the second semiconductor layer were formed. Thus, a pixel TFT having the first semiconductor layer, the first gate electrode and the first source and drain electrodes, and a circuit TFT having the second semiconductor layer, the second gate electrode and the second source and drain electrodes were fabricated.

FABRICATION EXAMPLE 2 OF PIXEL AND CIRCUIT TFTS

Except that a surface of a first semiconductor layer was treated for 120 seconds under conditions of a pressure of 660 Pa, an RF power of 700 W, and amounts of 5000 sccm He and 500 sccm O2, pixel and circuit TFTs of the Fabrication Example 2 were fabricated in the same manner as in the Fabrication Example 1.

COMPARATIVE EXAMPLE OF PIXEL AND CIRCUIT TFTS

Except that, after forming a first semiconductor layer and a second semiconductor layer, a gate insulating layer was formed on the first semiconductor layer and second semiconductor layer without performing surface treatment on the first semiconductor layer, pixel and circuit TFTs were fabricated in the same manner as in the fabrication example 1.

S-factors and standard deviations of the pixel and circuit TFTs according to the Fabrication Examples 1 and 2, and the Comparative Example were shown in Table 1.

Referring to Table 1, it may be appreciated that the S factor of the pixel TFT is larger than that of the circuit TFT in the case where the semiconductor layer of the pixel TFT is selectively surface treated with the inert gas plasma. Therefore, the pixel TFT and the circuit TFT, which have different electrical characteristics, may be fabricated on one substrate.

As described above, according to the present invention, a pixel TFT and a circuit TFT, which have different electrical characteristics, may be formed on one substrate by selectively performing surface treatment on a semiconductor layer of the pixel TFT to increase density of lattice defects on the surface of the semiconductor layer of the pixel TFT.

Although the present invention has been described with reference to certain exemplary embodiments thereof, it will be understood by those skilled in the art that a variety of modifications and variations may be made to the present invention without departing from the spirit or scope of the present invention defined in the appended claims, and their equivalents.