Switching device failure detection system and method for multilevel converters

A multilevel converter includes a plurality of phase legs each having at least two inner switching devices, at least two outer switching devices, at least two clamping diodes, a split DC link and a switching device failure detection circuit. The switching device failure detection circuit includes a logic module for each of the switching devices, a voltage calculation module and a failure detection algorithm. The logic module generates a blocking state logic signal by comparing a switching device voltage and a threshold reference voltage and the voltage calculation module determines an expected voltage blocking state for each of the switching devices based on the gate drive signals of the switching devices and an output current direction. The failure detection algorithm detects a failure condition in any of the switching devices based on the blocking state logic signals and the expected voltage blocking states of the switching devices.

BACKGROUND

This invention relates to a method for detection of switching device failure conditions in a multilevel converter.

Multilevel converters (e.g. neutral point clamped converters) are generally used in high power industrial applications such as variable speed drive (VSD) systems or in energy conversion applications such as a solar (or photovoltaic) power generation systems, wind turbine generators or marine and hydrokinetic power generation systems. The general function of the multilevel converter is to synthesize a sinusoidal voltage by several levels of voltages, typically obtained from capacitor voltage sources. A three level converter includes two capacitor voltages in series with the center tap as the neutral. Each phase leg of the three-level converter has two pairs of switching devices in series. The switching device is bidirectional in current, often realized as anti-parallel connection of a unidirectional electronic switching device (e.g. IGBT, IGCT) and a diode (free-wheeling diode).

The switching devices in a multilevel converter receive high electrical and thermal stress during short-circuit conditions or during turn-off switching of a clamped inductive load. For example if there is large power loss within the switching device due to electrical stress or overcurrent, the switching device overheats and it may lead to thermal breakdown of the switching device. Similarly, when an inductive load or inductive current is switched off, the switching device may observe overvoltage resulting into voltage breakdown of the switching device. Once a switching device is broken down or destroyed due to overheat or overvoltage, without protective measures, a chain reaction may occur resulting into destruction of the entire multilevel converter bridge. Thus, it is important to detect failures in switching devices in multilevel converters. One example of a measurement used for detecting switching device failure in IGBT converters is a desaturation circuit. However, methods using the desaturation circuit detect a failure condition only when the corresponding switching device is turned ON and do not provide any signal when the gate drive signal to the switching device is turned OFF. Thus, the desaturation circuit does not detect all possible short-circuit failure conditions.

Therefore, it is desirable to provide a method and a system that will address the foregoing issues.

BRIEF DESCRIPTION

In accordance with an embodiment of the present invention, a multilevel converter with a plurality of phase legs each having at least two inner switching devices, at least two outer switching devices, at least two clamping diodes and a split DC link is provided. The multilevel converter also includes a switching device failure detection circuit including a logic module for each of the switching devices to generate a blocking state logic signal by comparing a switching device voltage and a threshold reference voltage. The switching device failure detection circuit also includes a voltage calculation module to determine an expected voltage blocking state for each of the switching devices based on the gate drive signals of the switching devices and an output current direction. The switching device failure detection circuit further includes a failure detection algorithm to detect a failure condition in any of the switching devices based on the blocking state logic signals and the expected voltage blocking states of the switching devices.

In accordance with another embodiment of the present invention, a multilevel converter with a plurality of phase legs each having at least two inner switching devices, at least two outer switching devices, at least two clamping diodes and a split DC link is provided. The multilevel converter also includes a switching device failure detection circuit with a voltage calculation module to determine an expected output voltage at phase terminals of phase legs based on gate drive signals of switching devices and an output current direction and a failure detection algorithm to detect a failure condition in any of the switching devices by comparing the expected output voltage with an actual output voltage.

In accordance with an embodiment of the present invention, a method of determining a failure condition in switching devices of a multilevel converter comprising a split DC link and a plurality of phase legs each having at least two inner switching devices, at least two outer switching devices, at least two clamping diodes is provided. The method includes determining an expected voltage blocking state for each of the switching devices based on gate drive signals of the switching devices and an output current direction and generating a blocking state logic signals by comparing terminal voltages across the switching devices and a threshold reference voltage. The method also includes detecting failure conditions in the switching devices based on the blocking state logic signals and the voltage blocking states for the switching devices.

In accordance with yet another embodiment of the present invention, a switching device failure detection circuit for a multilevel converter comprising a split DC link and a plurality of phase legs each having at least two inner switching devices, at least two outer switching devices and at least two clamping diodes is provided. The switching device failure detection circuit includes a logic module for each of the switching devices to generate a blocking state logic signal by comparing a switching device voltage and a threshold reference voltage. The switching device failure detection circuit also includes a voltage calculation module to determine an expected voltage blocking state for each of the switching devices based on the gate drive signals of the switching devices and an output current direction. The switching device failure detection circuit further includes a failure detection algorithm to detect a failure condition in any of the switching devices based on the blocking state logic signals and the expected voltage blocking states of the switching devices.

DETAILED DESCRIPTION

As discussed in detail below, embodiments of the present invention enable a multilevel converter to convert a direct current (DC) power into an alternating current (AC) power with a switching device fault detection scheme. For example, in a three level Neutral Point Clamped (NPC) converter, a key failure mode exists when a switching device (16,18,20, or22ofFIG. 1) or a clamping diode (24or26ofFIG. 1) fails short. Under this condition, one half of the DC link, V1or V2inFIG. 1, is charged to the peak line-to-line voltage of the machine or grid side voltage. This value is typically higher than the maximum allowed blocking voltage of the switching devices and the capacitors. In this case, other switching devices or clamping diodes may be stressed in terms of voltage or current beyond their capability. Hence, this will cause additional switching devices, in particular switching devices in phase legs connected to the same DC bus, to fail after the failure of the initial switching device. The switching device failure detection scheme of the present invention provides a suitable logic circuit to detect failures in switching devices and so prevents secondary damage of multilevel converters which may be used in applications such as a solar (or photovoltaic) power generation systems, wind turbine generators or marine and hydrokinetic power generation systems.

FIG. 1illustrates a schematic10of one leg or one phase of a conventional neutral point clamped (NPC) or diode clamped three level converter and its output waveform12. One leg14of the three-level converter includes four switching devices16,18,20, and22and two clamping diodes24and26. Input voltages V1and V2are controlled to each have a voltage equal to Vdc/2, where Vdc is the total DC link voltage. Voltage V3is the phase A output voltage measured with respect to a center point28of DC link30. Switching device16is complementary to switching device20so that, when switching device16is gated on, switching device20is gated off and vice versa. Similarly, switching devices18and22are complementary.

In operation, each leg of the NPC three level converter has three switching stages. In the first switching stage, switching devices16and18are turned on and switching devices20and22are turned off. Assuming a stable operation, V1=V2=Vdc/2, and V3becomes Vdc/2. In the second switching stage, switching devices18and20are turned on while switching devices16and22are turned off. In this stage, V3is equal to zero. In the third switching stage, switching devices16and18are turned off whereas switching devices20and22are turned on. This results in V3becoming −Vdc/2 as shown in a waveform12. Thus, it can be seen that the phase voltage V3has three levels Vdc/2, −Vdc/2 and 0. When all three legs of the NPC three-phase converter are combined, then the resulting line to line voltages have five levels namely Vdc, Vdc/2, 0, −Vdc/2 and −Vdc. The three-level converter14ofFIG. 1may be increased to any level depending on the circuit topology and number of switching devices and diodes in the circuit. As the number of levels in the converter increases, the output waveform of the converter approaches a pure sine wave, resulting in lower harmonics in the output voltage. In general, the number of switching stages can be higher than three as switching devices may not be gated on if the corresponding free-wheeling diode is going to conduct current. This operation mode does not affect the number of levels of the output phase voltage.

FIG. 2shows a fault condition60in one leg40of a multilevel converter. As described earlier, each leg40of the converter includes two outer and two inner switching devices for example,42,48, and44,46respectively. Further, leg40comprises two clamping diodes50and52and its output voltage V0is measured between a center point49of leg40and a center point51of DC link53. Leg40is connected to a split DC link53with a top capacitor56and a bottom capacitor58.FIG. 2shows outer switching device42of leg40failing short (represented by referral numeral60). The condition may occur as a result of occurrences such as, for example, thermal breakdown of outer switching device42, the voltage breakdown of outer switching device42, failures due to cosmic rays, and failures due to weak manufacturing of the switching device. For example, when the bottom two switching devices46,48are gated on with the goal of having Vo=−Vdc/2, the voltage that appears across inner switching device44will be the total DC link voltage i.e. Vdc, which could result in a failure for switching device44.

FIG. 3shows a switching device failure detection circuit70in accordance with an embodiment of the present invention. The circuit includes logic modules or comparators72,74,76, and78, each corresponding to a respective one of the switching devices42,44,46, and48(FIG. 2). Switching device failure detection circuit70further includes a voltage calculation module80, and a failure detection algorithm82. Each comparator72,74,76, and78compares two inputs, i) a switching device voltage i.e. a voltage across a switching device Vsw and ii) a threshold reference voltage Vth and provides an output voltage referred as blocking state logic signal Vc. In one embodiment, the threshold reference voltage Vth is set slightly higher than the rated voltage drop across the switching device when it is conducting. In another embodiment, this signal is typically already available from de-saturation detection circuit, e.g. in IGBT converters. In yet another embodiment, the threshold reference voltage Vth may be set to an arbitrary suitable level between the voltage in the previous embodiment i.e., slightly higher than the rated voltage drop across the switching device and the lower limit of Vdc/2. In one embodiment, the blocking state logic signal Vc is ‘high’ if Vsw is greater than Vth else it is ‘low’. It should be noted that ‘high’ refers to the positive supply voltage of the comparator and ‘low’ refers to the negative supply voltage of the comparator. Thus, comparator72compares Vsw1and Vth and outputs Vc1, where Vsw1refers to voltage across switching device42, comparator74compares voltage across switching device44, Vsw2and Vth and outputs Vc2. Similarly, comparator76compares Vsw3, which is voltage across switching device46and Vth, and outputs Vc3, and comparator78compares voltage across switching device48, Vsw4and Vth and outputs Vc4. In one embodiment, the comparator may be an open loop operational amplifier circuit or a dedicated voltage comparator integrated within a chip. In another embodiment, a portion of a desaturation circuit generally used in IGBT drivers, which provides a threshold voltage logic signal, may also be used as comparator.

Based on the gate signals of the switching devices42,44,46and48and an output current direction (i.e. Io direction), voltage calculation module80determines whether in the current switching stage, each switching device is suppose to block a voltage across its terminals or not. Outputs of voltage calculation module are expected voltage blocking states Vs1, Vs2, Vs3and Vs4for the switching devices that are input into switching device failure detection algorithm82. An expected voltage Vexp at the output terminal points49and51of a leg of the multilevel converter during normal condition is calculated as an intermediate step in voltage calculation module80. The expected voltage is determined based on the inputs such as gate drive signals G1, G2, G3, and G4for switching devices42,44,46, and48and the corresponding output current direction i.e., Io direction. The expected output voltage Vexp has three levels, positive, negative, and zero. Based on these levels, the gate drive signals and the output current direction the determination of whether a particular switching device should block the voltage or not is made and thus, the logic signals Vs1, Vs2, Vs3and Vs4are generated. If any of the logic signals is high, it indicates that the particular switching device should block the voltage else it should not. Switching device failure detection algorithm82then compares for each switching devices the information whether a device is actually blocking or not (i.e. Vc1, Vc2, Vc3, and Vc4) with the information whether each device should be blocking or not (i.e. Vs1, Vs2, Vs3, and Vs4) in the current switching stage. If actual blocking state and expected blocking state of any switching device do not match (for example if Vc1≠Vs1), a failure is detected.

The above switching device failure detection circuit70may be implemented in the analog domain, or the digital domain, or a combination thereof. Where digital circuitry is used for processing, the circuitry will generally include analog-to-digital conversion, although analog processing components will generally not require such conversion unless some processing is done in the digital domain. Examples of digital circuitry include digital components, such as a programmed microprocessor, field programmable gate array (FPGA), application specific digital signal processor (DSP) or the like. It should be noted that the particular order of processing as represented by the components shown inFIG. 3may be altered, and other components may be included in the overall circuitry, where desired.

FIG. 4shows one example implementation of expected voltage calculation module81for determining expected output voltage at the multilevel converter terminals. Module81receives inputs such as gate drive signals G1, G2, G3, and G4for switching devices42,44,46, and48respectively and also output current or Io direction. It should be noted the gate drive signal levels determine whether any switching device is ON or not. For example, if G2or G3is high, switching device44or46is ON respectively. Thus, for all the cases presented below if the switching device is ON, the corresponding gate drive signal is referred to as high. In first step83, it is determined whether any one of inner switching devices44or46are ON and whether both outer switching devices42and48are OFF. In such a situation, one of clamping diodes50or52conducts, and thus expected voltage Vexp is equivalent to zero as represented by a block84. This condition is represented in step83by a Boolean equation, (G2+G3)·(G1+G4)=1. However, if this condition is not met, then in step86, it is determined whether both top switching devices42and44are ON i.e., whether G1·G2=1. If both top switching devices are ON then expected voltage Vexp at the output terminals should be a positive voltage i.e. V+, represented by a block88. If the condition checked in step86is not met, then step90determines whether both bottom switching devices46and48are ON i.e., whether G3·G4=1. Both bottom switching devices46and48being ON indicates that expected voltage Vexp should be a negative voltage i.e., V− represented by a block92. If any of the conditions83,86or90is not met, then output current (Io) direction helps in determining expected voltage Vexp. In step94, it is determined whether output current Io is negative or not. If output current Io is negative, then in step96it is determined whether all switching devices42,44,46, and48are OFF. This condition is represented in step96by (G1+G2+G3+G4)=1. If all switching devices are OFF and output current Io is negative, it indicates that freewheeling diodes of top two switching devices are conducting. Thus, expected voltage Vexp during this condition will be positive voltage V+, represented by block88. If it is determined in step94, that output current Io is not negative, then in step98it is determined whether the output current Io is positive or not. If output current Io is positive, in step100, it is again determined whether all switching devices are OFF. If all switching devices are OFF and current direction is positive, it indicates that freewheeling diodes of bottom two switching devices are conducting and the expected voltage during this condition will be negative voltage V−.

FIG. 5shows a failure detection algorithm110in accordance with an embodiment of the present invention. Algorithm110determines whether any switching device that should block a DC voltage is actually not blocking DC voltage. In step112of algorithm110, it is determined whether expected voltage Vexp is positive (V+) or not. If Vexp is not equal to V+, i.e., if Vexp is equal to negative voltage V− or zero voltage, then in step114it is checked whether blocking state logic signal Vc1of first switching device42is low or high. If Vc1is low then it indicates that switching device42is not blocking any voltage when actually it should block the voltage. The fault indication or the short circuit indication is then provided as shown in block116. Another condition that is checked if Vexp is not equal to V+ is whether Vexp is negative voltage i.e., V−. If it is determined in step118that Vexp is indeed V-, then in step120it is checked whether blocking state logic signal Vc2for switching device44is low. If Vc2is low then second switching device44is considered to be faulty as shown in block122. If it is determined in step124that Vexp is positive voltage i.e., V+, then in step124, blocking state logic signal Vc3for switching device46is compared with the low voltage. If it is found that Vc3is low then it means switching device46is faulty as shown in block126. Further, if Vexp is zero as determined from step118or positive as determined from step112, then in step128, it is checked whether blocking state logic signal Vc4for switching device48is low. If Vc4is low then it is indication of switching device48being faulty as shown in block130. Thus, in this way with various combinations, failure conditions of switching devices are determined.

FIG. 6shows another failure detection algorithm150in accordance with an embodiment of the present invention. Algorithm150is complementary to algorithm110i.e., it determines whether any switching device that is not expected to block any voltage is actually blocking the voltage. In step152of algorithm150, it is determined whether expected voltage Vexp is positive (i.e., i.e., V+). If Vexp is positive, then it is checked in step154whether blocking state logic signal Vc1of first switching device (42ofFIG. 2) is low or high. If Vc1is high then it indicates that switching device42is faulty as shown in block156. Further, if it is determined that Vexp is not positive i.e., either it is negative or zero, then it is checked whether blocking state logic signal Vc3for switching device46is high or low in step158, and, if it is determined that Vc3is high, then that indicates switching device46is faulty as shown in block160. It is checked from step162whether Vexp is negative i.e., V−, and, if yes, then it is determined from step164whether blocking state logic signal Vc4for switching device48is high or low. If Vc4is high then it indicates that switching device48is faulty as shown in block166. Further, if it is determined from step152that Vexp is V+ or from step162that Vexp is zero, then it is checked in step168, whether blocking state logic signal Vc2for switching device44is high or not. If Vc2turns out to be high, then it means switching device44is faulty as shown in block170. It should be noted that the steps presented inFIG. 4,5or6are not restricted by their sequence. In one embodiment, some of the steps can be performed in parallel or in another embodiment; the sequence of the steps can be interchanged as long as it does not affect the final outcome.

FIG. 7is another switching device failure detection circuit180in accordance with an embodiment of the present invention. Switching device failure detection circuit180utilizes voltage calculation module80described inFIG. 4. Circuit180further utilizes a failure detection algorithm182to detect failures in switching devices. Algorithm182compares expected voltage Vexp with actual voltage measured from multilevel converter leg output terminals. If there is mismatch it indicates failure of a switching device. For example, if Vexp is positive voltage and actual voltage is zero then it indicates that switching device46is short circuited. Thus, failure detection algorithm182detects failures in various switching devices.