Method of manufacturing semiconductor structure with improved etching process

The present disclosure provides a manufacturing method of a semiconductor structure. The method includes: forming a conformal layer over a first patterned layer over a substrate; forming a second layer over the conformal layer and between portions of the first patterned layer; performing a first etching to form a second patterned layer and a patterned conformal layer; performing a second etching to remove a portion of the first patterned layer to form a first inclined member of the first patterned layer tapered away from the substrate and lining a vertical portion of the patterned conformal layer, and to remove a portion of the second patterned layer to form a second inclined member of the second patterned layer tapered away from the substrate and lining the vertical portion of the patterned conformal layer; and performing a third etching to remove the vertical portions of the patterned conformal layer.

TECHNICAL FIELD

The present disclosure relates to a method of manufacturing a semiconductor structure. Particularly, the present disclosure relates to an improved technique for patterning processes.

DISCUSSION OF THE BACKGROUND

Semiconductor devices are used in a variety of electronic applications, such as personal computers, cellular phones, digital cameras, and other electronic equipment. The semiconductor devices are typically fabricated by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductive layers of material over a semiconductor substrate, and patterning the various material layers using lithography to form circuit components and elements thereon. As the semiconductor industry has progressed into advanced technology process nodes in pursuit of greater device density, higher performance, and lower costs, challenges of precise control of lithography across a wafer have arisen.

SUMMARY

One aspect of the present disclosure provides a method of manufacturing a semiconductor structure. The method includes forming a first patterned layer over a substrate; forming a conformal layer over the first patterned layer; forming a second layer over the conformal layer and between portions of the first patterned layer; performing a first etching to remove portions of the second layer and the conformal layer disposed over the first patterned layer, thereby forming a second patterned layer and a patterned conformal layer; performing a second etching to form a first inclined member of the first patterned layer tapered away from the substrate and lining a vertical portion of the patterned conformal layer, and to form a second inclined member of the second patterned layer tapered away from the substrate and lining the vertical portion of the patterned conformal layer; and performing a third etching to remove the vertical portions of the patterned conformal layer.

In some embodiments, the method further includes: providing the substrate; and forming a plurality of recesses in the substrate.

In some embodiments, the plurality of recesses are filled by the conformal layer.

In some embodiments, the method further includes: forming a first layer over the substrate; and removing portions of the first layer to form the first patterned layer.

In some embodiments, the method further includes: forming a first layer over the substrate; and removing portions of the first layer to form the first patterned layer.

In some embodiments, the first patterned layer includes rounded corners.

In some embodiments, the first etching stops when the rounded corners of the first patterned layer are entirely removed.

In some embodiments, rounded corners of the conformal layer are disposed over the rounded corners of the first patterned layer.

In some embodiments, the first etching stops when the rounded corners of the conformal layer are entirely removed.

In some embodiments, the first etching is a low-selectivity etching.

In some embodiments, the second etching or the third etching is a high-selectivity etching.

In some embodiments, a first etching rate of the low-selectivity etching to the first patterned layer is substantially equal to a second etching rate of the low-selectivity etching to the conformal layer.

In some embodiments, the first inclined member and the second inclined member are removed by the third etching.

In some embodiments, a top surface of the first patterned layer is substantially coplanar with a top surface of the second patterned layer after the third etching.

Another aspect of the present disclosure provides a method of manufacturing a semiconductor structure. The method includes forming a first patterned layer over a substrate; forming a second patterned layer over the substrate and alternately arranged with the first patterned layer; forming a patterned conformal layer disposed between the first patterned layer and the second patterned layer, wherein top surfaces of the first patterned layer, the patterned conformal layer, and the second patterned layer are substantially coplanar; forming a first recess extending into the first patterned layer and surrounded by the patterned conformal layer; removing vertical portions of the patterned conformal layer; and planarizing top surfaces of the first patterned layer and the second patterned layer.

In some embodiments, the method further includes: forming a plurality of recesses on the substrate prior to the formation of the first patterned layer; and forming a conformal layer prior to the formation of the second patterned layer, wherein the conformal layer is conformal to the substrate and the first patterned layer.

In some embodiments, sidewalls of the first patterned layer are substantially aligned with sidewalls of the plurality of recesses on the substrate.

In some embodiments, at least a portion of the patterned conformal layer is disposed below the first patterned layer.

In some embodiments, the method further includes: forming a second recess extending into the second patterned layer, concurrently with the formation of the first recess.

In some embodiments, the first recess is formed by a dry etching.

In some embodiments, the removal of the vertical portions of the patterned conformal layer and the planarizing of the top surfaces of the first patterned layer and the second patterned layer are performed concurrently.

In some embodiments, a directional dry etching is performed to remove the vertical portions of the patterned conformal layer and to planarize the top surfaces of the first patterned layer and the second patterned layer.

In some embodiments, the directional dry etching has a high selectivity to the patterned conformal layer.

In some embodiments, the second patterned layer is separated from the first patterned layer by a plurality of gaps and from the substrate by the patterned conformal layer after the planarization.

In some embodiments, the first patterned layer includes a first height substantially equal to a height of the patterned conformal layer and a second height substantially less than the height of the patterned conformal layer.

In some embodiments, the first patterned layer and the second patterned layer include a same material.

In some embodiments, the patterned conformal layer includes a material different from that of the first patterned layer or the second patterned layer.

Another aspect of the present disclosure provides a method of manufacturing a semiconductor structure. The method includes providing a substrate; forming a first layer over the substrate; patterning the first layer to form a first patterned layer and to expose portions of the substrate; forming a conformal layer over the first patterned layer and the substrate; forming a second layer over the conformal layer, wherein the second layer at least fills between different portions of the first patterned layer; removing portions of the conformal layer and the second layer disposed over the first patterned layer to form a patterned conformal layer and a second patterned layer, wherein top surfaces of the first patterned layer, the second patterned layer and the patterned conformal layer are substantially coplanar; performing a first etching to form a first recess on the first patterned layer and a second recess on the second patterned layer, wherein each of the first recess and the second recess is surrounded by the patterned conformal layer; and performing a second etching to remove portions of the patterned conformal layer to separate the first patterned layer and the second patterned layer by a plurality of gaps.

In some embodiments, the method further includes: transferring a pattern of the first patterned layer and the second patterned layer to the substrate.

In some embodiments, the pattern is transferred to a topmost layer of the substrate.

In some embodiments, a top surface of the substrate is substantially planar.

In some embodiments, a horizontal portion of the conformal layer is in contact with the substrate.

In some embodiments, the first layer or the second layer includes oxide.

In some embodiments, the conformal layer includes nitride.

In some embodiments, a total thickness of the second patterned layer and the conformal layer is substantially greater than a thickness of the first patterned layer.

In some embodiments, the method further includes: forming a sacrificial layer over the second layer, wherein a top surface of the sacrificial layer is substantially planar.

The foregoing has outlined rather broadly the features and technical advantages of the present disclosure in order that the detailed description of the disclosure that follows may be better understood. Additional features and technical advantages of the disclosure are described hereinafter, and form the subject of the claims of the disclosure. It should be appreciated by those skilled in the art that the concepts and specific embodiments disclosed may be utilized as a basis for modifying or designing other structures, or processes, for carrying out the purposes of the present disclosure. It should also be realized by those skilled in the art that such equivalent constructions do not depart from the spirit or scope of the disclosure as set forth in the appended claims.

DETAILED DESCRIPTION

As the semiconductor industry has progressed into advanced technology process nodes in pursuit of greater device density, it has reached an advanced precision of photolithography. In order to further reduce device sizes, a double patterning technique has been developed in which multiple hard layers are patterned at a same elevation to compose one pattern to be transferred to a target layer. The multiple hard layers undergo multiple operations, such as deposition, etching, planarization and so forth, and the pattern formed by the multiple hard layers may have an uneven top surface after the multiple operations. The uneven top surfaces of the pattern result in an uneven etching result on the target layer. The present disclosure relates to a method for manufacturing a semiconductor structure. In particular, the method of the present disclosure is able to provide a planar surface of a pattern so as to avoid the uneven etching result. A performance of a device formed according to the method and a product yield can be thereby improved.

FIG.1is a flow diagram illustrating a method S1for manufacturing a semiconductor device in accordance with some embodiments of the present disclosure. The method S1includes a number of operations (S11, S12, S13, S14, S15and S16) and the description and illustration are not deemed as a limitation to the sequence of the operations. In the operation511, a first patterned layer is formed over a substrate. In the operation S12, a conformal layer is formed over the first patterned layer. In the operation S13, a second layer is formed over the conformal layer and between portions of the first patterned layer. In the operation S14, a first etching is performed to remove portions of the second layer and the conformal layer disposed over the first patterned layer, thereby forming a second patterned layer and a patterned conformal layer. In the operation S15, a second etching is performed to form a first inclined member of the first patterned layer tapered away from the substrate and lining a vertical portion of the patterned conformal layer, and to form a second inclined member of the second patterned layer tapered away from the substrate and lining the vertical portion of the patterned conformal layer. In the operation S16, a third etching is performed to remove the vertical portions of the patterned conformal layer.

FIG.2is a flow diagram illustrating a method S2for manufacturing a semiconductor device in accordance with some embodiments of the present disclosure. The method S2includes a number of operations (S21, S22, S23, S24, S25and S26) and the description and illustration are not deemed as a limitation to the sequence of the operations. In the operation S21, a first patterned layer is formed over a substrate. In the operation S22, a second patterned layer is formed over the substrate and alternately arranged with the first patterned layer. In the operation S23, a patterned conformal layer is formed between the first patterned layer and the second patterned layer, wherein top surfaces of the first patterned layer, the patterned conformal layer, and the second patterned layer are substantially coplanar. In the operation S24, a first recess is formed extending into the first patterned layer and surrounded by the patterned conformal layer. In the operation S25, vertical portions of the patterned conformal layer are removed. In the operation S26, top surfaces of the first patterned layer and the second patterned layer are planarized.

FIG.3is a flow diagram illustrating a method S3for manufacturing a semiconductor device in accordance with some embodiments of the present disclosure. The method S3includes a number of operations (S31, S32, S33, S34, S35, S36, S37and S38) and the description and illustration are not deemed as a limitation to the sequence of the operations. In the operation S31, a substrate is provided. In the operation S32, a first layer is formed over the substrate. In the operation S33, the first layer is patterned to form a first patterned layer and to expose portions of the substrate. In the operation S34, a conformal layer is formed over the first patterned layer and the substrate. In the operation S35, a second layer is formed over the conformal layer, wherein the second layer at least fills between different portions of the first patterned layer. In the operation S36, portions of the conformal layer and the second layer over the first patterned layer is removed to form a patterned conformal layer and a second patterned layer, wherein top surfaces of the first patterned layer, the second patterned layer and the patterned conformal layer are substantially coplanar. In the operation S37, a first etching is performed to form a first recess in the first patterned layer and a second recess in the second patterned layer, wherein each of the first recess and the second recess is surrounded by the patterned conformal layer. In the operation S38, a second etching is performed to remove portions of the patterned conformal layer to separate the first patterned layer and the second patterned layer by a plurality of gaps.

The method S1, the method S2and the method S3are within a same concept of the present disclosure, and in order to further illustrate details of the method S1, the method S2, the method S3, and the concept of the present disclosure, the method S1, the method S2and the method S3are comprehensively described with embodiments of the present disclosure.

FIGS.4to19are schematic diagrams illustrating various fabrication stages constructed according to the method S1, S2or S3for manufacturing a semiconductor structure10in accordance with some embodiments of the present disclosure. The stages shown inFIGS.4to19are also illustrated schematically in the process flow inFIG.1,2or3. In the subsequent discussion, the fabrication stages shown inFIGS.4to16are discussed in reference to the process steps inFIG.1,2or3.

Referring toFIG.4,FIG.4is a schematic cross-sectional diagram at a stage of the method S1, the method S2and/or the method S3in accordance with some embodiments of the present disclosure. Prior to the operation S11, the operation S21and/or in the operation S31, a substrate11is provided, received, or formed.

The substrate11may be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, or the like. The substrate11can include an elementary semiconductor including silicon or germanium in a single crystal form, a polycrystalline form, or an amorphous form; a compound semiconductor material including at least one of silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and indium antimonide; an alloy semiconductor material including at least one of SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and GaInAsP; any other suitable materials; or a combination thereof. In some embodiments, the alloy semiconductor substrate may be a SiGe alloy with a gradient Si:Ge feature in which Si and Ge compositions change from one ratio at one location to another ratio at another location of the gradient SiGe feature. In another embodiment, the SiGe alloy is formed over a silicon substrate. In some embodiments, a SiGe alloy can be mechanically strained by another material in contact with the SiGe alloy.

In some embodiments, the substrate11may have a multilayer structure, or the substrate11may include a multilayer compound semiconductor structure. In some embodiments, the substrate11includes semiconductor devices, electrical components, electrical elements or a combination thereof. In some embodiments, the substrate11includes transistors or functional units of transistors. For a purpose of simplicity, the substrate11depicted inFIG.4can be a topmost layer of a multilayer structure of the substrate11. In some embodiments, the topmost layer of the substrate11includes crystalline silicon.

Referring toFIG.5,FIG.5is a schematic cross-sectional diagram at a stage of the method S1, the method S2and/or the method S3in accordance with some embodiments of the present disclosure. After the substrate11is provided, received or formed, prior to the operation S11, prior to the operation S12and/or in the operation S32, a first layer12is formed over the substrate11. In some embodiments, the first layer12is formed over a top surface11A of the substrate11. In some embodiments, a thickness of the first layer12is in a range of 50 to 500 nanometers (nm). In some embodiments, the first layer12includes one or more dielectric materials. In some embodiments, the dielectric material includes silicon oxide (SiOx), silicon nitride (SixNy), silicon oxynitride (SiON), or a combination thereof. In some embodiments, the first layer12includes silicon dioxide (SiO2).

In some embodiments, the dielectric material includes a polymeric material, an organic material, an inorganic material, a photoresist material or a combination thereof. In some embodiments, the dielectric material includes one or more low-k dielectric materials having a dielectric constant (k value) less than 3.9. In some embodiments, the low-k dielectric material includes fluorine-doped silicon dioxide, organosilicate glass (OSG), carbon-doped oxide (CDO), porous silicon dioxide, spin-on organic polymeric dielectrics, spin-on silicon based polymeric dielectrics, or a combination thereof. In some embodiments, the dielectric material includes one or more high-k dielectric materials having a dielectric constant (k value) greater than 3.9. The high-k dielectric material may include hafnium oxide (HfO2), zirconium oxide (ZrO2), lanthanum oxide (La2O3), yttrium oxide (Y2O3), aluminum oxide (Al2O3), titanium oxide (TiO2) or another applicable material. Other suitable materials are within the contemplated scope of this disclosure.

In some embodiments, the first layer12is formed by a blanket deposition. In some embodiments, the first layer12is formed by a chemical vapor deposition (CVD), a physical vapor deposition (PVD), an atomic layer deposition (ALD), a low-pressure chemical vapor deposition (LPCVD), a plasma-enhanced CVD (PECVD), or a combination thereof.

Referring toFIG.6,FIG.6is a schematic cross-sectional diagram at a stage of the method S1, the method S2and/or the method S3in accordance with some embodiments of the present disclosure. Prior to the operation S11, the operation S21and/or the operation S33, a photoresist layer21is formed over the first layer12. In some embodiments, portions of the first layer12are defined by and exposed through the photoresist layer21. The photoresist layer21is configured to protect portions of the first layer12covered by the photoresist layer21during a patterning operation that is subsequently performed.

Referring toFIG.7,FIG.7is a schematic cross-sectional diagram at a stage of the method S1, the method S2and/or the method S3in accordance with some embodiments of the present disclosure. In the operation S11, the operation S21and/or the operation S33, the first layer12is patterned to expose portions of the substrate11and form a first patterned layer121, wherein the first patterned layer121includes a plurality of portions as shown inFIG.7, and at least one opening31is defined between adjacent portions of the first patterned layer121.

In some embodiments, the patterning of the first layer12includes lift-off, ion beam etching, directional dry etching, reactive ion etching, solution wet etching, or a combination thereof. In some embodiments, the first patterned layer121is defined by the photoresist layer21shown inFIG.6. In some embodiments, after the formation of the first layer12, pre-cleaning, photoresist application (formation of the photoresist layer21), exposure, developing and etching are sequentially performed to form the first patterned layer121.

Referring toFIG.8,FIG.8is a schematic cross-sectional diagram at a stage of the method S1, the method S2and/or the method S3in accordance with some embodiments of the present disclosure. After the operation S11, the operation S21and/or the operation S33, surficial portions of the substrate11exposed through the first patterned layer121are removed to form at least one recess182extending from the top surface11A into the substrate11. In some embodiments, the recess182is connected to the opening31. In some embodiments, a sidewall121A of the first patterned layer121is substantially aligned with a sidewall182A of the recess182. In some embodiments, a distance41between adjacent portions of the first patterned layer121defines a width42of the recess182.

In some embodiments, corner portions of the first patterned layer121shown inFIG.7are removed concurrently with the formation of the recess182. In some embodiments, rounded corners61of the first patterned layer121are formed concurrently with the formation of the recess182. In some embodiments, the recess182can be formed prior to the formation of the first layer12or after the formation of the first patterned layer121. In some embodiments, the recess182is formed by an ion beam etching, a directional dry etching, a reactive ion etching, a solution wet etching, or a combination thereof. It should be noted that, in other manufacturing methods of different applications, the formation of the recess182may be omitted. In some embodiments, the recess182is formed if the method S1, S2or S3is applied in formation of a memory device. In some embodiments without the formation of the recess182, the subsequent process of the method S1, S2and/or S3is performed on the interim structure as shown inFIG.7.

Referring toFIG.9,FIG.9is a schematic cross-sectional diagram at a stage of the method S1, the method S2and/or the method S3in accordance with some embodiments of the present disclosure. In the operation S12, prior to the operation S22, and/or in the operation S34, a conformal layer13is formed over the first patterned layer121and the substrate11. In some embodiments, a profile of the conformal layer13is conformal to a profile of the first patterned layer121and the substrate11. In some embodiments, the conformal layer13includes rounded corners62disposed over the rounded corners61of the first patterned layer121.

In some embodiments, the conformal layer13includes horizontal portions13alining the top surface11A of the substrate11, upper portions13clining a top surface12A and the rounded corners61of the first patterned layer121, and vertical portions13bconnecting the horizontal portions13aand the upper portions13c. For a purpose of illustration, a dashed line is depicted inFIG.9to indicate an intersection between the vertical portion13band the upper portion13c. In some embodiments, the conformal layer13lines the openings31. In some embodiments, the conformal layer13lines sidewalls of portions of the first patterned layer121and portions of the top surface11A of the substrate11in the openings31. In some embodiments, the conformal layer13is in contact with the top surface12A of the first patterned layer121, the sidewall121A of the first patterned layer121, and the top surface11A of the substrate11. In some embodiments, at least the horizontal portions13aare disposed in the recess182. The horizontal portions13aof the conformal layer13may be partially or entirely below the first patterned layer121depending on a depth of the recess182and a thickness136of the conformal layer13. In some embodiments, the thickness136of the conformal layer13is configured to define a distance (or a width of a gap) between adjacent portions of a patterned layer of the substrate11to be formed. In some embodiments, the thickness136is substantially consistent throughout the entire conformal layer13. In some embodiments, an entirety of the horizontal portions13ais disposed in the recess182. In some embodiments, a distance43between adjacent vertical portions13bin the opening31is configured to define a width of a second patterned layer to be formed later in the process.

In some embodiments, the conformal layer13is formed by a chemical vapor deposition (CVD), a physical vapor deposition (PVD), an atomic layer deposition (ALD), a low-pressure chemical vapor deposition (LPCVD), a plasma-enhanced CVD (PECVD), or a combination thereof. In some embodiments, the conformal layer13includes one or more dielectric materials. The dielectric material of the conformal layer13may be selected from the dielectric materials described in reference to the first layer12, and repeated description is omitted herein. In some embodiments, the dielectric material of the conformal layer13is different from that of the first patterned layer121for a purpose of etching to be performed later in the process. In some embodiments, the first patterned layer121includes oxide, and the conformal layer13includes nitride. In some embodiments, a thickness of the conformal layer13is in a range of 5 to 50 nm. In some embodiments, the thickness of the conformal layer13is substantially consistent throughout the entire conformal layer13.

Referring toFIG.10,FIG.10is a schematic cross-sectional diagram at a stage of the method S1, the method S2and/or the method S3in accordance with some embodiments of the present disclosure. In the operation S13, prior to the operation S22and/or prior to the operation S35, a second layer14is formed over the conformal layer13. In some embodiments, the second layer14is formed by a blanket deposition. In some embodiments, the second layer14at least fills the openings31. In some embodiments, the second layer14is disposed over the first patterned layer121and between portions of the first patterned layer121. In some embodiments, a thickness of the second layer14is substantially greater than one-half of the distance43for a purpose of filling the opening31. In some embodiments, the thickness of the second layer14is substantially greater than a thickness of the first layer12. In some embodiments, a top surface14A of the second layer14is not a planar surface. In some embodiments, the top surface14aof the second layer14includes a plurality of recesses32disposed on each of the openings31due to a property of a deposition. In some embodiments, the recess32is vertically over a central region of a corresponding opening31.

In some embodiments, a portion of the second layer14is disposed in the recess182. In some embodiments, the second layer14is entirely above the recess182or the substrate11. In some embodiments, the formation of the second layer14includes a chemical vapor deposition (CVD), a physical vapor deposition (PVD), or a combination thereof. In some embodiments, the second layer14includes one or more dielectric materials. The dielectric material of the second layer14may be selected from the dielectric materials described in reference to the first layer12, and repeated description is omitted herein. In some embodiments, the dielectric material of the second layer14is the same as that of the first patterned layer121for a purpose of etching to be performed later in the process. In some embodiments, the second layer14includes oxide.

Referring toFIG.11,FIG.11is a schematic cross-sectional diagram at a stage of the method S1, the method S2and/or the method S3in accordance with some embodiments of the present disclosure. Prior to the operation S14, prior to the operation S22and/or prior to the operation S36, a sacrificial layer15is formed over the second layer14. In some embodiments, the sacrificial layer15is in physical contact with the top surface14A of the second layer14. In some embodiments, the sacrificial layer15fills the recesses32. In some embodiments, a top surface15A of the sacrificial layer15is substantially planar. In some embodiments, the sacrificial layer15is configured to provide a planar surface for an etching operation to be performed in the subsequent processing in order to provide a better etching result. In some embodiments, the sacrificial layer15includes a dielectric material, an anti-reflective coating material, an oxide-containing material, or other suitable materials.

Referring toFIG.12,FIG.12is a schematic cross-sectional diagram at a stage of the method S1, the method S2and/or the method S3in accordance with some embodiments of the present disclosure. In the operation S14, the operation S23and/or prior to the operation S36, a first etching51is performed to remove upper portions of the first patterned layer121, portions of the conformal layer13, and portions of the second layer14. In some embodiments, the first etching51includes ion beam etching, directional dry etching, reactive ion etching, solution wet etching, or a combination thereof. In some embodiments, the first etching operation51includes a low-selectivity etching. In some embodiments, the low-selectivity etching includes a low etching selectivity between two of the sacrificial layer15, the second layer14, the conformal layer13, and the first patterned layer121. In some embodiments, the low-selectivity etching includes an etching rate to the second layer14substantially equal to an etching rate to the conformal layer13. In some embodiments, the etching rate of the low-selectivity etching to the conformal layer13is substantially equal to an etching rate of the low-selectivity etching to the first patterned layer121. In some embodiments, the low-selectivity etching includes an oxide to nitride selectivity less than 3. In some embodiments, a detection of a material of the conformal layer13at an etched surface is performed after a certain duration of the first etching. A result of the detection can indicate the exposure of the first patterned layer121.

In some embodiments, the first etching51stops when the rounded corners61of the first patterned layer121are entirely removed. In some embodiments, the first etching51stops when the rounded corners62of the conformal layer13are entirely removed. In some embodiments, the first etching51stops at a line171. In some embodiments, the line171is at or below a bottom of the rounded corners62of the conformal layer13. In some embodiments, the line171is at or below the intersection (as indicated inFIG.7) of the upper portion13cand the vertical portion13b.

Referring toFIG.13,FIG.13is a schematic cross-sectional diagram at a stage of the method S1, the method S2and/or the method S3in accordance with some embodiments of the present disclosure.FIG.13shows a resulting structure of the first etching51. In some embodiments, the sacrificial layer15is entirely removed by the first etching51. In some embodiments, portions of the second layer14over the first patterned layer121shown inFIG.12are removed by the first etching51to form a second patterned layer141. In some embodiments, the upper portions13cshown inFIG.12of the conformal layer13are removed by the first etching51to form a patterned conformal layer131. In some embodiments, an entirety of the upper portions13cof the conformal layer13are removed by the first etching51. As a result, the second patterned layer141and the patterned conformal layer131are formed. The second patterned layer141is alternately arranged with the first patterned layer121. In some embodiments, the second patterned layer141includes portions of the second layer14surrounded by the patterned conformal layer131. In some embodiments, the patterned conformal layer131includes the vertical portion13band the horizontal portion13a. In some embodiments, the patterned conformal layer131covers only inner surfaces of the openings31shown inFIG.8. In some embodiments, the second patterned layer141is separated from the substrate11and the first patterned layer121by the patterned conformal layer131. In some embodiments, the second patterned layer141is separated from the substrate11by the horizontal portions13aof the patterned conformal layer131and from the first patterned layer121by vertical portions of the conformal layer131.

In some embodiments, the upper portions of the first patterned layer121having rounded corners61as shown inFIG.12are removed by the first etching51. In some embodiments, the rounded corners61of the first patterned layer121are removed by the first etching51. In some embodiments, an entirety of the rounded corners61of the first patterned layer121are removed by the first etching51. In some embodiments, a thickness71of the first patterned layer121shown inFIG.11prior to the first etching51is substantially greater than a thickness72of the first patterned layer121after the etching51shown inFIG.13. However, the present disclosure is not limited thereto. As mentioned above, the operation shown inFIG.8for forming the plurality of recesses42in the substrate11can be omitted. In some embodiments, as shown inFIG.7, the first etching51may stop at an exposure of the first patterned layer121, and upper portions of the first patterned layer121may be left in place after the first etching51. In some embodiments, the thickness71of the first patterned layer121shown inFIG.11prior to the first etching51is substantially equal to the thickness72of the first patterned layer121after the etching51shown inFIG.13. In some embodiments, top surfaces12b,13band14bof the first patterned layer121, the patterned conformal layer131and the second patterned layer141respectively are substantially coplanar. In some embodiments, a height73of the patterned conformal layer131is greater than a thickness74of the second patterned layer141. In some embodiments, a thickness72of the first patterned layer121is substantially equal to or less than a total thickness of the thickness74and the thickness136of the patterned conformal layer131.

Referring toFIG.14,FIG.14is a schematic cross-sectional diagram at a stage of the method S1, the method S2and/or the method S3in accordance with some embodiments of the present disclosure. In the operation S15, the operation S24and/or prior to the operation S37, a second etching52is performed to form a first recess33in the first patterned layer121and a second recess34in the second patterned layer141. In some embodiments, the first recess33is formed in each of the portions of the first patterned layer121shown inFIG.14. In some embodiments, the second recess34is formed in each of the portions of the second patterned layer141. In some embodiments, each of the first recess33and the second recess34is surrounded by the vertical portions of the patterned conformal layer131. In some embodiments, the second etching52includes an ion beam etching, a directional dry etching, a reactive ion etching, a solution wet etching, or a combination thereof. In some embodiments, the formation of the first recess33and the formation of the second recess34include one or more directional dry etching operations. In some embodiments wherein the first patterned layer121and the second patterned layer141include a same material, the second etching52may include one etching operation having a high selectivity to the first patterned layer121and the second patterned layer141. In some embodiments wherein the first patterned layer121and the second patterned layer141include different materials, the second etching52may include multiple etching operations, where one etching operation has a high selectivity to the first patterned layer121and one etching operation has a high selectivity to the second patterned layer141. In some embodiments, surficial portions of the vertical portions13bof the patterned conformal layer131are removed. In other words, a height of the vertical portions13bcan be slightly reduced by the second etching52. In some embodiments, the reduction in the height of the vertical portions13bof the patterned layer131is negligible. In some embodiments, the height of the vertical portions13bof the patterned layer131is consistent prior to and after the second etching52.

The first recess33may be defined by a first inclined member122of the first patterned layer121, and the second recess34may be defined by a second inclined member142of the second patterned layer141. In some embodiments, the first inclined member122of the first patterned layer121is tapered away from the substrate11. In some embodiments, the second inclined member142of the second patterned layer141is tapered away from the substrate11. In some embodiments, each of the vertical portions13bof the patterned conformal layer131is surrounded by the first inclined member122and the second inclined member142. In other words, a first inclined member122and an adjacent second inclined member142line a same vertical portion13bof the patterned conformal layer131. In some embodiments, a first height751of the first patterned layer121is greater than a second height752of the first patterned layer121, wherein the first height751is measured from a top of the first inclined member122to the top surface11A of the substrate11, and the second height752is measured from a bottom of the first recess33to the top surface11A of the substrate11. In some embodiments, the first height751is substantially equal to or less than the thickness72shown inFIG.13. In some embodiments, a first height761of the second patterned layer141is greater than a second height762of the second patterned layer141, wherein the first height761is measured from a top of the second inclined member142to the top surface11A of the substrate11, and the second height762is measured from a bottom of the second recess34to the top surface11A of the substrate11. In some embodiments, the second height761is substantially equal to or less than the height74shown inFIG.13.

Referring toFIGS.15and16,FIGS.15and16are enlarged schematic diagrams of a portion of the intermediate structure in a dotted circle indicated inFIG.14in accordance with different embodiments of the present disclosure. In some embodiments, a portion of the first patterned layer121above a bottom surface33A of the first recess33is defined as the first inclined member122. In other words, a bottom124of the first inclined member122is defined by a virtual line (indicated as a dashed line) extending along the bottom surface33A of the first recess33. In some embodiments, the first inclined member122includes a top123, the bottom124, and a first inclined surface125connecting the top123and the bottom124. In some embodiments, the first inclined surface125defines (or functions as as) an inner sidewall33B of the first recess33. In some embodiments, the first inclined surface125is a concave surface due to a property of the etching operation. The first inclined surface125of the first inclined member122may or may not contact the vertical portion13bof the patterned conformal layer131. In some embodiments, as shown inFIG.15, the first inclined surface125is separated from the vertical portion13bof the patterned conformal layer131. In some embodiments, the top123of the first inclined member122is a surface, which is a portion of the top surface12B of the first patterned layer121shown inFIG.13. In such embodiments, the first height751(shown inFIG.14) is substantially equal to the thickness72of the first patterned layer121(shown inFIG.13). In some embodiments, as shown inFIG.16, the first inclined surface125contacts the vertical portion13bof the patterned conformal layer131. In some embodiments, the top123of the first inclined member122forms a point, which is a contact point between the first inclined surface125and the vertical portion13bof the patterned conformal layer131. In such embodiments, the first height751(shown inFIG.14) is substantially equal to or less than the thickness72of the first patterned layer121(shown inFIG.13). In some embodiments, as shown inFIG.16, the first inclined surface125contacts the vertical portion13bat the top surface13B of the patterned conformal layer131, and the first height751is substantially equal to the thickness72of the first patterned layer121.

Similarly, in some embodiments, a portion of the second patterned layer141above a bottom surface34aof the second recess34is defined as the second inclined member142. In other words, a bottom144of the second inclined member142is defined by a virtual line (indicated as a dashed line) extending along the bottom surface34aof the second recess34. The bottom surface34aof the second recess34may or may not be aligned with the bottom surface33aof the first recess33. In some embodiments, as shown inFIG.15, the bottom surface33aof the first recess33is at an elevation different from an elevation of the bottom surface34aof the second recess34. In some embodiments, as shown inFIG.16, the bottom surface33aof the first recess33is aligned or coplanar with the bottom surface34aof the second recess34. In some embodiments, the second inclined member142includes a top143, the bottom144, and a second inclined surface145connecting the top143and the bottom144. In some embodiments, the second inclined surface145defines (or serves as) an inner sidewall34bof the second recess34. In some embodiments, the second inclined surface145is a concave surface due to a property of the etching operation. The second inclined surface145of the second inclined member142may or may not contact the vertical portion13bof the patterned conformal layer131. In some embodiments, as shown inFIG.15, the second inclined surface145is separated from the vertical portion13bof the patterned conformal layer131. In some embodiments, the top143of the second inclined member142is a surface, which is a portion of the top surface14bof the second patterned layer141shown inFIG.13. In such embodiments, the first height761(shown inFIG.14) is substantially equal to the height74of the second patterned layer141(shown inFIG.13). In some embodiments, as shown inFIG.16, the second inclined surface145contacts the vertical portion13bof the patterned conformal layer131. In some embodiments, the top143of the second inclined member142is a point, which is a contact point between the second inclined surface145and the vertical portion13bof the patterned conformal layer131. In such embodiments, the first height761(shown inFIG.14) is substantially equal to or less than the height74of the second patterned layer141(shown inFIG.13). In some embodiments, as shown inFIG.16, the second inclined surface145contacts the vertical portion13bat a position below the top surface13B of the patterned conformal layer131, and the first height761is less than the height74of the second patterned layer141.

Referring toFIG.17,FIG.17is a schematic cross-sectional diagram at a stage of the method S1, the method S2and/or the method S3in accordance with some embodiments of the present disclosure. In the operation S16, in the operations S25and S26, and/or in the operation S38, a third etching53is performed to remove the vertical portions13bof the patterned conformal layer131. In some embodiments, the vertical portions13bof the patterned conformal layer131are disposed between the first patterned layer121and the second patterned layer141. In some embodiments, the vertical portions13bof the patterned conformal layer131line the sidewalls of different portions of the first patterned layer121and/or different portions of the second patterned layer141. In some embodiments, the third etching53includes ion beam etching, directional dry etching, reactive ion etching, solution wet etching, or a combination thereof. In some embodiments, the third etching53includes a high-selectivity etching. In some embodiments, the third etching53has a high selectivity to the patterned conformal layer131. In some embodiments, the high selectivity of the third etching53includes an oxide to nitride selectivity greater than 10.

As a result, a plurality of gaps35are formed between the first patterned layer121and the second patterned layer141. In some embodiments, the second patterned layer141is separated from the first patterned layer121by the plurality of gaps35and from the substrate11by the horizontal portions13aof the patterned conformal layer131after the planarization. In some embodiments, the gaps35are at positions from which the vertical portions13bof the patterned conformal layer131were previously removed. In some embodiments, the horizontal portions13aof the patterned conformal layer131disposed between the substrate11and the second patterned layer141remain in place and collectively become a segmental layer132. In some embodiments, the segmental layer132includes a plurality of portions between portions of the second patterned layer141and the substrate11. In some embodiments, different portions of the segmental layer132are separated from each other. In some embodiments, portions of the substrate11are exposed through the gaps35. In some embodiments, a width351of the gaps35is defined by the thickness136of the conformal layer13shown inFIG.9. In some embodiments, the width351of the gaps35is substantially equal to the thickness136of the conformal layer13. In some embodiments, the horizontal portions13aof the patterned conformal layer131disposed between the substrate11and the second patterned layer141remain in place.

The first inclined member122and the second inclined member142may be removed concurrently with the removal of the vertical portions13bof the patterned conformal layer131by the third etching53. For a purpose of illustration, the first patterned layer121after the third etching is labelled as126, and the second patterned layer141after the third etching53is labelled as146. In some embodiments, a top surface12C of the first patterned layer126is planarized by the third etching53. In some embodiments, a top surface14C of the second patterned layer146is planarized by the third etching53. In some embodiments, the top surfaces12C and14C of the first patterned layer126and the second patterned layer146are planarized concurrently. In some embodiments, the removal of the vertical portions13band the planarization of the top surfaces12C and14C are performed concurrently by a directional dry etching. In some embodiments, the top surfaces12C and14C of the first patterned layer126and the second patterned layer146are substantially aligned. In some embodiments, the top surfaces12C and14C of the first patterned layer126and the second patterned layer146are substantially coplanar. In some embodiments, a height77of the first patterned layer126is substantially equal to the height752shown inFIG.14. In some embodiments, a height78of the second patterned layer146is substantially equal to the height762shown inFIG.14.

Referring toFIG.18,FIG.18is a schematic cross-sectional diagram at a stage of the method S1, the method S2and/or the method S3in accordance with some embodiments of the present disclosure. After the operation S16, after the operation S26and/or after the operation S38, a patterning is performed on the substrate11using the first patterned layer126and the second patterned layer146as a mask. In some embodiments, the patterning includes an ion beam etching, a directional dry etching, a reactive ion etching, a solution wet etching, or a combination thereof. As described above, the substrate11depicted inFIG.18may represent only the topmost layer of the substrate11. In some embodiments, a portion of the topmost layer of the substrate11exposed through the gap35is removed. In some embodiments, a pattern of the first patterned layer126and the second patterned layer146is transferred to the topmost layer of the substrate11, thereby forming a patterned substrate111. In some embodiments, a material of the topmost layer of the substrate11is different from that of the first patterned layer126and/or that of the second patterned layer146. In some embodiments, the material of the topmost layer of the substrate11is different from that of the segmental layer132.

Referring toFIG.19,FIG.19is a schematic cross-sectional diagram at a stage of the method S1, the method S2and/or the method S3in accordance with some embodiments of the present disclosure. After the patterning of the substrate11, the first patterned layer126, the second patterned layer146and the segmental layer132are removed, and a semiconductor structure10is thereby formed. In some embodiments, one or more etchings are performed to remove the first patterned layer126, the second patterned layer146and the segmental layer132individually or concurrently. In some embodiments, the one or more etchings include an ion beam etching, a dry etching, a reactive ion etching, a solution wet etching, or a combination thereof. In some embodiments, the removal of the first patterned layer126, the second patterned layer146and the segmental layer132includes a lift-off operation. In some embodiments, a post-cleaning operation is performed on the semiconductor structure10shown inFIG.19after the removal of the first patterned layer126, the second patterned layer146and the segmental layer132. In some embodiments, a top surface111A of the patterned substrate111includes recessed portions corresponding to positions of the recesses182shown inFIG.8. In some embodiments, a thickness of portions of the patterned substrate111defined by the second patterned layer146is less than a thickness of portions of the patterned substrate111defined by the first patterned layer126shown inFIG.18.

Widths, lengths, and/or configurations of different portions of the patterned substrate111can be defined by the first patterned layer126and the second patterned layer146. For instance, widths of adjacent portions of the patterned substrate111are defined by adjacent portions of the first patterned layer126and the second patterned layer146. It should be noted that a width127of a portion of the first patterned layer126and a width147of a portion of the second patterned layer146can be controlled and adjusted according to different applications. In some embodiments, the width127is substantially less than the width147as shown inFIG.18. In some embodiments, widths of different portions (e.g.,112and113shown inFIG.19indicate widths of two adjacent portions of the patterned substrate111) are substantially different. In alternative embodiments, a width127of a portion of the first patterned layer126and a width147of a portion of the second patterned layer146are substantially equal.

Due to a property of a directional dry etching, corner portions of portions of the first patterned layer121and corner portions of portions of the second patterned layer141may be removed by the third etching53. In a conventional method without formation of inclined members122and142, a configuration of the patterned layer is changed after a removal of vertical portions of a conformal layer, and a result of the subsequent patterning is affected. The lost material and changed configuration can lead to irregular shapes of the patterned substrate, and therefore cause instabilities and possible defect to subsequent processing. The first inclined member122and the second inclined member142serve a purpose of preventing changing of the configuration of the patterned layers, and therefore a better patterning result can be provided.

FIGS.20to25are schematic diagrams illustrating various fabrication stages constructed according to the method S1, S2or S3for manufacturing a semiconductor structure20in accordance with alternative embodiments of the present disclosure. The stages shown inFIGS.20to25are also illustrated schematically in the process flow inFIG.1,2or3. In the subsequent discussion, the fabrication stages shown inFIGS.20to25are discussed in reference to the process steps inFIG.1,2or3.

For ease of illustration, reference numerals with similar or same functions and properties are repeated in different embodiments and figures. For a purpose of brevity, in the following specification, only differences from the embodiments illustrated above are emphasized, and descriptions of similar or same elements, functions, properties and/or processing are omitted.

Referring toFIG.20,FIG.20is a schematic cross-sectional diagram at a stage of the method S1, the method S2and/or the method S3in accordance with some embodiments of the present disclosure. In some embodiments, the formation of the recesses182shown inFIG.8is omitted, and operations similar to those illustrated inFIGS.9to10are applied to an interim structure similar to that shown inFIG.7. A conformal layer13and a second layer14are sequentially formed over a first patterned layer121to form an interim structure as shown inFIG.20. In some embodiments, the first patterned layer121includes sharp corners61′ instead of the rounded corners61as shown inFIG.9. In some embodiments, the conformal layer13includes sharp corners62′ instead of the rounded corners62as shown inFIG.9. In some embodiments, the conformal layer13includes horizontal portions13alining the top surface11A of the substrate11, horizontal portions13clining a top surface12A of the first patterned layer121, and vertical portions13bconnecting the horizontal portions13aand the horizontal portions13c. In some embodiments, the conformal layer13lines the openings31. In some embodiments, the conformal layer13lines sidewalls121A of portions of the first patterned layer121and a portion of the top surface11A of the substrate11in the openings31. In some embodiments, the conformal layer13is in contact with the top surface12A of the first patterned layer121, the sidewall121A of the first patterned layer121, and the top surface11aof the substrate11.

Referring toFIG.21,FIG.21is a schematic cross-sectional diagram at a stage of the method S1, the method S2and/or the method S3in accordance with some embodiments of the present disclosure. Operations similar to those illustrated inFIG.11are applied to the structure as shown inFIG.20, and a sacrificial layer15is formed over the second layer14. In some embodiments, the sacrificial layer15and the second layer14shown inFIG.21is similar to the sacrificial layer15and the second layer14shown inFIG.11. In some embodiments, the second layer14covers the sharp corners62′ of the conformal layer13. In some embodiments, the second layer14is in physical contact with the sharp corners62′ of the conformal layer13.

Referring toFIGS.22and23,FIGS.22and23are schematic cross-sectional diagrams at a stage of the method S1, the method S2and/or the method S3in accordance with different embodiments of the present disclosure. A first etching51is performed on the structure as shown inFIG.22. In some embodiments, the first etching51stops at an exposure of the top surface12A of the first patterned layer121. In some embodiments, portions of the second layer14and portions of the conformal layer13above the top surface12A of the first patterned layer121are removed. In some embodiments, the first etching51stops at a line171. In some embodiments, only the horizontal portions13cof the conformal layer13are removed. In some embodiments as shown inFIG.22, the line171is at the top surface12A of the first patterned layer121; therefore, a material loss of the first patterned layer121can be minimized. In some embodiments, the horizontal portions13cand upper portions of the vertical portions13bof the conformal layer13are removed. In some embodiments as shown inFIG.23, the line171is below the top surface12A of the first patterned layer121; therefore, exposure of an entirety of the top surface12A of the first patterned layer121is ensured.

Referring toFIG.24,FIG.24is a schematic cross-sectional diagram at a stage of the method S1, the method S2and/or the method S3in accordance with some embodiments of the present disclosure.FIG.24shows a resulting structure of the first etching51performed on the interim structure as shown inFIG.21. In some embodiments, a thickness72of the first patterned layer121is substantially equal to a thickness71of the first patterned layer121prior to the first etching51shown inFIG.21if the first etching51stops at the line171shown inFIG.22. In some embodiments, the thickness72of the first patterned layer121is substantially less than the thickness71of the first patterned layer121prior to the first etching51if the first etching51stops at the line171shown inFIG.23. In some embodiments, a thickness74of the second patterned layer141is substantially less than the thickness72of the first patterned layer121. In some embodiments, a height73of the patterned conformal layer131is substantially equal to the thickness72. In some embodiments, the thickness72is substantially equal to a total thickness of the second patterned layer141(having the thickness74) and the patterned conformal layer131(having a thickness136).

Referring toFIG.25,FIG.25is a schematic cross-sectional diagram at a stage of the method S1, the method S2and/or the method S3in accordance with some embodiments of the present disclosure. Operations similar to those illustrated inFIGS.14and17to19are sequentially performed on the intermediate structure ofFIG.24to form a semiconductor structure20. In some embodiments, a top surface111A of a patterned substrate111is substantially planar.

One aspect of the present disclosure provides a method of manufacturing a semiconductor structure. The method includes forming a first patterned layer over a substrate; forming a conformal layer over the first patterned layer; forming a second layer over the conformal layer and between portions of the first patterned layer; performing a first etching to remove portions of the second layer and the conformal layer disposed over the first patterned layer, thereby forming a second patterned layer and a patterned conformal layer; performing a second etching to form a first inclined member of the first patterned layer tapered away from the substrate and lining a vertical portion of the patterned conformal layer, and to form a second inclined member of the second patterned layer tapered away from the substrate and lining the vertical portion of the patterned conformal layer; and performing a third etching to remove the vertical portions of the patterned conformal layer.

Another aspect of the present disclosure provides a method of manufacturing a semiconductor structure. The method includes forming a first patterned layer over a substrate; forming a second patterned layer over the substrate and alternately arranged with the first patterned layer; forming a patterned conformal layer disposed between the first patterned layer and the second patterned layer, wherein top surfaces of the first patterned layer, the patterned conformal layer, and the second patterned layer are substantially coplanar; forming a first recess extending into the first patterned layer and surrounded by the patterned conformal layer; removing vertical portions of the patterned conformal layer; and planarizing top surfaces of the first patterned layer and the second patterned layer.

Another aspect of the present disclosure provides a method of manufacturing a semiconductor structure. The method includes providing a substrate; forming a first layer over the substrate; patterning the first layer to form a first patterned layer and to expose portions of the substrate; forming a conformal layer over the first patterned layer and the substrate; forming a second layer over the conformal layer, wherein the second layer at least fills between different portions of the first patterned layer; removing portions of the conformal layer and the second layer disposed over the first patterned layer to form a patterned conformal layer and a second patterned layer, wherein top surface of the first patterned layer, the second patterned layer and the patterned conformal layer are substantially coplanar; performing a first etching to form a first recess on the first patterned layer and a second recess on the second patterned layer, wherein each of the first recess and the second recess is surrounded by the patterned conformal layer; and performing a second etching to remove portions of the patterned conformal layer to separate the first patterned layer and the second patterned layer with a plurality of gaps.

In conclusion, the application discloses a manufacturing method of a semiconductor structure. An etching operation is performed on patterned layers prior to transferring a pattern of the patterned layers, and inclined members are formed at corner portions of the patterned layers. A presence of the inclined members can protect a desired configuration of the patterned layers and provide improvement of a patterning result.