Multilayer image sensor structure for reducing crosstalk

An image sensor pixel includes a substrate, an epitaxial layer, and a light collection region. The substrate is doped to have a first conductivity type. The epitaxial layer is disposed over the substrate and doped to have a second conductivity type opposite of the first conductivity type. The light collection region is disposed within the epitaxial layer for collecting photo-generated charge carriers. The light collection region is doped to have the first conductivity type as well.

TECHNICAL FIELD

This disclosure relates generally to image sensors, and in particular but not exclusively, relates to CMOS image sensors.

BACKGROUND INFORMATION

Image sensors have become ubiquitous. They are widely used in digital still cameras, cellular phones, security cameras, as well as, medical, automobile, and other applications. The technology used to manufacture image sensors, and in particular, complementary metal-oxide-semiconductor (“CMOS”) image sensors (“CIS”), has continued to advance at great pace. For example, the demands of higher resolution and lower power consumption have encouraged the further miniaturization and integration of these image sensors.

FIG. 1illustrates a conventional front side illuminated CIS100. The front side of CIS100is the side of substrate105upon which the pixel circuitry is disposed and over which metal stack110for redistributing signals is formed. The metal layers (e.g., metal layer M1and M2) are patterned in such a manner as to create an optical passage through which light incident on the front side CIS100can reach the photosensitive or photodiode (“PD”) region115. To implement a color CIS, the front side further includes a color filter layer120disposed under a microlens125. Microlens125aids in focusing the light onto PD region115.

CIS100includes pixel circuitry130disposed adjacent to PD region115within a P doped well. Pixel circuitry130provides a variety of functionality for regular operation of CIS100. For example, pixel circuitry130may include circuitry to commence acquisition of an image charge within PD region115, to reset the image charge accumulated within PD region115to ready CIS100for the next image, or to transfer out the image data acquired by CIS100.

FIG. 2illustrates two neighboring CIS pixels100formed within a P-epitaxial (“epi”) layer140disposed over a P+ substrate105. When a photo-generated charge carrier is formed shallow within a pixel (e.g., charge carrier150), it experiences a strong upward attractive force (shown by the arrows) towards PD region115, due to the depletion region or P-N junction between the PD and the surrounding epitaxial layer. When a photo-generated charge carrier is formed deeper within a pixel (e.g., charge carrier155), it initially experiences a weaker upward repulsive force due to the dopant gradient at the junction between the P− epi layer140and the P+ substrate105.

Crosstalk is a serious problem in image sensors. There are three components to crosstalk: a) electrical crosstalk, b) optical crosstalk, and c) spectral crosstalk. Spectral crosstalk is caused by the diffraction and/or scattering of light off of metal lines and at interfaces between the dielectric layers within metal stack110. Spectral crosstalk results from the finite (nonzero) transmittance of color filter120to wavelengths outside its target pass band, such as the finite transmittance of green and blue wavelengths through a red filter.

One form of electrical crosstalk is lateral drift of photo-generated charge carriers created deep in the semiconductor epitaxial layers (e.g., charge carrier155). As these photo-generated charge carriers rise, they can drift laterally and end up collected in the PD region of a neighboring pixel. Blooming is another form of electrical crosstalk characterized by the lateral diffusion of charge carriers when a PD region becomes full or saturated with charge carriers. Blooming is most commonly experienced in high luminous environments. Photo carriers that are generated near a saturated PD region115will not be collected and therefore remain free to diffuse laterally into a neighboring pixel. Blooming results in the blurring of edges in still images and streaking in moving images. Both forms of electrical crosstalk are due to charge carriers generated in one pixel being collected by a neighboring pixel.

DETAILED DESCRIPTION

FIG. 3is a cross sectional view of two neighboring image sensors300A and300B (collectively image sensors300) having a multilayer structure that reduces electrical crosstalk, in accordance with an embodiment of the invention. The illustrated embodiment of image sensors300include a substrate305, a gradient junction310, an epitaxial (“epi”) layer315, collection regions320, and a biasing circuit325. The collection regions320of each image sensor300are isolated from each other with shallow trench isolations (“STI”) and dopant wells330. In the illustrated embodiment, a pinning layer335(e.g., P type pinning) overlays collection regions320to passivate their surfaces.

Although not illustrated, it should be appreciated that image sensors300may include a number of material layers disposed on the front side, such as those illustrated inFIG. 1(e.g., pixel circuitry130, a dielectric layer, metal stack110, color filter120, microlens125, etc.), as well as other conventional layers used for fabricating CMOS (complementary metal-oxide-semiconductor) image sensors (“CIS”) (e.g., antireflective films, etc.). Furthermore, the illustrated cross section of image sensors300does not illustrate the pixel circuitry of each sensor. However, it should be appreciated that each image sensor300includes pixel circuitry (for example seeFIG. 7) coupled to its collection region320for performing a variety of functions, such as commencing image acquisition, resetting accumulated image charge, transferring out acquired image data, or otherwise.

In the illustrated embodiment, substrate305is a silicon substrate highly doped with N type dopants (e.g., Arsenic, As; Phosphorous, P) while epi layer315is a silicon layer lightly doped with P type dopants (e.g., Boron, B). Collection regions320represent photosensitive regions (e.g., photodiode), which are doped with the same conductivity type as substrate305. The illustrated dopant wells330are P wells for isolating adjacent collection regions320and prevent direct interface between the STI and collection regions320. However, it should be appreciated that the conductivity types of all the elements can be swapped such that substrate305is P+ doped, epi layer315is N-doped, collection regions320are P+ doped, and dopant wells330are N doped.

One technique for reducing electrical crosstalk is to use a P− epi layer over an N type substrate. N type substrates may include silicon wafers doped with high concentrations of Arsenic or Phosphorous (also referred to as N+ substrates). Since standard CIS typically use P type epitaxial layers (e.g., P− epi layer315), when using N+ substrates, the P type epi layer315may be fabricated by growing the P type epi layer on the N+ substrate. The electric field340formed at the interface between P− epi layer315and N+ substrate305acts as a barrier to photo generated charge carriers (e.g., photo electrons) that are formed in N+ substrate305. This barrier lowers the probability that a charge carrier formed deep in the CIS structure can diffuse to an adjacent collection region320. Similarly, this structure reduces blooming. Electrons that are uncollected by a full collection region320are drawn into N+ substrate305by electric field340, rather than diffusing down around dopant wells330and into a neighboring collection region320.

The junction between the P− epi layer315and N+ substrate305is not infinitely abrupt. The N+ substrate is typically heavily doped with As or P. During the epitaxial growth, which is typically done at high temperatures (>800 C), N type dopants diffuse into P− epi layer315. In addition, thermal processing associated with CIS fabrication increase the N type dopant diffusion into epi layer315. As such, the junction between substrate305and epi layer315is graded (illustrated as gradient junction310). Electric field340, and therefore the field barrier generated to reduce crosstalk and blooming, is dependent on the diffusion gradient profile. The final thickness of epi layer315after diffusion is thus dependent on the diffusion gradient profile. Since epi layer315houses collection regions320, the light collection efficiency and the degree of lateral charge carrier diffusion and blooming will vary with the CIS process thermal budget and the epitaxial layer growth process.

During operation, photo-generated charge carriers that are created shallow within epi layer315are collected by the electric field generated by the depletion region at the P-N junction between collection region320and epi layer315. In contrast, photo-generated charge carriers that are created deep within epi layer315have a statistically increased chance of being drawn into substrate305by electric field340where they recombine without contributing to crosstalk. Similarly, photo-generated charge carriers that are created even deeper within substrate305are inhibited from diffusing up into a neighboring collection region320by the potential barrier created by field340. Finally, in one embodiment, substrate305can be positively biased relative to epi layer315and collection regions320by biasing circuit325. The presence of the biasing operates to further impede photo-electrons from crossing the potential barrier of field340. It should be appreciated that in an embodiment where substrate305is a P+ substrate and epi layer315is an N− epi layer, the biasing circuit325would negatively bias substrate305relative to epi layer315.

FIG. 4is a cross sectional view of two neighboring image sensors400A and400B (collectively image sensors400) having a multilayer structure that reduces electrical crosstalk, in accordance with an embodiment of the invention. Image sensors400are similar to image sensors300with the following exceptions. Image sensors400include an additional buffer layer405having the same conductivity type doping as substrate305, but in a lesser concentration (e.g., N− buffer layer405and N+ substrate305). Since the N type dopant concentration interface is not infinitely abrupt, gradient junction405represents a graded dopant profile from the N+ substrate305to the N− buffer layer410. In one embodiment, image sensors400may also include biasing circuit325to bias substrate305relative to collection regions320and epi layer315(e.g., positive for N type substrate and collection regions or negatively for a P type substrate and collection regions).

The depletion region formed at the interface of the N− buffer layer410and the P− epi layer315generates an electric field415, which draws deep photo-electrons into buffer layer410where they can recombine. A dopant gradient field420is generated at the gradient junction405, which also pulls photo-electrons generated in buffer layer410into substrate305or impedes the diffusion of photo-electrons generated in substrate305from migrating into buffer layer410and from there into epi layer315.

Similar to epi layer315, buffer layer410is an epitaxial layer grown over substrate305and serves a dual purpose. First, buffer layer410traps deep or excess photo-electrons resulting in a reduction in crosstalk and blooming. Second, buffer layer410serves as a N type diffusion buffer, preventing the high concentration N type dopants of substrate305from diffusing into the P type epi layer315during epitaxial growth cycles and the other high temperature CIS processes. The dopant concentration in buffer layer410is significantly lower than substrate305, resulting in significantly less N type dopant diffusion into the P type epi layer315. As such, buffer layer410can increase the thermal budget of image sensors400during fabrication. Buffer layer410adds process margin to device fabricated on N+ substrates, which eases process development and process transfers. In addition, this multilayer structure is less dependent on a particular wafer vendor's growth conditions, allowing wider sources of starting material.

The lower thickness limit to buffer layer410is determined by the amount of dopant diffusion expected from substrate305. However, the upper limit to the thickness of buffer layer410is not limited by the fabrication process. Photo-electrons present in buffer layer410will more easily diffuse to substrate305than cross the P-N junction barrier of field415. Therefore a wide margin can be used in choosing the thickness of buffer layer410. For example, buffer layer410may range between 0.3 μm and 10 μm.

FIG. 5is a cross sectional view of two neighboring image sensors500A and500B (collectively image sensors500) having a multilayer structure that reduces electrical crosstalk, in accordance with an embodiment of the invention. Image sensors500are similar to image sensors400with the following exceptions. Image sensors500include a barrier layer505disposed between epi layer315and buffer layer410. Barrier layer505has the same conductivity type as epi layer315(e.g., P type), but with a greater dopant concentration than epi layer315. In an alternative embodiment, image sensors500include barrier layer505, but lack buffer layer410.

Barrier layer505serves two purposes. On the device side, barrier layer505creates an electric field510that drives photo-electrons present in epi layer315up towards collection regions320. On the substrate side, barrier layer505increases the potential barrier that photo-electrons in buffer layer410must overcome to diffuse into epi layer315. Accordingly, barrier layer505impedes deep photo-electrons from migrating into a neighboring collection region320while promoting the collection of shallow photo-electrons by pushing them up. The size of the potential barrier is dependent upon the dopant concentrations of buffer layer410and barrier layer505. Barrier layer505may be doped via ion implantation or controlling epitaxial growth conditions. Of course, in one embodiment, image sensors500may also include biasing circuit325to bias substrate305relative to collection regions320and epi layer315(e.g., positive for N type substrate and N type collection regions or negatively for a P type substrate and P type collection regions).

FIG. 6is a block diagram illustrating an imaging system600, in accordance with an embodiment of the invention. The illustrated embodiment of imaging system600includes an image sensor array605having improved electrical crosstalk characteristics, readout circuitry610, function logic615, and control circuitry620.

Image sensor array605is a two-dimensional (“2D”) array of image sensors or pixels (e.g., pixels P1, P2. . . , Pn). In one embodiment, each pixel represents any of image sensors300,400, or500. In one embodiment, each pixel is a complementary metal-oxide-semiconductor (“CMOS”) image sensor. In one embodiment, image sensor array605is a color filter array including a color pattern (e.g., Bayer pattern or mosaic) of red, green, and blue filters. As illustrated, each pixel is arranged into a row (e.g., rows R1to Ry) and a column (e.g., column C1to Cx) to acquire image data of a person, place, or object, which can then be used to render a 2D image of the person, place, or object.

After each pixel has acquired its image data or image charge, the image data is readout by readout circuitry610and transferred to function logic615. Readout circuitry610may include amplification circuitry, analog-to-digital (“ADC”) conversion circuitry, or otherwise. Function logic615may simply store the image data or even manipulate the image data by applying post image effects (e.g., crop, rotate, remove red eye, adjust brightness, adjust contrast, or otherwise). In one embodiment, readout circuitry610may readout a row of image data at a time along readout column lines (illustrated) or may readout the image data using a variety of other techniques (not illustrated), such as a column/row readout, a serial readout, or a full parallel readout of all pixels simultaneously.

Control circuitry620is coupled to image sensor array605to control operational characteristic of image sensor array605. For example, control circuitry620may generate a shutter signal for controlling image acquisition. In one embodiment, the shutter signal is a global shutter signal for simultaneously enabling all pixels within image sensor array605to simultaneously capture their respective image data during a single acquisition window. In an alternative embodiment, the shutter signal is a rolling shutter signal whereby each row, column, or group of pixels is sequentially enabled during consecutive acquisition windows.

FIG. 7is a circuit diagram illustrating pixel circuitry700of two four-transistor (“4T”) pixels within an image sensor array, in accordance with an embodiment of the invention. Pixel circuitry700is one possible pixel circuitry architecture for implementing each pixel within image sensor array605ofFIG. 6. However, it should be appreciated that embodiments of the present invention are not limited to 4T pixel architectures; rather, one of ordinary skill in the art having the benefit of the instant disclosure will understand that the present teachings are also applicable to 3T designs, 5T designs, and various other pixel architectures.

InFIG. 7, pixels Pa and Pb are arranged in two rows and one column. The illustrated embodiment of each pixel circuitry700includes a photodiode PD, a transfer transistor T1, a reset transistor T2, a source-follower (“SF”) transistor T3, and a select transistor T4. During operation, transfer transistor T1receives a transfer signal TX, which transfers the charge accumulated in photodiode PD to a floating diffusion node FD. In one embodiment, floating diffusion node FD may be coupled to a storage capacitor for temporarily storing image charges.

Reset transistor T2is coupled between a power rail VDD and the floating diffusion node FD to reset the pixel (e.g., discharge or charge the FD and the PD to a preset voltage) under control of a reset signal RST. The floating diffusion node FD is coupled to control the gate of SF transistor T3. SF transistor T3is coupled between the power rail VDD and select transistor T4. SF transistor T3operates as a source-follower providing a high impedance connection to the floating diffusion FD. Finally, select transistor T4selectively couples the output of pixel circuitry700to the readout column line under control of a select signal SEL.

In one embodiment, the TX signal, the RST signal, and the SEL signal are generated by control circuitry620. In an embodiment where image sensor array605operates with a global shutter, the global shutter signal is coupled to the gate of each transfer transistor T1in the entire image sensor array605to simultaneously commence charge transfer from each pixel's photodiode PD. Alternatively, rolling shutter signals may be applied to groups of transfer transistors T1.