Adaptive gain control for voltage regulators

A voltage regulator which provides an output current at an output voltage at an output node, based on an input voltage at an input node is described. The voltage regulator has an output amplification stage comprising a pass transistor for deriving the output current at the output node from the input voltage at the input node; and comprising a driver stage to set a gate voltage at a gate of the pass transistor based on a drive voltage. A gain of the output amplification stage is adjustable. Furthermore, the voltage regulator comprises a differential amplification unit to determine the drive voltage in dependence of the output voltage and in dependence of a reference voltage. In addition, the voltage regulator comprises a gain control circuit to adjust the gain of the output amplification stage in dependence of the output current.

TECHNICAL FIELD

The present document relates to a voltage regulator. In particular, the present document relates to a voltage regulator exhibiting reduced internal losses and/or reduced dropout voltages.

BACKGROUND

Voltage regulators are frequently used for providing a load current at a stable load voltage to different types of loads (e.g. to the processors of an electronic device). A voltage regulator derives the load current from an input node of the regulator, while regulating the output voltage at the output node of the regulator in accordance to a reference voltage.

SUMMARY

The present document addresses the technical problem of providing a voltage regulator which exhibits reduced internal losses and/or which enables reduced drop-out voltages. According to an aspect, a regulator (notably a voltage regulator such as a linear dropout regulator) is described. The regulator is configured to provide at an output node of the regulator an output current (referred to herein as IOUT) at an output voltage (referred to herein as VOUT). The output node of the regulator may be coupled to a load (e.g. to a processor) which is to be operated using the load current. The output current is derived from an input voltage (referred to herein as VIN) at an input node of the regulator.

The regulator (notably the voltage regulator) comprises an output amplification stage. The output amplification stage comprises a pass transistor (e.g. an n-type metal oxide semiconductor transistor) for providing the output current at the output node from an input voltage at the input node of the regulator. The input node may correspond to a drain of the pass transistor and the output node may correspond to a source of the pass transistor. Furthermore, the output amplification stage comprises a driver stage which is configured to set a gate voltage at a gate of the pass transistor based on a drive voltage (referred to herein as VDRIVE_S3). The driver stage may comprise a drive transistor (e.g. an NMOS transistor) having a gate that is coupled to the gate of the pass transistor, having a source that is coupled to a source of the pass transistor, and having a drain that is coupled to the gate of the drive transistor. Hence, the drive transistor and the pass transistor may form a current mirror.

Furthermore, the voltage regulator comprises a differential amplification unit which is configured to determine the drive voltage in dependence of the output voltage and in dependence of a reference voltage. In particular, the differential amplification unit may be configured to determine the drive voltage in dependence of the difference between a feedback voltage (which is proportional to the output voltage) and the reference voltage.

A gain of the output amplification stage (referred to herein as GOUT) is adjustable. The adjustable gain may e.g. be implemented using an adjustable mirror ratio of the current mirror which is formed by the drive transistor and the pass transistor. The regulator further comprises a gain control circuit which is configured to adjust the gain of the output amplification stage in dependence of the output current. For this purpose, the gain control circuit may be configured to sense the output current (e.g. using current sensing means such as a scaled copy of the pass transistor). The gain may then be adjusted using the sensed output current.

By adjusting the gain of the output amplification stage based on the output current, the internal losses of the voltage regulator may be reduced, while at the same time maintaining a fast transient response and stability of the voltage regulator. In particular, the gain control circuit may be configured to adjust the gain such that the gain increases with increasing output current and decreases with decreasing output current, thereby achieving a good compromise between stability, speed and power consumption of the voltage regulator.

Alternatively or in addition, the gain control circuit may be configured to adjust the gain in dependence of the input voltage and/or in dependence of the output voltage, notably in dependence of a difference between the input voltage and the output voltage. In particular, the gain control circuit may be configured to increase the gain, if an absolute value of the difference between the output voltage and the input voltage decreases or if a value of the input voltage decreases.

Alternatively or in addition, the gain control circuit may be configured to decrease the gain, if an absolute value of the difference between the output voltage and the input voltage increases or if a value of the input voltage increases. By doing this, the voltage regulator may be enabled for regulation with relatively small differences between the input voltage and the output voltage (i.e. for small dropout voltages), as may occur e.g. in case of a decrease of the input voltage.

The gain control circuit may be configured to adjust the gain of the output amplification stage by a gain delta if the output current changes by a current delta. A ratio of the gain delta and the current delta may be equal to or smaller than a pre-determined transition threshold. The pre-determined transition threshold may be set to ensure stability of the voltage regulator. In other words, the gain control circuit may be configured to perform a gradual increase/decrease of the gain across a certain interval of values of the output current. By doing this, stable regulation of the voltage regulator may be ensured, even if the gain of the output amplification stage is adjusted.

By way of example, the output amplification stage may exhibit a minimum gain value and a maximum gain value for the gain of the output amplification stage. The gain control circuit may be configured to adjust the gain from the minimum gain value to the maximum gain value (or vice versa) across a transition range of values of the output current. The width of the transition range may be determined based on stability measurements of the voltage regulator. In particular, the transition range may be sufficiently wide to ensure stability of the voltage regulator, even for changing gains of the output amplification stage. This may be ensured by selecting the transition range based on stability measurements.

A minimum current value and/or a maximum current value of the transition range may depend on the input voltage and/or on an absolute value of a difference between the output voltage and the input voltage. By doing this, the voltage regulator may be enabled for regulation with relatively small differences between the input voltage and the output voltage, as may occur e.g. in case of a decrease of the input voltage.

As indicated above, the driver stage typically comprises a drive transistor which forms a current mirror with the pass transistor. The gain of the output amplification stage may be dependent on, notably equal to, a mirror ratio of the current mirror. As such, the gain of the output amplification stage may be adjusted by adjusting the mirror ratio of the current mirror.

By way of example, the current mirror may comprise an adjustable resistance between the drain of the drive transistor and the gate of the pass transistor. The gain control unit may be configured to control the adjustable resistance to control the gain of the output amplification stage. The adjustable resistance may e.g. comprise an auxiliary transistor, and the gain control unit may be configured to control a voltage which is applied to a gate of the auxiliary transistor (thereby adjusting the on-resistance of the auxiliary transistor). An adjustable resistance within the current mirror provides efficient means for adjusting the gain of the output amplification stage.

The gain control unit may be configured to adjust an effective size of the drive transistor to adjust the mirror ratio of the current mirror. Alternatively or in addition, the gain control unit may be configured to adjust a gain of the drive transistor to adjust the mirror ratio of the current mirror. Alternatively or in addition, the drive transistor may comprise a plurality of constituting transistors and the gain control unit may be configured to enable and/or disable one or more constituting transistors to adjust the mirror ratio of the current mirror. As such, various different means may be provided to adjust the gain of the output amplification stage.

The driver stage may comprise an input transistor which is controlled by the drive voltage to set an internal current of the driver stage. The input transistor and the drive transistor may be arranged in series with respect to one another, such that the internal current corresponds to the current through the input transistor and to the current through the drive transistor. The gain of the output amplification stage may be proportional to a ratio of the output current and the internal current.

According to a further aspect, a method for providing an output current at an output voltage at an output node of a regulator, based on an input voltage at an input node of the regulator is described. The method comprises deriving the output current at the output node from the input voltage at the input node using a pass transistor. Furthermore, the method comprises setting a gate voltage at a gate of the pass transistor based on a drive voltage. In addition, the method comprises determining the drive voltage in dependence of the output voltage and in dependence of a reference voltage.

The method further comprises adjusting a gain between the drive voltage and the gate voltage in dependence of the output current.

In the present document, the term “couple” or “coupled” refers to elements being in electrical communication with each other, whether directly connected e.g., via wires, or in some other manner.

DESCRIPTION

As outlined above, the present document is directed at providing a voltage regulator with reduced internal losses. An example of a voltage regulator is an LDO regulator. A typical LDO regulator100is illustrated inFIG. 1a. The LDO regulator100comprises an output amplification stage or output stage103, comprising e.g. a field-effect transistor (FET), at the output and a differential amplification stage101(also referred to as error amplifier) at the input. A first input (fb)107of the differential amplification stage101receives a fraction of the output voltage VOUTdetermined by the voltage divider104comprising resistors R0and R1. The second input (ref) to the differential amplification stage101is a stable voltage reference Vref108(also referred to as the bandgap reference). If the output voltage VOUTchanges relative to the reference voltage Vref, the drive voltage to the output amplification stage, e.g. to the power FET, changes by a feedback mechanism called main feedback loop to maintain a constant output voltage VOUT.

The LDO regulator100ofFIG. 1afurther comprises an additional intermediate amplification stage102configured to amplify the output voltage of the differential amplification stage101. An intermediate amplification stage102may be used to provide an additional gain within the amplification path. Furthermore, the intermediate amplification stage102may provide a phase inversion.

In addition, the LDO regulator100may comprise an output capacitance Cout(also referred to as output capacitor or stabilization capacitor or bypass capacitor)105parallel to the load106. The output capacitor105is used to stabilize the output voltage VOUTsubject to a change of the load106, in particular subject to a change of the requested load current or output current Iload/IOUT.

FIG. 1billustrates the block diagram of a LDO regulator100, wherein the output amplification stage103is depicted in more detail. In particular, the pass transistor or pass device201and the driver stage110of the output amplification stage103are shown. Typical parameters of an LDO regulator100are a supply voltage of 3V, an output voltage of 2V, and an output current or load current ranging from 1 mA to 100 or 200 mA. Other configurations are possible.

FIG. 1cshows further details of the driver stage110. The driver stage110comprises a drive transistor111(e.g. a p-type metal oxide semiconductor, PMOS, transistor) which is operated as a diode (i.e. the drain of the drive transistor111is coupled to the gate of the drive transistor111). The gate of the drive transistor111is coupled to the gate of the pass transistor201. Furthermore, the source of the drive transistor111is coupled to the source of the pass transistor201, which corresponds to the input node150of the regulator100. The drain of the pass transistor201corresponds to the output node of the regulator100.

The driver stage110further comprises an input transistor113(e.g. an n-type MOS or NMOS transistor) which is arranged in series with the drive transistor111, such that the current I_S3through the drive transistor111corresponds to the current through the input transistor113. This current is referred to herein as the internal current. The serial arrangement of the drive transistor111and the input transistor113may be arranged between the input node150and ground GND. The gate of the input transistor113is controlled by the output of the differential amplification unit160(which comprises e.g. the differential amplification stage101and the intermediate amplification stage102). The voltage at the output of the differential amplification unit160is referred to herein as the drive voltage VDRIVE_S3.

FIG. 1calso illustrates different terminals of the regulator100, notably an input terminal or input node (denominated as 1 inFIG. 1c) which is coupled to an unregulated input voltage VIN, an output terminal or output node (denominated as 2 inFIG. 1c) which provides the regulated output voltage VOUTand a ground terminal (denominated as 3 inFIG. 1c) which is coupled to ground GND.

The drive transistor111and the pass transistor201form a current mirror having a certain gain which corresponds to the ratio of the gain (GAIN_S1) of the drive transistor111and the gain (GAIN_S2) of the pass transistor201. This ratio of the gain of the drive transistor111and of the gain of the pass transistor201determines the ratio of the output current (I_OUT or IOUT) at the output terminal of the regulator100and the internal current (I_S3or IS3) through the drive transistor111. The gain GAIN_S2:GAIN_S1may be noted as GOUT(referred to as the gain of the output amplification stage), and the output current is given as GOUTtimes the internal current, i.e. IOUT=GOUT*IS3.

The drive transistor111and/or the pass transistor201may each be made up of multiple switch devices which are connected in a parallel configuration. For simplicity, the entire drive transistor structure (comprising a plurality of parallel contributing transistors) is referred to herein as a drive transistor S1.111. Similarly, the entire external pass transistor structure (comprising a plurality of parallel contributing transistors) is referred to herein as a pass transistor S2201. The gain ratio GOUT=GAIN_S2:GAIN_S1is typically fixed, such that the ratio of the output current (I_OUT) and of the internal current (I_S3) is also fixed.

The operation of a regulator100with a fixed gain or gain ratio GOUTis illustrated in the waveforms shown inFIGS. 2 and 3.FIGS. 2aand 3ashow the ratio between the gain of the pass transistor S2201and the gain of the drive transistor S1111, which remains constant across the entire range of the output load, i.e. across the entire range of the output current I_OUT or IOUT.FIGS. 2band 3bshow the linear relationship between the output current (I_OUT) and the internal current (I_S3). As a result of this, the internal loss of the regulator100increases linearly with the output current I_OUT, wherein the internal loss (measured in Watt) is given by:
Internal Loss=(I_S3)×(RDS(ON)_S1+RDS(ON_S3),
with RDS(ON)_S1being the on-resistance of the drive transistor111and with RDS(ON)_S3being the on-resistance of the input transistor113.

FIG. 2dillustrates the regulated output voltage V_OUT or VOUTas a function of the output current I_OUT.FIG. 2cillustrates that the differential amplification unit U1160increases the drive voltage VDRIVE_S3at the gate of the input transistor S3113as a function of output current IOUTin a linear manner, in order to linearly increasing the internal current I_S3through the input transistor113. In other words, increasing output currents IOUTlead to increasing drive voltages VDRIVE_S3.

As mentioned above, the input voltage V_IN or VINis typically unregulated. In the case of a portable electronic device, the input voltage V_IN is typically provided by a rechargeable battery. As the battery discharges, the level of the input voltage V_IN reduces.FIG. 3illustrates the operation of a linear regulator100when the level of the input voltage V_IN reduces to a level which is insufficient for supporting the requirements of the output load106. The arrow inFIG. 3cillustrates the decrease of the input voltage V_IN, which may be due e.g. to discharging of the battery of an electronic device which comprises the regulator100.

As described above, the gain ratio between the pass transistor S2201and the drive transistor S1111remains constant over the entire range of the output current I_OUT (FIG. 3a). Furthermore, the internal current I_S3through the input transistor113and the gate voltage VDRIVE_S3at the input transistor113are linearly related to the output current I_OUT (seeFIGS. 3band 3c). However, if the input voltage V_IN is not sufficiently high to provide the required gate voltage VDRIVE_S3in order to maintain the linear relationship between the gate voltage VDRIVE_S3and the output current I_OUT (as illustrated inFIG. 3c), the output voltage V_OUT cannot be regulated anymore in accordance to the reference voltage108(as illustrated inFIG. 3d). As such, a decreasing input voltage V_IN may lead to a situation, where the regulator100cannot regulate the output voltage V_OUT anymore.

FIG. 4illustrates a block diagram of a linear regulator100which comprises an output amplification stage111,113,201with an adaptable or adjustable gain. In particular, the gain ratio between the pass transistor S2201and the drive transistor S1111may be adapted. In other words, the gain of the current mirror402, which is formed by the drive transistor S1111and the pass transistor S2201may be adapted. The adaption of the gain may be controlled using a gain control unit401.

The gain ratio between the pass transistor S2201and the drive transistor S1111may be adapted, in order to improve the operational performance of the regulator100. In particular, adapting the gain ratio between the pass transistor S2201and the drive transistor S1111may be used to reduce the internal power loss of the regulator100. Furthermore, adapting the gain ratio between the pass transistor S2201and the drive transistor S1111may be used for maintaining output voltage regulation, even at reduced levels of the input voltage V_IN. The gain control unit401may be configured to adapt the gain ratio while balancing dynamic load and loop stability performance of the regulator100. The gain GOUTmay be adapted based on the level of the input voltage V_IN and/or based on the level of the output current I_OUT.

In the illustrated example ofFIG. 4, the regulator100comprises a differential amplification stage A1101, an intermediate amplification stage A2for providing the gate voltage VDRIVE_S3for the input transistor113of the output amplification stage111,201,113, a Miller capacitor C2161and a current source I_OUT.

Example waveforms during the operation of the regulator100ofFIG. 4are shown inFIG. 5. The regulator100may comprise a high gain setting501with a relatively high gain ratio GAIN_S2:GAIN_S1and a low gain setting502with a relatively low gain ratio GOUT=GAIN_S2:GAIN_S1. Within a transition phase503, the gain ratio may be adjusted smoothly between the low gain setting502and the high gain setting501, as illustrated inFIG. 5a. In particular, the transition may be performed in dependence on the output current I_OUT. As the output current I_OUT increases, the gain ratio may be increased from the low gain setting502to the high gain setting501(and vice versa). It should be noted that other modes for adjusting the gain ratio GAIN_S2:GAIN_S1may be used.

The gain ratio GAIN_S2:GAIN_S1may be optimized for specific operating conditions. For example, at light load conditions, it is typically more advantageous to maintain a relatively low gain ratio GAIN_S2:GAIN_S1. A relatively low gain ratio allows for relatively fast response times to optimize the load transient response of the regulator100, while maintaining a high degree of loop stability of the regulation loop. Conversely, for relatively high load currents I_OUT, it is typically advantageous to reduce the internal losses of the regulator100by reducing the internal current I_S3through the driver transistor111. This may be achieved by increasing the gain GOUT.

The above mentioned adaption of the gain GOUTis illustrated inFIG. 5b. The reduction of the internal losses of the regulator100due to the increase of the gain ratio GAIN_S2:GAIN_S1is given by:
Internal Loss reduction=ΔI_S3×(V_S1+V_S3),
wherein V_S1+V_S3(the drain-source voltages across the drive transistor111and the input transistor113) corresponds to the input voltage V_IN and wherein ΔI_S3is the reduction of the internal current I_S3due to the increase of the gain ratio GAIN_S2:GAIN_S1.

A further benefit of operating the regulator100with a relatively high gain ratio GAIN_S2:GAIN_S1is obtained in situations, where the regulator100is operated with an input voltage V_IN which is at a similar level as the regulated output voltage V_OUT. As illustrated inFIG. 3c, for relatively low input voltages V_IN, the gate voltage VDRIVE_S3of the input transistor S3113reaches a maximum value, which does not allow for the output voltage regulation to be maintained. On the other hand, the gate voltage VDRIVE_S3of the input transistor S3113can be reduced when increasing the gain ratio GAIN_S2:GAIN_S1, thereby creating an additional gap between the gate voltage VDRIVE_S3of the input transistor S3113and the input voltage V_IN (as illustrated inFIG. 5c). This gap can be used for maintaining the regulation of the output voltage V_OUT, even for relatively low input voltages V_IN (as illustrated inFIG. 5d).

FIG. 5ashows a gain transition period or interval503, within which the gain ratio GAIN_S2:GAIN_S1is adjusted. It is typically advantageous for a stable operation of the regulator100to perform a relatively gradual transition between the low gain setting502and the high gain setting501of the output amplification stage103(or vice versa). The gain ratio GAIN_S2:GAIN_S1of the pass transistor201and the driver transistor111may be adjusted gradually in various different ways. An example includes linearly adjusting the gain of one or more constituting switching elements comprised within the driver transistor S1111and/or enabling/disabling individual switching elements of the driver transistor S1111.

FIG. 6shows an example driver transistor arrangement111,602with a linearly adjustable gain. The gain may be adjusted by closing/opening the auxiliary transistor602(e.g. a PMOS transistor) using different gate voltages601.FIG. 6also illustrates the relationship between the internal current I_S3612and the gate voltage611of the pass transistor201. By changing the gate voltage601at the auxiliary transistor602, the relationship between the gate voltage611and the internal current612may be adjusted between the first relationship613and the second relationship614, thereby changing the gain ratio GAIN_S2:GAIN_S1in a smooth manner.

As mentioned above, it may be beneficial to operate the output amplification stage103with a relatively high gain ratio, when the input voltage V_IN is relatively close to the output voltage V_OUT. The difference between the input voltage V_IN and the output voltage V_OUT may be referred to as “headroom” voltage or dropout voltage. As such, by increasing the gain of the output stage103, the dropout voltage of the regulator100may be reduced. InFIG. 7a, the range503of the output current I_OUT, at which the gain transition between the low gain setting502and the high gain setting501occurs, may be adapted in response to the amount of headroom voltage that is available. This is illustrated by the arrows inFIG. 7a. As illustrated inFIG. 7a, the transition interval503may be moved to different ranges of the output current I_OUT, i.e. towards lower or higher ranges. As illustrated inFIG. 7b, the transition from a low to a high gain ratio may occur at a relatively low level of the output current, when the headroom voltage is low. Alternatively, as illustrated inFIG. 7c, the transition from a low to high gain ratio may occur at a relatively high level of the output current, when the headroom voltage is large. The transition interval503of the gain ratio may vary back and forth as the headroom voltage increases or decreases.

FIG. 8illustrates a block diagram of a regulator100comprising a gain control unit401which is configured to monitor the internal current I_S3612and/or the output current I_OUT. Furthermore, the gain control unit401may be configured to monitor the input voltage V_IN and/or the output voltage V_OUT. These parameters may be sensed indirectly. For example, the output current I_OUT may be determined by sensing the drive voltage VDRIVE_S3of the input transistor S3113and by determining the gain ratio GOUT. The gain ratio may then be adapted in dependence of the headroom voltage and/or in dependence of the output current I_OUT.

The gain control unit401may be configured to vary the gain ratio GOUTto accommodate the feedback function of the regulator100, i.e. notably to maintain the output voltage V_OUT in accordance to a predetermined reference voltage108. The gain ratio GOUTmay be set automatically as an outcome of the regulation. In the illustrated example, the gain ratio GOUTmay be set automatically in dependence of the internal current I_S3612(which may also be referred to as the drive current). The gain control unit401may make use of a predetermined characteristic (similar to the one shown inFIG. 5a) which maps the internal current I_S3612and/or the output current I_OUT to the gain ratio GOUT. The gain control unit401may then be configured to vary the gain ratio GOUTin dependence of the predetermined characteristic and the sensed internal current I_S3612and/or output current I_OUT.

FIG. 9shows a flow chart of an example method900for providing an output current IOUTat an output voltage VOUTat an output node of a regulator100, based on an input voltage VINat an input node150of the regulator100. The method900comprises deriving901the output current IOUTat the output node from the input voltage VINat the input node150using a pass transistor201. Furthermore, the method900comprises setting902a gate voltage611at a gate of the pass transistor201based on a drive voltage VDRIVE_S3. In addition, the method900comprises determining903the drive voltage VDRIVE_S3in dependence of the output voltage VOUTand in dependence of a reference voltage108, notably in dependence of a differential voltage derived based on the output voltage VOUTand the reference voltage108. Furthermore, the method900comprises adjusting904a gain GOUTbetween the drive voltage VDRIVE_S3and the gate voltage611in dependence of the output current IOUT. The gain GOUTmay be proportional to a ratio of the gate voltage611at the pass transistor201over the drive voltage VDRIVE_S3(at the input of the output amplification stage103and/or at the output of the differential amplification unit160). The gain may be increased for an increasing output current IOUT(or vice versa). Alternatively or in addition, the gain may be increased for a decreasing input voltage VIN(or vice versa).

In the present document, a regulator100has been described, which allows the gain of the output stage103of the regulator100to be adapted, thereby reducing internal losses of the regulator100and/or enabling reduced dropout voltages.