Methods and apparatus to implement current limit test mode

Methods, apparatus, systems and articles of manufacture are disclosed. An example apparatus includes a gate controller coupled between an input terminal and an intermediate node, the gate controller including a first transistor coupled between the input terminal and a first node; a second transistor coupled between the first node and the intermediate node; a third transistor coupled between the input terminal and the intermediate node; and a charge pump coupled to the intermediate node; a switching network coupled between the intermediate node and an output terminal, the switching network including a high-side drive (HSD) transistor having a HSD gate terminal coupled to the intermediate node, the HSD transistor coupled between an input voltage and a switch node.

FIELD OF THE DISCLOSURE

This disclosure relates generally to current limiting, and, more particularly, to implementing current limit test mode.

BACKGROUND

Power converter circuits are used in various devices to convert input voltages to desired output voltages. For example, a buck converter converts an input voltage into a lower, desired output voltage by controlling transistors and/or switches to charge and/or discharge inductors and/or capacitors to maintain the desired output voltage. Such transistors/switches conduct current and, like most devices, have a threshold of current they are able to conduct until the transistor/switch is damaged.

The figures are not to scale. In general, the same reference numbers will be used throughout the drawing(s) and accompanying written description to refer to the same or like parts. As used in this patent, stating that any part (e.g., a layer, film, area, region, or plate) is in any way on (e.g., positioned on, located on, disposed on, or formed on, etc.) another part, indicates that the referenced part is either in contact with the other part, or that the referenced part is above the other part with one or more intermediate part(s) located therebetween. Stating that any part is in contact with another part means that there is no intermediate part between the two parts. Although the figures show layers and regions with clean lines and boundaries, some or all of these lines and/or boundaries may be idealized. In reality, the boundaries and/or lines may be unobservable, blended, and/or irregular.

DETAILED DESCRIPTION

As used herein, the term “above” is used with reference to a bulk region of a base semiconductor substrate (e.g., a semiconductor wafer) on which components of an integrated circuit are formed. Specifically, as used herein, a first component of an integrated circuit is “above” a second component when the first component is farther away from the bulk region of the semiconductor substrate. Likewise, as used herein, a first component is “below” another component when the first component is closer to the bulk region of the semiconductor substrate. As noted above, one component can be above or below another with other components therebetween or while being in direct contact with one another.

Switched mode power converters (e.g., boost converters, buck converters, buck-boost converters, etc.), or power conversion stages, are used to convert a first voltage (e.g., an input voltage) to a second voltage (e.g., an output voltage). Such power converters include a switching network including one or more switching transistors coupled to a switching node that is switched to form circuit arrangements to direct current through an energy storage inductor and/or to charge/discharge an output capacitor. Such circuit arrangements supply load current and regulate the output voltage to remain substantially steady at the second voltage.

In some examples, a buck converter includes two main power transistors. A power transistor, such as a metal-oxide semiconductor field-effect transistor (MOSFET), includes two current terminals and a gate terminal. To turn on the MOSFET (e.g., initiate current conducting through the two current terminals), a voltage is applied to the gate terminal, and the amount of voltage determines the amount of current the MOSFET will conduct. The two main power transistors can conduct an excessive amount of current during a circuit over current (e.g., excess current existing through a conductor leading to excessive generation of heat), a transient (e.g., a large spike of current generated by a load or the start-up of a voltage supply), or a short circuit (e.g., an unintended contact of electrical components such as a voltage directly coupled to ground, resulting in low impedance and high current). When such power transistors conduct excessive amounts of current, they generate heat, sometimes too much heat, and become damaged and therefore stop working as intended. In order to protect such power transistors from conducting excessive current, a current limit is implemented.

A current limit can be implemented by a current limiting circuit. A current limiting circuit is utilized to impose an upper limit on the current that is delivered to the load to protect the power converter, that is transmitting the current, from harmful effects. In some examples, a current limiting circuit turns off (e.g., switches off, removes power, etc.) the power transistor when it senses the current conducting through the transistor has exceeded the upper limit of current. In order to determine if the current limiting circuit is sensing the current conducting through the power transistors and switching off the power transistors when the current exceeds the upper limit, a manufacturer must test the current limiting circuit.

In some examples, the current limiting mechanisms are tested in an automated test environment (ATE). ATE can also be defined as automatic test equipment. ATE includes control hardware, sensors, and software that performs tests on the current limiting circuit and further collects and analyzes the test results. Some examples of ATE resources (e.g., test hardware, sensors, analog inputs and outputs, digital inputs and outputs, and software) include a computer, a digital signal processor (DSP) for analog testing, a test program/software operating on the computer, a probe head that touches a probe pad, a probe card or membrane probe to measure signal on a pin or pad of the circuit, etc. The ATE resources may have limited current capabilities. For example, the test hardware such as the current sources or current sinks, which are used for testing, can only provide milliamps of current.

In some examples, a power converter such as a buck converter, has an upper limit of current in the ampere range. For example, a power transistor of the power converter may conduct eight amperes of current, which is greater than milliamps of current. Therefore, it is difficult/not possible to test a current limiting circuit with ATE systems due to the ATE hardware having limited current capabilities. Further, manufacturers, designers, engineers, etc., design a scaled down version of a switching network in order for the ATE resources to properly test the current limiting circuit. For this purpose, it has to be rendered possible to turn on only a portion of the power transistor to test the current limiting circuit. In some examples, it is trivial to turn on only a portion of power transistors such as a low-side N-Channel MOSFET and a high-side P-Channel MOSFET. In examples disclosed herein, it is not trivial to turn on a portion of a the high-side N-Channel MOSFET.

To turn on only a portion of the power transistor to test the current limiting circuit, the power transistor of the power converter is split into two transistors, where the two transistors are coupled in parallel to each other. For example, one transistor may be 90 percent of the size of the original transistor and a second transistor may be 10 percent of the size of the original power transistor. In this manner, the ATE hardware can test the operation of the current limiting circuit by turning on only the smaller transistor which increases the impedance of the parallel connection of the two transistors. For example, by splitting the power transistor into two transistors, where one is large and the other is small, a ratio is created. The ratio corresponds to the ratio of the maximum allowed current that will conduct during a normal operation to the current the ATE resource is able to sink during a test mode operation.

For example, if the maximum allowed current is 10 amps during normal operation and the ATE resource can only sink 100 milliamps during current limit test mode operation, then the ratio is 100. In this manner, the smaller transistor is 1/100 the size of the original transistor and the bigger transistor is 99/100 the size of the original transistor. In this manner, the impedance of the small transistor is one-hundred times the impedance of the combination of the bigger transistor and the smaller transistor. Since the current limiting circuitry senses the voltage drop across the transistors, the current limiting circuitry will trip at 100 milliamps of load current if only the small portion is on (e.g., because the voltage drop across the small transistor at 100 milliamps is the same as the voltage drop across the parallel connection of big and small transistor at 10 amps). A gate controller operates to turn on only the small transistor when the current limiting circuit is being tested by the ATE resource.

Challenges may arise when designing a gate controller that is able to turn on both transistors when the power converter is in normal operation or one hundred percent mode operation and turn on only the small transistor and turn off the larger transistor when the power converter is being tested by an ATE system. Normal operation of the power converter includes turning on a high-side power transistor and turning off a low-side power transistor and turning on the low-side power transistor and turning off the high-side power transistor to provide a regulated output voltage to a load. one hundred percent mode operation is when the high-side power transistor is on one hundred percent of the time, and the voltage at the input of the power converter is provided to the output. Challenges arise due to the requirement that in normal or one hundred percent mode operation, the gate terminals of the two transistors (e.g., the big transistor and the small transistor) should have the same voltage potential in order for the current limiting circuit to work as intended, but in test mode operation, the gate terminals of the two transistors should not have the same voltage potential and the bigger transistor should be off while the smaller transistor should be on.

Examples disclosed herein include a gate controller that controls the connection between the two gate terminals of the transistors to achieve normal operation mode, one hundred percent operation mode, and test mode when required. For example, the gate controller includes a P-channel transistors (e.g., P-channel metal oxide semiconductor field-effect transistors (MOSFET) (PMOS)) based switch to control the connection between the two gate terminals of the bigger transistor and the smaller transistor. Examples disclosed herein also utilize one charge pump to assist the power converter to operate in one hundred percent mode. Additionally, the charge pump operates to turn on the small transistor during current limit test mode. A charge pump is similar to a switching regulator that delivers power to an output by only charging and discharging capacitors.

In some examples, multiple charge pumps are utilized in the gate controller to turn on power transistors, which can take up a large silicon area on a die (e.g., a small block of semi-conducting material on which a given functional circuit is fabricated). Also in some examples, two gate drivers are utilized to drive the gate terminals of the two transistors which takes up silicon area. The larger the area of the die, the more costly. Thus, examples disclosed herein decrease the area size of power converter and gate driver schematic by utilizing one charge pump, one gate driver, and the PMOS based switch of the gate controller.

FIG. 1is a block diagram of an example voltage converter apparatus100. The example voltage converter100includes an example switching network102coupled to an example gate driver104. The example gate driver104includes an example first transistor106and an example second transistor108, an example gate controller110, and an example boot-strap capacitor (Cboot)112to boost (e.g., increase) a bias voltage to provide a current to a drain terminal of the example first transistor106.

InFIG. 1, the example voltage converter apparatus100includes the example switching network102to step down an input voltage to a regulated output voltage to power a load. The example switching network102includes a plurality of power transistors to conduct current to flow into the switching network102to the load via an output116or block current from flowing to the load via the output116. The example switching network102is coupled to receive a controlled voltage via the example first transistor106, an input voltage118, and a controlled voltage at node126via the example gate controller110. The example switching network102operates in three main modes: normal mode, one hundred percent mode, and current limit test mode. When the example switching network102is operating in normal mode, the voltage on the switching node124is a square wave, similar to a pulse-width modulation (PWM) signal. When the example switching network102is operating in one hundred percent mode, the voltage on the output116is equal to the input voltage118. When the example switching network102is operating in current limit test mode, the voltage at switching node124and output116are similar to the output during one hundred percent mode (e.g., the voltage at the SW node124is the input voltage118minus a voltage drop across the one or more high side drive transistors of the switching network102).

InFIG. 1, the example voltage converter100includes the example gate driver104to receive an input signal (e.g., a PWM signal) from a controller integrated-circuit and a switchable bias voltage circuit103produce an amplified signal from the low-power input to inject into the gate terminals of the example MN0106and the example MN2108. For example, the low-power input may be generated from a PWM generator. In some examples, the PWM signal is a control signal that controls the current conducting through the power transistors of the switching network102. The PWM signal is a turn-on and/or turn-off signal generated to control the operation of the power transistors. A PWM signal is injected into the example gate driver104to be amplified and injected into the gate terminal of a switching transistor. The PWM signal is an oscillating signal varying in duty cycle. Alternatively, the PWM signal may vary in frequency, therefore noted as a Pulse Frequency Modulated signal (PFM).

The PWM and/or PFM signal injected into the gate driver104contains information pertaining to the turn on and/or turn off times of the transistor. For example, the gate driver104may be configured to provide a plurality of PWM signals to the transistors, wherein each PWM signal may be the same and turn on transistors simultaneously, or they may be different and turn on and off transistors in different time intervals. In other examples, the PWM and/or PFM signal injected into the gate terminal may contain information pertaining to the turn on and/or turn off times of any power switch.

InFIG. 1, the example voltage converter apparatus100includes the example gate driver105to receive a control signal (e.g., a PWM signal, PFM signal, etc.) from a controller and produce an amplified signal from the low-power input to inject into the gate terminals to control an operation of a portion of the switching network102. For example, the gate driver105controls the operation of a low-side drive (LSD) transistor of the switching network102. The example gate driver105may be a power amplifier on an integrated chip (IC) or on a discrete module. In other examples, the gate driver105may include a plurality of electrical components that work together to amplify a low-power input signal to turn on or turn off a LSD transistor of the switching network102.

InFIG. 1, the example gate driver104includes the example first transistor106and the example second transistor108. The example first transistor (MN0)106and the example second transistor (MN2)108are N-channel MOSFETs (NMOS). Alternatively, MN0106and MN2108may be P-Channel MOSFETs, PNP BJTs, NPN BJTs, etc. Alternatively, MN0106and MN2108may be a switch or any other type of power switching device.

An NMOS includes two current terminals and a gate terminal, wherein one of the current terminals is a drain terminal and the second current terminal is a source terminal. The gate terminal of an NMOS controls the current that conducts out of the drain terminal to the source terminal. The NMOS operates in a linear mode when the gate-to-source voltage (Vgs) is greater than a threshold voltage (Vth) of the MOSFET and when the drain-to-source voltage (Vds) is less than the Vgs minus the threshold voltage (e.g., Vgs>Vth; Vds<Vgs−Vth). When the NMOS is in triode mode, the current conducting through the drain terminal (Id) to the source terminal is dependent upon the amount of voltage applied to the gate terminal. For example, if Vgs is small, then little drain current conducts, but when Vgs is big, then more drain current conducts. The NMOS operates in a saturation mode when Vgs>Vth and when the voltage Vds is greater than the voltage Vgs minus the threshold voltage (e.g., Vgs>Vth; Vds>Vgs−Vth). When the NMOS is in saturation mode, the drain terminal and source terminal act like a current source. In linear mode, current conducting through the two terminals varies depending on an increasing Vds voltage once the voltage has exceeded the threshold for saturation. In saturation, the current varies depending on an increasing gate voltage. Lastly, the NMOS operates in a cut-off mode when the Vgs is less than the threshold voltage Vth. In cut-off mode, no drain current Id conducts through the terminals.

In the illustrated example, a drain terminal of the first transistor106is coupled to the example Cboot112, a gate terminal of the example first transistor106is coupled to receive a first PWM signal (PWM), and a source terminal of the example first transistor106is coupled to a drain terminal of the example second transistor108at an example GATE_BIG node122. In the illustrated example, a gate terminal of the example second transistor108is coupled to receive a second PWM signal (PWM2), and a source terminal of the second transistor108is coupled to a portion of the switching network102at a switch (SW) node124.

InFIG. 1, the example gate driver104includes an example switchable bias voltage circuit111coupled to the example Cboot112. The switchable bias voltage circuit111is a bias voltage supply that provides a voltage to the Cboot112depending on the PWM input at the PWM node132to the example gate driver104. For example, a controller (e.g., a PWM generator) provides a high voltage signal to the gate driver104which initiates the switchable bias voltage circuit111to provide a voltage to the Cboot112. In other examples, a controller provides a low-voltage signal to the gate driver104to cause the switchable bias voltage circuit111to short the Cboot112to ground, thereby removing the voltage provided to the bottom plate of the Cboot112. The switchable bias voltage circuit111outputs a voltage that is corresponding to the value of the incoming PWM signal that is provided to the example gate driver104. For example, if the incoming PWM signal is low, the switchable bias voltage circuit111grounds the bottom plate of Cboot112. If the incoming PWM signal is a high (e.g., 1 volt), the switchable bias voltage circuit111applies a voltage to the bottom plate of the Cboot112, thereby increasing the voltage at the boot strap node120. The switchable bias voltage circuit111is initiated (e.g., outputs a high voltage) when the example voltage converter100is operating in normal mode or one hundred percent mode and the switchable bias voltage circuit111does not output a high voltage to the example Cboot112when the voltage converter100is operating in current limit test mode.

InFIG. 1, the example gate driver104includes the example gate controller110to enable the ATE test of the circuitry, which imposes an upper limit of current on the example switching network102. For example, the gate controller110includes a plurality of transistors, which may work together to adjust the impedance of a transistor of circuitry depending on the mode of operation. Essentially, the example gate controller110controls the state of operation of the example switching network102because the gate controller110decides which gate terminals of the switching network102to pull up (e.g., increase the voltage to the output of the first transistor106or increase the voltage to the voltage at node126). The example gate controller110is coupled to receive the input voltage118and determined to be coupled to receive the controlled voltage from the example first transistor106or the boosted voltage from the example Cboot112.

In some examples, the gate controller110is to assist an ATE system in testing circuitry which imposes an upper limit of current on the switching network102for proper operation during current limiting. For example, an ATE system with limited current capabilities may be used to test the circuitry, therefore the gate controller110must be able to control a portion of the switching network102, wherein the portion of the switching network will conduct a smaller amount of current than the whole switching network102would conduct. In order to be able to control (e.g., turn on and turn off) the whole switching network102or a portion of the switching network102, the example gate controller110is to be coupled to receive either the boosted voltage or the controlled voltage. The example switching network102and the example gate controller110are described in further detail below in connection withFIG. 2.

InFIG. 1, the example gate driver104includes the example Cboot112to boost or increase a bias voltage. A capacitor is a two terminal electrical component which stores potential energy in an electric field. The example Cboot112includes a first capacitor terminal and a second capacitor terminal, the first capacitor terminal is coupled to a switchable bias voltage circuit111of the example gate driver104and the second capacitor terminal is coupled to the drain terminal of example MN0106. A boot-strap capacitor acts to exceed the voltage output by the switchable bias voltage circuit111to twice the supply voltage (e.g., VIN118) in order to enable the turning on of the high-side NMOS type power transistor of the switching network102when PWM signal at the PWM node132is HIGH (e.g., logic 1) and when the voltage at the SW node124equals the voltage at VIN118.

InFIG. 1, the example MN2108of the example voltage converter100includes an example MN2body diode114coupled between the MN2drain terminal and the MN2source terminal. A body diode is an intrinsic feature of a MOSFET formed by the PN junction between the drain terminal and a bulk region of a MOSFET, wherein the drain terminal is an n-type material and the bulk region is a p-type material for an NMOS transistor. As used herein, the PN junction is a boundary or interface between two types of semi-conductor materials, p-type and n-type, wherein the p-type includes “holes” and is considered positive and the n-type includes electrons and is considered negative. In some examples, a body diode is referred to as a parasitic diode, a back-gate diode, or an internal diode.

FIG. 2illustrates an example schematic of the example switching network102and an example schematic of the example gate controller110that overcomes the challenge of initiating the three operating states of the example switching network102(e.g., normal mode, one hundred percent mode, and current limit test mode). The illustrated example schematic of the gate controller110inFIG. 2includes less power transistors relative to other gate controllers and one charge pump (CP), which decreases total die area (e.g., block of semiconducting material on which a given functional circuit is fabricated) relative to the gate controllers that utilize more charge pumps and transistors.

InFIG. 2, the example schematic of the example switching network102includes an example third transistor (HSD_BIG)202, an example fourth transistor (HSD_SMALL)204, an example fifth transistor (LSD)206, an example pull_down transistor208, an example inductor (L1)210, and an example output capacitor (Cout)212.

InFIG. 2, the example schematic of the example switching network102includes the example HSD_BIG202to conduct current from a drain terminal of the HSD_BIG202to SW node124to charge the example L1210. The example HSD_BIG202includes the drain terminal coupled to the input voltage118, a gate terminal coupled to GATE_BIG node122, and a source terminal of the HSD_BIG202coupled to the source terminal of MN2108, a drain terminal of low-side drive transistor206, and the example L1210at the SW node124. The example HSD_BIG202is a high-side drive NMOS which conducts large amounts of current (e.g., 1 amp to 8 amps) when a high voltage is applied to the gate terminal of HSD_BIG202(e.g., GATE_BIG node122is a high voltage). A high-side drive transistor, when enabled or activated, allows current to flow from supply (e.g., Vin), or a first phase voltage, through an inductor (e.g., L1210) to an output capacitor (e.g., Cout212), thereby charging the output capacitor Cout212and increasing the output voltage.

InFIG. 2, the example schematic of the example switching network102includes the example HSD_SMALL204to conduct current, smaller than the current conducting through the drain terminal of HSD_BIG202, from a drain terminal of the HSD_SMALL204to the SW node124. The example HSD_SMALL204includes a drain terminal coupled to the input voltage118, a gate terminal coupled to a drain terminal of an example eleventh transistor (MP1)232of the example gate controller110; a drain terminal of the example pull down transistor208; a source terminal of the example MP3214; and the example charge pump236, and an example source terminal coupled to a drain terminal of the example LSD206at the SW node124and coupled to an example inductor210. The example HSD_SMALL204is the same transistor type as the HSD_BIG202except the HSD_SMALL204is smaller (e.g., less total channel width) than HSD_BIG202, thereby having a higher impedance (e.g., the HSD_SMALL204cannot conduct as much current as HSD_BIG204). For example, the conducting state of HSD_SMALL204is determined by an example twelfth transistor (MP1)232and the MP0228of the example gate controller110, wherein the MP1232is configured to be coupled to the gate terminal of the HSD_BIG202and the gate terminal of HSD_SMALL204when the voltage converter100is to operate in normal mode or one hundred percent mode, and configured to remove the connection between HSD_BIG202and HSD_SMALL204when the voltage converter100is to operate in current limit test mode.

InFIG. 2, the gate terminal of the example HSD_BIG202and the gate terminal HSD_SMALL204are coupled together (e.g., when MP0228and MP1232are enabled). For example, the HSD_SMALL204replicates the operation of HSD_BIG202(e.g., the HSD_SMALL204and HSD_BIG202operate in parallel). Thus the HSD_SMALL204and HSD_BIG202conduct current from their respective drain terminal that is generated by input voltage118to L1210, thereby expanding the L1210magnetic field.

InFIG. 2, the example schematic of the example switching network102includes the example low-side drive transistor (LSD)206to conduct when the HSD_BIG202and HSD_SMALL204are not conducting. The example LSD206is an N-channel MOSFET that includes a drain terminal coupled to the source terminal of the example HSD_SMALL204at the SW node124, the source terminal of HSD_BIG202, the source terminal of MN2108, and to the inductor L1210. The example LSD206also includes a gate terminal coupled to the example LSD gate driver105, and a source terminal coupled to ground. Additionally or alternatively, the example LSD206may be a P-channel MOSFET, a bipolar junction transistor (BJT), or any other type of power switching device. A low-side transistor, when enabled or activated, pulls the SW node124to ground, thus creating a negative voltage across inductor L1210and thereby decreasing the current (e.g., the magnetic field) flowing through L1210.

InFIG. 2, the example schematic of the example switching network102includes the example pull_down transistor208to pull the voltage at GATE_SMALL240to ground when the digital signal at an second PWM node133goes high. For example, when MN2108discharges the voltage at GATE_BIG122to SW node124, the pull_down transistor208discharges GATE_SMALL node240to ground. The example pull_down transistor208operates in a saturation mode when the voltage applied to the gate terminal is greater than the Vth of the example pull_down transistor208and when the voltage at GATE_SMALL node240is greater than the Vgs minus Vth. For example, when the pull_down transistor208is operating in saturation mode, the current at GATE_SMALL node240conducts to the source terminal of the pull_down transistor208and to ground, resulting in the voltage at GATE_SMALL node240to decrease. The example pull_down transistor208operates in cut-off mode when the voltage applied to the gate terminal is less than the Vth. For example, when little to no voltage is applied to the gate terminal of the example pull_down transistor208, the voltage at GATE_SMALL node240depends on the output of the example gate controller110(e.g., node126).

InFIG. 2, the example schematic of the example switching network102includes the example inductor210which is a two terminal electrical component that stores energy in a magnetic field when current flows through it. The example inductor210includes a first inductor terminal and a second inductor terminal, the first inductor terminal coupled to the source terminal of the example HSD_BIG202, to the source terminal of the example HSD_SMALL204, the source terminal of the example MN2108, and the drain terminal of the example LSD206at the switch node124, and the second inductor terminal coupled to the output capacitor Cout212at the output node116. During a high side operation (i.e., the HSD_BIG202and/or HSD_SMALL204is/are conducting) energy is stored in the inductor210. On the other hand, during low side operation (i.e., the LSD206is conducting) energy is discharged from the inductor210to ground. During low side operation of normal mode, the current flowing through the inductor L1210is reducing, thereby reducing the energy stored in its magnetic field of the example L1210. The example inductor210creates a ripple current that occurs during the switching on and off of the HSD_BIG202and/or HSD_SMALL204and LSD206. Both HSD_SMALL204and HSD_BIG202are connected to the inductor L1210. As used herein, ripple current is defined as the peak-to-peak change in current during the on time of a switching transistor.

InFIG. 2, the example schematic of the example switching network102includes the example output capacitor Cout212. The example Cout212is a two terminal electrical component which stores energy when a voltage is applied across its terminals (e.g., when there is a voltage difference between the top and bottom plates of the Cout212). The example Cout212includes a third capacitor terminal and a fourth capacitor terminal, the third capacitor terminal is coupled to the second inductor terminal of the inductor L1210.

The example switching network102is coupled to the example gate controller110to facilitate correct current limit operation in normal mode and in one hundred percent mode by shorting GATE_SMALL240with GATE_BIG122(e.g., via the enabled MP0228and MP1232). The gate controller110facilitates one hundred percent mode operation by refreshing the potential at GATE_SMALL240and GATE_BIG122via the charge pump236. Additionally, the gate controller110increases the combined impedance of HSD_BIG202and HSD_SMALL204in current limit test mode by disconnecting the connection (e.g., creating an open circuit) between GATE_SMALL240with GATE_BIG122. In this manner, the charge pump236can output a voltage to the GATE_SMALL node240to on HSD_SMALL204without HSD_BIG202turning on also (e.g., while HSD_BIG202is off) to enable testing of the current limit circuitry with the limited current capabilities of the ATE resources.

InFIG. 2, the example schematic of the example gate controller110which includes an example seventh transistor (MP3)214, an example eight transistor218, an example thirteenth transistor (MN3)219, an example ninth transistor (MN1)222, an example tenth transistor (MP2)224, an example eleventh transistor (MP0)228, an example twelfth transistor (MP1)232, and an example charge pump (CP)236.

InFIG. 2, the example MP3214, the example eighth transistor218, the example MP2224, the example MP0228, and the example MP1232are P-channel MOSFETS. A P-channel MOSFET is on (e.g., current is conducting out of the drain terminal) when the voltage across the gate terminal and source terminal is less than a threshold voltage. A P-channel MOSFET operates in cut-off mode (e.g., current is not conducting from the drain terminal) when the source terminal-to-gate terminal voltage is less than a threshold voltage. Each of the example P-channel; MOSFETS MP3214, eighth transistor218, MP2224, MP0228, and MP1232include an example body diode. A body diode is an intrinsic diode formed in the body of a transistor due the PN junction between the p-material and the n-material of the transistor. For example, a transistor includes a body which refers to the bulk of the semiconductor in which the gate terminal, source terminal, and drain terminal are all connected. The body of a P-channel transistor creates an intrinsic body diode due to the PN junction formed between the n-material of the body and the p-material of the source terminal and drain terminal. The example MP3214includes a drain terminal coupled to the example eighth transistor218, a gate terminal coupled to the source terminal of the example MN0106, and a source terminal coupled to the example GATE_SMALL node240at node126. The example eighth transistor218includes a source terminal coupled to an example TEST_GATE node (e.g., test gate node)246, a gate terminal coupled to the input voltage118, and a drain terminal coupled to the example MP3214drain terminal and the MN3drain terminal of the example MN3transistor219.

InFIG. 2, the example MP2224includes an example drain terminal coupled to the input voltage118, and an example gate terminal coupled to an example source terminal, wherein the source terminal is coupled to the example MN1222at the TEST_GATE node246. The example MP0228includes an example drain terminal coupled to the example GATE_BIG node122, an example gate terminal coupled to the TEST-GATE node246, and an example source terminal coupled to the example MP1232. The example MP1232includes an example source terminal coupled to the MP0source terminal, an example gate terminal coupled to the TEST_GATE node246, and an example drain terminal coupled to the CP236and to the node126.

InFIG. 2, the example schematic of the example gate controller110includes the example MN1222to bias the voltage at the TEST_GATE node246when operating in normal operation to turn on example MP0228and example MP1232. The example MN1222includes an example source terminal coupled to the input voltage118, an example gate terminal coupled to the MP3gate terminal (e.g., the MP3gate terminal and the MN1gate terminal are coupled to the MN0source terminal and to GATE_BIG node122), and an example drain terminal coupled to TEST_GATE node. InFIG. 2, an electrical effect of a body diode of the example MN2222has been reduced, or otherwise eliminated, by biasing the body of the transistor to ground. For example, MN1222does not have the effect of the intrinsic body diode because the intrinsic body diode is always reverse-biased. In this manner, the MN2222does not have the same effect as the body diodes of example MN2108, example MP0228, example MP1232, example MP2224, and example MP3214. Body diodes are described in further detail below in connection with the example fourth body diode220ofFIG. 2.

InFIG. 2, the example schematic of the example gate controller110includes the example charge pump236to charge the GATE_SMALL node240when a voltage is applied to an example enable pin. The example CP236is a dual purpose CP and is coupled to receive the input voltage118and includes an example output pin coupled the MP1drain terminal as well as the GATE_SMALL node at node126; the source of the example MP3214; and the drain of the example pull down transistor208, and further includes the example enable pin coupled to an example controller238. The example CP236may be a charge-pump doubler. A charge-pump doubler is a charge pump that doubles the amount of input voltage118at the output voltage by stacking two capacitors, where one capacitor is coupled to the input voltage118and ground and the second capacitor is coupled to input voltage118and the output. Additionally or alternatively, the example CP236may be an unregulated or pre-regulated doubler, or a multi-capacitor/multi-gain boost CP. The example CP236is further illustrated inFIG. 7B.

The example schematic of the example gate controller110ofFIG. 2includes the example controller238to enable or disable the example CP236. The example controller238may be an oscillator, a PWM generator, etc., which is configured to output some voltage onto TM node248. For example, the controller238is configured to generate varying voltages and currents from a power source to an output (e.g., TM node248).

The example schematic of the example gate controller110ofFIG. 2includes the example MN3219to provide over voltage protection for transistor218and transistor214of the example gate controller110. The example MN3219is an NMOS includes an MN3gate terminal coupled to an MN3source terminal and ground. Additionally, the MN3219includes an MN3drain terminal coupled to the drain terminal of the transistor214and the drain of the transistor218.

The example voltage converter apparatus100includes three operating modes, as described above in connection withFIG. 1. The three operating modes are normal mode, one hundred percent mode, and current limit test mode. The example switching network102and the example gate controller110operate together in a manner to achieve one of the three different modes of operation of the example voltage converter apparatus100.

In a normal operating mode, the example switching network102ofFIG. 2provides a regulated output voltage to a load via the output node116and the example gate controller110ensures that GATE_BIG node122and GATE_SMALL node240are shorted together to ensure that current limit circuitry operates as intended. The example normal mode operation begins when the switchable bias voltage circuit103applies a voltage to the MN0gate terminal based on the PWM signal at the PWM node132. For example, when Vbias is zero volts the voltage at the boot strap node120is five volts and the switchable bias voltage circuit103amplified the incoming PWM signal at the PWM node132to ten volts at the MN0gate terminal, the example MN0106turns on and the charge at the boot strap node120flows from the MN0drain terminal to the MN0source terminal, which is coupled to the MP3gate terminal, MN1gate terminal, MP0drain terminal, and to the GATE_BIG node122. The example C_BOOT112has not begun the boot-strapping operation.

Concurrently, the example input voltage118is applied to MP2drain terminal and to the example fourth body diode226. In normal operation mode, the input voltage118forward biases the example fourth body diode226and charges the TEST_GATE node246to the input voltage118minus the voltage drop of the fourth body diode226. For example, if the input voltage118is five volts and the body diode226is a silicon diode, then five volts minus the voltage drop across the fourth body diode226is about is 4.3 volts. Thus, the TEST_GATE node246is charged to 4.3 volts. A silicon diode operating as forward bias has a voltage drop of 700 millivolts because of the inherent depletion region of the PN junction. When the diode is forward biased, the p-type material is coupled to a positive terminal such as an input voltage118and the n-type material is coupled to a negative terminal such as a terminal not receiving voltage. In this manner, when the voltage is applied to the p-type material, the electrons of the n-type material are forced over the PN junction (e.g., the interface) and some are lost in the process, thus causing the voltage drop across the diode. In other examples, a diode may be less than or greater than 700 millivolts, such as a Schottky diode, a germanium diode, a light emitting diode, etc.

InFIG. 2, when bootstrapping has not occurred, the example MP3214, the example MP0228, and the example MP1232are turned off because the MP3214, MP0228, and MP1232have a Vgs above the threshold voltage. The respective gate-to-source voltages of MP3214, MP0228, and MP1232are above the threshold voltage because during normal operation mode, the example CP236is not enabled by the example controller238. For example, the controller238outputs zero volts, a logic 0, etc., on the TM node248to not enable the CP236to double the input voltage118at the output. Further, there is no voltage at node GATE_SMALL node240because whatever voltage was there has been discharged to ground by the example pull_down transistor208.

InFIG. 2, the example MP0228is turned off because the voltage on MP0source terminal and the voltage on TEST_GATE246does not meet the threshold voltage required to turn on the P-channel MOSFET. For example, when the TEST_GATE node246has been charged to 4.3 volts, 4.3 volts are applied to the MP0gate terminal. In such an example, the MP0drain terminal is coupled to the MN0source terminal, which is five volts. Thus, the Vgs of MP0228does not meet the Vth to turn on (e.g., 4.3 volts−5 volts=−0.7 volts).

InFIG. 2, when bootstrapping occurs, the example switchable bias voltage circuit111outputs a Vbias and the example C_BOOT112boosts the Vbias voltage to a higher voltage at the charge node120. The second example switchable bias voltage circuit103outputs a voltage (e.g., when the signal at the PWM node132is high) to the gate of the example MN0106that is high enough to ensure that the MN0transistor106is turned on. In this manner, the voltage at the MN0gate terminal is greater than the voltage at node120to turn on the example MN0106. Further, when the example MN0106is turned on, current conducts through the MN0drain terminal to the MN0source terminal Thus, the voltage at the MN0source terminal is the same voltage at GATE_BIG node122, MP3gate terminal, MN1gate terminal, and MP0drain terminal. In response to the bootstrapping, the example MN1222, the example MP0228, and the example MP1232turn on and the example MP3214remains turned off. In this manner, the example MN1222will turn on, and bias the TEST_GATE246node to the input voltage118. When the voltage at the TEST_GATE node246equals the input voltage118, the value of the voltage at the TEST_GATE node246is applied to the MP0gate terminal and the MP1gate terminal which turns on the example MP0228and the example MP1232. For example, the Vgs of both the MP0228and the MP1232are “negative” because the voltage at the MP0source terminal and the MP1drain terminal is greater than the voltage at the MP0gate terminal and the MP1gate terminal. The gate-to-source voltages of the MP0228and MP1232are negative because for a PMOS, the voltage at the gate terminal must be smaller than the voltage at the source terminal to turn on the PMOS (e.g., a differential potential between the gate and the source being negative turns on the two P-channel MOSFETS MP0228and MP1232.

In this manner, the voltage at GATE_SMALL node240equals the voltage at GATE_BIG node122. For example, the voltage at the MP0drain terminal is equal to the voltage at the GATE_BIG node122, and when the example MP0228turns on, that voltage (e.g., MP0drain terminal voltage) charges the GATE_SMALL node240to be equal to the GATE_BIG node122. The example GATE_BIG202and the example GATE_SMALL240are “shorted together” (e.g., the HSD_BIG gate terminal and the HSD_SMALL gate terminal are coupled to each other and receiving identical voltages). In this manner, the example voltage converting apparatus100is operating in normal mode because both of the HSD transistors (e.g., HSD_BIG202and HSD_SMALL204) are on. Both of the HSD transistors (202and204) are turned on and their respective gates have the same potential, thus ensuring that the current limiting circuitry is operating as intended in normal mode (GATE_BIG=GATE_SMALL is a hard requirement for the current limiting circuitry to operate as intended in normal mode). The SW node124charges to the input voltage118when the example HSD_BIG202and the example HSD_SMALL204turn on and there is a positive voltage (e.g., the voltage at the SW node124is greater than the voltage at the output116) across the inductor210. Thus, the energy is stored in the example inductor210and the magnetic field of the inductor210expands.

InFIG. 2, the example gate driver104may reduce the voltage applied to the MN0gate terminal and the MN2gate terminal to turn off the transistors MN0106and MN2108. For example, the gate driver104may be configured to be coupled to receive a control signal from a pulse-width modulation (PWM) generator. In some examples, the PWM signal is a control signal because it controls the current conducting through the transistors. The PWM signal is a turn-on and/or turn-off signal generated to control the operation of the transistors. A PWM signal is injected into a gate terminal of a switching transistor via the gate driver104. The PWM signal is an oscillating signal varying in duty cycle. Alternatively, the PWM signal may vary in frequency, therefore noted as a Pulse Frequency Modulated signal (PFM). The PWM and/or PFM signal injected into the gate terminal via the gate driver104contains information pertaining to the turn on and/or turn off times of the switching transistor. For example, the PWM generator may be configured to provide a plurality of PWM signals to the example MN0106(e.g., via the switchable bias voltage circuit103), the example MN2108, and the example LSD206, wherein each PWM signal may be the same and turn on the transistors simultaneously, or they may be different and turn on and off the transistors in different time intervals.

InFIG. 2, when the example gate driver104removes the voltage injected into the MN0gate terminal, it may inject a voltage into the LSD gate terminal. For example, two different PWM signals may be 180 degrees out of phase (e.g., include the same frequency but operating in an opposite manner), wherein when the first PWM signal is high, the second PWM signal is low, and when the second PWM signal is high, the first PWM signal is low. In this manner, the HSD_BIG202and HSD_SMALL204are on when LSD206is off, and LSD206is turned on when HSD_BIG202and HSD_SMALL204are turned off. This occurs in normal operation mode because the gate driver104operates to regulate the voltage at the output node116by expanding the magnetic field in the example inductor210when the two high side transistors are turned on and collapsing the magnetic field of the example inductor210when the LSD206is turned on, releasing regulated voltage to a load.

InFIG. 2, the example schematics of the example switching network102and the example gate controller110act to turn on the example HSD_BIG202before turning on the example HSD_SMALL204when operating in normal mode. Turning on the example HSD_BIG202first enables the turning on of the example MP0228and the example MP1232, which can be referred to as the switches that connect and/or disconnect the GATE_BIG node122and the GATE_SMALL node240. During normal operation, when HSD_BIG202is turned on first, MP0228and MP1232automatically turn on. During test mode operation, when the charge pump236is turned on first to start charging the GATE_SMALL, MP0228and MP1232remain turned off automatically. Accordingly, the example gate controller110is “self-controlled.” Because the structure of MP0228and MP1232makes the gate controller110self-controlled, the structure of the example gate controller110is simple and consumes little die area.

The second example operating mode is current limit test mode, wherein the example HSD_SMALL204of the example switching network102ofFIG. 2is permanently on, driven by the example gate controller110. In this manner, the gate controller110increases the impedance of the switching network102by only turning on the HSD_SMALL204, which enables the testing of current limit circuitry, not disclosed herein, with just milliamps of current (e.g., as opposed to amperes of current), by utilizing hardware such as an ATE system.

The current limit test mode begins when the example controller238enables the example CP236. For example, the controller238may output a logic 1 or a positive voltage to the enable pin of the CP236, which activates the CP236to begin doubling the input voltage118at the output (e.g., the output of the CP236is coupled to node126and GATE_SMALL node240). In some examples, due to inherent capacitances at intermediate node126of the example voltage converter apparatus100, the GATE_SMALL node240increases linearly when the CP236is activated. As used herein, inherent capacitance is the term used when describing the unavoidable response of the circuit components in the example schematics of the example switching network102and the example gate controller110when there is a change in electric potential (e.g., voltage).

When the GATE_SMALL node240begins to increase due to the charging at the output of the example CP236, the voltage at SW node124follows the voltage at GATE_SMALL node240because the voltage at SW node124is equal to the voltage at GATE_SMALL node240minus the Vth of HSD_SMALL204. As the voltage at GATE_SMALL node240increases to the input voltage118plus Vth, the voltage at the SW node124reaches the input voltage118and stays at the input voltage118(e.g., the voltage at the SW node124cannot surpass this voltage due to the drain terminal of HSD_SMALL204equaling the input voltage118). The voltage at GATE_SMALL node240continues increasing until the voltage is approximately two times the input voltage118, bringing HSD_SMALL204into linear mode (e.g., Vgs−Vth>Vds; as Vgs=Vin and Vds is very small). The voltage drop across the example HSD_SMALL204depends on the current of the drain terminal going into the ON resistance of the transistor (Rdson). Rdson is a term used to define the resistance of a MOSFET when the MOSFET is operating in linear mode. The voltage drop across a transistor in linear mode is Rdson times the current at the drain terminal (Id).

In response to the SW node124charging and GATE_SMALL node240charging, the example first body diode114coupled to the example MN2108becomes forward biased, resulting in the current through the forward biased diode114charging the example GATE_BIG node122. For example, the voltage at the GATE_BIG node122is one diode voltage below the voltage at the SW node124, or in other examples, the voltage at the GATE_BIG node122is equal to the voltage at the SW node124minus the voltage drop across the example first body diode114. Additionally, the example MN2108is not turned on because the example gate driver104is not applying a high voltage to the MN2gate terminal.

When GATE_BIG node122is charged to equal one diode voltage below the voltage at the SW node124, the example MP3214turns on. For example, the MP3gate terminal is coupled to the GATE_BIG node122and the MP3source terminal is coupled to the GATE_SMALL node240, wherein the voltage at the MP3gate terminal is a threshold voltage plus diode voltage less than the voltage at the MP3source terminal, causing the MP3214to turn on. The voltage at the MP3source terminal is across the MP3drain terminal and further forward biases the example third body diode220that is coupled to the example eighth transistor218. In this manner, the example third body diode220charges the TEST_GATE node246to be equal to one diode voltage below the voltage at the GATE_SMALL node240. Because, the voltage at the TEST_GATE node246is applied to the MP0gate terminal and the MP1gate terminal, the example MP0228and the example MP1232are turned off (e.g., because the threshold voltages of MP0228and MP1232are greater than one diode voltage, 700 millivolts).

In the example current limit test mode, when the example CP236charges the GATE_SMALL node240to be equal to twice the amount of input voltage118, the example HSD_SMALL204enters linear mode. During the first half of the charging phase, HSD_SMALL204is in saturation mode (e.g., the voltage at the SW node124is one threshold voltage below the voltage at GATE_SMALL node240). As the voltage at GATE_SMALL node240surpasses a total voltage equal to the input voltage118plus the threshold voltage and the voltage at the SW node124reaches the input voltage118potential, the example HSD_SMALL204enters linear mode. In this manner, the voltage at the SW node124forward biases the example first body diode114. The example first body diode114charges the GATE_BIG node122to be equal to one diode voltage less than the voltage at the SW node124(e.g., the input voltage118) because the example HSD_SMALL204is operating in linear mode and fully on).

The example MP3214enters linear mode during the beginning of the charging phase. The MP3source terminal is shorted to the MP3drain terminal and the voltage at the MP3drain terminal equals the voltage at the GATE_SMALL node240. For example, the MP3source terminal is coupled to the GATE_SMALL node240at node126, and therefore, when the MP3source terminal and MP3drain terminal are shorted together, the MP3drain terminal receives the voltage at the GATE_SMALL node240. Further, the gate of the example eighth transistor218equals the input voltage118. When the MP3drain terminal exceeds the input voltage118plus threshold voltage, the eighth transistor218turns on (e.g., the eighth transistor source terminal is one threshold voltage greater than the eighth transistor gate terminal). When the eighth transistor218turns on, the voltage at the TEST_GATE node246is equal to the voltage at the MP3drain terminal, and, the voltage at GATE_SMALL node240. When the TEST_GATE node246is charged to equal the voltage at GATE_SMALL node240, the example MP0228and the example MP1232are in complete cut-off mode, wherein zero current is conducting through the example transistors228,232. For example, the MP0drain terminal is coupled to the MP3gate terminal, which is receiving one diode voltage below the input voltage118, and the MP0gate terminal is coupled to the TEST_GATE node246, which is receiving two times the input voltage118(e.g., due to the CP236charging the GATE_SMALL node240), therefore the MP0228is turned off.

The example current limit test mode is achieved when the example MP0228and the example MP1232are operating in cut-off mode. For example, when MP0228and MP1232are operating in cut-off mode, the HSD_SMALL gate terminal is disconnected from the HSD_BIG gate terminal, and only the HSD_SMALL204is turned on. Thus, a higher impedance of the total high-side drive transistor is achieved, since only a portion of the total high-side drive transistor (e.g., HSD_SMALL204) is on. In this manner, current limit circuitry, not disclosed herein, will trigger at a milliamp level of Isw244instead of an ampere level. The increase of the impedance (e.g., causing an increase of the voltage drop across the HSD_SMALL204) aids to test the example current limit circuitry when the ATE system is limited to sinking milliamps of current. When the example current limit test mode is achieved, bootstrapping is not occurring, the example MN0106is not turned on, and the example HSD_BIG202is not turned on. The ATE system replaces the inductor L1210at the at the SW node124and acts as a current sink (e.g. loads HSD_SMALL204) during current limit test mode. Now that the impedance of the parallel combination of HSD_BIG202and HSD_SMALL204has increased (e.g., since HSD_BIG202is off and HSD_SMALL204is on), the voltage drop across HSD_SMALL204and HSD_BIG202which is necessary to trigger the current limit circuitry will occur at only milliamps of current as compared to amps of current during normal operation, which allows for the current limit circuitry to be properly tested by the ATE system.

Internal logic of the gate driver104determines when to exit current limit test mode by utilizing a second PWM signal at the second PWM node133to turn on the pull_down transistor208. For example, when the second PWM signal at the second PWM node133goes high (e.g., logic 1, threshold voltage, etc.), the pull_down transistor208turns on and discharges the GATE_SMALL node240to ground. In this manner, the voltage at HSD_SMALL gate terminal is removed and HSD_SMALL204turns off.

Additionally, the example controller238assists to exit current limit test mode. The example controller238outputs a logic zero to TM node248to turn off the CP236, which in turn discontinues charging the intermediate node126to only turn on HSD_SMALL204and keep HSD_BIG202off. When the switching network102has exited current limit test mode, normal mode or one hundred percent mode can be achieved.

The third example operating mode is one hundred percent mode, wherein the example high-side drive transistors HSD_BIG202, HSD_SMALL204of the example switching network102ofFIG. 2are always on. The one hundred percent mode of operation begins in a similar manner as the normal mode of operation, wherein bootstrapping occurs to turn on the example HSD_BIG202and then turn on HSD_SMALL204by activating the example MP0228and the example MP1232, and the example CP236is not enabled. In some examples, the C_BOOT112may begin to leak current. Leakage current is a small amount of current that leaks from one capacitor terminal to the second capacitor terminal, which results in a voltage loss and causes the energy stored in the capacitor to drain. In one hundred percent mode, leakage current may cause the example HSD_BIG202and the example HSD_SMALL204to turn off if enough charge is lost due to leakage.

InFIG. 2, the example CP236is enabled during one hundred percent mode to refresh the voltage at the GATE_SMALL node240and the voltage at the GATE_BIG node122. For example, MP0228and MP1232are turned on and shorted together. In this manner, when the CP236is enabled, two times the input voltage118is injected into the HSD_SMALL gate terminal and two times the input voltage118is injected into the HSD_BIG gate terminal, because the two gate terminals are shorted together by MP0228and MP1232.

InFIG. 2, the example CP236is dual purpose because it operates to increase the voltage at GATE_SMALL node240in current limit test mode, and it operates to refresh the voltage at GATE_BIG node122and GATE_SMALL node240in one hundred percent mode. In some examples, the dual purpose CP236decreases area size of the example schematic because only one CP is needed and not two to perform the functions described above.

While an example manner of implementing the gate controller110ofFIG. 1is illustrated inFIG. 2, one or more of the elements, processes and/or devices illustrated inFIG. 2may be combined, divided, re-arranged, omitted, eliminated and/or implemented in any other way. Further, the example controller238ofFIG. 2may be implemented by hardware, software, firmware and/or any combination of hardware, software and/or firmware. Thus, for example, the example controller238could be implemented by one or more analog or digital circuit(s), logic circuits, programmable processor(s), programmable controller(s), graphics processing unit(s) (GPU(s)), digital signal processor(s) (DSP(s)), application specific integrated circuit(s) (ASIC(s)), programmable logic device(s) (PLD(s)) and/or field programmable logic device(s) (FPLD(s)). When reading any of the apparatus or system claims of this patent to cover a purely software and/or firmware implementation, at least one of the example controller238is/are hereby expressly defined to include a non-transitory computer readable storage device or storage disk such as a memory, a digital versatile disk (DVD), a compact disk (CD), a Blu-ray disk, etc. including the software and/or firmware. Further still, the example gate controller110ofFIG. 1may include one or more elements, processes and/or devices in addition to, or instead of, those illustrated inFIG. 2, and/or may include more than one of any or all of the illustrated elements, processes and devices. As used herein, the phrase “in communication,” including variations thereof, encompasses direct communication and/or indirect communication through one or more intermediary components, and does not require direct physical (e.g., wired) communication and/or constant communication, but rather additionally includes selective communication at periodic intervals, scheduled intervals, aperiodic intervals, and/or one-time events.

FIGS. 3 and 4are example signal plots corresponding to the example operations of the example voltage converter apparatus100.FIG. 3is an example first signal plot300corresponding to the current limit test mode operation of the example voltage converter apparatus100.FIG. 4is an example second signal plot400corresponding to the normal mode operation of the example voltage converter apparatus100.

InFIG. 3, the example first signal plot300depicts the voltage through the example voltage converter apparatus100operating in current limit test mode. For example, the first signal plot300embodies the voltage at nodes TEST_GATE246, GATE_BIG122, GATE_SMALL240, and the voltage at the SW node124when the example controller238outputs a logic one to the enable pin of the example CP236at the TM node248and when the example gate driver104does not output a high voltage at the PWM node132signal to the example MN0106(e.g., via the example switchable bias voltage circuit103). In the current limit test mode, the input voltage118is 5 volts. However, the input voltage118is not limited to 5 volts.

InFIG. 3, before time t1, the TEST_GATE node246is charged to approximately 4.8 volts. For example, before the CP236is enabled, the 5 volt input voltage118is dropped across the fourth body diode226of the MP2224, wherein the input voltage118forward biases the fourth body diode226and charges the TEST_GATE node246to equal one diode voltage below the input voltage118. In this manner, the example fourth body diode226drops 200 millivolts. At time t1, the example HSD_BIG202and HSD_SMALL204are turned off (e.g., the Vgs_big202and Vgs_small204before time t1are zero volts and below, indicating that voltage is not applied to HSD_BIG gate terminal and HSD_SMALL gate terminal).

InFIG. 3, at time t1, the example controller238outputs a logic high to the enable pin of the example CP236via TM node248. In response to enabling the CP236at time t1, the voltage at the GATE_SMALL node240begins to increase. For example, the CP236includes an output coupled to the GATE_SMALL node240and provides voltage to the GATE_SMALL node240when enabled. The GATE_SMALL node increases from zero volts to about 7 volts at time t1(e.g., it increases immediately). For example, due to inherent capacitance of the schematic ofFIG. 2, the output of the CP236does not bring the voltage at node240up to two times the input voltage118immediately.

InFIG. 3, the example HSD_SMALL204begins to turn on as the gate-to-source voltage begins to increase. For example, at time t1, the Vgs_small204rises from approximately −2 volts to 2 volts when the GATE_SMALL node240is being charged by the output of the CP236. When Vgs of the example HSD_SMALL204increases, the voltage across the transistor charges the SW node124. For example, at time t1, the voltage at the SW node124rises to the input voltage118potential. The voltage at the SW node124rises to the input voltage118potential because the input voltage118is applied to the HSD_SMALL drain terminal, and when the Vgs of HSD_SMALL increases above the threshold voltage, the voltage at the HSD_SMALL drain terminal drops across the transistor to the SW node124.

InFIG. 3, when the voltage at the SW node124increases to the input voltage118potential, the example first body diode114becomes forward biased and therefore provides voltage to the GATE_BIG node122and to the example MP3gate terminal. For example, the first signal plot300illustrates the voltage at GATE_BIG node122rising to approximately 4.5 volts (e.g., one diode voltage below the voltage at the SW node124) at time t1. In some examples, the voltage at the GATE_BIG node122does not meet the threshold voltage to turn on HSD_BIG202, therefore, at time t1, the voltage across the gate-to-source of HSD_BIG202begins to decrease because the voltage at SW node124has risen due to HSD_SMALL204turning on.

InFIG. 3, at time t1, when the example first body diode114becomes forward biased, the voltage at the TEST_GATE node246begins to increase with respect to the output of the example CP236. For example, the voltage at the MP3gate terminal is one threshold voltage and one diode voltage lower than the voltage at MP3source terminal (e.g., the voltage at the MP3gate terminal is equal to voltage at GATE_SMALL node240voltage). Therefore, MP3214is in linear mode and the MP3drain terminal is equal to the voltage at GATE_SMALL node240. The example third body diode220is forward biased and voltage at TEST_GATE node246is one diode voltage below the voltage at GATE_SMALL node240.

In current limit mode, when the TEST_GATE node246is charged to equal the output of the example CP236, the Vgs_BIG202remains low because the MP0228and MP1232are off. For example, the CP236is not charging GATE_BIG node122and thus, HSD_BIG202remains off.

InFIG. 3, at time t2, the voltage at the TEST_GATE node246and the GATE_SMALL node240have stepped up to equal approximately two times the input voltage118and the Vgs_BIG202is still below zero volts, indicating that the example HSD_SMALL202is conducting current and the HSD_BIG202is turned off. In this manner, the impedance of the high-side drive transistor has increased. A voltage difference between the input voltage118and the SW node124triggers the current limit circuitry to be tested at milliamps of current (e.g., to be delivered by the ATE system) as opposed to amps of current during normal operation, thereby enabling ATE testing of the current limit circuitry.

InFIG. 4, the example second signal plot400depicts the voltage through the example voltage converter apparatus100when operating in normal mode. For example, the second signal plot400embodies the voltage at nodes TEST_GATE246, GATE_BIG122, GATE_SMALL240, and SW node124when the example gate driver104receives a high PWM signal at the PWM node132. In the normal mode, the input voltage118is 5 volts. However, the input voltage118may be set to another voltage.

InFIG. 4, the example second signal plot400depicts the PWM signal at the PWM node132going high at time t1. For example, the PWM signal132rises from zero volts to approximately 2 volts at time t2. The PWM signal132is generated by a PWM generator and is provided to the example switchable bias voltage circuit103to out a voltage sufficient to turn on the example MN0106. The time between t1and t2depicts the propagation delay of the example gate driver104. For example, the time between t1and t2is the time it takes for the example switchable bias voltage circuit103to level shift the PWM signal132to a value which turns on the example MN0106. When the gate driver104receives a high PWM signal132, it takes time (e.g., 0.00017 microseconds) for the approximately 2 volt signal to be increased to a value that is large enough to turn on MN0106.

InFIG. 4, the example second signal plot400depicts the voltage at GATE_BIG node122increasing at time t2. For example, the switchable bias voltage circuit103injects an amplified signal into MN0gate terminal which turns on MN0106and further charges the GATE_BIG node122to equal the voltage at the node120. When the example GATE_BIG node122is charged, the Vgs_BIG202increases which allows the input voltage118to discharge through the HSD_BIG drain terminal to the HSD_BIG source terminal. The voltage at the SW node124begins to increase in response to the Vgs_BIG202increasing as the example HSD_BIG202turns on.

Concurrently, the voltage at the TEST_GATE node246biases to the input voltage118. For example, when the MN0106is turned on, MN1222turns on and conducts the input voltage to charge the TEST_GATE node246. In the example second signal plot400, the TEST_GATE node246follows the voltage at the input voltage118. The input voltage118varies with respect to inherent capacitances and inductances in the circuitry of the example voltage converter100.

InFIG. 4, the example second signal plot400depicts GATE_SMALL node240increasing at time t2when the GATE_BIG node122increases. For example, when the voltage at the GATE_BIG node122is increasing, the voltage is simultaneously applied to the MP0source terminal and the MN1gate terminal, thus turning on the example MP0228and further turning on the example MP1232. When MP0228and MP1232are turned on, MP0228and MP1232charge the voltage at node GATE_SMALL240to the voltage at node GATE_BIG122, creating a short between GATE_BIG122and GATE_SMALL240. In response to the voltage at the GATE_SMALL node240and GATE_BIG node122charging, the HSD_BIG202and HSD_SMALL204turn on and discharge the input voltage to the SW node124. For example, the voltage at the SW node124begins to increase at time t2with respect to the voltage at GATE_BIG node122and GATE_SMALL node240increasing.

InFIG. 4, the example second signal plot400depicts the voltage across Vgs_BIG202and Vgs_SMALL204increasing to a maximum potential at time t3. For example, at time t3, the voltage at each node122and240have increased to equal the voltage provided by the Cboot112, and the voltage provided by Cboot112fully turns on the example HSD_BIG202and HSD_SMALL204as indicated by the gate-to-source voltage (Vgs) signals. At time t3, the charging of all nodes (e.g., GATE_BIG node122and GATE_SMALL node240) is complete.

Turning toFIG. 5, a test mode implementation502and the example gate controller110are depicted in a silicon diagram to display the difference in total area size between the test mode implementation502and the example gate controller110. For example, the test mode implementation502includes a test mode switch and a charge pump and operates to perform similar functions as that of the example gate controller110. The test mode implementation502is greater in physical size than the example gate controller110, even though they perform the same functions. For example, the test mode implementation502is approximately 11,670 square micrometers and the example gate controller110is approximately 2,310 square micrometers.

FIG. 5illustrates an improvement of the example gate controller110over the test mode implementation502by minimizing the area size and number of components required to perform the functions of normal mode, one hundred percent mode, and current limit test mode. The reduction in die area consumption is due to a single charge pump (e.g., the charge pump236) and minimizes production costs. The example gate controller110is able to connect and/or disconnect GATE_BIG and GATE_SMALL with less components and more simplicity than the example test mode implementation502(e.g., because MP0228and MP1232are self-controlled and do not require special level shifting). Accordingly, the example gate controller110is implemented in a smaller die area than the example test mode implementation502. For example, the reduction in total number of components reduces the complexity of the gate controller110and likelihood that errors occur during building and operation. Thus, the decrease in the number of components and die area results in a decreased cost of implementing a circuit for normal, one hundred percent, and/or current limit test mode. The example gate controller110is approximately 9,360 square micrometers smaller than the test mode implementation502. By including less components and being smaller in physical size, the example gate controller110generates less electromagnetic interference (EMI), dissipates less heat, includes a faster response time, and is cost efficient. In other examples, the gate controller110is cost efficient because there are fewer components required, such as one dual purpose charge pump (e.g., in the gate controller110) versus two charge pumps (e.g., in the test mode implementation502).

FIG. 6illustrates a system layout600of the gate driver104which includes additional components and devices relative to the schematic illustrated inFIG. 2. The outlined gate controller110of the system layout600is depicted as a small portion of the high-side drive gate driver104which controls three modes of operation of the HSD transistor (e.g., HSD_BIG202and HSD_SMALL204) of the switching network102. The system layout600utilizes the plurality of electrical components to adjust the voltages provided to the HSD transistor of the switching network102. The system layout600may be implemented as a separate module than the switching network102or may be implemented on the same IC as the switching network102.

The machine readable instructions described herein may be stored in one or more of a compressed format, an encrypted format, a fragmented format, a packaged format, etc. Machine readable instructions as described herein may be stored as data (e.g., portions of instructions, code, representations of code, etc.) that may be utilized to create, manufacture, and/or produce machine executable instructions. For example, the machine readable instructions may be fragmented and stored on one or more storage devices and/or computing devices (e.g., servers). The machine readable instructions may require one or more of installation, modification, adaptation, updating, combining, supplementing, configuring, decryption, decompression, unpacking, distribution, reassignment, etc. in order to make them directly readable and/or executable by a computing device and/or other machine. For example, the machine readable instructions may be stored in multiple parts, which are individually compressed, encrypted, and stored on separate computing devices, wherein the parts when decrypted, decompressed, and combined form a set of executable instructions that implement a program such as that described herein. In another example, the machine readable instructions may be stored in a state in which they may be read by a computer, but require addition of a library (e.g., a dynamic link library (DLL)), a software development kit (SDK), an application programming interface (API), etc. in order to execute the instructions on a particular computing device or other device. In another example, the machine readable instructions may need to be configured (e.g., settings stored, data input, network addresses recorded, etc.) before the machine readable instructions and/or the corresponding program(s) can be executed in whole or in part. Thus, the disclosed machine readable instructions and/or corresponding program(s) are intended to encompass such machine readable instructions and/or program(s) regardless of the particular format or state of the machine readable instructions and/or program(s) when stored or otherwise at rest or in transit.

Turning toFIG. 7, the program700depicts an operation of the example gate controller110ofFIG. 2to operate in current limit test mode and one hundred percent mode. The program700ofFIG. 7begins at block702where the gate driver104determines the incoming PWM signal value at the at the PWM node132. For example, the gate driver104receives a signal from a controller, oscillator, signal generator, etc., which is a low-voltage signal (LOW) or a high-voltage signal (HIGH).

When the PWM signal at the PWM node132is HIGH (e.g., block702returns a YES), the MN2108and the pull_down transistor208are turned off (block704). For example, when the PWM signal at the PWM node132is HIGH, the second PWM signal at the second PWM node133goes LOW, such that the low-voltage signal turns off the MN2108and the pull_down transistor208. Additionally, in response to the HIGH PWM signal at the PWM node132, the MN0106turns on (e.g., the switchable bias voltage circuit103outputs a voltage sufficient to turn on the MN0106with the PWM signal is HIGH) (block706).

The HIGH PWM signal at the PWM node132is also applied to the switchable bias voltage (SBV) circuit111. The switchable bias voltage circuit111outputs switchable bias voltage to charge bootstrap node120(e.g., via the C_BOOT112) (block708). For example, a controller (e.g., a PWM generator) provides a high voltage signal to the gate driver104which initiates the switchable bias voltage circuit111to provide the bias voltage to the Cboot112. When the bootstrap node120is charged (block708), the MN0106charges GATE_BIG node122to go high (block710). For example, the MN0106is turned on causing the voltage at the GATE_BIG node122to be equal to or substantially similar to the voltage at the bootstrap node120.

When the GATE_BIG node122and GATE_SMALL node240are shorted (block714), HSD_BIG202and HSD_SMALL204are fully on (block716). For example, the voltage applied to the GATE_BIG node122turns on HSD_BIG202and the voltage applied to the GATE_SMALL node240turns on HSD_SMALL204. In this manner, GATE_BIG122is equal to GATE_SMALL240.

When HSD_BIG202and HSD_SMALL204are both fully on (block716), there is a low impedance connection between Vin118and SW node124(block718). During operation (e.g., HSD_BIG202and HSD_SMALL204are turned on), the C_BOOT112may begin to leak current. In this manner, the CP236is turned on (block720), and, because GATE_BIG122and GATE_SMALL240are shorted together by MP0228and MP1232, the CP236replenishes the lost charge on both GATE_BIG122and GATE_SMALL240(block714).

The CP236continues to refresh the voltage at GATE_BIG node122and GATE_SMALL node240when PWM signal at the PWM node132is HIGH (e.g., block722returns a YES). When the PWM signal at the PWM node132goes LOW (e.g., block722returns a NO), the MN2108and pull_down transistor208are turned on and the CP236and MN0106are turned off. For example, the second PWM signal at the second PWM node133goes HIGH and provides a turn-on voltage (e.g., a voltage value above Vth) to the MN2gate terminal and the pull_down transistor gate terminal.

When MN2108and pull_down transistor208are turned on, the HSD_BIG202and the HSD_SMALL204turn off (block726). For example, when the pull_down transistor208is turned on, the voltage at GATE_SMALL node240shorts to ground, thus removing the voltage from HSD_SMALL gate terminal and turning off HSD_SMALL204. Additionally, when the MN2108is turned on, it discharges the GATE_BIG node246to the SW node124. In this manner, the GATE_BIG node122shorts to SW node124, thereby reducing the gate voltage of the HSD_BIG202and HSD_BIG202is turned off. When MN2108is turned on, the voltage at MP0drain terminal is reduced to 0 volts, thus turning off MP0228and MP1232.

If the gate driver104receives a signal from a controller, oscillator, signal generator, etc., which is a LOW (e.g., block702returns a NO) then the program700ofFIG. 7begins at block730, where current limit test mode is determined to be activated. For example, when PWM signal at the PWM node132is LOW, the controller238(FIG. 2) may receive an initiating signal indicative to activate current limit test mode (e.g., block730returns a YES). In other examples, when PWM signal at the PWM node132is LOW, the controller238may not receive an initiating signal indicative to activate current limit test mode (e.g., block730returns a NO). In this manner, the example gate controller110continues to wait for a HIGH or LOW PWM signal at the PWM node132(block702).

When current limit test mode is determined to be activated (e.g., block730returns a YES), a controller, such as a PWM generator, oscillator, signal generator, etc., turns off the example MN2108and pull_down transistor208(block732). For example, the PWM signal133goes low and reduces the gate voltage of the MN2gate terminal and pull_down transistor gate terminal to 0 volts, thereby turning off the MN2108and the pull down transistor208.

When the MN2108and pull_down transistor208are turned off (block732), the controller238turns on CP236(block734). For example, the controller238outputs a high voltage signal (e.g., greater than zero volts) to the enable input of the example charge pump236via the TM node248. The output of the CP236charges the GATE_SMALL node240. For example, when the charge pump236is enabled, the charge pump236operates to double the input voltage118at the output (e.g., the intermediate node126).

When the CP236is charging, the voltage at the GATE_SMALL node240, the MP0228and MP1232remain off (block736). For example, MP0228and MP1232are, by default, turned off. Because the output of the CP236is coupled to the source terminal of MP3214, the potential at the source terminal of MP3214becomes higher than the potential at the gate terminal of the MP3214, thereby turning the MP3214on. Thus, the drain terminal of the MP3214receives the voltage at the GATE_SMALL node240and passes the voltage to the drain terminal of the eighth transistor218. Once the voltage at the GATE_SMALL node240surpasses Vin plus the threshold voltage of the eighth transistor218, the eighth transistor218turns on and passes the voltage at the GATE_SMALL node240to the TEST_GATE node246(e.g., the gates of the MP0228and the MP1232). Thus the voltage at the GATE_SMALL node240is applied to the gate of MP1232and to the source of MP1232. Because the Vgs of MP1232is zero volts, the MP1232is off. When MP0228and MP1232are both off, there is an open between GATE_SMALL node240and GATE_BIG node122(block738). For example, MP0228and MP1232are the transistors that inherently act as the switch between the gate terminals of HSD_BIG202and HSD_SMALL204(e.g., the GATE_BIG node122and GATE_SMALL node240), thus shorting or opening the connection between the two HSD transistors202,204.

When the CP236is charging GATE_SMALL node240, creating an open between GATE_BIG node122and GATE_SMALL node240, the HSD_SMALL204turns fully on and the HSD_BIG202is off (block740). For example, there is no voltage charging GATE_BIG node122, thus the voltage at HSD_BIG gate terminal is not great enough to turn the HSD_BIG202on. Because the output of the CP236is coupled to the source terminal of MP3214, the potential at the source terminal of MP3214becomes higher than the potential at the gate terminal of the MP3214, thereby turning the MP3214on. Thus, the drain terminal of the MP3214receives the voltage at the GATE_SMALL node240and passes the voltage to the drain terminal of the eighth transistor218. Once the voltage at the GATE_SMALL node240surpasses Vin plus the threshold voltage of the eighth transistor218, the eighth transistor218turns on and passes the voltage at the GATE_SMALL node240to the TEST_GATE node246(e.g., the gates of the MP0228and the MP1232). Thus the voltage at the GATE_SMALL node240is applied to the gate of MP1232and to the source of MP1232. Because the Vgs of MP1232is zero volts, the MP1232is off.

The example gate controller110operates to keep the HSD_BIG202off in current limit test mode because when HSD_BIG202is off, the impedance of the switching network102increases and the ATE hardware has the ability to test current limit circuitry without additional resources. For example, there is a high impedance connection between Vin118and SW node124(block742). The high impedance connection is a result of the HSD_BIG202being turned off. Thus, HSD_BIG202acts as an open circuit between Vin118and SW node124. Because HSD_SMALL204is on (e.g., creating a short circuit between Vin118and SW node124), current will flow though HSD_SMALL204(as opposed to both HSD_SMALL204and HSD_BIG202), thereby increasing the impedance between Vin118and the SW node124. Additionally, HSD_SMALL204is a smaller transistor (e.g., smaller in physical size relative to the HSD_BIG202) and a voltage difference between Vin118and SW node124which is sufficient to trigger the current limiting circuitry already occurs at milliamps of current (e.g., as opposed to amps of current when HSD_BIG202is turned on also). In this manner, current limiting circuitry can be tested with milliamps of current offered by ATE hardware.

The gate driver104may continue receiving an initiating signal indicative to active current limit test mode (e.g., block744returns a result YES) when operating in current limit test mode. If the gate driver104receives a signal indicative of inactive current limit test mode, the current limit test mode is to be no longer activated (e.g., block744returns a NO). In this manner, MN2108and the pull_down transistor208are turned on and the CP236is turned off (block746) to remove the gate voltage from MP3214and HSD_SMALL204, thus turning off MP3214and HSD_SMALL204(block748).

The program700ends when the HSD_BIG202and HSD_SMALL204are both off. The program700may be repeated when the gate driver104receives a HIGH PWM signal at the PWM node132or when the gate controller110receives a signal indicative of instructions to activate current limit test mode of the gate driver104.

From the foregoing, it will be appreciated that example methods, apparatus and articles of manufacture have been disclosed that reduce the number of components used to implement three modes of operation: normal mode, one hundred percent mode, and current limit test mode, for a switching network. The disclosed methods, apparatus and articles of manufacture increase the versatility of a switching network by implementing circuitry to perform multiple operations without requiring the need for a plurality of circuits to perform the multiple operations.