Emphasis signal generating circuit

An emphasis signal generating circuit includes: a branch circuit configured to split a signal into a plurality of paths; a delay circuit provided in one or more of the paths into which the signal has been split by the branch circuit, the delay circuit being configured to delay one or more signals; a phase compensation circuit provided in one or more of the paths into which the signal has been split by the branch circuit, the phase compensation circuit having such characteristics that a transmission intensity of a signal is low in a low frequency band and is high in a high frequency band; and an addition/subtraction circuit configured to perform addition and/or subtraction of signals from the plurality of paths and output a result.

CROSS-REFERENCE TO RELATED APPLICATION

This application is based upon and claims the benefit of priority of the prior Japanese Patent Application No. 2012-253724, filed on Nov. 19, 2012, the entire contents of which are incorporated herein by reference.

FIELD

The embodiments discussed herein are related to emphasis signal generating circuits configured to compensate for waveform degradation.

BACKGROUND

Recently, in the field of communications, with the increase in data transmission amount, the data rate has been increased in order to transmit a large amount of data in a single signal. High-speed data transmission has an issue in that degradation of data such as intersymbol interference is likely to occur in cables, boards, output devices, and so forth. Thus, taking the degradation of signals into consideration, an emphasis signal is often used in which a portion where intersymbol interference of the signal is likely to occur is enhanced.

A method (FIR method) for generating such an emphasis signal is disclosed. This method includes splitting a signal into multiple signals, generating a delay difference between the split signals, and adding or subtracting one of the split signals having the delay difference to or from the other signal (see, for example, Japanese Laid-open Patent Publication No. 2004-088693). The use of this method is being considered not only in a communication system that uses electrical signals but also in a communication system that uses light. The use of this method is also being considered in order to compensate for insufficient speeds of laser diodes (LDs) and surface emitting lasers (VCSELs), which are photoelectric conversion devices (see, for example, Japanese Laid-open Patent Publication No. 2012-044396).

However, there is a low degree of freedom in the shaping of the waveform of an emphasis signal generated through the FIR method. Thus, as compared to a case where an emphasis signal is not used, an eye opening improves, but frequency dependence of phase characteristics such as group delay increases, and thus jitter may disadvantageously increase. To resolve such an issue, increasing the number of split taps may be considered, as discussed in Japanese Laid-open Patent Publication No. 2012-044396. However, increasing the number of taps leads to other issues such as an increased circuit size and increased power consumption.

SUMMARY

According to an aspect of the embodiment, an emphasis signal generating circuit includes a branch circuit configured to split a signal into a plurality of paths; a delay circuit provided in one or more of the paths into which the signal has been split by the branch circuit, the delay circuit being configured to delay one or more signals; a phase compensation circuit provided in one or more of the paths into which the signal has been split by the branch circuit, the phase compensation circuit having such characteristics that a transmission intensity of a signal is low in a low frequency band and is high in a high frequency band; and an addition/subtraction circuit configured to perform addition and/or subtraction of signals from the plurality of paths and output a result.

DESCRIPTION OF EMBODIMENTS

Hereinafter, exemplary embodiments of the disclosed technique will be described in detail with reference to the accompanying drawings.FIG. 1illustrates an emphasis signal generating circuit according to a first embodiment.

An emphasis signal generating circuit100, for example, generates and outputs a drive signal (emphasis signal) for directly driving a light-emitting element (vertical cavity surface emitting laser (VCSEL))120serving as a drive target.

This emphasis signal generating circuit100includes a branch unit101, amplifiers102and103, a delay unit104, a phase compensation unit105, and an addition/subtraction unit106. The branch unit101splits an input signal (Data). In the example illustrated inFIG. 1, the branch unit101is configured to split the input signal into two paths (2-tap).

One output (path) of the branch unit101leads to the amplifier102, and an output of the amplifier102is outputted to the addition/subtraction unit106. The other output (path) of the branch unit101leads to the delay unit104, and the input signal is delayed by a predetermined delay amount τ in the delay unit104. An output of the delay unit104is amplified by the amplifier103, and the resulting signal is subjected to phase compensation by the phase compensation unit105and is outputted to the addition/subtraction unit106.

The addition/subtraction unit106includes a subtraction unit106aand an amplifier106b. The addition/subtraction unit106of the first embodiment has a subtraction function. The subtraction unit106asubtracts one of the split input signals from the other. Specifically, the subtraction unit106asubtracts an input signal (Data 2) that has been delayed by the delay unit104from an input signal (Data 1) that has not been delayed (Data 1−Data 2). Here, adjusting a predetermined addition ratio for each of the two signals through the respective paths allows the signal intensity to be adjusted and the waveform to be shaped. The amplifier106boutputs an amplified output signal (Data out). This output signal (Data out) is outputted as an emphasis signal whose rise and fall have been enhanced. This emphasis signal serves as a drive signal for the light-emitting element120.

In the configuration illustrated inFIG. 1, the output of the phase compensation unit105is subtracted in the addition/subtraction unit106. Therefore, a path leading from the output of the phase compensation unit105to the addition/subtraction unit106is preferably a linear circuit or a linear amplification circuit. Alternatively, a non-linear circuit or a limiter circuit may also bring about a sufficient effect, which will be described later. The order in which the amplifier (buffer)103and the phase compensation unit105are connected to the delay unit104in the circuit illustrated inFIG. 1may be switched as long as the circuit can retain the waveform of a phase compensation (equalizing) signal.

FIG. 2illustrates a circuit example of the phase compensation unit. The phase compensation unit105includes a circuit formed by a filter circuit200, which is a parallel circuit including a resistor201and a capacitor202, and a resistor203. The filter circuit200is directly connected in a signal path (path). One end of the resister203is connected to the aforementioned circuit and the other end thereof is grounded. Frequency characteristics Vout of the phase compensation unit105, for example, are expressed through Expression (1) below.

FIGS.3AA and3AB illustrate frequency characteristics of the phase compensation unit, and FIGS.3BA and3BB illustrate simulation results of frequency characteristics of the phase compensation unit. In FIGS.3AA and3BA, the horizontal axis represents frequency, and the vertical axis represents signal intensity. In FIGS.3AB and3BB, the horizontal axis represents frequency, and the vertical axis represents phase.

As illustrated in FIG.3AA, the phase compensation unit105has, in terms of the intensity, “zero” at a low frequency and “maximum” at a high frequency. In addition, as illustrated in FIG.3AB, the phase advances at a frequency around “zero”. The phase advances the most at an intermediate position between “zero” and “maximum” and returns around “maximum”. In this way, among the frequencies of an input signal, the phase compensation unit105has a low transmission intensity of a signal in a low frequency band and a high transmission intensity of a signal in a high frequency band.

Expression (1) above corresponds to the transmission characteristics. However, the embodiment is not limited to Expression (1) above, as long as a given configuration has the following characteristics. That is, “zero” and “maximum” appear in this order as the frequency increases, the phase advances around “zero” and returns around “maximum”, and the transmission intensity of a signal is low in a low frequency band and is high in a high frequency band. The positions of “zero” and “maximum” are set in a lower frequency band than a 3 dB bandwidth of a drive device (VCSEL120) to be driven through an output. Through this configuration, an emphasis signal that has “zero” and “maximum” in the band of the drive device and that is suitable for the drive device may be outputted.

FIG. 4illustrates another circuit example of the phase compensation unit.FIG. 4illustrates a circuit example of a continuous time linear equalizer (CTLE) serving as the phase compensation unit105having an amplification function. The circuit of the CTLE is not limited to the one illustrated inFIG. 4, and any existing circuit may be used instead.

In the exemplary circuit illustrated inFIG. 4, input terminals IN and IP are connected respectively to gates of FETs401and402, and drains of the FETs401and402are connected to a power supply terminal405, to which a power supply voltage VDDis to be applied, through respective resistors403and404. The drains of the FETs401and402are also connected to output terminals OUTP and OUTN, respectively. Sources of the FETs401and402are connected respectively to current sources407and408that are provided between the pair of FETs401and402and a power supply terminal406, to which a power supply voltage VSSis to be applied. A filter circuit409that includes a resistor409aand a capacitor409bis provided between the sources of the FETs401and402.

When the impedance of the filter circuit409is denoted by Z, the CTLE circuit illustrated inFIG. 4has an additive gain of (gmRA)/(1+gmZ) and has characteristics similar to those of the circuit illustrated inFIG. 2.

FIG. 5illustrates signal waveforms in respective units illustrated inFIG. 1in the first embodiment. On the basis of the characteristics of the phase compensation unit105illustrated in FIGS.3AA,3AB,3BA, and3BB, the output of Data 2 may be generated as a signal that has the delay amount τ relative to the input signal, whose intensity increases in a high speed band (high frequency band)501and decreases in a low speed band (low frequency band)502. In this respect, the stated signal differs from an existing signal that is merely delayed by the delay amount τ relative to an input signal. Using this Data 2 having the delay amount τ makes it possible to obtain a drive signal (emphasis signal) whose waveform has been shaped as desired as an output signal (Data out=Data 1−Data 2).

FIGS. 6A and 6Billustrate simulation results of frequency characteristics of an output signal in the first embodiment.FIG. 6Aillustrates intensity characteristics of an output signal (Data out) illustrated inFIG. 1, andFIG. 6Billustrates group delay characteristics thereof. According to the first embodiment, the intensity characteristics illustrated inFIG. 6Amake it possible to increase emphasis in a high frequency band601. In addition, the group delay characteristics illustrated inFIG. 6Bmay generate a recess in the characteristics of a low frequency band602and enable improvement in phase characteristics through group delay compensation.

FIGS. 7A and 7Billustrate simulation results of frequency characteristics of a drive signal for a light-emitting element in the first embodiment.FIG. 7Aillustrates intensity characteristics of a light emission state (VCSEL out) of the light-emitting element (VCSEL)120illustrated inFIG. 1, andFIG. 7Billustrates group delay characteristics thereof. According to the first embodiment, the intensity characteristics illustrated inFIG. 7Aenable a characteristic line701that is more planar over the entire frequencies, and thus an eye opening may be made wider. In addition, the group delay characteristics illustrated inFIG. 7Balso enable a characteristic line702that is more planar over the entire frequencies, and thus jitter may be reduced.

FIGS. 8A and 8Billustrate simulation results of time waveforms (eye openings) of a signal in the first embodiment. A waveform in the first embodiment (2-tap) is illustrated in the right half of each ofFIGS. 8A and 8B, and a waveform of an existing 2-tap circuit is illustrated in the left half of each ofFIGS. 8A and 8B.

When the output signals (Data out) illustrated inFIG. 8Aare compared, the rise and the fall of the signals are both clearer in the first embodiment, and thus the eye opening may be made wider compared to that in the existing configuration. When the light emission states (VCSEL out) illustrated inFIG. 8Bare compared, the eye opening may be made wider and the cross point is clearer in the first embodiment than in the existing configuration, and thus jitter may be reduced in the first embodiment.

FIGS. 9A and 9Billustrate simulation results of time waveforms (eye openings) of a signal during a limiter operation in the first embodiment.FIGS. 9A and 9Billustrate waveforms in the case of a non-linear circuit or in the case where a limiter operation occurs. Although the output of the phase compensation unit105provided in one of the taps and the addition/subtraction unit106are preferably linear circuits in order to retain the waveform as stated earlier, in reality, a non-linear circuit is employed or a limiter operation occurs. However, as illustrated inFIGS. 9A and 9B, even if a limiter operation occurs (portion901inFIG. 9B), an eye opening may be made wider and jitter may be reduced as can be seen from the waveform of the first embodiment (right half ofFIG. 9B).

FIG. 10Aillustrates an exemplary circuit configuration of the addition/subtraction unit. In the addition/subtraction unit106, input terminals IN1N and IN1P are connected respectively to gates of FETs1001and1002, and drains of the FETs1001and1002are connected to a power supply terminal1005, to which a power supply voltage VDDis to be applied, through respective resistors1003and1004. The drains of the FETs1001and1002are also connected to output terminals OUTP and OUTN, respectively. Sources of the FETs1001and1002are connected to a current source1007that is provided between the pair of FETs1001and1002and a power supply terminal1006, to which a power supply voltage VSSis to be applied (grounded source).

In addition, input terminals IN2N and IN2P are connected respectively to gates of FETs1011and1012, and drains of the FETs1011and1012are connected to the power supply terminal1005, to which the power supply voltage VDDis to be applied, through the respective resistors1003and1004. The drains of the FETs1011and1012are also connected to the output terminals OUTP and OUTN, respectively. Sources of the FETs1011and1012are connected respectively to current sources1013and1014that are provided respectively between the FET1011and the power supply terminal1006, to which the power supply voltage VSSis to be applied, and between the FET1012and the power supply terminal1006.

FIGS.10BA to10BD are waveform charts illustrating an influence of the addition/subtraction unit on an emphasis shaping component. The emphasis additive gain of the circuit of the addition/subtraction unit106described above is expressed through (gmRA)/(1+gmRB). If an ordinary addition circuit having the above-described configuration illustrated inFIG. 10Ais used, even if a waveform is shaped by the phase compensation unit105, the shaping component is degraded due to non-linearity of the addition circuit or a limiter operation, and thus an appropriate emphasis signal may not be obtained (portion1020in FIG.10BC).

The gain of the addition circuit (subtraction circuit) depends on the magnitudes of the joint impedance RBof sources of a differential circuit and of the conductance gm of a transistor. Accordingly, as illustrated inFIG. 10A, a resistor1015is provided between the sources of the FETs1011and1012in the first embodiment. This configuration enables adjustment of the gain and an improvement in the linearity of the output signal. Then, as illustrated in FIG.10BD, the shaping component of the waveform by the phase compensation unit105may be retained (portion1021in FIG.10BD). Here, in the case of a bipolar transistor, the resistor1015may be provided between emitters of grounded emitter transistors.

According to the first embodiment described thus far, a phase compensation unit is provided in one or more of the paths of the split taps of the input signal. With this phase compensation unit, “zero” appears at a low frequency, and “maximum” appears at a high frequency. Further, the phase advances around “zero” and returns around “maximum”. In addition, the phase compensation unit, among the frequencies of an input signal, has a low transmission intensity of a signal in a low frequency band and a high transmission intensity of a signal in a high frequency band. Such a phase compensation unit makes it possible to improve a waveform shaping function within a tap and, in particular, enables not only frequency intensity characteristics compensation but also phase compensation. Accordingly, the waveform of an emphasis signal or an LD output signal may be improved even with the same number of taps as the existing configuration.

A second embodiment has a configuration in which the disposition of the phase compensation unit105described in the first embodiment has been changed.FIGS. 11A,11B, and11C each illustrate an emphasis signal generating circuit according to the second embodiment. As illustrated inFIG. 11A, the phase compensation unit105may be provided in one of the split paths (i.e., in a tap that does not include the delay unit104). In this case, the addition unit106aof the addition/subtraction unit106adds the data pieces from the two taps (Data 1+Data 2). Alternatively, as illustrated inFIG. 11B, the phase compensation unit105may be provided in each of the two split taps.

FIG. 11Cillustrates a three-tap configuration in which the branch unit101splits an input signal into three paths. The phase compensation unit105is then provided in each of the three taps. A delay unit 2 (1104) configured to further delay a signal that has been delayed by a delay unit 1 (104) and an amplifier1103are disposed in a path of a third tap. The output of the phase compensation unit105in the third tap is inputted to the addition/subtraction unit106to be added therein. Although the addition/subtraction unit106has performed subtraction in the first embodiment, as illustrated inFIG. 11C, depending on the combination of the phase compensation units105, calculation in the addition/subtraction unit106is not limited to subtraction but may include addition.

According to the second embodiment described thus far, the phase compensation unit may be disposed in any of the split taps or may be disposed in all of the taps. Then, the waveform of an emphasis signal may be shaped by the phase compensation units disposed in the respective taps.

In a third embodiment, other modifications of the phase compensation unit will be described.FIGS. 12A and 12Billustrate the other exemplary circuit configurations of the phase compensation unit according to the third embodiment. The phase compensation unit105illustrated inFIG. 12Aincludes an operational amplifier1201. A parallel circuit (filter circuit)1202including the resistor201and the capacitor202has a similar configuration to that illustrated inFIG. 2. An output of the filter circuit1202is inputted to a non-inverting input (+) of the operational amplifier1201, and the inverting input (−) of the operational amplifier1201is grounded. The output of the operational amplifier1201is fed back to the non-inverting input through the resistor203. The output of the operational amplifier1201is inverted and outputted by an inverting element1203.

In the phase compensation unit105illustrated inFIG. 12B, an input signal is inputted to a non-inverting input (+) of an operational amplifier1204, and an inverting input (−) of the operational amplifier1204is grounded through a parallel circuit (filter circuit)1202including the resistor201and the capacitor202and a series circuit of a resistor1205. An output of the operational amplifier1204is fed back to the inverting input through the resistor203.

Each of these phase compensation units of the third embodiment is also a circuit that has a low transmission intensity in a low frequency band and a high transmission intensity in a high frequency band and has “maximum” at a point where the intensities of the low frequency band and the high frequency band change. The circuit configuration of the phase compensation unit is not limited to those described above, and any circuit configuration that has a similar function to those described above in terms of the intensity characteristics and the phase characteristics may be employed.

FIG. 13illustrates a configuration example of an addition/subtraction unit having a phase compensation function according to a fourth embodiment. The configuration illustrated inFIG. 13is similar to the configuration of the addition/subtraction unit106illustrated inFIG. 10A. A difference, however, lies in that a parallel circuit (filter circuit)1301including a resistor1301aand a capacitor1301bis additionally provided between the sources of the FETs1011and1012. According to the addition/subtraction unit106having such a configuration, the filter circuit1301that is similar to the one used in the phase compensation unit105is provided between the common sources of the FETs1011and1012.

This configuration makes it possible to realize the addition/subtraction unit106having the function of the phase compensation unit105, which allows the addition/subtraction and the phase compensation to be carried out simultaneously. Alternatively, as another configuration example, a filter circuit that is similar to the one described above may be provided in the delay unit104in a similar manner as described above, which makes it possible to realize the delay unit104having the function of the phase compensation unit105. Here, in the case of a bipolar transistor, the filter circuit1301may be provided between emitters of grounded emitter transistors.

According to the embodiments described thus far, by providing a phase compensation unit in a tap obtained by splitting an input signal, the phase characteristics may be better compensated even with the same number of taps as the existing configuration, and a good emphasis signal and a good drive signal for a light-emitting element may be obtained. Here, the existing configuration uses three or more taps in order to obtain emphasis signal characteristics equivalent to those of the embodiments. However, according to the embodiments, the number of taps may be reduced in comparison with the existing configuration, which allows the circuit size and the power consumption to be reduced.

Although an example in which an FET is used in a phase compensation unit or an addition/subtraction unit has been illustrated in the embodiments described above, the embodiments are not limited to the use of FETs, and a configuration in which another semiconductor device such as a bipolar transistor is used may yield similar effects as well.