Integrating display controller into low power processor

In one embodiment, a system comprises a memory; a memory interface coupled to the memory; a processor unit coupled to the memory interface, a second interface coupled to the processor unit, and a graphics processing unit. The processor unit comprises at least one processor core and a display controller configured to couple to a display. The graphics processing unit is configured to render data into a frame buffer representing an image to be displayed on the display. The processor unit is configured to deactivate the second interface if the graphics processing unit is not rendering, and the display controller is configured to read the frame buffer data for display even if the second interface is deactivated.

BACKGROUND

1. Field of the Invention

This invention is related to the field of processors and computer systems including processors, and to managing power consumption in such systems.

2. Description of the Related Art

Various types of mobile computing devices have become very popular, permitting users to do useful work at various locations remote from their fixed computing stations. Mobile computing devices include portable computers (also referred to as laptops), personal digital assistants (PDAs) such as those based on the Palm operating system (e.g. the Palm Pilot family of devices) as well as those based on the Windows CE platform, mobile communications devices such as the Blackberry line of products from Research in Motion, which provide wireless email access, and various wireless telephony devices such as cell phones, combinations of PDAs or Blackberries and cell phones, etc.

A common issue for all mobile computing devices is battery life. The longer the battery (or a given charge of the battery) can be made to last, the more satisfied the user is with the product and thus the more likely the user is to purchase their next product from the same manufacturer. Many mobile computing devices, especially laptops, may also be connected to an external power source (e.g. an A/C wall outlet) in addition to having an internal battery power source. When using an external power source, the battery is not used (and may in fact be charged from the external power source). Thus, higher power consumption may be permissible when using the external power source. Numerous power saving features have been implemented in various computing devices (e.g. the Advanced Configuration and Power Interface (ACPI) is frequently used in laptops). However, striving for improved battery life when the mobile computing device is not connected to an external power source is still an area of high interest and continuing innovation.

SUMMARY

In one embodiment, a system comprises a memory; a memory interface coupled to the memory; a processor unit coupled to the memory interface, a second interface coupled to the processor unit, and a graphics processing unit. The processor unit comprises at least one processor core and a display controller configured to couple to a display. The graphics processing unit is configured to render data into a frame buffer representing an image to be displayed on the display. The processor unit is configured to deactivate the second interface if the graphics processing unit is not rendering, and the display controller is configured to read the frame buffer data for display even if the second interface is deactivated.

In an embodiment, a processor unit comprises at least one processor core, a display controller configured to couple to a display, and a bridge coupled to the processor core and the display controller. The bridge is further configured to couple to a second interface to communicate with a graphics processing unit. The graphics processing unit is configured to render data into a frame buffer representing an image to be displayed on the display. The bridge unit can be configured to deactivate the second interface if the graphics processing unit is not rendering, and wherein the display controller is configured to read the frame buffer data for display even if the second interface is deactivated.

In another embodiment, an integrated circuit comprises at least one processor core and a display controller configured to couple to a display. The display controller is configured to read data from a frame buffer, the data representing an image. Additionally, the display controller is configured to cause the display to display the image. The integrated circuit excludes a graphics processing unit that renders the image into the frame buffer.

DETAILED DESCRIPTION OF EMBODIMENTS

Turning now toFIG. 1, a block diagram of a portion of a computer system10is shown. In the illustrated embodiment, the system10includes a system memory12, a processor unit14, a north bridge16, a liquid crystal display (LCD) display18, an optional other display20, and an input/output (I/O) hub22. The processor unit14includes at least one processor core (e.g. processor core24A and optional processor core24B in the illustrated embodiment), a bridge26, and a display controller28. The north bridge16includes a graphics processing unit30and an optional display controller32. The processor unit14(and more particularly, the bridge26in the illustrated embodiment) is coupled to a memory interface to communicate with the system memory12. The display controller28is coupled to an interface (e.g. the low voltage differential signalling (LVDS) interface in the illustrated embodiment) to the display18, and is further coupled to the bridge26. The bridge26is further coupled to the processor cores24A-24B, and to a bridge interface to the north bridge16. The display controller32is coupled to an interface (e.g. the high definition multimedia interface (HDMI)) to the display20. The north bridge16is further coupled to a peripheral interface to the I/O hub22.

The computer system10may be part of a mobile computing device (e.g. a laptop, PDA, etc.). The display18may be the display that is integrated into the mobile computing device. For example, the mobile computing device may comprise a housing into which the display and the computer system10are integrated. In a laptop, the display may be included in the “lid” that can be opened to expose the keyboard. In PDAs, the display is often on the front of the mobile computing device.

The display18may comprise a relatively low power display, in some embodiments, designed to optimize battery life. For example, as illustrated inFIG. 1, the display18may be an LCD. Other embodiments may have a thin film transistor (TFT) display, or any other display that may be integrated into the device. On the other hand, the display20may be a relatively high power display such as a cathode ray tube (CRT) display, an LCD or TFT display, or a plasma display or other display in a standalone unit separate from the laptop and connected via an external connector such as a video out, TV out, or dock connection. The display20may generally be used when the mobile computing device is provided with external power, and thus battery life may not be a concern.

The GPU30and the display controller28(and the display controller32, if included) may cooperate to provide for the display of objects generated by various software (e.g. software executing on the processor cores24A-24B) on the display18(and the display20). Generally, the software may create data structures in the system memory12representing the objects to be displayed. The data structures are illustrated at reference numeral34. The GPU30may read the data structures and process them, generating pixel data representing each pixel on the display. Processing the data structures representing objects to be displayed and generating image data (e.g. pixel data) is referred to as rendering the image. The pixel data may describe, e.g., the color of the corresponding pixel on the display. The GPU30may write the pixel data to a frame buffer (reference numeral36) in the system memory12. Thus, the frame buffer36may comprise data representing the image to be displayed on the display18or20. The display controllers28or32may read the frame buffer36from the system memory12, and may generate controls to the displays18or20to display the image described in the frame buffer36. In the embodiment ofFIG. 1, the GPU30accesses memory by generating read/write commands which are transmitted over the bridge interface. The commands are received by the bridge26, which routes corresponding commands to the system memory12. Similarly, the display controller32may generate read commands to read the frame buffer36, which may be transmitted on the bridge interface to the bridge26, which may route corresponding commands to the system memory12. On the other hand, the display controller28may read the frame buffer36by generating commands for the system memory12, which are conveyed by the bridge26.

The displays18or20may generally not include memory to store the image being displayed, and thus are refreshed repeatedly to continue displaying the image, even if the image is static (i.e. not changing). The rate at which the image is re-transmitted for display is referred to as the refresh rate. The refresh rate may be user selectable and may vary, e.g., from 60-120 Hertz (Hz) in typical displays. Thus, the display controller28or32may read the frame buffer data repeatedly to retransmit to the displays18or20(e.g. 60-120 times per second for typical displays).

In many cases, the GPU30is idle a relatively large percentage of the time that the system10is in operation (e.g. on the order of 90%). That is, the image being displayed is static for a large percentage of the time, and the GPU30is thus not rendering during such times. However, the display controllers28and32are not idle during these times, as they refresh the displays18and20with the image.

Since the display18is part of the mobile computing device in the present embodiment, the display18may be used during times that the device is operating on battery power. Accordingly, by integrated the display controller28into the processor unit14, the refresh of the display18by the display controller28may be performed over the memory interface and the LVDS interface. Particularly, the refresh of the display18may be performed without any transactions on the bridge interface to the north bridge16.

Thus, during times that rendering is not occurring, the system10may deactivate the bridge interface. More specifically, the processor unit14(e.g. the bridge26) may deactivate the bridge interface. Power that would otherwise be expended in operating the bridge interface may be conserved, which may extend battery life in some embodiments. The manner in which the interface is deactivated may vary from embodiment to embodiment, depending on the nature of the interface itself. Generally, deactivating the interface may refer to stopping transmission on the interface.

In one embodiment, the bridge interface may be compatible with the HypertTransport™ (HT) interface. The HT interface is a high speed, clock forwarded interface. Accordingly, even when no transactions are being communicated over the HT interface, idle data patterns are transmitted and the clock continues to run. Deactivating the HT interface may comprise performing a disconnect (which provides an orderly shutdown of the HT interface on both ends of the interface). After disconnecting, the clock for the HT interface may be stopped. Subsequently, the interface may be reconnected to perform communications between the processor unit14and the north bridge16.

Other interfaces may be deactivated for the purpose of reducing power consumption in other ways. For example, a shared bus interface may be deactivated simply by gating the clock that corresponds to the bus interface. Alternatively, the signals of an interface may be driven to inactive (deasserted) levels. Any mechanism for ceasing transmission on the interface may be used.

Furthermore, the GPU30may be a high performance processor which may be implemented in a relatively large number of transistors (e.g. rivaling the order of magnitude of transistor counts in a processor core24A-24B). Accordingly, by having the GPU30remain in the north bridge16and integrating the display controller28into the processor unit14, power conservation may be achieved while still permitting freedom for the GPU30to evolve unconstrained by power/area constraints in the processor unit14and without constraining the processor cores24A-24B as well, in some embodiments. Still further, various embodiments of the system10may use different GPUs30with the same processor unit14. In other embodiments, the GPU30may be fixed function logic, a programmable logic device, or a combination of one or both and the processor described above.

If the display controller32is in use (and thus there is a display20coupled to the system10), the bridge interface may not be deactivated because the display controller32would not be able to access the system memory12. However, if the display controller32is in use, typically the system10is being supplied from an external supply and thus battery life may not be an issue. Examples of times that the display controller32may be in use include a laptop connected to a docking station, or a laptop being used in presentation mode where a projector is connected to the VGA output of the laptop.

The data structures34may be defined in any desired fashion, and may vary from embodiment to embodiment of the GPU30. The data structures may in some way include a display list of the objects to be displayed. For example, in some embodiments, the display list may comprise triangles to be drawn into the image. The depth of each object in the image may also be specified, so that the GPU30may determine, when objects overlap, which objects are in front of other objects (e.g. zBuff inFIG. 1). Furthermore, the data structures may specify textures to be applied to the objects in various texture maps. Many other fashions for describing the objects may be used, including varying levels of complexity and any desired format, in various embodiments.

The north bridge16may further be coupled to an I/O hub22or I/O device(s) via a peripheral interface. In one embodiment, the peripheral interface may also be an HT interface. Alternatively, the peripheral interface may be any other communication interface (e.g. peripheral component interconnect (PCI), in its various forms, universal serial bus (USB), IEEE 1394 “Firewire”, serial or parallel interfaces, etc. The I/O hub22may connect to I/O devices, or may bridge to another desired peripheral interface, to which I/O devices may be coupled. Alternatively, one or more I/O devices may couple to the north bridge16via the peripheral interface.

Accordingly, in the embodiment ofFIG. 1, the bridge interface may be reactivated if either there is rendering for the GPU30to perform, or if there is I/O activity on the peripheral interface or directed to the peripheral interface. The peripheral interface may be deactivated as well if the bridge interface is deactivated, in some embodiments.

The processor cores24A-24B may implement any desired instruction set architecture. For example, the processor cores24A-24B may implement the x86 instruction set architecture (also referred to as IA-32). The processor cores24A-24B may implement the AMD64™ instruction set architecture. Other exemplary instruction set architectures include the PowerPC™ instruction set architecture, the ARM™ instruction set architecture, the SPARC™ instruction set architecture, the MIPS™ instruction set architecture, etc. In some embodiments, only one processor core may be included. In other embodiments, two or more processor cores may be include in a multi-core configuration.

The bridge26may generally be responsible for communicating between the bridge interface, the display controller28, the processor cores24A-24B, and the system memory12. Thus, the bridge26may incorporate memory controller functionality to control the system memory12. The memory interface may comprise any standard memory interface (e.g. the system memory12may comprise synchronous dynamic random access memory (SDRAM) modules and the memory interface may be an SDRAM interface). Any type of SDRAM memory may be used (e.g. single data rate, double data rate (DDR), DDR2, etc.). Generally, any type of semiconductor memory may be used as the system memory12, in various embodiments. For example, RAMBUS DRAM (RDRAM), static RAM, etc. may be used.

In the illustrated embodiment, the system memory12is a unified memory configuration, in which the system memory12is shared by both the graphics units (e.g. the data structures34and the frame buffer36) and by the processor cores24A-24B. For example, the processor code38executed by the processor cores24A-24B and the data40accessed/updated by the processor cores24A-24B in response to executing the code38are stored in the system memory12as well. In some embodiments, integrating the display controller28into the processor unit14and deactivating the bridge interface to conserve power may eliminate or substantially reduce the battery life cost that may be experienced in a unified memory design and still retain the connection of the system memory12to the processor unit14, which has performance advantages for the processor cores24A-24B.

The processor unit14may generally comprise any apparatus incorporating at least one processor core and other components. In one embodiment, the processor unit14may comprise a single integrated circuit chip. In other embodiments, the processor unit14may comprise two or more chips in a multi-chip module, two or more discrete integrated circuits coupled to a circuit board, etc. Similarly, the north bridge16may comprise a bridge unit, which may be a single integrated circuit chip, two or more chips in a multi-chip module, two or more discrete integrated circuits coupled to a circuit board, etc.

FIG. 2is a block diagram of various components of the system10shown inFIG. 1, illustrating certain data flow between the components for one embodiment. The processor cores24A-24B may read the processor code38from the system memory12(arrow50), and may read and write the data40(arrow52). Additionally, the processor cores24A-24B may read and write the data structure34to add/delete objects to be displayed. The GPU30may read the data structures34(arrow54) and may write the generated image data to the frame buffer36(arrow56). The display controllers28and32may read the frame buffer36(arrows58and60, respectively).

AsFIG. 2illustrates, if the display controller32is inactive (which may be the case for the mobile computing system being used on battery supply) and if the GPU30is not rendering (as is the case for a large percentage of the time), the interface to the north bridge16may be deactivated while still refreshing the local display via the display controller28.

FIG. 3illustrates a state machine including various states that may be implemented with regard to the system shown inFIG. 1, for one embodiment. The states are arranged vertically, with generally increasing power consumption occurring in the upward direction as shown inFIG. 3(arrow76). That is, power consumption in the peripheral interface active state70may be higher than the power consumption in the bridge interface active state72, which may be higher than the power consumption in the bridge interface inactive state74. In some embodiments, if the system10is receiving power from an external source, the state machine may remain in the peripheral interface active state70.

In the peripheral interface active state70, both the peripheral interface and the bridge interface are active. Any I/O activity and/or rendering activity may occur in the peripheral interface active state70. If there is no current I/O activity (except for graphics activity—arc78), the state machine may transition to the bridge interface active state72, and the system may deactivate the peripheral interface. Resumption of I/O activity (arc80) may cause a transition back to the peripheral interface active state70and reactivation of the peripheral interface.

In the bridge interface active state72, if the HDMI display is inactive (that is, display controller32is inactive) and no rendering is being performed by the GPU30, the system may transition to the bridge interface inactive state74and the system may deactivate the bridge interface (arc82). The display controller32may include an enable bit or other enable controls indicating whether or not the display controller32is active. The system may detect that rendering in not being performed if the GPU30is idle.

In the bridge interface inactive state74, if rendering is being performed or the HDMI display (display controller32) is activated, the system may reactivate the bridge interface and transition to the bridge interface activate state72(arc84). The system may detect that rendering is to be performed if the data structure34is changed, if a write to a given register in the bridge26is detected, if a command that signals the GPU30to commence rendering is detected, etc. If other (non-graphics) I/O activity is detected (arc86), both interfaces may be reactivated and the state machine may transition to the peripheral interface activate state70.

Other embodiments of the state machine may exclude the peripheral interface active state70. In some embodiments, the state machine shown inFIG. 3may be included in a larger power management scheme (e.g. ACPI). In one embodiment, for example, the bridge interface inactive state74may correspond to an Idle state in ACPI.

Turning now toFIG. 4, a block diagram of another embodiment of the computer system10is shown. The computer system10inFIG. 4may be similar to the computer system10shown inFIG. 1, and like elements are numbered in the same way inFIG. 4as compared toFIG. 1. In the embodiment ofFIG. 4, the processor unit14also includes a memory90which stores the frame buffer36(instead of the system memory12). In the embodiment ofFIG. 4, even the memory interface may be deactivated and the display controller28may refresh the display18from the memory90(e.g. in the state74shown inFIG. 3). Still more power consumption savings may be realized in some embodiments.

The memory90may comprise any type of semiconductor memory. For example, the memory90may comprise embedded DRAM, if the processor unit14is a single integrated circuit, or local DRAM in the processor unit14in other embodiments. The memory90may also be SRAM.

In one embodiment, the memory90may be mapped into the same address space as the system memory12. In such an embodiment, the memory90may automatically be written when the GPU30generates writes to the addresses allocated to the frame buffer36. In other embodiments, the memory90may be operated as a cache. The frame buffer36may also be stored in the system memory12, and the memory90may be maintained coherent with the system memory12or may be periodically reloaded from the system memory12if rendering is actively being performed.