Circuit and method for determining integrated circuit propagation delay

A circuit and method is provided for determining the delay of an integrated circuit common associated with chip-to-chip variations in the manufacturing process, changes in operating voltage, and fluctuations in temperature. A clock signal is inverted, thus generating an inverted clock signal which is then delayed multiple times, resulting in several delayed versions of the inverted clock signal, with each version being delayed a different length of time. The logical state of each delayed version of the inverted clock signal is then stored. That stored logical state provides an indication as to the magnitude of the delay of the integrated circuit which may then be used to tune critical signals of the integrated circuit to avoid timing problems resulting from variations in IC propagation delay.

BACKGROUND OF THE INVENTION

Of all the tasks an integrated circuit (IC) designer faces, resolving timing violations, especially in large, complex IC designs, is one of the most onerous. This task is made difficult, in part, by the fact that IC logic gate delays can vary up to three times in response to changes in power supply voltage, operating temperature, and variations in the IC manufacturing process. Of these three variables, variations in process tend to dominate over changes in voltage and temperature, primarily because changes in the IC process for a particular IC remain constant once that IC has been manufactured. Voltage and temperature, on the other hand are changeable and, to a certain degree, controllable while the IC is operating.

The variations associated with IC process tend to affect a single IC in a more or less uniform manner, so relative differences in speed between multiple logic gates residing on a single IC are not particularly sensitive to those changes. However, input and output signals that couple the IC with other electronic circuits are especially susceptible to IC process variations, as an off-chip circuit with which the IC communicates is not likely to possess the same process variation as the IC. As a result, the relative changes in signal propagation times between the IC and other external circuits tend to be much greater than that between two internal signals of the IC. Such problems are often exacerbated in designs that involve multiple clock domains, in which multiple clocks of different frequencies and phases are utilized.

Currently, a couple of automatic techniques are often employed by IC designers to limit the effects of IC process variations to avoid signal timing problems. For example, an analog phase-locked loop (PLL) or a digital delay-locked loop (DLL) is often used to synchronize IC clock signals with external clock sources to counteract the negative effects of IC process variation. In other situations, process-voltage-temperature (PVT) compensated input/output (I/O) pads for ICs have been utilized to combat the problem. However, circumstances often occur where neither of these techniques is available for a particular IC design, or the techniques cannot fully compensate for exceptional process variations.

Therefore, from the foregoing, a need currently exists for an alternative circuit or method that addresses the inherent problems associated with the manufacturing process variations of an integrated circuit.

SUMMARY OF THE INVENTION

As shown above, automatic compensation techniques are not always effective. Alternately, a more programmatic approach based on a determination of the extent of process variation in a particular IC may be more beneficial. More specifically, by somehow measuring the gate delay of an IC, that information may then be used in software executed on, for example, a microprocessor, to take effective action to counteract the process variation.

Embodiments of the invention, to be discussed in detail below, provide a circuit and method for determining the delay of an integrated circuit associated with chip-to-chip manufacturing process variations, voltage and temperature changes, and the like. First, a clock signal is inverted, thus generating an inverted clock signal, which is then delayed multiple times, resulting in several delayed versions of the inverted clock signal. Each version of the inverted clock signal is delayed a different length of time. The logical state of each delayed version of the inverted clock signal is then stored to provide an indication of the magnitude of the delay of the integrated circuit. Those stored logical states may then be employed to tune one or more critical signals to compensate for the observed propagation delays due to process, temperature, and voltage variations of the IC.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

A schematic diagram of a circuit100according to an embodiment of the invention for determining IC signal propagation delay is shown inFIG. 1. First, using a clock signal CLK as input for the determining circuit100, a logic inverter102is employed to generate an inverted clock signal106.

The inverted clock signal106is used as a signal to be measured in determining the process-oriented delay of the IC. More specifically, the inverted clock signal106is provided as input to a number N of delay units103coupled together in a serial fashion. In the specific example of the determining circuit100ofFIG. 1, each delay unit103consists of four inverters105. An even number of inverters103may be used, depending on the particular circumstances involved. Also, other structures, such as delay lines, may be employed to perform essentially the same function. As a result, the output of each delay unit103generates a delayed inverted clock signal107, which drives the next delay unit103in the series. Therefore, each delay unit103further along the series of delay units103produces a slightly more delayed version107of the inverted clock signal106than the immediately preceding delay unit103.

In the specific example ofFIG. 1, each delay unit103employs a substantially identical amount of delay, as evidenced by the equal number of inverters105within each unit103. This structure is especially useful if the circuit propagation delays are linearly associated with variables such as temperature, voltage, and process-oriented variations of the IC. In alternate embodiments, that relationship may not be linear, but may instead be exponential, logarithmic, geometric, or another arithmetic relationship. In such cases, one or more delay units103may exhibit different propagation delays from other units103to more accurately describe those relationships.

In addition to each delay unit103, a preliminary delay unit104located prior to the series of delay units103may also be employed to further delay each delayed inverted clock signal107by a uniform amount. This optional use of the preliminary delay unit104aids in positioning in time the transitions of the delayed inverted clock signals107compared to the original clock signal CLK, the importance of which is described below. The preliminary delay unit104may be positioned either before or after the logic inverter102. As is the case with the delay units103, the preliminary delay unit104may be an even number of inverters105(as shown inFIG. 1), delay lines, or some other similar structure.

Each delayed inverted clock signal107generated by the delay units103drives the data input D of a logic storage element108of a first rank110. Thus, each delay unit103has single logic storage element108of the first rank110with which it is associated. Further, each of the logic storage elements108of the first rank110is clocked by the original clock signal CLK by way of a clock input CK.

Given that each logic storage element108is driven by a slightly different delayed version107of the inverted clock signal106, the possibility of at least one of the logic storage elements108of the first rank110encountering a timing violation between its delayed inverted clock signal107input and the clock signal CLK is not inconsequential. In other words, situations may occur in which the delayed inverted clock signal107for a particular logic storage element108is in transition between logic LOW and HIGH states at the same time that the clock signal CLK is also in transition. Such a situation may possibly cause the logic storage element108in question to become “metastable,” which may cause the output of the storage element108to oscillate or hover at some voltage level between logic HIGH and LOW for an unacceptable period of time. To help prevent such problems, metastable-resistant flip-flops from the prior art may be employed for the logic storage elements108of the first rank110.

To additionally address a potential metastability problem, a second rank120of logic storage elements108may be utilized to capture the outputs of the storage elements108of the first rank110. In the specific embodiment of the determining circuit100ofFIG. 1, the second rank120is clocked directly by the clock signal CLK, and the data inputs D are driven by the data outputs Q of the first rank110of logic storage elements108. Alternately, if metastability problems are not anticipated at the data outputs Q of the first rank110, the second rank120of logic storage elements108will not be necessary.

In the specific embodiment ofFIG. 1, D-type flip-flops are employed as the logic storage elements108for both the first rank110and the second rank120. Other types of logic storage elements, such as J-K and S-R flip-flops, may be employed as alternatives.

To facilitate discussion of the operation of the determining circuit100,FIG. 2andFIG. 3show by way of timing diagrams how the circuit100operates within a faster-than-nominal IC and a slower-than nominal IC. In the fast case200shown inFIG. 2, the clock signal CLK and the inverted clock signal106(/CLK) are shown. Due to the action of the delay units103, the state of each succeeding delayed inverted clock signal107, each of which drives a data input D for each of the N logic storage elements108of the first rank110, is delayed further by each delay unit103. The waveforms for the data inputs D of the first rank110are numbered from DN-1to D0, aligning with the designation of the logic storage elements N-1through0shown inFIG. 1. For an IC that exhibits a comparatively short propagation delay, each delay due to a delay unit103is accordingly short. As a result, each delayed inverted clock signal107is only delayed slightly compared to the preceding one. In this particular example, the leading edge of the clock signal CLK, shown by the vertical dotted lines ofFIG. 2, clocks the logic level at the data inputs D into each logic storage element108of the first rank110. Due to the short propagation delays, a logic HIGH value is clocked into a majority of the logic storage elements108. Only after the effect of N-2delay units103does the possibility of a logic LOW value being captured (at the data input D2) into a logic storage element108of the first rank110exist. Assuming D2is interpreted as LOW, the resulting binary value captured collectively by the first rank110would be DN-1. . . . D0=1111 . . . 1000. The fact that the first LOW value occurs toward the far right end of the captured data value indicates that the IC involved is faster than a nominally-processed IC.

If a second rank120of logic storage elements108is employed, as shown inFIG. 1, the values stored in the first rank110are available at the outputs of the second rank120one pulse of the clock signal CLK later.

FIG. 3shows a slow case201in which a slower-than-nominal IC is involved. Again, the clock signal CLK and the inverted clock signal106(/CLK) are shown, along with the several delayed inverted clock signals107presented at the data input D of each logic storage element108of the first rank110. However, in this particular case, a slower IC propagation delay results in each successive delayed inverted clock signal107being delayed a greater length of time from its predecessor. As a result, the first LOW value captured occurs in this case as early as the data input DN-4. Also, as shown inFIG. 3, the later data inputs D may transition back to a logic HIGH. Other transitions may also be exhibited, depending on the number N of logic storage elements108residing in the first rank110. However, the first transition from HIGH to LOW, which is at DN-4in this instance, indicates that the IC propagation delay is longer than what may normally be expected.

To eliminate the possibility of multiple transitions in the values captured by the logic storage elements108of the first rank110, a logic AND gate109associated with each delay103may be employed as shown in the second determining circuit101ofFIG. 4. The output of each AND gate109is configured to drive the data input D of each logic storage element108of the first rank110. The first input of each AND gate is configured to be driven by its associated delay unit103, while the second input is fashioned to be driven by the output of the AND gate109associated with the previous delay unit103in the series. For the AND gate associated with the first of the series of delay units103, the second input is held to a logic HIGH level. Use of the AND gates109serves to ensure that a logic LOW value for a delayed inverted clock signal107nulls out any potential HIGH logic levels from later delay units103in the series. As a result, the values captured by the logic storage elements108of the first rank110are thus essentially forced to represent a single HIGH-to-LOW transition.

In order for the determining circuit100,101to operate well in all cases, some idea of the possible maximum and minimum propagation delays in the IC is helpful in order to determine an appropriate structure for the delay units103. More specifically, the number of delay units103and, hence, logic storage elements108, to employ, as well as the delay associated with each delay unit103, determine the total amount of delay that can be determined. For example, the total delay exhibited by all of the delay units103could be selected so that ICs exhibiting the shortest propagation delay would result in a timing violation or value transition from HIGH to LOW somewhere near the far right end of the series of delay units103(i.e., near data inputs D1or D0). Additionally, the determining circuit100could also be structured so that ICs with the longest propagation delays would exhibit a HIGH-to-LOW transition as early as DN-1or DN-2. Also, the higher the number N of delay units103, the more resolution in determining the relative propagation delay of the IC. Furthermore, the optional use of the preliminary delay unit104also helps determine where a possible timing violation is indicated within the N logic storage elements108of the first rank110.

Furthermore, the determining circuit100,101provides the added potential advantage of determining effects on IC propagation delay due to temperature and voltage variations while the IC is operating. Since the determining circuit100,101does not specifically distinguish between the three identified sources of IC propagation delay variation, the determining circuit100,101may be used to track any changes that occur during IC operation, not just those static propagation delays due to manufacturing process variation.

The determining circuit100,101may be used in conjunction with a tuning circuit300, as shown inFIG. 5, that uses the values from the determining circuits100,101to tune the speed of a critical signal SIGNAL, such as a digital clock, typically by way of a programmable delay. For example, a microprocessor, microcontroller, application-specific IC (ASIC), or similar device307may be employed to read the outputs of the first rank110or second rank120of logic storage elements108by way of an addressable register, a general purpose port, or similar means. The microprocessor or similar device307may then tune the speed of one or more critical signals based on that output value. Similar to the determining circuit100,101, the tuning circuit300employs M serially-coupled delay units305, each of which in this case are comprised of several logic inverters503. The output of each delay unit305drives the inputs of an M-to-1 multiplexer310. As a result, each input of the multiplexer310is driven by a delayed version of the critical signal SIGNAL, with each version exhibiting a different propagation delay. One of the delayed versions is selected and transferred to the output DELAYED SIGNAL of the multiplexer310by way of log2M selector lines, which may be driven by an addressable register, a general purpose port, or similar means by the microprocessor307. Thus, a critical signal may be delayed by some programmable amount depending on the overall IC propagation delay as determined by the determining circuit100,101, as described earlier.

The present invention also describes a method400for determining the propagation delay of an IC, as displayed inFIG. 6. Generally, a clock signal is logically inverted, resulting in an inverted clock signal (step410). The propagation of that inverted clock signal is then delayed multiple times, resulting in several delayed inverted clock signals (step420). Each of the delayed inverted clock signals is delayed a different amount. The logical state of each of the delayed inverted clock signals in then stored for each pulse of the original clock signal (step430). As a result, the resulting stored states indicate the relative propagation delay of the IC. Optionally, that information may then be used to tune critical signals of the IC (step440), as described above.

From the foregoing, specific embodiments of the invention provide a circuit and related method for determining the propagation delay associated with an integrated circuit. That circuit and method may then be used to tune critical signals of the IC to avoid timing problems resulting primarily from significant process25variations, as well as temperature and voltage changes. Other embodiments of the present invention that are not specifically described herein are also possible. As a result, the invention is not to be limited to the specific forms so described and illustrated; the invention is limited only by the claims.