Telescoping blind via in three-layer core

A multilayer PCB including at least one carrier, wherein the at least one carrier comprises a pseudo three-layer core. Each three-layer core includes a first metal layer, a first dielectric layer, an internal bridge layer, a second dielectric layer, and a second metal layer. The bridge layer includes a plurality of bridge pads. Each carrier includes a plurality of interlayer interconnection units for interconnecting the first and second metal layers. Each interlayer interconnection unit comprises a pair of opposed blind vias and a bridge pad disposed between, and in electrical contact with, the pair of blind vias.

BACKGROUND OF THE INVENTION

The present invention generally relates to printed circuit boards, and more particularly to multilayer printed circuit boards comprising a three-layer core having a dual blind via interlayer interconnection unit. The present invention also relates to methods for forming a three-layer core of a multilayer printed circuit board.

The present trend in the design and manufacture of printed circuit boards (PCBs) is towards decreased size, smaller hole or via diameter, and higher interconnection density. High interconnection densities require multilayer PCBs having more than one signal layer with numerous interconnections therebetween.

Each signal layer of prior art multilayer PCBs typically consists of a patterned conductive metal layer. Adjacent conductive layers are separated by an insulating material or dielectric layer comprising, for example, a polyimide or a resin which may be reinforced with glass fiber. Interconnections between the various conductive layers are provided by holes or vias that extend through the intervening dielectric layer, wherein the vias or holes are plated, filled, and/or plated over with conductive material. Such vias or holes may be through holes, blind vias, or buried vias. Through holes extend to all conductive layers of a multilayer assembly. In contrast, blind vias and buried vias pass through only part of a PCB—blind vias having one end of the via exposed, and buried vias having neither end of the via exposed. Thus, a blind via connects two or more layers of a PCB and starts on an outer layer, but does not pass completely through the PCB. A buried via connects two or more inner layers of a PCB but no outer layer.

Two-layer cores, which consist of a thin dielectric layer covered with copper foil, form the basic building block of prior art PCBs. Typically, the dielectric layer of a two-layer core is covered with copper foil on both sides. Multilayer PCBs of the prior art may be formed by laminating two or more two-layer cores. After patterning the copper foil of the signal layers, the layers are laminated using heat and pressure. Plated via holes for interlayer connection may be formed by drilling in the z-axis between layers, e.g., by laser drilling, followed by plating the hole. A blind via may be formed by drilling partly through one or more dielectric layers, followed by plating the hole, or by forming a plated through hole and then laminating an additional layer on one side thereof. A buried via may be formed by forming a blind via and laminating an additional layer on the exposed end of the blind via, or by providing a plated through hole and laminating an additional layer on each side of the plated through hole. Such procedures or processes are well known in the art.

As noted above, the standard building block of prior art PCBs is a core consisting of a two-layer dielectric carrier. Stacking a μvia on either side of such a carrier requires a solid target pad for laser ablating down to (or building up from with additive technology) the top of the carrier's buried via. This requires creating either a solid copper through via, or a via that is filled and plated over in the carrier. Creation of such vias becomes problematic as via size and dielectric thickness decrease. In order to form a large enough via in the carrier to drill and fill effectively, the minimum producible drill-to-adjacent-feature spacing cannot be maintained. Likewise, filling a through via on a thin carrier has limited producibility due to limitations of via fill and plating processes related to decreased carrier thickness. Also, restrictions on high aspect ratio of the filled hole effectively limit the thickness of the carrier's dielectric layer. However, in certain situations a thicker dielectric layer might be required, e.g., for impedance purposes, or for overall finished dimensions of the PCB. Furthermore, thin dielectric layers, which may be required to maintain a minimum aspect ratio for μvias formed therein, may lack the necessary dimensional stability for processing, e.g., filling a plated hole, which may result in destruction of the carrier.

In addition, filling a via of the prior art usually requires multiple plating cycles, and consequently may result in unacceptably thick total surface copper for etching fine features on a signal layer. Consequently, a significant portion of the total surface copper may have to be removed by mechanical means during processing according to the prior art.

FIG. 1Ais a cross-sectional view of a copper clad dielectric layer10for processing into a conventional two-layer carrier for a PCB, according to the prior art. Copper clad dielectric layer10includes a first copper layer20, a second copper layer22, and a dielectric layer24disposed between first and second copper layers20,22. Dielectric layer24may comprise a dielectric material, such as a glass fiber reinforced resin, or a polyimide, and the like.

FIG. 1Bis a cross-sectional view of a conventional carrier10′ for a PCB in the form of a two-layer core, according to the prior art. Carrier10′ has two metal layers, namely a first copper layer20and a second copper layer22, as well as a dielectric layer24disposed between first and second copper layers20,22. Carrier10′ includes a plated through hole40which has been filled and plated over. Plated through hole40extends from a first pad30within first copper layer20to a second pad32within second copper layer22. Plated through hole40serves as a conducting interconnection-between first and second copper layers20,22. Such plated through holes are well known in the art. Regions of the prior art two-layer core that lack first and second copper layers20,22, e.g., due to etching thereof, are represented by reference numeral26.

FIG. 1Cis a cross-sectional view of a conventional carrier10″ for a PCB in the form of a two-layer core, also according to the prior art. Carrier10″ includes a dielectric layer24disposed between first and second copper layers20,22, essentially as described forFIG. 1B.FIG. 1Cshows a blind via40′ which has been filled and plated over. Blind via40′ extends from a first pad30within first copper layer20to a second pad32within second copper layer22. Blind via40′ serves as a conducting interconnection between different layers of a multilayer PCB, e.g., between first and second copper layers20,22. Such blind vias are well known in the art. Regions of prior art carrier10″ that lack first and second copper layers20,22, e.g., due to etching thereof, are represented by reference numeral26.

As noted hereinabove, conventional two-layer cores of the prior art have a number of drawbacks and disadvantages. As an example, as hole size (e.g., via diameter) diminishes to accommodate higher interconnect densities, dielectric thickness must also decrease in order to maintain a certain minimum aspect ratio for the hole, since holes having aspect ratios below the producible minimum cannot be filled efficiently or reliably. Restrictions on dielectric thickness, in turn, are associated with a number of other disadvantages. However, dielectrics below a certain thickness cannot be processed reliably, leading to destruction of many incipient cores and poor processing efficiency. For example, increased dielectric thickness may be required for impedance purposes. Furthermore, a PCB having a relatively large overall dielectric thickness may offer advantages for providing connections thereto. In addition, increased overall dielectric thickness may allow for production of a PCB having a greater overall finished thickness, for example, to fit within a particular housing of an instrument, device, or appliance.

As can be seen, there is a need for a multilayer PCB having an interlayer interconnection unit, the formation of which requires only a single plating cycle. The use of only a single plating cycle can result in decreased thickness of total surface copper, thereby facilitating formation of fine features without the need for mechanical reduction of the surface copper layer. There is also a need for a dual via interlayer interconnection unit for a multilayer PCB, wherein the interconnection unit allows an overall increased aspect ratio, as compared with prior art plated through holes and vias. There is a further need for a PCB core or subassembly wherein the total thickness of the dielectric, at minimum hole and pad diameter, can be increased when greater dielectric thickness is required, for example, for impedance purposes or for overall finished thickness.

SUMMARY OF THE INVENTION

In one aspect of the present invention, an interlayer interconnection unit for a multi-layer printed circuit board (PCB) comprises an interstitial bridge pad having a first side and a second side, wherein the interstitial bridge pad is disposed between a first dielectric layer and a second dielectric layer; a first blind via disposed on the first side of the interstitial bridge pad, wherein the first blind via extends through the first dielectric layer; and a second blind via disposed on the second side of the interstitial bridge pad, wherein the second blind via extends through the second dielectric layer.

In another aspect of the present invention, an interlayer interconnection unit for a multi-layer PCB comprises a first capture pad having a first annular ring; a first via having a first via inner end and a first via outer end, with the first via outer end in contact with the first capture pad and encircled by the first annular ring; an interstitial bridge pad having a first side and a second side, with the first via inner end in contact with the first side of the interstitial bridge pad; a second via having a second via inner end and a second via outer end, with the second via inner end in contact with the second side of the interstitial bridge pad; and a second capture pad having a second annular ring, with the second via outer end in contact with the second capture pad and encircled by the second annular ring.

In yet another aspect of the present invention, a dual blind via interconnection unit for a multilayer PCB comprises a pair of opposed coaxial blind vias; and a bridge pad disposed between the pair of blind vias, wherein each of the pair of blind vias is in contact with the bridge pad.

In still another aspect of the present invention, a carrier for a multi-layer PCB comprises a pseudo three-layer core. The pseudo three-layer core includes a first metal layer, a first dielectric layer disposed on the first metal layer, a bridge layer disposed on the first dielectric layer, a second dielectric layer disposed on the bridge layer, and a second metal layer disposed on the second dielectric layer. The bridge layer comprises a plurality of spaced apart interstitial bridge pads, and each of the plurality of interstitial bridge pads is adapted for providing an interlayer interconnection between the first metal layer and the second metal layer.

In a further aspect of the present invention, a pseudo three-layer core for a PCB may comprise a plurality of interlayer interconnection units, wherein each of the interlayer interconnection units extends from a first metal layer to a second metal layer; a first dielectric layer disposed on the first metal layer; a bridge layer disposed on the first dielectric layer; and a second dielectric layer disposed on the bridge layer, wherein the second metal layer is disposed on the second dielectric layer. Each of the interlayer interconnection units may comprise an interstitial bridge pad located within the bridge layer, a first blind via extending from the first metal layer to a first side of the interstitial bridge pad, and a second blind via extending from the second metal layer to a second side of the interstitial bridge pad.

In yet a further aspect of the present invention, a multi-layer PCB comprises a first signal layer; a second signal layer; a bridge layer disposed between the first signal layer and the second signal layer; and a plurality of interlayer interconnection units. Each of the interlayer interconnection units may be adapted for connecting the first signal layer with the second signal layer through the bridge layer.

In still a further aspect of the present invention, a multi-layer PCB comprises at least one pseudo three-layer core. Each pseudo three-layer core may include a first metal layer, a first dielectric layer disposed on the first metal layer, a bridge layer disposed on the first dielectric layer, a second dielectric layer disposed on the bridge layer, a second metal layer disposed on the second dielectric layer, and a plurality of interlayer interconnection units. Each of the interlayer interconnection units may comprise an interstitial bridge pad having a first side and a second side, a first blind via disposed on the first side of the interstitial bridge pad, and a second blind via disposed on the second side of the interstitial bridge pad.

In an additional aspect of the present invention, a multilayer PCB may comprise a means for carrying a plurality of signal layers; and a plurality of means for interconnecting at least two of the signal layers, wherein the carrying means comprises a pseudo three-layer core, wherein the pseudo three-layer core includes an internal bridge layer, wherein the bridge layer comprises a plurality of interstitial bridge pads, and wherein each of the interconnecting means comprises a pair of opposed blind vias disposed on either side of each of the interstitial bridge pads.

In yet an additional aspect of the present invention, a method for forming a multilayer PCB comprises providing a metal clad first dielectric layer having a first metal clad side and a second metal clad side; forming a bridge layer from the second metal clad side, wherein the bridge layer comprises a plurality of bridge pads, and wherein the first metal clad side comprises a first metal layer; providing a second dielectric layer on the bridge layer, wherein the second dielectric layer has a second metal layer disposed thereon; forming a plurality of first blind vias through the first dielectric layer, with the plurality of first blind vias extending from the first metal layer to a first side of each of the plurality of bridge pads; and forming a plurality of second blind vias through the second dielectric layer, with the plurality of second blind vias extending from the second metal layer to a second side of each of the plurality of bridge pads.

In still a further aspect of the present invention, a method for forming a multilayer PCB comprises forming a pseudo three-layer core, wherein the pseudo three-layer core includes a first metal layer, a first dielectric layer disposed on the first metal layer, a bridge layer disposed on the first dielectric layer, a second dielectric layer disposed on the bridge layer, and a second metal layer disposed on the second dielectric layer, wherein the bridge layer comprises a plurality of spaced apart interstitial bridge pads. The method further comprises forming a plurality of interlayer interconnection units for interconnecting the first metal layer and the second metal layer, wherein each of the interlayer interconnection units includes a first blind via disposed on a first side of one of the plurality of interstitial bridge pads, wherein the first blind via extends from the first metal layer through the first dielectric layer; and a second blind via disposed on a second side of one of the plurality of interstitial bridge pads, wherein the second blind via extends from the second metal layer through the second dielectric layer.

In yet an additional aspect of the present invention, a method for forming a multilayer PCB comprises a step for forming a pseudo three-layer core, wherein the pseudo three-layer core includes a first metal layer, a first dielectric layer disposed on the first metal layer, a bridge layer disposed on the first dielectric layer, a second dielectric layer disposed on the bridge layer, and a second metal layer disposed on the second dielectric layer, wherein the bridge layer comprises a plurality of bridge pads. The method further comprises a step for forming a plurality of interlayer interconnection units for interconnecting the first metal layer and the second metal layer, wherein each of the interlayer interconnection units includes a first blind via disposed on a first side of one of the plurality of interstitial bridge pads, wherein the first blind via extends from the first metal layer through the first dielectric layer, and a second blind via disposed on a second side of one of the plurality of interstitial bridge pads, wherein the second blind via extends from the second metal layer through the second dielectric layer.

In still another aspect of the present invention, a method for forming a pseudo three-layer core for a PCB comprises providing a first metal layer; providing a first dielectric layer on the first metal layer; forming a bridge layer on the first dielectric layer, wherein the bridge layer comprises a plurality of bridge pads; providing a second dielectric layer on the bridge layer; providing a second metal layer on the second dielectric layer; forming a first blind via on a first side of each of the plurality of bridge pads, wherein the first blind via extends from the first metal layer through the first dielectric layer; and forming a second blind via on a second side of each of the plurality of bridge pads, wherein the second blind via extends from the second metal layer through the second dielectric layer.

DETAILED DESCRIPTION OF THE INVENTION

Generally, the present invention provides a carrier for a multilayer printed circuit board (PCB) or printed wiring board, wherein the carrier may include a novel interlayer interconnection unit for interconnecting a plurality of conductive layers of the multilayer PCB. A basic carrier, sub-assembly, or building block according to one embodiment of the invention may comprise a pseudo three-layer core. Each pseudo three-layer core may comprise two signal layers for a multilayer PCB, wherein the two signal layers are interconnected through an interconnection unit comprising an internal bridge layer disposed between the two signal layers.

A pseudo three-layer core of the present invention may have additional layers added thereto. For example, a multilayer PCB of the invention may comprise a single pseudo three-layer core, and up to six (6) or more conductive layers. A plurality of carriers may be combined, e.g., laminated together, to form a multilayer PCB having up to about 28 or more signal layers. Multilayer PCBs find almost universal applications in electrical or electronic devices, instruments, and appliances.

In contrast to a conventional two-layer core of the prior art, for example, as described hereinabove with reference toFIGS. 1B-C, in one embodiment the present invention provides a carrier having two dielectric layers, a bridge layer disposed between the two dielectric layers, and a pair of external conductive layers. As compared with carriers of the present invention, prior art carriers, i.e., two-layer cores of prior art multilayer PCBs, have only a single dielectric layer and lack a bridge layer. As compared with prior art multilayer PCBs which have a carrier comprising a two-layer core in which a single dielectric layer is disposed between two conductive layers, multilayer PCBs of the present invention have a carrier comprising a three-layer core, or pseudo three-layer core, including a pseudo metal layer or bridge layer disposed between two dielectric layers.

The bridge layer of carriers of the present invention may be referred to as a pseudo metal layer in that the bridge layer is not a metal layer of the type encountered in prior art carriers, for example, due to the lack of electrical connectivity within the bridge layer between the metal bridge pads that constitute the bridge layer. Due to the presence of the internal pseudo metal (bridge) layer in carriers of the present invention, the basic carrier of the invention, which may comprise the bridge layer, the two dielectric layers, and the pair of external conductive layers, may be referred to as a pseudo three-layer core. The pair of outer conductive layers may be interconnected by a plurality of interlayer interconnection units, wherein each interconnection unit may comprise an interstitial bridge pad located within the bridge layer, and a pair of coaxial, opposed blind vias disposed on either side of the interstitial bridge pad.

In some embodiments of the present invention, a pseudo three-layer core of the invention may itself constitute a multilayer PCB. In other embodiments of the invention, additional dielectric layers and additional conductive (e.g., signal) layers may be sequentially laminated to the pseudo three-layer core. Furthermore, two or more pseudo three-layer cores of the present invention, with or without additional dielectric and conductive layers, may be laminated to each other to form multilayer PCBs having up to 28 or more signal layers.

FIG. 2is a block diagram schematically representing a multilayer PCB100, according to one embodiment of the present invention. Multilayer PCB100may include a first carrier or core110a. In some embodiments, multilayer PCB100may further include one or more additional carriers110n. The one or more additional carriers110nmay be laminated to first carrier110a. Each of first carrier110aand additional carrier(s)110nmay comprise a pseudo three-layer core of the present invention. Each pseudo three-layer core may comprise two signal layers. Such a pseudo three-layer core is described fully hereinbelow, for example, with respect toFIGS. 4A-B. In some embodiments, one or more of first carrier110aand additional carriers110nmay further comprise one or more additional signal layers120′,122′ (FIG. 6).

FIG. 3is a sectional view showing a plurality of interlayer interconnection units within a portion of a pseudo three-layer core110, according to an embodiment of the present invention. Pseudo three-layer core110may include a first interlayer interconnection unit150a, and an nthinterlayer interconnection unit150n. Pseudo three-layer core110may include a first metal layer120, a first dielectric layer124disposed on first metal layer120, a bridge layer126disposed on first dielectric layer124, a second dielectric layer125disposed on bridge layer126, and a second metal layer122disposed on second dielectric layer125. Each of interlayer interconnection units150aand150nextend from first metal layer120, through bridge layer126, to second metal layer122. For the purpose of clarity, only two interconnection units150a,150nare shown inFIG. 3. In practice, pseudo three-layer core110may include any number of interlayer interconnection units. Typically, interlayer interconnection units150a,150nmay be present only at locations, with respect to the x and y dimensions of a PCB, at which it is desired to interconnect first metal layer120to second metal layer122. Locations at which interlayer interconnection units150a,150nmay be present correspond to the locations of bridge pads134. Such locations of bridge pads134are schematically represented inFIG. 5. The x and y dimensions are shown inFIG. 5by the arrows labeled “x” and “y” respectively. Interlayer interconnection units of the present invention are further described hereinbelow, e.g., with reference toFIGS. 4A-B.

FIG. 4Ashows an interlayer interconnection unit150within a three-layer core110, with interlayer interconnection unit150shown in perspective view, according to one embodiment of the present invention. Three-layer core110may include an internal bridge layer126disposed between first dielectric layer124and second dielectric layer125. Three-layer core110may further include first and second metal layers120,122, respectively, as described hereinabove.

Bridge layer126may comprise a plurality of spaced apart interstitial bridge pads134. Each bridge pad134may comprise an essentially disc-shaped conductive element, e.g., a copper disc. Each bridge pad134may lack electrical connection to other bridge pads134within bridge layer126. Interlayer interconnection unit150may include one bridge pad134located within bridge layer126(FIG. 5). That is to say, each bridge pad134may be a component of an interlayer interconnection unit150.

Interlayer interconnection unit150may further include a first capture pad130within first metal layer120, and a second capture pad132within second metal layer122. First capture pad130and second capture pad132may each comprise a conductive (e.g., copper) element, which may be formed by the selective removal, e.g., by etching, of first metal layer120and second metal layer122, respectively. It is apparent fromFIG. 4Athat bridge pad134may have a diameter, Dbthat is greater than a diameter, Dcof first and second capture pads130,132. First Interlayer interconnection unit150may still further include a first blind via140and a second blind via142. Each of first blind via140and second blind via142may be formed by a process such as laser drilling, plasma drilling, or photo-definition (photo-defining). AlthoughFIG. 4Ashows a gap112within bridge layer126on either side of bridge pad134, during lamination first and second dielectric layers124,125may fuse together such that bridge pad134may be encapsulated within first and second dielectric layers124,125.

During formation of interlayer interconnection unit150, a first annular ring131may be formed within first metal layer120. As an example, first annular ring131may comprise an annular, outer portion of first capture pad130. Similarly, during formation of interlayer interconnection unit150, a second annular ring133may be defined within second metal layer122. As an example, second annular ring133may comprise an annular, outer portion of second capture pad132. Each of first annular ring131and second annular ring133may comprise an annular conductive (e.g., copper) element.

After forming first and second blind vias140,142, respectively, first and second blind vias140,142may be plated shut. In some embodiments, first and second blind vias140,142may be plated shut using a μfill process, such as the MicroFill™ VF process of the Shipley Company, LLC (Marlborough, Mass.). Briefly, MicroFill™ VF is a direct current electrolytic copper plating process for filling blind vias, including vias. (See, for example,MicroFill™ VF, Electrolytic Copper, Plating Technology for Filling Blind Microvias in HDI/Build-up Printed Wiring Boards, Ref. No. PM02N006, Rev. No. 0, Copyright, 2002, Shipley Company, LLC (Marlborough, Mass.); andMicroFill VF Process Manual, Ref. No. PM03N002, Rev. No. 0, February, 2003, Shipley Company, LLC (Marlborough, Mass.), both of which are incorporated by reference herein).

FIG. 4Bis a side view of the interlayer interconnection unit ofFIG. 4A, according to the present invention. First and second dielectric layers124,125are omitted fromFIG. 4Bfor the sake of clarity. As may be seen inFIGS. 4A-B, bridge pad134may include a first side134aand a second side134b. First blind via140may include a first via inner end140aand a first via outer end140b. Inner end140amay be in electrical contact with bridge pad first side134a, while outer end140bmay be in electrical contact with first capture pad130and encircled by first annular ring131. Second blind via142may include a second via inner end142aand a second via outer end142b. Inner end142amay be in electrical contact with bridge pad second side134b, while outer end142bmay be in electrical contact with second capture pad132and encircled by second annular ring133. First and second annular rings131,133, may be considered to be the remaining annular portion of first and second capture pads130,132, respectively, after formation of a hole therethrough. Thus, interlayer interconnection unit150may extend from first capture pad130, through first blind via140, bridge pad134, second blind via142, and thence to second capture pad132.

Again with reference toFIGS. 4A-B, each of first and second blind vias140,142, respectively, may have an aspect ratio of about 1:1, and usually at least about 1:1. Because first and second blind vias140,142are aligned in the z dimension, or coaxial with each other, interlayer interconnection unit150may have an effective aspect ratio of about 2:1, and often greater than 2:1. Thus, interlayer interconnection unit150of the instant invention allows for a greater than two fold (2×) increase in effective aspect ratio for interconnecting adjacent conductive layers of multilayer PCBs, as compared with the prior art. At the same time, because pseudo three-layer core110of the instant invention has two dielectric layers and two signal layers (as compared with only one dielectric layer in prior art two-layer cores) the total dielectric thickness (i.e., the combined thickness of first and second dielectric layers124,125) per signal layer (e.g., the mean thickness of first metal layer120and second metal layer122) may be increased by about two fold in carriers of the present invention as compared with a prior art two-layer core. This increase in total dielectric thickness per signal layer is achieved without increasing the aspect ratio of each blind via, i.e., of first and second blind vias140,142. The effective aspect ratio of interlayer interconnection unit150, as referred to herein, is the ratio of the length, L (FIG. 4B) (i.e., the z dimension) of interlayer interconnection unit150to the diameter, Dv(FIG. 4B) of first and second blind vias140,142. The z axis is indicated inFIG. 4Aby the vertical arrow labeled “z”.

FIG. 5is a plan view of a portion of a bridge layer126of a carrier for a multilayer PCB of the present invention. Bridge layer126may include a plurality of interstitial bridge pads134. Each interstitial bridge pad134may comprise a metal, such as copper. The plurality of interstitial bridge pads134may be conveniently formed by etching one side of a copper clad dielectric layer124(e.g.,FIGS. 11A-B).

Interstitial bridge pads134may be spaced apart from each other by a distance, S in the range of from about 0.7 to 4 mils, with a center-to-center pitch, P in the range of from about 15 to 25 mils. Each interstitial bridge pad134may have a diameter, d in the range of from about 12 to 20 mils, usually in the range of from about 14 to 17 mils, and often in the range of from about 15 to 16 mils. Interstitial bridge pads134typically lack electrical connectivity, within bridge layer126, to other bridge pads134, or to any other conductive element (e.g., a trace or a component) of bridge layer126. That is to say, bridge layer126may consist of a plurality of spaced apart bridge pads134, with no electrical connections therebetween within bridge layer126.

FIG. 6schematically represents a carrier110′ for a multilayer PCB, according to one embodiment of the present invention. Carrier110′ may include a pseudo three-layer core110. As shown, carrier110′ may further include a first additional dielectric layer124′ and a first additional conductive layer120′ laminated thereto. Carrier110′ may still further include a second additional dielectric layer125′ and a second additional conductive layer122′ laminated thereto. In other embodiments of the invention (not shown inFIG. 6), carrier110′ may have fewer or more additional dielectric and conductive layers than those shown inFIG. 6laminated to pseudo three-layer core110.

As described hereinabove, pseudo three-layer core110may itself comprise two signal layers120,122. By adding additional conductive layers, e.g., layers120′,122′ to pseudo three-layer core110, each carrier110′ may comprise from three to six or more conductive layers (only four conductive layers120,122,120′, and122′ are shown inFIG. 6). Each of layers120,122,120′, and122′, or of any other additional conductive layers (not shown inFIG. 6) of a carrier or multilayer PCB100may comprise a signal layer; or one or more conductive layers (e.g., layers120,122,120′, and122′, or other additional conductive layers) of a carrier or multilayer PCB100may comprise a plane or ground layer, as is well known in the art. Two or more carriers110′ may be combined (laminated) together (FIG. 2) to form a multilayer PCB having from four to 28 or more conductive layers (see, e.g.,FIG. 6).

FIG. 7schematically represents a series of steps (202-214) involved in a method200for making a conventional carrier for a multilayer PCB, according to the prior art. Step202involves providing a metal clad dielectric layer, such as a layer of dielectric material having a layer of copper foil on each side. Due to production limitations associated with filling μvias of a defined diameter and aspect ratio in a thin dielectric layer, the minimum thickness of the dielectric layer in prior art PCBs is typically about 4 mils.

Step204involves forming pads (capture pads and target pads) on the copper layers by etching the copper foil. The formation of such pads is well known in the art. Due to the industry trend towards high-density interconnections, the diameter of current state of the art capture pads and target pads is typically limited to around 10 mils. In prior art processing, there may be difficulties in aligning the drill to pads of this size. In comparison, bridge pads134of the invention may have diameters, d up to about 20 mils or more. The larger diameter, d f bridge pads134of the invention is possible because the pseudo metal layer (or bridge layer)126of carriers of the invention may lack traces, components, or other conductive features. The larger diameter of bridge pads134of the invention offer the advantage of facilitating drill registration during via formation.

Step206involves drilling a hole though one or both of the copper layers and the dielectric layer, to form a blind via or a through hole. Step208involves plating the hole. Thereafter, step208, which entails a first plating cycle of the prior art process, adds to the overall thickness of the surface copper. Step210involves filling the hole with electrically conductive material, such as a high solids epoxy. Filling the hole in this manner becomes impracticable for presently used dielectric thickness, hole diameter, and aspect ratio. Step212involves plating over the fill, in a second plating cycle, to provide a contiguous metal layer over the filled hole. Thus, step212further adds to the surface copper thickness.

Excessive thickness of surface copper may prevent etching of fine features. For example, for a PCB having a 3 mil line and space specification, a surface copper thickness of 1.4 mils or less may be required. Prior art processes that result in surface copper thickness greater than 1.4 mils may require additional processing steps to remove excess surface copper.

Step214of the prior art process involves planarizing the copper layer(s) in which holes have been drilled, plated, filled, and plated over. Planarizing may be accomplished by mechanical reduction of surface copper, which process may excessively stress the carrier. In situations, where surface copper exceeds the maximum permissible thickness, reduction of surface copper may damage or destroy the carrier or its components, leading to decreased manufacturing efficiency.

In contrast to the prior art, processes of the invention for making a multilayer PCB may use only one plating cycle. As a result, a total surface copper thickness of about 1 mil or less can be readily achieved. Lower total surface copper thickness decreases the amount of planarizing and mechanical reduction of surface copper, and allows finer line and space resolution.

FIG. 8schematically represents a series of steps (302-318) which may be involved in a method300for making a multilayer PCB, according to one embodiment of the present invention. Step302may involve providing a metal clad first dielectric layer, such as a dielectric layer having a first side and a second side, and a layer of copper foil on both the first side and the second side. Step304may involve forming a bridge layer on one side of the dielectric layer. The bridge layer may comprise a plurality of spaced apart bridge pads, as described herein (FIGS. 4A-B,FIG. 5). The bridge layer may be formed by etching the copper foil on one side of the dielectric layer. Alternatively, the bridge pads and the bridge layer may be formed by building up from an exposed dielectric layer using an additive technology. The bridge layer formed during step302may be referred to as a pseudo metal layer.

Step306may involve providing a second dielectric layer disposed on the bridge layer. Step308may involve providing a second metal layer laminated to the second dielectric layer. Steps306and308may be combined into a single process in which a dielectric layer, which has been clad with the second metal layer, may be disposed on the bridge layer.

Step310may involve forming a first blind via, wherein the first blind via extends from the first metal layer, through the first dielectric layer, and to a first side of a bridge pad within the bridge layer. Step312may involve forming a second blind via from the second metal layer, through the second dielectric layer, and to a second side of the bridge pad within the bridge layer. Each of the first blind via and the second blind via142may be formed by a process such as laser drilling, plasma drilling, or photo-defining. Typically, the first blind via may emanate from a first capture pad of the first metal layer, and the second blind via may emanate from a second capture pad of the second metal layer. The first and second capture pads may be formed by etching the first and second metal layers, respectively.

Step314may involve plating shut the first and second blind vias, such that an interlayer interconnection unit may be formed within a multilayer carrier, wherein the interlayer interconnection unit may include a bridge pad disposed between the first and second blind vias (FIG. 4A). The first and second blind vias may be opposed to each other in the z dimension and coaxial with the bridge pad. The first and second blind vias may be plated shut in a single plating cycle using a μfill process, such as the MicroFill™VF process of the Shipley Company, LLC (Marlborough, Mass.), as referred to hereinabove.

Optional step316may involve laminating one or more additional dielectric layers, and one or more additional metal layers, to the first and second metal layers of the basic carrier or pseudo three-layer core formed by steps302-314. In this way, a carrier having up to six or more signal layers may be formed. Optional step318can involve laminating together two or more carriers formed by steps302-314, or by steps302-316, to provide a multilayer PCB having from 4 to 28 or more signal layers.

FIG. 9schematically represents a series of steps (402-404) involved in a method400for making a multilayer PCB, according to another embodiment of the present invention. Step402may involve forming a multilayer carrier or a pseudo three-layer core. A pseudo three-layer core formed according to step402may include two signal layers. In some embodiments, the multilayer carrier or pseudo three-layer core may be considered to be a sub-assembly for the multilayer PCB. For example, additional signal layers may be laminated to the pseudo three-layer core; or two or more pseudo three-layer cores may be laminated together to form a multilayer PCB having at least 4 signal layers. Step404may involve forming a plurality of interlayer interconnection units within the carrier for interconnecting two or more conductive layers of the carrier. Interlayer interconnection units of the invention were described hereinabove (e.g., with reference toFIGS. 4A-B). Formation of interlayer interconnection units of the invention is also described herein, for example, with reference to method400(FIG. 9).

FIG. 10schematically represents a series of steps (502-514) involved in a method500for making a carrier for a multilayer PCB, according to another embodiment of the present invention, wherein step502may involve providing a first metal layer. Step504may involve providing a first dielectric layer. The first metal layer may be laminated to a first side of the first dielectric layer.

Step506may involve forming a bridge layer. Bridge layer, which may comprise a plurality of spaced apart bridge pads, may be formed by etching a layer of copper foil laminated to a second side of the first dielectric layer. Formation of the bridge layer is described elsewhere herein, for example, with reference to method200(FIG. 7).

Step508may involve providing a second dielectric layer. The second dielectric layer provided in step508may be laminated to the bridge layer, such that the bridge pads of bridge layer are encapsulated in dielectric material between the first and second dielectric layers. Step510may involve providing a second metal layer, which may be laminated to the second dielectric layer.

Step512may involve forming a first blind via of an interlayer interconnection unit, wherein the first blind via may be disposed between the first metal layer and a first side of a bridge pad. Step514may involve forming a second blind via of the interlayer interconnection unit, wherein the second blind via may be disposed between the second metal layer and a second side of the bridge pad. First and second blind vias formed on opposite sides of a bridge pad within a multilayer carrier are described hereinabove, e.g., with reference toFIGS. 4A-BandFIG. 7.

In method500, first and second blind vias may be plated shut in a single plating cycle, for example, as described with reference to method200(FIG. 7). Use of a single plating cycle minimizes excessive build-up of surface copper, and therefore decreases the need for subsequent reduction of surface copper, as described hereinabove. Optionally, after forming and plating shut the first and second blind vias to form a pseudo three-layer core, one or more additional dielectric layers and metal layers may be laminated to the pseudo three-layer core (see, e.g., step316of method300(FIG. 8)).

FIGS. 11A-Eillustrate stages in forming an interlayer interconnection unit for a multilayer PCB, according to one embodiment of the present invention.FIG. 11Ashows a first dielectric layer124which can be clad on each side with a layer of copper foil, namely a first layer of copper foil120and a second layer of copper foil126′. First dielectric layer124may also be referred to as a metal clad first dielectric layer124having a first metal clad side clad with a first layer of copper foil120, and a second metal clad side clad with a second layer of copper foil126′. The first layer of copper foil120may also be referred to herein as first metal layer120. The second layer of copper foil126′ may be etched to form a bridge layer126(FIGS. 11B-E).

FIG. 11Bshows a bridge pad134, which may be formed by etching second layer of copper foil126′. For the sake of clarity,FIGS. 11B-Eshow only one bridge pad134within bridge layer126; however in practice, a much larger number of bridge pads may be formed within bridge layer126.

FIG. 11Cshows the structure ofFIG. 11Band which may have a second dielectric layer125and a second metal layer122laminated thereto. AlthoughFIGS. 11C-Eshow a gap112within bridge layer126adjacent to bridge pad134, during lamination first and second dielectric layers124,125may fuse around bridge pad134such that bridge pad134may be encapsulated within first and second dielectric layers124,125.

FIG. 11Dillustrates the structure ofFIG. 11Cafter etching first and second metal layers120,122, respectively to form capture pads130,132, respectively.FIG. 11Dalso shows a first blind via140and a second blind via142. First and second blind vias140,142can extend from first and second metal layers120,122, respectively, to first and second sides of bridge pad134.

FIG. 11Eshows the structure ofFIG. 11Dwhich may have solid first and second blind vias140′,142′ filled and plated shut to form interlayer interconnection unit150for interconnecting first and second metal layers120,122. An interlayer interconnection unit150of the invention has been described hereinabove. Briefly, interlayer interconnection unit150may include first capture pad130, solid first blind via140′, bridge pad134, solid second blind via142′, and second capture pad132.