SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME

A semiconductor device comprises a substrate that extends in first and second directions and includes a cell region and an extension region that extends from the cell region in the first direction, first and second insulating layers alternately stacked on the substrate in a third direction, a conductive line disposed on one sidewall of the second insulating layer in the second direction, a conductive pillar that extends in the third direction and penetrates through the first insulating layer, a semiconductor layer disposed on one sidewall of the conductive pillar and that extends in the third direction, and a ferroelectric layer disposed between the conductive line and the semiconductor layer and that extends in the third direction. The conductive line includes first and second conductive patterns spaced apart from each other in the second direction, and the second insulating layer is disposed between the first and second conductive patterns.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims priority under 35 U.S.C. 119 from Korean Patent Application No. 10-2022-0092505, filed on Jul. 26, 2022 in the Korean Intellectual Property Office, the contents of which are herein incorporated by reference in their entirety.

TECHNICAL FIELD

Embodiments of the present disclosure are directed to a semiconductor device and a method of fabricating the same, and more particularly, to a semiconductor device that includes ferroelectrics and a method of fabricating the same.

DISCUSSION OF THE RELATED ART

The degree of integration of a semiconductor device has been gradually increased to meet performance and cost demands of consumers. For a planar or two-dimensional semiconductor device, since the degree of integration is mainly determined by an area occupied by a unit cell, the semiconductor device is affected by the technology of forming fine patterns.

However, as a design rule of a semiconductor device is reduced, there are limitations in forming fine patterns due to limitations of resolution in a process of forming patterns for implementing a semiconductor device. Accordingly, three-dimensional semiconductor devices in which cells are three-dimensionally arranged have been proposed.

BRIEF SUMMARY

Embodiments of the present disclosure provide a semiconductor device and a method of fabricating the same, in which the number of processes that form a three-dimensionally arranged ferroelectric field effect transistor are reduced.

Embodiments of the present disclosure provide a semiconductor device and a method of fabricating the same, in which resistance characteristics of a three-dimensionally arranged ferroelectric field effect transistor are improved.

A semiconductor device according to some embodiments of the present disclosure comprises a substrate that extends in first and second directions that cross each other, where the substrate includes a cell region and an extension region that extends from the cell region in the first direction, first and second insulating layers alternately stacked on the substrate in a third direction that crosses the first and second directions, a conductive line disposed on one sidewall of the second insulating layer in the second direction, a conductive pillar that extends in the third direction and penetrates through the first insulating layer, a semiconductor layer disposed on one sidewall of the conductive pillar and that extends in the third direction, and a ferroelectric layer disposed between the conductive line and the semiconductor layer and that extends in the third direction. The conductive line includes first and second conductive patterns spaced apart from each other in the second direction, and the second insulating layer is disposed between the first and second conductive patterns.

A semiconductor device according to some embodiments of the present disclosure comprises a substrate that includes a cell region that extends in first and second directions that cross each other and includes a ferroelectric memory cell formed thereon, and an extension region that extends from the cell region in the first direction, a first conductive line that extends in the first direction on the substrate, a plurality of second conductive lines spaced apart from the first conductive line in the second direction and spaced apart from each other in the first direction, a ferroelectric layer disposed between one sidewall of the first conductive line and the plurality of second conductive lines and that extends in the first direction, a semiconductor layer disposed between the ferroelectric layer and the plurality of second conductive lines and that extends in the first direction, and an isolation plug disposed between the plurality of second conductive lines. The first conductive line includes a plurality of first and second conductive patterns spaced apart from each other in the second direction, and a silicon material layer that extends in the first direction and is disposed between the first and second conductive patterns.

A method of fabricating a semiconductor device according to some embodiments of the present disclosure comprises forming a stacked structure on a substrate, where the stacked structure includes an insulating layer and a sacrificial layer that are alternately stacked, and the substrate includes a cell region and an extension region, forming first and second trenches that penetrate through at least a portion of the stacked structure and are spaced apart from each other in a first direction, and a third trench between the first and second trenches, forming a sacrificial pattern that has a smaller width than the sacrificial layer by partially removing the sacrificial layer, forming a first conductive line that includes first and second conductive patterns that are spaced apart from each other on both sidewalls of the sacrificial pattern, respectively forming a ferroelectric layer, a semiconductor layer and a first dielectric layer in the first to third trenches, forming an opening that penetrates through the first dielectric layer and the semiconductor layer in the third trench, forming a second dielectric layer within the opening, and forming a plurality of second conductive layers by respectively removing the first dielectric layers from the first and second trenches.

DETAILED DESCRIPTION

Hereinafter, a semiconductor device according to some embodiments will be described with reference toFIGS.1to6.

FIG.1is a block diagram of a semiconductor device according to some embodiments.FIG.2is a circuit diagram of a semiconductor device according to some embodiments.FIG.3is a schematic perspective view of a semiconductor device according to some embodiments.FIG.4is a cross-sectional view taken along line A-A′ ofFIG.3.FIG.5is a cross-sectional view taken along line B-B′ ofFIG.3.FIG.6is a schematic layout view of a semiconductor device according to some embodiments.

Referring toFIG.1, the semiconductor device according to some embodiments is a random access memory50. The random access memory50includes a memory array52, a row decoder54, and a column decoder56.

The memory array52includes a memory cell58, a word line62, and a bit line64. The memory cell58are arranged in rows and columns. The word line62and the bit line64are electrically connected to the memory cell58. The word line62is a conductive line that extends along the row of the memory cell58. The bit line64is a conductive line that extends along the column of the memory cell58.

The row decoder54selects a desired memory cell58from the row of the memory array52by activating the word line62for the row. The column decoder56selects the bit line64for the desired memory cell58from the column of the memory array52of the selected row, reads data from the selected memory cell58by using the bit line64, or writes the data in a cell.

Referring toFIG.2, in an embodiment, the memory array52includes a plurality of memory cells58arranged in a matrix of rows and columns. Since the memory cells58are vertically stacked in a three-dimensional memory array, the degree of integration of the semiconductor device is increased. The memory array52is disposed in a back end of line (BEOL) of a semiconductor die.

The semiconductor device according to some embodiments is a three-dimensional non-volatile memory device, and includes a ferroelectric field effect transistor (FeFET).

Each memory cell58includes a transistor68. A gate of each transistor68is electrically connected to each word line62, a first source/drain region of each transistor68is electrically connected to each bit line64, and a second source/drain region of each transistor68is electrically connected to a source line66. The memory cells58in the same horizontal row of the memory array52share a common word line, and the memory cells58in the same vertical column of the memory array52share a common source line and a common bit line.

Referring toFIG.3, in an embodiment, the memory array52includes word lines62and a plurality of insulating layers72disposed between adjacent word lines62. The word lines62include a plurality of word lines62U,62A,62B and62C that are vertically stacked. The number of word lines62and the number of insulating layers72are not limited to those shown, and may be provided in various numbers.

The word lines62U,62A,62B and62C extend in a first direction D1parallel with an upper surface of a substrate (102ofFIG.4). The word lines62U,62A,62B and62C extends from a cell region CELL (seeFIG.5) to an extension region EXT (seeFIG.5), and have a stepwise shape in the extension region such that the lowermost word line62C is longer than the uppermost word line62U. The word line62corresponds to a first conductive line112that will be described below.

Some of the word lines62A,62B and62C are connected to respective word line contacts78A,78B and78C in the extension region EXT (seeFIG.5). The word line contacts78A,78B and78C are formed in exposed portions of the respective word lines62A,62B and62C. The word line contacts78A,78B and78C correspond to the first contact142that are connected to each word line62and extend in a third direction D3on each word line62.

The plurality of bit lines64and the source lines66are disposed between the word lines62adjacent in second direction D2that crosses the first direction D1. Each of the bit line64and the source line66extends in a third direction D3perpendicular to the first direction D1. The bit line64corresponds to a second conductive line134that will be described below, and the source line66corresponds to a third conductive line136.

An isolation layer74is disposed between adjacent bit lines64and source lines66to isolate them. The word line62, the bit line64and the source line66that cross each other define each memory cell58. The isolation layer74includes a dielectric material such as silicon oxide, but is not necessarily limited thereto.

A dielectric plug76is disposed between adjacent bit lines64and sources line66to isolate them. The bit line64and the source line66are electrically connected to a ground. The dielectric plug76corresponds to an isolation plug132that will be described below.

A semiconductor layer82provides a channel region for the transistor68of the memory cell58. For example, when an appropriate voltage, such as a voltage higher than each threshold voltage of the corresponding transistor68, is applied through the corresponding word line62, a region of the semiconductor layer82that crosses the word line62allows a current to flow along the first direction D1from the bit line64to the source line66.

Each semiconductor layer82is in contact with one surface of each corresponding word line62to provide a planar channel region for the transistor68. According to some embodiments, the semiconductor layer82provides a three-dimensional channel region for the transistor68by being in contact with a plurality of surfaces of the corresponding word line62. The semiconductor layer82is disposed between the isolation layer74and a ferroelectric layer84that will be described below.

The ferroelectric layer84is disposed between the word line62and the semiconductor layer82. The ferroelectric layer84provides a gate dielectric for the transistor68. The ferroelectric layer84includes, for example, at least one of hafnium oxide, zirconium oxide, hafnium zirconium oxide, or their combination.

To perform a write operation in the memory cell58, a write voltage is applied to a portion of the ferroelectric layer84that corresponds to the memory cell58. The write voltage is applied, for example, by applying an appropriate voltage to a corresponding word line62, a corresponding bit line64, and a source line66. The write operation of the memory cell58i applies a predetermined write voltage to the word line62to implement different residual polarizations in the ferroelectric layer84, and stores the different residual polarizations as signal information.

To perform a read operation for the memory cell58, a read voltage, such as voltage between a low threshold voltage and a high threshold voltage, is applied to the corresponding word line62. The read operation of the memory cell58changes the threshold voltage of the field effect transistor in accordance with a size or orientation of the residual polarization stored in the ferroelectric layer84.

Referring toFIGS.4to6, in some embodiments, a semiconductor device described inFIG.3is disposed on the substrate102. For example, a semiconductor device according to some embodiments includes a substrate102, a first insulating layer104A, a second insulating layer104B, a first conductive line112, a second conductive line134, a third conductive line136, a ferroelectric layer114, a semiconductor layer116, an isolation plug132, a first contact142, a second contact144(seeFIGS.20and21), a third contact146(seeFIGS.20and21), and an interlayer insulating layer180.

The substrate102extends in the first direction D1and the second direction D2. The first direction D1and the second direction D2are parallel to the upper surface of the substrate102and cross each other. The third direction D3is perpendicular to each of the first direction D1and the second direction D2.

The substrate102includes a cell region CELL in which a ferroelectric field effect transistor is disposed, and an extension region EXT that extends from the cell region CELL in the first direction D1. The first conductive line112, which will be described below, is disposed in the extension region EXT in a stepwise shape.

The substrate102includes a semiconductor substrate such as a silicon substrate, a germanium substrate, or a silicon-germanium substrate. Alternatively, the substrate102include a silicon-on-insulator (SOI) substrate or a germanium-on-insulator (GOI) substrate.

The first insulating layer104A and the second insulating layer104B are alternately stacked in the third direction D3. For example, the first insulating layer104A includes silicon oxide, and the second insulating layer104B includes silicon nitride.

The first conductive line112extends in the first direction D1on the substrate102. The first conductive line112is disposed on one sidewall of the second insulating layer104B in the second direction D2.

The first conductive line112includes a main conductive layer112M that includes first and second conductive patterns112A and112B spaced apart from each other. The second insulating layer104B is disposed between the first and second conductive patterns112A and112B. The first conductive line112further includes an adhesive layer112C disposed between the first conductive pattern112A and the second insulating layer104B and between the second conductive pattern112B and the second insulating layer104B.

The second conductive line134passes through the first insulating layer104A. For example, the second conductive line134extends in the third direction D3in a pillar shape. A plurality of second conductive lines134are spaced apart from each other in the first direction D1. The second conductive line134are spaced apart from the first conductive line112in the second direction D2.

The semiconductor layer116is disposed on one sidewall of the second conductive line134, and extends in the third direction D3. The semiconductor layer116is disposed between the ferroelectric layer114and the plurality of second conductive lines134in the second direction D2.

The semiconductor layer116includes, for example, one of doped polysilicon, doped silicon, silicon germanium (SiGe), or a semiconductor material formed through selective epitaxial growth (SEG), but is not necessarily limited thereto, and may include an oxide semiconductor material. The oxide semiconductor material is, for example, at least one of IGZO, Sn-IGZO, IWO, CuS2, CuSe2, WSe2, IZO, ZTO, or YZO, but is not necessarily limited thereto. For example, the semiconductor layer116include one of MoS2, MoSe2, or WS2.

The ferroelectric layer114is disposed between the first conductive line112and the semiconductor layer116, and extends in the third direction D3. The ferroelectric layer114is disposed between one sidewall of the first conductive line112and the second conductive line134in the second direction D2.

The ferroelectric layer114includes, for example, at least one of hafnium oxide, zirconium oxide, hafnium zirconium oxide, or their combination. In addition, the ferroelectric layer114may include a ferroelectric material that has a perovskite structure, such as one of PZT(PbZrxTi1−xO3), BaTiO3or PbTiO3. The ferroelectric layer114includes at least one dopant selected from carbon (C), silicon (Si), magnesium (Mg), aluminum (Al), yttrium (Y), nitrogen (N), germanium (Ge), tin (Sn), strontium (Sr), lead (Pb), calcium (Ca), barium (Ba), titanium (Ti), zirconium (Zr), gadolinium (Gd), or lanthanum (La). The ferroelectric layer114is formed of a crystalline material. For example, the ferroelectric layer114has an orthorhombic crystalline structure.

AlthoughFIG.4only shows the second conductive line134, the description of the second conductive line134made with reference toFIG.4equally applies to the third conductive line136.

The isolation plug132is disposed between the plurality of second conductive lines134, and extends in the third direction D3. The isolation plug132is disposed between the plurality of second conductive lines134in the first direction D1. The isolation plug132includes an insulating material. For example, the isolation plug132includes silicon oxide, but is not necessarily limited thereto. The ferroelectric layer114is disposed between the lower end of the isolation plug132and the substrate102.

The first contact142, which corresponds to word line contacts78A,78B and78C, is disposed on the first conductive line112, which corresponds to the word line62, and is connected to the first conductive line112, and extends in the third direction D3. The first contact142is a via that electrically connects an upper line structure140with the first conductive line112.

The second contact144(seeFIG.21) is disposed on the second conductive line134and is connected to the second conductive line134, and extends in the third direction D3. The second contact144is a via that electrically connects the upper line structure140with the second conductive line134.

Referring toFIG.6, in an embodiment, in a plan view, the word line62includes an uneven structure. For example, in the second direction D2, a width of each of the word lines62A,62B and62C of the extension region EXT differs from that of the word line62U of the cell region CELL.

The word lines62A,62B and62C of the extension region EXT include a first region R1in which the word line contacts78A,78B and78C are not formed and a second region R2in which the word line contacts78A,78B and78C are formed. A width W1in the second direction D2of the first region R1is greater than a width W2in the second direction D2of the second region R2.

In addition, the second insulating layer104B is disposed in the first region R1of the word lines62A,62B and62C, but is not disposed in the second region R2thereof. A plurality of second insulating layers104B are spaced apart from each other in the first direction D1.

In a process that partially removes a sacrificial layer described below, more of the sacrificial layer is removed from the second region R2than from the first region R1, so that the sacrificial layer in the extension region EXT does not remain where the word line contact is formed.

According to some embodiments, no insulating layer such as a silicon nitride layer is formed in a region where a word line contact is formed, whereby resistance characteristics of the word line contact are improved.

FIG.7is a schematic layout view of a semiconductor device according to some embodiments. For convenience of description, descriptions of components made with reference toFIGS.1to6may be omitted.

Referring toFIG.7, in an embodiment, in the second direction D2, a width W3of the word lines62A,62B and62C in the extension region EXT is less than a sum W6of a width of the word line62U and a width of a second insulating layer104B in the cell region CELL.

In the second direction D2, the width W3of the word lines62A,62B and62C in the extension region EXT is less than or equal to a sum of a width W4of the first conductive pattern112A in the cell region CELL and a width W5of the second conductive pattern112B in the cell region CELL.

For example, the second insulating layer104B is disposed in the cell region CELL but not in the extension region EXT.

In the second direction D2, the widths W4of the first conductive pattern112A and W5of the second conductive pattern112B in the cell region CELL refer to lengths W4and W5where the sacrificial layer is removed in a process that partially removes the sacrificial layer. For example, the length (the sum of W4and W5) of the region where the sacrificial layer is removed is greater than or equal to the width W3of the word lines62A,62B and62C in the extension region EXT so that no sacrificial layer remains in the extension region EXT.

FIGS.8to21illustrate intermediate steps of a method of fabricating a semiconductor device according to some embodiments. For convenience of description, descriptions of components described with reference toFIGS.1to7may be omitted.FIGS.8,10,12,14,16,18and20are three-dimensional views of a memory array52.FIGS.9,11,13,15,17,19and21are cross-sectional views taken along the C-C′ ofFIG.18.

Referring toFIGS.8and9, in some embodiments, a stacked structure104is formed on a substrate102. The stacked structure104includes a first insulating layer104A and a second insulating layer104B that are alternately disposed. The substrate102includes a cell region CELL and an extension region EXT as described above.

AlthoughFIGS.8and9show the stacked structure104as including five first insulating layers104A and four second insulating layers104B, embodiments of the present disclosure are not necessarily limited thereto. The number of first insulating layers104A and second insulating layers104B in the stacked structure104may different from those illustrated in the drawing. Further, the thicknesses of the substrate102, the first insulating layer104A and the second insulating layer104B are not necessarily limited to those shown in this drawing.

The material included in the first insulating layer104A and the second insulating layer104B has a high etch selectivity with respect to the material included in the substrate102.

The second insulating layer104B serves as a sacrificial layer, and at least a portion thereof is removed and replaced with a word line of the transistor68as described below. The material included in the second insulating layer104B has a high etch selectivity with respect to the material included in the first insulating layer104A.

For example, the second insulating layer104B includes at least one of silicon nitride, silicon oxynitride, silicon rich (Si-rich) nitride, or nanocrystalline silicon. In some embodiments, the second insulating layer104B is referred to as a silicon material layer containing silicon.

For example, when the substrate102is formed of silicon carbide, the first insulating layer104A includes silicon oxide and the second insulating layer104B includes silicon nitride, but embodiments of the present disclosure are not necessarily limited thereto, and other combinations of dielectric materials with acceptable etch selectivity are used in other embodiments.

The first insulating layer104A and the second insulating layer104B of the stacked structure104are formed by a known deposition method such as chemical vapor deposition (CVD) and/or atomic layer deposition (ALD).

Referring toFIGS.10and11, in some embodiment, the first to third trenches106T1,106T2and106T3are formed in the stacked structure104. The first and second trenches106T1and106T2penetrate through at least a portion of the stacked structure104, and are spaced apart from each other in the first direction D1. The third trench106T3is disposed between the first and second trenches106T1and106T2. For example, the second conductive line134, which will be described below, is formed in the first and second trenches106T1and106T2, and the isolation plug132, which will be described below, is formed in the third trench106T3.

The first to third trenches106T1,106T2and106T3extend in the third direction D3by penetrating through at least a portion of the stacked structure104and expose the substrate102. The first to third trenches106T1,106T2and106T3are formed through a selective etching process for the substrate102.

For example, the first to third trenches106T1,106T2and106T3are formed by etching the first insulating layer104A and the second insulating layer104B at a faster speed than the substrate102. The etching process includes, for example, one or more known processes, such as a reactive ion etch (RIE) or a neutral beam etch (NBE), etc.

Referring toFIGS.12and13, in some embodiments, at least a portion of the second insulating layer104B is removed to form a sacrificial pattern104C that has a recessed sidewall110. The first to third trenches106T1,106T2and106T3are enlarged to form the recessed sidewall110. Therefore, the sacrificial pattern104C whose width is smaller than that of the second insulating layer104B is formed.

For example, a portion of the sidewall of the second insulating layer104B exposed by the first to third trenches106T1,106T2and106T3is removed to form the recessed sidewall110. The recessed sidewall110is shown as having a straight line shape, but is not necessarily limited thereto, and the recessed sidewall may have a concave or convex curved shape in other embodiments.

The recessed sidewall110is formed using known etching processes for the second insulating layer104B. For example, when the first insulating layer104A is formed of silicon oxide and the second insulating layer104B is formed of silicon nitride, the first to third trenches106T1,106T2and106T3are expanded by an etching process that uses phosphoric acid (H3PO4).

Referring toFIGS.14and15, in some embodiments, the first conductive line112is formed in the recessed sidewall110. A plurality of first conductive lines112are formed that are spaced apart from each other. A plurality of first conductive lines112adjacent to each other serve as a single word line62.

The first conductive line112includes one or more main conductive layers112M and adhesive layers112C. The main conductive layer112M include a first conductive pattern112A and a second conductive pattern112B that are spaced apart from each other in the second direction D2. The sacrificial pattern104C is disposed between the first conductive pattern112A and the second conductive pattern112B.

Since the first conductive pattern112A and the second conductive pattern112B are a portion of the main conductive layer112M, they include the same material. For example, the first conductive pattern112A and the second conductive pattern112B are formed of a conductive material such as at least one of tungsten (W), ruthenium (Ru), molybdenum (Mo), cobalt (Co), aluminum (Al), nickel (Ni), copper (Cu), silver (Ag), gold (Au), or their alloy.

The adhesive layer112C is disposed between the first conductive pattern112A and the sacrificial pattern104C and between the second conductive pattern112B and the sacrificial pattern104C. The adhesive layer112C is disposed along upper surfaces, one side and lower surfaces of the first conductive pattern112A and the second conductive pattern112B.

For example, the adhesive layer112C is formed of a conductive material such as at least one of titanium nitride (TiN), tantalum nitride (TaN), molybdenum nitride, zirconium nitride or hafnium nitride. The adhesive layer112C includes a material that has an adhesive force with respect to the first insulating layer104A and the main conductive layer112M.

The adhesive layer112C and the main conductive layer112M are formed by known deposition methods, such as one or more of chemical vapor deposition (CVD) and/or atomic layer deposition (ALD). A portion of surfaces of the adhesive layer112C and the main conductive layer112M are etched by a known etching process so that the adhesive layer112C and the main conductive layer112M are formed on the same plane as a sidewall of the first insulating layer104A and the upper surface of the substrate102.

Referring toFIGS.16and17, in some embodiments, the ferroelectric layer114, the semiconductor layer116, and a first dielectric layer118are formed in each of the first to third trenches106T1,106T2and106T3. For example, the ferroelectric layer114is conformally formed along sidewalls and bottom surfaces of the first to third trenches106T1,106T2and106T3. The semiconductor layer116is formed of two layers along sidewalls of the ferroelectric layer114. The first dielectric layer118fills inner spaces of the first to third trenches106T1,106T2and106T3along sidewalls of the semiconductor layer116.

The ferroelectric layer114is a data storage layer formed of a ferroelectric material that stores digital values. The ferroelectric layer114is formed by a deposition process, such as one or more of chemical vapor deposition (CVD), atomic layer deposition (ALD) or physical vapor deposition (PVD).

The semiconductor layer116includes materials such as at least one of indium gallium zinc oxide (IGZO), indium tin oxide (ITO), indium gallium zinc tin oxide (IGZTO), zinc oxide (ZnO), polysilicon or amorphous silicon. The semiconductor layer116is formed of a semiconductor material that provides a channel region for the transistor68. The semiconductor layer116is formed by a deposition process such as one or more of chemical vapor deposition (CVD), atomic layer deposition (ALD) or physical vapor deposition (PVD).

The first dielectric layer118is formed of a dielectric material. For example, the dielectric material includes one of an oxide such as silicon oxide or aluminum oxide, a nitride such as silicon nitride, a carbide such as silicon carbide, or their combination such as silicon oxynitride, silicon oxycarbide or silicon carbonitride. The first dielectric layer118is formed by a deposition process such as one or more of chemical vapor deposition (CVD), atomic layer deposition (ALD) or physical vapor deposition (PVD).

A planarization process is performed on the ferroelectric layer114, the semiconductor layer116and the first dielectric layer118. For example, the planarization process is one of a chemical mechanical polish (CMP) process, an etch back process, or their combination. Upper surfaces of the ferroelectric layer114, the semiconductor layer116and the first dielectric layer118are made coplanar by the planarization process.

Referring toFIGS.18and19, in some embodiments, the isolation plug132penetrates through the first dielectric layer118and the semiconductor layer116and extends in the third direction D3. A first opening that penetrates through the first dielectric layer118and the semiconductor layer116is formed in the third trench106T3, and a second dielectric layer is formed in the first opening to form the isolation plug132.

The first opening is formed using one or more known photolithography or etching processes. One or more dielectric materials are formed in the first opening. For example, the dielectric material includes at least one of an oxide such as silicon oxide, a nitride such as silicon nitride, a carbide such as silicon carbide, or silicon oxynitride, silicon oxycarbide, silicon carbonitride, or their combination.

The isolation plug132is an isolation column disposed between adjacent transistors68, and physically and electrically isolates the adjacent transistors68.

Each isolation plug132is disposed between the bit line64of a transistor68and the source line66of another transistor68. For example, the bit line64and the source line66are disposed on opposite sides of each isolation plug132. Thus, each isolation plug132physically and electrically isolates adjacent transistors68.

In some embodiments, the isolation plug132does not extend by penetrating through the ferroelectric layer114. Alternatively, in some embodiments, the isolation plug132is formed that penetrates through the ferroelectric layer114. For example, the isolation plug132further extends and penetrates through at least a portion of the first insulating layer104A and the second insulating layer104B.

The second conductive line134and the third conductive line136are formed that penetrate through the first dielectric layer118and extend in the third direction D3.

To form the second conductive line134and the third conductive line136, a second opening for the second conductive line134and the third conductive line136is formed by passing through the first dielectric layer118. The second opening is formed using one or more known photolithography and/or etching processes.

A conductive material is formed in the second opening. For example, the conductive material includes metals, such as one or more of tungsten, cobalt, aluminum, nickel, copper, silver, gold or their alloys.

Each of the second conductive line134and the third conductive line136includes an adhesive layer and a main conductive layer on the adhesive layer, similar to the first conductive line112, but embodiments of the present disclosure are not necessarily limited thereto.

Referring toFIGS.20and21, in some embodiments, the upper line structure140is formed on the stacked structure104. For example, referring toFIGS.5and21, the upper line structure140includes an interlayer insulating layer180, a plurality of insulating layers141, and a line pad148.

The line pad148is electrically connected to the second conductive line134and the third conductive line136. The third contact146is a via that electrically connects the upper line structure140with the third conductive line136.

The plurality of insulating layers141include a dielectric material. The plurality of insulating layers141include one or more dielectric layers. The line pad148include a conductive material.

Therefore, a semiconductor device described usingFIG.4can be formed. According to some embodiments, the number of processes for replacing the sacrificial layer with the word line can be reduced. Further, the number of subsequent processes for forming the ferroelectric layer, the semiconductor layer and the dielectric layer can be reduced.

Although the embodiments of the present disclosure have been described with reference to the accompanying drawings, it will be apparent to those skilled in the art that embodiments of the present disclosure can take various forms without being limited to the above-described embodiments and can be embodied in other specific forms without departing from the spirit and essential characteristics of embodiments of the disclosure. Thus, the above embodiments are to be considered in all respects as illustrative and not restrictive.