SEMICONDUCTOR PACKAGE

Provided is a semiconductor package, including a semiconductor substrate including a plurality of first vias, a chip stack on the semiconductor substrate, the chip stack including first semiconductor chips on the semiconductor substrate, and a second semiconductor chip on an uppermost first semiconductor chip of the first semiconductor chips, and a mold layer on the semiconductor substrate and the chip stack, and exposing a top surface of the chip stack, wherein a first thickness of the semiconductor substrate is greater than a second thickness of each of the first semiconductor chips, wherein a third thickness of the second semiconductor chip is less than or equal to the second thickness of each of the first semiconductor chips, wherein the semiconductor substrate further includes lower substrate pads on a bottom surface of the semiconductor substrate, wherein each of the first semiconductor chips includes lower chip pads on a bottom surface of each of the first semiconductor chips, and wherein a first width of each of the lower substrate pads is greater than a second width of each of the lower chip pads.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims priority to Korean Patent Application No. 10-2023-0022852, filed on Feb. 21, 2023, in the Korean Intellectual Property Office, the disclosure of which is incorporated by reference herein in its entirety.

BACKGROUND

Embodiments of the present disclosure relate to a semiconductor package and a method of fabricating the same, and in particular, to a stack-type semiconductor package, in which a plurality of semiconductor chips are disposed on a substrate, and a method of fabricating the same.

With recent advancements in the electronics industry, there is an increasing demand for high-performance, high-speed, and compact electronic components. In response to this trend, packaging technologies of mounting a plurality of semiconductor chips in a single package are being developed.

Recently, a demand for portable electronic devices has been rapidly increasing in the market, and thus, it is necessary to reduce sizes and weights of electronic components constituting the portable electronic devices. To achieve this, it is necessary to develop packaging technologies that reduce the size and weight of each component and integrate a plurality of individual components in a single package.

In the semiconductor industry, various package technologies have been developed in response to an increase in demand for large-capacity, thin, and small semiconductor devices and/or electronic products therewith. For example, a package technology of vertically stacking semiconductor chips has been suggested to realize a high-density chip stacking structure. This technology makes it possible to integrate semiconductor chips of various functions on a small area, compared with a typical package provided in the form of a single semiconductor chip. However, various technical problems occur as the number of the disposed semiconductor chips increases.

SUMMARY

One or more embodiments provide a semiconductor package with an increase integration density.

One or more embodiments also provide a semiconductor package with a reduced size.

One or more embodiments also provide a semiconductor package with improved structural stability and improved heat-dissipation characteristics.

According to an aspect of an embodiment, there is provided a semiconductor package, including a semiconductor substrate including a plurality of first vias, a chip stack on the semiconductor substrate, the chip stack including first semiconductor chips on the semiconductor substrate, and a second semiconductor chip on an uppermost first semiconductor chip of the first semiconductor chips, and a mold layer on the semiconductor substrate and the chip stack, and exposing a top surface of the chip stack, wherein a first thickness of the semiconductor substrate is greater than a second thickness of each of the first semiconductor chips, wherein a third thickness of the second semiconductor chip is less than or equal to the second thickness of each of the first semiconductor chips, wherein the semiconductor substrate further includes lower substrate pads on a bottom surface of the semiconductor substrate, wherein each of the first semiconductor chips includes lower chip pads on a bottom surface of each of the first semiconductor chips, and wherein a first width of each of the lower substrate pads is greater than a second width of each of the lower chip pads.

According to another aspect of an embodiment, there is provided a semiconductor package, including a semiconductor substrate including a plurality of first vias, semiconductor chips on the semiconductor substrate, each of the semiconductor chips including second vias vertically penetrating the semiconductor chips, and a mold layer on the semiconductor substrate and the semiconductor chips, and exposing a top surface of an uppermost semiconductor chip of the semiconductor chips, wherein a first width of the semiconductor substrate is greater than a second width of the chip stack in a horizontal direction, wherein the semiconductor substrate has a first thickness in a vertical direction, wherein the semiconductor chips have second thicknesses, which are equal to each other, in the vertical direction, and wherein the first thickness is greater than the second thicknesses.

According to another aspect of an embodiment, there is provided a semiconductor package, including a substrate, first semiconductor chips on the substrate, and a second semiconductor chip on an uppermost first semiconductor chip of the first semiconductor chips, wherein each of the first semiconductor chips includes upper pads on a top surface each of the first semiconductor chips, first lower pads on a bottom surface each of the first semiconductor chips, and first vias vertically penetrating the first semiconductor chips and connecting the upper pads to the first lower pads, respectively, wherein the second semiconductor chip includes second lower pads a bottom surface of the second semiconductor chip, wherein first terminals on the first lower pads are between a lowermost first semiconductor chip of the first semiconductor chips and the substrate, wherein a first thickness of each of the first semiconductor chips is equal to a second thickness of the second semiconductor chip, wherein side surfaces of the first semiconductor chips are coplanar to a side surface of the second semiconductor chip, and wherein the second thicknesses of the semiconductor chips range from 20 μm to 40 μm.

DETAILED DESCRIPTION

Example embodiments will now be described more fully with reference to the accompanying drawings, in which example embodiments are shown.

FIG.1is a sectional view illustrating a semiconductor package according to an embodiment.FIG.2is an enlarged sectional view of a portion ‘A’ ofFIG.1.FIG.3is an enlarged sectional view of a portion ‘B’ ofFIG.1.

A semiconductor package according to an embodiment may be a stack-type package, in which via patterns are used. For example, semiconductor chips of the same type may be disposed (stacked) on a base substrate, and the semiconductor chips may be electrically connected to each other through via patterns, which are provided to penetrate the semiconductor chips. The semiconductor chips may be coupled to each other using chip terminals, which are provided on bottom surfaces of the semiconductor chips.

Referring toFIGS.1to3, a base substrate100may be provided. The base substrate100may be a semiconductor substrate. The base substrate100may include an integrated circuit which is provided therein. For example, the base substrate100may be a first semiconductor chip including an electronic element (e.g., a transistor). For example, the base substrate100may be a wafer-level die formed of a semiconductor material (e.g., silicon (Si)). AlthoughFIG.1illustrates an example in which the base substrate100is a first semiconductor chip, embodiments are not limited thereto. In an embodiment, the base substrate100may be a substrate (e.g., a printed circuit board (PCB)), in which an electronic element (e.g., a transistor) is not provided. A silicon wafer may be thinner than a printed circuit board (PCB). Hereinafter, the base substrate100may be referred to as a first semiconductor chip100.

A first thickness T1of the first semiconductor chip100in a vertical direction (stacking direction) may range from 30 μm to 60 μm. The first semiconductor chip100may include a first circuit layer110, a first via120, a first upper pad130, a first protection layer140, and a first lower pad150.

The first circuit layer110may be provided on a bottom surface of the first semiconductor chip100. The first circuit layer110may include the integrated circuit. For example, the first circuit layer110may include a memory circuit, a logic circuit, or combinations thereof. The bottom surface of the first semiconductor chip100may be an active surface.

The first via120may be provided to vertically penetrate the first semiconductor chip100. For example, the first via120may be extended toward a top surface of the first semiconductor chip100and may be exposed to the outside of the first semiconductor chip100near the top surface of the first semiconductor chip100. The first via120may be extended to the first circuit layer110and may be connected to the first circuit layer110. The first via120and the first circuit layer110may be electrically connected to each other. In an embodiment, a plurality of first vias120may be provided. An insulating layer may be provided to enclose the first via120. For example, the insulating layer may be formed of or include at least one of silicon oxide (SiO), silicon nitride (SiN), silicon oxynitride (SiON), or low-k dielectric materials. According to another embodiment, a seed layer or a barrier layer may be provided to cover a side surface and a bottom surface of the first via120. For example, the seed layer may be formed of or include gold (Au). For example, the barrier layer may be formed of or include titanium nitride (TiN) or tantalum nitride (TaN).

The first upper pad130may be disposed on the top surface of the first semiconductor chip100. The first upper pad130may be coupled to the first via120. In an embodiment, a plurality of first upper pads130may be provided. In this case, the first upper pads130may be coupled to the first vias120, respectively, and may be arranged in the same shape as the first vias120. The first upper pad130may be electrically connected to the first circuit layer110through the first via120. The first upper pad130may be formed of or include at least one of metallic materials (e.g., copper (Cu), aluminum (Al), and/or nickel (Ni)).

The first protection layer140may be disposed on the top surface of the first semiconductor chip100to enclose the first upper pad130. The first protection layer140may expose the first upper pad130. A top surface of the first protection layer140and a top surface of the first upper pad130may be substantially flat and may be substantially coplanar with each other. According to another embodiment, the first upper pad130may have a protruding portion, which is extended to a level higher than the top surface of the first protection layer140in the vertical direction, or the first protection layer140may be extended to the top surface of the first upper pad130to cover an edge portion of the first upper pad130and expose a center portion of the first upper pad130. The first semiconductor chip100may be protected by the first protection layer140. The first protection layer140may be formed of or include at least one of oxide, nitride, or oxynitride materials, which contain a semiconductor element included in the first semiconductor chip100. For example, the first protection layer140may be formed of or include at least one of silicon oxide (SiO), silicon nitride (SiN), silicon oxynitride (SiON), or combinations thereof. The first protection layer140may be an insulating coating layer containing an epoxy resin, a solder resist layer, or a photosensitive resin layer.

The first lower pad150may be disposed on the bottom surface of the first semiconductor chip100. For example, the first lower pad150may be disposed on a bottom surface of the first circuit layer110. The first lower pad150may be electrically connected to the first circuit layer110. In an embodiment, a plurality of first lower pads150may be provided. The first lower pad150may have a first width W1in a horizontal direction. The first lower pad150may be formed of or include at least one of metallic materials (e.g., copper (Cu), aluminum (Al), and/or nickel (Ni)).

The first semiconductor chip100may further include a lower protection layer. The lower protection layer may be disposed on the bottom surface of the first semiconductor chip100to cover the first circuit layer110. The first circuit layer110may be protected by the protection layer. The protection layer may expose a bottom surface of the first lower pad150, on the bottom surface of the first circuit layer110. The protection layer may be formed of or include, for example, silicon oxide (SiO) or silicon nitride (SiN).

An outer terminal160may be provided on the bottom surface of the first semiconductor chip100. The outer terminal160may be disposed on the first lower pad150. The outer terminal160may be electrically connected to the first circuit layer110and the first via120. In an embodiment, the outer terminal160may be disposed below the first via120. In this case, the first via120may be provided to penetrate the first circuit layer110and may be exposed to the outside of the first circuit layer110near the bottom surface of the first circuit layer110, and the outer terminal160may be directly coupled to the first via120. For example, the first lower pad150may not be provided below the first circuit layer110. The following description will be given based on the embodiment ofFIG.1. In an embodiment, a plurality of outer terminals160may be provided. In this case, the outer terminals160may be coupled to the first lower pads150, respectively. The outer terminal160may be formed of or include an alloy that contains at least one of tin (Sn), silver (Ag), copper (Cu), nickel (Ni), bismuth (Bi), indium (In), antimony (Sb), or cerium (Ce).

A chip stack may be disposed on the first semiconductor chip100. A width of the chip stack may be smaller than a width of the first semiconductor chip100in the horizontal direction. The chip stack may include a plurality of second semiconductor chips201and202. The second semiconductor chips201and202may be of the same type. For example, each of the second semiconductor chips201and202may be a memory chip. The chip stack may include lower semiconductor chips201, which are disposed on the first semiconductor chip100, and an upper semiconductor chip202, which is disposed on the lower semiconductor chips201. The lower semiconductor chips201and the upper semiconductor chip202may be sequentially disposed on the first semiconductor chip100. As an example, the upper semiconductor chip202may be the uppermost semiconductor chip in the chip stack, and the lower semiconductor chips201may be remaining semiconductor chips, which are placed below the upper semiconductor chip202. The lower semiconductor chips201may be sequentially disposed between the first semiconductor chip100and the upper semiconductor chip202.

A detailed structure of the lower semiconductor chips201will be described with reference to one lower semiconductor chip201. A width of the lower semiconductor chip201may be smaller than the width of the first semiconductor chip100in the horizontal direction. A second thickness T2of the lower semiconductor chip201may be smaller than the first thickness T1of the first semiconductor chip100in the vertical direction. The second thickness T2of the lower semiconductor chip201may range from 20 μm to 40 μm.

The lower semiconductor chip201may include a second circuit layer210, a second via220, a second upper pad230, a second protection layer240, and a second lower pad250.

The lower semiconductor chip201may have the second circuit layer210facing the first semiconductor chip100. The second circuit layer210may include the afore-described integrated circuit. For example, the second circuit layer210may include a memory circuit. For example, a bottom surface of the lower semiconductor chip201may be an active surface.

The second via220may be provided to vertically penetrate the lower semiconductor chip201in a direction from the second protection layer240toward the second circuit layer210. For example, the second via220may be extended toward a top surface of the lower semiconductor chip201and may be exposed to the outside of the lower semiconductor chip201near the top surface of the lower semiconductor chip201. The second via220may be extended toward the second circuit layer210and may be connected to the second circuit layer210. The second via220and the second circuit layer210may be electrically connected to each other. In an embodiment, a plurality of second vias220may be provided. An insulating layer may be provided to enclose the second via220. The insulating layer may be formed of or include at least one of silicon oxide (SiO), silicon nitride (SiN), silicon oxynitride (SiON), or low-k dielectric materials. According to another embodiment, a seed layer or a barrier layer may be provided to cover a side surface and a bottom surface of the second via220. The seed layer may be formed of or include, for example, gold (Au). The barrier layer may be formed of or include, for example, titanium nitride (TiN) or tantalum nitride (TaN).

The second upper pad230may be disposed on the top surface of the lower semiconductor chip201. The second upper pad230may be coupled to the second via220. In an embodiment, a plurality of second upper pads230may be provided. In this case, the second upper pads230may be coupled to the second vias220, respectively, and may be arranged in the same shape as the second vias220. The second upper pad230may be electrically connected to the second circuit layer210through the second via220. The second upper pad230may be formed of or include at least one of metallic materials (e.g., copper (Cu), aluminum (Al), and/or nickel (Ni)).

The second protection layer240may be disposed on the top surface of the lower semiconductor chip201to enclose the second upper pad230. The second protection layer240may expose the second upper pad230. A top surface of the second protection layer240and a top surface of the second upper pad230may be substantially flat and may be substantially coplanar with each other. According to another embodiment, the second upper pad230may have a protruding portion, which is extended to a level higher than the top surface of the second protection layer240in the vertical direction, or the second protection layer240may be extended to the top surface of the second upper pad230to cover an edge portion of the second upper pad230and expose a center portion of the second upper pad230. The lower semiconductor chip201may be protected by the second protection layer240. The second protection layer240may be formed of or include at least one of oxide, nitride, or oxynitride materials, which contain a semiconductor element included in the lower semiconductor chip201. For example, the second protection layer240may be formed of or include at least one of silicon oxide (SiO), silicon nitride (SiN), silicon oxynitride (SiON), or combinations thereof. The second protection layer240may be an insulating coating layer containing an epoxy resin, a solder resist layer, or a photosensitive resin layer.

The second lower pad250may be disposed on the bottom surface of the lower semiconductor chip201. For example, the second lower pad250may be disposed on a bottom surface of the second circuit layer210. The second lower pad250may be electrically connected to the second circuit layer210. The second lower pad250may have a second width W2in the horizontal direction. The second width W2of the second lower pad250may be smaller than the first width W1of the first lower pad150. In an embodiment, a plurality of second lower pads250may be provided. The second lower pad250may be formed of or include at least one of metallic materials (e.g., copper (Cu), aluminum (Al), and/or nickel (Ni)).

The lower semiconductor chip201may further include a lower protection layer. The lower protection layer may be disposed on the bottom surface of the lower semiconductor chip201to cover the second circuit layer210. The second circuit layer210may be protected by the protection layer. The protection layer on the bottom surface of the second circuit layer210may be provided to expose a bottom surface of the second lower pad250. The protection layer may be formed of or include silicon oxide (SiO) or silicon nitride (SiN).

The lower semiconductor chips201may have the same structure, for example, the elements have the same physical properties (e.g., size and shape) as each other.

Adjacent ones of the first and lower semiconductor chips100and201may be connected to each other by first chip terminals310. For example, the first chip terminals310may connect the first semiconductor chip100to the lowermost one of the lower semiconductor chips201of the chip stack and/or may connect adjacent ones of the lower semiconductor chips201to each other. For example, some of the first chip terminals310may be disposed between the first upper pad130of the first semiconductor chip100and the second lower pad250of the lowermost one of the lower semiconductor chips201. Some of the first chip terminals310may connect the first upper pad130to the second lower pad250. Others of the first chip terminals310, which are placed between the lower semiconductor chips201, may be disposed between the second upper pad230and the second lower pad250. In an embodiment, a plurality of first chip terminals310may be provided between the first semiconductor chip100and the lowermost one of the lower semiconductor chips201and between the lower semiconductor chips201. The first chip terminals310may electrically connect the first semiconductor chip100to the lower semiconductor chips201. A width of the first chip terminals310may be smaller than a width of the outer terminal160. The first chip terminals310may be solder balls that are formed of an alloy containing at least one of tin (Sn), silver (Ag), copper (Cu), nickel (Ni), bismuth (Bi), indium (In), antimony (Sb), or cerium (Ce).

First non-conductive layers410may be disposed between the first semiconductor chip100and the chip stack (i.e., between the first semiconductor chip100and the lowermost one of the lower semiconductor chips201) and between adjacent ones of the lower semiconductor chips201to enclose the first chip terminals310. Some of the first non-conductive layers410may be disposed between the first semiconductor chip100and the lowermost one of the lower semiconductor chips201to enclose the first chip terminal310. Others of the first non-conductive layers410may be disposed between adjacent ones of the lower semiconductor chips201to enclose the first chip terminals310. The first non-conductive layer410may have an extension portion, which is extruded to a region outside a side surface of the lower semiconductor chip201. The extension portion of the first non-conductive layer410may cover a portion of the side surface of the lower semiconductor chip201thereon. The first non-conductive layers410may be formed of or include an insulating material. For example, the first non-conductive layers410may include a non-conductive film (NCF) or a non-conductive paste (NCP). The first non-conductive layers410may be formed of or include an insulating polymer. For example, the first non-conductive layers410may be formed of or include an epoxy-based material, which does not contain any conductive particle. Since the first non-conductive layer410in use does not contain conductive particles, it may be possible to reduce the pitch of the first chip terminals310, without an electric short issue between adjacent ones of the first chip terminals310. In addition, since the first non-conductive layers410are used as under-fill layers filling a space between the first semiconductor chip100and the lowermost one of the lower semiconductor chips201and a space between adjacent ones of the lower semiconductor chips201, it may be possible to improve the mechanical durability of the first chip terminals310.

The upper semiconductor chip202may be disposed on the uppermost one of the lower semiconductor chips201. A width of the upper semiconductor chip202may be smaller than the width of the first semiconductor chip100in the horizontal direction. The width of the upper semiconductor chip202may be equal to the widths of the lower semiconductor chips201in the horizontal direction. Side surfaces of the lower semiconductor chips201may be coplanar to a side surface of the upper semiconductor chip202. For example, the semiconductor chips of the chip stack may be coplanar to each other. A third thickness T3of the upper semiconductor chip202may be equal to the second thickness T2of the lower semiconductor chip201in the vertical direction. The third thickness T3of the upper semiconductor chip202may be smaller than the first thickness T1of the first semiconductor chip100in the vertical direction. The third thickness T3of the upper semiconductor chip202may range from 20 μm to 40 μm. The upper semiconductor chip202may have substantially the same structure as the lower semiconductor chips201. For example, the upper semiconductor chip202may include the second circuit layer210facing the first semiconductor chip100, the second protection layer240opposite to the second circuit layer210, the second via220extended from the second protection layer240toward the second circuit layer210to penetrate the upper semiconductor chip202, the second upper pad230in the second protection layer240, and the second lower pad250on the second circuit layer210. The second circuit layer210may include a memory circuit. A width of the second upper pad230may be smaller than the first width W1of the first lower pad150in the horizontal direction. The second lower pad250of the upper semiconductor chip202may have a third width W3in the horizontal direction. The third width W3of the second lower pad250of the upper semiconductor chip202may be smaller than the first width W1of the first lower pad150in the horizontal direction. The third width W3of the second lower pad250of the upper semiconductor chip202may be equal to the second width W2of the second lower pad250of the lower semiconductor chips201in the horizontal direction.

According to an embodiment, the first thickness T1of the first semiconductor chip100may be greater than the second and third thicknesses T2and T3of the lower and upper semiconductor chips201and202of the chip stack in the vertical direction. Thus, even when many semiconductor chips201and202are provided in the chip stack, they may be more robustly supported by the first semiconductor chip100, and the first semiconductor chip100may not be damaged in a process of fabricating the semiconductor package (in particular, in a step of mounting the semiconductor chips201and202on the first semiconductor chip100). For example, it may be possible to realize a semiconductor package with improved structural stability.

According to an embodiment, the third thickness T3of the upper semiconductor chip202, which is the uppermost chip in the chip stack, may not be greater than the second thicknesses T2of the lower semiconductor chips201in the vertical direction, and thus, the chip stack may have a relatively small height. Furthermore, the chip stack in the semiconductor package may be required to have a specific height, and in this case, since the third thickness T3of the upper semiconductor chip202is relatively small, it may be possible to increase the number of the semiconductor chips201and202provided in the chip stack. For example, it may be possible to realize a semiconductor package with a relatively small size and a relatively high integration density.

According to an embodiment, the upper semiconductor chip202, which is the uppermost chip in the chip stack, may have the second vias220vertically penetrating the upper semiconductor chip202. Thus, heat, which is generated from the semiconductor chips201and202in the chip stack, may be more easily exhausted to a region on the chip stack through the upper semiconductor chip202and the second vias220in the upper semiconductor chip202. For example, it may be possible to improve the heat-dissipation efficiency of the semiconductor package.

Referring further toFIGS.1to3, the upper semiconductor chip202and the uppermost one of the lower semiconductor chips201may be connected to each other by a second chip terminal320. For example, the second chip terminal320may be disposed between the second upper pad230of the uppermost one of the lower semiconductor chips201and the second lower pad250of the upper semiconductor chip202. The second chip terminal320may connect the second upper pad230to the second lower pad250. In an embodiment, a plurality of second chip terminals320may be provided between the uppermost one of the lower semiconductor chips201and the upper semiconductor chip202. The second chip terminal320may electrically connect the uppermost one of the lower semiconductor chips201to the upper semiconductor chip202. A width of the second chip terminals320may be smaller than a width of the outer terminal160in the horizontal direction. The second chip terminals320may be solder balls that are formed of an alloy containing at least one of tin (Sn), silver (Ag), copper (Cu), nickel (Ni), bismuth (Bi), indium (In), antimony (Sb), or cerium (Ce).

A second non-conductive layer420may be disposed between the uppermost one of the lower semiconductor chips201and the upper semiconductor chip202to enclose the second chip terminal320. The second non-conductive layer420may have an extension portion, which is extruded to a region outside the side surface of the upper semiconductor chip202. The extension portion of the second non-conductive layer420may cover a portion of the side surface of the upper semiconductor chip202thereon. The second non-conductive layer420may include an insulating material. For example, the second non-conductive layer420may include a non-conductive film (NCF) or a non-conductive paste (NCP). The second non-conductive layer420may include an insulating polymer. For example, the second non-conductive layer420may be formed of or include an epoxy-based material, which does not contain any conductive particle. Since the second non-conductive layer420in use does not contain conductive particles, it may be possible to reduce the pitch of the second chip terminals320, without an electric short issue between adjacent ones of the second chip terminals320. In addition, since the second non-conductive layer420is used as an under-fill layer filling a space between the uppermost one of the lower semiconductor chips201and the upper semiconductor chip202, it may be possible to improve the mechanical durability of the second chip terminals320.

A mold layer500may be provided on the first semiconductor chip100. The mold layer500may cover the top surface of the first semiconductor chip100. A side surface of the mold layer500may be coplanar to a side surface of the first semiconductor chip100. The mold layer500may enclose the chip stack. For example, the mold layer500may cover the side surfaces of the second semiconductor chips201and202. The mold layer500may expose a top surface of the upper semiconductor chip202. The mold layer500may protect the second semiconductor chips201and202. The mold layer500may include an insulating material. For example, the mold layer500may include an epoxy molding compound (EMC). Unlike the illustrated structure, the mold layer500may be formed to cover the second semiconductor chips201and202. For example, the mold layer500may cover the top surface of the upper semiconductor chip202.

In the description of the embodiments to be explained below, an element previously described with reference toFIGS.1and2may be identified by the same reference number without repeating an overlapping description thereof, for concise description.

FIG.4is a sectional view illustrating a semiconductor package according to an embodiment.FIG.5is an enlarged sectional view of a portion ‘C’ ofFIG.4.

Referring toFIGS.4and5, the upper semiconductor chip202may be disposed on the uppermost one of the lower semiconductor chips201. The width of the upper semiconductor chip202may be smaller than the width of the first semiconductor chip100in the horizontal direction. The width of the upper semiconductor chip202may be equal to the widths of the lower semiconductor chips201in the horizontal direction. The semiconductor chips of the chip stack may be vertically aligned to each other. The third thickness of the upper semiconductor chip202may be equal to the second thickness of the lower semiconductor chip201in the vertical direction. The third thickness of the upper semiconductor chip202may be smaller than the first thickness of the first semiconductor chip100in the vertical direction. The upper semiconductor chip202may have a structure that is substantially similar to the lower semiconductor chips201. For example, the upper semiconductor chip202may include the second circuit layer210facing the first semiconductor chip100, the second protection layer240opposite to the second circuit layer210, and the second lower pad250on the second circuit layer210. For example, the upper semiconductor chip202may not have the second via220, which is provided to vertically penetrate the upper semiconductor chip202, and the second upper pad230, which is provided in the second protection layer240, unlike the lower semiconductor chips201. For example, the upper semiconductor chip202may have a relatively simpler structure than the lower semiconductor chips201.

In an embodiment, it may be possible to realize a semiconductor package with a relatively small size, a relatively high integration density, and a relatively simple structure.

FIG.6is a sectional view illustrating a semiconductor package according to an embodiment.FIG.7is an enlarged sectional view of a portion ‘D’ ofFIG.6.FIG.8is an enlarged sectional view of a portion ‘E’ ofFIG.6.

Referring toFIGS.6to8, the upper semiconductor chip202may be disposed on the uppermost one of the lower semiconductor chips201. The third thickness T3of the upper semiconductor chip202may be smaller than the second thickness T2of the lower semiconductor chip201in the vertical direction. For example, the upper semiconductor chip202, which is the uppermost chip in the chip stack, may be the thinnest semiconductor chip. The third thickness T3of the upper semiconductor chip202may be smaller than the first thickness T1of the first semiconductor chip100in the vertical direction. The upper semiconductor chip202may have substantially the same structure as the lower semiconductor chips201. For example, the upper semiconductor chip202may include the second circuit layer210facing the first semiconductor chip100, the second protection layer240opposite to the second circuit layer210, the second via220extended from the second protection layer240toward the second circuit layer210to penetrate the upper semiconductor chip202, the second upper pad230in the second protection layer240, and the second lower pad250on the second circuit layer210.

In an embodiment, the third thickness T3of the upper semiconductor chip202, which is the uppermost chip in the chip stack, may be smaller than the second thicknesses T2of the lower semiconductor chips201in the vertical direction, and thus, the chip stack may have a relatively small height. Furthermore, since the third thickness T3of the upper semiconductor chip202is relatively small, it may be possible to increase the number of the semiconductor chips201and202provided in the chip stack. For example, it may be possible to realize a semiconductor package with a relatively small size and a relatively high integration density.

FIG.9is a sectional view illustrating a semiconductor package according to an embodiment.

FIGS.1to8illustrate examples, in which the lower semiconductor chips201and the upper semiconductor chip202are mounted on the first semiconductor chip100and the lower semiconductor chips201using the chip terminals310and320, but embodiments are not limited thereto.

Referring toFIG.9, adjacent ones of the lower semiconductor chips201may be directly connected to each other. For example, the lower semiconductor chips201, which are vertically adjacent to each other, may be directly connected to each other.

The second upper pad230and the second lower pad250, which are respectively included in the adjacent ones of the lower semiconductor chips201, may be in direct contact with each other. Here, the second upper pad230and the second lower pad250may form an inter-metal hybrid bonding structure. In the present specification, the hybrid bonding structure may be a bonding structure which is formed by two materials, which are of the same type and are fused at an interface therebetween. For example, the second upper pad230and the second lower pad250, which are bonded to each other, may have a continuous structure, and there may be no visible interface between the second upper pad230and the second lower pad250. For example, the second upper pad230and the second lower pad250may be formed of the same material, and thus, there may be no interface between the second upper pad230and the second lower pad250. For example, the second upper pad230and the second lower pad250may be provided as a single element. For example, the second upper pad230and the second lower pad250may be coupled to each other to form a single object.

The first non-conductive layers410may be disposed between the lower semiconductor chips201, which are adjacent to each other. The first non-conductive layers410between adjacent ones of the lower semiconductor chips201may enclose the second upper pad230and the second lower pad250.

The upper semiconductor chip202and the uppermost one of the lower semiconductor chips201may be directly connected to each other.

The second upper pad230of the uppermost one of the lower semiconductor chips201may be in direct contact with the second lower pad250of the upper semiconductor chip202. Here, the second upper pad230and the second lower pad250may form an inter-metal hybrid bonding structure. For example, the second upper pad230and the second lower pad250, which are bonded to each other, may have a continuous structure, and there may be no visible interface between the second upper pad230and the second lower pad250. For example, the second upper pad230and the second lower pad250may be formed of the same material, and thus, there may be no interface between the second upper pad230and the second lower pad250. In other words, the second upper pad230and the second lower pad250may be provided as a single element. For example, the second upper pad230and the second lower pad250may be coupled to each other to form a single object.

The second non-conductive layer420may be disposed between the uppermost one of the lower semiconductor chips201and the upper semiconductor chip202. The second non-conductive layer420may be disposed between the uppermost one of the lower semiconductor chips201and the upper semiconductor chip202to enclose the second upper pad230and the second lower pad250.

In an embodiment, the pads230and250of the second semiconductor chips201and202may be directly connected to each other. For example, the pads230and250of the second semiconductor chips201and202may be connected to each other without additional chip terminals, and a distance between the second semiconductor chips201and202may be relatively small. For example, it may be possible to realize a semiconductor package with a relatively small size.

The first semiconductor chip100and the chip stack may be directly connected to each other. For example, the first semiconductor chip100may be directly connected to the lowermost one of the lower semiconductor chips201of the chip stack.

The first upper pad130of the first semiconductor chip100may be in direct contact with the second lower pad250of the lowermost one of the lower semiconductor chips201. Here, the first upper pad130and the second lower pad250may form an inter-metal hybrid bonding structure. For example, the first upper pad130and the second lower pad250, which are bonded to each other, may have a continuous structure, and there may be no visible interface between the first upper pad130and the second lower pad250. For example, the first upper pad130and the second lower pad250may be formed of the same material, and thus, there may be no interface between the first upper pad130and the second lower pad250. For example, the first upper pad130and the second lower pad250may be provided as a single element. For example, the first upper pad130and the second lower pad250may be coupled to each other to form a single object.

A portion of the first non-conductive layer410may be disposed between the first semiconductor chip100and the chip stack. The portion of the first non-conductive layer410may be disposed between the first semiconductor chip100and the lowermost one of the lower semiconductor chips201to enclose the first upper pad130and the second lower pad250.

FIG.9illustrates an example, in which the chip stack is directly connected to the first semiconductor chip100, but embodiments are not limited thereto. The chip stack may be mounted on the first semiconductor chip100using additional connection terminals. For example, while the semiconductor chips201and202of the chip stack are directly connected to each other, the lowermost one of the lower semiconductor chips201may be coupled to the first upper pad130of the first semiconductor chip100using a chip connection terminal provided on the second lower pad250.

FIG.10is a sectional view illustrating a semiconductor package according to an embodiment.

Referring toFIG.10, each of the lower semiconductor chips201may include the second circuit layer210, the second via220, the second upper pad230, the second protection layer240, and the second lower pad250.

The top surface of the second protection layer240and the top surface of the second upper pad230may be substantially flat and may be substantially coplanar with each other.

The second lower pads250may be disposed on bottom surfaces of the lower semiconductor chips201. For example, the second lower pad250may be disposed in the second circuit layer210. The bottom surface of the second lower pad250and the bottom surface of the second circuit layer210may be substantially flat and may be substantially coplanar with each other. The second lower pad250may be electrically connected to the second circuit layer210.

The lower semiconductor chips201, which are adjacent to each other, may be in direct contact with each other. In an embodiment, a top surface of the lower semiconductor chip201may be in full contact with the bottom surface of another lower semiconductor chip201thereon.

On an interface between the lower semiconductor chips201, the second protection layer240of the lower semiconductor chip201may be bonded to an insulating pattern of the second circuit layer210of another lower semiconductor chip201thereon. Here, the second protection layer240and the insulating pattern of the second circuit layer210may form a hybrid bonding structure of oxide, nitride, or oxynitride. For example, the second protection layer240and the insulating pattern of the second circuit layer210may be formed of the same material, and thus, there may be no interface between the second protection layer240and the insulating pattern of the second circuit layer210. For example, the second protection layer240and the insulating pattern of the second circuit layer210may be coupled to each other to form a single object. However, embodiments are not limited thereto. The second protection layer240and the insulating pattern of the second circuit layer210may be formed of different materials from each other and may not have a continuous structure, and thus, there may be a visible interface between the second protection layer240and the insulating pattern of the second circuit layer210.

On the interface between the lower semiconductor chips201, the second upper pad230and the second lower pad250, which are respectively included in the adjacent ones of the lower semiconductor chips201, may be in direct contact with each other. Here, the second upper pad230and the second lower pad250may form an inter-metal hybrid bonding structure. For example, the second upper pad230and the second lower pad250, which are bonded to each other, may have a continuous structure, and there may be no visible interface between the second upper pad230and the second lower pad250.

The upper semiconductor chip202may include the second circuit layer210, the second via220, the second upper pad230, the second protection layer240, and the second lower pad250.

The second lower pad250may be disposed in the second circuit layer210. The bottom surface of the second lower pad250and the bottom surface of the second circuit layer210may be substantially flat and may be substantially coplanar with each other.

The uppermost one of the lower semiconductor chips201may be in direct contact with the upper semiconductor chips202. In an embodiment, a top surface of the uppermost one of the lower semiconductor chips201may be entirely in contact with a bottom surface of the upper semiconductor chip202.

On an interface between the uppermost one of the lower semiconductor chips201and the upper semiconductor chip202, the second protection layer240of the uppermost one of the lower semiconductor chips201may be bonded to the insulating pattern of the second circuit layer210of the upper semiconductor chip202. Here, the second protection layer240and the insulating pattern of the second circuit layer210may form a hybrid bonding structure of oxide, nitride, or oxynitride. For example, the second protection layer240and the insulating pattern of the second circuit layer210may be formed of the same material, and thus, there may be no interface between the second protection layer240and the insulating pattern of the second circuit layer210. For example, the second protection layer240and the insulating pattern of the second circuit layer210may be coupled to each other to form a single object. However, embodiments are not limited thereto. The second protection layer240and the insulating pattern of the second circuit layer210may be formed of different materials from each other and may not have a continuous structure, and thus, there may be a visible interface between the second protection layer240and the insulating pattern of the second circuit layer210.

On the interface between the uppermost one of the lower semiconductor chips201and the upper semiconductor chip202, the second upper pad230of the uppermost one of the lower semiconductor chips201may be in direct contact with the second lower pad250of the upper semiconductor chip202. Here, the second upper pad230and the second lower pad250may form an inter-metal hybrid bonding structure. For example, the second upper pad230and the second lower pad250, which are bonded to each other, may have a continuous structure, and there may be no visible interface between the second upper pad230and the second lower pad250.

According to an embodiment, the second semiconductor chips201and202may be entirely in contact with each other. Thus, a distance between the second semiconductor chips201and202may be zero and it may be possible to realize a semiconductor package with a relatively small size.

The first semiconductor chip100and the chip stack may be in direct contact with each other. For example, the top surface of the first semiconductor chip100may be entirely in contact with the bottom surface of the lowermost one of the lower semiconductor chips201of the chip stack.

On the interface between the first semiconductor chip100and the lowermost one of the lower semiconductor chips201, the first protection layer140of the first semiconductor chip100may be bonded to the insulating pattern of the second circuit layer210of the lowermost one of the lower semiconductor chips201. Here, the first protection layer140and the insulating pattern of the second circuit layer210may form a hybrid bonding structure of oxide, nitride, or oxynitride. For example, the first protection layer140and the insulating pattern of the second circuit layer210may be formed of the same material, and thus, there may be no interface between the first protection layer140and the insulating pattern of the second circuit layer210. For example, the first protection layer140and the insulating pattern of the second circuit layer210may be coupled to each other to form a single object. However, embodiments are not limited thereto. The first protection layer140and the insulating pattern of the second circuit layer210may be formed of different materials from each other and may not have a continuous structure, and thus, there may be a visible interface between the first protection layer140and the insulating pattern of the second circuit layer210.

On the interface between the first semiconductor chip100and the lowermost one of the lower semiconductor chips201, the first upper pad130of the first semiconductor chip100may be in direct contact with the second lower pad250of the lowermost one of the lower semiconductor chips201. Here, the first upper pad130and the second lower pad250may form an inter-metal hybrid bonding structure. For example, the first upper pad130and the second lower pad250, which are bonded to each other, may have a continuous structure, and there may be no visible interface between the first upper pad130and the second lower pad250.

FIG.10illustrates an example, in which the chip stack is in direct contact with the first semiconductor chip100, but embodiments are not limited thereto. The chip stack may be mounted on the first semiconductor chip100using additional connection terminals. For example, while the semiconductor chips201and202of the chip stack are directly connected to each other, the lowermost one of the lower semiconductor chips201may be coupled to the first upper pad130of the first semiconductor chip100using a chip connection terminal provided on the second lower pad250.

FIG.11is a sectional view illustrating a semiconductor package according to an embodiment.

FIGS.1to10illustrate the embodiments, in which three lower semiconductor chips201are interposed between the first semiconductor chip100and the upper semiconductor chip202or the chip stack has four semiconductor chips, but the inventive concept is not limited to these embodiments. As shown inFIG.11, seven lower semiconductor chips201may be interposed between the first semiconductor chip100and the upper semiconductor chip202. According to embodiments, one, two, four, or more lower semiconductor chips201may be interposed between the first semiconductor chip100and the upper semiconductor chip202. For example, 3 to 15 lower semiconductor chips201may be provided between the first semiconductor chip100and the upper semiconductor chip202, and the chip stack may have 4 to 16 semiconductor chips.

FIG.12is a sectional view illustrating a semiconductor module according to an embodiment.

Referring toFIG.12, a semiconductor module may be a memory module and may include a module substrate610, a chip stack package630and a graphic processing unit (GPU)640, which are mounted on the module substrate610, and an outer mold layer650, which is provided to cover the chip stack package630and the graphic processing unit640. The semiconductor module may further include an interposer620provided on the module substrate610.

The module substrate610may be provided. The module substrate610may include a printed circuit board (PCB) having signal patterns, which are formed on a top surface of the module substrate610.

Module terminals612may be disposed below the module substrate610. The module substrate610may include solder balls or solder bumps, and the semiconductor module may be classified into a ball grid array (BGA) type, a fine ball-grid array (FBGA) type, or a land grid array (LGA) type, depending on the type and structure of the module substrate610.

The interposer620may be provided on the module substrate610. The interposer620may include first substrate pads622and second substrate pads624, which are respectively placed on top and bottom surfaces of the interposer620. The interposer620may be configured to provide a redistribution structure for the chip stack package630and the graphic processing unit640. The interposer620may be mounted on the module substrate610in a flip chip manner. For example, the interposer620may be mounted on the module substrate610using substrate terminals626, which are provided on the second substrate pads624. The substrate terminals626may include solder balls or solder bumps. A first under-fill layer628may be provided between the module substrate610and the interposer620.

The chip stack package630may be disposed on the interposer620. The chip stack package630may have the same or similar structure as the semiconductor package described with reference toFIGS.1to11.

The chip stack package630may be mounted on the interposer620. For example, the chip stack package630may be coupled to the first substrate pads622of the interposer620through the outer terminals160of the first semiconductor chip100. A second under-fill layer170may be provided between the chip stack package630and the interposer620. The second under-fill layer170may be provided to fill a space between the interposer620and the first semiconductor chip100and enclose the outer terminals160of the first semiconductor chip100.

The graphic processing unit640may be disposed on the interposer620. The graphic processing unit640may be disposed to be spaced apart from the chip stack package630. The graphic processing unit640may be thicker than the semiconductor chips100,201, and202of the chip stack package630in the vertical direction. A chip circuit layer642may be provided on a bottom surface of the graphic processing unit640. The chip circuit layer642of the graphic processing unit640may include a logic circuit. For example, the graphic processing unit640may be a logic chip. Chip pads644may be provided on the bottom surface of the graphic processing unit640. The chip pads644may be disposed on a bottom surface of the chip circuit layer642and may be electrically connected to the chip circuit layer642. Bumps646may be provided on the chip pads644. For example, the graphic processing unit640may be coupled to the first substrate pads622of the interposer620through the bumps646. A third under-fill layer648may be provided between the interposer620the graphic processing unit640. The third under-fill layer648may be provided to fill a space between the interposer620and the graphic processing unit640and enclose the bumps646.

The outer mold layer650may be provided on the interposer620. The outer mold layer650may cover the top surface of the interposer620. The outer mold layer650may enclose the chip stack package630and the graphic processing unit640. A top surface of the outer mold layer650may be located at the same level as a top surface of the chip stack package630in the vertical direction. The outer mold layer650may include an insulating material. For example, the outer mold layer650may include an epoxy molding compound (EMC).

FIGS.13to20are sectional views illustrating a method of fabricating a semiconductor package, according to an embodiment of the inventive concept.

Referring toFIG.13, a first wafer1000may be provided. The first wafer1000may have a top surface and a bottom surface, which are opposite to each other. For example, the first wafer1000may be a silicon wafer or a non-silicon semiconductor wafer. The first wafer1000may have device regions DR, which are spaced apart from each other. The device regions DR may be divided by a first sawing line SL1, on which a sawing process will be performed. Each of the device regions DR may be a region, in which one second semiconductor chip201or202(e.g., seeFIG.16) will be formed.

The first wafer1000may be provided on a first carrier substrate900. The first carrier substrate900may be an insulating substrate, which includes glass or polymer, or a conductive substrate, which includes a metallic material. An adhesive member may be provided on a top surface of the first carrier substrate900. In an embodiment, the adhesive member may include an adhesive tape.

A second circuit layer1010may be formed on the first wafer1000. The second circuit layer1010may include an electronic element (e.g., a transistor). For example, the second circuit layer1010may be formed using a typical process, such as a doping process, a deposition process, a patterning process. For example, a top surface of the first wafer1000, on which the second circuit layer1010is formed, may be an active surface of the first wafer1000.

Second lower pads1050may be formed on the second circuit layer1010. The second lower pads1050may be electrically connected to the second circuit layer1010.

Referring toFIG.14, the first carrier substrate900may be removed. Accordingly, an inactive surface of the first wafer1000may be exposed.

The first wafer1000may be provided on a second carrier substrate910. The second carrier substrate910may be an insulating substrate, which includes glass or polymer, or a conductive substrate, which includes a metallic material. An adhesive member912may be provided on a top surface of the second carrier substrate910. As an example, the adhesive member912may include an adhesive tape. The first wafer1000may be attached to the second carrier substrate910such that the second circuit layer1010faces the second carrier substrate910. If necessary, a thinning process may be performed on the inactive surface of the first wafer1000.

Second vias1020may be formed in the first wafer1000. For example, the second vias1020may be formed by forming penetration holes to vertically penetrate the first wafer1000and filling the penetration holes with a conductive material.

Second upper pads1030may be formed on the first wafer1000. For example, the second upper pads1030may be formed by forming a conductive layer on the inactive surface of the first wafer1000and patterning the conductive layer. The second upper pads1030may be formed on the second vias1020and may be coupled to the second vias1020.

A second protection layer1040may be formed on the first wafer1000. The second protection layer1040may enclose the second upper pads1030.

As described above, the second semiconductor chips201and202may be formed on the device regions DR of the first wafer1000. In the embodiment ofFIG.14, the lower and upper semiconductor chips201and202, which are included in the second semiconductor chips201and202, are illustrated to have the same elements, but embodiments are not limited thereto.

In another embodiment, the first carrier substrate900may be removed, as shown inFIG.15. The first wafer1000may be provided on the second carrier substrate910. The second vias1020, the second upper pads1030, and the second protection layer1040may be formed on the first wafer1000. Here, the second vias1020, the second upper pads1030, and the second protection layer1040may be formed only on a device region DR1, which is one of the device regions DR, not on another device region DR2. The lower semiconductor chip201may be formed on the device region DR1provided with the second vias1020, the second upper pads1030, and the second protection layer1040, and the upper semiconductor chip202may be formed on the device region DR2, in which the second vias1020, the second upper pads1030, and the second protection layer1040are not formed. The following description will be given based on the embodiment ofFIG.14.

Referring toFIG.16, a singulation process may be performed on the first wafer1000to separate the second semiconductor chips201and202from each other. For example, a sawing process may be performed along the first sawing line SL1. Some of the second semiconductor chips201and202, which are separated from each other, may be the lower semiconductor chips201, and the others may be the upper semiconductor chips202. Since the lower and upper semiconductor chips201and202are formed using the same wafer (i.e., the first wafer1000), the lower and upper semiconductor chips201and202may have the same thickness. The second circuit layer1010of the first wafer1000may be divided into the second circuit layers210of the second semiconductor chips201and202. The second protection layer1040of the first wafer1000may be divided into the second protection layers240of the second semiconductor chips201and202. The second lower pads1050, the second vias1020, and the second upper pads1030of the first wafer1000may correspond to the second lower pads250, the second vias220, and the second upper pads230of the second semiconductor chips201and202, respectively.

Referring toFIG.17, a second wafer1100may be provided. The second wafer1100may have a top surface and a bottom surface, which are opposite to each other. For example, the second wafer1100may be a silicon wafer or a non-silicon semiconductor wafer. In an embodiment, not a wafer but a printed circuit board (PCB) may be provided. A thickness of the second wafer1100may be greater than a thickness of the first wafer1000. The second wafer1100may include a first circuit layer1110, a first protection layer1140opposite to the first circuit layer1110, first vias1120, which are extended from the first protection layer1140toward the first circuit layer1110to penetrate the second wafer1100, first upper pads1130in the first protection layer1140, and a first lower pad1150on the first circuit layer1110.

The second wafer1100may be provided on a third carrier substrate920. The third carrier substrate920may be an insulating substrate, which includes glass or polymer, or a conductive substrate, which includes a metallic material. An adhesive member922may be provided on a top surface of the third carrier substrate920. As an example, the adhesive member922may include an adhesive tape. The second wafer1100may be attached to the third carrier substrate920such that the first circuit layer1110faces the third carrier substrate920.

Referring toFIG.18, a plurality of lower semiconductor chips201may be provided on the second wafer1100. Each of the lower semiconductor chips201may be one of the semiconductor chips, which are fabricated by the method described with reference toFIGS.13to16. The first chip terminals310and the first non-conductive layers410enclosing them may be provided on the bottom surfaces of the lower semiconductor chips201. For example, the first non-conductive layers410may include a non-conductive film (NCF) or a non-conductive paste (NCP). In the case where the first non-conductive layers410are the non-conductive paste, the first non-conductive layers410may be formed by coating a liquid non-conductive paste on the lower semiconductor chips201through a dispensing process. In the case where the first non-conductive layers410are the non-conductive film, the first non-conductive layers410may be formed by attaching the non-conductive films to the lower semiconductor chips201. In other words, the first non-conductive layers410may be provided on the second wafer1100, and the lower semiconductor chips201may be provided on the first non-conductive layers410.

Referring toFIG.19, the lower semiconductor chips201may be bonded to the second wafer1100through a thermocompression bonding process. The first chip terminals310may electrically connect the second wafer1100to the lower semiconductor chips201. In an embodiment, a width of a bonding tool2000, which is used in the bonding process, may be smaller than a width of the lower semiconductor chip201in the horizontal direction. In the case where the lower semiconductor chips201are compressed toward the second wafer1100, the first non-conductive layers410may be extruded to a region outside the side surfaces of the lower semiconductor chips201. The extruded portion of the first non-conductive layer410may form an extension portion. Here, the extension portion may be extended to the side surface of the lower semiconductor chip201to cover at least a portion of the side surface of the lower semiconductor chip201. A thickness of the extension portion may be greater than a distance between the second wafer1100and the lower semiconductor chips201in the vertical direction.

Referring toFIG.20, the process steps described with reference toFIGS.18and19may be repeated to stack a plurality of lower semiconductor chips201on the second wafer1100. Other lower semiconductor chips201may be disposed on and bonded to the lower semiconductor chips201, which are disposed on the second wafer1100. The first chip terminals310may electrically connect the lower semiconductor chips201to each other.

Next, the upper semiconductor chips202may be disposed on the lower semiconductor chips201. Each of the upper semiconductor chips202may be one of the semiconductor chips, which are fabricated by the method described with reference toFIGS.13to16. The process of stacking the upper semiconductor chips202may be the same as or similar to the process described with reference toFIGS.18and19. For example, the second chip terminals320and the second non-conductive layer420enclosing them may be provided on the bottom surfaces of the upper semiconductor chips202. In the case where the second non-conductive layer420is a non-conductive paste, the second non-conductive layer420may be formed by coating a liquid non-conductive paste on the upper semiconductor chips202through a dispensing process. In the case where the second non-conductive layer420is a non-conductive film, the second non-conductive layer420may be formed by attaching the non-conductive film to the upper semiconductor chips202. For example, the second non-conductive layer420may be provided on the uppermost one of the lower semiconductor chips201, and the upper semiconductor chips202may be provided on the second non-conductive layer420.

The upper semiconductor chips202may be bonded to the uppermost one of the lower semiconductor chips201through a thermocompression bonding process. The second chip terminals320may electrically connect the uppermost one of the lower semiconductor chips201to the upper semiconductor chips202. As described above, the lower semiconductor chips201and the upper semiconductor chips202may be sequentially disposed on the second wafer1100. The lower and upper semiconductor chips201and202may constitute chip stacks.

Referring toFIGS.20and1, the mold layer500may be formed on the second wafer1100. The mold layer500may cover the chip stacks. The mold layer500may enclose the lower semiconductor chips201, the upper semiconductor chips202, and non-conductive layers410and420on the second wafer1100. For example, the mold layer500may be formed by forming an insulating layer on the second wafer1100to cover the chip stacks and curing the insulating layer. After the formation of the mold layer500, a planarization process may be performed on the mold layer500to expose the top surfaces of the upper semiconductor chips202, if necessary.

Next, a singulation process may be performed on the mold layer500and the second wafer1100to form semiconductor packages, which are separated from each other. For example, a sawing process may be performed along a second sawing line SL2. The sawing process may be performed to cut the mold layer500and the second wafer1100between the chip stacks.

In a semiconductor package according to an embodiment, a thickness of a base substrate may be greater than thicknesses of semiconductor chips of a chip stack in the vertical direction. Thus, even when many semiconductor chips are provided in the chip stack, they may be more robustly supported by the base substrate, and the base substrate may not be damaged in a process of fabricating the semiconductor package (in particular, in a step of mounting the semiconductor chips on the base substrate). It may be possible to realize a semiconductor package with improved structural stability.

Furthermore, the uppermost semiconductor chip of the chip stack may not be thicker than the remaining ones of the semiconductor chips in the vertical direction, and thus, a height of the chip stack may be reduced. The chip stack in the semiconductor package may be required to have a specific height, and in this case, due to the relatively small thickness of the uppermost semiconductor chip, it may be possible to increase the number of the semiconductor chips provided in the chip stack. It may be possible to realize a semiconductor package with a relatively small size and a relatively high integration density.

In an embodiment, the uppermost semiconductor chip of the chip stack may have vias, which are provided to vertically penetrate the same. In this case, heat, which is generated from the semiconductor chips in the chip stack, may be easily exhausted to a region on the chip stack through the uppermost semiconductor chip and the vias therein. That is, it may be possible to improve the heat-dissipation efficiency of the semiconductor package.

In an embodiment, it may be possible to realize a semiconductor package with a relatively small size, a relatively high integration density, and a relatively simple structure.