Application processor for adjusting clock signal using hardware power management unit and devices including the same

An application processor includes a central processing unit (CPU), intellectual properties (IPs), a hardware power management unit (PMU) configured to determine whether the application processor is in system idle based on a first idle signal output from the CPU and output control signals as a result of the determination, and a clock signal supply control circuit configured to change an output signal supplied to the CPU and the IPs from clock signals to an oscillation clock signal, based on the control signals. The oscillation clock signal has a frequency lower than that of the clock signals.

CROSS-REFERENCE TO THE RELATED APPLICATIONS

This application claims priority from Korean Patent Application No. 10-2014-0115932 filed on Sep. 2, 2014, the disclosure of which is incorporated herein in its entirety by reference.

BACKGROUND

Apparatuses and methods consistent with exemplary embodiments of the inventive concept relate to an integrated circuit, and more particularly, to an application processor for changing a clock signal used in an integrated circuit into a clock signal of an oscillator using a hardware power management unit when the integrated circuit is in system idle and devices including the same.

Dynamic voltage and frequency scaling (DVFS) is a technique whereby an operating frequency and an operation voltage are dynamically adjusted. Electronic systems can reduce unnecessary power consumption using DVFS. In most commonly used DVFS, the usage of a target circuit is periodically checked and an operating frequency and voltage applied to the target circuit are adjusted according to the check result to reduce unnecessary power consumption of the target circuit.

DVFS performed based on a result of checking the usage of a target circuit during the operation of an electronic system including the target circuit can reduce current consumption at the electronic system to some extent and sustain the performance of the electronic system. However, when DVFS is performed based on the result of checking the usage of the target circuit while the electronic system is in a system idle state, DVFS itself adversely affects current consumption at the electronic system. Recently, a system on chip (SoC) supports a low-power mode in order to increase the use time of batteries. When a central processing unit (CPU) periodically wakes up in a SoC using the low-power mode in order to perform DVFS, power consumption of the CPU takes a significantly large part of the entire power consumption of the SoC.

SUMMARY

Exemplary embodiments of the inventive concept provide an application processor which supplies a clock signal of an oscillator instead of a clock signal used in an integrated circuit by using a hardware power management unit when the integrated circuit is in system idle, and devices including the same

According to some exemplary embodiments of the inventive concept, there is provided an application processor which may include a central processing unit (CPU), intellectual properties (IPs), a hardware power management unit (PMU) configured to determine whether the application processor is in system idle based on a first idle signal output from the CPU and output control signals as a result of the determination, and a clock signal supply control circuit configured to change an output signal supplied to the CPU and the IPs from clock signals to an oscillation clock signal, based on the control signals. The oscillation clock signal has a frequency lower than that of the clock signals.

Each of the IPs may transmit a second idle signal to the hardware PMU, and the hardware PMU is configured to output the control signals based on the first idle signal and the second idle signal.

The CPU may detect whether each of the CPU and the IPs is in an idle state and may transmit the first idle signal to the hardware power management unit.

The first idle signal may be set by the CPU in a register included in the hardware power management unit and the hardware power management unit may output the control signals based on the first idle signal set in the register. The first idle signal may indicate whether each of the IPs has been power-gated.

According to other exemplary embodiments of the inventive concept, there is provided a system on chip (SoC) which may include at least one first type IP comprising a CPU, at least one second type IP, a PMU configured to determine whether the SoC is in system idle based on an operating state of the first type IP and generate a control signal as a result of the determination, and a clock signal supply control circuit configured to change an output signal supplied to the at least one first type IP from a first clock signal to an oscillation clock signal, based on the control signal. The oscillation clock signal may have a frequency lower than that of the first clock signal.

The at least one first type IP may include a plurality of first type IPs. Each of the first type IPs may transmit an idle signal to the hardware power management unit. The hardware power management unit may determine the operating states of the first type IPs based on the idle signal from each first type IP and may output the control signal as a result of the determination of the operating states.

The system on chip may further include exclusive lines configured to transmit the idle signal from each of the first type IPs to the hardware power management unit.

The CPU may detect its operating state and an operating state of each of the other first type IPs and transmit detection information to the hardware power management unit. The hardware power management unit may determine the operating state of the first type IPs based on the detection information and output the control signal as a result of the determination of the operating states.

The detection information may be set by the CPU in a register included in the hardware power management unit. The hardware power management unit may output the control signal based on the detection information set in the register.

The operating state of each of the first type IPs except for the CPU may indicate whether each first type IP has been power-gated. The hardware power management unit may output the control signal based on an idle signal from the CPU and whether each of the first type IPs except for the CPU has been power-gated.

The clock signal supply control circuit may include an oscillator configured to generate the oscillation clock signal and a clock signal generator configured to generate the first clock signal. The clock signal supply control circuit may turn off the clock signal generator after the oscillation clock signal is applied to the at least one first type IP.

The clock signal supply control circuit may further include a plurality of selectors. One of the selectors may apply one of the first clock signal and the oscillation clock signal to one of the at least one first type IP in response to one of selection signals output from the hardware power management unit.

The hardware power management unit may turn on the clock signal generator, which has been turned off, in response to an interrupt signal and may apply the first clock signal to the at least one first type IP.

The hardware power management unit may maintain second clock signal applied to the second type IP in response to the control signal. The frequency of the oscillation clock signal may be lower than that of the second clock signal.

According to further exemplary embodiments of the inventive concept, there is provided a mobile device which may include an SoC in which the above application processor is included, a memory connected to the SoC, and a display connected to the SoC. The application processor may include a memory controller configured to control an operation of the memory and a display controller configured to control an operation of the display. The display controller may communicate with the display through a display serial interface.

According to still further exemplary embodiments of the inventive concept, there is provided an integrated circuit which may include a CPU, an intellectual property (IP); a power manager configured to determine an operating state of at least the CPU among the CPU and the IP; and a clock signal supply control circuit configured to supply a clock signal or an oscillation signal to each of the CPU and the IP based on the determination. Here, the power manger may determine an operating state of the CPU without determining an operating state of the IP, and, in response to the determination that the CPU is in an idle state, the clock signal supply control circuit may supply the oscillation clock signal to the CPU. Also, in response to the determination that the CPU is in an idle state, the clock signal supply control circuit may supply the oscillation clock signal to the CPU and, regardless of a result of the determination, supply the clock signal to the IP.

DETAILED DESCRIPTION OF THE EXEMPLARY EMBODIMENTS

FIG. 1is a schematic block diagram of a mobile device10, according to some exemplary embodiments. Referring toFIG. 1, the mobile device10may be a portable electronic device using a battery for an operating voltage.

The portable electronic device may be a laptop computer, a cellular phone, a smart phone, a tablet personal computer (PC), a personal digital assistant (PDA), an enterprise digital assistant (EDA), a digital still camera, a digital video camera, a portable multimedia player (PMP), a personal navigation device or portable navigation device (PND), a handheld game console, a mobile internet device (MID), a multimedia device, a wearable computer, an Internet of things (IoT) device, an Internet of everything (IoE) device, or an e-book.

The mobile device10may include an integrated circuit100, a memory300, and a display400. The mobile device10may also include a camera200.

The integrated circuit100may be a controller or processor that controls the operations of the mobile device10. The integrated circuit100may be implemented as a system on chip (SoC), an application processor (AP), a mobile AP, or a control chip.

Here, “system idle” indicates a state in which all or part of the integrated circuit100is entirely or nearly entirely idling or in an idle mode in order to reduce power consumption of the integrated circuit100. The integrated circuit100may enter the system idle when, instead of a plurality of clock signals, an oscillation clock signal of an oscillator is supplied to all or part of the integrated circuit100. The frequency of the oscillation clock signal is lower than that of each of the clock signals.

The integrated circuit100may include a plurality of clock domains110-1through110-8and a hardware power management unit (PMU) or power manager150. The integrated circuit100may include one or more circuits that do not use a clock signal, but these circuits are not illustrated inFIG. 1for clarity of the description.

Each of the clock domains110-1through110-8may include at least one intellectual property (IP) which operates using a clock signal applied to each clock domain. Here, an IP is a function block integrated into the integrated circuit100. The IP may be a central processing unit (CPU), a graphics processing unit (GPU), a processor, a core of a multi-core processor, memory, a universal serial bus (USB), a peripheral component interconnect (PCI), a digital signal processor (DSP), a wired interface, a wireless interface, a controller, embedded software, codec, a video module (e.g., a camera interface, a Joint Photographic Experts Group (JPEG) processor, a video processor, or a mixer), a three-dimensional graphics core, an audio system, or a driver. In other words, a hardware IP may be a function block used in the integrated circuit100and the function block may be a hardware module with unique features.

The clock domains110-1through110-8may be divided into first clock domains110-1through110-6including a first type IP and second clock domains110-7and110-8including a second type IP. Clock signals applied to the respective clock domains110-1through110-8have different frequencies.

In a normal operation, each clock signal is applied to each of the first clock domains110-1through110-6according to the control of the hardware PMU150. In system idle, an oscillation clock signal output from an oscillator is applied to the first clock domains110-1through110-6according to the control of the hardware PMU150. The frequencies of the respective clock signals are higher than that of the oscillation clock signal. Accordingly, in system idle in which the oscillation clock signal is applied to the first clock domains110-1through110-6, the power consumption of the integrated circuit100is reduced.

However, in both the normal operation and the system idle, each clock signal is applied to each of the second clock domains110-7and110-8. In other words, even in system idle, the clock signals instead of the oscillation clock signal are respectively applied to the second clock domains110-7and110-8. For example, an external connectivity IP may be formed in each of the second clock domains110-7and110-8.

A memory controller110-4A included in the fourth clock domain110-4may control an access (e.g., a write operation or a read operation) to the memory300. The memory300may be formed with a dynamic random access memory (DRAM), a flash memory, an embedded multimedia card (eMMC), or a universal flash storage (UFS).

A display controller110-5A included in the fifth clock domain110-5may control the operations of the display400. In some embodiments, the display controller110-5A may support mobile industry processor interface (MIPI®) display serial interface (DSI), embedded DisplayPort (eDP) interface, or high definition multimedia interface (HDMI), but the inventive concept is not restricted to these examples.

When the mobile device10includes the camera200, the integrated circuit100may also include a camera interface110-1A. The camera interface110-1A included in the first clock domain110-1may process image data output from the camera200. For example, the camera interface110-1A may support MIPI® camera serial interface (CSI).

The camera interface110-1A, the memory controller110-4A, and the display controller110-5A are examples of IPs.

FIG. 2is a block diagram of an integrated circuit corresponding to the integrated circuit100illustrated inFIG. 1, according to an exemplary embodiment. Referring toFIG. 2, an integrated circuit100A includes a CPU112A, a plurality of IPs113-1through113-n(where “n” is a natural number of at least 2), a selection circuit115, a clock signal generator118, a clock management unit or clock manager (CMU)121, and a hardware PMU150A.

The CPU112A and some of the IPs113-1through113-nmay be classified as first type IPs and the rest of the IPs113-1through113-nmay be classified as second type IPs. In other words, the type of each of the CPU112A and the IPs113-1through113-nmay be determined based on information set in a register153A illustrated inFIG. 5. As described above, a first type IP may receive a clock signal or an oscillation clock signal, whereas a second type IP may receive only a clock signal.

Each of the CPU112A and the IPs113-1through113-nmay be formed in a corresponding one of the clock domains110-1through110-8illustrated inFIG. 1. For example, a first type IP may be formed in one of the first clock domains110-1through110-6and a second type IP may be formed in one of the second clock domains110-7and110-8. A first clock domain may be changed to a second clock domain and vice versa in other embodiments.

A clock signal supply control circuit may supply clock signals CLK0through CLKn to the CPU112A and the IPs113-1through113-n, respectively, or supply an oscillation clock signal CLK to the CPU112A and the IPs113-1through113-nbased on selection signals SEL0through SELn output from the hardware PMU150A.

For example, during a normal operation, the clock signal supply control circuit may apply the clock signals CLK0through CLKn to the CPU112A and the IPs113-1through113-n, respectively, based on the selection signals SEL0through SELn, respectively, output from the hardware PMU150A. At this time, the selection signals SEL0through SELn may be at a first level (e.g., a high level).

However, in system idle, the clock signal supply control circuit may apply the oscillation clock signal CLK to the CPU112A and the IPs113-1through113-nbased on the selection signals SEL0through SELn, respectively, output from the hardware PMU150A. At this time, the selection signals SEL0through SELn may be at a second level (e.g., a low level).

The clock signal supply control circuit may include a selection circuit115, a clock signal generator118, and a clock management unit (CMU)121in some embodiments, but the inventive concept is not restricted to these embodiments.

The CPU112A may transmit an idle signal IDLE0to the hardware PMU150A. The IPs113-1through113-nmay respectively transmit idle signals IDLE1through IDLEn to the hardware PMU150A. For example, each of the idle signals IDLE0through IDLEn may be transmitted to the hardware PMU150A through a corresponding exclusive (or dedicated) line.

The hardware PMU150A may determine whether system idle has been entered based on the idle signal IDLE0and may generate the selection signals SEL0through SELn and first control signals CTR based on the determination result. Alternatively, the hardware PMU150A may determine whether system idle has been entered based on the idle signals IDLE0through IDLEn and may generate the selection signals SEL0through SELn and the first control signals CTR according to the determination result.

The selection circuit115may include a plurality of selectors115-0through115-n. The selector115-0may output the clock signal CLK0or the oscillation clock signal CLK to the CPU112A in response to the selection signal SEL0. The selectors115-1through115-nmay output the clock signals CLK1through CLKn, respectively, or the oscillation clock signal CLK to the IPs113-1through113-n, respectively, in response to the selection signals SEL1through SELn, respectively.

The clock signal generator118includes an oscillator117and phase-locked loops (PLLs)119-0through119-n. The oscillator117generates the oscillation clock signal CLK. The PLLs119-0through119-nmay generate the clock signals CLK0through CLKn, respectively, using the oscillation clock signal CLK. The clock signals CLK0through CLKn have different frequencies from one another.

The CMU121may generate second control signals PCTR for controlling the operation (e.g., on or off) of the PLLs119-0through119-nin response to the first control signals CTR. At least one of the PLLs119-0through119-nmay be turned on (or enabled) in response to the second control signals PCTR.

As described above, during a normal operation, the CPU112A and the IPs113-1through113-ndo not generate the idle signals IDLE0through IDLEn. Accordingly, the hardware PMU150A outputs the selection signals SEL0through SELn at the first level (i.e., the high level) and outputs the first control signals CTR instructing to maintain.

The clock signals CLK0through CLKn are applied by the selectors115-0through115-n, respectively, to the CPU112A and the IPs113-1through113-n, respectively. At this time, the CMU121generates the second control signals PCTR for maintaining the on-state of the PLLs119-0through119-nin response to the first control signals CTR instructing to maintain.

However, in system idle, the CPU112A and the IPs113-1through113-ngenerates the idle signals IDLE0through IDLEn. Accordingly, the hardware PMU150A outputs the selection signals SEL0through SELn at the second level (i.e., the low level) and outputs the first control signals CTR instructing to turn off the PLLs119-0through119-n. For example, the first control signals CTR may be transmitted in series or parallel to the CMU121.

The oscillation clock signal CLK is applied by the selectors115-0through115-nto the CPU112A and the IPs113-1through113-n. Thereafter, the CMU121generates the second control signals PCTR for turning off the PLLs119-0through119-nin response to the first control signals CTR instructing to turn off. Accordingly, after the oscillation clock signal CLK is applied to the CPU112A and the IPs113-1through113-n, the PLLs119-0through119-nare turned off to reduce power consumption.

When an interrupt signal INT is input to the hardware PMU150A, the hardware PMU150A generates the first control signals CTR instructing to turn on. The CMU121generates the second control signals PCTR for turning on the PLLs119-0through119-nin response to the first control signals CTR instructing to turn on.

After generating the first control signals CTR instructing to turn on, the hardware PMU150A generates the selection signals SEL0through SELn at the first level. The hardware PMU150A may determine the generation timing of the selection signals SEL0through SELn taking the lock time of the PLLs119-0through119-ninto account.

Control signals may include the selection signals SEL0through SELn, the first control signals CTR, and the second control signals PCTR. As described above, in system idle, the clock signal supply control circuit may output the oscillation clock signal CLK instead of the clock signals CLK0through CLKn applied to the CPU112A and the IPs113-1through113-ninto.

FIG. 3is a diagram of a clock signal generator corresponding to the clock signal generator118illustrated inFIG. 2, according to an exemplary embodiment. Referring toFIG. 3, the oscillator117of the clock signal generator118A may generate an oscillation signal using a clock signal output from a crystal oscillator OSC connected to the integrated circuit100A. A PLL118-1may generate a clock signal using the oscillation clock signal. Frequency dividers120-0through120-ndivide the frequency of the clock signal output from the PLL118-1to generate the clock signals CLK0through CLKn, respectively. The frequencies of the respective clock signals CLK0through CLKn may be different from one another.

FIG. 4is a diagram of a clock signal generator corresponding to the clock signal generator118illustrated inFIG. 2, according to an exemplary embodiment. Referring toFIG. 4, the PLL118-1of the clock signal generator118B may generate a clock signal using an external clock signal ECLK from an outside of the integrated circuit100A. The external clock signal ECLK may be received through a pin or a pad. The frequency dividers120-0through120-ndivide the frequency of the clock signal output from the PLL118-1to generate the clock signals CLK0through CLKn, respectively. The frequencies of the respective clock signals CLK0through CLKn may be different from one another.

FIG. 5is a block diagram of the hardware PMU150A illustrated inFIG. 2. Referring toFIGS. 2 and 5, the hardware PMU150A may include a control signal generator151A and a register153A. For example, the control signal generator151A may be a state machine.

The control signal generator151A may generate the selection signals SEL0through SELn and the first control signals CTR according to the idle signal IDLE0output from the CPU112A and information set in the register153A. The register153A may store a bit (e.g., “1” (or data “1”) or “0” (or data “0”)) corresponding to each of the CPU112A and the IPs113-1through113-n.

For example, when bits respectively corresponding to the CPU112A and the IPs113-1through113-nare all “1”, the hardware PMU150A may output the selection signals SEL0through SELn at the second level (e.g., having a value of “0”) and may output the first control signals CTR instructing to turn off all of the PLLs119-0through119-nto the CMU121in system idle. The selectors115-0through115-ntransmit the oscillation clock signal CLK to the CPU112A and the IPs113-1through113-n, respectively. Thereafter, all of the PLLs119-0through119-nare turned off in response to the second control signals PCTR from the CMU121. At this time, the CPU112A and the IPs113-through113-noperate as first type IPs.

However, when bits respectively corresponding to the CPU112A and the IPs113-2through113-nare “1” and a bit corresponding to the IP113-1is “0”, the hardware PMU150A may output the selection signals SEL0and SEL2through SELn at the second level, the selection signal SEL1at the first level (e.g., having a value of “1”), and the first control signals CTR instructing to turn off rest PLLs119-0and119-2through119-nexcept for the PLL119-1. Accordingly, the selectors115-0and115-2through115-ntransmit the oscillation clock signal CLK to the CPU112A and the IPs113-2through113-n, respectively, but the selector115-1transmits the clock signal CLK1to the IP113-1. Thereafter, the rest PLLs119-0and119-2through119-nexcept for the PLL119-1are turned off in response to the second control signals PCTR from the CMU121. In this case, the CPU112A and the IPs113-2through113-noperate as first type IPs and the IP113-1operates as a second type IP. For example, IP113-1may be formed in the second clock domain110-7or110-8.

Alternatively, the control signal generator151A may generate the selection signals SEL0through SELn and the first control signals CTR according to the idle signals IDLE0through IDLEn respectively from the CPU112A and the IPs113-1through113-nand information set in the register153A. The register153A may store a bit (e.g., “1” or “0”) corresponding to each of the CPU112A and the IPs113-1through113-n.

For example, when bits respectively corresponding to the CPU112A and the IPs113-1through113-nare all “1”, the hardware PMU150A may output the selection signals SEL0through SELn at the second level to the selection circuit115and may output the first control signals CTR instructing to turn off all of the PLLs119-0through119-nto the CMU121.

Accordingly, the selectors115-0through115-ntransmit the oscillation clock signal CLK to the CPU112A and the IPs113-1through113-n, respectively. Thereafter, all of the PLLs119-0through119-nare turned off in response to the second control signals PCTR from the CMU121. In this case, the CPU112A and the IPs113-through113-noperate as first type IPs, respectively.

However, when bits respectively corresponding to the CPU112A and the IPs113-2through113-nare “1” and a bit corresponding to the IP113-1is “0”, the hardware PMU150A may output the selection signals SEL0and SEL2through SELn at the second level and the selection signal SEL1at the first level to the selection circuit115and output the first control signals CTR instructing to turn off the rest PLLs119-0and119-2through119-nexcept for the PLL119-1to the CMU121.

Accordingly, the selectors115-0and115-2through115-ntransmit the oscillation clock signal CLK to the CPU112A and the IPs113-2through113-n, respectively, but the selector115-1transmits the clock signal CLK1to the IP113-1. Thereafter, the rest PLLs119-0and119-2through119-nexcept for the PLL119-1are turned off in response to the second control signals PCTR from the CMU121. In this case, the CPU112A and the IPs113-2through113-noperate as first type IPs and the IP113-1operates as a second type IP.

FIG. 6is a block diagram of an integrated circuit corresponding to the integrated circuit100illustrated inFIG. 1, according to another exemplary embodiment. Referring toFIG. 6, the integrated circuit100B includes a CPU112B, a plurality of IPs113-1′ through113-n′, a selection circuit115, a clock signal generator118, a CMU121, and a hardware PMU150B. For example, the IP113-1or113-1′ may be a GPU, the IP113-2or113-2′ may be a wired interface, and the IP113-nor113-n′ may be a video module in some embodiments, but the inventive concept is not restricted to these embodiments.

The CPU112B may monitor the operating states of the respective IPs113-1′ through113-n′ and may detect the operating states of the IPs113-1′ through113-n′ based on monitoring information ST1through STn. An operating state may be, for example, a run state or an idle state. The CPU112B may detect whether each of the IPs113-1′ through113-n′ is in an idle state based on the operating state of each IP. The CPU112B detects whether each of the CPU112B and the IPs113-1′ through113-n′ is in the idle state and transmits an idle signal or state information SET1to the hardware PMU150B according to the detection result.

FIG. 7is a block diagram of the hardware PMU150B illustrated inFIG. 6. Referring toFIGS. 6 and 7, the CPU112B or software (or firmware) executed in the CPU112B may detect whether each of the CPU112B and the IPs113-1′ through113-n′ is in an idle state and may set the idle signal or state information SET1in a register153B.

The hardware PMU150B includes a control signal generator151B and the register153B. The control signal generator151B may be a state machine. The control signal generator151B may generate the selection signals SEL0through SELn and the first control signals CTR using the state information SET1set in the register153B. The register153B may store a bit (e.g., “1” or “0”) corresponding to each of the CPU112B and the IPs113-1′ through113-n′.

For example, when bits respectively corresponding to the CPU112B and the IPs113-1′ through113-n′ are all “1”, the hardware PMU150B may output the selection signals SEL0through SELn having a value of “0” to the selection circuit115and may output the first control signals CTR instructing to turn off all of the PLLs119-0through119-nto the CMU121. The selectors115-0through115-ntransmit the oscillation clock signal CLK to the CPU112B and the IPs113-1′ through113-n′, respectively. Thereafter, all of the PLLs119-0through119-nare turned off in response to the second control signals PCTR output from the CMU121. In this case, the CPU112B and the IPs113-1′ through113-n′ operate as first type IPs.

However, when bits respectively corresponding to the CPU112B and the IPs113-2′ through113-n′ are “1” and a bit corresponding to the IP113-1′ is “0”, the hardware PMU150B may output the selection signals SEL0and SEL2through SELn having a value of “0” and the selection signal SEL1having a value of “1” to the selection circuit115and may output the first control signals CTR instructing to turn off the rest PLLs119-0and119-2through119-nexcept for the PLL119-1to the CMU121.

The selectors115-0and115-2through115-ntransmit the oscillation clock signal CLK to the CPU112B and the IPs113-2′ through113-n′, respectively, but the selector115-1transmits the clock signal CLK1to the IP113-1′. Thereafter, the rest PLLs119-0and119-2through119-nexcept for the PLL119-1are turned off in response to the second control signals PCTR output from the CMU121. In this case, the CPU112B and the IPs113-2′ through113-n′ operate as first type IPs and the IP113-1′ operates as a second type IP.

Alternatively, the CPU112B may determine whether each of power domains including any one of the IPs113-1′ through113-n′ is power-gated and transmit the idle signal or state information SET1to the hardware PMU150B. Whether the power domain is power-gated means whether power to the power domain is supplied or cut off. The corresponding power domain may include one or more IPs.

FIG. 8is a flowchart of the operation of the integrated circuit100A illustrated inFIG. 2according to some exemplary embodiments. The clock signal supply control circuit applies the clock signals CLK0through CLKn to the CPU112A and the IPs113-1through113-n, respectively, in operation S110.

The CPU112A and the IPs113-1through113-ntransmit their respective state information to the hardware PMU150A in operation S120. The state information may be the idle signal IDLE0and idle signals IDLE1through IDLEn.

The hardware PMU150A determines whether system idle has been entered based on the state information in operation S130. When system idle has not been entered, the clock signal supply control circuit performs operation S110. However, when system idle has been entered, the hardware PMU150A generates the selection signals SEL0through SELn and the first control signals CTR based on the state information and information stored in the register153A.

The clock signal supply control circuit applies the output signal CLK of the oscillator117to a first IP group of some of the IPs113-1through113-nand the CPU112A and applies clock signals output from PLLs to a second IP group of the rest of the IPs113-1through113-nin operation S140. At this time, IPs in the first IP group and the CPU112A may be first type IPs and IPs in the second IP group may be second type IPs.

When the interrupt signal INT is not input to the hardware PMU150A in operation S150, the clock signal supply control circuit performs operation S140. However, when the interrupt signal INT is input to the hardware PMU150A in operation S150, that is, when a wake-up event occurs, the control signal generator151A outputs the first control signals CTR for turning on at least one of the PLLs119-0through119-nthat has been off to the CMU121. At least one of the PLLs119-0through119-nis turned on in response to the second control signals PCTR output from the CMU121.

When a lock time for the at least one of the PLLs119-0through119-n, which has been on, elapses, the hardware PMU150A outputs at least one corresponding selection signal to the selection circuit115. Accordingly, the clock signal supply control circuit applies not the output signal CLK of the oscillator117but clock signals from PLLs that have been turned on to the first IP group and the CPU112A in operation S160.

FIG. 9is a flowchart of the operation of the integrated circuit110B illustrated inFIG. 6according to some exemplary embodiments. The clock signal supply control circuit applies the clock signals CLK0through CLKn to the CPU112B and the IPs113-1′ through113-n′, respectively.

The CPU112B detects or determines an operating state of each of the CPU112B and the IPs113-1′ through113-n′ (for example, the CPU112B detects whether each of the CPU112B and the IPs113-1′ through113-n′ is in an idle state) and transmits the idle signal or state information SET1to the hardware PMU150B in operation S210. In other words, the CPU112B stores the idle signal or state information SET1in the register153B of the hardware PMU150B in operation S210. The hardware PMU150B determines whether system idle has been entered based on the idle signal or state information SET1stored in the register153B in operation S220.

When system idle has been entered, the hardware PMU150B generates the selection signals SEL0through SELn and the first control signals CTR based on the idle signal or state information SET1stored in the register153B. The clock signal supply control circuit applies the output signal CLK of the oscillator117to a first IP group of some of the IPs113-1′ through113-n′ and the CPU112B and applies corresponding clock signals output from PLLs to a second group of the rest of the IPs113-1′ through113-n′ in operation S230. At this time, IPs in the first IP group and the CPU112B may be first type IPs and IPs in the second IP group may be second type IPs.

When the interrupt signal INT is not input to the hardware PMU150B in operation S240, the clock signal supply control circuit performs operation S230. However, when the interrupt signal INT is input to the hardware PMU150B in operation S240, that is, when a wake-up event occurs, the control signal generator151B outputs the first control signals CTR for turning on at least one of the PLLs119-0through119-nthat has been off to the CMU121. At least one of the PLLs119-0through119-nis turned on in response to the second control signals PCTR output from the CMU121.

When a lock time for the at least one of the PLLs119-0through119-n, which has been on, elapses, the hardware PMU150B outputs at least one corresponding selection signal to the selection circuit115. Accordingly, the clock signal supply control circuit applies not the output signal CLK of the oscillator117but clock signals from PLLs that have been turned on to the first IP group and the CPU112B in operation S250.

FIG. 10is a flowchart of the operation of the integrated circuit100B illustrated inFIG. 6according to other exemplary embodiments. The CPU112B stores the idle signal or state information SET1, which indicates whether each of power domains including any of the IPs113-1′ through113-n′ has been power-gated, to the hardware PMU150B in operation S310. In other words, the CPU112B stores the idle signal or state information SET1in the register153B of the hardware PMU150B in operation S310.

The clock signal supply control circuit applies the clock signals CLK0through CLKn to the CPU112B and the IPs113-1′ through113-n′, respectively, in operation S320. The hardware PMU150B determines whether system idle has been entered based on the idle signal or state information SET1stored in the register153B in operation S330. When system idle has been entered, the hardware PMU150B generates the selection signals SEL0through SELn and the first control signals CTR based on the idle signal or state information SET1.

The clock signal supply control circuit applies the output signal CLK of the oscillator117to a first IP group of some of the IPs113-1′ through113-n′ and the CPU112B and applies corresponding clock signals output from PLLs to a second group of the rest of the IPs113-1′ through113-n′ in operation S340. At this time, IPs in the first IP group and the CPU112B may be first type IPs and IPs in the second IP group may be second type IPs.

When the interrupt signal INT is not input to the hardware PMU150B in operation S350, the clock signal supply control circuit performs operation S340. However, when the interrupt signal INT is input to the hardware PMU150B in operation S350, that is, when a wake-up event occurs, the control signal generator151B outputs the first control signals CTR for turning on at least one of the PLLs119-0through119-nthat has been off to the CMU121. At least one of the PLLs119-0through119-nis turned on in response to the second control signals PCTR output from the CMU121.

When a lock time for the at least one of the PLLs119-0through119-n, which has been on, elapses, the hardware PMU150B outputs at least one corresponding selection signal to the selection circuit115. Accordingly, the clock signal supply control circuit applies not the output signal CLK of the oscillator117but clock signals from PLLs that have been turned on to the first IP group and the CPU112B in operation S360.

As described above, according to some embodiments of the inventive concept, an application processor supplies a clock signal of an oscillator instead of a clock signal used therein by using a hardware PMU when the application processor is in system idle, thereby reducing power consumption.

The operations or steps of the methods or algorithms described above can be embodied as computer readable codes on a computer readable recording medium, or to be transmitted through a transmission medium. The computer readable recording medium is any data storage device that can store data which can be thereafter read by a computer system. Examples of the computer readable recording medium include read-only memory (ROM), random-access memory (RAM), CD-ROMs, magnetic tapes, floppy disks, and optical data storage devices. The transmission medium can include carrier waves transmitted through the Internet or various types of communication channel. The computer readable recording medium can also be distributed over network coupled computer systems so that the computer readable code is stored and executed in a distributed fashion.

At least one of the components, elements or units represented by a block as illustrated inFIGS. 1-7may be embodied as various numbers of hardware, software and/or firmware structures that execute respective functions described above, according to an exemplary embodiment. For example, at least one of these components, elements or units may use a direct circuit structure, such as a memory, processing, logic, a look-up table, etc. that may execute the respective functions through controls of one or more microprocessors or other control apparatuses. Also, at least one of these components, elements or units may be specifically embodied by a module, a program, or a part of code, which contains one or more executable instructions for performing specified logic functions. Also, at least one of these components, elements or units may further include a processor such as a CPU that performs the respective functions, a microprocessor, or the like. Two or more of these components, elements or units may be combined into one single component, element or unit which perform all operations or functions of the combined two or more components, elements of units. Further, although a bus is not illustrated in the above block diagrams, communication between the components, elements or units may be performed through the bus. Functional aspects of the above exemplary embodiments may be implemented in algorithms that execute on one or more processors. Furthermore, the components, elements or units represented by a block or processing steps may employ any number of related art techniques for electronics configuration, signal processing and/or control, data processing and the like.