Manufacturing method of memory device having bit line with stepped profile

A method for preparing a semiconductor structure includes providing a semiconductor substrate having a first surface; disposing a first dielectric layer over the first surface of the semiconductor substrate, a conductive layer over the first dielectric layer, and a second dielectric layer over the conductive layer; disposing a patterned mask over the second dielectric layer; removing portions of the second dielectric layer, the conductive layer and the first dielectric layer exposed through the patterned mask to form a first trench; forming a spacer surrounding the first dielectric layer, the conductive layer and the second dielectric layer; disposing an energy-decomposable mask over the second dielectric layer and the spacer; irradiating a portion of the energy-decomposable mask by an electromagnetic radiation; removing the portion of the energy-decomposable mask irradiated by the electromagnetic radiation; and removing a portion of the second dielectric layer exposed through the energy-decomposable mask.

TECHNICAL FIELD

The present disclosure relates to a manufacturing method of a memory device and, and more particularly, to a manufacturing method of a memory device having a bit line (BL) with a stepped profile.

DISCUSSION OF THE BACKGROUND

Semiconductor devices are essential for many modern applications. With the advancement of electronic technology, semiconductor devices are becoming smaller in size while providing greater functionality and comprising greater amounts of integrated circuitry. Due to the miniaturized scale of semiconductor devices, various types and dimensions of semiconductor devices performing different functions are integrated and packaged into a single module. Furthermore, numerous manufacturing operations are implemented for integration of various types of semiconductor devices.

However, the manufacturing and integration of semiconductor devices involve many complicated steps and operations. An increase in complexity of manufacturing and integration of the semiconductor device may cause deficiencies such as misalignment of interconnect structures, bridging, short circuiting, etc. Accordingly, there is a continuous need to improve the structure and the manufacturing process of semiconductor devices.

SUMMARY

One aspect of the present disclosure provides a memory device. The memory device includes a semiconductor substrate including a first surface; a bit line disposed on the first surface of the semiconductor substrate, wherein the bit line includes a first dielectric layer, a conductive layer disposed over the first dielectric layer, a second dielectric layer disposed over the conductive layer, and a spacer surrounding the first dielectric layer, the conductive layer and the second dielectric layer, wherein the second dielectric layer includes a first portion surrounded by the spacer, and a second portion disposed over the first portion and exposed through the spacer, wherein a first width of the first portion is substantially greater than a second width of the second portion.

In some embodiments, the first width of the first portion is substantially consistent along a height of the second dielectric layer.

In some embodiments, the second width of the second portion is substantially consistent along a height of the second dielectric layer.

In some embodiments, a top surface of the first portion is substantially coplanar with a top surface of the spacer.

In some embodiments, a first height of the first portion is substantially greater than or equal to a second height of the second portion.

In some embodiments, the first dielectric layer and the second dielectric layer include a same material.

In some embodiments, the first dielectric layer and the second dielectric layer include nitride.

In some embodiments, the conductive layer includes tungsten (W).

In some embodiments, the spacer includes nitride and oxide.

In some embodiments, the spacer includes a first layer, a second layer and a third layer, wherein the second layer is disposed between the first layer and the third layer.

In some embodiments, the first layer contacts the first dielectric layer, the conductive layer and the second dielectric layer.

In some embodiments, the second layer and the third layer are isolated from the first dielectric layer, the conductive layer and the second dielectric layer.

In some embodiments, the first layer and the third layer include nitride.

In some embodiments, the second layer includes oxide.

In some embodiments, the second dielectric layer is partially surrounded by the spacer.

In some embodiments, the first dielectric layer and the conductive layer are entirely surrounded by the spacer.

Another aspect of the present disclosure provides a memory device. The memory device includes: a semiconductor substrate including a first surface; a first bit line and a second bit line disposed on the first surface of the semiconductor substrate and adjacent to each other, wherein the first bit line and the second bit line respectively include a first dielectric layer, a conductive layer disposed over the first dielectric layer, a second dielectric layer disposed over the conductive layer, and a spacer surrounding the first dielectric layer, the conductive layer and the second dielectric layer; and a gap disposed between the first bit line and the second bit line, wherein the gap has a first width and a second width substantially different from the first width.

In some embodiments, the first width is substantially less than the second width.

In some embodiments, the second width is disposed over the first width.

In some embodiments, the gap is tapered toward the first surface of the semiconductor substrate.

Another aspect of the present disclosure provides a method of manufacturing a memory device. The method includes steps of providing a semiconductor substrate having a first surface; disposing a first dielectric layer over the first surface of the semiconductor substrate, a conductive layer over the first dielectric layer, and a second dielectric layer over the conductive layer; disposing a patterned mask over the second dielectric layer; removing portions of the second dielectric layer, the conductive layer and the first dielectric layer exposed through the patterned mask to form a first trench; forming a spacer surrounding the first dielectric layer, the conductive layer and the second dielectric layer; disposing an energy-decomposable mask over the second dielectric layer and the spacer; irradiating a portion of the energy-decomposable mask by an electromagnetic radiation; removing the portion of the energy-decomposable mask irradiated by the electromagnetic radiation; and removing a portion of the second dielectric layer exposed through the energy-decomposable mask.

In some embodiments, the method further comprises removing a portion of the spacer exposed through the energy-decomposable mask.

In some embodiments, at least a portion of the second dielectric layer is exposed through the spacer.

In some embodiments, the removal of the portion of the second dielectric layer and the removal of the portion of the spacer are performed separately or simultaneously.

In some embodiments, the energy-decomposable mask includes a cross-linking compound having a functional group or a double bonding.

In some embodiments, the energy-decomposable mask includes polymer, polyimide, resin or epoxy.

In some embodiments, the electromagnetic radiation is emitted laterally toward the portion of the energy-decomposable mask.

In some embodiments, the electromagnetic radiation is infrared (IR), ultraviolet (UV) or electron beam (e-beam).

In some embodiments, the first trench extends toward the first surface of the semiconductor substrate and is adjacent to the second dielectric layer, the conductive layer and the first dielectric layer.

In some embodiments, the portion of the energy-decomposable mask irradiated by the electromagnetic radiation is disposed at a periphery of the energy-decomposable mask.

In some embodiments, the portion of the energy-decomposable mask irradiated by the electromagnetic radiation is in contact with the spacer and the second dielectric layer.

In some embodiments, a width of the energy-decomposable mask after the removal of the portion of the energy-decomposable mask irradiated by the electromagnetic radiation is substantially less than a width of the second dielectric layer after the formation of the first trench.

In some embodiments, after the removal of the portion of the second dielectric layer exposed through the energy-decomposable mask, the second dielectric layer includes a first width and a second width over the first width and substantially less than the first width.

In some embodiments, the method further comprises removing the energy-decomposable mask over the second dielectric layer after the removal of the portion of the second dielectric layer exposed through the energy-decomposable mask.

In conclusion, because a portion of a second dielectric layer of a bit line is removed to form a stepped profile, a distance or a critical dimension between two adjacent bit lines can be increased and bridging of two adjacent bit lines can be prevented. More specifically, because the bit line has the stepped profile around a periphery of the bit line, a subsequent filling of a gap between two adjacent bit lines with conductive or insulating material can be performed more efficiently. The gap between two adjacent bit lines can be filled completely without formation of voids or while minimizing the formation of voids. Therefore, a performance of the memory device and a process of manufacturing the memory device are improved.

DETAILED DESCRIPTION

FIG.1is a schematic cross-sectional side view of a memory device100in accordance with some embodiments of the present disclosure. In some embodiments, the memory device100includes several unit cells arranged in rows and columns.

In some embodiments, the memory device100includes a semiconductor substrate101. In some embodiments, the semiconductor substrate101includes semiconductive material such as silicon, germanium, gallium, arsenic, or a combination thereof. In some embodiments, the semiconductor substrate101includes bulk semiconductor material. In some embodiments, the semiconductor substrate101is a semiconductor wafer (e.g., a silicon wafer) or a semiconductor-on-insulator (SOI) wafer (e.g., a silicon-on-insulator wafer). In some embodiments, the semiconductor substrate101is a silicon substrate. In some embodiments, the semiconductor substrate101includes lightly-doped monocrystalline silicon. In some embodiments, the semiconductor substrate101is a p-type substrate.

In some embodiments, the semiconductor substrate101includes a first surface101aand a second surface101bopposite to the first surface101b. In some embodiments, the first surface101ais a front side of the semiconductor substrate101, wherein electrical devices or components are subsequently formed over the first surface101aand configured to electrically connect to an external circuitry. In some embodiments, the second surface101bis a back side of the semiconductor substrate101, where electrical devices or components are absent.

In some embodiments, the memory device100includes a bit line102disposed on the semiconductor substrate101. In some embodiments, the bit line102is disposed on and extends from the first surface101aof the semiconductor substrate101. In some embodiments, the bit line102is configured to read a bit in the memory device100or allow an electrical current to program the bit. In some embodiments, the bit line102extends orthogonal to the first surface101aof the semiconductor substrate101.

In some embodiments, the bit line102includes a first dielectric layer102a, a conductive layer102b, a second dielectric layer102cand a spacer102d. In some embodiments, the first dielectric layer102ais disposed on the first surface101aof the semiconductor substrate101. In some embodiments, the first dielectric layer102ais entirely surrounded by the spacer102d. In some embodiments, the first dielectric layer102aincludes dielectric material such as nitride or the like. In some embodiments, the first dielectric layer102aincludes silicon nitride.

In some embodiments, the conductive layer102bis disposed over the first dielectric layer102a. In some embodiments, the conductive layer102bis in contact with the first dielectric layer102a. In some embodiments, the conductive layer102bis entirely surrounded by the spacer102d. In some embodiments, the conductive layer102bincludes conductive material such as tungsten (W) or the like.

In some embodiments, the second dielectric layer102cis disposed over the conductive layer102band the first dielectric layer102a. In some embodiments, the second dielectric layer102cis in contact with the conductive layer102band is separated from the first dielectric layer102aby the conductive layer102b. In some embodiments, the second dielectric layer102cis partially surrounded by the spacer102d.

In some embodiments, the second dielectric layer102cincludes dielectric material such as nitride or the like. In some embodiments, the second dielectric layer102cincludes silicon nitride. In some embodiments, the first dielectric layer102aand the second dielectric layer102cinclude a same material or different materials.

In some embodiments, the spacer102dsurrounds the first dielectric layer102a, the conductive layer102band the second dielectric layer102c. In some embodiments, the spacer102dincludes dielectric material such as oxide, nitride or the like. In some embodiments, the spacer102dincludes oxide and nitride. In some embodiments, the spacer102dincludes several layers. In some embodiments, the spacer102dis a nitride-oxide-nitride (NON) structure.

FIG.2is an enlarged view of the bit line102showing the spacer102dhaving several layers. In some embodiments, the spacer102dincludes a first layer102j, a second layer102kand a third layer102m. In some embodiments, the second layer102kis disposed between the first layer102jand the third layer102m. In some embodiments, the first layer102jis in contact with the second dielectric layer102c, the conductive layer102band the first dielectric layer102a. In some embodiments, the first layer102jincludes nitride or oxide. In some embodiments, the first layer102jincludes nitride.

In some embodiments, the second layer102kis in contact with the first layer102jand the third layer102m. In some embodiments, the second layer102kis isolated from the first dielectric layer102a, the conductive layer102band the second dielectric layer102c. In some embodiments, the second layer102kincludes nitride or oxide. In some embodiments, the second layer102kincludes oxide.

In some embodiments, the third layer102mis in contact with the second layer102k. In some embodiments, the third layer102mis isolated from the first dielectric layer102a, the conductive layer102band the second dielectric layer102c. In some embodiments, the third layer102mincludes nitride or oxide. In some embodiments, the third layer102mincludes nitride.

Referring back toFIG.1, the second dielectric layer102chas a stepped profile. In some embodiments, the second dielectric layer102cis at least partially exposed through the spacer102d. In some embodiments, the second dielectric layer102cincludes a first portion102eand a second portion102fdisposed over the first portion102e. In some embodiments, the first portion102eis surrounded by the spacer102d. In some embodiments, the second portion102fis exposed through the spacer102d.

In some embodiments, the second portion102fprotrudes from the first portion102e. In some embodiments, a first width W1of the first portion102eis substantially different from a second width W2of the second portion102f. In some embodiments, the first width W1of the first portion102eis substantially greater than the second width W2of the second portion102f.

In some embodiments, the first portion102ehas a first height H1, and the second portion102fhas a second height H2. In some embodiments, the first height H1of the first portion102eis substantially greater than or equal to the second height H2of the second portion102f. In some embodiments, the first width W1of the first portion102eis substantially consistent at positions of various distance above a bottom surface of the second dielectric layer102c. In some embodiments, the second width W2of the second portion102fis substantially consistent at positions of various distance above a lower surface of the second portion102f.

In some embodiments, the first portion102ehas a top surface102gsubstantially coplanar with a top surface102iof the spacer102d. In some embodiments, the second portion102fhas a top surface102hdisposed higher than the top surface102gof the first portion102eand the top surface102iof the spacer102d. In some embodiments, the second portion102fis separated from the spacer102d.

Referring back toFIG.2, the top surface102iof the spacer102dincludes a top surface102nof the first layer102j, a top surface102pof the second layer102kand a top surface102rof the third layer102m. In some embodiments, the top surface102gof the first portion102eis substantially coplanar with the top surface102nof the first layer102j, the top surface102pof the second layer102kand the top surface102rof the third layer102m. In some embodiments, the top surface102hof the second portion102fis disposed higher than the top surface102nof the first layer102j, the top surface102pof the second layer102kand the top surface102rof the third layer102m.

Referring back toFIG.1, a gap103is disposed between two adjacent bit lines102. In some embodiments, at least a portion of the first surface101aof the semiconductor substrate101is exposed through the gap103. In some embodiments, the gap103is adjacent to the second portion102fof the second dielectric layer102cand adjacent to the spacer102d. In some embodiments, the gap103is tapered toward the first surface101aof the semiconductor substrate101.

In some embodiments, the gap103has a third width W3and a fourth width W4substantially different from the third width W3. In some embodiments, the gap103has the fourth width W4at a position higher than a position at which the gap103has the third width W3. In some embodiments, the third width W3is substantially less than the fourth width W4.

The stepped profile of the second dielectric layer102cof the bit line102causes the fourth width of the gap103between two adjacent bit lines102to be increased. As such, bridging of two adjacent bit lines102can be prevented, and a subsequent filling of the gap103between two adjacent bit lines102with conductive or insulating material can be performed more efficiently. The gap103can be filled completely without formation of voids or while minimizing the formation of voids. Therefore, performance of the memory device100is improved.

FIG.3is a flow diagram illustrating a method S200of manufacturing a memory device100in accordance with some embodiments of the present disclosure, andFIGS.4to26illustrate cross-sectional views of intermediate stages in formation of the memory device100in accordance with some embodiments of the present disclosure.

The stages shown inFIGS.4to26are also illustrated schematically in the flow diagram inFIG.3. In following discussion, the fabrication stages shown inFIGS.4to26are discussed in reference to process steps shown inFIG.3. The method S200includes a number of operations, and description and illustration are not deemed as a limitation to a sequence of the operations. The method S200includes a number of steps (S201, S202, S203, S204, S205, S206, S207, S208and S209).

Referring toFIG.4, a semiconductor substrate101is provided according to step S201inFIG.3. In some embodiments, the semiconductor substrate101includes semiconductive material such as silicon, germanium, gallium, arsenic, or a combination thereof. In some embodiments, the semiconductor substrate101is a silicon substrate. In some embodiments, the semiconductor substrate101has a first surface101aand a second surface101bopposite to the first surface101a.

Referring toFIGS.5to7, a first dielectric layer102a, a conductive layer102band a second dielectric layer102care disposed according to step S202inFIG.3. In some embodiments as shown inFIG.5, the first dielectric layer102ais disposed over the first surface101aof the semiconductor substrate101. In some embodiments, the first dielectric layer102ais disposed by deposition, chemical vapor deposition (CVD) or any other suitable process. In some embodiments, the first dielectric layer102aincludes dielectric material such as nitride or the like. In some embodiments, the first dielectric layer102aincludes silicon nitride.

In some embodiments as shown inFIG.6, the conductive layer102bis disposed over the first dielectric layer102a. In some embodiments, the conductive layer102bis disposed by deposition, chemical vapor deposition (CVD) or any other suitable process. In some embodiments, the conductive layer102bincludes conductive material such as tungsten (W) or the like.

In some embodiments as shown inFIG.7, the second dielectric layer102cis disposed over the conductive layer102b. In some embodiments, the second dielectric layer102cis disposed by deposition, chemical vapor deposition (CVD) or any other suitable process. In some embodiments, the second dielectric layer102cincludes dielectric material such as nitride or the like. In some embodiments, the second dielectric layer102cincludes silicon nitride. In some embodiments, the first dielectric layer102aand the second dielectric layer102cinclude a same material.

Referring toFIGS.8and9, a patterned mask104is disposed over the second dielectric layer102caccording to step S203inFIG.3. In some embodiments, the disposing of the patterned mask104includes disposing a photoresist104′ over the second dielectric layer102cas shown inFIG.8, and then removing some portions of the photoresist104′ to form the patterned mask104as shown inFIG.9.

In some embodiments, the photoresist104′ is disposed by spin coating or any other suitable process. In some embodiments, some portions of the photoresist104′ are removed by etching or any other suitable process. In some embodiments, at least a portion of the second dielectric layer102cis exposed through the patterned mask104after the formation of the patterned mask104as shown inFIG.9.

Referring toFIGS.10to12, portions of the first dielectric layer102a, the conductive layer102band the second dielectric layer102cexposed through the patterned mask104are removed to form a first trench105according to step S204inFIG.3. In some embodiments, the first trench105extends toward the first surface101aof the semiconductor substrate101and is adjacent to the second dielectric layer102c, the conductive layer102band the first dielectric layer102a.

In some embodiments, the formation of the trench105includes removing a portion of the second dielectric layer102cas shown inFIG.10, removing a portion of the conductive layer102bas shown inFIG.11, and removing a portion of the first dielectric layer102aas shown inFIG.12.

In some embodiments, the removal of the portion of the second dielectric layer102c, the removal of the portion of the conductive layer102band the removal of the portion of the first dielectric layer102ainclude etching or any other suitable process. In some embodiments, at least a portion of the first surface101aof the semiconductor substrate101is exposed after the formation of the first trench105as shown inFIG.12. In some embodiments as shown inFIG.13, after the formation of the first trench105, the patterned mask104is removed by etching, stripping or any other suitable process.

Referring toFIGS.14and15, a spacer102dsurrounding the first dielectric layer102a, the conductive layer102band the second dielectric layer102cis formed according to step S205. In some embodiments, the spacer102dis formed by disposing a spacer material102d′ over the semiconductor substrate101and the second dielectric layer102cand conformal to the first trench105as shown inFIG.14, and then removing portions of the spacer material102d′ disposed over the semiconductor substrate101and over the second dielectric layer102cas shown inFIG.15.

In some embodiments, the spacer material102d′ and the spacer102dinclude nitride and oxide. In some embodiments, the spacer material102d′ is disposed by deposition, CVD or any other suitable process. In some embodiments, the portions of the spacer material102d′ disposed over the semiconductor substrate101and the second dielectric layer102care removed by etching or any other suitable process. In some embodiments, at least a portion of the first surface101aof the semiconductor substrate101and at least a portion of the second dielectric layer102care exposed after the formation of the spacer102das shown inFIG.15.

In some embodiments, the formation of the spacer102dincludes formation of a first layer102jas shown inFIGS.16and17, formation of a second layer102kas shown inFIGS.18and19, and formation of a third layer102mas shown inFIGS.20and21. In some embodiments, the first layer102jis formed by disposing a first layer material102j′ over the semiconductor substrate101and conformal to the first trench105as shown inFIG.16, and then removing some portions of the first layer material102jover the semiconductor substrate101and over the second dielectric layer102cto form the first layer102jas shown inFIG.17.

In some embodiments, the second layer102kis formed by disposing a second layer material102k′ over the semiconductor substrate101and conformal to the first layer102jas shown inFIG.18, and then removing some portions of the second layer material102k′ over the semiconductor substrate101and over the second dielectric layer102cto form the second layer102kas shown inFIG.19.

In some embodiments, the third layer102mis formed by disposing a third layer material102m′ over the semiconductor substrate101and conformal to the second layer102kas shown inFIG.20, and then removing some portions of the third layer material102m′ over the semiconductor substrate101and over the second dielectric layer102cto form the third layer102mas shown inFIG.21. In some embodiments, the spacer102dincluding the first layer102j, the second layer102kand the third layer102mis formed as shown inFIG.21. In some embodiments, the first layer102jand the third layer102minclude nitride, and the second layer102kincludes oxide.

Referring toFIG.22, an energy-decomposable mask106is disposed over the second dielectric layer102cand the spacer102daccording to step S206inFIG.3. In some embodiments, the energy-decomposable mask106is disposed by deposition, CVD or any other suitable process. In some embodiments, the energy-decomposable mask16is thermally decomposable, photonically decomposable, electron-beam (e-beam) decomposable, or the like. In some embodiments, the energy-decomposable mask106can be decomposed by any suitable kind of energy such as heat, infrared (IR), ultraviolet (UV), e-beam or the like. In some embodiments, the energy-decomposable mask106includes a cross-linking compound having a functional group or a double bonding. In some embodiments, the energy-decomposable mask106includes polymer, polyimide, resin, epoxy or the like.

Referring toFIG.23, a portion106aof the energy-decomposable mask106is irradiated by an electromagnetic radiation R according to step S207inFIG.3. In some embodiments, the portion106aof the energy-decomposable mask106irradiated by the electromagnetic radiation R is disposed at a periphery106bof the energy-decomposable mask106. In some embodiments, the portion106aof the energy-decomposable mask106irradiated by the electromagnetic radiation is in contact with the spacer102dand the second dielectric layer102c.

In some embodiments, the electromagnetic radiation R irradiates the periphery106bof the energy-decomposable mask106to treat the portion106aof the energy-decomposable mask106. As a result, the portion106aof the energy-decomposable mask106becomes easily removable. In some embodiments, the electromagnetic radiation R is emitted laterally toward the portion106aof the energy-decomposable mask106. In some embodiments, the electromagnetic radiation R is infrared (IR), ultraviolet (UV), electron beam (e-beam) or the like.

Referring toFIG.24, the portion106aof the energy-decomposable mask106irradiated by the electromagnetic radiation R is removed according to step S208inFIG.3. In some embodiments, the portion106aof the energy-decomposable mask106is removed by etching or any other suitable process. After the removal of the portion106aof the energy-decomposable mask106, at least portions of the second dielectric layer102cand the spacer102dare exposed through the energy-decomposable mask106. In some embodiments, a width W5of the energy-decomposable mask106after the removal of the portion106aof the energy-decomposable mask106irradiated by the electromagnetic radiation R is substantially less than a width W1of the second dielectric layer102cafter the formation of the first trench105.

Referring toFIG.25, a portion of the second dielectric layer102cexposed through the energy-decomposable mask106is removed according to step209inFIG.3. In some embodiments, the portion of the second dielectric layer102cexposed through the energy-decomposable mask106is removed by etching or any other suitable process. After the removal of the portion of the second dielectric layer102cexposed through the energy-decomposable mask106, the second dielectric layer102cincludes a portion having a first width W1and a portion having a second width W2higher than the portion having the first width W1, wherein the second width W2is substantially less than the first width W1. In some embodiments, the second dielectric layer102cincluding a first portion102eand a second portion102fover the first portion102eis formed.

In some embodiments, a portion of the spacer102dexposed through the energy-decomposable mask106is removed as shown inFIG.25. In some embodiments, the portion of the spacer102dexposed through the energy-decomposable mask106is removed by etching or any other suitable process. After the removal of the portion of the spacer102dexposed through the energy-decomposable mask106, the second portion102fof the second dielectric layer102cis exposed through the spacer102d. In some embodiments, the removal of the portion of the second dielectric layer102cexposed through the energy-decomposable mask106and the removal of the portion of the spacer102dexposed through the energy-decomposable mask106are performed separately or simultaneously.

After the removal of the portion of the second dielectric layer102cexposed through the energy-decomposable mask106and the removal of the portion of the spacer102dexposed through the energy-decomposable mask106, a bit line102is formed and a gap103is formed between two adjacent bit lines102. In some embodiments, a lower portion of the gap103has a third width W3, and a higher portion of the gap103has a fourth width W4substantially greater than the third width W3.

In some embodiments, after the formation of the gap103, the energy-decomposable mask106over the second dielectric layer102cis removed as shown inFIG.26. In some embodiments, the energy-decomposable mask106is removed by etching or any other suitable process. In some embodiments, the memory device100ofFIG.1is formed as shown inFIG.26.

In an aspect of the present disclosure, a memory device is provided. The memory device includes a semiconductor substrate including a first surface; and a bit line disposed on the first surface of the semiconductor substrate, wherein the bit line includes a first dielectric layer, a conductive layer disposed over the first dielectric layer, a second dielectric layer disposed over the conductive layer, and a spacer surrounding the first dielectric layer, the conductive layer and the second dielectric layer, wherein the second dielectric layer includes a first portion surrounded by the spacer and a second portion disposed over the first portion and exposed through the spacer, wherein a first width of the first portion is substantially greater than a second width of the second portion.

In another aspect of the present disclosure, a memory device is provided. The memory device includes a semiconductor substrate including a first surface; a first bit line and a second bit line disposed on the first surface of the semiconductor substrate and adjacent to each other, wherein the first bit line and the second bit line respectively include a first dielectric layer, a conductive layer disposed over the first dielectric layer, a second dielectric layer disposed over the conductive layer, and a spacer surrounding the first dielectric layer, the conductive layer and the second dielectric layer; and a gap disposed between the first bit line and the second bit line, wherein the gap has a first width and a second width substantially different from the first width.

In another aspect of the present disclosure, a method of manufacturing a memory device is provided. The method includes steps of providing a semiconductor substrate having a first surface; disposing a first dielectric layer over the first surface of the semiconductor substrate, a conductive layer over the first dielectric layer, and a second dielectric layer over the conductive layer; disposing a patterned mask over the second dielectric layer; removing portions of the second dielectric layer, the conductive layer and the first dielectric layer exposed through the patterned mask to form a first trench; forming a spacer surrounding the first dielectric layer, the conductive layer and the second dielectric layer; disposing an energy-decomposable mask over the second dielectric layer and the spacer; irradiating a portion of the energy-decomposable mask by an electromagnetic radiation; removing the portion of the energy-decomposable mask irradiated by the electromagnetic radiation; and removing a portion of the second dielectric layer exposed through the energy-decomposable mask.

In conclusion, because a portion of a second dielectric layer of a bit line is removed to form a stepped profile, a distance or a critical dimension between two adjacent bit lines can be increased and bridging of two adjacent bit lines can be prevented. More specifically, because the bit line has the stepped profile around a periphery of the bit line, a subsequent filling of a gap between two adjacent bit lines with conductive or insulating material can be performed more efficiently. The gap between two adjacent bit lines can be filled completely without formation of voids or while minimizing the formation of voids. Therefore, performance of the memory device and a process of manufacturing the memory device are improved.