Method of fabricating a fin field effect transistor (FinFET) device

A method of fabricating a semiconductor using a fin field effect transistor (FINFET) is disclosed. In a particular embodiment, a method includes depositing, on a silicon substrate, a first dummy structure having a first sidewall and a second sidewall separated by a first width. The method also includes depositing, on the silicon substrate, a second dummy structure concurrently with depositing the first dummy structure. The second dummy structure has a third sidewall and a fourth sidewall that are separated by a second width. The second width is substantially greater than the first width. The first dummy structure is used to form a first pair of fins separated by approximately the first width. The second dummy structure is used to form a second pair of fins separated by approximately the second width.

The present disclosure is generally related to a method of fabricating a fin field effect transistor (FinFET) device.

II. DESCRIPTION OF RELATED ART

Static random access memory (SRAM) bitcells may be implemented using vertical double-gate or tri-gate fin field effect transistors (FinFETs). Using FinFETs enables SRAM bitcells to have one or more benefits over conventional planar Complimentary Metal Oxide Semiconductor (CMOS) technology, such as a smaller bitcell size, a larger cell current, a lower cell leakage current, or a higher static noise margin. FinFETs may be formed using a sidewall transfer method that yields an even number of fins. When the sidewall transfer method is used to fabricate a FinFET device having an odd number of fins, an even number of fins is created and then a fin is removed. However, removing one fin to yield an odd number of fins is a difficult process and requires a high degree of precision.

In a particular embodiment, a method includes depositing, on a silicon substrate, a first dummy structure having a first sidewall and a second sidewall separated by a first width. The method also includes depositing, on the silicon substrate, a second dummy structure concurrently with depositing the first dummy structure. The second dummy structure has a third sidewall and a fourth sidewall that are separated by a second width. The second width is substantially greater than the first width. The first dummy structure is used to form a first pair of fins separated by approximately the first width. The second dummy structure is used to form a second pair of fins separated by approximately the second width.

In another particular embodiment, an electronic device is disclosed. The electronic device includes a first pair of fins that are first and second protrusions on an etched silicon substrate. The first protrusion is substantially parallel to the second protrusion. The first protrusion and the second protrusion are separated by a first width. The electronic device also includes a second pair of fins that are third and fourth protrusions separated by a second width on the etched silicon substrate. The second width is different than the first width. The electronic device also includes a third pair of fins that are fifth and sixth protrusions separated by a third width on the etched silicon substrate. The second pair of fins is located between the first pair of fins and the third pair of fins. The first and second pair of fins are formed by applying a lithographic mask with dummy structures having different sizes.

In another particular embodiment, a method of fabricating a static random access memory (SRAM) is disclosed. The method includes forming a first dummy structure using a lithographic mask. The first dummy structure has a first width and first laterally opposed sidewalls. The method further includes forming a second dummy structure concurrently with forming the first dummy structure. The second dummy structure has a second width that is substantially greater than the first width. The second dummy structure has second laterally opposed sidewalls. The method further includes forming a third dummy structure concurrently with the first dummy structure. The third dummy structure has the first width and has third laterally opposed sidewalls. The method further includes depositing a first insulating material on the first laterally opposed sidewalls to form a first insulating spacer and a second insulating spacer. The method further includes depositing a second insulating material on the second laterally opposed sidewalls to form a third insulating spacer and a fourth insulating spacer. The method further includes depositing a third insulating material on the third laterally opposed sidewalls to form a fourth insulating spacer and a fifth insulating spacer. The method further includes removing the first dummy structure, removing the second dummy structure, and removing the third dummy structure.

In another particular embodiment a method includes depositing, on a silicon substrate, a first dummy structure having a first sidewall and a second sidewall separated by a first width. The method also includes depositing, on the silicon substrate, a second dummy structure concurrently with depositing the first dummy structure. The second dummy structure has a third sidewall and a fourth sidewall separated by a second width. The second width is substantially greater than the first width. The method also includes depositing a first insulating material to form a first insulating spacer adjacent to the first sidewall and to form a second insulating spacer adjacent to the second sidewall. The method also includes depositing a second insulating material to form a third insulating spacer adjacent to the third sidewall and a fourth insulating spacer adjacent to the fourth sidewall. The method also includes removing the first dummy structure from the silicon substrate. The method also includes removing the second dummy structure from the silicon substrate.

A particular advantage provided by at least one of the disclosed embodiments is a simplified dummy structure patterning process due to larger feature sizes for certain field effect transistors (FETs) of a bitcell. Another particular advantage provided by at least one of the disclosed embodiments is that one fin does not have to be removed to form a pull-up FET because two fins are used for each pull-up device.

V. DETAILED DESCRIPTION

Referring toFIG. 1, a first illustrative embodiment of a portion of a process to fabricate a fin field effect transistor (FinFET) device is disclosed and generally designated100.FIG. 1illustrates a lithographic mask102that includes a first window106, a second window108, and a third window110. The lithographic mask102may be used to concurrently deposit a first dummy structure112, a second dummy structure114, and a third dummy structure116on a silicon substrate104via a lithography process.

The first dummy structure112has a first width118, a first sidewall120and a second sidewall122. In an illustrative embodiment, the first sidewall120and the second sidewall122are first laterally opposed sidewalls. The second dummy structure114has a second width124. In an illustrative embodiment, the second width124may be different than the first width118. For example, the second width124may be substantially greater than the first width118.

The second dummy structure114has a third sidewall126and a fourth sidewall128. In an illustrative embodiment, the third sidewall126and the fourth sidewall128are referred to as second laterally opposed sidewalls. The third dummy structure116has a third width130. In an illustrative embodiment, the third width130may be approximately the same as the first width118. The third dummy structure116has a fifth sidewall132and a sixth sidewall134. In an illustrative embodiment, the fifth sidewall132and the sixth sidewall134are referred to as third laterally opposed sidewalls. An example of a side view of fabricating a fin field effect transistor (FinFET) device is illustrated inFIG. 9.

In a particular illustrative non-limiting embodiment, the second width124is greater than the first width118and the second width124is greater than the third width130. In an illustrative non-limiting embodiment, the first width118and the third width124are between 10 and 30 nanometers (nm) wide and the second width130is between 40 and 70 nm wide.

The first sidewall120and the second sidewall122are used to form dual-fin transistors. Similarly, the fifth sidewall132and the sixth sidewall134are used to form dual-fin transistors. Making the second width124substantially greater than the first width118and the third width130enables the third sidewall126and the fourth sidewall128to be used in separate one-fin devices. When the second width124is substantially equal in size to the first width118and to the third width130, either the third sidewall126or the fourth sidewall128is removed in order to create separate one-fin devices.

Thus, forming a second dummy structure with a width greater than the width of the first dummy structure and greater than the width of the third dummy structure, enables a simplified dummy structure patterning process. As will be discussed in more detail inFIG. 4, the greater width of the second dummy structure enables portions of material deposited on either side of the dummy structure to be easily removed, enabling the second dummy structure to be used to form separate one-fin devices. Further, this method does not require one fin to be removed as each fin is used for an FET, such as a pull-up FET. The methods described may be applied to fabricate any FinFET that has a similar layout, i.e. a layout with a double fin and a single fine. For example, the methods described may be applied to fabricate any FinFET that has multiples of the layout with a double fin and a single fin.

Referring toFIG. 2, a second illustrative embodiment of a portion of a process to fabricate a fin field effect transistor (FinFET) device is disclosed and generally designated200. The silicon substrate104includes the first dummy structure112having the first laterally opposed sidewalls120and122, the second dummy structure114having the second laterally opposed sidewalls126and128, and the third dummy structure116having the third laterally opposed sidewalls132and134.

A first insulating material202may be deposited on the first laterally opposed sidewalls120and122to form a first insulating spacer204and a second insulating spacer206. A second insulating material208may be deposited on the second laterally opposed sidewalls126and128to form a third insulating spacer210and a fourth insulating spacer212. A third insulating material214may be deposited on the third laterally opposed sidewalls132and134to form a fifth insulating spacer216and a sixth insulating spacer218.

Initially, the first insulating spacer204and the second insulating spacer206are joined. However, in subsequent steps, portions of the insulating material that joins the first insulating spacer204and the second insulating spacer206are removed, enabling a first fin to be formed using the first insulating spacer as an etch mask and enabling a second fin to be formed using the second insulating spacer as an etch mask. Further, in subsequent steps, portions of the insulating material that joins the third insulating spacer210and the fourth insulating spacer212are removed, enabling a third fin and a fourth fin to be formed. In addition, portions of the insulating material that joins the fifth insulating spacer216and the sixth insulating spacer218are removed, enabling a fifth fin and a sixth fin to be formed.

Referring toFIG. 3, a third illustrative embodiment of a portion of a process to fabricate a fin field effect transistor (FinFET) device is disclosed and generally designated300. InFIG. 3, the first dummy structure112, the second dummy structure114, and the third dummy structure116are removed from the silicon substrate104. AlthoughFIG. 3illustrates that the dummy structures112,114, and116are removed as whole structures, the dummy structures112,114, and116may be removed via an etch or otherwise dissolved.

Referring toFIG. 4, a fourth illustrative embodiment of a portion of a process to fabricate a fin field effect transistor (FinFET) device is disclosed and generally designated400. InFIG. 4, the first insulating spacer204, the second insulating spacer206, the third insulating spacer210, the fourth insulating spacer212, the fifth insulating spacer216, and the sixth insulating spacer218are depicted on the silicon substrate104. A first negative photo resist402is performed on the third insulating spacer210and a second negative photo resist404is performed the fourth insulating spacer212.

Performing the photo resists402and404on the insulating spacers210and212enables two single fin devices to be easily formed because the insulating spacers210and212are separated by a width substantially greater than the width of the insulating spacers204and206. In contrast, when the insulating spacers210and212are separated by a width substantially equivalent to the width of the insulating spacers204and206, then forming a one fin device involves trying to remove one of the insulating spacers210and212. Removing one of the insulating spacers210and212is typically difficult when the insulating spacers210and212are separated by a width substantially equivalent to the width of the insulating spacers204and206because of the very small width between the insulating spacers210and212.

Referring toFIG. 5, a fifth illustrative embodiment of a portion of a process to fabricate a fin field effect transistor (FinFET) device is disclosed and generally designated500.FIG. 5illustrates the FinFET device inFIG. 4after performing the first negative photo resist402and after performing the second negative photo resist404.FIG. 5illustrates that the first negative photo resist402has removed a portion of the third insulating spacer210and that the second photo resist404has removed a portion of the fourth insulating spacer212. Removing a portion of the third insulating spacer210enables the third insulating spacer210to be used for a single fin device. Additionally, removing a portion of the fourth insulating spacer212enables the fourth insulating spacer212to be used for a single fin device.

Referring toFIG. 6, a sixth illustrative embodiment of a portion of a process to fabricate a fin field effect transistor (FinFET) device is disclosed and generally designated600. InFIG. 6, a contact pad structure602, a contact pad structure604, and a contact pad structure606are deposited over their respective portions of the first insulating spacer204. The contact pad structure602, the contact pad structure604, and the contact pad structure606are deposited over their respective portions of the second insulating spacer206.

A contact pad structure608and a contact pad structure610may be deposited on the third insulating spacer210. A contact pad structure612and a contact pad structure614may be deposited on the fourth insulating spacer212. A contact pad structure616, a contact pad structure618, and a contact pad structure620may be deposited on the fifth insulating spacer216and may be deposited on the sixth insulating spacer218.

Referring toFIG. 7, a seventh illustrative embodiment of a portion of a process to fabricate a fin field effect transistor (FinFET) device is disclosed and generally designated700. An etch702is applied to the silicon substrate104inFIG. 6to form the etched silicon substrate704. In an illustrative embodiment, the etch702may be a silicon etch.

The insulating spacers204,206,210,212,216, and218inFIG. 6function as etch masks to so that the etch702forms a plurality of fins. The etch702may be used to form a first fin712under the first insulating spacer204, a second fin714under the second insulating spacer206, a third fin722under the third insulating spacer210, a fourth fin728under the fourth insulating spacer212, a fifth fin736under the fifth insulating spacer216, and a sixth fin738under the sixth insulating spacer218. The etch702may further be used to form seventh and eighth fins742and744under the first and second insulating spacers204and206, and ninth and tenth fins746and748under the fifth and the sixth insulating spacers216and218. Thus, the etch702may use the insulating spacers204,206,210,212,216, and218as etch masks to form, on the etched silicon substrate704, the fins712,714,742,744,722,728,736,738,746, and748. In an illustrative embodiment, at least one of the fins712,714,742,744,722,728,736,738,746, and748may be less than fifteen nanometers wide.

Further, the contact pad structures602,604, and606inFIG. 6function as etch masks so that the etch702forms contacts706,708, and710, respectively. Furthermore, after the etch702is complete the contact pad structures608and610may be removed to expose contacts718and720, respectively. In addition, after the etch702is complete the contact pad structures612and614may be removed to expose contacts724and726, respectively. Additionally, after the etch702is complete the contact pad structures616,618, and620may be removed to expose contacts730,732, and734.

Referring toFIG. 8, an eighth illustrative embodiment of a portion of a process to fabricate a fin field effect transistor (FinFET) device is disclosed and generally designated800.FIG. 8illustrates how the FinFET fabrication process described herein may be used to fabricate a six-transistor (6T) static random access memory (SRAM) bitcell.

A first field effect transistor802may be formed by depositing on the etched silicon substrate704a first gate structure804across the fins712and714and by depositing a gate pad area806at one end of the first gate structure804. The gate pad area806may enable a signal or voltage to be applied to the first gate structure804to enable the first gate structure804to modulate a current through the fins712and714. In an illustrative embodiment, the first field effect transistor (FET)802may be a pass-gate field effect transistor.

A second field effect transistor808and a third field effect transistor810may be formed by depositing a second gate structure812across the fins742,744, and722, and by depositing a gate pad area814at one end of the second gate structure812. The gate pad area814may enable a voltage or signal to be applied to the second gate structure812to enable the second gate structure812to modulate a current through the fins742,744, and722via the second gate structure812. In an illustrative embodiment, the second field effect transistor808is a pull-down field effect transistor and the third field effect transistor810is a pull-up field effect transistor.

A fourth field effect transistor816may be formed by depositing a third gate structure818across the fins746and748and by depositing a gate pad area820at one end of the third gate structure818. The gate pad area820may enable a signal or voltage to be applied to the first gate structure818to enable a current to be modulated through the fins746and748. In an illustrative embodiment, the fourth field effect transistor816is a pass-gate field effect transistor.

A fifth field effect transistor822and a sixth field effect transistor824may be formed by depositing a fourth gate structure826across the fins728,736, and738, and by depositing a gate pad area828at one end of the fourth gate structure826. The gate pad area828may enable a signal or voltage to be applied the fourth gate structure826to enable the fourth gate structure826to modulate a current through the fins728,736, and738. In an illustrative embodiment, the second field effect transistor808is a pull-down field effect transistor and the third field effect transistor810is a pull-up field effect transistor. In an illustrative embodiment, the fifth field effect transistor is a pull-down field effect transistor and the sixth field effect transistor824is a pull-up field effect transistor. The transistors802,808,810,816,822, and824may be interconnected to operate as a 6T SRAM bitcell.

Thus, by depositing a dummy structure114inFIG. 1having the second width124that is substantially greater than the first width118, the resulting fins722and728are separated by approximately the second width124. The second width124enables the transistors810and824to each use a single fin each while the transistors802,808,816and822each use two fins, because the second width124is substantially greater than the first width118and the third width130.

FIGS. 9-12depict a sidewall transfer method using dummy structures having variable widths. Referring toFIG. 9, a ninth illustrative embodiment of a portion of a process to fabricate a fin field effect transistor (FinFET) device is disclosed and generally designated900.FIG. 9illustrates fabricating a FinFET using a side view perspective. In an illustrative embodiment,FIG. 9depicts a side view of the portion of the fabrication process100ofFIG. 1.

A lithographic mask902includes a first window906, a second window908, and a third window910. The lithographic mask902may be used to concurrently form a first dummy structure912, a second dummy structure914, and third dummy structure916on a silicon substrate904, using a single lithographic process.

The first dummy structure912has first laterally opposed sidewalls920and922separated by a first width918. The second dummy structure914has second laterally opposed sidewalls926and928separated by a second width924. In one illustrative embodiment, the second width924may be different than the first width918. For example, the second width924may be substantially greater than the first width918. The third dummy structure916has third laterally opposed sidewalls932and934separated by a third width930.

Referring toFIG. 10, a tenth illustrative embodiment of a portion of a process to fabricate a fin field effect transistor (FinFET) device is disclosed and generally designated1000. In an illustrative embodiment,FIG. 10depicts a side view of the portion of the fabrication process200ofFIG. 2. The silicon substrate904includes the first dummy structure912having the first laterally opposed sidewalls920and922, the second dummy structure914having the second laterally opposed sidewalls926and928, and the third dummy structure916having the third laterally opposed sidewalls932and934. Insulating materials1002,1008, and1014are deposited on the laterally opposed sidewalls920,922,926,928,932and934to form insulating spacers1004,1006,1010,1012,1016, and1018, respectively.

Referring toFIG. 11, an eleventh illustrative embodiment of a portion of a process to fabricate a fin field effect transistor (FinFET) device is disclosed and generally designated1100. In an illustrative embodiment,FIG. 11depicts a side view of the portion of the fabrication process300ofFIG. 3. InFIG. 11, the first dummy structure912, the second dummy structure914, and the third dummy structure916are removed from the silicon substrate904. AlthoughFIG. 11illustrates that the dummy structures912,914, and916are removed as whole structures, the dummy structures912,914, and916may be removed via an etch or otherwise dissolved. After removing the dummy structures912,914, and916, the insulating spacers1004,1006,1010,1012,1016, and1018remain on the silicon substrate904.

Referring toFIG. 12, a twelfth illustrative embodiment of a portion of a process to fabricate a fin field effect transistor (FinFET) device is disclosed and generally designated1200. In an illustrative embodiment,FIG. 12depicts a side view of the fabrication process700ofFIG. 7with contacts removed for illustration purposes. The FinFET device inFIG. 12illustrates the result after applying an etch1202and removing the insulating spacers1004,1006,1010,1012,1016, and1018from the silicon substrate904ofFIG. 11. In an illustrative embodiment, the etch1202may be a silicon etch. The etch1202is used to form a first fin1206under the first insulating spacer1004, a second fin1208under the second insulating spacer1006, a third fin1210under the third insulating spacer1010, a fourth fin1212under the fourth insulating spacer1012, a fifth fin1214under the fifth insulating spacer1016, and a sixth fin1216under the sixth insulating spacer1018. Thus, the etch1202uses the insulating spacers1004,1006,1010,1012,1016, and1018ofFIG. 11as etch masks to form the fins1206,1208,1210,1212,1214, and1216. In an illustrative embodiment, at least one of the fins1206,1208,1210,1212,1214, and1216may be less than fifteen nanometers wide.

Each fin is a protrusion on the etched silicon substrate1204. The fins are formed in pairs, such as, the first pair of fins1206and1208, the second pair of fins1210and1212, and the third pair of fins1214and1216. The fins in each pair of fins is substantially parallel to each other and separated by widths corresponding to the widths of the dummy structures912,914, and916ofFIG. 9. The first pair of fins1206and1208are separated by approximately the first width118ofFIG. 1, the second pair of fins1210and1212are separated by approximately the second width124, and the third pair of fins1214and1216are separated by approximately the third width130. The second pair of fins1210and1212is located between the first pair of fins1206and1208, and the third pair of fins1214and1216and may be used in separate single-fin transistors, such as the transistors810and824inFIG. 8.

FIG. 13is a flow diagram of a first illustrative embodiment of a method of fabricating a fin field effect transistor (FinFET) device. At1302, a first dummy structure is deposited on a silicon substrate. The first dummy structure has a first sidewall and a second sidewall separated by a first width. Continuing to1304a second dummy structure is deposited on the silicon substrate concurrently with depositing the first dummy structure. The second dummy structure has a third sidewall and a fourth sidewall separated by a second width. The second width is substantially greater than the first width. Moving to1306, the first dummy structure is used to form a first pair of fins separated by approximately the first width and the second dummy structure is used to form a second pair of fins separated by approximately the second width. In a particular embodiment, the first and second dummy structures are the dummy structures106and108inFIG. 1.

Advancing to1308, a first insulating material is deposited to form a first insulating spacer adjacent to the first sidewall and to form a second insulating spacer adjacent to the second sidewall. Proceeding to1310, a second insulating material is deposited to form a third insulating spacer adjacent to the third sidewall and a fourth insulating spacer adjacent to the fourth sidewall. In a particular embodiment, the first, second, third and fourth insulating spacers are the insulating spacers204,206,210, and212inFIG. 2.

Continuing to1312, the first and second dummy structures are removed from the silicon substrate. In a particular embodiment, the first and second dummy structures are removed by dissolving the dummy structures using an etching process or other process for dissolving the dummy structures. Advancing to1314, a portion of at least one of the third insulating spacer and the fourth insulating spacer is removed. In a particular embodiment, a negative photo resist process is performed to remove a portion of at least one of the third and fourth insulating spacers as illustrated inFIG. 5.

Proceeding to1316, contact pad structures are deposited over at least a portion of at least one of the first insulating spacer, the second insulating spacer, the third insulating spacer, and the fourth insulating spacer. In a particular embodiment, the contact pad structures may be deposited over at least a portion of at least one of the insulating spacers as illustrated inFIG. 6.

Moving to1318, an etch is performed using the first insulating spacer, the second insulating spacer, the third insulating spacer, and the fourth insulating spacer as etch masks to form a plurality of fins. In a particular embodiment, the etch that is performed is a silicon etch process. An example of the result of the etch is illustrated inFIG. 7. In a particular embodiment, the plurality of fins are implemented in a six-transistor (6T) static random access memory (SRAM) bitcell.

Continuing to1320, at least one field effect transistor (FET) is formed to enable a first gate structure to modulate a current through at least one fin of the plurality of fins. In a particular embodiment, at least one field effect transistor is one of a pull-up FET, a pull-down FET and a pass-gate FET as illustrated inFIG. 8. In a particular embodiment, at least one fin is less than fifteen nanometers wide.

Advancing to1322, a pull-down FET is formed using a first gate to modulate a current through a fin formed using the first insulating spacer and the second insulating spacer. Moving to1324, a pull-up FET is formed using a second gate to modulate a current through a fin formed using the third insulating spacer or the fourth insulating spacer. The method ends at1326.

FIG. 14is a flow diagram of a second illustrative embodiment of a method of fabricating a fin field effect transistor (FinFET) device. At1402a first dummy structure is formed using a lithographic mask. The first dummy structure has a first width and first laterally opposed sidewalls. Continuing to1404, a second dummy structure is formed concurrently with the first dummy structure. The second dummy structure has second laterally opposed sidewalls. The second dummy structure may have a second width greater than the first width. In an illustrative embodiment, the second dummy structure has a second width significantly greater than the first width. Moving to1406, a third dummy structure is formed. The third dummy structure has third laterally opposed sidewalls. The third dummy structure has the first width. In a particular embodiment, the first, second, and third dummy structures may be the dummy structures112,114, and116inFIG. 1.

Advancing to1408, a first insulating material is deposited on the first laterally opposed sidewalls to form a first insulating spacer and a second insulating spacer. Moving to1410, a second insulating material is deposited on the second laterally opposed sidewalls to form a third insulating spacer and a fourth insulating spacer. Proceeding to1412, a third insulating material is deposited on the third laterally opposed sidewalls to form a fifth insulating spacer and a sixth insulating spacer. In a particular embodiment, the first, second, and third laterally opposed sidewalls may be the sidewalls204,206,210,212,216, and218inFIG. 2. Continuing to1414, the first dummy structure, the second dummy structure, and the third dummy structure are removed.

Advancing to1416, an etch is performed to form a first fin under the first insulating spacer, a second fin under the second insulating spacer, a third fin under the third insulating spacer, a fourth fin under the fourth insulating spacer, a fifth fin under the fifth insulating spacer, and a sixth fin under the sixth insulating spacer. In a particular embodiment, the fins712,714,722,728,736,738,742,744,746, and748are formed via the etch702as illustrated inFIG. 7.

Moving to1418, a pull-down field effect transistor (FET) is formed using a first gate to modulate a current through the first fin and through the second fin, a pull-up FET is formed using a second gate to modulate a current through the third fin or through the fourth fin, and a pass-gate FET is formed using a third gate to modulate a current through the fifth fin and through the sixth fin. In a particular embodiment, the pull-down FET is the FET808inFIG. 8, the pull-up FET is FET810, and the push gate is FET802. The method ends at1420.

FIG. 15is a flow diagram of a third illustrative embodiment of a method of fabricating a fin field effect transistor (FinFET) device. At1502, a first dummy structure is deposited on a silicon substrate. The first dummy structure has a first sidewall and a second sidewall separated by a first width. Continuing to1504, a second dummy structure is deposited on the silicon substrate concurrently with depositing the first dummy structure. The second dummy structure has a third sidewall and a fourth sidewall separated by a second width, wherein the second width is substantially greater than the first width. In a particular embodiment, the first width is between 10 and 30 nanometers and the second width is between 40 and 70 nanometers. In a particular embodiment, the first dummy structure is the dummy structure112or116inFIG. 1and the second dummy structure is the dummy structure114.

Proceeding to1506, a first insulating material is deposited to form a first insulating spacer adjacent to the first sidewall and to form a second insulating spacer adjacent to the second sidewall. Moving to1508, a second insulating material is deposited to form a third insulating spacer adjacent to the third sidewall and a fourth insulating spacer adjacent to the fourth sidewall.

Advancing to1510, the first dummy structure is removed from the silicon substrate. Continuing to1512, the second dummy structure is removed from the silicon substrate. In a particular embodiment, the first and second dummy structures112and114inFIG. 1may be removed from the silicon substrate104.

Proceeding to1514, a portion of at least one of the third insulating spacer and the fourth insulating spacer is removed. In a particular embodiment, a portion of the insulating spacers210and212is removed as inFIG. 500. In an illustrative embodiment, a photo resist process, such as a negative photo resist process is used to remove the insulating spacers. Advancing to1516, contact pad structures are deposited over at least a portion of at least one of the first insulating spacer, the second insulating spacer, the third insulating spacer, and the fourth insulating spacer. In a particular embodiment, the contact pad structures602,604,606,608,610,612,614,616,618, and620are deposited on insulating spacers204,206,210,212,216, and218, as inFIG. 6.

Moving to1518, an etch is performed using the first insulating spacer, the second insulating spacer, the third insulating spacer, and the fourth insulating spacer as etch masks to form a plurality of fins. In a particular embodiment, the etch702is a silicon etch, and the etch702is used to create the fins712,714,722,728,736,738,742,744,746, and748as inFIG. 7. The method ends at1520.