Semiconductor devices with multiple heat sinks

A semiconductor device that includes multiple heat sinks is provided along with methods for forming a semiconductor device having multiple heat sinks. The semiconductor device includes a first heat sink that is configured as a conductive lead frame. The conductive lead frame is electrically coupled to a conducting area of a semiconductor die. The semiconductor device also includes a second heat sink that is configured as a conductive clip. The conductive clip is electrically coupled to another conducting area of the die. Alternative embodiments of the device may include more than two heat sinks.

TECHNICAL FIELD

The present embodiments relate generally to the field of semiconductor devices and, more particularly, to semiconductor devices that include dual heat sinks.

BACKGROUND

Rapid growth in the electrical industry has produced a need for electrical devices that are smaller in size but that operate in high-power architectures to support multiple features/functions. A high-power device generally supports relatively higher currents and consequently higher power, which requires the device to have efficient heat dissipation capability. While heat sinks have typically been used in electronic devices as a means for facilitating heat dissipation, surface-mount discrete power semiconductor devices typically include no heat sink or a single heat sink because of the size constraints of these devices. A high-power device having no heat sink or only a single heat sink may not adequately dissipate heat from a high-power device, so there is a need for semiconductor devices that include more than a single heat sink.

Each publication and/or patent application mentioned in this specification is herein incorporated by reference in its entirety to the same extent as if each individual publication and/or patent application was specifically and individually indicated to be incorporated by reference.

DETAILED DESCRIPTION

A semiconductor device or “device” is provided that includes a semiconductor die coupled to multiple heat sinks. The device of an embodiment includes a first heat sink configured as a conductive lead frame that is electrically coupled to a conducting area of a die. The device also includes a second heat sink configured as a conductive clip that is electrically coupled to another conducting area of the die. Alternative embodiments of the device may include more than two heat sinks.

The following description provides specific details for a thorough understanding of, and enabling description for, embodiments of a semiconductor device that includes multiple heat sinks along with the corresponding processes for device formation. However, one skilled in the art will understand that the devices and processes described herein may be practiced without these details. In other instances, well-known structures and functions have not been shown or described in detail to avoid unnecessarily obscuring the description of the embodiments described herein.

FIG. 1is an exploded view of a semiconductor device100that includes dual heat sinks10and50, under an embodiment. The device100includes but is not limited to a first heat sink10, a first region or layer of conductive solder20, a semiconductor die30, a second region or layer of conductive solder40, and a second heat sink50. Each of the first heat sink10and second heat sink50comprise a conductive material or a combination of materials some of which are conductive as appropriate to the device. The first heat sink10of an embodiment is configured as a conductive mounting platform10(also referred to as “lower heat sink10” or “bottom heat sink10”). The second heat sink50of an embodiment is configured as a conductive clip50(also referred to as “upper heat sink50” or “top heat sink50”). While the device formation processes of an embodiment use solder20and40to join the die30to the other components of the device100, alternative embodiments may use other compounds to join the die30to the other components of the device100as appropriate to the process and/or device100.

Alternative embodiments of the device may include more than two heat sinks but are not so limited. For example, the top heat sink of an alternative embodiment may be formed from two or more different heat sinks. Similarly, the bottom heat sink of an alternative embodiment may be formed from two or more different heat sinks.

FIG. 2is a perspective view of a bottom heat sink10of the device100, under an embodiment. The bottom heat sink10couples to a lead frame structure (not shown) and serves as a conductive mounting platform that receives the die30of a device100. Solder20is mounted or applied to one or more regions or areas of the bottom heat sink10, and a first surface of a semiconductor die30is mounted or coupled to the bottom heat sink10using the solder20. The first surface of the die30of an embodiment is a bottom surface, but the embodiment is not so limited. The bottom surface may be either of an anode or cathode of the die30as appropriate to the configuration of the device100and/or the top surface of the die30.

FIG. 3is a perspective view of a top heat sink50of a device100, under an embodiment. The top heat sink50couples or connects the die30to the lead of the lead frame structure (not shown). Consequently, solder40is mounted or applied to one or more regions or areas of a second surface of the die30, and the top heat sink50is mounted or coupled to the die30using the solder40. The second surface of the die30of an embodiment is a top surface, but the embodiment is not so limited. The top surface may be either of an anode or cathode of the die30as appropriate to the configuration of the device100and/or the bottom surface of the die30.

FIG. 4is a cross-sectional view of a device100that includes dual heat sinks10and50, under an embodiment. As described above with reference toFIG. 1, the device100includes but is not limited to a bottom heat sink10(conductive mounting platform10), a first region or layer of conductive solder20, a semiconductor die30, a second region or layer of conductive solder40, and a top heat sink50(conductive clip50). Further, the device100is encapsulated in a compound60that can include epoxy compounds and the like. Each of the bottom heat sink10and top heat sink50comprise a conductive material or a combination of materials some of which are conductive as appropriate to the device. The bottom heat sink10of an embodiment is configured as a conductive mounting platform10, while the top heat sink50of an embodiment is configured as a conductive clip50.

FIG. 5Ais a top perspective view of a device100that includes dual heat sinks, under an embodiment. The device is encapsulated in a compound60and includes, among other components, a top heat sink50, as described above with reference toFIG. 1andFIG. 4.

FIG. 5Bis a bottom perspective view of a device100that includes dual heat sinks, under an embodiment. The device is encapsulated in a compound60and includes, among other components, a bottom heat sink10, as described above with reference toFIG. 1andFIG. 4.

FIG. 6is a flow diagram600for forming a semiconductor device that includes multiple heat sinks, under an embodiment. The semiconductor device formation600includes mounting or applying602solder on one or more portions of a bottom heat sink in preparation for die attachment. The bottom heat sink is configured as a conductive mounting platform but is not so limited.

The semiconductor device formation600further includes mounting604a first surface of a semiconductor die on the solder surface. The first surface of an embodiment is a bottom surface of the die, but the embodiment is not so limited. The bottom surface may be either of an anode or cathode of the die as appropriate to the device and the configuration of the top surface of the die. This mounting604forms an electrical connection between a portion of the surface of the bottom heat sink and the die.

The semiconductor device formation600further includes mounting or applying606solder to a second surface of the die. The second surface of an embodiment is a top surface of the die, but the embodiment is not so limited. The top surface may be either of an anode or cathode of the die as appropriate to the device and the configuration of the bottom surface of the die.

The semiconductor device formation600further includes mounting or attaching608a top heat sink to the solder on the second surface of the die. This mounting608forms an electrical connection between a portion of the surface of the top heat sink and the die. Consequently, the combination of the bottom heat sink (e.g., conductive mounting platform), the die, and the top heat sink (e.g., conductive clip), along with the solder, forms an electrically conductive path between the die and each of the top and bottom heat sinks, but the embodiment is not so limited.

The semiconductor device formation600further includes forming610a packaging enclosure around the components of the semiconductor device. Forming the enclosure includes encapsulating or encasing the bottom heat sink, solder, die, and top heat sink in an epoxy or other suitable compound as appropriate to the device and using processes as appropriate to the device. Following formation of the packaging enclosure, the device is separated from the lead frame structure.

FIG. 7is an exploded view of a semiconductor device700that includes dual heat sinks710and750, under an alternative embodiment. The device700includes but is not limited to a first heat sink710, a first region or layer of conductive solder720, a semiconductor die730, a second region or layer of conductive solder740, and a second heat sink750. Each of the first heat sink710and second heat sink750comprise a conductive material or a combination of materials some of which are conductive as appropriate to the device. The first heat sink710of an embodiment is configured as a conductive mounting platform710(also referred to as “lower heat sink710” or “bottom heat sink710”). The second heat sink750of an embodiment is configured as a conductive clip750(also referred to as “upper heat sink750” or “top heat sink750”). The second heat sink750is coupled to one or more conductive leads770using solder780but is not so limited. While the device formation processes of an embodiment use solder720/740/780to join or connect various components of the device700, alternative embodiments may use other compounds to join the components of the device700as appropriate to the process and/or device700.

Alternative embodiments of the device may include more than two heat sinks but are not so limited. For example, the top heat sink of an alternative embodiment may be formed from two or more different heat sinks. Similarly, the bottom heat sink of an alternative embodiment may be formed from two or more different heat sinks.

FIG. 8is a perspective view of a bottom heat sink710of the device700, under an alternative embodiment. The bottom heat sink710couples to a lead frame structure (not shown) and serves as a conductive mounting platform that receives the die730of a device700. Solder720is mounted or applied to one or more regions or areas of the bottom heat sink710, and a first surface of a semiconductor die730is mounted or coupled to the bottom heat sink710using the solder720. The first surface of the die730of an embodiment is a bottom surface, but the embodiment is not so limited. The bottom surface may be either of an anode or cathode of the die730as appropriate to the configuration of the device700and/or the top surface of the die730.

FIG. 9is a perspective view of a top heat sink750of a device700, under an alternative embodiment. The top heat sink750couples or connects the die730to the lead of the lead frame structure (not shown). Consequently, solder740is mounted or applied to one or more regions or areas of a second surface of the die730, and the top heat sink750is mounted or coupled to the die730using the solder740. The second surface of the die730of an embodiment is a top surface, but the embodiment is not so limited. The top surface may be either of an anode or cathode of the die730as appropriate to the configuration of the device700and/or the bottom surface of the die730.

FIG. 10is a cross-sectional view of a device700that includes dual heat sinks710and750, under an alternative embodiment. As described above with reference toFIG. 7, the device700includes but is not limited to a bottom heat sink710(conductive mounting platform710), a first region or layer of conductive solder720, a semiconductor die730, a second region or layer of conductive solder740, and a top heat sink750(conductive clip750). Further, the device700is encapsulated in a compound760that can include epoxy compounds and the like. Each of the bottom heat sink710and top heat sink750comprise a conductive material or a combination of materials some of which are conductive as appropriate to the device. The bottom heat sink710of an embodiment is configured as a conductive mounting platform710, while the top heat sink750of an embodiment is configured as a conductive clip750.

FIG. 11Ais a top perspective view of a device700that includes dual heat sinks, under an alternative embodiment. The device is encapsulated in a compound760and includes, among other components, a top heat sink750, as described above with reference toFIG. 7andFIG. 10.

FIG. 11Bis a bottom perspective view of a device700that includes dual heat sinks, under an alternative embodiment. The device is encapsulated in a compound760and includes, among other components, a bottom heat sink710, as described above with reference toFIG. 7andFIG. 10.

FIG. 12is a schematic of a portion of a lead frame/conductive mounting platform (bottom heat sink), under an embodiment.FIG. 13is a schematic of a portion of a conductive clip (top heat sink), under an embodiment.FIG. 14is a schematic showing the semiconductor package or device line relative to each of the top heat sink and bottom heat sink, under an embodiment. These schematics include dimensions (e.g., millimeters) of an example embodiment, however these dimensions do not limit the embodiments described herein to these exact dimensions as alternative embodiments can use different dimensions as appropriate to a specific semiconductor package design.

The semiconductor devices and processes of embodiments described herein can be used with systems like those described in one or more of U.S. patent application Ser. No. 11/048,460, filed Jan. 31, 2005, and U.S. patent application Ser. No. 11/048,461, filed Jan. 31, 2005.

Aspects of the semiconductor devices and processes including multiple heat sinks described above can be used in any of a variety of electronic components. Unless the context clearly requires otherwise, throughout the description, the words “comprise,” “comprising,” and the like are to be construed in an inclusive sense as opposed to an exclusive or exhaustive sense; that is to say, in a sense of “including, but not limited to.” Words using the singular or plural number also include the plural or singular number respectively. Additionally, the words “herein,” “hereunder,” “above,” “below,” and words of similar import refer to this application as a whole and not to any particular portions of this application. When the word “or” is used in reference to a list of two or more items, that word covers all of the following interpretations of the word: any of the items in the list, all of the items in the list and any combination of the items in the list.

The above descriptions are not intended to be exhaustive or to limit the disclosed embodiments to the precise forms disclosed. While specific embodiments of, and examples for, the semiconductor device including multiple heat sinks and the corresponding assembly processes are described herein for illustrative purposes, various equivalent modifications are possible within the scope of the description, as those skilled in the relevant art will recognize. The teachings provided herein can be applied to other manufacturing systems, not only for the semiconductor devices and processes described above.

The elements and acts of the various embodiments described above can be combined to provide further embodiments. These and other changes can be made to the semiconductor devices and processes in light of the above detailed description.