LOW-VARIABILITY, HIGH-DENSITY DISC CELL WITH HORIZONTALLY ALIGNED ELECTRODES

A memory device includes a dielectric substrate and a first metal electrode contact layer coupled to the dielectric substrate. A metal heater element is disposed longitudinally on top of the first metal electrode contact. A first section of a layer of crystalline phase change material is positioned perpendicular to and in contact with an exposed first end of the longitudinally disposed metal heater element. A first section of a second metal electrode contact layer is positioned parallel to and spaced from, the first section of the layer of crystalline phase change material. A dielectric spacer is positioned between the layer of crystalline phase change material and the first section of the second metal electrode contact layer.

BACKGROUND

Technical Field

The present disclosure generally relates to semiconductor device fabrication, and more particularly, to a low-variability, high-density disc cell with horizontally aligned electrodes.

Description of the Related Art

Phase-change memory (PCM) is an emerging non-volatile memory technology that has recently been commercialized as storage-class memory in a computer system. PCM is also being explored for non-von Neumann computing such as in-memory computing and neuromorphic computing. Phase change memory utilizes the orders of magnitude large difference between the resistivity of the amorphous and the crystalline phase in phase change materials. The phase change material in a PCM cell is located between two electrodes. Electrical currents are applied to switch the material (or at least a fraction of it that blocks the current path) repeatedly between the two phases.

Current PCM devices are called mushroom cells that use a phase-change material disposed between an enlarged switching contact area electrode (top electrode) and a small area contact bottom electrode (heater) element. The heater may be a via-based electrode that makes a small area contact with the phase change material. The electrical current that flows through the via-based heater electrode concentrates the heat just above the heater in the phase change material. Using a point-sized area contact for the heater electrode, it is common for current to jump straight from the heater electrode to the larger electrode unless the phase-change layer between the two electrodes is sufficiently thick. Alternatively, a disc or pancake cell can be made by forming contact points from the larger electrode are formed on the edges of the PCM away from the heater electrode. These cells enable the use of thinner PCM layers that have beneficial PCM properties like higher retention and lower programming current.

The top electrode is at a remote position relatively far away from the heater. The phase change material in a conventional PCM mushroom cell or cross-point pillar memory device may be approximately 30-100 nanometers thick, and the top electrode is placed directly on top of the phase change material. If the phase change material were made thinner in the conventional structure, with the contact electrode positioned in its typical location, the heat formed in the phase change material would be directly pulled out through the top electrode, which would negatively affect the ability of the crystalline material to effectively change states. Some designs such as the disc or pancake cells contact the top electrode from the edges forcing current to go sideways rather than just straight up, so that the heat gets retained.

SUMMARY

According to an embodiment of the present disclosure, a memory device is disclosed. The memory device includes a dielectric substrate and a first metal electrode contact layer coupled to the dielectric substrate. A metal heater element is disposed longitudinally on top of the first metal electrode contact layer. A first section of a layer of crystalline phase change material is positioned perpendicular to and in contact with an exposed first end of the longitudinally disposed metal heater element. A first section of a second metal electrode contact layer is positioned parallel to and spaced from, the first section of the layer of crystalline phase change material. A dielectric spacer is positioned between the layer of crystalline phase change material and the first section of the second metal electrode contact layer.

According to another embodiment of the present disclosure, a memory device is disclosed. The memory device includes a dielectric substrate and a first metal electrode contact coupled to the dielectric substrate. A metal heater element extends linearly across and on top of a top surface of the first metal electrode contact. A second metal contact electrode is positioned above the metal heater element and above the first metal electrode contact. A layer of crystalline phase change material is positioned parallel to a side wall of the first metal electrode contact and perpendicular to a first end of the metal heater element. An electrode layer is coupled to the second metal contact electrode and positioned parallel to the layer of crystalline phase change material and perpendicular to the first end of the heater element.

According to another embodiment of the present disclosure, a method of manufacturing a memory device is provided. The method includes providing a substrate. A layer of insulation is formed on top of the substrate. A first electrode is formed in a pocket of the layer of insulation and on top of the substrate. A metal heater element is deposited linearly across a top surface of the layer of insulation and in contact with the first electrode. A second layer of insulation is formed on top of the metal and on top of the first layer of insulation. A layer of crystalline phase change material is deposited on at least a side wall of the first layer of insulation, a side wall of the second layer of insulation, and in contact with a first end of the metal heater element. A layer of spacer dielectric is conformally deposited over the layer of crystalline phase change material. A second electrode is formed over the layer of spacer dielectric. The second electrode is parallel to the layer of crystalline phase change material and perpendicular to the first end of the metal heater element.

DETAILED DESCRIPTION

Overview

In general, the subject technology provides a memory device that includes a phase change material (PCM) cell with a footprint that is smaller than the state of the art and with an improvement over the retention of current in the PCM layer. As may be appreciated, there exists some space between the heater element and the outer or top electrode contact of general PCM cell devices, which limits how small the PCM cell can be made. If the heater electrode contact is brought too close to the top electrode contact, the current may quickly conduct to the top electrode and the heat will have a more difficult time staying inside the phase change material. Generally, PCM cells position the electrode cooperating with the PCM layer on the top of the device. The thickness of the PCM layer and the span of the top electrode of conventional PCM cells create a relatively large footprint that limits the number of PCM cells that can be used in a circuit environment.

A device of the subject technology may reduce the footprint of the cell potentially is by turning the cell sideways. Where conventional PCM device use a small electrode for the heater electrode by printing a little via hole and filling the via metal, there exists a lot of variability in the uniformity (size and shape) of the via. When the via is small and then the footprint of the device is relatively large, the ability to scale the device or manufacture many devices in one package is limited.

According to an embodiment of the present disclosure, a memory device is disclosed. The memory device includes a dielectric substrate and a first metal electrode contact layer coupled to the dielectric substrate. A metal heater element is disposed longitudinally on top of the first metal electrode contact. A first section of a layer of crystalline phase change material is positioned perpendicular to and in contact with an exposed first end of the longitudinally disposed metal heater element. A first section of a second metal electrode contact layer is positioned parallel to and spaced from, the first section of the layer of crystalline phase change material. A dielectric spacer is positioned between the layer of crystalline phase change material and the first section of the second metal electrode contact layer.

As may be appreciated, the memory device structure uses a layer of a PCM that is perpendicular to a longitudinal heater element. Using longitudinal heater elements allows for a thinner profile (for example, 2 to 4 nanometers), so the overall cross-section is smaller. The cross-section of the heater element can be made much smaller than the state of the art, which reduces reset current. The longitudinal heater element is easier to pattern and thus provides improved uniformity over via patterning used by conventional heater elements. In addition, by forming the PCM layer and the second metal electrode contact layer perpendicular to the heater element (the PCM cell), which in some cases may be on a side of the device, the footprint of the PCM cell is reduced, resulting in a higher density of PCM devices that can be formed in a circuit environment. Also, the dielectric spacer between the PCM layer and the electrode prevents current from being drawn away from the PCM layer to the electrode too quickly.

According to an embodiment, which may be combined with any of the previous embodiments, the first section of the layer of crystalline phase change material is less than fifteen nanometers in thickness. A thinner layer of PCM also contributed to a smaller footprint of the PCM cell so that more PCM cells can be fit into the same area.

According to an embodiment, which may be combined with any of the previous embodiments, a second section of the layer of crystalline phase change material is positioned parallel to the metal heater element. A second section of the second metal electrode contact layer is positioned parallel to the metal heater element and on top of the second section of the layer of crystalline phase change material. By extending the PCM layer and the electrode over the top of the device, the area available for inducing an amorphous change in the PCM layer increases, which provides an opportunity for more programming.

According to an embodiment, which may be combined with one or more of the previous embodiments, a contact is positioned on top of the second section of the second metal electrode contact layer. The contact provides an element to access the PCM cell since in some embodiments, the PCM cell may be disposed on a side of the device which may not be available for direct contact.

According to an embodiment, which may be combined with one or more of the previous embodiments, a third section of the layer of crystalline phase change material is positioned perpendicular to and in contact with an exposed first end of the longitudinally disposed metal heater element. A third section of the second metal electrode contact layer is positioned parallel to and spaced from, the third section of the layer of crystalline phase change material. By wrapping the PCM layer around so that both ends of the heater element are contacted, the device now essentially has two PCM cells, which may provide for example, a contingency in case one of the PCM cells fails.

According to an embodiment, which may be combined with one or more of the previous embodiments, a contact is positioned on top of the second section of the second metal electrode contact layer. The contact provides an element to access the PCM cell since in some embodiments, the PCM cell(s) may be disposed on a side(s) of the device which may not be available for direct contact.

According to an embodiment, which may be combined with one or more of the previous embodiments, there is a first opening in the second section of the layer of crystalline phase change material and there is a second opening in the second section of the second metal electrode contact layer. The third section of the layer of crystalline phase change material is isolated from the first section of the layer of crystalline phase change material by the first opening in the second section of the layer of crystalline phase change material. The openings isolate the two sides of the device so that there are two PCM cells that can now be operated independently of each other.

According to an embodiment, which may be combined with one or more of the previous embodiments, a first contact is coupled to the first section of the second metal electrode contact layer. A second contact is coupled to the third section of the second metal electrode contact layer. The contacts provide independent access to the independently operating PCM cells.

According to another embodiment of the present disclosure, a memory device is disclosed. The memory device includes a dielectric substrate and a first metal electrode contact coupled to the dielectric substrate. A metal heater element extends linearly across and on top of a top surface of the first metal electrode contact. A second metal contact electrode is positioned above the metal heater element and above the first metal electrode contact. A layer of crystalline phase change material is positioned parallel to a side wall of the first metal electrode contact and perpendicular to a first end of the metal heater element. An electrode layer is coupled to the second metal contact electrode and positioned parallel to the layer of crystalline phase change material and perpendicular to the first end of the heater element.

As may be appreciated, the memory device structure uses a layer of PCM that is perpendicular to a longitudinal heater element. Using a linearly extending heater element allows for a thinner profile (for example, 2 to 4 nanometers), so the overall cross-section is smaller. The cross-section of the heater element can be made much smaller than the state of the art which reduces reset current. The linear heater element is easier to pattern and thus provides improved uniformity over via patterning used by conventional heater elements. In addition, by forming the PCM layer and the second metal electrode contact layer on side walls of the device and perpendicular to the heater element, the footprint of the PCM cell is reduced, resulting in a higher density of PCM devices that can be formed in a circuit environment.

According to an embodiment, which may be combined with one or more of the previous embodiments, the layer of crystalline phase change material is less than fifteen nanometers in thickness. A thinner PCM contributes to a smaller device footprint.

According to an embodiment, which may be combined with one or more of the previous embodiments, a section of insulation is positioned between the heater element and the second metal contact electrode. The layer of crystalline phase change material extends around the section of insulation, over a span of the heater element, and under the second metal contact electrode. By extending the PCM layer and the electrode over the top of the device, the area available for inducing an amorphous change in the PCM layer increases, which provides an opportunity for more programming.

According to an embodiment, which may be combined with one or more of the previous embodiments, the layer of crystalline phase change material extends down a side wall of the section of insulation in contact with a second end of the metal heater element. By wrapping the PCM layer around so that both ends of the heater element are contacted, the device now essentially has two PCM cells, which may provide, for example, a contingency in case one of the PCM cells fails.

According to an embodiment, which may be combined with one or more of the previous embodiments, the electrode layer is coupled to the second metal contact electrode and extends around three sides of the insulation. By wrapping the PCM layer around so that both ends of the heater element are contacted, the device now essentially has two PCM cells, which may provide for example, a contingency in case one of the PCM cells fails.

According to an embodiment, which may be combined with one or more of the previous embodiments, there is a split in the electrode layer coupled to the second metal contact electrode. The split isolates the two sides of the device so that there are two PCM cells that can now be operated independently of each other.

According to another embodiment of the present disclosure, a method of manufacturing a memory device is provided. The method includes providing a substrate. A layer of insulation is formed on top of the substrate. A first electrode is formed in a pocket of the layer of insulation and on top of the substrate. A metal heater element is deposited linearly across a top surface of the layer of insulation and in contact with the first electrode. A second layer of insulation is formed on top of the metal and on top of the first layer of insulation. A layer of crystalline phase change material is deposited on at least a side wall of the first layer of insulation, a side wall of the second layer of insulation, and in contact with a first end of the metal heater element. A layer of spacer dielectric is conformally deposited over the layer of crystalline phase change material. A second electrode is formed over the layer of spacer dielectric. The second electrode is parallel to the layer of crystalline phase change material and perpendicular to the first end of the metal heater element.

Forming a memory device with a PCM cell as disclosed provides a device with a smaller footprint. In addition, the dielectric spacer provides insulation so that current is retained by the PCM layer which prevents heat from being drawn out from the PCM layer to the electrode prematurely.

According to an embodiment, which may be combined with one or more of the previous embodiments, the layer of crystalline phase change material is less than fifteen nanometers in thickness. A thinner PCM contributes to a smaller device footprint.

According to an embodiment, which may be combined with one or more of the previous embodiments, the metal heater element is 2-10 nanometers in thickness. The smaller metal heater profile provides a smaller cross-section which reduces reset current in the device.

According to an embodiment, which may be combined with one or more of the previous embodiments, the layer of crystalline phase change material is deposited on a first side wall of the first layer of insulation, a top surface of the first layer of insulation, and a second side wall of the first layer of insulation, and in contact with a second end of metal heater element. By extending the PCM layer and the electrode over the top of the device, the area available for inducing an amorphous change in the PCM layer increases, which provides an opportunity for more programming. In addition, making contact with both ends of the heater element provides two PCM cells in the same device.

According to an embodiment, which may be combined with one or more of the previous embodiments, a metal contact is formed over the top surface of the first layer of insulation, in contact with the second electrode. The contact provides an element to access the PCM cell since in some embodiments, the PCM cell(s) may be disposed on a side(s) of the device which may not be available for direct contact.

According to an embodiment, which may be combined with one or more of the previous embodiments, the second electrode is formed over the first side wall of the first layer of insulation, the top surface of the first layer of insulation, the second side wall of the first layer of insulation, and in contact with the layer of crystalline phase change material. An opening is formed through the second electrode and through the layer of crystalline phase change material, isolating one section of the layer of crystalline phase change material from another section of the layer of crystalline phase change material. The opening in the electrode isolates the two parts of the device so that there are two PCM cells that can now be operated independently of each other.

In one aspect, spatially related terminology such as “front,” “back,” “top,” “bottom,” “beneath,” “below,” “lower,” above,” “upper,” “side,” “left,” “right,” and the like, is used with reference to the direction of the Figures being described. Since components of embodiments of the disclosure can be positioned in a number of different directions, the directional terminology is used for purposes of illustration and is in no way limiting. Thus, it will be understood that the spatially relative terminology is intended to encompass different directions of the device in use or operation in addition to the direction depicted in the figures. For example, if the device in the figures is turned over, elements described as “below” or “beneath” other elements or features would then be oriented “above” the other elements or features. Thus, for example, the term “below” can encompass both an orientation that is above, as well as, below. Similarly, an element described as “on top of” of another element may mean either that the element is positioned above and is not necessarily in direct contact with the underlying element. The device may be otherwise oriented (rotated 90 degrees or viewed or referenced at other directions) and the spatially relative descriptors used herein should be interpreted accordingly.

As used herein, the terms “lateral”, “planar”, and “horizontal” describe an orientation parallel to a first surface of a chip or substrate. In the disclosure herein, the “first surface” may be the top layer of a semiconductor device where individual circuit devices are patterned in the semiconductor material.

As used herein, the terms “coupled” and/or “electrically coupled” are not meant to mean that the elements must be directly coupled together-intervening elements may be provided between the “coupled” or “electrically coupled” elements. In contrast, if an element is referred to as being “directly connected” or “directly coupled” to another element, there are no intervening elements present. The term “electrically connected” refers to a low-ohmic electric connection between the elements electrically connected together. The phrase “electrically connected” does not necessarily mean that the elements must be directly in physical contact together-intervening elements may be provided between the “connected” or “electrically connected” elements.

Although the terms first, second, etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of example embodiments. Nor does describing an element as “first” or “second”, etc. necessarily mean that there is an order or priority to any of the elements. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items.

Example embodiments are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized or simplified embodiments (and intermediate structures). As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, may be expected. Thus, the regions illustrated in the figures are schematic in nature and their shapes do not necessarily illustrate the actual shape of a region of a device and do not limit the scope. It should be appreciated that the figures and/or drawings accompanying this disclosure are exemplary, non-limiting, and not necessarily drawn to scale.

It is to be understood that other embodiments may be used, and structural or logical changes may be made without departing from the spirit and scope defined by the claims. The description of the embodiments is not limiting. In particular, elements of the embodiments described hereinafter may be combined with elements of different embodiments.

Definitions

Phase Change Material (PCM): A material that by default is typically in a conductive crystalline state, and after exposure to a pulse of current on the order of nanoseconds to melt and quench the PCM, a portion of the PCM changes to a resistive amorphous state.

Heater Element: A metal element that conducts a current that is applied to a PCM.

Electrode: A metallic element that conducts positioned to transfer or receive a current.

A Top or Outer Electrode: An electrode positioned in cooperation with a PCM. The top electrode is typically on the opposite side of a PCM from a heater element.

Example Device Structure

Referring now to FIG. 1, the subject disclosure provides a memory device 100 that is for example, a PCM cell. The memory device 100 generally includes a linearly disposed heater element 150 that spans transversely across the top surface of a first layer of insulation 120A and a first electrode 130. The heater element 150 may be for example, 80-200 nanometers long (20 nm from the edge of a 40 nm electrode contacting the heater element on either side up to 80 nm from the edge of the electrode to the heater element each way), and may have a profile that is approximately 2 to 6 nanometers thick. The heater element 150 is positioned perpendicular to a section of a PCM layer 160. The PCM layer 160 makes contact with a first end of the heater element 150.

The memory device 100 may have the PCM layer 160 on at least a side wall of the first and second insulation layers 120A and 120B, referred to as the “first section 162 of the PCM layer 160”. Some embodiments may extend the PCM layer 160 to over the top of the second insulation layer 120B, which may be a “second (or top) section 164 of the PCM layer 160”. Some embodiments further extend the PCM layer 160 over the other side walls of the second insulation layer 120B into contact with a second end of the heater element 150 (which can be seen for example in FIG. 13). This section of the PCM layer 160 may be referred to as the “third section 166”. Some embodiments may extend the PCM layer 160 further over legs 104 of the dielectric substrate 102 that are not covered by the first insulation layer 120A or the first electrode 130.

The memory device 100 also includes a second electrode 135 positioned parallel to the first section 162 of the PCM layer 160 that is on the side walls of the insulation layers 120A and 120B. In some embodiments, the second electrode 135 may extend from the dielectric substrate 102, up to a level above the second section 164 of the PCM layer 160, and may span across the length of the PCM layer 160.

The memory device 100 may also include a dielectric spacer 170 that is situated between the first section 162 of the PCM layer 160 and the second electrode 135. In some embodiments, the second electrode 135 is a layer that extends over one end of the dielectric spacer 170. In some embodiments, the PCM layer 160 that is present on the legs 104 may cover the other end of the dielectric spacer 170.

Some embodiments of the memory device 100 includes one or more contacts 140 that are coupled to the second electrode 135. The contacts 140 provide access to the PCM layer 160, which may not be available in some circuits since some of the memory device elements are primarily positioned on the side and interior of the memory device 100. A dielectric 110 may cover exposed conductive parts of the memory device 100.

FIG. 2 shows a view of the heater assembly 105 in isolation. The heater assembly may include the heater element 150 which may span in a line longitudinally between the insulation layers 120A and 120B. FIG. 1 is a cross-section along the line A-A′. As can be seen in both the illustrations of FIG. 1 and FIG. 2, the PCM layer 160 has a relatively thin profile, which may be in the range of 2 to 15 nanometers thick. The cross-section of the contact area between the heater element 150 and the PCM layer 160 is relatively small at their intersection. When a high voltage pulse is applied to the heater element 150, the current generates heat to the PCM layer 160. Depending on the material used for the PCM layer 160, a section of the PCM layer 160 transforms into an amorphous material 165. As can be further seen by the illustration of FIG. 1, since the length of the PCM layer 160 may be extended all around the top and sides of the insulation layers 120A and 120B, the amount of amorphous material 165 available to program may be increased.

Example Methodology of Manufacture

In the following, a process describes a general method of forming memory devices with one or more PCM cells that may be positioned on a side of the device. The fabrication of the devices described herein below can comprise multi-step sequences of, for example, photolithographic and/or chemical processing steps that facilitate gradual creation of electronic-based systems, devices, components, and/or circuits in a semiconducting and/or a superconducting device (e.g., an integrated circuit). For instance, memory device 100 can be fabricated on one or more substrates (e.g., a silicon (Si) substrates, and/or another substrate) by employing techniques including, but not limited to: photolithography, microlithography, nanolithography, nanoimprint lithography, photomasking techniques, patterning techniques, photoresist techniques (e.g., positive-tone photoresist, negative-tone photoresist, hybrid-tone photoresist, and/or another photoresist technique), etching techniques (e.g., reactive ion etching (RIE), dry etching, wet etching, ion beam etching, plasma etching, laser ablation, and/or another etching technique), evaporation techniques, sputtering techniques, plasma ashing techniques, thermal treatments (e.g., rapid thermal anneal, furnace anneals, thermal oxidation, and/or another thermal treatment), chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), molecular beam epitaxy (MBE), electrochemical deposition (ECD), chemical-mechanical planarization (CMP), backgrinding techniques, and/or another technique for fabricating an integrated circuit.

In one embodiment, the base dielectric substrate 102 may be a bulk semiconductor substrate formed of, for example, silicon, or other types of semiconductor substrate materials that are commonly used in bulk semiconductor fabrication such as, for example, monocrystalline Si, silicon germanium (SiGe), III-V compound semiconductor, II-VI compound semiconductor, or semiconductor-on-insulator (SOI). Group III-V compound semiconductors, for example, include materials having at least one group III element and at least one group V element, such as one or more of aluminum gallium arsenide (AlGaAs), aluminum gallium nitride (AlGaN), aluminum arsenide (AlAs), aluminum indium arsenide (AlIAs), aluminum nitride (AlN), gallium antimonide (GaSb), gallium aluminum antimonide (GaAlSb), gallium arsenide (GaAs), gallium arsenide antimonide (GaAsSb), gallium nitride (GaN), indium antimonide (InSb), indium arsenide (InAs), indium gallium arsenide (InGaAs), indium gallium arsenide phosphide (InGaAsP), indium gallium nitride (InGaN), indium nitride (InN), indium phosphide (InP) and alloy combinations including at least one of the foregoing materials. The alloy combinations can include binary (two elements, e.g., gallium (III) arsenide (GaAs)), ternary (three elements, e.g., InGaAs) and quaternary (four elements, e.g., aluminum gallium indium phosphide (AlInGaP)) alloys.

Referring now to FIG. 3, an initial semiconductor device formation is shown. The initial formation may include a base substrate 310. A layer of insulation 320 may be formed over the substrate 310. A pocket may be formed in the insulation layer 320, into which a metal 330 is deposited (forming the first electrode 130).

FIG. 4 shows a process of depositing a thin layer of metal 350 over the top of the layer of insulation 320 and the first electrode 130. The metal 350 may be deposited linearly across the span of the layer of insulation 320. The formation of the layer of metal 350 is the heater element 150 in the final device formation. Another layer of insulation 320 may be deposited over the layer of metal 350.

FIG. 5 shows a process of etching away some of the insulation layer 320 over the substrate 310 on one side of the formation. The area left vacated by etching will be used to form the PCM cell. The remaining insulation will be the first and second insulation layers 120A and 120B in the final device formation.

FIG. 6 shows a process of conformally depositing a layer of PCM 360 across the exposed areas of the substrate 310, up the sides of the insulation layers 120A and 120B (and in contact with an exposed end of the heater element 150), and across the top of the insulation layer 120B. Some embodiments may include conformally depositing a layer of spacer dielectric 370 over the top of the exposed areas of the layer of PCM 360.

FIG. 7 shows a process after the layer of spacer dielectric 370 has been etched back from the top of the device and from above the layer of PCM 360 in the open area on the right side of the device. A layer of metal 335 may be deposited over the layer of PCM 360 and the layer of dielectric spacer 370. The layer of dielectric spacer 370 may now be enclosed by the layer of metal 335 and the layer of PCM 360, which forms the dielectric spacer 170 in the final device formation. The remaining open areas may be filled with a dielectric 110 and planarized.

FIG. 8 shows a process of etching back the insulation layers 120A and 120B, the heater element 150, the layer of metal 335, and the layer of PCM 360, from the left side of the formation to a desired PCM cell size. The layer of metal 335, once encased by dielectric forms the second electrode 135. FIG. 9 shows a process after formation of a metal contact 140 is deposited in contact with the second electrode 135 on the top side of the final device formation.

In the following process embodiment, the method of manufacturing provides a memory device that may have two instances of PCM cells in the same package. FIGS. 10 and 11 show initial formations for another process of manufacturing a memory device. FIGS. 10 and 11 show the same formations previously shown in FIGS. 3 and 4, so their description is not repeated for sake of brevity. FIG. 12 shows a process of similar to the process of FIG. 5 except that the etch back of the insulation layers 320 is performed on both sides of the formation.

In FIG. 13, the insulation layers 320 are encased and will now be referred to by their final device formation labels; insulation layers 120a and 120B. The process in FIG. 13 conformally deposits a layer of PCM 360 on both sides of the insulation layers 120A and 120 and over the top of insulation layer 120B. Some of the exposed areas of the supporting substrate 310 may be covered by the layer of PCM 360. A layer of spacer dielectric 370 may be conformally deposited over the layer of PCM 360.

FIG. 14 shows a process after the layer of spacer dielectric 370 may be etched back everywhere except from the side walls of the insulation layers 120A and 120B and more accurately, from the sections of the layer of PCM 360 that will be the first section 162 and the third section 166. The remaining spacer dielectric material will be the dielectric spacers 170 in the final device formation. A layer of metal 335 may be deposited over the top of the layer of PCM 360 and the dielectric spacers 170. Dielectric 110 may fill in any open areas remaining on the formation. In FIG. 15, a metal contact 140 may be formed in contact with a top section of the metal layer 335, which becomes the second electrode 135. As can be seen in the final device formation of FIG. 15, the process provides two sections from which the heater element 150 may induce an amorphous reaction from the layer of PCM 160 on the sides of the device.

In the following process embodiment, the method of manufacturing provides a memory device that may have two instances of PCM cells that operate independently of one another in the same package. The formations shown in FIGS. 16-20 show the same formations shown in the previous embodiment in FIGS. 10-14, so their description is not repeated to avoid prolixity. FIG. 21 shows a process of forming an opening through the layer of metal 335 and through the layer of PCM 360 through the top of the formation down to the insulation layer 120B. By forming an opening through the layer of metal 335 and the layer of PCM 360, the device how has two PCM cells that are isolated from each other. As shown in FIG. 22, two different contacts 140 may be deposited in connection with respective second electrodes 135 on each side of the device. Each second electrode 135 cooperates with a set of the dielectric spacer 170 and a section of the PCM layer 160 that is also on the same side of the device. As can be appreciated, the process provide additional programming ability within the same package.

CONCLUSION