Data converter and related analog-to-digital converter, digital-to-analog converter and chip

The present application discloses a data converter (112). The data converter includes an input terminus (98), a digital-to-analog (D/A) converter (116) and a mapping unit (114). The input terminus is configured to receive an input signal. The D/A converter includes a plurality of D/A converter units configured to generate an output signal. The mapping unit is coupled between the input terminus and the D/A converter and is configured to cause the plurality of D/A conversion units to be equivalently arranged in a relative order in which the plurality of D/A conversion units are gated according to specific electrical characteristics of the plurality of D/A conversion units for digital-to-analog conversion. The present application further provides an A/D converter, a D/A converter and a related chip.

TECHNICAL FIELD

The present application relates to a converter; particularly to a data converter and a related analog-to-digital (A/D) converter, a digital-to-analog (D/A) converter and a chip.

BACKGROUND

In multi-bit delta-sigma (Δ-Σ) analog-to-digital (A/D) converters and digital-to-analog (D/A) converters, in order to solve the problem of device mismatch errors, a data weighted averaging technique is proposed, so as to carry out 1st-order noise shaping on the device mismatch errors; thereby greatly improving the signal-to-noise (S/N) ratio. However, when the amplitude of the input signal is relatively small (for example, the amplitude is about −50 dBFS), the data weighted averaging technique will cause repetition in the selection pattern of the digital-to-analog converter unit, and the repetition will be folded back into the frequency band to generate a spurious tone, which will still worsen the S/N ratio.

At present, one commonly used solution is to add an additional digital-to-analog converter unit to the digital-to-analog converter; this technology is called an incremental data weighted average technology. When the amplitude of the input signal is relatively small, using the incremental data weighted average technology can make the selection pattern of the digital-to-analog converter unit less prone to repeatability, thereby eliminating the spurious tone. However, when the amplitude of the input signal is around 1 LSB, the selection pattern of the digital-to-analog converter unit still shows repetition, which in turn produces the spurious tone.

In view of the foregoing, there is a need for further improvements and innovations to address the above-mentioned issues.

BRIEF SUMMARY OF THE INVENTION

One purpose of the present application is directed to a data converter; in particular, to a data converter, A/D converter, D/A converter and a related chip, so as to address the above-mentioned issues.

One embodiment of the present application discloses a data converter. The data converter includes an input terminus, a digital-to-analog (D/A) converter and a mapping unit. The input terminus is configured to receive an input signal. The D/A converter includes a plurality of D/A conversion units configured to generate an output signal. The mapping unit is coupled between the input terminus and the D/A converter and is configured to cause the plurality of D/A conversion units, according to a specific electrical characteristic of the plurality of D/A conversion units, to be equivalently arranged in a relative order in which the plurality of D/A conversion units are selected for digital-to-analog conversion.

One embodiment of the present application discloses an analog-to-digital (A/D) converter, which configured to convert an analog signal into a digital signal. The A/D converter includes an input terminus, a low-pass filter, a quantizer and a feedback loop. The input terminus is configured to receive the analog signal. The low-pass filter is coupled to the input terminus and generates a low-pass signal according to the analog signal. The quantizer is configured to generate a quantized signal according to the low-pass signal. The feedback loop is configured to feed the quantized signal back to an output terminus of the low-pass filter. The feedback loop includes the data converter.

One embodiment of the present application discloses a D/A converter, configured to convert a digital signal into an analog signal. The D/A converter includes an input terminus, an upsampling filter, a quantizer and the data converter. The input terminus is configured to receive the digital signal. The upsampling filter is coupled to the input terminus and generates an upsampled signal according to the digital signal. The quantizer is configured to generate a quantized signal according to the upsampled signal. The data converter is configured to generate the analog signal according to the quantized signal.

One embodiment of the present application discloses a chip. The chip includes the above data converter.

One embodiment of the present application discloses a chip. The chip includes the above A/D converter.

One embodiment of the present application discloses a chip. The chip includes the above D/A converter.

The data converter, A/D converter, D/A converter and related chip disclosed in the present application can effectively inhibit the spurious tone when the selection pattern of D/A conversion units shows repetition, so as to improve the S/N ratio.

DETAILED DESCRIPTION

The following disclosure provides many different embodiments, or examples, for implementing different features of the application. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and the second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and the second features, such that the first and the second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for the ease of the description to describe one element or feature's relationship with respect to another element(s) or feature(s) as illustrated in the drawings. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (e.g., rotated by 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

FIG. 1is a schematic block diagram illustrating a multi-bit Δ-Σ (sigma-delta) A/D converter10according to embodiments of the present application. Referring toFIG. 1, the multi-bit Δ-ΣA/D converter10is configured to convert an analog signal into a digital signal. The multi-bit Δ-ΣA/D converter10includes an input terminus98, a low-pass filter (LPT)100, a loop filter102, a quantizer104, a decimation filter106, an incremental data weighted averaging (IDWA) circuit110, a data converter112and a logic unit118, wherein the incremental data weighted averaging circuit110and the data converter112are disposed on the feedback loop108. The incremental data weighted averaging circuit110us coupled between the quantizer104and the data converter112.

The input terminus98is configured to receive the analog signal, the low-pass filter100is coupled to the input terminus98and generates a low-pass signal LPF_A according to the analog signal. The loop filter102is configured to generate a loop filter signal LF_A according to the low-pass signal LPF_A and the output Sout of the feedback loop108, the quantizer104is coupled to the loop filter102and is configured to generate a quantized signal Q_D according to the loop filter signal LF_A. The decimation filter106is configured to provide a multi-bit digital signal based on the quantized signal Q_D. The feedback loop108is configured to feed the quantized signal Q_D back to an output terminus of the low-pass filter100. Specifically, the incremental data weighted averaging circuit110is configured to provide the input signal Sin required by the data converter112based on the quantized signal Q_D. The data converter112is configured to generate an output signal Sout to the logic unit118based on the input signal Sin. The logic unit118is configured to subtract the output signal Sout from the low-pass signal LPF_A and then provide the subtraction result to the loop filter102. It should be noted that the present application is not limited to the incremental data weighted averaging circuit110; in some embodiments, the incremental data weighted averaging circuit110may be implemented using other circuits with similar functions; for example, it is feasible to use the data weighted averaging circuit to replace the incremental data weighted averaging circuit110.

FIG. 2is a schematic block diagram illustrating the data converter112according to one embodiment of the present application. Referring toFIG. 2, the data converter112includes an input terminus120configured to receive the input signal Sin of the multi-bit, an output terminus122configured to output the output signal Sout, a mapping unit114and a D/A converter116.

The D/A converter116includes D/A conversion units20_1,20_2, . . .20_N, wherein N is a positive integer. The converter116is configured to generate the output signal Sout. The D/A converter116can be any circuit unit capable of converting the digital signal into the analog signal, such as, current, charge or voltage. For example, the D/A converter116may include a current source, capacitor, resistor, or any other electronic component fitting the above-mentioned definition.

The mapping unit114is coupled between the input terminus120and the D/A converter116and is configured to cause D/A conversion units20_1,20_2, . . .20_N, according to specific electrical characteristics of the D/A conversion units20_1,20_2, . . .20_N, to be equivalently arranged in a relative order in which the plurality of D/A conversion units20_1,20_2, . . .20_N are selected for digital-to-analog conversion. Specifically, the equivalent arrangement does not mean to arrange the D/A conversion units20_1,20_2, . . .20_N in a circuit layout according to specific electrical characteristics of the D/A conversion units20_1,20_2, . . .20_N; rather, the mapping unit114is used to configure the connection relationship between D/A conversion units20_1,20_2, . . .20_N and the incremental data weighted averaging circuit110.

For example, whenever the data converter112is shipped out of the factory or everytime powered on, the specific electrical characteristics of the D/A conversion units20_1,20_2, . . .20_N are measured respectively to generate a plurality of measurement results, and the mapping unit114is programmed according to the plurality of measurement results; however, the present application is not limited thereto. It is feasible to effectively inhibit the spurious tone of the multi-bit Δ-ΣA/D converter10using the mapping unit114, thereby obtaining a better S/N ratio.

In some embodiments, the specific electrical characteristics are related to a current characteristic. For example, when the D/A conversion units20_1,20_2, . . .20_N include a current source, the specific electrical characteristics include the current provided by the current source. The measurement of the current characteristics can be implemented using any existing technology.

In some embodiments, the specific electrical characteristics are related to a voltage characteristic. For example, when the D/A conversion units20_1,20_2, . . .20_N include a capacitor, the specific electrical characteristics include the charges related to the voltage stored in the capacitor. The measurement of the voltage characteristics can be implemented using any existing technology.

To facilitate the discussion, in the following description of the present disclosure, the value of N is set as 33; i.e., the D/A converter116includes thirty-three D/A conversion units20_1,20_2, . . .20_33.

FIG. 3is a histogram showing the amplitude of the specific electrical characteristics of a plurality of D/A conversion units20_1,20_2, . . .20_33according to one embodiment of the present application. Referring toFIG. 3, the horizontal axis represents the original order of the D/A conversion units20_1,20_2, . . .20_33before being equivalently arranged, from position A1to A33; as could be appreciated, not all D/A conversion units are shown in the drawings for the sake of brevity. At the starting stage, the input signal Sin1that the data converter112receives in the beginning would cause some of the D/A conversion units starting from the position A1to be selected, for example, some of the D/A conversion units positioned at A1to A10would be selected, depending on the size of the first input signal Sin1. Then, the second input signal Sin2that the data converter112receives would cause some of the D/A conversion units starting from the position A11to be selected, such as, for example, some of the D/A conversion units positioned at A11to A30would be selected, depending on the size of the second input signal Sin2. Next, the third input signal Sin3that the data converter112receives would cause some of the D/A conversion units starting from the position A31to be selected, if the number exceeds the position A33, then it returns to the position A1for subsequent gating of the D/A conversion units; the third input signal Sin3would cause some of the D/A conversion units from the positions A31to A33and then from positions A1to A6to be selected, and the subsequent operations go on like this.

The vertical axis inFIG. 3represents the normalized amplitude of the specific electrical characteristics of the D/A conversion units20_1,20_2, . . .20_33, wherein the normalization reference value is 1. Due to the changes during the manufacturing process, device mismatch errors may occur among each D/A conversion unit20_1,20_2, . . .20_33, and accordingly, the level of the specific electrical characteristics may differ slightly. In other words, there is an electrical characteristic difference between the specific electrical characteristic of each D/A conversion unit20_1,20_2, . . .20_33and the reference value 1.

Reference is made back toFIG. 1. When the multi-bit Δ-ΣA/D converter10does not include the mapping unit114, the D/A conversion units20_1,20_2, . . .20_33are directly under the control of the incremental data weighted averaging circuit110. Reference is made back toFIG. 3again, which shows that the D/A conversion units20_1,20_2, . . .20_33includes several D/A conversion units positioned at A1to A17and several D/A conversion units positioned at A18to A33. In one scenario, the sum of the specific electrical characteristics of several D/A conversion units positioned at A1to A17is relatively larger, whereas the sum of the specific electrical characteristics of several D/A conversion units positioned at A18-A33is relatively smaller. Under the above premise, once the selection pattern of the D/A conversion units20_1,20_2, . . .20_33becomes repetitive seeFIG. 4for detailed description), the spurious tone will be particularly significant, thereby worsening the S/N ratio.

FIG. 4is a schematic diagram illustrating the gating status of the D/A conversion units20_1,20_2, . . .20_33, according to embodiments of the present application. Referring toFIG. 4, the code (1) in vertical column represents the quantized signal Q_D that the quantizer104generates at the beginning according to a first low-pass signal LPF_A; then, code (2) represents the quantized signal Q_D that the quantizer104generates according to a second low-pass signal LPF_A, and so on. The value after the equal sign of the code (1) represents the value of the quantized signal Q_D. For example, code (1)=16 means that the quantized signal Q_D is 16; that is, 16 D/A conversion units are selected according to the first low-pass signal LPF_A. At the starting stage, several D/A conversion units starting from the position A1are selected. In the present embodiment, several D/A conversion units positioned at A1to A16are selected. Because of the function of the incremental data weighted averaging circuit110, when code (2)=17, several D/A conversion units starting from the A17after the position A16nare selected, until the D/A conversion unit at the position A33is selected. When code (3)=17, the gating returns to the position A1, and several D/A conversion units positioned at A1to A17are selected. Similarly, when code (4)=16, several D/A conversion units positioned at A18to A33are selected. When code (5)=16, the gating returns to the position A1, and several D/A conversion units positioned at A1to A16are selected. When code (6)=17, several D/A conversion units positioned at A17to A33are selected.

As shown inFIG. 4, when the digital signal input sequence is code (5) and code (6), the D/A conversion units that are selected are the same as those are selected when the digital signal input sequence is code (1) and code (2). Therefore, the selection pattern is repetitive. In such cases (the sum of the specific electrical characteristics of several D/A conversion units positioned at A1to A16is relatively larger, whereas the sum of the specific electrical characteristics of several D/A conversion units positioned at A17to A33is relatively smaller), spurious tone will become particularly significant, thereby worsening the S/N ratio.

The D/A conversion units20_1,20_2, . . .20_33can be arranged equivalently according to the electrical characteristic difference corresponding to each of the D/A conversion units20_1,20_2, . . .20_33using the mapping unit114. Therefore, it is feasible to effectively inhibit the spurious tone of the multi-bit Δ-ΣA/D converter10, thereby obtaining a better S/N ratio.

FIG. 5is a histogram showing each amplitude shown inFIG. 3before being equivalently arranged and after being sorted according to one embodiment of the present application. Referring toFIG. 5, in which the horizontal axis represents the positions of the D/A conversion units20_1,20_2, . . .20_33before being equivalently arranged and after sorting, from position I1to I33; it should be noted that not all positions are shown inFIG. 5for the sake of brevity. After the sorting, the D/A conversion unit at the position A16inFIG. 3locates at the first position, I1; similarly, the D/A conversion unit at the position A30inFIG. 3locates at the last position, I33. The mapping unit114sorts the specific electrical characteristics from in an ascending order. In this way, the mapping unit114can easily determine the level of the specific electrical characteristics of D/A conversion units20_1,20_2, . . .20_33, so that the subsequent equivalent arrangement of D/A conversion units20_1,20_2, . . .20_33can be carried out in a relatively convenient way. It should be noted that this operation is optional. In some embodiments, this operation can be omitted.

FIG. 6Ais a schematic diagram illustrating a method for arranging an even number of D/A conversion units, according to the first embodiment of the present application. Referring toFIG. 6A, the D/A conversion unit with the minimum specific electrical characteristic and locating at the position I1is equivalently arranged at the first position in a relative order, and the D/A conversion unit with the maximum specific electrical characteristic and locating at the position I33is equivalently arranged at the second position in the relative order; next, the D/A conversion unit with the second lowest specific electrical characteristic is equivalently arranged at the third position in the relative order, and the D/A conversion unit with the second largest specific electrical characteristic is equivalently arranged at the fourth position in the relative order, and so on. Put it simply, after the equivalent arrangement, the amplitude of the specific electrical characteristic of the D/A conversion unit that is selected as the (2K−1)thone in the relative order ranks the Kthplace among the amplitudes of the specific electrical characteristics of the plurality of D/A conversion units20_1,20_2, . . .20_33, and the amplitude of the specific electrical characteristic of the D/A conversion unit that is selected as the 2Kthone in the relative order ranks the (N−K+1)thplace among the amplitudes of the specific electrical characteristics of the plurality of D/A conversion units20_1,20_2, . . .20_33, wherein N is the number of the plurality of D/A conversion units20_1,20_2, . . .20_33(in the present embodiment, N is 33), and wherein K≥1 and K≤N. For example, in one embodiment, the equivalent arrangement is carried out according to the amplitude of the voltage related to the D/A conversion units; that is, the D/A conversion units with the maximum and minimum amplitude of the voltage related to the D/A conversion units are put in the first and the second position, and then, the D/A conversion units with the second largest and smallest amplitude of the voltage are put at the third and fourth position, and so on, and the D/A conversion units with the voltage amplitudes ranking at the kthand (N−k+1)thare put at the (2k−1)thand 2kthposition.

FIG. 6Bis a schematic diagram illustrating a method for arranging an odd number of D/A conversion units, according to the first embodiment of the present application. Referring toFIG. 6B, the logic for equivalently arranging an odd number of D/A conversion units is the same as the logic for equivalently arranging an even number of D/A conversion units, and hence, a detailed description is omitted herein for the sake of brevity.

FIG. 6Cis a histogram showing each amplitude shown inFIG. 5after being equivalently arranged using the method set forth inFIG. 6B. Referring toFIG. 6C, wherein the horizontal axis represents the positions of the D/A conversion units20_1,20_2, . . .20_33after being equivalently arranged, from position C1to C33, it should be noted that not all positions are shown inFIG. 6Cfor the sake of brevity. At the starting stage, the first input signal Sin1that the data converter112receives in the beginning causes several D/A conversion units starting from the position C1to be selected, such as, several D/A conversion units positioned at C1to C10, according to the level of the first input signal Sin1. Then, the second input signal Sin2that the data converter112receives cause several D/A conversion units starting from the position C11to be selected, such as, several D/A conversion units positioned at C11to C30, according to the level of the second input signal Sin2. Next, third input signal Sin3that the data converter112receives causes the several D/A conversion units starting from the position C31to be selected, if the number exceeds the position C33, then it returns to the position C1for subsequent gating of the D/A conversion units, and the subsequent operations go on like this.

As shown inFIG. 6C, after equivalently arranging the D/A conversion units20_1,20_2, . . .20_33, the D/A conversion unit locating at the position A16before the equivalent arrangement now locates at the position C1; and the D/A conversion unit locating at the position A30before the equivalent arrangement now locates at the position C2.

Moreover, for D/A conversion units20_1,20_2, . . .20_33after being equivalently arranged, the amplitudes of the specific electrical characteristics of several D/A conversion units arranged in odd positions (such as, positions C1, C3, C5) are in an ascending order. Moreover, for D/A conversion units20_1,20_2, . . .20_33after being equivalently arranged, the amplitudes of the specific electrical characteristics of several D/A conversion units arranged in odd positions (such as, position C2, C4, C6) are in a descending order. However, the present application is not limited thereto. In other embodiments, for D/A conversion units20_1,20_2, . . .20_33after being equivalently arranged, the amplitudes of the specific electrical characteristics of several D/A conversion units arranged in odd positions are in a descending order, and for D/A conversion units20_1,20_2, . . .20_33after being equivalently arranged, the amplitudes of the specific electrical characteristics of several D/A conversion units arranged in odd positions are in an ascending order.

Returning back toFIG. 3, before being equivalently arranged, the several D/A conversion units of the first half of the D/A conversion units20_1,20_2, . . .20_33locate at positions A1to A17. The sum of the electrical characteristic differences corresponding to each of the several D/A conversion units at positions A1to A17is a first sum. Before being equivalently arranged, the several D/A conversion units of the second half of the D/A conversion units20_1,20_2, . . .20_33locate at positions A18to A33. The sum of the electrical characteristic differences corresponding to each of the several D/A conversion units at positions A18to A33is a second sum.

Returning back toFIG. 6C, after being equivalently arranged, the several D/A conversion units of the first half of the D/A conversion units20_1,20_2, . . .20_33locate at positions C1to C17. The sum of the electrical characteristic differences corresponding to each of the several D/A conversion units at positions C1to C17is a third sum. After being equivalently arranged, the several D/A conversion units of the second half of the D/A conversion units20_1,20_2, . . .20_33locate at positions C18to C33. The sum of the electrical characteristic differences corresponding to each of the several D/A conversion units at positions C18to C33is a fourth sum. The difference between the third sum and the fourth sum is smaller than the difference between the first sum and the second sum. In other words, for equivalently arranged D/A conversion units20_1,20_2, . . .20_33, the difference between the electrical characteristic difference of several D/A conversion units at the first half and the electrical characteristic difference of several D/A conversion units at the second half is relatively small. In this way, even the selection pattern exhibits the repetitive shown inFIG. 4, it is feasible to inhibit the spurious tone of the multi-bit Δ-ΣA/D converter10, thereby obtaining a better S/N ratio.

Moreover, other embodiments of the present application further include the arrangement patterns derived fromFIG. 6C. For example, the position C1shifts backward by one position, and accordingly, the position C2shifts backward by one position, and so on. The position C33then shifts to the position of the current position C1. Such arrangement also falls within the scope of the second embodiment of the present application. Moreover, in the above-mentioned example, the number of the shift is just an example. In the present application, the number by which the position is shifted can be any number.

FIG. 7is a spectrogram of the digital signal outputted by the multi-bit Δ-ΣA/D converter10according to one embodiment of the present application. Referring toFIG. 7, the horizontal axis is frequency (Hz); and the vertical axis is the amplitude (dB). The spectrogram shown inFIG. 7evidences that the spurious tone of the multi-bit Δ-ΣA/D converter10can be inhibited effectively.

FIG. 8Ais a schematic diagram illustrating a method for arranging an even number of D/A conversion units, according to the second embodiment of the present application. Referring toFIG. 8A, the D/A conversion unit with the minimum specific electrical characteristic and locating at the position I1is equivalently arranged at the first position in a relative order, and the D/A conversion unit with the maximum specific electrical characteristic and locating at the position I33is equivalently arranged at the second position in the relative order; next, the D/A conversion unit with the second lowest specific electrical characteristic is equivalently arranged at the second last position in the relative order, and the D/A conversion unit with the second largest specific electrical characteristic is equivalently arranged at the last position in the relative order, and so on.

FIG. 8Bis a schematic diagram illustrating a method for arranging an odd number of D/A conversion units, according to the second embodiment of the present application. Referring toFIG. 8B, the logic for equivalently arranging an odd number of D/A conversion units is the same as the logic for equivalently arranging an even number of D/A conversion units, and hence, a detailed description is omitted herein for the sake of brevity.

FIG. 8Cis a histogram showing each amplitude shown inFIG. 5after being equivalently arranged using the method set forth inFIG. 8B. Referring toFIG. 8C, wherein the horizontal axis represents the positions of the D/A conversion units20_1,20_2, . . .20_33after being equivalently arranged, from position D1to D33, it should be noted that not all positions are shown inFIG. 8Cfor the sake of brevity. At the starting stage, the first input signal Sin1that the data converter112receives in the beginning causes several D/A conversion units starting from the position C1to be selected, such as, several D/A conversion units positioned at D1to D10, according to the level of the first input signal Sin1. Then, the second input signal Sin2that the data converter112receives cause several D/A conversion units starting from the position D11to be selected, such as, several D/A conversion units positioned at D11to D30, according to the level of the second input signal Sin2. Next, third input signal Sin3that the data converter112receives causes the several D/A conversion units starting from the position D31to be selected, if the number exceeds the position D33, then it returns to the position D1for subsequent gating of the D/A conversion units, and the subsequent operations go on like this.

As shown inFIG. 8C, after equivalently arranging the D/A conversion units20_1,20_2, . . .20_33, the D/A conversion unit locating at the position A16before the equivalent arrangement now locates at the position D1; and the D/A conversion unit locating at the position A30before the equivalent arrangement now locates at the position D2.

Moreover, for D/A conversion units20_1,20_2, . . .20_33after being equivalently arranged, the amplitudes of the specific electrical characteristics of a portion of the several D/A conversion units arranged in odd positions (such as, positions D1, D3, D5) are in an ascending order, whereas the amplitudes of the specific electrical characteristics of the remaining portion of the several D/A conversion units arranged in odd positions are in a descending order.

Also, for D/A conversion units20_1,20_2, . . .20_33after being equivalently arranged, the amplitudes of the specific electrical characteristics of a portion of several D/A conversion units arranged in odd positions (such as, position D2, D4, D6) are in a descending order, whereas the amplitudes of the specific electrical characteristics of the remaining portion of the several D/A conversion units arranged in even positions are in an ascending order. However, the present application is not limited thereto.

After being equivalently arranged, the several D/A conversion units of the first half of the D/A conversion units20_1,20_2, . . .20_33locate at positions D1to D17. The sum of the electrical characteristic differences corresponding to each of the several D/A conversion units at positions D1to D17is a fifth sum. After being equivalently arranged, the several D/A conversion units of the second half of the D/A conversion units20_1,20_2, . . .20_33locate at positions D18to D33. The sum of the electrical characteristic differences corresponding to each of the several D/A conversion units at positions D18to D33is a sixth sum. The difference between the fifth sum and the sixth sum is smaller than the difference between the first sum and the second sum. In some specific embodiments, the difference between the fifth sum and the sixth sum is smaller than the difference between the third sum and the fourth sum.

Even the selection pattern exhibits the repetitive shown inFIG. 4, the spurious tone of the multi-bit Δ-ΣA/D converter10can still be inhibited by using the mapping unit114, thereby obtaining a better S/N ratio.

Moreover, other embodiments of the present application further include the arrangement patterns derived fromFIG. 8C. For example, the position D1shifts backward by one position, and accordingly, the position D2shifts backward by one position, and so on. The position D33then shifts to the position of the current position D1. Such arrangement also falls within the scope of the second embodiment of the present application. Moreover, in the above-mentioned example, the number of the shift is just an example. In the present application, the number by which the position is shifted can be any number.

FIG. 9shows the wave forms of S/N ratios of multi-bit Δ-ΣA/D converters that includes or does not includes the data converter10according to one embodiment of the present application. Referring toFIG. 9, the horizontal axis is the amplitude (dB); and the vertical axis is the S/N ratio (dB).FIG. 9shows curves Cf_1, Cf_2, Cf_3and Cf_4. Curve Cf_1represents the S/N ratio under an ideal situation. Curve Cf_2represents the S/N ratio of a multi-bit Δ-ΣA/D converter that does not include the data converter10according to the present application. Curve Cf_3represents the S/N ratio of the mapping unit114obtained using the arrangement pattern according to the first embodiment of the present application. Curve Cf_4represents the S/N ratio of the mapping unit114obtained using the arrangement pattern according to the second embodiment of the present application. As could be seen inFIG. 9, the multi-bit Δ-ΣA/D converter10may exhibit a better S/N ratio by using the mapping unit114.

In some embodiments, a chip including data converter11210is provided; for example, the chip can be a semiconductor chip implemented by different manufacturing process.

In some embodiments, a chip including the multi-bit Δ-ΣA/D converter10is provided; for example, the chip can be a semiconductor chip implemented by different manufacturing process.

FIG. 10is a schematic block diagram illustrating the multi-bit Δ-ΣD/A converter30according to embodiments of the present application. Referring toFIG. 10, the multi-bit Δ-ΣD/A converter30is similar to the multi-bit Δ-ΣA/D converter10shown inFIG. 1, except that the multi-bit Δ-ΣD/A converter30includes an upsampling filter300and a feedback loop302. The feedback loop302is configured to feed the output terminus of the quantizer104back to the output terminus of the upsampling filter300.

The input terminus98is configured to receive the digital signal, the upsampling filter300is coupled to the input terminus98and generates an upsampled signal U_D according to the digital signal. The loop filter102is configured to generate a loop filter signal LF_A according to the upsampled signal U_D and a quantized signal Q_D of the feedback loop302; the quantizer104is coupled to the loop filter102and is configured to generate the quantized signal Q_D according to the loop filter signal LF_A. The incremental data weighted averaging circuit110is configured to provide the input signal Sin that the data converter112needs based on the quantized signal Q_D. The data converter112is configured to generate an output signal Sout as the analog signal based on the input signal Sin.

It is feasible to effectively inhibit the spurious tone of the multi-bit Δ-ΣD/A converter30by using the mapping unit114, thereby obtaining a better S/N ratio.

In some embodiments, a chip includes the multi-bit Δ-ΣD/A converter30; for example, the chip can be semiconductor chips implemented by different manufacturing processes.