Interconnect structures for semiconductor devices

A cap layer for a copper interconnect structure formed in a first dielectric layer is provided. In an embodiment, the cap layer may be formed by an in-situ deposition process in which a process gas comprising germanium, arsenic, tungsten, or gallium is introduced, thereby forming a copper-metal cap layer. In another embodiment, a copper-metal silicide cap is provided. In this embodiment, silane is introduced before, during, or after a process gas is introduced, the process gas comprising germanium, arsenic, tungsten, or gallium. Thereafter, an optional etch stop layer may be formed, and a second dielectric layer may be formed over the etch stop layer or the first dielectric layer.

TECHNICAL FIELD

The present invention relates generally to semiconductors and, more particularly, to a cap layer over a conductive layer in a semiconductor device.

BACKGROUND

Generally, integrated circuits (ICs) comprise electronic components, such as transistors, capacitors, or the like, formed on a substrate. One or more metal layers are then formed over the electronic components to provide connections between the electronic components and to provide connections to external devices. The metal layers typically comprise an inter-layer dielectric (ILD) layer in which interconnect structures, such as vias and conductive traces, are formed, usually with a single- or dual-damascene process.

The trend in the semiconductor industry is towards the miniaturization or scaling of integrated circuits, in order to provide smaller ICs and improve performance, such as increased speed and decreased power consumption. While aluminum and aluminum alloys were most frequently used in the past for the material of conductive lines in integrated circuits, the current trend is to use copper for a conductive material because copper has better electrical characteristics than aluminum, such as decreased resistance, higher conductivity, and a higher melting point.

The change in the conductive line material and insulating materials of semiconductor devices has introduced new challenges in the manufacturing process. For example, copper oxidizes easily and has a tendency to diffuse into adjacent insulating materials, particularly when a low-K material or other porous insulator is used for the ILD layer. To reduce these effects, attempts have been made to form a cap layer comprising a single layer of CoWP and CoB over the copper material. While the CoWP and CoB cap layers help reduce the oxidation and diffusion of the copper into the surrounding ILD layer, the CoWP and CoB cap layers require numerous processing steps and often result in metal residue on the surface of the ILD layer. These cap layers also exhibit poor resistance to oxygen and other chemicals, which may result in Rc yield loss and high contact resistance.

Accordingly, there is a need for a cap layer that eliminates or reduces surface migration and diffusion of the conductive material into adjacent insulating materials while being easily and efficiently formed.

SUMMARY OF THE INVENTION

These and other problems are generally solved or circumvented, and technical advantages are generally achieved, by preferred embodiments of the present invention which provides a cap layer over a conductive material in a semiconductor device.

In accordance with an embodiment of the present invention, a method for forming a cap layer is provided. The method comprises forming a first dielectric layer on a substrate, and an interconnect structure in the first dielectric layer. A cap layer is formed over the interconnect structure such that the cap layer comprises germanium, arsenic, tungsten, or gallium. The cap layer may be formed of a silicide by introducing silane before, during, or after introduction of a process gas comprising germanium, arsenic, tungsten, or gallium.

In accordance with another embodiment of the present invention, a cap layer comprising a copper alloy is formed over a copper interconnect, the copper alloy comprises germanium, arsenic, tungsten, or gallium. The cap layer may be formed of a silicide by introducing silane before, during, or after introduction of a process gas comprising germanium, arsenic, tungsten, or gallium.

In accordance with yet another embodiment of the present invention, a method of providing a copper-metal cap layer is provided. The copper-metal cap layer may be formed by forming a copper interconnect structure in a first dielectric layer and introducing a process gas comprising GeH4, AsH3, GaH3, or WF6with a diluent gas comprising He, H2, or N2. The cap layer may be formed of a silicide by introducing silane before, during, or after introduction of a process gas comprising germanium, arsenic, tungsten, or gallium.

It should be appreciated by those skilled in the art that the conception and specific embodiment disclosed may be readily utilized as a basis for modifying or designing other structures or processes for carrying out the same purposes of the present invention. It should also be realized by those skilled in the art that such equivalent constructions do not depart from the spirit and scope of the invention as set forth in the appended claims.

DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS

The present invention will be described with respect to embodiments in a specific context, namely forming copper interconnects in an intermetal dielectric layer. The invention may also be applied, however, to other designs in which it is desirable to limit contamination between materials or to increase adhesive qualities of successive layers.

FIGS. 1-5illustrate cross-section views of a first embodiment of the present invention in which a cap layer is formed on a metal layer. Referring first toFIG. 1, a workpiece100is provided. The workpiece100comprises a semiconductor substrate110having a first dielectric layer112formed thereon. The semiconductor substrate110may comprise silicon or other semiconductor materials. The semiconductor substrate110may also include other active components or circuits (not shown). The workpiece100may include other conductive layers or other semiconductor elements, e.g. transistors, diodes, etc.

Generally, the first dielectric layer112may be formed, for example, of a low-K dielectric material, such as silicon oxide, phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), fluorinated silicate glass (FSG), SiOxCy, Spin-On-Glass, Spin-On-Polymers, silicon carbon material, compounds thereof, composites thereof, combinations thereof or the like, by any suitable method known in the art. In an embodiment, the first dielectric layer112comprises an oxide that may be formed by chemical vapor deposition (CVD) techniques using tetra-ethyl-ortho-silicate (TEOS) and oxygen as a precursor. Other materials and processes may be used. It should also be noted that the first dielectric layer112may comprise a plurality of dielectric layers, with or without an etch stop layer formed between adjacent dielectric layers. The first dielectric layer112is preferably about 500 Å to about 5000 Å in thickness, but more preferably 2000 Å.

An opening116is formed in the first dielectric layer112. The opening116may be a trench, via, or other pattern into which a conductive layer is to be formed. For example, in an embodiment, the opening116comprises a long thin trench that is relatively straight, or that curves and digresses in bends or other patterns to form conductive lines within a metal layer. In other embodiments, the opening116forms a via, contact plug, or other interconnect structure electrically coupled to electrical devices or other conductive lines formed on underlying layers.

The opening116may be formed by photolithography techniques known in the art. Generally, photolithography techniques involve applying a photoresist material (not shown) and exposing the photoresist material in accordance with a desired pattern. The photoresist material is then developed to remove a portion of the photoresist material, thereby exposing the underlying material in accordance with the desired pattern. The remaining photoresist material protects the underlying material from subsequent processing steps, such as etching, performed to form the opening116in the first dielectric layer112. The etching process may be a wet or dry, anisotropic or isotropic, etch process, but preferably is an anisotropic dry etch process. After the opening116is formed in the first dielectric layer112, the remaining photoresist, if any, may be removed. Other processes, such as electron beam lithography (EBL) or the like, may be utilized to form the opening116.

It should be noted that the process discussed above described a single-damascene process for illustrative purposes only. Other processes, such as a dual-damascene process may be utilized in accordance with an embodiment of the present invention. For example, a dual-amascene process may be utilized to form a trench and a via through one or more layers of the first dielectric layer112.

After the opening116is formed, an optional first barrier layer120is formed in the opening116. The first barrier layer120may be formed of one or more adhesion layers and/or barrier layers. In an embodiment, the first barrier layer120is formed of one or more layers of conductive materials, such as titanium, titanium nitride, tantalum, tantalum nitride, or the like. In an exemplary embodiment, the first barrier layer120is formed of a thin layer of tantalum nitride and a thin layer of tantalum deposited by CVD techniques. In this embodiment, the combined thickness of the tantalum nitride and tantalum layers is about 50 Å to about 500 Å.

A conductive layer122is formed in the opening on the optional first barrier layer120. The opening116may be filled with the conductive material by, for example, performing a blanket deposition process to a thickness such that the opening116is at least substantially filled. The conductive layer122may comprise metals, elemental metals, transition metals, or the like. In an exemplary embodiment, the conductive layer122is copper. The conductive layer122may also be formed by depositing a seed layer and performing an electro-chemical plating process.

A planarization process, such as a chemical-mechanical process (CMP), may be performed to planarize the surface and to remove excess deposits of the material used to form the first barrier layer120and the conductive layer122as illustrated inFIG. 1.

Furthermore, a preclean process may be performed to remove impurities along the surface of the conductive layer122. The pre-clean process may be a reactive or a non-reactive pre-clean process. For example, a reactive process may include a plasma process using a hydrogen-containing plasma, and a non-reactive process may include a plasma process using an argon-containing or helium-containing plasma. The pre-clean process may also be a plasma process using a combination of the above gases.

In an embodiment in which the conductive layer122comprises copper, the pre-clean process may be performed using an H2plasma, such as N2NH3, NH3, or the like, under a pressure of about 1 mTorr to about 10 Torr and a temperature of about 250° C. to about 400° C. Other processes and materials may be used.

FIG. 2illustrates the workpiece100after a cap layer210has been formed in accordance with an embodiment of the present invention. In an embodiment, the cap layer210comprises a copper-metal alloy. One of ordinary skill in the art will realize that the process described herein may be performed by in-situ deposition and does not necessarily require additional tools or equipment. Because of this, the cap layer210may be formed quickly and efficiently, thereby reducing costs.

For example, a cap layer210comprising a copper germanium alloy may be formed by introducing a process gas of GeH4with a diluent gas, such as He, H2, N2, or the like, at a ratio between about 1:100 to about 1:10, a pressure of about 1 mTorr to about 10 Torr, and a temperature of about 250° C. to about 400° C. As another example, a cap layer210comprising a copper arsenic alloy may be formed by introducing a process gas such as AsH3, ASCl3, or the like with a diluent gas, such as He, H2, N2, or the like, at a ratio between about 1:100 to about 1:10, a pressure of about 1 mTorr to about 10 Torr, and a temperature of about 250° C. to about 400° C. In yet another example, a cap layer210comprising a copper tungsten alloy may be formed by introducing a process gas such as WF6, W(Co)6or the like with a diluent gas, such as He, H2, N2, or the like, at a ratio between about 1:100 to about 1:10, a pressure of about 1 mTorr to about 10 Torr, and a temperature of about 250° C. to about 400° C. In yet another example, a cap layer210comprising a copper gallium alloy may be formed by introducing a process gas such as GaH3or the like with a diluent gas, such as He, H2, N2, or the like, at a ratio between about 1:100 to about 1:10, a pressure of about 1 mTorr to about 10 Torr, and a temperature of about 250° C. to about 400° C.

In another embodiment, the cap layer210comprises a copper-metal silicide material. In this embodiment, silane (SiH4) may be introduced before, during, or after the introduction of the process gas. The introduction of silane causes the selective formation of a silicon seed layer on the exposed copper of the interconnect structure and causes the formation of a copper-metal silicide cap layer. Generally, the seed layer (such as seed layer211illustrated inFIG. 2) comprises a thin atomic layer of a material to aid in the formation a thicker layer.

In an embodiment, the seed layer comprises a silicon seed layer formed by introducing SiH4or a silane-based gas (e.g., SiH6) for a time period of about 4 seconds to about 10 seconds at a temperature of about 250° C. to about 400° C. prior to the introduction of a metal precursor. A dissociation process occurs that results in a thin atomic silicon seed layer being selectively deposited on the conductive layer122. Thereafter, the metal precursor gas is introduced to form the copper-metal silicide cap layer210. For example, a cap layer210comprising a copper germanium silicide may be formed by introducing a process gas of GeH4, with a diluent gas, such as He, H2, N2, or the like, at a ratio of process gas mixture to diluent gas of between about 1:100 to about 1:10, a pressure of about 1 mTorr to about 10 Torr and a temperature of about 250° C. to about 400° C.

As another example, a cap layer210comprising a copper arsenic silicide may be formed by introducing a process gas of AsH3with a diluent gas, such as He, H2, N2, or the like, at a ratio of process gas mixture to diluent gas of between about 1:100 to about 1:10, a pressure of about 1 mTorr to about 10 Torr and a temperature of about 250° C. to about 400° C. In yet another example, a cap layer210comprising a copper tungsten silicide may be formed by introducing a process gas of WH6with a diluent gas, such as He, H2, N2, or the like, at a ratio of process gas mixture to diluent gas of about 1:100 to about 1:10, a pressure of about 1 mTorr to about 10 Torr and a temperature of about 250° C. to about 400° C. In yet another example, a cap layer210comprising a copper gallium silicide may be formed by introducing a process gas of GaH3with a diluent gas, such as He, H2, N2, or the like, at a ratio of process gas mixture to diluent gas of about 1:100 to about 1:10, a pressure of about 1 mTorr to about 10 Torr and a temperature of about 250° C. to about 400° C.

In yet another embodiment, a copper-metal silicide cap layer may be formed by simultaneously introducing a mixture of silane and a metal precursor. For example, a cap layer210comprising a copper germanium silicide may be formed by introducing a process gas mixture of GeH4and SiH4at a ratio GeH4to SiH4of between about 1:1 to about 1:100, with a diluent gas, such as He, H2, N2, or the like, at a ratio of process gas mixture to diluent gas of between about 1:100 to about 1:10, a pressure of about 1 mTorr to about 10 Torr and a temperature of about 250° C. to about 400° C. In this manner, the silicon of the SiH4selectively reacts with the cap layer210to form a metal silicide.

As another example, a cap layer210comprising a copper arsenic silicide may be formed by introducing a process gas mixture of AsH3and SiH4at a ratio of AsH3to SiH4of between about 1:1 to about 1:100 with a diluent gas, such as He, H2, N2, or the like, at a ratio of process gas mixture to diluent gas of between about 1:100 to about 1:10, a pressure of about 1 mTorr to about 10 Torr and a temperature of about 250° C. to about 400° C. In yet another example, a cap layer210comprising a copper tungsten silicide may be formed by introducing a process gas mixture of WF6and SiH4at a ratio of WH6to SiH4of between about 1:1 to about 1:10, with a diluent gas, such as He, H2, N2, or the like, at a ratio of process gas mixture to diluent gas of about 1:100 to about 1:10, a pressure of about 1 mTorr to about 10 Torr and a temperature of about 250° C. to about 400° C. In yet another example, a cap layer210comprising a copper gallium silicide may be formed by introducing a process gas mixture of GaH3and SiH4at a ratio of GaH3to SiH4of between about 1:1 to about 1:100, with a diluent gas, such as He, H2, N2, or the like, at a ratio of process gas mixture to diluent gas of about 1:100 to about 1:10, a pressure of about 1 mTorr to about 10 Torr and a temperature of about 250° C. to about 400° C.

In yet another embodiment, a cap layer210comprising a copper-metal silicide may be formed by introducing silane gas after the introduction of a metal precursor. For example, a cap layer210comprising a copper germanium silicide may be formed by introducing a process gas of GeH4, with a diluent gas, such as He, H2, N2, or the like, at a ratio of process gas mixture to diluent gas of between about 1:100 to about 1:10, a pressure of about 1 mTorr to about 10 Torr and a temperature of about 250° C. to about 400° C., and then introducing silane for a time period of about 4 seconds to about 10 seconds at a pressure of about 1 mTorr to about 10 Torr and a temperature of about 250° C. to about 400° C.

As another example, a cap layer210comprising a copper arsenic silicide may be formed by introducing a process gas of AsH3with a diluent gas, such as He, H2, N2, or the like, at a ratio of process gas mixture to diluent gas of between about 1:100 to about 1:10, a pressure of about 1 mTorr to about 10 Torr and a temperature of about 250° C. to about 400° C., and then introducing silane for a time period of about 4 seconds to about 10 seconds at a pressure of about 1 mTorr to about 10 Torr and a temperature of about 250° C. to about 400° C. In yet another example, a cap layer210comprising a copper tungsten silicide may be formed by introducing a process gas of WF6with a diluent gas, such as He, H2, N2, or the like, at a ratio of process gas mixture to diluent gas of about 1:100 to about 1:10, a pressure of about1mTorr to about 10 Torr and a temperature of about 250° C. to about 400° C., and then introducing silane for a time period of about 4 seconds to about 10 seconds at a pressure of about 1 mTorr to about 10 Torr and a temperature of about 250° C. to about 400° C. In yet another example, a cap layer210comprising a copper gallium silicide may be formed by introducing a process gas of GaH3with a diluent gas, such as He, H2, N2, or the like, at a ratio of process gas mixture to diluent gas of about 1:100 to about 1:10, a pressure of about 1 mTorr to about 10 Torr and a temperature of about 250° C. to about 400° C., and then introducing silane for a time period of about 4 seconds to about 10 seconds at a pressure of about 1 mTorr to about 10 Torr and a temperature of about 250° C. to about 400° C.

FIG. 3illustrates the workpiece100after an optional etch stop layer310has been formed thereon in accordance with an embodiment of the present invention. In an embodiment, a pre-treatment process is performed prior to the formation of the etch stop layer310. The pre-treatment process may be a plasma process using H2, N2NH3, a mixture of H2/N2H3, or the like at a flow rate of about 100 sccm to about 30000 sccm at a pressure of about 1 mTorr to about 100 mTorr and at power of about 200 Watts to about 1000 Watts and at a temperature of about 275° C. to about 400° C., for example.

Thereafter, the etch stop layer310may be formed on the surface of the first dielectric layer112. The etch stop layer310is preferably formed of a dielectric material having a different etch selectivity from adjacent layers. In an embodiment, the etch stop layer310may be formed of SiCN, SiCO, CN, BCN, combinations thereof, or the like deposited by CVD or PECVD to a thickness of about 0 Å to about 800 Å, but more preferably about 100 Å. The etch stop layer310protects the underlying structures, such as the first dielectric layer112, and also provides improved adhesion for subsequently formed layers.

FIG. 4illustrates the workpiece100after a second dielectric layer410has been formed in accordance with an embodiment of the present invention. The second dielectric layer410may be formed, for example, of a low-K dielectric material, such as silicon oxide, phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), fluorinated silicate glass (FSG), SiOxCy, Spin-On-Glass, Spin-On-Polymers, silicon carbon material, compounds thereof, composites thereof, combinations thereof or the like, by any suitable method known in the art. In an embodiment, second dielectric layer410comprises a material similar to the first dielectric layer112, such as an oxide that may be formed by chemical vapor deposition (CVD) techniques using tetra-ethyl-ortho-silicate (TEOS) and oxygen as a precursor. Other materials and processes may be used. It should also be noted that the second dielectric layer410may comprise a plurality of dielectric layers, with or without an etch stop layer formed between adjacent dielectric layers. The second dielectric layer410is preferably about 1000 Å to about 6000 Å in thickness, but more preferably 3000 Å.

FIG. 5illustrates the workpiece100without the optional etch stop layer310(seeFIG. 3) in accordance with an embodiment of the present invention. In this embodiment, the first dielectric layer112and the second dielectric layer410may comprise the same type of material or different materials.

It should be noted that the embodiments illustrated inFIGS. 1-5illustrate the cap layer210having a top surface that is coplanar with a top surface of the first dielectric layer112for illustrative purposes only. The conductive layer122may take any shape, and be formed using a single or dual damascene process.

For example,FIGS. 6-8illustrate other shapes for the conductive layer122and the cap layer210. In particular,FIG. 6illustrates the conductive layer122having a recess,FIG. 7illustrates the cap layer210protruding above a surface of the first dielectric layer112, andFIG. 8illustrates the conductive layer122protruding above a surface of the first dielectric layer112. Other configurations may be used.

One of ordinary skill in the art will realize that embodiments of the present invention may be utilized to form interconnections exhibiting lower line-to-line (L-L) leakage with materials coherent to current back-end-of-line (BEOL) processing materials. Furthermore, the metal/metal silicide cap layers disclosed herein exhibit improved integrity with less voids between the cap and the etch stop layer, and at a lower cost. The electromigration (EM) and time-dependent dielectric breakdown (TDDB) characteristics may also be improved.

Although the present invention and its advantages have been described in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the invention as defined by the appended claims. For example, different types of materials and processes may be varied while remaining within the scope of the present invention.