Cavity wall structure for semiconductor packaging

An improved method for forming a semiconductor package is disclosed herein. The method includes forming a multi-layer package substrate having a first major surface and a second major surface opposite to the first major surface. The package substrate comprises a recess region. A semiconductor die is attached to the die region within the recess region. A dam structure is formed within the recess region. The dam structure surrounds the semiconductor die and extends upward to a height below the first major surface of the package substrate. A liquid encapsulant material is dispensed into the recess region. The liquid encapsulant material is surrounded by the dam structure. The liquid encapsulant extends upwardly to a height below the height of the dam structure. A package lid is attached to the package substrate.

FIELD OF THE INVENTION

The present invention generally relates to a semiconductor package. More specifically, the present invention is directed to an improved semiconductor packaging structure that increases package reliability, lowers production cost and results in higher yield.

BACKGROUND

Ceramic semiconductor packages are typically fabricated with a cavity defined by sidewalls of a ceramic substrate. A semiconductor die is housed within the cavity and is electrically connected to the interconnect structures of the ceramic semiconductor package. A lid structure is positioned over the semiconductor chip and attached to an upper surface of the ceramic substrate to enclose the semiconductor chip within the cavity.

Conventional methods of forming such ceramic substrate packages may result in poor adhesion of the lid structure to the surface of the ceramic substrate, which reduces reliability and yield of the ceramic semiconductor package.

From the foregoing discussion, it is desirable to provide a ceramic semiconductor package with improved reliability and a cost-efficient method of forming such a semiconductor package.

SUMMARY

Embodiments generally relate to a semiconductor package having a cavity within which a semiconductor die is enclosed. In one embodiment, a method for forming the semiconductor package is disclosed. The method includes forming a multi-layer package substrate having a first major surface and a second major surface opposite to the first major surface. The package substrate comprises a recess region extending downwardly from the first major surface of the package substrate. The recess region is defined with a die region and a non-die region surrounding the die region. A semiconductor die is disposed in the die region within the recess region. Wire bonds are formed to electrically connect the semiconductor die to input/output (I/O) terminals disposed adjacent the second major surface of the package substrate. A dam structure is formed within the recess region. The dam structure surrounds the semiconductor die and extends upward to a height below the first major surface of the package substrate. A liquid encapsulant material is dispensed into the recess region. The liquid encapsulant material is surrounded by the dam structure. The liquid encapsulant extends upwardly to a height below the height of the dam structure. A package lid is attached to the package substrate.

In another embodiment, a method for forming the semiconductor package includes forming a package substrate having a first major surface and a second major surface opposite to the first major surface. The package substrate comprises a recess region extending downwardly from the first major surface of the package substrate. The recess region is defined with a die region and a non-die region surrounding the die region. A semiconductor die is disposed in the die region within the recess region. A dam structure is formed within the recess region. The dam structure surrounds the semiconductor die and extends upward to a height below the first major surface of the package substrate. A liquid encapsulant material is dispensed into the recess region. The liquid encapsulant material is surrounded by the dam structure. The liquid encapsulant extends upwardly to a height below the height of the dam structure. A package lid is attached to the package substrate to enclose the recess region.

In yet another embodiment, a semiconductor package is disclosed. The semiconductor package includes a package substrate having a first major surface and a second major surface opposite to the first major surface. The package substrate comprises a recess region defined with a die region and a non-die region surrounding the die region. A semiconductor die is mounted to the die region within the recess region. Wire bonds are disposed within the recess region to electrically connect the semiconductor die to input/output terminals disposed adjacent the second major surface of the package substrate. A dam structure is disposed within the recess region. The dam structure surrounds the semiconductor die and extends upwardly to a height below the first major surface of the package substrate. An encapsulant is disposed within the recess region. The encapsulant is surrounded by the dam structure. The encapsulant extends upwardly to a height below the height of the dam structure. A package lid is attached to the package substrate to enclose the recess region.

DETAILED DESCRIPTION

Embodiments generally relate to semiconductor packages and methods for forming semiconductor packages. The semiconductor package is used to package one or more semiconductor dies or chips having an integrated circuit (IC). For the case of more than one semiconductor die, the semiconductor dies may be arranged in a planar arrangement, vertical arrangement, or a combination thereof. The semiconductor dies, for example, may include memory devices, logic devices such as mixed signal logic devices, communication devices, radio frequency (RF) devices, optoelectronic devices, digital signal processors (DSPs), microcontrollers, system-on-chips (SOCs), micro-electromechanical (MEM) chips, as well as other types of devices or a combination thereof. Such packages may be incorporated into electronic products or equipment, such as phones, computers as well as mobile and mobile smart products. Incorporating the packages into other types of products may also be useful.

FIGS. 1a-1cshow various views of an embodiment of a semiconductor package100in accordance with the present invention. In particular,FIG. 1ashows a top view of a semiconductor package100having a package lid170,FIG. 1bshows a simplified plan view of the semiconductor package100ofFIG. 1awith the package lid removed, andFIG. 1cshows a cross-sectional view of the semiconductor package100ofFIG. 1ataken along the A-A plane.

The semiconductor package100includes a package substrate120. In one embodiment, the package substrate120may include a plurality of dielectric substrate layers that may be laminated or built-up. For example, the package substrate120includes a bottom substrate layer122, a first intermediate substrate layer124disposed on the bottom substrate layer122, a second intermediate substrate layer126disposed on the first intermediate substrate layer124, and a top substrate layer128disposed on the second intermediate substrate layer128. Other configurations of a multi-layer package substrate120may also be useful. In one embodiment, the package substrate120is a laminate-based multi-layer ceramic substrate. For example, the package substrate120includes first and second intermediate ceramic substrate layers124and126sandwiched between top and bottom ceramic substrate layers128and122. Other types of dielectric substrate layer may also be used to form the package substrate120. Each of the package substrate layers includes a first major surface (e.g.,122a,124a,126a,128a) and a second major surface (e.g.,122b,124b,126b,128b) opposite to the first major surface. The first major surface of the substrate layers may be referred to as the top planar surface and the second major surface of the substrate layers may be referred to as the bottom planar surface. Other designations for the first and second major surfaces may also be useful.

Although four package substrate layers are shown inFIG. 1c, it is understood that the package substrate120may be configured to include other number of substrate layers, depending on design requirements.

The package substrate120includes a plurality of interconnect structures that electrically connect the semiconductor die130to input/output (I/O) terminals160of the package substrate120located on the bottom planar surface122bof the bottom substrate layer122. The I/O terminals160are, for example, configured as terminal pads corresponding to metal lands. The I/O terminals160of the semiconductor package100may be arranged to provide a ball grid array (BGA) or land grid array (LGA) semiconductor package. Other shapes or arrangements of I/O terminals160may also be employed, depending on design requirements. For example, the I/O terminals160may also be configured to include metal balls (e.g., solder balls) or spherical-shaped bumps formed on the metal lands.

The interconnect structures may include a plurality of bond pads150, conductive traces154and via contacts152and156. In one embodiment, bond pads150and conductive traces154are formed on the top surfaces of the substrate layers. For example, bond pads150are disposed on the exposed top planar surface124aof the first intermediate substrate layer124while the conductive traces154are disposed on the top planar surface122aof the bottom substrate layer122. The bond pads150on the first intermediate substrate layer124may define a first line level; the conductive traces154on the top planar surface122aof the bottom substrate layer122may define a second line level; and the terminal pads160on the bottom planar surface122bof the bottom substrate layer122may define a third line level.

In one embodiment, a plurality of via contacts (e.g.,152and156) are disposed in the package substrate120to form an electrical interconnection between the different line levels120. For example, via contacts152in the first intermediate substrate layer124extend from the top planar surface124ato the bottom planar surface124bto electrically connect bond pads150in the first line level to conductive traces154in the second line level; and via contacts156in the bottom substrate layer122extend from the top planar surface122ato the bottom planar surface122bto electrically connect conductive traces154in the second line level to terminal pads160. Via contacts152in the first intermediate substrate layer124may define a first via level and via contacts156in the bottom substrate layer122may define a second via level.

Although the bond pads150are illustrated as extending to a side wall of the recess region (e.g., the inner sidewall of the second intermediate substrate layer126), it is understood that the bond pads150may be configured to be spaced away from the sidewall of the recess region. Although only bond pads150are illustrated in the first line level, it is understood that the first line level may also be configured to include one or more conductive traces. For example, conductive traces may be disposed in the first line level to electrically connect the bond pads150to via contacts152in the first via level. Other configurations of interconnect structures may also be useful, depending on design requirements. The interconnect structures can also include any number of bond pads150, conductive traces154, via contacts152and156, and I/O terminals160as required. Generally, conductive traces are configured with reduced thickness and pitch relative to bond pads to facilitate routing of electrical signals between interconnect structures.

A recess region is disposed in the package substrate120. The recess region exposes a portion of the top planar surface122aof the bottom substrate layer122and a portion of the top planar surfaces124aand126aof the first and second intermediate substrate layers124and126. In one embodiment, the recess region includes a first bottom surface defined by the exposed portion of the top planar surface122aof the bottom substrate layer122, and a second bottom surface defined by the exposed portion of the top planar surface124aof the first intermediate substrate layer124. The first and second bottom surfaces of the recess region may be non-coplanar surfaces. For example, the first bottom surface of the recess region is a step lower relative to the second bottom surface. The step height between the first and second bottom surfaces is, for example, defined by the thickness of the first intermediate substrate layer124. In one embodiment, the exposed portion of the top planar surface126aof the second intermediate substrate layer126corresponds to a lid-attach region of the package substrate120. For example, a package lid170is mounted onto the lid-attach region, as will be described in more detail below. The sidewalls of the recess region are defined by inner sidewalls of the top substrate layer128and inner sidewalls of the first and second intermediate substrate layers124and126.

In one embodiment, the recess region is defined with a die region102and a non-die region104surrounding the die region102. The die region102is, for example, concentrically positioned within the periphery of the first bottom surface. Other configurations of the die and non-die regions may also be useful. As shown, a semiconductor die or chip130is mounted onto the first bottom surface of the recess region in the die region102. The semiconductor die130includes a first major surface130aand a second major surface130bopposite to the first major surface. The first major surface130amay be referred to as the top surface and the second major surface130bmay be referred to as the bottom surface. Other designations for the first and second major surfaces may also be useful.

The top surface130aof the semiconductor die130includes openings in a final passivation layer to expose conductive die pads (not shown). The die pads serve as contact terminals for electrical connections to the internal circuitry of the semiconductor die130. The die pads are, for example, formed of a conductive material, such as copper (Cu), aluminum (Al), Gold (Au), Silver (Ag), Nickel (Ni), solder material, or the alloys of these materials, or a combination thereof. Other types of conductive material may also be useful. The die pads may be arranged into one or more rows disposed along the periphery of the top surface130a. Other arrangements of die pads may also be useful.

In one embodiment, the bottom surface130bof the semiconductor die130is mounted onto the die region of the first bottom surface of the recess region using a die attach layer (not shown). The die attach layer is, for example, an adhesive layer. Various adhesive material may be used to form the die attach layer. For example, the die attach layer may be a polymer material, including epoxy resin paste, polyimide tape, or the like. Other types of adhesive material, including solder material, may also be used to form the die attach layer. The die attach layer directly attaches the bottom surface130bof the semiconductor die130to the bottom substrate layer122.

In one embodiment, a plurality of wire bonds135are provided to electrically connect the die pads on the top surface130aof the semiconductor die130to the bond pads150on the second bottom surface of the recess region. The wire bonds135, for example, may be formed of any suitable metal material such as, but not limited to, Cu, Au, Ag, Al, or the alloys of these materials, or a combination thereof. Other types of conductive material may also be used. The wire bonds135create electrical connection between the interconnect structures (e.g., bond pads, conductive traces, via contacts, terminal pads) of the package substrate120and the semiconductor die130.

In one embodiment, a dam structure160is disposed within the recess region. The dam structure160, for example, substantially surrounds the semiconductor die130and wire bonds135, as shown particularly inFIG. 1b. The dam structure160extends along the first and second bottom surfaces of the recess region. For example, the portion of the dam structure conformally extends across the bond pads150disposed on the second bottom surface of the recess region. Alternatively, in the case where the bond pads150are spaced away from the side wall of the recess region (e.g., the inner sidewall of the second intermediate substrate layer126), the dam structure is positioned between the bond pads150and the sidewall of the recess region.

In one embodiment, the dam structure160abuts sidewalls of the recess region below the lid-attach region. For example, the dam structure160contacts and extends along inner sidewalls of the first and second intermediate substrate layers124and126. Other configurations for the dam structure may also be useful. For example, the dam structure160may also be positioned a distance away from the sidewalls of the recess region.

The dam structure160may include any suitable materials for forming a barrier structure against an encapsulation material. In one embodiment, the dam structure160includes a different dielectric material as the package substrate120. For example, the dam structure may be formed from epoxy based dielectric material, such as epoxy resin. Alternatively, providing a dam structure160having a same dielectric material as the package substrate120may also be useful. For example, the dam structure may be formed from ceramic material. Other suitable materials, including metal material and organic material may also be used to form the dam structure.

The dam structure160includes a top surface positioned at a height above the semiconductor die130and wire bonds135. The top surface of the dam structure160is a planar topmost surface having a substantially same height extending throughout the entire top surface of the dam structure160. In one embodiment, the dam structure, for example, extends upwardly from the exposed top planar surface122aof the bottom substrate layer122, and the exposed top planar surface124aof the first intermediate substrate layer124, to a same height below the top planar surface126aof the second intermediate substrate layer126. For example, the top surface of the dam structure160is a step lower relative to the lid-attach region (exposed portion of the top planar surface126a) of the package substrate120. The reference numeral190denotes the height difference (or step height) between the top surface of the dam structure160and the lid-attach region, as shown particularly inFIG. 1c. Alternatively, the dam structure160may also be configured with a height dimension aligned to the height dimension of the lid-attach region. Other configurations of the dam structure160and lid-attach region may also be useful.

The semiconductor package100includes a package lid170attached to the lid-attach region corresponding to the exposed top planar surface126aof the second intermediate substrate layer126. The package lid170includes opposing top and bottom surfaces. The package lid170may be formed from any suitable materials including transparent material (e.g., glass) or opaque material (e.g., metal or ceramic). In one embodiment, the package lid170includes a centrally located aperture175extending vertically through the package lid170, as shown particularly inFIGS. 1aand 1c. The aperture175, for example, extends from the top surface of the package lid to the bottom surface of the package lid. The package lid may include a same thickness extending throughout. In one embodiment, the top and bottom surfaces of the package lid170include a non-planar topography. For example, the central region of the package lid170protrudes upwardly relative to the peripheral region of the package lid170. The package lid170, in combination with the recess region of the package substrate120, defines a cavity180within which the semiconductor die130is enclosed, as shown particularly inFIG. 1c.

In one embodiment, the semiconductor die130may be a pressure sensor die130and the package lid170may be configured to accommodate the pressure sensor die130disposed in the cavity180. For example, the aperture175may be a vent hole to facilitate communication between the pressure sensor die130and the environment outside of the semiconductor package100for pressure sensing. Although an oval-shaped aperture175is illustrated inFIG. 1a, it is understood that the aperture175may also be configured with other geometrical shapes such as, but not limited to, rectangular, square and circular shapes. A person of ordinary skill in the art would appreciate that the package lid170may be configured to accommodate other types of semiconductor die130without departing from the spirit of the invention described herein. For example, the package lid170may be a transparent package lid170devoid of any openings to accommodate an image sensor die130.

The peripheral region of the package lid170may be attached to the lid-attach region using an adhesive layer165. The adhesive layer165, for example, bonds the bottom surface of the package lid170to the exposed top surface of the second intermediate substrate layer126. The adhesive layer165may an adhesive paste or film having a polymer material, including epoxy resin paste, polyimide tape or the like. Other types of adhesive material, including solder material, may also be used to form the adhesive layer165.

The semiconductor package100includes an encapsulant185disposed within the cavity180to completely encapsulate the semiconductor die130and wire bonds135. For example, the encapsulant185contacts the bond pads150and the first and second bottom surfaces of the recess region, as shown particularly inFIG. 1c. In one embodiment, the encapsulant185is formed from an encapsulation material. The encapsulation material may be a mold compound such as, but not limited to, epoxy resin. Other suitable types of encapsulation material may also be useful. The encapsulant185serves to protect the semiconductor die130and wire bonds135mechanically and environmentally from the outside environment. For example, the encapsulant185protects the semiconductor die130from moisture. The encapsulant185fills the cavity180to a height above the semiconductor die130from the first bottom surface of the recess region to define a height of the encapsulant185. In one embodiment, the encapsulant185partially fills the cavity180to a height below the top surface of the dam structure160. The dam structure160, for example, surrounds and extends above the top of the encapsulant185, as shown particularly inFIGS. 1band1c.

The semiconductor package100described herein advantageously includes a dam structure160, which functions as a reservoir (e.g., mold reservoir) within the cavity180to contain the encapsulant185and prevent the encapsulant from extending to the lid-attach region, as described in conjunction withFIGS. 5a-5e.

FIG. 2shows a cross-sectional view of another embodiment of a semiconductor package200in accordance with the present disclosure. The semiconductor package200is similar to that described inFIGS. 1a-1c. For example, the semiconductor package200includes a cavity180within which a semiconductor die130is enclosed. Common elements and features having the same reference numerals may not be described or described in detail. In the interest of brevity, the description below primarily focuses on the difference(s) of the semiconductor package200, as shown inFIG. 2, as compared with the semiconductor package100shown inFIGS. 1a-1c.

Referring toFIG. 2, a dam structure260is disposed within the cavity180in the recess region. The dam structure260, for example, substantially surrounds the semiconductor die130and wire bonds135. The dam structure260is disposed directly on the first and second bottom surfaces of the recess region. In one embodiment, the dam structure260abuts sidewalls of the recess region below the lid-attach region. For example, the dam structure260contacts and extends along inner sidewalls of the first and second intermediate substrate layers124and126. Other configurations for the dam structure may also be useful. For example, the dam structure260may also be positioned away from sidewalls of the recess region. The dam structure260may include any suitable materials for forming a barrier structure against an encapsulation material. In one embodiment, the dam structure260includes a different dielectric material as the package substrate120. For example, the dam structure may be formed from epoxy based dielectric material, such as epoxy resin. Alternatively, providing a dam structure having a same dielectric material as the package substrate120may also be useful. For example, the dam structure may be formed from ceramic material. Other materials, including metal material and organic material may also be used to form the dam structure.

The dam structure260includes a top surface positioned at a height above the semiconductor die130and wire bonds135. The top surface of the dam structure260is a planar topmost surface having a substantially same height extending throughout the entire top surface of the dam structure260. In one embodiment, the dam structure, for example, extends upwardly from the exposed top planar surface122aof the bottom substrate layer122, and the exposed top planar surface124aof the first intermediate substrate layer124, to a same height above the top planar surface126aof the second intermediate substrate layer126. For example, the top surface of the dam structure260is a step higher relative to the lid-attach region (exposed portion of the top planar surface126a) of the package substrate120. The reference numeral290denotes the height difference (or step height) between the top surface of the dam structure260and the lid-attach region. Other configurations of the dam structure260and the lid-attach region may also be useful.

Similar to the advantages described with respect toFIGS. 1a-1c, the dam structure260functions as a mold reservoir within the cavity180to contain the encapsulant185. For example, the dam structure260prevents encapsulation material from encroaching onto the lid-attach region when conventional process parameters are employed to form the encapsulant185, as described in conjunction withFIGS. 5a-5e.

FIG. 3shows a cross-sectional view of yet another embodiment of a semiconductor package300in accordance with the present disclosure. The semiconductor package300is similar to that described inFIGS. 1a-1c. For example, the semiconductor package300includes a cavity380within which a semiconductor die130is enclosed. Common elements and features having the same reference numerals may not be described or described in detail. In the interest of brevity, the description below primarily focuses on the difference(s) of the semiconductor package300, as shown inFIG. 3, as compared with the semiconductor package100shown inFIGS. 1a-1c.

Referring toFIG. 3, the semiconductor package300includes a package substrate320. In one embodiment, the package substrate320may include a plurality of dielectric substrate layers that may be laminated or built-up. For example, the package substrate320includes a bottom substrate layer122, an intermediate substrate layer124disposed on the bottom substrate layer122, and a top substrate layer328disposed on the intermediate substrate layer124. Other configurations of a multi-layer package substrate320may also be useful. In one embodiment, the package substrate320is a laminate-based multi-layer ceramic substrate. For example, the package substrate320includes an intermediate ceramic substrate layer124sandwiched between top and bottom ceramic substrate layers328and122. Other types of dielectric substrate layer may also be used to form the package substrate320. Each of the package substrate layers includes a first major surface (e.g.,122a,124a,328a) and a second major surface (e.g.,122b,124b,328b) opposite to the first major surface. The first major surface of the substrate layers may be referred to as the top planar surface and the second major surface of the substrate layers may be referred to as the bottom planar surface. Other designations for the first and second major surfaces may also be useful.

The semiconductor package300includes a package lid370attached to a lid-attach region defined on the top planar surface328aof the top substrate layer328. The package lid370includes opposing top and bottom surfaces. The package lid370may be formed from any suitable materials including transparent material (e.g., glass) or opaque material (e.g., metal or ceramic). In one embodiment, the package lid370includes a centrally located aperture175extending vertically through the package lid370. The aperture175, for example, extends from the top surface of the package lid to the bottom surface of the package lid. The package lid may include a same thickness extending throughout. In one embodiment, the entire top and bottom surfaces of the package lid370include a planar topography. For example, the package lid370may be configured with a flat shape. The package lid370, in combination with the recess region of the package substrate120, defines a cavity380within which the semiconductor die130is enclosed.

In comparison to the semiconductor package100shown inFIGS. 1a-1c, the semiconductor package300described with respect toFIG. 3aincludes additional benefits. For example, semiconductor package300includes a package substrate320having fewer intermediate substrate layers, and a flat shape package lid370mounted onto the package substrate320. As a result, the semiconductor package300advantageously includes a smaller cavity380and a reduced overall package thickness dimension relative to the semiconductor package100described inFIGS. 1a-1c.

FIGS. 4a-4cshows various views of another embodiment of a semiconductor package400in accordance with the present invention. In particular,FIG. 4ashows a top view of a semiconductor package400having a package lid170,FIG. 4bshows a simplified plan view of the semiconductor package400with the package lid170removed, andFIG. 4cshows a cross-sectional view of the semiconductor package400taken along the A-A plane. The semiconductor package400is similar to that described inFIGS. 1a-1c. For example, the semiconductor package400includes a cavity180within which a semiconductor die130is enclosed. Common elements and features having the same reference numerals may not be described or described in detail. In the interest of brevity, the description below primarily focuses on the difference(s) of the semiconductor package400shown inFIGS. 4a-4c, as compared with the semiconductor package100shown inFIGS. 1a-1c.

Referring toFIG. 4c, a dam structure460is disposed within the cavity180in the recess region. The dam structure460, for example, substantially surrounds the semiconductor die130and wire bonds135. The dam structure460is disposed directly on the first and second bottom surfaces of the recess region. In one embodiment, the dam structure460is positioned a distance away from sidewalls of the recess region below the lid-attach region, as shown particularly inFIGS. 4band 4c. For example, a gap region465separates the dam structure460from the inner sidewalls of the first and second intermediate substrate layers124and126. The gap region465, for example, surrounds the entire dam structure460. Other configurations for the dam structure may also be useful. In one embodiment, the bond pads150extend beyond a side of the dam structure460to a side wall of the recess region such that the gap region465overlaps and partially exposes the bond pads150. Alternatively, in the case where the bond pads150are spaced away from the side wall of the recess region, the bond pads150may be disposed between the dam structure460and the semiconductor die130such that the gap region465does not overlap and expose the bond pads150. The dam structure260may include any suitable materials. For example, the dam structure may be formed from same or different dielectric materials as the package substrate120. Providing a dam structure formed from metal material or organic material may also be useful.

The dam structure460includes a top surface positioned at a height above the semiconductor die130and wire bonds135. A height of the dam structure460is similar to that described with respect to the dam structure160described with respect toFIGS. 1a-1c. For example, the height of the top surface of the dam structure460is a step lower relative to the height of the lid-attach region of the package substrate120. Other configurations of the dam structure460and the lid-attach region may also be useful.

Similar to the advantages described with respect toFIGS. 1a-1c, the dam structure460functions as a mold reservoir within the cavity180of the semiconductor package400to ensure that the encapsulant185does not encroach onto the lid-attach region during manufacturing processes to form the encapsulant185.

FIGS. 5a-5eshow cross-sectional views of an embodiment of a process500for forming a semiconductor package. The process500may be employed to form, for example, a semiconductor package same or similar as that described inFIGS. 1a-1c,2and3. In the interest of brevity, common elements and features having the same reference numerals may not be described or described in detail.

Referring toFIG. 5a, a package substrate120is provided. The package substrate120may be processed to include a plurality of dielectric substrate layers laminated to form a multi-layer package substrate embedded with interconnect structures. In one embodiment, ceramic fabrication processes are employed to form the multi-layer package substrate120. For example, conventional fabrication processes are employed to form a multi-layered ceramic package substrate having a desired interconnect pattern corresponding to a plurality of interconnected line levels and via levels defined by the interconnect structures of the semiconductor package. Other suitable processes may also be employed to form the package substrate120and/or the interconnect structures. In an alternative embodiment, the interconnect structures may be formed by a printing process. The printing process may be an inkjet printing process as described in, for example, U.S. patent application Ser. No. 15/788,753, filed on Oct. 19, 2017, which is herein incorporated by reference in its entirety for all purposes.

The interconnect structures include, for example, bond pads150, conductive traces154, via contacts152and156, and terminal pads160. The conductive traces154and via contacts152and156provide an electrical connection from the bond pads150to the terminal pads160. The interconnect structures may be formed from any suitable conductive material, including Cu, A, Au, Ag, Ni, solder material, or the alloys of these materials, or a combination thereof. Other types of conductive material may also be employed.

The package substrate120includes at least one active device region corresponding to a region for processing a semiconductor package. In one embodiment, openings of various sizes are formed in the substrate layers within the active device region to form a recess region515in the substrate120. For example, a first rectangular opening is formed in the first intermediate substrate layer124, a second rectangular opening is formed in the second intermediate substrate layer126and a third rectangular opening is formed in the top substrate layer128. The various rectangular openings may be formed by mask and etch techniques. Other techniques may also be employed to form the rectangular openings.

The first rectangular opening formed in the first intermediate substrate layer124partially exposes the top planar surface122aof the bottom substrate layer122and includes a sufficient size to accommodate a semiconductor die disposed therein. For example, the exposed portion of the top planar surface122aof the bottom substrate layer122is a sufficient size to accommodate a die region102and a non-die region104surrounding the die attach region.

The second rectangular opening formed in the second intermediate substrate layer126completely exposes the first rectangular opening and partially exposes the top planar surface124aof the first intermediate substrate layer124. The exposed portion of the top planar surface124acorresponds to the location where bond pads150and a dam structure are to be formed on the first intermediate substrate layer124.

The third rectangular opening formed in the top substrate layer128completely exposes the second rectangular opening and partially exposes the top planar surface126aof the second intermediate substrate layer126. The exposed portion of the top planar surface126acorresponds to the location where the lid-attach region510is defined on the second intermediate substrate layer126. The first, second and third rectangular openings are superimposed to form a recess region515of the package substrate120. Sidewalls of the recess region515are, for example, defined by inner sidewalls of the different substrate layers. Exposed portions of the top planar surfaces122aand124adefine first and second bottom surfaces of the recess region515respectively.

Although one active device region is illustrated, it is to be understood that the package substrate120may be configured with two or more active device regions separated by inactive device regions for the assembly of a plurality of semiconductor packages. For example, the package substrate120may be configured with a plurality of active device regions arranged in a matrix format.

Referring toFIG. 5b, a semiconductor die130is mounted onto the exposed top planar surface122aof the bottom substrate layer122within the die region102. The semiconductor die130includes a top surface130aand a bottom surface130b. The top surface130aof the semiconductor die130includes openings in a final passivation layer to expose conductive die pads (not shown). The die pads serve as contact terminals for electrical connections to the internal circuitry of the semiconductor die130. The die pads are, for example, formed of a conductive material, such as Cu, Al, Au, Ag, Ni, solder material, or the alloys of these materials, or a combination thereof. Other types of conductive material may also be useful. The die pads may be arranged into one or more rows disposed along the periphery of the top surface130aof the semiconductor die130. Other arrangements of die pads may also be useful.

In one embodiment, the bottom surface130bof the semiconductor die130is attached to the top planar surface122aof the bottom substrate122using a die attach layer (not shown). The die attach layer, for example, covers the entire bottom surface130bof the semiconductor die130. The die attach layer may include an adhesive material to bind and fix the semiconductor die130in position within the recess region515. For example, the die attach layer may be a polymer material, including epoxy resin paste, polyimide tape, or the like. Other suitable types of adhesive material may also be employed.

In one embodiment, a plurality of wire bonds135are formed to electrically connect the semiconductor die130to the interconnect structures of the package substrate120. For example, a first end of the wire bonds135are bonded to the die pads of the semiconductor die130and a second end of the wire bonds135are bonded to the bond pads150formed on the exposed portion of the top surface124aof the first intermediate layer124. Each wire bond, for example, corresponds to a metal wire. The wire bonds may be formed from Au, Cu, Ag, Al, Ni or any alloy thereof. Other types of conductive material may also be used to form the wire bonds.

Referring toFIG. 5c, a dam structure160is formed within the recess region515of the package substrate120. In one embodiment, the dam structure160is a dielectric structure formed from any suitable techniques, including dispensing, jetting and bonding techniques. For example, dielectric material is dispensed into the recess region515to form the dam structure160at a predetermined position. In one embodiment, the dam structure160includes an epoxy based dielectric material. For example, suitable process parameters are employed to dispense epoxy resin into the recess region515to form the dam structure160having a desired height and thickness. In one embodiment, the dam structure160is formed to a height below the lid-attach region510. For example, the top surface of the dam structure160is a step lower relative to the lid-attach region510. Other dielectric materials may also be used to form the dam structure160.

In an alternative embodiment, the dam structure160includes a ceramic material same as the package substrate120. In such case, the dam structure160may be formed integrally and concurrently with the corresponding substrate layers124,126and128. For example, the dam structure may be a ceramic structure having a top surface that is in alignment with the lid-attach region (or top surface126aof the second intermediate substrate layer). Other materials, including metal material and organic material may also be used to form the dam structure160.

In one embodiment, the dam structure160abuts sidewalls of the recess region below the lid-attach region. For example, the dam structure160contacts and extends along inner sidewalls of the first and second intermediate substrate layers124and126. Positioning the dam structure away from sidewalls of the recess region may also be useful. The dam structure160defines a reservoir (e.g., mold reservoir) within the cavity180.

AlthoughFIG. 5cillustrates a process for forming an epoxy based dielectric dam structure160having a top surface positioned below the lid-attach region510, it is to be appreciated that the dam structure160may also be configured to extend upwardly above the lid-attach region510, as described particularly inFIG. 2. For example, the height of the top surface of the dam structure160may be a step higher relative to the lid-attach region510.

Referring toFIG. 5d, an encapsulant185is formed within the recess region515. The top surface of the encapsulant185extends above the wire bonds135and semiconductor die130. For example, the encapsulant185surrounds the semiconductor die130and wire bonds135. In one embodiment, the encapsulant185is configured to encapsulate exposed portions of the bond pads150. For example, the encapsulant185contacts and covers exposed portions of the bond pads150between the dam structure160and the semiconductor die130. The encapsulant185provides a rigid and mechanically strong structure to protect the semiconductor die130from mechanical stresses and moisture in the environment.

In one embodiment, the encapsulant185is formed by dispensing liquid encapsulant into the recess region515to partially fill the reservoir defined by the dam structure160. The liquid encapsulant, for example, extends to a height above the semiconductor die130and wire bonds135. The process parameters for dispensing the liquid encapsulant may be configured such that liquid encapsulant fills the recess region515to a height below the top surface of the dam structure160. For example, the height of the top surface of the dam structure160provides a dispensing endpoint for dispensing liquid encapsulant to a predetermined height. In one embodiment, the liquid encapsulant includes a low viscosity mold compound. For example, the liquid encapsulant includes epoxy resin in liquid form. Other types of liquefied molding compound such as ceramic, plastic, or a combination thereof, may also be used to form the encapsulant185. After the liquid encapsulant is dispensed into the recess region515, a curing process is performed to increase the viscosity of the liquid encapsulant and form the structurally rigid encapsulant185.

Referring toFIG. 5e, a package lid170is mounted onto the package substrate120. The package lid170is, for example, attached to the lid-attach region510defined on the package substrate120. The package lid170may be formed from any suitable materials including transparent material (e.g., glass) or opaque material (e.g., metal or ceramic). The package lid170, in combination with the recess region515of the package substrate120, defines a cavity180within which the semiconductor die130and encapsulant185is enclosed.

An adhesive layer165may be formed to bond and fix a peripheral region of the package lid170to the exposed portion of the top surface126aof the second intermediate substrate layer126corresponding to the lid-attach region510. In one embodiment, the adhesive layer165is formed by dispensing an adhesive material onto the lid-attach region510. The adhesive layer165may be an adhesive paste or film having a polymer material, including epoxy resin paste, polyimide tape, or the like. Other types of adhesive material may also be useful.

It is to be appreciated that attaching the package lid170to a lid-attach region510disposed in the recess region515advantageously allows sidewalls of the recess region515(corresponding to inner sidewalls of the top substrate layer128) to mechanically restrict the package lid170from any undesirable lateral movements during the process of mounting the package lid170to the lid-attach region.

In one embodiment, the process continues by performing a package singulation process. The singulation process, for example, mechanically separates the active device regions of the package substrate120from one another to form individual semiconductor packages100, such as that described inFIGS. 1a-1c.

Conventional methods for encapsulating a semiconductor die housed within a recess of a semiconductor package substrate generally utilize the height of the lid-attach region for endpoint monitoring, which often result in liquefied encapsulant material encroaching onto the lid-attach region of the package substrate. The presence of encapsulant material on the lid-attach region undesirably results in poor adhesion of the package lid to the lid-attach region of the package substrate. Existing solutions to circumvent manufacturing defects associated with encroachment of liquefied encapsulant material onto the lid-attach region include forming multiple layers of adhesive material onto the lid-attach region. For example, a first adhesive layer may be formed on the lid-attach region prior to encapsulating the semiconductor die and a second adhesive layer may be formed on the first adhesive layer after the semiconductor die is encapsulated.

In comparison, the present invention improves the process window for encapsulating the semiconductor die130by providing a dam structure160within the recess region515. The dam structure160functions as a reservoir within the recess region515to contain and prevent liquefied encapsulant material from encroaching onto the lid-attach region510during the process of encapsulating the semiconductor die130. For example, the dam structure160is configured with a top surface positioned below the lid-attach region510to improve endpoint control for dispensing liquid encapsulant into the recess region515. Alternatively, the dam structure may be configured with a top surface positioned above the lid-attach region510, as described inFIG. 2. Providing a dam structure that extends to a height above the lid-attach region510prevents liquefied encapsulant material from encroaching onto the lid-attach region510when conventional process parameters are employed to dispense liquid encapsulant into the recess region515. In addition, the present invention allows the adhesive layer165to be reliably formed in a single process step, thereby improving throughput and reducing manufacturing costs. Accordingly, the present invention provides a semiconductor package with improved reliability and yield.

FIGS. 6a-6cshow cross-sectional views of another embodiment of a process600for forming a semiconductor package. The process may be employed to form, for example, a semiconductor package same or similar as that described inFIGS. 4a-4c. The process600includes similar process steps as that described inFIGS. 5a-5e. In the interest of brevity, common elements, common process steps and features having the same reference numerals may not be described or described in detail.

Referring toFIG. 6a, a package substrate120is provided. The package substrate120may be partially processed to form same or similar features described inFIGS. 5a-5b. For example, the partially processed semiconductor package is at the same stage as that described inFIG. 5b.

Referring toFIG. 6b, the process600continues by forming a dam structure460within the recess region515. In one embodiment, the dam structure460includes a dielectric material. For example, the dam structure460may be an epoxy based dielectric structure or a ceramic structure. Other types of materials may also be used to form the dam structure460. The dam structure460may be formed from any suitable techniques, as described with respect toFIG. 5c.

In one embodiment, the dam structure460is formed to a height below the lid-attach region510. For example, the top surface of the dam structure160is a step lower relative to the lid-attach region510. In one embodiment, the dam structure460is positioned a distance away from sidewalls of the recess region515below the lid-attach region510. For example, a gap region465separates the dam structure460from the inner sidewalls of the first and second intermediate substrate layers124and126. Other configurations for the dam structure may also be useful. The dam structure460defines a reservoir surrounded by a gap region465within the cavity180.

Referring toFIG. 6c, an encapsulant185is formed within the reservoir in the recess region515. The top surface of the encapsulant185surrounds and extends above the wire bonds135and semiconductor die130. In one embodiment, the encapsulant185is configured to encapsulate exposed portions of the bond pads150. For example, the encapsulant185contacts and covers portions of the bond pads150exposed between the dam structure460and the semiconductor die130. In one embodiment, the encapsulant185is formed by dispensing liquid encapsulant into the recess region515to partially fill the reservoir defined by the dam structure460. The process parameters for dispensing the liquid encapsulant may be configured such that liquid encapsulant fills the recess region515to a height below the top surface of the dam structure460. For example, the height of the top surface of the dam structure460provides an endpoint reference for controlled dispensing of liquid encapsulant. After the liquid encapsulant is dispensed into the reservoir, a curing process is performed to increase the viscosity of the liquid encapsulant and form the structurally rigid encapsulant185.

In one embodiment, the process600continues as described with respect toFIG. 5e. For example, the process600continues by attaching a package lid170to the lid-attach region510to define a cavity180within which the semiconductor die130and encapsulant185is enclosed. Thereafter, a package singulation process mechanically separates the active device regions of the package substrate120from one another to form individual semiconductor packages400, such as that described inFIGS. 4a-4c.

In comparison to the process500described with respect toFIGS. 5a-5e, the process600described inFIGS. 6a-6cfurther improves the process window for encapsulating the semiconductor die130by surrounding the dam structure460with a gap region465. For example, the dam structure460functions as a primary mold reservoir within the recess region515to contain liquefied encapsulant material dispensed into the recess region515, while the gap region465functions as a secondary mold reservoir to contain any excess liquefied encapsulant material that may overflow from the primary mold reservoir. Accordingly, the endpoint control for dispensing liquid encapsulant material into the recess region515may be less stringent.