SEMICONDUCTOR DEVICE INCLUDING HYDROGEN INTRODUCTION LAYER PROVIDED ON SEMICONDUCTOR SUBSTRATE AND METHOD OF FORMING THE SAME

An apparatus includes: a first semiconductor substrate; a plurality of first regions extending in parallel in a first direction on the first semiconductor substrate, each of the plurality of first regions including a plurality of first shallow trench isolations (STI) therein; and a plurality of second regions each extending between corresponding adjacent two of the plurality of first regions, each of the plurality of second regions including a plurality of second STIs and a plurality of active regions arranged alternately and in line in the first direction. Each of the plurality of second STIs has a greater depth than each of the plurality of first STIs.

BACKGROUND

In recent years, semiconductor devices exemplified by dynamic random access memories (DRAMs) have been desired to have increased memory capacity. However, it is technically difficult to increase the memory capacity by fining processing dimensions. Therefore, there has been developed a technique which reduces the planar area of a memory cell by vertically stacking an access transistor and a storage capacitor of the memory cell to increase the memory capacity.

For example, a technique of forming an access transistor, a storage capacitor, and peripheral transistors of a memory cell on separate semiconductor substrates, and then bonding these substrates together to form DRAM has been developed as a technique for vertically stacking an access transistor and a storage capacitor of a DRAM memory cell.

DETAILED DESCRIPTION

Various embodiments of the present disclosure will be explained below in detail with reference to the accompanying drawings. The following detailed description refers to the accompanying drawings that show, by way of illustration, specific aspects, and various embodiments of the present disclosure. The detailed description provides sufficient detail to enable those skilled in the art to practice these embodiments of the present disclosure. Other embodiments may be utilized, and structural, logical, and electrical changes may be made without departing from the scope of the present disclosure. The various embodiments disclosed herein are not necessary mutually exclusive, as some disclosed embodiments can be combined with one or more other disclosed embodiments to form new embodiments.

Semiconductor devices according to first and second embodiments and a method of manufacturing the same will be described below with reference to the drawings. In the following description, a dynamic random access memory (hereinafter referred to as DRAM) will be illustrated as a semiconductor device. In the description of the embodiments, common or related elements or substantially the same elements are denoted by the same reference numerals, and duplicative description thereof will be omitted. In the following figures, the dimensions and dimensional ratios of the respective portions in the respective figures do not necessarily match the dimensions and dimensional ratios in the embodiments. Further, in the following description, a Y-direction is a direction perpendicular to an X-direction. A Z-direction is a direction perpendicular to an X-Y plane which is a plane of the semiconductor substrate, and may be referred to as a vertical direction.

The method of manufacturing the semiconductor device according to the first embodiment will be described below. As shown inFIGS.1A and1B, a first insulating film12is formed on a semiconductor substrate10including a memory cell region M and a peripheral circuit region N adjacent to the memory cell region M. Next, isolation trenches14are formed by using a known lithography technique and an anisotropic dry etching technique. The semiconductor substrate10includes, for example, a disk-shaped single-crystal silicon wafer having a mirror-finished principal surface. The first insulating film12contains an insulating material, for example, silicon nitride (SiN). The first insulating film12is formed, for example, by chemical vapor deposition (CVD). A plurality of isolation trenches14are arranged in the memory cell region M as shown inFIG.1A. Each isolation trench14has a linear shape and is obliquely arranged in plan view, and the plurality of isolation trenches14are arranged in parallel to one another.

Next, as shown inFIG.2, a second insulating film16is formed to fill the isolation trenches14and cover the surface of the first insulating film12. The second insulating film16contains an insulating material, for example, silicon dioxide (SiO2). The second insulating film16is formed, for example, by CVD.

Next, as shown inFIG.3, a hydrogen-implanted layer18is formed at a predetermined depth in the semiconductor substrate10. Hydrogen (H) is introduced into the hydrogen-implanted layer18. Hydrogen is formed, for example, by ion implantation of hydrogen ions (H+). The ion implantation is performed, for example, under the condition of an implantation energy of 50 Kev and an implantation dose of 1E16 atms/cm2. The hydrogen-implanted layer18is arranged between a lower semiconductor substrate10aand the semiconductor substrate10above the lower semiconductor substrate10a.In the first embodiment, hydrogen ions are implanted into the semiconductor substrate10in a state where structures such as the isolation trenches14have been formed.

Next, as shown inFIG.4, the semiconductor substrate10is rotated such that an X-axis is rotated around a Y-axis by 180 degrees. Next, by a wafer bonding technique, the semiconductor substrate10is bonded at a bonding surface D1to a first support substrate20on which a thin insulating film has been formed in advance. The surface of the second insulating film16and the surface of the first support substrate20are in contact with each other at the bonding surface D1.

Next, as shown inFIG.5, the semiconductor substrate10having the isolation trenches14formed therein and the first support substrate20bonded thereto is subjected to an annealing treatment at a temperature of 400 to 500° C. in an N2 atmosphere, for example, for 30 minutes. As a result, the hydrogen-implanted layer18expands, and the lower semiconductor substrate10ais peeled off at the hydrogen-implanted layer18. The lower semiconductor substrate10awhich is a part of the semiconductor substrate10is peeled off by forming the hydrogen-implanted layer18and performing the annealing treatment as described above, thereby thinning the semiconductor substrate10, which is called a smart cut technique. As described above, in the first embodiment, the smart cut technique is performed on the semiconductor substrate10on which patterned structures such as the isolation trenches14are formed.

Next, as shown inFIGS.6A and6B, a third insulating film22is formed on the semiconductor substrate10, and then a first resist24having openings26formed therein is formed. The third insulating film22contains an insulating material, for example silicon dioxide. The first resist24is formed using the known lithography technique. The openings26are arranged to be equally spaced from one another above and between the isolation trenches14located at predetermined positions.

Next, anisotropic dry etching is performed using the first resist24as a mask. This anisotropic dry etching penetrates the third insulating film22, and further etches a part of the semiconductor substrate10to form active isolation holes28. Next, after the first resist24is removed, an insulating material is formed to fill the active isolation holes28and cover the third insulating film22. The insulating material contains, for example, silicon dioxide. Next, etch back is performed by anisotropic dry etching to etch the insulating material, expose the upper surface of the third insulating film22, and leave pillar-shaped active isolation insulating films30in the active isolation holes28. The etch back by anisotropic dry etching is performed, for example, by setting an etching time in advance. A part of the side surface of the active isolation insulating film30is in contact with the side surface of the isolation trench14. Through the above steps, the structures shown inFIG.7are formed. The space between the isolation trenches14is an active region32serving as an island, and the isolation trenches14or the active isolation insulating films30have a function of isolating the active regions32. In a direction in which the active regions32extend, the active isolation insulating films30and the active regions32are alternately arranged in a row.

Next, as shown inFIG.8, the semiconductor substrate10is rotated such that the X-axis is rotated around the Y-axis by 180 degrees. Next, by the wafer bonding technique, the semiconductor substrate10is bonded at a bonding surface D2to a second support substrate34on which a thin insulating film has been formed in advance. The surface of the third insulating film22and the surface of the second support substrate34are in contact with each other at the bonding surface D2. Next, the first support substrate20is removed by etching. Anisotropic or isotropic dry etching can be used for this etching.

Next, as shown inFIGS.9A and9B, the second insulating film16and the first insulating film12are polished and removed by the CMP technique until the surface of the semiconductor substrate10is exposed. As a result, the second insulating film16remains in the isolation trenches14, and becomes isolation insulating films36. As shown inFIG.9A, the active isolation insulating films30are arranged at predetermined intervals between adjacent isolation insulating films36along the isolation insulating films36. As shown inFIGS.9A and9B, the side surfaces of the active isolation insulating films30are in contact with the isolation insulating films36adjacent thereto. A contact length P between the isolation insulating film36and the active isolation insulating film30is set in advance according to an etch-back amount described later with reference toFIGS.11A,11B and11C.

Next, a peripheral isolation38is formed in the peripheral circuit region N as shown inFIGS.10A and10B. The peripheral isolation38is formed by the following steps. First, a groove is formed in the peripheral circuit region N by using the known lithography technique and the anisotropic dry etching technique. Next, formation of an insulating material using a CVD technique and etch back using anisotropic dry etching are performed, whereby an insulating material is left in the groove. The peripheral isolation38contains an insulating material, for example contains silicon dioxide. Through the above steps, the structures shown inFIGS.10A and10Bare formed.

Next, word-lines40are formed as shown inFIGS.11A,11B and11C. The word-lines40are formed by the following steps. First, a plurality of trenches extending in parallel to the X-direction in the figure are formed. The trenches are formed using the known lithography technique and the anisotropic dry etching technique. The anisotropic dry etching is performed to the extent that at least the upper surfaces of the active isolation insulating films30are exposed, and parts of the active isolation insulating films30, the isolation insulating films36and the peripheral isolation38are etched. Next, a conductive material is formed so as to fill the trenches and cover the upper surfaces of the semiconductor substrate10, the isolation insulating films36and the peripheral isolation38. The conductive material is formed, for example, by CVD. Then, etch back is performed by anisotropic dry etching so as to remove the conductive material outside the trenches and leave the conductive material in the trenches. The word-lines40are formed in the trenches through the above steps. The word-lines40include the conductive material, for example, titanium nitride. The word-line40is arranged so as to straddle over a plurality of active isolation insulating films30. The bottom surface of the word-line40and the top surface of the active isolation insulating film30are in contact with each other. The active isolation insulating film30is sandwiched between the word-line40and the second support substrate34. The active isolation insulating film30is in contact with the bottom surface of the word-line40and the top surface of the second support substrate34. Each of the isolation insulating films36is sandwiched between the word-line40and the second support substrate34. Each of the isolation insulating films36is in contact with the bottom surface of the word-line40, but is not in contact with the top surface of the second support substrate34. The active isolation insulating film30has a greater depth than the isolation insulating film36in the Z-direction.

Through the above steps, the semiconductor device according to the first embodiment is formed. Thereafter, a peripheral circuit unit F and a capacitor unit G are connected in the same manner as in a second embodiment described later. As shown inFIGS.11A,11Band11C, the active regions32are electrically isolated by the isolation insulating films36and the active isolation insulating films30in the semiconductor device according to the first embodiment. The active isolation insulating films30are formed by a process different from that of the isolation insulating films36. The active isolation insulating films30are formed by forming the active isolation holes28from the back sides of the isolation insulating films36and filling the active isolation holes28with an insulating material.

The semiconductor device according to the embodiment makes it possible to reduce the planar area occupied by memory cells and peripheral circuits, thereby reducing the chip area of the semiconductor device. Therefore, it is possible to provide a semiconductor device which is reduced in cost.

A method of manufacturing a semiconductor device according to a second embodiment will be described below.

As shown inFIGS.12A and12B, a first semiconductor portion56and a first insulating portion58are laminated on a semiconductor substrate50to form films thereof. A memory cell region M and a peripheral circuit region N are provided on the semiconductor substrate50.

The semiconductor substrate50includes, for example, a disk-shaped single-crystal silicon wafer having a mirror-finished principal surface.

The first semiconductor portion56contains, for example, silicon (Si). The first semiconductor portion56can be formed as a film, for example, by epitaxial growth. The first insulating portion58includes, for example, a silicon nitride film (SIN). The first insulating portion58can be formed as a film, for example, by CVD.

Next, the first insulating portion58and the first semiconductor portion56are patterned by using a known lithography technique and an anisotropic dry etching technique. This etching causes the surface of the semiconductor substrate50to be exposed. As a result, a plurality of pillar structures K extending in a direction vertical to the semiconductor substrate50and arranged independently of one another are formed. The pillar structures K are formed in the memory cell region M. The pillar structures K are formed on the semiconductor substrate50, and the first semiconductor portion56and the first insulating portion58are laminated in each pillar structure K. A gap59is provided between the pillar structures K. Through the above steps, the structures shown inFIGS.12A and12Bare formed.

Next, as shown inFIGS.13A and13B, a first insulating film60and shield plates62are formed in the gaps59between the pillar structures K and in the peripheral circuit region N. A shield plate63is also formed near the boundary between the memory cell region M and the peripheral circuit region N. The shield plate63is formed around the memory cell region M. The first insulating film60contains an insulating material, for example, a silicon oxide film (SiO2). The shield plates62and63contain a conductive material, for example, polysilicon (poly-Si) doped with phosphorus (P) as impurities. The first insulating film60and the shield plates62and63can be formed, for example, by film formation of a conductive material using a CVD method and performing etch back by anisotropic dry etching. Thereafter, an insulating film is formed to cover the shield plates62and63with the first insulating film60.

Next, a hydrogen-implanted layer18is formed at a predetermined depth in the semiconductor substrate50. Hydrogen (H) is introduced into the hydrogen-implanted layer18. Hydrogen is formed, for example, by ion implantation of hydrogen ions (H+). The ion implantation is performed, for example, under the condition of an implantation energy of50Kev and an implantation dose of 1E16 atms/cm2. The hydrogen-implanted layer18is formed at a position deeper than the first semiconductor portion56. The hydrogen-implanted layer18is arranged between a lower semiconductor substrate50aand the semiconductor substrate50above the lower semiconductor substrate50a.

Here, the average projected range of hydrogen ions varies depending on the material through which the hydrogen ions pass. As shown inFIG.13B, silicon (Si) contained in the first semiconductor portion56and the shield plates62is abundant in the memory cell region M. On the other hand, silicon dioxide (SiO2) contained in the first insulating film60is abundant in the peripheral circuit region N. The average projected range of hydrogen ions is shorter in the case where hydrogen ions pass through silicon. Therefore, the average projected range of hydrogen ions to be implanted into the memory cell region M and the average projected range of hydrogen ions to be implanted into the peripheral circuit region N may differ. Therefore, in order to match the average projected ranges of hydrogen ions in the memory cell region M and the peripheral circuit region N, an adjustment portion for the average projected range which contains, for example, silicon dioxide or amorphous carbon having a predetermined film thickness may be provided on the peripheral circuit region N.

Next, as shown inFIGS.14A and14B, the semiconductor substrate50is rotated such that the X-axis is rotated around the Y-axis by 180 degrees. Next, the semiconductor substrate50is bonded at a bonding surface H2to a first support substrate69on which a third insulating film68has been formed in advance, by the wafer bonding technique. At the bonding surface H2, the surfaces of the first insulating film60and the first insulating portions58are in contact with the surface of the third insulating film68.

Next, as shown inFIGS.15A and15B, the smart cut technique is performed on the first support substrate69on which the pillar structures K and the shield plates62and63are formed. Specifically, an annealing treatment is performed at a temperature of 400 to 500° C. in an N2 atmosphere. As a result, the hydrogen-implanted layer18expands, so that the hydrogen-implanted layer18and the lower semiconductor substrate50aare peeled off. As described above, in the second embodiment, hydrogen ions are implanted into the first support substrate69on which patterned structures such as the pillar structures K and the shield plates62and63have been formed, and then the smart cut technique is performed.

Next, a step of forming a structure shown inFIGS.16A and16Bwill be described. A first doped layer70is formed at an upper portion of the first semiconductor portion56in the figure. The first doped layer70is formed, for example, by performing the ion implantation technique. The first doped layer70contains, for example, phosphorus (P) as impurities. Next, trenches71extending in the Y-direction in the figures are formed in a part of the first semiconductor portions56and the first insulating film60. The trenches71are formed, for example, by using the known lithography technique and the anisotropic dry etching technique. The anisotropic dry etching is performed under the condition that the etching rates of the first semiconductor portion56and the first insulating film60are substantially equal to each other. The bottom portions of the trenches71are controlled to be positioned above the lower surfaces of the first semiconductor portions56.

Next, for example, impurities, at least one of phosphorus or arsenic, are implanted into the first semiconductor portions56located at the bottom portions of the trenches71by ion implantation, and then a heat treatment is performed to activate the impurities. The heat treatment is performed at a temperature of 1050° C. in an inert gas atmosphere such as nitrogen, for example, by using a lamp annealing apparatus. As a result, the impurities doped in a first doped layer70, a second doped layer72and a third doped layer73are activated. In the formation of the second doped layer72and the third doped layer73, ion implantation is performed by using different implantation energies.

The first doped layer70, the second doped layer72, and the third doped layer73function as a source/drain region of an access transistor142which is a vertical transistor described later. The first semiconductor portion56functions as a channel region of the access transistor142. The third doped layer73functions as an extension portion of the source/drain region of the access transistor142.

The first semiconductor portion56functions as a channel region of the access transistor142. The access transistor142functions as a full depletion type or partial depletion type SOI transistor. The shield plates62and63are connected to a predetermined potential, and function as an isolation for electrically isolating the access transistor142.

In DRAM, the source and drain of an access transistor are interchanged between data writing and reading operations, and thus a pair of source and drain regions of a transistor is herein described as a source/drain region.

Next, a gate insulating film74and a gate electrode76are formed inside the trench71. The gate insulating film74contains, for example, silicon dioxide. The gate electrode76contains a conductive material, for example, titanium nitride. In the longitudinal sectional view ofFIG.16B, the gate electrode76is surrounded by the gate insulating film74. The gate insulating film74and the gate electrode76are formed by forming silicon dioxide and titanium nitride in the trench71, for example, by the CVD method, performing etch back by anisotropic dry etching, and then filling a recess formed on the gate electrode76by etching back with silicon dioxide. In this way, the gate electrode76is formed so as to face and contact, via the gate insulating film74, the side surface of the first semiconductor portion56which is a channel region.

In the same process steps as the formation of the trenches71and the gate electrodes76, trenches78aand pull-out-electrodes78are formed. The pull-out-electrodes78are formed of the same material as the gate electrodes76. The same insulating film as the gate insulating film74formed in the trench71is also formed on the side surface of the trench78a.However, since the insulating film is integrated with the first insulating film60, it is omitted fromFIG.16Band the like. The pull-out-electrodes78are formed by forming silicon dioxide and titanium nitride in the trenches78a,for example, by the CVD method and performing etch back by anisotropic dry etching in the same process steps as the formation of the gate electrodes76.

Here, etch back is performed in a state where a patterned resist (not shown) is formed on the pull-out-electrodes78. The resist is patterned by the known lithography technique. Additional etch back may be performed after removing the resist. In this way, the upper surfaces of the pull-out-electrodes78are adjusted to be higher than the upper surfaces of the gate electrodes76. Further, by this etch back, the height from the top surface of the first support substrate69to the top surfaces of the first doped layers70and the height from the top surface of the first support substrate69to the top surfaces of the pull-out-electrodes78are adjusted to be substantially equal to each other inFIG.16B.

Further, recesses are formed above the gate electrodes76by this etch back. Thereafter, silicon dioxide is filled in the recesses formed above the gate electrodes76. A structure in which the upper portions of the gate electrodes76are covered with the insulating film and the top surfaces of the pull-out-electrodes78are exposed is formed through the above steps. The structure shown inFIGS.16A and16Bis formed through the above steps.

Next, as shown inFIGS.17A and17B, a plurality of bit-lines80extending in the X-direction are formed. The bit-lines80contain a conductive material, for example, any one of tungsten silicide (WSi), tungsten nitride (WN), and tungsten (W). The bit-lines80are in contact with the first doped layers70and the pull-out-electrodes78, and are electrically connected to the first doped layers70and the pull-out-electrodes78. The bit-lines80are formed, for example, by performing the known lithography technique and the anisotropic dry etching technique on a conductive film formed by CVD.

Next, the steps of forming a structure shown inFIGS.18A and18Bwill be described. An on-bit-line insulating film84is formed on the bit-line80. The on-bit-line insulating film84contains an insulating material, for example, silicon nitride. The on-bit-line insulating film84is formed, for example, by CVD. A structure formed through the above steps, that is, a structure including the first support substrate69, the third insulating film68, the first insulating portions58, the first semiconductor portions56, the first doped layers70, the second doped layers72, and the third doped layers73, the gate insulating films74, the gate electrodes76, the pull-out-electrodes78, the bit-lines80, and the on-bit-line insulating films84is called a memory cell portion E.

Next, the memory cell portion E is rotated such that the X-axis is rotated around the Y-axis by 180 degrees. Next, a peripheral circuit portion F including a second semiconductor substrate136, peripheral circuit transistors138, wirings139, and the like is prepared. In the peripheral circuit portion F, the peripheral circuit transistors138, the wirings139and the like are formed on the second semiconductor substrate136in advance. A heat treatment for activation of impurities doped in the source/drain of each of the peripheral circuit transistors138is performed before bonding using the wafer bonding technique. The memory cell portion E and the peripheral circuit portion F are bonded to each other by the wafer bonding technique. In the wafer bonding technique, for example, a fusion bonding method can be used. The memory cell portion E and the peripheral circuit portion F are bonded to each other at a bonding surface H3. Through the above steps, the structure shown inFIGS.18A and18Bis formed.

Next, as shown inFIGS.19A and19B, the first support substrate69and the third insulating film68are removed. The first support substrate69and the third insulating film68can be removed, for example, by CMP, etching or the like. The first support substrate69and the third insulating film68are removed, so that the surface of the first insulating film60and the surfaces of the first insulating portions58are exposed. The memory cell portion E has a structure in which the first support substrate69and the third insulating film68are removed.

Next, the first insulating portions58are selectively removed. The first insulating portions58are selectively removed by etching using, for example, a hot phosphoric acid solution. Recesses are formed at places where the first insulating portions58have been removed, so that the top surfaces of the second doped layers72are exposed.

Next, by performing a known lithography method and anisotropic dry etching, trenches90areaching the surfaces of the pull-out-electrodes78from the surface of the first insulating film60are formed in the peripheral circuit region N. The trenches90aare formed by performing the known lithography method and the anisotropic dry etching. Next, contact holes93reaching the wirings139of the peripheral circuit section F are

formed. The contact holes93are formed by performing the known lithography method and the anisotropic dry etching. The order of forming the trenches90aand the contact holes93can be reversed. Next, the recesses formed by removing the first insulating portions58, the contact holes93and the trenches90aare filled with a conductive material, thereby forming conductive portions148, contact electrodes92, and pull-out-electrodes90. The filling of the conductive material is performed by forming a conductive material film, for example, by CVD, and performing anisotropic dry etching to etch back until the top surface of the first insulating film60is exposed. The conductive portions148, the contact electrodes92, and the pull-out-electrodes90contain a conductive material, for example, tungsten. The conductive portions148, the contact electrodes92and the pull-out-electrodes90are formed, for example, by CVD. A plane including the top surfaces of the first insulating film60, the conductive portions148, and the pull-out-electrodes90is formed.

An example in which the pull-out-electrodes90and the contact electrodes92are formed by using a so-called dual damascene technique is herein shown, but they may be formed by using a single damascene technique. In this way, the bit-lines80are electrically connected to the pull-out-electrodes78, the pull-out-electrodes90, the contact electrodes92, and the wirings139. Through the above steps, the structure shown inFIGS.19A and19Bis formed.

Next, as shown inFIGS.20A and20B, a capacitor portion G in which a storage capacitor150is formed in advance and the memory cell portion E are bonded to each other at a bonding surface H4by the wafer bonding technique. In the wafer bonding technique, for example, a fusion bonding method can be used. The top surface of the memory cell portion E and the bottom surface of the capacitor portion G are in contact with each other at the bonding surface H4. The capacitor portion G includes the storage capacitor150. The storage capacitor150includes first electrodes151, capacitive insulating films152, second electrodes154aand a third electrode154b.

The capacitive insulating film152contains, for example, a high-k film having a high relative dielectric constant, and contains, for example, metal oxide such as hafnium oxide (HfO2), zirconium oxide (ZrO2), or aluminum oxide (Al2O3). The capacitive insulating films152are formed, for example, by CVD. The first electrodes151and the second electrodes154acontain a conductive material, for example, titanium nitride (TiN). The first electrodes151and the second electrodes154aare formed, for example, by CVD. The capacitive insulating film152is sandwiched between the first electrode151and the second electrode154a.The capacitive insulating film152, the first electrode151, and the second electrode154afunction as a capacitor, and can store and release charges. The first electrode151is in contact with the conductive portion148. The second electrode154ais connected to a plate electrode (not shown). The third electrode154bcovers the second electrodes154a.The third electrode154bcontains a conductive material, for example, tungsten. The third electrode154bis formed, for example, by CVD, and patterned using the known lithography technique and the anisotropic dry etching technique. The storage capacitor150and the third electrode154bthat covers the storage capacitor150are covered by a fifth insulating film94.

Through the above steps, a memory cell array including the bit-lines80, the gate electrodes76, the access transistors142, and the storage capacitors150is formed. The access transistors142are provided in the active regions32and the first semiconductor portions56described above.

FIG.21shows an equivalent circuit of the memory cell array of the semiconductor devices according to the first and second embodiments. A plurality of memory cells145are arranged in a matrix form while the memory cells145are connected to respective intersections between pluralities of word-lines40and bit-lines80which are arranged orthogonally. One memory cell145includes a pair of the access transistor142and the storage capacitor150.

The access transistor142includes, for example, a MOSFET. The gate electrode of the access transistor142functions as a word-line40of the DRAM. The word-line40functions as a control line for controlling selection of corresponding memory cells. One of the source/drain of the access transistor142is connected to the bit-line80, and the other is connected to the storage capacitor150. The storage capacitor150includes a capacitor, and data is stored by accumulating charges in the capacitor.

When writing data into the memory cell145, a potential for setting the access transistor142to ON is applied to the word-line40, and a low potential or a high potential corresponding to write data “0” or “1” is applied to the bit-line80. When reading data from the memory cell145, a potential for setting the access transistor142to ON is applied to the word-line40. As a result, a potential drawn from the storage capacitor150to the bit-line80is sensed by a sense amplifier connected to the bit-line80, thereby determining the data.

Through the above steps, it is possible to achieve a structure in which the access transistor142and the storage capacitor150are vertically stacked in the Z direction. By implementing such an arrangement as described above, the area occupied by the memory cells on the X-Y plane can be reduced, so that a highly integrated semiconductor device can be achieved.

As described above, the semiconductor devices according to the embodiments have been described by illustrating DRAM, but these are examples and there is no intention to limit the semiconductor device to DRAM. With respect to the semiconductor devices, the embodiments are applicable to memory devices other than DRAM, for example, a static random access memory (SRAM), a flash memory, an erasable programmable read only memory (EPROM), a magnetoresistive random access memory (MRAM), a phase-change memory and the like. Further, with respect to the semiconductor devices according to the above embodiments, the embodiments are applicable to devices other than memories, for example, a microprocessor, a logic IC such as an application specific integrated circuit (ASIC), and the like.

Although various embodiments have been disclosed in the context of certain preferred embodiments and examples, it will be understood by those skilled in the art that the scope of the present disclosure extends beyond the specifically disclosed embodiments to other alternative embodiments and/or uses of the embodiments and obvious modifications and equivalents thereof. In addition, other modifications which are within the scope of this disclosure will be readily apparent to those of skill in the art based on this disclosure. It is also contemplated that various combination or sub-combination of the specific features and aspects of the embodiments may be made and still fall within the scope of the disclosure. It should be understood that various features and aspects of the disclosed embodiments can be combined with or substituted for one another in order to form varying modes of the disclosed embodiments. Thus, it is intended that the scope of at least some of the present disclosure should not be limited by the particular disclosed embodiments described above.