Electronic device with an output voltage booster mechanism

An electronic device includes: a clock booster configured to generate a boosted intermediate voltage greater than a source voltage, wherein the clock booster includes: a controller capacitor configured to store energy for providing a gate signal, wherein the gate signal is for controlling charging operations to generate the boosted intermediate voltage based on the source voltage, and a booster capacitor configured to store energy according to the gate signal for providing the boosted intermediate voltage, wherein the booster capacitor has greater capacitance level than the controller capacitor; and a secondary booster operatively coupled to the clock booster, the secondary booster configured to generate an output voltage based on the boosted intermediate voltage, wherein the output voltage is greater than both the source voltage and the boosted intermediate voltage.

This application contains subject matter related to a concurrently filed U.S. Patent Application by Michele Piccardi titled “ELECTRONIC DEVICE WITH A CHARGE RECYCLING MECHANISM.” The related application is assigned to Micron Technology, Inc., and is identified by Ser. No. 15/849,098. The subject matter thereof is incorporated herein by reference thereto.

This application contains subject matter related to a concurrently filed U.S. Patent Application by Michele Piccardi titled “ELECTRONIC DEVICE WITH A CHARGING MECHANISM.” The related application is assigned to Micron Technology, Inc., and is identified by Ser. No. 15/849,137. The subject matter thereof is incorporated herein by reference thereto.

TECHNICAL FIELD

The disclosed embodiments relate to electronic devices, and, in particular, to semiconductor devices with an output voltage booster mechanism.

BACKGROUND

Electronic devices, such as semiconductor devices, memory chips, microprocessor chips, and imager chips, can include a charge pump (e.g., a DC to DC converter that functions as a power source) to create a voltage that is different (e.g., higher or lower) than the available source voltage (e.g., ‘Vdd’). Charge pumps can include components (e.g., diodes, switches, comparators, capacitors, resistors, or a combination thereof) that are organized to provide an output voltage that is boosted or reduced from an incoming source voltage.

Some charge pumps can include the components arranged in units or stages (e.g., such that the connections between or relative arrangements of the units can be reconfigured to adjust one or more capabilities of the charge pump).FIG. 1A, illustrates a single stage of a charge pump in an electronic device101. In a pre-charge phase, an energy storage structure (e.g., one or more capacitors) in the single stage can be charged using an incoming voltage (e.g., ‘Vin’). As illustrated inFIG. 1B, the charged storage structure can be reconfigured (e.g., using one or more relays or switches) from a parallel connection with the voltage supply for the pre-charge phase to a series connection with the voltage supply for a boost phase. Accordingly, a resulting output (e.g., ‘Vout’) can be higher (e.g., ‘2Vin’) than the incoming voltage level (e.g. ‘Vin’).

With ‘N’ number of stages connected in series, the charge pump can produce a maximum voltage (‘Vmax’) that is further increased or boosted above the voltage level of the supply. The maximum voltage and the corresponding resistance value can be represented as:
Vmax=Vdd+N·Vdd=(N+1)·VddEquation (1).

Rout=N(fclk·Cp).Equation⁢⁢(2)
For example, the maximum voltage using ‘N’ stages can be ‘(N+1)’ times greater than the source voltage level of ‘Vdd’. Also for example, the corresponding resistance value for the charge pump having ‘N’ stages in series can correspond to a clock frequency (e.g., ‘fclk’) and a capacitance level or value (e.g., ‘Cp’) corresponding to the capacitor used in the pump stages.

The output voltage can be used to drive a load as illustrated inFIG. 1C. The boosted output can be connected to the electrical load. The load can draw a current (e.g., as represented ‘Iload’) and/or drive a load capacitance (e.g., as represented by a capacitance ‘Cload’). As such, when the load is connected to the charge pump, the output voltage (e.g., ‘Vout’) can drop according to the pump capability. Accordingly, multiple units or stages can be connected in series or in parallel to provide and/or maintain a targeted level of voltage, current, power, etc. to the connected load.

FIG. 2A-Care block diagrams of a charging stage of the charging mechanism.FIG. 2Ais a block diagram of a portion of a charging stage202(e.g., a voltage doubler) of the charging mechanism101. The charging stage202can include an input switch221, an output switch222, a first clock switch223, a second clock switch224, a charging capacitor225, or a combination thereof. The components of the charging stage202can operate according to a control signal226(e.g., 2 phase clock signal) having a first phase227(e.g., falling edge and/or a low magnitude portion of the control signal226, such as a lower half or a negative duty-cycle of the signal) and a second phase228(e.g., rising edge and/or a high magnitude portion of the control signal226, such as a higher half or a positive duty-cycle of the signal).

The charging stage202can operate according to the control signal226to charge the charging capacitor225and provide an output voltage through the output switch222. For example, two switches (e.g., the input switch221and the second clock switch224) can close at the first phase227(e.g., illustrated as ‘1’) while the other two switches (e.g., the output switch222and the first clock switch223) can be open (e.g., for charging the charging capacitor225). At the second phase228(e.g., illustrated ‘2’), the switches can be in an opposite state (e.g., the input switch221and the second clock switch224can be open and the output switch222and the first clock switch223can be closed).

FIG. 2Bis a block diagram of a portion of a charging stage203(e.g., a complementary doubler). The charging stage203can include the charging stage202(e.g., the voltage doubler illustrated inFIG. 2A) and a complementary stage204(e.g., a circuit complementary to the circuit202). The complementary stage204can include identical components as the circuit202, such as an input switch231, an output switch232, a first clock switch233, a second clock switch234, a charging capacitor235, or a combination thereof.

The complementary stage204can operate at opposite phase or polarity than the circuit202. For example, when the input switch221and the second clock switch224of the circuit202close at the first phase227, the corresponding portions of the complementary stage204(e.g., the input switch231and the second clock switch234) can be open. When the output switch222and the first clock switch223of the circuit202close at the second phase228, the corresponding portions of the complementary stage204(e.g., the output switch232and the first clock switch233) can be open.

FIG. 2Cis a block diagram of a portion of a charging stage205(e.g., a clock doubler, such as a 2-phase NMOS clock doubler). The charging stage205can use NMOS for input switch (e.g., the input switch221and/or the input switch231). For illustrative purposes, the output switches (e.g., the output switch222and/or the output switch232) are not shown. However, it is understood that the charging stage205can include output switches (e.g., NMOS or PMOS transistors corresponding to the output switch222and/or the output switch232). The clock switches can be abstracted or replaced by complementary clock signals (e.g., represented as ‘CLK’ and ‘!CLK’).

The portion of the charging stage202can include a first switch262(e.g., a first transistor, such as an NMOS transistor), a second switch264(e.g., a second transistor, such as an NMOS transistor), a first energy storage structure272(e.g., a first capacitor), a second energy storage structure274(e.g., a second capacitor), etc. For example, a portion (e.g., drain) of the first and second switches can be connected to the input voltage (e.g., ‘Vdd’). A different or opposing portion (e.g., source) of the first switch can be connected to the first energy storage structure and an emitter or source portion of the second switch can be connected to the second energy storage structure. A control portion (e.g., gate) of the first switch can also be connected to the emitter or source portion of the second switch and the second energy storage structure, and a gate or base portion of the second switch can be connected to the emitter or source portion of the first switch and the first energy storage structure. The first energy storage structure can further be connect to a clock signal (e.g., ‘CLK’) and the second energy storage structure can further be connected to an opposite or a negated form of the clock signal (e.g., ‘!CLK’). The two switches can function complementary to each other based on the opposing clock and negated clock signals and produce an output voltage (e.g., ‘Vout’) greater (e.g., by a factor of two) than the input voltage (e.g., ‘Vdd’).

The desired condition for the charging stage (e.g., the charging stage202,203, and/or205) is to achieve the required maximum voltage (‘Vmax’) based on having the pre-charge voltage (‘Vprecharge’) reach the supply voltage (‘Vdd’) in half of a clock cycle (‘0.5TCLK’) when the gate voltage (‘Vg’) is twice the supply voltage (‘2Vdd’). Ideally, the top plate/node of the charging capacitor should reach the supply voltage (e.g., Vprecharge=Vdd) for the first phase227. In the second phase228, the bottom plate/node can change from zero volt to the supply voltage to cause the tope plate to reach twice the supply voltage (e.g., 2Vdd=Vmax).

However, as illustrated inFIG. 2C, the clock doubler (e.g., 2-phase NMOS doubler) can include inefficiencies and losses that hinder the desired condition. For example, as illustrated by a dotted line (e.g., ‘⋅⋅⋅’), the clock doubler can be affected by a loading loss associated with supplying energy (e.g., such as when an output current, such as ‘Iout’, flows) to a connected device or unit (e.g., a further booster). As the current sinks, a gate voltage (e.g., ‘Vg’) also reduces (e.g., below ‘2Vdd’). Also for example, as illustrated by a dotted-dashed line (e.g., ‘-⋅⋅-⋅⋅’), the clock doubler can be affected by a semiconductor processing loss (e.g., based on voltage/current relationship of the physical implementation of the input switches). Also for example, as illustrated by a dashed line (e.g., ‘---’), the clock doubler can be affected by physical layout of the circuits and/or parasitic resistance from the connections.

For illustrative purposes, the various losses/loads are shown on one side of the complementary doubler inFIG. 2. However, it is understood that the various losses/loads can impact both/either side of the complementary doubler.

FIG. 3is a graphical representation of a relationship between a pre-charge current (e.g., current flowing across the input switch during the phase in which such switch is active, such as a precharge current shown as ‘Iprecharge’) and a potential energy loss for the charging mechanism (e.g., a reduction in magnitude of the voltage at which the top plate of the capacitor must be precharged during the phase in which the input switches are active, where the reduction can translate in energy loss for the charging mechanism).FIG. 3illustrates the loading loss (e.g., represented by a dotted line ‘⋅⋅⋅’), the processing loss (e.g., represented by a dotted-dashed line ‘-⋅⋅-⋅⋅’), and the loss from parasitic resistance and/or the physical layout (e.g., represented by a dashed line ‘---’) in relationship to the pre-charge current (‘Iprecharge’). For example, assuming switches are implemented with NMOS transistor, the losses can be represented based on the following equations:

A term β can represent a function of carrier mobility, oxide capacitance and devices sizes, while R is symbolically representing any parasitic resistor of the connections in the physical implementation of the clock doubler. As such, the overall loss can be characterized as:
Vprecharge=Vg−LOADING loss−PROCESS loss−LAYOUT loss.   Equation (6).

The voltage loss increases as the precharge current increases, which is the case when either the pump capacitors increase in size or the clock frequency increases to deliver a corresponding reduction in charge pump equivalent resistance. Accordingly, the voltage loss can cause a cascading impact on the required output voltage. Traditional method of compensating for the voltage loss has been to increase the number of stages.

DETAILED DESCRIPTION

The technology disclosed herein relates to electronic devices (e.g., semiconductor-level devices, sets of analog circuitry components, etc.), systems with electronic devices, and related methods for operating electronic devices in association with charge pumps and/or voltage booster mechanism (e.g., clock doubler) therein. The electronic devices can include a clock doubler (e.g., a 2-phase NMOS clock doubler) in each stage, and each clock doubler can include a controller portion and a separate booster portion (e.g., such as for a master-slave configuration). The controller portion (e.g., ‘master’ circuitry having a comparatively smaller capacitor) can drive or signal the booster portion (e.g., ‘slave’ circuitry having a comparatively larger capacitor) to produce the output voltage. The separation of the two portions with different size capacitors can reduce the various losses associated with the clock doubler, and further provide increased efficiency based on reducing the number of stages that are necessary to meet the target output voltage.

FIG. 4is a block diagram of an electronic device400(e.g., a multi-stage charge pump) including an output booster mechanism in accordance with an embodiment of the present technology. The electronic device400(e.g., a semiconductor device, an integrated circuit, a wafer or silicon level device, a set of digital and/or analog circuitry, etc.) can include a charge pump (e.g., a DC to DC converter, including one or more capacitors to store energy, that functions as a power source using various different internal configurations, arrangements, or electrical connections to provide an output voltage (“Vout”)). The charge pump can include multiple charging stages402(e.g., units of circuits, devices, components, etc. configured to produce a voltage greater than the input) connected in series.

Each of the charging stages402(e.g., double boosted charge pump circuits) can include a clock booster404(e.g., an output booster, such as a clock doubler), a secondary booster406(e.g., a Favrat booster), and a switching module408(e.g., a system or a set of switches and electrical connections). The clock booster404can be electrically coupled to the secondary booster406through the switching module408. For example, a boosted intermediate voltage410(e.g., an intermediate voltage, such as ‘2Vdd’, that is greater than and/or boosted from a source input voltage, such as ‘Vdd’,) from the clock booster404can be routed through the switching module408and provided as an input at the secondary booster406. The secondary booster406can use the boosted intermediate voltage410from the clock booster404to further increase a previous stage input voltage412(e.g., ‘Vdd’ for the first stage or a stage output414from a preceding secondary booster for subsequent stages). The stage output voltage414resulting from boosting the stage input voltage can be provided as an input voltage to the subsequent stage (e.g., as the stage input to subsequent instance of the secondary booster or as an output to the load).

In some embodiments, the switching module408can include multiple switching paths including one or more switches (e.g., NMOS transistors), one or more complementary switches (e.g., PMOS transistors), or a combination thereof. For example, the switching module408can include a first PMOS transistor422connected to the clock booster404on one end and a first NMOS transistor424, the secondary booster406, or a combination thereof on an opposing end. The switching module408can further include a second PMOS transistor426connected to the clock booster404on one end and a second NMOS transistor428, the secondary booster406, or a combination thereof on an opposing end.

The charging stages402including the clock booster404and the switching module408(e.g., for providing a voltage greater than the input voltage, such as ‘2Vdd’) with the secondary booster406provides increased charging efficiency. In comparison to the traditional switch pumps (e.g., as illustrated inFIGS. 1A-1C), the charge pump illustrated inFIG. 4can reduce the number of stages (e.g., by a factor of 2) necessary to produce the same target voltage and the corresponding resistance. For example, in contrast to Equations (1) and (2), the maximum voltage and the corresponding resistance value of the electronic device400can be represented as:
Vmax=Vdd+N/2·2VddEquation (8).

FIG. 5is an example circuit diagram of a clock booster502(e.g., 2-phase NMOS clock doubler) in accordance with an embodiment of the present technology.FIG. 5can illustrate a detailed example of the clock booster404inFIG. 4. The clock booster502can include a controller or a master portion504(“master-controller504”) and voltage booster or slave portions (e.g., first slave-booster506and second slave-booster508). The master-controller504can be configured to control the slave-booster portions according to phase or timing associated with the clock signal (e.g., for controlling the gate voltage ‘Vg’ according to the clock signal ‘CLK’ and ‘!CLK’). The slave-booster portions can be configured to produce an output voltage (‘Vprecharge’) greater than or boosted from the input voltage ‘Vdd’.

To control the slave-booster, the master-controller504can include control switches (e.g., a set of NMOS transistors) configured to control charging operations of the clock booster502(e.g., the slave-booster portions). For example, the control switches can include a first control switch512and a second control switch514. The first control switch512and the second control switch514can be connected to the input voltage at one end (e.g., at the drain portions). The control switches can further be connected to each other, such as by having an opposite end (e.g., the source portion) of the first control switch512connected to a control portion (e.g., the gate portion) of the second control switch514. Similarly, the opposite end or the source on the second control switch514can be connect to a control portion or the gate on the first control switch512.

The master-controller504can further include energy storage structures (e.g., a set of capacitors) that are directly connected to the opposite portions and the gate portions of control switches. For example, a first control capacitor516can be connected to the source of the first control switch512and the gate of the second control switch514on one terminal, and further connected to a clock signal (e.g., “CLK”) at an opposing terminal. Also, a second control capacitor518can be connected to the source of the second control switch514and the gate of the first control switch516on one terminal, and further connected to an opposite or a negated form of the clock signal (e.g., “!CLK”) at an opposing terminal.

The switches and the capacitors of the master-controller504can operate similar (e.g., complementary operations of the switches used to boost the output voltage) to other designs of charging stages or clock doublers, such as the charging stage202ofFIG. 2. However, the first control capacitor516and the second capacitor518can have capacitance levels that are smaller (e.g., by a factor of 2 or greater, such as 10, 20, 40, 60, or any number greater than 60) than that of capacitors used in the other designs. Using the master-controller504and the slave-boosters, the clock booster502can separate the phase or timing based control (e.g., function of the master-controller504) and the voltage boosting function (e.g., function of the slave-boosters) into separate portions or circuits. As such, the capacitance levels of the control capacitors can be drastically reduced when compared to similarly-located capacitors in the charging stage ofFIG. 2(e.g., since, unlike in those designs, they are not used to drive the output voltage and/or current).

To produce the boosted intermediate voltage410, the master-controller504can control the charging operations of the slave boosters (e.g., the first slave-booster506and the second slave-booster508). The slave boosters can each include one or more controllers (e.g. booster switches522) connected to the master-controller504. For example, the gates of the booster switches522in the first slave-booster506can be connected to the gate of the first control switch512, the source of the second control switch514, and the second controller capacitor518. Also for example, the gates of the booster switches in the second slave booster508can be connected to the gate of the second control switch514, the source of the first control switch512, and the first controller capacitor516. Based on the connection to the master-controller504, the booster switches522can operate similar to the control switches, such as by having the booster switches522of the second slave-booster508turning on or off according to the gate signals.

The booster switches522can be directly connected to the input source (e.g., at the drains) and booster capacitors524at opposing terminals (e.g., at the sources). The booster capacitors524can be further connected to the clock signal (e.g., for the booster capacitors524in the first slave booster506) or the opposite or the negated form of the clock signal (e.g., for the booster capacitors524in the second slave booster508) at a terminal opposite the input source. The booster capacitors524can be configured to drive the boosted intermediate voltage410(e.g., voltage and/or current) for the secondary booster406ofFIG. 4(e.g., illustrated by dotted lines inFIG. 5), and as such, the booster capacitors524can have capacitance levels that are much greater (e.g., by a factor of 10 or greater) than capacitance levels of the first control capacitor516and/or the second control capacitor518.

The slave-boosters can include multiple booster switches, multiple booster capacitors, or a combination thereof. In some embodiments, the slave boosters can include one booster switch one booster capacitor, such as illustrated for the first slave-booster506inFIG. 5. In some embodiments, the slave boosters can include multiple booster switches522connected to each of the booster capacitors524, such as illustrated for the second slave-booster508inFIG. 5. In some embodiments, the slave boosters can include multiple booster capacitors524and/or multiple circuit groupings each including a booster capacitor, where the multiple booster capacitors524are connected in parallel, such as illustrated for the second slave-booster508inFIG. 5.

For illustrative purposes, the first slave-booster506and the second slave-booster508are illustrated as having different number of circuit components. However, it is understood that the slave-boosters in the clock booster502can be similar to each other (e.g., number and/or arrangement of components).

The master-slave configuration for the clock booster502(e.g., including the master-controller504and one or more slave-boosters) provides increased efficiencies and reduced losses. The master-slave configuration can separate the load (e.g., the secondary booster406) from the controller capacitors (e.g., no direct connection), such that the load is driven by the booster capacitors524. Accordingly, unlike the LOADING loss described in Equation (3) andFIG. 2, the separation can allow the gate signal to remain unaffected by the loading, thereby reducing the loading loss.

Further, the master-slave configuration can reduce the PROCESS losses based on reducing the capacitance level associated with the gate signal. Based on removing the gate signal from directly driving the load, the control capacitors can process the control signal with reduced capacitance levels (e.g., by a factor of 2 or greater, such as 10, 20, 40, 60, or any number between 10-60, or any number greater than 60) in comparison to existing designs (e.g., capacitors illustrated inFIG. 2). As such, the current associated with the control capacitors and the gate signals can be reduced, which can further reduce the saturation loss.

Moreover, the master-slave configuration can reduce the LAYOUT loss (e.g., as illustrated inFIG. 2). Based on reducing the current associated with the gate signal as discussed above, the voltage drop caused by parasitic resistances in the master controller504reduces accordingly. Parasitic resistances can be further attenuated (e.g., for the slave-boosters) based on evenly or substantially uniformly distributing (e.g., based on physically arranging the components with regular or patterned spacing between the components, based on forming the components with similar size/capacity/dimension, etc.) the circuit components (e.g., the booster switches522and the booster capacitors524), such as along a silicon layer or wafer.

For illustrative purposes, the various losses (e.g., PROCESS, LAYOUT, and LOADING) are shown using dotted and/or dashed lines inFIG. 5. However, it is understood that the structures (e.g., resistors or current sinks) represented by the dotted and/or dashed lines can be absent from or not part of the clock booster502.

FIG. 6A-Cillustrate example input signals in accordance with an embodiment of the present technology.FIG. 6Aillustrates a signal input diagram600. The signal input diagram600can illustrate the input signals (e.g., clock signal, the negated signal, a derivative thereof, etc.) for the electronic device400ofFIG. 4or a portion therein (e.g., the clock booster502ofFIG. 5). For example, the master-controller504can use/receive a first clock signal601(e.g., the clock signal) and a second clock signal602(e.g., the negated signal). The first slave-booster506can use/receive a third clock signal603(e.g., the negated signal or a derivative thereof). The second slave-booster508can use/receive a fourth clock signal604(e.g., the clock signal or a derivative thereof). In some embodiments, the third clock signal603can be non-overlapped and negated form of the fourth clock signal604. In some embodiments, the third clock signal603and the fourth clock signal604can be separate or independent from the first clock signal601and the second clock signal602. In some embodiments, the first clock signal601can be same as or equal to the third clock signal603and/or the second clock signal602can be same as or equal to the fourth clock signal604.

FIG. 6Billustrates a signal timing diagram610. The signal timing diagram610can illustrate a relative timing between a clock signal612(e.g., the first clock signal601, the third clock signal603, or a combination thereof) and a negated signal614(e.g., the second clock signal602, the fourth clock signal604, or a combination thereof). The negated signal614can be a negated form of the clock signal612.

FIG. 6Cillustrates a further signal timing diagram620. The signal timing diagram610can illustrate a relative timing between a clock signal622(e.g., the first clock signal601, the third clock signal603, or a combination thereof) and a negated signal624(e.g., the second clock signal602, the fourth clock signal604, or a combination thereof). The negated signal624can be a negated and non-overlapped form of the clock signal622. The clock signal622and/or the negated signal624can have a duty cycle, a duration, a pulse width, a shape, etc. that is different (e.g., shorter or narrower) than the clock signal612and/or the negated signal614(e.g., in comparison to the signals illustrated inFIG. 6B). In some embodiments, the clock signal622and the negated signal624can have a duty cycle, a duration, a pulse width, a shape, etc. that is different from each other. In some embodiments, the clock signal622and the negated signal624can have a duty cycle that is different from 50%.

FIG. 7illustrates an example method700of manufacturing an electronic device in accordance with embodiments of the present technology. The method700can be for manufacturing the electronic device400ofFIG. 4or a portion therein, such as the clock booster502ofFIG. 5.

At block702, a master/controlling circuit can be provided for controlling charging operations to generate the boosted intermediate voltage410ofFIG. 4. The master/controlling circuit (e.g., the master-controller504ofFIG. 5) can be provided based on forming circuitry (e.g., such as based on forming the circuitry in one or more silicon wafers or layers) and/or assembling circuitry components. For example, at block704, controller switches (e.g., the first controller switch512ofFIG. 5, the second controller switch514ofFIG. 5, etc.) can be provided. Also for example, at block706, controller capacitors (e.g., the first controller capacitor516ofFIG. 5, the second controller capacitor518ofFIG. 5, etc.) can be provided. The controller switches and/or the controller capacitors can be arranged and/or connected as illustrated inFIG. 5and discussed above.

At block712, a slave/charging circuit can be provided for implementing the charging operations to generate the boosted intermediate voltage410. The slave/charging circuit (e.g., the first slave-booster506ofFIG. 5, the second slave-booster508ofFIG. 5, etc.) can be provided based on forming circuitry and/or assembling circuitry components. For example, at block714, booster switches (e.g., the booster switches522ofFIG. 5) can be provided. Also for example, at block716, controller capacitors (e.g., the booster capacitors524ofFIG. 5) can be provided. The booster switches and/or the booster capacitors can be arranged and/or connected as illustrated inFIG. 5and discussed above.

At block722, one or more stages or units of charge pumps (e.g., instances of the charge stage402ofFIG. 4) can be assembled. The charge stage402can be assembled based on forming circuitry and/or assembling circuitry components for generating the stage output voltage414based on further boosting the boosted intermediate voltage410. For example, at block724, switch modules (e.g., the switching module408ofFIG. 4) can be provided for routing the boosted intermediate voltage410to secondary boosters. Also for example, at block726, the secondary boosters (e.g., the secondary booster406ofFIG. 4, such as Favrat boosters) can be provided for generating the stage output voltage414based on using and/or further boosting the boosted intermediate voltage410. The switch modules and the secondary boosters can be arranged and/or connected asFIG. 4and discussed above.

At block732, the multiple charge pump units can be assembled or connected to generate a targeted voltage (e.g., ‘VMAX’). Multiple instances of the charge stages can be connected (e.g., based on forming at silicon level or at component assembly level) in a series connection, such as illustrated inFIG. 4and discussed above. The charge stages can be connected such that the stage output voltage414ofFIG. 4of one charge pump stage can be the previous stage input voltage412ofFIG. 4of the next charge pump stage in the sequential or serial connection. As such, the stage output voltage414can be amplified or boosted across each charge stage to generate the targeted voltage.

FIG. 8illustrates an example method800of operating an electronic system in accordance with embodiments of the present technology. The method800can be for operating the electronic device400ofFIG. 4or a portion therein, such as the clock booster502ofFIG. 5and/or the clock booster404ofFIG. 4.

At block802, the clock booster502can provide clock booster output. The clock booster404ofFIG. 4, the clock booster502ofFIG. 5, or a combination thereof can generate the clock booster output based on source input (e.g., ‘Vdd’), the clock signal, and the negated signal.

For example, at block804, the clock booster502can charge the control capacitors (e.g., the first controller capacitor516ofFIG. 5, the second controller capacitor518ofFIG. 5, etc.) based on the clock signal and/or the negated signal. At block806, the voltage level of the control capacitors can operate the switches (e.g., the booster capacitors524ofFIG. 5, the first controller capacitor516, the second controller capacitor518, or a combination thereof) that have their gates connected thereto. Based on operating the switches, at block808, the booster capacitors524ofFIG. 5can be charged using the source input and either the clock signal or the negated signal that is complementary to the signal connected to the control capacitor and driving the gate voltage. Further, the operation of the switches can further affect the charges on the control capacitors, such as by connecting the source input to a terminal opposite the clock signal or the negated signal. Accordingly, the clock booster502can generate the boosted intermediate voltage410(e.g., effectively doubling the source input) based on or from charging the booster capacitors524.

At block812, the switching module408ofFIG. 4can route (e.g., according to the clock signal, the negated signal, etc.) the output of the booster capacitors524(e.g., the boosted intermediate voltage410from a double boosted clock doubler) to the secondary booster406ofFIG. 4. For example, the switching module408can operate a set of switches (e.g., the first PMOS transistor422ofFIG. 4, the first NMOS transistor424ofFIG. 4, the second PMOS transistor426ofFIG. 4, the second NMOS transistor428ofFIG. 4, or a combination thereof) to provide the boosted intermediate voltage410as an input to the secondary booster406.

At block822, the secondary booster406can generate a charge stage output (e.g., the stage output voltage414ofFIG. 4) for the charge stage402. The secondary booster406(e.g., a Favrat booster) can generate the stage output voltage414based on the previous stage input voltage412ofFIG. 4(e.g., the stage output voltage414ofFIG. 4from a preceding instance of the charge stage or input source), the boosted intermediate voltage410, etc.

At block832, the charge pump (e.g., the electronic device400) can generate an accumulated output (e.g., ‘VMAX’). Through the series connection of the secondary boosters, the charge pump can aggregate and/or compound the voltage increase across the multiple charge stages to generate the accumulated output.

FIG. 9is a schematic view of a system that includes an electronic device in accordance with embodiments of the present technology. Any one of the semiconductor devices having the features described above with reference toFIGS. 1-8can be incorporated into any of a myriad of larger and/or more complex systems, a representative example of which is system990shown schematically inFIG. 9. The system990can include a processor992, a memory994(e.g., SRAM, DRAM, flash, and/or other memory devices), input/output devices996, and/or other subsystems or components998. The semiconductor assemblies, devices, and device packages described above with reference toFIGS. 1-8can be included in any of the elements shown inFIG. 9. The resulting system990can be configured to perform any of a wide variety of suitable computing, processing, storage, sensing, imaging, and/or other functions. Accordingly, representative examples of the system990include, without limitation, computers and/or other data processors, such as desktop computers, laptop computers, Internet appliances, hand-held devices (e.g., palm-top computers, wearable computers, cellular or mobile phones, personal digital assistants, music players, etc.), tablets, multi-processor systems, processor-based or programmable consumer electronics, network computers, and minicomputers. Additional representative examples of the system990include lights, cameras, vehicles, etc. With regard to these and other examples, the system990can be housed in a single unit or distributed over multiple interconnected units, e.g., through a communication network. The components of the system990can accordingly include local and/or remote memory storage devices and any of a wide variety of suitable computer-readable media.

From the foregoing, it will be appreciated that specific embodiments of the present technology have been described herein for purposes of illustration, but that various modifications may be made without deviating from the disclosure. In addition, certain aspects of the disclosure described in the context of particular embodiments may be combined or eliminated in other embodiments. Further, while advantages associated with certain embodiments have been described in the context of those embodiments, other embodiments may also exhibit such advantages. Not all embodiments need necessarily exhibit such advantages to fall within the scope of the present disclosure. Accordingly, the disclosure and associated technology can encompass other embodiments not expressly shown or described herein.