Neuron device and integrated circuit including neuron device

A neuron device may include an input unit, a synapse unit, and an output unit. The synapse unit can be connected with the input unit and may include one or more synapse modules. Each of the one or more synapse modules may include multiple synapse elements connected in series and may be configured to operate in a time division multiplexing mode. Each synapse element may have specific coefficient information. In each of the one or more synapse modules, one of the multiple synapse elements connected in series may be configured to apply coefficient information to one of the multiple input signals received by the input unit. The output unit may obtain a weighted sum of the multiple input signals and may generate an output signal based on the weighted sum.

TECHNICAL FIELD

The present disclosure relates to a neuron device and an integrated circuit including the same.

BACKGROUND

Recently, research on a system including a neuron device has continued. The system including a neuron device can implement a computer different from a conventional Von Neumann type computer and may have design flexibility and energy and space efficiency.

The system including a neuron device can process and learn data in a manner analogous to that of a biological brain. The neuron device is connected with other neuron devices through synapses of the neuron device and also receives data from the other neuron devices through the synapses. Also, the neuron device may store the received data. In order to configure a required system using the neuron device and/or the synapses of the neuron device, a number of neuron devices may be needed.

SUMMARY

In an example, a neuron device is generally described. One exemplary neuron device may include an input unit, a synapse unit, and an output unit. The input unit may be configured to receive multiple input signals. The synapse unit may be connected with the input unit and may include one or more synapse modules. Each of the one or more synapse modules of the synapse unit may include multiple synapse elements connected in series. Each of the synapse modules may be configured to operate in a time division multiplexing mode. Each of the multiple synapse elements may have specific coefficient information. According to the time division multiplexing mode, in each of the one or more synapse modules, one of the multiple synapse elements connected in series may be configured to apply coefficient information to one of the received multiple input signals. The output unit may obtain a weighted sum of the multiple input signals to which the coefficient information is applied and may generate an output signal based on the weighted sum. In an additional example, each synapse element of the synapse unit may include a floating gate metal oxide silicon field effect transistor (MOSFET).

In an additional example, the multiple input signals may be pulse signals. In another example, the multiple input signals may be analog signals. In yet another example, the multiple input signals may be digital signals.

Further, in an additional example, the input unit may be configured to receive an input signal in each time section according to the time division multiplexing mode. Each synapse element of the synapse unit may be configured to update the coefficient information in each time section according to the time division multiplexing mode. The output unit may be configured to generate an output signal in each time section according to the time division multiplexing mode.

In an additional example, the input unit may be configured to directly transmit an input signal to each synapse element. The input unit may be configured to transmit, according to the time division multiplexing mode, input signals to the other synapse elements than the synapse element applying the coefficient information, wherein the input signals to the other synapse elements is to operate the other synapse elements as closed switches.

In another example, the input unit may be configured to transmit an input signal to each synapse module. According to the time division multiplexing mode, in each of the one or more synapse modules, each of the synapse elements applying the coefficient information may receive a read signal that enables coefficient information to be read and apply the read coefficient information to an input signal transmitted to a corresponding synapse module. Meanwhile, in each of the one or more synapse modules, the other synapse elements than the synapse elements applying the coefficient information from among the multiple synapse elements connected in series may be configured to receive a pass signal to operate the other synapse elements as closed switches.

In an additional example, the output unit may be configured to generate an output signal when the weighted sum exceeds a threshold value. The coefficient information of each of the multiple synapse elements may have a positive value or a negative value.

In an additional example, the synapse elements connected in series may be configured to form a NAND flash structure.

In an example, an integrated circuit is generally described. The integrated circuit may include multiple neuron devices and a connection unit. Each of the multiple neuron devices may be configured as the above-described exemplary neuron device. The connection unit may be configured to enable interconnection among the multiple neuron devices. The connection unit is programmable. The connection unit may dynamically change the interconnection among the multiple neuron devices.

The above-described summary is for illustration purposes only and does not intend to limit in any ways. In addition to the illustrative embodiments, examples, and features described above, additional embodiments, examples, and features will become apparent by referring to the following detailed description and drawings.

MODE FOR CARRYING OUT THE INVENTION

In the following detailed description, reference is made to the accompanying drawings, which constitutes a part of the present disclosure. In the drawings, similar symbols typically identify similar components unless context dictates otherwise. The illustrative embodiments described in the detailed description, drawings, and claims are not meant to be limiting. Other embodiments may be used and other changes may be made, without departing from the spirit or scope of the subject matter presented herein. It will be readily understood that the aspects of the present disclosure, as generally described herein and illustrated in the drawings, may be arranged, substituted, combined, separated, and designed in a wide variety of different configurations, all of which are explicitly contemplated herein.

This disclosure is generally related, inter alia, to neuron devices and integrated circuits including multiple neuron devices.

Briefly stated, a neuron device may receive multiple input signals. The neuron device may include one or more synapse modules, and each of the synapse modules may include multiple synapse elements connected in series. In each of the one or more synapse modules, the multiple synapse elements connected in series may operate in a time division multiplexing mode. One of the multiple synapse elements connected in series may apply coefficient information to one of the input signals. The others of the multiple synapse elements connected in series may operate as a closed circuit.

In an example, each of the other synapse elements than the synapse element applying the coefficient information from among the multiple synapse elements connected in series may receive input signals to operate the other synapse elements as closed switches. In another example, each of the one or more synapse modules may receive one of the multiple input signals, and the synapse element applying the coefficient information may receive a read signal that enables coefficient information to be read and apply the coefficient information to the received input signal and the other synapse elements may receive a pass signal for a synapse element to operate as closed switches. The neuron device may obtain a weighted sum of the multiple input signals to which the coefficient information is applied and may generate an output signal based on the weighted sum.

FIG. 1is a diagram provided to explain signal transmission between neuron devices in an electronic device including the neuron devices in accordance with at least some exemplary embodiments of the present disclosure. An exemplary electronic device100may include multiple neuron devices110-1and110-2and120. In some examples, neuron device110-1may output a signal112-1. Neuron device110-2may output a signal112-2. In some examples, as illustrated inFIG. 1, signal112-2may have a time difference from the signal112-1of the neuron device110-1. In another example, neuron device120may receive signals112-1and112-2at the same time. As such, neuron device120may receive signal112-1from neuron device110-1and signal112-2from neuron device110-2.

As illustrated inFIG. 1, a graph130shows a change in internal potential and output of neutron device120when neuron device120receives signal112-1from neuron device110-1and signal112-2from neuron device110-2. As shown in graph130, during a time section130-1, neuron device120receives only signal112-1and the internal potential of neuron device120is increased. During a time section130-2, neuron device120receives all of signal112-1and signal112-2and the internal potential of neuron device120is rapidly increased as compared with time section130-1. During a time section130-3, neuron device120receives only signal112-2and the internal potential of neuron device120is slowly increased as compared with time section130-2. When the internal potential of neuron device120exceeds a specific value VThr, neuron device120generates an output signal during a time section130-4as shown in the output graph.

As such, neuron device120may receive signals from neuron devices110-1and110-2and generate an output signal based on the received signal. In a similar manner as described above, neuron devices110-1and110-2may also receive signals from one or more other neuron devices and output the signals112-1and112-2based on the received signals. AlthoughFIG. 1illustrates that neuron device120receives signals from two neuron devices110-1and110-2, neuron device120may receive signals from one neuron device or three or more neuron devices. Neuron devices110-1,110-2, and120may transmit, receive, and generate signals as described above and thus transfer information. AlthoughFIG. 1illustrates signals112-1and112-2as pulse signals, signals transmitted, received, and generated by the neuron devices may have various forms. For example, signals112-1and112-2may be analog signals and digital signals as well as pulse signals. If signals112-1and112-2are pulse signals, information may be expressed as pulse widths of the pulse signals. If signals112-1and112-2are analog signals, information may be expressed using magnitudes of voltage or currents of the analog signals. If signals112-1and112-2are digital signals, information may be expressed as one or more discrete values.

FIG. 2Ais an exemplary circuit diagram in which neuron devices such as neuron devices110-1,110-2, and120ofFIG. 1are implemented. A neuron device200is configured to receive multiple input signals such as spike_in[0], spike_in[1], spike_in[2], etc. Neuron device200may include a floating gate metal oxide silicon field effect transistor (FG MOSFET) as shown inFIG. 2A. DSL and SSL values may be associated with an effective operation of the FG MOSFET of the neuron device200. Gates of the FG MOSFETs are configured to receive input signals such as spike_in[0], spike_in[1], spike_in[2], etc., respectively. When the neuron device200receives an input signal, an internal potential Vmemof neuron device200is determined based on the received input signal. For example, when neuron device200receives the input signal spike_in[0], a charge is accumulated in a capacitor connected to a Vmemstage, and, thus, the internal potential Vmemmay be increased. As described above with reference toFIG. 1, when the internal potential Vmemof neuron device200exceeds a threshold value (e.g., Vth; not illustrated), neuron device200generates an output signal OUT. Meanwhile, when the output signal is generated by neuron device200, the output signal OUT is applied to a gate of the MOSFET connected to the Vmemstage, and, thus, the internal potential Vmemis initialized.

FIG. 2Bis a graph showing the relationship of input signals applied to the neuron device200ofFIG. 2A, internal potentials, and output signals. Neuron device200may receive an input signal spike_in[i] and an input signal spike_in[j]. For example, in an example illustrated inFIG. 2A, i may be 0 and j may be 1. When the input signal spike_in[i] is received as shown inFIG. 2B, the internal potential Vmemis increased but lower than the threshold value Vth, and, thus, the output OUT is not generated. After the input signal spike_in[i] is received and before the input signal spike_in[j] is received, the internal potential Vmemis not changed. When the input signal spike_in[j] is received, the internal potential Vmemis increased again. When the internal potential Vmemexceeds the threshold value Vth, the output signal OUT is generated and the generated output signal OUT is applied to the gate of the MOSFET connected to the Vmemstage. Thus, the internal potential Vmemis reset. Therefore, even if the input signal spike_in[j] is continuously received, the internal potential Vmemis not further increased.

FIG. 3is a block diagram illustrating an exemplary neuron device in accordance with at least some exemplary embodiments of the present disclosure. In some examples, a neuron device300may include an input unit310, a synapse unit320, and an output unit330. Input unit310may be configured to receive multiple input signals340-1to340-n.In some examples, the multiple input signals340-1to340-nreceived by input unit310may include various forms of signals. For example, the input signals340-1to340-nmay include pulse signals, analog signals, and digital signals. If the input signals340-1to340-nare pulse signals, information included in each input signal may be expressed as pulse widths of the pulse signals. If the input signals340-1to340-nare analog signals, information included in each input signal may be expressed using magnitudes of voltage or currents of the analog signals. If the input signals340-1to340-nare digital signals, information included in each input signal may be expressed as one or more discrete values.

In some embodiments, synapse unit320may be connected to input unit310and may include one or more synapse modules322-1to322-k.Each of one or more synapse modules322-1to322-kmay include multiple synapse elements connected in series. Each of the synapse elements may have specific coefficient information. In some examples, a synapse element may include an FG MOSFET. In such examples, the specific coefficient information may be determined based on a threshold voltage of the FG MOSFET in each synapse element, connection between synapse unit320and output unit330, and the like. For example, synapse module322-1and synapse module322-kmay include j synapse elements and 1 synapse elements, respectively, and the synapse elements of synapse module322-1may have coefficient information w11, w12, w13, . . . , w1j, respectively, and the synapse elements of synapse module322-kmay have coefficient information wk1, wk2, wk3, . . . , wk1, respectively. Herein, j and 1 are positive integers equal to or greater than 2.

In an example where a synapse element includes an FG MOSFET, synapse elements may be connected in series to form a NAND flash structure. As multiple FG MOSFETs are connected in series and form a NAND flash structure, when fabricating neuron device300with connecting synapse elements in series, the number of synapse elements included in a unit area can be increased.

In some embodiments, each of one or more synapse modules322-1to322-kmay be configured to operate in a time division multiplexing manner. The multiple synapse elements connected in series in each of one or more synapse modules322-1to322-kmay be configured to operate in the time division multiplexing mode. Each of the multiple synapse elements connected in series may be configured to operate in a different time section from each other. For example, synapse unit320may include synapse module322-1and synapse module322-k,and synapse module322-1may include a first synapse element and a second synapse element connected in series and synapse module322-kmay include a third synapse element and a fourth synapse element connected in series. In such example, during a first time section according to the time division multiplexing mode, input unit310may receive multiple input signals340-1to340-n.During the first time section, each of the first synapse element of synapse module322-1and the third synapse element of synapse module322-kmay be configured to apply specific coefficient information to one of multiple input signals340-1to340-nreceived by input unit310. Meanwhile, during the first time section, the second synapse element and the fourth synapse element may operate as closed switches.

During a second time section after the first time section, input unit310may receive new multiple input signals340-1′ to340-n′(not illustrated). The first synapse element and the third synapse element may operate as closed switches. Meanwhile, during the second time section, the second synapse element and the fourth synapse element may be configured to apply specific coefficient information to one of input signals340-1′ to340-n′received during the second time section.

In some examples, each of the first and third synapse elements may be configured to apply coefficient information to an input signal during the first time section, and then the first to fourth synapse elements may be configured to update coefficient information before the second time section. Similarly, each of the second and fourth synapse elements may receive input signals during the second time section, and then the first to fourth synapse elements may be configured to update coefficient information before a subsequent time section. The time division multiplexing mode will be described below in more detail with reference toFIG. 8andFIG. 10.

In some embodiments, output unit330may be connected to synapse unit320and configured to generate an output signal350. In some examples, output unit330may be configured to obtain a weighted sum of input signals to which coefficient information is applied by synapse unit320and generate an output signal based on the weighted sum. In some examples, output unit330may be configured to output an output signal when the weighted sum exceeds a predetermined threshold value. Even when input unit310receives an input signal and the synapse unit applies coefficient information to the received input signal, when a weighted sum obtained by the output unit330does not exceed the threshold value, the output unit330may not generate an output signal. In some examples, when the synapse unit320operates in the time division multiplexing mode, the output unit330may be configured to generate an output signal during each time section according to the time division multiplexing mode. In some examples, the weighted sum obtained by the output unit330may be reset in each time section. The output signal generated by output unit330may be an input signal of one or more other neuron devices or a synapse element in another stage.

FIG. 4is an exemplary circuit diagram of the neuron device ofFIG. 3. An input unit (not illustrated) of neuron device300may be configured to receive multiple input signals spike_in[0,0], spike_in[0,1], spike_in[0,2], spike_in[1,0], spike_in[1,1], spike_in[1,2], etc. and transfer the multiple input signals to gates of multiple FG MOSFETs, respectively. As shown inFIG. 4, a synapse unit of neuron device300may include one or more synapse modules410,420,430, etc. and each of synapse modules410,420,430, etc. may include multiple FG MOSFETs connected in series. Each FG MOSFET may correspond to a synapse element. DSL and SSL values may be associated with an effective operation of the FG MOSFET of the neuron device300. Synapse module410may be configured to receive spike_in[0,0] and spike_in[1,0]. Synapse module420may be configured to receive spike_in[0,1] and spike_in[1,1]. Synapse module430may be configured to receive spike_in[0,2] and spike_in[1,2]. When neuron device300receives an input signal, an internal potential Vmemof neuron device300is determined based on the received input signal. For example, when neuron device300receives the input signal spike_in[0,0], a charge is accumulated in a capacitor connected to a Vmemstage, and, thus, the internal potential Vmemmay be increased. In some examples, when the internal potential Vmemexceeds a predetermined threshold value, the neuron device300may generate an output signal OUT.

In some embodiments, each of synapse modules410,420, and430of neuron device300may be configured to operate in the time division multiplexing mode. In some examples, during a first time section in the time division multiplexing mode, an FG MOSFET in a first stage of synapse module410may be configured to receive spike_in[0,0], and the other FG MOSFETs in synapse module410than the FG MOSFET receiving spike_in[0,0] may receive input signals to operate as closed switches. Similarly, during the first time section, an FG MOSFET in a first stage of synapse module420may be configured to receive spike_in[0,1] and an FG MOSFET in a first stage of synapse module430may be configured to receive spike_in[0,2]. The other FG MOSFETs in synapse modules420and430than the FG MOSFETs in the first stages of synapse modules420and430may receive input signals to operate as closed switches. When spike_in[0,0], spike_in[0,1], and spike_in[0,2] are received during the first time section, specific coefficient information of the respective FG MOSFETs may be applied thereto, and, thus, charges corresponding thereto may be accumulated in capacitors connected to the Vmemstage. When a voltage of the internal potential Vmemexceeds the threshold value, an output unit of neuron device300may generate the output signal OUT. During a second time section after the first time section, an FG MOSFET in a second stage of the synapse module410may receive spike_in[1,0], an FG MOSFET in a second stage of the synapse module420may receive spike_in[1,1], and an FG MOSFET in a second stage of the synapse module430may receive spike_in[1,2]. During the second time section, the FG MOSFETs in the first stages of synapse modules410,420, and430may receive input signals to operate as closed switches. During the second time section, when spike_in[1,0], spike_in[1,1], and spike_in[1,2] are received, specific coefficient information of the respective FG MOSFETs may be applied thereto, and, thus, charges corresponding thereto may be accumulated in capacitors connected to the Vmemstage. When a voltage of the internal potential Vmemexceeds the threshold voltage, the output unit of neuron device300may generate the output signal OUT.

FIG. 5is another exemplary circuit diagram of the neuron device ofFIG. 3. The neuron device illustrated inFIG. 5has the same circuit diagram as neuron device300illustrated inFIG. 4except the layout of lines for input signals. Therefore, an explanation of the same parts as illustrated inFIG. 4will be omitted. Referring toFIG. 5, a synapse unit of neuron device300includes one or more synapse modules510,520,530, etc. An input unit (not illustrated) of neuron device300may be configured to receive multiple input signals spike_in[n,0], spike_in[n,1], spike_in[n,2], etc. and transmit the input signals to the respective synapse modules510,520,530, etc. As illustrated inFIG. 5, the input signals spike_in[n,0], spike_in[n,1], spike_in[n,2], etc. may be transmitted to gates of MOSFETs included in synapse modules510,520,530, etc., respectively. Herein, n includes 0 and positive integers. Two MOSFETs in each of the synapse modules illustrated inFIG. 5may be arranged to receive the same input signal.

Further, each of multiple FG MOSFETs included in each of multiple modules510,520,530, etc. may receive a signal indicating whether or not to read. For example, as illustrated inFIG. 5, FG MOSFETs in first stages of multiple modules510,520,530, etc., respectively, may receive a signal bias[0], and FG MOSFETs in second stages of multiple modules510,520,530, etc., respectively, may receive a signal bias[1]. Due to this layout of lines, lines may be simply arranged as compared with the circuit illustrated inFIG. 4, and, thus, signals in the circuit may be simplified.

In some embodiments, each of synapse modules510,520,530, etc. of neuron device300illustrated inFIG. 5may be configured to operate in the time division multiplexing mode. During a first time section in the time division multiplexing mode, synapse modules510,520,530, etc. may be configured to receive spike_in[0,0], spike_in[0,1], and spike_in[0,2], respectively. Referring toFIG. 5, during the first time section, an MOSFET of the synapse module510may be configured to receive spike_in[0,0]. Similarly, during the first time section, MOSFETs of synapse modules520and530may be configured to receive spike_in[0,1] and spike_in[0,2], respectively. During the first time section, FG MOSFETs in first stages of synapse modules510,520,530, etc. may receive a read signal such as bias[0]=Vread. The read signal Vreadmay be a value suitable for reading information stored in a floating gate. During the first time section, FG MOSFETs in second stages of synapse modules510,520,530, etc. may receive a pass signal such as bias[1]=Vpass. The pass signal Vpassmay be a value for an FG MOSFET to operate as a closed switch regardless of the information stored in the floating gate of the FG MOSFET. During the first time section, FG MOSFETs in the other stages than the FG MOSFETs in the first stages may operate as closed switches like the FG MOSFETs in the second stages. During a second time section after the first time section, the MOSFETs of synapse modules510,520and530may receive spike[1,0], spike_in[1,1], and spike_in[1,2], respectively. During the second time section, the FG MOSFETs in the first stages of synapse modules510,520,530, etc. may receive bias[0]=Vpass. Meanwhile, the FG MOSFETs in the second stages may receive bias[1]=Vread. During the second time section, FG MOSFETs in the other stages than the FG MOSFETs in the second stages may operate as closed switches like the FG MOSFETs in the first stages.

FIG. 6is a block diagram illustrating another exemplary neuron device in accordance with at least some exemplary embodiments of the present disclosure. In some embodiments, a neuron device600may include an input unit610, a synapse unit620, and an output unit630. Input unit610may be configured to receive multiple input signals640-1to640-n.In some examples, multiple input signals640-1to640-nreceived by input unit610may include various forms of signals. For example, the input signals640-1to640-nmay include pulse signals, analog signals, and digital signals.

In some embodiments, synapse unit620may be connected to input unit610and may include one or more synapse modules622-1to622-k.In some examples, each of one or more synapse modules622-1to622-kmay include multiple synapse elements connected in series. Each synapse element may include an FG MOSFET. Synapse modules622-1to622-koperate in a similar manner as synapse modules322-1to322-killustrated inFIG. 3. Therefore, a detailed explanation of the same parts will be omitted. In addition, as illustrated inFIG. 6, the multiple synapse elements in each of the one or more synapse modules622-1to622-kmay further include additional FG MOSFETs624-1to624-k.

Each of the multiple synapse elements may have specific positive coefficient information or specific negative coefficient information by the additional FG MOSFET. In some examples, the specific positive coefficient information and negative coefficient information may be determined based on a threshold voltage of an FG MOSFET of each synapse element and/or connection between synapse unit620and output unit630. In some examples, one of the multiple synapse elements connected in series in one or more synapse modules622-1to622-kmay operate to apply the positive coefficient information or the negative coefficient information to one of the multiple input signals640-1to640-n.For example, one of the multiple synapse elements in synapse module622-1may have coefficient information w1 and additional FG MOSFET624-1of the synapse element may have coefficient information −w1′. In an example, one of the multiple synapse elements in synapse module622-1may apply the positive coefficient information w1or the negative coefficient information −w1′ to the input signal640-1received by input unit610.

In some embodiments, each of one or more synapse modules622-1to622-kmay be configured to operate in the time division multiplexing mode. The operation of synapse modules622-1to622-kin the time division multiplexing mode is the same as illustrated inFIG. 3except that the multiple synapse elements connected in series in each of synapse modules622-1to622-kmay apply negative coefficient information to an input signal through the additional FG MOSFETs. Therefore, an explanation thereof will be omitted for clarity.

FIG. 7is an exemplary circuit diagram of the neuron device ofFIG. 6. An input unit (not illustrated) of neuron device600may be configured to receive multiple input signals spike_in[0,0], spike_in[0,1], spike_in[0,2], spike_in[1,0], spike_in[1,1], spike_in[1,2], etc. and transfer the multiple input signals to gates of multiple FG MOSFETs, respectively. As shown inFIG. 7, a synapse unit of neuron device600may include one or more synapse modules710,720,730, etc. and each of synapse modules710,720,730, etc. may include multiple FG MOSFETs connected in series. As compared with those ofFIG. 3, each of synapse modules710,720,730, etc. may further include multiple FG MOSFETs sharing an input with the multiple FG MOSFETs connected in series, and the additional FG MOSFETs are connected in series with each other. An FG MOSFET and an additional FG MOSFET in each stage of each of synapse modules710,720,730, etc. may correspond to multiple synapse elements, respectively. DSL and SSL values may be associated with an effective operation of the FG MOSFET of neuron device600. As illustrated inFIG. 7, synapse module710may be configured to receive spike_in[0,0] and spike_in[1,0]. Synapse module720may be configured to receive spike_in[0,1] and spike_in[1,1]. Synapse module730may be configured to receive spike_in[0,2] and spike_in[1,2]. When neuron device600receives an input signal, an internal potential Vmemof neuron device600is determined based on the received input signal. For example, when neuron device600receives the input signal spike_in[0,0], the input signal spike_in[0,0] may be effectively applied to one of an FG MOSFET on the left or an FG MOSFET on the right. When the input signal spike_in[0,0] is effectively applied to the FG MOSFET on the left, a charge is accumulated in a capacitor connected to a Vmemstage, and, thus, the internal potential Vmemmay be increased. Meanwhile, when the input signal spike_in[0,0] is effectively applied to the FG MOSFET on the right, the charge accumulated in the capacitor connected to the Vmemstage is discharged, and, thus, the internal potential Vmemmay be decreased. In some examples, when the internal potential Vmemexceeds a predetermined threshold value, an output unit of neuron device600may generate an output signal OUT.

In some embodiments, each of synapse modules710,720, and730of neuron device600may be configured to operate in the time division multiplexing mode. In some examples, during a first time section in the time division multiplexing mode, an FG MOSFET in a first stage of the synapse module710may be configured to receive spike_in[0,0], and the other FG MOSFETs than the FG MOSFET in the first stage may receive input signals to operate as closed switches. Similarly, during the first time section, an FG MOSFET in a first stage of synapse module720may be configured to receive spike_in[0,1] and an FG MOSFET in a first stage of synapse module730may be configured to receive spike_in[0,2]. The other FG MOSFETs in synapse modules720and730than the FG MOSFETs in the first stages of synapse modules720and730may receive input signals to operate as closed switchwa switches. When spike_in[0,0], spike_in[0,1], and spike_in[0,2] are received during the first time section, specific coefficient information of the respective FG MOSFETs may be applied thereto, and, thus, charges corresponding thereto may be accumulated in capacitors connected to the Vmemstage or discharged. For example, when an input signal is effectively received by an FG MOSFET on the left, the internal potential Vmemmay be increased, and when an input signal is effectively received by an FG MOSFET on the right, the internal potential Vmemmay be decreased. When a voltage of the internal potential Vmemexceeds the threshold value, the output unit of neuron device600may generate the output signal OUT. During a second time section after the first time section, an FG MOSFET in a second stage of the synapse module710may receive spike_in[1,0], an FG MOSFET in a second stage of synapse module720may receive spike_in[1,1], and an FG MOSFET in a second stage of synapse module730may receive spike_in[1,2]. The other FG MOSFETs than the FG MOSFETs in the second stages of synapse modules720and730may receive input signals to operate as closed switches. When spike_in[1,0], spike_in[1,1], and spike_in[1,2] are received during the second time section, specific coefficient information of the respective FG MOSFETs may be applied thereto, and, thus, charges corresponding thereto may be accumulated in capacitors connected to the Vmemstage or discharged. When the internal potential Vmemexceeds the threshold value, the output unit of neuron device500may generate the output signal OUT. The operation in the time division multiplexing mode will be described below in more detail with reference toFIG. 8.

FIG. 8illustrates an example where a synapse unit of the exemplary neuron device600according toFIG. 7operates in the time division multiplexing mode. AlthoughFIG. 8illustrates neuron device600illustrated inFIG. 7, it will be understood by those skilled in the art that the time division multiplexing mode illustrated inFIG. 8may be modified to be suitable for neuron device300illustrated inFIG. 3.

In some embodiments, time sections in the time division multiplexing mode may include a first time section810and a second time section820. As illustrated inFIG. 8, during the first time section810, FG MOSFETs in first stages within the multiple modules of the synapse unit may receive spike_in[0,0], spike_in[0,1], and spike_in[0,2], respectively. All of FG MOSFETs in the other stages of the multiple modules may receive input signals to operate as closed switches with respect to the synapse unit of neuron device600during the first time section inFIG. 8in order for spike_in[0,0], spike_in[0,1], and spike_in[0,2] received during the first time section to be applied with coefficient information and then applied to output unit630. When spike_in[0,0], spike_in[0,1], and spike_in[0,2] are applied with coefficient information and then applied to the output unit630during the first time section, output unit630may obtain a weighted sum thereof and then output spike_out[0] based on the weighted sum.

During the second time section820after the first time section810, FG MOSFETs in second stages within the multiple modules of the synapse unit may receive spike_in[1,0], spike_in[1,1], and spike_in[1,2], respectively, as shown inFIG. 8. All of FG MOSFETs in the other stages of the multiple modules may receive input signals to operate as closed switches with respect to the synapse unit of neuron device600during the second time section inFIG. 8in order for spike_in[1,0], spike_in[1,1], and spike_in[1,2] received during the second time section to be applied with coefficient information and then applied to output unit630. When spike_in[1,0], spike_in[1,1], and spike_in[1,2] are applied with coefficient information and then applied to output unit630during the second time section, output unit630may obtain a weighted sum thereof and then output spike_out[1] based on the weighted sum.

Further, in some embodiments, each synapse element of the synapse unit of neuron device600may update coefficient information in each time section. For example, after a gate of an FG MOSFET illustrated inFIG. 8receives an input signal, a specific potential formed within a floating gate may be updated by applying an appropriate voltage to the FG MOSFET. In some embodiments, an internal potential of output unit630of neuron device600may be reset in each time section, and after the internal potential of output unit630is reset, each synapse element of the synapse unit may update its coefficient information.

FIG. 9is another exemplary circuit diagram of the neuron device ofFIG. 6. The neuron device illustrated inFIG. 9has the same circuit diagram as neuron device600illustrated inFIG. 7except the layout of lines for input signals. Therefore, an explanation of the same parts as illustrated inFIG. 7will be omitted. An input unit (not illustrated) of neuron device600may be configured to receive multiple input signals spike_in[n,0], spike_in[n,1], spike_in[n,2], etc. and transmit the input signals to synapse modules910,920,930, etc., respectively. As illustrated inFIG. 9, the input signals spike_in[n,0], spike_in[n,1], spike_in[n,2], etc. may be transmitted to gates of MOSFETs included in synapse modules910,920,930, etc., respectively. Herein, n includes 0 and positive integers. Two MOSFETs in each of the synapse modules illustrated inFIG. 9may be arranged to receive the same input signal.

Further, each of multiple FG MOSFETs included in each of multiple modules910,920,930, etc. may receive a signal indicating whether or not to read. For example, as illustrated inFIG. 9, FG MOSFETs in first stages of multiple modules910,920,930, etc., respectively, may receive bias[0], and FG MOSFETs in second stages may receive bias[1]. Due to this layout of lines, lines may be simply arranged as compared with the circuit illustrated inFIG. 7, and, thus, signals in the circuit may be simplified.

FIG. 10illustrates an example where a synapse unit of the exemplary neuron device600according toFIG. 9operates in a time division multiplexing mode. AlthoughFIG. 10illustrates neuron device600illustrated inFIG. 9, it will be understood by those skilled in the art that the time division multiplexing mode illustrated inFIG. 9may be modified to be suitable for neuron device300illustrated inFIG. 3.

In some embodiments, time sections in the time division multiplexing mode may include a first time section1010and a second time section1020. As illustrated inFIG. 10, during the first time section1010, MOSFETs in first stages and last stages within the multiple modules of the synapse unit may receive spike_in[0,0], spike_in[0,1], and spike_in[0,2], respectively. During the first time section1010, the FG MOSFETs in first stages within the multiple modules of the synapse unit may receive a signal bias[0]=Vread. Herein, Vreadrefers to a voltage that enables information stored in an FG MOSFET to be read. During the first time section1010, FG MOSFETs in stages other than the first stages may receive a signal Vpass. Herein, Vpassrefers to a voltage that enables its corresponding FG MOSFET to operate as a closed switch. For example, FG MOSFETs in second stages receive a signal bias[1]=Vpass.

During the second time section1020after the first time section1010, the MOSFETs in the first stages and the last stages within the multiple modules of the synapse unit may receive spike_in[1,0], spike_in[1,1], and spike_in[1,2], respectively. During the second time section1020, the FG MOSFETs in the second stages within the multiple modules of the synapse unit may receive a signal bias[1]=Vreadas illustrated inFIG. 10. During the second time section1020, FG MOSFETs in stages other than the second stages may receive a signal Vpass. For example, the FG MOSFETs in the first stages receive a signal bias[0]=Vpass.

FIG. 11is a block diagram illustrating an exemplary integrated circuit in accordance with at least some exemplary embodiments of the present disclosure. An integrated circuit1100may include multiple neuron devices1110-1,1110-2to1110-nand a connection unit1120. In some embodiments, each of multiple neuron devices1110-1,1110-2to1110-nmay include: an input unit configured to receive multiple input signals; a synapse unit connected to the input unit and including one or more synapse modules; and an output unit connected to the synapse unit and configured to generate an output signal like neuron device300illustrated inFIG. 3or neuron device600illustrated inFIG. 6. The one or more synapse modules may include multiple modules including multiple synapse elements connected in series and may be configured to operate in the time division multiplexing mode. In some examples, each of the synapse elements in the synapse unit may include an FG MOSFET and may have specific coefficient information. In each of the one or more synapse modules, one of the synapse elements connected in series may be configured to apply coefficient information to one of the received input signals. The output unit may obtain a weighted sum of the input signals to which the coefficient information is applied and generate an output signal based on the weighted sum.

In some embodiments, connection unit1120may be configured to interconnect multiple neuron devices1110-1,1110-2to1110-n.In some examples, connection unit1120may be configured to connect an output from one of multiple neuron devices1110-1,1110-2to1110-nwith an input to one or more of multiple neuron devices1110-1,1110-2to1110-n.For example, connection unit1120may connect an output from neuron device1110-1with an input to neuron device1110-2and/or neuron device1110-n.Connection unit1120may also connect output from neuron device1110-1with another input to neuron device1110-1.

In some embodiments, connection unit1120is programmable. In some examples, connection unit1120may include a field programmable gate array (FPGA). Programmable connection unit1120may change the interconnection among multiple neuron devices1110-1,1110-2to1110-nwithout a physical process to the circuit. In some examples, connection unit1120may be configured to dynamically change the interconnection among multiple neuron devices1110-1,1110-2to1110-nduring an operation of integrated circuit1100.

There is little distinction left between hardware and software implementations of the connection unit1120. The use of hardware or software is generally (but not always, in that in certain contexts the choice between hardware and software may become significant) a design choice representing cost vs. efficiency tradeoffs. A favorable means may vary with the context in which the processes and/or systems and/or other technologies are deployed.

The foregoing detailed description has set forth various exemplary embodiments of the devices and/or processes through the block diagrams and/or examples. Insofar as such block diagrams and/or examples contain one or more functions and/or operations, it will be understood by those skilled in the art that each function and/or operation within such block diagrams or examples can be implemented, individually and/or collectively, by a wide range of hardware, software, firmware, or virtually any combination thereof.

With respect to the use of substantially any plural and/or singular terms herein, those skilled in the art can translate from the plural to the singular and/or from the singular to the plural as is appropriate to the context and/or application. The various singular/plural permutations may be expressly set forth herein for sake of clarity. It will be understood by those skilled in the art that, in general, terms used herein and especially in the appended claims (e.g., the appended claims) are generally intended as “open” terms (e.g., the term “including” should be interpreted as “including but not limited to,” the term “having” should be interpreted as “having at least,” the term “includes” should be interpreted as “includes but is not limited to,” etc.).