Step-up switching converter and control circuit and method thereof

A control circuit and control method for controlling a step-up switching converter. The control circuit has an ultra-low voltage regulation module used to generate a control signal based on an output voltage feedback signal and an input voltage signal. When the input voltage signal is smaller than an ultra-low voltage threshold, the control signal controls a high side switch of the step-up switching converter off and controls a low side switch of the step-up switching converter to perform on and off switching. Meanwhile, a parasitic diode of the high side switch is on once the low side switch is off.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims the benefit of CN application No. 202010515990.8, filed on Jun. 9, 2020, and incorporated herein by reference.

TECHNICAL FIELD

The present invention generally refers to electrical circuit, and more particularly but not exclusively refers to step-up switching converter with ultra-low input voltage and associated control circuit and method.

BACKGROUND

In recent years, with continuous development of wireless sensor network, portable and wearable devices, smart-home devices and biomedical technologies etc., the collection and utilization of small power energy has attracted widespread attention, and the step-up switching converters are widely used in these energy collection applications.

As a bridge connection between power source and load, step-up switching converters need to solve a number of design challenges. For example, some energy collection applications, such as thermoelectric generators, solar panels etc., can only provide an output voltage with a few tens of millivolts to a step-up switching converter. However, the step-up switching converter still needs to maintain a normal operation at such an ultra-low input voltage.

Therefore, it is desired to have a control scheme and associated control method for a step-up switching converter having an ultra-low input voltage signal.

SUMMARY

Embodiments of the present invention are directed to a control circuit for controlling a step-up switching converter, the control circuit comprising a regular voltage regulation module and an ultra-low voltage regulation module. The regular voltage regulation module is configured to receive a voltage feedback signal indicative of an output voltage signal of the step-up switching converter to generate a first control signal. The ultra-low voltage regulation module is configured to receive the voltage feedback signal and an input voltage signal of the step-up switching converter to generate a second control signal. When the input voltage signal is larger than an ultra-low voltage threshold, the first control signal is configured to control a high side switch and a low side switch of the step-up switching converter to perform on and off switching. When the input voltage signal is smaller than the ultra-low voltage threshold, the second control signal is configured to turn the high side switch off and to control the low side switch to perform on and off switching. When the low side switch is turned off, a parasitic diode of the high side switch is turned on.

Embodiments of the present invention are directed to a step-up switching converter comprising a high side switch, a low side switch, a regular voltage regulation module and an ultra-low voltage regulation module. The regular voltage regulation module is configured to receive a voltage feedback signal indicative of an output voltage signal of the step-up switching converter to generate a first control signal. The ultra-low voltage regulation module is configured to receive the voltage feedback signal and an input voltage signal of the step-up switching converter to generate a second control signal. When the input voltage signal is larger than an ultra-low voltage threshold, the first control signal is configured to control the high side switch and the low side switch to perform on and off switching. When the input voltage signal is smaller than the ultra-low voltage threshold, the second control signal is configured to turn the high side switch off and to control the low side switch to perform on and off switching. When the low side switch is turned off, a parasitic diode of the high side switch is turned on.

Embodiments of the present invention are directed to a control method for controlling a step-up switching converter, the control method comprising several steps. The first step is determining whether an input voltage signal of the step-up switching converter is smaller than an ultra-low voltage threshold. The first step is generating a first control signal based on a voltage feedback signal indicative of an output voltage signal of the step-up switching converter when the step-up switching converter is larger than the ultra-low voltage threshold. The first control signal is configured to control a high side switch and a low side switch of the step-up switching converter to perform on and off switching. The second step is generating a second control signal based on the voltage feedback signal and an input voltage signal of the step-up switching converter when the step-up switching converter is smaller than the ultra-low voltage threshold. The second control signal is configured to turn the high side switch off and to control the low side switch to perform on and off switching. When the low side switch is turned off, a parasitic diode of the high side switch is turned on.

DETAILED DESCRIPTION

The phrase “couple” includes direct connection and indirect connection. Indirect connection includes connection through conductor which has resistance and/or parasitic parameters such as inductance and capacitance, or connection through diode, and so on.

FIG. 1illustrates a block diagram of a step-up switching converter100in accordance with an embodiment of the present invention. As shown inFIG. 1, the step-up switching converter100may comprise an inductor L, an output capacitor COUT, a low side switch11, a high side switch12and a control circuit20. Herein, the high side switch12may comprise a parasitic diode1201having a current direction only allows a current signal flowing through an input terminal of the step-up switching converter100to an output terminal of the step-up switching converter100. The input terminal of the step-up switching converter100is used for receiving an input voltage signal VIN, and the output terminal of the step-up switching converter100is used for providing an output voltage signal VOUT. In an exemplary embodiment ofFIG. 1, the inductor L, the output capacitor COUT, the low side switch11, and the high side switch12are illustrated to have a BOOST topology. In detail, each of the high side switch11and the low side switch12has a first terminal, a second terminal and a control terminal. The first terminal of the low side switch11and the first terminal of the high side switch12may be coupled together to constitute a common connection node SW. The second terminal of the low side switch11is connected to a logic ground. The second terminal of the high side switch12may be coupled to the output terminal of the step-up switching converter100. The inductor L may be coupled between the input terminal of the step-up switching converter100and the common connection node SW. The output capacitor COUT may be connected between the output terminal of the step-up switching converter100and the logic ground.

In the exemplary embodiment ofFIG. 1, the low side switch11is illustrated as an N-type Metal Oxide Semiconductor Field Effect Transistor (“MOSFET”), and the high side switch12is illustrated as a P-type MOSFET. More detail, the drain of the P-type MOSFET may be operated as the first terminal of the high side switch12, and the source of the P-type MOSFET may be operated as the second terminal of the high side switch12. Therefore, the parasitic diode1201of the high side switch12is illustrated to have an anode connected to the common connection node SW and a cathode connected to the output terminal of the step-up switching converter100. As can be appreciated, whereas the high side switch12and the low side switch11are illustrated as MOSFETs inFIG. 1, in other embodiment, the high side switch12and the low side switch11may comprise other suitable semiconductor devices such as Junction Field Effect Transistors (“JFETs”), Insulated Gate Bipolar Translators (“IGBTs”), Double Diffusion Metal Oxide Semiconductor (“DMOS”) etc.

In the exemplary embodiment ofFIG. 1, the control circuit20may comprise a regular voltage regulation module21, an ultra-low voltage regulation module22, a mode determining circuit23and a logic circuit24. The step-up switching converter100may be configured to operate in a regular voltage regulation mode or an ultra-low voltage regulation mode.

In an embodiment, the regular voltage regulation module21may be configured to receive a voltage feedback signal VFB which is indicative of the output voltage signal VOUT, and further configured to generate a first control signal CTRL1based on the voltage feedback signal VFB. The first control signal CTRL1may be configured to control the high side switch12and the low side switch11to perform on and off switching when the step-up switching converter100operates in the regular voltage regulation mode. In an embodiment, the first control signal CTRL1may comprise a logic signal with an active state (e.g., the logic high state) and an inactive state (e.g., the logic low state). In an embodiment, when the voltage feedback signal VFB is smaller than a desired reference voltage, the first control signal CTRL1is in the active state; when the voltage feedback signal VFB is larger than the desired reference voltage, the first control signal CTRL1is in the inactive state. In an embodiment, the desired reference signal is indicative of a desired voltage of the output voltage VOUT of the step-up switching converter100. In an embodiment, when the first control signal CTRL1is in the active state, the low side switch11is turned on and the high side switch12is turned off so that an inductor current signal flowing through the inductor L is increased linearly. When the first control signal CTRL1is in the inactive state, the low side switch11is turned off and the high side switch12is turned on, the inductor current signal is freewheeling through the high side switch12. In an embodiment, the regular voltage regulation module21may adopt different control schemes, e.g., a constant ON time (COT) controlled scheme, a peak current controlled scheme, an average current controlled scheme, a valley current controlled scheme, etc., to regulate the output voltage signal VOUT. Therefore, the regular voltage regulation module21may comprise any suitable modules for realizing different control schemes. As can be appreciated, when the regular voltage regulation module21adopts any one of current controlled method, the regular voltage regulation module21may further be configured to receive a current feedback signal which is indicative of a current signal flowing through the step-up switching converter100. In such an application, the regular voltage regulation module21may be configured to generate the first control signal CTRL1based on the voltage feedback signal VFB and the current feedback signal.

In an embodiment, the ultra-low voltage regulation module22may be configured to receive the voltage feedback signal VFB and the input voltage signal VIN of the step-up switching converter100, and further configured to generate a second control signal CTRL2based on the voltage feedback signal VFB and the input voltage signal VIN. The second control signal CTRL2may be configured to control the high side switch12off and to control the low side switch11to perform on and off switching when the step-up switching converter100operates in the ultra-low voltage regulation mode. In an embodiment, the on time of the low side switch11is relative to a potential of the input voltage signal VIN. In an embodiment, a duration of the on time of the low side switch11is increased with decrease of the potential of the input voltage signal VIN, i.e., the smaller the potential of the input voltage signal VIN is, the longer the duration of the on time of the low side switch11is. In an embodiment, the second control signal CTRL2may comprise a logic signal with an active state (e.g., the logic high state) and an inactive state (e.g., the logic low state). In an embodiment, when the voltage feedback signal VFB is smaller than the desired reference voltage, the second control signal CTRL2is in the active state; when the voltage feedback signal VFB is larger than the desired reference voltage, the second control signal CTRL2is in the inactive state. In an embodiment, when the second control signal CTRL2is in the active state, the low side switch11is turned on and the high side switch12is turned off so that the inductor current signal flowing through the inductor L is increased linearly. When the second control signal CTRL2is in the inactive state, the low side switch11is turned off while the high side switch12is kept off and the inductor current signal is freewheeling through the parasitic diode1201of the high side switch12. For instance, in a COT controlled scheme, when the voltage feedback signal VFB is smaller than the desired reference signal, the second control signal CTRL2may be configured to control the low side switch11on and the high side switch12off such that the inductor L is charged by the input voltage signal VIN through the low side switch11. After a certain period, the second control signal CTRL2may be configured to control the low side switch11off such that the inductor current signal IL is freewheeling through the parasitic diode1201of the high side switch12. As can be appreciated, the certain period is determined by the input voltage signal VIN.

In the exemplary embodiment ofFIG. 1, the mode determining circuit23may be configured to receive the input voltage signal VIN, and further configured to compare the input voltage signal VIN with an ultra-low voltage threshold to generate an enable signal EN. In an embodiment, the enable signal EN is configured to determine whether the step-up switching converter100operates in the regular voltage regulation mode or the ultra-low voltage regulation mode. In an embodiment, the enable signal EN may comprise a logic signal with an active state (e.g., the logic high state) and an inactive state (e.g., the logic low state). In an embodiment, the active state of the enable signal EN may indicate that the step-up switching converter100operates in the regular voltage regulation mode, while the inactive state of the enable signal EN may indicate that the step-up switching converter100operates in the ultra-low voltage regulation mode. In an embodiment, the mode determining circuit23may further comprise an input voltage feedback circuit configured to generate an input voltage feedback signal indicative of the input voltage signal VIN. In such an embodiment, the mode determining circuit23may be configured to receive the input voltage feedback signal, and further configured to compare the input voltage feedback signal with an enable threshold indicative of the ultra-low voltage threshold to generate the enable signal EN.

In an embodiment, the logic circuit24may be configured to receive the enable signal EN, the first control signal CTRL1and the second control signal CTRL2, and further configured to conduct a logic operation of the enable signal EN, the first control signal CTRL1and the second control signal CTRL2to generate a high side control signal HS and a low side control signal LS. The high side control signal HS is configured to control the high side switch12to perform on and off switching. The low side control signal LS is configured to control the low side switch11to perform on and off switching. The high side control signal HS and the low side control signal LS may be logic signals having an active state (e.g., logic high) and an inactive state (e.g., logic low).

In an embodiment, when the input voltage signal VIN is larger than the ultra-low voltage threshold, the enable signal EN is configured to enable the logic circuit24to generate the high side control signal HS and the low side control signal LS based on the first control signal CTRL1. In such an application, the high side control signal HS is configured to control the high side switch12and the low side switch11to perform on and off switching, and the low side control signal LS is configured to control the low side switch11to perform on and off switching. When the input voltage signal VIN is smaller than the ultra-low voltage threshold, the enable signal EN is configured to enable the logic circuit24to generate the high side control signal HS and the low side control signal LS based on the second control signal CTRL2. In such an application, the high side control signal HS is configured to turn the high side switch11off, and the low side control signal LS is configured to control the low side switch11to perform on and off switching.

FIG. 2schematically illustrates a step-up switching converter200in accordance with an embodiment of the present invention. In the exemplary embodiment ofFIG. 2, the regular voltage regulation module21is illustrated as an adaptive COT controlled module. The first control signal CTRL1may comprise an on time control signal TON and an off time control signal TOFF. In an embodiment, both the on time control signal TON and the off time control signal TOFF may be logic signals with an active state (e.g., the logic high state) and an inactive state (e.g., the logic low state). As shown inFIG. 2, the regular voltage regulation module21may comprise an on time generator201and an off time generator202.

In the exemplary embodiment ofFIG. 2, the on time generator201may be configured to receive the input voltage signal VIN and the output voltage signal VOUT to generate the on time control signal TON. In an embodiment, when the on time control signal TON is changed from the inactive state to the active state, the low side switch11is turned off and the high side switch12is turned on. In an embodiment, the on time control signal TON is configured to determine the duration of the on time of the low side switch11when the step-up switching converter100operates in the regular voltage regulation mode. As can be appreciated, in a regular COT controlled scheme, the on time control signal TON may be irrelevant with the input voltage signal VIN and the output voltage signal VOUT. The on time generator201may be configured to generate the on time control signal TON based on a default constant voltage signal, e.g., a power supply voltage signal VCC.

In the exemplary embodiment ofFIG. 2, the off time generator202may be configured to receive the voltage feedback signal VFB and desired reference signal VREF, and further configured to compare the voltage feedback signal VFB with the desired reference signal VREF to generate the off time control signal TOFF.

In an embodiment, when the voltage feedback signal VFB is smaller than the desired reference signal VREF, the off time control signal TOFF is changed from the inactive state the active state to turn the low side switch11on. That is, the off time control signal TOFF is configured to determine the on moment of the low side switch11.

In the exemplary embodiment ofFIG. 2, the off time generator202may comprise a voltage comparator2021having an inverting terminal, a non-inverting terminal, and an output terminal. The inverting terminal of the voltage comparator2021operated as the first input terminal of the off time generator202is configured to receive the voltage feedback signal VFB, and the non-inverting terminal of the voltage comparator2021operated as the second input terminal of the off time generator202is configured to receive the voltage reference signal VREF. The voltage comparator2021may be configured to compare the voltage feedback signal VFB with the reference voltage signal VREF to generate the off time control signal TOFF at its output terminal.

In the exemplary embodiment ofFIG. 2, the ultra-low voltage regulation module22may also comprise the off time generator202. Besides, the ultra-low voltage regulation module22may further comprise a max on time generator203. In an embodiment, the max on time generator203may be configured to receive the input voltage signal VIN, and further configured to generate a max on time control signal TONmax based on the input voltage signal VIN. The max on time control signal TONmax may be a logic signal with an active state (e.g., the logic high state) and an inactive state (e.g., the logic low state). In an embodiment, when the max on time control signal TONmax is changed from the inactive state to the active state, the low side switch11is turned off. In an embodiment, the max on time control signal TONmax is configured to determine a duration of the on time of the low side switch11when the step-up switching converter100operates in the ultra-low voltage regulation mode. In an embodiment, the duration of the on time of the low side switch11is increased with decrease of the potential of the input voltage signal VIN, i.e., the smaller the input voltage signal VIN is, the longer the duration of the on time of the low side switch11is. In such an application, the second control signal CTRL2may comprise the off time control signal TOFF and the max on time control signal TONmax.

In the exemplary embodiment ofFIG. 2, the mode determining circuit23may be illustrated as a voltage comparator231having an inverting terminal, a non-inverting terminal, and an output terminal. The inverting terminal of the voltage comparator231is configured to receive the ultra-low voltage threshold VTH, and the non-inverting terminal of the voltage comparator231is configured to receive the input voltage signal VIN. The voltage comparator231may be configured to compare the input voltage signal VIN with the ultra-low voltage threshold VTH to generate the enable signal EN at its output terminal. In an embodiment, the ultra-low voltage threshold VTH is smaller than 300 mV. In an embodiment, when the input voltage signal VIN is larger than the ultra-low voltage threshold VTH, the enable signal EN is in the active state to enable the step-up switching converter100to operate in the regular voltage regulation mode. When the input voltage signal VIN is smaller than the ultra-low voltage threshold VTH, the enable signal EN is in the inactive state to enable the step-up switching converter100to operate in the ultra-low voltage regulation mode.

In the exemplary embodiment ofFIG. 2, the logic circuit24may be configured to receive the enable signal EN, the on time control signal TON, the off time control signal TOFF and the max on time control signal TONmax, and further configured to generate the high side control signal HS and the low side control signal LS based on the enable signal EN, the on time control signal TON, the off time control signal TOFF and the max on time control signal TONmax. In an embodiment, the logic circuit24may comprise a first RS flip-flop204, a second RS flip-flop205, a first AND logic gate206, a second AND logic gate207, a third AND logic gate208, and a first OR logic gate209.

The first RS flip-flop204may comprise a set terminal S configured to receive the off time control signal TOFF, a reset terminal R configured to receive the on time control signal TON, a first output terminal configured Q1to provide a first low side control signal LS1and a second output terminal Q2configured to provide a first high side control signal HS1. In an embodiment, when the off time control signal TOFF is in the active state, the first low side control signal LS1is in an active state (e.g., the logic high state), and the first high side control signal HS1is an inactive state (e.g., the logic low state). When the on time control signal TON is in the active state, and the first low side control signal LS1is in an inactive state (e.g., the logic low state), and the first high side control signal HS1is in an active state (e.g., the logic high state).

The second RS flip-flop205may comprise a set terminal S configured to receive the off time control signal TOFF, a reset terminal R configured to receive the max on time control signal TONmax, a first output terminal Q1configured to provide a second low side control signal LS2. In an embodiment, when the off time control signal TOFF is in the active state, the second low side control signal LS2is in the inactive state (e.g., the logic low state). When the max on time control signal TONmax is in an active state, the second low side control signal LS2is in an active state (e.g., the logic high state).

The first AND logic gate206may be configured to receive the enable signal EN and the first high side control signal HS1, and further configured to conduct a logic AND operation of the enable signal EN and the first high side control signal HS to generate the high side control signal HS.

It should be understood, when the step-up switching converter100is operated in a continuous conduction mode, the logic states of the high side control signal HS and the logic states of the low side control signal LS are complementary. However, when the step-up switching converter100is operated in a discontinuous conduction mode (DCM), the high side switch12should be turned off when the inductor current signal flowing through the inductor L is decreased to a zero-crossing threshold. In an embodiment, the zero-crossing threshold is equal to zero. Therefore, in such an application, the regular voltage regulation module21may further comprise a zero-crossing signal generator to generate a zero-crossing signal ZCD to denote whether the inductor current signal is decreased to the zero-crossing threshold. In such an application, the first control signal CTRL1may comprise the on time control signal TON, the off time control signal TOFF, and the zero-crossing signal ZCD. Meanwhile, the first AND logic gate206may further be configured to receive the zero-crossing signal ZCD and to generate the high side control signal HS based on the enable signal EN, the first high side control signal HS1and the zero-crossing signal ZCD.

The second AND logic gate207may be configured to receive the enable signal EN and the first low side control signal LS1, and further configured to conduct a logic AND operation of the enable signal EN and the first low side control signal LS1to generate a third low side control signal LS3.

The third AND logic gate208may be configured to receive an inversing signal of the enable signal EN and the second low side control signal LS2, and further configured to conduct a logic AND operation of the inversing signal of the enable signal EN and the second low side control signal LS2to generate a fourth low side control signal LS4.

The first OR logic gate209may be configured to receive the third low side control signal LS3and the fourth low side control signal LS4, and further configured to conduct a logic OR operation of the third low side control signal LS3and the fourth low side control signal LS4to generate the low side control signal LS.

FIG. 3schematically illustrates a step-up switching converter300in accordance with an embodiment of the present invention. Comparing with the step-up switching converter200ofFIG. 2, the step-up switching converter300may comprise a different logic circuit24.

As shown inFIG. 3, the logic circuit24of the step-up switching converter300may comprise a fourth AND logic gate301, a fifth AND logic gate302, a sixth AND logic gate305, a second OR logic gate303and a third RS flip-flop304.

The fourth AND logic gate301may be configured to receive the enable signal EN and the max on time control signal TONmax, and further configured to conduct a logic AND operation of the enable signal EN and the max on time control signal TONmax to generate a first on time control signal TON1.

The fifth AND logic gate302may be configured to receive an inversing signal of the enable signal EN and the on time control signal TON, and further configured to conduct a logic AND operation of the inversing signal of the enable signal EN and the on time control signal TON to generate a second on time control signal TON2.

The second OR logic gate303may be configured to receive the first on time control signal TON1and the second on time control signal TON2, and further configured to conduct a logic OR operation of the first on time control signal TON1and the second on time control signal TON2to generate a third on time control signal TON3.

The third RS flip-flop304may comprise a set terminal S configured to receive the off time control signal TOFF, a reset terminal R configured to receive the third on time control signal TON3, a first output terminal Q1to provide the low side control signal LS and a second output terminal Q2to provide a second high side control signal HS2. In an embodiment, when the off time control signal TOFF is in the active state, the second high side control signal HS2is in an inactive state (e.g., the logic low state); and when the third on time control signal TON3is in the active state, the second high side control signal HS2is in an active state (e.g., the logic high state).

The sixth AND logic gate305may be configured to receive the enable signal EN and the second high side control signal HS2, and further configured to conduct a logic AND operation of the enable signal EN and the second high side control signal HS2to generate the high side control signal HS.

As mentioned above, it should be understood that when the step-up switching converter100is operated in DCM, the regular voltage regulation module21may further comprise the zero-crossing signal generator to generate the zero-crossing signal ZCD. In such an application, the first control signal CTRL1may comprise the on time control signal TON, the off time control signal TOFF and the zero-crossing signal ZCD. The sixth AND logic gate305may further be configured to receive the zero-crossing signal ZCD, and further configured to generate the high side control signal HS based on the enable signal EN, the second high side control signal HS2and the zero-crossing signal ZCD.

FIG. 4schematically illustrates the max on time generator203ofFIGS. 2 and 3in accordance with an embodiment of the present invention. In the exemplary embodiment ofFIG. 4, the on time generator203may comprise a regulation current signal generator40, a capacitor45, a reset switch46and a comparator47.

In an embodiment, the regulation current signal generator40may be configured to receive the input voltage signal VIN to generate a regulation current signal Imax.

In the exemplary embodiment ofFIG. 4, the regulation current signal generator40may comprise an operational amplifier41, a transistor42, a current mirror43and a resistor44with a resistance RF. The operational amplifier41may have a first input terminal configured to receive the input voltage signal VIN, a second input terminal, and an output terminal. The transistor42may have a first terminal coupled to the second input terminal of the operational amplifier41, a second terminal, and a control terminal coupled to the output terminal of the operational amplifier41. The resistor44may be coupled between the first terminal of the transistor42and the logic ground. The current mirror43may have a first current terminal coupled to the second terminal of the transistor42, a second current terminal operated as an output terminal of the regulation current signal generator40to provide the regulation current signal Imax. Herein, the regulation current signal Imax is equal to VIN/RF.

The capacitor45may be connected between the output terminal of the regulation current signal generator40and the logic ground. The regulation current signal Imax is configured to charge the capacitor45to generate a voltage signal VCF1across the capacitor45. The voltage comparator47may have a first input terminal configured to receive the voltage signal VCF1, a second input terminal configured to receive a reference voltage signal VREF_on, and an output terminal. The comparator47may be configured to compare the voltage signal VCF1with the reference voltage signal VREF_on to generate the max on time control signal TONmax at its output terminal. The reset switch46may have a first input terminal coupled to the output terminal of the regulation current signal generator40, a second input terminal connected to the logic ground, and a control terminal. In an embodiment, the control terminal of the reset switch46is controlled by the low side control signal LS. In such an application, when the low side control signal LS is in the active state (i.e., the low side switch11is turned on), the reset switch46is turned off so that the regulation current signal Imax may begin to charge the capacitor45. When the low side control signal LS is in the inactive state (i.e., the low side switch11is turned off), the reset switch46is turned on so that the capacitor45is discharged through the reset switch46. In an embodiment, the smaller the input voltage signal VIN is, the longer time the voltage signal VCF1increases to be equal to the reference voltage signal VREF_on at the same resistance RF of the resistor44, capacitance CF of capacitor45and potential of the reference voltage signal VREF_on. That is, the on time of the low side switch11is varied in the change of the input voltage signal VIN, and the smaller the input voltage signal VIN is, the longer the on time of the low side switch11is.

FIG. 5schematically illustrates the max on time generator203ofFIGS. 2 and 3in accordance with other embodiments of the present invention. In the exemplary embodiment ofFIG. 5, the on time generator203may comprise a current source51, a capacitor52, a reset switch53, a controlled voltage signal generator54and a comparator55.

The capacitor52may be connected between the current source51and the logic ground. A current signal IREF_on provided by the current source51is configured to charge the capacitor52to generate a voltage signal VCF2across the capacitor52. The controlled voltage signal generator54may be configured to receive the input voltage signal VIN to generate a controlled voltage signal Vmax. In an embodiment, the potential of the controlled voltage signal Vmax is inversely proportion to the potential of the input voltage signal VIN, i.e., the smaller the input voltage signal VIN is, the larger the controlled voltage signal Vmax is, and vice versa. In an embodiment, the controlled voltage signal generator54may comprise a subtractor which is configured to subtract the input voltage signal VIN from a constant voltage signal VP to generate the controlled voltage signal Vmax., i.e., Vmax=VP−VIN. The voltage comparator55may have a first input terminal configured to receive the voltage signal VCF2, a second input terminal configured to receive the controlled voltage signal Vmax, and an output terminal. The comparator55may be configured to compare the voltage signal VCF2with the controlled voltage signal Vmax to generate the max on time control signal TONmax at its output terminal. The reset switch53may have a first input terminal coupled to the current source51, a second input terminal connected to the logic ground, and a control terminal. In an embodiment, the control terminal of the reset switch53is controlled by the low side control signal LS. In such an application, when the low side control signal LS is in the active state (i.e., the low side switch11is turned on), the reset switch53is turned off so that the current signal IREF_on may begin to charge the capacitor52. When the low side control signal SL is in the inactive state (i.e., the low side switch11is turned off), the reset switch53is turned on so that the capacitor52is discharged through the reset switch53. In an embodiment, for an unchanged resistance RF of the resistor44, capacitance CF of capacitor45and potential of the reference voltage signal VREF_on, the smaller the input voltage signal VIN is, the longer time the voltage signal VCF2increases to be equal to the controlled voltage signal Vmax. That is, the on time of the low side switch11is varied in the change of the input voltage signal VIN, and the smaller the input voltage signal VIN is, the longer the on time of the low side switch11is.

FIG. 6schematically illustrates the on time generator201ofFIGS. 2 and 3in accordance with an embodiment of the present invention. In the exemplary embodiment ofFIG. 6, the on time generator201may comprise a controlled current signal generator61, a controlled voltage signal generator62, a capacitor63, a reset switch64and a comparator65.

The controlled current signal generator61may be configured to receive the output voltage signal VOUT to generate a charging current signal ICH. In an embodiment, the value of the charging current signal ICH is proportional to the potential of the input voltage signal VIN. The capacitor63may be connected between an output terminal of the controlled current signal generator61and the logic ground. The charging current signal ICH is configured to charge the capacitor63to generate a voltage signal VCF3across the capacitor63. The controlled voltage signal generator62may be configured to receive the input voltage signal VIN and the output voltage signal VOUT to generate a controlled voltage signal VD. In an embodiment, the controlled voltage signal VD is proportional to a difference of the output voltage signal VOUT and the input voltage signal VIN (i.e., VOUT−VIN). The voltage comparator65may have a first input terminal configured to receive the controlled voltage signal VD, a second input terminal configured to receive the voltage signal VCF3, and an output terminal. The comparator65may be configured to compare the controlled voltage signal VD with the voltage signal VCF3to generate the on time control signal TON at its output terminal. The reset switch64may have a first input terminal coupled to the output terminal of the controlled current signal generator61, a second input terminal connected to the logic ground, and a control terminal. In an embodiment, the control terminal of the reset switch64is controlled by the low side control signal LS. In such an application, when the low side control signal LS is in the active state (i.e., the low side switch11is turned on), the reset switch64is turned off so that the charging current signal ICH may begin to charge the capacitor63. When the low side control signal LS is in the inactive state (i.e., the low side switch11is turned off), the reset switch64is turned on so that the capacitor63is discharged through the reset switch64. As can be appreciated, the embodiments illustrated inFIGS. 2 and 3, and 6are dedicated exemplary embodiments in which the on time control signal TON is relevant with the input voltage signal VIN and the output voltage signal VOUT. In other embodiments, such as the regular COT controlled scheme, the on time control signal TON may be irrelevant with the input voltage signal VIN and the output voltage signal VOUT. For example, the controlled current signal generator61and the controlled voltage signal generator62may respectively receive the power supply voltage signal VCC to generate the on time control signal TON.

As can be appreciated, the schematic diagrams of the regular voltage regulation module21ofFIGS. 2 and 3are embodiments for illustrating COT controlled schemes. In other embodiments, the regular voltage regulation module21may comprise other suitable modules and elements for realizing different voltage and current regulation schemes to generate the first control signal CTRL1to regulate the output voltage signal VOUT. For instance,FIG. 7schematically illustrates the regular voltage regulation module21ofFIGS. 2 and 3in accordance with an embodiment who has an average current controlled scheme. In such an embodiment, the first control signal CTRL1may comprise the on time control signal TON, the off time control signal TOFF and the zero-crossing signal ZCD, and the regular voltage regulation module21may comprise the on time generator201configured to provide the on time control signal TON, the off time generator202configured to provide the off time control signal TOFF and the zero-crossing signal generator74configured to provide the zero-crossing signal ZCD.

As shown inFIG. 7, the on time generator201may comprise a clock signal generator71configured to provide a clock signal operated as the on time control signal TON.

The off time generator202may comprise an error amplifier72and a current comparator73. In an embodiment, the error amplifier72may have a first input terminal, a second input terminal and an output terminal. The first input terminal of the error amplifier72may be configured to receive the voltage feedback signal VFB. The second input terminal of the error amplifier72may be configured to receive the reference signal VREF. The error amplifier72may be configured to amplify the difference of the voltage feedback signal VFB and the reference signal VREF to provide an error signal EA at its the output terminal. The current comparator73may have a first input terminal, a second input terminal and an output terminal. The first input terminal of the current comparator73may be configured to receive the error signal EA. The second input terminal of the current comparator73may be configured to receive a current sensing signal VCS indicative of the inductor current signal flowing through the inductor L. The current comparator73may be configured to compare the error signal EA with the current sensing signal VCS to provide the off time control signal TOFF at its output terminal. In an embodiment, the zero-crossing signal generator74may be configured to receive the current sensing signal VCS and a zero-crossing threshold VTH_zcd, and further configured to compare the current sensing signal VCS with the zero-crossing threshold VTH_zcd to generate the zero-crossing signal ZCD. As can be appreciated, the regular voltage regulation module21in the exemplary embodiment ofFIG. 7may be combined with the ultra-low voltage regulation module22and the logic circuit23ofFIGS. 2 and 3to generate the high side control signal HS and the low side control signal LS.

FIG. 8illustrates a control method800for a step-up switching converter in accordance with an embodiment of the present invention. The control method800can be carried out in the embodiments of this application mentioned above with reference toFIGS. 1-7. The control method800may comprise steps801-804.

In step801, determining whether the input voltage signal VIN is smaller than the ultra-low voltage threshold VTH. If the input voltage signal VIN is smaller than the ultra-low voltage threshold VTH, continues with step802, otherwise, turns to step804.

In step802, turning the high side switch12off. In an embodiment, the high side switch12may comprise a parasitic diode having the current direction only allowing a current signal flowing through the input terminal of the step-up switching converter to the output terminal of the step-up switching converter.

In step803, generating the low side control signal LS based on the input voltage signal VIN and the voltage feedback signal VFB to control the low side switch11to perform on and off switching. In an embodiment, when the low side switch11is turned off, the inductor current signal IL is freewheeling through the parasitic diode1201of the high side switch12. In an embodiment, the step803may comprise a step8031and a step8032.

In step8031, generating the off time control signal TOFF based on the voltage feedback signal VFB to control an on moment of the low side switch11.

In step8032, generating the max on time control signal TON based on the input voltage signal VIN to control an off moment of the low side switch11. In an embodiment, the duration of the on time of the low side switch11is increased with decrease of the potential of the input voltage signal VIN, i.e., the smaller the input voltage signal VIN is, the longer the on time of the low side switch11is.

In step804, generating the low side control signal LS and the high side control signal HS based on the voltage feedback signal VFB to control the low side switch11and the high side switch12to perform on and off switching.

It should be understood that in the exemplary embodiment ofFIG. 8, although the step803is arranged after the step802, actually, the step802and the step803may be happened synchronously. Similarly, although the step8032is arranged after the step8031, actually, the step8031and the step8032may be happened synchronously.

Obviously many modifications and variations of the present invention are possible in light of the above teachings. It is therefore to be understood that within the scope of the appended claims the invention may be practiced otherwise than as specifically described. It should be understood, of course, the foregoing invention relates only to a preferred embodiment (or embodiments) of the invention and that numerous modifications may be made therein without departing from the spirit and the scope of the invention as set forth in the appended claims. Various modifications are contemplated and they obviously will be resorted to by those skilled in the art without departing from the spirit and the scope of the invention as hereinafter defined by the appended claims as only a preferred embodiment(s) thereof has been disclosed.