Flash memory

The present invention aims at providing a flash memory that can perform a refresh operation at an appropriate time before a read error occurs. The controller performs the first read operation in which the memory cell as the read target is made to draw out the potential of one of the bit lines, the bit line potential controller is made to draw out the potential of the other of the bit lines at the first speed, and concurrently, the sense amplifier is made to read data; the second read operation in which the memory cell as the read target is made to draw out the potential of one of the bit lines, the bit line potential controller is made to draw out the potential of the other of the bit lines at the second speed faster than the first speed, and concurrently, the sense amplifier is made to read data; and the refresh operation in which, when the data read by the first read operation and the data read by the second read operation are determined to be different, the data stored in the memory cell as the read target is rewritten.

CROSS-REFERENCE TO RELATED APPLICATIONS

The disclosure of Japanese Patent Application No. 2016-173341 filed on Sep. 6, 2016 including the specification, drawings and abstract is incorporated herein by reference in its entirety.

BACKGROUND

The present invention relates to a flash memory.

The flash memory is employed for a memory device such as a USB memory and a memory card. In addition to this, the flash memory is also mounted in a micro controller to store data used by the micro controller.

The flash memory is a nonvolatile memory and the rewritten data is stored in a memory cell. However, depending on the conditions after the data is rewritten, a threshold voltage in the memory cell may be varied significantly so that the data may not be properly read any longer.

For example, Patent Literature 1 discloses a nonvolatile memory comprised of a temperature sensor and a timer, in which the timer measures a period when the temperature measured with the temperature sensor exceeds a threshold temperature, and when the measured period reaches a threshold, refresh is performed.

As another example, Patent Literature 2 discloses equipment comprised of a nonvolatile memory. The nonvolatile memory is comprised of a timer to measure an elapsed time after performing a write operation to the nonvolatile memory, a temperature sensor to measure temperature near the nonvolatile memory, and a counter to count the number of times of the write operation to the nonvolatile memory. After weighting the period measured with the timer, based on the temperature measured with the temperature sensor and on the number of times of the write operation counted with the counter, a rewrite operation is performed to the nonvolatile memory when the weighted elapsed time measured with the timer exceeds a prescribed period.

PATENT LITERATURE

SUMMARY

However, in Patent Literature 1, if the power supply is not turned on, there is no means to measure the period when the temperature of the nonvolatile memory exceeds the threshold temperature. Accordingly, it is difficult to measure correctly the period when the temperature of the nonvolatile memory exceeds the threshold temperature. Also in Patent Literature 2, if the power supply is not turned on, the timer cannot measure the elapsed time after the write operation. Accordingly, it is difficult to count the number of times of the write operation to the nonvolatile memory by the counter. Therefore, the timing of the refresh operation is delayed and data may not be read properly. When the timing of the refresh operation is specified by the period (time), an unnecessary refresh operation may be performed.

The present invention is made in view of the above, and aims at providing a flash memory that can perform a refresh operation at an appropriate time before a read error occurs.

The outline of a typical invention disclosed by the present application will be explained briefly as follows.

A flash memory according to a typical embodiment of the present invention is comprised of: multiple memory cells; a sense amplifier that is coupled, at an input terminal, to a pair of bit lines coupled to the mutually different memory cells, and that reads data stored in the memory cell as a read target, based on potential of one of the bit lines and potential of the other of the bit lines, coupled to the memory cell as the read target; a bit line potential controller to draw out the potential of the bit line; and a controller. The controller performs a first read operation, a second read operation, and a refresh operation. In the first read operation, the memory cell as the read target is made to draw out the potential of the one of the bit lines, the bit line potential controller is made to draw out the potential of the other of the bit lines at a first speed, and concurrently, the sense amplifier is made to read the data. In the second read operation, the memory cell as the read target is made to draw out the potential of the one of the bit lines, the bit line potential controller is made to raw out the potential of the other of the bit lines at a second speed faster than the first speed, and concurrently, the sense amplifier is made to read the data. In the refresh operation, the data read by the first read operation and the data read by the second read operation are compared, and when the data read by the first read operation and the data read by the second read operation are determined to be different, the data stored in the memory cell as the read target is rewritten in the memory cell as the read target.

The effect obtained by the typical invention disclosed by the present application will be explained briefly as follows.

That is, according to the typical embodiment, it becomes possible to perform a refresh operation at the appropriate time before a read error occurs.

DETAILED DESCRIPTION

Hereinafter, the embodiment of the present invention is described in detail, with reference to the drawings. In the entire diagrams to explain the embodiments of the present invention, the same symbol is attached to the same element in principle, and the repeated explanation thereof is omitted.

<The Configuration of a Micro Controller>

FIG. 1is a block diagram illustrating an example of the configuration of a micro controller that mounts a flash memory according to Embodiment 1 of the present invention. As illustrated inFIG. 1, the micro controller300is comprised of a flash memory100, a CPU (Central Processing Unit)301, a DMAC (Direct Memory Access Controller)302, a sequencer303, a RAM (Random Access Memory)304, a bus interface (bus I/F)305, a PLL (Phase Locked Loop)306, a temperature sensor307, a timer308, ports309and310, a high-speed bus311, and a peripheral bus312.

The flash memory100, the CPU301, the DMAC302, the sequencer303, the RAM304, and the bus interface305are mutually coupled via the high-speed bus311, and data input/output among these units is performed via the high-speed bus311. With the high-speed bus311, the data input/output is performed at higher speed than with the peripheral bus312.

The flash memory100, the bus interface305, the PLL306, the temperature sensor307, the timer308, and the ports309and310are mutually coupled via the peripheral bus312, and data input/output among these units is performed via the peripheral bus312.

The CPU301controls each unit configuring the micro controller300. For example, the CPU301performs data input/output to and from the flash memory100. The CPU301controls data input/output to be performed among the units such as the flash memory100and the peripheral circuit, via the DMAC302, as will be described later. The CPU301instructs the sequencer303to perform the sequence control related to each of operations such as an erase operation, a rewrite (write) operation, and a read operation to the flash memory100. The CPU301performs data input/output to and from each unit coupled to the peripheral bus312, via the bus interface305.

Based on instructions by the CPU301for example, the DMAC302performs data input/output between the flash memory100and the peripheral circuit for example, without passing the CPU301.

The sequencer303performs the sequence control over the flash memory100. Based on the instructions from the CPU301and the DMAC302for example, the sequencer303performs sequence control to each unit configuring the flash memory100(to be described later) with respect to each of operations such as an erase operation, a rewrite (write) operation, and a read operation in the flash memory100.

The RAM304is a volatile memory such as a DRAM and an SRAM. In the RAM304, various kinds of programs to operate the micro controller100for example are expanded. The CPU301executes the expanded program, to realize various kinds of function in the program. In the RAM304, various kinds of data handled by the CPU301are stored temporarily.

The bus interface305couples the high-speed bus311and the peripheral bus312, and performs data input/output among each of the units coupled via the different buses. For example, the CPU301and the PLL306are coupled via the bus interface305, and a clock signal outputted from the PLL306is inputted into the CPU301. The CPU301is coupled to the temperature sensor307via the bus interface305, and temperature data (for example, a value of resistance) outputted from, the temperature sensor307is inputted into the CPU301. The CPU301is coupled to the timer308via the bus interface305, and time data outputted from the timer308is inputted into the CPU301. The CPU301is coupled to the ports309and310via the bus interface305, data to be inputted into the external device is outputted from, the CPU301to the ports309and310, and data outputted from the external device is inputted into the CPU301.

The PLL306is a phase-locked loop having a crystal oscillator for example. The PLL306is coupled to an XTAL terminal on the input side, and an EXTAL terminal on the output side. The PLL306generates a clock signal of a predetermined frequency based on a signal inputted from the XTAL terminal. Alternatively, the PLL306generates multiple clock signals having respectively different frequencies, based on a signal inputted from the XTAL terminal. The generated clock signal is inputted into each unit of the micro controller300via the peripheral bus312.

The temperature sensor307measures the temperature of the micro controller300. For example, the temperature sensor307is comprised of a resistor made from metal for example, and outputs to the CPU301a value of resistance as the temperature data.

The timer308measures a time based on a clock generated inside the micro controller100or a clock inputted from the exterior. For example, the timer308measures the elapsed time from, a prescribed time of day based on the count, number of the clock and the frequency of the clock. The timer308outputs to the CPU301the measured elapsed time as the time data, for example.

The ports309and310are external interfaces to couple the micro controller100with an external device (not shown). Data input/output is performed between the micro controller300and the external device via the ports309and310. For example, the data outputted from the CPU301is inputted into the external device via the ports309and310. The data outputted from, the external device is inputted into the CPU301via the ports309and310.

The micro controller300is provided, with plural power supply terminals, and a high potential Vcc and a low potential Vss are supplied via the respective power supply terminal.

The micro controller300is also provided with a standby terminal into which a standby signal STBY is inputted, and a reset terminal into which a reset signal RES is inputted. When the standby signal STBY becomes effective, the micro controller300makes a transition to a standby state. When the reset signal RES becomes effective, the micro controller300is initialized.

FIG. 2illustrates an example of an address map in the micro controller. The address space of the micro controller300is comprised of an address map of the flash memory100, and an address map other than the flash memory100, as shown inFIG. 2for example.FIG. 2illustrates the case where the leading address of the micro controller300is equal to the leading address of the flash memory100. In this case, the space from the leading address of the flash memory100, i.e., the leading address of the micro controller300, to the final address of the flash memory300is the address space of the flash memory100, and the space from the next address of the final address of the flash memory100to the final address of the micro controller300is the address space of other memory than the flash memory100.

<A Configuration of the Flash Memory>

FIG. 3illustrates an example of the configuration of the flash memory according to Embodiment 1 of the present invention. As illustrated inFIG. 3, the flash memory100is typically comprised of a read system row selector101, an input clocked inverter102, an IO (input-output) circuit/power control circuit/register103, a power supply circuit104, a verification sense amplifier105, a rewrite column selector106, a write latch107, a memory array108, an output buffer109, a rewrite system, row selector110, and a controller120.

The read system row selector101selects a read system row (word) in the memory array108, based on the decoded result of the address signal inputted via the high-speed bus (also called an address bus)311.

The input clocked inverter102generates a signal to specify various kinds of timing in a write operation, an erase operation, and a read operation, for example, based on a signal inputted from the IO circuit/power control circuit/register103to be described later.

The IO circuit/power control circuit/register103controls the data input/output to and from, the peripheral bus312, in synchronization with a clock signal inputted via the peripheral bus312. The IO circuit/power control circuit/register103also controls the operation of the power supply circuit104to be described later. The IO circuit/power control circuit/register103also outputs write data inputted via the high-speed bus311to the write latch107. The IO circuit/power control circuit/register103also outputs write data inputted from the controller120(to be described later) to the write latch107.

The power supply circuit104generates several kinds of voltages to be used in the flash memory100. For example, the power supply circuit104generates the potential of each power supply, such as a high-potential-side power source Vdd and a low-potential-side power source Vss.

When performing the write operation to the memory array108, the verification sense amplifier105performs verification to confirm whether the write data and the written data are the same.

The rewrite column selector106selects a rewrite column (common bit line) at the time of performing a write operation to the memory array108, based on the signal generated by the input clocked inverter102, for example.

The write latch107holds temporarily the write data outputted from the IO circuit/power control circuit/register103. The write latch107outputs the write data currently held to a main bit line, based on the signal generated by the input clocked inverter102, for example.

The memory array108is comprised of an arrangement of multiple memory mats. The details of the memory array108will be described later.

The output buffer109outputs the data read from the memory array108to the CPU301, the DMAC302, and the RAM304for example, via the high-speed bus311. The output buffer109outputs the data read from the memory array108also to the controller120to be described later.

The rewrite system row selector110selects a rewrite system row (for example, a memory gate line) in the memory array108, based on the decoded result of the address signal inputted via the high-speed bus311.

The controller120compares the data read by the normal read (the first read operation) to be described later with the data read by a data 1 margin read (the second read operation) to be described later. When it is determined that the data read by the normal read and the data read by the data 1 margin read are different, the controller120performs a refresh operation in which the data stored in the memory cell140as a read target to be described later is rewritten to the memory cell140as the read target. When it is determined that the data read by the normal read and the data read by the data 1 margin read are the same, the controller120compares the data read by the normal read with the data read by a data 0 margin read (the third read operation) to be described later. When it is determined that the data read by the normal read is different from the data read by the data 0 margin read, the controller120performs the refresh operation described above.

Next, the memory array108is explained.FIG. 4illustrates an example of the configuration of a memory array according to Embodiment 1 of the present invention.FIG. 5is an enlarged drawing illustrating a part of the configuration of a memory mat according to Embodiment 1 of the present invention.FIG. 6is a sectional view illustrating an example of the configuration of a memory cell according to Embodiment 1 of the present invention.

The memory array108includes multiple memory mats mat, as illustrated inFIG. 4. As illustrated inFIG. 5, in the memory mat mat, multiple memory cells140are arranged in a matrix in the column direction (the second direction) and the row direction (the first direction), and multiple bit lines151(151j,151k) are provided for every memory cells140for one column arranged in the column direction.

The sense amplifier SA is provided for every pair of memory mats mat, as illustrated inFIG. 4. The bit line151(151j,151k) of each memory mat mat is coupled to the input terminal of the sense amplifier SA via a read memory cell selecting-switching element180(180j,180k), as illustrated inFIG. 3. The read memory cell selecting-switching element180(180j,180k) is comprised of a MOS (metal-oxide-semiconductor) transistor, for example. The gate of the read memory cell selecting-switching element180(180j,180k) is coupled to the memory cell selecting line181(181j,181k). The memory cell selecting line181(181j,181k) is coupled to the read system row selector101.

As illustrated inFIG. 3, each bit line151(151j,151k) is coupled to a common bit line150common to multiple memory mats mat, via a bit line selecting-switching element170(170j,170k). The bit line selecting-switching element170(170j,170k) is comprised of a MOS transistor, for example. A gate of the bit line selecting-switching element170(170j,170k) is coupled to a bit line selecting line171(171j,171k), which is further coupled to the rewrite system row selector110, for example.

A pair of the memory mats mat configure a hierarchy sense amplifier unit, as illustrated inFIG. 4. For example, a memory mat matj0and a memory mat matk0configure a hierarchy sense amplifier unit, and a sense amplifier SA0is provided between the memory mat matj0and the memory mat matk0, as illustrated inFIG. 4. A memory mat matj1and a memory mat matk1configure a hierarchy sense amplifier unit, and a sense amplifier SA1is provided between the memory mat matj1and the memory mat matk1, as illustrated inFIG. 4. A memory mat matj2and a memory mat matk2configure a hierarchy sense amplifier unit, and a sense amplifier SA2is provided between the memory mat matj2and the memory mat matk2, as illustrated inFIG. 4. A memory mat matj3and a memory mat matk3configure a hierarchy sense amplifier unit, and a sense amplifier SA3is provided between the memory mat matj3and the memory mat matk3, as illustrated inFIG. 4. Here, the example is illustrated for the configuration in which eight memory mats matj0to matj3and matkO to matk3, and four sense amplifiers SA0to SA3corresponding to these memory mats mat are provided. However, the configuration is not restricted to one described above.

In this way, in the present embodiment, the memory array108is divided into plural (for example, four) hierarchy sense amplifier units, and a write operation, an erase operation, and a read operation to be described later are performed in the selected hierarchy sense amplifier unit.

It is preferable that the memory cells140for one line arranged in the column direction in each memory mat mat are the same in number. According to the present setting, it is possible to suppress the variations in wiring load for every bit line151(151j,151k); accordingly, it is possible to suppress occurrence of errors at the time when the sense amplifier SA reads the data.

<A Configuration of the Memory Cell>

The memory cell140includes a selection transistor141and a memory transistor142, as illustrated inFIG. 5andFIG. 6. For example, as illustrated inFIG. 6, a WELL region140gcommon to the memory cells140is formed over a semiconductor substrate140a,and the selection transistor141and the memory transistor142are formed over the WELL region140g.The selection transistor141is comprised of a MOS transistor, for example. Specifically, as illustrated inFIG. 6, the selection transistor141has the configuration in which a gate oxide layer (oxide)141band a control gate (metal)141care laminated over the WELL region140gof the semiconductor substrate (semiconductor)140a.

The memory transistor142is an MONOS (metal-oxide-nitride-oxide-silicon) type transistor, for example. As illustrated inFIG. 6, the memory transistor142has a structure in the area near a source142f,in which an oxide layer (oxide)142b,a nitride layer (nitride)142c,an oxide layer (oxide)142d,and a memory gate (metal)142eare laminated over the WELL region140gof the semiconductor substrate (semiconductor)140a.

Near the boundary of the selection transistor141and the memory transistor142, the oxide layer (oxide)142b,the nitride layer (nitride)142c,and the oxide layer (oxide)142dare extended to the perpendicular upper part so as to split the control gate141cand the memory gate142e.In this way, the memory cell140has the MONOS structure of a split gate type in which the control gate141cand the memory gate142eare split. The nitride layer142cis sandwiched by the oxide layers142band142das insulating layers, and acts as a charge capture layer insulated electrically. That is, the memory cell140is formed by the charge capture-type memory system.

A drain141dof the selection transistor141is coupled to the bit line151(151j,151k), as illustrated inFIG. 5. The control gate141cof the selection transistor141is coupled to a word line152, as illustrated inFIG. 5. The word line152is provided for every row of the memory mat108. That is, the word line152is coupled to the memory cells140arranged in the row direction (the first direction). The word line152is coupled to the read system row selector101, as illustrated inFIG. 3. The source142fof the memory transistor142is coupled to a source line153common to the memory cells140, as illustrated inFIG. 5. The memory gate142eof the memory transistor142is coupled to a memory gate line154, as illustrated inFIG. 5. The memory gate line154is provided for every row of the memory mat108. That is, the memory gate line154is coupled to the memory cells140arranged in the row direction (the first direction). The memory gate line154is coupled to the rewrite system row selector110, as illustrated inFIG. 3.

FIG. 7AandFIG. 7Billustrate an example of the voltages applied to the memory cell in each operation.FIG. 7AandFIG. 7Billustrate voltages applied to the bit line151, the control gate141c,the memory gate142e,the source line153, and the WELL region140g,in the write operation, the erase operation, and the read operation.FIG. 7Aillustrates the case where the erase operation is performed by the method called BTBTHH (Band-to-band Tunneling Hot Hole) to be described later. According toFIG. 7Afor example, at the time of the write operation, a voltage of 0V is applied to the bit line151, a voltage of 1.5V is applied to the control gate141c,a voltage of 10V is applied to the memory gate142e,a voltage of 6V is applied to the source line153, and a voltage of 0V is applied to the WELL region140g.At the time of the write operation, a hot electron (electron) of high efficiency is injected into the nitride layer142cby the method called SSI (Source Side Injection), for example. The memory cell140to which the write operation has been performed stores data “0.”

For example, at the time of the erase operation, the bit line151is set at high impedance, a voltage of 1.5V is applied to the control gate141c,a voltage of −10V is applied to the memory gate142e,a voltage of 6V is applied to the source line153, and a voltage of 0V is applied to the WELL region140g.The erase operation is performed in units of blocks including the plural memory cells140, for example. At the time of the erase operation, a hot hole (hole) is injected into the nitride layer142cby the BTBTHH method, for example. The memory cell140to which the erase operation has been performed stores data “1.”

For example, at the time of the read operation, a voltage of 1.5V is applied to the bit line151, a voltage of 1.5V is applied to the control gate141c,a voltage of 0V is applied to the memory gate142e,a voltage of 0V is applied to the source line153, and a voltage of 0V is applied to the WELL region140g.

FIG. 7Billustrates the case where the erase operation is performed by an FN tunnel system to be described later. According toFIG. 7B, the potentials applied to each part in the write operation and the read operation are the same as inFIG. 7A. Accordingly, the detailed explanation thereof is omitted. At the time of the erase operation, for example, the bit line151is set at high impedance, a voltage of 1.5V is applied to the control gate141c,a voltage of 14V is applied to the memory gate142e,a voltage of 0V is applied to the source line153, and a voltage of 0V is applied to the WELL region140g.The erase operation is performed in units of blocks including the plural memory cells140, for example. At the time of the erase operation, a hole is injected into the nitride layer142cby the tunnel phenomenon from the memory gate142eaccording to the FN tunnel system, for example. The memory cell140to which the erase operation has been performed stores data “1.”

FIG. 8illustrates the outline of the threshold voltage of the memory cell in a write state and an erase state. In the memory cell140, the threshold voltage of the memory transistor142is changed by injecting a charge into the nitride layer142c.For example, the threshold voltage of the memory transistor142in the write state in which an electron has been injected into the nitride layer142cbecomes higher than the threshold voltage in the neutral state in which neither an electron nor a hole exists in the nitride layer142c,as illustrated inFIG. 8. As compared with this, the threshold voltage of the memory transistor142in the erase state in which the hole has been injected into the nitride layer142cbecomes lower than the threshold voltage in the neutral state, as illustrated inFIG. 8.

FIG. 9illustrates the outline of data holding characteristics of the flash memory.FIG. 10AandFIG. 10Billustrate the situation of degradation of the data holding characteristics. In the memory cell140, the threshold voltage is varied as time passes after data is rewritten. For example, in the memory cell140in the erase state storing data “1”, the threshold voltage rises gradually as time passes after the rewrite of data, as illustrated inFIG. 9. In the memory cell140in the write state storing data “0”, the threshold voltage falls gradually as time passes after the rewrite of data, as illustrated inFIG. 9. In this way, in the memory cell140, when time passes after the rewrite of data, the data holding characteristics are degraded.

In the memory cell140, the data holding characteristics are degraded also by repeating the rewrite of data. Specifically, in the memory cell140, the rewrite of data is performed by repeating the electron injection by the write operation and the hole injection by the erase operation. However, when the number of times of rewriting increases, the oxide layers142band142dare degraded, and the ability of the nitride layer142cto trap an electron and a hole is degraded.

When the erase operation is performed according to the above-described BTBTHH method, the degradation of the oxide layer142bis great, and as illustrated inFIG. 10A, for example, an electron and a hole escape from the nitride layer142cmainly via the oxide layer142b.When the erase operation is performed according to the above-described FN tunnel system, the degradation of the oxide layer142dis great, and as illustrated inFIG. 10B, for example, an electron and a hole escape from, the nitride layer142cmainly via the oxide layer142d.

Then, as illustrated inFIG. 9, even if the erase operation is performed, the threshold, voltage in the memory cell140to which many number of times of rewriting is performed becomes higher than in the memory cell140to which few number of times of rewriting is performed. As illustrated inFIG. 9, even if the write operation is performed, the threshold voltage in the memory cell140to which many number of times of rewriting is performed becomes lower than in the memory cell140to which few number of times of rewriting is performed. In this way, when the number of times of rewriting increases, the data holding characteristics of the memory cell140are degraded.

The degradation of such data holding characteristics is remarkable in the memory cell140holding data “1”, as illustrated inFIG. 9. The degradation of the data holding characteristics is remarkable particularly when the flash memory100is placed under hot environments.

FIG. 11illustrates an example of the circuit configuration of the sense amplifier and the periphery thereof. The sense amplifier SA is coupled, at the input terminals thereof, to a pair of bit lines151(151j,151k) that are coupled to the mutually different memory cells140. The sense amplifier SA reads data stored in the memory cell140as the read target, based on the potential of one of the bit lines151(for example, the bit line151j) and the potential of the other of the bit lines151(for example, the bit line151k), coupled to the memory cell140as the read target. For example, the sense amplifier SA reads the data of the memory cell140as the read target, based on the difference of the potential of one of the bit lines151jand the potential of the other of the bit lines151k.

As illustrated inFIG. 11, MOS transistors (for example, p-channel MOS transistors) M11, M12, and M13for precharge are coupled to the bit lines151jand151k.The bit line151jis coupled to a high-potential-side power source Vdd via the MOS transistor M11. The bit line151kis coupled to the high-potential-side power source Vdd via the MOS transistor M13. The bit line151jand the bit line151kare mutually coupled via the MOS transistor M12.

When performing the read operation, the bit lines151jand151kare precharged via the MOS transistors M11, M12, and M13. Specifically, when a precharge signal pen of a low level is inputted into gate electrodes of the MOS transistors M11, M12, and M13, these MOS transistors M11, M12, and M13are turned on, and precharge is performed to the bit lines151jand151k.

A bit line potential controller190to adjust the potential of the bit line151(151j,151k) is coupled to the bit line151(151j,151k). The bit line potential controller190includes a potential drawing-out unit191and a reference potential generator192.

The potential drawing-out unit191includes MOS transistors M14, M16, and M15. The bit line151jis coupled to a drain of the reference MOS transistor (for example, an n-channel MOS transistor) M15via the MOS transistor (for example, a p-channel MOS transistor) M14.

The bit line151kis coupled to the drain of the MOS transistor M15via the MOS transistor (for example, a p-channel MOS transistor) M16. A source of the MOS transistor M15is coupled to the low-potential-side power source Vss,

The operation of the MOS transistor M14is controlled by a potential drawing-out switching signal refdcjn as illustrated inFIG. 11. The operation of the MOS transistor M16is controlled by a potential drawing-out switching signal refdckn as illustrated inFIG. 11. The operation of the MOS transistor M15is controlled by a reference signal urefmosg_s as illustrated inFIG. 11. The reference potential Vref of the reference signal urefmosg_s is specified in the reference potential generator192to be described later.

As illustrated inFIG. 11, the MOS transistors M1, M2, and M3are couples in series. A source of the MOS transistor M1is coupled to the high-potential-side power source Vdd, and a source of the MOS transistor M3is coupled to the low-potential-side power source Vss. A gate electrode of the MOS transistor M2is coupled to a drain of the MOS transistor M3. A reference current trimming potential is supplied to a gate electrode of the MOS transistor M3. An electric current flowing through the MOS transistors M2and M3is specified by the reference current trimming potential; accordingly, a trimming potential Vtrim of a wiring that couples a gate electrode of the MOS transistor M2and a drain of the MOS transistor M3is specified.

As illustrated inFIG. 11, the MOS transistors M4and M5are coupled in series. The MOS transistors M7and M8are coupled in series. The MOS transistors M9and M10are coupled in series. A gate electrode of the MOS transistor M4is coupled to the low-potential-side power source Vss. A reference potential switching signal S1from the register REG is inputted into a gate electrode of the MOS transistor M7, and a reference potential switching signal S0from the register REG is inputted into a gate electrode of the MOS transistor M9.

The register REG has a 2-bit configuration corresponding to the MOS transistors M7and M9, for example. The MOS transistors M7and M9are individually turned on and off by the reference potential switching signals S0and S1outputted from, the register REG.

Gate electrodes of the MOS transistors M5, M8, and M10are coupled to the gate electrode and the drain of the MOS transistor M2and the drain of the MOS transistor M3. Drains of the MOS transistors M5, M8, and M10are coupled to a drain of the MOS transistor M6. A source of the MOS transistor M6is coupled to the low-potential-side power source Vss. The drains of the MOS transistors M5, M8, and M10and the drain of the MOS transistor M6are coupled to a gate electrode of the MOS transistor M15. The reference potential generator192generates the reference potential Vref to be inputted into the gate electrode of the MOS transistor M15, based on the trimming potential Vtrim inputted into the gate electrodes of the MOS transistors M5, M8, and M10, and the reference potential switching signals S0and S1outputted from, the register REG.

FIG. 12illustrates a list of register outputs at the time of each read operation according to Embodiment 1 of the present invention.FIG. 13A,FIG. 13B, andFIG. 13Cillustrate respectively the potential change of a bit line at the time of each read operation. In the present embodiment, in order to determine whether the refresh operation to be described later is performed, three kinds of read operations called a normal read (the first read operation), a data 1 margin read (the second read operation), and a data 0 margin read (the third read operation) are performed. In the following, the explanation is made assuming that the memory cell140coupled to the bit line151jis the read target memory cell. That is, the bit line151jis on the data side, and the bit line151kis on the reference side. Consequently, at the time of the read, operation, in the potential drawing-out unit191, a signal refdcjn of a high level is inputted into the gate electrode of the MOS transistor M14, and a signal refdckn of a low level is inputted, into the gate electrode of the MOS transistor M16on the reference side.

The normal read is the operation performed, by the controller120in which the memory cell140as the read, target is made to draw out the potential of the bit line (one of the bit lines)151j,the bit line potential controller190is made to draw out the potential of the bit line (the other of the bit lines) 151kat the first speed, and concurrently, the sense amplifier SA is made to read the data.

Specifically, in the normal read, the reference potential switching signal SI from the register REG is set to a low level “L”, and the reference potential switching signal S0is set to a high level “H.” At this time, in the reference potential generator192, the MOS transistors M4and M7are turned on, and an electric current (middle current) is supplied from the high-potential-side power source Vdd, via the path of the MOS transistors M4and M5and the path of the MOS transistors M7and M8. The reference potential Vref in the normal read is set at the halfway potential (middle potential) of the reference potential Vref in each of the data 1 margin read and the data 0 margin read to be described later. For example, the reference potential Vref at the time of the normal read is set so that the electric current flowing through the MOS transistors M14and M16of the potential drawing-out unit191is greater than the electric current flowing through the memory cell140that stores data “0”, and smaller than the electric current flowing through the memory cell140that stores data “1.”

In the normal read, the reference current Iref flows through the MOS transistors M16and M15from, the bit line151kon the reference side to the low-potential-side power sources Vss. Accordingly, the potential of the bit line151kis gradually drawn out at the predetermined speed (the first speed) and falls, as illustrated inFIG. 13A.

When the memory cell140as the read target is in the erase state storing data “1”, for example, the threshold voltage of the memory transistor142is low as described above. Accordingly, an electric current flows through the memory cell140from the bit line151jon the data side toward the source line153on the low voltage side. Then, as illustrated inFIG. 13A, the potential of the bit line151jon the data side is drawn out at a speed faster than the speed in the bit line151kon the reference side, and falls. Consequently, the potential of the bit line151jon the data side becomes lower than the potential of the bit line151kon the reference side, and the sense amplifier SA reads data “1” based on the difference of the potential of the bit line151jand the potential of the bit line151k.

As opposed to this, when the memory cell140is in the write state storing data “0”, for example, the threshold voltage of the memory transistor142is high. Accordingly, the electric current flowing through the memory cell140from the bit line151jon the data side toward the source line of the low voltage Vss is small as compared with the case of storing data “1.” Consequently, the potential of the bit line151jon the data side becomes higher than the potential of the bit line151kon the reference side, and the sense amplifier SA reads data “0” from the memory cell140.

The data 1 margin read is the operation performed by the controller120in which the memory cell140as the read target is made to draw out the potential of the bit line (one of the bit lines)151j,the bit line potential controller190is made to draw out the potential of the bit line (the other of the bit lines) 151kat a second speed faster than the first speed, and concurrently, the sense amplifier SA is made to read the data. The data 1 margin read is performed in order to detect a memory cell140of which the data holding characteristics of data “1” has been degraded.

Specifically, in the data 1 margin read, the reference potential switching signals S1and S0from the register REG are both set at a low level “L.” At this time, in the reference potential generator192, the MOS transistors M4, M7, and M9are turned on, and an electric current (high current) is supplied from, the high-potential-side power source Vdd, via the path, of the MOS transistors M4and M5, the path of the MOS transistors M7and M8, and the path of the MOS transistors M9and M10. Consequently, the reference potential Vref in the data 1 margin read is set at the potential (high potential) higher than the reference potential Vref in the normal read. The reference potential Vref in the data 1 margin read is set so that the electric current flowing through the MOS transistors M14and M16of the potential drawing-out unit191becomes greater than the current in the normal read. For example, the reference potential Vref in the data 1 margin read is set up so that the electric current flowing through the MOS transistors M14and M16of the potential drawing-out unit191is greater than the electric current flowing through the memory cell140storing data “1” of which the degradation of the data holding characteristics has advanced, and smaller than the electric current flowing through the memory cell140storing data “1” of which the degradation of the data holding characteristics has not advanced.

In the data 1 margin read, the predetermined reference current Iref greater than the reference current in the normal read flows through the MOS transistor M16, from the bit line 151ktoward the low-potential-side power sources Vss. Accordingly, the potential of the bit line151kis drawn out at a speed (the second speed) faster than the speed in the normal read and falls, as illustrated inFIG. 13B.

When the degradation of the data holding characteristics of the memory cell140storing data “1” has advanced and the threshold voltage of the memory transistor142has risen, the electric current flowing through the memory cell140from the bit line151jon the data side toward the source line153of the low voltage Vss decreases, as compared with the memory cell140of which the degradation of the data holding characteristics has not advanced. Therefore, as illustrated inFIG. 13B, the potential of the bit line151jis drawn out at a speed slower than the speed in the memory cell140of which the degradation of the data holding characteristics has not advanced, and falls. Then, the falling speed (the second speed) of the potential of the bit line151kon the reference side becomes faster than the falling speed of the potential of the bit line151jon the data side. Consequently, the potential of the bit line151jbecomes higher than the potential of the bit line151k,and the sense amplifier SA reads data “0” from the memory cell140storing data “1”.

In this way, in the data 1 margin read, the sense amplifier SA reads wrong data “0” from the memory cell140storing data “1”; accordingly, the memory cell140of which the degradation of the data holding characteristics of data “1” has advanced is detected.

As compared with this, when the memory cell140is in the write state storing data “0”, for example, the potential of the bit line151jdoes not become lower than the potential of the bit line151keven when the data 1 margin read is preformed; accordingly, the sense amplifier SA never reads out the wrong data.

The data 0 margin read is the operation performed by the controller120in which the memory cell140as the read target is made to draw out the potential of the bit line (one of the bit lines)151j,the bit line potential controller190is made to draw out the potential of the bit line (the other of the bit lines) 151kat a third speed slower than the first speed, and concurrently, the sense amplifier SA is made to read the data. The data 0 margin read is performed in order to detect, a memory cell140of which the data holding characteristics of data “0” has been degraded.

Specifically, in the data 0 margin read, the reference potential switching signals S1and S0from the register REG are both set at a nigh level “H.” At this time, in the reference potential generator192, the MOS transistor M4alone is turned on, and an electric current (high current) is supplied from the high-potential-side power source Vdd, via the path of the MOS transistors M4and M5. Consequently, the reference potential Vref in the data 0 margin read is set at the potential (low potential) lower than the reference potential Vref in the normal read. The reference potential Vref in the data 0 margin read is set so that the electric current flowing through the MOS transistors M14and M16of the potential drawing-out unit191becomes smaller than the current in the normal read. For example, the reference potential Vref in the data 0 margin read is set up so that the electric current flowing through the MOS transistors M14and M16of the potential drawing-out unit191is smaller than the electric current flowing through the memory cell140storing data “0” of which the degradation of the data holding characteristics has advanced, and greater than the electric current flowing through the memory cell140storing data “0” of which the degradation of the data holding characteristics has not advanced.

In the data 0 margin read, the predetermined reference current. Iref smaller than the reference current in the normal read flows through the MOS transistor M16, from the bit line151ktoward the low-potential-side power sources Vss. Accordingly, the potential of the bit line151kis drawn out at a speed (the third speed) slower than the speed in the normal read and falls, as illustrated inFIG. 13C.

When the degradation of the data holding characteristics of the memory cell140storing data “0” has advanced and the threshold voltage of the memory transistor142has fallen, the electric current flowing through the memory cell140from the bit line151jon the data side toward the source line153of the low voltage Vss increases, as compared with the memory cell140of which the degradation of the data holding characteristics has not advanced. Therefore, as illustrated inFIG. 13C, the potential of the bit line151jis drawn out at a speed faster than the speed in the memory cell140of which the degradation of the data holding characteristics has not advanced, and falls. Then, the falling speed (the second speed) of the potential of the bit line151kon the reference side becomes slower than the falling speed of the potential of the bit line151jon the data side. Consequently, the potential of the bit line151jbecomes lower than the potential of the bit line151k,and the sense amplifier SA reads data “1” from the memory cell140storing data “0.”

In this way, in the data 0 margin read, the sense amplifier SA reads wrong data “1” from the memory cell140storing data “0”; accordingly, the memory cell140of which the degradation of the data holding characteristics of data “0” has advanced is detected.

As compared with this, when the memory cell140is in the write state storing data “1”, for example, the potential of the bit line151jdoes not become higher than the potential of the bit line151keven when the data 0 margin read is preformed; accordingly, the sense amplifier SA never reads out the wrong data.

<A Refreshing Method of the Flash Memory>

Next, a refreshing method of the flash memory100is explained. In the present embodiment, a series of processing regarding the refresh operation is performed by detecting the memory cell140storing data “1” of which the degradation of the data holding characteristics is significant.FIG. 14is a flow chart illustrating the refreshing method of the flash memory according to Embodiment 1 of the present invention. In the present embodiment, as illustrated inFIG. 14, the refresh operation of the flash memory is performed by Step S1001to Step S1052.

The refresh operation is performed at the time of power-on, restart, power-off of the micro controller300, or in accordance with user's instructions.

At first, at Step S1001, the leading address when performing the normal read and the data 1 margin read to be described later is set up. The leading address may be the leading address of the address space of the nonvolatile memory or may be the leading address of an erasing unit. For example, the controller120illustrated inFIG. 3sets the leading address of the flash memory100illustrated inFIG. 2as the leading address at the time of performing the read operation. The controller120outputs the set leading address to the read system row selector101illustrated inFIG. 3, for example. The read system row selector101selects the word line152based on the leading address inputted from the controller120, and selects the memory cell140coupled to the selected word line152as the memory cell140as the read target.

Step S1010is a first read step at which the controller120performs the normal read. Specifically, the sense amplifier SA performs the normal read to the memory cell140as the read target, selected at Step S1001. The sense amplifier SA outputs the read data to the output buffer109illustrated inFIG. 3, and the output buffer109amplifies the data inputted from the sense amplifier SA, and outputs the amplified data to the controller120. The controller120instructs the data holding unit (not shown) to hold the data that is inputted from the output buffer109. Alternatively, the controller120may output the data inputted from the output buffer109to the RAM304via the high-speed bus311illustrated inFIG. 3, and may instruct the RAM304to hold the data.

Step S1020is a second read step at which the controller120performs the data 1 margin read. Specifically, the sense amplifier SA performs the data 1 margin read to the memory cell140to which the normal read has been performed at the immediately preceding step S1010. The sense amplifier SA outputs the read data to the output buffer109, and the output buffer109amplifies the data inputted from the sense amplifier SA, and outputs the amplified data to the controller120. The controller120instructs the data holding unit (not shown) to hold the data that is inputted from the output buffer109. Alternatively, the controller120may output the data inputted from the output buffer109to the RAM304via the high-speed bus311, and may instruct the RAM304to hold the data.

Step S1030is a first data comparison step (the first data comparison operation) in which the controller120compares the data read at the first read step S1010with the data read at the second read step S1020. Specifically, the controller120compares the data read at the first read step S1010and held in the data holding unit (not shown) with the data read at the second read step S1020. Alternatively, the controller120reads and compares the data read at the first read step S1010and held in the RAM304and the data read at the second read step S1020and held in the RAM304. The controller120compares these pieces of data to detect the memory cell140of which the degradation of the data holding characteristics of data “1” has advanced.

At Step S1030, when the controller120determines that the data read at the first read step S1010and the data read at the second read step S1020are different from each other (No), Step S1040is performed.

Step S1040is a first refresh step in which the controller120performs the first refresh operation by rewriting the data stored in the memory cell140as the read target to the memory cell140as the read target. For example, the controller120outputs the data read by the normal read to the IO circuit/power control circuit/register103illustrated inFIG. 3, as the write data. The IO circuit/power control circuit/register103outputs the inputted write data to the write latch107for example, to hold it.

The controller120outputs, to the rewrite system row selector110illustrated inFIG. 3, the memory gate selecting signal to select the memory gate line154that is coupled to the memory cell140to which the data 1 margin read has been performed at the immediately preceding step S1020. The rewrite system row selector110selects the memory gate line154coupled to the memory cell140to which the data 1 margin read has been performed, that is, the memory cell140to which the refresh operation is to be performed, based on the inputted memory gate selecting signal. Then, the controller120applies the potential for the write operation illustrated inFIG. 7AandFIG. 7Bto each part of the memory cell140to which the refresh operation is to be performed. Then, the write latch107outputs the write data held to the common bit line150, based on a signal outputted from the input clocked inverter102, for example. The write data outputted to the common bit line150is inputted and written in the memory cell140via the bit line selecting-switching element170and the bit line151. In this way, the refresh operation is performed every word line152arranged in the row direction in the memory array108, for example.

When the first refresh operation has been performed, the flow shifts to Step S1001, and the detection of the memory cell140of which the degradation of the data holding characteristics has advanced is performed again from the leading address. The leading address may be the leading address of the address space of the nonvolatile memory or may be the leading address of an erasing unit. That is, after performing the first refresh operation, the controller120performs to the memory cell140as the read target, the first read step S1010(the first read operation), the second read step S1020(the second read operation), and the first data comparison step S1030(the first data comparison operation).

At step S1030, when the controller120determines that the data read at the first read step S1010and the data read at the second read step S1020are the same (Yes), Step S1051is performed.

At step S1051, the address is incremented. Specifically, the controller120sets up the new address for selecting the memory cell140as the next read target.

At Step S1052, it is determined whether the new address set up at Step S1051has exceeded the final address. For example, the controller120compares the address set up at Step S1051with the final address of the flash memory100illustrated inFIG. 2. When it is determined that the address set up at Step S1051does not exceed the final address of the flash memory100illustrated inFIG. 2for example, but is the address within the flash memory100(No), the flow shifts to Step S1010. Then, to the memory cell140as the read target selected by the new address, the detection and the refresh operation of the memory cell140of which the degradation of the data holding characteristics has advanced are performed. These processing is performed to all the memory cells140of the memory array108, and the detection and the refresh operation of the memory cell140of which the degradation of the data holding characteristics has advanced are performed.

As compared with this, when the controller120determines that the address set up at. Step S1051exceeds the final address of the flash memory100illustrated inFIG. 2, and becomes the address of the other memory than the flash memory100(Yes), it is determined that the detection and the refresh operation of the memory cell140of which the degradation of the data holding characteristics has advanced has been performed to all the memory cells140, and the series of processing regarding to the refresh operation is finished.

<The Effect by the Present Embodiment>

According to the present embodiment, the controller120performs the normal read (the first, read operation, the first read step S1010) and the data 1 margin read (the second read operation, the second, read step S1020) to the memory cell140as the read target, and compares the data read by the normal read and the data read by the data 1 margin read (the first data comparison operation, the first data comparison step S1030). When it is determined that the data read by the normal read and the data read by the data 1 margin read is different, the controller120performs the first refresh operation (the first refresh step S1040).

According to this configuration, it is possible to detect the memory cell140of which the degradation of the data holding characteristics of data “1” has advanced, by performing the data 1 margin read with the read conditions of data “1” severer than the normal read. Accordingly, the refresh operation can be performed at the appropriate time before a read error occurs. In addition, according to the present configuration, the reliability of the flash memory100enhances and the reliability of the micro controller300that mounts the flash memory100enhances.

Moreover, according to this configuration, the detection of the memory cell140of which the degradation of the data holding characteristics has advanced is performed, specializing to data “1” with greater degradation of the data holding characteristics than data “0.” Accordingly, it is possible to reduce the time necessary for the refresh.

Furthermore, according to the present embodiment, the flash memory includes the memory array108having multiple memory mats mat in which the memory cells140are arranged in a matrix. The bit lines151are provided for every memory mat mat, and each of the bit line151(151j,151k) is coupled to the common bit line150common to the multiple memory mats mat, via the bit line selecting-switching element170(170j,170k).

According to this configuration, it is possible to shorten the bit line151(151j,151k) coupled to the sense amplifier SA. Accordingly, the wiring load at the time of the read operation is reduced. Accordingly, the drawing out time of the potential from the bit line151(151j,151k) is shortened, and the reading time of the data by means of the sense amplifier SA is shortened. Accordingly, the time required for the refresh operation is shortened.

Moreover, according to the present embodiment, in the memory mat mat, multiple memory cells140are arranged in a matrix in the row direction (the first direction) and the column direction (the second direction). The bit line151(151j,151) is provided for every memory cells140for one line arranged in the column direction, and each bit line151(151j,151k) is coupled to the input terminal of the sense amplifier SA via the read memory cell selecting-switching element180(180j,180k).

According to this configuration, plural bit lines151(151j,151k) share the sense amplifier SA. Accordingly, the sense amplifier SA is reduced in number and the wiring structure around the sense amplifier SA is simplified. Accordingly, increase of the chip area of the flash memory100is suppressed.

Moreover, according to the present embodiment, the sense amplifier SA is provided for every pair of memory mats matj and matk, and the bit line151(151j,151k) of each memory mat is coupled to the input terminal of the sense amplifier SA.

According to this configuration, the input terminal of the sense amplifier SA is coupled to the bit line151(for example, the bit line151k) of the memory mat matj to which a non-read-target memory cell140belongs. Accordingly, the control on the reference side at the time of read is simplified and the load of each circuit including the controller120is reduced.

Moreover, according to this configuration, the variations in the wire length to the sense amplifier SA are suppressed, and the variations in wiring load for every bit line151(151j,151k) are suppressed. Accordingly, occurrence of the read error of the data due to the variations in wiring load is suppressed. Accordingly, the reliability of the flash memory100is enhanced.

Moreover, according to the present embodiment, the memory cells for one line arranged in the column direction (the second direction) in each memory mat mat (matj, matk) are same in number.

According to this configuration, the length of each bit line151(151j,151k) becomes almost equal. Accordingly, the variations in wiring load for every bit line151(151j,151k) are suppressed. Accordingly, occurrence of the read error of the data due to the variations in wiring load is suppressed. Moreover, the reliability of the flash memory100is enhanced.

Moreover, according to the present embodiment, the controller120performs the first refresh operation every word line152.

According to this configuration, the number of the memory cells140to which the refresh operation is performed at a time is reduced. Accordingly, the time required for the first refresh operation is shortened. Moreover, according to this configuration, no refresh operation is performed if the memory cell140of which the degradation of the data holding characteristics has advanced is not coupled to one word line152. Accordingly, the power consumption for the refresh operation is reduced.

Moreover, according to the present embodiment, after performing the first refresh operation in the first refresh step S1040, the controller120performs the first read step S1010, the second read step S1020, and the first data comparison step S1030, to the memory cell140as the read target.

According to this configuration, the memory cell140to which the refresh operation has been performed is reconfirmed about whether the degradation of the data holding characteristics has advanced. Accordingly, the reliability of the flash memory100is enhanced, and the reliability of the micro controller300that mounts the flash memory100is enhanced.

Next, Embodiment 2 of the present invention is explained. The present embodiment explains the processing related to the refresh operation in which the data 0 margin read is also performed in addition to the data 1 margin read. In the following, the explanation about the contents overlapping with Embodiment 1 described above is omitted in principle.

FIG. 15is a flow chart illustrating a refreshing method of a flash memory according to Embodiment 2 of the present invention. In the present embodiment, as illustrated inFIG. 15, the refresh operation of the flash memory is performed by Step S1001to Step S1052, and Step S2060to Step S2080.

At Step S1030, when the controller120determines that the data read at the first read step S1010and the data read at the second read step S1020are the same (Yes), Step S2060is performed.

Step S2060is a third read step at which the controller120performs the data 0 margin read. Specifically, the sense amplifier SA performs the data 0 margin read to the memory cell140to which the read operation has been performed at Step S1010and Step S1020. The sense amplifier SA outputs the read data to the output buffer109, and the output buffer109amplifies the data inputted from the sense amplifier SA, and outputs the amplified data to the controller120. The controller120instructs the data holding unit (not shown) to hold the data that is inputted from the output buffer109. Alternatively, the controller120may output the data inputted from the output buffer to the RAM304via the high-speed bus311, and may instruct the RAM304to hold the data.

Step S2070is a second data comparison step (the second data comparison operation) in which the controller120compares the data read at the first read step S1010with the data read at the third read step S2060. Specifically, the controller120compares the data read at the third read step S2060with the data read at the first read step S1010and held in a data holding unit (not shown). Alternatively, the controller120reads and compares the data read at the first read step S1010and held in the RAM304and the data read at the third read step S2060and held in the RAM304. The controller120detects the memory cell140of which the degradation of the data holding characteristics of data “0” has advanced by comparing these pieces of data.

At Step S2070, when the controller120determines that the data read at the first read step S1010and the data read at the third read step S2060are different from each other (No), Step S2080is performed. Step S2080is the first refresh step. At Step S2080, the controller120performs the same processing as at the first refresh step S1040described above; accordingly, the detailed explanation thereof is omitted.

When the first refresh operation is performed, the flow shifts to Step S1001, and the detection of the memory cell140of which the degradation of the data holding characteristics has advanced is performed again from the leading address. The leading address may be the leading address of the address space of the nonvolatile memory or may be the leading address of an erasing unit. That is, after performing the refresh operation, the controller120performs, to the memory cell140as the read target, the first read step S1010(the first read operation), the second read step S1020(the second read operation), the first data comparison step S1030(the first data comparison operation), the third read step S2060(the third read operation), and the second data comparison step S2070(the second data comparison operation).

At Step S2070, when the controller120determines that the data read at the first read step S1010and the data read at the third read step S2060are the same (Yes), Step S1051and Step S1052are performed sequentially. The processing at Step S1051and Step S1052is already explained; accordingly, the detailed explanation thereof is omitted.

<The Effect by the Present Embodiment>

According to the present embodiment, in addition to the effect in the above-described embodiment, the following effects are obtained.

According to the present embodiment, when the controller120determines, in the first data comparison operation (the first data comparison step S1030), that the data read by the normal read (the first read operation, the first read step S1010) and the data read by the data 1 margin read (the second read operation, the second read step S1020) are the same, the controller120performs the data 0 margin read (the third read operation, the third read step S2060) to the memory cell140as the read target. Then, when the controller120compares the data read by the normal read with the data read by the data 0margin read (the second data comparison step S2070), and determines that the data read by the normal read and the data read by the data 0 margin read are different from each other, the controller120performs the first refresh operation (the first refresh step S2080).

According to this configuration, the controller120performs the data 1 margin read, and then performs the data 0margin read also. Accordingly, it is possible to enhance the accuracy of detecting the memory cell140of which the degradation of the data holding characteristics has advanced. Accordingly, the reliability of the flash memory100enhances and the reliability of the micro controller300that mounts the flash memory100enhances.

Furthermore, according to the present embodiment, after performing the first refresh operation (the first refresh step S2080), the controller120performs to the memory cell140as the read target to which the first refresh operation has been performed, the normal read (the first read operation, the first read step S1010), the data 1 margin read (the second read operation, the second read step S1020), the first data comparison operation (the first data comparison step S1030), the data 0 margin read (the third read operation, the third read step S2060), and the second data comparison operation (the second data comparison step S2070).

According to this configuration, also when the data 0margin read is performed, it is reconfirmed whether the degradation of the data holding characteristics has advanced, to the memory cell140to which the first refresh operation has been performed. Accordingly, the reliability of the flash memory100is further enhanced, and the reliability of the micro controller300that mounts the flash memory100is further enhanced.

Next, Embodiment 3 of the present invention is explained. The present embodiment explains a flash memory of a complementary system in which data is stored in a pair of memory cells. In the following, the explanation about the contents overlapping with Embodiment 1 and Embodiment 2 described above is omitted in principle.

<The Configuration of the Flash Memory>

FIG. 16illustrates an example of the configuration of the flash memory according to Embodiment 3 of the present invention.FIG. 17illustrates an example of the circuit configuration of a sense amplifier and the periphery thereof. As illustrated inFIG. 16, the flash memory100A is typically comprised of a read system, row selector101, an input clocked inverter102, an IO circuit/power control circuit/register103, a power supply circuit104, a verification sense amplifier105, a rewrite column selector106, a write latch107, a memory array108A, an output buffer109, a rewrite system row selector110, and a controller120.

In the flash, memory100A of the complementary system, data is stored by a pair of memory cells140(140p,140n) illustrated inFIG. 16. Specifically, the data is stored in one of the memory cells140pand the inverted data obtained by inverting the data in the other of the memory cells140n.In the following, the memory cell140pto store the data is also called a positive memory, and the memory cell140nto store the inverted data is called a negative memory.

In the memory array108A, the sense amplifier SA is provided for every pair of memory mats mat, as illustrated inFIG. 4, for example. A bit line151(for example,151jp,151jn,151kp,151kn) of each memory mat mat is coupled to the input terminal of the sense amplifier SA via the read memory cell selecting-switching element180(180jp,180jn,180kp,180kn), as illustrated inFIG. 16andFIG. 17. The read memory cell selecting-switching element180(180ip,180jn,180kp,180kn) is comprised of a MOS transistors, for example. Each gate of the read memory cell selecting-switching element180(180jp,180jn,180kp,180kn) is coupled respectively to the memory cell selecting line181(181jp,181jn,181kp,181kn). The memory cell selecting line181(181jp,181jn,181kp,and181kn) is coupled to the read system row selector101, for example.

The sense amplifier SA is coupled, at an input terminal, to a pair of bit lines coupled to the pair of the memory cells140(140p,140n). The pair of the memory cells140(140p,140n) are comprised of two memory cells140provided on the same word line152, as illustrated inFIG. 16for example. That is, the pair of the memory cells140(140p,140n) are provided for example in the same memory mat mat, and at the time of the read operation, the bit lines151jpand151jn(or the bit lines151kpand151kn) are coupled to the input terminals of the sense amplifier SA as the pair of bit lines, respectively. The sense amplifier SA reads the data stored in the pair of memory cells140(140p,140n), based on the potential of the bit line (one of the bit lines)151jpcoupled to the memory cell (one of the memory cells)140pand the potential of the bit line (the other of the bit lines)151jncoupled to the memory cell (the other of the memory cells)140n.

The bit line potential controller190A includes a potential drawing-out unit191. In the bit line potential controller190A, the reference potential generator192illustrated inFIG. 11is not provided. Therefore, as illustrated inFIG. 17, a reference signal urefmosg_s set at a predetermined potential is inputted into the gate electrode of the MOS transistor M15.

In the flash memory of the complementary system, the reason why the reference potential generator192is not provided in the bit line potential controller190is as follows. It is because, in the complementary system, the memory cell140(140p,140n) is coupled to each input terminal of the sense amplifier SA, and data can be read by making the memory cell140(140p,140n) draw out the potential of the bit lines151jp(151kp) and151jn(151kn).

FIG. 18A,FIG. 18B, andFIG. 18Cillustrate respectively the outline of the threshold voltage of the memory cell in an initialization state and a write state. In the initialization state before the write operation is performed, as illustrated inFIG. 18A, threshold voltages of the positive memory140pand the negative memory140nare both lower than the threshold voltage in a neutral state.

When data “1” is written in, the write operation is performed only to the negative memory140n.Therefore, the threshold voltage of the positive memory140pis lower than the threshold voltage in the neutral state, as illustrated inFIG. 18B. On the other hand, the threshold voltage of the negative memory140nis higher than the threshold voltage in the neutral state, as illustrated inFIG. 18B.

On the other hand, when data “0” is written, the write operation is performed only to the positive memory140p.Therefore, the threshold voltage of the positive memory140pis higher than the threshold voltage in the neutral state, as illustrated inFIG. 18C. On the other hand, the threshold voltage of the negative memory140nis lower than the threshold voltage in the neutral state, as illustrated inFIG. 18C.

In this way, as illustrated inFIG. 18BandFIG. 18C, in the complementary system, the memory cell140with the threshold voltage lower than the neutral state stores the “L” side data and the memory cell140with the threshold voltage higher than the neutral state stores the “H” side data. That is, when data “1” is stored, the positive memory140pstores the “L” side data, and the negative memory140nstores the “H” side data. On the other hand, when data “0” is stored, the positive memory140pstores the “H” side data, and the negative memory140nstores the “L” side data.

“L” here means the state where the threshold voltage of the memory cell140is lower than the neutral state, and the “L” side data means the data stored in the memory cell140of which the threshold voltage is lower than the neutral state. “H” here means the state where the threshold voltage of the memory cell140is higher than the neutral state, and the “H” side data means the data stored in the memory cell140of which the threshold voltage is higher than the neutral state.

Next, the read operation in the present embodiment is explained.FIG. 19illustrates the list of the potential applied to the potential drawing-out unit at the time of each read operation according to Embodiment 3 of the present invention.

In the present embodiment, in order to determine whether the refresh operation to be described later is performed, three kinds of read operations of the normal read (the fourth read operation), the data 1 margin read (the fifth read operation), and the data 0 margin read (the sixth read operation) are performed.

In the normal read, to a pair of the memory cells140as the read target, the controller120performs the operation in which the memory cell (one of the memory cells)140pis made to draw out the potential of the bit line (one of the bit lines)151jp(151kp), the memory cell (the other of the memory cells)140nis made to draw out the potential of the bit line (the other of the bit lines)151jn(151kn), and concurrently, the sense amplifier SA is made to read the data. Therefore, in the potential drawing-out unit191at the time of the normal read, as illustrated inFIG. 19, signals refdcjn and refdckn of a high level are inputted respectively into the gate electrodes of the MOS transistors M14and M16.

When a pair of the memory cells140as the read target store data “1”, for example, the positive memory140pstores the “L” side data, and the negative memory140nstores the “H” side data. At this time, the threshold voltage is low in the positive memory140p.Accordingly, an electric current flows through the memory cell140from, the bit line151jp(151kp) toward the source line153on the low voltage side. Then, the potential of the bit line151jp(151kp) is drawn out and falls. On the other hand, in the negative memory140n,the threshold voltage is high. Accordingly, an electric current flowing from the bit line151jn(151kn) toward the source line153is small as compared with the positive memory140p.Accordingly, the potential of the bit line151jn(151kn) is not drawn out and does not fall more than the potential of the bit line151jp(151kp). Consequently, the potential of the bit line151jp(151kp) becomes lower than the potential of the bit line151jn(151kn), and the sense amplifier SA reads data “1”, based on the difference of the potential of the bit line151jp(151kp) and the potential of the bit line151jn(151kn).

On the other hand, when a pair of memory cells140as the read target stores data “0”, for example, the positive memory140pstores the “H” side data, and the negative memory140nstores the “L” side data. At this time, the threshold voltage is low in the negative memory140n.Accordingly, an electric current flows through the memory cell140from the bit line151jn(151kn) toward the source line153on the low voltage side. Then, the potential of the bit line151jn(151kn) is drawn out and falls. On the other hand, in the positive memory140p,the threshold voltage is high. Accordingly, the electric current flowing from the bit line151jp(151kp) toward the source line153is small as compared with the negative memory140n.Accordingly, the potential of the bit line151jp(151kp) is not drawn out and does not fall more than the potential of the bit line151jn(151kn). Consequently, the potential of the bit line151jp(151kp) becomes higher than the potential of the bit line151jn(151kn), and the sense amplifier SA reads data “0”, based on the difference of the potential of the bit line151jp(151kp) and the potential of the bit line151jn(151kn).

In the data 1 margin read, to a pair of the memory cells140as the read target, the controller120performs the operation in which the memory cell (one of the memory cells)140pis made to draw out the potential of the bit line (one of the bit lines)151jp(151kp), the memory cell (the other of the memory cells)140nand the bit line potential controller190are made to draw out the potential of the bit line (the other of the bit lines)151jn(151kn), and concurrently, the sense amplifier SA is made to read the data. Therefore, in the potential drawing-out unit191at the time of the data 1 margin read, as illustrated inFIG. 19, the signal refdcjn of a high level is inputted into the gate electrode of the MOS transistor M14, and the signal refdckn of a low level is inputted into the gate electrode of the MOS transistor M16.

The potential of the reference signal urefmosg_s at the time of the data 1 margin read is set up so that for example, the electric current of the sum of the electric current flowing through the memory cell140(here the memory cell140n) storing the “H” side data and the electric current flowing through the MOS transistor M16of the potential drawing-out unit191is greater than the electric current flowing through the memory cell140(here the memory cell140p) storing the “L” side data of which the degradation of the data holding characteristics has advanced.

First, the explanation is made for the case where a pair of the memory cells140as the read target stores the data “1.” In the positive memory140p,the threshold voltage is low. Accordingly, an electric current flows through the memory cell140from the bit line151jp(151kp) toward the source line153on the low voltage side. Then, the potential of the bit line151jp(151kp) is drawn out and falls. On the other hand, in the negative memory140n,an electric current flows from the bit line151jn(151kn) toward the source line153. However, the threshold voltage of the negative memory140nis high. Accordingly, the electric current flowing from the bit line151jn(151kn) toward the source line153is small as compared with the positive memory140p.Then, an electric current flows from the bit line151jn(151kn) toward the low-potential-side power source Vss via the MOS transistor M16. Accordingly, in the bit line151jn(151kn), the potential is drawn out and falls.

When the degradation of the data holding characteristics of the positive memory140pstoring the “L” side data has advanced, the electric current flowing through the memory cell140from the bit line151jptoward the source line153of the low voltage Vss decreases, as compared with the case where the degradation of the data holding characteristics has not advanced. Accordingly, the falling speed of the potential of the bit line151jp(151kp) becomes slower than the falling speed of the potential of the bit line151jn(151kn). Then, the potential of the bit line151jp(151kp) becomes higher than the potential of the bit line151jn(151kn), and the sense amplifier SA reads data “0” from a pair of the memory cells140storing data “1.”

In this way, in the data 1 margin read, the sense amplifier SA reads wrong data “0” from a pair of the memory cells140storing data “1”; accordingly, a pair of the memory cells140of which the degradation of the data holding characteristics of data “1” has advanced is detected.

Then, when a pair of the memory cells140store data “0”, for example, the potential of the bit line151jp(151kp) does not become lower than the potential of the bit line151jn(151kn) even when the data 1 margin read is performed; accordingly, the sense amplifier SA never reads out the wrong data.

In the data 0 margin read, to a pair of the memory cells140as the read target, the controller120performs the operation in which the memory cell (one of the memory cells)140pand the bit line potential controller190are made to draw out the potential of the bit line (one of the bit lines)151jp(151kp), the memory cell (the other of the memory cells)140nis made to draw out the potential of the bit line (the other of the bit lines)151jn(151kn), and concurrently, the sense amplifier SA is made to read the data. Therefore, in the potential drawing-out unit191at the time of the data 0 margin read, as illustrated inFIG. 19, the signal refdcjn of a low level is inputted into the gate electrode of the MOS transistor M14, and the signal refdckn of a high level is inputted into the gate electrode of the MOS transistor M16.

The potential of the reference signal urefmosg s at the time of the data 0 margin read is set up so that for example, the electric current of the sum of the electric current flowing through the memory cell140(here the memory cell140p) which stores the “H” side data and of which the degradation of the data holding characteristics has advanced and the electric current flowing through the MOS transistor M14of the potential drawing-out unit191is greater than the electric current flowing through the memory cell140(here the memory cell140n) storing the “L” side data.

First, the explanation is made for the case where a pair of the memory cells140as the read target stores the data “0.” In the positive memory140p,the threshold voltage is high. Accordingly, an electric current flows through the memory cell140from the bit line151jp(151kp) toward the source line153on the low voltage side. However, the threshold voltage of the positive memory140pis high. Accordingly, the electric current flowing from the bit line151jp(151kp) toward the source line153is small as compared with the negative memory140n.Then, an electric current flows from the bit line151jp(151kp) toward the low-potential-side power source Vss via the MOS transistor M14. Accordingly, in the bit line151jp(151kp), the potential is drawn out and falls.

On the other hand, in the negative memory140n,an electric current flows from the bit line151jn(151kn) toward the source line153. Then, the potential of the bit line151jn(151kn) is drawn out and falls.

When the degradation of the data holding characteristics of the positive memory140pstoring the “H” side data has advanced, as compared with the case where the degradation of the data holding characteristics has not advanced, an electric current flowing through the memory cell140from the bit line151jptoward the source line153of the low voltage Vss increases. Accordingly, the falling speed of the potential of the bit line151jp(151kp) becomes faster than the falling speed of the potential of the bit line151jn(151kn). Then, the potential of the bit line151jp(151kp) becomes lower than the potential of the bit line151jn(151kn), and the sense amplifier SA reads data “1” from a pair of the memory cells140storing data “0”.

In this way, in the data 0 margin read, the sense amplifier SA reads wrong data “1” from a pair of the memory cells140storing data “0”. Accordingly, a pair of the memory cells140of which the degradation of the data holding characteristics of data “0” has advanced is detected.

When a pair of the memory cells140store data “1”, for example, the potential of the bit line151jp(151kp) does not become higher than the potential of the bit line151jn(151kn) even when the data 0 margin read is performed; accordingly, the sense amplifier SA never reads out the wrong data.

<A Refreshing Method of the Flash Memory>

Next, the refreshing method of the flash memory is explained. Also in the present embodiment, a series of processing related to the refresh operation is performed according to the flow chart illustrated inFIG. 14.

At first, at Step S1001, the leading address when performing the normal read and the data 1 margin read to be described later is set up. The leading address may be the leading address of the address space of the nonvolatile memory or may be the leading address of an erasing unit. The word line152is selected based on the set leading address, and a pair of the memory cells140coupled to the word line152are selected as a pair of the memory cells140as the read target.

Step S1010is a fourth read step at which the controller120performs the normal read. Specifically, the sense amplifier SA performs the normal read to a pair of the memory cells140as the read target selected at Step S1001.

Step S1020is a fifth read step at which the controller120performs the data 1 margin read. Specifically, the sense amplifier SA performs the data 1 margin read to the memory cell140to which the normal read has been performed at the immediately preceding step S1010.

Step S1030is a third data comparison step (the third data comparison operation) in which controller120compares the data read at the fourth read step S1010and the data read at the fifth read step S1020. The controller120detects the memory cell140of which the degradation of the data holding characteristics of data “1” has advanced by comparing these pieces of data.

At Step S1030, when the controller120determines that the data read at the fourth read step S1010and the data read at the fifth read step S1020are different from each, other (No), Step S1040is performed.

Step S1040is a second refresh step (the second refresh operation) in which the controller120rewrites the data stored in a pair of the memory cells140as the read target into the pair of the memory cells140as the read target. For example, the controller120generates inverted data from the data read by the normal read to make a pair, and writes the pair of data into a pair of the memory cells140(140p,140n) as the write data.

When the second refresh, operation is performed, the flow shifts to Step S1001, and the detection of the memory cell140of which the degradation of the data holding characteristics has advanced is performed again from the leading address. The leading address may be the leading address of the address space of the nonvolatile memory or may be the leading address of an erasing unit. That is, after performing the second, refresh operation, the controller120performs, to a pair of the memory cells140as the read target, the fourth read step S1010(the fourth read operation), the fifth read step S1020(the fifth read operation), and the third data comparison step S1030(the third data comparison operation).

At Step S1030, when the controller120determines that the data read at the fourth read step S1010and the data read at the fifth read step S1020are the same (Yes), Step S1051and Step S1052are performed sequentially. Step S1051and Step S1052are already explained; accordingly, the detail explanation thereof is omitted here.

<The Effect by the Present Embodiment>

According to the present embodiment, in addition to the effect in the above-described embodiment, the following effects are obtained.

According to the present embodiment, to a pair of the memory cells140pand140nas the read target, the controller120performs the normal read (the fourth read operation, the fourth read step S1010) and the data 1 margin read (the fifth read operation, the fifth read step S1020). Then, the controller120performs the third data comparison operation (the third data comparison step S1030) to compare the data read by the normal read and the data read by the data 1 margin read. Then, at the third data comparison operation, when the controller120determines that the data read by the normal read and the data read by the data 1 margin read are different, the controller120performs the second refresh operation (the second refresh step S1040).

According to this configuration, also in the flash memory100A of the complementary system, it is possible to detect a pair of the memory cells140of which the degradation of the data holding characteristics of data “1” has advanced, by performing the data 1 margin read with the read conditions of data “1” severer than the normal read. Accordingly, the refresh operation can be performed at the appropriate time before a read error occurs. In addition, according to the present configuration, the reliability of the flash memory100A enhances and the reliability of the micro controller300that mounts the flash memory100A enhances.

Furthermore, according to the present embodiment, after performing the second refresh operation at the second refresh step S1040, the controller120performs, to a pair of the memory cells140pand140nas the read target, the fourth read step S1010, the fifth read step S1020, and the third data comparison step S1030.

According to this configuration, it is reconfirmed whether the degradation of the data holding characteristics has advanced to a pair of the memory cells140to which the refresh operation, has been made. Accordingly, the reliability of the flash memory100A is enhanced. Also according to the present configuration, the reliability of the micro controller300that mounts the flash memory100A is enhanced.

Furthermore, according to the present embodiment, a pair of the memory cells140pand140nare coupled to the same word line152.

According to this configuration, it is possible to perform the erase operation, the write operation, and the read operation without selecting plural word lines. Accordingly, the load related to these operations is reduced.

Next, Embodiment 4 of the present invention is explained. The present embodiment explains the case where the data 0 margin read is also performed in addition to the data 1 margin read, in the processing related to the refresh operation. Also in the present embodiment, a series of processing related to the refresh operation is performed according to the flow chart illustrated inFIG. 15. In the following, the explanation about the contents overlapping with the above-described embodiments is omitted in principle.

At Step S1030, when the controller120determines that the data read at the fourth read step S1010and the data read at the fifth read step are the same (Yes), Step S2060is performed.

Step S2060is a sixth read step at which the controller120performs the data 0 margin read. Specifically, the sense amplifier SA performs the data 0 margin read to a pair of the memory cells140to which the read operation has been made at Step S1010and Step S1020.

Step S2070is a fourth data comparison step (the fourth data comparison operation) at which the controller120compares data read at the fourth read step S1010with data read at the sixth read step S2060. The controller120detects a pair of the memory cells140of which the degradation of the data holding characteristics of data “0” has advanced by comparing these pieces of data.

At Step S2070, when the controller120determines that the data read at the fourth read step S1010and the data read at the sixth read step S2060are different from each, other (No), Step S2080is performed. Step S2080is a second refresh step. At Step S2080, the controller120performs the same processing as in the second refresh, step S1040described above. Accordingly, the detailed explanation thereof is omitted here.

When the second refresh operation is performed, the flow shifts to Step S1001, and the detection, of a pair of the memory cells140of which, the degradation of the data holding characteristics has advanced is performed from the leading address. The leading address maybe the leading address of the address space of the nonvolatile memory or may be the leading address of an erasing unit. That is, after performing the refresh operation, the controller120performs, to a pair of the memory cells140as the read object, the fourth read step S1010(the fourth read operation), the fifth read step S1020(the fifth read operation), the third data comparison step S1030(the third data comparison operation), the sixth read step S2060(the sixth read operation), and the fourth data comparison step S2070(the fourth data comparison operation).

At Step S2070, when the controller120determines that the data read at the fourth read step S1010and the data read at the sixth read step S2060are the same (Yes), Step S1051and Step S1052are performed sequentially. The processing at Step S1051and Step S1052is already explained; accordingly, the detailed explanation thereof is omitted.

<The Effect by the Present Embodiment>

According to the present embodiment, in addition to the effect in the above-described embodiments, the following effects are obtained.

According to the present embodiment, when, in the third data comparison operation (the third data comparison step S1030), the controller120determines that the data read by the normal read (the fourth read operation, the fourth read step S1010) and the data read by the data 1 margin read (the fifth read operation, the fifth read step S1020) are the same, the controller120performs the data 0 margin read (the sixth read operation, the sixth read step S2060). Then, the controller120performs the fourth data comparison operation (the fourth data comparison step S2070) to compare the data read by the normal read with the data read by the data 0 margin read. In the fourth data comparison operation, when the controller120determines that the data read by the normal read and the data read by the data 0 margin read are different from each other, the controller120performs the second refresh operation (the second refresh step S2080).

According to this configuration, also in the flash memory100A of the complementary system, the controller120also performs the data 0 margin read, after performing the data 1margin read. Accordingly, it is possible to improve the accuracy to detect, a pair of the memory cells140of which the degradation of the data holding characteristics has advanced. Accordingly, the reliability of the flash memory100A improves more, and the reliability of the micro controller300that mounts the flash memory100A improves.

Furthermore, according to the present embodiment, after performing the second refresh operation (the second refresh step S2080), the controller120performs, to a pair of the memory cells140as the read object to which the second refresh operation has been performed, the normal read (the fourth read operation, the fourth read step S1010), the data 1 margin, read (the fifth read operation, the fifth read step S1020), the third data comparison operation (the third data comparison step S1030), the data 0 margin read (the sixth read operation, the sixth read step S2060), and the fourth data comparison operation (the fourth data comparison step S2070).

According to this configuration, also when, the data 0margin read is performed, it is reconfirmed whether the degradation of the data holding characteristics has advanced, to the memory cell140to which the second refresh, operation has been performed. Accordingly, the reliability of the flash memory100A improves more, and the reliability of the micro controller300that mounts the flash memory100improves more.

Next, Embodiment 5 of the invention is explained. The present embodiment describes the case where, in the refresh operation in the flash memory of the complementary system, the margin read is performed to the memory cell140storing the “L” side data. In the following, the explanation about the contents overlapping with the above-described embodiments is omitted in principle.

<The Configuration of the Flash Memory>

FIG. 20illustrates an example of the circuit configuration of the sense amplifier and the periphery thereof according to Embodiment 5 of the present invention. The bit line potential controller290includes a potential drawing-out unit191, a read-out data holding unit292, and a potential drawing-out bit-line selector293, as illustrated inFIG. 20.

The read-out data holding unit292includes a gate circuit201and a latch circuit LAT. One input terminal of the gate circuit201is coupled to the input terminal of the enable signal that switches ON/OFF of the sense amplifier SA.

The sense amplifier SA is turned on when the enable signal of a high level is inputted, and is turned off when the enable signal of a low level is inputted. Therefore, when the sense amplifier SA is turned on, the enable signal of a high level is inputted into the one input terminal of the gate circuit201. On the other hand, when the sense amplifier SA is turned off, the enable signal of a low level is inputted into the one input terminal of the gate circuit201.

The read mode signal according to the read mode (the normal read and the margin read) is inputted into the other input terminal of the gate circuit201. At the time of the normal read, the read mode signal of a high level is inputted into the other input terminal of the gate circuit201, for example. On the other hand, at the time of the L-side data margin read to be described later, the read mode signal of a low level is inputted into the other input terminal of the gate circuit201, for example.

The output terminal of the gate circuit201is coupled to the latch clock signal input terminal (enable) that switches ON/OFF of the latch circuit LAT.

The gate circuit201outputs the latch clock signal of a high level when the enable signal of a high level is inputted into the one input terminal and the read mode signal of a high level is inputted into the other input terminal. On the other hand, the gate circuit201outputs the latch clock signal of a low level when a signal of a low level is inputted into any one of the input terminals.

The data input terminal (data) of the latch circuit LAT is coupled to the output terminal of the sense amplifier SA. The data output terminal (out) of the latch circuit LAT is coupled to an input terminal of the gate circuit211of the potential drawing-out bit-line selector293to be described later.

The latch circuit LAT fetches and stores the data outputted from the sense amplifier SA. Specifically, when the latch clock signal of a high level is inputted into the latch clock signal input terminal of the latch circuit LAT, the latch circuit LAT is turned on, and the latch circuit LAT fetches and stores the data that the sense amplifier SA has read from a pair of the memory cells140(140p,140n). The sense amplifier SA outputs a signal of a high level as the read data for example when data “1” is read from a pair of the memory cells140(140p,140n), and outputs a signal of a low level as the read data for example when data “0” is read. The latch circuit. LAT outputs the fetched data to the potential drawing-out bit-line selector293.

The potential drawing-out bit-line selector293includes gate circuits211to214. The input terminal of the gate circuit211is coupled, to the data output terminal (out) of the latch circuit LAT. An output terminal of the gate circuit211is coupled to an input terminal of the gate circuit212and one input terminal of the gate circuit213. An output terminal of the gate circuit212is coupled to one input terminal of the gate circuit214. A reference current clock signal is inputted into the other input terminal of the gate circuit213and the other input terminal of the gate circuit214.

The reference current clock signal is a signal that becomes active at the time of performing the L-side data margin read to be described later. That is, at the time of performing the L-side data margin read, the reference current clock signal of a high level is inputted into each of the other input terminals of the gate circuits213and214. On the other hand, when not performing the L-side data margin read, the reference current clock signal of a low level is inputted into each of the other input terminals of the gate circuits213and214.

Next, the read operation in the present embodiment is explained.FIG. 21AandFIG. 21Billustrate the list of the potential applied to the potential drawing-out unit at the time of each read operation according to Embodiment 5 of the present invention.FIG. 21Aillustrates the normal read, andFIG. 21Billustrates the L-side data margin read.

In the present embodiment, in order to determine whether the refresh operation to be described later is performed, the normal read (the fourth read operation) and the L-side data margin read (the fifth read operation) are performed.

As is the case with Embodiments 3 and 4 described above, in the normal read, the controller120performs the operation in which, to a pair of the memory cells140as the read object, the memory cell (one memory cell)140pis made to draw out the potential of the bit line (one of the bit lines)151jp(151kp), the memory cell (the other of the memory cells)140nis made to draw out the potential of the bit line (the other of the bit lines)151jn(151kn), and concurrently, the sense amplifier SA is made to read the data.

The operation of the bit line potential controller290in this case is explained in detail in the following. The enable signal of a high level is inputted into the one input terminal of the gate circuit201. The read mode signal of a high level is inputted into the other input terminal of the gate circuit201. Accordingly, the gate circuit201outputs the latch clock signal of a high level. Accordingly, the latch circuit LAT is turned on, and the latch circuit LAT fetches and stores the signal outputted from the sense amplifier SA. At this time, when the data read from a pair of the memory cells140(140p,140n) is “1”, the latch circuit LAT stores the signal of a high level, for example. When the data read from a pair of the memory cells140(140p,140n) is “0”, the latch circuit LAT stores the signal of a low level, for example. The latch circuit LAT outputs the stored data to the potential drawing-out bit-line selector293.

The signal outputted from the latch circuit LAT is inputted into the input terminal of the gate circuit211of the potential drawing-out bit-line selector293. Accordingly, the inverted signal of the signal inputted into the input terminal of the gate circuit211is inputted into the one input terminal of the gate circuit213. The signal further inverted in the gate circuit212, that is, the same signal as the signal inputted into the input terminal of the gate circuit211, is inputted into the one input terminal of the gate circuit214.

Specifically, when data “1” is read by the sense amplifier SA, a signal of a high level is inputted into the input terminal of the gate circuit211. Accordingly, the signal of a low level is inputted into the one input terminal of the gate circuit213, and the signal of a high level is inputted into the one input terminal of the gate circuit214. On the other hand, when data “0” is read by the sense amplifier SA, a signal of a low level is inputted into the input terminal of the gate circuit211. Accordingly, the signal of a high level is inputted into the one input terminal of the gate circuit213, and the signal of a low level is inputted into the one input terminal of the gate circuit214.

In the normal read, the reference current clock signal of a low level is inputted into the other input terminals of the gate circuits213and214, respectively. Therefore, the gate circuits213and214output the potential drawing-out switching signals refdcjn and refdckn of a high level, respectively, as illustrated inFIG. 21A. Therefore, the MOS transistors M14and M16are turned off, and the potential drawing out of the bit lines151jp(151kp) and151jn(151kn) via the potential drawing-out unit191is not performed.

In the L-side data margin read, based on the data read by the normal read, the controller120performs the operation in which the memory cell140with a low threshold voltage of the pair of the memory cells140(140p,140n) is made to draw out the potential of the bit line151coupled to the memory cell140with the low threshold voltage, the memory cell140with a high threshold voltage of the pair of the memory cells140(140p,140n) and the bit line potential controller290are made to draw out the potential of the bit line151coupled to the memory cell140with a high threshold voltage, and concurrently, the sense amplifier SA is made to read data.

Therefore, at the time of the L-side data margin read, in the potential drawing-out unit191, as illustrated inFIG. 21B, the potential drawing-out switching signals refdcjn and refdckn to be inputted into the respective gate electrodes of the MOS transistors M14and M16are switched, according to the data read from the pair of the memory cells140(140p,140n).

In the L-side data margin read, the reference current clock signal of a high level is inputted into the other input terminal of the gate circuits213and214, respectively. When data “1” is read by the sense amplifier SA, the signal of a low level is inputted into the one input terminal of the gate circuit213, and the signal of a high level is inputted into the one input terminal of the gate circuit214. Therefore, as illustrated inFIG. 21B, the gate circuit213outputs the potential drawing-out switching signal refdcjn of a high level, and the gate circuit214outputs the potential drawing-out switching signal refdckn of a low level. Accordingly, the MOS transistor M14is turned off and the MOS transistor M16is turned on. Therefore, the potential drawing out of the bit line151jp(151kp) is not performed from the MOS transistor M14, however, the potential drawing out of the bit line151jn(151kn) is performed from the MOS transistor M16. That is, the bit line151jn(151kn) is coupled to the negative memory (the memory cell140n) storing the “H” side data, and the potential of the bit line151jn(151kn) coupled to the memory cell140nis drawn out from the MOS transistor M16.

On the other hand, when data “0” is read by the sense amplifier SA, the signal of a high level is inputted into the one input terminal of the gate circuit213, and the signal of a low level is inputted into the one input terminal of the gate circuit214. Therefore, as illustrated inFIG. 21B, the gate circuit213outputs the potential drawing-out switching signal refdcjn of a low level, and the gate circuit214outputs the potential drawing-out switching signal refdckn of a high level. Accordingly, the MOS transistor M14is turned on and the MOS transistor M16is turned off. Therefore, the potential drawing out of the bit line151jn(151kn) is not performed from the MOS transistor M16, however, the potential drawing out of the bit line151jp(151kp) is performed from the MOS transistor M14. That is, the bit line151jp(151kp) is coupled to the positive memory (the memory cell140p) storing the “H” side data, and the potential of the bit line151jp(151kp) couple to the memory cell140pis drawn out from the MOS transistor M14,

In this way, in the L-side data margin read, the potential of the bit line151coupled to the memory cell140storing the “H” side data is drawn out from the potential drawing-out unit191, irrespective of the data that the pair of the memory cells140store.

<A Refreshing Method of the Flash Memory>

Next, the refreshing method of the flash memory is explained.FIG. 22is a flow chart illustrating the refreshing method of the flash memory according to Embodiment 5 of the present invention. In the present embodiment, as illustrated inFIG. 22, after performing the normal read, the L-side data margin read is performed.

At first, at Step S1001, the leading address when performing the normal read and the L-side data margin read is set up. The leading address may be the leading address of the address space of the nonvolatile memory or may be the leading address of an erasing unit. The word line152is selected based on the set-up leading address, and a pair of the memory cells140coupled to the word line152are selected as the pair of the memory cells140as the read target.

Step S5010is the fourth read step at which the controller120performs the normal read. Specifically, the sense amplifier SA performs the normal read to the pair of the memory cells140as the read target selected at Step S1001.

The latch circuit LAT fetches and stores the data that the sense amplifier SA has read. The latch circuit LAT outputs the signal based on the stored data to the potential drawing-out bit-line selector293. In the potential drawing-out bit-line selector293, a signal based on the signal outputted from the latch circuit LAT is inputted into each of the one input terminals of the gate circuits213and214. That is, a signal of a low level is inputted into the one input terminal of the gate circuit coupled to the gate terminal of the MOS transistor on the side of the memory cell140storing the “L” side data. On the other hand, a signal of a high level is inputted into the one input terminal of the gate circuit coupled to the gate terminal of the MOS transistor on the side of the memory cell140storing the “H” side data.

Step S5020is a seventh read step at which the controller120performs the “L” side margin read. Specifically, the sense amplifier SA always performs the L-side data margin read to the memory cell140to which the normal read has been performed at the immediately preceding step S5010.

Step S5030is a fifth data comparison step (the fifth data comparison operation) at which the controller120compares the data read at the fourth read step S5010with the data read at the seventh read step S5020. The controller120detects the memory cell140of which the degradation of the data holding characteristics of the “L” side data has advanced, by comparing these pieces of data.

At Step S5030, when the controller120determines that the data read at the fourth read step S5010and the data read at the seventh read step S5020are different from each other (No), Step S1040is performed. The processing at Step S1040is already explained in Embodiment 3. Accordingly, the detailed explanation thereof is omitted here.

At Step S5030, when the controller120determines that the data read at the fourth read step S5010and the data read at the seventh read step S5020are the same (Yes), Step S1051and Step S1052are performed sequentially. The processing at Step S1051and Step S1052is already explained; accordingly, the detailed explanation thereof is omitted.

<The Effect by the Present Embodiment>

According to the present embodiment, in addition to the effect in the above-described embodiments, the following effects are obtained. According to the present embodiment, the controller120performs the L-side data margin read after performing the normal read.

According to this configuration, also in the flash memory of the complementary system, the margin read is performed only to the memory cell140which stores the “L” side data and of which the degradation of the data holding characteristics is significant. Accordingly, the memory cell140of which the degradation of the data holding characteristics has advanced is detected efficiently. No margin read is performed to the memory cell140storing the “H” side data. Accordingly, it is possible to shorten the time required for detecting the memory cell140of which the degradation of the data holding characteristics has advanced.

Next, Embodiment 6 of the invention is explained. The present embodiment explains a flash memory provided with an error corrector to be described later. In the following, the explanation about the contents overlapping with the above-described embodiments is omitted in principle. In the following explanation, the contents regarding the flash memory100and the contents regarding the flash memory100A are explained collectively, and are explained individually depending on the case.

<The Configuration of the Flash Memory>

FIG. 23is a block diagram illustrating an example of the configuration of the micro controller that mounts the flash memory according to Embodiment 6 of the present invention. The flash memory500according to the present embodiment is comprised of the flash memory100(100A) and an error corrector501that is coupled to the flash memory100(100A). The error corrector501is comprised of an ECC (Error Checking and Correcting) circuit, for example.

As illustrated inFIG. 23, the error corrector501is coupled to the high-speed bus311, and performs data input/output via the high-speed bus311. The error corrector501generates error correcting data based on the data, and generates error corrected data in which error of the data read by the sense amplifier has been corrected. The error in the present embodiment means that the data written in the memory cell is different from the data read from the sense amplifier SA.

The error corrector501generates error correcting data from the write data inputted via the high-speed bus311, or from the data written in the memory cell140, for example. The generated error correcting data may be stored in the memory array108(108A) with the original data, or may be stored in a memory device (not shown) separately from the original data. When an error is detected, the error corrector501generates the error corrected data based on the data read from the sense amplifier SA and the error correcting data.

Based on instructions of the controller120, the error corrector501may generate an error correcting data or may switch ON/OFF of the error correction function to generate the error corrected data. For example, when the error correction function is turned off, the error corrector501outputs the data inputted from the high-speed bus311to the flash memories100and100A as it is, and does not perform the error detection to the data read from the sense amplifier SA. That is, in such a case, the flash memory500according to the present embodiment has function equivalent to the flash memories100and100A explained in the embodiments described above.

<A Refreshing Method of the Flash Memory>

Next, the refreshing method of the flash memory is explained.FIG. 24is a flow chart illustrating the refreshing method of the flash memory according to Embodiment 6 of the present invention.

Step S1001is already explained; accordingly, the detailed explanation thereof is omitted.

At Step S1020, the controller120performs the data 1margin read. In the flash memory100, the controller120performs the data 1 margin read by the second read operation. In the flash memory100A, the controller120performs the data 1 margin read by the fifth read operation.

Next, Step S3030is explained. In the flash memory100, the controller120performs the first error detection operation in which the error corrector501is made to detect the error of data, based on the data read by the data 1 margin read (the second read operation) and the error correcting data. That is, Step S3030in the flash memory100is the first error detection step.

On the other hand, in the flash memory100A, the controller120performs the third error detection operation in which the error corrector501is made to detect the error of data based on the data read by the data 1 margin read (the fifth read operation) and the error correcting data. That is, Step S3030in the flash memory100A is the third error detection step.

For example, the controller120outputs the data read by the data 1 margin read (the second and the fifth read operation) to the error corrector501. The error corrector501detects the error of the data read by the data 1 margin read, based on the data outputted from, the controller120and the error correcting data read from the memory array108(108A) or the memory device (not shown).

At Step S3030(the first and the third error detection step), when the error corrector501detects the error of the data read by the data 1 margin read (the second and the fifth read operation) (Yes), Step S3040is performed.

Next, Step S3040is explained. In the flash memory100, the controller120performs the third refresh operation in which the error corrector501is made to generate the error corrected data of which the error is corrected based on the data read by the data 1 margin read (the second read operation) and the error correcting data, and the error corrected data is rewritten in the memory cell140as the read target. That is, Step S3040in the flash memory100is the third refresh step.

On the other hand, in the flash memory100A, the controller120performs the fifth refresh operation in which the error corrector501is made to generate the error corrected data of which the error is corrected based on the data read by the data 1 margin read (the fifth read operation) and the error correcting data, and the error corrected data is rewritten in the pair of the memory cells140pand140nas the read target. That is, Step S3040in the flash memory100A is the fifth refresh step.

The error corrected data generated at Step S3040is the same as the write data when the initial data has been stored in the memory cell140and the pair of the memory cells140pand140n.

When the third refresh operation and the fifth refresh operation are performed, the flow shifts to Step S1001, and the detection of the memory cell140and a pair of the memory cells140pand140nof which the degradation of the data holding characteristics has advanced is performed again from the leading address. The leading address may be the leading address of the address space of the nonvolatile memory or may be the leading address of an erasing unit. That is, after performing the third refresh operation and the fifth refresh operation, the controller120performs, Step S1020(the second and the fifth read step) and Step S3030(the first and the third error detection step), to the memory cell140and the pair of the memory cells140pand140nas the read target.

At Step S3030, when the error corrector501does not detect the error of the data read at Step S1020(the second and the fifth read step) (No), Step S1051and Step S1052are performed sequentially. Step S1051and Step S1052are already explained; accordingly, the detailed explanation thereof is omitted.

<The Effect by the Present Embodiment>

According to the present embodiment, in addition to the effect in the above-described embodiments, the following effects are obtained. According to the present embodiment, the error corrector501is included, and the controller120performs the data 1 margin read (the second and the fifth read operation, the second and the fifth read step S1020), and the first and the third error detection operation (the first and the third error detection step S3030), in which the error corrector501is made to detect, the error of data, based, on the data read by the data 1 margin read and the error correcting data. Then, when the error corrector501detects the error of the data read by the data 1 margin, read in the first and the third error detection operation, the controller120performs the third and the fifth refresh operation (the third and the fifth refresh step S3040), in which the error corrector501is made to generate the error corrected data of which the error correction has been performed based on the data read by the data 1 margin read and the error correcting data, and the error corrected data is rewritten to the memory cell140and the pair of the memory cells140pand140n,as the read target.

According to this configuration, it is not necessary to perform the normal read. Accordingly, the time required for the error detection of the data read by the sense amplifier SA is shortened, and the time related to the refresh operation is shortened. Accordingly, the power consumption related to the refresh operation is reduced.

Furthermore, according to the present embodiment, after performing the third and the fifth refresh operation (the third and the fifth refresh step S3040), the controller120performs, to the memory cell140and the pair of the memory cells140pand140nas the read target, the data 1 margin read (the second and the fifth read operation, the second and the fifth read step S1020), and the first and the third error detection operation (the first and the third error detection step S3030),

According to this configuration, it is reconfirmed whether the degradation of the data holding characteristics has advanced, to the memory cell140and the pair of the memory cells140pand140nto which the refresh operation has been performed. Accordingly, it is possible to enhance the reliability of the flash memories100and100A, and the reliability of the flash memory500in the end. Accordingly, it is possible to enhance the reliability of the micro controller300that mounts the flash memory500.

Next, Embodiment 7 of the invention is explained. The present embodiment explains the case where, in the refresh operation of the flash memory500(100,100A) provided with the error corrector501, the data 0 margin read is also performed in addition to the data 1 margin read.FIG. 25is a flow chart illustrating the refreshing method of the flash memory according to Embodiment 7 of the present invention. In the following, the explanation about the contents overlapping with the above-described embodiments is omitted in principle.

At Step S3030, when the error corrector501does not detect the error of the data read at Step S1020(the second and the fifth read step) (No), Step S2060is performed.

At Step S2060, the controller120performs the data 0margin read. In the flash memory100, the controller120performs the data 0 margin read by the third read operation.

In the flash memory100A, the controller120performs the data 0 margin read by the sixth read operation.

Next, Step S4070is explained. In the flash memory100, the controller120performs the second error detection operation in which the error corrector501is made to detect the error of the data based on the data read by the data 0 margin read (the third read operation) and the error correcting data. That is, Step S4070in the flash memory100is the second error detection step.

On the other hand, in the flash memory100A, the controller120performs the fourth error detection operation in which the error corrector501is made to detect the error of the data based on the data read by the data 0 margin read (the sixth read operation) and the error correcting data. That is, Step S4070in the flash memory100A is the fourth error detection step.

For example, the controller120outputs the data read by the data 0 margin read (the third and the sixth read operation) to the error corrector501. The error corrector501detects the error of the data read by the data 0 margin read from the data outputted from the controller120and the error correcting data read from the memory array108(108A) or a memory device (not shown).

At Step S4070(the second and the fourth error detection step), when the error corrector501detects the error of the data read by the data 0 margin read (the third and the sixth read operation) (Yes), Step S4080is performed.

Next, Step S4080is explained. In the flash memory100, the controller120performs the fourth refresh operation in which the error corrector501is made to generate the error corrected data to which the error correction has been performed based on the data read by the data 0 margin read (the third read operation) and the error correcting data, and the error corrected data is rewritten in the memory cell140as the read target. That is, Step S4080in the flash memory100is the fourth refresh step.

On the other hand, in the flash memory100A, the controller120performs the sixth refresh operation in which the error corrector501is made to generate the error corrected data to which the error correction has been performed based on the data read by the data 0 margin read (the fifth read operation) and the error correcting data, and the error corrected data is rewritten in the pair of the memory cells140pand140nas the read target. That is, Step S4080in the flash memory100A is the sixth refresh step.

The error corrected data generated at Step S4080is the same as the write data when the initial data has been stored in the memory cell140and the pair of the memory cells140pand140n.

When the fourth and the sixth refresh operation are performed, the flow shifts to Step S1001, and the detection of the memory cell140and a pair of the memory cells140pand140nof which the degradation of the data holding characteristics has advanced is performed again from the leading address. The leading address may be the leading address of the address space of the nonvolatile memory or may be the leading address of an erasing unit. That is, after performing the fourth and the sixth refresh operation, the controller120performs, to the memory cell140and the pair of the memory cells140pand140nas the read target, Step S1020(the second and the fifth read step), Step S3030(the first and the third error detection step), Step S2060(the third and the sixth read step), and Step S4070(the second and the fourth error detection step).

At Step S4070, when the error corrector501does not detect the error of the data read at Step S2060(the third and the sixth read step) (No), Step S1051and Step S1052are performed sequentially. Step S1051and Step S1052are already explained; accordingly, the detailed explanation thereof is omitted.

<The Effect by the Present Embodiment>

According to the present embodiment, in addition to the effect in the above-described embodiments, the following effects are obtained. According to the present embodiment, at Step S3030, when the error corrector501does not detect the error of the data read by the data 1 margin read (the second and the fifth read operation, the second and the fifth read step S1020), the controller120performs the data 0 margin read (the third and the sixth read operation, the third and the sixth read step S2060), and the second and the fourth error detection operation (the second and the fourth error detection step S4070) in which the error corrector501is made to detect the error of the data based on the data read by the data 0 margin read and the error correcting data.

When the error corrector501detects the error of the data read by the data 0 margin read in the second and the fourth error detection operation, the controller120performs the fourth and the sixth refresh operation (the fourth and the sixth refresh step S4080), in which the error corrector501is made to generate the error corrected data of which the error correction has been performed based on the data read by the data 0 margin read and the error correcting data, and the error corrected data is rewritten to the memory cell140and the pair of the memory cells140pand140n,as the read target.

According to this configuration, the controller120also performs the data 0 margin read, after performing the data 1margin read. Accordingly, it is possible to improve the accuracy to detect the memory cell140and the pair of the memory cells140pand140nof which the degradation of the data holding characteristics has advanced. Accordingly, it is possible to enhance more the reliability of the flash memories100and100A and it is possible to enhance the reliability of the flash memories100and100A, and the reliability of the flash memory500in the end. Accordingly, it is possible to enhance the reliability of the micro controller300that mounts the flash memory500.

Furthermore, according to the present embodiment, after performing the fourth and the sixth refresh operation (the fourth and the sixth refresh step S4080), the controller120performs, to the memory cell140and the pair of the memory cells140pand140nas the read target, the data 1 margin read (the second and the fifth read operation, the second and the fifth read step S1020), the first and the third error detection operation (the first and the third error detection step S3030), the data 0 margin read (the third and the sixth read operation, the third and the sixth read step S2060), and the second and the fourth error detection operation (the second and the fourth error detection step S4070).

According to this configuration, it is reconfirmed whether the degradation of the data holding characteristics has advanced, to the memory cell140and the pair of the memory cells140pand140nto which the refresh operation has been performed. Accordingly, it is possible to enhance more the reliability of the flash memories100and100A, and the reliability of the flash memory500in the end. Accordingly, it is possible to enhance more the reliability of the micro controller300that mounts the flash memory500.

Next, Embodiment 8 of the invention is explained. The present embodiment explains the case where the normal read and the L-side data margin read are performed, in the refresh operation of the flash memory500(100A) of the complementary system which is provided with the error corrector501. In the following, the explanation about the contents overlapping with the above-described embodiments is omitted in principle.

The flash memory500according to the present embodiment includes the bit line potential controller290illustrate inFIG. 20. The bit line potential controller290is already explained in Embodiment 5; accordingly, the detailed explanation thereof is omitted here. The normal read and the L-side data margin read in the present embodiment are also already explained in Embodiment 5; accordingly, the detailed explanation thereof is omitted here.

<A Refreshing Method of the Flash Memory>

Next, the refreshing method of the flash memory is explained.FIG. 26is a flow chart illustrating the refreshing method of the flash memory according to Embodiment 8 of the present invention. In the present embodiment, as illustrated inFIG. 26, after performing the normal read, the L-side data margin read is performed.

At first, at Step S1001, the leading address when performing the normal read and the data 1 margin read to be described later is set up. The leading address may be the leading address of the address space of the nonvolatile memory or may be the leading address of an erasing unit. The word line152is selected based on the set-up leading address, and a pair of the memory cells140coupled to the word line152are selected as the pair of the memory cells140as the read target.

Step S5010is the fourth read step at which the controller120performs the normal read. Step S5020is the seventh read step at which the controller120performs the L-side data margin read. Step S5010and Step S5020are explained in Embodiment 5. Accordingly, the detailed explanation thereof is omitted here.

At Step S6030, the controller120performs the fifth error detection operation in which the error corrector501is made to detect the error of the data, based on the data read by the L-side data margin read (the seventh read operation) and the error correcting data.

At Step S6030, for example, the controller120outputs the data read by the L-side data margin read to the error corrector501. The error corrector501detects the error of the data read by the L-side data margin read, from the data outputted from the controller120, and the error correcting data read from the memory array108(108A) or a memory device (not shown).

At Step S6030, when the error corrector501detects the error of the data read by the L-side data margin read (Yes), Step S6040is performed.

Next, Step S6040is explained. In the flash memory100A, the controller120performs the seventh refresh operation in which the error corrector501is made to generate the error corrected data of which the error correction has been performed based on the data read by the L-side data margin read and the error correcting data, and the error corrected data is rewritten in the pair of the memory cells140as the read target. That is, Step S6040is the seventh refresh step.

When the seventh refresh operation is performed, the flow shifts to Step S1001, and the detection of the memory cell140of which the degradation of the data holding characteristics has advanced is performed again from the leading address. The leading address may be the leading address of the address space of the nonvolatile memory or may be the leading address of an erasing unit. That is, after performing the seventh refresh operation, the controller120performs Steps S5010, S5020, and S6030, to the pair of the memory cells140(140p,140n) as the read target.

At Step S6030, when the error corrector501does not detect the error of the data read at Step S5020(No), Step S1051and Step S1052are performed sequentially. Step S1051and Step S1052are already explained. Accordingly, the detailed explanation thereof is omitted here.

<The Effect by the Present Embodiment>

According to the present embodiment, in addition to the effect in the above-described embodiments, the following effects are obtained. According to the present embodiment, the controller120performs the L-side data margin read after performing the normal read.

According to this configuration, also in the flash memory of the complementary system, the margin read is pier formed only to the memory cell140which stores the “L” side data and of which the degradation of the data holding characteristics is significant. Accordingly, the memory cell140of which the degradation of the data holding characteristics has advanced is detected efficiently. No margin read is performed to the memory cell140storing the “H” side data. Accordingly, it is possible to shorten the time required for detecting the memory cell140of which the degradation of the data holding characteristics has advanced.

Next, Embodiment 9 of the invention is explained. In the embodiments described above, the explanation is made for the case where the memory cell140is comprised of the selection transistor141and the memory transistor142. However, the memory cell is not restricted to such a configuration. In the present, embodiment, the case where the memory cell is comprised only of a memory transistor is explained.

FIG. 27illustrates an example of the circuit configuration of the memory cell according to Embodiment 9 of the present invention.FIG. 28is a sectional view illustrating an example of the configuration of the memory cell according to Embodiment 9 of the present invention. The memory cell940is comprised only of a memory transistor, as illustrated inFIG. 27andFIG. 28.

As illustrated inFIG. 28, in a semiconductor substrate940a,a WELL region940gcommon to multiple memory cells940is formed, and the memory cell940is formed over the WELL region940g.The memory cell940has a planer type MONOS structure, for example. As Illustrated inFIG. 28, in the area between a source942fand a drain941d,the memory cell940has a lamination of an oxide layer (oxide)942b,a nitride layer (nitride)942c,an oxide layer (oxide)942d,and a memory gate (metal)942e,over the WELL region940gof the semiconductor substrate (semiconductor)940a.

The drain941dof the memory cell940is coupled to the bit line151(151j,151jp,151jn,151k,151kp,151kn), as illustrated inFIG. 27. The memory gate942eof the memory cell940is coupled to the word line152as illustrated inFIG. 27, for example. The memory gate942eof the memory cell940may be coupled to the memory gate line154, for example. The source942fof the memory transistor940is coupled to the source line153common to the multiple memory cells940, as illustrated inFIG. 27.

FIG. 29illustrates an example of the voltages applied to the memory cell in each operation.FIG. 29illustrates voltages applied to the bit line151(151j,151jp,151jn,151k,151kp,151kn), the memory gate942e,the source line153, and the WELL region940gin each of the write operation, the erase operation, and the read operation.FIG. 29illustrates the case where each operation is performed in an FN tunnel system.

For example, as illustrated inFIG. 29, at the time of the write operation, the following voltages are applied: a voltage of −4V to the bit line151(151j,151jp,151jn,151k,151kp,151kn), a voltage of 6V to the memory gate942e(that is, the word line152), a voltage of −4V to the source line153, and a voltage of −4V to the WELL region140g.At the time of the write operation, an electron is injected from a channel by the method called the FN electron injection to the nitride layer942, to trap the electron to the nitride layer942c,thereby creating the state where the threshold voltage is high.

For example, as illustrated inFIG. 29, at the time of the erase operation, the following voltages are applied: a voltage of 6V to the bit line151(151j,151jp,151jn,151k,151kp,151kn), a voltage of −4V to the memory gate942e(that is, the word line152), a voltage of 6V to the source line153, and a voltage of 6V to the WELL region140g.At the time of the erase operation, a hole is injected from a channel by the method called the FN hole injection, to trap a hole to the nitride layer942c,thereby creating the state where the threshold voltage is low.

For example, as illustrated inFIG. 29, at the time of the read operation, the following voltages are applied: a voltage of 1.5V to the bit line151(151j,151jp,151jn,151k,151kp,151kn), a voltage of 1.5V to the memory gate942e(that is, the word line152), a voltage of 0V to the source line153, and a voltage of 0V to the WELL region140g.

When the number of times of rewriting increases, the ability to trap an electron and a hole in the nitride layer942cis degraded, and a variation of the threshold voltage in the rewrite state and the erase state become large. Therefore, also in the memory cell940that has such a configuration, a series of processing related to the refresh operation explained in the above-described embodiments is performed.

As described above, the invention accomplished by the present inventors has been concretely explained based on the embodiments. However, it cannot be overemphasized that the present invention is not restricted to the embodiments as described above, and it can be changed variously in the range that does not deviate from the gist.

In the following, the desirable main modes of the present invention are remarked in addition.

A flash memory is comprised of:

a plurality of memory cells;

a sense amplifier to read data stored in the memory cell;

a bit line potential controller to control the potential of the bit line; and a controller.

In a pair of the memory cells, the data is stored by storing the data in one of the memory cells and storing inverted data obtained by inverting the data in the other of the memory cells.

The sense amplifier is coupled, at an input terminal, to a pair of the bit lines coupled to the pair of the memory cells, and reads the data stored in the pair of the memory cells, based on potential of one of the bit lines coupled to one of the memory cells and potential of the other of the bit lines coupled to the other of the memory cells.

The controller performs

a fourth read operation in which one of the memory cells is made to draw out the potential of one of the bit lines, the other of the memory cells is made to draw out the potential of the other of the bit lines, and concurrently, the sense amplifier is made to read the data,

a seventh read operation in which, based on the data read by the fourth read operation, the memory cell with a low threshold voltage of the pair of the memory cells is made to draw out the potential of the bit line coupled to the memory cell with the low threshold voltage, the memory cell with a high threshold voltage of the pair of the memory cells and the bit line potential controller are made to draw out the potential of the bit line coupled to the memory cell with a high threshold voltage, and concurrently, the sense amplifier is made to read the data,

a fifth data comparison operation in which the data read by the fourth read operation and the data read by the seventh read operation are compared with each other, and

a second refresh operation in which, when the data read by the fourth read operation and the data read by the seventh read operation are determined to be different from each other in the fifth data comparison operation, the data and the inverted data stored in the pair of the memory cells are rewritten in the pair of the memory cells.

A flash memory is comprised of:

a plurality of memory cells;

a sense amplifier to read data stored in the memory cell;

a bit line potential controller to control the potential of the bit line;

an error corrector to generate error correcting data based on the data, and to correct an error of the data read by the sense amplifier; and

a controller.

In the pair of memory cells, the data is stored by storing the data in one of the memory cells and storing inverted data obtained by inverting the data in the other of the memory cells.

The sense amplifier is coupled, at an input terminal, to a pair of the bit lines coupled to the pair of the memory cells, and reads the data stored in the pair of memory cells, based on potential of one of the bit lines coupled to one of the memory cells and potential of the other of the bit lines coupled to the other of the memory cells.

The controller performs

a fourth read operation in which one of the memory cells is made to draw out the potential of one of the bit lines, the other of the memory cells is made to draw out the potential of the other of the bit lines, and concurrently, the sense amplifier is made to read the data, a seventh read operation in which, based on the data read by the fourth read operation, the memory cell with a low threshold voltage of the pair of the memory cells is made to draw out the potential of the bit line coupled to the memory cell with the low threshold voltage, the memory cell with a high threshold voltage of the pair of the memory cells and the bit line potential controller are made to draw out the potential of the bit line coupled to the memory cell with a high threshold voltage, and concurrently, the sense amplifier is made to read the data,

a fifth error detection operation in which the error corrector is made to detect an error of the data based on the data read by the seventh read operation and the error correcting data, and

a seventh refresh operation in which when the error corrector detects an error of the data read by the seventh read operation in the fifth error detection operation, the error corrector is made to generate the error corrected data of which the error is corrected based on the data read by the seventh read operation and the error correcting data, and the error corrected data is rewritten in the pair of the memory cells.