Pulse generation in dual supply systems

Various apparatuses and methods are disclosed. The system describes a pulse generator comprising a first stage configured to be powered by a first voltage; and a second stage configured to be powered by a second voltage different from the first voltage, wherein the second stage is further configured to generate a pulse in response to an input to the first stage comprising a trigger and feedback from the second stage.

BACKGROUND

The present disclosure relates generally to electronic circuits, and more particularly, to pulse generation in dual supply systems.

With the ever increasing demand for more processing capability in mobile devices, low power consumption has become a key design requirement. Various techniques are currently employed to reduce power consumption in such devices. One such technique involves reducing the operating voltage of certain circuits operating on a chip. As a result, different circuits on the chip operate at different voltages. Level shifters are used to convert one voltage level to another voltage level. Level shifters allow a signal to pass from one voltage domain to another voltage domain.

A common circuit used today in dual voltage systems is a one-shot pulse generator. A pulse is generated in a first voltage domain by the one-shot and then level shifted to a second voltage domain. The pulse is generated by gating a trigger with a delayed version of the trigger. The pulse-width is defined by the time between the trigger and the delayed trigger. However, the delay circuit may not track well with process, voltage and temperature (PVT) variations. The pulse width can be very narrow under extreme PVT conditions. This can cause a functional failure if the level-shifted pulse fails to switch from rail-to-rail. The only way to recover is by tuning the delay circuit. The can cost real estate and add timing complexities

SUMMARY

One aspect of a pulse generator includes a first stage configured to be powered by a first voltage, and a second stage configured to be powered by a second voltage different from the first voltage. The second stage is further configured to generate a pulse in response to an input to the first stage comprising a trigger and feedback from the second stage.

One aspect of a method includes generating a pulse from a pulse generator having a first stage powered by a first voltage and a second stage powered by a second voltage different from the first voltage. The method includes generating a pulse in response to an input to the first stage comprising a trigger and feedback from the second stage.

Another aspect of a pulse generator includes pulse generating means for generating a pulse and pre-pulse generating means for generating a pre-pulse from an input comprising a trigger and feedback from the pulse generating means. The pulse generating means is configured to generate the pulse from the pre-pulse. The pre-pulse generating means is configured to be powered by a first voltage, and the pulse generating means is configured to be powered by a second voltage different from the first voltage.

It is understood that other aspects of apparatuses and methods will become readily apparent to those skilled in the art from the following detailed description, wherein various aspects of apparatuses and methods are shown and described by way of illustration. As will be realized, these aspects may be implemented in other and different forms and its several details are capable of modification in various other respects. Accordingly, the drawings and detailed description are to be regarded as illustrative in nature and not as restrictive.

DETAILED DESCRIPTION

Various aspects of the disclosure will be described more fully hereinafter with reference to the accompanying drawings. This disclosure may, however, be embodied in many different forms by those skilled in the art and should not be construed as limited to any specific structure or function presented herein. Rather, these aspects are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art. Based on the teachings herein, one skilled in the art should appreciate that the scope of the disclosure is intended to cover any aspect of this disclosure, whether implemented independently of or combined with any other aspect of the disclosure. For example, an apparatus may be implemented or a method may be practiced using any number of the aspects set forth herein. In addition, the scope of the disclosure is intended to cover such an apparatus or method which is practiced using other structure and/or functionality in addition to or instead of other aspects of this disclosure. It should be understood that any aspect of the disclosure disclosed herein may be embodied by one or more elements of a claim.

The various circuits described throughout this disclosure may be implemented in various forms of hardware. By way of example, any of these circuits, either alone or in combination, may be implemented as an integrated circuit, part of an integrated circuit, discrete hardware components, or any other suitable implementation designed to perform the functions described herein. The integrated circuit may be an end product, such as a microprocessor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), programmable logic, memory, or any other suitable integrated circuit. Alternatively, the integrated circuit may be integrated with other chips, discrete circuit elements, and/or other components as part of either an intermediate product, such as a motherboard, or an end product. The end product can be any suitable product that includes integrated circuits, including by way of example, a cellular phone, a personal digital assistant (PDA), a laptop computer, a desktop computer (PC), a computer peripheral device, a multimedia device, a video device, an audio device, a global positioning system (GPS), a wireless sensor, or any other suitable device.

FIG. 1is a functional block diagram illustrating an example of a pulse generator with feedback. The pulse generator100is shown with two stages. The first stage may be a latch104and the second stage may be a level shifter108. The latch104may be powered by a first voltage source VDD1and the level shifter108may be powered by a second voltage source VDD2. The first voltage source VDD1may be greater than the second voltage source VDD2, or alternatively, second voltage source VDD2may be greater than the first voltage source VDD1. In at least one embodiment, the pulse generator100may be configured to operate with voltage scaling for dynamic power reduction, wherein the first and second voltage sources VDD1and VDD2may scale independently of each other according to the workload requirements of the system. By way of example, the first voltage source VDD1may scale below the second voltage source VDD2if the system powered by the first voltage source VDD1has lower activity and needs to go into a low power state, and vice versa.

The input to the latch104includes an external trigger102and feedback112from the level shifter108. In at least one embodiment, the external trigger102may be a clock or other periodic signal. As will be described in greater detail later, the latch104generates a pre-pulse106in the VDD1domain in response to the input. The level shifter108generates a pulse110in the VDD2domain in response to the pre-pulse106.

FIG. 2is a schematic representation illustrating an example of a pulse generator with feedback. The operation of the pulse generator will be described in connection with two logic states represented by two voltage bands: one near the supply voltage and one near the supply voltage return, typically ground. The term “high” may be used to reference the band near the supply voltage. By way of example, the term “high” used to describe the operation of a circuit in the VDD1domain means that the voltage is in a band near the supply voltage VDD1. The same applies for the VDD2domain. The term “low” may be used to reference the band near the supply voltage return or ground.

Returning toFIG. 2, the pulse generator100is shown with a latch104and a level shifter108. As described earlier, the latch104provides a means for generating a pre-pulse106from an input comprising an external trigger102and feedback112from the level shifter108, and the level shifter108provides a means for generating a pulse110from the pre-pulse106.

In at least one embodiment, the latch104is configured as an SR latch with a gated output. In this embodiment, the SR latch202is constructed from a pair of cross-coupled NOR gates204,206. Specifically, the output of the NOR gate204is coupled to a first input of the NOR gate206and the output of the NOR gate206is coupled to a first input of the NOR gate204. An external trigger is coupled to a second input of the NOR gate206and feedback from the level shifter108is coupled to a second input of the NOR gate204. The output from the NOR gate204is the Q output of the SR latch202and the output from the NOR gate206is the complimentary Q* output of the SR latch202. In operation, the external trigger102is used to set the SR latch202(i.e., force the Q output high) and the feedback112from the level shifter108is used to reset the SR latch202(i.e., force the Q output low). In at least one embodiment, the sizing of the NOR gate204may be skewed for strong NMOS and weak PMOS transistors so that the NOR gate204acts as another level shifter between the feedback112in the VDD2domain and the Q output of the NOR gate204in the VDD1domain.

With both the external trigger102and the feedback112from the level shifter108low, the cross-coupling between the two NOR gates204,206maintains the state of the SR latch202. The SR latch202is set by driving the external trigger102high with the feedback112from the level shifter108low. The SR latch202remains set when the external trigger returns to low. Similarly, the SR latch202is reset by driving the feedback112from the level shifter108high with the external trigger102low. The SR latch202remains reset when the feedback112from the level shifter108returns to low.

In the embodiment shown, the complimentary output Q* from the SR latch202is gated with external trigger102. Specifically, the Q* output from the SR latch202is coupled to a first input of a NOR gate208and the external trigger102is coupled to a second input of the NOR gate208. The output of the NOR gate208is the pre-pulse106A that is provided to the level shifter108. The pre-pulse106is also provided to an inverter210. The inverter210provides an inverted pre-pulse106B to the level shifter108. As will be explained in greater detail later, the level shifter108generates a pulse110in a different voltage domain from the pre-pulse106A and the inverted pre-pulse106B.

In operation, the rising edge of the external trigger102is used to set the SR latch202. The Q* output from the SR latch202is forced low when the SR latch202is set. With the Q* output from the SR latch202low, the NOR gate208is enabled. Specifically, the NOR gate208acts as an inverter for the external trigger102when the Q* output from the SR latch202is low, thereby setting the pre-pulse106high with the falling edge of the external trigger102. The level shifter108generates a pulse110in the VDD2domain from the pre-pulse106A (and the inverted pre-pulse106B) generated in the VDD1domain. The transition of the leading edge of the pulse110forces the feedback112provided to the SR latch104high. The feedback resets the SR latch202and forces the Q* output high. The Q* output, in turn, disables the NOR gate208, which forces the pre-pulse106low regardless of the state of the external trigger102.

The level shifter108may take on various forms depending upon the particular application and design requirements. In at least one embodiment, the level shifter108may be implemented as a CMOS level shifter. The CMOS level shifter includes a pair of NMOS transistors212,214with their sources coupled to ground, a pair of PMOS transistors220,222with their sources coupled to VDD2, and a pair of cross-coupled PMOS transistors216,218. The PMOS transistor216has a source coupled to the drain of the PMOS transistor220and a drain coupled at a node N1to the drain of the NMOS transistor212. The pulse110generated by the level shifter108is output from the node N1and provides a voltage swing between VDD2and ground. The PMOS transistor218has a source coupled to the drain of the PMOS transistor222and a drain coupled at a node N2to the drain of the NMOS transistor214. The gate of the PMOS transistor216is coupled to the node N2and the gate of the PMOS transistor218is coupled to the node N1.

The level shifter is operated in the VDD2domain and does not have access to the VDD1domain other than the pre-pulse be converted. The pre-pulse106A is coupled to the NMOS transistor212and the inverted pre-pulse106B is coupled to the NMOS transistor214.

When the pulse generator100is inactive, the pre-pulse106A is low and the inverted pre-pulse106B is high. In this state, the pre-pulse106A turns on the PMOS transistor216and turns off the NMOS transistor212. The inverted pre-pulse106B turns off the PMOS transistor222and turns on the NMOS transistor214. The node N2is pulled down to ground through the NMOS transistor214, which turns on the PMOS transistor216. The pulse110output from the level shifter108at node N1is pulled up to VDD2through the PMOS transistors216,220, which turns off the PMOS transistor218. The pulse110is also provided to an inverter224in the level shifter108. The inverter224is used to provide the inverted pulse as feedback112to the latch104.

As discussed earlier in connection with the latch104, the pre-pulse106A is forced high with the falling edge of the external trigger102. With the pre-pulse106A high, the PMOS transistor220is turned off and the NMOS transistor212is turned on. The inverted pre-pulse106B turns on the PMOS transistor222and turns off the NMOS transistor214. The pulse110output from the level shifter108at the node N1is pulled down to ground through the NMOS transistor212, which turns on the PMOS transistor218. The node N2is then pulled up to VDD2, through the PMOS transistors218,222, which turns off the PMOS transistor216. The inverted pulse, which is high, is provided by the inverter224to the latch104as feedback112to reset the SR latch202and force the pre-pulse106A low. This ensures that the pre-pulse106remains high until after the pulse110generated by the level shifter108has fully transitioned from VDD2to ground.

Once the pre-pulse106A is forced low by the feedback112, the level shifter is forced back into its inactive state with the PMOS transistor220turned on and the NMOS transistor212turned off by the pre-pulse106A, and the PMOS transistor222turned off and the NMOS transistor214turned on by the inverted pre-pulse106B. The node N2is pulled down to ground through the NMOS transistor214, which turns on the PMOS transistor216. The pulse110output from the level shifter108at node N1is pulled back up to VDD2through the PMOS transistors216,220, which turns off the PMOS transistor218. The inverted pulse is forced low and provided to the latch as feedback112.

The inverter224provides both a means for inverting the pulse110to provide feedback to the latch104and a means for delaying the feedback. Additional delay elements (not shown) may be added in the feedback path to increase the delay, and thereby increase the width of the pulse110. The delay elements may be a series of inverters or other devices.

FIG. 3is a timing diagram illustrating an example of the operation of a pulse generator. The pre-pulse106A is generated by the latch104in response to the falling edge of the external trigger102. The pre-pulse106A is output from the latch104to the level shifter108to generate the pulse110. In this example, the pulse110is triggered by the rising edge of the pre-pulse106A. The inverted pulse is provided to the latch as feedback112. Specifically, once the pulse110fully transitions from VDD2to ground, the feedback signal112is forced high. As described earlier, the feedback to the latch104may be delayed by a series of delay elements in the feedback path to increase the width of the pulse110. The feedback is used to reset the SR latch by forcing the Q output low, which in turn forces the complementary Q* output from the SR latch high. The rising edge of the Q* output forces the pre-pulse106A back to a low state, which in turn forces the pulse110back to a high state. The feedback signal112is forced low with the rising edge of the pulse110. The SR latch is then set with the next rising edge of external trigger102, which forces the Q output high and the Q* output low.

The SR latch may be used when the pulse is passed from a high voltage domain to a low voltage domain. However, when the pulse is being passed from a low voltage domain to a high voltage domain, the SR latch may be omitted.FIG. 4is a schematic representation illustrating an example a pulse generator having this embodiment. The pulse generator100is shown with two stages. The first stage may be a NOR gate208and inverter210and the second stage may be a level shifter108. The level shifter108may be the same as described earlier and is reproduced here inFIG. 4. Alternatively, the level shifter108may take on another form. In any event, the pulse110is inverted by the inverter224and provided directly to the first input of the NOR gate208as feedback112. The external trigger102is provided to the second input of the NOR gate208. The output from the NOR gate208is coupled to the level shifter108as the pre-pulse106A. The output is also provided to the inverter210which is used to provide an inverted pre-pulse106B to the level shifter108.

When the pulse generator100is inactive, the pulse110output from the level shifter108is high and the feedback112provided to the NOR gate208is low. The low feedback signal112enables the NOR gate208to act as an inverter for the external trigger102. When the external trigger102transitions from a high state to a low state, the pre-pulse106A output from the NOR gate208is forced high and the inverted pre-pulse106B is forced low. As explained in greater detail earlier, this forces the pulse110at the output of the level shifter to transition from VDD2to ground. Once the pulse110transitions, the feedback provided to the NOR gate208is forced high. The high feedback signal disables the NOR gate208forcing the pre-pulse106output low regardless of the state of the external trigger102. When the pre-pulse106transitions low, the pulse110output from the level shifter108is forced back into the high state.