Transmitting circuit, receiving circuit, interface switching module and interface switching method for SATA and SAS interfaces

A transmitter circuit, a receiver circuit and an interface switching module for SATA or SAS interface are provided. The invention uses transistors as elements with different impedance and also provides impedance modulating method in coordination with the exterior circuit and the layout design so as to develop an auto-switching mechanism between SATA and SAS interfaces, thereby integrating two transmission interfaces in a single system.

This application claims the benefit of the filing date of Taiwan Application Ser. No. 094136259, filed on Oct. 18, 2005, the content of which is incorporated herein by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The invention generally relates to a computer transmission interface, and more specifically to a transmitting circuit, a receiving circuit, a transceiver circuit, an interface switching module and an interface switching method for Serial Advanced Technology Attachment (SATA) and Serial Attached Small Computer System Interface (SAS).

2. Description of the Related Art

FIG. 1is a circuit diagram of a transmitting circuit in accordance with the SATA and the SAS standards.FIG. 2is a circuit diagram of a receiving circuit in accordance with the SATA and the SAS standards.

Referring toFIG. 1andFIG. 2, a transmitting circuit100, including a switch110and two variable resistors101, receives a transmitting data signal TXD to generate a first transmitting signal TXP and a second transmitting signal TXN. A receiving circuit200, including a differential amplifier210and two variable resistors101, receives a first receiving signal RXP and a second receiving signal RXN to generate a receiving data signal RXD. High-speed serial transmission interface specifications, such as SATA and SAS, define 50-ohm differential impedance elements101embedded in the transmitting circuit or the receiving circuit for impedance matching. Thus, when high-speed serial signals are transmitted via physical layer, even too much cyclic redundancy check (CRC) errors do not cause communication link failure. However, precision resistors are used as differential impedance elements in prior art but are not operable in impedance modulation.

Traditionally, a host or a device having same or different transmission interfaces uses a plurality of bridges for data transmission. A minimum of three transceivers is required for a bridge with a switching mechanism among a plurality of high-speed serial signals under the current SATA and SAS architecture, which is complex and high-cost in hardware design. If a plurality of transmission interfaces can be integrated in a single unit, it will significantly meet the convenience in use and reduce use cost.

SUMMARY OF THE INVENTION

In view of the above-mentioned problems, an object of the invention is to provide an interface switching module, by means of impedance modulation, for a system with a plurality of same or different transmission interfaces.

To achieve the above-mentioned object, the interface switching module, for a system with two serial transmission interfaces, comprises a first interface connector, a second interface connector and a transceiver circuit.

The first interface connector has a first transmitting signal pin, a second transmitting signal pin, a first receiving signal pin, a second receiving signal pin and a plurality of ground pins. All the ground pins are connected to the ground terminal of the system. A second interface connector has the same four signal pins as those of the first interface connector and a plurality of ground pins. At least one among the plurality of ground pins is floated. The four signal pins of the first interface connector are connected to the corresponding four signal pins of the second interface connector. At least one among the plurality of ground pins of the second interface connector is electrically connected to the plurality of ground pins of the first interface connector. According to the potential of the floated ground pin of the second interface connector, the transceiver circuit identifies whether there is a signal input from the second interface connector or not. When there is a signal input from the second interface connector, the transceiver circuit modulates the matching impedance of itself to a high impedance value, and thereby signals from the second interface connector outputs via the first interface connector. Contrarily, when there is no signal input from the second interface connector, the transceiver circuit modulates the matching impedance of itself to a predetermined impedance value, and thereby signals from the transceiver circuit output via the first interface connector.

Another object of the invention is to provide an interface switching method for a system having an interface switching module that switches between a first serial transmission interface and a second serial transmission interface. The interface switching method comprises: connecting the system with a first device having the first serial transmission interface; determining whether a second device having the second serial transmission interface is connected to the system; if the second device is connected to the system, disconnecting the system from the first device by using an impedance modulating method, and then returning to the step of determining; and if the second device is not connected to the system, connecting the system with the first device by using the impedance modulating method, and then returning to the step of determining.

A unique feature of the invention is that transistors are substituted for precision resistors as differential impedance elements embedded in the transmitting or receiving circuit of the physical layer transceiver. Also, by using the impedance modulating method, the invention not only has the same effect as precision resistors do, but also performs a switching function among high-speed serial signal flows, thereby developing a switching mechanism of a plurality of transmission interfaces.

DETAILED DESCRIPTION OF THE INVENTION

The transmitting circuit, the receiving circuit, the transceiver circuit, the interface switching module and method of the invention will be described with reference to the accompanying drawings.

FIG. 3Ais a circuit diagram of a transmitting circuit according to the invention. Referring toFIG. 3A, the transmitting circuit300, applied to the SATA and SAS interfaces, comprises two resistor units322,332, two switch units321,331, an auto-detection circuit310and a current source341.

According to the potential of an external reference signal, the auto-detection circuit310disables or enables a control signal in order to control or modulate the equivalent impedance of resistor units322,332, thereby controlling the transmission of data signals. Resistor units322,332are in the control of the control signal. When the control signal is enabled, the equivalent impedances of resistor units322,332are modulated to a predetermined impedance value (for example: 50 ohm). On the other hand, when the control signal is disabled, the equivalent impedances of resistor units322,332are modulated to a high impedance value. The input terminals of resistor units322,332are connected to a voltage source VCC, and the output terminals of resistor units322,332are connected to switch units321,331respectively. Switch units321,331respectively receive a transmitting data signal TXD and a reversed transmitting data signal /TXD. While the equivalent impedances of resistor units322,332are modulated to a predetermined impedance (Hi-Z) value, switch units321,331control the current flow directions of a first transmitting signal TXP and a second transmitting signal TXN. That is, the current flow first goes out along the direction of the second transmitting signal TXN and then comes in the reverse direction of the first transmitting signal TXP. While the equivalent impedances of resistor units322,332are modulated to a high impedance value, the first transmitting signal TXP and the second transmitting signal TXN are at high impedance state, and therefore no signal is output.

FIG. 3Bis a circuit diagram of a transmitting circuit according to the first embodiment of the invention. Referring toFIG. 3B, the transmitting circuit360comprises two enhancement PMOS transistors322a,332a, two enhancement NMOS transistors321a,331a, an auto-detection circuit310and a current source341. In this embodiment, the resistor unit322(332) inFIG. 3Ais implemented by using an enhancement PMOS transistor322a(332a). While working in the ohmic region, the enhancement PMOS transistor acts as a voltage variable resistor based on its own characteristic. According to the transistor specification, the invention modulates the equivalent impedance of the enhancement PMOS transistor to 50 ohm. While working in the cut-off region, the enhancement PMOS transistor acts as a turn-off switch (at a high impedance state). Furthermore, the resistor unit321(331) inFIG. 3Ais implemented by using an enhancement NMOS transistor321a(331a) in this embodiment. Thus, the impedance match is achieved through the equivalent impedances of the enhancement PMOS transistors equal to 50 ohm, and therefore the enhancement NMOS transistors321a,331acan respectively receive the transmitting data signal TXD and the reversed transmitting data signal /TXD to generate the first transmitting signal TXP and the second transmitting signal TXN. When transistors322a,332awork in the cut-off region, the first transmitting signal TXP and the second transmitting signal TXN are at high impedance state, and thus no signal is output.

FIG. 3Cis a circuit diagram of a transmitting circuit according to the second embodiment of the invention. Referring toFIG. 3C, the transmitting circuit370is quite similar to the transmitting circuit360, except for having two 50-ohm resistors322b,332b. In this embodiment, the resistor unit322(332) is implemented by using a 50-ohm resistor322b(332b) cascaded an enhancement PMOS transistor322a(332a) as shown inFIG. 3C. For this situation, the enhancement PMOS transistor322a(332a) is configured as a switch. Due to the small impedance of transistor322a(332a), the 50-ohm impedance for impedance matching is entirely provided by resistors322b(332b). Since the operations of the other devices included in the transmitting circuit370are illustrated above, the description is omitted here.

FIG. 3Dis a circuit diagram of a transmitting circuit according to the third embodiment of the invention. Referring toFIG. 3D, the transmitting circuit380is similar to the transmitting circuit370. With the resistor322b(332b) and the enhancement PMOS transistor322a(332a) having been exchanged with each other in the position, the transmitting circuit380performs the same operations as the transmitting circuit370does.

FIG. 4Ais a circuit diagram of a receiving circuit according to the invention. Referring toFIG. 4A, the receiving circuit400, applied to the SATA and SAS interfaces, comprises two resistor units322,332, two receiving units421,431, an auto-detection circuit310, a differential amplifier210and two current sources441,442.

The input terminals of the resistor units322,332respectively receive a first receiving signal RXP and a second receiving signal RXN, and are simultaneously controlled by the control signal output from the auto-detection circuit310. When the control signal is enabled, the equivalent impedance of the resistor unit322(332) is modulated to a predetermined impedance value (for example, 50 ohm). On the other hand, the equivalent impedance of the resistor unit322(332) is modulated to a high impedance value while the control signal is disabled. While the output terminals of the receiving units421,431are grounded, the input terminals443,444are respectively connected to the current source441,442and the input terminals445,446receive the first receiving signal RXP and the second receiving signal RXN, so that the input terminals443,444respectively generate a differential signal DR1and a differential signal DR2. After receiving the differential signal DR1and the differential signal DR2, the differential amplifier210amplifies the difference of two signals DR1, DR2and then generates the receiving data signal RXD. As mentioned above, the auto-detection circuit310enables or disables the control signal to control or modulate two resistor units322,332for impedance matching according to the potential of the external reference signal, thereby controlling the data signal transmission.

FIG. 4Bis a circuit diagram of a receiving circuit according to the first embodiment of the invention. Referring toFIG. 4B, the receiving circuit460comprises two enhancement NMOS transistors322c,332c, two enhancement PMOS transistors421a,431a, an auto-detection circuit310, a differential amplifier210and two current sources441,442. In this embodiment, the resistor unit322(332) and the receiving unit421(431) inFIG. 4Aare respectively implemented by using an enhancement NMOS transistor322c(332c) and an enhancement PMOS transistor421a(431a). The control signal is disabled or enabled by the auto-detection circuit310, and then is used to modulate the equivalent impedance of the transistor322c(332c) to 50 ohm for establishing data signal transmission or a high impedance value for terminating data signal transmission. If the control signal is disabled, the equivalent impedances of the transistors322c,332care modulated to high impedance values such that the first receiving signal RXP and the second receiving signal RXN are incapable of passing through NMOS transistors322c,332c, and PMOS transistors421a,431acannot be turned on. Contrarily, the equivalent impedances of the resistor units322c,332care modulated to a predetermined impedance value if the control signal is enabled. Consequently, the first receiving signal RXP and the second receiving signal RXN not only pass through NMOS transistors322c,332c, but also pull down the potentials of the input terminals445,446, so that PMOS transistors421a,431aare switched on and then the differential signal DR1and the differential signal DR2are correspondingly generated.

FIG. 4Cis a circuit diagram of a receiving circuit according to the second embodiment of the invention. Referring toFIG. 4C, the receiving circuit470is quite similar to the receiving circuit460, except for having two 50-ohm resistors322b,332b. In this embodiment, the resistor unit322(332) is implemented by using a 50-ohm resistor322b(332b) cascaded an enhancement NMOS transistor322c(332c) as shown inFIG. 4C. For this situation, the enhancement NMOS transistor322c(332c) acts like a switch and has a very small impedance. Thus, the 50-ohm impedance value for impedance matching is entirely provided by resistors322b(332b). Since the other devices included in the receiving circuit470are illustrated above, the description of the operations is omitted here.

FIG. 4Dis a circuit diagram of a receiving circuit according to the third embodiment of the invention. Referring toFIG. 4D, the receiving circuit480is similar to the receiving circuit470. With the resistor322b(332b) and the enhancement NMOS transistor322c(332c) having been exchanged with each other in the position, the operation of the receiving circuit480is also similar to that of the receiving circuit470.

In practice, only one auto-detection circuit310is required to simultaneously control the start-up and shut-down of the transmitting and the receiving circuits.FIG. 5is a circuit diagram of a transceiver circuit with switching function according to the invention. Referring toFIG. 5, the transceiver circuit500comprises an auto-detection circuit310, two resistor units322, two resistor units332, two receiving units421,431, two switch units321,331, a differential amplifier210and three current sources341,441,442. The operation of the transceiver circuit500is the same as that of the transmitting circuit300and that of the receiving circuit400. The transceiver circuit500combines the two circuits300,400which is controlled by a single auto-detection circuit310.

Summarily, the invention uses transistors as differential impedance elements in the physical layer transceiver, and also uses the auto-detection circuit310for modulating the equivalent impedance of the transistors to a predetermined value (50 ohm) or high impedance values, thereby setting the enable/disable state of the connection. When the equivalent impedances of the transistors are modulated to a predetermined value, the impedance matching is constituted and then data transmission is under way. When the equivalent impedances of the transistors are modulated to be high impedance values, the connection between terminal equipment and the system is terminated. This is hereinafter called impedance modulating method.

Accordingly, the invention covers the group consisting of serial signal interfaces, such as serial ATA (SATA), serial attached small computer system interface (SAS), high definition multimedia interface (HDMI), peripheral controller interface express (PCI-EXP), and low voltage differential signal (LVDS). By incorporating the above-mentioned impedance modulating method with the exterior circuitry and layout design, the invention is applicable to a system with two or more serial transmission interfaces, and thereby develops a switching mechanism among a plurality of different serial signal transmission interfaces. The switching mechanism among a plurality of different serial signal transmission interfaces will be hereinafter detailed.

FIG. 6Ais a circuit diagram of a device with an interface switching module according to an embodiment of the invention. Referring toFIG. 6A, the interface switching module630is applied to (or embedded in) a device600with two different serial signal transmission interfaces. The device600comprises components, such as a microprocessor605, a random access memory (not shown) or a read only memory (not shown), to execute other operations or functions. The interface switching module630comprises a SATA connector610, a E-SATA connector620and a transceiver circuit500. In this embodiment, the transceiver circuit500and the microprocessor605are integrated into a single chip606, and also integrated with the SATA connector610and the E-SATA connector620into a printed circuit board (PCB).

Due to transferring the same signals, both the SATA connector610and the E-SATA connector620have the same signal pins transferring the first transmitting signal TXP, the second transmitting signal TXN, the first receiving signal RXP and the second receiving signal RXN, and both also have three ground signals GND (not shown). The three ground signal pins of the SATA connector610are connected to the ground terminal of the device or the PCB. One side of the SATA connector610is connected to a SATA bus, and the other side is a socket capable of receiving the plug-in of the cable641being connected to the SATA device640. The E-SATA connector620is also connected to the SATA bus, but one of the three ground pins is floated with the other ground pins being connected to the three ground pins of the SATA connector610. Four signal pins TXP, TXN, RXP, RXN of the SATA bus are connected to the corresponding pins of the transceiver circuit500. The floated ground pin of the E-SATA connector620is connected to the auto-detection circuit310and regarded as the reference signal for impedance modulation. One side of the E-SATA connector620is a socket, which is capable of receiving the plug-in of the cable651being connected to the E-SATA device650. Once the plug of the cable651being connected to the E-SATA device650is plugged into the E-SATA connector620, the potential of the floated ground pin of the E-SATA connector620is then pulled down to zero owing to the three ground pins of the cable651being all connected to ground. At this moment, the auto-detection circuit310detects the zero-voltage potential of the reference signal and then modulates the input and the output terminals of the transceiver circuit500to a high impedance state, thus allowing the transmission between the SATA device640and the E-SATA device650.

The above-mentioned description of the switching mechanism between E-SATA and SATA interfaces is only an embodiment. In applications, the invention can be extended to general serial signal transmission interfaces, such as SAS, HDMI, PCI-EXP, LVDS . . . etc. For simplicity, hereinafter, device600, E-SATA device650and SATA device640inFIG. 6Aare renamed device A660, device B670and terminal equipment680inFIGS. 6B,6C.

FIG. 6Bshows the relationship and signal flows among device A660with an interface switching module, device B670and terminal equipment680.FIG. 6Cis a flow chart illustrating the interface switching method used in the interface switching module.

Referring toFIGS. 6B,6C, initially, in step S661, the device A660is connected to the terminal equipment680via the serial signal bus, and data exchange is performed between the device A660and the terminal equipment680. Then, in step S662, the auto-detection circuit310determines whether the device B670is plugged into the E-SATA connector620or not. The control circuit, shown inFIG. 6B, represents the reference signal as the floated ground pin of the E-SATA connector620inFIG. 6A. According to the potential of the reference signal, the auto-detection circuit310determines whether the device B670is plugged in or not. If the potential of the reference signal is equal to zero, it represents that the device B670has been plugged into the E-SATA connector620. In step S663, the auto-detection circuit310immediately modulates the equivalent impedance of resistor units322,332to high impedance (Hi-Z) values (the impedance matching method). Thus, the connection between the device A660and the terminal equipment680is terminated so as to allow the data exchange between the device B670and the terminal equipment680. Afterward, in step S664, the auto-detection circuit310continuously monitors the connection status of the device B670and the flow returns to step S662. In step662, if the potential of the reference signal is equal to 1, it means that the plug of the device B670has been removed from the E-SATA connector620. In step S665, the auto-detection circuit310immediately modulates the equivalent impedance of resistor units322,332to a standard impedance value (the impedance matching method) to establish the connection between the device A660and the terminal equipment680. Lastly, in step666, the data transmission between the device A660and the terminal equipment680is performed. In step S664, the auto-detection circuit310continuously monitors the connection status of the device B670and the flow returns to step S662.

According to the invention, the feature of the interface switching module630is sharing a serial signal data bus. Accordingly, while the device B670exists, the device A with the interface switching module630breaks up the connection with the terminal equipment680. While the device B670doesn't existed, the device A with the interface switching module630establishes the connection with the terminal equipment680to avoid the serial signal bus conflict.

Based on cost, design simplicity and convenience, IC designers achieve the same effect as prior art does by using the impedance modulating method. The invention not only saves time and cost of research and development, but also solves the noise and timing delay problems upon internal high speed switching. With a plurality of transmission interfaces having been integrated in a single unit, all the system designers have to do is simply think up the hardware layout, thus significantly reducing product cost.

While certain exemplary embodiments have been described and shown in the accompanying drawings, it is to be understood that such embodiments are merely illustrative of and not restrictive on the broad invention, and that this invention should not be limited to the specific construction and arrangement shown and described, since various other modifications may occur to those ordinarily skilled in the art.