Phase change RAM device

Disclosed are a phase change RAM device and a method for fabricating a phase change RAM device, which can efficiently lower intensity of current required for changing a phase of a phase change layer. The method includes the steps of providing a semiconductor substrate formed with an insulating interlayer including a tungsten plug, forming a first oxide layer on the semiconductor substrate, forming a pad-type bottom electrode, which makes contact with the tungsten plug, in the first oxide layer, forming a second oxide layer on the first oxide layer including the bottom electrode, and forming a porous polystyrene pattern on the second oxide layer such that a predetermined portion of the second oxide layer corresponding to a center portion of the bottom electrode is covered with the porous polystyrene pattern.

FIELD OF THE INVENTION

The present invention relates to a phase change RAM device. More particularly, the present invention relates to a method for fabricating a phase change RAM device, which can lower the intensity of current required for changing a phase of a phase change layer.

DESCRIPTION OF THE PRIOR ART

As generally known in the art, semiconductor memory devices are generally classified into volatile random access memory (RAM), which loses information stored therein when power is cut off, and non-volatile read only memory (ROM), which continuously retains information stored therein even if power is cut off. Volatile RAM includes dynamic RAM (DRAM) and static RAM (SRAM). Non-volatile ROM includes flash memory such as an electrically erasable and programmable ROM.

As is generally known to those skilled in the art, DRAM memory devices store data by storing electric charges in a capacitor. The charge storage capability of a capacitor is related to the spacing between electrodes, the material between electrodes and the surface area of the electrodes. While DRAM is a memory device known to have superior performance, DRAMs must include storage capacitors, which occupy space in a semiconductor device. Thus a DRAM presents a problem in view of high integration.

Flash memory devices do not require capacitors to store data as do DRAMs but flash memory devices require operational voltages higher than their nominal supply voltage because the flash memory has a stacked structure of two gates. Accordingly, the flash memory must additionally have a booster circuit in order to obtain voltage required for writing and deleting operations, so it is difficult to highly integrate the flash memory.

Many researches have been performed in order to develop new highly integrated memory devices having a simple structure with characteristics of the non-volatile memory devices. As one example of the new highly integrated memory devices, a phase change RAM device has recently been suggested.

The phase change RAM device determines information stored in a cell according to a resistance difference between a crystalline state and an amorphous state of a phase change layer based on the fact that the phase change layer interposed between bottom and top electrodes undergoes phase change from the crystalline state to the amorphous state as the current flows between the bottom and top electrodes.

In other words, the phase change RAM device employs a chalcogenide layer as the phase change layer, and such a chalcogenide layer is a compound layer including Ge, Sb, and Te. The chalcogenide layer undergoes phase change between an amorphous state and a crystalline state as current, that is, joule heat is applied thereto. In this case, since the resistivity of the phase change layer having the amorphous state is higher than the resistivity of the phase change layer having the crystalline state, it is determined whether the information stored in a phase change memory cell is logic “1” or logic “0” by detecting current flowing through the phase change layer in reading and writing modes.

FIG. 1is a sectional view illustrating the conventional phase change RAM device.

As shown inFIG. 1, gates4are formed on an active area of a semiconductor substrate1, which is defined by an isolation layer, and a junction area (not shown) is formed on the semiconductor substrate at both sides of the gates4.

An insulating interlayer5is formed on an entire surface of the semiconductor substrate1in such a manner that the insulating interlayer5covers the gates4. A first tungsten plug6aand a second tungsten plug6bare formed at predetermined portions of the insulating interlayer5where a phase change cell is formed and a ground voltage (Vss) is applied, respectively.

A first oxide layer7is formed on the insulating interlayer5having the first tungsten plug6aand the second tungsten plug6b. Although it is not shown in detail, a dotted metal pad8is formed at an area to be provided with the phase change cell such that the dotted metal pad8can make contact with the first tungsten plug6a, and a bar-type ground line9(a Vss line) is formed at an area, to which the ground voltage is applied, such that the bar-type ground line9(the Vss line) can make contact with the second tungsten plug6b.

A second oxide layer10is formed on the first oxide layer7having the metal pad8and the bar-type ground line9(the Vss line), and a plug-type bottom electrode11is formed in a predetermined portion of the second oxide layer10to be provided with the phase change cell such that the plug-type bottom electrode11can make contact with the metal pad8.

A phase change layer12and a top electrode13are sequentially stacked on the second oxide layer10in the form of a pattern such that the phase change layer12and the top electrode13can make contact with the bottom electrode11. Accordingly, the phase change cell including the plug-type bottom electrode11, the phase change layer12stacked on the plug-type bottom electrode11and the top electrode13stacked on the phase change layer12is formed.

In addition, a third oxide layer14is formed on the second oxide layer10such that the third oxide layer14can cover the phase change cell, and metal wiring15is formed on the third oxide layer14such that the metal wiring15can make contact with the top electrode13.

Meanwhile, such a phase change RAM device requires higher current (e.g., current exceeding 1 mA) in order to change the phase of the phase change layer. Thus, it is necessary to lower intensity of current required for the phase change of the phase change layer by reducing a contact area between the phase change layer and the electrode. To this end, conventionally, the plug-type bottom electrode having the size smaller than 100 nm is formed through an electron-beam process (E-beam process).

However, since the E-beam process is unstable, it is difficult to precisely form the bottom electrode having a desired size through the E-beam process. In particular, it is impossible to uniformly form the bottom electrode over the whole area of the semiconductor substrate through the E-beam process. For this reason, the contact area between the bottom electrode and the phase change layer is irregularly formed over the whole area of the semiconductor device, so the range of writing current of the phase change layer is increased.

SUMMARY OF THE INVENTION

In light of the foregoing problems in the prior art, an object of the present invention is to provide a phase change RAM device and a method for fabricating the same, which can efficiently reduce current required for changing a phase of a phase change layer.

Another object of the present invention is to provide a phase change RAM device and a method for fabricating the same, which can uniformly form the contact area between a bottom electrode and a phase change layer over the whole area of a semiconductor substrate.

To accomplish the above and other objects, there is provided a phase change RAM device including an oxide layer formed on a semiconductor substrate including a predetermined base layer, a pad-type bottom electrode formed in the oxide layer, a masking pattern formed on the bottom electrode so as to shield a center part of the bottom electrode and expose only a peripheral portion of the bottom electrode, a phase change layer formed on the oxide layer including the masking pattern and the exposed peripheral portion of the bottom electrode, and a top electrode formed on the phase change layer.

The masking pattern includes an oxide layer and has a nano size.

According to another aspect of the present invention, there is provided a method for fabricating a phase change RAM device, the method including the steps of providing a semiconductor substrate formed with an insulating interlayer including a tungsten plug, forming a first oxide layer on the semiconductor substrate, forming a pad-type bottom electrode, which makes contact with the tungsten plug, in the first oxide layer, forming a second oxide layer on the first oxide layer including the bottom electrode, forming a porous polystyrene pattern on the second oxide layer such that a predetermined portion of the second oxide layer corresponding to a center portion of the bottom electrode is covered with the porous polystyrene pattern, forming an oxide layer pattern exposing a peripheral portion of the bottom electrode while shielding the center portion of the bottom electrode by etching the second oxide layer using the porous polystyrene pattern, removing the porous polystyrene pattern, and sequentially forming a phase change layer making contact with the exposed peripheral portion of the bottom electrode and a top electrode on the second oxide layer including the oxide layer pattern and the exposed peripheral portion of the bottom electrode.

The bottom electrode is formed through a damascene process and includes one selected from the group consisting of TiN, TiW, Al, Cu, and WSi.

The porous polystyrene pattern is formed by removing poly-methyl-methacrylate from a diblock copolymer layer including polystyrene and poly-methyl-methacrylate using organic solvent.

The second oxide layer is etched using CHF3 gas and Ar gas.

The oxide layer pattern is formed with a nano size.

The phase change layer includes one selected from the group consisting of Ge—Sb—Te, Ge—Bi—Te, Sb—Te doped with at least one of Ag, In, and Bi, and Bi—Te doped with at least one of Ag, In, and Sn.

The top electrode includes one selected from the group consisting of Al, Ti, Ta, TaSiN, TaN, Ru, TiW, TiN and TiAlN.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

FIGS. 2ato2eare sectional views illustrating both a phase change memory device and the manufacturing procedure for a making a phase change RAM device.

Referring toFIG. 2a, a semiconductor substrate21having a base layer (not shown) is formed with an isolation layer and a transistor. Then, after forming an insulating interlayer22on the semiconductor substrate21such that the insulating interlayer22can cover the base layer, the surface of the insulating interlayer22is planarized.

Thereafter, the insulating interlayer22is etched in order to form a contact hole for exposing a predetermined portion of the semiconductor substrate to be provided with the phase change cell, that is, a drain area of a transistor. Then, a tungsten plug23making contact with the drain area is formed by filling the contact hole with a conductive layer (e.g., a tungsten layer).

Sequentially, a first oxide layer24is formed on the insulating interlayer22including the tungsten plug23. Then, according to a typical damascene process, the first oxide layer24is etched, thereby forming a hole for exposing the tungsten plug23and a pad-type bottom electrode25making contact with the tungsten plug23is formed by filling the hole with bottom electrode materials. The bottom electrode material includes TiN, TiW, Al, Cu, or WSi. Unlike the prior art technique in which a bottom electrode is formed through an E-beam process in order to reduce a contact area between the bottom electrode and a phase change layer, the bottom electrode25is formed through the damascene process, which is stably performed, so that the bottom electrode25can be easily formed. In addition, it is possible to uniformly form the bottom electrode over the whole area of the semiconductor substrate.

Referring toFIG. 2b, in order to form a masking pattern exposing only a peripheral portion of the bottom electrode25while shielding a center part of the bottom electrode25, a second oxide layer26is formed on the first oxide layer24including the bottom electrode25, and then a diblock copolymer layer27is formed on the second oxide layer26. Herein, the diblock copolymer layer27includes polystyrene (PS) and poly-methyl-methacrylate (PMMA) and has a structure provided with a hexagonal close-packed PMMA cylinder formed in a PS matrix.

Referring toFIG. 2c, a nano-sized porous PS pattern27ais formed on a predetermined portion of the second oxide layer26provided on the bottom electrode25by removing PMMA from the diblock copolymer layer using organic solvent. Then, the second oxide layer26is etched using CHF3 and Ar while employing the porous PS pastern27aas an etching barrier. Thus, a nano-sized oxide layer pattern26a, which exposes only a peripheral portion of the bottom electrode25while shielding the center part of the bottom electrode25, is formed.

Referring toFIG. 2d, an oxygen plasma process is performed with respect to the resultant substrate so as to remove the remaining porous PS pattern27a. Then, a phase change material layer28and a top electrode material layer29are sequentially deposited on the first oxide layer24including the oxide layer pattern26aand the exposed peripheral portion of the bottom electrode25.

Herein, the phase change material layer28includes Ge—Sb—Te, Ge—Bi—Te, Sb—Te doped with at least one of Ag, In, and Bi, or Bi—Te doped with at least one of Ag, In, and Sn. The top electrode material layer29includes Al, Ti, Ta, TaSiN, TaN, Ru, TiW, TiN, or TiAlN.

Referring toFIG. 2e, a top electrode29aand a phase change layer28aare formed by etching the phase change material layer28and the top electrode material layer29through any appropriate etching process. Thus, a phase change cell30including the pad-type bottom electrode25, the phase change layer28astacked on the pad-type bottom electrode25, and the top electrode29astacked on the phase change layer28ais formed.

Herein, since the bottom electrode25makes contact with the phase change layer28aat the peripheral portion of the bottom electrode25, it is possible to reduce the contact area between the bottom electrode25and the phase change layer28aas compared with that of the conventional technique. Therefore, according to the present invention, it is possible to efficiently lower intensity of writing current required for phase change of the phase change layer28aas compared with that of the conventional technique.

Thereafter, although it is not shown, typical following processes including a metal wiring process are sequentially performed, thereby obtaining the phase change RAM device according to the present invention.

As described above, according to the present invention, a phase change layer and a top electrode are formed under the state in which an oxide layer pattern exposing a peripheral portion of a bottom electrode while shielding a center part of the bottom electrode has been formed on the bottom electrode using a diblock copolymer layer, so that it is possible to reduce a contact area between the bottom electrode and the phase change layer as compared with that of the conventional technique. Accordingly, it is possible to efficiently reduce writing current required for phase change of the phase change layer.

In addition, according to the present invention, since a bottom electrode is fabricated in the form of a pad rather than a plug, it is easy to fabricate the bottom electrode.

Furthermore, according to the present invention, since the bottom electrode is fabricated in the form of a pad through a stable damascene process instead of an E-beam process, it is possible to uniformly form the bottom electrode over the whole area of a semiconductor substrate. Accordingly, it is possible to uniformly form the contact area between the bottom electrode and the phase change layer over the whole area of the semiconductor substrate, so that writing current in a chip can be lowered.