Three-dimensional semiconductor memory devices

Three-dimensional (3D) nonvolatile memory devices include a substrate having a well region of second conductivity type (e.g., P-type) therein and a common source region of first conductivity type (e.g., N-type) on the well region. A recess is provided, which extends partially (or completely) through the common source region. A vertical stack of nonvolatile memory cells are provided on the substrate. This vertical stack of nonvolatile memory cells includes a vertical stack of spaced-apart gate electrodes and a vertical active region, which extends on sidewalls of the vertical stack of spaced-apart gate electrodes and on a sidewall of the recess. Gate dielectric layers are provided, which extend between respective ones of the vertical stack of spaced-apart gate electrodes and the vertical active region. The gate dielectric layers may include a composite of a tunnel insulating layer, a charge storage layer, a relatively high bandgap barrier dielectric layer and a blocking insulating layer having a relatively high dielectric strength.

REFERENCE TO PRIORITY APPLICATION

This U.S. non-provisional patent application claims priority under 35 U.S.C. §119 to Korean Patent Application 10-2010-0091140, filed Sep. 16, 2010, the entire contents of which are hereby incorporated herein by reference.

BACKGROUND

The present disclosure herein relates to a semiconductor device and a method of fabricating the same and, more particularly, to a three-dimensional (3D) semiconductor memory device and a method of fabricating the same.

Due to characteristics such as miniaturization, multifunction and/or low-fabricating cost, semiconductor devices are getting the spotlight as an important factor in electronic industries. With the advance of electronic industries, requirements for the superior performances and/or low costs of semiconductor devices are increasing. For satisfying such requirements, high-integrating of semiconductor devices is growing. Particularly, high-integrating of semiconductor memory devices storing logical data is growing more.

In a degree of integration of typical Two-Dimensional (2D) semiconductor memory devices, planar areas that unit memory cells occupy may be main factors for deciding the degree of integration. Therefore, a degree of integration of the typical 2D semiconductor memory devices may be largely affected by the level of a technology for forming fine patterns. However, the technology for forming the fine patterns may be gradually reaching limitations, and also, the fabricating costs of semiconductor memory devices may increase because high-cost equipment is required. For solving such limitations, 3D semiconductor memory devices including three dimensionally-arranged memory cells have been proposed.

SUMMARY

Three-dimensional (3D) nonvolatile memory devices according to embodiments of the invention include a substrate having a well region of second conductivity type (e.g., P-type) therein and a common source region of first conductivity type (e.g., N-type) on the well region. A recess is provided in the substrate. In some embodiments of the invention, the recess extends partially through the common source region. A vertical stack of nonvolatile memory cells are provided on the substrate. This vertical stack of nonvolatile memory cells includes a vertical stack of spaced-apart gate electrodes and a vertical active region, which extends on sidewalls of the vertical stack of spaced-apart gate electrodes and on a sidewall of the recess. Gate dielectric layers are provided, which extend between respective ones of the vertical stack of spaced-apart gate electrodes and the vertical active region.

In other embodiments of the invention, the recess extends entirely through the common source region, which forms a P-N rectifying junction with the well region, and a sidewall of the recess defines an interface between the vertical active region and the well region. In addition, each of the gate dielectric layers may include a composite of: (i) a tunnel insulating layer in contact with the vertical active region, (ii) a charge storage layer on the tunnel insulating layer, (iii) a barrier dielectric layer on the charge storage layer; and (iv) a blocking insulating layer extending between the barrier dielectric layer and a respective gate electrode. In some of these embodiments of the invention, the barrier dielectric layer may be formed of a material having a greater bandgap relative to the blocking insulating layer. According to still further embodiments of the invention, a protective dielectric layer is provided on a sidewall of the recess. This protective dielectric layer extends between the vertical active region and the common source region. A bottom of the recess may also define an interface between the vertical active region and the well region. This vertical active region, which may have a cylindrical shape, may include a plurality of concentrically-arranged semiconductor layers of first conductivity type having equivalent or different dopant concentrations therein.

According to additional embodiments of the invention, the vertical stack of spaced-apart gate electrodes has an opening extending therethrough that is aligned to the recess. In addition, the gate dielectric layers may have a cylindrical shape, and may be concentrically-arranged relative to the plurality of concentrically-arranged semiconductor layers.

According to still further embodiments of the invention, the vertical active region includes an active region plug filling the recess and a cylindrically-shaped active layer on the active region plug. The cylindrically-shaped active layer includes a plurality of concentrically-arranged semiconductor layers of first conductivity type having equivalent or different doping concentrations therein. A vertical stack of at least two spaced-apart gate electrodes of respective ground selection transistors may also be provided, which extend opposite the active region plug. These ground selection transistors include respective gate dielectric layers that extend on sidewalls of the active region plug. The gate dielectric layers of the vertical stack of nonvolatile memory cells may be formed of different materials relative to the gate dielectric layers of the stacked ground selection transistors.

Methods of forming three-dimensional (3D) nonvolatile memory devices according to embodiments of the invention may include forming a vertical stack of a plurality of sacrificial layers and a plurality of insulating layers arranged in an alternating sequence, on a substrate. A selective etching step is then performed to etch through the vertical stack to define a first opening therein and a recess in the substrate. The recess is filled with an electrically conductive active region plug, which is electrically connected to a well region in the substrate. A sidewall of the first opening is then lined with a first vertical active layer before the first opening is filled with a dielectric pattern that extends on the first vertical active layer. Another selective etching step is performed to selectively etch through the vertical stack to define a second opening therein that exposes the substrate. Portions of the sacrificial layers extending between each of the plurality of insulating layers in the vertical stack are then replaced with gate dielectric layers and gate electrodes of respective memory cells. The step of lining a sidewall of the first opening may include lining a sidewall of the first opening with a first vertical active layer that contacts an upper surface of the active region plug. The step of filling the recess with an active region plug may also include filling the recess with an active region plug having an upper surface that is elevated relative to surface of the substrate. In particular, the substrate may include a well region of second conductivity type and a common source region of first conductivity type extending between the well region and a surface of the substrate, and the recess containing the active region plug may extend entirely through the common source region.

According to still further embodiments of the invention, the step of lining a sidewall of the first opening with a first vertical active layer may be preceded by a step of lining the sidewall of the first opening with a first electrically insulating sub-layer that contacts an upper surface of the active region plug. A step may also be performed to selectively etching through the first vertical active layer and the first electrically insulating sub-layer in sequence to expose the upper surface of the active region plug. In addition, the step of filling the first opening with a dielectric pattern may be preceded by lining an inner sidewall of the first vertical active layer with a second vertical active layer that contacts the upper surface of the active region plug. These first and second vertical active layers may be formed as doped or undoped cylindrically-shaped silicon layers.

DETAILED DESCRIPTION OF THE EMBODIMENTS

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the present invention. As used herein, the singular forms “a,” “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprising”, “including”, “having” and variants thereof, when used in this specification, specify the presence of stated features, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, steps, operations, elements, components, and/or groups thereof. In contrast, the term “consisting of” when used in this specification, specifies the stated features, steps, operations, elements, and/or components, and precludes additional features, steps, operations, elements and/or components.

Embodiments of the present invention are described herein with reference to cross-section and perspective illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the present invention. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, embodiments of the present invention should not be construed as limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, a sharp angle may be somewhat rounded due to manufacturing techniques/tolerances.

FIG. 1Ais a plan view illustrating a 3D semiconductor memory device according to an embodiment of the inventive concept.FIG. 1Bis a cross-sectional view taken along line I-I′ ofFIG. 1A.FIG. 1Cis a magnified view of a portion A ofFIG. 1B. Referring toFIGS. 1A and 1B, a well region102doped with a first conductive dopant may be disposed in a semiconductor substrate100(hereinafter referred to as a substrate). The substrate100may be a silicon substrate, a germanium substrate or a silicon-germanium substrate, for example a common source region105doped with a second conductive dopant may be formed in the well region102. An upper surface of the common source region105may be disposed on the substantially same level as that of the upper surface of the substrate100. A lower surface of the common source region105may be disposed on a level higher than that of a lower surface of the well region102. One of the first and second conductive dopants may be an n-type dopant, and the other may be a p-type dopant. For example, the well region102may be doped with a p-type dopant, and the common source region105may be doped with an n-type dopant.

A stack-structure, including insulation patterns110aand gate patterns155L,155a1,155aand155U that are stacked alternately and repeatedly, may be disposed on the common source region105. A plurality of the stack-structures may be disposed on the common source region105. As illustrated inFIG. 1A, the stack-structures may be extended side by side in a first direction. The stack-structures may be spaced apart in a second direction perpendicular to the first direction. The first and second directions may be parallel with the upper surface of the substrate100.

A vertical active pattern130may pass through the stack-structure. The vertical active pattern130may be extended into a recess region120that is formed in the common source region105under the vertical active pattern130. Therefore, the vertical active pattern130may be connected to the well region102under the vertical active pattern130. As illustrated inFIG. 1B, the recess region120may vertically pass through the common source region105. A bottom surface of the recess region120may be disposed on a level lower than that of the lower surface of the common source region105. The vertical active pattern130may contact the bottom surface of the recess region120. Accordingly, the vertical active pattern130may contact the well region102. Also, the vertical active pattern130may contact a sidewall of the recess region120. As a result, the vertical active pattern130may directly contact the common source region105.

According to an embodiment of the inventive concept, a portion122of the well region102just under the bottom surface of the recess region120may have a high dopant concentration. In other words, the first conductive dopant concentration of the portion122of the well region102may be higher than the first conductive dopant concentration of another portion of the well region102.

According to an embodiment of the inventive concept, the vertical active pattern130may have a hollow pipe shape or a macaroni shape. Herein, the lower end of the vertical active pattern130may be in a closed state. The inside of the vertical active pattern130may be filled with a filling dielectric pattern132.

A gate dielectric layer150may be disposed between a sidewall of the vertical active pattern130and each of the gate patterns155L,155a1,155aand155U. According to an embodiment of the inventive concept, as illustrated inFIG. 1B, the gate dielectric layer150may be extended to cover an upper surface and a lower surface of each of the gate patterns155L,155a1,155aand155U. That is, the extended portion of the gate dielectric layer150may be disposed between each of the gate patterns155L,155a1,155aand155U and the insulation pattern110aadjacent to each of the gate patterns155L,155a1,155aand155U.

The gate dielectric layer150will be described below in more detail with reference toFIG. 1C. Referring toFIG. 1C, according to an embodiment of the inventive concept, the gate dielectric layer150may include a tunnel dielectric layer141, a charge storage layer142and a blocking dielectric layer143. The tunnel dielectric layer141may be adjacent to the sidewall of the vertical active pattern130, and the blocking dielectric layer143may be adjacent to each of the gate patterns155L,155a1,155aand155U. The charge storage layer142may be disposed between the tunnel dielectric layer141and the blocking dielectric layer143. According to an embodiment of the inventive concept, as illustrated inFIG. 1C, the entirety of the gate dielectric layer150(i.e., the tunnel dielectric layer141, the charge storage layer142and the blocking dielectric layer143) may be extended to cover the upper and lower surfaces of each of the gate patterns155L,155a1,155aand155U.

The tunnel dielectric layer141may include oxide and/or oxynitride. The tunnel dielectric layer141may be single-layered or multi-layered. The charge storage layer142may include a dielectric material having traps for storing electric charges, for example, the charge storage layer142may include nitride and/or metal-oxide. The blocking dielectric layer143may include a high-k dielectric layer having a dielectric constant higher than that of the tunnel dielectric layer141. For example, the high-k dielectric layer in the blocking dielectric layer143may include metal-oxide such as aluminum-oxide or hafnium-oxide. Furthermore, the blocking dielectric layer143may further include a barrier dielectric layer. The barrier dielectric layer in the blocking dielectric layer143may include a dielectric material having a greater band gap than the high-k dielectric layer in the blocking dielectric layer143. For example, the barrier dielectric layer may include oxide. The barrier dielectric layer may be disposed between the high-k dielectric layer and the charge storage layer142.

A lowermost gate pattern155L in the stack-structure may correspond to a ground selection gate. A ground selection transistor including the lowermost gate pattern155L may include a vertical channel region that is defined in the sidewall of the vertical active pattern130. As illustrated inFIGS. 1A and 1B, the entire lower surface of the lowermost gate pattern155L may substantially overlap with the common source region105.

An uppermost gate pattern155U in the stack-structure may correspond to a string selection gate. Gate patterns155a1and155abetween the uppermost gate pattern155U and the lowermost gate pattern155L may correspond to cell gates. A string selection transistor including the uppermost gate pattern155U and cell transistors including the cell gates may also include vertical channel regions that are defined in the sidewall of the vertical active pattern130a. The vertical channel regions of the ground selection transistor, the cell transistor and the string selection transistor configuring one cell string may be defined in the vertical active pattern130.

According to an embodiment of the inventive concept, among gate patterns used as the cell gates in the stack-structure, a gate pattern most adjacent to the lowermost gate pattern155L may correspond to a dummy cell gate. For example, the gate pattern1551adisposed just on the lowermost gate pattern155L may be a dummy gate pattern. For example, the gate pattern155a1that is stacked secondly from the substrate100may be a dummy cell gate. Naturally, one of the insulation pattern110ais disposed between the lowermost gate pattern155L and the secondly-stacked gate pattern155a1. For example, a dummy cell transistor including the secondly-stacked gate pattern155a1may have the same shape as that of a cell transistor storing data, but may not serve as the cell transistor. For example, the dummy cell transistor may perform only a turn-on/off function. Thus, the secondly-stacked gate pattern155a1may be a second ground selection gate. In this case, the cell string may include a plurality of stacked ground selection transistors.

A plurality of the vertical active patterns130may pass through each of the stack-structures. As illustrated inFIG. 1A, the vertical active patterns130passing though each of the stack-structures may be arranged in the first direction to form one column. Alternatively, the vertical active patterns130passing though each of the stack-structures may be arranged in a zigzag shape in the first direction.

The vertical active pattern130may include a semiconductor material. For example, the vertical active pattern130may include the same semiconductor material as that of the substrate100. The vertical active pattern130may have an undoped state, or may be doped with the first conductive dopant. The vertical active pattern130may have a poly-crystalline state or a single crystalline state. The gate patterns155L,155a1,155aand155U include a conductive material. For example, the gate patterns155L,155a1,155aand155U may include at least one of a doped semiconductor (for example, doped silicon and others), a metal (for example, tungsten, aluminum, copper and others), a transition metal (for example, titanium, tantalum and others) or a conductive metal nitride (for example, a titanium nitride, a tantalum nitride and others). The insulation patterns110amay include oxide.

A device isolation pattern160amay be disposed between the stack-structures. An upper surface of the device isolation pattern160aand an upper surface of the stack-structure may substantially be coplanar. An interlayer dielectric165may be disposed on the substrate100. A contact plug167may be connected to an upper end of the vertical active pattern130through the interlayer dielectric165. A drain being doped with the second conductive dopant may be formed in the upper portion of the vertical active pattern130. A lower surface of the drain may be disposed on a level adjacent to an upper surface of the uppermost gate pattern155U. A bit line170may be disposed on the interlayer dielectric165, and may be connected to the contact plug167. The bit line170may be extended in the second direction and cross over the stack-structure. The interlayer dielectric165may include oxide. The contact plug167includes a conductive material. For example, the contact plug167may include tungsten. The bit line170also includes a conductive material. As an example, the bit line170may include tungsten, copper, aluminum or the like.

According to the above-described 3D semiconductor memory device, the vertical active pattern130may be disposed in the recess region120passing though the common source region105and be connected to the well region102. Moreover, the common source region105may be disposed under the lowermost gate pattern155L. Therefore, a distance between the vertical active pattern130and the common source region can be minimized, and also the vertical active pattern130can be connected to the well region102. Consequently, a current flowing through the vertical active pattern130can quickly flow to the common source region105. Accordingly, the reduction of an amount of current in a cell transistor can be minimized. Also, the vertical active pattern130is connected to the well region102, such that the erasing operation of cell transistors is very easy. As a result, the 3D semiconductor memory device can be implemented which has excellent reliability and is optimized for high integration.

Next, the modification examples of the 3D semiconductor memory device according to an embodiment of the inventive concept will be described below with reference to the accompanying drawings. In the modification examples, a description on the same elements as the above-described elements will be omitted for avoiding a repetitive description.

FIG. 2Ais a cross-sectional view taken along line I-I′ ofFIG. 1Afor describing a modification example of a 3D semiconductor memory device according to an embodiment of the inventive concept. Referring toFIG. 2Aand according to the modification example, protection dielectric patterns173amay be disposed between the insulation patterns110aand the vertical active pattern130and between the inner sidewall of the recess region120and the vertical active pattern130. The protection dielectric pattern173amay include a dielectric material for protecting the vertical active pattern130in a fabricating process. For example, the protection dielectric pattern173amay include oxide. According to the modification example, a capping semiconductor pattern175may be disposed on the vertical active pattern130. The capping semiconductor pattern175may also be disposed on the protection dielectric pattern173athat is disposed between an uppermost insulation pattern110aand the vertical active pattern130. The upper end of the vertical active pattern130may be disposed on a level lower than an upper surface of the uppermost insulation pattern110a. The upper surface of the capping semiconductor pattern175and the upper surface of the uppermost insulation pattern110amay be substantially coplanar. The capping semiconductor pattern175may include the same semiconductor material as that of the vertical active pattern130. The capping semiconductor pattern175may be doped with the second conductive dopant. The contact plug167may be connected to the capping semiconductor pattern175.

FIG. 2Bis a cross-sectional view taken along line I-I′ ofFIG. 1Afor describing other modification example of a 3D semiconductor memory device according to an embodiment of the inventive concept. Referring toFIG. 2Band according to the modification example, a bottom surface of the recess region120may be disposed on a level higher than the lower surface of the common source region105. In this case, a region122abeing counter-doped with the first conductive dopant may be disposed under the bottom surface of the recess region120a. The counter-doped region122amay contact the vertical active pattern130and the well region102. Therefore, the vertical active pattern130may be connected to the well region102through the counter-doped region122a.

FIG. 3Ais a cross-sectional view taken along line I-I′ ofFIG. 1Afor describing still other modification example of a 3D semiconductor memory device according to an embodiment of the inventive concept.FIG. 3Bis a magnified view of a portion B ofFIG. 3A. Referring toFIG. 3A, a gate dielectric layer150aaccording to the modification example may be disposed between a vertical active pattern130aand each of the gate patterns155L,155a1,155aand155U. The gate dielectric layer150amay include a first sub-layer147and a second sub-layer149. The first sub-layer147may be substantially extended vertically and be disposed between the vertical active pattern130aand the insulation pattern110a. The second sub-layer149may be substantially extended horizontally and cover the lower surface and upper surface of each of the gate patterns155L,155a1,155aand155U. The gate dielectric layer150amay include the tunnel dielectric layer, the charge storage layer and the blocking dielectric layer. Herein, the first sub-layer147may include at least a portion of the tunnel dielectric layer, and the second sub-layer149may include at least a portion of the blocking dielectric layer. One of the first and second sub-layers147and149may include the charge storage layer. In other words, a portion of the gate dielectric layer150aincluding the tunnel dielectric layer, the charge storage layer and the blocking dielectric layer may be extended vertically, and another portion of the gate dielectric layer150amay be extended horizontally.

The vertical active pattern130amay include first and second semiconductor patterns123and124. The first semiconductor pattern123may be disposed between the second semiconductor pattern124and the first sub-layer147. The first semiconductor pattern123may contact the first sub-layer147. According to an embodiment of the inventive concept, the first semiconductor pattern123may have a macaroni shape or a pipe shape where an upper end and a lower end are opened. The first semiconductor pattern123may not contact the inner surface of the recess region120by the first sub-layer147. The second semiconductor pattern124may contact the first semiconductor pattern123and the inner surface of the recess region120. The second semiconductor pattern124may have a macaroni shape or a pipe shape where a lower end is closed. A filling dielectric pattern132may fill the inside of the second semiconductor pattern124. The first and second semiconductor patterns123and124may have an undoped state or be doped with a dopant (i.e., the first conductive dopant) having the same type as that of the well region102.

According to an embodiment of the inventive concept, as illustrated inFIG. 3B, the first sub-layer147of the gate dielectric layer150amay include a tunnel dielectric layer141, a charge storage layer142and a barrier dielectric layer144. In this case, the second sub-layer149may include a high-k dielectric material (for example, metal-oxide such as aluminum oxide or hafnium oxide) having a dielectric constant higher than that of the tunnel dielectric layer141. The barrier dielectric layer144may include a dielectric material having a greater band gap than that of the high-k dielectric material. For example, the barrier dielectric layer144may include oxide. The second sub-layer149and the barrier dielectric layer144, disposed between the charge storage layer142and each of the gate patterns155L,155a1,155aand155U, may included in the blocking dielectric layer. In other words, the first sub-layer147may include the tunnel dielectric layer141, the charge storage layer142and a portion (i.e., the barrier dielectric layer144) of the blocking dielectric layer, and the second sub-layer149may include another portion (i.e., the high-k dielectric layer) of the blocking dielectric layer. However, an embodiment of the inventive concept is not limited thereto. The first and second sub-layers of the gate dielectric layer may be combined differently.

FIG. 3Cis a magnified view of a portion B ofFIG. 3Afor describing even other modification example of a 3D semiconductor memory device according to an embodiment of the inventive concept. Referring toFIG. 3C, a first sub-layer147aof a gate dielectric layer150baccording to the modification example may include a tunnel dielectric layer141and a charge storage layer142, and a second sub-layer149aof the gate dielectric layer150bmay include a barrier dielectric layer144and a high-k dielectric layer146. The high-k dielectric layer146may be formed of the same material as the high-k dielectric material that has been described above with reference toFIG. 3B. According to the modification example, the second sub-layer149bmay correspond to a blocking dielectric layer. According to the modification example, the first sub-layer147amay include the tunnel dielectric layer141and the charge storage layer142, and the second sub-layer149amay include the blocking dielectric layer.

FIG. 3Dis a magnified view of a portion B ofFIG. 3Afor describing yet other modification example of a 3D semiconductor memory device according to an embodiment of the inventive concept. Referring toFIG. 3D, a first sub-layer147bof a gate dielectric layer150caccording to the modification example may include the tunnel dielectric layer, and a second sub-layer149bof the gate dielectric layer150cmay include the charge storage layer142and the blocking dielectric layer143. According to the modification example, the tunnel dielectric layer in the gate dielectric layer150cmay be extended vertically and be disposed between the vertical active pattern130aand the insulation pattern110a, and the charge storage layer142and the blocking dielectric layer143in the gate dielectric layer150cmay be extended horizontally and cover the upper surface and lower surface of each of the gate patterns155L,155a1,155aand155U.

The first and second sub-layers according to an embodiment of the inventive concept are not limited to the modification examples that have been described above with reference toFIGS. 3B,3C and3D. The first and second sub-layers may be combined differently.

FIG. 4Ais a cross-sectional view taken along line I-I′ ofFIG. 1Afor describing further modification example of a 3D semiconductor memory device according to an embodiment of the inventive concept.FIG. 4Bis a magnified view of a portion C ofFIG. 4A. Referring toFIGS. 4A and 4B, the entirety of a gate dielectric layer150dbetween the vertical active pattern130aand each of the gate patterns155L,155a1,155aand155U may be substantially extended vertically. That is, the tunnel dielectric layer141, charge storage layer142and blocking dielectric layer143of the gate dielectric layer150dmay be substantially extended vertically. An extended portion of the gate dielectric layer150dmay be disposed between the vertical active pattern130aand the insulation pattern110a. The stack-structure ofFIGS. 1A and 1Bmay have a line shape that is extended in the first direction. Unlike this, the stack-structure may include gate patterns having a flat plate shape. This will be described below with reference to the accompanying drawings.

FIG. 5Ais a plan view illustrating still further modification example of a 3D semiconductor memory device according to an embodiment of the inventive concept.FIG. 5Bis a cross-sectional view taken along line II-II′ ofFIG. 5A. Referring toFIGS. 5A and 5B, a stack-structure according to the modification example may include gate patterns220L,220a,220and220U and insulation patterns210and210U that are stacked alternately and repeatedly. A lowermost gate pattern220L in the stack-structure may be a ground selection gate, and an uppermost gate pattern220U in the stack-structure may be a string selection gate. The gate pattern220ajust on the lowermost gate pattern220L may be used as a cell gate, a dummy cell gate or a second ground selection gate. The gate patterns220between the gate pattern220ajust on the lowermost gate pattern220L and the upper gate pattern220U may be used as cell gates.

The gate patterns220L,220aand220under a string selection gate, as illustrated inFIGS. 5A and 5B, may have a flat plate shape. The uppermost gate pattern220U corresponding to the string selection gate may have a line shape that is extended in the first direction. The uppermost gate pattern220U may be provided in plurality, and the uppermost gate patterns220U may be extended side by side in the first direction. The bit line170may be extended in the second direction and cross over the uppermost gate pattern220U. Like the uppermost gate pattern220U, an uppermost insulation pattern210U on the uppermost gate pattern220U may also be extended in the first direction.

The vertical active pattern130amay pass through the stack-structure and be extended into the recess region120under it. The lowermost gate pattern220L corresponding to the ground selection gate may be disposed on the common source region105in the substrate100. The entire lower surface of the lowermost gate pattern220L may substantially overlap with the common source region105. According to the modification example, the gate dielectric layer150dmay be disposed between the vertical active pattern130aand the inner sidewall of an opening115passing through the stack-structure. The gate dielectric layer150dmay be substantially extended vertically. The opening115and the recess region120may be self-aligned. The gate dielectric layer150dmay be extended into the recess region120. According to an embodiment of the inventive concept, the lower end of the gate dielectric layer150din the recess region120may be disposed on a level higher than the lower surface of the recess region120.

A lower interlayer dielectric163may be disposed between the uppermost gate patterns220U. An upper surface of the lower interlayer dielectric163may be coplanar with an upper surface of the uppermost insulation pattern210U. An upper interlayer dielectric165may be disposed on the lower interlayer dielectric163and the uppermost gate patterns220U. The insulation patterns210and210U may include oxide, nitride and/or oxynitride. The gate patterns220L,220a,220and220U may include at least one of a doped semiconductor (for example, doped silicon), a metal (for example, tungsten and others) or a conductive metal nitride (for example, a titanium nitride, a tantalum nitride and others).

The elements of the above-described modification examples may be combined or replaced. For example, the capping semiconductor pattern175ofFIG. 2Amay be disposed on the vertical active pattern130or130athat has been disclosed inFIG. 1B,3A,4A or5B.

FIGS. 6A to 6Hare cross-sectional views taken along line I-I′ ofFIG. 1Afor describing a method of fabricating 3D semiconductor memory device according to an embodiment of the inventive concept. Referring toFIG. 6A, a well region102may be formed by providing a first conductive dopant into the substrate100. A common source region105may be formed by providing a second conductive dopant into the upper portion of the well region102. Insulation layers110and sacrificial layers112may be alternately and repeatedly stacked on the common source region105. For example, the insulation layers110may be formed as oxide layers. The sacrificial layers112may be formed of materials having an etch selectivity with respect to the insulation layers112. For example, the sacrificial layers112may be formed as nitride layers.

Referring toFIG. 6B, an opening115and a recess region120may be formed by sequentially patterning the insulation layers110, sacrificial layers112and the substrate100. The opening115may pass through the insulation layers110and sacrificial layers112, and the recess region120may be formed in the common source region102under the opening115(i.e., in a portion of the substrate100). The recess region120is self-aligned in the opening115by sequentially patterning the insulation layers110and sacrificial layers112and the substrate100. The recess region120may pass through the common source region105, and the bottom surface of the recess region120may be disposed on a level lower than the lower surface of the common source region105. Therefore, the well region102may be exposed to the bottom surface of the recess region120, and the common source region105may be exposed to the inner sidewall of the recess region120. A high concentration region122may be formed by providing the first conductive dopant into the well region102through the bottom surface of the recess region120. The high concentration region122of the first conductive dopant may be higher than another portion of the well region102. That is, due to the high concentration region122, the well region102may partially have a high dopant concentration.

Referring toFIG. 6C, a semiconductor layer may be conformally formed on the substrate100having the opening115and the recess region120. Therefore, the semiconductor layer may be formed to have a substantially uniform thickness on the inner surface of the recess region120and an inner sidewall of the opening115. The semiconductor layer may contact the inner surface (i.e., an inner sidewall and a bottom surface) of the recess region120. The semiconductor layer may be formed in a chemical vapor deposition process and/or an atomic layer deposition process. A filling dielectric layer may be formed on the semiconductor layer to fill the opening115. For example, the filling dielectric layer may be formed as an oxide layer. By planarizing the filling dielectric layer and the semiconductor layer until the uppermost insulation layer110is exposed, a vertical active pattern130and a filling dielectric pattern132may be formed in the opening115and the recess region120.

Referring toFIG. 6D, a trench135may be formed by sequentially patterning the insulation layers110and sacrificial layers112, such that insulation patterns110aand the sacrificial patterns112abeing alternately and repeatedly stacked may be formed at a side of the trench135. The insulation patterns110aand sacrificial patterns112amay include the opening115. That is, the vertical active patterns130may sequentially pass through the insulation patterns110aand the sacrificial patterns112abeing alternately and repeatedly stacked on the substrate100. Sidewalls of the sacrificial patterns112aand the insulation patterns110aare exposed to the trench135.

Referring toFIG. 6E, empty regions140may be formed by removing the sacrificial patterns112aexposed to the trench135. Each of the empty regions140corresponds to a region from which the each sacrificial pattern112ais removed. The empty regions140may expose some portions of the sidewall of the vertical active pattern130, respectively.

Referring toFIG. 6F, a gate dielectric layer150may be conformally formed on the substrate100having the empty regions140. Therefore, the gate dielectric layer150may be conformally formed on the inner surfaces of the empty regions140. The gate dielectric layer150, as described above with reference toFIGS. 1B and 1C, may include the tunnel dielectric layer, the charge storage layer and the blocking dielectric layer.

A gate conductive layer155filling the empty regions140may be formed on the substrate100having the gate dielectric layer150. The gate conductive layer155may also be formed in the trench135. Herein, the gate conductive layer155may partially fill the trench135. Therefore, a space surrounded by the gate conductive layer155may be formed in the trench135. A bottom surface of the space may be lower than an inner-upper surface of the lowermost empty region140.

Referring toFIG. 6G, the gate patterns155L,155a1,155aand155U respectively filling the empty regions140may be formed by etching the gate conductive layer155. The gate patterns155L,155a1,155aand155U are separated by the etching process of the gate conductive layer155. According to an embodiment of the inventive concept, the etching process of the gate conductive layer155may be an isotropic etching process. The insulation patterns110aand the gate patterns155L,155a1,155aand155U, being alternately and repeatedly stacked on the substrate100, may be included in a stack-structure. Subsequently, a device isolation insulation layer160may be formed to fill the trench135.

Referring toFIG. 6H, the device isolation insulation layer160and the gate dielectric layer150may be planarized until the uppermost insulation pattern among the insulation patterns110ais exposed. Therefore, a device isolation pattern160amay be formed in the trench135. Subsequently, by forming the interlayer dielectric165, contact plug167and bit line170of theFIG. 1Bon the substrate100, the 3D semiconductor memory device that has disclosed inFIGS. 1A,1B and1C may be implemented. According to the above-described 3D semiconductor memory device, the opening115and the recess region120can be formed in self-alignment by sequentially patterning the insulation layers110, the sacrificial layers112and the substrate100(i.e. the common source region105). Therefore, the 3D semiconductor memory device can be implemented which has excellent reliability and is optimized for high integration. Next, a method of fabricating the 3D semiconductor memory device that has been disclosed inFIG. 2Awill be described below with reference to the accompanying drawings. The method may include the methods that have been described above with reference toFIGS. 6A and 6B.

FIGS. 7A to 7Dare cross-sectional views taken along line I-I′ ofFIG. 1Afor describing a modification example of a method of fabricating 3D semiconductor memory device according to an embodiment of the inventive concept.

Referring toFIGS. 6B and 7A, a protection dielectric layer173may be conformally formed on the substrate100having the opening115and the recess region120, and the protection dielectric layer173may be etched by a blanket anisotropic etching process until the bottom surface of the recess region120is exposed. As illustrated inFIG. 7A, therefore, the protection dielectric layer173may be formed on the sidewalls of the recess region120and the opening115. The protection dielectric layer173may include a dielectric material having an etch selectivity with respect to the sacrificial layer112. For example, the protection dielectric layer173may be formed of oxide.

Subsequently, a semiconductor layer may be formed, a filling dielectric layer may be formed on the semiconductor layer, and the filling dielectric layer and the semiconductor layer may be planarized. Therefore, the vertical active pattern130and the filling dielectric pattern132may be formed in the opening115and the recess region120. The vertical active pattern130may contact the bottom surface of the recess region120. The protection dielectric layer173may be disposed between the vertical active pattern130and the inner sidewalls of the opening115and the recess region120.

Referring toFIG. 7B, the upper ends of the vertical active pattern130, filling dielectric pattern132and protection dielectric layer175may be recessed lower than the upper surface of the uppermost insulation layer110. Subsequently, a capping semiconductor layer filling the opening110may be formed on the substrate100, and a capping semiconductor pattern175may be formed by planarizing the capping semiconductor layer until the uppermost insulation layer110is exposed. The capping semiconductor pattern175may cover the recessed upper ends of the vertical active pattern130, filling dielectric pattern132and protection dielectric layer175.

Subsequently, the trench135may be formed by sequentially patterning the insulation layers110and the sacrificial layers112. In this case, as described above, the insulation patterns110and the sacrificial patterns112athat are alternately and repeatedly stacked may be formed at a side of the trench135.

Referring toFIG. 7C, the sacrificial patterns112aexposed to the trench135may be removed. Therefore, the empty regions140may be formed which respectively exposes some portions of the protection dielectric layer173disposed on the sacrificial patterns112aand the vertical active patterns130. As described above, the protection dielectric layer173has an etch selectivity with respect to the sacrificial patterns112a, and thus it can protect the vertical active pattern130from a process of removing the sacrificial patterns112a. The protection dielectric layer173may be used as an etch stop layer in the process of removing the sacrificial patterns112a. Subsequently, the exposed portions of the protection dielectric layer173may be removed. Therefore, the empty regions140may expose some portions of the side wall of the vertical active pattern130, respectively. When removing the exposed portions of the protection dielectric layer173, the protection dielectric patterns173amay be formed between the vertical active pattern130and the insulation patterns110aand between the vertical active pattern130and the inner sidewall of the recess region120. The protection dielectric patterns173acorrespond to remaining portions of protection dielectric layer173.

Referring toFIG. 7D, the gate dielectric layer150may be conformally formed on the substrate100having the empty regions140, and the gate patterns155L,155a1,155aand155U respectively filling the empty regions140may be formed. Afterwards, the device isolation pattern160afilling the trench135may be formed. Subsequently, by forming the interlayer dielectric165, contact plug167and bit line170ofFIG. 2A, the 3D semiconductor memory device ofFIG. 2Acan be implemented.

The features of a method, that fabricates the 3D semiconductor memory device that has been disclosed inFIG. 2B, may have a process of forming the lower surface of the recess region120higher than the lower surface of the common source region105and a process of forming the counter-doped region122aby counter-doping the common source region105under the bottom surface of the recess region120with the first conductive dopant. Other processes may be the same as the processes that have been described above with reference toFIGS. 7A to 7D.

Next, a method of fabricating the 3D semiconductor memory device that has been disclosed inFIG. 3Awill be described below with reference to the accompanying drawings. The method may include the methods that have been described above with reference toFIGS. 6A and 6B.

FIGS. 8A to 8Fare cross-sectional views taken along line I-I′ ofFIG. 1Afor describing other modification example of a method of fabricating 3D semiconductor memory device according to an embodiment of the inventive concept.

Referring toFIGS. 6B and 8A, a first sub-layer147may be conformally formed on the substrate100having the opening115and the recess region120. The first sub-layer147may be conformally formed on the inner sidewall of the opening115and the inner surface of the recess region120. A first semiconductor layer121may be conformally formed on the substrate100having the first sub-layer147.

Referring toFIG. 8B, portions of the first sub-layer147and the first semiconductor layer121disposed on the bottom surface of the recess region120may be removed. At this point, portions of the first sub-layer147and the first semiconductor layer121disposed outside opening115may also be removed. Therefore, the first sub-layer147and the first semiconductor pattern123that are sequentially stacked on the sidewalls of the recess region120and opening115may be formed, the first semiconductor pattern123correspond to a portion of the first semiconductor layer121. According to an embodiment of the inventive concept, by blanket-anisotropic-etching the first semiconductor layer121and the first sub-layer147until the bottom surface of the recess region120is exposed, the first semiconductor pattern123may be formed. The first semiconductor pattern123may not contact the inner surface of the recess region120by the first sub-layer147.

Referring toFIG. 8C, subsequently, by isotropic-etching the first sub-layer147, at least one portion of the inner sidewall of the recess region120may be exposed. At this point, a portion of the first semiconductor pattern123in the recess region120may also be etched.

Referring toFIG. 8D, subsequently, a second semiconductor layer may be conformally formed on the substrate100, a filling dielectric layer filling the opening115may be formed on the second semiconductor layer. The second semiconductor layer may contact the first semiconductor pattern123, and also the second semiconductor layer may contact the bottom surface and exposed inner sidewall of the recess region120. By planarizing the second semiconductor layer and the filling dielectric layer, a second semiconductor pattern124and a filling dielectric pattern132may be formed in the opening115and the recess region120. The second semiconductor pattern124may contact the bottom surface and inner sidewall of the recess region120and the first semiconductor pattern123. The first and second semiconductor patterns123and124may configure a vertical active pattern130a.

Referring toFIG. 8E, subsequently, the trench135, the insulation patterns110aand the sacrificial patterns112may be formed by sequentially patterning the insulation layers110and the sacrificial layers112. The empty regions140may be formed by removing the sacrificial patterns112. At this point, the empty regions140may expose some portions of the first sub-layer147, respectively.

Referring toFIG. 8F, a second sub-layer149may be conformally formed on the substrate100having the empty regions140. The second sub-layer149may be conformally formed on the inner surfaces of the empty regions140. The second sub-layer149may contact the first sub-layer147exposed to the empty regions140. The first and second sub-layers147and149may be included in the gate dielectric layer150a. The first sub-layer147may include at least a portion of the tunnel dielectric layer, and the second sub-layer149may include at least a portion of the blocking dielectric layer. Herein, one of the first and second sub-layers147and149may include the charge storage layer. According to an embodiment of the inventive concept, the first and second sub-layers147and149may be the same as the layers that have been described above with reference toFIG. 3B. Unlike this, the first and second sub-layers147and149may be replaced with the first and second sub-layers147aand149aof theFIG. 3C, respectively. Unlike this, the first and second sub-layers147and149may be replaced with the first and second sub-layers149band149cof theFIG. 3C, respectively. Subsequently, the gate patterns155L,155a1,155aand155U respectively filling the empty regions140may be formed, and the device isolation pattern160afilling the trench135may be formed. Subsequently, the interlayer dielectric165, the contact plug167and the bit line170that have been disclosed inFIG. 3Amay be formed. Next, a method of fabricating the 3D semiconductor memory device that has been disclosed inFIGS. 4A and 4Bwill be described below with reference to the accompanying drawings. The method may include the methods that have been described above with reference toFIGS. 6A and 6B.

FIGS. 9A to 9Dare cross-sectional views taken along line I-I′ ofFIG. 1Afor describing still other modification example of a method of fabricating 3D semiconductor memory device according to an embodiment of the inventive concept. Referring toFIGS. 6B to 9A, a gate dielectric layer150dmay be conformally formed on the substrate100having the opening115and the recess region120. A first semiconductor layer may be conformally formed on the gate dielectric layer150d. Subsequently, the first semiconductor layer and the gate dielectric layer150dmay be etched by a blanket-anisotropic-etching process until the bottom of the recess region120is exposed, such that a first semiconductor pattern123may be formed in the opening115and the recess region120. At this point, the gate dielectric layer150dmay also be restrictively disposed in the opening115and the recess region120. The first semiconductor pattern123may not contact the side wall of the opening115and the inner surface of the recess region120by the gate dielectric layer150d.

Referring toFIG. 9B, subsequently, a second semiconductor may be conformally formed over the substrate100, and a filling dielectric layer may be formed on the second semiconductor layer. By planarizing the filling dielectric layer and the second semiconductor layer, a second semiconductor pattern124and a filling dielectric pattern132may be formed in the opening115and the recess region120. The first and second semiconductor patterns123and124may configure a vertical active pattern130a. Subsequently, a trench135, insulation patterns110aand sacrificial patterns112amay be formed by sequentially patterning the insulation layers110and the sacrificial layers112. According to the modification example, a portion of the lowermost insulation layer among the insulation layers110may remain under the trench135.

Referring toFIG. 9C, empty regions140may be formed by removing the sacrificial patterns112a. The empty regions140may expose the gate dielectric layer150d. Particularly, the blocking dielectric layer143(seeFIG. 4B) in the gate dielectric layer150dmay be exposed. Subsequently, a gate conductive layer155filling the empty regions140may be formed on the substrate100.

Referring toFIG. 9D, by removing the gate conductive layer outside the empty regions140, gate patterns155L,155a1,155aand155U filling the empty regions140may be formed. Subsequently, the device isolation pattern160afilling the trench135may be formed, and the interlayer dielectric165, contact plug167and bit line170ofFIG. 4Amay be formed. Thus, the 3D semiconductor memory device ofFIGS. 4A and 4Bcan be implemented. Next, a method of fabricating the 3D semiconductor memory device ofFIGS. 5A and 5Bwill be described below with reference to the accompanying drawings.

FIGS. 10A to 10Care cross-sectional views taken along line I-I′ ofFIG. 1Afor describing even other modification example of a method of fabricating 3D semiconductor memory device according to an embodiment of the inventive concept. Referring toFIG. 10A, insulation layers210and gate layers220may be alternately and repeatedly stacked on the common source region105in the substrate100. The insulation layers210and gate layers220L,220aand220may have a flat plate shape. Referring toFIG. 10B, an uppermost gate pattern220U and an uppermost insulation pattern210U may be formed by patterning an uppermost insulation layer and an uppermost gate layer. The uppermost gate pattern220U and the uppermost insulation pattern210U may have a line shape that is extended in one direction as illustrated inFIG. 5A. A lower interlayer dielectric163may be formed on the substrate100, and the lower interlayer dielectric163may be planarized. An opening115and a recess region120may be formed by sequentially patterning the uppermost insulation pattern210U, the uppermost gate pattern220U, the insulation layers210, the gate layers220L,220aand220and the common source region105. The recess region120may be formed in self-alignment in the opening115. By providing a first conductive dopant through the bottom surface of the recess region120, a high concentration region122may be formed. Subsequently, a gate dielectric layer150dmay be conformally formed over the substrate100, and a first semiconductor layer may be conformally formed on the gate dielectric layer150d. By blanket-isotropic-etching the first semiconductor layer and the gate dielectric layer150duntil the bottom surface of the recess region120is exposed, a first semiconductor pattern123may be formed in the opening115and the recess region120.

Referring toFIG. 10C, a second semiconductor layer may be conformally formed over the substrate100, and a filling dielectric layer may be formed on the second semiconductor. By planarizing the filling dielectric layer and the second semiconductor layer, a second semiconductor pattern124and a filling dielectric pattern132may be formed in the opening115and the recess region120. The first and second semiconductor patterns123and124may configure a vertical active pattern130a. Subsequently, the tipper dielectric layer165, contact plug167and bit line170ofFIG. 5Bmay be formed. Thus, the 3D semiconductor memory device ofFIGS. 5A and 5Bcan be implemented. According to the above-described method, the uppermost gate pattern220U may be formed, and thereafter the vertical active pattern130amay be formed. Unlike this, after the opening115, the recess region120and the vertical active pattern130amay be formed, and then the uppermost gate pattern220U may be formed.

When forming the uppermost gate pattern220U, a stack-structure having a line shape may be formed by sequentially patterning the gate layers220,220aand220L and insulation layers110under the uppermost gate pattern220U. In this case, the 3D semiconductor memory device ofFIGS. 4A and 4Bcan be implemented. In other words, the 3D semiconductor memory device ofFIGS. 4A and 4Bmay be implemented in the method that has been described above with reference toFIGS. 9A to 9Dor a modified method of a portion of the fabricating method ofFIGS. 10A to 10C.

FIG. 11is a cross-sectional view illustrating a 3D semiconductor memory device according to another embodiment of the inventive concept. Referring toFIG. 11, a well region102doped with a first conductive dopant may be disposed in a substrate100. A stack-structure may be disposed on the well region102. The stack-structure may include insulation patterns110aand gate patterns155L,155a1,155aand155U that are alternately and repeatedly stacked on the well region102. A plurality of the stack-structures may be disposed on the well region102. The stack-structures may be spaced apart from each other. As illustrated inFIG. 1a, the stack-structures may be extended in parallel.

A vertical active pattern280may pass through the stack-structure. Also, the vertical active pattern280may be extended into a recess region120that is formed in the substrate100under the vertical active pattern280. The vertical active pattern280may include a lower active pattern250and an upper active pattern270that are sequentially stacked. The lower active pattern250may fill the recess region120. The upper active pattern270may contact the inner surface (i.e., inner sidewall and bottom surface) of the recess region120. The lower active pattern250is disposed in the recess region120and contacts the well region102. The upper surface of the lower active pattern250may be disposed on a level higher than that of the upper surface of the substrate100. According to an embodiment of the inventive concept, as illustrated inFIG. 11, the upper surface of the lower active pattern250may be higher than the lower surface of the lowermost gate pattern155L and lower than the upper surface of the lowermost gate pattern155L. However, the inventive concept is not limited thereto.

The upper active pattern270contacts the upper surface of the lower active pattern250. According to an embodiment of the inventive concept, the lower active pattern250may have a pillar shape, and the upper active pattern270may have a pipe shape or a macaroni shape. In this case, the inside of the upper active pattern270may be filled with a filling dielectric pattern132. The lower and upper active patterns250and270may include a semiconductor material. For example, the lower and upper active patterns250and270may include the same semiconductor material as that of the substrate100. As an example, when the substrate100is a silicon substrate, the lower and upper active patterns250and270may include silicon. According to an embodiment of the inventive concept, the lower active pattern250may have a single crystalline state. The upper active pattern270may have a poly-crystalline state. The lower active pattern250may be doped with a dopant having the same type as that of the well region102. The upper active pattern270may be doped with a dopant having the same type as that of the well region102, or may have an undoped state.

A high concentration region122may be disposed under the bottom surface of the recess region120. The high concentration region122may correspond to a portion of the well region102, and it may have a higher dopant concentration than another portion of the well region102. A gate dielectric layer150may be disposed between a sidewall of the vertical active pattern280and each of the gate patterns155L,155a1,155aand155U. As described above in first embodiment of the inventive concept, the gate dielectric layer150may be extended horizontally and cover the upper surface and lower surface of each of the gate patterns155L,155a1,155aand155U.

According to an embodiment of the inventive concept, a common source regions105amay be disposed in the substrate100of the both sides of the stack-structure, respectively. The common source region105amay be laterally separated from the lower active pattern250. The common source region105ais doped with a second conductive dopant. A device isolation pattern160amay be disposed between the stack-structures. The common source region105amay be disposed under the device isolation pattern160a. In operating of the 3D semiconductor memory device, a horizontal channel may be generated in the well region102under the lowermost gate pattern155L. The common source region105amay be electrically connected to vertical channels that are formed in the vertical active pattern280by the horizontal channel in the well region102.

A contact plug167passing through the interlayer dielectric165may be connected to the upper end of the upper active pattern270. A drain doped with the second conductive dopant may be disposed in the upper portion of the upper active pattern270. The lower surface of the drain may be disposed on a level adjacent to the upper surface of the uppermost gate pattern155U in the stack-structure.

According to the above-described 3D semiconductor memory device, the lower active pattern250included in the vertical active pattern280fills the recess region120to contact the well region102. Therefore, reliability for the operations of a vertical cell string can be improved. Particularly, reliability for the erasing operation of cell transistors can be enhanced. Also, the vertical active pattern280may be divided into the lower active pattern250and the upper active pattern270. Accordingly, an independent and additional process may be performed in the lower active pattern250. For example, a dopant concentration may be adjusted in the lower active pattern250. Thus, it is very easy to control the characteristic of the 3D semiconductor memory device. As a result, the 3D semiconductor memory device can be implemented which has excellent reliability and is optimized for high integration.

Next, the modification examples of the 3D semiconductor memory device will be described below with reference to the accompanying drawings.

FIG. 12Ais a cross-sectional view illustrating a modification example of a 3D semiconductor memory device according to another embodiment of the inventive concept. Referring toFIG. 12A, a common source region105may be extended to the substrate100under the stack-structures. For example, the entire lower surface of the lowermost gate pattern155L may substantially overlap with the common source region105. In this case, the bottom of the recess region120may be disposed on a level lower than the lower surface of the common source region105. The common source region105may contact a sidewall of the lower active pattern250.

FIG. 12Bis a cross-sectional view illustrating other modification example of a 3D semiconductor memory device according to another embodiment of the inventive concept. Referring toFIG. 12B, a vertical active pattern280amay include a lower active pattern250and an upper active pattern270athat are sequentially stacked. A gate dielectric layer150amay be disposed between the upper active pattern270aand each of the gate patterns155a1,155aand155U disposed next to the upper active pattern270a. The gate dielectric layer150amay include a first and a second sub-layers147and149. As described above in first embodiment of the inventive concept, the first sub-layer147may be extended vertically and be disposed between the upper active pattern270aand the insulation pattern110a. The second sub-layer149may be extended horizontally and cover the lower surface and upper surface of each of the gate patterns155a1,155aand155U.

When the upper surface of the lower active pattern250is disposed on a level between the levels of the lower and upper surfaces of the lowermost gate pattern155L, the first sub-layer147may not exist between the lower active pattern250and the lowermost gate pattern155L. The upper active pattern270amay include a first semiconductor pattern265and a second semiconductor pattern267. The first semiconductor pattern265may be disposed between the first sub-layer147and the second semiconductor pattern267. The first semiconductor pattern265may be separated from the upper surface of the lower active pattern250by a portion of the first sub-layer147. The second semiconductor pattern267contacts the first semiconductor pattern265. Also, the second semiconductor pattern267contacts the upper surface of the lower active pattern250.

The upper surface of the lower active pattern250may be divided into a center portion252ccontacting the second semiconductor pattern267and an edge portion252econtacting the first sub-layer147. Herein, the center portion252cof the upper surface of the lower active pattern250may be disposed on a level lower than that of the edge portion252e. The upper active pattern270aincluding the first and second semiconductor patterns265and267may have a pipe shape or a macaroni shape. In this case, the inside of the upper active pattern270amay be filled with a filling dielectric pattern132. The first and second semiconductor patterns265and267may have a poly-crystalline state. In the modification example, the first and second sub-layers147and149may be replaced by the first and second sub-layers147aand149aofFIG. 3Cor the first and second sub-layers147band149bofFIG. 3C. Unlike this, as described above in first embodiment of the inventive concept, the first and second sub-layers147and149may be formed by another combination of a tunnel dielectric layer, a charge storage layer and a blocking dielectric layer.

FIG. 12Cis a cross-sectional view illustrating still other modification example of a 3D semiconductor memory device according to another embodiment of the inventive concept. Referring toFIG. 12C, at least edge portion of the upper surface of the lower active pattern250may be disposed on a level higher than the upper surface of the lowermost gate pattern155L. In this case, an oxide layer255may be disposed between the sidewall of the lower active pattern250and the lowermost gate pattern155L. The oxide layer255may include oxide formed by oxidizing the sidewall of the lower active pattern250. Therefore, the width of a first portion of the lower active pattern250next to the oxide layer255may be less than that of a second portion of the lower active pattern250disposed in the recess region120.

When the gate dielectric layer150aincludes the first and second sub-layers147and149, the oxide layer255and a portion of the second sub-layer149may be disposed between the sidewall of the lower active pattern250and the lowermost gate pattern155L. In other words, the first sub-layer147may not exist between the sidewall of the lower active pattern250and the lowermost gate pattern155L. According to an embodiment of the inventive concept, when the first sub-layer147includes a charge storage layer, the charge storage layer may not exist between the sidewall of the lower active pattern250and the lowermost gate pattern155L. Therefore, the reliability of a ground selection transistor including the lowermost gate pattern155L can be improved. Moreover, the lower active pattern250may have a single crystalline state. Accordingly, the reliability of the ground selection transistor can be more enhanced.

FIG. 12Dis a cross-sectional view illustrating even other modification example of a 3D semiconductor memory device according to another embodiment of the inventive concept. Referring toFIG. 12D, at least the edge portion of the upper surface of a lower active pattern250may be disposed on a level higher than the upper surface of a gate pattern155a1that is stacked secondarily from the substrate100and lower than the lower surface of a gate pattern that is stacked thirdly from the substrate100. The secondarily-stacked gate pattern155a1and the thirdly-stacked gate pattern are disposed over the lowermost gate pattern155L. In this case, an oxide layer255may also be disposed between the secondarily-stacked gate pattern155a1and the side wall of the lower active pattern250.

According to the modification example, a transistor including the secondarily-stacked gate pattern155a1may be used as a dummy transistor or a second ground selection transistor. In this case, a cell gate (for example, the thirdly-stacked gate pattern155a) adjacent to the secondarily-stacked gate pattern155a1may correspond to a dummy cell gate. As described above, a dummy cell transistor including the dummy cell gate has the same type as that of a cell transistor storing data, but it may not serve as a cell transistor. As an example, in operating of the cell string, the dummy cell transistor may perform only a turn-on/off function. However, the inventive concept is not limited thereto. The thirdly-stacked gate pattern may be used as a cell transistor.

FIG. 12Eis a cross-sectional view illustrating yet other modification example of a 3D semiconductor memory device according to another embodiment of the inventive concept. Referring toFIG. 12E, the entirety of a gate dielectric layer150dbetween the sidewall of the upper active pattern270aand each of the gate patterns155a1,155aand155U may be substantially extended vertically and be disposed between an upper active pattern270aand an insulation pattern110a. In this case, only an oxide layer255may be disposed between the sidewall of the lower active pattern250and the lowermost gate pattern155L.

FIG. 12Fis a cross-sectional view illustrating further modification example of a 3D semiconductor memory device according to another embodiment of the inventive concept. Referring toFIG. 12F, protection dielectric patterns173amay be disposed between the upper active pattern270aand the insulation patterns110a. In a fabricating process, the protection dielectric pattern173amay include a dielectric material for protecting the upper active pattern270. According to an embodiment of the inventive concept, the protection dielectric pattern173amay not exist between the lower active pattern250and the inner sidewall of the recess region120.

The elements of the above-described modification examples may be combined without clash or replaced. For example, the common source region105aofFIG. 11may be replaced with the common source region105ofFIGS. 12B to 12F. For example, in the 3D semiconductor memory devices ofFIGS. 11 and 12Ato12F, the heights of the upper surfaces of the lower active patterns250may be replaced.

FIGS. 13A to 13Eare cross-sectional views for describing a method of fabricating 3D semiconductor memory device according to another embodiment of the inventive concept. Referring toFIG. 13A, a well region102may be formed by providing a first conductive dopant to the substrate100. Insulation layers110and sacrificial layers112that are alternately and repeatedly stacked may be formed on the well region102. A recess region120and an opening115that are sequentially stacked may be formed by sequentially patterning the insulation layers110, the sacrificial layers112and the substrate100. The opening115may pass through the insulation layers110and the sacrificial layers112, and the recess region120may be self-aligned in the opening115and be formed in the substrate100. The recess region120may expose the well region102.

Referring toFIG. 13B, a high concentration region122may be formed by providing the first conductive dopant through the bottom of the recess region120.

A lower active pattern250filling the recess region120may be formed. The upper surface of the lower active pattern250may be higher than the upper surface of the substrate100. Therefore, a portion of the lower active pattern250may fill the lower portion of the opening115. The lower active pattern250contacts the well region102. The lower active pattern250may be formed in a selective epitaxial growth process that uses the substrate100exposed by the recess region120as a seed layer. Therefore, the lower active pattern250may be formed in a single crystalline state. The lower active pattern250may be formed in a pillar shape. The lower active pattern250may be doped with the first conductive dopant. The lower active pattern250may be doped by an in-situ process when the selective epitaxial growth process is performed. Unlike this, the lower active layer250may be doped by an ion-implanting process.

Referring toFIG. 13C, a semiconductor layer may be conformally formed on the substrate100having the lower active pattern250, and a filling dielectric layer filling the opening115may be formed on the semiconductor layer. The semiconductor layer may be conformally formed on the inner sidewall of the opening115and the upper surface of the lower active pattern250. The semiconductor layer may contact the lower active pattern250. The semiconductor layer may be formed in a chemical vapor deposition process and/or an atomic layer deposition process. Therefore, the semiconductor layer may be formed in a poly-crystalline state.

By planarizing the filling dielectric layer and the semiconductor layer, an upper active pattern270and a filling dielectric pattern132may be formed in the opening115. The lower and upper active patterns250and270may configure a vertical active pattern280. Subsequently, a trench135, insulation patterns110aand sacrificial patterns110amay be formed by sequentially patterning the insulation layers110and the sacrificial layers112. The vertical active pattern280passes through the insulation patterns110aand the sacrificial patterns112a. Subsequently, by providing a second conductive dopant into the well region102under the trench135, a common source region105amay be formed.

Referring toFIG. 13D, by removing sacrificial patterns112aexposed to the trench135, empty regions140may be formed. According to an embodiment of the inventive concept, at least a portion of an lowermost empty regions140may expose a portion of the sidewall of the lower active pattern250. A gate dielectric layer150may be conformally formed on the substrate100having the empty regions140, and a gate conductive layer155filling the empty regions140may be formed.

Referring toFIG. 13E, gate patterns155L,155a1,155aand155U, that are respectively disposed in the empty regions140, may be formed by etching the gate conductive layer155. Subsequently, a device isolation pattern160afilling the trench135may be formed. The 3D semiconductor memory device ofFIG. 11may be implemented by forming the interlayer dielectric165, contact plug167and bit line170ofFIG. 11.

According to the above-described 3D semiconductor memory device, the opening115and the recess region120are formed in self-alignment, and the lower active pattern250fills the recess region120to contact the well region102. After, the lower active pattern250is formed, and then the upper active pattern270may be formed. Therefore, the doping concentration of the lower active pattern250may be independently adjusted. As a result, the 3D semiconductor memory device having superior reliability can be implemented. The features of the method of fabricating 3D semiconductor memory device that is illustrated inFIG. 12Awill be described below with reference toFIG. 14.

FIG. 14is a cross-sectional view illustrating a modification example of a method of fabricating 3D semiconductor memory device according to another embodiment of the inventive concept. Referring toFIG. 14, a second conductive dopant is injected into a substrate100having a well region102, such that a common source region105may be formed. Insulation layers110and sacrificial layers112that are alternately and repeatedly stacked may be formed on the common source region105. An opening115and a recess region120may be formed by sequentially patterning the insulation layers110, the sacrificial layers112and the substrate100. The recess region120may pass through the common source region105, and thus the bottom surface of the recess region120may be lower than the lower surface of the common source region105. The bottom surface of the recess region120may expose the well region102, and the inner sidewall of the recess region120may expose the common source region105. Successive processes may be performed identically to the process that has been described above with reference toFIG. 13AthroughFIG. 13E. However, the process of forming the common source region105athat has been described above with reference toFIG. 13Cmay be omitted.

FIGS. 15A to 15Fare cross-sectional views illustrating other modification example of a method of fabricating 3D semiconductor memory device according to another embodiment of the inventive concept. A fabricating method according to the modification example may include the method that has been described above with reference toFIG. 14. Referring toFIGS. 14 and 15A, a lower active pattern250filling the recess region120may be formed on the substrate100having the opening115and the recess region120. The lower active pattern250may be formed identically to the process that has been described above with reference toFIG. 13B. The level of the upper surface of the lower active pattern250may be adjusted. InFIG. 15A, the upper surface of the lower active pattern250may be higher than the level of the upper surface of a lowermost sacrificial layer and lower than the level of the lower surface of a sacrificial layer just on the lowermost sacrificial layer. A first sub-layer147may be conformally formed on the substrate100having the lower active pattern250. A first semiconductor layer264may be conformally formed on the first sub-layer147. The first semiconductor layer264may be formed in a chemical vapor deposition process and/or an atomic layer deposition process. The first semiconductor layer264may be formed in a poly-crystalline state.

Referring toFIG. 15B, the first semiconductor layer264and the first sub-layer147may be blanket-anisotropic-etched until the upper surface of the lower active pattern250is exposed. Therefore, a first semiconductor pattern265may be formed in the opening115. According to an embodiment of the inventive concept, the center portion of the exposed upper surface of the lower active pattern250may be recessed lower than the edge portion of the upper surface of the lower active pattern250.

Referring toFIG. 15C, a second semiconductor layer may be conformally formed on the substrate100having the first semiconductor pattern265, and a filling dielectric layer may be formed on the second semiconductor layer. The second semiconductor layer may contact the first semiconductor pattern265and the center portion of the upper surface of the lower active pattern250. By planarizing the filling dielectric layer and the second semiconductor layer, a second semiconductor pattern267and a filling dielectric pattern132may be formed in the opening115. The first and second semiconductor patterns265and267may configure an upper active pattern270a, and the lower and upper active patterns250and270amay configure a vertical active pattern280a. Subsequently, a trench135, insulation patterns110aand sacrificial patterns112amay be formed by sequentially patterning the insulation layers110and the sacrificial layers112.

Referring toFIG. 15D, empty regions140may be formed by removing the sacrificial patterns112a. According to an embodiment of the inventive concept, the lowermost empty region of the empty regions140may expose the sidewall of the lower active pattern250, and empty regions on the lowermost empty region may expose the first sub-layer147. However, the inventive concept is not limited thereto. The number of empty regions for exposing the sidewall of the lower active pattern250may vary with the height of the edge portion of the upper surface of the lower active pattern250.

Referring toFIG. 15E, an oxide layer255may be formed by performing an oxidizing process in the exposed sidewall of the lower active pattern250. When the lower active pattern250is formed of silicon, the oxide layer255may be formed of a silicon oxide. The sidewall of the upper active pattern270amay not be oxidized by the first sub-layer147.

Referring toFIG. 15F, subsequently, a second sub-layer149may be conformally formed over the substrate100, and gate patterns155L,155a1,155aand155U respectively filling the empty regions140may be formed. Subsequently, an isolation pattern160a, an interlayer dielectric layer165, a contact plug167and a bit line170may be formed. Therefore, the 3D semiconductor memory device ofFIG. 12Ccan be implemented. In the fabricating method ofFIGS. 15A to 15F, the level of the upper surface of the lower active pattern250may be higher than the level of the upper surface of a sacrificial layer that is stacked secondarily from the upper surface of the substrate100and lower than the level of the lower surface of a thirdly-stacked sacrificial layer. In this case, the 3D semiconductor memory device ofFIG. 12Dcan be implemented. In the fabricating method ofFIGS. 15A to 15F, when the level of the upper surface of the lower active pattern250is disposed between the levels of the upper and lower surfaces of the lowermost sacrificial layer and the oxidizing process is omitted, the 3D semiconductor memory device ofFIG. 12Bcan be implemented. In the fabricating method ofFIGS. 15A to 15F, when the first sub-layer147is replaced by the gate dielectric layer150dand forming of the second sub-layer149is omitted, the 3D semiconductor memory device ofFIG. 12Ecan be implemented. Next, a method of fabricating the 3D semiconductor memory device that is illustrated inFIG. 12Fwill be described below with reference to the accompanying drawings. The method may include the method that has been described above with reference toFIG. 14.

FIGS. 16A and 16Bare cross-sectional views illustrating still other modification example of a method of fabricating 3D semiconductor memory device according to another embodiment of the inventive concept. Referring toFIGS. 14 and 16A, after a lower active pattern250may be formed, a protection dielectric layer may be conformally formed on the substrate100. The protection dielectric layer may be blanket-anisotropic-etched until the upper surface of the lower active pattern250is exposed. Therefore, a protection dielectric layer173may be formed to have a spacer shape in the sidewall of the opening115. Subsequently, a semiconductor layer may be conformally formed, and a filling dielectric layer may be formed. The filling dielectric layer and the semiconductor layer may be planarized, such that an upper active pattern270and a filling dielectric pattern132may be formed in the opening115.

Subsequently, the upper ends of the protection dielectric layer173, upper active pattern270and filling dielectric pattern132may be recessed, and then a capping semiconductor pattern175may be formed. The capping semiconductor pattern175may be formed in the same process as the process that has been described above with reference toFIG. 7B. Referring toFIG. 16B, a trench135, insulation patterns110aand sacrificial patterns112amay be formed by sequentially patterning insulation layers110and sacrificial layers112. Empty regions140may be formed by removing the sacrificial patterns112a. At this point, the protection dielectric layer173may be used an etch stop layer. Subsequently, by removing some portions of the protection dielectric layer173exposed to the empty regions140, some portions of the sidewall of the upper active pattern270may be exposed. Subsequently, the 3D semiconductor memory device ofFIG. 12Fcan be implemented by performing the method that has been described above with reference toFIGS. 13D and 13E. According to an embodiment of the inventive concept, after forming the empty regions140ofFIG. 16Band before forming a gate dielectric layer, an oxidizing process may be performed in the exposed sidewall of the lower active pattern250.

The 3D semiconductor memory devices according to embodiments of the inventive concept may be implemented as various types of packages. For example, the 3D semiconductor memory devices according to embodiments of the inventive concept may be packaged in a package type such as Package on Package (PoP), Ball Grid Arrays (BGAs), Chip Scale Packages (CSPs), Plastic Leaded Chip Carrier (PLCC), Plastic Dual In-Line Package (PDIP), Die In Waffle Pack (DIWP), Die In Wafer Form (DIWF), Chip On Board (COB), Ceramic Dual In-Line Package (CERDIP), Plastic Metric Quad Flat Pack (MQFP), Thin Quad Flat Pack (TQFP), Small Outline Package (SOP), Shrink Small Outline Package (SSOP), Thin Small Outline Package (TSOP), Thin Quad Flat Pack (TQFP), System In Package (SIP), Multi Chip Package (MCP), Wafer Level Stack Package (WLSP), Die In Wafer Form (DIWF), Die On Waffle Package (DOWP), Wafer-level Fabricated Package (WFP) and Wafer-Level Processed Stack Package (WSP).

A package on which the 3D semiconductor memory device according to embodiments of the inventive concept is mounted may further include at least one semiconductor device (for example, a controller, a memory device and/or a hybrid device) performing another function.

FIG. 17is a block diagram schematically illustrating an example of an electronic system including a 3D semiconductor memory device according to an embodiment of the inventive concept. Referring toFIG. 17, an electronic system1100according to an embodiment of the inventive concept may include a controller1110, an input/output (I/O) unit1120, a memory device1130, an interface1140, and a bus1150. The controller1110, the input/output (I/O) unit1120, the memory device1130and/or the interface1140may be connected through the bus1150. The bus1150corresponds to a path for transferring data.

The controller1110may include at least one of a microprocessor, a digital signal processor, a microcontroller, and logical devices for performing a function similar to the functions of the elements. The input/output unit1120may include a keypad, a keyboard, a display device and others. The memory device1130may store data and/or commands. The memory device1130may include at least one of the 3D semiconductor memory devices according to embodiments of the inventive concept. Also, the memory device1130may further include another type of semiconductor memory device (for example, Phase-change Random Access Memory (PRAM), Magnetoresistive Random Access Memory (MRAM), Dynamic Random Access Memory (DRAM) and/or Static Random Access Memory (SRAM)). The interface1140may transmit data to a communication network or receive data from the communication network. The interface1140may have a wired type or a wireless type. For example, the interface1140may include an antenna or a wired/wireless transceiver. Although not shown, the electronic system1100is a working memory device for improving the function of the controller1110, and may further include a high-speed DRAM and/or a high-speed SRAM.

The electronic system1100may be applied to Personal Digital Assistants (PDAs), portable computers, web tablets, wireless phones, mobile phones, digital music players, memory cards, and all electronic devices for transmitting/receiving information at a wireless environment.

FIG. 18is a block diagram schematically illustrating an example of a memory card including a 3D semiconductor memory device according to an embodiment of the inventive concept. Referring toFIG. 18, a memory card1200according to an embodiment of the inventive concept may include a memory device1210. The memory device1210may include at least one of the 3D semiconductor memory devices according to embodiments of the inventive concept. Also, the memory device1210may further include another type of semiconductor memory device (for example, PRAM, MRAM, DRAM and/or SRAM). The memory card1200may include a memory controller1220for controlling data exchange between a host and the memory device1210.

The memory controller1220may include a processing unit1222for controlling the overall operation of the memory card1200. Also, the memory controller1220may include an SRAM1221that is used as the working memory of the processing unit1222. Furthermore, the memory controller1220may further include a host interface1223and a memory interface1225. The host interface1223may include a data exchange protocol between the memory card1200and the host. The memory interface1225may connect the memory controller1220and the memory device1210. In addition, the memory controller1220may further include an error correction block (ECC)1224. The error correction block1224may detect and correct the error of data that is read from the memory device1210. Although not shown, the memory card1200may further include a ROM that stores code data for interfacing with the host. The memory card1200may be used as a portable data memory card. On the contrary, the memory card1200may be implemented as a Solid State Disk (SSD) that may replace the hard disk of a computer system.

According to the above-described 3D semiconductor memory device, the vertical active pattern can be disposed in the recess region of the common source region and be connected to the well region. Therefore, the distance between the vertical active pattern and the common source region can be minimized, and also, the vertical active pattern can be connected to the well region. As a result, the 3D semiconductor memory device which has excellent reliability and is optimized for high integration can be implemented.