Chip package and method for forming the same

A chip package including a chip having an upper surface, a lower surface and a sidewall is provided. The chip includes a signal pad region adjacent to the upper surface. A first recess extends from the upper surface toward the lower surface along the sidewall. At least one second recess extends from a first bottom of the first recess toward the lower surface. The first and second recesses further laterally extend along a side of the upper surface, and a length of the first recess extending along the side is greater than that of the second recess extending along the side. A redistribution layer is electrically connected to the signal pad region and extends into the second recess. A method for forming the chip package is also provided.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The invention relates to chip package technology, and in particular to a chip package and methods for forming the same.

2. Description of the Related Art

The chip packaging process is an important step in the fabrication of an electronic product. Chip packages not only protect the chips therein from outer environmental contaminants, but they also provide electrical connection paths between electronic elements inside and those outside of the chip packages. Conventional manufacturing processes of chip packages concern multiple patterning processes and material-deposition processes, which not only cost a lot but also require a long processing time.

Thus, there exists a need in the art for development of a chip package and methods for forming the same capable of mitigating or eliminating the aforementioned problems, and providing a simplified and fast chip-packaging technique.

BRIEF SUMMARY OF THE INVENTION

An embodiment of the invention provides a chip package comprising a chip having an upper surface, a lower surface and a sidewall. The chip comprises a signal pad region adjacent to the upper surface. A first recess extends from the upper surface toward the lower surface along the sidewall. At least one second recess extends from a first bottom of the first recess toward the lower surface. The first and second recesses further laterally extend along a side of the upper surface, and a length of the first recess extending along the side is greater than that of the second recess extending along the side. A redistribution layer is electrically connected to the signal pad region and extends into the second recess.

An embodiment of the invention provides a method for forming a chip package comprising providing a wafer having a plurality of chips, wherein each chip has an upper surface and a lower surface and comprises a signal pad region adjacent to the upper surface. A first recess is formed and extends from the upper surface toward the lower surface. At least one second recess is formed and extends from a first bottom of the first recess toward the lower surface. A redistribution layer extending into the second recess is formed to electrically connect to the signal pad region. The wafer is diced to separate the plurality of chips, such that each chip has a sidewall and the first recess extends along the sidewall. The first and second recesses further laterally extend a side of the upper surface. A length of the first recess extending along the side is greater than that of the second recess extending along the side.

DETAILED DESCRIPTION OF THE INVENTION

The making and using of the embodiments of the present disclosure are discussed in detail below. However, it should be noted that the embodiments provide many applicable inventive concepts that can be embodied in a variety of specific methods. The specific embodiments discussed are merely illustrative of specific methods to make and use the embodiments, and do not limit the scope of the disclosure. The disclosed contents of the present disclosure include all the embodiments derived from claims of the present disclosure by those skilled in the art. In addition, the present disclosure may repeat reference numbers and/or letters in the various embodiments. This repetition is for the purpose of simplicity and clarity, and does not imply any relationship between the different embodiments and/or configurations discussed. Furthermore, when a first layer is referred to as being on or overlying a second layer, the first layer may be in direct contact with the second layer, or spaced apart from the second layer by one or more material layers.

A chip package according to an embodiment of the present invention may be used to package micro-electro-mechanical system chips. However, embodiments of the invention are not limited thereto. For example, the chip package of the embodiments of the invention may be implemented to package active or passive devices or electronic components of integrated circuits, such as digital or analog circuits. For example, the chip package is related to optoelectronic devices, micro-electro-mechanical systems (MEMS), microfluidic systems, and physical sensors measuring changes to physical quantities such as heat, light, capacitance, pressure, and so on. In particular, a wafer-level package (WSP) process may optionally be used to package semiconductor chips, such as image-sensor elements, light-emitting diodes (LEDs), solar cells, RF circuits, accelerators, gyroscopes, microactuators, surface acoustic wave devices, pressure sensors, ink printer heads, and so on.

The above-mentioned wafer-level package process mainly means that after the package step is accomplished during the wafer stage, the wafer with chips is cut to obtain individual packages. However, in a specific embodiment, separated semiconductor chips may be redistributed on a carrier wafer and then packaged, which may also be referred to as a wafer-level package process. In addition, the above-mentioned wafer-level package process may also be adapted to form a chip package having multi-layer integrated circuit devices by stacking a plurality of wafers having integrated circuits.

Referring toFIG. 6, a cross-sectional view of an exemplary embodiment of a chip package according to the invention is illustrated. To simplify the diagram, only a portion of the chip package is shown herein. In the embodiment, the chip package comprises a chip100, a first recess220, a second recess230and a redistribution layer (RDL)280. The chip100has an upper surface100aand a lower surface100b. In one embodiment, the chip100comprises an insulating layer140adjacent to the upper surface100aand an underlying substrate150adjacent to the lower surface100b. In general, the insulating layer140may comprise an interlayer dielectric (ILD), an inter-metal dielectric (IMD) and a passivation layer. In the embodiment, the insulating layer140may comprise inorganic materials, such as silicon oxide, silicon nitride, silicon oxynitride, metal oxide, a combination thereof, or another suitable insulating material. In the embodiment, the substrate150may comprise silicon or another semiconductor material.

In the embodiment, the chip100may comprise a signal pad region160and a sensing region or device region200which may be adjacent to the upper surface100a. In one embodiment, the signal pad region160comprises a plurality of conducting pads and each conducting pad may be a single conducting layer or comprise multiple conducting layers. To simplify the diagram, only one conducting pad comprising a single conducting layer in the insulating layer140is depicted herein as an example. In the embodiment, the insulating layer140may comprise one or more openings exposing the respective conducting pads.

In one embodiment, the sensing region or device region200of the chip100comprises a sensing component which may be used for sensing biometric features (i.e., the chip100is a biometric sensing chip, such as a fingerprint-recognition chip). In another embodiment, the chip100may be used for sensing environmental features. For example, the chip100may comprise a temperature-sensing component, a humidity-sensing component, a pressure-sensing component, a capacitance-sensing component or another suitable sensing component. In yet another embodiment, the chip100may comprise an image-sensing component. In one embodiment, the sensing component in the chip100may be electrically connected to the signal pad region160by an interconnection structure (not shown) in the insulating layer140.

In one embodiment, the first recess220is located outside of the sensing region or device region200and the signal pad region160and extends from the upper surface100atoward the lower surface100balong a sidewall of the chip100to expose the underlying substrate150. In other embodiments, the first recess220may be located outside of the sensing region or device region200and expose the underlying substrate150.

The first recess220has a first sidewall220aand a first bottom220b. In the embodiment, the first sidewall220ais an edge of the insulating layer140. Moreover, the first bottom220bmay be located at or lower than an interface between the insulating layer140and the substrate150. In one embodiment, the first sidewall220amay substantially be perpendicular to the upper surface100a. In other embodiments, the first sidewall220amay be inclined to the upper surface100a. In addition, the first bottom220bis not limited to being parallel to the upper surface100a.

In one embodiment, the first recess220laterally extends across the entire length of four sides101,102,103and104of the upper surface100a, such that the sides101,102,103and104shift toward the inside of the upper surface100a, as shown inFIG. 7. In another embodiment, the first recess220may laterally extend across the entire length of the side101and further extend along the partial or entire length of the adjacent side102or103without extending along the side104. In yet another embodiment, the first recess220may laterally extend across the entire length of the side101and further extend along the partial or entire length of the two adjacent sides102and103without extending along the side104. In other embodiments, the first recess220may laterally extend along the partial or entire length of the side101without extending along the sides102,103and104.

The second recess230extends from the first bottom220bof first recess220toward the lower surface100balong the sidewall of the chip100. The second recess230has a second sidewall230aand a second bottom230b. In the embodiment, the second sidewall230ais substantially perpendicular to the upper surface100a. In other embodiments, the second sidewall230amay be inclined to the upper surface100a. In addition, the second bottom230bis not limited to being parallel to the upper surface100a.

In the embodiment, as shown inFIGS. 7 and 8, the chip package may comprise a plurality of individual second recesses230, which extend from the first bottom220btoward the lower surface100balong the partial length of the sides101,102,103and104of the upper surface100a, respectively. Moreover, the length L1of the first recess220laterally extending along the side101is greater than the length L2of the second recess230laterally extending along the side101. Similarly, the length of the first recess220laterally extending along the side102,103or104is greater than that of the respective second recess230laterally extending along the same side102,103or104. In addition, although not shown in the figures, it should be realized that the length of the first recess220and the location, number and size of the second recess230may have other arrangements as long as the length of the first recess220laterally extending along the side of the upper surface100ais greater than that of the respective second recess230laterally extending along the same side. For example, the chip package may merely comprise one second recess extending along the partial length of the side101,102,103or104while the first recess220may extend along the entire length of the same side.

In the embodiment, the first recess220is has the depth D1less than the depth D2of the second recess230, shown inFIG. 3. Moreover, the first bottom220bis has the width W1less than the width W2of the second bottom230b.

In one embodiment, an optional insulating layer260may be conformally disposed on the upper surface100aof the chip100. The insulating layer260extends onto the second sidewall230aand the second bottom230bthrough the first recess220, and exposes a portion of the signal pad region160. In the embodiment, the insulating layer260may comprise inorganic materials, such as silicon oxide, silicon nitride, silicon oxynitride, metal oxide, a combination thereof, or another suitable insulating material.

The redistribution layer280is patterned and conformally disposed on the insulating layer260. The redistribution layer280extends onto the second sidewall230aand the second bottom230band is electrically connected to the exposed signal pad region160. In one embodiment, the redistribution layer280does not reach an edge of the second bottom230b. In one embodiment, when the substrate150comprises a semiconductor material, the redistribution layer280can be electrically insulated from the semiconductor material by the insulating layer260. In one embodiment, the redistribution layer280may comprise copper, aluminum, gold, platinum, nickel, tin, a combination thereof, conductive polymer materials, conductive ceramic materials (such as indium tin oxide or indium zinc oxide), or another suitable conducting material.

A protection layer300is conformally disposed on the redistribution layer280and the insulating layer260and extends into the first recess220and the second recess230. The protection layer300comprises one or more openings exposing a portion of the redistribution layer280. In the embodiment, the protection layer300comprises openings320and340respectively exposing the redistribution layer280on the signal pad region160and in the second recess230. In another embodiment, the protection layer300may merely comprise the opening340. For example, the redistribution layer280on the signal pad region160may be fully covered by the protection layer300. In other embodiments, the protection layer300may comprise a plurality of openings340exposing portions of the redistribution layer280in the second recess230. In the embodiment, the protection layer300may comprise inorganic materials, such as silicon oxide, silicon nitride, silicon oxynitride, metal oxide, a combination thereof, or another suitable insulating material.

Another chip, such as a processor, an interposer or a circuit board380is attached onto the lower surface100bby an adhesive layer (such as a glue)360and is electrically connected to the signal pad region160through the redistribution layer280extending into the second recess230and a conducting structure440, such as a conducting bump or a bonding wire. In other embodiments, a circuit board (not shown) may additionally be disposed under the chip or interposer380to form a stacked chip package. Using the wire as an example, the wire440has a first end440adisposed on and electrically connected to the redistribution layer280extending into the second recess230through the opening340, and a second end440bdisposed on and electrically connected to the chip, interposer or circuit board380. In other embodiments, the first end440aof the wire440may be disposed on and electrically connected to the redistribution layer280on the signal pad region160through the opening320.

In one embodiment, the highest portion440cof the wire440is lower than the upper surface100a. In other embodiments, the highest portion440cof the wire440may protrude from the upper surface100a. Moreover, the wire440may comprise gold or another suitable conducting material.

An encapsulant layer (not shown) may optionally cover the conducting structure440and a portion of the chip100or it may further extend onto the upper surface100ato form a flat contacting region above the sensing region or device region200. In the embodiment, the encapsulant layer may comprise molding materials or sealing materials.

According to the aforementioned embodiments, since the chip100comprises the first and second recesses220and230and a portion of the conducting structure/wire440is disposed therein, the size of the chip package is reduced. When the highest portion of the conducting structure/wire440is lower than the upper surface100athrough the first and second recesses220and230, the size of the chip package can be reduced even further. Moreover, when the encapsulant layer further extends onto the upper surface100ato form a flat contacting region above the sensing region or device region200, the thickness of the encapsulant layer on the sensing region or device region200can be significantly reduced through the first and second recesses220and230, such that the sensitivity of the sensing region or device region200is increased.

An exemplary embodiment of a method for forming a chip package according to the invention is illustrated withFIGS. 1 to 6, whereinFIGS. 1 to 6are cross-sectional views of an exemplary embodiment of a method for forming a chip package according to the invention.

Referring toFIG. 1, a wafer having a plurality of chip regions120is provided. A plurality of chips100is defined by the chip regions120and scribe lines SC are defined between the chip regions120. To simplify the diagram, only a portion of the single chip region120is shown herein. The chip100has an upper surface100aand a lower surface100b. In one embodiment, the chip100comprises an insulating layer140adjacent to the upper surface100aand an underlying substrate150adjacent to the lower surface100b. In general, the insulating layer140may comprise an interlayer dielectric (ILD), an inter-metal dielectric (IMD) and a passivation layer. In the embodiment, the insulating layer140may comprise inorganic materials, such as silicon oxide, silicon nitride, silicon oxynitride, metal oxide, a combination thereof, or another suitable insulating material. In the embodiment, the substrate150may comprise silicon or another semiconductor material.

In the embodiment, the chip100in each chip region120may comprise a signal pad region160and a sensing region or device region200which are adjacent to the upper surface100a. In one embodiment, the signal pad region160comprises a plurality of conducting pads and each conducting pad may be a single conducting layer or comprise multiple conducting layers. To simplify the diagram, only one conducting pad comprising a single conducting layer in the insulating layer140is depicted herein as an example. In the embodiment, the insulating layer140may comprise one or more openings exposing the respective conducting pads.

In one embodiment, the sensing region or device region200of the chip100comprises a sensing component which may be used for sensing biometric features (i.e., the chip100is a biometric sensing chip, such as a fingerprint-recognition chip). In another embodiment, the chip100may be used for sensing environmental features. For example, the chip100may comprise a temperature-sensing component, a humidity-sensing component, a pressure-sensing component, a capacitance-sensing component or another suitable sensing component. In yet another embodiment, the chip100may comprise an image-sensing component. In one embodiment, the sensing component in the chip100may be electrically connected to the signal pad region160by an interconnection structure (not shown) in the insulating layer140.

Referring toFIG. 2, a first recess220may be formed in the chip100in each chip region120by lithography and etching processes (the etching process may comprise a dry etching process, a wet etching process, a plasma etching process, a reactive ion etching process or another suitable process) or a dicing process. The first recess220is formed outside of the sensing region or device region200and the signal pad region160in each chip region120and extends from the upper surface100atoward the lower surface100balong the scribe line SC between the chip regions120to expose the underlying substrate150. In other embodiments, the first recess220may be formed outside of the sensing region or device region200and expose the underlying substrate150.

The first recess220has a first sidewall220aand a first bottom220b. In the embodiment, the first sidewall220ais an edge of the insulating layer140. Moreover, the first bottom220bmay be located at or lower than an interface between the insulating layer140and the substrate150. In one embodiment, the first sidewall220amay substantially be perpendicular to the upper surface100a. In other embodiments, the first sidewall220amay be inclined to the upper surface100a. In addition, the first bottom220bis not limited to being parallel to the upper surface100a.

Referring toFIG. 3, one or more individual second recesses230may be formed in the chip100in each chip region120by lithography and etching processes (the etching process may comprise a dry etching process, a wet etching process, a plasma etching process, a reactive ion etching process or another suitable process) or a dicing process. The second recess230extends from the first bottom220bof first recess220toward the lower surface100balong the scribe line SC between the chip regions120. The second recess230has a second sidewall230aand a second bottom230b. In the embodiment, the second sidewall230ais substantially perpendicular to the upper surface100a. In other embodiments, the second sidewall230amay be inclined to the upper surface100a. In addition, the second bottom230bis not limited to being parallel to the upper surface100a.

In the embodiment, the first recess220is has the depth D1less than the depth D2of the second recess230, as shown inFIG. 3. Moreover, the first bottom220bis has the width W1less than the width W2of the second bottom230b, shown inFIG. 6.

Referring toFIG. 4, an optional insulating layer260may be conformally formed on the upper surface100aof the chip100by a deposition process (such as a coating process, a chemical vapor deposition process, a physical vapor deposition process or another suitable process). The insulating layer260extends to the second sidewall230aand the second bottom230bthrough the first recess220. In the embodiment, the insulating layer260may comprise inorganic materials, such as silicon oxide, silicon nitride, silicon oxynitride, metal oxide, a combination thereof, or another suitable insulating material.

Next, a portion of the insulating layer260on the signal pad region160is removed by lithography and etching processes (the etching process may comprise a dry etching process, a wet etching process, a plasma etching process, a reactive ion etching process or another suitable process) to expose a portion of the signal pad region160. A redistribution layer280is then patterned and conformally formed on the insulating layer260by a deposition process (such as a coating process, a chemical vapor deposition process, a physical vapor deposition process, an electroplating process, an electroless plating process or another suitable process) and lithography and etching processes. The redistribution layer280extends onto the second sidewall230aand the second bottom230band is electrically connected to the exposed signal pad region160. In one embodiment, the redistribution layer280does not reach an edge of the second bottom230b. In one embodiment, when the substrate150comprises a semiconductor material, the redistribution layer280can be electrically insulated from the semiconductor material by the insulating layer260. In one embodiment, the redistribution layer280may comprise copper, aluminum, gold, platinum, nickel, tin, a combination thereof, conductive polymer materials, conductive ceramic materials (such as indium tin oxide or indium zinc oxide), or another suitable conducting material.

Referring toFIG. 5, a protection layer300may be conformally formed on the redistribution layer280and the insulating layer260by a deposition process (such as a coating process, a chemical vapor deposition process, a physical vapor deposition process or another suitable process). The protection layer300extends into the first recess220and the second recess230. In the embodiment, the protection layer300may comprise inorganic materials, such as silicon oxide, silicon nitride, silicon oxynitride, metal oxide, a combination thereof, or another suitable insulating material.

Next, one or more openings may be formed in the protection layer300by lithography and etching processes (the etching process may comprise a dry etching process, a wet etching process, a plasma etching process, a reactive ion etching process or another suitable process) to expose a portion of the redistribution layer280. In the embodiment, the protection layer300comprises openings320and340respectively exposing the redistribution layer280on the signal pad region160and in the second recess230. In another embodiment, the protection layer300may merely comprise the opening340. For example, the redistribution layer280on the signal pad region160may be fully covered by the protection layer300. In other embodiments, the protection layer300may comprise a plurality of openings340exposing portions of the redistribution layer280in the second recess230. It should be realized that the number and position of openings in the protection layer300are determined by design requirements and it is not limited thereto.

Next, a dicing process is performed in the chip100along the scribe lines SC between the chip regions120to form a plurality of independent chips. After performing the dicing process, the first recess220extends from the upper surface100atoward the lower surface100balong a sidewall of the chip100and the second recess230extends from the first bottom220btoward the lower surface100balong the sidewall of the chip100. In one embodiment, the first recess220laterally extends to corners of the upper surface100aand extends continuously across the entire length of four sides101,102,103and104of the upper surface100a, such that the sides101,102,103and104shift toward the inside of the upper surface100a, as shown inFIG. 7. In another embodiment, the first recess220may laterally extend across the entire length of the side101and further extend along the partial or entire length of the adjacent side102or103without extending along the side104. In yet another embodiment, the first recess220may laterally extend across the entire length of the side101and further extend along the partial or entire length of the two adjacent sides102and103without extending along the side104. In other embodiments, the first recess220may laterally extend along the partial or entire length of the side101without extending along the sides102,103and104.

In the embodiment, as shown inFIGS. 7 and 8, the chip package comprises a plurality of individual second recesses230, which extend from the first bottom220btoward the lower surface100balong the partial length of the sides101,102,103and104of the upper surface100a, respectively. Moreover, the length L1of the first recess220extending along the side101is greater than the length L2of the second recess230extending along the side101. Similarly, the length of the first recess220extending along the side102,103or104is greater than that of the respective second recess230extending along the same side102,103or104. In addition, although not shown in the figures, it should be realized that when the first recess220laterally extends across the full length or width of one side of the upper surface100a, the second recess230laterally extending along the same side may have various configurations.

In the embodiment, the chip100comprises a step-like sidewall formed of the first and second sidewalls220aand230aand the first and second bottoms220band230b, and an adjacent cliff-form sidewall formed of only the first sidewall220aand the first bottom220b, as shown inFIGS. 7 and 8, whereinFIG. 8is a magnified perspective view of a portion P of the chip package shown inFIG. 7.

It is realized that the number of second recesses230shown inFIGS. 1 to 8is illustrated as an example and not limited thereto. The actual number of second recesses230is determined by design requirements. For example, in one embodiment, two or more continuous second recesses230may be formed in the chip100by performing several dicing processes or lithography and etching processes, such that the chip100may comprise a multi-step sidewall formed of the first sidewall220a, the first bottom220b, the second sidewalls230aand the second bottoms230b.

Referring toFIG. 6, another chip, such as a processor, an interposer or a circuit board380is attached onto the lower surface100bof the independent chip by an adhesive layer (such as a glue)360and is electrically connected to the signal pad region160through the redistribution layer280extending into the second recess230and a conducting structure440, such as a conducting bump or a bonding wire. In other embodiments, a circuit board (not shown) may additionally be disposed under the chip or interposer380to form a stacked chip package.

Using the wire as an example, the wire440having a first end440aand a second end440bis formed by a wire bonding process. The first end440ais formed on and electrically connected to the redistribution layer280extending into the second recess230through the opening340. The second end440bformed on and electrically connected to the chip, interposer or circuit board380. For example, the second end440bof the wire440may be formed initially and the first end440aof the wire440may be formed subsequently. In other embodiments, the first end440aof the wire440may be formed on and electrically connected to the redistribution layer280on the signal pad region160through the opening320.

In one embodiment, the highest portion440cof the wire440is lower than the upper surface100a. In other embodiments, the highest portion440cof the wire440may protrude from the upper surface100a. Moreover, the wire440may comprise gold or another suitable conducting material. Since the chip100comprises the first and second recesses220and230, the conducting path between the chip100and the chip, interposer or circuit board380can be led down from the upper surface100athrough the sidewall of the chip100.

In one embodiment, an encapsulant layer (not shown) may be formed on the chip100by a molding process or another suitable process. The encapsulant layer optionally covers the conducting structure440and a portion of the chip100or it may further extend onto the upper surface100ato form a flat contacting region above the sensing region or device region200. In the embodiment, the encapsulant layer may comprise molding materials or sealing materials.

In one embodiment, when the highest portion440cof the wire440is lower than the upper surface100athrough the first and second recesses220and230, the entire height of the chip package is significantly reduced. Moreover, since the thickness of the encapsulant layer on the sensing region or device region200can also be reduced through the first and second recesses220and230, the sensitivity of the sensing region or device region200is increased.

According to the aforementioned embodiments, since the highest portion of the conducting structure/wire440can be as low as possible by continuously forming the first and second recesses220and230in the chip100, rather than forming only one recess and directly extending it downward which removes too much substrate material, the chip100can have sufficient structural strength. Furthermore, undercutting at an interface between the insulating layer140and the substrate150can be prevented. As a result, the quality of the chip package is improved. Moreover, the first recess laterally spanning the entire width or length of the chip100allows greater flexibility in routing output signals of the chip package.