Non-volatile memory device and method for manufacturing same

According to an embodiment, a non-volatile memory device includes a first wiring provided on an underlayer, a first memory cell array provided on the first wiring and including a plurality of memory cells, a first select element including a first control electrode provided between the first wiring and the first memory cell array. The device also includes a second wiring provided at the same level as the first wiring and electrically connected to the first control electrode, and a first plug electrically connecting the first control electrode and the second wiring, one end of the first plug being in contact with the second wiring, and a side surface of the first plug being in contact with the first control electrode.

FIELD

Embodiments are generally related to a non-volatile memory device and a method for manufacturing the same.

BACKGROUND

A memory cell array having a three-dimensional structure has been studied for realizing next-generation non-volatile memory devices. For example, such a memory cell array is disposed above the drive circuit, which is provided in a semiconductor substrate. Select elements are provided between the drive circuit and the memory cell array, and each select element may be used to select one or more of the memory cells included in the memory cell array. Such a memory device may include vertical wirings (contact electrodes) that electrically connect the drive circuit and the memory cell array, and horizontal wirings that control the select elements.

On the other hand, when the number of wirings connecting the memory cell array and the drive circuit is increased, it leads to increase memory capacity, for example. Thus, a layout and structure of wirings are adjusted for shrinking the memory device.

DETAILED DESCRIPTION

According to an embodiment, a non-volatile memory device includes a first wiring provided on an underlayer, a first memory cell array provided on the first wiring and including a plurality of memory cells, a first select element including a first control electrode provided between the first wiring and the first memory cell array. The device also includes a second wiring provided at the same level as the first wiring and electrically connected to the first control electrode, and a first plug electrically connecting the first control electrode and the second wiring, one end of the first plug being in contact with the second wiring, and a side surface of the first plug being in contact with the first control electrode.

Hereinbelow, embodiments are described with reference to the drawings. Identical components in the drawings are marked with the same reference numerals, and a detailed description thereof is omitted as appropriate and different components are described. The drawings are schematic or conceptual; and the relationships between the thickness and width of portions, the proportions of sizes among portions, etc. are not necessarily the same as the actual values thereof. Further, the dimensions and proportions may be illustrated differently among drawings, even for identical portions.

FIG. 1is a schematic cross-sectional view of a non-volatile memory device1according to an embodiment. The non-volatile memory device1has a three-dimensional structure, and includes a memory portion5provided on an underlayer, a circuit6provided between the memory portion5and the underlayer, and a wiring layer7provided on the memory unit5, for example.

The underlayer is a silicon wafer, for example, and the circuit6that serves as a driver of the memory portion5is provided on the upper surface of the underlayer. The circuit6may be a CMOS logic circuit, for example. The underlayer is not limited to a silicon wafer, and may be a compound semiconductor substrate of silicon carbide (SiC) or the like, or a semiconductor layer or an insulating layer formed on a substrate, for example.

FIG. 2is a perspective view schematically showing one example of the memory unit5of the non-volatile memory device1according to the embodiment. The memory unit5includes a first wiring (hereinafter, a global bit line10) provided on the underlayer, a memory cell array20provided on the first wiring, and a select element, for example, a select transistor30provided between the global bit line10and the memory cell array20.

The global bit line10extends in a first direction (hereinafter, the X-direction) parallel to the upper surface of the underlayer, and select transistors30are aligned on the global bit line10. Each of the select transistors30includes an element portion31and a control electrode (hereinafter, a gate electrode35). The element portion31is connected to the global bit line10, and extends in a second direction (the Z-direction) perpendicular to the upper surface of the underlayer. The gate electrode35extends in a third direction (the Y-direction) crossing the X-direction in a plane parallel to the upper surface of the underlayer, and faces the side surface of the element portion31via a gate insulating film33. That is, the select transistor30is a thin film transistor (TFT) through which a current flows in the Z-direction, for example.

In this example, the first direction is the X-direction, the second direction is the Z-direction, and the third direction is the Y-direction. The extending directions of the wirings are orthogonal to one another, but are not limited to a case where the wirings are provided strictly orthogonal to each other. Some shifts from strictly orthogonal crossing may be allowable, for example, due to an accuracy limit of manufacturing technique etc. The third direction is not limited to the Y-direction orthogonal to the X-direction, and it may be sufficient in some cases to provide the wirings so that the third direction crosses the X-direction in the X-Y plane.

The memory cell array20includes local bit lines23(fifth wirings). Each local bit line23is connected to the element portion31, and extends in the Z-direction. That is, the select transistor30on/off-controls the electrical connection between the global bit line10and the local bit line23. Word lines25(fourth wirings) are provided via a memory layer27between the local bit lines23adjacent to each other in the X-direction. The word lines25are stacked via insulating films in the Z-direction.

FIG. 3is a transparent view from the upper side, showing one example of the memory portion5according to the embodiment.FIG. 3shows an arrangement of the word lines25with respect to the local bit lines23. InFIG. 3, the illustration of the insulating films provided between global bit lines10, and between local bit lines23in the Y-direction is omitted for convenience in viewing of the drawing.

As shown inFIG. 3, the global bit lines10extending are arranged in parallel so as to be aligned in the Y-direction. A plurality of local bit lines23are arranged on a global bit line10, and aligned in the X-direction. Local bit lines23are also arranged so as to be aligned in the Y-direction. That is, local bit lines23are arranged in a matrix configuration on the global bit lines10.

As shown inFIG. 3, at one level of the word lines25stacked in the Z-direction, word line combs25aand25bare provided. Each word line combs25aand25bhas an extending portion25cextending in the Y-direction between local bit lines23adjacent to each other in the X-direction and a common portion25dthat electrically bundles the extending portions25c, for example. The extending portions25cthat are disposed in every other space between local bit lines23adjacent to each other in the X-direction are electrically bundled by the common portion25d. The word line comb25ais provided so that each extending portion25cthereof is disposed on one side of each local bit line23in the X-direction, and the word line comb25bis provided so that each extending portion25cthereof is disposed on the other side.

A memory cell MC is formed in each portion where the local bit line23and the word line25(the extending portions25c) face each other across the memory layer27. That is, the memory cell array20includes memory cells (MC) that are three-dimensionally arranged therein.

In the specification, the word line combs25aand25bare collectively referred to as the word line25. Also for other components, there are a case where components of the same kind are distinguished by being marked with different reference numerals and a case where components of the same kind are collectively referred to using one reference numeral.

As shown inFIG. 3, the gate electrode35of the select transistor30extends in the Y-direction below the word line25. The gate electrode35faces the side surface of the element portion31provided under each local bit line23via the gate insulating film33.

The gate electrode35is provided on both sides of the element portion31in the X-direction, and both gate electrodes35face side surfaces of the element portion31opposite to each other, respectively. A gate electrode35aand a gate electrode35bare disposed alternately.

A shunt portion SNT is disposed between a memory cell array20aand a memory cell array20b.

The gate electrode35ahas a first portion35aaextending in the Y-direction, a turning portion35e, and a second portion35abextending in a direction opposite to the Y-direction, for example. The first portion35aaand the second portion35abface side surfaces of one element portion31opposite to each other, respectively.

On the other hand, the gate electrode35bhas a first portion35baextending in the Y-direction, a turning portion35e, and a second portion35bb. The first portion35baand the second portion35bbface side surfaces of one element portion31opposite to each other, respectively. Here, the turning portion35eis disposed in the shunt portion SNT. The layout of the gate electrode35aand the gate electrode35bmay be symmetrical in the Y-direction. Here, a contact portion is formed at the turning portion35e. By using such a layout, contact portions (where a plug50is to be formed) adjacent to each other in the X-direction can be disposed in a different position in Y-direction, and the distance between them can be widened. Placing turning portions35eso as to align in the X-direction can make it easy to connect the plug to the gate electrode35.

In the memory unit5according to the embodiment, a group of memory cells arranged along one local bit line23(for example, a first cell group) and another group of memory cells connected to one word line25(for example, a second cell group) share one memory cell. The first cell group is selected by turning one select transistor300N-state, and applying a voltage to the one word line25biases the second cell group. Thus, the memory cell shared with the first cell group and the second cell group can operate under the bias provided between the one local bit line23and the one word line25.

Next, the structure of the non-volatile memory device1is described in detail with reference toFIG. 1. In this example, the memory portion5includes a first memory cell array (hereinafter, the memory cell array20a) and a second memory cell array (hereinafter, the memory cell array20b). The memory cell arrays20aand20bare arranged on the underlayer so as to be aligned in the Y-direction.

As shown inFIG. 1, the global bit lines10are provided above an interlayer insulating film65that insulates each element of the circuit6from other. A first select element (hereinafter, a select transistor30a) is provided between the memory cell array20aand one global bit line10. On the other hand, a second select element (hereinafter, a select transistor30b) is provided between the memory cell array20band another global bit line10. In the cross section ofFIG. 1, the select transistor30aincludes a gate electrode35a, and the select transistor30bincludes a gate electrode35b. Both of the gate electrodes35aand35bextend in the Y-direction.

A second wiring (hereinafter, an inter-gate connection40) is provided between one group of global bit lines10provided under the memory cell array20aand another group of global bit lines10provided under the memory cell array20b. The inter-gate connection40is provided on the same level as the global bit lines10, and electrically connects the gate electrode35aand the gate electrode35b.

In the embodiment, a first plug (hereinafter, a plug50) is provided to electrically connect the gate electrode35aand the inter-gate connection40. The plug50is in contact with the inter-gate connection40at one end (the lower end) thereof, and in contact with the gate electrode35aat the side surface thereof. The gate electrode35bis also electrically connected to the inter-gate connection40via another plug50.

The gate electrode35is in contact with the side surface of the plug50at a side surface opposite to the memory cell array20. For example, when the surface facing the memory cell array20is the inner face, the gate electrode35is in contact with the plug50at the outer face thereof. Specifically, the gate electrode35is in contact with the plug50at the outer face of the turning portion35eshown inFIG. 3. The circuit6is provided below the global bit line10.

The circuit6includes a MOS (metal oxide semiconductor) transistor60provided on the upper surface of the underlayer, a wiring67, a contact plug68, and a connection terminal69, for example. The interlayer insulating film65is provided for electrically insulating these circuit elements from each other.

The MOS transistor60includes an active area61provided in the underlayer, for example a silicon wafer, a gate insulating film62, a gate electrode63, and source drain regions64. An STI (shallow trench isolation)66is provided between active areas61adjacent to each other in Y-direction.

On the other hand, the wiring layer7provided on the memory cell arrays20aand20bincludes a third wiring (hereinafter, an wiring71) electrically connected to each memory cell array20. The wiring71is provided in an interlayer insulating film73, and is electrically connected to, for example, the word line25of the memory cell array20. A pad wiring81is provided on the interlayer insulating film73. The pad wiring81is covered with an insulating film83and a protection film85.

As shown inFIG. 1, the connection terminal69of the circuit6is electrically connected to the wiring71via a second plug (hereinafter, a plug55). That is, the circuit6and the memory cell array20are electrically connected by the plug55and the wiring71.

The plugs50and55are contact plugs formed by the same step of a manufacturing process, for example. The gate electrode35and the inter-gate connection40are electrically connected by the plug50. That is, another end of the plug50on a side opposite to the one end in contact with the inter-gate connection40(an upper surface of the plug50) is not connected to an overlying wiring71, and covered with an insulating film. On the other hand, the plug55may be connected to the overlying wiring71.

Thus, it may become possible to simplify the manufacturing process by making electrical connection via the plug50between the gate electrode35and the inter-gate wiring40. In the case where the gate electrode35and the inter-gate connection40are directly brought in contact with each other, the gate electrode35is in contact with the inter-gate connection40via a contact hole, for example. The gate electrode35is formed on the insulating film16so as to be in contact with an exposed portion of the inter-gate connection in the contact hole. Subsequently, an insulating film is formed so as to cover the gate electrode35, and contact hole is formed for providing a plug55. In contrast to this, in the embodiment, a contact hole51for providing the plug50is formed simultaneously with a contact hole53for providing the plug55(FIG. 7B). Hence, the process step that forms a contact hole for exposing the inter-gate connection40in the insulating film16can be omitted, for example.

The inter-gate connection40is provided so as to avoid interfering with the plug55. That is, it becomes possible to downsize the non-volatile semiconductor memory device by using the inter-gate connection40, avoiding interfering with the plug55in a portion where the gate electrode35extending in the Y-direction and the plug55extending in the Z-direction cross each other.

There is a case where a word line WL is electrically connected to the underlying circuit6in the shunt region SNT between the memory cell arrays20aand20b, for example. Each word line WL is leads out from a word line hookup portion SK shown inFIG. 1to the overlying wiring71via a contact plug, and is also electrically connected to the underlying circuit6via the plug74, the connection terminal69, and the contact plug68. Here, the word line hookup portion SK is disposed on the upper side of the inter-gate connection40and the plug55. In this case, it is possible to draw a layout so as to avoid the interference between the plug55and the inter-gate connection40.

Since the gate electrode35may be formed by utilizing a sidewall as described later, it is difficult to flexibly draw a layout of a gate electrode35. On the other hand, a layout of the inter-gate connection40provided at one level lower than the gate electrode35is more flexibility than layout of the gate electrode35. Then, using the layout of the inter-gate connection40to avoid interference between the plug55and the inter-gate connection40, it is advantageous for shrinking the non-volatile semiconductor memory device.

Next, a method for manufacturing the non-volatile memory device1is described with reference toFIGS. 4 to 9.FIGS. 4 to 9are schematic views showing one example of the manufacturing process of the non-volatile memory device1according to the embodiment. The drawings show a process in which the memory portion5is formed on the circuit6provided, for example, on a silicon wafer.

FIG. 4is a perspective view schematically showing the global bit line10and the inter-gate connection40formed on the circuit6. In the drawing, the interlayer insulating film65is omitted in order to show the connection terminal69of the circuit6. Although one global bit line10is illustrated for convenience, a plurality of global bit lines10(not shown) are provided in this process.

The global bit line10and the inter-gate connection40are provided in the same wiring layer, and are formed simultaneously. For example, a metal film of tungsten (W) or the like is formed on the interlayer insulating film65using the CVD method, and then the configuration of the global bit line10and the inter-gate connection40are formed by a selective etching.

As shown inFIG. 4, the global bit line10is formed in a stripe shape extending in the X-direction. On the other hand, the inter-gate connection40has a portion40aextending in the Y-direction and portions40bbent in the X-direction at both ends of the portion40a. That is, the inter-gate connection40is formed to avoid overlapping with the underlying connection terminal69in the top view. The global bit line10and the inter-gate connection40are disposed in the same wiring layer, and may be formed simultaneously in the same processing step.

Next,FIG. 5Ais a plan view schematically showing the upper surface of the wafer, andFIGS. 5B and 5Cshow cross sections taken along line A-A and line B-B shown inFIG. 5A, respectively. A polysilicon (PS) wall, for example, is deposited above each global bit line10. For example, a polysilicon layer is formed above the global bit line10, and then selectively etched so that the PS-wall remains on each global bit line10. After that, an insulating film15(seeFIG. 7B) is deposited between the PS-walls. Further, an insulating film39is deposited above the PS-walls and the insulating film15.

As shown inFIG. 5A, the insulating film39includes portions formed in a stripe shape extending in the Y-direction (mask portions39aand39b). One end of the mask portion39ais located on the bent portion40bof the inter-gate connection40such that the mask portion39adoes not extend over an interconnecting space43between adjacent inter-gate connections40. On the other hand, the mask portion39bextends over the inter-gate connection40.

Next, the PS-wall and the insulating film15are etched using the insulating film39as a mask, and the PS-wall is processed like a pillar shape (PS-pillar). As shown inFIGS. 5B and 5C, a stripe core36including the PS-pillars and part of insulating film15is formed under the mask portion39a, and a stripe core37including the SP-pillars and another part of insulating film15is formed under the mask portion39b.

The stripe core36does not extend over the interconnecting space43between adjacent inter-gate connections40, and the stripe core37extends over the extending portion40aof the inter-gate connection40. That is, in the top view, the stripe core36is formed so as not to overlap with the connection terminal69of the circuit6. The stripe core37is formed above the global bit line10and on at least part of the inter-gate connection40.

Then, the insulating film16is deposited above the entire surface of wafer and etchback is performed to obtain a structure in which the insulating film16is disposed between the stripe core36and the stripe core37as shown inFIG. 5B, and between stripe cores37as shown inFIG. 5C. The insulating film16is formed such that the upper face of the insulating film16is lower than the upper faces of the stripe cores36and37.

FIG. 6is a perspective view schematically showing the arrangement of the stripe cores36and37. In the drawing, the illustration of insulating films is omitted in order to show the arrangement of the global bit line10, the inter-gate connection40, the connection terminal69, and the stripe cores36and37.

As shown inFIG. 6, the stripe core36does not extend on the interconnecting space43between inter-gate connections40adjacent to each other in the X-direction. On the other hand, the stripe core36extends over a portion of the inter-gate connections40avoiding the connection terminal69. As a result, an interconnecting space43is ensured between stripe cores37adjacent to each other in the X-direction. As described later, the plug55is formed in the interconnecting space43so as to be connected to the connection terminal69.

Next, the gate insulating film33and the gate electrode35are formed on the side surfaces of the stripe cores36and37(seeFIG. 8B). For example, a metal film that covers the stripe cores36and37is formed via the insulating film33, and then the metal film is etched back using RIE (reactive ion etching) so that a portion that serves as the gate electrode35is left on the side surfaces of the stripe cores36and37. That is, parts of the metal film formed between the stripe core36and the stripe core37and on upper portions thereof are removed (etched back) using anisotropic etching of RIE. Polysilicon or titanium nitride (TiN), for example, may be used for the metal film that forms the gate electrode35. The gate electrode35is formed on the insulating film16. That is, the gate electrode35is electrically isolated from the global bit line10via the insulating film16.

Thus, the gate electrode35is formed along the side surfaces of the stripe cores36and37. That is, the layout of the gate electrode35depends on the pattern of the stripe cores36and37, and it is difficult to draw a flexible design thereof.

Subsequently, an insulating film ZT is formed in the shunt portion SNT and between the gate electrodes35.

FIGS. 7A and 7Bare schematic views showing the wafer in which the contact holes51and53are formed.FIG. 7Ais a plan view showing the upper surface of the wafer, andFIG. 7Bis a cross-sectional view taken along line C-C shown inFIG. 7A.

A first contact hole (hereinafter, the contact hole51) is formed in the insulating film ZT so as to expose an upper surface of inter-gate connection40and a side surface of turning portion35e. And a second contact hole (hereinafter, the contact hole53) is formed in the insulating film ZT so as to expose an upper surface of the connection terminal69at the same time.

The contact holes51and53can be formed simultaneously using anisotropic etching of RIE. Here, the contact hole51removes the insulating film ZT and exposes the upper surface of the inter-gate connection40, while exposing the side surface of the gate electrode35. Here, the etching rate of the gate electrode35and the inter-gate connection40is set smaller than the etching rate of the insulating film. As a result, the bottom face of the contact hole51is located in the upper surface of the inter-gate connection40, and the bottom face of the contact hole53is located in the upper surface of the connection terminal69. The gate electrode35is left in the contact hole53, since it is not removed through the etching process. The contact holes51and53may be formed in a tapered shape such that a width thereof becomes narrower as the distance from the upper surface of the insulating film15becomes deeper.

When the contact hole51has a tapered shape, an etching mask (not shown) formed on the insulating film15may have a larger opening than the bottom area of the contact hole51formed in the upper surface of the inter-gate connection40, for example. Thereby, it is easy to form the contact holes51and53by photolithography, and then the etching process of the insulating film15becomes easy.

The turning portion35eof the gate electrode35ais exposed at the sidewall of the contact hole51. That is, the gate electrode35ais formed on the side surface of the stripe core36(seeFIG. 3). The portion35aaextending in the Y-direction is formed on one side surface of the stripe core36, and the portion35abextending in the opposite direction (the −Y direction) is formed on the other side surface of the stripe core36. The turning portion35eis formed in an end portion provided on the inter-gate connection40.

A width of the turning portion35eexposed form the contact hole51becomes thinner from bottom to top in the Z-direction, for example. That is, the width in the Y-direction of the turning portion35eis formed so as to become narrower as a distance from the inter-gate connection40increases in the Z-direction.

Next,FIGS. 8A to 8Care schematic views showing the wafer in which electrically conductive material, such as metal is buried in the contact holes51and53so as to form the plugs50and55.FIG. 8Ais a plan view showing the upper surface of the wafer.FIG. 8Bis a cross-sectional view taken along line D-D shown inFIG. 8A, andFIG. 8Cis a cross-sectional view taken along line E-E.

A barrier metal and a metal, for example, are buried in the contact holes51and53, and the upper surface of the wafer is planarized. For example, TiN may be used as the barrier metal covering the inner surfaces of the contact holes51and53. For example, Tungsten (W) may be used as the metal for filling the contact holes51and53. Since the plug50is in contact with the side surface of the gate electrode35at full length thereof, it is possible to reduce contact resistance therebetween.

As shown inFIG. 8C, the plug50is in contact with the inter-gate connection40at the bottom of the contact hole51. The plug50is in contact with the gate electrode35at the sidewall of the contact hole51. Thereby, electrical connection is obtained between the gate electrode35and the inter-gate connection40. The plug50has a shape in which its width becomes wider as a distance from the inter-gate connection40increases in the Z-direction.

On the other hand, one end of the plug55is in contact with the connection terminal69of the circuit6at the bottom of the contact hole53. The other end of the plug55is exposed at the upper surface of the insulating film15.

As shown inFIG. 8B, the gate electrode35ais formed on the side surface of the stripe core36via the gate insulating film33, and the gate electrode35bis formed on the side surface of the stripe core37via the gate insulating film33. Thereby, the select transistor30is formed in a portion including the PS-pillar (i.e. the element portion31) of the stripe cores36and37.

The gate electrode35is formed using anisotropic etching of RIE, and therefore has a shape in which the thickness becomes thinner as progressing in the Z-direction. That is, the gate electrode35is formed in a shape in which the thickness becomes thinner (that is, the width in the X-direction becomes narrower) as a distance from the global bit line10increases in the Z-direction.

Next, as shown inFIG. 9A, the memory cell array20and the wiring layer7are formed above the select transistor30.FIG. 9Ais a cross-sectional view taken along line F-F shown inFIG. 8A, for example.

The word line25is stacked on the select transistors30aand30band selectively etched into a prescribed shape, for example. Subsequently, the memory layer27and the local bit line23are formed in a trench provided between word lines25to complete the memory cell arrays20aand20b(seeFIG. 2).

As shown inFIG. 9A, the hookup portion SK includes stacked bodies SKA, SKB and SKC, and the stacked bodies SKA and SKC of word lines25and insulating films are disposed also on the plug50. However, since the stacked bodies SKA and SKC are stacked on the plug50via an insulating film26, the plug50is not electrically connected to each stacked body.

FIG. 9Bis an enlarged view of a region9B shown inFIG. 9A. As shown in the drawing, the plug50is in contact with the turning portion34eof the gate electrode35exposed at the sidewall of the contact hole51. The plug50is electrically connected only to the gate electrode35and the inter-gate wiring40.

Since the plug50for the connection of a gate electrode35C can be disposed below the hookup portion SK, it may be possible to downsize the layout space of the hookup portion SK.

Subsequently, the interlayer insulating film73is formed above the memory cell array20, and wirings71aand71bare formed in the interlayer insulating film73. The wirings71aand71bare electrically connected to one of the word lines25included in a stacked body SKB. The wiring71aand71binclude plugs74connecting to the plugs55. Here, the stacked body SKB is provide with a staircase form, wherein part of each word line25is exposed at any one of steps in the staircase form. Thus, the word lines25of all the layers may be electrically connected to the underlying circuit6via the wiring71and the plug55.FIG. 9Ashows one example, where the wirings71aand71bare respectively connected to word lines25in different steps. The wirings71aand71bare electrically connected also to the plug55. Then, the pad wiring81and the insulating films83and85are formed on the wiring layer7; thus, the non-volatile memory device1is completed (seeFIG. 1).

As shown inFIG. 9A, the word line25is electrically connected to the circuit6via the wiring71of the wiring layer7and the plug55. The circuit6applies a voltage to the word line25to drive a prescribed memory cell MC.

As mentioned above, the non-volatile memory device1according to the embodiment includes the two memory cell arrays20aand20b. A vertical wiring in the Z-direction (i.e. the plug55) is formed between the two memory cell arrays20aand20b, and makes electrical connection between the circuit6and each memory cell array. On the other hand, a horizontal wiring (i.e. the gate electrode35) formed on the side surfaces of the stripe cores36or37extends in the Y-direction. In this example, using the inter-gate connection40, the horizontal wiring is made to avoid interference with the vertical wiring; thereby, a margin for avoiding interference between the wirings is ensured in the Z-direction.

From another point of view, the select transistor30ahaving the gate electrode35aextending in the Y-direction and a select transistor30c(a third select element) having the gate electrode35bextending in the Y-direction likewise are formed between the memory cell array20aand the global bit line10. The select transistor30aand the select transistor30care aligned in the X-direction on the global bit line10, for example (seeFIG. 2).

On the other hand, the select transistor30bhaving the gate electrode35aand a select transistor30d(a fourth select element) having the gate electrode35bare formed between the memory cell array20band the global bit line10. The select transistor30band the select transistor30care disposed in the X-direction on the global bit line10, for example (seeFIG. 2).

As described in the manufacturing process mentioned above, one of the gate electrodes35ain memory cell array20aand the gate electrode35ain memory cell array20bare electrically connected via the inter-gate connection40. Then, the gate electrode35of one of select transistors30adjacent to each other in the X-direction is formed so as to avoid interference using the layout of the inter-gate connection40; thereby, a layout space43is ensured for forming the plug55.

Furthermore, the plug50may be formed simultaneously with the plug55, and the plug50electrically connects between the gate electrode35and the inter-gate wiring40. Thereby, the manufacturing process thereof can be simplified, and it becomes possible to improve manufacturing efficiency. Furthermore, the plug50has a tapered shape, where the upper end of the plug50is larger than the lower end thereof contacting the inter-gate wiring40. Thereby, it is easy to form the plug50by photolithography and etching, then it becomes possible to improve manufacturing yield.