MOLD-IN-MOLD STRUCTURE TO IMPROVE SOLDER JOINT RELIABILITY

A semiconductor package comprises a substrate having a first side and the second side, the second side comprising interconnect joints. One or more die stacks are over the first side of the substrate. An inner mold material having a low Young's modulus of less than 2500 MPa encapsulates the one or more die stacks. An outer mold material having a higher Young's modulus encapsulates the inner mold material.

TECHNICAL FIELD

Embodiments of the disclosure are in the field of semiconductor package and, in particular, a mold-in-mold structure to improve solder joint reliability.

BACKGROUND

Today's consumer electronics market frequently demands complex functions requiring very intricate circuitry. Scaling to smaller and smaller fundamental building blocks, e.g. transistors, has enabled the incorporation of even more intricate circuitry on a single die with each progressive generation. Semiconductor packages are used for protecting an integrated circuit (IC) chip or die, and also to provide the die with an electrical interface to external circuitry. With the increasing demand for smaller electronic devices, semiconductor packages are designed to be even more compact and must support larger circuit density, which in some cases may affect solder joint reliability.

For example, some semiconductor packages, such ball grid array (BGA) packages, may comprise a substrate, a die stack on the substrate, wire bonds coupling the die stack to the substrate, a mold material encapsulating the die stack and the wire bonds, and pads on a backside of the substrate to connect with other devices. The differing coefficients of thermal expansion (CTEs) of the substrate, the die stack, and the molding compound can create stress in the package caused by coefficient of thermal expansion (CTE) mismatches within the package. This can negatively affect the solder joint used to couple the package's pad to another the pad of another semiconductor package or a printed circuit board (PCB). This stress can cause cracks in the interconnect joint, cratering of the pads, etc.

Previous solutions to solve the problem include increasing solder resist openings and reducing die size. Sometime approaches place a bottom spacer between the die and the substrate, but results in an added expense. In addition, little improvement can be made through material choices, as the materials inside the package have already been optimized to get the most solder joint reliability (SJR).

Consequently, due to the nature of the problem, semiconductor manufacturers spend enormous resources to manage SJR, using for example, thermal cycling to test the reliability of the solder joints in BGA packages, especially NAND and 3D XPoint memory packages.

DESCRIPTION OF THE EMBODIMENTS

Embodiments of a mold-in-mold structure to improve solder joint reliability are described. In the following description, numerous specific details are set forth, such as specific material and tooling regimes, in order to provide a thorough understanding of embodiments of the present disclosure. It will be apparent to one skilled in the art that embodiments of the present disclosure may be practiced without these specific details. In other instances, well-known features, such as single or dual damascene processing, are not described in detail in order to not unnecessarily obscure embodiments of the present disclosure. Furthermore, it is to be understood that the various embodiments shown in the Figures are illustrative representations and are not necessarily drawn to scale. In some cases, various operations will be described as multiple discrete operations, in turn, in a manner that is most helpful in understanding the present disclosure, however, the order of description should not be construed to imply that these operations are necessarily order dependent. In particular, these operations need not be performed in the order of presentation.

One or more embodiments described herein are directed to a mold-in-mold structure to improve solder joint reliability in semiconductor packages. To provide context,FIG. 1is a diagram illustrating a cross-section view of a packaged system with a stacked die structure. As shown, the packaged system100includes stacked die102attached to a mold carrier or a substrate104. A rigid mold cap106is formed over the stacked die102and the substrate104to form a semiconductor package108. The semiconductor package108is attached to a board110(e.g., a PCB) with solder balls112or any type of interconnect architecture.

As described above, CTE mismatch between different materials comprising the package system100cause stresses in solder joints, which eventually fatigue and fail. As the z-height and complexity of die stacks increase, there is a need to improve solder joint reliability (SJR).

According to the disclosed embodiments, an additional low-modulus mold material is added within a mold cap that encapsulates die-stacks to aid the die-stacks in expanding or contracting more freely. The disclosed embodiments provide a semiconductor package comprising a substrate having a first side and the second side, the second side comprising interconnect joints. One or more die stacks are over the first side of the substrate. An inner mold material having a low Young's modulus of less than 2500 MPa encapsulates the stacks. An outer mold material having a higher Young's modulus encapsulates the inner mold material to provide a mold-in-mold structure. Such a mold-in-mold structure reduces the stress on interconnect joints, such as solder balls, which increases the life span of the interconnects.

FIG. 2is a diagram illustrating a cross-section view of a package system200comprising a semiconductor package having a mold-in-mold structure in accordance with the disclosed embodiments. An enlarged view of a portion of the package system200enclosed in a dashed box is also shown inFIG. 2. In embodiments, the package200comprises a semiconductor package202comprising a substrate204(e.g., a BGA substrate) having a first side and the second side, where the second side includes interconnect joints206. One or more die stacks208are over the first side of the substrate204. The substrate204may comprise any known substrate in the art. For example, an organic substrate, an inorganic substrate (e.g., ceramic substrate, silicon substrate, etc.), a combination of an organic substrate and an inorganic substrate, etc.

Each of the die stacks208comprise one or more die210attached to other die using die attach films (not shown). The die attach film can be formed from an epoxy adhesive for example. The package202also includes wire bonds209for coupling the dies210to the substrate204. The wire bonds209can be formed from copper or any other conductive materials known in the art. In an embodiment, the dies210may be offset from each other in order to provide access to the top surface of each of the dies210to allow for wire bonding from the top surface of the dies to the substrate204. In embodiments, the semiconductor package202may include other components other than one or more die stacks208, such as for example, an application-specific integrated circuit (ASIC) or integrated microelectromechanical systems (MEMS).

The interconnect joints206or any type of interconnect architecture couples the semiconductor package202to a board207(e.g., a printed circuit board (PCB)) or like receiving structure. The interconnect joints206can be solder bumps, gold bumps, conductive epoxy bumps, copper bumps, column-shaped bumps, spring-type connections, any other suitable interconnect joint known in the art (e.g., a pin grid array, a land grid array, etc.), or any combination thereof.

According to the disclosed embodiments, an inner mold material212having a low Young's modulus of less than 2500 Mpa is used to encapsulate the die stacks208(including the wire bonds209and die attach films), and an outer mold material214having a higher Young's modulus is used to encapsulate the inner mold material212to provide a mold-in-mold structure. The inner mold material212may have a low Young's modulus of 2500 Mpa or less over a temperature range of −50° C. to 270° C. The higher Young's modulus of the outer mold material214is at least approximately 20,000 MPa in embodiments. The coefficient of thermal expansion of the inner mold material212is not of significant importance to improving SJR.

In a further aspect of the disclosed embodiments, different ranges of the Young's modulus of the inner mold material212between 1 and 2500 MPa may be used to provide different ranges of SIR protection, where the higher the Young's modulus the lower the benefit. For example, the low Young's modulus of the inner mold material212may range from approximately 1 to 500 MPa to provide the greatest improvement in SJR. The low Young's modulus may range from approximately 501 to 1500 MPa to provide an intermediate improvement in SJR. The low Young's modulus may range from approximately 1501 to 2500 MPa to provide an incremental improvement in SJR. According to embodiments, using an inner mold material212having a Young's modulus of 500 MPa or less improves SJR by approximately 10 times using existing manufacturing processes and materials.

The mold-in-mold structure formed by the inner mold material212and the outer mold material214to improve solder joint reliability provides many advantages. The inner mold material212separates the outer mold material214from the die stacks208and absorbs stress that results from a CTE mismatch between the outer mold material214and die stacks208. Absorption of the stress by the inner mold material212assists with reducing the amount of stress transferred to the interconnect joints206and with minimizing or eliminating the occurrence of delamination within the package. In this way, interconnect joint reliability (e.g., SJR) may be improved. The inner mold material212is able to absorb the stress within the package system200because the inner mold material212has a Young's modulus that is lower than a Young's modulus of the outer mold material214. By absorbing the stress, the inner mold material212also enables fabrication of semiconductor packages that lack spacers and polyimide layers, which in turn reduces costs associated with semiconductor packaging.

In embodiments, the inner mold material212may comprise a soft material, while the outer mold material214may comprise a rigid material. The inner mold material212may can be any material that can be patterned. One example of such a material is a photoresist (e.g., photopolymeric photoresist, photodecomposing photoresist, photocrosslinking photoresist, self-assembled monolayer photoresist, and the like). In another embodiment, the material may include die attach film (DAF), such as KER-6020-F having a Young's Modulus of 6-21 Mpa over a temperature of −60 to 150° C.; DA7920 having a Young's Modulus of 1-30 Mpa over a temperature of −40 to 200° C.; and EM-770J1-P having a Young's Modulus of 1.1 Mpa (DMA 50° C.). In yet another embodiment, the material may include a glob top compound such as SMP-5008 having a Young's Modulus of 0-200 Mpa over a temperature of −50 to 190° C.

The thickness of the inner mold material212is application specific and depends on the z-height of the die stacks208. In one embodiment, the outer mold material214may comprise epoxy resin or any other suitable material known in the art. The outer mold material214is at least approximately 0.1 mm in thickness in some embodiments.

InFIG. 2, although the inner mold material212is shown encapsulating all the die stacks208, not all components of the semiconductor package202need to be embedded in the same material or a material having a same property. For example, one type of component could be embedded within one type of inner mold material having a different Young's modulus than another type of inner mold material embedding other components.

In yet another embodiment, the inner mold material212and/or the outer mold material214may be formed with more than one layer, where a first layer has a different Young's modulus than a second layer.

FIGS. 3A-3Cillustrate a process for fabricating a semiconductor package having a mold-in-mold structure.FIG. 3Aillustrates the fabrication process after one or more die stacks208are formed and coupled to the substrate204. In an embodiment, each die stack208comprises multiple dies stacked on one another. A pick and place machine may be used to place the die stack208on the substrate204. The substrate204may be formed from organic materials, inorganic materials, or any combination thereof. Next, the inner mold material212having a low Young's modulus of less than 2500 MPa is formed to encapsulate the one or more die stacks208and the substrate204. The inner mold material212encapsulate the top and lateral sides of the die stacks208. The inner mold material212can be formed, for example, by dispensing via a dispenser300, molding, lamination or printing. For example, a spin coating technique may be used to coat the die stack208and the substrate204. In one such embodiment, a soft material is used for the embedding of the die stacks208.

FIG. 3Bshows the process after the inner mold material212is patterned or cut away from edges of the substrate204to leave room for the outer mold material214. For example, the inner mold material212may be lithographically patterned. In one embodiment, the inner mold material212is cut away from edges of the substrate204a distance at least equal to the intended thickness of the outer mold material214. Rather than cover an entire area of the substrate204, in another embodiment, the mold material212may be patterned to only cover individual die stacks208, leaving remaining areas of the substrate204open.

FIG. 3Cshows the process after an outer mold material214having a higher Young's modulus is formed to encapsulate the inner mold material212and the substrate204. The outer mold material214may be deposited along a top and sidewalls of the inner mold material212.

In one embodiment, the process may further include attaching interconnect joints to a bottom side of the substrate204. In the embodiment, where the inner mold material212is patterned to only cover individual ones of the die stacks208, the process may further include enticing the die stacks such that portions of the outer mold material214are removed (e.g. with a saw or laser) between the die stacks208to provide singulated packages (not shown). The interconnect joints may then be attached to the bottom side of the substrates of the diced die stacks to form semiconductor packages.

FIG. 4is a cross-sectional side view of an integrated circuit (IC) device assembly that may include a mold-in-mold structure for improving solder joint reliability, in accordance with one or more of the embodiments disclosed herein.

Referring toFIG. 4, an IC device assembly400includes components having one or more integrated circuit structures described herein. The IC device assembly400includes a number of components disposed on a circuit board402(which may be, e.g., a motherboard). The IC device assembly400includes components disposed on a first face440of the circuit board402and an opposing second face442of the circuit board402. Generally, components may be disposed on one or both faces440and442. In particular, any suitable ones of the components of the IC device assembly400may include a number of RF filters fabricated on a semiconductor package using selective seeding, such as disclosed herein.

In some embodiments, the circuit board402may be a printed circuit board (PCB) including multiple metal layers separated from one another by layers of dielectric material and interconnected by electrically conductive vias. Any one or more of the metal layers may be formed in a desired circuit pattern to route electrical signals (optionally in conjunction with other metal layers) between the components coupled to the circuit board402. In other embodiments, the circuit board402may be a non-PCB substrate.

The IC device assembly400illustrated inFIG. 4includes a package-on-interposer structure436coupled to the first face440of the circuit board402by coupling components416. The coupling components416may electrically and mechanically couple the package-on-interposer structure436to the circuit board402, and may include solder balls (as shown inFIG. 4), male and female portions of a socket, an adhesive, an underfill material, and/or any other suitable electrical and/or mechanical coupling structure.

The package-on-interposer structure436may include an IC package420coupled to an interposer404by coupling components418. The coupling components418may take any suitable form for the application, such as the forms discussed above with reference to the coupling components416. Although a single IC package420is shown inFIG. 4, multiple IC packages may be coupled to the interposer404. It is to be appreciated that additional interposers may be coupled to the interposer404. The interposer404may provide an intervening substrate used to bridge the circuit board402and the IC package420. The IC package420may be or include, for example, a die or any other suitable component. Generally, the interposer404may spread a connection to a wider pitch or reroute a connection to a different connection. For example, the interposer404may couple the IC package420(e.g., a die) to a ball grid array (BGA) of the coupling components416for coupling to the circuit board402. In the embodiment illustrated inFIG. 4, the IC package420and the circuit board402are attached to opposing sides of the interposer404. In other embodiments, the IC package420and the circuit board402may be attached to a same side of the interposer404. In some embodiments, three or more components may be interconnected by way of the interposer404.

The interposer404may be formed of an epoxy resin, a fiberglass-reinforced epoxy resin, a ceramic material, or a polymer material such as polyimide. In some implementations, the interposer404may be formed of alternate rigid or flexible materials that may include the same materials described above for use in a semiconductor substrate, such as silicon, germanium, and other group III-V and group IV materials. The interposer404may include metal interconnects410and vias408, including but not limited to through-silicon vias (TSVs)406. The interposer404may further include embedded devices, including both passive and active devices. Such devices may include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, electrostatic discharge (ESD) devices, and memory devices. More complex devices such as radio-frequency (RF) devices, power amplifiers, power management devices, antennas, arrays, sensors, and microelectromechanical systems (MEMS) devices may also be formed on the interposer404. The package-on-interposer structure436may take the form of any of the package-on-interposer structures known in the art.

The IC device assembly400may include an IC package424coupled to the first face440of the circuit board402by coupling components422. The coupling components422may take the form of any of the embodiments discussed above with reference to the coupling components416, and the IC package424may take the form of any of the embodiments discussed above with reference to the IC package420.

The IC device assembly400illustrated inFIG. 4includes a package-on-package structure434coupled to the second face442of the circuit board402by coupling components428. The package-on-package structure434may include an IC package426and an IC package432coupled together by coupling components430such that the IC package426is disposed between the circuit board402and the IC package432. The coupling components428and430may take the form of any of the embodiments of the coupling components416discussed above, and the IC packages426and432may take the form of any of the embodiments of the IC package420discussed above. The package-on-package structure434may be configured in accordance with any of the package-on-package structures known in the art.

FIG. 5illustrates a computing device500in accordance with one implementation of the disclosure. The computing device500houses a board502. The board502may include a number of components, including but not limited to a processor504and at least one communication chip506. The processor504is physically and electrically coupled to the board502. In some implementations the at least one communication chip506is also physically and electrically coupled to the board502. In further implementations, the communication chip506is part of the processor504.

The processor504of the computing device500includes an integrated circuit die packaged within the processor504. In some implementations of the disclosure, the integrated circuit die of the processor includes a mold-in-mold structure for improving solder joint reliability, in accordance with implementations of embodiments of the disclosure. The term “processor” may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory.

The communication chip506also includes an integrated circuit die packaged within the communication chip506. In accordance with another implementation of embodiments of the disclosure, the integrated circuit die of the communication chip includes a mold-in-mold structure for improving solder joint reliability, in accordance with implementations of embodiments of the disclosure.

In further implementations, another component housed within the computing device500may contain an integrated circuit die that includes a mold-in-mold structure for improving solder joint reliability, in accordance with implementations of embodiments of the disclosure.

Thus, embodiments described herein include a mold-in-mold structure to improve sold or joint reliability in semiconductor packages.

Example embodiment 1: A semiconductor package comprises a substrate having a first side and the second side, the second side comprising interconnect joints. One or more die stacks are over the first side of the substrate. An inner mold material having a low Young's modulus of less than 2500 MPa encapsulates the one or more die stacks. An outer mold material having a higher Young's modulus encapsulates the inner mold material.

Example embodiment 2: The semiconductor package of embodiment 1, wherein the low Young's modulus of the inner mold material is approximately 2500 MPa or less over a temperature range of −50° C. to 270° C.

Example embodiment 3: The semiconductor package of embodiment 1 or 2, wherein the low Young's modulus of the inner mold material ranges from approximately 1 to 500 MPa.

Example embodiment 4: The semiconductor package of embodiment 1, 2 or 3, wherein the inner mold material improves solder joint reliability by approximately 10 times.

Example embodiment 5: The semiconductor package of embodiment 1, wherein the low Young's modulus of the inner mold material ranges from approximately 501 to 1500 MPa.

Example embodiment 6: The semiconductor package of embodiment 1, wherein the low Young's modulus of the inner mold material ranges from approximately 1501 to 2500 MPa.

Example embodiment 7: The semiconductor package of embodiment 1, 2, 3, 4, 5, or 6, wherein the higher Young's modulus of the outer mold material is approximately at least 20,000 MPa.

Example embodiment 8: The semiconductor package of embodiment 1, 2, 3, 4, 5, 6 or 7, wherein the outer mold material is at least approximately 0.1 mm in thickness.

Example embodiment 9: The semiconductor package of embodiment 1, 2, 3, 4, 5, 6, 7, wherein the inner mold material comprises one of: a photopolymeric photoresist, a photodecomposing photoresist, a photocrosslinking photoresist, a self-assembled monolayer photoresist, a die attach film, and a glob top compound.

Example embodiment 10: A package system comprises a printed circuit board and a semiconductor package. The semiconductor package comprises a substrate having a first side and the second side, the second side comprising an array of solder balls to couple the semiconductor package to printed circuit board. One or more die stacks are over the first side of the substrate. An inner mold material having a low Young's modulus of less than 2500 MPa encapsulates the one or more die stacks. An outer mold material having a higher Young's modulus encapsulates the inner mold material.

Example embodiment 11: The package system of embodiment 10, wherein the low Young's modulus of the inner mold material is approximately 2500 MPa or less over a temperature range of −50° C. to 270° C.

Example embodiment 12: The package system of embodiment 10, wherein the low Young's modulus of the inner mold material ranges from approximately 1 to 500 MPa.

Example embodiment 13: The package system of embodiment 10, 11, or 12, wherein the inner mold material improves solder joint reliability by approximately 10 times.

Example embodiment 14: The package system of embodiment 10, wherein the low Young's modulus of the inner mold material ranges from approximately 501 to 1500 MPa.

Example embodiment 15: The package system of embodiment 10, wherein the low Young's modulus of the inner mold material ranges from approximately 1501 to 2500 MPa.

Example embodiment 16: The package system of embodiment 10, 11, 12, 13, 14 or 15, wherein the higher Young's modulus of the outer mold material is approximately at least 20,000 MPa.

Example embodiment 17: The package system of embodiment 10, 11, 12, 13, 14, 15 or 16, wherein the outer mold material is at least approximately 0.1 mm in thickness.

Example embodiment 18: The package system of embodiment 10, 11, 12, 13, 14, 15, 16 or 17, wherein the inner mold material comprises one of: a photopolymeric photoresist, a photodecomposing photoresist, a photocrosslinking photoresist, a self-assembled monolayer photoresist, a die attach film, and a glob top compound.

Example embodiment 19: A method of fabricating a semiconductor package, comprises forming one or more die stacks over a first side of the substrate. An inner mold material having a low Young's modulus of less than 2500 MPa is used to encapsulate the one or more die stacks. An outer mold material having a higher Young's modulus is used to encapsulate the inner mold material.

Example embodiment 20: The method of embodiment 19, further comprising: forming the inner mold material having the low Young's modulus of approximately 2500 MPa or less over a temperature range of −50° C. to 270° C.

Example embodiment 21: The method of embodiment 19, further comprising: forming the inner mold material such that the low Young's modulus ranges from approximately 1 to 500 MPa.

Example embodiment 22: The method of embodiment 19, further comprising: forming the inner mold material such that the low Young's modulus ranges from approximately 501 to 1500 MPa.

Example embodiment 23: The method of embodiment 19, further comprising: forming the inner mold material such that the low Young's modulus ranges from approximately 1501 to 2500 MPa.

Example embodiment 24: The method of embodiment 19, 20, 21, 22, or 23, wherein forming an inner mold material further comprises: patterning the inner mold material away from edges of the substrate to leave room for the outer mold material.

Example embodiment 25: The method of embodiment 19, 20, 21, 22, or 23, wherein forming an inner mold material further comprises: patterning the inner mold material to only cover individual ones of the one or more die stacks.