Faster multi-cell read operation using reverse read calibrations

A memory device having a memory array with a plurality of memory cells electrically coupled to a plurality of wordlines and a plurality of bitlines and control logic coupled with the memory array. The control logic perform operations including: determining a metadata value characterizing a first read level voltage of a highest threshold voltage distribution of a subset of the plurality of memory cells, wherein the metadata value comprises at least one of a failed byte count or a failed bit count; adjusting, based on the metadata value, a second read level voltage for a second-highest threshold voltage distribution of the subset of the plurality of memory cells; and causing, to perform an initial calibrated read of the subset of the plurality of memory cells, the adjusted second read level voltage to be applied to a wordline of the plurality of wordlines to read the second-highest threshold voltage distribution.

TECHNICAL FIELD

Embodiments of the disclosure are generally related to memory sub-systems, and more specifically, relate to faster multi-cell read operation using reverse read calibration.

BACKGROUND

DETAILED DESCRIPTION

Embodiments of the present disclosure are directed to faster multi-cell read operation using reverse read calibration. One or more memory devices can be a part of a memory sub-system, which can be a storage device, a memory module, or a hybrid of a storage device and memory module. Examples of storage devices and memory modules are described below in conjunction withFIG.1A. In general, a host system can utilize a memory sub-system that includes one or more components, such as memory devices that store data. The host system can provide data to be stored at the memory sub-system and can request data to be retrieved from the memory sub-system.

A memory sub-system can include high density non-volatile memory devices where retention of data is desired when no power is supplied to the memory device. One example of non-volatile memory devices is a negative-and (NAND) memory device. Other examples of non-volatile memory devices are described below in conjunction withFIG.1A. A non-volatile memory device is a package of one or more dies. Each die can include two or more planes. For some types of non-volatile memory devices (e.g., NAND devices), each plane includes of a set of physical blocks. In some implementations, each block can include multiple sub-blocks. Each plane carries a matrix of memory cells formed onto a silicon wafer and joined by conductors referred to as wordlines and bitlines, such that a wordline joins multiple memory cells forming a row of the matrix of memory cells, while a bitline joins multiple memory cells forming a column of the matrix of memory cells.

Depending on the cell type, each memory cell can store one or more bits of binary information, and has various logic states that correlate to the number of bits being stored. The logic states can be represented by binary values, such as “0” and “1”, or combinations of such values. A memory cell can be programmed (written to) by applying a certain voltage to the memory cell, which results in an electric charge being held by the memory cell, thus allowing modulation of the voltage distributions produced by the memory cell. A set of memory cells referred to as a memory page can be programmed together in a single operation, e.g., by selecting consecutive bitlines.

Precisely controlling the amount of the electric charge stored by the memory cell allows establishing multiple logical levels, thus effectively allowing a single memory cell to store multiple bits of information. A read operation can be performed by comparing the measured threshold voltages (Vt) exhibited by the memory cell to one or more reference voltage levels in order to distinguish between two logical levels for single-level cell (SLCs) and between multiple logical levels for multi-level cells. In various embodiments, a memory device can include multiple portions, including, e.g., one or more portions where the sub-blocks are configured as SLC memory and one or more portions where the sub-blocks are configured as multi-level cell (MLC) memory that can store three bits of information per cell and/or (triple-level cell) TLC memory that can store three bits of information per cell. The voltage levels of the memory cells in TLC memory form a set of 8 programming distributions representing the8different combinations of the three bits stored in each memory cell. Depending on how the memory cells are configured, each physical memory page in one of the sub-blocks can include multiple page types. For example, a physical memory page formed from single level cells (SLCs) has a single page type referred to as a lower logical page (LP). Multi-level cell (MLC) physical page types can include LPs and upper logical pages (UPs), TLC physical page types are LPs, UPs, and extra logical pages (XPs), and QLC physical page types are LPs, UPs, XPs and top logical pages (TPs). For example, a physical memory page formed from memory cells of the QLC memory type can have a total of four logical pages, where each logical page can store data distinct from the data stored in the other logical pages associated with that physical memory page, which is herein referred to as a “page.”

A memory device typically experiences random workloads, which can impact the threshold voltage distributions, which can be shifted to higher or lower values. In order to compensate for various voltage distribution shifts, calibration operations can be performed in order to adjust the read level voltages. In certain memory devices, the adjustment can be performed based on values of one or more data state metrics obtained from a sequence of read and/or write operations. In an illustrative example, the data state metric can be represented by a raw bit error rate (RBER), which is the ratio of the number of erroneous bits to the number of all data bits stored in a certain portion of the memory device (e.g., in a specified data block). In these memory devices, sweep reads can be performed in order to create RBER/log likelihood ratio (LLR) profiles to error correction coding (ECC) and select the most efficient profile. However, these and other calibration techniques can exhibit pure accuracy and/or high latency. Furthermore, such techniques can be effectively “blind” with respect to the voltage distribution, which means that the threshold voltage estimate produced by such calibration techniques can gradually drift into the wrong voltage distribution valley, thus making the read data uncorrectable.

Additionally, some read voltage calibration operations adjust read level voltages, which are sequentially performed on memory cells of a page from a lowest threshold voltage distribution to a highest threshold voltage distribution. In order to avoid capacitive effects from both adjacent wordlines and a boosted voltage of unselected channels of three-dimensional (3D) NAND (e.g., vertical or V-NAND), sensing for the highest read level voltage can be performed first for a read operation. In certain devices, if a calibration to read level voltages is required based on the sensing operation, the wordline voltage is reduced so that read level voltages of respective threshold voltage distributions can be adjusted for read sensing, starting with a lowest threshold voltage distribution and moving to higher threshold voltage distributions, and ending with the highest threshold voltage distribution. This reduction in the wordline (WL) voltage to a read level voltage associated with the lowest threshold voltage distribution causes performance delays or latencies, e.g., due to the increase in read overhead time (tR) required to wait for the wordline voltage to settle down to a target read level voltage of the lowest threshold voltage distribution.

Aspects of the present disclosure address the above and other deficiencies through performing adjustments to read level voltages during a read calibration operation in a reverse order, namely, from a highest threshold voltage distribution to a lowest threshold voltage distribution. This reverse order allows the read level voltage adjustments to be made as the wordline voltage is reduced over time, e.g., while performing the read calibration operation. More specifically, in one embodiment, control logic of the NAND determines, based on a charge loss characteristic of a highest threshold voltage distribution, whether a charge loss of a subset of multiple memory cells satisfies a threshold voltage drop criterion. Satisfying the threshold voltage drop criterion can be understood as at least reaching a threshold change in voltage corresponding to a threshold charge loss (or temporal voltage shift).

In at least one embodiment, in response to the charge loss of a subset of a group memory cells not satisfying the threshold voltage drop criterion, the control logic determines that no adjustment is needed to the read level voltage for the highest threshold voltage distribution, e.g., by a target read level voltage becoming a reference read level voltage. In this embodiment, the control logic determines a metadata value characterizing a first read level voltage of the highest threshold voltage distribution of the subset of the group of memory cells, where the metadata value is at least one of a failed byte count (CFByte) or a failed bit count (CFBit). The failed byte count reflects (e.g., is equal to or is derived by a known transformation from) the number of bytes in the sensed data that have at least one non-conducting bitline. The failed bit count reflects (e.g., is equal to or is derived by a known transformation from) the number of non-conducting bitlines in the sensed data. In various implementations, the memory device can inspect four or eight bitlines in a byte when counting non-conducting bitlines.

In the at least one embodiment, the control logic further adjusts, based on the metadata value, a second read level voltage for a second-highest threshold voltage distribution of the subset of the group of memory cells. The control logic then, in this embodiment and to perform an initial calibrated read of the subset of the plurality of memory cells, causes the adjusted second read level voltage to be applied to a wordline of the plurality of wordlines to read the second-highest threshold voltage distribution. These updates to the read level voltages can continue to be performed sequentially to additional lower threshold voltage distributions of the group of memory cells, e.g., the third-highest threshold voltage distribution and the fourth-highest threshold voltage distribution.

In at least one embodiment, in response to the charge loss of the subset satisfying the threshold voltage drop criterion, the control logic begins the read calibration operation with a calibrated update also to the read level voltage of the highest threshold distribution. In this embodiment, the control logic first adjusts, based on the metadata value, the first read level voltage, and then causes the adjusted first read level voltage to be applied to a wordline of the memory array to read the highest threshold voltage distribution, e.g., to perform an initial calibrated read of the subset of the group of memory cells. These operations can be performed before moving to update and apply the second read level voltage to the second-highest threshold voltage distribution, and so forth, to the third-highest threshold voltage distribution, the fourth-highest threshold voltage distribution, and so on in subsequent calibrated reads.

Therefore, advantages of the systems and methods implemented in accordance with some embodiments of the present disclosure include, but are not limited to, improving the read overhead time (tR) by reducing the latency or delays associated with performing a read calibration operation. Other advantages will be apparent to those skilled in the art of read performance optimization in operating programmable memory devices, which will be discussed hereinafter.

In one embodiment, the memory sub-system110includes a memory interface component113. Memory interface component113is responsible for handling interactions of memory sub-system controller115with the memory devices of memory sub-system110, such as memory device130. For example, memory interface component113can send memory access commands corresponding to requests received from host system120to memory device130, such as program commands, read commands, or other commands. In addition, memory interface component113can receive data from memory device130, such as data retrieved in response to a read command or a confirmation that a program command was successfully performed. For example, the memory sub-system controller115can include a processor117(processing device) configured to execute instructions stored in local memory119for performing the operations described herein.

In at least one embodiment, memory device130includes a memory access manager configured to carry out memory access operations, e.g., in response to receiving memory access commands from memory interface113. In some implementations, local media controller135includes at least a portion of memory access manager and is configured to perform the functionality described herein. In some implementations, the memory access manager is implemented on memory device130using firmware, hardware components, or a combination of the above. In an illustrative example, the memory access manager receives, from a requestor, such as memory interface113, a request to read a data page of the memory device130. A read operation can include a series of read strobes, such that each strobe applied a certain read level voltage to a chosen wordline of a memory device130in order to compare the estimated threshold voltages VTof a set of memory cells to one or more read levels corresponding to the expected positions of the voltage distributions of the memory cells.

In some embodiments, the memory device130includes a page buffer152, which can provide the circuitry used to program data to the memory cells of the memory device130and to read the data out of the memory cells. In some embodiments, control logic of the local media controller135includes a calibration reader137that can implement or direct the read operations that include reverse read calibration and other related operations herein. In some embodiments, this control logic is integrated in whole or in part within the memory sub-system controller115and/or the host system120.

FIG.1Bis a simplified block diagram of a first apparatus, in the form of a memory device130, in communication with a second apparatus, in the form of a memory sub-system controller115of a memory sub-system (e.g., the memory sub-system110ofFIG.1A), according to an embodiment. Some examples of electronic systems include personal computers, personal digital assistants (PDAs), digital cameras, digital media players, digital recorders, games, appliances, vehicles, wireless devices, mobile telephones and the like. The memory sub-system controller115(e.g., a controller external to the memory device130), can be a memory controller or other external host device.

The memory device130includes an array of memory cells104logically arranged in rows and columns. Memory cells of a logical row are typically connected to the same access line (e.g., a word line) while memory cells of a logical column are typically selectively connected to the same data line (e.g., a bit line). A single access line can be associated with more than one logical row of memory cells and a single data line can be associated with more than one logical column. Memory cells (not shown inFIG.1B) of at least a portion of the array of memory cells104are capable of being programmed to one of at least two target data states.

Row decode circuitry108and column decode circuitry111are provided to decode address signals. Address signals are received and decoded to access the array of memory cells104. The memory device130also includes input/output (I/O) control circuitry112to manage input of commands, addresses and data to the memory device130as well as output of data and status information from the memory device130. An address register114is in communication with the I/O control circuitry112and row decode circuitry108and column decode circuitry111to latch the address signals prior to decoding. A command register124is in communication with the I/O control circuitry112and local media controller135to latch incoming commands.

A controller (e.g., the local media controller135internal to the memory device130) controls access to the array of memory cells104in response to the commands and generates status information for the external memory sub-system controller115, i.e., the local media controller135is configured to perform access operations (e.g., read operations, programming operations and/or erase operations) on the array of memory cells104. The local media controller135is in communication with row decode circuitry108and column decode circuitry111to control the row decode circuitry108and column decode circuitry111in response to the addresses.

The local media controller135is also in communication with a cache register118and a data register121. The cache register118latches data, either incoming or outgoing, as directed by the local media controller135to temporarily store data while the array of memory cells104is busy writing or reading, respectively, other data. During a program operation (e.g., write operation), data can be passed from the cache register118to the data register121for transfer to the array of memory cells104; then new data can be latched in the cache register118from the I/O control circuitry112. During a read operation, data can be passed from the cache register118to the I/O control circuitry112for output to the memory sub-system controller115; then new data can be passed from the data register121to the cache register118. The cache register118and/or the data register121can form (e.g., can form at least a portion of) the page buffer152of the memory device130. The page buffer152can further include sensing devices such as a sense amplifier, to sense a data state of a memory cell of the array of memory cells104, e.g., by sensing a state of a data line connected to that memory cell. A status register122can be in communication with I/O control circuitry112and the local memory controller135to latch the status information for output to the memory sub-system controller115.

The memory device130receives control signals at the memory sub-system controller115from the local media controller135over a control link132. For example, the control signals can include a chip enable signal CE #, a command latch enable signal CLE, an address latch enable signal ALE, a write enable signal WE #, a read enable signal RE #, and a write protect signal WP #. Additional or alternative control signals (not shown) can be further received over control link132depending upon the nature of the memory device130. In one embodiment, memory device130receives command signals (which represent commands), address signals (which represent addresses), and data signals (which represent data) from the memory sub-system controller115over a multiplexed input/output (I/O) bus134and outputs data to the memory sub-system controller115over I/O bus134.

For example, the commands can be received over input/output (I/O) pins [7:0] of I/O bus134at I/O control circuitry112and can then be written into a command register124. The addresses can be received over input/output (I/O) pins [7:0] of I/O bus134at I/O control circuitry112and can then be written into address register114. The data can be received over input/output (I/O) pins [7:0] for an 8-bit device or input/output (I/O) pins [15:0] for a 16-bit device at I/O control circuitry112and then can be written into cache register118. The data can be subsequently written into data register121for programming the array of memory cells104.

In an embodiment, cache register118can be omitted, and the data can be written directly into data register121. Data can also be output over input/output (I/O) pins [7:0] for an 8-bit device or input/output (I/O) pins [15:0] for a 16-bit device. Although reference can be made to I/O pins, they can include any conductive node providing for electrical connection to the memory device130by an external device (e.g., the memory sub-system controller115), such as conductive pads or conductive bumps as are commonly used.

FIG.2A-2Bare schematics of portions of an array of memory cells200A, such as a NAND memory array, as could be used in a memory of the type described with reference toFIG.1Baccording to an embodiment, e.g., as a portion of the array of memory cells104. Memory array200A includes access lines, such as word lines2020to202N, and data lines, such as bit lines2040to204M. The word lines202can be connected to global access lines (e.g., global word lines), not shown inFIG.2A, in a many-to-one relationship. For some embodiments, memory array200A can be formed over a semiconductor that, for example, can be conductively doped to have a conductivity type, such as a p-type conductivity, e.g., to form a p-well, or an n-type conductivity, e.g., to form an n-well.

Memory array200A can be arranged in rows (each corresponding to a word line202) and columns (each corresponding to a bit line204). Each column can include a string of series-connected memory cells (e.g., non-volatile memory cells), such as one of NAND strings2060to206M. Each NAND string206can be connected (e.g., selectively connected) to a common source (SRC)216and can include memory cells2080to208N. The memory cells208can represent non-volatile memory cells for storage of data. The memory cells208of each NAND string206can be connected in series between a select gate210(e.g., a field-effect transistor), such as one of the select gates2100to210M(e.g., that can be source select transistors, commonly referred to as select gate source), and a select gate212(e.g., a field-effect transistor), such as one of the select gates2120to212M(e.g., that can be drain select transistors, commonly referred to as select gate drain). Select gates2100to210Mcan be commonly connected to a select line214, such as a source select line (SGS), and select gates2120to212Mcan be commonly connected to a select line215, such as a drain select line (SGD). Although depicted as traditional field-effect transistors, the select gates210and212can utilize a structure similar to (e.g., the same as) the memory cells208. The select gates210and212can represent a number of select gates connected in series, with each select gate in series configured to receive a same or independent control signal.

A source of each select gate210can be connected to common source216. The drain of each select gate210can be connected to a memory cell2080of the corresponding NAND string206. For example, the drain of select gate2100can be connected to memory cell2080of the corresponding NAND string2060. Therefore, each select gate210can be configured to selectively connect a corresponding NAND string206to the common source216. A control gate of each select gate210can be connected to the select line214.

The drain of each select gate212can be connected to the bit line204for the corresponding NAND string206. For example, the drain of select gate2120can be connected to the bit line2040for the corresponding NAND string2060. The source of each select gate212can be connected to a memory cell208Nof the corresponding NAND string206. For example, the source of select gate2120can be connected to memory cell208Nof the corresponding NAND string2060. Therefore, each select gate212can be configured to selectively connect a corresponding NAND string206to the corresponding bit line204. A control gate of each select gate212can be connected to select line215.

The memory array200A inFIG.2Acan be a quasi-two-dimensional memory array and can have a generally planar structure, e.g., where the common source216, NAND strings206and bit lines204extend in substantially parallel planes. Alternatively, the memory array200A inFIG.2Acan be a three-dimensional memory array, e.g., where NAND strings206can extend substantially perpendicular to a plane containing the common source216and to a plane containing the bit lines204that can be substantially parallel to the plane containing the common source216.

Typical construction of memory cells208includes a data-storage structure234(e.g., a floating gate, charge trap, and the like) that can determine a data state of the memory cell (e.g., through changes in threshold voltage), and a control gate236, as shown inFIG.2A. The data-storage structure234can include both conductive and dielectric structures while the control gate236is generally formed of one or more conductive materials. In some cases, memory cells208can further have a defined source/drain (e.g., source)230and a defined source/drain (e.g., drain)232. The memory cells208have their control gates236connected to (and in some cases form) a word line202.

A column of the memory cells208can be a NAND string206or a number of NAND strings206selectively connected to a given bit line204. A row of the memory cells208can be memory cells208commonly connected to a given word line202. A row of memory cells208can, but need not, include all the memory cells208commonly connected to a given word line202. Rows of the memory cells208can often be divided into one or more groups of physical pages of memory cells208, and physical pages of the memory cells208often include every other memory cell208commonly connected to a given word line202. For example, the memory cells208commonly connected to word line202Nand selectively connected to even bit lines204(e.g., bit lines2040,2042,2044, etc.) can be one physical page of the memory cells208(e.g., even memory cells) while memory cells208commonly connected to word line202Nand selectively connected to odd bit lines204(e.g., bit lines2041,2043,2045, etc.) can be another physical page of the memory cells208(e.g., odd memory cells).

Although bit lines2043-2045are not explicitly depicted inFIG.2A, it is apparent from the figure that the bit lines204of the array of memory cells200A can be numbered consecutively from bit line2040to bit line204M. Other groupings of the memory cells208commonly connected to a given word line202can also define a physical page of memory cells208. For certain memory devices, all memory cells commonly connected to a given word line can be deemed a physical page of memory cells. The portion of a physical page of memory cells (which, in some embodiments, could still be the entire row) that is read during a single read operation or programmed during a single programming operation (e.g., an upper or lower page of memory cells) can be deemed a logical page of memory cells. A block of memory cells can include those memory cells that are configured to be erased together, such as all memory cells connected to word lines2020-202N(e.g., all NAND strings206sharing common word lines202). Unless expressly distinguished, a reference to a page of memory cells herein refers to the memory cells of a logical page of memory cells. Although the example ofFIG.2Ais discussed in conjunction with NAND flash, the embodiments and concepts described herein are not limited to a particular array architecture or structure, and can include other structures (e.g., SONOS, phase change, ferroelectric, etc.) and other architectures (e.g., AND arrays, NOR arrays, etc.).

FIG.2Bis another schematic of a portion of an array of memory cells200B as could be used in a memory of the type described with reference toFIG.1B, e.g., as a portion of the array of memory cells104. Like numbered elements inFIG.2Bcorrespond to the description as provided with respect toFIG.2A.FIG.2Bprovides additional detail of one example of a three-dimensional NAND memory array structure. The three-dimensional NAND memory array200B can incorporate vertical structures which can include semiconductor pillars where a portion of a pillar can act as a channel region of the memory cells of NAND strings206. The NAND strings206can be each selectively connected to a bit line2040-204Mby a select transistor212(e.g., that can be drain select transistors, commonly referred to as select gate drain) and to a common source216by a select transistor210(e.g., that can be source select transistors, commonly referred to as select gate source). Multiple NAND strings206can be selectively connected to the same bit line204. Subsets of NAND strings206can be connected to their respective bit lines204by biasing the select lines2150-215Kto selectively activate particular select transistors212each between a NAND string206and a bit line204. The select transistors210can be activated by biasing the select line214. In some embodiments, each sub-block or string of memory cells has a separate select line214from other sub-blocks or strings. In some embodiments, a pair of sub-blocks shares a select line214. Each word line202can be connected to multiple rows of memory cells of the memory array200B. Rows of memory cells that are commonly connected to each other by a particular word line202can collectively be referred to as tiers.

FIG.3is a conceptual depiction of threshold voltage ranges of multiple memory cells.FIG.3illustrates an example of threshold voltage ranges and their distributions for a population of a sixteen-level memory cells, e.g., QLC memory cells. For example, such a memory cell can be programmed to a threshold voltage (Vt) that falls within one of sixteen different threshold voltage ranges3300-33015, each being used to represent a data state corresponding to a bit pattern of four bits. The threshold voltage range3300typically has a greater width than the remaining threshold voltage ranges3301-33015as memory cells are generally all placed in the data state corresponding to the threshold voltage range3300, then subsets of those memory cells are subsequently programmed to have threshold voltages in one of the threshold voltage ranges3301-33015. As programming operations are generally more incrementally controlled than erase operations, these threshold voltage ranges3301-33015can tend to have tighter distributions.

The threshold voltage ranges3300,3301,3302,3303,3304,3305,3306,3307,3308,3309,33010,33011,33012,33013,33014, and33015can each represent a respective data state, e.g., L0, L1, L2, L3, L4, L5, L6, L7, L8, L9, L10, L11, L12, L13, L14and L15, respectively. As an example, if the threshold voltage of a memory cell is within the first of the sixteen threshold voltage ranges3300, the memory cell in this case can be storing a data state L0having a data value of logical ‘1111’ and is typically referred to as the erased state of the memory cell. If the threshold voltage is within the second of the sixteen threshold voltage ranges3301, the memory cell in this case can be storing a data state L1having a data value of logical ‘0111’. If the threshold voltage is within the third of the sixteen threshold voltage ranges3302, the memory cell in this case can be storing a data state L2having a data value of logical ‘0011,’ and so on. Table 1 provides one possible correspondence between the data states and their corresponding logical data values. Other assignments of data states to logical data values are known or can be envisioned. Memory cells remaining in the lowest data state (e.g., the erased state or L0data state), as used herein, will be deemed to be programmed to the lowest data state.

FIG.4is a conceptual depiction of a threshold voltage distribution of multiple memory cells following a programming operation. The threshold voltage distributions430d-430d+1ofFIG.4can represent some portion of the distributions for threshold voltage ranges3300-33015ofFIG.3at the completion of a programming operation for memory cells. With reference toFIG.4, adjacent threshold voltage distributions430are typically separated by some margin432(e.g., dead space) at the completion of programming. Applying a sense voltage (e.g., read level voltage) within the margin432to the control gates of the multiple memory cells can be used to distinguish between the memory cells of the threshold voltage distribution430d(and any lower threshold voltage distribution) and the memory cells of the threshold voltage distribution430d−1(and any higher threshold voltage distribution).

Due to the phenomenon known as slow charge loss, the threshold voltage of a memory cell changes in time as the electric charge of the cell is degrading, which is referred to as “temporal voltage shift” (since the degrading electric charge causes the voltage distributions to shift along the voltage axis towards lower voltage levels). The threshold voltage is changing rapidly at first (immediately after the memory cell was programmed), and then slows down in an approximately logarithmic linear fashion with respect to the time elapsed since the cell programming event. This temporal voltage shift, if left unadjusted, reduces the margin432between the threshold voltage distributions430d-430d−1over time, and can cause these threshold voltage distributions to overlap, as illustrated inFIG.10, making it more difficult to distinguish between adjacent threshold voltage distributions. Accordingly, failure to mitigate the temporal voltage shift caused by the slow charge loss can result in the increased bit error rate in read operations, which the fast read calibration described herein is intended to mitigate.

FIG.5Ais a set of graphs illustrating an example of a read calibration based on a metadata value according to at least one embodiment. In some embodiments, the calibration reader137utilizes memory device-originated metadata that characterizes voltage distributions for adjusting read level voltages. More specifically, in various embodiments, the temporal voltage shift discussed above can be selectively tracked for programmed pages or blocks grouped by time after program (TAP). In some embodiments, the temporal voltage shift provides an initial estimate of a charge loss characteristic. In at least some embodiments, the calibration reader137causes a dual-strobe sensing operation be performed directed at a highest read level voltage of a subset of a group of memory cells, which is discussed in more detail with reference toFIGS.9-11B.

In these embodiments, the dual-strobe sensing operation can estimate a charge loss between a target read level (LV_target) and a low read level voltage (LV_low) using such a charge loss characteristic. The calibration reader137can also measure the metadata value (whether CFByte or CFBit) using the first read strobe of the dual-strobe sensing operation, e.g., at the LV_target, and estimate, based on an average metadata value across the memory cells of the measured highest threshold voltage distribution, a read level voltage offset (illustrated as “D”). Accordingly, the memory device130can, in response to a read strobe, return one or more metadata values to the calibration reader137.

In an illustrative example, the memory device130can, upon performing the read strobe, return the failed byte count (CFByte). The failed byte count reflects (e.g., is equal to or is derived by a known transformation from) the number of bytes in the sensed data that have at least one non-conducting bitline. Given the use of a data scrambler of the memory device130, the CFByte value at a given read threshold voltage can have a strong correlation to the minimum valley location, as illustrated inFIG.5A. In another illustrative example, the memory device can, upon performing a read strobe, return the failed bit count (CFBit). The failed bit count reflects (i.e., is equal to or is derived by a known transformation from) the number of non-conducting bitlines in the sensed data. In various embodiments, the memory device can inspect four or eight bitlines in a byte when counting non-conducting bitlines.

The metadata values received from the memory device130in response to a read strobe can be used by the memory sub-system controller115or by control logic of the local media controller135(e.g., by the calibration reader137) to adjust the applied read level voltages in order to compensate for the voltage distribution shift. In some embodiments, the control logic utilizes one or more returned metadata values to index within a lookup table that maps memory device-originated metadata values (e.g., failed byte counts or failed bit counts) to the read voltage adjustment values (e.g., read voltage offsets). Then, the control logic can utilize the determined read voltage offset to adjust the read level voltage for performing the next read strobe in a sensing or read operation. In at least some embodiments, the control logic determines an estimated read position based on an average CFByte (or CFBit) at the valley14bottom (e.g., r14), and reduces the read level voltage for valley14by the read voltage offset within QLC-based memory. While QLC-based memory cells are used as exemplary, the principles and present disclosure equally apply to other multi-level memory cells.

FIG.5Bis a graph illustrating an example highest read level voltage change compared to an average failed count byte (CFByte) for different time after program (TAP) time periods according to at least one embodiment. As can be seen, the highest read level voltage is the fifteenth read level voltage (r15) of QLC-based memory cells, which may incur about 350 mV of charge loss within a minute of TAP and that CFByte (CFBit) generally decreases with charge loss as the TAP proceeds to 60, 120, 240, 480, and 960 minutes, for example.

FIG.5Cis a graph illustrating an average charge loss of a highest read level voltage compared to an average charge loss for a number of lower read level voltages according to at least one embodiment. The highest read level voltage may be the fifteenth read level voltage (r15) and the average charge loss is greatest for higher read level voltages (e.g., r9-r14) and smallest for the lower read level voltages (e.g., r1-r8).

In various embodiments, the control logic determines a read voltage offset of the highest read level voltage (r15) by a metadata value (e.g., CFByte or CFBit value) correlation and determines other read voltage offsets of the other lower read level voltages (e.g., r1through r14) via SCL characterization. In these embodiments, the metadata value can be determined via a first read strobe (of the dual-strobe sensing operation) that senses a target read level voltage (LV_target).

In these embodiments, the control logic can then use the metadata value (e.g., CFByte/CFBit value) to determine a Charge Loss Bucket Classifier (CBC) value that may be used to index within the lookup table that was previously referenced. The CBC value can then return a series of wordline (WL) voltage offsets that the control logic can cause to be applied to the read level voltage for sensing operation of corresponding threshold voltage distributions for a given page of data. For example, for a lower page (LP) of data of QLC-based memory cells, the page of data can include the L11, L6, L4, and L1threshold voltage distributions. Further, for an upper page (UP) of data, the page of data can include the L13, L9, L7, and L3threshold voltage distributions. Further, for an extra page (XP) of data, the page of data can include the L14, L8, and L2threshold voltage distributions. Finally, for a top page (TP) of data, the page of data can include the L15, L12, L10, and L5threshold voltage distributions.

By way of example, an exemplary lookup table for the TP is illustrated in Table 2. The lookup tables for each of the LP, UP, and XP may be similar, but index to different read voltage offsets for different threshold voltage distributions, which were referenced above. The calibration reader137(or other control logic of the local media controller135) can access these lookup tables within local memory to the memory device130, which may also be loaded into a type of cache for fast access. As discussed, each of the different read voltage offsets may be determined via device-originated metadata that characterizes voltage distributions with corresponding read voltage offsets, e.g., by employing information such as that illustrated inFIGS.5A-5B.

FIG.6is a graph depicting an example read calibration operation in which read level voltage adjustments are sequentially performed on memory cells of a page from a lowest threshold voltage distribution to a highest threshold voltage distribution according to an embodiment. In this example, the read level voltage adjustments are made sequentially to the read level voltages R5, R10, R12, and R15that read the L5, L10, L12, and L15threshold voltage distributions, respectively. As can be observed, the WL voltage requires a significant voltage drop610before beginning with a read calibration at the R5read level voltage, which is the lowest of the subset of memory cells of the top page (TP) of a set of QLC-based memory cells. Adjustments to additional read level voltages are performed in sequential order of increasingly greater threshold voltage distributions, e.g., L10, L12, L15. As discussed, this reduction in the WL voltage to a read level voltage associated with the lowest threshold voltage distribution causes performance delays or latencies, e.g., due to the increase in read overhead time (tR) required to wait for the WL voltage to settle down to a target read level voltage for R5.

FIG.7Ais a graph depicting an example read calibration operation in which read level voltage adjustments are sequentially performed on memory cells of a page from a second-highest threshold voltage distribution to a lowest threshold voltage distribution according to an embodiment. In at least one embodiment, if the charge loss of the subset of memory cells (e.g., for the TP) does not satisfy the threshold voltage drop criterion, then the R15read level voltage for the highest voltage distribution (L15) need not be adjusted or further sensed. Satisfying the threshold voltage drop criterion can be understood as at least meeting a threshold change in voltage corresponding to a threshold charge loss or temporal voltage shift. In these embodiments, the control logic can perform a lookup in the lookup table (e.g., Table 2) to determine the read voltage offset for each of the R12, R10, and R5based on the metadata value for the highest threshold voltage distribution (L15). This metadata value can be determined as characterizing the first read level voltage (R15) of the highest threshold voltage distribution (L15) of the subset of memory cells, e.g., based on analyzing results from a dual-strobe operation (seeFIGS.9-11B).

In these embodiments, the control logic can then adjust, based on the metadata value, a second read level voltage for a second-highest threshold voltage distribution of the subset of a group of memory cells, e.g., here, the R12read level voltage. This adjustment can be performed by applying (e.g., adding or subtracting) the read voltage offset for the second read level voltage to the second read level voltage. The control logic can then, to perform an initial calibrated read of the subset of the group of memory cells, cause the adjusted second read level voltage to be applied to a wordline of the plurality of wordlines of the subset of memory cells to read the second-highest threshold voltage distribution. The control logic can carry out these calibrated reads to also the third read level voltage (R10) and the fourth read level voltage (R5) before performing calibrated reads of the third-highest threshold voltage distribution (L10) and the fourth-highest threshold voltage distribution (L5), respectively. In this way, not only is tR time conserved in not adjusting the first read level voltage (of R15), but also in not having to wait for the WL read voltage to drop and settle to a level needed to read/sense the lowest read level voltage, which is R5in this example.

FIG.7Bis a graph depicting an example read calibration operation in which read level voltage adjustments are sequentially performed on memory cells of a page from a highest threshold voltage distribution to a lowest level voltage distribution according to at least one embodiment. In at least one embodiment, if the charge loss of the subset of the group of memory cells (e.g., for the TP) does satisfy the threshold voltage drop criterion (e.g., and is thus a larger charge loss than was determined inFIG.7A), then the control logic first adjusts the R15read level voltage for the highest voltage distribution before causing a sense operation to be performed at the first read level voltage (R15).

More specifically, in these embodiments, when the control logic performs a lookup in the lookup table (e.g., first column of Table 2), the control logic also determines a first read voltage offset for the highest threshold voltage distribution (L15) that maps to the metadata value. The control logic then applies the first read voltage offset to the first read level voltage to generate an adjusted first read level voltage, and causes, to perform an initial calibrated read of the subset of the group of memory cells, the adjusted first read level voltage to be applied to the wordline to read the highest threshold voltage distribution. In this embodiment, once the calibrated read is performed on the highest threshold voltage distribution (L15) of the subset of memory cells, then the control logic performs the additional calibrated reads (including adjustments to corresponding read level voltages) sequentially from a second-highest threshold voltage distribution (L12) to a lowest threshold voltage distribution (L5), as was discussed with reference toFIG.7A. In this way, although not as much tR time is conserved because the R15read level voltage is adjusted and sensed, some tR time is still conserved over the embodiment ofFIG.6by performing the calibrated read operation in reverse order, from the highest threshold voltage distribution to the lowest threshold voltage distribution.

FIGS.8A-8Bare flow diagrams of an example method800of performing a reverse read calibration in conjunction with a read operation performed on a group of memory cells according to various embodiments. The method800can be performed by processing logic that can include hardware (e.g., processing device, circuitry, dedicated logic, programmable logic, microcode, hardware of a device, integrated circuit, etc.), software (e.g., instructions run or executed on a processing device), or a combination thereof. In some embodiments, the method800is performed by the local media controller135(e.g., control logic) ofFIGS.1A-1B, e.g., by the calibration reader137, on a memory array that includes a plurality of memory cells electrically coupled to a plurality of wordlines and a plurality of bitlines. Although shown in a particular sequence or order, unless otherwise specified, the order of the processes can be modified. Thus, the illustrated embodiments should be understood only as examples, and the illustrated processes can be performed in a different order, and some processes can be performed in parallel. Additionally, one or more processes can be omitted in various embodiments. Thus, not all processes are required in every embodiment. Other process flows are possible.

At operation805, a highest threshold voltage distribution of a subset of the group of memory cells is read. More specifically, the processing logic reads a highest threshold voltage distribution (Vt) by sensing a first read level voltage. In the QLC-based memory cells example discussed herein, the highest Vt distribution is the L15Vt distribution for the TP subset of memory cells (but would be the L14Vt distribution for the XP subset of memory cells, the L13Vt distribution for the UP subset of memory cells, and the L11Vt distribution for the LP subset of memory cells). To read the highest Vt distribution, the processing logic can cause a dual-strobe sensing operation to be performed at the first (or highest) read level voltage. Examples of such a dual-strobe sensing operation are discussed with reference toFIGS.10-11B.

At operation810, a metadata value is determined. More specifically, the processing logic determines a metadata value characterizing the first read level voltage of the highest Vt distribution. The metadata value may be determined based on results of a first read strobe of the dual-strobe sensing performed in operation805, for example (seeFIGS.9-11B).

At operation815, a charge loss is analyzed. More specifically, the processing logic determines whether a charge loss of the subset of the group of memory cells satisfies a threshold voltage drop criterion. In some embodiments, the charge loss is determined according to a charge loss characteristic that is measured/determined by the dual-strobe sensing of operation805(seeFIG.9). In some embodiments, the charge loss is separately tracked and can be retrieved from storage or memory of the memory device130. This charge loss characteristic is discussed in more detail with reference toFIG.4andFIGS.5A-5C. In various embodiments, the threshold voltage drop criterion is set to be a threshold voltage change, corresponding to a particular charge loss or temporal voltage shift, such as 75 mV, 100 mV, 150 mV, 175 mV, or the like, where the threshold voltage change is associated with a relatively small time after program (TAP). Accordingly, the threshold voltage drop criterion can be user defined/programmed and satisfying the voltage drop criterion can include the charge loss (or temporal voltage shift) at least reaching (e.g., is greater than or equal to) the threshold voltage change.

In response to the charge loss not satisfying the threshold voltage drop criterion, at operation820, a second read level voltage is adjusted. More specifically, the processing logic adjusts, based on the metadata value, a second read level voltage for a second-highest threshold voltage distribution of the subset of the plurality of memory cells. To perform this adjustment, the processing device can identify, in a lookup table, an entry mapping the metadata value to a corresponding read voltage offset and apply the corresponding read voltage offset to the second read level voltage.

At operation825, a read is performed with the adjusted second read level voltage. More specifically, the processing logic causes, to perform an initial calibrated read of the subset of the group of memory cells, the adjusted second read level voltage to be applied to a wordline (e.g., the selected wordline) of the plurality of wordlines to read the second-highest threshold voltage distribution. Thus, the embodiment that includes operations820and825relate to the embodiment discussed with reference toFIG.7A. The read performed at operation825can include performing a bitline precharge and a single strobe sensing of the wordline using the adjusted second read level voltage to determine a second sensed read voltage value.

At operation830, additional calibrated reads are performed. More specifically, the processing logic optionally repeats operations820and825for any additional Vt distributions in reverse voltage level order. For example, the processing logic can adjust, based on the metadata value, a third read level voltage for a third-highest threshold voltage distribution of the subset of the plurality of memory cells. The processing logic can cause, to perform a second calibrated read of the subset of the group of memory cells, the adjusted third read level voltage to be applied to the wordline (e.g., selected wordline) to read the third-highest threshold voltage distribution. In this embodiment, the second calibrated read is performed sequentially after the first calibrated read. The read performed of the third-highest threshold voltage distribution can include performing a bitline precharge and a single strobe sensing of the wordline using the adjusted third read level voltage to determine a third sensed read voltage value.

Further, the processing logic can adjust, based on the metadata value, a fourth read level voltage for a fourth-highest threshold voltage distribution of the subset of the plurality of memory cells. The processing logic can further cause, to perform a third calibrated read of the subset of the group of memory cells, the adjusted fourth read level voltage to be applied to the wordline to read the fourth-highest threshold voltage distribution. In this embodiment, the third calibrated read is performed sequentially after the second calibrated read. The read performed of the fourth-highest threshold voltage distribution can include performing a bitline precharge and a single strobe sensing of the wordline using the adjusted fourth read level voltage to determine a fourth sensed read voltage value.

With additional reference toFIG.8B, at operation840, a charge loss is compared. More specifically, the processing logic determines, based on a charge loss characteristic of the highest threshold voltage distribution, whether a charge loss of the subset of the memory cells does not satisfy a second threshold voltage drop criterion. In this embodiment, the second threshold voltage drop criterion is smaller than the threshold voltage drop criterion to which the charge loss was compared at operation815, and thus the comparison of operation840is a finer comparison to determine whether the charge loss is statistically close to zero (“0”) or whether some charge loss exists.

In response to the charge loss satisfying the second threshold voltage drop criterion, at operation845, a low read level voltage (LV_low) value is stored. More specifically, the processing logic stores the low read level voltage value with sensed read voltage values for the threshold voltage (Vt) distribution(s) of the page in a secondary data cache (SDC). As will be discussed with reference toFIG.9and Table 3, the LV_low value can be obtained from a primary data cache (PDC), as having been previously stored in the PDC.

In response to the charge loss not satisfying the second threshold voltage drop criterion, at operation850, a target read level voltage (LV_target) value is stored. More specifically, the processing logic stores the target read level voltage with the sensed read voltage values for the respective threshold voltage (Vt) distributions of the page in the SDC. As will be discussed with reference toFIG.9and Table 3, the LV_target value can also be obtained from the primary data cache (PDC).

With renewed reference toFIG.8A, in response to, at operation815, the charge loss satisfying the threshold voltage drop criterion, at operation860, a first read level voltage is adjusted. More specifically, the processing logic adjusts the first read level voltage based on the metadata value.

At operation865, the adjusted first read level voltage is used. More specifically, the processing logic causes, to perform an initial calibrated read of the subset of the group of memory cells, the adjusted first read level voltage to be applied to a wordline of the memory array to read the highest threshold voltage distribution. Thus, the embodiment that includes operations860and865relate to the embodiment discussed with reference toFIG.7B. The read performed at operation865can include performing a bitline precharge and a single strobe sensing of the wordline using the adjusted first read level voltage to determine a first sensed read voltage value.

At operation870, a second read level voltage is adjusted. More specifically, the processing logic adjusts, based on, a second read level voltage for a second-highest threshold voltage distribution of the subset of the plurality of memory cells. To perform this adjustment, the processing device can identify, in a lookup table, an entry mapping the metadata value to a corresponding read voltage offset and apply the corresponding read voltage offset to second read level voltage.

At operation875, a read is performed with the adjusted second read level voltage. More specifically, the processing logic causes, to perform a second calibrated read of the subset of the group of memory cells, the adjusted second read level voltage to be applied to a wordline (e.g., the selected wordline) of the plurality of wordlines to read the second-highest threshold voltage distribution. In this embodiment, the second calibrated read is sequentially performed after the first calibrated read. The read performed at operation875can include performing a bitline precharge and a single strobe sensing of the wordline using the adjusted second read level voltage to determine a second sensed read voltage value.

At operation880, additional calibrated reads are performed. More specifically, the processing logic optionally repeats operations870and875for any additional Vt distributions in reverse voltage level order. For example, the processing logic can adjust, based on the metadata value, a third read level voltage for a third-highest threshold voltage distribution of the subset of the plurality of memory cells. The processing logic can further cause, to perform a third calibrated read of the subset of the group of memory cells, the adjusted third read level voltage to be applied to the wordline (e.g., selected wordline) to read the third-highest threshold voltage distribution. In this embodiment, the third calibrated read is performed sequentially after the second calibrated read. The read performed of the third-highest threshold voltage distribution can include performing a bitline precharge and a single strobe sensing of the wordline using the adjusted third read level voltage to determine a third sensed read voltage value.

Further, the processing logic can adjust, based on the metadata value, a fourth read level voltage for a fourth-highest threshold voltage distribution of the subset of the plurality of memory cells. The processing logic can further cause, to perform a fourth calibrated read of the subset of the group of memory cells, the adjusted fourth read level voltage to be applied to the wordline to read the fourth-highest threshold voltage distribution. In this embodiment, the fourth calibrated read is performed sequentially after the third calibrated read. The read performed of the fourth-highest threshold voltage distribution can include performing a bitline precharge and a single strobe sensing of the wordline using the adjusted fourth read level voltage to determine a fourth sensed read voltage value.

At operation885, the sensed read voltage values are stored. More specifically, the processing logic stores, in the SDC, the first sensed read voltage value for the highest threshold voltage distribution, the second sensed read voltage value for the second-highest threshold voltage distribution, and so forth for any third-highest, fourth-highest, or higher threshold voltage distribution depending on the memory type and the number of Vt distributions exists in the page. These sensed read voltage values can then be employed for subsequent read operations at the page.

FIG.9is a flow diagram of an example method900for performing a dual-strobe sensing operation to determine read levels associated with a highest threshold voltage distribution according to at least one embodiment. The method900can be performed by processing logic that can include hardware (e.g., processing device, circuitry, dedicated logic, programmable logic, microcode, hardware of a device, integrated circuit, etc.), software (e.g., instructions run or executed on a processing device), or a combination thereof. In some embodiments, the method900is performed by the local media controller135(e.g., control logic) ofFIGS.1A-1B, e.g., by the calibration reader137. Although shown in a particular sequence or order, unless otherwise specified, the order of the processes can be modified. Thus, the illustrated embodiments should be understood only as examples, and the illustrated processes can be performed in a different order, and some processes can be performed in parallel. Additionally, one or more processes can be omitted in various embodiments. Thus, not all processes are required in every embodiment. Other process flows are possible.

In at least one embodiment, the operations ofFIG.9are performed in order to carry out operation805ofFIG.8Aand thus involves preliminary operations of a read calibration of a subset of a group of multi-level cells (e.g., MLC, TLC, or QLC-based memory cells).FIG.10is a graph of a number of memory cells versus threshold voltage distribution illustrating waveforms before and after charge loss and identifying a target read level voltage (LV_target) and a low read level voltage (LV_low) that is lower than the target read level voltage according to an embodiment. These LV_target and LV_low read level voltages will be referred to below.

At operation910, a wordline (WL) voltage is set. More specifically, the processing logic causes a WL voltage of a selected wordline to be set to a first read level voltage, e.g., a target read level voltage (LV_target). Also, the processing logic may cause unselected wordlines to be boosted to mitigate read disturb effects on the memory cells connected to the selected wordline.

At operation920, bitlines and page buffers are precharged. More specifically, the processing logic causes bitlines and one or more page buffer nodes (e.g., Tc nodes) to be precharged in preparation for the reverse read calibration operation, which is described in detail with reference toFIGS.8A-8B.

At operation930, a dual-strobe sensing operation is performed. More specifically, the processing logic performs a dual-strobe sensing operation associated with the first read level voltage to sense at the target read level voltage (LV_target) and at the low read level voltage that is lower than the target read level voltage for the highest threshold voltage distribution. As discussed with reference toFIG.5A, the dual-strobe sensing operation can estimate a charge loss between the target read level (LV_target) and the low read level voltage (LV_low) using a charge loss characteristic, which can be tracked and/or estimated based on tracking temporal voltage shift of the group of memory cells from which the subset of the memory cells is derived. Further, the dual-strobe sensing operation can be performed in one of multiple ways, two of which include boost modulation (FIGS.11A-11B) and t-sense modulation.

At operation940, the target read level voltage (LV_target) and the low read level voltage (LV_low) are stored. More specifically, the target read level voltage and the low read level voltage are stored in the a primary data cache (PDC), e.g., for fast retrieval in order to perform additional operations of the overall reverse read calibration operation.

In various embodiments, Table 3 illustrates, for different pages of QLC-based memory cells, how the PDC and the SDC of a page buffer (e.g., the page buffer152) can be employed to store the LV_target, LV_low, and sensed read voltages for the various LP/UP/XP/TP pages, as an example. While PDC4is employed for the LV_target values and PDC3is employed for the LV_low values, different subsections of the PDC can be employed to store these read level voltages in other embodiments. Eventually, the LV_target or the LV_low is optionally stored with the sensed read voltages in the SDC, as applicable per operations845and850ofFIG.8B.

FIG.11Ais an example page buffer1100according to an embodiment. In some embodiments, the page buffer1100is the page buffer152ofFIGS.1A-1B.FIG.11Bis a set of graphs illustrating voltage at a boost node (Boost) and at a sense capacitor (TDC), which illustrates boost modulation as a way to perform dual-strobe sensing, according to an embodiment. The page buffer1100can precharge a bitline voltage and the sense capacitor (TDC), and thus an amount of boost voltage (Vboost) provided at the boost node and to the back plate of the sense capacitor can cause a shift in reference sensing current within one or more memory cells. The Vboost can be modulated in order to cause a corresponding change in the voltage of the sense capacitor (Vtdc), as illustrated inFIG.11B.

In an example of a dual-strobe sensing operation, Vtdc is discharged by the cell current during a development phase. The control logic (e.g., the calibration reader137) can adjust the boost voltage (Vboost) depending on the target sensing level (LV_target). For the LV_low, the sensing cell current (Icell) should be higher so that Vboost is higher during LV_low strobe. In contrast, the Vboost is lower during LV_target strobe because the sensing cell current is smaller for sensing at the LV_target read level voltage. In this way, the memory device can avoid making any WL read level adjustment for sensing the two different voltage levels of the first (e.g., highest) threshold voltage distribution. This saves time and is faster than adjusting the WL voltage of the selected WL.

While not explicitly illustrated, t-sense modulation performs a similar function to that of boost modulation in providing multiple current sensing levels within the page buffer1100(and/or sense amplifier circuit), but in a different way. This t-sense modulation may be performed by adjusting a current sensing level based on an amount of time the sense amplifier circuit of the page buffer1100passes through a sense mode. One of the current sensing levels can be stored in a sense latch while the sense amplifier circuit is allowed to undergo the sense mode for a different period of time, thus generating a different sense current level by which to modulate the reference sensing current for a given memory cell or group of memory cells. By having both sensing current levels available within the sense amplifier circuit, the WL voltage can again be kept constant while different read level voltages are sensed, e.g., to implement the disclosed dual-strobe read operation. One example of t-sense modulation is discussed in U.S. Pat. No. 8,559,226, dated Oct. 15, 2013, which is hereby incorporated by this reference in its entirety.

The example computer system1200includes a processing device1202, a main memory1204(e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM) such as synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM), etc.), a static memory1210(e.g., flash memory, static random access memory (SRAM), etc.), and a data storage system1218, which communicate with each other via a bus1230.

Processing device1202represents one or more general-purpose processing devices such as a microprocessor, a central processing unit, or the like. More particularly, the processing device can be a complex instruction set computing (CISC) microprocessor, reduced instruction set computing (RISC) microprocessor, very long instruction word (VLIW) microprocessor, or a processor implementing other instruction sets, or processors implementing a combination of instruction sets. Processing device1202can also be one or more special-purpose processing devices such as an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), a digital signal processor (DSP), network processor, or the like. The processing device1202is configured to execute instructions1228for performing the operations and steps discussed herein. The computer system1200can further include a network interface device1212to communicate over the network1220.

The data storage system1218can include a machine-readable storage medium1224(also known as a non-transitory computer-readable storage medium) on which is stored one or more sets of instructions1226or software embodying any one or more of the methodologies or functions described herein, including those associated with the calibration reader137. The data storage system1218can further include the local media controller135and the page buffer152that were previously discussed. The instructions1228can also reside, completely or at least partially, within the main memory1204and/or within the processing device1202during execution thereof by the computer system1200, the main memory1204and the processing device1202also constituting machine-readable storage media. The machine-readable storage medium1224, data storage system1218, and/or main memory1204can correspond to the memory sub-system110ofFIG.1A.