A phase-controllable oscillator consists of a capacitance and an apparatus for charging and an apparatus for discharging the capacitance. In addition, feedback is provided for activating the charging and discharging apparatus in dependence on the oscillator signal. An amplifier for amplifying the capacitance voltage can be phase-controlled by providing the amplifier with a control input for adjusting the phase difference between a zero-crossing of an amplifier output signal on the one hand and a reference phase in the oscillator signal on the other hand. In order to maintain the duty cycle, a switching apparatus is provided for reversing the polarity of the control input under the control of the oscillator signal.

BACKGROUND OF THE INVENTION 
This invention relates to an oscillator, comprising a capacitance, charging 
means and discharging means for charging and discharging the capacitance, 
respectively, feedback means for activating the charging means and 
discharging means in dependence on an oscillator signal, and an amplifier 
for amplifying the capacitance voltage. 
An oscillator of this kind is generally known, for example, as a 
multivibrator in the form of two cross-coupled inverter circuits, the 
capacitance being coupled between non-inverting outputs thereof. In order 
to generate two squarewave signals exhibiting a phase shift of 90.degree., 
a differential amplifier is connected across the capacitance. A first 
squarewave signal is available between inverting outputs of the inverter 
circuits, and a second squarewave signal is available on complementary 
outputs of the differential amplifier. A drawback of the known oscillator 
is that between the two squarewave signals a phase difference occurs which 
depends, for example, on the spread in technology-dependent parameters and 
on frequency-selective parasitic effects. These parasitic effects are more 
prominent as the oscillation frequency is higher. 
It is a further drawback of the known oscillator that the phase difference 
is not controllable, for example in order to compensate for said 
disturbing effects. 
SUMMARY OF THE INVENTION 
Therefore, it is an object of the invention to provide an oscillator of the 
kind set forth in which the phase difference is adjustable so that, for 
example, compensation for said disturbing effects is possible. 
To achieve this, an oscillator in accordance with the invention is 
characterized in that the amplifier comprises a control input for 
adjusting the phase difference between a zero-crossing of an amplifier 
output signal on the one hand and a reference phase in the oscillator 
signal on the other hand by means of an offset voltage. The phase 
difference between a zero-crossing of the squarewave signal on the 
differential amplifier output on the one hand and a reference phase in the 
oscillator signal on the other hand can be controlled by adjustment of the 
change-over point of the differential amplifier. 
An embodiment of an oscillator in accordance with the invention is 
characterized in that it comprises switching means for reversing the 
polarity of the offset voltage at the control input under the control of 
the oscillator signal. As a result of the reversal of the polarity of the 
offset voltage, the duty cycle of the squarewave signal on the 
differential amplifier output remains constant. 
A further embodiment of an oscillator in accordance with the invention is 
characterized in that there is provided a control loop which comprises a 
phase difference detector for generating the offset voltage for the 
control input in dependence on the oscillator signal and the amplifier 
output signal. Using the control loop, the phase difference between the 
oscillator signal on the one hand and the amplifier output signal on the 
other hand can be maintained at a predetermined, constant value.

DESCRIPTION OF THE PREFERRED EMBODIMENTS 
FIG. 1 diagrammatically shows a multivibrator circuit in accordance with 
the invention. The multivibrator comprises a first inverter circuit 
consisting of a series connection of a resistance 10, a current channel of 
a transistor 12 and a current source 14, and a second inverter circuit 
which includes a series connection of a resistance 16, a current channel 
of a transistor 18, and a current source 20. The inverting outputs of the 
inverter circuits are cross-wise connected to their inputs. The 
non-inverting outputs 23 and 25 are interconnected via a capacitance 22. A 
differential amplifier 24 is connected across the capacitance 22. In the 
ideal case a sawtooth voltage V.sub.c exists across the capacitance, which 
sawtooth voltage is converted into a squarewave voltage V.sub.2 by the 
amplifier 24, a phase difference of 90.degree. existing between said 
squarewave voltage V.sub.2 and the squarewave voltage V.sub.1 developed 
between the inverting outputs. However, because of the presence of 
disturbing effects, for example in the form of parasitic capacitances 26 
and 28, delays occur in the switching of the transistors. This can be 
understood as follows. By way of example a situation is assumed where the 
transistor 12 is turned on and the transistor 18 is turned off. The 
voltage on the emitter of the transistor 12 increases because the 
transistor 12 applies more current to the capacitance 22 than is drained 
by the current source 14. The voltage on the emitter of the transistor 18 
decreases due to the discharging of the capacitance 22 by the current 
source 20. When the emitter voltage of the transistor 18 has decreased 
below its base voltage so far that the transistor 18 is turned on, said 
discharging ceases. Upon the transition from the turned-off state to the 
turned-on state of the transitor 18, at the same time a transition from 
the turned-on state to the turned-off state of the transistor 12 would 
occur were it not for the fact that the parasitic capacitance 26 still 
retains a charge, thus introducing a delay into the operation. Because of 
this delay there is a period of time, indicative of the magnitude of the 
parasitic capacitance 26, during which both transistors 12 and 18 are 
turned on. The voltages on the nodes 23 and 25 then increase to the same 
extent so that the voltage V.sub.c across the capacitance 22 remains 
substantially constant during said period of time. However, as soon as the 
parasitic capacitance 26 has been discharged so far that the base-emitter 
voltage of the transistor 12 drops below the switching threshold, the 
transistor 12 is turned off so that the voltage V.sub.c changes under the 
influence of the current source 14. FIG. 2A shows this voltage V.sub.c as 
a function of time. Between successive edges of the sawtooth voltage 
V.sub.c there is a period of time during which the capacitance voltage 
remains substantially constant, as described above. 
FIG. 2B shows the output voltage V.sub.1. The transitions in the squarewave 
signal V.sub.1 relate to the instants at which the relevant parasitic 
capacitance 26 or 28 is discharged and the transistor 12 or 18 is turned 
off. The delay effect, therefore, also becomes manifest in the output 
voltage V.sub.1. 
FIG. 2C shows the uncorrected output signal V.sub.2 of the amplifier 24. 
This squarewave signal V.sub.2 exhibits transitions between two logic 
states at the instant at which the capacitance voltage is substantially 
zero, subject to the condition that the offset voltage V.sub.comp of the 
amplifier 24 is zero. The phase relationship between the squarewave signal 
V.sub.1 and the uncorrected output signal V.sub.2 no longer amounts to 
90.degree. because of the delay incurred by the first squarewave signal 
V.sub.1. The deviation from said 90.degree. is denoted by the reference d 
in the drawing. In order to restore the phase difference between the 
transitions from logic low to logic high of the squarewave signals V.sub.1 
and V.sub.2, it would be necessary to delay the output signal V.sub.2 in 
conformity with the deviation d. This is possible by adjusting the 
change-over point of the comparator 24 so that it is no longer equal to 
zero, but to a compensation voltage V.sub.comp (offset) unequal to zero. 
This is denoted in FIG. 2D by way of the output voltage V.sub.2 '. Said 
transitions from logic low to logic high again exhibit a phase difference 
of 90.degree. with respect to one another. A side effect of the adjustment 
of the compensation value consists in that the duty cycle of V.sub.2 ' 
changes because the transition from logic high to logic low in the signal 
V.sub.2 ' occurs prior to the zero-crossing of the capacitance voltage 
V.sub.c. When the negative-going edge in the signal V.sub.2 ' is shifted 
over a distance 2d as shown in FIG. 2E, the signal V.sub.2 " is obtained. 
In order to realize this shift, the compensation voltage V.sub.comp should 
be periodically switched between positive and negative values. 
FIGS. 3, 4 and 5 show some alternative embodiments of differential 
amplifiers which have a controllable change-over point and which are 
suitable for cooperation with a multivibrator of the described type. The 
controllable differential amplifier shown in FIG. 3 comprises a 
differential amplifier transistor pair which includes transistors 30 and 
32. A control electrode of the transistor 30 is connected to a first 
current branch which includes a transistor 34, a resistance 36 and a 
transistor 42. A control electrode of the transistor 32 is connected to a 
second current branch which includes a transistor 38, a resistance 40 and 
a transistor 44. In conjunction with a current source 46 the transistors 
42 and 44 consitute current sources which can be controlled in a mutually 
complementary fashion by the compensation voltage V.sub.comp. The control 
electrodes of the transistors 34 and 38 are connected to the nodes 23 and 
25 in FIG. 1. At the change-over point of this differential amplifier the 
control voltages of the transistors 30 and 32 are equal. In the case of 
unequal currents in the current branches, adjusted by means of the 
compensation voltage V.sub.comp, the voltage drop across the resistances 
36 and 40 (chosen to be identical in the present example) is also 
different. Assuming that the turned-on transistors 34 and 38 then have a 
control voltage of approximately 0.7 V, it follows that the input voltages 
for the transistors 34 and 38 are unequal. Therefore, the change-over 
point occurs for a capacitance voltage unequal to zero. The polarity 
reversal of the compensation voltage V.sub.comp will be described in 
detail hereinafter. 
The controllable differential amplifier shown in FIG. 4 comprises a first 
current branch with a series connection of a load 50, a transistor 52 and 
a transistor 54, and also comprises a second current branch consisting of 
a series connection of a load 56, a transistor 58 and a transistor 60. The 
current branches are fed by a current source 62. The current branches are 
interconnected via a resistance 64 at the area of nodes between the 
transistors in each of the branches. The control electrodes of the 
transistors 52 and 58 are connected to the nodes 23 and 25, i.e. across 
the capacitance 22 (FIG. 1). The control electrode of at least the 
transistor 54 or the transistor 60 constitutes a control input for the 
compensation signal. The outputs of the differential amplifier are formed 
by a node in each branch between the load 50 or the load 56 and the 
transistor 52 or the transistor 58, respectively. 
At the change-over point of this differential amplifier the currents 
through the loads 50 and 56 are equal, subject to the condition that the 
loads are identical. This implies that the base-emitter voltages of the 
transistors 52 and 58 are then equal. The difference between the emitter 
voltages of the transistors 52 and 58 is related to a compensation current 
through the resistance 64. The compensation current is equal to the 
current difference between the currents conducted by the transistor 52 and 
the transistor 54 as well as being equal to the current difference between 
the currents conducted by the transistor 58 and the transistor 60. This 
difference is adjustable by way of a voltage between the control 
electrodes of the transistors 54 and 60. Therefore, the emitter voltages 
of the transistors 52 and 58 being unequal for equal currents through the 
loads 50 and 56, the control voltages of the transistors 52 and 58 must 
also be different at the change-over point. The reversal of the polarity 
of the compensation voltage V.sub.comp will be described in detail 
hereinafter. 
The controllable differential amplifier shown in FIG. 5 comprises a first 
transistor pair 70 and 72 in a differential amplifier configuration, and a 
second transistor pair comprising transisitors 74 and 76 in a differential 
amplifier configuration. Both differential amplifier configurations are 
connected to the same loads 78 and 80 and are fed in a complementary 
fashion by means of a third differential amplifier transistor pair 82 and 
84. The latter transistor pair is fed by a current source 86. The first 
and the second transistor pairs have an asymmetrical construction. In the 
present example the transistors 72 and 76 are twice as large as the 
transistors 70 and 74. The control electrodes of the transistors 70 and 76 
are connected to the node 23 of the capacitance 22; the control electrodes 
of the transistors 72 and 74 are connected to the node 25 of the 
capacitance 22. The transistor pair 82/84 is controlled by means of a 
compensation voltage V.sub.comp whereby the currents feeding the first and 
the second transistor pair are adjusted. The nodes between the resistances 
78 and 80 and the transistor pairs constitute the output of the 
differential amplifier. At the change-over point of this differential 
amplifier the difference between the currents in the first transistor pair 
70 and 72 equals the difference between the currents in the second 
transistor pair 76 and 74. For both transistor pairs this difference can 
be expressed in the same function F where the arguments are the 
capacitance voltage, the total current through the relevant transistor 
pair, and the ratio of the magnitudes of the relevant transistors. Because 
both asymmetrical transistor pairs themselves are driven in a mutually 
opposed manner, a non-trivial solution is obtained for the capacitance 
voltage where the output voltage V.sub.2 is equal to zero below given 
currents through the transistors 82 and 84. 
FIG. 6 shows an example of a multivibrator circuit comprising a control 
loop and switching means for periodically reversing the polarity of the 
compensation voltage V.sub.comp. The reference numerals 10 to 22 
correspond to those of the multivibrator shown in FIG. 1. The reference 
numerals 50 to 62 correspond to those of the amplifier shown in FIG. 4. A 
polarity reversing circuit 90 has been added which, insynchronism with the 
signal V.sub.1, reverses the effect of the transistor pair 54/60. In the 
present example the polarity reversing circuit 90 comprises two mutually 
parallel-connected transistor differential pairs 90a/b and 90c/d which are 
controlled by the signal V.sub.1 in a mutually opposed manner. In order to 
provide amplification and a level shift, buffers 94 and 96 are arranged 
between the multivibrator comprising the components 10 to 20 and the 
polarity reversing circuit 90. The squarewave signal V.sub.1 is applied to 
a phase detector 92. The output signal V.sub.2 of the amplifier comprising 
the components 50 to 62 is also applied to the phase detector 92. The 
phase detector comprises, for example, a multiplier as known, for example 
from "Analysis and Design of Analog Integrated Circuits", Sec. Ed., P. 
Gray and R. Meyer, 1984, p. 603. The phase detector detects the phase 
difference and controls the value of the compensation signal applied to 
the transistor 60 so that the phase difference between the squarewave 
signals V.sub.1 and V.sub.2 is maintained at a predetermined value, for 
example, 90.degree.. 
It is to be noted that the circuits shown by way of example in the 
described Figures comprise bipolar transistors. It will be evident that 
equivalent circuits can be realized by means of unipolar transistors. 
It is also to be noted that a multivibrator delivering a symmetrical output 
signal is described in the foregoing examples. The invention can also be 
realized using an oscillator of the described kind which delivers an 
asymmetrical output signal. The absolute values of the slope of the 
positive-going edge and the negative-going edge are then unequal. The 
reversal of the polarity of the compensation voltage should then be 
accompanied by an appropriate change of the absolute value of the 
compensation voltage.