Semiconductor device having predictable electrical properties

A circuit element of a semiconductor device is provided. The circuit element has an electrical property and is formed by at least two like individual elements, each of said individual elements having an individual electrical property, the individual electrical property of each individual element including an error portion that is substantially statistically uncorrelated with regard to the other individual elements wherein the electrical property is a function of a summation of the individual electrical properties.

FIELD OF INVENTION

This application is a continuation-in-part of U.S. patent application Ser. No. 10/704,586 filed Nov. 12, 2003, now U.S. Pat. No. 7,131,075. The instant invention relates to semiconductor devices having enhanced intrinsic precision properties that allow establishing a characteristic length in the sub- μm region.

In particular, the present invention relates to semiconductor devices and circuit elements thereof having more predictable electrical properties.

BACKGROUND OF THE INVENTION

One of the major goals in modern telecommunication is to achieve ever increasing transmission rates as well as data broadcast speeds, which is intimately coupled with the need of new and advanced technologies providing the necessary tools for accomplishing this quest. The demand for high precision in manufacturing semiconductor devices calls for the development of new manufacture tools and technologies, which is accompanied with a considerable amount of financial efforts. Thus, it would be advantageous to have at hand simple concepts which allow for the production of semiconductor devices with a characteristic length well below the μm region, but which do not require additional operating expenses.

Semiconductor devices and the systems that contain these devices therein are designed to provide a very particular performance and meet a particular design specification. The ability of the device to meet the designed specification relies on the ability of the manufacturing process to fabricate the devices.

For example, a given process is used to manufacture a batch of semiconductor devices. The devices are then tested and graded as per their ability to meet certain criteria. Those that meet the most stringent criteria will command the highest value. The value of the devices will then decrease with a corresponding decrease in their performance. This variable performance is an attribute of most semiconductor processing where predictability of the process is not always as high as is desired.

There is therefore a need for a semiconductor device structure that overcomes the unpredictable nature of fabrication processes and provides for more predictable device properties.

SUMMARY OF THE INVENTION

It is an object of the invention to provide an improved Semiconductor Device Having Predictable Electrical Properties.

According to an aspect of the present invention there is provided a circuit element of a semiconductor device, the circuit element having an electrical property and being formed by at least two like individual elements each of said individual elements having an individual electrical property, the individual electrical property of each individual element including an error portion that is substantially statistically uncorrelated with regard to the other individual elements wherein the electrical property is a function of a summation of the individual electrical properties.

According to another aspect of the present invention there is provided a method of providing a design of a semiconductor device, the method comprising the steps of: providing a design of a circuit for inclusion within the semiconductor device, the circuit including at least one circuit element having an electrical property; forming the circuit element from a concatenation of a plurality of individual circuit elements each having an individual electrical property, the electrical property being a concatenation of the individual electrical properties; and providing an electronic design including the circuit element and having the individual circuit elements arranged such that any errors resulting from the manufacturing thereof are substantially uncorrelated one with another.

According to another aspect of the present invention there is provided a storage medium having instruction data stored therein for when executing by a processor resulting in performance of: providing a design of a circuit for inclusion within the semiconductor device, the circuit including at least one circuit element having an electrical property; forming the circuit element from a concatenation of a plurality of individual circuit elements each having an individual electrical property, the electrical property being a concatenation of the individual electrical properties; and providing an electronic design including the circuit element and having the individual circuit elements arranged such that any errors resulting from the manufacturing thereof being substantially other than correlated one with another.

According to another aspect of the present invention there is provided a semiconductor device comprising: a circuit element having a given value of a characteristic property and comprising: at least two individual elements, each having an individual value for the characteristic value thereof, the individual values including an error portion that is substantially statistically uncorrelated, the individual elements disposed solely for contributing to the values of the characteristic property.

According to another aspect of the present invention there is provided a method of providing a design of a semiconductor device comprising: providing a design of a circuit for inclusion within the semiconductor device, the circuit including a high precision circuit element having a first characteristic value; forming the high precision circuit element from a plurality of individual circuit elements having characteristic values other than the first characteristic value arranged for providing a concatenated circuit element having the first characteristic value; and, providing an electronic design including the concatenated circuit element and having the individual circuit elements arranged for resulting in errors in the manufacturing thereof, the errors being substantially other than correlated one with another.

According to another aspect of the present invention there is provided a storage medium having instruction data stored therein for when executing by a processor resulting in performance of: providing a design of a circuit for inclusion within the semiconductor device, the circuit including a high precision circuit element having a first characteristic value; forming the high precision circuit element from a plurality of individual circuit elements having characteristic values other than the first characteristic value arranged for providing a concatenated circuit element having the first characteristic value; and, providing an electronic design including the concatenated circuit element and having the individual circuit elements arranged for resulting in errors in the manufacturing thereof the errors being substantially other than correlated one with another.

DETAILED DESCRIPTION OF THE EMBODIMENTS

FIG. 1apresents a schematic diagram of a prior art semiconductor device structure100. The device100comprises individual circuit components designated as Q1101and Q2102, where the component101is a resistor and the component102is a capacitor. The components101and102and their arrangement shown inFIG. 1aare simply illustrative. A variety of different elements, such as resistors, capacitors, transistors, diodes, and the like may be elements of the circuit shown inFIG. 1a. The semiconductor device structure100will generally be manufactured using standard semiconductor manufacturing processes. In general, these processes will employ a plurality of deposition, masking and etching steps as will be apparent to one skilled in the art.

Generally, the component101, i.e., Qn, is a resistor that possesses characteristic dimensions, which are, for the resistor, characteristic length Ln, characteristic width Wn, and characteristic height Hn. The characteristic length Lnof the element extends in a direction substantially parallel to the current flow through the element Qn, and direction of characteristic width Wntogether with the direction of characteristic length Lndefine a set of vectors that span a two-dimensional plane perpendicular to the direction of current flow within the element Qn, of the semiconductor device100.

FIG. 1bschematically presents the physical structure of the component102. The component102is a capacitor. As Such it will be apparent to one of skill in the art that the structure of component102will include a dielectric layer103that separates two layers of conductor104and105that are on either side of the dielectric103. The dimensions of these layers will be determined by the required capacitance for the component102. For illustrative purposes the capacitor102has a capacitance of 100 pF (as shown).

Characteristic properties of the capacitor102are governed by the properties of the materials from which it is formed and the physical dimensions of the structures produced from these materials. The capacitance of component102is designated as Θnin Equation (1):

Θn=ɛLn(1)
where ∈ is the dielectric constant of the dielectric layer103and Lnis its thickness, which in turn is the separation between the conductors104and105.

Associated with each characteristic property, including the capacitance of capacitor102, i.e., Θn, is a certain error ΔΘn, defining the variance of the actual value of the characteristic property vs. the value that was designed. Similar to equation (1), the error ΔΘnis expressed as a function of the errors associated with the individual components as shown in Equation (2):
ΔΘn=ƒ(Δ∈, ΔLn)   (2)

In order to achieve a certain and predictable design specification for Θna very tight tolerance for ΔΘnis required. Meeting the error requirements for the designed properties often implies very tight control of the fabrication process or selective grading of manufactured devices with regard to their actual performance.

It will be apparent to one skilled in the art that other circuit elements will have characteristic properties including, but not limited to resistance and inductance, and so forth.

FIG. 2apresents a schematic diagram of a semiconductor circuit200that contains a semiconductor circuit element according to an embodiment of the present invention. The semiconductor device according to the present invention is manufactured using known technologies and in similar fashion as described herein. The semiconductor circuit200comprises a resistor201and a concatenated element Qcforming a capacitor202. The capacitor202comprises ten individual capacitors or individual circuit elements Q0210to Q9219, respectively. Referring toFIG. 2a, these elements are connected in parallel. Other arrangements and other circuit elements are easily envisioned, in which for example the elements Q0210to Q9219are connected in series.

FIG. 2bschematically presents the physical structure of the capacitor202. As such, it will be apparent to one of skill in the art that the structure of component202will include a dielectric layer220that separates two layers of conductor224and226that are on either side of the dielectric220. The dimensions of these layers will be determined by the required capacitance for the capacitor202. For illustrative purposes, the capacitor202ofFIG. 2bhas a capacitance of 100 pF.

InFIG. 2bit is illustrated, for exemplary purposes, that the dielectric220comprises10individual elements, such as element222, each having a capacitance of 10 pF. In this example the overall capacitance is therefore a summation of the capacitances of the ten individual capacitors210to219, respectively.

The principle of the instant invention is now illustrated for a capacitor with capacitance C comprising ten individual capacitors with capacitances C0to C9, respectively, the ten capacitors connected in parallel. A person of skill in the art with ease extends this example to other representative elements as well.

The capacitance C of a capacitor on a semiconductor device is basically expressed by equation (3):

In equation (3), ∈0is the dielectric constant in vacuo, and ∈ra material dependent dielectric constant of the semiconductor device. Assuming that the ten individual capacitors have constant height and constant width, and combining the constant values of W, H, ∈0and ∈rinto a new constant k, one obtains:
C=k·L(4)

Since the ten individual capacitors are connected in parallel, one obtains the following relation between capacitance and individual lengths:

Equation (5) in view of equation (3) suggests that the capacitance C is directly related to the capacitance of the individual capacitors. If the ten individual capacitors are manufactured in a statistically correlated fashion, that is if they are manufactured within the same process, the precision in capacitance ΔC is a sum of the absolute values of fabrication precision:

In equation (6), δ represents an absolute value of a fabrication precision ΔLn. In case that the ten individual capacitors are not manufactured with a same process, their individual errors are truly uncorrelated, and one obtains:

According to the instant invention, the semiconductor device is manufactured in a way that the individual elements constituting a given element Qnare manufactured independently, and are therefore not statistically correlated. Thus, the fabrication precision ΔLnis different for all individual elements, possibly not only in magnitude, but also in sign. This allows for error cancellation resulting in a concatenated element Qcwith a higher precision in its characteristic property than a single element Q having essentially the same value for Θ.

Statistical correlation is avoidable through numerous methods. One of skill in the art will appreciate that differing levels of statistical decorrelation result in improved or reduced benefit of the inventive method disclosed herein.

FIG. 2cschematically presents another embodiment of the physical structure of the capacitor202. InFIG. 2cit is illustrated, for exemplary purposes, that the dielectric layer230comprises10individual elements, such as element232. The individual elements ofFIG. 2chave individual capacitances according to an embodiment of the present invention. Namely, the individual capacitances have individual values that are within a certain error of 10 pF where this error between a particular capacitance and 10 pF is statistically uncorrelated with regard to the error of the other individual elements. As in the case ofFIG. 2b, the overall capacitance of capacitor202ofFIG. 2cis therefore a summation of the capacitances of the ten individual capacitors210to219, respectively.

Table 1 below illustrates some exemplary calculations according to an embodiment of the present invention (i.e., ten individual capacitances) in contrast with an embodiment according to a prior art approach (i.e., one 100 pF capacitor). Using the exemplary capacitance values from the physical structure described above and shown inFIG. 2c, it is readily apparent in Table 1 that the individual capacitances have individual values that are within a certain error of 10 pF where this error between a particular capacitance and 10 pF is statistically uncorrelated with regard to the error of the other individual elements. As in the case ofFIGS. 2band2c, the overall capacitance of the Table 1 capacitor representing an embodiment of the present invention is a summation of the capacitances of the values of the ten individual capacitors.

TABLE 1Exemplary calculations according to an embodiment of the present inventionINDIVIDUALACCUMULATIVEPOTENTIALVALUESQTYERRORERRORERROR{circumflex over ( )}3YIELD INCREASE10015.005RMS10100.501.58316.23%R{circumflex over ( )}3M{circumflex over ( )}39.50.481.1200.107171875000446.48%10.20.510.1326510000009.60.480.11059200000010.40.520.14060800000010.10.510.1287876250009.70.490.1140841250009.90.500.1212873750009.80.490.11764900000010.30.520.13659087500010.50.530.144703125000TOTAL1001.25412500BASIC COMPONENT ERROR = +/-5%

The relationship of the capacitances of the individual elements is further illustrated with regard toFIG. 3a.FIG. 3apresents a schematic for a semiconductor circuit element300according to the present invention wherein the individual elements constituting a given element Qnare specified distinctly and are therefore not statistically correlated. Here, each individual element has a different characteristic value differing from the others by an amount selected to be statistically distinct. For example, as shown, by selecting lengths of the capacitive elements that vary in small amounts but result in capacitances that sum to the overall desired capacitance, a further correlation between individual elements is eliminated. For example, when the capacitances are 10.02, 9.83, 10.08, 10.11 and 9.96, the error within each capacitance value is substantially uncorrelated as the errors relating to process vary due to the small variations in individual capacitor sizes. If the capacitive elements are also manufactured according to a different process—disposed on different layers or manufactured differently—then two types of decorrelation between individual errors result. Increasing the types of decorrelation acts to increase the convolution of error functions resulting in a larger proportion of errors being grouped about the desired value and fewer errors being distant therefrom (convolution of two peaks results in a sharper peak as shown inFIG. 3b).

Referring toFIG. 3b, a graph is shown having two curves. The curve351is a statistical distribution of random error for manufacturing of a single element. When two elements forming a concatenated element are manufactured with statistically uncorrelated processes, the resulting error distribution has a sharper peak thereby reducing the number of resulting concatenated elements falling outside a given accuracy. Though this is the case, the maximum error value resulting from the manufacturing process remains unchanged. Greater number of elements forming the concatenated element and each formed such that the error in the manufacture thereof is uncorrelated with the error within the manufacture of the other elements results in an even sharper peak and therefore in a tighter grouping of the concatenated element about a designated value.

As the level of correlation between individual elements is reduced, the portion of the manufacturing error that is able to cancel with other errors becomes increased for the set of individual elements. Thus, the level or percentage of repeatability in manufacture is enhanced through the present process. The present method allows for a tighter grouping of errors about a near zero error value therefore increasing yield or, for high precision components, manufacturability.

The capacitance of the individual elements may be considered as the total capacitance divided by the number of individual elements offset by a small but significant amount. Statistics may determine significance. The sum of all capacitors inFIG. 2cis the capacitance C, while each individual capacitor is slightly different.

Referring toFIG. 4, a semiconductor device according to the invention is shown wherein the individual elements constituting a given element Qnare specified distinctly and formed within different manufacturing steps. Here, each individual element has a different characteristic value differing from the others by an amount selected to be statistically distinct, for example 10.00, 10.40, and 9.60, and each individual element is disposed on a different layer or formed by a separate process, for example, using different dielectrics. As such, the level of correlation between individual elements is reduced both in dimension and in manufacturing resulting in the portion of the manufacturing error that is uncorrelated becoming increased for the set of individual elements. Conversely, correlated errors typically sum similarly for each additional element. Thus, when error is highly correlated, the resulting peak is similar regardless of the number of elements.

Referring toFIG. 5, a flow diagram of a method according to the invention is shown. A circuit is designed and provided for layout. In the layout process, circuit elements requiring high precision are identified and are then divided into a plurality of individual elements, the-plurality of individual elements having a same characteristic as the identified circuit element requiring-high precision. The individual elements are disposed within the layout in a manner to provide for a statistical decorrelation between manufacturing errors anticipated to occur for each individual element. Preferably, the statistical decorrelation is sufficient to improve the efficiency to or above the required high precision. The layout, is then provided for manufacture and, during manufacture testing is performed to ensure that the increase in parts meeting or exceeding the required high precision is achieved.

It is well known to those of skill in the art that the method ofFIG. 5may be implemented manually or by an automated software process. Further, the process may be implemented during design by the designer or by the software tools used during design. Of course implementing of the method during design in an automated fashion allows for simulation of the design as implemented providing increased testing abilities.

Decorrelation between errors induced in manufacture of individual elements is determinable through experimentation or through reasonable prediction. For example, elements formed by distinct processes, formed on different layers or with different masks, formed of different compositions, having distinct values. etc., typically result in smaller correlation between manufacturing errors therebetween. Of course, this may not always be the case.

Referring toFIG. 6, a flow diagram of a method according to the invention is shown. A circuit is designed and provided for layout. In the layout process, circuit elements requiring high precision are identified and are then divided into a plurality of individual elements, the plurality of individual elements having a same characteristic as the identified circuit clement requiring high precision. The individual elements are disposed within the layout in a manner to provide for a statistical decorrelation between manufacturing errors anticipated to occur for each individual element. Preferably, the statistical decorrelation is sufficient to improve the efficiency to or above the required high precision. The layout is then provided for simulation. Upon completion of the simulation, the design is modified as necessary and then the process is iterated until the design requirements are met. The layout is then provided for manufacture and during manufacture testing is performed to ensure that the increase in parts meeting or exceeding the required high precision is achieved.