TESTING PARITY AND ECC LOGIC USING MBIST

A processing device used for MBIST is provided which comprises a data storage structure configured to store data, data protection circuitry configured to add at least one protection bit to corresponding portions of the data written to the data storage structure, data protection checking circuitry configured to identify one or more errors made by the data protection circuitry and an MBIST controller configured to receive the corresponding portions of data written to the data storage structure and receive at least one indication identifying the one or more errors.

BACKGROUND

Built in self-test (BIST) is a hardware mechanism which allows a device to efficiently test itself and improve its reliability. BIST reduces the cost of self-testing by decreasing test-cycle duration, allowing test patterns to be applied at full memory speeds, and decreasing the reliance on external test equipment. In a microprocessor, BIST is typically run coming out of reset, warm reset, (cold or warm reset), but can also be run periodically. BIST is used in integrated circuits and devices for a wide range of industries (e.g., automobiles, aerospace, medical devices, military equipment) to detect of hard memory faults.

DETAILED DESCRIPTION

Parity is a type of data protection used to detect errors (e.g., n-bit data corruption) which occurs in memory by typically adding a parity bit to a string of binary data (e.g., a byte) stored in RAM and computing the parity (odd parity or even parity) to detect whether a data error has occurred. For example, if a device uses even parity and the total number of occurrences of 1s in the data string is an odd number of occurrences, the bit value of the parity bit added to the string of data is set to 1 to make the number occurrences of 1s an even number of occurrences. If the number of occurrences of 1s is an even number of occurrences, the parity bit value is set to 0. When odd parity is implemented, the coding is reversed (i.e., the parity bit value is set to 0 if the number of occurrences of 1s is odd and the parity bit value is set to 1 if the number of occurrences of 1s is even). No error is detected for an even parity implementation when the number of occurrences of bits having a value of 1 (including the parity bit) add up to an even number of occurrences and an error is detected when the number of occurrences of bits having a value of 1 add up to an odd number of occurrences. No error is detected for an odd parity implementation when the number of occurrences of bits having a value of 1 (including the parity bit) add up to an odd number of occurrences and an error is detected when the number of occurrences of bits having a value of 1 add up to an even number of occurrences.

Error correction code (ECC) is another type of data protection and uses ECC to both detect errors and correct errors before the errors cause data corruption or system crashes. Accordingly, ECC memory is used in many applications which have a low error (data corruption) tolerance. ECC uses multiple parity bits assigned to larger strings of data. Instead of a single parity bit per byte, ECC implements a hamming code which uses a number of additional parity bits to detect and correct errors (e.g., 8 bits of ECC syndrome bits generated for every 64 bits of data or a 7-bit ECC code (e.g., single error correction, double error detection (SEC DED ECC) code)) that is automatically generated for every 32 bits of data. For example, when the 32 bits of data is read out, a second 7-bit code is generated and compared to the original 7-bit code. If the codes match, then no error is detected. But if the codes do not match, depending on a number of check bits or syndrome bits, the device can determine where the error occurred in the data and correct the error (e.g., detect two bit errors and correct a single bit error) by comparing the two 7-bit codes.

Memory built in self-test (MBIST) circuitry is used to test data storage structures (e.g., memory) of a device. An MBIST controller generates, during an MBIST procedure, a sequence of read and write operations (e.g., sequence of read and write test patterns) to different memory cells to test if the cells are operating correctly (e.g., detect faults, such as faults where the logic value of a cell is stuck-at 1 or 0, transition delay faults, coupling or pattern sensitive faults and other memory faults). The data protection circuitry (e.g., parity bits generator and ECC bits generator) in conventional devices tests bits and gates around the memory or latch instances. However, the data protection circuitry of these conventional devices are not part of the MBIST hardware logic. Therefore, errors (e.g., logic faults) of the data protection circuitry can propagate or provide incorrect data if they are not tested for faults.

These conventional devices also do not include hardware to drive patterns of data to test if the data protection circuitry is working correctly. In addition, internal memory arrays are not memory mapped which limits the ability to drive the data patterns. Implementing data patterns via software to test the data protection circuitry are very inefficient because of the time required to execute each test pattern via software.

Features of the present disclosure provide improved methods and devices for data protection testing which integrate the data protection circuitry (e.g., parity generator circuitry) and ECC generator circuitry as part of the MBIST hardware circuitry. Features of the present disclosure expand the scope of MBIST circuitry to provide indications of errors by the data protection circuitry (e.g., errors resulting from adding parity bits or errors resulting from adding ECC bits) for each portion of data written to and read from the data storage structures during testing.

Accordingly, because errors (e.g., logic faults) of the tested data protection circuitry (e.g., checked data protection circuitry) are identified and provided to the MBIST controller (i.e., and not just errors of the tested memory as implemented in conventional devices), the errors of the data protection circuitry and any resulting incorrect data are prevented from propagating during testing.

A processing device used for MBIST is provided which comprises a data storage structure configured to store data, data protection circuitry configured to add at least one protection bit to corresponding portions of the data written to the data storage structure, data protection checking circuitry configured to identify one or more errors made by the data protection circuitry and an MBIST controller configured to receive the corresponding portions of data written to and read from the data storage structure and receive at least one indication identifying the one or more errors.

An MBIST controller used in a processing device, the MBIST controller configured to generate a sequence of read and write operations to different portions of a data storage structure and for each corresponding portion of data written to and read from the data storage structure, control data protection generating circuitry to add a number of protection bits to the corresponding portion of data, receive the number of protection bits and the corresponding portion of data written to and read from the data storage structure and receive at least one indication, from data protection checking circuitry, identifying one or more errors by the data protection generating circuitry for the corresponding portion of data.

A method of data protection testing using an MBIST controller is provided which comprises generating portions of data to be written to a data storage structure and for each portion of data, adding protection bits to the portion of data, writing the portion of data and the protection bits to the data storage structure, identifying one or more errors resulting from adding the protection bits based on the portion of data and the protection bits read from the data storage structure and receiving, by the MBIST controller, at least one indication of the one or more errors.

As described herein, testing data protection circuitry refers to the testing of any circuitry used to detect errors and/or correct errors in data storage structures such as memory, latch arrays and register files. Examples of data protection circuitry include, but are not limited to, a parity generator, a parity checker, an ECC generator and an ECC checker.

As used herein, programs includes any sequence of instructions to be executed using one or more processors to perform procedures or routines (e.g., operations, computations, functions, processes, jobs). As used herein, execution of programmed instructions (e.g., applications, drivers, operating systems or other software) on a processor includes any of a plurality of stages, such as but not limited to fetching, decoding, scheduling for execution, beginning execution and execution of a particular portion (e.g., rendering of video on full screen) of the programmed instructions. Programmed instructions include parameter settings (e.g., hardware parameter settings) and parameters (e.g., hardware parameters) having tunable (i.e., changeable) values used to control operation of hardware.

FIG.1is a block diagram of an exemplary device100in which one or more features of the present disclosure can be implemented. The device100includes, for example, a computer, a gaming device, a handheld device, a set-top box, a television, a mobile phone, or a tablet computer. The device100can also be implemented as part of an embedded system (e.g., as part of an electronic control unit (ECU) that controls one or more of systems or subsystems in a motor vehicle).

As shown inFIG.1, exemplary device100includes a processor102, memory104, a storage106, one or more input devices108, one or more output devices110, an input driver112and an output driver114. It is understood that the device100can include additional components not shown inFIG.1.

Exemplary processor types for processor102include a CPU, a GPU, a CPU and GPU located on the same die, or one or more processor cores, wherein each processor core is a CPU or a GPU. Memory104is, for example, located on the same die as the processor102or located separately from the processor102. Exemplary memory types for memory104include volatile memory, (e.g., random access memory (RAM), dynamic RAM, or a cache) and non-volatile memory (e.g., a hard-disk, motherboard boot read only memory (ROM), and BIOS memory).

The input driver112communicates with the processor102and the input devices108, and permits the processor102to receive input from the input devices108. The output driver114communicates with the processor102and the output devices110, and permits the processor102to send output to the output devices110. It is noted that the input driver112is an optional component (indicated by dashed lines) and that the device100will operate in the same manner if the input driver112is not present.

The output driver114includes an accelerated processing device (APD)116which is coupled to a display device118. The APD116is configured to accept compute commands and graphics rendering commands from processor102, to process those compute and graphics rendering commands, and to provide pixel output to display device118for display. As described in further detail below, the APD116includes one or more parallel processing units configured to perform computations in accordance with a single-instruction-multiple-data (SIMD) paradigm. Although various functionality is described herein as being performed by or in conjunction with the APD116, the functionality described as being performed by the APD116is also performed by other computing devices having similar capabilities that are not driven by a host processor (e.g., processor102) and configured to provide graphical output to a display device118. The functionality described herein is, for example, performed by any processing system that performs processing tasks in accordance with a SIMD paradigm. Alternatively, the functionality described herein is performed by computing systems that do not perform processing tasks in accordance with a SIMD paradigm.

FIG.2is a block diagram illustrating example components of a device200in which one or more features of the disclosure can be implemented. Components shown inFIG.2are, for example, components of a processor, such as a CPU, an accelerated processor (e.g., a GPU), a field programmable gate array (FPGA) processor or another processor.

As shown inFIG.2, the components include MBIST circuitry202, processor cores204, clients206, memory controller208, cache controllers210,218and220, and caches212,214and216.

As shown inFIG.2, components include a plurality of processor cores204. Each processor core204includes a corresponding level 1 cache controller218in communication with a corresponding level 1 cache214and configured to process data using the corresponding level 1 cache214.

As further shown inFIG.2, components also include a level 2 cache controller220in communication with level 2 cache216and configured to process data using level 2 cache216. Cache controller220is also in communication with a next cache level (higher cache level). Any number of N level caches can be used. The next level cache, such as N level cache212(e.g., last level cache) and N level cache controller210can be in communication with and shared by caches of multiple processors, such as for example, caches of a CPU or GPU (not shown), which may be located on the same die, or multiple dies.

Memory controller208is in communication with memory104(e.g., DRAM) and cache controllers220and218. As shown inFIG.2, multiple clients206are in communication with memory controller208. Clients206include, for example, peripheral memories for which the MBIST circuitry can be implemented. For simplified explanation purposes,FIG.2shows three clients206. However, features of the present disclosure can be implemented for testing the ECC and parity of peripheral memories for any number of clients.

The MBIST circuitry202is used to perform data protection testing for a device. The data protection testing includes testing the data storage structures (e.g., memory, latches, registers) for errors. The MBIST circuitry202generates sequences of read and write operations (e.g., sequences of test patterns) to different portions (e.g., array of cells) of one or more data storage structures (e.g., memory) to test whether the different portions of the data storage structures are operating correctly.

The data protection testing also includes testing data protection circuitry (e.g., parity generator logic, parity checker logic or ECC generator logic and ECC checker logic) which are used to detect errors and/or correct errors of the data written to and read from the data storage structures (e.g., memory such as memory104, cache memory212,214and216, latch arrays such as latch array222, memory of peripheral clients206and register files (not shown)). In addition, the MBIST circuitry202generates additional sequences of read and write operations based on feedback information from the data protection checking circuitry (e.g., parity checker logic or ECC checker logic), identifying one or more errors by the data protection checking circuitry (e.g., parity generator logic or ECC checker logic) which are identified by the data protection checking circuitry. Accordingly, because errors (e.g., logic faults) by the data protection circuitry are identified, measures can be taken (e.g., further testing of the data protection circuitry, replacing or fixing the data protection circuitry) to limit or prevent further data protection testing of the device.

A separate MBIST circuitry202can also be in communication with and register files (not shown inFIG.2. As shown inFIG.2, separate MBIST circuitries202are in communication with a different data storage structure (e.g., memory104, cache memory212,214and216, and register files224) of device200to detect and/or correct errors for each corresponding data storage structure of device200. Although not shown inFIG.2, a device can include a single MBIST circuitry in communication with each data storage structure of the device. Additionally, a device can include multiple MBIST circuitries202(not shown inFIG.2) each in communication with one or more (but not each) data storage structures of a device to detect and/or correct errors for the one or more data storage structures.

As described above, the data protection circuitry of the MBIST circuitry202can include logic for detecting errors (e.g., parity logic) of the data structures as well as logic for detecting and correcting errors (e.g., ECC logic).

FIG.3is a block diagram illustrating an example of the MBIST circuitry202shown inFIG.2including MBIST parity circuitry used to detect errors. As shown inFIG.3, the MBIST circuitry202includes MBIST controller302, parity generator306, parity checker308, semi-dynamic flip flops310(hereinafter “flip-flops”) and multiplexor (MUX)312. Each component of the MBIST circuitry202is connected to (i.e., directly or indirectly through one or more other components) memory304, as shown inFIG.3. The MBIST parity circuitry (i.e., parity generator306and parity checker308) shown inFIG.3and the parity bits described with regard toFIG.3is merely an example of MBIST protection circuitry and protection bits used to detect errors during an MBIST procedure.

The example shown inFIG.3includes memory304as an example of a data storage structure. As described above, however, features of the present disclosure can be implemented by testing data protection circuitry used to detect errors and/or correct errors in any type of data storage structure, such as memory, cache memory, latch arrays and register files. Memory304represents an array of memory cells to be tested. The array of memory cells can be part of any portion of memory of a device, such as for example, main memory, cache memory, memory of a CPU, memory of a GPU, and memory of peripheral devices. For example,FIG.7illustrates an example of a two-dimensional array of memory cells having 8 rows of memory cells MCs by 4 columns of memory cells MCs. The number memory cells MCs, as well as the number of rows and columns shown inFIG.7is merely an example.

The flip-flops shown inFIG.3andFIG.4are merely examples of sequential logic elements used to synchronize the logic and bits in the MBIST circuitry202. The locations of the flip-flops shown inFIG.3andFIG.4are also examples of locations. Features of the disclosure can be implemented with any number of sequential logic elements and at different locations than those shown inFIG.3andFIG.4.

MBIST controller302is configured to generate sequences of reads and writes to one or more portions of memory304to test if the memory (e.g., cells of the memory) are operating correctly. For example, as shown inFIG.3, each bit of data (representing portions of data) is input (as write_data) to multiplexor312at a first input (bottom input of the multiplexor312). The bits of data are received from a processor (e.g., one of the processor cores204shown inFIG.2). MBIST controller302also provides input bits of data to a second input (top input of the multiplexor312). MBIST controller302controls the values of bits of data output from the multiplexor to be written to the memory304(i.e., write_data) to be the bits of data received from the processor or the input bits using select bits provided to a select input of the multiplexor312, MBIST controller302also controls the parity bits (i.e., protection bits) generated by parity generator306(as parity bits) and added to each corresponding portion of data (i.e., write_data provided to a first input of the parity generator306) that are written to and read from the memory304. MBIST controller302controls the parity bits (e.g., values of the parity bits) which are added to a corresponding portion of data using the select bits which are also provided to a second input of the parity generator306.

Parity generator306then adds the parity bits based on the select bits provided from the MBIST controller302and the write_data provided from multiplexor312. That is, parity bits are added to each corresponding portion of data, which are written to different arrays of memory cells of memory304in particular patterns (e.g., different arrays of memory cells MCs shown inFIG.7). The parity generator306also includes, for example, row and address decoders used to select cell locations to be accessed and tested in memory304(e.g., locations of memory cells MCs at rows 1-8 and columns 1-4).

Parity checker308receives, as inputs, the parity bits and corresponding data read from memory304(e.g., read_data), generates additional parity bits from the corresponding data read from memory304, and compares the additional parity bits to the parity bits read from memory. Based on the comparison, parity checker308identifies whether an error occurred by the parity generator306(i.e., a parity error resulted from the parity bits added to a corresponding portion of data). Parity checker308then provides an indication (e.g., “1” or “0”) as parity_results to MBIST controller302identifying whether or not an error occurred by the parity generator306.

Each error by the parity generator306is logged (e.g., stored in local memory) by MBIST controller302. In one example, the errors (e.g., logged errors) by the parity generator306are tracked and detection of the tracked errors occurs at the completion of MBIST procedure, indicating either that the number of test patterns generated a target (e.g., threshold) number of correct results (a pass signature and status) or that the number of test patterns did not generate a target (e.g., threshold) number of correct results (fail signature and status). In another example, the MBIST procedure can be terminated during testing in response to a number of errors exceeding an error threshold.

The data that is read from memory (read_data) and the output of the parity checker308(parity_results) are also provided to the processor (e.g., one of the processor cores204shown inFIG.2) which provided the write_data to the multiplexor312.

FIG.4is a block diagram illustrating an example of the MBIST circuitry202shown inFIG.2including MBIST ECC circuitry used to detect and correct errors. The MBIST ECC circuitry (i.e., ECC generator406and ECC checker408) shown inFIG.4and the ECC bits described with regard toFIG.4is merely an example of MBIST protection circuitry and protection bits used to both detect and correct errors during MBIST. Features of the present disclosure can be implemented, however, using other types of MBIST protection circuitry and protection bits used to both detect and correct errors.

As shown inFIG.4, the MBIST circuitry includes ECC generator406(instead of the parity generator306shown inFIG.3) and ECC checker408(instead of the parity checker308shown inFIG.3). The other components (MBIST controller302, memory304, semi-dynamic flip flops310and MUX312) and their functions are the same (or substantially similar) in bothFIGS.3and4. Accordingly, any description of these components and/or functionality deemed as being superfluous (as being previously described above) is omitted with regard toFIG.4.

ECC generator406generates ECC bits based on the input from the MBIST controller302and the output from multiplexor312. MBIST controller302controls the ECC bits (i.e., protection bits) added to each corresponding portion of data written to the memory304and reads the ECC bits and data bits from the memory304.

ECC checker408receives, as inputs, the ECC bits and corresponding data read from memory304, generates additional ECC bits from the corresponding data read from memory304, and compares the additional ECC bits to the ECC bits read from memory. Based on the comparison, ECC checker408identifies whether an error occurred by the ECC generator406(i.e., an ECC error resulted from the ECC bits added to a corresponding portion of data). ECC checker408then provides an indication (e.g., “1” or “0”) as ECC_results to MBIST controller302identifying whether or not an error occurred by the ECC generator406.

Each error by the ECC generator406is logged (e.g., stored in local memory) by MBIST controller302. In one example, the errors (e.g., logged errors) by the ECC generator306are tracked and detection of the tracked errors occurs at the completion of MBIST, indicating either that the number of test patterns generated a target (e.g., threshold) number of correct results (a pass signature and status) or that the number of test patterns did not generate a target (e.g., threshold) number of correct results (fail signature and status). In another example, the MBIST can be terminated during testing in response to a number of errors exceeding an error threshold.

The data that is read from memory (read_data) and the output of the ECC checker408(ECC_results) are also provided to the processor (e.g., one of the processor cores204shown inFIG.2) which provided the write_data to the multiplexor312).

FIG.5is a flow diagram500illustrating an example method of data protection testing using MBIST.

As shown at block502, the method includes generating portions of data to be written to a data storage structure (e.g., memory). For example, MBIST controller302generate sequences of reads and writes to different portions (arrays of cells) to test if the different portions of the data storage structure are operating correctly.

As shown at block504, for each portion of data, protection bits (e.g., parity bits or ECC bits) are added. For example, MBIST controller302controls the number of protection bits added to each corresponding portion of data to be written to the data storage structure.

The portion of data and the protection bits are written to the data storage structure at block506. The portion of data and the protection bits are then read from the data storage structure at block508and provided to both MBIST controller302and the data protection checking circuitry (e.g., parity checker308or ECC checker408).

As shown at block510, one or more errors resulting from adding the protection bits (e.g., parity bits or ECC bits) are identified based on the corresponding portion of data read from the data storage structure (e.g., read_data) and the protection bits that are read from the data storage structure. For example, one or more errors are identified by generating additional protection bits from the portion of data read from the data storage structure, comparing the additional protection bits to the protection bits read from the data storage structure then identifying an error from the comparison (e.g., an error is identified in response to the additional protection bits not matching the protection bits read from memory).

As shown at block512, the errors resulting from adding the protection bits (e.g., parity bits or ECC bits) are provided to the MBIST controller302as parity_results or ECC_results. For example, for each portion of corresponding data written to and read from the data storage structure, one or more identified errors (parity_results or ECC_results) are provided to MBIST controller302.

As shown at block514, the method500includes logging the errors. For example, MBIST controller302logs the errors in local memory. For example, each error (e.g., identified by the parity generator306or ECC generator406) is logged in local memory by MBIST controller302. The tracked (logged) errors can be used at the completion of MBIST, to indicate a pass or fail signature and status, or alternatively, the MBIST can be terminated during testing in response to a number of tracked (logged) errors exceeding an error threshold. In an example, MBIST controller302logs the errors identified during testing of a portion of memory (e.g., a cache levels, a latch array, main memory) and a processor (e.g.,102) globally logs the errors for testing other portions of memory.

FIG.6is a flow diagram600illustrating an example method of performing data protection testing by an MBIST controller.

As shown at block602, the method600includes generating a sequence of read and write operations to different portions of a data storage structure. For example, the MBIST controller302generates the sequences of reads and writes by controlling portions of data (e.g., 64 bits of data per portion, 32 bits of data per portion, or another amount of bits per portion) to be written to and read from different portions (arrays of cells) of a data storage structure (e.g., memory) to test if the different portions of the data storage structure are operating correctly (e.g., different portions of the array of memory cells MCs shown inFIG.7).

As shown at block604, the method600includes controlling data protection generating circuitry to add protection bits to corresponding portion of data. For example, for each portion of data, MBIST controller302controls data protection generating circuitry (e.g., parity generator306shown inFIG.3or ECC generator406shown inFIG.4) to add protection bits (e.g., the parity bits shown inFIG.3or the ECC bits shown inFIG.4).

As shown at block606, the method600includes receiving the protection bits and the corresponding portion of data that are written to and read from the data storage structure. For example, MBIST controller302receives the protection bits (e.g., the parity bits shown inFIG.3or the ECC bits shown inFIG.4) to be written to memory304and the corresponding portion of data (e.g., write data) to be written to memory304. MBIST controller302also receives the protection bits (e.g., the parity bits shown inFIG.3or the ECC bits shown inFIG.4) read from memory304and the corresponding portion of data (e.g., read_data) read from memory304.

As shown at block608, the method600includes receiving an indication identifying one or more errors by the data protection generating circuitry for the corresponding portion of data. For example, for each corresponding portion of data, data protection checking circuitry (e.g., parity checker308shown inFIG.3or ECC checker408inFIG.4) identifies one or more errors resulting from adding the protection bits (e.g., parity bits or ECC bits) based on the corresponding portion of data read from the data storage structure (e.g., read_data) and the protection bits that are read from the data storage structure (e.g., the parity bits shown inFIG.3or the ECC bits shown inFIG.4). One or more errors are identified by, for example, generating additional protection bits from the portion of data read from the data storage structure, comparing the additional protection bits to the protection bits read from the data storage structure then identifying an error from the comparison (e.g., an error is identified in response to the additional protection bits not matching the protection bits read from memory304). The MBIST controller302then receives an indication of the one or more errors (e.g., parity_results shown inFIG.3or ECC_results shown inFIG.4) from the data protection checking circuitry (e.g., parity checker308shown inFIG.3or ECC checker408inFIG.4).

As shown at block610, the method600includes logging the one or more errors. For example, MBIST controller302logs error in local memory. For example, each error (e.g., identified by the parity generator306or ECC generator406) is logged in local memory by MBIST controller302. The tracked (logged) errors can be used at the completion of MBIST, to indicate a pass or fail signature and status, or alternatively, the MBIST can be terminated during testing in response to a number of tracked (logged) errors exceeding an error threshold. In an example, MBIST controller302logs the errors identified during testing of a portion of memory (e.g., a cache levels, a latch array, main memory) and a processor (e.g.,102) globally logs the errors for testing other portions of memory.