Multilayered dual bit memory device with improved write/erase characteristics and method of manufacturing

A dual bit ROM multilayered structure with improved write and erase functions and a method of manufacturing is disclosed. The structure includes a pair of floating gates at the middle or nitride layer to better define the two locations of electrons representing the dual data bits collected in the middle layer.

TECHNICAL FIELD

The present invention relates generally to a dual bit memory devices and more particularly to multilayered memory devices such as ONO (oxide-nitride-oxide) devices, combined with dual gate members to improve write and erase characteristics.

BACKGROUND

As is well known by those skilled in the art, a continuing goal in manufacturing and production of memory devices is increased storage in the minimum area or least amount of silicon. This relentless demand for reduction in size has resulted in various new approaches for building memories. Further, although DRAM or volatile type memories are suitable for many uses, the continuous need for refreshing of this type of memory is simply unacceptable for other uses. There are, of course, non-volatile mass storage memories such as magnetic hard drives, but such devices are much too slow for high-speed computer operations. Thus, high-speed non-volatile memories are in greater and greater demand.

For example, flash memory was developed in 1988 and is programmable, erasable and non-volatile. The basic flash memory cell is an NMOS transistor that has been modified with a “floating” gate. The flash memory cell is programmed by applying a high voltage to the transistor gate or the WL (word line). If a “zero” bit is to be programmed, a high voltage is also applied to the drain by way of the BL (bit line). These voltages excite the electrons such that they push through the thin oxide layer and are trapped on the floating gate. Consequently, the gate carries a negative charge. If the negative charge on the floating gate is above a selected threshold level, the bit stored in the cell is defined as a “zero.” On the other hand, if a low voltage is applied to the drain or BL, the number of electrons on the floating gate does not exceed the threshold level so that the state remains the same or a “one.” Thus, the default state is “one.”

The cell programmed with a “zero” may be erased by applying a high voltage to the gate and leaving the drain or bit line open or floating. Thus, the excess electrons that were trapped on the floating gate now move to the “source” of the transistor, which is typically connected to ground so that the floating gate is again neutral.

To “read” the cell, a high voltage is applied to the gate. If the transistor is turned on, its drain output is pulled low on the bit line and is defined as a “one” using negative logic. If the transistor is not on, its drain is high on the bit line, which is defined as “zero.” The cell threshold voltage for a typical un-programmed or erased single bit cell is less than about 3.1 volts, while a cell programmed with a “zero” has a threshold voltage greater than 5.0 volts. Thus, the floating gate NMOS transistor provides a high-speed non-volatile memory cell.

As the demand increases for larger and larger non-volatile high-speed memories, the typical answer has been to aggressively decrease the geometry or size of a memory chip and simply pack more and more cells in the same area. However, demand and need is increasing faster than can be accommodated by scaling or decreased geometry. Consequently, there have now been developed flash cells that can provide two data bits per cell and effectively double the amount of storage in an array. Flash memory cells that can store 2 bits do so by using 4 different precise voltages to represent the state of the 2 bits. For example, for a “1”, “1” state, the threshold voltage is typically less than 3.0 volts. For a “1”, “0” state, the threshold voltage is typically between about 3.5 volts and 3.8 volts, and for a “0”, “1” state, the threshold voltage is typically between about 4.3 volts and 4.7 volts. Finally, for a “0”, “0” state, the threshold voltage is above about 5.5 volts.

Of course, the manufacturing process for cells having floating gates that can be charged to these precise voltage settings becomes critical. Furthermore, the circuitry for providing the necessary word line, bit line and gate voltages to achieve the necessary threshold electron charges and resulting voltages is also significantly more complicated.

Another recent development that can store 2 data bits in a single memory cell uses an ONO structure. This memory cell is a transistor with an ONO dielectric programmed by channel hot electrons pumped to the “N” or silicon nitride layer of the ONO structure, which acts as the floating gate. The electron charge is trapped in the silicon nitride layer of the drain junction edge of the ONO stack when the charge is pumped to the edge of the silicon nitride gate. Since charge can be pumped and removed at both edges of the silicon nitride gate, each edge can store a data bit that can be programmed and erased. A “read” operation is carried out in a direction opposite to the direction the bit was programmed, and an erase operation occurs as a result of tunnel enhanced hot “holes” injections created by band-to-band tunneling at the drain junction edge and acceleration occurring from the lateral field.

This type ONO memory array consists of bit lines and word lines that are orthogonal to each other and consequently are presently the densest of known flash memories and at present appear to have a greater future potential than other memory types. Unfortunately, the prior art structures now available are often unreliable in the write and erase operations, because of the difficulty of properly locating the erasing charge over the charged site. Therefore, an ONO or other multilayered type dual bit memory cell that demonstrates reliable write and erase operations would be advantageous.

SUMMARY OF THE INVENTION

These and other problems are generally solved or circumvented, and technical advantages are generally achieved, by preferred embodiments of the present invention which discloses a dual bit multilayered memory cell structure (such as ONO) with a reliable write and erase operation and a method of manufacturing such a structure.

The memory cell comprises a substrate defining at least one channel between a pair of buried diffusion areas that may serve as a source and drain. A first or bottom dielectric layer, such as silicon oxide, is formed over the channel region and a data storage layer is formed over the first dielectric layer. The data storage layer comprises a middle dielectric portion, such as for example silicon nitride formed over a center portion of the first or bottom dielectric layer having a first edge and a second edge. First and second floating gates, such as poly silicon portions are located proximate the first and second edges, respectively, of the middle or nitride dielectric. A top or second dielectric layer, such as silicon oxide, is formed over the data storage layer and a gate electrode, such as a poly gate and spacers are then formed to complete the memory cell structure. The first and second floating gates are adjacent the two edges of the middle dielectric or silicon nitride and define the locations of the charged storage at the edge of the middle layer (e.g., silicon nitride), such that the write and erase operations are consistent and repeatable.

An etching step that is highly selective to the top and bottom dielectric layers is used to etch away portions of the middle dielectric layer thereby “pulling back” the middle layer to leave pockets between the top and bottom dielectric layers at the edge of the middle layer. The first and second floating gates, such as for example, poly silicon portions discussed above are formed in these pockets. According to one embodiment, a first poly silicon deposition step is used to fill these pockets to form two poly floating gates at each edge of a nitride dielectric layer. A second poly silicon deposition is then etched to form the transistor gate over the top of the second oxide dielectric. Spacers are then formed at the edge of the gate in a manner well known to those skilled in the art.

DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS

Referring now toFIG. 1, there is shown a simplified illustration of a prior art NROM dual bit “ONO” memory cell having a nitride dielectric floating gate “N” sandwiched between two oxide dielectric layers. As shown, a silicon substrate10defines a channel region12separating buried diffusion areas or source and drain areas14aand14b. An “O” or oxide dielectric layer16, such as silicon oxide, is deposited above the channel region12. An “N” or nitride type dielectric layer18, such as silicon nitride, is deposited over the oxide dielectric layer16. As will be discussed, the nitride dielectric layer18operates as a floating gate to trap electrons when the cell is programmed. A second “O” or oxide dielectric layer20is then deposited over the nitride layer18. A poly gate layer22and spacers24aand24bare then formed to complete the basic structure. As will be appreciated by those skilled in the art, the NROM cell structure allows the storage of two data bits because the two undefined edge areas18aand18bof the nitride dielectric layer18, and more clearly shown inFIG. 1, can each received isolated pumped electrical charges.

FIG. 2Aillustrates a typical layout of an NROM (ONO) dual bit memory cell structure. Those portions of the structure ofFIG. 2Athat are equivalent to the simplified structure ofFIG. 1carry the same reference numbers, and show the straightforward orthogonal arrangement of the WL's (word lines)28a,28band28cand the BL's (bit lines)30aand30b. The dotted line area31shows the outline of a cross-sectional more realistic structural view of the prior art NROM dual bit memory of FIG.1and as shown in FIG.2B. Those elements ofFIG. 2Bthat are equivalent to elements inFIG. 1carry the same reference numbers.

Referring now toFIG. 3, there is a simplified illustration of the dual bit ROM structure of the present invention. Those portions ofFIG. 3that are equivalent to portions ofFIG. 1, also carry the same reference numbers. Therefore, as shown, the structure is similar to the structure ofFIG. 1, except for the storage layer containing a middle dielectric material such as silicon nitride. Therefore, as shown, a data storage layer32comprised of a middle dielectric layer34(e.g., silicon nitride) is formed over an intermediate or central portion of a first or bottom dielectric layer16, such as for example silicon oxide. At this point, the structure is typically subjected to an oxidation process that converts the surfaces at the edges of the middle dielectric layer34to oxide portions38aand38b, such as silicon oxide portions. A pair of floating gates40aand40b(e.g., poly silicon) make up the rest of the data storage layer32.FIG. 3also illustrates how poly gates40aand40bdefine the areas42aand42bwhere the electrons collect that will represent the dual data bits. A top or second dielectric layer20, a structure gate22, such as poly silicon gates and spacers24aand24bare then formed to complete the dual bit memory cell structure ofFIG. 3according to the present invention.

A layout of circuits of the type shown inFIG. 4will have the orthogonal arrangement of the WL's (word lines) and BL's (bit lines) similar to that shown in FIG.2A.FIG. 4also illustrates the location of the small floating gates40aand40bthat define the locations42aand42bwhere the electron charges will be stored. Thus, it is seen that the operation of the structure of the present invention as shown inFIGS. 3 and 4is similar to that of the memory cell devices ofFIGS. 1,2A and2B except that that placement of the dual gates40aand40bprecisely define the locations of the pumped electrons of the two data bits. This precise location of the pumped electrons results in improved reliability for the write/erase operations.

Referring now toFIGS. 5A-5G, there is illustrated the process flow for manufacturing the dual bit memory cell of the present invention. The process figures use reference numbers that represent the same elements discussed above with respect toFIGS. 1,2A,2B,3and4. Therefore, as shown inFIG. 5A, there is a substrate10made of a material such as silicon covered by a first or bottom dielectric layer16, such as silicon oxide. A middle dielectric layer18, such as silicon nitride is then deposited over the bottom or first dielectric16followed by a deposition of a top or second dielectric layer20, such as silicon oxide, as shown. According to one embodiment, the layered structure is then covered by a layer of photoresist that is patterned by photolithography to form the photoresist mask indicated by photoresist portions46a,46band46c. The structure is then subjected to an etch process that removes the top or second layer of dielectric20and the middle dielectric18and stops at the bottom or first layer of dielectric16to produce the structure illustrated in FIG.5B. Buried diffusion or source/drain regions48aand48bconnected to bit lines may then be formed by ion implantation as illustrated by arrow49in FIG.5G. After the ion implantation step, the photoresist portions46a,46band46care removed and the structure is exposed to an RTP (rapid thermal process). The RTP is followed by an etching process, such as wet etching, that readily etches the middle dielectric layer18(e.g., silicon nitride) but is highly selected to the bottom and top or first and second dielectric layers so as to “pull back” the middle layer to form the pocket structure shown in FIG.5D. The “pull back” areas or pockets50a-50fbetween the top and bottom dielectric layers16and20are then, according to an embodiment of the invention, subjected to an ISSG (in situ steam generation) process to convert the exposed surface of the middle or nitride dielectric layer18to form a silicon oxide film. A first layer of poly silicon is then deposited and isotropically etched to produce or form a pair of floating poly side gates52aand52bas shown in FIG.5E. The etched structure with the floating gates52aand52bis then subjected to an oxidation process to form an oxide film54aand54bon the sidewalls of the gate structure54and the isolation oxide indicated at56aand56bin FIG.5F.

A second layer58of poly silicon is then deposited over the structure to form the structure in FIG.5G.

The second poly silicon layer58is then patterned and etched in a manner well known to those skilled in the art to form the poly silicon gate22shown in FIG.3. The structure is then completed by forming sidewall spacers24aand24band the deposition and etching of conductive material to form the word lines28a,28band28cas shown in FIG.4.