Methods and apparatus to improve detection of capacitors implemented for regulators

An apparatus includes a resistor having a resistor terminal. The apparatus includes a capacitor coupled to the resistor terminal. The apparatus includes a transistor having a current terminal and a gate. The gate is coupled to the resistor terminal and coupled to the capacitor. The apparatus includes a comparator having a comparator input and a comparator output. The comparator input is coupled to the current terminal. The apparatus includes a latch having a latch input coupled to the comparator output.

TECHNICAL FIELD

This description relates generally to buffering, and more particularly to methods and apparatus to improve detection of capacitors implemented for regulators.

BACKGROUND

Regulators, such as voltage regulators, receive an unregulated input voltage signal and provide a substantially constant voltage. In other words, the voltage regulator regulates the input signal so that it can be used by other devices (e.g., mobile phones, music players, voltage sensitive devices, computers, etc.). The stabilized output voltage provides less noise and distortion for devices connected to the voltage regulator.

SUMMARY

An apparatus includes a resistor having a resistor terminal. The apparatus includes a capacitor coupled to the terminal. The apparatus includes a transistor having a current terminal and a gate. The gate is coupled to the resistor terminal and coupled to the capacitor. The apparatus includes a comparator having a comparator input and a comparator output. The comparator input is coupled to the current terminal. The apparatus includes a latch having a latch input coupled to the comparator output.

DETAILED DESCRIPTION

The drawings are not necessarily to scale. Generally, the same reference numbers in the drawing(s) and this description refer to the same or like parts. Although the drawings show layers and regions with clean lines and boundaries, some or all of these lines and/or boundaries may be idealized. In reality, the boundaries and/or lines may be unobservable, blended and/or irregular.

Various forms of the term “couple” are used in this description. These terms may cover connections, communications or signal paths that enable a functional relationship consistent with this description. For example, if device A generates a signal to control device B to perform an action, then: (a) in a first example device, A is coupled to device B by direct connection; or (b) in a second example device, A is coupled to device B through intervening component C if intervening component C does not alter the functional relationship between device A and device B, such that device B is controlled by device A via the control signal generated by device A.

In this description, the term “configured to” may encompass being configurable, but it does not require being configurable. Certain features described herein in the context of separate embodiments can also be implemented in combination in a single embodiment. Conversely, various features described herein in the context of a single embodiment can also be implemented in multiple embodiments separately or in any suitable subcombination.

Even if the drawings show operations performed in an example particular order, such operations are not required be performed in the example particular order or in sequential order, and some illustrated operations may be optional. In certain circumstances, multitasking and parallel processing may be advantageous.

A Low Dropout Regulator (LDO) is a voltage regulator that regulates the output voltage even when the supply voltage (e.g., the input voltage) is within a close range to the output voltage. For example, voltage regulators usually require a large voltage drop between the input and output to operate properly. Therefore, voltage regulators generally require a relatively high-voltage input power supply to operate properly. However, an LDO regulator can operate correctly (e.g., regulate the output voltage) even when the input power supply is low-voltage (e.g., within a close range to the output voltage). In some examples, in order to correctly regulate the output voltage and maintain a stable output voltage, the LDO regulator is configured with a frequency compensated feedback loop.

A common approach to frequency compensation in LDO regulator feedback loops is outfitting the LDO regulator with an output capacitor changes occur. Also, the output capacitor is used as a power supply decoupling capacitor to suppress high-frequency noise output by the input power supply. To compensate the frequency of the feedback loop (e.g., to stabilize the feedback loop) and to suppress high-frequency noise provided by the power supply, the LDO regulator output capacitor is designed within a certain range of capacitance. The particular value of capacitance ranges based on load current, headroom available, etc.

In some examples, if an LDO regulator is turned on (e.g., enabled) without the output capacitor or without the correct capacitance of the output capacitor, the LDO regulator output is likely to oscillate with a large voltage swing. For example, if the capacitance of the output capacitor is too small or too large, then the output of the LDO regulator will not be stabilized (e.g., the output voltage will oscillate). An oscillating output can damage the circuitries (e.g., the loads) powered by the LDO regulator and, in some examples, also damage the LDO regulator itself. In other examples, the LDO regulator may not be outfitted with an output capacitor, which causes instability responsive to high load currents, sudden changes in power supply, etc. The output capacitor may be considered “missing” from the LDO regulator output if the output capacitor was never installed, if the output capacitor has been damaged, etc. In such an example, if the LDO regulator is turned on and the output capacitor is “missing,” the LDO regulator output is likely to oscillate. Detecting the absence of a valid capacitor and/or a capacitor in the permitted range avoids system damage, such as in the case of an automotive ECU (Electronic Control Unit). For example, if a regulator self-detects the absence of a valid capacitor or a capacitor out of range, the regulator determines not to power up and instead to assert appropriate safety signals to the ECU microcontroller.

Output capacitor detector circuits are designed to detect if an LDO regulator includes an output capacitor to avoid oscillation at the output of the LDO regulator. The output capacitor detector circuit usually requires a reference voltage, an accurate timer, and a clock signal to accurately detect the output capacitor. The need for a reference voltage implies the need for an additional circuit, such as a bandgap reference, which in turn, requires a stable supply. While such a reference circuit may exist on chip, enabling a reference would result in additional power consumption during detection, which could be avoided with examples described herein. Further, the requirement of a timer or clock signal in a conventional detector circuit prevents the usage of the detector circuit in regulators that do not otherwise have a clock generator on chip, such as an oscillator. This is a limitation for regulators that are powered on before the oscillator on chip (e.g., an “always-on LDO”). The limitation also implies the need for logic sequence and a digital control of the detection. The need for logic and digital control implies that an active digital controller must be powered and available before the regulator is active. Therefore, the requirement of a timer or clock is limiting in general and limiting in low cost applications. The detection of the output capacitor depends on the accuracy of these features (e.g., reference voltage, timer, and clock signal), which are subject to variation throughout the life of the output capacitor detector. In this manner, such output capacitor detector circuits may need to increase complexity and/or area to reduce such variation and hence are more expensive.

In examples described herein, the examples relate to LDO regulators adapted to be coupled to an external output capacitor. In examples described herein, an external output capacitor is external to the die of the LDO regulator. Examples described herein include a capacitor detector circuit to detect whether the external output capacitor exists and/or is properly operating within the specifications of the LDO regulator. The detection of the external output capacitor in examples described herein does not depend on a timer, a clock signal, or a reference voltage.

For example, the capacitor detector circuit includes two charging circuits, where a first charging circuit includes a first resistor (R1) and is coupled to the external output capacitor (Cext) (e.g., the output of the LDO regulator) and the second charging circuit includes a second resistor (R2) coupled to a reference internal capacitor (Cint). The charging circuits of the capacitor detector circuit are used to charge the capacitors (e.g., the external capacitor and the reference capacitor) and compare the relative voltage ramp rate between the two capacitors during charging. In examples described herein, the term “charging” corresponds to applying voltage and current to an electric component, such as a capacitor, so that the electric component stores energy during charging, the voltage across the capacitor increases, generating a voltage ramp. The slope of the voltage ramp indicates how fast the capacitor is charging and, thus, how big or small the capacitor is. For example, the bigger the capacitor, the longer it takes to charge the capacitor. By comparing the voltage ramp rate between the external output capacitor and the reference capacitor, a logic circuit of the capacitor detector circuit determines whether the external output capacitor has been detected or not detected. Therefore, the detection of the external output capacitor depends only on the reference capacitor in the second charging circuit.

In examples described herein, the capacitor detector circuit is activated before the LDO regulator is powered. The capacitor detector circuit provides a detection signal to the controller that is indicative of a status of the external output capacitor. In this manner, the controller can determine if the LDO regulator should be enabled based on the detection signal from the capacitor detector circuit.

FIG.1is a block diagram of an example system100. InFIG.1, the system100includes an example controller102, an example capacitor detector circuit104, an example low dropout (LDO) regulator108, an example input power supply110, and an example load112. In some examples, the system100includes an external capacitor114. The system100is a device that manages power provided to the load112. The device may be a part of any type of computing system and/or non-computing system such as a subsystem of mobile phone, a laptop, a speaker, a television, etc. The system100may include additional parts not illustrated herein.

InFIG.1, the system100includes the controller102to control the enabling of the detector circuit104and the LDO regulator108. The controller102includes a first output terminal116coupled to the LDO regulator108at a first control node118, a second output terminal120coupled to the detector circuit104at a second control node124, and an input terminal126coupled to the detector circuit104at a DETECTION node128. The controller102sends control signals, via the respective output terminals116,120, to enable and/or disable the detector circuit104and the LDO regulator108. In some examples, the controller102is an analog circuit. In other examples, the controller102is a logic circuit, a state machine, and/or any other type of processor/device that can send control signals to the detector circuit104and the LDO regulator108.

InFIG.1, the system100includes the detector circuit104to detect a connection of the external capacitor114. For example, the detector circuit104determines if the external capacitor114is operating properly (e.g., not damaged) and/or if the external capacitor114is disconnected. The detector circuit104includes an input terminal coupled to the output terminal120of the controller102at the second control node124, a PIN terminal132coupled to an output of the LDO regulator108at PIN node134, and an output terminal coupled to the controller102at the DETECTION node128. The detector circuit104is coupled to the controller102for receiving enable and disable signals. In some examples, the detector circuit104turns on and off responsive to control signals (e.g., enable and disable signals) from the controller102. The detector circuit104is described in further detail below in connection withFIG.2.

InFIG.1, the system100includes the LDO regulator108to regulate voltage, supplied by the input power supply110, for use by the load112. For example, the LDO regulator108reduces voltage to a reference level that is useful to drive the load112. In some examples, the LDO regulator108regulates voltage at the output independent of load impedance, input-voltage variations, temperature, and time. The LDO regulator108includes an input terminal that is coupled to the controller102at the first control node118and an output terminal coupled to the load112at the PIN node134. In some examples, the output terminal of the LDO regulator108is coupled to the external capacitor114at the PIN node134.

InFIG.1, the system100includes the input power supply110to supply power to the load112. The input power supply110may be any regulated, switched, and/or battery power supply. The input power supply110may generate supply voltages that are too high for the load112and, thus, would damage the load112. In this manner, the input power supply110is coupled to the LDO regulator108for regulating the high voltages.

InFIG.1, the system100includes the load112to draw power from the input power supply110via the LDO regulator108. The load112includes an input terminal coupled to the output terminal of the LDO regulator at the PIN node134. In some examples, the input terminal of the load112is coupled to the external capacitor114at PIN node134. The load112may be a processor, a transceiver, a microcontroller, and/or any type of circuit performing an action for the system100.

Multiple instances of system100ofFIG.1may be included in an application to regulate power to multiple loads. For example, a laptop includes loads such as speakers, microphones, cameras, calculators, touch screens, displays, keypads, etc. Each of the loads in the computer may include a separate LDO regulator that regulates supply voltage based on the loads' specifications.

In an example operation of the system100, the controller102may be pre-programmed to perform a capacitor detection program at a specific time. For example, the controller102may be configured to execute the capacitor detection program at a time before the load112is powered. In other examples, the controller102obtains a notification from a user of the system100indicative to execute the capacitor detection program. In examples herein, the capacitor detection program is initiated before the regulator108is powered up, because turning on a regulator with a capacitor fault detected on the output node is not desirable.

The controller102, responsive to the timing and/or the notification, generates a first control signal configured to cause the LDO regulator108to enter a high impedance state (e.g., a Hi-Z state). For example, the controller102sends a control signal to the LDO regulator108via the first control node118that causes the LDO regulator108to open a switch between the input power supply110and the output terminal of the LDO regulator108so that the output signal of the LDO regulator108at PIN node134is not determined by the LDO regulator108. The output signal at PIN node134is left open so that the detector circuit104can drive and/or determine the signal at PIN node134.

The controller102, responsive to the LDO regulator108entering the Hi-Z state, initiates the detector circuit104by sending a second control signal to the detector circuit104. The controller102generates the second control signal that is configured to turn on the detector circuit104to begin the process of detecting the external capacitor114.

The detector circuit104detects whether the external capacitor114is connected or disconnected (e.g., present or missing) responsive to the supply voltage. The detector circuit104provides a detection signal, indicative of the status of the external capacitor114(e.g., connected, disconnected, operating within or outside a known range, etc.) to the controller102via the DETECTION node128.

The controller102makes a decision to turn on the LDO regulator108responsive to the detection signal at the DETECTION node128. For example, if the detection signal is indicative that the external capacitor114is connected, the controller102initiates the LDO regulator108. In other examples, if the detection signal is indicative that the external capacitor114is disconnected, the controller102does not initiate the LDO regulator108and may flag the LDO regulator108as not coupled to an external cap and/or notify an operator of the non-operating external capacitor114. For example, if the external capacitor114is not operating, the LDO regulator108and the load112are subject to damage due to voltage oscillation at PIN node134.

FIG.2is a schematic diagram of the detector circuit104ofFIG.1. The detector circuit104ofFIG.2includes an example external capacitor charging circuit202, an example reference charging circuit204, and an example logic circuit206. The external capacitor charging circuit202ofFIG.2includes an example first switch208, an example second switch210, an example first resistor212, an example first transistor214, an example first comparator216, and an example first current source246. The example reference charging circuit204includes an example third switch218, an example fourth switch220, an example second resistor222, an example internal capacitor224(Cint), an example second transistor226, an example second comparator228, and an example second current source248. The logic circuit206includes an example first logic gate230, an example first latch (DFF1)232, an example second latch (DFF2)234, an example second logic gate236, an example third logic gate240, an example delay logic242, and an example third latch (DFF3)244. The detector circuit104ofFIG.2includes an example enabler250.

InFIG.2, the first transistor214and the second transistor226are N-channel metal-oxide-semiconductor field-effect transistors (MOSFETs) (e.g., N-channel silicon MOSFETs, N-channel gallium nitride (GaN) MOSFETs, etc.). Alternatively, the first transistor214and the second transistor226may be implemented by P-channel metal-oxide-semiconductor field-effect transistors (MOSFETs), bipolar junction transistors (BJTs), and/or any other type of transistor by reconfiguring the components of the detector circuit104ofFIG.2.

In the example ofFIG.2, the first switch208, the second switch210, the third switch218, and the fourth switch220are solid state switches. For example, the first switch208, the second switch210, the third switch218, and the fourth switch220may be any type of solid state switches such as transistors, MOSFETs, Insulated Gate Bipolar Transistors (IGBTs), Silicon Controlled Rectifiers (SCRs), Gate Turn-Off Thyristors (GTOs), etc.

In the example ofFIG.2, the first comparator216and the second comparator228are Schmitt triggers. Additionally and/or alternatively, the first comparator216and the second comparator228may be any type of comparator. InFIG.2, the first comparator216is an inverting comparator. In some examples, the first comparator216is an inverting Schmitt trigger.

InFIG.2, the first logic gate230, the second logic gate236, and the third logic gate240are logic gates. In this example ofFIG.2, the first logic gate230and the second logic gate236are inverters (e.g., inverting logic gates, an inverter logic gates, etc.) and the third logic gate240is an OR gate (e.g., an OR logic gate, a logic OR gate, etc.).

InFIG.2, the first latch232, the second latch234, and the third latch244are implemented by D-type flip-flops. Additionally and/or alternatively, the first latch232, the second latch234, and the third latch244may be implemented by set/reset (SR) latches, JK-type flip-flops, T-type flip-flops, and/or any type of basic latch and/or flip-flop.

The external capacitor charging circuit202includes the first resistor212which is coupled to the output of the LDO regulator108and adapted to be coupled to the external capacitor114at PIN node134. The first resistor212and the external capacitor114form a first RC network configured to charge and discharge during detection. The reference charging circuit204includes the second resistor222and the internal capacitor224to form a second RC network configured to charge and discharge during detection.

The enabler250is coupled to the output terminal120of the controller102at the second control node124. The enabler250generates a detection logic sequence responsive to receiving a detection initiation from the controller102. The enabler250provides the detection logic sequence to the first switch208, the second switch210, the third switch218, and the fourth switch220. InFIG.2, the enabler includes four outputs, two of which correspond to a switch (SW) sequence and two of which correspond to a switch not (SW) sequence. The two outputs corresponding to the SW sequence are output to the first switch208and the third switch218. The other two outputs corresponding to theSWsequence are provided to the second switch210and the fourth switch220. In this manner, the first switch208and the third switch218obtain the same logic signal and the second switch210and the fourth switch220obtain the same logic signal, opposite (e.g., inverted) from the SW sequence logic signal.

In the external capacitor charging circuit202, the first switch208includes a first switch terminal and a second switch terminal, the second switch210includes a first switch terminal and a second switch terminal, the first resistor212includes a first terminal and a second terminal, the first transistor214includes a gate terminal, a first current terminal (e.g., drain terminal), and a second current terminal (e.g., source terminal), and the first comparator216includes an input terminal and an output terminal. The first switch terminal of the first switch208is coupled to a supply252at a first node201. The input terminal of the first comparator216is coupled to an output of the current source (Idc1)246at a third node205. The first current source246is coupled to the supply252at the first node201. The second switch terminal of the first switch208is coupled to a first terminal of the first resistor212at a second node203and coupled to the first switch terminal of the second switch210at the second node203. The second terminal of the first resistor212is coupled to the output of the LDO regulator108ofFIG.1at PIN node134. In some examples, the second terminal of the first resistor212is coupled to a first terminal of the external capacitor114ofFIG.1at the PIN node134. The gate terminal of the first transistor214is coupled to the output of the LDO regulator108ofFIG.1at PIN node134and the second terminal of the first resistor212at PIN node134. In some examples, the gate terminal of the first transistor214is coupled to the first terminal of the external capacitor114. The first current terminal of the first transistor214is coupled to the input terminal of the first comparator216at the third node205.

In the reference charging circuit204, the third switch218includes a first switch terminal and a second switch terminal, the fourth switch220includes a first switch terminal and a second switch terminal, the second resistor222includes a first terminal and a second terminal, the internal capacitor224includes a first terminal and a second terminal, and the second transistor226includes a gate terminal, a first current terminal (e.g., drain terminal), and a second current terminal (e.g., source terminal). The first switch terminal of the third switch218is coupled to the supply252at a fourth node207. The input terminal of the second comparator228is coupled to an output of the second current source (Idc2)248at a seventh node213. The second current source248is coupled to the supply252at the fourth node207. The second switch terminal of the third switch218is coupled to the first terminal of the second resistor222at a fifth node209and coupled to the first switch terminal of the fourth switch220at the fifth node209. The second terminal of the second resistor222is coupled to the first terminal of the internal capacitor224at a sixth node211and coupled to the gate terminal of the second transistor226at the sixth node211. The first current terminal of the second transistor226is coupled to the input terminal of the second comparator228at the seventh node213.

The logic circuit206includes the logic gates230,236,240and the latches232,234,244to comparing a speed of the charge and discharge rate of the first RC network in the external capacitor charging circuit202to a speed of the charge and discharge rate of the second RC network in the reference charging circuit204. The logic circuit206includes the third latch244to provide a status of the external capacitor114based on the comparison of the charge and discharge rates of the two RC networks. The status of the external capacitor114is indicative of the connection of the external capacitor114at the output of the LDO regulator108. For example, the status determines whether the external capacitor114is connected to the output of the LDO regulator108or whether the external capacitor114is disconnected and/or operating abnormally.

In the logic circuit206, the first logic gate230includes an input terminal and an output terminal, the first latch232includes a clock input, a data pin input, and an output, the second latch234includes a clock input, a data pin input, and an output, the second logic gate236includes an input terminal and an output terminal, the third logic gate240includes a first input terminal, a second input terminal, and an output terminal, the delay logic242includes an input and an output, and the third latch244includes a clock input, a data pin input, and an output.

In the logic circuit206, the output terminal of the second comparator228is coupled to the input terminal of the first logic gate230at a latchz node215, coupled to the clock input of the second latch234at the latchz node215, and coupled to the delay logic242at the latchz node215. The output terminal of the first logic gate230is coupled to the clock input of the first latch232at a latch node217. The output terminal of the first comparator216is coupled to the data pin of the first latch232at an external capacitor detection (DCEXT) node219and coupled to the data pin of the second latch234at the DCEXT node219. The output terminal of the first latch232is coupled to the input terminal of the second logic gate236at a detection rise (DETRISE) node221. The output terminal of the second logic gate236is coupled to the first input of the third logic gate240. The output terminal of the second latch234is coupled to the second input terminal of the third logic gate240at a detection fall (DETFALL) node223. The output terminal of the third logic gate240is coupled to the data pin of the third latch244at a detection (DET) node225. The delay logic242is coupled to the clock input of the third latch244at a LATCHZ_DLY node227. The output of the third latch244is coupled to the controller102ofFIG.1at the DETECTION node128.

In an example first operation of the detector circuit104, the external capacitor114is present in the system100and operating properly. In the example first operation, the enabler250provides the detection logic sequence that enables the first switch208and the third switch218(e.g., go high, etc.) and disables the second switch210and fourth switch220responsive to a control signal from the controller102. For example, the enabler250initiates and terminates the detection process using a single pulse (e.g., the detection logic sequence). The rising edge of the pulse triggers the signal at the second node203to go high (e.g., SW=logic 1). The falling edge of the pulse triggers the signal at the second node203to go low (e.g., SW=logic 0). When the first switch208and third switch218are closed (e.g., SW=1), the signal at the DETRISE node221is obtained by the third logic gate240. When first switch208and the second switch210are open (e.g., SW=0), the signal at the DETFALL node223is obtained by the third logic gate240. Together, the results of the pulses are combined to obtain the final result at the DETECTION node128. The width of the detection logic sequence (e.g., the SW pulse and theSWpulse) is to enable reliable detection of the presence or absence of the external capacitor114.

In some examples, the first RC network comprising the first resistor212and the external capacitor114begin to charge responsive to the first switch208turning on. The charging of the first RC network generates the first voltage (VG1). The voltage at the external capacitor114ramps up at a rate determined by an RC time constant.

Simultaneously, the second RC network comprising the second resistor222and the internal capacitor224begins to charge responsive to the third switch218turning on. The charging of the second RC network generates the second voltage (VG2). The voltage at the internal capacitor224ramps up at a rate determined by the RC time constant. In some examples, the ramp rate is exponential. In examples herein, the ramp rate of VG2is approximately linear. The internal capacitor224is designed to be a capacitance equal to CEXT/N, where N is greater than 1 so that the capacitance of the internal capacitor224on the integrated circuit (e.g., the integrated circuit being the detector circuit104) is small enough to be fabricated with very low area. The choice of the capacitance of the internal capacitor224is such that for a minimum acceptable value of the external capacitor114, the VG2voltage always rises and falls at a faster rate than the VG1voltage. In some examples, the first resistor212and the second resistor222may be implemented with the same unit resistors to achieve the best matching of the charging or discharging current values in the two resistors.

When the second voltage VG2ramps above a threshold voltage (Vth) of the second transistor226, the second transistor226turns on. The first current terminal (e.g., the drain terminal) of the second transistor226is coupled to a current source (Idc2) and coupled to the input terminal of the second comparator228. Thus, when the second transistor226turns on, responsive to the VG2ramping above the threshold voltage (Vth), the second transistor226sinks the current from the current source (Idc2). When the second transistor226sinks current, the signal at the seventh node213goes low. For example, the signal at the seventh node213goes from high to low responsive to the second transistor226turning on.

In some examples, when the signal at the seventh node213goes low, the signal at the output of the second comparator228also goes low. For example, the signal at latchz node215goes low. In this example, the second comparator228is a Schmitt trigger and removes the noise of the signal at the seventh node213, thus causing the signal at the latchz node215to be a logic high (1) or a logic low (0).

In some examples, when the signal at the latchz node215goes low, the first logic gate230provides a high signal at the latch node217. The first logic gate230inverts the input signal (low) at the output (high). As such, the signal at the latch node217is high responsive to the second transistor226turning on.

In some examples, the first latch232latches the signal at the DCEXT node219when the signal at the latch node217goes high. The clock input of the first latch232is configured to receive the signal at the latch node217. When the input signal to the clock input of the first latch232goes high, the first latch232latches the logic value of the signal at the data pin input, which is configured to receive the signal at the DCEXT node219. The first latch232provides the signal at the DCEXT node219responsive to the signal at the latch node217going high. The latched value of DCEXT node219is presented on first latch output232pin Q, coupled to the signal DETRISE node221.

The signal at the DCEXT node219depends on the ramp rate of the first voltage VG1. The voltage ramp rate of VG1depends on the capacitance of the external capacitor114. In some examples, the size of the external capacitor114is greater than the size of the internal capacitor224multiplied by a resistor ratio of the first and second resistor212,222and, thus, the voltage ramp rate of VG1is slower than the voltage ramp rate of VG2. When the voltage VG1increases above the threshold voltage (Vth) of the first transistor214, the first transistor214turns on.

The first current terminal (e.g., the drain terminal) of the first transistor214is coupled to the output of the first current source (Idc1)246and to the input terminal of the first comparator216at the third node205. The signal at the third node205goes low responsive to the first transistor214turning on.

The first comparator216is an inverting Schmitt trigger that removes the noise of the low signal at the third node205and inverts the input signal at the output to be high.

When VG1ramps slower than VG2, the first latch232latches a logic low (0) signal at DCEXT node219, because the clock input coupled to the LATCHZ node217has a rising edge before the signal at DCEXT node219has changed state from low to high. The signal at DCEXT node219is a logic low until the first transistor214turns on responsive to VG1ramping to a voltage that exceeds the threshold voltage (Vth) of the first transistor214. In such an example, the signal at the DETRISE node221is a logic low, regardless if the signal at the DCEXT node219goes high (1).

The enabler250applies a charging (or ramping up) and discharging (or ramping down) sequence to make the final detection at DETECTION node128. The enabler250is designed to provide a pulse of finite duration to first charge the external capacitor114(e.g., on the rising edge of the detection logic sequence pulse) and subsequently discharge the external capacitor114(e.g., on the falling edge of the detection logic sequence pulse). The detection logic sequence may be a direct controlling signal of the switches208,210,218,220. The length of the pulse provided by the enabler250needs to be greater than the duration it takes for ramping voltage at the sixth node211(e.g., VG2) above threshold voltage (Vth of the second transistor226. In some examples, the length of this pulse may be of the order of100microseconds (e.g., as shown below in connection withFIGS.7and8). In other examples, the length of the pulse may vary depending on the range of external capacitance to be detected reliably. In some examples, the enabler250turns the switches (208,218) on until the second voltage VG2charges up to a supply voltage (e.g., ramps to the supply voltage from supply252). When the pulse goes low, the first switch208and the third switch218are turned off.

The second switch210and the fourth switch220turn on responsive to the first switch208and the third switch218turning off. In some examples, the initial charge of VG2is approximately equal to the charge of the supply voltage from the supply252when the third switch218turns off and the fourth switch220turns on. The fourth switch220turns on and the charge at the sixth node211drops to ground. In this manner, the enabler250discharges the internal capacitor224and, thus, discharges the signal at the sixth node211.

When the second voltage VG2at the sixth node211discharges to ground, the second transistor226begins to turn off. The signal at the seventh node213is a logic high (1) responsive to the second transistor226turning off. For example, the second transistor226discontinues sinking current and, thus, the signal at the seventh node213goes high.

The signal at the latchz node215goes high responsive to the signal at the seventh node213going high. When the signal at the latchz node215is a logic high, the second latch234latches (e.g., locks) the signal at the DCEXT node219. For example, the latchz node215is coupled to the clock input of the second latch234so that when the signal to the clock input goes high, the second latch234latches the signal at the data pin input which is coupled to the signal at the DCEXT node219.

When the signal of the latch node217goes high, the signal at the DCEXT node219depends on the discharge rate of the external capacitor114. For example, when the first switch208is turned off and the second switch210is turned on, the first voltage VG1at PIN node134discharges. However, because the size of the external capacitor114is greater than the size of the internal capacitor224times the resistor ratio, the discharge rate of the first voltage VG1is longer than the discharge rate of the second voltage VG2. Therefore, when the signal at the latchz node215goes high, the signal at the DCEXT node219is still high (e.g., because the first transistor214is still turned on and sinking current). In this manner, the second latch234latches a logic high and provides the logic high at the DETFALL node223.

The third logic gate240obtains the signal at the DETFALL node223. The third logic gate240obtains an inverted signal of the signal at the DETRISE node221. The signal at the DETRISE node221is low (e.g., the first flop-flop232latches the logic low at the DCEXT node219when the first switch208and the third switch218are turned on and the external capacitor114is present) and, thus, the third logic gate240obtains a logic high signal (e.g., via the inverter). In some examples, the third logic gate240provides a logic high at the DET node225. For example, the third logic gate240is an OR gate and provides a logic high when either input signal is a logic high.

In some examples, when the signal at the latchz node215goes high, the delay logic242obtains the logic high and initiates. For example, the delay logic242initiates responsive to a logic high input signal. In such an example, the delay logic242delays providing a logic high at the LATCHZ_DLY node227for a period of time. In some examples, the period to delay is greater than the amount of time it takes for the signal at the DETFALL node223to propagate from the output of the second latch234to the input of the third latch244.

In some examples, when the delay logic242provides the logic high at the LATCHZ_DLY node227, the third latch244latches the signal at the DET node225. For example, the third latch244latches a logic high and provides the logic high signal at the DETECTION node128. In such an example, the third latch244, and/or more generally, the detector circuit104, provides a signal notifying the controller102that the external capacitor114is coupled to the output of the LDO regulator108. The example first operation described above is shown in a first signal plot300ofFIG.3.

In an example second operation of the detector circuit104, the external capacitor114is not included in the system100. For example, the output of the LDO regulator108does not include a capacitor coupled in parallel to the load112. In the example second operation, the first switch208and the third switch218are enabled responsive to the rising edge of the detection logic sequence pulse from the enabler250and the second switch210and fourth switch220are turned off responsive to a falling edge of a detection logic sequence pulse from the enabler250.

In some examples, the first resistor212generates the first voltage (VG1) responsive to the first switch208turning on and the second switch210turning off. Because the external capacitor114is not included in the system100, VG1increases to the supply voltage almost (e.g., approximately) immediately. For example, the first voltage (VG1) increases to the supply voltage at nearly the same time the first switch208turns on due to the missing external capacitor114.

Simultaneously, the second RC network comprising the second resistor222and the internal capacitor224begins to charge responsive to the third switch218turning on and the fourth switch220turning off. The charging of the second RC network generates the second voltage (VG2). The second voltage VG2ramps up at a slower rate than VG1because external capacitor114is not present.

The first transistor214turns on responsive to the first voltage (VG1) exceeding the threshold voltage (Vth) of the first transistor214. In such an example, the signal at the third node205equals a logic low responsive to the first transistor214turning on. When the signal at the third node205goes low, the first comparator216provides a logic high at the DCEXT node219.

The second transistor226turns on responsive to the second voltage (VG2) exceeding the threshold voltage (Vth) of the second transistor226. The signal at the seventh node213is a logic high (1) until the second transistor226turns on. The signal at the seventh node213goes low when the second transistor226turns on.

In the example second operation, the first transistor214turns on before the second transistor226because the first resistor212generates the threshold voltage (Vth) of the first transistor214faster than the second RC network, comprising the second resistor222and the internal capacitor224, generates the threshold voltage (Vth) of the second transistor226. In this manner, the signal at the third node205goes low before the signal at the seventh node213goes low. Therefore, when the signal at the DCEXT node219goes high, the signal at the latchz node215is still logic low.

In some examples, when the second transistor226turns on, the signal at the seventh node213goes low. The second comparator228obtains the low signal and provides the low signal at the latchz node215. The first logic gate230inverts the signal at the latchz node215and provides the inverted signal at the latch node217. The signal at the latch node217is a logic high responsive to the second comparator228providing the logic low.

When the signal at the latch node217goes high, the first latch232obtains the logic high at the clock input and latches the signal input to the data pin (e.g., the signal at the DCEXT node219). In the example second operation the first latch232locks the logic high signal at the DCEXT node219, since the DCEXT node219transitioned to logic high before latch node217, and, thus, provides a logic high signal at the DETRISE node221. The second logic gate236inverts the logic high signal at the DETRISE node221and provides a logic low signal to the first input terminal of the third logic gate240.

The enabler250disables the first switch208and the third switch218. The second switch210and the fourth switch220turn on responsive to the first switch208and the third switch218turning off. Prior to the enabler250swapping the logic states of the second switch210and the fourth switch220, and the first switch208and the third switch218, the first voltage (VG1) and the second voltage (VG2) are approximately equal to the supply voltage. This is ensured by constructing the width of the SW sequence pulse appropriately. Thus, when the first switch208is turned off and second switch210is turned on, the voltage at the PIN node134discharges to ground. Also, when the third switch218is turned off and the fourth switch220is turned on, the voltage at the sixth node211will be discharged to ground. In the second operation, the voltage at the PIN node134and, thus, the first voltage (VG1) discharges approximately instantaneously responsive to the first switch208turning off because the external capacitor114is not present Therefore, the first voltage (VG1) discharges faster than the second voltage (VG2).

In some examples, the first transistor214turns off when the first voltage (VG1) discharges below the threshold voltage of the first transistor214. The signal at the third node205goes high responsive to the first transistor214turning off. The first comparator216obtains the input logic high signal at the third node205and provides an inverted version of the signal at the third node205. For example, the first comparator216provides a logic low signal to the data pin input of the first latch232via the DCEXT node219. The first latch232does not latch the logic low signal at the data pin input because the clock input (e.g., the signal at the latch node217) is high (e.g., the clock input did not receive a rising edge signal that enables the latching of the data at the data pin). In this manner, the signal at the DETRISE node221is the logic high (1) and the second logic gate236provides the logic low (0) (e.g., inverts the logic high (1) from the DETRISE node221at the output) to the first input terminal of the third logic gate240.

In some examples, the second transistor226turns off when the second voltage (VG2) discharges below the threshold voltage of the second transistor226. In some examples, the second transistor226turns off after the first transistor214turns off in the second operation. The signal at the seventh node213goes high responsive to the second transistor226turning off. The second comparator228provides a logic high signal to the first logic gate230, to the clock input of the second latch234, and to the delay logic242. For example, the signal at the latchz node215goes high responsive to the second transistor226turning off.

In some examples, the second latch234latches the signal at the data pin (e.g., the signal at the DCEXT node219) responsive to the signal at the latchz node215going high. In this example, the second latch234latches a logic low (0) and provides the logic low to the DETFALL node223. For example, the second latch234latches the signal at the DCEXT node219which is low because the first transistor214turns off before the second transistor226turns off.

The third logic gate240obtains the low signal at the DETFALL node223. The third logic gate240obtains an inverted signal of the signal at the DETRISE node221. The signal at the DETRISE node221is high (e.g., the first flop-flop232latches the logic high at the DCEXT node219when the first switch208and the third switch218are turned on and the external capacitor114is not present) and, thus, the third logic gate240obtains a logic low signal (e.g., via the second logic gate236). The third logic gate240provides a logic low at the DET node225because the signal at the DETRISE node221is high and the signal at the DETFALL node223is low.

In some examples, when the signal at the latchz node215goes high, the delay logic242obtains the logic high and initiates. For example, the delay logic242initiates responsive to a logic high input signal. In such an example, the delay logic242delays providing a logic high at the LATCHZ_DLY node227for a period of time. In some examples, the period to delay is greater than the amount of time it takes for the signal at the DETFALL node223to propagate from the output of the second latch234to the input of the third latch244.

In some examples, when the delay logic242provides the logic high at the LATCHZ_DLY node227, the third latch244latches the signal at the DET node225. For example, the third latch244latches a logic low and provides the logic low signal at the DETECTION node128. In such an example, the third latch244, and/or more generally, the detector circuit104, provides a signal notifying the controller102that the external capacitor114is not coupled to the output of the LDO regulator108and/or is not operating properly at the output of the LDO regulator108. The example second operation described above is shown in the second signal plot400ofFIG.4.

In some examples, the external capacitor114, when included in the system100and operating within specifications, includes an initial charge. For example, the external capacitor114stores charge for a given voltage that may be provided by the load112and/or the LDO regulator108when the system100is in a down state (e.g., turned off or in a low Q state). The detector circuit104detects the external capacitor114regardless if the external capacitor114includes an initial charge or not. For example, in the first operation it is assumed that the external capacitor114does not include an initial charge (e.g., the charge stored in the external capacitor114is zero). However, in an imperfect scenario, the external capacitor114may include an initial charge.

In an example third operation, the external capacitor114is present in the system100and includes an initial charge that is less than the threshold voltage of the first transistor214. In the example third operation, the external capacitor114is physically large and takes a long amount of time to charge relative to a physically smaller capacitor (e.g., such as the internal capacitor224).

In the example third operation, the enabler250turns on the first switch208and the third switch218and turns off the second switch210and the fourth switch220. The first RC network comprising the first resistor212and the external capacitor114generate the first voltage (VG1) responsive to the first switch208turning on and the second switch210turning off. The voltage at the external capacitor114(VG1) ramps up at a rate determined by the R1Cexttime constant, where Cextincludes an initial charge. The first voltage VG1ramps up from the initial charge of the external capacitor114.

Simultaneously, the second RC network comprising the second resistor222and the internal capacitor224begins to charge responsive to the third switch218turning on and the fourth switch220turning off. The charging of the second RC network generates the second voltage (VG2).

When the second voltage VG2ramps above the threshold voltage (Vth) of the second transistor226, the second transistor226turns on. The first current terminal (e.g., the drain terminal) of the second transistor226is coupled to the second current source (Idc2)248and coupled to the input terminal of the second comparator228. Thus, when the second transistor226turns on, responsive to the VG2ramping above the threshold voltage (Vth), the signal at the seventh node213goes low.

In some examples, when the signal at the seventh node213goes low, the signal at the output of the second comparator228also goes low. For example, the signal at latchz node215goes low. The first logic gate230provides a high signal at the latch node217responsive to the signal at the latchz node215going low. In some examples, the first latch232latches the signal at the DCEXT node219when the signal at the latch node217goes high. For example, the clock input of the first latch232is configured to receive the signal at the latch node217. When the input signal to the clock input of the first latch232goes high, the first latch232latches (e.g., locks) the signal at the data pin input (e.g., the signal at the DCEXT node219). For example, the first latch232provides the signal at the DCEXT node219responsive to the signal at the latch node217going high.

The signal at the DCEXT node219depends on the ramp rate of the first voltage VG1. In some examples, even though there is an initial charge of the external capacitor114, the ramp rate of VG1is slower than the ramp rate of VG2and VG1may not have enough time to ramp above the threshold voltage (Vth) of transistor214, thus, the output of the first comparator216is logic low (e.g., the first transistor214is not turned on and the signal at the third node205is high) when the signal at the latch node217goes high. In this example, the first latch232latches the logic low signal and provides the logic low signal to the DETRISE node221.

In some examples, the enabler250turns off the first switch208and the third switch218after a time period (e.g., the length of the detection logic sequence pulse).

The second switch210and the fourth switch220turn on responsive to the first switch208and the third switch218turning off. The initial voltage of VG2is approximately equal to the supply voltage when the third switch218turns off. In this example, when the third switch218is turned off, the enabler250turns the fourth switch220on. The fourth switch220turns on and the charge at the sixth node211drops to ground.

When the second voltage VG2at the sixth node211discharges to ground, the second transistor226begins to turn off. For example, when the second voltage VG2drops below the threshold voltage (Vth) of the second transistor226, the second transistor226turns off. The signal at the seventh node213is a logic high (1) responsive to the second transistor226turning off.

The signal at the latchz node215goes high responsive to the signal at the seventh node213going high. When the signal at the latchz node215is a logic high, the second latch234latches (e.g., locks) the signal at the DCEXT node219. For example, the latchz node215is coupled to the clock input of the second latch234so that when the signal to the clock input goes high, the second latch234latches the signal at the data pin input (e.g., the signal at the DCEXT node219).

When the signal of the latch node217goes high, the signal at the DCEXT node219depends on the discharge rate of the external capacitor114. In some examples, the first transistor214does not turn on before the first switch208is turned off. For example, the VG1ramp rate may be too slow to meet the threshold voltage of the first transistor214during the high pulse provided by the controller102. Therefore, the first transistor214does not turn on during the third operation. When the signal at the latchz node215goes high, the signal at the DCEXT node219is still low (e.g., because the first transistor214is still turned off). In this manner, the second latch234latches a logic low and provides the logic low at the DETFALL node223.

The third logic gate240obtains the low signal at the DETFALL node223. The third logic gate240obtains an inverted signal of the signal at the DETRISE node221. The signal at the DETRISE node221is low (e.g., the first flop-flop232latches the logic low at the DCEXT node219when the first switch208and the third switch218are turned on and the external capacitor114is present) and, thus, the third logic gate240obtains a logic high signal (e.g., via the inverter). In some examples, the third logic gate240provides a logic high at the DET node225.

In some examples, when the signal at the latchz node215goes high, the delay logic242obtains the logic high and initiates. For example, the delay logic242initiates responsive to a logic high input signal. In such an example, the delay logic242delays providing a logic high at the LATCHZ_DLY node227for a period of time. In some examples, the period to delay is greater than the amount of time it takes for the signal at the DETFALL node223to propagate from the output of the second latch234to the input of the third latch244.

In some examples, when the delay logic242provides the logic high at the LATCHZ_DLY node227, the third latch244latches the signal at the DET node225. For example, the third latch244latches a logic high and provides the logic high signal at the DETECTION node128. In such an example, the third latch244, and/or more generally, the detector circuit104, provides a signal notifying the controller102that the external capacitor114is coupled to the output of the LDO regulator108. The example third operation described above is shown in a third signal plot500ofFIG.5.

In an example fourth operation, the external capacitor114is present in the system100and includes an initial charge that is greater than the threshold voltage of the first transistor214. In the example third operation, the external capacitor114is physically large and takes a long amount of time to charge relative to a physically smaller capacitor (e.g., such as the internal capacitor224).

In the example fourth operation, the first transistor214is on before the first switch208is turned on because the initial charge of the external capacitor114is greater than the threshold voltage of the first transistor214. The enabler250provides the SW sequence and theSWsequence, which is configured to turn on the first switch208and the third switch218and turn off the second switch210and the fourth switch220. The charge at the PIN node134(e.g., the first voltage VG1) continues to ramp up to the supply252responsive to the first switch208turning on. The signal at the third node205is low before and during the charging of the signal at the PIN node134because the first transistor214is turned on. The first comparator216provides a logic high at the DCEXT node219.

In this manner, when the second transistor226turns on, the first latch232latches the high signal at the DCEXT node219. For example, the first logic gate230provides a high signal responsive to the second comparator228providing a logic low at the latchz node215, causing the clock input of the first latch232to go high and latch the signal at the data pin. The first latch232provides a logic high at the DETRISE node221.

During a discharge phase of the detector circuit104(e.g., the phase that occurs when the enabler250turns off the first switch208and the third switch218and turns on the second switch210and the fourth switch220), the second transistor226turns off before the first transistor214because the discharge rate of VG2is faster than the discharge rate of VG1due to the size of the external capacitor114. In this manner, the second comparator228provides a logic high at the latchz node215when the second transistor226turns off.

The second latch234obtains the logic high from the second comparator228(e.g., via the latchz node215) at the clock input. The second latch234latches the signal at the DCEXT node219responsive to the high signal at the clock input. In the example fourth operation, the signal at the DCEXT node219is high when the second transistor226turns off because the first voltage (VG1) is still above the threshold voltage of the first transistor214. Therefore, the second latch234latches the high signal at the DCEXT node219and provides the high signal to the third logic gate240via the DETFALL node223.

The signal at the DETRISE node221is high and the signal at the DETFALL node223is high. The third logic gate240obtains an inverted version of the signal at the DETRISE node221(e.g., a logic low) at the first input terminal and obtains the signal at DETFALL node223(e.g., a logic high) at the second input terminal. The third logic gate240provides a logic high to the data pin of the third latch244via the DET node225responsive to the high input signal at the second input terminal (e.g., the high signal at the DETFALL node223).

Also, the delay logic242provides a high signal to the LATCHZ_DLY node227responsive to the delay period ending. For example, the input of the delay logic242obtains the high signal at the latchz node215, delays for a time period, then provides a logic high signal to the clock input of the third latch244. The third latch244latches the signal at the data pin (e.g., the logic high signal at the DET node225) responsive to obtaining the logic high signal from the delay logic242. In such an example, the third latch244, and/or more generally, the detector circuit104, provides a signal notifying the controller102that the external capacitor114is coupled to the output of the LDO regulator108. The example fourth operation described above is shown in a fourth signal plot600ofFIG.6.

For example, at the output of the LDO regulator108, there may be a parasitic capacitance formed by the printed circuit board (PCB) and/or by the device containing the system100. In this manner, the target size of the external capacitor114has to be greater than the largest parasitic capacitance. The largest parasitic capacitance can be determined by the PCB and/or by the device containing the system100. The target size of the external capacitor114is selected to be greater than this parasitic capacitance.

In some examples, the target size of the external capacitor114can be determined using the capacitance of the internal capacitor224and the resistances of the first resistor212and the second resistor222. For example, the target size of the external capacitor114can be determined using Equation 1 below.

In Equation 1 above, the internal capacitor224multiplied by the resistor ratio between the first resistor (R1)212and the second resistor (R2)222to determine the target size of the external capacitor114. The ratio of the first resistor212and the second resistor222is selected based on the size of the internal capacitor224. For example, if the largest parasitic capacitance of the output of the LDO regulator108is C, and the size of the internal capacitor224is Cint, then the ratio M between the first resistor212and second resistor222is C divided by Cint. Therefore, the variation of the target size of the external capacitor114only depends on the variation of the internal capacitor224.

The resistance of the second resistor222is greater than the resistance of the first resistor212to generate an appropriate voltage ramp rate at the sixth node211when the external capacitor114is present. In some examples, the detector circuit104may be configured to generate the voltage ramps at the PIN node134and the sixth node211based on current and capacitance. However, using resistors (212,222) to generate the voltage ramps provides significant benefits in terms of area and matching.

Advantageously, the logic circuit206of the detector circuit104generates the detection signal based on the comparison between the voltage ramp rate generated by the external capacitor114in the external capacitor charging circuit202and the voltage ramp rate generated by the internal capacitor224in the reference charging circuit204. Only a single pulse controlling the switches is required to generate the voltage ramps, as long as the detection logic sequence pulse provides a time longer than it takes to charge and discharge the internal capacitor224. A continuous clock signal is not required. Therefore, the accuracy of the detector circuit104does not rely on a reference voltage, a clock signal, and/or an accurate timer but merely relies on the variation of the internal capacitor224.

FIGS.3-6are the example first signal plot300, the example second signal plot400, the example third signal plot500, and the example fourth signal plot600.FIG.3is the example first signal plot300illustrating a response of the elements of the example detector circuit104ofFIG.2during the first operation when the external capacitor114is present.FIG.4is the example second signal plot400which is a signal plot illustrating a response of the elements of the example detector circuit104ofFIG.2during the second operation when the external capacitor114is not present.FIG.5is the example third signal plot500which is a signal plot illustrating a response of the elements of the example detector circuit104ofFIG.2during the third operation when the external capacitor114is present and includes an initial charge less than the threshold voltage of the first transistor214.FIG.6is the example fourth signal plot600which is a signal plot illustrating a response of the elements of the example detector circuit104ofFIG.2during the fourth operation when the external capacitor114is present and includes an initial charge that is greater than the threshold voltage of the first transistor214.

Referring toFIG.3, the first signal plot300illustrates the signals at nodes in the detector circuit104. In the first plot300, the SW sequence, provided by the enabler250, goes high at time t1302. For example, the enabler250generates the SW sequence signal configured to turn on the first switch208and the third switch218and generates theSWsequence signal configured to turn off the second switch210and the fourth switch220. The signal at the sixth node211(e.g., the second voltage VG2) begins to increase at a ramp rate, responsive to the signal at the SW sequence going high, at time t1302. For example, the second resistor222and the internal capacitor224charge the signal at the sixth node211to generate second voltage (VG2). The signal at the PIN node134(e.g., the first voltage VG1) begins to increase at a ramp rate, responsive to the SW sequence going high, at time t1302.

The signal at the sixth node211meets the threshold voltage of the second transistor226at time t2304. For example, the second resistor222and the internal capacitor224generate the threshold voltage (Vth) of the second transistor226between time t1302and time t2304. The signal at the latch node217goes high responsive to the signal at the sixth node211meeting the threshold voltage (Vth) of the second transistor226at time t2304. For example, the second transistor226turns on, causing the input signal to the second comparator228(e.g., the signal at the seventh node213) to go low. The second comparator228provides a logic low at the latchz node215causing the first logic gate230to invert the logic low and provides a logic high at the latch node217.

The signal at the PIN node134(e.g., VG1) increases slower than the signal at the sixth node211(VG2) and, thus, VG1is does not meet or exceed the threshold voltage (Vth) of the first transistor214at time t2304. Therefore, the first latch232latches the logic low provided by the first comparator216and provides the logic low at the DETRISE node221at time t2304.

The enabler250provides a falling edge of the SW sequence to the first switch208and the third switch218at time t3306, and a rising edge of the SW sequence to the second switch210and the fourth switch220at time t3306. For example, the enabler250turns off the first switch208and the third switch218at time t3306and turns on the second switch210and the fourth switch220at time t3306. The signal at the sixth node211begins to decrease at a ramp rate at time t3306. For example, VG2discharges responsive to the third switch218turning off and fourth switch220turning on. Also, the signal at the PIN node134begins to decrease at a ramp rate at time t3306. For example, VG1discharges responsive to the first switch208turning off and the second switch210turning on.

The fourth switch220, the second resistor222, and the internal capacitor224discharge the signal at the sixth node211below the threshold voltage (Vth) of the second transistor226at time t4308. For example, VG2falls below the threshold voltage of the second transistor226at time t4308. The signal at the latch node217goes low at time t4308responsive to VG2falling below Vth of the second transistor226. For example, the second transistor226turns off responsive to not having a high enough input at the gate terminal which causes the input to the second comparator228to go high (e.g., the signal at the seventh node213to be a high signal). The second comparator228provides the logic high to the latchz node215at time t4308.

The second latch234latches the signal at the DCEXT node219at time t4308responsive to obtaining the logic high of the latchz node215. The signal at the DCEXT node219is a logic high because the first transistor214is on (e.g., VG1does not fall below the threshold voltage of the first transistor214when VG2falls below the threshold voltage of the second transistor226). In this manner, the signal at the DETFALL node223goes high at time t4308because the second latch234latches the logic high signal at the DCEXT node219.

The delay logic242provides a logic high at the LATCHZ_DLY node227at time t5310. For example, the delay logic242obtains the logic high at the latchz node215at time t4308and delays providing the logic high until time t5310. The third latch244obtains the high input of the LATCHZ_DLY node227at the clock input and latches the signal at the DET node225at time t5310. For example, the third logic gate240provides a logic high at the DET node225when the third logic gate240obtains the high signal of the DETFALL node223at time t4308. In this manner, when the third latch244is enabled (e.g., when the clock input is high), the third latch244provides whatever signal is at the data pin (e.g., the signal at the DET node225). Therefore, at time t5310, the third latch244latches the logic high signal of the DET node225and provides the logic high signal at the DETECTION node128.

Referring toFIG.4, the second signal plot400illustrates the signals at nodes in the detector circuit104. In the second signal plot400, the SW sequence signal goes high at time t1402. For example, the enabler250generates the SW sequence signal configured to turn on the first switch208and the third switch218and generates theSWsequence signal configured to turn off the second switch210and the fourth switch220. The signal at the sixth node211(e.g., the second voltage VG2) begins to increase at a ramp rate, responsive to the third switch218turning on and the fourth switch220turning off, at time t1402. For example, the second resistor222and the internal capacitor224charge the signal at the sixth node211to generate second voltage (VG2).

The signal at the PIN node134(e.g., the first voltage VG1) increases to the supply voltage at time t1302. For example, the external capacitor114is not present and does not resist the change in voltage supplied by the first switch208and the first resistor212when the first switch208is turned on. Therefore, VG1(e.g., the signal at the PIN node134) increases approximately simultaneously to the supply voltage.

The latch node217goes high at time t2404responsive to the signal at the sixth node211meeting the threshold voltage of the second transistor226. For example, the first logic gate230inverts the signal at the latchz node215when the second comparator228provides a logic low at time t2404responsive to the second transistor226turning on. The high signal at the latch node217enables the first latch232and, thus, the first latch232latches the signal at the DCEXT node219at time t2404. In some examples, the signal at the DCEXT node219is a logic high because the first transistor214is turned on at time t1402and remains on when the second transistor226turns on at time t2404.

The signal at the DETRISE node221goes high at time t2404responsive to the first latch232latching the high signal at the DCEXT node219. The signal at the DET node225goes low at time t2404responsive to the second logic gate236inverting the high signal at the DETRISE node221. For example, the inverted version of the signal at the DETRISE node221is input to the first input terminal of the third logic gate240and the signal at the DETFALL node223(e.g., a logic low signal) is input to the second input terminal of the third logic gate240thus causing the third logic gate240to output a logic low signal at the DET node225at time t2404.

The enabler250provides a logic low of the SW sequence at time t3406. The signal at the sixth node211begins to discharge at time t3406at a ramp rate responsive to the SW sequence. The signal at the PIN node134discharges to ground at time t3406, turning the first transistor214off. The first comparator216provides a logic low at the DCEXT node219at time t3406responsive to the first transistor214turning off.

The signal at the latch node217goes low at time t4408responsive to the signal at the sixth node211falling below the threshold voltage of the second transistor226. Also, the signal at the latchz node215goes high at time t4408responsive to the signal at the sixth node211falling below the threshold voltage of the second transistor226.

The second latch234latches the signal at the DCEXT node219at time t4408responsive to the high input at the latchz node215. For example, the second latch234provides a logic low at the DETFALL node223at time t4408responsive to obtaining a high signal at the clock input of the second flip-flip234.

The delay logic242provides a logic high at the LATCHZ_DLY node227at time t5410responsive to delaying the high input signal received at time t4408. The third latch244latches the signal at the DET node225at time t5410responsive to obtaining the high input signal from the delay logic242at the clock input of the third latch244. The signal at the DET node225is a logic low due to the first transistor214turning on before the second transistor226at time t1402and the first transistor214turning off before the second transistor226at time t3406. Therefore, third latch244provides a logic low at the DETECTION node128.

Referring toFIG.5, the third signal plot500illustrates the signals at nodes in the detector circuit104during the third operation. The third operation of the detector circuit104begins in a similar manner as the first and second operations. For example, the first switch208and the third switch218are turned on and the signal at the PIN node134and the sixth node211increase from their initial state. In the third signal plot500, the signal at the PIN node134is ramping up from a charged initial state at a time when the SW sequence goes high. The initial charge of the signal at the PIN node134is less than the threshold voltage of the first transistor214.

The signal at the latch node217goes high at time t1502responsive to the signal at the sixth node211meeting the threshold voltage of the second transistor226. For example, the second resistor222and the internal capacitor224generate the second voltage (VG2) that turns on the second transistor226. The second transistor226turns on at time t1502causing the second comparator228to provide a logic low at the latchz node215. The first logic gate230inverts the signal at the latchz node215and provides the logic high signal at the latch node217at time t1502.

The first latch232latches the signal at the DCEXT node219at time t1502responsive to the signal at the latch node217going high. The signal at the DCEXT node219is low at time t1502because the first transistor214is not turned at time t1502. Therefore, the first latch232provides a logic low at the DETRISE node221.

The signal at the latch node217goes low at time t2504responsive to the second transistor226turning off. For example, the enabler250turns off the first switch208and the third switch218and the signal at the sixth node211discharges below the threshold voltage of the second transistor226at time t2504.

The second latch234latches the signal at the DCEXT node219at time t2504. For example, the second latch234latches the logic low signal at the DCEXT node219(e.g., the first transistor214is turned off and the signal at the third node205is high) at time t2504. The signal at the DETFALL node223is low at time t2504.

The delay logic242provides a high signal at the LATCHZ_DLY node227at time t3506responsive to the signal at the latchz node215going high for a delay period. For example, when the second transistor226turns off, the second comparator228provides a logic high to input of the delay logic242. When the signal at the LATCHZ_DLY node227goes high, the third latch244latches the signal at the DET node225at time t3506.

The signal at the DET node225is high. For example, the third logic gate240obtains the inverted version of the signal at the DETRISE node221(e.g., a logic high) and the signal at the DETFALL node223(e.g., logic low) at time t3506. The third logic gate240provides a logic high signal at the DET node223at time t3506because the third logic gate240is an OR gate and at least one of the input terminals is receiving a logic high signal.

The third latch244provides the logic high signal at the DETECTION node128at time t3506. Therefore, the external capacitor114is detected, regardless of the initial charge.

Referring toFIG.6, the fourth signal plot600illustrates the signals at nodes in the detector circuit104during the fourth operation. The fourth operation of the detector circuit104begins in a similar manner as the first, second, and third operations. For example, the first switch208and the third switch218are turned on and the signal at the PIN node134and the sixth node211increase from their initial state. In the fourth signal plot600, the signal at the PIN node134is ramping up from a charged initial state at a time when the SW sequence goes high. The initial charge of the signal at the PIN node134is greater than the threshold voltage of the first transistor214.

The signal at the sixth node211increases beyond the threshold voltage of the second transistor226at time t1602and, thus, the signal at the latch node217goes high. For example, the second transistor226turns on responsive to the signal at the sixth node211increasing beyond the threshold voltage of the second transistor226and the second comparator228provides a logic low at the latchz node215, causing the first logic gate230to provide a logic high at the latch node217.

The first latch232latches the signal at the DCEXT node219at time t1602responsive to the signal at the latch node217going high. The first latch232latches a logic high signal at the DCEXT node219because the initial charge of the external capacitor114is greater than the threshold voltage of the first transistor214and, thus, the first transistor214is turned on before time t1602. The first latch232provides a logic high at the DETRISE node221at time t1602. The second logic gate236provides a logic low to the input of the third logic gate240at time t1602, and the second latch234does not provide a signal to the third logic gate240at time t1602. Therefore, the signal at the DET node223goes low responsive to the third logic gate240providing a logic low at time t1602.

The signal at the sixth node211decreases below the threshold voltage of the second transistor226at time t2604and, thus, the signal at the latch node217goes low. For example, the signal at the latchz node215goes high responsive to the second transistor226turning off at time t2604.

The second latch234latches the signal at the DCEXT node219responsive to the latchz node215going high at time t2604. In this example, the second latch234latches a logic high signal at the DCEXT node219because the signal at the PIN node134does not decrease below the threshold voltage of the first transistor214at time t2604. The second latch234provides a logic high at the DETFALL node223at time t2604responsive to latching the high signal at the DCEXT node219.

The delay logic242initiates at time t2604responsive to the signal at the latchz node215going high. For example, the delay logic242begins the delay period at time t2604. The delay logic242provides a logic high at the LATCHZ_DLY node227at time t3606. For example, the delay period occurs between time t2602and t3606and the delay logic242provides a logic high when the delay period ends (e.g., at time t3606).

The third flip-flip244latches the signal at the DET node225responsive to the signal at the LATCHZ_DLY node227going high. In this example, the signal at the DET node225is high at time t3606because the signal at the DETFALL node223is high at time t3606. The third latch244provides the logic high signal at the DETECTION node128. Therefore, the external capacitor114is detected, regardless of the initial charge.

FIGS.7and8are simulation results of responses of the elements of the example detector circuit104.FIG.7is a first simulation result700corresponding to the first signal plot300ofFIG.3, the third signal plot500ofFIG.5, and the fourth signal plot600ofFIG.6.FIG.8is a second simulation result800corresponding to the second signal plot400ofFIG.4.

The first simulation result700ofFIG.7shows the signals at the various nodes of the detector circuit104when the external capacitor114is present with a capacitance of 50 nF, 100 nF, 200 nF, 500 nF and 1 μF and an initial charge of 0 volts to 0.8 volts with a step of 0.1 volts, and a supply voltage of 1.7 volts to 1.9 volts. The first simulation result700illustrates16conditions of strong and weak combinations of the first transistor214, the second transistor226, the first and second resistors212,222, and the external capacitor114. For example, the strong and weak combinations correspond to the strong and weak fabrications of each of the above mentioned components. All of the 16 conditions of the detector circuit104illustrated in the first simulation result700have a bias current of approximately 10 percent variation.

In the first simulation result700, the signal at the latch node217goes high at time t1702responsive to the signal at the sixth node211(VG2) increasing to the threshold voltage (e.g., approximately 1 volt) and turning the second transistor226on. Additionally, in an example of the first simulation result700, the signal at the PIN node134(e.g., VG1) does not meet the threshold voltage of the first transistor214at time t1702because the external capacitor114causes the signal at the PIN node134to ramp slower than the signal at the sixth node211(e.g., as described above in connection withFIG.3). In another example of the first simulation result700, the signal at the PIN node134does meet the threshold voltage of the first transistor214at time t1702when the external capacitor114has an initial charge that is greater than the threshold voltage (e.g., as described above in connection withFIG.6). In another example of the first simulation result700, the signal at the PIN node134does not meet the threshold voltage of the first transistor214at time t1702because the external capacitor114has an initial charge that is less than the threshold voltage of the first transistor214and the capacitance is greater than the capacitance of the internal capacitor224(e.g., as described above in connection withFIG.5).

In the first simulation result700ofFIG.7, the transitions between high and low throughout the different nodes directly corresponds to the transitions between high and low of the signals illustrated in the first signal plot300, the third signal plot500, and the fourth signal plot600. In all examples, the signal at the DETECTION node128goes high at the end of the detection (e.g., at time t2704), to indicate that the external capacitor114is present.

The second simulation result800ofFIG.8shows the signals at the various nodes of the detector circuit104when the external capacitor114is not present. For example, the second simulation result800illustrates the response of the elements in the detector circuit104when the supply voltage is 1.7 volts to 1.9 volts, and the external capacitor114is not present. In the second simulation result800, the signal at the PIN node134(VG1) increases at a faster ramp rate than the signal at the sixth node211(VG2) responsive to the first switch208and the third switch218turning on at time t1802. In the second simulation result800, the signal at the DETECTION node128remains low at the end of the detection at time t2804to indicate that the external capacitor114is not present.

In the second simulation result800ofFIG.8, the transitions between high and low throughout the different nodes directly corresponds to the transitions between high and low of the signals illustrated in the second signal plot400.

FIG.9is an example truth table900showing the signals at the DETRISE node221, the DETFALL node223, and the DETECTION node128during four example conditions of the detector circuit104ofFIG.2corresponding to the four example operations.

For example, the truth table900illustrates the signals at the DETRISE node221, the DETFALL node223, and the DETECTION node128for the first condition902, when no external capacitor114is present in the system100. During the first condition902, when the third latch244latches the signal at the DET node225, the output of the first latch232is a logic high (1) at the DETRISE node221and the output of the second latch234is a logic low (0) at the DETFALL node223. The third logic gate240obtains the inverted signal at the DETRISE node221(e.g., a logic low (0)) and the low signal (0) at the DETFALL node223and provides a logic low (0) to the data pin of the third latch244. In this manner, the signal at the DETECTION node128is logic low (0), indicating that the external capacitor114is not coupled to the output of the LDO regulator108.

The truth table900illustrates the signals at the DETRISE node221, the DETFALL node223, and the DETECTION node128for the second condition904, when the external capacitor114is included in the system100with no initial charge. At the time the third flip-flip244is enabled (e.g., when the signal at the LATCHZ_DLY node227goes high), the signal at the DETRISE node221is logic low (0) and the signal at the DETFALL node223is logic high (1). The third logic gate240obtains the inverted signal at the DETRISE node221(e.g., a logic high (1)) and the high signal (1) at the DETFALL node223and provides a logic high (1). In this manner, the third latch244provides a logic high (1) at the DETECTION node128, indicating that the external capacitor114is coupled to the output of the LDO regulator108.

The truth table900illustrates the signals at the DETRISE node221, the DETFALL node223, and the DETECTION node128for the third condition906, when the external capacitor114is included in the system100with an initial charge that is less than the threshold voltage (Vth) of the first transistor214. At the time the third flip-flip244is enabled (e.g., when the signal at the LATCHZ_DLY node227goes high), the signal at the DETRISE node221is logic low (0) and the signal at the DETFALL node223is logic low (0). The third logic gate240obtains the inverted signal at the DETRISE node221(e.g., a logic high (1)) and the low signal (0) at the DETFALL node223and provides a logic high (1). In this manner, the third latch244provides a logic high (1) at the DETECTION node128, indicating that the external capacitor114is coupled to the output of the LDO regulator108.

The truth table900illustrates the signals at the DETRISE node221, the DETFALL node223, and the DETECTION node128for the fourth condition908, when the external capacitor114is included in the system100with an initial charge that is greater than the threshold voltage (Vth) of the first transistor214. At the time the third flip-flip244is enabled (e.g., when the signal at the LATCHZ_DLY node227goes high), the signal at the DETRISE node221is logic high (1) and the signal at the DETFALL node223is logic high (1). The third logic gate240obtains the inverted signal at the DETRISE node221(e.g., a logic high (1)) and the low signal (0) at the DETFALL node223and provides a logic high (1). In this manner, the third latch244provides a logic high (1) at the DETECTION node128, indicating that the external capacitor114is coupled to the output of the LDO regulator108.

FIG.10is a schematic of an example first capacitor detection circuit1000. The first capacitor detection circuit1000includes a first MOSFET1002, a second MOSFET1004, a large resistor1006, and a comparator1008. In some examples, the first capacitor detection circuit1000includes an external capacitor1010.

InFIG.10, the first MOSFET1002is a P-channel MOSFET and the second MOSFET1004is an N-channel MOSFET. The first MOSFET1002turns on when the gate-to-source voltage (Vgs) is greater than a threshold voltage of the first MOSFET1002. The second MOSFET1004turns on when the Vgs of the is greater than the threshold voltage of the second MOSFET1004.

The first capacitor detection circuit1000detects if a pin node1012is forced high, is forced low, or is floating. For example, the large resistor1006is coupled to the comparator1008and an output of an LDO regulator at the pin node1012. The LDO regulator may be implemented in a similar fashion as the LDO regulator108ofFIG.1.

In an operation of the first capacitor detection circuit1000, a clock signal1014is applied to a gate terminal of the first MOSFET1002and a gate terminal of the second MOSFET1004. In some examples, the clock signal1014causes the first MOSFET1002to turn on and the second MOSFET1004to turn off and vice versa. For example, the first MOSFET1002turns off and the second MOSFET1004turns on responsive to the clock signal1014going high. In other examples, the first MOSFET1002turns on and the second MOSFET1004turns off responsive to the clock signal1014going low. In this manner, the signal at an output node1016goes high and low. For example, when the first MOSFET1002is on, the signal at the output node1016goes high and when the second MOSFET1004is on, the signal at the output node1016goes low.

In a condition where the external capacitor1010is not coupled to the pin node1012, the output of the comparator1008toggles between high and low. For example, if the external capacitor1010is not present to oppose the changes in voltage of the signal at the output node1016, the signal at the pin node1012follows the inverted clock signal1014and, thus, the output of the comparator1008toggles.

In a condition where the external capacitor1010is coupled to the pin node1012, the output of the comparator1008is either always high or always low. For example, if the external capacitor1010is opposing the changes in voltage at the output node1016, the signal at the pin node1012depends on how long the external capacitor1010takes to charge (e.g., how big the capacitor1010is), the frequency of the clock signal1014, the resistance of the resistor1006, the threshold of the comparator1008, and a supply voltage supplied to the first MOSFET1002and the second MOSFET1004.

The first capacitor detection circuit1000ofFIG.10does not include an internal reference capacitor (e.g., such as the internal capacitor224ofFIG.2) and, thus, requires accurate clock signals1014, an accurate comparator1008, and a specific resistance of the resistor1006to operate accurately. The accuracy of the detector circuit104ofFIGS.1and2is bounded by variations in the internal capacitor224which, in an IC fabrication process, is very well controlled to be of the order of +/−10% and also includes temperature stability. Further the accuracy of the detector circuit104only depends on the ratio of resistors (e.g., the first resistor212and the second resistor222) which, when fabricated on an IC, can be very well matched to 0.1% accuracy. Further the capacitance of internal capacitor224can be trimmed (e.g., adjusted) using fuses or EEPROM (electrically erasable programmable read-only memory) during production test to generate a more precise level of accuracy (e.g., less than 1% accuracy) of the internal capacitor224in the application.

FIG.11is a schematic of an example LDO circuit1100. The LDO circuit1100includes an error amplifier1102, a power FET1104, a first feedback resistor1106, a second feedback resistor1108, an external capacitor1110, a switch1112, a minimum capacitor1114, a reference source1116, a kernel circuit1118, a clock and timing circuit1120, and a level detection circuit1122.

The error amplifier1102is the error amplifier of the LDO circuit1100. The error amplifier1102includes two input signals. The first input signal to the error amplifier1102is a reference signal from the reference source1116. The second input signal to the error amplifier1102is a feedback signal from the first feedback resistor1106and the second feedback resistor1108. The error amplifier1102includes an output signal coupled to a gate terminal of the power FET1104.

The power FET1104regulates the signal at the output of the LDO circuit1100based on the output of the error amplifier1102. The power FET1104charges the signal at the Vlow node1124responsive to the error amplifier1102. The signal at the Vlow node1124charges at a rate that is dependent on the external capacitor1110.

The switch1112, the clock and timing circuit1120, and the level detection circuit1122are implemented in the LDO circuit1100for the purpose of detecting the external capacitor1110. For example, in an operation of the LDO circuit1100, the detection of the external capacitor1110is initiated when the clock and timing circuit1120sends a control signal to the switch1112. The switch1112shorts (e.g., turns on, enables, etc.) responsive to the control signal.

The clock and timing circuit1120turns on the switch1112and the voltage at the Vlow node1124is directly input to the positive terminal of the error amplifier1102. The error amplifier1102provides a high level to turn off the power FET1104, because the power FET1104is a P-channel MOSFET. The voltage at the Vlow node1124is discharged, responsive to turning off the power FET1104. The second feedback resistor1108discharges the voltage at the Vlow node1124until the voltage at the Vlow node1124is equal to a reference voltage output by the reference source1116and until the output voltage of the error amplifier1102slows down (e.g., decreases, slows down to the original working voltage, etc.).

During the error amplifier1102recovery process (e.g., the process at which the output voltage of the error amplifier decreases), the level detecting circuit1122detects whether the error amplifier1102is always at a high level between settings (e.g., for a length of pre-determined time). If the level detecting circuit1122determines the error amplifier1102is at a high level between the setting, the level detecting circuit1122determines that the external capacitor1110has a normal capacitance and/or is otherwise connected to the output of the LDO circuit1100. Otherwise, the level detecting circuit1122determines that the external capacitor1110is not connected or the capacitance is abnormal.

Example methods, apparatus and articles of manufacture described herein improve the accuracy of detecting external capacitors in systems implementing LDO regulators. Example methods, apparatus and articles of manufacture described herein improve the accuracy of detection by implementing an internal capacitor with a number of match components, such as matched resistors, matched comparators, and matched transistors that assist in generating and comparing two voltage ramps corresponding to the internal capacitor and the external capacitor.

Example methods, apparatus, systems, and articles of manufacture to improve detection of capacitors implemented for regulators are described herein such as the following.

Example 1 includes an apparatus comprising a resistor (212) having a resistor terminal, a capacitor (114) coupled to the resistor terminal, a transistor (214) having a current terminal and a gate, the gate coupled to the resistor terminal and coupled to the capacitor (114), a comparator (216) having a comparator input and a comparator output, the comparator input coupled to the current terminal, and a latch (232) having a latch input coupled to the comparator output.

Example 2 includes the apparatus of example 1, wherein the resistor (212) is a first resistor (212), the resistor terminal is a first resistor terminal, the capacitor (114) is a first capacitor (114), the transistor (214) is a first transistor (214), the current terminal is a first current terminal, the gate is a first gate, and the comparator (216) is a first comparator (216), the comparator input is a first comparator input, the comparator output is a first comparator output, the apparatus further including a second resistor (222) having a second resistor terminal, a second capacitor (224) coupled to the second resistor terminal, a second transistor (226) having a second current terminal and a second gate, the second gate coupled to the second resistor terminal and the second capacitor (224), and a second comparator (228) having a second comparator input and a second comparator output, the second comparator input coupled to the second current terminal.

Example 3 includes the apparatus of example 1, wherein the resistor (212) is a first resistor (212), the resistor terminal is a first resistor terminal, the capacitor (114) is a first capacitor (114), the transistor (214) is a first transistor (214), the current terminal is a first current terminal, the gate is a first gate, and the comparator (216) is a first comparator (216), the comparator input is a first comparator input, the comparator output is a first comparator output, the first resistor (212) includes a second resistor terminal and wherein the apparatus further includes a second resistor (222) having a third resistor terminal and a fourth resistor terminal, a second capacitor (224) coupled to the third resistor terminal, a second transistor (226) having a second current terminal and a second gate, the second gate coupled to the third resistor terminal and the second capacitor (224), a second comparator (228) having a second comparator input and a second comparator output, the second comparator input coupled to the second current terminal, a supply terminal (252), a first switch (208) having a first switch terminal and a second switch terminal, the first switch terminal coupled to the supply terminal (252) and the second switch terminal coupled to the second resistor terminal, a second switch (210) having a third switch terminal coupled to the second switch terminal and the second resistor terminal, a third switch (218) having a fourth switch terminal and a fifth switch terminal, the fourth switch terminal coupled to the supply terminal (252) and the fifth switch terminal coupled to the fourth resistor terminal, and a fourth switch (220) having a sixth switch terminal coupled to the fourth resistor terminal.

Example 4 includes the apparatus of example 3, wherein the first comparator (216) is an inverting Schmitt trigger and the second comparator (228) is a Schmitt trigger.

Example 5 includes the apparatus of example 1, wherein the transistor (214) is an N-channel metal-oxide-semiconductor field-effect transistors (MOSFETs).

Example 6 includes the apparatus of example 1, wherein the latch (232) is a first latch (232), the resistor (212) is a first resistor (212), the resistor terminal is a first resistor terminal, the capacitor (114) is a first capacitor (114), the transistor (214) is a first transistor (214), the current terminal is a first current terminal, the gate is a first gate, and the comparator (216) is a first comparator (216), the comparator input is a first comparator input, the comparator output is a first comparator output, the apparatus further includes a second resistor (222) having a third resistor terminal and a fourth resistor terminal, a second capacitor (224) coupled to the third resistor terminal, a second transistor (226) having a second current terminal and a second gate, the second gate coupled to the third resistor terminal and the second capacitor (224), a second comparator (228) having a second comparator input and a second comparator output, the second comparator input coupled to the second current terminal, the first latch (232) having a first data input, a first clock input, and a first latch output, the first data input coupled to the first comparator output, a second latch (234) having a second data input, a second clock input, and a second latch output, the second data input coupled to the first comparator output and the second clock input coupled to the second comparator output, and a first logic gate (230) having a first logic gate input and a first logic gate output, the first logic gate input coupled to the second comparator output and the first logic gate output coupled to the first clock input.

Example 7 includes the apparatus of example 6, wherein the apparatus includes a second logic gate (236) having a second logic gate input and a second logic gate output, the second logic gate input coupled to the first latch output, and a third logic gate (240) having a first logic input, a second logic input, and a third logic gate output, the first logic input coupled to the second logic gate output, the second logic input coupled to the second latch output.

Example 8 includes the apparatus of example 7, wherein the first logic gate (230) and the second logic gate (236) are inverter logic gates.

Example 9 includes the apparatus of example 7, wherein the third logic gate (240) is an OR logic gate.

Example 10 includes the apparatus of example 1, wherein the latch (232) is a first latch (232), the resistor (212) is a first resistor (212), the resistor terminal is a first resistor terminal, the capacitor (114) is a first capacitor (114), the transistor (214) is a first transistor (214), the current terminal is a first current terminal, the gate is a first gate, and the comparator (216) is a first comparator (216), the comparator input is a first comparator input, the comparator output is a first comparator output, the apparatus further includes a second resistor (222) having a third resistor terminal and a fourth resistor terminal, a second capacitor (224) coupled to the third resistor terminal, a second transistor (226) having a second current terminal and a second gate, the second gate coupled to the third resistor terminal and the second capacitor (224), a second comparator (228) having a second comparator input and a second comparator output, the second comparator input coupled to the second current terminal, a second latch (234) coupled to the first comparator output and the second comparator output, a first logic gate (230) coupled to the second comparator output and coupled to the first latch (232), a second logic gate (236) coupled to the first latch (232), a third logic gate (240), the third logic gate (240) coupled to the second logic gate (236) and coupled to the second latch (234), and a third latch (244) coupled to the third logic gate (240).

Example 11 includes the apparatus of example 10, wherein the first latch (232), the second latch (234), and the third latch (244) are D-type flip-flops.

Example 12 includes the apparatus of example 1, wherein the latch (232) is a first latch (232), the transistor (214) is a first transistor (214), the current terminal is a first current terminal, the gate is a first gate, and the comparator (216) is a first comparator (216), the comparator input is a first comparator input, the comparator output is a first comparator output, the apparatus further includes a second transistor (226) having a second current terminal, a second comparator (228) having a second comparator input and a second comparator output, the second comparator input coupled to the second current terminal, a delay logic (242) having a delay logic input and a delay logic output, the delay logic input coupled to the second comparator output, and a second latch (244) having a clock input coupled to the delay logic output.

Example 13 includes the apparatus of example 1, wherein the latch (232) is a first latch (232), the resistor (212) is a first resistor (212), the resistor terminal is a first resistor terminal, the capacitor (114) is a first capacitor (114), the transistor (214) is a first transistor (214), the current terminal is a first current terminal, the gate is a first gate, and the comparator (216) is a first comparator (216), the comparator input is a first comparator input, the comparator output is a first comparator output, the apparatus further includes a second resistor (222) having a third resistor terminal and a fourth resistor terminal, a second capacitor (224) coupled to the third resistor terminal, a second transistor (226) having a second current terminal and a second gate, the second gate coupled to the third resistor terminal and the second capacitor (224), a second comparator (228) having a second comparator input and a second comparator output, the second comparator input coupled to the second current terminal, the first latch (232) having a first data input, a first clock input, and a first latch output, the first data input coupled to the first comparator output, a second latch (234) having a second data input, a second clock input, and a second latch output, the second data input coupled to the first comparator output and the second clock input coupled to the second comparator output, a first logic gate (230) having a first logic gate input and a first logic gate output, the first logic gate input coupled to the second comparator output and the first logic gate output coupled to the first clock input, a second logic gate (236) having a second logic gate input and a second logic gate output, the second logic gate input coupled to the first latch output, a third logic gate (240) having a first logic input, a second logic input, and a third logic gate output, the first logic input coupled to the second logic gate output, the second logic input coupled to the second latch output, a delay logic (242) having a delay logic input and a delay logic output, the delay logic input coupled to the second comparator output, and a third latch (244) having a third data input and a third clock input, the third data input coupled to the third logic gate output and the third clock input coupled to the delay logic output.

Example 14 includes a system comprising a regulator (108) including a regulator output adapted to be coupled to a first capacitor (114), and a detector circuit (104) including a first transistor (214) having a first gate coupled to the regulator output and adapted to be coupled to the first capacitor (114), a second transistor (226) including a second gate adapted to be coupled to a second capacitor (224), and a latch (244) configured to latch a detection signal corresponding to a comparison between a first signal at the regulator output and a second signal at the second gate, the detection signal indicative of a status of the first capacitor (114).

Example 15 includes the system of example 14, wherein the system comprises a controller (102), the controller (102) includes a first controller output (116) coupled to an input, a second controller output (120) coupled to the detector circuit (104), and a controller input (126) coupled to an output of the latch (244).

Example 16 includes the system of example 15, wherein the detector circuit (104) comprises an enabler (250) coupled to the second controller output (120), the enabler (250) to initiate the detector circuit (104) to generate the detection signal based on a third signal at the second controller output (120).

Example 17 includes the system of example 14, wherein the regulator (108) is a low-dropout regulator adapted to be coupled to the first capacitor (114) externally.

Example 18 includes a method comprising applying a detection logic sequence to a detector circuit (104), generating a first voltage (VG1) responsive to the detection logic sequence at a first gate terminal of a first transistor (214), the first voltage (VG1) to ramp at a first voltage ramp rate dependent on a status of a first capacitor (114) and a first resistor (212) coupled to the first transistor (214), generating a second voltage (VG2) responsive to the detection logic sequence at a second gate terminal of a second transistor (226), the second voltage (VG2) to ramp at a second voltage ramp rate dependent on a size of a second capacitor (224) and a second resistor (222), the second capacitor (224) and the second resistor (222) coupled to the second transistor (226), comparing a speed of the first voltage ramp rate to a speed of the second voltage ramp rate, and determining the status of the first capacitor (114) based on the comparison.

Example 19 includes the method of example 18, wherein applying the detection logic sequence includes enabling a first switch (208) and a third switch (218) for a first period of time to generate the first voltage (VG1) and the second voltage (VG2), the first switch (208) coupled to the first resistor (212) and the third switch (218) coupled to the second resistor (222), disabling a second switch (210) and a fourth switch (220) for the first period of time concurrently to enabling the first switch (208) and the third switch (210) to generate the first voltage (VG1) and the second voltage (VG2), the second switch (210) coupled to the first resistor (212) and the fourth switch (220) coupled to the second resistor (222), responsive to the first period of time ending disabling the first switch (208) and the third switch (218), enabling the second switch (210) and the fourth switch (220) concurrently to disabling the first switch (208) and the third switch (218) to discharge the first voltage (VG1) through the second switch (210) and the first resistor (212) and to discharge the second voltage (VG2) through the fourth switch (220) and the second resistor (222), comparing a speed of a first discharge rate of the first voltage (VG1) to a speed of a second discharge rate of the second voltage (VG2), and determining the status of the first capacitor (114) based on the comparison.

Example 20 includes the method of example 18, further including providing a detection signal indicative of the status of the first capacitor (114) to a controller (102), the status corresponding to a connection of the first capacitor (114).

Example 21 includes the method of example 18, further including configuring the detector circuit (104) for detection of a valid range of the first capacitor (114) based on modifying values of the first resistor (212) and the second resistor (222).

In this description, the term “and/or” (when used in a form such as A, B and/or C) refers to any combination or subset of A, B, C, such as: (a) A alone; (b) B alone; (c) C alone; (d) A with B; (e) A with C; (f) B with C; and (g) A with B and with C. Also, as used herein, the phrase “at least one of A or B” (or “at least one of A and B”) refers to implementations including any of: (a) at least one A; (b) at least one B; and (c) at least one A and at least one B.

In this description, unless otherwise stated, if two components or values are described as being “approximately” the same, “approximately” equal or “approximately” identical, then it means they are within +/−5 percent (±5%) of each other.