Voltage reference circuit using PTAT voltage

A voltage reference generator is disclosed that includes a current generator for generating a current that is proportional to absolute temperature (PTAT), the current generator having an internal resistance. This provides a PTAT current that is proportional to the resistance and wherein the temperature coefficient of the PTAT current is defined by the resistance. An output node is driven by the current generator with the PTAT current. A stack of serial connected MOS devices is connected between the output voltage and a ground reference voltage. The stack of transistors has a transimpedance associated therewith which has a temperature coefficient that is opposite in polarity to the temperature coefficient of the internal resistance and of a magnitude to provide a voltage on the output node that is substantially stable over temperature.

TECHNICAL FIELD OF THE INVENTION

The present invention relates in general to voltage references and, more particularly, to a voltage reference utilized in a voltage regulator incorporating therein a low power band gap reference generator.

BACKGROUND OF THE INVENTION

Many analog circuits require voltage references, such as A/D and D/A converters, voltage regulators, etc. A voltage reference must be, inherently, well-defined and insensitive to temperature, power supply and load variations. The resolution of an A/D or D/A converter, for example, is limited by the precision of its reference voltage over the supply voltage range of the circuit and the operating temperature range thereof. A band gap reference voltage generator is a well utilized circuit that is typically used for the purpose of generating such a temperature independent reference voltage. These voltage references exhibit both high power supply rejection and possess a low temperature coefficient, and these type of voltage reference circuits are probably the most popular high performance voltage references utilized in integrated circuits. However, integrated circuit design is predominated by the need for low power, low voltage operation. This inherently will lead to the need for utilizing CMOS process technology, the technology of choice. Since the band gap reference is bipolar in nature, solutions are required to create the reference voltage without the use of the costly BiCMOS process. Further, for low power operation, there will typically be provided in the band gap reference ratiometric related resistors. In order to provide for a low current, one of these resistors is typically on the order of many times the size of the other resistor and this can lead to some fairly large resistors to realize the low current operation. The area required for these larger resistors is of concern and presents a disadvantage when considering an area efficient reference generator.

SUMMARY OF THE INVENTION

The present invention disclosed and claimed herein, in one aspect thereof, comprises a voltage reference generator. A current generator is provided for generating a current that is proportional to absolute temperature (PTAT), the current generator having an internal resistance. This provides a PTAT current that is proportional to the resistance and a voltage and wherein the temperature coefficient of the PTAT current is defined by both. An output node is driven by the current generator with the PTAT current. A stack of serial connected MOS devices is connected between the output voltage and a ground reference voltage. The stack of transistors has a transimpedance associated therewith and which has a temperature coefficient such that, when combined with the PTAT generated current, provides a voltage on the output node that is of sufficient magnitude and substantially stable over temperature.

DETAILED DESCRIPTION OF THE INVENTION

Referring now toFIG. 1, there is illustrated a diagram for a voltage regulator. The voltage regulator basically is comprised of a p-channel pass transistor102having the source/drain thereof connected between an input voltage on node104and a regulated output voltage on output pad106. The output regulated voltage on the output pad106drives the on-chip circuitry associated therewith (not shown). This is the regulated voltage output. The gate of the transistor102is driven by an amplifier108that provides the regulating voltage. The negative input of amplifier108is connected to a node110. Node110has a current driven thereto by a current source112connected between the supply voltage and node110for driving a reference load device114. The reference load device114will be described in detail herein below. The current source112provides a current that is a Proportional To Absolute Temperature (PTAT) current. This current has a Positive Temperature Coefficient (PTC) and the reference load114will have a counteracting Negative Temperature Coefficient (NTC), so as to provide an overall zero temperature coefficient (ZTC) output on node110. In general, the current source112and output reference load114provide a voltage circuit.

The positive input of the amplifier108is connected to a node116. Node116is also connected to one side of a current sink119to ground. The amplifier108will compare this voltage on node116with the voltage on node110and adjust the voltage on the gate of transistor102such that the voltage on node106is regulated to that on the reference node110. Note that this is a fairly conventional regulator circuit with the exception of the way in which the reference voltage on node110is generated.

Referring now toFIG. 2, there is illustrated a schematic diagram of a conventional prior art band gap generator. These type of band gap generator circuits are well known in the art. A first PNP transistor202is connected between a node204and ground with the emitter thereof connected to node204and the collector thereof connected to ground. The base thereof is connected to ground. As such, transistor202appears as a diode. A second PNP transistor203is connected between a node206and ground with the emitter thereof connected to node206and the collector thereof connected to ground. The base of transistor203is connected to ground and, therefore, it is configured as a diode between node206and ground. A resistor208is connected between node206and a node210. A first current source212is connected between VDDand node204and drives the emitter of transistor202. A second current source214is mirrored with transistor212and is connected between VDDand node210and drives the resistor208and transistor203. An operational amplifier216has one input thereof connected to node210and one input thereof connected to node204. The output of operational amplifier216is operable to vary the currents through current sources212and214.

An output leg is provided with a PNP transistor218connected between a node220and ground, the emitter thereof connected to node220and the collector thereof connected to ground. The base thereof is connected to ground also. This is a diode configured transistor. A resistor222is connected between an output node224and node220. A third current source226is connected between VDDand node224and drives the current thereto. For discussion purposes, transistor202will be labeled Q1, transistor203labeled Q2, resistor208labeled R1and resistor222labeled R2. The voltage on the node224is defined as:

Vref=VEBQ3+R2R1⁢VT⁢⁢ln⁡(A1A2)
This is a well understood equation and is found in most text books on the subject matter.

Both of the resistors208and222have a Positive Temperature Coefficient (PTC). If resistor222were the same value as resistor208, then the variation with respect to temperature would be the same. To minimize this, it is typical to increase the size of resistor222relative to that of resistor208such that resistor222is on the order of approximately five times the size of resistor208. However, it can be noted that the drop across the emitter-base junction of transistor218will be 0.7V and this is defined by the physics of the semiconductor device. This is fairly constant even through process variations. The PTAT current flowing through resistor222is ratiometrically related to the current flowing through resistor208. By increasing the size of resistor222relative to resistor202, the PTC is amplified. For example, the emitter-based junction of transistor218or the diode provided thereby has a Negative Temperature Coefficient (NTC) of approximately −2 mV/° C. The voltage I-R using resistor206has a temperature coefficient of +0.5 mV/° C., such that four resistors the size of resistor206that would comprise resistor222would result in a +2.0 mV/° C. PTC. This would offset the temperature coefficient of the diode218and would provide a temperature stable output voltage on node224. Again, this is a conventional operation.

For low current operations, it is desirable to minimize the amount of current that flows through resistor208and resistor222. If resistor208is increased in size, since the diode in transistor203has a relatively fixed voltage there across, then a much lower current can be provided. However, this then requires that resistor222to be much larger. The problem this presents in a low current operational mode is that the resistors become very large and can occupy a large amount of area. For example, for a low current operation, the resistor208might be of the size 127 kilo-ohms and the resistor222could be on the order of 522 kilo-ohms. These are very large resistors and take up a lot of area and are not very area efficient.

Referring now toFIG. 3, there is illustrated a schematic diagram of the voltage reference circuit of the present disclosure with an area efficient output load device which is comprised of a stack of saturated and linear devices with a PTAT current flowing there through. An n-channel transistor302has the source/drain path thereof connected between a node304and ground, the gate thereof connected to node304. A second n-channel transistor306has the source/drain path thereof connected between a node308and a node310. Node310is connected to one side of a resistor312, the other side thereof connected to ground. Node304is connected to one side of the source/drain path of a p-channel transistor314, the other side thereof connected to VDD. The gate of transistor314is connected to a node316with a second p-channel transistor318having the source/drain path thereof connected between VDDand the node308, the gate of p-channel transistor318connected to node316in a diode-configured manner. In this embodiment, transistor314is sized at “X” and transistor318is sized at “2x.” Therefore, the current flowing through transistor314will be I1and the current flowing through transistor318will be 2I1. Thus, the current flowing through resistor312will be 2I1. The currents I1and 2I1are PTAT currents. This is sometimes referred to as a self-biased low current reference generator.

The current through transistors314and318is mirrored to a p-channel transistor330having the source/drain path thereof connected between VDDand an output node332, the gate thereof connected to node316. Transistor330is sized in the disclosed embodiment to “X” such that the current there through is I1. Node332is connected to one side of the output node reference114to ground. The PTAT current flowing through the output reference node114will vary over temperature, but the impedance of the output mode reference114will vary as a function of temperature to maintain the voltage on node332at a temperature independent level. This will be described in more detail herein below. As will also be described herein below, the output reference node114is fabricated with a stack of linear and saturated MOS devices and, therefore, will have significantly less area associated with the construction thereof and is easily programmed.

Referring now toFIG. 4, there is illustrated a schematic diagram of the output reference mode114. There are provided four n-channel transistors404,406,408and410connected in series between node332and a node412in a stack. Transistor404has the source/drain path thereof connected between node332and a node414, the gate thereof connected to the source at node332in a diode configuration. Transistor406is also connected in a diode configuration with the source/drain path thereof connected between node414and a node416, the gate thereof connected to node414. Transistor408has the source/drain path thereof connected between node416and a node418, the gate thereof connected to node416. Transistor410has the source/drain path thereof connected between node418and node412, the gate thereof connected to node418. Transistors404–410are therefore configured such that they are operating in the saturated mode. The voltage across the source/drain path of each of the transistors404–410will be the gate-to-source voltage, VGS, due to the way they are connected. The transistors406–410are low VTdevices.

Each of the transistors404–410are operable to be switched out of the circuit between node332and node412. A first p-channel transistor424has the source/drain path thereof connected between node332and node414. The second p-channel transistor426has the source/drain path thereof connected between node332and node416. A third p-channel transistor428has the source/drain path thereof connected between node332and node418. A fourth p-channel transistor430has the source/drain path thereof connected between node332and node412. The gates of transistors424–430provide the signals for selecting how many and which of the transistors404–410are connected in series between node332and node412.

There are provided two variable length transistor structures432and434, comprised of a transistor structure that effectively provides a transistor with a variable length for a given width. (It should be understood that the transistors could have a variable width also.) The variable length transistor structure432is connected between node412and a node436. The variable length transistor structure434is connected between node436and a node438. Each of the variable length transistor structures432and434is illustrated as a transistor having the gate thereof connected in a diode configuration such that they operate in the saturated range such that VGSis the voltage there across. Therefore, there will be a voltage VGSacross nodes412and436and a voltage VGSacross nodes436and438, this being varied by varying the length of the transistor, as will be described herein below. A third variable length transistor structure440is provided and is disposed between node438and ground. This is illustrated as a transistor with an associated gate structure that is connected to node412and, therefore, operates in the linear region. The voltage there across will be the drain-to-source voltage, VDS. Changing the length of transistors432and434changes the VGS. Transistor operates like a linear rdsresistor with a PTC. Further, each of the variable length transistor structures432and434has the length varied there through for the purpose of changing the voltage on the output node332and calibrating out process variations. By changing the length on the transistors, there is provided an overall effect on the R of the device and the voltage thereacross.

Referring now toFIG. 5, there is illustrated a schematic diagram of either of the transistor structures432or434, the transistor structure432being illustrated. The transistor structure432is comprised of a plurality of n-channel transistors444disposed in series with basically a common channel with the gates thereof all connected together and to the node412. There are provided a plurality of p-channel transistors446that are connected between the node412and the source/drain junction of select ones of the transistors444. In one disclosed embodiment, there are provided a plurality of these transistors444. However, some of these transistors444have different L/W ratios (length-to-width ratios). For example, the first three of the transistors444connected to node436from the bottom thereof have widths of 5 microns, but lengths of 250 microns, one micron and five microns, respectively. The remaining of the transistors444have a width of one micron and a length of five microns. Therefore, it can be seen that the width of the channel for substantially all the transistors is approximately 1 micron. The p-channel transistors446are configured such that they selectively connect node412to eight (not all) of the source/drain junctions between transistors444. The first five source/drain junctions between the first and second transistors444from node436extending up to node412will be selectively connectable to node412and also the eighth and twelfth source/drain junctions.

The transistor structure434is identical to structure432but connected between nodes438and436.

Referring now toFIG. 6, there is illustrated a schematic diagram of the variable length transistor structure440. There are provided a plurality of n-channel transistors602connected in series between the node438and ground with all of the gates thereof connected to node412, such that, as described herein above, they operate in the linear region. There will be provided a plurality of N-channel gate transistors604connected between select ones of the common source/drain junctions between adjacent ones of transistors602and other ones thereof. As such, the transistors604can selectively “short-out” select ones of the transistors602from the “stack.” This is in response to a temperature coefficient adjustment for the overall stack of transistors comprised of the saturated and linear operating transistors.

Referring now toFIG. 7, there is illustrated a layout for the transistors disposed in the stack, these being adjacent transistors. There is provided a common channel region that runs along a given length of the semiconductor substrate. This will typically be formed in an active region, such that a channel can be defined. Each transistor will be defined by a source region702and a drain region704, it being noted that each of the source regions and drain regions are shared by another adjacent transistor, such that they are common source/drain regions. There will be a channel region706disposed there between, each channel region defined by a region of active semiconductor material disposed between insulated regions such as field oxide insulating regions. The source/drain regions702/704are heavily diffused regions that are of opposite conductivity to the conductivity type of the channel region. These allow for contacts from upper layers to interfaced therewith. As such, they may have a larger dimension than the channel region706. Each of the channel regions has disposed there over a gate conductor710, which gate conductor710is separated from the surface of the channel region by a layer of gate oxide. The length of the transistor is the dimension between the source/drain region702/704. The width of the transistor is the width of the channel region. Therefore, it can be seen that by connecting transistors in this manner, a fairly long string of adjacently disposed transistors can be connected together. Further, if a diode connection is required, it is only necessary for the gate conductor to be connected to the appropriate one of the associated source/drain regions702/704. This connection is not shown in this embodiment, as this merely shows the length of adjacently disposed transistors being stringed together.