Isolation/removal of faults during LBIST testing

A method of LBIST testing of an entire chip (i.e. all logic and arrays are getting system clocks) enables finding intermittent fault in an area, such as the L1 cache. Latches such as GPTR latches can be set such that the L1 cache will no longer receive system clocks during LBIST testing. Logic causing an intermittent failure will no longer receive system clocks and hence will no longer cause intermittent LBIST signatures. LBIST testing can proceed on looking for the next failure, if one existed, or proving that the remaining logic contains no faults. Generally, a chip, has a basic clock distribution and control system that the chip is divided into a number (N) of functional units with each unit receiving system clocks from its own clock control macro. Each clock control macro receives an oscillator signal and a bit from the GPTR (General Purpose Test Register). All the functional units contain latches that are connected into one scan chain.

FIELD OF THE INVENTION 
This invention is related to computer system chips and in particular to an 
improved isolation/removal of faults during logic built in self test 
(LBIST) testing via clock system controls. 
BACKGROUND OF THE INVENTION 
LBIST (Logic Built In Self Test) was (and still is) used extensively within 
IBM on chips to test for both DC and AC faults in the logic and some 
portions of the arrays. Published materials about LBIST include IBM's TDB 
v38 n11 of 11-95, dealing with a method an apparatus for handling multiple 
clock domains within a single logic built-in self test structure. This is 
but an example of testing during the debug of IBM's system chips. LBIST 
testing has been used to diagnose and characterize chip problems and 
uncovered a number of unique failure mechanisms. Two examples of these 
failure mechanisms are: 
1) Coupled noise causing critical signals to change their delay as well as 
causing latches to change states when certain test patterns were executed. 
2) A wide range in process parameters of the chips that were manufactured 
(for example very strong P-fets with very weak N-fets) stressed some of 
the dynamic circuits in the arrays, causing intermittent failures. 
If these failure mechanisms result in "hard" repeatable faults, LBIST 
testing could still be used to test the remaining logic since there are 
known mathematical formulas for determining a new "valid signature" when a 
"hard" fault exists. 
Unfortunately these failure mechanisms resulted in faults that were 
intermittent and very sensitive to environmental conditions such as power 
supply and temperature. Hence, LBIST could not be used to test the 
remaining logic on the chip because we could not determine what the "valid 
signature" should be. This one intermittent fault could be masking a 
number of other faults, that may be real design problems, yet LBIST would 
not be able to test for these faults. This would be desirable. 
SUMMARY OF THE INVENTION 
Our invention provides a way of testing a chip in parts by testing areas 
where control can be maintained for those sections of the chip that 
receive system clocks. In the case where intermittent faults are found to 
exist on the chip, the sections of the chip that produce intermittent 
faults can be isolated and removed from generating intermittent LBIST 
signatures. In addition, we can minimize the power supply noise to an 
acceptable level by maintaining control over those sections of the chip 
that receive system clocks. 
The improvements which we have made achieve a way to use LBIST as a 
standard industry manufacturing test technique for these problem areas and 
this approach expands the capabilities of LBIST such that it can be used 
to diagnose and characterize chip problems by the industry. 
These and other improvements are set forth in the following detailed 
description. For a better understanding of the invention with advantages 
and features, refer to the description with reference to the following 
drawing.

DETAILED DESCRIPTION OF THE INVENTION 
Before considering our preferred embodiments in detail, it may be 
worthwhile to note, by way of example, that in accordance with our 
invention, if we start LBIST testing the entire chip (i.e. all logic and 
arrays are getting system clocks) and find an intermittent fault in the L1 
cache, we could set the GPTR 10 latches shown in FIG. 1 having bits 1, 2, 
3 . . . N such that the L1 cache will no longer receive system clocks 
during LBIST testing. Hence the logic causing the intermittent failure 
will no longer receive system clocks and hence will no longer cause 
intermittent LBIST signatures. LBIST testing can proceed on looking for 
the next failure, if one existed, or proving that the remaining logic 
contains no faults. 
Turning now to our invention in greater detail, it will be seen from FIG. 1 
showing a chip with a basic clock distribution and control system that the 
chip is divided into a number (N) of functional units with each unit 
receiving system clocks from its own clock control macro. Each clock 
control macro receives an oscillator signal and a bit from the GPTR 
(General Purpose Test Register). All the functional units, the L1 cache 
array 11, the L1 directory array 12, the Instruction Unit 13, the 
Execution Unit 14, listed in FIG. 1 and any others on the chip contain 
latches that are connected into one scan chain (Scan In to Scan Out). FIG. 
1 which illustrates our preferred embodiment in which the chip is divided 
up into a number (N) of functional units (e.g. 11, 12, 13, 14) with each 
unit's system clock being controlled independently from its own unique 
clock control macro 15, 16, 17, 18. The clock macro uses the oscillator 
input 19 to generate system clocks to the functional unit that it is 
connected to via the main clock distribution unit 20. The GPTR bit is used 
by the clock control macro to stop or gate-off the system clocks when the 
GPTR bit is set to a binary `1` value. If and when a functional unit on 
the chip experiences an intermittent fault, we can simply set the GPTR bit 
that stops the system clocks to that functional unit. The LBIST test can 
then be run with the clocks to that functional unit shut off to test the 
remaining logic on the chip that receives clocks. 
As we just described we isolate and remove the logic that was causing an 
intermittent fail so LBIST could continue to be used to search for the 
next failure if any existed by using on-chip clock control and 
distribution logic to individually control the clocks to each unique array 
and to a number of different logic sections on the chip. A set of scan 
only GPTR (General Purpose Test Registers) is used to determine what 
arrays and sections of logic will receive system clocks during LBIST 
testing. 
A sufficient number of GPTR's will be used to divide a chip into many 
individually controllable sections. Under this design multiple faults can 
be isolated and removed from the generation of the LBIST signature. 
This solution has another advantage that we believe is important for future 
high performance machines. Since LBIST uses pseudo random patterns to test 
the chip, the switching activity of the logic under test is on average 
50%, which is much higher than the switching activity when the chip is 
functioning under "normal" operating conditions. As chip speeds and 
density increase, the amount of instantaneous power supply noise and its 
influence of the operation of the circuits is becoming a real concern 
under these very stressful test conditions. By maintaining control of the 
system clocks to various sections of the chips, one can minimize the power 
supply noise to an acceptable level. 
While we have described our preferred embodiments of our invention, it will 
be understood that those skilled in the art, both now and in the future, 
may make various improvements and enhancements which fall within the scope 
of the claims which follow. These claims should be construed to maintain 
the proper protection for the invention first disclosed.