Data control unit

A data control unit includes a primary power supply line to which a primary power supply voltage is supplied; a secondary power source line to which a secondary power supply voltage is supplied; a voltage converter for converting the primary power supply voltage into the secondary power supply voltage; a voltage level detection unit which is connected to the primary power source line, and outputs a voltage level detection signal; a reset signal generator which is connected to the secondary power source line, and outputs a reset signal; and a control signal generation unit which receives the voltage level detection signal and the reset signal, and outputs a control signal. The data control unit detects power supply cutoff, and secures the time for sufficient backup process.

This application is based upon and claims the benefit of priority from prior Japanese Patent Applications No. P2008-33721 filed on Feb. 14, 2008, the entire contents of which are incorporated herein by reference.

TECHNICAL FIELD

The present invention relates to a data control unit. In particular, the present invention relates to a data control unit which can detect power supply cutoff and can secure time for sufficient backup process.

BACKGROUND ART

Generally, since data currently treated in an electronic circuit disappears with a stop of the current supply resulting from a power failure, battery deterioration, etc., even if it turns ON a power supply again, it cannot resume a process. As a method of solving this, there is a method for backing up stored data to a nonvolatile storage and holding data, when the power supply cutoff is detected. A data hold device and data holding method using a nonvolatile storage device are already disclosed (for example, refer to Patent Literature 1).

In the above-mentioned method, a control device which detects power supply cutoff/turn-on and outputs a signal for request for backup/recovering of data is used toward a controlled system device having a function for performing fixation of the data. Since these control devices process after the power supply cutoff detection, it is necessary to secure another power supply. However, using a battery causes cost increase. In order to solve this problem, “DATA RESTORING METHOD” is proposed as the method of processing by utilizing discharging time of a capacitor (for example, refer to Patent Literature 2).

On the other hand, “PROGRAMMABLE CONTROLLER AND DISPOSAL METHOD AT THE TIME OF POWER OFF FOR THE SAME” for monitoring the power supply lines of two systems (for example, AC 100V side and DC 5V side, etc.) is already disclosed (for example, refer to Patent Literature 3). However, the method disclosed in the Patent Literature 3 does not set up power source monitor time, and is targeted for only at the time of a stop of the device.

Citation List

SUMMARY OF THE INVENTION

Technical Problem

When utilizing the discharging time of a capacitor and performing the process after power supply cutoff, it is useful from the view point of cost to secure needed processing time using the capacitor of small capacity as much as possible. However, in the above-mentioned method, it is necessary to enlarge capacity of a capacitor in order to secure processing time.

When utilizing the discharging time of a capacitor and performing the process after power supply cutoff, since it is necessary to detect power supply cutoff in the range in which the system can operate, it is necessary to set up the voltage level to detect more highly. Usually, for example, in the power supply of 3.3V, when about 3.1V is detected, it is set to regarding as the power supply cutoff etc.

In this case, when the value of power supply voltage is varied by a noise on a power supply line, etc., a possibility of being regarded as the power supply cutoff is high, a useless backup process occurs as a result, and normal operation is prevented.

The purpose of the invention is to provide a data control unit, which can secure the period for sufficient backup process which can be processed, when detecting the power supply cutoff/turn-on and outputting the signal for requesting a backup (data restoring/recovery) of data.

Solution to Problem

According to an aspect of the invention, a data control unit comprises a controlled target circuit which has a nonvolatile storage element and performs a predetermined operation; a power supply voltage converter for converting a primary power supply voltage into a secondary power supply voltage; and a detection/control unit for detecting variation of a potential of each of the primary power supply voltage and the secondary power supply voltage, and outputting a control signal which transfers data in the controlled target circuit to the nonvolatile storage element toward the controlled target circuit.

According to another aspect of the invention, a data control unit comprises a voltage level detection unit for monitoring a voltage level of a power supply; and a control signal generation unit for outputting a control signal for requesting backup of data of a controlled target circuit in the voltage level detection unit when a voltage level of cutoff/turn-on of the power supply is detected.

According to another aspect of the invention, a data control unit comprises a nonvolatile CPU including a nonvolatile storage element; a power supply voltage converter for converting a primary power supply voltage into a secondary power supply voltage; a voltage level detection unit which the primary power supply voltage is inputted and outputs a voltage detection signal; a reset signal generation unit which the secondary power supply voltage is inputted and outputs a reset signal; a control signal generation unit which the voltage detection signal and the reset signal are inputted, and outputs a control signal and a clock enable signal to the nonvolatile CPU; a clock generation device for outputting a clock signal; and a logic unit for generating an output signal for operating the nonvolatile CPU based on the clock enable signal and the clock signal.

According to another aspect of the invention, a data control unit comprises a primary power supply line to which a primary power supply voltage is supplied; a secondary power source line in which a secondary power supply voltage is supplied; a voltage converter which is placed between the primary power supply line and the secondary power source line, and converts the primary power supply voltage into the secondary power supply voltage; a voltage level detection unit which is connected to the primary power supply line, and outputs a voltage level detection signal; a reset signal generation unit which is connected to the secondary power source line, and outputs a reset signal; and a control signal generation unit which receives the voltage level detection signal and the reset signal, and outputs a control signal.

Advantageous Effects of Invention

According to the data control unit of the present invention, when applying to the controlled system which has a power source line of two systems, the capacity of the capacitor for performing the voltage securing after the power supply cutoff can be applied small.

Moreover, according to the data control unit according to the present invention, when the value of the power supply voltage is varied by the noise on the power source line, etc., a useless backup process (data restoring/recovery) can be suppressed.

DESCRIPTION OF EMBODIMENTS

Various embodiments of the present invention will be described with reference to the accompanying drawings. It is to be noted that the same or similar reference numerals are applied to the same or similar parts and elements throughout the drawings, and the description of the same or similar parts and elements will be omitted or simplified. Generally, and as is conventional in the representation of the circuit blocks, it will be appreciated that the various drawings are not drawn to scale from one figure to another nor inside a given figure, and in particular that the circuit diagrams are arbitrarily drawn for facilitating the reading of the drawings. In the following descriptions, numerous specific details are set forth such as specific signal values, etc. to provide a thorough understanding of the present invention. However, it will be obvious to those skilled in the art that the present invention may be practiced without such specific details. In other instances, circuits well-known have been shown in block diagram form in order to not obscure the present invention with unnecessary detail.

The embodiments shown below exemplify an apparatus and a method that are used to implement the technical ideas according to the present invention, and do not limit the technical ideas according to the present invention to those that appear below. These technical ideas, according to the present invention, may receive a variety of modifications that fall within the claims.

First Embodiment

As shown inFIG. 1, a theoretic block configuration of a data control unit12according to a first embodiment of the present invention includes: a primary power supply line VDL1to which a primary power supply voltage VDD1is supplied; a secondary power supply line VDL2to which a secondary power supply voltage VDD2is supplied; a power supply voltage converter14which is placed between the primary power supply line VDL1and the secondary power supply line VDL2, and converts the primary power supply voltage VDD1into the secondary power supply voltage VDD2; and a detection/control unit15placed between the primary power supply line VDL1and the secondary power supply line VDL2. As shown inFIG. 1, a controlled target circuit10connected to the secondary power supply line VDL2is connected also to the primary power supply line VDL1through the detection/control unit15.

At this point, in the case of the data control unit12which uses the power supply of two systems which composes the primary power supply voltage VDD1and the secondary power supply voltage VDD2, it is assumed that the controlled target circuit10which uses the power supply of the system of the secondary power supply voltage VDD2can be operated within the limits of the secondary power supply voltage VDD2±10% VDD2.

An operation of the data control unit12shown inFIG. 1is expressed as shown inFIG. 2.(a) InFIG. 2, before the power supply OFF, the primary power supply voltage VDD1and the secondary power supply voltage VDD2(VDD2<VDD1) are supplied to the primary power supply line VDL1and the secondary power supply line VDL2, respectively.(b) Next, it is considered that the primary power supply voltage VDD1is the power supply OFF because the primary power supply voltage VDD1supplied to the primary power supply line VDL1is detected that it is power supply cutoff (power supply OFF) as compared with VDD1detecting voltage level VLV1level (90% VDD1). As shown inFIG. 2, the voltage drop of the primary power supply voltage VDD1supplied to the primary power supply line VDL1is performed by a predetermined time constant. On the other hand, the voltage drop of the secondary power supply voltage VDD2supplied to the secondary power supply line VDL2is performed by a predetermined time constant, after a fixed state is held.(c) Next, it is considered that the secondary power supply voltage VDD2is the power supply OFF because the secondary power supply voltage VDD2supplied to the secondary power supply line VDL2is detected that it is power supply cutoff (power supply OFF) as compared with VDD2detecting voltage level VLV2(90% VDD2). As a result, the controlled target circuit10is turned to a not-ready state.

A period from the time point of the primary power supply voltage VDD1becoming the VDD1detecting voltage level VLV1and being considered that the primary power supply voltage VDD1is the power supply OFF to the time point of the secondary power supply voltage VDD2becoming the VDD2detecting voltage level VLV2, and the controlled target circuit10is turned to the not-ready state is a period TW1which can process backup, such as data restoring/recovery of the controlled target circuit10after detection of the power supply cutoff.

According to the data control unit according to the first embodiment of the present invention, it becomes possible to detect the power supply cutoff before secondary power supply voltage VDD2of the secondary power supply line VDL2drops by monitoring that the primary power supply voltage VDD1(VDD2<VDD1) of another system whose power supply voltage is higher than the secondary power supply voltage VDD2, and detecting that the primary power supply voltage VDD1is the power supply cutoff (power supply OFF) as compared with the VDD1detecting voltage level VLV1. Therefore, the period TW1which can process the controlled target circuit10after the detection of power supply cutoff can be set up widely.

On the other hand, as shown inFIG. 3, a schematic block configuration of a data control unit according to the comparative example of the first embodiment of the present invention includes: a primary power supply line VDL1to which a primary power supply voltage VDD1is supplied; a secondary power supply line VDL2to which a secondary power supply voltage VDD2is supplied; and a power supply voltage converter4which is placed between the primary power supply line VDL1and the secondary power supply line VDL2, and converts the primary power supply voltage VDD1into the secondary power supply voltage VDD2. As shown inFIG. 3, a controlled target circuit3connected to the secondary power supply line VDL2is not connected to the primary power supply line VDL1.

An operation of the data control unit shown inFIG. 3is expressed as shown inFIG. 4.(a) InFIG. 3, the secondary power supply voltage VDD2is supplied to the secondary power supply line VDL2before the power supply OFF. Similarly, the primary power supply voltage VDD1is supplied to the primary power supply line VDL1.(b) Next, it is considered that the secondary power supply voltage VDD2is the power supply OFF because the secondary power supply voltage VDD2supplied to the secondary power supply line VDL2is detected that it is power supply cutoff (power supply OFF) as compared with VDD2detecting voltage level VLV2level (95% VDD2). As shown inFIG. 4, the voltage drop of the secondary power supply voltage VDD2supplied to the secondary power supply line VDL2is performed by a predetermined time constant.(c) Next, the controlled target circuit3is turned to a not-ready state because the secondary power supply voltage VDD2supplied to the secondary power supply line VDL2is detected that it is power supply cutoff as compared with the VDD2detecting voltage level VLV2(90% VDD2).

A period from the time point of secondary power supply voltage VDD2becoming the VDD2detecting voltage level VLV2(95% VDD2) and being considered that it is the power supply OFF to the time point secondary power supply voltage VDD2becoming the VDD2detecting voltage level VLV2(90% VDD2), and the controlled target circuit3being turned to the not-ready state is a period TW2which can process backup, such as data restoring/recovery of the controlled target circuit3after the detection of power supply cutoff.

As shown inFIG. 4, the operation of the data control unit according to the comparative example monitors only the secondary power supply voltage VDD2of the secondary power supply line VDL2to which the controlled target circuit3is connected, and then detects the power supply cutoff. That is, since the power supply cutoff is detected after the secondary power supply voltage VDD2drops, the time TW2in which the process is possible after the power supply cutoff detection is short.

When monitoring the voltage level of the primary power supply voltage VDD1of another system and detecting the power supply cutoff, the voltage level to detect can be set up low as compared with the case where monitor only secondary power supply voltage VDD2and the power supply cutoff is detected.

When the primary power supply voltage VDD1of another system is monitored, it is considered that the primary power supply voltage VDD1is the power supply OFF, and the detection level is 90% of normal operation voltage (VDD1) by detecting the primary power supply voltage VDD1is power supply cutoff (power supply OFF) as compared with the VDD1detecting voltage level VLV1level (90% VDD1) as mentioned above.

On the other hand, when monitoring the secondary power supply voltage VDD2of the secondary power supply line VDL2, as shown inFIG. 4, the detection level is 95% of the normal operation voltage (VDD2).

Therefore, as for the data control unit according to the first embodiment of the present invention, the probability which can absorb fluctuation of the power supply becomes high compared with the comparative example.

As a detailed schematic block configuration is shown inFIG. 5, the data control unit12according to the first embodiment of the present invention includes: a primary power supply line VDL1to which a primary power supply voltage VDD1is supplied; a secondary power supply line VDL2to which a secondary power supply voltage VDD2is supplied; a power supply voltage converter14which is placed between the primary power supply line VDL1and the secondary power supply line VDL2, and converts the primary power supply voltage VDD1into the secondary power supply voltage VDD2; a voltage level detection unit18which is connected to the primary power supply line VDL1, and outputs a voltage level detection signal VDT; a reset signal generation unit16which is connected to the secondary power supply line VDL2, and outputs a reset signal RSTn; and a control signal generation unit20which receives the voltage level detection signal VDT from the voltage level detection unit18, receives the reset signal RSTn from the reset signal generation unit16, and outputs a control signal CLS.

As shown inFIG. 5, a controlled target circuit10is connected to the secondary power supply line VDL2, and the controlled target circuit10receives the reset signal RSTn from the reset signal generation unit16in the data control unit12, and receives the control signal CLS from the control signal generation unit20in the data control unit12.

Moreover, inFIG. 5, capacitors C1and C2are parasitism capacitors which the primary power supply line VDL1and the secondary power supply line VDL2have, respectively.

FIG. 6shows an operation example of the data control unit shown inFIG. 5. InFIG. 6, power supply variation waveforms of the primary power supply voltage VDD1and the secondary power supply voltage VDD2is shown, and operation waveforms of the reset signal RSTn, the voltage level detection signal VDT, and the control signal CLS is further shown corresponding to these power supply variation waveforms, respectively.(a) First of all, in the period of the time t0to the time t1, a power supply is in OFF state. The reset signal RSTn of negative logic is in ON state, the voltage level detection signal VDT is in OFF state, and the control signal CLS is in a standby state.(b) Next, the power supply is turned ON in the time t1.(c) Next, in the period of the time t1to the time t2, the operation waveforms of the primary power supply voltage VDD1and the secondary power supply voltage VDD2rises, and when the value of the secondary power supply voltage VDD2reaches a reset voltage level VRST, the reset signal RSTn is turned to the OFF state.(d) Next, in the time t2, when the value of the primary power supply voltage VDD1reaches a VDD1detection voltage level VLV1, the voltage level detection signal VDT is turned to the ON state.(e) Next, in the period of the time t2to the time t3, the ON state is held for the primary power supply voltage VDD1and the secondary power supply voltage VDD2. Immediately after the time t2, the control signal CLS is turned from the standby state to the ON state, and the control signal CLS is outputted toward the controlled target circuit10from the control signal generation unit20. Then, the standby state is held.(f) Next, in the period of the time t3to the time t4, when the value of the primary power supply voltage VDD1becomes lower than the VDD1detection voltage level VLV1, and the value of secondary power supply voltage VDD2also drops and is higher than the reset voltage level VRST, although the reset signal RSTn holds the OFF state, the voltage level detection signal VDT is turned to the OFF state. As for the control signal CLS, the standby state is held.(g) Next, in the period of the time t4to the time t5, when the value of the primary power supply voltage VDD1becomes higher than the VDD1detection voltage level VLV1, and the value of the secondary power supply voltage VDD2also rises and is higher than the reset voltage level VRST, although the reset signal RSTn holds the OFF state, the voltage level detection signal VDT is turned to the ON state. As for the control signal CLS, the standby state is held.(h) Next, in the period of the time t5to the time t6, when the value of the primary power supply voltage VDD1becomes lower than the VDD1detection voltage level VLV1, the voltage level detection signal VDT is turned to the OFF state. The control signal CLS is turned to the ON state and the control signal CLS is outputted toward the controlled target circuit10from the control signal generation unit20. Then, the standby state is held.

When the value of the primary power supply voltage VDD1further drops, and the value of the secondary power supply voltage VDD2becomes lower than the reset voltage level VRST, the reset signal RSTn is turned to the ON state.

Further, when the primary power supply voltage VDD1rises, and the value of secondary power supply voltage VDD2becomes higher than reset voltage level VRST, the reset signal RSTn is turned to the OFF state.

Further, when the primary power supply voltage VDD1rises and becomes higher than the VDD1detection voltage level VLV1, as for the reset signal RSTn, the OFF state is held, and the voltage level detection signal VDT is turned to the ON state.(i) Next, in the period of the time t6to the time t7, the ON state is held for both the primary power supply voltage VDD1and the secondary power supply voltage VDD2. Immediately after the time t6, the control signal CLS is turned from the standby state to the ON state, and the control signal CLS is outputted toward the controlled target circuit10from the control signal generation unit20. Then, the standby state is held.(j) Next, the power supply is turned OFF in the time t7.(k) Next, in the period of the time t7to the time t8, the operation waveform of the primary power supply voltage VDD1drops, and, on the other hand, the operation waveform of the secondary power supply voltage VDD2holds a substantially constant value.(l) Next, in the time t8, when the value of the primary power supply voltage VDD1reaches the VDD1detection voltage level VLV1, the reset signal RSTn holds the OFF state, but the voltage level detection signal VDT is turned to the OFF state.(m) Next, in the period of the time t8to the time t9, as for the primary power supply voltage VDD1, the voltage drops by a predetermined time constant, as shown inFIG. 6. On the other hand, as for the secondary power supply voltage VDD2, the voltage drops by a predetermined time constant, after a fixed state is held. Immediately after the time t8, the control signal CLS is turned from the standby state to the ON state, and the control signal CLS is outputted toward the controlled target circuit10from the control signal generation unit20.(n) Next, in the time t9, the controlled target circuit10is turned to the not-ready state because the secondary power supply voltage VDD2reaches the reset voltage level VRSTand it detects power supply cutoff (power supply OFF). Simultaneously, the reset signal RSTn is turned the ON state, the voltage level detection signal VDT holds the OFF state, and the control signal CLS is turned to the standby state.

According to the data control unit according to the first embodiment of the present invention, when applying to the controlled target circuit system which has the power source lines of two systems, since the time constant by the capacitor which the power source line has is not used, the capacity of the capacitor for performing voltage securing after the power supply cutoff can be applied small.

Moreover, according to the data control unit according to the first embodiment of the present invention, when the value of the power supply voltage is varied by the noise on the power source line, etc., a useless backup process (data restoring/recovery) can be suppressed.

Second Embodiment

As shown inFIG. 7, a data control unit12which is a data control unit according to the second embodiment of the present invention and performs a data restoring/recovery control operation includes: a primary power supply line VDL1to which a primary power supply voltage VDD1is supplied; a secondary power source line VDL2to which a secondary power supply voltage VDD2is supplied; a power supply voltage converter14which is placed between the primary power source line VDL1and the secondary power source line VDL2, and converts the primary power supply voltage VDD1into the secondary power supply voltage VDD2; a voltage level detection unit18which is connected to the primary power source line VDL1, and outputs a voltage level detection signal VDT; a reset signal generator16which is connected to the secondary power source line VDL2, and outputs a reset signal RSTn; and a control signal generation unit20which receives the voltage level detection signal VDT from the voltage level detection unit18, receives reset signal RSTn from the reset signal generation unit16, and outputs a data restoring control signal DRCS and a data recovery control signal DSCS.

As shown inFIG. 7, a controlled target circuit30is connected to the secondary power source line VDL2. The controlled target circuit30receives the reset signal RSTn from the reset signal generation unit16in the data control unit12, and receives the data restoring control signal DRCS and the data recovery control signal DSCS from the control signal generation unit20.

The controlled target circuit30includes a main operational unit32, a nonvolatile storage element36, and a data interface control unit34between the main operational unit32and the nonvolatile storage element36, as shown inFIG. 7.

As shown inFIG. 7, the main operational unit32, the data interface control unit34, and the nonvolatile storage element36in the controlled target circuit30receive the reset signal RSTn from the reset signal generation unit16in the data control unit12, and the data interface control unit34receives the data restoring control signal DRCS and the data recovery control signal DSCS from the control signal generation unit20.

Moreover, inFIG. 7, capacitors C1and C2are parasitism capacitors which the primary power source line VDL1and secondary power source line VDL2have, respectively.

(Operating Sequence of Data Control Unit)

An operating sequence of the data control unit12according to the second embodiment of the present invention will be explained using the state transition diagram showing inFIG. 8.

A reset state S1indicates the state where the data control unit12is held while being a reset state, and is not operating.

A power recovery waiting state S2indicates the state where the primary power supply voltage VDD1is standing by until becoming certain specific threshold voltage Vth1(for example, the VDD1detecting voltage level VLV1).

A data recovery signal output state S3indicates the state where the data recovery control signal DSCS toward the controlled target circuit30is sent from the data control unit12, and data is recovered from the nonvolatile storage element36in the controlled target circuit30.

A power source monitor state S4indicates the state where it is checking and monitoring whether or not the primary power supply voltage VDD1is a level which is less than specific threshold voltage Vth1(for example, the VDD1detecting voltage level VLV1).

A data restoring signal output state S5indicates the state where the data restoring control signal DRCS is sent toward the controlled target circuit30from the data control unit12, and data is restored to the nonvolatile storage element36in the controlled target circuit30.

(a) First of all, in the reset state S1, as shown by RSTn=“1”, when the reset signal RSTn is turned to OFF state, the state shifts from the reset state S1to the power recovery waiting state S2.(b) Next, in the power recovery waiting state S2, as shown by RSTn=“0”, when the reset signal RSTn is turned to ON state, the state shifts from the power recovery waiting state S2to the reset state S1.(c) Next, in the power recovery waiting state S2, as shown by VDT=“1”, when the voltage level detection signal VDT is turned to the ON state, the state shifts from the power recovery waiting state S2to the data recovery signal output state S3.(d) Next, the state shifts from the data recovery signal output state S3to the power source monitor state S4.(e) Next, in the power source monitor state S4, as shown by VDT=“0”, when the voltage level detection signal VDT is turned to the OFF state, the state shifts from the power source monitor state S4to the data restoring signal output state S5.(f) Next, the state shifts from the data restoring signal output state S5to the power recovery waiting state S6.(g) Next, in the power recovery waiting state S6, as shown by VDT=“1”, when the voltage level detection signal VDT is turned to the ON state, the state shifts from the power recovery waiting state S6to the data restoring signal output state S5.(h) Next, in the power recovery waiting state S6, as shown by RSTn=“0”, when the reset signal RSTn is turned to the OFF state, the state shifts from the power recovery waiting state S6to the reset state S1.
(Operation Timing Chart)

FIG. 9shows an operation example of the data control unit12shown inFIG. 7. InFIG. 9, the power supply variation waveform of the primary power supply voltage VDD1and the secondary power supply voltage VDD2is shown, and the operation waveform of the reset signal RSTn, the voltage level detection signal VDT, the data recovery control signal DSCS, and the data restoring control signal DRCS is shown, respectively, corresponding to these power supply variation waveforms.(a) First of all, in the period of the time t0to the time t1, a power supply is in OFF state. The reset signal RSTn of negative logic is in ON state, the voltage level detection signal VDT is in OFF state, and the data restoring control signal DRCS and the data recovery control signal DSCS are in OFF state.(b) Next, the power supply is turned ON in the time t1.(c) Next, in the period of the time t1to the time t2, the operation waveforms of the primary power supply voltage VDD1and the secondary power supply voltage VDD2rises, and when the value of the secondary power supply voltage VDD2reaches the reset voltage level VRST, the reset signal RSTn is turned to the OFF state.(d) Next, in the time t2, when the value of the primary power supply voltage VDD1reaches the VDD1detection voltage level VLV1, the voltage level detection signal VDT is turned to the ON state.(e) Next, in the period of the time t2to the time t3, the ON state is held for both the primary power supply voltage VDD1and the secondary power supply voltage VDD2. Immediately after the time t2, the data recovery control signal DSCS is turned from the OFF state to the ON state, and the data recovery control signal DSCS is outputted toward the data interface control unit34of the controlled target circuit30from the control signal generation unit20. Then, the OFF state is held.(f) Next, in the period of the time t3to t4, when the value of the primary power supply voltage VDD1becomes lower than the VDD1detection voltage level VLV1, and the value of the secondary power supply voltage VDD2also drops and is higher than the reset voltage level VRST, although the reset signal RSTn holds the OFF state, the voltage level detection signal VDT is turned to the OFF state. As for the data recovery control signal DSCS, the OFF state is held.(g) Next, in the period of the time t4to the time t5, when the value of the primary power supply voltage VDD1becomes higher than the VDD1detection voltage level VLV1, and the value of the secondary power supply voltage VDD2also rises and is higher than the reset voltage level VRST, although the reset signal RSTn holds the OFF state, the voltage level detection signal VDT is turned to the ON state. The data restoring control signal DRCS and the data recovery control signal DSCS are in the OFF state.(h) Next, in the period of the time t5to the time t6, when the value of the primary power supply voltage VDD1becomes lower than the VDD1detection voltage level VLV1, the voltage level detection signal VDT is turned to the OFF state. At this point, the data restoring control signal DRCS is turned to the ON state, and the data restoring control signal DRCS is outputted toward the data interface control unit34of the controlled target circuit30from the control signal generation unit20. Then, the OFF state is held.

Further, when the value of the primary power supply voltage VDD1drops, and the value of the secondary power supply voltage VDD2becomes lower than the reset voltage level VRST, the reset signal RSTn is turned to the ON state.

Furthermore, when the primary power supply voltage VDD1rises, and the secondary power supply voltage VDD2becomes higher than the reset voltage level VRST, the reset signal RSTn turned to the OFF state.

Furthermore, when the primary power supply voltage VDD1rises and becomes higher than the VDD1detection voltage level VLV1, as for the reset signal RSTn, the OFF state is held, and the voltage level detection signal VDT is turned to the ON state.(i) Next, in the period of the time t6to the time t7, the ON state is held for both the power primary supply voltage VDD1and the secondary power supply voltage VDD2. Immediately after the time t6, the data recovery control signal DSCS is turned from the OFF state to the ON state, and the data recovery control signal DSCS is outputted toward the data interface control unit34of the controlled target circuit30from the control signal generation unit20. Then, the OFF state is held.(j) Next, the power supply is turned OFF in the time t7.(k) Next, in the period of the time t7to the time t8, the operation waveform of the primary power supply voltage VDD1drops, and, on the other hand, the operation waveform of the secondary power supply voltage VDD2holds a substantially constant value.(l) Next, in the time t8, when the value of the primary power supply voltage VDD1reaches the VDD1detection voltage level VLV1, the reset signal RSTn holds OFF state, but the voltage level detection signal VDT is turned to OFF state.(m) Next, in the period of the time t8to the time t9, as the primary power supply voltage VDD1is shown inFIG. 9, the voltage drops by a predetermined time constant. On the other hand, as for the secondary power supply voltage VDD2, the voltage drops by a predetermined time constant after a fixed state is held. Immediately after the time t8, the data restoring control signal DRCS is turned from the OFF state to the ON state, and the data restoring control signal DRCS is outputted toward the data interface control unit34of the controlled target circuit30from the control signal generation unit20.(n) Next, in the time t9, it is considered that the secondary power supply voltage VDD2is the power supply OFF, and the controlled target circuit30is turned to a not-ready state, because the secondary power supply voltage VDD2reaches the reset voltage level VRSTand it detects power supply cutoff (power supply OFF). Simultaneously, the reset signal RSTn is turned to the ON state, the voltage level detection signal VDT holds the OFF state, and both the data restoring control signal DRCS and the data recovery control signal DSCS are turned to the OFF state.

At the time of power recovery, the power recovery state is detected by monitoring the voltage level of the primary power supply voltage VDD1, and detecting that the primary power supply voltage VDD1became VDD1>VLV1as compared with the VDD1detecting voltage level VLV1. As a result, the data recovery control signal DSCS is outputted to the data interface control unit34of the controlled target circuit30from the data control unit12. In the above-mentioned case, the power source monitor of the secondary power supply voltage VDD2is applied only to the reset signal generation unit16of the data control unit12with which the power supply is supplied from the secondary power supply voltage VDD2.

According to the data control unit according to the second embodiment of the present invention, when detecting power supply cutoff/turn-on, and outputting the signal for requesting backup (data restoring/recovery) of data, the period for sufficient the backup process which can be processed can be secured.

According to the data control unit according to the second embodiment of the present invention, when applying to the controlled target circuit system which has the power source line of two system, since the time constant by the capacitor which the power source line has is not used, the capacity of the capacitor for performing voltage securing after the power supply cutoff can be applied small.

Moreover, according to the data control unit according to the second embodiment of the present invention, when the value of the power supply voltage is varied by the noise on the power source line, etc., a useless backup process (data restoring/recovery) can be suppressed.

Third Embodiment

As shown inFIG. 10, a data control unit12which is a data control unit according to a third embodiment of the present invention and applies a nonvolatile CPU40as controlled target includes: a primary power supply line VDL1to which a primary power supply voltage VDD1is supplied; a secondary power source line VDL2to which a secondary power supply voltage VDD2is supplied; a power supply voltage converter14which is placed between the primary power source line VDL1and the secondary power source line VDL2, and converts the primary power supply voltage VDD1into the secondary power supply voltage VDD2; a voltage level detection unit18which is connected to the primary power source line VDL1, and outputs a voltage level detection signal VDT; a reset signal generation unit16which is connected to the secondary power source line VDL2, and outputs a reset signal RSTn; and a control signal generation unit20which receives the voltage level detection signal VDT from the voltage level detection unit18, and receives the reset signal RSTn from the reset signal generation unit16.

The control signal generation unit20outputs a ferroelectric element write signal E1, a normal operation signal E2, a ferroelectric element both ends short circuit signal FRST, and ferroelectric element driving signals PL1and PL2toward the nonvolatile CPU40. Moreover, a clock enable signal CLKEN outputted from the control signal generation unit20and an output signal from a clock generation device42are inputted into an AND gate44, and an output signal of the AND gate44is inputted into the nonvolatile CPU40.

As shown inFIG. 10, the nonvolatile CPU40is connected to the secondary power source line VDL2, and receives the reset signal RSTn from the reset signal generation unit16in the data control unit12, and receives the ferroelectric element write signal E1, the normal operation signal E2, the ferroelectric element both ends short circuit signal FRST, and the ferroelectric element driving signals PL1and PL2from the control signal generation unit20. Moreover, the nonvolatile CPU40receives the clock signal CLK through the AND gate44.

Moreover, inFIG. 10, capacitors C1and C2are parasitism capacitors which the primary power source line VDL1and the secondary power source line VDL2have, respectively.

(Configuration Example of Nonvolatile CPU)

FIG. 11shows a schematic block configuration of the nonvolatile CPU40which applies the data control unit according to the third embodiment of the present invention. As shown inFIG. 11, the nonvolatile CPU40includes: an instruction processing unit102; an arithmetic processing unit110which is connected to the instruction processing unit102and receives an arithmetic control signal ACS from the instruction processing unit102; a calculated result storage unit104which is connected to the arithmetic processing section110and receives an arithmetic output signal z from the arithmetic processing section110; a switch block106which is connected to the calculated result storage unit104and the instruction processing unit102, and supplies an output signal a to the arithmetic processing section110; and a switch block108which is connected to the switch block106and the instruction processing unit102, receives a switch control signal SCS from the instruction processing unit102, and supplies an output signal b to the arithmetic processing section110.

Through a program/data input/output line112, a program/data input terminal112ais connected to the instruction processing unit102, and a program/data output terminal112bis connected to the switch block108.

Moreover, as shown inFIG. 11, a control signal input terminal114band a control signal output terminal114aare connected to the nonvolatile CPU40through a control signal input/output line114.

Moreover, as shown inFIG. 11, the clock signal CLK is supplied to the nonvolatile CPU40through a clock control terminal92, and the ferroelectric element write signal E1, the normal operation signal E2, the ferroelectric element driving signals PL1and PL2, and the ferroelectric element both ends short circuit signal FRST are supplied the nonvolatile CPU40through a nonvolatile operation control terminal94connected to a nonvolatile operation control line100.

Moreover, as shown inFIG. 11, the instruction processing unit102includes a logic circuit block58which has a nonvolatile memory gate50, the calculated result storage unit104includes a logic circuit block54which has a nonvolatile memory gate50, and the arithmetic processing unit110includes a logic circuit block56which has a nonvolatile memory gate50.

(Configuration Example of Nonvolatile Memory Gate)

FIG. 12shows a configuration example of the nonvolatile memory gate50applicable to the nonvolatile CPU40which is a controlled system of the data control unit according to the third embodiment of the present invention. As shown inFIG. 12, the nonvolatile memory gate50includes: first and second nonvolatile storage elements (NVSE)361and362; a first data interface control unit341which is placed adjoining of the first nonvolatile storage element361, and receives an external control signal for data read-out from the first nonvolatile storage element361and the data write to the first nonvolatile storage element361; a second data interface control unit342which is placed adjoining of the second nonvolatile storage element362, and receives an external control signal for data read-out from the second nonvolatile storage element362and the data write to the second nonvolatile storage element362; and a volatile storage element (VSE)35which is placed adjoining of the first data interface control unit341and the second data interface control unit342, receives a data input signal D from a data input terminal, receives a clock signal CLK from a clock input terminal, and outputs a data output signal Q from a data output terminal.

As shown inFIG. 12, the first nonvolatile storage element (NVSE)361includes MOS transistors Q1aand Q1band ferroelectric capacitors51aand51b, and the second nonvolatile storage element (NVSE)362includes MOS transistors Q2aand Q2band ferroelectric capacitors52aand52b.

As shown inFIG. 12, the first data interface control unit341includes an inverter76and a pass switch78, and the second data interface control unit342includes an inverter80and a pass switch82.

An input terminal of the inverter61is connected to a voltage applied terminal of the data input signal D. An output terminal of the inverter61is connected to an input terminal of the inverter60. An output terminal of the inverter60is connected to a first input terminal (1) of the multiplexer84through the pass switch66. Furthermore, the output terminal of the inverter60is connected to an input terminal of the inverter64, and an output terminal of the inverter64is connected to the input terminal of the inverter60through the pass switch62.

An output terminal of the multiplexer84is connected to an input terminal of the inverter72. An output terminal of the inverter72is connected to an input terminal of the inverter74. An output terminal of the inverter74is connected to a pulling out terminal of the data output signal Q. A first input terminal (1) of the multiplexer86is connected to the output terminal of the inverter72. An output terminal of the multiplexer86is connected to an input terminal of the inverter70. An output terminal of the inverter70is connected to the first input terminal (1) of the multiplexer84through the pass switch68.

Thus, as shown inFIG. 12, the nonvolatile memory gate50includes the volatile storage element (VSE)35which has a loop structure unit LOOP (a part surrounded by84,72,86, and70inFIG. 12) holding the inputted data input signal D, using two logical gates (the inverters72and70inFIG. 12) connected to loop shape.

An input terminal of the inverter76is connected to the first input terminal (1) of the multiplexer84. An output terminal of the inverter76is connected to a second input terminal (0) of the multiplexer86through the pass switch78. An input terminal of the inverter80is connected to the first input terminal (1) of the multiplexer86. An output terminal of the inverter80is connected to a second input terminal (0) of the multiplexer84through the pass switch82.

A positive electrode terminal of the ferroelectric capacitor51ais connected to a first plate line, and the ferroelectric element driving signal PL1is supplied. A negative electrode terminal of the ferroelectric capacitor51ais connected to a second input terminal (0) of the multiplexer86. A MOS transistor Q1ais connected between the both terminals of the ferroelectric capacitor51a. A gate of the MOS transistor Q1ais connected to a voltage applied terminal of the ferroelectric element both ends short circuit signal FRST.

A positive electrode terminal of the ferroelectric capacitor51bis connected to the second input terminal (0) of the multiplexer86. A negative electrode terminal of the ferroelectric capacitor51bis connected to a second plate line, and the ferroelectric element driving signal PL2is supplied. A MOS transistor Q1bis connected between the both terminals of the ferroelectric capacitor51b. A gate of the MOS transistor Q1bis connected to the voltage applied terminal of the ferroelectric element both ends short circuit signal FRST.

A positive electrode terminal of the ferroelectric capacitor52ais connected to a first plate line, and the ferroelectric element driving signal PL1is supplied. A negative electrode terminal of the ferroelectric capacitor52ais connected to a second input terminal (0) of the multiplexer84. A MOS transistor Q2ais connected between the both terminals of the ferroelectric capacitor52a. A gate of the MOS transistor Q2ais connected to the voltage applied terminal of the ferroelectric element both ends short circuit signal FRST.

A positive electrode terminal of the ferroelectric capacitor52bis connected to a second input terminal (0) of the multiplexer84. A negative electrode terminal of the ferroelectric capacitor52bis connected to a second plate line, and the ferroelectric element driving signal PL2is supplied. A MOS transistor Q2bis connected between the both terminals of the ferroelectric capacitor52b. A gate of the MOS transistor Q2bis connected to the voltage applied terminal of the ferroelectric element both ends short circuit signal FRST.

In addition, the pass switches62and66are turned ON/OFF according to the clock signal CLK, and the pass switch68is turned ON/OFF according to inverted clock signal CLKB (logic inverted signal of the clock signal CLK), among the above-mentioned components. That is, the pass switches62and66and the pass switch68of each other are turned ON/OFF exclusively (complementary). On the other hand, both the pass switches78and82are turned ON/OFF according to the ferroelectric element write signal E1. As for both the multiplexers84and86, the signal path is switched according to the normal operation signal E2.

Although the drivers for data write (inverters76and80) and the multiplexers84and86are newly needed in the configuration example of the nonvolatile memory gate50shown inFIG. 12, since the occupation area of the nonvolatile memory gate50in the instruction processing unit102of the nonvolatile CPU40, the arithmetic processing unit110, and the calculated result storage unit104is only several percent, there is almost no influence of the increase in size given to whole of the nonvolatile CPU40.

(Operation Timing Chart at the Time of Control of Nonvolatile CPU)

An operation timing chart at the time of control of the nonvolatile CPU40which is an operation waveform of the data control unit according to the third embodiment of the present invention is expressed as shown inFIG. 13. InFIG. 13, the power supply variation waveforms of the primary power supply voltage VDD1and the secondary power supply voltage VDD2are shown. Corresponding to these power supply variation waveforms, the reset signal RSTn, the voltage level detection signal VDT, the clock signal CLK, the clock enable signal CLKEN, the ferroelectric element write signal E1, the normal operation signal E2, the ferroelectric element both ends short circuit signal FRST, the ferroelectric element driving signals PL1and PL2, the volatile data signal VSEDATA, and the nonvolatile data signal NVSEDATA are shown.

In the following description, as shown inFIG. 12, the voltage which appears in the connection node of the ferroelectric capacitors51aand51bis set to V1, the voltage which appears in the connection node of the ferroelectric capacitors52aand52bis set to V2, the voltage which appears in the input terminal of the inverter70is set to V3, the voltage which appears in the output terminal of the inverter70is set to V4, the voltage which appears in the input terminal of the inverter72is set to V5, and the voltage which appears in the output terminal of the inverter72is set to V6.

First of all, a normal operation will be explained.(a) During the period T1to the time point W1shown by the time t0to the time t1, a power supply is in ON state. The reset signal RSTn of negative logic is in OFF state, and the voltage level detection signal VDT is in ON state. In the predetermined time t01during the time t0to the time t1, when the power supply is turned OFF, although the voltage of the primary power supply voltage VDD1drops by a predetermined time constant, the secondary power supply voltage VDD2is still a fixed state.

The nonvolatile CPU40is in a normal operation state. Since the ferroelectric element both ends short circuit signal FRST is set to “H (high-level)”, the MOS transistors Q1a, Q1b,Q2a, and Q2bare turned ON, and between each both terminals of the ferroelectric capacitors51a,51b,52a, and52bis short-circuited, it is in the state where no voltage is applied to these ferroelectric capacitors51a,51b,52a, and52b. In addition, the ferroelectric element driving signals PL1and PL2applied to the first plate line and the second plate line are all set to “L (low level)”.

Moreover, till the point in time W1, since the ferroelectric element write signal E1is set to “L” and the pass switch78and the pass switch82are turned OFF, each driver for data write (inverters76and82in the example ofFIG. 12) is invalid.

Moreover, till the point in time W1, since the normal operation signal E2is set to “H” and the first input terminal (1) of the multiplexer84and the multiplexer86is selected, the normal loop is formed in the loop structure unit LOOP (the part surrounded by84,72,86, and70inFIG. 12).

In the volatile storage element35, when the clock signal CLK is high-level, the inverter61is turned OFF, the pass switch62is turned ON, the pass switch66is turned ON, and the pass switch68is turned OFF. Therefore, in the loop composed of the inverter60and the inverter64, when the clock signal CLK changes from the low level to the high level, the imported data input signal D is held. And, in the loop structure unit (84,72,86,70), the data is passed in that condition and the data output signal Q is outputted from the volatile storage element35.

On the other hand, when the clock signal CLK is the low level, in the loop structure unit (84,72,86,70), the data input signal D imported when the clock signal CLK changed from the high level to the low level is held, and the data output signal Q is outputted.

—Data Restoring Operation to Ferroelectric Element—

Next, a data restoring operation to the ferroelectric element will be explained.(b) In the time t1, when the value of the primary power supply voltage VDD1reaches the VDD1detection voltage level VLV1, the voltage level detection signal VDT is turned OFF. As for the reset signal RSTn, the ON state is held.(c) In the period T2of the time points W1to W3shown by the time t1to the time t3, and the period T3of the time points W3to W4shown by the time t3to the time t4, the nonvolatile CPU40is in a data restoring state, and a data write operation to the ferroelectric element in the nonvolatile memory gate50is executed.

The clock signal CLK is set to “L” and the inverted clock signal CLKB is set to “H”. Therefore, the pass switch66is turned OFF and the pass switch68is turned ON.

In particular, in the period of the time points W2to W3shown by the time t2to the time t3, a data write operation from the volatile storage element (VSE)35to the nonvolatile storage elements (NVSE)361and362is executed. This data write operation is indicated by the arrow A from the volatile data signal VSEDATA to the nonvolatile data signal NVSEDATA.

Moreover, in the time points W1to W3, the ferroelectric element both ends short circuit signal FRST is set to “L”, the MOS transistors Q1a, Q1b, Q2a, and Q2bare turned OFF, and it is in the state in which the voltage impression toward the ferroelectric capacitors51a,51b,52a, and52bis possible.

Moreover, in the time points W1to W3, the ferroelectric element write signal E1is set to “H”, and the pass switch78and the pass switch82are turned ON. Therefore, each driver for data write (inverters76and82in the example ofFIG. 12) is validated.

In addition, in the time points W1to W3, since the normal operation signal E2is set to “H” and the first input terminal (1) of the multiplexer84and the multiplexer86is selected similarly till then, the normal loop is formed in the loop structure unit LOOP (a part surrounded by84,72,86, and70inFIG. 12).

Moreover, in the time points W1to W2, the ferroelectric element driving signal PL1applied to the first plate line and the ferroelectric element driving signal PL2applied to the second plate line are set to “L”, and the ferroelectric element driving signals PL1and PL2is set to “H”. That is, the same pulse voltage is applied toward the first plate line and the second plate line. The residual polarization state inside the ferroelectric capacitor is set to either the inverted state/non-inverted state by impression of such the pulse voltage.

More specifically based on the example ofFIG. 12, at the time W1, since the output signal Q is “H”, the node voltage V1is set to “L”, and the node voltage V2is set to “H”. Therefore, in the time points W1to W2, while the ferroelectric element driving signal PL1applied to the first plate line and the ferroelectric element driving signal PL2applied to the second plate line are set to “L”, it is in the state where the voltage is not applied between the both terminals of the ferroelectric capacitors51aand51b, is in the state where the voltage of negative polarity is applied between the both terminals of the ferroelectric capacitor52a, and is in the state where the voltage of positive polarity is applied between the both terminals of the ferroelectric capacitor52b.

On the other hand, in the time points W2to W3, while the ferroelectric element driving signal PL1applied to the first plate line and the ferroelectric element driving signal PL2applied to the second plate line are set to “H”, it is in the state where the voltage is not applied between the both terminals of the ferroelectric capacitors52aand52b, is in the state where the voltage of positive polarity is applied between the both terminals of the ferroelectric capacitor51a, and is in the state where the voltage of negative polarity is applied between the both terminals of the ferroelectric capacitor51b.

Thus, the residual polarization state inside the ferroelectric element is set to either the inverted state/non-inverted state by applying the pulse voltage toward the first plate line and the second plate line. In addition, between the ferroelectric capacitors51aand51band between the ferroelectric capacitors52aand52b, the mutual residual polarization state becomes reverse. Moreover, between the ferroelectric capacitors51aand52aand between the ferroelectric capacitors51band52b, the mutual residual polarization state also becomes reverse.(d) In the period T3of the time points W3to W4shown by the time t3to the time t4, it is in a power supply cutoff waiting state. In the time point W3, since the ferroelectric element both ends short circuit signal FRST is set to “1” again, the MOS transistors Q1a, Q1b, Q2a, and Q2bare turned ON, and between each both terminals of the ferroelectric capacitors51a,51b,52a, and52bis short-circuited, it is in the state where no voltage is applied to these ferroelectric capacitors51a,51b,52a, and52b. At this time, each of the ferroelectric element driving signal PL1applied to the first plate line and the ferroelectric element driving signal PL2applied to the second plate line are set to “L”.

Moreover, in time point W3, since the ferroelectric element write signal E1is again set to “L”, and the pass switch78and the pass switch82are turned OFF, each driver for data write (inverters76and80in the example ofFIG. 12) is invalid. In addition, although it is unquestioned about the normal operation signal E2, it is set to “L” in the example ofFIG. 13.(e) Next, in the period T4of the time points W4to W6shown by the time t4to the time t6, it is in a power supply cutoff state. That is, at the time point W4shown by the time t4, the secondary power supply voltage VDD2reaches the reset voltage level VRST. Furthermore, when the value of the primary power supply voltage VDD1drops, and the value of the secondary power supply voltage VDD2becomes lower than the reset voltage level VRST, the nonvolatile CPU40is in the power supply cutoff state. The reset signal RSTn of negative logic is turned to the ON state, the voltage level detection signal VDT is turned to the OFF state, and the ferroelectric element write signal E1, the normal operation signal E2, and the ferroelectric element driving signals PL1and PL2are turned to the OFF state. In particular, the nonvolatile CPU40connected to the secondary power source line VDL2is turned to the power OFF state in the predetermined time t41in the time t4to the time t5, and the nonvolatile CPU40is turned to the power OFF state during the time t41to the time t42.

The ferroelectric element both ends short circuit signal FRST is maintained by “H” from time point W3, the MOS transistors Q1a, Q1b, Q2a, and Q2bare turned ON, and between each both terminals of the ferroelectric capacitors51a,51b,52a, and52bare short-circuited. Therefore, since it is in the state where no voltage is applied to the ferroelectric capacitors51a,51b,52a, and52b, even when it is a case where the voltage variation occurs at the time of the power supply cutoff, the voltage which is not aimed to the ferroelectric capacitors51a,51b,52a, and52bis not applied, thereby it becomes possible to avoid data deformation.

—Data Recovery Operation from Ferroelectric Element—

Next, a data recovery operation from the ferroelectric element will be explained.(f) The power supply is turned ON in the time t42. The operation waveform of the primary power supply voltage VDD1and the secondary power supply voltage VDD2rises, and when the value of the secondary power supply voltage VDD2reaches the reset voltage level VRST, the reset signal RSTn is turned OFF.(g) The time points R1to R5shown by the time t5to the time t9, the clock signal CLK is set to “L” and the inverted clock signal CLKB is set to “H”. Therefore, the pass switch66is turned OFF and the pass switch68is turned ON. In addition, at the time point R1, each of the ferroelectric element driving signal PL1applied to the first plate line and the ferroelectric element driving signal PL2applied to the second plate line are set to “L”.(h) In the period T5of the time points of R2to R3shown by the time t6to the time t7, it is in a power recovery waiting state. At the time point R2, each the ferroelectric element write signal E1and the normal operation signal E2are in the state of “L” (that is, a state where the driver for data write becomes invalid and the normal loop is formed in the loop structure unit LOOP), and the secondary power supply voltage VDD2reaches the reset voltage level VRST. Furthermore, when the value of the primary power supply voltage VDD1rises, and the value of the secondary power supply voltage VDD2becomes higher than the reset voltage level VRST, the nonvolatile CPU40is in the power recovery waiting state.(i) Next, in the time t7, when the value of the primary power supply voltage VDD1reaches the VDD1detection voltage level VLV1, the voltage level detection signal VDT is turned ON. At this point, the data recovery operation is started.(j) Next, in the period of the time t7to the time t10, the ON state is held for the primary power supply voltage VDD1and the secondary power supply voltage VDD2. Immediately after the time t7, the ferroelectric element driving signal PL1is turned from the OFF state to the ON state, and data reading operation shown by the arrow B from the nonvolatile data signal NVSEDATA to the volatile data signal VSEDATA is executed.

In particular, in the period T6at the time points R3to R5, data read-out from the nonvolatile storage elements (NVSE)361and362to the volatile storage element (VSE)35is executed.

At the time point R3, whereas the ferroelectric element both ends short circuit signal FRST is set to “L”, the MOS transistors Q1a, Q1b, Q2a, and Q2bare turned OFF, and it is turned to the state in which the voltage impression toward the ferroelectric capacitors51a,51b,52a, and52bis possible, while the ferroelectric element driving signal PL2applied to the second plate line is maintained by “L”, the ferroelectric element driving signal PL1applied to the first plate line is set to “H”. By impression of such the pulse voltage, the voltage signal corresponding to the residual polarization state in the ferroelectric capacitor appears as the node voltage V1and the node voltage V2.

More specifically based on the example ofFIG. 12, a comparatively low voltage signal (the logic is hereinafter referred to “WL (Weak Low)”) appears as the node voltage V1, and a comparatively high voltage signal (the logic is hereinafter referred to “WH (Weak Hi)”) appears as the node voltage V2. That is, it becomes a shape which the voltage difference according to the difference of the residual polarization state in the ferroelectric capacitor occurs, between the node voltage V1and the node voltage V2.

At this time, at the time points R3to R4, since the normal operation signal E2is set to “L”, and the multiplexer84and the second input terminal (0) of the multiplexer86is selected, the logic of the node voltage V3is turns to WL, and the logic of the node voltage V4is turns to WH. Moreover, the logic of the node voltage V5is turned to WH, and the logic of the node voltage V6is turned to WL. Thus, at the time points R3to R4, the node voltages V1to V6of each part is still in an unstable state (state where logic inverted in the inverter76and the inverter80is not performed thoroughly, and the output logic does not become “L”/“H” securely).

At the time point R4, since the normal operation signal E2is set to “H” and the multiplexer84and the first input terminal (1) of the multiplexer86is selected, the normal loop is formed in the loop structure unit LOOP. With the change of such a signal path, the output terminal (logic: WH) of the inverter70and the input terminal (logic: WH) of the inverter72are connected, and the output terminal (logic: WL) of the inverter72and the input terminal (logic: WL) of the inverter70are connected. Therefore, mismatching is not occurred in the signal logic (WH/WL) of each node. Hereinafter, while the normal loop is formed in the loop structure unit LOOP, the inverter72tends to pull up the output logic to “H” in response to the input of the logic WL, and the inverter70tends to pull down the output logic to “L” in response to the input of the logic WH. As a result, the output logic of the inverter72is settled by “L” from the unstable logic WL, and the output logic of the inverter70is settled by “H” from the unstable logic WH.

At the time point R4, it becomes a shape where the signal (potential difference of the node voltage V1and the node voltage V2) read from the ferroelectric capacitor is amplified in the loop structure unit LOOP, with the loop structure unit LOOP being applied into the normal loop, and the held data before power supply cutoff is recovered.

At the time point R5, since the ferroelectric element both ends short circuit signal FRST is again set to “H”, the MOS transistors Q1a, Q1b, Q2a, and Q2bare turned ON, and between each both terminals of the ferroelectric capacitors51a,51b,52a, and52bis short-circuited, it is in the state where no voltage is applied to these ferroelectric capacitors51a,51b,52a, and52b. At this time, each of the ferroelectric element driving signal PL1applied to the first plate line and the ferroelectric element driving signal PL2applied to the second plate line are set to “L”. Therefore, it recovers to the normal operation state as well as the time point W1or before.

According to the third embodiment of the present invention, also in the case where the controlled system is applied to the nonvolatile CPU, when detecting the power supply cutoff/turn-on and outputting the signal for requesting the backup (data restoring/recovery) of data, the data control unit which can secure the period for sufficient backup process which can be processed can be provided.

According to the data control unit according to the third embodiment of the present invention, when the controlled system is applied to the nonvolatile CPU which has a power source line of two systems, the capacity of the capacitor for performing voltage securing after the power supply cutoff can be applied small.

Moreover, according to the data control unit according to the third embodiment of the present invention, when the controlled system is applied to the nonvolatile CPU and the value of power supply voltage is varied by the noise on the power source line, etc., a useless backup process (data restoring/recovery) can be suppressed.

Other Embodiments

While the present invention is described in accordance with the aforementioned embodiments, it should not be understood that the description and drawings that configure part of this disclosure are to limit the present invention. This disclosure makes clear a variety of alternative embodiments, working examples, and operational techniques for those skilled in the art.

Accordingly, the technical scope of the present invention is defined by the claims that appear appropriate from the above explanation, as well as by the spirit of the invention. Various modifications will become possible for those skilled in the art after receiving the teachings of the present disclosure without departing from the scope thereof.

INDUSTRIAL APPLICABILITY

Since the data control unit of the present invention can detect the voltage level of power supply cutoff/turn-on and sufficient time for backup (data restoring/recovery) of the data of the controlled target circuit can be secured, the data control unit of the present invention can be applied to wide fields as the controlled target circuit, such as processors, such as a logic operation circuit, a logic unit, CPU, MPU, and DSP, and a game machine, and a mobile computing device, and becomes advantageous in respect of the data protection at the time of battery exhaustion, etc. in particular in battery powered devices.

Reference Signs List

2,3,10,30; controlled target circuit4; power supply voltage converter12; data control unit14; power supply voltage converter15; detection/Control unit16; reset signal generation unit18; voltage level detection unit20; control signal generation unit32; main operational unit34,341,342; data interface control unit35; volatile storage element (VSE)36,361,362; nonvolatile storage element(NVSE)40; nonvolatile CPU42; clock generation device44; AND gate50; nonvolatile memory gate51a,51b,52a,52b;ferroelectric capacitor54,56,58; logic circuit block60,61,64,70,72,74,76,80; inverter62,66,68,78,82; pass switch84,86; multiplexer102; instruction processing unit104; calculated result storage unit106,108; switch block110; arithmetic processing unit112; program/data input/output line112a;program/data input terminal112b;program/data output terminal114; control signal input/output line114a;control signal output terminal114b;control signal input terminalD; data input signalQ; data output signalCLK; clock signalCLKB; inverted clock signalE1; ferroelectric element write signalE2; normal operation signalFRST; ferroelectric element both ends short circuit signalPL1, PL2; ferroelectric element driving signalVDD; power supply voltageVDD1; primary power supply voltageVDD2; secondary power supply voltageVDL1; primary power supply lineVDL2; secondary power supply lineTW1, TW2; periodRSTn; reset signal (negative logic)VDT; voltage level detection signalCLS; control signalVLV1; VDD1detecting voltage levelVLV2; VDD2detecting voltage levelVRST; reset voltage levelC1, C2; capacitorDRCS; data restoring control signalDSCS; data recovery control signalACS; arithmetic control signal