METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE

A method of manufacturing a semiconductor device includes forming a stacked structure by stacking gate layers and interlayer insulating layers alternately on a substrate; and forming a channel structure passing through the stacked structure in a vertical direction, wherein the forming a channel structure includes forming an opening by etching the stacked structure; forming a gate insulating layer covering a side surface of the opening; forming a variable resistive material layer on the gate insulating layer; changing an oxygen vacancy concentration in a region of the variable resistive material layer by performing a plasma treatment process or an annealing process on the variable resistive material layer; forming a core insulating pattern covering the variable resistive material layer and filling at least a portion of the opening; and forming a pad pattern on the core insulating pattern.

CROSS-REFERENCE TO RELATED APPLICATION(S)

This application claims benefit of priority to Korean Patent Application No. 10-2022-0000680 filed on Jan. 4, 2022 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety.

BACKGROUND

Some example embodiments relate to a method of manufacturing or fabricating a semiconductor device and/or a semiconductor device.

In a data storage system requiring data storage, a semiconductor device capable of storing high-capacity data is required or desired. Accordingly, a method of increasing data storage capacity of a semiconductor device is being researched. For example, as a method for increasing the data storage capacity of a semiconductor device, a semiconductor device including three-dimensionally arranged memory cells, instead of two-dimensionally arranged memory cells, has been proposed.

SUMMARY

Some example embodiments may provide a method of manufacturing a semiconductor device having improved electrical characteristics and/or a simplified manufacturing process.

Alternatively or additionally, some example embodiments may provide a semiconductor device having improved electrical characteristics and a simplified manufacturing process, and/or a data storage system including the same.

According some example embodiments, a method of manufacturing a semiconductor device includes forming a stacked structure by stacking gate layers and interlayer insulating layers alternately on a substrate; and forming a channel structure passing through the stacked structure in a vertical direction, wherein the forming a channel structure includes forming an opening by etching the stacked structure; forming a gate insulating layer covering at least a side surface of the opening; forming a variable resistive material layer on the gate insulating layer; changing an oxygen vacancy concentration in a region of the variable resistive material layer by performing one or both of a plasma treatment process or an annealing process on the variable resistive material layer; forming a core insulating pattern that covers the variable resistive material layer and fills at least a portion of the opening, after the performing the one or both of plasma treatment process and the annealing process; and forming a pad pattern on the core insulating pattern.

According to some example embodiments, a method of manufacturing a semiconductor device includes forming a stacked structure by stacking gate layers and interlayer insulating layers alternately on a substrate; and forming a channel structure passing through the stacked structure in a vertical direction. The forming a channel structure includes forming an opening by etching the stacked structure; forming a gate insulating layer covering at least a side surface of the opening; forming a variable resistive material layer on the gate insulating layer and including a first region and a second region; changing an oxygen vacancy concentration in a first subregion of the first region or a second subregion of the second region; forming a core insulating pattern filling at least a portion of the opening; and forming a pad pattern on the core insulating pattern.

According to some example embodiments, a method of manufacturing a semiconductor device includes forming a stacked structure by stacking gate layers and interlayer insulating layers alternately on a substrate; and forming a channel structure passing through the stacked structure in a vertical direction. The forming a channel structure includes forming an opening by etching the stacked structure; forming a gate insulating layer in the opening; forming a variable resistive material capping layer filling the opening and contacting the gate insulating layer; etching a central region of the variable resistive material capping layer to form a variable resistive material layer extending along a side surface of the gate insulation layer and having a specific thickness from the side surface of the gate insulation layer; changing an oxygen vacancy concentration in a region of the variable resistive material layer by performing one or both of a plasma treatment process or an annealing process on the variable resistive material layer; forming a core insulating pattern that covers the variable resistive material layer and that fills at least a portion of the opening, after performing the one or both of the plasma treatment process or the annealing process; and forming a pad pattern on the core insulating pattern.

According to some example embodiments, a semiconductor device includes a substrate; gate electrodes stacked on the substrate and spaced apart from each other in a vertical direction; and a channel structure in an opening that passes through the gate electrodes in the vertical direction. The channel structure includes a core insulating pattern spaced apart from a side surface of the opening, a gate insulating layer contacting the gate electrodes at the side surface of the opening, and a variable resistive material layer between the gate insulating layer and the core insulating pattern. The variable resistive material layer includes a channel region including oxygen vacancies at a first concentration, and an data storage region including oxygen vacancies at a second concentration, less than the first concentration, wherein the channel region is in contact with the gate insulating layer and extends along a side surface of the gate insulating layer, and the data storage region is in contact with the core insulating pattern and extends along a side surface of the core insulating pattern.

According to some example embodiments, a data storage system includes a semiconductor storage device including a lower substrate, a lower structure including circuit elements on the lower substrate, an upper structure on the lower structure, an input/output pad electrically connected to the circuit elements; and a controller electrically connected to the semiconductor storage device through the input/output pad and configured to control the semiconductor storage device, wherein the semiconductor storage device includes an upper substrate; gate electrodes stacked on the upper substrate spaced apart from each other in a vertical direction; and a channel structure in an opening that passes through the gate electrodes in the vertical direction. The channel structure includes a core insulating pattern spaced apart from a side surface of the opening, a gate insulating layer contacting the gate electrodes at the side surface of the opening, and a variable resistive material layer between the gate insulating layer and the core insulating pattern. The variable resistive material layer includes a channel region including oxygen vacancies at a first concentration, and an data storage region including oxygen vacancies at a second concentration, less than the first concentration, wherein the channel region is in contact with the gate insulating layer and extends along a side surface of the gate insulating layer, and the data storage region is in contact with the core insulating pattern and extends along a side surface of the core insulating pattern.

DETAILED DESCRIPTION

Hereinafter, various example embodiments of inventive concepts will be described with reference to the accompanying drawings.

FIG.1is a schematic plan view of a semiconductor device according to various example embodiments.

FIG.2is a schematic cross-sectional view of a semiconductor device according to various example embodiments.FIG.2illustrates a cross-sectional view taken along line I-I′ ofFIG.1.

FIG.3is a partially enlarged view of a portion of a semiconductor device according to various example embodiments.FIG.3illustrates an enlarged view of portion ‘A’ ofFIG.2.

Referring toFIGS.1to3, a semiconductor device100may include a first structure1including a lower substrate10and a second structure2including an upper substrate101. The second structure2may be disposed on the first structure1. The first structure1may be or correspond to a region in which a peripheral circuit region of the semiconductor device100is disposed, and the peripheral circuit region may include one or more of a column decoder, a row decoder, a page buffer, other peripheral circuits, a redundancy circuit, and the like. The second structure2may be a region in which memory cells of the semiconductor device100are disposed, and may include gate electrodes130, channel structures CH, and the like. The semiconductor device100may be or may include a cell-over-peri (COP) semiconductor device; however, example embodiments are not limited thereto.

The first structure1may include a lower substrate10, device isolation layers15sdefining an active region15aon the lower substrate10, circuit elements20disposed on the lower substrate10, a lower interconnection structure30electrically connected to the circuit elements20, and a lower insulating layer40.

The lower substrate10may include a semiconductor material, for example, one or more of a group IV semiconductor, a group III-V compound semiconductor, or a group II-VI compound semiconductor. The lower substrate10may be provided as a bulk wafer or an epitaxial layer. The lower substrate10may be doped, e.g. may be lightly doped with one or more of boron, arsenic, or phosphorus; however, example embodiments are not limited thereto. The lower substrate10may be disposed below an upper substrate101. The device isolation layers15smay be disposed in the lower substrate10, and source/drain regions22including impurities such as one or more of boron, phosphorus, or arsenic may be disposed in a portion of the active region15a.

The circuit elements20may each include a transistor such as a planar transistor including a source/drain region22, a circuit gate dielectric layer24, and a circuit gate electrode26. The source/drain regions22may be disposed on both sides of the circuit gate electrode26in the active region15a. The circuit gate dielectric layer24may be disposed between the active region15aand the circuit gate electrode26. Spacer layers28may be disposed on both sides of the circuit gate electrode26. The circuit gate electrode26may include, for example, a material layer such as one or more of tungsten (W), titanium (Ti), tantalum (Ta), tungsten nitride (WN), titanium nitride (TiN), tantalum nitride (TaN), polysilicon, or a metal-semiconductor compound.

The lower interconnection structure30may be electrically connected to the circuit elements20. The lower interconnection structure30may include a lower contact32and a lower interconnection34. A portion of lower contacts32may extend in a Z-direction to be connected to the source/drain regions22. The lower contact32may electrically connect the lower interconnections34disposed on different levels to each other. The lower interconnection structure30may include a conductive material, for example, a metal material such as one or more of tungsten (W), titanium (Ti), tantalum (Ta), copper (Cu), aluminum (Al), cobalt (Co), molybdenum (Mo), ruthenium (Ru), or the like. A barrier layer formed of a material such as one or more of tungsten nitride (WN), titanium (Ti), titanium nitride (TiN), or the like may be disposed on bottom and side surfaces of the lower interconnection structure30. The number of layers and arrangement of the lower contacts32and the lower interconnections34, constituting the lower interconnection structure30, may be variously changed. At least a portion of the lower interconnections34may include a pad layer to which a plurality of through-contact plugs extending downwardly from the second structure2are directly connected. In some example embodiments, the plurality of through-contact plugs may be disposed to pass through a through-region formed in a stacked structure ST of the second structure2.

The lower insulating layer40may be disposed to cover the lower substrate10, the circuit elements20, and the lower interconnection structure30. The lower insulating layer40may be formed of an insulating material such as silicon oxide and/or silicon nitride. The lower insulating layer40may include a plurality of insulating layers. The lower insulating layer40may include an etch stop layer formed of silicon nitride.

The second structure2may include an upper substrate101on the first structure1, a stacked structure ST including gate electrodes130spaced apart and stacked on the upper substrate101, first separation patterns MS passing through the stacked structure ST and separating the gate electrodes130, channel structures CH passing through the stacked structure ST, a second separation pattern SS separating upper gate electrodes130U among the gate electrodes130between the first separation patterns MS, and bit lines180disposed on the stacked structure ST. The second structure2may further include interlayer insulating layers120with which the gate electrodes130are alternately stacked and forming a portion of the stacked structure ST, and contact plugs170and upper insulating layers191and192, arranged between the channel structures CH and the bit lines180.

The upper substrate101may include a semiconductor material, for example, one or more of a group IV semiconductor, a group III-V compound semiconductor, or a group II-VI compound semiconductor. The upper substrate101may include, for example, a polysilicon layer having N-type or P-type conductivity. The upper substrate101may include an impurity region contacting the channel structure CH.

The gate electrodes130may be stacked on the upper substrate101to be spaced apart from each other in the Z-direction, and may form a portion of the stacked structure ST. The gate electrodes130may extend in the X-direction. The gate electrodes130may include a lower gate electrode130L forming a gate of a ground select transistor, memory gate electrodes130M forming a plurality of memory cells, and upper gate electrodes130U forming gates of string select transistors. The number of the memory gate electrodes130M constituting the memory cells may be determined according to capacity of the semiconductor device100. In some example embodiments, the number of the gate electrodes constituting the string select transistor may be one or two or more, and the number of the gate electrodes constituting the ground select transistor may be one or two or more.

The gate electrodes130may be vertically spaced apart and stacked on the upper substrate101, and although not illustrated, may extend by different lengths in a Y-direction to form a stepped structure or a stair structure. The gate electrodes130may have pad regions in which a lower gate electrode among the gate electrodes130is extended to be longer than an upper gate electrode among the gate electrodes130due to the stepped structure. Gate contact plugs may be connected to the gate electrodes130through the pad regions of the gate electrodes130. In some example embodiments, the gate contact plugs may be electrically connected to the circuit elements20of the first structure1through through-contact plugs passing through a through-region disposed in the stacked structure ST.

The gate electrodes130may be arranged to be separated from each other in the Y-direction by the first separation patterns MS extending in an X-direction. The gate electrodes130between a pair of first separation patterns MS may form one memory block, but a scope of the memory block is not limited thereto. The gate electrodes130may include a first layer and a second layer, respectively. The first layer may cover upper and lower surfaces of the second layer, and may extend between the channel structures CH and the second layer. The first layer may include a high-k material such as aluminum oxide (AlO) or the like, and the second layer may include at least one of titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), tungsten (W), or tungsten nitride (WN). In some example embodiments, the gate electrodes130may include polysilicon and/or a metal-semiconductor compound.

The interlayer insulating layers120may be disposed between the gate electrodes130, and may form the stacked structure ST. Like the gate electrodes130, the interlayer insulating layers120may be spaced apart from each other in the Z-direction, and may be disposed to extend in the X-direction. The interlayer insulating layers120may include an insulating material such as silicon oxide. A portion of the interlayer insulating layers120may have different thicknesses. For example, an uppermost interlayer insulating layer120, among the interlayer insulating layers120, may have a thickness, greater than a thickness of each of the other interlayer insulating layers120.

The first separation patterns MS may be disposed to pass through the gate electrodes130of the stacked structure ST in the Z-direction, and extend in the X-direction. First separation patterns MS adjacent in the Y-direction may be disposed parallel to each other. The first separation patterns MS may entirely pass through the gate electrodes130of the stacked structure ST in the Z-direction, to contact the upper substrate101. The first separation patterns MS may be formed of an insulating material, for example, silicon oxide. In some example embodiments, each of the first separation patterns MS may include a core pattern including a conductive material and contacting the upper substrate101, and a separation insulation pattern covering a side surface of the core pattern and including an insulating material.

As illustrated inFIG.1, the channel structures CH may form a memory cell string, and may be disposed to be spaced apart from each other while forming rows and columns. The channel structures CH may be disposed to form a grid pattern between the first separation patterns MS or may be disposed to form a zigzag shape in a direction. The channel structures CH may be disposed in an opening OP passing through the stacked structure ST in the Z-direction. The channel structures CH may have a pillar shape, and may have inclined side surfaces, narrower in width, as they approach the upper substrate101according to an aspect ratio. The channel structures CH may have a tapered pillar profile.

Each of the channel structures CH may include a gate insulating layer141, a variable resistive material layer142, a core insulating pattern145, and a pad pattern149. The variable resistive material layer142may be formed in an annular shape to cover or surround an outer side surface of the core insulating pattern145. The gate insulating layer141may be formed in an annular shape to cover or surround an outer side surface of the variable resistive material layer142. The gate insulating layer141, the variable resistive material layer142, and the core insulating pattern145may be sequentially disposed from side surfaces of the gate electrodes130. For example, the gate insulating layer141may be in contact with the gate electrodes130on a side surface of the opening OP, the core insulating pattern145may be spaced apart from the side surface of the opening OP, and the variable resistive material layer142may be disposed between the gate insulating layer141and the core insulating pattern145.

The gate insulating layer141may be disposed between the gate electrodes130and the variable resistive material layer142. The gate insulating layer141may extend along the side surface of the opening OP. The gate insulating layer141may extend from a level lower than the lower gate electrode130L to a level higher than the upper gate electrode130U. An upper surface of the gate insulating layer141may be coplanar with or substantially coplanar with an upper surface of the pad pattern149. The gate insulating layer141may be formed of silicon oxide or doped silicon oxide such as nitrogen-doped silicon oxide.

The variable resistive material layer142may cover side and lower surfaces of the core insulating pattern145, and may be in contact with the upper substrate101. The variable resistive material layer142may be formed as a single layer including a transition metal oxide, and may include regions having different oxygen vacancy concentrations. For example, the variable resistive material layer142may include a first region142a(corresponding to a ‘channel region’ of a memory cell transistor, and, hereinafter, referred to as a ‘channel region’) having an oxygen vacancy of a first concentration, and a second region142b(corresponding to an ‘data storage region’ of the memory cell transistor, and, hereinafter, referred to as a ‘data storage region’) having an oxygen vacancy of a second concentration, different from the first concentration. The second concentration may be lower than the first concentration. As used herein, an “oxygen vacancy” may refer to a point, such as a point defect, in a unit cell of a crystalline lattice of atoms in an oxide crystal that is absent of an oxygen atom. An oxygen vacancy concentration may indicate a concentration in units of vacancies per volume of unit cells in an oxide crystalline lattice that are void of oxygen.

An oxygen vacancy concentration in the channel region142aof the variable resistive material layer142may be greater than an oxygen vacancy concentration in the data storage region142bof the variable resistive material layer142. The channel region142amay be in contact with the gate insulating layer141, and the data storage region142bmay be in contact with the core insulating pattern145. In the drawings, a line between the channel region142aand the data storage region142bis illustrated for convenience of explanation, but an interface between the channel region142aand the data storage region142bmay not exist. Since the channel region142aand the data storage region142bmay be regions formed of the same material, resistance therebetween may be relatively lower than contact resistance due to an interface formed between them, formed of different materials.

A lower portion of the channel region142aof the variable resistive material layer142may be in contact with the upper substrate101. Since the channel region142aof the variable resistive material layer142corresponds to a channel region of the memory cell transistor as described above, a further channel layer may not be disposed between the variable resistive material layer142and the gate insulating layer141. For example, the variable resistive material layer142may be in contact with the gate insulating layer141without interposing a polysilicon layer between the variable resistive material layer142and the gate insulating layer141. For example, the channel region142aof the variable resistive material layer142may not include polysilicon. The channel region142aof the variable resistive material layer142may be a region in which a portion of the variable resistive material layer142is subjected to a plasma treatment process and/or an annealing process to increase an oxygen vacancy concentration. The annealing process may be or may include a thermal annealing process and/or a laser annealing process. Since a portion of the variable resistive material layer142may be post-processed to change electrical characteristics, and may be used as the channel region142aof the memory cell transistor, an operation of forming a further channel layer including a material, different from the variable resistive material layer142, may be omitted. There may be a reduction in fabrication time, and/or an improvement in yield and/or reliability and/or efficiency, from the annealing process and/or the plasma treating process.

The data storage region142bof the variable resistive material layer142may be a region in which a portion of the variable resistive material layer142is subjected to a plasma treatment process and/or an annealing process to decrease an oxygen vacancy concentration.

The data storage region142bof the variable resistive material layer142may have different resistance, according to a set state and a reset state in operating the semiconductor device100. For example, among word lines WL, a program operation may turn off (OFF) selected word line WLa and may turn on (ON) unselected word lines WLb1and WL1b2. In this case, a current indicated by reference numeral CP inFIG.3may sequentially flow along a portion of the channel region141afacing a first unselected word line WLb1located above the selected word line WLa, the selected word line WLa facing the selected word line WLa, and a portion of the channel region141afacing a second unselected word line WLb2located below the selected word line WLa. A dotted line indicated by reference numeral CP inFIG.3may indicate a current flow during a program operation. For example, the current flow CP during the program operation may flow along the portion of the channel region142afacing the first unselected word line WLb1, may shift to the data storage region142bfacing the selected word line WLa, may shift to the portion of the channel region142afacing the second unselected word line WLb2, and may flow along the portion of the channel region142a. As a current flows along the data storage region142bfacing the selected word line WLa, resistance of the data storage region142bmay be changed, and a portion of the data storage region142bfacing the selected word line WLa may be in a set state. By such a program operation, resistance of a portion of the data storage region142bfacing the selected word line WLa may be locally lowered.

An erase operation may turn off the selected word line WLa, similarly to the program operation, and may turn off the unselected word lines WLb1and WLb2, but may flow a current in a direction, opposite to the current flow during the above-described program operation, to change a magnetic field, to change a portion of the data storage region142bfacing the selected word line WLa in a reset state. Due to the erase operation, resistance of the portion of the data storage region142bfacing the selected word line WLa may be locally increased.

The core insulating pattern145may have a prismatic shape or a cylindrical shape extending in the vertical direction (Z). The core insulating pattern145may be disposed in a region including a center of the channel structure CH. An upper surface of the core insulating pattern145may be in contact with the pad pattern149. The core insulating pattern145may be formed of at least one of silicon oxide, silicon nitride, or silicon oxynitride.

The pad pattern149may be disposed on the core insulating pattern145, and may be in contact with an upper portion of the variable resistive material layer142. The pad pattern149may electrically connect the variable resistive material layer142to the bit lines180. The pad pattern149may be formed of doped polysilicon, for example, doped polysilicon having N-type conductivity.

The second separation pattern SS may extend between the first separation patterns MS in the X-direction. The second separation pattern SS may pass through the upper gate electrode130U, among the gate electrodes130, in the Z-direction, to separate them from each other in the Y-direction. The number of and/or thicknesses of upper gate electrodes130U, separated by the second separation pattern SS, may be variously changed in some example embodiments. The upper gate electrodes130U, separated by the second separation pattern SS, may form different string select lines. The second separation pattern SS may include an insulating material, for example, silicon oxide, silicon nitride, or silicon oxynitride.

The contact plugs170may be disposed between the channel structures CH and the bit lines180. The contact plugs170may be respectively connected to the channel pad149. The contact plugs170may be connected to the bit lines180. The contact plugs170may pass through at least one of the upper insulating layers191and192, for example, a first upper insulating layer191and a second upper insulating layer192in the Z-direction. In some example embodiments, a plurality of studs connected to the contact plugs170may be further disposed between one channel structure CH and one bit line180.

The contact plugs170may include a conductive pattern and a barrier layer covering side and bottom surfaces of the conductive pattern. The barrier layer may include, for example, at least one of titanium (Ti), titanium nitride (TiN), tantalum (Ta), or tantalum nitride (TaN). The conductive pattern may include a metal material, for example, at least one of tungsten (W), titanium (Ti), copper (Cu), cobalt (Co), aluminum (Al), or alloys thereof. In some example embodiments, the contact plugs170may be formed as a plurality of plug structures.

The bit lines180may be disposed on the stacked structure ST and the channel structures CH, and may extend in the Y-direction. The bit lines180may be electrically connected to the circuit elements20of the first structure1through through-contact plugs. The bit lines180may be electrically connected to the variable resistive material layer141.

The bit lines180may include a conductive pattern and a barrier layer covering side and bottom surfaces of the conductive pattern. The barrier layer may include, for example, at least one of titanium (Ti), titanium nitride (TiN), tantalum (Ta), or tantalum nitride (TaN). The conductive pattern may include a metal material, for example, at least one of tungsten (W), titanium (Ti), copper (Cu), cobalt (Co), aluminum (Al), or alloys thereof.

The upper insulating layers191and192may be disposed on the stacked structure ST. The upper insulating layers191and192may include a first upper insulating layer191and a second upper insulating layer192, sequentially stacked on the stacked structure ST. The upper insulating layers191and192may be formed of an insulating material such as silicon oxide.

FIGS.4A to4Dare graphs illustrating an oxygen vacancy concentration in a variable resistive material layer of a semiconductor device according to various example embodiments.

Referring toFIG.4A, a variable resistive material layer142may have an oxygen vacancy concentration varying a concentration in a stepped profile, e.g. in a piecewise linear profile. For example, an oxygen vacancy concentration of the variable resistive material layer142in a width direction may decrease in a step profile, in a direction from a gate insulating layer141toward a core insulating pattern145. For example, a channel region142aof the variable resistive material layer142may have an oxygen vacancy at a first concentration C1, and a data storage region142bof the variable resistive material layer142may have an oxygen vacancy at a second concentration C2, lower than the first concentration C1. The first concentration C1may be a constant concentration according to a change in thickness of the channel region142a, and the second concentration C2may be a constant concentration according to a change in thickness of the data storage region142b.

Referring toFIGS.4B and4C, a variable resistive material layer142may have an oxygen vacancy concentration that gradually changes, e.g. that decreases in a polynomial or exponential manner or a piecewise polynomial or exponential manner, and an oxygen vacancy concentration in a data storage region142bof the variable resistive material layer142may be lower than an oxygen vacancy concentration in a channel region142aof the variable resistive material layer142.

Referring toFIG.4B, for example, the oxygen vacancy concentration in the channel region142aof the variable resistive material layer142may increase as the channel region142aapproaches a gate insulating layer141, and the oxygen vacancy concentration in the data storage region142bmay decrease as the data storage region142bapproaches a core insulating pattern145. For example, in the channel region142a, an oxygen vacancy concentration of a portion of the channel region142aadjacent to the gate insulating layer141may be higher than an oxygen vacancy concentration of a portion of the channel region142aadjacent to the data storage region142b. For example, in the data storage region142b, an oxygen vacancy concentration of a portion of the data storage region142badjacent to the channel region142amay be higher than an oxygen vacancy concentration of a portion of the data storage region142badjacent to the core insulating pattern145.

Referring toFIG.4C, for example, an oxygen vacancy concentration of a channel region142aof a variable resistive material layer142may decrease as the channel region142aapproaches a gate insulating layer141, and an oxygen vacancy concentration of the data storage region142bmay increase as the data storage region142bapproaches a core insulating pattern145. For example, in the channel region142a, an oxygen vacancy concentration of a portion of the channel region142aadjacent to the gate insulating layer141may be higher than an oxygen vacancy concentration of a portion of the channel region142aadjacent to the data storage region142b. For example, in the data storage region142b, an oxygen vacancy concentration of a portion of the data storage region142badjacent to the channel region142amay be lower than an oxygen vacancy concentration of a portion the data storage region142badjacent to the core insulating pattern145.

Referring toFIG.4D, a variable resistive material layer142may have an oxygen vacancy concentration that constantly changes. For example, in the variable resistive material layer142, the oxygen vacancy concentration may gradually decrease from a channel region142ato a data storage region142b. Therefore, the data storage region142bmay have a lower oxygen vacancy concentration, compared to the channel region142a.

FIG.5Ais a partially enlarged view of a portion of a semiconductor device according to various example embodiments.

FIG.5Bis a graph illustrating an oxygen vacancy concentration in a variable resistive material layer of a semiconductor device according to various example embodiments.

Referring toFIGS.5A and5B, a data storage region142bof a variable resistive material layer142may include a first data storage region142b1adjacent to a channel region142aand a second data storage regions142b2adjacent to a core insulating pattern145. The first data storage region142b1may have oxygen vacancies at a second concentration C2, lower than a first concentration C1of the channel region142a, and the second data storage region142b2may have oxygen vacancies at a third concentration C3, lower than the first concentration C1and higher than the second concentration C2. InFIG.5B, the variable resistive material layer142is illustrated as having an oxygen vacancy concentration varying a concentration in a stepped profile, but the variable resistance layer142may have an oxygen vacancy concentration that gradually changes, as illustrated inFIGS.4B and4C, or may have an oxygen vacancy concentration that constantly changes, as illustrated inFIG.4D.

FIGS.6A and6Bare partially enlarged views illustrating a portion of a semiconductor device according to various example embodiments.FIGS.6A and6Billustrate a region corresponding to a region indicated by portion ‘B’ ofFIG.2.

Referring toFIG.6A, a channel structure CHa may further include an epitaxial layer107. The epitaxial layer107may be disposed to contact an upper substrate101on a lower end of the channel structure Cha, and may be disposed adjacent to a side surface of at least one gate electrode130. The epitaxial layer107may be disposed in a recessed region of the upper substrate101. An upper surface of the epitaxial layer107may be higher than an upper surface of a lower gate electrode130L, and may be lower than the lower surface of a gate electrode130on the lower gate electrode130L, but the present inventive concept is not limited thereto. The epitaxial layer107may be connected to a variable resistive material layer142through the upper surface of the epitaxial layer107. An insulating layer109may be further disposed between the epitaxial layer107and the lower gate electrode130L adjacent to the epitaxial layer107.

Referring toFIG.6B, a semiconductor device100may further include a first horizontal conductive layer102disposed along an upper surface of an upper substrate101and a second horizontal conductive layer103extending along an upper surface of the first horizontal conductive layer102. The first horizontal conductive layer102and the second horizontal conductive layer103may be disposed between the upper substrate101and a stacked structure ST. At least a portion of the first horizontal conductive layer102and at least a portion of the second horizontal conductive layer103may be formed of polysilicon having N-type conductivity. The first horizontal conductive layer102may pass through a gate insulating layer141below a channel structure CHb, and may be in contact with a side surface of a variable resistive material layer142.

FIGS.7to9are schematic cross-sectional views of a semiconductor device according to various example embodiments.

Referring toFIG.7, gate electrodes130of a semiconductor device100A may include a first gate portion131adjacent to channel structures CH and a second gate portion132adjacent to first isolation patterns MS, respectively. The first gate portion131may surround side surfaces of the channel structures CH.

The first gate portion131may be formed of doped polysilicon, and the second gate portion132may be formed of a metal-semiconductor compound (e.g., one or more of WSi, TiSi, or the like), a metal nitride (e.g., WN, TiN, or the like), and/or a metal (e.g., W or the like).

Each of the gate electrodes130may include the first and second gate portions131and132, to improve electrical characteristics of the gate electrodes130. Therefore, in some example embodiments, a semiconductor device having improved electrical characteristics may be provided.

Referring toFIG.8, in a semiconductor device100B, a stacked structure ST of a second structure2may include a lower stacked structure and an upper stacked structure on the lower stacked structure, and channel structures CHc may include a lower channel structure passing through the lower stacked structure and an upper channel structure passing through the upper stacked structure, respectively. A variable resistive material layer142of the first channel structure and a variable resistive material layer142of the second channel structure may be connected to each other. In the connection region, a gate insulating layer141and a variable resistive material layer142may be respectively bent. For example, a side surface of the variable resistive material layer142may include a bent portion due to a difference in width in the connection region, and a side slope may be changed. Example embodiments a case in which a stacked structure is a double stacked structure, and inventive concepts may also include a multi-stacked structure that may be a double or more stacked structure. Furthermore a number of gate electrodes130below the bent portion may be the same as, or greater than, or less than a number of gate electrodes above the bent portion.

Referring toFIG.9, a first structure1and a second structure2of a semiconductor device100C may be bonded to each other through a bonding structure without a further adhesive layer. The second structure2of the semiconductor device100C is illustrated as vertically inverting the second structure2of the semiconductor device100ofFIG.2. The semiconductor device100C may further include an upper bonding pad165and a lower bonding pad65. The second structure2may further include a third upper insulating layer193. The upper bonding pad165may be electrically connected to a bit line180through an upper bonding via163, and the lower bonding pad65may be electrically connected to circuit elements20through a lower via63. The lower bonding pad65and the upper bonding pad165may include, for example, tungsten (W), aluminum (Al), copper (Cu), tungsten nitride (WN), tantalum nitride (TaN), or titanium nitride (TiN), or a combination thereof, respectively. The lower bonding pad65and the upper bonding pad165may function as bonding layers for bonding the first structure1and the second structure2. In addition, the lower bonding pad65and the upper bonding pad165may provide an electrical connection path between the first structure1and the second structure2. The lower bonding pad65and the upper bonding pad165may be bonded by copper(Cu)-to-copper(Cu) bonding. Alternatively or in addition to the copper-to-copper bonding, the first structure1and the second structure2may be bonded by dielectric-to-dielectric bonding. The dielectric-to-dielectric bonding may form, for example, a portion of each of the third upper insulating layer193and a lower insulating layer40, and may be a bonding by dielectric layers surrounding the upper bonding pad165and the lower bonding pad65.

FIGS.10A to11Bare flowcharts illustrating a method of manufacturing a semiconductor device according to various example embodiments.

FIGS.12to23are schematic views illustrating a method of manufacturing a semiconductor device according to various example embodiments.

Referring toFIGS.10A,10B, and12, a first structure1including circuit elements20and a lower interconnection structure30may be formed on a lower substrate10, an upper substrate101may be formed on the first structure1, sacrificial layers110and interlayer insulating layers120may be alternately stacked on the upper substrate101(S10), and openings OP passing through the sacrificial layers110and the interlayer insulating layers120may be formed (S21).

First, device isolation layers15smay be formed in a lower substrate10, and a circuit gate dielectric layer24and a circuit gate electrode26may be sequentially formed on an active region15a. The device isolation layers15smay be formed by, for example, a shallow trench isolation (STI) process. The circuit gate dielectric layer24may be formed of silicon oxide, and the circuit gate electrode26may be formed as at least one of a polysilicon layer or a metal-semiconductor compound layer, but is not limited thereto. Next, a spacer layer28may be formed on both sidewalls of the circuit gate dielectric layer24and both sidewalls of the circuit gate electrode26, and source/drain regions22may be formed in the active region15a. In some example embodiments, the spacer layer28may be formed as a plurality of layers. The source/drain regions22may be formed by performing an ion implantation process and/or an in-situ dopant deposition process; however, example embodiments are not limited thereto.

Lower contacts32and lower interconnections34of the lower interconnection structure30may be formed by partially forming a lower insulating layer40, etching and removing a portion thereof, and filling a conductive material therein, or may be formed by depositing a conductive material, patterning the same, and filling a portion removed by the patterning with a portion of a lower insulating layer40.

The lower insulating layer40may be formed as a plurality of insulating layers. The lower insulating layer40may be partially formed in each operation of forming the lower interconnection structure30, and may be further partially formed on an uppermost lower interconnection34, to be finally prepared to cover the circuit elements20and the lower interconnection structure30.

The upper substrate101may be formed of, for example, polysilicon. Polysilicon constituting the upper substrate101may include impurities, which may be implanted and/or may be incorporated during deposition of the polysilicon.

The sacrificial layers110may be partially replaced by a gate electrodes130(refer toFIG.2) by a subsequent process. The sacrificial layers110may be formed of a material, different from that of the interlayer insulating layers120, and may be formed of a material that may be etched with etching selectivity for the interlayer insulating layers120under specific etching conditions. For example, the interlayer insulating layer120may be formed of at least one of silicon oxide or silicon nitride, and the sacrificial layers110may be formed of a material, different from that of the interlayer insulating layer120, selected from silicon, silicon oxide, silicon carbide, and silicon nitride.

The sacrificial layer110may be referred to as a ‘gate layer,’ and when the sacrificial layer110includes polysilicon, the gate layer including polysilicon may function as a gate electrode, and a process of replacing the sacrificial layer110with a subsequent gate electrode130may be omitted. In some example embodiments, thicknesses of the interlayer insulating layers120may not all be the same. Thicknesses of the interlayer insulating layers120and the sacrificial layers110and/or the number of layers constituting the interlayer insulating layers120and the sacrificial layers110may be variously changed from those illustrated. A preliminary stacked structure may be formed by stacking the sacrificial layers110and the interlayer insulating layers120. After the preliminary stacked structure is formed, second separation patterns MS2passing through a portion of upper sacrificial layers110, among the sacrificial layers110, may be formed.

Openings OP may be formed by anisotropically etching the preliminary stacked structure. Due to a height of the preliminary stacked structure, side surfaces of the openings OP may be inclined with respect to an upper surface of the upper substrate101.

Referring toFIGS.10B,11A,13A, and14, a gate insulating layer141covering the side surfaces of the openings OP may be formed (S22), and a variable resistive material layer142P may be formed. (S23), and the forming a variable resistive material layer142P (S23) may include forming a first variable resistive material layer142_1(S23A) and forming a second variable resistive material layer142_2on the first variable resistive material layer142_1(S23B).

The gate insulating layer141may be formed to conformally cover side and lower surfaces of the openings OP. The gate insulating layer141may be partially formed even on a level higher than an uppermost interlayer insulating layer120. After partially opening a lower portion of the gate insulating layer141, the first variable resistive material layer142_1and the second variable resistive material layer142_2may be conformally formed. The first variable resistive material layer142_1may be in contact with the upper substrate101, and may be in contact with the gate insulating layer141. The first variable resistive material layer142_1and the second variable resistive material layer142_2may be formed of the same material, and may be formed by, for example, performing an atomic layer deposition (ALD) process. The first variable resistive material layer142_1and the second variable resistive material layer142_2may be formed, for example, at the same time and/or in the same process chamber; however, example embodiments are not limited thereto. Although the first variable resistive material layer141_1and the second variable resistive material layer142_2are illustrated as respective layers for convenience of description, but may be substantially formed as a single layer (142P).

Referring toFIGS.10B,11B,13B, and14, a gate insulating layer141covering the side surfaces of the openings OP may be formed (S22), and a variable resistive material layer142P may be formed. (S23), and the forming a variable resistive material layer142P (S23) may include forming a variable resistive material capping layer142′ filling the opening OP and contacting the gate insulating layer141(S23A′), and etching the variable resistive material capping layer142′ (S23B′). The gate insulating layer141may be formed to conformally cover side and lower surfaces of the openings OP. The gate insulating layer141may be partially formed even on a level higher than an uppermost interlayer insulating layer120. After partially opening a lower portion of the gate insulating layer141, for example, a chemical vapor deposition (CVD) process or a sputtering process may be performed to form the variable resistive material capping layer142′. The variable resistive material capping layer142′ may fill the opening OP, and may be in contact with the gate insulating layer141in the opening OP. A central region of the variable resistive material capping layer142′ may be etched, to form the variable resistive material layer142P extending along a side surface of the gate insulating layer141and having a specific thickness from the side surface of the gate insulating layer141. The specific thickness may be predetermined, or alternatively may be dynamically or variably determined.

As inFIG.13A-14, a method of forming the variable resistive material layer142P before performing the following post-processing process, as described above, may include the manufacturing processes ofFIGS.13A and14, or may include the manufacturing processesFIGS.13B and14.

Referring toFIGS.10B and14, a plasma treatment process PP may be performed on the variable resistive material layer142P to change an oxygen vacancy concentration in a portion of the variable resistive material layer142P (S24), to form a variable resistive material layer142including a channel region142aand a data storage region142b. The plasma treatment process PP may be performed using a source gas including one or more of oxygen (02), hydrogen (H2), silane (SiH4), argon (Ar), or the like. For example, a plasma treatment process PP using argon (Ar) may be performed, which may reduce an oxygen vacancy concentration in a portion of a surface of the variable resistive material layer142P. Through this, a structure in which an oxygen vacancy concentration in the channel region142ais relatively lower than an oxygen vacancy concentration in the data storage region142bmay be formed.

For example, an annealing process may be performed, instead of or in addition to the plasma processing process PP, to change an oxygen vacancy concentration in a portion of the variable resistive material layer142P. For example, an annealing process may be performed to reduce an oxygen vacancy concentration in a region from a surface of the variable resistive material layer142P. The annealing process may be or may include a thermal annealing process and/or a laser annealing process.

For example, referring toFIG.13Atogether, before forming the first variable resistive material layer142_1and forming the second variable resistive material layer142_2, a plasma processing process PP and/or an annealing process on the first variable resistive material layer142_1may be performed to change the oxygen vacancy concentration. Thereafter, after forming the second variable resistive material layer142_2, an additional plasma treatment process PP and/or an additional annealing process may be performed or may not be performed.

A change in oxygen vacancy concentration in a width direction of the variable resistive material layer142, e.g., an oxygen vacancy concentration profile or an oxygen vacancy concentration distribution, may be determined, for example, by one or more of Energy Dispersive X-ray Spectroscopy (EDS), X-ray Photoelectron Spectrometry (XPS), Secondary Ion Mass Spectrometry (SIMS), Rutherford back-scattering (RBS), Raman spectroscopy, Mott-Schottky impedance spectroscopy, x-ray crystallography (XRD), or the like.

Referring toFIGS.10B and16to19, a core insulating pattern145may be formed to cover the variable resistive material layer142and fill at least a portion of the opening OP (S25). The forming a core insulating pattern145(S25) may include forming a first core insulating layer145A, partially removing the first core insulating layer145A and the variable resistive material layer142from upper portions thereof, respectively, filling the opening OP with a second core insulating layer145B, and forming the core insulating pattern145by partially removing the first and second core insulating layers145A and145B from upper portions thereof.

First, the first core insulating layer145A may be formed to conformally cover an inner side surface of the variable resistive material layer142in the opening OP. Next, the first core insulating layer145A and the variable resistive material layer142may be partially removed from upper portions thereof, to lower heights of upper ends thereof, compared to an upper end of the gate insulating layer141. Next, the second core insulating layer145B may fill an entirely unfilled space of the opening OP. An interface between the first core insulating layer145A and the second core insulating layer145B may be seen, depending on process conditions, but may not be clearly distinguished. Next, a planarization process such as a chemical mechanical planarization process and/or an etch-back process may be performed to remove a portion of the second core insulating layer145B covering an upper end of the gate insulating layer141. A space for forming a subsequent pad pattern149may be formed in the opening OP by partially removing the first and second core insulating layers145A and145B from upper portions thereof.

Referring toFIGS.10A,10B,20, and21, a pad pattern149may be formed on the core insulating pattern145(S26). The forming a pad pattern149(S26) may include forming a capping material layer149P on the core insulating pattern145, and performing a planarization process such as a chemical mechanical planarization process and/or an etch-back process to remove a portion of the capping material layer149P disposed on the upper end of the gate insulating layer141. During the planarization process, a portion of the gate insulating layer141on an uppermost interlayer insulating layer120may also be removed. Therefore, channel structures CH passing through the preliminary stacked structure may be formed (S20).

Referring toFIG.22, separation openings T passing through the sacrificial layers110and the interlayer insulating layers120may be formed, and the sacrificial layers110may be removed through the separation openings T to form horizontal openings LT.

First, after the channel structure CH is formed, a first upper insulating layer191may be formed on the channel structure CH. The separation openings T may be formed by forming a mask layer and anisotropically etching the first upper insulating layer191, the sacrificial layers110, and the interlayer insulating layers120, using a photolithography process. The separation openings T may be formed in a trench shape extending in the X-direction, and may expose the upper substrate101from lower ends of the separation openings T.

Next, the sacrificial layers110may be selectively removed with respect to the interlayer insulating layers120and the first upper insulating layer191through the separation openings T. Therefore, a plurality of horizontal openings LT may be formed between the interlayer insulating layers120.

Referring toFIGS.10A and23, gate electrodes130may be formed in the horizontal openings LT, and first separation patterns MS may be formed in the separation openings T (S30).

First, the gate electrodes130may be formed by filling the horizontal openings LT, formed by removing the sacrificial layers110through the separation openings T, with a conductive material. Therefore, a stacked structure ST in which the interlayer insulating layers120and the gate electrodes130are alternately stacked may be formed. The forming the gate electrodes130may include sequentially forming a first layer and a second layer.

Next, the first separation patterns MS may be formed by filling the separation openings T with an insulating material. In some example embodiments, a separation insulating pattern including an insulating material and a conductive core pattern including a conductive material may be sequentially formed in the separation openings T. The conductive core pattern may be formed to be spaced apart from the gate electrodes130and to contact the upper substrate101.

Next, a second upper insulating layer192may be formed, and contact plugs170and bit lines180may be formed (S40), to manufacture the semiconductor device100ofFIGS.1to3.

FIG.24is a view schematically illustrating a data storage system including semiconductor devices according to various example embodiments.

Referring toFIG.24, a data storage system1000may include a semiconductor device1100and a controller1200electrically connected to the semiconductor device1100. The data storage system1000may be a storage device including one or more semiconductor devices1100, or an electronic device including the storage device. For example, the data storage system1000may be a solid state drive device (SSD), a universal serial bus (USB), a computing system, a medical device, or a communication device, including one or more semiconductor devices1100.

The semiconductor device1100may be or may include a non-volatile memory device, for example, a NAND flash memory device described above with reference toFIGS.1to9. The semiconductor device1100may include a first structure1100F, and a second structure1100S on the first structure1100F. In some example embodiments, the first structure1100F may be disposed next to the second structure1100S. The first structure1100F may be a peripheral circuit structure including a decoder circuit1110, a page buffer1120, and a logic circuit1130. The second structure1100S may be a memory cell structure including bit lines BL, a common source line CSL, word lines WL, first and second gate upper lines UL1and UL2, first and second gate lower lines LL1and LL2, and memory cell strings CSTR between each of the bit lines BL and the common source line CSL.

In the second structure1100S, each of the memory cell strings CSTR may include lower transistors LT1and LT2adjacent to the common source line CSL, upper transistors UT1and UT2adjacent to each of the bit lines BL, and a plurality of memory cell transistors MCT disposed between each of the lower transistors LT1and LT2and each of the upper transistors UT1and UT2. The number of lower transistors LT1and LT2and/or the number of upper transistors UT1and UT2may be variously changed according to various example embodiments, and may be the same, or different, from each other.

In some example embodiments, each of the upper transistors UT1and UT2may include a string select transistor, and each of the lower transistors LT1and LT2may include a ground select transistor. The lower gate lines LL1and LL2may be gate electrodes of the lower transistors LT1and LT2, respectively. The word lines WL may be gate electrodes of the memory cell transistors MCT, and the upper gate lines UL1and UL2may be gate electrodes of the upper transistors UT1and UT2, respectively.

In some example embodiments, the lower transistors LT1and LT2may include a lower erase control transistor LT1and a ground select transistor LT2, connected in series. The upper transistors UT1and UT2may include a string select transistor UT1and an upper erase control transistor UT2, connected in series. At least one of the lower erase control transistor LT1or the upper erase control transistor UT2may be used for an erase operation of erasing data stored in the memory cell transistors MCT using a gate-induced-drain-leakage (GIDL) phenomenon.

The common source line CSL, the first and second gate lower lines LL1and LL2, the word lines WL, and the first and second gate upper lines UL1and UL2may be electrically connected to the decoder circuit1110through first connection interconnections1115extending from the first structure1100F into the second structure1100S. The bit lines BL may be electrically connected to the page buffer1120through second connection interconnections1125extending from the first structure1100F into the second structure1100S.

In the first structure1100F, the decoder circuit1110and the page buffer1120may perform a control operation on at least one selected memory cell transistor among the plurality of memory cell transistors MCT. The decoder circuit1110and the page buffer1120may be controlled by the logic circuit1130. The semiconductor device1100may communicate with the controller1200through an input/output pad1101electrically connected to the logic circuit1130. The input/output pad1101may be electrically connected to the logic circuit1130through input/output connection interconnections1135extending from the first structure1100F into the second structure1100S.

The controller1200may include a processor1210, a NAND controller1220, and a host interface1230. According to some example embodiments, the data storage system1000may include a plurality of semiconductor devices1100, and in this case, the controller1200may control the plurality of semiconductor devices1100.

The processor1210may control an overall operation of the data storage system1000including the controller1200. The processor1210may operate according to a predetermined or alternatively variably determined firmware, and may access to the semiconductor device1100by controlling the NAND controller1220. The NAND controller1220may include a NAND interface1221processing communications with the semiconductor device1100. A control command for controlling the semiconductor device1100, data to be written to the memory cell transistors MCT of the semiconductor device1100, data to be read from the memory cell transistors MCT of the semiconductor device1100, or the like may be transmitted through the NAND interface1221. The host interface1230may provide a communication function between the data storage system1000and an external host. When a control command is received from the external host through the host interface1230, the processor1210may control the semiconductor device1100in response to the control command.

FIG.25is a perspective view schematically illustrating a data storage system including a semiconductor device according to various example embodiments.

Referring toFIG.25, a data storage system2000according to various example embodiments of inventive concepts may include a main substrate2001, a controller2002mounted on the main substrate2001, a semiconductor package2003, which may be provided as one or more semiconductor packages, and a DRAM2004. The semiconductor package2003and the DRAM2004may be connected to the controller2002by interconnection patterns2005formed on the main substrate2001.

The main substrate2001may include a connector2006including a plurality of pins, which may be coupled to an external host. The number and an arrangement of the plurality of pins in the connector2006may vary according to a communication interface between the data storage system2000and the external host. In some example embodiments, the data storage system2000may be communicated with the external host according to any one interface of a universal serial bus (USB), peripheral component interconnection express (PCI-Express), serial advanced technology attachment (SATA), M-Phy for universal flash storage (UFS), or the like. In some example embodiments, the data storage system2000may be operated by power supplied from the external host through the connector2006. The data storage system2000may further include a power management integrated circuit (PMIC) distributing power, supplied from the external host, to the controller2002and the semiconductor package2003.

The controller2002may write data to the semiconductor package2003or read data from the semiconductor package2003, and may improve an operation speed of the data storage system2000.

The DRAM2004may be or may include a buffer memory reducing a difference in speed between the semiconductor package2003, which may be a data storage space, and the external host. The DRAM2004included in the data storage system2000may also operate as a type of cache memory, and may provide a space temporarily storing data in a control operation on the semiconductor package2003. When the DRAM2004is included in the data storage system2000, the controller2002may further include a DRAM controller controlling the DRAM2004in addition to a NAND controller controlling the semiconductor package2003.

The semiconductor package2003may include first and second semiconductor packages2003aand2003b, spaced apart from each other. Each of the first and second semiconductor packages2003aand2003bmay be a semiconductor package including a plurality of semiconductor chips2200. Each of the first and second semiconductor packages2003aand2003bmay include a package substrate2100, semiconductor chips2200on the package substrate2100, adhesive layers2300disposed on a lower surface of each of the semiconductor chips2200, a connection structure2400electrically connecting each of the semiconductor chips2200and the package substrate2100, and a molding layer2500covering the semiconductor chips2200and the connection structure2400on the package substrate2100.

The package substrate2100may be a printed circuit board including package upper pads2130. Each of the semiconductor chips2200may include an input/output pad2210. The input/output pad2210may correspond to the input/output pad1101ofFIG.24. Each of the semiconductor chips2200may include stacked structures3210and memory channel structures3220. Each of the semiconductor chips2200may include a semiconductor device according to any one of embodiments described above with reference toFIGS.1to9.

In some example embodiments, the connection structure2400may be a bonding wire electrically connecting the input/output pad2210and the upper package pads2130. Therefore, in each of the first and second semiconductor packages2003aand2003b, the semiconductor chips2200may be electrically connected to each other by a bonding wire process, and may be electrically connected to the package upper pads2130of the package substrate2100. According to embodiments, in each of the first and second semiconductor packages2003aand2003b, the semiconductor chips2200may be electrically connected to each other by a connection structure including a through silicon via (TSV), instead of a connection structure2400by a bonding wire process.

In some example embodiments, the controller2002and the semiconductor chips2200may be included in one (1) package. In some example embodiments, the controller2002and the semiconductor chips2200may be mounted on a further interposer substrate, different from the main substrate2001, and the controller2002and the semiconductor chips2200may be connected to each other by an interconnection formed on the interposer substrate.

FIG.26is a cross-sectional view schematically illustrating a semiconductor package according to various example embodiments.FIG.26may illustrate various example embodiments of the semiconductor package2003ofFIG.25, and may conceptually illustrate a region taken along line II-II′ of the semiconductor package2003ofFIG.25.

Referring toFIG.26, in the semiconductor package2003, the package substrate2100may be a printed circuit board. The package substrate2100may include a package substrate body portion2120, package upper pads2130disposed on an upper surface of the package substrate body portion2120(seeFIG.25), lower pads2125disposed on a lower surface of the package substrate body portion2120or exposed from the lower surface, and internal interconnections2135electrically connecting the upper pads2130and the lower pads2125in the package substrate body portion2120. The upper pads2130may be electrically connected to the connection structures2400. The lower pads2125may be connected to the interconnection patterns2005of the main substrate2001of the data storage system2000, as illustrated inFIG.25, through conductive connection portions2800.

Each of or at least some of the semiconductor chips2200may include a semiconductor substrate3010, and a first structure3100and a second structure3200, sequentially stacked on the semiconductor substrate3010. The first structure3100may include a peripheral circuit region including peripheral interconnections3110. The second structure3200may include a common source line3205, a stacked structure3210on the common source line3205, channel structures3220and separation regions3230, passing through the stacked structure3210, bit lines3240electrically connected to the memory channel structures3220, and gate contact plugs3235electrically connected to word lines WL (refer toFIG.24) of the stacked structure3210. As described above with reference toFIGS.1to9, each of the semiconductor chips2200may include a lower substrate10, circuit elements20, an upper substrate101, gate electrodes130, channel structures CH, first separation patterns MS, second separation patterns SS, and bit lines180.

Each of or at least some of the semiconductor chips2200may include a through-interconnection3245electrically connected to the peripheral interconnections3110of the first structure3100and extending into the second structure3200. The through-interconnection3245may disposed outside the stacked structure3210, and may be further disposed to pass through the stacked structure3210. Each of the semiconductor chips2200may further include an input/output pad2210electrically connected to the peripheral interconnections3110of the first structure3100(refer toFIG.25).

A method of manufacturing a semiconductor device having improved electrical characteristics and a simplified manufacturing process, in which a variable resistive material layer includes a channel region having a high oxygen vacancy concentration and a data storage region having a low oxygen vacancy concentration, may be provided.

Various advantages and effects of inventive concepts are not limited to the above, and will be more easily understood in the process of describing specific example embodiments of inventive concepts.

Any of the elements and/or functional blocks disclosed above may include or be implemented in processing circuitry such as hardware including logic circuits; a hardware/software combination such as a processor executing software; or a combination thereof. For example, the processing circuitry more specifically may include, but is not limited to, a central processing unit (CPU), an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field programmable gate array (FPGA), a System-on-Chip (SoC), a programmable logic unit, a microprocessor, application-specific integrated circuit (ASIC), etc. The processing circuitry may include electrical components such as at least one of transistors, resistors, capacitors, etc. The processing circuitry may include electrical components such as logic gates including at least one of AND gates, OR gates, NAND gates, NOT gates, etc.

While various example embodiments have been illustrated and described above, it will be apparent to those skilled in the art that modifications and variations could be made without departing from the scope of inventive concepts as defined by the appended claims. Furthermore example embodiments are not necessarily mutually exclusive with one another. For example, some example embodiments may include one or more features described with reference to one or more figures, and may also include one or more other features described with reference to one or more other figures.