Power aware method and apparatus of video decoder on a multi-core platform

Disclosed is a power aware method and apparatus of video decoder on a multi-core platform. The power aware apparatus comprises a power management unit, and a processor unit having an entropy decoder and a decoder. The processor unit has at least one voltage and at least one frequency. One processor of the multi-core platform performs the entropy decoding for a frame, collects the entropy decoded information, and computes the decompressing time. Based on the computed decompressing time, the processor sets up the voltage and frequency for other or all processors to reduce power consumption for video decoders.

FIELD OF THE INVENTION

The present invention generally relates to a power aware method and apparatus of a video decoder on a multi-core platform.

BACKGROUND OF THE INVENTION

The continuous breakthrough with high density nano fabrication technology and the system-on chip (SoC) design enable a single chip to accommodate a plurality of processing units. The demands for the consumer digital products are the focus of the electronic industry. The popular products in demands include hand-held devices, such as mobile phone, digital camera, portable media player (PMP), and home theater, such as LCD TV, DVD, PVR, RG, and so on. The types of data that need to be processed on all these electronic devices are increasing, including video, audio, and text.

In response to the complex processing demands, the multi-core platform is considered as a promising solution. The multi-core platform not only uses a microprocessor with a reduced instruction set computing (RISC) based micro processing unit (MPU), such as ARM, MIPS, and PowerPC, and a digital signal processing (DSP) unit for processing signals.

Each of these processing units can be an individual multi-core platform, including multi-core RISC-based network processor, such as Broadcom, Freescale, and PMC-Sierra, or multimedia processing with RISC, DSP and even reconfigurable accelerator, such as OMAP(TI), i.Smart (Freescale), Vision (Agere), and PAC(ITRI).

To meet the ever-growing multimedia application, the dual-core processor with a RISC-based MPU and a DSP is gaining popularity. The RISC-based microprocessor, such as ARM, is responsible for the operating system (OS), man-machine interface (MMI) and other routine tasks, while the DSP processor is for executing complex mathematical computing, such as audio coding/decoding, video decoding, and so on.

In other words, the RISC-based microprocessor of the dual core platform performs tasks different from the DSP. The RISC-enhanced DSP may be powerful in DSP, but not in the general RISC processing. The DSP is optimized for real-time signal processing, which may require less power consumption and computing cost than the RISC processing. In addition, the pipeline of the DSP, although can perform complex signal processing efficiently, is not suitable for simple control. Therefore, the DSP processor is not efficient for general-purpose control processor.

The multimedia application on portable devices, such as PDA and smart phone, is common. As the portable devices are battery-powered, it is important to prolong the battery life. However, the video signal processing usually is complex and consumes a large amount of power. The advanced video compression standard H.264/AVC (advance video coding) reports that a large difference exists in the computing complexity in reconstructing a frame.FIG. 1shows the number of cycles required for decoding a QCIF image, with the minimum number of cycles 1,020,140, and the maximum number of cycles 4,002,744. The average number of cycles is 2,446,444, and the standard deviation is as high as 710,647 cycles.

In general, the microprocessor is designed for the worse scenario. Therefore, the microprocessor usually has a large amount of idle time. When a microprocessor is idling, the operating voltage or frequency can be reduced to save power consumption.

FIG. 2shows a decoding flowchart200of H.264/AVC. The coded bitstream, after entropy decoding, is decoded as two types of data. The first type of data is the syntax elements, including block file header data, motion vector, and so on, and the second type of data is quantized residual coefficient.

H.264 uses power Columbus code to decode the first type of data, and uses context adaptive variable length codes (CAVLC) to decode the second type of data. CAVLC decoding includes the following steps101-106, with each step using a different code table.

Step101: decoding the total number of non-zero coefficients TC and the number of ±1 T1s. The range of TC is 0-16, and the range of T1sis 0-3. This step determines the lookup table based on the nC, where nC is the average of the numbers of non-zero coefficients in the upper part and the left part of the current block that is already decoded.
Step102: based on T1s, decoding the sign. Use 0 to represent the positive sign, and use 1 to indicate the negative sign.
Step103: based on TC, decoding non-zero coefficient level. The look up table used in this step is determined by the previous decoded non-zero coefficient.
Step104: decoding the total number of zeros preceding the non-zero coefficients. The lookup table used in this step is determined based on TC.
Step105: decoding the number of zeros preceding each non-zero coefficient. The lookup table used in this step is determined by the number of zeros preceding the non-zero coefficient.
Step106: recovering the 16 zig-zag sequenced coefficients, based on the values of the previous steps.

FIG. 3shows the quantized residual coefficients generated after entropy decoding201. The quantized residual coefficients include the coefficients of 27 small blocks. With the exception of 16thand 17thsmall blocks302being 2×2, the rest of the small blocks are all 4×4. Also, only in the Intra—16×16 coding mode, the −1th small block301will be generated after the entropy decoding.

In H.264/AVC decoding process, inverse quantization202is the quantized residual coefficient matrix multiplied by the corresponding quantized matrix. The computation equation is shown inFIGS. 4A-4E, where matrix [cij] is the quantized residual coefficient matrix, S is determined by quantization parameter QP divided by 6, and T is the matrix after the inverse quantization, called transform residual block coefficient matrix.

Inverse quantization202performs the 4×4 inverse quantization computing on the −1th small block301, performs the 2×2 DC inverse quantization computing on the 16thand 17thsmall blocks302, and performs the 4×4 DC inverse quantization computing rest of small blocks303.

The transform residual coefficients after the inverse quantization are shown inFIG. 3. The transform residual coefficients include coefficients of 27 small blocks. With the exception of 16thand 17thsmall blocks302being 2×2, the rest of the small blocks are all 4×4. Also, only in the Intra—16×16 coding mode, the −1th small block301will be generated after the entropy decoding.

In the H.264/AVC decoding process, the computing equation of inverse transform203is shown inFIGS. 5A-5C, where matrix [yij] is the transform residual coefficient matrix, and X is the residual coefficient matrix. Inverse transform203performs the 4×4 inverse transform computing on the −1th small block301, performs the 2×2 DC inverse transform computing on the 16thand 17thsmall blocks302, and performs the 4×4 DC inverse transform computing on the rest of small blocks303.

In the H.264/AVC decoding process, motion compensation (MC)204is the sum of the inverse transform output and the predictor found in intra-frame prediction207or inter-frame prediction208.

Intra-frame prediction207provides intra—4×4 and intra—16×16 types. Intra-4×4 is to find the predictor using the luma 4×4 small block as the unit. There are 9 prediction directions for finding predictor. Intra—16×16 is similar to intra—4×4, but using luma 16×16 small block as the unit, and has 4 prediction directions for finding predictor. The intra-frame prediction technique also provides 4 intra-frame prediction directions for chroma, which uses chroma 8×8 block as the unit.

Inter-frame208uses the motion vector206to generate prediction block in the reference frame. The unit of motion vector206can be an integer dot, ½ dot, or ¼ dot. As the ½ dot and ¼ dot information is not recorded during storing the frame, the ½ dot and ¼ dot information must be computed using an integer dot.

The type of intra-frame prediction207can be obtained from the first type of data after entropy decoding, and the motion vector of inter-frame prediction208can be computed from the first type of data after entropy decoding.

In the H.264/AVC decoding process, the operation of deblocking filter205is shown inFIG. 6A. The four vertical boundary lines a-d and the four horizontal boundary lines e-h are used to divide a 16×16 luma block into 16 4×4 luma sub-blocks. Similarly, two vertical boundary lines i, j and two horizontal boundary lines k, l can be used to divide an 8×8 chroma block into 4 4×4 chroma sub-blocks, as shown inFIG. 6B.

When executing deblocking filtering on luma blocks, the execution order is to process four vertical boundary lines a-d, and then four horizontal lines e-h. Similarly, when executing deblocking filtering on chroma blocks, the execution order is to process vertical boundary lines i, j, and then two horizontal boundary lines k, l.

During the deblocking filtering, the boundary strength (BS) is used to determine whether the filtering is required. When BS=1, 2, 3, 4, the filtering is performed. When BS=0, no filtering is performed. The BS is determined by the conditions inFIG. 7. In summary, the conventional decoding process is shown inFIG. 8.

U.S. Pat. No. 6,944,229 disclosed two methods of dynamically adjusting the voltage frequency of the processor. The first method is DVS-Dm, and the second is DVS-PD. DVS-DM is to use the previous load record to adjust the voltage frequency. By categorizing the decoding time into delay state and drop state, the delay state implies the CPU has sufficient time to decode. The greater the delay is, the more time CPU has for decoding. A delay of zero implies that the CPU has just sufficient time to decode. A drop state implies that the CPU has no time to decode and must drop the current frame. When decoding I-type and P-type frames, the voltage frequency must be adjusted to the highest, and when decoding B-type frame, the voltage frequency is tuned high. When being in the delay state and the delay is greater than 100, the voltage frequency is tuned down.

DVS-PD uses the previous load record and the estimation of decoding time to adjust the voltage frequency. Because the time required for decoding an I-type, P-type and B-type frame is different, the decoding time can be estimated by the frame type and the load record of the same type frame. The voltage frequency can be tuned similar to the DVS-DM.

SUMMARY OF THE INVENTION

The present invention provides a power aware method and apparatus of video decoder on a multi-core platform. Because it is a multi-core platform, one of the processor can execute the entropy decoding of a frame, collect the information after the entropy decoding to estimate the frequency required for this frame, and tune the voltage and frequency of some or all of the other processors to reduce the power consumption.

The present invention uses nC to determine the lookup table to use. The nC is the average of the total numbers of the non-zero coefficients in the upper and the left part of the current block that is decoded. The number of zero quantized residual coefficients after entropy decoding can thus be obtained. The decoding time, including inverse quantization and inverse transform time, motion compensation time and deblocking filter time, can be estimated. The operating voltage and frequency can be tuned by estimating the decoding time.

The power aware apparatus of video decoder on a multi-core platform includes a processor unit and a power management unit. The processor unit has at least an operating voltage and at least an operating frequency.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

The present invention analyzes the H.264/AVC decoding process, and takes advantage of the fact that some computing can be omitted during the decoding process when quantized residual coefficients are all zero. For example, (1) inverse quantization and inverse transform can be omitted; (2) the motion compensation requires only duplicating, instead of computing, when the unit of motion vector is an integer; and (3) when BS=0, deblocking filtering is not required.

The nC is used to determine the lookup table to use. The nC is the average of the total numbers of the non-zero coefficients in the upper and the left part of the current block that is decoded. The number of zero quantized residual coefficients after entropy decoding can thus be obtained.

The required operating frequency can be estimated by collecting the information after the entropy decoding. The estimation result can then be used for tuning the operating voltage and the operating frequency of other or all the processors for processing the next frame.FIG. 9shows a flowchart of the power aware method of the present invention. The multi-core platform includes at least a processor.

Refer toFIG. 9. Step901is to receive a bitstream of an encoded frame and to use a processor of the multi-core platform for performing the entropy decoding on the bitstream and outputting the decoded information. The entropy-decoded information includes at least the number of the all-zero quantized residual coefficients. Step903is to estimate the decoding time for the encoded frame based on the entropy-decoded information. Step905is to tune the operating voltage and the operating frequency of other or all the processors for decoding the frame in accordance with the estimation.

Because there is a linear relationship between the entropy decoding time and the number of bits in the bitstream, it only needs to know how may bits in a bitstream to estimate the entropy decoding time in step901.

To save power consumption, it is necessary to correctly tune the operating voltage and frequency of the processor to decode the frame. The following describes how to correctly estimate the required decoding time.

The estimation of decoding time in step903includes the estimation of inverse quantization and inverse transform time ETIQ&IT, motion compensation time ETMC, and deblocking filter time ETDF. That is, the estimated decoding time equals to ETIQ&IT+ETMC+ETDF.

The estimation of inverse quantization and inverse transform time ETIQ&ITis described as follows. Basically, the inverse quantization and inverse transform can be regarded as the computing of 24 4×4 small blocks. When the coefficients of a 4×4 small block are all-zero, the inverse quantization and inverse transform can be omitted as the result is always 0. Therefore, it only needs to know the number of non-zero quantized residual coefficients of the entropy-decoded 24 4×4 small blocks in order to estimate the inverse quantization and inverse transform time. In the first step (step101) of CAVLD, nC determines the lookup table to be used, where nC is the average of the total numbers of the non-zero coefficients in the upper and the left part of the current block that is decoded. The required information can be collected from nC.

The estimation of motion compensation time ETMCis described as follows. Motion compensation includes the addition of the predicator from the intra-frame prediction or inter-frame prediction and the output of inverse transform. Therefore, the motion compensation execution time includes the predictor generation time and the addition time.

As aforementioned, H.264/AVC provides two types of intra-frame predictions for luma, intra—4×4 and intra—16×16, and provides four types of intra-frame predictions for chroma. The chroma uses chroma 8×8 as the unit. The inter-frame prediction uses motion vector in the reference frame to generate prediction block. The unit of motion vector can be an integer dot, ½ dot, or ¼ dot. When the unit of motion vector is an integer dot, the motion compensation does not require to compute, but only requires to duplicate. Because there is no ½ dot and ¼ dot data stored in storing the frame, the ½ dot and ¼ dot data are computed by the integer dot. Therefore, the compensation for motion vector of integer dot, ½ dot and ¼ dot are different. The type of intra-frame prediction can be obtained from the first type data after entropy decoding, and the motion vector of the inter-frame prediction can also be obtained from the first type data after entropy decoding.

The estimation of deblocking filter execution time ETDFis as follows. Basically, the execution of deblocking filter can be seen as the deblocking filter computing of 32 4×4 small blocks in accordance with the BS value. When BS=0, no deblocking filter computing is performed. When BS=1, 2 or 3, the estimation equation is different from the equation when BS=4.

FIG. 10shows a schematic view of the power aware apparatus of the present invention. As shown inFIG. 10, a power aware apparatus includes a processor unit1001and a power management unit1003. Processor unit1001at least includes an operating voltage and an operating frequency. Processor unit1001also includes an entropy decoder1011and a decoder1021. Processor unit1001receives a bitstream of a frame. Entropy decoder1011performs entropy decoding on the bit stream and outputs the entropy decoded information1011a. Entropy decoded information1011aat least includes the number of the information1011bof all-zero quantized residual coefficients. Based on information1011b, power management unit1003estimates the decoding time of the encoded frame, and tune the operating voltage and frequency of processor unit1001. Based on the tuning, decoder1021executes the decoding of the frame.

Therefore, the present invention tunes the operating voltage and frequency for processor unit1001when decoding each frame for saving power.

Decoder1021uses the entropy decoded information1011ato decode each frame, including inverse quantization and inverse transform, motion compensation and deblocking filtering.

Without the loss of generality, the following embodiments use dual-core and unit-core platforms for explanation.

In the first embodiment, the multi-core platform is a dual-core platform, including a first processor and a second processor. The first processor, such as a microprocessor, receives a bitstream of a frame, executes the entropy decoding and estimates the decoding time, and then tunes the operating voltage and frequency of the second processor, such as DSP processor. The second processor decodes the encoded frame, including performing inverse quantization and inverse transform, motion compensation, and deblocking filter.

FIG. 11shows a schematic view of the embodiment of the present invention applied to a dual-core platform. The second processor (DSP processor) executes the decoding of the Nth frame, including inverse quantization and inverse transform, motion compensation, and deblocking filter, and the first processor (microprocessor) executes the entropy decoding, decoding time estimation, and computing the required operating voltage and frequency for the N+1thframe.

Because the decoding of a frame takes more time, when the second processor decodes the Nthframe, the first processor can execute its tasks on the N+1th, N+2th, . . . , frames to save power.

In the second embodiment, the multi-core platform is a uni-core platform, for example, including only a DSP processor and a microprocessor. The processor first executes the entropy decoding, the decoding-time estimation, and the computation of the required operating voltage and frequency for the N+1thframe. It then executes the inverse quantization, the inverse transform, the motion compensation, and the deblocking filter for the Nthframe. At the end of executing the Nthframe, the processor sets up the operating voltage and frequency for decoding the N+1thframe. In other words, the uni-core platform is a special case ofFIG. 11where the first processor and the second processor are the same one.

The simulation is conducted to compare the power consumption of the method and apparatus of the present invention and the conventional method. The multi-core platform is a dual-core platform, and each frame must be decoded in 1/15 seconds.

FIG. 12shows the required cycles for decoding each frame and the percentage of the decoding time within 1/15 seconds of each frame when using the conventional fixed voltage and frequency method. The fixed voltage and frequency are 1.2V and 228 MHz, respectively.

Assume the DSP consumes a unit of power to execute 1/15 second decoding, and consumes no power at the remaining time. The power consumption inFIG. 12is equal to 1×9.08+0×5.92=9.08. Where 9.08 is the sum of the percentage of each frame of 1/15 second decoding ofFIG. 11, and 5.92 is the sum of the remaining time percentage after the 1/15 second decoding.

If the required cycles of decoding each frame can be known in advance, the voltage and frequency can be tuned to save power. According to the present invention,FIG. 13Ashows the relationship between the power consumption and the voltage/frequency of the six power modes (mode1-mode6) of DSP.FIG. 13Bshows that of the 1/15 second decoding when decoding each frame using dynamic tuning of voltage and frequency. On the other hand, the power consumption inFIG. 13Bis equal to 1×(2.78)+(1.0/1.2)2(152/228)×(8.73)+(0.8/1.2)2(114/228)×(0.92)=2.78+4.04+0.26=7.08 units.

As shown, the present invention consumes 22% less power than the conventional fixed voltage and frequency when using a DSP processor.