Method and apparatus for testing the data output system of a memory system

A method and apparatus for testing or verifying proper operation of a data output system of a memory system are provided. A known data signal is applied to a bit line, independent of the memory cells of the memory system associated with the bit line. Expected outputs of the data output system are determined based upon the formation or configuration of the data output system and the known data signal. Following application of the known data signal to the bit line, actual outputs of the data output system are compared to the expected outputs to verify proper operation of the data output system.

RELATED APPLICATION INFORMATION 
This application relates to the following commonly assigned, co-pending 
U.S. patent applications: 
Application Ser. No. 08/575,312, entitled "Field Programmable Memory 
Array," filed Dec. 20, 1995; 
Application Ser. No. 08/575,422, entitled "System For Implementing Write, 
Initialization, And Reset In A Memory Array Using A Single Cell Write 
Port," filed Dec. 20, 1995; and 
Application Ser. No. 08/724,573, Attorney Docket No. FI9-96-090, entitled 
"Method And Apparatus For Testing The Address System Of A Memory System," 
filed concurrently herewith. 
Each of these applications is hereby incorporated by reference herein in 
its entirety. 
TECHNICAL FIELD 
This invention relates to digital memory systems. More particularly, this 
invention relates to a method and apparatus for verifying proper operation 
of a data output system of a digital memory system. 
BACKGROUND OF THE INVENTION 
Test techniques for memory systems conventionally include the application 
of predetermined input bit patterns to memory cells of the memory system, 
and thereafter reading the contents of the memory cells to determine 
whether the output patterns match the input patterns. If the output 
patterns do not match the input patterns, it follows that a fault has 
occurred somewhere in the memory system. 
Memory systems, however, are becoming increasingly complex, and the above 
conventional input/output pattern matching technique does not offer an 
adequate level of fault isolation for such complex memory systems. An 
exemplary, complex memory system is disclosed in the above-incorporated 
U.S. patent application entitled "Field Programmable Memory Array." FIG. 1 
herein is a functional block diagram of the sub-systems of the field 
programmable memory array, which are discussed in detail in the 
incorporated application. Programmable memory array 10 includes a 
plurality of memory sub-arrays 12.sub.1, 12.sub.2, 12.sub.3, . . . along 
with respective data input multiplexers 14.sub.1, 14.sub.2, 14.sub.3, . . 
. and respective data output multiplexers 15.sub.1, 15.sub.2, 15.sub.3, . 
. . An address system 20 produces signals on write word lines 50.sub.1 and 
read word lines 60.sub.1 for memory sub-array 12.sub.1. The signals on the 
write word lines are produced by using multiplexer 22.sub.1 and decoder 
24.sub.1. Multiplexer 22.sub.1 programmably selects a write address 30 
from an address bus (not shown), and decoder 24.sub.1 decodes the selected 
address and applies the proper signals to write word lines 501. 
Multiplexer 26.sub.1 and decoder 28.sub.1 similarly process a read address 
40 and apply the proper signals to read word lines 60.sub.1. 
Data signals from the memory cells selected by the read word line signals 
are transmitted from the sub-arrays 12 using bit lines 16.sub.1, 16.sub.2, 
16.sub.3, . . . to a data output system 70. The data output system may 
include multiplexers 15.sub.1, 15.sub.2, 15.sub.3, . . . as well as any 
other circuitry necessary to present to the user of the system a 
representation of the information stored in memory cells of the sub-arrays 
12. In the field programmable memory array embodiment of a data output 
system, a hierarchical bit line system 18 may be employed, in addition to 
bit lines 16, to programmably transmit data from multiple sub-array 
sources to multiple output destinations. 
The complexity of the memory system of FIG. 1 results from, in addition to 
customized memory sub-arrays 12, the data handling system including 
multiplexers 14 and 15, as well as the address handling system 20. The 
potential complexity of address system 20 can be better understood by 
reviewing FIGS. 26a-c of the above-incorporated U.S. patent application 
entitled "Field Programmable Memory Array." The potential complexity of 
the data output system can be better understood by reviewing FIGS. 2a-b, 
18a-b, 23-25, and 29-30 of the same application. 
Using the above-identified conventional input/output pattern matching test 
techniques for the system of FIG. 1 results in a memory system test signal 
path of the following form: 
##STR1## 
An input/output pattern matching test is adequate to indicate that a fault 
has occurred somewhere in the above path, however, it is not adequate to 
isolate a particular system within which the fault has occurred. Complex 
address and data handling systems are more likely to produce faults, and 
isolation of such faults is required to effectively test the entire 
system. 
What is required, therefore, are test/verification methods and systems 
which provide a greater degree of fault isolation for complex memory 
systems. 
SUMMARY OF THE INVENTION 
The shortcomings of conventional test techniques are overcome by the 
present invention which provides a technique to isolate errors in the data 
output system of a memory system. 
The memory system includes an array of memory cells, and a bit line for 
carrying a data signal indicative of a stored state of at least one memory 
cell of the array of memory cells. A data output system is coupled to the 
bit line for receiving the data signal therefrom. A test circuit is 
coupled between the bit line and a known data signal source and controls 
coupling of a known data signal to the bit line. A resultant data signal 
at an output of the data output system can be compared to an expected data 
signal to verify proper operation of the data output system. 
The memory system may include a first coupling circuit, coupled to the bit 
line, for selectively coupling a first pre-charge signal component thereto 
during operation of the array of memory cells. The test circuit itself 
includes a second coupling circuit, coupled to the bit line, for 
selectively coupling a second signal component thereto. The first, 
pre-charge signal component and the second signal component comprise the 
known data signal and correspond to signal components expected to be 
carried by the bit line during operation of the memory cells. 
A test enable signal source and a pre-charge control signal source are used 
to place the test circuit and the first coupling circuit collectively into 
one of two modes. In the first mode, the second coupling circuit of the 
test circuit is prevented from coupling the second signal component to the 
bit line, and the coupling of the first, pre-charge signal component to 
the bit line by the first coupling circuit is controlled by the pre-charge 
control signal source. In the second mode, the coupling of the first, 
pre-charge signal component by the first coupling circuit and the coupling 
of the second signal component by the second coupling circuit to the bit 
line are controlled by the test circuit as a function of the known data 
signal source. 
In another embodiment, the present invention relates to a method for 
verifying proper operation of a data output system of a memory array 
having a plurality of memory cells arranged therein. The plurality of 
memory cells uses at least one bit line to transmit signals therefrom, the 
signals transmitted by the bit line being coupled through the data output 
system during operation of the memory array. The method includes, 
independent of the plurality of memory cells, applying a known signal to 
the bit line thereby resulting in an actual output signal at an output of 
the data output system. The actual output signal is compared to an 
expected output signal to verify proper operation of the data output 
system. 
A first signal component of the known signal may be applied to the bit line 
using a pre-charge circuit coupled to the bit line. The pre-charge circuit 
is also used to pre-charge the bit line during operation of the memory 
array. A second signal component of the known signal may be applied to the 
bit line using a test circuit coupled to the bit line. 
In one embodiment of the invention, the memory array comprises a 
programmable memory array, and the data output system thereof comprises a 
configurable data output system. In this embodiment, the configurable data 
output system is configured such that the expected output signal is 
expected to appear at the output of the configurable data output system. 
The verification apparatus and methods of the instant invention therefore 
provide an effective fault-isolation technique for a data output system of 
a memory system. The instant invention is an improvement over conventional 
input/output pattern matching techniques, because the instant invention 
allows for isolation of a fault within the data output system, to the 
exclusion of any faults which may reside in other portions of the memory 
system.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT(S) 
As discussed above with reference to FIG. 1, a complex memory system 10 may 
include a complex data output system 70, including at least portions of 
bit lines 16, multiplexers 15, possibly a hierarchical bit line structure 
18, and any necessary I/O. During normal operation of the memory system, 
data signals representative of the stored states of cells within 
sub-arrays 12 are transmitted over bit lines 16, through multiplexers 15, 
and are eventually presented to a user of the system. Multiplexers 15 may 
be programmable using configuration memory (not shown), in accordance with 
the above-incorporated U.S. patent application entitled "Field 
Programmable Memory Array." The instant invention relates to a method and 
apparatus for verifying the proper operation of the data output system of 
a complex memory system. 
With reference to FIG. 2, a test signal path is established, in accordance 
with the instant invention, over which known data signals are applied 
directly to bit lines 16 from an internal or external tester. Multiplexer 
15, part of the data output system 70, has its inputs coupled to the bit 
lines (as discussed above). The outputs of the data output system are 
applied to the tester. A known configuration of multiplexer 15 serves as a 
basis upon which expected outputs thereof can be predicted, given the 
known data signals applied to its inputs via bit lines 16. The known 
configuration is determined based on the known, hard-wired formation of 
this portion of the data output system, or based on a configuration 
thereof established via configuration memory. 
Once the expected outputs are determined, they can be compared by the 
tester to the actual outputs of the data output system. Equivalency 
between the expected and actual outputs results in a determination that no 
faults (or off-setting faults) exist in the data output system. A lack of 
equivalency between these outputs results in a determination that faults 
likely exist in the data output system. 
The known data source depicted in FIG. 2 can either be driven by the actual 
data inputs to the sub-arrays depicted in FIG. 1 (but routed around the 
data input multiplexers and/or the memory cells to the output bit lines), 
or by an auxiliary data source or sources independent of the addressing, 
data input and memory cell circuitry shown generally in FIG. 1 and 
normally associated with a memory array. 
By employing the technique depicted in FIG. 2, the test signal path is now: 
##STR2## 
Upon comparison of this test path to the much more complicated test path 
illustrated above for a conventional input/output pattern matching test, 
it is evident that a fault can now be isolated within the data output 
system itself without regard to the operation of the memory sub-arrays or 
their data input or addressing systems. Such fault isolation is especially 
necessary when considering the rather complex data output systems being 
employed in memory systems, such as a field programmable memory array. As 
discussed above, such data output systems may contain configurable 
multiplexers and a hierarchical bit line routing system. 
The verification technique of the instant invention can isolate faults to 
the data output system which may include the multiplexer 15 depicted in 
FIG. 2, as well as the configuration memory (not shown) which may be 
associated with multiplexer 15, any follow-on input/output facilities, the 
bit lines themselves, and the hierarchial bit line routing system (if 
employed). 
Two exemplary embodiments of a test circuit for applying known data to a 
bit line are depicted in schematic form in FIGS. 3a-b. With reference to 
FIG. 3a, memory cells 112 are associated with bit line 110. Those skilled 
in the art will recognize that numerous configurations are possible 
connecting memory cells 112 to their associated bit line 110. As discussed 
above, bit line 110 carries data indicative of the stored state of memory 
cells 112 and that data is propagated through data output multiplexer 15, 
the outputs of which are applied to a tester. 
Also depicted in FIG. 3a is a pre-charge coupling circuit 130 for coupling 
a voltage level V.sub.1 to bit line 110, during operation of memory cells 
112. Pre-charge coupling circuit 130 may be an N-FET transistor as shown, 
the control gate of which is usually driven by a pre-charge control line. 
Those skilled in the art will recognize that such pre-charge coupling 
circuits are used in many memory circuits to charge the bit line which 
usually has a parasitic capacitance. Using a pre-charge approach, the 
memory cells 112 need only maintain or discharge the charge on bit line 
110, and therefore need not be of sufficient size to drive the parasitic 
capacitance on bit line 110 from one signal level to another signal level. 
Therefore, the existence of pre-charge coupling circuit 130 allows memory 
cells 112 to have less drive capability and therefore be smaller in size. 
The smaller size of these memory cells results in a greater density and 
thus a greater overall size of the memory array per unit area. 
In accordance with this embodiment of the invention, a test circuit 120 is 
employed in combination with pre-charge coupling circuit 130 to drive bit 
line 110 with a known data signal. The known data signal usually includes 
two components, in this embodiment voltage levels, which are the levels 
expected to be carried by bit line 110 during operation of memory cells 
112. Test circuit 120 employs an additional coupling circuit 126, which 
couples the second voltage level V.sub.2 to the bit line, and further 
includes the necessary circuitry to enable test circuit control of both 
coupling circuits 126 and 130 during test, while also allowing disabling 
of coupling circuit 126 and control of coupling circuit 130 via the 
pre-charge control line during normal memory array operation. These two 
modes of the circuitry are made possible by AND gate 122, transistor 124, 
and OR gate 128. 
First Mode--Array Operation 
As discussed above, a known data signal is applied to the bit line 110 in 
accordance with a known data source, depicted as one of the inputs to AND 
gate 122. Another input of AND gate 122 is the test enable line. The test 
enable line is also applied to the control gate of N-FET transistor 124, 
and the controllable current path through transistor 124 is connected 
between the output of AND gate 122 and the control gate of P-FET 
transistor 126. If test enable is low, triggering of AND gate 122 is 
inhibited and the control gate of transistor 126 is held high via pull-up 
resistor 123. In this configuration, coupling circuit 126 is disabled and 
therefore is prevented from applying level V.sub.2 to bit line 110. 
Further, with test enable low, AND gate 122 is not triggered, and 
therefore the output of OR gate 128 is controlled by the pre-charge 
control line. Therefore, coupling circuit 130 is controlled solely by the 
usual pre-charge control line during normal operation of the memory array. 
The path from the test enable line to and including the control gate of 
transistor 124, and its effect on coupling circuit 126, is an exemplary 
embodiment of what is generally referred to herein as the test enable 
path. The path from the pre-charge control line to the coupling circuit 
130, including OR gate 128, is an exemplary embodiment of what is 
generally referred to herein as the pre-charge control path. Those skilled 
in the art will recognize that various forms of circuitry can be employed 
to provide the inventive functionality of the test enable and pre-charge 
control paths without departing from the principles of the present 
invention. 
Second Mode--System Test 
In the second mode of operation, test circuit 120 is enabled by a high 
signal level on the test enable line. A high signal on the test enable 
line allows the output of AND gate 122 to be controlled solely by the 
known data source. Further, a high signal level on the test enable line 
turns on the current path through transistor 124, and therefore allows the 
output level of AND gate 122 to directly drive the control gate of 
coupling circuit 126. (Those skilled in the art will recognize that the 
value of resistance 123 is generally large, but the value at the control 
gate of coupling circuit 126 can be effectively pulled low by a stronger 
AND gate 122 output.) During the second mode, pre-charge control line is 
held low, so that OR gate 128 is controlled solely by the output of AND 
gate 122. The value at the output of AND gate 122 is thus propagated 
through OR gate 128 to the control gate of coupling circuit 130. 
Alternating levels of the known data source will thus result in 
alternating levels applied to the orthogonally formed (P-FET/N-FET) pair 
of transistor coupling circuits 126 and 130, thus resulting in a 
corresponding set of alternating levels applied to bit line 110. Voltage 
levels V.sub.1 and V.sub.2 are appropriately chosen to correspond to the 
expected signal levels on bit line 110 during operation of memory cells 
112. During the second, test mode, the voltage levels present on bit line 
110 are applied to the bit line and therefore to the data output 
multiplexer 15 of the data output system. As discussed above, the outputs 
of the data output system can be compared to the expected outputs thereof, 
considering the known data source, and an indication of any faults in the 
data output system can be obtained by this comparison. 
The paths from the known data source to and including the coupling circuits 
126 and 130 are exemplary embodiments of what are referred to herein as 
data paths. Those skilled in the art will recognize that various forms of 
circuitry can be employed to provide the inventive functionality of those 
data paths without departing from the principles of the present invention. 
FIG. 3b is an alternate embodiment 120' of test circuit 120 of FIG. 3a. 
Elements 122', 126', and 128' correspond to elements 122, 126, and 128 of 
FIG. 3b. However, elements 123 and 124 of FIG. 3a are replaced in FIG. 3b 
by invertor 143 and OR gate 144. Those skilled in the art will recognize 
that this arrangement of circuits results in the same type of orthogonal 
control of coupling circuits 126' and 130 for the corresponding 
application of levels V.sub.1 and V.sub.2 to bit line 110. 
Tables 1 and 2 below are truth tables of the relevant states of the devices 
depicted in FIGS. 3a, and 3b, respectively during the second, test mode of 
operation. 
TABLE 1 
__________________________________________________________________________ 
Truth Table - FIG. 3a 
PRE- 
CHARGE 
TEST KNOWN 124 
126 126 130 
CONTROL 
ENABLE 
DATA 122 
(N) 
INPUT 
(P) 
128 
(N) 
BL 
__________________________________________________________________________ 
0 0 0 0 OFF 
1 OFF 
0 OFF 
-- 
0 0 1 0 OFF 
1 OFF 
0 OFF 
-- 
0 1 0 0 OFF 
0 ON 0 OFF 
V.sub.2 
0 1 1 1 OFF 
1 OFF 
1 ON V.sub.1 
__________________________________________________________________________ 
TABLE 2 
__________________________________________________________________________ 
Truth Table - FIG. 3b 
PRE- 
CHARGE 
TEST KNOWN 126' 130 
CONTROL 
ENABLE 
DATA 122' 
143 
144 (P) 
128' 
(N) 
BL 
__________________________________________________________________________ 
0 0 0 0 1 1 OFF 
0 OFF 
-- 
0 0 1 0 1 1 OFF 
0 OFF 
-- 
0 1 0 0 0 0 ON 0 OFF 
V.sub.2 
0 1 1 1 0 1 OFF 
1 ON V.sub.1 
__________________________________________________________________________ 
Those skilled in the art will recognize that the signal polarities and 
types of gates employed in the test circuit may be varied without 
departing from the principles of the present invention. The term "gate" is 
used broadly herein to denote any type of electrical circuit. The terms 
"coupling" and "connecting" are used broadly herein to denote direct 
connections between elements, or indirect connections (e.g., 
buffered/inverted) over which the associated information is nevertheless 
communicated between elements. 
In the exemplary embodiments of FIGS. 3a-3b, an existing pre-charge circuit 
is employed with the added test circuit to apply one of the signal levels 
required. This unique use of the existing pre-charge circuit allows the 
remainder the test circuit itself to occupy less additional circuit area 
than would otherwise be possible. However, this invention also 
contemplates the application of known signals to bit lines, independent of 
the memory cells, and without the use of existing pre-charge circuits. 
If a hierarchical bit line output structure is employed, the circuits of 
FIGS. 3a-b could also be employed to apply known data signals to any of 
the bit lines thereof, to test downstream portions of the data output 
system. 
This invention may also be used in combination with the address system test 
techniques disclosed in the above-incorporated U.S. patent application 
entitled "Method and Apparatus For Testing The Address System Of A Memory 
System" to provide fault isolation to the address and/or data output 
systems. 
The instant invention offers a greater degree of fault isolation in memory 
systems than conventional input/output pattern matching tests can provide. 
This greater degree of fault isolation is especially important for complex 
memory systems, in which the complexity of the individual systems therein 
increases the likelihood of untraceable errors when using a conventional 
input/output pattern matching technique. 
While the invention has been particularly shown and described with 
reference to preferred embodiment(s) thereof, it will be understood by 
those skilled in the art that various changes in form and details may be 
made therein without departing from the spirit and scope of the invention.