Encapsulated photomultiplier device of semiconductor material, for use, for example, in machines for performing positron-emission tomography

An embodiment of a photomultiplier device is formed by a base substrate of insulating organic material forming a plurality of conductive paths and carrying a plurality of chips of semiconductor material. Each chip integrates a plurality of photon detecting elements, such as Geiger-mode avalanche diodes, and is bonded on a first side of the base substrate. Couplings for photon-counting and image-reconstruction units are formed on a second side of the base substrate. The first side of the base substrate is covered with a transparent encapsulating layer of silicone resin, which, together with the base substrate, bestows stiffness on the photomultiplier device, preventing warpage, and covers and protects the chips.

PRIORITY CLAIM

The instant application claims priority to Italian Patent Application No. TO2010A000947, filed Nov. 29, 2010, which application is incorporated herein by reference in its entirety.

TECHNICAL FIELD

An embodiment relates to a photomultiplier device of semiconductor material, in particular for use in machines for performing positron-emission tomography (PET).

BACKGROUND

As is known, positron-emission tomography (PET) is widely used, i.e., in the medical sector for the detection of structures and formations in human tissues, and consists in supplying a tracer isotope bound to an active molecule to tissues to be examined. The decay of the isotope in the tissues causes generation of positrons that are annihilated with electrons and give rise to gamma rays, which can be detected by a layer of inorganic crystals (scintillator) where a flash is created, which is in turn detected by a photomultiplication structure arranged adjacent to the layer of inorganic crystals.

For example,FIG. 1shows a typical detector ring1present in a PET machine. As may be noted, the detector ring1is formed by a plurality of detector blocks2, circumferentially arranged around the ring, each with radial extension. Referring toFIG. 2, each detector block2includes an array of inorganic crystals or scintillators3adjacent to an array of photomultipliers4.

Traditionally, the photomultipliers4are formed by photomultiplier tubes (PMTS); however, in the last few years, the use of silicon photomultipliers (SiPms) has been proposed, thanks to the high efficiency that can be obtained (see, for example, “Silicon Photo-multipliers as Photon Detector for PET”, by R. Pestotnik et al., 2008 IEEE Nuclear Science Symposium Conference Record, which is incorporated by reference).

The proposed SiPms are formed as arrays of individual photomultiplier cells, each made up of a plurality of elements for detecting individual photons, typically Geiger-mode avalanche diodes (GMAPs), made, for example, as described in US 2009-0184317 and US 2009-0184384, which are incorporated by reference. In particular, the avalanche diodes operate at reverse biasing voltages that are a few volts higher than the breakdown voltage, and each avalanche diode detects an individual photon. In fact, as shown inFIG. 3, each avalanche diode5is coupled to the supply Vb through a respective quenching resistor6, disposed (e.g., integrated) in series, and forms with the latter a pixel7. In each pixel7, the quenching resistor6is able to quench the avalanche current and reset only the relevant avalanche diode5after detection of a photon. In a photomultiplier cell8, the pixels7are coupled in parallel to one another so that the currents detected by each of the individual pixels7are added together. The intensity of the total current of the photomultiplier cell8is thus given by the analog superposition of the signals (binary signals in an embodiment) produced by all activated pixels7, which is, in turn, proportional to the number of incident photons (to a first approximation, if multiple hits on different pixels7are neglected).

Thus, in case of weak flows of photons, a photomultiplier cell8of SiPm diodes behaves as an analog or proportional device, whereas the individual pixels operate in digital or Geiger mode. For this reason, silicon photomultipliers are also frequently represented as digital-to-analog conversion devices.

Currently, in general, each photomultiplier cell is manufactured in a chip with dimensions of approximately 4×4 mm2, or, at the most, approximately 5×5 mm2, and the various chips are arranged near each other so as to form more extensive detection surfaces. In particular, the chips are bonded to an intermediate substrate (generally a die of semiconductor material), which is, in turn, bonded to a base substrate, which is larger and is generally obtained from a printed circuit board (PCB) or from PCB material. The group formed by the base substrate, the intermediate substrate, and the array of cells is then bonded to the array of scintillators3, for example, with the interposition of an optical grease (see, for example, “Evaluation of Arrays of Silicon Photomultipliers for Beta Imaging”, E. Heckathorne, L. Tiefer, F. Daghighian, M. Dahlborm, 2008 IEEE Nuclear Science Symposium Conference Record, which is incorporated by reference).

However, arranging the cells near each other typically requires the presence of free areas for providing the connections (paths, pads for the connection wires, etc.). In at least some known devices, for example, the active areas represent approximately 50-60% of the total area. Consequently, there are “dead” or “blind” areas with no pixels, where, consequently, photons are lost. This entails a reduction in the theoretical resolution of the PET, and may entail a lengthening of the times for carrying out the medical examination.

This problem may increase when the single chips that integrate a cell are bonded to an own intermediate substrate, on account of the tolerance of bonding the intermediate substrates.

Attempts at directly bonding the chips to the base substrate have not solved the problem since the structure tends to undergo deformation and to lose planarity (i.e., warp), because of the large dimensions of the base substrate, of the layer of cement used, and of the bonding process, thus preventing proper contact between the photomultipliers and the photomultiplier cells, and thus worsening the detection efficiency.

It is also possible to reduce the dead spaces by providing through silicon vias (TSVs) through the base substrate and through the intermediate substrate, when present, but this solution typically does not solve the problem of warpage, and may be costly.

On the other hand, the creation of the array of cells in a single integrated device, for example, of approximately 32×32 mm2, gives rise to problems of yield, and also devices of these dimensions tend to undergo considerable deformation due to stress. In addition, also in this case it would probably be necessary to create through vias through the base substrate, with all the problems highlighted above.

On the other hand, the lack of an effective protection of the chips is a problem since bonding the array of photomultiplier cells to the array of scintillators is generally performed in a plant remote from the site where the photomultiplier devices are produced.

SUMMARY

An embodiment is a photomultiplier device that overcomes one or more drawbacks of the prior art.

DETAILED DESCRIPTION

FIG. 4shows a cross-section through a photomultiplier device10according to an embodiment. The photomultiplier device10includes a base substrate11having one side, designated by way of example, as front side12, bonded to an array of chips13, each forming a photomultiplier cell8of the type shown inFIG. 3and thus including a plurality of photon detecting elements of semiconductor material, typically Geiger-mode avalanche diodes. The chips13are covered by an encapsulating layer14that is to be bonded to a scintillator crystal18represented with a dashed line. A second side of the base substrate11, designated as rear side15, is used for coupling to the “outside world.”

The base substrate11may be an organic substrate made up of one or more core layers16of insulating material, typically plastic, in particular an epoxy resin, and specifically a laminate of BT (bismaleimide triazine) or FR-4 or some other material used for forming printed circuits.

On the two sides of the core layer16coupling structures are present. In the example shown, the coupling structures are formed by eight conductive levels or layers20-27, four to each side of the core layer16, separated from one another by layers of dielectric material designated as a whole by28, and coupled where envisaged by interlevel conductive vias30and by through conductive vias31(two whereof are visible inFIG. 4). In detail, the example shown includes the following conductive levels20-27(in sequence, starting from the front side):

chip coupling level20on the front side12of the substrate, forming both wire-bonding pads35and upper pads36;

first shielding level21, which shields the chips13from the underlying coupling level. This level, like the similar shielding levels described below, extends through most the area of the photomultiplier device10and is interrupted only to ensure electrical separation of the various current paths;

first routing level22, formed by a plurality of conductive paths which couple the underlying levels to the pads35and36;

second shielding level23, which is adjacent to the top side of the core layer16and shields the first routing level underneath;

third shielding level24, adjacent to the lower side of the core layer16; this level may be omitted, but it may be useful for the symmetry of the structure;

second routing level25, formed by a respective plurality of conductive paths so as to allow, together with the first routing level, crossing of the various current paths and coupling the conductive regions of the third shielding level24to the points provided for the external couplings;

fourth shielding level26, for shielding the second routing level25at the bottom; and

external coupling level27forming a plurality of external pads, for enabling coupling of the photomultiplier device10to the signal-processing units of an image-detecting system, for example of a PET machine.

The conductive levels20-27and the dielectric layers28may be obtained in a conventional manner employing conventional techniques for manufacturing printed-circuit boards. For example, in an embodiment, the conductive levels20-27are made of copper, and the dielectric layers28are made of organic material, such as bismaleide triazine (BT).

The thickness of the base substrate11is selected so as to bestow on the photomultiplier device10, together with the encapsulating layer14, the desired stiffness; for example, the thickness can be approximately between 0.5 and 1.5 mm. In addition, the core layer16can have a thickness of approximately 400-600 μm, e.g., approximately 0.5 mm; the conductive levels can have each a thickness between approximately 15 and 20 μm, e.g., approximately 20 μm; and the dielectric layers28can have a thickness of between approximately 30 and 40 μm, e.g., approximately 30 μm, so as to obtain a total minimum thickness greater than approximately 800 μm, for example, greater than approximately 900 μm, e.g., approximately 920 μm. In general, the base substrate11has a maximum thickness of between 0.5 approximately and 1.5 mm.

The interlevel conductive vias30are made, for example, of copper deposited in openings in the dielectric layers; the through conductive vias31are formed by a metal layer covering holes extending through the core layer16and filled with dielectric material.

The wire-bonding pads35formed in the chip coupling level20are covered with a bonding layer33of gold or other material suitable for coupling with bonding wires34; the latter are also coupled each to a respective chip pad38provided on a front surface of each chip13. Each chip13moreover has a rear surface covered with a metal layer32, for example, of Cr—Ni—Au, bonded to a respective pad36via conductive adhesive regions37formed by a layer referred to also as “conductive die-attach film” (CDAF). For example, the conductive adhesive layer37can be product LE5000 manufactured by Lintec Corporation, with a thickness of approximately 15-50 μm.

A front solder-mask layer40and a rear solder-mask layer41completely cover respectively the chip coupling level20(except at the wire-bonding pads35and the upper pads36) and the external coupling level27(except at external pads in the external coupling level27), respectively. The front and rear solder-mask layers40,41are of a non-conductive material, which can be patterned via chemical etching. For example, the non-conductive material may be a polymeric material, such as AUS 308 manufactured by Taiyo America, Inc.

The encapsulating layer14extends above the front solder-mask layer40and alongside the latter where it is open for the contacts. The encapsulating layer14has the purpose of encapsulating the photomultiplier device10, forming a protection structure for the chips13during transport, storage, and handling. The encapsulating layer14has also a stiffening function, such as to bestow, together with the base substrate11, the desired stiffness to the photomultiplier device10, preventing warpage thereof, which, in addition to jeopardizing proper operation of the photomultiplier device10, may prevent bonding thereof to the scintillator crystal18. In order to enable functionality of the photomultiplier device10, the encapsulating layer14has a relatively high transparency, for example, higher than 90% at the operating wavelengths of the apparatus wherein the photomultiplier device10is mounted. For example, for application in machines for PET, the working wavelength is approximately within the 400-to-800-nm band.

In the example considered, the encapsulating layer14is a non-dispensable, transparent (in the sense defined above) silicone resin, having a relatively low Young's modulus that enables compensation for minor warpage. For example, the Young's modulus may be between approximately 2 MPa and 10 MPa.

For example, the encapsulating layer14may be a layer that can be applied by liquid compression moulding, such as OE-6635A/B manufactured by DOW CORNING™ or LPS3412 and LPS5400 manufactured by SHIN-ETSU™.

The encapsulating layer14typically has a thickness between approximately 100 and 250 μm, for example, approximately 150-200 μm, above the chips13, i.e., between approximately 150 and 600 μm, for example, approximately between 400 and 450 μm, starting from the surface of the base substrate11, and more precisely from the solder-mask layer40. In this way, with chips13of a height of approximately 250 μm (the bottom base whereof is approximately aligned with the top surface of the solder-mask layer40) and bonding wires34projecting approximately 100 μm above the chips (i.e., with a wire-bonding loop of approximately 100 μm) the space above the bonding wires34is approximately 50-100 μm. Since the encapsulating layer14can be moulded with high planarity of the top surface, it can be bonded directly to the scintillator crystal18, without any need to interpose glue layers, thus improving the transparency and avoiding the corresponding cost.

An embodiment of a process for manufacturing an embodiment of the photomultiplier device10includes forming the base substrate11according to known techniques for producing printed circuits, and includes:

covering the top side and the bottom side of the core layer16with a conductive layer (for example, via lamination of a copper layer or by sputtering and subsequent electrolytic or electroless plating with copper) so as to form the second and third shielding levels23,24;

perforating the core layer16(using a purposely provided perforating tool, such as a microdrill) and covering the walls of the holes (for example, via plating with metal material, for example copper, or sputtering);

etching and patterning the second and third shielding levels23,24according to the desired paths;

filling the holes with dielectric material;

creating the sequence of insulating layers and conductive levels20-22and25-27, with formation of the interlevel conductive vias30and the vias31, in a conventional manner;

plating the wire-bonding pads35and the upper pads36, for example with gold; and

depositing and patterning the solder-mask layers40,41so as to free the pads.

Then, the individual chips13are bonded on the upper pads36via the interposition of the conductive adhesive regions37, which may be pre-applied on the photomultiplier devices10at the wafer level before dicing. The wire connections are obtained by bonding the bonding wires34between the chips13and the corresponding wire-bonding pads35, and then the encapsulating layer14is moulded over an entire wafer. For this purpose, a wafer including a plurality of base substrates11and of the corresponding chips13is introduced in a half-mould. The encapsulating material is deposited in the half-liquid phase in the other half-mould, and the two half-moulds are closed. Then a thermal curing step is performed, for example, for approximately 100-300 s at approximately 150-220° C. Finally, the wafer thus obtained is diced to obtain the individual photomultiplier devices10, with the encapsulating layer14that covers the chips13at the top and laterally, so protecting them.

FIG. 5shows a layout of the photomultiplier device10ofFIG. 4according to an embodiment. Here, the photomultiplier device10includes 8×8 chips13, aligned in an array of rows and columns, with wire-bonding pads35arranged between the first and the second columns, between the third and the fourth columns, between the fifth and the sixth columns, and between the seventh and the eighth columns. In particular, the two wire-bonding pads35arranged between two adjacent chips in the direction of the rows are staggered with respect to each other in the direction of the columns so as to reduce the overall dimensions.

With the above arrangement, for placing the chips13, it may be possible to create a single reference (“fiducial”)39every four chips, in a position facing four adjacent corners of the four chips13.

Consequently, with chips of dimensions of approximately 3.95×3.95 mm2, side edge A, D 250 μm, distance between columns without pad B≈120 μm, distance between columns with pad C≈150 μm, distance between rows of chips referred to a same reference39E1≈80 μm, distance between rows of chips referred to different references39E2≈120 μm, the total area of the photomultiplier device10is approximately 115.284 mm2and the active surface is approximately 88.5% of the area of the photomultiplier device10.

FIG. 6shows a different layout according to an embodiment, wherein the wire-bonding pads35are arranged on the left side of the first column, between the second and the third columns, between the fourth and the fifth columns, between the sixth and the seventh columns, and to the right of the eighth column. In this case, with a side edge A of approximately 350 μm and all the other dimensions being approximately the same as described above in conjunction withFIG. 5, the active surface is approximately 88% of the area of the photomultiplier device10.

FIG. 7shows a part of a different embodiment, wherein the chips13still have a square or rectangular base, but have a bevelled corner44. By arranging four chips13with the bevelled corners44facing one another, an area45is formed where it may be possible to provide four wire-bonding pads35, one for each chip13that faces the area45. Also arranged at the center of each area45is a reference39. In this way, it may be possible to position and align the chips13with high precision and ensure an extensive active area. For the remaining portions of the device10, the cross-section of the photomultiplier device10is approximately the same as illustrated inFIG. 4. In this case, each chip loses an area of approximately 0.78 mm2on account of the bevelled corner44, but it may be possible to arrange the chips at a constant distance both in the rows and in the columns. In this case, an occupation of area of approximately 93% may be obtained.

The chamfer44can be obtained easily in the dicing step via laser techniques, and the chamfer may also present different shapes, such as that of the arc of a circumference so as to define as a whole a circular area, or an area having some other regular or irregular geometrical shape, for bonding.

FIG. 8is a cross section of a device10according to an embodiment including an intermediate substrate50, of semiconductor material (silicon), bonded to the base substrate11through an insulating adhesive layer51, in a conventional manner. Bonding wires34couple the chip pads38to respective intermediate pads53on the intermediate substrate50. In addition, in a way similar toFIG. 4, each chip13has a metal layer32bonded to corresponding pads (not shown) via respective conductive adhesive regions (which are not shown either). Alternatively, the chips13may not be metallized at the rear and each may have two or more chip pads38coupled to respective intermediate pads53. In this case, the chips13are bonded to the intermediate substrate50by means of insulating material, in a conventional manner. Moreover conductive paths (not shown) are provided on the intermediate substrate50and couple the intermediate pads53and the possible pads underneath the chips13to peripheral pads54. In turn, the peripheral pads54are coupled to wire-bonding pads35formed in the chip coupling level20through intermediate-coupling wires55. Here, the solder-mask layer40electrically insulates the wire-bonding pads and the intermediate substrate50with respect to each other. Also in this case, the thickness of the encapsulating layer14is such that the space above the bonding wires34is approximately 50-100 μm and thus approximately between 150 and 600 μm, typically approximately between 400 and 450 μm above the intermediate substrate, and is thicker only in the narrow edge area, where the wire-bonding pads35are present.

The embodiment ofFIG. 8can be used for example with the layout ofFIG. 9. Alternatively, the layout ofFIG. 6could be used.

The embodiment ofFIG. 8may have the advantage that the reference for positioning the chips can be provided on the intermediate silicon substrate50, and thus with a lower tolerance as compared to the embodiments ofFIGS. 4-7. In this way, it may be possible to further reduce the space between the chips13and thus optimize still further the occupation of area.

In this case, the manufacturing process differs from the one described above with reference toFIG. 4in that the chips13are initially bonded on the intermediate substrate50and then the wire couplings34are provided; next, the intermediate substrate50with the chips13is bonded by the insulating adhesive layer51to the base substrate11, and the intermediate-coupling wires55are provided.

In the embodiments ofFIGS. 10-12, each chip60houses four photomultiplier cells of the type shown schematically inFIG. 3. In particular, each chip60has four active areas61, electrically insulated from one another in a conventional manner (e.g., by junction or trench insulation).

Since four active areas61are integrated in a same body of semiconductor material (chip60), no metallization is present on the rear side of the chip60, as in the embodiments ofFIGS. 8 and 9. Consequently, on each chip60eight chip pads38are provided coupled via respective coupling wires63(FIG. 10) to corresponding pads53formed on the intermediate substrate50, similarly toFIG. 8.

FIGS. 11 and 12differ only as regards the position of the chip pads38: inFIG. 11, the chip pads38are arranged close to the respective active area, on the edges of the chip60; inFIG. 12all the chip pads38of the active areas are arranged along a same edge of the chip60. In the latter case, on the surface of the chip60, paths are provided, arranged between the active areas61so as to couple the two furthest active areas61to the chip pads38.

An embodiment of a process for manufacturing the photomultiplier device10ofFIGS. 10-12is similar to the one described for the embodiments ofFIGS. 8-9but without rear metallization.

FIG. 13shows an embodiment wherein the chips13, which each have integrated thereon a single photomultiplier cell8, are coupled to the substrate11(or the intermediate substrate50if present) by through vias.

In this case, the chips13have internal through vias, represented by dashed lines and designated by65inFIG. 13, which contact respective bumps66on the rear side of each chip. For example, each chip13has two through vias65(just one whereof is represented schematically), arranged diametrically and symmetrically with respect to the chip13and coupled to as many bumps66(only one whereof is visible for each chip13). For reasons of stability, on the rear side of each chip13another two auxiliary bumps67are formed (only one whereof is visible), which, however, are not electrically coupled to other elements and have the sole purpose of forming, with the bumps66, four resting points for each chip13.

The bumps66,67are bonded to upper pads36formed in the chip coupling level20; in particular, in this case, at least two upper pads36are provided for each chip (one for each bump66coupled to a respective through via65). For the remaining portions of the device10, the structure is similar to the one shown inFIG. 4.

Also in this case, the thickness of the encapsulating layer14is such that the space above the chips13is typically approximately between 150 and 200 μm, so that, in case of chips13having a thickness of approximately 250 μm, the thickness of the encapsulating layer14, above the solder-mask layer40, is typically approximately between 400 and 450 μm.

Such an embodiment enables further reduction of the dead areas due to the presence of the wire-bonding pads, thus increasing the percentage of active area with respect to the total surface of the photomultiplier device10.

Such an embodiment provides for through silicon vias (TSVs) made through the chips13during machining thereof, in a conventional manner.

An embodiment of the above-described photomultiplier device10can be used in an image-detecting system70of a PET type, shown schematically inFIG. 14and including a plurality of detector blocks71, a digital counter72, and a controller such as a processing unit73.

Each detector block71includes a photomultiplier device10, according to, for example, embodiments described in conjunction with any ofFIGS. 4-13, and a scintillator crystal18, bonded to the encapsulating layer14. The digital counter72is coupled to the photomultiplier devices10through couplings coupled to the pads in the external coupling level27and supplies the result of the counts to a processing unit73, for example integrated together with the digital counter in an ASIC, so as to process the data received and reconstruct the image of the examined structures, possibly with the aid of an external computer.

An embodiment of the photomultiplier device10described herein may have numerous advantages.

For example, encapsulation with the silicone layer14enables protection of the chips13,60during handling, transport, and storage of the photomultiplier device10. Since the silicone material is transparent at the considered operating wavelengths, it does not interfere with operation of the photomultiplier cells integrated in the chips13,60and bestows, together with the base substrate11, stiffness to the device. Warpage of the photomultiplier device10is thus prevented, which may not enable bonding of the device to the scintillator crystal18, or in any case may prevent a suitable quality of adhesion, thus possibly jeopardizing operation of the image detecting system. On the other hand, the slight resilience of the encapsulating layer14enables a sufficient adaptation thereof to any possible imperfections of the scintillator crystal18.

The use of the silicone material does not cause stress on the chips13,60at the considered operating temperatures, in view also of the low levels of operating current.

The chips13can be assembled in the photomultiplier device10so as to ensure reduced “dark” areas, i.e., a high ratio between the useful and the total area of the device, thus improving the efficiency of detection of the detection system that incorporates it.

In addition, it may be possible to generate current paths of substantially the same length for the signals generated in the chips13as far as the couplings on the external coupling level27. The structure of the base substrate11also enables a shielding of the routing paths and thus low levels of noise to be achieved.

Finally, it is clear that modifications and variations may be made to the photomultiplier device described and illustrated herein without thereby departing from the scope of the present disclosure.

For example, using suitable design techniques, it may be possible to generate signal paths within the base substrate11so that there are no intercouplings or cross-over points. In this case, the conductive levels or layers20-27may be reduced to six, with the elimination of the first routing level22or the second routing level25and one shielding level23,24or26.

In addition, when four active areas61are integrated on a single chip60, it may be possible to bond the multiple chips60directly on the base substrate11, instead of using an intermediate substrate50, by directly bonding the coupling wires63to the wire-bonding pads35.

Finally, also an embodiment where the multiple chip60accommodate a number of active areas61may be provided with through vias65and bumps66, as described above in conjunction withFIG. 13.