Self testing digital fault interrupter

A fault interrupter apparatus having a line side and a load side and a conductive path there between. The apparatus includes a solenoid that is adapted to move a plurality of contacts disposed in the conductive path from a first position to a second position, an alarm indicator that is adapted to provide status information on the operation of the fault interrupter apparatus, and a processor that is adapted to detect four condition states of the fault interrupter and indicate the four condition states of the fault interrupter using the alarm indicator.

CROSS-REFERENCE TO RELATED APPLICATION

Related subject matter is disclosed in U.S. Non-provisional Patent Application of John R. Baldwin et al., filed on Nov. 28, 2000, Ser. No. 09/722,423, entitled “Fault Interrupter Using Microprocessor for Fault Sensing and Automatic Self-Testing”, and in U.S. Non-provisional Patent Application of John R. Baldwin, filed on Mar. 4, 2002, Ser. No. 10/087,125, entitled “Digital Fault Interrupter With Self-Testing Capabilities”, the entire content of said applications being incorporated herein by reference.

FIELD OF THE INVENTION

The present invention relates generally to a self testing fault interrupting device, such as a ground fault circuit interrupter or an arc fault circuit interrupter. More particularly, the present invention relates to a self testing fault interrupting device where the self test is performed independent of a manual test.

BACKGROUND OF THE INVENTION

Fault interrupting devices are designed to trip in response to the detection of a fault condition at an AC load. The fault condition can result when a person comes into contact with the line side of the AC load and an earth ground, a situation which can result in serious injury. A ground fault circuit interrupter (GFCI) detects this condition by using a sense transformer to detect an imbalance between the currents flowing in the line and neutral conductors of the AC supply, as will occur when some of the current on the line side is being diverted to ground. When such an imbalance is detected, a relay or circuit breaker within the GFCI device is immediately tripped to an open condition, thereby removing all power from the load.

Many types of GFCI devices are capable of being tripped not only by contact between the line side of the AC load and ground, but also by a connection between the neutral side of the AC load and ground. The latter type of connection, which may result from a defective load or from improper wiring, is potentially dangerous because it can prevent a conventional GFCI device from tripping at the required threshold level of differential current when a line-to-ground fault occurs.

A ground fault is not the only class of potentially dangerous abnormal operating conditions. Another type of undesirable operating condition occurs when an electrical spark jumps between two conductors or from one conductor to ground also known as an arcing path. This spark represents an electrical discharge through the air and is objectionable because heat is produced as an unintentional by-product of the arcing. Such arcing faults are a leading cause of electrical fires.

Arcing faults can occur in the same places that ground faults occur; in fact, a ground fault would be called an arcing fault if it resulted in an electrical discharge, or spark, across an air gap. A device known as an arc fault circuit interrupter (AFCI) can prevent many classes of arcing faults. Both GFCIs and AFCIs are referred to as fault protection devices.

Conventional self testing fault protection devices typically provide a self test which replaces a user having to perform manually tests at fixed periods of time, for example, weekly, monthly, and so on. Because the user relies on the self testing fault protection device to perform self tests, the user may have a false sense of security. For example, many self testing fault protection devices only test for the opening and closing of contacts of the self testing fault protection device during the required fixed periods of time. If there is a defect with a component other than the contacts or a defect with another component prior to the fixed period of testing, a user can believe that the device is providing fault protection and can inadvertently be injured.

Also, as a solenoid of a fault protection device is operated over time, the semiconductor that is used to operate the solenoid can become degraded to a point where it approaches failure. This occurs because a 500 volt transient is placed across the transistor every time the solenoid is deenergized. Many manufacturers of fault protection devices place a diode between the solenoid and transistor. The diode is referred to as a suppressor diode. However, placing a suppressor diode between the solenoid and transistor significantly lengthens the time to open contacts to break a conductive path. United Laboratories (UL) requirements allow for a maximum time period within which the load must be disconnected from the power supply in the event of a ground fault or arc fault. Since a life may be involved, time is of the essence regarding quickly opening the contacts of the fault protection device.

Another problem with conventional fault protection devices is that their load or feed-through terminals are hard wired to the face receptacles of the GFCI and AFCI. Therefore, if a user miswires the GFCI or AFCI by connecting the hot and neutral lines to the load terminals, equipment plugged into the GFCI or AFCI via the face receptacles, the face receptacles can still be powered even if the GFCI or AFCI is in a tripped or off state. This can lead to potential injury to the user because the user would be under the impression that the GFCI or AFCI in a tripped condition always provides protection.

Still another problem with conventional fault protection devices is electrical sparks associated with the input power line sometimes occur when the contacts of the protection device close. The high temperatures associated with the electrical sparks sometimes melt the plastic housing of the protection device. Current solutions such as making the walls of the protection device thicker are not cost effective.

Yet another problem with conventional fault protection devices is that users are not adequately aware of the operational status of the GFCI. For example, in a typical fault protection device, there is a two-state alarm indication device. The two-state alarm indication device usually indicates that the fault protection device is in one of two states—operational or nonoperational. However, there may be situations where the fault protection device is functioning in a third-state. For example, there are situations where the fault protection device is operating as a normal receptacle. That is, the fault protection device no longer provides fault protection. However, a user may be content to operate the fault protection device in this mode. A third state serves as a constant reminder to the user of the status of the fault protection device. Conventional fault protection devices presently do not indicate the third-state.

Therefore a need also exists for a self testing fault protection device that does not simply test the contacts of the GFCI and AFCI at fixed time periods, but other components as well prior to the fixed time periods for testing the contacts.

There is a further need for a fault protection device which allows for a quick response in opening the contacts of the fault protection device without damaging the transistor or adding a delay in responding to a fault condition.

Still yet another need exists for a fault protection device that has face receptacles that are isolated from the load terminals.

Still another need exists for a fault protection device that allows the fault protection device to self test without providing a momentary interruption in power to current sensitive equipment.

Another need exists for a fault protection device that provides a tri-state alarm indication.

A further need exists for a structural housing that is resistant to burning or melting from the high temperatures related to electrical sparks. The structure should also provide an arrangement that maximizes space on a printed circuit board.

SUMMARY OF THE INVENTION

One aspect of the present invention provides a fault interrupter apparatus having a line side and a load side and a conductive path therebetween. The apparatus includes a solenoid that is adapted to move a plurality of contacts disposed in the conductive path from a first position to a second position, an alarm indicator that is adapted to provide status information on the operation of the fault interrupter apparatus, and a processor that is adapted to detect four condition states of the fault interrupter and indicate the four condition states of the fault interrupter using the alarm indicator.

Another aspect of the present invention provides a fault interrupter apparatus having a line terminals and load terminals and a conductive path therebetween. The apparatus comprises a fault sensing transformer that is adapted to detect a fault condition in the conductive path, a solenoid that is adapted to move a plurality of contacts disposed in the conductive path from a first position when the solenoid is deenergized or to a second position when the solenoid is energized, a switch that is adapted to place said solenoid in the energized state in the absence of the fault condition and in the deenergized state in the presence of the fault condition, and a varistor that is adapted to protect said switch from transient voltage when the solenoid goes from the energized state.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

FIG. 1is a perspective view of an example of a fault indication and protection circuit10in accordance with an embodiment of the present invention. The fault indication and protection circuit10can be a ground fault circuit interrupter (GFCI), an arc fault circuit interrupter (AFCI) and/or perform the functions of both an AFCI and GFCI. However, for purposes of illustration, the fault indication and protection circuit10will be described as a GFCI device10. The GFCI device10comprises a housing12having a cover portion14and a rear portion16. The GFCI device10also includes a barrier between the cover portion14and the rear portion (SeeFIGS. 12 and 13) when the cover portion14is removed from the rear portion16. The cover portion14and rear portion are removably secured to each other via fastening means such as clips, screws, brackets, tabs and the like. The cover portion includes face receptacles (also known as plugin slots)18and20and grounding receptacles22. It will be appreciated by those skilled in the art that face receptacles18and20and grounding receptacles22can accommodate polarized, non-polarized, grounded or non-grounded blades of a male plug. The male plug can be a two wire or three wire plug without departing from the scope of the present invention. The GFCI device10further includes mounting strap24having mounting holes26for mounting the GFCI receptacle10to a junction box (not shown). At the rear wall of the housing12is a grounding screw28for connecting a ground conductor (not shown).

A test button30extends through opening32in the cover portion14of the housing12. The test button is used to activate a test operation that tests the operation of the circuit interrupting portion disposed in the GFCI device10. The circuit interrupting portion, to be described in more detail below, is used to break electrical continuity in one or conductive paths between the line and load side of the GFCI device10. A reset button34extends through opening36in the cover portion14of the housing12. The reset button34is used to activate a reset operation, which reestablishes electrical continuity in the open conductive paths.

Rear portion16has four screws, only two of which are shown inFIG. 1. Load terminal screw38is connected to a neutral conductor and a load terminal screw37(SeeFIG. 4) is connected to the hot conductor. Line terminal screw40is connected to the neutral conductor and a line terminal screw39(SeeFIG. 4) is connected to the hot conductor. It will be appreciated by those skilled in the art that the GFCI receptacle10can also include apertures proximate the line and load terminal screws37,38,39and40to receive the bare end of conductors rather than connecting the bare end of the wires to the line and load terminal screws.

GFCI device10also has an alarm indicator42for providing an indication to a user that GFCI device10is operating normally, the conductive path between the line and load terminals is open, or the GFCI device10is operating as a receptacle without fault protection.

Alarm indicator42comprises a bi-color light emitting diode (LED), which provides a first color when a first chip is activated, a second color when a second chip is activated, and in accordance with an embodiment of the present invention, a third color when both chips are activated. As discussed in more detail below, an embodiment of the present invention, the alarm indicator42illuminates to provide a green color when the GFCI device10is operating normally and providing GFCI protection, illuminates red when the conductive path between the line and load terminals is open, and illuminates solid green and flashing red color when the GFCI device10is operating as a normal receptacle and not providing ground fault protection. When the alarm indicator42is solid green and flashing red, a third color, orange, results when red and green are illuminated simultaneously. It should be appreciated by those skilled in the art that although the alarm indicator is described as being a dual chip LED, two separate single LEDs, a single LED having a single filament, or a buzzer can be used to provide an alarm indication without departing from the scope of the present invention. In addition, two separate lamps or a bicolored lamp can be used. If a single LED or lamp is used, the LED or lamp can have different flash rates to provide various status indications to a user.

FIG. 2is a schematic diagram of a ground fault circuit interrupter in accordance with a first embodiment of the present invention, in which a conventional GFCI chip is employed in combination with a microprocessor to operate the GFCI. The GFCI device10employs a GFCI chip100with an output102to a microprocessor104. Microprocessor104is preferably a Type PIC12F629 or PIC12F675 microprocessor manufactured by Microchip, located in Chandler, Ariz. A transistor122is powered, via the microprocessor104, to energize solenoid101, thus closing contacts62,66,68and72to establish a conductive path between line terminals39and40and faceplate receptacles18and20and load or feedthrough terminals37and38.

In an embodiment of the present invention, the PIC12F675 microprocessor104is used where there is a need for a I/O port to accept more than one condition. For example, as an option, the test button30and reset button34can share an I/O port. A voltage divider can be used to distinguish whether the test or reset button was pressed. Another option would be to eliminate test button30and use reset button34as a test/reset button. For example, microprocessor104would distinguish a first press of the button as being a test and a second press of the button as being a reset.

The GFCI device10employs three sets of contacts, namely contacts62and68,64and70, and66and72. Contact62establishes electrical continuity between line terminal39and load terminal37via hot conductor58and path74. Contact68establishes electrical continuity between line terminal40and load terminal38via neutral conductor60and path76. Contacts66and72establish electrical continuity between the line terminals39and40and face terminals18and20via hot conductor58and neutral conductor60, respectively. The isolation of contacts66and72from the load terminals37and38prevent the face terminals18and20from being powered if the GFCI device10is mistakenly wired so that power source41is connected to the load terminals37and38. It should be noted that GFCI device10is structured and arranged to permit the electronics of the circuit to only be powered when the GFCI device10is wired from the line terminals39and40via a power source. If a power source41is connected to the load terminals37and38, the electronics of the GFCI device10cannot be powered to close contacts62and68, which are driven closed by energization of the solenoid101. Before power is applied contacts62and68are open, and contacts64and70are closed. As discussed in more detail below, opto-isolater92detects when contacts64and70are closed by detecting current from the line side on hot conductor58and neutral conductor60via conductors77and78. It should be noted that contacts62and68are the primary contacts, which close the connection between the line and load terminals. Contacts64and70are the auxiliary contacts, which provide an indication to opto-isolater92that contacts62and68are open. In operation, when the primary contacts62and68are closed, the auxiliary contacts are open and vice versa. This function can be performed by a single pole double throw switch, for example.

The contacts62and68and66and72are opened and closed simultaneously by a solenoid101preferably having specifications as detailed in TABLE 1 below. A suitable solenoid101is available from Bicron Electronics located in Canaan, Conn. having a footprint of about 0.650 square inch, an aspect ratio of about 1.500, and dimensions of about 0.650 inch in height, 0.650 inch in width, and 1.00 inch in length. It should be appreciated by those skilled in the art that the subject invention is not limited to the types of solenoids mentioned, alternate types of solenoids can be substituted without departing from the scope of the present invention.

The detection of a ground fault condition at a load connected to one of the face receptacles18,20or to the load terminals37and38, is implemented by a current sense transformer54, the GFCI chip100which has a direct input into the microprocessor104via line102, as well as other interconnecting components. The GFCI chip100is preferably a Type RV4145N integrated circuit manufactured by Fairchild Semiconductor, located in South Portland, Me. The GFCI chip100and the microprocessor104are powered from the line terminals39and40by a full-wave bridge rectifier46and filter capacitor47. A transient voltage suppressor44is connected across the line terminals39and40to provide protection from voltage surges due to lightning and other transient conditions. As the transients increase, the voltage suppressor44absorbs energy.

Within the GFCI device10, the hot conductor58, as mentioned above, connects the line terminal39to the load line terminal37, and neutral conductor60connects the line terminal40to the load terminal38, in a conventional manner. The conductors58and60pass through the magnetic cores52and56of the two transformers50and54, respectively. The transformer54serves as a differential sense transformer for detecting a leakage path between the line side of the AC load and an earth ground (not shown), while the transformer50serves as a grounded neutral transformer for detecting a leakage path between the neutral side of the AC load and an earth ground. In the absence of a ground fault, the current flowing through the conductors58and60are equal and opposite, and no net flux is generated in the core56of the differential sense transformer54. In the event that a connection occurs between the line side of the AC load and ground, however, the current flowing through the conductors58and60no longer precisely cancel, and a net flux is generated in the core56of the differential sense transformer54. This flux gives rise to a potential at the output of the secondary coil55, and this output is applied to the input of the GFCI chip100to produce a trip signal on the output line102. As mentioned above, this output is fed directly into the microprocessor104via pin108, which in turn controls the operation of solenoid101to open the contacts62,66,68and70. This closes contacts64and70to remove the AC power from the face receptacles18and20and the load or feedthrough terminals37and38.

Since the GFCI chip100is a commercially available component, its operation is well known to those skilled in the art, and need not be described in detail. In utilizing the GFCI chip100, resistor88serves as a feedback resistor for setting the gain of the controller and hence its sensitivity to normal faults. Capacitors80and84provide noise filtering at the inputs of the controller. Capacitor82AC couples low frequency signals out of the sense transformer54, to the GFCI chip's100internal operational amplifier (not shown).

The contacts62,66,68and72are in a closed state while contacts64and70are in an open state when the solenoid101is energized. This state will be referred to as the normal state or close state. However, when the solenoid101is not energized, the contacts62,66,68, and72are in an open state while contacts64and70are in a closed state. This state will be referred to as an abnormal or open state.

In operation, a ground fault can occur via a manual or self-test, or an actual ground fault, for example when a person comes into contact with the line side of the AC load and an earth ground at the same time. In a manual test described in more detail below, a user presses test button30. Test button30is connected between the hot conductor58and neutral conductor60. When the test button30is pressed, an imbalance is detected by sense transformer54. Specifically, the current passes through resistor31, the core52of the ground transformer, the core56of the sense transformer54via the hot conductor58. However, for the return path bypass conductor57is used rather than the neutral conductor60. Since there is no canceling current in the opposite direction, sense transformer54detects the current imbalance. The microprocessor104determines the existence of faults via the GFCI chip100. As discussed above, the GFCI chip100detects a fault condition via transformers50and54. GFCI chip100communicates the fault condition via a signal to pin108of the microprocessor104using line out102. The microprocessor104then deenergizes the solenoid101via transistor122. Since the microprocessor104has no way of knowing whether a ground fault was triggered by an actual fault or by a manual fault simulated by pressing test button30, the microprocessor104always reacts as if an actual fault condition has occurred.

The microprocessor104also does not know whether the actual fault has been removed until a user presses the reset button34. When the reset button34is pressed, an input is provided to pin110and the microprocessor104closes the contacts. If the fault is still present, the microprocessor104will detect the condition via GFCI chip100and reopen the contacts immediately as discussed above. If a manual test was performed, the fault will no longer be present and microprocessor104will close the contacts and check for the existence of faults. If there are no faults the GFCI device10returns to normal operation.

In an embodiment of the present invention, a self test is performed on the fault detection portion of the GFCI device10. In this example, the self test is preferably performed at 1 minute intervals, but the microprocessor104can be programmed to perform testing at any interval of time. During the self test the microprocessor104communicates a signal to the SCR48, which creates an imbalance similar to that caused by closing test button30that is detected by the transformers50and54. The GFCI chip10communicates the imbalance to the pin108of microprocessor104via the line out102. The microprocessor104is aware that it initiated the fault condition and expects to receive the signal from the GFCI chip100. Therefore, the microprocessor104does not control the solenoid to open the contacts62,66,68and72. If the microprocessor104does not receive the expected signal from the GFCI chip100, it determines that the fault detection portion of GFCI10is defective and activates the red LED42B in a manner which will be described below. In an embodiment of the invention, at the next one minute interval, the microprocessor104drops pin114for 200 microseconds to ground. The collector of transistor122goes high for 200 microseconds and the microprocessor104detects this condition via pin118. Thus, two portions of the GFCI device10is tested. The GFCI chip100, which detects a fault condition and the transistor which deenergizes the solenoid101. It should be appreciated that in the one minute test the solenoid is not deenergized. Rather, the transistor122is tested and the voltage at the collector of the transistor is detected via pin118. If the correct conditions are detected at the collector and/or the resistance of the solenoid is within parameters, it is assumed that the solenoid101is operational. It should further be appreciated by those skilled in the art that the two portions of the one minute test can be performed separately via separate one minute tests or can be performed as one test within a one minute time interval.

In another embodiment of the present invention, a self test is performed on the circuit interruption portion of the GFCI device10. This self test is preferably performed at daily intervals, but the microprocessor104can be controlled to perform this test at any desired interval. During testing, the microprocessor104communicates a signal to the SCR48, which creates an imbalance in the transformers50and54. The GFCI chip10communicates the imbalance to the pin108of microprocessor104via the line out102. The microprocessor104then deenergizes the contacts62,68,66and72via pin114. The contacts open and go to the auxiliary contact position64and70. Now, diode current is in the opto-isolater92. The opto-isolator92puts out a signal across resistor132into pin116of the microprocessor104. The opto-isolater92signals the microprocessor104that the contacts62,68,66and72are open, and that contacts64and70are closed. The microprocessor104opens the contacts62,68,66and72momentarily (preferably for a period of time not to exceed 20 msec.), in order to avoid disrupting the load during the daily self test.

In an embodiment of the present invention, if the GFCI device10determines that the one minute periodic test failed, the one minute test can be repeated and if the test failed again, the contacts62,68,66and72can be opened instantly.

In another embodiment of the present invention, when the microprocessor10detects the nonfunctioning of GFCI device10during either the periodic minute or daily test, the GFCI10can be optioned to provide a lockout feature wherein a user cannot reset the contacts of GFCI device10. However, the lockout feature will not take affect if a manual test was performed.

The automatic daily self-test, mentioned above, is performed on a periodic basis. The microprocessor104can maintain a software record of the current state of the contacts62,68,66and72(i.e., either open or closed) and conducts an automatic self-test only if normal operation is in progress with the contacts62,68,66and72being closed. During a self-test, pin112is brought high by the microprocessor104to drive the SCR48gate for 5 msec. Pin108looks for a 3.8 ms pulse from the GFCI chip100. When pin108receives a pulse, pin114is asserted low by the microprocessor104to open the contacts62,68,66and72momentarily. The microprocessor104checks pin116for a low signal indicating that the contacts64and70are closed which indicates that contacts62,68,66and72opened for 20 msec and then re-closed. After contacts62,68,66and72open for <20 ms, pin114is asserted high and the contacts62,68,66and72re-close.

In an embodiment of the present invention, the microprocessor104monitors the AC sinusoidal signal and performs the self test only when the sinusoidal signal is not a zero crossing point. For example, the transistor122is driven low when the sinusoidal signal is at its peak.

In another embodiment of the present invention, the microprocessor104does not monitor the zero crossing of the sinusoidal signal. Rather, the microprocessor104performs two self tests within 4.2 ms apart. This prevents the self test from accepting a false positive caused by the test occurring at a zero crossing point being initiated at a zero crossing point.

In still another embodiment of the present invention, the GFCI device10can be optioned by a user to convert from a unit that performs both a daily and one minute periodic test to a unit that only performs a periodic one minute test and vice versa.

The invention will now be described with reference to green LED42A and red LED alarm indicator42B both of which comprise alarm indicator42. During normal operation of the GFCI device10, the solenoid101is energized via pin114of the microprocessor104. This high condition causes the green LED42A to be illuminated. The red LED42B is off since it is not powered. Specifically, the voltage applied to the anode of red LED42B is insufficient to drive red LED42B.

During a fault condition, the microprocessor104detects the fault condition in the manner described above. Pin114of the microprocessor goes to ground, thus removing power from the solenoid101and causing the green LED42A to go out. The collector of the transistor122rises, and current is provided through resistor130which enables a sufficient voltage to appear at the anode of red LED42B to cause the red LED42B to illuminate.

In the case where a self test was performed and it was determined that GFCI10is nonfunctional, the microprocessor104drops the signal on pin114to zero which deenergizes the solenoid101and turns off the green LED42A. The collector of the transistor122goes high causing the red LED42B to illuminate as described above. However, since the GFCI device10is nonfunctional, the user needs to be aware of this condition. Pin118of the microprocessor104periodically shunts the red LED42B anode to ground with diode120, which causes the red LED42B to flash.

In the case where it was determined that the GFCT device10is nonfunctional, the user has the option of resetting the GFCI device10and close the contacts62,68,66and72. The red LED42B continues to flash. The microprocessor104detects the pressing of the reset button34via pin110. Pin114then goes high, thus energizing the solenoid101and illuminating the green LED42A. Since the red LED42B continues to flash, a user sees the illuminated green LED42A when the red LED42B is off and orange when the red LED42B and green LED42A are on simultaneously.

In an embodiment of the present invention, varistor98is used across the transistor122to protect the transistor from transient voltages that occur when the solenoid101is energized or deenergized.

In another embodiment of the present invention, a resistor in series with a diode is placed between solenoid101and transistor122to reduce the transient voltage on the transistor122. Specifically, the diode and resistor are sized to obtain optimal balance between reduced transient voltage and increased response time for opening the contacts of the GFCI device10.

In still another embodiment of the present invention, the transistor's intrinsic collector to emitter breakdown energy handling capability is utilized to provide a GFCI without the need for separate transient voltage protection e.g., a varistor.

FIG. 3is a schematic diagram of a ground fault circuit interrupter in accordance with a second embodiment of the present invention, which is simular to the first embodiment ofFIG. 1, but additionally providing redundant contacts for allowing a self test without a power interrupt on the load side of the GFCI. The GFCI device310operates in a similar manner to GFCI device10. Only the differences between the two embodiments will be discussed for conciseness. Redundant contacts262and268,264and270, and266and272mirror the operation of the primary contacts62and68,64and70, and66and72, respectively. For example, when a primary contact is open, a respective secondary contact should be closed and vice versa.

Referring to GFCI device310, when a daily self test is performed, the microprocessor204communicates a signal to the SCR48, which creates an imbalance in the transformers50and54. The GFCI chip100communicates the imbalance to the pin208of microprocessor204via the line out102. The microprocessor204then energizes solenoid201via pin210which closes redundant contacts262,266,268and272providing a secondary path for current between the line and load terminals39and40, and37and38. Opto-isolater292detects that contacts264and270are open and changes the signal level on pin216of the microprocessor204e.g., a PIC12F675 with analog I/O ports. The microprocessor204records this change and continues with the daily self test. Microprocessor204provides a signal on pin214which deenergizes solenoid101which results in contacts62and68, and66and72being open. Opto-isolater92detects the position of contacts64and70and provides a change in signal level on pin216of the microprocessor204. The microprocessor204then communicates a signal via pin214which energizes solenoid101and closes contacts62and68, and66and72. This causes contacts64and70to open. Since the opto-isolater92removes its contribution to the signal via pin216, the microprocessor204knows that contacts62and68, and66and72will be re-closed in a few milliseconds. After a few milliseconds of delay, the microprocessor204then communicates a signal via pin216which causes solenoid201to deenergize and open redundant contacts262,266,268and272. This closes contacts264and270which the opto-isolater292detects and signals the microprocessor204via pin210. Thus, the primary contacts can be momentarily opened and closed without a user detecting a power interrupt.

It should be appreciated by those skilled in the art that the present invention can be practiced with only one opto-isolater without departing from the scope of the invention. For example, opto-isolater292can be omitted and opto-isolater92can remain in the circuit to confirm that the primary contacts opened. In addition, microprocessor204can be modified to detect the opening and closing of the primary contacts.

In an embodiment of the present invention, a third conductor, connected to SCR48passes through the transformers50and56and provides a path between the hot conductor and the neutral conductor to provide a current imbalance when a self test is performed.

In still another embodiment of the present invention, rather than deenergize the solenoid101momentarily during a self test, the energy to the solenoid is increased.

FIG. 4is a perspective view illustrating components of the ground fault circuit interrupter disposed on the inner housing of the GFCI in accordance with an embodiment of the present invention. The GFCI device10ofFIG. 4comprises a printed circuit board17, line terminals39and40, load terminals37and38, solenoid101, solenoid plunger400, supporting walls401, brush terminal supports402, brushes404, and a location for the auxiliary contacts406. Supporting walls401is comprised of a plastic known as Rynite, which is a member of the family comprising Polyethylene Terephtalate. It should be appreciated by those skilled in the art that other plastics comprising the family of plastics known as Polyethylene Terephtalate can be substituted without departing from the scope of the present invention. Rynite provides the housing with structural integrity and high resistance to heat caused by electrical sparks.FIG. 5shows a top view of the PCB13including various components. For example, supporting walls401is shown providing structural support to brush terminal supports402and contacts66and72. Specifically, contacts66and72are in an open position.

InFIG. 6, a top view of the PCB13is also shown. However, supporting walls401is not shown. Brush supports402and contacts66and72are shown as being mounted to the PCB13.FIG. 7shows a top view of the PCB13without any terminals and contacts andFIG. 8shows the inner housing13from a bottom view.FIGS. 7 and 8both show a plurality of apertures408disposed within the inner housing. The spacing of the plurality of apertures allow components such as the brush terminal supports402, brushes404, upper walls401, solenoid101solenoid plunger400, and contacts62,64,66,68,70and72to be arranged with precision. For example, when solenoid101is energized, the plunger400moves in the direction of A bringing the brushes404in contact with contacts62,68,66and72as shown inFIG. 9. When the solenoid is deenergized the plunger moves in the direction of B bringing the contacts in contact with contacts64and70as shown inFIG. 10. Since space on a printed circuit board is limited, there is not a great amount of room for the movement of solenoid101. However, the arrangement shown inFIG. 4allows the contacts to make contact with the least amount of distance possible and also be in a position of disengagement with the least amount of space possible. As shown inFIG. 11, the face terminal contacts66and72are separate from the primary contacts62and68. Thus, if the GFCI device10was wired from the load side, the face receptacles18and20would not be powered. It should be noted that upper walls401provide support and guidance for the plunger400.

FIG. 12Ashows a partially assembled sub-assembly of GFCI device10. The receptacle barrier15and rear portion16of the GFCI is shown. Specifically, hot conductor58and neutral conductor60are shown making contact with face receptacles18and20. The conductors58and60are ultrasonically welded when the GFCI10is being assembled.FIG. 12Bshows a completed sub-assembly. Specifically, the receptacle barrier15is mounted to the rear portion16of the GFCI10.FIGS. 13 and 14show detailed views of the receptacle barrier15.

Those skilled in the art can now appreciate from the foregoing description that the broad teachings of the present invention can be implemented in a variety of forms. Therefore, while this invention can be described in connection with particular examples thereof, the true scope of the invention should not be so limited since other modifications will become apparent to the skilled practitioner upon a study of the drawings, specification and following claims.