Power conversion device

A power converter includes an arm in which a plurality of converter cells are connected in series, each of the converter cells including at least two switching elements, a power storage element and a pair of output terminals. A control device controls the power converter. The converter cell includes a switch to have the converter cell bypassed. When the control device senses failure of the converter cell, it has the failed converter cell bypassed, estimates an output voltage lost by bypassing the failed converter cell, and has a normal converter cell supply the estimated output voltage of the failed converter cell.

TECHNICAL FIELD

The present invention relates to a power conversion device.

BACKGROUND ART

A modular multilevel converter (which will be referred to as an MMC converter below) in which a plurality of unit converters (which will be referred to as converter cells below) are cascaded can readily address a high voltage by increasing converter cells. The modular multilevel converter has widely been applied to power transmission and distribution systems as a high-capacity static var compensator or an alternating-current (AC)-direct-current (DC) power conversion device for high-voltage DC power transmission. The converter cell includes a plurality of switching elements and a power storage element (which may be referred to as a capacitor). Even when a converter cell fails in the MMC converter, the MMC converter can continue operating by bypassing the failed converter cell.

PTL 1 describes an operation method without requiring adjustment of a modulation factor of each arm by adjusting the number of operating converter cells in each arm in accordance with the number of failures in an arm largest in number of failed converter cells and increasing a capacitor voltage.

CITATION LIST

Patent Literature

SUMMARY OF INVENTION

Technical Problem

PTL 1, however, does not consider a harmonic component in an arm current that increases after bypass of the failed converter cell.

An output voltage from a converter cell in the MMC converter contains a harmonic component such as a switching frequency component, an integer-order component thereof, and a sideband wave component thereof (which will simply be referred to as a harmonic component below), in addition to a frequency component included in an arm voltage command value such as a fundamental wave component on an AC output side (simply a fundamental wave component below) and a DC component. The MMC converter adopting phase shift pulse width modulation (PWM) cancels a harmonic component in an output voltage from each converter cell by equally shifting a PWM reference phase for each converter cell in each arm. A switching frequency of the output voltage from the arm can thus be made higher.

When a converter cell fails and the failed converter cell is bypassed, however, an output voltage from the failed converter cell becomes zero. Since an amount of shift of the PWM reference phase is thus no longer equal, the harmonic component in the output voltage from each converter cell cannot be canceled. Consequently, the harmonic component in the output voltage from each converter cell remains in the output voltage from the arm. Energy of the harmonic component is thus concentrated in some converter cells. Consequently, capacitor voltages of some converter cells deviate from a protection level and the MMC converter may stop operating for a protection purpose.

Therefore, an object of the present invention is to provide a power conversion device capable of suppressing a harmonic component in an output voltage from an arm that increases after bypass of a failed converter cell.

Solution to Problem

A power conversion device according to the present invention includes a power converter including an arm in which a plurality of converter cells are connected in series, each of the plurality of converter cells including at least two switching elements, a power storage element, and a pair of output terminals, and a control device to control the power converter. The converter cell includes a switch to have the converter cell bypassed. When the control device senses failure of a converter cell, the control device has a failed converter cell bypassed, estimates an output voltage lost by bypass of the failed converter cell, and has a normal converter cell supply the estimated output voltage of the failed converter cell.

Advantageous Effects of Invention

According to the present invention, a harmonic component in an arm current that increases after bypass of a failed converter cell can be suppressed.

DESCRIPTION OF EMBODIMENTS

First Embodiment

(Overall Configuration of Power Conversion Device)

FIG. 1is a schematic configuration diagram of a power conversion device1in an embodiment. Referring toFIG. 1, power conversion device1is configured of a modular multilevel converter which includes multiple converter cells connected in series. Note that the “converter cell” is also called a “sub-module,” SM, or a “unit converter.” Power conversion device1converts power between a DC circuit14and an AC circuit12. Power conversion device1includes a power converter2and a control device3.

Power converter2includes multiple leg circuits4u,4v,4w(will be described as a leg circuit4when referred to collectively or when referring to any leg circuit) which are connected in parallel between a positive DC terminal (i.e., a high-potential-side DC terminal) Np and a negative DC terminal (i.e., a low-potential-side DC terminal) Nn.

Leg circuit4is provided for each of multiple phases constituting an alternating current. Leg circuit4is connected between AC circuit12and DC circuit14, and converts power between the circuits. AC circuit12shown inFIG. 1is a three-phase AC circuit which includes three leg circuits4u,4v,4wcorresponding to a U phase, a V phase, and a W phase, respectively.

AC input terminals Nu, Nv, Nw provided for respective leg circuits4u,4v,4ware connected to AC circuit12via a transformer13. AC circuit12is, for example, an AC power system which includes an AC power supply, etc. For ease of illustration,FIG. 1does not show the connection between AC input terminals Nv, Nw and transformer13.

High-potential-side DC terminal Np and low-potential-side DC terminal Nn, which are connected in common to each leg circuit4, are connected to DC circuit14. DC circuit14is, for example, a DC power system, including a DC power grid, or a DC terminal of other power conversion devices. In the latter case, a BTB (Back To Back) system for connecting different AC power systems having different rated frequencies is formed by coupling two power conversion devices.

AC input terminals Nu, Nv, Nw may be connected to AC circuit12via an interconnection reactor, instead of transformer13inFIG. 1. Furthermore, instead of AC input terminals Nu, Nv, Nw, a primary winding may be provided for each of leg circuits4u,4v,4w, and leg circuits4u,4v,4wmay be connected to transformer13or an interconnection reactor in an AC manner via a secondary winding magnetically coupled to the primary winding. In this case, the primary winding may be reactors8A,8B described below. In other words, leg circuit4is electrically (i.e., a DC manner or an AC manner) connected to AC circuit12via the connector provided for each of leg circuits4u,4v,4w, such as AC input terminals Nu, Nv, Nw or the above primary winding.

Leg circuit4uincludes an upper arm5from high-potential-side DC terminal Np to AC input terminal Nu, and a lower arm6from low-potential-side DC terminal Nn to AC input terminal Nu. AC input terminal Nu, which is the point of connection between upper arm5and lower arm6, is connected to transformer13. High-potential-side DC terminal Np and low-potential-side DC terminal Nn are connected to DC circuit14. Leg circuits4v,4whave the same configuration as leg circuit4u, and leg circuit4uwill thus be representatively described below.

Upper arm5includes multiple cascade-connected converter cells7and reactor8A. Multiple converter cells7and reactor8A are connected in series. Similarly, lower arm6includes multiple cascade-connected converter cells7and reactor8B. Multiple converter cells7and reactor8B are connected in series. In the description below, the number of converter cells7included in each of upper arm5and lower arm6is set to Ncell. Ncell is set to Ncell≥2.

Reactor8A may be inserted anywhere in upper arm5of leg circuit4u. Reactor8B may be inserted anywhere in lower arm6of leg circuit4u. Multiple reactors8A and multiple reactors8B may be present. The reactors may have different inductance values. Furthermore, only reactor8A of upper arm5may be provided, or only reactor8B of lower arm6may be provided.

Reactors8A,8B are provided to prevent a rapid increase of a fault current in the event of a fault of AC circuit12or DC circuit14, for example. However, reactors8A,8B having excessive inductance values result in reduced efficiency of power converter2. Accordingly, preferably, all the switching elements of each converter cell7are stopped (turned off) as soon as possible in the event of a fault.

As detectors for measuring the electrical quantities (current, voltage, etc.) for use in the control, power conversion device1further includes an AC voltage detector10, an AC current detector16, DC voltage detectors11A,11B, and arm current detectors9A,9B. Arm current detectors9A,9B are provided for each leg circuit4. Signals detected by these detectors are input to control device3.

Note that, for ease of illustration, inFIG. 1, some of signal lines for the signals input from the detectors to control device3and signal lines for the signals input/output to/from control device3and each converter cell7are depicted collectively, but they are, in practice, provided for each detector and each converter cell7. The signal lines may be provided separately for transmission and reception of the signals between each converter cell7and control device3. For example, an optical fiber may be adopted as the signal line.

In the following, each detector is described in detail.

AC voltage detector10detects a U-phase AC voltage Vacu, a V-phase AC voltage Vacv, and a W-phase AC voltage Vacw of AC circuit12. In the description below, Vacu, Vacv, and Vacw are collectively denoted as Vac.

AC current detector16detects a U-phase AC current Iacu, a V-phase AC current lacy, and a W-phase AC current Iacw of AC circuit12. In the description below, Iacu, lacy, and Iacw are collectively denoted as Iac.

DC voltage detector11A detects a DC voltage Vdcp of high-potential-side DC terminal Np connected to DC circuit14. DC voltage detector11B detects a DC voltage Vdcn of low-potential-side DC terminal Nn connected to DC circuit14. A difference between DC voltage Vdcp and DC voltage Vdcn is defined as a DC voltage Vdc.

Arm current detectors9A and9B, included in leg circuit4ufor U phase, respectively detect an upper arm current Ipu flowing through upper arm5and a lower arm current Inu flowing through lower arm6. Arm current detectors9A and9B, included in leg circuit4vfor V phase, detect an upper arm current Ipv and a lower arm current Inv, respectively. Arm current detectors9A and9B, included in leg circuit4wfor W phase, detect an upper arm current Ipw and a lower arm current Inw, respectively. In the description below, upper arm currents Ipu, Ipv, and Ipw are collectively denoted as an upper arm current Iarmp, lower arm currents Inu, Inv, and Inw are collectively denoted as a lower arm current Iarmn, and upper arm current Iarmp and lower arm current Iarmn are collectively denoted as Iarm.

FIGS. 2 (a) and (b)is a diagram showing a configuration of converter cell7that makes up power converter2.

Converter cell7shown inFIG. 2 (a)has a circuit configuration called a half-bridge configuration. This converter cell7includes a serial body formed by connecting two switching elements31pand31nto each other in series, a power storage element32, a bypass switch34, and a voltage detector33. The serial body and power storage element32are connected in parallel.

Opposing terminals of switching element31nare defined as input and output terminals P1and P2. A voltage across ends of power storage element32and a zero voltage are provided as a result of switching operations by switching elements31pand31n. For example, when switching element31pis turned on and switching element31nis turned off, the voltage across ends of power storage element32is provided. When switching element31pis turned off and switching element31nis turned on, the zero voltage is provided.

Bypass switch34is connected between input and output terminals P1and P2. By turning on bypass switch34, converter cell7is short-circuited. As converter cell7is short-circuited, switching elements31pand31nincluded in converter cell7are protected against an overcurrent produced at the time of a fault.

Voltage detector33detects a voltage Vc across ends of power storage element32.

Converter cell7shown inFIG. 2 (b)has a circuit configuration called a full-bridge configuration. This converter cell7includes a first serial body formed by connecting two switching elements31p1and31n1to each other in series, a second serial body formed by connecting two switching elements31p2and31n2to each other in series, power storage element32, bypass switch34, and voltage detector33. The first serial body, the second serial body, and power storage element32are connected in parallel.

A point intermediate between switching element31p1and switching element31n1and a point intermediate between switching element31p2and switching element31n2are defined as input and output terminals P1and P2of converter cell7. The voltage across ends of power storage element32or the zero voltage is provided as a result of switching operations by switching elements31p1,31n1,31p2, and31n2.

Bypass switch34is connected between input and output terminals P1and P2. By turning on bypass switch34, converter cell7is short-circuited. As converter cell7is short-circuited, each element included in converter cell7is protected against an overcurrent produced at the time of a fault.

Voltage detector33detects voltage Vc across ends of power storage element32.

InFIGS. 2 (a) and (b), switching elements31p,31n,31p1,31n1,31p2, and31n2are configured, for example, by connection of a freewheeling diode (FWD) in anti-parallel to a self-arc-extinguishing semiconductor switching element such as an insulated gate bipolar transistor (IGBT) and a gate commutated turn-off (GCT) thyristor.

InFIGS. 2 (a) and (b), a capacitor such as a film capacitor is mainly employed as power storage element32. Power storage element32may be referred to as a capacitor in the description below.

An example in which converter cell7has the half-bridge cell configuration shown inFIG. 2 (a), a semiconductor switching element is employed as the switching element, and a capacitor is employed as the power storage element will be described below by way of example. Converter cell7included in power converter2, however, may have the full-bridge configuration shown inFIG. 2 (b). A converter cell in a configuration other than the configuration shown above, such as a converter cell to which a circuit configuration called a clamped double cell is applied, may be employed, and the switching element and the power storage element are not limited to the above either.

FIG. 3is a diagram showing an internal configuration of control device3in a first embodiment.

Control device3includes a switching controller501and a bypass controller510.

Switching controller501controls on and off of switching elements31pand31nin converter cell7.

When bypass controller510senses failure of converter cell7within the arm, it protects failed converter cell7within the arm against an overcurrent by turning on bypass switch34in failed converter cell7.

Switching controller501includes a U-phase basic controller502U, a U-phase upper arm controller503UP, a U-phase lower arm controller503UN, a V-phase basic controller502V, a V-phase upper arm controller503VP, a V-phase lower arm controller503VN, a W-phase basic controller502W, a W-phase upper arm controller503WP, and a W-phase lower arm controller503WN.

In the description below, U-phase basic controller502U, V-phase basic controller502V, and W-phase basic controller502W are collectively denoted as a basic controller502. U-phase upper arm controller503UP, U-phase lower arm controller503UN, V-phase upper arm controller503VP, V-phase lower arm controller503VN, W-phase upper arm controller503WP, and W-phase lower arm controller503WN are collectively denoted as an arm controller503.

FIG. 4is a diagram showing a configuration of basic controller502.

Basic controller502includes an arm voltage command generator601and a capacitor voltage command generator602.

Arm voltage command generator601calculates an arm voltage command value krefp for the upper arm and an arm voltage command value krefn for the lower arm. In the description below, krefp and krefn are collectively denoted as kref.

Capacitor voltage command generator602calculates a capacitor command voltage value Vcrefp for capacitors32in N converter cells7included in the upper arm. Capacitor voltage command generator602calculates a capacitor command voltage value Vcrefn for capacitors32in N converter cells7included in the lower arm. For example, an average voltage of capacitors32in converter cells7in the upper arm is defined as capacitor command voltage value Vcrefp and an average voltage of capacitors32in converter cells7in the lower arm is defined as capacitor command voltage value Vcrefn. In the description below, Vcrefp and Vcrefn are collectively denoted as Vcref.

Arm voltage command generator601includes an AC current controller603, a circulating current calculator604, a circulating current controller605, and a command distributor606.

AC current controller603calculates an AC control command value Vcp such that a difference between detected AC current Iac and a set AC current command value Iacref is set to 0.

Circulating current calculator604calculates a circulating current Iz that flows through one leg circuit4based on arm current Iarmp in the upper arm and arm current Iarmn in the lower arm. The circulating current is a current that circulates among a plurality of leg circuits4. For example, circulating current Iz that flows through one leg circuit4can be calculated in accordance with an expression below.
Idc=(Ipu+Ipv+Ipw+Inu+Inv+Inw)/2  (1)
Iz=(Iarmp+Iarmn)/2−Idc/3  (2)

Circulating current controller605calculates a circulation control command value Vzp for controlling circulating current Iz to follow a set circulating current command value Izref such as 0.

Command distributor606receives AC control command value Vcp, circulation control command value Vzp, a DC voltage command value Vdcref, a neutral point voltage Vsn, and AC voltage Vac. Since an AC side of power converter2is connected to AC circuit12with transformer13being interposed, neutral point voltage Vsn can be calculated based on a voltage of a DC power supply of DC circuit14. DC voltage command value Vdcref may be provided under DC output control or may be set to a constant value.

Based on these inputs, command distributor606calculates voltages to be supplied by the upper arm and the lower arm in a burden-sharing manner. Command distributor606determines arm voltage command value krefp for the upper arm and arm voltage command value krefn for the lower arm by subtracting voltage lowering due to an inductance component within the upper arm and the lower arm from respective calculated voltages.

Determined arm voltage command value krefp for the upper arm and arm voltage command value krefn for the lower arm serve as output voltage commands to control AC current Iac to follow AC current command value Iacref, to control circulating current Iz to follow circulating current command value Izref, to control DC voltage Vdc to follow DC voltage command value Vdcref, and to feedforward-control AC voltage Vac.

Basic controller502provides arm current lump of the upper arm, arm current Iarmn of the lower arm, arm voltage command value krefp for the upper arm, arm voltage command value krefn for the lower arm, capacitor command voltage value Vcrefp for the upper arm, and capacitor command voltage value Vcrefn for the lower arm.

FIG. 5is a diagram showing a configuration of arm controller503.

When arm controller503senses failure of converter cell7, it has failed converter cell7bypassed and estimates an output voltage missed due to bypass of failed converter cell7. Arm controller503has normal converter cell7provide the estimated output voltage of failed converter cell7.

Arm controller503includes Ncell individual cell controllers202and a cell additional voltage calculator203.

Individual cell controller202individually controls corresponding converter cell7. Individual cell controller202receives arm voltage command value kref, arm current Iarm, and capacitor command voltage value Vcref from basic controller502. Individual cell controller202receives a capacitor voltage Vc and a cell normality determination signal cn from corresponding converter cell7. The cell normality determination signal is set to “1” when converter cell7is normal, and the cell normality determination signal is set to “0” when converter cell7has failed. Individual cell controller202receives a cell additional voltage signal dcvm from cell additional voltage calculator203.

Individual cell controller202generates a gate signal ga for corresponding converter cell7and provides the gate signal to corresponding converter cell7. Individual cell controller202generates a lost output voltage signal cvm for corresponding converter cell7and provides the lost output voltage signal to cell additional voltage calculator203.

FIG. 6is a diagram showing a configuration of individual cell controller202.

Individual cell controller202includes an individual cell balance controller2021, a PWM modulator2022, signal switches2023A,2023B,2023C, and2023D, a cell output voltage estimator2024, and an adder2051.

Signal switch2023A receives cell additional voltage signal dcvm provided from cell additional voltage calculator203and a zero signal representing a zero voltage. Signal switch2023A provides a signal selected depending on cell normality determination signal cn. When converter cell7is normal, cell normality determination signal cn is set to “1” and cell additional voltage signal dcvm is provided. When converter cell7fails, cell normality determination signal cn is set to “0” and the zero signal is provided.

Individual cell balance controller2021provides an individual cell balance control output dkrefc such that capacitor voltage Vc matches with capacitor command voltage value Vcref based on capacitor command voltage value Vcref, capacitor voltage Vc of corresponding converter cell7, and arm current Iarm. For example, individual cell balance controller2021can generate individual cell balance control output dkrefc based on a result of multiplication of a difference between Vcref and Vc by a gain K.

Signal switch2023B receives individual cell balance control output dkrefc and a zero signal representing a zero voltage. Signal switch2023B provides a signal selected depending on cell normality determination signal cn. When converter cell7is normal, cell normality determination signal cn is set to “1” and individual cell balance control output dkrefc is provided. When converter cell7fails, cell normality determination signal cn is set to “0” and the zero signal is provided.

Adder2051adds a signal provided from signal switch2023A, a signal provided from signal switch2023B, and arm voltage command value kref. A result of addition is provided as cell voltage command value krefc.

PWM modulator2022provides a PWM modulated signal by modulating cell voltage command value krefc in accordance with phase shift PWM with a carrier reference phase CRP and a dead time DT being defined as parameters. PWM modulator2022performs modulation depending on a configuration of converter cell7. Depending on the configuration of converter cell7, the number n of provided PWM modulated signals also increases or decreases. For example, in the case of a half-bridge cell, n is set to n=2, and in the case of a full-bridge cell, n is set to n=4.

When there are Ncell converter cells7in one arm, intervals among Ncell PWM carrier reference phases CRP within one arm become even by allocating phases different by 360°/Ncell to PWM modulators2022in converter cells7within one arm. Thus, a harmonic component in the output voltage from each converter cell7can be canceled and an equivalent switching frequency of the output voltage from one arm can be high. When converter cell7fails and the output voltage from failed converter cell7becomes zero, however, the harmonic component in the output voltage from each converter cell7cannot be canceled. Consequently, the harmonic component in the output voltage from each converter cell7remains in the output voltage from the arm.

Signal switch2023C receives the PWM modulated signal and a zero signal representing a zero voltage. Signal switch2023C provides a signal selected depending on cell normality determination signal cn. When converter cell7is normal, cell normality determination signal cn is set to “1” and the PWM modulated signal is provided. When converter cell7fails, cell normality determination signal cn is set to “0” and the zero signal is provided. The signal provided from signal switch2023C is sent to a gate driver for switching elements31pand31nin corresponding converter cell7as gate signal ga to control switching of switching elements31pand31nin corresponding converter cell7.

Cell output voltage estimator2024receives the PWM modulated signal. Cell output voltage estimator2024estimates the output voltage from corresponding converter cell7when switching elements31pand31nare switched in response to the PWM modulated signal. Cell output voltage estimator2024provides an estimation signal pcv representing magnitude of the estimated cell output voltage. Specifically, cell output voltage estimator2024estimates the output voltage from corresponding converter cell7as the zero voltage or the capacitor voltage, depending on whether switching elements31pand31nin corresponding converter cell7are turned on or off in response to the PWM modulated signal. Specifically, cell output voltage estimator2024estimates the output voltage from corresponding converter cell7as capacitor voltage Vc (voltage across ends of power storage element32) when switching element31pis turned on and switching element31nis turned off in response to the PWM modulated signal to switching element31pand the PWM modulated signal to switching element31n. Cell output voltage estimator2024estimates the output voltage from corresponding converter cell7as the zero voltage when switching element31pis turned off and switching element31nis turned on in response to the PWM modulated signal to switching element31pand the PWM modulated signal to switching element31n.

Though only the PWM modulated signal is assumed to be provided to cell output voltage estimator2024for the sake of brevity, arm current Iarm may be provided thereto. In this case, cell output voltage estimator2024can estimate the output voltage during a dead time period based on arm current Iarm. Specifically, when switching element31pis turned off and switching element31nis turned off in response to the PWM modulated signal to switching element31pand the PWM modulated signal to switching element31n, cell output voltage estimator2024estimates the output voltage from corresponding converter cell7in accordance with an orientation of arm current Iarm. The output voltage from corresponding converter cell7can thus highly accurately be estimated.

Signal switch2023D receives estimation signal pcv and a zero signal representing magnitude of a zero voltage. Signal switch2023D provides a signal selected depending on cell normality determination signal cn. When converter cell7is normal, cell normality determination signal cn is set to “1” and the zero signal is provided as lost output voltage signal cvm representing magnitude of an estimated value of the lost output voltage. When converter cell7fails, cell normality determination signal cn is set to “0” and estimation signal pcv is provided as lost output voltage signal cvm. Specifically, when converter cell7fails, individual cell controller202estimates based on the PWM modulated signal, a voltage that should have been provided from that converter cell7if converter cell7had been normal, and provides a result of estimation to cell additional voltage calculator203.

FIG. 7is a diagram showing a configuration of cell additional voltage calculator203.

Cell additional voltage calculator203includes a lost output voltage addition unit2031, a normal cell calculator2032, and a divider2033.

Lost output voltage addition unit2031adds lost output voltage signals cvm estimated and calculated in Ncell individual cell controllers202and provides a total lost output voltage signal ccvm representing the total of lost output voltages of at least one failed converter cell7in the arm.

Normal cell calculator2032adds Ncell cell normality determination signals cn. A result of addition represents the number of normal converter cells (the number of normal cells below) within the arm.

Divider2033divides total lost output voltage signal ccvm by the number sc of normal cells and provides cell additional voltage signal dcvm representing a result of division. Cell additional voltage signal dcvm represents magnitude of an additional output voltage allocated to one normal converter cell7within the arm. Cell additional voltage signal dcvm is sent to signal switch2023A of individual cell controller202.

According to the configuration, power conversion device1in the first embodiment can continue operating even when converter cell7fails.

(Operations by Control Device3)

Operations by control device3in each of a case where all converter cells7are normal and a case where at least one converter cell7has failed will be described below.

(Operations when all Converter Cells7within Arm are Normal)

Operations by control device3when all converter cells7within the arm are normal will be described.

When all converter cells7within the arm are normal, cell normality determination signals cn for all converter cells7within the arm are set to “1”. Since the zero signal is provided from signal switch2023D in all individual cell controllers202within the arm, all lost output voltage signals cvm are set to 0. Thus, cell additional voltage signal dcvm provided from cell additional voltage calculator203is also set to 0. In other words, when all converter cells7within the arm are normal, cell additional voltage signal dcvm is set to 0.

In individual cell controller202, signal switch2023B provides individual cell balance control output dkrefc provided from individual cell balance controller2021. Signal switch2023A provides cell additional voltage signal dcvm (=0) provided from cell additional voltage calculator203.

Adder2051adds arm voltage command value kref, individual cell balance control output dkrefc, and cell additional voltage signal dcvm (=0) to obtain cell voltage command value krefc representing a result of addition.

PWM modulator2022performs PWM modulation on cell voltage command value krefc and provides the PWM modulated signal. Signal switch2023C provides the PWM modulated signal. The PWM modulated signal provided from signal switch2023C is sent to the gate driver for switching elements31pand31nin converter cell7as gate signal ga to control switching of switching elements31pand31nin converter cell7.

(Operations when Failed Converter Cell7is Included within Arm)

Operations by control device3when failed converter cell7is included within the arm will be described.

When at least one failed converter cell7is included in the arm, cell normality determination signal cn for failed converter cell7is set to “0”. Thus, in individual cell controller202corresponding to failed converter cell7, signal switch2023D provides estimation signal pcv as lost output voltage signal cvm.

Lost output voltage signal cvm is provided to cell additional voltage calculator203, and cell additional voltage signal dcvm representing magnitude of the additional output voltage allocated to one normal converter cell7within the arm is obtained.

(Operations by Normal Converter Cell)

In individual cell controller202in normal converter cell7, signal switch2023A provides cell additional voltage signal dcvm and signal switch2023B selects and provides individual cell balance control output dkrefc.

Adder2051adds cell additional voltage signal dcvm, individual cell balance control output dkrefc, and arm voltage command value kref, and provides cell voltage command value krefc representing a result of addition.

PWM modulator2022performs PWM modulation on cell voltage command value krefc and provides the PWM modulated signal. Signal switch2023C provides the PWM modulated signal. The PWM modulated signal provided from signal switch2023C is sent to the gate driver for switching elements31pand31nin converter cell7as gate signal ga to control switching of switching elements31pand31nin converter cell7.

(Operations by Failed Converter Cell) In individual cell controller202in failed converter cell7, signal switches2023A and2023B both provide the zero signal, and hence cell voltage command value krefc provided from adder2051is equal to arm voltage command value kref.

PWM modulator2022performs PWM modulation on cell voltage command value krefc and provides the PWM modulated signal, whereas signal switch2023C provides the zero signal. Therefore, gate signal ga is the zero signal. Switching elements31pand31nin converter cell7are thus turned off.

As a result of the operations above, the lost output voltage which should have been provided from failed converter cell7within the arm is included in the cell voltage command value for normal converter cell7within the arm. Therefore, the output voltage lost as a result of bypass of failed converter cell7is supplied from normal converter cell7. Thus, a voltage harmonic that has been provided from failed converter cell7is vicariously supplied from normal converter cell7and a harmonic current that increases due to absence of a counter voltage can be suppressed. Consequently, power conversion device1can continue operating without protective suspension of power conversion device1due to deviation of capacitor voltages of some converter cells7from the protection level.

First Modification of First Embodiment

Though cell output voltage estimator2024estimates the output voltage of failed converter cell7based on the PWM modulated signal in the description above, a method of estimation is not limited. For example, cell output voltage estimator2024may estimate the output voltage of failed converter cell7based on a carrier reference phase of failed converter cell7and the cell voltage command value.

Second Modification of First Embodiment

Though corresponding individual cell controllers202of all normal converter cells7within the arm are described as calculating the cell voltage command value resulting from addition of the cell additional voltage in the description above, limitation thereto is not intended. Corresponding individual cell controllers202of some normal converter cells7within the arm may calculate the cell output voltage command value resulting from addition of the cell additional voltage so as to have some normal converter cells7within the arm supply a counter voltage. In this case, cell additional voltage calculator203calculates cell additional voltage signal dcvm by dividing total lost output voltage signal ccvm representing the sum of lost output voltages of failed converter cells7by the total number of some normal converter cells7within the arm. Cell additional voltage signal dcvm represents magnitude of the additional voltage allocated to one of some normal converter cells7within the arm.

(Hardware Configuration of Control Device3)

FIG. 8is a diagram showing an exemplary hardware configuration of control device3.

Control device3is configured similarly to what is called a digital relay device. Control device3includes an analog-digital (AD) converter unit530, an arithmetic processing unit535, an input and output (IO) unit543, and a settling-and-display unit547.

In a stage preceding AD converter unit530, a plurality of transformers (not shown) to convert input signals from arm current detectors9A and9B, AC voltage detector10, AC current detector16, DC voltage detectors11A and11B, and voltage detector33to a voltage level suitable for signal processing within control device3may be provided.

AD converter unit530includes an analog filter531and an AD converter532. Analog filter531is a low-pass filter provided to remove an aliasing error in AD conversion. AD converter532converts the signal that has passed through analog filter531into a digital value.

WhileFIG. 8representatively shows only one channel as the input to AD converter unit530, AD converter unit530, in practice, has a multiple-input configuration to receive the signals from the respective detectors. Accordingly, more specifically, AD converter unit530includes multiple analog filters531, and a multiplexer (not shown) for selecting signals having passed through analog filters531.

Arithmetic processing unit535includes a central processing unit (CPU)536, a memory537, bus interfaces538,539, and a bus540connecting these components. CPU536controls the entire operation of control device3. Memory537is used as a primary storage for CPU536. Furthermore, by including a nonvolatile memory, such as a flash memory, memory537stores programs, and settings values for the signal processing.

Note that arithmetic processing unit535may be configured of any circuit that has computing functionality, and is not limited to the example ofFIG. 8. For example, arithmetic processing unit535may include multiple CPUs. Instead of the processor such as CPU, arithmetic processing unit535may be configured of at least one ASIC (Application Specific Integrated Circuit), or at least one FPGA (Field Programmable Gate Array). Alternatively, arithmetic processing unit535may be configured of any combination of the processor, ASIC, and FPGA.

IO unit543includes a communication circuit544, a digital input circuit545, and a digital output circuit546. Communication circuit544generates an optical signal to be provided to each converter cell7. The signal provided from communication circuit544is transmitted to converter cell7through an optical repeater555. Digital input circuit545and digital output circuit546are interface circuits for communication between CPU536and external devices.

Settling-and-display unit547includes a touch panel548for inputting settling values and for display. Touch panel548is an input/output interface which is a combination of a visual display, such as a liquid crystal panel, and an input device, such as a touchpad. Touch panel548is connected to bus540via a bus interface539.

Second Embodiment

It is when an AC output current and a DC output current from power converter2are low and an effective value of an arm current is small that there is a concern about imbalance in capacitor voltages in normal converter cells7due to increase in harmonic component of arm current Iarm when converter cell7fails.

Though individual cell balance control is sufficiently effective when the effective value of the arm current is large, it may not be sufficiently effective when the effective value of the arm current is small.

AC output power and DC output power, however, are determined by a higher-order command. Therefore, the AC output current and the DC output current cannot freely be set. Since a circulating current of a DC component and an AC fundamental wave component is basically used for controlling balance in average value of each phase of capacitor voltages of converter cells7or controlling balance in average value between the upper arm and the lower arm, there is no degree of freedom.

In a second embodiment, when the AC output current and the DC output current from power converter2are low to such an extent that the capacitor voltages of converter cells7within the arm are not balanced, a current at a frequency different from a frequency of a current provided from power converter2is circulated within power converter2. Since the effective value of the arm current is thus larger, individual cell balance control is sufficiently effective and imbalance among converter cells7is rectified. The current at the frequency different from the frequency of the current provided from power converter2refers to a current other than a DC current and an AC current (a current of the fundamental wave) provided from AC circuit12.

FIG. 9is a diagram showing a configuration of control device3in the second embodiment.

Control device3in the second embodiment includes switching controller501and bypass controller510similarly to control device3in the first embodiment and includes a cell balancing circulating current controller610.

When cell balancing circulating current controller610senses failure of converter cell7in any of the plurality of arms, it has a current circulated within power converter2in order to increase the effective value of arm current Iarm, the current having a frequency different from the frequency of the current provided from power converter2.

FIG. 10is a diagram showing a configuration of cell balancing circulating current controller610.

Cell balancing circulating current controller610includes a first coordinate converter611, a compensator612, and a second coordinate converter613.

First coordinate converter611converts circulating current components Izu, Izv, and Izw of three phases of U, V, and W onto a dq two-phase coordinate that rotates at a frequency θ different from the frequency of the current provided from power converter2. Resultant Izd represents an effective component and Izq represents a reactive component, both of which represent a DC quantity.

Compensator612provides two-phase DC voltage command components Vzdref and Vzqref such that two-phase circulating current components Izd and Izq follow circulating current command components Izdref and Izqref converted to the two phases.

Second coordinate converter613converts two-phase DC voltage command components Vzdref and Vzqref calculated by compensator612to three-phase DC voltage command circulating current components Vdccu, Vdccv, and Vdccw. V DC voltage command circulating current components dccu, Vdccv, and Vdccw are sent to arm voltage command generators601of U-phase basic controller502U, V-phase basic controller502V, and W-phase basic controller502W, respectively. In the description below, Vdccu, Vdccv, and Vdccw are collectively denoted as Vdcc.

FIG. 11is a diagram showing a configuration of arm voltage command generator601in the second embodiment.

Command distributor606receives AC control command value Vcp, circulation control command value Vzp, DC voltage command value Vdcref, neutral point voltage Vsn, and AC voltage Vac as in the first embodiment and receives DC voltage command circulating current component Vdcc.

Command distributor606calculates based on these inputs, voltages to be supplied by the upper arm and the lower arm as in the first embodiment. Command distributor606determines arm voltage command value krefp for the upper arm and arm voltage command value krefn for the lower arm by subtracting voltage lowering due to an inductance component within the upper arm and the lower arm from the calculated voltages.

Since the effective value of arm current Iarm increases according to the present embodiment, the fundamental wave that makes up the cell voltage command value is larger. Consequently, individual cell balance control is sufficiently effective and imbalance among converter cells7is rectified.

Third Embodiment

In the present embodiment, transformer13is defined as a transformer variable in transformation ratio. The transformer variable in transformation ratio is implemented, for example, by a transformer with a tap switching function.

Since AC output power and DC output power are determined by a higher-order command in the second embodiment, the AC output current and the DC output current are described as not freely being set.

Power conversion device1is interconnected to AC circuit12with transformer13being interposed. Therefore, by varying the transformation ratio of transformer13, AC output current Vac can be varied without affecting AC output power and DC output power. Since the effective value of arm current Iarm can thus be increased, imbalance among converter cells7can be rectified.

FIG. 12is a diagram showing a configuration of control device3in a third embodiment.

Control device3in the third embodiment includes switching controller501and bypass controller510as in the first embodiment and includes a transformer controller504.

When transformer controller504senses failure of converter cell7in any of the plurality of arms, it varies the transformation ratio of transformer13in order to increase the effective value of arm current Iarm. Specifically, the AC current that flows from AC circuit12to power conversion device1is increased by lowering a ratio N (V2/V1) between a voltage V1on a side of AC circuit12of transformer13and a voltage V2on a side of power conversion device1. Since the effective value of arm current Iarm thus increases, the fundamental wave that makes up the cell voltage command value is larger. Consequently, influence of a harmonic can be lessened.

Fourth Embodiment

FIG. 13is a diagram showing a configuration of a power conversion device1A in a fourth embodiment.

Power conversion device1A in the fourth embodiment is different from power conversion device1in the first embodiment in that each arm in a power converter2A of power conversion device1A in the fourth embodiment includes a redundant converter cell (RSM)7a. Redundant converter cell7ais similar in configuration to converter cell7shown inFIGS. 2 (a) and (b).

Redundant converter cell7ain each arm is bypassed before occurrence of failure in any converter cell7within each arm. Therefore, during this period, redundant converter cell7adoes not perform a conversion operation.

Bypass of redundant converter cell7ain each arm is canceled after occurrence of failure in any converter cell7within each arm. Therefore, during this period, redundant converter cell7aperforms the conversion operation instead of converter cell7that has failed.

Before any converter cell7within the arm fails, bypass controller510turns on bypass switch34of redundant converter cell7awithin that arm. After any converter cell7within the arm fails, bypass controller510turns off bypass switch34of redundant converter cell7awithin that arm.

As set forth above, in the present embodiment, after any converter cell7within each arm fails, redundant converter cell7aperforms the conversion operation instead of converter cell7that has failed. Thus, even when converter cell7fails, the number of converter cells that operate in one arm does not vary and a harmonic component in the output voltage from the converter cell can be canceled.

The number of redundant converter cells7awithin the arm is not limited to one but a plurality of redundant converter cells may be provided. Redundant converter cell7awithin the arm does not have to be fixed. A redundant converter cell may be selected every certain cycle, sequentially, or randomly, from among a plurality of converter cells that have not failed.

The present invention is not limited to the embodiments above but includes also modifications as below.

(1) Configuration of Power Converter2

In the embodiment above, power converter2is in a configuration called a double star. Power converter2is mainly used as an AC-DC converter for high voltage direct current (HVDC) power transmission. Control of the power converter described in the embodiment above is also applicable to a power converter in another configuration.

FIG. 14is a diagram showing a configuration of a part of a power conversion device1B.

A power converter2B of power conversion device1B is in a configuration called a single delta. Power converter2B is mainly used for a static var compensator.

FIG. 15is a diagram showing a configuration of a part of a power conversion device1C.

A power converter2C of power conversion device1C is in a configuration called a single star. Power converter2C is also mainly used for a static var compensator.

A scheme for suppressing a harmonic produced due to failure of converter cell7as described in the embodiments above is effective also in power converters2B and2C. In power converter2C including an output only on the AC side, a circulating current described in the second embodiment may be a current at a frequency other than a fundamental wave component. For example, a circulating current containing a DC component may flow.

(2) Though triangular wave comparison PWM modulation is described by way of example, sawtooth wave comparison PWM modulation in which carriers are sawtooth waves may be applicable and carriers are not restricted. In a case of space voltage vector PWM modulation as well, by adding a function to achieve a similar effect, a converter can continue operating also in case of failure in a converter cell.

(3) Control described in the embodiment above may intermittently operate when imbalance in capacitor voltage among converter cells7is aggravated.

(4) Converter Cell for Circulating Current Control

When an arm includes a common converter cell and a converter cell for controlling a circulating current, the configuration of the basic controller is different from that shown inFIG. 4.

FIG. 16is a diagram showing a configuration of a basic controller502A in a modification.

Basic controller502A inFIG. 16is different from basic controller502inFIG. 4in that circulation control command value Vzp provided from basic controller502A is not provided to a command distributor606A.

Command distributor606A receives AC control command value Vcp, DC voltage command value Vdcref, neutral point voltage Vsn, and AC voltage Vac. Based on these inputs, command distributor606A calculates voltages to be supplied by the upper arm and the lower arm. Command distributor606A determines arm voltage command value krefp for the upper arm and arm voltage command value krefn for the lower arm by subtracting voltage lowering due to an inductance component within the upper arm and the lower arm from the calculated voltages. A signal to control common converter cells within the arm is generated based on arm voltage command value krefp and arm voltage command value krefn for the lower arm, as described in the first embodiment.

A not-shown control block provides a PWM modulated signal to the converter cell for circulator control based on circulation control command value Vzp provided from basic controller502A.

REFERENCE SIGNS LIST