Method of preparing detectors for oxide bonding to readout integrated chips

In one embodiment, a method of preparing detectors for oxide bonding to an integrated chip, e.g., a readout integrated chip, includes providing a wafer having a plurality of detector elements with bumps thereon. A floating oxide layer is formed surrounding each of the bumps at a top portion thereof. An oxide-to-oxide bond is formed between the floating oxide layer and an oxide layer of the integrated chip which is provided in between corresponding bumps of the integrated chip. The oxide-to-oxide bond enables the bumps on the detector elements and the bumps on the integrated chip to be intimately contacted with each other, and removes essentially all mechanical stresses on and between the bumps. In another embodiment, a device has an interconnect interface that includes the oxide-to-oxide bond and an electrical connection between the bumps on the detector elements and the bumps on the integrated chip.

BACKGROUND

The present disclosure relates to a method of preparing detectors with bumps thereon for oxide bonding to integrated chips, and a device utilizing oxide-bonded bumps.

Conventionally, an indium-to-indium cold-welding process is utilized to bond detectors, for example, HgCdTe detectors to readout integrated chips. The indium-to-indium cold-welding process requires application of high external pressure and force to form the bond. Indium, being a weak material, is subject to breakage on application of such high external pressure/force. In addition, the indium-to-indium cold-welding process may also cause mechanical damage to the detectors due to the application of the high external pressure/force.

These and other drawbacks to conventional approaches exist.

SUMMARY

The present disclosure address these and other drawbacks in conventional approaches relating to a method of preparing detectors with bumps thereon for oxide bonding to integrated chips.

In one embodiment, a method includes providing a wafer having a plurality of detector elements with bumps thereon; forming a layer of polymer between each of the bumps; depositing an oxide layer on a top portion of each of the bumps and the polymer layer; forming a plurality of vias in the oxide layer between adjacent bumps; and removing the polymer layer such that a remaining oxide layer forms a floating oxide layer, the floating oxide layer surrounding each of the bumps at the top portion thereof.

In one embodiment, a microelectronic device is fabricated. The microelectronic device includes a detector array having a plurality of detector elements with bumps thereon, each of the bumps having a floating oxide layer surrounding the bumps at a top portion thereof; an integrated chip having corresponding bumps thereon and an oxide layer in between the bumps; and an interconnect interface between the corresponding bumps on the integrated chip and the bumps on the detector elements. The interconnect interface includes an oxide-to-oxide bond between the floating oxide layer and the oxide layer of the integrated chip, the oxide-to-oxide bond providing a structural bond between the detector elements and the integrated chip and removing essentially all mechanical stresses on and between the bumps on the integrated chip and the bumps on the detector elements; and an electrical connection between each of the corresponding bumps on the integrated chip and the bumps on the detector elements.

Various other features and aspects of this disclosure will be apparent through the detailed description of various embodiments and the drawings attached hereto. It is also to be understood that both the foregoing general description and the following detailed description are exemplary and not restrictive of the scope of the inventive concept.

DETAILED DESCRIPTION

FIG. 1is an exemplary flowchart of operations performed for preparing detector elements with bumps thereon for oxide bonding. In operation110, a wafer having a plurality of detector elements with bumps thereon is provided. In one embodiment, as shown in aspects of a method illustrated inFIGS. 2-10, a detector device200comprises wafer210having a plurality of detector elements220a,220b,220c, . . . ,220nwith bumps230a,230b,230c, . . . ,230nthereon. In one embodiment, detector device200may be an infrared detector device used in thermal imaging applications. In one embodiment, detector elements220a, . . . ,220nmay be photodiodes or photoconductors that detect infrared radiation or radiation in another wavelength band of interest. In one embodiment, detector elements220a, . . . ,220nform a detector array, for example, a focal plane array, or other type of detector array. In one embodiment, detector elements220a, . . . ,220nmay be fabricated from HgCdTe or InSb semiconductor material that is capable of detecting radiation at various wavelengths, e.g., at infrared wavelengths. Other kinds of semiconductor materials may be used to fabricate the detector elements. In one embodiment, bumps230a, . . . ,230nare indium bumps.

Referring back toFIG. 1, optionally, a barrier layer may be formed on each of the bumps in operation120. In one embodiment, as shown inFIG. 3, barrier layer310may be formed on each of bumps230a,230b, . . . ,230n. In one embodiment, barrier layer310may comprise a plurality layers, for example, first layer320, second layer330, and/or other layers. In one embodiment, first layer320is a diffusion barrier layer that may serve as a diffusion barrier between bumps230a,230b, . . . ,230n, and second layer330. In one embodiment, first layer320may be a metal nitride layer. In one embodiment, second layer330may be a metal contact layer comprising Ziptronix® metal. In one embodiment, first layer320may prevent Ziptronix® metal from second layer330from diffusing into indium bumps230a,230b, . . . ,230n. In one embodiment, barrier layer310may be formed by first depositing first layer320onto bumps230a,230b, . . . ,230n, and then depositing second layer330onto first layer320. In one embodiment, deposition of second layer on first layer320may be performed at a temperature of less than or equal to 100° C. Elevated temperatures could result in damage to certain sensitive components resulting, at least in part, from the semiconductor material that is used to fabricate the detector elements. For example, a temperature of 170° C. might be acceptable for a short period of time; however, a temperature of more than 100° C. for an extended period of time may not be acceptable depending on the particular semiconductor materials used.

Referring back toFIG. 1, in operation130, a layer of polymer may be formed between each of the bumps230a,230b, . . . ,230n. In one embodiment, as shown inFIG. 4A, a layer of polymer410may be formed between bumps230a,230b, . . . ,230n, wherein at least a top portion420of each of the bumps is exposed. In one embodiment, polymer layer410may be formed by performing the following operations: forming a layer of polymer430on and in between each of the bumps230a,230b, . . . ,230n(as shown inFIG. 4B, for example); and then, thinning down polymer layer430such that polymer layer410is formed in between the bumps230a,230b, . . . ,230n, and such that at least a top portion420of each of the bumps230a,230b, . . . ,230nis exposed. In one embodiment, the thinning down of polymer layer430may be performed by a process that uses de-ionized water. In one embodiment, the thinning down of polymer layer430may be performed by an etching process that uses a mixture of de-ionized water and isopropyl alcohol. In one embodiment, polymer layer410/430may be a soluble polymer layer. In another embodiment, polymer layer410/430may be a water soluble polymer layer. In one embodiment, polymer layer410/430may be polyethylene glycol, for example, PEG-10000. In one embodiment, polymer layer430may be formed by warming the polymer to a temperature of about 60-100° C. to improve flow characteristics, and then dispensing the polymer on a spinner device as conventionally used for application of photoresist. In one embodiment, polymer layer430may be formed by adding a solvent to the polymer to improve flow characteristics, and then removing the solvent by baking.

Referring back toFIG. 1, in operation140, an oxide layer may be deposited on a top portion of each of the bumps and the polymer layer. In one embodiment, as shown inFIG. 5, oxide layer510may be deposited on top portion420of each of the bumps230a,230b, . . . ,230nand polymer layer410. In one embodiment, oxide layer510may be deposited by a sputtering process. In one embodiment, oxide layer510may be deposited by a chemical vapor deposition process. In one embodiment, deposition of oxide layer510may be performed at a temperature less than the melting point of the polymer used, in order to avoid undesirable non-uniformities.

Referring back toFIG. 1, in operation150, a plurality of vias may be formed in the oxide layer between adjacent bumps. In one embodiment, as shown inFIG. 6A, vias610may be formed in oxide layer510in between adjacent bumps230a,230b, . . . ,230n. In one embodiment, vias610may be formed by performing the following operations: applying a photoresist layer620on oxide layer510(as shown in, for example,FIG. 6B); patterning the photoresist layer620for the formation of vias between the adjacent bumps230a,230b, . . . ,230n(not shown); etching oxide layer510through the photoresist later620to form vias610in oxide layer510between adjacent bumps230a,230b, . . . ,230n(as shown in, for example,FIG. 6C); and removing the photoresist layer620to expose vias610(as shown in, for example,FIG. 6A). In one embodiment, before the formation of vias in the oxide layer510, the oxide layer may be planarized such that a top surface thereof710is aligned with a top surface720of each of the bumps230a,230b, . . . ,230n(as shown inFIG. 7, for example). In one embodiment, the photoresist layer620may be applied by dispensing the photoresist onto a spinning wafer using conventional semiconductor processing equipment. In one embodiment, hydrofluoric acid may be used to etch the oxide layer510. In one embodiment, the oxide layer510may be dry etched in a plasma system.

Referring back toFIG. 1, in operation160, the polymer layer is removed such that the remaining oxide layer (for example, oxide layer remaining after the formation of vias in the oxide layer) forms a floating oxide layer surrounding each of the bumps at the top portion thereof. In one embodiment, as shown inFIG. 8, polymer layer410may be removed such that the remaining oxide layer forms a floating oxide layer810surrounding each of the bumps230a,230b, . . . ,230nat the top portion420thereof. The floating oxide layer810floats above the detector elements220a,220b, . . . ,220nand does not contact the surfaces of the detector elements220a,220b, . . . ,220nor surfaces of wafer210. In one embodiment, the polymer layer410may be removed by performing a de-ionization rinse.

In one embodiment, floating oxide layer810may be utilized for oxide bonding of detector elements220a,220b, . . . ,220nto an integrated chip, for example, a readout integrated chip. As shown inFIG. 9, readout integrated chip900is provided with a plurality of corresponding bumps930a,930b, . . . ,930nand an oxide layer910in between the corresponding bumps930a,930b, . . . ,930n. It will be appreciated that even though oxide layer910is shown surrounding the corresponding930a,930b, . . . ,930n, the oxide layer may be formed on the entire surface between the bumps.

In one embodiment, optionally, corresponding bumps930a,930b, . . . ,930nof readout integrated chip900may also have corresponding barrier layer (not shown) formed on each of the bumps930a,930b, . . . ,930n, wherein the corresponding barrier layer comprises a corresponding diffusion barrier layer and metal contact layer.

Once in alignment, the bumps230a,230b, . . . ,230nof detector elements220a,220b, . . . ,220nand corresponding bumps930a,930b, . . . ,930nof readout integrated chip900may be brought into contact with one another (as shown inFIG. 10, for example). When the bumps are brought into contact with one another, floating oxide layer810and oxide layer910may also be brought into contact with one another. An oxide-to-oxide bond starts forming between floating oxide layer810and oxide layer910essentially as soon as the layers are brought into contact. In one embodiment, the oxide-to-oxide bond may be a chemical bond, for example, a covalent bond. In one embodiment, upper surfaces of floating oxide layer810and oxide layer910may be activated prior to initiating the formation of the oxide-to-oxide bond. In one embodiment, the formation of the oxide-to-oxide bond between the floating oxide layer810and oxide layer910may be initiated by a temperature excursion to a temperature acceptable for the particular materials being used. In one embodiment, the formation of the oxide-to-oxide bond between the floating oxide layer810and oxide layer910may be initiated by applying a slight threshold pressure, which is significantly less than the amount of external pressure applied during an indium-to-indium cold welding process. One process of forming oxide-to-oxide bonds is described in more detail in U.S. Pat. Nos. 6,902,987 and 6,962,835, and U.S. Patent Application Publication No. 2004/0235266 assigned to Ziptronix, Inc, that are hereby incorporated by reference in their entirety. Consequently, the oxide-to-oxide bonding process will not be discussed in detail.

In one embodiment, the oxide-to-oxide bond formed between floating oxide layer810and oxide layer910may serve as a structural bond between detector elements220a,220b, . . . ,220n, and readout integrated chip900. The pressure generated by the bonding of the floating oxide layer810and oxide layer910causes the bumps230a,230b, . . . ,230nof detector elements220a,220b, . . . ,220nand corresponding bumps930a,930b, . . . ,930nof readout integrated chip900to be intimately contacted with one another. In one embodiment, the pressure generated by the bonding of the floating oxide layer810and oxide layer910is enough to bring the bumps on detector elements220a,220b, . . . ,220nand corresponding bumps930a,930b, . . . ,930non readout integrated chip900into intimate contact with each other without the need for application of external pressure (as is the case in conventional indium-to-indium cold welding). In one embodiment, the formation of the oxide-to-oxide bond removes essentially all mechanical stresses on and between the bumps on detector elements220a,220b, . . . ,220nand corresponding bumps930a,930b, . . . ,930non readout integrated chip900.

In one embodiment, a non-oxide bond may be formed between the intimately contacted bumps230a,230b, . . . ,230nof detector elements220a,220b, . . . ,220nand corresponding bumps930a,930b, . . . ,930nof readout integrated chip900. In one embodiment, the non-oxide bond provides an electrical connection between detector elements220a,220b, . . . ,220nand readout integrated chip900. In one embodiment, the non-oxide bond is a metallic bond formed between the bumps230a,230b, . . . ,230nof detector elements220a,220b, . . . ,220nand corresponding bumps930a,930b, . . . ,930nof readout integrated chip900. In one embodiment, the metallic bond between the bumps is formed by the fusion or diffusion of metal atoms (of the bumps).

In one embodiment, optionally, the non-oxide bond is a bond formed between the barrier layer310on bumps230a,230b, . . . ,230nof detector elements220a,220b, . . . ,220nand corresponding barrier layer on corresponding bumps930a,930b, . . . ,930nof readout integrated chip900. In one embodiment, optionally, the non-oxide bond is a metallic bond formed between metal contact layer330on bumps230a,230b, . . . ,230nof detector elements220a,220b, . . . ,220nand corresponding metal contact layer on corresponding bumps930a,930b, . . . ,930nof readout integrated chip900. In one embodiment, optionally, the non-oxide bond between the barrier layers/metal contact layers is formed by an annealing process, which may be carried out at a temperature of less than or equal to 170° C., for example.

As mentioned above, when a conventional indium-to-indium cold welding process is utilized to bond detector elements to a readout integrated chip, high external pressure/force needs to be applied. Conventionally, the indium-to-indium bond formed between the detector elements and the readout integrated chip serves as a structural bond as well as an electrical connection between the detector elements and the readout integrated chip. As can be appreciated, per various embodiments described herein, an oxide-to-oxide bond between floating oxide layer810and oxide layer910is formed without application of high external pressure, and serves as a structural bond between detector elements220a,220b, . . . ,220nand the readout integrated chip900. Because floating oxide layer810does not contact surfaces of detector elements220a,220b, . . . ,220nor surfaces of wafer210, no damage is caused to detector elements220a,220b, . . . ,220nduring the oxide-to-oxide bonding process, offering a substantial improvement over the conventional approach described above. Moreover, the non-oxide bond formed between the bumps230a,230b, . . . ,230nof detector elements220a,220b, . . . ,220nand corresponding bumps930a,930b, . . . ,930nof readout integrated chip900(which serves as an electrical connection between detector elements220a,220b, . . . ,220nand the readout integrated chip900), may also be formed without application of high pressure/force. Undesirable reduction in the production yield may also be avoided due to the breakage of indium bumps resulting from the high pressures/forces required to be applied during the conventional bonding process, e.g., indium-to-indium cold welding.

Other embodiments, uses and advantages of the inventive concept will be apparent to those skilled in the art from consideration of the above disclosure and the following claims. The specification should be considered non-limiting and exemplary only, and the scope of the inventive concept is accordingly intended to be limited only by the scope of the following claims.