Variable gain control system and method for an amplifier

An amplifier circuit for a millimeter wave (mmW) communication system includes an amplifier coupled to a matching network, and a variable gain control circuit in the matching network, the variable gain control circuit having an adjustable gain control resistance, the adjustable gain control resistance having adjustable segments and a center node therebetween, the center node coupled to an alternating current (AC) ground.

FIELD

The present disclosure relates generally to electronics, and more specifically to amplifiers in communication devices.

BACKGROUND

Wireless communication devices and technologies are becoming ever more prevalent. Wireless communication devices generally transmit and receive communication signals. A communication signal is typically processed by a variety of different components and circuits. One of the circuits that process a communication signal is a transceiver. A transceiver may include a transmitter and a receiver. Some wireless communication devices may be configured to operate on a variety of different communication bands. For example, a modern wireless communication device may be configured to operate on radio spectrum covering both 5G and 4G LTE frequencies. In some instances, a modern wireless communication device may be configured to operate simultaneously on 5G and 4G LTE frequencies in what can be referred to as carrier aggregation (CA) in which a wireless communication device may simultaneously communicate over multiple carriers.

A millimeter-wave (mmW) transmitter typically used in 5G or new radio (NR) communication systems uses a number of transmit chains, each having one or more amplifiers, and each coupled to one or more antenna elements of a phased-array antenna system that may be configured to perform beamforming. Beamforming refers to altering a phase of a transmit and/or a receive signal provided to different antenna elements of the phased-array antenna system to affect the directionality of the resulting communication beam.

It is desirable to have a way to provide fine gain control for a mmW communication system that uses a phased-array antenna system.

SUMMARY

One aspect of the disclosure provides an amplifier circuit for a millimeter wave (mmW) communication system including an amplifier coupled to a matching network, and a variable gain control circuit in the matching network, the variable gain control circuit having an adjustable gain control resistance, the adjustable gain control resistance having adjustable segments and a center node therebetween, the center node coupled to an alternating current (AC) ground.

Another aspect of the disclosure provides a method for providing amplifier gain control including amplifying a radio frequency (RF) signal with an amplifier circuit, coupling a common mode current to a ground, and independently varying a resistance of adjustable segments of an adjustable gain control resistance.

Another aspect of the disclosure provides a device including means for amplifying a radio frequency (RF) signal, means for means for coupling a common mode current to a ground, and means for independently varying a resistance of adjustable segments of an adjustable gain control resistance.

Another aspect of the disclosure provides a gain control system for an amplifier circuit including a transconductance amplifier coupled to a matching network, the transconductance amplifier comprising n-type metal oxide semiconductor (NMOS) transistor devices, and a variable gain control circuit in the matching network, the variable gain control circuit having an adjustable gain control resistance, the adjustable gain control resistance comprising p-type metal oxide semiconductor (PMOS) transistor devices, the adjustable gain control resistance having adjustable segments and a center node coupled to at least a portion of each of the adjustable segments, the center node further coupled to an alternating current (AC) ground.

DETAILED DESCRIPTION

In a communication system that uses an amplifier coupled to a phased-array antenna system for generating a beamformed communication beam, it may be advantageous to operate the amplifier with fine gain control. For example, when operating an amplifier in a transmitter coupled to a phased-array antenna system at maximum power, that is, where every element of the phased-array is at a maximum power, fine gain control is desirable to provide gain alignment among the elements of the phased-array, and may further allow for maintaining amplifier linearity for the full power condition.

An amplifier used in a mmW communication system may be implemented with a transconductor (a transconductance amplifier), an input load and an output load. Gain control is possible by modifying the transconductor (modifying the current through the transconductance amplifier) and/or by modifying the impedance of the load or by modifying the impedance at the input to the transconductance amplifier.

One conventional way of providing gain control lowers the impedance of the load in differential mode (DM) without significantly affecting the common mode (CM) impedance. As a result, the second harmonic content of the output voltage waveform, VOUT 2fo, does not change, while the first harmonic content, VOUT,fo, is reduced by the gain control circuit. That is, the output voltage waveform is more distorted when the gain control circuit is enabled.

Exemplary embodiments of the disclosure are directed to a variable gain control system and method that provides fine gain control to an amplifier. In some configurations, the amplifier may be operating in a high or full power condition.

Exemplary embodiments of the disclosure are directed to a variable gain control system and method that provides linear fine gain control to an amplifier that may be coupled to a phased-array antenna system.

Exemplary embodiments of the disclosure are directed to a variable gain control system and method that provides linear fine gain control to an amplifier that may be used in a beamforming application.

Exemplary embodiments of the disclosure are directed to a variable gain control system and method for an amplifier that may be implemented in a matching network in accordance with an exemplary embodiment of the disclosure.

FIG.1is a diagram showing a wireless device110communicating with a wireless communication system120. The wireless communication system120may be a 5G NR (new radio) system, Long Term Evolution (LTE) system, a Code Division Multiple Access (CDMA) system, a Global System for Mobile Communications (GSM) system, a wireless local area network (WLAN) system, or some other wireless system. A CDMA system may implement Wideband CDMA (WCDMA), CDMA 1×, Evolution-Data Optimized (EVDO), Time Division Synchronous CDMA (TD-SCDMA), or some other version of CDMA. For simplicity,FIG.1shows wireless communication system120including two base stations130and132and one system controller140. In general, a wireless communication system may include any number of base stations and any set of network entities.

The wireless device110may also be referred to as a user equipment (UE), a mobile station, a terminal, an access terminal, a subscriber unit, a station, etc. Wireless device110may be a cellular phone, a smartphone, a tablet, a wireless modem, a personal digital assistant (PDA), a handheld device, a laptop computer, a smartbook, a netbook, a tablet, a cordless phone, a medical device, a device configured to connect to one or more other devices (for example through the internet of things), a wireless local loop (WLL) station, a Bluetooth device, etc. Wireless device110may communicate with wireless communication system120. Wireless device110may also receive signals from broadcast stations (e.g., a broadcast station134), signals from satellites (e.g., a satellite150) in one or more global navigation satellite systems (GNSS), etc. Wireless device110may support one or more radio technologies for wireless communication such as 5G NR, LTE, WCDMA, CDMA 1×, EVDO, TD-SCDMA, GSM, 802.11, etc.

Wireless device110may support carrier aggregation, for example as described in one or more LTE or 5G standards. In some embodiments, a single stream of data is transmitted over multiple carriers using carrier aggregation, for example as opposed to separate carriers being used for respective data streams.

Wireless device110may be able to operate in a low-band (LB) covering frequencies lower than 1000 megahertz (MHz), a mid-band (MB) covering frequencies from 1000 MHz to 2300 MHz, and/or a high-band (HB) covering frequencies higher than 2300 MHz. For example, low-band may cover 698 to 960 MHz, mid-band may cover 1475 to 2170 MHz, and high-band may cover 2300 to 2690 MHz and 3400 to 5000 MHz. Low-band, mid-band, and high-band refer to three groups of bands (or band groups), with each band group including a number of frequency bands (or simply, “bands”). Each band may cover up to 200 MHz in some configurations and may include one or more carriers. Each carrier may cover up to 20 MHz in LTE. LTE Release 11 supports 35 bands, which are referred to as LTE/UMTS bands and are listed in 3GPP TS 36.101. Wireless device110may be configured with up to five carriers in one or two bands in LTE Release 11. Wireless device110may further be able to operate at frequencies higher than 5000 MHz, for example at frequencies up to 6 or 7 GHz and/or at mmW frequencies. Frequencies of approximately 20 GHz or higher, for example around 24 GHz or higher, may be considered mmW frequencies.

The wireless device110may also be in communication with a wireless device160. In an exemplary embodiment, the wireless device160may be a wireless access point, or another wireless communication device that comprises, or comprises part of a wireless local area network (WLAN). An exemplary embodiment of a WLAN signal may include WiFi, or other communication signals that use unlicensed communication spectrum in the range of, for example, 5 GHz to 6 GHz or in mmW frequencies. The wireless device110may also be capable of ENDC (E-UTRAN New Radio Dual Connectivity), where the wireless device110may simultaneously be in communication with a first base station (for example, an eNodeB) and with a second base station (for example, a gNodeB).

In general, carrier aggregation (CA) may be categorized into two types—intra-band CA and inter-band CA. Intra-band CA refers to operation on multiple carriers within the same band. Inter-band CA refers to operation on multiple carriers in different bands.

FIG.2is a block diagram showing a wireless device200in which the exemplary techniques of the present disclosure may be implemented. The wireless device200may be an example of the wireless device110in some embodiments. In other embodiments, the wireless device200may be an example of one of the base stations,130,132, the wireless device160, a device not illustrated inFIG.1such as a customer premises equipment (CPE), etc.FIG.2shows an example of a transceiver220. In general, the conditioning of the signals in a transmitter230and a receiver250may be performed by one or more stages of amplifier, filter, upconverter, downconverter, etc. These circuit blocks may be arranged differently from the configuration shown inFIG.2. Furthermore, other circuit blocks not shown inFIG.2may also be used to condition the signals in the transmitter230and receiver250. Unless otherwise noted, any signal inFIG.2, or any other figure in the drawings, may be either single-ended or differential. Some circuit blocks inFIG.2may also be omitted.

In the example shown inFIG.2, wireless device200generally comprises the transceiver220and a data processor210. The data processor210may include a processor296operatively coupled to a memory298. The memory298may be configured to store data and program codes, as exemplary software or firmware299, and may generally comprise analog and/or digital processing elements. The processor296and the memory298may cooperate to control, configure, program, or otherwise fully or partially control some or all of the operation of the embodiments of the amplifier circuit and variable gain control system and method described herein.

The transceiver220includes a transmitter230and a receiver250that support bi-directional communication. In general, wireless device200may include any number of transmitters and/or receivers for any number of communication systems and frequency bands. In some embodiments, only a transmitter or only a receiver may be implemented. All or a portion of the transceiver220may be implemented on one or more analog integrated circuits (ICs), RF ICs (RFICs), mixed-signal ICs, etc.

A transmitter or a receiver may be implemented with a super-heterodyne architecture or a direct-conversion architecture. In the super-heterodyne architecture, a signal is frequency-converted between radio frequency (RF) and baseband in multiple stages, e.g., from RF to an intermediate frequency (IF) in one stage, and then from IF to baseband in another stage for a receiver. In the direct-conversion architecture, a signal is frequency converted between RF and baseband, or near baseband, in one stage. The super-heterodyne and direct-conversion architectures may use different circuit blocks and/or have different requirements. In the example shown inFIG.2, transmitter230and receiver250are implemented with the direct-conversion architecture. In other examples, such as the example discussed with respect toFIG.3, a super-heterodyne architecture may be used.

In the illustrated transmit path, the data processor210processes data to be transmitted and provides in-phase (I) and quadrature (Q) analog output signals to the transmitter230. In an exemplary embodiment, the data processor210includes digital-to-analog-converters (DAC's)214aand214bfor converting digital signals generated by the data processor210into the I and Q analog output signals, e.g., I and Q output currents, for further processing. In other embodiments, the DACs214aand214bare included in the transceiver220and the data processor210provides data (e.g., for I and Q) to the transceiver220digitally.

Within the transmitter230, lowpass filters232aand232bfilter the I and Q analog transmit signals, respectively, to remove undesired images caused by the prior digital-to-analog conversion Amplifiers (Amp)234aand234bamplify the signals from lowpass filters232aand232b, respectively, and provide I and Q baseband signals. An upconverter240upconverts the I and Q baseband signals with I and Q transmit (TX) local oscillator (LO) signals from a TX LO signal generator290and provides an upconverted signal. A filter242filters the upconverted signal to remove undesired images caused by the frequency upconversion as well as noise in a receive frequency band. A power amplifier (PA)244amplifies the signal from filter242to obtain the desired output power level and provides a transmit RF signal. The transmit RF signal may be routed through a duplexer or switch246and transmitted via an antenna248.

The power amplifier244may comprise one or more stages comprising, for example, driver stages, power amplifier stages, or other components, that can be configured to amplify a communication signal on one or more frequencies, in one or more frequency bands, and at one or more power levels. Depending on various factors, the power amplifier244can be configured to operate using one or more bias signals and can be configured in various topologies or architectures.

Exemplary embodiments of the variable gain control system and method described herein may be implemented within the power amplifier244, or within the various amplifier stages of the power amplifier244.

In the receive path, antenna248receives communication signals and provides a received RF signal, which may be routed through duplexer or switch246and provided to a low noise amplifier (LNA)252. The duplexer246may be designed to operate with a specific RX-to-TX duplexer frequency separation, such that RX signals are isolated from TX signals. The received RF signal is amplified by LNA252and filtered by a filter254to obtain a desired RF input signal. Downconversion mixers261aand261bmix the output of filter254with I and Q receive (RX) LO signals (i.e., LO_I and LO_Q) from an RX LO signal generator280to generate I and Q baseband signals. The I and Q baseband signals are amplified by amplifiers262aand262band further filtered by lowpass filters264aand264bto obtain I and Q analog input signals, which are provided to data processor210. In the exemplary embodiment shown, the data processor210includes analog-to-digital-converters (ADC's)216aand216bfor converting the analog input signals into digital signals to be further processed by the data processor210. In some embodiments, the ADCs216aand216bare included in the transceiver220and provide data to the data processor210digitally. One or more exemplary embodiments of an inductorless interference cancellation filter may be implemented in the filter254ofFIG.2. In some embodiments, the variable gain control system and method described herein may be implemented within the LNA252.

InFIG.2, TX LO signal generator290generates the I and Q TX LO signals used for frequency upconversion, while RX LO signal generator280generates the I and Q RX LO signals used for frequency downconversion. Each LO signal is a periodic signal with a particular fundamental frequency. A phase locked loop (PLL)292receives timing information from data processor210and generates a control signal used to adjust the frequency and/or phase of the TX LO signals from LO signal generator290. Similarly, a PLL282receives timing information from data processor210and generates a control signal used to adjust the frequency and/or phase of the RX LO signals from LO signal generator280.

Wireless device200may support CA and may (i) receive multiple downlink signals on multiple downlink carriers at different frequencies and/or (ii) transmit multiple uplink signals on multiple uplink carriers. Those of skill in the art will understand, however, that aspects described herein may be implemented in systems, devices, and/or architectures that do not support carrier aggregation.

Certain elements of the transceiver220are functionally illustrated inFIG.2, and the configuration illustrated therein may or may not be representative of a physical device configuration in certain implementations. For example, as described above, transceiver220may be implemented in various integrated circuits (ICs), RF ICs (RFICs), mixed-signal ICs, etc. In some embodiments, the transceiver220is implemented on a substrate or board such as a printed circuit board (PCB) having various modules. For example, the PA244, the filter242, the LNA252, and/or the duplexer246may be implemented in separate modules or as discrete components, while the remaining elements illustrated in the transceiver220may be implemented in a single transceiver chip. Further, whileFIG.2illustrates I and Q signals, those of skill in the art will understand that the transceiver220may alternatively be implemented using a polar architecture or may include elements to implement a polar architecture in addition to a quadrature architecture.

FIG.3Ais a block diagram of at least a portion of an exemplary transmit chain300in which exemplary embodiments of the variable gain control system and method may be implemented. In an exemplary embodiment, the transmit chain300may be implemented in a mmW communication device that implements a super-heterodyne (superhet) architecture in which a communication signal that is to be transmitted may be converted from a baseband information signal, to an intermediate frequency signal, and then upconverted from the intermediate frequency to a radio frequency signal. Similarly, a received communication signal may be downconverted from an RF signal, to an IF signal, and then further downconverted from the IF signal to a baseband information signal. For example, in some embodiments, an additional mixer (e.g., mixer302described below) is implemented between the filter242and the PA244. In some embodiments, another additional mixer is also included between the LNA252and the filter254. In some such embodiments, these additional mixers, the PA244, and the LNA252are implemented in an RFIC separate from an IC on which other elements of the transceiver220are implemented. The separate RFIC may be integrated into a module including the antenna248in some embodiments. In some embodiments including the additional mixers, an LO for communications in the 20s or 30s of GHz is implemented, and may be included in the RFIC. While the description below includes a superhet architecture, those of skill in the art will understand that embodiments are not limited to amplifiers in such architecture. Further, those of skill in the art will understand that the embodiments described herein may be implemented in an amplifier in a receive chain. The exemplary transmit chain300is shown for illustrative purposes only and may comprise a portion of a transmit chain in an mmW communication device.

In an exemplary embodiment, the transmit chain300may comprise a mixer302configured to receive an intermediate frequency (IF) communication signal over differential connections304, and a local oscillator (LO) signal over differential connections306. The mixer302, using the LO signal, may be configured to upconvert the IF communication signal to a mmW frequency communication signal (referred to inFIG.3as an RF signal).

In an exemplary embodiment, the transmit chain300may comprise one or more amplifier stages, with three exemplary amplifier stages320,322and324shown inFIG.3for example only. The three amplifier stages320,322and324may be configured to provide the same or different levels of signal amplification. In an exemplary embodiment, the first amplifier stage320and the second amplifier stage322may be referred to as driver stages, and the third amplifier stage324may be referred to as a power amplifier. More or fewer amplifier stages may be included in a transmit chain, depending on application.

In an exemplary embodiment, the transmit chain300may comprise one or more matching networks310,312,314and316. The matching networks310,312,314and316may be configured to pass an RF signal from one component to another component, such as from the mixer302to the amplifier stage320, from amplifier stage to amplifier stage, and from amplifier stage to a load, such as an antenna, a phase shifter, etc. The matching networks310,312,314and316may each comprise one or more passive and/or active components, such as transistors, resistances, capacitances, inductances (not shown inFIG.3). In some embodiments, the matching networks310,312,314and316may also comprise transformers (not shown). Although shown inFIG.3as being a differential architecture, the transmit chain300may also be configured in a single-ended architecture. Further, while three amplifier stages and four matching networks are illustrated inFIG.3, embodiments may include a greater or fewer number of amplifier stages and matching networks.

In an exemplary embodiment, the matching networks310,312,314and316; and the amplifier stages320,322and324may comprise a transmit path330, where one or more transmit paths330may be implemented in a phased array architecture. The transmit path330may include a fewer or greater number of amplifier stages and/or a fewer or greater number of matching networks in other embodiments.

In an exemplary embodiment, the output of the amplifier stage324is shown as being connected through the matching network316to an antenna342. However, in other embodiments, the output of the power amplifier316may be coupled to other elements, such as to a phase shifter, to another amplifier, etc.

Exemplary embodiments of the variable gain control system and method described herein may be implemented in one or more of an amplifier, a matching circuit, or in an amplifier circuit that may comprise an amplifier and a matching circuit having the variable gain control system.

FIG.3Bis a block diagram of at least a portion of an exemplary transmit chain350in which exemplary embodiments of the variable gain control system and method may be implemented. The transmit chain350is an example of a phased array antenna architecture in which multiple transmit paths330-1,330-2through330-nmay be coupled to the mixer302. In an exemplary embodiment, the number of transmit paths330is dependent upon implementation, with three transmit paths330-1,330-2and330-nshown for simplicity of illustration.

In an exemplary embodiment, an input of each transmit path330is coupled to a respective phase shifter332, where transmit path330-1is coupled to a phase shifter332-1, transmit path330-2is coupled to a phase shifter332-2and transmit path330-nis coupled to a phase shifter332-n. In an exemplary embodiment, each phase shifter332is coupled between the mixer302and the respective transmit path330. In such embodiments, an output of each of the transmit paths330is coupled to a respective antenna element334in an array336of antenna elements. For example, transmit path330-1is coupled to antenna element334-1, transmit path330-2is coupled to antenna element334-2and transmit path330-nis coupled to antenna element334-n.

FIG.4is a schematic diagram showing an exemplary embodiment of an implementation of an amplifier circuit400including an amplifier and a matching network having a variable gain control system in accordance with an exemplary embodiment. The amplifier circuit400may be an example of one or more of the amplifiers (320,322,324) and matching networks (312,314,316) shown inFIG.3. In an exemplary embodiment, the amplifier circuit400may include a variable gain control circuit that may provide fine gain control.

The amplifier circuit400includes an amplifier410, which in an exemplary embodiment can be a transconductance amplifier. The amplifier410may be configured to receive a differential input signal at nodes412aand412b, and may be configured to provide a differential output signal at nodes414aand414b. A DC bias voltage, Vbias, may be provided to the nodes412aand412b. The differential input signal may be provided in the form of an input voltage, Vin, for example such that it is also provided to the nodes412a(Vin_p, or Vin+) and412b(Vin_m, or Vin−) as an AC radio frequency (RF) input signal.

In an exemplary embodiment, the amplifier410may be implemented using n-type metal oxide semiconductor (NMOS) transistors422and424. In an exemplary embodiment, the source of each transistor422and424may be coupled to system ground and the drain of each transistor422and424may be coupled to the output nodes414aand414b. The capacitances426and428are optional, and may be implemented in some mmW frequency systems to improve differential mode stability and gain, and are sometimes referred to as neutralization capacitors. In an exemplary embodiment, the capacitances426and428may be implemented to cancel the effect of gate-source capacitance (Cgs) of the transistor422and the transistor424. In an exemplary embodiment, the capacitance426connects the gate of the transistor422(Vin_p) to the drain of the transistor424(Vout_p) and the capacitance428connects the gate of the transistor424(Vin_m) to the drain of the transistor422(Vout_m). The capacitances426and428may be realized using discrete capacitors or transistor devices. Although shown inFIG.4as being implemented using NMOS transistor devices, the amplifier410may also be implemented using PMOS transistor devices, as will be described herein.

The amplifier circuit400also includes a matching network450. In an exemplary embodiment, the matching network450may be referred to as a load matching network configured to operate as an output matching network for the amplifier410. In an exemplary embodiment, the matching network450may also be configured with a variable gain control system for providing linear gain control for the amplifier410. In an exemplary embodiment, the matching network450includes a load inductance452, a differential mode (DM) load resistance (RDM)454and a differential mode load capacitance (CDM)456. Although shown as discrete elements, the differential mode load resistance (RDM)454and the differential mode load capacitance (CDM)456may be created by parasitic resistance and parasitic capacitance generated by the components in the amplifier circuit400. The matching network450may also be implemented using other components, such as, for example, transformers, or other components that may alter the impedance presented to the differential output414aand414bof the amplifier410.

In an exemplary embodiment, the matching network450also includes an adjustable gain control resistance470. In an exemplary embodiment, the adjustable gain control resistance470may be referred to as RGC, and may comprise one or more adjustable segments. In an exemplary embodiment, the adjustable gain control resistance470may comprise two adjustable segments472and474, each having a value RGC/2, and a center node475therebetween, coupled to at least a portion of each of segments472and474. In some embodiments, the adjustable segments472and474may be separately adjustable and/or are capable of being adjusted to have different values. In an exemplary embodiment, the resistance provided by each of the adjustable segments472and474may be independently and selectively adjusted by a respective control signal provided by the data processor210ofFIG.2or by another control unit (not illustrated) disposed elsewhere in the wireless device200.

In an exemplary embodiment, the center node475of the adjustable gain control resistance470can be coupled to an alternating current (AC) ground. In an example, the AC ground may be interpreted to include the system voltage VDD. In other exemplary embodiments, the system ground and AC ground may be shorted. A capacitance478may appear between the node475and system ground415. In other examples, the AC ground may be provided at locations other than VDD. In the example shown inFIG.4, the center node475is also coupled to a center tap of the inductance452. In an exemplary embodiment, the adjustable segments472and474are controlled so as to provide substantially the same resistance.

In an exemplary embodiment, the adjustable gain control resistance470can be adjusted by one or more control signals from the data processor210(FIG.2) in differential mode (DM), that is, both adjustable segments472and474of the adjustable gain control resistance470may be selectively adjusted over a range of resistance values, for example to lower the differential mode load impedance, ZDM, fo, while allowing the fundamental current, Ifoto remain substantially unaffected and while the differential mode output voltage, VOUT, fo, decreases, thus providing a variable and in some embodiments, a linear gain control function to the amplifier410. The output current, that is the fundamental current, Ifoand the second harmonic current I2fois generated by the transconductance of the amplifier410. Therefore, the output current depends only on the input voltage, Vin, and the transconductance of the amplifier410(i.e., the output current does not depend on the output load). Accordingly, when the resistance of the load (Rload including RDMand RGCvaries, the output current, Iout, remains unaffected, but the output voltage, Vout, varies with the change in the load according to Vout=Iout*Rload. That is, the output voltage, Vout, varies with the varying resistance of the adjustable gain control resistance470. In an exemplary embodiment, the center node475provides a common mode AC path to ground for the second harmonic current I2fo, thus allowing the second harmonic current I2foa low impedance path to ground, while allowing the common mode output voltage, VOUT, 2fo, to decrease linearly or non-linearly for the common mode as well as the differential mode.

In this manner, both the differential mode load impedance (ZDM, fo) and the common mode load impedance (ZCM, 2fo) can be simultaneously lowered by selectively varying the adjustable gain control resistance470. An example range of resistance values for the adjustable gain control resistance470may be from a low impedance value of about 20 Ohm to a high impedance value of about 2K Ohm. These values are for example only and may differ based on implementation. In an exemplary embodiment, the resistance of the adjustable segments472and474of the adjustable gain control resistance470may be selectively adjusted to be the same resistance value.

In some embodiments, the load inductance452may be a primary side of a transformer482. The transformer482may be part of an output circuit480in which the output of the amplifier circuit400may be taken from the nodes484aand484b. The transformer482and output circuit480are shown in dotted line to indicate that they are optional. However, the linear gain control aspect of the matching network450is not dependent on whether the load inductance452is implemented as part of a transformer482. Further, while the transformer482and output circuit480are not illustrated in subsequent figures, it will be understood that the transformer482and/or output circuit480may be included in any other embodiment (e.g., embodiments illustrated inFIGS.5-8) herein.

While the amplifier circuit400having the matching network450is described in a transmit application, the linear gain control system and method described herein applies to any differential load used for highly linear gain control at mmW frequencies.

FIG.5is a schematic diagram showing an exemplary embodiment of an implementation of an amplifier circuit500including an amplifier and a matching network having a variable gain control system in accordance with an exemplary embodiment. The amplifier circuit500may be an example of one or more of the amplifiers (320,322,324) and matching networks (312,314,316) shown inFIG.3. In an exemplary embodiment, the amplifier circuit500may include a variable gain control circuit that may provide fine gain control.

The amplifier circuit500includes an amplifier510, which can be a transconductance amplifier. The amplifier510may be configured to receive a differential input signal at nodes512aand512b, and may be configured to provide a differential output signal at nodes514aand514b. In an exemplary embodiment, the amplifier510may be implemented using NMOS transistors522and524. In an exemplary embodiment, the source of each transistor522and524may be coupled to system ground and the drain of each transistor522and524may be coupled to the output nodes514aand514b. The capacitances526and528are optional, and may be implemented in some mmW frequency systems to improve differential mode stability and gain, and are sometimes referred to as neutralization capacitors. In an exemplary embodiment, the capacitances526and528may be implemented to cancel the effect of gate-source capacitance (Cgs) of the transistor522and the transistor524. It an exemplary embodiment, the capacitance526connects the gate of the transistor522(Vin_p) to the drain of the transistor524(Vout_p) and the capacitance528connects the gate of the transistor524(Vin_m) to the drain of the transistor522(Vout_m). The capacitances526and528may be realized using discrete capacitors or transistor devices.

The amplifier circuit500also includes an exemplary embodiment of a matching network550. In an exemplary embodiment, the matching network550may be referred to as a load matching network configured to operate as an output matching network for the amplifier510. In an exemplary embodiment, the matching network550may also be configured to provide linear gain control for the amplifier510. In an exemplary embodiment, the matching network550includes a load inductance552, a differential mode (DM) load resistance (RDM)554and a differential mode load capacitance (CDM)556. Although shown as discrete elements, the differential mode load resistance (RDM)554and the differential mode load capacitance (CDM)556may be created by parasitic resistance and parasitic capacitance generated by the components in the amplifier circuit500. The matching network550may also be implemented using other components, such as, for example, transformers, or other components that may alter the impedance presented to the differential output514aand514bof the amplifier510.

In an exemplary embodiment, the matching network550also includes an adjustable gain control resistance570. In an exemplary embodiment, the adjustable gain control resistance570may be implemented using PMOS transistor devices to realize the adjustable segments572and574. In an exemplary embodiment, the adjustable segment572may comprise a number (equal to n+1 in the embodiment illustrated inFIG.5) of PMOS transistor571through573. In an exemplary embodiment, the adjustable segment574may comprise the same number of PMOS transistors, illustrated inFIG.5as PMOS transistors577through579. Each of the PMOS transistors571through573and577through579are on when the gate voltage (illustrated inFIG.5as Vctrl<n:0>) provided to the gate of the respective PMOS transistor571through573and577through579is at logic low, or zero volts or below, that is, when the gate of the respective PMOS transistor571through573and577through579is coupled to a logic low signal, such as system ground. WhileFIG.5illustrates segments572and574receiving the same control signal, Vctrl, the segments572,574(or portions thereof) may receive control signals separate and/or different from each other, or may otherwise be separately adjustable.

In an exemplary embodiment, the drain of the transistor571is coupled to the source of the transistor577and also is coupled to system voltage VDD at the center node575, which may also be coupled to a center tap of the inductance552. Similarly, the drain of the transistor573is coupled to the source of the transistor579and also is coupled to system voltage VDD at the center node575. In this way, a center node between any two pairs of PMOS transistors in the adjustable gain control resistance570may be coupled to VDD. The source of the transistor571is coupled to the output node514aand the source of the transistor573is coupled to the output node514a; and the drain of the transistor577is coupled to the output node514band the drain of the transistor579is coupled to the output node514b. Similarly, the source of any other transistor in segment572may be coupled to the output node514aand the drain of any other transistor in segment574may be coupled to the output node514b.

The state of the PMOS transistors571through573and577through579may be controlled by a control signal from the data processor210ofFIG.2or by another controller (not illustrated) disposed elsewhere in the wireless device200. In an exemplary embodiment, the resistance provided by the transistors571and577may be determined by their size; and the resistance provided by the transistors573and579may also be determined by their size, that is, their width “W” divided by their length “L” (W/L). The on-resistance of the transistors571,573,577and579(and any other transistors in the adjustable gain control resistance570) is inversely proportional to W/L. In an exemplary embodiment, the size, and therefore the resistance, of each the transistors571and577may be the same or may be different from one or more other transistors, and similarly the size of each of the transistors573and579may be the same or may be different from one or more other transistors herein. The size of the transistors571through573, and the size of the transistors577through579may be the same and there may be an explicit common mode point at node575between the transistors571and577and between the transistors573and579. Therefore, the amount of resistance provided by the separately adjustable segments572and574may be determined by the size of the transistor devices and the number of transistor devices enabled by the control signal, Vctrl<n:0>, to provide adjustable resistance.

In an exemplary embodiment, the center node575of the adjustable gain control resistance570can be coupled to an alternating current (AC) ground. In an example, the AC ground may be interpreted to include the system voltage VDD. A capacitance578may appear between the node575and system ground515. In other examples, the AC ground may be provided at locations other than VDD.

In an exemplary embodiment, the adjustable gain control resistance570can be adjusted by one or more control signals from the data processor210(FIG.2) in differential mode (DM). For example, segments572and574of the adjustable gain control resistance570may be adjusted to lower the differential mode load impedance, ZDM, fo, while allowing the fundamental current, Ifoto remain substantially unaffected and while the differential mode output voltage, VOUT; fo, decreases, thus providing a variable and in some embodiments, linear gain control function to the amplifier510. The output current, that is the fundamental current, Ifoand the second harmonic current I2fois generated by the transconductance of the amplifier510. Therefore, the output current depends only on the input voltage, Vin, and the transconductance of the amplifier510(i.e., the output current does not depend on the output load). Accordingly, when the resistance of the load (Rload including RDMand RGC) varies, the output current, Iout, remains unaffected, but the output voltage, Vout, varies with the change in the load according to Vout=Iout*Rload. That is, the output voltage, Vout, varies with the varying resistance of the adjustable gain control resistance570. In an exemplary embodiment, the center node575provides a common mode AC path to ground for the second harmonic current I2fo, thus allowing the second harmonic current I2foa low impedance path to ground, while allowing the common mode output voltage, VOUT, 2fo, to decrease linearly, or non-linearly, for the common mode as well as the differential mode.

In this manner, both the differential mode load impedance (ZDM, fo) and the common mode load impedance (ZCM, 2fo) can be simultaneously lowered by varying the adjustable gain control resistance570. An example range of resistance values for the adjustable gain control resistance570may be from a low impedance value of about 20 Ohm to a high impedance value of about 2K Ohm. These values are for example only and may differ based on implementation. In an exemplary embodiment, the resistance of the separately adjustable segments572and574of the adjustable gain control resistance570may be selectively adjusted to be the same resistance value.

In the exemplary embodiment shown inFIG.5, the output circuit480shown inFIG.4, is omitted fromFIG.5for ease of illustration; however, the output circuit480may also be implemented in the amplifier circuit500ofFIG.5.

FIG.6is a schematic diagram showing an exemplary embodiment of an implementation of an amplifier circuit600including an amplifier and a matching network having a variable gain control system in accordance with an exemplary embodiment. The amplifier circuit600may be an example of one or more of the amplifiers (320,322,324) and matching networks (312,314,316) shown inFIG.3. In an exemplary embodiment, the amplifier circuit600may include a variable gain control circuit that may provide fine gain control.

The amplifier circuit600includes an amplifier610, which can be a transconductance amplifier. The amplifier600may be implemented using PMOS transistor devices, instead of the NMOS transistor devices used in the amplifier510ofFIG.5. The amplifier610may be configured to receive a differential input signal at nodes612aand612b, and may be configured to provide a differential output signal at nodes614aand614b. In an exemplary embodiment, the amplifier610may be implemented using PMOS transistors622and624. In an exemplary embodiment, the source of each transistor622and624may be coupled to system voltage, VDD, and the drain of each transistor622and624may be coupled to the output nodes614aand614b. The capacitances626and628are optional, and may be implemented in some mmW frequency systems to improve differential mode stability and gain, and are sometimes referred to as neutralization capacitors. In an exemplary embodiment, the capacitances626and628may be implemented to cancel the effect of gate-source capacitance (Cgs) of the transistor622and the transistor624. It an exemplary embodiment, the capacitance626connects the gate of the transistor622(Vin_p) to the drain of the transistor624(Vout_p) and the capacitance628connects the gate of the transistor624(Vin_m) to the drain of the transistor622(Vout_m). The capacitances626and628may be realized using discrete capacitors or transistor devices.

The amplifier circuit600also includes an exemplary embodiment of a matching network650. In an exemplary embodiment, the matching network650may be referred to as a load matching network configured to operate as an output matching network for the amplifier610. In an exemplary embodiment, the matching network650may also be configured to provide gain control for the amplifier610. In an exemplary embodiment, the matching network650includes a load inductance652in which a center node is coupled to system ground, a differential mode (DM) load resistance (RDM)654and a differential mode load capacitance (CDM)656. Although shown as discrete elements, the differential mode load resistance (RDM)654and the differential mode load capacitance (CDM)656may be created by parasitic resistance and parasitic capacitance generated by the components in the amplifier circuit600. The matching network650may also be implemented using other components, such as, for example, transformers, or other components that may alter the impedance presented to the differential output614aand614bof the amplifier610.

In an exemplary embodiment, the matching network650also includes an adjustable gain control resistance670. In an exemplary embodiment, the adjustable gain control resistance670may be implemented using NMOS transistor devices to realize separately adjustable segments672and674. In an exemplary embodiment, the separately adjustable segment672may comprise a number (equal to n+1 in the embodiment illustrated inFIG.6) of NMOS transistors671through673. In an exemplary embodiment, the separately adjustable segment674may comprise the same number of NMOS transistors, illustrated inFIG.6as NMOS transistors677through679. Each of the NMOS transistors671through673and677through679are on when the gate voltage (illustrated inFIG.6as Vctrl<n:0>) provided to the gate of the respective NMOS transistor671through673and677through679is at system voltage, VDD, that is, when the gate of the respective NMOS transistor671through673and677through679is coupled to a logic high signal, such as system voltage, VDD. WhileFIG.6illustrates segments672and674receiving the same control signal, Vctrl, the segments672,674(or portions thereof) may receive control signals separate and/or different from each other, or may otherwise be separately adjustable.

In an exemplary embodiment, the drain of the transistor671is coupled to the source of the transistor677and also is coupled to system ground at the center node675. Similarly, the drain of the transistor673is coupled to the source of the transistor679and also is coupled to system ground at the center node675. In this way, a center node between any two pairs of NMOS transistors in the adjustable gain control resistance670may be coupled to system ground. The source of the transistor671is coupled to the output node614aand the source of the transistor673is coupled to the output node614a. The drain of the transistor677is coupled to the output node614band the drain of the transistor679is coupled to the output node614b. Similarly, the source of any other transistor in segment672may be coupled to the output node614aand the drain of any other transistor in segment674may be coupled to the output node614b.

The state of the NMOS transistors671through673and677through679may be controlled by a control signal from the data processor210ofFIG.2or by another control unit (not illustrated) disposed elsewhere in the wireless device200. In an exemplary embodiment, the resistance provided by the transistors671and677may be determined by their size; and the resistance provided by the transistors673and679may also be determined by their size, that is, their width “W” divided by their length “L” (W/L). The on-resistance of the transistors671,673,677and679(and any other transistors in the adjustable gain control resistance670) is inversely proportional to W/L. In an exemplary embodiment, the size, and therefore the resistance, of each the transistors671and677may be the same or may be different from one or more other transistors, and similarly the size of each of the transistors673and679may be the same or may be different from one or more other transistors. The size of the transistors671through673, and the size of the transistors677through679may be the same and there may be an explicit common mode point at node675between the transistors671and677and between the transistors673and679. Therefore, the amount of resistance provided by the adjustable segments672and674may be determined by the size of the transistor devices and the number of transistor devices enabled by the control signal, Vctrl<n:0>, to provide adjustable resistance.

In an exemplary embodiment, the center node675of the adjustable gain control resistance670can be coupled to an alternating current (AC) ground. In an example, the AC ground may be interpreted to include the system ground.

In an exemplary embodiment, the adjustable gain control resistance670can be adjusted by one or more control signals from the data processor210(FIG.2) in differential mode (DM). For example, segments672and674of the adjustable gain control resistance670may be adjusted to lower the differential mode load impedance, ZDM, fo, while allowing the fundamental current, Ifoto remain substantially unaffected and while the differential mode output voltage, VOUT, fo, decreases, thus providing a variable and in some embodiments linear gain control function to the amplifier610. The output current, that is the fundamental current, Ifoand the second harmonic current I2fois generated by the transconductance of the amplifier610. Therefore, the output current depends only on the input voltage, Vin, and the transconductance of the amplifier610(i.e., the output current does not depend on the output load). Accordingly, when the resistance of the load (Rload including RDMand RGC) varies, the output current, Iout, remains unaffected, but the output voltage, Vout, varies with the change in the load according to Vout=Iout*Rload. That is, the output voltage, Vout, varies with the varying resistance of the adjustable gain control resistance670. In an exemplary embodiment, the center node675provides a common mode AC path to ground for the second harmonic current I2fo, thus allowing the second harmonic current I2foa low impedance path to ground, while allowing the common mode output voltage, VOUT, 2fo, to decrease linearly, or non-linearly, for the common mode as well as the differential mode.

In this manner, both the differential mode load impedance (ZDM,fo) and the common mode load impedance (ZCM, 2 fo) can be simultaneously lowered by adjusting the adjustable gain control resistance670. An example range of resistance values for the adjustable gain control resistance670may be from a low impedance value of about 20 Ohm to a high impedance value of about 2K Ohm. These values are for example only and may differ based on implementation. In an exemplary embodiment, the resistance of the separately adjustable segments672and674of the adjustable gain control resistance670may be selectively adjusted to be the same resistance value.

In the exemplary embodiment shown inFIG.6, the output circuit480shown inFIG.4, is omitted fromFIG.6for ease of illustration; however, the output circuit480may also be implemented in the amplifier circuit600ofFIG.6.

FIG.7is a schematic diagram showing an exemplary embodiment of an implementation of an amplifier circuit700including an amplifier and a matching network having a variable gain control system in accordance with an exemplary embodiment. The amplifier circuit700may be an example of one or more of the amplifiers (320,322,324) and matching networks (312,314,316) shown inFIG.3. In an exemplary embodiment, the amplifier circuit700may include a variable gain control circuit that may provide fine gain control.

The amplifier circuit700includes an amplifier710, which can be a transconductance amplifier. The amplifier710may be configured to receive a differential input signal at nodes712aand712b, and may be configured to provide a differential output signal at nodes714aand714b. In an exemplary embodiment, the amplifier710may be implemented using NMOS transistors722and724. In an exemplary embodiment, the source of each transistor722and724may be coupled to system ground and the drain of each transistor722and724may be coupled to the output nodes714aand714b. The capacitances726and728are optional, and may be implemented in some mmW frequency systems to improve differential mode stability and gain, and are sometimes referred to as neutralization capacitors. In an exemplary embodiment, the capacitances726and728may be implemented to cancel the effect of gate-source capacitance (Cgs) of the transistor722and the transistor724. It an exemplary embodiment, the capacitance726connects the gate of the transistor722(Vin_p) to the drain of the transistor724(Vout_p) and the capacitance728connects the gate of the transistor724(Vin_m) to the drain of the transistor722(Vout_m). The capacitances726and728may be realized using discrete capacitors or transistor devices.

The amplifier circuit700also includes an exemplary embodiment of a matching network750. In an exemplary embodiment, the matching network750may be referred to as a load matching network configured to operate as an output matching network for the amplifier710. In an exemplary embodiment, the matching network750may also be configured to provide gain control for the amplifier710. In an exemplary embodiment, the matching network750includes a load inductance752, a differential mode (DM) load resistance (RDM)754and a differential mode load capacitance (CDM)756. Although shown as discrete elements, the differential mode load resistance (RDM)754and the differential mode load capacitance (CDM)756may be created by parasitic resistance and parasitic capacitance generated by the components in the amplifier circuit700. The matching network750may also be implemented using other components, such as, for example, transformers, or other components that may alter the impedance presented to the differential output714aand714bof the amplifier710.

In an exemplary embodiment, the matching network750also includes an adjustable gain control resistance770. In an exemplary embodiment, the adjustable gain control resistance770may be implemented using PMOS transistor devices to realize adjustable segments772and774. In an exemplary embodiment, the adjustable segment772may comprise a number (equal to n+1 in the embodiment illustrated inFIG.7) of PMOS transistors771through773. In an exemplary embodiment, the separately adjustable segment774may comprise the same number of PMOS transistors, illustrated inFIG.7as PMOS transistors777through779. Each of the PMOS transistors771through773and777through779are on when the gate voltage (illustrated inFIG.7as Vctrl<n:0>) provided to the gate of the respective PMOS transistor771through773and777through779is at zero volts or lower, that is, when the gate of the respective PMOS transistor771through773and777through779is coupled to a logic low signal, such as system ground. WhileFIG.7illustrates segments772and774receiving the same control signal, Vctrl, the segments772,774(or portions thereof) may receive control signals separate and/or different from each other, or may otherwise be separately adjustable.

In an exemplary embodiment, the drain of the transistor771is coupled to the source of the transistor777and also is coupled to the center node775. Similarly, the drain of the transistor773is coupled to the source of the transistor779and also is coupled to the center node775. In this way, a center node between all pairs of PMOS transistors in the adjustable gain control resistance670may be coupled together.

In the embodiment shown inFIG.7, separate control of the 1stharmonic termination and the 2ndharmonic termination is provided. For example, the node775is coupled to AC ground through a capacitance785and the node775is coupled to system voltage, VDD, through a resistance787. The capacitance785may be referred to as a bias capacitance, CB, and the resistance787may be referred to as a bias resistance, RB. In this exemplary embodiment, for an AC RF input signal, VDD and system ground are considered shorted. In this exemplary embodiment, the center node is DC biased to VDD through the resistor787. In this manner, there is no DC current flowing through the transistors771through773or the transistors777through779, and the transistors771through773and the transistors777through779operate as switches.

Depending on the actual layout implementation it might be easier to realize a low impedance connection to system ground or to system voltage, VDD. The connection from node475to system voltage VDD in the amplifier circuit400ofFIG.4may exhibit a low impedance at a frequency of 2fo. Depending on the circuit layout this might be challenging and or cause coupling issues when circuit connections are routed in top metal in a practical layout. The exemplary embodiment of the amplifier circuit700shown in inFIG.7eliminates such a low impedance connection. In the exemplary embodiment shown inFIG.7, the system voltage, VDD, provides only a DC voltage to the node775through a resistance787(RB), to bias the transistors771through773and777through779. The coupling between the node775and VDD may be realized practically with a low-level metal that presents a high impedance, thus eliminating coupling issues. In an exemplary embodiment, the capacitance785(CB) is provided to couple the node775to system ground to close the loop for the second harmonic current I2foand to provide a low impedance path to system ground in common mode.

The source of the transistor771is coupled to the output node714aand the source of the transistor773is coupled to the output node714a; and the drain of the transistor777is coupled to the output node714band the drain of the transistor779is coupled to the output node714b. Similarly, the source of any other transistor in segment772may be coupled to the output node714aand the drain of any other transistor in segment774may be coupled to the output node714b.

The state of the PMOS transistors771through773and777through779may be controlled by a control signal from the data processor210ofFIG.2or by another control unit (not illustrated) disposed elsewhere in the wireless device200. In an exemplary embodiment, the resistance provided by the transistors771and777may be determined by their size; and the resistance provided by the transistors773and779may also be determined by their size, that is, their width “W” divided by their length “L” (W/L). The on-resistance of the transistors771,773,777and779(and any other transistors in the adjustable gain control resistance770) is inversely proportional to W/L. In an exemplary embodiment, the size, and therefore the resistance, of each the transistors771and777may be the same or may be different from one or more other transistors, and similarly the size of each of the transistors773and779may be the same or may be different from one or more other transistors. The size of the transistors771through773, and the size of the transistors777through779may be the same and there may be an explicit common mode point at node775between the transistors771and777and between the transistors773and779. Therefore, the amount of resistance provided by the separately adjustable segments772and774may be determined by the size of the transistor devices and the number of transistor devices enabled to provide adjustable resistance.

In an exemplary embodiment, the adjustable gain control resistance770can be adjusted by one or more control signals from the data processor210(FIG.2) in differential mode (DM). For example, segments772and774of the adjustable gain control resistance (RGC/2)770may be adjusted to lower the differential mode load impedance, ZDM, fo, while allowing the fundamental current, Ifoto remain substantially unaffected and while the differential mode output voltage, VOUT; fo, decreases, thus providing a variable and in some embodiments linear gain control function to the amplifier710. The output current, that is the fundamental current, Ifoand the second harmonic current I2fois generated by the transconductance of the amplifier710. Therefore, the output current depends only on the input voltage, Vin, and the transconductance of the amplifier710(i.e., the output current does not depend on the output load). Accordingly, when the resistance of the load (Rload including RDMand RGC) varies, the output current, Iout, remains unaffected, but the output voltage, Vout, varies with the change in the load according to Vout=Iout*Rload. That is, the output voltage, Vout, varies with the varying resistance of the adjustable gain control resistance770. In an exemplary embodiment, the center node775provides a common mode AC path to ground through the capacitance785(CB) for the second harmonic current I2fo, thus allowing the second harmonic current I2foa low impedance path to ground, while allowing the common mode output voltage, VOUT, 2fo, to decrease linearly or non-linearly for the common mode as well as the differential mode.

In this manner, both the differential mode load impedance (ZDM,fo) and the common mode load impedance (ZCM, 2fo) can be simultaneously lowered by adjusting the adjustable gain control resistance770. An example range of resistance values for the adjustable gain control resistance770may be from a low impedance value of about 20 Ohm to a high impedance value of about 2K Ohm. These values are for example only and may differ based on implementation. In an exemplary embodiment, the resistance of the separately adjustable segments772and774of the adjustable gain control resistance770may be selectively adjusted to be the same resistance value.

In the exemplary embodiment shown inFIG.7, the output circuit480shown inFIG.4, is omitted fromFIG.7for ease of illustration; however, the output circuit480may also be implemented in the amplifier circuit700ofFIG.7.

FIG.8is a schematic diagram showing an exemplary embodiment of an implementation of an amplifier circuit800including an amplifier and a matching network having a variable gain control system in accordance with an exemplary embodiment. The amplifier circuit800may be an example of one or more of the amplifiers (320,322,324) and matching networks (312,314,316) shown inFIG.3. In an exemplary embodiment, the amplifier circuit800may include a variable gain control circuit that may provide fine gain control.

The amplifier circuit800includes an amplifier810, which can be a transconductance amplifier. The amplifier810may be configured to receive a differential input signal at nodes812aand812b, and may be configured to provide a differential output signal at nodes814aand814b. In an exemplary embodiment, the amplifier810may be implemented using NMOS transistors822and824. In an exemplary embodiment, the source of each transistor822and824may be coupled to system ground and the drain of each transistor822and824may be coupled to the output nodes814aand814b. The capacitances826and828are optional, and may be implemented in some mmW frequency systems to improve differential mode stability and gain, and are sometimes referred to as neutralization capacitors. In an exemplary embodiment, the capacitances826and828may be implemented to cancel the effect of gate-source capacitance (Cgs) of the transistor822and the transistor824. It an exemplary embodiment, the capacitance826connects the gate of the transistor822(Vin_p) to the drain of the transistor824(Vout_p) and the capacitance828connects the gate of the transistor824(Vin_m) to the drain of the transistor822(Vout_m). The capacitances826and828may be realized using discrete capacitors or transistor devices.

The amplifier circuit800also includes an exemplary embodiment of a matching network850. In an exemplary embodiment, the matching network850may be referred to as a load matching network configured to operate as an output matching network for the amplifier810. In an exemplary embodiment, the matching network850may also be configured to provide gain control for the amplifier810. In an exemplary embodiment, the matching network850includes a load inductance852, a differential mode (DM) load resistance (RDM)854and a differential mode load capacitance (CDM)856. Although shown as discrete elements, the differential mode load resistance (RDM)854and the differential mode load capacitance (CDM)856may be created by parasitic resistance and parasitic capacitance generated by the components in the amplifier circuit800. The matching network850may also be implemented using other components, such as, for example, transformers, or other components that may alter the impedance presented to the differential output814aand814bof the amplifier810.

In an exemplary embodiment, the matching network850also includes an adjustable gain control resistance870. In an exemplary embodiment, the adjustable gain control resistance870may be implemented using PMOS transistor devices to realize separately adjustable segments872and874. In an exemplary embodiment, the separately adjustable segment872may comprise a number (equal to n+1 in the embodiment illustrated inFIG.8) of PMOS transistors871through873. In an exemplary embodiment, the separately adjustable segment874may comprise the same number of PMOS transistors, illustrated inFIG.8as PMOS transistors877through879. Each of the PMOS transistors871through873and877through879are on when the gate voltage (illustrated inFIG.8as Vctrl<n:0>) provided to the gate of the respective PMOS transistor871through873and877through879is at zero volts or lower, that is, when the gate of the respective PMOS transistor871through873and877through879is coupled to a logic low signal, such as system ground. WhileFIG.8illustrates segments872and874receiving the same control signal, Vctrl, the segments872,874(or portions thereof) may receive control signals separate and/or different from each other, or may otherwise be separately adjustable.

In an exemplary embodiment, the drain of the transistor871is coupled to the source of the transistor877and also is coupled to a node875. Similarly, the drain of the transistor873is coupled to the source of the transistor879and also is coupled to a node876.

In the embodiment shown inFIG.8, separate control of the 1stharmonic termination and the 2ndharmonic termination is provided. For example, the node875is coupled to AC ground through a capacitance885and the node875is coupled to system voltage, VDD, through a resistance887. The capacitance885may be referred to as a bias capacitance, CB, and the resistance887may be referred to as a bias resistance, RB. Similarly, the node876is coupled to AC ground through a capacitance895and the node876is coupled to system voltage, VDD, through a resistance897. The capacitance895may be referred to as the nth bias capacitance, nCB, and the resistance897may be referred to as the nth bias resistance, nRB. It will be understood that a center node between each pair of PMOS transistors in the adjustable gain control resistance870may be coupled to system ground through a respective capacitor and to system voltage, VDD, through a respective resistor.

Similar to the amplifier circuit700ofFIG.7, depending on the actual layout implementation it might be easier to realize a low impedance connection to system ground or to system voltage, VDD. The connection from node475to system voltage VDD in the amplifier circuit400ofFIG.4may exhibit a low impedance at a frequency of 2fo. Depending on the circuit layout this might be challenging and/or cause coupling issues when circuit connections are routed in top metal in a practical layout. The exemplary embodiment of the amplifier circuit800shown in inFIG.8, similar toFIG.7, eliminates such a low impedance connection. In the exemplary embodiment shown inFIG.8, the system voltage, VDD, provides only a DC voltage separately to the node875through a resistance887(RB), and separately provides a DC voltage to the node876through a resistance897(nRB), (to bias the transistors871and877separately from biasing the transistors873and879). The coupling between the node875and VDD, and the coupling between the node876and VDD may be realized practically with a low-level metal that presents a high impedance, thus eliminating coupling issues. To close the loop for the second harmonic current I2foand to provide a low impedance path to system ground in common mode, the capacitance885(CB) is provided to couple the node875to system ground and the capacitance895(nCB) is provided to couple the node876to system ground. In this manner, the common mode impedance may be separately controlled by separately controlled instances of transistor pairs in the adjustable gain control resistance870.

The amplifier circuit800ofFIG.8is similar to the amplifier circuit700ofFIG.7. However, in the amplifier circuit700ofFIG.7, the common mode impedance presented to the amplifier700depends only on the transistors (771through773and777through779) in the adjustable gain control resistance770. In the exemplary embodiment of the amplifier circuit800shown inFIG.8, the common mode impedance presented to the amplifier800depends also on the various CBthrough nCB, and RBthrough nRBcircuits that are enabled separately with the transistors in the adjustable segment872and the adjustable segment874.

The source of the transistor871is coupled to the output node814aand the source of the transistor873is coupled to the output node814a; and the drain of the transistor877is coupled to the output node814band the drain of the transistor879is coupled to the output node814b. Similarly, the source of any other transistor in segment872may be coupled to the output node814aand the drain of any other transistor in segment874may be coupled to the output node814b.

The state of the PMOS transistors871through873and877through879may be controlled by a control signal from the data processor210ofFIG.2or by another control circuit (not illustrated) disposed elsewhere in the wireless device200. In an exemplary embodiment, the resistance provided by the transistors871and877may be determined by their size; and the resistance provided by the transistors873and879may also be determined by their size, that is, their width “W” divided by their length “L” (W/L). The on-resistance of the transistors871,873,877and879(and any other transistors in the adjustable gain control resistance770) is inversely proportional to W/L. In an exemplary embodiment, the size, and therefore the resistance, of each the transistors871and877may be the same or may be different from one or more other transistors, and similarly the size of each of the transistors873and879may be the same or may be different from one or more other transistors. The size of the transistors871through873, and the size of the transistors877through879may be the same and there may be an explicit common mode point at node875between the transistors871and877and an explicit common mode point at node876between the transistors873and879. Therefore, the amount of resistance provided by the adjustable segments872and874may be determined by the size of the transistor devices and the number of transistor devices enabled by the control signal(s) (e.g., Vctrl<n:0>) to provide adjustable resistance.

In an exemplary embodiment, the adjustable gain control resistance870can be adjusted by one or more control signals from the data processor210(FIG.2) in differential mode (DM). For example, segments872and874of the adjustable gain control resistance870may be adjusted to lower the differential mode load impedance, ZDM, fo, while allowing the fundamental current, Ifoto remain substantially unaffected and while the differential mode output voltage, VOUT, fo, decreases, thus providing a variable and in some embodiments linear gain control function to the amplifier810. The output current, that is the fundamental current, Ifoand the second harmonic current I2fois generated by the transconductance of the amplifier810. Therefore, the output current depends only on the input voltage, Vin, and the transconductance of the amplifier810(i.e., the output current does not depend on the output load). Accordingly, when the resistance of the load (Rload including RDMand RCG/2) varies, the output current, Iout, remains unaffected, but the output voltage, Vout, varies with the change in the load according to Vout=Iout*Rload. That is, the output voltage, Vout, varies with the varying resistance of the adjustable gain control resistance870. In an exemplary embodiment, the center node875and the center node876separately provide a common mode AC path to ground through the capacitance885(CB) and the capacitance895(nCB), respectively, for the second harmonic current I2fo, thus allowing the second harmonic current I2foa low impedance path to ground, while allowing the common mode output voltage, VOUT, 2fo, to decrease linearly, or non-linearly, for the common mode as well as the differential mode.

In this manner, both the differential mode load impedance (ZDM, fo) and the common mode load impedance (ZCM, 2fo) can be simultaneously lowered by adjusting the adjustable gain control resistance870. An example range of resistance values for the adjustable gain control resistance870may be from a low impedance value of about 20 Ohm to a high impedance value of about 2K Ohm. These values are for example only and may differ based on implementation. In an exemplary embodiment, the resistance of the separately adjustable segments872and874of the adjustable gain control resistance (RGC/2)870may be selectively adjusted to be the same resistance value.

In the exemplary embodiment shown inFIG.8, the output circuit480shown inFIG.4, is omitted fromFIG.8for ease of illustration; however, the output circuit480may also be implemented in the amplifier circuit800ofFIG.8.

FIG.9is a flow chart900describing an example of a variable gain control method900. The blocks in the method900can be performed in or out of the order shown, and in some embodiments, can be performed at least in part in parallel.

In block902, a radio frequency (RF) signal is amplified with an amplifier circuit. For example, the amplifier410ofFIG.4may amplify an RF signal.

In block904, a common mode current is coupled to ground. For example, a center node475may couple a common mode current of the amplifier410to system ground or to AC ground.

In block906, the resistance of each of two adjustable segments may be independently varied to provide linear gain control. For example, the two adjustable segments472and474of the adjustable gain control resistance470may be separately varied.

FIG.10is a functional block diagram of an apparatus1000for variable gain control. The apparatus1000comprises means1002for amplifying a radio frequency (RF) signal. In certain embodiments, the means1002for amplifying a radio frequency (RF) signal can be configured to perform one or more of the functions described in operation block902of method900(FIG.9). In an exemplary embodiment, the means1002for amplifying a radio frequency (RF) signal may comprise the amplifier410ofFIG.4, for example configured to amplify an RF signal.

The apparatus1000also comprises means1004for coupling a common mode current to ground. The means1004for coupling a common mode current to ground can be configured to perform one or more of the functions described in operation block904of method900(FIG.9). In an exemplary embodiment, the means1004for coupling a common mode current to ground may comprise a center node475, for example configured to couple a common mode current of the amplifier410to system ground or to AC ground.

The apparatus1000also comprises means1006for independently varying the resistance of each of the two adjustable segments to provide linear gain control. The means1006for independently varying the resistance of each of the two adjustable segments to provide linear gain control can be configured to perform one or more of the functions described in operation block906of method900(FIG.9). In an exemplary embodiment, the means1006for independently varying the resistance of each of the two adjustable segments to provide linear gain control may comprise the two adjustable segments472and474of the adjustable gain control resistance470being separately varied.

The circuit architecture described herein described herein may be implemented on one or more ICs, analog ICs, RFICs, mixed-signal ICs, ASICs, printed circuit boards (PCBs), electronic devices, etc. The circuit architecture described herein may also be fabricated with various IC process technologies such as complementary metal oxide semiconductor (CMOS), N-channel MOS (NMOS), P-channel MOS (PMOS), bipolar junction transistor (BJT), bipolar-CMOS (BiCMOS), silicon germanium (SiGe), gallium arsenide (GaAs), heterojunction bipolar transistors (HBTs), high electron mobility transistors (HEMTs), silicon-on-insulator (SOI), etc.

An apparatus implementing the circuit described herein may be a stand-alone device or may be part of a larger device. A device may be (i) a stand-alone IC, (ii) a set of one or more ICs that may include memory ICs for storing data and/or instructions, (iii) an RFIC such as an RF receiver (RFR) or an RF transmitter/receiver (RTR), (iv) an ASIC such as a mobile station modem (MSM), (v) a module that may be embedded within other devices, (vi) a receiver, cellular phone, wireless device, handset, or mobile unit, (vii) etc.