Current signal generation useful for sampling

Sampler circuitry including load circuitry having sampler switches to sample first and second load currents, the load circuitry having first and second load nodes and a biasing node; a power supply node connected to a voltage source; a first current path extending from the power supply node to the first load node to provide the first load current at the first load node, where a first supply-connection impedance is connected along the first current path; a second current path extending, in parallel with the first current path, from the power supply node to the second load node to provide the second load current at the second load node for use by the load circuitry, where a second supply-connection impedance is connected along the second current path between the power supply node and the second load node; first and second input-connection impedances; and control circuitry.

CROSS-REFERENCE OF RELATED APPLICATIONS

This application claims the benefit of European Patent Application 19180669.4, filed on Jun. 17, 2019, the entire disclosure of which Application is incorporated by reference herein.

The present invention relates to current signal generation useful for sampling, and in particular to circuitry for receiving an input voltage signal and generating a current signal based on the input voltage signal.

Such circuitry comprises load circuitry, which may be current-mode circuitry, operable based on the current signal. In one example, the current-mode circuitry may be part or all of a sampler operable to sample the current signal (representative of the input voltage signal). For ease of understanding, such an example will be followed herein with applicability in or as analogue-to-digital circuitry. Corresponding methods are also envisaged.

By way of context, reference may be made to EP2211468,FIGS. 9, 10 and 16of which are reproduced asFIGS. 1, 2 and 3herein. A brief description of these Figures is provided below to aid the reader in understanding a potential application of the present invention. A fuller description can be found in EP2211468.

The sampler42is configured to perform four-way or four-phase time-interleaving so as to split the input current IINinto four time-interleaved sample streams A to D. The sampler42operates in the current mode, and, accordingly, streams A to D are effectively four time-interleaved streams of current pulses originating from (and together making up) input current IIN, each stream having a sample rate one quarter of the overall sample rate. Four sets of n digital streams (following multiplexing46and analogue-to-digital conversion 48) are input to the digital unit50which multiplexes those streams to produce a single digital output signal representative of the analogue input signal, current IIN. Calibration unit52calibrates operation of the sampler42, demultiplexers46and/or ADC banks (sub-ADC units)48, based on the digital output signal.

FIG. 2is a schematic circuit diagram of four-phase (i.e. multiphase) current-mode (current-steering) sampler42. Sampler42is configured to receive such a differential input current signal, modeled here as a current source W whose magnitude varies with the input signal. Because of the differential signaling, sampler42effectively has two matching (or corresponding or complementary) sections54and56for the two differential inputs. Accordingly, there is a first set of output streams IOUTAto IOUTDin section54and a second set of matching output streams IOUTBAto IOUTBD, where IOUTB meansIOUT, and wherein IOUTAis paired with IOUTBA, IOUTBis paired with IOUTB, and so on and so forth.

Focusing on the first section54by way of example (because the second section56operates analogously to the first section54), there are provided four n-channel MOSFETs58Ato58D(i.e. one per stream or path) with their source terminals connected together at a common tail node60. The gate terminals of the four transistors58Ato58Dare driven by the four clock signals θ0to θ3, respectively, provided from the VCO44.

The current drawn from the common tail node60is defined by the DC current source62for that node and the current source IN. Similarly, the current drawn from the common tail node66(of the second section56) is defined by the DC current source68for that node and the current source IIN. Transistors64Ato64Dof section56correspond respectively to transistors58Ato58Dof section54, and are similarly driven by the four clock signals θ0to θ3, respectively, provided from the VCO44.

As already mentioned, ADC circuitry41operates in the current domain, i.e. effectively as a current-mode ADC. As a result, the input signal required is a current signal. However, typical signals that require use of an ADC or sampler are voltage-domain signals, in which the variable under examination is a voltage rather than a current.FIG. 3is a schematic circuit diagram of an example implementation43of sampling circuitry (sampler)42, to which it is possible to apply an input differential voltage signal. Implementation43, similarly to circuitry42, comprises two sections54and56for the so-called “plus” and “minus” components of the differential signals. Section54comprises switching transistors58Ato58Dconnected to common tail node60, and section56comprises switching transistors64Ato64Dconnected to common tail node66, as before.

Implementation43basically works by receiving the input voltage signal and by employing resistances to passively convert the received input voltage signal into an equivalent input current signal. An example set of resistance values are shown inFIG. 3. These values have been chosen assuming an example design objective that the input impedance looking into each of the common tail nodes60and66towards the switching transistors (sampler switches) is 50Ω, and that the input impedance looking into each of the input terminals104and106is also 50Ω as shown inFIG. 3.

There is ever increasing pressure on the performance of such circuitry, in particular sampler circuitry (for example for an ADC), for example in relation to its bandwidth.

It is desirable to provide improved circuitry in light of the above.

According to an embodiment of a first aspect of the present invention, there is provided sampler circuitry, comprising: an input node configured to receive an input voltage signal; a primary current path connected between high and low voltage supply nodes; a secondary current path connected between high and low voltage supply nodes; current mirror circuitry; and load circuitry comprising sampler switches operable to sample a current signal, wherein: the input node is defined along the primary current path, the primary current path configured to carry a primary current dependent on the input voltage signal; the current mirror circuitry comprises a primary side and a secondary side, the primary side connected along the primary current path and the secondary side connected along the secondary current path so that a secondary current dependent on the primary current is caused to flow along the secondary current path; and the load circuitry is connected along the secondary current path so that the secondary current at least partly forms the current signal.

Such circuitry enables the secondary current to be provided with gain compared to the primary current. The sampler circuitry can be considered to be “folded” due to the current mirror circuitry. The “folding” of the sampler circuitry enables reduced stacking and achieves associated advantages as described herein. The “folding” of the sampler circuitry can lead to improved S11 (the S11 scattering parameter) performance, and can reduce a trade-off between S11 performance and gain which can affect other circuitry aimed at providing a current signal.

The load circuitry is connected along the secondary current path rather than along the primary current path so that the secondary current rather than the primary current at least partly forms the current signal.

The high voltage supply node for the primary current path and the high voltage supply node for the secondary current path may be the same as or different from each other. The low voltage supply node for the primary current path and the low voltage supply node for the secondary current path may be the same as or different from each other.

The sampler circuitry may comprise a current source connected along the primary current path and configured to define a bias current flowing along that path.

The primary current may be considered to comprise: a DC bias current component defined by the current source; and an AC current component dependent on the input voltage signal.

The input node may be located along the primary current path so as to divide the primary current path into first and second portions, the first portion of the primary current path configured to carry the primary current; and the primary side of the current mirror circuitry may be connected along the first portion of the primary current path.

The sampler circuitry may comprise an impedance connected in series along the first portion of the primary current path between the input node and the primary side of the current mirror circuitry.

The impedance may be referred to as a second impedance, and the sampler circuitry may comprise a first impedance connected in series along the second portion of the primary current path.

The first impedance may be implemented as a resistor or as a resistor connected in series with an inductor and/or the second impedance may be implemented as a resistor or as a resistor connected in parallel with a capacitor.

The sampler circuitry may comprise: a third impedance connected in series along the primary current path between the high voltage supply node concerned and the primary side of the current mirror circuitry; and/or a fourth impedance connected in series along the secondary current path between the high voltage supply node concerned and the secondary side of the current mirror circuitry.

The third impedance may be implemented as a resistor or as a resistor connected in series with an inductor; and/or the fourth impedance may be implemented as a resistor or as a resistor connected in parallel with a capacitor.

The sampler circuitry may comprise a fifth impedance connected between the primary and secondary sides of the current mirror circuitry. The fifth impedance may be connected between gate terminals of a diode-connected transistor of the primary side and a corresponding mirror transistor of the secondary side of the current mirror circuitry. The fifth impedance may be implemented as an inductor.

The sampler circuitry may comprise control circuitry operable to configure the current mirror circuitry so as to control a gain provided by the current mirror circuitry in the secondary current relative to the primary current.

The control circuitry may be configured to control one or more voltage signals applied to the gates of one or more transistors of the current mirror circuitry. The control circuitry may be configured to control the one or more voltage signals applied to the gates of the one or more transistors of the current mirror circuitry to switch the or those transistors on or off, to control the gain provided by the current mirror circuitry. Thereby the gain may be adjusted. In other words, the sampler circuitry can achieve programmability (programmable gain). The gain may be adjusted to compensate for loss due to parasitic capacitance and any other effects which might degrade the signal level of the current signal. That is, calibration may be performed by adjusting/programming the gain to tune out parasitic capacitances and other effects that reduce the magnitude of or otherwise degrade the current signal.

The primary and secondary sides of the current mirror circuitry may each comprise at least one cascode transistor, and the voltage signals controlled by the control circuitry may be voltage signals provided to the gates of cascode transistors of the current mirror circuitry. These voltage signals may be provided to the gates of one or more cascode transistors of the secondary side of the current mirror circuitry.

The control circuitry may be configured to control one or more gate voltages of one or more cascode transistors, respectively, of the primary side of the current mirror circuitry so that the one or more cascode transistors of the primary side of the current mirror circuitry operate at or around the border of their triode and saturation regions.

The sampler switches may comprise switching transistors. The load circuitry may be a front-end of an analogue-to-digital converter. The load circuitry may comprise current-mode circuitry.

According to an embodiment of a second aspect of the present invention, there is provided differential sampler circuitry comprising a first section and a second section, the first and second sections each comprising sampler circuitry of the aforementioned first aspect of the present invention.

The differential sampler circuitry may comprise differential load circuitry comprising the load circuitry of the first section and the load circuitry of the second section, the first and second sections may share the same current source, and the differential sampler circuitry may be configured to: receive a differential input voltage signal as said input voltage signals received by the first and second sections; and output to the differential load circuitry a differential output current signal as said current signals.

According to an embodiment of a third aspect of the present invention, there is provided analogue-to-digital conversion circuitry operable to generate a digital output signal based upon an analogue input differential current signal, wherein: the analogue-to-digital conversion circuitry comprises the differential sampler circuitry of the aforementioned second aspect of the present invention; and the analogue input differential current signal of the analogue-to-digital conversion circuitry comprises the differential output current signal of the differential sampler circuitry.

According to an embodiment of a fourth aspect of the present invention, there is provided analogue-to-digital conversion circuitry comprising the sampler circuitry of the aforementioned first aspect of the present invention, or the differential sampler circuitry of the aforementioned second aspect of the present invention.

According to an embodiment of a fifth aspect of the present invention, there is provided integrated circuitry, such as an IC chip, comprising the sampler circuitry of the aforementioned first aspect of the present invention, or the differential sampler circuitry of the aforementioned second aspect of the present invention, or the analogue-to-digital conversion circuitry of the aforementioned third aspect of the present invention, or the analogue-to-digital conversion circuitry of the aforementioned fourth aspect of the present invention.

According to an embodiment of a sixth aspect of the present invention, there is provided a circuitry system, comprising: an input node configured to receive an input voltage signal; a primary current path connected between high and low voltage supply nodes; a secondary current path connected between high and low voltage supply nodes; current mirror circuitry; and load circuitry operable based on a current signal, wherein: the input node is defined along the primary current path, the primary current path configured to carry a primary current dependent on the input voltage signal; the current mirror circuitry comprises a primary side and a secondary side, the primary side connected along the primary current path and the secondary side connected along the secondary current path so that a secondary current dependent on the primary current is caused to flow along the secondary current path; and the load circuitry is connected along the secondary current path so that the secondary current at least partly forms the current signal.

According to an embodiment of a seventh aspect of the present invention, there is provided sampler circuitry, comprising: a voltage input node; a current source for supplying a sampling current to the voltage input node; a plurality of switch transistors for sampling input current signals; and a current mirror circuit that couples the plurality of switch transistors with the voltage input node and the current source.

According to an embodiment of an eighth aspect of the present invention, there is provided sampler circuitry operable (configured to be operated) based on a differential input voltage signal provided between first and second input nodes, the sampler circuitry comprising: load circuitry comprising sampler switches configured to sample first and second load currents which define a differential current signal, the load circuitry having first and second load nodes and a biasing node; a power supply node for connection to a voltage source; a first current path extending from the power supply node to the first load node to provide the first load current at the first load node for use by the load circuitry, wherein a first supply-connection impedance is connected along the first current path between the power supply node and the first load node; a second current path extending, in parallel with the first current path, from the power supply node to the second load node to provide the second load current at the second load node for use by the load circuitry, wherein a second supply-connection impedance is connected along the second current path between the power supply node and the second load node; first and second input-connection impedances; and control circuitry, wherein: the control circuitry is configured, based on measurement of a common mode voltage indicative of a common mode between voltages at the first and second load nodes, to control a biasing signal provided to the biasing node of the load circuitry to regulate the common mode voltage; and the first and second input nodes are connected to the first and second load nodes via the first and second input-connection impedances, respectively, so that the differential current signal is dependent on the differential input voltage signal.

Such circuitry can achieve “peaking” in the gain profile—i.e. gain boosting at high frequency. In other words such circuitry can achieve gain, where gain here refers to the ratio of the magnitude of the differential current signal at high (higher) frequencies (of the differential input voltage signal) to the magnitude of the differential current signal at low (lower) frequencies (of the differential input voltage signal). The sampler circuitry of the eighth aspect of the present invention (between the input and load nodes, i.e. excluding the load circuitry) can be considered to be passive. The sampler circuitry of the eighth aspect of the present invention can achieve reduced stacking and can achieve decoupling of the S11 performance from the gain.

In the aforementioned eighth aspect of the present invention, the control circuitry may comprise first and second measurement impedances connected in series between the first and second load nodes, and may be configured to measure the common mode voltage from a measurement node between the first and second measurement impedances.

The first and second measurement impedances may be implemented as resistors; and/or the first and second measurement impedances may have the same impedance as one another.

The sampler circuitry of the aforementioned eighth aspect of the present invention may comprise an auxiliary current path connected between the first and second input nodes, and having an auxiliary impedance connected therealong.

The first and second supply-connection impedances may be implemented as resistors or as resistors connected in series with respective inductors; and/or the first and second supply-connection impedances may have the same impedance as one another; and/or the first and second input-connection impedances may be implemented as resistors or as resistors connected in parallel with respective capacitors; and/or the first and second input-connection impedances may have the same impedance as one another; and/or the auxiliary impedance may be implemented as a resistor or as a resistor connected in series with an inductor.

The first and second load currents may be considered to comprise: respective DC bias current components defined by a voltage level of the voltage source, the first and second supply-connection impedances, respectively, and the common-mode voltage; and respective AC current components dependent on the differential input voltage signal.

The regulation of the common mode voltage may cause the DC bias currents to be regulated.

In the aforementioned eighth aspect of the present invention, the sampler switches may comprise switching transistors connected to the first and second load nodes, and the biasing signal may control the DC voltage level of gate-control switching signals provided to the gate terminals of the switching transistors.

In the aforementioned eighth aspect of the present invention, the load circuitry may be a front-end of an analogue-to-digital converter. In the aforementioned eighth aspect of the present invention, the load circuitry may comprise current-mode circuitry. In the aforementioned eighth aspect of the present invention, the load circuitry may be differential load circuitry.

According to an embodiment of a ninth aspect of the present invention, there is provided analogue-to-digital conversion circuitry operable to generate a digital output signal based upon an analogue input differential current signal, wherein: the analogue-to-digital conversion circuitry comprises the sampler circuitry of the aforementioned eighth aspect of the present invention; and the sampler circuitry is configured to generate the analogue input differential current signal as said differential current signal dependent on the differential input voltage signal.

According to an embodiment of a tenth aspect of the present invention, there is provided integrated circuitry, such as an IC chip, comprising the sampler circuitry of the aforementioned eighth aspect of the present invention, or the analogue-to-digital conversion circuitry of the aforementioned ninth aspect of the present invention.

According to an embodiment of an eleventh aspect of the present invention, there is provided differential circuitry operable (configured to be operated) based on a differential input voltage signal provided between first and second input nodes, the differential circuitry comprising: load circuitry configured to operate based on first and second load currents which define a differential current signal, the load circuitry having first and second load nodes and a biasing node; a power supply node for connection to a voltage source; a first current path extending from the power supply node to the first load node to provide the first load current at the first load node for use by the load circuitry, wherein a first supply-connection impedance is connected along the first current path between the power supply node and the first load node; a second current path extending, in parallel with the first current path, from the power supply node to the second load node to provide the second load current at the second load node for use by the load circuitry, wherein a second supply-connection impedance is connected along the second current path between the power supply node and the second load node; first and second input-connection impedances; and control circuitry, wherein: the control circuitry is configured, based on measurement of a common mode voltage indicative of a common mode between voltages at the first and second load nodes, to control a biasing signal provided to the biasing node of the load circuitry to regulate the common mode voltage; and the first and second input nodes are connected to the first and second load nodes via the first and second input-connection impedances, respectively, so that the differential current signal is dependent on the differential input voltage signal.

According to an embodiment of a twelfth aspect of the present invention, there is provided sampler circuitry, comprising: a pair of differential voltage input nodes; a pair of switch transistor groups for sampling input current signals; a pair of first resistors (input resistors) provided between the pair of switch transistor groups and the pair of differential input nodes; a second resistor (for detecting a common mode voltage) provided between the pair of switch transistor groups; a pair of third resistors (for flowing a sampling current) provided between the pair of switch transistor groups and a voltage source node (AVD); and a feedback loop control circuit that controls a DC voltage supplied to gates of switch transistors constituting each of the switch transistor groups so that a constant current flows through the third resistors on the basis of a voltage of an intermediate node of the second resistor.

Features of method aspects may apply equally to apparatus (circuitry) aspects, and vice versa.

FIG. 4is a schematic diagram of sampler circuitry100, as a comparative example. Similarities with the implementation43of sampling circuitry42shown inFIG. 3will be apparent. Sampler circuitry100is shown inFIG. 4as differential circuitry operable based on a differential input voltage signal. It will be apparent that sampler circuitry100may also be provided as single-ended circuitry operable based on a single-ended input voltage signal.

Sampler circuitry100comprises two matching (or corresponding or complementary) sections101and102for the two differential inputs (i.e. the two input voltage signals which form the differential input voltage signal). The first section101comprises an input node14A, a first impedance20A, a second impedance30Aand a load node16A. The input node14Ais configured to receive an input voltage signal VINPvia a terminal15A. The input node14Aand the terminal15Aas shown inFIG. 4are denoted separately but they could be the same. The input node14Ais connected to a tail node12via the first impedance20A. The tail node12is connected via a current source10to a voltage reference (power supply node, or equally voltage source node) VHwhose voltage level is above that of VINP(and VINM). In particular, current source10supplies a constant (regulated) DC current IDCto the sampler circuitry100. The current IDCmay be referred to as a bias current and/or as a sampler current. The input node14Ais connected to the load node16Avia the second impedance30A. The second section102has a corresponding arrangement (with like elements denoted with a subscript B rather than a subscript A) as shown inFIG. 4, including an input node14Bto receive an input voltage signal VINM. A detailed description of the second section102is therefore omitted. Input voltage signals VINPand VINMare the “plus” and “minus” components of the (differential) input voltage signal.

Sampler circuitry100comprises load circuitry40. As shown inFIG. 4, load circuitry40comprises switches40A0to40AN-1connected to the load node16Aof the first section101, and switches40B0to40BN-1connected to the load node16Bof the second section102. The switches40A0to40AN-1and40B0to40BN-1may be referred to as sampling switches or sampler switches. In line withFIGS. 1 to 3, these sampling switches may be the sampling switches of a current-mode sampler (in such a case the sampling switches40A0to40AN-1and40B0to40BN-1may be controlled by time-interleaved clock signals). In general, however, it will be appreciated that the load circuitry40may comprise any current-mode circuitry. The load circuitry40(or subsequent circuitry connected beyond the load circuitry40) will of course be connected to a voltage reference (power supply node) VLwhose voltage level is below that of the voltage reference VH. The voltage reference VHmay be referred to as a high reference voltage and the voltage reference VLmay be referred as a low voltage reference, and the potential difference between VHand VLmay be referred to as the supply voltage (provided by a power supply).

In overview, sampler circuitry100operates by receiving the input voltage signal and by employing impedances to passively convert the received input voltage signal into an equivalent input current signal. For example, a differential input current signal is received by the load circuitry between (or at) the load nodes16Aand16B. In this regard, sampler circuitry100comprises voltage-to-current conversion circuitry, its output being the current signal received by the load circuitry40between the load nodes16Aand16B. Further, the sampler circuitry100may be referred to simply as circuitry or a circuitry system.

The first impedance20Aas shown inFIG. 4comprises a resistor21A and an inductor22Aconnected together in series. The second impedance30Aas shown inFIG. 4comprises a resistor31Aand a capacitor33Aconnected together in parallel and an inductor32Aconnected with the resistor31A in series. In other arrangements the first impedance20Aand the second impedance30A may comprise any component(s) that give rise to an impedance. The same considerations apply to the first and second impedances20Band30Bof the second section102.

As described above, sampler circuitry100can also be provided as single-ended circuitry operable based on a single-ended input voltage signal and operable to output a single-ended current signal. That is, single-ended sampler circuitry may comprise the first section101, the current source10, the tail node12and load circuitry (e.g. the relevant part of the load circuitry40). The following description of the operation of the sampler circuitry100will be understood to apply equally to a single-ended implementation.

A brief summary of operation of sampler circuitry100is as follows, focusing on the first section101by way of example (with the understanding that sampler circuitry100may be single-ended and that in the case of differential sampler circuitry100a corresponding explanation applies for the second section102). Ignoring for the moment the capacitor33A(as if it were not present) and the inductors22Aand32A(as if they were shorted), i.e. considering operation at DC, the amount of current flowing through resistor31Ais effectively a portion of the current IDCdependent in part on the value of the input voltage signal VINP(and of course the resistance/impedance values). This current flows through the load circuitry40(the switches40A0to40AN-1, inFIG. 4) and may be referred to as a load current (or a first load current for a differential implementation of sampler circuitry100). A current IINPis drawn in at the input node14Aand is split between resistors21Aand31A. The proportion of the current IINPwhich flows through each of the resistors21Aand31Acan be adjusted by appropriate selection of the resistance values of the resistors21Aand31A. It is possible to select these resistors for each application so that the desired proportion of the current IINPflows through each of the resistors21Aand31A. However, it is difficult to make the resistance values of the resistors21Aand31Aswitchable without affecting bandwidth and input parasitic capacitance of the sampler circuitry100. For the purpose of the following description it is assumed that sampler circuitry100corresponds generally to the sampler42ofFIG. 1and connects to the input of sub-ADC units (corresponding to the sub-ADC units48ofFIG. 1), perhaps via demultiplexing stages (corresponding to demultiplexing stages46ofFIG. 1), but as mentioned above the load circuitry40could be any current-mode circuitry.

At high frequency (of the input voltage signal VINP), there are two peaking mechanisms which boost the amount of current passing though the sampler switches40A0to40AN-1. The first peaking mechanism is the capacitor33A, which may be referred to as a shunting capacitor. At high frequencies (in relative terms), the effective AC resistance of the resistor31A connected in parallel to the capacitor33A drops, which in turn increases the amount of current injected to the sampler switches40A0to40AN-1. The second peaking mechanism is the inductor22A. At high frequencies (in relative terms), the inductor22A increases the impedance seen looking into the first impedance20Afrom the input (or branch) node14and so causes the proportion of the current IINPwhich flows through the first impedance20Ato decrease. On the other hand, the impedance seen looking into the input node14Afrom the input terminal15Aincreases, which in turn causes the current IINPto decrease. The amount of current drop in the proportion of the current IINPflowing through the first impedance20Ais more than the overall current drop in the current IINP. So, the overall effect of the inductor22A is that the proportion of the current IINPflowing through the second impedance30A (and so the current flowing through the sampler switches40A0to40AN-1) increases in magnitude. Corresponding considerations apply to the second section102and the current flowing through the sampler switches40B0to40BN-1.

Due to the shunting mechanism described above with regard to the shunting capacitor33A, the impedance seen looking into the input node14Afrom the input terminal15Achanges significantly, which leads to unwanted effects. To restore some of this impedance and bring it closer to its ideal value (for example 50 ohms), the inductor32Ais added to the second impedance30A. The inductor32Ahelps to bring the scattering parameter S11 (a common measure of the performance of a circuit) close to its required or desired value.

It has been found that there are some disadvantages with the structure of the sampler circuitry100shown inFIG. 4, which are described below with reference to the first section101of the sampler circuitry100(with the same considerations applying to the second section102).

A first disadvantage is that there is a strong trade-off between the amount of gain (peaking) and the value of the S11 parameter. Gain is used here to refer to the amount of gain “peaking”, i.e. the current flowing into the load node16A at high frequency (of the input voltage signal VINP/M) compared to at low frequency (of the input voltage signal VINP/M), in particular the ratio of the amount of current passing through the load node16A(and thus the sampler switches) at high input frequencies divided by the amount of current passing through the load node16Aat low input frequencies. Of course, in general the gain of the sampler circuitry100can be considered to be the current flowing into the load node16Adivided by the input voltage VINP, or in the differential case to be the difference between the currents flowing into the load nodes16Aand16Bdivided by the difference between VINPand VINM. Gain in this latter sense could be expressed as I=G(f)·Vin, where Vin is the input voltage, I is the output current and Gain G(f) is a function of frequency f of the input voltage signal. Increasing the value of the inductance of the inductor22Aand/or the value of capacitance of the shunting capacitor33A, although increasing gain peaking, takes the impedance seen looking into the input node14Afrom the input terminal15Afurther away from its ideal value which in turns degrades the value of the S11 parameter.

A second disadvantage is a relatively low voltage headroom. That is, there is a large number of devices/components stacked on top of one another, from the current source10down to the load circuitry40(and other subsequent circuitry). The supplied voltage is “used up” by the large number of devices stacked on top of one another. This puts pressure in terms of voltage headroom on the devices (in particular, of the load circuitry40) and makes it difficult (and up to a point, impossible) to reduce the voltage supply (which would be advantageous from a power-saving point of view).

A third disadvantage is the difficulty associated with current scaling. That is, the amount of current that can be injected towards the current mode input circuit (i.e. to the load node16A) is a portion of the current IDC. For higher resolution applications (taking the ADC application as an example) it is useful to scale the current supplied to the load node16A(for example, in an ADC the thermal noise of the sampling capacitor is a limit and therefore a higher capacitance value for the sampling capacitor may be required which requires a much higher value of the current IDC). In order to increase the value of IDC, the voltage drop of the resistors21Aand31Amust be reduced. This will result in a lower characteristic impedance seen looking into the input node14Afrom the input terminal15A(e.g. less than a desired 50 Ohm). This makes the shunting capacitor33Amuch less effective. That is, to achieve a reasonable effect using the shunting capacitor33Ain view of the lower characteristic impedance, the shunting capacitor33Awould need to be very large, which is not feasible in practice since such a large capacitor33Awould give rise to much more parasitic capacitance and thereby degrade the bandwidth of the sampler circuitry100, which is not desirable. Moreover, the stacking of the devices in the sampler circuit100would be much more difficult with higher currents.

To overcome some of these disadvantages (among others), two example arrangements are disclosed herein.

FIG. 5is a schematic diagram of a first example arrangement200of sampler circuitry.

Sampler circuitry200is shown inFIG. 5as differential circuitry operable based on a differential input voltage signal. Sampler circuitry200can also be provided as single-ended circuitry operable based on a single-ended input voltage signal.

It will become apparent that the sampler circuitry200is similar to the circuitry100, but uses a current mirror approach to address the above-mentioned problems. The current mirror enables the circuit to have a “folded” structure. As explained in more detail below, the current mirror also provides additional gain. Further, the various impedances impact the operation to provide gain boosting at high frequencies as compared to at low frequencies.

Sampler circuitry200comprises two matching (or corresponding or complementary) sections201and202for the two differential inputs, similar to the circuitry100.

The first section201comprises an input node214A, a mirror node218A, a first impedance220A, a second impedance230A, a third impedance270A, a fourth impedance280A, current mirror circuitry265A, a primary reference node290A, a secondary reference node292A, a load node216Aand load circuitry240A.

The input node214Ais configured to receive an input voltage signal VINPvia a terminal215A. The input node214Aand the terminal215Aas shown inFIG. 5are provided separately but they could be the same. The input node214Ais connected to a tail node212via the first impedance220A. The tail node212is connected via a current source210to a voltage reference (power supply node) VL1whose voltage level is below that of VINP(and VINM). In particular, current source210supplies a constant DC current IDCto the sampler circuitry200. The current IDCmay be referred to as a bias current or as a sampler current in some examples. The input node214Ais connected to the mirror node218Avia the second impedance230A. The mirror circuitry265Acomprises a primary side250Aconnected between the mirror node218Aand the third impedance270A, and a secondary side260Aconnected between the load node216Aand the fourth impedance280A. The primary side250Ais connected to the primary reference node290Avia the third impedance270A. The secondary side260Ais connected to the secondary reference node292Avia the fourth impedance280A. The load circuitry240Ais connected to the load node216A.

The primary and secondary reference nodes290Aand292Aare connected to voltage references (power supply nodes). Here it is assumed that the references nodes (power supply nodes)290Aand292Aare connected to the same voltage reference (power supply node) VHwhich may be referred to as a high voltage reference. The load circuitry240A(or subsequent circuitry connected beyond the load circuitry240) will of course be connected to a voltage reference (power supply node) VL2whose voltage level is below that of the voltage reference (power supply node) VHand which may be referred to as a low voltage reference. Here it is assumed that the voltage references (power supply nodes) VL1and VL2are connected to the same voltage reference (power supply node) VLwhich may be referred to as the low voltage reference (e.g. GND), although different voltage levels for VL1and VL2could be provided.

The first section201can be described as comprising a primary current path2011connected between high and low voltage references VHand VL1and a secondary current path2012connected between high and low voltage references VHand VL2. The input node214A, the mirror node218A, the first impedance220A, the second impedance230A, the third impedance270A, and the primary side250Aof the current mirror circuitry265Aare connected along the primary current path2011. The fourth impedance280A, the secondary side260Aof the current mirror circuitry265A, the load node216Aand the load circuitry240Aare connected along the secondary current path2012. The primary current path2011is configured to carry a primary current dependent on the input voltage signal VINP. The current mirror circuitry265Ais connected to receive the primary current at its primary side250Aand to output a secondary current at its secondary side260A(that is, a secondary current dependent upon the primary current is caused to flow along the secondary current path2012). The tail node212and the current source210may be considered connected along the primary current path2011and the current source210configured to define a bias current flowing along that path. The input node214Amay be considered located along the primary current path2011so as to divide the primary current path into first and second portions, the first portion of the primary current path2011configured to carry the primary current, the primary side250Aof the current mirror circuitry265Aconnected along the first portion of the primary current path2011, and the first impedance220Aconnected along the second portion of the primary current path2011.

The second section202has a corresponding arrangement (with like elements denoted with a subscript B rather than a subscript A) as shown inFIG. 5, including an input node214Bto receive an input voltage signal VINM. A detailed description of the second section202is therefore omitted. Input voltage signals VINPand VINMare the “plus” and “minus” components of the (differential) input voltage signal.

Sampler circuitry200comprises load circuitry240. As shown inFIG. 5, load circuitry240corresponds closely to the load circuitry40inFIG. 4, and equivalent considerations apply. That is, the switches240A0to240AN-1and240B0to240BN-1, may be referred to as sampling switches or sampler switches; these sampling switches may be the sampling switches of a current-mode sampler corresponding to sampler42(in such a case the sampling switches240A0to240AN-1and240B0to240BN-1may be controlled by time-interleaved clock signals). The load circuitry240comprises the load circuitry240Aof the first section201and the load circuitry240Bof the second section202as shown inFIG. 5. The load circuitry240as depicted inFIG. 5is however an example and in general may comprise any current-mode circuitry.

Sampler circuitry200basically works in a similar way to the sampler circuitry100: by receiving the input voltage signal and by employing impedances to passively convert the received input voltage signal into an equivalent input current signal. For example, a current signal is received by the load circuitry240Aat the load node216A. The secondary current at least partly forms the current signal. In a differential implementation, for example, a differential current signal is received by the load circuitry at the load nodes216Aand216B(and the secondary currents output by the secondary sides260Aand260Bof the current mirror circuitry265Aand265B, respectively, at least partly form the differential current signal). In this regard, sampler circuitry200may be considered to comprise voltage-to-current conversion circuitry, with its output being the current signal received by the load circuitry240between or at the load nodes216Aand216B. Further, the sampler circuitry200may be referred to simply as circuitry or a circuitry system. In the following description it is assumed for convenience that the current signal received by the load circuitry240Ais the same as the secondary current (and this may be referred to as a load current), with an equivalent assumption holding for the second section202.

The first to fourth impedances220A,230A,270Aand280Aare shown inFIG. 5as comprising particular combinations of resistor, capacitor and/or inductor. However, as discussed above with regard to the first and second impedances20Aand30Aof sampler circuitry100, any component(s) giving rise to an impedance may be used to implement the first to fourth impedances220A,230A,270Aand280A. Further, the third and fourth impedances270Aand280Aare not essential. Equivalent considerations apply to the first to fourth impedances220B,230B,270Band280Bof the second section202.

The primary and secondary reference nodes290Aand292Aof the first section201and the primary and secondary reference nodes290Band292Bof the second section202as shown inFIG. 5are all connected to the same voltage reference (power supply node) VH(AVD). However, the reference nodes290A,292A,290Band292Bmay each be connected to voltage references (power supply nodes) different to or the same as any other reference node290A,292A,290Band292B.

As described above, sampler circuitry200can also be provided as single-ended circuitry operable based on a single-ended input voltage signal and operable to output a single-ended current signal (load current). That is, single-ended sampler circuitry may comprise the first section201, the current source210, the tail node212and load circuitry (e.g. the load circuitry240A), i.e. without the second section202. The following description of the operation of the sampler circuitry200will be understood to apply equally to a single-ended implementation.

A brief summary of the operation of sampler circuitry200is as follows, focusing on the first section201by way of example (a corresponding explanation applies for the second section202). Further, the following description is mainly focused on the differences between this first example arrangement200and sampler circuitry100shown inFIG. 4. The current generated with the second impedance230A(the primary current) is injected to the (advantageously wide swing) current mirror circuitry265Aat its primary side250A and is multiplied and copied and at its secondary side260A. In other words, the secondary current is caused to flow along the secondary current path2012. The gain of the secondary current compared to the primary current is defined as G. The maximum value of G is n/m, where n and m are the number of unit devices (transistors, such as field-effect transistors) on the secondary and primary sides260A and250A of the current mirror circuitry265A, respectively. On the primary side250A, transistor252Ais the diode connected device and transistor251A is the cascode for the primary side250A. On the secondary side260A, the transistor262Ais the mirror device and transistor261Ais the cascode for the secondary side260A.

Ignoring the third and fourth impedances270Aand280Aand the inductor255A, the devices251A,252A,261Aand262Aform a wide swing current mirror which mirrors the input-dependent current (the primary current) with the gain of G to form the secondary current. In the sampler circuitry200, both the DC and the AC amplitude of the primary current is multiplied with the same factor. This is appropriate for the example in which the load circuitry240comprises sampler switches constituting an ADC front-end where the output load is defined by the sub-ADC sampling capacitance. This ability to amplify the primary current solves the problem associated with the third disadvantage described above. That is, the amount of current at the load node216A can be increased without the need to increase the current generated at the current source210(i.e. the bias current IDC), and therefore the values of the first and second impedances220A,230A do not need to be changed to account for a change in the current loc. Thereby a larger secondary current is achieved with an advantageous S11 value and bandwidth.

The sampler circuitry200also solves the problem associated with the second disadvantage mentioned above. In particular, the splitting of the stacking into the primary and secondary current paths2011and2012(i.e. “folding”) solves this problem. As mentioned above, the primary current path2011comprises the input node214A, the mirror node218A, the first impedance220A, the second impedance230A, the third impedance270A, and the primary side250A of the current mirror circuitry265A, each connected therealong. For example with a 1.8 V supply voltage (i.e. AVD=1.8 V), this part of the sampler circuitry200(the primary current path2011) can be designed without any voltage headroom problem. This design relaxation is such that the bias current loc can be generated (by current source210) using a simple current mirror without the need for a DC control loop, for example. As mentioned above, the secondary current path2012comprises the fourth impedance280A, the secondary side260A of the current mirror circuitry265A, the load node216A and the load circuitry240A, each connected therealong. The secondary current path2012may also effectively comprise any subsequent circuitry connected beyond the load circuitry240A, for example (sub-) ADC circuitry. Importantly, the secondary current path2012need not (and does not) comprise elements of the primary current path2011such as the first impedance220A, the second impedance230A, and the current source210.

A mirror voltage signal Vpinput at the gate of transistor251A may be generated with a DC control loop circuit (not shown) and controls the transistor251A so that it is on the border of triode and saturation. This guarantees a high resolution operation of the current mirror circuitry265Aand therefore of the sampler circuitry200. The transistor261Ais controlled by the register295as shown inFIG. 5. The register295generates either a supply voltage (e.g. having the same value, AVD, as VH) or a defined bias voltage (which may also be generated by a control loop circuit, not shown inFIG. 5) for input at the gate of transistor261A. When the register295(depending on a value it stores) generates the supply voltage at the gate of transistor261A, the transistor261Ais OFF, and when the register295generates a bias voltage at the gate of transistor261A, the transistor261Ais ON (to a defined level). The amount of gain G of the current mirror circuitry265Avaries accordingly (assuming transistor261Ais implemented as a plurality of devices which can be controlled separately as mentioned below). Although not shown inFIG. 5, it will be understood that the voltages supplied from the register295to the transistors261Aand261Bcould be different from one another, i.e. optimised for the relevant circuit section201,202. The register295may be referred to as or form part of control circuitry. Control circuitry may comprise the register295as well as any DC control loops described above.

It will be appreciated that any of transistors251A252A,261Aand262Amay correspond to a plurality of transistors/devices. In particular, transistor261Amay correspond to a plurality of transistors/devices, in which case the register295controls individual transistors/devices as described above (i.e. generating a supply voltage or a bias voltage at the gates of individual transistors/devices to switch some or all of them OFF and some or all of them ON) in order to vary the gain G of the current mirror circuitry265A. This control of the gain G of the current mirror circuitry265Abrings programmability to the sampler circuitry200. With such programmability of the sampler circuitry200, programmability can be removed from (or simplified in) the current-mode circuitry being driven (i.e. the load circuitry), including any subsequent circuitry, for example, a (sub-) ADC. This enables the design of the current-mode circuitry being driven to be more compact and efficient, especially for higher resolution applications. Moreover, the amount of current at the load node216A (i.e. the magnitude of the secondary/load current) can be adjusted to compensate for loss due to parasitic capacitance and any other effects which might degrade the signal level supplied to, for example, a (sub-) ADC front-end (i.e. load circuitry240Aand subsequent circuitry). That is, calibration can be performed to tune out parasitic capacitances and other effects that reduce the magnitude of or otherwise degrade the secondary/load current.

The function of the first and second impedances220Aand230A(in particular the inductor222Aand the capacitor233A) is substantially the same as that of the first and second impedances20Aand30Adescribed above with reference toFIG. 4. A detailed description of the operation of the first and second impedances220Aand230Ais therefore omitted. In addition to the gain that can be added (in the sense of boosting the gain at high frequencies relative to at low frequencies) by the configuration of the first and second impedances220Aand230Aas shown inFIG. 5, more gain can be added (in the sense of high-frequency boosting) by using the configuration of the third and fourth impedances270Aand280Ashown inFIG. 5, and also by using the inductor255Ain the current mirror circuitry265A, as follows.

The inductor255Abetween the gates of transistors252Aand262A(and preferably using as the inductor255Aa fairly high-Q inductor with a small inductance) provides a mid-frequency resonance with the gate-source capacitance of the transistor262A. In other words, the inductor255A“tunes out” the gate-source capacitance of the transistor262A. This results in peaking in the secondary current, and also compensates for the low frequency operation of the current mirror circuitry265A. Thus the inductor255Aextends the bandwidth of the current mirror circuitry265A.

The inductor272Aconnected between the source of the transistor252Aand the primary reference node290A(and preferably using as the inductor272Aa medium-sized inductor (relatively speaking)) provides high frequency source degeneration which boosts the gate voltage of the transistor262A(and also the gate voltage of transistor252Asince the gates of transistors262Aand252Aare connected together via the inductor255A). This also provides some gain boosting at high frequency (i.e. boosting of the gain at high frequencies relative to at low frequencies) in the secondary current depending on the size of the inductor272A.

The resistors271Aand281Aconnected between the source of the transistor252Aand the primary reference node290A, and between the source of the transistor262Aand the secondary reference node292A, respectively (preferably small (high current) resistors), act as degeneration resistors. The resistor281Aon the secondary side2012is shunted with the capacitor283Aconnected in parallel with the resistor281A(preferably the capacitor283Ais a small capacitor, relatively speaking). At high frequency (of the input voltage signal VINP), the shunting capacitor283Aremoves the degeneration in the source of the transistor262Awhich in turn increases the gain of the current mirror circuitry265A. Preferably, the resistance values of the resistors271A and281Aare scaled so that the resistance value of the resistor281Ais smaller than the resistance value of the resistor271Aby a factor of G (the gain of the current mirror circuitry265A), for example to provide improved matching and to stabilise the gain. Using the resistors271Aand281Ato boost the gain (at high frequencies relative to at low frequencies) does consume some voltage headroom which could be noticeable, especially in the secondary current path2012. Further, when the sampler circuitry200is operated with a high current, low resistance value and high current resistors are required for the resistors271Aand281A—which can be difficult to implement in some practical arrangements.

For some implementations the resistors271Aand281Aare not employed. In other words, the inductors255Aand272Amay add sufficient gain to the current mirror circuitry265A. As mentioned above, the first to fourth impedances220A,230A,270Aand280Amay have configurations other than those depicted inFIG. 5, and the sampler circuitry200may not comprise the third and fourth impedances270Aand280A.

In terms of the S11 parameter, the inductor272Aincreases the impedance seen at high frequencies from the drain of the transistor251A. This increase compensates for the impedance decrease seen at high frequencies due to the shunting capacitor233A(the description of which is analogous to that of the shunting capacitor33A above), and therefore the inductor272Aprovides improved matching and thereby improves the S11 parameter. At the same time, due to source degeneration as described above, the inductor272Aincreases the gain boosting at high frequencies (i.e. boosting of the gain at high frequencies relative to at low frequencies). Therefore, the inductor272Acan improve both the gain profile and S11 parameter. This relaxes the above mentioned S11-gain trade-off (the first disadvantage described above of the sampler circuitry100). Moreover, in the sampler circuitry200the load circuitry240Ais connected to the secondary side260Aof the current mirror265A(along the secondary current path2012) which makes the S11 parameter independent of effects from the load circuitry240A(e.g. the gm(transconductance) of the sampling switches240A0to240AN-1. This relaxes the conditions for ensuring a good S11 parameter.

As described above, an advantage of the sampler circuitry200(compared to the sampler circuitry100) is the extra amount of gain. This additional gain improves the bandwidth of the sampler circuitry200, and the bandwidth can be brought towards the Nyquist rate at high ADC sample rates.

FIG. 6Ais a graph showing the peaking in the secondary/load current for an implementation of the sampler circuitry100(not folded) and for an implementation of the first example arrangement of sampler circuitry200(folded) for a 128 GSa/s ADC design example (i.e. with the load circuitry240configured as a sampler with a 128 GSa/s sample rate). As can be seen, more than 4 dB of gain is added into the signal path in the sampler circuitry200compared to the sampler circuitry100in these implementations.

FIG. 6Bis a graph showing the bandwidth of an implementation of the sampler circuitry100(not folded) and for an implementation of the first example arrangement of sampler circuitry200(folded) for the 128 GSa/s design example. It is apparent fromFIG. 6B(considering e.g. the −3 dB level) that the bandwidth of the sampler circuitry200is improved compared to that of the sampler circuitry100(it can be seen that the bandwidth is improved by at least 4 GHz for these example implementations).

The gain provided in the first example arrangement200allows the input voltage level to be reduced (whilst achieving the same output level) compared to the sampler circuitry100. This reduces the amount of harmonics injected ultimately into the current signal that is to be provided to the load circuitry240(i.e. the secondary/load current) which in turn improves the effective resolution of the sampler circuitry200(in particular of the sampler implemented by way of the load circuitry240). This is appropriate for low speed (low bandwidth) applications where a higher effective number of bits (ENOB) is normally required.

FIG. 7Ais a graph showing the ENOB of an implementation of the sampler circuitry100(not folded) and of an implementation of the first example arrangement of sampler circuitry200(folded) in a 56 GSa/s ADC design example in which the output is kept at −3 dBFS (3 dB lower than full scale). As can be seen inFIG. 7A, the first example arrangement200provides an improved ENOB compared to the sampler circuitry100across a wide range of input frequencies. In particular, at low (lower) input frequencies, the ENOB provided by the first example arrangement200is around 2.5 bits higher than the ENOB provided by the sampler circuitry100for these example implementations. In this implementation of the first example arrangement200, the gain of the current mirror circuitry265Ais set to G=2.5 dB.

FIG. 7Bis a graph showing the ENOB of an implementation of the sampler circuitry100(not folded) and of an implementation of the first example arrangement of sampler circuitry200(folded) in a 56 GSa/s ADC design example in which the output is kept at −1 dBFS (1 dB lower than full scale). In this implementation of the first example arrangement200, the gain of the current mirror circuitry265Ais set to G=6 dB. As can be seen inFIG. 7B, the ENOB improvement provided by the example arrangement200compared to the sampler circuitry100is better than that provided by the example arrangement200as implemented forFIG. 7A, due to the higher gain G of the current mirror circuitry265A. In this implementation of the first example arrangement200, at low (lower) frequencies, the ENOB provided is enhanced by around 4 bits compared to the ENOB provided by the sampler circuitry100.

FIG. 8is a graph showing the current output signal level of an implementation of the first example arrangement of sampler circuitry200in a 56 GSa/s ADC design example in which (as an extreme example to illustrate the ENOB enhancement) the gain of the current mirror circuitry265Ais increased to G=9.5 dB. This allows the input signal level VINP/Mto be reduced by more than 9 dB. As can be seen inFIG. 8, this practically pushes the harmonics (i.e., mainly the third harmonic) lower than the clock spurs (shown at fs/4+fin, fs/4−fin and fs/2−fin, where fs is the sampling frequency and fin is the frequency of the input signal, and the Nyquist frequency fs/2=28 GHz). This corresponds to a sampler design with no or negligible harmonic distortion.

In summary, some of the advantages of the first example arrangement200(which may be referred to as an ultra high frequency, programmable equalizer, folded structure with high linearity) compared to, for example, the sampler circuitry100are as follows.Gain enhancement. The current mirror circuitry265Acan provide gain. Also, other components (e.g. impedances) can provide gain boosting at high frequencies without affecting the S11 parameter due to solving the problem of trade-off between gain and S11 by using the primary and secondary current paths2011and2012.Improved linearity. Due to the improved gain the input voltage level VINP/Mcan be reduced whilst still achieving a sufficient output current signal level, so that there is less distortion in the output signal level. Therefore the linearity in the secondary/load current and therefore in the current signal input to load circuitry240Ais improved.Programmability. The current mirror circuitry265Acan be controlled as described above in order to adjust the gain G. This adjustment can be used to compensate for loss due to parasitic capacitance and any other effects which might degrade the output signal level.Sample frequency tuning. Due to the programmability of the current mirror circuitry265A, the gain G of the current mirror circuitry265Acan be adjusted according to the sample frequency. Considering an example in which the load circuitry corresponds to sampling switches of a sub-ADC, without this programmability the capacitance value of the sub-ADC sampling capacitor would need to be adjusted according to the sample frequency (higher sample frequencies mean lower integration time and so a lower capacitance value of the sub-ADC sampling capacitor would be required, e.g. to achieve the same input voltage swing). However due to the programmability of the gain G of the current mirror circuitry265A, the capacitance value of the sub-ADC sampling capacitor (considering an example in which the load circuitry corresponds to sampling switches of a sub-ADC) can be fixed and instead the gain of the current mirror circuitry265Acan be adjusted according to the sample frequency.Bandwidth extension. The bandwidth can be extended due to the improved gain profile (i.e. the added gain, and the boosting of gain at high frequencies relative to at low frequencies) and due to the improved S11 parameter.Decoupling of S11 performance from the load circuitry240. Due to the “folding” of the first example arrangement (i.e. the current mirror circuitry265A, giving rise to the first and second current paths2011and2012), the S11 parameter is not affected by the load circuitry240Aand subsequent circuitry which is connected along the secondary current path (2012). This relaxes the conditions for ensuring a good S11 parameter.

FIG. 9is a schematic diagram of a second example arrangement300of sampler circuitry.

Sampler circuitry300is differential circuitry operable based on a differential input voltage signal. Sampler circuitry300comprises control circuitry395and two matching (or corresponding or complementary) sections301and302for the two differential inputs, similar to the circuitry100.

The first section301comprises an input node314A, an intermediate node316A, a tail node312A, an input-connection impedance330A, a supply-connection impedance320A, a measurement impedance350Aand load circuitry340A. The intermediate node316A as shown inFIG. 9may be referred to as a load node.

The input node314Ais configured to receive an input voltage signal VINPvia a terminal315A. The input node314Aand the terminal315Aas shown inFIG. 9are provided separately but they could be the same as one another. The intermediate node316A is connected to the tail node312Avia the supply-connection impedance320A. The input node314Ais connected to the intermediate node316A via the input-connection impedance330A. The intermediate node316A is connected to a measurement node318via the measurement impedance350A.

The input-connection, supply-connection, and measurement impedances330A,320Aand350Aare shown inFIG. 9as comprising particular combinations of resistor, capacitor and/or inductor. Similarly as discussed above with regard to the sampler circuitry100and200, any component(s) giving rise to an impedance may be used to implement the impedances320A,330Aand350A. In particular, the input-connection impedance330Amay comprise a capacitor (not shown) connected in parallel with the resistor.

The second section302has a corresponding arrangement as shown inFIG. 9, the measurement node318being shared between the first and second sections301and302. A detailed description of the second section302is therefore omitted. Input voltage signals VINPand VINMare the “plus” and “minus” components of the (differential) input voltage signal.

The nodes314A,316Aand312A, the impedances320A,330Aand350A, and the load circuitry340Aof the first section301may be labelled with the prefix “first” and nodes314B,316Band312B, impedances320B,330Band350B, and load circuitry340Bof the second section302may be labelled with the prefix “second” to distinguish elements of the first and second sections301and302from each other. The first and second tail nodes312Aand312Bmay be connected to the same voltage reference or power supply node VH(e.g. AVD as shown inFIG. 9) and thereby may be referred to together as a tail node312. First and second load circuitry340Aand340Bmay be referred together as load circuitry340. Load circuitry340comprises a biasing node342. The load circuitry340(or subsequent circuitry connected beyond the load circuitry340) will of course be connected to a voltage reference (power supply node) VL whose voltage level is below that of the voltage reference (power supply node) VH. The voltage reference (power supply node) VHmay be referred to as a high voltage reference and the voltage reference (power supply node) VLmay be referred as a low voltage reference, and the potential difference between VHand VLmay be referred to as the supply voltage.

The first section301can be described as comprising a first current path300Aextending from the tail node312via the first intermediate node316Ato a first load node (which as shown inFIG. 9is the same as the first intermediate node316Abut may be provided separately from the first intermediate node316A) to provide a first load current at the first intermediate (or load) node316Afor use by the load circuitry340, wherein the first supply-connection impedance320Ais connected along the first current path300Abetween the tail node312and the first intermediate node316A.

The second section302can be described as comprising a second current path300Bextending from the tail node312via the second intermediate node316Bto a second load node (which as shown inFIG. 9is the same as the second intermediate node316Bbut may well be provided separately from the second intermediate node316B) to provide a second load current at the second intermediate (or load) node316Bfor use by the load circuitry340, wherein the second supply-connection impedance320Bis connected along the second current path300Bbetween the tail node312and the second intermediate node316B. The first and second load currents define a differential current signal upon which the load circuitry340is configured to operate. The first and second input nodes314Aand314Bare connected to the first and second intermediate nodes316Aand316Bvia the first and second input-connection impedances330Aand330B, respectively, so that the differential current signal is dependent on the differential input voltage signal. The first and second load currents comprise respective DC bias current components (defined by the first and second supply-connection impedances320Aand320B, respectively, the voltage level of the voltage reference (power supply node) VH, and a common-mode voltage indicative of a common mode between voltages at the first and second intermediate nodes316Aand316B), and also respective AC current components dependent on the differential input voltage signal (VINPand VINM).

The control circuitry395is configured, based on measurement of the common mode voltage indicative of the common mode between voltages at the first and second intermediate nodes316Aand316B, to control a biasing signal SBprovided to the biasing node342of the load circuitry340to regulate the common mode voltage. Effectively, the biasing signal S biases (regulates) operation (e.g. an operating point) of the load circuitry340which in turn affects (regulates) the common mode voltage. A common mode control loop is thus implemented. Thereby, the DC bias current components of the first and second load currents are regulated, respectively. The control circuitry395may comprise the first and second measurement impedances350Aand350B.

The load circuitry340as shown inFIG. 9corresponds closely to the load circuitry40inFIG. 4and the load circuitry240inFIG. 5, and equivalent considerations apply. That is, the switches340A0to340AN-1and340B0to340BN-1may be referred to as sampling switches or sampler switches; these sampling switches may be the sampling switches of a current-mode sampler corresponding to sampler42(in such a case the sampling switches340A0to340AN-1and340B0to340BN-1may be controlled by time-interleaved clock signals). The load circuitry340of the sampler circuitry300may comprise any current-mode circuitry capable of receiving a biasing signal (e.g. the biasing signal S). The load circuitry340comprises the load circuitry340Aof the first section301and the load circuitry340Bof the second section302as shown inFIG. 9.

Sampler circuitry300basically works in a similar way to the sampler circuitry100and200: by receiving the (differential) input voltage signal and by employing impedances to passively convert the received input voltage signal into an equivalent input current signal. For example, the input current signal is received by the load circuitry340between the load nodes316Aand316B(and the input current signal may be referred to as a load current or as a differential current signal). In this regard, sampler circuitry300may be considered to comprise voltage-to-current conversion circuitry, its output being the current signal received by the load circuitry340between the load nodes316Aand316B(the load current). Further, the sampler circuitry300may be referred to simply as circuitry or a circuitry system (for example, where the load circuitry340is current-mode circuitry other than sampler circuitry).

To describe in further detail the operation of the second example arrangement300, reference is first made back to the sampler circuitry100ofFIG. 4. In the following description, the shunting capacitors33A and33B ofFIG. 4are ignored for simplicity.

The current at the input node14Adue to the input voltage signal VINPmay be referred to as IINP. Considering the first section101of the sampler circuitry100(with the understanding that the sampler circuitry100may be single-ended or differential and in the case of differential sampler circuitry100equivalent analysis applies to the second section102), the proportion of the current IINPthrough the first and second impedances20Aand30Acan be adjusted by appropriate selection of the first and second impedances20Aand30A(in particular of the resistors21Aand31A). It is possible to select these impedances (resistors) for each application but difficult to make them switchable without affecting the bandwidth of the sampler circuitry100and parasitic capacitance (particularly at the input node). For the purpose of the following description it is assumed that the sampler circuitry100connects to the input of sub-ADC units (i.e. that the load circuitry40is a front-end sampler whose transistors serve as sampler switches which provide current pulse samples to sub-ADC units). It will be appreciated that a similar analysis could be applied for any current-mode circuit.

At low frequency of the (differential) input voltage signal, the portion I2Lof the current IINPthat flows towards the sampler switches (i.e. the input-dependent current at low frequency) can be calculated/approximated as (Equation 1):
I2L=(R2/(R2+R1+1/gm))×IINP
where R1and R2are the resistance values of the resistors31Aand21A, respectively, and gmis the transconductance of the sampler switches.

At high frequency of the (differential) input voltage signal, ignoring the frequency response of the sampler switches, the portion I2Hof the current IINPthat flows towards the sampler switches (i.e. the input-dependent current at high frequency) can be calculated/approximated as (Equation 2):
I2H=((R2+L1×ω)/(R2+L1×ω+R1+1/gm))×IINP
where L1is the inductance value of the inductor22Aand ω=2πfin, where fin is the input frequency, i.e. of the input voltage signal VINP.

Assuming that at sufficiently high input frequencies (ω=2πfin), L1is large enough such that (Equation 3):
R2+L1×ω>>R1+1/gm,
then Equation 2 can be approximated as follows (Equation 4):
I2H˜IINP

The amount of high frequency gain achievable (i.e. the input-dependent current at high frequency compared to the input-dependent current at low frequency), taking into account the approximation (Equation 3) is Equation 4 divided by Equation 1. Therefore the amount of high frequency gain achievable GMAXis (Equation 5):
GMAX=1+R1/R2+1/gmR2

Equation 5 shows the maximum gain achievable (i.e. the input-dependent current at high frequency compared to at low frequency) with the sampler circuitry100. In practice the amount of gain achievable is limited by the desire for a good S11 parameter. A similar analysis can be carried out for S11 parameter calculation as follows. At low frequencies, the impedance ZINL(L for low frequency) seen looking into the input node14Afrom the input terminal15Acan be calculated/approximated as (Equation 6):
ZINL=(R1+1/gm)∥R2=Z0
where ∥ means in parallel with, and where Z0(ohms) is the characteristic impedance of the system, such as an RF system, to be connected at the input (e.g. 50 ohm). At high frequencies, using the approximation of Equation 3, the impedance ZINH(H for high frequency) seen looking into the input node14Afrom the input terminal15A can be calculated/approximated as (Equation 7):
ZINH=(R1+1/gm)∥(R2+L1×ω)˜(R1+1/gm)

Using Equation 6 in Equation 7, the high frequency impedance ZINHcan be calculated/approximated as (Equation 8):
ZINH=Z0×R2/(R2−Z0)

Therefore the reflection coefficient (S11 parameter) can be calculated as (Equation 9):
S11=(ZINH−Z0)/(ZINH+Z0)=Z0/(2R2−Z0)

As an example, R1=50Ω, R2=100Ω and 1/gm=50Ω. In this case, the maximum AC gain (i.e. amount of high frequency gain achievable) according to Equation 5 is (Equation 10):
GMAX=1+50/100+50/100=2˜6 dB
(for completeness, in Equation 10, GMAX=2 is unit-less; in logarithmic scale it corresponds to 20*log10(2) which is ˜6 dB). Further, the S11 parameter (in decibels) in this case can be calculated according to Equation 9 as (Equation 11):
S11=20×log(50/(200−50))=−9.5 dB

Reference is now made again to the second example arrangement300shown inFIG. 9.

Operation of sampler circuitry300will now be described, focusing sometimes on only the first section301with the understanding that corresponding considerations apply for the second section302. Comparing the sampler circuitry300to the sampler circuitry100, it is apparent that (among other differences) the current source10(which generates the sampler or bias current IDC) is absent from the sampler circuitry300, whereas it is present in the sampler circuitry100. Another difference is that in the sampler circuitry300the input-connection impedance330A(which can be considered to correspond with the second impedance30Aof the sampler circuitry100) is outside of the first current path300A(in other words, outside the stack, the stack meaning the stack of elements along the first current path300A), whereas in the sampler circuitry100the second impedance30Ais connected along a current path from the tail node12to the load node16A(in other words, within the stack, the stack meaning the stack of elements along the current path from VH(AVD) via the tail node12to the load node16A).

The first and second measurement impedances350Aand350Bare used to sense the common mode voltage indicative of the common mode between voltages at the first and second intermediate nodes316Aand316B. The first and second measurement impedances350Aand350Bare shown inFIG. 9as resistors by way of example but may be implemented as complex impedances. Preferably, the first and second measurement impedances350Aand350Bare large (relatively speaking) resistors (i.e. resistors having a large resistance value).

The control circuitry395receives a measurement signal SCMindicative of the common mode voltage from the measurement node318. The control circuitry395controls the biasing signal SBwhich is provided to the biasing node342in order to regulate the common mode voltage. That is, the control circuitry395controls the biasing signal Se to bring the measurement signal SCMto or towards a target value corresponding to a target common mode voltage. Thereby, the control circuitry395controls or regulates (i.e. brings to or towards a target value) the DC bias current components of the first and second load currents, respectively, because the DC voltage drops over the impedances320Aand320Bare then controlled/regulated. The control circuitry395may thus be considered the control element of a common mode control loop.

The load circuitry340shown inFIG. 9comprises switches340A0to340AN-1and340B0to340BN-1equivalent to the corresponding switches shown inFIGS. 4 and 5. The switches340A0to340BN-1are shown inFIG. 9as switching transistors, and may also be referred to as sampling switches or sampler switches. As described above, the load circuitry340may however in general be any current-mode circuitry.

In an example in which the load circuitry340comprises the switches340A0to340AN-1and340B0to340BN-1, the biasing signal Se may control the DC level of gate-control switching signals provided to gate terminals to the switching transistors340A0to340BN-1. For example, the biasing signal may comprise one or more individual signals for one or more switching transistors340A0to340BN-1.

In the following description of the operation of sampler circuitry300, it is assumed that the load circuitry340is as shown inFIG. 9and that the biasing signal Se controls the DC level of gate-control switching signals provided to gate terminals of the switching transistors340A0to340BN-1. In other words, a feedback loop is used to set the DC voltage of the gates of the sampler switches such that a DC component of the current which flows through the first and second supply-connection impedances320Aand320Bis constant or regulated over PVT (process, voltage, temperature). In this case (and considering the first current path300A), the control circuitry395controls the biasing signal Se so that the common mode voltage VCMsatisfies the following (Equation 12):
AVD=VCM+R2×ISAMP/2
where AVD is the voltage reference VH, R2is the resistance value of the impedance320A, ISAMPis the desired current drawn from AVD by the sampler circuitry300(corresponding to IDCinFIG. 4), and the impedances320Aand320are the same as one another.

Comparing the sampler circuitry300to the sampler circuitry100, an amount of additional voltage headroom of the sampler circuitry300can be determined by calculating the voltage headroom used up by the second impedance30Aand the current source10in the sampler circuitry100(because the current source10is not required in the sampler circuitry300and because the second impedance30Acorresponds to the input-connection impedance330Awhich is not in the stack).

This additional voltage headroom AAVD can be calculated as (Equation 13):
ΔAVD=R1×ISAMP/2+VOD,SAMP
where VOD,SAMPis the overdrive voltage of the current source10and R1×ISAMP/2 is the voltage drop across the second impedance30Aof the sampler circuitry100.

Due to this additional voltage headroom of the sampler circuitry300compared to the sampler circuitry100, the supply voltage can be reduced (i.e. the difference between the high and low voltage references reduced). That is, ΔAVD may be considered an amount of supply voltage drop achievable using the sampler circuitry300compared to the sampler circuitry100.

Continuing the example assuming that the load circuitry340comprises the sampling switches as shown inFIG. 9, at low frequencies (L for low frequency) the current I2Lsampled by the sampler switches (the input-dependent current) from the first current path300Acan be calculated as (Equation 14):
I2L=(R2/(R2+1/gm))×IINP
where IINPis the current drawn in at the input node314A, R2is again the resistance value of the impedance320A, and gmis the transconductance of the sampler switches. At high frequencies the current I2H(H for high frequency) sampled by the sampler switches (the input-dependent current) from the first current path300Acan be calculated as (Equation 15):
I2H=((R2+L1×ω)/(R2+L1×ω+1/gm))×IINP
where L1is the inductance value of the supply-connection impedance320Aand ω=2πfin, where fin is the input frequency, i.e. of the input voltage signal VINP. Assuming that (Equation 16):
R2+L1×ω>>1/gm
then Equation 15 can be approximated as follows (Equation 17):
I2H˜IINP

Similar to Equation 5 above, the amount of high frequency gain achievable (i.e. the input-dependent current at high frequency compared to the input-dependent current at low frequency) of sampler circuitry300can be calculated/approximated by dividing Equation 17 by Equation 14. Therefore the amount of high frequency gain achievable GMAXis (Equation 18):
GMAX=1+1/gmR2

Similar to Equations 6 to 9 above, the reflection coefficient (S11 parameter) can be calculated as follows. At low frequencies, the impedance ZNLseen looking into the input node314Afrom the input terminal315Acan be calculated/approximated as (Equation 19):
ZINL=R1+1/gm∥R2=Z0
where R1is the resistance value of the input-connection impedance330A. At high frequencies, the impedance ZINH(H for high frequency) seen looking into the input node314Afrom the input terminal315Acan be calculated/approximated as (Equation 20):
ZINH=R1+1/gm∥(R2+L1×ω)(R1+1/gm)

Using Equation 19 in Equation 20, the high frequency impedance ZINHcan be calculated/approximated as (Equation 21):
ZINH=Z0+(1/gm)/(1+gm×R2)

Therefore the reflection coefficient (S11 parameter) can be calculated as (Equation 22):
S11=1/(1+2gm×Z0×(1+gm×R2))

A comparison can now be made between the sampler circuitry100and the sampler circuitry300.

Both sampler circuitry100and sampler circuitry300provide similar high frequency gain. As an example, R1=25Ω, R2=50Ω and 1/gm=50Ω. In this case, the maximum AC gain (i.e. amount of high frequency gain achievable) according to Equation 18 is (Equation 23):
GMAX=1+50/50=2˜6 dB

This is similar to the gain GMAXcalculated for the sampler circuitry100.

The S11 parameter (in dB) for the sampler circuitry300can be calculated using Equation 22 as (Equation 24):
S11=1/(1+(2/50)×50×(1+50/50))=1/5˜−14 dB

Comparing the gain and the S11 parameter for the above examples (i.e. Equations 10, 11, 23 and 24), it is apparent that the sampler circuitry300can provide a similar gain compared to the sampler circuitry100whilst providing improved S11 performance (S11 scattering parameter value).

Due to the additional voltage headroom of the sampler circuitry300compared to the sampler circuitry100, the supply voltage can be lowered (i.e. the difference between the high and low voltage references VHand VLcan be reduced) which is advantageous from a power-saving point of view. Another advantage is that the additional voltage headroom can be used in the load circuitry and/or subsequent circuitry.

FIG. 10is a schematic diagram of a modified second example arrangement400of sampler circuitry.

Sampler circuitry400comprises first and second matching (or corresponding or complementary) sections401and402for the two differential inputs, the first and second sections401and402corresponding closely with the first and second sections301and302of sampler circuitry300. Each element of the sampler circuitry400in common with sampler circuitry300has the same reference numeral as the corresponding element of the sampler circuitry300. The principle of operation of the sampler circuitry400is substantially the same as that of the sampler circuitry300and duplicate description of elements common to sampler circuitry300and sampler circuitry400is omitted.

The sampler circuitry400additionally comprises an auxiliary current path403connected between the first and second input nodes314Aand314B, and having an auxiliary impedance370connected therealong. The auxiliary impedance370as shown inFIG. 10comprises two resistors371and375and two inductors372and374. In brief, the auxiliary current path403provides an additional AC signal path for the input current and consequently, another gain factor (i.e. gain boosting at high frequencies, relative to at low frequencies) at frequencies when the inductors372and374begin to dominate. The auxiliary impedance370can of course have other arrangements comprising any element(s) giving rise to an impedance, for example a single resistor and a single inductor.

Similar calculations as for the sampler circuitry300can be applied to the sampler circuitry400as follows, focusing on the first section401with the understanding that equivalent analysis can be carried out for the second section402. At low frequencies (of the input voltage signal VNP) the current I2Lsampled by the sampler switches (the input-dependent current) from the first current path300A, and including a contribution from the auxiliary current path403, can be calculated as (Equation 25):
I2L=(R3/(R3+R1+R2|(1/gm))×(R2/(R2+1/gm))×IINP
where R3is the resistance value of the auxiliary impedance370Aand the other quantities are as described with reference to the sampler circuitry300. At high frequency, the inductance values of the supply-connection impedance330Aand of the auxiliary impedance370Abecome large and (substantially) all the input current IINPgoes into the sampler switches. Therefore at high frequency the current I2Hsampled by the sampler switches (the input-dependent current) from the first current path300A, and including a contribution from the auxiliary current path403, can be calculated as (Equation 26):
I2H˜IINP

The amount of high frequency gain achievable or AC gain (i.e. the input-dependent current at high frequency compared to the input-dependent current at low frequency) is Equation 26 divided by Equation 25. Therefore the amount of high frequency gain achievable GMAXis (Equation 27):
GMAX=(1+R1/R3+(R2∥1/gm)/R3)×(1+1/gmR2)

Comparing the amount of high frequency gain achievable (or AC gain) for the sampler circuitry400to that for the sampler circuitry300(i.e. comparing equations 18 and 27), it is apparent that the amount of extra gain achieved due to the auxiliary current path403is (Equation 28):
Gboost=1+R1/R3+(R2∥1/gm)/R3

As an example for the sampler circuitry400, R1=50Ω, R2=50Ω, R3=15Ω and 1/gm=50Ω. According to Equation 28, the extra gain of the sampler circuitry400compared to the sampler circuitry300is (Equation 29):
Gboost=(1+50/150+(50∥50)/150)=1.5˜3.5 dB

Referring to Equation 23, this means that the total amount of high frequency gain achievable (i.e. the input-dependent current at high frequency compared to the input-dependent current at low frequency) for the sampler circuitry400is approximately (Equation 30):
GMAX=6 dB+3.5 dB=9.5 dB

Therefore, the sampler circuitry400provides a very large gain with which, when the load circuitry340is for example a front-end of a (sub-) ADC, near Nyquist rate bandwidth ADC operation can be achieved.

Continuing the analysis of the sampler circuitry400, at high frequency the inductance values of the inductors332Aand372(and374) become very large so that the impedance ZINHseen looking into the input node314Afrom the input terminal315Acan be calculated/approximated as (Equation 31):
ZINH˜(R1+1/gm)

It is apparent that this high frequency impedance is similar to the high frequency impedance for the sampler circuitry100calculated in Equation 7. Using the example parameter values above, the S11 parameter (reflection coefficient) can be calculated (using Equation 9) as (Equation 32):
S11=(100−50)/(100+50)=1/3˜−9.5 dB

This value for the S11 parameter is similar to the S11 parameter for the sampler circuitry100(Equation 11). Therefore the sampler circuitry400can operate with much higher AC gain (i.e. the amount of high frequency gain achievable GMAX, Equation 30) than the sampler circuitry100but with similar S11 performance (i.e. Equation 32), whilst there is the additional advantage that the supply voltage (i.e. the difference between the high and low voltage references) can be dropped compared to the sampler circuitry100for example by the amount calculated in (13).

To demonstrate the advantages associated with the second example arrangement300and the modified second example arrangement400, circuitry has been designed (in particular a 77 GSa/s sampler) and simulated using the sampler circuitry100, the second example arrangement300and the modified second example arrangement400.

FIG. 11Ais a graph showing the signal level of the reconstructed signal at the output of the designed and simulated 77 GSa/s sampler with respect to the input signal (VINP/M) frequency for the sampler circuitry100(without control), the second example arrangement300(with control) and the modified second example arrangement400(with control (boosted)). Also marked on the graph inFIG. 11Ais the frequency at 0.3 fs bandwidth, which is a useful example frequency to consider (for example, in current-mode ADCs such as disclosed in EP2211468, a “sinc effect” due to the integration of charge/current can theoretically limit the bandwidth of the system to a value more than 0.3 fs but less than the Nyquist bandwidth), and the Nyquist bandwidth. It is apparent fromFIG. 11Athat the second example arrangement300provides improved bandwidth compared to the sampler circuitry100and that the modified second example arrangement400provides improved bandwidth compared to the sampler circuitry100and to the second example arrangement300. In the simulation on which the graph inFIG. 11Ais based, the sampler circuitry100was implemented with a 1.8 V supply voltage (i.e. difference between high and low reference voltages) while the second example arrangement300and the modified second example arrangement400were implemented with a 1.5 V supply voltage, demonstrating the advantage of supply voltage reduction. The second example arrangement300and the modified second example arrangement400can work with supply voltages less than 1.5 V.

FIG. 11Bis a graph showing the S11 parameter value profile of the designed and simulated 77 GSa/s sampler for the sampler circuitry100(without control), the second example arrangement300(with control) and the modified second example arrangement400(with control (boosted)). Also marked on the graph inFIG. 11Bwith a dotted line is an example S11 specification. In the simulation on which the graph inFIG. 11Bis based, the sampler circuitry100was implemented with a 1.8 V supply voltage (i.e. difference between high and low reference voltages) while the second example arrangement300and the modified second example arrangement400were implemented with a 1.5 V supply voltage, demonstrating the advantage of supply voltage reduction. The second example arrangement300and the modified second example arrangement400can work with supply voltages less than 1.5 V.

It is apparent fromFIG. 11Bthat the second example arrangement300provides the best S11 performance while the modified second example arrangement400provides similar S11 performance to the sampler circuitry100as predicted in Equation 32, but the modified second example arrangement400provides more gain compared to the sampler circuitry100and to the second example arrangement300.

In summary, some of the advantages of the second example arrangement300and the modified second example arrangement400(both of which may be referred to as a low voltage, gain boosted current mode sampler) compared to, for example, the sampler circuitry100are as follows.Removal of current source (i.e. current source10in sampler circuitry100) from the stack. The current source (as a separate element) is not required in either of the first and second current paths300Aand300B. This results in additional voltage headroom. The removal of the current source from the stack is advantageous from a power-saving point of view.Removal of matching network from stack. That is, the input-connection impedances330Aand330Bare outside the first and second current paths300Aand300B, respectively. This results in improved S11 performance, relaxed requirements concerning ensuring good S11 performance, and improved voltage headroom.Reduction in supply voltage. Due to the additional voltage headroom, the supply voltage can be reduced. This is advantageous from a power-saving point of view.Improved S11 (input matching) performance. The S11 performance of the sampler circuitry300and400is better than (or at least as good as) the S11 performance of the sampler circuitry100, whilst at the same time a better gain “profile” and improved voltage headroom can be provided by the sampler circuitry300and400.Addition of gain (high frequency compared to low frequency) into the signal path without affecting the S11 parameter, in the sense of (relative) boosting at high frequencies (i.e. sacrificing gain at low frequencies so that it appears better at high frequencies—i.e. to affect the gain profile but without adding overall DC to high frequency gain, such as active-device gain). As described above, sampler circuitry300provides improved gain (high frequency gain boosting) compared to the sampler circuitry100and the sampler circuitry400provides improved gain (high frequency gain boosting) compared to the sampler circuitry100and300. At the same time, the sampler circuitry300and400can provide improved (or at least as good) S11 performance and also improved voltage headroom.Bandwidth extension. The bandwidth can be extended due to the improved gain “profile” and due to the improved S11 parameter.

Sampler circuitry100,200,300and400are shown in the Figures as comprising P-channel devices (in this case, field-effect transistors). N-channel devices may also be used in place of P-channel devices, i.e. by providing the circuitry the “other way up”.

It will be appreciated that sampler circuitry200,300,400could be provided along with mixed-signal circuitry such as ADC circuitry (or, in some arrangements, DAC circuitry). As illustrated inFIG. 12A, for example, sampler circuitry200,300,400disclosed herein could be provided along with or as part of ADC circuitry1.

Circuitry of the present invention may be implemented as integrated circuitry, for example on an IC chip such as a flip chip.FIG. 12Bis a schematic diagram of an integrated circuit2comprising the ADC circuitry1. An integrated circuit comprising the sampler circuitry200,300and/or400could also be provided.

The present invention extends to integrated circuitry and IC chips as mentioned above, circuit boards comprising such IC chips, and communication networks (for example, internet fiber-optic networks and wireless networks) and network equipment of such networks, comprising such circuit boards. Circuitry of the present invention may also be implemented with discrete components provided on circuit boards. Circuitry of the present invention may be implemented alone (as a standalone circuit) or together with other circuitry.

In any of the above method aspects (for example, control of values stored in the register295or control of the control unit395), the various features as appropriate may be implemented in hardware, or as software modules running on one or more processors. Features of one aspect may be applied to any of the other aspects.

The invention also provides a computer program or a computer program product for carrying out any of the methods described herein, and a computer readable medium having stored thereon a program for carrying out any of the methods described herein. A computer program embodying the invention may be stored on a computer-readable medium, or it could, for example, be in the form of a signal such as a downloadable data signal provided from an Internet website, or it could be in any other form.

Further embodiments may be provided within the spirit and scope of the present invention as disclosed herein.