Random code generator with antifuse differential cell and associated sensing method

A random code generator includes a memory cell array and a sensing circuit. The memory cell array includes plural antifuse differential cells. The sensing circuit has an input terminal and an inverted input terminal. When a first antifuse differential cell of the memory cell array is a selected cell, a bit line of the selected cell is connected with the input terminal of the sensing circuit and an inverted bit line of the selected cell is connected with the inverted input terminal of the sensing circuit. During a read cycle, the sensing circuit judges a storage state of the selected cell according to a first charging current of the bit line and a second charging current of the inverted bit line, and determines a bit of a random code according to the storage state of the selected cell.

FIELD OF THE INVENTION

The present invention relates to a random code generator and an associated sensing method, and more particularly to a random code generator with an antifuse differential cell and an associated sensing method.

BACKGROUND OF THE INVENTION

As is well known, an antifuse cell is one kind of one time programmable cell (also referred as an OTP cell). The antifuse cell comprises an antifuse transistor. If the voltage difference between the gate terminal and the source/drain terminal of the antifuse transistor is not higher than the withstanding voltage, the antifuse transistor is in a high-resistance state. Whereas, if the voltage difference between the gate terminal and the source/drain terminal of the antifuse transistor is higher than the withstanding voltage, the gate oxide layer of the antifuse transistor is ruptured and the antifuse transistor is in a low-resistance state.

Moreover, U.S. Pat. No. 9,613,714 disclosed an OTP cell that is able to generate a random code.FIG. 1Ais a schematic equivalent circuit diagram illustrating a conventional antifuse differential cell for generating a random code.FIG. 1Bis a bias voltage table illustrating the bias voltages for programming and reading the conventional antifuse differential cell ofFIG. 1A.

As shown inFIG. 1A, the antifuse differential cell c1comprises a first select transistor S1, a first antifuse transistor A1, an isolation transistor O, a second antifuse transistor A2and a second select transistor S2, which are serially connected between a bit line BL and an inverted bit line BLB. The gate terminal of the first select transistor S1is connected with a word line WL. The gate terminal of the first antifuse transistor A1is connected with a first antifuse control line AF1. The gate terminal of the isolation transistor O is connected with an isolation control line IG. The gate terminal of the second antifuse transistor A2is connected with a second antifuse control line AF2. The gate terminal of the second select transistor S2is connected with the word line WL.

Please refer toFIG. 1B. During a program cycle, a ground voltage (0V) is provided to the bit line BL and the inverted bit line BLB, a select voltage Vdd is provided to the word line WL, a program voltage Vpp is provided to the first antifuse control line AF1and the second antifuse control line AF2, and an on voltage Von is provided to the isolation control line IG.

During the program cycle, all of the first select transistor S1, the second select transistor S2and the isolation transistor O are turned on and the state of one of the first antifuse transistor A1and the second antifuse transistor A2is changed. For example, the first antifuse transistor A1is changed to the low-resistance state, but the second antifuse transistor A2is maintained in the high-resistance state. Alternatively, the second antifuse transistor A2is changed to the low-resistance state, but the first antifuse transistor A1is maintained in the high-resistance state.

During a read cycle, the ground voltage (0V) is provided to the bit line BL and the inverted bit line BLB, the select voltage Vdd is provided to the word line WL, a read voltage Vr is provided to the first antifuse control line AF1and the second antifuse control line AF2, and an off voltage Voff is provided to the isolation control line IG.

During the read cycle, the first select transistor S1and the second select transistor S2are turned on, and the isolation transistor O is turned off. The first antifuse transistor A1and the second antifuse transistor A2generate read currents to the bit line BL and the inverted bit line BLB. Generally, the read current generated by the antifuse transistor with the low-resistance state is higher, and the read current generated by the antifuse transistor with the high-resistance state is lower. For example, the read current generated by the antifuse transistor with the low-resistance state is 10 μA, and the read current generated by the antifuse transistor with the high-resistance state is 0.1 μA.

During the read cycle, a processing circuit (not shown) determines the storage state of the antifuse differential cell c1according to the magnitudes of the read currents from first antifuse transistor A1and the second antifuse transistor A2. In case that the read current generated by the first antifuse transistor A1is higher and the read current generated by the second antifuse transistor A2is lower, the antifuse differential cell c1is verified to have a first storage state. In case that the read current generated by the first antifuse transistor A1is lower and the read current generated by the second antifuse transistor A2is higher, the antifuse differential cell c1is verified to have a second storage state. Due to the manufacturing variations of the antifuse transistors A1and A2, it is unable to realize which of the antifuse transistors A1and A2has the changed state while the reading action is performed. After the antifuse differential cell c1is programmed, the storage state of the antifuse differential cell c1is used as a bit of a random code. For example, the eight storage states of the eight programmed antifuse differential cells indicate a one-byte random code.

FIG. 2Ais a schematic equivalent circuit diagram illustrating another conventional antifuse differential cell for generating a random code.FIG. 2Bis a bias voltage table illustrating the bias voltages for programming and reading the conventional antifuse differential cell ofFIG. 2A.

As shown inFIG. 2A, the antifuse differential cell c2comprises a first antifuse transistor A1, an isolation transistor O and a second antifuse transistor A2, which are serially connected between a bit line BL and an inverted bit line BLB. The gate terminal of the first antifuse transistor A1is connected with a first antifuse control line AF1. The gate terminal of the isolation transistor O is connected with an isolation control line IG. The gate terminal of the second antifuse transistor A2is connected with a second antifuse control line AF2.

The gate oxide layer of the first antifuse transistor A1comprises a first part and a second part. In the first antifuse transistor A1, the first part of the gate oxide layer is closer to the isolation transistor O, and the second part of the gate oxide layer is closer to the bit line BL. The first part of the gate oxide layer is thinner than the second part of the gate oxide layer. Similarly, the second antifuse transistor A2comprises a first part and a second part. In the second antifuse transistor A2, the first part of the gate oxide layer is closer to the isolation transistor O, and the second part of the gate oxide layer is closer to the inverted bit line BLB. The first part of the gate oxide layer is thinner than the second part of the gate oxide layer.

Please refer toFIG. 2B. During program cycle, a ground voltage (0V) is provided to the bit line BL and the inverted bit line BLB, a program voltage Vpp is provided to the first antifuse control line AF1and the second antifuse control line AF2, and an on voltage Von is provided to the isolation line IG.

During the program cycle, the storing state of one the first antifuse transistor A1or the second antifuse transistor A2is changed. For example, in case that the first part of the gate oxide layer of the first antifuse transistor A1is ruptured and the first antifuse transistor A1is changed to the low-resistance state, the second antifuse transistor A2is maintained in the high-resistance state. Alternatively, in case that the first part of the gate oxide layer of the second antifuse transistor A2is ruptured and the second antifuse transistor A2is changed to the low-resistance state, the first antifuse transistor A1is maintained in the high-resistance state.

During a read cycle, the ground voltage (0V) is provided to the bit line BL and the inverted bit line BLB, a read voltage Vr is provided to the first antifuse control line AF1and the second antifuse control line AF2, and an off voltage Voff is provided to the isolation control line IG. Consequently, the first antifuse transistor A1and the second antifuse transistor A2generate read currents to the bit line BL and the inverted bit line BLB. Subsequently, a processing circuit (not shown) determines the storage state of the antifuse differential cell c2according to the magnitudes of the read currents from first antifuse transistor A1and the second antifuse transistor A2.

Due to the manufacturing variations of the antifuse transistors A1and A2, it is unable to realize which of the antifuse transistors A1and A2has the changed state while the reading action is performed. After the antifuse differential cell c2is programmed, the storage state of the antifuse differential cell c2is used as a bit of a random code.

FIG. 3Ais a schematic equivalent circuit diagram illustrating another conventional antifuse differential cell for generating a random code.FIG. 3Bis a bias voltage table illustrating the bias voltages for programming and reading the conventional antifuse differential cell ofFIG. 3A.

As shown inFIG. 3A, the antifuse differential cell c3comprises a first select transistor S1, a first switch transistor W1, a first antifuse transistor A1, an isolation transistor O, a second antifuse transistor A2, a second switch transistor W2and a second select transistor S2, which are serially connected between a bit line BL and an inverted bit line BLB.

The gate terminal of the first select transistor S1is connected with a word line WL. The gate terminal of the first switch transistor W1is connected with a switch control line SW. The gate terminal of the first antifuse transistor A1is connected with a first antifuse control line AF1. The gate terminal of the isolation transistor O is connected with an isolation control line IG. The gate terminal of the second antifuse transistor A2is connected with a second antifuse control line AF2. The gate terminal of the second switch transistor W2is connected with a switch control line SW. The gate terminal of the second select transistor S2is connected with the word line WL.

Please refer toFIG. 3B. During a program cycle, a ground voltage (0V) is provided to the bit line BL and the inverted bit line BLB, a select voltage Vdd is provided to the word line WL, a switch voltage Vsw is provided to the switch control line SW, a program voltage Vpp is provided to the first antifuse control line AF1and the second antifuse control line AF2, and an on voltage Von is provided to the isolation control line IG.

During the program cycle, all of the first select transistor S1, the second select transistor S2, the first switch transistor W1, the second switch transistor W2and the isolation transistor O are turned on and the state of one of the first antifuse transistor A1and the second antifuse transistor A2is changed. For example, the first antifuse transistor A1is changed to the low-resistance state, but the second antifuse transistor A2is maintained in the high-resistance state. Alternatively, the second antifuse transistor A2is changed to the low-resistance state, but the first antifuse transistor A1is maintained in the high-resistance state.

During a read cycle, the ground voltage (0V) is provided to the bit line BL and the inverted bit line BLB, the select voltage Vdd is provided to the word line WL, the switch voltage Vsw is provided to the switch control line SW, a read voltage Vr is provided to the first antifuse control line AF1and the second antifuse control line AF2, and an off voltage Voff is provided to the isolation control line IG.

During the read cycle, the first select transistor S1, the second select transistor S2, the first switch transistor W1and the second switch transistor W2are turned on, and the isolation transistor O is turned off. The first antifuse transistor A1and the second antifuse transistor A2generate read currents to the bit line BL and the inverted bit line BLB. Subsequently, a processing circuit (not shown) determines the storage state of the antifuse differential cell c3according to the magnitudes of the read currents from first antifuse transistor A1and the second antifuse transistor A2.

Due to the manufacturing variations of the antifuse transistors A1and A2, it is unable to realize which of the antifuse transistors A1and A2has the changed state while the reading action is performed. After the antifuse differential cell c3is programmed, the storage state of the antifuse differential cell c3is used as a bit of a random code.

Ideally, during the program cycle of the antifuse differential cell, the gate oxide layer of only one antifuse transistor is ruptured and the state is changed. Whereas, the gate oxide layer of the other antifuse transistor is not ruptured, and the state is not changed.

However, in some situations, the gate oxide layers of the two antifuse transistors are ruptured during the program cycle of the antifuse differential cell. Correspondingly, during the read cycle, the read currents generated by the two antifuse transistors of the antifuse differential cell are very large. Under this circumstance, the processing circuit cannot accurately judge the storage state of the antifuse differential cell.

SUMMARY OF THE INVENTION

An embodiment of the present invention provides a random code generator. The random code generator includes a memory cell array and a sensing circuit. The memory cell array includes plural antifuse differential cells. The sensing circuit has an input terminal and an inverted input terminal. When a first antifuse differential cell of the memory cell array is a selected cell, a bit line of the selected cell is connected with the input terminal of the sensing circuit and an inverted bit line of the selected cell is connected with the inverted input terminal of the sensing circuit. During a read cycle, the selected cell generates a first charging current to charge the bit line and generates a second charging current to charge the inverted bit line. If a first voltage of the bit line is higher than a second voltage of the inverted bit line, the sensing circuit discharges the second voltage of the inverted bit line to enhance a voltage difference between the bit line and the inverted bit line. If the second voltage of the inverted bit line is higher than the first voltage of the bit line, the sensing circuit discharges the first voltage of the bit line to enhance the voltage difference between the bit line and the inverted bit line. The sensing circuit judges a storage state of the selected cell according to the voltage difference and determines a bit of a random code according to the storage state of the selected cell.

Another embodiment of the present invention provides a sensing method for a random code generator. The random code generator includes a memory cell array and a sensing circuit. The memory cell array includes plural antifuse differential cells. The sensing method includes following steps. Firstly, a first antifuse differential cell of the memory cell array is selected as a selected cell. Then, a first read voltage is provided to a first antifuse control line of the selected cell, a second read voltage is provided to a second antifuse control line of the selected cell, a bit line of the selected cell is connected to an input terminal of the sensing circuit, and an inverted bit line of the selected cell is connected to an inverted input terminal of the sensing circuit. Then, the bit line and the inverted bit line of the selected cell are pre-charged to a ground voltage. Then, a first charging current is generated to charge the bit line, and a second charging current is generated to charge the inverted bit line. If a first voltage of the bit line is higher than a second voltage of the inverted bit line, the second voltage of the inverted bit line is discharged so as to enhance a voltage difference between the bit line and the inverted bit line. If the second voltage of the inverted bit line is higher than the first voltage of the bit line, the first voltage of the bit line is discharged so as to enhance the voltage difference between the bit line and the inverted bit line. Then, a storage state of the selected cell is judged according to the voltage difference, and a bit of a random code is determined according to the storage state of the selected cell.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

The present invention provides a random code generator with an antifuse differential cell and an associated sensing method. Even if the read currents generated by the two antifuse transistors of the antifuse differential cell are very large during the read cycle, the sensing circuit of the present invention can still accurately judge the storage state of the antifuse differential cell.

FIG. 4is a schematic circuit block diagram illustrating the architecture of a random code generator according to a first embodiment of the present invention. As shown inFIG. 4, the random code generator400comprises a memory cell array410and a sensing circuit420.

The memory cell array410comprises plural antifuse differential cells cell1˜cell4, which have the same structures. A bit line BL and an inverted bit line BLB corresponding to the selected cell of the memory cell array410are connected with an input terminal IN and an inverted input terminal INB of the sensing circuit420, respectively. For example, if the antifuse differential cell cell1is the selected cell during a read cycle, the bit line BL and the inverted bit line BLB corresponding to the antifuse differential cell cell1are connected with the input terminal IN and the inverted input terminal INB of the sensing circuit420, respectively. Meanwhile, the sensing circuit420determines a storage state of the selected cell (e.g., the antifuse differential cell cell1) according to the read currents from the bit line BL and the inverted bit line BLB.

Similarly, if one of the antifuse differential cells cell2˜cell4is the selected cell, the bit line BL and the inverted bit line BLB corresponding to the selected cell are connected with the input terminal IN and the inverted input terminal INB of the sensing circuit420, respectively.

The structures of the antifuse differential cells will be described as follows. For example, the antifuse differential cell cell1comprises a first antifuse element402, a connection circuit408and a second antifuse element406. Each of the first antifuse element402and the second antifuse element406comprises an antifuse transistor.

The antifuse differential cells as shown inFIGS. 1A, 2A and 3Acan be used as the antifuse differential cells cell1˜cell4of the memory cell array410. During the program cycle, a program voltage Vpp is provided to the first antifuse control line AF1and the second antifuse control line AF2. During the read cycle, a read voltage Vr is provided to the first antifuse control line AF1and the second antifuse control line AF2.

In case that the antifuse differential cell as shown inFIG. 1Ais employed, the connection circuit408comprises the isolation transistor O, the first antifuse element402comprises the first select transistor S1and the first antifuse transistor A1, and the second antifuse element406comprises the second antifuse transistor A2and the second select transistor S2. In case that the antifuse differential cell as shown inFIG. 2Ais employed, the connection circuit408comprises the isolation transistor O, the first antifuse element402comprises the first antifuse transistor A1, and the second antifuse element406comprises the second antifuse transistor A2. In case that the antifuse differential cell as shown inFIG. 3Ais employed, the connection circuit408comprises the isolation transistor O, the first antifuse element402comprises the first select transistor S1, the first switch transistor W1and the first antifuse transistor A1, and the second antifuse element406comprises the second select transistor S2, the second switch transistor W2and the second antifuse transistor A2.

In addition to the antifuse differential cells as shown inFIGS. 1A, 2A and 3A, the antifuse differential cells with other structures are suitably used in the present invention. For example, in another embodiment, the connection circuit408comprises a conducting line in replace of the isolation transistor O as shown inFIGS. 1A, 2A and 3A. That is, the connection circuit408is a conducting line, and the conducting line is connected between the first antifuse element402and the second antifuse element406.

In this embodiment, the sensing circuit420comprises a positive feedback circuit422, an output circuit428, a first reset circuit424and a second reset circuit426. The two sensing terminals s1and s2of the positive feedback circuit422are connected with the input terminal IN and the inverted input terminal INB of the sensing circuit420, respectively. The first reset circuit424is connected with the input terminal IN of the sensing circuit420. The second reset circuit426is connected with the inverted input terminal INB of the sensing circuit420. The two input terminals of the output circuit428are connected with two output terminals of the positive feedback circuit422, respectively. An output terminal OUT and an inverted output terminal OUTB of the output circuit428generate two output signals that are complementary to each other.

FIG. 5is a schematic circuit diagram illustrating the sensing circuit of the random code generator according to the first embodiment of the present invention.

The positive feedback circuit422comprises four transistors mc1, mc2, m1and m2. The drain terminal of the transistor mc1is the sensing terminal s1of the positive feedback circuit422. The source terminal of the transistor mc1is connected with a node “a”. The gate terminal of the transistor mc1receives a control signal ctrl. The drain terminal of the transistor mc2is the sensing terminal s2of the positive feedback circuit422. The source terminal of the transistor mc2is connected with a node “b”. The gate terminal of the transistor mc2receives the control signal ctrl. The drain terminal of the transistor m1is connected with the node “a”. The gate terminal of the transistor m1is connected with the node “b”. The source terminal of the transistor m1is connected with a ground terminal GND. The drain terminal of the transistor m2is connected with the node “b”. The gate terminal of the transistor m2is connected with the node “a”. The source terminal of the transistor m2is connected with the ground terminal GND.

The first reset circuit424comprises a transistor mc3. The drain terminal of the transistor mc3is connected with the input terminal IN of the sensing circuit420. The source terminal of the transistor mc3is connected with the ground terminal GND. The gate terminal of the transistor mc3receives a reset signal RST.

The second reset circuit426comprises a transistor mc4. The drain terminal of the transistor mc4is connected with the inverted input terminal INB of the sensing circuit420. The source terminal of the transistor mc4is connected with the ground terminal GND. The gate terminal of the transistor mc4receives the reset signal RST.

In an embodiment, the output circuit428is a differential amplifier. The positive input terminal of the differential amplifier is connected with the node “a”. The negative input terminal of the differential amplifier is connected with the node “b”. The output terminal OUT and the inverted output terminal OUTB of the differential amplifier generates the two complementary output signals. Since the differential amplifier has been widely applied to the electronic circuits, the principles of the differential amplifier are not redundantly described herein.

In the beginning of the read cycle (i.e., a first stage of the read cycle), the transistors mc3and mc4are temporarily turned on according to the reset signal RST. Consequently, the bit line BL and the inverted bit line BLB are pre-charged to the ground voltage (i.e., 0V). Then, the selected cell generates read currents IBLand IBLBto charge the bit line BL and the inverted bit line BLB. Consequently, the voltages of the bit line BL and the inverted bit line BLB are gradually increased from 0V. In other words, the read currents IBLand IBLBare charging currents.

Generally, the voltage rising speeds of the bit line BL and the inverted bit line BLB are related to read currents IBLand IBLB. For example, if the read current IBLis higher than the read current IBLB, the voltage rising speed of the bit line BL is higher than the voltage rising speed of the inverted bit line BLB. Whereas, if the read current IBLBis higher than the read current IBL, the voltage rising speed of the inverted bit line BLB is higher than the voltage rising speed of the bit line BL.

Moreover, during the first stage of the read cycle, the transistors mc1and mc2are turned on according to the control signal ctrl. Consequently, the node “a” is connected with the bit line BL, and the node “b” is connected with the inverted bit line BLB. Since the voltage rising speeds of the bit line BL and the inverted bit line BLB are different, one of the transistors m1and m2is turned on and the other of the transistors m1and m2transistors m1and m2is turned off.

For example, if the voltage rising speed of the bit line BL is higher than the voltage rising speed of the inverted bit line BLB, the transistor m2is turned on. Consequently, the voltage of the inverted bit line BLB is discharged and gradually decreased. Since the transistor m1is turned off, the voltage of the bit line BL is continuously increased. Whereas, if the voltage rising speed of the inverted bit line BLB is higher than the voltage rising speed of the bit line BL, the transistor m1is turned on. Consequently, the voltage of the bit line BL is discharged and gradually decreased. Since the transistor m2is turned off, the voltage of the inverted bit line BLB is continuously increased.

In other words, the voltage difference between the bit line BL and the inverted bit line BLB is enhanced by the positive feedback circuit422during the first stage of the read cycle. Moreover, since the bit line BL is connected with the node “a” and the inverted bit line BLB is connected with the node “b”, the voltage difference between the node “a” and the node “b” is also enhanced.

During a second stage of the read cycle, the transistors mc1and mc2are turned off according to the control signal ctrl. According to the voltage difference between the node “a” and the node “b”, the output circuit428connected between the node “a” and the node “b” generate the output signal and the inverted output signal from the output terminal OUT and the inverted output terminal OUTB. According to the output signal and the inverted output signal, the sensing circuit420judges a storage state of the selected cell. Consequently, a bit of a random code is determined.

FIG. 6is a flowchart illustrating a sensing method for the random code generator according to the first embodiment of the present invention.

Firstly, a selected cell is selected from the memory cell array410(Step S608).

Then, a read voltage Vr is provided to the antifuse control lines AF1and AF2of the selected cell, and the bit line BL and the inverted bit line BLB of the selected cell are respectively connected with the input terminal IN and an inverted input terminal INB of the sensing circuit420(Step S610).

Then, the bit line BL and the inverted bit line BLB of the selected cell are pre-charged to a ground voltage by the first reset circuit424and the second reset circuit426(Step S612).

Then, the selected cell generates two read currents IBLand IBLBto charge the bit line BL and the inverted bit line BLB (Step S614). In other words, the read currents IBLand IBLBare charging currents for charging the bit line BL and the inverted bit line BLB.

The positive feedback circuit422enhances a voltage difference between the bit line and the inverted bit line (Step S616). If the voltage of the bit line BL is higher than the voltage of the inverted bit line BLB, the voltage of the inverted bit line BLB is discharged and the voltage difference between the bit line BL and the inverted bit line BLB is enhanced. Whereas, if the voltage of the inverted bit line BLB is higher than the voltage of the bit line BL, the voltage of the bit line BL is discharged and the voltage difference between the bit line BL and the inverted bit line BLB is enhanced.

Then, the output circuit428generates an output signal and an inverted output signal according to the voltage difference between the bit line BL and the inverted bit line BLB and determines a bit of a random code according to the storage state of the selected cell (Step S618).

From the above descriptions, the present invention provides a random code generator with an antifuse differential cell and an associated sensing method. After the antifuse differential cell of the memory cell array410is programmed, the sensing circuit420judges the storage state of the antifuse differential cell during the read cycle and determines a bit of the random code. Then, the positive feedback circuit422of the sensing circuit420enhances the voltage difference between the bit line BL and the inverted bit line BLB. Under this circumstance, even if the read currents generated by both of the bit line BL and the inverted bit line BLB are very large, the sensing circuit420is still able to accurately judge the storage state of the antifuse differential cell.

During the read cycle, the memory cell array410generates the read currents to the bit line BL and the inverted bit line BLB. In addition, the memory cell array410also generates leakage currents to the bit line BL and the inverted bit line BLB. For offseting the leakage currents, the random code generator needs to be further improved. In a second embodiment of the present invention, the sensing circuit of the random code generator further comprises two current sinks to offset the leakage currents from the memory cell array.

FIG. 7is a schematic circuit block diagram illustrating the architecture of a random code generator according to a second embodiment of the present invention. As shown inFIG. 7, the random code generator700comprises a memory cell array410and a sensing circuit720. The structure of the memory cell array410is similar to that of the first embodiment, and is not redundantly described herein.

In this embodiment, the sensing circuit720comprises a positive feedback circuit422, an output circuit728, a first reset circuit424, a second reset circuit426, a first current sink724and a second current sink726. The structures of the first reset circuit424and the second reset circuit426are similar to those of the first embodiment, and are not redundantly described herein.

The first current sink724is connected with the input terminal IN of the sensing circuit720. The second current sink726is connected with the inverted input terminal INB of the sensing circuit720. The two input terminals of the output circuit728are connected with the two output terminals of the positive feedback circuit422, respectively. Moreover, the output terminal OUT and the inverted output terminal OUTB of the output circuit728generate two complementary output signals.

FIG. 8Ais a schematic circuit diagram illustrating the sensing circuit of the random code generator according to the second embodiment of the present invention. The circuitry structures of the positive feedback circuit422, the first reset circuit424and the second reset circuit426are similar to those ofFIG. 5, and are not redundantly described herein.

The first current sink724comprises transistors m5and mc6. The drain terminal of the transistor m5is connected with the input terminal IN of the sensing circuit720. The gate terminal of the transistor m5receives a first bias voltage Vbias1. The drain terminal of the transistor mc6is connected with the source terminal of the transistor m5. The source terminal of the transistor mc6is connected with the ground terminal GND. The gate terminal of the transistor mc6receives a read enabling signal EN.

The second current sink726comprises transistors m6and mc7. The drain terminal of the transistor m6is connected with the inverted input terminal INB of the sensing circuit720. The gate terminal of the transistor m6receives a second bias voltage Vbias2. The drain terminal of the transistor mc7is connected with the source terminal of the transistor m6. The source terminal of the transistor mc7is connected with the ground terminal GND. The gate terminal of the transistor mc7receives the read enabling signal EN.

The output circuit728comprises transistors m3, m4and mc5. The source terminal of the transistor mc5is connected with a power supply voltage Vcc. The gate terminal of the transistor mc5receives the control signal ctrl. The gate terminal of the transistor mc5is connected with a node “c”. The source terminal of the transistor m3is connected with the node “c”. The drain terminal of the transistor m3is connected with the node “c”. The gate terminal of the transistor m3is connected with the node “b”. The source terminal of the transistor m4is connected with the node “c”. The drain terminal of the transistor m4is connected with the node “b”. The gate terminal of the transistor m4is connected with the node “c”. The node “a” is used as the output terminal OUT. The node “b” is used as the inverted output terminal OUTB. In this embodiment, the output circuit728has the above circuitry. In some other embodiment, the output circuit728is implemented with any other appropriate differential amplifier.

For example, during the read cycle, the leakage current generated by the memory cell array410is 0.5 μA. According to the first bias voltage Vbias1of the first current sink724and the second bias voltage Vbias2of the second current sink726, a first bias current Ibias1generated by the first current sink724and a second bias current Ibias2generated by the second current sink726are 0.5 μA. For example, the read currents IBLand IBLBoutputted from the bit line BL and the inverted bit line BLB are 12 μA and 1 μA, respectively. After the read currents are offset by the first bias current Ibias1and the second bias current Ibias2, the two charging currents are 11.5 μA and 0.5 μA, respectively. Consequently, the judging accuracy of the sensing circuit720is increased.

FIG. 8Bis a schematic timing waveform diagram illustrating associated signals processed by the sensing circuit ofFIG. 8A. During the read cycle, the read enabling signal EN is in a high level state. In the time interval between the time point t1and the time point t4, the sensing circuit720judges the storage state of a first selected cell. In the time interval between the time point t4and the time point t7, the sensing circuit720judges the storage state of a second selected cell. In the first stage of the read cycle, the control signal ctrl is in the high level state. Meanwhile, the transistors mc1and mc2are turned on, and the transistor mc5is turned off. In the second stage of the read cycle, the control signal ctrl is in the low level state. Meanwhile, the transistors mc1and mc2are turned off, and the transistor mc5is turned on.

As shown inFIG. 8B, the time interval between the time point t1and the time point t3indicates the first stage of the read cycle. Firstly, the transistors mc3and mc4are temporarily turned on according to the reset signal RST. Consequently, the bit line BL and the inverted bit line BLB are pre-charged to the ground voltage (i.e., 0V). Then, the selected cell generates read currents IBLand IBLBto charge the bit line BL and the inverted bit line BLB. Consequently, the voltages of the bit line BL and the inverted bit line BLB are gradually increased from 0V.

At the time point t2, the voltage of the bit line BL is higher than the voltage of the inverted bit line BLB, and the transistor m2is turned on according to the voltage of the bit line BL. Consequently, after the time point t2, the voltage of the bit line BL is gradually increased and the voltage of the inverted bit line BLB is gradually decreased. Since the bit line BL is connected with the node “a” and the inverted bit line BLB is connected with the node “b”, the voltage of the output terminal OUT is equal to the voltage of the bit line BL, and the voltage of the inverted output terminal OUTB is equal to the voltage of the inverted bit line BLB.

The time interval between the time point t3and the time point t4indicates the second stage of the read cycle. Meanwhile, the bit line BL is not connected with the node “a”, and the inverted bit line BLB is not connected with the node “b”. Consequently, the voltage of the inverted bit line BLB is increased again. Moreover, since the transistor mc5is turned on, the voltage of the output terminal OUT is latched to the power supply voltage Vcc, and the voltage of the inverted output terminal OUTB is latched to the ground voltage (i.e., 0V). Under this circumstance, the first selected cell is judged to have a first storage state.

Similarly, the time interval between the time point t4and the time point t6indicates the first stage of the read cycle. Firstly, the transistors mc3and mc4are temporarily turned on according to the reset signal RST. Consequently, the bit line BL and the inverted bit line BLB are pre-charged to the ground voltage (i.e., 0V). Then, the selected cell generates read currents IBLand IBLBto charge the bit line BL and the inverted bit line BLB. Consequently, the voltages of the bit line BL and the inverted bit line BLB are gradually increased from 0V.

At the time point t5, the voltage of the inverted bit line BLB is higher than the voltage of the bit line BL, and the transistor m1is turned on according to the voltage of the inverted bit line BLB. Consequently, after the time point t5, the voltage of the inverted bit line BLB is gradually increased and the voltage of the bit line BL is gradually decreased. Since the bit line BL is connected with the node “a” and the inverted bit line BLB is connected with the node “b”, the voltage of the output terminal OUT is equal to the voltage of the bit line BL, and the voltage of the inverted output terminal OUTB is equal to the voltage of the inverted bit line BLB.

The time interval between the time point t6and the time point t7indicates the second stage of the read cycle. Meanwhile, the bit line BL is not connected with the node “a”, and the inverted bit line BLB is not connected with the node “b”. Consequently, the voltage of the bit line BL is increased again. Moreover, since the transistor mc5is turned on, the voltage of the output terminal OUT is latched to the ground voltage (i.e., 0V), and the voltage of the inverted output terminal OUTB is latched to the power supply voltage Vcc. Under this circumstance, the second selected cell is judged to have a second storage state.

FIG. 9is a flowchart illustrating a sensing method for the random code generator according to the second embodiment of the present invention. In comparison with the sensing module ofFIG. 6, the sensing method of this embodiment further comprises a step S914in replace of the step S614. Hereinafter, only the step S914will be described.

In the step S914, the bias voltages Vbias1and Vbias2are provided to the current sinks724and726, so that the current sinks724and726generate the bias currents Ibs1and Ibs2. Moreover, the selected cell generates the read currents IBLand IBLB. The result of subtracting the bias current Ibs1from the read current IBL, i.e., (IBL−Ibs1), is used as the charging current to charge the bit line BL. The result of subtracting the bias current Ibs2from the read current IBL, i.e., (IBLB−Ibs2), is used as the charging current to charge the inverted bit line BLB.

Since the bias currents Ibs1and Ibs2are provided to offset the leakage currents of the memory cell array401, the judging accuracy of the sensing circuit720is increased.

Moreover, the sensing method ofFIG. 9can also be used to judge the quality of the selected cell.

During a first sensing period, the same read voltage Vr is provided to the antifuse control lines AF1and AF2, and the same bias voltage (i.e., Vbias1=Vbias2) is provided to the two current sinks724and726. Then, the sensing method as described inFIG. 9is performed to judge the storage state of the selected cell. For example, the sensing circuit720judges that the selected cell is in the first storage state.

During a second sensing period, the read voltage Vr1is provided to the first antifuse control line AF1, the read voltage Vr2is provided to the second antifuse control line AF2, and the same bias voltage (i.e., Vbias1=Vbias2) is provided to the two current sinks724and726. The read voltage Vr1is higher than the read voltage Vr2. Then, the sensing method as described inFIG. 9is performed to judge the storage state of the selected cell. If the sensing circuit720judges that the selected cell is in the second storage state, it means that the quality of the selected cell is not good.

If the sensing circuit720judges that the selected cell is in the first storage state during the second sensing period, the procedure in a third sensing period is continuously done. During the third sensing period, the read voltage Vr1is provided to the first antifuse control line AF1, the read voltage Vr2is provided to the second antifuse control line AF2, and the same bias voltage (i.e., Vbias1=Vbias2) is provided to the two current sinks724and726. The read voltage Vr1is lower than the read voltage Vr2. Then, the sensing method as described inFIG. 9is performed to judge the storage state of the selected cell. If the sensing circuit720judges that the selected cell is in the second storage state, it means that the quality of the selected cell is not good.

If the sensing circuit720judges that the selected cell is in the first storage state during the third sensing period, the procedure in a fourth sensing period is continuously done. During the fourth sensing period, the same read voltage Vr is provided to the antifuse control lines AF1and AF2, and different bias voltages (i.e., Vbias1>Vbias2) is provided to the two current sinks724and726. Then, the sensing method as described inFIG. 9is performed to judge the storage state of the selected cell. If the sensing circuit720judges that the selected cell is in the second storage state, it means that the quality of the selected cell is not good.

If the sensing circuit720judges that the selected cell is in the first storage state during the fourth sensing period, the procedure in a fifth sensing period is continuously done. During the fifth sensing period, the same read voltage Vr is provided to the antifuse control lines AF1and AF2, and different bias voltages (i.e., Vbias1<Vbias2) is provided to the two current sinks724and726. Then, the sensing method as described inFIG. 9is performed to judge the storage state of the selected cell. If the sensing circuit720judges that the selected cell is in the second storage state, it means that the quality of the selected cell is not good.

If the sensing circuit720judges that the selected cell is in the first storage state after all of the five sensing periods, it means that the quality of the selected cell is good.

From the above descriptions, the present invention provides a random code generator with an antifuse differential cell and an associated sensing method. After the antifuse differential cell of the memory cell array is programmed, the sensing circuit is capable of judging the storage state of the antifuse differential cell during the read cycle and determining a bit of the random code.