Electrical over-stress detection circuit

In an embodiment, an electrical over-stress (EOS) circuit includes a detection circuit coupled between first and second supply terminals and configured to detect a perturbation in a supply voltage potential between the first and second supply terminals or between a supply voltage potential and a pad voltage of a bond pad. The EOS circuit further includes an alert generation circuit configured to store data indicating an EOS event in response to detecting the perturbation.

FIELD

The present disclosure is generally related to integrated circuits, and more particularly to electrical over-stress detection circuits for integrated circuits.

BACKGROUND

Electronic circuits can be susceptible to damage or operational failure as a result of Electrostatic Discharge (ESD) events or Electrical Over-stress (EOS) events that occur on their terminals. An ESD event or an EOS event may occur, for example, when a user who has accumulated electrostatic charge picks up the integrated circuit, touches an exposed pin, or, for example, interacts with a touch pad coupled to the integrated circuit. As used herein, the term “ESD event” refers to a transient surge of energy, which may be as high as a few thousand volts, that appears across the terminals of the integrated circuit. As used herein, the term “EOS event” refers to a rapid change in energy that appears on terminals of the integrated circuit, which change may be greater than an application-specific threshold and which can cause an observable change in the behavior of the circuit. While EOS events can be produced through user interactions with the circuit, EOS events can also be created within the chip itself, such as through switching activity of a large input/output driver circuit. Regardless of the source, such EOS events may disrupt operation of the circuit (such as by corrupting measurement data) or may cause long term damage by over-stressing sensitive circuitry.

Most integrated circuits incorporate ESD protection structures that are coupled to input/output (I/O) pins and to the power supply terminals to protect other circuit structures on the integrated circuit. Such ESD protection structures are designed to activate in response to a transient voltage in excess of a pre-determined energy threshold, which is usually at a voltage level that is below a voltage rating for associated circuitry. In a particular example, if a logic circuit of the integrated circuit is rated to withstand voltages up to approximately 7.0 volts, the ESD energy threshold would be set at a level below 7.0 volts, so that the ESD protection structure is activated to clamp the voltage before the voltage rises to a level that would damage the other circuitry. It should be understood that the above numbers are illustrative only, and that other voltages, both lower and significantly higher, may be used as thresholds in such circuits. In many instances, such ESD protection structures operate to clamp the input voltage at a pre-configured voltage level and to divert excess energy from the ESD event to one of the power supply terminals in order to prevent damage to the circuitry from such high-energy transients.

EOS discharges below the ESD threshold level may not activate the ESD protection structure. However, the elevated voltage and/or current peaks associated with these discharges can nevertheless disrupt circuit operation and may damage associated circuitry. Circuit functions that involve the generation or measurement of very small voltages or currents, such as analog-to-digital converters, are particularly susceptible to corruption from such EOS events. Such corruption can include short-term disruption of measurement data and/or permanent damage to measurement circuitry due to over-stress. Furthermore, it can be very difficult to determine when such corruption occurs, since the EOS-induced perturbation in the integrated circuit's output may be similar to one caused by a valid change to an analog input signal.

SUMMARY

In an embodiment, an electrical over-stress (EOS) circuit includes a detector coupled to first and second supply terminals and configured to detect a perturbation in a supply voltage potential between the first and second supply terminals. The EOS circuit further includes an alert generator configured to store data indicating an EOS event in response to the detection circuit detecting the perturbation.

In another embodiment, a circuit includes an electrostatic discharge (ESD) protection circuit for detecting a voltage potential that exceeds an ESD threshold between first and second supply terminals. The circuit further includes an electrical over-stress (EOS) detector configured to detect a perturbation in the voltage potential that is greater than a pre-determined threshold and, in response to detecting the perturbation, to store in a storage element data indicating an EOS event in response to detecting the perturbation in a storage element.

In still another embodiment, a system includes a first supply terminal, a second supply terminal, and a circuit coupled between the first and second supply terminals. The circuit is sensitive to perturbations in a voltage potential between the first and second supply terminals. The system further includes an electrostatic discharge (ESD) protection circuit configured to detect an ESD event when the voltage potential between the first and second supply terminals exceeds an ESD threshold. The ESD protection circuit is configured to shunt excess current between the first and second supply terminals and to clamp the voltage potential at a pre-determined voltage level in response to detecting the ESD event. The system also includes an electrical over-stress (EOS) circuit including an EOS detector and a storage element. The EOS detector is configured to detect a perturbation in the voltage potential that is greater than an EOS threshold and, in response to detecting the perturbation, to store in the storage element data indicating detection of an EOS event.

In the following description, the use of the same reference numerals in different drawings indicates similar or identical items. Further, it should be understood that the drawings are provided for illustrative purposes only. In the illustrated embodiments, direct connections between components are illustrative and it should be understood that such illustrated connections may include intervening elements that are not shown.

DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS

Exemplary embodiments of an EOS detection circuit are described below that are configured to determine when an EOS event has occurred and to produce an output signal in response to detecting the EOS event. The output signal can be a digital signal that can be stored by a storage element, allowing a control circuit coupled to the storage element to process the EOS event, such as applying appropriate filtering to output values or sets of output values, discarding potentially corrupted data, and so on.

In the following discussion of the illustrated embodiments, various elements are depicted as being connected to one another. However, it should be understood that the various embodiments may include additional circuit elements (not shown) through which such connections are made. Accordingly, in the following discussion, the term “coupled” includes, but is broader than, a direct connection.

FIG. 1is a block diagram of an embodiment of a portion of an integrated circuit100including an EOS detection circuit102. Circuit100includes a first supply terminal104and a second supply terminal106. Circuit100further includes an electrostatic discharge (ESD) protection circuit108, and a control circuit118. ESD protection circuit108, EOS detection circuit102, and control circuit108are coupled between first and second supply terminals104and106.

Circuit100may include other circuitry, such as discrete circuit components and integrated circuits. Such circuitry is typically designed to withstand voltages up to a maximum threshold for the particular component or circuit. Such a maximum threshold is typically determined based on the lowest voltage rating of any of the components of the circuit. ESD protection circuit108is configured to detect a power surge in excess of an ESD threshold, which is less than the maximum threshold, and to clamp or limit a voltage potential between the first and second supply terminals to a desired level until the transient event is over and the excess energy is dissipated. In particular, the ESD protection circuit108may shunt excess current between the first and second supply terminals104and108and clamp the voltage at a level that corresponds to one or more diode voltage drops.

EOS detection circuit102includes detection circuit112configured to detect a perturbation in the voltage potential between the first and second supply terminals104and106. Such a perturbation may be any variation in the voltage potential, including variations that are equal to or that exceed a pre-determined threshold, which may be less than the ESD threshold. In some instances, detection circuit112may be configured to detect variations that are as small as or smaller than a single diode voltage drop.

EOS detection circuit102further includes alert generation logic110, which is responsive to detection circuit112to store a value indicating detection of the perturbation. Alert generation logic110includes a storage element116, which is coupled to an output terminal114. In some instances, alert generation logic110changes from a first state to a second state in response to detection of the perturbation, and is returned to its first state, for example, by a reset signal from control circuit118.

Storage element116may be a memory device, a register, a latch, a counter, or other data storage element or circuit, which is configured to store one or more values indicative of an EOS event. In some instances, storage element116may be configured to retain a log or history of perturbation events, which log or history may be accessed to retrieve data for analysis. Storage element116is coupled to control circuit118by output terminal114. In an embodiment, storage element116stores a status bit, which can be used as an interrupt for control circuit118. In this instance, control circuit118may periodically poll the output terminal114to determine the value of the status bit and may perform some operation in response to a status bit indicating the detection of a perturbation. In some instances, the perturbation may be caused by a change in an analog signal, and control circuit118may be configured to perform various functions to determine the cause of the perturbation. In other instances, control circuit118may reset various measurements or perform other operations in response to the status bit. Once the operations are performed, control circuit118resets the memory element116.

In operation, detection circuit112detects a perturbation in the voltage potential between the first and second supply terminals104and106or between one of the first and second supply terminals104and106and a bond pad, such as the bond pad208depicted inFIG. 2. Alert generation logic110stores data related to the perturbation in storage element116, which stores the data even after the perturbation is removed, allowing time for control circuit118to notice that a perturbation was detected. Since transient events occur quickly and dissipate rapidly, storage element116retains information related to a detected perturbation, allowing time for the control circuit118to detect and evaluate the event.

It should be noted that the ESD threshold is typically much greater than the EOS threshold, which makes it possible for the EOS detection circuit102to store data from EOS events that may be too small to activate the ESD protection circuitry, but which nevertheless may damage sensitive circuitry or cause circuitry to produce an incorrect output. Additionally, the ESD threshold is typically determined by the associated circuitry, whereas the pre-determined EOS threshold may be application-specific. In some instances, the EOS threshold may be programmed, such as by providing a programmable reference current source (such as the current sources depicted inFIGS. 6 and 7below.

While the illustrated circuit100does not show a bond pad, bond pads, pins, and other conductive leads can be sources of ESD and EOS events. Such bond pads may be coupled to ESD protection circuit108through first and second supply terminals104and106. In some implementations, EOS detection circuit102may also be coupled to such a bond pad to detect EOS events. One example of circuit including EOS detection circuit102coupled to a bond pad for detecting an EOS event is described below with respect toFIG. 2.

FIG. 2is a schematic diagram of a circuit200including an embodiment of the EOS detection circuit102ofFIG. 1. Circuit200includes supply pins204and206coupled to supply terminals104and106, respectively. Supply pin (VDD)204carries a voltage that is positive relative to a voltage on supply pin (VSS)206. Additionally, circuit200includes diodes210and212coupled in series between supply terminals104and106. The anode of diode212is coupled to supply terminal106and the cathode is coupled to a bond pad208. The anode of diode210is coupled to bond pad208and the cathode is coupled to supply terminal104.

Diodes210and212form part of the ESD protection circuit108and may be formed from the drain-to-bulk junctions of metal oxide semiconductor field effect transistors (MOSFETs) or may be implemented as separate devices. Diodes210and212will shunt high current from an ESD or EOS event on the bond pad208to the supply terminals104and106. For example, an EOS discharge that is negative with respect to a ground supply voltage will cause diode212to turn on, preventing the voltage on bond pad208from falling to a negative voltage level that might damage circuit200. Resistor220isolates internal circuits from EOS events on the bond pad208by ensuring that the high currents flow through diodes212and210, which are designed to withstand high transient current levels. A typical “on” voltage across diode212may be around 0.6V at moderate currents, but could exceed 1V during high-energy EOS events.

EOS detection circuit102includes a current source214coupled to supply terminal104and configured to provide a current (I1) to a drain of a transistor216, which is an n-channel MOSFET. Transistor216further includes a gate coupled to supply terminal106and a source coupled to bond pad208through resistor220. Resistor220includes a first terminal coupled to bond pad208and a second terminal coupled to the source of transistor216. Further, EOS detection circuit102includes a parasitic transistor218, which is an NPN bipolar junction transistor that is an integral part of transistor216, with its collector, base, and emitter formed from the n-doped drain, p-doped bulk, and n-doped source regions of transistor216, respectively.

In operation, in a normal state, transistor216and parasitic transistor218are turned off (i.e. nonconductive), and current source214will pull up a voltage on the drain of transistor216to voltage potential of supply terminal104, i.e., a logic high level. In response to a negative EOS discharge on the bond pad218, the pad voltage will drop below ground until diode212becomes forward-biased, causing diode212to conduct current and clamping the pad voltage. This pad voltage will be coupled through resistor220to the source of transistor216, which is also the emitter of parasitic transistor218. The decreasing voltage potential of the source of transistor216and the emitter of parasitic transistor218will turn these devices on, causing the drain voltage at the input of the alert generation logic110to decrease to a level that approaches the clamped voltage level, i.e., a logic low level. Thus, the drain voltage is a digital value that represents normal operation in its high state (VDD) and that represents detection of a negative EOS event in its low state, which digital value can be stored in storage element116of alert generation logic110.

In the illustrated embodiment, the conduction characteristics of transistor216and parasitic transistor218, and the value of pull-up current source214determine the detection threshold. Since the base-emitter junction of parasitic transistor218would normally be formed from the same types of doped semiconductor regions as are used for p-n junction of diode212, and since the voltage potentials across those two junctions would be substantially the same (assuming that the current in parasitic transistor218is low enough that the voltage drop across resistor220is negligible), then the base-emitter current of parasitic transistor218will be proportional to the current in diode212, with the proportionality constant determined primarily by the ratio the effective p-n junction areas of the two devices. For a given current value, the voltage across diode212is a strong function of temperature; however, the base-emitter junction of parasitic transistor218will have a matching temperature characteristic, so that the current ratio between diode212and parasitic transistor218will be substantially independent of temperature. The collector current of parasitic transistor218is proportional to the base current, and can be calculated according to the following equation:
Ic=β×Ib(1)

In Equation 1, the collector current (Ic) is proportional to the base current (Ib) of the parasitic transistor218based on beta (β) in the forward-active region. Further, the contribution of parasitic transistor218to the total pull-down current is determined primarily by the junction area of diode212, the base-emitter junction area of parasitic transistor218, and the beta of parasitic transistor218, provided that the current is low enough to neglect the effect of resistor220.

Transistor216will provide a pull-down current in parallel to that of parasitic transistor218. The width-to-length (W/L) ratio of transistor216and its threshold voltage (VT) largely determine the magnitude of the pull-down current. A typical N-channel MOSFET used inside a circuit having a bond pad218may have a threshold voltage of around 0.7V at room temperature. If transistor216is produced in a similar manner, transistor216may not become conductive until diode212is conducting a large current. However, the fact that the source of transistor216will be at a lower potential than the bulk terminal means that the effective threshold voltage of transistor216will be reduced by the back-gate effect, and the effective threshold voltage of transistor216may be comparable to or even below the voltage at which diode212conducts substantial current.

By appropriate choice of the W/L ratio of transistor216, the emitter area of parasitic transistor218, and the size of the pull-up current (I1), it is possible to adjust the switching point of the input to alert generation logic110on the drain of transistor216over a wide range, so that the circuit200may be designed with high sensitivity (to detect very small currents flowing through diode212), with low sensitivity (so that the output signals switches only upon detection of large EOS events), or with any desired threshold. A circuit200configured with high sensitivity would be able to detect a wide range of interfering events, such as low-level interference from noise sources via capacitive, inductive, or electromagnetic coupling, but may result in a larger number of false alarms. Such false alarms can be filtered out by control circuit118either through testing of various parameters, by reviewing other values stored in storage element116, or through various filters.

It is also possible to provide adjustable sensitivity by making any of those parameters programmable in response to an analog control signal or a digital control word. For example, current source214may be implemented as a programmable current source. Current source214can be implemented as an active current source or as a resistor, either of which can be made to have programmable values. Adjustable sensitivity can be used to tune circuit200for specific sources of interference or to compensate for manufacturing-induced variations, supply-induced variations, or temperature-induced variations in components of EOS detection circuit102.

In the illustrated embodiment, EOS detection circuit102pulls down the voltage on the drain of transistor216when a pad voltage on bond pad208is negative relative to the supply potential of supply terminal106by at least one diode voltage drop of diode212. In particular, the threshold voltage of diode212operates as a perturbation detection threshold for EOS detection circuit102.FIG. 3shows representative example waveforms on bond pad208and on the drain of transistor216during a representative EOS event, which illustrates the diode212operating as an EOS threshold.

FIG. 3is a graph300of voltage versus time of an input voltage304at bond pad208and an output voltage302at the drain of transistor216of EOS detection circuit102for an EOS event that forces the pad voltage to drop below a voltage on supply terminal106. When an EOS event occurs at314, a negative voltage is applied to bond pad208. The pad voltage on bond pad208decreases from ground until diode212is forward biased, causing diode212to conduct current at314until the voltage on bond pad208is clamped by diode212at324. The drain voltage of transistor216that is provided to output114remains at a high state at312while diode212begins conducting, and then changes from the high state to a low state, starting at322when the pad voltage decreases below the threshold (i.e., a threshold voltage of diode212) of EOS detection circuit102. Output voltage302may decrease to the clamped voltage level at332, approximately 0.0020 microseconds after the start of the EOS event.

While circuit200can be adjusted by programming various parameters, sensitivity can also be enhanced by incorporating a capacitor between the bond pad208and the drain of transistor216. An example of an alternative circuit that includes such a capacitor is described below with respect toFIG. 4.

FIG. 4is a schematic diagram of a second embodiment of a circuit400including the EOS detection circuit102ofFIG. 1. This embodiment of EOS detection circuit102is the same as that described above with respect toFIG. 2, except that a capacitor402is added that is coupled between bond pad208and the drain of transistor216, which is also coupled to output114.

In operation, capacitor402serves as a parallel current path to couple fast transient events on bond pad208to the drain of transistor216, which is the input to alert generation logic110. Coupling transients directly to the input of alert generation logic110provides an additional opportunity for adjusting the sensitivity of the EOS detection circuit102or for tailoring the sensitivity of EOS detection circuit102to detect EOS events having a specific set of characteristics. In particular, AC transients can be shunted to the output terminal114even before the diodes212and210begin conducting, and alert generation logic110can capture such transients to provide an early interrupt for control circuit118.

Embodiments of the EOS detection circuit102shown inFIGS. 1,2, and4uses an N-channel MOSFET that will detect EOS events that produce a drop in the pad voltage on bond pad208that fall below the voltage potential on supply terminal106by more than a diode voltage drop across diode212. In the circuit400ofFIG. 4, EOS detection circuit102is also configured to capture fast transients that fall below ground. However, it may be desirable to detect increases in the pad voltage that rise above the positive supply rail. A complementary circuit (such as a P-channel MOSFET) can be used to detect EOS events that cause the pad voltage to rise above the VDD potential. One example of such a circuit is discussed below with respect toFIG. 5.

FIG. 5is a schematic diagram of a circuit500including third embodiment of the EOS detection circuit102ofFIG. 1. The illustrated embodiment of the EOS detection circuit102of circuit500includes the components discussed above with respect toFIG. 2and includes a PMOS transistor502and a second current source504to provide a second current (I2). PMOS transistor502includes a source coupled to the source of NMOS transistor216and to resistor220. PMOS transistor502further includes a gate coupled to supply terminal104and a drain coupled to current source504.

In this instance, transistors216and502cooperate to sense pad voltages that are below ground or above a positive supply rail. PMOS transistor502has an inherent parasitic PNP bipolar junction transistor (not shown) formed in the same manner as the NPN transistor218associated with NMOS transistor216. NMOS transistor216detects negative perturbations (i.e., perturbations that are more negative than the negative supply potential) and PMOS transistor502detects perturbations that are greater than the positive supply potential). The positive and negative detectors can have separate digital outputs corresponding to the voltages on their respective drains, but to minimize circuit area and routing, the outputs of the two detectors may be combined into a single digital output using logic circuitry included in alert generation circuit110to provide a single input to storage element116.

In the illustrated embodiment, one possible implementation of alert generation logic110, including logic circuitry to combine the digital outputs to produce a single digital output, is depicted. Alert generation circuit110includes an inverter506having an input coupled to the drain of transistor216and having an output coupled to a first input of a logical OR gate508. OR gate508further includes a second input coupled to the drain of PMOS transistor502and includes an output coupled to a data input of a storage element116. Storage element116includes a reset input coupled to reset pin510and an output coupled to output terminal114. Storage element116also includes a clock input for receiving a clock signal (not shown). Since many EOS events are very fast, it may be desirable to capture (latch) the output of EOS detection circuit102to give the system (such as a control circuit) time to respond appropriately.

Once the system has acknowledged the EOS event, the system (or control circuit) applies a signal to reset pin512to clear (reset) storage element116to resume EOS detection. In one embodiment, the system is a microcontroller unit (MCU), and the output of storage element116could be made available as a register bit that could be polled by software, or it could serve as a hardware interrupt. The MCU would clear the bit after processing the interrupt.

In some embodiments, it may be advantageous to combine the outputs of a plurality of EOS detection circuits102into a single interrupt source in order to reduce circuit size and complexity. In such a case, information about which pad suffered the EOS event may be lost. However, in many situations it is actually the high current flowing through the supply terminals104and106(which may be VDD and ground lines) that causes the most significant circuit malfunction. In such instances, it may not be important for the system to determine which specific I/O pad introduced the EOS energy.

The system may use the interrupt or EOS event detection signal in a variety of ways, depending on the context. In one instance, upon receipt of the EOS detection signal from storage element116, the system is configured to flush recent measurement data or other data sensitive to EOS perturbations. In other instances, the system is configured to apply filters to such data to correct for any such perturbations, for example by interpolating the measurement data with respect to other measurements. In still other instances, the system is configured to run diagnostics to determine whether any circuitry sustained permanent damage due to the EOS event. In an embodiment, control circuit118may use historical data retrieved from storage element116to produce filters for processing EOS events.

In the illustrated embodiments of EOS detection circuit102depicted inFIGS. 2,4, and5, only one circuit is shown. However, it should be appreciated that detection thresholds of EOS detection circuit102are programmable, and that, within an integrated circuit, additional detection circuits may be included that are programmed to have different thresholds.

Further, while the embodiments of EOS detection circuit102depicted inFIGS. 2,4, and5detect EOS events that exceed a threshold that corresponds to a diode voltage drop across either diode212or diode210, it is possible to detect smaller perturbations. In some instances, it may be desirable to detect EOS events that are less than a diode voltage drop. One example of a circuit to provide such high sensitivity to EOS events is described below with respect toFIG. 6.

FIG. 6is a schematic diagram of a circuit600including a fourth embodiment of the EOS detection circuit102ofFIG. 1. In this embodiment, EOS detection circuit102includes current sources602,604, and606and transistors612,614, and616, which are n-channel MOSFETs. First current source602is coupled to supply terminal104and is configured to provide a first current (I1) to a drain of transistor612, which includes a gate and includes a source coupled to supply terminal106. Second current source604is coupled to supply terminal104and is configured to provide a second current (I2) to a drain of transistor614, which includes a gate coupled to the gate of transistor612and includes a source coupled to supply terminal106. Third current source606is coupled to supply terminal104and is configured to provide a third current (I3) to a drain of transistor616, which includes a gate coupled to the gate of transistor612and includes a source coupled to supply terminal106. EOS detection circuit102further includes a capacitor608, which includes a first electrode coupled to supply terminal104and a second electrode coupled to the gates of transistors612,614, and616. Additionally, the drains of transistors612and616are coupled to first and second inputs, respectively, of alert generation logic110. The first input of alert generation logic110may be inverted (as illustrated by inverter610).

In operation, transistor614is diode-coupled to provide a reference current. In one embodiment, transistors612and616may be sized in order to allow more or less current to flow in response to the same applied gate voltage. When the potential difference between the voltages on the positive and negative supply terminals104and106is constant or changes very slowly, circuit600will be in a balanced state. In one embodiment, the currents I1, I2, and I3are substantially equal, and the W/L ratio of transistor612is larger than that of transistor614, while the width-to-length (W/L) ratio of transistor616is smaller than that of transistor614. In response to such a substantially constant or slowly changing voltage, transistor612will conduct more current than transistor614, and therefore the drain of transistor612will stay near the negative supply voltage. Conversely, transistor616will conduct less current than transistor614, so the drain of transistor616will be pulled high by current source606. The logic high level at the drain of transistor616will be inverted by inverter610, resulting in a logic low signal provided to alert generation logic110.

In response to a rapid increase in the positive supply voltage on supply terminal104, the rapid increase will be passed through capacitor608to diode-connected transistor614, causing a temporary increase in the currents conducted by transistors612,614, and616. Since the drain of transistor612is already at a logic low level, an increase in the current conducted by transistor612will have no effect on its drain voltage. However, an increase in the drain current of transistor616may, if it exceeds a threshold, cause the drain of transistor616to change from a logic high to a logic low level. Inverter610will invert this logic low level to present a logic high signal to alert generation logic110. From this description, it is apparent that a rapid decrease in the positive supply voltage can cause the voltage on the drain of transistor612to change from a logic low level to a logic high level. Thus, circuit600is capable of detecting either positive or negative perturbations in the voltage potential between supply terminals104and106.

The sensitivity of circuit600(i.e. the detection thresholds) may be modified by adjusting the values of currents I1, I2, and I3, the value of capacitor608, and the W/L ratios of transistors612,614, and616. From this description, it should be apparent that similar behavior would be obtained by making transistors612,614, and616to be the same size, and instead by varying the values of currents I1, I2, and I3such that I1<I2<I3.

Because of the action of capacitor608, circuit600will be responsive to transient EOS events, but will not be responsive to gradual changes in supply voltage. Many circuits are designed to operate from a variety of supply voltages, or can operate from a supply voltage that changes slowly with time, such as a discharging battery. Because such a supply voltage can vary over time and over a predetermined range, it is not feasible to employ a detector with a fixed, absolute threshold voltage or voltages, since an EOS event may cause a perturbation in the supply voltage that is sufficiently large to cause harm, but which does not cause the supply voltage to exceed the predetermined acceptable operating voltage range. Therefore, circuit600is responsive to changes in the supply voltage potential rather than to absolute levels, providing a superior solution.

Depending on the implementation, current sources602,604, and606may be resistors, resistive networks, MOSFET devices, or more complex circuits. Depending on the implementation, the current sources602,604, and606may be programmable to allow the sensitivity to perturbations to be adjusted.

In an alternative embodiment, a resistor may be included between the gate of the diode-connected transistor614and the gates of transistors612and616, providing a differential between the gate-to-source voltages. One example of such a circuit is described below with respect toFIG. 7.

FIG. 7is a schematic diagram of a circuit700including a fifth embodiment of the EOS detection circuit102ofFIG. 1. The illustrated circuit700is configured the same as circuit600inFIG. 6, except that a resistor702is included between the gate of transistor614and the gates of transistors612and616. Additionally, a separate coupling is provided between the drain and the gate of transistor614. Thus, transistor614is diode-connected, and the voltage on the gates of transistors612and616are related to the voltage on the drain of transistor612through resistor702.

In operation, resistor702provides a voltage differential between the gate of transistor614and the gates of transistors612and616. In this instance, circuit700operates the same as the circuit600inFIG. 6. Fast-transients are passed by capacitor608to the gates of transistors612and616, while the gate of transistor614receives such transients through resistor702. Thus, any rapid perturbation in the voltage potential between supply terminals104and106will imbalance current flow through transistors612and616. Thus, the size of resistor702, the sizes of transistors612,614, and616, and the current sources602,604, and606may be controlled to provide a desired sensitivity to perturbations on the supply terminals104and106.

While the illustrated embodiments of600and700included only a single EOS detection circuit102, it should be appreciated that the circuits600and700may be implemented with multiple EOS detection circuits. In such an implementation, each of the EOS detection circuits may be configured to have a different detection threshold, making it possible to reliably detect a power event and to provide a signal indicative of detection of a power event to a storage element.

In the circuits600and700shown inFIGS. 6 and 7, capacitor608makes the EOS detection circuit102responsive to fast transient voltages as opposed to a slowly changing supply potential. However, in other embodiments, an analog-to-digital converter (ADC) can be configured to periodically sample the supply voltage, and logic can be implemented in hardware or software to look for a large difference between successive ADC samples, such a large difference can cause the circuit to generate an interrupt or set a status bit. While EOS detection using an ADC may be more expensive than implementing a capacitor, the ADC makes it easier for the EOS detection to be implemented in software. Other techniques for identifying fast-transients while ignoring slow-changing voltage potentials are also contemplated.

In the above-discussion ofFIGS. 2,4,5, and7, resistors are depicted as discrete circuit elements. However, it should be understood that such resistors may be implemented as adjustable impedance networks, which can be controlled or programmed to alter the impedance dynamically in order to provide a desired sensitivity. Further, in some instances, the programmable impedance may provide a complex impedance.

In an embodiment, a system may be provided that includes circuitry, which is sensitive to perturbations in a voltage potential between two terminals. Such circuitry can include capacitive-sensor circuitry (such as for a touch-screen or touch-pad type of human interface), a keypad, a voltage or current reference circuit, a receiver circuit, or other circuitry that can be impacted by such perturbations. The system may include ESD protection circuitry coupled to the two terminals to detect and provide protection from ESD events. The system may also include an EOS circuit coupled to the two terminals. The EOS circuit can be configured to detect an EOS event and to store data indicating detection of the EOS event in a data storage element, such as a register, a latch, or other storage element. The system may be part of an electronic device, such as a music player, a portable computer, a portable phone, or another electronic device.

While the above-discussion has focused on embodiments of EOS detection circuit102, it should be appreciated that, regardless of the circuitry used to detect the EOS event, the resulting digital signal may be used in a variety of ways to prevent data corruption, to diagnose permanent damage, and so on. One possible method that can be implemented based on the EOS detection circuit is described below with respect toFIG. 8.

FIG. 8is a flow diagram of an embodiment of a method800of detecting an EOS event using the EOS detection circuit ofFIG. 1. At802, a perturbation is detected in a voltage level on one of a first supply terminal or a second supply terminal relative to a threshold level. The threshold level may be based on a discrete circuit component, such as a diode, or may be based on a programmable circuit element, such as a programmable current source or an adjustable resistance. In some instances, the threshold level may also be based on appropriate sizing of transistors.

Advancing to804, an output signal is generated in response to detecting the perturbation in the voltage level. The output signal may be a digital voltage level indicating a logic high voltage in a first state (such as a non-EOS state) and a logic low voltage in a second state (such as an EOS event detected state).

Continuing to806, the output signal is provided to a storage element having an output accessible to a control circuit to indicate a detected perturbation in the power supply. Thus, storage element captures even fast, transient, EOS events, allowing time for the control circuit or system to notice the event and appropriately process the event. Moving to808, the output signal (or register value) is processed by the control circuit or system. In an example, the control circuit is configured to investigate the source of the EOS event, to review and optionally discard recent data, to reset or recalibrate various components, or perform other operations in response to receiving the output signal indicating detection of the EOS event. In some instances, the control circuit or system may perform a diagnostic process to determine whether any permanent damage was sustained. Further, the control circuit may produce an output to a user interface or other system, providing a notification function to alert an administrator or operator.

In conjunction with the circuits and methods described above with respect toFIGS. 1-8, embodiments of an EOS detection circuit are described that are configurable to detect a perturbation in a voltage potential between power supply rails and/or between a supply terminal and a bond pad and to store a value in response to detecting the perturbation. The digital signal may be latched to provide time for a control circuit or system to process the signal. In some embodiments, the threshold at which a perturbation is detected may be related to a diode voltage drop. In other embodiments, the sensitivity of the EOS detection circuit is programmable, allowing for detection of extremely small perturbations.