Current detection circuit

A current detection circuit includes an N-type first transistor configured to supply a first current to an output terminal, an N-type second transistor that constitutes a current mirror circuit with the first transistor, a comparison circuit configured to output a detection result showing whether or not the first current is larger than a predetermined threshold based on a current flowing through the second transistor, a ground fault detection circuit configured to output a result detecting a ground fault of the output terminal, and a logical circuit configured to output a current detection signal showing whether or not the first current is an overcurrent based on the detection result of the comparison circuit and the ground fault detection result of the ground fault detection circuit.

CROSS-REFERENCE TO RELATED APPLICATION

This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2019-98774 filed in Japan on May 27, 2019; the entire contents of which are incorporated herein by reference.

FIELD

An embodiment of the present invention herein relates generally to a current detection circuit.

BACKGROUND

In a conventional driving circuit configured to supply a current to, for example, a motor or a power supply circuit, a current detection circuit may be provided in order to prevent an overcurrent. The current detection circuit detects a current flowing through an output transistor and detects an overcurrent based on whether or not a current value is larger than a threshold.

However, depending on conditions of a ground fault etc. of an output terminal, a problem that the current detection circuit may be incapable of detect an overcurrent is present.

DETAILED DESCRIPTION

A current detection circuit according to an embodiment includes an N-type first transistor configured to supply a first current to an output terminal, an N-type second transistor that constitutes a current mirror circuit with the first transistor, a comparison circuit configured to output a detection result showing whether or not the first current is larger than a predetermined, threshold based on a current flowing through the second transistor, a ground fault detection circuit configured to output a result detecting a ground fault of the output terminal, and a logical circuit configured to output a current detection signal showing whether or not the first current is an overcurrent based on the detection result of the comparison circuit and the ground fault detection result of the ground fault detection circuit.

Hereinafter, the embodiment of the present invention will be described in detail with reference to the accompanying drawings.

First Embodiment

FIG. 1is a circuit diagram showing a current detection circuit according to a first embodiment. Further.FIG. 2is a circuit diagram showing related technology of the current detection circuit. The current detection circuit according to the present embodiment adds a circuit that performs a ground fault detection to a circuit that performs a current detection and detects an overcurrent based on a current detection result and a ground fault detection result. InFIGS. 1 and 2, the same components are denoted by the same reference numerals, and redundant description is omitted in the same components. For example, the current detection circuit shown inFIGS. 1 and 2may configure a high side driver.

First, the related technology of the current detection circuit will be described with reference toFIG. 2. An N-type MOS transistor M1is an output transistor configured to supply a current Woad to a load (not shown) connected to an output terminal VOUT. A drain of the transistor M1is connected to a power supply terminal VCC1, a source of the transistor M1is connected to the output terminal VOUT, and an output of a gate voltage control circuit1is applied to a gate of the transistor M1. The transistor M1is driven by the gate voltage control circuit1and outputs the current ILoad corresponding to a drain-source voltage Vgs to the output terminal VOUT.

The gate voltage control circuit1operates while a voltage is applied from a power supply terminal VCC2and supplies a voltage corresponding to a fluctuation in a load connected to the output terminal VOUT to the gate of the transistor M1to thereby control the predetermined current ILoad to flow through.

An N-type MOS transistor M2that constitutes a current mirror circuit with the transistor M1is provided to detect the current ILoad. Specifically, a gate of the transistor M2is connected to the gate of the transistor M1and a drain of the transistor M2is connected to the power supply terminal VCC1. Note that a size of the transistor M2is α times the size of the transistor M1. A value a is a real number smaller than one and is an extremely small value. Accordingly, when a gate potential, a drain potential, and a source potential of the transistor M1are the same as a gate potential, a drain potential, and a source potential of the transistor M2, respectively, a current α times the current ILoad flows through the transistor M2.

An operational amplifier AMP1is adopted in order to make the source potential of the transistor M1and the source potential of the transistor M2the same. A positive input terminal of the operational amplifier AMP1is connected to the source of the transistor M1and a negative input terminal of the operational amplifier AMP1is connected to a source of the transistor M2. An output terminal of the operational amplifier AMP1is connected to a gate of a P-type MOS transistor M3. A source of the transistor M3is connected to the source of the transistor M2and a drain of the transistor M3is connected to a reference potential point through a drain-source path of an N-type MOS transistor M4.

The operational amplifier AMP1controls the transistor M3to make the positive input terminal and the negative input terminal the same potential. Thereby, the current α×ILoad flows from the source of the transistor M2to the reference potential point.

A gate of the transistor M4is connected to a drain of the transistor M4, and at the same time, is also connected to a gate of an N-type MOS transistor M5with which the transistor M4constitutes a current mirror circuit. A drain of the transistor M5is connected to a power supply terminal VCC3through a drain-source path of a P-type MOS transistor M6and a source of the transistor M5is connected to the reference potential point.

In the transistor M6, a gate of the transistor M6is connected to a drain of the transistor M6, and at the same time, is also connected to a gate of a P-type MOS transistor M7with which the transistor M6constitutes a current mirror circuit. A source of the transistor M7is connected to the power supply terminal VCC3and a drain of the transistor M7is connected to the reference potential point via a resistor R1.

Through the current mirror circuit configured by the transistor M4and the transistor M5, the current α×ILoad flowing through the drain-source path of the transistor M4also flows through a source-drain path of the transistor M5and a source-drain path of the transistor M6. Further, through the current mirror circuit configured by the transistor M6and the transistor M7, the current α×ILoad flowing through the source-drain path of the transistor M6also flows through a source-drain path of the transistor M7and the resistor R1.

In a case in which a size ratio of the transistor M4and the transistor M5is 1:1 and a size ratio of the transistor M6and the transistor M7is 1:1, a voltage drop due to the resistor R1having a resistance value R1is equal to R1×α×ILoad. By using a comparator COMP1, the voltage drop is compared to a reference voltage VREF1that imparts a threshold of an overcurrent to thereby detect the overcurrent.

A positive input terminal of the comparator COMP1is connected to a connection point between the resistor R1and the drain of the transistor M7and a voltage due to the voltage drop of the resistor R1is applied. A negative input terminal of the comparator COMP1is connected to the reference potential point via the reference voltage source VREF1and the reference voltage VREF1is applied. The comparator COMP1outputs a result of comparing two inputs as a current detection signal from an output terminal. In a ease of R1×α×ILoad>VREF1, comparison result becomes a high level. The comparison result becomes the high level, and thereby the comparator COMP1is capable of detecting that the current ILoad becomes larger than VREF1/(R1×α) (overcurrent). Specifically, VREF1/(R1×α) is an overcurrent determination threshold determining whether or not the current ILoad is an overcurrent.

FIG. 3is a waveform diagram describing operations of the comparator COMP1. A horizontal axis represents the current ILoad and a vertical axis represents the current detection signal from the comparator COMP1. In a case in which the current ILoad is equal to or smaller than the overcurrent determination threshold, the current detection signal becomes a low level (LO). On the other hand, in a case in which the current ILoad is larger than the overcurrent determination threshold, the current detection signal becomes the high level (HI).

Meanwhile, a ground fault may occur in the output terminal VOUT. As a result, the source of the transistor M1is 0 V and the positive input terminal of the operational amplifier AMP1is 0 V. In this state, the source of the transistor M2is also required to be 0 V in order to accurately detect the current ILoad. However, the transistor M3is turned on in a relatively small voltage Vsd. On the other hand, the voltage Vgs for turning on the transistor M4is relatively large. Accordingly, in a source potential of the transistor M3(source potential of the transistor M2), a minimum potential is restricted by the voltage Vgs of the transistor M4and the minimum potential is incapable of being reduced up to 0 V. In the result, a current flowing through the source of the transistor M2is not u times the current ILoad and the current ILoad is incapable of being accurately detected.

FIG. 4is a timing chart describing the above problem. Note that, in the following descriptions, in the transistors, the drain-source voltage is set to the voltage Vgs, a drain-source voltage is set to a voltage Vds, a current flowing through the drain-source path is set to a current Ids, and a threshold voltage is set to a voltage Vth. Further, a sign attached to the transistor is enclosed in parentheses, and thereby showing a characteristic value of any transistor. Further, in the following descriptions, at the time of the ground fault, the ground fault occurs in the output terminal VOUT and at the time of a non-ground fault, the ground fault does not occur in the output terminal VOUT. InFIG. 4, a horizontal axis represents a time, and a time change in the current ILoad, the drain-source voltage Vgs, the voltage drop VR1in the resistor R, and the current detection signal in the COMP1are shown in this order from the top.

An example in which the current ILoad fluctuates at the time of the non-ground fault is shown. When the current ILoad is larger than the overcurrent determination threshold, an output of the comparator COMP1is changed from the low level to the high level. In a case in which the current ILoad is equal to or smaller than the overcurrent determination threshold, the output of the comparator COMP1becomes the low level.

At the time of the non-ground fault, when the current ILoad is larger than the overcurrent determination threshold, the comparator COMP1outputs the current detection signal at the high level. At the time of the non-ground fault, the voltage Vgs (M1) in the transistor M1coincides with the voltage Vgs (M2) in the transistor M2.

On the other hand, when the ground fault occurs in the output terminal VOUT, the source of the transistor M1is 0 V, the voltage Vgs (M1) becomes large, and the current ILoad becomes larger than the overcurrent determination threshold. At this time, a value of the voltage Vgs (M2) is equal to a value lower than the value of the voltage Vgs (M1) by the voltage Vgs (M4) (second stage ofFIG. 4). In the result, a current to be detected by the transistor M2is reduced and a voltage drop due to the resistor R1is equal to or lower than the voltage VREF1(third stage ofFIG. 4). Specifically, at the time of the ground fault, the output of the comparator COMP1remains the low level as it is and the overcurrent is incapable of being detected (fourth stage ofFIG. 4).

To solve the above problem, according to the present embodiment, a circuit2that performs a ground fault detection in the current detection circuit and an OR circuit OR1that calculates a logical OR of outputs of the circuit2and the comparator COMP1are adopted. At the time of the non-ground fault, the overcurrent is detected by the output of the comparator COMP1and, at the time of the ground fault, the overcurrent is detected by an output of the circuit2.

InFIG. 1, between the positive input terminal (hereinafter, referred to as a node N) of the operational amplifier AMP1and a connection point between the source of the transistor M1and the output terminal VOUT, a diode D1is provided. An anode of the diode D1is connected to the output terminal VOUT and a cathode of the diode D1is connected to the node N. Further, the node N is connected to the reference potential point via a current source IREF1. Further, an anode of a diode D3is connected to the power supply terminal VCC1through a source-drain path of a P-type MOS transistor M8and a cathode of the diode D3is connected to the node N.

The current supply IREF1, the transistor M8, and the diode D1are provided to detect an occurrence of the ground fault. At the time of the ground fault, the output terminal VOUT is turned out 0 V and thereby the diode D1turned off. A current generated by the current source IREF1, that is, a current between the power supply terminal VCC1and the node N flows in the reference potential point through the source-drain path of the transistor M8and the diode D3. Specifically, the occurrence of the ground fault is detected by a current flowing through the transistor M8.

However, in order to accurately detect the current ILoad flowing through the transistor M1, the transistor M8may be in an off state. To solve the above problem, in a case in which the current ILoad is equal to or smaller than the overcurrent determination threshold at the time of the non-ground fault, the transistor M8is set to be turned off. Specifically, at the time of the non-ground fault, in a case in which the current ILoad is the overcurrent determination threshold VREF1/(R1×α), a voltage Vth (M8) of the transistor M8is set to a value larger than a maximum drain-source voltage (Vds (M1) . . . max) of the transistor M1. In a case in which the conditions are satisfied, when the current ILoad equal to or smaller than the overcurrent determination threshold is supplied at the time of the non-ground fault, the transistor MB is necessarily turned off.

Note that, in an example ofFIG. 1, only the diode D3is connected between a drain of the transistor MB and the node N. Further, in a case in which Vds (M1)_max<Vth (M8) does not hold, m (m is an integer equal to or larger than one) diodes are additionally connected and Vds (M1)_max<Vth (M8)+VF (add)×m is caused to hold. The voltage VF (add) is a forward voltage of a diode to be added.

The operational amplifier AMP1controls an output so that the positive input terminal and the negative input terminal have the same potential. Since the diode D1is provided between the source of the transistor M1and the node N, a diode D2is also provided between the source of the transistor M2and the negative input terminal of the operational amplifier AMP1.

Note that a current value of the current source IREF1is set to IREF1<<ILoad. By adding the current source IREF1, the current Ids (M1) is changed into a sum current of the current ILoad and the current IREF1. Since the current IREF1is sufficiently small in comparison with the current ILoad, a change in the voltage Vds (M1) is extremely small and a detection error of the current ILoad is negligible.

Further, in order to enhance a detection accuracy of the overcurrent, in a case in which the current ILoad is near to the overcurrent determination threshold, the source potential of the transistor M1may be caused to coincide with the source potential of the transistor M2by the operational amplifier AMP1. To solve the above problem, in a case in which the current ILoad has the overcurrent determination threshold, a forward voltage of the diode D1is caused to coincide with a forward voltage of the diode D2. Specifically, in a case in which the current ILoad of the overcurrent determination threshold is supplied, the current IREF1is set to a value approximately equal to the current Ids (M2) (=α×ILoad) of the transistor M2.

A gate of the transistor M8is connected to the drain of the transistor M8, and at the same time is also connected to a gate of a P-type MOS transistor M9with which the transistor M8constitutes a current mirror circuit. A source of the transistor M9is connected to the power supply terminal VCC1and a drain of the transistor M9is connected to the reference potential point through a source-drain path of a P-type MOS transistor M10, a drain-source path of an N-type MOS transistor M11, and a resistor R2.

A voltage VREF2is applied to a gate of the transistor M10. Further, a gate of the transistor M11is connected to the power supply terminal VCC3. The power supply terminal VCC3is connected to the reference potential point through the current source IREF2that configures an active load, and a drain-source path of an N-type MOS transistor M12. A gate of the transistor M12is connected to a connection point between a source of the transistor M11and the resistor R2. Note that a resistor may be adopted in place of the current source IREF2.

By the current mirror circuit configured by the transistor M8and the transistor M9, the current IREF1flowing through the transistor M8flows through the resistor R2from the transistor M9via the transistor M10and the transistor M11. When a size ratio of the transistor M8and the transistor M9is set to 1:1 and a resistance value of the resistor R2is set to R2, a voltage drop due to the resistor R2is equal to a voltage IREF1×R2. A threshold Vth (M12) of the transistor M12is set to IREF1×R2>Vth (M12) to thereby turn on the transistor M12.

When the transistor M12is turned off, a drain of the transistor M12is changed into the high level by the power supply voltage VCC3, and when the transistor M12is turned on, the drain of the transistor M12is changed into the low level. Specifically, when the transistor M8is turned from off to on, the drain of the transistor M12is changed from the high level to the low level. A drain voltage of the transistor M12is applied to an inverter INV1. The inverter INV1inverts the drain voltage of the transistor M12and outputs the inverted drain voltage to the OR circuit OR1. By using the resistor R2, the current source IREF2, the transistor M12, and the inverter INV1, a ground fault detection result output circuit is configured.

The OR circuit Ob1outputs an output logical add of the comparator COMP1and the inverter INV1as the current detection signal.

The transistor M10configures a voltage clamp of the transistor M9. Specifically, the voltage VREF2is applied to the gate of the transistor M10, and thereby the transistor M10maintains a potential of the drain of the transistor M9at a predetermined value. Further, the transistor M11is a voltage clamp of the transistor M12. Specifically, when a voltage drop of the resistor R2is extremely large, the transistor M11is turned off and acts so as to suppress the voltage Vgs (M12). Note that when there is no problem in an element withstand-voltage of the transistor M9and the transistor M12, the transistor M10and the transistor M11can be omitted.

Further, in the related technology ofFIG. 2, a large input voltage from the power supply voltage VCC1to 0 V (at the time of the ground fault) is input to the positive input terminal of the operational amplifier AMP1. On the other hand, according to the present embodiment, the positive input terminal of the operational amplifier AMP1is restricted to an input voltage from the power supply voltage VCC1to VCC1−(Vgs (M8)+VF (D3)). VF (D3) is a forward voltage of the diode D3. Accordingly, according to the present embodiment, there is also an advantage such that a differential input circuit of the operational amplifier AMP1is capable of being configured by low withstand-voltage elements.

Note that, also at the time of the non-ground fault, when the current ILoad larger than the overcurrent determination threshold is supplied, the transistor M8may be turned on. Therefore, due to a value of the resistor R2, etc., an amount of the current ILoad, or the like, the transistor M12is turned on and an output of the inverter INV1becomes the high level. However, the high level showing the overcurrent is also output from the comparator COMP1, and therefore there is no problem particularly.

Next, operations according to the present embodiment configured as described above will be described with reference toFIG. 5.FIG. 5is a timing chart describing the operations according to the present embodiment. A horizontal axis represents a time; further, represents a time change in the current ILoad, the output of the COMP1, the output of the INV1, and an output of the OR1in this order from the top.

At the time of the non-ground fault, the current ILoad is supposed to be equal to or less than VREF1/(R1×α). The overcurrent determination threshold shows VREF1/(R1×α). At the time of the non-ground fault, the current ILoad fluctuates and a period in which the current ILoad is larger than the overcurrent determination threshold is also included (first stage ofFIG. 5).

In a case in which the current ILoad is equal to or smaller than the overcurrent determination threshold, the transistor M8is turned off. Accordingly, the drain of the transistor M12is the high level and the output of the inverter INV1is the low level. Specifically, in this case, the circuit2does not exert an influence on the current detection signal.

As a result of acting so that the source potential of the transistor1471is made the same as the source potential of the transistor M2, Vds (M1)+VF (D1)=Vds (M2)+VP (D2) holds in the operational amplifier AMP1. A voltage VF (D1) and a voltage VP (D2) are a forward voltage of the diode D1and a forward voltage of the diode D2, respectively. Since the current Ids (M2) is equal to α×ILoad, a voltage drop of a voltage ILoad×R1×α occurs in the resistor R1. The voltage drop ILoad×R1×α is equal to or lower than the voltage VREF1and the output of the comparator COMP1is the low level.

On the other hand, at the time of the non-ground fault, when the current ILoad is larger than the overcurrent determination threshold, the voltage drop ILoad×R1×α in the resistor R1is higher than the voltage VREF1and the output of the comparator COMM becomes the high level. In a case in which the current ILoad is larger than the overcurrent determination threshold, the current detection signal becomes the high level.

(At Time of Ground Fault)

At the time of the ground fault, the output terminal VOUT is 0 V, the diode D1is turned off, and the voltage Vgs (M1) is increased. Then, the current ILoad is larger than the overcurrent determination threshold. As a result of turning off the diode D1, the current IREF1flows through the transistor M8. A mirror current of the current IREF1flows through the reference potential point via the transistor M10, the transistor M11, and the resistor R2from the transistor M9. The voltage drop of the voltage IREF1×R2occurs in the resistor R2and the drain of the transistor M12is changed from the high level to the low level.

Meanwhile, the output of the inverter INV1is changed from the low level to the high level (third stage ofFIG. 5). Then, the current detection signal from the OR circuit OR1becomes the high level at the time of the ground fault.

As described above, according to the present embodiment, a circuit configured to detect the ground fault is added to a current detection circuit and the current detection signal is obtained by an output of a ground fault detection circuit at the time of the ground fault. At the time of the non-ground fault, an overcurrent is detected by the output of the comparator COMP1, and at the time of the ground fault, an overcurrent is detected by the output of the inverter INV1. Thereby, the current detection signal can be accurately obtained in either a non-ground fault time or a ground fault time.