Fin etch and Fin replacement for FinFET integration

A method and device are provided for etching and replacing silicon fins in connection with a FinFET integration process. Embodiments include providing a first plurality and a second plurality of silicon fins on a silicon wafer with an oxide between adjacent silicon fins; forming a first nitride liner on an upper surface of the first plurality of silicon fins and the oxide therebetween; etching the second plurality of silicon fins, forming trenches; removing the first nitride liner; depositing a second nitride liner on an upper surface of the first plurality of silicon fins and the oxide therebetween and in the trenches; removing the second nitride liner down to the upper surface of the first plurality of silicon fins; and recessing the oxide.

TECHNICAL FIELD

The present disclosure relates to a FinFET integration process, and more particularly to a fin replacement process.

BACKGROUND

FinFet integration generally involves the formation of a “sea-of-fins” to obtain fin uniformity, which is then followed by a dry etch process that removes the fins that are not needed for the electrical circuit and/or the fins that need to be removed for other reasons, e.g., gate contacts. However, this fin removal process usually causes wide and deep trenches that are costly to fill. Further, the typical fin removal process usually requires an additional chemical mechanical polishing (CMP) step that is performed on a non-uniform wafer, which after fin recess leaves behind topography that has to be accounted for during the gate formation.

A need therefore exists for a methodology enabling removal of unnecessary fins without requiring costly trench etching and trench filling as well as producing a planar wafer as an end result.

SUMMARY

An aspect of the present disclosure is a method for etching and replacing silicon fins.

Another aspect of the present disclosure is a device including silicon fins and nitride fins.

According to the present disclosure, some technical effects may be achieved in part by a method including: providing a first plurality and a second plurality of silicon fins on a silicon wafer with an oxide between adjacent silicon fins; forming a first nitride liner on an upper surface of the first plurality of silicon fins and the oxide therebetween; etching the second plurality of silicon fins, forming trenches; removing the first nitride liner; forming a second nitride liner on an upper surface of the first plurality of silicon fins and the oxide therebetween and in the trenches; removing the second nitride liner down to the upper surface of the first plurality of silicon fins; and recessing the oxide.

Aspects of the present disclosure include forming the first nitride liner to a thickness of 50 angstroms (Å) to 100 Å. Another aspect includes forming the first nitride liner from furnace nitride or plasma-enhanced chemical vapor deposition (PECVD) nitride. Other aspects include forming the first nitride liner by depositing a nitride layer on an upper surface of the first and second pluralities of silicon fins and on the oxide therebetween; forming a photo mask on the first nitride layer on the first plurality of silicon fins and on the oxide therebetween; and etching away the nitride layer on the second plurality of fins and on the oxide therebetween. Further aspects include stripping the photo mask after etching the nitride layer. Additional aspects include dry etching the nitride layer on the second plurality of silicon fins and on the oxide therebetween. Another aspect includes dry etching the nitride liner selectively against the underlying oxide. Other aspects include etching the second plurality of silicon fins by dry etching the fins to a depth of 500 Å to 5000 Å. Further aspects include isotropically wet etching any stringers in the trenches following the dry etching of the silicon fins. Additional aspects include etching the second plurality of silicon fins by etching the silicon fins to a depth of 500 Å to 5000 Å and then isotropically wet etching any stringers remaining in the trenches following the wet etching. Further aspects include removing the first nitride liner by wet or dry etching. Another aspect includes forming the second nitride liner on the upper surface of the first plurality of silicon fins and the oxide therebetween and in the trenches to a thickness of 75 percent of a width of one of the plurality of silicon fins. Other aspects include forming the second nitride liner from furnace nitride. Further aspects include removing the second nitride liner down to the upper surface of the first plurality of silicon fins by dry etching or CMP the second nitride liner. Another aspect includes recessing the oxide by atomic layer etching or wet etching the oxide to a depth of 200 Å to 400 Å. Other aspects include recessing the oxide by etching with high selectivity to silicon and nitride.

Another aspect of the present disclosure is a device including a silicon wafer including a plurality of silicon fins, a plurality of nitride fins, and an oxide filling a portion of a recess between each pair of adjacent fins. Aspects of the present disclosure include an upper surface of the silicon fins and an upper surface of the nitride being coplanar.

Another aspect of the present disclosure is a method including: providing first and second pluralities of silicon fins and an oxide between adjacent pairs of fins on a silicon wafer; forming a furnace nitride to a thickness of 50 Å to 100 Å on an upper surface of the first and second pluralities of silicon fins and on the oxide therebetween; forming a photo mask on the furnace nitride on the first plurality of fins and on the oxide therebetween; dry etching the furnace nitride on the second plurality of fins and on the oxide therebetween, exposing the second plurality of fins; dry etching the exposed second plurality of silicon fins to a depth of 500 Å to 5000 Å, forming trenches; wet etching any stringers remaining in the trenches following the dry etching; stripping the photo mask; etching the remaining furnace nitride; forming a second furnace nitride to a thickness of 75 percent of a width of one of the plurality of silicon fins on the upper surface; CMP the furnace nitride; and atomic layer etching the oxide to a depth of 200 Å to 400 Å. A further aspect includes a FinFET multi-gate transistor produced by the disclosed methods.

DETAILED DESCRIPTION

The present disclosure addresses and solves the current problem of wide, deep trenches that are costly to fill attendant upon fin removal and replacement. In addition, current processes usually require an additional CMP step that is performed on a non-uniform wafer, which after fin recess leaves behind topography that must be accounted for during the gate formation.

Methodology in accordance with embodiments of the present disclosure includes providing a first plurality and a second plurality of silicon fins on a silicon wafer with an oxide between adjacent silicon fins; forming a first nitride liner on an upper surface of the first plurality of silicon fins and the oxide therebetween; etching the second plurality of silicon fins, forming trenches; removing the first nitride liner; depositing a second nitride liner on an upper surface of the first plurality of silicon fins and the oxide therebetween and in the trenches; removing the second nitride liner down to the upper surface of the first plurality of silicon fins; and recessing the oxide.

Referring toFIG. 1, silicon fins102are formed, e.g. by etching, in a silicon wafer101. An oxide103is filled between adjacent fins102. Fins102may be formed to a width of 80 Å to 800 Å, for example 200 Å, and to a depth of 800 Å to 5000 Å. e.g. 2000 Å. The oxide103may, for example, be formed of tetraethyl orthosilicate (TEOS), high aspect ratio process (HARP) material, or spin-on dielectric (SOD) material including a densification process.

As illustrated inFIG. 2, a nitride layer201for example of furnace nitride, e.g., formed at 760° C., or PECVD nitride, is deposited on the upper surface of the silicon fins102and on the oxide103therebetween. The nitride layer201may be formed to a thickness of 50 Å to 100 Å.

Referring toFIG. 3, a photo mask301is formed on the nitride layer201, on a plurality of silicon fins102and on the oxide103therebetween. In particular, the photo mask301is formed over and protects the permanent fins, and exposes areas where fins need to be removed. The nitride layer201is then dry etched selectively against the underlying oxide103, leaving a first nitride liner201′ beneath the photo mask301, as illustrated inFIG. 4.

Referring toFIG. 5, the exposed silicon fins102are dry etched to a depth of 500 Å to 5000 Å, e.g., 2000 Å, resulting in etched silicon fins102′. By way of example, the dry etch chemistry may be a sulfur hexafluoride (SF6) based chemistry or a nitrogen trifluoride (NF3) based chemistry. The dry etch process may be followed by a short isotropic wet etch or a short silicon oxidation to remove any “stringers” that may have formed in overhanging areas in the trenches or as a result of small defects that block the dry etch process. Alternatively, rather than dry etching the exposed silicon fins102, the exposed silicon fins102may be wet etched using a nitric acid (HNO3) plus hyrdrofluoric (HF) acid or a tetramethylammonium hydroxide (TMAH).

Once the exposed fins have been etched to an appropriate depth, the photo mask301is stripped off, as illustrated inFIG. 6. Adverting toFIG. 7, the first nitride liner201′ is removed from the upper surface of the first plurality of silicon fins201, by a wet or dry etch. This avoids a step in the wafer101where the etched first nitride liner201′ was previously located.

Referring toFIG. 8, a second nitride liner801is formed on the upper surface of silicon fins102, the etched silicon fins102′, and oxide103therebetween. The second nitride liner801will completely fill the trenches above the etched silicon fins102′ and is formed above silicon fins102and oxide103to a thickness of 75 percent of a width of one of the silicon fins102. More specifically, the second nitride liner801may be formed of furnace nitride, which yields better step coverage than PECVD nitride. Moreover, removing the etched first nitride liner201′ avoids a step in the second nitride liner801.

As illustrated inFIG. 9, the second nitride liner801is removed down to the upper surface of silicon fins102by dry etching or CMP. As a result, only nitride801′ formed in the trenches on top of the etched silicon fins102′ remains.

Referring toFIG. 10, the oxide103′ is recessed to a depth of 200 Å to 400 Å by atomic layer etching or wet etching with high selectivity to silicon and nitride. As a result, both the silicon fins102and the nitride fins801′ are exposed. More specifically, the upper surface of the silicon fins102and an upper surface of the nitride fins801′ are coplanar.

The embodiments of the present disclosure can achieve several technical effects including avoiding costly trench etching and trench filling and achieving a planar surface after removal of the unnecessary fins. Embodiments of the present disclosure enjoy utility in various industrial applications as, for example, microprocessors, smart phones, mobile phones, cellular handsets, set-top boxes, DVD recorders and players, automotive navigation, printers and peripherals, networking and telecom equipment, gaming systems, and digital cameras. The present disclosure therefore enjoys industrial applicability in any of various types of highly integrated semiconductor devices including FinFETs.