Switching regulator with slope compensation independent of changes in switching frequency

Compensation for a switching regulator is attained by developing a compensation signal for a switching regulator that is independent of changes in the switching frequency. The regulator operational frequency is established in accordance with a repetitive ramp signal of constant slope and adjustable frequency. The voltage of the ramp signal is monitored and an offset signal is derived therefrom. The peak value of the ramp signal, detected during monitoring, is used to derive the offset signal. Initiation of the compensation occurs at the same duty cycle point during each switching cycle and thus is independent of switching frequency. The compensation signal may have a linear or non-linear slope.

TECHNICAL FIELD

This disclosure is related to switching regulators, and more particularly to provision of compensation during control of the switching duty cycle.

BACKGROUND

The use of current mode switching regulators to control a DC output voltage at a level higher than, lower than, or the same as an input voltage is well known. Typically, one or more switches are activated to supply current pulses via an inductor to charge an output capacitor. The output voltage level is maintained at a desired level by adjusting the on and off times of the switching pulses in accordance with output voltage and load conditions.

FIG. 1is a block diagram of a typical current mode switching regulator. Switching control circuit10may comprise any of various known controllers that provide pulse width modulated output pulses to regulate a DC output voltage VOUTat a level that may be greater than, lower than, or the same as a nominal input voltage VIN. Typically, the control circuit includes a latch, having set and reset inputs, coupled to a controlled switch that supplies switched current ISWto inductor12. Capacitor14is connected between the output VOUTand ground. Resistors16and18are connected in series between VOUTand ground. A load20is supplied from the regulator output.

The set input is coupled to clock22, which may generate pulses in response to an oscillator. During normal operation, the latch is activated to initiate a switched current pulse when the set input receives each clock pulse. The switched current pulse is terminated when the reset input receives an input signal, thereby determining the width of the switched current pulse. The reset input is coupled to the output of comparator24. An output voltage feedback signal VFBis taken at the junction of resistors16and18and coupled to negative input of error amplifier26. A voltage reference VREFis applied to the positive input of error amplifier26. Capacitor28is coupled between the output of error amplifier26and ground.

The level of charge of capacitor28, and thus its voltage VC, is varied in dependence upon the output of amplifier26. As load current increases, the output voltage, and thus VFB, decreases. As the feedback voltage VFBdecreases, VCincreases. Thus, VCis proportional to load current. VCis coupled to the inverting input of comparator24. The non-inverting input is coupled to adder30. Adder30combines signal ISW, which is proportional to the sensed switch current, with a compensation signal. Upon switch activation in response to a clock set signal, switch current builds through inductor12. When the level of the signal received from adder30exceeds VC, comparator24generates a reset signal to terminate the switched current pulse. During heavier loads, VCincreases and the switched current pulse accordingly increases in length to appropriately regulate the output voltage VOUT.

For normal regulator operation at duty cycles of fifty percent or higher, compensation is needed in the switching control to avoid sub-harmonic oscillation. A typical compensation approach is termed “slope compensation,” wherein a signal of increasing magnitude is added to the current signal ISW, or subtracted from the signal VC, during each switching cycle.FIG. 2is a circuit diagram of a prior art slope compensation generator that may be input to adder30to modify the current signal applied to the non-inverting input of comparator24. The output of the circuit is a current signal Sx, corresponding to the current in the series circuit path of transistor32, resistor (R)34and voltage bias (VB) source36. The base of transistor32is coupled to the output of unity gain buffer amplifier38. The positive input of amplifier38is coupled to receive an oscillator generated ramp signal Vramp. The negative input of amplifier38is coupled to the junction between transistor32and resistor34.

FIG. 3is a simplified waveform diagram illustrative of the compensation function of the circuit ofFIG. 2. The Vramp signal is a sawtooth format signal that is generated at the beginning of each clock cycle and extends at linear slope to the end of the cycle, corresponding to one hundred percent duty cycle. As an example, the Vramp magnitude may vary between zero and one volt. Transistor32begins conduction at a percent duty cycle point Ts at which Vramp overtakes the fixed voltage VB. As compensation is needed at fifty percent duty cycle operation or greater, VB typically is arbitrarily chosen at one half the value of the maximum Vramp level, or one half-volt in the present example. Ts thus will be at fifty percent duty cycle. As Vramp continues to increase after point Ts, the base signal applied to transistor32increases and, thus, the output current Sx increases linearly to a maximum Smax at the end of the switching cycle. Sx is determined by (Vramp-VB)/R. The compensation curve Sx starting point Ts is thus determined by VB, and its slope is determined by R. In this example, Ts occurs at fifty percent of the switching cycle at the oscillator operating frequency, regardless of the actual switch duty cycle. Compensation is provided throughout an operational range of fifty to one hundred percent switch duty cycle.

FIG. 4is a circuit diagram of a typical oscillator circuit used for producing the Vramp signal. Constant current source102is connected in series with capacitor104. Coupled across capacitor104is the series arrangement of controlled switch106, shown schematically, and constant current source108. Switch106assumes a closed, or conductive, state in response to a high logic level output of comparator110. The positive input of comparator110is coupled to the junction between constant current source102and capacitor104. The negative input of comparator110is coupled to the series arrangement of resistor112and voltage reference threshold source114. Transistor116is coupled in parallel with resistor112and source114.

With switch106in the open state as shown, charge is applied to capacitor104to build up its voltage at a constant rate until it exceeds the voltage at the negative input, Vn, of the comparator110. At that point, the comparator outputs a signal to activate the switch106to a conductive state, thereby coupling the capacitor to constant current source108to discharge capacitor104. As the current source108is much greater than the current source102, and the comparator is configured with sufficient hysteresis, the capacitor is quickly discharged to its base minimum level voltage. The voltage at capacitor104produces the Vramp signal. In the absence of application of an activation signal to the base of transistor116, the circuit operates as a free running oscillator. The charge and discharge cycle is repeated continuously at a constant frequency dependent upon the time necessary for the voltage at capacitor104to rise from its base level to its threshold level of reference source114. The time required for capacitor discharge is negligible.

The oscillator may be controlled to operate at a higher frequency by application of a higher frequency synchronous signal to the base of transistor116. When a synchronizing pulse is applied to the base of transistor116, the negative input to comparator110is coupled to ground, causing the immediate closure of switch106and discharge of capacitor104by current discharge source108. Upon discharge of the capacitor to the base voltage level of Vramp, the comparator ceases its output signal, switch106again transitions to an open state, and charge is again applied to capacitor104to build the Vramp signal. The circuit thus will provide a Vramp signal output at the higher frequency with decreased charging period for capacitor104.

The waveforms ofFIGS. 5A-5Dillustrate operation in both the free running and synchronized oscillator modes. Waveform (a) represents an external voltage signal, Vsync, applied to the base of transistor116. Waveform (b) represents the voltage at the negative input to comparator110. Waveform (c) represents the Vramp signal. The Vramp signal is applied to the positive input of amplifier38ofFIG. 2. Waveform (d) represents the compensation signal Vcomp. For comparison with the waveform ofFIG. 3, it is assumed that the voltage threshold source114is one volt and that the base line level is zero volt. 100 kHz is taken as an example of the free running oscillator frequency.

Between time t0and t2, Vsync (waveform a) is zero, whereby the circuit operates as a free running oscillator at 100 kHz. Vramp (waveform c) exhibits a constant slope from a value of 0.0 volt at t0to the threshold 1.0 volt at t1. The slope is dependent on the value of capacitor104and constant current charge source102. Vn (waveform b) drops to 0.0 volt level from 1.0 volt during the brief period of transition of Vramp from its maximum to minimum levels. The compensation signal, Vcomp, is initiated when the Vramp signal attains the voltage VB of the reference source32. This point is at fifty percent duty cycle, as described above with respect toFIGS. 2 and 3.

Waveforms (a)-(d) repeat as described until time t2, when a Vsync signal having a frequency of 150 kHz is applied to the base of transistor116. At that time, the voltage Vn at the negative input to comparator110is forced low, the Vramp signal attains the 0.0 volt level and then begins to increase. As there has been no change to the constant current charge source102or to the capacitor104, the slope of Vramp remains the same. At time t3, the next Vsync pulse occurs, again forcing Vn low to terminate the Vramp pulse. As the Vsync frequency of 150 kHz is greater than the 100 kHz frequency at free running operation, the time during which charge can build on capacitor104, i.e., between t2and t3, has decreased. The maximum value of the Vramp signal is 0.66 volt.

The effect of application of the 150 kHz Vramp signal to the positive input of amplifier38on compensation signal Vcomp is as follows. As the voltage bias (VB) source36remains at 0.5 volt and the slope of Vramp remains the same, the length of time required to initiate the compensation signal in each cycle remains the same. The percent duty cycle point of Ts is derived as follows: Ts/0.5 volt=100%/0.66 volt; Tx=(0.5/0.66)(100%)=76%. As illustrated in the waveform ofFIG. 5D, Ts has shifted from the fifty percent duty starting point for 100 kHz frequency operation to seventy six percent duty starting point for 150 kHz frequency operation. The regulator loses slope compensation between fifty and seventy six percent duty cycle and thus becomes susceptible to sub-harmonic oscillation in that duty cycle range. If a higher frequency synchronization signal is applied to the oscillator, an even greater shift of Ts will occur. Moreover, as the slope of the compensation signal remains independent of operating frequency, Smax will attain only a small magnitude.

As VCis an indication of load, it can be monitored by internal circuitry, not shown, to detect light load conditions. In response to VCreaching a predetermined light load condition threshold, the operation can be changed to a “sleep mode,” in which some circuit elements can be deactivated to conserve power. At low duty cycles at which no compensation signal is produced, the level of VCcorresponds to the amount of switch and regulator output currents. At higher duty cycles at which compensation signals are produced, the level of VCcorresponds to a load level less than the actual load level. As the compensation signal increases with higher duty cycles, the load level correspondence decreases. For VCto be a reasonably accurate indicator of load level, the slope compensation Sx should be at the minimum signal magnitude necessary for compensation.

To obtain adequate compensation, a compensation signal of greater magnitude is required at increased duty cycles. The slope of the linear compensation curve thus is typically set to provide the appropriate magnitude for the maximum duty cycle operation. While this curve satisfies the maximum duty requirement, it over-compensates as duty cycle operation decreases to fifty percent. As the minimum necessary compensation between fifty percent and one hundred percent duty cycle operation is not linear, VCcontains an unnecessary offset component through much of that range.

The need thus exists for a slope compensation arrangement that provides adequate slope compensation at fifty percent duty cycle and above for all operating frequencies. The need also exists to avoid over-compensation.

DISCLOSURE

The above-described needs of the prior art are fulfilled, at least in part, by developing a compensation signal for a switching regulator that is independent of changes in the switching frequency. The regulator operational frequency is established in accordance with a repetitive ramp signal of constant slope and adjustable frequency. The voltage of the ramp signal is monitored and an offset signal is derived therefrom. A compensation signal is derived based on the ramp signal and the derived offset signal. A duty cycle control signal for the regulator is dependent in part on the developed compensation signal. The peak value of the ramp signal, detected during monitoring, is used to derive the offset signal. Initiation of the compensation occurs at the same percent duty cycle point during each switching cycle and thus is independent of switching frequency. The compensation signal may have a constant slope, or an exponentially increasing slope, and a time duration that is proportional to the difference between the ramp signal and the derived offset signal. Preferably, the derived offset signal is proportional to the detected peak value.

In an exemplified implementation, a compensation circuit is coupled to an input of a switching controller for terminating a switching pulse during each switching cycle. The compensation circuit is configured to output a compensation signal that varies as a function of changes in regulator switching frequency while maintaining a constant percent duty cycle. A peak detector is coupled to a ramp generator. The ramp generator may have an input coupled to an adjustable frequency synchronization signal, thereby to set the frequency of the repetitive ramp signal to the frequency of the synchronizing signal. A peak voltage hold circuit is coupled to the peak detector. Preferably a voltage divider circuit is coupled between the peak voltage hold circuit and a negative input of an amplifier. A summer, coupled in series with the output circuit, has inputs for receiving a signal from the voltage divider and a voltage reference. An output of the summer is fed to the negative input of the amplifier. A positive input of the amplifier is coupled to the ramp generator. An output circuit comprising a transistor, having a control terminal coupled to the amplifier output, and an impedance coupled in series with the transistor provides the compensation signal to the switching regulator.

The series arrangement may further include a first multiplier circuit coupled to the transistor and configured to output a signal that is a function of the peak level of the ramp signal and a second multiplier circuit coupled to the first multiplier circuit and configured to output a signal that is proportional to the square of the signal output by the first multiplier circuit.

DETAILED DESCRIPTION

An underlying concept of the present disclosure is based on the realization that loss of slope compensation when the oscillator frequency is increased can be avoided by maintaining the start of the compensation signal Sx at a constant duty cycle Ts.FIG. 6is a diagram of an implementation80for regulating the compensation signal accordingly. The output of oscillator100is coupled to peak detector120as well as to the positive input of amplifier38. The negative input of amplifier38is coupled to a junction between transistor32and resistor34. Connected in parallel between the output of peak detector120and ground are capacitor122, “droop” current source124, and the series arrangement of unity gain amplifier buffer126, resistor128and resistor130. Unity gain amplifier buffer132is coupled to a junction resistor128and resistor130. Summer134has one input coupled to the buffer132, another input coupled to a reference voltage Vtl, and an output coupled to resistor34. Peak detector120outputs the peak voltage of oscillator100, Vhold, which is held temporarily by capacitor122. Buffers126and132avoid loading on the capacitor voltage.

The compensation signal Sx is initiated, at time Ts, when amplifier38outputs a signal to activate transistor32. Ts occurs when the Vramp signal at the positive input overtakes the voltage VB applied at the negative input. The voltage VB is a function of the voltage at resistor130, and thus of the voltage Vpeak. The voltage at the output of buffer132can be calculated as follows:
V132=(Vhold*R130)/(R128+R130); whereinVhold=Vpeak.  (1)
The voltage (VB) at the output of summer134is thus:
VB=V132+Vtl=(Vpeak*R130)/(R128+R130)+Vtl;(2)
wherein Vtl is the base line threshold voltage. In keeping with the earlier described example, the base line voltage for the oscillator Vramp signal is selected to be zero volt; thus Vtl=0.

Ts⁢⁢(in⁢⁢percent⁢⁢duty⁢⁢cycle)=(VB-Vtl)/(Vpeak-Vtl)=(Vpeak*R⁢⁢130)/(R⁢⁢128+R⁢⁢130)⁢(Vpeak)=R⁢⁢130/(R⁢⁢128+R⁢⁢130).(3)
Ts is thus a constant, determined by values of the resistors R128and R130.

FIGS. 7A-7Dare diagrams of waveforms illustrating operation with the compensation arrangement ofFIG. 6. The voltage threshold levels and charging rate are taken to be the same as the earlier described example for purpose of comparison. The Vsync and Vramp waveforms are the same as those ofFIGS. 5A-5D. The peak oscillator output voltage Vpeak changes with changes in frequency, i.e., 1.0 volt at 100 kHz and 0.66 volt at 150 kHz. As shown in the Vcomp waveform, the start Ts of the compensation signal in each cycle, at both frequencies is fifty percent. Compensation is thus provided at every percent duty cycle above fifty percent at all frequencies.

FIG. 8is a circuit diagram of a peak detector120that may be employed in the circuit of FIG.6. Current source140is coupled in series with PNP transistor142. NPN transistor144is coupled in series with current source146. The oscillator Vramp signal is applied to the base of transistor142. The emitter of transistor142is coupled to the base of transistor144. The emitter of transistor144is coupled in series with controlled switch148and the Vhold terminal of capacitor122. A positive input of comparator150is supplied by the Vramp signal. A negative input of comparator150is coupled to a junction between switch148and capacitor122.

The voltage at the emitter of transistor142is Vramp plus the base-emitter voltage. The voltage at the emitter of transistor144is Vramp plus the base-emitter voltage of transistor142minus the base-emitter voltage of transistor144, i.e., substantially equal to Vramp. The transistors142and144are buffers for level shift. When switch148is closed, Vhold will be forced to equal Vramp. When switch148is open, Vhold is isolated from Vramp and is held by capacitor122. Switch148is activated when the voltage at the positive input of comparator150exceeds the voltage at the negative input. Vhold will then follow the increase in Vramp. When Vramp goes lower than Vhold, comparator148will turn off switch148.

Vhold thus maintains the peak of the Vramp signal, Vpeak, until a higher peak is reached. If, for example, the oscillator reverts from synchronized operation at 150 kHz to free running 100 kHz operation, the increase in Vpeak will be detected and the compensation signal Sx adjusted to maintain Ts at fifty percent duty cycle. If frequency is increased, Vpeak will decrease. The provision of the “droop” current source124(FIG. 6) in parallel with capacitor122permits discharge of the capacitor at an appropriate rate to detect a lower Vpeak. In response to the lower value of Vhold, Sx will be adjusted to maintain the percent duty cycle, Ts, constant.

FIG. 9is a circuit diagram of another peak detector120that may be employed in the circuit ofFIG. 6. The Vramp signal is applied to a positive input of unity gain buffer amplifier150. Coupled in series with the output of amplifier150are diode152and the Vhold terminal of capacitor122. The Vhold terminal is coupled to the negative input of amplifier150. Blocking diode152allows flow of amplifier output current only when Vramp is higher than Vhold. When Vramp is higher than Vhold, the diode will be forward biased and Vhold will follow Vramp. When Vramp goes lower than Vhold, the diode will be reversed biased and Vpeak will be held until a higher peak is produced or until the discharge of capacitor112by “droop” current source124brings Vhold lower than Vramp.

FIG. 10is a diagram of a variation of the slope compensation arrangement ofFIG. 6. TheFIG. 6implementation80is shown by the elements surrounded by a dashed outline. The linear slope signal Sx output therefrom is not directly applied as the compensation signal input to adder30. A first multiplier160receives the signal Sx and multiplies that signal by the factor Vth/Vpeak to compensate the reduction in Vpeak that occurs with increased frequency. Thus, while block160is designated a multiplier inFIG. 10, it performs the function of dividing Vth by Vpeak and multiplying the result by Sx. Sx1, the output of block160is Sx * (Vth/Vpeak). Sx1is applied to a second multiplier180to produce an output Sx2. The function of block180is multiply Sx1by itself, the result divided by a constant Iconst. The output Sx2is (Sx*Vth/Vpeak)2/Iconst. Sx2is applied as the compensation signal input to adder30.

Circuits that may be utilized in the multipliers160and180are illustrated inFIG. 11. The output Sx of the compensation circuit80ofFIG. 10, which has a linear slope characteristic, is mirrored by transistors162and164. Connected in series between Vcc and ground is the series path including transistors164and166. A parallel circuit path, comprising transistor168and current source170is also connected between Vcc and ground. Current source170is proportional to Vth. The base of transistor168is connected to the junction of transistors164and166. The base of transistor166is connected to the junction of transistor168and current source170. Transistor172is connected between Vcc and current source174. Current source174is connected to the buffer126ofFIG. 10and thus is proportional to Vpeak. The base of transistor172is also connected to the junction of transistors164and166. Transistor178and176are connected in series across Vcc and ground. The base of transistor176is connected to the junction of transistor172and current source174. The current through transistor178is the output Sx1of multiplier circuit160.

Sx1is mirrored by transistor182in multiplier circuit180. Connected in series between Vcc and ground are transistors182,184and186. The base and collector of each of transistors184and186are connected together. Connected in series between Vcc and ground are transistor188and constant current source190. The base of transistor188is connected to the junction of transistors182and184. The junction of transistor188and current source190is coupled to the base of transistor192. The current through transistor192is the output Sx2of multiplier circuit180that is applied to the adder30as a compensation signal.

Circuits160and180operate as follows, wherein VBE represents base to emitter voltage; Vt is the thermal voltage of a bipolar resistor; Ic is the collector current of a bipolar transistor; Is is the saturation current of a bipolar transistor and proportional to transistor size; Ie is emitter current; and Rx is an arbitrarily assigned resistor, to convert voltage to current. The functional operation of multiplier160is performed by transistors166,168,172and176. The voltage at the collector node of transistor166, is represented as follows:
Vc166=VBE168+VBE166=VBE172+VBE176
As the base to emitter voltage (VBE)=Vt In (Ic/Is), the above relationship becomes:
Vtln(Ic168/Ic168)+Vtln(Ic166/Ic166)=Vtln(Ic172/Ic172)+Vtln(Ic176/Ic176)
The transistors166,168,172and176may be chosen to be of the same size so that Is of all of these transistors are equal. Thus:
(Ic168)*(Ic166)=(Ic172)*(Ic176); and
Ic176=[(Ic168)*(Ic166)]/Ic172
Since Ic166=Sx, Ic168=Vth/Rx, and Ic172=Vpeak/Rx, and Ic176=Sx1, then:
Sx1=Sx*(Vth/Vpeak)
The functional operation of multiplier180is performed by transistors184,186,188and192. Using the same analysis applied above for multiplier160, the current of transistor192is:
Ic192=[(Ic184)*(Ic186)]/Ic188
Since Ic184=Ic186=Sx1, Ic188=Iconst, and Ic192=Sx2, then:
Sx2=(Sx1)2/Iconst

FIG. 12is a waveform diagram illustrating the signals Vramp, Sx, Sx1and Sx2for the free running oscillator mode and the synchronized oscillator mode, comparable to the conditions illustrated inFIGS. 5A-5D. The left hand portion of the waveform, designated by “a”, depicts a free running 100 kHz frequency operation with Vpeak at one volt. The right hand portion, designated by “b”, depicts a synchronized 150 kHz frequency operation with Vpeak at 0.66 volt.

At 100 kHz operation, Vpeak is equal to Vth and the signals Sxaand Sx1aare equal with linear slope. Sx2ahas an exponential characteristic instead of a linear slope. Tsais at fifty percent duty cycle. At 150 kHz operation, Vpeak is no longer equal to Vth. Sxband Sx1bhave linear, but unequal, slopes. Sx2bhas an exponential characteristic. Tsbis at fifty percent duty cycle. As evident from these waveforms for the compensation circuit ofFIGS. 10 and 11, the start, of the compensation signal Ts in each cycle is maintained at fifty percent. Compensation is thus provided at every percent duty cycle above fifty percent at all frequencies. As the slope of the compensation signal Sx2is non-linear, it can satisfy maximum duty cycle requirements without over-compensating at duty cycles closer to fifty percent. The signal VCis thus a reliable indicator of load current at all duty cycles.

In this disclosure there are shown and described only preferred embodiments of the invention and but a few examples of its versatility. It is to be understood that the invention is capable of use in various other combinations and environments and is capable of changes or modifications within the scope of the inventive concept as expressed herein. The principles of the invention are applicable to a variety of voltage regulators, including buck, boost, and buck-boost regulators. By appropriate selection of the parameters of the circuit elements of the compensation circuit and the oscillator circuit, and the operating voltage levels, the slope of Sx and its onset at a constant duty cycle can be defined. If, for example, the use of a particular regulator would find more advantageous use with a compensation signal of a different slope characteristic, or at a constant onset Tx percent duty cycle level other than fifty percent, these ends are attainable within the concepts of the present disclosure.