Semicondutor memory device and memory system including the same

A semiconductor memory device may include a cell array comprising a plurality of memory cells, each memory cell connected to a word line and a bit line, the cell array divided into a plurality of blocks, each block including a plurality of word lines, the plurality of blocks including at least a first defective block; a nonvolatile storage circuit configured to store address information of the first defective block, and to output the address information to an external device; and a fuse circuit configured to cut off an activation of word lines of the first defective block.

CROSS-REFERENCE TO RELATED APPLICATIONS

This U.S. non-provisional patent application claims priority under 35 U.S.C. §119 to Korean Patent Application No. 10-2013-0137082, filed on Nov. 12, 2013, the entire contents of which are hereby incorporated by reference.

BACKGROUND

The present disclosure herein relates to a semiconductor memory device, and more particularly, to a semiconductor memory device managing a bad block and a memory system including the same.

The operating speeds of semiconductor memory devices constituting electronic systems are increasing. As integration of a semiconductor memory device increases, the number of memory cells that are integrated in a same area also increases. For example, in the case of dynamic random access memory (DRAM), as integration and performance are improved, yield is relatively decreased. In the case where failed cells are detected by a memory block unit, the failed cells are typically not easily repaired and thereby the DRAM including the failed cells is often rejected and not used.

SUMMARY

Exemplary embodiments provide a semiconductor memory device. The semiconductor memory device may include a cell array comprising a plurality of memory cells, each memory cell connected to a word line and a bit line, the cell array divided into a plurality of blocks, each block including a plurality of word lines, the plurality of blocks including at least a first defective block; a nonvolatile storage circuit configured to store address information of the at least one defective block, and to output the address information to an external device; and a fuse circuit configured to cut off an activation of word lines of the first defective block.

Other exemplary embodiments provide a memory system. The memory system may include a semiconductor memory device comprising a plurality of blocks including at least a first defective block, each block including a plurality of word lines, and the semiconductor memory device that stores information of the first defective block; and a host to receive information of the first defective block from the semiconductor memory device, and to access the semiconductor memory device based on the information of the first defective block. The semiconductor memory device cuts off an activation of word lines corresponding to the first defective block.

Still other exemplary embodiments provide a memory system. The memory system may include a memory device and a host. The memory device includes: a memory cell array including a plurality of memory cells each connected to a word line and a bit line, and divided into a first set of blocks, and a second set of blocks that includes at least a first defective block, each block including a plurality of word lines; and a row decoder configured to inactivate word lines of the second set of blocks. The first and second sets of blocks correspond to row addresses. The host is configured to receive address information of the second set of blocks, and access the memory device based on the address information.

DETAILED DESCRIPTION OF THE EMBODIMENTS

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the disclosure. As used herein, the singular terms “a,” “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items. Expressions such as “at least one of,” when preceding a list of elements, modify the entire list of elements and do not modify the individual elements of the list.

Throughout the specification, it will also be understood that when an element is referred to as being “connected to” another element, it can be directly connected to the other element, or intervening elements may also be present. Similarly, it will also be understood that when an element is referred to as being “on” another element, it can be directly on the other element, or intervening elements may also be present. In contrast, the term “directly” means that there are no intervening elements. It will be further understood that the terms “comprises,” “comprising,” “includes” and/or “including,” when used herein, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

Unless the context indicates otherwise, terms such as “same,” “planar,” or “coplanar,” as used herein when referring to orientation, layout, location, shapes, sizes, amounts, or other measures do not necessarily mean an exactly identical orientation, layout, location, shape, size, amount, or other measure, but are intended to encompass nearly identical orientation, layout, location, shapes, sizes, amounts, or other measures within acceptable variations that may occur, for example, due to manufacturing processes. The term “substantially” may be used herein to reflect this meaning.

FIG. 1is a block diagram illustrating a bad block in accordance with an exemplary embodiment. Referring toFIG. 1, a semiconductor memory device includes a bad block12designated in a cell array10. Memory cells included in the bad block12are set to be access-inhibited when necessary.

The cell array10includes a plurality of memory cells MC arranged along one or more rows and columns. Each memory cell MC may include a cell capacitor Cc and a selection transistor ST. A gate and a drain of the selection transistor ST are connected to a word line WL and a bit line BL respectively. A selection structure of the memory cells may be repeatedly formed by a word line WL unit. One word line WL corresponds to one row. Thus, one word line can be selected by one row address.

The cell array10may include the bad block12. The bad block12may include a plurality of successive rows RA0˜RA1(e.g., 0000-1111). The bad block12has a row address range corresponding to at least one block. The rows RA0˜RA1designated as the bad block12have a row address range corresponding to at least one block. For example, the bad block includes one or more bad rows and a bad row includes at least one bad cell. One block may correspond to an area in which a sub word line driver SWD and a bit line sense amplifier BLSA cross each other.

In one embodiment, an access to the bad block12may be cut off. Address information of the bad block12may be provided to an external device (e.g., a controller or a host). Thus, an access to the bad block12from the outside can be inhibited. Moreover, when a periodic internal access operation is performed like a self-refresh operation, activation of word lines corresponding to the bad block12may also be inhibited. A fuse circuit may be added to provide a structure and functionality for that.

FIG. 2is a block diagram illustrating a selection method of a bad block in accordance with exemplary embodiments. Referring toFIG. 2, a cell array of a semiconductor memory device includes a plurality of blocks arranged along a row and a column.

For example, a defect20exists in a memory cell in a block, a range of row addresses RA0˜RA1associated with a corresponding block may be designated as a bad block BB. The defect20that occurs in a memory cell array may correspond to one row, but it may be a large-scale defect which is difficult to be repaired through a row redundancy scheme. The defect20may be, for example, a short among a plurality of word lines caused by a particle occurring in a manufacturing process or a defect caused by a burst of a specific memory area. In this case, since excessive repair resources are generally consumed to repair all the word lines using a row redundancy method, it is uneconomical.

A defect30shows an example of a defect for which at least two blocks adjacent to each other along a column direction and a row direction are processed to be a bad block BB. For example, a range of row addresses RA2˜RA3may be designated as a bad block BB by a defect of a control circuit or a bit line sense amplifier BLSA being disposed in adjacent areas of the blocks. A defect40shows an example of a defect that exists in a sub word line driver SWD or a global word line. If a problem occurs in a function of a control line for driving a sub word line driver SWD or in a function of a sub word line, at least two adjacent blocks covered by the sub word line driver SWD may be processed to be defective. Thus, in this case, a range of row addresses RA4˜RA5associated with a corresponding block may be designated as a bad block BB.

Examples of bad block BB were described above but the bad block BB is not limited to those examples. A specific row address range of a cell array may be designated as a bad block BB as a result of various defects besides those examples.

FIG. 3is a block diagram illustrating a semiconductor memory device in accordance with an exemplary embodiment. Referring toFIG. 3, in the case that a bad block row address BBRA corresponds to a bad block BB, a semiconductor memory device100can cut off an activation of word lines designated as a bad block BB. To perform that function, the semiconductor memory device100may include, for example, a column decoder120, a row decoder130and a fuse block140.

In the cell array110, a plurality of memory cells is connected to word lines and bit lines to be arranged in a row direction and a column direction, respectively. The cell array110may be divided into a plurality of blocks and each block includes a plurality of word lines. In the case that a defect occurs in any one block, all the rows associated with the any one block are designated as a bad block BB. Addresses of the rows designated as part of a bad block BB are designated as a bad block row address BBRA to be inhibited from an access. For example, such as during a refresh operation, an activation of word lines corresponding to a bad block BB may be cut off.

The column decoder120selects a bit line in response to a column address CA. Data input to a bit line BL selected by the column decoder120is transmitted to the cell array110. Data sensed from a bit line BL selected by the column decoder120is transmitted to an input/output buffer (not shown).

The row decoder130selects a word line of a memory cell to be accessed in response to a row address RA. The row decoder130decodes the row address RA to activate a corresponding word line. In a self refresh operation, the row decoder130can decode a row address RA being generated from an address counter (not shown) to activate a corresponding word line.

The fuse block140is programmed to cut off an access to a row of each block unit. The fuse block140may include fuse circuits BRF_0˜BRF_5for controlling an access to rows of block. For example, information about whether or not an access to each of block rows is possible is programmed in the fuse circuits BRF_0˜BRF_5. For example, a fuse circuit BRF_3may be blown to cut off an access to the block BLK3designated as a bad block BB. In this case, activation of all word lines included in the block BLK3is cut off. Thus, even in a refresh operation, word lines included in the block BLK3are not activated.

The fuse block140may be replaced with a fuse box performing a program operation by applying a strong current or irradiating laser, an e-fuse performing a program operation by using an electrical method, or various nonvolatile memories.

A constitution of the semiconductor memory device100was simply described above. In some embodiments, a semiconductor memory device100such as described above cuts off an access to a defective block that cannot be repaired using a row redundancy method by a bad block BB process. Reliability of an operation can be improved by the fuse block140preventing word lines of a bad block BB from being activated during, for example, a self refresh operation.

FIG. 4is a block diagram illustrating a memory system in accordance with an exemplary embodiment. Referring toFIG. 4, a memory system includes a semiconductor memory device100aand a host200a. The semiconductor memory device100amay provide bad block address BBA information to the host200a.

For example, the bad block address BBA information may include information of a range of row addresses designating a bad block BB. The range of the row addresses is referred to as a bad block row address BBRA.

In the cell array110a, a bad block BB can be designated by a block unit. It is assumed that a range of row addresses corresponding to a block BLK2is designated as a bad block row address BBRA. The semiconductor memory device100amay include an on-die fuse block150a. Address information about the bad block BB is stored in the on-die fuse block150a. For example, the on-die fuse block150amay include an anti-fuse circuit. However, a constitution of the on-die fuse block150ais not limited to a fuse circuit. Various nonvolatile storage devices may be provided by a constitution of the on-die fuse block150a.

The host200acontrols the semiconductor memory device100a. The host200amay control the semiconductor memory device100aso that the semiconductor memory device100astores data or may request the semiconductor memory device100aso that data stored in the semiconductor memory device100ais output. The host200aincludes a bad block address table210ato cut off generation of an address with respect to a bad block BB. The bad block address table210amay be constituted on a SRAM being driven in the host200a.

The host200areads bad block address (BBA) information from the on-die fuse block150aincluded in the semiconductor memory device100awhen a booting operation of the memory system is performed. The host200aconstitutes the bad block address table210aon the basis of the BBA information. When an access request to the semiconductor memory device100aoccurs, the host200agenerates an address for accessing to the semiconductor memory device100awith reference to the bad block address table210a. However, a row address corresponding to the bad block BB is inhibited in the host200a.

A method that BBA information is transmitted from the semiconductor memory device100ato the host200awas described above.

In one embodiment, during a manufacturing process such as a test of a semiconductor memory device, information of a bad block address BBA may be programmed in the on-die fuse block150a.

FIG. 5is a flow chart illustrating an exemplary operating method that in the memory system ofFIG. 4, an address of a bad block is transmitted from the semiconductor memory device100ato the host200a. Referring toFIG. 5, when a booting or power-on operation of the memory system is performed, a bad block row address BBRA programmed in the on-die fuse block150amay be transmitted to the host200a.

In a step S110, if power is provided to a memory system, a power-on operation begins. However, the power-on operation may occur by a reset of the memory system or an initial operation of the memory system.

In a step S120, if a level of a power voltage being supplied to the host200aand the semiconductor memory device100areaches a specific level, the semiconductor memory device100areads out data stored in the on-die fuse block150a. The semiconductor memory device100atransmits a bad block row address BBRA read from the on-die fuse block150ato the host200a.

In a step S130, the host200aconstitutes a bad block address table with reference to the bad block row address BBRA provided from the semiconductor memory device100a. For example, an access to the semiconductor memory device100ais performed with reference to the bad block address table210a.

The method that host200ais provided with bad block row address BBRA information (e.g., bad block address BBA information) from the semiconductor memory device100aincluding the on-die fuse block150awas described above.

FIG. 6is a block diagram illustrating a memory system in accordance with another exemplary embodiment. Referring toFIG. 6, a memory system includes a semiconductor memory device100band a host200b. Bad block address (BBA) information may be programmed in an on-die fuse block150b, for example, in a test process of the semiconductor memory device110b. In a memory system production process, the bad block address (BBA) information stored in the semiconductor memory device100bis transmitted to a nonvolatile memory220bof the host200b. The bad block address (BBA) information stored in the nonvolatile memory220bof the host200bmay be transmitted to a bad block address table210bwhen a booting operation is performed.

The host200bgenerates a command and an address with reference to the bad block address table210bwhen the host200baccess to the semiconductor memory device100b. The host200bis set not to generate an address of the bad block BB corresponding to a bad block BLK2.

For example, the host200bmay be a memory controller for controlling the semiconductor memory device100b. For example, the host200bmay be a memory managing unit MMU of a computing system including a function of the memory controller. The whole devices accessing to the semiconductor memory device100bmay be commonly called the host200b.

FIG. 7is a block diagram illustrating a memory system in accordance with still another exemplary embodiment. Referring toFIG. 7, a memory system includes a semiconductor memory device100cand a host200c. The host200cincludes a built-in-self-test (BIST) device230cperforming a function of a BIST. The host200cmay obtain address information of a bad block BB of the semiconductor memory device100cby the BIST.

The semiconductor memory device100cmay include blocks designated as a bad block BB. The semiconductor memory device100cdoes not need to include a separate nonvolatile memory device for storing address information about a bad block BB. In a cell array110c, a bad block BB can be designated by a block unit likeFIG. 3described above. InFIG. 7, row addresses corresponding to the block BLK2can be designated as a bad block row address BBRA. The semiconductor memory device100cmay include a fuse circuit for cutting off activation of a bad block BB when a word line is selected like a refresh operation.

The host200ccontrols the semiconductor memory device100c. The host200cmay control the semiconductor memory device100cso that the semiconductor memory device100cstores data or may request the semiconductor memory device100cso that data stored in the semiconductor memory device100cis output. The host200cincludes a bad block address table210cto cut off an access to a bad block BB. The bad block address table210cmay be constituted on a SRAM being driven in the host200c.

The host200cmay perform a built-in-self-test (BIST) operation with respect to the semiconductor memory device100c. The host200cmay perform a test autonomously when a booting or reset operation of the memory system is performed. The host200cincludes a test pattern with respect to the semiconductor memory device100camong various test items. In addition, the host200cmay include a detecting operation with respect to a bad block BB among various test items with respect to the semiconductor memory device100c. The host200ccan perform a general defect test and can collect a test result to generate address information about a bad block BB.

The host200cobtains bad block (BB) information about the semiconductor memory device100cby the BIST and the obtained information is loaded on the bad block address table210c. When the host200caccesses to the semiconductor memory device100c, the host200cgenerates a row address with reference to the bad block address table210c. In this way, the host200ccan forbear to access to a row address designated as the bad block BB.

FIG. 8is a flow chart illustrating an exemplary operating method that a bad block row address BBRA in the memory system ofFIG. 7is transmitted from the semiconductor memory device100cto the host200c. Referring toFIG. 8, when a booting operation of the memory system is performed, the host200cperforms a test autonomously to obtain address information of the bad block BB of the semiconductor memory device110c.

In a step S210, when a booting or power-on operation of the memory system is performed, the host200cand the semiconductor memory device100care activated when a power voltage is applied.

In a step S220, if a level of the power voltage being provided to the host200cand the semiconductor memory device100creaches a specific level, the semiconductor memory device100cperforms a built-in self-test (BIST) operation. The BIST operation may be a part of a power on self test (POST) operation. The host200ctransmits a test request to the semiconductor memory device100cand can test whether or not the semiconductor memory device100cis defective. For example, the host200cand the semiconductor memory device100cmay detect a bad block BB of the semiconductor memory device100cand transmit a bad block row address BBRA to the host200cthrough a channel.

In a step S230, the host200cupdates the bad block row address BBRA transmitted by the built-in-self-test in the bad block address table210c. After that, the host200caccesses to the semiconductor memory device100cwith reference to information loaded on the bad block address table210c.

A method that information of the bad block row address BBRA of the semiconductor memory device100cis fetched to the host200cby the built-in-self-test (BIST) was described above. In the case that the bad block row address BBRA of the semiconductor memory device100cis detected by the built-in-self-test (BIST), the semiconductor memory device100cdoes not need a constitution like the on-die fuse block. Thus, the unit cost of production of the semiconductor memory device100ccan be relatively lowered through the constitution of the memory system.

FIG. 9is a block diagram illustrating a memory system in accordance with yet another exemplary embodiment. Referring toFIG. 9, a memory system includes a semiconductor memory device100dand a host200d. In a production process of the memory system, an address of the bad block BB may be programmed in a nonvolatile volatile memory220dof the host200d.

As described above, the semiconductor memory device100dmay include blocks designated as a bad block BB. The semiconductor memory device100ddoes not need to include address information about a bad block BB of the semiconductor memory device100d. In a cell array110d, a bad block BB may be designated by a block unit likeFIG. 7described above. InFIG. 9, row addresses corresponding to a block BLK2may be designated as a bad block row address BBRA. The semiconductor memory device100dmay include a fuse circuit for cutting off activation of a bad block BB when a word line is selected like a refresh operation.

The host200dcontrols the semiconductor memory device100d. The host200dmay control the semiconductor memory device100dso that the semiconductor memory device100dstores data or can request the semiconductor memory device100dso that data stored in the semiconductor memory device100dis output. The host200dincludes a bad block address table210dto cut off an access to a bad block BB. The bad block address table210dmay be constituted on a SRAM being driven in the host200d.

The host200dincludes the nonvolatile memory220d. The nonvolatile memory220dmay store the bad block address BBRA of the semiconductor memory device100ddetected in the production process stage. When a booting operation of the memory system is performed, the host200dconstitutes a bad block address table210don the basis of information stored in the nonvolatile memory220d.

For example, if the address information of the bad block BB is only once stored in the host200d, it can be continuously maintained. Thus, the memory system of which an access to the bad block BB can be cut off without raising the unit cost of production of the semiconductor memory device200dcan be constituted.

FIG. 10is a block diagram illustrating a memory system in accordance with yet another exemplary embodiment. Referring toFIG. 10, a memory system includes a semiconductor memory device100eand a host200e. The host200eincludes a bad block address table210eincluding information about a bad block BB. The semiconductor memory device100ecan provide memory size information to the host200e. The host200ecan determine a range of a row address that can access to the semiconductor memory device100ewith reference to the memory size information.

The semiconductor memory device100emay provide no address information of the bad block BB but available memory size information. The memory size information is determined in a test process when the semiconductor memory device100eis produced. The memory size information is determined as a value obtained by subtracting a memory size corresponding to the bad block BB from the whole integrated memory size of the semiconductor memory device100e. The memory size information may be stored together with ID information of the semiconductor memory device100e.

If the memory system is boosted, the host200erequests ID information and memory size information about the semiconductor memory device100efirst. The semiconductor memory device100eprovides memory size information stored when a test process is performed to the host200e. The host200ecan determine a range of a row address to be accessed to the semiconductor memory device100ewith reference to the transmitted memory size information.

The semiconductor memory device100ehas to reorder a row address of word lines corresponding to the bad block BB. The semiconductor memory device100eis internally set so that a row address of word lines corresponding to the bad block BB gets out of a range of an accessible row address constituted by the host200e. That is, a row address has to be set so that an address of the bad block BB is located to exceed an accessible range from the host200e. In addition, the semiconductor memory device100e, although not illustrated, may further include a nonvolatile device storing memory size information.

FIG. 11is a drawing for explaining an address reordering method set in the inside of a semiconductor memory device ofFIG. 10in accordance with an exemplary embodiment. Referring toFIG. 11, it is assumed that blocks BLK3and BLK6correspond to a bad block BB. The semiconductor memory device100eis set to substitute a row address of the blocks BLK2and BLK6with an address of virtual blocks VBLK0and VBLK1, respectively. For example, a block row address of the semiconductor memory device100ecan be remapped.

The semiconductor memory device100eremaps the address of the blocks BLK2and BLK6to the address of the virtual blocks VBLK1and VBLK0. The virtual blocks VBLK1and VBLK0correspond to a row address range AR2exceeding a memory size which the semiconductor memory device100ecan provide. A row address of the remaining blocks BLK3˜BLK5and BLK7˜BLK9can be remapped to maintain continuity of row address. For example, the row address of the blocks BLK3˜BLK5and BLK7˜BLK9can be remapped to solve discontinuity that occurs by a remapping of the blocks BLK2and BLK6. For example, a row address of the blocks BLK3˜BLK5can be remapped to an address of the blocks BLK2˜BLK4and a row address of the blocks BLK7˜BLK9can be remapped to an address of the blocks BLK5˜BLK7. The memory size information is stored as a size corresponding to continuous eight blocks BLK0˜BLK7reconstituted by an address remapping. When a request for the memory size from the host200eoccurs, the stored memory size information is output. The host200egenerates a row address so that the host200ecan access to only the continuous eight blocks BLK0˜BLK7reconstituted by an address remapping with reference to the memory size information being provided from the semiconductor memory device100e.

FIG. 12is a block diagram illustrating a semiconductor memory device in accordance with another exemplary embodiment. Referring toFIG. 12, in a semiconductor memory device300, in the case that any one block corresponds to a bad block BB, adjacent blocks are also set to be a bad block. To perform that function, the semiconductor memory device300includes a cell array310, a column decoder320, a row decoder330and a fuse block340. Functions of the column decoder320and the row decoder330are same as those described inFIG. 3. Thus, a detailed description of the column decoder320and the row decoder330will be omitted.

The cell array310is the same as the cell array110ofFIG. 3. Memory cells of the cell array310may be divided by a block unit. In the case that a defect occurs in any one block, all the rows in which a corresponding defective block exists are designated as a bad block BB. If any one block (for example, BLK3) is designated as a bad block BB, adjacent blocks BLK2and BLK4are designated as a semi bad block. Even though the semi bad block does not include a bad block, a block that belongs to a semi bad block is likely to proceed to a bad block in the semiconductor memory device300requiring high reliability. Thus, according to a proceeding characteristic of the defect, memory cells adjacent to the bad block BB may be designated as a semi bad block.

An address of rows designated as a bad block BB is designated as a bad block row address BBRA to be access-inhibited. For example, in a refresh operation, an active operation of word lines corresponding to the bad block BB may be cut off. In addition, an address of rows designated as a semi bad block is designated as a bad block row address BBRA to be access-inhibited. For example, in a refresh operation, an active operation of word lines corresponding to the semi bad block may be cut off.

The fuse block340is programmed to cut off an access to a row of block unit. The fuse block340may include fuse circuits BRF_0˜BRF_5for controlling an access to each of rows of block unit. For example, the fuse circuits BRF_0˜BRF_5store information about whether or not an access to each of the blocks is possible. The fuse circuit BRF_3may be blown to cut off an access to the block BLK3designated as a bad block BB. In this case, activation of all word lines included in the block BLK3is cut off. Even when a refresh operation is performed, word lines included in the block BLK3are not activated. The fuse circuits BRF2and BRF4may be blown to cut off activation of word lines included in the semi bad blocks BLK2and BLK4adjacent to the block BLK3.

If a defective block exists in any one block to be designated as a bad block BB, fuse circuits corresponding to the semi bad blocks adjacent to the bad block BB are blown. Thus, even if a progressive defect occurs in a block included in the semi bad blocks, it cannot absolutely affect reliability of the semiconductor memory device300.

FIG. 13is a block diagram illustrating a semiconductor memory device in accordance with still another exemplary embodiment. Referring toFIG. 13, an access to a bad block of a semiconductor memory device400is possible and a part of the bad block may be used as a redundant word line. To perform that function, the semiconductor memory device400includes a cell array410, a column decoder420, a row decoder430, a fuse block440and a redundant circuit450. The column decoder420and the row decoder430are same as those described inFIG. 12. Thus, a detailed description of the column decoder420and the row decoder430will be skipped.

The cell array410may include a bad block BB. For example, it is assumed that a block BLK3is a bad block BB. However, an access to partial word lines of the bad block is possible. The partial word lines of the bad block BB can be selected and an access to the partial word lines of the bad block BB is possible. For example, one of the accessible word lines of the bad block BB may be used as a redundant word line.

In one embodiment, a function of cutting off a selection of the bad block BB of the fuse block440may be inactivated. The fuse block440may be set so that all the word lines of the bad block BB are selected and activated or set so that only partial word lines among all the word lines of the bad block BB are not activated. For example, the fuse circuit BRF_3of the fuse block440may include a plurality of sub fuse circuits so that only partial word lines among all the word lines of the bad block BB are set not to be activated.

The redundant circuit450is set to use a partial word line of the bad block BB as a redundant word line. One of word lines having no defects among partial word lines of the bad block BB is used as a redundant word line. In the case that a specific word line of a block has a defect, a word line among a plurality of word lines included in the bad block BB may replace the defective word line. The redundant circuit450includes the repair setting. In the case that a row address RA being input corresponds a defective word line, the redundant circuit450replaces the address of the defective word line with a word line included in the bad block BB.

A constitution of the semiconductor memory device400was described. The semiconductor memory device400provides a bad block row address BBRA to the external, and internally uses a normal word line of the bad block BB as a repair resource. Through those settings, the number of redundant cells that have to be provided for a repair may be reduced.

FIG. 14is a drawing illustrating a repair method of the semiconductor memory device ofFIG. 13in accordance with an exemplary embodiment. Referring toFIG. 14, a partial word line of the bad block BB is used to repair a word line having defect. The setting for a repair is provided by the redundant circuit450ofFIG. 13described above.

The cell array410can be divided into a plurality of blocks. The blocks are arranged along a row and a column. In any one block among the blocks, defects may exist over a plurality of word lines. It is assumed that a block BLK3is designated as a bad block BB. A bad block row address BBRA with respect to the block BLK3detected as a bad block BB is transmitted to the external (for example, a host). The host does not generate a bad block row address BBRA corresponding to the bad block BB.

A defective word line may exist in the cell array410. It is assumed that a word line WLi of a block BLK0is a defective word line. The defective word line WLi can be repaired with a word line WLj that exists in the bad block BB by the redundant circuit450. An access to the defective word line WLi is cut off by a setting of the redundant circuit450and an access to the word line WLj of the bad block BB occurs.

The repair operation is possible without a separate fuse blowing. However, to cut off a selection with respect to defective rows of the bad bloc BB in an operation like a self refresh operation, a process of the fuse block440may be needed. For example, one block BLK may include a plurality of fuses. The fuse block440may be configured such that parts of the fuses are blown and parts of the fuses are accessible in one block BLK. It can be set so that fuses corresponding to partial defective word lines of the bad block BB are blown and fuses corresponding to the remaining word lines (for example, WLj) are not blown. It can be set so that each of fuse circuits441,442,443,444and445includes a plurality of fuses and a part of the fuse circuit444corresponding to the bad block BB is blown. A first fuse BRF_30of the fuse circuit444is not blown and only second fuse BRF_31is blown and thereby activation of partial rows of the bad block BB may be cut off.

Through that constitution of the fuse block440, a repair function of the bad block BB is supported and activation of a defective word line can be cut off. As a result, high reliability can be implemented.

FIG. 15is a drawing illustrating an address mapping method in accordance with an exemplary embodiment. Referring toFIG. 15, in a semiconductor memory device, in the case that a bad block occurs in an area in which important data is stored, an address of a bad block has to be reordered. For example, defects such as a bad block or a bad page should not exist in an area in which, for example, a kernel of an operating system OS is stored. If a memory area in which kernel information of a system is stored is fixed, when a semiconductor memory device is produced, it can be set so that an address of the bad block BB is replaced with a block of an area in which user data is stored.

If an address of a semiconductor memory device in which a kernel of the operating system is stored is flexible, when a system including a semiconductor memory device is produced, an address of the bad block should be changed.

FIG. 16is a block diagram illustrating a semiconductor memory device performing an address reorder in accordance with an exemplary embodiment. Referring toFIG. 16, in the case that a bad block BB of a semiconductor memory device500stores a system file such as a kernel, the bad block BB can be replaced with a block of an area in which user data is stored. To perform that function, the semiconductor memory device500includes a cell array510, a column decoder520, a row decoder530, a fuse block540and a reorder decoder550. The column decoder520, the row decoder530and the fuse circuit540are same as those ofFIG. 12. Thus, description of the column decoder520, the row decoder530and the fuse block540is omitted.

The cell array510may be divided into a memory area in which important data is stored and a memory area in which user data is stored. Data like a kernel, if a defect exists, may be fatal to the system. Thus, reliability of important data like the system file should be guaranteed. The data such as a kernel is stored in a kernel area. Data which a user inputs is stored in a user area. However, in the case that a bad block BB exists in the kernel area, reliability of the system is rapidly degraded. Thus, an address reorder should be performed that the bad block that exists in the kernel area is replaced with a block of the user area.

In one embodiment, the address reorder may be performed by a reorder decoder550. A row address of the bad block BB located in the kernel area is reordered to a row address of the user area by the reorder decoder550. If an address of the kernel area is flexible, a setting of the reorder decoder550may be performed when a system including the semiconductor memory device500is produced.

A function of the reorder decoder550may be controlled in a host. For example, in the case that an address reorder is needed, a MRS setting of the semiconductor memory device500may be performed by a request of the host. According to a MRS setting, an address of the bad block BB that exists in the kernel area of the semiconductor memory device500may be replaced with an address of a block in the user area.

FIG. 17is a block diagram illustrating a user device in accordance with certain embodiments. Referring toFIG. 17, a user device1000(for example, a computer system) includes a central processing unit1100, a chipset1200, a ROM1300, a DRAM1400and an auxiliary storage1500. The DRAM1400is provided as a main memory or a working memory of the user device1000, and is disclosed herein according to example embodiments.

The central processing unit1100reads a BIOS or an operating system OS from the ROM1300or the auxiliary storage1500and executes the BIOS or the operating system OS. When a booting operation of the user device1000is performed, the central processing unit1100reads a boot program (or boot strap) of a BIOS from the ROM1300and executes the boot program. The central processing unit1100performs an arithmetic operation for data processing of the user device1000. The central processing unit1100accesses the auxiliary storage1500according to a given sequence to drive a program like an operating system OS when a booting operation is performed. The central processing unit1100controls the auxiliary storage1500and a memory managing unit1250so that operating system data stored in the auxiliary storage1500is read to be stored in the DRAM1400. That control operation is only an illustration and the central processing unit1100manages all the control operations of the user device1000.

The chip set1200controls various devices being mounted on the user device1000. To control devices being mounted on the user device1000, a plurality of control circuits may be built in the chip set1200. The chip set1200may include the memory managing unit1250for controlling the DRAM1400.

The chip set1200may be separated into two chip sets of a north bridge and a south bridge. The north bridge is located near the central processing unit1100and can control the central processing unit1100and the DRAM1400. For example, the memory managing unit1250may be included in the north bridge. Although not illustrated, expansion card slots for a high speed such as an AGP, a PCI express, etc. are controlled by the north bridge. However, a constitution and a role of the chip set1200are not limited to the aforementioned description. The central processing unit1100may include the memory managing unit.

The ROM1300stores BIOS. The BIOS supports the most basic processing routine of the user device1000. For example, the BIOS includes a start-up routine, a service processing routine and a hard ware interrupt routine. The start-up routine performs a POST work and an initialization work when the user device1000is booted. The service processing routine processes a work which the operating system OS or an application program requests.

The DRAM1400is a main or a working memory and is driven in the user device1000. The DRAM1400can be accessed by a byte unit and is a rewritable nonvolatile memory device. An operation system OS, an application program being driven and data being updated are stored in the DRAM1400being used as a working memory when the user device1000is driven. The DRAM1400can transmit information about the bad block BB to the chip set1200. The DRAM1400can cut off activation of the bad block BB through a fuse setting when necessary.

The auxiliary storage1500stores data such as user data, an operating system OS, an application program, etc. The auxiliary storage1500may be one of, for example, a hard disk driver (HDD), a solid state driver (SSD) and a hybrid hard disk driver (Hybrid HDD). The auxiliary storage1500is a high storage device and may store a program, a code or setting data being driven in the user device1000. However, the auxiliary storage1500is not limited to those examples described above.

The user device1000may further include a user interface, a battery, a modem, etc. Although not illustrated, an application chipset, a camera image processor CIS, a mobile DRAM, etc. may be further provided to the user device1000.

The user device1000can be mounted by various types of packages. For example, the user device1000can be mounted by various types of packages such as PoP (package on package), ball grid array (BGA), chip scale package (CSP), plastic leaded chip carrier (PLCC), plastic dual in-line package (PDIP), die in waffle pack, die in wafer form, chip on board (COB), ceramic dual in-line package (CERDIP), plastic metric quad flat pack (MQFP), thin quad flat pack (TQFP), small outline (SOIC), shrink small outline package (SSOP), thin small outline (TSOP), thin quad flatpack (TQFP), system in package (SIP), multi chip package (MCP), wafer-level fabricated package (WFP) and wafer-level processed stack package (WSP).

According to the above-disclosed embodiments, even if defects occur by a block unit, a semiconductor memory device that can be provided as a good product can be embodied. Thus, Reliability of a semiconductor memory device being reduced with the increase of integration and performance may be increased.