Silicon carbide semiconductor device and manufacturing method of the same

In order to provide a high-performance and reliable silicon carbide semiconductor device, in a silicon carbide semiconductor device including an n-type SiC epitaxial substrate, a p-type body layer, a p-type body layer potential fixing region and a nitrogen-introduced n-type first source region formed in the p-type body layer, an n-type second source region to which phosphorus which has a solid-solubility limit higher than that of nitrogen and is easily diffused is introduced is formed inside the nitrogen-introduced n-type first source region so as to be separated from both of the p-type body layer and the p-type body layer potential fixing region.

TECHNICAL FIELD

The present invention relates to a silicon carbide semiconductor device which is constituted of a plurality of power semiconductor devices using a silicon carbide substrate, and a manufacturing method of the same.

BACKGROUND ART

Conventionally, in a power metal insulator semiconductor field effect transistor (MISFET) which is one of the power semiconductor devices, a power MISFET using a silicon (Si) substrate (hereinafter, referred to as an Si power MISFET) has been a mainstream.

However, the power MISFET using a silicon carbide (SiC) substrate (hereinafter, referred to as an SiC substrate) (hereinafter, referred to as an SiC power MISFET) can achieve higher breakdown voltage and lower loss compared to the Si power MISFET. Therefore, the SiC power MISFET has drawn attention in the field of power saving or eco-friendly inverter technologies.

Compared to the Si power MISFET, the SiC power MISFET can achieve a lower ON resistance at the same breakdown voltage. This is because the dielectric breakdown electric field intensity of silicon carbide (SiC) is about seven times as large as that of silicon (Si), so that an epitaxial layer serving as a drift layer can be made thin. However, considering the original characteristics to be obtained from silicon carbide (SiC), it cannot be said that sufficient characteristics have been obtained, and further reduction of the ON resistance has been desired from the viewpoint of high efficient utilization of energy.

One of the problems to be solved for the ON resistance of the SiC power MISFET of a DMOS (Double diffused Metal Oxide Semiconductor) structure is a parasitic contact resistance on a contact surface between a source diffusion layer and a metal electrode, which is a unique problem in the SiC power MISFET. The contact resistance component occupies about 0.5 to 1 mΩcm2in the ON resistance component. Although the On resistance depends on a rated breakdown voltage, it is about 2 to 5 mΩcm2in the case of a breakdown voltage of 600 to 1000 V. Therefore, a ratio occupied by the contact resistance is 10% or more, and the resistance increase and variation cannot be ignored. In general, in order to reduce the contact resistance, a silicide layer is formed on an SiC substrate where a contact is formed. Furthermore, it is desirable that a substrate concentration of a contact surface between the silicide layer and the source diffusion layer is high, and a range of 1×1019cm−3to 1×1021cm−3is desirable.

Nitrogen or phosphorus is used as an impurity of the source diffusion layer in an SiC power DMOS (for example, Non-Patent Documents 1 and 2). In the case where the nitrogen is used as an impurity, there is a problem in that a solid-solubility limit is low and electrical activation is not sufficiently achieved even when the impurity is implanted at a high concentration. For example, as described in Non-Patent Document 1, even when phosphorus and nitrogen are implanted at the same concentration and an activation thermal treatment is performed at the same temperature for the same period, the nitrogen is less electrically activated, and sheet resistance in the case where nitrogen is used as an impurity is ten times higher compared to the case where phosphorus is used as an impurity.

Therefore, there is a need for a technology to use phosphorus in the source diffusion layer of the contact portion. For example, as described in Japanese Patent Application Laid-Open Publication No. 2006-173584 (Patent Document 1) and Japanese Patent Application Laid-Open Publication No. 2009-064970 (Patent Document 2), a method of using phosphorus as an impurity of the source diffusion layer of the contact portion is disclosed.

RELATED ART DOCUMENTS

Patent Documents

SUMMARY OF THE INVENTION

Problems to be Solved by the Invention

However, as described in Non-Patent Document 2, for example, as a problem in the case where phosphorus is used as an impurity, there is known that the phosphorus is likely to be diffused in a direction of the (11-20) plane compared to the (0001) plane after being subjected to the activation thermal treatment. Therefore, in consideration of the problem above, the inventors have further examined the problem in the case where phosphorus is applied to the DMOS. In the DMOS, the direction of the (11-20) plane corresponds to a channel direction and a direction of a body layer potential fixing region, and a direction of the diffusion is a transverse direction with respect to the substrate. Therefore, in the case where phosphorus is used for a source diffusion layer, there is a concern that the channel is shortened and a threshold voltage is lowered. As another problem, the concentration of the body layer potential fixing region is lowered due to the diffusion of phosphorus in a transverse direction, and it becomes difficult to fix the potential of the body layer. As a result, there is a risk that a breakdown voltage failure may occur. In addition, it has been found that the width of the body layer potential fixing region is as small as about 1 μm at most, and there is a risk that the problems of a reduction in concentration and a reduction in area of the body layer potential fixing region both occur when high-concentration phosphors is diffused in the transverse direction.

An object of the invention is to provide a high-performance and reliable silicon carbide semiconductor device and a manufacturing method of the silicon carbide semiconductor device, even in the case where nitrogen or the like which is hard to be diffused and has a low solid-solubility limit is used as an impurity of a source diffusion layer and phosphorus which is easy to be diffused and has a solid-solubility limit higher than that of the nitrogen is used at a high concentration as an impurity of a source diffusion layer of a contact portion.

Means for Solving the Problems

The following is a brief description of an embodiment of a typical invention disclosed in the present application.

A silicon carbide semiconductor device includes: a substrate of a first conductivity type which includes a first main surface and a second main surface which is an opposite surface of the first main surface and is made of silicon carbide; an epitaxial layer which is formed on the first main surface of the substrate and made of silicon carbide; a body layer of a second conductivity type different from the first conductivity type, which has a first depth from a surface of the epitaxial layer and is formed in the epitaxial layer; a body layer potential fixing region of the second conductivity type, which has a second depth from the surface of the epitaxial layer and is formed in the epitaxial layer; a first source region of the first conductivity type, which has a third depth from the surface of the epitaxial layer and is formed in the body layer so as to be separated from an end portion of the body layer and to be adjacent to the body layer potential fixing region, and to which a first impurity is introduced; a second source region of the first conductivity type, which has a fourth depth from the surface of the epitaxial layer and is formed inside the first source region on a side of the end portion of the body layer and is further formed inside the first source region so as to be separated from the body layer potential fixing region on a side of the body layer potential fixing region, and to which a second impurity which has a solid-solubility limit higher than that of the first impurity and is easily diffused is introduced; a third source region of the first conductivity type, which has a fifth depth from the surface of the epitaxial layer and is formed of the first source region and the second source region overlapped with each other; a source diffusion layer region including the first source region, the second source region and the third source region; a channel region formed in the body layer between the end portion of the body layer and the first source region; a gate insulating film formed to be in contact with the channel region; a gate electrode formed to be in contact with the gate insulating film; and a drain region of the first conductivity type, which has a sixth depth from the second main surface of the surface and is formed in the substrate.

Also, in a silicon carbide semiconductor device which uses a silicon carbide substrate and includes a plurality of power semiconductor devices, in the power semiconductor device, a drift layer of a first conductivity type, a body layer of a second conductivity type different from the first conductivity type in which a channel is formed, a source region of the first conductivity type, and a body layer potential fixing region of the second conductivity type which fixes a potential of the body layer are arranged in this order in a channel length direction on a surface of a region made of silicon carbide, a gate insulating film and a gate electrode are stacked on the body layer, the drift layer is connected to a drain region of the first conductivity type, a region having a high nitrogen concentration and a region having a high phosphorus concentration are arranged in the channel length direction in the source region, and the body layer and the region having the high nitrogen concentration are in contact with each other.

Also, a manufacturing method of a silicon carbide semiconductor device, includes the steps of: (a) forming an epitaxial layer of a first conductivity type made of silicon carbide on a first main surface of a substrate of the first conductivity type made of silicon carbide; (b) forming a drain region of the first conductivity type having a sixth depth from a second main surface of the substrate in the second main surface which is an opposite surface of the first main surface of the substrate; (c) forming a first mask on a surface of the epitaxial layer so as to cover a part of the epitaxial layer and implanting an impurity of the second conductivity type to the epitaxial layer exposed from the first mask, thereby forming a body layer having a first depth from the surface of the epitaxial layer in the epitaxial layer; (d) forming a second mask on a surface of the body layer so as to cover a part of the body layer and implanting a first impurity of the first conductivity type to the body layer exposed from the second mask, thereby forming a first source region having a third depth from the surface of the epitaxial layer in the body layer; (e) forming a third mask on the surface of the epitaxial layer so as to cover the second mask; (f) forming a sidewall made of the third mask on a side surface of the second mask by processing the third mask by anisotropic dry etching and forming the third mask made of the sidewall on the surface of the epitaxial layer so as to cover a part of the first source region; and (g) implanting an impurity of the first conductivity type, which has a solid-solubility limit higher than that of the first impurity and is easily diffused, to the epitaxial layer where the body layer exposed from the second mask is formed, thereby forming a second source region having a fourth depth from the surface of the epitaxial layer.

The effects obtained by a typical embodiment of the invention disclosed in the present application will be briefly described below.

It is possible to provide a high-performance and reliable silicon carbide semiconductor device and a manufacturing method of the silicon carbide semiconductor device even in the case where nitrogen or the like which is hard to be diffused and has a low solid-solubility limit is used as an impurity of a source diffusion layer and phosphorus which is easy to be diffused and has a solid-solubility limit higher than that of the nitrogen is used at a high concentration as an impurity of a source diffusion layer of a contact portion.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

In the embodiments described below, the invention will be described in a plurality of sections or embodiments when required as a matter of convenience. However, these sections or embodiments are not irrelevant to each other unless otherwise stated, and the one relates to the entire or a part of the other as a modification example, details, or a supplementary explanation thereof.

Also, in the embodiments described below, when referring to the number of elements (including number of pieces, values, amount, range, and the like), the number of the elements is not limited to a specific number unless otherwise stated or except the case where the number is apparently limited to a specific number in principle, and the number larger or smaller than the specified number is also applicable. Further, in the embodiments described below, it goes without saying that the components (including element steps) are not always indispensable unless otherwise stated or except the case where the components are apparently indispensable in principle. Similarly, in the embodiments described below, when the shape of the components, positional relation thereof, and the like are mentioned, the substantially approximate and similar shapes and the like are included therein unless otherwise stated or except the case where it is conceivable that they are apparently excluded in principle. The same goes for the numerical value and the range described above.

Also, in some drawings used in the following embodiments, hatching is used even in a plan view so as to make the drawings easy to see. Also, components having the same function are denoted by the same reference characters throughout the drawings for describing the embodiments, and the repetitive description thereof is omitted. Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

A structure of the silicon carbide semiconductor device according to the first embodiment of the present invention will be described with reference toFIGS. 1 and 2.FIG. 1is a top view illustrating a principal part of a semiconductor chip in which the silicon carbide semiconductor device constituted of a plurality of SiC power MISFETs is mounted, andFIG. 2is a cross-sectional view illustrating a principal part of the SiC power MISFET. The SiC power MISFET constituting the silicon carbide semiconductor device is a MISFET of a DMOS structure.

As illustrated inFIG. 1, a semiconductor chip1in which the silicon carbide semiconductor device is mounted includes an active region (an SiC power MISFET forming region, an element forming region)2in which a plurality of n-channel SiC power MISFETs are connected in parallel and a peripheral forming region surrounding the active region2when seen in a plan view. In the peripheral forming region, a plurality of p-type floating field limiting rings (FLR)3which are formed to surround the active region2when seen in a plan view and an n-type guard ring4which is formed to surround the plurality of p-type floating field limiting rings3when see in a plan view are formed.

On a front surface side of the active region of an n-type silicon carbide (SiC) epitaxial substrate (hereinafter, referred to as an SiC epitaxial substrate), a gate electrode, an n+-type source region and a channel region of the SiC power MISFET are formed, and an n+-type drain region of the SiC power MISFET is formed on the rear surface side of the SiC epitaxial substrate.

With the plurality of p-type floating field limiting rings3formed around the active region2, the maximum electric field portion moves sequentially toward the outermost p-type floating field limiting ring3at the time of turning off, and is broken down in the outermost p-type floating field limiting ring3, so that a high breakdown voltage can be achieved in the silicon carbide semiconductor device. InFIG. 1, an example of three p-type floating field limiting rings3is illustrated, but the invention is not limited thereto. In addition, the n-type guard ring4has a function to protect the SiC power MISFET formed in the active region2.

The gate electrodes of the plurality of SiC power MISFETs formed in the active region2are connected to form a stripe pattern when seen in a plan view, and the gate electrodes of all the SiC power MISFETs are electrically connected to a gate wiring electrode5by lead wirings (gate bus lines) connected to each stripe pattern. The example in which the gate electrodes are formed in the stripe pattern has been described here, but the invention is not limited thereto, and the gate electrodes may be formed in, for example, a box pattern or a polygonal pattern.

In addition, the source regions of the plurality of SiC power MISFETs are electrically connected to a source wiring electrode7through openings6formed in an interlayer insulating film which covers the plurality of SiC power MISFETs. The gate wiring electrode5and the source wiring electrode7are formed to be separated from each other, and the source wiring electrode7is formed in the almost entire active region2except the region in which the gate wiring electrode5is formed. In addition, the n+-type drain region formed on the rear surface side of the n-type SiC epitaxial substrate is electrically connected to a drain wiring electrode8(not illustrated) which is formed on the entire rear surface of the n-type SiC epitaxial substrate.

Next, a structure of the SiC power MISFET according to the first embodiment will be described with reference toFIG. 2.

An n−-type epitaxial layer102made of silicon carbide (SiC) having an impurity concentration lower than that of an n+-type SiC substrate (substrate)101made of silicon carbide (SiC) is formed on the surface (first main surface) of the n+-type SiC substrate101, and an SiC epitaxial substrate104is constituted of the n+-type SiC substrate101and the n−-type epitaxial layer102. The thickness of the n−-type epitaxial layer102is, for example, about 5 to 20 μm.

In the n−-type epitaxial layer102, a p-type body layer (well region)105is formed to have a predetermined depth from the surface of the n−-type epitaxial layer102. Furthermore, in the p-type body layer105, an n+-type source region (first source region)106containing nitrogen as an impurity is formed to have a predetermined depth from the surface of the n−-type epitaxial layer102, and an n++-type source region (second source region)107containing phosphorus as an impurity is formed in the n+-type source region (first source region)106. A source region made up of an n++-type third source region108formed of the first source region and the second source region overlapped with each other is formed.

The channel region is formed between the n+-type first source region106and an end portion of the p-type body layer.

Furthermore, in the p-type body layer105, a p+-type body layer potential fixing region109is formed to have a predetermined depth from the surface of the n−-type epitaxial layer102.

The depth (first depth) of the p-type body layer105from the surface of the epitaxial layer102is, for example, about 0.5 to 2.0 μm. In addition, the depth (third depth) of the n+-type first source region106from the surface of the epitaxial layer102is, for example, about 0.05 to 0.25 μm. Meanwhile, the depth (fourth depth) of the n++-type second source region107from the surface of the epitaxial layer102is, for example, about 0.1 to 0.35 μm. The depth (fifth depth) of the third source region108from the surface of the epitaxial layer102is, for example, about 0.05 to 0.25 μm.

Namely, the n++-type second source region107is formed at a position separated from the end portion of the channel region in the n+-type first source region106and the end portion of the p+-type body layer potential fixing region109.

Furthermore, the depth (second depth) of the p+-type body layer potential fixing region109from the surface of the epitaxial layer102is, for example, about 0.05 to 0.35 μm. In addition, an n+-type drain region103is formed to have a predetermined depth (sixth depth) from the rear surface (second main surface) of the SiC substrate101.

Further, “−” and “+” are symbols indicating a relative impurity concentration of the n or p conductivity type, and for example, the impurity concentration of an n-type impurity increases in order of “n−”, “n”, “n+” and “n++”.

A desirable range of the impurity concentration of the n+-type SiC substrate101is, for example, 1×1018to 1×1021cm−3, a desirable range of the impurity concentration of the n−-type epitaxial layer102is, for example, 1×1014to 1×1017cm−3, and a desirable range of the impurity concentration of the p-type body layer105is, for example, 1×1016to 1×1019cm−3. In addition, a desirable range of the impurity concentration of the n+-type first source region106is, for example, 1×1018to 1×1020cm−3and a desirable range of the impurity concentration of the n++-type second source region107is, for example, 1×1019to 1×1021cm−3. A desirable range of the impurity concentration of the p+-type body layer potential fixing region109is, for example, 1×1018to 1×1021cm−3.

A gate insulating film110is formed on the channel region, a gate electrode111is formed on the gate insulating film110, and the gate insulating film110and the gate electrode111are covered with an interlayer insulating film112. Furthermore, a part of the n++-type third source region108and the p+-type body layer potential fixing region109are exposed on the bottom surface of an opening CNT formed in the interlayer insulating film112, and a metal silicide layer113is formed on the surfaces thereof. Furthermore, the source wiring electrode7is electrically connected to a part of the n++-type third source region108and the p+-type body layer potential fixing region109through the metal silicide layer113, and the drain wiring electrode8is electrically connected to the n+-type drain region103through a metal silicide layer116. Though not illustrated in the drawing, similarly, the gate electrode111is electrically connected to the gate wiring electrode. A source potential is applied from the outside to the source wiring electrode7, a drain potential is applied from the outside to the drain wiring electrode8, and a gate potential is applied from the outside to the gate wiring electrode.

Next, the features of the structure of the SiC power MISFET according to the first embodiment will be described with reference toFIG. 2mentioned above.

As illustrated inFIG. 2mentioned above, in the n+-type first source region106, the n++-type second source region107is formed to be separated from the end portion of the p+-type body layer potential fixing region109and the end portion of the channel region positioned on the opposite side thereof. The impurity of the n+-type first source region106is nitrogen, and the impurity of the n++-type second source region107is phosphorus. The second source region107is formed deeper than the first source region106. In addition, the n++-type third source region108is formed in a portion where the first source region106and the second source region107are overlapped. Since phosphorus which is electrically active is implanted as an impurity at a high concentration in the second source region107, a contact resistance can be reduced. In addition, since the n++-type second source region107is formed to be separated from the p+-type body layer potential fixing region109and the channel, even when the phosphorus as the impurity of the second source region107is diffused in the transverse direction, a potential can be applied to the p-type body layer105without reducing the concentration of the p+-type body layer potential fixing region109. In addition, since the phosphorus is not diffused up to the channel region, a short channel effect causing a reduction in threshold voltage does not occur. Therefore, it is possible to provide an SiC power DMOSFET which is not degraded in performance due to the transverse diffusion of the phosphorus while realizing a low contact resistance.

<<Manufacturing Method of Silicon Carbide Semiconductor Device>>

A manufacturing method of the silicon carbide semiconductor device according to the first embodiment of the present invention will be described in process order with reference toFIGS. 3 to 16.FIGS. 3 to 16are cross-sectional views illustrating a principal part in which a part of the SiC power MISFET forming region (element forming region) and a part of the peripheral forming region of the silicon carbide semiconductor device are depicted in an enlarged manner. Note that three floating field limiting rings are illustrated in the peripheral forming region ofFIGS. 3 to 16.

First, the n+-type 4H-SiC substrate101is prepared as illustrated inFIG. 3. An n-type impurity is introduced to the n+-type SiC substrate101. The n-type impurity is, for example, nitrogen (N), and the impurity concentration of the n-type impurity is, for example, in a range of 1×1018to 1×1021cm−3. In addition, the n+-type SiC substrate101has both of an Si surface and a C surface, and the surface of the n+-type SiC substrate101may be the Si surface or the C surface.

Next, the n−-type epitaxial layer102made of silicon carbide (SiC) is formed on the surface (first main surface) of the n+-type SiC substrate101by an epitaxial growth method. In the n−-type epitaxial layer102, an n-type impurity having an impurity concentration lower than that of the n+-type SiC substrate101is introduced. The impurity concentration of the n−-type epitaxial layer102is, for example, in a range of 1×1014to 1×1017cm−3though it depends on a device rating of the SiC power MISFET. In addition, the thickness of the n−-type epitaxial layer102is, for example, 5 to 20 μm. Through the process above, the SiC epitaxial substrate104constituted of the n+-type SiC substrate101and the n−-type epitaxial layer102is formed.

Next, the n+-type drain region103is formed on the rear surface (second main surface) of the n+-type SiC substrate101so as to have a predetermined depth (sixth depth) from the rear surface of the n+-type SiC substrate101. The impurity concentration of the n+-type drain region103is, for example, in a range of 1×1019to 1×1021cm−3.

Next, as illustrated inFIG. 4, a mask1is formed on the surface of the n−-type epitaxial layer102. The thickness of the mask1is, for example, about 1.0 to 3.0 μm. The width of the mask1in the element forming region is, for example, about 1.0 to 5.0 μm. An inorganic material may be used as the material of the mask. In this case, an SiO2film is used as the material of the mask.

Next, a p-type impurity, for example, aluminum atoms (Al) is ion-implanted to the n−-type epitaxial layer102over the mask1. In this manner, the p-type body layer105is formed in the element forming region of the n−-type epitaxial layer102, and a p-type floating field limiting ring (hereinafter, referred to as a ring)105ais formed in the peripheral forming region.

The depth (first depth) of the p-type body layer105and the p-type ring105afrom the surface of the epitaxial layer102is, for example, about 0.5 to 2.0 μm. In addition, the impurity concentration of the p-type body layer105and the p-type ring105ais, for example, in a range of 1×1016to 1×1019cm−3. Although the p-type ring105ais formed in the peripheral forming region in this case, the structure of the termination portion is not limited thereto, and for example, a junction termination extension (JTE) may be employed.

Next, as illustrated inFIG. 5, a mask2is formed using an SiO2film after the mask1is removed. The thickness of the mask2is, for example, about 0.5 to 1.5 μm. In addition, an opening portion of the mask2is provided not only in the element forming region but also in the peripheral forming region.

Next, nitrogen atoms (N) are ion-implanted as an n-type impurity to the n−-type epitaxial layer102over the mask2, so that the n+-type first source region106is formed in the element forming region and an n+-type first guard ring106ais formed in the peripheral forming region. The depth (third depth) of the n+-type first source region106and the n+-type first guard ring106afrom the surface of the epitaxial layer102is, for example, about 0.05 to 0.25 μm. In addition, the impurity concentration of the n+-type first source region106and the n+-type first guard ring106ais, for example, in a range of 1×1018to 1×1020cm−3.

Next, as illustrated inFIG. 6, a mask3is formed to cover the mask2and the n+-type first source region106. The film thickness of the mask3is, for example, about 0.1 to 0.5 μm, and the material thereof is silicon oxide (SiO2).

Next, as illustrated inFIG. 7, the mask3is processed by an anisotropic dry etching method to form a sidewall made of the mask3on the side surface of the mask2. Since the sidewall made of the mask3is formed, an area of the n++-type second source region107when seen in a plan view to be formed in the subsequent process can be made smaller than that of the n+-type first source region106when seen in a plan view. The width of the sidewall made of the mask3is determined by the film thickness of the mask3and is, for example, about 0.1 to 0.5 μm. Phosphorus atoms (P) are ion-implanted as an n-type impurity to the n++-type epitaxial layer102over the sidewall made of the mask3and the mask2, thereby forming the n++-type second source region107and an n++-type second guard ring107ain the element forming region. The depth (fourth depth) of the n++-type second source region107and the n++-type second guard ring107afrom the surface of the epitaxial layer102is, for example, about 0.1 to 0.35 μm. In addition, the impurity concentration of the n++-type second source region107and the n+-type second guard ring107ais, for example, in a range of 1×1019to 1×1021cm−3.

By forming the n++-type second source region107and the n++-type second guard ring107ato be deeper than the n+-type first source region106and the n+-type first guard ring106a, the n++-type third source region108is formed in an overlapped portion between the n+-type first source region106and the n++-type second source region107, and an n++-type third guard ring108ais formed in an overlapped portion between the n+-type first guard ring106aand the n++-type second guard ring107a. The depth (fifth depth) of the third source region108and the third guard ring108afrom the surface of the epitaxial layer102is, for example, about 0.05 to 0.25 μm.

In the first embodiment, since the source region (the n+-type first source region106, the n++-type second source region107and the n++-type third source region108) of the element forming region and the guard ring (the n+-type first guard ring106a, the n++-type second guard ring107aand the n++-type third guard ring108a) of the peripheral forming region are formed at the same time, the source region and the guard ring have the same impurity distribution in the depth direction.

Next, as illustrated inFIG. 8, a mask4is formed using an SiO2film after the mask2and the mask3are removed. The mask4is provided with an opening portion only in a region where the p+-type body layer potential fixing region109for fixing the potential of the p-type body layer105is formed in the subsequent process. The thickness of the mask4is, for example, about 0.5 to 1.5 μm.

Next, the p-type impurity, for example, aluminum atoms (Al) is ion-implanted to the n−-type epitaxial layer102over the mask4, thereby forming the p+-type body layer potential fixing region109. The depth (second depth) of the p+-type body layer potential fixing region109from the surface of the epitaxial layer102is, for example, about 0.05 to 0.35 μm. The impurity concentration of the p+-type body layer potential fixing region109is, for example, in a range of 1×1018to 1×1021cm−3.

Next, after the mask4is removed, though not illustrated in the drawing, a carbon (C) film is deposited on the front surface and the rear surface of the SiC epitaxial substrate104by, for example, a plasma CVD method. The thickness of the carbon (C) film is, for example, about 0.03 μm. After covering the front surface and the rear surface of the SiC epitaxial substrate104with the carbon (C) film, thermal treatment is performed on the SiC epitaxial substrate104at a temperature of 1500° C. or more for about 2 to 3 minutes. In this manner, the impurities which have been ion-implanted to the SiC epitaxial substrate104are activated. After the thermal treatment, the carbon (C) film is removed by, for example, an oxygen plasma treatment.

Next, as illustrated inFIG. 9, the gate insulating film110is formed on the surface of the n−-type epitaxial layer102. The gate insulating film110is made of an SiO2film by, for example, a thermal CVD method. The thickness of the gate insulating film110is, for example, about 0.05 to 0.15 μm.

Next, as illustrated inFIG. 10, an n-type polycrystalline silicon (Si) film111A is formed on the gate insulating film110. The thickness of the n-type polycrystalline silicon (Si) film111A is, for example, about 0.2 to 0.5 μm.

Next, as illustrated inFIG. 11, the polycrystalline silicon (Si) film111A is processed by the dry etching method with using a mask5(photoresist film), thereby forming the gate electrode111.

Next, as illustrated inFIG. 12, after the mask5is removed, the interlayer insulating film112is formed on the surface of the n−-type epitaxial layer102by, for example, the plasma CVD method so as to cover the gate electrode111and the gate insulating film110.

Next, as illustrated inFIG. 13, the interlayer insulating film112and the gate insulating film110are processed by the dry etching method with using a mask6(photoresist film), thereby forming an opening CNT which reaches a part of the n++-type third source region108, a part of the n+-type first source region106and the p+-type body layer potential fixing region109.

Next, as illustrated inFIG. 14, after the mask6is removed, the metal silicide layer113is formed on the respective surfaces of a part of the n++-type third source region108, a part of the n+-type first source region106and the p+-type body layer potential fixing region109exposed on the bottom surface of the opening CNT.

First, though not illustrated in the drawing, a first metal film, for example, nickel (Ni) is deposited on the surface of the n−-type epitaxial layer102so as to cover the interlayer insulating film112and the inside of the opening CNT (side surface and bottom surface) by, for example, a sputtering method. The thickness of the first metal film is, for example, about 0.05 μm. Subsequently, a silicide thermal treatment is performed at 600 to 1000° C. to make the first metal film and the n−-type epitaxial layer102react with each other on the bottom surface of the opening CNT, thereby forming the metal silicide layer113, for example, a nickel silicide (NiSi) layer on the respective surfaces of a part of the n++-type third source region108, a part of the n+-type first source region106and the p+-type body layer potential fixing region109exposed on the bottom surface of the opening CNT. Then, the unreacted first metal film is removed by a wet etching method. In the wet etching method, for example, a sulfuric acid/hydrogen peroxide mixture is used.

Next, as illustrated inFIG. 15, a third metal film, for example, a stacked film made up of a titanium (Ti) film, a titanium nitride (TiN) film and an aluminum (Al) film is deposited on the interlayer insulating film112including the inside of the opening CNT reaching the metal silicide film113formed on the respective surfaces of a part of the n++-type third source region108, a part of the n+-type first source region106and the p+-type body layer potential fixing region109and the inside of the opening (not illustrated) reaching the gate electrode111. A desirable thickness of the aluminum (Al) film is, for example, 2.0 μm or more. Subsequently, the third metal film is processed to form the source wiring electrode7electrically connected to a part of the n++-type third source region108through the metal silicide layer113and the gate wiring electrode (not illustrated) electrically connected to the gate electrode111. Note that the gate wiring electrode is fabricated by the same process as that of the source wiring electrode except the polycrystalline silicon film.

Next, though not illustrated in the drawing, an SiO2film or a polyimide film is stacked as a passivation film so as to cover the gate wiring electrode and the source wiring electrode7.

Next, as illustrated inFIG. 15, the passivation film is processed to form a passivation film115.

Next, though not illustrated in the drawing, a second metal film is deposited on the rear surface of the n+-type SiC substrate101by, for example, the sputtering method. The thickness of the second metal film is, for example, about 0.1 μm.

Next, as illustrated inFIG. 16, the second metal film is reacted with the n+-type SiC substrate101by a laser silicide thermal treatment, thereby forming the metal silicide layer116so as to cover the n+-type drain region103formed on the rear surface side of the n+-type SiC substrate101. Subsequently, the drain wiring electrode8is formed so as to cover the metal silicide layer116. As the drain wiring electrode8, a stacked film made up of a Ti film, an Ni film and a gold (Au) film is deposited to have a thickness of 0.5 to 1 μm.

Thereafter, external wirings are electrically connected to the source wiring electrode7, the gate wiring electrode (not illustrated) and the drain wiring electrode8.

As described above, according to the first embodiment, the n++-type second source region107is formed inside the n+-type first source region106so as to be separated from the end portion of the p+-type body layer potential fixing region109and the end portion of the channel region positioned on the opposite side thereof. The impurity of the n+-type first source region106is nitride, and the impurity of the n++-type second source region107is phosphorus. Since phosphorus which is electrically active is implanted as an impurity at a high concentration in the second source region107, a contact resistance can be reduced. In addition, since the n++-type second source region107is formed to be separated from the p+-type body layer potential fixing region109and the channel, even when the phosphorus as the impurity of the second source region107is diffused in the transverse direction, a potential can be applied to the p-type body layer105without reducing the concentration of the p+-type body layer potential fixing region109. In addition, since the phosphorus is not diffused up to the channel region, a short channel effect causing a reduction in threshold voltage does not occur. Therefore, it is possible to provide an SiC power DMOSFET which is not degraded in performance due to the transverse diffusion of the phosphorus while realizing a low contact resistance.

As described above, according to this embodiment, it is possible to provide a high-performance and reliable silicon carbide semiconductor device and a manufacturing method of the silicon carbide semiconductor device even in the case where nitrogen or the like which is hard to be diffused and has a low solid-solubility limit is used as an impurity of a source diffusion layer and phosphorus which is easy to be diffused and has a solid-solubility limit higher than that of the nitrogen is used at a high concentration as an impurity of a source diffusion layer of a contact portion.

A difference between the second embodiment and the above-mentioned first embodiment lies in a method of forming the source region. Namely, in the second embodiment, an n++-type second source region208is made shallower than an n+-type first source region206as illustrated inFIG. 17, and thus the second source region208becomes equivalent to the third source region. Note that the reference numeral201indicates an n+-type SiC substrate (substrate), the reference numeral202indicates an n−-type epitaxial layer, the reference numeral203indicates an n+-type drain region, the reference numeral204indicates an SiC epitaxial substrate, the reference numeral205indicates a p-type body layer (well region), the reference numeral209indicates a p+-type body layer potential fixing region, the reference numeral210indicates a gate insulating film, the reference numeral211indicates a gate electrode, the reference numeral212indicates an interlayer insulating film, the reference numeral213indicates a metal silicide layer, the reference numeral27indicates a source wiring electrode, the reference numeral216indicates a metal silicide layer, and the reference numeral28indicates a drain wiring electrode.

<<Manufacturing Method of Silicon Carbide Semiconductor Device>>

A manufacturing method of the silicon carbide semiconductor device according to the second embodiment will be described in process order with reference toFIGS. 18 to 21.FIGS. 18 to 21are cross-sectional views illustrating a principal part in which a part of the SiC power MISFET forming region (element forming region) and a part of the peripheral forming region of the silicon carbide semiconductor device are depicted in an enlarged manner.

In the same manner as the first embodiment mentioned above, as illustrated inFIG. 18, the n−-type epitaxial layer202is formed on the surface (first main surface) of the n+-type SiC substrate (substrate)201, and the SiC epitaxial substrate204constituted of the n+-type SiC substrate201and the n+-type epitaxial layer202is formed. The impurity concentration of the n+-type SiC substrate201is, for example, in a range of 1×1018to 1×1021cm−3, and the impurity concentration of the n−-type epitaxial layer202is, for example, in a range of 1×1014to 1×1017cm−3. Subsequently, the n+-type drain region203is formed on the rear surface (second main surface) of the n+-type SiC substrate201. The impurity concentration of the n+-type drain region203is, for example, in a range of 1×1019to 1×1021cm−3.

Next, a mask (not illustrated) made of, for example, an SiO2film is formed on the surface of the n−-type epitaxial layer202. Subsequently, the p-type impurity, for example, aluminum atoms (Al) is ion-implanted to the n−-type epitaxial layer202over the mask. In this manner, the p-type body layer (well region)205is formed in the element forming region on the surface side of the n−-type epitaxial layer202, and a p-type ring205ais formed in the peripheral forming region. The depth (first depth) of the p-type body layer205and the p-type ring205afrom the surface of the epitaxial layer202is, for example, about 0.5 to 2.0 μm. In addition, the impurity concentration of the p-type body layer205and the p-type ring205ais, for example, in a range of 1×1016to 1×1019cm−3.

Next, as illustrated inFIG. 18, a mask7(SiO2film) is formed after the mask is removed. The thickness of the mask7is, for example, about 0.5 to 1.5 μm. In addition, the opening portion of the mask7is provided not only in the element forming region but also in the peripheral forming region.

Next, nitrogen atoms (N) are ion-implanted as an n-type impurity to the n−-type epitaxial layer202over the mask7, so that the n+-type first source region206is formed in the element forming region and an n+-type first guard ring206ais formed in the peripheral forming region. The depth (third depth) of the n+-type first source region206and the n+-type first guard ring206afrom the surface of the epitaxial layer202is, for example, about 0.1 to 0.35 μm. In addition, the impurity concentration of the n+-type first source region206and the n+-type first guard ring206ais, for example, in a range of 1×1018to 1×1020cm−3.

Next, as illustrated inFIG. 19, a mask8is formed so as to cover and surround the mask7and the n+-type first source region206. The film thickness of the mask8is, for example, about 0.1 to 0.5 μm, and the material thereof is SiO2.

Next, as illustrated inFIG. 20, the mask8is processed by the anisotropic dry etching method to form a sidewall made of the mask8on the side surface of the mask7. Since the sidewall made of the mask8is formed, an area of the n++-type second source region208when seen in a plan view to be formed in the subsequent process can be made smaller than that of the n+-type first source region206when seen in a plan view. Phosphors atoms (P) are ion-implanted as an n-type impurity to the n−-type epitaxial layer202over the sidewall made of the mask8and the mask7, thereby forming the n++-type second source region208and an n++-type second guard ring208ain the element forming region. The depth (fourth depth) of the n++-type second source region208and the n++-type second guard ring208afrom the surface of the epitaxial layer202is, for example, about 0.05 to 0.25 μm. In addition, the impurity concentration of the n++-type second source region208and the n++-type second guard ring208ais, for example, in a range of 1×1019to 1×1021cm−3.

Since the n++-type second source region208is formed to be shallower than the n+-type first source region206, an n++-type third source region is formed in an overlapped portion between the n+-type first source region206and the n++-type second source region208. At this time, the third source region and the second source region are formed in common. Since the n++-type second guard ring208ais formed to be shallower than the n+-type first guard ring206a, the n++-type third guard ring is formed in the overlapped portion between the n+-type first guard ring206aand the n++-type second guard ring208a. At this time, the third guard ring and the second guard ring208aare formed in common. In the second embodiment, since the source region (the n+-type first source region206and the n++-type second source region208) of the element forming region and the guard ring (the n+-type first guard ring206aand the n++-type second guard ring208a) of the peripheral forming region are formed at the same time, the source region and the guard ring have the same impurity distribution in the depth direction.

Thereafter, as illustrated inFIG. 21, in the same manner as the first embodiment mentioned above, the p+-type body layer potential fixing region209for fixing the potential of the p-type body layer205, the gate insulating film210, the gate electrode211and others are formed. Subsequently, after the interlayer insulating film212is formed on the surface of the n−-type epitaxial layer202, the opening CNT is formed in a desired region of the interlayer insulating film212, and the metal silicide layer213is formed on the respective surfaces of a part of the n++-type second source region208, a part of the n+-type first source region206and the p+-type body layer potential fixing region209which are exposed on the bottom surface of the opening CNT. Next, after the opening (not illustrated) reaching the gate electrode211is formed in the interlayer insulating film212, the source wiring electrode27electrically connected to a part of the n++-type second source region208through the metal silicide layer213and the gate wiring electrode (not illustrated) electrically connected to the gate electrode211are formed. Note that the gate wiring electrode is fabricated by the same process as that of the source wiring electrode except the polycrystalline silicon film. Next, a passivation film215to protect the electrode is formed. Then, after the metal silicide layer216is formed so as to cover the n+-type drain region203formed on the rear surface side of the n+-type SiC substrate201, the drain wiring electrode28is formed so as to cover the metal silicide layer216.

As described above, according to the second embodiment, the n++-type second source region208is formed inside the n+-type first source region206so as to be separated from the end portion of the p+-type body layer potential fixing region209and the end portion of the channel region positioned on the opposite side thereof. The impurity of the n+-type first source region206is nitrogen, and the impurity of the n++-type second source region208is phosphorus. Since phosphorus which is electrically active is implanted as an impurity at a high concentration in the second source region208, a contact resistance can be reduced. In addition, since the n++-type second source region208is formed to be shallow, the energy necessary for implanting the phosphorus is small, and the phosphorus is less diffused in the transverse direction. Therefore, the diffusion of phosphorus in the transverse direction is reduced compared to the first embodiment, so that a reduction in concentration of the p+-type body layer potential fixing region209is more suppressed and a potential can be applied to the p-type body layer205. In addition, since the diffusion of the phosphorus up to the channel region can be suppressed more reliably, the short channel effect causing a reduction in threshold voltage can also be suppressed. Therefore, it is possible to provide an SiC power DMOSFET which is not degraded in performance due to the transverse diffusion of the phosphorus while realizing a low contact resistance.

As described above, according to this embodiment, it is possible to provide a high-performance and reliable silicon carbide semiconductor device and a manufacturing method of the silicon carbide semiconductor device even in the case where nitrogen or the like which is hard to be diffused and has a low solid-solubility limit is used as an impurity of a source diffusion layer and phosphorus which is easy to be diffused and has a solid-solubility limit higher than that of the nitrogen is used at a high concentration as an impurity of a source diffusion layer of a contact portion. In addition, since the second source region is formed to be shallow, it is possible to obtain the higher reliability than that of the first embodiment.

A difference between the third embodiment and the above-mentioned first and second embodiments lies in a method of forming the source region. Namely, in the third embodiment, the depth of an n++-type second source region308is made equal to the depth of an n+-type first source region306as illustrated inFIG. 22. Note that the reference numeral301indicates an n+-type SiC substrate (substrate), the reference numeral302indicates an n−-type epitaxial layer, the reference numeral303indicates an n+-type drain region, the reference numeral304indicates an SiC epitaxial substrate, the reference numeral305indicates a p-type body layer (well region), the reference numeral309indicates a p+-type body layer potential fixing region, the reference numeral310indicates a gate insulating film, the reference numeral311indicates a gate electrode, the reference numeral312indicates an interlayer insulating film, the reference numeral313indicates a metal silicide layer, the reference numeral37indicates a source wiring electrode, the reference numeral316indicates a metal silicide film, and the reference numeral38indicates a drain wiring electrode.

<<Manufacturing Method of Silicon Carbide Semiconductor Device>>

A manufacturing method of the silicon carbide semiconductor device according to the third embodiment will be described in process order with reference toFIGS. 23 to 26.FIGS. 23 to 26are cross-sectional views illustrating a principal part in which a part of the SiC power MISFET forming region (element forming region) and a part of the peripheral forming region of the silicon carbide semiconductor device are depicted in an enlarged manner.

In the same manner as the first and second embodiments mentioned above, as illustrated inFIG. 23, the n−-type epitaxial layer302is formed on the surface (first main surface) of the n+-type SiC substrate (substrate)301, and the SiC epitaxial substrate304constituted of the n+-type SiC substrate301and the n−-type epitaxial layer302is formed. The impurity concentration of the n+-type SiC substrate301is, for example, in a range of 1×1018to 1×1021cm−3, and the impurity concentration of the n−-type epitaxial layer302is, for example, in a range of 1×1014to 1×1017. Subsequently, the n+-type drain region303is formed on the rear surface (second main surface) of the n+-type SIC substrate301. The impurity concentration of the n+-type drain region303is, for example, in a range of 1×1019to 1×1021cm−3.

Next, a mask (not illustrated) made of, for example, an SiO2film is formed on the surface of the n−-type epitaxial layer302. Subsequently, the p-type impurity, for example, aluminum atoms (Al) is ion-implanted to the n−-type epitaxial layer302over the mask. In this manner, the p-type body layer (well region)305is formed in the element forming region on the surface side of the n−-type epitaxial layer302, and a p-type ring305ais formed in the peripheral forming region. The depth (first depth) of the p-type body layer305and the p-type ring305afrom the surface of the epitaxial layer302is, for example, about 0.5 to 2.0 μm. In addition, the impurity concentration of the p-type body layer305and the p-type ring305ais, for example, in a range of 1×1016to 1×1019cm−3.

Next, as illustrated inFIG. 23, a mask9(SiO2film) is formed after the mask is removed. The thickness of the mask9is, for example, about 0.5 to 1.5 μm. In addition, the opening portion of the mask9is provided not only in the element forming region but also in the peripheral forming region.

Next, nitrogen atoms (N) are ion-implanted as an n-type impurity to the n−-type epitaxial layer302over the mask9, so that the n+-type first source region306is formed in the element forming region and an n+-type first guard ring306ais formed in the peripheral forming region. The depth (third depth) of the n+-type first source region306and the n+-type first guard ring306afrom the surface of the epitaxial layer302is, for example, about 0.1 to 0.35 μm. In addition, the impurity concentration of the n+-type first source region306and the n+-type first guard ring306ais, for example, in a range of 1×1018to 1×1020cm−3.

Next, as illustrated inFIG. 24, a mask10is formed so as to cover the mask9and the n+-type first source region306. The film thickness of the mask10is, for example, about 0.1 to 0.5 μm, and the material thereof is SiO2.

Next, as illustrated inFIG. 25, the mask10is processed by the anisotropic dry etching method to form a sidewall made of the mask10on the side surface of the mask9. Since the sidewall made of the mask10is formed, an area of the n++-type second source region308when seen in a plan view to be formed in the subsequent process can be made smaller than that of the n+-type first source region306when seen in a plan view. Phosphors atoms (P) are ion-implanted as an n-type impurity to the n−-type epitaxial layer302over the sidewall made of the mask10and the mask9, thereby forming the n++-type second source region308and an n++-type second guard ring308ain the element forming region. The depth (fourth depth) of the n++-type second source region308and the n++-type second guard ring308afrom the surface of the epitaxial layer302is, for example, about 0.1 to 0.35 μm. In addition, the impurity concentration of the n++-type second source region308and the n++-type second guard ring308ais, for example, in a range of 1×1019to 1×1021cm−3.

Since the n++-type second source region308and the n++-type second guard ring308aare formed to have the depth equal to those of the n+-type first source region306and the n+-type first guard ring306a, an n++-type third source region is formed in an overlapped portion between the n+-type first source region306and the n++-type second source region308. At this time, the third source region and the second source region are formed in common. Since the n++-type second guard ring308ais formed to have the depth equal to that of the n+-type first guard ring306a, the n++-type third guard ring is formed in an overlapped portion between the n+-type first guard ring306aand the n++-type second guard ring308a. At this time, the third guard ring and the second guard ring308aare formed in common. In the third embodiment, since the source region (the n+-type first source region306and the n++-type second source region308) of the element forming region and the guard ring (the n+-type first guard ring306aand the n++-type second guard ring308a) of the peripheral forming region are formed at the same time, the source region and the guard ring have the same impurity distribution in the depth direction.

Thereafter, as illustrated inFIG. 26, in the same manner as the first and second embodiments mentioned above, the p+-type body layer potential fixing region309for fixing the potential of the p-type body layer305, the gate insulating film310, the gate electrode311and others are formed. Subsequently, after the interlayer insulating film312is formed on the surface of the n−-type epitaxial layer302, the opening CNT is formed in a desired region of the interlayer insulating film312, and the metal silicide layer313is formed on the respective surfaces of a part of the n+-type second source region308, a part of the n+-type first source region306and the p+-type body layer potential fixing region309which are exposed on the bottom surface of the opening CNT. Next, after the opening (not illustrated) reaching the gate electrode311is formed in the interlayer insulating film312, the source wiring electrode37electrically connected to a part of the n++-type second source region308through the metal silicide layer313and the gate wiring electrode (not illustrated) electrically connected to the gate electrode311are formed. Next, a passivation film315to protect the electrode is formed. Then, after the metal silicide layer316is formed so as to cover the n+-type drain region303formed on the rear surface side of the n+-type SiC substrate301, the drain wiring electrode38is formed so as to cover the metal silicide layer316.

As described above, according to the third embodiment, the n++-type second source region308is formed inside the n+-type first source region306so as to be separated from the end portion of the p+-type body layer potential fixing region309and the end portion of the channel region positioned on the opposite side thereof. The impurity of the n+-type first source region306is nitrogen, and the impurity of the n++-type second source region308is phosphorus. Since phosphorus which is electrically active is implanted as an impurity at a high concentration in the second source region308, a contact resistance can be reduced. In addition, since the first source region306and the second source region308are deeply formed to have the same depth, the sheet resistance can also be reduced. In addition, since the n++-type second source region308is formed to be separated from the p+-type body layer potential fixing region309and the channel, even when the phosphorus as the impurity of the second source region308is diffused in the transverse direction, a potential can be applied to the p-type body layer305without reducing the concentration of the p+-type body layer potential fixing region309. In addition, since the phosphorus is not diffused up to the channel region, a short channel effect causing a reduction in threshold voltage does not occur. Therefore, it is possible to provide an SiC power DMOSFET which is not degraded in performance due to the transverse diffusion of the phosphorus while realizing a low contact resistance.

As described above, according to this embodiment, it is possible to provide a high-performance and reliable silicon carbide semiconductor device and a manufacturing method of the silicon carbide semiconductor device even in the case where nitrogen or the like which is hard to be diffused and has a low solid-solubility limit is used as an impurity of a source diffusion layer and phosphorus which is easy to be diffused and has a solid-solubility limit higher than that of the nitrogen is used at a high concentration as an impurity of a source diffusion layer of a contact portion.

In the foregoing, the present invention has been described in detail, and the main embodiments of the invention will be enumerated below.

The embodiment relates to an SiC power MISFET in which a p-type body layer is formed in an n-type epitaxial layer formed on a front surface side of a substrate, a source region, a body layer potential fixing region and a channel region are formed in the p-type body layer, a gate insulating film is formed to be in contact with the channel region, a gate electrode is formed to be in contact with the gate insulating film, and an n-type drain region is formed on a rear surface side of the substrate. The source region is constituted of an n-type first source region which contains nitrogen as an impurity, an n-type second source region which is formed in the first source region at a position separated from the channel and the body layer potential fixing region and contains phosphorus as an impurity, and a third source region in which the first source region and the second source region are overlapped.

The embodiment relates to a manufacturing method of an SiC power MISFET including the following steps. An n-type epitaxial layer is formed on a front surface side of a substrate, and an n-type drain region is formed on a rear surface side of the substrate. After a p-type body layer having a first depth from a surface of the epitaxial layer is formed in the epitaxial layer with using a first mask, nitrogen is implanted into the body layer with using a second mask to form a first source region having a third depth from the surface of the epitaxial layer, a third mask is formed on the surface of the epitaxial layer so as to cover the second mask, and a sidewall made of the third mask is formed on a side surface of the second mask by processing the third mask by dry etching. Subsequently, phosphorus is implanted into the first source region with using the second mask and the sidewall of the third mask formed on the side surface of the second mask, thereby forming a second source region having a fourth depth from the surface of the epitaxial layer and simultaneously forming a third source region having a fifth depth in which the first source region and the second source region are overlapped. Sequentially, a p-type body layer potential fixing portion having a second depth from the surface of the epitaxial layer is formed with using a fourth mask.

For example, materials, conductivity types, manufacturing conditions and others of the respective parts are not limited to those described in the embodiments above, and it is a matter of course that various modifications can be made thereto. Herein, for the sake of explanation, the description has been made on the assumption that the conductivity types of the semiconductor substrate and the semiconductor film are fixed, but the conductivity types are not limited to those described in the embodiments above.

INDUSTRIAL APPLICABILITY

The present invention can be applied to a silicon carbide power semiconductor device which is used for high breakdown voltage and large current.

EXPLANATION OF REFERENCE CHARACTERS