Uniform critical dimension size pore for PCRAM application

A memory cell and a method of making the same, that includes insulating material deposited on a substrate, a bottom electrode formed within the insulating material, a plurality of insulating layers deposited above the bottom electrode and at least one of which acts as an intermediate insulating layer. A via is defined in the insulating layers above the intermediate insulating layer. A channel is created for etch with a sacrificial spacer. A pore is defined in the intermediate insulating layer. All insulating layers above the intermediate insulating layer are removed, and the entirety of the remaining pore is filled with phase change material. An upper electrode is formed above the phase change material.

FIELD OF THE INVENTION

The present invention is directed toward computer memory, and more particularly to a non-volatile phase change memory device.

BACKGROUND OF THE INVENTION

There are two major groups in computer memory: non-volatile memory and volatile memory. Constant input of energy in order to retain information is not necessary in non-volatile memory but is required in the volatile memory. Examples of non-volatile memory devices are Read Only Memory, Flash Electrical Erasable Read Only Memory, Ferroelectric Random Access Memory, Magnetic Random Access Memory, and Phase Change Memory. Examples of volatile memory devices include Dynamic Random Access Memory (DRAM) and Static Random Access Memory (SRAM). The present invention is directed to phase change memory. In phase change memory, information is stored in materials that can be manipulated into different phases. Each of these phases exhibit different electrical properties which can be used for storing information. The amorphous and crystalline phases are typically two phases used for bit storage (1's and 0's) since they have detectable differences in electrical resistance. Specifically, the amorphous phase has a higher resistance than the crystalline phase.

Glass chalcogenides are a group of materials commonly utilized as phase change material. This group of materials contain a chalcogen (Periodic Table Group 16/VIA) and a more electropositive element. Selenium (Se) and tellurium (Te) are the two most common semiconductors in the group used to produce a glass chalcogenide when creating a phase change memory cell. An example of this would be Ge2Sb2Te5(GST), SbTe, and In2Se3. However, some phase change materials do not utilize chalcogen, such as GeSb. Thus, a variety of materials can be used in a phase change material cell as long as they can retain separate amorphous and crystalline states.

The amorphous and crystalline phases in phase change material are reversible. This is achieved by forming a via lined with insulating material. A lower electrode (also referred to as the source) is formed below the phase change material and an upper electrode (also referred to as the drain) is formed above the phase change material. This allows an electrical pulse to travel through the phase change material when electricity is applied from the source to the drain. Due to ohmic heating, the phase change material changes its phase. A relatively high intensity, short duration current pulse with a quick transition at the trailing edge results in the phase change material melting and cooling quickly. The phase change material does not have the time to form organized crystals, thereby creating an amorphous solid phase. A relatively low intensity, long duration pulse allows the phase change material to heat and slowly cool, thus crystallizing into the crystalline phase. It is possible to adjust the intensity and duration of the pulses to produce a varying degree of resistance for multi-bit storage in a memory cell.

A phase change cell is read by applying a pulse of insufficient strength to program, i.e. to alter the phase of, the material. The resistance of this pulse can then be read as a “1” or “0”. The amorphous phase which carries a greater resistance is generally used to represent a binary 0. The crystalline phase which carries a lower resistance can be used to represent a binary 1. In cells where there are varying degrees of resistance, the phases can be used to represent, for example, “00”, “01”, “10”, and “11”.

SUMMARY OF THE INVENTION

An exemplary aspect of the invention is a method of forming a memory cell. The method for forming the memory cell begins with standard front end of line (FEOL) wafers generally forming with a plurality of insulating layers over a substrate. A bottom electrode is formed within at least one of the insulating layers. A via is defined by etching through at least one of the insulating layers above the bottom electrode. The via and bottom electrode are separated by at least one intermediate insulating layer. A sacrificial spacer is formed in the via above the intermediate insulating layer. A channel with a smaller diameter than the diameter of the via is defined within the sacrificial spacer walls. A pore is created in the intermediate insulating layer below the sacrificial spacer and above the bottom electrode such that the channel continues through the intermediate insulating layer to the bottom electrode. The sacrificial spacer is then removed and phase change material is deposited into the pore, filling the entire pore. Finally, an upper electrode is deposited above the phase change material.

Another exemplary aspect of the present invention is a memory cell. The memory cell includes a substrate, an insulating layer formed over the substrate, a bottom electrode formed within the insulating layer, a pore in the insulating layer above the bottom electrode, phase change material formed within the pore, with the phase change material filling the entire pore, and an upper electrode formed above the phase change material.

Another exemplary aspect of the present invention is an integrated circuit comprising one or more memory cells with at least one of the memory cells comprising a substrate, an insulating layer formed over the substrate, a bottom electrode formed within the insulating layer, a pore in the insulating layer above the bottom electrode, phase change material formed within the pore, with the phase change material filling the entire pore, and an upper electrode formed above the phase change material. Additionally, the upper electrode may be patterned for bit line connections.

DETAILED DESCRIPTION OF THE INVENTION

The present invention is described herein with reference to embodiments of the invention. Throughout the description of the invention reference is made toFIGS. 1-8. When referring to the figures, like structures and elements shown throughout are indicated with like reference numerals.

FIG. 1illustrates the cross sectional view of an exemplary memory cell102contemplated by the present invention. The exemplary memory cell102is comprised of an insulating layer104, a bottom electrode106, an intermediate insulating layer108, a pore114within the intermediate insulating layer that contains phase change material110, and an upper electrode112. The memory cell102is typically formed on a substrate with metal-oxide-semiconductor field-effect transistors (MOSFETs) (not shown). Other switching devices known to those skilled in the art, such as junction FETs and bipolar junction transistors, may be used with the present invention.

InFIG. 2an exemplary embodiment of a starting front end of line (FEOL) wafer with insulating layer depositions is shown. The exemplary FEOL wafer is comprised of the insulating layer104. The insulating layer104may be composed of, but not limited to, silicon dioxide (SiO2). The bottom electrode106may be, but is not limited to, titanium nitride (TiN), tungsten (W), silver (Ag), gold (Au), or aluminum (Al).

In a particular embodiment of the invention, the thickness of the insulating layer104and the bottom electrode106is greater than 50 nm. The dimension of the bottom electrode is such that its diameter is larger than the diameter of the pore114(seeFIG. 1) plus tolerance for overlay so that adequate electrical contact is made. In a particular embodiment the diameter of the bottom electrode106is at least 80 nm.

Insulating layers disposed above the starting FEOL wafers are the intermediate insulating layer108, a silicon dioxide layer202, and an upper insulating layer204. The intermediate insulating layer108may be comprised of, but not limited to, silicon nitride (SiNX). The silicon dioxide layer202may also be comprised of, but not limited to, amorphous silicon/polysilicon (Si), or any material which can be removed selectively to the intermediate insulating layer108.) The upper insulating layer204may also be comprised of silicon nitride. The insulating materials, SiO2and SiNX, can be formed in one plasma enhanced chemical vapor deposition (PECVD) chamber sequentially or formed separately. In a particular embodiment of the invention, the intermediate insulating layer108is approximately 30 nm thick, the silicon dioxide layer202approximately 250 nm thick, and the upper insulating layer204is approximately 30 nm. It is contemplated that substitute insulating materials may be used for the insulating layer104with the present invention, such silicon oxycarbide (SiOC). The intermediate insulating layer108and upper insulating layer204may also be comprised of alternate insulating materials. An example of alternate insulating materials would be the aforementioned SiO2and SiNX, aluminum oxide (Al2O3), tantalum pentoxide (Ta2O5), etc. Additionally, the SiO2layer202may be comprised of polysilicon/amorphous silicon.

In an alternate embodiment of the starting FEOL wafer with insulating layer deposition, the wafer is comprised of a silicon dioxide insulating layer104, a bottom electrode106, an intermediate insulating layer108, a silicon dioxide layer202, and an upper insulating layer204. The bottom electrode106may be, but is not limited to, titanium nitride or tungsten. The intermediate insulating layer108may be comprised of, but not limited to, SiNX. The silicon dioxide layer202may be comprised of, but not limited to, silicon dioxide and may contain any material which can be removed selectively to the intermediate insulating layer. The upper insulating layer204may be comprised of, but not limited to, silicon nitride.

Starting withFIG. 2and turning toFIG. 3, a via302is etched into the silicon dioxide layer202and upper insulating layer204. The via302stops at the intermediate insulating layer108. Defining the via302can be performed by first forming a lithography mask with photo resist (not shown) above the upper insulating layer204and the silicon layer202. The photo resist is pattern so that the area above the bottom electrode106is exposed to the proceeding etch. The etch can then be performed using an anisotropic reactive-ion etch (RIE) process. The photo resist is then stripped from the surface of the upper insulating layer204. The undercut304can be formed by performing a dilute HF wet etch where the HF attacks the silicon dioxide more rapidly than the silicon nitride or amorphous silicon. In a particular embodiment of the invention, the via302is approximately 200 nm in diameter and 250 nm in height. The undercut amount304is approximately 15 nm per side.

FIG. 4illustrates the deposition of a conformal insulating layer402and a cavity404formed therein. In one embodiment of the invention, amorphous silicon is used as the conformal insulating layer402. The conformal insulating layer402can be deposited by chemical vapor deposition (CVD). The thickness of the conformal insulating layer402should be greater than the radius of the via302in order to create the cavity404therein. The size of the undercut304in the silicon dioxide layer202correlates to the size of the cavity404formed within the conformal insulating layer402. The diameter of the cavity404is approximately twice the size of the undercut304of the silicon dioxide layer202. For example, a 30 nm undercut creates a 60 nm diameter cavity404. Furthermore, the diameter of the cavity404will be independent of the diameter of the via302, providing that the silicon dioxide layer thickness202is greater than or equal to a minimum value Hmin. Mathematically, this value can be represented by equation 1 and describes the point at which the cavity dimension is below the triangular pinch-off.
Hmin=r+√{square root over ((2r-Δ)Δ)}  Eq. 1
Here Hminis the silicon dioxide layer thickness202, Δ the size of the undercut304(half the cavity diameter) and r the radius of the via302.
In another embodiment however, the diameter of the cavity404can be modulated by the profile of the via302. Specifically, if a controlled taper angle is present in the via, the cavity diameter will decrease according to equation 2, where δ is the effective size of the reduction.

InFIG. 5, a sacrificial spacer502is defined by anisotropic selective reactive-ion etch. The etch removes all of the conformal insulating material above and below the cavity404(seeFIG. 4) and stops on intermediate insulating layer108. Additionally, the etch removes the upper insulating layer204(seeFIG. 4). A channel504is created within the sacrificial spacer502during this process. The channel allows further etching to be concentrated onto a small region of the intermediate insulating layer108above the bottom electrode106.

FIG. 6shows the process step for defining the pore114. Defining the pore114in the intermediate insulating layer108may be performed by a selective and anisotropic reactive ion etch process (to maintain the sacrificial spacer critical dimension) or by a phosphoric acid wet etch (if dimension is not critical). The phosphoric acid etches the channel504within the sacrificial spacer502into the intermediate insulating layer108, stopping at the bottom electrode106. Consequently, if a phosphoric acid wet etch is used, the upper insulating layer204is also removed. The resulting radius of the pore114is that of the channel504and substantially smaller than that of the via302(seeFIG. 4). Furthermore, the pore radius is substantially uniform throughout. The height of the pore114created is that of the thickness of the intermediate insulating layer108. Additionally, the surface of the pore114is substantially planar and perpendicular to the side surfaces of the intermediate insulating layer108. In a particular embodiment of the invention, the pore114is approximately 30 nm in diameter and 30 nm in height.

Illustrated inFIG. 7Ais the removal of the sacrificial spacer502(seeFIG. 6) and the silicon dioxide layer202. In this exemplary embodiment dilute HF is used to etch the silicon dioxide layer202. The sacrificial spacer502is etched with dilute potassium hydroxide (KOH). In an alternate embodiment, KOH is used to etch the amorphous silicon from the sacrificial spacer502. Dilute HF is used to etch the SiO2from the silicon dioxide layer202. The remaining surface is that of the intermediate insulating layer and that of the top surface of the bottom electrode106at the bottom of the pore114. To ensure that the surface is planar a chemical mechanical polish (CMP) can be performed. Additionally the CMP will remove and excess insulating material above the intermediate insulating layer108.

In another alternate embodiment, illustrated inFIG. 7B, the silicon dioxide layer202is retained. KOH is used to remove the sacrificial spacer502and the dilute HF step is omitted. A channel202H is created within the silicon dioxide layer202.

InFIG. 8A, the phase change material110is deposited above the intermediate insulating layer108and filling the entirety of the pore114. The phase change material110can be comprised of a chalcogenide. Chalcogenides are comprised of a chalcogen (Periodic Table Group 16/Group VIA) and a more electropositive element. An example of phase change materials would be GeSb and SbTe. An upper electrode112is then formed above the phase change material110. The upper electrode112may be comprised of, but not limited to, silver (Ag), gold (Au), tungsten (W), or aluminum (Al).

In this exemplary embodiment, a phase change region116is a region of the phase change material110that changes phases. The remaining phase change material110above the intermediate insulating layer108acts as a conductive passage for an electrical current. This current runs from the bottom electrode106, to the phase change region116, through the phase change material110and up to the upper electrode112. It is contemplated that the phase change material110and the upper electrode112above the intermediate insulating layer108and away of the pore114may be removed with CMP.

InFIG. 8B, the phase change material110A is deposited into the channel202H, within the silicon dioxide layer202, and into the pore114. The phase change material110A fills the entirety of the channel202H and pore114. The phase change material within the pore is the phase change region116. In this alternate embodiment, the phase change material110A does not require additional etching as explained below.

Returning toFIG. 1, the phase change material110of the completed memory cell102above the intermediate insulating layer108and the upper electrode112are patterned for bit line connections. This may be accomplished by forming a lithography mask with photo resist, performing a reactive-ion etch on the regions exposed with the mask, and then stripping the photo resist from the memory cell102. A Reactive Ion Etching or Ion Milling process can be used to etch the upper electrode112and phase-change material110.

To program the memory cell102, an electrical pulse is applied beginning at the bottom electrode106, to phase change region116, into the phase change material110above the intermediate insulating layer108, and finally up to the upper electrode112. Ohmic heating created by the resistance heats the phase change material110in the phase change region116and changes its resistive properties. A short, strong electrical pulse causes the phase change region116to heat and cool quickly resulting in an amorphous phase. A long, weaker electrical pulse causes the phase change region116to heat and cool slowly, thereby allowing the phase change region116to crystallize. The amorphous and crystalline phases exhibit, respectively, higher and lower resistive properties. The stored data can be retrieved by reading the resistance of a particular cell with an electrical pulse that is either too weak or too short to alter the phase in the phase change region116.

The manufacture of an integrate circuit of cells is achieved by producing the cells in an array so that rows and columns are formed. These cells are then linked together at the FET gates in the MOSFET creating a “word” line. The wiring, used also as the upper electrode112, is linked together perpendicular to the FET gate linkage creating a “bit” line. This allows each cell to be read or programmed individually by mapping its “word” and “bit” line coordinates.

The description of the present invention has been presented for purposes of illustration and description, but is not intended to be exhaustive or limited to the invention in the form disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the invention. The embodiment was chosen and described in order to best explain the principles of the invention and the practical application, and to enable others of ordinary skill in the art to understand the invention for various embodiments with various modifications as are suited to the particular use contemplated. Having thus described the invention of the present application in detail and by reference to embodiments thereof, it will be apparent that modifications and variations are possible without departing from the scope of the invention defined in the appended claims.