Voltage regulator circuit for RFID circuit

A voltage regulator circuit for RFID circuit utilizing a high efficiency circuit topology to minimize power consumption to provide only required current to regulate output voltage. The voltage regulator circuit does not consume quiescent current which minimizes power consumption. It does not contain inductor, transformer, op-amp, voltage and current reference which reduces complexity and die area. The voltage regulator circuit comprises a driving element, a control circuit and a sensing circuit. The driving element drives controlled current to output to ramp up the voltage. The sensing circuit measures voltage at the output and sends signal to the control circuit if the voltage reaches target value set by the internal parameters of the components. The control circuit stops the driving element when output voltage reaches the threshold minimizing current required to regulate voltage.

This application is a U.S. national stage application of International Application No. PCT/IB2020/062466, filed on Dec. 28, 2020, the entire contents of which application is hereby incorporated by reference in its entirety.

TECHNICAL FIELD OF THE INVENTION

This invention relates to voltage regulator circuit for RFID circuit and more specifically power-efficient voltage regulator circuit.

BACKGROUND OF THE INVENTION

Radio Frequency Identification (RFID) systems utilize “tags” which are attached to an object to be tracked and have been used in automated pay systems and the tracking of animals or goods in inventory or in transit.

For passive RFID tags, a front-end circuit, such as rectifier and regulator etc., is utilized to extract energy from an incoming RF signal and provide power for the processor circuits inside the RFID chip. Since the power in the RF signal that can be extracted is inversely proportional to the reading distant, the maximum reading distant of the RFID tags is limited by the power consumption of the RFID circuits.

To reduce power consumption of the circuits without affecting the processor of the RFID tags, one can reduce the power consumption of the front-end circuit such as a regulator circuit.

Document U.S. Pat. No. 7,538,673 B2 describes a voltage regulator circuit based on low drop oscillators (LDO). The LDO approach has an advantage of having no inductor or transformer which would be impossible to implement in RFID tags, however, it has many parts that consume quiescent current resulting in higher power consumption. Also, the circuit has many active circuits, such as op-amp and current reference, that adds complexity and die area.

Document U.S. Pat. No. 10,043,124 B2 describes a voltage regulator circuit based on switching regulator without inductor or transformer. This invention contains static comparator which consumes quiescent current. The circuit can be designed to consume very low current by using very large resistor, but the size would be impractical for the regulator inside RFID chip. Also, the output voltage level is set by input voltage level which is achieved by using shunt limiter to shunt excess power to ground. Therefore, if the target output voltage is low, the more power is wasted.

In view of the above, there is a need to provide an improved regulator for RFID tags that does not consume quiescent current to reduce power consumption, and does not contain op-amp, voltage or current reference to reduce complexity and die area.

SUMMARY OF THE INVENTION

The present invention relates to a voltage regulator circuit for RFID circuit comprising:first and second input nodes connected to outputs of a rectifier circuit which generate half wave rectified voltage signals from an electromagnetic wave signal received by the RFID circuit;an output node connected to RFID circuit;a control circuit connected to the first and second input nodes, a control node and a sensing node, wherein the control circuit is able to control the control node when triggered by the sensing node, the control circuit comprisesfirst and second transistors of cross-coupled pair formed the cross-coupled pair configuration,an impulse current source connected to the first and second transistors of cross-coupled pair, a first switch connected to the first and second transistors of cross-coupled pair,a second switch connected to the first and second transistors of cross-coupled pair, anda third switch connected to the first and second transistors of cross-coupled pair;a driving element coupled between the first input node and the output node and driven by the control node, wherein the driving element comprisesa driving transistor connected to the first input node and the control node to drive the current from the first input node to the output node when driven by the control node, anda blocking diode coupled between the driving transistor and the output node to block the current from flowing back to the first input node; anda sensing circuit connected to the output node, wherein the sensing circuit is capable of sensing an output voltage and signaling the other circuit when sensed voltage reaches a target value, the sensing circuit comprisesan output voltage adjusting component,a fourth switch connecting the sensing node and the output voltage adjusting component, anda fifth switch connecting the sensing node to ground.

According to the present invention, the voltage regulator circuit for RFID circuit further comprising an output capacitor connecting the output node to ground.

According to the present invention, the first switch and third switch connected with the first and second transistors of cross-coupled pair via latch node.

According to the present invention, the second switch connected with the first and second transistors of cross-coupled pair via the control node.

According to the present invention, the impulse current source connected between the first input node and the first transistor of cross-coupled pair.

According to the present invention, the first switch is configured to connect between the latch node and ground.

According to the present invention, the second switch is configured to connect between the control node and ground.

According to the present invention, the third switch is configured to connect either between the latch node and the first input node or between the latch node and ground.

According to the present invention, the first switch is transistor driven by the sensing node.

According to the present invention, the second and third switches are transistors driven by a second holding node, controlled by switch controller.

According to the present invention, the switch controller comprises first, second, third and fourth transistors of switch controller which first and second transistors of the switch controller are connected in diode-connected configuration.

According to the present invention, the transistor of switch controller is configured to connect the first input node to first holding node.

According to the present invention, the second transistor of switch controller is configured to connect the second input node to the second holding node.

According to the present invention, the third transistor of switch controller is connected to the first holding node to ground driven by the second input node.

According to the present invention, the fourth transistor of switch controller is configured to the second holding node to ground driven by the first holding node.

According to the present invention, the first and second transistors of switch controller connecting each input node to the third switch and the second switch.

According to the present invention, the first and second transistors of switch controller could be replaced with diode.

According to the present invention, the impulse current source in the control circuit comprises a current mirror having a first mirror transistor and a second mirror transistor, wherein source terminals of the first mirror transistor and the second mirror transistor connecting together with the first input node, and gates of the first mirror transistor and the second mirror transistor connecting together with the mirror node, and a current source resetting transistor coupled the mirror node to ground.

According to the present invention, the mirror node is coupled to ground via the current source resetting transistor.

According to the present invention, the current source resetting transistor is driven by the second input node.

According to the present invention, drain of the first mirror transistor is connected to the mirror node.

According to the present invention, the voltage regulator circuit for an RFID circuit further comprising a capacitor connecting the mirror node to ground.

According to the present invention, blocking diode could be replaced with a diode-connected transistor.

According to the present invention, the output voltage adjusting component is either diode, diode-connected transistor, stacks of diodes, diode-connected transistor, resistor, or any combination thereof.

According to the present invention, the target value could be internally adjusted.

According to the present invention, the fourth switch is a transistor driven by one of the input nodes.

According to the present invention, the fifth switch is a transistor driven by the other one of the input nodes.

The general purpose of this invention is to provide a power-efficient voltage regulator circuit for RFID tags which minimizes power dissipation in the voltage regulator circuit and maximizes reading range of the RFID tags. The voltage regulator circuit possesses most, if not all, of the advantages of related prior art voltage regulators while possessing none of their significant disadvantages. To attain this purpose, the developed voltage regulator circuit in which voltage regulation is achieved by utilizing a driving element with a control circuit and a sensing circuit. The driving element drives controlled current to output to ramp up the voltage. The sensing circuit measures voltage at output and sends signal to the control circuit if voltage reaches target value which is set by internal parameters of the components. The control circuit stops the driving element when output voltage reaches the target value minimizing current required to regulate voltage. Furthermore, the voltage regulator circuit does not contain any quiescence current branch which further improves the power efficiency of the voltage regulator circuit.

Another purpose of this invention is to provide a voltage regulator circuit of the type described which does not requires coupling transformers or inductors, and which may easily be constructed utilizing a relatively small area on RFID tags.

Another purpose of this invention is to provide a voltage regulator circuit of the type described which does not requires any additional voltage or current references, and which may easily be constructed utilizing a relatively small area on RFID tags.

These purposes are achieved in accordance with the circuit features which have been briefly summarized above and which will be described in further detail with reference to the accompanying drawings.

DETAILED DESCRIPTION

FIG.1shows a functional block diagram of RFID tags100. InFIG.1, the RF signal is received by an antenna101. Then, the rectifier circuit102rectifies the signal into two half-wave rectified signals with phase difference about 180 degrees, at the first input node103and second input node104. These signals are then fed into the voltage regulator circuit105which supplies the output capacitor106and provides a regulated voltage at output node107. The regulated voltage at the output node107, which stays around the predetermined value, called “target value”, with the ripple size below 10%, is used to provide power for RFID circuit108.

FIG.2shows a schematic architecture of a voltage regulator circuit105according to the present invention. The voltage regulator circuit105has two inputs connected to the first and second input nodes103and104and has one output connected to the output node107. The voltage regulator circuit105comprises control circuit201, driving element202, and sensing circuit203. The control circuit201is connected to the sensing circuit203by the sensing node204and is connected to the driving element202by the control node205. The driving element202is also connected to the sensing circuit203by the output node107.

The voltage regulator circuit105operates in a cycle which can be divided into two phases i.e. driving phase where the voltage at first input node103is more than 0 volt but the voltage at second input node104is approximately 0 volt, and reset phase where the voltage at second input node104is more than 0 volt but the voltage at first input node103is approximately 0 volt. In the driving phase, the control circuit201controls the driving element202via the control node205to drive current from the first input node103to output node107through the driving element202, resulting in rising of the voltage at the output node107. When the voltage at the output node107reaches the “target value”, the sensing circuit203will send a signal to the control circuit201via the sensing node204. Then, the control circuit201will stop the driving element202from driving current to the output node107, resulting in stopping voltage at the output node107to rise too far beyond the “target value” (typically not over 5% of the target value). In the reset phase, the voltage regulator circuit105is reset back to the initial state before starting the driving phase and be ready for the next driving phase. As a result, the voltage at the output node107will be regulated and stay around the “target value”.

The size of the output capacitor106can be adjusted to control the ripple size of the output voltage at the output node107.

FIG.3shows a control circuit201of the voltage regulator circuit according to the present invention. The control circuit201comprises first transistor of cross-coupled pair319and second transistor of cross-coupled pair320forming the cross-coupled pair configuration, an impulse current source310, a first switch321, a second switch322, and a third switch316. The first transistor of cross-coupled pair319and the second transistor of cross-coupled pair320are connected to the first switch321and the third switch316via the latch node303, and to the second switch322via the control node205. The impulse current source310is connected between the first input node103and the first transistor of cross-coupled pair319. The first switch321is connected between the node303and ground. The second switch322is connected between the control node205and ground. The third switch316is connected between the latch node303and the first input node103.

The operation of the control circuit201is initially at the start of the driving phase. All three switches321,322,316are off, and the impulse current source310supplies current for a short amount of time from the first input node103through the first transistor of cross-coupled pair319into the latch node303causing the voltage at the latch node303to be higher than the voltage at the control node205. The amount of time to supply the current must be minimized to reduce the power consumption. After the first input node103is risen enough, the first transistor of cross-coupled pair319will turn on before the opening of the second transistor of cross-coupled pair320causing the first and second transistors of cross-coupled pair319and320to latch with the latch node303as high and the control node205as ground. If the first switch321is turned on during the driving phase, the voltage at the latch node303will be pulled to ground which, in turn, triggers the first and second transistors of cross-coupled pair319and320and pulls up the voltage at the control node205equal to the voltage at the first input node103.

As would be well understood by the person skilled in the art, a switch could be implemented with a transistor or combination of transistors. The first switch321, for example, can be implemented with a transistor driven by the sensing node204to trigger the operation of the control circuit201.

The voltage at the control node205can be used to control the driving element202directly; by connecting the control node205to the driving element202, or indirectly by putting a buffer or inverter in between the control node205and the driving element202, for example.

For the reset phase, the first switch321must be turned off, and the second switch322and third switch316must be turned on to reset the latch node303and the control node205, keeping the voltage of both nodes at ground.

In another embodiment, the third switch316can be connected between the latch node303and ground instead of the first input node103and the latch node303.

FIG.4is an example circuit implementation of the switches i.e. the third switch316and the second switch322, and switch controller in the control circuit201of the voltage regulator circuit according to the present invention. The second and third switches316,322, for example, could be implemented with a transistor commonly driven by the second holding node302. The second holding node302is controlled by the switch controller to keep the third switch316and second switch322off during the driving phase, and on during the reset phase.

The switch controller comprises first, second, third and fourth transistors of switch controller311,312,313and314, which the first and second transistors of switch controller311,312are connected in diode-connected configuration. The first transistor of switch controller311connects the first input node103to first holding node301. The second transistor of switch controller312connects the second input node104to second holding node302. The third transistor of switch controller313connects the first holding node301to ground driven by the second input node104. The fourth transistor of switch controller314connects the second holding node302to ground driven by the first holding node301.

In the driving phase, the voltage at the first input node103turns on the first transistor of switch controller311, while the second input node104keeps the second and third transistors of switch controller312,313off, which makes the voltage at the first holding node301equal to the voltage at the first input node103minus an internal threshold voltage of the first transistor of switch controller311, which, in turn, turns on the fourth transistor of switch controller314and keeps the voltage at the second holding node302at approximately 0 volt, keeping the third switch316and second switch322off. While the first input node103is falling, the voltage at the first holding node301will stay at the maximum value, causing the first transistor of switch controller311to block the reverse current, to ensure that the third switch316and second switch322are off throughout the driving phase.

In the reset phase, the voltage at the first input node103is approximately 0 volt keeping the first transistor of switch controller311off. The voltage at the second input node104turns on the second and third transistors of switch controller312,313pulling the voltage at the first holding node301down to 0 volt, which, in turn, turns off the fourth transistor of switch controller314. This makes the voltage at the second holding node302equal to the voltage at the second input node104minus an internal threshold, which eventually turns on the third switch316and second switch322. While the second input node104is falling, the voltage at the second holding node302will stay at maximum value to ensure that the third switch316and second switch322are on throughout the reset phase.

In another embodiment, the first and second transistors of switch controller311and312, which are connected in diode-connected configuration, could be replaced with diode.

FIG.5is an example circuit implementation of an impulse current source310in the control circuit201of the voltage regulator circuit according to the present invention. The impulse current source310comprises a current source resetting transistor315driven by the second input node104, and a current mirror having a first mirror transistor317and a second mirror transistor318. The first mirror transistor317and second mirror transistor318have their source terminal connected to the first input node103and the gate connected to the mirror node304. The drain of the first mirror transistor317is connected to the mirror node304. The mirror node304is coupled to ground via the current source resetting transistor315. The main current path of the impulse current source310is the path through the second mirror transistor318from the first input node103to the node at another terminal which is connected to other node in the circuit.

The operation of the impulse current source310is divided into two phases including driving phase and reset phase. In the driving phase, when the first input node103is rising, the first mirror transistor317is turned on and current starts to flow through from the first input node103into the mirror node304. Due to the parasitic capacitance at the mirror node304, the voltage at the mirror node304will be rising with a delay comparing to the first input node103resulting in larger difference of voltage between the mirror node304and the first input node103. However, the voltage at the first input node103will rise at a slower rate which allows the voltage at the mirror node304to keep up and then resulting in smaller voltage difference between the mirror node304and the first input node103. During this time, the second mirror transistor318is also turned on and off, depending on the size of voltage difference, supplying current for a short amount of time. The amount of time relating to the amount of supplied current while the second mirror transistor318is on can be adjusted by increasing threshold voltage of the second mirror transistor318or decreasing threshold voltage of the first mirror transistor317. The amount of supplied current can also be adjusted by adding a capacitor coupled with the mirror node304to ground or adjusting the parasitic capacitance at the mirror node304. In another aspect of the invention, the mirror node304is also connected to the ground via the current source resetting transistor315. The current source resetting transistor315is driven by the second input node104to reset the circuit in the reset phase where the voltage at the second input node104is rising.

FIG.6is an example circuit implementation of the driving element202of the voltage regulator circuit according to the present invention. The driving element202comprises a driving transistor323connected in series with a blocking diode324. The driving transistor323is used for driving the current from one terminal to another, and the blocking diode324is used for blocking the reversing current flow.

In another embodiment, the blocking diode324could be replaced with a diode-connected transistor.

FIG.7is a sensing circuit203of the voltage regulator circuit according to the present invention. The sensing circuit203comprises two switches i.e. a fourth switch326and a fifth switch327, and an output voltage adjusting component325. The fourth switch326connects the sensing node204and the output voltage adjusting component325. The fifth switch327connects the sensing node204to ground. The operation of the sensing circuit203is divided into two phases including driving phase and reset phase.

In the driving phase, the fourth switch326must be turned on and the fifth switch327must be turned off to connect the sensing node204to the output node107with the output voltage adjusting component325. This results in the voltage at the sensing node204to become equal to the voltage at the output node107minus the voltage across the output voltage adjusting component325if the voltage at the output node107is larger than the voltage across the output voltage adjusting component325, or else the voltage at the sensing node204will stay approximately equal to 0 volt. When the voltage at the sensing node204reaches a certain voltage, it will serve as a signal to trigger the control circuit201to stop the driving element202.

Thus, the target value is equal to the summation of the voltage across the output voltage adjusting component325and the trigger voltage of the control circuit201.

The voltage across the output voltage adjusting component325can be used for setting the target value of the regulated voltage at the output node107.

The output voltage adjusting component325could be implemented with any components that could generate the voltage across the components such as a diode, a diode-connected transistor, a transistor, a resistor, stacks of diodes or any combination thereof. Using the internal parameters of the components to set the target value eliminates the need for external reference circuits and reduces the complexity, die area, and power consumption.

In the reset phase, the fourth switch326must be turned off to cut the current path from the output node107to the sensing node204, and the fifth switch327must be turned on to reset the sensing node204to ground.

FIG.8shows an example embodiment of the voltage regulator circuit of the present invention, with various stages therein corresponding to the functional stages inFIG.2. The first switch321, for example, is implemented with a transistor driven by the sensing node204. The second switch322and the third switch316, for example, are implemented with the circuit inFIG.4. The driving element202is implemented with the circuit inFIG.6, in which the driving transistor323is connected to the first input node103and directly driven by the control node205, and the blocking diode324is connected to the output node107. In the sensing circuit203, the fourth switch326, for example, is implemented with a transistor driven by the first input node103, the fifth switch327, for example, is implemented with a transistor driven by the second input node104, and the output voltage adjusting component325is implemented with a diode resulting in the target value equal to the summation of the internal threshold voltage of the output voltage adjusting component325and the first switch321.

FIG.9illustrates a graph of the voltage and current waveforms as they appear at various circuit points referenced inFIG.8.

In the driving phase, the voltage regulator circuit105operates as follows.

Firstly, the voltage at the first input node103continuously rises causing the first transistor of switch controller311to turn on, while the second input node104stays at approximate 0 volt, keeping the first and second transistors of switch controller312and313, and the current source resetting transistor315off, which makes the voltage at the first holding node301equal to the voltage at the first input node103minus an internal threshold voltage of the first transistor of switch controller311, which, in turn, turns on the fourth transistor of switch controller314and pulls the voltage at the second holding node302to ground keeping the third switch316and second switch322off. While the first input node103is falling, the voltage at the first holding node301will stay at the maximum value, causing the first transistor of switch controller311to block the reverse current to ensure that the third switch316and second switch322are off throughout the driving phase.

While the voltage at the output node107does not reach the target value, as depicted in the first two cycles of the waveforms inFIG.9, the voltage at the sensing node204stays approximately 0 volt which keeps the first switch321off.

The input node103also turns on the first mirror transistor317while the second input node104keeps the current source resetting transistor315off, which, in turn, turns on the second mirror transistor318and then supplies some current through the first transistor of cross-coupled pair319into the latch node303. Since the first and second transistors of cross-coupled pair319and320are a cross-coupled pair, the current supplied through the first transistor of cross-coupled pair319will latch the cross-coupled pair keeping the voltage at the latch node303equal to the first input node103while the voltage at the control node205is still at approximately 0 volt in the meantime. This eventually turns on the driving transistor323resulting in current flow through the driving transistor323from the first input node103to the output node107ramping up the voltage at the output node107.

When the voltage at the output node107ramps up beyond the target value during the driving phase, as depicted in the third, fourth, and fifth cycles of the waveforms inFIG.9, the voltage at the sensing node204will also ramp up and turn the first switch321on which in turn pull the voltage at the latch node303down to the ground, triggering the first and second transistors of cross-coupled pair319and320to pull the control node205up, turn off and stop the current that flows through the driving transistor323, and stop ramping up the voltage at the output node107. As a result, the voltage at the output node107will be regulated and stay around the “target value”.

Noted that the waveforms shown inFIG.9is an example; meaning, the operation of the voltage regulator circuit105could use more or less than three cycles for the voltage at the output node107to reach the target value. This depends on many factors such as the level of the target value, the capacitance of the output capacitor106, the current consumption of the RFID circuit108, the amplitude of the half-wave rectified signal at the first input node103, and etc.

In the reset phase, the voltage regulator circuit105operates as follows.

The voltage at the first input node103stays approximately 0 volt keeping the first transistor of switch controller311off. The voltage at the second input node104begins rising and turns on the second and third transistors of switch controller312and313pulling the voltage at the first holding node301down to 0 volt, which, in turn, turns the fourth transistor of switch controller314off and makes the voltage at the second holding node302equal to the voltage at the second input node104minus an internal threshold voltage of the second transistor of switch controller312, thus, turns on the third switch316and second switch322. While the second input node104is falling, the voltage at the second holding node302will hold its maximum value to keep the third switch316and second switch322on throughout the reset phase.

The third switch316keeps the voltage at the first input node103equal to the latch node303to turn off the second transistor of cross-coupled pair320and let the second switch322reset the voltage at the control node205to ground which, in turn, resets the injecting node305to ground. The second input node104also turns on the current source resetting transistor315resetting the voltage at the mirror node304to ground. The blocking diode324blocks the current from flowing back from the output node107to the first input node103. The first input node103turns off the fourth switch326blocking the current flow from the output node107to the sensing node204. The second input node104also turns on the fifth switch327resetting the voltage at the sensing node204to the ground. The circuit is then completely reset and ready to operate in the driving phase again.

The operation of the voltage regulator circuit according to the present invention does not require any branch with quiescent current, but only requires a small amount of current as necessary to operate; e.g. only a small amount of the voltage at the sensing node204is required to turn on the first switch321, thus minimizes power consumption.