Systems and methods for format efficient timing recovery in a read channel

Various embodiments of the present invention provide systems, methods and media formats for processing user data derived from a storage medium. As an example, a system is described that includes a storage medium with a series of data. The series of data includes a servo data and a user data region. The user data region includes a first synchronization pattern and a second synchronization pattern located a distance from the first synchronization pattern. A storage buffer is provided that is operable to receive at least a portion of the series of data. A retiming circuit calculates an initial phase offset and frequency offset for a defined bit within the storage buffer using a first location of the first synchronization pattern and a second location of the second synchronization pattern. An error correction loop circuit re-samples the series of data from the storage buffer based at least in part on the initial phase offset and a frequency offset.

BACKGROUND OF THE INVENTION

The present invention is related to storage media, and more particularly to systems and methods for synchronizing read operations.

A typical storage medium includes a number of storage locations where data may be stored. Data is written to the medium within areas designated for user data by positioning a read/write head assembly over the storage medium at a selected location, and subsequently passing a modulated electric current through the head assembly such that a corresponding magnetic flux pattern is induced in the storage medium. To retrieve the stored data, the head assembly is positioned over a track containing the desired information and advanced until it is over the desired data. The previously stored magnetic flux pattern operates to induce a current in the head assembly, and the induced current may then be converted to an electrical signal representing the originally recorded data.

User data regions on a storage medium are separated by wedges that include servo data. The servo data includes address and other location information. Once a desired location is identified, user data subsequent to the servo data may be read. The user data is not necessarily synchronized to the servo data, and as such a synchronizing pattern may be included within the user data region directly following the servo data. In a typical scenario, the synchronization pattern may include a very large number of bits to allow for accurate phase and frequency adjustment. Increasing the number of bits dedicated to the synchronization pattern increases the accuracy of the phase and frequency adjustment, and therefore the accuracy of the data read from the storage medium. However, increasing the number of bits dedicated to the synchronization pattern also reduces the amount of actual user data that may be stored in the user data region.

Hence, for at least the aforementioned reasons, there exists a need in the art for advanced systems and methods for increasing the accuracy of read operations and/or increasing the format efficiency of the user data region.

BRIEF SUMMARY OF THE INVENTION

The present invention is related to storage media, and more particularly to systems and methods for synchronizing read operations.

Various embodiments of the present invention provide bit density efficient systems for accurately processing user data derived from a storage medium. The systems include a storage medium with a series of data. The series of data includes a servo data and a user data region. The user data region includes a first synchronization pattern and a second synchronization pattern located a distance from the first synchronization pattern. A storage buffer is provided that is operable to receive at least a portion of the series of data. A retiming circuit calculates an initial phase offset and frequency offset for a defined bit within the storage buffer using a first location of the first synchronization pattern and a second location of the second synchronization pattern. An error correction loop circuit re-samples the series of data from the storage buffer based at least in part on the initial phase offset and a frequency offset.

In some instances of the aforementioned embodiments, the retiming circuit includes a first location calculation circuit that is operable to determine a first location corresponding to the first synchronization pattern, and a second location calculation circuit that is operable to determine a second location corresponding to the second synchronization pattern. In addition, the retiming circuit includes a frequency offset calculation circuit that is operable to calculate a frequency offset based at least in part on the first location and the second location, and an initial phase offset circuit that is operable to calculate an initial phase offset based at least in part on the frequency offset. In some cases, the first location calculation circuit includes a synchronization detector circuit is operable to detect the first synchronization pattern, and a location calculation circuit that calculates a location of where the first synchronization pattern was detected by the synchronization detector circuit. In particular cases, the first location calculation circuit further includes a T/2 interpolation circuit that provides at least an additional point from which the location of where the first synchronization pattern was detected can be found. In such cases, the location of where the first synchronization pattern was detected is within one quarter sampling period of the actual location of the first synchronization pattern. In various instances of the aforementioned embodiments, the retiming circuit includes a window signal circuit that is operable to identify a first window during which the first synchronization pattern is expected within the series of data, and to identify a second window during which the second synchronization pattern is expected within the series of data.

In some instances of the aforementioned embodiments, the error correction loop circuit includes a digital phase lock loop circuit that receives the initial phase offset and the frequency offset, and provides a bit period by bit period updated phase shift output; and an interpolator circuit that interpolates the series of data accessed from the storage buffer. In some such cases, the series of data accessed from the storage buffer is multiplied by a gain correction factor prior to being interpolated by the interpolator circuit. In various such cases, the error correction loop circuit further includes a data detector circuit that applies a detection algorithm to an output derived from the interpolator circuit to yield a data output. The bit period by bit period updated phase shift output provided by the digital phase lock loop circuit is based at least in part on the data output.

Other embodiments of the present invention provide methods for processing user data derived from a storage medium. Such methods include providing a storage medium including a series of data. The series of data includes a servo data and a user data region, with the user data region includes a first synchronization pattern and a second synchronization pattern located a distance from the first synchronization pattern. The methods further include sampling data from the storage medium and storing the resulting series of data samples to a storage buffer; determining a first location of the first synchronization pattern; determining a second location of the second synchronization pattern; calculating a frequency offset and an initial phase offset based at least in part on the first location and the second location; and interpolating at least a portion of the series of data from the storage buffer based at least in part on the frequency offset and the initial phase offset.

In some instances of the aforementioned embodiments, determining the first location of the first synchronization pattern includes: detecting the first synchronization pattern in the series of data and asserting a first synchronization pattern found signal; and determining a number of bit periods from a defined point until assertion of the first synchronization pattern found signal. In some such instances, the data is sampled at a period T to yield T samples, and determining the first location of the first synchronization pattern further includes: interpolating the series of data using a T/2 interpolator circuit to yield T/2 samples; determining which of a T sample or T/2 sample exhibits a maximum within a first synchronization pattern window; and assigning a location of the determined T sample or T/2 sample as the first location.

Yet other embodiments of the present invention provide storage systems that include a storage medium, a read/write head assembly, and a read channel circuit. The storage medium includes a series of data with a servo data and a user data region. The user data region includes a first synchronization pattern and a second synchronization pattern located a distance from the first synchronization pattern. The read/write head assembly disposed in relation to the storage medium. The read channel circuit is operable to receive an analog input derived from the read/write head assembly that corresponds to the series of data, and includes a storage buffer that is operable to receive at least a portion of the series of data, a retiming circuit that is operable to calculate an initial phase and frequency offset for a defined bit within the storage buffer using a first location of the first synchronization pattern and a second location of the second synchronization pattern; and an error correction loop circuit that re-samples the series of data from the storage buffer based at least in part on the initial phase offset and a frequency offset.

This summary provides only a general outline of some embodiments of the invention. Many other objects, features, advantages and other embodiments of the invention will become more fully apparent from the following detailed description, the appended claims and the accompanying drawings.

DETAILED DESCRIPTION OF THE INVENTION

The present invention is related to storage media, and more particularly to systems and methods for synchronizing read operations.

Various embodiments of the present invention utilize a data format including two synchronization patterns spaced a defined distance apart in a user data region. A sampling clock is used to sample input data. The first synchronization pattern is processed to determine its location, and a phase offset between the sample clock and the first synchronization pattern. An interim portion of user data subsequent to the first synchronization pattern is sampled using the sampling clock, and the resulting samples are stored to a memory. The interim portion of user data is of defined length and is followed by the second synchronous pattern. Similar to the first synchronous pattern, the second synchronous pattern is processed to determine its location. The location of the first synchronous pattern is subtracted from the location of the second synchronous pattern, and the difference is divided by the length of the intervening user data to yield a frequency offset. This frequency offset is combined with the phase offset corresponding to the first synchronous pattern to yield a phase offset for the initial data samples stored in the memory. The phase offset and frequency offset are provided as initial values to an error correction loop that interpolates the stored samples. By providing a more accurate initial phase offset and frequency offset, the ability of the error correction loop to properly interpolate the data stored in the memory is greatly enhanced.

It should be noted that while some of the discussion provided herein refers to a single user data field disposed between two consecutive servo data patterns, that it is possible to process multiple re-synchronized, user data sections disposed between two consecutive servo data patterns. Where a single user data pattern is disposed between consecutive servo patterns, the servo pattern may operate as a signal to begin processing. Alternatively, where multiple user data patterns are placed between servo data patterns, a signal indicating completion of a user data pattern may be used to signal the start of processing. One such signal may be a read gate signal found on some hard disk drives that toggles between the processing of consecutive user data patterns. Based upon the disclosure provided herein, one of ordinary skill in the art will recognize a variety of signals that may be used to signal transitions between user data patterns.

Turning toFIG. 1a, a region format101suitable for enhanced synchronization with relatively long user data regions disposed between servo data regions is shown in accordance with one or more embodiments of the present invention. Region format101includes a user data region102followed by a servo data104. Servo data104may be any servo data pattern known in the art. As an example, servo data104may include, but is not limited to, a preamble pattern, a sector address mark, a gray code and a burst. As another example, servo data104may include a preamble, a first sector address mark, a gray code, a first burst, a second sector address mark and a second burst. Such a servo data pattern is discussed in PCT Patent Application PCT/US08/78047 entitled “Systems and Methods for Improved Servo Data Operation”, and filed Sep. 29, 2008 by Ratnakar Aravind. The entirety of the aforementioned application is incorporated herein by reference for all purposes. Based upon the disclosure provided herein, one of ordinary skill in the art will recognize a variety of servo data patterns that may be utilized in accordance with different embodiments of the present invention.

A portion of user data108is written after synchronization pattern106in user data region107. User data108is followed by a second synchronization pattern110(Sync B). Synchronization pattern110is similar to synchronization pattern106in that it includes an identifiable pattern spread over a limited number of bit periods. In some cases, synchronization pattern110is identical to synchronization pattern106. In other cases, synchronization pattern110includes a different pattern and/or a different length than synchronization pattern108. The distance between synchronization pattern106and synchronization pattern110(i.e., the number of bit periods devoted to user data108) is known. To increase the accuracy of the frequency offset estimates, the distance between synchronization pattern106and synchronization pattern110is chosen to be relatively large. However, as more fully described below in relation toFIG. 2, the distance between synchronization pattern106and synchronization pattern110corresponds to the size of a memory buffer used in performing processing of the user data. Thus, the distance is chosen as a tradeoff between increased accuracy and limiting the size of memory used in processing. In one particular embodiment of the present invention, the distance is chosen between five hundred (500) and two thousand, five hundred (2500) bit periods in length. Based upon the disclosure provided herein, one of ordinary skill in the art will recognize a variety of distances (i.e., amounts of user data108) between synchronization data106and synchronization data110depending upon particular design constraints. Following synchronization data110, user data108is continued in a user data112as part of user data region107. A subsequent servo data114follows user data region107and the dual synchronization pattern interspersed in user data is followed in user data region116. In one embodiment of the present invention, a relatively long user data region is one that is greater than two thousand, five hundred bit periods in length.

In use, a data processing system receives a series of samples corresponding to user data region107. From these samples, the location of synchronization pattern106is identified along with any phase offset exhibited in the location. The data processing system continues to receive samples of user data108until an expected time later when samples of synchronization pattern110are received. The samples of synchronization pattern110are used to identify the location of synchronization pattern110. The identified locations of synchronization patterns106,110are compared to determine a phase offset and a frequency offset between the sampling clock and the actual bit periods represented in synchronization pattern106and synchronization pattern110. The frequency offset and phase offset may be used to calculate the phase and frequency offset exhibited for the initial bit periods of user data region107. The calculated initial frequency offset and phase offset may be provided to an error correction loop including a digital phase lock loop circuit that provides re-sampling (e.g., interpolating) the data from user data region107.

Turning toFIG. 1b, a region format103suitable for enhanced synchronization with medium length user data regions disposed between servo data regions is shown in accordance with various embodiments of the present invention. Region format103includes user data region102followed by servo data104. Servo data104is followed by a user data region109. User data region109begins with an unused empty space193. Following empty space193, preamble pattern195is written. Preamble pattern195is followed by first synchronization pattern106(Sync A) written in user data region109. User data108is written after synchronization pattern106in user data region109. User data108is followed by synchronization pattern110(Sync B). In this case, because only a relatively small amount of user data is to be written in user data region109, synchronization pattern110is written at the end of user data region109and followed thereafter by subsequent servo data114. The distance between synchronization pattern106and synchronization pattern110corresponds to the total amount of data stored in user data108. Subsequent servo data114follows user data region109and the dual synchronization pattern interspersed in user data is followed in user data region116. In one embodiment of the present invention, a medium length user data region is between five-hundred (500) bit periods in length and two thousand, five hundred (2500) bit periods in length.

In use, a data processing system receives a series of samples corresponding to preamble synchronization pattern106. From these samples, the location of synchronization pattern106is identified along with any phase offset exhibited in the location. The data processing system continues to receive samples of user data108until an expected time later when samples of synchronization pattern110are received. The samples of synchronization pattern110are used to identify the location of synchronization pattern110. The identified locations of synchronization patterns106,110are compared to determine a phase offset and a frequency offset between the sampling clock and the actual bit periods represented in synchronization pattern106and synchronization pattern110. The frequency offset and phase offset may be used to calculate the phase and frequency offset exhibited for the initial bit periods of user data region109. The calculated initial frequency offset and phase offset may be provided to an error correction loop including a digital phase lock loop circuit that provides re-sampling (e.g., interpolating) the data from user data region109.

Turning toFIG. 1c, a region format105suitable for enhanced synchronization relatively short user data regions disposed between servo data regions is shown in accordance with various embodiments of the present invention. Region format105includes user data region102followed by servo data104. Servo data104is followed by a user data region111. User data region109begins with an unused empty space193. Following empty space193, preamble pattern195is written. Preamble pattern195is followed by first synchronization pattern106(Sync A) written in a user data region109. In this case, the overall length of user data region111is so short that use of two synchronization patterns would result in an unacceptable level of overhead and/or the distance between the two synchronization patterns would be so close together that they would not provide a high degree of accuracy. In such a case, only a single synchronization pattern is used followed by user data108. User data108is followed by subsequent servo data114and the synchronization pattern interspersed in user data region116. In one embodiment of the present invention, a relatively short user data region is one that is less than five hundred (500) bit periods in length.

Turning toFIG. 2, a block diagram of a data processing circuit200for processing enhanced user data synchronization patterns in accordance with some embodiments of the present invention. Among other things, data processing circuit200includes an error correction loop299that is initialized by initial phase and frequency offsets232calculated by a sync based retiming circuit230. One embodiment of sync based retiming circuit230is discussed below in relation toFIG. 3. Data processing circuit200includes a read/write head assembly210that senses a magnetic field205stored on a storage medium (not shown) and converts the sensed information to an electrical signal212. Electrical signal212is provided to an analog processing block213as is known in the art, and the output of analog processing block213is provided to a preamplifier215that amplifies the signal and provides a corresponding amplified signal217. An analog to digital converter220receives amplified signal217and converts it to a series of digital samples222each corresponding to a time instant governed by a sample clock224. Digital samples222are provided to a sync based retiming circuit230that operates to detect synchronization pattern106and synchronization pattern110, and based thereon to calculate initial phase and frequency offsets232that are provided to a digital phase lock loop circuit235.

In addition, digital samples222are stored to a user data buffer240. User data buffer240may be any memory capable of storing and later providing access to digital samples222. In some embodiments of the present invention, user data buffer240is a first-in/first-out memory as are known in the art. User data buffer240may be sized to allow storage of slightly more than the amount of data expected in the user data region up to the end of synchronization pattern110. This allows for the processing of synchronization pattern106and synchronization pattern110before re-sampling or interpolation of the previously stored samples from the user data region starts. Serial data222is pulled from user data buffer240and provided to a multiplier circuit245that is part of error correction loop299where it is multiplied by a gain factor249to yield an output247. Gain factor249is a variable gain correction that is applied to correct any gain error in the analog input circuit. Output247is provided to an interpolator circuit250that interpolates output247based upon a phase shift output237from digital phase lock loop circuit235.

Interpolator circuit250provides an interpolated output252to a digital finite impulse response filter255that provides a filtered output257. Digital finite impulse response filter255may be any digital finite response filter known in the art. In some cases, digital finite impulse response filter255is an adaptive filter as are known in the art. A baseline correction value259is added to filtered output257by an adder circuit260to yield an output262. Baseline correction value259is operable to remove any DC offset or perform any other needed baseline correction. Output262is provided to a detector circuit265that yields a data output270. Detector circuit265may be any detector circuit known in the art including, but not limited to, a Viterbi algorithm detector or a low density parity check decoder as are known in the art. Data output270is provided to a target filter280that provides a target output282, and to a digital phase lock loop look up table290that provides a table value292. Target filter280may be any filter known in the art that is capable of conforming an input to a target. In some cases, target filter280is a three tap digital finite impulse response filter as are known in the art. Table value292is one of a number of values designed to adaptively adjust digital phase lock loop circuit235based upon the value of data output270.

In addition, output262is provided to a delay circuit275that provides a delayed output277. Delayed output277is output262delayed an amount corresponding to the time required to process output262through detector circuit265and target filter280. Said another way, delayed output277and target output182are aligned in time by delay circuit275. Target output282is subtracted from delayed output277using an adder circuit285to yield an error value287. Error value287is provided to digital phase lock loop circuit235where it is used along with table value292to adjust phase shift output237that is provided to interpolator circuit250. It should be noted that error correction loop299from output247to phase shift output237, may be done with other error correction loops known in the art that are capable of receiving initial phase and frequency offsets232, and beginning operation based upon the received offsets. In some cases, error correction loop299may be the same error correction loop operating in systems relying on a single synchronizing pattern.

In operation, data input205is sensed from a magnetic storage medium and processed into digital samples222. Digital samples222are sequentially queried to identify synchronization pattern106and synchronization pattern110. Once synchronization pattern110has been detected, an expected distance and an actual distance between the two is used to calculate initial phase and frequency offsets232as is more dully described below in relation toFIG. 3.

While awaiting detection of synchronization pattern110, digital samples are stored in user data buffer240. Once synchronization pattern110is received and initial phase and frequency offsets232are available, initial phase and frequency offsets232are provided to digital phase lock loop circuit235. Initial phase and frequency offsets232may provide a phase and frequency offset to any bit within those stored in user data buffer240where processing is to begin. In some cases, this is the initial bit in the user data region from which synchronization pattern106and synchronization pattern110are derived. At this point, data samples representing the user data region are sequentially pulled from user data buffer240, gain adjusted and interpolated by interpolator circuit250. The interpolated data is processed through detector circuit265. For each processed bit, error value287is generated and provided to digital phase lock loop circuit235. Digital phase lock loop circuit235generates an updated phase offset for each bit. The updated phase offset is provided by digital phase lock loop circuit235to interpolator circuit250where it is used to interpolate the next data sample pulled from user data buffer240. This process is repeated for each bit of user data108and where available, user data112is processed.

By using two synchronizing patterns (i.e., synchronizing pattern106and synchronizing pattern110) to calculate the initial phase and frequency offsets, error correction loop299including digital phase lock loop circuit235is more able to accurately lock and track the phase and frequency of data samples pulled from user data buffer240. In particular, use of a single synchronizing pattern allows for somewhat accurate determination of a phase offset corresponding to the data near the synchronizing pattern. However, the phase shift continues to change over the course of the user data due to frequency offset. Error correction loop299attempts to correct for the frequency offset by changing the interpolation performed by interpolator circuit250to account for the frequency offset and its effect on phase offset over time. Where the frequency offset is significant, the error correction loop299may not be able to recover with sufficient speed resulting in data errors. By using the second synchronization pattern, the initial frequency offset can be accurately calculated. This frequency offset can be used to correctly adjust not only the phase offset, but also the initial frequency allowing the error correction loop including the digital phase lock loop circuit to more quickly lock to the phase and frequency of the data.

Turning toFIG. 3, a block diagram of a processing system300that processes user data synchronization patterns to yield a frequency offset and a phase offset in accordance with some embodiments of the present invention. Processing system300includes a digital finite impulse response filter310that receives a data input stream305and provides a filtered output312. Digital finite impulse response filter310is a replica of digital finite impulse response filter255, and uses adaptive taps that were derived for the prior sector. Digital finite impulse response filter310may be any digital finite response filter known in the art. Filtered output312is provided to both a sync A detector circuit315and a sync B detector circuit325. Sync A detector circuit315compares the received input with a known pattern to determine whether it matches synchronization pattern106. When synchronization pattern106is detected, a sync A found output317is asserted. In some cases, sync A detector circuit315only allows assertion of sync A found output317within a defined window (i.e., during assertion of a sync A window signal396) where synchronization pattern106is expected to be found. For example, sync A detector circuit315may only assert sync A found output317within N and M bit periods of the end of servo data104as determined by a window signals circuit390. Window signals circuit390may receive a sync A found signal352, a preamble found signal392and a sampling clock394. In this case, N may be the length of synchronization pattern106less a small number of bit periods and M may be the length of synchronization pattern106plus a small number of bit periods. By limiting the window in this way, false positives on sync A found output317may be reduced or eliminated. Similarly, sync B detector circuit325compares the received input with a known pattern to determine whether it matches synchronization pattern110. When synchronization pattern110is detected, a sync B found output327is asserted. In some cases, sync B detector circuit325only allows assertion of sync B found output327within a defined window (i.e., during assertion of a sync B window signal398) where synchronization pattern110is expected to be found. For example, sync B detector circuit325may only assert sync B found output327within X and Y bit periods after assertion of sync A found output317. In this case, X may be the expected distance between synchronization pattern106and synchronization pattern110(i.e., the length of user data108) less a small number of bit periods and Y may be the expected distance between synchronization pattern106and synchronization pattern110plus a small number of bit periods. By limiting the window in this way, false positives on sync B found output327may be reduced or eliminated.

Sync A found output317is provided directly to a sync A location and phase detection circuit340, and to a T/2 interpolation circuit330that interpolates the sync A output317based on a half rate frequency and provides an interpolated output332to sync A location and phase detection circuit340. Sync A location and phase detection circuit340compares the magnitude of sync A found output317and interpolated output332. The input with the greatest magnitude is identified as being closest to the actual location of synchronization pattern106, and this location is stored as the location of synchronization pattern106. By using only sync A found output317, the location can be found within T/2, however, by additionally using interpolated output332, the location can be found within T/4. It should be noted that finer interpolation may be used to allow for a more accurate identification of the location of synchronization pattern106. Sync A location and phase detection circuit340provides the location as a location output342. Also, upon identification of synchronization pattern106, a declare sync A found circuit350asserts a sync A found output352.

Similarly, sync B found output327is provided directly to a sync B location and phase detection circuit345, and to a T/2 interpolation circuit335that interpolates the sync B output327based on a half rate frequency and provides an interpolated output337to sync B location and phase detection circuit345. Sync B location and phase detection circuit345compares the magnitude of sync B found output327and interpolated output337. The input with the greatest magnitude is identified as being closest to the actual location of synchronization pattern110, and this location is stored as the location of synchronization pattern110. Again, by using only sync b found output327, the location can be found within T/2, however, by additionally using interpolated output337, the location can be found within T/4. It should be noted that finer interpolation may be used to allow for a more accurate identification of the location of synchronization pattern110. Sync B location and phase detection circuit345provides the location as a location output347. By picking maximum correlation locations for synchronization pattern106and synchronization pattern110, the process is rendered largely insensitive to gain variations.

Location output342and location output347are provided to a frequency offset calculation circuit360. Frequency offset calculation circuit360subtracts the value of location output342from the value of location output347, and divides the result by the expected distance between synchronization pattern106and synchronization pattern110to yield a frequency offset362. The following equation describes the process:

Frequency⁢⁢Offset⁢⁢362=Location⁢⁢Output⁢⁢347-Location⁢⁢Output⁢⁢342Expected⁢⁢Distance-1.
As an example, where the difference between the location outputs is 257.1 and the expected distance is 256, the calculated frequency offset is 0.00429. This frequency offset causes the phase offset to change slightly for every sample of the user data that is taken.

Frequency offset362is provided to an initial phase offset estimation circuit370along with location output342. Location output342provides the location of synchronization pattern106that is accurate to within T/4. Where frequency offset362is zero, sampling of user data108could be performed by simply adding 1T to each successive sample starting from location output342. However, as mentioned, because frequency offset362is often non-zero, the accuracy of sampling decreases over time causing data errors due to an inability of the error correction loop to adjust for a significant initial phase offset and/or frequency offset. To correct this, frequency offset362is used by initial phase estimation circuit370to calculate an accurate phase offset372corresponding to the first sample of user data108. The phase offset may be calculated in accordance with the following equation:
Phase Offset 372=Location Output 342−(BitPeriods)Frequency Offset 362,
where Bit Periods is the number of bit periods between location output342and user data108.

Turning toFIG. 4, a timing diagram400graphically depicts the process for determining the location of synchronization patterns106,110that may be used in accordance with different embodiments of the present invention. In particular, in a period410before the pattern corresponding to a synchronization pattern is received, the signal level provided by either Sync A detector circuit315or sync B detector circuit325is relatively low. Once the synchronization pattern is detected during a user data sync pattern period420the signal level provided by either Sync A detector circuit315or sync B detector circuit325increases. During user data sync pattern period420, either Sync A detector circuit315or sync B detector circuit325provides multiple levels corresponding to sample periods442,444,446as sync A output317or sync B output327. The levels correspond to locations, t(x−1), t(x) and t(x+1), respectively. In addition, T/2 interpolation circuit330or T/2 interpolation circuit335interpolate T/2 locations452,454,456and provides levels corresponding to the sample locations as interpolated output332or interpolated output337. In this case, the largest value corresponds to T/2 location454. As such, the T/2 location454is identified as the location of the synchronization pattern being processed (i.e., half way between t(x) and t(x+1)). As should be appreciated, the process graphically depicted inFIG. 4is repeated in Sync A detector circuit315for synchronization pattern106and in Sync B detector circuit325for synchronization pattern110.

In some cases, a fine phase offset estimation is utilized. The estimation includes subtracting the value corresponding to the sample succeeding (i.e., the sample 1T later) the sample exhibiting the maximum value from the sample preceding (i.e., the sample 1T before). The difference is divided by two times the maximum value in accordance with the following equation:

Phase⁢⁢Offset=K⁢Preceding⁢⁢Sample-Succeeding⁢⁢Sample2*Maximum⁢⁢Sample.
In this example, the preceding sample corresponds to T/2 location452and the succeeding sample corresponds to T/2 location456, and the maximum sample corresponds to T/2 location454. K is a normalizing scaling factor that depends on the target where the detector circuits (i.e., sync A detector circuit315and sync B detector circuit325) are implemented to use target information to determine specific coefficients used within the sync detector circuits. The target information corresponds to the detection targets used in a data detector in the circuit (e.g., a Virterbi algorithm detector, or a low density parity check decoder). As an example, where the detector circuits are two tap target filters, a K value of 0.9994 may be used where the two taps are eight and fourteen, respectively.

Turning toFIG. 5, a timing diagram500illustrates a process of interpolating buffered user data samples that may be used in relation to different embodiments of the present invention. In particular, a number of data samples each corresponding to respective sample points (t(0), t(1), t(2), t(3), t(4), t(5) and t(6)) are shown. Each of the samples are interpolated by a delta value corresponding to the particular phase offset for that sample under the control of the error correction loop299.

Turning toFIG. 6, a flow diagram600depicts a method in accordance with one or more embodiments of the present invention for processing user data synchronization patterns to yield a frequency offset and a phase offset in accordance with various embodiments of the present invention. Following flow diagram600, a series of digital samples is received and continuously queried to determine if a new read process has started (block605). In particular, it is determined whether a user data field is started in which synchronizing patterns are to be located. In some cases, toggling of a read gate signal indicates a change in user data fields. Where the read process has started (block605), the input data stream is queried to determine whether a first user data sync (e.g., synchronization pattern106) is found (block615). At the same time that the input stream is being queried for the first data sync, the received data samples are stored to a user data buffer (block635).

Once synchronization pattern106is detected (block615), the location of the synchronization pattern is calculated and stored (block620). This may be done using the approach graphically displayed inFIG. 4above and described in relation toFIG. 3above. Alternatively, the location may be determined using any other approach known in the art for identifying the location of a signal. Once synchronization pattern106is detected and its location stored (block615and block620), the series of digital samples is queried for synchronization pattern110(block625). Once synchronization pattern110is detected (block625), the location of the synchronization pattern is calculated and stored (block630). This may be done using the approach graphically displayed inFIG. 4above and described in relation toFIG. 3above.

With the locations of synchronization pattern106and synchronization pattern110established, a frequency offset is calculated (block640). This frequency offset may be calculated in accordance with the following equation:

Frequency⁢⁢Offset=Location⁢⁢of⁢⁢Pattern⁢⁢110-Location⁢⁢of⁢⁢Pattern⁢⁢106Expected⁢⁢Distance-1.
The calculated frequency offset may then be used to calculate an initial phase offset (block645). The phase offset may be calculated in accordance with the following equation:
Phase Offset=Location of Pattern 106−(BitPeriods)Frequency Offset,
where Bit Periods is the number of bit periods between the location of pattern110and the location of pattern106. The calculated phase offset and frequency offset values may then be used by an error correction loop to interpolate the earlier stored samples (block650).

Turning toFIG. 7, a storage system700including a read channel module710with a dual synchronizing pattern user data processing circuit is shown in accordance with various embodiments of the present invention. Storage system700may be, for example, a hard disk drive. Storage system700also includes a preamplifier770, an interface controller720, a hard disk controller766, a motor controller768, a spindle motor772, a disk platter774, and a read/write head776disposed in relation to the disk platter. Interface controller720controls addressing and timing of data to/from disk platter774. The data on disk platter774consists of groups of magnetic signals that may be detected by read/write head assembly776when the assembly is properly positioned over disk platter774. In one embodiment, disk platter774includes magnetic signals recorded in accordance with either a longitudinal or a perpendicular recording scheme, and including user data regions separated by servo data. The user data regions may include two synchronization patterns similar to that discussed above in relation toFIGS. 1a-1b.

In a typical read operation, read/write head assembly776is accurately positioned by motor controller768over a desired data track on disk platter774. Motor controller768both positions read/write head assembly776in relation to disk platter774and drives spindle motor772by moving read/write head assembly to the proper data track on disk platter774under the direction of hard disk controller766. Spindle motor772spins disk platter774at a determined spin rate (RPMs). Once read/write head assembly774is positioned adjacent the proper data track, magnetic signals representing data on disk platter774are sensed by read/write head assembly776as disk platter774is rotated by spindle motor772. The sensed magnetic signals are provided as a continuous, minute analog signal representative of the magnetic data on disk platter774. This minute analog signal is transferred from read/write head assembly776to read channel module710via preamplifier770. Preamplifier770is operable to amplify the minute analog signals accessed from disk platter774. In turn, read channel module710decodes and digitizes the received analog signal to recreate the information originally written to disk platter774. This data is provided as read data703to a receiving circuit. As part of decoding the received information, read channel module710performs error correction based upon the location of the first synchronization pattern and the second synchronization pattern similar to that discussed above in relation toFIGS. 1-6. A write operation is substantially the opposite of the preceding read operation with write data701being provided to read channel module710. This data is then encoded and written to disk platter774.

In conclusion, the invention provides novel systems, devices, methods and arrangements for accessing a storage medium. While detailed descriptions of one or more embodiments of the invention have been given above, various alternatives, modifications, and equivalents will be apparent to those skilled in the art without varying from the spirit of the invention. For example, one or more embodiments of the present invention may be applied to various data storage systems and digital communication systems, such as, for example, tape recording systems, optical disk drives, wireless systems, and digital subscribe line systems. Therefore, the above description should not be taken as limiting the scope of the invention, which is defined by the appended claims.