MEMORY DEVICE PERFORMING TIMING SKEW AND OFFSET CALIBRATION

A memory device includes a data input/output (I/O) pin, an output driver, a multi-level receiver and a calibrator. The output driver is connected to the data I/O pin, and generates an internal input signal based on a first clock signal. The multi-level receiver is connected to the data I/O pin, and includes a plurality of samplers. The plurality of samplers generate a plurality of decision signals by sampling the internal input signal based on a reference voltage and a second clock signal. The calibrator detects and compensates at least one of timing skew and offset associated with the plurality of samplers based on the plurality of decision signals. The internal input signal is a multi-level signal having three or more voltage levels that are different from each other.

CROSS-REFERENCE TO RELATED APPLICATION(S)

This application claims priority under 35 USC § 119 to Korean Patent Application No. 10-2023-0086319 filed on Jul. 4, 2023 in the Korean Intellectual Property Office (KIPO), the disclosure of which is herein incorporated by reference in its entirety.

BACKGROUND

1. Technical Field

Example embodiments relate generally to semiconductor integrated circuits, and more particularly to memory devices performing timing skew and offset calibration.

2. Description of the Related Art

Semiconductor memory devices may be divided into two categories depending upon whether or not they retain stored data when disconnected from a power supply. These categories include volatile memory devices, which lose stored data when disconnected from power, and nonvolatile memory devices, which retain stored data when disconnected from power. While volatile memory devices may perform read and write operations at a high speed, contents stored therein may be lost at power-off. Since nonvolatile memory devices retain contents stored therein even at power-off, they may be used to store data that needs to be retained.

Recently, as the performance of semiconductor memory devices has improved, communication speed (or interface speed) between a memory controller and a semiconductor memory device has also increased. Thus, multi-level signaling in which a plurality of bits are transmitted during one unit interval (UI) has been researched.

SUMMARY

At least one example embodiment of the present disclosure provides a memory device capable of efficiently calibrating timing skew and offset internally without an external input while receiving a signal based on a multi-level signaling scheme.

At least one example embodiment of the present disclosure provides a memory device capable of efficiently calibrating timing skew and offset internally without an external input while receiving a signal based on a non-return-to-zero (NRZ) scheme.

According to example embodiments, a memory device includes a data input/output (I/O) pin, an output driver, a multi-level receiver and a calibrator. The output driver is connected to the data I/O pin, and generates an internal input signal based on a first clock signal. The multi-level receiver is connected to the data I/O pin, and includes a plurality of samplers. The plurality of samplers generate a plurality of decision signals by sampling the internal input signal based on a reference voltage and a second clock signal. The calibrator detects and compensates at least one of timing skew and offset associated with the plurality of samplers based on the plurality of decision signals. The internal input signal is a multi-level signal having three or more voltage levels that are different from each other.

According to example embodiments, a memory device includes a data input/output (I/O) pin, an output driver, a receiver and a calibrator. The output driver is connected to the data I/O pin, and generates an internal input signal based on a first clock signal. The receiver is connected to the data I/O pin, and includes a plurality of samplers. The plurality of samplers generate a plurality of decision signals by sampling the internal input signal based on a reference voltage and a plurality of second clock signals whose phases partially overlap. The calibrator detects and compensates an offset associated with the plurality of samplers based on the plurality of decision signals. The internal input signal is a non-return-to-zero (NRZ) signal having two voltage levels that are different from each other.

According to example embodiments, a memory device includes a data input/output (I/O) pin, an output driver, a multi-level receiver and a calibrator. The output driver is connected to the data I/O pin, and generates an internal input signal based on a first clock signal. The multi-level receiver is connected to the data I/O pin, and includes a plurality of samplers. The plurality of samplers generate a plurality of decision signals by sampling the internal input signal based on a reference voltage and a second clock signal. The calibrator detects and compensates at least one of timing skew and offset associated with the plurality of samplers based on the plurality of decision signals. The plurality of samplers include a first sampler, a second sampler, a third sampler, a fourth sampler, a fifth sampler and a sixth sampler. The first sampler generates a first decision signal by sampling the internal input signal based on the reference voltage and a first sub-clock signal. The second sampler generates a second decision signal by sampling the internal input signal based on the reference voltage and a second sub-clock signal. The third sampler generates a third decision signal by sampling the internal input signal based on the reference voltage and a third sub-clock signal. The fourth sampler generates a fourth decision signal by sampling the internal input signal based on the reference voltage and a fourth sub-clock signal. The fifth sampler generates a fifth decision signal by sampling the internal input signal based on the reference voltage and a fifth sub-clock signal. The sixth sampler generates a sixth decision signal by sampling the internal input signal based on the reference voltage and a sixth sub-clock signal. The first to sixth sub-clock signals are generated based on the second clock signal. Phases of the first to fourth sub-clock signals are partially overlapped with each other, and phases of the first, fifth, and sixth sub-clock signals are the same as each other. The calibrator includes a first offset control cell and a first delay control cell. The first offset control cell determines that an offset associated with the first sampler has occurred, and adjusts an output level of the first sampler, in response to a logic level of the first decision signal being different from a logic level of each of the second, third and fourth decision signals. The first delay control cell determines that a timing skew associated with the first sampler has occurred, and adjusts a phase of the first sub-clock, in response to a logic level of the first decision signal being different from a logic level of each of the fifth and sixth decision signals.

In the memory device according to example embodiments, a self-calibration operation may be performed using the internal input signal generated from the output driver. For example, the self-calibration operation may be internally performed without the external input signal. Accordingly, the timing skew and/or the offset associated with the plurality of samplers may be efficiently compensated, and the memory device may have relatively improved or enhanced DQ margin.

DETAILED DESCRIPTION OF THE EMBODIMENTS

Various example embodiments will be described more fully with reference to the accompanying drawings, in which embodiments are shown. The present disclosure may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Like reference numerals refer to like elements throughout this application.

FIG.1is a block diagram illustrating a memory device according to example embodiments.

Referring toFIG.1, a memory device1000includes a data input/output (I/O) pin1010, an output driver1100, a multi-level receiver1200and a calibrator1300.

In some example embodiments, the memory device1000may operate based on a multi-level signaling scheme. For example, in a normal operation mode, the output driver1100may generate a multi-level signal based on multi-bit data, and the multi-level receiver1200may generate a plurality of decision signals for generating multi-bit data based on a multi-level signal. For example, the multi-level signal may have one of three or more voltage levels that are different from each other during one unit interval (UI), and the multi-bit data may include two or more bits that are different from each other. Detailed operations of the memory device1000in the normal operation mode will be described with reference toFIGS.3A and3B.

In some example embodiments, the memory device1000may operate in a calibration mode (or compensation mode) different from the normal operation mode. For example, the memory device1000may include the calibrator1300for performing an operation in the calibration mode. For example, in the calibration mode, the calibrator1300may detect and compensate (or calibrate or correct) at least one of timing skew and offset associated with (or related to) the multi-level receiver1200.FIG.1illustrates a detailed operation of the memory device1000in the calibration mode.

The output driver1100is connected to the data I/O pin1010, and generates an internal input signal IS_CAL based on a first clock signal OSC_CLK. For example, although not illustrated in detail, the output driver1100may include at least one p-type metal oxide semiconductor (PMOS) transistor and at least one n-type metal oxide semiconductor (NMOS) transistor. The at least one PMOS transistor may be connected between a power supply voltage and an output node, and the at least one NMOS transistor may be connected between the output node and a ground voltage. For example, the output driver1100may be referred to as an off-chip driver (OCD).

The multi-level receiver1200is connected to the data I/O pin1010, and includes a plurality of samplers1210. The plurality of samplers1210generate a plurality of decision signals DCS_CAL by sampling the internal input signal IS_CAL based on a reference voltage VREF_CAL and a phase-adjusted (or delay-adjusted) second clock signal S_CLK′ adjusted based on a second clock signal S_CLK that is different from the first clock signal OSC_CLK. Herein, a phase of the phase-adjusted second clock signal S_CLK′ may be the same as a phase of the second clock signal S_CLK before the second clock signal is adjusted. For example, unlike in the normal operation mode, all of the plurality of samplers1210may operate using the same reference voltage (e.g., the reference voltage VREF_CAL) in the calibration mode.

Detailed configurations of the multi-level receiver1200will be described with reference toFIGS.5,10A and10B.

In some example embodiments, when a calibration operation is performed in the calibration mode, both the output driver1100and the multi-level receiver1200may be enabled (or activated) and operate.

In some example embodiments, as will be described with reference toFIGS.6,7A,7B,7C and7D, the internal input signal IS_CAL may have a variable level (e.g., a variable voltage level), and the reference voltage VREF_CAL may have a fixed level (e.g., a fixed voltage level). In other words, a sampling operation may be performed while fixing the level of the reference voltage VREF_CAL and changing the level of the internal input signal IS_CAL. In some example embodiments, as will be described with reference toFIG.14, the internal input signal IS_CAL may have a fixed level, and the reference voltage VREF_CAL may have a variable level. In other words, a sampling operation may be performed while fixing the level of the internal input signal IS_CAL and changing the level of the reference voltage VREF_CAL.

The calibrator1300detects and compensates at least one of timing skew and offset associated with the plurality of samplers1210based on the plurality of decision signals DCS_CAL. As will be described with reference toFIGS.9A and9B, the timing skew may represent or indicate temporal errors (or differences) with respect to outputs of the plurality of samplers1210and/or temporal errors with respect to the phase-adjusted second clock signal S_CLK′ provided to the plurality of samplers1210. As will be described with reference toFIGS.13A and13B, the offset may represent or indicate errors (or differences) in output levels (e.g., voltage level) of the outputs of the plurality of samplers1210.

Detailed configurations of the calibrator1300will be described with reference toFIGS.2A,2B,5,10A and10B.

The data I/O pin1010is connected to the output driver1100and the multi-level receiver1200. For example, a pin may be a contact pad or a contact pin, but example embodiments are not limited thereto.

In some example embodiments, in the calibration mode, the at least one of the timing skew and the offset associated with the plurality of samplers1210may be detected and compensated using only the internal input signal IS_CAL, without an external input signal received from an outside (e.g., from an external device) through the data I/O pin1010. For example, in the calibration mode, the data I/O pin1010may have a high impedance (Hi-Z) state to prevent a reception of the external input signal.

The memory device1000according to example embodiments may perform a self-calibration operation using the internal input signal IS_CAL generated from the output driver1100. For example, the self-calibration operation may be internally performed without the external input signal. Accordingly, the timing skew and/or the offset associated with the plurality of samplers1210may be efficiently compensated, and the memory device1000may have relatively improved or enhanced DQ margin.

FIGS.2A and2Bare block diagrams illustrating examples of a calibrator included in a memory device according to example embodiments.

Referring toFIG.2A, a calibrator1302may include a timing skew detection circuit1304and a plurality of delay control cells1306.FIG.2Aillustrates an example where the calibrator1302detects and compensates the timing skew associated with the plurality of samplers1210.

The timing skew detection circuit1304may detect the timing skew associated with the plurality of samplers1210based on the plurality of decision signals DCS_CAL, and may generate a plurality of delay control signals DCON for controlling the plurality of delay control cells1306.

The plurality of delay control cells1306may compensate the timing skew associated with the plurality of samplers1210by adjusting a phase of the second clock signal S_CLK based on the plurality of delay control signals DCON, and may generate the phase-adjusted (or delay-adjusted) second clock signal S_CLK′. For example, the number of the plurality of delay control cells1306may be substantially equal to the number of the plurality of samplers1210. For example, the plurality of samplers1210may operate based on the phase-adjusted second clock signal S_CLK′.

Referring toFIG.2B, a calibrator1312may include an offset detection circuit1314and a plurality of offset control cells1316.FIG.2Billustrates an example where the calibrator1312detects and compensates the offsets associated with the plurality of samplers1210.

The offset detection circuit1314may detect the offset associated with the plurality of samplers1210based on the plurality of decision signals DCS_CAL, and may generate a plurality of offset control signals OCON for controlling the plurality of offset control cells1316.

The plurality of offset control cells1316may compensate the offset associated with the plurality of samplers1210based on the plurality of offset control signals OCON. For example, the number of the plurality of offset control cells1316may be substantially equal to the number of the plurality of samplers1210. For example, each of the plurality of offset control cells1316may be included in a respective one of the plurality of samplers1210.

In some example embodiments, the calibrator may include all of the timing skew detection circuit1304and the plurality of delay control cells1306inFIG.2Aand the offset detection circuit1314and the plurality of offset control cells1316inFIG.2B. In other words, the calibrator may detect and compensate both the timing skew and the offset associated with the plurality of samplers1210.

FIGS.3A and3Bare block diagrams illustrating a memory device according to example embodiments. The descriptions repeated withFIG.1will be omitted.

Referring toFIGS.3A and3B, operations of the memory device1000in the normal operation mode are illustrated.

As illustrated inFIG.3A, in the normal operation mode subsequent to the calibration mode, the memory device1000may perform a data output operation. For example, the output driver1100may generate a multi-level output signal ML_OUT based on multi-bit data MBDAT, and the multi-level output signal ML_OUT may be output through the data I/O pin1010.

In some example embodiments, the data output operation may be at least a part of a data read operation of the memory device1000. For example, when the data read operation is performed, the data output operation may be an operation of outputting the multi-bit data MBDAT read from a memory cell array (e.g., bank arrays280ato280dinFIG.22) to an external device (e.g., a memory controller20inFIG.20).

As illustrated inFIG.3B, in the normal operation mode subsequent to the calibration mode, the memory device1000may perform a data reception operation. For example, a multi-level input signal ML_IN may be received through the data I/O pin1010, and the plurality of samplers1210included in the multi-level receiver1200may generate a plurality of decision signals DCS_ML by sampling the multi-level input signal ML_IN based on a plurality of reference voltages VREF_ML and the phase-adjusted second clock signal S_CLK′. The plurality of reference voltages VREF_ML may be different from each other. For example, unlike in the calibration mode, at least some of the plurality of samplers1210may operate using different reference voltages (e.g., the plurality of reference voltages VREF_ML) in the normal operation mode.

In some example embodiments, the data reception operation may be at least a part of the data write operation of the memory device1000. For example, when the data write operation is performed, the data reception operation may be an operation of receiving the multi-level input signal ML_IN corresponding to multi-bit data to be written into the memory cell array from the external device.

In some example embodiments, when the data output operation or the data reception operation is performed in the normal operation mode, one of the output driver1100and the multi-level receiver1200may be enabled (or activated) and operate. For example, when the data output operation is performed as illustrated inFIG.3A, the output driver1100may be enabled and the multi-level receiver1200may be disabled (or deactivated). For example, when the data reception operation is performed as illustrated inFIG.3B, the multi-level receiver1200may be enabled and the output driver1100may be disabled. In some example embodiments, when the data output operation or the data reception operation is performed in the normal operation mode, the calibrator1300may be disabled. InFIGS.3A and3B, disabled components are illustrated with dotted lines.

In some example embodiments, the operation mode of the memory device1000may be externally set (e.g., set based on an external control). For example, when a calibration mode entry command is received from the external device (e.g., the memory controller20inFIG.20), the memory device1000may operate in the calibration mode, and may perform the calibration operation illustrated inFIG.1. For example, when a write command or a read command is received from the external device, the memory device1000may perform the data write operation or the data read operation, and may perform the data output operation illustrated inFIG.3Aor the data reception operation illustrated inFIG.3B.

In some example embodiments, the operation mode of the memory device1000may be internally set (e.g., set by itself). For example, at every predetermined cycle or when a predetermined operating environment is satisfied, the memory device1000may operate in the calibration mode, and may perform the calibration operation illustrated inFIG.1.

The memory device1000according to example embodiments may operate based on a multi-level signaling scheme. The multi-level signaling scheme may be used as a means of compressing the bandwidth required to transmit data at a given bit rate. In a simple binary scheme, two single symbols, usually two voltage levels, may be used to represent ‘1’ and ‘0’, and thus the symbol rate may be equal to the bit rate. In contrast, the principle of the multi-level signaling scheme may use a larger alphabet of m symbols to represent data, so that each symbol may represent more than one bit of data. As a result, the number of symbols that needs to be transmitted may be less than the number of bits (e.g., the symbol rate may be less than the bit rate), and thus the bandwidth may be compressed. The alphabet of symbols may be constructed from a number of different voltage levels. For example, in a four-level scheme, groups of two data bits may be mapped to one of four symbols. Only one symbol need be transmitted for each pair of data bits, so the symbol rate may be a half of the bit rate.

In other words, the multi-level signaling scheme may be used to increase a data transmission (or transfer) rate without increasing the frequency of data transmission and/or a transmission power of the communicated data. An example of one type of the multi-level signaling scheme is a pulse amplitude modulation (PAM) scheme, where a unique symbol of a multi-level signal may represent a plurality of bits of data. The number of possible pulse amplitudes in a digital PAM scheme may be some power of two. For example, there may be 22possible discrete pulse amplitudes in a 4-level PAM (e.g., in PAM4), there may be 23possible discrete pulse amplitudes in an 8-level PAM (e.g., in PAM8), and there may be 24possible discrete pulse amplitudes in a 16-level PAM (e.g., in PAM16). However, example embodiments are not limited thereto, and example embodiments may be applied or employed to an X-level PAM (e.g., PAM(X)) having X possible pulse amplitudes, where X is a positive integer greater than or equal to three.

FIGS.4A and4Bare diagrams for describing a multi-level signal that is input to or output from a memory device according to example embodiments.

FIG.4Aillustrates an ideal eye diagram of a data signal (e.g., a PAM4 signal) generated based on the 4-level scheme (e.g., the PAM4 scheme) that is an example of the multi-level signaling scheme (e.g., the PAM scheme).FIG.4Bis a diagram illustrated by simplifying the ideal eye diagram ofFIG.4A. For example, the PAM4 signal ofFIGS.4A and4Bmay be an example of the multi-level output signal ML_OUT inFIG.3Aor the multi-level input signal ML_IN inFIG.3B.

Referring toFIG.4A, an eye diagram may be used to indicate the quality of signals in high-speed transmissions. For example, the eye diagram may represent four symbols of a signal (e.g., ‘00,’ ‘01,’ ‘10’ and ‘11’), and each of the four symbols may be represented by a respective one of different voltage levels (e.g., voltage amplitudes) VL11, VL12, VL13and VL14. The eye diagram may be used to provide a visual indication of the health of the signal integrity, and may indicate noise margins of the data signal.

To generate the eye diagram, an oscilloscope or other computing device may sample a digital signal according to a sample period SP (e.g., a unit interval or a bit period). The sample period SP may be defined by a clock signal associated with the transmission of the measured signal. The oscilloscope or other computing device may measure the voltage level of the signal during the sample period SP to form a plurality of traces TRC. Various characteristics associated with the measured signal may be determined by overlaying the plurality of traces TRC.

The eye diagram may be used to identify a number of characteristics of a communication signal such as jitter, cross talk, electromagnetic interference (EMI), signal loss, signal-to-noise ratio (SNR), other characteristics, or combinations thereof. For example, a width W of an eye in the eye diagram may be used to indicate a timing synchronization of the measured signal or jitter effects of the measured signal. For example, the eye diagram may indicate an eye opening OP, which represents a peak-to-peak voltage difference between the various voltage levels VL11, VL12, VL13and VL14. The eye opening OP may be related to a voltage margin for discriminating between different voltage levels VL11, VL12, VL13and VL14of the measured signal.

Referring toFIG.4B, different first, second, third and fourth voltage levels VL11, VL12, VL13and VL14of the data signal that is the PAM4 signal are illustrated, and different first, second and third reference levels VLREF_H, VLREF_M and VLREF_L for sensing or detecting the level of the data signal are illustrated. For example, the number of the reference levels may be less than the number of the voltage levels of the data signal by one.

The fourth voltage level VL14that is the highest voltage level among the voltage levels VL11, VL12, VL13and VL14may be higher than the third voltage level VL13, the third voltage level VL13may be higher than the second voltage level VL12, and the second voltage level VL12may be higher than the first voltage level VL11that is the lowest voltage level among the voltage levels VL11, VL12, VL13and VL14. In addition, the first reference level VLREF_H may be a voltage level between the third and fourth voltage levels VL13and VL14, the second reference level VLREF_M may be a voltage level between the second and third voltage levels VL12and VL13, and the third reference level VLREF_L may be a voltage level between the first and second voltage levels VL11and VL12. The voltage level (e.g., the symbol) of the data signal may be decided or determined based on a result of comparing the data signal with the reference levels VLREF_H, VLREF_M and VLREF_L.

For example, when the multi-level input signal ML_IN inFIG.3Bis the PAM4 signal, the plurality of reference voltages VREF_ML used by the plurality of samplers1210may include a first reference voltage having the first reference level VLREF_H, a second reference voltage having the second reference level VLREF_M and a third reference voltage having the third reference level VLREF_L.

Hereinafter, example embodiments will be described in detail based on the PAM4 scheme. However, example embodiments are not limited thereto, and example embodiments may be applied or employed to the PAM(K) scheme having K possible pulse amplitudes.

FIG.5is a block diagram illustrating an example of a memory device ofFIG.1according to example embodiments.

Referring toFIG.5, a memory device1000amay include a data I/O pin1010, an output driver1100, a multi-level receiver1200aand a calibrator1300a.

The data I/O pin1010and the output driver1100may be substantially the same as those described with reference toFIG.1, and the descriptions repeated withFIG.1will be omitted.

The multi-level receiver1200amay include a first sampler1220, a second sampler1230and a third sampler1240.

The first sampler1220may generate a first decision signal DO by sampling the internal input signal IS_CAL based on the reference voltage VREF_CAL and a phase-adjusted second clock signal S_CLK_D0′. The second sampler1230may generate a second decision signal D1by sampling the internal input signal IS_CAL based on the reference voltage VREF_CAL and a phase-adjusted second clock signal S_CLK_D1′. The third sampler1240may generate a third decision signal D2by sampling the internal input signal IS_CAL based on the reference voltage VREF_CAL and a phase-adjusted second clock signal S_CLK_D2′. As described above, in the calibration mode, all of the first, second and third samplers1220,1230and1240may operate using the same reference voltage (e.g., the reference voltage VREF_CAL).

The calibrator1300amay include a first delay control cell (DCC1)1320, a second delay control cell (DCC2)1330, a third delay control cell (DCC3)1340and a control circuit1350.

The first delay control cell1320may generate the phase-adjusted second clock signal S_CLK_D0′ provided to the first sampler1220by adjusting the phase of the second clock signal S_CLK based on the first delay control signal DCON1. The second delay control cell1330may generate the phase-adjusted second clock signal S_CLK_D1′ provided to the second sampler1230by adjusting the phase of the second clock signal S_CLK based on the second delay control signal DCON2. The third delay control cell1340may generate the phase-adjusted second clock signal S_CLK_D2′ provided to the third sampler1240by adjusting the phase of the second clock signal S_CLK based on the third delay control signal DCON3. The control circuit1350may generate the first, second and third delay control signals DCON1, DCON2and DCON3based on the first, second and third decision signals D0, D1and D2. For example, each of the first, second and third delay control signals DCON1, DCON2and DCON3may have an initial value before a calibration operation is performed.

The calibrator1300amay detect and compensate timing skew associated with the first, second and third samplers1220,1230and1240, and may correspond to the calibrator1302ofFIG.2A. For example, the control circuit1350may correspond to the timing skew detection circuit1304inFIG.2A, and the first, second and third delay control cells1320,1330and1340may correspond to the plurality of delay control cells1306inFIG.2A.

Although not illustrated in detail, in the normal operation mode ofFIG.3B, the first sampler1220may sample the multi-level input signal ML_IN using the first reference voltage having the first reference level VLREF_H inFIG.4B, the second sampler1230may sample the multi-level input signal ML_IN using the second reference voltage having the second reference level VLREF_M inFIG.4B, the third sampler1240may sample the multi-level input signal ML_IN using the third reference voltage having the third reference level VLREF_L inFIG.4B, and a voltage level of the multi-level input signal ML_IN may be determined and the multi-level data corresponding thereto may be generated based on the decision signals D0, D1, and D2generated by results of the sampling operations. For example, when the voltage level of the multi-level input signal ML_IN is higher than all of the first, second and third reference levels VLREF_H, VLREF_M and VLREF_L, it may be determined that the multi-level input signal ML_IN has the voltage level VL14, and the multi-level data ‘11’ corresponding to the voltage level VL14may be generated.

FIGS.6,7A,7B,7C,7D,8,9A and9Bare diagrams for describing an operation of a memory device ofFIG.5according to example embodiments.

Referring toFIG.6, example waveforms of the first clock signal OSC_CLK, the internal input signal IS_CAL and the second clock signal S_CLK are illustrated.

The internal input signal IS_CAL may be generated by driving (e.g., toggling) the output driver1100based on the first clock signal OSC_CLK. Therefore, a period T1(or frequency) of the first clock signal OSC_CLK and a period (or frequency) of the internal input signal IS_CAL may be substantially equal to each other.

The internal input signal IS_CAL may be sampled based on the second clock signal S_CLK. In other words, the second clock signal S_CLK may be used as a sampling clock for the internal input signal IS_CAL. Therefore, a frequency of the second clock signal S_CLK may be higher than the frequency of the internal input signal IS_CAL (e.g., the frequency of the first clock signal OSC_CLK), and a period T2of the second clock signal S_CLK may be shorter than the period of the internal input signal IS_CAL (e.g., the period T1of the first clock signal OSC_CLK). For example, if the frequency of the internal input signal IS_CAL (e.g., the frequency of the first clock signal OSC_CLK) is defined by f, where f is a positive real number, the frequency of the second clock signal S_CLK may be higher than 2f.

Referring toFIG.7A, an example operation of sampling the internal input signal IS_CAL using the reference voltage VREF_CAL and the second clock signal S_CLK is illustrated.

The internal input signal IS_CAL may swing between a level of a power supply voltage VDD and a level of a ground voltage VSS, and the reference voltage VREF_CAL may have a reference level VLREF_CAL. For example, the level of the power supply voltage VDD and the level of the ground voltage VSS may correspond to the voltage level VL14and voltage level VL11inFIGS.4A and4B, respectively, and the reference level VLREF_CAL may correspond to the second reference level VLREF_M inFIG.4B. For example, the reference level VLREF_CAL may be about VDD/2.

At each of sampling time points ts11, ts12, ts13, ts14, ts15, ts16, ts17and ts18, the first, second and third samplers1220,1230and1240may generate the first, second and third decision signals D0, D1and D2, respectively, by comparing the level of the internal input signal IS_CAL with the reference level VLREF_CAL. For example, at sampling time points ts11, ts12, ts13and ts14, the level of the internal input signal IS_CAL may be higher than the reference level VLREF_CAL, and thus the first sampler1220may generate the first decision signal D0having a value of ‘1’. For example, at sampling time points ts15, ts16, ts17and ts18, the level of the internal input signal IS_CAL may be lower than the reference level VLREF_CAL, and thus the first sampler1220may generate the first decision signal D0having a value of ‘0’.

In some example embodiments, the above-described sampling operation may be performed based on rising edges or falling edges of the second clock signal S_CLK, and thus the sampling time points ts11, ts12, ts13, ts14, ts15, ts16, ts17and ts18may correspond to the rising edges or the falling edges of the second clock signal S_CLK. In some example embodiments, the above-described sampling operation may be performed based on both rising edges and falling edges of the second clock signal S_CLK, and thus the sampling time points ts11, ts12, ts13, ts14, ts15, ts16, ts17and ts18may correspond to both the rising edges and the falling edges of the second clock signal S_CLK.

Referring toFIG.7B, an example where timing skew occurs in the example ofFIG.7Ais illustrated.

As described with reference toFIG.7A, in a normal case where the timing skew does not occur, the level of the internal input signal IS_CAL may be lower than the reference level VLREF_CAL at the sampling time point ts15, and thus the first sampler1220may generate the first decision signal D0having a value of ‘0’. On the other hand, when the timing skew occurs as illustrated inFIG.7B. Before the calibration is performed, when a phase of the phase-adjusted second clock signal S_CLK_D0′ provided to the first sampler1220leads, the sampling operation may be performed at a sampling time point ts15′ prior to the sampling time point ts15. At the sampling time point ts15′, the level of the internal input signal IS_CAL may be higher than the reference level VLREF_CAL, and thus the first sampler1220may generate the first decision signal D0having a value of ‘1’. In this case, after the calibration is performed the calibrator1300or1300amay generate the phase-adjusted second clock signal S_CLK_D0′ and the sampling operation may be performed at the sampling time point ts15such that the first sampler1220may generate the first decision signal D0having a value of ‘0.’

Referring toFIG.7C, an example operation of sampling the internal input signal IS_CAL using the reference voltage VREF_CAL and the second clock signal S_CLK is illustrated. The descriptions repeated withFIG.7Awill be omitted.

At each of sampling time points ts21, ts22, ts23, ts24, ts25, ts26, ts27and ts28, the first, second and third samplers1220,1230and1240may generate the first, second and third decision signals D0, D1and D2, respectively, by comparing the level of the internal input signal IS_CAL with the reference level VLREF_CAL. For example, at sampling time points ts21, ts22, ts23, ts24and ts25, the level of the internal input signal IS_CAL may be higher than the reference level VLREF_CAL, and thus the first sampler1220may generate the first decision signal D0having a value of ‘1’. For example, at sampling time points ts26, ts27and ts28, the level of the internal input signal IS_CAL may be lower than the reference level VLREF_CAL, and thus the first sampler1220may generate the first decision signal D0having a value of ‘0’.

Referring toFIG.7D, an example where timing skew occurs in the example ofFIG.7Cis illustrated.

As described with reference toFIG.7C, in a normal case where the timing skew does not occur, the level of the internal input signal IS_CAL may be higher than the reference level VLREF_CAL at the sampling time point ts25, and thus the first sampler1220may generate the first decision signal D0having a value of ‘1’. On the other hand, when the timing skew occurs as illustrated inFIG.7D. Before the calibration is performed, when a phase of the phase-adjusted second clock signal S_CLK_D0′ provided to the first sampler1220lags, the sampling operation may be performed at a sampling time point ts25′ later than the sampling time point ts25. At the sampling time point ts25′, the level of the internal input signal IS_CAL may be lower than the reference level VLREF_CAL, and thus the first sampler1220may generate the first decision signal D0having a value of ‘0’. In this case, after the calibration is performed the calibrator1300or1300amay generate the phase-adjusted second clock signal S_CLK_D0′ and the sampling operation may be performed at the sampling time point ts25such that the first sampler1220may generate the first decision signal D0having a value of ‘1.’

Accordingly, it may be determined whether the timing skew has occurred by performing the sampling operation using the first, second and third samplers1220,1230and1240based on the same internal input signal IS_CAL and the same reference voltage VREF_CAL. For example, when a value of one of the first, second and third decision signals D0, D1and D2generated from the first, second and third samplers1220,1230and1240is different from values of the remaining decision signals, it may be determined that the timing skew illustrated inFIG.7BorFIG.7Dhas occurred.

Referring toFIG.8, an example of values (e.g., logic levels) of the first, second and third decision signals D0, D1, and D2generated as a result of the sampling operation in the calibration mode is illustrated.

When only the third decision signal D2has the value of ‘1’ and the first and second decision signals D0and D1have the value of ‘0’ among the first, second and third decision signals D0, D1and D2, it may be determined that the timing skew illustrated inFIG.7Bhas occurred on the third sampler1240, e.g., the phase of the phase-adjusted second clock signal S_CLK_D2′ provided to the third sampler1240leads. Thus, the phase of the phase-adjusted second clock signal S_CLK_D2′ provided to the third sampler1240may be adjusted (e.g., delayed) using the third delay control signal DCON3and the third delay control cell1340. As a result, the phase of the phase-adjusted second clock signal S_CLK_D2′ provided to the third sampler1240may be matched (or coincide) with the phase-adjusted second clock signals S_CLK_D0′ and S_CLK_D1′ provided to the first and second samplers1220and1230, and the timing skew may be compensated or calibrated.

Similarly, when only the second decision signal D1has the value of ‘1’ and the first and third decision signals D0and D2have the value of ‘0’, it may be determined that the timing skew illustrated inFIG.7Bhas occurred on the second sampler1230, e.g., the phase of the phase-adjusted second clock signal S_CLK_D1′ provided to the second sampler1230leads, and thus the phase of the phase-adjusted second clock signal S_CLK_D1′ provided to the second sampler1230may be adjusted using the second delay control signal DCON2and the second delay control cell1330. When only the first decision signal D0has the value of ‘1’ and the second and third decision signals D1and D2have the value of ‘0’, it may be determined that the timing skew illustrated inFIG.7Bhas occurred on the first sampler1220, e.g., the phase-adjusted second clock signal S_CLK_D0′ provided to the first sampler1220leads, and thus the phase-adjusted second clock signal S_CLK_D0′ provided to the first sampler1220may be adjusted using the first delay control signal DCON1and the first delay control cell1320.

When only the first decision signal D0has the value of ‘0’ and the second and third decision signals D1and D2have the value of ‘1’ among the first, second and third decision signals D0, D1and D2, it may be determined that the timing skew illustrated inFIG.7Dhas occurred on the first sampler1220, e.g., the phase-adjusted second clock signal S_CLK_D0′ provided to the first sampler1220lags. Thus, the phase-adjusted second clock signal S_CLK_D0′ provided to the first sampler1220may be adjusted (e.g., pulled forward) using the first delay control signal DCON1and the first delay control cell1320. As a result, the phase-adjusted second clock signal S_CLK_D0provided to the first sampler1220may be matched with the phase-adjusted second clock signals S_CLK_D1′ and S_CLK_D2′ provided to the second and third samplers1230and1240, and the timing skew may be compensated.

Similarly, when only the second decision signal D1has the value of ‘0’ and the first and third decision signals D0and D2have the value of ‘1’, it may be determined that the timing skew illustrated inFIG.7Dhas occurred on the second sampler1230, e.g., the phase of the phase-adjusted second clock signal S_CLK_D1′ provided to the second sampler1230lags, and thus the phase of the phase-adjusted second clock signal S_CLK_D1′ provided to the second sampler1230may be adjusted using the second delay control signal DCON2and the second delay control cell1330. When only the third decision signal D2has the value of ‘0’ and the first and second decision signals D0and D1have the value of ‘1’, it may be determined that the timing skew illustrated inFIG.7Dhas occurred on the third sampler1240, e.g., the phase of the phase-adjusted second clock signal S_CLK_D2′ provided to the third sampler1240lags, and thus the phase of the phase-adjusted second clock signal S_CLK_D2′ provided to the third sampler1240may be adjusted using the third delay control signal DCON3and the third delay control cell1340.

In other words, the clock skew direction may be detected, determined and compensated by driving the first, second and third samplers1220,1230and1240.

When all of the first, second and third decision signals D0, D1and D2have the value of ‘1’, or when all of the first, second and third decision signals D0, D1and D2have the value of ‘0’, it may be determined that there is no timing skew on the first, second and third samplers1220,1230and1240, for example, the phase-adjusted second clock signals S_CLK_D0′, S_CLK_D1′ and S_CLK_D2′ provided to the first, second and third samplers1220,1230and1240are matched or identical. In this case, the calibration operation may not be performed.

Although example embodiments are described based on the example where the phase of the clock signal corresponding to the decision signal having the different value is adjusted when the value of one of the first, second and third decision signals D0, D1and D2is different from the values of the remaining decision signals, example embodiments are not limited thereto. For example, one of the first, second and third decision signals D0, D1and D2may be set as a reference value, and phases of clock signals corresponding to decision signals other than the reference value of the one of the first, second and third decision signals D0, D1and D2may be adjusted. For example, when the first decision signal D0is set as a reference value, and when the value of at least one of the second and third decision signals D1and D2is different from the value of the first decision signal D0, at least one of the phase-adjusted second clock signals S_CLK_D1′ and S_CLK_D2′ may be adjusted. For example, when the first decision signal D0has the value of ‘0’ and the second and third decision signals D1and D2have the value of ‘1’, or when the first decision signal D0has the value of ‘1’ and the second and third decision signals D1and D2have the value of ‘0’, the phase-adjusted second clock signals S_CLK_D1′ and S_CLK_D2′ may be adjusted rather than adjusting the phase of the phase-adjusted second clock signal S_CLK_D0′, and thus the timing skew may be compensated.

Referring toFIGS.9A and9B, examples of outputs of the first, second and third samplers1220,1230and1240are illustrated. For example, eye diagrams or valid windows of the first, second and third decision signals D0, D1and D2are illustrated inFIGS.9A and9B. Among a plurality of rectangular blocks inFIGS.9A and9B, a hatched rectangular block represents a valid region or a pass region in which data is determined to be valid, and an empty rectangular block represents an invalid region or a fail region in which data is determined to be invalid.

As illustrated inFIG.9A, before the calibration operation is performed, eye diagrams EYE_D0_BC, EYE_D1_BC, and EYE_D2_BC of the first, second and third decision signals D0, D1and D2may not be aligned with respect to a sampling time point t1, and timing skew, timing mismatch (or inconsistency) and/or timing error may exist.

As illustrated inFIG.9B, after the calibration operation is performed, eye diagrams EYE_D0_AC, EYE_D1_AC and EYE_D2_AC of the first, second and third decision signals D0, D1and D2may be aligned with respect to a sampling time point t2, and the timing skew may be removed or eliminated, and the DQ margin may be improved or enhanced.

FIGS.10A and10Bare block diagrams illustrating an example of a memory device ofFIG.1according to example embodiments.

Referring toFIGS.10A and10B, a memory device1000bincludes a data I/O pin1010, an output driver1100, a multi-level receiver1200band a calibrator1300b.

The data I/O pin1010and the output driver1100may be substantially the same as those described with reference toFIG.1, and the descriptions repeated withFIG.1will be omitted.

The multi-level receiver1200bmay include a first sampler1221, a second sampler1223, a third sampler1225and a fourth sampler1227.

The first, second, third and fourth samplers1221,1223,1225and1227may operate based on a sampler clock signal S_CLK_D0. The sampler clock signal S_CLK_D0may be generated from the second clock signal S_CLK and include a first sub-clock signal S_CLK0_D0, a second sub-clock signal S_CLK1_D0, a third sub-clock signal S_CLK2_D0and a fourth sub-clock signal S_CLK3_D0whose phases partially overlap. In some embodiments, phases of the first to fourth sub-clock signals S_CLK0_D0to S_CLK3_D0may be the same as each other. The first, second, third and fourth samplers1221,1223,1225and1227may correspond to the first sampler1220inFIG.5.

The first sampler1221may generate a first decision signal D0_0by sampling the internal input signal IS_CAL based on the reference voltage VREF_CAL and the first sub-clock signal S_CLK0_D0. The second sampler1223may generate a second decision signal D0_1by sampling the internal input signal IS_CAL based on the reference voltage VREF_CAL and the second sub-clock signal S_CLK1_D0. The third sampler1225may generate a third decision signal D0_2by sampling the internal input signal IS_CAL based on the reference voltage VREF_CAL and the third sub-clock signal S_CLK2_D0. The fourth sampler1227may generate a fourth decision signal D0_3by sampling the internal input signal IS_CAL based on the reference voltage VREF_CAL and the fourth sub-clock signal S_CLK3_D0.

The calibrator1300bmay include a first offset control cell (OCC1-1)1321, a second offset control cell (OCC1-2)1323, a third offset control cell (OCC1-3)1325, a fourth offset control cell (OCC1-4)1327and a first control circuit1351.

The first offset control cell1321may be included in the first sampler1221, and may adjust an output level of the first sampler1221based on a first offset control signal OCON1_1. The second offset control cell1323may be included in the second sampler1223, and may adjust an output level of the second sampler1223based on a second offset control signal OCON1_2. The third offset control cell1325may be included in the third sampler1225, and may adjust an output level of the third sampler1225based on the third offset control signal OCON1_3. The fourth offset control cell1327may be included in the fourth sampler1227, and may adjust an output level of the fourth sampler1227based on the fourth offset control signal OCON1_4. The first control circuit1351may generate the first, second, third and fourth offset control signals OCON1_1, OCON1_2, OCON1_3and OCON1_4based on the first, second, third and fourth decision signals D0_0, D0_1, D0_2and D0_3.

The multi-level receiver1200bmay further include a fifth sampler1231, a sixth sampler1233, a seventh sampler1235, an eighth sampler1237, a ninth sampler1241, a tenth sampler1243, an eleventh sampler1245and a twelfth sampler1247. The calibrator1300bmay further include a fifth offset control cell1331, a ninth offset control cell1341, a second control circuit1353and a third control circuit1355. Although not illustrated in detail, the calibrator1300bmay further include a sixth offset control cell, a seventh offset control cell, an eighth offset control cell, a tenth offset control cell, an eleventh offset control cell and a twelfth offset control cell.

The fifth, sixth, seventh and eighth samplers1231,1233,1235and1237may operate based on a sampler clock signal S_CLK_D1, and may correspond to the second sampler1230inFIG.5. As with the sampler clock signal S_CLK_D0, the sampler clock signal S_CLK_D1may include a fifth sub-clock signal, a sixth sub-clock signal, a seventh sub-clock signal and an eighth sub-clock signal whose phases partially overlap. The fifth, sixth, seventh and eighth samplers1231,1233,1235and1237may generate fifth, sixth, seventh and eighth decision signals D1_0, D1_1, D1_2and D1_3, respectively, by sampling the internal input signal IS_CAL based on the reference voltage VREF_CAL and the fifth, sixth, seventh and eighth sub-clock signals, respectively. The fifth offset control cell1331may be included in the fifth sampler1231, and may adjust an output level of the fifth sampler1231based on a fifth offset control signal OCON2_1. The sixth, seventh and eighth offset control cells may be included in the sixth, seventh and eighth samplers1233,1235and1237, respectively, and may adjust output levels of the sixth, seventh and eighth samplers1233,1235and1237based on sixth, seventh and eighth offset control signals OCON2_2, OCON2_3and OCON2_4, respectively. The second control circuit1353may generate the fifth, sixth, seventh and eighth offset control signals OCON2_1, OCON2_2, OCON2_3and OCON2_4based on the fifth, sixth, seventh and eighth decision signals D1_0, D1_1, D1_2and D1_3.

The ninth, tenth, eleventh and twelfth samplers1241,1243,1245and1247may operate based on a sampler clock signal S_CLK_D2, and may correspond to the third sampler1240inFIG.5. As with the sampler clock signal S_CLK_D0, the sampler clock signal S_CLK_D2may include a ninth sub-clock signal, a tenth sub-clock signal, an eleventh sub-clock signal and a twelfth sub-clock signal whose phases partially overlap. The ninth, tenth, eleventh and twelfth samplers1241,1243,1245and1247may generate ninth, tenth, eleventh and twelfth decision signals D2_0, D2_1, D2_2and D2_3, respectively, by sampling the internal input signal IS_CAL based on the reference voltage VREF_CAL and the ninth, tenth, eleventh and twelfth sub-clock signals, respectively. The ninth offset control cell1341may be included in the ninth sampler1241, and may adjust an output level of the ninth sampler1241based on a ninth offset control signal OCON3_1. The tenth, eleventh and twelfth offset control cells may be included in the tenth, eleventh and twelfth samplers1243,1245and1247, respectively, and may adjust output levels of the tenth, eleventh and twelfth samplers1243,1245and1247based on tenth, eleventh and twelfth offset control signals OCON3_2, OCON3_3and OCON34, respectively. The third control circuit1355may generate the ninth, tenth, eleventh and twelfth offset control signals OCON3_1, OCON3_2, OCON3_3and OCON3_4based on the ninth, tenth, eleventh and twelfth decision signals D2_0, D2_1, D2_2and D2_3.

The calibrator1300bmay detect and compensate offset associated with the first, second, third and fourth samplers1221,1223,1225and1227, may detect and compensate offset associated with the fifth, sixth, seventh and eighth samplers1231,1233,1235and1237, may detect and compensate offset associated with the ninth, tenth, eleventh and twelfth samplers1241,1243,1245and1247, and may correspond to the calibrator1312ofFIG.2B. For example, the control circuits1351,1353and1355may correspond to the offset detection circuit1314inFIG.2B, and the offset control cells1321,1323,1325,1327,1331and1341may correspond to the plurality of offset control cells1316inFIG.2B.

Although not illustrated in detail, in the normal operation mode ofFIG.3B, the first, second, third and fourth samplers1221,1223,1225and1227may sample the multi-level input signal ML_IN using the first reference voltage having the first reference level VLREF_H inFIG.4B, the fifth, sixth, seventh and eighth samplers1231,1233,1235and1237may sample the multi-level input signal ML_IN using the second reference voltage having the second reference level VLREF_M inFIG.4B, the ninth, tenth, eleventh and twelfth samplers1241,1243,1245and1247may sample the multi-level input signal ML_IN using the third reference voltage having the third reference level VLREF_L inFIG.4B, and a voltage level of the multi-level input signal ML_IN may be determined and the multi-level data corresponding thereto may be generated based on the decision signals D0_0, D0_1, D0_2, D0_3, D1_0, D1_1, D1_2,1_3, D2_0, D2_1, D2_2and D2_3generated by results of the sampling operations.

FIGS.11,12,13A and13Bare diagrams for describing an operation of a memory device ofFIGS.10A and10Baccording to example embodiments.

Referring toFIG.11, example waveforms of four sub-clock signals S_CLK0, S_CLK1, S_CLK2and S_CLK3included in each of the sampler clock signals S_CLK_D0, S_CLK_D1and S_CLK_D2are illustrated.

The first sub-clock signal S_CLK0may be substantially the same as the second clock signal S_CLK inFIG.6. Among the first to fourth sub-clock signals S_CLK0, S_CLK1, S_CLK2and S_CLK3, high levels of two adjacent sub-clock signals (e.g., the first and second sub-clock signals S_CLK0and S_CLK1) may partially overlap. For example, the second to fourth sub-clock signals S_CLK1, S_CLK2and S_CLK3may have a phase difference of about 90 degrees, about 180 degrees and about 270 degrees from the first sub-clock signal S_CLK0, respectively. For example, each of the sampler clock signals S_CLK_D0, S_CLK_D1and S_CLK_D2may be referred to as a 4-phase clock signal.

Referring toFIGS.7A and12, an example of values (e.g., logic levels) of the first, second, third and fourth decision signals D0_O, D0_1, D0_2and D0_3generated as a result of the sampling operation in the calibration mode is illustrated.

It may be determined whether the offset has occurred by performing the sampling operation using the first, second, third and fourth samplers1221,1223,1225and1227based on the same internal input signal IS_CAL and the same reference voltage VREF_CAL. For example, when a value of one of the first, second, third and fourth decision signals D0_0, D0_1, D0_2and D0_3generated from the first, second, third and fourth samplers1221,1223,1225and1227is different from values of the remaining decision signals, it may be determined that the offset has occurred.

For example, in a normal case where the offset does not occur, the level of the internal input signal IS_CAL may be higher than the reference level VLREF_CAL at sampling time points ts11, ts12, ts13and ts14, and thus the first, second, third and fourth samplers1221,1223,1225and1227may generate the first, second, third and fourth decision signals D0_0, D0_1, D0_2and D0_3having the value of ‘1’. Similarly, the level of the internal input signal IS_CAL may be lower than the reference level VLREF_CAL at sampling time points ts15, ts16, ts17and ts18, and thus the first, second, third and fourth samplers1221,1223,1225and1227may generate the first, second, third and fourth decision signals D0_0, D0_1, D0_2and D0_3having the value of ‘0’.

On the other hand, when only the third decision signal D0_2has the value of ‘0’ and the first, second and fourth decision signals D0_0, D0_1and D0_3have the value of ‘1’ at the sampling point ts14, it may be determined that the offset occurs associated with the third sampler1225, and thus the output level of the third sampler1225may be adjusted using the third offset control signal OCON1_3and the third offset control cell1325.

In other words, the offset direction may be detected, determined and compensated by driving the first, second, third and fourth samplers1221,1223,1225and1227and by comparing output averages of the first, second, third and fourth samplers1221,1223,1225and1227.

Although example embodiments are described based on the example where the output level of the sampler corresponding to the decision signal having the different value is adjusted when the value of one of the first, second, third and fourth decision signals D0_0, D0_1, D0_2and D0_3is different from the values of the remaining decision signals, example embodiments are not limited thereto. For example, one of the first, second, third and fourth decision signals D0_0, D0_1, D0_2and D0_3may be set as a reference value, and output levels of samplers corresponding to decision signals other than the reference value may be adjusted. For example, when the third decision signal D0_2is set as a reference value, and when the value of at least one of the first, second and fourth decision signals D0_0, D0_1and D0_3is different from the value of the third decision signal D02, at least one of the output levels of the first, second and fourth samplers1221,1223and1227may be adjusted. For example, when the third decision signal D0_2has the value of ‘0’ and the first, second and fourth decision signals D0_0, D0_1and D0_3have the value of ‘1’, the output levels of the first, second and fourth samplers1221,1223and1227may be adjusted rather than adjusting the output level of the third sampler1225, and thus the offset may be compensated.

Although not illustrated in detail, the above-described offset detection and calibration operation may also be performed on the fifth, sixth, seventh and eighth samplers1231,1233,1235and1237, and the above-described offset detection and calibration operation may also be performed on the ninth, tenth, eleventh and twelfth samplers1241,1243,1245and1247.

Referring toFIGS.13A and13B, examples of outputs of the first, second, third and fourth samplers1221,1223,1225and1227are illustrated. For example, eye diagrams or valid windows of the first, second, third and fourth decision signals D0_0, D0_1, D0_2and D0_3are illustrated inFIGS.13A and13B.

As illustrated inFIG.13A, before the calibration operation is performed, eye diagrams EYE_D0_0_BC, EYE_D0_1_BC and EYE_D0_3_BC of the first, second and fourth decision signals D0_0, D0_1and D0_3may be different from an eye diagram EYE_D0_2_BC of the second decision signal D0_2. For example, an output average level VLA of the first, second and fourth decision signals D0_0, D0_1, and D0_3and an output average level VLB of the third decision signal D0_2may be different from each other, and offset mismatch (or inconsistency) and/or offset error may exist.

As illustrated inFIG.13B, after the calibration operation is performed, eye diagrams EYE_D0_0_AC, EYE_D0_1_AC, EYE_D0_2_AC and EYE_D0_3_AC of the first, second, third and fourth decision signals D0_0, D0_1, D0_2and D0_3may be substantially the same as each other. For example, the output average level VLA of the first, second, third and fourth decision signals D0_0, D0_1, D0_2and D0_3may be substantially the same as each other, and the offset and the DQ margin may be improved or enhanced.

In some example embodiments, the calibrator1300bincluded in the memory device1000bmay additionally perform the timing skew calibration operation described with reference toFIGS.5,6,7A to7D,8,9A, and9B. In other words, when timing skew has occurred between a first group of the samplers1221,1223,1225and1227, a second group of the samplers1231,1233,1235and1237, and a third group of the samplers1241,1243,1245and1247, the calibrator1300bmay further compensate the timing skew.

FIG.14is a diagram for describing an operation of memory devices ofFIGS.5,10A and10Baccording to example embodiments.

Referring toFIG.14, an example operation of sampling the internal input signal IS_CAL using the reference voltage VREF_CAL and the second clock signal S_CLK is illustrated. Unlike the examples ofFIGS.7A,7B,7C and7D, the internal input signal IS_CAL may be sampled using the internal input signal IS_CAL having a fixed level and the reference voltage VREF_CAL having a variable level, and then the calibration operation may be performed based on a result of the sampling operation.

FIG.15is a block diagram illustrating a memory device according to example embodiments. The descriptions repeated withFIG.1will be omitted.

Referring toFIG.15, a memory device2000includes a data I/O pin2010, an output driver2100, a receiver2200and a calibrator2300.

In some example embodiments, the memory device2000may operate based on a non-return-to-zero (NRZ) scheme. For example, in a normal operation mode, the output driver2100may generate an NRZ signal based on single-bit data, and the receiver2200may generate a plurality of decision signals for generating single-bit data based on an NRZ signal. For example, the NRZ signal may have one of two voltage levels that are different from each other during one unit interval, and the single-bit data may include one bit. Detailed operations of the memory device2000in the normal operation mode will be described with reference toFIGS.17A and17B.

In some example embodiments, the memory device2000may operate in a calibration mode different from the normal operation mode. For example, the memory device2000may include the calibrator2300for performing an operation in the calibration mode. For example, in the calibration mode, the calibrator2300may detect and compensate offset associated with the receiver2200.FIG.15illustrates a detailed operation of the memory device2000in the calibration mode.

The output driver2100is connected to the data I/O pin2010, and generates an internal input signal IS_CAL based on a first clock signal OSC_CLK.

The receiver2200is connected to the data I/O pin2010, and includes a plurality of samplers2210. The plurality of samplers2210generate a plurality of decision signals DCS_CAL by sampling the internal input signal IS_CAL based on a reference voltage VREF and a second clock signal S_CLK. For example, as described with reference toFIG.11, the second clock signal S_CLK may include a plurality of sub-clock signals whose phases partially overlap.

In some example embodiments, when a calibration operation is performed in the calibration mode, both the output driver2100and the receiver2200may be enabled and operate.

The calibrator2300detects and compensates offset associated with the plurality of samplers2210based on the plurality of decision signals DCS_CAL.

In some example embodiments, in the calibration mode, the offset associated with the plurality of samplers2210may be detected and compensated using only the internal input signal IS_CAL, without an external input signal received from an outside (e.g., from an external device) through the data I/O pin2010. For example, in the calibration mode, the data I/O pin2010may have a high impedance state to prevent a reception of the external input signal.

FIG.16is a block diagram illustrating an example of a calibrator included in a memory device according to example embodiments. The descriptions repeated withFIG.2Bwill be omitted.

Referring toFIG.16, a calibrator2312may include an offset detection circuit2314and a plurality of offset control cells2316. The offset detection circuit2314and the plurality of offset control cells2316may be substantially the same as the offset detection circuit1314and the plurality of offset control cells1316inFIG.2B, respectively.

FIGS.17A and17Bare block diagrams illustrating a memory device according to example embodiments. The descriptions repeated withFIGS.3A,3B and15will be omitted.

Referring toFIGS.17A and17B, operations of the memory device2000in the normal operation mode are illustrated.

As illustrated inFIG.17A, in the normal operation mode subsequent to the calibration mode, the memory device2000may perform a data output operation. For example, the output driver2100may generate an NRZ output signal NRZ_OUT based on single-bit data SBDAT, and the NRZ output signal NRZ_OUT may be output through the data I/O pin2010.

As illustrated inFIG.17B, in the normal operation mode subsequent to the calibration mode, the memory device2000may perform a data reception operation. For example, an NRZ input signal NRZ_IN may be received through the data I/O pin2010, and the plurality of samplers2210included in the receiver2200may generate a plurality of decision signals DCS_NRZ by sampling the NRZ input signal NRZ_IN based on the reference voltages VREF and the second clock signal S_CLK. The plurality of samplers2210may operate using the same reference voltage (e.g., the reference voltage VREF) in the calibration mode and the normal operation mode.

In some example embodiments, when the data output operation or the data reception operation is performed in the normal operation mode, one of the output driver2100and the multi-level receiver2200may be enabled and operate. In some example embodiments, when the data output operation or the data reception operation is performed in the normal operation mode, the calibrator2300may be disabled.

FIG.18is a diagram for describing an NRZ signal that is input to or output from a memory device according to example embodiments.

Referring toFIG.18, an ideal eye diagram of a data signal (e.g., an NRZ signal) generated based on the NRZ scheme that is an example of the 2-level signaling scheme is illustrated. For example, the NRZ signal ofFIG.18may be an example of the NRZ output signal NRZ_OUT inFIG.17Aor the NRZ input signal NRZ_IN inFIG.17B.

An eye diagram may be used to indicate the quality of signals in high-speed transmissions. For example, the eye diagram inFIG.18may represent two symbols of a signal (e.g., ‘0’ and ‘1’), and each of the two symbols may be represented by a respective one of different voltage levels (e.g., voltage amplitudes) VL21and VL22. A reference level VLREF may be a voltage level between the voltage levels VL21and VL22. The voltage level (e.g., the symbol) of the data signal may be decided or determined based on a result of comparing the data signal with the reference level VLREF.

In some example embodiments, the voltage levels VL21and VL22and the reference level VLREF may be substantially the same as the voltage levels VL11and VL14and the second reference level VLREF_M inFIGS.4A and4B, respectively. However, example embodiments are not limited thereto.

FIG.19is a block diagram illustrating an example of a memory device ofFIG.15according to example embodiments. The descriptions repeated withFIGS.10A and10Bwill be omitted.

Referring toFIG.19, a memory device2000aincludes a data I/O pin2010, an output driver2100, a receiver2200aand a calibrator2300a.

The data I/O pin2010and the output driver2100may be substantially the same as those described with reference toFIG.15, and the descriptions repeated withFIG.15will be omitted.

The receiver2200amay include a first sampler2221, a second sampler2223, a third sampler2225and a fourth sampler2227. The first, second, third and fourth samplers2221,2223,2225and2227may generate first, second, third and fourth decision signals D_0, D_1, D_2and D_3by sampling the internal input signal IS_CAL based on the reference voltage VREF and the sub-clock signals S_CLK0, S_CLK1, S_CLK2and S_CLK3whose phases partially overlap.

The calibrator2300amay include a first offset control cell2321and a control circuit2351. Although not illustrated in detail, the calibrator2300amay further include a second offset control cell, a third offset control cell and a fourth offset control cell. The first offset control cell2321may be included in the first sampler2221, and may adjust an output level of the first sampler2221based on a first offset control signal OCON_1. The second, third and fourth offset control cells may be included in the second, third and fourth samplers2223,2225and2227, respectively, and may adjust output levels of the second, third and fourth samplers2223,2225and2227based on second, third and fourth offset control signals OCON_2, OCON_3and OCON_4, respectively. The control circuit2351may generate the first, second, third and fourth offset control signals OCON_1, OCON_2, OCON_3and OCON_4based on the first, second, third and fourth decision signals D_0, D_1, D_2and D_3.

The samplers2221,2223,2225and2227, the offset control cell2321, the control circuit2351, the sub-clock signals S_CLK0, S_CLK1, S_CLK2and S_CLK3, the decision signals D_0, D_1, D_2and D_3, and the offset control signals OCON_1, OCON_2, OCON_3and OCON_4may correspond to the samplers1221,1223,1225and1227, the offset control cell1321, the control circuit1351, the sub-clock signals S_CLK0_D0, S_CLK1_D0, S_CLK2_D0and S_CLK3_D0, the decision signals D0_0, D0_1, D0_2and D0_3, and the offset control signals OCON1_1, OCON1_2, OCON1_3and OCON1_4inFIGS.10A and10B, respectively. The receiver2200aand the calibrator2300amay perform the offset calibration operation similar to that described with reference toFIGS.11,12,13A and13B.

FIG.20is a block diagram illustrating a memory system according to example embodiments.

Referring toFIG.20, a memory system10includes a memory controller20and a memory device40. The memory system10may further include a plurality of signal lines30that electrically connect the memory controller20to the memory device40.

The memory device40is controlled by the memory controller20. For example, based on requests from a host (not illustrated), the memory controller20may store (e.g., write or program) data into the memory device40, or may retrieve (e.g., read or sense) data from the memory device40.

The plurality of signal lines30may include control lines, command lines, address lines, data input/output (I/O) lines and power lines. The memory controller20may transmit a command CMD, an address ADDR and a control signal CTRL to the memory device40via the command lines, the address lines and the control lines, may exchange a data signal DS with the memory device40via the data I/O lines, and may transmit a power supply voltage PWR to the memory device40via the power lines. For example, the data signal DS may be the multi-level signal or the NRZ signal that is transmitted and/or received according to example embodiments. Although not illustrated inFIG.20, the plurality of signal lines30may further include data strobe signal (DQS) lines for transmitting a DQS signal.

FIGS.21A and21Bare block diagrams illustrating an example of a memory system ofFIG.20according to example embodiments.

Referring toFIGS.21A and21B, a memory system11includes a memory controller21, a memory device41and a plurality of channels31a,31band31c. For example, the number of the channels31a,31band31cmay be N, where N is a positive integer greater than or equal to two.

The memory controller21may include a plurality of transmitters25a,25band25c, a plurality of receivers27a,27band27c, and a plurality of data I/O pads29a,29band29c. The memory device41may include a plurality of transmitters45a,45band45c, a plurality of receivers47a,47band47c, and a plurality of data I/O pads49a,49band49c.

Each of the plurality of transmitters25a,25b,25c,45a,45band45cmay generate the multi-level signal or the NRZ signal. In example embodiments, each of the plurality of transmitters25a,25b,25c,45a,45band45cmay employ one of the output drivers1100and2100ofFIGS.1,5,10A,15, and19. Each of the plurality of receivers27a,27b,27c,47a,47band47cmay receive the multi-level signal or the NRZ signal. In example embodiments, each of the plurality of receivers27a,27b,27c,47a,47band47cmay employ one of the multi-level receivers1200,1200a,1200b,2200, and2200aofFIGS.1,5,10A,15, and19. The memory controller21and/or the memory device41may include one of the calibrators described above inFIGS.1,2A,2B,5,10A,15,16, and19for compensating at least one of the timing skew and the offset according to example embodiments.

Each of the plurality of data I/O pads29a,29b,29c,49a,49band49cmay be connected to a respective one of the plurality of transmitters25a,25b,25c,45a,45band45cand a respective one of the plurality of receivers27a,27b,27c,47a,47band47c.

The plurality of channels31a,31band31cmay connect the memory controller21with5the memory device41. Each of the plurality of channels31a,31band31cmay be connected to a respective one of the plurality of transmitters25a,25band25cand a respective one of the plurality of receivers27a,27band27cthrough a respective one of the plurality of data I/O pads29a,29band29c. Similarly, each of the plurality of channels31a,31band31cmay be connected to a respective one of the plurality of transmitters45a,45band45cand a respective one of the plurality of receivers47a,47band47cthrough a respective one of the plurality of data I/O pads49a,49band49c. The multi-level signal or the NRZ signal may be transmitted through each of the plurality of channels31a,31band31c.

FIG.21Aillustrates an operation of transferring data from the memory controller21to the memory device41. For example, the transmitter25amay generate a data signal DS11based on input data DAT11, the data signal DS11may be transmitted from the memory controller21to the memory device41through the channel31a, and the receiver47amay receive the data signal DS11to obtain output data ODAT11corresponding to the input data DAT11. Similarly, the transmitter25bmay generate a data signal DS21based on input data DAT21, the data signal DS21may be transmitted to the memory device41through the channel31b, and the receiver47bmay receive the data signal DS21to obtain output data ODAT21corresponding to the input data DAT21. The transmitter25cmay generate a data signal DSN1based on input data DATN1, the data signal DSN1may be transmitted to the memory device41through the channel31c, and the receiver47cmay receive the data signal DSN1to obtain output data ODATN1 corresponding to the input data DATN1. For example, the input data DAT11, DAT21and DATN1may be write data to be stored into the memory device41, and a write command and a write address for storing the write data may be provided to the memory device41together with the write data.

FIG.21Billustrates an operation of transferring data from the memory device41to the memory controller21. For example, the transmitter45amay generate a data signal DS12based on input data DAT12, the data signal DS12may be transmitted from the memory device41to the memory controller21through the channel31a, and the receiver27amay receive the data signal DS12to obtain output data ODAT12corresponding to the input data DAT12. Similarly, the transmitter45bmay generate a data signal DS22based on input data DAT22, the data signal DS22may be transmitted to the memory controller21through the channel31b, and the receiver27bmay receive the data signal DS22to obtain output data ODAT22corresponding to the input data DAT22. The transmitter45cmay generate a data signal DSN2based on input data DATN2, the data signal DSN2may be transmitted to the memory controller21through the channel31c, and the receiver27cmay receive the data signal DSN2to obtain output data ODATN2corresponding to the input data DATN2. For example, the input data DAT12, DAT22and DATN2may be read data retrieved from the memory device41, and a read command and a read address for retrieving the read data may be provided to the memory device41.

FIG.22is a block diagram illustrating an example of a memory device included in a memory system according to example embodiments.

Referring toFIG.22, a memory device200includes a control logic210, a refresh control circuit215, an address register220, a bank control logic230, a row address multiplexer240, a column address latch250, a row decoder, a column decoder, a memory cell array, a sense amplifier unit, an input/output (I/O) gating circuit290, a data I/O buffer295and a data I/O pad299. In some example embodiments, the memory device200may be, e.g., a volatile memory device. For example, the memory device200may be one of various volatile memory devices such as a dynamic random access memory (DRAM).

The memory cell array may include a plurality of memory cells. The memory cell array may include a plurality of bank arrays, e.g., first through fourth bank arrays280a,280b,280cand280d. The row decoder may include a plurality of bank row decoders, e.g., first through fourth bank row decoders260a,260b,260cand260dconnected to the first through fourth bank arrays280a,280b,280cand280d, respectively. The column decoder may include a plurality of bank column decoders, e.g., first through fourth bank column decoders270a,270b,270cand270dconnected to the first through fourth bank arrays280a,280b,280cand280d, respectively. The sense amplifier unit may include a plurality of bank sense amplifiers, e.g., first through fourth bank sense amplifiers285a,285b,285cand285dconnected to the first through fourth bank arrays280a,280b,280cand280d, respectively.

The first through fourth bank arrays280ato280d, the first through fourth bank row decoders260ato260d, the first through fourth bank column decoders270ato270d, and the first through fourth bank sense amplifiers285ato285dmay form first through fourth banks, respectively. For example, the first bank array280a, the first bank row decoder260a, the first bank column decoder270a, and the first bank sense amplifier285amay form the first bank; the second bank array280b, the second bank row decoder260b, the second bank column decoder270b, and the second bank sense amplifier285bmay form the second bank; the third bank array280c, the third bank row decoder260c, the third bank column decoder270c, and the third bank sense amplifier285cmay form the third bank; and the fourth bank array280d, the fourth bank row decoder260d, the fourth bank column decoder270d, and the fourth bank sense amplifier285dmay form the fourth bank.

The address register220may receive an address ADDR including a bank address BANK_ADDR, a row address ROW_ADDR and a column address COL_ADDR from a memory controller (e.g., the memory controller20inFIG.20). The address register220may provide the received bank address BANK_ADDR to the bank control logic230, may provide the received row address ROW_ADDR to the row address multiplexer240, and may provide the received column address COL_ADDR to the column address latch250.

The bank control logic230may generate bank control signals in response to receipt of the bank address BANK_ADDR. One of the first through fourth bank row decoders260ato260dcorresponding to the received bank address BANK_ADDR may be activated in response to the bank control signals generated by the bank control logic230, and one of the first through fourth bank column decoders270ato270dcorresponding to the received bank address BANK_ADDR may be activated in response to the bank control signals generated by the bank control logic230.

The refresh control circuit215may generate a refresh address REF_ADDR in response to receipt of a refresh command or entrance of any self-refresh mode. For example, the refresh control circuit215may include a refresh counter that is configured to sequentially change the refresh address REF_ADDR from a first address of the memory cell array to a last address of the memory cell array. The refresh control circuit215may receive control signals from the control logic210.

The row address multiplexer240may receive the row address ROW_ADDR from the address register220, and may receive the refresh address REF_ADDR from the refresh control circuit215. The row address multiplexer240may selectively output the row address ROW_ADDR or the refresh address REF_ADDR. A row address RA output from the row address multiplexer240(e.g., the row address ROW_ADDR or the refresh address REF_ADDR) may be applied to the first through fourth bank row decoders260ato260d.

The activated one of the first through fourth bank row decoders260ato260dmay decode the row address output from the row address multiplexer240, and may activate a wordline corresponding to the row address. For example, the activated bank row decoder may apply a wordline driving voltage to the wordline corresponding to the row address.

The column address latch250may receive the column address COL_ADDR from the address register220, and may temporarily store the received column address COL_ADDR. The column address latch250may apply the temporarily stored or received column address COL_ADDR′ to the first through fourth bank column decoders270ato270d.

The activated one of the first through fourth bank column decoders270ato270dmay decode the column address COL_ADDR output from the column address latch250, and may control the I/O gating circuit290to output data corresponding to the column address COL_ADDR.

The I/O gating circuit290may include a circuitry for gating I/O data. For example, although not illustrated, the I/O gating circuit290may include an input data mask logic, read data latches for storing data output from the first through fourth bank arrays280ato280d, and write drivers for writing data to the first through fourth bank arrays280ato280d.

Data DQ to be read from one of the first through fourth bank arrays280ato280dmay be sensed by a sense amplifier coupled to the one bank array, and may be stored in the read data latches. The data DQ stored in the read data latches may be provided to the memory controller via the data I/O buffer295and the data I/O pad299. Data DQ received via the data I/O pad299that are to be written to one of the first through fourth bank arrays280ato280dmay be provided from the memory controller to the data I/O buffer295. The data DQ received via the data I/O pad299and provided to the data I/O buffer295may be written to the one bank array via the write drivers in the I/O gating circuit290. For example, the data I/O buffer295may include an output driver OD and a receiver RCV, and may compensate at least one of the timing skew and the offset using a calibrator CAL according to example embodiments. In example embodiments, the output driver OD, the receiver RCV, and the calibrator CAL of the memory device200may correspond to the output driver, the multi-level receiver, and calibrator ofFIGS.1,2A,2B,3A,3B,5,10A,10B,15,16,17A,17B, and19.

The control logic210may control an operation of the memory device200. For example, the control logic210may generate control signals for the memory device200to perform a data write operation or a data read operation. The control logic210may include a command decoder211that decodes a command CMD received from the memory controller and a mode register212that sets an operation mode of the memory device200.

Although the memory device included in the memory system according to example embodiments is described based on a DRAM, the memory device according to example embodiments may be any volatile memory device, and/or any nonvolatile memory device, e.g., a static random access memory (SRAM), a flash memory, a phase-change random access memory (PRAM), a resistive random access memory (RRAM), a nano floating gate memory (NFGM), a polymer random access memory (PoRAM), a magnetic random access memory (MRAM), a ferroelectric random access memory (FRAM), a thyristor random access memory (TRAM), or the like.

FIG.23is a flowchart illustrating a method of operating a memory device according to example embodiments.

Referring toFIG.23, in a method of operating a memory device according to example embodiments, an internal input signal is generated based on a first clock signal (operation S100), a plurality of decision signals are generated by sampling the internal input signal based on a reference voltage and a second clock signal (operation S200), and at least one of timing skew and offset associated with a plurality of samplers is detected and compensated based on the plurality of decision signals (operation S300). For example, the memory device may be the memory device operating based on the multi-level signal as described with reference toFIGS.1,2A,2B,3A,3B,4A,4B,5,6,7A-7D,8,9A,9B,10A,10B,11,12,13A,13B, and14, or may be the memory device operating based on the NRZ signal as described with reference toFIGS.15,16,17A,17B,18, and19.

The example embodiments may be applied to various electronic devices and systems that include the memory devices. For example, the example embodiments may be applied to systems such as a personal computer (PC), a server computer, a data center, a workstation, a mobile phone, a smart phone, a tablet computer, a laptop computer, a personal digital assistant (PDA), a portable multimedia player (PMP), a digital camera, a portable game console, a music player, a camcorder, a video player, a navigation device, a wearable device, an internet of things (IoT) device, an internet of everything (IoE) device, an e-book reader, a virtual reality (VR) device, an augmented reality (AR) device, a robotic device, a drone, etc.