MOSFET gate and source/drain contact metallization

A MOSFET is described incorporating a common metal process to make contact to the source, drain and the metal gate respectively which may be formed concurrently with the same metal or metals.

BACKGROUND

The present invention relates to MOSFET metallization in semiconductor chips and more specifically, to gate, source and drain metallization.

Typically, metallization for high K metal gates of MOSFET's and source/drain contacts is done separately using different metals.

SUMMARY

A method for fabricating a transistor having a source, drain and channel regions in a Si containing substrate exposed through openings in a dielectric layer, the opening to the channel region having sidewall spacers, is described comprising forming a metal silicide in the source and drain regions, forming a high K dielectric layer is the channel region, forming a metal gate layer over the high K dielectric layer, forming a first metal liner layer over the metal silicide in the source and drain regions and over the metal gate layer and over the sidewalls of the openings in the dielectric layer, forming a second metal layer over the first metal liner layer and having a thickness to fill the openings, and planarizing the first metal liner layer and the second metal layer down to the dielectric layer.

The invention further provides an alternate method where forming a high K dielectric layer in the channel region and forming a metal gate layer over the high K dielectric layer is performed before forming a metal silicide in the source and drain regions.

The invention further provides as one embodiment of the present invention, a field effect transistor comprising a semiconductor substrate of a first type, a high K dielectric on said substrate, a first metal having a first work function over the high K dielectric forming a metal gate, a first spacer adjacent to respective sides of the metal gate, a source and drain of a second type spaced apart adjacent to respective sidewall spacers on the opposite sides of the metal gate in the substrate to form a channel there between, and a dielectric layer having a first thickness above the substrate having a first opening to the source region, a second opening to the drain region, the first and second openings having a metal silicide layer on the source and drain region and a third opening to the metal gate, the first and second openings having a first metal on the first metal silicide at the bottom and on sidewalls and a second metal over the first metal filling the first and second openings, the first metal extending from the metal gate over sidewalls of the first and second spacers and on sidewalls of the third opening and a second metal over the first metal filling the third opening.

DETAILED DESCRIPTION

Referring now to the drawing, a process for forming a metal oxide silicon field effect transistor (MOSFET) having a common contact metal for the source/drain and gate electrodes is illustrated.FIG. 1is a cross section view of semiconductor structure10comprising a patterned resist12on upper surface13of Si layer14. Patterned resist12may comprise the shape of a sacrificial gate electrode to be used to pattern Si layer14. Si layer14may comprise polysilicon or amorphous Si (a-Si) which will comprise the material of a sacrificial Si gate electrode to be formed. Si layer14is formed on dielectric layer16which may, for example, have a high dielectric constant K (high K) material and which will function as a sacrificial gate dielectric of a MOSFET after patterning. Dielectric layer16is formed on semiconductor substrate20. Semiconductor substrate20may be single crystal and doped p type or n type depending on the type of MOSFET to be formed.

FIG. 2is a cross section view of semiconductor structure22after Si layer14and dielectric layer16are patterned using patterned resist12as a mask. Si layer14and dielectric layer16may be patterned down to the upper surface23of semiconductor substrate20, for example, by Reactive Ion Etching (RIE) to form sacrificial Si gate24and sacrificial gate dielectric18. After patterning Si layer14to form sacrificial Si gate24and dielectric layer16to form sacrificial gate dielectric18, patterned resist12is removed.

FIG. 3is a cross section view ofFIG. 2after a first spacer layer26is formed over sacrificial Si gate24and upper surface23of semiconductor substrate20forming structure28. First spacer layer26may comprise, for example, SiO2, carbon doped oxide, boron nitride, silicon nitride, perfluorocyclobutane (PFCB), fluorosilicate glass (FSG), any stress memory dielectric materials, and low K materials where K is less than 4. First spacer layer26may have a thickness in the range from 5% to 30% of the minimum gate length. First spacer layer26is removed over upper surface23and over sacrificial Si gate24shown inFIG. 4by a plasma etch shown by arrows27inFIG. 3.

FIG. 4is a cross section view ofFIG. 3showing ion implantation of ions30through first upper surface23of semiconductor substrate20to form Halo/extension implants32and33in semiconductor substrate20forming structure28′. First spacer layer26′ along the sidewalls of sacrificial Si gate24and sacrificial Si gate24form a mask to self align the Halo/extension implants32and33.

FIG. 5is a cross section view ofFIG. 4after a second spacer layer34is formed over first spacer layer26′, upper surface23and sacrificial Si gate24forming structure38. Second spacer layer34may comprise, for example, SiO2, carbon doped oxide, boron nitride, silicon nitride, perfluorocyclobutane (PFCB), fluorosilicate glass (FSG), any stress memory dielectric materials, and low K materials where K is less than 4. Second spacer layer34may have a thickness in the range from 20% to 100% of the minimum gate length. The minimum gate length may be the distance between spacers46and48.

FIG. 6is a cross section view ofFIG. 5after a plasma etch is performed to form sidewall spacers50and52. The plasma etch removes second spacer layer34in field or surface areas40and41of upper surface23of semiconductor substrate20and on surface13of sacrificial Si gate24. Further,FIG. 6is a cross section view ofFIG. 5after a source/drain ion implantation and after an activation anneal of the source/drain regions is performed to form source region58and drain region60of structure44. First spacer layer26′ shown inFIG. 5has portions remaining after plasma etch to form sidewall spacers46and48on opposite sides of sacrificial Si gate24. Second spacer layer34has portions remaining after plasma etch to form sidewall spacers50and52over sidewall spacers46and48, respectively, on opposite sides of sacrificial Si gate24. Sidewall spacers50and52along with sidewall spacers46and48function to provide the correct spacing or distance from sacrificial Si gate24for self alignment of source and drain regions58and60to be formed during ion implantation into surface areas40and41of substrate20. Source region58overlaps Halo/extension implant32. Drain region60overlaps Halo/extension implant33.

A metal silicide may be formed over source region58and drain region60first before forming a gate dielectric and metal gate as shown inFIGS. 7 and 8. The thermal stability of the metal silicide must be high enough to undergo the subsequent gate dielectric and metal gate process temperatures and thermal budget.

Alternatively, a metal silicide may be formed after the gate dielectric and metal gate are formed by bypassing the metal silicide process illustrated inFIGS. 7 and 8and proceeding to the process starting withFIG. 9. The metal silicide process illustrated inFIGS. 14 and 15would be used after performing the processes illustrated inFIGS. 9-13to form the gate dielectric and metal gate. Openings82′ and84′ in a dielectric layer64′ shown inFIG. 15are required to form the metal silicide regions86and88which is limited in area by the size of the openings. With a metal silicide first process shown inFIGS. 7 and 8, the metal silicide is not limited in area by openings in a dielectric layer. The metal silicide regions61and63extends to all of the exposed Si and extends up to the spacers50and52shown inFIG. 8.

FIG. 8is a cross section view ofFIG. 7after a first anneal at a temperature in the range from 100° C. to 500° C. to react metal layer54with silicon in source and drain regions58and60and sacrificial Si gate24to form a metal silicide as shown by metal silicide regions61,62and63over source and drain regions58′ and60′ and sacrificial Si gate24′. A first selective wet etch is then performed to remove unreacted or remaining metal of metal layer54. A second anneal may be performed to transform high resistance metal rich silicide to a low resistance silicide. A second wet etch may be performed to remove any residue or remaining metal from metal layer54. Metal silicide region61extends from spacer50over source region58′ and metal silicide region63extends from spacer52over drain region60′.

FIG. 9is a cross section view ofFIG. 6after dielectric layer64is formed over semiconductor structure44and after planarization such as by chemical mechanical polishing (CMP) of dielectric layer64is performed down to upper surface13of sacrificial Si gate24. Dielectric layer64has an upper surface65and may be selected from the group consisting of SiO2, CDO (carbon doped oxide), silicon nitride, PFCB (perfluorocyclobutane), FSG (fluorosilicate glass), any stress memory technology dielectric materials, and low K materials (where K is less than 4) and combinations thereof.FIG. 9shows semiconductor structure66. If the metal silicide process shown inFIGS. 7 and 8was performed first, thenFIG. 9would include metal silicide regions61,62and63shown inFIG. 8and metal silicide regions61and63would be shown in subsequentFIGS. 10-13and16-18in place of metal silicide regions86and88.

FIG. 10is a cross section view ofFIG. 9after sacrificial Si gate24and sacrificial gate dielectric18is removed forming gate electrode cavity68. A high K gate dielectric layer67is formed on semiconductor substrate20at the bottom of cavity68, on the sidewalls of cavity68and on upper surface65. High K gate dielectric layer67may be selected from the group consisting of hafnium oxide, hafnium silicon oxide, hafnium silicon oxynitride, lanthanum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, BST, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, lead zinc niobate, PZT or combinations thereof.

A metal gate layer69is formed over high K gate dielectric layer67. Metal gate layer69is selected to provide a desired work function for N and P type MOSFETs, respectively and to provide a capping layer on high K gate dielectric layer67. Metal gate layer69may provide a diffusion barrier to Cu.FIG. 10shows the resulting semiconductor structure70. Metal gate layer69may have a suitable work function for N or P type to provide a MOSFET with a desired threshold voltage Vth. Metal gate layer69may also provide a barrier liner. Metal gate layer69may comprise titanium nitride, tantalum nitride, hafnium, zirconium, a metal carbide, and a conductive metal oxide which meets a Vth (threshold voltage) requirement of the MOSFET to be formed. Two different work function metals for metal gate layer69may be required for NMOS and PMOS which involves an NMOS work function metal deposition of metal gate layer69and then strip off of PMOS part and then block NMOS and deposit a PMOS work function metal gate layer69. Metal gate layer69may be deposited by CVD, PVD, ALD, electrolytic plating, electroless plating, and epitaxial deposition.

FIG. 11is a cross section view ofFIG. 10after an organic planarization layer72is formed over semiconductor structure70shown inFIG. 10. Organic planarization layer72fills gate electrode cavity68completely and covers the upper surface of metal gate layer69. Organic planarization layer72is planarized at a height above upper surface65. Organic planarization layer72may comprise a resist material that gives very good planarization. A resist layer74is formed on the upper surface73of organic planarization layer72.

FIG. 12is a cross section view ofFIG. 11after resist layer74has been patterned to form respective openings76and78above source region58and drain region60respectively in resist layer74′ and organic planarization layer72′ down to metal gate layer69.

FIG. 13is a cross section view ofFIG. 12showing openings82and84extended through metal gate layer69, high K gate dielectric layer67and dielectric layer64′ which extend down to source region58and drain region60, respectively. Resist layer74′ shown inFIG. 12is removed. After openings82and84have been formed, organic planarization layer72′ shown inFIG. 12is removed reforming gate cavity68. If metal silicide regions61and63had been formed earlier as shown inFIGS. 7 and 8, thenFIG. 13would have metal silicide regions61and63and the process as shown inFIGS. 14 and 15would not be performed. The next process would be as describe with reference toFIG. 16with metal silicide regions86and88replaced with metal silicide regions61and63shown inFIG. 8.

FIG. 15is a cross section view ofFIG. 14after a first anneal at a temperature in the range from 100° C. to 500° C. and selective wet etching to remove unsilicided metal to form metal silicide regions86and88at the bottom of openings82and84, respectively, to provide electrical ohmic contact to source region58and drain region60, respectively. A second anneal is optional to transform high resistance metal rich silicide to a low resistance silicide. A second wet clean may be performed to remove residual metal i.e. unsilicided materials.

FIG. 16is a cross section view ofFIG. 15after a first metal liner layer92has been formed on metal gate layer69, opening82, gate cavity68and opening84.FIG. 16shows a second metal layer96formed over first metal liner layer92. Second metal layer96fills the remaining volume of opening82, gate cavity68and opening84. Metal liner layer92may have a suitable work function to provide a MOSFET with a desired threshold voltage Vth. Metal layer92may also provide a barrier liner such as to Cu. First metal liner layer92may comprise tantalum, titanium, titanium nitride, tantalum nitride, titanium silicon nitride, ruthenium, ruthenium oxide, ruthenium phosphorus, hafnium, zirconium, a metal carbide, a conductive metal oxide and combinations thereof which meets a threshold voltage Vth requirement of the MOSFET to be formed. Two different work function metals may be required for NMOS and PMOS which involves NMOS work function metal deposition of metal layer92and then strip off of PMOS part and then block NMOS and deposit a PMOS work function metal layer92. Metal layer92may be deposited by CVD, PVD, ALD, electrolytic plating, electroless plating, and epitaxial deposition.

FIG. 17is a cross section view ofFIG. 16after second metal layer96and first metal liner layer92are polished. Second metal layer96′ and first metal liner layer92′ are polished via chemical mechanical polish down to upper surface65′ of dielectric layer64′. Second metal layer96′ may comprise copper, ruthenium, palladium, platinum, cobalt, nickel, ruthenium oxide, tungsten, aluminum, titanium, tantalum, hafnium zirconium, a metal carbide, carbon nano tube, and a conductive metal oxide.

FIG. 18is a cross section view ofFIG. 17after metal vias102,104and106and metallization112,114and116respectively have been formed in dielectric layer118above upper surface65′ to contact those areas of first metal liner layer92′ and second metal layer96′ in dielectric layer64′ to contact source58(by way of metal silicide86), the gate electrode and drain60(by way of metal silicide88). As shown inFIG. 18, metallization112,114, and116and dielectric layer118has an upper surface122which has been planarized by chemical mechanical polishing. Metal vias102,104and106may be formed in dielectric layer118by either a single damascene process or by a dual damascene process.

While there has been described and illustrated a method for fabricating a MOSFET with common metal process to make contact to the source, drain and gate electrode formed at the same time or concurrently with the same metal or metals, it will be apparent to those skilled in the art that modifications and variations are possible without deviating from the broad scope of the invention which shall be limited solely by the scope of the claims appended hereto.