Vertical SiC MOSFET

A vertical SiC MOSFET having a source terminal, a drain terminal, and a gate region, as well as an epitaxial layer disposed between the source terminal and the drain terminal and having a doping of a first type, is furnished, a horizontally extending intermediate layer, which has regions having a doping of a second type different from the doping of a first type, being embedded into the epitaxial layer. The vertical SiC MOSFET is notable for the fact that at least the regions having doping of a second type are electrically conductively connected to the source terminal. The gate region can be disposed in a gate trench.

FIELD OF THE INVENTION

The present invention relates to a vertical SiC MOSFET, i.e. to a metal oxide semiconductor field effect transistor (MOSFET) that is manufactured on the basis of silicon carbide and whose elements are disposed predominantly vertically one above another. In particular, the direction of the current flow is also oriented substantially vertically.

BACKGROUND INFORMATION

Semiconductor components, in particular power components such as power MOSFETs, have a variety of criteria to be optimized. For example, a high short-circuit strength, i.e. withstanding a short-circuit situation in the form of zero-load operation without damage, is desirable. Low values for Rdson, i.e. the resistance between drain and source in the “on” state, are also generally advantageous in order to reduce power loss. Classically, in conventional MOSFETs the two values are directly correlated with one another: a typical conventional metal oxide semiconductor field effect transistor (MOSFET), which is considered here as a representative of a power MOSFET, is governed by the elementary MOSFET equations according to which the saturation current is:

Idsat=12⁢Rdson*⁢(Vg-Vth),
where Vgdenotes the applied gate voltage, Vththe inception threshold voltage of the MOS channel, and R*dson=Rdson−Rdriftthe channel resistance of the MOSFET in the linear region. What is obtained for the constant Kf

KF=12⁢⁢ldsat⁢Rdson*⁢(Vg-Vth)
for the MOSFET according to the existing art is the value KF=1 (for Idsatmeasured at the beginning of the linear operation plateau).

The short-circuit strength is typically energy-limited, for example due to melting of the aluminum metallization after impression of the short-circuit energy Esc,max, so that as defined by

Tscwt=Esc,maxIdsat·Uds∼Rdson*,
the achievable short-circuit time tscwtfor an applied voltage Udsdepends directly on R*dson. In conventional MOSFETs, a decrease in R*dsontherefore automatically results in a reduction in short-circuit strength; in other words, R*dsonand short-circuit strength cannot be optimized independently of one another.

In traction applications, a guaranteed short-circuit strength of tscwt>10 μs is state of the art for Si-based 1200 V semiconductors such as insulated gate bipolar transistors (IGBTs). That value is not attained by present-day SiC MOSFET concepts, and is even more difficult to achieve as a result of the cost-driven trend toward lower Rdsonvalues. See for example:

“Concept with Grounded Bottom Layer from Mitsubishi,” “Impact of Grounding the Bottom Oxide Protection Layer on the Short-Circuit Ruggedness of 4H—SiC Trench MOSFETs,” R. Tanaka et al. (Mitsubishi Electr. Corp.), ISPSD 2014;

Excessively high fields in the gate oxide can be a further problem. In principle, the gate oxide on silicon carbide (SiC) has a lower band offset in the conduction band than comparable silicon components, so that degradation as a result of tunneling currents already occurs at lower gate field strengths. For SiC MOSFETs, a useful field strength in the gate oxide is approximately 3 MV/cm. Conforming to that limit value is critical especially in blocking mode and, for trench devices in particular, necessitates design measures to limit the gate field strength (see e.g. Kevin Matocha, “Challenges in SiC Power MOSFET Design,” Solid State Electronics 52 (2008) 1631-1635; “High Performance SiC Trench Devices with Ultra-Low Ron,” T. Nakamura et al., 2011 IEEE International Electron Devices Meeting, pp. 26.51-26.53).

Possibilities for at least limiting the gate field strength are known from the existing art. For instance, the field strength at the gate oxide can be reduced by introducing a double trench with deep p implantation, such that the deeper p regions electrostatically shield the actual trench MOSFET structure (see e.g. Nakamura et al.).

Alternatively, the two measures recited above (double trench, p bubbles) can be combined (see Shinsuke Harada et al., “Determination of Optimum Structure of 4H—SiC MOSFET,” Proceedings of the 2012 24th International Symposium on Power Semiconductor Devices and ICs, pp. 253 ff.). A corresponding doping profile with no double trench is conceivable as a further variant if the p regions are implanted very deep.

German Published Patent Application No. 10 2014 00613 discloses a vertical trench MOSFET that has, within the epitaxial layer, an oppositely doped compensation layer allowing the maximum field strengths that occur to be limited.

SUMMARY

The present invention makes available a vertical SiC MOSFET having a source terminal, a drain terminal, and a gate region, and having an epitaxial layer that is disposed between the source terminal and the drain terminal and has a doping of a first type, a horizontally extending intermediate layer, which has regions having a doping of a second type different from the doping of a first type, being embedded into the epitaxial layer, at least the regions having doping of a second type being electrically conductively connected to the source terminal. A further plane that has at least regions having doping opposite from the doping of the epitaxial layer is therefore located below the conventional MOS structure.

The statement that the intermediate layer is “embedded” into the epitaxial layer is understood to mean in particular that the intermediate layer is surrounded on both sides by the epitaxial layer. It can therefore be stated that the epitaxial layer is divided by the intermediate layer into an upper region that as a rule is located on that side of the intermediate layer which faces toward the source terminal, and a lower region that as a rule is located on that side of the intermediate layer which faces toward the drain terminal. In a special instance, further regions or layers can be disposed between the intermediate layer and the upper and/or lower region of the epitaxial layer. It is likewise possible, however, for the intermediate layer to be respectively adjacent directly, and in a special instance over its entire surface, to the upper and/or the lower region of the epitaxial layer. The upper and the lower region of the epitaxial layer can have identical or different doping concentrations.

The SiC MOSFET according to the present invention has the advantage that the current through the component in the event of a short circuit can be effectively limited. It is thereby possible to manufacture components having particularly high levels of short-circuit robustness which were not previously obtainable for SiC technology.

Because the concept according to the present invention is vertically integrated, the additional structures do not create any additional space requirement on the chip.

The invention is thus area-neutral in terms of Rdson*A as compared with conventional components.

The design according to the present invention furthermore offers the advantage that the field strength in the gate oxide is limited to a level below 3 MV in order to meet stringent requirements in terms of component service life. It is thus possible both to limit the current in the event of a short circuit, and to effectively shield the gate oxide in blocking mode when a voltage is applied.

Reliability advantages are accordingly achieved by shielding the MOS channel from the drain field, and a reduction in short-channel effects is also made possible in the form of a rise in saturation current with rising drain voltage; this is likewise advantageous with regard to short-circuit strength.

It is also possible for the intermediate layer to have both first-doping-type regions and second-doping-type regions. The properties of the MOSFET can then be adjusted in controlled fashion by selecting the dimensioning and doping concentration of the various regions. Both the first-doping-type and second-doping-type regions can extend over the entire layer thickness.

Advantageously, provision is made that the second-doping-type regions are not completely cleared out when a voltage less than or equal to a blocking voltage of the SiC MOSFET is applied. This can be achieved by heavy doping, for example at least 5*1017/cm3. It is advantageous in this context if the doping changes laterally from one region to the other region as abruptly as possible. In other words, if possible, no (or only very small) transition regions having lighter doping or mixed doping are present. Because the regions having doping of a second type furnish, in the blocking instance, considerable counter-charge for reception of the blocking voltage thanks to clearing of those regions, the channel length of the MOSFET can be reduced. This results in an advantageous decrease in Rdson.

It is advantageously possible for the intermediate layer to be disposed entirely below the gate region. A relatively simple physical structure then results. The statement that the intermediate layer is disposed “below” the gate region is understood in particular to mean that the intermediate layer is disposed vertically between the gate region and the drain region. Elements of the gate region, for example a gate trench, therefore do not intersect or interrupt the intermediate layer.

According to a preferred embodiment of the invention, provision is made that the intermediate layer, together with the epitaxial layer, functionally constitutes a junction field effect transistor. In the static blocking state with the gate shut off, the first-doping-type regions are cleared out with increasing drain voltage, i.e. no further quasi-neutral regions are present in the intermediate layer in regions having a first type of doping, so that a further increase in the drain voltage can be absorbed substantially by the JFET. The current flowing through the MOSFET in the event of a short circuit can then be effectively limited by the junction field effect transistor (junction FET or JFET).

The statement that regions are “not completely cleared” is understood in particular to mean that quasi-neutral areas are still present in the relevant region even after application of the blocking voltage.

This furthermore yields a further design parameter, since the MOS region in the upper part of the MOSFET can now be designed for a substantially lower blocking voltage, since the intermediate layer, or the JFET, absorbs a substantial portion of the blocking voltage. Cleared counter-charge is furnished in the blocking state, so that only a substantially smaller electric field is present at the actual MOS structure, and less counter-charge is therefore necessary in the body. This allows the reduction in channel length as compared with the existing art.

This is achieved by the fact that the thickness and doping (NA=PPjfet) of the regions having doping of a second type are selected so that the voltage of the drift zone can be dissipated at least by the charge of the regions having doping of a second type. This yields the following design rule (for constant dopings):

If the dopings in the intermediate layer and in the EPI layer are not constant in portions, instead of the products of NA, ND, and the dimensions, the corresponding volume integrals are to be used.

As a result of the JFET functionality, the sheet charge density in the body can be reduced in accordance with the equation qbnew=qbold−qJFET+Delta3D, where qbnewis the sheet charge density, reduced according to the present invention, in the body; qboldis the sheet charge density in the body of a conventional MOSFET, as would be necessary in a design having no JFET region; qJFETis the effective charge, at maximum voltage, of the intermediate layer, functioning as a JFET region, in the partly cleared state in accordance with the field distribution in the blocking state; and Delta3Dis an adaptation term for three-dimensional effects and a safety margin for sufficient blocking strength so that punching through the body to the source does not occur.

A refinement of the invention provides that a transition layer, having heavier doping of a first type as compared with the epitaxial layer, vertically adjoins the intermediate layer in the direction of the source terminal and/or in the direction of the drain terminal. This prevents the vertical p-n transitions to second-doping-type regions of the intermediate layer from resulting in excessively large vertical space charge zones or current constrictions above and below the intermediate layer.

It is furthermore advantageous if a transition layer, having heavier doping of a first type as compared with the epitaxial layer, vertically adjoins the epitaxial layer in the direction of the source terminal. In other words, the transition layer is therefore adjacent to the upper region of the epitaxial layer. Here as well, current constrictions at the p-n transitions are avoided.

For the same reason, it is favorable if an upper part, disposed between the source terminal and the intermediate layer, of the epitaxial layer has heavier doping of a first type, in particular doping of a first type that is heavier by a factor of 2 to 4, than a lower part, disposed between the intermediate layer and the drain terminal, of the epitaxial layer.

The above-described transition layers that have heavier, i.e. more highly concentrated, doping of a first type, and that adjoin the epitaxial layer can also be referred to as “spread layers.” Advantageously, in configuring the spread layers the design rule adhered to is that the total dose of introduced dopings is kept constant as compared with the single epitaxial layer. In other words, when the concentration is raised at one point, a lower doping concentration is selected at another point in order to create an equalization.

A refinement of the invention provides that the first-doping-type regions of the intermediate layer are adjoined vertically in the direction of the source terminal and/or in the direction of the drain terminal by transition regions having a heavier doping of a first type as compared with the epitaxial layer, the epitaxial layer being at least in part adjacent to the second-doping-type regions of the intermediate layer. What is used here, as compared with the embodiment described above, is not complete spread layers but instead only transition regions or spread regions that are adjacent to the second-doping-type regions of the intermediate layer. A further optimization of the on-state resistance of the MOSFET is thereby obtained. The design described can be implemented in practice, for example, by multiple implantation at different depths in combination with a mask spacer.

A special embodiment of the invention provides that the first-doping-type regions of the intermediate layer have a double-funnel-shaped profile or an hourglass-shaped profile. In other words, the horizontal extent of the first-doping-type regions of the intermediate layer tapers respectively from the top and bottom toward the center of the intermediate layer. This measure also allows the breakdown voltage to be increased. All the measures described can of course be combined with one another if geometrically possible.

An advantageous embodiment of the invention provides that a channel of the junction field effect transistor and a channel of the MOSFET are disposed vertically one above another. The periodicity (cell pitch) of the junction field effect transistor can correspond to half the cell pitch of the trench MOS cells.

It is thereby possible to minimize the contributions of the junction field effect transistor to the resistance RDson. Proceeding from an optimal position, the functionality of the component is relatively insensitive to a lateral shift (misalignment) of the JFET region with respect to the MOS region, or to a change in the value of dpJFET.

Provision is advantageously made that the functional junction field effect transistor is connected electrically in series with the MOSFET. The “MOSFET” is understood here as the conventional, functional MOSFET within the component, i.e. in general as that region of the component which is disposed above the intermediate layer. Integration of a MOSFET-JFET cascade designed for short-circuit strength in a single component is thereby enabled. An advantage of this configuration is that the JFET is counter-coupled to the MOSFET via the voltage drop of the MOS region, thus placing an upper limit on the current: if the drain current rises sufficiently that the voltage drop across the MOS region is of the same order of magnitude as the value of the pinch voltage of the JFET, the JFET then makes a critical contribution to current limiting. The drain current is then limited by the fact that the threshold condition (pinch voltage) of the JFET is reached. Channel length modulation, and thus a further increase in the saturation current of the MOSFET at high drain voltages, are thus avoided. The point at which the threshold condition is reached can be adjusted within certain limits by way of the voltage drop or via the doping of the MOS region and the pinch voltage.

The JFET channels within the JFET region and within the intermediate layer can also have a different periodicity and/or a different orientation from the MOS cells. In other words, the elements of the MOS structure which are disposed on a specific width of the chip can differ from the elements of the intermediate layer in terms of number and spacing. Any angle can also be present between the alignment of the elements of the MOS plane, i.e. for example the gate electrodes, and the alignment of the elements of the intermediate plane.

Other JFET gate shapes, for example a honeycomb structure, a square structure, or the like, are also possible. A typical dimension of the first-doping-type regions of the intermediate layer is in the vicinity of 500 nm. Advantageously, the lateral extent of the second-doping-type regions of the intermediate layer is somewhat greater than that of the first-doping-type regions, for example by a factor of 1.2 or 1.5. The number of first- and second-doping-type regions per unit cell of the MOS structure, i.e. per gate trench, is then obtained from the ratio between the spacing of those MOS structures and the periodicity of the intermediate layer.

The MOS structure can be present on the chip (plan view or layout) as a linear structure or two-dimensional grid structure. Three-dimensional structures such as square grids, honeycombs, or hexagonal grids can also be present within the plane of the JFET layer and of the intermediate plane. Those structures can, in principle, be combined with any desired analogous periodic JFET grid structure.

Advantageous refinements of the invention are indicated in the dependent claims and described in the description.

DETAILED DESCRIPTION

FIG. 1is an equivalent circuit diagram of an embodiment of the invention showing the typical elements of a MOSFET1, namely source terminal2, drain terminal4, and gate terminal6. Also shown are two resistances, namely the resistance of MOS region8and the resistance of drift region10. The conductive connection12between source terminal2and JFET gate14results in formation of a junction field effect transistor that effectively limits high currents through the component.

When the voltage dropping across MOS region6and8becomes greater than or equal to the value of the pinch voltage of the junction field effect transistor, the latter absorbs the further drain voltage increase. Channel length modulation, and thus a further rise in the saturation current of the MOSFET at high drain voltages, are thus avoided. The exact manner in which the junction field effect transistor, or JFET, functions will be further explained below with reference to the additional Figures.

FIG. 2is a cross section through an exemplifying embodiment of a MOSFET20according to the present invention. Only a portion of the component is shown; the component can typically be made up of a plurality of unit cells. Some elements of MOSFET20are also not completely depicted.

An n-doped epitaxial layer22, in which an intermediate layer24is in turn embedded, is applied onto a typically heavily doped substrate21. In practice, the epitaxial layer is divided into an upper region22.1and a lower region22.2. Toward the bottom, a metallization26represents the drain terminal. Intermediate layer24is depicted inFIG. 2at first without further details. The typical elements of a trench MOSFET20are depicted in the top region of the Figure: a metallization28constituting source contact2, and a metallization30constituting a gate contact, are evident. Also depicted are the n-doped source region34as well as gate region36disposed in a trench structure. Gate region36is separated by an insulating layer38from source region32and from epitaxial layer22. When a voltage is applied between source contact2and gate contact4, an electrical current flows from top to bottom in the Figure, i.e. vertically, through MOSFET20when a voltage above the threshold voltage of MOSFET20is present at gate contact32and a voltage that is positive with respect to source contact28is present at drain26.

FIG. 3is a detailed depiction of intermediate layer24ofFIG. 2. Also shown, respectively in the upper and lower region of the Figure, are the upper and lower parts22.1,22.2of the epitaxial layer that adjoins intermediate layer24. It is evident that intermediate layer24has a special structure in a horizontal or lateral direction. For example, p-doped regions40.1,40.2, and40.3, as well as n-doped regions42.1and42.2, are present in the intermediate layer. Be it noted once again at this juncture that, as is usual with MOSFETs, the exemplifying embodiments depicted can also be manufactured with respectively reversed doping.

Important design parameters for the functionality of component20are the dimensions of p-doped regions40and of n-doped regions42, and the thickness Ijfetof intermediate layer22. Intermediate layer22as such constitutes, in its entirety, the so-called JFET region. The width of p-doped regions40is labeled dpjfet, and the width of the n-doped regions42is labeled djfet. Also schematically depicted is conductive connection12that creates the electrical connection between p-doped regions40and source terminal2. Also depicted, schematically and merely in order to illustrate the functional principle, is circuit symbol16of the junction field effect transistor, whose source terminal17is located in the upper (in the Figure) region of epitaxial layer22, whereas drain terminal18of junction field effect transistor16is located in the lower region of epitaxial layer22. Gate terminal19of the junction field effect transistor is connected to p-doped regions40. Those p-doped regions40thus represent the gate of junction field effect transistor16.

The dopings of regions40and42are a further important design parameter.FIG. 4is a diagram in which possible doping concentrations for n-doped regions42are plotted as a function of the width of n-doped regions42for various JFET pinch voltages UgJFET.thr; in other words, the pinch voltage of the JFET can be adjusted by corresponding selection of the parameters. All the values depicted were calculated for a doping concentration of 5*1018/cm3for the p-doped areas. Curve101applies to the minimum value for d_jfet for the respective doping concentration. Curve102applies to a JFET pinch voltage Ugthr=5 V, curve103to a JFET pinch voltage Ugthr=10 V, curve104to a JFET pinch voltage Ugthr=20 V, and curve105to a JFET pinch voltage Ugthr=50 V.

FIG. 5is a diagram analogous toFIG. 4, except that it is based on a doping concentration of 5*1017/cm3for the p-doped regions.

The pinch voltage UgJFET.throf the JFET region, which is present between contacts17and19(see e.g.FIGS. 2 and 3), is characterized in that the n-side space charge zones become as large as djfet, i.e. the quasi-neutral areas of the n-majority charge carriers of n-doped regions42between p-doped regions40disappear. In order to take the short-circuit behavior into account, the depth tjfetand the n-doping inside the MOS region are selected so that for the desired saturation current I-Dsatwith an applied voltage Uds=Ucc, which typically corresponds to 50% of the nominal blocking strength of the components, a potential drop “UMOS” as far as the n-opening of JFET opening24is achieved for n-majority charge carriers, shifting the JFET into the current-limiting state. In other words, the result of the pre-voltage is that the space charge zone of the p-n connections surrounding n-layer42becomes enlarged to the point that it is larger than or equal to djfet. UMOSadvantageously has values of at least 1 V, typically between 5 V and 20 V. A useful upper limit can be equal to 20% of the blocking voltage. The following apply:

UMOS=UgJFETthr⁢⁢and⁢⁢UMOS≡∫Int⁢⁢1⁢(tjfet)⁢E->⁢⁢d⁢⁢l->,
the path for the line integral being shown inFIG. 6as Int1. The line integral Int1extends from source region34through epitaxial layer22to n-doped region42.

The lateral extent and doping of n-regions40and p-regions42within the JFET region are selected so that at Uds=0 V, the n-opening djfetis larger than the double n-side space charge zone of the p-n connection between NA and ND, so that in the zero-voltage state, n-majority charge carriers are left over for current transport within the n-region of the JFET region.

The following ideally typical design rule is thus obtained for the case of an abrupt one-dimensional p-n transition:

The limit value for djfetcorresponds to the respective lowest curve, drawn as d_jfet_min, inFIG. 4andFIG. 5. For real, physical geometries and doping distributions, the corresponding correlations cannot be represented analytically but are present all the same and are numerically solvable. Ubirefers here to the “built-in” voltage that already drops across the p-n transition, without an external applied voltage, due to the dopings in the valence band and conduction band. NA is the p-doping concentration and ND the n-doping concentration.

FIG. 7is a cross section through an embodiment having transition layers50.1,50.2that are disposed respectively above and below intermediate layer24. Transition layers50.1,50.2each have an n-doping of higher concentration than the respective epitaxial layer22.1and22.2. A configuration of this kind prevents the formation of large space charge zones or current constrictions at the vertical p-n transitions to p-doped regions40. Also shown is pIjfetconstituting a lateral dimension of the JFET structure.

FIG. 8shows a refinement of the exemplifying embodiment shown inFIG. 6, notable for a third transition layer50.3that is disposed between source region34and epitaxial layer22. It is also evident that the dopings of the three transition layers nsp1, nsp2, and nsp3can be different.

FIG. 9shows a variant in which the transition layers do not cover the entire cross section of the MOSFET but extend only locally in the layers in question. They are therefore referred to as “transition regions” or “spread regions”52.1,52.2,52.3. Transition region52.1is located in turn above intermediate layer24in the region between intermediate layer24and epitaxial layer22. Transition region52.2is located below intermediate layer24between intermediate layer24and epitaxial layer22. Transition regions52.1,52.2respectively span n-doped region42between two p-doped regions40.1,40.2. They furthermore cover a small portion of the adjacent p-doped region40.1,40.2on both sides of the n-doped region of intermediate layer24. The extent of transition regions52.1,52.2beyond the “gap” between p-doped regions40.1,40.2is approximately equal in size to half the width of the n-doped region in the intermediate layer.

Third transition region52.3is disposed in the region in which gate region36, p-body64, and epitaxial layer22adjoin one another. It has a relatively small extent. It is apparent that NA and ND, i.e. ppjfetand njfet, NDEPI, and the doping between MOSFET body and the JFET region do not need to be constant, but can instead exhibit a local dependence.

FIG. 10shows a further possibility for configuring intermediate layer24. Here as well, the objective is to avoid current constrictions. In the exemplifying embodiment depicted, this is achieved by the fact that p-doped regions40are slightly “retracted” in the vicinity of epitaxial layer22. Intermediate layer24can be understood here as being constructed from three separate layers24.1,24.2,24.3that in principle are constructed identically but differ in terms of lateral extent. Middle layer24.2is constructed substantially as in the exemplifying embodiments already described. It can be the thickest of the three layers24.1,24.2,24.3. In particular, the width of n-doped region42.2of middle layer24.2is equal to the width of n-doped regions40in the exemplifying embodiments already described. Upper layer24.1and lower layer24.3of n-doped region42, however, have a greater extent. The overall result is a roughly hourglass-shaped or double-funnel-shaped cross section for n-doped region40.

FIG. 11shows three embodiments that differ in terms of the configuration of epitaxial layer22.1above intermediate layer24. The left-hand portion of the Figure shows an exemplifying embodiment in which a p-doped region62.1, extending as far as intermediate layer24, is introduced below gate trench39in epitaxial layer22. In other words, the region between gate trench39and intermediate layer24is filled for the most part with p-doped material. That region of intermediate layer24which is located below gate trench39is also made of p-doped material. As compared with the embodiments so far described, n-doped material below gate trench39has therefore been replaced by p-doped material.

In the middle portion ofFIG. 11, a further p-doped region62.2is disposed below p-body region64. This region as well is disposed substantially congruently above a p-doped region40of intermediate layer24. The right-hand portion ofFIG. 11shows an exemplifying embodiment that combines the two versions with one another, i.e. has both p-doped region62.1and p-doped region62.2. All the embodiments shown inFIG. 11have the advantage that p-charges which are not located in the channel region are made available.

FIG. 12shows a longitudinal section and a cross section through an exemplifying embodiment analogous to the exemplifying embodiment shown inFIGS. 2 and 3. The dashed line extending vertically identifies the section plane of the section depicted in the right-hand portion ofFIG. 12. It is evident that p-doped areas40are conductively connected to source pad2. It is further evident that gate electrode36disposed in gate trench39has been partly interrupted for contacting. Contacting can be implemented technically, for example, by way of a contact implant in trench39in combination with p-doped crosspieces60between the p-doped regions. Those crosspieces60are shown inFIG. 13.

Contacting via a deep contact implant is also possible. With two JFET channels for each MOS cell that extends in parallel, no crosspieces are then necessary for electrical connection of the p-regions. The contacts are not limited to JFET structures proceeding parallel to the trench, but can instead also be made in spot fashion at contact spots between JFET grids (p-areas of the JFET region) and the contact configurations. Contacting of the p-areas outside the active MOS cells is also conceivable.

FIG. 13is a horizontal section along the horizontal dashed line ofFIG. 12. The section thus proceeds through intermediate layer24and parallel to it. Gate regions36located inherently above the plane that is depicted are drawn with dashed lines. Once vertical contacting of p-doped areas40has been brought about by way of the interruptions in trenches39, it is apparent here that the individual p-doped areas40are connected to one another by the fact that n-doped regions42of intermediate layer24are interrupted.

FIG. 14is a depiction analogous toFIG. 13. On the basis of gate regions36, once again drawn as dashed lines, it is apparent that intermediate plane24can be rotated through any angle α with respect to the remainder of the MOSFET. In other words, an angle of, for example, 20°, 45°, or even 90° can exist between, for example, gate trenches39and n-doped regions42of intermediate layer24. The n-doped regions42of intermediate layer24can, however, of course also extend parallel to gate regions39. Different periodicities are also possible.

FIG. 15shows two embodiments of MOSFET20according to the present invention, which differ only in terms of the structure of intermediate layer24and, in that context, in turn in terms of the spacing and number of n-doped regions42and p-doped regions40of intermediate layer24. The left-hand portion of the Figure shows an example that has, for each MOS cell, only one n-doped region42in intermediate layer24. The exemplifying embodiment depicted in the right-hand portion of the Figure, conversely, has five n-doped regions42for each unit cell; one of the regions is located centrally below gate trench39, and only half of it is depicted because only a half-cell is shown. The p-doped regions40located between n-doped regions42are embodied to be somewhat wider than n-doped regions40.

FIG. 16shows a typical exemplifying embodiment. All the important dimensions are illustrated once again in the Figure, and the reference characters already known from the other Figures apply.

FIG. 17shows the applicability of the concept to various transistor concepts. The left-hand portion of the Figure shows integration into a trench MOSFET, as already known. A double-diffused metal oxide semiconductor (DMOS) field effect transistor, having an intermediate layer24according to the present invention, is evident in the center portion of the Figure. The right-hand portion of the Figure depicts a V-grooved MOS (VMOS) field effect transistor having an intermediate layer24according to the present invention.

FIG. 18shows output characteristic curves (107) of a conventional MOSFET as compared with two MOSFET's according to the present invention (108), (109). In a conventional MOSFET, a pronounced increase in saturation current with increasing drain voltage is evident. In the MOSFET according to the present invention, a sharp rise in current (i.e. good on-state resistance) is evident at low drain voltages. For higher drain voltages, a sharp transition occurs to an almost horizontal characteristic curve. The transition occurs once the drain voltage reaches the pinch voltage of the junction field effect transistor. The saturation current at high drain voltages, i.e. voltages above the transition voltage, can be set to different values depending on the embodiment and design, as is evident from a comparison of the two MOSFET characteristic curves according to the present invention. Advantageously, the location of the JFET pinch voltage is selected so that it is located well above typical on-state voltages with the MOSFET in the activated state, but usefully does not exceed 20% of the MOSFET's blocking voltage.

In all the exemplifying embodiments described, the signs of the dopings can of course be exchanged without deviating from the concept of the present invention. In other words, all the n-dopings that are described can be replaced with p-dopings, and vice versa.