Power gating in integrated circuits for leakage reduction

A system is disclosed for reducing current leakages in an integrated circuit (IC), the system comprises one or more separated power supply lines connecting between one or more power sources and an isolated circuitry, one or more switches on the separated power supply lines for controlling the connections between the power sources and the isolated circuitry, and one or more controllers for turning the switches on or off according to one or more predetermined conditions.

BACKGROUND

The present invention relates generally to an integrated circuit (IC) design, and, more particularly, to designs of power supply to built-in test circuitries in ICs.

As semiconductor processing technology has progressed to deep submicron technologies, more and more devices can be packed in a single chip. Each device may have a small amount of leakage, but an accumulative leakage from a great number of devices can pose a problem, especially to a chip used in a hand-held equipment powered by batteries.

Many complicated chips have built-in self test (BIST) circuitries to facilitating the testing of the chips prior to shipping them to customers. These BIST circuitries are used only during the chip testing phase, once a chip passes the test and is shipped to a customer, those BIST circuitries will not be used any more. But devices in the BIST circuitries are still coupled to a power supply, hence still produce leakage, even they have no functions during the chip operations.

A traditional way to reduce leakage from BIST circuitries is to use devices with higher threshold voltage to build the BIST circuitries, as speed requirements for the BIST is normally very lose. High threshold voltage devices have lower leakage, but switching speed is also slower than their lower threshold voltage counterparts. But this method does not completely cut off the leakage, and some time it may require additional processing steps.

So what is desired is a design that can reduce the number of devices, which can contribute to the overall leakage to the minimum.

SUMMARY

In view of the foregoing, the following provides a method and system for reducing current leakages in an integrated circuit (IC).

In one embodiment, the system comprises one or more separated power supply lines connecting between one or more power sources and an isolated circuitry, one or more switches on the separated power supply lines for controlling the connections between the power sources and the isolated circuitry, and one or more controllers for turning the switches on or off according to one or more predetermined conditions.

DESCRIPTION

The present disclosure provides a system and method for supplying power to built-in self test (BIST) circuitries only when the BIST circuitry is in operation.

FIG. 1is a block diagram illustrating a chip100with a built-in self test (BIST) circuitry110. A mode pad120is used to determine whether the chip100is in normal operation or in test mode. Customarily when a logic high voltage is applied to the mode pad120, the chip100goes into test mode. The BIST circuitry110sends out a signal from node C to turn off a multiplexer130and turn on another multiplexer140, so that a main pad150becomes coupled to the BIST circuitry110during a test mode operation. Then the main pad150becomes an I/O pad for the BIST circuitry110, which in turn performs various test functions as designed. Referring toFIG. 1, the singular main pad150is only a representative of a plurality of main pads.

Referring toFIG. 1, a main circuitry160is the main functional circuitry that chip100is all about. The BIST circuitry110is so designed to facilitate testing of the main circuitry160.

Referring toFIG. 1, a power supply is hard wired to both main circuitry160and the BIST circuitry110. Even during normal operation when the BIST circuitry110is totally disengaged from the main circuitry160, the power supply is still provided to the BIST circuitry110, which will then inevitably produce some leakage current.

FIG. 2is a block diagram illustrating a power supply to the BIST circuitry110being controlled by a switch210according to one embodiment of the present invention. The switch210is controlled by a controller220, which is coupled to the mode pad120. When mode pad120is in logic high state, the BIST circuitry110is engaged, and the controller220closes the switch210, so that the power is supplied to the BIST circuitry to allow it to function normally. When mode pad120is in logic low state, the BIST circuitry110is disengaged, and the controller220opens the switch210, so that the power supply to the BIST circuitry110is cut off. Then the BIST circuitry110does not contribute any leakage.

The present disclosure uses BIST as an example to illustrate the inventive concept. In fact, any circuitry that can be isolated from the main circuitry, and is disengaged from the main circuitry during normal operation, can employ the present invention. A boundary scan, or JTAG, circuitry is another example of such isolated circuitries.

FIG. 3A˜3Dare schematic diagrams illustrating implementations of the switch210and the switch controller220that together control the power supply to the BIST circuitry.

FIG. 3Aillustrates that an N-type metal-oxide-semiconductor (NMOS) transistor310is used as a power switch for the BIST circuitry110. A source and a drain of the NMOS transistor310is placed between the BIST circuitry110and a low supply voltage (Vss), and a gate of the NMOS transistor310is coupled to the mode pad120. When the mode pad120is in high logic state, the chip enters test mode, and the NMOS transistor310is turned on, so that the power supply to the BIST circuitry110can flow from a high supply voltage (Vdd) to the Vss. When the mode pad120is in low logic state, the chip enters normal operation, and the NMOS transistor310is turned off, so that the power supply to the BIST circuitry110is cut off. So the direct connection of the mode pad120to the gate of the NMOS transistor310serves as a controller for the NMOS transistor310switch.

FIG. 3Billustrates that a P-type metal-oxide-semiconductor (NMOS) transistor320is used as a power switch for the BIST circuitry110. A source and a drain of the PMOS transistor320is placed between the BIST circuitry110and the Vdd, and a gate of the PMOS transistor320is coupled to the mode pad120through an inverter325. When the mode pad120is in a high logic state, the chip enters test mode, and the PMOS transistor320is turned on, so that the power supply to the BIST circuitry110can flow from the Vdd to the Vss. When the mode pad120is in a low logic state, the chip enters normal operation, and the PMOS transistor320is turned off, so that the power supply to the BIST circuitry110is cut off. So the connection of the mode pad120to the gate of the PMOS transistor320through an inverter serves as a controller for the PMOS transistor320switch.

In certain applications, once a chip passes the test and is packaged, its BIST circuitry will never be used and can be permanently disabled. Then other kinds of switch control schemes can be used, such as blowing a fuse.

FIG. 3Cillustrates a fuse330and a resistor340connected at node V with the other terminal of the fuse330coupled to the Vdd, and the other terminal of the resistor340coupled to the Vss. The gate of the switching NMOS310is coupled to the node V. The resistance of the fuse330is normally less than 100 ohm. While the resistance of the resistor340can be set at higher than 20K ohm to limit a current flowing through a path formed by the fuse330and the resistor340. The resistor340can be formed by passive semiconductor materials, such as Nwell, or by high-resistance always-on active devices.

Referring toFIG. 3C, before being blown, the fuse330provides a low resistance connection between the node V and the Vdd, so that the NMOS310is on to provide power supply to the BIST circuitry110. After the chip is tested, and the BIST circuit110is no longer useful, the fuse330can be blown, so that the connection between the node V and the Vdd is cut off, and the node V becomes coupled to the Vss which turns off the NMOS transistor310. Then the power supply to the BIST circuitry110is cut off.

FIG. 3Dillustrates the fuse330and the resistor340connected at node V and with the other terminal of the fuse330coupled to the Vss, and the other terminal of the resistor340coupled to the Vdd. The gate of the switching PMOS320is coupled to the node V. The resistance of the fuse330is normally less than 100 ohm. While the resistance of the resistor340can be set at higher than 20K ohm to limit a current flowing through a path formed by the fuse330and the resistor340. The resistor340can be formed by passive semiconductor materials, such as Nwell, or by high-resistance always-on active devices.

Referring toFIG. 3D, before being blown, the fuse330provides a low resistance connection between the node V and the Vss, so that the PMOS320is on to provide power supply to the BIST circuitry110. After the chip is tested, and the BIST circuit110is no longer useful, the fuse330can be blown, so that the connection between the node V and the Vss is cut off, and the node V becomes coupled to the Vdd, which turns off the PMOS transistor320. Then the power supply to the BIST circuitry110is cut off.