Variable reference voltage circuit for non-volatile memory

A variable reference voltage circuit for performing memory operation on non-volatile memory includes a multi-level voltage source and a selector circuit. The multi-level voltage source generates multiple voltages. The selector circuit includes a selector input and a selector output. The selector input is coupled to the multi-level voltage source to selectively couple any of the multiple voltages to the selector output. The selector output of the selector circuit is coupled to a non-volatile memory array to provide the NV memory array with a selectable program voltage for programming the NV memory array and a selectable erase voltage for erasing the NV memory array.

TECHNICAL FIELD

This disclosure relates generally to electronic circuits, and in particular but not exclusively, relates to control circuits for non-volatile memories.

BACKGROUND INFORMATION

Electrically erasable programmable read only memory (“EEPROM”) is a type of rewritable non-volatile (“NV”) memory chip that holds its content without power. EEPROMs have lifespans, measured in number of write cycles, considerably greater than electrical programmable read only memories (“EPROMs”), the technology that preceded EEPROMS.

EEPROMS use a floating gate to hold a charge. Based on whether charge is trapped on the floating gate, the EEPROM transistor acts like a permanently-open or closed transistor. Charging the floating gate is accomplished by grounding source and drain terminals of the EEPROM transistor and placing a voltage on a control gate (write terminal). Applying a reverse voltage to the control gate causes the charge to dissipate into the substrate.

SONOS (poly-Silicon-Nitride-Oxide-Silicon) is a type of non-volatile (“NV”) memory that has attracted much attention due to its advantages over traditional floating-gate flash. Some of these advantages include lower programming voltages, better scalability, and improved cycling endurance. However, SONOS memory still suffers from endurance and retention degradation over its lifespan due to operational stresses. These operational stresses arise from the programming and erasing voltages applied to the control gate and from elevated operating temperatures. Eventually operational stresses lead to trapped charge accumulation on the floating gate of the EEPROM, resulting in the inability of an EEPROM memory cell to retain data.

DETAILED DESCRIPTION

Embodiments of an apparatus for and a method of operation of a variable reference voltage circuit for performing memory operations on a non-volatile memory array are described herein. In the following description numerous specific details are set forth to provide a thorough understanding of the embodiments. One skilled in the relevant art will recognize, however, that the techniques described herein can be practiced without one or more of the specific details, or with other methods, components, materials, etc. In other instances, well-known structures, materials, or operations are not shown or described in detail to avoid obscuring certain aspects.

FIG. 1is a circuit diagram illustrating a nonvolatile (“NV”) memory cell100for storing a bit value of data. Hundreds, thousands, or even millions of NV memory cells100may be grouped together to form an NV memory array (e.g., flash memory, EEPROM, etc.). In one embodiment, NV memory cell100represents a single memory cell of a poly-silicon-oxide-nitride-oxide-silicon (“SONOS”) flash memory array.FIG. 1is not intended to be a complete detailed schematic of an NV memory cell, but rather one of ordinary skill in the art having the benefit of the instant disclosure will appreciate only relevant components for the purposes of this discussion are illustrated.

The illustrated embodiment of NV memory cell100includes transistors T1and T2, an inverter buffer105, and a current source110. In one embodiment, transistor T1is an EEPROM transistor including a control gate coupled to a write terminal115and a floating gate120. By appropriate application of write voltages to write terminal115, charge can be made to accumulate onto floating gate120or dissipate from floating gate120, thereby writing data to NV memory cell100. Since power is not required for NV memory cell100to retain its data on floating data120, NV memory cell100is referred to as “non-volatile.”

A write operation on NV memory cell100may include either “programming” or “erasing.” As mere arbitrary convention for the purpose of this discussion, a programming operation writes a logical ‘1’ bit value into NV memory cell100by application of a positive voltage onto write terminal115. An erase operation writes a logical ‘0’ bit value into NV memory cell100by application of a negative voltage onto write terminal115.

NV memory cell100can be read by asserting a read enable terminal125of transistor T2to close circuit transistor T2and by applying a read voltage VR to read terminal130of current source110. Read voltage VR is converted to a read current IRby current source100(e.g., 5 μA). Depending upon the write state of transistor T1, node N1either will be pulled up towards the supply voltage (VS) rail or pulled down towards the ground voltage (GND) rail.

In the embodiment where NV memory array100represents SONOS flash memory, programming places transistor T1in a near zero current state (e.g., 1 μA), thereby resembling an open circuit. In the programmed state, node N1is pulled up to VS and inverting buffer105outputs a ‘0’ bit value. Erasing places transistor T1in a current draw state (e.g., 30 μA), thereby resembling a current source that overwhelms current source110. In the erased state, node N1is pulled down to GND and inverting buffer105outputs a ‘1’ bit value.

Conventional techniques use a write voltage with a single absolute magnitude (e.g., either positive or negative) applied to write terminal115for both erase and program operations. Furthermore, conventional techniques apply the same magnitude write voltage to read terminal130for generating read current IR. However, each memory operation (program, erase, and read) has its own optimal voltage for maximizing endurance and retention of NV memory cell100, balanced against minimizing operation time. These optimal voltages need not be the same. In fact, these optimal voltages are typically not the same and therefore conventional techniques attempt to select a single write voltage magnitude that achieves a reasonable compromise between the optimal voltages for erasing and programming. Embodiments of the instant invention include a variable reference voltage circuit capable of applying a different voltage to write terminal115and read terminal130dependent upon the memory operation being performed. Since the write voltages for each memory operation are decoupled, compromise is no longer necessary and designers are free to select a read voltage VR, a program voltage VP, and an erase voltage VE specifically tailored for the intended memory operation.

FIG. 2is a line graph200illustrating aging effects on NV memory cell100due to non-optimal selection of write voltages, in accordance with an embodiment of the invention.FIG. 2is merely provided for illustrative purposes and is not drawn to scale based on actual data. As illustrated, at the beginning of life (“BOL”), NV memory cell100has a distinct differentiation between erase state currents (lines205and210) and the program state current (line215). However, as NV memory cell100ages (measured in number of write cycles), line215slowly drifts up and lines205and210drift down, resulting in reduced differentiation between the erase and program state currents. Eventually, differentiation between the erase and program states will become indistinguishable resulting in eventual failure at the end of life (“EOL”).

However, in the case where a single compromise voltage is used for both erase and program operations, the degree of downward drift is more dramatic than in the case where the program voltage VP and erase voltage VE are independently selected. Use of multiple independent voltage levels for erase and program operations can increase the endurance (life span) and retention of NV memory cell100.

FIG. 3is a functional block diagram illustrating a variable reference voltage circuit300for controlling read and write operations on an NV memory array305, in accordance with an embodiment of the invention. The illustrated embodiment of variable reference voltage circuit300includes a multi-level voltage source310and a selector circuit315. In one embodiment, NV memory array305is a SONOS memory array including a plurality of individual NV memory cells100coupled for storing data.

Multi-level voltage source310generates multiple control voltages which may each be independently selected and forwarded to NV memory array305by selector circuit315during memory operations (e.g., read, program, and erase). In one embodiment, multi-level voltage source310generates the multiple control voltages based on a stable reference voltage VREF, amplifies the stable VREF and then divides the amplified VREF into the multiple different control voltages. It should be appreciated that a variety of techniques not illustrated may be used to implement multi-level voltage source310to generate the multiple control voltages.

Selector circuit315is coupled to multi-level voltage source310, to selectively tap off the different multiple control voltages and forward selected ones of the multiple control voltages to NV memory array305dependent upon the type of memory operation being performed. In one embodiment, selector circuit315selects a specific voltage from multi-level voltage source310under control of a controller (e.g., microcontroller, state machine, etc.). For example, selector circuit315may include a multiplexer (“MUX”) having a selector input320, a selector output325, and a multi-bit MUX select input330. The selector input320may be coupled to receive each of the different control voltages from multi-level voltage source310and selectively forwards them to selector output325under control of MUX select input330.

The forwarded control signals output from selector output325may then be used on NV memory array305to perform each of the memory operations. During the read operation, a read control signal having a read voltage VR is forwarded to NV memory array305by selector circuit315. During the program operation, a program control signal having a program voltage VP is forwarded to NV memory array305by selector circuit315. During the erase operation, an erase control signal having an erase voltage VE is forwarded to NV memory array305by selector circuit315. Each voltage VR, VP, and VE can be selected to optimize the particular memory operation for speed, retention, and/or endurance, as well as other factors.

The voltages VR, VP, and VE may be determined on a part-by-part basis or on a batch basis after a chip including variable reference voltage circuit300has been fabricated. After each chip is fabricated, it may be tested to determine the optimal or near optimal voltages VR, VP, and VE for each memory operation. Alternative, voltages VR, VP, VE may be determined on an architectural basis prior to fabrication if the intended type of NV memory array305to be used with variable reference voltage circuit300is known. Since the voltages VR, VP, and VE can be selected under control of a programmable controller (e.g., microcontroller, state machine, etc.), these voltages can be adjusted in real-time based on the operating temperature of NV memory array305and based on the age of NV memory array305. As illustrated above inFIG. 2, the optimal read current IRmay change over the lifespan of NV memory array300. Accordingly, the controller may be programmed to account for aging and selected differing read voltages VR based on the number of write cycles performed on a given NV memory array305. In this embodiment, variable reference voltage circuit300or the controller may maintain a write cycle counter or other types of aging counters.

The desired factors for which voltages VR, VP, and VE are optimized may also be selected. For example, voltages VR, VP, and VE can be optimized to increase endurance and/or retention of NV memory array305, at the expense of operation speed. Voltages VR, VP, and VE may be optimized to increase operation speed at the expense of endurance and/or retention. Or, voltages VR, VP, and VE may each be independently selected for optimal compromises between operation speed, retention, and endurance.

FIG. 4is a circuit diagram illustrating one embodiment of variable reference voltage circuit300in greater detail. In the illustrated embodiment, multi-level voltage source310is represented by a reference voltage source405, an operational amplifier410, and a voltage divider415. In the illustrated embodiment, selector circuit315is represented by a plurality of switches SW0-SW7(collectively switches420) coupled between intermediate nodes along voltage divider415and selector output325.FIG. 4further illustrates control logic for controlling switches420. The illustrated embodiment of the control logic includes a controller425, registers430and435, and decoder logic440. In various embodiments, controller425may be implemented as a microcontroller, a state machine, or the like.

Reference voltage source405may be implemented by a variety of techniques for generating a known stable voltage. For example, reference source405may represent a band gap voltage reference generating a reference voltage VREF approximately equal to 1.3V. Operational amplifier410is configured in a follower with gain configuration and outputs a reference voltage V1(e.g., 1.8 V) based on VREF and a feedback gain factor of the gain follower configuration.

Voltage divider415includes a plurality of resistors R0-R8coupled in series. Resistor R0is coupled to the output of operational amplifier410to receive reference voltage V1. Resistor R8is coupled to the GND voltage rail or to any potential lower or higher than the output of operational amplifier410. In one embodiment, resistors R0-R8are polysilicon resistors. AlthoughFIG. 4illustrates nine series coupled resistors, it should be appreciated that embodiments of the invention may include more or less resistors dependent, in part, upon the voltage resolution desired for the control signals. In one embodiment where NV memory array305is a SONOS memory array, voltages V2and V3generated by voltage divider415range between V2=1.2V and V3=1.8V. However, other voltage ranges are possible. It should be appreciated that voltage divider415illustrated inFIG. 4is only one of many possible circuits and techniques for implementing voltage division in connection with embodiments of the invention.

The illustrated embodiment of selector circuit315includes eight switches SW0-SW7; however, selector circuit315may include more or less switches420dependent, in part, on the voltage resolution or increment size desired. Switches420are coupled to the intermediate nodes between resistors R0-R8to selectively forward any of the voltages between V2and V3to selector output325. Switches420include control terminals μC0-μC7for controlling conductivity of switches420. Control terminals μC0-μC7are coupled to the output of decoder logic440.

During operation, controller425writes a multi-bit value into register435indicating the type of memory operation to be performed on NV memory array305. In response, decoder logic440decodes the multi-bit value to selectively close one of switches420(i.e., place in a conducting state) and open circuit the rest of switches420. In this manner, controller425is capable of selecting a different voltage dependent upon the memory operation being performed based on the multi-bit value written into register435.

In one embodiment, decoder440determines what voltage to select for a given memory operation based on operation values stored in register430. Register430may store three values: a program value indicating the program voltage VP to be applied to NV memory array305during a program operation, an erase value indicating the erase voltage VE to be applied to NV memory array305during an erase operation, and a read value indicating the read voltage VR to be applied to NV memory array305during a read operation. As discussed above these values may be determined on a part-by-part basis and programmed into register430after fabrication. In one embodiment, controller425may update the values stored in register430under user control.

Accordingly, in one embodiment, the multi-bit value written into register435by controller425selects the type of memory operation to perform and decoder440uses the multi-bit value written in register435to access the appropriate value corresponding to the memory operation stored in register430. Subsequently, decoder440enables/disables the appropriate switches420to achieve the desired voltage indicated by the value stored in register430for the memory operation indicated in register435. In an alternative embodiment, controller425may access register430to determine what voltage to select for a given memory operation and then write a multi-bit value into register435that indicates to decoder440both the type of memory operation to perform and the specific voltage to apply. In this alternative embodiment, decoder440need not be coupled to register430.

In one embodiment, register430stores a plurality of program values each indicating a different program voltage VP to be applied at a given operating temperature range. Alternatively, register430may store temperature scaling factors to be applied to the single program value based on the current operating temperature. Register430may also store a plurality of program values or aging scaling factors that may be used to adjust the program voltage VP based on the age of NV memory array305. Similarly, multiple erase values or temperature/aging scaling factors may be stored to adjust the erase voltage VE based on operating temperature and/or age. Similarly, multiple read values or temperature/aging scaling factors may be stored to adjust the read voltage VR based on operating temperature and/or age.

FIG. 5is a flow chart illustrating a process500for operating variable reference voltage circuit300, in accordance with an embodiment of the invention. The order in which some or all of the process blocks appear in each process should not be deemed limiting. Rather, one of ordinary skill in the art having the benefit of the present disclosure will understand that some of the process blocks may be executed in a variety of orders not illustrated.

In a process block505, variable reference voltage circuit300is powered on and/or reset. Once powered on, reference voltage source405generates reference voltage VREF (process block510), operational amplifier410amplifies reference voltage VREF to reference voltage V1(process block515), and voltage divider415divides reference voltage V1into multiple voltages ranging between V3and V2(process block520).

When a request to perform a memory operation on NV memory array305is received (decision block525), controller425writes the appropriate multi-bit value into register435corresponding to the requested memory operation type (read, program, or erase). Decoder logic440decodes the multi-bit value buffered in register435with reference to register430to selectively couple the appropriate control voltage (e.g., VR, VP, or VE) from multi-level voltage source310into NV memory array305(process block530).

If the requested memory operation is a program operation (decision block535), then selector circuit315provides the program voltage VP to NV memory array305for application to write terminal115of transistor T1(seeFIG. 1) of an appropriate NV memory cell100within NV memory array305(process block540). If the requested memory operation is an erase operation (decision block535), then selector circuit315provides the erase voltage VE to NV memory array305for application to write terminal115of transistor T1(seeFIG. 1) of an appropriate NV memory cell100within NV memory array305(process block545). If the requested memory operation is a read operation (decision block535), then selector circuit315provides the read voltage VR to NV memory array305for application to read terminal130of transistor T2(seeFIG. 1) of an appropriate NV memory cell100within NV memory array305(process block540).

FIG. 6is a block diagram illustrating a demonstrative processing system600implemented with embodiments of the invention. The illustrated embodiment of processing system600includes one or more processors (or central processing units)605, system memory610, NV memory615, a data storage unit (“DSU”)620, a communication link625, and a chipset630. The illustrated processing system600may represent a computing system including a desktop computer, a notebook computer, a workstation, a handheld computer, a server, a blade server, a removable storage device, a peripheral device, or the like. NV memory615may represent the combination of variable reference voltage circuit300and NV memory array305.

The elements of processing system600are interconnected as follows. Processor(s)605is communicatively coupled to system memory610, NV memory615, DSU620, and communication link625, via chipset630to send and to receive instructions or data thereto/therefrom. In one embodiment, NV memory615is a flash memory device (e.g., SONOS flash memory). In one embodiment, system memory610includes random access memory (“RAM”), such as dynamic RAM (“DRAM”), synchronous DRAM (“SDRAM”), double data rate SDRAM (“DDR SDRAM”), static RAM (“SRAM”), and the like. DSU620represents any storage device for software data, applications, and/or operating systems, but will most typically be a nonvolatile storage device. DSU620may optionally include one or more of an integrated drive electronic (“IDE”) hard disk, an enhanced IDE (“EIDE”) hard disk, a redundant array of independent disks (“RAID”), a small computer system interface (“SCSI”) hard disk, and the like. Although DSU620is illustrated as internal to processing system600, DSU620may be externally coupled to processing system600. Communication link625may couple processing system600to a network such that processing system600may communicate over the network with one or more other computers. Communication link625may include a modem, an Ethernet card, a Gigabit Ethernet card, Universal Serial Bus (“USB”) port, a wireless network interface card, a fiber optic interface, or the like.

It should be appreciated that various other elements of processing system600have been excluded fromFIG. 6and this discussion for the purpose of clarity. For example, processing system600may further include a graphics card, additional DSUs, other persistent data storage devices (e.g., tape drive), and the like. Chipset630may also include a system bus and various other data buses for interconnecting subcomponents, such as a memory controller hub and an input/output (“I/O”) controller hub, as well as, data buses (e.g., peripheral component interconnect bus) for connecting peripheral devices to chipset630. Moreover, processing system600may operate without one or more of the elements illustrated. For example, processing system600need not include DSU620.

The processes described above may constitute machine-executable instructions embodied within a machine (e.g., computer) accessible medium, which when executed by a machine will cause the machine to perform the operations described herein. Additionally, the processes may be embodied within hardware, such as an application specific integrated circuit (“ASIC”) or the like. A machine-accessible medium includes any mechanism that provides (i.e., stores and/or transmits) information in a form accessible by a machine (e.g., a computer, network device, personal digital assistant, manufacturing tool, any device with a set of one or more processors, etc.). For example, a machine-accessible medium includes recordable/non-recordable media (e.g., read only memory (ROM), random access memory (RAM), magnetic disk storage media, optical storage media, flash memory devices, etc.), as well as electrical, optical, acoustical or other forms of propagated signals (e.g., carrier waves, infrared signals, digital signals, etc.).

As described above, variable reference voltage circuit300and NV memory array305may be incorporated into various other systems and integrated circuits. Descriptions of variable reference voltage circuit300and/or NV memory array305may be generated and compiled for incorporation into these other systems and integrated circuits. For example, behavioral level code describing variable reference voltage circuit300and NV memory array305, or portions thereof, may be generated using a hardware descriptive language, such as VHDL or Verilog, and stored to a machine-accessible medium. Furthermore, the behavioral level code can be compiled into register transfer level (“RTL”) code, a netlist, or even a circuit layout and stored to a machine-accessible medium. The behavioral level code, the RTL code, the netlist, and the circuit layout all represent various levels of abstraction to describe variable reference voltage circuit300and NV memory array305.