A voltage-level converter and a method of converting a first logic voltage level to a second logic voltage level are described. In one embodiment, a voltage-level converter connects a first logic unit connected to a first supply voltage to a second logic unit connected to a second supply voltage. The voltage-level converter includes at least one transistor connected to the second supply voltage. The at least one transistor has a threshold voltage whose absolute value is greater-than-or-about-equal to the absolute value of the difference between the second supply voltage and the first supply voltage. In an alternative embodiment, a method for converting a first logic voltage level to a second logic voltage level includes transmitting a logic signal from a logic unit having an output voltage swing of between a first voltage level and a second voltage level, receiving the logic signal at a logic circuit having a pull-up transistor and an output voltage swing between a third voltage level and a fourth voltage level, and turning off the pull-up transistor when the logic signal has a value slightly greater than the difference between the third voltage level and the first voltage level.

FIELD

This invention relates to integrated circuits and, more particularly, to integrated circuit voltage-level converters.

BACKGROUND

A voltage-level converter converts a logic signal at a first voltage level to a logic signal at a second voltage level. In a modem integrated circuit, such as a microprocessor, a digital signal processor, or an application specific integrated circuit, different voltage levels, such as a first supply voltage level and a second supply voltage level, provide power to different groups of circuits to reduce the overall power consumption in the integrated circuit. However, signals generated by circuits powered at a first supply voltage level are usually incompatible with circuits powered at a second supply voltage level. Therefore, signals generated by circuits powered at a first supply voltage level are converted to signals compatible with circuits powered at a second supply voltage level by inserting a voltage-level converter between the circuits powered at the first supply voltage level and the circuits powered at the second supply voltage level.

FIG. 1Ais a schematic diagram of a prior art voltage-level converter100. The voltage-level converter100includes transistors102-105having threshold voltages that are about equal. The voltage-level converter100converts a logic signal at a first logic voltage level (VCC1) at the node107to a logic signal at a second logic voltage level (VCC2) at the node109. Unfortunately, if the logic signal at the first logic voltage level (VCC1) does not cause the transistor102to enter the cut-off region of operation, the conversion of a logic signal from the first logic voltage level (VCC1) at node107to the second logic voltage level (VCC2) at node109can cause the voltage-level converter to consume power. Furthermore, as the difference between the first voltage level (VCC1) and the second voltage level (VCC2) increases, the voltage-level converter100increases its static power consumption. Thus, even though the voltage-level converter100provides relatively fast voltage level conversion when compared with other voltage-level converters, the voltage-level converter100can consume power for static inputs and is not well suited for applications that require low power consumption.

FIG. 1Bis a schematic diagram of a prior art voltage-level converter110. The voltage-level converter110includes transistors114-117and inverter119. The transistors114-117have threshold voltages that are about equal. After a low-to-high voltage transition at the input node112, the first cross-coupled pull-up transistor114is turned off, the second cross-coupled pull-up transistor115is turned on, the transistor116is turned on, and the transistor117is turned off. With the transistors114and117turned off, there is no direct current path through the voltage-level converter110, and the voltage-level converter110consumes substantially zero power. However, during a low-to-high voltage transition at the input node112, there is contention at nodes122and124, and this contention increases the delay and the dynamic power consumption of the voltage-level converter110.

Therefore, even though the voltage-level converter110consumes substantially zero power for static voltage level inputs, the performance (speed) of the voltage-level converter110is relatively low, and the voltage-level converter110consumes power during voltage transitions.

DESCRIPTION

In the following detailed description of the invention, reference is made to the accompanying drawings which form a part hereof, and in which are shown, by way of illustration, specific embodiments of the invention which may be practiced. In the drawings, like numerals describe substantially similar components throughout the several views. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention. Other embodiments may be utilized and structural, logical, and electrical changes may be made without departing from the scope of the present invention. The following detailed description is not to be taken in a limiting sense, and the scope of the present invention is defined only by the appended claims, along with the full scope of equivalents to which such claims are entitled.

FIG. 2Ais a block diagram of some embodiments of a logic unit200according to the teachings of the present invention. The logic unit200includes a first logic unit202, a second logic unit204, and a voltage-level converter206. The first logic unit202includes an output port208, the second logic unit204includes an input port210, and the voltage-level converter206includes an input port212and an output port214. The output port208of the first logic unit202is coupled to the input port212of the voltage-level converter206and the output port214of the voltage-level converter206is coupled to the input port216of the second logic unit204. Power is provided to the logic unit200by a first supply voltage218, a second supply voltage220, and a third supply voltage222. The first logic unit202is connected to the first supply voltage218and the third supply voltage222, the second logic unit204is connected to the second supply voltage220and the third supply voltage222, and the voltage-level converter206is connected to the second supply voltage220and the third supply voltage222.

In one embodiment, the first supply voltage218has a positive potential, the second supply voltage220has a positive potential greater than the positive potential of the first supply voltage218, and the third supply voltage222has a zero or negative potential.

The first logic unit202includes one or more logic or storage devices for performing a logical function. Exemplary logic devices include AND gates, OR gates, NAND gates, NOR gates, and XOR gates. Exemplary storage devices include memory devices such as dynamic random access memory devices and core storage devices. The first logic unit202is not limited to being fabricated using a particular semiconductor technology. In one embodiment, the first logic unit202is fabricated using a complimentary metal-oxide semiconductor process.

The second logic unit204includes one or more logic or storage devices for performing a logical function. The second logic unit can include critical functional units and/or critical circuit paths. A critical functional unit is a functional unit, such as an arithmetic and logic unit, that is designed to perform a logical operation as fast as possible. A critical circuit path is a circuit path, such as a clock path found in a clock distribution unit, that is designed to transmit signals as fast as possible along the path. Exemplary logical units include AND gates, OR gates, NAND gates, NOR gates, and XOR gates. Exemplary storage devices include static random access memory devices and electrically programmable read-only memory devices. The second logic unit204is not limited to being fabricated using a particular technology. In one embodiment, the second logic unit204is fabricated using a complimentary metal-oxide semiconductor process. In an alternative embodiment, the second logic unit204is fabricated using a bipolar process.

The voltage-level converter206is connected to the second supply voltage220at a node224and to the third supply voltage222at a node226. In operation, the voltage-level converter206receives an input signal at an input port212, processes the input signal, and provides an output signal at an output port214.

FIG. 2Bis a sketch of an exemplary input signal228received at an input port212(shown inFIG. 2A) of the voltage-level converter206(shown inFIG. 2A) and an output signal230(shown inFIG. 2A) produced by the voltage-level converter206in response to the exemplary input signal228. The exemplary input signal228and the output signal230are described in more detail in theFIG. 2Cdescription provided below.

FIG. 2Cis a schematic diagram of one embodiment of the voltage-level converter206shown in FIG.2A. The voltage-level converter206includes an insulated gate p-type field-effect transistor236and an insulated gate n-type field-effect transistor238. The gate of the insulated gate p-type field-effect transistor236and the gate of the insulated gate n-type field-effect transistor238are coupled together to form the input port212of the voltage-level converter206. A drain/source of the insulated gate p-type field-effect transistor236and a drain/source of the insulated gate n-type field-effect transistor238are coupled together to serially couple the insulated gate p-type field-effect transistor236to the insulated gate n-type field-effect transistor238. A drain/source of the insulated gate p-type field-effect transistor236forms the node224. A drain/source of the insulated gate n-type field-effect transistor238forms the node226. As configured inFIG. 2C, the insulated gate p-type field-effect transistor236and the insulated gate n-type field-effect transistor238perform a logical inversion function (i.e., a logical one is converted to a logical zero, and a logical zero is converted to a logical one).

Preferably, the insulated gate n-type field-effect transistor238has a threshold voltage239(shown inFIG. 2B) that is slightly greater than the third supply voltage222(shown in FIG.2B). In one embodiment, the insulated gate p-type field-effect transistor236has a threshold voltage240(shown inFIG. 2B) having an absolute value that is about equal to a difference voltage241(shown in FIG.2B). The difference voltage241is the difference between the second supply voltage220(shown inFIG. 2B) and the first supply voltage218(shown in FIG.2B). In an alternative embodiment, the insulated gate p-type field-effect transistor236has a threshold voltage240having an absolute value that is greater than the difference voltage241.

Setting the threshold voltage240of the insulated gate p-type field-effect transistor236to a value greater than or equal to the difference between the second supply voltage220and the first supply voltage218permits the insulated gate p-type field-effect transistor236to completely turn off for a signal at the input port212having a value about equal to the first supply voltage218. Thus, for a static input signal at the input port212substantially zero current flows through the voltage-level converter206and between the second supply voltage220(shown inFIG. 2A) and the third supply voltage222(shown in FIG.2A). Also, substantially zero power is consumed for the input signal at the input port212of the voltage-level converter206about equal to the first supply voltage218(shown in FIG.2A). Furthermore, a level conversion delay time242(shown inFIG. 2B) is short. Therefore, utilizing an extraordinary high-threshold p-type filed-effect transistor236results in a fast and low power voltage level conversion.

FIG. 2Dis a schematic diagram of an alternative embodiment of the voltage-level converter206shown in FIG.2A. The voltage-level converter206includes a first inverter243serially coupled to a second inverter246. The first inverter243includes an insulated gate p-type field-effect transistor249and an insulated gate n-type field-effect transistor252. The gate of the insulated gate p-type field-effect transistor249and the gate of the insulated gate n-type field-effect transistor252are coupled together to form the input port212. A drain/source of the insulated gate p-type field-effect transistor249and a drain/source of the insulated gate n-type field effect transistor252are coupled together to serially couple the insulated gate p-type field-effect transistor249to the insulated gate n-type field-effect transistor252.

The second inverter246includes an insulated gate p-type field-effect transistor255and an insulated gate n-type field-effect transistor257. The gate of the insulated gate p-type field-effect transistor255and the gate of the insulated gate n-type field-effect transistor257are coupled to a drain/source of the insulated gate p-type field effect transistor249and to a drain/source of the insulated gate n-type field effect transistor252. A drain/source of the insulated gate p-type field-effect transistor255and a drain/source of the insulated gate n-type field effect transistor257are coupled together to serially couple the insulated gate p-type field-effect transistor255to the insulated gate n-type field-effect transistor257. A drain/source of the insulated gate p-type field-effect transistor249is coupled to a drain/source of the insulated gate p-type field-effect transistor255to form the node224, and a drain/source of the insulated gate n-type field-effect transistor252is coupled to a drain/source of the insulated gate n-type field-effect transistor257to form the node226.

As configured inFIG. 2D, the first inverter243and the second inverter246perform a voltage-level conversion without logical inversion (i.e., a logical one is voltage-level converted and remains a logical one, and a logical zero is voltage-level converted and remains a logical zero).

Preferably, the threshold voltage of the insulated gate n-type field-effect transistor252, the threshold voltage of the insulated gate p- type field-effect transistor255, and the threshold voltage of the insulated gate n-type field-effect transistor257are about equal. In one embodiment, the threshold voltages of the insulated gate n-type field-effect transistor252, the threshold voltage of the insulated gate p-type field-effect transistor255, and the threshold voltage of the insulated gate n-type field-effect transistor257are about equal to 0.3 volts. In one embodiment, the threshold voltage of the insulated gate p-type field-effect transistor249has an absolute value that is about equal to the difference between the second supply voltage220(shown inFIG. 2A) and the first supply voltage218(shown in FIG.2A). In an alternative embodiment, the threshold voltage of the insulated gate p-type field-effect transistor249has an absolute value that is greater than the difference between the second supply voltage220and the first supply voltage218. Setting the threshold voltage of the insulated gate p-type field-effect transistor249to a value such that the absolute value of the threshold voltage is greater-than-or-equal to the difference between the second supply voltage220and the first supply voltage218permits the insulated gate p-type field-effect transistor249to completely turn off for a signal at the input port212having a value about equal to the first supply voltage218. Thus, for a static input signal substantially zero current flows between the second supply voltage220and the third supply voltage222in the voltage-level converter206, and substantially zero power is consumed after the input voltage at the input port212of the voltage-level converter206is about equal to the voltage of the first supply voltage218.

The voltage-level converter206shown inFIG. 2Dincludes the first inverter243which consumes substantially zero power for a high-level input voltage because the insulated gate p-type field effect transistor249is completely turned off. The second inverter246, in this embodiment, provides improved drive capability when compared with the voltage-level converter206shown in FIG.2C. Thus, the second inverter246is capable of driving a large number of loads or a large capacitance without a significant decrease in speed. Further, the two inverters243and246together provide a non-inverting buffer, which generates a level converted signal with the same polarity as an input signal at the input port212.

FIG. 2Eis a block diagram of another alternative embodiment of the voltage-level converter206shown in FIG.2A. The voltage-level converter206includes a logic circuit261having a p-type metal-oxide semiconductor (PMOS) pull-up transistor262and a logic circuit263having an NMOS pull-down transistor264. The logic circuit261is serially connected to the logic circuit263. The serial connection forms the output port214. The input port of the logic circuit261and the input port of the logic circuit263are coupled together to form the input port212. The input port212is illustrated as a single connection, however the input port212is not limited to a single connection. A plurality of inputs signals can be received at input port212and provided to the logic circuits261and263. In operation, the logic circuits261and263cooperate to provide a single logic function. The logic function provided by circuits261and263is not limited to a particular logic function. Exemplary logic functions include AND, OR, NAND, NOR, and XOR.

In one embodiment, p-type metal-oxide semiconductor (PMOS) pull-up transistor262is an insulated gate p-type field-effect transistor. In one embodiment, the threshold voltage of the p-type metal-oxide semiconductor (PMOS) pull-up transistor262is about equal to the difference between the second supply voltage200(shown inFIG. 1A) and the first supply voltage218(shown in FIG.1A). In an alternative embodiment, the threshold voltage of the p-type metal-oxide semiconductor (PMOS) pull-up transistor262is greater than the difference between the second supply voltage200and the first supply voltage218. As configured inFIG. 2E, the voltage-level converter206performs a voltage-level conversion and a logic function, such as an AND, OR, NAND, NOR, or XOR. Thus, by utilizing the suggested condition for an appropriate high threshold voltage PMOS transistor in the logic circuit261, a logic block can perform logic as well as a fast, low power level conversion at the same time. This in turn results also in a significant area saving since there is no need for an explicit level converter such as provided inFIGS. 2C and 2D.

FIG. 3is a flow diagram of one embodiment of a method300for converting a signal having a first voltage swing to a signal having a second voltage swing according to the teachings of the present invention. In one embodiment, the first voltage swing is less than the second voltage swing. The method300includes the operations of transmitting a logic signal (block302), receiving a logic signal (block304), and turning off a pull-up transistor (block306). Transmitting a logic signal includes a transmitting a logic signal from a logic unit having an output voltage swing between the first voltage level and a second voltage level as shown in block302. Receiving a logic signal includes receiving a logic signal and a logic circuit having a pull-up transistor and an output voltage swing between the third voltage level and a fourth voltage level as shown in block304. Turning off a pull up transistor includes turning off the pull-up transistor when the logic signal has a value slightly greater than the difference between the third voltage level as shown in block306. In one embodiment, the first voltage level is greater than the second voltage level, the third voltage level is greater than the fourth voltage level, and the third voltage level is greater than the first voltage level. In an alternative embodiment, the first voltage level is greater than the second voltage level, the third voltage level is greater than the fourth voltage level, and the third voltage level is about equal to the first voltage level.

In the embodiments described above, reference is made to the value of the threshold voltage of one or more transistors. Those skilled in the art will appreciate that many factors affect the threshold voltage in a transistor and many methods are available for controlling the value of the threshold voltage. In one such method, charge is implanted under the gate of the transistor to control the threshold voltage.

Although specific embodiments have been described and illustrated herein, it will be appreciated by those skilled in the art, having the benefit of the present disclosure, that any arrangement which is intended to achieve the same purpose may be substituted for a specific embodiment shown. This application is intended to cover any adaptations or variations of the present invention. Therefore, it is intended that this invention be limited only by the claims and the equivalents thereof.