Apparatus and associated methods relate to a bond-pad structure having small pad-substrate capacitance for use in high-voltage MOSFETs. The bond-pad structure includes upper and lower polysilicon plates interposed between a metal bonding pad and an underlying semiconductor substrate. The lower polysilicon plate is encapsulated in dielectric materials, thereby rendering it floating. The upper polysilicon plate is conductively coupled to a source of the high-voltage MOSFET. A perimeter of the metal bonding pad is substantially circumscribed, as viewed from a plan view perspective, by a perimeter of the upper polysilicon plate. A perimeter of the upper polysilicon plate is substantially circumscribed, as viewed from the plan view perspective, by a perimeter of the lower polysilicon plate. In some embodiments, the metal bonding pad is conductively coupled to a gate of the high-voltage MOSFET. The pad-substrate capacitance is advantageously made small by this bond-pad structure.

BACKGROUND

Bonding pads provide a method of electrically interconnecting semiconductor devices to circuitry external to the semiconductor device. The bonding pad presents an exposed metal surface for the purpose of electrical connection to the external circuitry. This electrical connection can be performed in various manners, such as wire bonding, solder bumps, gold bumps, etc. The relative size of a bonding pad is relatively large compared with typical minimum device dimensions that can be produced with standard semiconductor processes. The bonding pads are relatively large to facilitate connection via wires and bumps that are large compared to the dimension of the devices manufactured on the semiconductor device.

Because the bonding pad is relatively large, the parasitic electrical parameters associated with the bonding pad can also be relatively large. For example, a bonding pad has a parasitic capacitance associated with the bonding pad. The parasitic capacitance can deleteriously reduce the performance of a device electrically connected to the bonding pad. Thus, the present disclosure is directed to bonding-pad structures that reduce the parasitic capacitance associated therewith.

SUMMARY

Apparatus and associated methods relate to a bonding-pad structure for minimizing capacitance to a drain-biased semiconductor substrate of a high-voltage MOSFET. The bonding-pad structure includes a first dielectric layer on top of the semiconductor substrate. A first polysilicon plate is disposed on top of the first dielectric layer. A second dielectric layer is formed on top of the first polysilicon plate. The first and second dielectric layers encapsulate the first polysilicon plate, thereby electrically isolating the first polysilicon plate from the semiconductor substrate. A second polysilicon plate is disposed on top of the second dielectric layer. The second polysilicon plate is conductively coupled to a source of the high-voltage MOSFET. A third dielectric layer is formed on top of the second polysilicon layer. A metal bonding pad is disposed on top of the third dielectric layer. The metal bonding pad is electrically isolated from both the first and second polysilicon plates.

Some embodiments relate to a method of manufacturing a bonding pad. The method includes providing a semiconductor substrate and depositing a first dielectric layer on top of the provided semiconductor substrate. A first polysilicon layer is then deposited on top of the deposited first dielectric layer. The deposited first polysilicon layer is selectively etched so as to produce a first polysilicon plate. Then, a second dielectric layer is deposited on top of the first polysilicon plate. The deposited first and second dielectric layers encapsulate the first polysilicon plate, thereby electrically isolating the first polysilicon plate from the semiconductor substrate. A second polysilicon layer is deposited on top of the deposited second dielectric layer. Then the deposited second polysilicon layer is selectively etched so as to produce a second polysilicon plate. The second polysilicon plate is conductively coupled to a source of the high-voltage MOSFET. Then, a third dielectric layer is deposited on top of the second polysilicon plate. A metal bonding pad is formed on top of the deposited third dielectric layer. The metal bonding pad is electrically isolated from both the first and second polysilicon plates.

DETAILED DESCRIPTION

Apparatus and associated methods relate to a bond-pad structure having small pad-substrate capacitance for use in high-voltage MOSFETs. The bond-pad structure includes upper and lower polysilicon plates interposed between a metal bonding pad and an underlying semiconductor substrate. The lower polysilicon plate is encapsulated in dielectric materials, thereby rendering it floating. The upper polysilicon plate is conductively coupled to a source of the high-voltage MOSFET. A perimeter of the metal bonding pad is substantially circumscribed, as viewed from a plan view perspective, by a perimeter of the upper polysilicon plate. A perimeter of the upper polysilicon plate is substantially circumscribed, as viewed from the plan view perspective, by a perimeter of the lower polysilicon plate. In some embodiments, the metal bonding pad is conductively coupled to a gate of the high-voltage MOSFET. The pad-substrate capacitance is advantageously made small by this bond-pad structure.

FIG. 1is a drawing of a cross-sectional view of an exemplary low-capacitance gate bonding pad. InFIG. 1, a portion of a high-voltage MOSFET10that includes bonding-pad structure12is shown. Bonding-pad structure12includes a series of layers of various materials. Beginning from the bottom of the depicted embodiment, bonding-pad structure12is formed on top of semiconductor substrate14. On top of semiconductor substrate14is first dielectric layer16. In some embodiments, first dielectric layer is formed by oxidizing the top surface of semiconductor substrate14. In some embodiments, first dielectric layer16is called a liner oxide. On top of first dielectric layer16is first polysilicon plate18. Above first polysilicon plate18is second dielectric layer20. First polysilicon plate18can be electrically coupled to a source electrode of the high-voltage MOSFET or first and second dielectric layers16and20can encapsulate first polysilicon plate18thereby floating or isolating first polysilicon plate18from other conductive regions and electrical nets of high-voltage MOSFET10. In some embodiments, second dielectric layer20includes a high-density deposited (HDP) glass.

Second polysilicon plate22is formed above second dielectric layer20. Third dielectric layer24is formed above second polysilicon plate22. In some embodiments, second polysilicon plate22is oxidized, thereby creating an oxidation coating24A on the top and sides of second polysilicon plate22. In some embodiments, third dielectric layer24includes a borophosphosilicate glass layer24B. Above third dielectric layer24is metal bonding pad26. Above metal bonding pad26is polyimide film28. Polyimide film28has been selectively removed, thereby exposing portion30of metal bonding pad26so as to permit a bond wire to be bonded thereto. For example, selectively removing polyimide film28at portion30, which is inset from a periphery of metal bonding pad26, permits electrical connection between metal bonding pad26of high-voltage MOSFET10and an electrical component external to the semiconductor die (e.g., a package, a lead-frame, a circuit board, and/or other electrical circuit element).

Between the metal bonding pad26and semiconductor substrate14are two separate polysilicon plate(s)18and/or22, each isolated above and below by dielectric layers16and20and/or dielectric layers20and24, respectively. First and second polysilicon plate(s)18and/or22are configured to provide electrical shielding between metal bonding pad26and semiconductor substrate12upon which bonding-pad structure12is formed. Such electrical shielding provides a low capacitance and low leakage current between metal bonding pad26and semiconductor substrate12. In some embodiments, semiconductor substrate14is drain biased beneath all or most of metal bonding pad26. In some embodiments, both metal bonding pad26and second polysilicon plate22are gate biased. In other embodiments, second polysilicon plate22can be floating or source biased. Thus, a large voltage differential can be produced for high-voltage MOSFET10between drain biased semiconductor substrate14, and metal bonding pad26, for example.

In some embodiments, semiconductor substrate14of high-voltage MOSFET10is conductively coupled to a drain of high-voltage MOSFET10. Thus, the substrate is drain-biased, and the substrate can be biased to a maximum drain voltage that can be specified for high-voltage MOSFET10. In some embodiments, metal bonding pad26can be conductively coupled to a gate of high-voltage MOSFET10. Such conductive coupling of the gate to metal bonding pad26can be achieved via interconnect wiring, vias and/or contacts.

In some applications, high-voltage MOSFET10is configured to amplify and invert the gate-voltage signal supplied to high-voltage MOSFET10. This amplified and inverted gate-voltage signal can be provided as a drain voltage signal. An effective capacitance between the gate and the drain, as seen from the gate terminal, of high-voltage MOSFET10configured in such a manner can be many times higher than the actual capacitance between the gate and drain. This amplification of the capacitance is called the Miller amplification. Because of the inversion and gain between these two nodes, from the perspective of the gate terminal the capacitance acts as if it were (1-Av) times the actual capacitance between the gate and drain. Here Av is the voltage gain at the drain with respect to the gate, and (1-Av) is often called the Miller gain. Because the effective capacitance—the Miller capacitance—can be many times larger than the actual capacitance, reducing the actual gate-drain capacitance can be very advantageous. Gate-drain capacitance can be reduced without increasing the thickness of second dielectric layer24by forming first polysilicon plate18between substrate14and metal bonding pad26.

Providing shield(s), such as polysilicon plates18and/or22surrounded by dielectric layers16and20and/or dielectric layers20and24, respectively, between the gate bonding pad and the drain-biased substrate can reduce the actual capacitance between the metal bonding pad26and semiconductor substrate14. Polysilicon plate(s)18and/or22serve as electrical shields between metal bonding pad26and semiconductor substrate14. The actual capacitance between metal bonding pad26and second polysilicon plate22can be greater than the capacitance between metal bonding pad26and semiconductor substrate14would be without intervening polysilicon plate(s)18and/or22. By forming lower polysilicon plate18the distance separating upper polysilicon plate22and substrate14can be increased, thereby decreasing the capacitance therebetween.

Although the actual capacitance between metal bonding plate26and second polysilicon plate22is larger than the capacitance between metal bonding plate26and substrate14, the metal bonding plate26/second polysilicon plate22effective capacitance can still be much less than the metal bonding plate26/substrate14effective capacitance, because of Miller gain. This can result in a lower effective capacitance, as seen from the gate terminal. In some embodiments, the upper and/or lower polysilicon plates can be isolated (e.g., floating) or conductively coupled to some biasing node (e.g., source terminal) other than the gate terminal. In the depicted embodiment, electrical biasing of the upper and lower polysilicon plates is not shown. In biased polysilicon plate embodiments, the Miller amplification can be unity, and therefore the effective capacitance seen by metal bonding pad26is equal to the actual capacitance between metal bonding pad26and the biased polysilicon plate18or22nearest to metal bonding pad26.

FIG. 2is a plan view of a layout of an exemplary low-capacitance gate bonding pad. InFIG. 2, four specific layers have been identified: i) Field Plate polysilicon feature (FP); ii) Gate Polysilicon feature (GP); iii) Metal feature; and iv) Polyimide Film feature (PIF). In the depicted embodiment, the Gate Polysilicon feature (GP) is the upper or second polysilicon plate22depicted inFIG. 1. The Field Plate polysilicon feature (FP) is the lower or first polysilicon plate18depicted inFIG. 1. In the depicted embodiment, Polyimide Film feature PIF is a layout feature that defines portion30from which the polyimide film28is removed, thereby exposing a portion of the underlying metal bonding pad26.

A perimeter of the depicted Polyimide Film feature PIF is entirely circumscribed by a perimeter of underlying metal bonding pad26as defined by the Metal feature. The Metal feature includes metal bonding pad26and metal interconnect wire32laterally extending from metal bonding pad26. Metal bonding pad26includes the portion30exposed by the selective remove of the polyimide film28as defined by the PolyImide Film feature PIF as well as metal skirt34surrounding the PolyImide Film feature PIF.

The perimeter of the depicted metal bonding pad26is substantially circumscribed by a perimeter of the underlying upper polysilicon plate22as defined by the Gate Polysilicon feature GP. The perimeter of the depicted metal bonding pad26is not entirely circumscribed by a perimeter of the underlying upper polysilicon plate22, because metal interconnect wire32(e.g., to provide electrical conduction between metal bonding pad26and the gate of the device) laterally extends from metal bonding pad26. Herein the term “substantially circumscribing” means that if the extending interconnecting wire(s) is severed from the substantially circumscribed layer, the remaining feature is entirely circumscribed. The Gate Polysilicon GP feature includes upper polysilicon plate22and polysilicon interconnect wire36laterally extending from upper polysilicon plate22. The perimeter of the depicted metal bonding pad26traverses laterally extending polysilicon wire36, thereby defining a connection location of laterally extending polysilicon wire36(e.g., to provide biasing of upper polysilicon plate22) to upper polysilicon plate22. Laterally extending polysilicon wire36, can provide conductive connection between the source of high-voltage MOSFET10and upper polysilicon plate. Such conductive connection can be achieved via interconnect wiring, vias and/or contacts. The perimeter of the depicted upper polysilicon plate22is circumscribed by a perimeter of the underlying lower polysilicon plate18as defined by the Field Plate polysilicon FP feature.

FIG. 3is a cross-sectional view of an exemplary MOSFET with integral edge-termination structures. InFIG. 3, MOSFET40includes active-device trenches42, edge-termination trenches44, and periphery trench46. Note that periphery trench46has a latitudinal width that is larger than latitudinal widths of active-device trenches42and edge-termination trenches44. Because periphery trench46has a larger latitudinal width, periphery trench46is also deeper than active-device trenches42and edge-termination trenches44. Each of active-device trenches42, edge-termination trenches44, and periphery trench46has dielectric sidewalls and a dielectric bottom. The dielectric sidewalls and dielectric bottom electrically isolating a conductive core within each of the longitudinal trenches from a drain-biased region outside of and adjacent to the longitudinal trench. In the depicted embodiment, the conductive core includes conductive gate polysilicon48and conductive field polysilicon50, separated from conductive gate polysilicon48by inter-polysilicon dielectric52.

In the depicted embodiment, gate polysilicon48is patterned to act as a field plate extending over the top of the active die between and beyond edge-termination trenches44and periphery trench46. MOSFET40also includes metallization layer54, which in this cross-sectional view makes electrical contact with source56of MOSFET40. Metallization layer54has been patterned so that it also acts as a field plate extending directly over edge-termination trenches44, and periphery trench46.

Active-device trenches42of MOSFET40have been disclosed by Kosier et al. in U.S. patent application Ser. No. 14/989,032, filed Jan. 6, 2016, titled “Self-Aligned Split-Gate Trench Power MOSFET,” the entire disclosure of which is hereby incorporated by reference. An embodiment of a split-gate trench MOSFET disclosed in the Kosier application will be described with respect toFIG. 8below.FIG. 8is a reproduction of FIG. 1 of the Kosier application.

FIG. 8is a side elevation view of a cross-section of split-gate trench MOSFET110. Split-gate trench MOSFET110includes trenches112etched into silicon layer113, gate structures114aand114b, source regions116, body regions118, and drain120. Body regions118may include heavily doped regions121. Gate structures114aand114bare separated from source regions116, body regions118, and drain120by dielectric122. Topside metal124is formed over silicon layer113and configured to contact, for example, heavily doped regions121and source regions116. Dielectric122may be relatively thin so as to facilitate the field effect of gate structures114aand114bupon body region118. Gate structures114aand114bmay be, for example, polysilicon, and dielectric122may be silicon-dioxide. Source regions116and drain120may be doped either both n-type or p-type depending on the desired transistor species, with body regions118being doped opposite the type of source regions116and drain120.

Trenches112include device gate structure114aand field gate structure114btherein. Field gate structure114bmay be biased such that field gate structures114bin adjacent trenches112effectively shield intervening semiconductor pillars (i.e. the portion of silicon layer113located between adjacent trenches112) from excessive voltage. Drain120may be biased, for example, with a high voltage via a backside wafer connection (not shown). Field gate structures114bon either side of semiconductor pillars can effectively shield the respective semiconductor pillar from voltages that might cause breakdown of MOSFET110.

In the embodiment illustrated inFIG. 8, no contact is etched into silicon layer113between trenches112. Topside metal124is able to contact both heavily doped body region121and source region116. In prior art transistors, a high aspect ratio contact (i.e. a deep, narrow contact etched into the silicon) was required for the topside metal to contact both the body and the source regions of the transistor. Body region118, along with heavily doped region121, may be implanted into silicon layer113in a manner that is self-aligned to trenches112. Source region16may be implanted, for example, into silicon layer113in a manner that is self-aligned to gate structure114a. Because of this, topside metal124contacts both body region118and source region116without the need for a deep contact between trenches112. Without a deep contact between trenches112, the pitch (P1) between trenches112may be, for example, less than one micron. Although illustrated inFIG. 8with a relatively planar surface, silicon layer113may be non-planar in contact with topside metal124depending upon the method of fabricating MOSFET112. Even in non-planar embodiments, however, no deep contact is required for topside metal124and thus, the pitch (P1) may be minimized.

FIG. 4is a close-up plan view of a layout of a MOSFET with integral edge-termination structures. InFIG. 4, the sequence of parallel and longitudinal trenches42of the MOSFET is again depicted. Between adjacent longitudinal trenches42,44and46in the sequence are defined longitudinal semiconductor pillars64. The depicted MOSFET also has a perpendicular trench66merged with each of longitudinal ends of each of the sequence of parallel longitudinal trenches42,44and46.

In the depicted embodiment the lateral width W1of the first (and/or last) longitudinal trench46is equal to the lateral width W2of the perpendicular longitudinal trench66. The lateral widths W1and W2of the first (and/or last) longitudinal trench46and the perpendicular longitudinal trench66are each greater than the lateral width W3of the other trenches42and44in the sequence of longitudinal trenches42,44and46. These other trenches42and44include both active-device trenches and other edge-termination trenches. In some embodiments, a ratio between the lateral width W1of the first (and/or last) longitudinal trench46to lateral width W3of the other trenches42and44in the sequence of longitudinal trenches42,44and46is greater than 1.25, 1.33, 1.5 or 2.0. In some embodiments, a ratio between the lateral width W2of the perpendicular longitudinal trench66to lateral width W3of the other trenches42and44in the sequence of longitudinal trenches42,44and46is greater than 1.25, 1.33, 1.5 or 2.0.

Some embodiments relate to a MOSFET with integral edge termination structures. The MOSFET includes a sequence of parallel and alternating longitudinal trenches and longitudinal semiconductor pillars. Each of the longitudinal trenches has dielectric sidewalls and a dielectric bottom. The dielectric sidewalls and dielectric bottom are electrically isolating a conductive core within each of the longitudinal trenches from a drain-biased region outside of and adjacent to the longitudinal trench. A first and a last longitudinal trench in the sequence of parallel and alternating trenches has a latitudinal width that is larger than latitudinal widths of the longitudinal trenches between the first and the last longitudinal trench. The MOSFET also includes a perpendicular trench merged with each of longitudinal ends of each of the sequence of parallel longitudinal trenches. Each of the perpendicular trenches has a latitudinal width that is larger than latitudinal widths of the longitudinal trenches between the first and the last longitudinal trench.

FIG. 5is drawing of a cross-section of an exemplary seal ring configured to block diffusion of contamination from an edge of a die. InFIG. 5, a peripheral portion of a semiconductor device70is shown in cross-section. The die's edge72is shown at the right-hand side of the figure. The semiconductor device70is covered with polyimide film74to protect the semiconductor device70from mechanical stress, diffusion of mobile ions and moisture. Polyimide film74covers substantially the entire semiconductor device70with the exception of bonding pads (not depicted in the figure) located on the top surface of the die. In the depicted embodiment, an outer annular trench76is cut through a BoroPhosphoSilicate Glass (BPSG) layer78and a High-Density Plasma deposited Glass (HDP) layer80and is cut into semiconductor substrate82. The BPSG78and the HDP80layers provide a glass passivation layer for semiconductor device70. In some embodiments, outer annular trench76circumscribes a split-gate power MOSFET fabricated in an interior portion of the semiconductor die (not shown inFIG. 1).

InFIG. 5, inner annular trench84is depicted as well. Inner annular trench84is located between outer annular trench76and the split-gate power MOSFET. Inner annular trench84has dielectric sidewalls86and a dielectric bottom88. Dielectric sidewalls86and dielectric bottom88electrically isolate two conductive cores90and92within inner annular trench84from a drain-biased region of the semiconductor die outside of and adjacent to inner annular trench84. Polysilicon field plate90is formed within dielectric sidewalls86and dielectric bottom88. Polysilicon plug92is formed within dielectric sidewalls86and above polysilicon field plate90. Polysilicon plug92is separated from polysilicon field plate90by an HDP glass barrier therebetween. Polysilicon field plate90and polysilicon plug92can be biased to control an electric field along the periphery of the semiconductor die. Inner annular trench84can be referred to as an EQual potential Ring (EQR).

FIG. 6is a drawing of a cross-section of an exemplary gate polysilicon ring94without inner annular trench84. In the depicted embodiment, no inner annular trench84has been formed below the EQR ring94of gate poly. Because no inner annular trench84has been formed, gate polysilicon ring94is perched on the top of the HDP glass80, which is a relatively thick. The HDP glass permits mobile ions to diffuse therethough. These mobile ions can cause the behavior of the semiconductor device to degrade in performance. Such a configuration is therefore not advantageous as a barrier to diffusion of contaminants. This embodiment is shown as a comparison to the embodiment depicted inFIG. 5. TheFIG. 5embodiment presents a better barrier to diffusion of contaminants by providing a more constricted diffusion path, as will be described with reference toFIG. 7below.

FIG. 7is a drawing of a cross-section of an exemplary gate polysilicon ring without a trench. The EQR ring depicted inFIG. 5is shown in close-up inFIG. 7. Contrary to the configuration depicted inFIG. 6, theFIG. 7embodiment provides a good barrier to diffusion of contaminants. This is because the HDP glass is etched in the inner annular trench regions84. Thus only a thin gate oxidation96, which is formed after the HDP etch separates the gate polysilicon from the top of the semiconductor die, resides between polysilicon plug92and semiconductor substrate82. This polysilicon plug92presents an improved barrier to the diffusion of contaminants compared with the relatively thick un-etched HDP glass. Both inner annular trench84and outer annular trench76circumscribe the split-gate power MOSFET. Outer annular trench76is proximate edge72of the semiconductor die. In some embodiments, polysilicon plug92is conductively coupled to a drain of the split-gate power MOSFET so that both polysilicon plug92and the drain-biased surrounding region of the semiconductor die are biased at the drain biasing potential.

Some embodiments relate to a semiconductor device that can include a semiconductor die. The semiconductor device includes a split-gate power MOSFET having a source, a gate, and a drain. The semiconductor device has passivation glass on the semiconductor die. The semiconductor device includes two bonding pads configured to provide electrical conduction between a top of the semiconductor device through the passivation glass and to each of the source and the gate of the split-gate power MOSFET. The semiconductor device includes an outer annular trench circumscribing the split-gate power MOSFET. The outer annular trench cuts through the passivation glass on a semiconductor die and cuts into the semiconductor die. The semiconductor device also a polyimide film substantially covering the die except for the two bonding pads. The polyimide film fills the outer annular trench.

In some embodiments, the semiconductor device can further include an inner annular trench between the split-gate power MOSFET and the outer annular trench. The inner annular trench has dielectric sidewalls and a dielectric bottom. The dielectric sidewalls and dielectric bottom electrically isolated a conductive core within the inner annular trench from a drain-biased region of the semiconductor die outside of and adjacent to the inner annular trench. The dielectric sidewalls also isolate a polysilicon plug from the drain-biased region of the semiconductor die outside and adjacent to the inner annular trench. The polysilicon plug is vertically isolated from the conductive core within the inner annular trench via a dielectric. The polysilicon plug can be conductively coupled to the drain biased semiconductor die via a conductive net.

Discussion of Possible Embodiments

Apparatus and associated methods relate to a bonding-pad structure for reducing capacitance to a semiconductor drain-biased substrate of a high-voltage MOSFET. The bonding-pad structure includes a first dielectric layer on top of the semiconductor substrate. The bonding-pad structure includes a first polysilicon plate on top of the first dielectric layer. The bonding-pad structure includes a second dielectric layer on top of the first polysilicon plate. The first and second dielectric layers encapsulate the first polysilicon plate, thereby electrically isolating the first polysilicon plate from the semiconductor substrate. The bonding-pad structure also includes a metal bonding pad directly above the first polysilicon plate and the second dielectric layer, the metal bonding pad electrically isolated from the first polysilicon plate.

A further embodiment of the foregoing bonding-pad structure can further include a second polysilicon plate on top of the second dielectric layer. The second polysilicon plate can be positioned substantially between the first polysilicon plate and the metal bonding pad and conductively coupled to the gate of the high-voltage MOSFET. The bonding-pad structure can further include a third dielectric layer on top of the second polysilicon plate.

A further embodiment of any of the foregoing bonding-pad structures, wherein the metal bonding pad can be conductively coupled to a gate of the high-voltage MOSFET.

A further embodiment of any of the foregoing bonding-pad structures, wherein the metal bonding pad can be conductively coupled to a gate of the high-voltage MOSFET via, at least in part, a metal wire laterally extending from the metal bonding pad.

A further embodiment of any of the foregoing bonding-pad structures, wherein the metal bonding pad, when viewed from a plan view perspective, can have a periphery that is substantially circumscribed by a periphery of the second polysilicon plate.

A further embodiment of any of the foregoing bonding-pad structures can further include a polyimide film on top of the metal bonding pad, wherein the polyimide film is selectively removed so as to expose a portion of the metal bonding pad to which a bond wire can be bonded.

A further embodiment of any of the foregoing bonding-pad structures can further include a polyimide film on top of the metal bonding pad, wherein the polyimide film is selectively removed so as to expose a portion of the metal bonding pad to which a bond wire can be bonded. The portion of the metal bonding pad exposed by the removal of the polyimide film, when viewed from a plan view perspective, has a perimeter that is entirely circumscribed by a perimeter of the second polysilicon plate.

A further embodiment of any of the foregoing bonding-pad structures, wherein the second polysilicon plate, when viewed from a plan view perspective, can have a periphery that is substantially circumscribed by a periphery of the first polysilicon plate.

A further embodiment of any of the foregoing bonding-pad structures, wherein the second polysilicon plate can be conductively coupled to a source of the high-voltage MOSFET via, at least in part, a polysilicon wire laterally extending from the second polysilicon plate.

A further embodiment of any of the foregoing bonding-pad structures, wherein the second dielectric layer can include a borophosphosilicate glass (BPSG).

A further embodiment of any of the foregoing bonding-pad structures, wherein the third dielectric layer can include a high-density plasma (HDP) deposited glass.

Some embodiments relate to a method of manufacturing a bonding pad. The method includes providing a semiconductor substrate. The method includes depositing a first dielectric layer on top of the semiconductor substrate. The method includes depositing a first polysilicon layer on top of the first dielectric layer. The method includes selectively etching the first polysilicon layer so as to produce a first polysilicon plate. The method includes depositing a second dielectric layer on top of the first polysilicon plate. The first and second dielectric layers can encapsulate the first polysilicon plate, thereby electrically isolating the first polysilicon plate from the semiconductor substrate. The method can also include depositing a metal bonding pad directly above the first polysilicon plate and the second dielectric layer. The metal bonding pad can be electrically isolated from the first polysilicon plate.

A further embodiment of the foregoing method can include depositing a second polysilicon layer on top of the second dielectric layer. The method can include selectively etching the second polysilicon layer so as to produce a second polysilicon plate. The method can include conductively coupling the second polysilicon plate to a source of the high-voltage MOSFET. The method can also include depositing a third dielectric layer on top of the second polysilicon plate.

A further embodiment of any of the foregoing methods can include conductively coupling the metal bonding pad to a gate of the high-voltage MOSFET.

A further embodiment of any of the foregoing methods, wherein conductively coupling the metal bonding pad to a gate of the high-voltage MOSFET can include laterally extending a metal wire from the metal bonding pad.

A further embodiment of any of the foregoing methods, wherein the metal bonding pad, when viewed from a plan view perspective, can have a periphery that is substantially circumscribed by a periphery of the second polysilicon plate.

A further embodiment of any of the foregoing methods can include depositing a polyimide film on top of the metal bonding pad. The method can include selectively removing the polyimide film so as to expose a portion of the metal bonding pad to which a bond wire can be bonded.

A further embodiment of any of the foregoing methods can include depositing a polyimide film on top of the metal bonding pad. The method can include selectively removing the polyimide film so as to expose a portion of the metal bonding pad to which a bond wire can be bonded. The portion of the metal bonding pad exposed by the removal of the polyimide film, when viewed from a plan view perspective, can have a perimeter that is entirely circumscribed by a perimeter of the second polysilicon plate.

A further embodiment of any of the foregoing methods, wherein the second polysilicon plate, when viewed from a plan view perspective, can have a periphery that is substantially circumscribed by a periphery of the first polysilicon plate.

A further embodiment of any of the foregoing methods, wherein conductively coupling the second polysilicon plate to a source of the high-voltage MOSFET can include laterally extending a polysilicon wire from the second polysilicon plate.

A further embodiment of any of the foregoing methods, wherein depositing the second dielectric layer on top of the second polysilicon plate can include depositing a borophosphosilicate glass (BPSG).

A further embodiment of any of the foregoing methods, wherein depositing the third dielectric layer on top of the first polysilicon plate can include depositing glass using a high-density plasma (HDP).