Memory device, its access method, and memory system

A memory device comprises a controller having an interface and an MPU, and configured to enable transferring a device driver for a second access mode via the interface in a first access mode, the second access mode differently defined from the first access mode, and a semiconductor memory with the device driver stored thereon.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is based upon and claims the benefit of priority from prior Japanese Patent Application No. 2006-206615, filed Jul. 28, 2006, the entire contents of which are incorporated herein by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a memory device, its access method, and a memory system. The invention is applied to a memory device, etc., on which, for example, a NAND type flash memory is mounted as the memory device.

2. Description of the Related Art

Conventionally, when a host device attempts to access a memory device having a differently defined access mode (new interface (hereinafter, referred to as I/F) protocol), it cannot access thereto because device drivers to drive access modes are different from each other. In addition, in accessing through the differently defined access mode, the memory device needs to replace the device driver of the host device. Because the device driver is installed in firmware on a read only memory (ROM) of the host device and the ROM is impossible to be rewritten.

In contrast, the replacement of the firmware in the host device also requires to replace, for instance, an I/F of the memory device such as an NAND type flash memory. Therefore, the host device becomes impossible to access the NAND type flash memory which the host device has accessed until then.

Accordingly, in such case, the host device has to prepare firmware corresponding to two kinds of access modes for the device driver for the NAND type flash memory and the device driver for the differently defined access mode (new I/F protocol). Or, the host device needs to prepare more than two kinds of device drivers and also select any one of the device drivers from a plurality of device drivers depending on the memory device connected to the host device.

As a result, when accessing a memory device having any access mode of differently defined (new I/F protocol), the host device needs to replace the device driver thereof, so that the memory device results in reducing its convenience.

For instance, Jpn. Pat. Appln. KOKAI Publication No. 2001-266580 discloses a system equipped with a memory device of a common interface method.

BRIEF SUMMARY OF THE INVENTION

A memory device according to an aspect of the invention comprises a controller having an interface and an MPU, and configured to enable transferring a device driver for a second access mode via the interface in a first access mode, the second access mode differently defined from the first access mode, and a semiconductor memory with the device driver stored thereon.

An access method for a memory device, according to an aspect of the invention, which is having a controller including an interface and an MPU, and a semiconductor memory with a device driver for a second access mode differently defined from a first access mode stored thereon, comprising: accessing the controller to the outside in the first access mode via the interface; and transferring the device driver via the interface.

A memory system according to an aspect of the invention comprises a host device having a CPU, a host interface, and a ROM to store a first device driver for driving a first access mode, and a memory device having a controller including a memory interface and an MPU and enable transferring a second device driver for a second access mode differently defined from the first access mode in accessing the host device in the first access mode via the memory interface, and a semiconductor memory with the second device driver stored thereon.

DETAILED DESCRIPTION OF THE INVENTION

Embodiments of the invention will be described with reference to the drawings hereinafter. In the description, common components are designated by common reference symbols over the whole drawings.

A memory device regarding a first embodiment of the present invention will be described while referring toFIG. 1toFIG. 3.FIG. 1is a plan view for explaining the memory device relating to the first embodiment. A use environment of a memory device11regarding the first embodiment is one of a type in which a host device12loads a driver (LBA NAND device driver)17-2therefor from a NAND type flash memory15.

The memory device11and the host device12are arranged as shown inFIG. 1.

The host device12has hardware and software for accessing the memory device11to be accessed via a bus (not shown).

The memory device11is driven by receiving power supply on being connected to the host device12to conduct processing corresponded to access from the host device12. The memory device11performs rear-out/write-in in so-called sector units or in prescribed data size units. Hereinafter, the memory device11in the first embodiment will be described as an example in which the memory device11is solder-mounted on a printed board like a below-mentioned TSOP package, etc.

The memory device11includes a NAND type flash memory15that is a memory device and a controller16to control the flash memory15.

The flash memory15has stored the LBA NAND device driver17-2to drive an LBA NAND access mode (second access mode)26-2. The LBA NAND access mode26-2is an access mode (new I/F protocol) differently defined from a Pure NAND access mode (first access mode)26-1to access (connect) the flash memory15.

As mentioned later, the LBA NAND access mode (hereinafter, referred to as LBA NAND mode)26-2uses the same signal pins as those of the Pure NAND access mode (hereinafter, referred to as Pure NAND mode)26-1, and a command sequence of the LBA NAND mode26-2makes communications via the same NAND I/Fs20and31according to the Pure NAND mode26-1. In this case, the command sequence means a series of order (input timing) through which commands, addresses and data are input.

As mentioned above, definitions of addresses in the LBA NAND mode26-2are different from those of the Pure NAND mode26-1. That is, as compared that the Pure NAND mode26-1accesses by using physical addresses (such as column addresses and page addresses), the LBA NAND mode26-2differs in the definitions of the addresses in respect of being accessed with the use of logical sector addresses. In conducting read-out operations in the Pure NAND mode26-1, the memory device11may read out the data preset in the prescribed order without referring to the addresses issued from the host device12.

The LBA NAND mode26-2is an access mode of error free (error-correcting code (ECC)-corrected data is output) which receives accesses in logical sector access hierarchies and does not need to be conscious of sizes of erased blocks.

FIG. 2illustrates a data arrangement in the NAND type flash memory15. As illustrated inFIG. 2, each page of the flash memory15has a 2,112 B (data memory part of 2 k byte+redundancy part of 64 byte (wherein, k represents 1,024)+managed data memory part of24B), for example, 128-page represents one erasure unit (256 kB+8 kB, wherein, k represents 1,024). In the following descriptions, as a matter of convenience, the erasure unit of the flash memory15is set to 256 kB.

The flash memory15has a page buffer41A to perform a data input and output to and from the flash memory15. The memory capacity of the page buffer41A is 2,112 B (2,048 B+64 B). In writing in the data, etc., the page buffer41A executes the data input and output to the flash memory15in units by one page equivalent to its own memory capacity.

If the memory capacity of the flash memory15is, for instance, 1 G bits, the number of 256 kB-blocks (erasure unit) becomes 512 pieces.

InFIG. 2, the erasure unit of 256 kB-blocks being exemplified, it is practically effective to establish the erasure unit to become, for example, 16 kB-blocks. In this case, each page has 528 B (data storage part of 512 B+redundancy part of 16 B), and 32-page is one erasure unit (16 kB+0.5 kB).

The controller16manages a physical condition inside the flash memory15(for instance, what number logical sector address data is included in which physical block address, or which block is erasure condition). The controller16has NAND type flash memory interfaces (hereinafter, referred to as NAND I/F)20and22, a micro processing unit (MPU)21, and a buffer random access memory (RAM)23.

The MPU21is provided with a program read only memory (ROM)17, and configured to control operations of the whole of the memory device11. For example, when the memory device11receives the power supply, the MPU21reads out the firmware (control program) stored on the flash memory15onto the buffer RAM23to execute prescribed processing, then, it creates various kinds of tables on the buffer RAM23. The MPU21is configured to receive a write-in command, read-in command and erasure command from the host device12, execute prescribed processing to the flash memory15, and control data transfer processing through the buffer RAM23.

The program ROM17has stored a program (not shown) so that the memory device11operates in the LBA NAND mode26-2. The program ROM17is provided so that the MPU21receives the commands transmitted from the host device12to send predetermined responses.

The buffer RAM23is configured, for instance, in writing the data transmitted from the host device12to the flash memory15, so as to temporarily store a fixed amount of data (for example, of one page), and in transmitting the data read-out from the flash memory15, so as to temporarily store the fixed amount of the data.

A device identification (ID)25is set to the NAND I/F20. The device ID25is data to be output from the memory device11through a prescribed protocol in order to identify the memory device11is an already known device by the host device12when the host device12accesses the memory device11in the below-mentioned access mode transition operations. Furthermore, the device ID25can determine such as a device capacity, erasure block size and page length of the memory device11. It is not always necessary for the capacity, erasure block size, page length, etc. of the memory device11which can be determined by means of the device ID to be equal to the capacity, erasure block size, page length, etc. of the flash memory15mounted on the memory device11.

The host device12includes a CPU30, a NAND I/F31, a ROM32and a RAM33.

The CPU30is configured in order to control the operations of the whole of the host device12. The CPU30, for instance, operates so as to execute prescribed processing for predetermined commands received from the memory device12.

The ROM32has stored Pure NAND device driver17-1to drive the Pure NAND mode26-1. Therefore, reading out the device ID25though the host device12enables the host device12to access the memory device11in the Pure NAND mode (first access mode)26-1as an already known access mode.

The RAM33has stored the LBA NAND device driver17-2for driving the LBA NAND mode26-2. The LBA NAND device driver17-2is loaded from the memory device11through the below-mentioned access mode transition operations to be installed in the RAM33.

The host device12accesses the memory device11via the NAND I/F31to conduct operations such as writing and reading.

The signals exchanged between the memory device11and the host device12are described as follows.

An I/O signal includes signals of an address, data and prescribed command.

A command latch enable (CLE) signal is a signal to control taking in an operation command to the inside of the memory device11, and data on I/O terminals is taken in as a command into a command register by achieving the CLE signal at an H level at a rising edge and a down edge of a write enable (WE) signal.

An address latch enable (ALE) signal is a signal to control taking in address data to an address register inside the device, and the data on the I/O terminals is taken in as address data into the corresponding register by achieving the ALE signal at the H level at the rising edge and the down edge of the WE signal.

A chip enable (-CE) signal is a device selecting signal, and becomes a standby mode for low power by achieving the -CE signal at an H level in a Ready condition. In a Busy condition during operations of a program, erasure and read (RY/-BY=“L”), both conditions of “H” and “L” are acceptable.

A write enable (-WE) signal is a signal to take in each data from the I/O terminals to the inside of the device.

A read enable (-RE) signal is a signal to output the data serially from the I/O terminals.

A write protect (WP) signal is a signal to forcibly prohibit writing and erasing operations, and operations of an inside high-voltage generation circuit is reset at WP=“L”. The WP signal is a signal used at WP=“H”, but it is used to control to a condition of WP=“L” and protect stored data from unexpected operations when an input signal is indeterminate as like in shutting off power supply, or the like.

A ready/busy (RY/-BY) signal is an output signal to notify the inside operation condition of the memory device11. In programming, erasing and reading, during an internal execution, the memory device11outputs the busy signal (RY/BY=“L”), and when completing the output, the memory device11automatically outputs the ready signal (RY/BY=“H”).

The memory device11may be used by sealing it in a package (thin small outline package (TSOP) package) as shown inFIG. 3.FIG. 4is a view illustrating the names of the pins to which each signal mentioned above is input. Wherein, a signal pin NC inFIG. 4is a signal pin for no use.

Next, access mode transition operations of the memory device regarding the first embodiment will be described while usingFIG. 5toFIG. 11.FIG. 5is a timing chart for explaining the access mode transition operations regarding the first embodiment.FIG. 6is a plan view illustrating the memory device11and the host device12before the access mode transition operations. The transition operations will be described in line with the timing chart inFIG. 5hereinafter.

At first, as shown inFIG. 6, before a time t0(before turning on power source), the LBA NAND device driver17-2has not stored in the RAM33of the host device12yet.

Next to this, at a time t1, on turning on the power of the host device12, the memory device11starts in accordance with a pour source voltage Vcc supplied from the host device12.

Subsequently, at a time t2, the memory device11outputs the device ID25possible to be accessed in the Pure NAND mode26-1(first access mode) known by the host device11to the memory device11.

At this moment, the read-out sequence of the device ID25relating to the first embodiment is expressed as shown inFIG. 7.

The memory device11firstly takes in an ID read command COM34transmitted from the host device12through signal pins I/O1-I/O8at the raising edge of the write enable signal -WE, when the command latch enable signal CLE is “High (hereinafter, referred to as H)”, the chip enable signal -CE is “Low (hereinafter, referred to as L)”, the address latch enable signal ALE is “L”, and the read enable signal -RE is “H”.

Next, the memory device11takes in an address adr 0 35 from signal pins I/O1-I/O8at the raising edge of the write enable signal -WE when the command latch enable signal CLE is “L”, the chip enable signal -CE is “L”, the address latch enable signal ALE is “H”, and the read enable signal -RE is “H”.

Next to this, the host device12takes in a code36from the signal pins I/O1-I/O8at the raising edge of the read enable signal -RE when the command latch enable signal CLE is “L”, the chip enable signal -CE is “L”, the address latch enable signal ALE is “L”, and the read enable signal -RE is “H”. From this moment, the host device12starts a real read-out operation.

Subsequently, the host device12takes in the device ID25from signal pins I/O1-I/O8at the raising edge of the read enable signal -RE when the command latch enable signal CLE is “L”, the chip enable signal -CE is “L”, the address latch enable signal ALE is “L”, and the write enable signal -WE is “H”.

Therefore, after this, the host device12can conducts read-out operations (Read) in the Pure NAND mode26-1driven by the device driver17-1. At this moment, as shown inFIG. 6, in the first embodiment, the host device12performs the read-out operations without passing through the MPU21.

In this case, one read-out sequences in the Pure NAND mode26-1is expressed, for example, as the followingFIG. 9andFIG. 10.

The read-out sequence1is, as shown inFIG. 9, a sequence in which column addresses and page addresses are input between commands 00h and 30h. As for the column address and the page address, for instance, 0000h and 000000h are described.

That is, the memory device11takes in the command 00h to the controller16transmitted from the host device12through the signal pins I/O1-I/O8at the raising edge of the write enable signal -WE when the command latch enable signal CLE is “H”, the chip enable signal -CE is “L”, and the address latch enable signal ALE is “L”.

Next, the memory device11takes in the column address 00h and the page address 00h to the controller16from the signal pins I/O1-I/O8at the raising edge of the write enable signal -WE when the command latch enable signal CLE is “L”, the chip enable signal -CE is “L”, and the address latch enable signal ALE is “H”.

Next to this, the memory device11takes in an end command 30h to the controller16transmitted from the host device12through the signal pins I/O1-I/O8at the raising edge of the write enable signal -WE when the command latch enable signal CLE is “H”, the chip enable signal -CE is “L”, and the address latch enable signal ALE is “L”.

Hereinafter, after the busy signal -BY returns to the ready RY condition, the memory device11synchronizes with the raising edge of the read enable signal -RE to read out the data by clocking the read enable signal -RE.

The read-out sequence2includes, as shown inFIG. 10, only the command 00h and the command 30h (read command46-1), and it omits inputs of the addresses. As mentioned above, it is possible for the read-out operations in the Pure NAND mode to be configured so as not to refer the addresses issued from the host device12and to read out the preset data in prescribed order. In such case, inputs of the addresses may be omitted. The read-out sequence2illustrated inFIG. 10has omitted the inputs of the addresses.

That is, the memory device11takes in a read command COM46-1(command 00h and command 30h) to the controller16transmitted from the host device12through the signal pins I/O1-I/O8when the address latch enable signal ALE is “L”, the chip enable signal -CE is “L”, the read enable signal -RE is “H”, and the command latch enable signal CLE is “H”.

Subsequently, the host device12takes in data (Data0)43-0from the signal pins I/O1-I/O8at the down edge of the read enable signal -RE when the chip enable signal -CE is “L”. The memory device11then outputs the data43-0to the host device12at the raising edge of the read enable signal -RE.

Next to this, after the busy signal -BY returns to the ready condition RY, the host device12takes in data (Data1)43-1from the signal pins I/O1-I/O8at the down edge of the read enable signal -RE when the chip enable signal -CE is “L”. The memory device then outputs the data43-1to the host device12at the raising edge of the read enable signal -RE.

After this, the read-out sequence2repeats the same operations as those mentioned above, and conducts the read-out operations in the Pure NAND mode26-1.

Here, read-out operations in the Pure NAND mode26-1having described in detail, the Pure NAND mode26-1is not limited to the forgoing read-out operations and the writ-in and erasing operations may be implemented in a similar manner.

At the time t2, the host device12loads a Boot code (not shown) stored in the ROM32to perform the read-out operations, etc.

Further, at this moment, the host device12accesses the memory device11in the Pure NAND mode26-1driven by the device driver17-1stored in the memory32. The host device12then stores the LBA NAND device driver17-2in its own RAM32.

Here, the read-out sequence in the LBA NAND mode26-2is expressed as shown inFIG. 11.

The memory device11firstly takes in a read command COM46-2to the controller16transmitted from the host device12through the signal pins I/O1-I/O8at the raising edge of the write enable signal -WE when the command latch enable signal CLE is “H”, the chip enable signal -CE is “L” and the address latch enable signal ALE is “L”.

Next, the memory device11takes in packets45of addresses adr0-adr4to the controller16from the signal pins I/O1-I/O8at the down edge of the write enable signal -WE when the command latch enable signal CLE is “L”, the chip enable signal -CE is “L” and the address latch enable signal ALE is “H”. Among the packets45, the addresses adr0-adr1configure a sector count M, and the addresses adr2-adr4configure a sector address N.

Like this, this embodiment transfers by defining the address as the sector address N (in the embodiment, address having a minimum unit of almost 512 bytes). In contrast, conventionally, the memory device transfers the addresses by dividing them into almost 5 bytes. The sector count M announces beforehand to transfer haw many sectors will be transferred from now.

Subsequently, the memory device11takes in the end command COM46-3to the controller16transmitted from the host device12through the signal pins I/O1-I/O8at the down edge of the write enable signal -WE when the command latch enable signal CLE is “H”, the chip enable signal -CE is “L” and the address latch enable signal ALE is “L”.

Next, the memory device11outputs the ready/busy -RY/-RB signals in the “L” condition (busy condition) during the take in of the packets45.

Next to this, the memory device11transfers a transfer unit47composed of a plurality of pieces of data (Data0, Data1, etc.) to the host device12from the signal pins I/O1-I/O8after a time tR from the down edge of the read enable signal -RE when the chip enable signal -CE is “L”, and the ready/busy -RY/-BY signal is “H”.

The transfer packet of the transfer unit47is transmitted by matching its size with that of the conventional transfer packet (for example, almost 528-byte (512+16) is set as one unit).

Like this, in the present embodiment, even in either access mode of the Pure NAND mode26-1or the LBA NAND mode26-2, the same signal pins I/O1etc., shown inFIG. 3andFIG. 4are used, and both access modes are in conformity to with electric interfaces (signal line definitions).

For the LBA NAND mode26-2, only the read-out operations have been described in detail. However, the LBA NAND mode26-2is not limited to the aforementioned read-out operations, and the write-in and erasing operations, etc., may be done similarly.

Next to this, the host device12establishes a system boot environment, and a LBA NAND access mode26-2environment loaded beforehand. The system boot environment includes, for example, a universal serial bus (USB) memory system, an MP 3 system, and the like.

Next, at a time t3, when the LBA NAND mode environment is completely established, the host device12issues a mode change command FEh (h represents hexadecimal notation).

Subsequently, at a time t4, when receiving the mode change command FEh, the memory device11transits to the LBA NAND mode26-2. After this, the memory device11conducts write-in/read-out (Read/Program) operations, etc., in the transited LBA NAND mode26-2.

At the time t4, the host device12transits to the established LBA NAND mode26-2to start the operation mode for the read-out operations, etc., in the transited LBA NAND mode26-2.

At the later time, as shown inFIG. 8, to change the access area of the memory device11, the host device12issues a mode change command FAh (h represents hexadecimal notation).

Subsequently, when receiving the mode change command FAh, the memory device11changes the access area from a Pure NAND read (PNR) area and a vender firmware store (VFS) area to a music data store (MDS) area. Changing the access area in this manner enables the memory device11to store application data such as music transmitted from the host device12in a prescribed area.

In such case, the PNR area includes an area, which is read out by the host device12in the Pure NAND mode26-1on the basis of the device ID25, and an area with the LBA NAND device driver17-2stored therein. The VFS area is an area to be accessed in the LBA NAND mode26-2, and an area with the firmware of the host device12stored therein. The MDS area is an area which is accessed in the LBA NAND mode26-2, and an area with the music data stored therein, if the host device12is, for example, an audio player.

Further, the access mode transitional operations may be implemented with modifications as follows.

For example, when becoming possible to output data in the Pure NAND mode26-1(at the time t2), the memory device11seems to be in the Ready condition as a device for the host device12. At this moment, it is no matter that the memory device11has not enabled the data to output in the LBA NAND mode26-2yet.

In this case, the memory device11conducts initializing processing to enable the data to output in the LBA NAND26-2after the time t2. The MPU21, for instance, creates system data to store it on the buffer RAM23. Here, as an example of the system data, an address conversion table, etc., may be included. The address conversion table includes a table to convert between the logical addresses and the physical addresses in the flash memory15.

Modifying like this enables starting a firm loading time for the host device12in a short time, and enables reducing the start time. Even if time-out setting until the flash memory15starts the access is relatively short, the host device12can transit to the LBA NAND mode26-2.

Here, the host device12confirms whether or not the access environment of the Pure NAND mode26-2for the memory device11has been already established, for example, in a manner as follows.

After implementing the Pure NAND mode26-1, the host device12firstly issues a reset command to the memory device11. The memory device11then can confirms it by waiting until the Busy condition of its command response becomes the Ready condition. Or, the host device12can confirm it by setting the reset command for exclusive use of the LBA NAND access mode and by waiting until the Busy condition of its dedicated reset command response becomes the Ready condition.

In the case of Pure NAND mode26-1, the memory device11may execute to read out the data preset in prescribed order regardless of the addresses of the flash memory15issued from the host device12.

When the existing NAND type flash memory (firmware) is applied to the ROM32in the host device12, the memory device11may record the access data in the Pure NAND mode26-1so as to enable using an update function (page copy function) of the NAND type flash memory. Of course, even when the LBA NAND mode26-2is put in use, the memory device11may add the update function of the flash memory of the host device12. In operating update writing of the flash memory of the host device12, the memory device11may store the data in data order so as to be read out it in the prescribed order regardless of the addresses of the flash memory issued from the host device12.

In the case of the Pure NAND access mode26-2, the Page lengths of the flash memory have values such as (2 k+64) Bytes. Among of the Page lengths, ECC data, etc. generated from the host device12are included sometimes. In this case, after the host device12comes to know a generation defining formula of the ECC data, the memory device11may generates the ECC data therein, and the memory device11may record the ECC data generated from the host device12as it is in the NAND type flash memory15. When the ECC data generated from the host device12mentioned above is included, the following three aspects may be taken into account.

A first aspect is the case in which the memory device11has known the generation defining formula of the ECC data generated from the host device12. In this case, in operating the writing of the data, the memory device11omits the ECC data received from the host device12to store the rest data in the NAND type flash memory15. In the reading out operations of the data, the memory device11generates the ECC data therein to transmit the data including the ECC data to the host device12.

In the writing operations of the data, the memory device11sometimes writes the ECC data received from the host device12as it is in the NAND type flash memory.

Further, a second aspect is the case, in which in the wiring operations of the data, the memory device11further generates second ECC data for the data including first ECC data received from the host device12within the memory device11, and the memory device11writes in the data including the first ECC data and the second ECC data in the NAND type flash memory15. That is such aspect, in which the memory device11records the data by using two pages of the NAND type flash memory15.

In this case, in general, the memory device11having owned a unique ECC definition, if access from the host device12side has, for instance, a value of (2 k+64) Bytes and the Page length of the NAND type flash memory15mounted on the memory device11is (2 k+64) Bytes, etc., the memory device11performs write-in operations in the Pure NAND access mode26-1through which the memory device11records the data from the host device12of one-Page into the NAND type flash memory15mounted therein by using the two-Page.

As mentioned above, according to the memory device, and its access method and memory system regarding this embodiment, at least the following (1) to (4) effects are obtained.

(1) Convenience can be improved.

As described above, the memory device11transmits the device ID25and makes the host device12recognize that the memory device11is an accessible device (known device). Subsequently, the host device12accesses the memory device11in the Pure NAND mode26-1owned thereby (step SM2). Further, the memory device11can transfer the LBA NAND device driver17-2driving the LBA NAND mode26-2via the NAND I/F20(step SH2). This is because the same signal pins shown inFIG. 3andFIG. 4are used and the electric interface (signal line definition) are compliant with the Pure NAND mode26-1and the LBA NAND mode26-2. After this, the host device12stores the LBA NAND device driver17-2in its own RAM33(step SH3), transits into the LBA NAND mode26-2, and can start the read-out operations in the LBA NAND mode26-2(step SM4).

Therefore, as long as the memory device11transmits the device ID25and the host device12has the Pure NAND mode26-1, even when the host device12attempts to make access by using the LBA NAND mode26-2which is differently defined (new I/F protocol), it can access the memory device11by means of the differently defined access mode. At this moment, since the memory device11can transfer the LBA NAND device driver17-2driving the differently defined LBA NAND mode26-2, the host device12has no need to change its own firmware. Like this, the memory device11can be accessed in the desired and differently defined access mode and improve the convenience without having to change the firmware of the host device12.

In general, the device driver for an optimal combination between a memory device and a host device is determined with the property of the memory device. As mentioned above, the memory device11regarding the present embodiment can transfer the device driver17-2to be selected by the memory device11to the host device12(Step SH2). Therefore, the host device12can load the optimal device driver17-2selected on the basis of the property of the memory device11.

Like this manner, the memory device11is advantageous in terms of a configuration in which an optimum combination of the device drivers17-2can be established with the optimum combination between the device drivers17-2of the memory device11and the host device12selected and transferred.

(3) The host device12can access even for a not foreseen and differently defined access mode.

Like the first embodiment, even if the host device12has been designed in a specification in which the host device12has originally assumed only the Pure NAND mode26-1as the access mode for the NAND flash memory15, the aforementioned access mode transitional operation enables mode transition to other access mode (for example, LBA NAND mode26-2).

Therefore, the host device12can access the differently defined access mode unexpected by the host device12to actually drive.

(4) The controller16can be easily configured.

As described above, in the first embodiment, in conducting the read-out operations in the Pure NAND mode26-1(step SM2), the controller16is configured to read out the preset data in prescribed order (Data0, Data1, etc.) without referring to the addresses issued from the host device12.

Like this manner, the controller16does not read-out the data the order of which is determined in advance by the host device12faithfully with so far as reference to the addresses. Therefore, the first embodiment is advantageous in terms of enabling a simple configuration of the controller16by reading out the preset data in the prescribed order without referring to the addresses. Even if the write-in operations are conducted in the Pure NAND mode26-1, the similar effects above mentioned will be obtained as long as the operations are conducted without referring to the addresses.

Furthermore, it is also possible to employ embodiments to which modifications such as a (variation 1) to a (variation 6) are applied if necessary. According to the memory device, its access method, and memory system regarding the following (variation 1) to (variation 6), at least the aforementioned (1) to (4) effects are obtained.

(Version 1) A memory device that is powered by a plurality of access modes, namely, one access mode among them is an access mode for a NAND type flash memory, and although other access modes are based on electric interfaces, they are differently defined access modes.

For instance, as shown inFIG. 12, the memory device11employing the Pure NAND access mode26-1, and preparing the Pure NAND access mode26-1and other plurality of access modes based on the electric interface is a possible approach. In such case, even when the differently defined access mode (access mode2, access mode3, etc.) are applied, the memory device11can access the host device12without having to change the firmware of the host device12.

Like such manner, the embodiment having described the access modes by taking the Pure NAND mode26-1and LBA NAND mode26-2as an example, the access modes are not limited to the example, the version 1 may applicable to a memory device further employing a plurality of access modes. That is, the variation 1 is applicable to a memory device having a first access mode accessing a certain memory device and having other plurality of access modes based on the first access mode and the electric interface.

With the foregoing configuration, the variation 1 is advantageous in terms that the use of other plurality of access modes becomes possible without having to change the hardware of the CPU30in the host device12.

(Variation 2) LBA NAND mode26-2is made possible to accept access in a logical sector access hierarchy.

Making the LBA NAND mode26-2possible to accept the access in the logical sector access hierarchy poses an advantage in terms of the simplicity of the configuration of the device driver17-2driving the LBA NAND access mode26-2installed in the firmware of the host device12.

Further, access becoming possible in a abstracted hierarchy regardless of the property of the memory device mounted on the memory device11, for instance, there is a merit enabling the same device driver17-2to make access in spite of the property of the memory device such as a NAND type flash memory15.

(Variation 3) LBA NAND mode26-2is made possible to accept access in a hierarchy of a file system (name of file).

A modification as mentioned above can make the configuration of the device driver17-2driving the LBA NAND mode26-2simple. Moreover, because of the same reason as that of the variation 2, the variation 3 has a merit in enabling accessing through the same device driver17-2despite the property of the memory device in the memory device11.

(Variation 4) A memory device provided with a plurality of access modes, one access mode among of them is an access mode of a NAND type flash memory, and other access modes are differently defined access modes, but not based on any electric interface.

Such configuration becomes available through a manner that the memory device11newly wires a CPU bus, etc., to access the host device12other than the NAND I/F20. Such configuration is applicable in case of need.

(Variation 5) In performing read-out operations in the Pure NAND mode26-1(Step SM2), the memory device11reads out/writes in by referring to the addresses issued from the host device12.

As depicted inFIG. 8, in the first embodiment, in the reading out operations through the Pure NAND mode26-1(Step SM2), the memory device11does not read out with reference to the addresses issued from the host device12. However, with read-out by referring to the addresses insured from the host device12, the memory device11can match more faithfully to the access mode of the NAND type flash memory, and it is advantageous in terms of expansion of the compatibility with the host device12.

Moreover, in conducting the write-in operations, even when the memory device11performs the write-in operations with reference to the addresses issued from the host device12, the same effect is obtained. Because the compatibility with a host device having a wider rage can be achieved together with the write-in property by further faithfully coordinating with the access mode of the NAND type flash memory.

(Variation 6) A data quantity of data43-0, etc., readable in the Pure NAND mode26-1is limited to an extremely small part of the data quantity in the memory device11.

In many cases, the firmware data quantity requires only an extremely limited memory capacity. Therefore, when only the limited memory capacity is required, with the data quantity of the read out data43-0, etc., inFIG. 8limited, the variation 6 is advantageous in terms of the possibility of making the configuration of the memory device11simple.

In the aforementioned description, the memory device11having described by including a semiconductor package of the TSOP package, etc., as one example, the present invention is not limited to this, for instance, it is applicable to a memory card and the like.

The memory device mounted on the memory device11is not limited to the NAND type flash memory shown in the embodiment, other memory devices such as a ferroelectric random access memory (FeRAM) and a magnetic random access memory (MRAM) are similarly applicable.

Further, the embodiment having described by taking the case in which the device driver of the host device12is loaded from the memory device of the memory device11as one example, the present invention is not limited to such case.