Switch-driving circuit and DAC using the same

A switch-driving circuit and a Digital-to-Analog Converter (DAC) using the switch-driving circuit are provided. The switch-driving circuit includes a main cell and a reference cell. The main cell includes a current source and a resistance-control component electronically connected to the current source. The reference cell is coupled to the current source and the resistance-control component, and includes a first loop, the first loop is configured to track a target reference voltage so as to provide at least one first control voltage to control a resistance change of the resistance-control component. The reference cell and the main cell are implemented by MOS transistors in place of capacitors which occupy an increased circuit area, rendering reduced circuit area for the switch-driving circuit, and decreasing manufacturing costs. Further, the switch-driving circuit outputs a voltage signal with reduced noise, increasing the performance of the Digital-to-Analog Converter.

CROSS REFERENCE TO RELATED APPLICATIONS

This application claims priority of China Patent Application No. 201210166673.5, filed on May 25, 2012, and the entirety of which is incorporated by reference herein.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present disclosure relates to driving circuitries, and in particular to a switch-driving circuit and DAC employing the switch-driving circuit.

2. Description of the Related Art

High-Definition Television (HDTV) and Blu-ray Disc (BD) players have gained immense popularity in the daily life of consumers recently. The HDTV and BD players both employ high-prevision and high-speed Digital-to-Analog Converters (DAC) for reconstructing high-quality images or video information.

A switch-driving circuit plays an important part in the DAC. The switch-driving circuit typically comprises a Low Dropout Regulator (LDO) and a core part for the switch-driving circuit. The LDO is employed to provide a stable voltage supply signal VDD2 to the core part for the switch-driving circuit. Nevertheless, since the DAC is operated by digital signals switching on and off to control signal processing, the voltage supply signal VDD2 may be affected by switch noise owned to the signal switching processes, which can affect the performance of the DAC.

In the conventional DAC, the LDO in the switch-driving circuit typically adopts a large capacitor component to suppress the noise. Due to the large area occupied by the capacitor component in the switch-driving circuit, the switch-driving circuit requires an increased circuit area, leading to an increased manufacturing cost for the DAC.

BRIEF SUMMARY OF THE INVENTION

An embodiment of a switch-driving circuit is described, comprising a main cell and a reference cell. The main cell comprises a current source and a resistance-control component interconnected with the current source. The reference cell is coupled to the current source and the resistance-control component and includes a first loop. The first loop is configured to track a target reference voltage so as to provide a first control voltage to control the resistance of the resistance-control component.

Another embodiment of a Digital-to-Analog Converter is provided, comprising a decoder and a switch-driving circuit connected thereto. The switch-driving circuit includes: a main cell, comprising a current source and a resistance-control component electronically connected to the current source; and a reference cell, coupled to the current source and the resistance-control component, comprising a loop configured to track a target reference voltage so as to provide at least one first control voltage to control a resistance change of the resistance-control component.

DETAILED DESCRIPTION OF THE INVENTION

In the specification and subsequent applications, persons with ordinary skill in the art will understand that certain terminology is adopted for certain devices and components, and hardware manufacturers may adopt a different nomenclature to refer to the same devices and components. The scope of the invention is not limited by the names of the devices and components, but limited by the functions of the devices and components that define those devices and components. The phrase “comprise” in the specification and the claims is an open-ended term, encompassing all the elements listed, but may also include additional, unnamed elements. The phrase “couple” includes any directly and indirectly electrically connected means. When a first device is coupled to a second device, it can be understood as meaning that the first device can be connected to the second device directly, or through other means or devices connected to the second device.

A switch-driving circuit is provided. The switch-driving circuit can be adopted in a Digital-to-Analog Converter (DAC). Details for the switch-driving circuit are provided as follows.

FIG. 1is a block diagram of a DAC10according to an embodiment of the invention.FIG. 2is a circuit schematic of the DAC10according to an embodiment of the invention. The DAC10includes a decoder11, a switch-driving circuit12, and a power supply13. The decoder11is coupled to the switch-driving circuit12, and the switch-driving circuit12is coupled to the power supply13. The switch-driving circuit12includes a reference cell121and one or more main cells122.

As shown inFIG. 2, the switch-driving circuit12includes n number of main cells122, and the decoder11can output a plurality of digital signals D1-Dn to the n number of main cells122. The power supply14includes n number of constant current source cells131. The number of constant current source cells131is equal to that of the main cells122.

In the present embodiment, each main cell122can acquire a first control voltage VBP and a second control voltage VBR from the reference cell121. Each main cell122includes two output nodes QP and QN. Particularly, for each main cell122, an output node QP1is coupled to a control node of a control switch K1, and an output node QN1is coupled to a control node of a control switch K2. Output nodes of the corresponding constant current source cells131are respectively coupled to the first nodes of the control switches K1and K2, a second node of the control switch K1is coupled to one end of a resistor R1, the other end of the resistor R1is coupled to the ground, and a second node of the control switch K2is coupled to the ground. The control switch K1is opened (i.e. turned off) when the output node QP1outputs a signal “1”. The control switch K2is closed (i.e. turned on) when the output node QN1outputs a signal “0”, rendering the output node DACO of the DAC10to output a signal “0”. The control switch K1is closed when the output node QP1outputs a signal “0”. The control switch K2is opened when the output node QN1outputs a signal “1”, causing the output node DACO of the DAC10to output a non-zero voltage. Accordingly, the DAC10in the embodiment can control the switch-driving circuit12to generate the switch driving signals via the decoder11, thereby controlling the output voltage, such as the voltage at the output node DACO, of the power supply13, converting a digital signal output from the decoder11into an analog signal.

Please refer toFIG. 3, showing a circuit schematic of the switch-driving circuit12inFIG. 1according to an embodiment of the invention. The main cell122in the embodiment includes a current source1221, a latch switch1222, and a resistance-control component1223connected in serial. The reference cell121is coupled to the current source1221and the resistance-control component1223. The reference cell121is configured to provide at least one control voltage to the current source1221and the resistance-control component1223to control the resistance change of the resistance-control component1223. In the embodiment, the reference cell121can provide the first control voltage VBP to the current source1221, and the second control voltage VBR to the resistance-control component1223.

The reference cell121includes an operational amplifier1211and a loop1212. A target reference voltage VREF is input into a first input node of the operational amplifier1211. The loop1212is configured to adjust the output voltage of the operational amplifier1121. One end of the loop1212is coupled to an output node of the operational amplifier1211, and the other end of the loop1212is coupled to a second input node1214of the operational amplifier1221, thereby tracking the target reference voltage VREF by the voltage fed back to the second input node1214of the operational amplifier1211.

FIG. 4is a circuit schematic of the main cell122inFIG. 3according to an embodiment of the invention. The current of the current source1221and the output current of the reference cell121are in a mirrored relationship. The current source1221includes a PMOS transistor M1. The source of the PMOS transistor M1is coupled to a first reference voltage VDD, the gate of the PMOS transistor M1is coupled to the first control voltage VBP output from the reference cell121, and the drain of the PMOS transistor M1is coupled to the latch switch1222. The first control voltage VBP controls the current to pass through the PMOS transistor M1.

In the embodiment, the latch switch1222includes a PMOS transistor M2, a PMOS transistor M3, an NMOS transistor M4, an NMOS transistor M5, a first inverter N1, and a second inverter N2. The source of the PMOS transistor M2and that of the PMOS transistor M3are both coupled to the drain of the PMOS transistor M1. The drain of the PMOS transistor M2is coupled to the gate of the PMOS transistor M3. The drain of the PMOS transistor M2and the drain of the PMOS transistor M3are both coupled to the resistance-control component1223. The drain of the NMOS transistor M4is coupled to the drain of the PMOS transistor M2. The drain of the NMOS transistor M5is coupled to the drain of the PMOS transistor M3. The gate of the NMOS transistor M4is coupled to the output node of the second inverter N2. The gate of the NMOS transistor M5is coupled to the output node of the first inverter N1. The source of the NMOS transistor M4and the source of the NMOS transistor M5are coupled to the ground. The input node of the first inverter N1and the output node D1(seeFIG. 1) of the decoder11are coupled, and the output node of the first inverter N1and the input node of the second inverter N2are coupled.

In other embodiments, the first and second inverters N1and N2may be replaced by other implementations by persons having ordinary skill in the art. For example, a single inverter with an input node coupled to the output node D1of the decoder11, an output node coupled to the gate of the NMOS transistor M4, and the input node also coupled to the gate of the NMOS transistor M5.

In the present embodiment, the resistance-control component1223includes an NMOS transistor M6and an NMOS transistor M7. The drain of the NMOS transistor M6is coupled to the drain of the PMOS transistor M2. The drain of the NMOS transistor M7is coupled to the drain of the PMOS transistor M3. The gate of the NMOS transistor M6and the gate of the NMOS transistor M7are coupled to the second control voltage VBR output from the reference cell121. The source of the NMOS transistor M6and the source of the NMOS transistor M7are coupled the second reference voltage VSS. The second control voltage VBR is used to control an equivalent resistance of the NMOS transistor M6and NMOS transistor M7.

The operation principle of the main cell122is detailed as follows.

When the output node D1of the decoder11outputs a voltage level as “0”, the first inverter N1can output a signal “1” at the output node and the second inverter N2can output a signal “0” at the output node. This renders the PMOS transistor M3and the NMOS transistor M4both opened, the PMOS transistor M2and the NMOS transistor M5both closed, and the main cell122outputting a signal “1” at the output node QN and a signal “0” at the output node QP.

When the output node D1of the decoder11outputs a voltage level as “1”, the first inverter N1can output a signal “0” at the output node and the second inverter N2can output a signal “1” at the output node. This renders the PMOS transistor M3and the NMOS transistor M4both closed, the PMOS transistor M2and the NMOS transistor M5both opened, and the main cell122outputting a signal “0” at the output node QN and a signal “0” at the output node QP.

Herein, the first node of the PMOS transistor is defined to be the source, the second node the PMOS transistor is defined to be the gate, and the third node the PMOS transistor is defined to be the drain. Furthermore, the first node of the NMOS transistor is defined to be the drain thereof, the second node the NMOS transistor is defined to be the gate thereof, and the third node the NMOS transistor is defined to be the source thereof.

FIG. 5illustrates a circuit schematic of the switch-driving circuit inFIG. 3according to an embodiment of the invention. As shown inFIG. 5, the loop1212is a first negative loop, including a PMOS transistor M8, a PMOS transistor M9, and an NMOS transistor M10. The source of the PMOS transistor M8is coupled to the first reference voltage VDD, the gate of the PMOS transistor M8is coupled to the output node of the operational amplifier1211, and the drain of the PMOS transistor M8is coupled to the source of the PMOS transistor M9. The drain of the PMOS transistor M9is coupled to the second input node1214of the operational amplifier1211, the gate of the PMOS transistor M9is coupled to the drain of the NMOS transistor M10, and the gate of the NMOS transistor M10is coupled to a third reference voltage VCC. The source of the NMOS transistor M10is coupled to the ground, and the output node of the operational amplifier1211outputs the first control voltage VBP.

In the embodiment, the reference cell121includes an NMOS transistor M11. The drain of the NMOS transistor M11is coupled to the drain of the PMOS transistor M9, the gate of the NMOS transistor M11is coupled to a fourth reference voltage V4, and the source of the NMOS transistor M11is coupled to the second control voltage VSS. The second control voltage VBR is obtained according to the fourth reference voltage V4.

Further, the reference cell121also includes a testing network1213which comprises a PMOS transistor M15, a PMOS transistor M16, an NMOS transistor M17, and an NMOS transistor M18. The source of the PMOS transistor M15is coupled to the first reference voltage VDD, the gate of the PMOS transistor M15is coupled to the output node of the operational amplifier1211, and the drain of the PMOS transistor M15is coupled to the source of the PMOS transistor M16. The gate of the PMOS transistor M16is coupled to the drain of the NMOS transistor M17, the gate of the NMOS transistor M17is coupled to the third reference voltage VCC, and the source of the NMOS transistor M17is coupled to the ground. The drain of the NMOS transistor M18is coupled to the drain of the PMOS transistor M16, the gate of the NMOS transistor M18is coupled to the fourth reference voltage V4, and the source of the NMOS transistor M18is coupled to the second reference voltage VSS.

The switch-driving circuit in the embodiment also includes the main cell122. The description therefore can be found in the preceding section and will not be repeated here. The gate of the PMOS transistor M1in the main cell122is coupled to the output node of the operational amplifier1211to obtain the first control voltage VBP. The gate of the NMOS transistor M6and the gate of the NMOS transistor M7are coupled to the fourth reference voltage V4to obtain the second control voltage VBR.

The operation principle of the reference cell121and the first negative loop are detailed as follows.

When the third reference voltage VCC is a predetermined voltage, such as when the voltage VCC is 1.2V, the NMOS transistor M10and the NMOS transistor M17are turned on, and the PMOS transistor M8, the PMOS transistor M9, and the NMOS transistor M11are also turned on. It should be understood that the predetermined value of the voltage VCC may vary with different applications and implementations. When the voltage at the second input node1214of the operational amplifier1211increases, the first control voltage VBP output from the output node of the operational amplifier1211increases accordingly, thereby decreasing the voltage at the gate of the PMOS transistor M8and the current passing through the PMOS transistor M8, the PMOS transistor M9, and the NMOS transistor M11. As a result, the voltage of the NMOS transistor M11is declined, thereby reducing the voltage at the second input node1214of the operational amplifier1211. This traces the target reference voltage VREF at the second input node1214of the operational amplifier1211, and in turn, adjusts the first control voltage VBP output by the operational amplifier1211. The output voltage VDD2 at the output node of the testing network1213can promptly detect the voltage output by the switch-driving circuit. The preferred value of the voltage VDD2 equals the target reference voltage VREF.

The reference cell121and the main cell122in the switch-driving circuit in the embodiments are realized via the MOS transistors, obviating the need to use capacitor components, which occupy an increased area on the integrated circuit, and thereby reducing the circuit area of the switch-driving circuit. Further, since the DAC10includes a number of main cells122, the reduced circuit area for each main cell122can amount to a considerable reduction in the circuit area of the DAC10, increasing the integrity of the circuit, reducing the occupied area of the integrated circuit, and thereby decreasing the manufacturing costs.

FIG. 6depicts a circuit schematic of the switch-driving circuit according to another embodiment of the invention, in which the loop1212is a second negative loop which includes an NMOS transistor M11, an NMOS transistor M12, an NMOS transistor M13, a PMOS transistor M14, and a resistor R. The source of the PMOS transistor M14is coupled to the first reference voltage VDD, the gate of the PMOS transistor M14is coupled to the output node of the operational amplifier1211, and the drain of the PMOS transistor M14is coupled to the drain of the NMOS transistor M13. The gate of the NMOS transistor M13is coupled to the gate of the NMOS transistor M12, and the drain and the gate of the NMOS transistor M13are coupled. The source of the NMOS transistor M13, the source of the NMOS transistor M12, and the source of the NMOS transistor M11are coupled to the second reference voltage VSS. The drain of the NMOS transistor M12is coupled to the gate of the NMOS transistor M11, and the drain of the NMOS transistor M11is coupled to the second input node1214of the operational amplifier1211. One end of the resistor R is coupled to the first reference voltage VDD, and the other end of the resistor R is coupled to the drain of the NMOS transistor M12. The node connected to the drain of the NMOS transistor M12and the resistor R outputs the second control voltage VBR.

In the embodiment, the reference cell121can further include: a PMOS transistor M8, a PMOS transistor M9, and an NMOS transistor M10. The source of the PMOS transistor M8is coupled to the first reference voltage VDD. The gate of the PMOS transistor M8is coupled to a fifth reference voltage V5, and the drain of the PMOS transistor M8is coupled to the source of the PMOS transistor M9. The gate of the PMOS transistor M9is coupled to the drain of the NMOS transistor M10. The drain of the PMOS transistor M9is coupled to the second input node1214of the operational amplifier1211. The gate of the NMOS transistor M10is coupled to the third reference voltage VCC, and the source of the NMOS transistor M10is coupled to the ground. The first control voltage VBP is acquired from the fifth reference voltage V5.

Moreover, the reference121can include the testing network1213, which is identical to the testing network inFIG. 5, and details therefore can be referenced in the preceding section and are not repeated here. The gate of the PMOS transistor M15is coupled to the fifth reference voltage V5, and the gate of the NMOS transistor M18is coupled to the gate of the NMOS transistor M11.

The switch-driving circuit can further include the main cell122, which is identical to those main cells described in the preceding sections, and therefore the details are omitted here for brevity. Herein, the gate of the PMOS transistor M1is coupled to the fifth reference voltage V5to obtain the first control voltage VBP. The gate of the NMOS transistor M6, the gate of the NMOS transistor M7, and the gate of the NMOS transistor M11are coupled together to obtain the second control voltage VBR.

The operation principle of the second negative loop is detailed as follows.

When the first control voltage VBP output from the operational amplifier1211increases, the currents through the PMOS transistor M14, the NMOS transistor M13, and the NMOS transistor M12decrease accordingly, resulting in an decreased voltage on the resistor R and the second control voltage VBR increasing. This leads to a reduced voltage at the second input node1214of the operational amplifier1211and enable the voltage at the second input node1214of the operational amplifier1211to track the target reference voltage VREF, thereby adjusting the first control voltage VBP output at the output node of the operational amplifier1211. The output node of the testing network1213can output the voltage VDD2, promptly detecting the output voltage of the switch-driving circuit. The preferred value for the voltage VDD2 is equal to the target reference voltage VREF.

As shown inFIG. 7, which depicts a circuit schematic of the switch-driving circuit according to another embodiment of the invention, the loop1212in this embodiment includes the first negative loop and the second negative loop mentioned above. The first negative loop and the second negative loop here form two loops to lock the voltage at the second input node1214of the operational amplifier1211to the target reference voltage VREF.

In the embodiment, the first negative feedback circuit includes a PMOS transistor M8, a PMOS transistor M9, and an NMOS transistor M10. The source of the PMOS transistor M8is coupled to the first reference voltage VDD, the gate of the PMOS transistor M8is coupled to the output node of the operational amplifier1211, and the drain of the PMOS transistor M8is coupled to the source of the PMOS transistor M9. The drain of the PMOS transistor M9is coupled to the second input node1214of the operational amplifier1211, and the gate of the PMOS transistor M9is coupled to the drain of the NMOS transistor M10. The gate of the NMOS transistor M10is coupled to the third reference voltage VCC, and the source of the NMOS transistor M10is coupled to the ground. The output node of the operational amplifier1211outputs the first control voltage VBP.

In the embodiment, the second negative loop includes an NMOS transistor M11, an NMOS transistor M12, an NMOS transistor M13, a PMOS transistor M14, and a resistor R. The source of the PMOS transistor M14is coupled to the first reference voltage VDD, the gate of the PMOS transistor M14is coupled to the output node of the operational amplifier1211, and the drain of the PMOS transistor M14is coupled to the drain of the NMOS transistor M13. The gate of the NMOS transistor M13is coupled to the gate of the NMOS transistor M12, the drain and the gate of the NMOS transistor M13are coupled together. The source of the NMOS transistor M13, the source of the NMOS transistor M12, and the source of the NMOS transistor M11are coupled to the second reference voltage VSS. The drain of the NMOS transistor M12is coupled to the gate of the NMOS transistor M11, and the drain of the NMOS transistor M11is coupled to the second input node1214of the operational amplifier1211. One end of the resistor R is coupled to the first reference voltage VDD, and the other end of the resistor R is coupled to the drain of the NMOS transistor M12. The node connected to the drain of the NMOS transistor M12and the resistor R outputs the second control voltage VBR.

Further, the reference121can include a testing network1213identical to the testing network inFIG. 5. Details can therefore be found referenced in the preceding section and shall not be repeated here. Herein, the gate of the PMOS transistor M15is coupled to the output node of the operational amplifier1211, and the gate of the NMOS transistor M18is coupled to the gate of the NMOS transistor M11.

The switch-driving circuit can further include a main cell122identical to those main cells described in the preceding sections, and for the sake of brevity, the details thereof shall not be repeated here. Herein, the gate of the PMOS transistor M1is coupled to the output node of the operational amplifier1211to obtain the first control voltage VBP. The gate of the NMOS transistor M6, the gate of the NMOS transistor M7, and the gate of the NMOS transistor M11are coupled together to obtain the second control voltage VBR. If the voltage at the second input node1214of the operational amplifier1211is higher than the target reference voltage VREF, the first control voltage VBP goes high and the current through the PMOS transistor M14and the NMOS transistor M11is decreased. Therefore the voltage at the second input node1214is pulled back. Meanwhile, the first control voltage VBP going high also reduces the current in the NMOS transistor M13. So current mirror consist of the NMOS transistor M13and the NMOS transistor M12outputs the reduced current leading to the decreasing of the second control voltage VBR of the NMOS transistor M11. Herein, the NMOS transistor M11acts as an active resistor. This also will pull the voltage at the second input node1214to a lower voltage level.

In comparison to the embodiments inFIG. 5andFIG. 6, the embodiment inFIG. 7is distinct at the switch-driving circuit which includes two negative loops, since a value of power supply rejection (PSR) of an operational amplifier (OP) for the switch-driving circuit ofFIG. 7is greater than that of the switch-driving circuits inFIG. 5andFIG. 6. In detail, the PSR for the switch-driving circuit ofFIG. 7reflects the power noise immunization ability of the switch-driving circuit, and can be calculated by the following formula:

PSR=vdd⁢⁢2vdd=1PSRROP·(Av⁢⁢1+Av⁢⁢2)⁢Av,OP(Av⁢⁢1+Av⁢⁢2)⁢Av,OP+1.
Wherein, PSRROPrepresents the power supply rejection ratio of the OP, Av,oprepresents the DC gain of the OP, Av1represents the DC gain of the first negative loop, and Av2represents the DC gain of the second negative loop.

In the other embodiments of the invention, persons with ordinary skill in the art may utilize the NMOS transistors to replace one or more of the PMOS transistors and vise versa.

The switch-driving circuit in the embodiments employs MOS transistors to realize the reference cell and the main cell, preventing from using capacitor components which occupy an increased circuit area, thereby reducing the circuit area of the switch-driving circuit. Further, since the DAC10includes a number of main cells122, the reduced circuit area for each main cell122can amount to a considerable reduction in the circuit area of the DAC10, increasing the integrity of the circuit, reducing the occupied area of the integrated circuit, and thereby decreasing manufacturing costs for the DAC10. Contrary to the operation mechanism of using the LDO to provide the operation voltage VDD2, by applying current through the resistance-control component and providing the current source through the reference cell and the control voltage signal through the resistance-control component, the switch-driving circuits in the embodiments implement an operation mechanism which generates the required operation voltage, rendering the voltage signals output by the switch-driving circuit purer and less noisy, and increasing the performance of the DAC10.

The various illustrative logical blocks, modules and circuits described in connection with the present disclosure may be implemented or performed with a general purpose processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array signal (FPGA) or any other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general purpose processor may be a microprocessor, but in the alternative, the processor may be any commercially available processor, controller, microcontroller, or state machine.

The operations and functions of the various logical blocks, modules, and circuits described herein may be implemented in circuit hardware or embedded software codes that can be accessed and executed by a processor.