Method and system for enhancement of power amplifier efficiency through controlled variation of gain in a power Amplifier Driver

Aspects of a method and system for enhancement of power amplifier (PA) efficiency through controlled variation of gain in a power amplifier driver are presented. Aspects of the system may comprise an envelope detector that enables detection of an amplitude of an analog input signal. The envelope detector may enable computation of a first gain value based on the detection. A second gain value may be computed based on the first gain value. A PA may enable generation of an analog output signal based on the analog input signal, the first gain value and the second gain value.

FIELD OF THE INVENTION

Certain embodiments of the invention relate to wireless communications. More specifically, certain embodiments of the invention relate to a method and system for enhancement of power amplifier efficiency through controlled variation of gain in a power amplifier driver.

BACKGROUND OF THE INVENTION

A power amplifier (PA) circuit may be characterized by its mode, or “class” of operation. Exemplary classes include Class A, Class AB, and Class B. In Class A operation, a PA may operate in a conducting, or ON, state during 100% of the cycle, or the entire cycle, of the input signal. In Class A operation, the output signal from the PA is typically a scaled version of the input signal, where the scaling factor is a function of the gain associated with the PA circuit. However, for Class A operation, the PA is typically in a conducting state even when there is no input signal. Furthermore, even when the PA is amplifying an input signal, the efficiency of the PA may not exceed 50%.

In Class B operation, a PA may operate in a conducting state during 50%, or half, of the cycle of the input signal. This may result in large amounts of distortion of the input signal in the output signal. The higher efficiency of the Class B PA results from the PA being in a non-conducting, or OFF, state half of the time.

In Class AB operation, a PA may operate in a conducting state for greater than 50%, but less than 100%, of the cycle of the input signal. In Class AB operation, the PA may be more efficient than in Class A operation, but less efficient than in Class B operation. Furthermore, in Class AB operation, the PA may produce more distortion than in Class A operation, but less than in Class B operation.

The amount of DC power required from a DC power supply may increase with increasing input signal amplitudes to the PA circuit. Large peak input signal amplitude to average input signal amplitude may result in the PA circuit operating with low efficiency.

BRIEF SUMMARY OF THE INVENTION

A method and system for enhancement of power amplifier efficiency through controlled variation of gain in a power amplifier driver, substantially as shown in and/or described in connection with at least one of the figures, as set forth more completely in the claims.

DETAILED DESCRIPTION OF THE INVENTION

Certain embodiments of the invention may be found in a method and system for enhancement of power amplifier efficiency through controlled variation of gain in a power amplifier driver. Various embodiments of the invention may enable the amplitude of input signals to a PA circuit to be controlled within an amplitude range, which enables the PA to operate in an efficient manner. Efficiency, η, for a PA circuit may be defined as in the following equation:

η=PRFPDC[1]
where PRFrefers to the power level for an RF signal output by a PA circuit in an RF transmitter, and PDCrefers to delivered power from a DC power supply source (such as a battery).

When the peak input signal level is large compared to the average input signal level, or high peak to average ratio, the PA circuit may be biased to accommodate the peak input signal level, PINMAX. The value of PDCmay be set to enable generation of an RF signal output level from the PA circuit, PRFMAX, when the corresponding input signal level is PINMAX. Thus, efficiency, η, may be highest for a given value PDCwhen the RF signal output level from the PA circuit is PRFMAX. However, for high peak to average ratios, the input signal level is typically less than PINMAXfor a substantial portion of the time that the PA circuit is operating. Therefore, the average RF signal output level, PRFAVG, may be significantly lower than PRFMAX. Consequently, the need to support high peak to average ratios may result in low efficiency for the PA circuit.

In various embodiments of the invention, an envelope detector circuit may detect the amplitude of an input signal to a power amplifier driver (PAD) circuit, and dynamically adjust the gain of the PA and PAD circuits to maintain a constant input signal level at the PA. The input signal level may be selected to enable efficient operation of the PA. For each adjustment of the PA gain, a corresponding adjustment to PAD gain may be made such that the total gain through the PA and PAD remains constant.

FIG. 1is a block diagram illustrating and exemplary mobile terminal, which may be utilized in connection with an embodiment of the invention. Referring toFIG. 1, there is shown mobile terminal120that may comprise an RF receiver123a, an RF transmitter123b, a digital baseband processor129, a processor125, and a memory127. In some embodiments of the invention, the RF receiver123a, and RF transmitter123bmay be integrated into an RF transceiver122, for example. A single transmit and receive antenna121may be communicatively coupled to the RF receiver123aand the RF transmitter123b. A switch124, or other device having switching capabilities may be coupled between the RF receiver123aand RF transmitter123b, and may be utilized to switch the antenna121between transmit and receive functions.

The RF receiver123amay comprise suitable logic, circuitry, and/or code that may enable processing of received RF signals. The RF receiver123amay enable receiving RF signals in frequency bands utilized by various wireless communication systems, such as GSM and/or CDMA, for example.

The digital baseband processor129may comprise suitable logic, circuitry, and/or code that may enable processing and/or handling of baseband signals. In this regard, the digital baseband processor129may process or handle signals received from the RF receiver123aand/or signals to be transferred to the RF transmitter123bfor transmission via a wireless communication medium. The digital baseband processor129may also provide control and/or feedback information to the RF receiver123aand to the RF transmitter123b, based on information from the processed signals. The digital baseband processor129may communicate information and/or data from the processed signals to the processor125and/or to the memory127. Moreover, the digital baseband processor129may receive information from the processor125and/or to the memory127, which may be processed and transferred to the RF transmitter123bfor transmission via the wireless communication medium.

The RF transmitter123bmay comprise suitable logic, circuitry, and/or code that may enable processing of RF signals for transmission. The RF transmitter123bmay enable transmission of RF signals in frequency bands utilized by various wireless communications systems, such as GSM and/or CDMA, for example.

The processor125may comprise suitable logic, circuitry, and/or code that may enable control and/or data processing operations for the mobile terminal120. The processor125may be utilized to control at least a portion of the RF receiver123a, the RF transmitter123b, the digital baseband processor129, and/or the memory127. In this regard, the processor125may generate at least one signal for controlling operations within the mobile terminal120.

The memory127may comprise suitable logic, circuitry, and/or code that may enable storage of data and/or other information utilized by the mobile terminal120. For example, the memory127may be utilized for storing processed data generated by the digital baseband processor129and/or the processor125. The memory127may also be utilized to store information, such as configuration information, which may be utilized to control the operation of at least one block in the mobile terminal120. For example, the memory127may comprise information necessary to configure the RF receiver123ato enable receiving RF signals in the appropriate frequency band.

FIG. 2is an exemplary block diagram illustrating an RF transmitter utilizing power amplifier driver gain variation, in accordance with an embodiment of the invention. Referring toFIG. 2, there is shown an RF transmitter123b, an envelope detector252, and a baseband processor240. The RF transmitter123bmay comprise a power amplifier (PA)214, a power amplifier driver (PAD)212, an RF programmable gain amplifier (RFPGA)210, a transmitter In-phase signal (I) mixer208a, a transmitter Quadrature-phase signal (Q) mixer208b, an I transconductance amplifier (gm)206a, a Q gm206b, an I low pass filter (LPF)204a, a Q LPF204b, an I digital to analog converter (I DAC)202a, and a Q DAC202b.

The PA214may comprise suitable logic, circuitry, and/or code that may enable amplification of input signals to generate a transmitted signal of sufficient signal power (as measured by dBm, for example) for transmission via a wireless communication medium. In an exemplary embodiment of the invention, the PA214may receive a differential input signal, labeled PAininFIG. 2, and output a differential output signal, labeled RFoutinFIG. 2. In addition, the PA214may receive a control signal, labeled PA Gain Control inFIG. 2, which may enable the PA214to dynamically select a gain level, referred to as g3(t). The gain level may vary with time in response to the PA Gain Control signal. The gain level may determine an amplification level by which the input signal PAinmay be amplified to generate the output signal RFout.

The PAD212may comprise suitable logic, circuitry, and/or code that may enable amplification of input signals to generate an amplified output signal. The PAD212may be utilized in multistage amplifier systems wherein the output of the PAD212may be an input to a subsequent amplification stage. In an exemplary embodiment of the invention, the PAD212may receive a differential input signal, labeled as PADininFIG. 2, and output a differential output signal, labeled PAininFIG. 2. In addition, the PAD212may receive a control signal, labeled PAD Gain Control inFIG. 2, which may enable the PAD212to dynamically select a gain level, referred to as g2(t). The gain level may vary in time in response to the PAD Gain Control signal. The gain level may determine an amplification level by which the input signal PADinmay be amplified to generate the output signal RFout.

The RFPGA210may comprise suitable logic, circuitry, and/or code that may enable amplification of input signals to generate an amplified output signal, wherein the amount of amplification, as measured in dB for example, may be determined based on an input control signal. In various embodiments of the invention, the input control signal may comprise binary bits. In an exemplary embodiment of the invention, the RFPGA210may receive a differential input signal and generate a differential output signal, labeled as PADininFIG. 2.

The transmitter I mixer208amay comprise suitable logic, circuitry, and/or code that may enable generation of an RF signal by upconversion of an input signal. The transmitter I mixer208amay utilize an input local oscillator signal labeled as LO208ato upconvert the input signal. The upconverted signal may be an RF signal. The transmitter I mixer208amay produce an RF signal for which the carrier frequency may be equal to the frequency of the signal LO208a. In an exemplary embodiment of the invention, the transmitter I mixer208amay receive a differential input signal and generate a differential output signal.

The transmitter Q mixer208bmay be substantially similar to the transmitter I mixer208a. The transmitter Q mixer208bmay utilize an input local oscillator signal labeled as LO208bin quadrature (inFIG. 2) to upconvert the input signal.

The I gm206amay comprise suitable, logic, circuitry, and/or code that may enable generation of an output current, the amplitude of which may be proportional to an amplitude of an input voltage, wherein the measure of proportionality may be determined based on the transconductance parameter, gmI, associated with the I gm206a. In an exemplary embodiment of the invention, the I gm206amay receive a differential input signal and output a differential output signal.

The Q gm206bmay be substantially similar to the I gm206a. The transconductance parameter associated with the Q gm206bis gmQ.

The I LPF204amay comprise suitable logic, circuitry, and/or code that may enable selection of a cutoff frequency, wherein the LPF may attenuate the amplitudes of input signal components for which the corresponding frequency is higher than the cutoff frequency, while the amplitudes of input signal components for which the corresponding frequency is less than the cutoff frequency may “pass,” or not be attenuated, or attenuated to a lesser degree than input signal components at frequencies higher than the cutoff frequency. In various embodiments of the invention, the I LPF210amay be implemented as a passive filter, such as one that utilizes resistor, capacitor, and/or inductor elements, or implemented as an active filter, such as one that utilizes an operational amplifier. In an exemplary embodiment of the invention, the I LPF210amay receive a differential input signal and output a differential output signal.

The Q LPF204bmay be substantially similar to the I LPF204a.

The I DAC202amay comprise suitable logic, circuitry, and/or code that may enable conversion of an input digital signal to a corresponding analog representation.

The Q DAC202bmay be substantially similar to the I DAC202a.

The envelope detector252may comprise suitable logic, circuitry and/or code that may enable detection of an amplitude of a time varying input signal, labeled as PADininFIG. 2. Based on the detected amplitude of the input signal, the envelope detector252may enable generation of output signals, labeled as PA Gain Control and PAD Gain Control inFIG. 2.

The baseband processor240may comprise suitable logic, circuitry, and/or code that may enable processing tasks, which correspond to one or more layers in an applicable protocol reference model (PRM). For example, the baseband processor240may perform physical (PHY) layer processing, layer 1 (L1) processing, medium access control (MAC) layer processing, logical link control (LLC) layer processing, layer 2 (L2) processing, and/or higher layer protocol processing. The processing tasks performed by the baseband processor240may be referred to as being within the digital domain. The baseband processor240may also generate control signals. In an exemplary embodiment of the invention, the baseband processor240may generate differential output signals. The differential output signals may be referred to as quadrature baseband signals labeled IBBand QBBinFIG. 2.

In operation, the baseband processor240may generate baseband signals IBBand QBB, comprising a sequence of bits to be transmitted via a wireless communications medium. The baseband processor240may send the IBBsignal to the I DAC202a, and send the QBBsignal to the Q DAC202b. The I DAC202amay generate an analog signal. The Q DAC202bmay similarly generate an analog signal.

The analog signals generated by the I DAC202aand Q DAC202bmay comprise undesirable frequency components. The I LPF204aand Q LPF204bmay attenuate signal amplitudes associated with these undesirable frequency components in signals generated by the I DAC202aand Q DAC202brespectively. The baseband processor240may configure the transmitter I mixer208ato select a frequency for the LO208asignal utilized to upconvert the filtered signal from the I LPF204a. The upconverted signal output from the transmitter I mixer208amay comprise an I component RF signal. The baseband processor240may similarly configure the transmitter Q mixer208bto generate a Q component RF signal from the filtered signal from the Q LPF204b.

The RFPGA210may amplify the I component and Q component RF signals to generate an RF signal, wherein the level of amplification provided by the RFPGA210may be configured based on control signals generated by the baseband processor240. The RFPGA210may generate a differential output signal, PADin. The envelope detector252may receive the PADinsignal and detect the time varying signal amplitude ∥PADin(t)∥. The envelope detector252may generate control signals PA Gain Control and PAD Gain Control based on the detected signal amplitude. The PA Gain Control signal may enable the PA214to dynamically adjust the gain, g3(t), and the PAD Gain Control signal may enable the PAD212to dynamically adjust the gain, g2(t). The envelope detector252may enable dynamic adjustments for the gain g2(t) and the gain g3(t) such that:
c1=g2(t)·g3(t)  [2]
where c1is a numerical constant.

The PAD212may provide a second stage of amplification, g2(t), for the PADinsignal generated by the RFPGA210. The PAD212may dynamically adjust the gain g2(t) in response to the PAD Gain Control signal from the envelope detector252. The PAD212may generate an input signal to the PA214, labeled PAininFIG. 2.

The PA214may provide a third stage of amplification, g3(t), for the PAinsignal generated by the PAD212. The PA214may dynamically adjust the gain g3(t) in response to the PA Gain Control signal from the envelope detector252. The PA214may generate an output signal, labeled RFoutinFIG. 2. The amplified signal from the PA214, RFout, may be transmitted to the wireless communications medium via the antenna121.

In an exemplary embodiment of the invention, an increase in the amplitude ∥PADin(t)∥ may result in a decrease in the gain level g2(t) and a corresponding increase in the gain level g3(t) in accordance with equation [2]. The decrease in the gain level g2(t) may, for example, enable the amplitude ∥PAin(t)∥ to remain constant even when there is an increase in the amplitude ∥PADin(t)∥. The increase in the gain level g3(t) may enable the overall gain level between the signal PADinand the signal RFoutto remain constant at a level c1(as set forth in equation [2] above) even when the respective intermediate gain levels g2(t) and g3(t) are dynamically adjusted. For example, when ∥PADin(t)∥ decreases, the PAD gain g2(t) increases, and the PA gain g3(t) decreases such that ∥PAin(t)∥ remains constant. In various embodiments of the invention, the increase in g2(t) and decrease in g3(t) are in accordance with equation [2]. The value of ∥PAin(t)∥ may be selected to enable the PA214to operate with high efficiency. Thus, in various embodiments of the invention, the peak to average ratio at the PA may be reduced in comparison to systems, which do not dynamically adjust PA gain and/or PAD gain levels.

FIG. 3is a diagram of an exemplary amplifier with programmable gain, in accordance with an embodiment of the invention. Referring toFIG. 3, there is shown an amplifier300. The amplifier300may comprise a plurality of inductors302and304, and a plurality of gain stages310, . . . , and320. The gain stage310may comprise a plurality of transistors312,314,316and318. The gain stage320may comprise a plurality of transistors322,324,326and328.

The plurality of gain stages310, . . . , and320may comprise individually selectable gain stages that may be enabled so as to dynamically increase gain, gA(t), for the amplifier300, or disabled so as to dynamically decrease amplifier300gain gA(t). The gain gA(t) may be a measure of signal amplification between the amplifier300inputs, labeled IN+and IN−inFIG. 3, and the outputs, labeled OUT+and OUT−. Individual gain stages may be selected based on gain control signal, such as the signals labeled PA Gain Control and PAD Gain Control inFIG. 2. The gain stage310may represent a first gain stage in the plurality of gain stages, and the gain stage320may represent a last gain stage in a plurality of n gain stages.

The gain stage310may receive a control signal, labeled Ctls1inFIG. 3, which may be utilized to enable or disable the gain stage310. When enabled, the gain stage310may provide a gs1level of amplification of the differential input signal to transistors316and318, labeled as IN+and IN−respectively inFIG. 3. The first stage gain level, gs1, may contribute to the overall level of gain in the amplifier300, gA(t).

The gain stage320may receive a control signal, labeled CtlsninFIG. 3, which enables or disables the gain stage320. When enabled, the gain stage320may provide a gsnlevel of amplification of the differential input signal to transistors326and328, labeled as IN+and IN−respectively inFIG. 3. The nthstage gain level, gsn, may contribute to the overall level of gain in the amplifier300, gA(t).

The overall level of gain, gA(t), for the amplifier300may be collectively based on the individual stage gains, gsi, for each of the enabled gain stages i.

The amplifier300may be representative of the PA214and/or the PAD212. When representing the PA214, the input signals IN+and IN−may represent the signal labeled PAininFIG. 2, the output signals OUT+and OUT−may represent the signal labeled RFout, and the control signals for the gain stages Ctlsimay represent the signal labeled PA Gain Control. When representing the PAD212, the input signals IN+and IN−may represent the signal labeled PADininFIG. 2, the output signals OUT+and OUT−may represent the signal labeled PAin, and the control signals for the gain stages Ctlsimay represent the signal labeled PAD Gain Control.

FIG. 4is a flow chart illustrating exemplary steps for a method and system for enhancement of power amplifier efficiency through controlled variation of gain in a power amplifier driver, in accordance with an embodiment of the invention. Referring toFIG. 4, in step402the baseband processor240configure the envelope detector252for a constant gain level c1, as shown in equation [2]. In step404, the envelope detector252may detect the PAD input signal envelope magnitude ∥PADin(t)∥. In step406, the envelope detector252may dynamically compute the PA gain level g3(t) and the PAD gain level g2(t). The values g2(t) and g3(t) may be computed in accordance with equation [2]. The envelope detector252may generate PA Gain Control signals (FIG. 2) in response to the computed value g3(t), and PAD Gain Control signals in response to the computed value g2(t).

In step408, the PAD212may receive PAD Gain Control signals that enable the PAD212to be configured to provide a gain level, g2(t), for amplification of the PADinsignal. In step410, the PA214may receive PA Gain Control signals that enable the PA214to be configured to provide a gain level, g3(t), for amplification of the PAinsignal. In step412, the PA214may generate an output signal, RFout. Step404may follow step412as the envelope detector252detects a subsequent input signal envelope magnitude.

FIG. 4describes a method and system for dynamically adjusting the PAD gain level, g2(t), and/or the PA gain level, g3(t), during continuous operation such that the amplitude of the input signal to the PA214, ∥PAin(t)∥, is maintained approximately constant. The amplitude of the input signal, ∥PAin(t)∥, may be selected to enable efficient operation of the PA214for a given level of delivered power from a DC power supply source, PDC.

Aspects of a method and system for enhancement of power amplifier (PA) efficiency through controlled variation of gain in a power amplifier driver may comprise an envelope detector252that enables detection of an amplitude of an analog input signal. The envelope detector252may enable computation of a first gain value, g2(t), based on the detection. A second gain value, g3(t), may be computed based on the first gain value. A PA214may enable generation of an analog output signal based on the analog input signal, the first gain value and the second gain value. The multiplicative product of the first gain value and the second gain value may be a constant value. The amplitude of the analog input signal may be time varying.

A PAD212may enable generation of an intermediate analog signal based on the analog input signal and the first gain value. The PA214may enable generation of the analog output signal based on the intermediate analog signal and the second gain value. The amplitude of the intermediate analog signal may be constant. The envelope detector252may enable dynamic adjustment of the first gain value based on a detected change in the amplitude of the analog input signal at the PAD212. The envelope detector252may enable dynamic adjustment of the second gain value in response to the dynamically adjusted first gain value. The multiplicative product of the first gain value and the second gain value may be approximately equal to the multiplicative product of the dynamically adjusted first gain value and the dynamically adjusted second gain value. The ratio of the detected amplitude of the analog input signal and an amplitude of the generated analog output signal may be a constant value.

In various embodiments of the invention, AM-AM distortion and/or AM-PM distortion that may result from dynamic gain adjustment may be reduced by utilizing a calibration feedback and input predistortion method as is described in U.S. patent application Ser. No. 11/618,876, which is incorporated herein by reference in its entirety.