Circuit design watermarking

Methods and systems for watermarking a circuit design include defining a watermarked cell library that includes cells, each of which defines a design structure that corresponds to a manufacturable physical structure, at least one of which being a watermarked call that includes a watermark. The watermark is encoded using a design structure that extends beyond a respective cell boundary. A first circuit design file is generated for a device to be manufactured. The first circuit design file including at least one watermarked cell. The first circuit design file is sent to a manufacturer for fabrication of a corresponding device that includes a watermark structure that encodes an identifier.

BACKGROUND

The present invention generally relates to integrated circuit design, and, more particularly, to watermarking integrated circuit designs.

The design of an integrated circuit may be created by a separate entity from that which manufactures the circuit. As a result, the design of the integrated circuit may leave the direct control of the designer when it is sent to the manufacturer. This exposes the design to the risk of being copied, leaked, or stolen, which jeopardizes the designer's intellectual property.

SUMMARY

A method for watermarking a circuit design includes defining a watermarked cell library that includes cells, each of which defines a design structure that corresponds to a manufacturable physical structure, at least one of which being a watermarked call that includes a watermark. The watermark is encoded using a design structure that extends beyond a respective cell boundary. A first circuit design file is generated for a device to be manufactured. The first circuit design file including at least one watermarked cell. The first circuit design file is sent to a manufacturer for fabrication of a corresponding device that includes a watermark structure that encodes an identifier.

A system for watermarking a circuit design includes a hardware processor and a memory that stores a computer program. When the computer program is executed by the hardware processor, it causes the hardware processor to define a watermarked cell library that includes cells, each of which defines a design structure that corresponds to a manufacturable physical structure, at least one of which being a watermarked call that includes a watermark, to generate a first circuit design file for a device to be manufactured, the first circuit design file including at least one watermarked cell, and to send the first circuit design file to a manufacturer for fabrication of a corresponding device. The watermark being encoded using a design structure that extends beyond a respective cell boundary that includes a watermark structure that encodes an identifier.

DETAILED DESCRIPTION

By making subtle alterations to a chip design, a design may effectively be watermarked, such that analysis of a device can definitely show whether or not the device was made using the design. Such watermarking may be used to identify the source of a leak, for example by providing designs with different watermarks to different downstream parties. Watermarking may also be used to indicate that a device is likely to include structures that infringe a patent, for example by showing that a design which embodies the patent was used to make the device.

Exemplary design watermarking may include, for example, modifying the lengths of structures within the design. The watermark may be applied to structures which do not affect the functioning of the device. The lengths of these structures may be used to encode an identifier, such as a serial number or other code. By observing the resulting device under a microscope, these structures can be readily seen and can be used to reproduce the code. In some cases, the design may be watermarked in such a way that the ultimate device is not affected. In such design-only watermarks, the design file itself may be analyzed to find the identifier.

Referring now toFIG.1, a diagram illustrates how a watermarked design may be used. This scenario is presented solely for the sake of illustration, and should not be interpreted as being limiting. A circuit designer110creates a design file that represents instructions for fabricating a device. The circuit designer110transmits the design file to a set of different manufacturers120. In some cases, different manufacturers120may receive a different version of the design file, labeled here as A, B, and C. Each design file includes a different respective watermark. In some cases, each manufacturer120may receive the same design file, with the same watermark.

In this scenario, a third party130obtains design file C. This may be through an intentional or unintentional leak, corporate espionage, trade secret theft, or illicit network intrusion. The third party130uses the design file at a third party manufacturer140to fabricate a device150. The device150includes physical structures that encode the watermark for design file C. The circuit designer110obtains the device150. By analyzing the device150, for example by performing a cross-section of the device150or by observing the device150under a microscope, the circuit designer110can verify that the device was made using design file C.

This knowledge can benefit the circuit designer110in various ways. In some cases, this can be used to identify a leak, so that the manufacturer120that was sent design file C may be excluded from future projects. In other cases, the knowledge that the device150was fabricated using a watermarked design can help the circuit designer to identify infringements of intellectual property.

In other scenarios, rather than recovering a physical device150that was made using a watermarked design file, the circuit designer110may be able to recover the leaked design file itself. In such a case, the circuit designer110may analyze the design file to identify the watermark encoded therein, and may use the knowledge gleaned by that analysis in a manner similar to that described above.

Referring now toFIG.2, a comparison is shown between two logic blocks. These logic blocks may be stored in a cell library that includes a variety of different circuit design parts. When creating a circuit design, a circuit designer110may use these libraries to quickly generate complex structures. A logic block may have a variety of different structures.

In this illustrative example, an unwatermarked first logic block202is compared with a watermarked second logic block212. The first logic block202includes a set of fins204and gates206, and the second logic block includes a respective set of fins214and gates218. Notably, the two logic blocks shown differ in the lengths of their fins, with the fins214of the watermarked logic block212being longer than the fins204of the unwatermarked logic block202. It is particularly contemplated that the watermarked logic block212may be implemented using cells in the cell library that are frequently used in circuit designs, to maximize their occurrence within designs.

The additional lengths218of the longer fins214can be used to encode information. In one illustrative example, a binary value may be encoded by whether the additional length218is on the “top” or “bottom” of the watermarked logic block212, with a length218on the “top” indicating an exemplary binary value of 1, and with a length218on the “bottom” indicating an exemplary binary value of 0. As an alternative, the additional lengths218may be used on one side of the logic block212, with the presence of an additional length218indicating a first binary value and the absence of an additional length218indicating a second binary value. In a further alternative, the size of the additional lengths218may be used to encode non-binary values. For example, multiple different sizes may be used, with each size corresponding to a different numerical value. In a further alternative, some fins214may have additional lengths218on both the top and the bottom of the logic block212. In such an embodiment, the top and the bottom may encode different information.

Following this example, a number of unique codewords that can be created within a particular logic block may be a function of three parameters: a maximum extension X of the additional lengths218, a total cell contact poly pitch (CPP) C, and a layout grid size. The maximum extension X may represent the maximum distance of the additional length218beyond the outline of the logic block212. The layout grid size may be fixed for a given fabrication technology. The number of unique codewords would then be

Referring now toFIG.3, an exemplary pair of neighboring logic blocks is shown. In this example, two logic blocks are placed directly next to one another in a circuit design. Because the additional lengths218of their fins214extend past the boundaries of the logic block212, the fins of one logic block212may extend into a neighboring logic block.

To prevent conflicts, the watermark may be added to designs that can be stacked without conflict. In this present example, the fins214of one logic block overlap with the fins214of the neighboring logic block. Thus, any overlap302that might result from the additional lengths218reaching into a neighboring logic block would not cause a detrimental effect to the ultimate design, as the overlap could be safely ignored.

Thus, when logic blocks overlap in this manner, the watermark is encoded at the periphery of the manufactured device. A place-and-route process may group a large number of such logic blocks together for functional purposes, but an open area may be placed around a tiled pattern of such logic blocks, to meet design rules. At this border, the encoded watermark will be visible. Furthermore, when viewed at a relatively high level of abstraction, with only the general boundaries of the cell being shown, the variations that encode the watermark may not be visible at all. In that case, only zooming in to the granularity of individual structures would show the differences in lengths.

Referring now toFIG.4, a step in an exemplary watermarking scheme is shown. This illustrative view shows a magnified portion402of a larger circuit design. The view402shows the location of mandrels404, which may be formed on a substrate. Between different regions of the design, there may be certain areas of whitespace408. Such white space may be located, for example, at the edge of an array of devices, and is generally non-functional in the ultimate fabricated device. For example, such white space may occur when a placing and routing leaves a gap between neighboring arrays of components, without room for additional components in between. While the bulk of such whitespace may be filled by, e.g., an interlayer dielectric, there may remain some whitespace between the design components and the fill. Similarly, there may not be any fill between neighboring arrays, due to only having a small area.

This whitespace408may be used for watermarking, in a manner similar to that described above. In this illustrative example, the mandrels404may include an additional length410that extends into whitespace408. These additional lengths410can be used to encode values as above. However, mandrels are often removed during processing, such as in a self-aligned double patterning process. Thus, if these additional lengths410are left without further modification, they may not imply any change to the manufactured device. This may be used in some cases to generate a design-only watermark, where the design file will show the watermark, but the device will not.

Referring now toFIG.5, a step in an exemplary watermarking scheme is shown. Similar to the watermark ofFIG.4, the mandrels404may have additional lengths410that extend into a whitespace408. In this view, however, the additional lengths410have been covered by a mask502. This mask502may be used to preserve portions of the mandrels404during regular processing steps, for example to identify regions where fins will ultimately be formed. By covering the additional lengths410, the mask502preserves the additional lengths410for these subsequent processing steps, such that there may remain structures related to the additional lengths410in the manufactured device. Thus, this watermark scheme will be apparent in both the design file and in any device that is manufactured using the design file.

In this example, the circuit design file may provide modified instructions for multiple different stages of chip fabrication. For example, the structure and locations of the mandrels404may be defined in a first patterning step, while the structure and locations of the masks502may be defined in a subsequent patterning step. Watermarking information may be added at different patterning steps as well, including single-exposure direct patterning, multiple-exposure direct patterning, direct patterning with cuts (where cut masks are used in the process step), self-aligned double, triple, or quadruple patterning with no keep mask, and self-aligned double, triple, or quadruple patterning with keep masks to preserve the watermarking.

Additionally, other types of watermarking structures may be used. For example, dummy via arrays may be used to embed a watermark encoding. A metal dummy pattern may similarly be used to encode watermarking information. Thus, the cell definitions in a circuit design library may be modified in any appropriate way to generate repeatable, observable watermarking structures, which are not immediately apparent to a potential infringer who does not know what to look for.

Referring now toFIG.6, a step in an exemplary watermarking scheme is shown. This view shows the chip during the manufacturing process, after the mask502has been applied, after the exposed mandrel410has been etched away, and after the mask502has been removed. The removal of the mask502exposes the remaining pieces of the mandrel410, which were covered by the mask502during the etch of the mandrel410. Subsequent steps, such as an isotropic etch of an underlying layer using remaining mandrel regions602as a mask, or self-aligned double patterning that forms sidewall fins on the remaining mandrel regions602, will leave a structure on the device that will be visible during analysis.

Referring now toFIG.7, a method for watermarking a circuit design is shown. Block702watermarks cells in a design library. As noted above, the design library may include cells with a variety of different logic blocks, each of which may be associated with a different function and different physical structures. These cells may, for example, provide instructions to a device manufacturer on how to create functional structures on a device. As noted above, the watermark may be encoded in the lengths of structures that are defined within the cells, and may include structures that are formed in multiple distinct processing steps. Additionally, the watermark may be a design-only watermark, which may not produce physical differences in a manufactured device. The watermark may alternatively be a design-plus-device watermark, where the manufactured device includes observable physical structures that can be used to extract the watermark.

In block704, the circuit designer110creates a watermarked circuit design file using the library. The watermarked circuit design file includes one or more watermarked logic blocks. As noted above, the design file may undergo automated place-and-route, which automatically organizes the circuit design into a space-efficient layout while maintaining functional connections between components. The watermark is selected such that the watermark structures will survive the place-and-route process to preserve an identifiable watermark when the device is manufactured.

In block706, the circuit designer110distributes the watermarked circuit design to one or more manufacturers120. As noted above, each manufacturer may receive a circuit design file that includes a different encoded watermark, to make the products that they produce distinguishable under a microscope. This step may also include transmitting the design library to the manufacturer, if it is needed for the manufacturer to properly interpret the circuit design. In such a case, it may be advantageous to include cells in the design library that use watermarked cells which will not result in changes in the manufactured device—this makes it possible to identify new designs that have been created with a misappropriated design library, even if the infringer would otherwise notice a watermark on a physical device.

Referring now toFIG.8, a method for detecting and decoding a watermark on a device is shown. In block702, a device is obtained which may have been copied from a watermarked design file, or may have been designed using a library that included watermarked cells. This device may include, for example, an integrated chip, or a larger device that includes an integrated chip in it. The device may be disassembled to expose the device components that are potentially watermarked. For example, a cross-section of the device may be performed, using an appropriate saw or other tool.

Block804then analyzes the device under a microscope or any other appropriate tool. For example, this analysis may include locating cells that correspond to cells that have been watermarked within a design library. These cells may then be checked in detail, in block806, for deviations from a norm (e.g., lengths of structures that exceed a cell boundary) that correspond to a watermark. These deviations serve to identify the location of the watermark. The watermark may then be decoded in block808, for example by determining binary values that correspond to the deviations. Once the watermark has been decoded, appropriate action may be taken against the manufacturer of the device, or the source of a leak.

In other embodiments, the hardware processor subsystem can include dedicated, specialized circuitry that performs one or more electronic processing functions to achieve a specified result. Such circuitry can include one or more application-specific integrated circuits (ASICs), FPGAs, and/or PLAs.

Referring now toFIG.9, a watermarking circuit design system900is shown. The watermarking circuit design system900may be used by a circuit designer110to generate a watermarked circuit design. The system900includes a hardware processor and a memory904. A number of functional components may be implemented in the form of software that is stored in the memory904and that is executed by the hardware processor902. In some embodiments, one or more of the functional components may be implemented in the form of discrete hardware components, for example as ASICs or FPGAs. A network interface906provides communications with other systems, such as the manufacturers120.

A user interface908accepts inputs from a circuit designer using a computer aided design (CAD) system910. The CAD system910accesses a design library912that includes watermarked cells. As described above, these watermarked cells may have design features that can be used to encode specific identifiers as a watermark. The user thereby creates a circuit design914, which may be sent to the manufacturers120.

The same circuit design914may be watermarked with multiple distinct encoded identifiers. For example, the design library may include multiple versions of a given cell, each of which may encode a different value. These differently watermarked circuit designs914may then be forwarded to different manufacturers120.