Method and apparatus of adjusting phase of a sampling clock and prediction timing of a synchronization signal through a disc signal

A detection apparatus of an optical storage device for detecting a synchronization signal includes a sampling module for sampling a disc signal to generate a plurality of sampled data, a comparing module coupled to the sampling module for comparing the sampled data and a synchronization pattern to generate a first compared result and to generate a second comparing result after a time interval, and an adjusting module coupled to the comparing module for gathering a statistic of the first and the second comparing results to generate an adjusting signal for adjusting a phase of the sampling clock.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The invention relates to optical storage devices, and more particularly, to a method and an apparatus of adjusting a sampling phase of the disc signal.

2. Description of the Prior Art

In communication systems, the transmitter utilizes a synchronization pattern in order to align each frame and transfer data. The receiver searches the synchronization pattern when receiving signals and to decode data following after the synchronization pattern. For example, the synchronization pattern of a digital versatile disc (DVD) is a series of 14 signals, whose logic level are all 1. When decoding the DVD signals, the DVD displayer continuously compares the DVD signals with the 14 logic-level-1 signals to search for the synchronization pattern in the DVD signals and decode the following data after the synchronous pattern.

In communication systems, the receiver utilizes a sampling clock to sample the analog signal, and utilizes a signal level to transform the sampling clock into a digital signal for following digital signal process. However, signal jitter causes the sampling signal not to sample the analog signal according to an ideal timing so that the sampling value of the sampling signal diverges from the ideal value. That is, the bit error rate of the communication system rises. When the signal jitter drives the sampling clock to sample at an incorrect timing (that is, the phase of the sampling clock shifts), the sampling signal is determined as an incorrect signal level so that the synchronization signal of the disc signal is impacted or the following decoding procedure of the disc signal is impacted. Furthermore, the disc signal may not be decoded smoothly and correctly.

SUMMARY OF THE INVENTION

It is therefore one objective of the claimed invention to provide a method or an apparatus of adjusting the phase of the sampling clock and/or prediction timing of a synchronization signal through the disc signal.

According to the claimed invention, a detection method comprises: utilizing a sampling clock to sample a disc signal to generate a plurality of sampled data; comparing the sampled data with a synchronization pattern to generate a first compared result and at a specified interval to generate a second compared result after a time interval; and adjusting the timing of the sampling clock according to a statistical result generated from the compared results.

Furthermore, the detection device comprises: a sampling module for utilizing a sampling clock to sample a disc signal for generating a plurality of sampled data; a comparing module for comparing the sampled data and a synchronization pattern to generate a first compared result and to generate a second comparing result after a time interval; and an adjusting module for gathering a statistic of the comparing results to generate an adjusting signal for adjusting a phase of the sampling clock.

DETAILED DESCRIPTION

FIG. 1is a diagram of a phase adjusting device20and a synchronization signal detection device30utilized in an optical disc drive10according to the invention. The optical disc drive10receives an input signal Sin (eg., an eight-to-fourteen modulation (EFM) signal from an optical disc). The analog filter12filters the input signal Sin to generate a filtered signal S. The slicer14transforms the filtered signal into a corresponding sliced signal S′ according to a slice level. Furthermore, non-symmetric compensating module16forms a feedback loop for moving out the DC offset of the sliced signal S′. That is, the DC offset is moved out by adjusting the slice level of the slicer14. In addition, the phase-locked-loop (PLL)18generates a sampling clock CLK according to the sliced signal S′. The phase adjusting device20adjusts a phase of the sampling clock CLK to sample the sliced signal S′, and comprises a delay unit22, a sampling module24, and an adjusting module38. The synchronization signal detection device30detects a synchronization signal of the input signal Sin, and comprises a comparing module32, a storage unit34, and an adjusting module36. In this embodiment, the sampling module24utilizes an adjusted sampling clock CLK′ to sample the sliced signal S′ in order to generate sampled data D. The post-processing module26executes additional processing on the sampled data D.

Please refer toFIG. 2andFIG. 3. The operation is illustrated as follows:

Step100: The sampling module24continuously samples the sliced signal S′ using the adjusted sampling clock CLK′ to orderly generate a plurality of sampled data D.

Step102: The comparing module32compares the sampled data D with a known synchronization pattern to generate a first synchronization signal SYNC1.

Step104: The comparing module32predicts a timing of a next synchronization signal SYNC2according to the first synchronization signal SYNC1. The preferred embodiment is utilized in a DVD system; therefore, the interval of two synchronization signals is 1488 cycles. In addition, it is easily seen that the timing of the synchronization signal SYNC2comes 1488 cycles after the timing of the synchronization signal SYNC1.

Step106: Before the predicted timing of the second synchronization signal SYNC2, the comparing module32compares the sampled data corresponding to the comparing timing with the synchronization pattern to generate a plurality of calculation values V. In this embodiment, the comparing module32compares the sampled data D with the synchronization pattern from 2 cycles before the timing of the synchronization signal SYNC2, and triggers the storing clock CLKsv. That is, the comparing module32compares the sampled data D with the synchronization pattern between 2 cycles before the timing of the synchronization signal SYNC2and 2 cycles after the timing of the synchronization signal SYNC2to respectively calculate 5 calculation values V.

Step108: The storage unit34stores the calculation values V according to a storing clock CLKsv. In this embodiment, the 5 calculation values V are stored in the storage unit34. In this embodiment, the calculation value V is calculated by executing correlation arithmetic on the sampled data D and the predetermined synchronization pattern. This also means that the calculation value V represents the similarity between the sampled data D and the synchronization pattern.

Step110: The adjusting module36predicts a timing of a third synchronization signal according to the calculation values V stored in the storage unit34.

Step112: The adjusting module36utilizes the calculation values V stored in the storage unit34to drive the delay unit22for adjusting the phase of the adjusted sampling clock CLK′.

FIG. 4is a block diagram of the comparing module32shown inFIG. 1. The comparing module32comprises serially-coupled delay units40a,40b,40c, and40d, an adder42, a subtractor44, and a delay unit46. In this embodiment, the input signal Sin is a signal which conforms to the DVD standard. Therefore, the comparing module32utilizes 14 serially-coupled delay units40to compare the synchronization pattern having 14 continuous logic values 1. Additionally, the comparing module32executes correlation arithmetic on the synchronization pattern having 14 continuous logic values 1 to calculate a correlation value (the calculation value V). The sampled data D is orderly inputted into the comparing module32. In the following, assuming that the delay units40a,40b,40c,40d, and46all have an initial value 0, when a sampled data D1is inputted into the delay unit40a, the delay unit40akeeps the sampled data D1. Furthermore, the output data A of the adder42is the sampled data D1, and the output data C of the subtractor44is also sampled data D1. When next sampled data D2is inputted into a delay unit40a, the delay unit40atransfers the original sampled data D1to the delay unit40band then keeps the sampled data D2. This also means that the delay units40aand40bkeep the sampled data D2and D1, respectively. Furthermore, because the delay unit currently keeps the sampled data D1, the output data A of the adder42is the sum of the sampled data D1and D2, and the output data C of the subtractor44is also the sum of the sampled data D1and D2. Therefore, the delay unit46updates the stored value to be the sum of the sampled data D1and D2. Furthermore, when the above-mentioned 14 sampled data D1-D14are all inputted into the comparing module32, the delay units40a,40b,40c,40drespectively store the sampled data D14, D13, D2, D1, and the delay unit46stores the sum of all sampled data D1-D14. When the next sampled data D15is inputted into the comparing module32, the output data A of the adder42is the sum of the sampled data D1-D15, and the delay unit40dkeeps the sampled data D2and outputs the original sampled data D1(the output data B). Therefore, the output data C of the subtractor44becomes the sum of the sampled data D2-D15so that the stored value (the calculation value V) in the delay unit46is further updated. Please note that the delay units40a,40b,40c,40dshown inFIG. 4eventually store the sampled data D15, D14, D3, D2. Therefore, for every 14 sampled data, the comparing module32can calculate the calculation value V corresponding to the time interval of the 14 sampled data.

FIG. 5is a diagram of the storage unit34shown inFIG. 1. The storage unit34comprises registers50,52,54,56,58, which are used for respectively storing the five calculation values V. The calculation values V are calculated in order by the comparing module32, according to the storing clock CLKsv. Here, the starting timing of the comparing time corresponding to the register54is a median value of a plurality of starting timing of the comparing time corresponding to the registers50,52,54,56, and58. Please refer toFIG. 5andFIG. 6. For ease of illustration, five marks R−2, R−1, R0, R1, and R2are respectively used on the horizontal axis to represent the above-mentioned registers50,52,54,56, and58. Additionally, the vertical axis represents the calculation values V (or called as correlation value in this invention) stored in the registers50,52,54,56, and58. For example, in an ideal operation, the calculation value of the comparing module32is 12 at 2 cycles before the predetermined timing of the synchronization signal SYNC2. Additionally, the calculation value (12) is stored in the register50. At 1 cycle before the predetermined timing of the synchronization signal SYNC2, the calculation value of 13 is stored in the register52. Similarly, at the predetermined timing of the synchronization signal SYNC2, the calculation value of 14 is stored in the register54. Similarly, at 1 cycle after the predetermined timing of the synchronization signal SYNC2, the calculation value of 13 is stored in the register56. Additionally, at 2 cycles after the predetermined timing of the synchronization signal SYNC2, the calculation value of 12 is stored in the register58.

In this embodiment, the adjusting module36utilizes the calculation values V stored in the registers50,52,54,56, and58to predict and adjust the timing of the next synchronization signal SYNC3. If the timing of the synchronization signal SYNC2can be correctly predicted according to the synchronization signal, the register54stores the largest calculation value among the registers50,52,54,56, and58. If the largest calculation value is not stored in the register54, a shift value between the register having the biggest calculation value and the register54is utilized to determine a timing offset of the current synchronization signal SYNC2, and further utilized to adjust the predicted timing of the next synchronization signal SYNC3. For example, if the biggest calculation value is stored in the register56(for example, when the synchronization signal SYNC1is used to predict the timing of the synchronization signal SYNC2, the predicted timing of the synchronization signal SYNC2is 1 cycle later than the real timing of the synchronization signal SYNC2), therefore, when the predicted timing of the synchronization signal SYNC2is utilized to predict the timing of the synchronization signal SYNC3, one cycle should be advanced to correctly predict the timing of the synchronization signal SYNC3. This also means that after 1487 cycles from the predicted timing of the synchronization signal SYNC2, the next triggered timing of the next cycle is the timing of the synchronization signal SYNC3. Furthermore, if the largest calculation value is stored in the register50(for example, when the synchronization signal SYNC1is utilized to predict the timing of the synchronization signal SYNC2, the predicted timing of synchronization signal SYNC2is 2 cycles early than the real timing of the synchronization signal SYNC2), therefore, when the predicted timing of the synchronization signal SYNC2is used to predict the timing of the synchronization signal SYNC3, 2 sampling clock cycles have to be delayed. That is, after 1490 sampling clock cycles from the predicted timing of the synchronization signal SYNC2, the next triggered timing of the next cycle is the timing of the synchronization signal SYNC3. In this way, the adjusting module38can utilize the calculation values according to the 5 comparing timings to adjust the predicted timing of the next synchronization signal.

In this embodiment, the adjusting module38also utilizes the calculation values V stored in the registers50,52,54,56, and58to drive the delay unit22for adjusting the phase of the adjusted sampling clock CLK′. Please refer toFIG. 7, which is a diagram of an average calculation value generated by the adjusting module38of the phase adjusting device20shown inFIG. 1. The horizontal axis represents the registers RV−2, RV−1, RV0, RV1, RV2, which are used for storing the average calculation value, and the vertical axis represents the average calculation value. The registers RV−2, RV−1, RV0, RV1, RV2corresponds to the registers50,52,54,56,58of the storage unit34, respectively. Furthermore, each register RV−2, RV−1, RV0, RV1, RV2is used to store an average value of the calculation values V outputted by the corresponding registers50,52,54,56,58. In other words, the adjusting module36continuously calculates a new average value according to the received calculation values V in order to update the original average value. In an ideal situation, when the adjusted sampling clock CLK′ does not have significant jitter, the average calculation values V1, V2, V3, V4, V5stored in the registers RV−2, RV−1, RV0, RV1, RV2correspond to the characteristic curve CV shown inFIG. 7. That is, two registers (such as RV−1and RV1, or RV−2and RV2) symmetric to the central register RV0theoretically have the same average calculation value. However, when the adjusted sampling clock CLK′ samples earlier because of jitter, the average calculation value stored in the register RV−1is between 12 and 13 (as shown by mark A inFIG. 6), and the average calculation value stored in the register RV1is between 13 and 14 (as shown by mark C inFIG. 6). Therefore, if the average calculation value stored in the register RV1is larger than the average calculation value stored in the register RV−1, the adjusting module36drives the delay unit22to delay the adjusted sampling clock CLK′ to sample the disc signal. On the other hand, when the adjusted sampling clock CLK′ is delayed because of jitter, the average calculation value stored in the register RV−1is between 13 and 14 (as the mark B shown inFIG. 6), and the average calculation value stored in the register RV1is between 12 and 13 (as the mark D shown inFIG. 6). Therefore, if the average calculation value stored in the register RV−1is larger than the average calculation value stored in the register RV1, the adjusting module36drives the delay unit22to make the adjusted sampling clock CLK′ sample the disc signal earlier. Finally, the sampling module24utilizes the adjusted sampling clock CLK′ to sample the slicing signal S′ in order to generate sampled data, and then the post-processing module26post-processes the sampled data (such as demodulation or digital signal processing).

As mentioned above, the adjusting module36utilizes a maximum calculation value stored in the register50,52,54,56,58to adjust the predicted timing of the next synchronization signal. Because the calculation values are symmetric, the calculation values stored in the symmetric registers can also be used to determine the predicted timing. That is, in an ideal situation, symmetric registers (register52and register56) theoretically have the same calculation value. When the maximum calculation value is stored in the register56and the calculation value of the register is 12, a shift value can be calculated by subtracting the maximum calculation value and the calculation value of the register52, where the shift value is used to represent that the predicted timing of the synchronization signal SYNC2has to be delayed to meet the real timing. Therefore, the timing of the next synchronization signal SYNC3is also predicted according to the shift value. Furthermore, the calculation values stored in symmetric registers can be used to check if the sampling phase of the disc signal is correct, and used to further drive the delay unit22to adjust the phase of the adjusted sampling clock CLK′.

In this invention, the synchronization signal is not detected through comparing all sampled data. The invention only compares several cycles to determine a shift value, and utilizes the shift value to adjust the timing of the next synchronization. Therefore, if an optical disc is partially damaged, the present invention can quickly determine a correct synchronization signal so that the power consumption is reduced. Furthermore, adjusting the phase of the adjusted clock according to this invention so that bit error rate due to jitter is reduced.