Three-dimensional memory device including laterally constricted current paths and methods of manufacturing the same

A vertically alternating sequence of insulating layers and sacrificial material layers is formed over a substrate. Line trenches extending along a first horizontal direction are formed through the vertically alternating sequence. The vertically alternating sequence is divided into vertically alternating stacks of insulating strips and sacrificial material strips. Laterally alternating sequences of memory opening fill structures and dielectric pillar structures are formed within the line trenches. Each of the memory opening fill structures includes a respective vertical bit line and memory material portion located between each laterally neighboring pair of the sacrificial material strip and the vertical bit line. A lateral extent of an overlap between the memory material portion and a most proximal one of the sacrificial material strips along the first horizontal direction is less than a lateral extent along the first horizontal direction of the memory opening fill structure containing the memory material portion. The sacrificial material strips are replaced with electrically conductive strips.

FIELD

The present disclosure relates generally to the field of semiconductor devices, and particular to a three-dimensional memory device containing laterally constricted current paths and methods of manufacturing the same.

BACKGROUND

A phase change material (PCM) memory device (also known as a phase change random access memory “PCRAM” or “PRAM”) is a type of non-volatile memory device that stores information as a resistivity state of a material that can be in different resistivity states corresponding to different phases of the material. The different phases can include an amorphous state having high resistivity and a crystalline state having low resistivity (i.e., a lower resistivity than in the amorphous state). The transition between the amorphous state and the crystalline state can be induced by controlling the rate of cooling after application of an electrical pulse that renders the phase change material amorphous in a first part of a programming process. The second part of the programming process includes control of the cooling rate of the phase change material. If rapid quenching occurs, the phase change material can cool into an amorphous high resistivity state. If slow cooling occurs, the phase change material can cool into a crystalline low resistivity state.

SUMMARY

According to an aspect of the present disclosure, a three-dimensional memory device comprises vertically alternating stacks of insulating strips and electrically conductive strips that overlie a substrate and are laterally spaced from each other by line trenches that laterally extend along a first horizontal direction, and laterally alternating sequences of memory opening fill structures and dielectric pillar structures located within a respective one of the line trenches. Each memory opening fill structure comprising a respective vertical bit line and a memory material portion, and the memory material portion is located between the vertical bit line and a respective electrically conductive strip. The insulating strips and the electrically conductive strips laterally extend along the first horizontal direction and the vertically alternating stacks are laterally spaced apart along a second horizontal direction that is perpendicular to the first horizonal direction. A lateral extent of an overlap between the memory material portion and a most proximal one of the electrically conductive strips along the first horizontal direction is less than a lateral extent along the first horizontal direction of the memory opening fill structure containing the memory material portion.

According to another aspect of the present disclosure, a method of forming a three-dimensional memory device is provided, which comprises: forming an vertically alternating sequence of insulating layers and sacrificial material layers over a substrate; forming line trenches extending along a first horizontal direction through the vertically alternating sequence, wherein the vertically alternating sequence is divided into vertically alternating stacks of insulating strips and sacrificial material strips that are laterally spaced apart along a second horizontal direction; forming laterally alternating sequences of memory opening fill structures and dielectric pillar structures within the line trenches, wherein each of the memory opening fill structures comprises a vertical bit line and a memory material portion located between each laterally neighboring pair of a sacrificial material strip and the vertical bit line, wherein a lateral extent of an overlap between the memory material portion and a most proximal one of the sacrificial material strips along the first horizontal direction is less than a lateral extent along the first horizontal direction of the memory opening fill structure containing the memory material portion; and replacing the sacrificial material strips with electrically conductive strips.

DETAILED DESCRIPTION

As discussed above, the embodiments of the present disclosure are directed to three-dimensional phase change memory devices including laterally constricted current paths between the word lines and the phase change material in each memory cell and methods of manufacturing the same.

The drawings are not drawn to scale. Multiple instances of an element may be duplicated where a single instance of the element is illustrated, unless absence of duplication of elements is expressly described or clearly indicated otherwise. Ordinals such as “first,” “second,” and “third” are employed merely to identify similar elements, and different ordinals may be employed across the specification and the claims of the instant disclosure. The same reference numerals refer to the same element or similar element. Unless otherwise indicated, elements having the same reference numerals are presumed to have the same composition and the same function.

Unless otherwise indicated, a “contact” between elements refers to a direct contact between elements that provides an edge or a surface shared by the elements. As used herein, a first element located “on” a second element can be located on the exterior side of a surface of the second element or on the interior side of the second element. As used herein, a first element is located “directly on” a second element if there exist a physical contact between a surface of the first element and a surface of the second element. As used herein, a first element is “electrically connected to” a second element if there exists a conductive path consisting of at least one conductive material between the first element and the second element. As used herein, a “prototype” structure or an “in-process” structure refers to a transient structure that is subsequently modified in the shape or composition of at least one component therein.

As used herein, a first surface and a second surface are “vertically coincident” with each other if the second surface overlies or underlies the first surface and there exists a vertical plane or a substantially vertical plane that includes the first surface and the second surface. A substantially vertical plane is a plane that extends straight along a direction that deviates from a vertical direction by an angle less than5degrees. A vertical plane or a substantially vertical plane is straight along a vertical direction or a substantially vertical direction, and may, or may not, include a curvature along a direction that is perpendicular to the vertical direction or the substantially vertical direction.

Referring toFIG. 1, a first exemplary structure according to a first embodiment of the present disclosure is illustrated, which can be employed, for example, to fabricate a three-dimensional phase change memory device. The first exemplary structure includes a substrate9. The substrate can include a substrate semiconductor layer9. The substrate semiconductor layer9maybe a semiconductor wafer or a semiconductor material layer, and can include at least one elemental semiconductor material (e.g., single crystal silicon wafer or layer), at least one III-V compound semiconductor material, at least one II-VI compound semiconductor material, at least one organic semiconductor material, or other semiconductor materials known in the art. The substrate can have a major surface7, which can be, for example, a topmost surface of the substrate semiconductor layer9. The major surface7can be a semiconductor surface. In one embodiment, the major surface7can be a single crystalline semiconductor surface, such as a single crystalline semiconductor surface.

At least one semiconductor device700for a peripheral circuitry can be formed on a portion of the substrate semiconductor layer9. The at least one semiconductor device can include, for example, field effect transistors. For example, at least one shallow trench isolation structure720can be formed by etching portions of the substrate semiconductor layer9and depositing a dielectric material therein. A gate dielectric layer, at least one gate conductor layer, and a gate cap dielectric layer can be formed over the substrate semiconductor layer9, and can be subsequently patterned to form at least one gate structure (750,752,754,758), each of which can include a gate dielectric750, a gate electrode (752,754), and a gate cap dielectric758. The gate electrode (752,754) may include a stack of a first gate electrode portion752and a second gate electrode portion754. At least one gate spacer756can be formed around the at least one gate structure (750,752,754,758) by depositing and anisotropically etching a dielectric liner. Active regions730can be formed in upper portions of the substrate semiconductor layer9, for example, by introducing electrical dopants employing the at least one gate structure (750,752,754,758) as masking structures. Additional masks may be employed as needed. The active region730can include source regions and drain regions of field effect transistors. A first dielectric liner761and a second dielectric liner762can be optionally formed. Each of the first and second dielectric liners (761,762) can comprise a silicon oxide layer, a silicon nitride layer, and/or a dielectric metal oxide layer. As used herein, silicon oxide includes silicon dioxide as well as non-stoichiometric silicon oxides having more or less than two oxygen atoms for each silicon atoms. Silicon dioxide is preferred. In an illustrative example, the first dielectric liner761can be a silicon oxide layer, and the second dielectric liner762can be a silicon nitride layer. The least one semiconductor device for the peripheral circuitry can contain a driver circuit for memory devices to be subsequently formed, which can include at least one phase change memory device.

A dielectric material such as silicon oxide can be deposited over the at least one semiconductor device, and can be subsequently planarized to form a planarization dielectric layer770. In one embodiment the planarized top surface of the planarization dielectric layer770can be coplanar with a top surface of the dielectric liners (761,762). Subsequently, the planarization dielectric layer770and the dielectric liners (761,762) can be removed from an area to physically expose a top surface of the substrate semiconductor layer9. As used herein, a surface is “physically exposed” if the surface is in physical contact with vacuum, or a gas phase material (such as air).

An insulating material layer10is formed on the top surface of the substrate semiconductor layer9prior to, or after, formation of the at least one semiconductor device700by deposition of an insulating material, for example, by chemical vapor deposition. The insulating material layer can be any insulating material, such as silicon oxide, and may have a thickness of 50 nm to 300 nm. Portions of the deposited insulating material located above the top surface of the planarization dielectric layer770can be removed, for example, by chemical mechanical planarization (CMP). In this case, the insulating material layer10can have a top surface that is coplanar with the top surface of the planarization dielectric layer770.

The region (i.e., area) of the at least one semiconductor device700is herein referred to as a peripheral device region200. The region in which a memory array is subsequently formed is herein referred to as a memory array region100. A staircase region300for subsequently forming stepped terraces of electrically conductive layers can be provided between the memory array region100and the peripheral device region200.

Each first material layer includes a first material, and each second material layer includes a second material that is different from the first material. In one embodiment, each first material layer can be an insulating layer32L, and each second material layer can be a sacrificial material layer. In this case, the stack can include an alternating plurality of insulating layers32L and sacrificial material layers42L, and constitutes a prototype stack of alternating layers comprising insulating layers32L and sacrificial material layers42L.

The stack of the alternating plurality is herein referred to as a vertically alternating sequence (32L,42L). In one embodiment, the vertically alternating sequence (32L,42L) can include insulating layers32L composed of the first material, and sacrificial material layers42L composed of a second material different from that of insulating layers32L. The first material of the insulating layers32L can be at least one insulating material. As such, each insulating layer32L can be an insulating material layer. Insulating materials that can be employed for the insulating layers32L include, but are not limited to, silicon oxide (including doped or undoped silicate glass), silicon nitride, silicon oxynitride, organosilicate glass (OSG), spin-on dielectric materials, dielectric metal oxides that are commonly known as high dielectric constant (high-k) dielectric oxides (e.g., aluminum oxide, hafnium oxide, etc.) and silicates thereof, dielectric metal oxynitrides and silicates thereof, and organic insulating materials. In one embodiment, the first material of the insulating layers32L can be silicon oxide.

The sacrificial material layers42L may comprise an insulating material, a semiconductor material, or a conductive material. The second material of the sacrificial material layers42L can be subsequently replaced with electrically conductive electrodes which can function, for example, as word lines of a phase change memory device. Non-limiting examples of the second material include silicon nitride, an amorphous semiconductor material (such as amorphous silicon), and a polycrystalline semiconductor material (such as polysilicon). In one embodiment, the sacrificial material layers42L can be spacer material layers that comprise silicon nitride or a semiconductor material including at least one of silicon and germanium.

In one embodiment, the insulating layers32L can include silicon oxide, and sacrificial material layers can include silicon nitride sacrificial material layers. The first material of the insulating layers32L can be deposited, for example, by chemical vapor deposition (CVD). For example, if silicon oxide is employed for the insulating layers32L, tetraethyl orthosilicate (TEOS) can be employed as the precursor material for the CVD process. The second material of the sacrificial material layers42L can be formed, for example, CVD or atomic layer deposition (ALD).

The sacrificial material layers42L can be suitably patterned so that conductive material portions to be subsequently formed by replacement of the sacrificial material layers42L can function as electrically conductive electrodes, such as word lines of a phase change memory device to be subsequently formed. The sacrificial material layers42L may comprise a portion having a strip shape extending substantially parallel to the major surface7of the substrate.

The thicknesses of the insulating layers32L and the sacrificial material layers42L can be in a range from20nm to50nm, although lesser and greater thicknesses can be employed for each insulating layer32L and for each sacrificial material layer42L. The number of repetitions of the pairs of an insulating layer32L and a sacrificial material layer (e.g., a control gate electrode or a sacrificial material layer)42L can be in a range from 2 to 1,024, and typically from 8 to 256, although a greater number of repetitions can also be employed. The top and bottom gate electrodes in the stack may function as the select gate electrodes. In one embodiment, each sacrificial material layer42L in the vertically alternating sequence (32L,42L) can have a uniform thickness that is substantially invariant within each respective sacrificial material layer42L.

Optionally, an insulating cap layer70L can be formed over the vertically alternating sequence (32L,42L). The insulating cap layer70L includes a dielectric material that is different from the material of the sacrificial material layers42L. In one embodiment, the insulating cap layer70L can include a dielectric material that can be employed for the insulating layers32L as described above. The insulating cap layer70L can have a greater thickness than each of the insulating layers32L. The insulating cap layer70L can be deposited, for example, by chemical vapor deposition. In one embodiment, the insulating cap layer70L can be a silicon oxide layer.

The terrace region is formed in the staircase region300, which is located between the memory array region100and the peripheral device region200containing the at least one semiconductor device for the peripheral circuitry. The stepped cavity can have various stepped surfaces such that the horizontal cross-sectional shape of the stepped cavity changes in steps as a function of the vertical distance from the top surface of the substrate9.

In one embodiment, the stepped cavity can be formed by repetitively performing a set of processing steps. The set of processing steps can include, for example, an etch process of a first type that vertically increases the depth of a cavity by one or more levels, and an etch process of a second type that laterally expands the area to be vertically etched in a subsequent etch process of the first type. As used herein, a “level” of a structure including alternating plurality is defined as the relative position of a pair of a first material layer and a second material layer within the structure.

Each sacrificial material layer42L other than a topmost sacrificial material layer42L within the vertically alternating sequence (32L,42L) laterally extends farther than any overlying sacrificial material layer42L within the vertically alternating sequence (32L,42L) in the terrace region. The terrace region includes stepped surfaces of the vertically alternating sequence (32L,42L) that continuously extend from a bottommost layer within the vertically alternating sequence (32L,42L) to a topmost layer within the vertically alternating sequence (32L,42L).

Each vertical step of the stepped surfaces can have the height of one or more pairs of an insulating layer32L and a sacrificial material layer. In one embodiment, each vertical step can have the height of a single pair of an insulating layer32L and a sacrificial material layer42L. In another embodiment, multiple “columns” of staircases can be formed along a first horizontal direction hd1such that each vertical step has the height of a plurality of pairs of an insulating layer32L and a sacrificial material layer42L, and the number of columns can be at least the number of the plurality of pairs. Each column of staircase can be vertically offset among one another such that each of the sacrificial material layers42L has a physically exposed top surface in a respective column of staircases. In the illustrative example, two columns of staircases are formed for each block of memory stack structures to be subsequently formed such that one column of staircases provide physically exposed top surfaces for odd-numbered sacrificial material layers42L (as counted from the bottom) and another column of staircases provide physically exposed top surfaces for even-numbered sacrificial material layers (as counted from the bottom). Configurations employing three, four, or more columns of staircases with a respective set of vertical offsets among the physically exposed surfaces of the sacrificial material layers42L may also be employed. Each sacrificial material layer42L has a greater lateral extent, at least along one direction, than any overlying sacrificial material layers42L such that each physically exposed surface of any sacrificial material layer42L does not have an overhang. In one embodiment, the vertical steps within each column of staircases may be arranged along the first horizontal direction hd1, and the columns of staircases may be arranged along a second horizontal direction hd2that is perpendicular to the first horizontal direction hd1. In one embodiment, the first horizontal direction hd1may be perpendicular to the boundary between the memory array region100and the staircase region300.

A retro-stepped dielectric material portion65(i.e., an insulating fill material portion) can be formed in the stepped cavity by deposition of a dielectric material therein. For example, a dielectric material such as silicon oxide can be deposited in the stepped cavity. Excess portions of the deposited dielectric material can be removed from above the top surface of the insulating cap layer70L, for example, by chemical mechanical planarization (CMP).

The remaining portion of the deposited dielectric material filling the stepped cavity constitutes the retro-stepped dielectric material portion65. As used herein, a “retro-stepped” element refers to an element that has stepped surfaces and a horizontal cross-sectional area that increases monotonically as a function of a vertical distance from a top surface of a substrate on which the element is present. If silicon oxide is employed for the retro-stepped dielectric material portion65, the silicon oxide of the retro-stepped dielectric material portion65may, or may not, be doped with dopants such as B, P, and/or F.

Referring toFIGS. 4A-4D, a lithographic material stack (not shown) including at least a photoresist layer can be formed over the insulating cap layer70L and the retro-stepped dielectric material portion65, and can be lithographically patterned to form line-shaped openings therein. The line-shaped openings laterally extend along a first horizontal direction hd1, and have a uniform width along a second horizontal direction hd2that is perpendicular to the first horizontal direction hd1. The pattern in the lithographic material stack can be transferred through the insulating cap layer70L or the retro-stepped dielectric material portion65, and through the vertically alternating sequence (32L,42L) by at least one anisotropic etch that employs the patterned lithographic material stack as an etch mask. Portions of the vertically alternating sequence (32L,42L) underlying the line-shaped openings in the patterned lithographic material stack are etched to form line trenches49. As used herein, a “line trench” refers to a trench that has laterally extends straight along a horizontal direction.

The line trenches49laterally extend along the first horizontal direction hd1(e.g., word line direction) through the vertically alternating sequence (32,42). In one embodiment, the line trenches49have a respective uniform width that is invariant under translation along the first horizontal direction hd1. In one embodiment, the line trenches49can have the same width throughout, and the spacing between neighboring pairs of the line trenches49can be the same. In this case, the line trenches49can constitute a one-dimensional periodic array of line trenches49having a pitch along a second horizontal direction hd2(e.g., bit line direction) that is perpendicular to the first horizontal direction hd1. The width of the line trenches49along the second horizontal direction hd2can be in a range from 30 nm to 500 nm, such as from 60 nm to 250 nm, although lesser and greater widths can also be employed.

The line trenches49extend through each layer of the vertically alternating sequence (32,42) and the retro-stepped dielectric material portion65. The chemistry of the anisotropic etch process employed to etch through the materials of the vertically alternating sequence (32L,42L) can alternate to optimize etching of the first and second materials in the vertically alternating sequence (32L,42L). The anisotropic etch can be, for example, a series of reactive ion etches. The sidewalls of the line trenches49can be substantially vertical, or can be tapered. The patterned lithographic material stack can be subsequently removed, for example, by ashing.

The line trenches49laterally extend through the entire memory array region100, and laterally extend into the contact region300. The line trenches49may laterally extend through the entire contact region300along the first horizontal direction hd1, or may laterally extend only through part of a width, but not the entire width along the first horizontal direction hd1, of the contact region300. In one embodiment, an overetch into the insulating material layer10may be optionally performed after the top surface of the insulating material layer10is physically exposed at a bottom of each line trench49. The overetch may be performed prior to, or after, removal of the lithographic material stack. In other words, the recessed surfaces of the insulating material layer10may be vertically offset from the un-recessed top surfaces of the insulating material layer10by a recess depth. The recess depth can be, for example, in a range from 1 nm to 50 nm, although lesser and greater recess depths can also be employed. The overetch is optional, and may be omitted. If the overetch is not performed, the bottom surfaces of the line trenches49can be coplanar with the topmost surface of the insulating material layer10.

Each of the line trenches49may include a sidewall (or a plurality of sidewalls) that extends substantially perpendicular to the topmost surface of the substrate. Each patterned portion of an insulating layer32L is herein referred to as an insulating strip32, which can laterally extend along the first horizontal direction hd1and is located between a respective neighboring pair of line trenches49. Each patterned portion of a sacrificial material layer42L is herein referred to as a sacrificial material strip42, which can laterally extend along the first horizontal direction hd1and is located between a respective neighboring pair of line trenches49. Each patterned portion of the insulating cap layer70L is herein referred to as an insulating cap strip70, which can laterally extend along the first horizontal direction hd1and is located between a respective neighboring pair of line trenches49. The vertically alternating sequence (32L,42L) is divided into vertically alternating stacks (32,42) of insulating strips32and sacrificial material strips42that laterally extend along the first horizontal direction hd1, and are laterally spaced apart along a second horizontal direction hd2. A vertically alternating stack (32,42) is also referred to as an alternating stack (32,42) in the present disclosure.

Referring toFIGS. 5A and 5B, a sacrificial fill material is deposited in the line trenches49. The sacrificial fill material comprises a material that can be removed selective to the materials of the insulating strips32, the sacrificial material strips42, and the insulating cap strips70. For example, the sacrificial fill material can include amorphous silicon, a silicon-germanium alloy, amorphous carbon, diamond-like carbon, a polymer material, borosilicate glass, or organosilicate glass. In one embodiment, a sacrificial liner such as a silicon oxide liner, a silicon nitride liner, or a dielectric oxide liner may be deposited prior to deposition of the sacrificial fill material in the line trenches49. Excess portions of the sacrificial fill material can be removed from above the horizontal plane including the top surfaces of the insulating cap strips70. Each remaining portion of the sacrificial fill material filling a respective line trench49constitutes a sacrificial rail structure22R that laterally extends along the first horizontal direction hd1.

Referring toFIGS. 6A-6D, a photoresist layer can be applied over the vertically alternating stacks (32,42) and the sacrificial rail structures22R, and can be lithographically patterned to form a two-dimensional array of openings therethrough. The two-dimensional array of openings includes rows of opening arranged along the first horizontal direction hd1and overly a respective one of the sacrificial rail structures22R. An anisotropic etch process can be performed to etch portions of the material of the sacrificial rail structures22R that are not masked by the patterned photoresist layer. In one embodiment, the chemistry of the anisotropic etch process can etch the material of the sacrificial rail structures22R selective to the material of the insulating cap strips70. In one embodiment, edges of the openings in the photoresist layer that overlie the sacrificial rail structures22R can be parallel to the second horizontal direction hd2.

Via cavities23′ can be formed in the volumes from which portions of the sacrificial rail structures22R are removed. Each via cavity23′ can vertically extend down to the top surface of the substrate9, such as the top surface of the insulating material layer10. In one embodiment, the via cavities23′ can comprise rectangular via cavities having a respective rectangular horizontal cross-sectional shape. Each remaining portion of the sacrificial rail structures22R constitutes a sacrificial pillar structure22. In one embodiment, each sacrificial pillar structure22can have a rectangular horizontal cross-sectional area. In one embodiment, a row of sacrificial pillar structures22can be interlaced with a row of via cavities23′ within each line trench49.

Referring toFIGS. 7A and 7B, an isotropic etch process is performed to laterally recess the sacrificial material strips42selective to the insulating strips32, the insulating cap strips70, and the sacrificial pillar structures22. In an illustrative example, the sacrificial material strips42include silicon nitride, the insulating strips32and the insulating cap strips70include silicon oxide, and the sacrificial pillar structures22can include amorphous silicon. In this case, a wet etch process employing hot phosphoric acid, a mixture of hydrofluoric acid and glycerol at an elevated temperature, or a mixture of ethylene glycol, acetic acid, nitric acid, and ammonium fluoride at an elevated temperature may be employed to laterally recess the sacrificial material strips42selective to the insulating strips32, the insulating cap strips70, and the sacrificial pillar structures22.

In one embodiment, each of the sacrificial pillar structures22can have a same first rectangular horizontal cross-sectional shape, and each of the via cavities23′ can have a same second rectangular shape prior to the isotropic etch process. The lateral recess distance of the isotropic etch process can be less than one half of the dimension of each sacrificial pillar structure22along the first horizontal direction hd1. A laterally-undulating via cavity23is formed by lateral expansion of each via cavity23′ at the levels of the sacrificial material strips42. Each of the laterally-undulating via cavities23has a vertical cross-sectional profile along vertical planes that are perpendicular to the first horizontal direction in which the respective laterally-undulating via cavity23′ laterally protrudes at each level of the sacrificial material strips42. Each horizontal cross-sectional view of a laterally-undulating via cavities23at a level of a sacrificial material strip42includes a rectangular shape and a pair of “wing shapes” that have an areal overlap with overlying insulating strips32and/or underlying insulating strips32. Each rectangular shape does not have any areal overlap with overlying insulating strips32and/or underlying insulating strips32. Each horizontal cross-sectional view of a laterally-undulating via cavities23at a level of an insulating strip32includes only a rectangular shape. Each sacrificial pillar structure22can have a rectangular horizontal cross-sectional shape that is invariant with translation along a vertical direction.

Referring toFIGS. 8A and 8B, a dielectric fill material can be deposited within each of the laterally-undulating via cavities23by a conformal deposition process (such as low pressure chemical vapor deposition process) or a self-planarizing deposition process (such as spin coating). The dielectric fill material can include a planarizable dielectric material such as undoped silicate glass, a doped silicate glass, or flowable oxide (FOX). Excess portions of the dielectric fill material can be removed from above the horizontal plane including the top surfaces of the insulating cap strips70. Each remaining portion of the dielectric fill material constitutes a dielectric pillar structure24.

Each dielectric pillar structure24has a laterally-undulating vertical profile in vertical cross-sectional views in vertical planes that are perpendicular to the first horizontal direction hd1. Each horizontal cross-sectional view of a dielectric pillar structure24at a level of a sacrificial material strip42includes a rectangular shape and a pair of wing shapes that have an areal overlap with overlying insulating strips32and/or underlying insulating strips32. Each rectangular shape does not have any areal overlap with overlying insulating strips32and/or underlying insulating strips32. Each horizontal cross-sectional view of a dielectric pillar structure24at a level of an insulating strip32includes only a rectangular shape. A two-dimensional array of dielectric pillar structures24is formed. In one embodiment, each sacrificial pillar structure22can have a rectangular horizontal cross-sectional area. In one embodiment, a row of dielectric pillar structures24can be interlaced with a row of sacrificial pillar structures22within each line trench49. A laterally alternating sequence of sacrificial pillar structures22and dielectric pillar structures24is formed within each line trench49.

Referring toFIGS. 9A and 9B, the sacrificial pillar structures22can be removed selective to the dielectric pillar structures24, the insulating strips32, the insulating cap strips70, the sacrificial material strips42, and the insulating material layer10. If the sacrificial pillar structure22includes amorphous silicon, a wet etch process using hot trimethyl-2 hydroxyethyl ammonium hydroxide (“hot TMY”) or tetramethyl ammonium hydroxide (TMAH) may be used to remove the sacrificial pillar structures22. A memory opening25is formed in each volume from which each sacrificial pillar structure22is removed. In one embodiment, each of the memory openings25can be a rectangular memory opening having a same horizontal rectangular cross-sectional area that is invariant with translation along the vertical direction.

A laterally alternating sequence of memory openings25and dielectric pillar structures24can be formed within each line trench49. A two-dimensional array of memory openings25can be interlaced with a two-dimensional array of dielectric pillar structures24. In one embodiment, the two-dimensional array of memory openings25can be a periodic two-dimensional array having a two-dimensional periodicity, and the two-dimensional array of dielectric pillar structures24can be a periodic two-dimensional array having the same two-dimensional periodicity as the periodic two-dimensional array of memory openings25.

Referring toFIGS. 10A-10C, continuous material layers can be sequentially deposited in the memory openings25. The continuous material layers can include, for example, an optional selector-side spacer layer57, a selector material layer56, an optional intermediate spacer layer55, a memory material layer54, an optional memory-side spacer layer52, and a vertical bit line60. The set of the selector-side spacer layer57, the selector material layer56, the intermediate spacer layer55, the memory material layer54, and the memory-side spacer layer52constitutes a memory film50.

In general, the memory material layer54can include any non-volatile memory material that can provide two distinct resistive states depending on the history of a bias voltage thereacross. In one embodiment, the memory material layer54can include a resistive memory material that can be employed in resistive random access memory devices. For example, the memory material layer54can include a transition metal oxide material that provides different resistive states through oxygen vacancy migration (such as hafnium oxide, tantalum oxide, tungsten oxide), a transition metal oxide material that functions as a reversible thermo-chemical fuse/antifuse (such as nickel oxide), an electrochemical migration-based programmable metallization material, which is also referred to as a conductive bridging material (such as copper-doped silicon dioxide glass, silver-doped germanium selenide, or silver-doped germanium sulfide), a Schottky barrier material or a tunnel barrier material (such as a memristor material, a barrier modulated cell/vacancy-modulated conductive oxide material (e.g., titanium oxide), or a praseodymium-calcium-manganese oxide (PCMO) material), a phase change memory material (such as a chalcogenide alloy, e.g., a germanium-antimony-telluride compound), a superlattice structure that exhibits multiple resistive states through interfacial effects (such as a superlattice of chalcogenide alloys), a tunneling magnetoresistance material (such as a layer stack of a CoFeB/MgO/CoFeB), or a Mott transition-based metal-insulator transition (MIT) switching device. The thickness of the memory material layer54may be suitably selected, and may be in a range from2nm to50nm, such as from 5 nm to 20 nm, although lesser and greater thicknesses can also be employed.

In one embodiment, the memory material layer54includes a resistive memory material. In one embodiment, the memory material layer54includes the phase change memory material. As used herein, a “phase change memory material” refers to a material having at least two different phases providing different resistivity. The at least two different phases can be provided, for example, by controlling the rate of cooling from a heated state to provide an amorphous state having a higher resistivity and a polycrystalline state having a lower resistivity. In this case, the higher resistivity state of the phase change memory material can be achieved by faster quenching of the phase change memory material after heating to an amorphous state, and the lower resistivity state of the phase change memory material can be achieved by slower cooling of the phase change memory material after heating to the amorphous state

Exemplary phase change memory materials include, but are not limited to, germanium antimony telluride compounds such as Ge2Sb2Te5(GST), germanium antimony compounds, indium germanium telluride compounds, aluminum selenium telluride compounds, indium selenium telluride compounds, and aluminum indium selenium telluride compounds. These compounds (e.g., compound semiconductor material) may be doped (e.g., nitrogen doped GST) or undoped. Thus, the phase change memory material layer can include, and/or can consist essentially of, a material selected from a germanium antimony telluride compound, a germanium antimony compound, an indium germanium telluride compound, an aluminum selenium telluride compound, an indium selenium telluride compound, or an aluminum indium selenium telluride compound. The thickness of the phase change memory material layer can be in a range from 1 nm to 60 nm, such as from 10 nm to 50 nm and/or from 20 nm to 40 nm, although lesser and greater thicknesses can also be employed.

The selector material layer56includes a non-Ohmic material that provides electrical connection of electrical isolation depending on the magnitude and/or the polarity of an externally applied voltage bias thereacross. In one embodiment, the selector material layer56includes at least one threshold switch material layer. The at least one threshold switch material layer includes any suitable threshold switch material which exhibits non-linear electrical behavior, such as an ovonic threshold switch material or volatile conductive bridge. In another embodiment, the selector material layer56includes at least one non-threshold switch material layer, such as a tunneling selector material or diode materials (e.g., materials for p-n semiconductor diode, p-i-n semiconductor diode, Schottky diode or metal-insulator-metal diode). As used herein, an ovonic threshold switch (OTS) is a device that does not crystallize in a low resistance state under a voltage above the threshold voltage, and reverts back to a high resistance state when not subjected to a voltage above the threshold voltage across the OTS material layer. As used herein, an “ovonic threshold switch material” refers to a material that displays a non-linear resistivity curve under an applied external bias voltage such that the resistivity of the material decreases with the magnitude of the applied external bias voltage. In other words, an ovonic threshold switch material is non-Ohmic, and becomes more conductive under a higher external bias voltage than under a lower external bias voltage.

An ovonic threshold switch material (OTS material) can be non-crystalline (for example, amorphous) in a high resistance state, and can remain non-crystalline (for example, remain amorphous) in a low resistance state during application of a voltage above its threshold voltage across the OTS material. The OTS material can revert back to the high resistance state when the high voltage above its threshold voltage is lowered below a critical holding voltage. Throughout the resistive state changes, the ovonic threshold switch material can remain non-crystalline (e.g., amorphous). In one embodiment, the ovonic threshold switch material can comprise a chalcogenide material which exhibits hysteresis in both the write and read current polarities. The chalcogenide material may be a GeTe compound or a Ge—Se compound doped with a dopant selected from As, N, and C, such as a Ge—Se—As compound semiconductor5material. The ovonic threshold switch material layer can include a selector material layer56which contains any ovonic threshold switch material. In one embodiment, the selector material layer56can include, and/or can consist essentially of, a GeSeAs alloy, a GeTeAs, a GeSeTeSe alloy, a GeSe alloy, a SeAs alloy, a GeTe alloy, or a SiTe alloy.

In one embodiment, the material of the selector material layer56can be selected such that the resistivity of the selector material layer56decreases at least by two orders of magnitude (i.e., by more than a factor of 100) upon application of an external bias voltage that exceeds a critical bias voltage magnitude (also referred to as threshold voltage). In one embodiment, the composition and the thickness of the selector material layer56can be selected such that the critical bias voltage magnitude can be in a range from 1 V to 6 V, although lesser and greater voltages can also be employed for the critical bias voltage magnitude. The thickness of the selector material layer56can be, for example, in a range from 1 nm to 50 nm, such as from 5 nm to 25 nm, although lesser and greater thicknesses can also be employed.

Each of the selector-side spacer layer57, the intermediate spacer layer55, and the memory-side spacer layer52is optional, and can include a material that can control conduction of electrical current thereacross at a suitable level. For example, each of the selector-side spacer layer57, the intermediate spacer layer55, and the memory-side spacer layer52can independently include any material selected from a conductive metallic nitride such as titanium nitride, tungsten or tungsten nitride, a conductive metallic carbide, selenium, tellurium, doped silicon, germanium, an elemental metal such as silver, copper, or aluminum, amorphous carbon or diamondlike carbon (DLC), carbon nitride, an intermetallic alloy or an alloy of at least one metallic element and at least one non-metallic element, an alloy of any of the preceding materials, and/or a layer stack including a plurality of the preceding materials. Some of the above materials, such as carbon, may also function as a thermally insulating material. Each of the selector-side spacer layer57, the intermediate spacer layer55, and the memory-side spacer layer52can have a thickness in a range from 1 nm to 30 nm, such as from 3 nm to 10 nm, although lesser and greater thicknesses can be employed for each of the selector-side spacer layer57, the intermediate spacer layer55, and the memory-side spacer layer52.

The vertical bit line60includes at least one conductive material, which can comprise at least one metallic material or at least one heavily doped (conductive) semiconductor material. For example, the vertical bit line60can include a metallic nitride liner60A including a metallic nitride material (such as TiN, TaN, or WN) and a metallic fill material portion60B including a metallic fill material (such as W, Cu, Co, Ru, or Mo).

A planarization process can be performed to remove portions of the various material layers from above the horizontal plane including the top surface of the insulating cap strips70. The planarization process can include, for example, a recess etch process that indiscriminately etches the various material layers of the memory film50and the vertical bit line60. Remaining material portions of the memory film50and the vertical bit line60within each memory openings25can have top surfaces within the horizontal plane including the top surface of the insulating cap strips70. The set of all material portions that fills a memory opening25is herein referred to as a memory opening fill structure58, which can include a memory film50and a vertical bit line60.

Generally, laterally alternating sequences of memory opening fill structures58and dielectric pillar structures24are formed within the line trenches49. Each of the memory opening fill structures58comprises a respective vertical bit line60. A memory material portion (such as a respective portion of the memory material layer54) is formed between each laterally neighboring pair of a sacrificial material strip42and a vertical bit line60. A lateral extent of an overlap between the memory material portion (such as a respective portion of the memory material layer54) and a most proximal one of the sacrificial material strips42along the first horizontal direction hd1can be the same as the dimension along the first horizontal direction hd1of a tip portion of the sacrificial material strip42that contacts the memory film50(such as the selector-side spacer layer57). As such, the lateral extent of an overlap between the memory material portion and a most proximal one of the sacrificial material strips42along the first horizontal direction hd1can be less than a lateral extent of the most proximal one of the memory opening fill structures58along the first horizontal direction hd1.

Referring toFIGS. 11A and 11B, backside cavities69are formed in portions of the line trenches49located in the staircase region300. In one embodiment, portions of the line trenches49may be filled with the same dielectric fill material as the dielectric pillar structures24, and can be removed by a combination of lithographic patterning and an anisotropic etch process. Alternatively, the sacrificial fill material of the sacrificial rail structures22R can be protected in the staircase region by a patterned etch mask layer that covers the staircase region during etch processes that remove the material of the sacrificial rail structures22R. Remaining portions of the sacrificial rail structures22R can be removed after formation of the memory opening fill structures58to form the backside cavities69. Optionally, additional backside cavities may be formed within the memory array region100within areas from which material portions filling the line trenches49are removed. Such material portions that are removed to form the additional backside trenches may include remaining portions of the sacrificial rail structures22R or dielectric material portions having the same material composition as the dielectric pillar structures24. Sidewalls of each layer within the vertically alternating stacks (32,42) can be physically exposed around the backside cavities69. Optionally, a top surface of the insulating material layer10may be physically exposed at the bottom of each backside cavity69.

Referring toFIGS. 12A-12C, backside recesses43are formed in volumes from which the sacrificial material strips42are removed. The removal of the second material of the sacrificial material strips42can be selective to the first material of the insulating strips32, the material of the retro-stepped dielectric material portion65, the insulating material layer10, and the material of the outermost material portions of the memory opening fill structures58. In case the sacrificial material strips42include silicon nitride, a wet etch process employing hot phosphoric acid can be employed to form the backside recesses43.

For example, the isotropic etch process employed to form the backside recesses43can employ an etch chemistry that is selective to the material of the selector-side spacer layer57. Each backside recess43can be a laterally extending cavity having a lateral dimension that is greater than the vertical extent of the cavity. In other words, the lateral dimension of each backside recess43can be greater than the height of the backside recess43. A plurality of backside recesses43can be formed in the volumes from which the second material of the sacrificial material strips42is removed. The memory openings in which the memory opening fill structures58are formed are herein referred to as front side openings or front side cavities in contrast with the backside recesses43. In one embodiment, each backside recess43can define a space for receiving a respective word line of a three-dimensional memory device.

Each of the plurality of backside recesses43can extend substantially parallel to the top surface of the substrate9. A backside recess43can be vertically bounded by a top surface of an underlying insulating strip32and a bottom surface of an overlying insulating strip32. In one embodiment, each backside recess43can have a uniform height throughout.

Referring toFIGS. 13A-13F, a barrier layer44can be optionally formed. The barrier layer44, if present, comprises a conductive material, a semiconducting material, or a dielectric material that limits the electrical current through a neighboring memory material portion. The barrier layer44can be formed in the backside recesses43and on a sidewall of the backside cavity69. The barrier layer44can be formed directly on horizontal surfaces of the insulating strips32and sidewalls of the memory opening fill structures58within the backside recesses43. In one embodiment, the barrier layer44can be formed by a conformal deposition process such as atomic layer deposition (ALD). The barrier layer44can include a material selected from a conductive metallic nitride such as titanium nitride, tungsten or tungsten nitride, a conductive metallic carbide, selenium, tellurium, doped silicon, germanium, an elemental metal such as silver, copper, or aluminum, amorphous carbon or diamondlike carbon (DLC), carbon nitride, an intermetallic alloy or an alloy of at least one metallic element and at least one non-metallic element, an alloy of any of the preceding materials, and/or a layer stack including a plurality of the preceding materials. The thickness of the barrier layer44can be in a range from 1 nm to 15 nm, such as 2 to 6 nm, although lesser and greater thicknesses can also be employed.

At least one metallic material can be subsequently deposited in remaining volumes of the backside recesses43. The at least one metallic material can include a metallic barrier layer and a metallic fill material. The metallic barrier layer includes an electrically conductive metallic material that can function as a diffusion barrier layer and/or adhesion promotion layer for a metallic fill material to be subsequently deposited. The metallic barrier layer can include a conductive metallic nitride material such as TiN, TaN, WN, or a stack thereof, or can include a conductive metallic carbide material such as TiC, TaC, WC, or a stack thereof. In one embodiment, the metallic barrier layer can be deposited by a conformal deposition process such as chemical vapor deposition (CVD) or atomic layer deposition (ALD). The thickness of the metallic barrier layer can be in a range from 2 nm to 8 nm, such as from 3 nm to 6 nm, although lesser and greater thicknesses can also be employed. In one embodiment, the metallic barrier layer can consist essentially of a conductive metal nitride such as TiN.

The metal fill material can be subsequently deposited in remaining volumes of the plurality of backside recesses43, on the sidewalls of the at least one the backside cavity69, and over the top surface of the insulating cap strips70to form a metallic fill material layer. The metallic fill material can be deposited by a conformal deposition method, which can be, for example, chemical vapor deposition (CVD), atomic layer deposition (ALD), electroless plating, electroplating, or a combination thereof. In one embodiment, the metallic fill material layer can consist essentially of at least one elemental metal. The at least one elemental metal of the metallic fill material layer can be selected, for example, from tungsten, cobalt, ruthenium, titanium, and tantalum. In one embodiment, the metallic fill material layer can consist essentially of a single elemental metal. In one embodiment, the metallic fill material layer can be deposited employing a fluorine-containing precursor gas such as WF6. In one embodiment, the metallic fill material layer can be a tungsten layer including a residual level of fluorine atoms as impurities. The metallic fill material layer is spaced from the insulating strips32and the memory opening fill structures58by the metallic barrier layer, which is a metallic barrier layer that blocks diffusion of fluorine atoms therethrough.

A plurality of electrically conductive strips46can be formed in the plurality of backside recesses43, and a continuous electrically conductive material strip can be formed on the sidewalls of each backside cavity69and over the insulating cap strips70. Each electrically conductive strip46includes a portion of the metallic barrier layer and a portion of the metallic fill material layer that are located between a vertically neighboring pair of dielectric material layers such as a pair of insulating strips32. The continuous electrically conductive material strip includes a continuous portion of the metallic barrier layer and a continuous portion of the metallic fill material layer that are located in the backside cavities69or above the insulating cap strips70. Each sacrificial material strip42can be replaced with an electrically conductive strip46. An elongated void is present in the portion of each backside cavity69that is not filled with the barrier layer44and the continuous electrically conductive material strip.

The deposited metallic material of the continuous electrically conductive material strip is etched back from the sidewalls of each backside cavity69and from above the insulating cap strips70, for example, by an isotropic wet etch, an anisotropic dry etch, or a combination thereof. Each remaining portion of the deposited metallic material in the backside recesses43constitutes an electrically conductive strip46. Each electrically conductive strip46can be a conductive line structure. Thus, the sacrificial material strips42are replaced with the electrically conductive strips46.

Each electrically conductive strip46can function as a word line. In other words, each electrically conductive strip46can be a word line that functions as a common electrode for the plurality of vertical memory devices.

In one embodiment, the removal of the continuous electrically conductive material strip can be selective to the material of the barrier layer44. In this case, a horizontal portion of the barrier layer44can be present at the bottom of each backside cavity69. In another embodiment, the removal of the continuous electrically conductive material strip may not be selective to the material of the barrier layer44or, the barrier layer44may not be employed.

The electrically conductive strips46can be formed with serration such that a serrated portion (i.e., a protruding portion) laterally extends toward each neighboring memory opening fill structure58. The width of the areal overlap between a vertical sidewall of a serrated portion of an electrically conductive strip46and a neighboring memory opening fill structure58is the same as the width of the vertical sidewall of the serrated portion of the electrically conductive strip46, and is less than the lateral dimension of the neighboring memory opening fill structure58along the first horizontal direction hd1. In one embodiment, each electrically conductive strip46can comprise a pair of laterally undulating sidewalls that provides the feature of serration. Each memory material portion can be formed as a memory material layer54within a respective one of the rectangular memory openings25.

In one embodiment, the center portion of the dielectric pillar structure24has a first lengthwise lateral extent LLE1(i.e., a lateral distance between neighboring pairs of memory opening fill structures58in a line trench49) along the first horizontal direction hd1, and each laterally protruding portion within the two vertical stacks of laterally protruding portions of the dielectric pillar structures24has a second lengthwise lateral extent LLE2along the first horizontal direction that is greater than the first lengthwise lateral extent LLE1.

Referring toFIGS. 14A and 14B, an insulating material layer can be formed in the backside cavities69and over the insulating cap strips70by a conformal deposition process. Exemplary conformal deposition processes include, but are not limited to, chemical vapor deposition and atomic layer deposition. The insulating material layer includes an insulating material such as silicon oxide, silicon nitride, a dielectric metal oxide, an organosilicate glass, or a combination thereof. In one embodiment, the insulating material layer can include silicon oxide. The insulating material layer can be formed, for example, by low pressure chemical vapor deposition (LPCVD) or atomic layer deposition (ALD). The horizontal portion of the insulating material layer overlying the insulating cap strips70constitute a contact-level dielectric layer80. Each portion of the insulating material layer in the backside cavities69constitutes a backside dielectric fill structure76.

Line trenches laterally extending along the second horizontal direction hd2can be formed through the contact-level dielectric layer in areas that overlie the vertical bit lines60. At least one conductive material can be deposited in the line trenches to form horizontally extending conductive lines, which are herein referred to as global bit lines98. The global bit lines98can laterally extend along the second horizontal direction hd2, and can contact a respective subset of the vertical bit lines60. In an illustrative example, each global bit line98can contact a set of vertical bit line60that are located in every other line trench49and aligned along the second horizontal direction hd2.

Word line contact via structures86can be formed on the electrically conductive layers46through the contact level dielectric layer80, and through the retro-stepped dielectric material portion65. The word line contact via structures86provide electrical contact to each of the electrically conductive lines46, which can function as word lines.

Referring toFIGS. 15A and 15B, a second exemplary structure according to a second embodiment of the present disclosure is illustrated, which can be the same as the first exemplary structure illustrated inFIGS. 8A and 8B.

Referring toFIGS. 16A and 16B, the processing steps ofFIGS. 9A and 9Bcan be performed on the second exemplary structure. Specifically, rectangular memory openings25can be formed by removing the sacrificial pillar structures22selective to the dielectric pillar structures24, the insulating strips32, and the sacrificial material strips42. The second exemplary structure at this processing step can be the same as the first exemplary structure at the processing step ofFIGS. 9A and 9B.

Referring toFIGS. 17A and 17B, surface portions of the sacrificial material strips42can be laterally recessed around each memory opening25. Each memory opening25can be laterally expanded at each level of the sacrificial material strips42to include two vertical stacks of lateral recesses25R. Each lateral recess25R has an areal overlap with an underlying insulating strip32and with an overlying insulating strip32and/or an overlying insulating cap strip70. The surface portions of the sacrificial material strips42can be laterally recessed by an isotropic etch process that etches the material of the sacrificial material strips42selective to the materials of the insulating strips32, the insulating cap strips70, the dielectric pillar structures24, and the insulating material layer10. For example, if the sacrificial material strips42include silicon nitride, a wet etch process employing hot phosphoric acid, a mixture of hydrofluoric acid and glycerol at an elevated temperature, or a mixture of ethylene glycol, acetic acid, nitric acid, and ammonium fluoride at an elevated temperature may be employed to laterally recess the sacrificial material strips42selective to the insulating strips32, the insulating cap strips70, and the sacrificial pillar structures22.

The lateral recess distance of the isotropic etch process at this processing step may be less than the lateral etch distance of the isotropic etch process at the processing steps ofFIGS. 7A and 7B. In this case, the width of each physically exposed sidewall of the sacrificial material strips42that borders a respective lateral recess25R can be less than the maximum lateral dimension of the memory opening25that the respective lateral recess25R belongs to. In one embodiment, the lateral recess distance of the isotropic etch process at this processing step may be in a range from 5 nm to 200 nm, such as from 10 nm to 100 nm, although lesser and greater lateral etch distances can also be employed.

Referring toFIGS. 18A and 18B, an optional continuous memory-side spacer layer52L and a continuous memory material layer54L can be formed by conformal deposition processes. The continuous memory-side spacer layer52L can have the same material composition as, and the same thickness as, the memory-side spacer layer52described above. The continuous memory material layer54L can have the same material composition as the memory material layer54. The thickness of the continuous memory material layer54L can be selected such that the entire volume of each lateral recess25R of the memory openings25is filled within the combination of the continuous memory-side spacer layer52L and the continuous memory material layer54L. Each of the continuous memory-side spacer layer52L and the continuous memory material layer54L can be formed as a respective single continuous layer that extends over the insulating cap strips70and extends into each of the memory openings25.

Referring toFIGS. 19A and 19B, an anisotropic etch process can be performed to remove portions of the continuous memory-side spacer layer52L and the continuous memory material layer54L that are not masked by an overlying material portion (which can be an insulating cap strip70or an insulating strip32). The continuous memory-side spacer layer52L is divided into a plurality of memory-side spacer layers52located within a respective one of the lateral recesses25R. The continuous memory material layer54L is divided into a plurality of memory material portions154. Each memory material potion154is a memory material portion that is formed in a respective one of the lateral recesses25R.

Referring toFIGS. 20A and 20B, an intermediate spacer layer55, a selector material layer56, and a selector-side spacer layer57can be sequentially formed at a periphery of the unfilled volume of each memory opening25. Each of the intermediate spacer layer55, the selector material layer56, and the selector-side spacer layer57can have the same thickness as, and the same material composition as, the in the first exemplary structure of the first embodiment. At least one conductive material can be deposited within each remaining volume of the memory openings25on the inner sidewalls of the selector-side spacer layer57(or on the inner sidewalls of the selector material layer56in case the selector-side spacer layer57is omitted). Portions of the at least one conductive material, the intermediate spacer layer55, the selector material layer56, and the selector-side spacer layer57that overlie the horizontal plane including the top surfaces of the insulating cap strips70can be removed by a planarization process. Each remaining portion of the at least one conductive material constitutes a vertical bit line60.

Each contiguous combination of a memory-side spacer layer52, a memory material portion154, an intermediate spacer layer55, a selector material layer56, and a selector-side spacer layer57constitutes a memory film50. The set of all material portions that fills a memory opening25is herein referred to as a memory opening fill structure58, which can include a memory film50and a vertical bit line60. Each memory opening fill structure58can have a first lateral extent LE1along the first horizontal direction hd1. Each memory material portion154can have a second lateral extent LE2along the first horizontal direction hd1that is less than first lateral extent LE1.

Laterally alternating sequences of memory opening fill structures58and dielectric pillar structures24are formed within the line trenches49. Each of the memory opening fill structures58comprises a respective vertical bit line60. A memory material portion154is formed between each laterally neighboring pair of a sacrificial material strip42and a vertical bit line60. A lateral extent of an overlap between the memory material portion and a most proximal one of the sacrificial material strips42along the first horizontal direction hd1(which can be the second lateral extend LE2) is less than a lateral extent of the most proximal one of the memory opening fill structures58along the first horizontal direction hd1(which can be the first lateral extend LE1). A selector material portion comprising a portion of a selector material layer56may be located between each laterally neighboring pair of a sacrificial material strip42and a vertical bit line60.

Referring toFIGS. 21A-21D, the processing steps ofFIGS. 11A and 11B, 12A-12C, and13A-13F can be subsequently performed to replace each sacrificial material strip42within an electrically conductive strip46or a combination of a portion of a barrier layer44and an electrically conductive strip46.

In one embodiment, the center portion of the dielectric pillar structure24has a first lengthwise lateral extent LLE1(i.e., a lateral distance between neighboring pairs of memory opening fill structures58in a line trench49) along the first horizontal direction hd1, and each laterally protruding portion within the two vertical stacks of laterally protruding portions of the dielectric pillar structures24has a second lengthwise lateral extent LLE2along the first horizontal direction that is greater than the first lengthwise lateral extent LLE1. The configuration ofFIG. 21Bmakes the distance LLE2between adjacent phase change memory material portions154longer, which lessens a thermal disturb effect between phase change memory material portions154.

Referring toFIGS. 22A and 22B, a third exemplary structure according to a third embodiment of the present disclosure is illustrated, which can be the same as the first exemplary structure illustrated inFIGS. 8A and 8B.

Referring toFIGS. 23A and 23B, the processing steps ofFIGS. 9A and 9Bcan be performed on the second exemplary structure. Specifically, rectangular memory openings25can be formed by removing the sacrificial pillar structures22selective to the dielectric pillar structures24, the insulating strips32, and the sacrificial material strips42. The third exemplary structure at this processing step can be the same as the first exemplary structure at the processing step ofFIGS. 9A and 9B.

Referring toFIGS. 24A and 24B, the processing stepsFIGS. 17A and 17Bcan be performed to form lateral recesses25R by laterally recessing surface portions of the sacrificial material strips42around each memory opening25. Each memory openings25can be laterally expanded at each level of the sacrificial material strips42to include two vertical stacks of lateral recesses25R. The third exemplary structure at this processing step can be the same as the second exemplary structure at the processing steps ofFIGS. 17A and 17B.

Referring toFIGS. 25A and 25B, continuous material layers can be sequentially deposited in the memory openings25. The continuous material layers can include, for example, a continuous selector-side spacer layer57L, a continuous selector material layer56L, a continuous intermediate spacer layer55L, and a continuous memory material layer54L. The continuous selector-side spacer layer57L can have the same material composition and the same thickness as the selector-side spacer layer57described above. The continuous selector material layer56L can have the same material composition and the same thickness as the selector material layer56described above. The continuous intermediate spacer layer55L can have the same material composition and the same thickness as the intermediate spacer layer55described above. The continuous memory material layer54L can have the same material composition and the same thickness as the memory material layer54described above.

Referring toFIGS. 26A and 26B, an anisotropic etch process can be performed to remove portions of the continuous selector-side spacer layer57L, the continuous selector material layer56L, the continuous intermediate spacer layer55L, and the continuous memory material layer54L that are not masked by an overlying material portion (which can be an insulating cap strip70or an insulating strip32).

The continuous selector-side spacer layer57L is divided into a plurality of selector-side spacer layers157located within a respective one of the lateral recesses25R. The continuous selector material layer56L is divided into a plurality of selector material layers156located within a respective one of the lateral recesses25R. The continuous intermediate spacer layer55L is divided into a plurality of intermediate spacer layers55located within a respective one of the lateral recesses25R. The continuous memory material layer54L is divided into a plurality of memory material portions154located within a respective one of the lateral recesses25R. Each memory material potion154is formed in a respective one of the lateral recesses25R. Each unfilled volume of a memory opening25can have a rectangular horizontal cross-sectional shape that is invariant with translation along the vertical direction.

In one embodiment, the selector material portion156is clam-shaped, encloses a respective one of the memory material portions154, and is located between a respective laterally neighboring pair of a vertical bit line60and a sacrificial material strip42.

Referring toFIGS. 27A and 27B, a memory-side spacer layer52can be sequentially formed at a periphery of the unfilled volume of each memory opening25. The memory-side spacer layer52can have the same material composition and the same thickness as in the first exemplary structure. At least one conductive material can be deposited within each remaining volume of the memory openings25on the inner sidewalls of the memory-side spacer layer52(or on the inner sidewalls of a set of material portions including a selector-side spacer layer157, a selector material layer156, an intermediate spacer layer155, a memory material portion154in case the memory-side spacer layer52is omitted). Portions of the at least one conductive material and the memory-side spacer layer52that overlie the horizontal plane including the top surfaces of the insulating cap strips70can be removed by a planarization process. Each remaining portion of the at least one conductive material constitutes a vertical bit line60.

Each contiguous combination of selector-side spacer layers157, selector material layers156, intermediate spacer layers155, memory material portions154, and a memory-side spacer layer52constitutes a memory film50. The set of all material portions that fills a memory opening25is herein referred to as a memory opening fill structure58, which can include a memory film50and a vertical bit line60. Each memory opening fill structure58can have a first lateral extent LE1along the first horizontal direction hd1. Each memory material portion154can have a second lateral extent LE2along the first horizontal direction hd1that is less than first lateral extent LE1.

Laterally alternating sequences of memory opening fill structures58and dielectric pillar structures24are formed within the line trenches49. Each of the memory opening fill structures58comprises a respective vertical bit line60. A memory material portion (such as a memory material portion154) is formed between each laterally neighboring pair of a sacrificial material strip42and a vertical bit line60. A lateral extent of an overlap between the memory material portion and a most proximal one of the sacrificial material strips42along the first horizontal direction hd1(which can be the second lateral extend LE2) is less than a lateral extent of the most proximal one of the memory opening fill structures58along the first horizontal direction hd1(which can be the first lateral extend LE1). A selector material portion156may be located between each laterally neighboring pair of a sacrificial material strip42and a vertical bit line60.

Referring toFIGS. 28A-28D, the processing steps ofFIGS. 11A and 11B, 12A-12C, and13A-13F can be subsequently performed to replace each sacrificial material strip42within an electrically conductive strip46or a combination of a portion of a barrier layer44and an electrically conductive strip46.

In one embodiment, the center portion of the dielectric pillar structure24has a first lengthwise lateral extent LLE1(i.e., a lateral distance between neighboring pairs of memory opening fill structures58in a line trench49) along the first horizontal direction hd1, and each laterally protruding portion within the two vertical stacks of laterally protruding portions of the dielectric pillar structures24has a second lengthwise lateral extent LLE2along the first horizontal direction that is greater than the first lengthwise lateral extent LLE1.

Referring to all drawings and according to various embodiments of the present disclosure, a three-dimensional memory device is provided, which comprises: vertically alternating stacks of insulating strips32and electrically conductive strips46that overlie a substrate9and are laterally spaced apart from each other by line trenches49that laterally extend along a first horizontal direction hd1, and laterally alternating sequences of memory opening fill structures58and dielectric pillar structures24located within a respective one of the line trenches49. Each memory opening fill structure58comprises a respective vertical bit line60and a memory material portion (54,154). The memory material portion (54,154) is located between the vertical bit line60and a respective electrically conductive strip46. The insulating strips32and the electrically conductive strips46laterally extend along the first horizontal direction hd1, and the vertically alternating stacks (32,46) are laterally spaced apart along a second horizontal direction hd2that is perpendicular to the first horizonal direction hd1. A lateral extent of an overlap between the memory material portion(54,154) and a most proximal one of the electrically conductive strips46along the first horizontal direction hd1is less than a lateral extent along the first horizontal direction hd1of the memory opening fill structure58containing the memory material portion (54,154).

In the first embodiment illustrated inFIG. 13B, the electrically conductive strips46comprise serrated electrically conductive strips. Each of the serrated electrically conductive strips46comprises a pair of laterally undulating sidewalls, and each undulating sidewall of the electrically conductive strips46comprises a lateral repetition of recessed segments contacting a respective one of the dielectric pillar structures24, and comprises laterally protruding segments contacting a respective one of the memory opening fill structures58. Each laterally protruding segment has a lateral extend that is smaller than a lateral extent of the memory opening fill structure58.

In one embodiment, each of the dielectric pillar structures24comprises: a center portion extending from the substrate9to a height of topmost electrically conductive strips of the vertically alternating stacks (32,46) and contacting a respective subset of the insulating strips32of the vertically alternating stacks (32,46); and two vertical stacks of laterally protruding portions (i.e., wing-shaped portions) that contact a respective subset of the recessed segments of the undulating sidewalls of the electrically conductive strips46.

In one embodiment, each of the dielectric pillar structures24in the respective one of the line trenches49has a greater lateral extent along the second horizontal direction hd2than each memory opening fill structure58in the same line trench at each level of the electrically conductive strips46, and has a same lateral extent along the second horizontal direction hd2as each memory opening fill structure58in the same line trench49.

In one embodiment, each of the dielectric pillar structures24comprises four vertically-extending convex surfaces at each level of the electrically conductive strips46.

In one embodiment, each recessed segment of the electrically conductive strips46is adjoined to a respective one of the protruding segments of the electrically conductive strips46via a concave sidewall of a respective one of the electrically conductive strips46.

In one embodiment, the memory material portions (54,154) comprise phase change memory material portions, and the electrically conductive strips46comprise word lines.

In one embodiment, each of the memory opening fill structures58comprises a selector material layer56that laterally surrounds the vertical bit line60.

Referring toFIGS. 21B and 28Bof the second and third embodiments of the present disclosure, the vertical bit line60in a respective one of the memory opening fill structures58has a pair of first straight sidewalls extending along the first horizontal direction hd1and a pair of second straight sidewalls extending along the second horizontal direction hd2(i.e., having a rectangular horizontal cross-sectional shape); and a lateral extent of each vertical bit line60along the first horizontal direction hd1is greater than a lateral extent of any one of the memory material portions154in the same memory opening fill structure58.

In one embodiment, each of the memory material portions154in a respective one of the memory fill opening structures58has a trapezoidal horizontal cross-sectional profile in which a width (measured along the first horizontal direction hd1) of a respective memory material portion154decreases with a lateral distance from a most proximal one of the electrically conductive strips46toward a most proximal one of the vertical bit lines60in the same memory opening fill structure58.

In one embodiment, each of the memory opening fill structures58further comprises a memory-side spacer layer52that laterally surrounds a respective vertical bit line60.

In one embodiment, each of the memory opening fill structures58further comprises a selector material portion (which may be a discrete selector material portion156or a portion of a selector material layer56) is disposed between each laterally neighboring pair of the memory material portion154and the vertical bit line60.

In one embodiment, the selector material portion comprises a portion of a selector material layer56provided within a respective one of the memory opening fill structures58.

In one embodiment, the selector material portion156is clam-shaped, encloses a respective one of the memory material portions154, and is located between a respective laterally neighboring pair of a vertical bit line60and an electrically conductive strip46.

The lateral extent of each region in which an outer surface of a memory material potion (54,154) has an areal overlap (as measured in a vertical plane) with a most proximal sidewall surface of the electrically conductive strips46is less than the maximum lateral extent of a vertical bit line60adjacent to the memory material portion (54,154). By reducing the overlap area between neighboring pairs of a memory material potion and an electrically conductive strip (i.e., word line)46, the reset current density in a phase change memory material is increased. This causes more intense Joule heating and more rapidly elevates temperature of a phase change memory material near the overlap area with an electrically conductive layer46. The transition from a low resistive crystalline phase to a high resistive amorphous phase occurs faster due the thermal energy, and enables the device operation quicker. The local current density increase only in the phase change memory material may also reduce the supply voltage for the memory device chip. This reduces the device power consumption and reduces the required size of the driver transistor(s). Furthermore, this also makes the distance between adjacent phase change memory material portions, which lessens the thermal disturb effect between the adjacent phase change memory material portions.