SEMICONDUCTOR MEMORY DEVICE

A memory plane region includes a first structure and a second structure having conductive layers, and includes a first memory region to a third memory region, a first region between the first memory region and the second memory region, and a second region between the second memory region and the third memory region. The first structure comprises first via contact electrodes in the first region. The second structure comprises second via contact electrodes in the second region. The first via contact electrodes are electrically connected to transistors provided at positions where the first structure and the first region overlap, and where the second structure and the first region overlap. The second via contact electrodes are electrically connected to transistors provided at positions where the first structure and the second region overlap, and where the second structure and the second region overlap.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is based upon and claims the benefit of Japanese Patent Application No. 2022-150375, filed on Sep. 21, 2022, the entire contents of which are incorporated herein by reference.

FIELD

Background

The present embodiment relates to a semiconductor memory device.

Description of the Related Art

There is known a semiconductor memory device comprising: a semiconductor substrate; a plurality of conductive layers stacked in a stacking direction intersecting a surface of this semiconductor substrate; a semiconductor layer facing these plurality of conductive layers; and a charge accumulating film provided between the conductive layers and the semiconductor layer. The charge accumulating film comprises a memory portion capable of storing data, such as an insulative charge accumulating film of the likes of silicon nitride (SiN) or a conductive charge accumulating film of the likes of a floating gate, for example.

DETAILED DESCRIPTION

A semiconductor memory device according to one embodiment comprises a first structure and a second structure. The first structure has a plurality of first conductive layers that are continuous in a first direction and are laminated in a laminating direction which intersects the first direction. The second structure has a plurality of second conductive layers that are continuous in the first direction, are laminated in the laminating direction, are aligned in a second direction which intersects the first direction and the laminating direction with respect to the first conductive layers, and are electrically independent from the first conductive layers.

A memory plane region, which includes the first structure and the second structure, includes a first memory region, a second memory region, a third memory region, a first region, and a second region. The first memory region, the second memory region, and the third memory region are aligned in the first direction and each include a plurality of semiconductor columns and a plurality of charge accumulating films. The plurality of semiconductor columns extend in the laminating direction.

A plurality of first transistors and a plurality of third transistors are provided in an opposite direction to the laminating direction with respect to the first structure. A plurality of second transistors and a plurality of fourth transistors are provided in an opposite direction to the laminating direction with respect to the second structure.

The second memory region is provided between the first memory region and the third memory region.

The first structure further comprises a plurality of first via contact electrodes that are provided in the first region, extend in the laminating direction, and are connected to at least a part of the plurality of first conductive layers. The second structure further comprises a plurality of second via contact electrodes that are provided in the second region, extend in the laminating direction, and are connected to at least a part of the plurality of second conductive layers.

A part of the plurality of first via contact electrodes are electrically connected to at least a part of the plurality of first transistors provided at a position where the first structure and the first region overlap, looking from the laminating direction. The other part of the plurality of first via contact electrodes are electrically connected to at least a part of the plurality of second transistors provided at a position where the second structure and the first region overlap, looking from the laminating direction,

A part of the plurality of second via contact electrodes are electrically connected to at least a part of the plurality of third transistors provided at a position where the first structure and the second region overlap, looking from the laminating direction. The other part of the plurality of second via contact electrodes are electrically connected to at least a part of the plurality of fourth transistors provided at a position where the second structure and the second region overlap, looking from the laminating direction.

Next, semiconductor memory devices according to embodiments will be described in detail with reference to the drawings. Note that the following embodiments are merely examples, and are not shown with the intention of limiting the present invention. Moreover, the following drawings are schematic, and, for convenience of description, a part of configurations, and so on, thereof will sometimes be omitted. Moreover, portions that are common to a plurality of embodiments will be assigned with the same symbols, and descriptions thereof sometimes omitted.

Moreover, when a “semiconductor memory device” is referred to in the present specification, it will sometimes mean a memory die, and will sometimes mean a memory system including a control die, of the likes of a memory chip, a memory card, or an SSD (Solid State Drive). Furthermore, it will sometimes mean a configuration including a host computer, of the likes of a smartphone, a tablet terminal, or a personal computer.

Moreover, in the present specification, when a first configuration is said to be “electrically connected” to a second configuration, the first configuration may be connected to the second configuration directly, or the first configuration may be connected to the second configuration via the likes of a wiring, a semiconductor member, or a transistor. For example, in the case of three transistors having been serially connected, the first transistor is still “electrically connected” to the third transistor even if the second transistor is in an OFF state.

Moreover, in the present specification, when a first configuration is said to be “electrically connected between” a second configuration and a third configuration, it will sometimes mean that the first configuration, the second configuration, and the third configuration are serially connected, and the second configuration is connected to the third configuration via the first configuration.

Moreover, in the present specification, when a circuit, or the like, is said to “make electrically continuous” two wirings, or the like, this will sometimes mean, for example, that this circuit, or the like, includes a transistor, or the like, that this transistor, or the like, is provided in a current path between the two wirings, and that this transistor, or the like, is in an ON state.

Moreover, in the present specification, a certain direction parallel to an upper surface of a substrate will be called an X direction, a direction parallel to the upper surface of the substrate and perpendicular to the X direction will be called a Y direction, and a direction perpendicular to the upper surface of the substrate will be called a Z direction.

Moreover, in the present specification, a direction intersecting the surface of the substrate will sometimes be called a stacking direction. Moreover, a direction lying along a certain plane intersecting the stacking direction will sometimes be called a first direction, and a direction intersecting the first direction along this plane will sometimes be called a second direction. The stacking direction may correspond to the Z direction, but need not do so. Moreover, the first direction and the second direction may correspond to either of the X direction and the Y direction, but need not do so.

Moreover, in the present specification, expressions such as “up” or “down” will be defined with reference to the substrate. For example, an orientation of moving away from the substrate along the above-described Z direction will be called up, and an orientation of coming closer to the substrate along the Z direction will be called down. Moreover, when a lower surface or a lower end is referred to for a certain configuration, this will be assumed to mean a surface or end portion on a substrate side of this configuration, and when an upper surface or an upper end is referred to for a certain configuration, this will be assumed to mean a surface or end portion on an opposite side to the substrate of this configuration. Moreover, a surface intersecting the X direction or the Y direction will be called a side surface, and so on.

Moreover, in the present specification, when the likes of a “width”, a “length”, or a “thickness” in a certain direction is referred to for a configuration, a member, and so on, this will sometimes mean a width, a length, or a thickness, and so on, in a cross section observed by the likes of SEM (Scanning Electron Microscopy) or TEM (Transmission Electron Microscopy), and so on.

First Embodiment

[Circuit Configuration of Memory Die MD]

FIG.1is a schematic circuit diagram showing a part of configurations of a memory die MD. As shown inFIG.1, the memory die MD comprises a memory cell array MCA and a peripheral circuit PC. As shown inFIG.1, the memory cell array MCA comprises a plurality of memory blocks BLK. These plurality of memory blocks BLK each comprise a plurality of string units SU. These plurality of string units SU each comprise a plurality of memory strings MS. One ends of these plurality of memory strings MS are respectively connected to the peripheral circuit PC via bit lines BL. Moreover, other ends of these plurality of memory strings MS are each connected to the peripheral circuit PC via a common source line SL.

The memory string MS comprises a drain side select transistor STD, a plurality of memory cells MC (memory transistors), and a source side select transistor STS. The drain side select transistor STD, the plurality of memory cells MC, and the source side select transistor STS are connected in series between the bit line BL and the source line SL. Hereafter, the drain side select transistor STD and the source side select transistor STS will sometimes simply be called select transistors (STD, STS).

The memory cell MC is a field effect type transistor. The memory cell MC comprises a semiconductor layer, a gate insulating film, and a gate electrode. The semiconductor layer functions as a channel region. The gate insulating film includes a charge accumulating film as a memory portion. A threshold voltage of the memory cell MC changes according to an amount of charge in the charge accumulating film. The memory cell MC stores one bit or a plurality of bits of data. Note that the gate electrodes of the plurality of memory cells MC corresponding to one memory string MS are respectively connected with word lines WL. These word lines WL are each commonly connected to all of the memory strings MS in one memory block BLK.

The select transistor (STD, STS) is a field effect type transistor. The select transistor (STD, STS) comprises a semiconductor layer, a gate insulating film, and a gate electrode. The semiconductor layer functions as a channel region. The gate electrodes of the select transistors (STD, STS) are respectively connected with select gate lines (SGD, SGS). One drain side select gate line SGD is commonly connected to all of the memory strings MS in one string unit SU. One source side select gate line SGS is commonly connected to all of the memory strings MS in one memory block BLK.

FIG.2is a schematic circuit diagram showing a part of configurations of the peripheral circuit PC. As shown inFIG.2, for example, the peripheral circuit PC comprises a row control circuit RowC. The row control circuit RowC comprises a plurality of block decode units blkd and a block decoder BLKD.

The plurality of block decode units blkd are provided correspondingly to the plurality of memory blocks BLK in the memory cell array MCA. The block decode unit blkd comprises a plurality of transistors TBLK. The plurality of transistors TBLKcorrespond to the plurality of word lines WL in the memory block BLK. The transistor TBLKis a field effect type NMOS transistor, for example. A drain electrode of the transistor TBLKis connected to the word line WL. A source electrode of the transistor TBLKis connected to a wiring CG. The wiring CG is connected to all of the block decode units blkd in the row control circuit RowC. A gate electrode of the transistor TBLKis connected to a signal supply line BLKSEL. A plurality of the signal supply lines BLKSEL are provided correspondingly to all of the block decode units blkd. Moreover, the signal supply line BLKSEL is connected to all of the transistors TBLKin the block decode unit blkd.

The block decoder BLKD decodes a block address during a read operation or write operation. Moreover, one of the plurality of signal supply lines BLKSEL is set to an “H” state and the remaining signal supply lines BLKSEL are set to an “L” state, depending on the block address that has been decoded.

FIG.3is a schematic circuit diagram showing a part of configurations of the peripheral circuit PC. As shown inFIG.3, for example, the peripheral circuit PC comprises a column control circuit ColC. The column control circuit ColC comprises: switch transistors BLS, BLBIAS that are connected to the bit line BL; a sense amplifier circuit SADL which is connected to the bit line BL via the switch transistor BLS; and a latch circuit XDL which is connected to the sense amplifier circuit SADL.

The switch transistors BLS, BLBIAS are field effect type NMOS transistors, for example. Drain electrodes of the switch transistors BLS, BLBIAS are connected to the bit line BL. A source electrode of the switch transistor BLS is connected to the sense amplifier circuit SADL. A source electrode of the switch transistor BLBIAS is connected to an unillustrated voltage supply line.

The sense amplifier circuit SADL comprises a sense circuit, a latch circuit, and a voltage transfer circuit. The sense circuit comprises a sense transistor and a data wiring. A gate electrode of the sense transistor is electrically connected to the bit line BL. A drain electrode of the sense transistor is connected to the data wiring. The sense transistor attains an ON state depending on voltage or current of the bit line BL. The data wiring is charged or discharged depending on an ON/OFF state of the sense transistor. The latch circuit latches data of “1” or “0” depending on voltage of the data wiring. The voltage transfer circuit makes the bit line BL electrically continuous with either of two voltage supply lines, depending on the data latched in the latch circuit.

The latch circuit XDL is electrically connected to the data wiring within the sense amplifier circuit SADL via a wiring DBUS. Data included in the latch circuit XDL is sequentially transferred to the sense amplifier circuit SADL or an unillustrated input/output control circuit.

[Structure of Memory Die MD]

FIG.4is a schematic exploded perspective view showing an example of configuration of the memory die MD. As shown inFIG.4, the memory die MD comprises: a chip CMon a memory cell array MCA side; and a chip CPon a peripheral circuit PC side.

An upper surface of the chip CMis provided with a plurality of external pad electrodes PXconnectable to unillustrated bonding wires. Moreover, a lower surface of the chip CMis provided with a plurality of bonding electrodes PI1. Moreover, an upper surface of the chip CPis provided with a plurality of bonding electrodes PI2. Hereafter, a surface provided with the plurality of bonding electrodes PI1, of the chip CMwill be called a front surface of the chip CM, and a surface provided with the plurality of external pad electrodes PX, of the chip CMwill be called a back surface of the chip CM. Moreover, a surface provided with the plurality of bonding electrodes PI2, of the chip CPwill be called a front surface of the chip CP, and a surface on an opposite side to the front surface, of the chip CPwill be called a back surface of the chip CP. In the example illustrated, the front surface of the chip CPis provided above the back surface of the chip CP, and the back surface of the chip CMis provided above the front surface of the chip CM.

The chip CMand the chip CPare disposed in such a manner that the front surface of the chip CMand front surface of the chip CPface each other. The plurality of bonding electrodes PI1are provided respectively correspondingly to the plurality of bonding electrodes PI2, and are disposed at positions enabling them to be bonded to the plurality of bonding electrodes PI2. The bonding electrodes PI1and bonding electrodes PI2function as bonding electrodes for bonding and making electrically continuous the chip CMand chip CP.

Note that in the example ofFIG.4, corners a1, a2, a3, a4of the chip CMrespectively correspond to corners b1, b2, b3, b4of the chip CP.

FIG.5is a schematic bottom view showing an example of configuration of the chip CM. InFIG.5, a part of configurations such as the bonding electrodes PI1are omitted. In the example ofFIG.5, the chip CMcomprises a total of four memory plane regions RMPaligned in twos in the X direction and the Y direction.

The memory plane regions RMPeach function as the memory cell array MCA described with reference toFIG.1. Moreover, these four memory plane regions RMPeach comprise a plurality of finger structures FS aligned in the Y direction. In the present embodiment, the finger structures FS each correspond to the memory block BLK described with reference toFIG.1. However, a correspondence relationship of the finger structure FS and the memory block BLK is appropriately adjustable. For example, a plurality of the finger structures FS may function as one memory block BLK.

Moreover, the memory plane region RMPin the example ofFIG.5comprises: three memory regions RMHaligned in the X direction; and two hookup regions RHUrespectively provided between pairs of the memory regions RMHadjacent in the X direction. Length in the X direction of the 2nd memory region RMHcounting from a negative side in the X direction is longer than lengths in the X direction of the 1stand 3rdmemory regions RMHcounting from a negative side in the X direction.

FIG.6is a schematic plan view showing an example of configuration of the chip CP. InFIG.6, a part of configurations such as the bonding electrodes PI2are omitted. In the example ofFIG.6, the chip CPcomprises four peripheral circuit regions RPCaligned in the X direction and the Y direction correspondingly to the four memory plane regions RMP.

The two end portions in the X direction, of the peripheral circuit region RPCare each provided with a row control circuit region RRowC. Moreover, a column control circuit region RColC(sense amplifier region) and a circuit region ROCthat are aligned in the Y direction are provided between these two row control circuit regions RRowC. The row control circuit region RRowCis provided with the row control circuit RowC described with reference toFIG.2. The column control circuit region RColCis provided with the column control circuit ColC described with reference toFIG.3. The circuit region ROCis provided with other circuits in the peripheral circuit PC.

FIG.7is a schematic cross-sectional view showing a part of configurations of the chips CM, CP. As shown inFIG.7, the chip CMcomprises: the memory cell array MCA; and a wiring layer group MG which is provided below the memory cell array MCA. Moreover, the chip CPcomprises: a semiconductor substrate100; and a wiring layer group DG which is provided above the semiconductor substrate100.

InFIG.7, there are exemplified: the transistors TBLKdescribed with reference toFIG.2; and sense amplifier transistors TSADLconfiguring the sense amplifier circuit SADL described with reference toFIG.3.

Note that inFIG.7, a position in a vicinity of a center in the X direction of the row control circuit region RRowCis indicated as a position XRowC. The position XRowCmay coincide with a center position in the X direction of the row control circuit region RRowC, but need not do so. Moreover, the position XRowCmay coincide with a center position in the X direction of the hookup region RHU, but need not do so. Moreover, a region provided more to a positive side in the X direction than the position XRowCin the row control circuit region RRowCand region provided more to a negative side in the X direction than the position XRowCin the row control circuit region RRowCare each indicated as a transistor region RTr.

The 1sttransistor region RTrcounting from a negative side in the X direction is provided at a position overlapping the 1stmemory region RMHcounting from a negative side in the X direction, looking from the Z direction. Moreover, this transistor region RTris provided at a position overlapping a part (a region more to a negative side in the X direction than the position XRowC) of the 1sthookup region RHUcounting from a negative side in the X direction, looking from the Z direction.

The 2nd transistor region RTrcounting from a negative side in the X direction is provided at a position overlapping a part (a region more to a positive side in the X direction than the position XRowC) of the 1sthookup region RHUcounting from a negative side in the X direction, looking from the Z direction. Moreover, this transistor region RTris provided at a position overlapping a part (a region in a vicinity of an end portion on a negative side in the X direction) of the 2ndmemory region RMHcounting from a negative side in the X direction, looking from the Z direction.

The column control circuit region RColCis provided at a position overlapping a part (a region excluding the region in a vicinity of the end portion on a negative side in the X direction and excluding a region in a vicinity of an end portion on a positive side in the X direction) of the 2ndmemory region RMHcounting from a negative side in the X direction, looking from the Z direction.

The 3rdtransistor region RTrcounting from a negative side in the X direction is provided at a position overlapping a part (the region in a vicinity of the end portion on a positive side in the X direction) of the 2ndmemory region RMHcounting from a negative side in the X direction, looking from the Z direction. Moreover, this transistor region RTris provided at a position overlapping a part (a region more to a negative side in the X direction than the position XRowC) of the 2ndhookup region RHUcounting from a negative side in the X direction, looking from the Z direction.

The 4thtransistor region RTrcounting from a negative side in the X direction is provided at a position overlapping a part (a region more to a positive side in the X direction than the position XRowC) of the 2ndhookup region RHUcounting from a negative side in the X direction, looking from the Z direction. Moreover, this transistor region RTris provided at a position overlapping the 3rdmemory region RMHcounting from a negative side in the X direction, looking from the Z direction.

Configurations of the memory cell array MCA, the semiconductor substrate100, the wiring layer group MG, and the wiring layer group DG will be described in order below.

[Structure in Memory Region RMHof Memory Cell Array MCA]

FIG.8is a schematic bottom view showing enlarged the portion indicated by A inFIG.5.FIG.9is a schematic cross-sectional view in which the structure shown inFIG.8has been cut along the line B-B′ and viewed along a direction of the arrows.FIG.10is a schematic cross-sectional view showing enlarged the portion indicated by C inFIG.9. AlthoughFIG.10shows a YZ cross section, a similar structure to inFIG.10will be observed, even if a cross section other than a YZ cross section (for example, an XZ cross section) along a central axis of a semiconductor column120is observed.

As has been described with reference toFIG.5, the memory plane region RMPis provided with a plurality of the finger structures FS aligned in the Y direction. As shown inFIG.8, an inter-finger structure ST is provided between two finger structures FS adjacent in the Y direction.

As shown inFIG.9, for example, the finger structure FS comprises: a plurality of conductive layers110stacked in the Z direction; a plurality of the semiconductor columns120extending in the Z direction; and a gate insulating film130provided between these conductive layers110and semiconductor columns120.

The conductive layer110comprises a substantially plate-like shape extending in the X direction. The conductive layer110may include the likes of a stacked film in which there are stacked a barrier conductive film of titanium nitride (TiN), or the like, and metal film of tungsten (W), molybdenum (Mo), or the like. Moreover, the conductive layer110may include the likes of polycrystalline silicon including an impurity such as phosphorus (P) or boron (B), for example. An inter-layer insulating layer101of the likes of silicon oxide (SiO2) is provided between the plurality of conductive layers110stacked in the Z direction. Moreover, an insulating layer102of the likes of silicon oxide (SiO2) is provided on a lower surface of the most downwardly provided conductive layer110.

The one or plurality of conductive layers110located in the uppermost layer, of the plurality of conductive layers110function as the gate electrode of the source side select transistor STS (FIG.1) and as the source side select gate line SGS. These plurality of conductive layers110are electrically independent every memory block BLK. These plurality of conductive layers110are continuous in the X direction from one end to the other end in the X direction of the finger structure FS.

Moreover, the plurality of conductive layers110located below these uppermost layer-located conductive layers110function as the gate electrodes of the memory cells MC (FIG.1) and as the word lines WL. These plurality of conductive layers110are each electrically independent every memory block BLK. These plurality of conductive layers110are continuous in the X direction from one end to the other end in the X direction of the finger structure FS.

Moreover, the one or plurality of conductive layers110located below these word line WL-functioning conductive layers110function as the gate electrode of the drain side select transistor STD (FIG.1) and as the drain side select gate line SGD. As shown inFIG.8, for example, width YSGDin the Y direction of these plurality of conductive layers110is smaller than width YWLin the Y direction of the conductive layers110functioning as the word lines WL. Moreover, an insulating member SHE of the likes of silicon oxide (SiO2) is provided between two conductive layers110adjacent in the Y direction within the finger structure FS. These plurality of conductive layers110are continuous in the X direction from one end to the other end in the X direction of the memory region RMH. Hence, length in the X direction of those provided in the 2ndmemory region RMHcounting from a negative side in the X direction, of the plurality of conductive layers110functioning as the drain side select gate line SGD, and so on, is longer than that of those provided in the 1stand 3rdmemory regions RMHcounting from a negative side in the X direction, of the plurality of conductive layers110functioning as the drain side select gate line SGD, and so on.

As shown inFIG.8, for example, the semiconductor columns120are aligned in a certain pattern in the X direction and the Y direction. The semiconductor columns120each function as channel regions of the plurality of memory cells MC and the select transistors (STD, STS) included in one memory string MS (FIG.1). The semiconductor column120includes the likes of polycrystalline silicon (Si), for example. The semiconductor column120has a substantially cylindrical shape, and, in its central portion, is provided with an insulator column125of the likes of silicon oxide. An outer peripheral surface of the semiconductor column120is surrounded by each of a plurality of the conductive layers110, and faces these plurality of conductive layers110.

Moreover, as shown inFIG.9, an impurity region122is provided at an upper end of the semiconductor column120. In the example ofFIG.9, a lower end of the impurity region122is expressed by a dotted line. The impurity region122includes an N type impurity such as phosphorus (P) or P type impurity such as boron (B), for example. The impurity region122is connected to a conductive layer112provided above the plurality of conductive layers110.

The conductive layer112functions as part of the source line SL (FIG.1). The conductive layer112may include a semiconductor layer of the likes of silicon (Si) that has been implanted with an N type impurity such as phosphorus (P) or P type impurity such as boron (B), may include a metal such as tungsten (W), or may include a silicide such as tungsten silicide (WSi), for example.

Moreover, an impurity region121is provided at a lower end of the semiconductor column120. In the example ofFIG.9, an upper end of the impurity region121is expressed by a dotted line. The impurity region121includes an N type impurity such as phosphorus (P), for example. The impurity region121is connected to a via contact electrode Ch. The via contact electrode Ch is electrically connected to the bit line BL via a via contact electrode Vy (FIG.8).

As shown inFIG.9, for example, the gate insulating film130has a substantially cylindrical shape covering the outer peripheral surface of the semiconductor column120. As shown inFIG.10, for example, the gate insulating film130comprises a tunnel insulating film131, a charge accumulating film132, and a block insulating film133that are stacked between the semiconductor column120and the conductive layer110. The tunnel insulating film131and the block insulating film133include the likes of silicon oxide (SiO2) or silicon oxynitride (SiON), for example. The charge accumulating film132includes a film capable of accumulating charge, of the likes of silicon nitride (SiN), for example. The tunnel insulating film131, the charge accumulating film132, and the block insulating film133have substantially cylindrical shapes, and extend in the Z direction along the outer peripheral surface of the semiconductor column120excluding a contact portion of the semiconductor column120and the conductive layer112.

Note thatFIG.10has shown an example where the gate insulating film130comprises the charge accumulating film132of the likes of silicon nitride. However, the gate insulating film130may comprise a floating gate of the likes of polycrystalline silicon including an N type or P type impurity, for example.

As shown inFIGS.8and9, for example, the inter-finger structure ST extends in the X direction and the Z direction. As shown inFIG.9, for example, the inter-finger structure ST comprises: an inter-finger electrode141; and an inter-finger insulating member142of the likes of silicon oxide (SiO2), provided on a side surface in the Y direction of the inter-finger electrode141. The inter-finger electrode141functions as part of the source line SL (FIG.1). An upper end of the inter-finger electrode141is connected to the conductive layer112. The inter-finger electrode141may include for example the likes of a stacked film in which there are stacked a barrier conductive film of titanium nitride (TiN), or the like, and metal film of tungsten (W), or the like. Moreover, the inter-finger electrode141may include the likes of polycrystalline silicon including an impurity such as phosphorus (P) or boron (B), for example.

[Structure in Hookup Region RHUof Memory Cell Array MCA]

FIG.11is a schematic bottom view showing enlarged the portion indicated by D inFIG.5.FIG.12is a schematic cross-sectional view in which the structure shown inFIG.11has been cut along the line E-E′ and viewed along a direction of the arrows.

As shown inFIG.11, the hookup region RHUis provided with: a word line hookup region RHUWL; and drain side select gate line hookup regions RHUSGDprovided on a positive side and a negative side in the X direction with respect to the word line hookup region RHUWL. Note that in the drawing, a via contact electrode CC provided in the word line hookup region RHUWLis illustrated as a via contact electrode CC(WL). Moreover, a via contact electrode CC provided in the drain side select gate line hookup region RHUSGDis illustrated as a via contact electrode CC(SGD).

The word line hookup region RHUWLis provided with: a plurality of the via contact electrodes CC(WL) aligned in the X direction over a plurality of columns (in the example illustrated, two columns); and a plurality of insulator columns HR aligned in the X direction and the Y direction.

The via contact electrodes CC are provided correspondingly to all of the conductive layers110. The via contact electrode CC extends in the Z direction, and has its upper end connected to its corresponding conductive layer110, as shown inFIG.12. The via contact electrode CC includes the likes of a stacked film of titanium nitride (TiN) and tungsten (W), for example. An insulating film CCSW of the likes of silicon oxide (SiO2) is provided between the via contact electrode CC(WL) and the conductive layer110. An outer peripheral surface of the via contact electrode CC(WL) faces via the insulating film CCSW an inner peripheral surface of a through-hole provided in the conductive layers110.

In the example ofFIG.12, the more to a negative side in the X direction a certain one of these plurality of via contact electrodes CC(WL) is provided, the longer its length in the Z direction will be, and the more upward the conductive layer110to which it is connected will be. Moreover, the more to a positive side in the X direction it is provided, the shorter its length in the Z direction will be, and the more downward the conductive layer110to which it is connected will be.

The insulator column HR (FIG.11) supports a structure under manufacture, during manufacturing of the semiconductor memory device. The insulator column HR extends in the Z direction penetrating the plurality of conductive layers110, although illustration of this is omitted. The insulator column HR may include solely an insulating layer of the likes of silicon oxide (SiO2), for example. Moreover, the insulator column HR may comprise a similar structure to the gate insulating film130, the semiconductor column120, and the insulator column125.

As shown inFIG.11, the drain side select gate line hookup region RHUSGDis provided with a plurality of terrace regions T that correspond to the plurality of conductive layers110corresponding to the drain side select gate line SGD. The terrace region T is a region that, looking from below, does not overlap the other conductive layers110, of a lower surface of the conductive layer110. In the example ofFIG.11, each terrace region T is correspondingly provided with one via contact electrode CC(SGD) and four insulator columns HR.

InFIG.12, there are exemplified two drain side select gate line hookup regions RHUSGDaligned in the X direction. In the one provided more to a positive side in the X direction, of these two drain side select gate line hookup regions RHUSGD, the more to a positive side in the X direction a certain one of the plurality of via contact electrodes CC(SGD) is provided, the more downward the conductive layer110to which it is connected will be. Moreover, the more to a negative side in the X direction it is provided, the more upward the conductive layer110to which it is connected will be. On the other hand, in the one provided more to a negative side in the X direction, of the two drain side select gate line hookup regions RHUSGDinFIG.12, the more to a negative side in the X direction a certain one of the plurality of via contact electrodes CC(SGD) is provided, the more downward the conductive layer110to which it is connected will be. Moreover, the more to a positive side in the X direction it is provided, the more upward the conductive layer110to which it is connected will be.

Note that as has been described with reference toFIG.5, the memory plane region RMPis provided with two hookup regions RHUaligned in the X direction. In this kind of structure, it is possible for the via contact electrodes CC(WL) corresponding to the word lines WL and source side select gate line SGS to be provided solely in one of the two hookup regions RHUin each finger structure FS.

For example, as mentioned above,FIG.11shows enlarged the portion indicated by D inFIG.5. Now, in the hookup region RHUexemplified inFIG.11(the hookup region RHUmore to a positive side in the X direction inFIG.5), there are provided via contact electrodes CC(WL) corresponding to the finger structure FS provided more to a positive side in the Y direction, of the illustrated two finger structures FS, but there are not provided via contact electrodes CC(WL) corresponding to the finger structure FS provided more to a negative side in the Y direction, of the illustrated two finger structures FS. Contrarily, in the hookup region RHUmore to a negative side in the X direction inFIG.5, there are not provided via contact electrodes CC(WL) corresponding to the finger structure FS provided more to a positive side in the Y direction, of the two finger structures FS illustrated inFIG.11, but there are provided via contact electrodes CC(WL) corresponding to the finger structure FS provided more to a negative side in the Y direction, of the two finger structures FS illustrated inFIG.11, although illustration of this contrary case is omitted.

For example, one of the two hookup regions RHUinFIG.5may include the via contact electrodes CC(WL) corresponding to even-numbered finger structures FS or memory blocks BLK counting from a negative side in the Y direction. In this case, the other of the two hookup regions RHUmay include the via contact electrodes CC(WL) corresponding to odd-numbered finger structures FS or memory blocks BLK counting from a negative side in the Y direction, for example.

Moreover, for example, one of the two hookup regions RHUinFIG.5may include the via contact electrodes CC(WL) corresponding to the 4n+1th(where n is an integer of 0 or more) and 4n+4thfinger structures FS or memory blocks BLK counting from a negative side in the Y direction. In this case, the other of the two hookup regions RHUmay include the via contact electrodes CC(WL) corresponding to the 4n+2thand 4n+3thfinger structures FS or memory blocks BLK counting from a negative side in the Y direction, for example.

The via contact electrodes CC(SGD) corresponding to the drain side select gate line SGD are basically provided in all of the hookup regions RHU. However, the 2ndmemory region RMHcounting from a negative side in the X direction (FIG.5) has both of its sides in the X direction provided with the hookup region RHU. In this kind of structure, it is possible too for the via contact electrodes CC(SGD) corresponding to the drain side select gate line SGD in this memory region RMHto be omitted in the 1stor 2ndhookup region RHUcounting from a negative side in the X direction.

The semiconductor substrate100includes P type silicon (Si) that includes a P type impurity such as boron (B), for example. As shown inFIG.12, for example, a surface of the semiconductor substrate100is provided with: a semiconductor region AA; and an insulating region STI of the likes of silicon oxide (SiO2). Some of the semiconductor regions AA are provided in an N type well region including an N type impurity such as phosphorus (P). Some of the semiconductor regions AA are provided in a P type well region including a P type impurity such as boron (B). The semiconductor region AA may be provided in a region including both the N type well region and the P type well region, may be provided in a region including only one of these well regions, or may be provided in a region not including either of these well regions.

An electrode layer GC is provided on an upper surface of the semiconductor substrate100via an insulating layer gi. The electrode layer GC includes a plurality of electrodes gc facing the semiconductor regions AA. Moreover, the semiconductor regions AA and the plurality of electrodes gc included in the electrode layer GC are each connected to a via contact electrode CS.

The semiconductor regions AA respectively function as channel regions of the plurality of transistors and as one of the electrodes of the plurality of capacitors, and so on, configuring the peripheral circuit PC (FIG.1).

The plurality of electrodes gc included in the electrode layer GC respectively function as gate electrodes of the plurality of transistors and as the other of the electrodes of the plurality of capacitors, and so on, configuring the peripheral circuit PC (FIG.1).

The via contact electrode CS extends in the Z direction, and has its lower end connected to an upper surface of the semiconductor region AA or electrode gc. A connecting portion of the via contact electrode CS and semiconductor region AA is provided with an impurity region including an N type impurity or P type impurity. The via contact electrode CS may include for example the likes of a stacked film in which there are stacked a barrier conductive film of titanium nitride (TiN), or the like, and metal film of tungsten (W), or the like.

[Structure in Row Control Circuit Region RRowCof Semiconductor Substrate100]

FIG.13is a schematic plan view showing enlarged the portion indicated by F inFIG.6. InFIG.13, a region overlapping the finger structure FS looking from the Z direction is indicated by a dotted line (refer toFIG.11).

The row control circuit region RRowCis provided with a plurality of the transistors TBLKaligned in the X direction over two columns, in a region corresponding to two of the finger structures FS, for example. That is, the region corresponding to the two finger structures FS is provided with a plurality of the semiconductor regions AA aligned in the X direction over two columns. In the example ofFIG.13, these plurality of semiconductor regions AA are indicated as semiconductor regions AABLK. The insulating region STI is provided between these plurality of semiconductor regions AABLK.

The semiconductor regions AABLKin the row control circuit region RRowCeach extend in the Y direction and are connected to the via contact electrode CS functioning as a source electrode and to the via contact electrode CS functioning as a drain electrode. Moreover, between these two via contact electrodes CS, there are provided the electrode gc functioning as a gate electrode, and the via contact electrode CS connected to this electrode gc.

Moreover, inFIG.13, there are illustrated a plurality of the via contact electrodes CC(WL) described with reference toFIG.11. Those functioning as the drain electrode, of the plurality of via contact electrodes CS connected to the plurality of semiconductor regions AABLK, are respectively electrically connected to the via contact electrodes CC(WL), via wirings in the wiring layer groups MG, DG.

For example, the transistors TBLKcorresponding to the one provided more to a negative side in the X direction, of the transistor regions RTrexemplified inFIG.13are connected to the conductive layers110functioning as the source side select gate line SGS and to those provided above a certain height position, of the conductive layers110functioning as the word lines WL (refer toFIG.12).

Moreover, the transistors TBLKcorresponding to the one provided more to a positive side in the X direction, of the transistor regions RTrexemplified inFIG.13are connected to those provided below the certain height position, of the conductive layers110functioning as the word lines WL (refer toFIG.12).

[Structure of Wiring Layer Group MG]

As shown inFIG.12, for example, the wiring layer group MG comprises: wiring layers M0, M1which are provided below the memory cell array MCA; and a chip bonding electrode layer MB which is provided below the wiring layers M0, M1.

A plurality of wirings included in the wiring layers M0, M1are electrically connected to at least one of configurations in the memory cell array MCA and configurations in the chip CP, for example.

The wiring layer M0includes a plurality of wirings m0. These plurality of wirings m0may include for example the likes of a stacked film in which there are stacked a barrier conductive film of titanium nitride (TiN), or the like, and metal film of copper (Cu), or the like.

Some of the plurality of wirings m0function as the bit line BL. As shown inFIG.8, for example, the bit lines BL are aligned in the X direction and extend in the Y direction.

As shown inFIG.12, for example, the wiring layer M1includes a plurality of wirings ml. These plurality of wirings ml may include for example the likes of a stacked film in which there are stacked a barrier conductive film of titanium nitride (TiN), or the like, and metal film of tungsten (W), or the like.

Some of the plurality of wirings ml are electrically connected between the bit line BL, and the sense amplifier transistor TSADLin the column control circuit region RColC(FIG.7), and function as a wiring CBL extending in the X direction. One end portion in the X direction of the wiring CBL is provided at a position overlapping its corresponding bit line BL looking from the Z direction. The other end portion in the X direction of the wiring CBL is provided in a vicinity of its corresponding sense amplifier circuit SADL, in the column control circuit region RColC.

For example, in a structure of the kind exemplified inFIG.7, the wirings CBL corresponding to the 1stmemory region RMHcounting from a negative side in the X direction extend in the X direction straddling a region overlapping at least a part of the 1stmemory region RMHcounting from a negative side in the X direction, the 1sthookup region RHUcounting from a negative side in the X direction, a part of the 2ndmemory region RMHcounting from a negative side in the X direction, and a part of the column control circuit region RColC, looking from the Z direction.

Moreover, the wirings CBL corresponding to the 2ndmemory region RMHcounting from a negative side in the X direction are provided within a range of a region overlapping a part of the 2ndmemory region RMHcounting from a negative side in the X direction, looking from the Z direction.

Moreover, the wirings CBL corresponding to the 3rdmemory region RMHcounting from a negative side in the X direction extend in the X direction straddling a region overlapping at least a part of the 3rdmemory region RMHcounting from a negative side in the X direction, the 2ndhookup region RHUcounting from a negative side in the X direction, a part of the 2ndmemory region RMHcounting from a negative side in the X direction, and a part of the column control circuit region RColC, looking from the Z direction.

The chip bonding electrode layer MB (FIG.12) includes a plurality of the bonding electrodes PI1. These plurality of bonding electrodes PI1may include for example the likes of a stacked film in which there are stacked a barrier conductive film pI1Bof titanium nitride (TiN), or the like, and metal film pI1Mof copper (Cu), or the like. These plurality of bonding electrodes PI1are electrically connected to at least one of configurations in the memory cell array MCA and configurations in the chip CP.

[Structure of Wiring Layer Group DG]

The wiring layer group DG comprises: wiring layers D0, D1, D2, D3, D4which are provided above the electrode layer GC; and a chip bonding electrode layer DB which is provided above the wiring layers D0, D1, D2, D3, D4.

A plurality of wirings included in the wiring layers D0, D1, D2, D3, D4are electrically connected to at least one of configurations in the memory cell array MCA and configurations in the chip CP, for example.

The wiring layers D0, D1, D2respectively include pluralities of wirings d0, d1, d2. These pluralities of wirings d0, d1, d2may include for example the likes of a stacked film in which there are stacked a barrier conductive film of titanium nitride (TiN), or the like, and metal film of tungsten (W), or the like.

Some of the pluralities of wirings d0, d1, d2are electrically connected between the word line WL, and a configuration in the row control circuit region RRowC, and function as the wiring CWL extending in the X direction. One end portion in the X direction of the wiring CWL is provided in a vicinity of its corresponding via contact electrode CC(WL). The other end portion in the X direction of the wiring CWL is provided in a vicinity of its corresponding transistor TBLK, in the row control circuit region RRowC.

For example, the wirings CWL corresponding to the one provided more to a negative side in the X direction, of the transistor regions RTrexemplified inFIG.13have their end portion on a via contact electrode CC(WL) side provided more to a positive side in the X direction (more to a side of the position XRowCdescribed with reference toFIG.7) than their end portion on a transistor TBLKside is. These wirings CWL are provided within a range of a region provided at a position overlapping the transistor region RTrmore to a negative side in the X direction, looking from the Z direction. Some of these wirings CWL have their one end and the other end in the X direction provided within a range of a region overlapping a region more to a negative side than the position XRowC, of one hookup region RHU, looking from the Z direction. The remaining ones of these wirings CWL extend in the X direction straddling a region overlapping one hookup region RHUand at least a part of the memory region RMHprovided more to a negative side in the X direction than this hookup region RHU, looking from the Z direction.

Similarly, the wirings CWL corresponding to the one provided more to a positive side in the X direction, of the transistor regions RTrexemplified inFIG.13have their end portion on a via contact electrode CC(WL) side provided more to a negative side in the X direction (more to a side of the position XRowCdescribed with reference toFIG.7) than their end portion on a transistor TBLKside is. These wirings CWL are provided within a range of a region overlapping the transistor region RTrmore to a positive side in the X direction, looking from the Z direction. Some of these wirings CWL have their one end and the other end in the X direction provided within a range of a region overlapping a region more to a positive side than the position XRowC, of one hookup region RHU, looking from the Z direction. The remaining ones of these wirings CWL extend in the X direction straddling a region overlapping one hookup region RHUand at least a part of the memory region RMHprovided more to a positive side in the X direction than this hookup region RHU, looking from the Z direction.

The wiring layers D3, D4(FIG.12) respectively include pluralities of wirings d3, d4. These pluralities of wirings d3, d4may include for example the likes of a stacked film in which there are stacked a barrier conductive film of titanium nitride (TiN), tantalum nitride (TaN), a stacked film of tantalum nitride (TaN) and tantalum (Ta), or the like, and metal film of copper (Cu), or the like.

The chip bonding electrode layer DB includes a plurality of the bonding electrodes PI2. These plurality of bonding electrodes PI2may include for example the likes of a stacked film in which there are stacked a barrier conductive film pI2Bof titanium nitride (TiN), tantalum nitride (TaN), a stacked film of tantalum nitride (TaN) and tantalum (Ta), or the like, and metal film pI2Mof copper (Cu), or the like. These plurality of bonding electrodes PI2are electrically connected to at least one of configurations in the memory cell array MCA and configurations in the chip CP.

Note that when the metal films pI1M, pI2Mof copper (Cu), or the like, are employed in the bonding electrode PI1and bonding electrode PI2, the metal film pI1Mand the metal film pI2Mamalgamate, so that identification of their boundary with each other becomes difficult. However, due to distortion of shape where the bonding electrode PI1and bonding electrode PI2have been bonded resulting from positional shift of bonding, and due to positional shift (generation of discontinuous places in side surfaces) of the barrier conductive films pI1B, pI2Bresulting from positional shift of bonding, bonding structure can be identified. Moreover, when the bonding electrode PI1and bonding electrode PI2are formed by a damascene method, their respective side surfaces will have a tapered shape. Therefore, shape of a cross section along the Z direction in a portion where the bonding electrode PI1and bonding electrode PI2have been bonded will be non-rectangular due to side walls being non-linearly shaped. Moreover, when the bonding electrode PI1and bonding electrode PI2are bonded, there will result a structure where each of a bottom surface, side surface, and upper surface of the Cu forming them will be covered by a barrier metal. In contrast, in a general wiring layer employing Cu, the upper surface of the Cu is provided with an insulating layer (of the likes of SiN or SiCN) functioning to prevent oxidation of the Cu, and is not provided with a barrier metal. Therefore, distinction from a general wiring layer is possible, even when positional shift of bonding has not occurred.

Comparative Example

FIG.14is a schematic cross-sectional view showing configuration of a semiconductor memory device according to a comparative example. The semiconductor memory device according to the comparative example comprises: a chip CM′ on a memory cell array MCA side; and a chip CP′ on a peripheral circuit PC side.

The chip CM′ according to the comparative example comprises: a memory region RMH; and two hookup regions RHUprovided on each of a positive side and a negative side in the X direction with respect to the memory region RMH. The hookup region RHUprovided more to a negative side in the X direction does not have a memory region RMHprovided on its negative side in the X direction. Similarly, the hookup region RHUprovided more to a positive side in the X direction does not have a memory region RMHprovided on its positive side in the X direction.

In the chip CP′ according to the comparative example, all of the wirings CWL corresponding to the row control circuit region RRowCprovided more to a negative side in the X direction have their end portion on a via contact electrode CC(WL) side in the X direction provided more to a negative side in the X direction than their end portion on a transistor TBLKside in the X direction is. Moreover, all of the wirings CWL corresponding to the row control circuit region RRowCprovided more to a positive side in the X direction have their end portion on a via contact electrode CC(WL) side in the X direction provided more to a positive side in the X direction than their end portion on a transistor TBLKside in the X direction is.

Now, with rise in level of integration of the semiconductor memory device, the number of conductive layers110(refer toFIG.9) stacked in the Z direction in each finger structure FS is increasing. Accordingly, the number of transistors TBLK(refer toFIG.13) aligned in the X direction in the row control circuit region RRowC, too, is increasing. In a structure like that of the comparative example, as the number of conductive layers110and number of transistors TBLKincrease, the number of wirings CWL too increases. For example, if the number of word lines WL and source side select gate lines SGS included in each finger structure FS is 128, then the number of wirings CWL corresponding to one finger structure FS, too, will be 128.

The wirings CWL are provided in a region overlapping the row control circuit region RRowC, of the wiring layers DO-D2, looking from the Z direction, for example. Moreover, the wirings CWL corresponding to one finger structure FS are provided within a range of a region overlapping two finger structures FS looking from the Z direction, for example. This will result in that when, for example, the number of wirings CWL corresponding to one finger structure FS is 128, these 128 wirings CWL will be provided in such a region, of the wiring layers D0-D2. For this purpose, conceivably, 50 wirings CWL aligned in the Y direction will be provided in each of the wiring layers D0, D1, and 28 wirings CWL aligned in the Y direction will be provided in the wiring layer D2, for example.

[Advantages of Semiconductor Memory Device According to First Embodiment]

In the first embodiment, the row control circuit region RRowCis provided at a position overlapping at least parts of two memory regions RMHaligned in the X direction and the hookup region RHUprovided between those two memory regions RMH, looking from the Z direction. Moreover, the row control circuit region RRowCis divided into two transistor regions RTraligned in the X direction, and a part of the wirings CWL are provided within a range of a region provided at a position overlapping one of those two transistor regions RTrlooking from the Z direction, while the remaining ones of the wirings CWL are provided within a range of a region provided at a position overlapping the other of those two transistor regions RTrlooking from the Z direction.

Due to this kind of configuration, it is possible for the number of wirings CWL aligned in the Y direction in the wiring layers D0-D2to be reduced. For example, in the case where the number of wirings CWL corresponding to one finger structure FS is 128, and the position XRowCdescribed with reference toFIG.7coincides with the center position in the X direction of the row control circuit region RRowCand center position in the X direction of the hookup region RHU, it will result in the two transistor regions RTraligned in the X direction each being provided with 64 wirings CWL of these 128 wirings CWL. For this purpose, conceivably, 25 wirings CWL aligned in the Y direction will be provided in each of the wiring layers D0, D1, and 14 wirings CWL aligned in the Y direction will be provided in the wiring layer D2, for example.

Hence, due to the semiconductor memory device according to the first embodiment, it is possible for the conductive layers110and transistors TBLKto be suitably connected, even when the number of conductive layers110increases. Moreover, it is possible for width in the Y direction of the wiring CWL to be made larger to a certain extent, even when the number of conductive layers110increases. This makes it possible for wiring resistance between the word line WL, and so on, and transistor TBLKto be reduced.

Moreover, due to the semiconductor memory device according to the first embodiment, it is possible for longest length in the X direction of the wiring CWL to be reduced more compared to in the comparative example. This makes it possible for maximum value of wiring resistance between the word line WL, and so on, and transistor TBLKto be made smaller.

Moreover, in the semiconductor memory device according to the first embodiment, the row control circuit region RRowCis provided in both end portions in the X direction of the peripheral circuit region RPC. In such a configuration, it is conceivable too that in the case of the center position in the X direction of the row control circuit region RRowCand center position in the X direction of the hookup region RHUhaving been matched or substantially matched, a region more to a negative side in the X direction than the 1sthookup region RHUcounting from a negative side in the X direction, of a region overlapping the 1strow control circuit region RRowCcounting from a negative side in the X direction, of the memory cell array MCA, looking from the Z direction, will end up becoming dead space. Moreover, it is conceivable too that in the case of the center positions having been matched or substantially matched as described above, a region more to a positive side in the X direction than the 2ndhookup region RHUcounting from a negative side in the X direction, of a region overlapping the 2ndrow control circuit region RRowCcounting from a negative side in the X direction, of the memory cell array MCA, looking from the Z direction, will end up becoming dead space. Accordingly, in the first embodiment, a memory region RMHof short length in the X direction is provided in these kinds of regions too. This makes it possible for dead space to be reduced, and for rise in level of integration of the semiconductor memory device to thereby be achieved.

Second Embodiment

In the semiconductor memory device according to the first embodiment, as shown inFIG.5, the hookup regions RHUare provided in vicinities of end portions in the X direction, of the memory plane region RMP. Moreover, as shown inFIG.6, the row control circuit regions RRowCare provided in end portions in the X direction, of the peripheral circuit region RPC.

However, this kind of configuration is merely an exemplification, and it is possible for specific configuration to be appropriately changed. For example, the hookup regions RHUmay be provided in a vicinity of a center in the X direction, of the memory plane region RMP. Moreover, the row control circuit regions RRowCmay be provided at a center position in the X direction, of the peripheral circuit region RPC.

Such a configuration will be exemplified below as a semiconductor memory device according to a second embodiment.

The semiconductor memory device according to the second embodiment is basically configured similarly to the semiconductor memory device according to the first embodiment. However, the semiconductor memory device according to the second embodiment comprises a chip CM2, instead of the chip CM.FIG.15is a schematic bottom view showing an example of configuration of the chip CM2. InFIG.15, a part of configurations such as the bonding electrodes PI1are omitted.

The chip CM2is basically configured similarly to the chip CM. However, the chip CM2comprises a memory plane region RMP2, instead of the memory plane region RMP. The memory plane region RMP2is basically configured similarly to the memory plane region RMP. However, in the memory plane region RMP2, lengths in the X direction of the of the 1stand 3rdmemory regions RMHcounting from a negative side in the X direction are longer than length in the X direction of the 2ndmemory region RMHcounting from a negative side in the X direction.

Moreover, the semiconductor memory device according to the second embodiment comprises a chip CP2, instead of the chip CP.FIG.16is a schematic bottom view showing an example of configuration of the chip CP2. InFIG.16, a part of configurations such as the bonding electrodes PI2are omitted.

The chip CP2is basically configured similarly to the chip CP. However, the chip CP2comprises a peripheral circuit region RPC2, instead of the peripheral circuit region RPC. The peripheral circuit region RPC2is basically configured similarly to the peripheral circuit region RPC. However, at a center position in the X direction, of the peripheral circuit region RPC2, there are provided two of the row control circuit regions RRowCaligned in the X direction. Moreover, a region on a positive side in the X direction and region on a negative side in the X direction with respect to these two row control circuit regions RRowCare each provided with the column control circuit region RColCand circuit region ROCaligned in the Y direction.

FIG.17is a schematic cross-sectional view showing a part of configurations of the chips CM2, CP2.

The 1stcolumn control circuit region RColCcounting from a negative side in the X direction is provided at a position overlapping a part (a region excluding a region in a vicinity of an end portion on a positive side in the X direction) of the 1stmemory region RMHcounting from a negative side in the X direction, looking from the Z direction.

The 1sttransistor region RTrcounting from a negative side in the X direction is provided at a position overlapping a part (the region in a vicinity of the end portion on a positive side in the X direction) of the 1stmemory region RMHcounting from a negative side in the X direction, looking from the Z direction. Moreover, this transistor region RTris provided at a position overlapping a part (a region more to a negative side in the X direction than the position XRowC) of the 1sthookup region RHUcounting from a negative side in the X direction, looking from the Z direction.

The 2ndtransistor region RTrcounting from a negative side in the X direction is provided at a position overlapping a part (a region more to a positive side in the X direction than the position XRowC) of the 1sthookup region RHUcounting from a negative side in the X direction, looking from the Z direction. Moreover, this transistor region RTris provided at a position overlapping a part (a region more to a negative side in the X direction than a center position in the X direction) of the 2ndmemory region RMHcounting from a negative side in the X direction, looking from the Z direction.

The 3rdtransistor region RTrcounting from a negative side in the X direction is provided at a position overlapping a part (a region more to a positive side in the X direction than the center position in the X direction) of the 2ndmemory region RMHcounting from a negative side in the X direction, looking from the Z direction. Moreover, this transistor region RTris provided at a position overlapping a part (a region more to a negative side in the X direction than the position XRowC) of the 2ndhookup region RHUcounting from a negative side in the X direction, looking from the Z direction.

The 4thtransistor region RTrcounting from a negative side in the X direction is provided at a position overlapping a part (a region more to a positive side in the X direction than the position XRowC) of the 2ndhookup region RHUcounting from a negative side in the X direction, looking from the Z direction. Moreover, this transistor region RTris provided at a position overlapping a part (a region in a vicinity of an end portion on a negative side in the X direction) of the 3rdmemory region RMHcounting from a negative side in the X direction, looking from the Z direction.

The 2ndcolumn control circuit region RColCcounting from a negative side in the X direction is provided at a position overlapping a part (a region excluding the region in a vicinity of the end portion on a negative side in the X direction) of the 3rdmemory region RMHcounting from a negative side in the X direction, looking from the Z direction.

The semiconductor memory device according to the second embodiment enables similar advantages to those of the semiconductor memory device according to the first embodiment to be displayed.

Moreover, in the semiconductor memory device according to the second embodiment, the hookup region RHUis provided in a vicinity of a center in the X direction, of the memory plane region RMP2. In this kind of configuration, it is possible for maximum value of distance between the via contact electrode CC and the semiconductor column120to be reduced by about half, compared to in the semiconductor memory device according to the first embodiment. This makes it possible for wiring resistance in the conductive layer110to be reduced, and for speeding-up of operation to thereby be achieved.

Third Embodiment

In the first embodiment and the second embodiment, the row control circuit region RRowCis divided into two transistor regions RTraligned in the X direction, and a part of the wirings CWL are provided within a range of a region provided at a position overlapping one of those two transistor regions RTrlooking from the Z direction, while the remaining ones of the wirings CWL are provided within a range of a region provided at a position overlapping the other of those two transistor regions RTrlooking from the Z direction. This makes it possible for the number of wirings CWL aligned in the Y direction in the wiring layers D0-D2to be reduced, and for rise in level of integration of the semiconductor memory device to thereby be achieved.

Now, it is possible too for the transistor regions RTraligned in the X direction in the row control circuit region RRowCto be further divided in the X direction, and for the wirings CWL to be provided within a range of a region provided at a position overlapping any of these divided regions looking from the Z direction, for example. This makes it possible for the number of wirings CWL aligned in the Y direction in the wiring layers DO-D2to be further reduced.

Such a configuration will be exemplified below as a semiconductor memory device according to a third embodiment.

The semiconductor memory device according to the third embodiment is basically configured similarly to the semiconductor memory device according to the second embodiment. However, the semiconductor memory device according to the third embodiment comprises a chip CM3and a chip CP3, instead of the chip CM2and the chip CP2.

FIG.18is a schematic bottom view showing an example of configuration of the chip CM3. InFIG.18, a part of configurations such as the bonding electrodes P u are omitted.FIG.19is a schematic cross-sectional view showing a part of configurations of the chips CM3, CP3.

The chip CM3is basically configured similarly to the chip CM2. However, in the chip CM3, the hookup region RHUis divided into two divided hookup regions RHUDseparated in the X direction. Moreover, the memory region RMHis provided between two of the divided hookup regions RHUDadjacent in the X direction.

The divided hookup region RHUDis basically configured similarly to the hookup region RHU. However, the hookup region RHUcomprises all of the via contact electrodes CC(WL). On the other hand, the divided hookup region RHUDcomprises only a part of the via contact electrodes CC(WL). That is, in the case of the hookup region RHUbeing divided into n (where n is an integer of 2 or more) in the X direction, the via contact electrodes CC(WL) will be disposed dispersed among n of the divided hookup regions RHUD.

For example, in the example ofFIG.19, in the 1sthookup region RHUcounting from a negative side in the X direction, there are disposed the plurality of via contact electrodes CC(WL) corresponding to a certain finger structure FS. Now, in the 1stdivided hookup region RHUDcounting from a negative side in the X direction, there are disposed the via contact electrodes CC(WL) corresponding to the conductive layers110provided below a certain position. Moreover, in the 2nddivided hookup region RHUDcounting from a negative side in the X direction, there are disposed the via contact electrodes CC(WL) corresponding to the conductive layers110provided above the certain position.

Moreover, in the example ofFIG.19, in the 2ndhookup region RHUcounting from a negative side in the X direction, there are disposed the plurality of via contact electrodes CC(WL) corresponding to another finger structure FS. Now, in the 3rddivided hookup region RHUDcounting from a negative side in the X direction, there are disposed the via contact electrodes CC(WL) corresponding to the conductive layers110provided above a certain position. Moreover, in the 4thdivided hookup region RHUDcounting from a negative side in the X direction, there are disposed the via contact electrodes CC(WL) corresponding to the conductive layers110provided below the certain position.

The chip CP3is basically configured similarly to the chip CP2. However, the chip CP3comprises a peripheral circuit region RPC3, instead of the peripheral circuit region RPC2. Moreover, the chip CP3comprises a wiring layer group DG3, instead of the wiring layer group DG.

The peripheral circuit region RPC3is basically configured similarly to the peripheral circuit region RPC2. However, in the peripheral circuit region RPC3, the transistor region RTris divided into two divided transistor regions RTrDseparated in the X direction.

InFIG.19, a position in a vicinity of a center in the X direction of the transistor region RTris indicated as position XRowCD. The position XRowCDmay coincide with a center position in the X direction of the transistor region RTr, but need not do so. Moreover, the position XRowCDmay coincide with a center position in the X direction of the divided hookup region RHUD, but need not do so. Moreover, a region provided more to a positive side in the X direction than the position XRowCD, in the transistor region RTrand region provided more to a negative side in the X direction than the position XRowCD, in the transistor region RTrare each indicated as the divided transistor region RTrD.

The divided transistor regions RTrDare each provided at a position overlapping a part (a region on a positive side or negative side in the X direction with respect to the position XRowCD) of some one of the divided hookup regions RHUD, looking from the Z direction. Moreover, the divided transistor regions RTrDare each provided at a position overlapping a part of some one of the memory regions RMH, looking from the Z direction.

The wiring layer group DG3is basically configured similarly to the wiring layer group DG. However, in the wiring layer group DG3, the plurality of wirings CWL are provided within a range of a region provided at a position overlapping any of the divided transistor regions RTrD, looking from the Z direction.

The semiconductor memory device according to the third embodiment enables similar advantages to those of the semiconductor memory device according to the second embodiment to be displayed.

Moreover, due to the semiconductor memory device according to the third embodiment, it is possible for the number of wirings CWL aligned in the Y direction in the wiring layers D0-D2to be further reduced. Moreover, it is possible for maximum value of wiring resistance between the word line WL, or the like, and transistor TBLKto be made even smaller.

Fourth Embodiment

A semiconductor memory device according to a fourth embodiment is basically configured similarly to the semiconductor memory device according to the third embodiment. However, the semiconductor memory device according to the fourth embodiment comprises a chip CM4and a chip CP4, instead of the chip CM3and the chip CP3.

FIG.20is a schematic bottom view showing an example of configuration of the chip CM4. InFIG.20, a part of configurations such as the bonding electrodes PI1are omitted.FIG.21is a schematic cross-sectional view showing a part of configurations of the chips CM4, CP4.

The chip CM4is basically configured similarly to the chip CM3. However, in the chip CM4, the memory region RMHis not provided between two of the hookup regions RHUaligned in the X direction.

The chip CP4is basically configured similarly to the chip CP3. However, as shown inFIG.21, the chip CP4comprises a peripheral circuit region RPC4, instead of the peripheral circuit region RPC3. Moreover, the chip CP4comprises a wiring layer group DG4, instead of the wiring layer group DG3.

The peripheral circuit region RPC4is basically configured similarly to the peripheral circuit region RPC3. However, in the peripheral circuit region RPC4, the one provided on a side of a center position in the X direction of the peripheral circuit region RPC4, of two transistor regions RTr, is not divided into two divided transistor regions RTrD. Moreover, the transistor region RTrprovided on the side of the center position in the X direction of the peripheral circuit region RPC4, and the two divided transistor regions RTrDeach include about the same number of transistors TBLK.

The wiring layer group DG4is basically configured similarly to the wiring layer group DG3. However, in the wiring layer group DG4, a part of the wirings CWL are provided within a range of a region provided at a position overlapping the transistor region RTrprovided on the side of the center position in the X direction of the peripheral circuit region RPC4, looking from the Z direction.

The semiconductor memory device according to the fourth embodiment enables similar advantages to those of the semiconductor memory device according to the third embodiment to be displayed.

Fifth Embodiment

In the semiconductor memory device according to the first embodiment, as has been described with reference toFIG.12, the outer peripheral surface of the via contact electrode CC(WL) faces via the insulating film CCSW the inner peripheral surface of a through-hole provided in the conductive layers110. Part of a method of manufacturing such a structure will be described below with reference toFIGS.22-25.FIGS.22-25are schematic cross-sectional views for explaining part of a method of manufacturing the via contact electrode CC(WL).

As shown inFIG.22, during manufacture of the via contact electrode CC(WL), a sacrifice layer110A of the likes of silicon nitride (SiN) may be formed at a position corresponding to the conductive layer110. During manufacture of the via contact electrode CC(WL), a contact hole CCA is formed at each of a plurality of positions corresponding to a plurality of the via contact electrodes CC(WL). The contact holes CCA extend in the Z direction and penetrate a plurality of the sacrifice layers110A, and so on, to each expose a surface of a certain one of the sacrifice layers110A.

Next, as shown inFIG.23, a surface of the structure shown inFIG.22is coated with a resist Reg.

Next, as shown inFIG.24, part of the resist Reg is removed to expose a part of the contact holes CCA.

Next, as shown inFIG.25, bottom surfaces of the exposed a part of the contact holes CCA have removed therefrom precisely a certain number of the sacrifice layers110A and inter-layer insulating layers101. For example, in the example ofFIG.25, eight layers each of the sacrifice layers110A and inter-layer insulating layers101are removed. This step is executed by anisotropic etching such as RIE (Reactive Ion Etching), for example. Moreover, in this step, there are alternately executed a certain number of times each (inFIG.25, eight times each): a step in which the sacrifice layer110A is selectively removed; and a step in which the inter-layer insulating layer101is selectively removed.

In the case of the via contact electrode CC(WL) being formed by this kind of method, part of the resist Reg that has been coated during the coating with resist Reg described with reference toFIG.23, is drawn into the contact hole CCA. Now, in a region where a deep contact hole CCA is formed, an amount of the resist Reg drawn in (hereafter, called “drawn-in amount”) becomes comparatively large. On the other hand, in a region where a shallow contact hole CCA is formed, the drawn-in amount becomes comparatively small. As a result, film thickness of the resist Reg sometimes ends up becoming ununiform in the hookup region RHU.

If film thickness of the resist Reg ends up becoming ununiform in the hookup region RHU, then optimum focus of a lithography device ends up deviating between a place where film thickness of the resist Reg is thick and a place where it is thin. Hence, a margin in process of lithography with respect to focus deviation of the lithography device lowers. As a result, there is a risk that the contact hole CCA will become unopened or that uniformity of dimensions of the contact hole CCA will fall. Moreover, there is a possibility that in some regions, film thickness of the resist Reg will be insufficient. In particular, the larger the number of layers of sacrifice layers110A becomes, the deeper the contact hole CCA will become, and the easier for there to occur an insufficiency of film thickness of the resist Reg it will become.

Accordingly, in a fifth embodiment, as shown inFIG.26, in regions corresponding to each of the finger structures FS, the word line hookup region RHUWLwhich is not to be provided with the via contact electrode CC(WL) has formed therein a dummy contact hole DCCA.

InFIG.26, a region corresponding to one finger structure FS and one word line hookup region RHUWLis divided into two regions RA, RBin the X direction. These regions RA, RBeach have formed therein the contact hole CCA. Moreover, inFIG.26, a region corresponding to the finger structure FS adjacent in the Y direction to this one finger structure FS, and one word line hookup region RHUWL, is divided into two regions RC, RDin the X direction. These regions RC, RDeach have formed therein the dummy contact hole DCCA.

Now, the dummy contact holes DCCA each have a such a depth as will ease variation in depths of the contact holes CCA. For example, in the case where in the regions RA, RB, as inFIG.22, the more to a negative side in the X direction a certain contact hole CCA is provided, the deeper it will be, and the more to a positive side in the X direction a certain contact hole CCA is provided, the shallower it will be, it is conceivable that, as shown inFIG.27, in the regions RC, RD, there be formed a structure of the kind whereby the more to a positive side in the X direction a certain dummy contact hole DCCA is provided, the deeper it will be, and the more to a negative side in the X direction a certain dummy contact hole DCCA is provided, the shallower it will be. This makes it possible for uniformity of film thickness of the resist Reg coated in the step described with reference toFIG.23to be improved.

FIG.28is a schematic bottom view showing a part of configurations of a semiconductor memory device according to the fifth embodiment.FIG.29is a schematic cross-sectional view in which the structure shown inFIG.28has been cut along the line G-G′ and viewed along a direction of the arrows.

The semiconductor memory device according to the fifth embodiment is basically configured similarly to the semiconductor memory device according to the first embodiment. However, the semiconductor memory device according to the fifth embodiment comprises a dummy contact DCC (columnar body such as insulator column). The dummy contact DCC is an insulating member provided in the dummy contact hole DCCA, and includes silicon oxide (SiO2), for example.

As shown inFIG.5, the memory plane region RMPaccording to the fifth embodiment is provided with two of the hookup regions RHUaligned in the X direction. In the fifth embodiment, in each finger structure FS, the via contact electrode CC(WL) is provided in one of the two hookup regions RHU, and the dummy contact DCC is provided in the other of the two hookup regions RHU.

InFIG.28, there are exemplified two finger structures FS aligned in the Y direction. Moreover, a region corresponding to the finger structure FS provided more to a positive side in the Y direction, and the word line hookup region RHUWL, is divided into the two regions RA, RBin the X direction. These regions RA, RBare each provided with the via contact electrode CC(WL). Moreover, inFIG.28, a region corresponding to the finger structure FS adjacent in the Y direction to this more-Y-direction-positive-side-disposed finger structure FS, and the word line hookup region RHUWL, is divided into the two regions RC, RDin the X direction. These regions RC, RDare each provided with the dummy contact DCC.

In a similar way to in the example ofFIG.12, the more to a negative side in the X direction a certain one of the plurality of via contact electrodes CC(WL) provided in the regions RA, RBis provided, the longer its length in the Z direction will be, and the more upward the conductive layer110to which it is connected will be. Moreover, the more to a positive side in the X direction a certain one of the plurality of via contact electrodes CC(WL) provided in the regions RA, RBis provided, the shorter its length in the Z direction will be, and the more downward the conductive layer110to which it is connected will be. Note that the plurality of via contact electrodes CC(WL) provided in the region RAhave shorter lengths in the Z direction than the plurality of via contact electrodes CC(WL) provided in the region RB.

As shown inFIG.29, the more to a negative side in the X direction a certain one of the plurality of dummy contacts DCC provided in the regions RC, RDis provided, the shorter its length in the Z direction will be. Moreover, the more to a positive side in the X direction it is provided, the longer its length in the Z direction will be. Note that the plurality of dummy contacts DCC provided in the region RChave longer lengths in the Z direction than the plurality of dummy contacts DCC provided in the region RD.

Moreover, length in the Z direction of the mth(where m is an integer of 1 or more) via contact electrode CC(WL) counting from a positive side in the X direction in the word line hookup region RHUWLis identical to or substantially identical to length in the Z direction of the mthdummy contact DCC counting from a negative side in the X direction in the word line hookup region RHUWL. Hence, length in the Z direction of the via contact electrodes CC(WL) provided in the region RAis shorter than length in the Z direction of the dummy contacts DCC provided in the region RC. Moreover, length in the Z direction of the via contact electrodes CC(WL) provided in the region RBis longer than length in the Z direction of the dummy contacts DCC provided in the region RD.

Other Embodiments

That concludes description of the semiconductor memory devices according to the first through fifth embodiments. However, the configurations described above are merely exemplifications, and specific configurations may be appropriately adjusted.

For example, as has been described with reference toFIGS.18and19, in the third embodiment, similarly to in the second embodiment, the hookup regions RHUare provided in a vicinity of a center in the X direction, of a memory plane region RMP3. Moreover, the row control circuit regions RRowCare provided at a center position in the X direction, of the peripheral circuit region RPC3. However, in the third embodiment, similarly to in the first embodiment, the hookup regions RHUmay be provided in vicinities of end portions in the X direction, of the memory plane region RMP3(refer toFIGS.5and7). Moreover, the row control circuit regions RRowCmay be provided in end portions in the X direction, of the peripheral circuit region RPC3(refer toFIGS.6and7).

Likewise, in the fourth embodiment (FIGS.20and21) too, similarly to in the first embodiment, the hookup regions RHUmay be provided in end portions in the X direction, of a memory plane region RMP4(refer toFIGS.5and7). Moreover, the row control circuit regions RRowCmay be provided in end portions in the X direction, of the peripheral circuit region RPC4(refer toFIGS.6and7).

Moreover, in the first through fifth embodiments, the memory plane regions RMP, RMP2, RMP3, RMP4are provided with two hookup regions RHU. However, in the first through fifth embodiments, one of the hookup regions RHUmay be omitted. Moreover, in this case, one of the row control circuit regions RRowCmay be omitted in the peripheral circuit regions RPC, RPC2, RPC3, RPC4.

Moreover, the dummy contact DCC described with reference toFIGS.28and29may be provided in the semiconductor memory devices according to the second, third, or fourth embodiments.

Moreover, in the first through fifth embodiments, layout of the wirings CWL is appropriately adjustable.FIGS.30-32are schematic plan views for explaining one example of layout of the wirings CWL.FIG.30exemplifies a wiring pattern in the wiring layer DO.FIG.31exemplifies a wiring pattern in the wiring layer D1.FIG.32exemplifies a wiring pattern in the wiring layer D2.

InFIGS.30-32, there are illustrated configurations of regions provided at positions overlapping the transistor region RTr, of the wiring layers DO-D2. Moreover, inFIGS.30-32, there are illustrated: regions RHU6ddividing into six in the X direction a region from the position X Row c to an end position in the X direction of the hookup region RHU; and regions RTr6ddividing into six in the X direction the transistor region RTr.

As shown inFIG.30, at positions overlapping the transistor region RTrlooking from the Z direction, of the wiring layer D0, there are provided two wiring groups CWLP00, CWLP01aligned in the X direction. These two wiring groups CWLP00, CWLP01each comprise a plurality of the wirings CWL aligned in the Y direction.

One ends (end portions on a via contact electrode CC(WL) side) of the plurality of wirings CWL included in the wiring group CWLP00are provided from a boundary on a side of the position XRowCto a boundary on an opposite side to the position XRowC, of the region RHU6d1stclosest to the position XRowC(the region surrounded by a dotted line in the drawing). The plurality of via contact electrodes CC(WL) included in the region RHU6d1stclosest to the position XRowCare electrically connected to the plurality of wirings CWL included in the wiring group CWLP00.

Moreover, the other ends (end portions on a transistor TBLKside) of the plurality of wirings CWL included in the wiring group CWLP00are provided from a boundary on a side of the position XRowCto a boundary on an opposite side to the position XRowC, of the region RTr6d1stclosest to the position XRowC(the region surrounded by a two dot-chain line in the drawing). The plurality of transistors TBLKincluded in the region RTr6d1stclosest to the position XRowCare electrically connected to the plurality of wirings CWL included in the wiring group CWLP00.

One ends (end portions on a via contact electrode CC(WL) side) of the plurality of wirings CWL included in the wiring group CWLP01are provided from a boundary on a side of the position XRowCto a boundary on an opposite side to the position XRowC, of the region RHU6d4thclosest to the position XRowC(the region surrounded by a dotted line in the drawing). The plurality of via contact electrodes CC(WL) included in the region RHU6d4thclosest to the position XRowCare electrically connected to the plurality of wirings CWL included in the wiring group CWLP01.

Moreover, the other ends (end portions on a transistor TBLKside) of the plurality of wirings CWL included in the wiring group CWLP01are provided from a boundary on a side of the position XRowCto a boundary on an opposite side to the position XRowC, of the region RTr6d4thclosest to the position XRowC(the region surrounded by a two dot-chain line in the drawing). The plurality of transistors TBLKincluded in the region RTr6d4thclosest to the position XRowCare electrically connected to the plurality of wirings CWL included in the wiring group CWLP01.

As shown inFIG.31, at positions overlapping the transistor region RTrlooking from the Z direction, of the wiring layer D1, there are provided two wiring groups CWLP10, CWLP11aligned in the X direction. These two wiring groups CWLP10, CWLP11each comprise a plurality of the wirings CWL aligned in the Y direction.

One ends (end portions on a via contact electrode CC(WL) side) of the plurality of wirings CWL included in the wiring group CWLP10are provided from a boundary on a side of the position XRowCto a boundary on an opposite side to the position XRowC, of the region RHU6d2ndclosest to the position XRowC(the region surrounded by a dotted line in the drawing). The plurality of via contact electrodes CC(WL) included in the region RHU6d2ndclosest to the position XRowCare electrically connected to the plurality of wirings CWL included in the wiring group CWLP10.

Moreover, the other ends (end portions on a transistor TBLKside) of the plurality of wirings CWL included in the wiring group CWLP10are provided from a boundary on a side of the position XRowCto a boundary on an opposite side to the position XRowC, of the region RTr6d2ndclosest to the position XRowC(the region surrounded by a two dot-chain line in the drawing). The plurality of transistors TBLKincluded in the region RTr6d2ndclosest to the position XRowCare electrically connected to the plurality of wirings CWL included in the wiring group CWLP10.

One ends (end portions on a via contact electrode CC(WL) side) of the plurality of wirings CWL included in the wiring group CWLP11are provided from a boundary on a side of the position XRowCto a boundary on an opposite side to the position XRowC, of the region RHU6d5thclosest to the position XRowC(the region surrounded by a dotted line in the drawing). The plurality of via contact electrodes CC(WL) included in the region RHU6d5thclosest to the position XRowCare electrically connected to the plurality of wirings CWL included in the wiring group CWLP11.

Moreover, the other ends (end portions on a transistor TBLKside) of the plurality of wirings CWL included in the wiring group CWLP11are provided from a boundary on a side of the position XRowCto a boundary on an opposite side to the position XRowC, of the region RTr6d5thclosest to the position XRowC(the region surrounded by a two dot-chain line in the drawing). The plurality of transistors TBLKincluded in the region RTr6d5thclosest to the position XRowCare electrically connected to the plurality of wirings CWL included in the wiring group CWLP11.

As shown inFIG.32, at positions overlapping the transistor region RTrlooking from the Z direction, of the wiring layer D2, there are provided two wiring groups CWLP20, CWLP21aligned in the X direction. These two wiring groups CWLP20, CWLP21each comprise a plurality of the wirings CWL aligned in the Y direction.

One ends (end portions on a via contact electrode CC(WL) side) of the plurality of wirings CWL included in the wiring group CWLP20are provided from a boundary on a side of the position XRowCto a boundary on an opposite side to the position XRowC, of the region RHU6d3rdclosest to the position XRowC(the region surrounded by a dotted line in the drawing). The plurality of via contact electrodes CC(WL) included in the region RHU6d3rdclosest to the position XRowCare electrically connected to the plurality of wirings CWL included in the wiring group CWLP20.

Moreover, the other ends (end portions on a transistor TBLKside) of the plurality of wirings CWL included in the wiring group CWLP20are provided from a boundary on a side of the position XRowCto a boundary on an opposite side to the position XRowC, of the region RTr6d3rdclosest to the position XRowC(the region surrounded by a two dot-chain line in the drawing). The plurality of transistors TBLKincluded in the region RTr6d3rdclosest to the position XRowCare electrically connected to the plurality of wirings CWL included in the wiring group CWLP20.

One ends (end portions on a via contact electrode CC(WL) side) of the plurality of wirings CWL included in the wiring group CWLP21are provided from a boundary on a side of the position XRowCto a boundary on an opposite side to the position XRowC, of the region RHU6d6thclosest to the position XRowC(the region surrounded by a dotted line in the drawing). The plurality of via contact electrodes CC(WL) included in the region RHU6d6thclosest to the position XRowCare electrically connected to the plurality of wirings CWL included in the wiring group CWLP21.

Moreover, the other ends (end portions on a transistor TBLKside) of the plurality of wirings CWL included in the wiring group CWLP21are provided from a boundary on a side of the position XRowCto a boundary on an opposite side to the position XRowC, of the region RTr6d6thclosest to the position XRowC(the region surrounded by a two dot-chain line in the drawing). The plurality of transistors TBLKincluded in the region RTr6d6thclosest to the position XRowCare electrically connected to the plurality of wirings CWL included in the wiring group CWLP21.

Moreover, in the first through fifth embodiments, the chips CM, CM2, CM3, CM4are respectively provided with totals of four memory plane regions RMP, RMP2, RMP3, RMP4aligned in twos in the X direction and the Y direction. However, the number and disposition of memory plane regions provided in a chip is appropriately adjustable. For example, in the example ofFIG.33, a chip CM16is provided with a total of 16 memory plane regions RMPaligned in fours in the X direction and the Y direction. The chip CM16may be provided with the memory plane regions RMP2, RMP3, RMP4, rather than the memory plane region RMP.

Moreover, in the first through fifth embodiments, as has been described with reference toFIG.12, and so on, the outer peripheral surface of the via contact electrode CC(WL) faces via the insulating film CCSW the inner peripheral surface of a through-hole provided in the conductive layers110. However, such a configuration is merely an exemplification, and specific configuration is appropriately adjustable.

FIG.34is a schematic bottom view showing another example of configuration of the word line hookup region RHUWL.FIG.35is a schematic cross-sectional view in which the structure shown inFIG.34has been cut along the line E-E′ and viewed along a direction of the arrows.

Note that as has been described with reference to the likes ofFIG.5, in the case where the memory plane region RMPis provided with two hookup regions RHUaligned in the X direction, one of these two hookup regions RHUmay include the via contact electrodes CC(WL) corresponding to the 4n+1th(where n is an integer of 0 or more) and 4n+4thfinger structures FS or memory blocks BLK counting from a negative side in the Y direction. In this case, the other of the two hookup regions RHUmay include the via contact electrodes CC(WL) corresponding to the 4n+2thand 4n+3thfinger structures FS or memory blocks BLK counting from a negative side in the Y direction, for example.

Now,FIG.11shows configuration of the above-described one of the hookup regions RHUcorresponding to the 4n+3thand 4n+4thfinger structures FS counting from a negative side in the Y direction, for example. On the other hand,FIG.34shows configuration of the above-described one of the hookup regions RHUcorresponding to the 4n+4thand 4n+1th(4n+5th) finger structures FS counting from a negative side in the Y direction, for example.

In the example ofFIG.34too, the conductive layer110functioning as the word line WL, and so on, is continuous in the X direction over a plurality of the memory regions RMHaligned in the X direction. However, in the example ofFIGS.34and35, the word line hookup region RHUWLis provided with a plurality of the terrace regions T aligned in the X direction correspondingly to the plurality of via contact electrodes CC(WL). Note that in the example ofFIG.34, the plurality of via contact electrodes CC(WL) are provided over two columns, correspondingly to each finger structure FS. However, in the case of the via contact electrodes CC(WL) being provided in one column, the terrace regions T too will be provided in one column. Moreover, in the case of the via contact electrodes CC(WL) being provided over three or more columns, the terrace regions T too will be provided over three or more columns.