Integrated circuit with configurable I/O transistor arrangement

I/O circuits and a method for transmitting different types of I/O signals are disclosed. An embodiment of the I/O circuit comprises multiple transistors with multiple switches coupled to the transistors. The switches may be used to selectively couple the transistors to a power source or to another transistor to form different transistor configurations. The transistors may be configured to form a parallel configuration or a stacked configuration. Stacking up transistors may reduce voltage swings in the transistors and subsequently reduce degradation in the transistors.

BACKGROUND

Transistors used in ICs are susceptible to degradation due to frequent voltage swings. “Wear-out” tests are generally carried out on semiconductor devices to test the reliability of a device and the hot carrier-induced (HCI) degradation test is an example of such a “wear-out” test. In deep sub-micron technology, certain input/output (I/O) standards become more sensitive to HCI degradation. In some I/Os, the degradation is caused by voltage swings at the output transistors. As a consequence, the saturation drive current, i.e., the IDsat of a transistor, degrades significantly after constant operation under such condition.

The degradation would subsequently affect the performance and reliability of a device. In order to reduce the gradual degradation of the transistors, the electric field or voltage swing needs to be removed or at least reduced. One way to reduce the electric field seen across the source and drain terminals of a transistor is to stack up multiple transistors in order to divide the high voltage seen in an individual transistor among several transistors. This way, the voltage drop across any one transistor can be reduced. For example, when four transistors are stacked between a 12-volt power supply and ground, the average voltage across each transistor is only 3 volts. Because the transistors do not need to handle constant sudden voltage swings, their performance can be maintained for a much longer period of time.

Consequently the lifespan of an IC or a device can be substantially lengthened because of the reduced degradation in transistors. However, I/Os in an IC generally support different drive strengths and merely stacking up transistors just to support a particular I/O standard or drive strength is not efficient and may unnecessarily affect the performance of the I/Os.

Therefore, it is desirable to have an IC with transistors that can be configured to support a higher drive strength with a high voltage swing without significantly affecting the performance and reliability of the device. It is also desirable to have a mechanism that reduces performance degradation without sacrificing area or incurring additional cost.

SUMMARY

Embodiments of the present invention include circuits and a method for reducing voltage swing in an integrated circuit (IC).

It should be appreciated that the present invention can be implemented in numerous ways, such as a process an apparatus, a system, a device or a method on a computer readable medium. Several inventive embodiments of the present invention are described below.

In one embodiment, an I/O circuit is disclosed. The I/O circuit includes multiple transistors coupled to a number of switches. Some of the switches are coupled to the source of a few of the transistors while some others are coupled to the drain of some of the transistors. The switches selectively couple the source and drain of the transistors to different signals based on the I/O standard being transmitted. In one embodiment, the transistors include a number of PMOS and NMOS transistors and the switches connect the PMOS and NMOS transistors in a specific manner according to the I/O signal being transmitted by the I/O circuit.

In another embodiment, another I/O circuit is disclosed. The I/O circuit has numerous transistors with a number of programmable switches and a few biasing circuits to provide a desirable voltage level to drive some of the transistors when necessary. The switches selectively couple the gate of the transistors either to the biasing circuits or pull-up/pull-down pre-drivers. In one embodiment, the switches are metal programmable switches that can be used to connect the transistors in the I/O circuit in a stacked configuration based on the I/O signals being transmitted.

In yet another embodiment in accordance with the present invention, a method for transmitting different types of I/O signal is disclosed. The type of I/O signal to be transmitted is determined and a set of switches are set or configured to accommodate either a stacked transistor configuration or a parallel transistor configuration depending on the type of I/O signal being transmitted. A different signal is also transmitted through a second set of switches based on the type of I/O signal being transmitted.

DETAILED DESCRIPTION

The following embodiments describe circuits and a method for reducing voltage swing in an integrated circuit (IC).

It will be obvious, however, to one skilled in the art, that the present invention may be practiced without some or all of these specific details. In other instances, well-known operations have not been described in detail in order not to unnecessarily obscure the present invention.

The embodiments described herein provide techniques to create an IC with configurable transistor arrangements, which ensure that the voltage swing across any one of certain transistors in the I/O does not unduly degrade the transistor. More specifically, the various embodiments allow transistors in the IC to be configured in, for example, a stacked or parallel arrangement, based on the type of I/O standard in use. For example, I/O standards that require higher drive strengths will generally create a larger voltage swing. Previously, this would inevitably cause transistors that experience the full extent of such voltage swings to degrade significantly. The embodiments described herein address this issue by configurably spreading the voltage swings across two or more transistors. Conversely, I/O standards that do not require higher drive strengths will generally create a smaller voltage swing. Such I/O standards do not require a stacked transistor arrangement. In fact, use of a stack transistor arrangement with such I/O standards, i.e., I/O standards that do not require higher drive strength, is generally not employed because the stack transistor arrangement may adversely affect speed and performance. While stacked transistors can be used for I/O standards that do not require higher drive strength, in one embodiment, a parallel configuration is preferred for such I/O standards because transistors in a parallel configuration are closer to output pins and as such may offer speed and performance benefits as propagation paths are shorter in a parallel arrangement compared to a stacked arrangement.

Thus, the following embodiments provide a technique for transistors to be configured based on the I/O standard being transmitted in order to lengthen the lifespan of the transistors and subsequently, that of the circuit and at the same time, maintain circuit performance. Switches are used in the IC to configure transistors in, for example, a stacked or parallel configuration based on the drive strength that the IC is transmitting at any one time. Switches discussed herein can refer to resettable or one-time programmable switches and to polyfuse switches, antifuses, programmable metal switches, via switches, etc or any other type of configurable switch capable of selecting the desired transistor arrangement. The switches may be configured by setting a configuration random access memory bit in one embodiment.

FIG. 1, meant to be illustrative and not limiting, shows an embodiment of a programmable device100in accordance with the present invention. Programmable device100includes logic region115and110elements110. Other auxiliary circuits such as phase-locked loops (PLLs)120for clock generation and timing, can be placed in between I/O elements110and other unoccupied areas in logic region115and in the periphery of programmable device100as shown inFIG. 1. Logic region115may be filled with logic cells that include, among other things, at the most basic level, “logic elements” (LEs). LEs may include look-up table-based logic regions and these logic elements may be grouped into “Logic Array Blocks” (LABs). The logic elements and groups of logic elements or LABs can be configured to perform logical functions desired by the user. In the embodiment shown, region115also includes a plurality of embedded memory blocks118. Each of the memory blocks118may have a different size. For example, some of the memory blocks may be medium-embedded-memory (MEAB) blocks while others may be mega-RAM (MRAM) blocks.

I/O elements110are preferably located around logic region115and the perimeter of programmable device100. I/O elements110may support a variety of single-ended and differential I/O standards. Some examples of single-ended I/O standards include low-voltage transistor transistor logic (LVTTL), high-speed transceiver logic (HSTL), low-voltage complementary metal oxide semiconductor (LVCMOS), etc. These I/O standards usually use voltage levels like 1.5V, 1.8V, 2.5V and 3.3V. Each I/O element or I/O bank110can usually be configured to operate at a particular voltage. A single device like programmable device100can potentially support a variety of different interfaces and each individual I/O bank110can support a different I/O standard with a different voltage level.

FIG. 2, meant to be illustrative and not limiting, shows a typical I/O circuit200with multiple transistors connected to I/O pin220. Transistors202,204, and206are p-channel metal-oxide-semiconductor field-effect (PMOS) transistors while transistors212,214and216are n-channel metal-oxide-semiconductor field-effect (NMOS) transistors. The source of each of PMOS transistors202,204and206is coupled to a power source. In an exemplary embodiment, the power source is a voltage level, e.g., Vdd. The drain of each of PMOS transistors202,204and206are coupled to I/O pin220. Pull-up pre-drivers, PGATE0, PGATE1and PGATE2, are coupled to the gate of transistors202,204and206respectively to drive each of the transistors.

Still referring toFIG. 2, the source of transistors212,214and216are coupled I/O pin220and a power source is coupled to the drain of transistors212,214and216. In an exemplary embodiment, the power source supplies a ground potential to the drain of transistors212,214and216. Transistors212,214and216are driven by pull-down pre-drivers, NGATE0, NGATE1and NGATE2respectively. I/O circuit200may be an I/O circuit in an I/O bank within a programmable device like programmable device100inFIG. 1. In an exemplary embodiment, I/O pin220sends data from I/O circuit200to an external circuit or device. It should be appreciated that I/O pin220can also receive data from an external source.

FIG. 3, meant to be exemplary and not limiting, shows I/O circuit300with multiple switches and bias circuits as an embodiment of the present invention. Switch S1is coupled to the drain of transistor202to selectively couple the drain of transistor202to either I/O pin220or the source of transistor204. The connection to the source of transistor204is controlled by switch S2as switch S2selectively couples the source of transistor204to either the drain of transistor202or a power source. In one embodiment, the power source supplies a voltage level to the source of transistor204. The gate of transistor204is coupled to yet another switch, i.e., switch S3, which selectively couples either biasing circuit320or pull-up pre-driver PGATE1to the gate of transistor204. In one embodiment, biasing circuit320supplies a pre-determined voltage level to drive transistor204when the transistors in I/O circuit300are placed in a stacked configuration.

Similarly, switch S4is coupled to the gate of transistor214to connect either biasing circuit322or pull-down pre-driver NGATE1to the gate of transistor214. In one embodiment, biasing circuits320and322are similar and supply a similar voltage level to each of transistors204and214. In another embodiment, biasing circuits320and322are different circuits. The drain of transistor214is coupled to switch S5which selectively couples the drain of transistor214to either a power source or the source of transistor212. In one embodiment, the power source is a ground potential. Switch S6selectively couples the source of transistor212to either I/O pin220or the drain of transistor214through switch S5.

In one embodiment, switches S1, S2, S3, S4, S5and S6are metal programmable switches in via and metal layers of a programmable device and as such, are configured or connected through the vias. One skilled in the art should appreciate that switches S1, S2, S3, S4, S5and S6can be programmed using CRAM bits. In an exemplary embodiment, CRAM bits are used to store configuration information for each of the switches S1-S6based on the voltage level of signal being transmitted to I/O pin220. In another embodiment, I/O circuit300is a circuit within a PLD and I/O pin220is a pin on the PLD, and the switches in I/O circuit300are programmed by a software utility used to configure the PLD. In such an embodiment, a specific I/O standard with a specific voltage level is selected using the software utility. The software utility then generates an appropriate configuration file for the PLD based on the selection. Switches S1, S2, S3, S4, S5and S6in I/O circuit300are configured to either connect transistors202,204and206and transistors212,214and216in a stacked configuration or a parallel configuration based on the voltage level of the I/O standard being transmitted. One skilled in the art should also appreciate that there may be a few I/O circuits like I/O circuit300in a PLD and each I/O circuit300may be configured to transmit a different I/O standard. Other blocks of such a device are not shown or described so as not to obscure the present invention. Therefore, the switches in I/O circuit300are configured in a specific manner depending on the I/O signal, or rather, the voltage of the I/O signal being transmitted, details of which are shown inFIGS. 4A and 4Band explained in the following paragraphs.

FIG. 4A, meant to be illustrative and not limiting, shows I/O circuit400with switches configured to form a stacked transistor configuration as one embodiment of the present invention. In the embodiment ofFIG. 4A, transistors in I/O circuit400are stacked when transmitting I/O signals at 3.3V or higher voltage. Switch S1, coupled to the drain of transistor202, is configured to connect the drain of transistor202to the source of transistor204through switch S2. Therefore, in one embodiment, the configuration of switch S2is consistent with the configuration of switch S1. Switch S3selects and transmits a voltage level from biasing circuit320to the gate of transistor204to drive transistor204.

Still referring toFIG. 4A, switch S5connects the drain of transistor214to the source of transistor212through switch S6. Switch S4, coupled to the gate of transistor214, couples bias circuit322to the gate of transistor214to drive transistor214. In an exemplary embodiment, bias circuits320and322supply a consistent voltage level to drive transistors204and214respectively. For example, if I/O circuit400is configured such that I/O pin220is driving a 3.3V I/O signal, then bias circuits320and322would supply approximately 1.65V, i.e., half of the total voltage, to drive transistors204and214. However, this is meant to be exemplary and not limiting. One skilled in the art should appreciate that biasing circuits320and322can be built to supply any voltage value that best serves the purpose of I/O circuit400. Therefore, in the embodiment ofFIG. 4A, I/O signals are transmitted through stacked transistors202,204,212and214to I/O pin220. The stacked configuration allows the voltage of the I/O signal transmitted to be distributed across the transistors in I/O circuit400. In one embodiment, transistors206and216are disabled by a software utility used to configure I/O circuit400. In another embodiment, transistors206and216are removed from I/O circuit400based on the voltage level of the I/O signals being transmitted by I/O circuit400. In yet another embodiment, transistors206and216are not removed and are stacked up with transistors202and204and with transistors212and214, respectively.

FIG. 4B, meant to be illustrative and not limiting, shows I/O circuit450configured with all the transistors stacked up as another embodiment in accordance with the present invention. Transistors206and216are not disabled or removed in the configuration shown in I/O circuit450. Instead, additional switches and biasing circuits are used to form a longer stack of transistors. Switch S7couples the drain of transistor204to the source of transistor206through switch S8. An additional biasing circuit, i.e., biasing circuit502, is coupled to the gate of transistor206through switch S9. Similarly, another additional biasing circuit, biasing circuit504, is connected to the gate of transistor216through switch S10. The drain of transistor216is coupled to the source of transistor214through switches S11and S12to stack transistor216up with transistors214and212. In one embodiment, biasing circuits320and322supply one voltage level to transistors204and214while biasing circuits502and504supply another voltage level to transistors206and216. In an exemplary embodiment, the voltage level supplied by biasing circuits502and504is higher than the voltage level supplied by biasing circuits320and322.

As an illustrative example, if I/O circuit500is transmitting a 3.3V I/O standard, biasing circuits320and322would supply approximately 1.1V, or about ⅓ of the total voltage, to drive transistors204and214while biasing circuits502and504would supply approximately 2.2V, or about ⅔ of the total voltage, to drive transistors206and216so that each of all the transistors in I/O circuit500will get about ⅓ of the total voltage. A higher voltage is generally needed at the end of the stacked configuration to drive the whole chain of transistors. Therefore, in this embodiment, biasing circuits502and504supply a higher voltage to drive transistors206and216compared to biasing circuits320and322. In one embodiment, how much voltage passes through each transistor is based on the voltage level of the I/O signal being transmitted and the total number of stacked transistors. Even though only a few transistors are shown in I/O circuit500, one skilled in the art should appreciate that more transistors can be used and different I/O circuits may have a different number of transistors.

FIG. 4C, meant to be illustrative and not limiting, shows I/O circuit480with switches configured to form a parallel transistor configuration as one embodiment of the present invention. In the embodiment illustrated inFIG. 4C, I/O circuit480is configured to transmit an I/O signal with a voltage level lower than 3.3V. Therefore, I/O circuit480generally functions like a typical I/O circuit as that shown inFIG. 2. Switch S1is configured to connect the drain of transistor202to I/O pin220. Switch S2, coupled to the source of transistor204, connects a power source, i.e., a voltage level, to the source of transistor204. The gate of transistor204is coupled to pull-up pre-driver PGATE1through switch S3. Similarly, the gate of transistor214is coupled to pull-down pre-driver NGATE1through switch S4. Switch S5is configured to connect the drain of transistor214to a ground potential while switch S6is configured to connect the source of transistor216to I/O pin220. In one embodiment, transistors202,204and206are driven by pull-up pre-drivers PGATE0, PGATE1and PGATE2respectively, and transistors212,214and216are driven by pull-down pre-drivers NGATE0, NGATE1and NGATE2respectively. Therefore, programmable switches placed in I/O circuits as shown inFIGS. 4A,4B and4C can be used to connect transistors202,204,206,212,214and216in a specific configuration to reduce transistor degradation.

FIG. 5, meant to be illustrative and not limiting, shows method flow500for transmitting different types of I/O signals as another embodiment of the present invention. The type of I/O signal to be transmitted is determined in operation510. In one embodiment, one type of I/O signal is an I/O signal below 3.3V and another type of I/O signal is an I/O signal that is driven by a 3.3V or more voltage level. After the type of I/O signal to be transmitted is determined, a group of switches are configured accordingly. If the I/O signal to be transmitted operates at 3.3V or higher voltage, then the switches are configured to stack up the transistors in the I/O circuit in operation520. A separate signal is then transmitted to another group of switches in operation525. In one embodiment, the signal transmitted may be a pre-determined voltage level supplied by a biasing circuit. In another embodiment, the I/O circuit with the switches configured this way is similar to circuit450shown inFIG. 4A.

Still referring to method flow500ofFIG. 5, if the I/O signal to be transmitted operates below 3.3V, then the switches are configured to connect the transistors in the I/O circuit in a parallel configuration in operation530. Similarly, a different signal is then transmitted to another group of switches in operation535. In one embodiment, the signal transmitted is transmitted from either a pull-up or pull-down pre-driver to the gate of the transistors. In another embodiment, the I/O circuit with the switches configured to connect the transistors in a parallel configuration is similar to circuit480shown inFIG. 4C.

I/O circuits that include a mechanism to connect transistors in a different manner, i.e., connecting transistors in a stacked or parallel configuration based on the type of I/O signals being transmitted at any one time, may have a considerably longer lifespan than a typical I/O circuit with a standard unalterable transistors configuration. Because the switches used do not usually take up much space in a device, using switches to create a configurable transistor stack when needed is a viable and effective solution that reduces voltage swing and transistor degradation in the device.

The embodiments, thus far, were described with respect to integrated circuits. The method and apparatus described herein may be incorporated into any suitable circuit. For example, the method and apparatus may be incorporated into numerous types of devices such as microprocessors or programmable logic devices. Exemplary programmable logic devices include programmable array logic (PAL), programmable logic array (PLA), field programmable logic array (FPLA), electrically programmable logic devices (EPLD), electrically erasable programmable logic device (EEPLD), logic cell array (LCA), field programmable gate array (FPGA), application specific standard product (ASSP), application specific integrated circuit (ASIC), just to name a few.