Device for controlling the operation of internal voltage generator

The present invention discloses a circuit for controlling a timing of overdriving a core voltage (internal voltage) which is a driving voltage of a sense amplifier of a memory device and a duration of the overdriven core voltage, and a method for easily measuring the timing and duration. A device for controlling an operation of an internal voltage generator includes an internal voltage driver for outputting an internal voltage to an output terminal, an internal voltage over-driver for compensating for a potential level of the output terminal, and a controller for controlling an enable timing and a disable timing of the internal voltage over-driver. The controller receives a first control signal and outputs a second control signal, and the second control signal is generated after a predetermined time from reception of the first control signal, an operation of the internal voltage over-driver being controlled according to the second control signal.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a circuit for controlling a timing of overdriving an internal voltage of a memory device, and more particularly to, a circuit for controlling a timing of overdriving a core voltage which is a driving voltage of a sense amplifier of a memory device and a duration of the overdriven core voltage.

2. Description of the Related Art

In general, a memory device is driven by an external power voltage Vext, but internal circuits of the memory device are driven by various levels of internal voltages generated in internal voltage generators of the memory device. Therefore, the levels of the internal voltages must be stabilized to improve the operation of the memory device.

Especially, the read/write operations are major functions of the memory device. It is thus essential to stabilize a core voltage which is one of the internal voltages used for the read/write operations. Here, the core voltage implies an internal voltage used as a driving voltage of a sense amplifier during the read/write operations.

In the auto refresh operation, the read/write operations are performed on a number of memory cells at the same time, which may increase transient current consumption and destabilize the level of the core voltage. Because variations of the core voltage affect the performance and reliability of the memory device, a compensation circuit for restricting rapid variations of the core voltage is generally provided.

FIG. 1is a circuit diagram illustrating a general core voltage generator.

Referring toFIG. 1, a core voltage driver101outputs a core voltage Vcore, and a core voltage over-driver102restricts variations of a level of the core voltage Vcore during the operation of a sense amplifier. That is, while the sense amplifier is operated, the core voltage over-driver102couples an externally-supplied driving voltage VDD to a core voltage terminal, thereby compensating for power.

A driving timing of the core voltage over-driver102is very important. When the core voltage over-driver102is operated much earlier or later than the sense amplifier, effects of the core voltage over-driver102are reduced.

In addition, how long the core voltage over-driver102is operated is also very important. When the core voltage over-driver102is operated for an extended period of time, the core voltage Vcore unnecessarily rises.

However, a circuit for precisely monitoring and tuning an operation timing of the core voltage over-driver102has not been suggested. It is thus difficult to output stable internal voltages.

Furthermore, after a packaging process of a semiconductor device is finished, the internal voltages of the semiconductor device cannot be externally measured.

SUMMARY OF THE INVENTION

Accordingly, the present invention has been made in an effort to solve the problems occurring in the related art, and an object of the present invention is to provide a device for outputting stabilized internal voltages, by precisely controlling an operation of an over-driver for compensating for the internal voltages.

Another object of the present invention is to provide a method for measuring internal voltages through external pins after finishing a packaging process of a semiconductor device.

In order to achieve the above objects, according to one aspect of the present invention, there is provided a device for controlling an operation of an internal voltage generator, including: an internal voltage driver for outputting an internal voltage to an output terminal; an internal voltage over-driver for compensating for a potential level of the output terminal; and a controller for controlling an enable timing and a disable timing of the internal voltage over-driver.

Preferably, the controller receives a first control signal and outputs a second control signal, and the second control signal is generated after a predetermined time from reception of the first control signal, an operation of the internal voltage over-driver being controlled according to the second control signal.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

FIG. 2ais a block diagram illustrating a device for controlling an operation of an internal voltage generator in accordance with the present invention. An internal voltage outputted from the internal voltage generator can be used as a driving voltage for driving, for example, a sense amplifier of a memory device.

As illustrated inFIG. 2a, the device for controlling the operation of the internal voltage generator includes an internal voltage driver21for outputting an internal voltage Vint to an output terminal, an internal voltage over-driver22for compensating for a potential level of the output terminal, and a controller23for controlling an enable timing and a disable timing of the internal voltage over-driver22.

InFIG. 2a, the internal voltage driver21corresponds to the core voltage driver101ofFIG. 1, and the internal voltage over-driver22corresponds to the core voltage over-driver102ofFIG. 1, which can be constituted in the same manner. In addition, the internal voltage Vint can be the core voltage Vcore mentioned inFIG. 1.

Here, the controller23receives a control signal sest30and outputs a control signal sense_enz. The control signal sest30is enabled to perform a predetermined internal operation. For example, the control signal sest30can be generated under an active command of the memory device. The control signal sense_enz is generated after a predetermined time from reception of the control signal sest30, for controlling an operation of the internal voltage over-driver22.

FIG. 2bis a circuit diagram illustrating the controller23ofFIG. 2a.

As shown inFIG. 2b, the controller23includes a delay unit200for receiving the control signal sest30, a PMOS transistor TR21coupled between a power voltage Vext and a node N3, an NMOS transistor TR22coupled between the node N3and a ground terminal, a delay unit210using the node N3as an input terminal, and a controller output unit220for receiving the output signals from the delay unit200and the delay unit210. The controller output unit220is comprised of a NAND gate NAND21, and an even number of inverters coupled to an output terminal of the NAND gate NAND21. The output signal from the controller output unit220is the control signal sense_enz for controlling the operation of the internal voltage over-driver22ofFIG. 2a.

A transmission path of the control signal sest30supplied to the delay unit200is determined by switches PG1, PG2, PG3and PG4which are selectively turned on. The switches PG1, PG2, PG3and PG4are controlled according to test mode signals tm0, tm1, tm2and tm3. The test mode signals tm0, tm1, tm2and tm3determine a delay time of the delay unit200, which will later be explained in detail with reference toFIG. 5a.

An output node N1of the delay unit200is coupled to an input terminal of the NAND gate NAND21.

Still referring toFIG. 2b, the controller output unit220receives the output signal from the delay unit200and the output signal from the delay unit210. The output from the controller output unit220is the control signal sense_enz.

The control signal sense_enz is supplied to a gate of the PMOS transistor TR21coupled between the power voltage. Vext and the node N3.

The delay unit210using the node N3as the input terminal receives a signal from the node N3, delays the signal for a predetermined time, and outputs an inverted signal. That is, the input and output signals of the delay unit210have opposite phases.

The delay unit210controls an RC delay time by selectively coupling a plurality of MOS transistors n11, n12, n13, n14, n15and n16respectively to a plurality of PMOS capacitors. The plurality of MOS transistors n11, n12, n13, n14, n15and n16are coupled to the signal transmission line, namely the node N3according to test mode signals tm_d0, tm_d1, tm_d2, tm_d3z, tm_d4zand tm_d5z, to contribute to determination of the delay time. The test mode signals tm_d0, tm_d1, tm_d2, tm_d3z, tm_d4zand tm_d5zwill later be explained in detail with reference toFIG. 5b.

A probing pad230is a signal detection pad. Therefore, after a packaging process of a semiconductor device is finished, an operation period of the control signal sense_enz can be externally precisely measured through pins coupled to the probing pad230, which will later be explained with reference toFIG. 7.

The output signal from the delay unit200is inverted by an inverter inv0, and supplied to a gate of the NMOS transistor TR22. As depicted inFIG. 2b, the NMOS transistor TR22is disposed between the node N3and the ground.

FIG. 3is a waveform diagram illustrating one example of the signals sest30and sense_enz of the circuit ofFIG. 2b. Especially,FIG. 3shows an operation of the control signal sense_enz, when the delay time of the delay unit200is controlled according to the test mode signals tm0, tm1, tm2and tm3.

As shown inFIG. 3, while the control signal sest30is enabled in a high level for a predetermined time, a timing of enabling the control signal sense_enz in a low level and a timing of disabling the control signal sense_enz in a high level can be controlled according to logical levels of the test mode signals tm0, tm1, tm2and tm3.

That is, when the delay time of the delay unit200ofFIG. 2bis the shortest (when tm1has a high level), the timing of enabling the control signal sense_enz in a low level is the earliest.

Conversely, when the delay time of the delay unit200ofFIG. 2bis the longest (when tm3has a high level), the timing of enabling the control signal sense_enz in a low level is the latest.

FIG. 4is a waveform diagram illustrating another example of the signals sest30and sense_enz of the circuit ofFIG. 2b. Especially,FIG. 4shows that the enable timing and period of the control signal sense_enz can be controlled according to variations of the delay time of the delay unit200and the delay time of the delay unit210.

As depicted inFIG. 4, the timing of enabling the control signal sense_enz in a low level is identical. As explained inFIG. 3, it can be controlled by measuring the delay time of the delay unit200.

The timing of disabling the control signal sense13enz in a high level can be adjusted by controlling the delay time of the delay unit210. Accordingly, the period of enabling the control signal sense_enz in a low level can be controlled.

That is, when the delay time of the delay unit210is controlled by using the test mode signals tm_d0, tm_d1, tm_d2, tm_d3z, tm_d4zand tm_d5z, the disable timing of the control signal sense_enz can be controlled. On the other hand, as shown inFIG. 4, tm_delay0is used instead of tm_d0, but denotes the same signal. It applies to the other test mode signals.

For example, still referring toFIG. 4, when the test mode signals tm_d0, tm_d1, tmd2, tm_d3z, tm_d4zand tm_d5zhave high levels to make the delay time of the delay unit210the longest, the disable timing of the control signal sense_enz becomes the latest. Therefore, when the delay time of the delay unit200is constant, the enable pulse period of the control signal sense_enz is the longest.

Conversely, when the test mode signals tm_d0, tm_d1, tm_d2, tm_d3z, tm_d4zand tm_d5zhave low levels to make the delay time of the delay unit210the shortest, the disable timing of the control signal sense_enz becomes the earliest. Thus, when the delay time of the delay unit200is constant, the enable pulse period of the control signal sense_enz is the shortest.

FIGS. 5aand5bare circuit diagrams illustrating a decoder circuit for generating the test mode signals tm0, tm1, tm2and tm3for the delay unit200of the circuit ofFIG. 2band the test mode signals tm_d0, tm_d1, tm_d2, tm_d3z, tm_d4zand tm_d5zfor the delay unit210thereof, respectively.

As illustrated inFIG. 5a, the decoder circuit receives a test mode entry signal tm entry for notifying test mode entry and test mode address signals tm_start0and tm_start1for controlling the enable timing of the control signal sense_enz, and outputs the test mode signals tm0, tm1, tm2, and tm3. For information, one detailed example of a fuse means ofFIG. 5ais shown inFIG. 6. InFIG. 5a, the decoder circuit includes a plurality of NAND gates NA0–NA9, a NOR gate NO1and a plurality of inverters. An initial state of the fuse means maintains a high level, which will later be explained with reference toFIG. 6.

The operation of the decoder circuit ofFIG. 5awill now be described.

When the test mode entry signal tm_entry has a low level, the output signals from the NAND gates NA0and NA1have high levels. Accordingly, the NAND gates NA2, NA3and NA4output high level signals, and the NAND gate NA5outputs a low level signal. Logical levels of the test mode signals tm3, tm1and tm2which are the output signals from the NAND gates NA6, NA7and NA8are low. Therefore, a logical level of the test mode signal tm0which is the output signal from the NOR gate NO1is high. As mentioned above, when the test mode entry signal tm_entry has a low level (namely, not in the test mode), only the test mode signal tm0has a high level.

When the test mode entry signal tm entry has a high level, logical levels of the test mode signals tm0, tm1, tm2and tm3are determined according to the test mode address signals tm_start0and tm_start1. That is, when the test node address signals tm_start0and tm_start1have low levels (L and L), only the test mode signal tm0has a high level. When the test mode address signals tm_start0and tm_start1have low and high levels (L and H), only the test mode signal tm1has a high level. When the test mode address signals tm_start0and tm_start1have high and low levels (H and L), only the test mode signal tm2has a high level. When the test mode address signals tm_start0and tm_start1have high levels (H and H), only the test mode signal tm3has a high level.

As depicted inFIG. 5b, the decoder circuit outputs the test mode signals tm_d0˜tm_d5zfor controlling the disable timing of the control signal sense_enz. The decoder circuit receives test mode address signals tm_delay0˜tm_delay5for controlling the disable time of the control signal sense_enz.

The decoder circuit ofFIG. 5bincludes a plurality of NAND gates NA0˜NA11and a plurality of inverters. The circuit ofFIG. 6is used as a fuse means. Thus, the output signal outputted from the fuse means in an initial state has a high level.

When the test mode entry signal tm_entry has a low level (namely, not in the test mode), the test mode signals tm_d0˜tm_d2have low levels, and the test mode signals tm_d3z˜tm_d5zhave high levels.

When the test mode entry signal tm_entry has a high level, logical levels of the test mode signals tm_d0˜tm_d2and tm_d3z˜tm_d5zcan be controlled according to logical levels of the test mode address signals tm_delay0˜tm_delay5.

FIG. 6is a circuit diagram illustrating the fuse means ofFIGS. 5aand5b.

As shown inFIG. 6, the initial state of the fuse means has a high level in a fuse-coupled state and a low level in a fuse-cut state. In the case that the fuse is cut inFIGS. 5aand5bso that the output from the fuse means can have a low level, logical levels of the test mode signals can be determined. It is thus possible to set the optimum enable period of the control signal sense_enz of the circuit of FIG.2b.

FIG. 7is a circuit diagram illustrating a method for measuring the control signal sense_enz and the internal voltage Vcore in a wafer or packaging state.FIG. 7also shows data drivers driven by a power voltage Vddq and a ground voltage Vssq. Here, up signal controls a pull-up driving transistor, and dnz signal controls a pull-down driving transistor.

Referring toFIG. 7, when the test mode entry signal tm_entry has a high level, the control signal sense_enz and the internal voltage Vcore are outputted through data pads DQ0and DQ1.

Although not illustrated, operations of the data drivers coupled to the data pads DQ0and DQ1are intercepted in the test mode. Therefore, after the test mode is ended, the data pads DQ0and DQ1are used for the data drivers.

As described earlier, in accordance with the present invention, the operation of the internal voltage over-driver ofFIG. 2acan be appropriately controlled by adjusting the enable period of the internal control signal. As a result, stabilized internal voltages can be provided to internal circuits.

As apparent from the above description, the enable period of the signal for controlling generation of the internal voltages of the memory device can be freely controlled.

In addition, the internal control signal can be measured even in the packaging state.

Furthermore, when the memory device has a defect, it can be directly corrected in the wafer level by using the fuse means.

As a result, the test price can be cut down and the yield can be improved without requiring additional expenses.