Memory having read assist device and method of operating the same

A memory includes a first bit line, a memory cell coupled to the first bit line, and a read assist device coupled to the first bit line. The read assist device is configured to pull a first voltage on the first bit line toward a predetermined voltage in response to a first datum being read out from the memory cell. The read assist device includes a first circuit configured to establish a first current path between the first bit line and a node of the predetermined voltage during a first stage. The read assist device further includes a second circuit configured to establish a second current path between the first bit line and the node of the predetermined voltage during a second, subsequent stage.

CROSS-REFERENCE TO RELATED APPLICATION

The present application relates to U.S. patent application Ser. No. 12/913,087, filed on Oct. 27, 2010, which is incorporated herein by reference in its entirety.

BACKGROUND

Besides processors, memories are main parts of computing systems and electronic devices. The performance of a memory, such as capacity, access speed, power consumption etc. impacts the overall performance of the system or electronic device. Developments are constantly sought to improve performance of memories.

DETAILED DESCRIPTION

It is to be understood that the following disclosure provides many different embodiments or examples, for implementing different features of various embodiments. Specific examples of components and arrangements are described below to simplify the present disclosure. The inventive concept may, however, be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein; rather, these embodiments are provided so that this description will be thorough and complete, and will fully convey the inventive concept to those of ordinary skill in the art. It will be apparent, however, that one or more embodiments may be practiced without these specific details.

The drawings are not drawn to scale, and include certain features that are exaggerated for clarity. Like reference numerals in the drawings denote like elements. The elements and regions illustrated in the figures are schematic in nature, and thus relative sizes or intervals illustrated in the figures are not intended to limit the scope of the inventive concept.

FIG. 1is a schematic circuit diagram of a segment of a memory100in accordance with some embodiments. The memory100includes one or more memory cells102, one or more pairs of bit lines BLU/BLBU, BLL/BLBL, and one or more global bit lines GBL. One or more memory cells102are coupled to each pair of bit lines to form one or more memory blocks. Specifically, multiple memory cells102are coupled to the pair of bit lines BLU and BLBU to form an upper half120U of a memory block120, whereas multiple memory cells102are coupled to the pair of bit lines BLL and BLBL to form a lower half120L of the memory block120. One or more memory blocks is coupled to a global bit line. Specifically, the memory block120is coupled to the global bit line GBL. The memory100further includes a plurality of word lines WL(0)-WL(2k−1) (where k is an integer) coupled to the memory cells102. The memory100has a lower half130L and an upper half130U. In the lower half130L, the memory cells102are coupled to one half of the word lines, i.e., the word lines WL(0)-WL(k−1). In the upper half130U, the memory cells102are coupled to the other half of the word lines, i.e., the word lines WL(k)-WL(2k−1). InFIG. 1, WT and WC denote pairs of write data lines.

Each memory block120includes bit line pre-charging circuits104L,104U, and read assist devices106L,106U in the corresponding lower and upper halves130L,130U of the memory100. The memory block120further includes a write pass gate circuit108, a sensing amplifier110, and a pull-down circuit112all of which are common for both the lower and upper halves. The sensing amplifier110is connected to the bit lines BLU and BLL to detect a state of the bit lines BLU and BLL in a single-ended sensing scheme (i.e., one bit line BLU, rather than both bit lines BLU/BLBU, is used for the sensing operation). In some embodiments, a dual-rail sensing scheme is used where the sensing amplifier110uses both bit lines, e.g., BLU/BLBU, for the sensing operation.

In this example, the sensing amplifier110is implemented as a NAND gate, although other configurations are also within the scope of this disclosure. The bit line pre-charging circuits104L,104U are similarly configured and each include two p-channel metal-oxide semiconductor (PMOS) transistors. The read assist devices106L,106U are similarly configured. The memory block120in particular and the memory100in general have a symmetrical structure. In some embodiments, the memory100does not necessarily have a symmetrical structure. For example in some embodiments, the upper half of the memory100, including the word lines WL(k)-WL(2k−1), the associated memory cells102, the bit line pre-charging circuit104U and the read assist device106U, is omitted.

For read and/or write operations, the bit line pre-charging circuits104L,104U are arranged to pre-charge the corresponding bit lines BLU, BLL, and the read assist devices106L,106U are arranged to pull the pre-charged bit lines toward a predetermined voltage. The write pass gate circuit108is arranged to enable or disable writing to the memory cells102in the memory block120. In some embodiments, when a logical “0” is read from a memory cell102in the memory block120, the corresponding bit line (e.g., BLU) is pulled down to a ground voltage VSS, the sensing amplifier110outputs, at a node BLPD, a high voltage to the pull-down circuit112which, in turn, is opened to pull the global bit line GBL to the ground voltage. When a logical “1” is read from a memory cell102in the memory block120, the corresponding bit line (e.g., BLU) is pulled up to a power supply voltage VDD, the sensing amplifier110outputs, at the node BLPD, a low voltage to the pull-down circuit112which, in turn, is closed and leaves the global bit line GBL at a global bit line pre-charge voltage.

The memory access speed depends on several factors, including how fast the read assist devices106L,106U pull the voltages on the corresponding bit lines to a predetermined voltage, e.g., the ground voltage. Circuitry for read assist devices and memories using such devices in accordance with some embodiments is described below.

In some embodiments, the operation of a read assist device in a memory includes first and second stages during which corresponding first and second current paths are established between a bit line and a node of a predetermined voltage. The first current path increases a transition speed of a voltage on the bit line toward the predetermined voltage during the first stage. The second current path further increases the transition speed during the second stage. As a result, the transition time is shortened and the access speed of the memory is increased.

FIG. 2Ais a schematic block diagram of a memory200A in accordance with some embodiments. The memory200A includes a bit line BL, a memory cell202coupled to the bit line BL, a read assist device206, and a control circuit210. The read assist device206is coupled to the bit line BL and is configured to pull a voltage on the bit line BL toward a predetermined voltage Vp of a node220in response to a datum being read out from the memory cell202. In some embodiments, the predetermined voltage is the ground voltage VSS in a pull-down arrangement in which the voltage of the bit line BL is pulled down to the ground. In some embodiments, the predetermined voltage is a power supply voltage VDD in a pull-up arrangement in which the voltage of the bit line BL is pulled up to power supply voltage VDD. In some embodiments, the predetermined voltage is a voltage between the ground voltage VSS and the power supply voltage VDD or another voltage level depending on applications and/or other considerations.

The read assist device206includes a first circuit216and a second circuit226. The first circuit216is configured to establish a first current path I1between the bit line BL and the node220during a first stage, and the second circuit226is configured to establish a second current path I2between the bit line BL and the node220during a second, subsequent stage. When the first current path I1is established, a current flows along the first current path I1between the bit line BL and the node220. Accordingly, the voltage on the bit line BL is pulled toward the predetermined voltage Vp of the node220faster than when no current paths are established. Subsequently, the second current path I2is established, and the current flows along both the first current path I1and second current path I2, which are parallel with each other, thereby pulling the voltage on the bit line BL toward the predetermined voltage Vp faster than when only the first current path I1is established. As a result, the transition speed of the voltage on the bit line toward the predetermined voltage Vp is increased which, in turn, increases the access speed.

The first circuit216is enabled by a first stage enabling signal ST1to establish the first current path I1, and the second circuit226is enabled by a second stage enabling signal ST2to establish the second current path I2. The first stage enabling signal ST1and second stage enabling signal ST2are supplied from the control circuit210to the corresponding first circuit216and second circuit226. The first stage enabling signal ST1is supplied first to the first circuit216during the first stage, and then the second stage enabling signal ST2is supplied to the second circuit226during the second stage. In some embodiments, the first stage enabling signal ST1is maintained during the whole second stage to maintain both the first current path I1and the second current path12during the whole second stage. In some embodiments, the first stage enabling signal ST1is maintained at the beginning of the second stage and then discontinued toward the end of the second stage. The reason is that the presence of multiple current paths provides a higher transition speed increasing effect at the beginning of the transition, than at the end. Power consumption is reduced by discontinuing the first stage enabling signal ST1when the presence of the first current path I1(in addition to the second current path I2) has become less effective.

In some embodiments, the control circuit210provides the second stage enabling signal ST2by delaying the first stage enabling signal ST1. For this purpose, the control circuit210includes a delay circuit, for example, as disclosed in U.S. patent application Ser. No. 12/913,087, filed on Oct. 27, 2010 which is incorporated herein by reference in its entirety.

FIG. 2Bis a schematic circuit diagram of a memory200B in accordance with some embodiments. Similar to the memory200A, the memory200B includes the bit line BL, the memory cell202coupled to the bit line BL, the read assist device206, and the control circuit210(which is not illustrated inFIG. 2Bfor simplicity). The memory200B further includes a bit line bar BLB which defines together with the bit line BL a pair of bit lines. The memory cell202is coupled to the pair of bit lines.

The read assist device206further includes, in addition to the first circuit216and second circuit226, a third circuit236and a fourth circuit246. The third circuit236and fourth circuit246are coupled to pull a voltage on the bit line bar BLB toward the predetermined voltage Vp in response to a second datum being read out from the memory cell202. The third circuit236is configured to establish a third current path I3between the bit line bar BLB and the node220during the first stage, upon application of the first stage enabling signal ST1from the control circuit210to the third circuit236. The fourth circuit246is configured to establish a fourth current path I4between the bit line bar BLB and the node220during the second stage, upon application of the second stage enabling signal ST2from the control circuit210to the fourth circuit246. The third current path I3and fourth current path I4increase the transition speed of the voltage on the bit line bar BLB toward the predetermined voltage Vp in a manner similar to the first current path I1and second current path I2increasing the transition speed of the voltage on the bit line BL toward the predetermined voltage Vp.

Unlike the first circuit216and third circuit236which are configured to pull the voltage on the bit line BL toward the predetermined voltage Vp in response to a first datum being read out from the memory cell202, the third circuit236and fourth circuit246are configured to pull the voltage on the bit line bar BLB toward the predetermined voltage Vp in response to a second datum being read out from the memory cell202. For example, when the first datum, e.g., a logic “0,” is read out from the memory cell202, the third circuit236and fourth circuit246are disabled by a voltage supplied from the bit line BL via a cross-coupling connection234, and the first circuit216and second circuit226are enabled by a voltage supplied from the bit line BL via a cross-coupling connection212. As a result, the voltage on the bit line BL is pulled toward the predetermined voltage Vp, e.g., the ground voltage VSS, by the first current path I1and second current path I2. When the second datum, e.g., a logic “1,” is read out from the memory cell202, the first circuit216and the second circuit226are disabled whereas the third circuit236and the fourth circuit246are enabled. As a result, the voltage on the bit line bar BLB is pulled toward the predetermined voltage Vp, e.g., the ground voltage VSS, by the third current path I3and fourth current path I4. An effect similar to that of the memory200A is therefore achieved in the memory200B.

FIG. 3is a schematic circuit diagram of a read assist device300for a memory in accordance with some embodiments. In the read assist device300, first through fourth switches316,326,336,346perform the functions of the corresponding first through fourth circuits216,226,236,246in the memory200B, i.e., to establish the corresponding first through fourth current paths I1, I2, I3, I4. Any suitable configuration for a switch is usable for each of the first through fourth switches316,326,336,346. In some embodiments, the circuitry is simplified in order to maximize the operating speed and minimize power consumption, by implementing one or more of the first through fourth switches316,326,336,346as a single transistor, e.g., an n-channel metal-oxide semiconductor (NMOS) transistor or a p-channel metal-oxide semiconductor (PMOS) transistor.

The first and third switches316,336together define a first input stage for the read assist device300. The second and fourth switches326,346together define a second input stage for the read assist device300. Besides the first and second input stages, the read assist device300further includes first and second output stages defined by corresponding first and second current sources370,380. Any suitable configuration for a current source is usable for each of the first and second current sources370,380. In some embodiments, the circuitry is simplified in order to maximize the operating speed and minimize power consumption, by implementing one or both of the first and second current sources370,380as a single transistor, e.g., an NMOS transistor or a PMOS transistor.

The first and third switches316,336, which together define the first input stage, are commonly connected to a first intermediate node651which is then connected to the node220via the first current source370. The second and fourth switches326,346, which together define the second input stage, are commonly connected to a second intermediate node352which is then connected to the node220via the second current source380. The first current source370commonly coupling the first and third switches316,336to the node220of the predetermined voltage Vp is enabled during the first stage, by the first stage enabling signal ST1supplied from a control circuit, e.g., the control circuit210. When the first current source370is enabled, a current flows from the bit line BL or the bit line bar BLB (depending on whether a logical “0” or a logical “1” is read from a memory cell coupled to the pair of bit lines), through the corresponding first switch316or third switch336, to the first current source370and then to the node220. The voltage transition speed on the corresponding bit line BL or the bit line bar BLB is thus increased.

The second current source380commonly coupling the second and fourth switches326,346to the node220of the predetermined voltage Vp is enabled during the second stage, by the second stage enabling signal ST2supplied from the control circuit210. When the second current source380is enabled, an additional current flows from the bit line BL or the bit line bar BLB (depending on whether a logical “0” or a logical “1” is read from the memory cell coupled to the pair of bit lines), through the corresponding second switch326or fourth switch346, to the second current source380and then to the node220. The voltage transition speed on the corresponding bit line BL or the bit line bar BLB is thus increased further. In some embodiments, the first current source370is enabled during both the first and second stages.

In some embodiments, the first through fourth switches316,326,336,346are all commonly connected to an intermediate node (e.g.,351). The first and second current sources370,380are coupled in parallel between the common intermediate node351and the node220having the predetermined voltage Vp.

In some embodiments, a single current source (e.g.,370) is coupled between the first through fourth switches316,326,336,346and the node220. The second stage enabling signal ST2is supplied to enable the second and fourth switches326,346and/or the first stage enabling signal ST1is supplied to enable the first and third switches316,336. The single current source370is enabled during both the first and second stages.

FIG. 4is a schematic circuit diagram of a read assist device400for a memory in accordance with some embodiments. The read assist device400includes first through sixth transistors M1-M6. The first and fifth transistors M1, M5are coupled in series between the bit line BL and the node220. The first and second transistors M1, M2are coupled in parallel. The third and sixth transistors M3, M6are coupled in series between the bit line bar BLB and the node220. The third and fourth transistors M3, M4are coupled in parallel. The fifth and sixth transistors M5, M6are cross-coupled, with a gate of the fifth transistor M5coupled to the bit line bar BLB and a gate of the sixth transistor M6coupled to the bit line BL.

As used herein, two transistors are coupled “in series” if one of a source or a drain of one transistor is coupled to one of a source or a drain of the other transistor to enable a current, when both transistors are in the open or enabled state, to flow serially through the transistors. Particularly, when the transistors are of the same type, the source of one transistor is coupled to the drain of the other transistor. More particularly, in some embodiments where the first through sixth transistors M1-M6are NMOS transistors, the first and fifth transistors M1, M5are coupled in series by coupling the source of the first transistor M1to the drain of the fifth transistor M5. Similarly, the third and sixth transistors M3, M6are coupled in series by coupling the source of the third transistor M3to the drain of the sixth transistor M6.

As used herein, two transistors are coupled “in parallel” if each of a source and a drain of one transistor is coupled to a corresponding one of a source and a drain of the other transistor to enable currents, when both transistors are in the open or enabled state, to flow in parallel through the transistors. Particularly, when the transistors are of the same type, the sources of the transistors are coupled together and the drains of the transistors are coupled together. More particularly, in some embodiments where the first through sixth transistors M1-M6are NMOS transistors, the first and second transistors M1, M2are coupled in parallel by coupling the source of the first transistor M1to the source of the second transistor M2, and the drain of the first transistor M1to the drain of the second transistor M2. Similarly, the third and fourth transistors M3, M4are coupled in parallel by coupling the source of the third transistor M3to the source of the fourth transistor M4, and the drain of the third transistor M3to the drain of the fourth transistor M4.

The fifth transistor M5and sixth transistor M6are commonly coupled to an intermediate node420. The read assist device400further includes a seventh transistor M7coupling the intermediate node420to the node220of the predetermined voltage Vp. Thus, the seventh transistor M7commonly couples the fifth and sixth transistors M5, M6to the node220. The read assist device400also includes an eighth transistor M8coupled in parallel to the seventh transistor M7. In some embodiments where the first through eighth transistors M1-M8are NMOS transistors, the sources of the cross-coupled fifth transistor M5and sixth transistor M6are commonly coupled via the intermediate node420to the drains of the seventh transistor M7and the eighth transistor M8.

The first through fourth transistors M1-M4perform the functions of the corresponding first through fourth circuits216,226,236,246of the read assist device206in the memory200B and/or the functions of the corresponding first through fourth switches316,326,336,346of the read assist device300. The cross-coupled fifth transistor M5and sixth transistor M6define an enabling circuit for selectively enabling the first and second transistors M1, M2or the third and fourth transistors M3, M4depending on a datum (e.g., a logical “0” or a logical “1”) being read out from a memory cell coupled to the pair of bit lines BL/BLB. The seventh transistor M7and eighth transistor M8perform the functions of the corresponding first current source370and second current source380in the read assist device300.

In some embodiments, one of the seventh transistor M7or eighth transistor M8is omitted. The read assist device400functions similarly to the read assist device300when one of the first current source370or second current source380is omitted.

In some embodiments, for example, in a read assist device500for a memory inFIG. 5, both the seventh transistor M7and eighth transistor M8are omitted. The fifth transistor M5and sixth transistor M6are coupled to the node220of the predetermined voltage Vp. The read assist device500functions similarly to the read assist device206of the memory200B.

Returning toFIG. 4, a control circuit, such as the control circuit210, is coupled to the gates of the first through fourth, seventh and eighth transistors M1-M4, M7, M8to enable the transistors. Specifically, the first and third transistors M1, M3are enabled before the second and fourth transistors M2, M4. The first and third transistors M1, M3are enabled by corresponding enabling signals SAE1and SAE1′. The eighth transistor M8is enabled simultaneously with the second and fourth transistors by an enabling signal SAE2. The seventh transistor M7is enabled, by an enabling signal SEGD, before the first transistor M1. The first transistor M1is enabled by the enabling signal SAE1before the third transistor M1.

FIGS. 6A and 6Bare various timing diagrams of voltages during operation of a memory having the read assist device400in accordance with some embodiments. Specifically, the operation of reading a logical “0” is described with respect to the bit line BL. The operation of reading a logical “1” is performed similarly with respect to the bit line bar BLB.

In some embodiments, the bit line BL and the bit line bar BLB are pre-charged to a pre-charge voltage Vpc.

Reference numerals651,661and691inFIG. 6Aindicate a voltage at the output of a sensing amplifier (e.g., the node BLPD inFIG. 1), the voltage on the bit line BL, and the voltage on the bit line bar BLB in the absence of a read assist device. When a memory cell is selected by an appropriate voltage WL on the corresponding word line to output a logical “0” contained in the memory cell, the voltage661on the bit line BL begins to transit from the pre-charge voltage Vpc toward the ground voltage VSS. Without a read assist device, the transition speed is slow under certain circumstances. With such a slow transition speed, at the end of the signal WL, the voltage661on the bit line BL reaches a level671which is insufficient for the sensing amplifier to output a correct reading of the datum (logical “0”) being read. The voltage651at the output BLPD of the sensing amplifier indicates a failed read at681.

Reference numerals652,662and692inFIG. 6Aindicate the voltage at the output of the sensing amplifier (e.g., the node BLPD inFIG. 1), the voltage on the bit line BL, and the voltage on the bit line bar BLB in a read assist device with a single stage. When a memory cell is selected by an appropriate voltage WL on the corresponding word line to output a logical “0” contained in the memory cell, the voltage662on the bit line BL begins to transit from the pre-charge voltage Vpc toward the ground voltage VSS. When the single stage of the read assist device is enabled by the enabling signal SAE1, the transition speed is faster than when no read assist device is used, i.e., the slope of the voltage662is higher than the slope of the voltage661. With such a faster transition speed, at or near the end of the signal WL, the voltage662on the bit line BL reaches a level672which is sufficient for the sensing amplifier to output a correct reading of the datum (logical “0”) being read. The voltage652at the output BLPD of the sensing amplifier indicates a successful read at682.

Reference numerals653,663and693inFIG. 6Aindicate the voltage at the output of the sensing amplifier (e.g., the node BLPD inFIG. 1), the voltage on the bit line BL, and the voltage on the bit line bar BLB in a read assist device with a two stages in accordance with some embodiments. When a memory cell is selected by an appropriate voltage WL on the corresponding word line to output a logical “0” contained in the memory cell, the voltage663on the bit line BL begins to transit from the pre-charge voltage Vpc toward the ground voltage VSS. When the first stage of the read assist device is enabled by the enabling signal SAE1, a transition speed comparable to that of the voltage662is achieved. Afterwards, when the second stage of the read assist device is enabled by the enabling signal SAE2, the transition speed is further increased and becomes faster than when a read assist device with a single stage is used, i.e., the slope of the voltage663becomes higher than the slope of the voltage662. With such an even faster transition speed, well before the end of the enabling signal SEGD, the voltage663on the bit line BL reaches a level673which is sufficient for the sensing amplifier to output a correct reading of the datum (logical “0”) being read. The voltage653at the output BLPD of the sensing amplifier indicates a successful read at683which occurs earlier than the successful read682achieved by a read assist device with a single stage.

Thus, the dual-stage read assist device in accordance with some embodiments achieves a high successful read rate and at a fast access speed. Because a successful read is achievable at an early time, the durations of one or more of the signals WL, SAE1and SAE2are reduced in some embodiments to reduce power consumption.

A detailed explanation of how the voltage on the bit line BL transits during the reading operation of a logical “0” in the read assist device400is given with respect toFIG. 6B. In some embodiments, at the beginning of the reading operation, the bit line BL and the bit line bar BLB are pre-charged to a pre-charge voltage Vpc.

An enabling signal SEGD is applied to enable the seventh transistor M7when a memory cell is selected by a signal WL to output the logical “0” stored in the memory cell on the bit line BL and the bit line bar BLB. The voltage on the bit line bar BLB is pulled high, e.g., toward the power supply voltage VDD and the voltage on the bit line BL begins its transition toward a predetermined voltage Vp, e.g., the ground voltage VSS, with a transition speed S0comparable to that of the voltage661when no read assist device is used.

The high voltage on the bit line bar BLB is applied to the gate of the fifth transistor M5and enables (i.e., opens) the fifth transistor M5. As the voltage on the bit line BL reduces the voltage on the gate of the sixth transistor M6coupled to the bit line BL is also reduced and eventually disables (i.e., closes) the sixth transistor M6. With the closing of the sixth transistor M6, the voltage on the bit line bar BLB remains at the high voltage regardless of the states of the third transistor M3and fourth transistor M4in the subsequent stages.

At the beginning of the first stage, a first enabling signal SAE1, which corresponds to the first stage enabling signal ST1, is applied to the gate of the first transistor M1to enable the first transistor M1. As a result, a first current path is established between the bit line BL and the node or ground220through the opened first transistor M1, fifth transistor M5and seventh transistor M7. Such a first current path pulls the voltage on the bit line BL faster toward the ground, at a transition speed S1higher than the transition speed S0and comparable to that of the voltage662.

At the beginning of the second stage, a second enabling signal SAE2, which corresponds to the second stage enabling signal ST2, is applied to the gate of the second transistor M2to enable the second transistor M2. The second enabling signal SAE2is also applied to the gate of the eighth transistor M8to enable the eighth transistor M8. As a result, a second current path is established between the bit line BL and the node or ground220through the opened second transistor M2, fifth transistor M5and eighth transistor M8. Such a second current path further pulls the voltage on the bit line BL even faster toward the ground, at a transition speed S2higher than the transition speed S1.

The third transistor M3is also enabled during the first stage but does not significantly affect the operation because the sixth transistor M6is disabled. The fourth transistor M4is also enabled during the second stage but does not significantly affect the operation because the sixth transistor M6is disabled.

A similar operation of reading a logical “1” is performed with respect to the bit line bar BLB. Summarily, the first transistor M1, second transistor M2and fifth transistor M5are disabled, a third current path is established during the first stage via the opened third transistor M3, sixth transistor M6and seventh transistor M7, and a fourth current path is established during the second stage via the opened fourth transistor M4, sixth transistor M6and eighth transistor M8.

In some embodiments, during the first stage, the enabling signal SAE1′ is applied to the third transistor M3not earlier than the first enabling signal SAE1applied to the first transistor M1. The reason is to prevent a logical “0” read disturbance which is possible if the sixth transistor M6is not fully closed at the time the third transistor M3is turned on by the enabling signal SAE1′.

In some embodiments, the first enabling signal SAE1is applied to the first transistor M1not earlier than the signal SEGD applied to the seventh transistor M7(i.e., not earlier than the memory cell selection by a signal WL on the corresponding word line). The reason is to prevent a logical “1” read disturbance which is possible if the fifth transistor M5is not fully closed at the time the seventh transistor M7is turned on by the signal SEGD.

In some embodiments, during the second stage, two or more of the second transistor M2, fourth transistor M4and eighth transistor M8is/are enabled at a different timings. In some embodiments, more than two stages are provided in the read assist device. Such embodiments, while possible and within the scope of this disclosure, increase circuitry complexity and power consumption without a comparable gain in memory access speed. In some embodiments, the first and second stages are enabled at the same time, i.e., the first and second current paths (during a logical “0” reading) are established at the same time. Such embodiments, while possible and within the scope of this disclosure, may not necessarily increase the memory access speed in certain circumstances. The delays between the WL signal and the first enabling signal SAE1, and between the first enabling signal SAE1and the second enabling signal SAE2are tunable to best fit a particular memory configuration. In some embodiments, the delay between WL and SAE1is from 4 gate delay to 10 gate delay depend on BL loading, and/or the delay between SAE1and SAE2is 1 transmission gate delay.

FIG. 7is a flow chart of a method700of operating a memory in accordance with some embodiments. At step705, a bit line, e.g., the bit line BL, is pre-charged to a pre-charge voltage Vpc. In some embodiments, this step is omitted.

At step710, in response to a datum (e.g., a logical “0”) being read out from a memory cell connected to the bit line BL, the pre-charge voltage Vpc on the bit line BL is caused to transit toward a ground voltage VSS with an initial transition speed (e.g., S0inFIG. 6B). During a first stage of the transition, a first current path (e.g., the first current path I1) is established between the bit line BL and the ground to increase the transition speed (e.g., S1inFIG. 6B).

At step715, during a second, subsequent stage of the transition, a second current path (e.g., the second current path I2) is established in parallel with the first current path to further increase the speed of the transition (e.g., S2inFIG. 6B).

At step720, the voltage on the bit line BL reaches a sufficient level that permits a sensing amplifier (e.g.,110) to detect and output the datum read out from the memory cell.

The above method embodiment shows exemplary steps, but they are not necessarily required to be performed in the order shown. Steps may be added, replaced, changed order, and/or eliminated as appropriate, in accordance with the spirit and scope of embodiments of the disclosure. Embodiments that combine different features and/or different embodiments are within scope of the disclosure and will be apparent to those skilled in the art after reviewing this disclosure.

According to some embodiments, a memory comprises a first bit line, a memory cell coupled to the first bit line, and a read assist device coupled to the first bit line. The read assist device is configured to pull a first voltage on the first bit line toward a predetermined voltage in response to a first datum being read out from the memory cell. The read assist device comprises a first circuit configured to establish a first current path between the first bit line and a node of the predetermined voltage during a first stage. The read assist device further comprises a second circuit configured to establish a second current path between the first bit line and the node of the predetermined voltage during a second, subsequent stage.

According to some embodiments, a memory comprises a pair of bit lines including a first bit line and a second bit line, a memory cell coupled to the first and second bit lines, and first through sixth transistors. The first and fifth transistors are coupled in series between the first bit line and a node. The first and second transistors are coupled in parallel. The third and sixth transistors are coupled in series between the second bit line and the node. The third and fourth transistors are coupled in parallel. The fifth and sixth transistors are cross-coupled, with a gate of the fifth transistor coupled to the second bit line, and a gate of the sixth transistor coupled to the first bit line.

According to some embodiments, in a method of operating a memory, a bit line is pre-charged to a pre-charge voltage. In response to a datum being read out from a memory cell connected to the bit line, a transition of the pre-charge voltage on the bit line toward a ground voltage is caused. During a first stage of the transition, a first current path is established between the bit line and a ground to increase a speed of the transition. During a second, subsequent stage of the transition, a second current path is established in parallel with the first current path to further increase the speed of the transition.