Providing exclusive use of cache associated with a processing entity of a processor complex to a selected task

A plurality of processing entities are maintained in a processor complex. In response to determining that a task is a critical task, the critical task is dispatched to a scheduler, wherein it is preferable to prioritize execution of critical tasks over non-critical tasks. In response to dispatching the critical task to the scheduler, the scheduler determines which processing entity of the plurality of processing entities has a least amount of processing remaining to be performed for currently scheduled tasks. Tasks queued on the determined processing entity are moved to other processing entities, and the currently scheduled tasks on the determined processing entity are completed. In response to moving tasks queued on the determined processing entity to other processing entities and completing the currently scheduled tasks on the determined processing entity, the critical task is dispatched on the determined processing entity.

BACKGROUND

Embodiments relate to the providing of exclusive use of cache associated with a processing entity of a processor complex to a selected task.

A storage system may control access to storage for one or more host computational devices that may be coupled to the storage system over a network. A storage management application that executes in the storage system may manage a plurality of storage devices, such as disk drives, tape drives, flash drives, direct access storage devices (DASD), etc., that are coupled to the storage system. A host may send Input/Output (I/O) commands to the storage system and the storage system may execute the I/O commands to read data from the storage devices or write data to the storage devices.

The storage system may include two or more servers, where each server may be referred to as a node, a storage server, a processor complex, a Central Processor Complex (CPC), or a Central Electronics Complex (CEC). Each server may be included in a cluster. Each server may have a plurality of processor cores (also referred to as cores) and the servers may share the workload of the storage system. In a two server configuration of the storage system, either server can failover to the other if there is a failure or a planned downtime for one of the two servers. For example, a first server may failover to a second server is there is a failure of the first server.

A computational device, such as a host or a server of storage system, may include a plurality of processors and form a multiprocessing system. A computational device may have a processor complex that may have a single core or a plurality of cores, where a core may correspond to a central processing unit (CPU). For example, a dual-core processor complex has two central processing units, so that the dual-core processor complex may appear to the operating system as two CPUs.

A process (or task) is an instance of a computer program that is being executed. Depending on the operating system, a process may be made up of multiple threads of execution that execute instructions concurrently. Multiple threads may exist within the same process and share resources such as memory. A thread is what the CPU actually runs, whereas a process has the allocated memory for instructions and data. A process may need one or more threads because that is what is actually run by the CPU. Multiple threads corresponding to a process implies that the process gets more time slices on the same CPU or gets to run on more CPUs concurrently. A process needs at least one thread that the CPU executes. In a multi-core processor complex, a different process may use a different core at the same time to speed up the system.

U.S. Pat. No. 8,276,142 describes a method that includes scheduling a thread to run on a core of a multi-core processor. U.S. Pat. No. 8,250,347 describes asymmetric hardware support for a special class of threads. US Patent Publication 2005/0015768 describes a method for scheduling tasks. U.S. Pat. No. 6,212,544 describes a method for performing computer processing operations in a data processing system having a multithreaded processor and thread switch logic. U.S. Pat. No. 6,085,215 describes a method using a combination of processing threads, polling, and a use of interrupts to allocate the use of processing resources fairly among competing functions.

SUMMARY OF THE PREFERRED EMBODIMENTS

Provided are a method, a system, and a computer program product in which a plurality of processing entities are maintained in a processor complex. In response to determining that a task is a critical task, the critical task is dispatched to a scheduler, wherein it is preferable to prioritize execution of critical tasks over non-critical tasks. In response to dispatching the critical task to the scheduler, the scheduler determines which processing entity of the plurality of processing entities has a least amount of processing remaining to be performed for currently scheduled tasks. Tasks queued on the determined processing entity are moved to other processing entities, and the currently scheduled tasks on the determined processing entity are completed. In response to moving tasks queued on the determined processing entity to other processing entities and completing the currently scheduled tasks on the determined processing entity, the critical task is dispatched on the determined processing entity. As a result, critical tasks are executed faster relative to non-critical tasks.

In certain embodiments, in response to determining that the task is a non-critical task, the task is scheduled for execution in any of the plurality of processing entities. As a result, non-critical tasks may have to share the cache of the plurality of processing entities.

In further embodiments, the plurality of processing entities comprise a plurality of cores, and wherein the determined processing entity corresponds to a determined core that has a clean L1 cache and a clean L2 cache at a time at which the critical task is scheduled for execution in the determined core. As a result, critical tasks may have exclusive use of the L1 cache and L2 cache.

In yet further embodiments, the critical task executes faster by using the clean L1 cache and the clean L2 cache of the determined core, in comparison to scheduling the critical task on any other core of the plurality of cores, wherein in the other cores the L1 cache and the L2 cache are shared among a plurality of tasks. As a result, critical tasks may execute faster than non-critical tasks.

In certain embodiments, the plurality of processing entities comprise a plurality of chips having a plurality of cores, wherein the determined processing entity corresponds to a determined chip that has a clean L1 cache, a clean L2 cache, and a clean L3 cache at a time at which the critical task is scheduled for execution in the determined chip. As a result, critical tasks may have exclusive use of the L1, L2, and L3 cache.

In further embodiments, the critical task executes faster by using the clean L1 cache, the clean L2 cache, and the clean L3 cache of the determined chip, in comparison to scheduling the critical task on any other chip of the plurality of chips, wherein in the other chips the L1 cache, the L2 cache, and the L3 cache are shared among a plurality of tasks. As a result, critical tasks may execute faster that non-critical tasks in chips having L1, L2, and L3 cache.

In certain embodiments, in response to completion of the critical task in the determined processing entity, the scheduler is returned to a mode in which the scheduler schedules non-critical tasks for execution on the determined processing entity. As a result, critical tasks are scheduled earlier than certain non-critical tasks.

DETAILED DESCRIPTION

A computational device, such has a server, may comprise a CPU complex (processor complex) that has many chips. A chip may have a plurality of cores that may simultaneously execute a plurality of threads. All the threads running in a core may share the same L1 and L2 cache. Additionally, the threads that run on the cores in a chip share an L3 cache (This may be somewhat different in some CPU architectures where the L3 cache is also shared within the same core instead of the chip). If data is not found in the L1 cache, then the date is retrieved from the L2 cache, and if the data is not found in the L3 cache then the data is retrieved from the L3 cache.

A server in a storage system may have certain tasks that are critical for ensuring a high performance storage system. When such critical tasks are running, they may need cache hits (to the L1, L2, and L3 cache) to be efficient. If there are other tasks running in the same core or same chip, the other tasks may share the L1, L2, and L3 cache and the critical task that needs to be efficient and have good L1, L2, and L3 cache hits may execute relatively slowly.

In certain embodiments, to speed up the execution of such critical tasks the following operations are performed:

(1) A task scheduler selects the core or chip that has least runtime left for the currently scheduled tasks;

(2) The task scheduler schedules the critical task on the selected core or chip and no other task is allowed to run on the selected core or chip while the critical task runs its timeslice; and

(3) Once the critical task completes its timeslice, the task scheduler returns to a normal dispatch mode on the selected core or chip.

In certain embodiments, by scheduling a critical task on a processing entity (e.g., a core and/or a chip) that is least lightly loaded, after allowing scheduled tasks on the processing entity to complete and moving queued tasks on the processing entity to other processing entities, exclusive use of the cache is provided to the critical task to allow the critical task to execute faster in comparison to non-critical tasks. Hit ratios on the cache are improved for the critical task in comparison to hit ratios on the cache for non-critical tasks that share the cache with other non-critical tasks.

Exemplary Embodiments

FIG. 1illustrates a block diagram of a computing environment100comprising a storage system102comprising a first server104and a second server106, where the storage system102communicates with a plurality of hosts108,110over a network, in accordance with certain embodiments.

The storage system102, the servers104,106and the hosts108,110may comprise any suitable computational device including those presently known in the art, such as, a personal computer, a workstation, a server, a mainframe, a hand held computer, a palm top computer, a telephony device, a network appliance, a blade computer, a processing device, a controller, etc. The plurality of servers104,106may provide redundancy because if one server undergoes a failure from which recovery is not possible, an alternate server may perform the functions of the server that failed. Each of the plurality of servers104,106may be referred to as a processor complex, a central electronics complex (CEC), or a central processing unit (CPU) complex and may include one or more processors and/or processor cores. The storage system102may also be referred to as a dual-server storage system.

The storage system102, the servers104,106and the hosts108,110may be elements in any suitable network, such as, a storage area network, a wide area network, the Internet, an intranet. In certain embodiments, storage system102, the servers104,106and the hosts108,110may be elements in a cloud computing environment.

It should be noted that the storage system102may be configured and accessed in many different ways. For example, virtualization may be performed to access the hardware elements of the storage system102. Additionally, in certain embodiments, the storage system102may have a single server or more than two servers.

In certain embodiments, each of the servers104,106may have corresponding applications and data structures implemented in each, and the applications and data structures implemented in the first server104are shown. The server106may have similar applications and data structures, and may have similar hardware, firmware, and/or software.

The first server104includes a plurality of processing entities126,128, where in certain embodiments each processing entity is a central processing unit (CPU) such as a core. In certain embodiments, each processing entity126,128is the lowest granularity of a processor that is configurable to execute a task.

Each server104may also include a dispatcher130and a task scheduler132. The dispatcher130dispatches one or more tasks134,136to the task scheduler132where the task scheduler132schedules one or more threads of a task for execution on a processing entity126,128. Each task134,136may be a critical or a non-critical task as shown via reference numerals138,140. A critical task is a task that is desirable to execute ahead of a non-critical task in a fast manner. For example, in the server104when a device adapter indicates completion of stage and destage requests with respect to a cache, the completions may be critical tasks that may need to be processed in a fast manner over other tasks. The critical tasks may be referred to as dedicated tasks and are dispatched by the task scheduler132for preferential execution on cores while at the same time exclusive access to the cache is provided on the cores to the dedicated tasks.

FIG. 2illustrates a block diagram of the server104that comprises a processor complex or a central electronics complex (CEC), in accordance with certain embodiments. The server104may be comprised of a plurality of chips202,204where each chip is comprised of a plurality of cores206,208as shown inFIG. 2. Each core may have a L1 cache and a L2 cache (shown via reference numerals210,212,214,216) that is shared by threads that execute in the core, and each chip202may have an L3 cache218that is shared among threads that execute in one or more cores206,208of the chip202.

In certain embodiments, each core206,208corresponds to a processing entity126,128shown inFIG. 1. In other embodiments, each chip202,204corresponds to a processing entity126,128shown inFIG. 1. Other arrangements of L1 cache, L2 cache, and L3 cache may be found in the server104.

FIG. 3illustrates a block diagram300that shows normal processing mode of tasks in a core301, in accordance with certain embodiments. Threads corresponding to a plurality of tasks302,304may be assigned for execution in the core301. Some of these threads may be currently scheduled threads306and some of these threads may be queued threads308.

FIG. 4illustrates a block diagram400that shows a dedicated processing mode for a task in a core, in accordance with certain embodiments.

In certain embodiments, before threads corresponding to a critical task (referred to as a dedicated task) are executed on a core401, the currently scheduled threads402on the core401are allowed to complete, whereas the queued threads404on the core401are moved (shown via reference numeral406) to another core. Subsequently, the threads corresponding to the dedicated task (i.e., the critical task)408execute in the core401and have exclusive access to the L1, L2 cache of the core401.

FIG. 5illustrates a first flowchart500that shows mechanisms to provide exclusive use of cache associated with a core or a chip to a selected task in a multi-core processor complex, in accordance with certain embodiments. The operations shown inFIG. 5may be performed by the task scheduler132that executes in the server104.

Control starts at block502in which the task scheduler132determines which core (or chip) has the least runtime remaining for the currently scheduled tasks. The task scheduler132schedules (at block504) a dedicated task (i.e., a critical task) on the determined core (or chip) and no other task can run on that core (or chip) while the dedicated task runs its timeslice (i.e., while the threads corresponding to the dedicated task run).

From block504control proceeds to block506in which once the critical task completes its timeslice, the task scheduler132returns to normal processing mode on the determined core (or chip).

FIG. 6illustrates a second flowchart600that shows mechanisms to provide exclusive use of cache associated with a core or a chip to a selected task in a multi-core processor complex, in accordance with certain embodiments. The operations shown inFIG. 6may be performed in the server104,106or the storage system102.

Control starts at block602in which a critical task is marked as a dedicated task and is dispatched by the dispatcher130to the task scheduler132in the operating system that executes in the server104. The task scheduler132initiates (at block604) a processing of the dedicated task.

Control proceeds to block606in which the task scheduler checks all the cores (or chips) to determine which core (or chip) has the least amount of work for the currently scheduled tasks and moves (at block608) the queued work from the core (or chip) to queues in other cores (or chips).

Control proceeds to block610in which a determination is made as to whether all currently scheduled tasks on the core (or chip) have completed their work. If not, then the task scheduler132waits (at block612) for currently scheduled tasks to complete their work in the core (or chip).

If at block610a determination is made that all currently scheduled tasks on the core (or chip) have completed their work, then control proceeds to block614in which the task scheduler132schedules the dedicated task on a thread in the core (or chip). It may be noted that no other threads are running on the core (or chip) at this time and as a result the dedicated task gets exclusive access (at block616) to the appropriate cache (e.g., L1, L2 cache of the core, or L1, L2, L3 cache in case of the chip).

From block616control proceeds to block618in which in response to completion of execution of threads of the dedicated task, the task scheduler132returns to a normal mode of processing by starting to dispatch non-critical tasks on the core (or chip)

FIG. 7illustrates a third flowchart700that shows mechanisms to provide exclusive use of cache associated with a core or a chip to a selected task in a multi-core processor complex, in accordance with certain embodiments. The operations shown inFIG. 7may be performed in the server104,106or the storage system102.

Control starts at block702in which a plurality of processing entities126,128(e.g., cores and/or chips) are maintained in a processor complex104. In response to determining that a task is a critical task, the critical task is dispatched (at block704) to a scheduler132, wherein it is preferable to prioritize execution of critical tasks over non-critical tasks.

Control proceeds to block706, in which in response to dispatching the critical task to the scheduler132, the scheduler132determines which processing entity of the plurality of processing entities126,128has a least amount of processing remaining to be performed for currently scheduled tasks. Tasks queued on the determined processing entity are moved (at block708) to other processing entities, and the currently scheduled tasks on the determined processing entity are completed.

Control proceeds to block710, in which in response to moving tasks queued on the determined processing entity to other processing entities and completing the currently scheduled tasks on the determined processing entity, the critical task is dispatched on the determined processing entity. Subsequently, at block712in response to completion of the critical task in the determined processing entity, the scheduler132is returned to a mode in which the scheduler132schedules non-critical tasks for execution on the determined processing entity.

In certain embodiments, in response to determining that the task is a non-critical task, the task is scheduled for execution in any of the plurality of processing entities126,128.

In certain embodiments, the plurality of processing entities126,128comprise a plurality of cores206,208, and the determined processing entity corresponds to a determined core206that has a clean L1 cache210and a clean L2 cache212at a time at which the critical task is scheduled for execution in the determined core206. The critical task executes faster by using the clean L1 cache210and the clean L2 cache212of the determined core206, in comparison to scheduling the critical task on any other core208of the plurality of cores, wherein in the other cores208the L1 cache214and the L2 cache216are shared among a plurality of tasks.

In certain embodiments, the plurality of processing entities126,128comprise a plurality of chips202,204having a plurality of cores, wherein the determined processing entity corresponds to a determined chip202that has a clean L1 cache210,214, a clean L2 cache214,216, and a clean L3 cache218at a time at which the critical task is scheduled for execution in the determined chip. The critical task executes faster by using the clean L1 cache210,212, the clean L2 cache214,216, and the clean L3 cache218of the determined chip202, in comparison to scheduling the critical task on any other chip204of the plurality of chips202,204, wherein in the other chips the L1 cache, the L2 cache, and the L3 cache are shared among a plurality of tasks.

Therefore,FIGS. 1-7illustrate certain embodiments in which by scheduling a critical task on a processing entity that is least lightly loaded, after allowing scheduled tasks on the processing entity to complete and moving queued tasks on the processing entity to other processing entities, exclusive use of the cache is provided to the critical task to allow the critical task to execute faster in comparison to non-critical tasks.

Cloud Computing Environment

Cloud computing is a model for enabling convenient, on-demand network access to a shared pool of configurable computing resources (e.g., networks, servers, storage, applications, and services) that can be rapidly provisioned and released with minimal management effort or service provider interaction.

Workloads layer66provides examples of functionality for which the cloud computing environment may be utilized. Examples of workloads and functions which may be provided from this layer include: mapping and navigation; software development and lifecycle management; virtual classroom education delivery; data analytics processing; transaction processing; and the dedicated task scheduling68as shown inFIGS. 1-7.

Additional Embodiment Details

The described operations may be implemented as a method, apparatus or computer program product using standard programming and/or engineering techniques to produce software, firmware, hardware, or any combination thereof. Accordingly, aspects of the embodiments may take the form of an entirely hardware embodiment, an entirely software embodiment (including firmware, resident software, micro-code, etc.) or an embodiment combining software and hardware aspects that may all generally be referred to herein as a “circuit,” “module” or “system.” Furthermore, aspects of the embodiments may take the form of a computer program product. The computer program product may include a computer readable storage medium (or media) having computer readable program instructions thereon for causing a processor to carry out aspects of the present embodiments.

FIG. 10illustrates a block diagram that shows certain elements that may be included in the storage system102, the first server104, the second server106, the hosts108,110or other computational devices in accordance with certain embodiments. The system1000may include a circuitry1002that may in certain embodiments include at least a processor1004. The system1000may also include a memory1006(e.g., a volatile memory device), and storage1008. The storage1008may include a non-volatile memory device (e.g., EEPROM, ROM, PROM, flash, firmware, programmable logic, etc.), magnetic disk drive, optical disk drive, tape drive, etc. The storage1008may comprise an internal storage device, an attached storage device and/or a network accessible storage device. The system1000may include a program logic1010including code1012that may be loaded into the memory1006and executed by the processor1004or circuitry1002. In certain embodiments, the program logic1010including code1012may be stored in the storage1008. In certain other embodiments, the program logic1010may be implemented in the circuitry1002. One or more of the components in the system1000may communicate via a bus or via other coupling or connection1014. Therefore, whileFIG. 10shows the program logic1010separately from the other elements, the program logic1010may be implemented in the memory1006and/or the circuitry1002.