Method of forming barrier free contact for metal interconnects

A method includes forming a first insulating layer having one or more vias formed in at least a portion of the first insulating layer. The vias are filled with a first metallic material. A cap layer is deposited on a top surface of the first insulating layer and a top surface of the one or more vias and a second insulating layer is deposited on a top surface of the cap layer. One or more openings are formed in the second insulating layer and the cap layer. A self-assembled monolayer is formed on an exposed top surface of the first metallic material in the one or more vias. A barrier layer is formed on at least the exposed surface of the one or more openings. The self-assembled monolayer is removed and the one or more openings are filled with a second metallic material.

BACKGROUND

This disclosure relates generally to integrated circuits (IC), and more particularly to semiconductor ICs, and methods for their construction.

With the current trends in IC miniaturization, and increasingly smaller critical dimensions, it is desirable in semiconductor device technology to integrate many different functions on a single chip. In the IC chip fabrication industry, there are three sections referred to in a typical IC chip build: front end of the line (FEOL), back end of the line (BEOL) and the section that connects those two together, the middle of the line (MOL). The FEOL is made up of the semiconductor devices, e.g., transistors, the BEOL is made up of interconnects and wiring, and the MOL is an interconnect between the FEOL and BEOL that includes material to prevent the diffusion of BEOL metals to FEOL devices.

The FEOL transistor devices are typically processed using single crystal and poly-crystalline silicon. The BEOL interconnects are typically made of multiple metals; the bulk of the conductor is copper. If copper diffuses into the FEOL silicon-based devices, it can cause shorting or alter sensitive transistor characteristics and render the semiconductor useless. This is the reason for the MOL connection. BEOL generally begins when the first layer of metal is deposited on the wafer. BEOL includes contacts, insulating layers (dielectrics), metal levels, and bonding sites for chip-to-package connections.

SUMMARY

According to an exemplary embodiment of the present invention, a method for fabricating a semiconductor device includes forming a first insulating layer having one or more vias formed in at least a portion of the first insulating layer, wherein the one or more vias are filled with a first metallic material. The method further comprises forming a cap layer on a top surface of the first insulating layer and a top surface of the one or more vias formed in at least a portion of the first insulating layer. The method further comprises forming a second insulating layer on a top surface of the cap layer. The method further comprises forming one or more openings in the second insulating layer and the cap layer and exposing at least a portion of a top surface of the first metallic material in the one or more vias. The method further comprises forming a self-assembled monolayer of a material on the exposed top surface of the first metallic material in the one or more vias. The method further comprises forming a barrier layer on at least an exposed surface of the one or more openings. The method further comprises removing the self-assembled monolayer to expose the top surface of the first metallic material in the one or more vias.

According to an exemplary embodiment of the present invention, a semiconductor structure includes a first insulating layer having one or more vias in at least a portion of the first insulating layer, wherein the one or more vias contain a first metallic material. The semiconductor structure further comprises a cap layer disposed on a top surface of the first insulating layer and a top surface of the one or more vias. The semiconductor structure further comprises a second insulating layer disposed on a top surface of the cap layer. The semiconductor structure further comprises one or more openings in the second insulating layer and the cap layer. The semiconductor structure further comprises a self-assembled monolayer of a material disposed on an exposed top surface of the first metallic material in the one or more vias. The semiconductor structure further comprises a barrier layer disposed on at least an exposed surface of the one or more openings.

These and other exemplary embodiments of the invention will be described in or become apparent from the following detailed description of exemplary embodiments, which is to be read in connection with the accompanying drawings.

DETAILED DESCRIPTION

Exemplary embodiments of the invention will now be discussed in further detail with regard to integrated circuits and a method of manufacturing the IC, and more particularly to a barrier free contact for BEOL metal interconnects and MOL metal interconnects using selective deposition of a barrier liner. High contact resistance between multi-level contacts in BEOL metal interconnects is a major hurdle for scaling due to highly resistive barrier liners (e.g., titanium nitride (TiN), tantalum nitride (TaN), etc.). For MOL metal interconnects, the use of cobalt allows reduction of TiN barrier thicknesses. However, it is still not sufficient to meet future contact resistance requirements due to the use of a highly resistive barrier liner. Thus, embodiments described herein provide a barrier free contact formed in metal interconnects.

It is to be understood that the various layers, structures, and/or regions shown in the accompanying drawings are schematic illustrations that are not necessarily drawn to scale. In addition, for ease of explanation, one or more layers, structures, and regions of a type commonly used to form semiconductor devices or structures may not be explicitly shown in a given drawing. This does not imply that any layers, structures, and regions not explicitly shown are omitted from the actual semiconductor structures.

Furthermore, it is to be understood that the embodiments discussed herein are not limited to the particular materials, features, and processing steps shown and described herein. In particular, with respect to semiconductor processing steps, it is to be emphasized that the descriptions provided herein are not intended to encompass all of the processing steps that may be used to form a functional semiconductor integrated circuit device. Rather, certain processing steps that are commonly used in forming semiconductor devices, such as, for example, wet cleaning and annealing steps, are purposefully not described herein for economy of description.

Moreover, the same or similar reference numbers are used throughout the drawings to denote the same or similar features, elements, layers, regions, or structures, and thus, a detailed explanation of the same or similar features, elements, layers, regions, or structures will not be repeated for each of the drawings. Also, in the figures, the illustrated scale of one layer, structure, and/or region relative to another layer, structure, and/or region is not necessarily intended to represent actual scale.

It is to be understood that the terms “about” or “substantially” as used herein with regard to thicknesses, widths, percentages, ranges, etc., are meant to denote being close or approximate to, but not exactly. For example, the term “about” or “substantially” as used herein implies that a small margin of error may be present, such as 1% or less than the stated amount.

The semiconductor devices and methods for forming same in accordance with embodiments of the present invention can be employed in applications such as, for example, hardware, and/or electronic systems. Suitable hardware and systems for implementing embodiments of the invention may include, but are not limited to, personal computers, communication networks, electronic commerce systems, portable communications devices (e.g., cell and smart phones), solid-state media storage devices, functional circuitry, etc. Systems and hardware incorporating the semiconductor devices are contemplated embodiments of the invention. Given the teachings of embodiments of the invention provided herein, one of ordinary skill in the art will be able to contemplate other implementations and applications of embodiments of the invention.

Illustrative embodiments for forming a barrier free contact for metal interconnects in a semiconductor device will be described below with reference toFIGS. 1-15.

For example, according to a first embodiment,FIG. 1illustrates a schematic cross-sectional side view of a semiconductor structure100for use in forming a barrier free contact for BEOL metal interconnects in a semiconductor device. For the purpose of clarity, several fabrication steps leading up to the production of semiconductor structure100as illustrated inFIG. 1are omitted. In other words, semiconductor structure100does not necessarily start out in the form illustrated inFIG. 1, but may develop into the illustrated structure over one or more well-known processing steps which are not illustrated but are well-known to those of ordinary skill in the art.

As shown inFIG. 1, the semiconductor structure100comprises a first insulating layer101. First insulating layer101includes any suitable low-k dielectric material such as, for example, silicon oxide, hydrogenated silicon carbon oxide (SiCOH), SiCH, SiCNH, or other types of silicon based low-k dielectrics (e.g., k less than about 4.0), porous dielectrics, or known ultra-low-k (ULK) dielectric materials (e.g., k less than about 2.5). Insulating layer101further includes via contacts103formed in at least a portion of first insulating layer101. Via contacts103have a diffusion barrier/liner layer102formed on the sidewalls and on an exposed surface of insulating layer101and is filled with a metallic material104.

In one embodiment, the via contacts103are formed by etching a via in at least a portion of first insulating layer101, lining the via with a diffusion barrier/liner layer102and filling the via with a first metallic material104. The diffusion barrier/liner layer102can be formed from, for example, TiN, TaN, and ruthenium (Ru). Suitable metallic material104includes, for example, aluminum (Al), tungsten (W), copper (Cu) or cobalt (Co). The diffusion barrier/liner material102and metallic material104can be conformally deposited using known methods such as atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), electroplating, or electroless plating. A chemical mechanical planarization (CMP) process is performed to remove the overburden of the diffusion barrier/liner material and metallic material used to fill the via hole, and to planarize the structure surface prior to deposition of the dielectric cap layer.

A cap layer106overlies the top surface of first insulating layer101and vias103. The cap layer106can be any suitable dielectric layer. In one embodiment, cap layer106is a dielectric layer such as an NBLoK (nitrogen-doped silicon carbide) layer. A second insulating layer108overlies the top surface of dielectric cap layer106. Second insulating layer108can be of any suitable low-k dielectric material as described above for first insulating layer101. In one embodiment, dielectric cap layer106can have a thickness ranging from about 20 to about 100 nanometers (nm). In one embodiment, second insulating layer108can have a thickness ranging from about 40 to about 1000 nm.

A first sacrificial dielectric layer110(e.g., a sacrificial nitride spacer) overlies the top surface of the second insulating layer108. A first metallic hardmask layer112overlies a portion of first sacrificial dielectric layer110, and a first oxide layer114overlies a portion of metallic hardmask layer112. Suitable materials for the first metallic hardmask layer112include, for example, TiN, TiOx, TaN, AlOx, HfOx etc. The first sacrificial dielectric layer110, first metallic hardmask layer112and first oxide layer114may be formed using known deposition techniques, such as, for example, CVD, PVD, PECVD, ALD, or spin on deposition, followed by a standard planarization process (e.g., CMP) to planarize the upper surfaces prior to forming trench116.

Trench116is formed by a conventional trench mask etching process by etching through first oxide layer114and first metallic hardmask layer112and a portion of first sacrificial dielectric layer110. A first organic planarization layer (OPL)118is then deposited in trench116using, e.g., a spin-on coating process. First OPL118fills the trench and is formed over the top surface of first oxide layer114. The first OPL118can be a self-planarizing organic material that includes carbon, hydrogen, oxygen, and optionally nitrogen, fluorine, and silicon. In one embodiment, the self-planarizing organic material can be a polymer with sufficiently low viscosity so that the top surface of the applied polymer forms a planar horizontal surface. In one embodiment, the first OPL118can include a transparent organic polymer. The OPL can be a standard CxHy polymer. Non-limiting examples of OPL materials include, but are not limited to, CHM701B, commercially available from Cheil Chemical Co., Ltd., HM8006 and HM8014, commercially available from JSR Corporation, and ODL-102 or ODL-401, commercially available from ShinEtsu Chemical, Co., Ltd.

Second sacrificial dielectric layer120(e.g., a sacrificial nitride or oxide spacer) is then deposited over the top surface of first OPL118. Second metallic hardmask layer122overlies second sacrificial dielectric layer120, and a second oxide layer124overlies second metallic hardmask layer122. Suitable materials for second metallic hardmask layer122can include any of those discussed above for first metallic hardmask layer112. The second sacrificial dielectric layer120, second metallic hardmask layer122and second oxide layer124may be formed using known deposition techniques, such as, for example, ALD, CVD, PECVD, PVD or spin on deposition, followed by a standard planarization process (e.g., CMP) to planarize the upper surfaces.

A second OPL126is formed over, and in contact with, first oxide layer124. The OPL126can be a self-planarizing organic material as discussed above. An anti-reflective coating layer128is formed over, and in contact with OPL126. The layer128may, for example, comprise silicon containing materials such as a SiARC coating as known to those skilled in the art. The OPL126and SiARC layer128can be applied by known techniques, for example, by spin-coating. In one embodiment, SiARC layer128can have a thickness ranging from about 10 to about 100 nm. In one embodiment, OPL layer126can have a thickness ranging from about 30 to about 300 nm.

Next, photoresist130is formed onto the SiARC layer128and is lithographically patterned to form a plurality of via openings132therein.

FIG. 2illustrates the semiconductor structure100at an intermediate stage of fabrication after a further etching to extend the plurality of via openings132using the photoresist130as a guide. The etch may, for example, comprise a reactive ion etch (ME) as known to those skilled in the art. As shown inFIG. 2, the plurality of via openings132are extended through semiconductor structure100and expose the top surface of dielectric cap layer106in second insulating layer108. The photoresist130is completely removed during the etching process. In addition, the remaining second sacrificial dielectric layer120, second metallic hardmask layer122, second oxide layer124, OPL126and SiARC layer128are removed by known ME or wet etching techniques as shown inFIG. 2.

FIG. 3illustrates the semiconductor structure100at an intermediate stage of fabrication wherein a trench and vias are formed, according to an embodiment of the invention. In particular,FIG. 3schematically illustrates an intermediate step using any suitable etching technique that is commonly implemented for a “dual damascene” process, wherein both a via hole and a corresponding trench are formed in second insulating layer108, i.e., an ILD layer, prior to filling both the via hole and trench with a single metallic material. The opening135comprises via holes135-1and a corresponding trench135-2. In one embodiment of the invention, the opening135is formed by removing first OPL118by a standard O2or N2/H2based OPL ash and then carrying out a conventional trench etching to remove a portion of second insulating layer108. First oxide layer114is removed during the trench etch exposing the top surface of first metallic hardmask layer112to form opening135comprising a via hole135-1and a corresponding trench135-2.

FIG. 4illustrates the semiconductor structure100at an intermediate stage of fabrication wherein dielectric cap layer106is removed from via hole135-1by, for example, RIE, to expose the top surface of the first metallic material104in via contact103and selectively removing first metallic hardmask layer112using, for example, a wet etch process.

FIG. 5illustrates the semiconductor structure100at an intermediate stage of fabrication wherein self-assembled monolayer (SAM)140is deposited on the top surface of the metallic material104in via contact103selective to other exposed surfaces of layers106,108and110. This selective deposition is enabled by suitable selection of SAM140which only attaches to metallic surface. The suitable material SAM140also advantageously prevents deposition of the barrier layer on the metallic material104. In general, the SAM140will comprise a first functional group to anchor or bind the monolayer to the metallic material104, and a second functional group for organometallic deactivation. In one embodiment, a SAM140comprises a thiol compound as a first functional group and having the formula: RSH wherein R is a linear or branched, substituted or unsubstituted, alkyl, alkenyl, cycloalkyl or aromatic containing from about 6 to about 25 carbon atoms. When substituted, the substituent may be an alkyl having from 1 to about 3 carbon atoms, a halogen such as Cl, Br, F or I, hydroxyl, ammonium and other like substituents. Suitable thiol compounds include, for example, 1-hexadecanthiol and 1-octadecane thiol. In one embodiment, a thiol includes those wherein R is an alkyl having from 16 to about 20 carbon atoms.

In another embodiment, a SAM140can include a phosphonic acid, a phosphonate group, an amine, phosphine, and isocyanide as a first functional group. For example, a SAM140may be one or more of diethyl (3-aminopropyl)phosphonate, diethyl(3-(pentacosa-10,12-diynamido)propyl)phosphonate, and (3-(pentacosa-10,12-diynamido)propyl) phosphonic acid. Examples of such SAMs can be seen in, for example, Wojtecki et al., “Reactive Monolayers in Directed Additive Manufacturing—Area Selective Atomic Layer Deposition,” J. Photopolymer Science & Technology, (2018).

The SAM140can be deposited in via hole135-1on the top surface of the metallic material104in via contact103by techniques known in the art, e.g., spin coating. In one embodiment, the SAM140is formed by immersing the structure in a thiol-containing solution. The treatment process is carried out at room temperature for a time period of from about 0.1 to about 24 hours. If desired, elevated temperatures up to about 70° C. can also be used as long as the elevated temperature does not adversely effect the various layers of the structure. The SAM solution may be a concentrated solution or can be a diluted solution in which the SAM material such as a thiol compound is dissolved in a solvent such as ethanol or heptane. In one embodiment, a diluted solution containing from about 0.001 to about 0.01% SAM material is employed in forming the self-assembled monolayer. In one illustrative embodiment, the SAM140may have a thickness ranging from about 1 to about 20 nm.

FIG. 6illustrates the semiconductor structure100at an intermediate stage of fabrication wherein barrier layer150is deposited on the exposed surfaces of opening135. In one embodiment, barrier layer150is deposited on the exposed surfaces of opening135and not on a top surface of SAM140. The barrier layer150can comprise a metal-containing material such as, for example, TaN, TiN or Ru. In one illustrative embodiment, the barrier layer150may have a thickness ranging from about 1 to about 5 nm. The presence of SAM140prevents barrier layer150deposition on the metal surface104in via contact103. The barrier layer150can be formed by a deposition process including, for example, CVD, PECVD, ALD, PVD, sputtering, chemical solution deposition and plating.

FIG. 7illustrates the semiconductor structure100at an intermediate stage of fabrication wherein SAM140is removed from via hole135-1to expose the top surface of the metallic material104in via contact103. SAM140can be removed by conventional dry etching processes. For example, in one illustrative embodiment, SAM140is removed by a standard plasma etch using N2/H2chemistry.

FIG. 8illustrates the semiconductor structure100at an intermediate stage of fabrication wherein second metallic material160is deposited in opening135to fill via hole135-1and trench135-2. The second metallic material160can be any of the first metallic materials104discussed above for filling via contact103. In addition, second metallic material160can be deposited by any known method such as ALD, CVD, and PVD. A CMP process is performed to remove the overburden of the metallic material used to fill the opening, and to planarize the structure. Accordingly, a barrier free contact is thus formed between second metallic material160and first metallic material104in the resulting semiconductor structure100.

According to another embodiment,FIG. 9illustrates a schematic cross-sectional side view of a semiconductor structure200for use in forming a barrier free contact for MOL metal interconnects in a semiconductor structure. For the purpose of clarity, several fabrication steps leading up to the production of semiconductor structure200as illustrated inFIG. 9are omitted. In other words, semiconductor structure200does not necessarily start out in the form illustrated inFIG. 9, but may develop into the illustrated structure over one or more well-known processing steps which are not illustrated but are well-known to those of ordinary skill in the art.

As shown inFIG. 9, the semiconductor structure200comprises an insulating layer201. Insulating layer201can be formed on, for example, a semiconductor substrate (not shown) comprising a semiconductor material including, but not limited to, silicon (Si), silicon germanium (SiGe) at various Si and Ge concentrations, silicon carbide (SiC), Si:C (carbon doped silicon), silicon germanium carbide (SiGeC), carbon doped silicon germanium (SiGe:C), compound semiconductor materials (e.g. Groups III-V), or other like semiconductor material. In addition, multiple layers of the semiconductor materials can be used as the semiconductor material of the substrate. The semiconductor substrate can be a bulk substrate or a semiconductor-on-insulator substrate such as, but not limited to, a silicon-on-insulator (SOI), silicon-germanium-on-insulator (SGOI) or Groups III-V-on-insulator substrate including a buried insulating layer, such as, for example, a buried oxide, nitride layer or aluminum oxide.

Insulating layer201includes any suitable low-k dielectric material as discussed above for first insulating layer101. Insulating layer201further includes via contacts203formed in at least a portion of insulating layer201. Via contacts203have a diffusion barrier/liner layer202formed on the sidewalls and bottom surface of insulating layer201and is filled with a first metallic material204.

In one embodiment, the via contacts203are formed by etching a via hole in at least a portion of first insulating layer201, lining the via hole with a diffusion barrier/liner layer202(e.g., TiN, TaN, Ru, etc.), and filling the via hole with a first metallic material204such as Co, Al, W or Cu. The diffusion barrier/liner material and metallic material can be conformally deposited using known methods such as ALD, CVD, PVD, electroplating, or electroless plating. A CMP process is performed to remove the overburden of the diffusion barrier/liner material and metallic material used to fill the via hole, and to planarize the structure surface prior to deposition of the dielectric cap layer.

A first dielectric cap layer206(e.g., a sacrificial nitride spacer) overlies the top surface of first insulating layer201and via contacts203. The first dielectric cap layer206may be formed using known deposition techniques, such as, for example, CVD, PVD, PECVD, ALD, or spin on deposition, followed by a standard planarization process (e.g., CMP) to planarize the upper surface. In one embodiment, first dielectric cap layer206can have a thickness ranging from about 40 to about 200 nm.

An oxide layer208overlies sacrificial spacer layer206. The oxide layer208may be formed using known deposition techniques, such as, for example, ALD, CVD, PECVD, PVD or spin on deposition, followed by a standard planarization process (e.g., CMP) to planarize the upper surface. In one embodiment, oxide layer208can have a thickness ranging from about 40 to about 200 nm.

An OPL210is formed over, and in contact with, oxide layer208. The OPL210can be a self-planarizing organic material as discussed above. An anti-reflective coating layer212is formed over, and in contact with OPL210. The layer212may, for example, comprise silicon containing materials such as a SiARC coating as known to those skilled in the art. The OPL210and SiARC layer212can be applied by known techniques, for example, by spin-coating. In one embodiment, OPL layer210can have a thickness ranging from about 30 to about 300 nm. In one embodiment, SiARC layer212can have a thickness ranging from about 10 to about 100 nm.

Next, photoresist214is formed onto the SiARC layer212and is lithographically patterned to form a plurality of via openings216therein.

FIG. 10illustrates the semiconductor structure200at an intermediate stage of fabrication after a further etching to extend the plurality of via openings216using the photoresist214as a guide. The etch may, for example, comprise a RIE as known to those skilled in the art. As shown inFIG. 10, the plurality of via openings216are extended through semiconductor structure200and exposing the top surface of oxide layer208in OPL210. The photoresist214is removed during the etching process, as shown inFIG. 10.

FIG. 11illustrates the semiconductor structure200at an intermediate stage of fabrication after a further etching to extend the plurality of via openings216through oxide layer208and dielectric cap layer206. The etch may, for example, comprise a fluorocarbon (e.g., a C4F6etch, C4F8etch, CH2F2etch, CHF3etch, CF4etch, etc.) based RIE as known to those skilled in the art. During this etch, the SiARC layer212is also removed, since fluorocarbon chemistry etches SiARC. The remaining OPL layer210is then removed by a standard RIE using O2chemistry. As shown inFIG. 11, the plurality of via openings216are extended through oxide layer208and expose at least a portion of the top surfaces of metallic material204in via contact203and first insulating layer201. The OPL210is then removed by known techniques, as shown inFIG. 11.

FIG. 12illustrates the semiconductor structure200at an intermediate stage of fabrication wherein SAM218is deposited on the top surface of the exposed top surface of first metallic material204in via contacts203selective to other exposed dielectric surfaces of layers201,206and208. This selective deposition is achieved by suitable selection of SAM218which only attaches to the metallic surface. The suitable material for SAM218also prevents deposition of the barrier layer on the first metallic material204in via contacts203. In general, the SAM218can comprise any material as discussed above for SAM140. The SAM218can be deposited in via openings216and on the exposed top surface of first metallic material204in via contacts203by techniques known in the art, e.g., spin coating. In one embodiment, the SAM218is formed by immersing the structure in a thiol-containing solution. The treatment process can be carried out as discussed above for SAM140. In one illustrative embodiment, the SAM218may have a thickness ranging from about 1 to about 20 nm.

Next, barrier layer220is deposited on the exposed surfaces of opening216, oxide layer208and insulating layer201. The barrier layer220can comprise a metal-containing material as discussed above for barrier layer150. In one embodiment, barrier layer220is TiN. The barrier layer220can be formed by a deposition process including, for example, CVD, PECVD, ALD, PVD, sputtering, chemical solution deposition and plating. The thickness of barrier layer220can range from about 1 to about 5 nm. In addition, the presence of SAM218prevents barrier layer deposition on the surface of first metallic material204in via contact203.

FIG. 13illustrates the semiconductor structure200at an intermediate stage of fabrication wherein SAM218is removed from opening216to expose the top surface of the metallic material204in via contact203and a portion of sidewalls of dielectric cap layer206under the barrier layer220. SAM218can be removed by conventional dry or wet etching processes. For example, in one illustrative embodiment, SAM218is removed by a plasma etch using standard N2/H2chemistry.

FIG. 14illustrates the semiconductor structure200at a stage of fabrication wherein second metallic material222is deposited in and fills opening216. The second metallic material222can be any of the first metallic materials204discussed above for filling via contact203. In addition, second metallic material222can be deposited by any known method such as ALD, CVD, and PVD. A CMP process is performed to remove the overburden of the metallic material222used to fill the opening216, and to planarize the structure as shown inFIG. 15. Accordingly, a barrier free contact is thus formed between second metallic material222and first metallic material204in the resulting semiconductor structure200.

Although illustrative embodiments have been described herein with reference to the accompanying drawings, it is to be understood that the invention is not limited to those precise embodiments, and that various other changes and modifications may be made by one skilled in art without departing from the scope or spirit of the invention.