Capacitor charging circuit with a soft-start function

When a primary winding current increases to an upper limit determined by a reference voltage having a soft-start characteristic, a power switch is turned OFF. When a secondary winding current decreases to a lower limit determined by another predetermined reference voltage, the power switch is turned ON. A minimum ON-time limiting unit prevents the power switch from being turned OFF before a minimum ON-time expires. The minimum ON-time may be provided with a soft-start modulation. A minimum OFF-time limiting unit prevents the power switch from being turned ON before a minimum OFF-time expires. A maximum ON-time limiting unit prevents the power switch from still remaining ON after a maximum ON-time expires.

BACKGROUND OF INVENTION

1. Field of the Invention

The present invention relates to a charging circuit and, more particularly, to a capacitor charging circuit with a soft-start function, applicable to effectively charge photoflash capacitors of digital still cameras or other capacitive loads over a wide voltage range.

2. Description of the Related Art

In photoflash systems of digital still cameras, a battery voltage source of approximately 3 volts is supplied to charge a photoflash capacitor through a transformer for raising the capacitor voltage from zero to several hundreds volts required for the excitation of a photoflash lamp. U.S. Pat. No. 6,411,064, U.S. Pat. No. 6,417,649, U.S. Pat. No. 6,518,733, and U.S. Pat. No. 6,636,021, all incorporated herein by reference, have already disclosed a variety of capacitor charging methods and circuits for charging capacitive loads such as photoflash capacitors over a wide voltage range. However, several problems are encountered in the prior art charging circuits and still need to be cured with further improvements and innovations.

At first, during an initial period of a charging process, a large amount of inrush current flows into a primary winding of the transformer, resulting in a significantly large amount of energy to be stored in the transformer. However, it takes an extremely long time for delivering the stored energy to the capacitive load through a secondary winding of the transformer since the terminal voltage across the capacitive load is almost zero at that time. As a result, the charging process is adversely affected by a very low efficiency during the initial period.

Each time when the power switch coupled to the primary winding performs ON/OFF switching operations, both of the primary winding current and the secondary winding current inevitably fluctuate up and down with a great proportion to their DC mean values. Because the primary and secondary winding currents are detected in order to determine the ON/OFF timing of the power switch, such fluctuant noise that casts an incredulous shadow over the current detecting results may destroy the control mechanism of the charging circuit.

After continuously supplying energy in the photoflash system for a long time, the battery voltage source may be subjected to a significant drop. The lower the battery voltage, the longer the primary winding current increases to a predetermined upper limit which controls the ON-to-OFF switching operation of the power switch. Consequently, each charging cycle is prolonged, resulting in large output ripples and low charging efficiency.

SUMMARY OF INVENTION

In view of the above-mentioned problems, an object of the present invention is to provide a capacitor charging circuit capable of reducing the inrush current and enhancing the charging efficiency during the initial period of the charging process.

Another object of the present invention is to provide a capacitor charging circuit capable of preventing the ON/OFF switching operations from being erroneously triggered by the fluctuant noise.

Still another object of the present invention is to provide a capacitor charging circuit capable of preventing the charging process from being deteriorated by the drop of the battery voltage.

According to one aspect of the present invention, a capacitor charging circuit is provided for controlling a transformer such that a voltage source coupled to a primary winding of the transformer charges a capacitive load coupled to a secondary winding of the transformer.

The capacitor charging circuit includes a power switch, a switch controller, and a soft-start circuit. The power switch is coupled to the primary winding of the transformer such that a primary winding current is allowed to flow during an ON-time of the power switch but is terminated during an OFF-time of the power switch. The switch controller is adopted to control the ON-time and the OFF-time of the power switch. During an initial period of a charging process, the soft-start circuit modulates the ON-time to gradually increase. Therefore, the capacitor charging circuit according to the present invention effectively reduces the inrush current and enhances the charging efficiency during the initial period of the charging process.

A first current detector is adopted to detect the primary winding current for generating a primary current detection signal. A reference voltage generator is controlled by the soft-start circuit for generating a soft-start reference voltage. A first voltage comparator is adopted to compare the primary current detection signal with the soft-start reference voltage so as to output an ON-time ending signal to the switch controller. A second current detector is adopted to detect a secondary winding current for generating a secondary current detection signal. A second voltage comparator is adopted to compare the secondary current detection signal with a predetermined reference voltage so as to output an OFF-time ending signal to the switch controller.

A minimum ON-time limiting unit is coupled to the switch controller or the first voltage comparator for preventing the power switch from being turned off before a minimum ON-time expires. Preferably, the minimum ON-time limiting unit is controlled by the soft-start circuit for modulating the minimum ON-time to gradually increase during the initial period of the charging process. A minimum OFF-time limiting unit is coupled to the switch controller or the second voltage comparator for preventing the power switch from being turned on before a minimum OFF-time expires. Therefore, the capacitor charging circuit according to the present invention effectively prevents the ON/OFF switching operations of the power switch from being erroneously triggered by the fluctuant noise of the winding currents.

A maximum ON-time limiting unit is coupled to the switch controller for preventing the power switch from still remaining ON after a maximum ON-time expires. Therefore, the capacitor charging circuit effectively prevents the charging process from being deteriorated by the drop of the battery voltage.

DETAILED DESCRIPTION

The preferred embodiments according to the present invention will be described in detail with reference to the drawings.

FIG. 1is a circuit block diagram showing a capacitor charging circuit10according to a first embodiment of the present invention. Referring toFIG. 1, under the ON/OFF switching operations of a power switch SW, a battery voltage Vbatis regulated to provide an output voltage for charging a capacitive load Cload. In one embodiment of the present invention, the power switch SW may be implemented by an NMOS transistor manufactured in a high voltage semiconductor process. A primary winding L1and a secondary winding L2are arranged to have opposite polarities, as indicated by black dots inFIG. 1, and therefore the transformer11belongs to a flyback type. When the power switch SW is at the ON state, the battery voltage Vbatsupplies a primary winding current Iprito store energy in the transformer11. Meanwhile, a secondary winding current Isecis zero and the terminal voltage Voutacross the capacitive load Cloadremains unchanged. When the power switch SW is at the OFF state, the battery voltage Vbatstops supplying the primary winding current Ipri. Meanwhile, the energy stored in the transformer11is delivered to the capacitive load Cloadthrough the secondary winding current Isec, causing the terminal voltage Voutto increase. Arranged between the secondary winding L2and the capacitive load Cload, a diode D is adopted to allow the secondary current Isecto charge the capacitive load Cloadand prevent the capacitive load Cloadfrom backwardly discharging to the secondary winding L2.

Based on the variations of the primary and secondary winding currents Ipriand Isec, a switch controller12generates a switch control signal DRV for determining the ON/OFF switching operations of the power switch SW. More specifically, a current detector13is adopted to detect the primary winding current Iprifor generating a primary current detection signal Vpri. The primary current detection signal Vpriis coupled to a non-inverting input terminal of a voltage comparator15. A reference voltage generator14outputs a soft-start reference voltage Vrsto an inverting input terminal of the voltage comparator15. When the power switch SW is at the ON state, the battery voltage Vbatdelivers energy to the transformer11, causing the primary current detection signal Vprito gradually increase from zero. Once the primary current detection signal Vprireaches the soft-start reference voltage Vrs, an ON-time ending signal Vongenerated by the voltage comparator15makes a transition from LOW to HIGH and then triggers the switch controller12to finish the ON-time and begin the OFF-time of the power switch SW. As a result, the primary winding current Ipriis terminated to become zero. Based on the back electromotive force of the inductive windings, the secondary winding current Isecjumps from zero to a value determined by the primary winding current Ipriimmediately before terminated and the winding ratio L2/L1.

During the OFF-time of the power switch SW, the secondary winding current Iseccharges the capacitive load Cloadand therefore continuously decreases. A secondary current detection signal Vsecis generated by a series-connected resistor Rsecthrough detecting the secondary winding current Isec. The secondary current detection signal Vsecis coupled to a non-inverting input terminal of a voltage comparator16while a predetermined reference voltage Vris coupled to an inverting input terminal of the voltage comparator16. Once the secondary current Isecbecomes low enough for causing the voltage comparator16to generate a HIGH level of an OFF-time ending signal Voff, the switch controller12is triggered to finish the OFF-time and begin the ON-time of the power switch SW. As a result, the secondary winding current Isecis terminated to become zero. Based on the back electromotive force of the inductive windings, the primary winding current Iprijumps from zero to a value determined by the secondary winding current Isecimmediately before terminated and the winding ratio L1/L2. The charging cycle described above is continuously repeated for raising the terminal voltage Voutacross the capacitive load Cloadto several hundreds volts.

In one embodiment of the present invention, the current detector13may be implemented by a series-connected resistor. In another embodiment of the present invention, the current detector13may be implemented according to the disclosure of the US Patent Publication No. 2004-0130359, entitled “Current Sensing Circuit And Method Of A High-Speed Driving Stage,” filed by the Assignee, and published on Jul. 8, 2004, which is incorporated herein by reference.

The capacitor charging circuit10is further provided with a soft-start circuit17and a time limiter18for enhancing the charging efficiency. In response to a charge command signal CH, the soft-start circuit17outputs a soft-start signal SS to the reference voltage generator14and the time limiter18. In response to the soft-start signal SS, the reference voltage generator14outputs the soft-start reference voltage Vrsto the voltage comparator15. In response to the soft-start signal SS and the switch control signal DRV, the time limiter18outputs a minimum ON-time limiting signal Tonmin, a maximum ON-time limiting signal Tonmax, and a minimum OFF-time limiting signal Toffminto the switch controller12.

FIG. 2(a) is a detailed circuit diagram showing an example of the soft-start circuit17according to the first embodiment of the present invention. When the charge command signal CH is at the LOW level, an inverter Nsoutputs HIGH to turn on an NMOS transistor Qs. As a result, the soft-start signal SS is coupled to a ground potential. When the charge command signal CH is at the HIGH level to activate the capacitor charging circuit10for the charging process, the inverter Nsoutputs LOW to turn off the NMOS transistor Qs. A current source Isstarts charging a capacitor Cs, causing the soft-start signal SS to gradually increase from the ground potential until being clamped by forward bias drops of diodes D1and D2.

FIG. 2(b) is a detailed circuit diagram showing an example of the reference voltage generator14according to the first embodiment of the present invention. Referring toFIG. 2(b), the soft-start signal SS is coupled to a first non-inverting input terminal of a voltage comparator CP. A predetermined reference voltage Vr1is coupled to a second non-inverting input terminal of the voltage comparator CP. An output terminal of the voltage comparator CP is coupled to control a gate electrode of an NMOS transistor Qv1. A source electrode of the NMOS transistor Qv1is coupled to an inverting input terminal of the voltage comparator CP and a resistor R1. In one embodiment, the reference voltage Vr1is set smaller than the stable value of the soft-start signal SS, in which the stable value of the soft-start signal SS is, for example, equal to the forward bias drops of the diodes D1and D2as shown inFIG. 2(a). PMOS transistors Qv2and Qv3constitute a current mirror for generating the soft-start reference voltage Vrs. A drain electrode of the transistor Qv2is coupled to a drain electrode of the transistor Qv1while a drain electrode of the transistor Qv3is coupled to a resistor R2. Therefore, when the soft-start signal SS is smaller than the reference voltage Vr1, the soft-start reference voltage Vrsgradually increases along with the increase of the soft-start signal SS. Once the soft-start signal SS becomes larger than the reference voltage Vr1, the soft-start reference voltage Vrsis determined by the reference voltage Vr1and therefore remains stable.

In one embodiment of the present invention, the time limiter18includes a minimum ON-time limiting unit18-1, a maximum ON-time limiting unit18-2, and a minimum OFF-time limiting unit18-3for respectively generating the minimum ON-time limiting signal Tonmin, the maximum ON-time limiting signal Tonmax, and the minimum OFF-time limiting signal Toffmin.FIG. 2(c) is a detailed circuit diagram showing an example of the minimum ON-time limiting unit18-1according to the first embodiment of the present invention.FIG. 2(d) is a detailed circuit diagram showing an example of the maximum ON-time limiting unit18-2according to the first embodiment of the present invention.FIG. 2(e) is a detailed circuit diagram showing an example of the minimum OFF-time limiting unit18-3according to the first embodiment of the present invention.

Referring toFIG. 2(c), when the switch control signal DRV is at the LOW level to turn off the power switch SW ofFIG. 1, an inverter N1outputs HIGH to turn on an NMOS transistor Q1. As a result, a non-inverting input terminal of a voltage comparator CP1is coupled to the ground potential, and therefore the voltage comparator CP1outputs a LOW level of the minimum ON-time limiting signal Tonmin. Once the switch control signal DRV makes a transition from LOW to HIGH to turn on the power switch SW ofFIG. 1, the inverter N1outputs LOW to turn off the NMOS transistor Q1. In this case, a current source11is allowed to charge a capacitor C1such that the voltage at the non-inverting input terminal of the voltage comparator CP1eventually becomes larger than that at the inverting input terminal of the voltage comparator CP1, and then the HIGH level of the minimum ON-time limiting signal Tonminis output. As appreciated from the following detailed description with regard to the switch controller12, the switch control signal DRV is constrained at the HIGH level for ensuring that the power switch SW remains ON if the minimum ON-time limiting signal Tonminis at the LOW level. Therefore, such a time interval from the occurrence of the HIGH level of the switch control signal DRV until the occurrence of the HIGH level of the minimum ON-time limiting signal Tonminis referred to as the minimum ON-time of the power switch SW according to the present invention.

It should be noted that the minimum ON-time limiting unit18-1according to the present invention may, based on the soft-start signal SS, determine when to generate the HIGH level of the minimum ON-time limiting signal Tonmin, thereby also performing a soft-start modulation on the minimum ON-time. As shown inFIG. 2(c), the soft-start signal SS is coupled to a gate electrode of a PMOS transistor Q2for controlling the supply of a current source I2to the capacitor C1. When the soft-start signal SS gradually increases from the ground potential to the stable value, the current source I2gradually reduces the portion supplied to the capacitor C1because the differential pair constituted by the PMOS transistors Q2and Q3distributes the current source I2between the two current paths in proportion to the ratio of the soft-start signal SS and the reference voltage Vr2. In other words, during the initial period of the charging process of the capacitor charging circuit10, the soft-start signal SS is much smaller than the reference voltage Vr2such that the current source I2almost completely flows through the transistor Q2for charging the capacitor C1. In this case, the terminal voltage across the capacitor C1increases with a greater rate such that the HIGH level of the minimum ON-time limiting signal Tonminoccurs much earlier. That is, the minimum ON-time limiting unit18-1provides a shorter minimum ON-time. Along with the increase of the soft-start signal SS, the current source12reduces the portion supplied to charge the capacitor C1such that the HIGH level of the minimum ON-time limiting signal Tonminoccurs later and later. That is, the minimum ON-time limiting unit18-1provides a longer minimum ON-time. Therefore, the minimum ON-time provided by the minimum ON-time limiting unit18-1is also subjected to the soft-start modulation from shorter to longer.

Referring toFIG. 2(d), when the switch control signal DRV is at the LOW level to turn off the power switch SW ofFIG. 1, an inverter N2outputs HIGH to turn on an NMOS transistor Q4. As a result, a non-inverting input terminal of a voltage comparator CP2is coupled to the ground potential, and therefore the voltage comparator CP2outputs the LOW level of the maximum ON-time limiting signal Tonmax. Once the switch control signal DRV makes a transition from LOW to HIGH for turning on the power switch SW ofFIG. 1, the inverter N2outputs LOW to turn off the NMOS transistor Q4. In this case, a current source13is allowed to charge a capacitor C2such that the voltage at the non-inverting input terminal of the voltage comparator CP2eventually becomes larger than that at the inverting input terminal of the voltage comparator CP2, and then the HIGH level of the maximum ON-time limiting signal Tonmaxis output. As appreciated from the following detailed description with regard to the switch controller12, the HIGH level of the maximum ON-time limiting signal Tonmaxtriggers the switch control signal DRV to become LOW for turning off the power switch SW ofFIG. 1. Therefore, such a time interval from the occurrence of the HIGH level of the switch control signal DRV until the occurrence of the HIGH level of the maximum ON-time limiting signal Tonmaxis referred to as the maximum ON-time of the power switch SW according to the present invention.

Referring toFIG. 2(e), when the switch control signal DRV is at the HIGH level to turn on the power switch SW ofFIG. 1, an NMOS transistor Q5is turned on for coupling a non-inverting input terminal of a voltage comparator CP3to the ground potential, and therefore the LOW level of the minimum OFF-time limiting signal Toffminis output. Once the switch control signal DRV makes a transition from HIGH to LOW for turning off the power switch SW ofFIG. 1, the NMOS transistor Q5is turned off for allowing a current source14to charge a capacitor C3. In this case, once the voltage at the non-inverting input terminal is eventually larger than that at the inverting input terminal, the voltage comparator CP3outputs the HIGH level of the minimum OFF-time limiting signal Toffmin. As appreciated from the following detailed description with regard to the switch controller12, the switch control signal DRV is constrained at the LOW level for ensuring that the power switch SW remains OFF if the minimum OFF-time limiting signal Toffminis at the LOW level. Therefore, such a time interval from the occurrence of the LOW level of the switch control signal DRV until the occurrence of the HIGH level of the minimum OFF-time limiting signal Toffminis referred to as the minimum OFF-time of the power switch SW according to the present invention.

FIG. 2(f) is a detailed circuit diagram showing an example of the switch controller12according to the first embodiment of the present invention. Referring toFIG. 2(f), the switch controller12is a logical control circuit including two AND logic gates A1and A2, an OR logic gate O1, and an SR latch LA. The AND logic gate A1has two input terminals for receiving the ON-time ending signal Vonand the minimum ON-time limiting signal Tonmin, respectively. The AND logic gate A2has two input terminals for receiving the minimum OFF-time limiting signal Toffminand the OFF-time ending signal Voff, respectively. The OR logic gate O1has two input terminals coupled to the output terminal of the AND logic gate A1and the maximum ON-time limiting signal Tonmax, respectively. The SR latch LA has a reset input terminal R coupled to the output terminal of the OR logic gate O1, a set input terminal S coupled to the output terminal of the AND logic gate A2, and a non-inverting terminal Q for providing the desired switch control signal DRV.

Hereinafter is described in detail the operations and advantageous effects achieved by the capacitor charging circuit10according to the present invention.FIG. 3is a waveform timing chart showing a soft-start characteristic according to the present invention.FIG. 4is a waveform timing chart showing the primary winding current Ipriand the secondary winding current Isecaccording to the present invention.FIG. 5is a waveform timing chart showing the charging process in response to the drop of the battery voltage Vbataccording to the present invention.

Referring toFIG. 3, the charge command signal CH enters the HIGH level for activating the charging process of the capacitor charging circuit10. The soft-start signal SS gradually increases from the ground potential to the stable value. The soft-start reference voltage Vrsgradually increases along with the soft-start signal SS, and reaches the stable value earlier than the soft-start signal SS. The stable value of the soft-start reference voltage Vrsmay be set smaller than the stable value of the soft-start signal SS. The charging period before the soft-start reference voltage Vrsreaches the stable value is referred to as a soft-start charging period, and the charging period after the soft-start reference voltage Vrsreaches the stable value is referred to as a stable charging period. During the soft-start charging period, the HIGH-time of the switch control signal DRV each charging cycle, corresponding to the ON-time of the power switch SW, gradually prolongs along with the increase of the soft-start reference voltage Vrs. During the stable charging period, the HIGH-time of the switch control signal DRV each charging cycle remains constant because the soft-start reference voltage Vrshas already been stable. Since the ON-time of the power switch SW has such a soft-start modulation characteristic, the capacitor charging circuit10according to the present invention effectively prevents the large inrush current from flowing into the primary winding L1of the transformer11during the initial period of the charging process. As a result, a smaller amount of energy is to be stored in the transformer11each charging cycle, saving the time necessary for delivering the energy to the capacitive load Cloadeven when the terminal voltage Voutacross the capacitive load Cloadis almost zero. Therefore, the capacitor charging circuit10according to the present invention effectively enhances the charging efficiency during the initial period of the charging process.

Referring toFIG. 4, during the HIGH level of the switch control signal DRV every charging cycle, the primary winding current Ipricontinuously increases due to the energy delivery from the battery voltage Vbatto the transformer11while the secondary winding current Isecis terminated to zero. During the LOW level of the switch control signal DRV every charging cycle, the secondary winding current Iseccontinuously decreases due to the energy delivery from the transformer11to the capacitive load Cloadwhile the primary winding current Ipriis terminated to zero. Each time when the switch control signal DRV makes HIGH-to-LOW or LOW-to-HIGH transitions, i.e. the power switch SW performs the ON/OFF switching operations, the primary and secondary winding currents Ipriand Isecinevitably fluctuate up and down with a great ratio to their DC values.

In order to avoid erroneous switching caused by such fluctuant noise, the capacitor charging circuit10is provided with the minimum ON-time limiting signal Tonminand the minimum OFF-time limiting signal Toffmin. As clearly seen fromFIG. 4, the fluctuant noise associated with the LOW-to-HIGH transition of the switch control signal DRV completely occurs within a period when the minimum ON-time limiting signal Tonminstill remains LOW. In this case, the AND logic gate A1ofFIG. 2(f) always outputs LOW regardless of the ON-time ending signal Von, thereby effectively preventing the fluctuant noise from erroneously triggering the switch control signal DRV. Furthermore, the fluctuant noise associated with the HIGH-to-LOW transition of the switch control signal DRV completely occurs within a period when the minimum OFF-time limiting signal Toffminstill remains LOW. In this case, the AND logic gate A2ofFIG. 2(f) always outputs LOW regardless of the OFF-time ending signal Voff, thereby effectively preventing the fluctuant noise from erroneously triggering the switch control signal DRV.

Incidentally, during the soft-start charging period, the maximum value of the primary winding current Iprieach charging cycle gradually increases because of the increase of the soft-start reference voltage Vrs. However, during the stable charging period, the maximum value of the primary winding current Iprieach charging cycle remains constant due to the stable value of the soft-start reference voltage Vrs.

Referring toFIG. 5, in the case that the battery voltage Vbatis normal or high enough, the primary winding current Ipriincreases with a normal rate during the HIGH level of the switch control signal DRV. When the primary winding current Iprireaches the upper limit determined by the soft-start reference voltage Vrs, the ON-time ending signal Vonthrough the switch controller12triggers the switch control signal DRV to become LOW, as described above. After continuously supplying energy for a long time, the battery voltage Vbatmay be subjected to a significant drop. In the case that the battery voltage Vbatis too low, the primary winding current Ipriincreases with a much slower rate during the HIGH level of the switch control signal DRV. Consequently, each charging cycle is prolonged, causing the larger output ripples and lower charging efficiency.

As a countermeasure, the capacitor charging circuit10is provided with the maximum ON-time limiting signal Tonmax. When the switch control signal DRV has already stayed HIGH for a predetermined maximum ON-time, the maximum ON-time limiting signal Tonmaxthrough the switch controller12triggers the switch control signal DRV to become LOW even if the primary winding current Ipriis still smaller than the upper limit. Therefore, the capacitor charging circuit10according to the present invention effectively prevents the charging process from being deteriorated by the drop of the battery voltage Vbat.

FIG. 6is a circuit block diagram showing a capacitor charging circuit10′ according to a second embodiment of the present invention. The capacitor charging circuit10′ of the second embodiment shown inFIG. 6is different from the capacitor charging circuit10of the first embodiment shown inFIG. 1in that: (1) the minimum ON-time limiting unit18-1outputs the minimum ON-time limiting signal Tonminto a voltage comparator15′ for preventing an ON-time ending signal Von′ from becoming LOW before the minimum ON-time expires; (2) the minimum OFF-time limiting unit18-3outputs the minimum OFF-time limiting signal Toffminto a voltage comparator16′ for preventing an OFF-time ending signal Voff′ from becoming LOW before the minimum OFF-time expires; and (3) a switch controller12′ generates the switch control signal DRV in response to the ON-time ending signal Von′, the OFF-time ending signal Voff′, and the maximum ON-time limiting signal Tonmax.

FIG. 7(a) is a detailed circuit diagram showing an example of the voltage comparator15′ according to the second embodiment of the present invention. Referring toFIG. 7(a), the voltage comparator15′ is formed by a switch transistor Q6and an inverter N3coupled to the non-inverting input terminal of the voltage comparator15ofFIG. 1. When the minimum ON-time limiting signal Tonminis at the LOW level, the inverter N3outputs HIGH to turn on the switch transistor Q6. As a result, the non-inverting input terminal of the voltage comparator15is coupled to the ground potential. In this case, the ON-time ending signal Vonis constrained at the LOW level for effectively avoiding the influence of the fluctuant noise. When the HIGH level of the minimum ON-time limiting signal Tonminoccurs, i.e. the minimum ON-time expires, the inverter N3outputs LOW and stops turning on the switch transistor Q6. As a result, the non-inverting input terminal of the voltage comparator15returns to normally receive the primary current detection signal Vpriso as to perform the comparison function described in the first embodiment.

FIG. 7(b) is a detailed circuit diagram showing an example of the voltage comparator16′ according to the second embodiment of the present invention. Referring toFIG. 7(b), the voltage comparator16′ is formed by a switch transistor Q7and an inverter N4coupled to the non-inverting input terminal of the voltage comparator16ofFIG. 1. When the minimum OFF-time limiting signal Toffminoff is at the LOW level, the inverter N4outputs HIGH to turn on the switch transistor Q7. As a result, the non-inverting input terminal of the voltage comparator16is coupled to the ground potential. In this case, the OFF-time ending signal Voffis constrained at the LOW level for effectively avoiding the influence of the fluctuant noise. When the HIGH level of the minimum OFF-time limiting signal Toffminoccurs, i.e. the minimum OFF-time expires, the inverter N4outputs LOW and stops turning on the switch transistor Q7. As a result, the non-inverting input terminal of the voltage comparator16returns to normally receive the secondary current detection signal Vsecso as to perform the comparison function described in the first embodiment.

FIG. 7(c) is a detailed circuit diagram showing an example of the switch controller12′ according to the second embodiment of the present invention. As described above, since the ON-time ending signal Von′ is constrained at the LOW level before the minimum ON-time expires, the ON-time ending signal Von′ is equivalent in logic to the output signal of the AND logic gate A1ofFIG. 2(f). Likely, since the OFF-time ending signal Voff′ is constrained at the LOW level before the minimum OFF-time expires, the OFF-time ending signal Voff′ is equivalent in logic to the output signal of the AND logic gate A2ofFIG. 2(f). Therefore, in the switch controller12′ ofFIG. 7(c), the OR logic gate O1has two input terminals coupled to the ON-time ending signal Von′ and the maximum ON-time limiting signal Tonmax, respectively. The SR latch LA has the reset input terminal R coupled to the output terminal of the OR logic gate O1, the set input terminal S coupled to the OFF-time ending signal Voff′, and the non-inverting output terminal Q for providing the desired switch control signal DRV.

While the invention has been described by way of examples and in terms of preferred embodiments, it is to be understood that the invention is not limited to the disclosed embodiments. To the contrary, it is intended to cover various modifications. Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications.