System and method for photolithography in semiconductor manufacturing

A method for photolithography in semiconductor manufacturing includes providing a substrate for a wafer and providing a mask for exposing the wafer. The wafer is exposed by utilizing a combination of high angle illumination and focus drift exposure methods.

BACKGROUND

The present disclosure relates generally to the manufacturing of semiconductor devices, and more particularly to a photolithography process in semiconductor manufacturing.

Since the inception of the semiconductor industry, photolithography has been used for forming the components of integrated circuits. The continued increase in the density of components that can be placed on a chip has been largely due to advances in photolithography, and especially the ever decreasing wavelengths of radiation. As long as the critical dimension of the components is greater than the wavelength of the radiation used to expose the photoresist, advances in the art do not require any significant changes of the masks.

However, when the wavelength of the imaging radiation is larger than the critical dimension, the effects of diffraction, though always present, become sufficiently prominent to introduce noticeable distortions into the projected images. Those distortions are particularly sensitive to the distances between the various features in the image pattern and are frequently referred to as “proximity effects.”

Another problem associated with photolithography at wavelengths close to the critical dimensions is depth of focus (DOF). In particular, when the DOF is less than the thickness of the resist being exposed, image sharpness will be lost. In practice, because of diffraction effects, the resulting image often becomes a blurred circle.

When resolution is not a concern, DOF can be increased by restricting the incoming light to the center of the lens, thus reducing the angle of the light cone so that focused rays travel further before leaving the blurred circle. However, when resolution is also a consideration, that solution is no longer acceptable.

Traditionally, approaches for increasing DOF have been directed toward bringing both densely packed and isolated contact holes into simultaneous focus. However, since the increase of DOF for densely packed contact holes often result in the decrease of the DOF for isolated contact holes, such efforts frequently result in unfocused images. For example, to balance respective DOFs for densely packed and isolated contact holes, previously available art utilizes multiple or continuing exposures with conventional illumination to enhance DOF. However, such an approach results in poor DOF for dense holes.

Therefore, it is desirable to improve the existing lithography system and method.

DETAILED DESCRIPTION

The present disclosure presents a new approach of lithography that utilizes a combination of high angle illumination and focus drift exposure methods. The high angle illumination method including off-axis illumination will be further described below in connections withFIGS. 3-6. The focus drift exposure, which may include multiple exposures and/or wafer/mask titling as well as dry or wet lithography, will be further described below.

Referring now toFIG. 1, shown therein is a simplified photolithography method10for implementing one or more embodiments of the present invention. The method initiates with step12, which provides a photo-resist coated substrate. Pursuant to step14, a mask for exposing the wafer is provided. Finally, pursuant to step16of the method10, the wafer is exposed utilizing a combination of high angle illumination and focus drift exposure methods.

The method10may be utilized in the manufacturing of a variety of semiconductor devices, such as memory devices (including but not limited to a static random access memory (SRAM)), logic devices (including but not limited to a metal-oxide semiconductor field-effect transistor (MOSFET)), and/or other devices. The method10begins at step12wherein a wafer is provided.

Referring now toFIG. 2, a wafer28used in step12of the method10can be illustrated as part of a simplified exemplary lithography system20. In this embodiment, a light source21emits light beams23, which are condensed by a condenser22. The wavelength of the light source is less than 250 nm, and in the present embodiments about 248 nm, 193 nm, or 157 nm. As a result, a mask24, which includes patterns, is illuminated uniformly by light beams27. After passing through the mask24, light beams25are focused by a projection lens26prior to being projected onto the wafer28.

It is noted since the lithography system20is known in the art, most components thereof will not be further described herein.

Pursuant to step16of the method10, the wafer28is exposed utilizing a combination of high angle illumination and focus drift exposure methods, each of which will be described below.

The high illumination method will now be further described. In one example, the light source21may be adjusted by methods known in the art to provide high angle illumination as illustrated inFIGS. 3-6.

Referring now toFIG. 3, in one example, a substantially circular area C1has been formed within an illumination area30, with a radius29of about 1 sigma. The area C1, which may have a radius31that is approximately at least 0.65 sigma, may be represented by a filter or any other devices, and may possess a light transmission rate of approximately between about 0% and about 100%. In the present embodiment, the light transmission rate is approximately between about 20% and about 100%.

Referring now toFIG. 4, in another example, a first substantially circular area C2and a second adjacent torus-shaped area A2adjacent to the first substantially circular area C2have been formed within an illumination area35with a radius33of about 1 sigma. The area C2, which has a radius32that is approximately at least 0.2 sigma, may be represented by a filter or any other devices, and may possess a light transmission rate of approximately between about 0% and about 100%. In the present embodiment, the light transmission rate is approximately between about 20% and about 100%. The area A2, which has an inner radius32that is approximately at least 0.2 sigma, and an outer radius34that is at least approximately 0.7 sigma, may be represented by a filter or any other devices, and may possess a light transmission rate of approximately between about 0% and about 100%. In the present embodiment, the light transmission rate is approximately between about 20% and about 100%.

Referring now toFIG. 5, in another example, a first substantially circular area C3and two torus-shaped areas (A3and a second torus-shaped area B3) have been formed within an illumination area40with a radius37of about 1 sigma. The area C3, which has a radius36that is approximately at least 0.2 sigma, may be represented by a filter or any other devices, and may possess a light transmission rate of approximately between about 0% and about 100%. In the present embodiment, the light transmission rate is approximately between about 20% and about 100%.

The area B3is adjacent to the first substantially circular area C3. The area A3is not adjacent to the first substantially circular area C3. The area A3has an inner radius38that is greater than approximately 0.2 sigma, and an outer radius41that is approximately at least 0.7 sigma. The area A3may be represented by a filter or any other devices, and may possess a light transmission rate of approximately between about 0% and about 100%. In the present embodiment, the light transmission rate is approximately between about 20% and about 100%. It is noted that the area B3that is between the areas A3and C3may have a light transmission rate of about 0%.

Referring now toFIG. 6, in one example, a first substantially circular area C4and a plurality of second areas A4around the circumference of the area C4have been formed within an illumination area48. The area C4, which may have a radius42of about at least 0.2 sigma, may be represented by a filter or any other devices, and may possess a light transmission rate of approximately between about 0% and about 100%. In the present embodiment, the light transmission rate is approximately between about 20% and about 100%.

It is contemplated that each of the areas A4may be identical or different, and only a single area A4may be present. In the present example, at least one of the areas A4may have an inner radius42that is approximately at least 0.2 sigma, and an outer radius44that is approximately at least 0.7 sigma. It is noted that at least one of the areas A4may be represented by a filter or any other devices, and may possess a light transmission rate of approximately between about 0% and about 100%. In the present embodiment, the light transmission rate is approximately between about 20% and about 100%. In one embodiment, an angle46is at least about 30 degrees.

The focus drift exposure method will now be further described. Referring now toFIG. 7, in one example, the wafer28may be tilted at an angle52, which is between about 30 and about 250 micro radians (urad), for purposes of exposing the wafer28. For illustration purposes, a pattern50afrom the mask may be formed on the wafer28as a corresponding pattern50b.

Referring toFIG. 8, in another example, the mask24may be a high precision plate containing microscopic images of electronic circuits. The mask24may include a variety of materials, such as quartz, soda lime, white crown, and/or other materials. Generally, a layer of chrome may be included on one side of the mask24, and electronic circuits (frequently referred to as geometry) may be etched in the chrome layer. The thickness of the mask24may be any suitable thickness known in the art. In one example, the mask24may be tilted at an angle54, which is between about 120 and about 1000 milli-radians (mrad), for purposes of exposing the wafer28. It is contemplated that both the mask24and the wafer28may be titled tilted for an identical exposure process.

In furtherance of the example, the focus drift exposure method may include at least two exposures, which may be used independently or in combination with the structures ofFIG. 7and/orFIG. 8. The multiple exposures may be accomplished by scanning or static methods, and/or other methods known in the art. In one example, the focus ranges for first and second exposures may be approximately between about 0.1 mm and about 0.6 mm. In a second example, the focus difference between multiple exposures may be between about 0.1 mm and about 0.4 mm. However, it is noted that other focus ranges/differences are also contemplated by the present disclosure. Since multiple exposures are known in the art, they will not be further described herein.

Referring now toFIG. 9, for the sake of example, the wafer28ofFIG. 2is expanded to include a substrate110, a dielectric layer114, an anti-reflective coating layer120, and a photoresist layer122.

The substrate110may include one or more insulator, conductor, and/or semiconductor layers. For example, the substrate110may include an elementary semiconductor, such as crystal silicon, polycrystalline silicon, amorphous silicon, and/or germanium; a compound semiconductor, such as silicon carbide and/or gallium arsenic; an alloy semiconductor, such as SiGe, GaAsP, AlInAs, AlGaAs, and/or GaInP. Further, the substrate110may include a bulk semiconductor, such as bulk silicon, and such a bulk semiconductor may include an epi silicon layer. It may also or alternatively include a semiconductor-on-insulator substrate, such as a silicon-on-insulator (SOI) substrate, or a thin-film transistor (TFT) substrate. The substrate110may also or alternatively include a multiple silicon structure or a multilayer compound semiconductor structure.

The dielectric layer114may be deposited over the surface of the substrate110. The dielectric layer114may be formed by chemical vapor deposition (CVD), plasma-enhanced CVD (PECVD), atomic layer deposition (ALD), physical vapor deposition (PVD), spin-on coating and/or other processes. The dielectric layer114may be an inter-metal dielectric (IMD), and may include low-k materials, silicon dioxide, polyimide, spin-on-glass (SOG), fluoride-doped silicate glass (FSG), Black Diamond® (a product of Applied Materials of Santa Clara, Calif.), Xerogel, Aerogel, amorphous fluorinated carbon, and/or other materials.

The anti-reflective coating layer120may be deposited over the dielectric layer114by a variety of techniques, including but not limited to spin-on coating, PVD, CVD, and/or other processes. In another embodiment, the anti-reflective coating layer120is formed by a dual arc approach, for example, one spin-on ARC film is coated on another CVD ARC film. In the present embodiment, the layer120is a bottom anti-reflective coating (BARC) with a thickness between 10 nm to 150 nm.

In the present embodiment, the anti-reflective coating layer120absorbs the light that inadvertently penetrates the bottom of a photoresist layer (not shown). To perform the light absorption, the anti-reflective coating layer120may include a material with a high extinction coefficient, and/or considerable thickness. On the other hand, a high coefficient of the anti-reflective coating layer120may lead to the high reflectivity of the anti-reflective coating layer, which counters the effectiveness of the anti-reflective coating layer120. Accordingly, it is contemplated that the anti-reflective coating layer120may possess a coefficient value at approximately between about 0.2 to about 0.5, and may possess a thickness of about 200 nm. However, it is noted that other ranges of coefficient values and thickness are also contemplated by the present disclosure.

Additionally or alternatively, an index matching approach may be adopted for the anti-reflective coating layer120. In that case, the anti-reflective coating layer120may include a material with a refraction index and thickness that match those of the light. In operation, once the light strikes the anti-reflective coating layer120, a portion of the light is reflected therefrom. Meanwhile, another portion of the light enters the anti-reflective coating layer120and is transformed into a light with a shifted phase, which interferes with the first portion of the light that is reflected from the anti-reflective coating layer120, resulting in the reduction of the light reflectivity.

It is contemplated that the anti-reflective coating layer120may employ both the light absorption and index matching approaches to achieve the desired results. In some instances, the anti-reflective coating layer120may simply remain over the dielectric layer114and serve as a diffusion barrier for the wafer18, as the removal of the anti-reflective coating layer120may be difficult to accomplish.

The photoresist layer122may be deposited over the anti-reflective coating layer120, and formed by spin-on coating and/or other processes. In operation, a photoresist solution is dispensed onto the surface of a partial wafer, and the wafer28is spun rapidly until the photoresist solution is almost dry. In one example, the photoresist layer112may be a chemically amplified resist that employs acid catalysis. In that case, the photoresist layer may be formulated by dissolving an acid sensitive polymer in a casting solution.

Following the deposition of the photoresist layer122, the wafer28may undergo a soft bake (known in the art) and an exposure process (described above in connection with the method10).

Thereafter, additional steps are adopted for forming a complete semiconductor device. Since those additional steps are known in the art, they will not be further described herein.

It is noted that many variations of the above example are contemplated herein. In one example, the method10may be applied to patterns that include at least one line. In a second example, the method10may be applied to patterns that include at least one hole. In a third example, the method10may be applied to patterns that include dense and isolated features. In a fourth example, the method10may be applied to patterns that include dense features. In a fifth example, the method10can be used as part of a non-damascene, damascene or dual-damascene process. Therefore, a variety of modifications are contemplated by this disclosure.

Although only a few exemplary embodiments of this disclosure have been described in details above, those skilled in the art will readily appreciate that many modifications are possible in the exemplary embodiments without materially departing from the novel teachings and advantages of this disclosure. Also, features illustrated and discussed above with respect to some embodiments can be combined with features illustrated and discussed above with respect to other embodiments. Accordingly, all such modifications are intended to be included within the scope of this disclosure.