An electrooptical device includes a substrate having pixel regions arranged in a matrix, pixel electrodes disposed in the pixel regions of the substrate, switching elements disposed between the pixel regions of the substrate and electrically connected to the pixel electrodes, capacitors disposed between the pixel regions of the substrate to hold electrical charge on the pixel electrodes, wiring disposed between the pixel regions of the substrate, and grooves disposed in a surface of the substrate so as to extend between the pixel regions thereof. The capacitors each include a first capacitor electrode, an insulating film, and a second capacitor electrode. The wiring includes data lines and scanning lines corresponding to the switching elements. The capacitors are at least partially disposed in the grooves.

BACKGROUND

1. Technical Field

The present invention relates to electrooptical devices, electronic apparatuses, and projectors.

2. Related Art

Electrooptical devices such as liquid crystal devices for use as, for example, light valves for projectors are often based on an active-matrix driving system including thin-film transistors (TFTs).

This type of liquid crystal device includes TFTs connected to pixel electrodes disposed in pixel regions. These TFTs are disposed in interpixel regions where data lines and scanning lines are also disposed to supply electrical signals to the TFTs. The liquid crystal device further includes capacitors that hold a predetermined electrical charge in operation to achieve stable operation.

Recently, more compact, higher-definition light valves having pixel regions with higher aperture ratios have been demanded. JP-A-2000-98409, JP-A-2002-31796, and JP-A-2002-244154, for example, discuss liquid crystal devices having capacitors formed in interpixel regions. Among these publications, JP-A-2000-98409 discloses a technique for forming grooves, called trenches, on a substrate and forming capacitor electrodes therein. This technique allows formation of capacitors along the bottoms and sidewalls of the trenches with high definition to efficiently increase capacitance without widening the interpixel regions.

The above technique, however, cannot sufficiently reduce the interpixel regions because the grooves are formed only in regions where the capacitors are to be formed. This technique therefore cannot significantly increase the aperture ratio of pixel regions.

SUMMARY

An advantage of some aspects of the invention is that they provide a more compact, higher-definition electrooptical device having pixel regions with a significantly increased aperture ratio and also provide an electronic apparatus and a projector which include the electrooptical device.

In electrooptical device according to a first aspect of the invention includes a substrate having pixel regions arranged in a matrix, pixel electrodes disposed in the pixel regions of the substrate, switching elements disposed between the pixel regions of the substrate and electrically connected to the pixel electrodes, capacitors disposed between the pixel regions of the substrate to hold electrical charge on the pixel electrodes, wiring disposed between the pixel regions of the substrate, and grooves disposed in a surface of the substrate so as to extend between the pixel regions thereof. The capacitors each include a first capacitor electrode, an insulating film, and a second capacitor electrode. The wiring includes data lines and scanning lines corresponding to the switching elements. The capacitors are at least partially disposed in the grooves.

That is, the capacitors are at least partially disposed in spaces defined by the grooves and a plane extending over the grooves along the surface of the substrate. According to the first aspect of the invention, the grooves are disposed in the surface of the substrate so as to extend between the pixel regions thereof, and the capacitors are at least partially disposed in the grooves so that the capacitors occupy smaller areas in interpixel regions Accordingly, the size of the electrooptical device can be reduced, and the area of the pixel regions can be increased relative to that of the interpixel regions. Thus, this structure contributes to size reduction and higher definition and can also significantly increase the aperture ratio of the pixel regions. In addition, the electrooptical device advantageously has increased light resistance because the area of the capacitors in the interpixel regions can be reduced to inhibit light reflection/absorption leading to an increase in the temperature of the device.

An electrooptical device according to a second aspect of the invention includes a substrate having pixel regions arranged in a matrix, pixel electrodes disposed in the pixel regions of the substrate, switching elements disposed between the pixel regions of the substrate and electrically connected to the pixel electrodes, capacitors disposed between the pixel regions of the substrate to hold electrical charge on the pixel electrodes, wiring disposed between the pixel regions of the substrate, and grooves disposed in a surface of the substrate so as to extend between the pixel regions thereof. The capacitors each include a first capacitor electrode, an insulating film, and a second capacitor electrode. The wiring includes data lines and scanning lines corresponding to the switching elements. The data lines are at least partially disposed in the grooves between the switching elements and the substrate.

According to the second aspect of the invention, the grooves are disposed in the surface of the substrate so as to extend between the pixel regions thereof, and the data lines are at least partially disposed in the grooves between the switching elements and the substrate so that the data lines occupy smaller areas in interpixel regions. Accordingly, the size of the electrooptical device can be reduced, and the area of the pixel regions can be increased. Thus, this structure contributes to size reduction and higher definition and can also significantly increase the aperture ratio of the pixel regions.

In addition, the data lines, which are formed of thin films in the known art, can be extended along the depth of the grooves to increase the cross-sectional area of the data lines. This allows for a reduction in the resistance of the data lines for efficient signal transmission. Furthermore, the electrooptical device advantageously has increased light resistance because the area of the data lines in the interpixel regions can be reduced to inhibit light reflection/absorption leading to an increase in the temperature of the device.

An electrooptical device according to a third aspect of the invention includes a substrate having pixel regions arranged in a matrix, pixel electrodes disposed in the pixel regions of the substrate, switching elements disposed between the pixel regions of the substrate and electrically connected to the pixel electrodes, capacitors disposed between the pixel regions of the substrate to hold electrical charge on the pixel electrodes, wiring disposed between the pixel regions of the substrate, and grooves disposed in a surface of the substrate so as to extend between the pixel regions thereof. The capacitors each include a first capacitor electrode, an insulating Film, and a second capacitor electrode. The wiring includes data lines and scanning lines corresponding to the switching elements. The capacitors are at least partially disposed in the grooves. The data lines are at least partially disposed in the grooves between the switching elements and the substrate.

According to the third aspect of the invention, the grooves are disposed in the surface of the substrate so as to extend between the pixel regions thereof, and the capacitors are at least partially disposed in the grooves so that the capacitors occupy smaller areas in interpixel regions. Also, the data lines are at least partially disposed. In the grooves between the switching elements and the substrate so that the data lines occupy smaller areas in the interpixel regions. Accordingly, the size of the electrooptical device can be reduced, and the area of the pixel regions can be increased. Thus, this structure contributes to size reduction and higher definition and can also significantly increase the aperture ratio of the pixel regions. In addition, the capacitors, the wiring, and the switching elements can be stacked in layers. Such a structure advantageously facilitates production of the electrooptical device.

Furthermore, the electrooptical device advantageously has increased light resistance because the areas of the capacitors and the data lines in the interpixel regions can be reduced to inhibit light reflection/absorption leading to an increase in the temperature of the device.

Preferably, the scanning lines are at least partially disposed in the grooves. In this case, the scanning lines occupy smaller areas in the interpixel regions. Accordingly, the size of the electrooptical device can be reduced, and the area of the pixel regions can be increased.

Preferably, the cross-sectional area of the grooves is larger on the opening side thereof than on the bottom side thereof. In this case, side surfaces of the grooves can be successfully covered with thin films such as the capacitors.

The electrooptical device according to the first aspect of the invention may further include light-shielding portions that cover intersection regions of the data lines and the scanning lines in plan view and do not overlap the pixel regions in plan view, and the width of the data lines and the scanning lines is preferably smaller than the maximum width of the light-shielding portions. If the width of the data lines and the scanning lines is smaller than the maximum width of the light-shielding portions, the area of the pixel regions can be increased to increase the aperture ratio thereof. In addition, if the maximum width of the light-shielding portions is larger than the width of the data lines and the scanning lines, light can be efficiently utilized by collecting it into the pixel regions in a circle using, for example, microlenses. Furthermore, if the light-shielding portions do not overlap the pixel regions in plan view, light can be efficiently utilized without being blocked when entering the pixel regions.

Alternatively, the electrooptical device may further include light-shielding portions covering the intersection regions of the data lines and the scanning lines in plan view and overlapping the pixel regions in plan view, and the width of the data lines and the scanning lines is preferably smaller than the maximum width of the light-shielding portions. Even if the light-shielding portions overlap the pixel regions in plan view, the area of the pixel regions can be increased to increase the aperture ratio thereof because the width of the data lines and the scanning lines is smaller than the maximum width of the light-shielding portions.

Preferably, the grooves extend along the capacitor electrodes of the capacitors and the wiring; the capacitor electrodes and the wiring are at least partially disposed in the grooves and are separated by insulating films; and the capacitor electrodes extend through the grooves along the wiring. In this case, both the capacitor electrodes and the wiring can be disposed in the interpixel regions without contact even though the interpixel regions are narrow regions.

Preferably, the capacitor electrodes are closer to the side surfaces of the grooves than the wiring. That is, the capacitor electrodes can be disposed outside the wiring in the grooves to increase the surface area of the capacitor electrodes. For example, the surface area of the capacitor electrodes can be increased by forming them on the side surfaces of the grooves.

Preferably, the capacitor electrodes are formed along bottom and side surfaces of the grooves. In this case, the surface area of the capacitor electrodes can be increased.

Preferably, the switching elements overlap the intersection regions of the wiring in plan view; the wiring has flat portions electrically connected thereto and extending from regions of the grooves corresponding to the intersection regions; and the switching elements and the flat portions are connected via contact holes. In this case, alignment can be easily performed to avoId connection defects even if the switching elements and the wiring are separated from each other in a direction parallel to the surface of the substrate. In addition, the switching elements and the wiring can be connected via the flat portions to ensure a sufficient contact area therebetween, stabilizing signal transmission and thus the operation of the switching elements.

Preferably, the switching elements are disposed in regions covered by the light-shielding portions in plan view. The intersection regions of the data lines and the scanning lines are positioned in regions surrounded by four corners of the pixel regions (intercorner regions). If the switching elements are disposed in the regions covered by the light-shielding portions in plan view, the switching elements overlap the corners of the pixel regions in plan view. If the light-shielding portions overlap the pixel regions in plan view, the light-shielding portions not only protect the switching elements from light, but also block light entering the corners of the pixel regions (pixel corner light).

It is known that the pixel corner light contributes to decreased image contrast in comparison with light passing through the centers of the pixel regions (pixel center light). According to the above aspects of the invention, the intensity of the pixel center light is increased because the aperture ratio of the pixel regions is increased relative to that of the known art. Accordingly, the intensity of the pixel center light, which contributes to higher contrast, is increased while the pixel corner light, which contributes to lower contrast, is blocked by the switching elements. This allows for a higher proportion of high-contrast light and thus a higher total contrast than those achieved by the known art.

It is also known that light passing through the periphery of the pixel regions other than the corners thereof (pixel periphery light) contributes to decreased image contrast in comparison with the pixel center light. If the switching elements are disposed in regions including the interpixel regions, the light-shielding portions covering the switching elements block the pixel periphery light. Accordingly, the intensity of the pixel central light, which contributes to higher contrast, is increased while the pixel periphery light, which contributes to lower contrast, is blocked by the switching elements. This allows for a higher proportion of high-contrast light and thus a higher total contrast than those achieved by the known art.

The electrooptical device preferably further includes microlenses that collect light into the pixel regions. Use of the microlenses for pixel regions having an increased aperture ratio can produce a synergistic effect of increasing light availability. In particular, the microlenses can also collect the pixel corner light, which would otherwise be blocked at the corners of the pixel regions if the switching elements are disposed therebetween, into the centers of the pixel regions to further increase the light availability.

An electronic apparatus may include the electrooptical device. This electronic apparatus can provide a bright display with high contrast because the aperture ratio of the pixel regions can be increased to enhance light availability.

A projector may include the electrooptical device. This projector can provide a bright display with high contrast because the aperture ratio of the pixel regions can be increased to enhance light availability.

DESCRIPTION OF EXEMPLARY EMBODIMENTS

First Embodiment

A first embodiment of the invention will now be described with reference to the drawings, where the individual components are illustrated on different scales if necessary for convenience of illustration. In this embodiment, a TFT active-matrix liquid crystal device including TFTs serving as pixel-switching elements will be described as an example.

Liquid Crystal Device

FIG. 1Ais a plan view of a liquid crystal device according to this embodiment.FIG. 1Bis a sectional view taken along line1B-1B ofFIG. 1A. InFIGS. 1A and 1B, a liquid crystal device100according to this embodiment includes a TFT array substrate (active matrix substrate)10and a counter substrate20which are stacked and bonded with a seal42having a substantially rectangular frame shape in plan view. A liquid crystal layer50is sealed in a space surrounded by the seal42. The liquid crystal layer50is formed of, for example, a liquid crystal material having positive dielectric anisotropy. The seal42has a liquid crystal inlet45(on the bottom side inFIG. 1A) filled with another seal44. A side partition43having a substantially rectangular frame shape in plan view is disposed inside the seal42to define a pixel display region11.

The pixel display region11includes pixel regions12arranged in a matrix, each defining one pixel, that is, the minimum display unit of the pixel display region11. The pixel display region11is surrounded by peripheral circuits, including a data-line drive circuit101and external circuit mounting terminals102disposed along one side of the TFT array substrate10(the bottom side inFIG. 1A) and scanning-line drive circuits104disposed along two sides of the TFT array substrate10adjacent to the bottom side thereof.

Wiring105is disposed on the other side of the TFT array substrate10(the top side inFIG. 1A) to connect the two scanning-line drive circuits104. Intersubstrate conductors106are disposed at the corners of the counter substrate20to electrically connect it to the TFT array substrate10. The liquid crystal device100according to this embodiment, which is a transmissive liquid crystal device, modulates light emitted from a light source (not shown) disposed on the TFT array substrate10side and outputs the light through the counter substrate20as image light.

InFIG. 1B, pixel electrodes9are arranged on the inner side of the TFT array substrate10(on the liquid crystal layer50side) and are covered with an alignment film16. The side partition43and a light-shielding film (not shown) are formed on the inner side of the counter substrate20and are covered with a common electrode21. Another alignment film22is formed over the common electrode21. A polarizer48is disposed on the outer side of the TFT array substrate10(facing away from the liquid crystal layer50).

FIG. 2is an equivalent circuit diagram of the liquid crystal device100. The pixel regions12are arranged in a matrix in the display region11. The pixel electrodes9are disposed in the individual pixel regions12. TFTs30are disposed beside the pixel electrodes9and are used as switching elements to control electrical connection to the pixel electrodes9. Data lines6aare connected to sources of the TFTs30and are supplied with image signals S1to Sn from, for example, data-line drive elements.

Scanning lines3aare connected to gates of the TFTs30and are supplied with pulsed scanning signals G1to C-m from, for example scanning-line drive elements at predetermined timings. The pixel electrodes9are connected to drains of the TFTs30.

When the scanning signals G1to Gm are supplied via the scanning lines3ato turn the TFTs30on for a predetermined period, the image signals S1to Sn are supplied to the pixel regions12at predetermined timings via the data lines6aand the pixel electrodes9.

The image signals S1to Sn are held in the pixel regions12by liquid crystal capacitors defined between the pixel electrodes9and the common electrode21for a predetermined period. Capacitors17are disposed between the pixel electrodes9and capacitor lines4bin parallel with the liquid crystal capacitors to prevent leakage of the image signals S1to Sn. Thus, the application of voltage signals to the liquid crystal changes the alignment of liquid crystal molecules, depending on the voltage levels of the signals, to modulate incident light emitted from a light source and generate image light.

The pixel structure of the liquid crystal device100on the TFT array substrate10side will be described with reference toFIGS. 3 to 6.FIG. 3is a plan view of the TFT array substrate10, on which components such as the data lines6a, the scanning lines3a, and the pixel electrodes9are formed. InFIG. 3, the vertical direction corresponds to the lateral direction of the TFT array substrate10, and the horizontal direction corresponds to the longitudinal direction of the TFT array substrate10.FIG. 4is a sectional view taken along line A1-A6ofFIG. 3.FIG. 5is a sectional view taken along line V-V ofFIG. 3.FIG. 6is a perspective view of a wiring structure shown inFIG. 3(the TFTs30are omitted).

InFIG. 3, the pixel electrodes9are disposed in the pixel regions12of the TFT array substrate10. The term “pixel regions” hereinafter refers to regions where the pixel electrodes9are disposed. The pixel electrodes9are formed in a rectangular shape so as to cover the pixel regions12in plan view. The pixel electrodes9are formed of a transparent conductive material such as indium tin oxide (ITO).

A light-shielding film (not shown) is disposed in regions (interpixel regions)14between the pixel electrodes9. Grooves10a(outlined by the broken lines) are disposed in a region where the light-shielding film is disposed. These grooves10aare formed in a grid pattern so as to extend along the interpixel regions14vertically and horizontally inFIG. 3. The vertical grooves10across the horizontal grooves10abetween the corners of the pixel regions12. The grooves15ahave slightly wider portions around the intersections thereof. In addition, the grooves10ahave a larger cross-sectional area parallel to the TFT array substrate10on the opening side of the grooves10athan on the bottom side thereof. That is, as shown inFIG. 4, the width L of the grooves10adecreases along the depth D of the grooves10afrom the top surface of the TFT array substrate10.

The grooves10ahave rectangular flat portions10bextending from the intersection regions thereof. That is, the flat portions10bprotrude from the grooves10ato the pixel regions12. As shown inFIG. 4, for example, the flat portions10bare positioned at a level that is one step lower than the top surface of the TFT array substrate10. In plan view, for example, these flat portions10boverlap the upper and lower left corners of the pixel regions12inFIG. 3.

The capacitors17, the data lines6a, and the scanning lines3aare disposed in the grooves10aand the flat portions10bthereof. The capacitors17are disposed in the wider portions of the grooves10aso as to extend in two orthogonal directions (in the vertical and horizontal directions inFIG. 3) along wall surfaces of the grooves10afrom the intersection regions thereof. InFIG. 4, for example, the capacitors17are mainly composed of capacitor electrodes17a, insulating films17c, and capacitor electrodes17bwhich are disclosed in the grooves10a. The capacitors17are formed on the wall surfaces of the grooves10a(including the bottom and side surfaces thereof) so that the capacitors17are U-shaped in cross section along the wall surfaces of the grooves10a.

The capacitor electrodes17aare disposed on the wall surfaces of the grooves10aand are formed of thin films of a metal such as titanium, molybdenum, chromium, tungsten, tantalum, or palladium. The insulating films17care disposed inside the capacitor electrodes17aand are formed of an insulating material such as SiO2. Although not illustrated inFIG. 4, the capacitor electrodes17aare connected to the capacitor lines4bshown inFIG. 2so that they are maintained at the same potential.

The capacitor electrodes17bare metal films disposed inside the insulating films17cso as to face the capacitor electrodes17aand are formed of the same material as the capacitor electrodes17a. The capacitor electrodes17bare U-shaped in cross section inside the grooves10aand have flat portions17dextending over the flat portions10bof the TFT array substrate10. These flat portions17dare disposed above the flat portions10bof the TFT array substrate10and are formed integrally with the capacitor electrodes17b. The capacitors17hold electrical charge between the capacitor electrodes17aand17bwith the insulating films17cdisposed therebetween.

InFIGS. 4 and 5, the data lines6aand the scanning lines3aare disposed inside the capacitors17with insulating films61disposed therebetween. The data lines6aare disposed in the vertical grooves10ainFIG. 3while the scanning lines3aare disposed in the horizontal grooves10ainFIG. 3. The data lines6across the scanning lines3ain the intersection regions of the grooves10ato define intersection regions.

The data lines6aare formed of a metal such as copper, aluminum, silver, gold, nickel, or chromium and extend along the vertical grooves10ainFIG. 3. The data lines6aare partially surrounded by the capacitors17around the intersections of the grooves10a.

The data lines6aare U-shaped in cross section inside the grooves10aand have flat portions6bextending over the flat portions10bof the TFT array substrate10so as to overlap the upper left corners of the pixel regions12inFIG. 3. That is, the flat portions6bprotrude from the regions of the grooves10acorresponding to the intersection regions of the data lines6aand the scanning lines3ato the pixel regions12. These flat portions6bare formed of the same metal as the data lines6aand are formed Integrally therewith.

The data lines6aare formed in such a shape that the width thereof (the length in a direction perpendicular to the longitudinal direction thereof) decreases gradually from the opening side of the grooves10ato the bottom side thereof. The data lines6asatisfy the following relationship:
1<(Lz/Lw)<50
wherein Lz is the depth of the data lines6a(the length from the top surface of the TFT array substrate10to the bottom of the data lines6a) and Lw is the width of the data lines6a. The top surfaces of the data lines6aand the flat portions6bthereof are flush with the top surface of the TFT array substrate10.

The scanning lines3aare formed of a metal such as copper, aluminum, silver, gold, nickel, or chromium and extend along the horizontal grooves10ainFIG. 3. The scanning lines3aare partially surrounded by the capacitors17around the intersections of the grooves10a.

The scanning lines3a, which are similar in cross-sectional shape to the data lines6a, are formed in such a shape that the width thereof (the length in a direction perpendicular to the longitudinal direction thereof) decreases gradually from the opening side of the grooves10ato the bottom side thereof. The scanning lines3asatisfy the same depth-width relationship as the data lines6a.

Gate electrodes3bare disposed in the intersection regions of the data lines6aand the scanning lines3aso as to extend along the scanning lines3a. These gate electrodes3bare positioned above the top surface of the TFT array substrate10(on the liquid crystal layer50side). Both ends of each of the gate electrodes3bare connected to the scanning lines3avia contact holes3c.

In the intersection regions of the data lines6aand the scanning lines3a, as clearly shown inFIG. 6, the data lines6aextend through the grooves10a, and the scanning lines3aextend across the data lines6avia the gate electrodes3b. The scanning lines3ahave substantially the same depth and width as the data lines6a.

The TFTs30have a lightly doped drain (LDD) structure and are mainly composed of semiconductor films62, insulating films67, and the gate electrodes3b. In plan view, the semiconductor films62overlap the intersection regions of the data lines6aand the scanning lines3a. InFIG. 3, the TFTs30are formed in the interpixel regions14in a rectangular shape that covers four adjacent corners of the pixel regions12and a region surrounded by the corners (intercorner region). In plan view, the corners of the semiconductor films62overlap the flat portions6bof the data lines6aand the flat portions17dof the capacitors17, and the centers of the semiconductor films62overlap the gate electrodes3b. InFIGS. 4 and 5, the gate electrodes3bare positioned above the semiconductor films62with the insulating films67disposed therebetween.

The semiconductor films62are formed of a semiconductor material such as silicon. The insulating films67are thin films disposed above the semiconductor films62(on the liquid crystal layer50side) and formed of, for example, silicon oxide (SiO2). The semiconductor films62each include a channel region1a, a heavily doped source region1b, a heavily doped drain region1c, a lightly doped source region1d, and a lightly doped drain region1e.

The channel regions1aoverlap the gate electrodes3bin plan view (in the centers of the semiconductor films62in the vertical direction inFIG. 3). The insulating films67are disposed between the channel regions1aand the gate electrodes3b. The channel regions1aserve as switches for allowing transmission of electrical signals from the data lines6a.

The heavily doped source regions1boverlap the flat portions6bof the data lines6ain plan view (on the bottom side of the semiconductor films62inFIG. 3). The heavily doped source regions1bare electrically connected to the flat portions6bof the data lines6avia source contact holes65.

The heavily doped drain regions1coverlap the flat portions17bof the capacitors17in plan view (on the top side of the semiconductor films62inFIG. 3). The heavily doped drain regions1care electrically connected to the pixel electrodes9via pixel contact holes63and to the flat portions17bof the capacitors17via capacitor contact holes64. The lightly doped source regions1dare disposed between the channel regions1aand the heavily doped source regions1b. The lightly doped drain regions1eare disposed between the channel regions1aand the heavily doped drain regions1c.

Method for Producing Liquid Crystal Device

An example of a process for producing the liquid crystal device100according to the first embodiment of the invention will be described. In this process, liquid crystal devices are simultaneously formed on a large mother substrate before they are separated by cutting.

The liquid crystal device100is formed by preparing, stacking, and cutting a mother counter substrate and a mother TFT array substrate. The mother TFT array substrate is a large substrate having rectangular display regions, each corresponding to the TFT array substrate10. The mother counter substrate is a large substrate having rectangular display regions, each corresponding to the counter substrate20.

Preparation of the mother TFT array substrate will be described. First, the grooves10aand the flat portions10bthereof are formed on a large substrate (TFT array substrate10) formed of a transparent material such as glass or quartz.

A detailed description will be given with reference toFIGS. 7 and 8. A resist layer70having a uniform thickness of about 3 μm is formed on the TFT array substrate10by, for example, spin coating or spray coating using a resist such as OFPR series (manufactured by Tokyo Ohka Kogyo Co., Ltd.) or AZ series (Clariant Ltd.). The resist layer70is covered with a mask71before the resist layer70is exposed for a predetermined period of time. The resist layer70is then covered with another mask72before the resist layer70is further exposed. The mask71has openings10acorresponding to the grooves10aof the TFT array substrate10while the mask72has openings72acorresponding to the flat portions10bof the TFT array substrate10. After the double exposure, the resist layer70is subjected to development to form grooves70aextending through the resist layer70and stepped grooves70b.

The TFT array substrate10is subjected to dry etching through the resist layer70having the grooves70aand70busing an etchant such as CF, C4F8, or CHF3. The etching is performed with the TFT array substrate10placed in a chamber having an evacuation system such as a pump. The pressure around the TFT array substrate10is reduced to 0.133 to hundreds of pascals. A mixture gas containing the etchant is supplied at about 30 sccm and is excited (into, for example, a radical state) by applying a high-frequency voltage (for example, about 13.56 MHz) to electrodes disposed in the chamber to etch the TFT array substrate10with the reactive gas. As shown inFIG. 8, the pattern of the resist layer70is transferred to the TFT array substrate10to form the grooves10aand the flat portions10bthereof.

The inventors have confirmed that the inclination angle of the wall surfaces of the grooves10adepends on the temperature of the TFT array substrate10. For example, the inclination angle is 99° at a substrate temperature of 156° C., 85° at a substrate temperature of 46° C., and 78° at a substrate temperature of 9° C. This is because fluorocarbons produced by reaction between carbon and fluorine are deposited on the wall surfaces of the grooves10aand protect the wall surfaces. Hence, the amount of fluorocarbons deposited may be adjusted by changing the temperature of the TFT array substrate10so as to incline the wall surfaces of the grooves10ato a desired angle.

Formation of the capacitors17on the TFT array substrate10having the grooves10aand the flat portions10bthereof will be described with reference toFIGS. 9 to 13. First, a metal film74is formed on the TFT array substrate10so as to cover the top surface, grooves13a, and flat portions10bthereof. The metal film74is formed of, for example, titanium, molybdenum, chromium, tungsten, tantalum, or palladium. Referring toFIG. 9, a protective layer75is formed on portions of the metal film74corresponding to the grooves10aand the flat portions11bthereof.

The metal film74is etched with the protective layer75disposed thereon to remove unprotected portions, thus forming the capacitor electrodes17ain the grooves1aand on the flat portions10thereof. This etching may be performed by the same method described above or wet etching.

Referring toFIG. 10, the insulating film17cis formed on the top surface of the TFT array substrate10and the capacitor electrodes17a. Referring toFIG. 11, a metal film77is formed on the insulating film17c. This metal film77is formed of the same material as the capacitor electrodes17a, for example, titanium, molybdenum, chromium, tungsten, tantalum, or palladium. After a protective layer78is formed above the grooves10aand the flat portions10bthereof, the metal film77is etched to form the capacitor electrodes17bin the grooves11aand form the flat portions17dof the capacitor electrodes17babove the flat portions10bof the TFT array substrate10.

Referring toFIG. 12, the insulating film61is formed on the top surface of the TFT array substrate1uand the capacitor electrodes17b. Referring to13, the data lines6aare formed in the grooves10acovered with the insulating film61. The data lines6aare formed of a metal such as copper, aluminum, silver, gold, nickel or chromium. The scanning lines3aare similarly formed. Subsequently, unnecessary portions are removed from the TFT array substrate10, and the substrate10is planarized.

After the grooves10a, the flat portions10bthereof, the capacitors17, the data lines6a, and the scanning lines3aare formed on the TFT array substrate10, the contact holes64and65are formed, and the semiconductor films62are formed so as to be connected to the contact holes64and65. The insulating films67are then formed on the semiconductor films62, and the gate electrodes3bare formed on the insulating films67so as to be connected to the scanning lines3a. The contact holes63are formed in the insulating films67, and the pixel electrodes9are formed so as to be connected to the contact holes63. The alignment film16is formed on the top surface of the TFT array substrate10, and the seal42is formed on the alignment film16.

Preparation of the mother counter substrate will be briefly described. The mother counter substrate is a large substrate, similar to the mother TFT array substrate, formed of a transparent material such as glass or quartz. The common electrode21is formed in display regions of the mother counter substrate, and the alignment film22is formed on the common electrode21.

The mother TFT array substrate and the mother counter substrate are stacked and bonded with the seal42disposed therebetween. The seal42is then cured by ultraviolet (UNT) exposure.

Scribe lines are formed on the mother TFT array substrate and the mother counter substrate before they are cut along the scribe lines to separate individual liquid crystal panels. These panels are washed, and a liquid crystal is sealed into the panels. Flexible circuit boards, for example, are mounted on the panels with anisotropic conductive films (ACFs) disposed therebetween. The liquid crystal device100is thus completed.

According to this embodiment, the grooves10aare disposed in the top surface of the TFT array substrate10so as to extend along the interpixel regions14. The capacitors17, the data lines6a, and the scanning lines3acan be partially disposed in the grooves10aso that they occupy smaller areas in the interpixel regions14. Accordingly, the size of the liquid crystal device100can be reduced, and the area of the pixel regions12can be increased relative to that of the interpixel regions14. Thus, this structure contributes to size reduction and higher definition and can also significantly increase the aperture ratio of the pixel regions12.

In addition, the liquid crystal device100has increased light resistance because the areas of the capacitors17, the data lines6a, and the scanning lines3ain the interpixel regions14can be reduced to inhibit light reflection/absorption leading to an increase in the temperature of the liquid crystal device100. Furthermore, the data lines6aand the scanning lines3acan be extended along the depth of the grooves10ato increase the cross-sectional area of the data lines6aand the scanning lines3a. This allows for a reduction in the resistance of the data lines6aand the scanning lines3afor efficient signal transmission.

In this embodiment, additionally, the TFTs30are disposed between the corners of the pixel regions12so as to overlap them in plan view. Referring toFIG. 14, a voltage can be stably applied between the pixel electrodes9and the common electrode21to reliably align the light crystal in the centers of the pixel regions12. Central light L1passing through the centers of the pixel regions12therefore reliably undergoes a predetermined amount of phase shift (substantially 90°). The central light L1can thus be transmitted through a polarizer with high transmittance to provide clear black or white display and high contrast.

On the other hand, the voltage is less stably applied in the peripheries of the pixel regions12, including the corners of the pixel regions12, than in the centers of the pixel regions12, and thus the liquid crystal is less reliably aligned in the peripheries of the pixel regions12. Light passing therethrough can therefore fail to reach the predetermined amount of phase shift. For example, peripheral light L2passing through the peripheries of the pixel regions12undergoes a phase shift of only about 60°, and peripheral light L3passing through the corners of the pixel regions12undergoes a phase shift of only about 45°. The peripheral light L2and the peripheral light L3are thus transmitted through the polarizer with lower transmittance than the central light L1. This results in unclear black or white display and low contrast.

In this embodiment, the intensity of the central light L1can be increased because the total aperture ratio of the pixel regions12is increased relative to that of pixel regions of a known liquid crystal device. Accordingly, the intensity of the central light L1, which contributes to higher contrast, is increased while the peripheral light L2, which contributes to lower contrast, is blocked by the TFTs30. The liquid crystal device100thus allows high-contrast light to pass through the polarizer with higher transmittance than the known liquid crystal device to provide higher contrast.

In this embodiment, additionally, the data lines6aand the scanning lines3asatisfy the depth-width relationship described above, namely, 1<(Lz/Lw)<50, so that they can have a cross-sectional area sufficient to supply the current required for driving the TFTs30even for smaller line widths.

In this embodiment, additionally, the capacitors17overlap the data lines6a(scanning lines3a) in plan view. The capacitors17and the data lines6a(scanning lines3a, can thus be stacked in layers to facilitate the preparation of the TFT array substrate10.

Second Embodiment

A second embodiment of the invention will be described with reference to the drawings, where the individual components are illustrated on different scales if necessary for convenience of illustration, as in the first embodiment. This embodiment is different from the first embodiment in that data lines are disposed inside grooves while scanning lines are disposed outside the grooves. The description below will focus on this point.

FIG. 15is a plan view of a TFT array substrate210of a liquid crystal device200according to this embodiment. InFIG. 15, as in the first embodiment, the vertical direction corresponds to the lateral direction of the TFT array substrate210, and the horizontal direction corresponds to the longitudinal direction of the TFT array substrate210.FIG. 16is a sectional view taken along line XVI-XVI ofFIG. 15.

InFIG. 15, a light-shielding film (not shown) is disposed in Interpixel regions214. Grooves210a(outlined by the broken lines) are disposed in a region where the light-shielding film is disposed. These grooves210aare formed in a stripe pattern so as to extend along the interpixel regions214vertically inFIG. 15. In this embodiment, only the vertical grooves210aare formed, and no horizontal grooves are formed. InFIG. 16, additionally, the grooves210ahave a uniform width over the depth thereof from the opening side to the bottom side. The grooves210ahave flat portions210boverlapping the lower right corners of pixel regions212inFIG. 15. The flat portions210bprotrude from the grooves210ato the left adjacent pixel regions212.

Capacitors217, data lines206a, scanning lines203a, and TFTs230are disposed in the interpixel regions214. Among them, the data lines206aand the capacitors217are disposed in the grooves210a. Specifically, the capacitors17are disposed in wider portions of the grooves210aso as to extend along wall surfaces thereof. InFIG. 16, for example, the capacitors217are mainly composed of capacitor electrodes217a, insulating films217c, and capacitor electrodes217bwhich are disposed in the grooves210a. The capacitor electrodes217bhave flat portions217dextending over the flat portions210bof the TFT array substrate210. The capacitors217are formed on the wall surfaces of the grooves210aso that the capacitors217are box-shaped in cross section along the wall surfaces of the grooves210a.

The data lines206aare surrounded by the capacitors217and have a uniform width over the depth thereof. The data lines206asatisfy the following relationship:
0.5<(Lz/Lw)<15
wherein Lz is the depth of the data lines206aand Lw is the width of the data lines206a. The top surfaces of the data lines206aare flush with the top surface of the TFT array substrate210.

The scanning lines203aextend horizontally inFIG. 15along the interpixel regions214. Portions of the scanning lines3awhich cross the data lines206aserve as gate electrodes203b. The scanning lines203aare positioned above the top surface of the TFT array substrate10(on the liquid crystal layer250side). In this embodiment, there is no difference between the heights of the scanning lines203aand the gate electrodes203bfrom the top surface of the TFT array substrate210. The gate electrodes203bare composed of portions of the scanning lines3awhich overlap the TFTs230in plan view; that is, the gate electrodes3bconstitute part of the scanning lines3a.

The TFTs230, as in the first embodiment, have an LDD structure and are mainly composed of semiconductor films262, insulating films267, and the gate electrodes203b. InFIG. 15, the semiconductor films262and the insulating films267are formed in an inversed L shape in regions including the regions between the corners of the pixel regions212so as to overlap the lower right corners of the pixel regions212, the data lines6a, and the flat portions217dof the capacitors217in plan view. The centers of the semiconductor films262overlap the gate electrodes203bin plan view. InFIG. 16, the gate electrodes203bare positioned above the semiconductor films262with the insulating films267disposed therebetween.

The semiconductor films262each include a channel region201a, a heavily doped source region201b, a heavily doped drain region201c, a lightly doped source region201d, and a lightly doped drain region201e. The channel regions201aoverlap the gate electrodes203bin plan view (in the centers of the semiconductor films262in the vertical direction inFIG. 15). The insulating films267are disposed between the channel regions201aand the gate electrodes203b.

The heavily doped source regions201boverlap the data lines206ain plan view (on the bottom side of the semiconductor films262inFIG. 15). The heavily doped source regions201bare directly connected to the data lines206avia source contact holes265. Unlike the first embodiment, the heavily doped source regions201bdo not overlap the pixel regions212in plan view, and the aperture ratio of the pixel regions212can be increased accordingly.

The heavily doped drain regions201coverlap the flat portions217bof the capacitors217in plan view (on the top side of the semiconductor films262inFIG. 15). The heavily doped drain regions201care electrically connected to the pixel electrodes209via pixel contact holes263and to the flat portions217bof the capacitors217via capacitor contact holes264. The lightly doped source regions201dare disposed between the channel regions201aand the heavily doped source regions201b. The lightly doped drain regions201eare disposed between the channel regions201aand the heavily doped drain regions201c.

This embodiment provides the same advantages as the first embodiment even if only the grooves210aextending in the lateral direction of the TFT array substrate210are formed thereon and no grooves extending in the longitudinal direction are formed. According to this embodiment, additionally, the gate electrodes3bcan be formed as part of the scanning lines3ato facilitate formation of the gate electrodes3b.

In this embodiment, additionally, the heavily doped source regions201bof the semiconductor films262overlap the data lines206ain plan view and are directly connected thereto. This structure can eliminate the need for providing connecting portions between the heavily doped source regions201band the data lines206ato increase the area of the pixel regions212and thus the aperture ratio thereof.

In this embodiment, additionally, the data lines206asatisfy the depth-width relationship described above, namely, 0.5<(Lz/Lw)<15, so that they can have a cross-sectional area sufficient to supply the current required for driving the TFTs230even for smaller line widths.

Third Embodiment

A third embodiment of the invention will be described with reference to the drawings, where the Individual components are illustrated on different scales if necessary for convenience of illustration, as in the first embodiment. This embodiment is different from the first embodiment in the structure of semiconductor films of TFTs. The description below will focus on this point.

FIG. 17is a plan view of a TFT array substrate310of a liquid crystal device300according to this embodiment. InFIG. 17, as in the first embodiment, the vertical direction corresponds to the lateral direction of the TFT array substrate310, and the horizontal direction corresponds to the longitudinal direction of the TFT array substrate310.FIG. 18is a sectional view taken along line XVIII-XVIII ofFIG. 17.FIG. 19is a sectional view taken along line XIX-XIX ofFIG. 18.

InFIG. 17, a light-shielding film315is disposed in interpixel regions314. Grooves310aare disposed in a region where the light-shielding film315is disposed (the light-shielding film315is partially omitted for convenience of illustration) The width of the light-shielding film315in the vertical direction inFIG. 17is substantially the same as that of the light-shielding film315in the horizontal direction.

The grooves310aare formed in a grid pattern so as to extend along the interpixel regions314vertically and horizontally inFIG. 17. The vertical grooves310across the horizontal grooves310abetween the corners of pixel regions312. The width of the grooves310adecreases along the depth thereof at a constant rate.

Capacitors317, data lines306a, scanning lines303a, and TFTs330are disposed in the interpixel regions314. Among them, the data lines306a, the scanning lines303a, and the capacitors317are disposed in the grooves310a. The data lines306across the scanning lines303aat the intersections of the grooves310ato define intersection regions. The capacitors17are disposed in wider portions of the grooves310aso as to extend along wall surfaces thereof. InFIG. 18, for example, the capacitors317are mainly composed of capacitor electrodes317a, insulating films317c, and capacitor electrodes317bwhich are disposed in the grooves310a. The capacitor electrodes317bhave flat portions317dextending over the flat portions310bof the TFT array substrate310. The capacitors317are formed along the wall surfaces of the grooves310a.

The data lines306aextend vertically inFIG. 17along the vertical grooves310a. As shown inFIGS. 18 and 19, the data lines306aare formed along the cross-sectional shape of the grooves310aso that the width of the data lines306adecreases at a constant rate along the depth from the top surface of the TFT array substrate310(trapezoidal4nFIG. 18). In addition, the data lines306asatisfy the following relationship:
0.5<(Lz/Lw)<15
wherein Lz is the depth of the data lines306aand Lw is the width of the data lines306a. The data lines306ahave flat portions306bextending from the regions of the grooves310acorresponding to the intersection regions of the data lines306aand the scanning lines303a.

The scanning lines303aextend horizontally inFIG. 17along the horizontal grooves310a. The scanning lines303aare formed in the same cross-sectional shape as the data lines306a, that is, formed along the cross-sectional shape of the grooves310aso that the width of the scanning lines303adecreases at a constant rate along the depth from the top surface of the TFT array substrate310(trapezoidal inFIG. 18). The scanning lines303ahave substantially the same depth and width as the data lines300aand thus satisfy the same depth-width relationship as the data lines306a.

Gate electrodes303bare disposed in the intersection regions of the data lines306aand the scanning lines303aso as to extend along the scanning lines303a. These gate electrodes303bare positioned above the top surface of the TFT array substrate310(on the liquid crystal layer340side). Both ends of each of the gate electrodes303bare connected to the scanning lines303avia, for example, contact holes. The top surfaces of the data lines306a, the flat portions306bthereof, and the scanning lines303aare flush with the top surface of the TFT array substrate310.

The TFTs330are mainly composed of semiconductor films342, insulating films347, and the gate electrodes303b. In plan view, the semiconductor films342and the insulating films347overlap the intersection regions of the data lines306aand the scanning lines303aand are formed in an octagonal shape that covers regions surrounded by the corners of the pixel regions312.

In plan view, specifically, the semiconductor films342are formed so as to overlap the corners of the pixel regions312in triangular regions and also cover the flat portions306bof the data lines306aand the flat portions317dof the capacitors317. The centers of the semiconductor films342overlap the gate electrodes303bin plan view. The light-shielding film315includes light-shielding portions covering the semiconductor films342. These light-shielding portions satisfy the following relationship:
W1×0.8>W2
wherein W1is the maximum width of the light-shielding portions and W2is the width of the data lines306aand the scanning lines303a.

The semiconductor films342each include a channel region301a, a heavily doped source region301b, a heavily doped drain region301c, a lightly doped source region301d, and a lightly doped drain region301e. The channel regions301aoverlap the gate electrodes303bin plan view. The heavily doped source regions301boverlap the flat portions306bof the data lines306ain plan view and are connected thereto via source contact holes345. The heavily doped drain regions301coverlap the flat portions317bof the capacitors317in plan view and are connected to the pixel electrodes309via pixel contact holes343and to the flat portions317bof the capacitors317via capacitor contact holes344. The lightly doped source regions301dare disposed between the channel regions301aand the heavily doped source regions301b. The lightly doped drain regions301eare disposed between the channel regions301aand the heavily doped drain regions301c.

In this embodiment, the semiconductor films342are formed in an octagonal shape so that the area where the semiconductor films342overlap the pixel regions212in plan view can be minimized with the maximum width W1of the light-shielding portions being smaller than the width W2of the data lines306aand the scanning lines303a. This allows for a further increase in the aperture ratio of the pixel regions312.

In this embodiment, additionally, the data lines306aand the scanning lines303asatisfy the depth-width relationship described above, namely, 0.5<(Lz/Lw)<15, so that they can have a cross-sectional area sufficient to supply the current required for driving the TFTs330even for smaller line widths.

In this embodiment, additionally, the grooves310a, the light-shielding film315, the data lines306a, and the scanning lines303aare formed so as to satisfy the width relationship described above, namely, W1×0.8>W2. This allows for a reduction in the space occupied by the data lines306a, the scanning lines303a, and the capacitors317to increase the aperture ratio of the pixel regions312.

Fourth Embodiment

A fourth embodiment of the invention will be described with reference to the drawings, where the individual components are illustrated on different scales if necessary for convenience of illustration, as in the first embodiment. This embodiment is different from the first embodiment in the structure of semiconductor films of TFTs. The description below will focus on this point.

FIG. 20is a plan view of a TFT array substrate410of a liquid crystal device400according to this embodiment. InFIG. 20, as in the first embodiment, the vertical direction corresponds to the lateral direction of the TFT array substrate410, and the horizontal direction corresponds to the longitudinal direction of the TFT array substrate410.FIG. 21is a sectional view taken along line F1-F7ofFIG. 20.

InFIG. 20, a light-shielding film (not shown) is disposed in Interpixel regions414. Grooves410aare disposed in a region where the light-shielding film is disposed. The grooves410aare formed in a grid pattern so as to extend along the interpixel regions414vertically and horizontally inFIG. 20. The grooves410ahave rectangular flat portions410bprotruding from intersection regions thereof. In plan view, for example, these flat portions410boverlap the lower left corners of pixel regions412inFIG. 20.

The data lines406aare disposed in the vertical grooves410ainFIG. 20and are formed in substantially the same cross-sectional shape as those in the first embodiment. The data lines406asatisfy the same depth-width relationship as in the first embodiment. Scanning lines403aare disposed in the interpixel regions414so as to extend horizontally inFIG. 20. Gate electrodes403bare disposed in intersection regions of the data lines406aand the scanning lines403a. The scanning lines403ahave substantially the same depth and width as the data lines406a.

InFIG. 21, the gate electrodes403bare positioned above the top surface of the TFT array substrate410(on the liquid crystal layer450side). Both ends of each of the gate electrodes403bare connected to the scanning lines403avia contact holes403c. The top surfaces of the data lines406aand the scanning lines403aare flush with the top surface of the TFT array substrate410.

Capacitors417are mainly composed of capacitor electrodes417a, insulating films417c, and capacitor electrodes417b, and flat portions417d. The materials, planar structure, and cross-sectional structure of the capacitors417are substantially the same as those in the first embodiment, and thus no description will be given here.

TFTs430are mainly composed of semiconductor films462, insulating films467, and the gate electrodes403b. InFIG. 20, the semiconductor films462are formed in a box shape so as to overlap regions surrounded by the corners of pixel regions412. That is, the semiconductor films462are formed in a box shape having an opening on the upper side ofFIG. 20.

In plan view, the semiconductor films462overlap flat portions406bof the data lines406aand the flat portions417dof the capacitors417, and the centers of the semiconductor films462overlap the gate electrodes403b. InFIG. 21, the gate electrodes403bare positioned above the semiconductor films462with the insulating films467disposed therebetween.

The semiconductor films462each include a channel region401a, a heavily doped source region401b, a heavily doped drain region401c, a lightly doped source region401d, and a lightly doped drain region401e. The channel regions401aoverlap the gate electrodes403bin plan view. The heavily doped source regions401boverlap the data lines406ain plan view and are directly connected thereto via source contact holes465. The heavily doped drain regions401coverlap the flat portions417bof the capacitors417in plan view and are electrically connected to the pixel electrodes409via pixel contact holes463and to the flat portions417bof the capacitors417via capacitor contact holes464. The lightly doped source regions401dare disposed between the channel regions401aand the heavily doped source regions401b. The lightly doped drain regions401eare disposed between the channel regions401aand the heavily doped drain regions401c.

In this embodiment, the semiconductor films462are formed in a box shape so that the area where the semiconductor films462overlap the pixel regions412in plan view can be minimized to further increase the aperture ratio of the pixel regions412. In this embodiment, additionally, the heavily doped source regions401bof the semiconductor films462overlap the data lines406ain plan view and are directly connected thereto. This structure can eliminate the need for providing connecting portions between the heavily doped source regions401band the data lines406ato increase the area of the pixel regions412and thus the aperture ratio thereof.

Fifth Embodiment

A fifth embodiment of the invention will be described with reference to the drawings, where the individual components are illustrated on different scales if necessary for convenience of illustration, as in the first embodiment. This embodiment is different from the first embodiment in that a microlens array is provided. The description below will focus on this point.

FIG. 22is a sectional view of a liquid crystal device500according to this embodiment.FIG. 23is a plan view of pixel regions of the liquid crystal device500. InFIG. 22, the liquid crystal device500includes a TFT array substrate510and a counter substrate520which are stacked and bonded with a liquid crystal layer550sealed therebetween using a seal (not shown). A pixel display region of the liquid crystal device500includes pixel regions512arranged in a matrix.

Grooves510aare disposed in interpixel regions of an inner surface of the TFT array substrate510(on the liquid crystal layer550side). Data lines506aand scanning lines503a, for example, are disposed in the grooves510aand are connected to TFTs530. InFIG. 23, the TFTs530overlap the corners of the pixel regions512in plan view. For example, the structures of the grooves510aplan data lines506a, the scanning lines503a, and the TFTs530are substantially the same as those in any of the first to fourth embodiments. Pixel electrodes509are arranged in the pixel regions512of the inner surface of the TFT array substrate510. A light-shielding film515is disposed in the interpixel regions. For example, the light-shielding film515is positioned closer to the liquid crystal layer550than the TFTs530to prevent light from the counter substrate520from impinging on the TFTs530. An alignment film516is disposed over the pixel electrodes509and the light-shielding film515.

A microlens array540is disposed on the inner surface of the counter substrate520. The microlens array540includes lens portions540aarranged in the pixel regions512. The lens portions540aare separated from the pixel electrodes509by a distance of d, for example, 15 μm. A common electrode521is disposed over the entire inner surface of the microlens array540, and another alignment film522is disposed over the common electrode521.FIG. 22shows one of the pixel regions512(pixel electrodes509).

Light entering the liquid crystal device500will be described. InFIG. 22, for example, light L4entering substantially the center of the pixel region512perpendicularly to the surface of the counter substrate520is collected into substantially the center of the pixel electrode509by the lens portion540a. Light L5entering the same region at a certain angle θ with respect to the surface of the counter substrate520is collected into a region separated from the center of the pixel electrode509by a distance of r by the lens portion540a. InFIG. 23, accordingly, the lens portion540acollects light into a circular region centered at the center of the pixel electrode509and having a radius of r. If the angle θ is 12°, for example, the radius r is about 3.2 μm. The pixel region512, which is square inFIG. 23, may also be rectangular, and the region where light is collected, which is circular inFIG. 23, may also be elliptical.

FIG. 24Ashows the intensity distribution of the light collected in the circular region.FIG. 24Bis a graph taken along line XXIVB-XXIVB ofFIG. 24A. According toFIGS. 24A and 24B, the intensity of the light is highest in the center of the circular region, that is, in the center of the pixel region512, and decreases toward the periphery of the pixel region512, and little incident light is collected onto the corners of the pixel region512.

In this embodiment, the TFTs530are disposed so as to overlap the corners of the pixel regions512in plan view. Accordingly, the interpixel regions can be reduced to increase the aperture ratio of the pixel regions512. Thus, the area where light enters the pixel regions512can be increased to allow more light with high intensity to enter the pixel regions512. The use of microlenses for the pixel regions512with the increased aperture ratio can produce a synergistic effect of increasing light availability.

Light collected on the corners of the pixel regions512has low intensity even if the microlens array540is provided in the liquid crystal device500. The TFTs530block only the low-intensity light collected on the corners of the pixel regions512, and thus the pixel regions512exhibit little loss of light in total. Accordingly, the use of the microlens array540increases the light availability.

Sixth Embodiment

A sixth embodiment of the invention will be described with reference to the drawings, where the individual components are illustrated on different scales if necessary for convenience of illustration, as in the first embodiment. This embodiment is different from the first embodiment in that wiring (data lines and scanning lines) and capacitors are disposed in different grooves. The description below will focus on this point, and no description will be given to the same components as in the first embodiment.FIG. 25is a sectional view of a TFT array substrate610of a liquid crystal device600according to this embodiment, corresponding to a cross section taken along line G-G ofFIG. 3.

A light-shielding film (not shown) is disposed in interpixel regions614of the TFT array substrate610. Grooves611aand610care disposed in a region where the light-shielding film is disposed. The grooves610aand610chave a uniform width over the depth from the top surface of the TFT array substrate610and extend in parallel along the interpixel regions614. The grooves610aand610chave substantially the same depth. Flat portions610bprotrude from the grooves610cso as to overlap pixel regions612in plan view.

Capacitors617, data lines606a, scanning lines603a, and TFTs630are disposed in the interpixel regions614. As in the first embodiment, the data lines606aand the scanning lines603aare formed in the grooves610aalong the cross-sectional shape thereof so as to have a uniform width over the depth from the top surface of the TFT array substrate610. As in the second embodiment, the data lines606aand the scanning lines603asatisfy the following relationship:
0.5<(Lz/Lw)<15
wherein Lz is the depth of the data lines606aand the scanning lines603aand Lw is the width of the data lines606aand the scanning lines603a.

The capacitors617are disposed in the grooves610cand are mainly composed of capacitor electrodes617a, capacitor electrodes617b, and insulating films617c. The capacitor electrodes617aare formed along wall surfaces of the grooves610a. The insulating films617care formed on the capacitor electrodes617a. The capacitor electrodes617bare disposed opposite the capacitor electrodes617awith the insulating films617cdisposed therebetween. The capacitor electrodes617bhave flat portions617dextending over the flat portions610bof the TFT array substrate610.

In this embodiment, the wiring (the data lines606aand the scanning lines603a) and the capacitors617are disposed in the different grooves610aand610c, respectively, so that they can be separated from each other to prevent parasitic capacitance from occurring therebetween. This embodiment can also simplify the structures of the grooves610aand610cto facilitate production of the liquid crystal device500.

Seventh Embodiment

A seventh embodiment of the invention will be described with reference to the drawings, where the individual components are illustrated on different scales if necessary for convenience of illustration, as in the first embodiment. In this embodiment, no description will be given to the same components as in the first embodiment.

FIG. 26is a sectional view of a TFT array substrate710of a liquid crystal device700according to this embodiment, corresponding to the cross section taken along line G-G ofFIG. 3. The seventh embodiment is different from the sixth embodiment in the shape of grooves, although wiring (data lines and scanning lines) and capacitors are disposed in different grooves as in the sixth embodiment.

Grooves710aand710care disposed in interpixel regions of the TFT array substrate710. As in the first embodiment, the grooves710aare formed such that the width thereof decreases gradually along the depth from the top surface of the TFT array substrate710. The grooves710care formed such that the centers thereof (in the horizontal direction inFIG. 26) are constricted toward the top surface of the TFT array substrate710.

Data lines706aand scanning lines703aare disposed in the grooves710a. The data lines706aand the scanning lines703aare formed along wall surfaces of the grooves710asuch that the width thereof decreases gradually along the depth from the top surface of the TFT array substrate710. As in the first embodiment, the data lines706aand the scanning lines703asatisfy the following relationship:
1<(Lz/Lw)<50
wherein Lz is the depth of the data lines706aand the scanning a lines703aand Lw is the width of the data lines706aand the scanning lines703a.

Capacitors717are disposed in the grooves710c. Capacitor electrodes717aare outer electrodes disposed along the bottom and side surfaces of the grooves710c. The centers of the capacitor electrodes717a(in the horizontal direction inFIG. 26) are constricted toward the top surface of the TFT array substrate710. Capacitor electrodes717bare surrounded by the capacitor electrodes717awith insulating films717cdisposed therebetween.

In this embodiment, the centers of the grooves710care constricted toward the top surface of the TFT array substrate710, and thus the centers of the capacitor electrodes717a, which are disposed in the grooves710a, are similarly constricted toward the top surface of the TFT array substrate710. This structure can increase the surface area of the capacitor electrodes717ato increase the capacitance of the capacitors717.

Eighth Embodiment

An eighth embodiment of the invention will be described with reference to the drawings, where the individual components are illustrated on different scales if necessary for convenience of illustration, as in the first embodiment. In this embodiment, no description will be given to the same components as in the first embodiment.FIG. 27is a sectional view of a TFT array substrate810of a liquid crystal device800according to this embodiment, corresponding to the cross section taken along line G-G ofFIG. 3.

This embodiment is different from the first embodiment in the shape of grooves. Grooves810aare disposed in interpixel regions of the TFT array substrate810. The depth of the grooves810aincreases stepwise toward the centers thereof in the horizontal direction inFIG. 27.

Data lines806a, scanning lines803a, and capacitors817are disposed in the grooves810a. The data lines806aand the scanning lines803aare formed along wall surfaces of the grooves810aso that they are stepped toward the centers thereof in the horizontal direction inFIG. 27. The capacitors817are mainly composed of capacitor electrodes817a, insulating films817c, and capacitor electrodes817bwhich are stepped along the shape of the grooves810a.

In this embodiment, the depth of the grooves810aincreases stepwise toward the centers thereof in the horizontal direction inFIG. 27, and thus the capacitor electrodes817aand817b, which are disposed in the grooves810a, are similarly stepped. This structure can increase the surface area of the capacitor electrodes817ato increase the capacitance of the capacitors817. In addition, the grooves810aare stepped so that the capacitor electrodes817aand817b, the data lines806a, and the scanning lines803acan easily be formed in the grooves810a.

Ninth Embodiment

A ninth embodiment of the invention will be described with reference to the drawings, where the individual components are illustrated on different scales if necessary for convenience of illustration, as in the first embodiment. In this embodiment, no description will be given to the same components as in the first embodiment.FIG. 28is a sectional view of a TFT array substrate910of a liquid crystal device900according to this embodiment, corresponding to the cross section taken along line G-G ofFIG. 3.

This embodiment is different from the first embodiment in the shape of grooves. Grooves910aare disposed in interpixel regions of the TFT array substrate910. The depth of the grooves910aincreases toward the centers thereof in the horizontal direction inFIG. 28so that they are arc-shaped. Data lines906a, scanning lines903a, and capacitors917are disposed in the grooves910a. The data lines906aand the scanning lines903aare formed in a semicircular shape along wall surfaces of the grooves910a. The data lines906aand the scanning lines903asatisfy the following relationship:
0.5<(Lz/Lw)<15
wherein Lz is the depth of the data lines906aand the scanning lines903aand Lw is the width of the data lines906aand the scanning lines903a. The capacitors917are mainly composed of capacitor electrodes917a, insulating films917c, and capacitor electrodes917bwhich are arc-shaped along the wall surfaces of the grooves910a.

In this embodiment, the depth of the grooves910aincreases toward the centers thereof in the horizontal direction inFIG. 28so that they are arc-shaped, and thus the capacitor electrodes917aand917b, which are disposed in the grooves910a, are similarly arc-shaped. This structure can reflect part of external light traveling toward the capacitor electrodes917ain a direction normal to the top surface of the TFT array substrate910to increase light availability.

Tenth Embodiment

A tenth embodiment of the invention will be described with reference to the drawings, where the individual components are illustrated on different scales if necessary for convenience of illustration, as in the first embodiment. In this embodiment, no description will be given to the same components as in the first embodiment.FIG. 29is a sectional view of a TFT array substrate1010of a liquid crystal device1000according to this embodiment, corresponding to the cross section taken along line G-G ofFIG. 3.

This embodiment is different from the first embodiment in that pairs of capacitors are provided. Grooves1010ahaving flat portions1010bare disposed in interpixel regions of the TFT array substrate1010. The width of the grooves1010adecreases at a constant rate along the depth thereof from the top surface of the TFT array substrate1010. Data lines1006aand scanning lines1003aare disposed in the grooves1010a. The data lines1006aand the scanning lines1003aare formed along wall surfaces of the grooves1010aso that the width thereof decreases at a constant rate along the depth from the top surface of the TFT array substrate1010.

Inner capacitors1017and outer capacitors1027are disposed in layers in the grooves1010a.

The capacitors1017and1027have flat portions1017dand1027d, respectively, which are disposed over the flat portions1010bof the grooves1010a. The flat portions1017dand1027dare connected to heavily doped drain regions of TFTs1030via contact holes1065aand1065b, respectively. According to this embodiment, the capacitors1017and1027are disposed in the grooves1010aso as to form a double-layer structure that can provide higher capacitance.

Projector

An example of a projector including the liquid crystal device according to any of the embodiments described above as an optical modulator will be described.FIG. 30is a schematic diagram illustrating the inner structure of a projector1102as an example of a projection display. This projector1102mainly includes a light source1107, fly-eye lenses1103and1109, dichroic mirrors1110and1111, reflective mirrors1112,1113, and1114, liquid crystal light valves1115,1116, and1117, a cross dichroic prism1118, and a protection lens1119. This projector1102is, for example, a color liquid crystal projector including transmissive liquid crystal light valves for red (R), green (G), and blue (B) colors,

The light source1107includes a lamp1107athat emits, for example, white light (such as a high-pressure mercury lamp) and a reflector1107bthat reflects the light emitted from the lamp1107a. The fly-eye lenses1108and1109are optical components that convert the illuminance distribution of the light into a uniform distribution. The fly-eye lens1108is disposed on the light source1107side to form secondary optical images, and the fly-eye lens1109is disposed on the screen side to superimpose the secondary optical images.

The dichroic mirror1110is an optical component that transmits a red light component LRcontained in the write light emitted from the light source1107and reflects a green light component LGand a blue light component LBcontained in the white light. The dichroic mirror1111is an optical component that reflects the green light component LGand transmits the blue light component LB.

The liquid crystal light valves1115,1116, and1117are optical modulators that modulate the red light component LR, the green light component LG, and the blue light component LB, respectively, according to predetermined image signals. In this embodiment, any of the liquid crystal devices100to1000may be used as the liquid crystal light valves1115,1116, and1117.

The cross dichroic prism1118is an optical component including four right-angle prisms that are bonded to each other. Dielectric multilayer films1118aand1118bare formed on inner surfaces of the cross dichroic prism1118so as to cross each other. The dielectric multilayer film1118areflects the red light component LR, and the dielectric multilayer film1118breflects the blue light component LB. These dielectric multilayer films1118aand1118bcombine the red light component LR, the green light component LG, and the blue light component LBinto color image light (video light). The projection lens1119is an optical component that projects the video light onto a screen1103.

The operation of the projector1102will be described. When the projector1102is operated, the lamp1107aemits white light, and a collimator lens (not shown) collimates the white light and its reflection by the reflector1107b. The fly-eye lenses1108and1109convert the illuminance distribution of the collimated light into a uniform distribution.

The light then reaches the dichroic mirrors1110and1111, which separate the light into the red light component LR, the green light component LG, and the blue light component LB. The dichroic mirrors1110and1111and the reflective mirrors1112,1113, and1114guide the light components LR, LGand LBto the liquid crystal light valves1115,1116, and1117, respectively, which modulate them into desired patterns. The protection lens1119projects the modulated light components LR, LG, and LBonto the screen1103. According to this embodiment, the projector1102can provide a bright display with high contrast because the projector1102includes any of the liquid crystal devices100to1000, which have an increased aperture ratio to enhance light availability.

Electronic Apparatus

A cellular phone will be described as an example of an electronic apparatus according to an embodiment of the invention.FIG. 31is a perspective view of a cellular phone1200. This cellular phone1200includes a casing1201, an operating unit1202having operating buttons, and a display unit1203that displays, for example, images, videos, and characters. The display unit1203includes any of the liquid crystal devices100to1000according to the embodiments described above.

According to this embodiment, the cellular phone1200can provide a bright display with high contrast because the cellular phone1200includes any of the liquid crystal devices100to1000, which have an increased aperture ratio to enhance light availability.

The technical field of the invention is not limited to the embodiments described above, and various modifications are permitted within the scope of the invention. For example, the inclination angle of the wall surfaces of the grooves10a, which is adjusted by changing the temperature of the TFT array substrate10in the embodiments described above, may also be adjusted by other methods. For example, the inclination angle may be adjusted by appropriately selecting the etchant gas used for dry matching. For example, the etching may be promoted using a mixture of a saturated halocarbon gas, such as CF4or CCl4, and an additive gas that inhibits polymerization to promote the etching, such as Cl2, O2, or F2. On the other hand, an additive gas such as H2, C2F4, or CH4produces fluorocarbons through polymerization with CF4. Such fluorocarbons protect the wall surfaces of the grooves10afrom being etched. Thus, the inclination angle of the wall surfaces of the grooves10acan be adjusted to a desired angle by appropriately selecting the etching gas used. Alternatively, the inclination angle can be adjusted by repeating photolithography and dry etching.

In the embodiments described above, wiring (data lines and scanning lines) and capacitors are disposed in grooves formed on a TFT array substrate, although other structures may also be used. For example, part of TFTs (e.g., semiconductor layers) may be disposed in the grooves.