Semiconductor memory device and test method therefor

Provided is a semiconductor memory device including: first and second SRAM cells; a first bit line pair provided with the first SRAM cell; a second bit line pair provided with the second SRAM cell; a first switch circuit provided between the first bit line pair and the second bit line pair; and a controller that controls the first switch circuit to render the first bit line pair and the second bit line pair conductive, in a case of testing the first SRAM cell.

INCORPORATION BY REFERENCE

This application is based upon and claims the benefit of priority from Japanese patent application No. 2009-045330, filed on Feb. 27, 2009, the disclosure of which is incorporated herein in its entirety by reference.

BACKGROUND

1. Field of the Invention

The present invention relates to a semiconductor memory device and a test method therefor, and more particularly, to a static random access memory (SRAM) and a test method therefor.

2. Description of Related Art

The recent miniaturization of static random access memories (SRAMs) has made it more difficult to secure their operation margin. As disclosed in Japanese Unexamined Patent Application Publication No. 2007-102902 and Published Japanese Translation of PCT International Publication for Patent Application, No. 2008-522334 (PCT Application WO 2006/056902), the operation margin of SRAMs is generally evaluated using static noise margin (SNM). In contrast to the SNM, dynamic noise margin (DNM) is known as an operation margin reflecting more actual operations.

Incidentally, in view of high speed operations and an improvement in the resistance of SRAMs to noise, the number of memory cells, i.e., the number of rows provided for each bit line pair tends to decrease. At present, it is considered that the number of rows is suitably in the range of about 8 to 32.

As a related art of the present invention, Japanese Unexamined Patent Application Publication No. 10-308100 discloses a method for testing an operation margin in a dynamic random access memory (DRAM). In addition, Japanese Unexamined Patent Application Publication No. 11-353898 discloses a method for testing an operation margin in a ferroelectric random access memory (FRAM).

Referring now toFIG. 12which is a graph illustrating a change in noise margin with respect to the number of rows of memory cells of a 40 nm SRAM. The horizontal axis represents, in units of bits, the number of memory cells, i.e., row cells connected to each bit line pair. The longitudinal axis represents, in units of volt (V), a minimum operating voltage (VDDmin) for a memory cell serving as an index of a noise margin. A voltage equal to or higher than VDDmin is required to retain data.

Specifically, the SNM and DNM at six points where the number of rows=8, 16, 32, 64, 128, and 256 bits are plotted. As shown inFIG. 12, the SNM which is a static evaluation value is constant with respect to the number of rows. Meanwhile, the DNM is a dynamic evaluation value which rapidly decreases as the number of rows decreases, resulting in an increase in deviation from the SNM.

SUMMARY

The evaluation of the operation margin using the SNM is suitable as long as the number of rows is large and the deviation between the SNM and DNM is small as in the conventional case. However, when the number of rows is reduced, as described above, the deviation between the SNM and DNM increases. Accordingly, the evaluation of the operation margin using the SNM has a problem in that the operation margin becomes excessively large and the yield is considerably lowered. In other words, if the operation margin can be evaluated appropriately by using the DNM, the yield, i.e., the productivity of high-speed SRAMs can be improved.

A first exemplary aspect of the present invention is a semiconductor memory device including: a first SRAM cell and a second SRAM cell; a first bit line pair provided with the first SRAM cell; a second bit line pair provided with the second SRAM cell; a first switch circuit provided between the first bit line pair and the second bit line pair; and a controller that controls the first switch circuit to render the first bit line pair and the second bit line pair conductive, in a case of testing the first SRAM cell.

A second exemplary aspect of the present invention is a test method for a semiconductor memory device, the semiconductor memory device including: a first bit line pair provided with a first SRAM cell; and a second bit line pair provided with a second SRAM cell, the test method including: in a case of testing the first SRAM cell, rendering the first bit line pair and the second bit line pair conductive at a first timing; and performing a read operation for the first SRAM cell at a second timing subsequent to the first timing.

The provision of the controller that controls the first switch circuit to render the first bit line pair and the second bit line pair conductive, in the case of testing the first SRAM cell, makes it possible to provide a semiconductor memory device which is capable of evaluating the operation margin simply by using the DNM and is excellent in the productivity based on the DNM evaluation.

According to an exemplary aspect of the present invention, it is possible to provide a semiconductor memory device excellent in the productivity based on the evaluation of the operation margin using the DNM.

DETAILED DESCRIPTION OF THE EXEMPLARY EMBODIMENTS

Exemplary embodiments of the present invention will be described in detail below with reference to the accompanying drawings. Note that the present invention is not limited to exemplary embodiments described below. The following descriptions and drawings are simplified as appropriate to clarify the explanation.

First Exemplary Embodiment

FIG. 1is a circuit diagram illustrating a semiconductor memory device according to a first exemplary embodiment of the present invention. The semiconductor memory device is an SRAM. The semiconductor memory device includes a control circuit CTR, a sense amplifier SA, a write circuit WC, n (n is a natural number) pairs of Y selectors YS1ato YSna and YS1bto YSnb, n pairs of precharge circuits PC1ato PCna and PC1bto PCnb, 2n pairs of bit lines BLT1aand BLB1ato BLTna and BLBna, and BLT1band BLB1bto BLTnb and BLBnb, a pair of word line selectors WLSa and WLSb, m (m is a natural number) pairs of word lines WL1ato WLma and WL1bto WLmb, and n×m pairs of memory cells MC. The sense amplifier and write circuit SA/WC includes the sense amplifier SA and the write circuit WC which are integrally illustrated inFIG. 1for convenience of illustration. The sense amplifier SA is a circuit that amplifies a potential difference between two sense nodes of a memory cell MC selected in a read operation. In the case of a memory cell MC1, for example, the sense nodes herein described refer to nodes at which the memory cell MC1is connected with the bit line pair BLT1aand BLB1a. The write circuit WC is a circuit that writes data to the selected memory cell MC in a write operation. That is, the sense amplifier SA and the write circuit WC complementarily operate at different timings.

The sense amplifier and write circuit SA/WC is connected with the n pairs of Y selectors YS1ato YSna and YS1bto YSnb. Each of the Y selectors is connected with a bit line pair including two bit lines. For example, the Y selector YS1ais connected with the bit line pair BLT1aand BLB1a.

As shown inFIG. 1, the Y selectors YS1ato YSna switch electrical connection states between the sense amplifier and write circuit SA/WC and the bit line pairs BLT1aand BLB1ato BLTna and BLBna based on selection signals YE1ato YEna, respectively. Similarly, the Y selectors YS1bto YSnb switch electrical connection states between the sense amplifier and write circuit SA/WC and the bit line pairs BLT1band BLB1bto BLTnb and BLBnb based on selection signals YE1bto YEnb, respectively.

As shown inFIG. 1, the Y selectors YS1ato YSna are connected with the precharge circuits PC1ato PCna, respectively. The precharge circuits PC1ato PCna precharge the bit line pairs BLT1aand BLB1ato BLTna and BLBna, respectively, based on a precharge signal PEa. Similarly, the Y selectors YS1bto YSnb are connected with the precharge circuits PC1bto PCnb, respectively. The precharge circuits PC1bto PCnb precharge the bit line pairs BLT1band BLB1bto BLTnb and BLBnb, respectively, based on a precharge signal PEb.

As shown inFIG. 1, the sense amplifier and write circuit SA/WC, the Y selectors YS1ato YSna and YS1bto YSnb, and the precharge circuits PC1ato PCna and PC1bto PCnb constitute a local circuit LC.

The control circuit CTR is a circuit that controls the Y selectors YS1ato YSna and YS1bto YSnb and the precharge circuits PC1ato PCna and PC1bto PCnb. The selection signals YE1ato YEna and YE1bto YEnb and the precharge signals PEa and PEb are generated based on a test signal TE.

As shown inFIG. 1, the m number of word lines WL1ato WLma are disposed substantially orthogonal to the n pairs of bit lines BLT1aand BLB1ato BLTna and BLBna. The word lines WL1ato WLma are each connected to the word line selector WLSa. Similarly, the m number of word lines WL1bto WLmb are disposed substantially orthogonal to the n pairs of bit lines BLT1band BLB1bto BLTnb and BLBnb.

The n pairs of bit lines BLT1aand BLB1ato BLTna and BLBna are connected with m number of memory cells MC, each of which is connected with the m number of word lines WL1ato WLma. That is, the n×m number of memory cells MC are disposed at intersections of the n pairs of bit lines BLT1aand BLB1ato BLTna and BLBna and the m number of word lines WL1ato WLma. The n×m number of memory cells MC constitute a cell array CA. Herein, “m” represents the number of memory cells, i.e., row cells connected to each bit line pair.

Similarly, the n pairs of bit lines BLT1band BLB1bto BLTnb and BLBnb are connected with m number of memory cells MC, each of which is connected with the m number of word lines WL1bto WLmb. That is, the n×m number of memory cells MC are disposed at intersections of the n pairs of bit lines BLT1band BLB1bto BLTnb and BLBnb and the m number of word lines WL1bto WLmb.

FIG. 2is a detailed circuit diagram illustrating a part of the SRAM shown inFIG. 1.FIG. 2shows the circuit configurations of the Y selector YS1a, the bit line pair BLT1aand BLB1a, the precharge circuit PC1a, and the memory cell MC1, which are illustrated inFIG. 1. Referring toFIG. 2, the bit line pair BLT1aand BLB1ais indicated by boldface.

The Y selector YS1ais a switch circuit which includes two PMOS transistors P1and P2, two NMOS transistors N1and N2, and an inverter INV1. One of the source and drain of each of the PMOS transistor P1and the NMOS transistor N1is connected to the sense amplifier and write circuit SA/WC, and the other of the source and drain of each of the PMOS transistor P1and the NMOS transistor N1is connected to the bit line BLT1a. Similarly, one of the source and drain of each of the PMOS transistor P2and the NMOS transistor N2is connected to the sense amplifier and write circuit SA/WC, and the other of the source and drain of each of the PMOS transistor P2and the NMOS transistor N2is connected to the bit line BLB1a.

The gates of the PMOS transistors P1and P2receive the selection signal YE1athrough the inverter INV1. The gates of the NMOS transistors N1and N2directly receive the selection signal YE1a. When the selection signal YE1ais at “H” (high) level, all the four transistors are turned on. Meanwhile, when the selection signal YE1ais at “L” (low) level, all the four transistors are turned off.

The precharge circuit PC1aincludes three PMOS transistors P3to P5. The sources of the PMOS transistors P4and P5are connected to a power supply (power supply voltage VDD). The drain of the PMOS transistor P4and one of the source and drain of the PMOS transistor P3are connected to the bit line BLT1a. The drain of the PMOS transistor P5and the other of the source and drain of the PMOS transistor P3are connected to the bit line BLB1a.

The gates of the PMOS transistors P3to P5receive the precharge signal PEa. When the precharge signal PEa is at the “L” level, the PMOS transistors P3to P5are turned on and the bit line pair BLT1aand BLB1ais precharged with the power supply voltage VDD. Meanwhile, when the precharge signal PEa is at the “H” level, the PMOS transistors P3to P5are turned off.

The memory cell MC1includes six MOS transistors: two load transistors LD1and LD2which are PMOS transistors, two drive transistors DR1and DR2which are NMOS transistors, and two selection transistors AC1and AC2which are NMOS transistors. The load transistor LD1and the drive transistor DR1constitute an inverter. Similarly, the load transistor LD2and the drive transistor DR2also constitute an inverter.

The sources of the load transistors LD1and LD2are connected to the power supply (power supply voltage VDD). The drains of the load transistors LD1and LD2are connected to the drains of the drive transistors DR1and DR2, respectively. The sources of the drive transistors DR1and DR2are grounded. The gates of the load transistor LD1and the drive transistor DR1are connected to a node at which the drains of the load transistor LD2and the drive transistor DR2are connected to each other. The gates of the load transistor LD2and the drive transistor DR2are connected to a node at which the drains of the load transistor LD1and the drive transistor DR1are connected to each other.

One of the source and drain of the selection transistor AC1is connected to a node at which the drains of the load transistor LD1and the drive transistor DR1are connected to each other. The other of the source and drain of the selection transistor AC1is connected to the bit line BLT1a. One of the source and drain of the selection transistor AC2is connected to the node at which the drains of the load transistor LD2and the drive transistor DR2are connected to each other. The other of the source and drain of the selection transistor AC2is connected to the bit line BLB1a. The gates of the selection transistors AC1and AC2are connected to the word line WL1a.

Referring next toFIGS. 3 to 6, a test operation of the semiconductor memory device according to this exemplary embodiment will be described.FIG. 3is a timing diagram illustrating the test operation according to the first exemplary embodiment. As shown inFIG. 3, a cycle1corresponds to a normal write operation period. During this period, the signal level of the word line WL1abecomes the “H” level, and the memory cell MC1shown inFIG. 1is selected. Further, since the selection signal YE1ais at the “H” level, the memory cell MC1and the sense amplifier and write circuit SA/WC are rendered conductive through the bit line pair BLT1aand BLB1a. Meanwhile, since the precharge signal PEa is at the “H” level, the bit line pair BLT1aand BLB1ais not precharged.

FIG. 4Ais a diagram schematically illustrating a connection state in the cycle1shown inFIG. 3. A write signal WE is input to the write circuit WC so as to activate the write circuit WC. As a result, data is written to the memory cell MC1. In the case ofFIG. 3, “L” is written to the node on the bit line BLT1aside of the memory cell MC1and “H” is written to the node on the bit line BLB1aside of the memory cell MC1.

Referring toFIG. 3, each period between adjacent cycles is a precharge period. During this period, the precharge signal PEa is at the “L” level, and the bit line pair BLT1aand BLB1ais precharged to the “H” signal level. Note that the signal level of the word line WL1aand the selection signal YE1abecome the “L” level, and the memory cell MC1and the sense amplifier and write circuit SA/WC are rendered non-conductive with the bit line pair BLT1aand BLB1a.

A cycle2shown inFIG. 3corresponds to a normal read operation period. During this period, the signal level of the word line WL1aand the selection signal YE1abecome the “H” level, and the memory cell MC1and the sense amplifier and write circuit SA/WC are rendered conductive through the bit line pair BLT1aand BLB1a. In this case, the signal level at the node on the bit line BLT1aside of the memory cell MC1is maintained at the “L” level. Accordingly, in the cycle2, the potential of the bit line BLT1agradually decreases from the “H” level due to the precharge. After the elapse of a predetermined period of time in the cycle2, a sense signal SAE is switched from the “L” level to the “H” level, to thereby activate the sense amplifier SA. As a result, the signal level of the bit line BLT1adrops to the “L” level.

FIG. 4Bis a diagram schematically illustrating a connection state in cycles2and4shown inFIG. 3. The sense signal SAE is input to the sense amplifier SA so as to activate the sense amplifier SA. As a result, data is read from the memory cell MC1.

A cycle3shown inFIG. 3corresponds to a noise addition period. During this period, the test signal TE changes from the “L” level to the “H” level. Further, the signal level of the word line WL1aand the selection signal YE1abecome the “H” level, and the memory cell MC1and the sense amplifier and write circuit SA/WC are rendered conductive through the bit line pair BLT1aand BLB1a. Furthermore, the selection signal YE1bbecomes the “H” level, and the memory cell MC1is also connected to the bit line pair BLT1band BLB1b.

Note that only during the period of the cycle3, the precharge signal PEb becomes the “H” level and the bit line pair BLT1band BLB1bis not precharged. In the cycle3, the sense amplifier SA is not activated, and the read operation, i.e., determination is not performed. In this case, after the sense amplifier SA is activated at the same timing as the cycle2, the bit line pair BLT1aand BLB1aor the word line WL1amay be non-selected to omit the determination.

In this case, the signal level at the node on the bit line BLT1aside of the memory cell MC1is maintained at the “L” level. Accordingly, in the cycle3, the potential of the bit line BLT1agradually decreases from the “H” level due to the precharge. Because the bit line BLT1bis electrically connected with the bit line BLT1a, the potential of the bit line BLT1balso decreases. In the cycle3, the load of the bit line pair BLT1aand BLB1aas well as the load of the bit line pair BLT1band BLB1b, i.e., a double load is applied to the memory cell MC1. For this reason, if the DNM of the memory cell MC1is insufficient, the data is overwritten. Note that the bit line load can be increased by, for example, rendering a bit line pair BLT2band BLB2bconductive to triple the bit line load to be applied to the memory cell MC1.

FIG. 4Cis a diagram schematically illustrating a connection state in the cycle3shown inFIG. 3. The memory cell MC1is connected not only to the bit line pair BLT1aand BLB1abut also to the bit line pair BLT1band BLB1b.

The cycle4shown inFIG. 3corresponds to the normal read operation period. The operation is similar to that in the cycle2, so the description thereof is omitted. In this case, if the DNM of the memory cell MC1is insufficient, the data is overwritten in the cycle3. Accordingly, a DNM deficiency can be determined.

FIG. 5is a flowchart showing the test operation according to the first exemplary embodiment. As described above with reference toFIG. 3, the normal write operation is first carried out in the cycle1. The normal read operation is then carried out in the cycle2. Here, PASS or FAIL is determined. In the case of FAIL, a write margin deficiency or a sense margin deficiency is determined. In the case of PASS in the cycle2, noise is added in the cycle3. Then, the normal read operation is carried out in the cycle4. Here, PASS or FAIL is determined. In the case of FAIL, the DNM deficiency is determined. This DNM test method enables discrimination between FAIL due to the DNM deficiency and FAIL due to other causes.

Specifically, for example, as shown inFIG. 12, in the case of an SRAM having 16 row cells, VDDmin=0.62 V. When bit line loads of 32 row cells are applied to the SRAM having 16 row cells, VDDmin=0.66 V. Accordingly, this test method enables screening of the noise margin in the case where 0.04 V=40 mV. As a matter of course, a larger noise margin can be screened by increasing the bit line load to be applied in the cycle3. That is, the bit line load to be applied in the cycle3may be appropriately determined based on the required DNM.

Referring next toFIG. 6, a description is given of the reason why only the noise addition is performed in the cycle3and the read operation, i.e., determination is not performed in the cycle3.FIG. 6is a graph illustrating, in a superimposed manner, a potential drop of the bit line BLT1ain the cycle2and a potential drop of the bit line BLT1ain the cycle3, which are shown in the timing diagram ofFIG. 3.

As shown inFIG. 6, after the elapse of the predetermined period of time in the cycle2, the sense signal SAE is switched from the “L” level to the “H” level to carry out the read operation. In this case, a voltage drop of the bit line BLT1aat a sense amplifier activation timing is represented by VSA1. Meanwhile, in the cycle3, the load of the bit line pair BLT1aand BLB1aas well as the load of the bit line pair BLT1band BLB1bis applied to the memory cell MC1.

Thus, if the sense amplifier is activated at the same timing, a voltage drop of the bit line BLT1ais represented by VSA2which is smaller than VSA1. This causes a fear that FAIL is determined not due to the DNM deficiency but due to the sense margin deficiency. That is, the cause of the FAIL determination cannot be discriminated. For this reason, the noise addition is performed in the cycle3and the read operation (determination) is performed in the cycle4, i.e., the noise addition and the determination are performed in different cycles.

FIG. 7is a layout diagram of the semiconductor memory device according to the first exemplary embodiment. As described in detail with reference toFIG. 1, the cell arrays CA are formed on both sides of a local circuit LC1. Similarly, the cell arrays CA are formed on both sides of each of local circuits LC2to LC4. The local circuits LC1to LC4are aligned substantially in parallel with each other and are arranged in a rectangular shape as a whole. Along one side of the rectangular shape, a word line sector WSL is disposed, and along another side adjacent to the one side of the rectangular shape, an input/output circuit10is disposed.

As shown inFIG. 7, the number of rows of cell arrays CA, i.e., “m” shown inFIG. 1is preferably in the range from 8 to 32. As shown inFIG. 12, when the number of rows exceeds 32, the change in the DNM due to the increase in the bit line load, i.e., the number of rows becomes smaller, which makes it difficult to perform the DNM test according to this exemplary embodiment. Meanwhile, when the number of rows is smaller than 8, the occupied area of the local circuit LC becomes relatively large, which causes a problem of an increase in the size of the device.

As described above, another bit line pair is temporarily added as a load to the bit line pair, which is provided with the memory cells MC, thereby enabling the DNM test for the memory cells MC. In this case, the bit line pair which is temporarily added as a load is a bit line pair not for test but for normal memory. According to this exemplary embodiment, the operation margin can be appropriately evaluated using the DNM. Therefore, the productivity of high-speed SRAMs can be improved as compared with the evaluation using the conventional SNM.

Second Exemplary Embodiment

Next, a second exemplary embodiment of the present invention will be described with reference toFIG. 8.FIG. 8is a circuit diagram illustrating a semiconductor memory device according to the second exemplary embodiment. The semiconductor memory device shown inFIG. 8differs from the semiconductor memory device shown inFIG. 1in that bridge circuits BLG for connecting the bit line pairs which are opposed to each other through the local circuit LC are provided for each bit line pair. The other configurations are similar to those of the first exemplary embodiment, so the description thereof is omitted.

Specifically, the bit line pair BLT1aand BLB1aand the bit line pair BLT1band BLB1bare connected through the bridge circuit BLG without involving the sense amplifier SA. That is, between the bit line pair BLT1aand BLB1aand the bit line pair BLT1band BLB1b, the bridge circuit BLG and the sense amplifier SA are connected in parallel with each other. Similarly, a bit line pair BLT2aand BLB2aand the bit line pair BLT2band BLB2bare connected through the bridge circuit BLG. The other bit line pairs have the same configuration.

Each bridge circuit BLG includes two PMOS transistors. The bridge circuit BLG which connects the bit line pair BLT1aand BLB1aand the bit line pair BLT1band BLB1bwill be described as a representative example. The gates of the two PMOS transistors receive a bridge signal BE output from the control circuit CTR. When the bridge signal BE is at the “L” level, both the PMOS transistors are turned on, and the bit line pair BLT1aand BLB1aand the bit line pair BLT1band BLB1bare rendered conductive. Meanwhile, when the bridge signal BE is at the “H” level, both the PMOS transistors are turned off. The configuration of the bridge circuit BLG is not limited thereto, and a configuration similar to that of the Y selector, which is described in the first exemplary embodiment, may be employed, for example.

Referring next toFIG. 9, a test operation for the semiconductor memory device according to this exemplary embodiment will be described.FIG. 9is a timing diagram illustrating the test operation according to the second exemplary embodiment. The cycles1,2, and4shown inFIG. 9are similar to the cycles1,2, and4shown inFIG. 3of the first exemplary embodiment, so the description thereof is omitted. The cycle3shown inFIG. 9is described in comparison with the cycle3shown inFIG. 3. While the selection signal YE1bis at the “H” level in the cycle3shown inFIG. 3, the selection signal YE1bis maintained at the “L” level in the cycle3shown inFIG. 9. Meanwhile, in the cycle3shown inFIG. 9, the bridge signal BE for the bridge circuit BLG, which is additionally provided in this exemplary embodiment, changes from the “H” level to the “L” level only during this period. Accordingly, as in the first exemplary embodiment, the memory cell MC1is also connected to the bit line pair BLT1band BLB1b.

The use of the bridge circuit BLG makes it possible to perform the DNM test similar to that of the first exemplary embodiment, even in the case where the sense amplifier SA is not a shared sense amplifier.

Third Exemplary Embodiment

Next, a third exemplary embodiment of the present invention will be described with reference toFIG. 10.FIG. 10is a circuit diagram illustrating a semiconductor memory device according to the third exemplary embodiment. The semiconductor memory device shown inFIG. 10includes two circuits shown inFIG. 1, and the two circuits are connected through the bridge circuits BLG.

On both sides of the local circuit LC1, cell arrays CAa and CAb are connected to each other. Similarly, on both sides of the local circuit LC2, cell arrays CAc and CAd are connected to each other. Additionally, word line selectors WLSb, WLSc, and WLSd are connected to the cell arrays CAb, CAc, and CAd through word lines WLb, WLc, WLd, respectively. Note that the word lines WLb, WLc, and WLd are each represented by one line for convenience of illustration. The detailed configurations of the local circuits LC1and LC2and the cell arrays CAa, CAb, CAc, and CAd are similar to those ofFIG. 1.

The cell array CAb and the cell array CAc are connected through the bridge circuits BLG. Specifically, the bit line pair BLT1band BLB1band a bit line pair BLT1cand BLB1care connected through the bridge circuit BLG. Similarly, the bit line pair BLT2band BLB2band a bit line pair BLT2cand BLB2care connected through the bridge circuit BLG. The other bit line pairs have the same configuration.

Each bridge circuit BLG includes two PMOS transistors. The bridge circuit BLG which connects the bit line pair BLT1band BLB1band the bit line pair BLT1cand BLB1cwill be described as a representative example. The gates of the two PMOS transistors receive the bridge signal BE output from the control circuit CTR. When the bridge signal BE is at the “L” level, both the PMOS transistors are turned on, and the bit line pair BLT1band BLB1band the bit line pair BLT1cand BLB1care rendered conductive. Meanwhile, when the bridge signal BE is at the “H” level, both the PMOS transistors are turned off. The configuration of the bridge circuit BLG is not limited thereto, and a configuration similar to that of the Y selector, which is described in the first exemplary embodiment, may be employed, for example.

Referring next toFIG. 11, a test operation for the semiconductor memory device according to this exemplary embodiment will be described.FIG. 11is a timing diagram illustrating the test operation. The cycles1,2, and4shown inFIG. 11are similar to the cycles1,2, and4shown inFIG. 3of the first exemplary embodiment, so the description thereof is omitted.

The cycle3shown inFIG. 11is described in comparison with the cycle3shown inFIG. 3. In the cycle3shown inFIG. 3, the selection signal YE1bis switch to the “H” level only during this period, whereas in the cycle3shown inFIG. 9, not only the selection signal YE1bbut also selection signals YE1cand YE1dare switched to the “H” level only during this period. Further, in the cycle3shown inFIG. 9, the bridge signal BE for the bridge circuit BLG, which is additionally provided in this exemplary embodiment, is switched from the “H” level to the “L” level only during this period. Accordingly, the memory cell MC1is connected not only to the bit line pair BLT1aand BLB1abut also to the bit line pair BLT1band BLB1b, the bit line pair BLT1cand BLB1c, and a bit line pair BLT1dand BLB1d. That is, a fourfold load is applied to the memory cell MC1.

Note that only during the period of the cycle3, precharge signals PEb, PEc, and PEd become the “H” level, and the bit line pair BLT1band BLB1b, the bit line pair BLT1cand BLB1c, and the bit line pair BLT1dand BLB1dare not precharged.

According to this exemplary embodiment, even in the case where the cell array CA has only one row (when n=1 inFIG. 1), a double or greater bit line load can be added to the memory cells MC.

While the invention has been described in terms of several exemplary embodiments, those skilled in the art will recognize that the invention can be practiced with various modifications within the spirit and scope of the appended claims and the invention is not limited to the examples described above.