Digital decoder with complementary outputs

A digital decoder is provided that produces true and complementary output signals. The digital decoder may be formed from n-channel and p-channel metal-oxide-semiconductor transistors. The digital decoder produces four true outputs and four complementary outputs from two inputs. A first of the true outputs and a first of the complementary outputs are provided using a NOR gate and an inverter. A NAND gate and an inverter are used to provide a second of the true outputs and a second of the complementary outputs. Third and fourth complementary outputs are produced using first and second logic circuits. The first and second logic circuits are powered using only a positive power supply voltage. Third and fourth true outputs are produced using third and fourth logic circuits. The third and fourth logic circuits are powered using only a ground power supply voltage. The logic circuits each include an n-channel and p-channel transistor pair.

BACKGROUND

This invention relates to decoders for digital logic circuits, and more particularly, to digital decoders with true and complementary output lines that operate with short delay times and that can be implemented using relatively few circuit resources.

Digital decoders convert binary input signals on a relatively small number of input lines to a set of corresponding decoded output signals on a relatively larger number of output lines. For example, a two-input digital decoder receives first and second binary signals as inputs and produces four (22) corresponding output signals, whereas a three-input decoder produces eight (23) outputs. Some circuit applications such as memory addressing and tristate driver control require true and complementary control signals. Decoders used in these environments have complementary outputs. For example, a two-input decoder of this type has eight outputs made up of four noninverted and four inverted decoded signals.

Well-designed decoders exhibit short decoding times. Decoders that perform rapidly without undesirable delay times will operate satisfactorily in a variety of integrated circuits and will not unnecessarily slow circuit operation. At the same time, it is important not to use too many circuit resources when implementing a decoder. A decoder that uses a large number of circuit resources will consume a relatively large amount of circuit real estate and may be more prone to failure than less complex designs.

It would therefore be desirable to be able to provide a decoder with an architecture that is capable of supplying both true and complementary decoded outputs while exhibiting short delay times and requiring relatively few circuit resources to implement.

SUMMARY

In accordance with the present invention, digital decoders are provided that can be implemented using a reduced amount of circuit resources while still exhibiting improved switching speeds and reduced power consumption.

The digital decoders use logic circuits that contain complementary transmission gates formed from parallel p-channel and n-channel transistors. When operating in parallel configurations such as these, the p-channel and n-channel transistors can rapidly pass a variety of logic signals. When operated separately, p-channel transistors have difficulties in passing logic zeros and n-channel transistors have difficulties passing logic ones.

Some of the transistors in the decoder are used to form logic gates that are powered using both a positive power supply voltage and a ground power supply voltage. Other transistors are used to form logic circuits that are only powered using a single power supply voltage.

The digital decoder produces four true outputs and four complementary outputs from two inputs.

DETAILED DESCRIPTION

The present invention relates to digital decoders and to integrated circuits in which such decoders are used. The integrated circuits in which the digital decoders may be used may include memory circuits, programmable logic devices, digital signal processing circuits, microprocessors, application specific integrated circuits, or any other suitable integrated circuit containing digital logic. The digital decoders of the present invention may be implemented using any suitable type of logic circuitry. With one particularly suitable arrangement, the digital decoders of the present invention are implemented using complementary metal-oxide-semiconductor (CMOS) transistor technology. Decoder circuitry based on CMOS technology is described herein as an example.

A conventional two-input CMOS digital decoder10is shown inFIG. 1. Decoder10receives input signals on input lines12and produces corresponding decoded output signals on output lines14and16. Input lines12are sometimes referred to as address lines. Decoder10produces both true and complementary outputs. True outputs are produced on output lines14. The complements of the true outputs are produced on output lines16.

The two inputs to decoder10are labeled “A” and “B.” Signals A and B can be either high (i.e., a logic one represented by a high voltage of Vdd) or low (i.e., a logic zero represented by a low voltage of Vss). The values of Vdd and Vss are determined by the power supply levels used on the integrated circuit in which decoder10is used. In a typical scenario, the high voltage Vdd is 1.1 volts and the low voltage Vss is 0 volts.

Decoder10has CMOS inverters18,20,30,32,34, and36, CMOS NOR gate22, and CMOS AND gates24,26, and28. In operation, the input signal A may be a 0 or a 1 and the input signal B may be a 0 or a 1, leading to four possible inputs AB=00, AB=01, AB=10, and AB=11. Decoder10converts these four encoded digital signals into corresponding true signals AB00, AB01, AB10, and AB11and respective complementary signals NAB00, NAB01, NAB10, and NAB11. The true signals go high whenever a corresponding encoded input signal is detected at the input of the decoder. If, for example, the input signal is such that A=0 and B=1, the output signal AB01will be high and its complement NAB01will be low. The remaining true signals (AB00, AB10, and AB11in this example) will be low and the remaining complement signals (NAB00, NAB10, and NAB11in this example) will be high.

Consider, as an example, the situation in which A and B are low. The low A and B signals are routed to the inputs of NOR gate22. The output of NOR gate22is therefore high, so signal AB00at the output of the NOR gate22is high. Inverter30inverts the high AB00 signal, taking signal NAB00at the output of inverter30low.

When A and B are low, the NAND gates24,26, and28each produce high signals at their outputs which are inverted by inverters32,34, and36to produce decoded signals AB01, AB10, and AB11that are low. The complement signals NAB01, NAB10, and NAB11do not pass through the inverters32,34, and36and are therefore the inverse of AB01, AB10, and AB11(i.e., NAB01, NAB10, and NAB11are all high).

As an example, consider the operation of NAND gate24. The low A signal at the decoder input is inverted by inverter18to produce a high signal at a first of the two inputs to NAND gate24. The low signal B is routed to the other of the two inputs of NAND gate24. With one input high and the other low, the output of NAND gate24is high. The NAND gates26and28function similarly.

As this example demonstrates, when the input is such that both A and B are low, the signal AB00is high and the remaining true decoded signals are low.

If A and B are both high, the two inputs to NAND gate28will be high and the output of NAND gate28will be low. Inverter36will invert the low signal to take AB11high. At the same time, the decoded signals AB00, AB01, and AB10will be low.

If A is low and B is high (i.e., A=0 and B=1), the output of inverter18will be high. The inputs to NAND gate24will therefore both be high and the output of NAND gate24will be low. Inverter32will invert this low signal to produce a high AB01 signal. At the same time, the decoded signals AB00, AB10, and AB11will be low.

If A is high and B is low (i.e., AB=10), the output of inverter20will be high. The inputs to NAND gate26will therefore both be high and the output of NAND gate26will be low. Inverter34will invert this low signal to produce a high AB10 signal. At the same time, the decoded signals AB00, AB01, and AB11will be low.

Another conventional decoder arrangement is similar to the arrangement ofFIG. 1, but uses a NAND gate with its inputs tied to the outputs of inverters18and20in place of NOR gate22.

Although the operation of conventional decoders such as decoder10ofFIG. 1is often satisfactory, decoders of this type require 28 transistors to implement and have a maximum path delay equal to three gate delays and a minimum path delay equal to one gate delay.

A circuit diagram of a CMOS inverter such as inverter18is shown inFIG. 2. The inverter ofFIG. 2receives an input logic signal X at input line38and produces a corresponding inverted output signal NX at output line40. The inverter is powered using a positive power supply voltage Vdd (e.g., 1.1 volts) and a ground power supply voltage of Vss (e.g., 0 volts). Two transistor46and48are arranged in series between positive power supply terminal42and ground power supply terminal44. Transistor46is a p-channel metal-oxide-semiconductor (PMOS) transistor, which is activated when its gate input is low. Transistor48is an n-channel metal-oxide-semiconductor (NMOS) transistor, which is activated when its gate input is high.

Logic signal X at input38may either be a logic one (i.e., a high signal represented by voltage Vdd) or a logic zero (i.e., a low signal represented by voltage Vss). If the input on line38is low, transistor46is turned on and transistor48is turned off. Under these conditions, the signal NX on output line40is pulled towards Vdd. If the input on line38is high, transistor46is off and transistor48is on, pulling output NX low towards Vss. Because the output NX is high when the input X is low and the output NX is low when the input X is high, the circuit ofFIG. 2serves as an inverter.

A two-input CMOS NAND gate such as NAND gates24,26, and28ofFIG. 1is shown inFIG. 3. Input signals Y and Z are received on input lines50. A corresponding output signal OUT is produced on output line52. The NAND gate ofFIG. 3receives positive power supply voltage Vdd at positive power supply terminal54and receives ground power supply signal Vss at ground terminal56. PMOS transistors58and60have gates connected to inputs Z and Y, respectively. Transistors62and64are connected in series between output52and ground power supply terminal56.

In operation, the logic circuit ofFIG. 3produces an output signal OUT that is a logical NAND function of inputs Y and Z. If Y and Z are both high, transistors58and60will be off and transistors62and64will be on. In this situation, the output line52is electrically connected to ground56and the output signal OUT is low. If either Y or Z is low or if both Y and Z are low, at least one of transistors62and64will be off while at least one of transistors58and60will be on, thereby pulling output signal OUT high.

A CMOS logic NOR gate such as NOR gate22ofFIG. 1is shown inFIG. 4. The NOR gate ofFIG. 4receives input logic signals Y and Z on input lines66and produces a corresponding output logic signal OUT on output line68. The NOR gate is powered by a positive power supply signal Vdd at positive power supply terminal70and a ground power supply voltage Vss at ground power supply terminal72. The NOR gate has two series-connected PMOS transistors74and76. Transistors78and80are NMOS transistors and are connected in parallel between output68and ground terminal72.

In operation, the logic circuit ofFIG. 4produces an output signal OUT at output68that is a logical NOR function of inputs Y and Z on input lines66. If either Y or Z or both Y and Z are high, transistor78or transistor80or both transistors78and80will be turned on, while at least one of transistors74and76will be off. Under these conditions, the output line68will be electrically connected to ground Vss and the output signal OUT will be low. If both Y and Z are low, transistors78and80will be off while transistors74and76are on, so the output OUT will be high.

As the diagrams ofFIGS. 2,3, and4demonstrate, CMOS logic gates are powered by both a positive power supply and a ground power supply. Inverters generally require two transistors such as transistors46and48ofFIG. 2, two-input CMOS NAND gates require four transistors such as transistors58,60,62, and64ofFIG. 3, and two-input CMOS NOR gates require four transistors such as transistors74,76,78, and80ofFIG. 4. A two-input decoder10of the type shown inFIG. 1therefore requires 28 transistors to implement using CMOS logic. Twelve transistors are used to implement the six inverters18,20,30,32,34, and36, four transistors are used to implement the NOR gate22, and twelve transistors are used to implement the three NAND gates24,26, and28.

The switching speed of decoder10is limited by its critical signal paths. The critical paths in decoder10ofFIG. 1contain three logic gates. For example, the decoded output signal AB01is produced using a signal that travels from input A through three gates: inverter18, NAND gate24, and inverter32. As another example, the decoded output signal AB10is produced using a signal that travels from input B through inverter20, NAND gate26, and inverter34. Because the AB01 and AB10 signals must be valid before the output of the decoder10will be valid, these slow paths through decoder10place an upper limit on the switching speed of decoder10of three gate delays.

Another aspect of the performance of decoder10relates to its power consumption. In many circuit environments, power consumption can be minimized by reducing the difference between the maximum and minimum path delays exhibited by the decoder. For example, when decoders are used to control tri-state buffers that drive a common bus, minimizing the time that two tri-state buffers are simultaneously conducting will reduce the short circuit current. Balancing the path delays of the decoder will ensure that the short circuit current of the tri-state buffers are minimized. Decoder10has a maximum path delay equal to three gate delays and a minimum path delay of one gate delay, so the difference between the maximum and minimum path delays is equal to two gate delays.

An alternative conventional decoder architecture is shown inFIG. 5. With the decoder82ofFIG. 5, switching speed performance is increased and power consumption is reduced at the expense of increased resource consumption.

Decoder82converts encoded input signals A and B on input lines84to decoded output signals AB00, AB01, AB10, and AB11on true output lines86and NAB00, NAB01, NAB10, and NAB11on complement output lines88. Decoder82has inverters90,92,94, and108, NAND gates96,98, and100, and NOR gates102,104, and106. The logic decoding function performed by decoder82is the same as that performed by decoder10ofFIG. 1. When the inputs A and B are such that AB=00, decoded output signal AB00goes high and signals AB01, AB10, and AB11go low. If AB=01, signal AB01is high and signals AB00, AB10, and AB11are low. If AB=10, signal AB10is high and signals AB00, AB01, and AB11are low. If A and B are high, the decoded signal AB11goes high while decoded signals AB00, AB01, and AB10go low. The complement signals on outputs88are always the inverse of the true signals on outputs86.

Consider, as an example, the situation in which A is low and B is low. In this situation, the inputs to NAND gate96are both low and the output of NAND gate96is high. Inverter94inverts the output of NAND gate96to produce a low signal AB11.

The critical paths in decoder82contain only two logic gates, so the decoder82switches in two gate delays. For example, output signal AB11is produced using signals that flow from inputs A and B through a first gate96and a second gate94. As another example, the output signal AB01uses a signal that travels from the B input through a first gate92and a second gate104. Because the slowest signal paths in decoder82involve no more than two logic gates, the decoder82can switch significantly faster than the decoder10ofFIG. 1, which exhibits switching times equal to three gate delays.

Moreover, the maximum path delay for decoder82is equal to two gate delays and the minimum path delay for decoder82is equal to one gate delay, so the difference between the maximum and minimum path delays for decoder82is equal to one gate delay. Decoder82therefore tends to consume less power than decoder10, which exhibits a maximum to minimum path delay difference of two gate delays.

However, a decoder82of the type shown inFIG. 5uses more circuit resources than a decoder10of the type shown inFIG. 1. The four inverters in decoder82require a total of eight CMOS transistors. The three NAND gates require twelve transistors. There are three NOR gates, each of which requires four transistors, so twelve NOR gate transistors are required. In total, the decoder design ofFIG. 5requires 32 transistors. Circuit real estate in integrated circuits is a scare commodity, so the use of 32 transistors in decoder82in place of the 28 transistors used in the decoder10ofFIG. 1gives rise to a significant real estate penalty.

Decoders in accordance with the present invention can be implemented using fewer transistors while still exhibiting fast switching speeds and low power consumption. Such decoders use logic circuits that contain complementary transmission gates. The complementary transmission gates are formed from parallel p-channel and n-channel transistors. When operating in parallel configurations such as these, the p-channel and n-channel transistors can rapidly pass a variety of logic signals. When operated separately, p-channel transistors have difficulties in passing logic zeros and n-channel transistors have difficulties passing logic ones.

An illustrative p-channel transistor110is shown inFIGS. 6 and 7. P-channel transistor110has a gate terminal G, a drain terminal D and a source terminal S. The gate terminal G serves as a control terminal and receives control signal CNT. Drain and source terminals D and S are sometimes collectively referred to as drain-source terminals. In the arrangement shown inFIGS. 6 and 7, one drain-source terminal serves as an input and receives input signal IN, while another drain-source terminal serves as an output and provides a corresponding output signal OUT. When a low gate control signal CNT is applied to transistor110as shown inFIGS. 6 and 7, the transistor110is activated and can pass signals from its input to its output.

The behavior of PMOS transistor110differs depending on whether the input signal IN is low or high. If the input signal IN is low, as shown inFIG. 6, the output signal OUT will be about one threshold voltage Vt above ground (i.e., OUT will be about Vt). If the output voltage OUT is above Vt, the gate-to-source voltage Vgs of transistor110will be more than Vt and transistors110will turn on. With transistor110turned on, the low voltage of the input signal IN will pull the voltage of the output signal OUT low. If the output voltage OUT starts to fall below Vt, the gate-to-source voltage Vgs of transistor110will fall below Vt and the transistor110will turn off. In a typical PMOS transistor, Vt is about 300 mV, which limits the output signal OUT to about 300 mV.

If, however, the input signal is high (i.e., 1.1 volts), as shown inFIG. 7, the gate-source voltage Vgs of transistor110will exceed Vt and transistor110will be turned on. With transistor110turned on, the drain and source of transistor110are electrically connected to each other and the output signal OUT will be pulled to Vdd.

Because of these switching characteristics, PMOS transistors are able to pass high input signals to their outputs with little or no loss in signal quality, as shown inFIG. 7, whereas PMOS transistors are unable to pass low signals from their inputs to their outputs without signal degradation, as shown inFIG. 6.

FIGS. 8 and 9show an NMOS transistor112that is being activated by applying a high control signal CNT to gate G. The behavior of NMOS transistors such as NMOS transistor112also differs depending on whether the transistor input signal IN is high or low.

As shown inFIG. 8, when the input signal IN is high, the output signal OUT is unable to rise above Vdd-Vt. If the output signal OUT falls below this voltage, the gate-source voltage Vgs of transistor will exceed the transistor's threshold voltage Vt, which will turn the transistor112on and will electrically connect output OUT to input IN. This will pull the output OUT high. If the output voltage OUT rises above about Vdd−Vt, the gate-source voltage Vgs of the transistor112will be less than the transistor's threshold voltage Vt, which will turn transistor112off. This will cause the output signal OUT to drop back towards Vdd-Vt.

As shown inFIG. 9, when the input signal IN is low, the gate-source voltage Vgs of transistor112will exceed the threshold voltage Vt, thereby turning transistor112fully on. With transistor112fully on, the output OUT is electrically connected to the low input signal IN, pulling output signal OUT low.

These switching characteristics allow NMOS transistors to pass low input signals to their outputs with little or no loss in signal quality, as shown inFIG. 9. As shown inFIG. 8, NMOS transistors are unable to pass high signals from their inputs to their outputs without signal degradation.

The architecture of the decoder of the present invention uses low-transistor-count logic circuits that include parallel NMOS and PMOS transistors in place of at least some of the logic gates used in conventional decoder architectures. This design reduces the number of transistors that are required to implement the decoder while producing fast switching speeds. This design also minimizes the difference between the path delays for the fastest and slowest paths.

A circuit diagram of a decoder114in accordance with the present invention is shown inFIG. 10. As shown inFIG. 10, decoder114has two inputs116(i.e.,116(1) and116(2)), which receive logic input signals A and B. Inputs116are sometimes referred to as address lines. Decoder114decodes the encoded input signals A and B and generates corresponding decoded output signals on output lines118(i.e.,118(1),118(2),118(3), and118(4)) and120(i.e.,120(1),120(2),120(3), and120(4)). True output signals AB00, AB01, AB10, and AB11are produced on output lines118and respective complementary output signals NAB00, NAB01, NAB10, and NAB11are produced on output lines120.

Decoder114has a NOR gate122that receives the A and B input signals. NOR gate122may be, for example, a NOR gate of the type shown inFIG. 4. A NAND gate124receives the A and B input signals in parallel with the NOR gate. NAND gate126may be, for example, a NAND gate of the type shown inFIG. 3. The outputs of the NOR gate122and NAND gate124are provided to respective inverters126and128. Inverters126and128may be of the type shown inFIG. 2.

Decoder114also has logic circuits130,132,134, and136. Unlike NOR and NAND logic gates, the logic circuits130,132,134, and136are not powered using both power supply rails. Logic circuits130and132are only powered using a positive power supply voltage Vdd at positive power supply terminals138, not a ground power supply voltage Vss. Logic circuits134and136are powered using Vss at ground power supply terminals140, but not Vdd.

Logic circuits130and132each receive as inputs logic input signals A and B and the output of NAND gate124. Logic circuits134and136receive logic signals A and B and the output of NOR gate122as inputs.

Logic circuit136produces the output signals AB10, which is high when A is high and B is low. Logic circuit132produces the complement of signal AB10(i.e., signal NAB10). Signal NAB10is the inverse of signal AB10.

Logic circuit134produces signal AB01, which is high when A is low and B is high. Complementary output signal NAB01is produced by logic circuit130.

The logic circuits130,132,134, and136contain pairs of parallel NMOS and PMOS transistors. When one of the transistors in these complementary transistor pairs is experiencing difficulty in passing logic signals, the other transistor in the pair helps to complete the necessary switching operation. For example, when an NMOS transistor is having difficulty passing a logic one as described in connection withFIG. 8, a PMOS transistor that is operating in parallel with the NMOS transistor assists the NMOS transistor by passing the logic one to a shared output. Similarly, when a PMOS transistor is having difficulty passing a logic zero from its input to its output as described in connection withFIG. 6, a parallel NMOS transistor is used to assist the PMOS transistor.

Because the PMOS and NMOS transistors assist each other, the logic circuits130,132,134, and136exhibit switching speeds that are comparable to the switching speeds associated with traditional NOR and NAND logic gates. In practice, switching speeds are influenced by output loading capacitance, so switching times vary as a function of output loading. If the output lines for signals AB01, AB10, NAB01, and NAB10are lightly loaded, the delay time associated with switching circuits130,132,134, and136might be equal to about 10%-15% more than a conventional gate delay. Under more heavily loaded conditions, the switching speed for circuits130,132,134, and136will decrease, but switching delay times for circuits130,132,134, and136will still be less than two gate delays.

The critical paths for decoder114are the paths that pass through two logic gates. In particular, the signal NAB00is produced using signals that pass through a first logic gate122and a second logic gate126. Similarly, the signal AB11is produced using signals that pass through a first logic gate124and a second logic gate128. The signals NAB00and AB11therefore exhibit two gate delays. Signals NAB00and AB11are the slowest decoded output signals produced by decoder114, because the switching delay times for circuits130,132,134, and136are each less than two gate delays.

The maximum path delay associated with decoder114is equal to two gate delays while the minimum path delay associated with decoder114is equal to one gate delay. In contrast, the conventional decoder10ofFIG. 1has a minimum path delay equal to one gate delay and a maximum path delay of three gate delays. As a result, the difference between the maximum and minimum path delays for the decoder114ofFIG. 10(one gate delay) is less than the corresponding path delay difference in the conventional decoder ofFIG. 1(two gate delays).

Minimizing the difference between the maximum and the minimum path delays can reduce power consumption significantly. Decoders with complementary outputs are often used to drive tristate buffers. For example, decoders can produce complementary outputs that drive tristate buffers in programmable logic device look-up tables and tristate drivers in logic circuits such as memories. In environments such as these, tristate buffers drive a common circuit network. When tristate buffers are used to drive a common circuit network, current is wasted whenever one tristate driver is turned off while another tristate driver is turned on. This is because there is a direct path between the positive supply (sometimes called VDD) and ground (sometimes called VSS). If there is a substantial time difference between the time at which one tristate driver is turned on and the other is turned off, the amount of wasted current can be considerable. In an ideal situation, one would like any two tristate buffers that drive a common circuit network to switch simultaneously. Although absolutely simultaneous switching is not possible in practice, the decoder circuit ofFIG. 10comes close to the ideal limit by exhibiting a minimal difference between its maximum and minimum path delays

The design of decoder114uses a relatively small number of transistors. In decoder114, four transistors are used to implement inverters126and128. Eight transistors are used to implement NOR gate122and NAND gate124. Logic circuits130,132,134, and136require a total of twelve transistors. The decoder114is therefore implemented using 24 transistors.

The decoder114uses fewer transistors than the conventional decoder10ofFIG. 1(which uses 28 transistors) and the conventional decoder82ofFIG. 5(which uses 32 transistors). At the same time, the two-gate-delay switching speed of decoder114is faster than the three-gate-delay switching speed of conventional decoder10ofFIG. 1and matches the switching speed of conventional decoder82ofFIG. 5. Because decoder114exhibits a difference of only one gate delay between its maximum and minimum path delays, power consumption is minimized.

FIGS. 11,12,13, and14are truth tables showing how the decoded outputs AB00, AB01, AB10, AB11, go high in response to corresponding sets of input signals A and B.

For example, the truth table ofFIG. 13shows how the decoded output signal AB00goes high when A is low and B is low (i.e., when A=0 and B=0), whereas the remaining decoded output signals AB01, AB10, and AB11are low (in this example). The complementary output signals NAB00, NAB01, NAB10, and NAB11are the inverse of signals AB00, AB01, AB10, and AB11. When signals A and B are both low, the output of NOR gate122is high, so AB00is high, as shown in theFIG. 13truth table. Inverter126inverts the high AB00 signal, so that NAB00is low.

The truth table ofFIG. 14shows the output signals that are produced when A=1 and B=1 (i.e., when A and B are both high). When A and B are high, the output of NAND gate124is low. The low output signal from the output of NAND gate124is conveyed to the NAB11output line120(2). Inverter128inverts the low NAB11 signal to produce signal AB11on the output line118(2) that is connected to the output of inverter128.

When A is high and B is low or when B is high and A is low, the output of NOR gate122is low and the output of NAND gate124is high. As shown in the truth tables ofFIGS. 13 and 14, the signals AB00and AB11are therefore low. Under these conditions, the signals AB01and AB10(and complementary signals NAB01and NAB10) are produced using logic circuits130,132,134, and136.

Consider, as an example, the output AB01of logic circuit134, which corresponds to the truth table ofFIG. 11. Line142passes the input signal A to the gate of PMOS transistor T1and the gate of NMOS transistor T3.

When A is high, transistor T1is off and transistor T3is on. Lines144and146pass the high A signal and the low B signal to the inputs of NOR gate122. Because A is high, the output of NOR gate122is low, regardless of the state of B. The low signal at the output of NOR gate122is passed to the gate of transistor T2via path148. Transistor T2is an NMOS transistor and is therefore turned off by the low signal on its gate. With transistors T1and T2off and transistor T3on, the output line for signal AB01is tied to ground terminal140. Signal AB01is therefore pulled low to Vss both when B is high and when B is low, as shown in the last two rows of the third column of the truth table ofFIG. 11.

When A is low, transistor T1is on and transistor T3is off. The low A signal is applied to the input of NOR gate122via line144. The other input of NOR gate122receives the signal B via line146. Because the A signal input is low, the output of NOR gate122is equal to the complement of logic signal B (called NB). The signal NB is passed from the output of NOR gate122to the gate of transistor T2via path148.

If B is high when A is low, signal NB will be low, turning NMOS transistor T2off. Because NMOS transistor T2is off, NMOS transistor T2will not be able to transmit the high B signal from path150to output AB01. However, PMOS transistor T1is connected in parallel with transistor T2. PMOS transistor T1is turned on, because the A input signal on line142is low. The low A signal on line142also turns NMOS transistor T3off. With transistor T3off, turning transistor T1on allows the high B signal from line150to propagate through transistor T1to output AB01. As shown by the row in the table ofFIG. 11corresponding to A=0 and B=1, AB01therefore goes high.

If B is low when A is low, the low A signal on the gates of transistors T1and T3will turn transistor T1on and transistor T3off. With transistor T1on, transistor T will start to pass the low B signal on path150to output AB01. However, because transistor T1is a PMOS transistor, transistor T1will have difficulty in successfully passing the low B signal from line150to output AB01. As described in connection withFIG. 6, PMOS transistors have difficulty in passing logic zero values and tend to produce output signals that are not at Vss, but rather are at a somewhat higher voltage of Vt (e.g., 300 mV).

The presence of parallel NMOS transistor T2helps circuit134overcome this difficulty. With B and A low, the output of NOR gate122goes high. Path148passes this high signal to the gate of NMOS transistor T2and turns transistor T2on slightly after PMOS transistor T1is turned on. Transistor T2is an NMOS transistor and therefore successfully conveys the low B signal from line150onto output AB01. As shown in table ofFIG. 11, when A and B are low, the output signal AB01is low. There is one gate delay required for transistor T2to turn on while B is transitioning from 1 to 0. However, this one-gate-delay penalty is approximately the same amount of delay that is required for the transition from B=1 to B=Vt. In other words, the PMOS transistor T1is able to pass the signal B from input116as it transitions from B=1 to B=Vt, so that by the time the NMOS transistor T2is needed to help handle the rest of transition (B=Vt to 0), the gate of transistor T2will already be high. The one-gate-delay penalty associated with transistor T2therefore does not add any delay to the decoder and the decoder exhibits a switching time of close to one gate delay.

In circuit136, the A and B signals are reversed relative to the circuit134. Circuit136therefore operates similarly to circuit134, but with A and B reversed. The output AB10of circuit136for various input conditions is shown in the truth table ofFIG. 12.

Circuits130and132are used to produce the complementary output signals NAB01(the complement to signal AB01) and NAB10(the complement to signal AB10). Consider, as an example, the operation of circuit132.

If input signal A is low, then transistor Ta in circuit132will be on and transistor Tb in circuit132will be off. With A low, the output of NAND gate124will be high, turning transistor Tc off. With transistors Tb and Tc off and transistor Ta on, the output signal NAB10will be high, regardless of the state of signal B. This functionality is illustrated by the two rows in the truth table ofFIG. 12corresponding to A=0.

If input signal A is high, then transistor Ta in circuit132is off and transistor Tb is on. Under these conditions, the output signal NAB10depends on the state of B.

If B is low while A is high, the output of NAND gate124will be high and transistor Tc of circuit132will be off. Although transistor Tc is off, the low B signal will be easily passed from line152to output NAB10through NMOS transistor Tb, which is on. This causes signal NAB10to go low, as shown in the row of the table inFIG. 12corresponding to A=1, B=0.

If B is high while A is high, transistor Tb of circuit132will start to pass the high B signal from line152to output NAB10, but will have difficulty as described in connection withFIG. 8. However, with B high and A high, the output of NAND gate124will go low. Once the output of NAND gate124goes low, parallel transistor Tc is turned on. Transistor Tc is a PMOS transistor and is therefore able to assist the NMOS transistor Tb in passing the high B signal from line152to output NAB10. As shown in the row of the table inFIG. 12corresponding to A=1, B=1, this ensures that the NAB10 signal goes high.

In circuit130, the A and B signals are reversed relative to the circuit132. Circuit130therefore operates similarly to circuit132, but with A and B reversed. The output NAB01of circuit130for various states of input signals A and B is shown in the truth table ofFIG. 11.

Decoders with both true and complementary output lines are particularly useful in application such as memory addressing and controlling tristate drivers. If desired, however, two-input decoders such as decoder114ofFIG. 10may be constructed without some or all of the complementary output lines or without some or all of the true output lines.

Decoders with more than two inputs can be constructed by combining a number of two-input decoders of the type shown inFIG. 10. An illustrative four-input decoder154that has been constructed from two two-input decoders156and158is shown inFIG. 15. In the example ofFIG. 15, decoder156produces four true outputs AB00, AB01, AB10, and AB11in response to input signals A and B. Decoder158produces four true outputs CD00, CD01, CD10, and CD11in response to input signals C and D. Decoders156and158may, if desired, be two-input decoders of the type shown inFIG. 10that produce both true and complementary outputs. Complementary outputs are not shown inFIG. 15to avoid over-complicating the drawing.

As shown inFIG. 15, the decoded outputs from decoder156and the decoded outputs from decoder158may be combined using AND gates160. The resulting outputs162from the AND gates serve as the decoded outputs of the four-input decoder154.