Semiconductor device and method for fabricating the same

A semiconductor device includes a substrate including a first active region, a second active region, and an isolation region positioned between the first active region and the second active region; and a gate layer crossing over the first active region, the second active region, and the isolation region, wherein the gate layer includes a first impurity doped portion overlapping with the first active region, a second impurity doped portion overlapping with the second active region, and a diffusion barrier portion positioned between the first impurity doped portion and the second impurity doped portion.

CROSS-REFERENCE TO RELATED APPLICATIONS

The present application claims priority to Korean Patent Application No. 10-2020-0059191, filed on May 18, 2020, which is incorporated herein by reference in its entirety.

BACKGROUND

Various embodiments of the present invention relate generally to a semiconductor device and a method for fabricating the same, and more particularly, to a semiconductor device applying a dual polysilicon gate, and a method for fabricating the semiconductor device.

2. Description of the Related Art

In a recent CMOS fabrication process, when a polysilicon gate electrode is used, a Dual Poly Gate (DPG) that induces a threshold voltage of a transistor to a predetermined range by implanting an N type impurities to an NMOS region and a P type impurities to a PMOS region to match their work function, is being applied.

The dual poly gate, however, has a problem in that the implanted impurities may be diffused out of the gate region into an adjacent region by a subsequent heat process which may deteriorate the performance of opposite type transistors.

SUMMARY

Embodiments of the present invention are directed to a semiconductor device capable of preventing deterioration in the performance of a transistor, and a method for fabricating the semiconductor device.

In accordance with an embodiment of the present invention, a semiconductor device includes: a substrate including a first active region, a second active region, and an isolation region positioned between the first active region and the second active region; and a gate layer crossing over the first active region, the second active region, and the isolation region, wherein the gate layer includes a first impurity doped portion overlapping with the first active region, a second impurity doped portion overlapping with the second active region, and a diffusion barrier portion positioned between the first impurity doped portion and the second impurity doped portion.

In accordance with another embodiment of the present invention, a method for fabricating a semiconductor device includes: providing a substrate including a first active region, a second active region, and an isolation region positioned between the first active region and the second active region; forming a gate layer crossing over the first active region, the second active region, and the isolation region; forming a first impurity doped portion in the gate layer overlapping with the first active region; forming a second impurity doped portion in the gate layer overlapping with the second active region; and forming a diffusion barrier portion in the gate layer between the first impurity doped portion and the second impurity doped portion.

In accordance with another embodiment of the present invention, a semiconductor device includes: an isolation region positioned between a first active region and a second active region; and a gate layer including a first and second impurity doped portions separated by a diffusion barrier portion, wherein the first impurity doped portion is formed over the first active region and extends over an edge of the first active region facing the isolation region to partially overlap with the isolation region, wherein the second impurity doped portion is formed over the second active region and extends over an edge of the second active region.

DETAILED DESCRIPTION

It will be further understood that when an element is referred to as being “connected to”, or “coupled to” another element, it may be directly on, connected to, or coupled to the other element, or one or more intervening elements may be present. Furthermore, the connection/coupling may not be limited to a physical connection but may also include a non-physical connection, e.g., a wireless connection.

In addition, it will also be understood that when an element is referred to as being “between” two elements, it may be the only element between the two elements, or one or more intervening elements may also be present.

As used herein, singular forms are intended to include the plural forms as well, unless the context clearly indicates otherwise.

It should also be noted that features present in one embodiment may be used with one or more features of another embodiment without departing from the scope of the invention.

It is further noted, that in the various drawings, like reference numbers designate like elements.

The described embodiment of the present invention may be applied to a semiconductor device using a dual poly gate having a doped polysilicon gate with an NMOS region and a PMOS region that are separately formed by implanting impurities through an ion implantation process. The described process may be applied to most silicon semiconductor device fabrication processes, except for the fabrication processes of some high-performance semiconductor devices (for example, high-k metal gates) that includes metal gate electrodes and high-k dielectric layers as constituent elements.

The methods of forming a dual polysilicon gate may be roughly categorized into methods which implant an impurity simultaneously with the polysilicon deposition and methods which implant an impurity into each region after forming an undoped polysilicon gate.

A dual polysilicon gate forming method of implanting an impurity during a polysilicon deposition may be performed by Chemical Vapor Deposition. The dual polysilicon gate forming method may be performed by adding a gas containing a group-5 element, such as phosphorus (P), when a polysilicon layer is deposited so as to form a pre-doped N+ polysilicon layer on the profile, forming a mask that opens a PMOS region, and then forming a P+ polysilicon layer by implanting a group-3 element, such as boron (B). In order to form the P+ polysilicon layer in the PMOS region, it is necessary to convert most impurities of the PMOS region to boron through a counter doping process of doping more boron (B) than the phosphorus (Ph) that is already implanted in the deposition process. This process is advantageous in that the process is relatively simple and the concentration distribution of the implanted phosphorus during the deposition is uniform. However, the amount of boron implanted to form the P+ polysilicon layer is excessive which makes it difficult to finely adjust the work function of the P+ polysilicon layer in the PMOS region. Because of these problems with the dual polysilicon gate forming method of implanting an impurity during the polysilicon deposition, a dual poly gate process of forming an N+ polysilicon layer and a P+ polysilicon layer by implanting impurities into the respective regions after forming an undoped polysilicon gate is applied according to an embodiment of the present invention.

FIG. 1is a plan view illustrating a semiconductor device in accordance with an embodiment of the present invention.FIGS. 2A and 2Bare cross-sectional views illustrating a semiconductor device in accordance with an embodiment of the present invention.FIG. 2Ais a cross-sectional view taken along a line A-A′ shown inFIG. 1, andFIG. 2Bis a cross-sectional view taken along a line B-B′ and a line C-C′.FIG. 6is a cross-sectional view illustrating another example of the semiconductor device in accordance with the embodiment of the present invention.FIG. 7is a plan view illustrating a semiconductor device according to a comparative example.FIG. 8is a graph showing a variation of an impurity concentration of a gate layer after heat diffusion of the semiconductor device according to the comparative example.

Referring toFIG. 1, a substrate11may include a first active region13A, a second active region13B, and an isolation region12positioned between the first active region13A and the second active region13B. Also, a gate layer15may be formed over the substrate11to cross over the first active region13A, the second active region13B, and the isolation region12. The gate layer15may include a first impurity doped portion15A overlapping with the first active region13A and a first portion of the isolation region12, a second impurity doped portion15B overlapping with the second active region13B and a second portion of the isolation region, and a diffusion barrier portion15C positioned between the first impurity doping portion15A and the second impurity doping portions15B. According to an embodiment, the diffusion barrier portion15C may overlap with a third portion of the isolation region12which is positioned centrally between the first and second portions of the isolation region12.

The substrate11may include a semiconductor substrate. The substrate11may be formed, for example, of a material containing silicon.

An active region13may be defined by the isolation region12. The isolation region12may be a shallow trench isolation region (STI) region formed by a trench etching process. The isolation region12may include, for example, silicon oxide, silicon nitride, or a combination thereof.

The first active region13A and the second active region13B may be regions for forming different types of MOS transistors. The active regions may be formed as the first active region13A and the second active region13B according to the conductivity type of the impurity implanted into the substrate11. For example, the first active region13A may be a PMOS region, and the second active region13B may be an NMOS region. The width of the first active region13A may be larger than that of the second active region. The first and second active regions13A and13B may be divided by the isolation region12.

A gate dielectric layer14may be positioned between the gate layer15and the substrate11.

The gate layer15may include a conductive material. The gate layer15may include polysilicon. The gate layer15may be formed in a shape of a continuous line crossing over the first active region13A, the second active region13B, and the isolation region12.

The gate layer15may include the first impurity doped portion15A overlapping with the first active region13A, the second impurity doped portion15B overlapping with the second active region13B, and the diffusion barrier portion15C positioned between the first impurity doped portion15A and the second impurity doped portions15B. To be specific, the first impurity doped portion15A may overlap with the first active region13A and may further include an extension portion15AE partially overlapping the isolation region12. The second impurity doped portion15B may overlap with the second active region13B and may further include an extension portion15BE partially overlapping the isolation region12. The diffusion barrier portion15C may overlap with the isolation region12positioned between the first active region13A and the second active region13B.

The first impurity doped portion15A and the second impurity doped portion15B may have different diffusion coefficients. The first impurity doped portion15A and the second impurity doped portion15B may have the opposite conductivity types.

For example, when the first active region13A is a PMOS region, the first impurity doped portion15A may include a P-type impurity. The P-type impurity may include, for example, a group-3 element. The group-3 element may include, for example, boron (B). As shown inFIG. 2B, the first active region13A may have a P-type gate in which the gate dielectric layer14and the first impurity doped portion15A are stacked.

When the second active region13B is an NMOS region, the second impurity doped portion15B may include an N-type impurity. The N-type impurity may include, for example, a group-5 element. The group-5 element may include, for example, phosphorus (P). As shown inFIG. 2B, the second active region13B may include an N-type gate in which the gate dielectric layer14and the second impurity doped portion15B are stacked.

The diffusion barrier portion15C may include an undoped region. The diffusion barrier portion15C may serve to prevent the impurities implanted into the first and second impurity doped portions15A and15B from being diffused into the opposite regions.

Referring toFIG. 1, hereinafter, for the sake of convenience in description, an edge of the first active region13A facing the diffusion barrier portion15C may be represented by ‘E1’, and an edge of the second active region13B facing the diffusion barrier portion15C may be represented by ‘E2’, and an edge of the diffusion barrier portion15C facing the first active region13A may be represented by ‘E31’, and an edge of the diffusion barrier portion15C facing the second active region13B may be represented by ‘E32’.

The edges E31and E32of the diffusion barrier portion15C may be spaced apart from the edges E1and E2of the facing first and second active regions13A and13B. The width of the diffusion barrier portion15C, that is, the distance between the edges E31and E32of the diffusion barrier portion15C may be shorter than the distance D12between the edge E1of the first active region and the edge E2of the second active region.

The distance D131between the edge E1of the first active region and the edge E31of the diffusion barrier portion15C that are facing each other may be shorter than the distance D132between the edge E1of the first active region and the edge E32of the diffusion barrier portion15C on the opposite side of the diffusion barrier portion.

The distance D232between the edge E2of the second active region and the edge E32of the diffusion barrier portion15C that are facing each other may be shorter than the distance D231between the edge E2of the second active region and the edge E31of the diffusion barrier portion15C on the opposite side.

The first and second active regions13A and13B may be spaced apart by a predetermined design rule to retain a processing margin. Hereinafter, the space between the first active region13A and the second active region13B may be called ‘N-P space’. The distance (or width) of the N-P space may be represented by D12. The interface between the first impurity doped portion15A and the second impurity doped portion15B, that is, the diffusion barrier portion15C, may be positioned in the N-P space, and the width of the diffusion barrier portion15C may be adjusted to an effective distance as far as the inter-diffusion of the implanted impurities does not reach the active region on the opposite side even though the inter-diffusion of the implanted impurities occurs. In other words, the effective distance means a distance that the inter-diffusion in the first impurity doped portion15A does not reach the second active region13B, and also that the inter-diffusion in the second impurity doped portion15B does not reach the first active region13A. This design rule defines the space D231of the first impurity doped portion15A and the space D132of the second impurity doped portion15B.

As a comparative example, referring toFIG. 7, an interface E50between the first impurity doped portion55A and the second impurity doped portion55B may be formed in contact. This is based on that the internal diffusion and the external diffusion phenomena occurring in the inter-diffusion are the same and, consequently, a space definition value and an overlap definition value in terms of the design rule are set the same. That is, the relationship between the space D52of the first impurity doped portion55A and the overlap D52of the second impurity doped portion55B, or the relationship between the space D15of the second impurity doped portion55B and the overlap D15of the first impurity doped portion55A, which are in a complementary relationship to each other, may be set the same. Also, it may not be assumed that the relationship between the space D52of the first impurity doped portion55A and the space D15of the second impurity doped portion55B, and, the value of the overlap D15of the first impurity doped portion55A and the value of the overlap D52of the second impurity doped portion55B may be the same. In other words, since the first impurity doped portion55A and the second impurity doped portion55B existing in the N-P space between the first active region53A and the second active region53B are complementary to each other, they may be designed without any overlapping region or a region that does not belong to any region. However, the position of the boundary E50between the first impurity doped portion55A and the second impurity doped portion55B in the N-P space region may be arbitrary.

Since the thermal diffusion phenomenon of the impurities in the first and second impurity doped portions55A and55B is an inter-diffusion phenomenon, the phenomenon occurring at the interface between the first impurity doped portion55A and the second impurity doped portion55B may mean that an internal diffusion (diffuse-in) and an external diffusion (diffuse-out) occur simultaneously. Since the thermal diffusion inside a solid is a chemical equilibrium phenomenon occurring in a direction to offset a concentration difference, the inter-diffusion phenomena before and after the heat treatment may be schematically shown inFIG. 8. Referring toFIG. 8, it may be seen that the interface between the first impurity doped portion55A and the second impurity doped portion55B may be vertically detected before the heat treatment but, after the heat treatment, the concentration of each impurity may be distributed in an X shape according to the inter-diffusion phenomenon.

It is noted that the comparative example is based on a design technique assuming that the diffusion coefficients of the internal diffusion and the external diffusion in the inter-diffusion phenomenon are the same, and the diffusion coefficient of an impurity for substantially forming an impurity doped portion may differ according to the kind of the impurity. Particularly, since a silicide region is formed over polysilicon or a metal layer is bonded for the purpose of decreasing the resistance of a gate, the difference in the diffusion coefficients according to the structural situation of a gate electrode may also be large in a metal-silicon gate process.

Therefore, this embodiment of the present invention may be able to decrease the distance D12of the N-P space, compared to the comparative example (in which the interface between the first impurity doped portion55A and the second impurity doped portion55B is formed in contact) by forming the diffusion barrier portion15C, which is an undoped region, between the first impurity doped portion15A and the second impurity doped portion15B.

The variation in the effective doping concentration of the gate layer15in the first active region13A and the second active region13B that are adjacent to the interface between the first impurity doped portion15A and the second impurity doped portion15B may be defined by a space D231of the first impurity doped portion15A and a space D132of the second impurity doped portion15B defined by the internal diffusion of the impurities. Also, at the same time, it may be defined by the overlap D131of the first impurity doped portion15A (over the first active region) and the overlap D232of the second impurity doped portion15B (over the second active region), which are defined by the external diffusion of the impurities.

When a P-type impurity is applied as the first impurity doped portion15A and an N-type impurity is applied as the second impurity doped portion15B, the internal diffusion phenomenon of the impurities may appear much more after the heat treatment. Therefore, in this embodiment of the present invention, the N-P space value may be designed to be larger than the overlap definition value.

In this embodiment of the present invention, the first impurity doped portion15A and the second impurity doped portion15B may not be complementary, and there is an effect of making the space definition value larger than the overlap definition value in terms of the design rule by forming the diffusion barrier portion15C, that is, an undoped region, between the first impurity doped portion15A and the second impurity doped portion15B. Therefore, even in an N-P space that is smaller than that of the comparative example, device characteristics may be secured without causing deterioration in the device performance that may occur due to inter-diffusion. Also, since the process of forming the diffusion barrier portion15C adopts an independent mask process for forming the first impurity doped portion15A and the second impurity doped portion15B as it is, there may be no additional process or a change in the process.

As described above, according to the embodiment of the present invention, in a semiconductor device to which the dual poly gate process is applied, the first impurity doped portion15A and the second impurity doped portion15B may be independently set in consideration of the diffusion coefficients of the doped impurities. Therefore, it may be possible to prevent the performance deterioration of NMOS and PMOS caused by inter-diffusion and reduce the N-P space. Since a CMOS circuit formed of a combination of NMOS and PMOS has to be positioned adjacent to the NMOS region and the PMOS region, the decrease in the N-P space defined by the distance between the two regions may result in a reduction in the size of the basic layout elements that form the CMOS circuit. As a result, it is possible to obtain the effect of reducing the total circuit area.

Also, considering that the operation of the CMOS circuit is performed by signal transfer between the NMOS and the PMOS, the decrease of the N-P space may inevitably have an effect of shortening the length of a wiring layer formed for signal connection between the NMOS and the PMOS. The length of a wire used for signal transfer being shortened may mean that both resistance and capacitance of the wiring layer are decreased. This may decrease the time constant defined in a RC delay so as to raise the speed of the signal transfer rate between semiconductor devices. The fast signal transfer rate may improve the overall operation rate of a semiconductor circuit.

The difference in the diffusion coefficients between the internal diffusion and the external diffusion in the inter-diffusion phenomenon may appear due to various reasons, such as a case when the characteristics of the gate material are different, in particular, a case when a gate structure having a complex cross-sectional structure using a metal-silicon junction is used, a case when a different kind of an impurity other than the typical impurities specified as phosphorus or boron, or a case when an electrical inert impurity such as carbon (C), nitrogen (N) and fluorine (F) is implanted.

Therefore, according to another embodiment of the present invention, as shown inFIG. 6, the diffusion barrier portion15D may include a neutral region in which both N-type and P-type impurities are doped. This is not the case where the diffusion coefficient of the internal diffusion is not greater than the diffusion coefficient of the external diffusion in the inter-diffusion phenomenon, which is the case of the embodiment of the present invention, but the opposite case, and thus the overlap definition value may be set larger than the space definition value in terms of the design rule.

FIGS. 3A to 3Dare cross-sectional views illustrating a method for fabricating a semiconductor device in accordance with an embodiment of the present invention.

Referring toFIG. 3A, an isolation region12and an active region13may be formed in a substrate11.

The active region13may be defined by the isolation region12. The isolation region12may be a shallow trench isolation region (STI) region formed by a trench etching process. The isolation region12may be formed by filling a shallow trench, for example, an isolation trench, with a dielectric material. The isolation region12may include, for example, silicon oxide, silicon nitride, or a combination thereof.

The active region may be formed of a first active region13A and a second active region13B according to the conductivity type of the impurity implanted into the substrate11. For example, the first active region13A may be formed as a PMOS region, and the second active region13B may be formed as an NMOS region.

Subsequently, a gate dielectric layer14may be formed over the substrate11. In an embodiment, the gate dielectric layer14may be formed directly on the substrate11and be in contact with the top surfaces of the first and second active regions13A,13B and the isolation region12. The gate dielectric layer14may include, for example, silicon oxide.

Subsequently, a gate layer15may be formed over the gate dielectric layer14. The gate layer15may be formed directly on the gate dielectric layer14. The gate layer15may include a conductive material. For example, the gate layer15may include polysilicon. The gate layer15may include undoped (intrinsic) polysilicon. The gate layer15may be formed, for example, by chemical vapor deposition (Chemical Vapor Deposition).

Referring toFIG. 3B, a first mask layer16may be formed over the second active region13B and the isolation region12. The first mask layer16may be formed directly on the second active region13B and the isolation region12. The first mask layer16may open the first active region13A and a portion of the isolation region12. This is to secure device characteristics that are resistant to process dispersion including alignment errors that may occur during the process.

Subsequently, a first ion implantation101for forming the first impurity doped portion15A may be performed. When the first active region13A is a PMOS region, the first impurity doped portion15A may include a P-type impurity. The P-type impurity may include, for example, a group-3 element. The group-3 element may include, for example, boron (B).

Subsequently, although not illustrated, after the first ion implantation101is completed, the first mask layer16may be removed. When the first mask layer16includes a photosensitive film, the removal process of the first mask layer16may be performed by a strip process.

Referring toFIG. 3C, a second mask layer17may be formed over the first active region13A and the isolation region12. The second mask layer17may be formed directly on the first active region13A and the isolation region12. The second mask layer17may open the second active region13B and a portion of the isolation region12. This is to secure device characteristics that are resistant to process dispersion including alignment errors that may occur during the process.

Subsequently, the second ion implantation102may be performed to form the second impurity doped portion15B. When the second active region13B is an NMOS region, the second impurity doped portion15B may include an N-type impurity. The N-type impurity may include, for example, a group-5 element. The group-5 element may include, for example, phosphorus (P).

Subsequently, although not illustrated, the second mask layer17may be removed after the second ion implantation102is completed. When the second mask layer17includes a photosensitive film, the removal process of the second mask layer17may be performed by a strip process.

Referring toFIG. 3D, a first impurity doped portion15A, a second impurity doped portion15B, and a diffusion barrier portion15C positioned between the first impurity doped portion15A and the second impurity doped portion15B may be formed through the first and second ion implantation (see101,102,FIGS. 3B and 3C). The diffusion barrier portion15C may contact the first impurity doped portion15A and the second impurity doped portion15B. The diffusion barrier portion15C may be maintained as an undoped region, since the gate layer15protected by the first and second mask layers (see16,17,FIGS. 3B and 3C) during the first and second ion implantation processes101and102is not doped with an impurity.

FIG. 4is a perspective view illustrating another example of a semiconductor device in accordance with an embodiment of the present invention.

Referring toFIG. 4, a substrate11may include a first active region13A, a second active region13B, and an isolation region12positioned between the first active region13A and the second active region13B. Also, a recess pattern R may be formed in a gate region of the substrate11. The recess pattern R may be formed to cross the first active region13A, the second active region13B, and the isolation region12. Then, a gate layer15may be formed to gap-fill the recess pattern R and cross the first active region13A, the second active region13B, and the isolation region12. The gate layer15may include a first impurity doped portion15A overlapping with the first active region13A, a second impurity doped portion15B overlapping with the second active region13B, and a diffusion barrier portion15C between the first impurity doped portion15A and the second impurity doped portions15B. The first impurity doped portion15A may further include an extension portion15AE partially overlapping the isolation region12. The second impurity doped portion15B may further include an extension portion15BE partially overlapping the isolation region12. A gate dielectric layer14may be formed between the gate layer15and the substrate11.

FIG. 5is a perspective view illustrating yet another example of the semiconductor device in accordance with an embodiment of the present invention.

Referring toFIG. 5, a substrate11may include a first active region13A, a second active region13B, and an isolation region12positioned between the first active region13A and the second active region13B. Also, a fin pattern F may be formed in a gate region of the substrate11. The fin pattern F may be formed to cross over the first active region13A, the second active region13B, and the isolation region12. Also, a gate layer15covering the upper portion of the fin pattern F and crossing over the first active region13A, the second active region13B, and the isolation region12may be formed. The gate layer15may include a first impurity doped portion15A overlapping with the first active region13A, a second impurity doped portion15B overlapping with the second active region13B, and a diffusion barrier portion15C between the first impurity doped portion15A and the second impurity doped portions15B. The first impurity doped portion15A may further include an extension portion15AE partially overlapping the isolation region12. The second impurity doped portion15B may further include an extension portion15BE partially overlapping the isolation region12. A gate dielectric layer14may be formed between the gate layer15and the substrate11.

The first and second impurity doped regions15A,15B may cover the top surface and side surfaces of the fin region F of the respective first and second active regions13A and13B. The first and second impurity doped regions15A,15B may extend laterally away from the sides of the fin region F to cover a portion of the respective first and second active regions13A and13B.

According to an embodiment of the present invention, the reliability of a semiconductor device may be improved by preventing deterioration in the performance of a transistor.