Pin device and manufacturing method thereof, photosensitive device and display device

A PIN device includes: a first doped layer, a second doped layer, and an intrinsic layer between the first doped layer and the second doped layer, where the second doped layer includes a body portion and an electric field isolating portion at least partially enclosing the body portion; and the electric field isolating portion is doped differently from the body portion.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is the U.S. national phase of PCT Patent Application No. PCT/CN2019/126653 filed on Dec. 19, 2019, which claims the priority of Chinese Patent Application No. 201910233511.0, filed on Mar. 26, 2019, the entire content of both of which is incorporated herein by reference in their entirety for all purposes.

FIELD

The disclosure relates to the field of optoelectronic technology, and in particular but not limited to a PIN device, a manufacturing method thereof, a photosensitive device, and a display device.

BACKGROUND

A PIN device is a device with an un-doped intrinsic semiconductor region between a p-type semiconductor region and an n-type semiconductor region. The p-type and n-type regions are typically heavily doped because they are used for ohmic contacts.

The PIN device is the core electronic component of optical fingerprint recognition device and X-ray flat panel detector, and its photoelectric performance directly restricts the performance of the whole system.

SUMMARY

Embodiments of the present disclosure provide a PIN device and a manufacturing method thereof, a photosensitive device, and a display device.

According to a first aspect of the present disclosure, there is provided a PIN device, including: a first doped layer, a second doped layer, and an intrinsic layer between the first doped layer and the second doped layer, where the second doped layer includes a body portion and an electric field isolating portion at least partially enclosing the body portion; and the electric field isolating portion is doped differently from the body portion.

According to a second aspect of the present disclosure, there is provided a method of manufacturing a PIN device, including: forming a first doped layer, and an intrinsic layer on the first doped layer; forming a second doped layer on the intrinsic layer, the second doped layer including: a body portion and an electric field isolating portion at least partially enclosing the body portion; and further doping the electric field isolating portion such that the electric field isolating portion is doped differently from the body portion.

According to a third aspect of the present disclosure, there is provided a photosensitive device, including: a substrate; a thin film transistor on the substrate; and at least one of a PIN device which includes: a first doped layer, a second doped layer, and an intrinsic layer between the first doped layer and the second doped layer, where the second doped layer includes a body portion and an electric field isolating portion at least partially enclosing the body portion; and the electric field isolating portion is doped differently from the body portion.

DETAILED DESCRIPTION

The disclosure will be described hereinafter with reference to the accompanying drawings, which illustrate embodiments of the disclosure. The described embodiments are only exemplary embodiments of the present disclosure, but not all embodiments. Other variations may be derivable by a person of ordinary skill in the art based on the embodiments of the present disclosure without creative efforts, and are within the scope of the present disclosure.

References throughout the disclosure to “one embodiment”, “an embodiment”, “an example”, “some embodiments”, or similar language mean that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment. Thus, appearances of the phrases “in one embodiment”, “in an embodiment”, “in some embodiments”, and similar language throughout the disclosure may, but do not necessarily, all refer to the same embodiment(s), but mean “one or more embodiments”. These may or may not include all the embodiments disclosed. Accordingly, features or elements of some embodiments may be available in some other embodiments unless the context indicates otherwise.

Unless otherwise defined, technical terms or scientific terms used in the embodiments of the present disclosure should be construed in the ordinary meaning of the person of ordinary skill in the art.

The terms “first”, “second” and similar terms used in the present disclosure do not denote any order, quantity, or importance. They are merely used for references to relevant devices, components, procedural steps, etc. These terms do not imply any spatial or chronological orders, unless expressly specified otherwise. For example, a “first device” and a “second device” may refer to two separately formed devices, or two parts or components of the same device. In some cases, for example, a “first device” and a “second device” may be identical, and may be named arbitrarily. Similarly, a “first step” of a method or process may be carried or performed before, after, or simultaneously with, a “second step”.

The terms “comprising”, “including”, “having”, and variations thereof mean “including but not limited to”, unless expressly specified otherwise.

An enumerated listing of items does not imply that any or all of the items are mutually exclusive, unless expressly specified otherwise. The terms “a”, “an”, and “the” also refer to “one or more” unless expressly specified otherwise.

The words “connected” or “connection” and the like are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect.

The words “above”, “below”, “under”, “upper”, “lower”, “left”, “right”, etc., may be used to refer to relative positions of an element under normal operation mode or installation orientation, to facilitate understanding of the relevant embodiments. The scope of the disclosure is not limited to the specific operation mode or installation orientation as described.

The steps illustrated in the flowcharts of the drawings may be executed by a computer system such as a set of computer executable instructions. Although logical sequences are shown in the flowcharts, in some cases, the steps shown or described may be performed in a different order than the ones described herein.

The drawings of the present disclosure relate only to structures involved in the present disclosure, and other structures may refer to the usual design.

In the drawings used to describe the embodiments of the present disclosure, the thickness and size of layers or microstructures are exaggerated. It will be understood that when an element such as a layer, a film, a region or a substrate is referred to as being “on” or “below” another element, the element may be “directly on” or “directly below” the another element, or there may be intermediate elements.

According to some studies, certain damage may be caused to sidewall of a PIN device during the manufacturing process, resulting in an increase in dark current in the PIN device, thereby reducing the switching ratio and performance of the PIN device.

Embodiments of the present disclosure provide a PIN device and a manufacturing method thereof, a photosensitive device, and a display device, which can reduce the increase in the dark current due to the damage of the sidewall of the PIN device, thereby improving the switching ratio and performance of the PIN device.

Some embodiments of the present disclosure provide a PIN device.FIG.1is a schematic diagram showing a structure of a PIN device, andFIG.2is a top view of a second doped layer of the PIN device. As shown inFIG.1andFIG.2, the PIN device according to some embodiments of the present disclosure includes a first electrode10, a first doped layer20, an intrinsic layer30, a second doped layer40, and a second electrode50, which are sequentially disposed.

The second doped layer40includes a body portion41and an electric field isolating portion42disposed in a same layer, and the electric field isolating portion42at least partially encloses, or surrounds, the body portion41to isolate an electric field which would be formed on the sidewall of the PIN device due to damage caused during the manufacturing process.

The electric field isolating portion42may partially surround the body portion41, or completely surround the body portion41. For example,FIG.2shows an example in which the electric field isolating portion42encloses the entire body portion41. The electric field isolating portion42directly contacts with the body portion41.

As shown inFIG.1, the orthographic projections of the first doped layer20, the intrinsic layer30and the second doped layer40on the lower electrode10coincide. The orthographic projection of the body portion41on the lower electrode10is separated from, or does not overlap with, the orthographic projection of the electric field isolating portion42on the lower electrode10. The orthographic projection of the electric field isolating portion42on the lower electrode10does not overlap with the orthographic projection of the upper electrode50on the lower electrode10, that is, the upper electrode50(i.e. the second electrode) does not cover the electric field isolation portion42. The area of the lower electrode10is greater than or equal to the area of the first doped layer20, that is, if the PIN device is disposed on a substrate, the orthographic projection of the lower electrode10on the substrate completely covers the orthographic projection of the first doped layer20on the substrate.

Optionally, the first doped layer20may be a p-type semiconductor layer, or it may be an n-type semiconductor layer. Optionally, the first doped layer20may have a thickness of 200-700 angstroms.

Optionally, the intrinsic layer30may be an intrinsic amorphous silicon layer or an intrinsic germanium layer, etc. The intrinsic layer30may have a thickness of 5000 to 15000 angstroms. It should be noted that the doping concentration of the intrinsic layer30may be very low, so that the absorption coefficient of the intrinsic layer30is small, and the light incident on the intrinsic layer may easily enter and be sufficiently absorbed to generate a large number of electron-hole pairs. Therefore, it may achieve a high photoelectric conversion efficiency.

Optionally, the body portion41may be a p-type semiconductor layer. It may also be an n-type semiconductor layer. When the first doped layer20is a p-type semiconductor layer, the body portion41is an n-type semiconductor layer; when the first doped layer20is an n-type semiconductor layer, the body portion41is a p-type semiconductor layer.

The thickness of the body portion41and the electric field isolating portion42may be the same. The second doped layer40may have a thickness of 200 to 700 angstroms.

In the embodiment, the body portion41is configured to cooperate with the upper electrode50, the lower electrode10, the first doped layer20, and the intrinsic layer30to form a built-in electric field of the PIN device. In the embodiment, since the electric field isolating portion41at least partially encloses the body portion, the built-in electric field of the PIN device may be shrunk, which in turn is able to isolate the sidewall electric field that would be formed in the PIN device. Therefore, it may significantly reduce the dark current due to the damage of the sidewall of the PIN device, and in some cases, the reduction is at least by an order of magnitude.

In the embodiment, the working principle of the PIN device is that the intrinsic layer30is used to generate a large number of electron-hole pairs after absorbing incident light. Under the effect of a strong electric field, the electrons of the electron-hole pairs in the intrinsic layer drift toward the n-type semiconductor layer, and the holes drift toward the p-type semiconductor layer, thereby forming a photocurrent and converting an optical signal into an electrical signal.

According to the embodiment of the present disclosure, there is provided a PIN device, the PIN device including: a lower electrode, a first doped layer, an intrinsic layer, a second doped layer, and an upper electrode disposed in sequence; and the second doped layer includes: a body portion and an electric field isolating portion disposed in the same layer, the electric field isolating portion at least partially enclosing or surrounding the body portion to isolate an electric field formed on a sidewall of the PIN device.

In the embodiment, the electric field isolating portion of the second doped layer at least partially surrounding the body portion is capable of isolating an electric field formed on the sidewall of the PIN device, thereby reducing a dark current increase due to damages or defects on the sidewall of the PIN device and improving the switching ratio and performance of the PIN device.

According to some embodiments of the present disclosure, a PIN device includes a first doped layer20, a second doped layer40, and an intrinsic layer30between the first doped layer20and the second doped layer40; the second doped layer includes a body portion41and an electric field isolating portion42at least partially enclosing the body portion41; and the electric field isolating portion42is doped differently from the body portion41of the second doped layer40.

The electric field isolating portion42may be reversely doped with respect to the body portion41to isolate the electric field formed on the sidewall of the PIN device. The electric field isolating portion42may have an effective concentration of dopants higher than that of the first doped layer20. The electric field isolating portion42may have an effective concentration of dopants higher than that of the body portion41.

FIG.3is a schematic diagram showing a structure of a PIN device according to some embodiments of the present disclosure.FIG.4is a top view of the PIN device. The electric field isolating portion42includes a first doped portion43(i.e. a first further doped portion) and a second doped portion44(i.e. a second further doped portion) disposed in the same layer; the first doped portion43at least partially surrounds or partially encloses the body portion41, and the second doped portion44at least partially surrounds or encloses the first doped portion43. The first further doped portion43directly contacts with the body portion41.

The first doped portion43may partially surround the body portion41, or it may completely surround the body portion41. For example,FIG.3illustrates an example in which the first doped portion43entirely surrounds, or encloses the body portion41. The disclosure does not limit to this. The second doped portion44may partially surround the first doped portion43, or it may completely surround the first doped portion43. As illustrated inFIG.3as an example, the second doped portion44entirely surrounds, or encloses the first doped portion43. The present disclosure does not limit to this.

In the embodiment, as shown inFIG.3andFIG.4, there is no overlapping area between the orthographic projection of the body portion41on the lower electrode10and the orthographic projection of the first doped portion43on the lower electrode10. There is no overlap between the orthographic projection of the body portion41on the lower electrode10and the orthographic projection of the second doped portion44on the lower electrode10. There is also no overlapping area between the orthographic projection of the first doped portion43on the lower electrode10and the orthographic projection of the second doped portion44on the lower electrode10.

In order to ensure that the built-in electric field of the PIN device is not affected by the electric field isolating portion, as shown inFIG.3, the orthographic projection of the body portion41on the lower electrode10in the embodiment covers the orthographic projection of the upper electrode50on the lower electrode10.FIG.4is an example in which the orthographic projection of the body portion41on the lower electrode10completely overlaps with the orthographic projection of the upper electrode50on the lower electrode10.

In an embodiment, the first doped layer20is an n-type semiconductor layer; the body portion41and the first doped portion43are p-type semiconductor layers; and the second doped portion44is an n-type semiconductor layer. That is, the second doped portion44is reversely doped with respect to the body portion41. The hole concentration of the first doped portion43is greater than the hole concentration of the doped body portion41, and the free electron concentration of the second doped portion44is greater than the free electron concentration of the first doped layer20.

In another embodiment, the first doped layer20is a p-type semiconductor layer; the body portion41and the first doped portion43are n-type semiconductor layers; and the second doped portion44is a p-type semiconductor layer. That is, the second doped portion44is reversely doped with respect to the body portion41. The free electron concentration of the first doped portion43is greater than the free electron concentration of the body portion41, and the hole concentration of the second doped portion44is greater than the hole concentration of the first doped layer20.

That is, the second doped portion44has an effective concentration of dopants higher than that of the first doped layer20; the first doped portion43is reversely doped with respect to the second doped portion44, and has an effective concentration of dopants higher than that of the body portion41; and the second doped portion44has an effective concentration of dopants higher than that of the body portion41.

In another example, the first doped portion43may be reversely doped with respect to the second further doped portion44, and may have an effective concentration of dopants approximately equal to zero.

FIG.5is a schematic diagram illustrating electric fields of a PIN device according to some embodiments of the present disclosure. As shown inFIG.5, the intrinsic layer30includes: a first region A1and a second region A2. The orthographic projection of A1on the lower electrode10coincides with the orthographic projection of the body portion41on the lower electrode10, and the orthographic projection of the second region A2on the lower electrode10coincides with the orthographic projections of the first doped portion43and the second doped portion44on the lower electrode10.

As shown inFIG.5, in the embodiment, a first electric field E1is formed in the first region A1under the effects of the upper electrode50and the lower electrode10, that is, the built-in electric field of the PIN device; and a second electric field E2is formed in the second region A2under the effects of the first doped portion43and the second doped portion44. The second electric field E2isolates an electric field formed on the sidewall AA of the PIN device from the first electric field E1.

It should be noted that in the example shown inFIG.5, the first doped layer20is an n-type semiconductor layer; the body portion41and the first doped portion43are p-type semiconductor layers; and the second doped portion44is an n-type semiconductor layer.

In the embodiment, the second doped portion44has a higher free electron concentration, which corresponds to a negative electrode; and the first doped portion43has a higher hole concentration, corresponding to a positive electrode. Even there are no electrodes in contact with the first doped portion43and the second doped portion44, the first doped portion43and the second doped portion44may form the second electric field E2in the second region A2with an upward field direction, i.e. the direction of the second electric field E2is from bottom to top as shown inFIG.5. Since the first doped layer20is an n-type semiconductor layer and the body portion41is a p-type semiconductor layer, under the effect of the upper electrode and the lower electrode, the direction of the first electric field E1formed is downward, i.e. from top to bottom. The first electric field E1and the second electric field E2are in opposite directions.

In another embodiment, the first doped layer20is a p-type semiconductor layer; the body portion41and the first doped portion43are n-type semiconductor layers; and the second doped portion44is a p-type semiconductor layer. Here, the first doped portion43has a higher free electron concentration, which corresponds to a negative electrode, and the second doped portion44has a higher hole concentration, corresponding to a positive electrode. Even there are no electrodes on the first doped portion43and the second doped portion, the first doped portion43and the second doped portion44may form a second electric field E2in the second region A2with a downward field direction, i.e. the direction of the second electric field E2is from top to bottom. Since the first doped layer20is a p-type semiconductor layer and the body portion41is an n-type semiconductor layer, under the effect of the upper electrode and the lower electrode, the direction of the first electric field E1formed is upward, i.e. from bottom to top. The electric field direction of the first electric field E1is opposite to the electric field direction of the second electric field E2.

It should be noted that the field intensity of the first electric field E1depends on the voltages applied to the upper electrode and the lower electrode, and the field intensity of the second electric field E2depends on the amount and depth of the doping materials doped in the first doped portion and the second doped portion. The details may be determined based on actual requirements, and the present disclosure does not limit this.

In the embodiment of the present disclosure, by including the first doped portion43and the second doped portion44in the second doped layer40, the second electric filed for isolating electric fields inside the PIN device can be formed in the second region A2of the intrinsic layer30, thereby isolating the electric field of the sidewall of the PIN device from the first electric field. The field directions of the first electric field and the second electric field are opposite. Since the dark current direction is consistent with the direction of the electric field, the dark current directions of the first electric field and the second electric field are also opposite, and thus the dark current of the second electric field can neutralize the dark current of the first electric field, thereby further reducing the dark current in the PIN device such that the dark current in the PIN device can be reduced by more than an order of magnitude. For example, there is data indicating that the dark current level of the PIN device is 10e−13amps when the second electric field is not formed, and the dark current level is reduced to 10e−14˜10e−15amps when the second electric field is formed.

Optionally,FIG.6is a schematic structural diagram of the lower electrode according to an embodiment of the present disclosure. As shown inFIG.6, the lower electrode10includes a first protective layer11, a second protective layer13and a metal layer12disposed between the first protective layer11and the second protective layer13, in which the second protective layer13is located on a side of the first protective layer11away from the first doped layer20.

Optionally, the material of the first protective layer11and the second protective layer13includes: molybdenum or titanium.

Optionally, the material of metal layer12includes copper, aluminum or aluminum telluride.

The lower electrode in the embodiment has a three-layer structure including a first protective layer, a second protective layer, and a metal layer therebetween, such that the metal layer is protected from the upper and lower sides. The present disclosure does not specifically limit this.

The lower electrode10is a planar electrode in the example. The shape and size of the planar electrode are not specifically limited by the example, and may be determined according to the actual requirements.

Optionally, the upper electrode50is made of a transparent conductive material, for example, indium tin oxide. The upper electrode50is a planar electrode in the example. The shape and size of the planar electrode are not specifically limited by the example, and may be determined according to actual requirements.

Some embodiments of the present disclosure also provide a method of manufacturing a PIN device.FIG.7is a flowchart of a method of manufacturing a PIN device according to an embodiment of the present disclosure. As shown inFIG.7, the method of manufacturing the PIN device according to the embodiment of the present disclosure includes the following steps.

Step S1: forming a first doped layer, and an intrinsic layer on the first doped layer.

The first doped layer may be formed by patterning a first doped semiconductor film; and the intrinsic layer may be formed by depositing an intrinsic semiconductor film on the first doped layer, and patterning the intrinsic semiconductor film.

Step S2: forming a second doped layer on the intrinsic layer.

The second doped layer includes: a body portion and an electric field isolating portion at least partially enclosing the body portion. The second doped layer may be formed by depositing a second doped semiconductor film on the intrinsic layer, and patterning the second doped semiconductor film.

The first doped semiconductor film, the intrinsic semiconductor film, and the second doped semiconductor film may be deposited by a sputtering process.

Step S3: further doping the electric field isolating portion such that the electric field isolating portion is doped differently from the body portion.

The method of manufacturing the PIN device may further include providing a substrate; and forming a first electrode or a lower electrode on the substrate.

The first electrode is a planar electrode, for example.

The first doped layer is formed on the first electrode; and the first electrode includes a first protective film, a metal film, and a second protective film.

The method may further include: forming a conductive layer on the second doped layer; patterning the conductive layer to form a second electrode covering the body portion of the second doped layer, and exposing the electric field isolating portion of the second doped layer; doping the electric field isolating portion of the second doped layer with a dopant different from that of the body portion (i.e. a dopant of a different type, for example, p-type dopant or n-type dopant). Doping the electric field isolating portion may include masking a first portion of the electric field isolating portion, and doping the electric field isolating portion with a dopant different from that of the body portion to form a second further doped portion; and masking a second portion of the electric field isolating portion, and doping the electric field isolating portion with a dopant same as (i.e. a dopant of a same type) that of the body portion to form a first further doped portion.

The second electrode may be made of a transparent material.

According to some embodiments of the present disclosure, another method of manufacturing a PIN device includes:

Step S10: forming a lower electrode.

The lower electrode is a planar electrode, for example.

Forming the lower electrode includes: depositing a first protective film, a metal film and a second protective film respectively, and forming a lower electrode including a first protective layer, a metal layer and a second protective layer by a patterning process.

It should be noted that the patterning process includes photoresist coating, exposure, development, etching, photoresist stripping and the like.

Step S20: forming a first doped layer, an intrinsic layer, a second doped layer, and an upper electrode on the lower electrode.

The second doped layer includes: a body portion and an electric field isolating portion disposed in the same layer, the electric filed isolating portion at least partially enclosing or surrounding the body portion to isolate an electric field formed on a sidewall of the PIN device.

The upper electrode is a planar electrode.

The step S20includes: depositing a first doped semiconductor film on the lower electrode, and forming a first doped layer by a patterning process; depositing an intrinsic semiconductor film on the first doped layer, and forming an intrinsic layer by a patterning process; depositing a second doped semiconductor film on the intrinsic layer, and forming a doped body layer by a patterning process; depositing a transparent conductive film on the doped body layer, and forming an upper electrode by a patterning process; doping in the doped body layer a first sub-doped material and a second sub-doped material to form a second doped layer including a body portion, a first doped portion, and a second doped portion.

The first doped semiconductor film, the intrinsic semiconductor film, and the second doped semiconductor film may be deposited by a sputtering process.

The method for manufacturing a PIN device according to the embodiment of the present disclosure includes: forming a lower electrode; forming a first doped layer, an intrinsic layer, a second doped layer, and an upper electrode on the lower electrode; and the second doped layer includes: a body portion and an electric field isolating portion disposed in a same layer, the electric field isolating portion at least partially enclosing or surrounding the body portion to isolate an electric field formed on a sidewall of the PIN device. In the embodiments of the present disclosure, the electric field isolating portion at least partially surrounding the body portion included in the second doped layer is capable of isolating the electric field formed on the sidewall of the PIN device, thereby reducing the dark current increase due to the damage of the sidewall of the PIN device, and improving the switching ratio and performance of the PIN device.

Taking the first doped layer as the n-type semiconductor layer as an example and with reference toFIG.8toFIG.11, a method for manufacturing the PIN device according to an embodiment of the present disclosure includes the following steps.

Step100: forming sequentially a lower electrode10, a first doped layer20, and an intrinsic layer30, as shown inFIG.8.

Step200: depositing a p-type semiconductor material on the intrinsic layer30, and forming a doped body layer45by a patterning process, as shown inFIG.9.

Step300: depositing a transparent conductive material on the doped body layer45, and forming an upper electrode50by a patterning process, as shown inFIG.10.

The orthographic projection of the upper electrode50on the intrinsic layer30is covered by the orthographic projection of the lower electrode10on the intrinsic layer30.

Step400: doping the doped body layer45with a first sub-doped material to form a body portion41and a first doped portion43at least partially surrounding or enclosing the body portion41, as shown inFIG.11.

The first doped portion43is a p-type semiconductor layer, and the hole concentration of the first doped portion43is greater than the hole concentration of the body portion41.

Step500: doping the doped body layer45with a second sub-doped material to form a second doped portion44at least partially surrounding or enclosing the first doped portion43, as shown inFIG.3.

The second doped portion44is an n-type semiconductor layer, and the free electron concentration of the second doped portion44is greater than the free electron concentration of the first doped layer20.

It should be noted that when the first doped layer20is a p-type semiconductor layer, the body portion41is an n-type semiconductor layer, the first doped portion43is an n-type semiconductor layer, and the second doped portion44is a p-type semiconductor layer. The manufacturing method is similar to the above, and will not be described here.

Some embodiments of the present disclosure also provide a photosensitive device PD.FIG.12is a schematic structural diagram of the photosensitive device PD according to an embodiment of the present disclosure. As shown inFIG.12, the photosensitive device PD includes: a substrate1, a thin film transistor2and the PIN device3provided on the substrate1. A protection layer5may be provided to surround the PIN device3and a planarization layer6may be provided to smooth a surface of the photosensitive device. The second electrode of the PIN device is connected to a bias line7to receive a bias voltage.

The thin film transistor2includes: a gate electrode21, a gate insulating layer22, an active layer23, a buffer layer24, an interlayer insulating layer25, a source electrode26, a drain electrode27, and a passivation layer28. The thin film transistor may have a top gate structure or a bottom gate structure. A top gate structure is shown inFIG.12as an example.

The first electrode10of the PIN device3is connected to the drain electrode27of the thin film transistor2.

Optionally, the photosensitive device can be used in various applications, for example, to form an imaging element or the like, to implement a touch function or a fingerprint recognition function based on the principle of photo-sensing, etc. For example, the above functions may be integrated in a display panel by micro-nano electronic process technology, thereby obtaining a display panel with a touch function, a display panel having a fingerprint recognition function, or the like. The photosensitive device may also be used in an X-ray flat panel sensor.

Some embodiments of the present disclosure further provide a display device including the photosensitive device.

Optionally, the display device may be a liquid crystal display, or an Organic Light-Emitting Diode (OLED) display device.

The display device may be any product or component having a display function, such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, and the like.

Various embodiments and/or examples are disclosed to provide exemplary and explanatory information to enable a person of ordinary skill in the art to put the disclosure into practice. Features or components disclosed with reference to one embodiment or example are also applicable to all embodiments or examples unless specifically indicated otherwise.

Although the disclosure is described in combination with specific embodiments, it is to be understood by the person skilled in the art that many changes and modifications may be made and equivalent replacements may be made to the components without departing from a scope of the disclosure. Embodiments may be practiced in other specific forms. The described embodiments are to be considered in all respects only as illustrative and not restrictive.