Guard ring structure for a Schottky diode

A Schottky device having a substrate layer of a first conductivity type having a surface, and a guard ring formed over the surface of the substrate layer and also surrounding a barrier region of the substrate layer. The guard ring has a gate of a second conductivity type disposed over a dielectric layer. A metal can be formed over the barrier region to form a Schottky junction.

TECHNICAL FIELD

The present invention relates generally to processes for the manufacture of semiconductor devices and, more particularly, to the formation of a guard ring structure for a Schottky diode.

BACKGROUND OF THE INVENTION

Schottky diodes have been used for many years in the semiconductor industry in, for example, electronic systems, such as amplifiers, receivers, control and guidance systems, power and signal monitors, and as rectifiers and clamps in RF circuits. Commercial applications include radiation detectors, imaging devices, and wired and wireless communications products. A Schottky diode can be formed by the connection of a metal or silicide layer to a doped semiconductor layer. A Schottky junction (or Schottky barrier) is formed at the junction of the metal layer and the doped semiconductor layer.

Schottky diodes are prone to high electric field regions at the ion implant regions where the metal or silicide of the diode structure meets the isolation structure. Typically, these electric field regions prohibit the diode from performing at its optimum characteristic level. Parameters that are adversely affected by this field include the reverse bias leakage current and breakdown voltage.

Current approaches at eliminating the high electric field regions near the isolation barrier consist of adding a pn diode guard ring at the edge of the isolation structure. In the case of an n-type Schottky diode, the p-type guard rings are implanted into the n-type regions at the perimeter of the Schottky contact region. This provides for a better diode; however, it increases the capacitance of the device and adds a minority carrier injection mechanism into the device, which in turn increases the diode recovery time. Additionally, fabrication of such a guard ring typically requires an additional masking step.

SUMMARY OF THE INVENTION

The present invention relates to a Schottky device and a fabrication method for the Schottky device. The Schottky device includes a semiconductor substrate of a first conductivity type and a metal in contact with the semiconductor substrate. The metal and the semiconductor substrate can form a Schottky junction. A guard ring structure can be formed on the semiconductor substrate that surrounds the Schottky junction. The guard ring structure comprises a gate of a second conductivity type that overlies a gate dielectric layer. The gate and the gate dielectric form a metal oxide semiconductor (MOS) structure with the semiconductor substrate that surrounds the Schottky junction. The MOS structure creates a MOS depletion region under the gate dielectric. The MOS depletion region mitigates perimeter edge effects at the edges of the Schottky junction that are due to the high electric field generated by the curved depletion boundary.

DETAILED DESCRIPTION

In describing the embodiments of the present invention, reference will be made herein toFIGS. 1-13of the drawings in which like numerals refer to like features of the invention. Features of the invention are not necessarily shown to scale in the drawings.

The present invention relates generally to a Schottky device and a fabrication method for the Schottky device. The Schottky device includes a semiconductor substrate of a first conductivity type and a metal in contact with the semiconductor substrate. The metal and the semiconductor substrate can form a Schottky junction or a Schottky barrier. After the metal is placed on a surface of the semiconductor substrate, charge can be exchanged to equilibrate the Fermi energy. Since the semiconductor substrate contains substantially less charge than the metal, the donor state is empty producing a depleted region with a curved depletion boundary below the metal in the semiconductor substrate.

A guard ring structure can be formed on the semiconductor substrate that surrounds the Schottky junction. The guard ring structure comprises a gate of a second conductivity type that overlies a gate dielectric. The gate and the gate dielectric form a metal oxide semiconductor (MOS) structure with the semiconductor substrate that generally surrounds the Schottky junction. The MOS structure forms a MOS depletion region under the gate dielectric. The MOS depletion region mitigates perimeter edge effects at the edges of the Schottky junction that are due to the high electric field generated by the curved depletion boundary. Mitigation of the perimeter edge effects can increase the breakdown voltage of the Schottky device and improve the leakage characteristics of the Schottky junction.

FIG. 1illustrates a schematic cross-sectional view of a Schottky device10in accordance with an aspect of the invention. The Schottky device10can be formed of a semiconductor substrate12having embedded therein an n-well14. The semiconductor substrate12can be a p-type semiconductor material and the n-well14can be formed in the p-type semiconductor material, for example, by implanting an n-type dopant, such as phosphorous (P), in the p-type semiconductor substrate12. It is to be appreciated that the Schottky device10is provided for illustrative purposes and that the semiconductor substrate12can include a plurality of Schottky devices and other integrated circuit devices.

The Schottky device10can include an isolation region16that is formed in the semiconductor substrate12. The isolation region16can be recessed in the semiconductor substrate12so that the isolation region16does not extend substantially above a surface18of the semiconductor substrate12. The isolation region16can define a perimeter that provides some isolation between the Schottky10and other semiconductor devices that can potentially be formed on or in the semiconductor substrate12. The isolation region16can also define an n-moat region20within the semiconductor substrate12. The n-moat region20comprises the active region of the Schottky device10. The isolation region16can comprise shallow trench isolation structures (STI) that are formed in the semiconductor substrate by any known process, such as etching the substrate and depositing a recessed oxide (ROX) for isolation. Although an STI structure is illustrated inFIG. 1, other isolation structures may be used with the present invention, such as field oxide structures.

A guard ring structure24can be formed at least partially over the isolation region16and the n-moat region20. The guard ring structure24surrounds a barrier region25of the semiconductor substrate. The term “ring” is conventionally used, and is used herein to describe generally any shape that generally surrounds the barrier region25to provide necessary isolation. Typically, this guard ring structure24is substantially circular or has a polygonal (e.g., rectangular) shape, although other shapes are possible.

The guard ring structure24includes a relatively thin gate dielectric layer26(e.g., having a uniform thickness between about 5 Å and about 500 Å) that can be formed (e.g., by thermal oxidation) over a portion the n-moat region adjacent the isolation region16. The gate dielectric layer26can be an oxide (e.g., silicon dioxide (SiO2)) or any other dielectric material suitable for use as an insulator in a MOS device. The guard ring structure24can also include a relatively thin gate28(e.g., having a uniform thickness between about 300 Å and about 700 Å). The thin gate28is thin to facilitate the formation of a continuous silicide from the thin gate28to the barrier region25. The gate28can comprise, for example, a polysilicon gate material or a re-crystallized polysilicon gate material that is doped with a p-type dopant (e.g., B11and BF2). The gate28can be formed (e.g., by chemical vapor deposition (CVD)) over the gate dielectric layer26and at least part of the isolation region16. The gate28has an inner side surface30, an outer side surface32, and a top surface34that interconnects the inner side surface30and the outer side surface32. The inner side surface30can have a substantially undulating shape (not shown) with a plurality of protrusions (not shown) that can extend into the barrier region25and/or a plurality of grooves that extend into the inner side surface30. The undulating shape of the inner side surface30mitigates formation of a sidewall spacer along the inner side surface30of the gate28in the vicinity of sharp protrusions.

The gate28, the gate dielectric layer26, and the semiconductor substrate12can form a MOS structure. The MOS structure can create MOS depletion region29under the gate dielectric26, that mitigates MOS capacitance as well as perimeter edge effects, which are due to a high electric field generated by a Schottky junction of the Schottky device10. Mitigation of the perimeter edge effects can increase the breakdown voltage of the Schottky device10and improve the leakage characteristics of the Schottky junction.

The guard ring structure24can also include a sidewall spacer40. The sidewall spacer40can extend from the gate28over a portion of the isolation region16. The sidewall spacer40can contact the gate28substantially along the outer side surface32of the gate28. The sidewall spacer40can comprise a nitride material, such as silicon nitride (Si3N4). The sidewall spacer40can be formed by, for example, CVD of a silicon nitride material followed by dry plasma etching of the deposited silicon nitride.

A Schottky barrier metal layer50can cover the barrier region25and extend over the inner side surface30and the top surface34of the gate24. The Schottky barrier metal layer50can comprise a refractory metal that, when deposited (e.g., physical vapor deposition (PVD)) on the barrier region25of the semiconductor substrate12and the gate28, forms a silicide material upon high temperature (e.g., greater than about 800° C.) annealing. A first portion52of the Schottky barrier metal layer50overlying the barrier region25can form the Schottky junction with the barrier region25of the semiconductor substrate12. The Schottky junction can create a depletion region54that extends below the first portion52of the Schottky barrier metal layer50to the MOS depletion region29. A second portion56of the Schottky barrier metal layer50can form an ohmic contact surface over the inner side surface30and the top surface34of the gate24.

Contacts60(e.g., aluminum electrodes) to the Schottky barrier metal layer50can be formed (e.g., by CVD) over the guard ring structure24. The contacts60can form an ohmic contact with the second portion56of the Schottky barrier metal layer50. By forming the contacts60over the guard ring structure60instead of over the barrier region25, damage to the Schottky barrier metal layer50that could potentially occur during formation of the contacts60should not affect the Schottky junction and, hence, the performance of the Schottky device should not be adversely affected.

FIGS. 2-10illustrate a methodology of fabricating part of a Schottky device similar to the Schottky device of FIG.1. Referring toFIG. 2, an n-buried layer100can be formed in a p-type substrate layer12by an implanting process104that implants an n+ type dopant, such as phosphorous and/or arsenic, into the p-type substrate layer12. The p-type substrate layer12can be formed from a semiconductor material, such as silicon. The substrate layer12, however, could be formed from any material, such as gallium arsenide, germanium, silicon-germanium, epitaxial formations, silicon carbide, indium phosphide, silicon-on-insulator substrates (SOI), strained Si substrates, and/or other semiconductor substrate materials.

The implantation of the n+ type dopant can be performed, for example, using an ion implanter that accelerates the dopant ions (e.g., P) at a high energy (e.g., greater than about 200 keV). In an aspect of the invention, the n+ type buried layer100can be formed by implanting a phosphorous implant at doses of about 1×1013cm2to about 1×1015cm2at energies of about 850 keV to about 1200 keV.

FIG. 3illustrates an isolation region16in the substrate layer12following formation of the n+ type buried layer100. The isolation region16can define a perimeter of a moat region20where a Schottky junction can be formed. The isolation region16can provide some electrical isolation between the moat region20and adjacent regions to be used for the formation of additional semiconductor devices. The isolation region16can comprise a shallow trench isolation (STI) structure. The STI structure can be formed by etching (e.g., dry plasma etching) the substrate layer12, depositing (e.g., CVD) a recessed oxide (ROX), and polishing the deposited ROX using a chemical mechanical planarization (CMP) technique (e.g., trench oxide polish). The ROX can be, for example, SiO2or another suitable oxide material that can perform the operation associated with the isolation region. Those skilled in the art will understand and appreciate other deposition techniques that can be employed to grow an ROX, such as those identified above. It is to be further understood and appreciated that other materials could be employed to form the isolation region16and that other isolation structures may be used with the present invention.

FIG. 4illustrates that after formation of the isolation region16, an n-well114can be formed in the substrate layer12by an implanting process112that implants an n-type dopant, such as phosphorous and/or arsenic, into the substrate layer12. The n-well implant defines the background doping concentration of the moat region20.

The implantation of the n-well14can be performed, for example, using an ion implanter (not shown) that accelerates the dopant ions (e.g., P) at a high energy (e.g., about 350 to about 850 keV). In an aspect of the invention, the n-well14can be formed with multiple implants. The well implant can be a high-energy implant that forms a deep low resistance region in the n-well. This low resistance region keeps the voltage close to ground everywhere in the n-well14and helps prevent transient voltages from building up. The well implant may comprise a phosphorous implant at doses of about 2×1013cm2to about 9×1013cm2at energies of about 350 keV to about 850 keV.

FIG. 5illustrates a dielectric layer116formed over the n-well14and the isolation region16. The dielectric layer116can be formed by an oxidation process, which forms an oxidation layer (e.g., silicon dioxide (SiO2) layer). The dielectric layer116can have a thickness of about 5 Å to about 500 Å, and be formed by a wet and/or dry thermal oxidation process. Thermal oxidation is the standard method of forming a dielectric layer116having a thickness of about 5 Å to about 500 Å. It is to be appreciated that alternate methodologies besides thermal oxidation can be employed to form the dielectric layer116. For example, any suitable technique (e.g., plasma enhanced CVD, thermal enhanced CVD and spin on techniques) may be employed in forming the gate dielectric layer116.

Additionally, alternate materials can be employed to provide the dielectric layer116. The dielectric layer can comprise the same material as the isolation region16. The dielectric layer116can be, for example, SiO2or another suitable oxide material that can perform the operation associated with the dielectric layer116. Those skilled in the art will understand and appreciate appropriate types of deposition techniques that can be employed to grow suitable crystalline structures to form the dielectric layer116, such as those identified above. It is to be further understood and appreciated that other materials also could be employed to form the dielectric layer116.

FIG. 6illustrates a conductive layer118and a patterned photoresist layer120deposited over the dielectric layer116. The conductive layer118can have a thickness of about 300 Å to about 700 Å (e.g., about 500 Å). The conductive layer118can be doped with a p-type dopant, such as B11and BF2. If the conductive layer118is comprised of polysilicon, the conductive layer118may be formed using any suitable technique including CVD techniques, such as low-pressure CVD (LPCVD) or plasma enhanced CVD (PECVD). The polysilicon can be formed in a polycrystalline state or an amorphous state, which is later, converted to a crystalline state. If the conductive layer118is comprised of amorphous silicon or germanium, standard deposition techniques may be employed. After layer118is deposited, it can be implanted with a p-type dopant. To save patterning masks, and be able to use the p source/drain (PSD) implant, the implanted area can be patterned using the PSD mask. Lower gate dopant concentrations and conductivities can be achieved.

The patterned photoresist layer120can have a thickness suitable for carrying out the present invention. Accordingly, the thickness of the patterned photoresist layer120can vary in correspondence with the wavelength of radiation used to pattern the photoresist layer120. The patterned photoresist layer120can be formed by providing a photoresist layer over the conductive layer118via conventional spin-coating or spin casting deposition techniques. The photoresist layer can be etched (e.g., anisotropic reactive ion etching (RIE)) to provide the patterned photoresist layer120. A selective etch technique can be used to etch the photoresist layer at a relatively greater rate as compared to the rate of the underlying conductive layer118to provide the patterned photoresist layer120. The patterned photoresist layer120can be used as a mask to define an area of a gate of a guard ring structure during a subsequent etching processing. An inner surface121of the patterned photoresist layer120can have an undulating shape (not shown) so that when the gate is formed (e.g., by etching the conductive layer118and the dielectric layer116), an inner surface of the gate will have a substantially undulating shape.

FIG. 7illustrates an etching process130being performed to remove a portion of the conductive layer118and the dielectric layer116to form a gate28and gate dielectric21. Any suitable etch technique can be used to etch the conductive layer118and the dielectric layer116. For example, the conductive layer118and dielectric layer116can be anisotropically etched with a plasma gas(es), (e.g., carbon tetrafluoride (CF4) containing fluorine ions) in a commercially available etcher, such as a parallel plate RIE apparatus or, an electron cyclotron resonance (ECR) plasma reactor. Any combination of a wet or dry etch process can be employed to etch the conductive layer118and the dielectric layer116. In one aspect, a selective etch technique is used to etch the conductive layer118and the dielectric layer116at a relatively greater rate as compared to the rate of the patterned photoresist layer120.

Following formation of the gate28and gate dielectric26, the patterned photoresist layer120can be stripped off the gate28(e.g., Ultra-Violet (UV)/Ozone (O3)/Sulfuric Acid (H2SO4) and cleaned by wet chemical cleanup processes. Those skilled in the art would be familiar with a variety of different cleanup procedures that can be employed to clean the structure.

FIG. 8illustrates the substrate12after the patterned photoresist120has been removed. The gate28and gate dielectric26can form a guard ring structure24. The guard ring structure24can define a barrier region25in the moat region20for the formation of a Schottky junction (or Schottky barrier). The gate28and the gate dielectric26of the guard ring structure24can form a metal oxide semiconductor (MOS) structure. The MOS structure can create a MOS depletion region that mitigates perimeter edge effects of the Schottky junction. The gate28of the guard ring structure24can extend partially over the isolation region16and the moat20. The gate28can have an inner side surface30, an outer side surface32, and a top surface34that connects the inner side surface30and the outer side surface32. Referring toFIG. 9, which is a top plan view ofFIG. 8, the inner side surface30of the gate28can have a substantially undulating shape with a plurality of protrusions148that extend into the barrier region25and/or a plurality of grooves that extend into the side surface30. The protrusions148(or grooves) can mitigate formation of a sidewall spacer at the extremities of the protrusions on the inner side surface30of the gate28during subsequent processing.

FIG. 10illustrates that a sidewall spacer40can be formed, which contacts the outer side surface32of the gate28. The sidewall spacer40can extend laterally from the outer side surface32of the gate so that it overlies part of the isolation region16and the substrate layer12. The sidewall spacer40can comprise an insulating material, such as silicon dioxide or silicon nitride. It is to be further understood and appreciated the sidewall spacer40can comprise other materials. The sidewall spacer40can be formed by depositing a film of the insulating material over the guard ring structure24and moat region20using any suitable technique including CVD techniques, such as LPCVD or PECVD. Other deposition techniques, such as sputtering techniques can also be used. Following deposition of the film of insulating material, the film can be etched (e.g., anisotropic reactive ion etching (RIE)) to provide the sidewall spacer40on the outer side surface32of the gate28. For example, a silicon nitride film can be anisotropically etched with a plasma gas(es), (e.g., carbon tetrafluoride (CF4) containing fluorine ions) in a commercially available etcher, such as a parallel plate RIE apparatus or, an electron cyclotron resonance (ECR) plasma reactor. The film covering the protrusions148(FIG. 9) of the inner side surface30of the gate28can be readily etched from the extremities of the protrusions148to mitigate the formation of a sidewall spacer along the inner side surface30of the gate28.

FIG. 11illustrates that a Schottky barrier metal50can be deposited over the gate28and barrier region135. In this example, a continuous layer of the Schottky barrier metal50can be formed over the top surface34of the gate28, the inner side surface30of the gate28, and the barrier region25. The Schottky barrier metal layer50can form a Schottky junction with the substrate layer12of the barrier region25. The Schottky junction can create a depletion region54that extends under Schottky junction to the MOS depletion region29. The Schottky barrier metal50can also form a contact region over the gate28. The Schottky barrier metal can comprise a refractory metal that can be alloyed by a thermal anneal process (e.g., rapid thermal anneal (RTA) at a temperature greater than about 800° C.) with the silicon of the semiconductor substrate12and the polysilicon of the gate28to form a continuous silicide layer. Refractory metals typically do not react with oxides or nitrides so the refractory metals can be easily etched off the sidewall spacer40following alloying. Examples of metals that can be deposited and alloyed to form the silicide can include cobalt, molybdenum, platinum, tantalum, titanium, and tungsten. Other metals that can be deposited and alloyed with the silicon can also be used.

Following deposition of the Schottky barrier metal50to form the Schottky junction and the ohmic contact, contacts (not shown) to the Schottky barrier metal50can be formed. The contacts can be provided over the guard ring structure24. The contacts can be an electrode that is formed from a metal, such as aluminum, aluminum alloy, copper, copper alloy, tungsten by conventional deposition techniques. By forming the contact to the Schottky junction over the guard ring structure24, potential damage to the Schottky junction can be mitigated. The resultant structure is similar to the structure illustrated in FIG.1.

FIG. 12illustrates a schematic cross-sectional view of a Schottky device210in accordance with another aspect of the invention. The Schottky device210in accordance with this aspect can have a structure similar to the structure of the Schottky device10(FIG. 1) except that a guard ring structure of the Schottky device210(FIG. 12) comprises a plurality (e.g., at least two) of overlying (i.e., stacked) gates. The plurality of gates can be aligned so that a guard ring structure can be formed having a substantially stepped-shape. The thickness of the each of the gates can also be substantially less than the thickness of the gate28(FIG. 1) so that each gate has an inner side surface (i.e., edge) with a substantially reduced thickness compared to the inner side surface30of the gate28(FIG.1). The stepped-shape guard ring structure and the reduced inner side surface of each of the gates can mitigate formation of a nitride sidewall on the inner side surfaces of the gates by allowing nitride material, which is deposited on the gates during fabrication, to be more readily etched from the inner side surfaces of the gates compared to outer surfaces of the gates. The substantial absence of a sidewall on the inner side surface of gates can facilitate the formation of a continuous silicide layer from the gates to a barrier region.

Referring again toFIG. 12, the Schottky device210can be formed of a semiconductor substrate212having embedded therein an n-well214. The semiconductor substrate212can be a p-type semiconductor material and the n-well214can be formed in the p-type semiconductor material, for example, by implanting an n-type dopant, such as phosphorous (P), in the p-type semiconductor substrate212. It is to be appreciated that the Schottky device210is provided for illustrative purposes and that the semiconductor substrate212can include a plurality of Schottky devices and other integrated circuit devices.

The Schottky device210can include an isolation region216that is formed in the semiconductor substrate212. The isolation region can be recessed in the semiconductor substrate212so that the isolation region216does not extend substantially above a surface218of the semiconductor substrate212. The isolation region216can define a perimeter that provides some isolation between the Schottky device and other semiconductor devices that can potentially be formed on the semiconductor substrate212. The Schottky device210can also define an n-moat region220within the semiconductor substrate212. The n-moat region220comprises the active region of the Schottky device210. The isolation region216can comprise STI structures that are formed in the semiconductor substrate by any known process, such as etching the substrate and depositing a ROX for isolation. Although an STI structure is illustrated inFIG. 12, other isolation structures may be used with the present invention.

A guard ring structure224can be formed at least partially over the isolation region216and the n-moat region220. The guard ring structure224surrounds a barrier region225of the semiconductor substrate212. The guard ring structure224has a substantially stepped-shape structure that can facilitate formation of a continuous silicide over the guard ring structure224to the barrier region225.

The guard ring structure224includes a relatively thin gate dielectric layer226(e.g., having a uniform thickness between about 5 Å and about 500 Å) that can be formed (e.g., by thermal oxidation) over a portion the n-moat region220adjacent the isolation region216. The gate dielectric layer226can be an oxide (e.g., silicon dioxide (SiO2)) or any other dielectric material suitable for use as an insulator in a MOS device. The guard ring structure224can also include a first relatively thin gate228(e.g., having a uniform thickness between about 300 Å and about 700 Å). The first relatively thin gate can be formed (e.g., by CVD) over the gate dielectric layer226and at least part of the isolation region216. The first gate228can have an inner side surface230, an outer side surface232, and a top surface234that interconnects the inner side surface230and the outer side surface232. The inner side surface230can have a substantially undulating shape (not shown) with a plurality of protrusion (not shown) that can extend into the barrier region225. The undulating shape of the inner side surface230can mitigate formation of a sidewall spacer at the extremities of protrusions along the inner side surface230of the first gate228. The first gate228can comprise, for example, a polysilicon gate material or a re-crystallized polysilicon gate material that is doped with a p-type dopant (e.g., B11and BF2).

The guard ring structure224can also include a second relatively thin gate236(e.g., having a uniform thickness between about 300 Å and about 700 Å). The second relatively thin gate236can be formed (e.g., by CVD) over the first gate228. The second gate236can be substantially narrower than the first gate228and can be substantially aligned over the isolation region216to provide the substantially stepped-shape gate structure. The second gate236can have an inner side surface238, an outer side surface240, and a top surface242that interconnects the inner side surface238and the outer side surface240. The inner side surface238can have a substantially undulating shape (not shown) with a plurality of protrusion (not shown) that can extend into the first gate region234. The undulating shape of the inner side surface238can mitigate formation of a sidewall spacer at the extremities of protrusions along the inner side surface238of the second gate236. The second gate236can comprise, for example, a polysilicon gate material or a re-crystallized polysilicon gate material that is doped with a p-type dopant (e.g., B11and BF2).

It will be appreciated by one skilled in the art that additional gates (e.g., one or more additional gates) can be provided over the first gate228and the second gate236. These additional gates can form additional steps for the stepped-shape guard ring structure224. The additional steps can further mitigate the formation of a sidewall on the inner side surfaces of the gates and facilitate formation of a continuous silicide from the gates to the barrier region225.

The first gate228, the second gate236, the gate dielectric layer226, and the semiconductor substrate212can form a MOS structure. The MOS structure can create a MOS depletion region244under the gate dielectric226, that mitigates MOS capacitance as well as perimeter edge effects, which are due to a high electric field generated by a Schottky junction of the Schottky device210. Mitigation of the perimeter edge effects can increase the breakdown voltage of the Schottky device210and improve the leakage characteristics of the Schottky junction.

The guard ring structure224can also include a sidewall spacer260. The sidewall spacer260can extend from the gates236and238over a portion of the isolation barrier216. The sidewall spacer260can contact the gates228and236substantially along the outer side surfaces232and240of the gates228and236. The sidewall spacer260can comprise a nitride material, such as silicon nitride (Si3N4). The sidewall spacer260can be formed by, for example, by CVD of a silicon nitride material followed by dry plasma etching.

A Schottky barrier metal layer270can cover the barrier region225and extend over the inner side surface230and part of the top surface234of the first gate228and the inner side surface238and the top surface242of the second gate236. The Schottky barrier metal layer can comprise a refractory metal that when deposited (e.g., PVD) on the barrier region225of the semiconductor substrate212, the first gate228, and the second gate236forms a silicide material upon high temperature (e.g., greater than about 800° C.) annealing. A first portion272of the Schottky barrier metal layer270overlying barrier region225can form the Schottky junction (or Schottky barrier) with the barrier region225of the semiconductor substrate212. The Schottky junction can create a depletion region274that extends below the first portion272of the Schottky barrier metal layer270to the MOS depletion region244. A second portion276of the Schottky barrier metal layer270can provide a contact surface over the top surface242of the second gate236.

Contacts280(e.g., aluminum or tungsten electrodes) to the Schottky barrier metal layer270can be formed (e.g., by CVD) over the second gate236of the guard ring structure224. The contacts can form an ohmic contact with the second portion276of the Schottky barrier metal layer270. By forming the contacts280to the Schottky barrier metal layer270over the second gate236instead of the first gate228, damage that could potentially occur during formation of the contacts should not affect MOS structure and the Schottky junction and, hence, the performance of the Schottky device should not be adversely effected.

FIG. 13illustrates a schematic cross-sectional view of a Schottky device310in accordance with yet another aspect of the invention. The Schottky device310in accordance with this aspect can have a structure similar to the structure of the Schottky device10(FIG. 1) except that a sidewall can be provided on an inner side surface of a gate of a guard ring structure. Formation of a sidewall on the inner side surface of the gate can obviate the formation of a continuous silicided layer from the gate of the guard ring structure to a barrier region of the Schottky device. A contact can then be provided with the silicide overlying the barrier region as well as the silicide overlying the guard ring structure.

Referring again toFIG. 13, the Schottky device310can be formed of a semiconductor substrate312having embedded therein an n-well314. The semiconductor substrate312can be a p-type semiconductor material and the n-well314can be formed in the p-type semiconductor material, for example, by implanting an n-type dopant, such as phosphorous (P), in the p-type semiconductor substrate312. It is to be appreciated that the Schottky device310is provided for illustrative purposes and that the semiconductor substrate312can include a plurality of Schottky devices and other integrated circuit devices.

The Schottky device310can include an isolation region316that is formed in the semiconductor substrate312. The isolation region316can be recessed in the semiconductor substrate so that the isolation region does not extend substantially above a surface318of the semiconductor substrate312. The isolation region316can define a perimeter structure that provides some isolation between the Schottky device310and other semiconductor devices that can potentially be formed on the semiconductor substrate312. The isolation region316can also define an n-moat region320within the semiconductor substrate312. The n-moat region320comprises the active region of the Schottky device310. The isolation region316can comprise STI structures that are formed in the semiconductor substrate312by any known process, such as etching the substrate and depositing a ROX for isolation. Although an STI structure is illustrated inFIG. 13, other isolation structures may be used with the present invention.

A guard ring structure324can be formed at least partially over the isolation region316and the n-moat region320, which is defined by the isolation region316. The guard ring structure324surrounds a barrier region of the semiconductor substrate. The guard ring structure324includes a relatively thin gate dielectric layer326(e.g., having a uniform thickness between about 5 Å and about 500 Å) that can be formed (e.g., by thermal oxidation) over a portion of the n-moat region320adjacent the isolation region316. The gate dielectric layer326can be an oxide (e.g., silicon dioxide (SiO2)) or any other dielectric material suitable for use as an insulator in a MOS device.

The guard ring structure324can also include a relatively thin gate328(e.g., having a uniform thickness between about 300 Å and about 700 Å). The gate328can be formed (e.g., by chemical vapor deposition (CVD)) over the gate dielectric layer326and at least part of the isolation region316. The gate328has an inner side surface330, an outer side surface332, and a top surface334that interconnects the inner side surface330and the outer side surface332. The gate328can comprise, for example, a polysilicon gate material or a re-crystallized polysilicon gate material that is doped with a p-type dopant (e.g., B11and BF2).

The gate328, the gate dielectric layer326, and the semiconductor substrate312can form a MOS structure. The MOS structure can create a MOS depletion region344under the gate dielectric326, that mitigates MOS capacitance as well as perimeter edge effects, which are due to a high electric field generated by a Schottky junction of the Schottky device310. Mitigation of the perimeter edge effects can increase the breakdown voltage of the Schottky device310and improve the leakage characteristics of the Schottky junction.

The guard ring structure324can also include a first sidewall spacer340and a second sidewall spacer342. The first sidewall spacer340can extend from the gate328over a portion of the isolation barrier316. The first sidewall spacer340can contact the gate328substantially along the outer side surface332of the gate328. The second sidewall spacer342can extend from the gate328over a portion of the barrier region325. The second sidewall spacer342can contact the gate328substantially along the inner side surface330of the gate328. The second sidewall spacer342can be sized so that a depletion region created under the Schottky junction can extend under the sidewall spacer342to the MOS depletion region344. The first sidewall spacer340and the second sidewall spacer342can comprise a nitride material, such as silicon nitride (Si3N4). The sidewall spacers340and342can be formed by, for example, CVD of a silicon nitride material followed by dry plasma etching.

A Schottky barrier metal layer350can cover the barrier region325and the top surface334of the gate328. Unlike the previously described Schottky devices, the Schottky barrier metal layer does not extend over the inner side surface342of the gate328. The Schottky barrier metal layer350can comprise a refractory metal that when deposited (e.g., PVD) on the barrier region325of the semiconductor substrate312and the gate328forms a silicide material upon high temperature (e.g., greater than about 800° C.) annealing. A first portion352of the Schottky barrier metal layer350overlying the barrier region325can form the Schottky junction with the barrier region325of the semiconductor substrate312. The Schottky junction can create a depletion region360that extends below the first portion352of the Schottky barrier metal layer350to the MOS depletion region344. A second portion354of the Schottky barrier metal layer350can provide a contact surface over the top surface334of the gate328.

Contacts380(e.g., electrodes) to the Schottky barrier metal layer350can be formed (e.g., by CVD) over the guard ring structure324and the barrier region325. The contacts380can form ohmic contacts with the Schottky barrier metal layer350. It is desirable to form a contact over the barrier region325because the sidewall spacer342separates the first portion352of the Schottky barrier metal layer350from the second portion354of the metal layer350forming the silicide contact to the gate328.

Those skilled in the art will also understand and appreciate that variations in the processing operations can be utilized in the formation of a gate structure in accordance with an aspect of the present invention. For example, it is to be appreciated that a p-well can be formed in an n-type substrate material and that a gate of a guard ring structure can be doped with an n-type dopant. It is further to be appreciated that a plurality of Schottky devices can be formed on the semiconductor substrate. Moreover, it is to be appreciate that the Schottky device can be fabricated on a semiconductor substrate using conventional MOS processes. Additionally, it is to be appreciated that an additional mask can be provide during fabrication of the Schottky device to prevent formation of a sidewall space on the inner side surface of the gate.

What has been described above includes examples and implementations of the present invention. Because it is not possible to describe every conceivable combination of components, circuitry or methodologies for purposes of describing the present invention, one of ordinary skill in the art will recognize that many further combinations and permutations of the present invention are possible. Accordingly, the present invention is intended to embrace all such alterations, modifications and variations that fall within the spirit and scope of the appended claims.