MEMORY ASSEMBLY WITH PROCESSOR MATCHING PIN-OUT

A memory device includes one or more memory semiconductor chips housed in a surface-mount semiconductor package and formed on a package substrate. The package substrate includes a two-dimensional array of package leads for connecting signals of the one or more memory semiconductor chips to an external system. The memory assembly has a package pin-out being a mirror image of a memory interface pin-out of a processor. In other embodiments, a circuit module includes a printed circuit board, a processor mounted on a first side of the printed circuit board and a memory assembly mounted on a second, opposite side of the printed circuit board. The memory assembly has a memory assembly pin-out that is a mirror image of the memory interface pin-out of the processor and the memory assembly is positioned in direct alignment with the memory interface pin-out of the processor.

BACKGROUND OF THE INVENTION

Most ball grid array (BGA) packaged memory devices in the market today use a JEDEC standard pin-out. In the case of DRAM devices, the standard JEDEC standard pin-out applies to all of the technologies in the market. For example, standard JEDEC standard pin-out are used for Extended Data Out (EDO), FP (Fast Page), SDRAM (Synchronous DRAM), DDR (Double Data Rate), DDR2 (second generation Double Data Rate), DDR3 and other DRAM devices. Having memory devices that follows a standard pin-out has its advantages. For instance, generic models can be used to place parts on boards and standardized test equipment can be manufactured. Also, economies of scale for standardized devices can be realized to keep the manufacturing cost low.

While there is a JEDEC standard for the pin-out of memory devices, there is no standard for the pin-out of processors or graphics controllers that use external memory. Hence, every design that uses a processor or graphics controller and a memory must have unique routing on the printed circuit (PC) board to connect the processor to the memory. As the processors get more complicated and faster, and as the memory interfaces also get more complicated and faster, there are many challenges involved in the routing of the signals between these components. For instance, the trace length and via counts for each of the address lines must be balanced, that is, the address lines on the PC board must be equal in length and have a common number of vias for each line. The same applies to the data lines as well. In addition, the control lines need to be carefully set up so that the timing of the signals with regards to the address and data lines is not distorted. In order to maintain the signal integrity, a multi-layer PC board is often required.

DETAILED DESCRIPTION

The invention can be implemented in numerous ways, including as a process; an apparatus; a system; and/or a composition of matter. In this specification, these implementations, or any other form that the invention may take, may be referred to as techniques. In general, the order of the steps of disclosed processes may be altered within the scope of the invention.

According to embodiments of the present invention, a memory assembly has a package pin-out that is a mirror-image of the pin-out of the memory interface of a processor. In this manner, the processor can be mounted on one side of a printed circuit board and the memory assembly can be mounted to the opposite side of the printed circuit board in direct alignment with the memory interface pin-out of the processor. The memory assembly pins or leads are connected to the processor device memory interface pins or leads using through-vias formed in the printed circuit board. The memory assembly thus configured has the advantage of simplifying the printed circuit board layout by eliminating traces and multiple vias that may be necessary to connect external memory to a processor. More importantly, the memory assembly of the present invention with processor-specific package pin-out ensures that the connections of the address lines and data lines between the memory chips in the memory assembly and the processor are shortened and balanced. Furthermore, using the memory assembly of the present invention can lead to a reduction in the number of layers required for the printed circuit board as compared to the use of discrete memory devices. Lastly, using the memory assembly of the present invention can also eliminate the need for termination resistors thus lowering the materials and manufacturing costs for a processor-memory circuit module.

FIG. 1is a perspective view of a conventional circuit module including a processor connected to one or more discrete memory devices. A circuit module1is formed on a printed circuit (PC) board10which is typically a multi-layer PC board. The circuit module1includes a processor12connected to discrete memory devices14and15. Discrete memory device14or15refers to an integrated circuit or a packaged semiconductor device containing a memory semiconductor chip (or an integrated circuit die). Discrete memory devices14and15typically have a standard package pin-out, such as the JEDEC standard pin-out. The discrete memory devices14and15are connected to the processor12using conductive traces18formed on or in the multi-layer PC board10. Conductive traces18between adjacent layers are typically connected through vias. In order to ensure signal integrity between the processor and the discrete memory devices, especially when the speed of the processors becomes faster, the routing connections between the discrete memory devices14,15and the processor12must be well balanced. Furthermore, to ensure signal integrity, termination resistance16is often required at the ends of the conductive traces18to prevent signal reflection.

FIG. 2(a) illustrates a circuit module constructed using a memory assembly having processor-specific package pin-out according to one embodiment of the present invention.FIGS. 2(b) and2(c) are front-side view and back-side view, respectively, of the circuit module ofFIG. 2(a). Referring toFIGS. 2(a) to2(c), a circuit module5is formed on a printed circuit (PC) board20. In some embodiments, the circuit module5is a multi-layer PC board. The circuit module5may include various components that are mounted on one side (e.g., the front side) or on both sides (e.g., the front and back sides) of the PC board20. In some applications, components are mounted on both sides of the PC board to minimize the size of the PC board20.

The circuit module5includes a processor12mounted on a first side, such as the front side, of the PC board20. The processor20can be a microprocessor, a central processing unit, or a graphic processor. The operation of the processor12is typically supported by an external memory. Therefore, it is often necessary to couple an external memory to the processor12on the same PC board20. In the present embodiment, the circuit module5includes a memory assembly26connected to the processor12to support the operation of the processor. In embodiments of the present invention, memory assembly26may be formed using SRAM, DRAM, and/or Flash memory devices. In one embodiment, memory assembly26includes a single memory semiconductor chip. In an alternate embodiment, memory assembly26includes two or more memory semiconductor chips (or an integrated circuit die). The two or more memory semiconductor chips may be the same type of memory devices, such as all SRAM chips, or they may be different types of memory devices, such as an SRAM and a DRAM. The specific types of memory and the number of memory chips incorporated in the memory assembly26depends on the application of the processor and the circuit module in which the processor is incorporated.

The processor12is typically a packaged semiconductor device or an integrated circuit. The processor12has a given package pin-out to interface with components of the circuit module5, including the memory assembly26. The package pin-out defines the function of each package lead of the processor12. In the present embodiment, the processor12is housed in a surface-mount packaging. In some embodiments, the processor12is packaged using a surface-mount packaging, such as a grid array package, including a ball grid array package or a land grid array package. In a ball or land grid array package, the package leads are arranged in a two-dimensional array on the bottom-side of the package. The grid array package is mounted on the PC board so that the two-dimensional array of package leads are connected to corresponding conductive pads on the PC board to enable electrical connection to be made between leads of the processor integrated circuit and other components on the PC board. A processor that interfaces with an external memory or a supporting memory includes package leads that are assigned to interface with the memory. The memory interface package leads may include address lines, data lines and control signals, such as chip enable and output enable signals. In the present description, a memory interface pin-out refers to the positions or assignment of package leads of a processor for interfacing with a supporting memory. Accordingly, a processor that interfaces with an external memory will have a given memory interface pin-out defining the package leads that are to be connected to the supporting memory device.

In embodiments of the present invention, the memory assembly26is configured to have a processor-specific package pin-out to allow the memory assembly to be mounted on the opposite side of the PC board20from the processor and in direct alignment to the processor12. More specifically, in embodiments of the present invention, memory assembly26is formed using surface-mount packaging, such as a ball or land grid array package. Memory assembly26is configured to have a package pin-out that is a mirror-image of a corresponding memory interface pin-out of the processor12. For instance, the processor12may have a first group of package leads forming the memory interface pin-out for interfacing with a supporting memory. Memory assembly26is provided with a processor-specific package pin-out that corresponds to a mirror image of the memory interface pin-out of the processor12. As thus configured, the memory assembly26can be mounted on the opposite side of the PC board20directly under the processor12and aligned with the memory interface pin-out. In some embodiment, the memory interface package leads of the processor12are electrically connected to the package leads of the memory assembly26using vertical through-vias formed in the PC board20.

FIG. 3is a cross-sectional view of the circuit module ofFIGS. 2(a)-(c) along a line A-A′ in some embodiments of the present invention. Referring toFIG. 3, the processor12is formed on a first side (e.g. front side) of the printed circuit board20. In the present illustration, the processor12is packaged as a ball grid array. When the processor12is mounted on the printed circuit board20, the ball leads32of the processor12are connected to conductive pads34formed on the PC board20. The conductive pads34of the PC board20are connected to conductive traces formed on or in the PC board to interconnect the processor to components formed on the PC board.

In embodiments of the present invention, the memory assembly26with processor-specific package pin-out is mounted to a second side, opposite to the first side, of the printed circuit board20. In the present illustration, the memory assembly26is packaged in a ball grid array package. When the memory assembly26is mounted on the printed circuit board20, the ball leads36of the memory assembly26are connected to conductive pads38formed on the PC board20. More specifically, the memory assembly26is positioned such that the leads of the memory assembly are in direct alignment with the corresponding memory interface leads of the processor12. In this manner, the memory assembly26can be connected to the processor12using through-vias30formed in the PC board20. In embodiments of the present invention, through-vias30refer to vias formed in the PC board that connects conductive pads formed on one side of the PC board directly to the opposite side of the PC board. In some embodiments, a through-via is perpendicular to the surface of the PC board and represents the shortest distance through the PC board between a pair of vertically aligned conductive pads formed on opposite sides of the PC board. In the present embodiment, through-vias30are perpendicular to the surface of the PC board20. In other embodiments, the through-vias30may be parallel slanted conductive vias. The exact structure of through-vias30is not critical to the practice of the present invention. Through-vias30are typically formed using the shortest distance between a pair of vertically aligned conductive pads on opposite sides of the PC board.

In embodiments of the present invention, memory assembly26may include one or more memory semiconductor chips24. The number of memory semiconductor chips that may be included in a memory assembly depends on the requirement or configuration of the processor12. For example, a 32-bit processor may use two 16-bit memory devices. In the present embodiment, the memory assembly26includes two memory semiconductor chips24formed on a package substrate23, sometimes referred to as an interposer. The leads of the semiconductor chips24are connected to the package substrate23, such as through wire bonding as shown inFIG. 3. In other embodiments, the memory semiconductor chips24can be connected to the package substrate23through other interconnection methods, such as tape-automated-bonding (TAB) or direct attach flip-chip bonding. Furthermore, in the present illustration, the memory semiconductor chips24are positioned side-by-side on the package substrate23. In other embodiments, the memory semiconductor chips24may be configured in a stacked formation. The memory semiconductor chips24are typically encapsulated, such as in a mold compound.

The package substrate23(or interposer) connects the leads of the memory semiconductor chips24to the package leads, such as ball leads36of the memory assembly. In this manner, the package substrate connects signals of the memory semiconductor chips24to the ball leads36so that the signals can be accessed outside of the memory assembly26. The package substrate23is configured so that the ball leads36have a processor-specific package pin-out. In this manner, regardless of the number or types of memory semiconductor chips formed thereon, the package substrate23provides the processor-specific package pin-out to enable the memory assembly26to interface directly with an external system, such as the processor12. In some embodiments, the memory assembly26includes memory semiconductor chips of the same memory type. That is, the memory semiconductor chips24may be SRAM, DRAM, or Flash memory devices. In other embodiments, the memory assembly26includes memory semiconductor chips of different memory types. That is, the memory semiconductor chips24may include a SRAM device, a DRAM device, and/or a Flash memory device.

FIG. 4, which includesFIGS. 4(a) and4(b), illustrates the pin-out patterns of a processor (FIG. 4(a)) and a memory assembly (FIG. 4(b)) with processor-specific package pin-out according to embodiments of the present invention. Referring toFIG. 4, in the present embodiment, the processor12and the memory assembly26are formed using surface-mount packaging and more specifically, are formed using ball grid array packages. Accordingly, each of the processor and the memory assembly includes a two-dimensional array of package leads formed on one side, usually the bottom side, of the surface-mount package. In the present illustration, the packages are shown with a full array of ball leads. It is understood that a grid array package may be formed using less than the full array of ball leads. The use of a full array of ball leads inFIG. 4is illustrative only.

The processor12includes a set of memory interface package leads (shaded leads in area42) that are assigned to interface with a supporting memory. The memory assembly26with processor-specific package pin-out is formed with a pin-out pattern or package lead pattern that is a mirror-image of the memory interface package leads in area42. More specifically, the memory assembly26includes package leads46(shaded leads) that are configured to correspond to the memory interface package leads of the processor12. For example, address pins A1 to A3 and data pins D1 to D4 on the processor correspond to the same address pin A1 to A3 and data pins D1 to D4 on the memory assembly but in a mirror image arrangement. The package leads46of memory assembly26are arranged to have a mirror image of the memory interface package leads42so that the memory assembly26can be coupled on the opposite side of the PC board in direct alignment with the processor12. In embodiments of the present invention, the memory assembly26may be formed using only the set of leads46that corresponds to the memory interface package leads42of the processor. Other leads (dotted circle) of the two-dimensional array may be omitted. In some embodiments, the memory assembly26includes one or more dummy leads48for structural support and ease of manufacturing. The dummy leads48can be left electrically floating or electrically grounded.

The memory assembly having processor-specific package pin-out realizes many advantages when applied in circuit modules. First, the memory assembly of the present invention ensures that the connections of the address lines and data lines between the memory assembly and the processor are well balanced. That is, all the address lines have equal length and equal number of connecting vias. Furthermore, the memory assembly of the present invention ensures the shortest connection between the processor leads and the memory assembly leads. As thus configured, the memory assembly supports high speed interface to the processor without degrading signal integrity.

Second, the memory assembly having processor-specific package pin-out of the present invention enables mounting of the memory assembly directly under the processor to reduce the space required to implement the processor and the supporting memory. Accordingly, the size of the PC board required to implement the circuit module can be reduced, thereby reducing manufacturing cost for the circuit module.

Third, when a memory assembly having processor-specific package pin-out is used, the circuit module5can be constructed using a printed circuit board with reduced number of conductive layers. In particularly, when the memory assembly is directly connected to the processor12using through-vias, the number of conductive traces needed to interconnect the memory assembly to the processor reduces significantly. A printed circuit board with reduced number of conductive layers can be used, thereby reducing the cost of the PC board and the associated cost for the circuit module. In one embodiment, a circuit module using a memory assembly having processor-specific package pin-out may be formed using a printed circuit board with 4-6 layers whereas a circuit module using conventional discrete memory devices may require a printed circuit board with 8-12 conductive layers, depending on the complexity of the complete application circuit.

Fourth, when the amount of conductive traces is reduced, electromagnetic interference (EMI) from the circuit module is reduced and shielding cost associated with the circuit module may also be reduced.

Lastly, the use of the memory assembly eliminates the need for termination resistance as the length of the conductive traces that connect the processor and the memory assembly is reduced to a shortness such that the needs for termination resistance is obviated. Accordingly, a circuit module formed using the memory assembly of the present invention does not require the use of termination resistance at the ends of the conductive traces.

In some embodiments, the memory assembly with processor-specific package pin-out can be formed using a single memory semiconductor chip (or an integrated circuit die). In other embodiments, the memory assembly with processor-specific package pin-out can be formed using a multi-chip module with multiple memory semiconductor chips housed in a single package. For example, a memory assembly may have two to four memory semiconductor chips packaged together into a single package. The exact configuration of the memory assembly is not critical to the practice of the present invention.