Digital pattern generator (DPG) for E-beam lithography

A method of lithography including providing a first mirror array and a second mirror array of a digital pattern generator (DPG); the second mirror array is offset from the first mirror array in a first direction. A first data piece and a second data piece associated with an IC device, are received by the DPG. The first and second data piece each defines a state of a pixel of the DPG. The first data piece is provided to a first pixel of the DPG. The second data piece is also provided to the first pixel of the DPG. A first point on a photosensitive layer on a target substrate is exposed. The first point is defined by the first data piece and the second data piece. The target substrate moved in a second direction, perpendicular to the first direction to expose a second point.

BACKGROUND

One process where advances are concentrated is lithography—lithography generally involves the patterned exposure of a photosensitive layer on a target substrate so that portions of the layer can be selectively removed to provide a masking element on the substrate. The masking layer exposes underlying areas for selective processing such as by etching, material deposition, implantation and the like. Photolithography utilizes electromagnetic energy in the form of ultraviolet light for selective exposure of the resist. As an alternative to electromagnetic energy, charged particle beams have been used for high resolution lithographic resist exposure. In particular, electron beams have been used since the low mass of electrons allows relatively accurate control of an electron beam at relatively low power and relatively high speed. Electron beam lithography system is also an effective method to scale down the feature size. However, production-level wafer throughput by the current lithography systems is a challenge in large scale fabrication in the IC industry.

Accordingly, what needed are systems and methods for increasing the wafer throughput and saving the footprint for the lithography system.

DETAILED DESCRIPTION

It is to be understood that the following disclosure provides many different embodiments, or examples, for implementing different features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. Moreover, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed interposing the first and second features, such that the first and second features may not be in direct contact. Various features may be arbitrarily drawn in different scales for simplicity and clarity. It is noted that the term region as used herein, for example to provide an exposure region, does not necessitate any given area unless specifically described. For example, a region of a target substrate may be as defined as a e-beam exposure point.

FIG. 1illustrates a schematic diagram of an electron beam lithography system100according to one or more embodiments of the present disclosure. As shown inFIG. 1, the electron beam lithography system100includes a source102, a condenser lens column104, a digital pattern generator (DPG)106, an electric signal generator (ESG)108, an integrated circuit (IC) design database110, a projection lens column112, a wafer stage114, and a wafer116disposed on the wafer stage114. It is understood that other configurations and inclusion or omission of various items in the system100may be possible. The system100is an example embodiment, and is not intended to limit the present invention beyond what is explicitly recited in the claims. In an embodiment, the system100is a reflective electron beam lithography tool, also referred to as REBL. One example is described in further detail inREBL Nanowriter: Reflective Electron Beam Lithography, by Petric et al., Proc. of SPIE Vol. 7271, which is hereby incorporated by reference in its entirety.

The source102provides a beam, such as an electron beam or an ion beam. The source102may include an ion source or an electron source. In some embodiments, the electron source includes a cathode, an anode, and an aperture. The condenser lens column104guides the radiation beams from the source102to the pattern generator106. In some embodiments, the condenser lens column104may include a plurality of electromagnetic apertures, electrostatic lenses, and electromagnetic lenses.

The digital pattern generator106may be coupled through fiber optics to an electric to optical signal converter that is coupled to the electric signal generator108and to the IC design database110. In an embodiment, the pattern generator106includes a mirror array plate. In some embodiments, at least one electrode plate is disposed over the mirror array plate, and at least one insulator is between the mirror array plate and the electrode plate or between the electrode plates. The mirror array plate includes a plurality of “mirrors” arranged in an array of columns and rows, similar to a memory device configuration. In an embodiment, the mirrors are metallic pads of the size between nanometers and micrometers. Each pad constitutes a pixel of the DPG. The reflectivity of the mirrors or pixels is switched on and off by the electric signal (data) from the electric signal generator108. The pattern generator106provides patterning radiation beams118according to a design layout by reflecting or absorbing a radiation beam incident each mirror. The electric signal generator108connects to mirrors embedded into the mirror array plate of the pattern generator106and to the IC design database110. The electric signal generator108turns mirrors on or off according to the IC design database110by reflecting or absorbing a radiation beam.

The IC design database110connects to the electric signal generator108, and thus the DPG106. The IC design database110includes an IC design layout. In some embodiments, an IC design layout includes one or more IC design features or patterns. The IC design may define a device such as a static random access memory (SRAM) and/or other logic circuits, passive components such as resistors, capacitors, and inductors, and active components such as P-channel field effect transistors (PFET), N-channel FET (NFET), metal-oxide semiconductor field effect transistors (MOSFET), complementary metal-oxide semiconductor (CMOS) transistors, bipolar transistors, high voltage transistors, high frequency transistors, other memory cells, and combinations thereof. The IC design layout is presented in one or more data files having the information of geometrical patterns. In some examples, the IC design layout may be expressed in a graphic database system (GDS) format. The IC design database110controls the electric signal generator108according to the IC design layout and therefore controls the pattern generator106to provide the patterning radiation beams118.

The data is sent from the IC database110. The data may be stored and/or sent as a computer file, for example, as a graphic database system (GDS) type file, as an open artwork system interchange standard (OASIS) type file, and/or as any appropriate type file. The GDS or OASIS files are database files used for data exchange of IC layout artwork. For example, these files may have binary file formats for representing planar geometric shapes, text labels, as well as other layout information of the IC layout. The GDS or OASIS files may each contain multiple layers. The GDS or OASIS files may be used to reconstruct the IC layout artwork, and as such can be transferred or shared between various fabrication tools including the system100.

The projection lens column112guides the patterning radiation beams118generated from the pattern generator106to the wafer116secured on the wafer stage114. In some embodiments, the projection lens column112includes a plurality of electromagnetic apertures, electrostatic lenses, electromagnetic lenses, and deflectors. The wafer stage114secures the wafer116by electrostatic force and provides accurate movement of the wafer116in X, Y and Z directions during focusing, leveling, and exposing the wafer116in the electron beam lithography system100. In some embodiments, the wafer stage114includes a plurality of motors, roller guides, and tables.

In some embodiments, a high electric potential is applied between a cathode and an anode at the source102, which accelerates the electrons towards and through the aperture. The value of the applied electric potential determines the energy level of the electron beams leaving the aperture. The energy of the electron beams reduces as the electron beams travel toward the DPG106. The pixels in the DPG106are programmed to pattern the beam. For example, as discussed above, the DPG106includes a CMOS-based device or chip with multiple mirror arrays and multiple pixels, each pixel being independently operable to be “on” or “off”. The multiple pixels are arranged in an array; the arrays may be arranged in segments referred to herein as mirror arrays (MA). For example, when a pixel is in an “on” state, the e-beam can be directed through the pixel, also referred to as absorbed. When the pixel is in an “off” state, the e-beam may be blocked from going through the pixel, also referred to as reflected. During the lithography process, the e-beam is directed to the pattern generator, the pattern generator is controlled to independently turn on or off each pixel by a control circuit coupled with each pixel and addressing each pixel. The controlled pixel status is determined by the data from IC database110. The pixel may be turned off/on by sending “data” to the pixel for example, applying a voltage potential to the pixel (e.g., 2V). The data sent to the mirror is also referred to herein as a data piece or bit. The “mirrors” of the mirror array may be square pads of conductive material (e.g., TiN), a lenslet structure, and/or other structures including those later developed.

The DPG106may include N×M number of mirror arrays, also referred to as mirror array segments. Each mirror array includes a plurality of pixels disposed in an array as discussed above. The system100may use the DPG106, which has binary (on/off) pixels, to provide a gray tone exposure to provide a pattern on the substrate116. For example, as the substrate116moves under the beam, the pattern of pixels on the DPG106shifts.

The optical column112forms an image reduced in size and may accelerate the electrons to reach the wafer116secured on the wafer stage114. In some embodiments, the electron beam lithography system100is operated under a vacuum condition.

The electron beam lithography system100also includes a computer120with a processor, a memory, and an I/O interface. The computer120may be coupled to the source102, the DPG106, the ESG108, the IC database110, and/or the wafer stage114, for performing one or more of the operations described herein. Some common forms of the computer readable media used in the present disclosure may include, for example, floppy disk, flexible disk, hard disk, magnetic tape, any other magnetic medium, CD-ROM, any other optical medium, punch cards, paper tape, any other physical medium with patterns of holes, RAM, PROM, EPROM, FLASH-EPROM, any other memory chip or cartridge, carrier wave, or any other medium from which a computer is adapted to read. These media may be used to store and/or implement the embodiments discussed herein including those ofFIGS. 2-6.

Referring now toFIG. 2, provided is a flowchart illustrating a method200of forming a pattern on a substrate, such as wafer116, using lithography system, such as lithography system100. It is understood that additional steps can be provided before, during, and after the method200, and some steps described can be replaced, eliminated, or moved around for additional embodiments of the method200.

The method200begins at step202by providing a substrate. The substrate may be substantially similar to the wafer116described above with reference toFIG. 1. In some embodiments, the substrate may be a silicon wafer. Alternatively or additionally, the substrate may include another elementary semiconductor, such as germanium; a compound semiconductor including silicon carbide, gallium arsenic, gallium phosphide, indium phosphide, indium arsenide, and/or indium antimonide; or an alloy semiconductor including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and/or GaInAsP. In an embodiment, the substrate includes a semiconductor on insulator (SOI). A plurality of conductive and non-conductive thin films may be deposited on the substrate. In an embodiment, a photosensitive layer is disposed on a top surface of the substrate. The photosensitive layer may include photoresist film and/or electron beam sensitive resist film. For example, a positive resist or a negative resist may be provided, In embodiments, the layer may be a single layer resist film or a multiple layer resist film.

The method200proceeds to step204by patterning or exposing the resist film deposited on the substrate using the lithography system100. In some embodiment, a region of the substrate patterned by the beam may be referred to as a data grid pixel, which is defined by the patterned beam after demagnification. When the electron beam lithography system100is used at step204, the pattern is decided by the pattern generator106ofFIG. 1, and implemented using the patterning electron beam118provided by the pattern generator106, as discussed with regard toFIG. 1. The provision of this pattern is discussed in further detail below with reference toFIGS. 3-6.

After providing a pattern onto the photosensitive layer, the method200proceeds to step206by developing the exposed photosensitive layer on the substrate to form a resist pattern. In some embodiments, a developer includes a water based developer, such as tetramethylammonium hydroxide (TMAH). In other embodiments, a developer may include an organic solvent or a mixture of organic solvents, such as methyl a-amyl ketone (MAK) or a mixture involving the MAK. Developer may be applied onto the exposed resist film, for example using a spin-on process. The applied developer may also be performed with a post exposure bake (PEB), a post develop bake (PDB) process, or a combination thereof. After development of the photosensitive layer, the remaining resist pattern may be referred to as a masking element.

The method200then proceeds to step208and transferring the resist pattern defined by the masking element to the substrate or layer formed thereon, for example by an etching process such as a dry (plasma) etching, a wet etching, and/or other etching methods.

During an exposure process using the lithography system100and/or the method200, a wafer stage, such as the stage114may be moved so that various regions on a target substrate may be exposed using one exposure tool. For example, when the wafer stage114is moving relative to the lens112, a first region of a wafer may be exposed along an opposite direction of the moving direction of the wafer stage in a scanning mode. After finishing exposing the first region, the wafer stage114may be continuously or discretely moved relative to the lens112, so that a second region, which is different from the first region of the wafer may be exposed in the scanning mode. During the one or more “scanning” processes, the wafer stage114may be mobile, and the lens112may be stationary. In other embodiments, the beam118may be mobile.FIG. 2may be implemented by the system100and/or the devices described below with reference toFIGS. 3-6.

Referring now toFIG. 3, illustrates is an embodiment of a DPG mirror array. The mirror array302may in the DPG106of the system100ofFIG. 1. The mirror array302has a “mirrors” or pixels arranged in an array defined by columns and rows. The mirror array302may be one segment or MA of a plurality of MAs of the DPG. The blocks may be used to provide an appropriate dose corresponding to the grayscale desired to implement the data (e.g., design data). The design data is reproduced as a pattern on the wafer116by providing the corresponding dose of the beam. The dose of the beam is performed by controlling the mirrors of the mirror array including the time of exposure to a given mirror and the time of exposure to a cumulative number of mirrors as the wafer and/or beam move relative to one another. To accomplish this, each pixel of the mirror array is fed with a new bit or piece of data on a continuous basis during the exposure process. For example, in an embodiment, each piece of incoming data is delayed so that the mirrors of the block it is associated with are controlled in succession. The summation of these as the projected beam is incident a moving wafer provides the appropriate dose (e.g., grayscale) for each portion of the wafer. One embodiment of a DPG mirror array is described in Grella et al.,Digital pattern generator: an electron-optical MEMS for massively parallel reflective beam lithography, J. Micro/Nonlith. MEMS MOEMS, July-September 2013, Vol. 12 pages 031107-1-031107-10, which is hereby incorporated by reference. In an embodiment, this DPG mirror array may be used to implement the methods described below.

Referring now toFIG. 4, illustrated is a diagrammatic representation of a DPG400that includes a plurality of mirror arrays implementing a pixel shift method. A pixel shift method implementation of the mirror arrays may serve to increase resolution provided by the mirror array. The DPG400may be substantially similar to the DPG106described above with reference toFIG. 1and/or the DPG ofFIG. 3.

The DPG400as illustrated includes four segments or four mirror array (MA) illustrated as402,404,406and408. The DPG400may be referred to as a 2×2 DPG. Using the context of the notation N×M discussed herein, N=2 and M=2 for DPG400, where N is a mirror array number in the x-direction and M is a mirror array number in a y-direction. As illustrated, the mirror array402has a plurality of a first set of data (e.g., also referred to bits or pieces of data, which may be simply a voltage applied to the mirror, illustrated by1A,1B etc) delivered to each pixel the mirror array402. Mirror arrays404,406, and408also include data delivered to the respective mirror array. It is noted that mirror array404is shifted in the x-direction from mirror array402. Specifically, it is shifted 0.5 pixel (or half a pixel distance) in the x-direction. A hashed grid is provided inFIG. 4for illustration of the shifting of the mirror arrays. Similarly, mirror array406is shifted in the y-direction from mirror array402by 0.5 pixel. The mirror array408is shifted in both the x-direction and the y-direction by 0.5 pixel from the mirror array402. Like the number of mirror arrays, the shift of the mirror arrays as illustrated (e.g., 0.5 shift in a direction) is exemplary only and any degree of shift may be possible.

Illustrated by element410ofFIG. 4is the produced exposure using the mirror arrays402,404,406, and408. As illustrated by resultant pattern410, each of the mirror array402,404,406,408acts upon a region of a target substrate. In other words, the element410illustrates a cumulative dose of the modulated beam seen by a region of a target substrate. The cumulative exposure410is an overlapping of each of mirror arrays402,404,406, and408incident the target substrate. In an embodiment, the cumulative exposure410is provided on a region of a photosensitive layer on a substrate, such as the wafer116ofFIG. 1and/or the substrate described above with reference to block202ofFIG. 2. (It is noted that the exposure if provided one ‘point’ by one ‘point’ on the substrate.) The illustration of element410shows the benefits of the pixel shift methodology. The shift of the mirror arrays allows for increased resolution for the target substrate (e.g., decreased effective pixel size). See, for example, the resultant pattern410where each region of the target (i.e., defined by the pixel size of the DPG) is partitioned into various segments (e.g., 4) based on the shift of the original mirror arrays404,406,408. These segments may be effective pixel regions each having separately controlled and defined exposure. In an embodiment, by implementing the shifts of states404,406, and408(i.e., a 4× shift pattern) a 2× resolution improvement for the mirror array can be seen. In an embodiment, this may be shown as an N2mirror array can get an N resolution improvement. For example, 22=4 mirror array with 1 μm pixel size is equivalent to an effective pixel size of ½=0.5 μm pixel size. As another example, 32=9 mirror array with 1 μm pixel size is equivalent to an effective pixel size of ⅓=0.33 μm pixel size. However, it is noted that the area, routing signal, and power are also increased as N2.

Referring now toFIG. 5, illustrated is a method500for providing data to a digital pattern generator. The method500may be used with the system100, described above with reference toFIG. 1, the method200, described above with reference toFIG. 2, and/or the DPG302described above with reference toFIG. 3.

The method500begins at block502where a pattern of data (pieces) is provided. The pattern may be suitable for an N×M configuration of mirror arrays. SeeFIG. 4above. It is noted that the method500discusses block502and the presentation of the pattern as an N×M array pattern for ease of understanding. The data set may be referred to as Ndata×Mdataor Nd×Md. However, it is not necessary for the method500for the data to be presented in the indicated array form. For example, in other embodiments, block502is omitted and data is presented in another form. The data may be determined based on the target pattern for the integrated circuit to be generated on a target substrate. For example, the data may be generated using an IC database such as the IC database110, described above with reference toFIG. 1.

The method500then proceeds to block504where a DPG is provided. In an embodiment, the DPG includes a plurality of mirror arrays (MA) or mirror array segments. In an embodiment, the DPG includes N×M mirror arrays where N is the number of mirror arrays in an x-direction and M is a number of mirror arrays in a y-direction. The DPG may be configured such that the scan direction is in the x-direction, as discussed herein. However, other scan directions are possible.

In an embodiment, the DPG provided has a configuration of mirror array numbers (N×M) where N=1 and M is equal to a number greater than one. In such an embodiment, the DPG is operable to accept Nd×Md, where Ndis greater than 1, as described in further detail below. It is noted that as discussed herein the terms “x” and “y” directions are used for illustrative purposes only and indicative only of a relative direction and may be reversed in any of the embodiments discussed herein. Additionally, the directions may be referred to with reference to the scan direction (x in the present example is the scan direction, and perpendicular scan direction, y in the present example).

In an embodiment of block504, the DPG includes M mirror array in the y-direction, where M is greater than 1. In an embodiment, each of the M mirror arrays may be shifted from one another as described above with reference toFIG. 4. The shift may be any pixel fraction in the y-direction.FIG. 6is illustrative of a DPG600having an N×M mirror array configuration where N=1 and M=2. Specifically, the exemplary DPG600includes two MA in the y-direction (M is equal to two). The second mirror array604is shifted from the first mirror array602by 0.5 pixel in the y-direction. It is noted that this is exemplary only and not intended to be limiting, for example, in embodiments, M may be any number. In embodiments, the shift in the y-direction may be any fraction of a pixel. As but one other example, in an embodiment M is equal to three mirror arrays and a shift of ⅓ of a pixel in the y-direction is provided by each of the M mirror arrays.

As discussed above, the DPG provided in block504of the method500has N number of MA in the x-direction. In an embodiment, N is equal to 1. This embodiment is illustrated by the DPG600ofFIG. 6. The DPG600does not include a mirror array shifted in the x-direction. In an embodiment, the x-direction is the scan direction. Rather, data (e.g., Nd), or scan direction may be shared by a single pixel as discussed with reference to block506below.

The method500then proceeds to block506where the data is provided to the DPG and mirror arrays discussed above with reference to block504. In an embodiment, the data is a data set having a piece of data for each pixel of MA of an N×M configuration, the data referred to herein as Nd (data for N mirror arrays in the x-direction) and Md (data for M mirror arrays in the y-direction), where Nd and Md are greater than 1. However, in contrast toFIG. 4, the data may be delivered to a DPG having a configuration of mirror arrays of N×M where N is less than Nd, such as N=1. The data is delivered such that multiple pieces of data “share” one or more pixels of a mirror array. This allows less MA for receiving the same amount of data. The sharing may be accomplished by increasing the signal frequency of delivering the data to the mirror array(s) or decreasing the scan speed such that the relation between the scan speed and the frequency provide for a single pixel of the DPG to exhibit two or more states defined different data pieces during a scan of the pixel of the DPG. This may be referred to herein as a “shared data mode” operation of the DPG and/or mirror arrays such that at least one pixel of the DPG is used to provide two different data points to a single region on the target substrate. (A single region on the target substrate is a region of the substrate defined by the size of the pixel of the DPG, after demagnification. This is also referred to as a region of a data grid.) It is noted that the exposure on the substrate is substantially a point exposure, however, for ease of reference the region corresponding to the pixel size of the DPG after demagnification is referred to herein as region in which multiple data pieces are used to define the exposure (points).

In other words, in a shared data mode, data from the set of data (Nd) in x-direction is “filled in” to the mirror array in order. As one example, the DPG has N=1 mirror array in the x-direction and Nd=2, the data typically configured for the second MA is instead “filled in” to the single mirror array by time-sharing the pixel. (Again, in an embodiment, the x-direction is the scan direction). This configuration is illustrated byFIG. 6, discussed below. UsingFIG. 4as a comparison, the data from a second MA that shares the same Y-position as a first MA is merged or shares a single pixel of the first MA, eliminating the need for a second MA to contain that piece of data. For example, inFIG. 6a single mirror array602includes the data provided to two different mirror arrays402,404ofFIG. 4because the mirror array402,404share the same y-position. Similarly, the mirror array604ofFIG. 6holds the data of both mirror array406,408ofFIG. 4. As discussed herein the data in mirror array602shares the pixel by occupying the pixel for ½ t; while the data in402,404occupies the respective pixel for t. “t” is a unit of time.

In an embodiment, the frequency of data delivery to a pixel of the DPG and the scan speed of the operation (e.g., scan speed of the target substrate) must have a defined relationship in order to expose a pixel region of the target substrate. In order to effectuate the shared data mode of operation of the DPG discussed herein, at least two pieces of data are delivered to a given pixel of the DPG during the time it takes to scan the given pixel. In an embodiment, while scanning the DPG in a first direction during the lithography process a scan speed of S/T is used. S is the pixel dimension in the first direction and T is a time to scan over the full length S of the pixel. The data is delivered to the pixel at a frequency of F. In an embodiment, the magnitude of frequency F is such that during the time T, at least two pieces of data are delivered to the pixel. Thus, in an embodiment, the signal frequency F is greater than 1/T. In an embodiment, the signal frequency is 2×1/T. In another embodiment, the signal frequency is 3×1/T. However, any signal frequency that provides more than one piece of data during time T is within the scope of this disclosure.

Referring now to the device ofFIG. 6in detail, illustrated is a DPG600of N×M size, where N=1 and M=2. The DPG600is exemplary only and not intended to be limiting to any quantity of MA or number of data pieces sharing a given pixel. The DPG600includes a mirror array602and a mirror array604. The mirror array604is shifted in the y-direction from the mirror array602. In an embodiment, the shift is 0.5 pixel. It is noted that there is no shift in the x-direction (e.g., scan direction); however, other embodiments of the physical configuration of the DPG are possible including additional quantities of MA, different shift directions, different shift amounts, etc.

As illustrated inFIG. 6, a pattern of data that includes data for pixels of mirror arrays of 2×2 MA DPG is provided to the DPG600, of in other words, data of Nd=2 and Md=2 size is provided. The data pieces are illustrated as a #letter (e.g.,1A,3B, etc). The data may be determined from IC data generated as a computer file, for example, as a graphic database system (GDS) type file, as an open artwork system interchange standard (OASIS) type file, and/or as any appropriate type file. The GDS or OASIS files are database files used for data exchange of IC layout artwork, the layouts may be transferred into a pattern defining the layout using a mirror array. In an embodiment, the data includes a definition of the state of mirrors of the array (e.g., on or off, reflective or not) for example, provided by applying a voltage to the pixel or mirror.

While the data illustrated inFIG. 6is of the size Nd=2, Md=2, the DPG mirror array number itself is reduced in size. The DPG600has a mirror arrays602,604that are in an N×M array where N=1 and M=2. Two different pieces of data are delivered to each pixel of each of the MA602and604, illustrated as a data piece on the left and right of a pixel. For example, data1A and2A “share” pixel602aof the MA602. It is noted that the “sharing” is temporal, in that data1A occupies pixel602afor a first time, data2A occupies pixel602afor a second time. The second time may immediately follow the first In an embodiment, the sharing is accomplished by increasing (e.g., doubling) the frequency of delivering data to the pixel as discussed above. In another embodiment, the sharing is accomplished by decreasing the scan speed of the process. This is compared toFIG. 4where the data1A and2A are each provided to different MAs shifted in the x-direction (see402and404of DPG400). Similarly, data3A and4A share pixel604aof the MA604during a single scan time. Thus,FIG. 6illustrates a DPG that images a pattern by merging two pieces of data such that they share a pixel (see, e.g.,1A and2A) in the x-direction or scan direction. In other embodiments, any number of pieces of data can share the same pixel during a scan of the pixel.

The configuration illustrated byFIG. 6and the accompanying description ofFIG. 5also makes is possible reduce the number of mirror arrays and thus, reduces the routing signals of the DPG. For example, two pieces of data share a same data line to a single pixel.

The method500ofFIG. 5, then proceeds to block508where the substrate is exposed by the pattern of radiation created by the DPG and defined by the data as discussed above in block506. The exposure and the target substrate may be substantially similar to as discussed above with reference toFIG. 1.

Illustrated by element606ofFIG. 6is the produced pattern using the methodology discussed above. Element606is a cumulating result of the data pieces of mirror arrays602and604. In other words, the element606illustrates a cumulative dose of the modulated beam seen by a target such as a target substrate. In an embodiment, the cumulative exposure606is provided on a region of a photosensitive layer on a substrate, such as the wafer116ofFIG. 1and/or the substrate described above with reference to block202ofFIG. 2, after demagnification. The element608illustrates a magnified region of the element606. Region610is a region of the data grid of the substrate and corresponds to a pixel size of the DPG (before demagnification). Region610illustrates that for a given region of the resultant pattern on the target substrate, the region is defined by the overlap of data provided by the time control. For example, the region602adefines the region on the substrate, which includes with the upper portion of region604aoverlaid. The region610illustrates a point at the center of which (1A/2A/3A/4A) is an exposure point.

The illustration of element606shows a benefit of the shared data methodology by increasing the frequency of providing the data. By implementing this methodology, an Nd=2 and Md=2 set of data can be reduced to a 1×2 mirror array number (compareFIGS. 4 and 6). Furthermore, routing signals inFIG. 6(in comparison withFIG. 4) are reduced.

Thus, what are provided are methods and devices that allow for an increase in the frequency of a given mirror array pixel to write data on the wafer. In other words, the frequency of the data delivery to the pixel of the DPG is increased, while the scan speed is maintained. Or conversely, the scan speed is decreased relative to the frequency of data delivery. This allows a reduced number of MA and thus area, to write the same data onto a substrate. For instance, one or more pieces of data are provided to the pixel of the mirror array during the scanning of that pixel for exposure of a target substrate. As a result, for example, a mirror array may 1×M to write data of Nd×Md size. It is noted that the size 1 in the x-direction (scan direction) is exemplary only. The methods and systems discussed above can also implement a shift in the x-direction (e.g., as illustrated inFIG. 4) in addition to the sharing of data in each of the MA of the x-direction.

As illustrated above, in an embodiment, a mirror array that is N×M may be reduced to 1×M, while providing the same resolution using the decreased exposure period by a factor of N. In one embodiment, a mirror array having N=3 and M=3 may be reduced from 9× to 3×. In a further embodiment, routing signals are also reduced from N×M quantity to 1×M quantity. Extending on the previous example, from 9× to 3×. As further illustrated above, embodiments of the methods discussed herein including, for example, the shared data mode allow for reducing a critical dimension (CD) by a factor n where n<1.

Thus, in one embodiment, describes a method that includes providing first data piece and a second data piece associated with an integrated circuit (IC) device. The first and second data piece each defines a state of a pixel of a digital pattern generator (DPG). The first data piece is provided to a first pixel of the digital pattern generator (DPG). The second data piece is provided to the first pixel of the DPG. Further, a point of a target substrate is exposed using radiation beam defined by the first and second data pieces.

In another of the embodiments, a method of lithography includes providing a digital pattern generator (DPG) having a first mirror array and a second mirror array. The second mirror array is shifted from the first mirror array in a first direction. The DPG is programmed to provide a patterned beam. The programming includes providing a first data piece to a first pixel of the first mirror array; providing a second data piece to the first pixel of the first mirror array; providing a third data piece to a first pixel of the second mirror array; and providing a fourth data piece to the first pixel of the second mirror array. A patterned beam is provided by the programming and delivered to a substrate, wherein the point defined on the substrate is defined by each of the first, second, third, and fourth data pieces.

In another embodiment, a method of lithography is provided. A DPG is provided that has a first pixel. The DPG is scanned in a first direction during a lithography process with a scan speed of S/T, while sending a data signal to the DPG. The data signal has a signal frequency of greater than 1/T. S is the pixel dimension in the first direction and T is a time to scan over the full dimension S of the pixel.

In a further embodiment, the patterned beam exposes a pixel of the substrate. This pixel includes: a first portion defined by the first data piece; a second portion defined by the second data piece; a third portion defined by the first data piece and the third data piece; and a fourth portion defined by the second data piece and the fourth data piece.

In yet another of the broader embodiments, provided is an apparatus including a computer readable medium that stores a plurality of instructions for execution by at least one computer processor. The instructions are for receiving a plurality of data defining states for pixels in a plurality of mirror arrays oriented in an x-direction and a y-direction; determining a data delivery frequency that is greater than the inverse of the time for scanning a pixel of the DPG.

In one embodiment, a method of lithography is provided that includes providing a first mirror array and a second mirror array of a digital pattern generator (DPG). The second mirror array is offset from the first mirror array in a first direction (e.g., perpendicular a scan direction). A first data piece and a second data piece associated with an integrated circuit (IC) device are received. The first and second data piece each defines a state of a pixel of the DPG. The first data piece is sent to a first pixel of the DPG and the second data piece is then sent to the first pixel of the DPG (e.g., subsequent and immediately following the first piece.) A first point on a photosensitive layer on a target substrate is exposed; the first point is defined by the first data piece and the second data piece. During the method of lithography, the target substrate is moved in a second direction, perpendicular to the first direction to expose a second point.

In a further embodiment, the DPG is scanned in the second direction during the method of lithography with a scan speed S/T while sending the first and the second data pieces to the DPG with a signal frequency greater than 1/T, wherein S is the first pixel length in the first direction and T is a time to scan the first pixel length S.

In another further embodiment, the providing the first data piece and the providing the second data piece is performed through a single data line to the first pixel of the DPG.

In another broader embodiment, an electron beam lithography system is provided that includes a digital pattern generator (DPG). The DPG includes a plurality of mirror arrays, wherein each of the plurality of mirror arrays is offset only in a first direction, and each of the plurality of mirror arrays are not offset in a second direction. The system also includes a wafer stage operable to move a target substrate in a second direction, perpendicular the first direction.

In a further embodiment, this plurality of mirror arrays consists of two, and only two, mirror arrays. In an embodiment, the offset in the first direction is a distance of ½ of a pixel of one of the plurality of mirror arrays. In an embodiment, the DPG includes three mirror arrays (and in a further embodiment only three arrays). In such an embodiment, the offset in the first direction is a distance of ⅓ of a pixel of one of the plurality of mirror arrays.