ARRAY SUBSTRATE AND METHOD FOR MANUFACTURING THE SAME, DISPLAY PANEL AND DISPLAY DEVICE

An array substrate, a method for manufacturing an array substrate, a display panel and a display device are provided. The array substrate includes a substrate; an insulating layer arranged at a side of the substrate, where the insulating layer is provided with an opening, the insulating layer includes a first area and a second area, a thickness of the first area is less than a thickness of the second area, and the first area is arranged around at least a part of the opening; and a first conductive part arranged at a side of the insulating layer away from the substrate, where an orthographic projection of the first conductive part on the substrate and an orthographic projection of the first area on the substrate are at least partially overlapped.

This application claims priority to Chinese Patent Application No. 202410109528.6, titled “ARRAY SUBSTRATE AND METHOD FOR MANUFACTURING THE SAME, DISPLAY PANEL AND DISPLAY DEVICE”, filed on Jan. 25, 2024 with the China National Intellectual Property Administration, which is hereby incorporated by reference in its entirety.

FIELD

The present disclosure relates to the field of display devices, and in particular to an array substrate, a method for manufacturing an array substrate, a display panel and a display device.

BACKGROUND

With the continuous development of display panel technology, requirements for the yield of display panels have been raising. To improve the display effect of a display area, components without display functions are generally arranged in a non-display area, and the components in the display area are connected to those in the non-display area through signal wires.

In conventional technology, the display area and/or non-display area is provided with openings, and the signal wires located in different layers are connected with each other through the structure of the openings to transmit signals. In practical scenario, the signal wires adjacent to the opening area are more likely to be disconnected, which causes a low yield of the display panels.

SUMMARY

An array substrate, a method for manufacturing an array substrate, a display panel and a display device are provided according to embodiments of the present disclosure, which are interested in how to solve the problem of a low yield of the display panels due to metal wires in the display panel being more likely to be disconnected.

In the embodiments of the present disclosure, an array substrate is provided, the array substrate includes a substrate; an insulating layer, arranged at a side of the substrate, wherein the insulating layer is provided with an opening, and the insulating layer comprises a first area and a second area, wherein a thickness of the first area is less than a thickness of the second area, and the first area is arranged around at least a part of the opening; and a first conductive part, arranged at a side of the insulating layer away from the substrate, wherein an orthographic projection of the first conductive part on the substrate and an orthographic projection of the first area on the substrate are at least partially overlapped.

In the embodiments of the present disclosure, a display panel is further provided, including the array substrate according to any one of embodiments.

In the embodiments of the present disclosure, a display device is further provided, including the display panel in the above embodiments.

In the embodiments of the present disclosure, a method for manufacturing an array substrate is further provided, including:providing an insulating material layer on a substrate;patterning the insulating material layer to form an insulating layer including an opening, a first area and a second area, a thickness of the first area is less than a thickness of the second area, and the first area is arranged around at least a part of the opening;providing a conductive material layer at a side of the insulating layer away from the substrate; andpatterning the conductive material layer to form a first conductive part, wherein an orthographic projection of the first conductive part on the substrate and an orthographic projection of the first area on the substrate are at least partially overlapped.

REFERENCE SIGNS IN THE DRAWINGS

DETAILED DESCRIPTION

The features and exemplary embodiments of the present disclosure are described in detail below. In the following detailed description, many specific details are provided to facilitate full understanding of the present disclosure. The present disclosure may be implemented without some of these specific details. The description of the exemplary embodiments is only intended to provide a better understanding of the present disclosure. In the drawings and the following description, at least part of well-known structures and techniques are omitted to avoid unnecessarily obscuring the present disclosure. In addition, sizes of part of structures may be enlarged for clarity. Furthermore, the described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

In the description of the present disclosure, it should be noted that “multiple” refers to at least two. Unless otherwise noted; the orientation or positional relationships indicated by terms such as “up”, “down”, “left”, “right”, “inner”, “outer” and the like are merely for the convenience of describing the present disclosure and the simplification of the description rather than indicating or implying that the device or component referred must be arranged in a particular orientation, or be constructed and operated in a particular orientation, and therefore should not be construed as a limitation to the present disclosure. In addition, the terms “first”, “second” and the like are for purpose of description, and should not be construed as indicating or implying relative importance.

All orientation words used in the following description are the directions shown in the drawings and are not intended to limit the specific structures of the embodiments of the present disclosure. In a description of the present disclosure, it should be further noted that, unless otherwise explicitly specified and located, terms such as “install” and “connect” should be understood in a broad sense, for example, the terms may imply a fixed connection, a detachable connection, or an integral connection; may imply a direct connection or an indirect connection. The specific meaning of the above terms in the present disclosure may be understood under specific circumstances.

In conventional technology, part of the insulating film layers of the display area and/or the non-display area in the display panel are provided with openings. For example, openings are arranged on the insulating film layer of the non-display area to accommodate components such as a control chip, and openings are arranged on the film layer of the display area and the wiring in different layers can be connected to each other through the openings. In practical scenario, the signal wiring around the peripheral side of the openings are more likely to be disconnected, e.g., the signal wiring may be broken, resulting in a low yield of the display panels.

In a case that conductive wiring is required to be manufactured on the insulating film layer with vias, the inventor found that in a case that the conductive material is patterned to manufacture the metal wiring by using photoresist and the like processes or techniques, the photoresist may flow into the vias due to the existence of the openings, causing the conductive material, which should be covered by photoresist during the manufacturing process, is exposed and etched, affecting the yield of conductive wiring, resulting in the problems such as disconnection, e.g., wiring breakage, thereby compromising the overall yield of the display panels.

In order to more clearly understand the present disclosure, a display panel20, a display device30, an array substrate10and a method for manufacturing the array substrate are described in detail below in conjunction with theFIGS.1to20.

Reference is made toFIGS.1to3.FIG.1is a schematic structural diagram of an array substrate10according to an embodiment of the present disclosure.FIG.2is a schematic structural diagram of a partially enlarged view of a position P shown inFIG.1.FIG.3is a section view in an A-A direction shown inFIG.2.FIG.1illustrates the position P located in the non-display area NA as an example. In other embodiments, the position P may further be located in the display area AA, and the position P may be partially located in the display area AA and partially located in the non-display area NA. As shown inFIG.1toFIG.3, the array substrate10provided in an embodiment of the present disclosure includes a substrate100, an insulating layer200, and a first conductive part300. The insulating layer200is arranged at a side of the substrate100, and the insulating layer200is provided with an opening210. The insulating layer200includes a first area220and a second area230. The thickness of the first area220is less than the thickness of the second area230, and the first area220are arranged around at least a part of the opening210. A first conductive part300is arranged at a side of the insulating layer200away from the substrate100, where an orthographic projection of the first conductive part300on the substrate100at least partially and an orthographic projection of the first area220on the substrate100are overlapped. The dividing line between the first area220and the second area230is indicated in a dash-dotted line as shown inFIG.2.

According to an embodiment of the present disclosure, the array substrate10includes a substrate100, an insulating layer200arranged on the substrate100and a first conductive part300. The first conductive part300is arranged at a side of the insulating layer200. In a case of manufacturing the first conductive part300, the conductive material on the insulating layer200may be patterned to form the first conductive part300. The insulating layer200is provided with the first area220and the second area230, and the first area220is arranged around at least a part of the openings210, and a distance from the first area220to the opening210is less than a distance from the second area230to the opening210. In this way, material on the first area220is more likely to flow into the opening210. An orthographic projection of the first conductive part300on the substrate100and an orthographic projection of the first area220on the substrate100are at least partially overlapped, i.e., the first conductive part300is located on the first area220. During the process of patterning the conductive material covered by photoresist on the first area220to form the first conductive part300, the photoresist is more likely to flow into the opening210, which may cause the conductive material to be over-etched, resulting in faults such as the disconnection of the first conductive part300. In view of this, in an embodiment of the present disclosure, the thickness of first area220is configured to be less than the thickness of the second area230. In this way, due to a levelling property of the photoresist, a relatively large amount of photoresist can be provided within the first area220. Even if a part of the photoresist flows toward the opening210, sufficient photoresist material will be covered on the conductive material, which can prevent the conductive material in the first area220from being over-etched, to improve the yield of the first conductive part300. In addition, since the thickness of the first area220is minor, and a thickness difference between the first area220and the opening210is minor, which can slow down the flow speed of the photoresist and further prevent the conductive material in the first area220from being over-etched, and the yield of the first conductive part is improved. Furthermore, with the minor thickness of the first area, a relatively large difference in thickness between a surface of the insulating layer200away from the substrate100and the opening210is divided into at least two minor differences in thickness. By doing so, it can further reduce the flow speed of the photoresist. Consequently, the conductive material in the first area220is prevented from being over-etched, which improves the yield of the first conductive part. Therefore, according to the embodiment of the present disclosure, a local thickness of the insulating layer200under the first conductive part300is reduced, which can improve the low yield caused by the first conductive part300is more likely to be disconnected.

According to an embodiment of the present disclosure, in a case of manufacturing the first conductive part300on the insulating layer200, the insulating layer200may be patterned first to form the opening210, the first area220and the second area220. For example, the opening210and the first area220may be formed respectively through the double-etching process. In one embodiment, the opening210and the first area220may be formed through the semi-etching process. Then a conductive material layer is arranged on the insulating layer200. Subsequently, a photoresist material layer is coated on the conductive material layer, and the photoresist layer is formed by patterning the photoresist material layer. Finally, the area of the conductive material that is not covered by the photoresist layer is removed, and the conductive material covered by the photoresist layer is remained to form the first conductive part300. In a case that the conductive material of the first area220is coated with photoresist to manufacture the first conductive part300, due to the small thickness of the first area220, the photoresist layer in the first area220may be thicker, the thickness of the photoresist layer in the first area220is greater than the thickness of the photoresist layer in the second area230. In this way, even if a part of the photoresist material in the first area220flows toward, e.g., the opening210, there will be photoresist layer sufficiently covered on the conductive material. In addition, due to the minor thickness of the first area220, the difference in thickness between the first area220and the opening210is minor, which can further reduce the flow speed of the photoresist layer toward the opening210, and the conductive material in the first area220is prevented from being over-etched, and the yield of the first conductive part300is improved. Furthermore, with the minor thickness of the first area, a relatively large difference in thickness between a surface of the insulating layer200away from the substrate100and the opening210is divided into at least two minor differences in thickness. By doing so, it can further reduce the flow speed of the photoresist. Consequently, the conductive material in the first area220is prevented from being over-etched, which improves the yield of the first conductive part300. In an embodiment, the insulating layer200is provided with an upper surface away from the substrate100. The thickness of the first area220is less than that of the second area230, consequently, an upper surface of the insulating layer200located in the first area220, is located at a side of an upper surface of the insulating layer200located in the second area230adjacent to the substrate100. In other words, a distance between the upper surface of the insulating layer200located in the first area220and the substrate100is less than a distance between the upper surface of the insulating layer200located in the second area230and the substrate100. The upper surface of the insulating layer200forms a recess201in the first area220, and more photoresist material for covering the first conductive part300is able to fall within the recess201.

The insulating layer200may be made of organic material or inorganic material. For example, the insulating layer200may be made of a material including but is not limited to polyimide, polyethylene, polyvinylidene difluoride, polyteflon, silicon oxide, silicon nitride, or the like. The insulating layer200may arranged to be adjacent to the substrate100, or other film layers may be arranged between the insulating layer200and the substrate100.

The first conductive part300may be arranged in multiple manners. The first conductive part300may be configured to transmit a data signal, a scanning signal, and a power supply voltage signal and the like. The types of the signal transmitted by the first conductive part300are not limited in the present disclosure. The first conductive part300may be configured to transmit the same signal. In one embodiment, in a case that the number of the first conductive parts300is more than one, different first conductive parts300may be configured to transmit different signals. The first conductive part300may be in a straight line shape, or the first conductive part300may further be in a shape of curved line, a zigzag line and other irregular shapes. The number of the first conductive parts300is one or more than one. For example, at least two first conductive parts300may be arranged side by side at a side of the opening210or at a peripheral side of the opening210. The first area220may be arranged around a part of the opening210. For example, in a case that the first conductive part300is arranged around a part of opening210, the first area220may be arranged around a part of the opening210. In an embodiment, in a case that the first conductive parts300are arranged at different sides of the opening210, the first area220may be arranged around the peripheral side of the opening210, as long as a thinned first area220is arranged under part of the first conductive parts300which are arranged around the opening210.

The number of the first areas220may be one or more. Reference is made toFIGS.1to5. The number of first areas220is more than one, and multiple first areas220may be arranged side by side in a direction away from the opening210. By arranging multiple first areas220, the thicknesses of the insulating layers200in multiple areas can be thinned, to better prevent the problem that the first conductive part300is more likely to be disconnected. The dividing lines between different first areas220are indicated in dash-dotted lines as shown inFIG.4.

Furthermore, by arranging multiple first areas220, different degrees of compensation can be achieved for the line width in the same area. By reasonably adjusting the position of the first area220, the first conductive part300at different positions or different positions of the first conductive part300can be compensated in different degrees, better preventing the first conductive part300from being disconnected such as broken.

In a case that the number of the first areas220is more than one, as shown inFIG.6andFIG.7, multiple first areas220may be spaced in a direction away from the opening210, the first conductive part300is arranged correspondingly in at least part of the first areas220. For example, the first conductive part300is arranged in each first area220.

In these embodiments, by spacing multiple first areas220and configuring the first conductive parts300in the first areas220correspondingly, multiple first conductive parts300are provided with corresponding first areas220, which can prevent the first conductive parts300from being disconnected.

In these embodiments, by configuring recesses at specific locations to form multiple first areas220spaced instead of reducing the overall thickness of local insulating layer200, the first conductive parts300in different line widths can be compensated to prevent the first conductive parts300from being disconnected. In addition, the impact of thinning insulating layer200on the overall flatness of the insulating layer200can be weaken, which can ensure the flatness of the surface of the insulating layer200away from the substrate100and reduce the negative impact caused by thinning the insulating layer200.

In an embodiment, among the spaced multiple first areas220, the first conductive part300is arranged in each first area220, i.e., different first conductive parts300corresponds to different first areas220. In this way, the problem of first conductive parts300being more likely to be disconnected can be prevented by the first areas220.

In a case that the number of the first areas220is more than one, the multiple first areas220may be of the same thickness. For example, multiple first areas220in the same thickness are spaced.

In other embodiments, as shown inFIG.4andFIG.5, in a case that the number of the first areas220is more than one, the thicknesses of the first areas220are gradually decreased in a direction of approaching the opening210.

In these embodiments, as approaching the first area220, the photoresist layer on the insulating layer200is more likely to flow toward the opening210, where the photoresist layer is configured to cover on the conductive material to manufacture the first conductive part300, causing that the first conductive part300is more likely to be disconnected. By gradually decreasing the thicknesses of the first areas220in the direction of approaching the opening210, the thickness of the photoresist layer on the first conductive part is increased in the direction of approaching the opening210, to better prevent the problem that the first conductive part300is more likely to be disconnected. In addition, as the thicknesses of the first areas220are gradually decreased in the direction of approaching the opening210, the difference in thickness between the opening210and the first area220closer to the opening210is reduced, further slowing down the flow speed of the photoresist layer.

In a case that the thicknesses of the first areas220are gradually decreased, the multiple first areas220may be adjacent, and the surface of the insulating layer200away from the substrate100forms a step shape. In an embodiment, one or more first conductive parts300may be arranged at each step.

In an embodiment, as shown inFIG.8, in a case that the thicknesses of the first areas220are gradually decreased, these multiple first areas220may be spaced, and each first area220forms a recess201at the surface of the insulating layer200away from the substrate100, and multiple recesses201are formed on the insulating layer200. One or more first conductive parts300may be arranged in each recess201.

In an embodiment, there are various positions for arranging the opening210. The opening210may be located in the display area or non-display area of the display panel20. The relative position relationship between the opening210and the first conductive part300may be arranged in multiple manners. The first conductive part300may be arranged around the opening21. In one embodiment, the orthographic projection of the first conductive part300on the substrate100and the orthographic projection of the opening210on the substrate100may be at least partially overlapped.

In some embodiments, as shown inFIGS.1to8, the opening210include a first opening211, the first conductive parts300and the first opening211are spaced, and at least part of the first conductive parts300are arranged around the first opening211.

In these embodiments, the first conductive part300is arranged around at least part of the first opening211. During the manufacturing process of the first conductive part300, the photoresist layer covering the first conductive part of the conductive material is more likely to flow toward the first opening211, causing disconnection of the first conductive part. According to the embodiment, by arranging the thinned first area220around the first opening211and the first conductive part300arranged on the first area220, more photoresist layers is remained on the first area220, it further prevent the problem of disconnection of the first conductive part300due to the photoresist layer is more likely to flow toward the first opening211.

The first conductive part300may be arranged around the first opening211in multiple manners. The first conductive part300may be in a straight line shape and arranged at a side of the first opening211.

In other embodiments, as shown inFIG.2, the first conductive part300includes a first segment310and a second segment320connected in sequence. The first segment310is arranged around the first opening211, and the second segment320is connected to a terminal of the first segment310, and is extend and formed in a direction away from the first opening211. An orthographic projection of the first segment310on the substrate100and an orthographic projection of the first area220on the substrate100are at least partially overlapped.

In these embodiments, the first conductive part300includes the first segment310and the second segment320. Since the first segment310is arranged around the first opening211and the second segment320is arranged away from the first opening211, the first segment310is more likely to be disconnected during manufacture. By configuring the orthographic projection of the first segment310on the substrate100to be at least partially overlapped with the orthographic projection of the first area220on the substrate100, i.e., the first segment310is located on the first area220, it can prevent the problem that the first segment310is more likely to be disconnected.

In an embodiment, the orthographic projection of the second segment320on the substrate100and the orthographic projection of the second area230on the substrate100are at least partially overlapped. In other words, the second segment320is located on the second area230. Where, the second segment320is manufactured according to normal process. Although more manufacture material of the first segment310is used due to the first segment310is arranged on the first area220, as the photoresist layer covered on the conductive material for manufacturing the first segment310flows toward the opening210, a thickness of the photoresist layer covered the conductive material for manufacturing the first segment310and that of the photoresist layer covered the conductive material for manufacturing the second segment320in the unit length are substantially identical, and the line width of the first segment310of the first conductive part300is substantially identical to the line width of the second segment320of the first conductive part300, which improves the uniformity of the distribution of the first conductive part300.

The first segment310may be in a straight-line shape.

In other embodiments, as shown inFIG.2, the first segment310may include a first sub-segment311and a second sub-segment312, where the first sub-segment311is located at a side of the first opening211in a first direction X, and the first sub-segment311is extended and formed in a second direction Y. The second sub-segment312is located at a side of the first opening211in the second direction Y, and the second sub-segment312is extended and formed in the first direction X. The second segment320is connected to a terminal of the second sub-segment312away from the first segment310, and is extended and formed in the second direction Y away from the first opening211.

In these embodiments, the first segment310is in a shape of zigzag line and includes the first sub-segment311and the second sub-segment312. The first sub-segment311and the second sub-segment312are arranged at different positions around the first opening211. The first sub-segment311and the second sub-segment312are extended and are formed in different directions. An orthographic projection of the first sub-segment311and the second sub-segment312on the substrate100at least partially overlaps with the orthographic projection of the second area230on the substrate100, which prevents the problem that the first sub-segment311and the second sub-segment312are more likely to be disconnected.

In some embodiments, the opening210further includes a second opening212. An orthographic projection of the second opening212on the substrate100at least partially overlaps with an orthographic projection of the second segment320on the substrate100. A minimum distance between the first opening211and the second opening212is greater than or equal to 25 μm.

In these embodiments, the orthographic projection of the second opening212on the substrate100and the orthographic projection of the second segment320on the substrate100are at least partially overlapped, and at least part of the second segment320passes through the second opening212. The first conductive part300is at least partially arranged between the first opening211and the second opening212. By configuring the minimum distance between the first opening211and the second opening212greater than or equal to 25 μm, it can leave sufficient space to arrange the first conductive part300. In this way, it can prevent the problem of the first conductive part300being more likely to be disconnected due to the first conductive part300and the first opening211are too close.

In an embodiment, as described above, the array substrate10includes a display area and a non-display area arranged around at least a part of the display area, and the first opening211may be located in the non-display area. In a case that the first opening211is located in the non-display area, the first opening211may be used to accommodate a control chip400. In other words, the control chip400may be a sunken/embedded control chip400. In an embodiment, the first conductive part300may include a fanout line, which is arranged in the non-display area around the first opening211, where the first opening211is configured to accommodate the control chip400. In this case, the fanout line may be disconnected easily. According to an embodiment, the thickness of the first area220is reduced to prevent the fanout line from being disconnected.

In some embodiments, a minimum distance between the first conductive part300and the first opening211is greater than or equal to 8 μm.

In conventional technology, since the distance between the first conductive part300and the first opening211is minor, the photoresist layer covered on the conductive material for manufacturing the first conductive part300is more likely to flow into the first opening211, resulting in first conductive part300being more likely to be disconnected. In these embodiments of the present disclosure, by configuring the minimum distance between the first conductive part300and the first opening211to meet the above requirement, it can prevent the above problem of the first conductive part300being more likely to be disconnected.

In an embodiment, in a case that the first opening211is located in the non-display area, for example, in a case that the first opening211is located in the non-display area and is configured to accommodate the control chip400, the minimum distance between the first conductive part300and the first opening211may be ensured to be greater than or equal to 8 μm by reducing the size of the first opening211. For example, the width of the first opening211in the first direction may be reduced to 5.6 μm approximately, to ensure that the minimum distance between the first opening211and the first sub-segment311of the first conductive part300is greater than or equal to 8 μm. By reducing the size of the first opening211, the amount of the photoresist layer flowing into the first opening211may further be reduced, where the photoresist layer is covered on the conductive material for manufacturing the first conductive part300, to prevent the problem of the first conductive part300being more likely to be disconnected. In an embodiment, the first opening211may be located in the display area, and the minimum distance between the first conductive part300and the first opening211may be adjusted. By reducing the size of the first opening211, the amount of the photoresist layer flowing into the first opening211may further be reduced, where the photoresist layer is covered on the conductive material for manufacturing the first conductive part300, to prevent the problem that the first conductive part300being more likely to be disconnected.

In some embodiments, the number of first conductive parts300is greater than one, and a minimum distance between two adjacent first conductive parts300is greater than or equal to 4 μm. In this way, it can prevent the problem that two adjacent first conductive parts300are more likely to occur short-circuit connection due to the excessively minor distance between the two adjacent first conductive parts300.

In an embodiment, the distance between two adjacent first conductive parts300may be set to 5 μm, to prevent the problem of short-circuiting between them. The distance between two adjacent first conductive parts300may be altered by changing a mask plate used for manufacturing the first conductive part300. It has been verified that the defect rate primarily due to the short-circuiting connection between the two adjacent first conductive parts300is decreased from 16% to 0% after increasing the distance between the two adjacent first conductive parts300to 5 μm, showing a significant and effective improvement.

In any one of the above embodiments, in a case that the first conductive part300is arranged around the first opening211, the first conductive part300may be a signal wire. For example, the first conductive part300is located in the non-display area NA and is a fanout line. The first conductive part300may further be part of the signal wire or a pixel driving circuit in the display panel. For example, the first conductive part300is located in the display area AA and is a source terminal or a drain terminal of the transistor.

In some embodiments, as shown inFIG.9andFIG.10, the opening210includes a third opening213, the orthographic projection of the third opening213on the substrate100and the orthographic projection of the first conductive part300on the substrate100are at least partially overlapped, and the first area220is arranged around the third opening213and adjacent to the third opening213.

In these embodiments, an orthographic projection of the third opening213on the substrate100at least partially overlaps with the orthographic projection of the first conductive part300on the substrate100, that is, the first conductive part300is arranged through the third opening213. The first area220is arranged around the third opening213and adjacent to the third opening213, i.e., no interval between the first area220and the third opening213. The material used for manufacturing the first conductive part300is relatively thick at the peripheral side of the third opening area213. In this way, it can prevent the first conductive part300adjacent to the third opening213from being disconnected. In some embodiments, the array substrate10further includes a second conductive part500, which is arranged at a side of the insulating layer200facing the substrate100. The second conductive part500overlaps with the first conductive part300to form an overlapped area. The orthographic projection of the third opening213on the substrate100at least partially overlaps with an orthographic projection of the overlapped area on the substrate100, and the first conductive part300is connected to the second conductive part500through the third opening213.

In these embodiments, the second conductive part500is located at a side of the insulating layer200facing the substrate100, i.e., the second conductive part500is located under the insulating layer200. The second conductive part500and the first conductive part300above the insulating layer200are in the via-connection through the third opening213. In other words, the third opening213is configured to connect the first conductive part300and the second conductive part500.

The relative position relationship among the third opening213, the first conductive part300, and the second conductive part500may be arranged in multiple manners. For example, the first conductive part300and the second conductive part500extend in different directions and form an overlapped area. The orthographic projection of the third opening on the substrate100at least overlaps with the orthographic projection of the overlapped area on substrate100, and the first conductive part300can be connected to the second conductive part500in the overlapped area.

The relative position relationship among the first area220, the first conductive part300and the second conductive part500may be arranged in multiple manners. For example, the line width of first conductive part300is less than that of the second conductive part500, and the orthographic projection of the first area220on the substrate100may be within the orthographic projection of the second conductive part500on the substrate100. In other words, the first area220is correspondingly within the second conductive part500. In one embodiment, in a case that the line width of first conductive part300is greater than the line width of second conductive part500, the orthographic projection of the first area220on the substrate100may be arranged within the orthographic projection of the first conductive part300on the substrate100, i.e., the first area220is correspondingly within the first conductive part300. In other embodiments, the first area220may further be arranged to extend out of the first conductive part300or the second conductive part500. In other words, the width of first area220is greater than the first conductive part300or the second conductive part500.

In an embodiment, as shown inFIG.11andFIG.12, in a case that the opening210include the third opening213, the number of the first areas220may be greater than one, and the thicknesses of multiple first areas220are gradually decreased in the direction of approaching the third opening213.

In these embodiments, as approaching the third opening213, the photoresist layer on the insulating layer200is more likely to flow into the third opening213, where the photoresist layer is configured to cover on the conductive material to manufacture the first conductive part300, causing the first conductive part300being more likely to be disconnected. By gradually decreasing the thicknesses of the first areas220in the direction of approaching the third opening213, the thickness of the photoresist layer used for manufacturing the first conductive part300is increased in the direction of approaching the third opening213. While manufacturing the first conductive part300, sufficient photoresist layer can be remained on the conductive material, which can better prevent the first conductive part300from being disconnected.

In an embodiment, reference is made toFIG.11andFIG.12. Multiple first areas220may be adjacent to each other, and the surface of the insulating layer200forms a step shape. In these embodiments, the third opening213is arranged corresponding to the same first conductive part300, and multiple first areas220are arranged to be adjacent to each other instead of spacing, which can prevent the same first conductive part300for being disconnected.

In an embodiment, in a case that the number of the first conductive parts300is greater than one, and each first conductive part300is connected to the second conductive part500through the third opening213, each first conductive part300is provided with a first area220correspondingly, to better prevent the disconnections of the multiple first conductive parts300.

In a case that the first conductive part300and the second conductive part500are in the via-connection through the third opening213, the first area220is arranged on the peripheral side of the third opening213to prevent the disconnection of the first conductive part300caused by the excessive depth of the third opening213while ensuring the performance of the array substrate10.

In an embodiment, the third opening213may be located in the display area AA or the non-display area NA. As long as there are two signal wires via-connected through the third opening213, a thinned first area220may be arranged at the peripheral side of the third opening213. For example, the third opening213is located in the display area AA, the first conductive part300and the second conductive part500transmit the same signal. For example, the first conductive part300and the second conductive part500may be configured to transmit data signals, or transmit scanning signals, or transmit power supply voltage signals and the like. The third opening213may further be located in the non-display area NA, and the first conductive part300and the second conductive part500may be fan-out lines and configured to transmit data signals.

In an embodiment, the third opening213may be located in the display area AA or the non-display area NA, as long as there are different-layer structures via-connected through the third opening213, a thinned first area220may be arranged at the peripheral side of the third opening213. In an embodiment, the first conductive part300and the second conductive part500may be signal wires arranged in different layers. For example, the first conductive part300and the second conductive part500may be power supply voltage signal wires. In one embodiment, the first conductive part300and the second conductive part500may be a non-wired conductive structure and a signal wire arranged in different layers. For example, one of the first conductive part300and the second conductive part500is a signal wire, and the other is a conductive structure electrically connected to the signal wire. For example, one of the first conductive part300and the second conductive part500may be the source terminal of a transistor, and the other is a data signal wire. In one embodiment, the first conductive part300and the second conductive part500may further be two non-wired conductive structures arranged in different layers. For example, one of the first conductive part300and the second conductive part500is a drain terminal of the transistor, and the other is a connection part configured to be connected to a pixel electrode. According to an embodiment of the present disclosure, as long as the first conductive part300is via-connected to the second conductive part500through the third opening213, the thinned first area220may be arranged at the peripheral side of the third opening213, to prevent the problem that a wire or a non-wired conductive structure on the insulating layer is more likely to be disconnected. As shown inFIG.13, a display panel20is further provided according to an embodiment of the present disclosure, the display panel20includes the array substrate10according to any one of the embodiments described above. Since the display panel20provided according to the embodiments of the present disclosure includes the array substrate10according to any one of the embodiments of the embodiments described above, the display panel20provided according to the embodiments of the present disclosure has the beneficial effects of the array substrate10according to any one of the embodiments described above, which will not be repeated herein.

In an embodiment, the display panel20may be at least one of a liquid crystal display panel, an organic light-emitting diode display panel or a micro light-emitting diode display panel. The display panel20may further be a transparent display panel, a splicing display panel and the like, as long as the display panel includes the array substrate.

As shown inFIG.14, a display device30is further provided according to embodiments of the present disclosure. Where, the display device30includes a display panel20according to any one of the embodiments described above. Since the display device30provided according to an embodiment of the present disclosure includes the display panel20according to any one of the embodiments described above, the display device30provided in the embodiments of the present disclosure has the beneficial effects of the display panel20according to any one of the embodiments described above, which will not be repeated herein.

In the embodiments of the present disclosure, the display device30includes but is not limited to a mobile phone, a personal digital assistant (PDA), a tablet computer, an e-book, a television set, an access control, a smart fixed phone, a console and other devices with display functions.

Reference is made toFIG.15.FIG.15is a schematic flowchart of a method for manufacturing an array substrate10according to an embodiment of the present disclosure.

As shown inFIG.15, according to the embodiments of the present disclosure, a method for manufacturing an array substrate10is further provided. The array substrate10may be the array substrate10provided according to any one of the embodiments described above. Reference is made toFIGS.1to15, the method for manufacturing the array substrate10may include steps S01to S04as follows.

In step S01, an insulating material layer is provided on the substrate100.

In step S02, the insulating material layer is patterned to form an insulating layer200including an opening210, a first area220and a second area230, where the thickness of the first area220is less than the thickness of the second area230, and the first area220is arranged around at least a part of the opening210.

In step S03, a conductive material layer is provided at a side of the insulating layer200away from the substrate100.

In step S04, the conductive material layer is patterned to form the first conductive part300, where an orthographic projection of the first conductive part300on the substrate100and an orthographic projection of the first area220on the substrate100are at least partially overlapped.

In the method for manufacturing the array substrate according to the embodiments of the present disclosure, an insulating material layer is first provided on the substrate100, and then the insulating material layer is patterned to form an insulating layer200through step S02. The thickness of the first area220is less than the thickness of the second area230, and the surface of the first area220away from the substrate100can form a recess201. In step S04, a photoresist layer is provided at the side of the conductive material layer away from the insulating layer200. When the conductive material layer is patterned by patterning the photoresist layer, the thickness of the photoresist layer in the first area220is relatively large. Even if part of the photoresist layer in the first area220flows toward the opening210, sufficient photoresist layer is remained in the first area220. In addition, due to the minor thickness of the first area220, the difference in thickness between the first area220and the opening210is minor, which can slow down the flow speed of the photoresist layer between the first area220and the opening210, to ensure that sufficient photoresist layer is remained in the first area220. When the conductive material layer is patterned to form the first conductive part300, the conductive material covered by the photoresist layer is remained and forms the first conductive part300. Since sufficient photoresist layer is remained in the first area220, the over-etching problem caused by insufficient photoresist layer on the first conductive part300can be improved, to prevent the first conductive part300layer on the first area220from disconnection.

In step S02, there are various methods for patterning the insulating material layer. For instance, the insulating material layer may undergo two patterning processes. In one patterning process, the opening210is formed. In the other patterning process, the first area220is formed. The area that is not subjected to patterning process forms a thicker second area230.

In some embodiments, as shown inFIG.16, step S02may include steps S021and S022as follows.

In step S021, as shown inFIG.17, a first mask plate600is provided at a side of the insulating material layer away from the substrate100. The first mask plate600includes a first via610, a first light-shielding area620and a second light-shielding area630. The light transmittance of the first light-shielding area620is greater than the light transmittance of the second light-shielding area630.

In step S022, as shown inFIG.18, the first mask plate600is irradiated from the side of the first mask plate600away from the insulating material layer to form the opening210at a position corresponding to the first via610, the first area220is formed at a position corresponding to the first light-shielding area620, and the second area230is formed at a position corresponding to the second light-shielding area630.

In these embodiments, the first mask plate600is arranged on the insulating layer200through step S021, the first mask plate600has a fully transparent area (i.e., the first via610), a semi-transparent area (i.e., the first light-shielding area620), and an opaque area (i.e., the second light-shielding area630). When the mask plate is irradiated in step S022, a greater amount of light passes through the first via610to form an opening210on the insulating layer200, while a lesser amount of light passes through the first light-shielding area620to form the first area220on the insulating layer200, and minimal to no light passes through the second light-shielding area630to form a thicker second area230. According to an embodiment of the present disclosure, by arranging the first mask plate600, the opening210, the first area220and the second area230can be formed with just one patterning process, which can simplify the manufacture process of the insulating layer200and improve the manufacture efficiency of the array substrate10.

In other embodiments, as shown inFIG.19, step S02may include steps S021′ and S022′ as follows.

In step S021′, as shown inFIG.20, a second mask plate700is provided at a side of the insulating material layer away from the substrate100. The second mask plate700includes a second via710, a third light-shielding area720and a fourth light-shielding area730, and multiple slits721are spaced in the third light-shielding area720.

In step S022′, as shown inFIG.18, the second mask plate700is irradiated from the side of the second mask plate700away from the insulating material layer to form the opening210at a position corresponding to the second via710, the first area220is formed at a position corresponding to the third light-shielding area720, and the second area230is formed at a position corresponding to the fourth light-shielding area730.

In these embodiments, a second mask plate700is first provided on the insulating layer200through step S021′. The second mask plate700has a fully transparent area and slit(s)721, which, when light passes through, create diffraction, to remove part of the insulating material to form thinned first area(s)220. Therefore, when the mask plate is irradiated in step S022′, a greater amount of light passes through the second via710to form an opening210on the insulating layer200, while a lesser amount of light passes through the third light-shielding area720to form the first area220on the insulating layer200, and minimal to no light passes through the fourth light-shielding area730to form a thicker second area230. According to an embodiment of the present disclosure, by arranging the second mask plate700, the opening210, the first area220and the second area230can be formed with just one patterning process, which can simplify the manufacture process of the insulating layer200and improve the manufacture efficiency of the array substrate10.

According to the embodiments of the present disclosure, the array substrate includes a substrate, an insulating layer arranged on the substrate and a first conductive part. The first conductive part is arranged at a side of the insulating layer. In a case of manufacturing the first conductive part, the conductive material on the insulating layer may be patterned to form the first conductive part. The insulating layer is provided with the first area and the second area, and the first area is arranged around at least a part of the opening, and a distance from the first area to the opening is less than a distance from the second area to the opening. In this way, material on the first area is more likely to flow into the opening. An orthographic projection of the first conductive part on the substrate and an orthographic projection of the first area on the substrate are at least partially overlapped, i.e., the first conductive part is located on the first area. During the process of patterning the conductive material covered by photoresist on the first area, the photoresist is more likely to flow into the opening, which may cause the conductive material to be over-etched, resulting in faults such as the disconnection of the first conductive part. In view of this, in the embodiments of the present disclosure, the thickness of first area is configured to be less than the thickness of the second area. In this way, a greater amount of photoresist can be provided within the first area. Even if a part of the photoresist flows toward the opening, sufficient photoresist material can cover the conductive material, which can prevent the conductive material in the first area from being over-etched, to improve the yield of the first conductive part. In addition, since the thickness of the first area is minor, and a thickness difference between the first area and the opening is minor, which can slow down the flow speed of the photoresist and further prevent the conductive material in the first area from being over-etched, and the yield of the first conductive part is further improved. Furthermore, with the minor thickness of the first area, a relatively large difference in thickness between a surface of the insulating layer away from the substrate and the opening is divided into at least two minor differences in thickness. By doing so, it can further reduce the flow speed of the photoresist. Consequently, the conductive material in the first area is prevented from being over-etched, which improves the yield of the first conductive part. Therefore, according to the embodiments of the present disclosure, a local thickness of the insulating layer under the first conductive part is thinned, which can improve the low yield caused by the first conductive part being more likely to be disconnected.

Although the present disclosure is described with reference to the embodiments, various improvements can be made to it and the components therein can be replaced with equivalents, without departing from the scope of the present disclosure. In particular, as long as there is no structural conflict, the various features mentioned in the various embodiments can be combined in any manner.