Powder conditioner with reduced capacitor voltage ripples

A power conditioner includes a power converter module, a detector module and a control module. The power converter module performs power conversion upon a three-phase AC power input from a first microgrid based on a PWM output to generate a three-phase AC power output for a second microgrid. The detector module detects the three-phase AC power input, and a first zero sequence current input that is received by the power converter module from the second microgrid. The control module generates the PWM output based at least on a result of the detection, such that the power converter module further receives, from the first microgrid, a second zero sequence current input which is anti-phase with the first zero sequence current input.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims priority of Taiwanese Patent Application No. 106107888, filed on Mar. 10, 2017.

FIELD

The disclosure relates to a power conditioner, and more particularly to a power conditioner with reduced ripples in capacitor voltages.

BACKGROUND

A conventional power conditioner is used to control power flow between a first microgrid and a second microgrid. Each of the first and second microgrids has a neutral terminal. The conventional power conditioner includes a first power converter that is coupled to the first microgrid and that performs AC (alternating current) to DC (direct current) conversion, a second power converter that is coupled to the second microgrid and that performs DC to AC conversion, a DC bus circuit that is coupled to the first and second microgrids, and other circuits. The DC bus circuit includes two capacitors that are coupled to each other. A common node of the capacitors is coupled to the neutral terminals of the first and second microgrids.

When the second microgrid is in an abnormal state (e.g., the second microgrid encounters frequency fluctuation and/or voltage sag), the second power converter transmits active power and/or reactive power from the capacitors to the second microgrid, so as to alleviate power disturbance of the second microgrid. Meanwhile, the first power converter transmits active power from the first microgrid to the capacitors, so that a voltage across the capacitors can be constant.

However, when the second microgrid provides three unbalanced phase voltages, a zero sequence current input received at the common node of the capacitors from the neutral terminal of the second microgrid has a non-zero amplitude, and therefore a voltage across each capacitor has a ripple component, which accelerates aging of the capacitors and may cause malfunction of the conventional power conditioner.

There are two conventional ways to reduce the ripple component of the voltage across each capacitor. The first conventional way is to increase a capacitance of each capacitor. The second conventional way is to include, in the conventional power conditioner, a power supply that provides DC voltages respectively to the capacitors. However, in the first conventional way, the capacitors would be relatively bulky; in the second conventional way, the power supply is required; and in each conventional way, the conventional power conditioner has relatively high manufacturing costs.

SUMMARY

Therefore, an object of the disclosure is to provide a power conditioner that can alleviate the drawbacks of the prior art.

According to the disclosure, the power conditioner is used to control power flow between a first microgrid and a second microgrid. Each of the first and second microgrids has a neutral terminal. The power conditioner includes a power converter module, a detector module and a control module. The power converter module is used to be coupled to the first microgrid for receiving a three-phase AC (alternating current) power input therefrom, is used to be coupled further to the second microgrid, further receives a PWM (pulse width modulation) output, and includes two capacitors that are coupled to each other. A common node of the capacitors is used to be coupled to the neutral terminal of the first microgrid, and is used to be coupled further to the neutral terminal of the second microgrid for receiving a first zero sequence current input therefrom. The power converter module performs AC to DC (direct current) to AC conversion upon the three-phase AC power input based on the PWM output to generate a DC voltage across the capacitors, and to generate a three-phase AC power output for the second microgrid. The detector module is coupled to the power converter module, detects voltages and current inputs of the three-phase AC power input to generate a first detection output, and further detects the first zero sequence current input to generate a second detection output. The control module is coupled to the detector module for receiving the first and second detection outputs therefrom, and is coupled further to the power converter module. The control module generates the PWM output for the power converter module based at least on the first and second detection outputs, such that the common node of the capacitors further receives, from the neutral terminal of the first microgrid, a second zero sequence current input which has a non-zero amplitude and is anti-phase with the first zero sequence current input when the first zero sequence current input has a non-zero amplitude.

DETAILED DESCRIPTION

Referring toFIG. 1, an embodiment of a power conditioner according to the disclosure is used to control power flow between a first microgrid11and a second microgrid12. Each of the first and second microgrids11,12is a three-phase four-wire system, has a neutral terminal110,120, a first terminal111,121, a second terminal112,122and a third terminal113,123, and provides three phase voltages (Va1, Vb1, Vc1, Va2, Vb2, Vc2) respectively at the first to third terminals (111-113,121-123) thereof. The power conditioner of this embodiment includes a power converter module2, a detector module3and a control module4.

The power converter module2includes a DC (direct current) bus circuit23, a first power converter21and a second power converter22. The DC bus circuit23includes two capacitors231,232that are coupled to each other, and that have, for example, the same capacitance. A common node (P) of the capacitors231,232is used to be coupled to the neutral terminal110of the first microgrid11, and is used to be coupled further to the neutral terminal120of the second microgrid12for receiving a first zero sequence current input (Io) therefrom. The first power converter21is used to be coupled to the first to third terminals111-113of the first microgrid11for receiving a three-phase AC (alternating current) power input therefrom, and is further coupled across the capacitors231,232. The second power converter22is coupled across the capacitors231,232, and is used to be further coupled to the first to third terminals121-123of the second microgrid12. The first and second power converters21,22cooperatively receive a PWM (pulse width modulation) output from the control module4, and cooperatively perform AC to DC to AC conversion upon the three-phase AC power input based on the PWM output to generate a DC voltage (Vdc) across the capacitors231,232, and to generate a three-phase AC power output for the second microgrid12.

Referring toFIGS. 2 and 3, in this embodiment, the PWM output includes a first group of six PWM signals (S11-S16) as shown inFIG. 2, and a second group of six PWM signals (S21-S26) as shown inFIG. 3. As shown inFIG. 2, the first power converter21includes three inductors211and six switches212. Each switch212is operable between conduction and non-conduction based on a respective PWM signal (S11-S16) of the first group. As shown inFIG. 3, the second power converter22includes six switches221and three inductors222. Each switch221is operable between conduction and non-conduction based on a respective PWM signal (S21-S26) of the second group.

Referring back toFIG. 1, the detector module3is coupled to the power converter module2, detects voltages (i.e., the phase voltages (Va1-Vc1)) and current inputs (Ia1, Ib1, Ic1) of the three-phase AC power input to generate a detection output (D1), detects voltages (i.e., the phase voltages (Va2-Vc2)) and current outputs (Ia2, Ib2, Ic2) of the three-phase AC power output to generate a detection output (D2), detects the DC voltage (Vdc) to generate a detection output (DVdc), detects the first zero sequence current input (Io) to generate a detection output (DIo), and detects voltages (V1, V2) respectively across the capacitors231,232to generate a detection output (Dc).

The control module4is coupled to the detector module3for receiving the detection outputs (D1, D2, DVdc, DIo, Dc) therefrom, is coupled further to the power converter module2, and further receives a target voltage value (Vref) and two target power values (Pref, Qref). The control module4generates the PWM output for the power converter module2based on the detection outputs (D1, D2, DVdc, DIo, Dc), the target voltage value (Vref) and the target power values (Pref, Qref) such that: (a) the DC voltage (Vdc) is stabilized at the target voltage value (Vref); (b) the common node (P) of the capacitors231,232further receives a second zero sequence current input (Io′) from the neutral terminal110of the first microgrid11; and (c) active power and reactive power of the three-phase AC power output are respectively stabilized at the target power values (Pref, Qref). When the first zero sequence current input (Io) has a non-zero amplitude, the second zero sequence current input (Io′) has a non-zero amplitude and is anti-phase with the first zero sequence current input (Io). When the amplitude of the first zero sequence current input (Io) is zero, the amplitude of the second zero sequence current input (Io′) is also zero. The first and second zero sequence current inputs (Io, Io′) are combined at the common node (P) of the capacitors231,232into a compensated zero sequence current input.

Referring toFIGS. 1 and 4, in this embodiment, the control module4includes a first control circuit41, a second control circuit42and a PWM circuit43.

The first control circuit41is coupled to the detector module3for receiving the detection outputs (D1, DVdc, DIo, Dc) therefrom, further receives the target voltage value (Vref) and generates a first control output (C1) based on the detection outputs (D1, DVdc, DIo, Dc) and the target voltage value (Vref).

The second control circuit42is coupled to the detector module3for receiving the detection output (D2) therefrom, and further receives the target power values (Pref, Qref). The second control circuit42determines whether the second microgrid12is encountering unbalanced voltage sag or not based on the detection output (D2) and a predetermined phase voltage value, and generates a second control output (C2) based on the detection output (D2), the target power values (Pref, Qref) and a result of the determination.

In this embodiment, the predetermined phase voltage value equals a rated amplitude (e.g., a rated peak amplitude) of each phase voltage (Va2-Vc2) and the second microgrid12is determined as encountering the unbalanced voltage sag when each of some (i.e., at least one but not all) of the voltages (Va2-Vc2) of the three-phase AC power output as indicated by the detection output (D2) has an amplitude (e.g., a peak amplitude) that is less than the predetermined phase voltage value. When the second microgrid12is determined as encountering the unbalanced voltage sag, the second control output (C2) is generated in a way as disclosed inFIG. 10and Equations 33-35 of “Power Controllability of a Three-Phase Converter With an Unbalanced AC Source” by Ke Ma et al., IEEE Transactions on Power Electronics, vol. 30, no. 3, pp. 1591-1604, March 2015; otherwise, the second control output (C2) is generated in a similar way, except that Equations 33-35 are modified as the followings:

The PWM circuit43is coupled to the first and second control circuits41,42for receiving the first and second control outputs (C1, C2) respectively therefrom, is coupled further to the power converter module2, and generates the PWM output for the power converter module2based on the first and second control outputs (C1, C2). In this embodiment, the PWM output is generated using sinusoidal PWM (SPWM) techniques, the PWM signals (S11-S16) (seeFIG. 2) thereof are generated based on the first control output (C1), and the PWM signals (S21-S26) (seeFIG. 3) thereof are generated based on the second control output (C2).

In this embodiment, the first control circuit41includes a command generator411, a target generator412, three calculators413,415,417, a proportional resonator414and a frame transformer416.

The command generator411is coupled to the detector module3for receiving the detection outputs (D1, DVdc) therefrom, and further receives the target voltage value (Vref). Each of the voltages (Va1-Vc1) and the current inputs (Ia1-Ic1) of the three-phase AC power input includes a positive sequence component, a negative sequence component and a zero sequence component. The command generator411generates, based on the detection outputs (D1, DVdc) and the target voltage value (VRef), first control command (Vabc) that is associated with the positive and negative sequence components of the voltages (Va1-Vc1) and the current inputs (Ia1-Ic1) of the three-phase AC power input. The command generator411further generates, based on the detection output (D1), a zero axis voltage value (V0) that is associated with the zero sequence components of the voltages (Va1-Vc1) of the three-phase AC power input, and a zero axis current value (I0) that is associated with the zero sequence components of the current inputs (Ia1-Ic1) of the three-phase AC power input.

In this embodiment, the command generator411includes two frame transformers4111,4113and an operator4112.

The frame transformer4111is coupled to the detector module3for receiving the detection output (D1) therefrom, and performs stationary frame to synchronous frame transformation (e.g., Park's transformation) upon the voltages (Va1-Vc1) and the current inputs (Ia1-Ic1) of the three-phase AC power input as indicated by the detection output (D1), so as to generate a transformation output (S1), the zero axis voltage value (V0) and the zero axis current value (I0). In this embodiment, the transformation output (S1) includes a first direct axis voltage value and a first quadrature axis voltage value (which are associated with the positive sequence components of the voltages (Va1-Vc1) of the three-phase AC power input), a second direct axis voltage value and a second quadrature axis voltage value (which are associated with the negative sequence components of the voltages (Va1-Vc1) of the three-phase AC power input), a first direct axis current value and a first quadrature axis current value (which are associated with the positive sequence components of the current inputs (Ia1-Ic1) of the three-phase AC power input), and a second direct axis current value and a second quadrature axis current value (which are associated with the negative sequence components of the current inputs (Ia1-Ic1) of the three-phase AC power input).

The operator4112is coupled to the frame transformer4111and the detector module3for receiving the transformation output (S1) and the detection output (DVdc) respectively therefrom, further receives the target voltage value (Vref), and generates an operation output (S2) based on the transformation output (S1), the detection output (DVdc) and the target voltage value (Vref). In this embodiment, the operation output (S2) includes a first output portion (which is associated with the positive sequence components of the voltages (Va1-Vc1) and the current inputs (Ia1-Ic1) of the three-phase AC power input), and a second output portion (which is associated with the negative sequence components of the voltages (Va1-Vc1) and the current inputs (Ia1-Ic1) of the three-phase AC power input). The operator4112calculates, based on the DC voltage (Vdc) indicated by the detection output (DVdc) and on the target voltage value (Vref), a first target current value that corresponds to the first direct axis current value. The operator4112generates the first output portion based on the first direct axis voltage value, the first quadrature axis voltage value, the first direct axis current value, the first quadrature axis current value, the first target current value, and a predetermined second target current value (which corresponds to the first quadrature axis current value, and which is, for example, zero). The operator4112generates the second output portion based on the second direct axis voltage value, the second quadrature axis voltage value, the second direct axis current value, the second quadrature axis current value, and a predetermined third target current value and a predetermined fourth target current value (which respectively correspond to the second direct axis current value and the second quadrature axis current value, and which are, for example, zero).

The frame transformer4113is coupled to the operator4112for receiving the operation output (S2) therefrom, and performs synchronous frame to stationary frame transformation (e.g., inverse Park's transformation) upon the operation output (S2) to generate the first control command (Vabc). In this embodiment, the first control command (Vabc) includes a first command portion that is generated based on the first output portion of the operation output (S2), and a second command portion that is generated based on the second output portion of the operation output (S2).

The target generator412is coupled to the detector module3for receiving the detection outputs (DIo, Dc) therefrom, and generates a target current value (I*) based on the detection outputs (DIo, Dc) and a predetermined threshold voltage value (Vp). In this embodiment, first, the target generator412determines whether a minimum of the voltages (V1, V2) respectively across the capacitors231,232as indicated by the detection output (Dc) is greater than the predetermined threshold voltage value (Vp), and obtains a compensation factor (k) based on a result of the determination and the detection output (Dc). When the minimum of the voltages (V1, V2) respectively across the capacitors231,232as indicated by the detection output (Dc) is determined to be greater than the predetermined threshold voltage value (Vp) (e.g., Vp=Vpeak×110%, where Vpeakdenotes a rated peak amplitude of each phase voltage (Va1-Vc1, Va2-Vc2)), the compensation factor (k) is set to a predetermined constant that is greater than zero and that is less than or equal to one (i.e., 0<k≤1). When the minimum of the voltages (V1, V2) respectively across the capacitors231,232as indicated by the detection output (Dc) is determined to be not greater than the predetermined threshold voltage value (Vp), the compensation factor (k) is obtained according to the following equation:

k=2×(Vp-V1,m⁢⁢i⁢⁢n)V1,r,Equation⁢⁢1
where V1,mindenotes the minimum of the voltages (V1, V2) respectively across the capacitors231,232as indicated by the detection output (Dc), and V1,rdenotes a difference between a maximum and a minimum of the voltage (V1, V2) across one of the capacitors231,232as indicated by the detection output (Dc). Second, the target generator412obtains the target current value (I*) based on the compensation factor (k) and the detection output (DIo) according to the following equation:
I*=−k×i0,
where i0denotes the first zero sequence current input (Io) indicated by the detection output (DIo).

The calculator413is coupled to the frame transformer4111and the target generator412for receiving the zero axis current value (I0) and the target current value (I*) respectively therefrom, and calculates a difference between the zero axis current value (I0) and the target current value (I*) to generate a difference current value (Is). In this embodiment, Is=I*−I0.

The proportional resonator414is coupled to the calculator413for receiving the difference current value (Is) therefrom, and generates a first voltage value (Vs1) based on the difference current value (Is).

The calculator415is coupled to the frame transformer4111and the proportional resonator414for receiving the zero axis voltage value (V0) and the first voltage value (Vs1) respectively therefrom, and calculates a second voltage value (Vs2) based on the zero axis voltage value (V0) and the first voltage value (Vs1). In this embodiment, Vs2=V0+Vs1.

The frame transformer416is coupled to the calculator415for receiving the second voltage value (Vs2) therefrom, and performs synchronous frame to stationary frame transformation (e.g., inverse Park's transformation) upon the second voltage value (Vs2) to generate a second control command (Vs3).

The calculator417is coupled to the frame transformers4113,416for receiving the first and second control commands (Vabc, Vs3) respectively therefrom, is coupled further to the PWM circuit43, and calculates a sum of the first and second command portions of the first control command (Vabc) and the second control command (Vs3) to generate the first control output (C1) for the PWM circuit43.

An example of parameters of the power conditioner of this embodiment and the first and second microgrids11,12are shown in the following Table 1.

TABLE 1a rated power of each of the first5kVAand second power converters 21, 22a rated root mean square amplitude220Vof each phase voltage (Va1-Vc1,Va2-Vc2)the target voltage value (Vref)700Van inductance of each inductor 211,2mH222 (see FIGS. 2 and 3)a switching frequency of each PWM20kHzsignal (S11-S16, S21-S26) (see FIGS.2 and 3)

Assuming that the power conditioner of this embodiment and the first and second microgrids11,12have the parameters shown in Table 1, and that the predetermined constant is one,FIGS. 5 and 6respectively illustrate a simulation result of the power conditioner without current compensation (e.g., the elements412-416are omitted) and a simulation result of the power conditioner of this embodiment under a first circumstance (where the target power values (Pref, Qref) are respectively 1.5 W and 0 kVar, where the capacitance of each capacitor231,232is 3.3 mF, and where the amplitude of the phase voltage (Va2) is less than the predetermined phase voltage value), andFIGS. 7 and 8respectively illustrate a simulation result of the power conditioner without current compensation and a simulation result of the power conditioner of this embodiment under a second circumstance (where the target power values (Pref, Qref) are respectively 5 kW and 0 kVar, where the capacitance of each capacitor231,232is 1.65 mF, and where the amplitude of the phase voltage (Va2) is less than the predetermined phase voltage value).

Referring toFIGS. 5 and 6, under the first circumstance, the amplitude of the first zero sequence current input (Io) is non-zero. As shown inFIG. 5, without current compensation, the second zero sequence current input (Io′) is not generated, the voltage (V1, V2) across each capacitor231,232(seeFIG. 1) has a ripple component, and the minimum of the voltages (V1, V2) respectively across the capacitors231,232(seeFIG. 1) is greater than the predetermined threshold voltage value (Vp) (i.e., 342V). In this embodiment, the second zero sequence current input (Io′) is generated. Initially, the minimum of the voltages (V1, V2) respectively across the capacitors231,232(seeFIG. 1) equals that of the power conditioner without current compensation as shown inFIG. 5, and is greater than the predetermined threshold voltage value (Vp) (i.e., 342V). Therefore, the compensation factor is set to the predetermined constant of one. Thereafter, as shown inFIG. 6, the second zero sequence current input (Io′) is non-zero in amplitude, is substantially equal to the first zero sequence current input (Io) in amplitude, and is substantially opposite to the first zero sequence current input (Io) in phase; and the ripple component of the voltage (V1, V2) across each capacitor231,232is reduced to nearly zero as compared to that of the power conditioner without current compensation.

Referring toFIGS. 7 and 8, under the second circumstance, the amplitude of the first zero sequence current input (Io) is non-zero. As shown inFIG. 7, without current compensation, the second zero sequence current input (Io′) is not generated, the voltage (V1, V2) across each capacitor231,232(seeFIG. 1) has a ripple component, and the minimum of the voltages (V1, V2) respectively across the capacitors231,232(seeFIG. 1) is less than the predetermined threshold voltage value (Vp) (i.e., 342V). In this embodiment, the second zero sequence current input (Io′) is generated. Initially, the minimum of the voltages (V1, V2) respectively across the capacitors231,232(seeFIG. 1) equals that of the power conditioner without current compensation as shown inFIG. 7, and is less than the predetermined threshold voltage value (Vp) (i.e., 342V). Therefore, the compensation factor obtained according to Equation 1 is less than one. Thereafter, as shown inFIG. 8, the second zero sequence current input (Io′) is non-zero in amplitude, is less than the first zero sequence current input (Io) in amplitude, and is opposite to the first zero sequence current input (Io) in phase; and the ripple component of the voltage (V1, V2) across each capacitor231,232is reduced as compared to that of the power conditioner without current compensation.

Referring toFIGS. 1 and 4, in view of the above, the power conditioner of this embodiment has the following advantages:

1. By virtue of the control module4that causes the first microgrid1to generate the second zero sequence current input (Io′), when the phase voltages (Va2-Vc2) are unbalanced, the ripple component of the voltage (V1, V2) of each capacitor231,232can be reduced. Therefore, aging of the capacitors231,232can be slowed down, and malfunction of the power conditioner can be prevented.

2. By virtue of the control module4that causes the first microgrid1to generate the second zero sequence current input (Io′), an increase in capacitance of each capacitor231,232is not required, and a power supply that provides DC voltages respectively to the capacitors231,232is not required. Therefore, the capacitors231,232can be relatively compact, and the power conditioner can have relatively low manufacturing costs.

It should be noted that, since the first and second power converters21,22are identical in this embodiment, the power conditioner of this embodiment can be modified such that, the first microgrid11provides power to the second microgrid12through the modified power conditioner when the second microgrid12is in an abnormal state, and that the second microgrid12provides power to the first microgrid11through the modified power conditioner when the first microgrid11is in an abnormal state. In one example of the modified power conditioner, the detector module3further detects the second zero sequence current input (Io′) to generate a detection output (DIo′), and control logic that causes the following operations is included: (a) the first control circuit41receives the detection outputs (D1, DIo) when the second microgrid12is in the abnormal state, and receives the detection outputs (D2, DIo′) when the first microgrid11is in the abnormal state; (b) the second control circuit42receives the detection output (D2) when the second microgrid12is in the abnormal state, and receives the detection output (D1) when the first microgrid11is in the abnormal state; (c) the first power converter21receives the PWM signals (S11-S16) (seeFIG. 2) of the first group when the second microgrid12is in the abnormal state, and receives the PWM signals (S21-S26) (seeFIG. 3) of the second group when the first microgrid11is in the abnormal state; and (d) the second power converter22receives the PWM signals (S21-S26) (seeFIG. 3) of the second group when the second microgrid12is in the abnormal state, and receives the PWM signals (S11-S16) (seeFIG. 2) of the first group when the first microgrid11is in the abnormal state.

While the disclosure has been described in connection with what is considered the exemplary embodiment, it is understood that the disclosure is not limited to the disclosed embodiment but is intended to cover various arrangements included within the spirit and scope of the broadest interpretation so as to encompass all such modifications and equivalent arrangements.