Methods and apparatus to improve data training of a machine learning model using a field programmable gate array

Methods, apparatus, systems, and articles of manufacture are disclosed to improve data training of a machine learning model using a field-programmable gate array (FPGA). An example system includes one or more computation modules, each of the one or more computation modules associated with a corresponding user, the one or more computation modules training first neural networks using data associated with the corresponding users, and FPGA to obtain a first set of parameters from each of the one or more computation modules, the first set of parameters associated with the first neural networks, configure a second neural network based on the first set of parameters, execute the second neural network to generate a second set of parameters, and transmit the second set of parameters to the first neural networks to update the first neural networks.

FIELD OF THE DISCLOSURE

This disclosure relates generally to machine learning and, more particularly, to methods and apparatus to improve data training of a machine learning model using a field programmable gate array (FPGA).

BACKGROUND

Machine learning models, such as neural networks, are useful tools that have demonstrated their value solving complex problems regarding pattern recognition, natural language processing, automatic speech recognition, etc. Neural networks operate, for example, using artificial neurons arranged into layers that process data from an input layer to an output layer, applying weighting values to the data during the processing of the data. Such weighting values are determined during a training process. Training a machine learning model on a large dataset is a challenging and expensive task that can take anywhere from hours to weeks to complete.

DETAILED DESCRIPTION

Machine learning workloads, such as training a machine learning model on a large dataset, are challenging and computationally expensive tasks that can take anywhere from hours to weeks to complete. For example, obtaining large volumes of data to train a machine learning model used to generate personalized learning strategies that are optimized for special needs students can take years to complete. In such examples, data collection for individual student behavior may take years to ensure that the machine learning model produces conclusive results. In some instances, the unavailability of large volumes of labeled data to train the machine learning model causes a real-time correction gap when adjusting the machine learning model over time.

Certain machine learning workloads are better suited for particular types of hardware. Such hardware is referred to as a machine learning accelerator and may include, for example, an application specific integrated circuit(s) (ASIC(s)), a central processing unit (CPU), a field programmable gate array (FPGA), a graphics processing unit (GPU), etc., and/or combinations thereof. Example approaches disclosed herein accelerate dynamic data training for artificial intelligence tasks (e.g., personalized learning, adjusting logistic schedules of public transportation, medication dosage analysis, etc.) by utilizing one or more machine learning accelerators to dynamically train machine learning model(s) used for execution of a workload.

Examples disclosed herein include a usage model including one or more personalized computation modules that are coupled and/or otherwise paired with a machine learning accelerator (e.g., an ASIC, a FPGA, etc.). In some disclosed examples, the computation modules execute personalized machine learning models that obtain data in various formats tailored to users of the computation modules. In some disclosed examples, the computation modules generate outputs such as proposed customized learning strategies for special needs students, proposed medication dosage changes for hospital patients, etc. In some disclosed examples, the computation modules transmit obtained data, machine learning model parameters, etc., to the machine learning accelerator to accelerate training of the machine learning models of the computation modules. In some disclosed examples, the FPGA provides enhanced real-time data training, data inference, and error correction processes to generate updated machine learning parameters to be used by the computation models for improved operation.

FIG.1is a block diagram of a typical machine learning system100used to train a machine learning model such as a neural network. The machine learning system100implements a design flow with machine learning including a first operation102. At the first operation102, improvement strategies are generated and/or otherwise assembled. In the example of developing customized learning strategies for special needs students, the improvement strategies may correspond to previously determined learning strategies for a particular special needs student. The previously determined learning strategies may include audio, visual, or text-based techniques tailored for an individual special needs student's education as determined by a doctor, a parent, a teacher, etc.

InFIG.1, data is collected at a second operation104. For example, the data may include the improvement strategies that are generated at the first operation102. In other examples, the data may include data that is collected using a camera (e.g., a video camera), a microphone, etc. Data may include audio of a student's speech when processing educational materials, video of the student's behavior when presented with the educational materials, etc. In response to collecting data to train the neural network at the second operation104, a subset or an entirety of the collected data is selected to be stored in a database106.

At the second operation104, training the computation module may take weeks, months, etc. For example, data collected at the second operation104may include extensive manual effort by teachers, parents, doctors, etc., associated with a special needs student. In such examples, the manual effort includes classifying data based on generic grading rubrics, analyzing answers and responses from the special needs student, tutoring feedback, etc. Similarly, sourcing of data to train the computation module at a third operation108may take weeks, months, etc., because the data source is associated with only one special needs student.

When the collected data is stored in the database106, a computation module trains a first neural network at the third operation108. The first neural network may be based on a machine learning framework such as Caffe, SqueezeNet, ResNet, TensorFlow, etc. For example, the first neural network may be a Caffe based neural network. The computation module at the third operation108may train the first neural network using the improvement strategies assembled at the first operation102, the data collected at the second operation104, etc.

InFIG.1, an FPGA obtains data and parameters at a fourth operation110when the personal computation module is trained at the third operation108. For example, the FPGA may obtain data collected at the second operation104from the computation module. In other examples, the FPGA may obtain parameters (e.g., neural network parameters) associated with the first neural network from the computation module. At the fourth operation110, the FPGA performs real-time inferencing by implementing a second neural network configured using the data, the parameters, etc., obtained from the computation module. When the FPGA detects an error using the obtained data, parameters, etc., the FPGA determines updated parameters for the first neural network that reduce and/or otherwise eliminate the error.

At a fifth operation112, the computation module or a computing system (e.g., a server) communicatively coupled to the computation module chooses a network to be implemented by the computation module. At the fifth operation112, a machine learning framework such as Caffe, SqueezeNet, ResNet, TensorFlow, etc., is selected based on the computation module. For example, the updated parameters generated by the FPGA at the fourth operation110may be mapped and/or otherwise translated to the first neural network in a format associated with Caffe. In response to the mapping at the fifth operation112, the computation module updates the first neural network at the third operation108to generate outputs based on the updated parameters.

FIG.2is a block diagram of an example machine learning system200including example computation modules202,204,206and an example FPGA208for accelerating training of neural networks executed by the computation modules202,204,206. Although three computation modules202,204,206are depicted inFIG.2, fewer or more than three computation modules202,204,206may be used. Although only the FPGA208is depicted inFIG.2, more than one FPGA208may be used.

In the illustrated example ofFIG.2, the machine learning system200is deployed in a school environment. For example, the machine learning system200may be used to generate customized learning outputs used to prepare education lesson plans for special needs students. Alternatively, the machine learning system200may be applicable to any other environment using a machine learning model, application, etc. For example, the machine learning system200may be used to adjust medication dosages for hospital patients, modify logistic schedules for public transit systems such as bus systems, train systems, etc.

InFIG.2, the computation modules202,204,206are computing systems such as a personal computer, a mobile device (e.g., a cell phone, a smart phone, a tablet such as an iPad™), a headset, or other wearable device, or any other type of computing device. Each of the computation modules202,204,206may be operated by a user (e.g., a student). InFIG.2, the computation modules202,204,206include a first example computation module202, a second example computation module204, and a third example computation module206. For example, the first computation module202may be a tablet (e.g., a tablet with a stylus) used to capture text or written data (e.g., handwritten data, mark-ups, notes, etc.) from a first student. In other examples, the second computation module204may be a laptop with an integrated camera used to capture graphical/visual data from a second student. In yet other examples, the third computation module206may be a smartwatch with an integrated microphone used to capture audio/speech from a third student. Alternatively, one or more of the students may have more than one computation module202,204,206.

In the illustrated example ofFIG.2, the computation modules202,204,206each include an example collection engine209, an example database210, an example neural network212,214,216, and an example network configurator218. The computation modules202,204,206include the collection engine209to collect and/or otherwise obtain data that can be used to train the neural networks212,214,216. The collection engine209includes means to obtain data from an input device of the computation modules202,204,206. For example, the collection engine209may obtain data from one or more input devices such as an audio sensor, a microphone, a camera (still or video), a keyboard, a button, a mouse, a touchscreen, a track-pad, a trackball, an isopoint device, and/or a voice recognition system.

In the illustrated example ofFIG.2, the collection engine209obtains example improvement strategies220,222,224including first example improvement strategies220associated with the first student, second example improvement strategies222associated with the second student, and third example improvement strategies224associated with the third student. The improvement strategies220,222224each include a pre-trained machine learning model configured and/or otherwise developed based on input from a doctor, a parent, a teacher, etc., associated with the students. For example, the pre-trained machine learning models may be neural network models with parameters determined by a medical diagnosis, behavioral tendencies, etc. In such examples, the pre-trained machine learning models may correspond to a pre-defined neural network including a baseline number of layers, neurons per layer, training iterations, etc. InFIG.2, the collection engine209stores the pre-trained machine learning models associated with the improvement strategies220,222,224in the database210.

In the illustrated example ofFIG.2, the computation modules202,204,206include the database210to record data (e.g., audio data, text data, visual data, neural network model(s), neural network parameters, etc.). The database210can be implemented by a volatile memory (e.g., a Synchronous Dynamic Random Access Memory (SDRAM), Dynamic Random Access Memory (DRAM), RAMBUS Dynamic Random Access Memory (RDRAM), etc.) and/or a non-volatile memory (e.g., flash memory). The database210can additionally or alternatively be implemented by one or more double data rate (DDR) memories, such as DDR, DDR2, DDR3, mobile DDR (mDDR), etc. The database210can additionally or alternatively be implemented by one or more mass storage devices such as hard disk drive(s), compact disk drive(s) digital versatile disk drive(s), etc. While in the illustrated example the database210is illustrated as a single database, the database210can be implemented by any number and/or type(s) of databases. Furthermore, the data stored in the database210can be in any data format such as, for example, binary data, comma delimited data, tab delimited data, structured query language (SQL) structures, etc. In some examples, the database210can be cloud-based to enable synchronous retrieving and updating.

The computation modules202,204,206ofFIG.2include the neural networks212,214,216to generate example outputs226,228,230including first example outputs226, second example outputs228, and third example outputs230. InFIG.2, the outputs226,228,230can correspond to proposed customized learning strategies for special needs students. For example, the first outputs226may include a learning strategy corresponding to a teaching lesson plan that incorporates an increased quantity of visual aids, visual aids with a particular color scheme, visual aids with a particular layout or organization, etc., where the learning strategy is customized, personalized, tailored, etc., for the first student.

The neural networks212,214,216ofFIG.2include a first example neural network212, a second example neural network214, and a third example neural network216. The neural networks212,214,216are personalized neural networks tailored and/or otherwise associated with a corresponding student. For example, the first neural network212is associated with the first student, the second neural network214is associated with the second student, and the third neural network216. For example, the first neural network212is trained based on the first improvement strategies220and data collected by the collection engine209from one or more input devices of the first computation module202.

Artificial neural networks such as the neural networks212,214,216are computer system architecture models that learn to do tasks and/or provide responses based on evaluation or “learning” from examples having known inputs and known outputs. Neural networks such as the neural networks212,214,216feature a series of interconnected nodes referred to as “neurons” or nodes. Input nodes are activated from an outside source/stimulus, such as input from the database210. The input nodes activate other internal network nodes according to connections between nodes (e.g., governed by machine parameters, prior relationships, etc.). The connections are dynamic and can change based on feedback, training, etc. By changing the connections, the outputs226,228,230of the neural networks212,214,216can be improved or optimized to produce more/most accurate results. For example, the neural networks212,214,216can be trained using information from one or more sources to map inputs to the outputs226,228,230.

Machine learning techniques, whether neural networks, deep learning networks, support vector machines, and/or other experiential/observational learning system(s), can be used to generate optimal results, locate an object in an image, understand speech and convert speech into text, and improve the relevance of search engine results, for example. Deep learning is a subset of machine learning that uses a set of algorithms to model high-level abstractions in data using a deep graph with multiple processing layers including linear and non-linear transformations. While many machine learning systems are seeded with initial features and/or network weights to be modified through learning and updating of the machine learning network, a deep learning network trains itself to identify “good” features for analysis. Using a multilayered architecture, machines (e.g., the computation modules202,204,206) employing deep learning techniques can process raw data better than machines using conventional machine learning techniques. Examining data for groups of highly correlated values or distinctive themes is facilitated using different layers of evaluation or abstraction.

In some examples, the neural networks212,214,216are the same type of neural network. In other examples, one or more of the neural networks212,214,216may be different. For example, the first and second neural networks212,214may be Caffe-based neural networks while the third neural network216may be a TensorFlow based neural network. InFIG.2, the neural networks212,214,216are convolutional neural networks (CNNs). For example, the neural networks212,214,216may segment data using convolutional filters to locate and identify learned, observable features in the data. Each filter or layer of the CNN architecture transforms the input data to increase the selectivity and invariance of the data. This abstraction of the data allows the machine to focus on the features in the data it is attempting to classify and ignore irrelevant background information.

Deep learning operates on the understanding that many datasets include high-level features which include low-level features. While examining an image, for example, rather than looking for an object, it is more efficient to look for edges that form motifs that form parts, which form the object being sought. These hierarchies of features can be found in many different forms of data. Learned observable features include objects and quantifiable regularities learned by the computation modules202,204,206during supervised learning. As the computation modules202,204,206are provided with a large set of well classified data, the computation modules202,204,206become better equipped to distinguish and extract the features pertinent to successful classification of new data.

The computation modules202,204,206ofFIG.2can properly connect data features to certain classifications as affirmed by the FPGA208. Conversely, the computation modules202,204,206can, when informed of an incorrect classification by the FPGA208, update the parameters for classification. Settings and/or other configuration information, for example, can be guided by learned use of settings and/or other configuration information and, as a system is used more (e.g., repeatedly and/or by multiple users), a number of variations and/or other possibilities for settings and/or other configuration information can be reduced for a given situation.

The neural networks212,214,216are initially configured by one or more pre-defined machine learning models included in the improvement strategies220,222,224. For example, the first neural network212may be initially configured using a pre-defined machine learning model included in the first improvement strategies220. In such examples, the pre-defined machine learning model of the first neural network212may be subsequently trained on a set of expert classified data from the database210. This set of data builds the first parameters for the first neural network212, and this would be the stage of supervised learning. During the stage of supervised learning, the first neural network212can be tested whether the desired behavior has been achieved.

In some examples, the neural networks212,214,216calculate a loss function to measure an inconsistency or a difference between a predicted value of the neural networks212,214,216and an actual value assigned to data stored in the corresponding database210. For example, the first neural network212may obtain data from the database210such as a handwritten sample from the first student. The handwritten sample may have a first classification that has been verified and/or otherwise validated by a doctor, a teacher, etc., associated with the first student. The first neural network212may classify the handwritten sample with a second classification. The first neural network212may calculate a loss function based on a comparison of the first and second classifications. For example, the first neural network212may calculate the loss function by calculating a difference between an actual value associated with the first classification and a predicted value associated with the second classification.

In some examples, the neural networks212,214,216determine whether a loss function threshold has been satisfied. For example, the first neural network212may determine whether the loss function associated with the first and second classifications satisfies the loss function threshold. The first neural network212may compare the difference between the actual and predicted values to a loss function threshold value. The first neural network212may determine that the difference satisfies the loss function threshold value when the difference is greater than the loss function threshold value.

In some examples, the neural networks212,214,216determine parameter adjustments to reduce the loss function. For example, the first neural network212may determine to adjust a network topology, artificial neuron weights, bias values, a quantity of activation layers, etc., of the first neural network212when the loss function threshold has been satisfied. For example, the first neural network212may continuously update and train the first neural network212until the loss function has been minimized and/or cannot be reduced further. In such examples, the first neural network212may obtain and process (e.g., iteratively obtain and process) data from the database210to train the first neural network212.

Once a desired neural network behavior has been achieved (e.g., the computation modules202,204,206have been trained to operate according to a specified threshold or accuracy threshold, etc.), the neural networks212,214,216of the computation modules202,204,206can be deployed for operation (e.g., testing the neural networks212,214,216with “real” data, new data, query data, etc.). During operation, neural network classifications can be confirmed or denied by the FPGA208to continue to improve and/or accelerate the training of neural network behavior. The neural networks212,214,216are then in a state of transfer learning, as parameters for classification that determine neural network behavior are updated based on ongoing interactions, where the updated parameters are determined by the FPGA208.

In the illustrated example ofFIG.2, the machine learning system200includes the FPGA208to accelerate and/or otherwise improve training of the neural networks212,214,216of the computation modules202,204,206. The FPGA208includes one or more machine learning models that can be adapted, modified, and/or otherwise configured based on data, parameters, etc., obtained from the computation modules202,204,206via an example network232. For example, the FPGA208may include a neural network that synthesizes data, parameters, etc., obtained from one or more of the computation modules202,204,206. In other examples, the FPGA208may include a neural network that corresponds to each of the computation modules202,204,206. For example, the FPGA208may include a first FPGA neural network that uses data, parameters, etc., from the first neural network212, a second FPGA neural network that uses data, parameters, etc., from the second neural network214, a third FPGA neural network that uses data, parameters, etc., from the third neural network216, etc.

InFIG.2, the FPGA208is initially loaded with a pre-trained machine learning model such as an inference engine. For example, the FPGA208may obtain data from the computation modules202,204,206and determine whether a classification error is generated by processing the obtained data with the inference engine. In such examples, the FPGA208may generate new parameters that can be used to update one or more of the computation modules202,204,206to reduce and/or otherwise eliminate the classification error.

The FPGA208is re-programmed in response to obtaining data, parameters, etc., from one or more of the computation modules202,204,206. For example, the FPGA208may obtain parameters of the first neural network212. For example, the parameters may include a trained network topology, weights, bias values, etc., of the first neural network212. The FPGA208may run a model optimizer to generate an optimized Intermediate Representation (IR) of the first neural network212based on the parameters. For example, an IR can correspond to a data structure or code used by the FPGA208to represent source code. In such examples, the IR can correspond to a representation of a program between a source language (e.g., a programming language associated with the first neural network212) and a target language (e.g., a programming language associated with the FPGA208), where the program may be independent of the source language and the target language. The FPGA208may be re-programmed to implement a neural network to test the IR of the first neural network212. For example, the FPGA208may use the inference engine to test the first neural network212in the IR format with data (e.g., text, an image, etc.) obtained from the first computation module202. In such examples, the FPGA208may detect classification errors when processing the data.

In some examples, the model optimizer of the FPGA208performs static, compilation-time analysis of the neural networks212,214,216to optimize execution on the computation modules202,204,206. In some examples, the model optimizer included in the FPGA208performs horizontal and vertical layer fusion and redundant network branch pruning. In some examples, the model optimizer performs the fusion and pruning before quantizing the network weights of the neural networks212,214,216. In some examples, the model optimizer feeds the reduced, quantized network to the inference engine, which further optimizes inference for the FPGA208with an emphasis on footprint reduction (e.g., a reduction in resources of the FPGA208used to test the neural networks212,214,216).

In some examples, the FPGA208generates updated parameters, configurations, etc., of the neural networks212,214,216when a classification error is detected. For example, when detecting a classification error based on the first neural network212, the FPGA208may generate a network topology, a weight, a bias value, etc., that can be deployed to the first computation module202to update the first neural network212.

In some examples, the FPGA208is re-programmed when the FPGA208obtains data, parameters, etc., from all of the computation modules202,204,206. For example, the FPGA208may generate an IR corresponding to a synthesis or combination of the neural networks212,214,216. In such examples, the FPGA208may re-program itself to test the IR and determine whether classification errors are generated when using data from the first computation module202, the second computation module204, the third computation module206, etc.

In some examples, the FPGA208is re-programmed between different tests of the neural networks212,214,216. For example, the FPGA208may generate a first IR based on the first neural network212, re-program itself using a first configuration to test the first IR, and generate first updated parameters for the first neural network212to use when updating. In response to generating the first updated parameters, the FPGA208may generate a second IR based on the second neural network212, re-program itself using a second configuration different from the first configuration to test the second IR, and generate second updated parameters for the second neural network214, where the second updated parameters are different from the first updated parameters.

In some examples, the FPGA208filters data (e.g., uncleaned data) obtained by the computation modules202,204,206. For example, the FPGA208may test an IR generated based on parameters obtained from the first computation module202by using data collected by the collection engine209of the first computation module202. For example, the FPGA208may obtain an image from the database210of the first computation module202. The FPGA208may test the IR using the image and determine that the image produces an arbitrary or non-relevant classification. For example, an image that is blurry or of an item such as a ceiling fan, a classroom clock, etc., that is not relevant to generating an education lesson plan, may cause the FPGA208to generate a classification that can skew updated parameters to be sent to the first computation module202. In such examples, the FPGA208may identify and/or otherwise flag the image for removal from the database210of the first computation module202. For example, the FPGA208may transmit a command, an instruction, etc., to the first computation module202to delete the image from the database210.

In the illustrated example ofFIG.2, the FPGA208transmits updated parameters, data management instructions (e.g., instructions to remove data from the database210), etc., to the network configurator218of the computation modules202,204,206via the network232. InFIG.2, the computation modules202,204,206include the network configurator218to map and/or otherwise translate parameters in a first format from the FPGA208to parameters in a second format based on a configuration, a type, etc., of the neural networks212,214,216. For example, the FPGA208may transmit neural network parameters based on Caffe to the network configurator218of the first computation module202that is running TensorFlow. In such examples, the network configurator218may translate the Caffe neural network parameters to TensorFlow neural network parameters. In other examples, the network configurator218may convert a new network topology based on Caffe generated by the FPGA208to a new network topology based on TensorFlow of the first neural network212by adjusting a number of activation layers, a number of pooling layers, biasing values, etc., of the first neural network212.

In the illustrated example ofFIG.2, the neural networks212,214,216include means to configure, modify, and/or otherwise update the neural networks212,214,216based on parameters received, processed, and mapped by the network configurator218. For example, the network configurator218may transmit the updated parameters to the neural networks212,214,216and the neural networks212,214,216may deploy a new instance of the neural networks212,214,216based on the updated parameters.

InFIG.2, the neural networks212,214,216include means to train the neural networks212,214,216based on data obtained by the collection engine209. The neural networks212,214,216include means to improve and/or otherwise optimize the neural networks212,214,216based on the training. For example, the neural networks212,214,216may adjust one or more weights, bias values, etc., of the neural networks212,214,216as increased data are collected by the collection engine209and classified by the neural networks212,214,216. In other examples, the neural networks212,214,216may adjust a quantity of activation layers, a quantity of pooling layers, etc., or any other CNN parameter based on the increased collection of data.

Further shown in the example ofFIG.2, the machine learning system200includes an example environment collection engine234to collect and/or otherwise obtain data that can be used to train the neural networks212,214,216. InFIG.2, the environment collection engine234is a classroom data collector. In some examples, the environment collection engine234is monitoring and obtaining data in the same classroom as the first through third students ofFIG.2. Additionally or alternatively, the environment collection engine234may monitor and obtain data in a different classroom. For example, the environment collection engine234may correspond to a set of input devices in one or more classrooms, hospital rooms, train stations, etc.

In the illustrated example ofFIG.2, the environment collection engine234includes means to obtain data from an input device such as an audio sensor, a microphone, a camera (still or video), and/or a voice recognition system that is monitoring an entire classroom or area. In such examples, the environment collection engine234may be obtaining behavioral data associated with the first student, the second student, and the third student. The behavioral data may include how the students interact with each other, how the students as a group react to presented educational materials, etc. In some examples, the environment collection engine234obtains data related to the students that the computation modules202,204,206may not capture (e.g., when the first student walks away from the first computation module202). Such behavioral data may be used by the FPGA208to improve the neural networks212,214,216by testing the neural networks212,214,216with data that the neural networks212,214,216have not yet obtained and/or processed.

The network232of the illustrated example ofFIG.2is the Internet. However, the network232may be implemented using any suitable wired and/or wireless network(s) including, for example, one or more data buses, one or more Local Area Networks (LANs), one or more wireless LANs, one or more cellular networks, one or more private networks, one or more public networks, etc. The network232enables the computation modules202,204,206to be in communication with the FPGA208.

While an example manner of implementing the computation modules202,204,206is illustrated inFIG.2, one or more of the elements, processes, and/or devices illustrated inFIG.2may be combined, divided, re-arranged, omitted, eliminated, and/or implemented in any other way. Further, the example collection engine209, the example database210, the example neural networks212,214,216, the example network configurator218, and/or, more generally, the example computation modules202,204,206ofFIG.2may be implemented by hardware, software, firmware, and/or any combination of hardware, software, and/or firmware. Thus, for example, any of the example collection engine209, the example database210, the example neural networks212,214,216, the example network configurator218, and/or, more generally, the example computation modules202,204,206could be implemented by one or more analog or digital circuit(s), logic circuits, programmable processor(s), programmable controller(s), graphics processing unit(s) (GPU(s)), digital signal processor(s) (DSP(s)), application specific integrated circuit(s) (ASIC(s)), programmable logic device(s) (PLD(s)), and/or field programmable logic device(s) (FPLD(s)). When reading any of the apparatus or system claims of this patent to cover a purely software and/or firmware implementation, at least one of the example collection engine209, the example database210, the example neural networks212,214,216, and/or the example network configurator218is/are hereby expressly defined to include a non-transitory computer readable storage device or storage disk such as a memory, a digital versatile disk (DVD), a compact disk (CD), a Blu-ray disk, etc., including the software and/or firmware. Further still, the example computation modules202,204,206ofFIG.2may include one or more elements, processes, and/or devices in addition to, or instead of, those illustrated inFIG.2, and/or may include more than one of any or all of the illustrated elements, processes, and devices. As used herein, the phrase “in communication,” including variations thereof, encompasses direct communication and/or indirect communication through one or more intermediary components, and does not require direct physical (e.g., wired) communication and/or constant communication, but rather additionally includes selective communication at periodic intervals, scheduled intervals, aperiodic intervals, and/or one-time events.

FIG.3is a schematic illustration of an example inference design flow300corresponding to operation of the FPGA208ofFIG.2. InFIG.3, the FPGA208operates an example FPGA neural network302including an example input layer304, example hidden layers306,308, and an example output layer310. The input layer304of the FGPA neural network302obtains data from the computation modules202,204,206ofFIG.2. For example, the input layer304may obtain data from the database210of the first computation module202, neural network parameters associated with the first neural network212, etc. The input layer304includes first example artificial neurons312that retrieve data such as text-based data, graphical/visual-based data, audio/speech data, etc., to the FPGA neural network302for processing.

In the illustrated example ofFIG.3, the FPGA neural network302includes a first example hidden layer306and a second example hidden layer308. The first and second hidden layers306,308are disposed between the input layer304and the output layer310. The first hidden layer306includes second example artificial neurons314and the second hidden layer308includes third example artificial neurons316. InFIG.3, the FPGA neural network302calculates and/or otherwise determines values of the second artificial neurons314and the third artificial neurons316by multiplying and accumulating neuron values and edge weights from previous layers. For example, the third artificial neurons316may obtain a set of weighted inputs associated with the second artificial neurons314and calculate example output(s)318through example activation function(s)320.

In the illustrated example ofFIG.3, the FPGA neural network302is operative to fine-tune and/or calibrate weighted inputs of the second artificial neurons314, the third artificial neurons316, etc., through backpropagation. For example, the FPGA208can perform a forward pass through the FPGA neural network302by taking a sample at the input layer304, proceed through the hidden layers306,308, and generate a prediction at the output layer310. When the FPGA208is performing an inference function, the FPGA208performs the forward pass to obtain the prediction for a given sample input. For accelerated training of the neural networks212,214,216ofFIG.2, a prediction error from the forward pass is then fed back during a backward pass to update the network weights of the second artificial neurons314, the third artificial neurons316, etc.

InFIG.3, the FPGA208accelerates the training of the neural networks212,214,216by setting the network weights of the second artificial neurons314and the third artificial neurons316based on the parameters obtained from the computation modules202,204,206. For example, the FPGA208may obtain neural network parameters of the first neural network212ofFIG.2including a network topology, network weights, etc. In such examples, the FPGA208may adjust the network topology of the FPGA neural network302to match and/or otherwise be based on the network topology of the first neural network212. In other examples, the FPGA208may adjust the weights of the second artificial neurons314and the third artificial neurons316based on the network weights obtained from the first neural network212. For example, the FPGA208may perform such adjustments to the FPGA neural network302by inserting example FPGA connections322between layers of the FPGA neural network302. In some examples the FPGA connections322may sample outputs of layers and provide intermediary feedback. For example, the FPGA connections322disposed between the first hidden layer306and the second hidden layer308may sample outputs from the first hidden layer306and adjust network weights elsewhere in the FPGA neural network302based on the sampled outputs.

FIG.4depicts an example deep learning architecture (DLA)400of the FPGA208ofFIG.2. The DLA400corresponds to a block diagram of hardware and/or software used to implement the FPGA208ofFIG.2. The DLA400ofFIG.4obtains data from example memory402. InFIG.4, the memory402is DDR off-chip memory. Alternatively, the memory402may be included in the DLA400. InFIG.4, the DLA includes an example stream buffer404, an example processing element (PE) array406, and an example interconnect and width adapters408. The stream buffer404retrieves and/or otherwise obtains data to process from the memory402. InFIG.4, the stream buffer404is on-chip (e.g., included in the FPGA208).

In the illustrated example ofFIG.4, the PE array406includes example PE elements410to process incoming data. For example, each of the PE elements410may include an accumulator, a multiplier, a comparator, etc., and/or a combination thereof. For example, the PE array406may perform convolution operations on input images using Red-Green-Blue pixel values associated with the input images. The interconnect and width adapters408ofFIG.4facilitate communication between the PE array406and example convolution functions412,414,416including an example activation convolution function412, an example max pool convolution function414, and an example local response normalization (LRN) convolution function416.

InFIG.4, the interconnect and width adapters408can configure the PE array406based on a convolution function to be performed. For example, the interconnect and width adapters408may obtain parameters associated with the activation convolution function412and transmit the parameters to the PE array406via the stream buffer404. In such examples, the interconnect and width adapters408may configure one or more of the PE elements410based on the parameters. In other examples, the interconnect and width adapters408may configure one or more of the PE elements410based on parameters associated with the max pool convolution function414, the LRN convolution function416, etc. InFIG.4, the interconnect and width adapters408is operative to transmit data (e.g., output data, convolution outputs, PE array outputs, etc.) to the memory402.

FIG.5is a block diagram of an example implementation of the FPGA208ofFIG.2. InFIG.5, the FPGA208obtains information from the computation modules202,204,206ofFIG.2. InFIG.5, the FPGA208can obtain information including an example CNN model502corresponding to one of the neural networks212,214,216. InFIG.5, the FPGA208can obtain information including neural network parameters such as example model weights (e.g., network weights, neuron weights, etc.)504corresponding to the CNN model502. For example, the CNN model502may correspond to a network topology and the model weights504may correspond to weights assigned to artificial neurons included in the network topology.

In the illustrated example ofFIG.5, the FPGA208includes an example model optimizer506to generate a first example IR508and a second example IR510. For example, the model optimizer506may perform static, compilation-time analysis of the CNN model502, the model weights504, etc., to optimize execution on the FPGA208. InFIG.5, the model optimizer506generates the first IR508based on the CNN model502. InFIG.5, the first IR508is an XML file (Graph.xml), which corresponds to a representation of the network topology of the CNN model502. InFIG.5, the model optimizer506generates the second IR510based on the model weights504. InFIG.5, the second IR510is a bin file (Graph.bin), which corresponds to a representation of the model weights504.

In some examples, the model optimizer506performs horizontal and vertical layer fusion and redundant network branch pruning on the CNN model502, the model weights504, etc., to generate the first and second IR508,510. For example, the model optimizer506may determine that one or more layers, connections, etc., of the CNN model502are not used and can be removed by the model optimizer506. In the illustrated example ofFIG.5, the model optimizer506feeds the reduced, quantized network corresponding to the first and second IR508,510to an example inference engine512. The inference engine512ofFIG.5applies logical rules to a knowledge base and deduces new knowledge or inferences. For example, the inference engine512may apply logical rules to data obtained from the computation modules202,204,206to generate new classifications, outputs, etc. In such examples, additional rules in the inference engine512can be triggered as additional data is obtained from the computation modules202,204,206. In some examples, the inference engine512can adjust the first and second IR508,510prior to being compiled by the DLA400ofFIG.4.

In the illustrated example ofFIG.5, the DLA400ofFIG.4includes an example high-graph compiler516and an example assembler518. InFIG.5, the high-graph compiler516is operative to compile a high-level computation graph into an IR corresponding to optimized hardware architecture, machine code, etc. For example, the high-graph compiler516may compile and/or otherwise translate the first and second IR508,510into a third IR corresponding to a configuration of the FPGA208. In other examples, the high-graph compiler516may compile and/or otherwise translate the first and second IR508,510into a fourth IR corresponding to machine readable instructions.

InFIG.5, the high-graph compiler516can generate an IR corresponding to the hardware architecture, the machine code, etc., by performing graph analysis and/or transformation passes. For example, the high-graph compiler516may perform graph analysis including at least one of addressing, slice analysis, or slice offsets on the first and second IR508,510. For example, the high-graph compiler516may generate addresses for artificial neurons included in the CNN model502. In other examples, the high-graph compiler516may determine slices or biases included in the first and second IR508,510.

In the illustrated example ofFIG.5, the high-graph compiler516transmits output(s) (e.g., the third IR, the fourth IR, etc.) to the assembler518. InFIG.5, the DLA400includes the assembler518to generate a hardware configuration, machine readable instructions, etc., based on the third and fourth IR. For example, the assembler518may convert the third IR into a hardware configuration of the FPGA208. For example, the FPGA208may program itself based on the hardware configuration based on the third IR. In such examples, the FPGA208may process data from the computation modules202,204,206at runtime520using the hardware configuration. In other examples, the assembler518may convert the fourth IR into computer readable instructions. For example, the assembler518may convert the fourth IR binary code.

In operation, the FPGA208obtains information from one or more of the computation modules202,204,206to generate a FPGA neural network that can be executed at runtime520. For example, the FPGA neural network may correspond to the FPGA neural network302ofFIG.3. For example, the FPGA208may execute the FPGA neural network302that corresponds to the first neural network212ofFIG.2. In such examples, the FPGA208may obtain data from the database210of the first computation module202, process the data with the FPGA neural network302, and generate outputs based on the processing. The FPGA neural network302may generate classifications, identify the data, etc. The FPGA neural network302may compare the classifications, the identifications, etc., to the classifications, the identifications, etc., generated by the first neural network212. In such examples, the FGPA neural network302executing at runtime520may determine whether the first neural network212can be adjusted. The FPGA neural network302that is operative on the FPGA208may generate and transmit a network topology, neural network parameter(s), etc., to the network configurator218of the first computation module202in response to the determination.

Flowcharts representative of example hardware logic, machine readable instructions, hardware implemented state machines, and/or any combination thereof for implementing the computation modules202,204,206ofFIG.2and/or the FPGA208ofFIGS.2,3, and/or5is shown inFIGS.6-7. The machine readable instructions may be an executable program or portion of an executable program for execution by a computer processor such as the processor812shown in the example processor platform800discussed below in connection withFIG.8. The program may be embodied in software stored on a non-transitory computer readable storage medium such as a CD-ROM, a floppy disk, a hard drive, a DVD, a Blu-ray disk, or a memory associated with the processor812, but the entire program and/or parts thereof could alternatively be executed by a device other than the processor812and/or embodied in firmware or dedicated hardware. Further, although the example program is described with reference to the flowcharts illustrated inFIGS.6-7, many other methods of implementing the example computation modules202,204,206and/or the FPGA208may alternatively be used. For example, the order of execution of the blocks may be changed, and/or some of the blocks described may be changed, eliminated, or combined. Additionally or alternatively, any or all of the blocks may be implemented by one or more hardware circuits (e.g., discrete and/or integrated analog and/or digital circuitry, an FPGA, an ASIC, a comparator, an operational-amplifier (op-amp), a logic circuit, etc.) structured to perform the corresponding operation without executing software or firmware.

FIG.6is a flowchart representative of example machine readable instructions600which may be executed to implement one or more of the computation modules202,204,206ofFIG.2to train one or more of the neural networks212,214,216ofFIG.2. The machine readable instructions600ofFIG.6begin at block602, at which the computation modules202,204,206load a pre-trained machine learning model. For example, the first computation module202may configure the first neural network212based on a pre-trained machine learning model included in the first improvement strategies220.

At block604, the computation modules202,204,206assign weights to the pre-trained machine learning model. For example, the first neural network212may assign artificial neuron weights, bias values, etc., to the first neural network212. In some examples, the artificial neuron weights, bias values, etc., are randomly generated. In other examples, the artificial neuron weights, bias values, etc., are assigned using default values included in the database210of the first computation module202.

At block606, the computation modules202,204,206select data to process. For example, the first neural network212may obtain text data from the database210. In such examples, the text data may be handwritten data, mark-up notes on education materials, etc., generated by the first student. For example, the text data may be a handwriting sample validated and/or otherwise classified by a teacher.

At block608, the computation modules202,204,206calculate a loss function. For example, the first neural network212may calculate a loss function that is used to measure an inconsistency, a difference, etc., between a predicted value of the first neural network212and an actual value assigned to the text data by the teacher.

At block610, the computation modules202,204,206determine whether a loss function threshold has been satisfied. For example, the first neural network212may compare a first value of the difference between the predicted value and the actual value to a second value of the loss function threshold and determine whether the first value satisfies the loss function threshold. In such examples, the first value may satisfy the loss function threshold by being greater than the second value. For example, the first value may correspond that the predicted value is too inaccurate when compared to the actual value. In such examples, the first value may be greater than the second value, where an increase in the first value may correspond to a decrease in accuracy of the first neural network212.

If, at block610, the computation modules202,204,206determine that the loss function threshold has not been satisfied, control proceeds to block616to determine whether to select additional data to process. If, at block610, the computation modules202,204,206determine that the loss function threshold has been satisfied, then, at block612, the computation modules202,204,206determine parameter adjustments to reduce the loss function. For example, the first neural network212may generate an updated network topology, artificial neuron weights, bias values, etc., to reduce the loss function.

At block614, the computation modules202,204,206adjust the neural network. For example, the first neural network212may train and/or otherwise update the first neural network212using the parameters determined at block612.

At block616, the computation modules202,204,206determine whether to select additional data to process. For example, the first neural network212may select another instance of text-based data from the database210. In other examples, the first neural network212may determine not to select additional data as the loss function has been determined to have been optimized and/or otherwise cannot be reduced further.

If, at block616, the computation modules202,204,206determine to select additional data to process, control returns to block606to select additional data to process, otherwise the machine readable instructions600ofFIG.6conclude.

FIG.7is a flowchart representative of example machine readable instructions700which may be executed to implement the FPGA208ofFIG.2to accelerate the training of one or more of the neural networks212,214,216ofFIG.2. The machine readable instructions700ofFIG.7begin at block702, at which the FPGA208obtains neural network information from computation module(s). For example, the model optimizer506ofFIG.5may obtain the CNN model502and the model weights504ofFIG.5. In such examples, the CNN model502and the model weights504may correspond to the first neural network212ofFIG.2.

At block704, the FPGA208generates intermediate representation(s). For example, the model optimizer506may generate the first IR508based on the CNN model502and the second IR510based on the model weights504.

At block706, the FPGA208adjusts the intermediate representation(s). For example, the inference engine512ofFIG.5may adjust the first IR508and/or the second IR510.

At block708, the FPGA208compiles the intermediate representation(s). For example, the high-graph compiler516ofFIG.5may compile the first IR508and the second IR510into a third IR. In such examples, the third IR may correspond to a hardware configuration of the FPGA208, machine readable instructions, etc.

At block710, the FPGA208assembles output(s). For example, the assembler518ofFIG.5may generate a hardware configuration of the FPGA208, readable instructions, etc., based on the third IR generated by the high-graph compiler516.

At block712, the FPGA208executes output(s) at runtime. For example, the FPGA208may re-program itself based on the hardware configuration generated by the assembler518. In such examples, the FPGA208may execute the FPGA neural network302using the hardware configuration. The FPGA neural network302may process data obtained from the first computation module202at runtime520ofFIG.5.

At block714, the FPGA208determines whether neural network information from the computation module(s) is to be adjusted. For example, the FPGA neural network302executing at runtime520may generate a classification of data obtained from the first computation module202. In such example, the FPGA neural network302may compare the classification of the data to a classification determined by the first neural network212. The FPGA neural network302may determine that the first neural network212is to be updated based on the comparison.

If, at block714, the FPGA208determines that neural network information from the computation module(s) is not to be adjusted, the machine readable instructions700ofFIG.7conclude. If, at block714, the FPGA208determines that neural network information from the computation module(s) is to be adjusted, then, at block716, the FPGA208generates neural network adjustments. For example, the FPGA208may generate an updated network topology, artificial neuron weights, bias values, a quantity of activation layers, etc., associated with the first neural network212.

At block718, the FPGA208adjusts the neural network of the computation module(s). For example, the FPGA208may transmit the neural network adjustments to the network configurator218of the first computation module202. When the network configurator218receives the adjustments, the network configurator218may adjust the first neural network212based on the adjustments. In response to the adjustment, the first neural network212may process data from the database210of the first computation module202using the adjustments generated by the FPGA208. In response to adjusting the neural network of the computation module(s), the machine readable instructions700ofFIG.7conclude.

FIG.8is a block diagram of an example processor platform800structured to execute the instructions ofFIG.6to implement one of the computation modules202,204,206ofFIG.2. The processor platform800can be, for example, a personal computer, a workstation, a self-learning machine (e.g., a neural network), a mobile device (e.g., a cell phone, a smart phone, a tablet such as an iPad™), a personal digital assistant (PDA), a personal video recorder, a headset or other wearable device, or any other type of computing device.

The processor platform800of the illustrated example includes a processor812. The processor812of the illustrated example is hardware. For example, the processor812can be implemented by one or more integrated circuits, logic circuits, microprocessors, GPUs, DSPs, or controllers from any desired family or manufacturer. The hardware processor may be a semiconductor based (e.g., silicon based) device. In this example, the processor812implements the collection engine209, the neural networks212,214,216, and the network configurator218.

The processor platform800of the illustrated example also includes an interface circuit820. The interface circuit820may be implemented by any type of interface standard, such as an Ethernet interface, a universal serial bus (USB), a Bluetooth® interface, a near field communication (NFC) interface, and/or a PCI express interface.

In the illustrated example, one or more input devices822are connected to the interface circuit820. The input device(s)822permit(s) a user to enter data and/or commands into the processor812. The input device(s)822can be implemented by, for example, an audio sensor, a microphone, a camera (still or video), a keyboard, a button, a mouse, a touchscreen, a track-pad, a trackball, an isopoint device, and/or a voice recognition system.

The processor platform800of the illustrated example also includes one or more mass storage devices828for storing software and/or data. Examples of such mass storage devices828include floppy disk drives, hard drive disks, compact disk drives, Blu-ray disk drives, redundant array of independent disks (RAID) systems, and digital versatile disk (DVD) drives. In this example, the mass storage devices828implement the database210ofFIG.2.

The machine executable instructions832ofFIG.6may be stored in the mass storage device828, in the volatile memory814, in the non-volatile memory816, and/or on a removable non-transitory computer readable storage medium such as a CD or DVD.

FIG.9is a block diagram of an example processor platform900structured to execute the instructions ofFIG.7to implement the FPGA208ofFIGS.2,3, and/or5. The processor platform900can be, for example, a server, a personal computer, a workstation, a self-learning machine (e.g., a neural network), or any other type of computing device.

The processor platform900of the illustrated example includes a processor912. The processor912of the illustrated example is hardware. For example, the processor912can be implemented by one or more integrated circuits, logic circuits, microprocessors, GPUs, DSPs, or controllers from any desired family or manufacturer. The hardware processor may be a semiconductor based (e.g., silicon based) device. In this example, the processor912implements the model optimizer506, the inference engine512, the high-graph compiler516, and the assembler518ofFIG.5.

The processor platform900of the illustrated example also includes an interface circuit920. The interface circuit920may be implemented by any type of interface standard, such as an Ethernet interface, a universal serial bus (USB), a Bluetooth® interface, a near field communication (NFC) interface, and/or a PCI express interface.

In the illustrated example, one or more input devices922are connected to the interface circuit920. The input device(s)922permit(s) a user to enter data and/or commands into the processor912. The input device(s)922can be implemented by, for example, an audio sensor, a microphone, a camera (still or video), a keyboard, a button, a mouse, a touchscreen, a track-pad, a trackball, an isopoint device, and/or a voice recognition system.

The processor platform900of the illustrated example also includes one or more mass storage devices928for storing software and/or data. Examples of such mass storage devices928include floppy disk drives, hard drive disks, compact disk drives, Blu-ray disk drives, redundant array of independent disks (RAID) systems, and digital versatile disk (DVD) drives.

The machine executable instructions932ofFIG.7may be stored in the mass storage device928, in the volatile memory914, in the non-volatile memory916, and/or on a removable non-transitory computer readable storage medium such as a CD or DVD.

From the foregoing, it will be appreciated that example systems, methods, apparatus, and articles of manufacture have been disclosed that improve data training of a machine learning model using an FPGA. Examples disclosed herein include a plurality of computation modules associated with corresponding users. The plurality of computation modules is operative to collect various data formats tailored to users of the computation modules. One or more of the computation modules transmit neural network parameters to a FPGA to accelerate training the neural networks of the one or more computation modules. The FPGA can re-program itself based on the neural network parameters, execute a FPGA neural network based on the re-programming, and can generate updated parameters that can be used to improve operation of the neural networks of the one or more computation modules. The disclosed systems, methods, apparatus, and articles of manufacture improve the efficiency of using a computing device by off-loading data training tasks to a dedicated FPGA to re-allocated previously used computing resources to other tasks of the computing device. The disclosed methods, apparatus and articles of manufacture are accordingly directed to one or more improvement(s) in the functioning of a computer.

The following pertain to further examples disclosed herein.

Example 1 includes a system to improve data training of a neural network, the system comprising one or more computation modules, each of the one or more computation modules associated with a corresponding user, the one or more computation modules training first neural networks using data associated with the corresponding users, and a field-programmable gate array (FPGA) to obtain a first set of parameters from each of the one or more computation modules, the first set of parameters associated with the first neural networks, configure a second neural network based on the first set of parameters, execute the second neural network to generate a second set of parameters, and transmit the second set of parameters to the first neural networks to update the first neural networks.

Example 2 includes the system of example 1, wherein each of the one or more computation modules is a headset, a mobile device, or a wearable device.

Example 3 includes the system of example 1, wherein the data is audio data, visual data, or text data.

Example 4 includes the system of example 1, wherein at least one of the first set of parameters or the second set of parameters includes at least one of an artificial neuron weight, a bias value, a network topology, a quantity of activation layers, or a quantity of pooling layers.

Example 5 includes the system of example 1, wherein each of the one or more computation modules includes a collection engine to obtain the data, a database to store the data, and a network configurator to train the first neural networks using the second set of parameters.

Example 6 includes the system of example 1, wherein the FPGA includes a model optimizer to generate a first intermediate representation based on one of the first neural networks, an inference engine to adjust the intermediate representation, a high-graph compiler to generate a second intermediate representation, and an assembler to generate an output based on the second intermediate representation, the output to be executed at runtime.

Example 7 includes the system of example 6, wherein the output is a hardware configuration of the FPGA or machine readable instructions.

Example 8 includes a non-transitory computer readable storage medium comprising instructions which, when executed, cause a machine to at least train first neural networks using one or more computation modules, each of the one or more computation modules associated with a corresponding user, the one or more computation modules to train the first neural networks using data associated with the corresponding users, obtain, with a field-programmable gate array (FPGA), a first set of parameters from each of the one or more computation modules, the first set of parameters associated with the first neural networks, configure, with the FPGA, a second neural network based on the first set of parameters, execute, with the FPGA, the second neural network to generate a second set of parameters, and transmit, with the FPGA, the second set of parameters to the first neural networks to update the first neural networks.

Example 9 includes the non-transitory computer readable storage medium of example 8, wherein each of the one or more computation modules is a headset, a mobile device, or a wearable device.

Example 10 includes the non-transitory computer readable storage medium of example 8, wherein the data is audio data, visual data, or text data.

Example 11 includes the non-transitory computer readable storage medium of example 8, wherein at least one of the first set of parameters or the second set of parameters includes at least one of an artificial neuron weight, a bias value, a network topology, a quantity of activation layers, or a quantity of pooling layers.

Example 12 includes the non-transitory computer readable storage medium of example 8, wherein each of the one or more computation modules includes a collection engine to obtain the data, a database to store the data, and a network configurator to train the first neural networks using the second set of parameters.

Example 13 includes the non-transitory computer readable storage medium of example 8, wherein the FPGA includes a model optimizer to generate a first intermediate representation based on one of the first neural networks, an inference engine to adjust the intermediate representation, a high-graph compiler to generate a second intermediate representation, and an assembler to generate an output based on the second intermediate representation, the output to be executed at runtime.

Example 14 includes the non-transitory computer readable storage medium of example 13, wherein the output is a hardware configuration of the FPGA or machine readable instructions.

Example 15 includes a system to improve data training of a neural network, the system comprising means to train first neural networks, each of the means associated with a corresponding user, the means to train the first neural networks is to use data associated with the corresponding users, means to obtain a first set of parameters associated with the first neural networks, means to configure a second neural network based on the first set of parameters, means to execute the second neural network to generate a second set of parameters, and means to transmit the second set of parameters to the first neural networks to update the first neural networks.

Example 16 includes the system of example 15, wherein the means to train the first neural networks include a headset, a mobile device, or a wearable device.

Example 17 includes the system of example 15, wherein the data is audio data, visual data, or text data.

Example 18 includes the system of example 15, wherein at least one of the first set of parameters or the second set of parameters includes at least one of an artificial neuron weight, a bias value, a network topology, a quantity of activation layers, or a quantity of pooling layers.

Example 19 includes the system of example 15, wherein the means to train the first neural networks includes means to obtain the data, means to store the data, and means to train the first neural networks using the second set of parameters.

Example 20 includes the system of example 15, further including means to generate a first intermediate representation based on one of the first neural networks, means to adjust the intermediate representation, means to generate a second intermediate representation, and means to generate an output based on the second intermediate representation, the output to be executed at runtime.