Overlay error correction

A calibration curve for a wafer comprising a layer on a substrate is determined. The calibration curve represents a local parameter change as a function of a treatment parameter associated with a wafer exposure to a light. The local parameter of the wafer is measured. An overlay error is determined based on the local parameter of the wafer. A treatment map is computed based on the calibration curve to correct the overlay error for the wafer. The treatment map represents the treatment parameter as a function of a location on the wafer.

FIELD

Embodiments of the present invention pertain to the field of electronic device manufacturing, and in particular, to an overlay error correction.

BACKGROUND

Current electronic device manufacturing involves depositing layers of patterned materials on a substrate to fabricate transistors, contacts, and other devices. For proper operation of the device, these patterned layers for example contacts, lines and transistor features need to be aligned. Generally, an overlay control is defined as a control of the alignment of a patterned layer to one or more underlying patterned layers for a multilayer device structure. Typically, an overlay error represents a misalignment between the patterned layers.

The misalignment between the patterned layers can cause short circuits and connection failures that impact manufacturing yield and cost. Generally, as the device features decrease and pattern density increases, overlay error budgets shrink. Conventional multi-exposure and multi-patterning schemes require very tight overlay error budgets. In conventional lithographic systems, various alignment mechanisms are provided to align features in a given layer to the features in a underlying layer. For advanced nodes, however, optical or extreme ultraviolet (EUV) scanner improvements alone does not reduce the overlay error enough to meet the required specifications. A process related overlay error has become a significant part (about 50%) of the overall overlay budget. Typically, the overlay error reduces the device performance, yield and throughput significantly. Additionally, a stress related process induced overlay error significantly impacts high volume production (HVP) of logic and memory devices.

SUMMARY

Methods and apparatuses to provide light induced overlay error correction are described. In one embodiment, a calibration curve for a wafer comprising a layer on a substrate is determined. The calibration curve represents a local parameter change as a function of a treatment parameter associated with a wafer exposure to a light. The local parameter of the wafer is measured. An overlay error is determined based on the local parameter of the wafer. A treatment map is computed based on the calibration curve to correct the overlay error for the wafer. The treatment map represents the treatment parameter as a function of a location on the wafer.

In one embodiment, a non-transitory machine readable medium comprises instructions that cause a data processing system to perform operations comprising determining a calibration curve for a wafer comprising a layer on a substrate, wherein the calibration curve represents a local parameter change as a function of a treatment parameter associated with a wafer exposure to a light; measuring the local parameter of the wafer; determining an overlay error based on the local parameter; and computing a treatment map based on the calibration curve to correct the overlay error for the wafer, wherein the treatment map represents the treatment parameter as a function of a location on the wafer.

In one embodiment, a system to manufacture an electronic device, comprises a processing chamber. A processor is coupled to the processing chamber. A memory is coupled to the processor. The processor has a configuration to control determining a calibration curve for a wafer. The processor has a configuration to control measuring the local parameter of the wafer. The processor has a configuration to control determining an overlay error based on the local parameter. The processor has a configuration to control computing a treatment map based on the calibration curve to correct the overlay error for the wafer.

Other features of the embodiments of the present invention will be apparent from the accompanying drawings and from the detailed description which follows.

DETAILED DESCRIPTION

Methods and apparatuses to correct an overlay error using light are described. A calibration curve for a wafer is determined. The wafer comprises one or more layers on a substrate. The calibration curve represents a change of the local parameter of the wafer as a function of a treatment parameter associated with the wafer exposure to a light. The local parameter of the wafer is measured. An overlay error is determined based on the local parameter. A treatment map is computed based on the calibration curve. The treatment map is to correct the overlay error for the wafer. The treatment map represents the treatment parameter as a function of a location on the wafer.

In one embodiment, a laser induced stress change is used to decrease process related overlay errors. A process induced overlay error is correlated with a process related stress non-uniformity of a wafer. Typically, the process related stress non-uniformity of the wafer is defined as being generated at a wafer processing operation, e.g., a mechanical, chemical, thermal, etch, deposition, or other wafer processing operation.

In one embodiment, the wafer comprises a film or a multilayer stack. In one embodiment, the overlay error is reduced by reducing the process related non-uniformity of the wafer using a laser annealing technique. This technique relies on the knowledge of the wafer properties and the wafer response to the annealing conditions. The light delivered to the film or stack is precisely controlled using spatial, temporal and dose control tools.

Embodiments of the light induced overlay error correction described herein advantageously reduce a process related overlay error up to about 90%. In at least some embodiments, the light induced overlay error correction provides an advantage of relaxing specifications for lithography tools that result in production gain compared to conventional techniques that require exhaustive overlay measurements. In at least some embodiments, a global stress or bow of the wafer is reduced by a light that improves wafer handling and acceptance on different processing tools e.g., electrostatic chucks (ESC), lithography tools, or other processing tools. In at least some embodiments, reducing a global stress of the wafer, a local stress non-uniformity of the wafer, or both by a light improves structural integrity of etched patterns.

In at least some embodiments, different wavelengths of the light and different light processing conditions are advantageously used to correct overlay errors for different films, stacks or process flows. In at least some embodiments, the light induced overlay error correction technique is a highly flexible technique that provides different exposure setups to increase manufacturing throughput. In at least some embodiments, the light induced overlay error correction technique improves wafer-to-wafer, lot-to-lot and chamber-to-chamber matching in terms of overlay performance, as described in further detail below.

In the following description, numerous specific details, such as specific materials, chemistries, dimensions of the elements, etc. are set forth in order to provide thorough understanding of one or more of the embodiments of the present invention. It will be apparent, however, to one of ordinary skill in the art that the one or more embodiments of the present invention may be practiced without these specific details. In other instances, semiconductor fabrication processes, techniques, materials, equipment, etc., have not been described in great details to avoid unnecessarily obscuring of this description. Those of ordinary skill in the art, with the included description, will be able to implement appropriate functionality without undue experimentation.

While certain exemplary embodiments of the invention are described and shown in the accompanying drawings, it is to be understood that such embodiments are merely illustrative and not restrictive of the current invention, and that this invention is not restricted to the specific constructions and arrangements shown and described because modifications may occur to those ordinarily skilled in the art.

Moreover, inventive aspects lie in less than all the features of a single disclosed embodiment. Thus, the claims following the Detailed Description are hereby expressly incorporated into this Detailed Description, with each claim standing on its own as a separate embodiment of this invention. While the invention has been described in terms of several embodiments, those skilled in the art will recognize that the invention is not limited to the embodiments described, but can be practiced with modification and alteration within the spirit and scope of the appended claims. The description is thus to be regarded as illustrative rather than limiting.

FIG. 1is a flowchart of a method100to correct an overlay error according to one embodiment. At block101a calibration curve for an incoming wafer is determined. In one embodiment, the calibration curve for the wafer is determined based on one or more wafer characteristics, as described in further detail below. In one embodiment, the wafer comprises one or more layers on a substrate. The calibration curve represents a change of the local parameter of the wafer as a function of a treatment parameter associated with the wafer exposure to a light. In one embodiment, the local parameter comprises a local stress curvature. In one embodiment, the treatment parameter comprises a light power, a light fluence, a light pulse width, a light beam shape, a light beam size, a light wavelength, a light exposure repetition rate, a light exposure time, a light scan speed, a number of light flashes, a light zone temperature, an ambient condition, a light exposure mode, a light exposure sequence, a light exposure pattern, or any combination thereof, as described in further detail below.

FIG. 2is a view200illustrating an exposure of a wafer203to a light204according to one embodiment. As shown inFIG. 2, wafer203is placed on a wafer holder202on a movable pedestal201. In one embodiment, movable pedestal201comprises an electrostatic chuck (“ESC”), or other movable pedestal known to one of ordinary skill in the art of electronic device manufacturing. In alternative embodiments, pedestal202, light204, or both are moved along a plurality of axes, e.g., an X axis206and an Y axis207to expose local portions of the wafer203to light204. In one embodiment, wafer holder202is any wafer holder known to one of ordinary skill in the art of electronic device manufacturing.

In one embodiment, light204is supplied from a light source (not shown) to induce annealing at a predetermined location205on wafer203. In one embodiment, light204is a coherent light beam generated by a coherent light source, e.g., a laser. In another embodiment, light204is an incoherent light generated by a incoherent light source, e.g., one or more light bulbs, one or more light emitting diodes, or other incoherent light sources. In one embodiment, the wafer203comprises a mask layer on a front side of a substrate. In another embodiment, the wafer203comprises a backside layer on a back side of the substrate. In yet another embodiment, the wafer203comprises a mask layer deposited on the front side of the substrate and a backside layer deposited on the back side of the substrate, as described in further detail below with respect toFIG. 3. In one embodiment, the substrate of the wafer203comprises a multilayer stack including conducting, semiconducting, insulating, or any combination thereof layers deposited on top of one another.

In an embodiment, the substrate of the wafer203comprises a semiconductor material, e.g., silicon (Si). In one embodiment, the substrate is a monocrystalline Si substrate. In another embodiment, the substrate is a polycrystalline silicon substrate. In another embodiment, the substrate represents a previous interconnect layer. In yet another embodiment, the substrate is an amorphous silicon substrate. In alternative embodiments, the substrate includes silicon, germanium (“Ge”), silicon germanium (“SiGe”), a III-V materials based material e.g., gallium arsenide (“GaAs”), or any combination thereof. In one embodiment, the substrate includes metallization interconnect layers for integrated circuits. In an embodiment, the substrate is a semiconductor-on-isolator (SOI) substrate including a bulk lower substrate, a middle insulation layer, and a top monocrystalline layer. The top monocrystalline layer may comprise any material listed above, e.g., silicon. In various implementations, the substrate can be, e.g., an organic, a ceramic, a glass, or a semiconductor substrate. In one implementation, the semiconductor substrate may be a crystalline substrate formed using a bulk silicon or a silicon-on-insulator substructure. In other implementations, the semiconductor substrate may be formed using alternate materials, which may or may not be combined with silicon, that include but are not limited to germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, indium gallium arsenide, gallium antimonide, or other combinations of group III-V or group IV materials.

In at least some embodiments, the substrate comprises any material to make any of integrated circuits, passive (e.g., capacitors, inductors) and active (e.g., transistors, photo detectors, lasers, diodes) microelectronic devices. The substrate may include insulating (e.g., dielectric) materials that separate such active and passive microelectronic devices from a conducting layer or layers that are formed on top of them e.g., silicon dioxide, silicon nitride, sapphire, other dielectric materials, or any combination thereof. Although a few examples of materials from which the substrate may be formed are described here, any material that may serve as a foundation upon which passive and active electronic devices (e.g., transistors, memories, capacitors, inductors, resistors, switches, integrated circuits, amplifiers, optoelectronic devices, or any other electronic devices) may be built falls within the spirit and scope of the embodiments described herein.

In one embodiment, the mask layer of wafer203comprises a hard mask layer. In another embodiment, the mask layer of wafer203comprises a photoresist layer. In an embodiment, the mask layer of the wafer203is an organic hard mask layer comprising carbon. In an embodiment, the mask layer of the wafer203is an amorphous carbon layer (ACL), a nitride layer e.g., silicon nitride, silicon oxide nitride, or other nitride layer, an oxide layer e.g., a silicon oxide, a titanium oxide, or other oxide layer. In one embodiment, the ACL of the wafer203is doped with a chemical element (e.g., boron, silicon, aluminum, gallium, indium, or other chemical element). In one embodiment, the backside layer of the wafer203is an oxide, a nitride, a carbide, other backside film, or any combination thereof.

In one embodiment, the light204is supplied to a local portion on the mask layer of the wafer204. In another embodiment, the light204is supplied to a local portion of the backside film of the wafer204. In yet another embodiment, the light204is supplied to a local portion of the mask layer of the wafer203and to a local portion of the backside layer of the wafer203, as described in further detail below.

FIG. 3is a side view300of a wafer310according to one embodiment. As shown inFIG. 3, wafer310comprises a mask layer302on a top side of a substrate301. As shown inFIG. 3, a backside layer324is deposited on a bottom side of the substrate301. As shown inFIG. 3, substrate301comprises an interconnect layer307on a metallization (M) layer306on an interconnect layer305on a device layer304on a substrate303. In one embodiment, substrate303represents one of the substrates described above with respect toFIG. 2. In another embodiment, substrate301represents one of the substrates described above with respect toFIG. 2. In one embodiment, mask layer309represents one of the mask layers described with respect toFIG. 2. In one embodiment, backside layer324represents one of the backside layers described above with respect toFIG. 2.

As shown inFIG. 3, the device layer304includes one or more electronic devices features, e.g., a device feature312and a device feature315formed on an electrically insulating layer316. In alternative embodiments, the device features312and315represent features of transistors, memories, capacitors, resistors, optoelectronic devices, switches, or any other active and passive electronic devices features. As shown inFIG. 3, interconnect layer305comprises conductive interconnects311and317formed on an insulating layer321. Interconnect layer307comprises conductive interconnects314and319on an insulating layer322. In one embodiment, the conductive interconnects are conductive vias, or other interconnects. Metallization layer306comprises conductive lines313and318formed on an insulating layer323. Interconnect311connects device feature312to conductive line313.

Interconnect314connects conductive line313to an upper metallization layer (not shown). Each of the insulating layers316,321,322and323can be for example, an interlayer dielectric, a trench insulation layer, or any other electrically insulating layer known to one of ordinary skill in the art of the electronic device manufacturing. In alternative embodiments, device layer304includes polyimide, epoxy, photodefinable materials, such as benzocyclobutene (BCB), and WPR-series materials, or spin-on-glass. In an embodiment, the features of the device layer, metallization layer, and interconnect layers of the substrate301comprise a metal, for example, copper (Cu), aluminum (Al), indium (In), tin (Sn), lead (Pb), silver (Ag), antimony (Sb), bismuth (Bi), zinc (Zn), cadmium (Cd), gold (Au), ruthenium (Ru), nickel (Ni), cobalt (Co), chromium (Cr), iron (Fe), manganese (Mn), titanium (Ti), hafnium (Hf), tantalum (Ta), tungsten (W), vanadium (V), molybdenum (Mo), palladium (Pd), gold (Au), platinum (Pt), polysilicon, other electrically conductive material known to one of ordinary skill in the art of electronic device manufacturing, or any combination thereof.

In one embodiment, the thickness of the mask layer309is enough to substantially absorb and prevent the light326from being propagated into the substrate301. In one embodiment, light325represents light204, or a portion thereof. In one embodiment, a wavelength of the light325is selected to maximize absorption in the mask layer309to avoid propagation of the light326into substrate301. In an embodiment, the thickness of the mask layer is from about 2 nm to about 5 μm. Mask layer309can be deposited using one of a mask layer deposition techniques, such as but not limited to a spin coating, a sputtering, a chemical vapour deposition (“CVD”), e.g., a Plasma Enhanced Chemical Vapour Deposition (“PECVD”), a physical vapour deposition (“PVD”), molecular beam epitaxy (“MBE”), metalorganic chemical vapor deposition (“MOCVD”), atomic layer deposition (“ALD”), or other mask layer deposition techniques known to one of ordinary skill in the art of electronic device manufacturing.

In one embodiment, the thickness of the backside layer324is enough to substantially absorb and prevent the light326from being propagated into the substrate301. In one embodiment, a wavelength of the light326is selected to maximize absorption in the backside layer324to avoid propagation of the light326into substrate301. In one embodiment, light326represents light204, or a portion thereof. In an embodiment, the thickness of the backside layer324is from about 2 nm to about 5 μm. Backside layer324can be deposited using one of a backside layer deposition techniques, such as but not limited to a spin coating, a sputtering, a chemical vapour deposition (“CVD”), e.g., a Plasma Enhanced Chemical Vapour Deposition (“PECVD”), a physical vapour deposition (“PVD”), molecular beam epitaxy (“MBE”), metalorganic chemical vapor deposition (“MOCVD”), atomic layer deposition (“ALD”), or other mask layer deposition techniques known to one of ordinary skill in the art of electronic device manufacturing.

FIG. 4is a side view400illustrating variations of a local curvature of the wafer according to one embodiment. As shown inFIG. 4, a wafer401has a global curvature403that is substantially uniform along the wafer. A wafer411has a global curvature404that is substantially uniform along the wafer. In one embodiment, each of the wafers401and411represents one of the wafer203or wafer310. Global curvature403has a radius that is substantially constant along the wafer401. Global curvature404has a radius that is substantially constant along the wafer411. Typically, the global curvature is associated with a global stress of the wafer.

Wafer401has a local curvature402that varies along the wafer. Wafer411has a local curvature412that varies along the wafer. Generally, the variation of the curvature from one location to another location on the wafer is associated with a local variation of the stress of the wafer. Typically, non-uniform local stress of the wafer causes a process related non-correctable lithography overlay error and device yield loss. In one embodiment, an overlay error is associated with local variations of the stress curvature of the wafer. In one embodiment, the local variations of the stress curvature are reduced by light to correct the overlay error of the wafer, as described in further detail below.

FIG. 5is a flowchart of a method500to determine a calibration curve according to one embodiment. At a block501a response of the local stress parameter of one or more reference wafers to a plurality of treatment conditions is measured. In at least some embodiments, the plurality of treatment conditions are characterized by a plurality of treatment parameters associated with exposure of the wafer to the light. In one embodiment, the treatment parameter with exposure of the wafer to the light controls the local annealing temperature of the wafer.

In one embodiment, the treatment parameters comprise e.g., a dose, a power, a fluence, a pulse width, a beam shape, a beam size, a wavelength, an exposure repetition rate, an exposure time, a scan speed, a number of flashes, a zone temperature, an ambient condition, an exposure mode, an exposure sequence, an exposure pattern, or any combination thereof.

In one embodiment, the light incident to the wafer is a laser light having the beam size from about few microns to about few centimeters. In more specific embodiment, the laser beam size is about 25 microns. In one embodiment, the laser light wavelength is from near ultraviolet (UV) wavelength to infrared (IR) wavelength. In more specific embodiment, the wavelength of the light is about 532 nm. In one embodiment, the laser repetition rate is from about few hertz (Hz) to about 100s of KiloHertz (KHz). In one embodiment, the laser fluence range is from few microjoules per square centimeter (μJ/cm2) to about few joules per square centimeter (J/cm2). In one embodiment, an exposure time of the wafer to the light is from about few nanosecond (nS) to about few seconds.

In one embodiment, the light pulse width determines the exposure time. In one embodiment, the laser beam shape determines a gradient of the local annealing temperature on the wafer. In one embodiment, the laser beam shape is Gaussian, asymmetric Gaussian, trail-ending Gaussian, trail-leading Gaussian, square, triangular, saw-tooth, trail-ending triangular, trail-leading triangular, or any other laser beam shape. In alternative embodiments, an ambient condition at which the wafer is exposed to the light is an atmospheric (e.g., air), an inert gas, or a vacuum condition. In one embodiment, the wafer exposed to the light is heated at a temperature greater than a room temperature. In alternative embodiments, a wafer exposure mode is a full wafer single exposure mode (in a flash), a continuous (scan mode), or discontinuous (ON and OFF) mode. In one embodiment, single or multiple exposures on a wafer are used to correct the overlay error. In one embodiment, an exposure sequence pattern is used to precisely control exposure to the light to correct the overlay error.

In one embodiment, a single laser beam is expanded e.g., using optics to provide a full wafer single exposure to the light. In another embodiment, multiple laser beams having a combined beam diameter substantially equal to the wafer diameter with stitching is used to control an exposure of the wafer to the light (e.g., location dependent dose delivery). In another embodiment, for a single exposure a plurality of flash bulbs are used to provide a single exposure of the wafer to the light. In one embodiment, the treatment parameter, e.g., the fluence, power, exposure time or combination thereof of the light output by the flash bulbs are controlled to provide a location dependent light delivery. In one embodiment, the flash bulbs are halogen bulbs.

At block502one or more stress correction calibration curves are generated based on measuring of the responses of the one or more reference wafers. In one embodiment, the one or more calibration curves are stored in a memory. At block503a process window for at least one of the calibration curves is determined. In one embodiment, a dependence of the treatment towards the wafer characteristics, e.g., the film thickness, optical, thermal properties, deposition conditions, and other wafer characteristics is determined. In one embodiment, the treatment parameter is chosen based on the wafer characteristic. At block504a correlation between the response and the treatment parameters is established based on the process window. In one embodiment, a calibration curve is selected from the plurality of calibration curves stored in the memory based at least on the process window, as described in further detail below.

FIG. 6is a view600showing an exemplary calibration curve603according to one embodiment. Calibration curve603is a local stress parameter modulation sensitivity curve. In one embodiment, calibration curve603is a stress correction calibration curve. Calibration curve603shows a change (Δ) of a local stress parameter R1601as a function of a treatment parameter PT607associated with a wafer exposure to a light. In one non-limiting embodiment, the local stress parameter R1is a local wafer curvature (mm−1). In another embodiment, the local stress parameter R1is a parameter associated with an optical, thermal, chemical or mechanical property or any combination thereof. In one embodiment, the change (Δ) of the local stress parameter R1represents a difference between the local stress parameter of the treated wafer and the local stress parameter of the untreated wafer.

In one embodiment, the size of the process window is determined based on one or more wafer characteristics (e.g., film thickness, optical and thermal properties, deposition conditions and other wafer characteristics). In one embodiment, the calibration curve for an incoming wafer is selected from the plurality of calibration curves based on the process window. In one embodiment, the calibration curve having the largest process window is selected from the plurality of the calibration curves for the wafer. In one embodiment, a treatment condition is selected for the wafer based on the wafer quality and the size of the process window.

Referring back toFIG. 1, at block102the local stress parameter of the incoming wafer is measured. In one embodiment, the local stress parameter map is generated based on the measurement.FIG. 7is a view showing an initial local stress parameter map700of the incoming wafer according to one embodiment. As shown inFIG. 7, the local stress parameter of the wafer varies along an X axis701and an Y axis702. In one embodiment, the local stress parameter is a local stress curvature. Referring back toFIG. 1, at block103an overlay error is determined based on the local stress parameter of the wafer.

In one embodiment, the overlay error map is computed based on the local stress parameter map. In more specific embodiment, the overlay error map is computed based on the local stress curvature map. In one embodiment, the information obtained from the local curvature map, local stress map, or both is used to compute an overlay error map. In one embodiment, a mean plus 3 sigma (σ) overlay error (residual overlay) along each of X and Y axes is computed based on the initial local stress parameter map. In one non-limiting example, the residual overlay computed based on the initial local stress parameter map700along X axis is about 15 nm and along Y axis is about 13 nm. In one embodiment, the residual overlay is computed using linear scanner correction terms. In another embodiment, the residual overlay is computed using non-linear or higher order terms.

Referring back toFIG. 1, at block104a treatment map for the incoming wafer is computed based on the selected calibration curve to correct the overlay error for the incoming wafer.FIG. 8is a view showing a full wafer treatment map800according to one embodiment. The wafer treatment map represents a treatment parameter802as a function of a location on the wafer801. In one embodiment, the full wafer map for the treatment of the incoming wafer is determined using the calibration curve and the overlay error map. At block105the incoming wafer is processed using the treatment map. In one embodiment, the incoming wafer is treated using a location dependent exposure to the light to reduce variations of the local stress curvature of the wafer. In one embodiment, the treatment parameter to expose the first wafer to the light is controlled using the first treatment map.

FIG. 10is a view1000showing exemplary continuous light scanning modes1001to process an incoming wafer to correct the overlay error according to one embodiment. A continuous light scanning mode1003involves performing one or more sequential directional scans of a light beam1020along an X axis1007(X-scan) over the wafer. The light beam1020has a length1012and a width1013, as shown inFIG. 10. In one embodiment, the width1013determines a resolution of the scan. In one embodiment, the width1013is from about few microns to about few centimeters. In more specific embodiment, the width1013is about 125 microns. In one embodiment, the length1012is greater than the diameter of the wafer. In one embodiment, the length1012is from about few microns to about few centimeters.

A continuous light scanning mode1005involves performing one or more sequential directional raster scans of a light beam1023along an X direction1009(X-scan) over the wafer. As shown inFIG. 10, the width1015of the light beam1023determines a resolution of the scan. In one embodiment, the width1015is similar to the width1013. In one embodiment, the length1014of the light beam1023is smaller than the diameter of the wafer. In one embodiment, the length1014is from about few microns to about few centimeters. In one embodiment, each of the scanning modes1003and1005is used to change a local stress curvature component (Ry) of the wafer along an Y axis. In one embodiment, the Y axis is substantially perpendicular to the X axis.

A continuous light scanning mode1004involves performing sequential directional scans of a light beam1021along an Y direction1008(Y-scan) over the wafer. In one embodiment, a length1017and a width1016of the light beam1021are similar to that of light beam1020. A continuous light scanning mode1006involves performing sequential directional raster scans of a light beam1024along an Y direction1011(Y-scan) over the wafer. In one embodiment, a length1018and a width1019of the light beam1024are similar to that of light beam1023. In one embodiment, each of the scanning modes1004and1006are used to change a local stress curvature component of the wafer along an X direction (Rx).

In one embodiment, each of the light beams1020,1021,1023and1024represents a single laser beam, or other single light beam. In another embodiment, each of the light beams1020,1021,1023and1024represents a plurality of laser beams, or other light beams.

FIG. 11is a view1100showing exemplary continuous light scanning modes to process the incoming wafer to correct the overlay error according to another embodiment. A continuous light scanning mode1101involves performing sequential directional scans (e.g., 1, 3) of a light beam1111along an X axis1105(X-scans) and directional scans (e.g., 2, 4) of a light beam1112along an Y axis1105(Y-scan).

As shown inFIG. 11, mode1101involves a sequence of scans1104X (1),1105Y(2),1104X(3), and1105Y(4) of light beams1111and1112respectively. In one embodiment, the length and the width of the light beams1111and1112are similar to that of light beam1020. A continuous scanning mode1102involves performing sequential directional scans (e.g., 1, 3) of a light beam1121along an X axis in one direction1106and along the X axis in an opposite direction1107(X-scans) and directional scans (e.g., 2, 4) of a light beam1122along an Y axis in one direction1108and along the Y axis in an opposite direction1109(Y-scans). As shown inFIG. 11, mode1102involves a sequence X (1)-Y(2)-X(3)-Y(4) of scans1106,1108,1107, and1109of light beams1121and1122.

In one embodiment, the length and the width of the light beams1121and1122are similar to that of laser beam1023. In one embodiment, each of the light beams1111,1112,1121and1122represents a single laser beam, or other single light beam. In another embodiment, each of the light beams1111,1112,1121and1122represents a plurality of laser beams, or other light beams. In one embodiment, the treatment parameter PTof the light (e.g., a dose, power, fluence) is changed along the scanning of the light. In one embodiment, for each of the continuous scanning modes described above with respect toFIGS. 10 and 11, the treatment parameter PTof the light (e.g., a dose, power, fluence, or other treatment parameter) is changed along the scanning of the light based on the wafer treatment map.

FIG. 12is a view1200showing exemplary light scanning modes to process an incoming wafer to correct the overlay error according to another embodiment. As shown inFIG. 12, a scanning mode1201involves a single exposure of the wafer to a light beam having the light dose controlled as a function of a location on the wafer. The scanning mode1201is represented by curve1203that shows a fluence, or power PTdistribution of a laser beam1201as a function of a location x on the wafer. In one embodiment, the light beam1201represents a single laser beam, or other single light beam. In another embodiment, light beam1201represents a plurality of laser beams, or other light beams with stitching. The scanning mode1201can be used to correct overlay error over a region of the wafer from about few microns to about few centimeters.

A scanning mode1202involves using a superimposed grey scaling to deliver a location dependent dose of light to the wafer and improve throughput. For scanning mode1202, a scanning location and a scanning speed are controlled. Scanning mode1202is represented by a curve1204that shows a fluence, or power PTdistribution of the grey level output as a function of a location x on the wafer.

FIG. 13A is a view1300showing a wafer that is treated using a discontinuous (ON and OFF) exposure mode to correct an overlay error according to one embodiment. Generally, for the discontinuous (ON and OFF) exposure mode, a location dependent light dose delivery can be achieved using different beam sizes, a fluence of the light and a location on the wafer control with a stitching overlap e.g., to correct an overlay area of about few microns to few centimeters, and treating the wafer in the form of a grid divided into unit cells and sub-cells, or any combination thereof. In one embodiment, for the ON and OFF exposure an exposure pattern is used to control a wafer quality and correct an overlay error.

In one embodiment, the overlap between consecutive exposures is minimized to improve overlay error correction performance. In one embodiment, the overlap between consecutive exposures is minimized using a predetermined exposure sequence. In one embodiment, an exposure sequence determination is based on a light beam size, a unit cell and sub-cell design and throughput considerations. In one embodiment, single or multiple pulses of the light with a even temporal distribution, an un-even temporal distribution, or any combination thereof are delivered to a single sub-cell based on the wafer and overlay requirements.

As shown inFIG. 13, the wafer is associated with a grid1301that is divided to a plurality of unit cells, e.g., a unit cell1302and a unit cell1303. Each unit cell is divided into a plurality of sub-cells, such as a sub-cell1305. In one embodiment, each unit cell comprises a N×N sub-cells, where N is any number, excluding zero. In one embodiment, each unit cell comprises at least 3×3 sub-cells. In one embodiment, the size of the sub-cell is substantially similar to the size of the light beam.

FIG. 13Bis a view1310showing exemplary exposure sequences using the grid shown inFIG. 13Aaccording to one embodiment. Each of the unit cells1311,1312,1313,1314, and1315can represent unit cell1302. In one embodiment, to change both X and Y components of the local stress parameter and avoid a directional bias, the wafer is exposed to the light in the discontinued (ON and OFF) mode according to a predetermined pattern. This pattern is created to treat both X and Y components of the local stress curvature to avoid a directional bias of the local stress parameter of the wafer. In one embodiment, an overlap between consecutive exposures of the wafer is minimized.

As shown inFIG. 13B, a pattern represented at unit cell1311involves moving a light beam pulse from a sub-cell1317(1) to a sub-cell1318(2). This pattern is a valid pattern, as an overlap1316between the first (1) and next (2) exposures on the wafer is minimized to a dot. A pattern represented at unit cell1312involves moving a light beam pulse from one sub-cell (1) to a next sub-cell (2) horizontally. This pattern is a valid pattern, as a first (1) and a next (2) light beam exposures on the wafer are separated by a sub-cell1319, so that the consecutive exposures do not overlap.

A pattern represented at unit cell1313involves moving a light beam pulse from a sub-cell1to a sub-cell2diagonally. This pattern is a valid pattern, as the first (1) and next (2) light beam locations on the wafer are separated by a sub-cell1320, so that there is no overlap between the consecutive exposures. A pattern represented at unit cell1314involves moving a light beam pulse from a sub-cell1to a next sub-cell2. This pattern is a valid pattern, as the sub-cell1and sub-cell2of the unit cell1314are not adjacent sub-cells, so that the consecutive exposures do not overlap. A pattern represented at unit cell1315involves moving a light beam from a sub-cell1to an adjacent sub-cell2. This pattern is an invalid pattern, as there is a substantial overlap1312between the consecutive exposures.

Returning back toFIG. 13A, a pattern involving a sequence of light exposures 1, 2, 3, 4, 5, 6, 7, 8, and 9 is a valid pattern, as an overlap between consecutive exposures is minimized. In one embodiment, the unit cells1302and1303are exposed to light pulses at the same time. In another embodiment, the unit cells1302and1303are exposed to light pulses at different times. In one embodiment, the unit cells1302and1303are exposed to light using a similar sequence pattern. In another embodiment, the unit cells1302and1303are exposed to light pulses using different sequence patterns. In another embodiment, light exposure sequence of unit cells1302and1303are carried out alternatively such as light exposure 1 of unit cell1302followed by light exposure 1 of unit cell1303, followed by light exposure 2 of unit cell1302followed by light exposure 2 of unit cell1303and so on. After processing the wafer, the wafer quality can be re-assessed and if needed the wafer can be reprocessed for further improvement.

Referring back toFIG. 1, at block106the local stress parameter of the wafer is re-measured, as described above. At block107an overlay error map is determined based on the re-measured local stress parameter, as described above. At block108, a determination is made if the overlay error is greater than a predetermined threshold. If the overlay error is above the predetermined threshold, at block109a treatment map for the wafer is computed based on the overlay error map computed at block107. At block110the wafer is processed by controlling the treatment parameter using the treatment map computed at block109, and method100returns to block106. If the overlay error is not greater than the predetermined threshold method100ends at block111.

FIG. 9is a view900showing a local stress parameter map901of the wafer after the light treatment according to one embodiment. As shown inFIG. 9, the local stress parameter of the wafer is substantially the same along an X axis and an Y axis. In one embodiment, the local stress parameter map901is a local stress curvature map. In one embodiment, the overlay error map is computed based on the local stress parameter map901. In one embodiment, the information obtained from the local curvature map, local stress map, or both is used to compute the overlay error map. In one non-limiting example, the residual overlay computed based on the local stress parameter map901along X axis is about 1.44 nm and along Y axis is about 1.98 nm that is substantially less comparing to the initial overlay error of the wafer before light treatment. That is, embodiments of the treatment of the wafer using light as described herein demonstrate the overlay error correction of more than 80 percent.

FIG. 14is a view1400showing a local stress parameter map of the wafer before laser treatment1401and a local stress parameter map of the wafer after laser treatment1402according to one embodiment. In one embodiment, a residual overlay along each of X and Y axes is computed at a center portion1403, a middle portion1404and at an edge portion1401of the wafer based on the local stress parameter map1401. In one embodiment, the residual overlay is computed using linear scanner correction terms. In another embodiment, the residual overlay is computed using non-linear or higher order terms. In one non-limiting example, the residual overlay of the wafer before laser treatment along X axis at the center portion is about 5 nm, at the middle portion is about 9 nm and at the edge portion is about 6 nm. In one non-limiting example, the residual overlay of the wafer before laser treatment along Y axis at the center portion is about 9.5 nm, at the middle portion is about 5.5 nm and at the edge portion is about 2.5 nm.

In one embodiment, a residual overlay along each of X and Y axes is computed at a center portion1406, a middle portion1407and at an edge portion1408of the wafer based on the local stress parameter map1402. In one non-limiting example, the residual overlay of the wafer after laser treatment along X axis at the center portion is about 2 nm, at the middle portion is about 2.5 nm and at the edge portion is about 2 nm. In one non-limiting example, the residual overlay of the wafer after laser treatment along Y axis at the center portion is about 1.5 nm, at the middle portion is about 1.3 nm and at the edge portion is about 0.43 nm. That is, the overlay error of the wafer is minimized using the laser treatment at intra litho die resolution.

In one embodiment, the laser induced overlay error correction is performed on wafers that have been processed in different processing chambers. Typically, the wafers that have been processed in different processing chambers have different overlay error patterns (signatures). The laser induced overlay error correction substantially matches the chamber-to-chamber overlay error signatures. In one embodiment, the laser induced overlay error correction reduces the chamber-to-chamber difference in overlay error signatures to less than 30%.

FIG. 15shows a block diagram of an embodiment of a processing system1500to perform methods of light induced overlay error correction, as described above. As shown inFIG. 15, system1500has a processing chamber1501. A movable pedestal1502to hold a wafer1503is in processing chamber1501. Pedestal1502comprises an electrostatic chuck (“ESC”), a DC electrode1508embedded into the ESC, and a cooling/heating base. A DC power supply1504is connected to the DC electrode1508of the pedestal1502. A light1507is supplied to the wafer1503, as described above. Wafer1503is loaded through an opening1518and placed on pedestal1502. Wafer1503represents one of the wafers described above. The processing chamber1501may be any type of processing chamber known in the art, such as, but not limited to chambers manufactured by Applied Materials, Inc. located in Santa Clara, Calif. Other commercially available processing chamber systems may be used to perform the methods as described herein.

System1500comprises an inlet to input one or more process gases1516through a mass flow controller1509to chamber1501. As shown inFIG. 15, a pressure control system1523provides a pressure to processing chamber1501. As shown inFIG. 15, chamber1501has an exhaust outlet1510to evacuate volatile products produced during processing in the chamber.

A control system1511is coupled to the chamber1501. The control system1511comprises a processor1524, a local stress parameter measuring system1513, a light controller1514, a memory1512and input/output devices1515to provide a light induced error correction, as described herein. Memory1512is configured to store one or more calibration curves, local stress parameter maps, wafer treatment maps, overlay error maps, as described above. In one embodiment, the processor1524has a configuration to control determining a calibration curve for a wafer, as described above. The processor1524has a configuration to control measuring the local parameter of the first wafer, as described above. The processor1524has a configuration to control determining an overlay error based on the local parameter, as described above. The processor1524has a configuration to control computing a treatment map based on the calibration curve to correct the overlay error for the wafer, as described above. The processor1524has a configuration to control the treatment parameter using the treatment map to expose the first wafer to the light, as described above.

The processor1524has a configuration to control measuring a response of the local parameter of a reference wafer to a plurality of treatment conditions associated with a plurality of treatment parameters, as described above. The processor1524has a configuration to control generating a plurality of calibration curves based on measuring, as described above. The processor1524has a configuration to control determining a process window for each of the calibration curves, as described above.

Processor1524represents one or more general-purpose processing devices such as a microprocessor, central processing unit, or other processing device. Processor1102may also be one or more special-purpose processing devices such as an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), a digital signal processor (DSP), network processor, or the like. Processor1524is configured to control a processing logic for performing the operations, as described herein with respect toFIGS. 1-14.

The memory1512may include a machine-accessible storage medium (or more specifically a computer-readable storage medium) on which is stored one or more sets of instructions embodying any one or more of the methodologies or functions described herein. The instructions may also reside, completely or at least partially, within the processor1524during execution thereof by the control system1511, the processor1524also constituting machine-readable storage media. The instructions may further be transmitted or received over a network via a network interface device.