Semiconductor device and method for manufacturing the same

A semiconductor device comprises at least one gate structure disposed on a substrate; a first dielectric layer disposed on the substrate and contacting an outer sidewall of the at least one gate structure; a second dielectric layer having a L shape disposed on the first dielectric layer and contacting the outer sidewall of the at least one gate structure; an etch stop layer contacting the second dielectric layer, the first dielectric layer and the substrate, wherein the second dielectric layer has an upper portion and a lower portion contacting the upper portion, the upper portion extends along the outer sidewall, the lower portion extends from the outer sidewall to the etch stop layer; and an air gap between the second dielectric layer and the etch stop layer; wherein the first dielectric layer and the lower portion of the second dielectric layer have a same width.

TECHNICAL FIELD

The disclosure relates to a semiconductor device and a method for manufacturing the same. More particularly, the disclosure relates to a semiconductor device comprising an air gap and a method for manufacturing the same.

BACKGROUND

With a trend toward scaling down the size of the semiconductor device, FinFET (Field Effect Transistor) devices are more and more popular. During FinFET process, the air gap is usually used as a spacer material to improve the parasite capacitance. However, the method for manufacturing the air gap is too complicated. Therefore, there is a need for developing an improved method for manufacturing the air gap.

SUMMARY OF THE INVENTION

The invention is directed to a semiconductor device and a method for manufacturing the same.

According to one aspect of the present invention, a semiconductor device is provided. The semiconductor device comprises at least one gate structure disposed on a substrate; a first dielectric layer disposed on the substrate and contacting an outer sidewall of the at least one gate structure; a second dielectric layer having a L shape disposed on the first dielectric layer and contacting the outer sidewall of the at least one gate structure; an etch stop layer contacting the second dielectric layer, the first dielectric layer and the substrate, wherein the second dielectric layer has an upper portion and a lower portion contacting the upper portion, the upper portion extends along the outer sidewall, the lower portion extends from the outer sidewall to the etch stop layer; and an air gap between the second dielectric layer and the etch stop layer; wherein the first dielectric layer and the lower portion of the second dielectric layer have a same width.

According to one aspect of the present invention, a method for manufacturing a semiconductor device is provided. The method comprises the following steps. Firstly, at least one gate structure disposed on a substrate is formed. Next, a first dielectric layer disposed on the substrate and contacting an outer sidewall of the at least one gate structure is formed. Then, a second dielectric layer having a L shape disposed on the first dielectric layer and contacting the outer sidewall of the gate structure is formed. Afterwards, an etch stop layer contacting the second dielectric layer, the first dielectric layer and the substrate is formed. The second dielectric layer has an upper portion and a lower portion contacting the upper portion, the upper portion extends along the outer sidewall, the lower portion extends from the outer sidewall to the etch stop layer. Thereafter, an air gap between the second dielectric layer and the etch stop layer. The first dielectric layer and the lower portion of the second dielectric layer have a same width.

DETAILED DESCRIPTION OF THE INVENTION

The procedures and details of the manufacturing method and the structure of the embodiments are for exemplification only, not for limiting the scope of protection of the disclosure. Moreover, the identical or similar elements of the embodiments are designated with the same reference numerals. Also, it is also important to point out that the illustrations may not be necessarily be drawn to scale, and that there may be other embodiments of the present disclosure which are not specifically illustrated. Thus, the specification and the drawings are to be regard as an illustrative sense rather than a restrictive sense. It is to be noted that the drawings are simplified for clearly describing the embodiments, and the details of the structures of the embodiments are for exemplification only, not for limiting the scope of protection of the disclosure. Ones having ordinary skills in the art may modify or change the structures according to the embodiments of the present disclosure.

FIGS. 1-11are cross-sectional views showing a method for manufacturing a semiconductor device100according to an embodiment of the invention.

Referring toFIG. 1, a plurality of dummy gate structures120may be provided on the substrate102, and the dummy gate structures120are covered by a first dielectric layer112. The dummy gate structures120are separated from each others, and protrude from a top surface102aof the substrate102as a three-dimensional structure. Each of the dummy gate structure120comprises a polysilicon layer122, a first insulating layer124and a second insulating layer126. A gate dielectric layer104is disposed between the substrate102and the dummy gate structure120. The first dielectric layer112may directly contact the dummy gate structures120and the gate dielectric layer104. The substrate102may be a silicon substrate, a silicon-containing substrate, a silicon-on-insulator (SOI) substrate, or the like. The first dielectric layer112may comprise a low-k dielectric material, such as SiOCN or other suitable low-k dielectric materials. In one embodiment, the first dielectric layer112may have a thickness or a width W1in a range of 80 to 100 angstroms. The width W1may be measured in a first direction, e.g. the X-axis direction.

Referring toFIG. 2, a portion of the first dielectric layer112may be then removed by an etching process, and a bottom portion of the first dielectric layer112is remained after the etching process. The etching process may be a dry etching process. A top portion of the dummy gate structure120is exposed from the first dielectric layer112. A bottom portion of the dummy gate structure120is covered by the first dielectric layer112.

Referring toFIG. 3, a second dielectric layer114and a third dielectric layer116may be sequentially formed on the first dielectric layer112and the dummy gate structure120. In one embodiment, the second dielectric layer114may comprise a nitride material or an oxide material, such as silicon nitricarbide (SiCN), a low-k dielectric material or other suitable material. The third dielectric layer116may comprise an ultra low-k dielectric material or silicon nitride (SiN). The second dielectric layer114and the third dielectric layer116may be formed by a deposition process, such as a Chemical Vapor Deposition (CVD) process, an Atomic Layer Deposition (ALD) process or the like. The second dielectric layer114may have a hardness larger than that of the third dielectric layer116, and may have a hardness equal to or similar to that of the first dielectric layer112.

Referring toFIG. 4, portions of the first dielectric layer112, the second dielectric layer114and the third dielectric layer116are removed, and a plurality of recesses106rare formed in the substrates102. Each of the recesses106rextends from a top surface102aof the substrate102toward inside of the substrate102. Then, a plurality of epitaxial semiconductor layers106are formed inside the recesses106r, respectively. In one embodiment, portions of the first dielectric layer112, the second dielectric layer114, the third dielectric layer116are removed, and the recesses106rare formed by a dry etching process. The epitaxial semiconductor layers106may be formed by an epitaxial process on the substrate102.

Referring toFIG. 5, an etch stop layer118may be formed on and contact the first dielectric layer112, the second dielectric layer114, the third dielectric layer116, the substrate102and the epitaxial semiconductor layers106. In one embodiment, the etch stop layer118may be formed by a deposition process, such as a CVD process, an ALD process or the like, and may comprise SiCN.

Referring toFIG. 6, an interlayer dielectric layer132may be formed on the etch stop layer118. The interlayer dielectric layer132may be formed by a deposition process, such as a CVD process, an ALD process or the like.

Referring toFIG. 7, portions of the second dielectric layer114, the etch stop layer118, the dummy gate structure120, the interlayer dielectric layer132, and the third dielectric layer116may be removed, and the polysilicon layer122, the second dielectric layer114and the third dielectric layer116may be exposed. In one embodiment, the second insulating layer126and a portion of the second dielectric layer114and the third dielectric layer116surrounding and above the second insulating layer126are removed by a dry etching process. The first insulating layer124and a portion of the second dielectric layer114and the third dielectric layer116surrounding and above the first insulating layer124are removed by a planarization process, such as a chemical mechanical planarization (CMP) process.

Referring toFIG. 8, the polysilicon layer122may be removed to form a first opening120p, and then a bottom gate142is formed in the first opening120p. The bottom gate142may comprise interlayer dielectric materials, high-k dielectric material, work function materials, other suitable material, or a combination thereof. The high-k dielectric material may be HfO2, HfSiO4, HfSiON, Al2O3, La2O3, Ta2O5, Y2O3, ZrO2, SrTiO3, ZrSiO4, HfZrO4, SBT (SrBi2Ta2O9), PZT (PbZrxTi1-xO3), BST (BaxSr1-xTiO3), or the like. The work function materials may be TiN or the like (for p-type semiconductor device), or may be TiAl, TiAlN, or the like (for n-type semiconductor device).

Referring toFIG. 9, an upper portion of the bottom gate142may be removed to form a second opening142p, and then a cap structure144is formed in the second opening142p. In this manner, a gate structure140comprising the bottom gate142and the cap structure144is formed. In one embodiment, the cap structure144may comprise nitride, and may be formed by a deposition process. After forming the cap structure144in the second opening142p, a planarization process, such as a chemical mechanical planarization (CMP) process may be performed. In this manner, a plurality of gate structures140are formed to protrude from substrate102. The first dielectric layer112disposed on the substrate102may contact an outer sidewall140aof the gate structure140. The remained second dielectric layer114may have a L shape, may be disposed on the first dielectric layer112and contact the outer sidewall140aof the gate structure140. The second dielectric layer114have an upper portion114aand a lower portion114bcontacting the upper portion114a. The upper portion114aextends along the outer sidewall140aof the gate structure140. The lower portion114bextends from the outer sidewall140aof the gate structure140to the etch stop layer118. The first dielectric layer112and the lower portion of the second dielectric layer114may have a same width W1.

Referring toFIG. 10, the third dielectric layer116may be removed by an etching process, such as a dry etching process or a wet etching process, to form a gap116pbetween the second dielectric layer114and the etch stop layer118. In the etching process, an etchant may have a first etching rate and a second etching rate to the second dielectric layer114and the third dielectric layer116, respectively, and the second etching rate is larger than the first etching rate. In one embodiment, the second etching rate is 10 times larger than the first etching rate. That is, the etchant may have a high selectivity to etch the third dielectric layer116than the second dielectric layer114, and the second dielectric layer114having a L shape may be remained intact. In one embodiment, the etchant can be diluted HF, H3PO4or other suitable etchant that selectively etches the third dielectric layer116.

Since the outer sidewall140aof the gate structure140and a portion of structures on the substrate102(e.g. a portion of the gate dielectric layer104, a fin structure or other suitable structures) are covered by the second dielectric layer114and the first dielectric layer112, the gate structure140and a portion of the structure disposed on the substrate102can be protected from damaging during the etching process to form the gap116p. Further, since the first dielectric layer112and the bottom portion114bof the second dielectric layer114have a same width W1, the thickness of the first dielectric layer112is large enough to protect the gate structure140and a portion of the structure disposed on the substrate102(e.g. a portion of the gate dielectric layer104, a fin structure or other suitable structures) during the etching process.

Referring toFIG. 11, a top dielectric layer134may be formed on and contact the second dielectric layer114, the etch stop layer118, the interlayer dielectric layer132and the gate structure140, and the gap116psealed by the top dielectric layer134turns out to be an air gap116a. In other words, the air gap116ais disposed between the second dielectric layer114, the etch stop layer118and the top dielectric layer134. In one embodiment, the top dielectric layer134may be formed by a deposition process and comprise dielectric materials, such as tetraethoxysilane (TEOS). The etch stop layer118extends along the air gap116a, the second dielectric layer114, the first dielectric layer112to the top surface102aof the substrate102and covers the epitaxial semiconductor layer106. A sum of the upper portion114aof the second dielectric layer114and the air gap has a second width W2, and the first width W1may be similar or equal to the second width W2.

In this manner, the air gap116acan be simply formed by using an etching process with different etching rate to the second dielectric layer114and the second dielectric layer116. The process flow of the present invention can be more simplified than a comparative example without using a different etching rate to form an air gap. The semiconductor device100having the air gap116acan have an improved parasitic capacitance in comparison to a comparative example without using the air gap as a spacer material.

In the present invention, since the second dielectric layer114having a L shape is disposed on the first dielectric layer112and contacts he outer sidewall140aof the gate structure140, the gate structure140can be protected from damaging while manufacturing, such as the etching process to form the air gap116a. The first dielectric layer112disposed on the substrate102and contacting the outer sidewall140aof the gate structure140can also protect the gate structure140from damaging while manufacturing, such as the etching process to form the air gap116a. Further, since the first dielectric layer112and the bottom portion114bof the second dielectric layer114have a same width W1, the thickness of the first dielectric layer112is large enough to protect the gate structure140and a portion of the structure disposed on the substrate102(e.g. e.g. a portion of the gate dielectric layer104, a fin structure or other suitable structures) during the etching process. Therefore, the semiconductor device of the present invention can be formed in a more simple way in comparison to the conventional process for forming an air gap, and the structure of the semiconductor device can be well protected during manufacturing, so as to obtain the semiconductor device having an improved performance.