MOS-driver compatible JFET structure with enhanced gate source characteristics

A MOSFET driver compatible JFET device is disclosed. The JFET device can include a gate contact, a drain contact, and a source contact. The JFET device can further include a first gate region of semiconductor material adjacent the gate contact and a second region of semiconductor material adjacent the first gate region. The first gate region and the second gate region can form a first p-n junction between the first gate region and the second gate region. The JFET device can further include a channel region of semiconductor material adjacent the source contact. The channel region and the second gate region can form a second p-n junction between the second gate region and the channel region.

BACKGROUND

The present disclosure relates generally to junction field effect transistors (JFETs), and more particularly to gate region structures for JFETs.

A JFET is a field effect transistor device that provides the capability of modulating current through a channel region between the drain and the source of the JFET. The current through the channel region is controlled by adjusting the voltage applied to a p-n junction proximate the gate of the JFET. In normally off JFETs, or enhancement mode JFETs, the depletion width of the p-n junction typically extends all the way across the channel region of the JFET when about 0V is applied to the gate. Application of a positive voltage to the gate forward biases the p-n junction and reduces the width of the depletion region in the channel region. This creates a conduction path for current in the channel region between the source and drain of the JFET. In this regard, a normally off JFET can be used as a controllable switch for power electronics applications.

FIG. 1depicts a conventional normally off JFET device100. As illustrated, JFET device100includes a source terminal110, a drain terminal120, and a gate terminal130. Source terminal110is coupled to source contacts112. Drain terminal120is coupled to drain contact122. Gate terminal130is coupled to gate contacts132. A gate region140of semiconductor material is adjacent each gate contact132. A channel region150of semiconductor material is disposed between adjacent gate regions140and under source contact112. A drift region160of semiconductor material is disposed between, on one side, gate regions140and channel regions150, and, on the other side, drain contact122.

JFET device100illustrated inFIG. 1is an n-channel normally off JFET such that channel region150and drift region160are n-type semiconductor materials. Gate region140is of a p-type semiconductor material to form a p-n junction145between gate region140and channel region150. Another p-n junction146is formed between gate region140and drift region160. P-n junction145has a depletion region155with a depletion width that extends across channel region150when a 0V is applied to gate contact132. When the voltage applied to gate contact132reaches a threshold voltage, p-n junction145becomes forward-biased and the width of depletion region155is reduced. This creates a channel in channel region150for conduction of current between drain contact122and source contact112.

Conventional normally off JFETs, such as silicon carbide (SiC) JFETs, turn on at low threshold gate voltages, such as at about 1V, and are fully on at low gate voltages, such as at about 3V. These voltage levels are not compatible with conventional MOSFET gate drivers, which operate between about 0V (off-state) and about 15V (on-state). The threshold voltage of a conventional normally off SiC JFET of about 1V is so low that it is not safe to use a normally off SiC JFET with a MOSFET gate driver in power electronics applications, where noise could be higher than about 1V. Additionally, a 15V gate voltage would cause the p-n junction between gate and source to conduct a very large current, which can cause significant losses and defect propagation and subsequent device failure in the SiC material. In this regard, a specially designed gate driver is typically required for operation of SiC JFETs, which limits the application of JFETs in power electronics.

In a conventional normally off JFET, the gate source region forms a p-n junction which conducts a gate source current when the p-n junction is forward biased. The gate source current can be about 50 mA or even higher, which causes power losses in WET driver circuits. Moreover, the p-n junction in a conventional normally off JFET is almost fully forward biased when the JFET is turned on and the width of the depletion region of the p-n junction is very thin. The thin depletion region between the gate and channel can introduce a high gate source capacitance, which can limit dynamic performance of the JFET significantly.

Thus, there is a need for a normally off SiC JFET structure that is compatible with MOSFET drivers that overcomes the above-mentioned disadvantages.

SUMMARY

One embodiment of the present disclosure is directed to a JFET device that includes a gate contact, a drain contact, and a source contact. The JFET device includes a first gate region of semiconductor material adjacent the gate contact and a second region of semiconductor material adjacent the first gate region. The first gate region and the second gate region form a first p-n junction between the first gate region and the second gate region. The JFET device further includes a channel region of semiconductor material adjacent the source contact. The channel region and the second gate region form a second p-n junction between the second gate region and the channel region. The first p-n junction has a depletion width that is adjustable based at least in part on a gate voltage applied to the gate contact.

In a variation of this exemplary embodiment, the second p-n junction can have a depletion width that is adjustable based at least in part on the gate voltage. In another variation of this exemplary embodiment, the depletion width of the second p-n junction can decrease as the depletion width of the first p-n junction increases when the gate voltage is greater than a threshold voltage for the first p-n junction.

In another variation of this exemplary embodiment, the first gate region can be an n-type semiconductor material and the second gate region can be a p-type semiconductor material. In yet another variation of this exemplary embodiment, the second gate region can have a higher doping concentration than the channel region.

In a further variation of this exemplary embodiment, the second gate region can have a first side adjacent the channel region and a second side adjacent a drift region of semiconductor material. The drift region and the second gate region can form a third p-n junction between the drift region and the second gate region. In a variation of this exemplary embodiment, the first side of the second gate region can have a thickness that is less than a thickness of the second side of the second gate region. In another variation of this exemplary embodiment, the first side of the second gate region can have a thickness that is approximately equal to the sum of the depletion width of the first p-n junction and the depletion width of the second p-n junction when a 0V is applied to the gate contact and to the source contact.

In still a further variation of this exemplary embodiment, the first gate region, the second gate region, and the channel region can comprise a silicon carbide material.

Another exemplary embodiment of the present disclosure is directed to a JFET device that includes a gate contact, a drain contact, and a source contact. The JFET device includes a first gate region of semiconductor material adjacent the gate contact and a second region of semiconductor material adjacent the first gate region so that a first p-n junction is formed between the first gate region and the second gate region. The JFET device further includes a channel region of semiconductor material adjacent the source contact and the second gate region so as to form a second p-n junction between the second gate region and the channel region. The JFET device further includes a drift region of semiconductor material disposed adjacent the drain contact, the channel region, and the second gate region so as to form a third p-n junction between the second gate region and the drift region. In a variation of this exemplary embodiment, the second gate region can at least partially surround the first gate region.

Another exemplary embodiment of the present disclosure is directed to a normally off SiC JFET device. The normally off SiC JFET device includes a gate contact, a source contact, and a drain contact. The normally off SiC JFET device includes an n gate region of n-type semiconductor material adjacent the gate contact and a p gate region of p-type semiconductor material partially surrounding the n gate region. The p gate region and the n gate region form a first p-n junction between the p gate region and the n gate region. The normally off SiC JFET device further includes an n channel region of n-type semiconductor material adjacent the source contact and the p gate region. The n channel region and the p gate region form a second p-n junction between the n channel region and the p gate region. The normally off SiC JFET device further includes an n drift region of n-type semiconductor material adjacent the drain contact, the n channel region, and the p gate region. The n drift region and the p gate region form a third p-n junction between the n drift region and the p gate region.

In a variation of this exemplary embodiment, the SiC JFET device has a threshold voltage of about 6V. In another variation of this exemplary embodiment, the p gate region is substantially depleted when a gate voltage of about 6V is applied to the gate contact. In still another variation of this exemplary embodiment, the n channel region is substantially undepleted when a gate voltage of about 15V is applied to the gate contact.

Other variations and modifications can be made to these exemplary embodiments of the present disclosure.

DETAILED DESCRIPTION

In general, the present disclosure is directed to a normally off JFET structure that is compatible with MOSFET driver circuits. The normally off JFET structure includes a gate contact, a source contact, and a drain contact. The normally off JFET structure includes a first gate region of semiconductor material adjacent the gate contact and a second gate region of semiconductor material adjacent the first gate region so as to form a first p-n junction between the first gate region and the second gate region. A channel region is disposed adjacent the second gate region to form a second p-n junction between the second gate region and the channel region.

The JFET structure according to embodiments of the present disclosure can provide for a normally off JFET with a threshold voltage in the range of about 3V to about 6V, and a fully on voltage of about 15V and can block high drain voltage. The JFET structure provides for a reduced gate current when the JFET is fully on and can provide for reduced gate source capacitance and gate drain capacitance. Moreover, when the JFET is in a fully on condition, a larger channel region can be used for current conduction. In view of the above characteristics, the JFET structure according to embodiments of the present disclosure can provide for a normally off SiC JFET that is compatible with MOSFET driver circuits and can be used in power electronics applications.

The JFET structure according to embodiments of the present disclosure is applicable to any JFET device. While the present disclosure is made with reference to an n-channel normally off JFET device, those of ordinary skill in the art, using the disclosures provided herein, should readily understand that the present disclosure is equally applicable to other JFET devices, such as p-channel JFET devices, vertical JFET devices, planar JFET devices, Si JFET devices, SiC JFET devices, normally on JFET devices, and normally off JFET devices.

FIG. 2illustrates an exemplary JFET device200according to an exemplary embodiment of the present disclosure. As illustrated, JFET device200includes a source terminal210, a drain terminal220, and a gate terminal230. Source terminal210is coupled to source contacts212. Drain terminal220is coupled to drain contact222. Gate terminal230is coupled gate contacts232. An n gate region242of n-type semiconductor material is disposed adjacent the gate contacts232. A p gate region244of p-type semiconductor material is disposed adjacent the n gate region242and partially surrounds n gate region242. A first p-n junction243is formed between the n gate region242and the p gate region244.

An n channel region250of n-type semiconductor material is disposed between source contacts212and drain contact260. N channel region250is adjacent to p gate region244so that a second p-n junction245is formed between n channel region250and p gate region244. An n drift region260is adjacent to drain contact222, n channel region250, and p gate region244so as to form a third p-n junction246between the p gate region244and the n drift region260.

The doping concentration of p gate region233is much higher than the doping concentration of n channel region250, such that the depletion region of second p-n junction245is mostly in n channel region250. When a 0V is applied to gate contact232, the depletion width of the depletion region associated with second p-n junction245extends across n channel region250which prevents current from flowing through n channel region250from drain contact222to source contact212.

As illustrated inFIG. 2, p gate region244has first side adjacent n channel region250and a second side adjacent n drift region260. The thickness of the p gate region244at the second side adjacent n drift region260is much thicker than the thickness of the first side of p gate region244adjacent n channel region250. The thick p gate region244at the second side adjacent n drift region260is designed to support high drain voltage when the JFET is pinched off. When a high voltage is applied to drain contact222, the depletion region of third p-n junction246between p gate region244and n drift region260will shield n channel region250from a high electric field. Most high voltage applied on drain contact222can be supported by third p-n junction246between p gate region244and n drift region260. Therefore, p gate region244at the first side adjacent n channel region250is protected from high reverse-bias voltage between drain contact222and source contact212.

With reference now toFIG. 3, the JFET device200will now be discussed in more detail. When a 0V is applied to gate contact232and to source contact212, n channel region250is completely pinched off by the depletion width of the depletion region associated with second p-n junction245between p gate region244and n channel region250. The electric field along cut line310when a 0V is applied to gate contact232and source contact212is illustrated inFIG. 4. Curve400ofFIG. 4represents the electric field in n gate region242and a portion of p gate region244. Curve402shows the electric field in a portion of p gate region244and n channel region250.

As the voltage applied to gate contact232increases, the blocking voltage of first p-n junction243between n gate region242and p gate region244also increases. The depletion width of the depletion region associated with first p-n junction243will increase because first p-n junction243between n gate region242and p gate region244is blocking more and more voltage. At one point, p gate region244becomes totally depleted. The voltage applied to gate contact232at this moment is the threshold voltage of JFET device200. The electric field distribution at this moment along cut line310ofFIG. 3is illustrated inFIG. 5. Curve404ofFIG. 5illustrates the electric field in the n-gate region and the p-gate region. The area406between curve400and curve404represents the threshold voltage of JFET device200.

When the voltage applied to gate contact232is higher than the threshold voltage, the positive and negative electric fields in p gate region244compete with each other. As a result, the depletion width of the depletion region associated with first p-n junction243between n gate region242and p gate region244keeps increasing, which causes the depletion width of the depletion region in p gate region244associated with second p-n junction245between p gate region244and n channel region250to decrease. As the depletion width in p gate region244of the depletion region associated with second p-n junction245decreases, the depletion width in the n channel region250of the depletion region associated with second p-n junction245also decreases because the blocking voltage of the second p-n junction245decreases. As the depletion width of the depletion region in n channel region250reduces, n channel region250starts to open for current to flow from drain contact222to source contact212.

When the voltage between n gate region242and n channel region250is higher than the threshold voltage, p gate region244is totally depleted. No carriers exist in p gate region244. N gate region242and n channel region250become separated by a region of semiconductor material that is free of carriers. Electrons in n channel region250can go through the lowered potential barrier between p gate region244and n channel region250and are swept across the first p-n junction243by an electric field of opposite polarity between n gate region242and p gate region244. Gate current is thus much smaller in JFET device200when compared to conventional JFETs because only one carrier type, namely electrons in this exemplary embodiment, participates in gate source current, while both carrier types conduct gate source current in a conventional JFET structure.

Eventually, when gate voltage is about 15V, the n channel region250is mostly open. The electric field distribution at this moment along cut line310ofFIG. 3is illustrated inFIG. 6. Curve410ofFIG. 6represents the electric field in n gate region242and p gate region244. Curve414shows the electric field in n channel region250. Area412between curve410and curve400represents the fully open gate voltage. As illustrated, the electric field in n channel region has shifted from curve402to curve414. When the JFET is fully on, the first p-n junction243between n gate region242and p gate region244supports the most voltage applied on gate contact232. The depletion width of the depletion region associated with second p-n junction245between p gate region244and n channel region250is reduced so that a portion of n channel region250is available for current conduction.

A finite element simulation has been performed to determine the electric field distribution along cut line320ofFIG. 3in p gate region244and n channel region250as gate bias voltage increases from 0 volts to 15 volts.FIG. 7depicts the simulation results. Curve702depicts simulation results for when the gate voltage is less than the threshold voltage of JFET device200. When the gate voltage is smaller than the threshold voltage, p gate region244is not completely depleted and n channel region250is completely depleted so that JFET200is off. Curve704depicts simulation results for when the gate voltage is equal to the threshold voltage of JFET device200. When gate bias is around the threshold voltage, p gate region244is completely depleted. Curve706depicts simulation results for when the gate voltage is greater than the threshold voltage of JFET device. When the gate voltage is higher than the threshold voltage, a portion of n channel region250becomes undepleted, i.e. the n channel region250starts to open for conduction. When properly designed, n channel region250is fully open when the gate voltage is about 15V.

The transconductance waveform of JFET device200is illustrated inFIG. 8. Curve802depicts the transconductance waveform of a conventional JFET device. Curve804depicts the transconductance waveform of a JFET device according to an exemplary embodiment of the present disclosure. As illustrated, the conventional JFET device turns on at about 1 V, while the JFET device according to an exemplary embodiment of the present disclosure turns on at about 6 V.

One of the advantages of the JFET device according to exemplary embodiments of the present disclosure is that only one carrier type can penetrate both first p-n junction243and second p-n junction245. This reduces gate current significantly. This advantage is illustrated inFIG. 9. Curve904depicts characteristics of a conventional JFET device while curve902depicts characteristics of a JFET device according to an exemplary embodiment of the present disclosure. As illustrated, the gate-source current of the JFET structure according to embodiments of the present disclosure is only a tenth of the gate current of a traditional JFET structure when the n channel region250is open more than 50%.

N channel region250can open close to 100% if sufficiently high voltage is applied to gate contact232. Although a high current will go through gate region if the barrier presented by second p-n junction245between p gate region244and n channel region250disappears, the p-n junction245barrier can be reduced to a very small value while maintaining a relatively small gate current because only one carrier conducts current from gate contact232to source contact212.

Another advantage of JFET device200is that the gate source capacitance and gate drain capacitance can be reduced significantly because the depletion width between n gate region242and n channel region250and between n gate region242and n drift region260are increased significantly when compared to conventional JFET devices. Reduced gate source and gate drain capacitance improves dynamic performance of JFET device200significantly.