Integrated multi-chip module optical interconnect platform

Techniques, systems, and devices are disclosed to provide multilayer platforms for integrating semiconductor integrated circuit dies, optical waveguides and photonic devices to provide intra-die or inter-die optical connectivity. For example, an integrated semiconductor device having integrated circuits respectively formed on different semiconductor integrated circuit dies is provided to include a carrier substrate structured to form openings on a top side of the carrier substrate; semiconductor integrated circuit dies fixed to bottom surfaces of the openings of the carrier substrate, each semiconductor integrated circuit die including a semiconductor substrate and an integrated circuit formed on the semiconductor substrate to include one or more circuit components, and each semiconductor integrated circuit die being structured to have a top surface substantially coplanar with the top side of the carrier substrate; and planar layers formed on top of the top surfaces of the semiconductor integrated circuit dies and the top side of the carrier substrate to include optical waveguides and photonic devices to provide (1) intra-die optical connectivity for photonic devices associated with a semiconductor integrated circuit die, or (2) inter-die optical connectivity for photonic devices associated with different semiconductor integrated circuit dies.

BACKGROUND

This patent document relates to photonic devices and techniques.

Photonic components, interconnects, devices and modules can be used to use modulated light for carrying and transferring information with a broad bandwidth and at a high speed in data communications. It is desirable in various applications to integrate electronic circuits such as microprocessors and other integrated processing circuits together with photonic interconnects and devices to provide high performance information processing and broadband communications between different circuits or processors, including using high speed photonic interconnects (e.g., optical waveguides) to interconnect different circuits or processors. As a specific example, advances in silicon and silicon-compatible photonics have spurred intense research in the area of optical interconnects for increasing the bandwidth and lowering the power of computing systems such as multi- and many-core processors.

Various technical challenges exist in integrating electronic circuits, photonic or optical components together, including limited real estate on semiconductor substrates for integrating electronic components/devices and photonic components/devices, certain incompatibility between processing in fabrication of electronics and processing for fabrication of photonics and interconnect issues between electronics and photonic devices.

SUMMARY

Techniques, systems, and devices are disclosed to provide multilayer platforms for integrating semiconductor integrated circuit dies, optical waveguides and photonic devices to provide intra-die or inter-die optical connectivity.

In one aspect, an integrated semiconductor device having integrated circuits respectively formed on different semiconductor integrated circuit dies is provided to include a carrier substrate structured to form openings on a top side of the carrier substrate; semiconductor integrated circuit dies fixed to bottom surfaces of the openings of the carrier substrate, each semiconductor integrated circuit die including a semiconductor substrate and an integrated circuit formed on the semiconductor substrate to include one or more circuit components, and each semiconductor integrated circuit die being structured to have a top surface substantially coplanar with the top side of the carrier substrate; and planar layers formed on top of the top surfaces of the semiconductor integrated circuit dies and the top side of the carrier substrate to include optical waveguides and photonic devices to provide (1) intra-die optical connectivity for photonic devices associated with a semiconductor integrated circuit die, or (2) inter-die optical connectivity for photonic devices associated with different semiconductor integrated circuit dies.

In another aspect, a method for providing optical interconnects to various devices on an integrated platform is provided to include providing different integrated circuits on separated semiconductor integrated circuit dies; embedding the semiconductor integrated circuit dies in openings of a carrier substrate to fix each semiconductor die on a bottom surface of the carrier substrate in each opening to make a top surface of each semiconductor integrated circuit die substantially coplanar with a top side of the carrier substrate; and forming planar layers on top of the top surfaces of the semiconductor integrated circuit dies and the top side of the carrier substrate to include optical waveguides and photonic devices to provide inter-die optical connectivity for photonic devices associated with different semiconductor integrated circuit dies to enable direct optical communication from one die to another die without converting an optical signal into an electrical signal when communicating between two dies.

In another aspect, a method for fabricating an integrated platform that supports different devices and optical interconnects for the different devices is provided to include processing a carrier substrate to form openings on a top side of the carrier substrate; forming an adhesive layer in a bottom surface in each opening of the carrier substrate; and placing semiconductor integrated circuit dies over bottom surfaces of the openings of the carrier substrate so that each semiconductor integrated circuit die is fixed in position by the adhesive layer. Each semiconductor integrated circuit die includes a semiconductor substrate and an integrated circuit formed on the semiconductor substrate to include one or more circuit components, and each semiconductor integrated circuit die is structured to have a top surface substantially coplanar with the top side of the carrier substrate. This method further includes forming a sacrificial layer over the top surfaces of the semiconductor integrated circuit dies and the top side of the carrier substrate; processing the sacrificial layer to produce a flat top surface; forming planar layers over the flat top surface of the sacrificial layer to include optical waveguides and photonic devices in the planar layers to provide inter-die optical connectivity for photonic devices associated with different semiconductor integrated circuit dies; and forming electrical contacts to the semiconductor integrated circuit dies.

In another aspect, an integrated semiconductor device having integrated circuits respectively formed on different semiconductor integrated circuit dies is provided to include a carrier substrate structured to form openings on a top side of the carrier substrate; and semiconductor integrated circuit dies fixed to bottom surfaces of the openings of the carrier substrate. Each semiconductor integrated circuit die includes a semiconductor substrate, at least one integrated circuit formed on the semiconductor substrate, and one or more conductive contacts to provide electrical conductivity between the at least one integrated circuit and a circuit outside the semiconductor integrated circuit die. The device further includes a dielectric layer formed over the semiconductor integrated circuit dies and the top side of the carrier substrate and processed to provide a planar top surface; and planar optical layers formed on top of the planar top surface of the dielectric layer, the planar optical layers structured to include one or more optical waveguides and one or more photonic devices. One photonic device in the planar optical layers is electrically coupled to one of the semiconductor integrated circuit dies underneath the planar optical layers to either receive an electrical signal from, or send an electrical signal to, the coupled semiconductor integrated circuit die, and one optical waveguide in the planar optical layers is coupled to optically interconnect the one photonic device electrically coupled to the semiconductor integrated circuit die with another photonic device in the planar optical layers.

In another aspect, an integrated structure includes a carrier substrate; a plurality of semiconductor integrated circuit dies embedded within the carrier substrate, where each semiconductor integrated circuit die has a surface substantially coplanar with the carrier substrate; and at least one optical component layer located upon exposed portions of the carrier substrate and the plurality of semiconductor integrated circuit die. In implementations, the structure may include a silicon semiconductor substrate as the carrier substrate; the optical component layer may include a planarized optical interconnect layer.

In another aspect, a method is provided for fabricating an integrated structure and includes assembling within a plurality of trenches within a carrier substrate a plurality of semiconductor integrated circuit die so that a surface of each semiconductor integrated circuit die is substantially coplanar with a surface of the carrier substrate; and forming upon the exposed surfaces of the plurality of semiconductor integrated circuit die and the carrier at least one optical component layer. In implementations, this method may, in the assembling the plurality of integrated circuit die to the carrier substrate, use a flowable adhesive material.

In yet another aspect, an integrated semiconductor device is provided to include integrated circuits respectively formed on different semiconductor integrated circuit dies. This device includes a carrier substrate structured to form openings on a top side of the carrier substrate; semiconductor integrated circuit dies fixed to bottom surfaces of the openings of the carrier substrate, each semiconductor integrated circuit die including a semiconductor substrate, at least one integrated circuit formed on the semiconductor substrate, and one or more conductive contacts to provide electrical conductivity between the at least one integrated circuit and a circuit outside the semiconductor integrated circuit die; a dielectric layer formed over the semiconductor integrated circuit dies and the top side of the carrier substrate and processed to provide a planar top surface; and planar optical layers formed on top of the planar top surface of the dielectric layer, the planar optical layers structured to include one or more optical waveguides and one or more photonic devices. One of the one or more photonic devices in the planar optical layers is electrically coupled to one of the semiconductor integrated circuit dies underneath the planar optical layers to either receive an electrical signal from, or send an electrical signal to, the coupled semiconductor integrated circuit die. One of the one or more photonic devices in the planar optical layers includes a nonlinear optical device that is optically coupled one optical waveguide to receive a pump light and to produce one or more optical signals at optical wavelengths different from the pump light.

These and other aspects and their implementations are described in greater detail in the attached drawing, the description and the claims.

DETAILED DESCRIPTION

Specific examples of multilayer platforms are described below to integrate semiconductor integrated circuit dies, optical waveguides and photonic devices over a common substrate to provide intra-die or inter-die optical connectivity.FIG. 1Ashows an example of a multilayer platform that includes a substrate101, an integrated circuit (IC) layer102having IC dies110formed over the substrate101and optical layers120formed over the IC layer102. Each semiconductor integrated circuit die110is pre-fabricated with a desired processing, such as a fabrication process for IV semiconductors like the complementary metal-oxide-semiconductor (CMOS) processing for Si circuits or a fabrication processing for III-V semiconductors for various optoelectronic circuits. Each semiconductor integrated circuit die110in the IC layer102includes a semiconductor substrate and one or more integrated circuits formed on the semiconductor substrate or includes one or more circuit components. On top of the semiconductor integrated circuit dies110, planar layers120are formed to include optical waveguides and photonic devices. This multilayer platform places semiconductor integrated circuit dies110in an IC layer102that is separate from the planar layers120hosting the optical waveguides and photonic devices to enable freedom and flexibility in placing the optical waveguides for inter-die optical interconnects without being affected by the placement of the semiconductor integrated circuit dies110of the IC layer102. If needed, additional layers can be formed to add optical waveguides or photonic devices to further increase the freedom and flexibility in placing the optical waveguides and photonic devices relative to the underlying semiconductor integrated circuit die110. Similarly, more than one IC layers102may be implemented. An underlying semiconductor integrated circuit die110includes conductive contacts that are coupled to a photonic device with the planar layers120above the IC layer102to provide an electrical signal or control to the coupled photonic device which may be, e.g., a photodetector, an optical resonator or an optical modulator. Notably, the optical waveguides can be used to provide (1) intra-die optical connectivity for photonic devices associated with a semiconductor integrated circuit die110, or (2) inter-die optical connectivity for photonic devices associated with different semiconductor integrated circuit dies110.

The above multilayered configuration inFIG. 1Asignificantly reduces the obstacles in placing optical interconnects due by avoiding problematic optical waveguide crossings in the same layer and providing flexibility in arranging electric conductive paths or optical waveguides in a particular layer. Such a multilayered configuration can also reduce limitations due to real estate on a chip. Notably, the multiplayer configuration inFIG. 1Aenables multilayered photonics that opens up a new dimension to explore; facilitates denser as well as more complex networks with radically higher cross-sectional bandwidth and reduced communication power consumption. The above multilayer configuration can also be implemented to separate the process for fabricating the optical layers120from the process for fabricating the IC layer102. As such, the integration of photonic interconnects with on-chip electronics avoids a costly change to a well-established process used in fabricating either the IC layer102(e.g., the CMOS process) or the optical layers120.

In some implementations, the substrate101can be a carrier substrate structured to form openings on a top side of the carrier substrate101. The semiconductor integrated circuit dies110are fixed to bottom surfaces of the openings of the carrier substrate101. Each semiconductor integrated circuit die110includes its own semiconductor substrate, at least one integrated circuit formed on the semiconductor substrate, and one or more conductive contacts to provide electrical conductivity between the at least one integrated circuit and a circuit outside the semiconductor integrated circuit die110. A dielectric layer can be formed over the semiconductor integrated circuit dies110and the top side of the carrier substrate101and processed to provide a planar top surface. The planar optical layers120are then formed on top of the planar top surface of the dielectric layer and are structured to include one or more optical waveguides and one or more photonic devices. One photonic device in the planar optical layers120is electrically coupled to one of the semiconductor integrated circuit dies110underneath the planar optical layers120to either receive an electrical signal from, or send an electrical signal to, the coupled semiconductor integrated circuit die110, and one optical waveguide in the planar optical layers120is coupled to optically interconnect the one photonic device electrically coupled to the semiconductor integrated circuit die110with another photonic device in the planar optical layers120.

FIG. 1Bshows an example of a 3D photonic network platform based on the multilayer configuration inFIG. 1A. This platform is a multi-chip module (MCM) which includes a CMOS circuit layer on the bottom and several photonic layers above the CMOS circuit layer to provide crossed optical waveguides in different optical layers without physical crossing in the same layer. As illustrated, the platform includes an array of photonic devices in the middle while the CMOS circuit layer underneath provides CMOS circuits that are respectively coupled to the photonic devices. The optical waveguides are formed either in the same layer as the photonic devices or above the photonic devices to provide desired optical interconnects.

InFIG. 1B, the CMOS circuits can be implemented to provide desired circuit functions. For example, the CMOS circuits may include a central processing unit (CPU) on one of the semiconductor integrated circuit dies to enable communication to and from the CPU via one or more of the optical waveguides above the CMOS circuit layer. The CMOS circuits may include a memory device in communication with the CPU via one or more optical waveguides to provide high-bandwidth communications between the CPU and the memory device. As yet another example, the CMOS circuits may include a graphic processing unit (GPU) in communication with the CPU via one or more of the optical waveguides.

The multilayer configurations in the examples inFIGS. 1A and 1Benable planar processing of integrated optics between semiconductor dies. Planar processing takes direct advantage of various processing advancements in the semiconductor industry. As further described below, the multiplayer configuration can be implemented by embedding the dies in mechanically stable trenches of a common carrier substrate that match the dimension of the dies. The dies can be glued down the trenches to withstand mechanical vibrations and/or shocks. Under this implementation, the chips or dies are placed in a mechanically stable carrier substrate, it is more conducive to attaching heat sinks to manage heat, which can be critical for reliable operation of modern integrated circuits.

Due to the separation of layers for the IC circuits and the optical waveguides, a multilayer configuration based on the disclosed technology in this document allows flexible and versatile routing of optical interconnects between and through several nodes of the optical multi-chip module without being limited to optical routing just between one node to another. This flexible optical routing provides varying interconnects for various functionality that may be difficult to achieve in other integration architectures. Specifically, a module with more than two dies based on the present multilayer configuration can provide optical routing between and through all other dies for maximum flexibility and connectivity.

In the above multilayered configuration as illustrated inFIG. 1A or 1B, optical devices can be placed at various desired locations with respect to the underlying integrated circuits located on the dies, without requiring to place optical devices to be at certain locations, e.g., the edge of the semiconductor dies. This flexible placement capability is beneficial for multiple reasons. For example, this flexible placement capability frees up of the edge of the dies for wirebonds and/or solder bumps for electrical interconnection, which tends to be overcrowding. For another example, this flexible placement capability provides sufficient real estate for optical devices due to being in multiple optical layers and has flexibility for optical routing that is difficult to achieve by using the real estate in the IC layer for the underlying individual dies. In addition, this flexible placement capability allows for routing of global signal directly from the origin to the destination in the more efficient optical interconnect, instead of having to use inefficient long electrical interconnect, then conversion or switch to optical interconnect.

As a specific example for implementing the above multilayer configuration inFIG. 1A,FIGS. 2A-2Hshow a process for fabricating an integrated multi-chip module by using a Si carrier substrate and the structure of the multi-chip module. The illustrated method for fabricating the integrated multi-chip module that supports different devices and optical interconnects for the different devices includes processing a carrier substrate to form openings on a top side of the carrier substrate; forming an adhesive layer in a bottom surface in each opening of the carrier substrate; and placing semiconductor integrated circuit dies over bottom surfaces of the openings of the carrier substrate so that each semiconductor integrated circuit die is fixed in position by the adhesive layer. Each semiconductor integrated circuit die includes a semiconductor substrate and an integrated circuit formed on the semiconductor substrate to include one or more circuit components, and each semiconductor integrated circuit die is structured to have a top surface substantially coplanar with the top side of the carrier substrate. The illustrated method also includes forming a sacrificial layer over the top surfaces of the semiconductor integrated circuit dies and the top side of the carrier substrate; processing the sacrificial layer to produce a flat top surface; forming planar layers over the flat top surface of the sacrificial layer to include optical waveguides and photonic devices in the planar layers to provide inter-die optical connectivity for photonic devices associated with different semiconductor integrated circuit dies; and forming electrical contacts to the semiconductor integrated circuit dies.

As shown inFIGS. 2A and 2B, the fabrication process starts by preparing a carrier substrate201for hosting individual IC dies210by first forming openings or trenches202on a top side of the carrier substrate201. For example, contact photolithography can be used to define the openings or trenches202with precise dimensions for die placement within a few microns of tolerance. This moderate tolerance gives enough mechanical clearance for a die210to sit and orient with respect to other dies210. The depth204of the openings or trenches202can be controlled, e.g., by using Bosch etch (or wet etch) to achieve a desired to substantially match the thickness of dies210so that the carrier wafer top surface206is substantially coplanar with the top surface of the die210. An adhesive layer208is subsequently formed on the bottom surface in each trench202. This can be done by applying a small drop of flowable oxide in the trench202. Next, the dies210are placed in the trenches202and a light pressure is applied on the dies in the trenches202to allow adhesion of each die210to the carrier substrate201. The carrier substrate201is then baked at a suitable baking temperature (e.g., at400C for 1 hour) to bake out solvents and form oxide bonding of the dies210to the carrier substrate201. In this example, the subsequent deposition steps can be performed at400C. SeeFIGS. 2C and 2D.

In the illustrated example, each die210includes a substrate on which an IC layer212is formed (e.g., a transistor layer) and a chip dielectric layer214is formed over the IC layer212. Electrically conductive contacts216are formed in the die210to allow electrical contacts between the IC circuit on the die210and circuitry outside the die210. The conductive contacts216are used to provide electrical power to and or signaling/communication associated with the IC circuit on the die210as part of the IC layer102inFIG. 1A, including providing electrical connectivity with a photonic device in the optical layers120inFIG. 1A. Conductive contacts216can be conductive lines, pads or vias depending on the specifics of the die210. Due to presence of the conductive contracts216, the chip dielectric layer214tends to have bumps or protrusions214aover locations of the conductive contracts216.

Next, as shown inFIGS. 2E and 2F, a layer of a sacrificial material220is formed over the top surfaces of the semiconductor integrated circuit dies210and the top side206of the carrier substrate201. For example, several microns of PECVD Silicon Oxynitride can be used as the sacrificial layer220on the wafer, taking care not to induce excessive stress on the wafer. The top part of the sacrificial layer220can be processed, e.g., removed and polished, to produce a flat top surface for forming the optical layers. For example, a chemical mechanical polishing (CMP) process can be performed to polish the deposited surface of the layer220down to a desired thickness and roughness (e.g., below 3 nm RMS roughness). InFIG. 2G, a lower cladding layer230is deposited over the polished layer220, e.g., a layer of 3 um of PECVD Silicon Oxide as an optical under cladding. In addition, an optical waveguide layer232is formed over the lower cladding layer230. For example, a layer of 400 nm of low stress PECVD Silicon Nitride can be used as the optical waveguide layer232. The refractive index of the optical waveguide layer232is higher than that of the cladding layer230. Next inFIG. 2H, an aligned photolithography process is performed on an i-line stepper, followed by ICP-RIE etching of Silicon Nitride to etch out optical waveguides234. An interlayer dielectric layer (e.g., a dielectric oxide) is deposited over the exposed surfaces of the under cladding layer230and the waveguides234to bury the optical waveguides234so that the combined structure of the under cladding layer230and the later deposited interlayer dielectric layer together form the final optical cladding236in which the optical waveguides234are embedded. Subsequently, additional optical layers can be formed as needed to add photonic devices and/or optical waveguides. After the final optical layer, the whole structure over the wafer is cladded with 2 um of PECVD Silicon oxide, completing the process.

In the above multilayer design, multiple optical layers over the IC layer can be used to provide various optical or photonic devices/components, including either or both optically passive and optically active devices or components. Examples of optically passive devices or components include a passive optical delay line, a passive optical resonator, a passive optical bandpass filter, a passive optical grating, a passive optical add/drop filter, or other optical/photonic components that are fixed in their properties and cannot be tuned or controlled. Examples of optically active devices or components include optical/photonic devices that can be controlled by a control signal to change or modify a property of a signal such as an optical modulator including an electro-optical modulator, an optical-to-electrical conversion device such as a photodetector, an electrical-to-optical conversion device such as an optical amplifier, a light source/laser. The use of the carrier substrate201provides a common and stable platform for supporting the IC layer and optical layers. This construction is mechanically robust and based on planar processing for convenient fabrication.

FIG. 3shows an example of a multilayer structure formed by the above process inFIGS. 2A-2Hwhere an optical ring is formed in or coupled to some optical waveguides on top of the underlying CMOS circuit layer. Such an optical ring can be a passive ring or an active ring in form of an electro-optic modulator or switch.

FIG. 4illustrates an example of an active optical ring based on an electro-optic diode design. This active ring can be configured as a micrometer-scale electro-optic modulator by using a polysilicon ring resonator of a radius of 20 μm or 10 μm embedded in a 40 nm-tall p+n−n+diode structure and laterally coupled to a polysilicon waveguide. In a prototype sample device, the modulator can be operated at 2.5 Gbps and 10 dB extinction ratio. In addition, this device can be fabricated using the Excimer Laser Annealing (ELA) process to be operated at 3 Gbps. The polycrystalline silicon material exhibits properties that simultaneously enable high quality factor optical resonators and sub-nanosecond electrical carrier injection. An embedded p+n−n+diode can be used to achieve optical modulation using the free carrier plasma dispersion effect. Active optical devices in a deposited microelectronic material can break the dependence on the traditional single layer silicon-on-insulator platform and help lead to monolithic large-scale integration of photonic networks on a microprocessor chip.

FIG. 4includesFIG. 4a,FIG. 4bandFIG. 4c. More specifically,FIG. 4adepicts a top plan schematic view of an electro-optic modulator formed over a substrate formed of a deposited microelectronic material, such as polycrystalline silicon (i.e. polysilicon), for example. In other implementations, the substrate may be formed from at least one of another form of silicon, germanium, or a compound semiconductor such as gallium arsenide or indium phosphide, for example. Electro-optic modulator includes an optical ring resonator doped with n−, a p-type doped semiconducting region (p+) inside the ring resonator, and another n-type doped semiconducting region (n+) outside the ring resonator so that the n−-doped ring resonator is sandwiched between the inner semiconducting region (p+) and the outer semiconducting region (n+) to form the embedded p+n−n+diode structure. An optical waveguide is formed on the substrate close to the ring resonator to be optically coupled with the ring resonator by optical evanescent coupling to provide input light to the ring resonator and output light out of the ring resonator. An additional n-type doped semiconducting region (n+) is formed on the other side of the optical waveguide to so that the segment of the ring resonator closest to the optical waveguide is also in the p+n−n+diode structure. An electrical signal is applied to the p+n−n+diode structure to control the carrier injection and optical modulation using the free carrier dispersion effect. This electrical signal can be used to change or control the resonant wavelength of the optical ring resonator, thus changing or controlling the optical transmission of an optical signal output by the optical waveguide.

FIG. 4bshows a scanning electron microscope (SEM) image of the device inFIG. 4awhere a ring polysilicon resonator and 450 nm-wide bus waveguide are buried under 1 μm silicon dioxide.FIG. 4cfurther show a cross-section schematic of the device (not to scale) inFIG. 4a.

FIGS. 5A and 5Bshow an example of an optical wavelength division multiplexing (WDM) device using an optical ring in interaction with two optical waveguides at different optical layers in a multilayer configuration based onFIG. 1A. The optical coupling between two optical components in two different layers is based on evanescent optical coupling. This device effectuates a multi-layer optical link, traversing two layers and one passive WDM filter. The first layer (L1) on the lower side of the device is patterned with waveguides and rings with 30 μm radius. L1spans the full die ending in inverse-tapered couplers on both ends of the chip to provide an input and through port. L2, the second upper photonic layer begins above the microring resonator in the first layer L1and extends to the output facet, where light can be coupled out to read the drop port (seeFIG. 5B-a). Referring toFIG. 5B-b, the optical coupling between the L2waveguides and the ring resonator is set by the vertical and horizontal offsets provided by the mid-layer SiO2layer and lithographic positioning.FIGS. 5B-cand d show false-color SEM images of the cross section of the chip with emphasis on the L1waveguide. The optical WDM device inFIGS. 5A and 5Bcan be a passive WDM drop device where the device configuration is fixed to effectuate separating a selected WDM wavelength from the input into the optical ring resonator and routing the selected WDM wavelength into the drop waveguide L2while other WDM channels remain the waveguide L1. Alternatively, the optical WDM device inFIGS. 5A and 5Bcan be an active WDM drop device where the WDM wavelength that is coupled into the optical ring resonator can be controlled and adjusted by a control signal, e.g., a control signal applied to the optical ring resonator to alter the resonance condition of the optical ring resonator.

The above described multilayer configuration for integrating an IC layer with optical layers can be used to construct various photonic devices or modules. Some examples are provided below with respect toFIGS. 6, 7, 8 and 9.

FIG. 6shows an example of a CMOS backend deposited photonic device having a CMOS microelectronic layer and multiple layers having deposited photonic circuits on top of the CMOS backend. The CMOS microelectronic layer includes the Front End Of Line (FEOL) having the transistors and other active devices fabricated on the silicon substrate at the bottom, and the Back End Of Line (BEOL) having multiple layers of metal (as many as 10 or more in modern logic process) and interlayer dielectric for connecting the frontend devices together to form a circuit. The BEOL in other CMOS devices ends with the last metal layer that interfaces with the outside and the passivation layer on top to protect the BEOL. InFIG. 6, the BEOL is connected to multiple photonic layers.

In the upper deposited photonics layer in the example inFIG. 6, two layers of Silicon Nitride (SiN (waveguides are marked as lower optical waveguide and upper optical waveguide. One layer of a Excimer Laser Anneal (ELA) polysilicon is shown to form the active photonic device that is electrically coupled to a CMOS transistor circuit in the CMOS layer. In the illustrated examples inFIGS. 6-9, the active photonic device is shown to be an optical ring resonator configured to provide a desired function (e.g., a modulator or detector). In implementations, such an active photonic device can be implemented in various configurations in connection with the underlying CMOS transistor circuit. Each optical waveguide needs optical isolation, and this isolation is provided inFIG. 6by a layer of SiO2deposited using Plasma Enhanced Chemical Vapor Deposition (PECVD). Each SiN lower optical waveguide and the upper optical waveguide in multiple layers are oriented to be mutually orthogonal in order to minimize unwanted interlayer crosstalk and crossing losses. The optical ring resonator is evanescently coupled to a nearby lower optical waveguide and to the upper optical waveguide, thus effectuating as an optical via which may be configured to have a low crossing loss (e.g., −0.04 dB/cross) and a low interlayer coupling insertion (e.g., −0.6 dB). To modulate and detect optical data, separate active layers are placed in between any of the multiple SiN waveguide layers to efficiently couple to and from the bus waveguides.

FIG. 7shows an example of an optical detector formed in a CMOS backend deposited photonic device based on the architecture inFIG. 6. An optical ring is formed below the upper optical waveguide to receive, via evanescent coupling, optically coded data in the light guided by the upper optical waveguide. The optical ring is configured as an optical detector which is electrically coupled to a CMOS transistor circuit for receiving the electrical output of the optical detector. As such, the optically coded data in the guided light in the upper optical waveguide is detected by the optical ring detector and the detected electrical signal is routed via the metal via interconnecting the optical ring detector and the underlying CMOS transistor circuit for output at the Front End Of Line (FEOL) fabricated on the silicon substrate at the bottom.

FIG. 8shows an example of an optical modulator formed in a CMOS backend deposited photonic device based on the architecture inFIG. 6. An optical ring is formed below the upper optical waveguide to receive, via evanescent coupling, the input light guided by the upper optical waveguide. The optical ring resonator is configured as an optical modulator (e.g., the optical ring modulator inFIG. 4) which is electrically coupled to a CMOS transistor circuit in the Front End Of Line (FEOL) fabricated on the silicon substrate at the bottom for supplying an electrical modulation control signal that causes the modulation operation in the optical ring resonator. As such, the input light that is coupled into the optical ring resonator is optically modulated and the modulated light is then evanescently coupled back to the upper optical waveguide.

FIG. 9shows an example of a CMOS backend deposited photonic device based on the architecture inFIG. 6showing that two different active photonic devices1and2in two different multi-layered optical stacks are electrically coupled to two different CMOS transistor circuits1and2, respectively, that are formed in the Front End Of Line (FEOL) fabricated on the silicon substrate at the bottom. Based on the multi-layered design inFIG. 1A, the number of optical layers over the CMOS layer can be selected based on the needs of a particular application. In addition, more than one CMOS layer may be provided in some applications.

Backend deposited silicon photonics offers multiple benefits-independence from complex CMOS frontend processing, reduced constraint in photonic footprint, and multi-level architecture. In some CMOS processes, a process flow may involve many layers, e.g., more than 40 mask layers. In such a complex set of processes, every small tweak to a given processing step can lead to unintended compounding of side effects that can adversely affect yield or even render a process unstable. It does not help that the industry profit margin is thin, so it is almost natural for the CMOS foundries to be very risk adverse and unreceptive to bringing new processes or modules into their facility, including photonics.

The FEOL of a CMOS is the most sensitive part of the process, and thus foundries are rightfully opposed to making changes at the frontend to accommodate photonics. BDSP (Backend Deposited Silicon Photonics) decouples photonics from the most sensitive part of a CMOS process, and adds the whole photonics module after the very end of a CMOS process, so that foundries are not required to change their process. In fact, backend photonic processing can in principle be done in a different foundry from which the CMOS wafer was fabricated, since the photonics process is its own complete module that does not intrude upon, or depend on other processing steps of the underlying CMOS. This aspect greatly lowers the barrier of introducing silicon photonics into manufacturing.

The cost of adding the photonics module is kept low by use of i-line or 248 nm lithography used in non-critical backend layers. The SiN waveguide has a width of 1 um, and polysilicon active waveguide is 700 nm wide, well within capability of i-line lithography. Furthermore, the lateral alignment requirement across layers is expected to be around 100 nm depending on specific extinction ratio requirements, which is easily met even by i-line tool at 12 nm overlay. Photonic module will add approximately 7 mask layers per active layer and1layer per passive SiN waveguide, where much of active layer masks can be reused for patterning additional devices in different layers in some scenarios to reduce cost. Note that the masks become exponentially more expensive as the technology node becomes smaller, and by using backend process lithography, which is a generation or two behind the node of the process, total cost of the photonic module can be kept to a small fraction of the total mask cost process cost.

Deposited silicon photonics also greatly alleviates the constraints on footprint of photonic devices. The frontend silicon real estate is considered a highly valuable commodity, since every savings in area translates to more dies, hence revenue, per wafer. This is the reason why the microelectronics industry has pursued larger wafers and smaller transistors. If integrating photonics in the frontend means that total die area is going to increase significantly, one takes a hit not only because there are less dies per wafer, but also because yield of a die decreases nonlinearly as a function of the die area.

Therefore, if photonics is to be introduced in the frontend, its footprint is an important factor and a compact photonic device design is desirable with the footprint as small as possible. An optical ring resonator is one of the well-known compact photonic structures (along with photonic crystal cavities and others). However, the ring resonator in many designs remains to be relatively large, e.g., several microns in radius. This ring resonator footprint translates to hundreds of micron squared of footprint once optical isolation is considered. In addition, photonic transceiver circuitries in various implementations tend to be several hundreds of micron squared per channel, which adds significantly to the total area. Therefore, moving the photonic devices out of the frontend significantly decreases the total real estate needed for photonic interconnects, enhancing its area competitiveness. This competitive edge becomes even more apparent when we consider other common designs like Mach-Zehnder interferometer based modulators which can easily approach a millimeter in length in order to achieve sufficient extinction ratio at CMOS voltages. Therefore, by separating the photonics to dedicated layers, we greatly alleviate the issue of photonic footprint.

Similar to the multiple metal layers in CMOS backend, deposited silicon photonics naturally lends itself to multilayer optical routing, and in addition, deposited silicon photonics further enables multiple layers of active devices. A network-on-a-chip (NOC) that supports communication between cores in a massively multicore chip multiprocessor, for example, requires a closely knit network that can only be realized with many waveguide crossings. In-plane waveguide crossing is inherently lossy, and even relatively low loss (e.g., 0.7 dB/cross) can accumulate quickly and renders a network topology infeasible. However, in BDSP with multiple layers of low loss waveguides with very low crossing losses as discussed earlier, such network is perfectly feasible. Another benefit of having photonics on the backend is its easy access to end fire coupling from the periphery of the die. In a logic die where top side of the chip is completely covered in arrays of bumps for I/O, accommodating fibers vertically among arrays of bumps may be difficult. However, side of the die remains clear, and the plasma etched facet to define the smooth facet required for end fire coupling can be used to achieve efficient side coupling while being compatible with both flipchip packaging and mass manufacturing in just a single dielectric etch process followed by dicing. In addition, on-wafer testability can be maintained by use of grating couplers in SiN layers for optical testing before bump metallization.

Backend deposited silicon photonics has a multitude of benefits including reduced constraint in photonic footprint, multi-level optical routing, potential for unique device and system architecture that makes use of its 3D nature, and most importantly its independence from CMOS. The combination of mass production compatible multi-level Silicon active layers, modularity, and strict CMOS compatibility makes BDSP an appealing solution for both photonics designers and CMOS foundries. This opens up a different dimension to silicon photonic integration, potentially transforming what photonic integration on CMOS means and help more rapid adoption by the CMOS foundries in part due to its fundamentally non-intrusive nature to the CMOS process

The above multilayer platforms for integrating semiconductor integrated circuit dies, optical waveguides and photonic devices can be implemented to include various optical and photonic functionalities in the optical layers. Referring back toFIG. 1A, in some applications, certain photonic functions may be difficult to be integrated into the optical layers120. Such photonic functions may be added to the multilayer platforms inFIG. 1Aby bounding photonic chips on top of the optical layers120.

FIG. 10shows an example of adding certain photonic chips1010and1020on top of the optical layers120by chip bounding. For example, a photonic chip1010can be a laser such as a semiconductor quantum well laser that is bounded to provide laser light to the optical layers120. Various chip bounding techniques can be used to provide the desired mechanical connections, desired electrical connectivity and optical coupling.

The above inclusion of photonic functions based on the optical layers120in the multilayer platforms inFIG. 1Aand other implementations can be implemented by including one or more nonlinear optical devices. Such a nonlinear optical device can be fabricated in a compatible manner with the MCM. For example, Aluminum Nitride (AlN) and low optical loss materials such as Hydex by Little Optics and others can be used to form a nonlinear optical device in the MCM platforms disclosed in this document.

Low-loss optical materials, structures and methods disclosed in U.S. Pat. No. 6,614,977 entitled “Use of deuterated gases for the vapor deposition of thin films for low-loss optical devices and waveguides” can be used to implement the structures and devices disclosed in this document. The disclosure of U.S. Pat. No. 6,614,977 is incorporated by reference as part of this document. Among others, the '977 Patent discloses devices and methods for the vapor deposition of amorphous, silicon-containing thin films using vapors comprised of deuterated species. Thin films grown on a substrate wafer by this method contain deuterium but little to no hydrogen. Optical devices comprised of optical waveguides formed using this method have significantly reduced optical absorption or loss in the near-infrared optical spectrum commonly used for optical communications, compared to the loss in waveguides formed in thin films grown using conventional vapor deposition techniques with hydrogen containing precursors. In one variation, the optical devices are formed on a silicon-oxide layer that is formed on a substrate, such as a silicon substrate. The optical devices of some variations are of the chemical species SiOxNy:D. Since the method of formation requires no annealing, the thin films can be grown on electronic and optical devices or portions thereof without damaging those devices. In one embodiment, deuterated gases (gases and vapors are used interchangeably herein), such as SiD4and ND3(D being deuterium), serving as precursors, along with a gaseous source of oxygen, such as nitrous-oxide (N2O) or oxygen (O2), are used for the chemical vapor deposition of silicon-oxynitride (SiOxNy:D) or other non-polymeric thin films on a cladding. The cladding is composed, for example, of silicon oxide (SiO2), phosphosilicate glass, fluorinated silicon oxide, or SiOxNy:D having an index of refraction less than that of the thin film. In implementations, the cladding is formed on a substrate, such as silicon, quartz, glass, or other material containing germanium, fused silica, quartz, glass, sapphire, SiC, GaAs, InP, or silicon. In embodiments of the present invention, the thin film and the cladding formed on the substrate can vary in thickness and width, depending, for example, on the device being formed. In embodiments of the present invention, the cladding is formed with a thickness varying from 2 to 20 microns, and the thin film is formed with a thickness varying from about 0.5 to 5 microns. Other thicknesses of the cladding and the thin film are also usable in accordance with the present invention. For example, ridge structures can be formed from the thin deuterium containing films such as SiOxNy, Si3N4, or SiO2, by an etching process, such as reactive ion etching (RIE), to form an optical waveguide, one basic building block of integrated optical device.

FIG. 11shows an example of a photonic device having a nonlinear optical device and a CMOS backend in a MCM platform. In this example, the non-linear optical device is located below one or more optical waveguides and is optically coupled to at least one optical waveguide. For example, an input laser signal in the optically coupled optical waveguide is coupled into the non-linear optical device to optically coupled the non-linear optical device to cause a non-linear optical effect to occur, e.g., a nonlinear harmonic generation, four wave mixing or optical parametric oscillation. The light in the non-linear optical device is coupled out of the non-linear optical device into one optical waveguide above to produce an optical output from the non-linear optical device.

A particular kind of nonlinear optical devices is an Optical Parametric Oscillator (OPO) which can be used to generate multiple new wavelengths from a single laser source. This OPO operation in a MCM platform is attractive for implementing a wavelength division multiplexing (WDM) system. The OPO operation can be generated by using materials like AlN and Hydex. Specifically, the example inFIG. 11can be used in a network-on-a-chip system by optical wavelength-division-multiplexing (WDM) to increase the total available bandwidth of such a system. WDM typically requires separate laser sources for each of the desired WDM wavelengths, increasing the total cost of the system and making integration and assembly difficult. To overcome this issue, a nonlinear optical device, such as an Optical Parametric Oscillator (OPO), can be used to generate multiple wavelengths of laser from a single laser source, which mitigates the aforementioned issues. An OPO can be fabricated in high temperature annealed Silicon Nitride (SiN), but the high temperature annealing step used in fabricating OPO in SiN makes SiN incompatible with integration on a MCM because the annealing step will destroy the electronics underneath. Advantageously, OPO devices can be fabricated by using optical materials that do not require high temperature annealing process incompatible with MCM. Examples of such compatible materials include sputtered Aluminum Nitride (AlN) or Hydex™, and OPO has been fabricated and successfully demonstrated in the respective materials.