Integrated circuits with FinFET gate structures

Examples of an integrated circuit with FinFET devices and a method for forming the integrated circuit are provided herein. In some examples, an integrated circuit device includes a substrate, a fin extending from the substrate, a gate disposed on a first side of the fin, and a gate spacer disposed alongside the gate. The gate spacer has a first portion extending along the gate that has a first width and a second portion extending above the first gate that has a second width that is greater than the first width. In some such examples, the second portion of the gate spacer includes a gate spacer layer disposed on the gate.

BACKGROUND

The semiconductor integrated circuit (IC) industry has experienced rapid growth. In the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component (or line) that can be created using a fabrication process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and lowering associated costs. However, such scaling down has also been accompanied by increased complexity in design and manufacturing of devices incorporating these ICs. Parallel advances in manufacturing have allowed increasingly complex designs to be fabricated with precision and reliability.

For example, advances in fabrication have enabled three-dimensional designs, such as Fin-like Field Effect Transistors (FinFETs). A FinFET may be envisioned as a typical planar device extruded out of a substrate and into the gate. An exemplary FinFET is fabricated with a thin “fin” (or fin structure) extending up from a substrate. The channel region of the FET is formed in this vertical fin, and a gate is provided over (e.g., wrapping around) the channel region of the fin. Wrapping the gate around the fin increases the contact area between the channel region and the gate and allows the gate to control the channel from multiple sides. This can be leveraged in a number of way, and in some applications, FinFETs provide reduced short channel effects, reduced leakage, and higher current flow. In other words, they may be faster, smaller, and more efficient than planar devices.

As device sizes shrink, the features of the integrated circuit, such as the gates and contacts that couple to the gates, may become increasingly difficult to form and align. Advances that improve techniques for forming minute features or that provide additional space for forming larger features have the potential to increase yield, improve performance, reduce variability, reduce circuit area, and provide other benefits.

DETAILED DESCRIPTION

The following disclosure provides many different embodiments, or examples, for implementing different features of the disclosure. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. Moreover, the formation of a feature connected to and/or coupled to another feature in the present disclosure that follows may include embodiments in which the features are formed in direct contact, and may also include embodiments in which additional features may be formed interposing the features, such that the features may not be in direct contact.

In addition, spatially relative terms, for example, “lower,” “upper,” “horizontal,” “vertical,” “above,” “over,” “below,” “beneath,” “up,” “down,” “top,” “bottom,” etc. as well as derivatives thereof (e.g., “horizontally,” “downwardly,” “upwardly,” etc.) are used for ease of the present disclosure of one features relationship to another feature. The spatially relative terms are intended to cover different orientations of the device including the features. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations beyond the extent noted.

Integrated circuits include an ever-increasing number of active and passive circuit devices formed on a substrate or wafer, of which Fin-like Field Effect Transistors (FinFETs) are an example. FinFETs may include a number of raised semiconductor portions (e.g., fins) containing source/drain features and channel regions with gate structures wrapping around the channel regions. Some examples of the present technique improve the formation of contacts that couple to the source/drain features and to the gate structures by reducing the thickness of dielectric gate spacers that are disposed alongside the gates. The thinner gate spacers may allow more space for contacts, making the contacts easier to fabricate and align. Furthermore, in some such examples, the portions of the gate spacers alongside the gates are thinner than the portions of the gate spacers above the gates where a contact may be formed. The thinner portions of the gate spacer may provide a relatively wider recess in which to form a gate, which may make the gate easier to fabricate and align. Wider gate structures may also reduce adverse short channel effects. The thicker portions of the gate spacer elsewhere provide isolation between contacts, may reduce time-dependent gate oxide breakdown, and provide other benefits.

The present technique may avoid forming the gate structure in those regions where the gate spacer is thicker by omitting the gate structure entirely above the fins while retaining it alongside the fins. Instead, a conductive cap is formed on a fin that electrically couples the gate structures on either side of the fin. This may reduce the amount of conductive material in the gate structure. In addition to simplifying the gate, this may reduce gate capacitance and increase device switching speed. These advantages are merely examples and no particular advantage is required for any particular embodiment.

The present disclosure provides examples of an integrated circuit including a plurality of FinFETs and the associated gate structures. In that regard,FIGS. 1A and 1Bare flow diagrams of a method100of fabricating a workpiece200with FinFET gate structures according to various aspects of the present disclosure. Additional steps can be provided before, during, and after the method100, and some of the steps described can be replaced or eliminated for other embodiments of the method100.FIG. 2is a perspective illustration of the workpiece200undergoing the method100of fabrication according to various aspects of the present disclosure.FIGS. 3-11, 13, 15, 17, 19, 21, 23, 25, 27, and 29are cross-sectional illustrations of the workpiece200taken in a fin-length direction that cut through a fin, as indicated by plane202, according to various aspects of the present disclosure.FIGS. 12, 14, 16, 18, 20, 22, 24, 26, 28, and30are cross-sectional illustrations of the workpiece200taken in the fin-length direction that cut through an isolation feature, as indicated by plane204, according to various aspects of the present disclosure.FIG. 31is a cross-sectional illustration of the workpiece200taken in a gate-length direction that cuts through a gate structure, as indicated by plane206, according to various aspects of the present disclosure.

The substrate208may be uniform in composition or may include various layers, some of which may be selectively etched to form the fins. The layers may have similar or different compositions, and in various embodiments, some substrate layers have non-uniform compositions to induce device strain and thereby tune device performance. Examples of layered substrates include silicon-on-insulator (SOI) substrates208. In some such examples, a layer of the substrate208may include an insulator such as a semiconductor oxide, a semiconductor nitride, a semiconductor oxynitride, a semiconductor carbide, and/or other suitable insulator materials.

Doped regions, such as wells, may be formed on the substrate208. In that regard, some portions of the substrate208may be doped with p-type dopants, such as boron, BF2, or indium while other portions of the substrate208may be doped with n-type dopants, such as phosphorus or arsenic; and/or other suitable dopants including combinations thereof.

In some examples, the devices to be formed on the substrate208extend out of the substrate208. For example, FinFETs and/or other non-planar devices may be formed on device fins210disposed on the substrate208. The device fins210are representative of any raised feature and include FinFET device fins210as well as fins210for forming other raised active and passive devices upon the substrate208. The fins210may be similar in composition to the substrate208or may be different therefrom. For example, in some embodiments, the substrate208may include primarily silicon, while the fins210include one or more layers that are primarily germanium or a SiGe semiconductor. In some embodiments, the substrate208includes a SiGe semiconductor, and the fins210include a SiGe semiconductor with a different ratio of silicon to germanium than the substrate208.

The fins210may be formed by etching portions of the substrate208, by depositing various layers on the substrate208and etching the layers, and/or by other suitable techniques. For example, the fins210may be patterned using one or more photolithography processes, including double-patterning or multi-patterning processes. Generally, double-patterning or multi-patterning processes combine photolithography and self-aligned processes, allowing patterns to be created that have, for example, pitches smaller than what is otherwise obtainable using a single, direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over the fins210and one or more fin-top hard masks212. The sacrificial layer is patterned using a photolithography process. Spacers are formed alongside the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed, and the remaining spacers are used to pattern the fins210by removing material of the fin-top hard mask212and the substrate208that is not covered by the spacers so that the fins210remain.

The fin-top hard mask212may be used to control the etching process that defines the fins210and may protect the fins210during subsequent processing. Accordingly, the fin-top hard mask212may be selected to have different etch selectivity from the material(s) of the fins210. The fin-top hard mask212may include a dielectric material such as a semiconductor oxide, a semiconductor nitride, a semiconductor oxynitride, a semiconductor carbide, a semiconductor carbonitride, a semiconductor oxycarbonitride, and/or a metal oxide. In some examples, the fin-top hard mask212includes silicon oxide or silicon nitride. The fin-top hard mask212may be formed to any suitable thickness and, in various examples, has a thickness between about 1 nm and about 10 nm.

The workpiece200may also include an isolation dielectric layer216disposed on the substrate208between the fins210to form isolation features (e.g., Shallow Trench Isolation features (STIs)). The isolation dielectric layer216may include a dielectric material such as a semiconductor oxide, a semiconductor nitride, a semiconductor oxynitride, a semiconductor carbide, a semiconductor carbonitride, a semiconductor oxycarbonitride, a metal oxide, etc., and in some examples, the isolation dielectric layer216includes multiple sublayers of different dielectric materials. The isolation dielectric layer216may be formed by any suitable process, and in some examples, the isolation dielectric layer216is deposited using Atomic Layer Deposition (ALD), Plasma Enhanced ALD (PEALD), Chemical Vapor Deposition (CVD), Plasma Enhanced CVD (PECVD), High-Density Plasma CVD (HDP-CVD), and/or other suitable deposition processes. Following deposition, the isolation dielectric layer216may be etched back so that the uppermost portions of the fins210protrude above the isolation dielectric layer. In various such examples, the fins210and fin-top hard mask212extend between about 100 nm and about 500 nm above the topmost surface of the isolation dielectric layer216.

An I/O oxide layer214may be disposed on top of the fin-top hard mask212and on the sides of the fins210. The I/O oxide layer214may include a dielectric material such as a semiconductor oxide, a semiconductor oxynitride, a semiconductor oxycarbonitride, and/or a metal oxide. The I/O oxide layer214may be formed by any suitable deposition process including ALD, PEALD, CVD, PECVD, HDP-CVD, thermal growth, and/or other suitable techniques. In various examples, the I/O oxide layer214is deposited to a thickness between about 1 nm and about 5 nm.

The workpiece may also include placeholder gates218formed over and surrounding the channel regions of the fins210. When materials of the functional gate structures are sensitive to fabrication processes or are difficult to pattern, placeholder gates218of polysilicon, dielectric, and/or other resilient material may be used during some of the fabrication processes. The placeholder gates are later removed and replaced with elements of functional gates (e.g., a gate electrode, a gate dielectric layer, an interfacial layer, etc.) in a gate-last process. In this way, the placeholder gates218reserve area for the forthcoming functional gates.

The placeholder gates218may include any suitable material, such as polysilicon, one or more dielectric materials (e.g., a semiconductor oxide, a semiconductor nitride, a semiconductor oxynitride, a semiconductor carbide, a semiconductor carbonitride, a semiconductor oxycarbonitride, etc.), and/or other suitable material. The material of the placeholder gates218may be formed by any suitable process including CVD, PECVD, HDP-CVD, Physical Vapor Deposition (PVD), ALD, PEALD, and/or other suitable deposition processes. In some examples, the material of the placeholder gates218is deposited in a blanket deposition and etched to selectively remove portions of the material so that the placeholder gates218remain over the channel regions of the fins210. To aid in patterning, one or more gate hard mask layers (e.g., layers220and222) of dielectric material or other suitable material may be formed on top of the placeholder gate material prior to etching. The gate hard mask layers220and222may have similar or different compositions, and in an example, a first gate hard mask layer220includes a semiconductor nitride and a second gate hard mask layer222includes a semiconductor oxide.

The placeholder gates218run perpendicular to the fins210and extend above the top of the fins210(including any fin-top hard masks212) as indicated by marker223. In an example where the fins210and fin-top hard mask212extend between about 100 nm and about 500 nm above the topmost surface of the isolation dielectric layer216, the placeholder gates218extend between about 50 nm and about 150 nm from the upper-most surface of the fin-top hard mask212.

Referring to block104ofFIG. 1Aand toFIG. 3, gate spacers302are formed on side surfaces of the placeholder gates218and any gate hard mask layers220and222. In various examples, the gate spacers302include one or more layers of suitable materials, such as a dielectric material (e.g., a semiconductor oxide, a semiconductor nitride, a semiconductor oxynitride, a semiconductor carbide, a semiconductor oxycarbonitride, etc.). In some such examples, the gate spacers302each include a first spacer layer304of a low-k dielectric material (e.g., SiCN, SiOC, SiOCN, etc.) and a second spacer layer306of the same or another low-k dielectric material. In the example, the first spacer layer304has a thickness between about 1 nm and about 5 nm and the second spacer layer306has a thickness between about 1 nm and about 5 nm.

The gate spacer layers304and306may be formed using any suitable deposition technique (e.g., ALD, CVD, HDP-CVD, etc.). In an example, the gate spacer layers304and306are deposited on the placeholder gates218, the fins210, and the isolation dielectric layer216using a conformal technique. The gate spacer layers304and306are then selectively etched to remove them from the horizontal surfaces of the gate hard mask layers220and222, the fins210, and the isolation dielectric layer216while leaving them on the vertical surfaces of the placeholder gates218. The remaining material defines the gate spacers302. The etching process may be performed using any suitable etching method, such as anisotropic dry etching, wet etching, Reactive Ion Etching (RIE), and/or other etching methods and may use any suitable etchant chemistries. The etching methods and the etchant chemistries may vary as the gate spacer layers304and306are etched to target the particular material being etched while minimizing unintended etching of the materials not being targeted.

Referring to block106ofFIG. 1Aand toFIG. 4, source/drain features402are formed on opposing sides of the placeholder gates218. The source/drain features402may be formed by recessing a portion of the fins210and depositing material in the recess using a CVD deposition technique (e.g., Vapor-Phase Epitaxy (VPE) and/or Ultra-High Vacuum CVD (UHV-CVD)), molecular beam epitaxy, and/or other suitable processes. The epitaxy process may use gaseous and/or liquid precursors, which interact with a component of the remaining portions of the fins210(e.g., silicon or silicon-germanium) to form the source/drain features402. The semiconductor component of the source/drain features402may be similar to or different from the remainder of the fin210. For example, Si-containing source/drain features402may be formed on a SiGe-containing fin210or vice versa. When the source/drain features402and fins210contain more than one semiconductor, the ratios may be substantially similar or different.

The source/drain features402may be in-situ doped to include p-type dopants, such as boron, BF2, or indium; n-type dopants, such as phosphorus or arsenic; and/or other suitable dopants including combinations thereof. Additionally or in the alternative, the source/drain features402may be doped using an implantation process (i.e., a junction implant process) after the source/drain features402are formed. With respect to the particular dopant type, the source/drain features402are doped to be of opposite type than the remainder of the fins210. For a p-channel device, the fin210is doped with an n-type dopant and the source/drain features402are doped with a p-type dopant, and vice versa for an n-channel device. Once the dopant(s) are introduced into the source/drain features402, a dopant activation process, such as Rapid Thermal Annealing (RTA) and/or a laser annealing process, may be performed to activate the dopants.

Referring to block108ofFIG. 1Aand toFIG. 5, an etching process is performed to thin the outermost layer or layers of the gate spacers302(e.g., gate spacer layer306). Thinning the gate spacers302may provide additional space for contacts to extend alongside the gate spacers302and contact the source/drain features402. This additional space may allow for wider contact trenches and wider contacts. As narrow contact trenches may be more difficult to uniformly fill with contact material, thinning the gate spacers302may improve the fill quality of the deposited contact material. Wider contacts may also have reduced contact resistance and allow for more overlay error when depositing subsequent materials. In these ways and others, the thinner gate spacers302may provide more reliable circuit devices.

The process may use any suitable etching technique, including dry etching, wet etching, RIE, and other suitable techniques, and in some examples, the gate spacers302are thinned using wet etching with Standard Clean 1 (SC-1) (a mixture of NH4OH, H2O2, and H2O), and/or Standard Clean 2 (SC-2) (a mixture of HCl, H2O2, and H2O). The process may remove any suitable thickness502, and in various such examples, between about 1 nm and about 2 nm of the outer gate spacer layer306is removed, leaving a total gate spacer302width of between about 1 nm and about 10 nm. In some examples, the thinning technique may leave a bottommost portion of the gate spacers302unetched so that the bottommost portion is thicker than a topmost portion by, for example, between about 1 nm and about 2 nm.

Referring to block110ofFIG. 1Aand toFIG. 6, a Bottom Contact Etch Stop Layer (BCESL)602is formed on the source/drain features402and along the top and sides of the placeholder gates218and gate hard mask layers220and222. The BCESL602may be formed by any suitable technique, including ALD, PEALD, CVD, PECVD, and/or HDP-CVD, and may be formed to any suitable thickness. In some examples, the BCESL602has a thickness between about 1 nm and about 10 nm. The BCESL602may include a dielectric (e.g., a semiconductor oxide, a semiconductor nitride, a semiconductor oxynitride, a semiconductor carbide, etc.) and/or other suitable material, and in various embodiments, the BCESL602includes SiN, SiO, SiON, and/or SiC.

Referring to block112ofFIG. 1Aand toFIG. 7, an Inter-Level Dielectric (ILD) layer702is formed on the workpiece200. The ILD layer702acts as an insulator that supports and isolates conductive traces of an electrical multi-level interconnect structure. In turn, the multi-level interconnect structure electrically interconnects elements of the workpiece200, such as the source/drain features402and the functional gates. The ILD layer702may be formed by any suitable process including CVD, PVD, spin-on deposition, and/or other suitable processes. The ILD layer702may include a dielectric material (e.g., a semiconductor oxide, a semiconductor nitride, a semiconductor oxynitride, a semiconductor carbide, etc.), Spin-On-Glass (SOG), fluoride-doped silicate glass (FSG), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), Black Diamond® (Applied Materials of Santa Clara, Calif.), Xerogel, Aerogel, amorphous fluorinated carbon, parylene, BCB, SILK® (Dow Chemical of Midland, Mich.), and/or combinations thereof.

As illustrated inFIG. 8, a Chemical Mechanical Planarization/Polishing (CMP) process may be performed following the deposition of the ILD layer702to planarize the ILD layer702, the BCESL602, the gate spacers302, and the placeholder gates218. In particular, the CMP process may remove the gate hard mask layers220and222from the top of the placeholder gates218.

Referring to block114ofFIG. 1Aand referring toFIG. 9, the remaining placeholder gates218are removed. Removing the placeholder gates218form recesses between the gate spacers302in which to form functional gates. The placeholder gates218may be removed using one or more iterations of various etching techniques, such as dry etching, wet etching, RIE, etc., each configured to selectively etch a particular material or set of materials of the placeholder gates218.

In general, the techniques and etchants may be configured to avoid significant etching of the surrounding materials such as the ILD layer702and the gate spacers302. However, in some examples, the etching may be configured to thin the materials of the gate spacers302(e.g., gate spacer layer304). Thinning the gate spacers302may widen the recesses for the functional gates. In turn, the wider recesses may improve the quality and uniformity of the gate materials. The wider recesses may also allow the formation of wider functional gates, which may increase the control over the channel region, reduce gate resistance, and reduce alignment issues. In this way and others, the thinner gate spacers302may provide more reliable circuit devices. The etching may remove any suitable thickness, and in various such examples, between about 1 nm and about 2 nm of the gate spacer layer304is removed, leaving a total gate spacer302width of between about 1 nm and about 10 nm.

The etching technique(s) used to remove the placeholder gates218may also cause some inadvertent etching of the ILD layer702as shown inFIG. 9.

Referring to block116ofFIG. 1Aand referring toFIG. 10, a portion of the I/O oxide layer214that is exposed by removing the placeholder gates218is removed. The I/O oxide layer214may be removed using any suitable etching technique such as dry etching, wet etching, RIE, and/or other suitable techniques. Removing the I/O oxide layer214may expose the fin-top hard mask212disposed on the top of the fins210and may expose the side surfaces of the fins210themselves.

Referring to block118ofFIG. 1Aand toFIGS. 11 and 12, functional gates1102are formed in the recesses left by removing the placeholder gates218. The functional gates1102may include multiple layers of dielectric and conductor materials. For clarity, the gate electrode1106, which may itself include multiple layers of different materials, is shown as a single feature in the intermediate figures, and exemplary layers that form the gate electrode1106are shown in the context of the final structure.

In some examples, the forming of the functional gates1102in the recesses begins by forming an interfacial layer on the side surfaces of the fins210. The interfacial layer may include an interfacial material, such as a semiconductor oxide, semiconductor nitride, semiconductor oxynitride, other semiconductor dielectrics, other suitable interfacial materials, and/or combinations thereof. The interfacial layer may be formed to any suitable thickness using any suitable process including thermal growth, ALD, CVD, HDP-CVD, PVD, spin-on deposition, and/or other suitable deposition processes. In some examples, the interfacial layer is formed by a thermal oxidation process and includes a thermal oxide of a semiconductor present in the fins210(e.g., silicon oxide for silicon-containing fins210, silicon-germanium oxide for silicon-germanium-containing fins210, etc.).

A gate dielectric1104is formed on the interfacial layer on the side surfaces of the fins210and is formed on the fin-top hard mask212on top of the fins210. The gate dielectric1104may include one or more dielectric materials, which are commonly characterized by their dielectric constant relative to silicon dioxide. In some embodiments, the gate dielectric1104includes a high-k dielectric material, such as HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, zirconium oxide, aluminum oxide, hafnium dioxide-alumina (HfO2—Al2O3) alloy, other suitable high-k dielectric materials, and/or combinations thereof. Additionally or in the alternative, the gate dielectric1104may include other dielectrics, such as a semiconductor oxide, semiconductor nitride, semiconductor oxynitride, semiconductor carbide, amorphous carbon, TEOS, other suitable dielectric material, and/or combinations thereof. The gate dielectric1104may be formed using any suitable process including ALD, PEALD, CVD, Plasma Enhanced CVD (PE CVD), HDP-CVD, PVD, spin-on deposition, and/or other suitable deposition processes. The gate dielectric1104may be formed to any suitable thickness, and in some examples, the gate dielectric1104has a thickness of between about 0.1 nm and about 3 nm.

A gate electrode1106is formed on the gate dielectric1104above and between the fins210. The gate electrode1106may include a number of different conductive layers, including capping layers, work function layers, and an electrode fill. For example, forming a gate electrode may include forming one or more capping layers on the gate dielectric1104to prevent migration of other gate materials into the gate dielectric1104. The capping layer(s) may include any suitable conductive material including metals (e.g., W, Al, Ta, Ti, Ni, Cu, Co, etc.), metal nitrides, and/or metal silicon nitrides, and may be deposited via CVD, ALD, PE CVD, PEALD, PVD, and/or other suitable deposition processes. In various embodiments, the capping layer(s) include TaSiN, TaN, and/or TiN.

In some examples, forming a gate electrode1106includes forming one or more work function layers on the capping layer(s). Suitable work function layer materials include n-type and/or p-type work function materials based on the type of circuit device being formed. Exemplary p-type work function metals include TiN, TaN, Ru, Mo, Al, WN, ZrSi2, MoSi2, TaSi2, NiSi2, WN, other suitable p-type work function materials, and/or combinations thereof. Exemplary n-type work function metals include Ti, Ag, TaAl, TaAlC, TiAlN, TaC, TaCN, TaSiN, Mn, Zr, other suitable n-type work function materials, and/or combinations thereof. The work function layer(s) may be deposited by any suitable technique including ALD, PEALD, CVD, PE CVD, PVD, and/or combinations thereof. Because the p-channel and n-channel devices may have different work function layers, in some examples, the p-type work function layers are deposited in a first deposition process that uses a dielectric hard mask to prevent depositing on the electrodes of the n-channel devices, and the n-type work function layers are deposited in a second deposition process that uses a dielectric hard mask to prevent depositing on the electrodes of the p-channel devices.

In some examples, forming a gate electrode1106includes forming an electrode fill on the work function layer(s). The electrode fill may include any suitable material including metals (e.g., W, Al, Ta, Ti, Ni, Cu, Co, etc.), metal oxides, metal nitrides and/or combinations thereof, and in an example, the electrode fill includes tungsten. The electrode fill may be deposited by any suitable technique including ALD, PEALD, CVD, PE CVD, PVD, and/or combinations thereof.

Forming the functional gates1102may also include forming a conductive cap layer1108on the gate electrode1106. The conductive cap layer1108may include any suitable conductive material including metals (e.g., W, Al, Ta, Ti, Ni, Cu, Co, etc.), metal oxides, metal nitrides and/or combinations thereof. The material(s) of the conductive cap layer1108may be deposited by any suitable technique including ALD, PEALD, CVD, PE CVD, PVD, and/or combinations thereof. In some examples, the conductive cap layer1108includes tungsten and is formed by a fluorine-free ALD process.

Referring to block120ofFIG. 1Aand toFIGS. 13-14, after depositing the materials that form the functional gates1102, a CMP process is performed on the workpiece200. The CMP process may remove some or all of the conductive cap layer1108from over the fins210.

Referring to block122ofFIG. 1Band toFIGS. 15-16, the materials of the functional gate1102are etched back to remove the functional gate1102from the top of the fins210while leaving the functional gate1102materials alongside the fins210. This may include performing one or more etching processes (e.g., dry etching, wet etching, RIE, etc.) configured to etch the gate dielectric1104and the gate electrode1106without significant etching of the surrounding materials, such as the gate spacers302, the fin-top hard mask212, and the ILD layer702. In particular, the process of block122may be configured to stop etching when the fin-top hard mask212is exposed. In this way, the topmost surfaces of the gate dielectric1104and the gate electrode1106alongside the fins210inFIG. 16may be substantially coplanar with the topmost surface of the fin-top hard mask212inFIG. 15.

Referring to block124ofFIG. 1Band referring still toFIGS. 15-16, the uppermost portions of the gate spacers302(e.g., gate spacer layers304and306) are etched back to create additional space for gate contacts to couple to the functional gates1102. This may include etching back the BCESL602so that the top of the BCESL remains substantially coplanar with the top of the gate spacers302. The etch back of the gate spacers302may include one or more etching processes (e.g., dry etching, wet etching, RIE, etc.) configured to etch the gate spacer layers304and306and/or the BCESL602without significant etching of the surrounding materials. The etching may be configured to stop while some portion of the gate spacers302remains over the fins210and over the functional gates1102. In various examples where the ILD layer702extends about 100 nm above the fin210as indicated by marker1502, the remaining gate spacers302may have a height between about 25 nm and about 75 nm as indicated by marker1504, while between about 25 nm and 75 nm of the ILD layer702is free of the gate spacers302as indicated by marker1506. In various such examples, after etching, the height1504of the gate spacer302over the fins210is between about 30% and about 60% of the height1502of the ILD layer702over the fins210.

By etching back the gate spacers302, additional space is created for the gate contacts. In some examples, the recess between the gate spacers302is between about 10 nm and about 15 nm in width as indicated by marker1508, while the recess above the gate spacers302is between about 15 nm and about 25 nm in width as indicated by marker1510. Because the aspect ratio of a recess affects how evenly contact materials are deposited, reducing the height of the narrower recess between the gate spacers302may improve the quality and uniformity of the resulting contacts.

Referring to block126ofFIG. 1Band toFIGS. 17-18, an additional gate spacer layer (third gate spacer layer1702) is formed on the side surfaces of the existing gate spacers302. The third gate spacer layer1702may also be formed on top surfaces of the gate spacers302, the BCESL602, the fin-top hard mask212, the gate dielectric1104, and the gate electrode1106as well as the side surfaces of the ILD layer702. The third gate spacer layer1702may be formed using any suitable deposition technique (e.g., ALD, CVD, HDP-CVD, etc.). The third spacer layer1702may be formed to any suitable thickness, and in some such examples, the third spacer layer1702has a thickness between about 1 nm and about 5 nm. By forming the third spacer layer1702on the functional gate1102after the gates have been formed, the gate spacer302is thinner alongside the gate1102than above the gates, which may improve the ability to form the layers of the functional gates1102between the gate spacers302.

The third gate spacer layer1702may include one or more layers of suitable materials, such as a dielectric material (e.g., a semiconductor oxide, a semiconductor nitride, a semiconductor oxynitride, a semiconductor carbide, a semiconductor oxycarbonitride, etc.). In some such examples, the third gate spacer layer1702includes a low-k dielectric material (e.g., SiCN, SiOC, SiOCN, etc.) that may be the same or different from a material of the first spacer layer304and the second spacer layer306.

Referring to block128ofFIG. 1Band toFIGS. 19-20, a break-thru etching is performed on the third gate spacer layer1702to expose at least the top of the gate electrode1106. In some examples, the break-thru etching is configured to remove the third spacer layer1702from horizontal surfaces (e.g., the top surfaces of the gate spacers302, the BCESL602, the fin-top hard mask212, the gate dielectric1104, and/or the gate electrode1106), while leaving the third spacer layer1702on the vertical surfaces of the gate spacer302and/or the ILD layer702. The etching may use any suitable technique including anisotropic dry etching, wet etching, and/or RIE and may be configured to remove the third gate spacer layer1702from the horizontal surfaces without significant etching of the surrounding materials.

Referring to block130ofFIG. 1Band toFIGS. 21-22, a second conductive cap layer2102is formed on the gate electrode1106and on the fin-top hard mask212. The second conductive cap layer2102extends over a fin210and the fin-top hard mask212to couple gate electrodes1106on opposite sides of the fin210. In particular, the second conductive cap layer2102extends between the gate spacers302and physically contacts the third gate spacer layer1702of the gate spacers302. The second conductive cap layer2102may include any suitable conductive material including metals (e.g., W, Al, Ta, Ti, Ni, Cu, Co, etc.), metal oxides, metal nitrides and/or combinations thereof, and in an example, the second conductive cap layer2102includes tungsten. The material(s) of the second conductive cap layer2102may be deposited by any suitable technique including ALD, PEALD, CVD, PE CVD, PVD, and/or combinations thereof. In some examples, the second conductive cap layer2102includes tungsten and is formed by a fluorine-free ALD process. The second conductive cap layer2102may be formed to any suitable thickness, and in some examples, the second conductive cap layer2102has a thickness between about 2 nm and about 10 nm.

In examples where the third gate spacer layer1702is formed on the side surfaces of the ILD layer702, the third gate spacer layer1702may be removed from these surfaces as shown in blocks132-138. Referring first to block132ofFIG. 1Band referring still toFIGS. 21-22, a sacrificial material2104is formed on the second conductive cap layer2102within a recess defined by the third gate spacer layer1702. The sacrificial material2104may include any suitable material such as a dielectric, amorphous silicon, and/or other suitable materials, and the material(s) may be selected to have a different etch selectivity than, for example, the third gate spacer layer1702and the second conductive cap layer2102.

Referring to block134ofFIG. 1Band toFIGS. 23-24, the sacrificial material2104is etched back to expose the portions of the third gate spacer layer1702on the side surfaces of the ILD layer702. The etching may be controlled to protect the portions of the third gate spacer layer1702disposed on the side surfaces of the gate spacers302. Accordingly, after etching, a top surface of the sacrificial material2104may be substantially coplanar with a top surface of the gate spacers302and a top surface of the BCESL602. The etching process may use any suitable etching technique including wet etching, dry etching, and/or RIE.

Referring to block136ofFIG. 1Band toFIGS. 25-26, the exposed portions of the third gate spacer layer1702on the side surfaces of the ILD layer702are removed. The third gate spacer layer1702may be removed using any suitable etching technique including wet etching, dry etching, and/or RIE. The particular etching technique(s) and etchant(s) may be selected to avoid significant etching of surrounding materials such as the ILD layer702, the gate spacers302, and/or the BCESL602.

Referring to block138ofFIG. 1Band referring still toFIGS. 25-26, the remaining sacrificial material2104may be removed. This may be performed substantially as described in block134.

Referring to block140ofFIG. 1Band toFIGS. 27-28, a Self-Aligned Contact (SAC) dielectric layer2702is formed on the second conductive cap layer2102over the fin210and over the functional gate1102. The SAC dielectric layer2702may include any suitable material, such as one or more dielectric materials including a semiconductor oxide, a semiconductor nitride, a semiconductor oxynitride, a semiconductor carbide, a semiconductor carbonitride, a semiconductor oxycarbonitride, and/or a metal oxide. In various examples, the SAC dielectric layer2702includes HfO, ZrO, AlO, LaO, BN, silicon oxide, silicon nitride, silicon carbonitride, silicon oxynitride, and/or silicon oxycarbonitride.

The SAC dielectric layer2702may be formed by any suitable process, and in some examples, the SAC dielectric layer2702is deposited using CVD, PECVD, HDP-CVD, PVD, ALD, PEALD, and/or other deposition processes. The deposition may be followed by a CMP process to remove material outside of the gate region, and the planarized SAC dielectric layer2702within the gate region may have any suitable thickness following the CMP process. In various examples, the SAC dielectric layer2702has a thickness between about 50 nm and about 150 nm.

Referring to block142ofFIG. 1Band toFIGS. 29-31, the workpiece200may then be provided for further fabrication. In various examples, this includes forming contacts2902electrically coupling to the source/drain features402and to the functional gates1102, forming a Contact Etch Stop Layer (CESL)2904on the ILD layer702and the contacts2902, forming a remainder of an electrical interconnect structure, dicing, packaging, and other fabrication processes.

By thinning the gate spacer layers304and306and by forming the third gate spacer layer1702on top of the functional gate1102rather than alongside, some examples of the present technique provide a relatively wider recess in which to form the functional gate1102. In general, a wider functional gate1102provides better control of the carriers through the channel region and reduces or avoids adverse short channel effects such as drain-induced barrier lowering, punchthrough, velocity saturation, and hot carrier degradation. Wider functional gates1102may also reduce contact alignment issues. Accordingly, the present technique may achieve these benefits and others without encroaching on the contacts2902and thereby compromising contact formation. Moreover, by removing the functional gate1102from the top of the fins210, the gate capacitance may be reduced, which in turn may improve switching speed and the AC response of the transistor.

FIGS. 30-31show the material layers of the gate electrode1106in more detail and includes a capping layer3002, a work function layer3004, and an electrode fill3006each substantially as described above.

Referring toFIG. 31, two regions of the workpiece200are shown. In a first region3102, the functional gate1102extends alongside the fin210and the fin-top hard mask212to a top surface of the fin-top hard mask212. However, due to process conditions such as the etch rate, in a second region3104, the functional gate1102extends alongside the fin210but stops at or near the bottom of the fin-top hard mask212. Instead, the side surfaces of the fin-top hard mask212are covered by the third gate spacer layer1702. Both configurations are equally suitable.

Referring next toFIGS. 32-34, another workpiece3200is illustrated that is also formed by method100.FIG. 32is a cross-sectional illustration of the workpiece3200taken in a fin-length direction that cuts through a fin according to various aspects of the present disclosure.FIG. 33is a cross-sectional illustration of the workpiece3200taken in the fin-length direction that cuts through an isolation feature according to various aspects of the present disclosure.FIG. 34is a cross-sectional illustration of the workpiece3200taken in a gate-length direction that cuts through a gate structure according to various aspects of the present disclosure.

The workpiece3200is substantially similar to workpiece200except that the process of removing the third gate spacer layer1702from the side surfaces of the ILD layer702of blocks132-138are omitted. Accordingly, the third gate spacer layer1702is disposed between the ILD layer702and SAC dielectric layer2702and/or between the ILD layer702and the contacts2902depending on whether the SAC dielectric layer2702was replaced by a contact2902at a particular location.

Further examples that use an alternative technique for forming a Bottom Contact Etch Stop Layer are described with references toFIGS. 35-50.FIG. 35is a flow diagram of a method3500of fabricating a workpiece3600using selective deposition according to various aspects of the present disclosure. Additional steps can be provided before, during, and after the method3500, and some of the steps described can be replaced or eliminated for other embodiments of the method3500.FIGS. 36-38, 40, 42, 44, 46, and 48are cross-sectional illustrations of the workpiece3600taken in a fin-length direction that cut through a fin according to various aspects of the present disclosure.FIGS. 39, 41, 43, 45, 47, and 49are cross-sectional illustrations of the workpiece3600taken in the fin-length direction that cut through an isolation feature according to various aspects of the present disclosure.FIG. 50is a cross-sectional illustration of a workpiece3600taken in a gate-length direction that cuts through a gate structure according to various aspects of the present disclosure.

Referring to block3502ofFIG. 35and toFIG. 36, the processes of blocks102-108ofFIG. 1Aare performed substantially as described above. Accordingly, a workpiece3600may be received that is substantially similar to workpiece200. The workpiece3600includes a substrate208, fins210extending from the substrate, a fin-top hard mask212disposed on the fins210, an I/O oxide layer214disposed on the fins210and the fin-top hard mask212, placeholder gates218disposed on the fins, and gate hard mask layers220and222disposed on the placeholder gates218. Gate spacers302(e.g., gate spacer layers304and306) are formed on side surfaces of the placeholder gates218. Source/drain features402are formed on opposite sides of the placeholder gates218. An etching process is performed to thin the outermost layer of the gate spacers302(e.g., gate spacer layer306).

Referring to block3504ofFIG. 35and toFIG. 37, a BCESL3702is selectively formed on the source/drain features402. A number of suitable techniques may be used to prevent formation of the BCESL3702elsewhere, such as on the side surfaces of the gate spacers302. In some such examples, a pre-treatment is applied to the workpiece3600to remove a native oxide from the source/drain features402. The pre-treatment may include applying a wet chemical solution (e.g., HF, HCl, and/or other solutions) to the workpiece3600, applying a vacuum such as an ultra-high vacuum (i.e., approximately on the order of 10−8Torr or less), and/or other suitable cleaning techniques.

An inhibitor may be selectively formed on the surfaces where the BCESL3702is to be excluded. For example, an inhibitor may be deposited on the side surfaces of the gate spacers302(e.g., gate spacer layer306). The inhibitor may be configured to prevent adhesion of the subsequently formed BCESL3702and may include a dielectric, a polymer, and/or other suitable materials.

After the inhibitor is applied, the BCESL3702is formed on the source/drain features402. The BCESL3702may be deposited by any suitable technique, including ALD, PEALD, CVD, PECVD, and/or HDP-CVD, and the inhibitor may prevent the BCESL3702from being deposited on those surfaces where the inhibitor is present.

The BCESL3702may include a dielectric (e.g., a semiconductor oxide, a semiconductor nitride, a semiconductor oxynitride, a semiconductor carbide, etc.) and/or other suitable material, and in various embodiments, the BCESL3702includes SiN, SiO, SiON, and/or SiC. The BCESL3702may be formed to any suitable thickness, and in some examples, the BCESL3702has a thickness between about 1 nm and about 10 nm.

After the BCESL3702is formed, any remaining inhibitor may be removed.

Referring to block3506ofFIG. 35and toFIGS. 38-39, blocks112-124ofFIGS. 1A-1Bare performed on the workpiece3600. In some examples, an Inter-Level Dielectric (ILD) layer702is formed on the workpiece3600, and the remaining placeholder gates218are removed. A portion of the I/O oxide layer214exposed by removing the placeholder gates218is also removed. Functional gates1102are formed in the recesses left by removing the placeholder gates218, and a CMP process is performed on the workpiece3600. The materials of the functional gate1102are etched back to remove the functional gate1102from the top of the fins210while leaving the functional gate1102materials alongside the fins210. The uppermost portions of the gate spacers302(e.g., gate spacer layers304and306) are etched back to create additional space for gate contacts to couple to the functional gates1102.

Referring to block3508ofFIG. 35and toFIGS. 40-41, an additional gate spacer layer (third gate spacer layer4002) is formed on the side surfaces of the existing gate spacers302. The third gate spacer layer4002may also be formed on the top surface of the functional gate1102. In some examples, a selective deposition technique is used to avoid forming the third gate spacer layer4002elsewhere, such as on the side surfaces of the ILD layer702.

This may include selectively forming an inhibitor on the surfaces where the third gate spacer layer4002is to be excluded. For example, an inhibitor may be deposited on the side surfaces of the ILD layer702. The inhibitor may be configured to prevent adhesion of the subsequently formed third gate spacer layer4002and may include a dielectric, a polymer, and/or other suitable materials.

After the inhibitor is applied, the third gate spacer layer4002is formed on the source/drain features402. The third gate spacer layer4002may be deposited by any suitable technique, including ALD, PEALD, CVD, PECVD, and/or HDP-CVD, and the inhibitor may prevent the third gate spacer layer4002from being deposited on those surfaces where the inhibitor is present.

The third gate spacer layer4002may include one or more layers of suitable materials, such as a dielectric material (e.g., a semiconductor oxide, a semiconductor nitride, a semiconductor oxynitride, a semiconductor carbide, a semiconductor oxycarbonitride, etc.). In some such examples, the third gate spacer layer4002includes a low-k dielectric material (e.g., SiCN, SiOC, SiOCN, etc.) that may be the same or different from a material of the first spacer layer304and the second spacer layer306. The third spacer layer4002may be formed to any suitable thickness, and in some such examples, the third spacer layer4002has a thickness between about 1 nm and about 5 nm.

After the third spacer layer4002is formed, any remaining inhibitor may be removed.

Referring to block3510ofFIG. 35and toFIGS. 42-43, a break-thru etching is performed on the third gate spacer layer4002to expose at least the top of the gate electrode1106. This may be performed substantially similar to block128ofFIG. 1B.

Referring to block3512ofFIG. 35and toFIGS. 44-45, a second conductive cap layer2102is formed on the gate electrode1106and on the fin-top hard mask212. This may be performed substantially similar to block130ofFIG. 1B.

Referring to block3514ofFIG. 35and toFIGS. 46-47, a SAC dielectric layer2702is formed on the second conductive cap layer2102over the fin210and over the functional gate1102. This may be performed substantially similar to block140ofFIG. 1B.

Referring to block3516ofFIG. 35and toFIGS. 48-50, the workpiece3600may then be provided for further fabrication. In various examples, this includes forming contacts2902coupling to the source/drain features402and to the functional gates1102, forming a CESL2904on the ILD layer702and the contacts2902, forming a remainder of an electrical interconnect structure, dicing, packaging, and other fabrication processes. By not forming the BCESL3702on the side surfaces of the gate spacers302, the method3500allows the formation of wider contacts2902with less separation between the contacts2902and the functional gate1102. All other dimensions may be substantially similar to the examples of method100.

Thus, the present disclosure provides examples of an integrated circuit with FinFET gates and a method for forming the integrated circuit. In some embodiments, an integrated circuit device includes a substrate, a fin extending from the substrate, a first gate disposed on a first side of the fin, and a gate spacer disposed alongside the first gate. The gate spacer has a first portion extending along the first gate that has a first width and a second portion extending above the first gate that has a second width that is greater than the first width. In some such embodiments, the second portion of the gate spacer includes a gate spacer layer disposed on the first gate. In some such embodiments, the gate spacer layer physically contacts a gate dielectric of the first gate and physically contacts a side surface of another gate spacer layer. In some such embodiments, the integrated circuit device further includes a second gate disposed on a second side of the fin, and a conductive cap disposed on the fin, the first gate, and the second gate. The conductive cap electrically couples the first gate and the second gate. In some such embodiments, the second portion of the gate spacer includes a gate spacer layer that physically contacts a side surface of the conductive cap and a top surface of the first gate. In some such embodiments, the integrated circuit device further includes a hard mask disposed on the fin between the fin and the conductive cap. In some such embodiments, a top surface of the first gate is substantially coplanar with a top surface of the hard mask. In some such embodiments, the integrated circuit device further includes an inter-level dielectric layer disposed on the fin. The inter-level dielectric layer extends above a top surface of the gate spacer. In some such embodiments, the integrated circuit device further includes a contact etch stop layer disposed on the fin alongside the gate spacer. A top surface of the contact etch stop layer is substantially coplanar with a top surface of the gate spacer. In some such embodiments, the gate spacer further has a third portion disposed on the fin and having a third width, and a fourth portion disposed on the third portion and having a fourth width that is less than the third width.

In further embodiments, a device includes a substrate having a fin, an isolation dielectric disposed on the substrate such that the fin extends above the isolation dielectric, a pair of gate structures disposed on the isolation dielectric on opposing sides of the fin, a gate spacer disposed on a side surface of the pair of gate structures and on the fin, and an interlevel dielectric disposed on the isolation dielectric and on the fin. The interlevel dielectric extends alongside and above the gate spacer. In some such embodiments, the gate spacer has a first thickness adjacent the pair of gate structures and a second thickness that is greater than the first thickness above the pair of gate structures and above the fin. In some such embodiments, the interlevel dielectric physically contacts the gate spacer. In some such embodiments, the device further includes a contact electrically coupled to the pair of gate structures, and the interlevel dielectric physically contacts the contact. In some such embodiments, the device further includes, a conductive cap disposed on the fin and on the pair of gate structures to electrically couple the pair of gate structures. The conductive cap is disposed between the fin and the contact.

In yet further embodiments, a method of fabricating an integrated circuit device includes receiving a substrate having a fin extending from the substrate and a placeholder gate disposed on the fin and disposed on opposing sides of the fin. A gate spacer is formed on a side surface of the placeholder gate, and a gate replacement process is performed to replace the placeholder gate with a functional gate. An additional gate spacer layer is formed on a side surface of the gate spacer and on a top surface of the functional gate. In some such embodiments, the functional gate is recessed to remove the functional gate from a top surface of the fin prior to the forming of the additional gate spacer layer. In some such embodiments, a conductive cap is formed on the fin to electrically couple a first portion of the functional gate on a first side of the fin to a second portion of the functional gate on a second side of the fin. In some such embodiments, the additional gate spacer layer extends along a side surface of the conductive cap. In some such embodiments, forming an inter-level dielectric is formed on the substrate, and removing the additional gate spacer layer is removed from a side surface of the inter-level dielectric.