NITRIDE SEMICONDUCTOR MODULE

A nitride semiconductor module includes a chip including at least one transistor, wherein the chip includes: a semiconductor substrate including a substrate upper surface and a substrate lower surface facing an opposite side of the substrate upper surface; an electron transit layer formed over the substrate upper surface of the semiconductor substrate and made of GaN; and an electron supply layer formed over the electron transit layer and made of GaN having a larger band gap than the electron transit layer, wherein the at least one transistor includes a gate electrode, a source electrode, and a drain electrode, which are formed over the electron supply layer, and wherein the semiconductor substrate is a GaN substrate having a thickness of 100 μm or less.

CROSS-REFERENCE TO RELATED APPLICATION

This application is based upon and claims the benefit of priority from Japanese Patent Application No. 2023-095603, filed on Jun. 9, 2023, the entire contents of which are incorporated herein by reference.

TECHNICAL FIELD

The present disclosure relates to a nitride semiconductor module.

BACKGROUND

Currently, a high electron mobility transistor (HEMT) using a Group III nitride semiconductor such as a gallium nitride (GaN) semiconductor or the like (hereinafter, sometimes referred simply as a “nitride semiconductor”) is being commercialized. The HEMT uses a two-dimensional electron gas (2DEG) formed near an interface of a semiconductor heterojunction as a conductive path (channel). A power device using the HEMT is recognized as a device that enables a lower on-resistance, higher speed operation and higher frequency operation than a typical silicon (Si) power device.

For example, in the related art, a nitride semiconductor device includes a silicon substrate, an electron transit layer made of a gallium nitride (GaN) layer, and an electron supply layer made of an aluminum gallium nitride (AlGaN) layer. A 2DEG is formed in the electron transit layer near the interface of the heterojunction between the electron transit layer and the electron supply layer. Further, in the nitride semiconductor device of the related art, a gate layer (e.g., a p-type GaN layer) containing an acceptor type impurity is provided over the electron supply layer and directly below a gate electrode. According to this configuration, in a region directly below the gate layer, the gate layer raises a band energy of a conduction band near the interface of the heterojunction between the electron transit layer and the electron supply layer, causing the channel directly below the gate layer to disappear to realize a normally-off state.

DETAILED DESCRIPTION

Hereinafter, embodiments of a semiconductor module according to the present disclosure will be described with reference to the accompanying drawings. For simplicity and clarity of explanation, the components shown in the drawings are not necessarily drawn to a constant scale. Further, in order to facilitate understanding, hatching lines may be omitted in cross-sectional views. The accompanying drawings are merely illustrative of the embodiments of the present disclosure and should not be considered as limiting the present disclosure.

The following detailed description includes apparatuses, systems, and methods that embody exemplary embodiments of the present disclosure. This detailed description is exemplary in nature and is not intended to limit the embodiments of the present disclosure or the application and uses of such embodiments.

First Embodiment

[Schematic Structure of Semiconductor Module]

FIG.1is a schematic plan view of an exemplary nitride semiconductor module (hereinafter, referred to as a semiconductor module)100according to a first embodiment.FIG.2is a cross-sectional view taken along line2-2inFIG.1.

As shown inFIGS.1and2, the semiconductor module100may be, for example, a surface-mounted package. The semiconductor module100includes a module upper surface100sand a module lower surface100rfacing an opposite side of the module upper surface100s.

The semiconductor module100includes a chip101including a transistor51to be described later, a first conductive terminal102A, a second conductive terminal102B and a third conductive terminal102C, which are electrically connected to the chip101, a heat dissipation member103, and a sealing member104that seals the chip101. In order to facilitate understanding, only an outline of the sealing member104is shown inFIGS.1and2.

The chip101includes a chip upper surface101sand a chip lower surface101rfacing an opposite side of the chip upper surface101s.The chip upper surface101sis a surface facing a same side as the module upper surface100s.The chip lower surface101ris a surface facing a same side as the module lower surface100r.A shape of the chip101in a plan view, i.e., a shape of the chip upper surface101sand the chip lower surface101rin a plan view, is, for example, rectangular. The chip101includes a semiconductor substrate12, a nitride semiconductor layer50, the transistor51, an insulator layer60, electrode pads70, and a lower surface electrode80. InFIG.2, the illustration of the electrode pads70and the lower surface electrode80is omitted.

The semiconductor substrate12is a substrate made of GaN. The semiconductor substrate12is, for example, a substrate formed of n-type GaN in which N holes function as donors. The carrier density may be, for example, 1×1016cm−3or more.

The semiconductor substrate12includes a substrate upper surface12sand a substrate lower surface12rfacing an opposite side of the substrate upper surface12s.The substrate upper surface12sis a surface facing a same side as the chip upper surface101s.The substrate lower surface12ris a surface facing a same side as the chip lower surface101r.

A Z-axis direction of mutually orthogonal XYZ axes shown inFIGS.1and2is a thickness direction of the semiconductor substrate12. The term “plan view” used in this specification refers to viewing the semiconductor module100from above along the Z-axis direction, unless explicitly stated otherwise. Details of a thickness of the semiconductor substrate12will be described later.

The nitride semiconductor layer50is formed over the substrate upper surface12sof the semiconductor substrate12. The transistor51is configured by using the nitride semiconductor layer50. Details of the nitride semiconductor layer50and the transistor51will be described later.

As shown inFIG.4, the lower surface electrode80is formed at the lower surface12rof the semiconductor substrate12. The lower surface electrode80is electrically connected to a source electrode28, which will be described later. The lower surface electrode80may be made of an arbitrary conductive material containing, for example, at least one selected from the group of titanium (Ti), nickel (Ni), nickel vanadium alloy (NiV), silver (Ag), and gold (Au). The lower surface electrode80may include one or more metal layers. For example, an example of the lower surface electrode80is an electrode in which three layers of a Ti layer, a Ni layer, and an Au layer are laminated in order from the substrate lower surface12rof the semiconductor substrate12. Further, the lower surface electrode80may be an electrode formed by stacking four layers of a Ti layer, a Ni layer, an Au layer, and an Ag layer in order from the substrate lower surface12rof the semiconductor substrate12, or an electrode formed by stacking three layers of a Ti layer, a NiV layer, and an Ag layer in order from the substrate lower surface12rof the semiconductor substrate12. The lower surface electrode80constitutes the chip lower surface101rof the chip101.

Further, the lower surface electrode80may be omitted. In this case, the semiconductor substrate12is electrically connected to a source electrode28, which will be described later. For example, the semiconductor substrate12and the source electrode28are electrically connected by forming a via in contact with the substrate upper surface12sof the semiconductor substrate12and the source electrode28in the nitride semiconductor layer50arranged between the semiconductor substrate12and the source electrode28. When the lower surface electrode80is omitted, the chip lower surface101rof the chip101may be constituted by, for example, the substrate lower surface12rof the semiconductor substrate12.

The insulator layer60is formed over the nitride semiconductor layer50. The insulator layer60may be made of, for example, a material containing any one of silicon nitride (SiN), silicon dioxide (SiO2), silicon oxynitride (SiON), alumina (Al2O3), AlN, and aluminum oxynitride (AlON). In one example, the insulator layer60is formed of a material containing SiN.

The electrode pads70are formed over an upper surface of the insulator layer60. The electrode pads70include one or more source pads71, one or more drain pads72, and one or more gate pads73.

InFIG.2, the illustration of the electrode pads70is omitted. The source pad71is electrically connected to a source electrode28, which will be described later. The drain pad72is electrically connected to a drain electrode30, which will be described later. The gate pad73is electrically connected to a gate electrode24, which will be described later. Each of the electrode pads may be made of, for example, an arbitrary conductive material containing at least one selected from the group of Ti, titanium nitride (TiN), aluminum (Al), copper (Cu), AlCu alloy, Ni, and Au. An example of the electrode pad70includes a metal layer and a plating layer covering the metal layer. The metal layer has, for example, a structure in which four layers of a Ti layer, a TiN layer, an AlCu layer, and a TiN layer are stacked in order from the upper surface of the insulator layer60. The plating layer has, for example, a structure in which a Cu layer, a Ni layer, and an Au layer are stacked in this order from the metal layer.

In the example shown inFIG.2, the chip101includes a plurality of source pads71, a plurality of drain pads72, and a plurality of gate pads73. Each of the source pads71and each of the drain pads72are formed in a rectangular shape extending in a Y-axis direction, and are arranged alternately at intervals in an X-axis direction. The gate pads73are arranged at intervals in the Y-axis direction of the pads (drain pads72inFIG.1) arranged on both sides of the X-axis direction among the source pads71and the drain pads72.

A first conductive terminal102A, a second conductive terminal102B, and a third conductive terminal102C are electrically connected to the electrode pads70of the chip101. Specifically, the first conductive terminal102A is bonded to an upper surface of the source pad71via a conductive bonding material (not shown). The second conductive terminal102B is bonded to an upper surface of the drain pad72via a conductive bonding material (not shown). The third conductive terminal102C is connected to an upper surface of the gate pad73via a wire102D.

The first conductive terminal102A, the second conductive terminal102B, and the third conductive terminal102C are made of, for example, Cu or an alloy containing Cu. A solder or conductive paste may be used as the conductive bonding material. The solder may be a lead (Pb)-free solder such as a tin (Sn)-silver (Ag)-copper (Cu)-based solder, or a lead-containing solder such as a Sn—Pb—Ag-based solder. An example of the conductive paste is an Ag paste. The wire102D is a bonding wire formed by a wire bonding device, and is made of a conductor such as gold (Au), Al, or Cu.

Each of the first conductive terminal102A and the second conductive terminal102B has, for example, a bridge shape. Each of the first conductive terminal102A, the second conductive terminal102B, and the third conductive terminal102C includes an external connection surface (each lower surface) partially exposed from the sealing member104to the module lower surface100r.The external connection surface of each of the first conductive terminal102A, the second conductive terminal102B, and the third conductive terminal102C is electrically connected to a mounting substrate when the semiconductor module100is mounted on the mounting substrate (not shown).

The heat dissipation member103is installed at the chip lower surface101rof the chip101. A method of installing the heat dissipation member103at the chip lower surface101ris not particularly limited. In one example, the heat dissipation member103is installed using a bonding material (not shown). Examples of the bonding material include a metal material such as a solder, an Ag paste, or the like, and a resin material such as a thermosetting resin, a photocurable resin, or the like. In another example, the heat dissipation member103is bonded to the chip lower surface101rof the chip101by diffusion bonding or solid phase diffusion bonding.

The heat dissipation member103includes an exposed surface partially exposed from the sealing member104to the module lower surface100r.The shape of the heat dissipation member103is not particularly limited as long as the heat dissipation member103includes the exposed surface. The heat dissipation member103is, for example, a plate-shaped heat dissipation plate. The heat dissipation member103is made of a material with good heat conductivity. The heat dissipation member103is made of, for example, ceramics or metal. Ceramics contain, for example, alumina (Al2O3) as a main component.

The sealing member104may define a package contour of the semiconductor module100. The sealing member104seals a portion of the first conductive terminal102A, a portion of the second conductive terminal102B, a portion of the third conductive terminal102C, and a portion of the heat dissipation member103, along with the chip101. The sealing member104may be made of an insulating resin material such as an epoxy resin, an acrylic resin, or a phenol resin. In one example, the sealing member104may be formed by molding an insulating resin material. The sealing member104is made of a material having lower thermal conductivity than the material (GaN) forming the semiconductor substrate12. The chip upper surface101sand the chip lower surface101rof the chip101are formed by the sealing member104.

[Details of Nitride Semiconductor Layer and Transistor]

(Schematic Structure of Transistor)

The chip101includes an active region where the transistor51is formed, and an inactive region where the transistor51is not formed in a plan view.

FIG.3is a schematic plan view of the transistor51formed in an active region. InFIG.3, the insulator layer60and the electrode pads70are omitted.FIG.4is a schematic cross-sectional view of the transistor51, and is a cross-sectional view taken along line4-4inFIG.3. In one example, the transistor51may be a HEMT using GaN. A cross-sectional structure of the transistor51will be described below with reference toFIG.4, and then a plan-view structure of the transistor51will be described with reference toFIG.3.

As shown inFIG.4, the transistor51includes the semiconductor substrate12and the nitride semiconductor layer50formed over the semiconductor substrate12. The nitride semiconductor layer50is epitaxially grown on the substrate upper surface12sof the semiconductor substrate12. The nitride semiconductor layer50includes an electron transit layer16formed over the semiconductor substrate12and an electron supply layer18formed over the electron transit layer16.

The electron transit layer16is a GaN layer made of GaN. An example of the electron transit layer16is an undoped GaN layer. Details of a thickness of the electron transit layer16will be described later. In order to suppress current leakage in the electron transit layer16, an impurity may be introduced into a portion of the electron transit layer16to make the region other than a surface layer of the electron transit layer16semi-insulating. In this case, the impurity is, for example, C, and a peak concentration of the impurity in the electron transit layer16is, for example, 1×1019cm−3or more.

The electron supply layer18is made of a nitride semiconductor having a larger band gap than the electron transit layer16. The electron supply layer18is, for example, an AlGaN layer. In this case, as the Al composition becomes larger, the bandgap becomes larger. Therefore, the electron supply layer18, which is an AlGaN layer, has a larger bandgap than the electron transit layer16, which is a GaN layer. In one example, the electron supply layer18is made of AlxGa1-xN, where x satisfies 0.1<x<0.4, more preferably 0.2<x<0.3. A thickness of the electron supply layer18is, for example, 5 nm or more and 20 nm or less.

The electron transit layer16and the electron supply layer18are composed of nitride semiconductors having different lattice constants. Therefore, the GaN layer constituting the electron transit layer16, and the GaN layer (e.g., AlGaN layer) constituting the electron supply layer18form a lattice-mismatched heterojunction. Due to the spontaneous polarization of the electron transit layer16and the electron supply layer18and the piezo polarization caused by a stress applied to the electron supply layer18near the heterojunction interface, an energy level of a conduction band of the electron transit layer16near the heterojunction interface becomes lower than the Fermi level. As a result, a two-dimensional electron gas (2DEG)20spreads in the electron transit layer16at a position close to the heterojunction interface between the electron transit layer16and the electron supply layer18(e.g., at a position within a range of several nm from the heterojunction interface).

The nitride semiconductor layer50may include layers other than the electron transit layer16and the electron supply layer18. For example, the nitride semiconductor layer50may include an intermediate layer disposed between the semiconductor substrate12and the electron transit layer16. An example of the intermediate layer is a buffer layer provided to facilitate epitaxial growth of the electron transit layer16, and may be made of an arbitrary material that is capable of facilitating the epitaxial growth of the electron transit layer16. Another example of the intermediate layer is a high resistance layer provided to suppress current leakage in a vertical direction, i.e., current leakage between the semiconductor substrate12and the drain electrode30described later, and may be made of an arbitrary material that enables epitaxial growth of the electron transit layer16. The high resistance layer is, for example, a layer with a higher resistance than the electron transit layer16.

The transistor51includes a gate layer22formed over the electron supply layer18, a gate electrode24formed over the gate layer22, and a passivation layer26. The passivation layer26is formed over the electron supply layer18, the gate layer22, and the gate electrode24, and includes a first opening26A and a second opening26B. Further, the transistor51includes a source electrode28in contact with an upper surface18A of the electron supply layer18via the first opening26A, and a drain electrode30in contact with the upper surface18A of the electron supply layer18via the second opening26B.

The gate layer22is located between the first opening26A and the second opening26B of the passivation layer26, and is spaced apart from each of the first opening26A and the second opening26B. The gate layer22is located closer to the first opening26A than the second opening26B. A thickness of the gate layer22is, for example, 50 nm or more and 200 nm or less.

The gate layer22has a smaller band gap than the electron supply layer18and is made of a nitride semiconductor containing an acceptor type impurity. The gate layer22may be made of, for example, an arbitrary material having a smaller bandgap than the electron supply layer18, which is an AlGaN layer. In one example, the gate layer22is a GaN layer (p-type GaN layer) doped with an acceptor type impurity.

The acceptor type impurity may include at least one selected from the group of magnesium (Mg), zinc (Zn), and C. An example of the acceptor type impurity is Mg. A maximum concentration of the acceptor type impurity in the gate layer22is, for example, 1×1018cm−3or more or 1×1019cm−3or more. The maximum concentration of the acceptor type impurity in the gate layer22is, for example, 1×1020cm−3or less.

Since the acceptor type impurity is contained in the gate layer22as described above, energy levels of the electron transit layer16and the electron supply layer18are raised. Therefore, in a region directly below the gate layer22, the energy level of the conduction band of the electron transit layer16near the heterojunction interface between the electron transit layer16and the electron supply layer18is approximately the same as or higher than the Fermi level. Therefore, at the time of zero bias at which no voltage is applied to the gate electrode24, a 2DEG20is not formed in the electron transit layer16in the region directly below the gate layer22. On the other hand, a 2DEG20is formed in the electron transit layer16in regions other than the region directly below the gate layer22.

In this manner, the 2DEG20disappears in the region directly below the gate layer22due to the presence of the gate layer22doped with the acceptor type impurity. As a result, a normally-off operation of the transistor is realized. When an appropriate on-voltage is applied to the gate electrode24, a channel is formed by the 2DEG20in the electron transit layer16in the region directly below the gate electrode24, such that a source and a drain are electrically connected.

The gate electrode24includes one or more metal layers. The gate electrode24is, for example, a titanium nitride (TiN) layer. Alternatively, the gate electrode24may include a first metal layer made of a material containing Ti, and a second metal layer stacked on the first metal layer and made of a material containing TiN. The gate electrode24may form a Schottky junction with the gate layer22. The gate electrode24may be formed in a region smaller than the gate layer22in a plan view. A thickness of the gate electrode24is, for example, 50 nm or more and 200 nm or less.

The passivation layer26is formed over the electron supply layer18. It may be said that the passivation layer26covers the upper surface18A of the electron supply layer18. The passivation layer26may be made of, for example, a material containing any one of silicon nitride (SiN), silicon dioxide (SiO2), silicon oxynitride (SiON), alumina (Al2O3), AlN, and aluminum oxynitride (AlON). In one example, the passivation layer26is made of a material containing SiN. A portion of the passivation layer26that covers the gate layer22and the gate electrode24is formed along the upper surfaces of the gate layer22and the gate electrode24, and therefore has a non-flat upper surface. The passivation layer26has a thickness of, for example, 200 nm or less. Herein, the thickness of the passivation layer26may be, for example, the thickness of a portion in contact with the electron supply layer18or the thickness of a portion in contact with an upper surface of the gate electrode24.

The source electrode28and the drain electrode30are arranged over the upper surface18A of the electron supply layer18with the gate layer22located therebetween. On the upper surface18A of the electron supply layer18, the gate layer22, the source electrode28, and the drain electrode30are aligned in the X-axis direction.

The source electrode28and the drain electrode30may include one or more metal layers. For example, the source electrode28and the drain electrode30may include a combination of two or more metal layers selected from the group of a Ti layer, a TiN layer, an Al layer, an AlSiCu layer, and an AlCu layer. At least a portion of the source electrode28is filled in the first opening26A and is in ohmic contact with the 2DEG20directly below the electron supply layer18via the first opening26A. Similarly, at least a portion of the drain electrode30is filled in the second opening26B and is in ohmic contact with the 2DEG20directly below the electron supply layer18via the second opening26B.

As described above, the source electrode28is electrically connected to the source pad71via the wiring (not shown) formed in the insulator layer60. The drain electrode30is electrically connected to the drain pad72via the wiring (not shown) formed in the insulator layer60. The gate electrode24is electrically connected to the gate pad73via the wiring (not shown) formed in the insulator layer60. Further, the insulator layer60is formed over the passivation layer26, the source electrode28, and the drain electrode30. It may also be said that the insulator layer60covers the passivation layer26, the source electrode28, and the drain electrode30.

(Plan-View Structure of Transistor)

Next, a plan-view structure of the transistor51will be described with reference toFIG.3. InFIG.3, the illustration of the passivation layer26and the source electrode28is omitted, and the first opening26A and the second opening26B of the passivation layer26are depicted by broken lines.

The transistor51includes, within the active region, first active regions that contribute to the transistor operation and second active regions (not shown) that do not contribute to the transistor operation. In one example, the first active regions and the second active regions are alternately disposed in the Y-axis direction.

In the first active region of the transistor51, the source electrode28(seeFIG.4), the gate electrode24, and the drain electrode30are disposed adjacent to each other in the X-axis direction on the electron supply layer18(seeFIG.4). A combination of the source electrode28, the gate electrode24, and the drain electrode30, which are adjacent to each other in the X-axis direction, constitutes one HEMT cell51HC. In the example ofFIG.3, two HEMT cells51HC are disposed in the X direction in the active region. In reality, more HEMT cells51HC may be arranged in each active region. The number of HEMT cells51HC is not particularly limited, and may be one or more. The chip101may include a plurality of transistors51(HEMT cells51HC) formed on a same substrate.

[Details of Thickness of Each Part of Semiconductor Module]

The thickness of each part of the semiconductor module100will be described with reference toFIGS.2and4.

As shown inFIG.2, a thickness T1of the semiconductor module100is, for example, 900 μm or more. The thickness T1of the semiconductor module100is, for example, 1,500 μm or less. A thickness T2of the chip101is, for example, 80 μm or more. The thickness T2of the chip101is, for example, 140 μm or less.

A distance from an upper surface of the nitride semiconductor layer50(the upper surface18A of the electron supply layer18) to the module upper surface100sis defined as a thickness T3. The thickness T3is, for example, 400 μm or more. The thickness T3is, for example, 550 μm or less.

As shown inFIG.4, a thickness T4of the semiconductor substrate12of the chip101is 100 μm or less. The thickness T4of the semiconductor substrate12may be 80 μm or less. Further, the thickness T4of the semiconductor substrate12is, for example, 60 μm or more.

An example of the thickness T4of the semiconductor substrate12is thinner than the thickness T3, which is the distance from the upper surface of the nitride semiconductor layer50(the upper surface18A of the electron supply layer18) to the module upper surface100s.A ratio (T4/T3) of the thickness T4of the semiconductor substrate12to the thickness T3is, for example, 0.25 or less. Further, a difference (T3−T4) between the thickness T3and the thickness T4of the semiconductor substrate12is, for example, 480 μm or more.

As shown inFIG.4, a thickness T5of the electron transit layer16constituting the nitride semiconductor layer50is, for example, 1.2 μm or more. The thickness T5of the electron transit layer16is, for example, 6 μm or less. In an example of the nitride semiconductor layer50, the electron transit layer16is formed over the semiconductor substrate12made of n-type GaN, and an intermediate layer such as a buffer layer or the like is not interposed between the semiconductor substrate12and the electron transit layer16. In this case, insulation between the 2DEG20generated in the electron transit layer16and the semiconductor substrate12may be secured by forming the electron transit layer16thickly, for example, by setting the thickness T5to be 1,200 μm or more. As a result, it is possible to suppress a leakage current from flowing through the electron transit layer16to the semiconductor substrate12.

A combined thickness of the semiconductor substrate12and the nitride semiconductor layer50, i.e., a distance D1from the substrate lower surface12rof the semiconductor substrate12to the upper surface18A of the electron supply layer18, is, for example, 106 μm or less. Further, the distance D1is, for example, 61 μm or more.

As shown inFIG.2, a thickness T6of the heat dissipation member103is, for example, 150 μm or less. The thickness of the heat dissipation member103is, for example, 100 μm or more. By reducing the thickness T6of the heat dissipation member103to, for example, 150 μm or less, it is possible to improve the heat dissipation performance of the heat dissipation member103. The thickness T6of the heat dissipation member103in one example is thicker than the thickness T4of the semiconductor substrate12. Further, the thickness T6of the heat dissipation member103in another example is thinner than the thickness T4of the semiconductor substrate12.

In a thickness direction of the semiconductor module100, the chip lower surface101rof the chip101is located closer to the module lower surface100rthan the module upper surface100sof the semiconductor module100. In other words, a distance D2between the chip lower surface101rand the module lower surface100ris shorter than a distance D3between the chip lower surface101rand the module upper surface100s.

Next, the operation of the semiconductor module100of the embodiment will be described. The semiconductor module100includes the chip101including the transistor51. The chip101includes the semiconductor substrate12having the substrate upper surface12sand the substrate lower surface12r,and the electron transit layer16and the electron supply layer18, which are formed over the substrate upper surface12sand made of GaN. The transistor51includes the electron transit layer16and the electron supply layer18, and includes the gate electrode24, the source electrode28, and the drain electrode30, which are formed over the electron supply layer18.

In the case of the chip101having the above configuration, heat generated from the transistor51is dissipated externally via the semiconductor substrate12. Specifically, the semiconductor module100includes the heat dissipation member103that is bonded to the substrate lower surface12rof the semiconductor substrate12and exposed at the module lower surface100r.The heat generated from the transistor51is dissipated externally from the module lower surface100rof the semiconductor module100via the semiconductor substrate12and the heat dissipation member103. Therefore, the semiconductor module100may be said to be a single-side heat dissipation type module.

Herein, the chip101uses, as the semiconductor substrate12, a GaN substrate, i.e., a substrate made of a same material as the electron transit layer16and the electron supply layer18formed over the semiconductor substrate12. Thus, the thickness of the semiconductor substrate12may be made thinner than that of the conventional structure using other substrates. Specifically, the thickness of the semiconductor substrate12may be reduced to 100 μm or less.

Specifically, when a material constituting the semiconductor substrate12and a material constituting the electron transit layer16and electron supply layer18formed thereon are different materials, the difference in linear expansion coefficients of the two materials generates a stress that tends to warp the chip101. As a result, the semiconductor substrate needs to have a thickness that is able to retain a strength to withstand the above stress. For example, when using a Si substrate, a thickness of the Si substrate needs to be 200 μm or more.

On the other hand, when the material constituting the semiconductor substrate12and the material constituting the electron transit layer16formed thereon are both the same type of material (GaN-based material), the difference in linear expansion coefficients of the two materials becomes small or disappears. Therefore, the stress that tends to warp the chip101due to the difference in the linear expansion coefficients becomes smaller or no longer occurs. This makes it possible to reduce the strength required for the semiconductor substrate12. As a result, it becomes possible to use a semiconductor substrate12with relatively low strength, i.e., a semiconductor substrate12with a thickness of 100 μm or less.

By using the thin semiconductor substrate12with a thickness of 100 μm or less, thermal resistance when heat flows in the thickness direction of the semiconductor substrate12may be reduced. As a result, in the chip101, thermal resistance when the heat generated from the transistor51is dissipated externally via the semiconductor substrate12is reduced. Thus, heat dissipation of the semiconductor module100is improved.

Further, the thermal conductivity of Si used in the conventional semiconductor substrate is 1.5 W/cm·K. On the other hand, the thermal conductivity of GaN is 2 W/cm·K, which is higher than that of Si. Therefore, as compared to a case when a Si substrate is used, when a GaN substrate is used, the effect of improving heat dissipation may be obtained due to the higher thermal conductivity of the material constituting the semiconductor substrate12.

For reference, thermal resistance of the chip101using a GaN substrate as the semiconductor substrate12and thermal resistance of the chip101using a Si substrate as the semiconductor substrate12are compared by simulation. The thermal resistance is determined by determining thermal resistance between a specific first point on the upper surface18A of the electron supply layer18and a specific second point on the substrate lower surface12rof the semiconductor substrate12. First, a first model of a semiconductor module including a chip101using a Si substrate with a thickness of 200 μm and having an area of 10 mm2in a plan view is prepared, and the thermal resistance thereof is calculated. Next, a second model having the same configuration as the first model except that a GaN substrate with a thickness of 80 μm is used is prepared, and the thermal resistance thereof is calculated. As a result, the thermal resistance of the first model using the Si substrate is calculated to be 0.13 degrees C./W. On the other hand, the thermal resistance of the second model using the GaN substrate is calculated to be 0.04 degrees C./W, which was equal to or less than ⅓ of the thermal resistance of the first model.

According to the semiconductor module100of the first embodiment, the following effects are obtained.(1-1)

The semiconductor module100includes the chip101including the transistor51. The chip101includes the semiconductor substrate12, the electron transit layer16formed over the semiconductor substrate12and made of GaN, and the electron supply layer18formed over the electron transit layer16and made of GaN. The transistor51includes the gate electrode24, the source electrode28, and the drain electrode30, which are formed over the electron supply layer18. The semiconductor substrate12is a GaN substrate having a thickness of 100 μm or less.

According to the above configuration, by using the GaN substrate as the semiconductor substrate12, the thickness of the semiconductor substrate12may be set to 100 μm or less. This reduces the thermal resistance when the heat generated from the transistor51is dissipated externally via the semiconductor substrate12. As a result, the heat dissipation of the semiconductor module100is improved. By improving the heat dissipation of the semiconductor module100, an amount of heat generated by the chip101is reduced. This makes it possible to increase an upper limit of the drain current (allowable current) that flows through the transistor51.(1-2)

Further, when the semiconductor substrate12is the GaN substrate, the electron transit layer16and the electron supply layer18, which are GaN layers, may be formed over the semiconductor substrate12by epitaxial growth without using a buffer layer. For example, the electron supply layer18is formed in contact with the substrate upper surface12sof the semiconductor substrate12.

In this case, by omitting a buffer layer, it is possible to shorten a distance from the upper surface18A of the electron supply layer18to the semiconductor substrate12. This makes it possible to shorten a heat dissipation path through which the heat generated from the transistor51is dissipated externally via the electron transit layer16and the semiconductor substrate12. In this respect as well, the thermal resistance when the heat generated from the transistor51is dissipated externally through the heat dissipation path is reduced. As a result, the heat dissipation of the semiconductor module100is further improved.

Further, when the electron transit layer16is disposed over the semiconductor substrate12made of n-type GaN without using a buffer layer, the electron transit layer16made of undoped GaN may be formed thick to ensure insulation between the 2DEG20and the semiconductor substrate12. In this case as well, a decrease in the thickness of the electron transit layer16due to the omission of the buffer layer is greater than an increase in the thickness of the electron transit layer16. Therefore, the distance from the upper surface18A of the electron supply layer18to the semiconductor substrate12may be made shorter than that of the configuration having a buffer layer.(1-3)

The chip101includes the plurality of transistors51(HEMT cells51HC). Each of the transistors51is a horizontal transistor in which the gate electrode24, the source electrode28, and the drain electrode30are formed over the electron supply layer18. The chip101may be miniaturized by arranging the plurality of transistors51, which are horizontal transistors, in a dense manner. However, the amount of heat generated by the chip101tends to increase as the heat generated from each of the adjacent transistors51interferes with each other. Therefore, it is particularly effective to use a GaN substrate having a thickness of 100 μm or less for the chip101including the plurality of transistors51.(1-4)

The semiconductor module100includes the sealing member104that covers the chip101. The semiconductor module100includes the module upper surface100sfacing a same side as the substrate upper surface12s,and the module lower surface100rfacing a same side as the substrate lower surface12r.The thickness T4of the semiconductor substrate12is thinner than the thickness T3, which is the distance from the upper surface18A of the electron supply layer18to the module upper surface100s.In this case, since the thickness T4of the semiconductor substrate12is thin, the thermal resistance when the heat generated from the transistor51, especially near the electron supply layer18, is dissipated externally via the semiconductor substrate12, is further reduced.(1-5)

In the thickness direction of the semiconductor substrate12, the chip lower surface101rof the chip101is located closer to the module lower surface100rthan the module upper surface100sof the semiconductor module100. In this case, it is possible to shorten the one-sided heat dissipation path through which the heat generated from the transistor51is dissipated from the module lower surface100rvia the semiconductor substrate12. Thus, the thermal resistance when the heat generated from the transistor51is dissipated externally via the semiconductor substrate12is further reduced.(1-6)

The transistor51is formed over the electron supply layer18and includes the gate layer22made of GaN containing an acceptor type impurity. The gate electrode24is formed over the gate layer22. That is, the transistor51is of a normally-off type. In this case, at a zero bias at which no voltage is applied to the gate electrode24, no 2DEG20is formed in the region directly below the gate layer22in the electron transit layer16. On the other hand, a 2DEG20is formed in the electron transit layer16in the regions other than the region directly below the gate layer22. When an on-voltage is applied to the gate electrode24, a channel is formed by the 2DEG20in the electron transit layer16in the region directly below the gate electrode24.

Herein, when the on-voltage is applied to the gate electrode24, the 2DEG20generated in the region directly below the gate layer22in the electron transit layer16is less than the 2DEG20generated in the regions other than the region directly below the gate layer22in the electron transit layer16. Therefore, the region directly below the gate layer22in the electron transit layer16has a higher resistance than the regions other than the region directly below the gate layer22in the electron transit layer16, resulting in an increase in an amount of heat generated. Therefore, when the transistor51included in the chip101is a normally-off type transistor having the gate layer22, the amount of heat generated by the chip101tends to become larger than when the transistor51is a normally-on type transistor having no gate layer22. Thus, it is particularly effective to use a GaN substrate having a thickness of 100 μm or less for the chip101including the normally-off type transistor51.

Second Embodiment

A semiconductor module200of a second embodiment differs from that of the first embodiment in that it includes a control circuit. The other configurations are the same as those in the first embodiment. Hereinafter, the components similar to those of the first embodiment will not be described, and the components different from those of the first embodiment will be described.

FIG.5is a schematic plan view of an exemplary semiconductor module200according to the second embodiment.

[Schematic Structure of Semiconductor Module]

As shown inFIG.5, the semiconductor module200includes a module upper surface200sand a module lower surface (not shown) facing an opposite side of the module upper surface200s.

The semiconductor module200includes a chip101including a transistor51, a first conductive terminal102A and a second conductive terminal102B electrically connected to the chip101, and a heat dissipation member103. These components are the same as those of the first embodiment.

The semiconductor module200further includes a control chip201including a control circuit, a plurality of fourth conductive terminals102E electrically connected to the control chip201, a control heat dissipation member202, and a sealing member203that seals the chip101and the control chip201.

The fourth conductive terminal102E includes an external connection surface (each lower surface) partially exposed from the sealing member203to the module lower surface. A material forming the fourth conductive terminal102E may be the same as a material forming the first conductive terminal102A.

The control chip201includes a chip upper surface201sfacing a same side as the module upper surface200s.The control chip201includes a first electrode pad81and a plurality of second electrode pads82formed over the chip upper surface201s.The first electrode pad81is connected to an upper surface of the gate pad73of the chip101via a wire81A. The plurality of second electrode pads82are respectively connected to different fourth conductive terminals102E via wires82A. Materials forming the first electrode pad81and the second electrode pads82may be the same as a material forming the electrode pad70. Materials forming the wires81A and82A may be the same as a material forming the wire102D.

The control heat dissipation member202is installed at a chip lower surface of the control chip201. The method of installing the control heat dissipation member202at the chip lower surface is not particularly limited. The method for installing the control heat dissipation member202may be the same as the method described above for the heat dissipation member103. The control heat dissipation member202includes an exposed surface (not shown) that is partially exposed from the sealing member203to the module lower surface. A material forming the control heat dissipation member202may be the same as a material forming the heat dissipation member103.

The sealing member203may define a package contour of the semiconductor module200. The sealing member203seals a portion of the first conductive terminal102A, a portion of the second conductive terminal102B, a portion of the fourth conductive terminals102E, a portion of the heat dissipation member103, and a portion of the control heat dissipation member202, along with the chip101and the control chip201. A material forming the sealing member203may be the same as a material forming the sealing member104.

The control circuit of the control chip201generates a drive signal that drives the transistor51. The drive signal is applied to the gate electrode24of the transistor51. The control circuit turns the transistor51on and off.

The semiconductor module200of the second embodiment has the same effects as the semiconductor module100of the first embodiment.

Third Embodiment

A semiconductor module300of a third embodiment differs from that of the second embodiment in that it is embodied as a bridge module having a bridge circuit. In the present embodiment, as an example, a semiconductor module300embodied as a half-bridge module having a half-bridge circuit will be described.

[Circuit Configuration of Semiconductor Module]

FIG.6is a schematic circuit diagram of the semiconductor module300. The semiconductor module300includes a half-bridge circuit301and a control circuit C. The half-bridge circuit301includes a first transistor302and a second transistor303. The control circuit C controls the driving of the first transistor302and the second transistor303.

The first transistor302and the second transistor303are connected in series with each other. The first transistor302functions as a high-side transistor (control transistor) of the half-bridge circuit301, and the second transistor303functions as a low-side transistor (synchronous rectification transistor) of the half-bridge circuit301.

The first transistor302provided as the high-side transistor includes a source terminal302S, a drain terminal302D, and a gate terminal302G. The drain terminal302D is connected to an input terminal T10, and the source terminal302S is connected to an output terminal T20. An input voltage VINis applied to the input terminal T10.

The second transistor303provided as the low-side transistor includes a source terminal303S, a drain terminal303D, and a gate terminal303G. The drain terminal303D is connected to the output terminal T20, and the source terminal303S is connected to a ground GND. Therefore, the first transistor302and the second transistor303are connected in series between the input terminal T10and the ground GND, and a connection node between the first transistor302and the second transistor303is connected to the output terminal T20.

The control circuit C includes a high-side driver310and a low-side driver320. The high-side driver310generates a high-side control signal VGHthat drives the first transistor302. The high-side control signal VGHis applied to the gate terminal302G of the first transistor302. The low-side driver320generates a low-side control signal VGLthat drives the second transistor303. The low-side control signal VGLis applied to the gate terminal303G of the second transistor303.

The control circuit C generates a switch voltage VSWat the output terminal T20by performing complementary on/off control of the first transistor302and the second transistor303based on the high-side control signal VGHand the low-side control signal VGL. A load circuit (not shown) including, for example, a coil and an inductor is connected to the output terminal T20.

When the first transistor302is turned on and the second transistor303is turned off, a switch current ISWflows from the input terminal T10to the load circuit (output terminal T20) via the first transistor302, and a switch voltage VSWbased on the input voltage VINis outputted to the output terminal T20. When the first transistor302is turned off and the second transistor303is turned on, the switch current ISWflows from the load circuit (output terminal T20) to the ground GND via the second transistor303, and the switch voltage VSWis lowered to 0 V.

[Schematic Structure of Semiconductor Module]

As shown inFIG.7, the semiconductor module300includes a module upper surface300sand a module lower surface (not shown) facing an opposite side of the module upper surface300s.

The semiconductor module300includes a chip331including the first transistor302and the second transistor303, a fifth conductive terminal332A, a sixth conductive terminal332B and a seventh conductive terminal332C, which are electrically connected to the chip331, and a heat dissipation member335bonded to the chip331. The semiconductor module300further includes a control chip333including a control circuit C, a plurality of eighth conductive terminals332D electrically connected to the control chip333, a control heat dissipation member202, and a sealing member337that seals the chip331and the control chip333. For ease of understanding, only the contour of the sealing member337is shown inFIG.7.

The chip331includes a chip upper surface331sfacing a same side as the module upper surface300s.A shape of the chip331in a plan view, i.e., a shape of the chip upper surface331sin a plan view, is, for example, rectangular. The chip331includes a semiconductor substrate12, a nitride semiconductor layer50(seeFIG.8), a first transistor302(seeFIG.8), a second transistor303(seeFIG.8), an insulator layer60(not shown), an electrode pad370, and a lower surface electrode80. The semiconductor substrate12, the lower surface electrode80(seeFIG.8), and the insulator layer60are the same as those in the first embodiment. Details of the nitride semiconductor layer50will be described later.

The electrode pad370is formed over the chip upper surface331s.The electrode pad370includes one or more source pads371H, one or more drain pads372H, and one or more gate pads373H. The source pad371H is electrically connected to a source electrode28H of the first transistor302, which will be described later. The drain pad372H is electrically connected to a drain electrode30H of the first transistor302, which will be described later. The gate pad373H is electrically connected to a gate electrode24H of the first transistor302, which will be described later.

Further, the electrode pad370includes one or more source pads371L, one or more drain pads372L, and one or more gate pads373L. The source pad371L is electrically connected to a source electrode28L of the second transistor303, which will be described later. The drain pad372L is electrically connected to a drain electrode30L of the second transistor303, which will be described later. The gate pad373L is electrically connected to a gate electrode24L of the second transistor303, which will be described later. A material forming the electrode pad370is the same as a material forming the electrode pad70of the first embodiment.

In the example shown inFIG.7, the chip331includes a plurality of source pads371H, a plurality of drain pads372H, a gate pad373H, a plurality of source pads371L, a plurality of drain pads372L, and a gate pad373L.

The plurality of source pads371H and the plurality of drain pads372H are each formed in a rectangular shape extending in the Y-axis direction, and are arranged alternately in the X-axis direction in a region along a +Y-axis direction of the chip upper surface331s.The gate pad373H is arranged closer to an outer periphery of the chip upper surface331sthan the plurality of source pads371H and the plurality of drain pads372H. More specifically, the gate pad373H is arranged at an interval in the +Y-axis direction from a pad (source pad371H inFIG.7) arranged at an end in a −X-axis direction.

The plurality of source pads371L and the plurality of drain pads372L are each formed in a rectangular shape extending in the Y-axis direction, and are arranged alternately at intervals in the X-axis direction in a region along a −Y-axis direction of the chip upper surface331s.Further, the source pads371L are arranged at intervals toward the −Y-axis direction of the drain pad372H. The drain pads372L are arranged at intervals toward the −Y-axis direction of the source pad371H. The gate pad373L is arranged closer to the outer periphery of the chip upper surface331sthan the plurality of source pads371L and the plurality of drain pads372L. Specifically, the gate pad373L is arranged at an interval in the −Y-axis direction from a pad (drain pad372L inFIG.7) arranged at the end in the −X-axis direction.

The fifth conductive terminal332A, the sixth conductive terminal332B, and the seventh conductive terminal332C are electrically connected to the electrode pad370of the chip331. Specifically, the fifth conductive terminal332A is bonded to an upper surface of the drain pad372H via a conductive bonding material (not shown). The sixth conductive terminal332B is bonded to an upper surface of the source pad371L via a conductive bonding material (not shown). The seventh conductive terminal332C is bonded to both an upper surface of the source pad371H and an upper surface of the drain pad372L via a conductive bonding material (not shown).

Each of the fifth conductive terminal332A, the sixth conductive terminal332B, and the seventh conductive terminal332C has a bridge shape, for example. Each of the fifth conductive terminal332A, the sixth conductive terminal332B, and the seventh conductive terminal332C includes an external connection surface (lower surface of each terminal) that is partially exposed from the sealing member337to the module lower surface. The external connection surface of the fifth conductive terminal332A corresponds to the input terminal T10inFIG.6. The external connection surface of the sixth conductive terminal332B corresponds to the ground GND inFIG.6. The external connection surface of the seventh conductive terminal332C corresponds to the output terminal T20inFIG.6.

The control chip333includes a chip upper surface333sfacing a same side as the module upper surface300s.A shape of the control chip333in a plan view, i.e., a shape of the chip upper surface333sin a plan view, is, for example, rectangular.

The control chip333includes a third electrode pad335A, a fourth electrode pad335B, and a plurality of fifth electrode pads335C, which are formed over the chip upper surface333s.The third electrode pad335A is connected to an upper surface of the gate pad373H of the chip331via a wire336A. The fourth electrode pad335B is connected to an upper surface of the gate pad373L of the chip331via a wire336B. The fifth electrode pads335C are respectively connected to a plurality of different eighth conductive terminals332D via wires336C. Each of the plurality of eighth conductive terminals332D has an external connection surface (lower surface of each terminal) partially exposed from the sealing member337to the module lower surface.

(Schematic Structure of First Transistor and Second Transistor)

FIG.8is a schematic cross-sectional view of the first transistor302and the second transistor303. The first transistor302and the second transistor303include a common semiconductor substrate12and a common nitride semiconductor layer50formed over the semiconductor substrate12. The nitride semiconductor layer50is epitaxially grown over the substrate upper surface12sof the semiconductor substrate12. The nitride semiconductor layer50includes an electron transit layer16formed over the semiconductor substrate12and an electron supply layer18formed over the electron transit layer16. The semiconductor substrate12and the nitride semiconductor layer50are the same as those of the first embodiment.

The first transistor302includes a gate layer22H formed over the electron supply layer18and a gate electrode24H formed over the gate layer22H. The second transistor303includes a gate layer22L formed over the electron supply layer18and a gate electrode24L formed over the gate layer22L.

The first transistor302and the second transistor303include a passivation layer26. The passivation layer26is formed over the electron supply layer18, the gate layers22H and22L, and the gate electrodes24H and24L, and includes first openings26AH and26AL and second openings26BH and26BL.

The first openings26AH and26AL and the second openings26BH and26BL are arranged at intervals in the order of the first opening26AL, the second opening26BL, the first opening26AH, and the second opening26BH toward a +X direction. In one example, in the X direction, a distance between the first opening26AL and the second opening26BL is equal to a distance between the first opening26AH and the second opening26BH. A distance between the second opening26BL and the first opening26AH is shorter than the distance between the first opening26AL and the second opening26BL and the distance between the first opening26AH and the second opening26BH.

The first transistor302includes the source electrode28H in contact with the upper surface18A of the electron supply layer18via the first opening26AH, and the drain electrode30H in contact with the upper surface18A of the electron supply layer18via the second opening26BH. The gate layer22H of the first transistor302is located between the first opening26AH and the second opening26BH of the passivation layer26, and is spaced apart from each of the first opening26AH and the second opening26BH. The source electrode28H and the drain electrode30H are disposed over the upper surface18A of the electron supply layer18with the gate layer22H located therebetween. On the upper surface18A of the electron supply layer18, the gate layer22H, the source electrode28H, and the drain electrode30H are arranged in the X-axis direction. The details of the configuration of the first transistor302are the same as those of the transistor51of the first embodiment. The source electrode28H is electrically connected to the source pad371H. The drain electrode30H is electrically connected to the drain pad372H. The gate electrode24H is electrically connected to the gate pad373H.

The second transistor303includes the source electrode28L in contact with the upper surface18A of the electron supply layer18via the first opening26AL, and the drain electrode30L in contact with the upper surface18A of the electron supply layer18via the second opening26BL. The gate layer22L of the second transistor303is located between the first opening26AL and the second opening26BL of the passivation layer26, and is spaced apart from each of the first opening26AL and the second opening26BL. The source electrode28L and the drain electrode30L are disposed over the upper surface18A of the electron supply layer18with the gate layer22L located therebetween. On the upper surface18A of the electron supply layer18, the gate layer22L, the source electrode28L, and the drain electrode30L are arranged in the X-axis direction. The source electrode28L is electrically connected to the source pad371L. The drain electrode30L is electrically connected to the drain pad372L. The gate electrode24L is electrically connected to the gate pad373L.

The semiconductor module300of the third embodiment has the same effects as the semiconductor module100of the first embodiment. Further, according to the semiconductor module300of the third embodiment, the following effects may be obtained.

The chip331includes the bridge circuit configured by the plurality of transistors (first transistor302and second transistor303). An example of the bridge circuit is the half-bridge circuit301including the first transistor302(high-side transistor) and the second transistor303(low-side transistor) connected in series. The semiconductor module300includes the control circuit C that controls on/off of the plurality of transistors (first transistor302and second transistor303).

In the case of the bridge circuit, the plurality of transistors are disposed close to each other in order to operate at a high frequency and to reduce the size of the chip331. Therefore, an amount of heat generated by the chip331tends to increase as heat generated from the adjacent transistors interferes with each other. Therefore, it is particularly effective to use a GaN substrate having a thickness of 100 μm or less for the chip101including the bridge circuit.

Modification

Each of the above-described embodiments may be modified as follows, for example. The above-described embodiments and the following modifications may be combined with each other as long as there is no technical contradiction. In addition, in the following modifications, parts common to the above-described embodiments are designated by the same reference numerals as in each of the above-described embodiments, and the description thereof will be omitted.

The transistor51may be of a normally-on type that does not have the gate layer22. The same applies to the first transistor302and the second transistor303.

As used herein, the term “over” includes the meanings of both “on” and “above” unless the context clearly indicates otherwise. Thus, the phrase “a first layer is formed over a second layer” refers to a case where the first layer is directly disposed on the second layer in contact with the second layer in a certain embodiment and a case where the first layer is arranged above the second layer without contacting the second layer in another embodiment. That is, the term “over” does not exclude a structure in which another layer is formed between the first layer and the second layer.

The term Z direction used herein does not necessarily have to be the vertical direction, nor does it have to completely coincide with the vertical direction. Therefore, various structures according to the present disclosure are not limited to structures in which the “up” and “down” in the Z direction described herein are “up” and “down” in the vertical direction. For example, the X-axis direction may be a vertical direction, or the Y-axis direction may be a vertical direction.

The terms such as “first,” “second,” and “third” in the present disclosure are used merely to distinguish between objects, and are not intended to rank the objects.

The technical ideas that may be understood from the present disclosure are described below. Not for the purpose of limitation but for the purpose of aiding understanding, the reference numerals of the corresponding components in the embodiments are attached to the components recited in the supplementary notes. The reference numerals are indicated by way of example to aid understanding, and the components recited in each supplementary note should not be limited to the components indicated by the reference numerals.

[Supplementary Note 1] A nitride semiconductor module (100,200or300), including:a chip (101or331) including at least one transistor (51,302or303),wherein the chip (101or331) includes:a semiconductor substrate (12) including a substrate upper surface (12s) and a substrate lower surface (12r) facing an opposite side of the substrate upper surface (12s);an electron transit layer (16) formed over the substrate upper surface (12s) of the semiconductor substrate (12) and made of GaN; andan electron supply layer (18) formed over the electron transit layer (16) and made of GaN having a larger band gap than the electron transit layer (16),wherein the at least one transistor (51,302or303) includes a gate electrode (24), a source electrode (28), and a drain electrode (30), which are formed over the electron supply layer (18), andwherein the semiconductor substrate (12) is a GaN substrate having a thickness of 100 μm or less.

[Supplementary Note 2] The nitride semiconductor module of Supplementary Note 1, wherein the at least one transistor (51,302or303) includes a plurality of transistors (51,302and303), andwherein the chip (101or331) includes the plurality of transistors (51,302and303).

[Supplementary Note 3] The nitride semiconductor module of Supplementary Note 1 or 2, further including:a sealing member (26or203) configured to cover the chip (101or331),wherein the nitride semiconductor module includes a module upper surface (100s,200sor300s) formed of the sealing member (26or203) and facing a same side as the substrate upper surface (12s), and a module lower surface (100r,200ror300r) formed of the sealing member (26or203) and facing a same side as the substrate lower surface (12r), andwherein a thickness (T4) of the semiconductor substrate (12) is thinner than a distance (T3) from an upper surface (18A) of the electron supply layer (18) to the module upper surface (100s,200sor300s).

[Supplementary Note 4] The nitride semiconductor module (100,200or300) of any one of Supplementary Notes 1 to 3, further including:a sealing member (26or203) configured to cover the chip (101or331),wherein the nitride semiconductor module includes a module upper surface (100s,200sor300s) formed of the sealing member (26or203) and facing a same side as the substrate upper surface (12s), and a module lower surface (100r,200ror300r) formed of the sealing member (26or203) and facing a same side as the substrate lower surface (12r), andwherein a chip lower surface (101ror331r) of the chip (101or331) is located closer to the module lower surface (100r,200ror300r) than the module upper surface (100s,200sor300s) in a thickness direction of the semiconductor substrate (12).

[Supplementary Note 5] The nitride semiconductor module (100,200or300) of any one of Supplementary Notes 1 to 4, further including:a sealing member (26or203) configured to cover the chip (101or331),wherein the nitride semiconductor module includes a module upper surface (100s,200sor300s) formed of the sealing member (26or203) and facing a same side as the substrate upper surface (12s), and a module lower surface (100r,200ror300r) formed of the sealing member (26or203) and facing a same side as the substrate lower surface (12r), andwherein the nitride semiconductor module further includes a heat dissipation member (103) installed at the substrate lower surface (12r) and exposed to the module lower surface (100r,200ror300r).

[Supplementary Note 6] The nitride semiconductor module (100,200or300) of Supplementary Note 5, wherein the heat dissipation member (103) has a thickness of 150 μm or less.

[Supplementary Note 7] The nitride semiconductor module of any one of Supplementary Notes 1 to 6, wherein the electron transit layer (16) is a GaN layer, andwherein the electron supply layer (18) is an AlGaN layer.

[Supplementary Note 8] The nitride semiconductor module (100,200or300) of any one of Supplementary Notes 1 to 7, wherein the at least one transistor (51,302or303) includes a gate layer (22) formed over the electron supply layer (18) and made of GaN containing an acceptor type impurity, andwherein the gate electrode (24) is formed over the gate layer (22).

[Supplementary Note 9] The nitride semiconductor module (100,200or300) of Supplementary Note8, wherein the electron transit layer (16) is a GaN layer,wherein the electron supply layer (18) is an AlGaN layer, andwherein the gate layer (22) is a GaN layer containing the acceptor type impurity.

[Supplementary Note 10] The nitride semiconductor module (200or300) of any one of Supplementary Notes 1 to 9, further including:a control circuit (C1or C2) configured to control an on/off operation of the at least one transistor (51,302or303).

[Supplementary Note 11] The nitride semiconductor module (300) of any one of Supplementary Notes 1 to 9, wherein the at least one transistor (51,302or303) includes a plurality of transistors (51,302and303), andwherein the chip (101or331) includes the plurality of transistors (51,302and303), andwherein the nitride semiconductor module (300) further includes a bridge circuit (301) configured by using the plurality of transistors (302and303).

[Supplementary Note 12] The nitride semiconductor module (300) of Supplementary Note 11, wherein the plurality of transistors (302and303) constitutes a half-bridge circuit (301) including a high-side transistor (302) and a low-side transistor (303) connected in series with each other, andwherein the nitride semiconductor module (300) further includes a control circuit (C2) configured to control on/off operations of the high-side transistor (302) and the low-side transistor (303).

[Supplementary Note 13] A chip including:a nitride semiconductor layer (50) formed over a semiconductor substrate (12); anda plurality of transistors (302and303) including the nitride semiconductor layer (50),wherein the plurality of transistors (302and303) constitutes a half-bridge circuit (301) including a high-side transistor (302) and a low-side transistor (303) connected in series with each other,wherein the chip further includes: one or more source pads (371H) formed over a chip upper surface (101s) orthogonal to a thickness direction of the semiconductor substrate (12) and electrically connected to a source electrode (28H) of the high-side transistor (302); one or more drain pads (372H) formed over the chip upper surface (101s) and electrically connected to a drain electrode (30H) of the high-side transistor (302); one or more gate pads (373H) formed over the chip upper surface (101s) and electrically connected to a gate electrode (24H) of the high-side transistor (302); a plurality of source pads (371L) formed over the chip upper surface (101s) and electrically connected to a source electrode (28L) of the low-side transistor (303); a plurality of drain pads (372L) formed over the chip upper surface (101s) and electrically connected to a drain electrode (30L) of the low-side transistor (303); and a gate pad (373L) formed over the chip upper surface (101s) and electrically connected to a gate electrode (24L) of the low-side transistor (303),wherein the plurality of source pads (371H) and the plurality of drain pads (372H) are each disposed in a region on one side (toward a +Y-axis direction) of a first direction on the chip upper surface (101s) so as to be arranged alternately in a second direction (X-axis direction) orthogonal to the first direction on the chip upper surface (101s),wherein the plurality of source pads (371L) and the plurality of drain pads (372L) are each disposed in a region on the other side (toward a −Y-axis direction) of the first direction on the chip upper surface (101s) so as to be arranged alternately in the second direction (X-axis direction) on the chip upper surface (101s),wherein the plurality of source pads (371L) are disposed so as to be arranged at intervals on the other side (toward the −Y-axis direction) of the first direction on the drain pad (372H), andwherein the plurality of drain pads (372L) are disposed so as to be arranged at intervals on the other side (toward the −Y-axis direction) of the first direction on the source pad (371H).

[Supplementary Note 14] The chip of Supplementary Note 13, wherein the gate pad (373H) is arranged closer to an outer periphery than the plurality of source pads (371H) and the plurality of drain pads (372H), andwherein the gate pad (373L) is arranged closer to the outer periphery than the plurality of source pads (371L) and the plurality of drain pads (372L).

A thickness of the semiconductor substrate (12) included in the chip recited in Supplementary Notes 13 and 14 and the material forming the semiconductor substrate (12) are not particularly limited.

According to the nitride semiconductor module of the present disclosure, it is possible to enhance heat dissipation.