Method of fabricating self-aligned FET structure having a high temperature stable T-shaped Schottky gate contact

A method of fabricating a self-aligned FET having a semi-insulating substrate of GaAs or InP with a conductive channel formed either by doping the surface or an epitaxially grown channel by molecular beam epitaxy or metalorganic vapor phase epitaxy in the substrate adjacent the surface. Forming a high temperature stable LaB.sub.6 /TiWN "T-shaped" Schottky gate contact on the substrate surface, which is used for source and drain ohmic region implants into the substrate adjacent to the surface and self-aligned to the "T-shaped" gate, with source and drain ohmic contacts also self-aligned with respect to the gate.

FIELD OF THE INVENTION 
The present invention pertains to field effect transistors (FETs) and more 
specifically to self-aligned FET structure. 
BACKGROUND OF THE INVENTION 
Self-aligned GaAs FETs are widely used in high speed integrated circuits to 
minimize the gate-source and gate-drain parasitic resistances. Most 
self-aligned processes use a refractory gate metal (i.e. TiW) as a mask 
for self-aligned implantation of n+ source and drain ohmic regions. 
Refractory metals are used for their high temperature electrical, 
metallurgical stability during the post implant high temperature annealing 
of about 800.degree.-850.degree. C. This self-aligned n+ source and drain 
implant reduces the parasitic source and drain resistances, however in 
order to substantially reduce these parasitic resistances it is necessary 
to reduce the distance between source and drain ohmic contacts by 
developing a manufacturable process that allows for self-aligned 
deposition of source and drain metal contacts. 
It is also important to be table to control the distance between gate metal 
and n+ source and drain implant regions, since they play an important role 
in both speed (through gate-source capacitance Cgs) and power (breakdown 
voltage VBgd) performance of a FET. A prior art patent, U.S. Pat. No. 
4,782,032, issued to Geissberger et al on Nov. 1, 1988, addresses the 
control of n+ source and drain implants to the gate metal by using a 
"mushroom" or "T-shaped" gate process. This process requires the 
deposition of another layer either a dielectric or metal on top of the 
refractory metal and acts as the mask for subsequent etching and 
undercutting (in a controllable fashion) of the underlying refractory 
gate. The etching process is done either by wet chemical etch or dry 
etching. The sacrificial top layer is then removed prior to high 
temperature annealing of the n+ source and drain implants due to lack of 
high temperature stability of the top layer. Removing the top layer 
eliminates the choice of fabricating the ohmic metal contacts in a 
self-aligned manner with respect to the gate metal. 
In another prior art patent, U.S. Pat. No. 4,712,219, issued to McLevige on 
Dec. 15, 1987, a high temperature stable material using a doped silicon 
layer is suggested that requires a complicated process of selectively 
etching and doping of a silicon layer, which is not a manufacturable 
process. There is no prior art that combines the "mushroom" or "T-shaped" 
gate process using a stable top layer for both self-align n+ source and 
drain implant, and ohmic contacts that is easily manufacturable. 
It would be desirable, therefore, to devise a method of fabricating 
self-aligned FETs which is easily manufacturable. 
It is a purpose of the present invention to provide a method of fabricating 
self-aligned FETs with both n+ implants and ohmic metals formed in a 
self-aligned fashion with respect to the gate which is easily 
manufacturable. 
It is a further purpose of the present invention to provide a method of 
fabricating self-aligned FETs with controllable distances between gate 
metal and n+ source and drain implants. 
It is a still further purpose of the present invention to provide a method 
of fabricating self-aligned FETs which eliminates any critical alignment 
of source and drain ohmic contacts. 
It is a still further purpose of the present invention to provide a method 
of fabricating self-aligned FETs with improved speed performance for use 
in digital circuitry. 
It is a still further purpose of the present invention to provide a method 
of fabricating self-aligned FETs which eliminates any critical processing 
steps for reducing gate resistance. 
SUMMARY OF THE INVENTION 
The present invention provides a method of fabricating a self-aligned FET 
on a surface of a semiconductor substrate using LaB6/TiWN as a "T-shape" 
gate structure formed by a controllable dry etching of the TiWN using LaB6 
as the mask which allows control of n+ implant distance to gate edge. The 
high temperature stability of the LaB.sub.6 /TiWN structure allows the 
"T-shaped" gate to be preserved during the high temperature post n+ source 
and drain implant annealing step and subsequently to be used for the 
self-aligned formation of source and drain ohmic contact metals on the 
surface of the substrate and in spaced relationship while simultaneously 
depositing extra low resistance metal over the "T-shaped" gate metal, 
producing low gate resistance without extra complicated processes.

DESCRIPTION OF THE PREFERRED EMBODIMENT 
FIG. 1 shows a simplified cross-sectional view of an intermediate step in 
the fabrication of a self-aligned FET structure using a LaB.sub.6 /TiWN 
"T-shape" gate in accordance with the present invention. FIG. 1 includes 
semiconductor substrate GaAs 10, or other semiconductor substrates such as 
indium phosphide or silicon, with an implanted channel 15 followed by 
sputter deposition of TiWN refractory gate metal layer 11. TiWN is used 
for its high temperature stability. Channel 15 could also be epitaxially 
grown by either molecular beam epitaxy or metal organic chemical vapor 
epitaxy. 
Referring specifically to FIG. 2, a photoresist layer 12 is deposited on 
the surface of layer 11 so as to specifically overlie implanted channel 
15. An opening 16 is formed in layer 12 by any standard photolithography 
process. FIG. 3 illustrates the selective deposition of a LaB.sub.6 layer 
13 on the surface of layer 11 in opening 16 through the lift-off process. 
Layer 13 of LaB.sub.6 is deposited by electron beam evaporation which 
eliminates any subsequent patterning and selective etch development. 
FIG. 4 shows the cross section of LaB.sub.6 /TiWN "T-shape" gate structure. 
The "T-shaped" gate structure is formed by removing photoresist layer 12 
and selective dry etching of TiWN layer 11 using LaB6 layer 13 as the 
mask. The selective dry etching uses SF6 (20 SCCM), CHF3 (13 SCCM), He (40 
SCCM) at plasma frequency of 13.56 MHz with RF power and pressure of 145 W 
and 130 m Torr respectively. The etch rate of this process is around 500 
.ANG./min and due to extremely high selectivity of this etch (greater than 
200:1) during the etching of TiWN layer 11 neither LaB.sub.6 layer 13 nor 
channel layer 15 is etched. The etch rate of TiWN is slow enough to allow 
the reproducible control of undercut 14. FIG. 5 shows the cross section of 
a silicon nitride layer 17 passivated LaB.sub.6 /TiWN "T-shaped" gate 
structure. After the etching step of FIG. 4, the entire structure is 
passivated by forming layer 17 thereover. 
Source and drain ohmic regions 19 are implanted in a self-aligned fashion 
using the "T-shaped" gate as the mask, as shown in FIG. 6. The structure 
is subsequently annealed at 750.degree. C. for 10 second. Since LaB.sub.6 
layer 13 is both a metal and can withstand high temperature processes it 
does not have to be removed before deposition of source drain metal in a 
self-aligned fashion. The distance of undercut 14 determines the distance 
20 between gate metal 11 and n+ source and drain implant regions 19 which 
influence the speed (through affecting the gate-source capacitance) and 
power performance (through affecting the breakdown voltage) of a FET 
device. 
Most prior art used a "T-shape" gate structure with a top layer 13 such as 
nickel, silicon dioxide, or silicon nitride. The problem with these top 
layers are that the silicon dioxide, or silicon nitride are dielectric 
layers which can withstand high temperature process, however they 
eliminate the option of a self-aligned formation of source drain ohmic 
contacts using the "T-shaped" gate as the mask since they have to be 
removed prior to source anti drain metallization. If the silicon dioxide 
or silicon nitride layers are not removed, a dielectric layer is left 
between gate metal layer 11 and the subsequently deposited contacts. On 
the other hand metallic layers such as nickel are not compatible with the 
high temperature (greater than 750.degree. C.) annealing process required 
for activation of n+ source and drain implant regions 19 and therefore 
have to be removed or etched at this step of the processing. 
In the prior art patent (U.S. Pat. No. 4,712,219) described above, a high 
temperature stable conductive material using a doped silicon layer was 
suggested that requires a complicated process of selectively etching and 
doping of a silicon layer which is not a manufacturable process. However 
in the present invention we propose LaB6 layer 13 which is a refractory 
metal and has excellent mechanical, metallurgical, and electrical 
stability (was verified by secondary ion mass spectroscopy SIMS and 
scanning electron microscope SEM analysis) during high temperature 
processes when sandwiched between silicon nitride 17 and TiWN 11. 
The advantages of LaB6 over other refractory metals is that it is easily 
evaporated using electron beam evaporation and patterned using 
conventional lift-off process therefore eliminating difficult dry etching 
processes needed for other refractory metal such as molybdenum. Also since 
LaB.sub.6 is difficult to etch it acts as a perfect mask for selective 
etching of TiWN underlying gate layer 11 for its patterning and formation 
of the "T-shaped" gate. 
Referring specifically to FIG. 7, a photoresist layer 12 is deposited on 
the surface of substrate 10 so as to specifically overlie the entire 
structure. An opening 26 is formed in layer 12 using standard 
photolithography process as illustrated in FIG. 7. FIG. 8 illustrates the 
selective deposition of a layer 16 of Ge/Ni/Au in a self-aligned manner on 
the surfaces of layer 13 and layer 19 and in the opening 26 through the 
lift-off process that eliminates any need for precise registration and 
aligning of the source and drain contacts. This self-align ohmic contact 
process not only minimizes the parasitic resistance it also reduces the 
gate resistance simultaneously by depositing layer 16 on top of layer 13 
in the "T-shape" gate. This is extremely important since most refractory 
metals have very high resistance which severely degrade the gain, noise 
figure, frequency response, and efficiency of the transistor. 
FIG. 9 shows the final step of the fabrication process which is device 
isolation formation. The device formed as described above, is isolated 
from other devices on substrate 10 by mesa etch (see FIG. 9) or by ion 
implantation. In ion implantation a guard ring is implanted around the 
device for isolation in a well known manner. 
The present invention provides a method of fabricating self-aligned FET 
with both n+ implants and ohmic metals formed in a self-aligned fashion 
with respect to the gate which is easily manufacturable with controllable 
distances between gate metal and n+ source and drain implants which 
eliminates any critical alignment of source and drain ohmic contacts. The 
present invention still further provides a method of fabricating 
self-aligned FETs with improved speed performance for use in digital 
circuitry which eliminates any critical processing steps for reducing gate 
resistance. 
While we have shown and described specific embodiments of the present 
invention, further modifications and improvements will occur to those 
skilled in the art. We desire it to be understood, therefore, that this 
invention is not limited to the particular forms shown and we intend in 
the appended claims to cover all modifications that do not depart from the 
spirit and scope of this invention.