Tapered gate electrode for semiconductor devices

The subject matter disclosed herein relates to metal-oxide-semiconductor (MOS) devices, such as silicon carbide (SiC) power devices (e.g., MOSFETs, IGBTs, etc.) In an embodiment, a semiconductor device includes a gate oxide layer disposed on top of a semiconductor layer. The semiconductor device also includes a gate electrode having a tapered sidewall. Further, the gate electrode includes a polysilicon layer disposed on top of the gate oxide layer and a metal silicide layer disposed on top of the polysilicon layer.

BACKGROUND

The subject matter disclosed herein relates to metal-oxide-semiconductor (MOS) devices, such as silicon carbide (SiC) power devices (e.g., MOSFETs, IGBTs, etc.).

Power conversion devices are widely used throughout modern electrical systems to convert electrical power from one form to another form for consumption by a load. Many power electronics systems utilize various semiconductor devices and components, such as thyristors, diodes, and various types of transistors (e.g., metal-oxide-semiconductor field-effect transistor (MOSFETs), junction gate field-effect transistor (JFETs), insulated gate bipolar transistors (IGBTs), and other suitable transistors), in this power conversion process.

Specifically for high-voltage and/or high-current applications, devices utilizing wide bandgap semiconductors, such as silicon carbide (SiC), aluminum nitride (AlN), gallium nitride (GaN), etc., may afford a number of advantages in terms of high temperature operation, reduced ON-resistance, and smaller die size than corresponding silicon (Si) devices. Accordingly, wide bandgap semiconductor devices offer advantages to electrical conversion applications including, for example, power distribution systems (e.g., in electrical grids), power generation systems (e.g., in solar and wind converters), as well as consumer goods (e.g., electric vehicles, appliances, power supplies, etc.). For many semiconductor devices, such as SiC power devices, reliability is highly desirable. That is, it may be desirable to produce semiconductor devices (e.g., MOSFET devices) that exhibit long lifetimes, even after extended exposure to high-temperature and high-bias conditions.

BRIEF DESCRIPTION

In an embodiment, a semiconductor device includes a gate oxide layer disposed on top of a semiconductor layer. The semiconductor device also includes a gate electrode having a tapered sidewall. Further, the gate electrode includes a polysilicon layer disposed on top of the gate oxide layer and a metal silicide layer disposed on top of the polysilicon layer.

In another embodiment, a method of manufacturing a metal-oxide semiconductor (MOS) device includes forming a photoresist layer over a portion of a surface of the MOS device, wherein the photoresist layer has a first tapered edge. The method includes plasma etching the surface of the MOS device such that the first tapered edge of the photoresist layer imparts a second tapered edge in at least one layer of the MOS device disposed below the photoresist layer.

In another embodiment, a semiconductor substrate includes an oxide layer disposed over a surface of the semiconductor substrate and a polysilicon layer disposed over a portion of the gate oxide layer. The polysilicon layer has a tapered edge that is disposed at an angle relative to the surface of the semiconductor substrate, wherein the angle is less than 90 degrees. The semiconductor substrate also includes a photoresist layer disposed above the polysilicon layer, wherein the photoresist layer has a rounded edge disposed near the tapered edge of the polysilicon layer.

DETAILED DESCRIPTION

When introducing elements of various embodiments of the present disclosure, the articles “a,” “an,” and “the” are intended to mean that there are one or more of the elements. The terms “comprising,” “including,” and “having” are intended to be inclusive and mean that there may be additional elements other than the listed elements. Additionally, it should be understood that references to “one embodiment” or “an embodiment” of the present disclosure are not intended to be interpreted as excluding the existence of additional embodiments that also incorporate the recited features. It should be understood that, in describing the layers of the semiconductor devices, the terms “above” and “below,” as used herein, may designate a relative position of two layers that may or may not be in direct contact with one another. It should also be understood that the terms “over,” “on top of,” and “directly below,” as used herein, designate the relative position of two layers that are in direct contact with one another.

Many modern semiconductor devices rely in a relatively thin gate oxide layer to electrically isolate the gate electrode from other components of the semiconductor device structure. As such, for many semiconductor devices, this thin gate oxide layer may be a principle limiting factor in the reliability and lifetime of the device. Accordingly, different techniques have been explored for improving reliability of MOS devices. Certain techniques focus on the quality of the gate oxide itself, including, for example, techniques involving special anneals of the gate oxide layer, the use of thicker gate oxide layers, the use of different types of gate materials, and so forth. However, these techniques generally involve some performance trade-off in exchange for the improved reliability.

With the foregoing in mind, present embodiments are directed toward improving the reliability in semiconductor devices, such as SiC MOS devices, without sacrificing device performance. Present embodiments improve the reliability of the gate oxide layer by providing a MOS device having a gate electrode with sloped or tapered sidewalls. For example, as set forth below, during the photolithographic patterning of the gate electrode layer of the device, a high-temperature reflow bake may be used to round or taper the edges of a photoresist disposed over the gate electrode. As such, as set forth below, when the edges of the gate electrode are plasma etched, the rounded or tapered edges of the photoresist may impart sloping or tapered edges to the sidewalls of the gate electrode, which remains after the photoresist is subsequently removed. Additionally, as set forth in detail below, the presently disclosed tapered gate electrode design enables a cleaner gate oxide layer (e.g., with little to no etching byproducts) with a controlled thickness (e.g., due to reduced trenching of the gate oxide at the edge of the gate electrode). These improvements enable the fabrication of a semiconductor device having greater reliability and/or performance when compared to the similar semiconductor devices having gate electrodes with substantially vertical sidewalls or edges.

It may be appreciated that the presently disclosed semiconductor designs may be applicable to controlling the sidewall geometry of a polysilicon layer, such as a polysilicon layer of a gate electrode of a MOS device (e.g., MOSFETs, insulated gate bipolar transistors (IGBTs), insulated base MOS-controlled thyristor (IBMCT), base resistance MOS-Controlled thyristor (BRT), etc.). Additionally, in certain embodiments, semiconductor devices of the present approach may be manufactured from silicon (Si), germanium (Ge), aluminum nitride (AlN), gallium nitride (GaN), gallium arsenide (GaAs), diamond (C), or any other semiconductor that may utilize a polysilicon layer (e.g., a polysilicon gate electrode). Further, it may be appreciated that, while the present technique is discussed herein in terms of fabricating a gate electrode having a tapered sidewall, the present approach may be useful for fabricating any polysilicon structure having a tapered or sloping edge or sidewall.

With the foregoing in mind,FIG. 1illustrates an active cell of a planar n-channel field-effect transistor, namely a DMOSFET, hereinafter MOSFET device10, having a gate electrode12with a substantially vertical edge. It may be appreciated that, in order to more clearly illustrate certain components of the MOSFET device10, as well as other devices discussed below, certain commonly understood design elements (e.g., top metallization, passivation, edge termination, and so forth) may be omitted. The illustrated MOSFET device10ofFIG. 1includes a drain contact13disposed on the bottom of the device, below an n-type substrate layer14. Above the substrate layer14, an n-type drift layer16is disposed. Near the surface of the MOSFET device10, p-well18(e.g., well region18) and an n+ region20are situated below a source contact22. Further, a gate oxide layer24isolates a gate26from the n+ region20and the p-well18. During operation, an appropriate gate voltage (e.g., at or beyond a threshold voltage (VTH) of the MOSFET device10) may cause an inversion layer to form in the channel region28, as well as a conductive path to form in the junction gate field-effect transistor (JFET) region29, allowing current to flow between the source contact22and the drain contact12.

Additionally, for the MOSFET device10illustrated inFIG. 1, the sidewalls30of the gate electrode12are substantially vertical. That is, the sidewalls30of the illustrated gate electrode12are oriented substantially orthogonal (e.g., approximately) 90° relative to the surface of the semiconductor device10. It may be appreciated that, during the manufacture of the gate electrode12of the illustrated MOSFET device10, the gate oxide layer24may first be formed (e.g., grown and/or deposited) over the surface of the semiconductor device10. Subsequently, one or more gate electrode layers may be formed (e.g., grown and/or deposited) on top of the gate oxide layer24. Then, photolithography may be used to pattern the one or more gate electrode layers into the gate electrode12. For example, once a photoresist has been deposited and developed, portions of the one or more gate electrode layers may be exposed after undeveloped portions of a photoresist are subsequently removed. As such, these exposed portions of the gate electrode layers may be removed during plasma etching (e.g., using an inductively coupled plasma (ICP) processing system), defining the vertical edges30of the gate electrode12.

It may be appreciated that forming the vertical sidewalls30of the gate electrode12, as illustrated inFIG. 1, hinders reliability of the gate oxide layer24for at least two reasons. First, when plasma etching to form the vertical sidewalls30of the gate electrode12, a typical photoresist layer disposed over the one or more gate electrode layers may have substantially vertical sidewall. This substantially vertical sidewall of the photoresist is highly susceptible to accumulating contaminants and byproducts formed during the etching process. These byproducts may include conductive elements, such as metals, that may become incorporated into the gate oxide layer12after removing the photoresist layer, diminishing the effectiveness of the gate oxide layer12. Secondly, once the vertical sidewalls30of the gate electrode12are formed during a plasma etching process, the vertical sidewalls30may subsequently increase the etching rate of the gate oxide layer24disposed directly beneath the vertical sidewalls30, which is commonly known as “trenching.” As such, the vertical sidewalls30may lead to a significant amount of trenching of the gate oxide layer24at the edges of the gate electrode24. This trenching effect may lead to thinner gate oxide layers24near the vertical sidewalls30of the gate electrode24, which may result in shorter device lifetimes and poorer device reliability.

In contrast,FIG. 2is a schematic illustrating a portion of a semiconductor device40having a gate electrode12with a sloped or tapered sidewall42, in accordance with an embodiment of the present approach. The gate electrode12of the illustrated semiconductor device40includes a metal silicide layer44(e.g., a metal silicide sublayer44of the gate electrode layer12), which is disposed on top of a polysilicon layer46(e.g., a polysilicon sublayer46of the gate electrode layer12). In certain embodiments, the metal silicide layer44may include tantalum silicide, nickel silicide, cobalt silicide, titanium silicide, molybdenum silicide, tungsten silicide, niobium silicide, hafnium silicide, zirconium silicide, vanadium silicide, chromium silicide, and/or platinum silicide. In certain embodiments, the metal silicide layer44may include tantalum silicide having a particular relative ratio between the number of silicon atoms per tantalum atom (e.g., a particular formula) in the layer. It may be appreciated that, in general, a more Si-rich metal silicide layer44may advantageously have a lower level of stress, but may also provide lower conductivity and/or a higher void density. Conversely, if too little Si is present when forming the metal silicide layer44, a portion of the polysilicon layer46may be inadvertently consumed and the resulting metal silicide layer44may have a higher stress. For example, in certain embodiments, the number of silicon atoms per tantalum atom may be any value between approximately 2 and 4 (e.g., TiSi2-TiSi4), such as 2.7 (e.g., TiSi2.7) or 3.3 (e.g., TiSi3.3). In certain embodiments, the polysilicon layer46may be a highly doped (e.g., highly N or P doped) polysilicon layer. Additionally, in certain embodiments, the gate electrode12may include additional layers (e.g., additional metal silicide layers) without negating the effect of the present approach.

Additionally,FIG. 2illustrates the angle48of the edge50of the metal silicide layer44, as well as the angle52of the edge54of the polysilicon layer42, relative to the surface of the semiconductor device. It may be appreciated that the edges58and62together form the sidewall42of the gate electrode12. As illustrated, the angle48of the edge50of the metal silicide layer44may, in certain embodiments, be less than or equal to approximately 90° (e.g., between approximately 70° and approximately 90°). The illustrated angle52of the substantially tapered edge54of the polysilicon layer42may, in certain embodiments, be less than 90°, or between approximately 50° and approximately 90°, between approximately 55° and approximately 85°, between approximately 60° and approximately 80°, between approximately 65° and approximately 75°, or approximately 70°. As discussed in greater detail below, the angles48and52may be influenced by the angle of the sidewall of a photoresist layer disposed above the gate electrode12, as well as the relative vertical and lateral etching rates of the metal silicide layer44and the polysilicon layer46, during plasma etching.

Further, for the semiconductor device40illustrated inFIG. 2, the two layers44and46of the gate electrode12are disposed on top of the gate oxide layer24, which electrically isolates the gate electrode12from other portions of the semiconductor device40disposed below the gate oxide layer24. The gate oxide layer24includes a first portion45that is disposed directly under the gate electrode12and includes a second portion47that is not disposed directly under the gate electrode12. As illustrated inFIG. 2, in certain embodiments, the first portion45of the gate oxide layer24may have thickness55(e.g., between approximately 475 Å and approximately 600 Å, or approximately 500 Å) that is substantially retained during the plasma etch. Meanwhile, the exposed second portion47of the gate oxide layer24may be thinned (e.g., by between approximately 75 Å and approximately 200 Å) during plasma etching to achieve a thickness60(e.g., approximately 350 Å). As discussed in greater detail below, in certain embodiments, the second portion47of the gate oxide layer24may be thinned by between approximately 20% and approximately 35% or between approximately 20% and approximately 45%. As such, in certain embodiments, after plasma etching, the second portion47of the gate oxide layer24may have a thickness between approximately 275 Å and approximately 400 Å, or between approximately 300 Å and approximately 375 Å, after between approximately 100 Å and approximately 175 Å of the gate oxide layer24is removed.

As with the trenching effect described above with respect to the MOSFET device10, the tapered sidewall42may somewhat increase the rate of etching of the gate oxide layer24near the sidewall42relative to the remainder of the portion47of the gate oxide layer24. As illustrated inFIG. 2, a shallow trench56(e.g., microtrench56having a depth58of approximately 120 Å or less) may form near the sidewall42of the gate electrode12while thinning the second portion47of the gate oxide layer24to the desired thickness60(e.g., approximately 350 Å). It should be appreciated that the increased etching rate produced by the tapered sidewall42may be significantly less than the increased etching rate produced by the vertical sidewalls (e.g., vertical sidewalls30illustrated inFIG. 1) of the MOSFET device10. As such, in certain embodiments, the gate oxide layer24may be substantially free or completely free of microtrenches56near the tapered sidewall42of the gate electrode12. Therefore, the reduced trenching enabled by the tapered sidewall42either provides shallower trenches56or eliminates them altogether, thereby improving the quality of the gate oxide layer24, especially near the edges of the gate electrode12.

FIG. 3is an illustration of a cross-section of a top portion of a semiconductor device70after plasma etching, in accordance with an embodiment of the present approach. More specifically,FIGS. 3 and 4are line drawing representations of scanning electron microscope (SEM) images collected during cross-sectional analysis of the semiconductor device70. As such,FIGS. 3 and 4illustrate the layers of the semiconductor device70as having minor imperfections (e.g., layers that are not perfectly planar, edges that are not perfectly straight, and so forth) that are common to the semiconductor fabrication techniques currently employed in the field, as may be appreciated by those skilled in the art. Like the semiconductor device40illustrated inFIG. 2, the semiconductor device50includes a gate electrode24having a bottom polysilicon layer46and having an upper metal silicide layer44disposed on top of the gate oxide layer24. However, unlike the semiconductor device40illustrated inFIG. 2, for the semiconductor device50illustrated inFIG. 3, the photoresist layer72has not yet been removed from the surface of the gate electrode12(e.g., using a plasma ashing process) so that the rounded shape (e.g., tapered or sloped shape) of the photoresist layer72may be appreciated. As set forth in detail below with respect toFIG. 7, in certain embodiments, certain process steps may be performed to deposit, develop, and shape a photoresist material into a rounded photoresist layer72(e.g., a photoresist layer72with tapered sidewalls or edges), as illustrated inFIG. 3.

FIG. 4is an illustration depicting an enlarged view of one of the sidewalls42of the semiconductor device70illustrated inFIG. 3. As such,FIG. 4illustrates the various layers (e.g., the gate oxide layer24, the polysilicon layer46and the metal silicide layer44of the gate electrode12, and the rounded photoresist layer72) discussed above. In addition to the angles48and52discussed above,FIG. 4includes angle74, which is the angle of the edge76of the rounded or tapered photoresist layer72. In certain embodiments, the angle74may be between approximately 30° and approximately 70°, between approximately 35° and approximately 65°, between approximately 40° and approximately 60°, between approximately 45° and approximately 55°, or approximately 50°.

It may be appreciated that, during the aforementioned plasma etch process that forms tapered gate electrode12illustrated inFIGS. 3 and 4, the rounded photoresist layer72, the metal silicide layer44, and the polysilicon layer46may each have a vertical etch rate and a lateral etch rate that influences the resulting shape of the sidewall42. For example, in an embodiment, the photoresist layer52, the metal silicide layer44, and the top of the polysilicon layer46may all have an effective lateral etch rate of approximately 570 Å/min, while the bottom of the polysilicon layer46(e.g., closest to the gate oxide layer24) may have an effective lateral etch rate of approximately 0 Å/min. Additionally, for such an embodiment, the photoresist layer52may have a vertical etch rate of approximately 1500 Å/min, the metal silicide layer44may have a vertical etch rate of approximately 5500 Å/min, and the polysilicon layer46may have a vertical etch rate of approximately 2700 Å/min. Accordingly, the rapid vertical etching rate of the metal silicide layer44, which greatly exceeds the lateral etch rate, resulting in a substantially vertical metal silicide layer44. Further, the substantial lack of etching at the bottom of the polysilicon layer46compared to the substantial etching of the top of the polysilicon layer46, the photoresist layer52, and metal silicide layer44contributes to forming the angle52of the edge54of the polysilicon layer, contributing to the tapered sidewall42of the gate electrode12.

FIG. 5is a flow diagram illustrating an embodiment of a process90by which a tapered gate electrode12may be fabricated. The illustrated process90begins with forming (block92) a gate oxide layer24over the surface of a semiconductor device (e.g., a SiC MOSFET device) during fabrication. A polysilicon layer46of a gate electrode12may then be formed (block94) on top of a portion of the gate oxide layer24. Subsequently, a metal silicide layer44of the gate electrode12may be formed (block96) on top of the polysilicon layer46. Next, a photoresist layer72may be deposited and shaped (block98) on top of the metal silicide layer44of the gate electrode12, as discussed in detail below with respect toFIG. 7.

Continuing through the process90illustrated inFIG. 5, after forming the rounded photoresist layer72, plasma etching may be performed (block100) to remove at least a portion of the metal silicide layer44and the polysilicon layer46of the gate electrode12from the surface of the semiconductor device40, as discussed in greater detail below with respect toFIG. 9. Additionally, in certain embodiments, during the plasma etch, a portion of the gate oxide layer24may be intentionally removed from the surface of the semiconductor device in order to remove any contaminants that may be present in the surface of the gate oxide layer24. Furthermore, in certain embodiments, additionally or alternatively a wet etch (e.g., 2% hydrofluoric acid (HF) for approximately 70 seconds) may be performed (block102) to remove a portion of the exposed surface of the gate oxide layer24after plasma etching is completed. For such embodiments, this wet etch may remove a top surface (e.g., approximately 120 Å) of the gate oxide layer, which may remove the small trench56discussed above with respect toFIG. 2that may be formed near the tapered sidewall42of the gate electrode12during plasma etching. Further, for such embodiments, this wet etch may remove contamination from the etching process, remove a plasma damage layer formed as a side-effect of the plasma etch process, and clean residue from the sidewalls of the gate (e.g., including remaining metallic veils), while removing the gate oxide in a reasonable and controllable amount of time.

It may be appreciated that it is desirable to control the thickness of the gate oxide (e.g., the thickness60of the portion of the gate oxide layer that is not disposed under the gate electrode) when plasma etching and/or wet etching the surface of the semiconductor device40. For example,FIG. 6illustrates a graph104that includes two curves: curve105and curve106. The curve105illustrates a general trend for semiconductor device leakage as a function of the gate oxide layer24removed/remaining from a semiconductor device embodiment that has an initial gate oxide thickness (e.g., thickness55illustrated inFIG. 2) of approximately 475 Å. The curve106illustrates a general trend for device reliability as a function of the gate oxide layer24removed/remaining for the embodiment of the semiconductor device40. Accordingly, the range108illustrates a desired gate oxide thickness to be achieved after one or more etching steps for the semiconductor device embodiment. That is, as illustrated by the range108, it may be desirable to remove approximately 100 Å to approximately 175 Å of the gate oxide layer24to achieve a gate oxide thickness60between approximately 300 Å and approximately 375 Å for the illustrated embodiment of the semiconductor device40. In other words, in certain embodiments, it may be desirable to remove between approximately 20% and approximately 35% of the gate oxide layer24, leaving approximately 80% to approximately 65% of the gate oxide layer24remaining in order to achieve a semiconductor device with suitable leakage and reliability.

As mentioned above,FIG. 7illustrates an embodiment of a process110(represented by block98ofFIG. 5) whereby the photoresist layer72may be deposited and suitably shaped prior to plasma etching of the surface of the semiconductor device40. The illustrated process110begins with depositing (block112) a photoresist (e.g., approximately 1.3 μm) over the gate electrode12of the semiconductor device40. Then, the photoresist may be soft baked (block114) (e.g., approximately 1 minute at approximately 110° C.) prior to selectively exposing (block116) portions of the photoresist to a suitable light source (e.g., approximately 200 mJ/cm2). Subsequently, the photoresist may be soft baked (block114) once again (e.g., approximately 1 minute at approximately 110° C.) prior to developing (block120) the photoresist (e.g., for approximately 75 seconds). Finally, a higher temperature reflow bake of the photoresist may be performed (block122) (e.g., approximately 3 minutes at approximately 170° C.) in order to impart a rounded shape (e.g., the rounded or tapered sidewalls or edges76) to the photoresist72that is illustrated inFIG. 3. In other words, the reflow bake may generally approach or reach a melting point or melting point range of the photoresist layer such that the substantially vertical edges at least partially melt to form rounded (e.g., tapered or sloped) edges or sidewalls76. As such, the reflow bake step produces a rounded photoresist sidewall profile, as illustrated inFIG. 3, which, in addition to helping impart the tapered shape to the sidewall42of the gate electrode12, may help to prevent inorganic sidewall residue accumulation during the subsequent plasma etching process.

However, it may be appreciated that the reflow bake process also presents challenges to the device design. For example,FIG. 8is a graph126illustrating an average gate line width127for semiconductor devices manufactured using a typical photoresist layer as well as an average gate line width128for semiconductor device embodiments (e.g., device40) manufactured using the presently disclosed rounded photoresist layer72. As illustrated in the graph126, while the typical photoresist layer provides a certain average gate line width127, the rounded photoresist layer72provides an average gate line width128that is larger (e.g., 0.1%, 0.2%, 0.3%, 0.4%, 0.5%, or 1% greater) than the average gate line width127. Accordingly, since smaller gate line widths are typically desirable, one of skill in the art may hesitate in implementing the tapered gate electrode design presently disclosed. However, for certain device structures, the benefits provided by the presently disclosed tapered sidewall42to the reliability and performance of the resulting semiconductor device40may exceed the negative impacts of the greater gate line width afforded by the present approach.

As mentioned above,FIG. 9illustrates an embodiment of a process130(represented by block100ofFIG. 5) that describes plasma etching of the semiconductor device40. The illustrated process130includes plasma etching (block132) through the metal silicide layer44of the gate electrode12at the edges of the photoresist layer72to provide the metal silicide layer44with substantially vertical edges50. The illustrated process130also includes plasma etching (block134) through the polysilicon layer46of the gate electrode12below the substantially vertical edges of the metal silicide layer44to provide the polysilicon layer46with substantially tapered edges54. As such, it may be appreciated that the actions described in block132and134may provide the gate electrode12having the tapered sidewall42. Further, as mentioned above, in certain embodiments, the process130may include etching (block136) (e.g., plasma or wet etching) away a surface layer (e.g., approximately 100 Å) of the portion of the gate oxide layer24that is not disposed below the gate electrode12. It may be appreciated that, at certain points during the etching process, at least a portion of the etching described in blocks132,134, and136may occur simultaneously as the surface of the semiconductor device is exposed to etching conditions in certain embodiments.

It should also be appreciated that the disclosed rounded photoresist layer72(e.g., having the rounded or tapered edge76) helps to prevent the accumulation of residue (e.g., etch byproducts) during the plasma etching process130. That is, for a semiconductor device having a photoresist layer that does not undergo a reflow bake, during plasma etching, inorganic etch products can build up on vertical sidewalls of the photoresist layer. Subsequently, when the photoresist is subsequently removed (e.g., using plasma ashing), the inorganic etch products may remain behind, possibly imparting undesired conductivity to the gate oxide layer24. Further, these inorganic residues may be exceedingly difficult to remove, even with wet cleaning steps post ashing. However, these inorganic residues are not collected on the surface of the rounded photoresist layer72during plasma etching since they are etched away faster than they are deposited, which enables a cleaner device surface after the photoresist layer72is removed (e.g., using plasma ashing). Accordingly, the presently disclosed rounded photoresist layer72may prevent residue build-up and deposition, enabling the fabrication of semiconductor devices with better reliability and performance.

Technical effects of the invention include improving the reliability and performance of semiconductor devices. In particular, present embodiments improve the reliability of the gate oxide layer of MOS devices by utilizing a gate electrode having tapered sidewalls. As discussed above, during plasma etching, a photoresist layer having rounded edges (e.g., from a reflow bake process) imparts tapered edges to the sidewalls of the gate electrode. Additionally, during plasma etching, the rounded photoresist layer may not accumulate inorganic etch byproducts, resulting in a cleaner gate oxide layer after photoresist removal. Further, during plasma etching, the tapered sidewall of the gate electrode results in less trenching of the underlying gate oxide, which may further improve the quality of the gate oxide layer. Further, these tapered sidewalls MOS devices demonstrate improved the performance and reliability during operation. As such, the presently disclosed tapered gate electrode and higher quality gate oxide layer enable the fabrication of a semiconductor device having better performance and reliability when compared to the similar semiconductor devices having gate electrodes with substantially vertical sidewalls.