Single wire bus communication protocol

A method of communication over a single-wire bus between a transmitter device and at least one receiver device, wherein each data bit is transmitted in a frame successively including: a synchronization slot different from a reference voltage of the devices; a first idle slot in a state corresponding to the reference voltage of the circuit; a slot representing the data bit to be transmitted; a second idle slot identical to the first one; a slot intended to contain the state of an optional response bit; and an end slot identical to the idle slot.

CROSS REFERENCE TO RELATED APPLICATIONS

This application claims the priority benefit of French patent application Ser. No. 09/55109, filed on Jul. 22, 2009, entitled “SINGLE-WIRE BUS COMMUNICATION PROTOCOL,” which is hereby incorporated by reference to the maximum extent allowable by law.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention generally relates to electronic circuits and, more specifically, to communication protocols over a single-wire link. The present invention also relates to such protocols capable of operating in bidirectional fashion.

2. Discussion of the Related Art

There exist many communication protocols over a single-wire bus between two electronic circuits. Reference is often made to so-called SWP (Single-Wire Protocol) or 12C protocols, which are standardized protocols. Such protocols actually exploit two transmission lines, one for a clock signal and the other for a data signal.

A problem of single-wire buses is that the loads (the transmit and receive circuits) which are connected thereto generate coupling variations. Further, single-wire buses are often sensitive to noise since the communication frames have no reference levels.

SUMMARY OF THE INVENTION

It would be desirable to have a single-wire bus communication protocol which overcomes all or part of the disadvantages of usual protocols.

An object of an embodiment of the present invention is to provide a communication protocol over a single-wire bus both conveying the synchronization and data signals.

An object of an embodiment of the present invention is to provide a bidirectional protocol.

An object of an embodiment of the present invention is to provide a multipoint system in which a same master circuit can send data to several slave circuits.

To achieve all or part of these objects as well as others, at least one embodiment of the present invention provides a method of communication over a single-wire bus between a transmitter device and at least one receiver device, wherein each data bit is transmitted in a frame successively comprising:

a synchronization slot different from a reference voltage of the devices;

a first idle slot in a state corresponding to the reference voltage of the circuit;

a slot representing the data bit to be transmitted;

a second idle slot identical to the first one;

a slot intended to contain the state of an optional response bit; and

an end slot identical to the idle slots.

According to an embodiment of the present invention, the durations of all the slots of the frame are identical.

According to an embodiment of the present invention, the synchronization slot is coded differently from the high level of the data bits.

According to an embodiment of the present invention, the reference voltage is identical to the low level of the data bits.

According to an embodiment of the present invention, to transmit data from the receiver to the transmitter, the receiver codes the slot intended for the response bit.

According to an embodiment of the present invention, the bus is, in the idle state, set to the reference voltage.

At least one embodiment of the present invention also provides a transceiver unit comprising:

a control unit;

an element for serializing data to be transmitted;

an element for parallelizing received data;

an encoder of the data to be transmitted, receiving the output of the serialization element and having its output connected to the single-wire bus; and

a decoder having its input connected to the single-wire bus and having its output connected to the input of the parallelizing circuit.

According to an embodiment of the present invention, the unit comprises a unit for configuring the transmission speed.

According to an embodiment of the present invention, the circuit comprises an input for configuring the master or slave status of the concerned circuit.

According to an embodiment of the present invention, the circuit comprises an input for configuring the mode in which the transmissions are coded and decoded among several modes.

DETAILED DESCRIPTION

The same elements have been designated with the same reference numerals in the different drawings.

For clarity, only those elements useful to the understanding of the present invention have been shown and will be described. In particular, the nature of the data to be transmitted has not been detailed, the present invention being compatible with any usual digital data. Further, the destination of the transmitted data has not been detailed either, the present invention being here again compatible with any usually exploited data.

FIG. 1is a partial block diagram of a system of communication between two circuits1and2via a single-wire bus or link3. Each circuit1,2comprises one or several units11,21(PU) for processing the data to be transmitted and received. Each unit11or21communicates with a transceiver unit5(Tx/Rx MOD), having the function of converting data to be transmitted present on a bus12, respectively22, to have them transit over single-wire link3towards the other circuit, and of decoding a signal received over single-wire bus3into receive data to be transmitted to the corresponding processing unit. Other circuits (memories, sensors, various processing circuits according to the application, etc.) may equip circuits1and2.

For a given communication, one of circuits1or2operates as a master and the other one operates as a slave. The master circuit controls the rate of the communication to the slave circuit.

Other circuits4(in dotted lines inFIG. 1) may be connected to single-wire link3for an application to a multipoint communication structure. In this case, one circuit behaves as a master and all other circuits operate as slaves. Most often, the beginning of a communication comprises an address of the circuit to which this communication is addressed, which enables, in a bidirectional mode, this sole circuit to respond to the master circuit.

For an operation in a system where several circuits are capable of taking control of the bus to start a transmission towards one or several other circuits, that is, where several circuits are capable of being masters, the single-wire bus is idle at ground. In the idle state, all the connected circuits pull (weakly) the bus to ground, only so that the bus level is not floating. Before grabbing the line to start a communication, a circuit connected to the bus desiring to transmit data starts by making sure that the bus is at the low level for a sufficient time period. A sufficient time period means, as will be better understood hereafter, a time period enabling to make sure that no communication is already going on over the bus. If the bus is free, the circuit desiring to take control of it pulls the bus to a different level, typically a level close to its supply voltage, for example, by means of a resistor (pull-up). The other circuits connected to the bus are then placed in slave mode.

In a simplified embodiment where a single circuit is capable of behaving as a master, such precautions are not necessary.

FIG. 2shows an embodiment of a transmission frame between a master circuit and one or several slave circuits. Frame10comprises six time slots. All the slots of a same frame have the same duration. Further, the different slots of frame10respect predefined states.

a synchronization slot11(SYNC);

an idle slot12(IDLE1);

a slot13representing the state (Tx) of a bit transmitted in the frame in the transmitter-to-receiver or master-to-slave direction;

a second idle slot14(IDLE2);

a slot15representing the state of a bit transmitted from the receiver to the transmitter (RX); and

an end slot16(END) or another idle slot.

Synchronization slots11are represented by a state considered as high, selected to be different from the two states (for example, 0 and 1) representative of a data bit. Slot11enables each receiver to synchronize its receive circuit. The beginning of the synchronization occurs on the rising edge of slot11and the end of the synchronization occurs on its falling edge. The time interval (duration of the synchronization slot) is used as a time base for the entire frame.

Idle slots12and14, as well as slot16, are represented by a low state. This state is, for example, identical to one (for example, 0) of the two states representative of a data bit. The presence of slots12and14between the data slots enables to absorb possible disturbances and to prepare the actual transmissions and receptions.

The slots containing the bits transmitted by transmitter TX (called transmit bits) or by receiver RX (called receive bits) take a high or low state according to the value 1 or 0 (or conversely) to be transmitted. The high state of the transmitted bits is coded differently from the high state of the synchronization slot. In a specific embodiment, a receive bit in the high state corresponds to an acknowledgement of receipt for the transmit bit.

FIG. 3is a timing diagram illustrating a first embodiment of frame10ofFIG. 2. In this example, a voltage modulation is considered. The low states are coded by a low voltage level, preferably the reference potential of the power supply voltage of the circuits (typically the ground). The high states are coded by two different voltage levels V1and V2(V1being arbitrarily greater than V2), one for the synchronization slot, the other for a data bit. The circuits connected to the bus have a common reference voltage (ground) but may have different high power supply voltages, provided that they have levels V1and V2. To simplify the following description, the system circuits are assumed to be powered independently from the bus and with the same voltage level. The low or high state of slots13and15has been illustrated by a cross to enhance the fact that the slot takes level0or V2according to the state of the bit to be transmitted.

As illustrated inFIG. 3, the data bits to be transmitted are transmitted in successive frames. The interval between two frames is preferably null, that is, a synchronization slot11of a frame follows the end slot16of the previous frame. As a variation, a time shift may be provided. In particular, such a shift is generally present between the end of a transmission and the beginning of the next one.

It should be noted that each transmission comprises a fixed number of transmitted bits (and thus a same number of frames). This number (for example, 8 or 16 bits) preferably corresponds to the depth (number of bits) of a register used in receive mode as will be better understood in relation with the followingFIG. 5.

Duration tbitof each slot of the frame depends on the desired transmission speed, for example selected according to the capacity of the circuit detectors. This time must at least enable the receiver circuit to interpret the frame.

FIG. 4is a timing diagram illustrating another embodiment in which the high states of the synchronization slot and of the data bits are respectively coded by A.C. signals at two different frequencies. For example, the synchronization slot is coded by a group of halfwaves (for example, a sinusoidal train) or a train of pulses at a first frequency (fH) while a high state of slots13or15is coded by a group of halfwaves or a train of pulses at a second frequency (fL), for example, lower than the first one. The low states of slots12,14, and16as well as the bits of value 0 transmitted in slots13and14are coded by the absence of any signal and the forcing of the bus to the reference voltage (the ground). In this embodiment, the A.C. signals are preferably centered on the reference voltage (between voltages −V and V).FIG. 4illustrates the transmission of three transmit bits (slots TX) having states 1, 0, and 1, and of three receive bits (slots RX) having states 1, 1, and 0.

FIG. 5is a simplified block diagram of a transceiver unit5capable of equipping the different system circuits (seeFIG. 1). Data TDATA to be transmitted are provided to unit5, for example, in parallel by words (for example, of 8 or 16 bits) over an output bus of the processing unit (not shown inFIG. 5). For the needs of the transmission, the data must be serialized. To achieve this, unit5comprises a transmit serializing circuit51(Tx SHIFT), for example, a shift register, preferably of first-in-first-out type (FIFO). Register51receives in parallel data TDATA to be transmitted and provides these data bit by bit to an encoder52(ENC SYNC) in charge of generating frames10. The output of encoder52is connected to single-wire bus3. On the receive side, bus3is connected to the input of a decoding circuit53(DEC SYNC) in charge of decoding the received frames. The output of decoder53is sent to the input of a circuit54for parallelizing (Rx SHIFT) the received flow into words RDATA over several bits (for example, 8 or 16). The operation of unit5is controlled by a circuit55(SAMPLER) which receives, for example, from the processing unit, a signal Tx SPEED indicative of the desired transmission speed. This signal may correspond to a clock signal or, assuming that unit5further receives a clock signal, to a speed selection signal. Circuit55also receives a signal M/S indicative of the master or slave mode of the circuit containing unit5. It further receives data relative to the transmitted and receive words from registers51and54. More specifically, register51provides data Txempty indicating that it is empty, that is, that the byte which has been loaded therein has been transmitted (at least sent to encoder52). Similarly, register54provides a signal Rxfull indicating that it contains a full data word. Indicative signals Txempty and Rxfull are also sent to circuit55to cause the sending of a new data word or notify that a received word has been delivered.

Circuits52and53also ensure the functions of modulation and demodulation of the coded frames.

Finally, unit5comprises a circuit56(PULL UP/DOWN) for managing functions pulling up the bus or pulling it down. This circuit is used in the idle state to impose a low state on the bus, and to then detect that a circuit has pulled up the bus, which enables the current circuit to set to a slave mode.

If unit5is capable of operating both in voltage mode (FIG. 3) and in frequency mode (FIG. 4), it receives a configuration bit V/F transferred by circuit55to encoders52and decoders53to place them in the adapted configuration.

Circuit55provides encoder52with data relative to the bit of the frame to be transmitted. These data are, for example, transmitted over a control bus E(S/I/T/R) in the form of a signal S/I/T/R indicating to the encoder the nature of the current slot of the frame from among the synchronization slot, an idle slot, the transmit slot, or the receive slot.

Similarly, decoder53provides circuit55with data as to the nature of the current slot that it receives in the form of a signal S/I/T/R over a bus R(S/I/T/R).

Finally, circuit55provides registers51and52with control signals TxSAMP and RxSAMP to synchronize their operation with that of encoder52and decoder53.

Signals Txempty, M/S, V/S, Rxfull, TxSAMP, and RxSAMP are, for example, binary signals having their state representing the data conveyed by the signal. Signals S/I/T/R are for example signals over two bits respectively decoded by encoder52and sampler55. Other control modes are possible, provided to respect the described functionalities. Further, other control and configuration signals may transit between the different elements of the unit (for example, power supply, clock signals, etc.).

FIG. 6is a simplified flowchart of an example of transmission of a data byte from a master circuit to a slave circuit. A first step (block601, V/F) to comprises selecting the voltage or frequency mode of the transmission. This selection is optional. In a simplified embodiment, the system only operates in voltage mode or in frequency mode and the different circuits are then set for this operating mode.

In a second step (block602, Tx SPEED), the central processing unit communicates the desired communication speed. Here again, in a simplified embodiment, the transmission speed is predefined. It should, however, be noted that the transmission speed may be modified at any time (from one bit to the other) since a synchronization slot is present at each bit.

A third step (block611, MS->M) comprises indicating to unit5an operation in master mode. Then (block612, DATA), a data byte is loaded into register51.

Circuit55then synchronizes the operation of unit5for the eight data bits to be transmitted. Circuit55is informed of the presence of the byte in register51by a state switching of signal Txempty. Circuit55sets (block621, S) bus E(S/I/T/R) to a state giving circuit52the indication to transmit a synchronization slot. Then (block622, I), it switches to the state indicating the sending of an idle slot. Circuit55then causes a state switching of signal TxSAMP (block623) directed towards register51so that said register presents the first bit to be transmitted to encoder52. Then (block624, T) it switches bus E(S/I/T/R) (block624) to value T to cause the transmission of the data bit. Circuit55then switches (block625, I) bus E(S/I/T/R) to a second idle slot I, then to state R (block626) to place encoder52in the idle state during the reception of the bit by decoder53. When decoder53has decoded slot15of the frame, it notifies circuit55by a switching of bus R(S/I/T/R) that it has received a slot15. Circuit55then switches signals Rx SAMP (block627) to notify register54that the bit provided by decoder53should be loaded. Finally, circuit55switches bus E(S/I/T/R) to the end slot or an idle slot (block628, I).

Steps621and628are carried out as long as the last data bit (block631, LAST BIT) has not been transmitted. Once it has been transmitted, the byte transmission loop is left (output Y of block631).

FIG. 7is a simplified timing diagram of an example of operation of a receiver (unit5operating in slave mode).

Regarding the master unit, it is started (block701) by selecting the operating mode between voltage and frequency.

Unit5is switched to the slave mode (block711, M/S->S) by circuit55which has detected that another circuit has taken control of the bus.

In the case of a bidirectional communication, the receive unit prepares data to be sent (block712in dotted lines, DATA).

After this, a byte receive loop starts. As soon as unit5has set to a slave mode, it expects the next edge to be the beginning of a synchronization slot, the measurement of the duration of the synchronization slot enabling circuit55to synchronize the detection of the sendings that it will perform as a response. The first step thus is (block721, DETECT S) the detection of a slot S. When it is detected, circuit53switches bus R(S/I/T/R) to notify circuit55of the reception of the synchronization slot. The next step (block722, DETECT I) is the detection of an idle slot. Circuit53places bus R(S/I/T/R) to notify circuit55of the reception of slot12. Then, it configures detector53for the decoding of slot13(reading of a level0or of a level1). As soon as the data bit is decoded (block723, DETECT T), detector53set bus R(S/I/T/R) to the corresponding state. Sampler55then switches (block724) signal Rx SAMP to indicate to register54to take into account the state present at the output of detector53. Then (block725, DETECT I), decoder53detects an idle slot.

If data must be sent from the receiver to the transmitter, circuit55detects this by the state of signal Txempty which notifies it that bits to be transmitted are present in register51. Circuit55then switches (block726in dotted lines) signal TxSAMP for the bit sending and switches (block727C in dotted lines) bus E(S/I/T/R) so that encoder52transmits the bit over bus3.

It is not disturbing for decoder53to carry on the detection during slot15. Indeed, since all slots have the same duration, detector53does not take slot15into account.

Detector53then detects the end slot (block728).

Steps721and728are repeated as long as the byte is not finished (block731, LAST BIT).

It can be seen that a synchronizations slot is sent on each exchange of a data bit. This enables resynchronizing the shift registers of the transmit and receive units.

Preferably, the circuit having initiated the transmission continues until it receives an acknowledgement of receipt for a full byte. As a variation, the transmission only proceeds from one data bit to the next data bit from the time when the receiver has acknowledged that it has received the previous bit.

It should be noted that the master and slave status of the different circuits may be configured during the communication. However, in a simplified embodiment, dedicated circuits may be used. In this case, the pull-up resistance of bus3may be omitted.

Various embodiments with different variations have been described hereabove. It should be noted that those skilled in the art may combine various elements of these various embodiments and variations without showing any inventive step. Further, the practical implementation of embodiments of the present invention and in particular of transceiver unit5based on the functional indications given hereabove is within the abilities of those skilled in the art, using usual electronic components. Further, although the present invention has been described in relation with a specific voltage and frequency mode, other coding modes of the high and low states may be envisaged. For example, a different phase may be provided according to state 0 or 1 with a signal at constant frequency. Finally, the sequencings provided as an example in the timing diagrams ofFIGS. 6 and 7may be modified according to the application.