Method, structure, and computer program product for implementing high frequency return current paths within electronic packages

A method, structure and computer program product are provided for implementing high frequency return current paths within electronic packages. Electronic package physical design data is received for identifying a design layout. For each of a plurality of cells in a grid of a set cell size within the identified design layout, a respective number of signal vias, reference voltage vias, and ground vias are identified. A signal to reference via ratio is calculated for each of the plurality of cells. Each cell having a calculated signal to reference via ratio greater than a target ratio is identified. Vias are selectively added within each of the identified cells for providing high frequency return current paths.

FIELD OF THE INVENTION

The present invention relates generally to the data processing field, and more particularly, relates to a method, structure and computer program product for implementing high frequency return current paths within electronic packages.

DESCRIPTION OF THE RELATED ART

Electronic packages typically include multiple layers or planes including multiple signal, voltage and ground planes. In high speed package design, closing the return current path of signals that change wiring planes is a key concern to guarantee proper signal integrity. When a high speed signal is traveling down a trace sandwiched between two reference planes, a return current is induced on the adjacent planes.

When the signal changes wiring layers through a via, the return current needs a low inductance path through which it can track the signal. If an adequate path is not supplied for the return current, then signal degradation occurs due to the inductive nature of the added path. Depending on the rise time of the signal, the return current path is required to be electrically close to where the signal changes planes.

Current solutions to this problem include a time consuming process of visual inspection or complicated full-wave simulation of the entire design. This costs time and money, especially when designing many high speed packages at one time. Additionally, visually inspecting a complex design is subjective and error prone.

A need exists for a mechanism for implementing high frequency return current paths within electronic packages.

SUMMARY OF THE INVENTION

A principal object of the present invention is to provide a method, structure and computer program product for implementing high frequency return current paths within electronic packages. Other important objects of the present invention are to provide such a method, structure and computer program product for implementing high frequency return current paths within electronic packages substantially without negative effect and that overcome many of the disadvantages of prior art arrangements.

In brief, a method, structure and computer program product are provided for implementing high frequency return current paths within electronic packages. Electronic package physical design data is received for identifying a board layout. For each of a plurality of cells in a grid of a set cell size within the identified board layout, a respective number of signal vias, reference voltage vias, and ground vias are identified. A signal to reference via ratio is calculated for each of the plurality of cells. Each cell having a calculated signal to reference via ratio greater than a target ratio is identified. Vias are selectively added within each of the identified cells to provide high frequency return current paths.

In accordance with features of the invention, the electronic package physical design data includes stack-up data for identifying reference voltages residing on multiple planes and reference voltages referenced by high speed nets; a board file for identifying locations of high speed nets, locations of plane change vias, and board dimensions; and a net list for creating a list of all reference voltages. The target ratio is selected by a user and is equal to a maximum desired signal to reference via ratio.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Referring now to the drawings, inFIGS. 1 and 2there is shown a computer system generally designated by the reference character100for implementing high frequency return current paths within electronic packages in accordance with the preferred embodiment. Computer system100includes a main processor102or central processor unit (CPU)102coupled by a system bus106to a memory management unit (MMU)108and system memory including a dynamic random access memory (DRAM)110, a nonvolatile random access memory (NVRAM)112, and a flash memory114. A mass storage interface116coupled to the system bus106and MMU108connects a direct access storage device (DASD)118and a CD-ROM drive120to the main processor102. Computer system100includes a display interface122coupled to the system bus106and connected to a display124.

Computer system100is shown in simplified form sufficient for understanding the present invention. The illustrated computer system100is not intended to imply architectural or functional limitations. The present invention can be used with various hardware implementations and systems and various other internal hardware devices, for example, multiple main processors.

As shown inFIG. 2, computer system100includes an operating system130, an electronic package design program132, a return current path customizing program134of the preferred embodiment, and a user interface136.

Various commercially available computers can be used for computer system100, for example, an IBM personal computer. CPU102is suitably programmed by the return current path customizing program134to execute the flowchart ofFIG. 3for implementing high frequency return current paths within electronic packages in accordance with the preferred embodiment.

In accordance with features of the preferred embodiment, a method is provided for identifying and resolving insufficient return current path locations in any type of package design in a minimal amount of time and effort, and in a consistent and reproducible manner. A systematic, computer-automated approach is used to analyze design files, interpret the outputs, and to construct a final electronic package design including customized return current paths that optimizes return current paths and maintains signal integrity.

FIG. 3illustrates the process of the preferred embodiment, drawing on interface requirements and design files as inputs. The method of the preferred embodiment provides a significant advantage of a consistent and concise way to analyze many different designs, including cards and first level packages to rapidly construct an electronic package design with optimized return current paths and signal integrity.

Referring now toFIG. 3, there are shown exemplary steps for implementing high frequency return current paths in accordance with the preferred embodiment. Electronic package physical design data is received, reference voltages residing on multiple planes are identified, and reference voltages referenced by high speed nets are identified from a plane stack-up block300. A target ratio equal to a maximum signal to reference via ratio is identified at a target ratio block302. A determination is made of locations of high speed nets, locations of plane change vias, and board dimensions from a board file as indicated in a block304. A list of all reference voltages is created from a net list block306. A via ratio calculation tool308receiving inputs from blocks300,302,304, and306, creates a reference nets list of all ground and reference voltages GND & REF—VOLTAGE(i), an ignore nets list of all reference voltages except GND & REF—VOLTAGE(i), and defines a grid size. The reference nets list of all ground and reference voltages GND & REF—VOLTAGE(i) includes each ground and voltage plane adjacent to a signal plane.

The via ratio calculation tool308determines the number of signal and reference vias within a specified cell size or board region. The reference vias within the specified cell size or board region can include only ground vias, only voltage vias or both voltage vias and ground vias. Based on the relative density of signal to reference vias, the via ratio calculation tool308calculates a qualitative figure of merit for each cell. As a result, cells that have a deficient signal return path or a calculated via ratio greater than the target ratio are identified for further processing. The user then uses this ratio as input to the remaining steps in the flow chart to determine what action must be taken. This action optimizes return current paths in a design and ensures signal integrity of all switching signals without significantly impacting design time. For cells that have an adequate signal return path or a ratio less than or equal to the target ratio, no further processing is needed as indicated in a block310.

For all cells with a ratio greater than the target ratio, checking for module or connector pins present in the cell is performed as indicated in a decision block312. Any module or connector pins present in the cell may also provide return current paths. When module or connector pins are present in the cell, then the grid size or offset optionally is changed as indicated in a block314and calculations are repeated by the via ratio calculation tool308with the changed grid size. Alternatively, the target ratio optionally is changed as indicated in a block316. The user determines the required target ratio at block316and cell size at block314for each interface or critical signals depending on design margins. Adding vias for cells that have a deficient signal return path can be accomplished through an automated or systematic approach with further processing as shown inFIG. 3.

When module or connector pins are not present in the cell or after the target ratio is increased at block316, then checking for nets referenced to REF—VOLTAGE(i) present in the cell is performed as indicated in a decision block318. When signal nets referenced to REF—VOLTAGE(i) are not present in the cell, then no further processing is needed as indicated in a block320. When signal nets referenced to REF—VOLTAGE(i) are present in the cell, then checking for critical nets changing reference domains present in the cell is performed as indicated in a decision block322. Critical nets changing reference domains include signal changes from one plane to another plane with a different reference voltage, for example, from one plane with an adjacent 1.8 voltage reference plane to another plane with an adjacent 1.2 voltage reference plane. When critical nets changing reference domains are present in the cell, then a number X of ground vias are added to the cell as indicated in a block324. When critical nets changing reference domains are not present in the cell, then checking whether the stack-up shows high speed nets changing reference domains in general is performed as indicated in a decision block326. When the stack-up shows high speed nets changing reference domains in general, then a number X/2 of ground vias are added to the cell and the rest are added to the cell as REF—VOLTAGE vias as indicated in a block328. When the stack-up does not show high speed nets changing reference domains in general, then a number X/2 of REF—VOLTAGE vias are added to the cell and a number of X/2-Y ground vias are added to the cell, where Y equals the number of ground vias already added to the cell by previous iterations of this process as indicated in a block330. This process is repeated for each cell having a ratio greater than the target ratio.

Referring now toFIG. 4, an article of manufacture or a computer program product400of the invention is illustrated. The computer program product400includes a recording medium402, such as, a floppy disk, a high capacity read only memory in the form of an optically read compact disk or CD-ROM, a tape, a transmission type media such as a digital or analog communications link, or a similar computer program product. Recording medium402stores program means404,406,408,410on the medium402for carrying out the methods for implementing high frequency return current paths within electronic packages of the preferred embodiment in the system100ofFIG. 1.

A sequence of program instructions or a logical assembly of one or more interrelated modules defined by the recorded program means404,406,408,410, direct the computer system100for implementing high frequency return current paths within electronic packages of the preferred embodiment.