Data restoration in electronic device

Restoration data is enabled to be written into a nonvolatile memory according to a simple process without using large capacity of a volatile memory.An SRAM writing section sets an updating request flag in a non-delay updating request flag region corresponding to a non-delay region where the restoration data is written. When the updating request flag is set in the non-delay updating request flag region, an EEPROM writing section writes the restoration data stored in the non-delay region corresponding to the non-delay updating request flag region into an EEPROM.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to an electronic device having a nonvolatile memory for storing data to be restored.

2. Description of the Related Art

In electronic devices such as AV amplifiers for amplifying audio signals and outputting them to speakers and personal computers, when power supply to a self device is shut off but then the power source is supplied to the self device, a state of the self device is required to be brought into a state before the power supply is shut off. For this reason, a CPU of an electronic device writes data to be restored (hereinafter, referred to as “restoration data”), which is stored in a volatile memory (for example, an SRAM) provided inside a microcomputer into an EEPROM or the like as a nonvolatile memory before the power supply is shut off. When the power source is again supplied, the CPU of the electronic device again writes (copies) the restoration data stored in the nonvolatile memory into the volatile memory, and returns the self device into the state before the power supply is shut off.

It is also considered that at a moment when the power supply to the electronic device is shut off, the restoration data stored in the volatile memory is written into the nonvolatile memory. Since the nonvolatile memory, however, requires a time for data writing, large-capacity restoration data cannot be written into the nonvolatile memory when the power supply is shut off. For this reason, conventionally, every time when the restoration data stored in the volatile memory changes, the restoration data is written into the nonvolatile memory.

Further, the CPU writes data into the volatile memory according to an application program. Restoration data and data that does not have to be restored (hereinafter, referred to as “restoration unnecessary data”) are occasionally mixed in the data to be written into the volatile memory. In such a case, when the CPU determines whether the data to be written into the volatile memory is restoration data or restoration unnecessary data according to an application program, a structure of the application program becomes complicated. Further, when the application program is corrected according to a specification change, the number of portions to be corrected increases, and erroneous correction is very likely to occur. In order to avoid this, a structure for allowing the CPU to determine whether the data to be written into the volatile memory is the restoration data or the restoration unnecessary data is not provided to the application program, and the application program only allows the CPU to write data into the volatile memory. Another program allows the CPU to monitor whether the restoration data is written into the volatile memory, namely, whether the restoration data stored in the volatile memory changes. Only when the restoration data changes, a process for writing the restoration data into the nonvolatile memory is executed.

A method for detecting whether restoration data changes includes a method for allowing the CPU to read the restoration data stored in the nonvolatile memory and comparing the read restoration data with the restoration data stored in the volatile memory. When the CPU determines that the read restoration data does not match with the restoration data stored in the volatile memory, the CPU detects a change in the restoration data. The nonvolatile memory is, however, connected mostly by a serial interface (particularly, an EEPROM), and thus constant reading of the restoration data from the nonvolatile memory places a burden on the CPU.

Therefore, in order to reduce an access to the nonvolatile memory, a copy of the restoration data written into the nonvolatile memory is written into the volatile memory.FIG. 11is a diagram illustrating a conventional process for writing data into the volatile memory (SRAM), and a process for writing data into the nonvolatile memory (EEPROM).FIG. 11illustrates the writing of data into an EEPROM103in a form of hardware, but actually a CPU101writes data into the EEPROM103according to a program (software module) (software process). Regions D01to D0N of an SRAM102are restoration data regions where restoration data is written. Regions C01to C0N of the SRAM102are restoration data copy regions where copy of restoration data is written. The CPU101compares restoration data written into the restoration data regions D01to D0N with copies of restoration data written into the restoration data copy regions C01to C0N ((1) inFIG. 11). When the CPU101determines that the restoration data does not match with the copy of the restoration data, it writes the restoration data into the EEPROM103((2) inFIG. 11). At the same time, the CPU101writes the copy of the restoration data into the restoration data copy regions C01to C0N ((3) inFIG. 11). However, since the copy of the restoration data is written into the SRAM102, an extra capacity of the SRAM102(the volatile memory) is necessary. Particularly when a capacity of the restoration data is large, a writable region of the SRAM102(the volatile memory) becomes small, and this is a problem.

As a method for reducing the capacity of the volatile memory where the copy of the restoration data is written, Japanese Patent Application Laid-Open No. 2012-137881 discloses an invention where only a checksum is written into a volatile memory. According to the invention disclosed in Japanese Patent Application Laid-Open No. 2012-137881, a necessary capacity of the volatile memory is greatly reduced, but a capacity for writing of the checksum is necessary. Further, the CPU bears a burden of calculation of the checksum.

Further, since the number of rewriting times is limited in the nonvolatile memory such as an EEPROM, when restoration data that changes frequently is written into the nonvolatile memory at every change time, a life of the nonvolatile memory is shortened. For this reason, the restoration data that changes frequently is written into the nonvolatile memory after some time (a few seconds) passes from the change in some cases (delay writing). Regions D11to D1nof the SRAM102shown inFIG. 11are delay restoration data regions where restoration data to be delayed and written is written. Regions C11to C1nof the SRAM102are delay restoration data copy regions where a copy of restoration data to be delayed and written is written. The CPU101compares the restoration data written into the delay restoration data regions D11to D1nwith the copy of the restoration data written into the delay restoration data copy regions C01to C0N ((4) inFIG. 11). When the CPU101determines that the restoration data does not match with the copy of the restoration data, it starts a timer ((5) inFIG. 11). When the timer overflows ((6) inFIG. 11), the CPU101writes the restoration data into the EEPROM103((7) inFIG. 11). At the same time, the CPU101writes the copy of the restoration data into the delay restoration data copy regions C11to C1n((8) inFIG. 11). As shown inFIG. 11, the conventional process for writing the restoration data into the nonvolatile memory is very complicated.

As described above, there is a problem that the large capacity of the volatile memory is used in order to write restoration data into the nonvolatile memory. Further, it is also a problem that the conventional process for writing the restoration data into the nonvolatile memory is very complicated.

SUMMARY OF THE INVENTION

It is an object of the present invention to enable restoration data to be written into a nonvolatile memory according to a simple process without using a large capacity of a volatile memory.

An electronic device comprising: a volatile memory having a first region, a second region where restoration data that should be stored even when power supply to a self device is shut off is stored, and a first flag region where a first flag is set correspondingly to the second region; a nonvolatile memory; a first writing section that writes data including the restoration data into the volatile memory; and a second writing section that writes the restoration data stored in the second region into the nonvolatile memory, wherein the first writing section sets the first flag in the first flag region corresponding to the second region where the restoration data is written, when the first flag is set in the first flag region, the second writing section writes the restoration data stored in the second region corresponding to the first flag region into the nonvolatile memory.

In the present invention, the volatile memory is provided with a flag region where a flag is set when restoration data is written into a second region. Further, when a flag is set in the flag region, a second writing section writes the restoration data stored in the second region corresponding to the flag region into the nonvolatile memory. Therefore, since a checksum is not calculated unlike a conventional manner, the restoration data can be written into the nonvolatile memory using the simple process. Further, for example, when a flag is set, information “1” whose data amount is small is stored in the flag region. For this reason, a copy of the restoration data and the checksum are not stored in the volatile memory unlike the conventional manner. As a result, the restoration data can be written into the nonvolatile memory without using the large capacity of the volatile memory.

Preferably, wherein the volatile memory further includes a third region where the restoration data to be delayed and written into the nonvolatile memory is stored, a second flag region where a second flag is set correspondingly to the third region, and a timer region for counting a time, the first writing section sets the second flag in the second flag region corresponding to the third region where the restoration data is written and starts time counting in the timer region, when the time counting in the timer region continues for over a predetermined time after the second flag is set in the second flag region, the second writing section writes the restoration data stored in the third region corresponding to the second flag region into the nonvolatile memory.

In the present invention, when counting in a timer region continues for over a predetermined time after a second flag is set in a second flag region, the second writing section writes restoration data stored in a third region corresponding to the second flag region into the nonvolatile memory. That is to say, the second writing section performs delay writing. For this reason, the number of times of writing into the nonvolatile memory is repressed, and a life of the nonvolatile memory can be lengthened.

Preferably, wherein the volatile memory further includes a third region where the restoration data to be delayed and written into the nonvolatile memory is stored, a second flag region where a second flag is set correspondingly to the third region, a third flag region where a third flag for prohibiting writing of the restoration data into the nonvolatile memory using the second writing section is set, and a timer region for counting a time, the first writing section sets the second flag in the second flag region corresponding to the third region where the restoration data is written, sets the third flag in the third flag region, and starts time counting in the timer region, when time counting in the timer region continues for over a predetermined time, deletes the third flag in the third flag region, when the second flag is set in the second flag region and the third flag is deleted in the third flag region, the second writing section writes the restoration data stored in the third region corresponding to the second flag region into the nonvolatile memory.

In the present invention, when the second flag is set in the second flag region and a third flag is deleted from a third flag region, namely, the counting in the timer region continues for over the predetermined time, the second writing section writes the restoration data stored in the third region corresponding to the second flag region into the nonvolatile memory. That is to say, the second writing section performs delay writing. For this reason, the number of times of writing into the nonvolatile memory is repressed, and a life of the nonvolatile memory can be lengthened.

Preferably, wherein the first writing section determines a region where the data is written based on an address of the volatile memory, when the determination is made that the restoration data is written into the second region, sets the first flag in the first flag region corresponding to the second region where the restoration data is written, when the determination is made that the restoration data is written into the third region, sets the flag in the second flag region corresponding to the third region where the restoration data is written, sets the third flag in the third flag region, and starts time counting in the timer region.

In the present invention, a region where data is written is determined based on an address of the volatile memory, and a flag can be set in a flag region corresponding to the region where the data is written.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

An embodiment of the present invention is described below.FIG. 1is a block diagram illustrating a constitution of an AV amplifier according to the present embodiment. An AV amplifier1(an electronic device) outputs an audio signal and a video signal input from, for example, a BD (Blu-ray (registered trademark) Disc) player100as a reproducing apparatus connected to an outside, to a speaker200and a display300, respectively. As shown inFIG. 1, the AV amplifier1includes a microcomputer2, an EEPROM (Electrically Erasable Programmable Read-Only Memory)3, an audio processor4, an amplifier5, a video processor6, a display section7, an operating section8and the like.

The microcomputer2is composed of hardware such as a CPU (Central Processing Unit)21, a ROM (Read Only Memory)22, and an SRAM (Static Random. Access Memory)23. The CPU21controls respective sections composing the AV amplifier1according to programs stored in the ROM22. Further, the CPU21functions as an SRAM writing section11, described later. When the CPU21executes various control processes, the SRAM.23temporarily stores a program read from the ROM22and data necessary for executing the various control processes in the CPU21. The SRAM23is a volatile memory from which stored data is deleted when power supply is shut off. The EEPROM3is for storing restoration data to be stored even when the power supply to the AV amplifier1is shutoff. The EEPROM3is a nonvolatile memory for retaining stored data even at a time of no power supply.

The audio processor4executes audio processes such as an equalizer process, a D/A converting process, a volume adjusting process on the audio signal output from the BD player100. The audio processor4outputs the audio signal subjected to the audio processes to the amplifier5. The amplifier5amplifies the audio signal output from the audio processor4. The amplifier5outputs the amplified audio signal to the speaker200. The speaker200reproduces the audio based on the audio signal output from the AV amplifier1.

The video processor6executes video processes such as an image adjusting process, a resolution converting process, and an aspect ratio converting process on the video signal output from the BD player100. The video processor6outputs the video signal subjected to the video processes to the display300. The display300reproduces a video based on the video signal output from the AV amplifier1.

The display section7displays a setting screen, a volume level and the like, and it is an LCD (liquid crystal display), a fluorescent display or the like. The operating section8accepts user operations, and it is operation buttons or a remote controller provided on an enclosure of the AV amplifier1.

Examples of the above restoration data are information about the audio processes to be executed by the audio processor4, and information about the video processes to be executed by the video processor6.FIG. 2is a diagram illustrating a process for writing data into the SRAM23and a process for writing data into the EEPROM3. As shown inFIG. 2, the SRAM23has a region B, regions D01to D0N, regions D11to D1n, regions D21to D2m, regions F01to F0N, regions F11to F1n, regions F21to F2m, regions F1sand F2s, and regions TIMERD1and TIMERD2. The region B (first region) is a region where data that does not have to be restored (hereinafter, referred to also as “restoration unnecessary data”) is stored (hereinafter, referred to also as “restoration unnecessary region”). Further, the restoration unnecessary region B includes a region smaller than an address AS0of the SRAM23, and a region larger than an address ASf.

The regions D01to D0N (second regions) are regions where restoration data is stored. Concretely, the regions D01to D0N are delay non-writing regions (hereinafter, referred to also as “non-delay regions”) where every time when restoration data is stored, namely, data stored in the regions D01to D0N changes, the written restoration data is written also into the EEPROM3. Further, the non-delay regions D01to D0N are regions of the SRAM23at addresses AS0to AS1.

The regions D11to D1n(third regions) are regions where restoration data is stored. Concretely, the regions D11to D1nare regions where delay writing is carried out in such a manner that the restoration data is written into the EEPROM3after a predetermined time passes from the writing of the restoration data, namely, the change in the data stored in the regions D11to D1n(hereinafter, referred to also as “first delay area”). Further, first delay regions D11to D1nare regions of the SRAM23at addresses AS1to AS2. The regions D21to D2m(third regions) are regions where restoration data is stored. Concretely, the regions D21to D2mare regions where delay writing is carried out (hereinafter, referred to also as “second delay region”). Further, the second delay regions D21to D2mare regions of the SRAM23at addresses AS2to ASf. In the first delay regions D11to D1nand the second delay regions D21to D2m, since restoration data is frequently changed, the restoration data is written into the EEPROM3after some time (a few seconds) passes from the change. As a result, since the number of writing times of the restoration data into the EERPOM3is reduced, a life of the EEPROM3becomes long. A time (delay writing time) from the writing of the restoration data into the SRAM23to the writing of the restoration data into the EEPROM3is different between the first delay regions D11to D1nand the second delay regions D21to D2m.

The EEPROM3has a page unit such that 8 to 32 bytes compose one page. Since writing for one page takes the same time as writing for 1 byte, the writing is generally managed in unit of one page. Therefore, the regions D01to D2mhave a constitution corresponding to the page unit of the EEPROM3.

The regions F01to F0N (first flag regions) are non-delay updating request flag regions where an updating request flag (first flag) in the non-delay region is set correspondingly to the non-delay regions D01to D0N. “Setting a flag” is changing a value of the flag region from “0” into “1”. On the contrary, “deleting a flag” is changing a value of the flag region from “1” into “0”. Therefore, when a flag is set, “1” is stored in the flag region. The regions F11to F1n(second flag regions) are first delay updating request flag regions where an updating request flag (second flag) in the first delay region is set correspondingly to the first delay regions D11to D1n. The regions F21to F2m(second flag regions) are second delay updating request flag regions where an updating request flag (second flag) in the second delay region is set correspondingly to the second delay regions D21to D2m.

Regions F1S and F2S (third flag regions) are updating repression flag regions where an updating repression flag (third flag) for prohibiting restoration data from being written into the EEPROM3using an EEPROM writing section12, described later. The region F1S is a first delay updating repression flag region corresponding to the first delay regions D11to D1n. The region F2S is a second delay updating repression flag region corresponding to the second delay regions D21to D2m. The regions TIMERD1and TIMERD2are timer regions where a time is counted. Concretely, the regions TIMERD1and TIMERD2are regions where a time value that is counted up by the SRAM writing section11, described later, is stored. Further, a maximum timer value that can be counted up is set to a predetermined time in the regions TIMERD1and TIMERD2, and when the timer value reaches the maximum timer value, overflow occurs. The region TIMERD2is a first timer region corresponding to the first delay regions D11to D1n. The maximum timer value of the first timer region TIMERD2is set to a delay writing time in the first delay regions D11to D1n. The region TIMERD2is a second timer region corresponding to the second delay regions D21to D2m. The maximum timer value of the second timer region TIMERD2is set to a delay writing time of the second delay regions D21to D2m.

A process to be executed by the CPU21is described below. The CPU21functions as the SRAM writing section11and the EEPROM writing section12. The SRAM writing section11(first writing section) writes data in the SRAM23. Concretely, the SRAM writing section11writes restoration unnecessary data in the restoration unnecessary region B based on an address of the SRAM23as a writing destination. Further, the SRAM writing section11writes restoration data in the regions D01to D2m.

Further, the SRAM writing section11determines a region where data is written based on an address of the SRAM23. Concretely, when the SRAM writing section11writes data in a region smaller than the address AS0of the SRAM23or a region larger than the address ASf, it determines that restoration unnecessary data is written in the restoration unnecessary region B. Further, when the SRAM writing section11writes data in the regions of the SRAM23at the addresses AS0to AS1, it determines that restoration data is written in the non-delay regions D01to D0N. Further, when the SRAM writing section11writes data in the regions of the SRAM23at the addresses AS1to AS2, it determines that restoration data is written in the first delay regions D11to D1n. Further, when the SRAM writing section11writes data in the regions of the SRAM23at the addresses AS2to ASf, it determines that restoration data is written in the second delay regions D21to D2m.

Further, the SRAM writing section11sets flags in the flag regions F01to F2m, F1S, and F2S, and deletes the flags. That is to say, the SRAM writing section11changes values of the flag regions F01to F2m, F1S and F2S from “0” into “1” so as to set the flags, and changes the values of the flag regions F01to F2m, F1S and F2S from “1” into “0” so as to delete the flags. Concretely, when the SRAM writing section11determines that restoration data is written in the non-delay regions D01to D0N, it sets updating request flags in the non-delay updating request flag regions F01to F0N, respectively, corresponding to the non-delay regions D01to D0N where the restoration data is written.

Further, when the SRAM writing section11determines that the restoration data is written in the first delay regions D11to D1n, it sets the updating request flags in first delay updating request flag regions F11to F1n, respectively, corresponding to the first delay regions D11to D1nwhere the restoration data is written. At this time, the SRAM writing section11sets the updating repression flag in a first delay updating repression flag region F1s. Further, the SRAM writing section11starts time counting in the first timer region TIMERD1. When counting in the first timer region TIMERD1continues for over a predetermined time and overflow occurs, the SRAM writing section11deletes the updating repression flag in the first delay updating repression flag region F1S. As shown inFIG. 3, the SRAM writing section11sets the value of the first delay updating repression flag region F1S to 0 (S101).

Further, when the SRAM writing section11determines that the restoration data is written in the second delay regions D21to D2m, it sets the updating request flags in second delay updating request flag regions F21to F2m, respectively, corresponding to the second delay regions D21to D2mwhere the restoration data is written. At this time, the SRAM writing section11sets the updating repression flag in a second delay updating repression flag region F2S. Further, the SRAM writing section11starts the time counting in the second timer region TIMERD2. When the counting in the second timer region TIMERD2continues for over the predetermined time and overflow occurs, the SRAM writing section11deletes the updating repression flag in the second delay updating repression flag region F2S. As shown inFIG. 4, the SRAM writing section11sets the value of the second delay updating repression flag region F2S to 0 (S102).

The setting of a flag in the SRAM23by the SRAM writing section11and the time counting using the SRAM23(storage of the counted-up timer value) are also processes to be executed by writing data in the SRAM23.

The EEPROM writing section12(second writing section) writes restoration data into the EEPROM3. Concretely, when the updating request flags are set in the non-delay updating request flag regions F01to F0N, the EEPROM writing section12writes the restoration data stored in the non-delay regions D01to D0N corresponding to the non-delay updating request flag regions F01to F0N into the EEPROM3. Further, when the updating request flags are set in the first delay updating request flag regions F11to F1n, and the updating repression flag in the first delay updating repression flag region F1S is deleted, the EEPROM writing section12writes the restoration data stored in the first delay regions D11to D1ncorresponding to the first delay updating request flag regions F11to F1ninto the EEPROM3. Further, when the updating request flags are set in the second delay updating request flag regions F21to F2m, and the updating repression flag in the second delay updating repression flag region F2S is deleted, the EEPROM writing section12writes the restoration data stored in the second delay regions D21to D2mcorresponding to the second delay updating request flag regions F21to F2minto the EEPROM3.

The non-delay regions D01to D0N of the SRAM23at the addresses AS0to AS1are related to regions of the EEPROM3at addresses AE0to AE1, and the EEPROM writing section12writes the restoration data stored in the non-delay regions D01to D0N into the regions of the EEPROM3at the addresses AE0to AE1. Further, the first delay regions D11to D1nof the SRAM23at the addresses AS1to AS2are related to regions of the EEPROM3at addresses AE1to AE2, and the EEPROM writing section12writes the restoration data stored in the first delay regions D11to D1ninto the regions of the EEPROM3at the addresses AE1to AE2. Further, the second delay regions D21to D2mof the SRAM23at the addresses AS2to ASf are related to regions of the EEPROM3at addresses AE2to AEf, and the EEPROM writing section12writes the restoration data stored in the second delay regions D21to D2minto the regions of the EEPROM3at the addresses AE1to AE2.

A process for writing data into the SRAM23is described below with reference to the flowchart shown inFIG. 5. When, for example, the process for writing into the SRAM.23according to an application program is generated, the CPU21(the SRAM writing section11) executes the following process. In this embodiment, since data is written into the SRAM23by a software process in the CPU21, the following process is incorporated as API of OS, library and middleware.

The SRAM writing section11first sets a variable A corresponding to the address of the SRAM23as an address of a writing destination (S1). The SRAM writing section11determines whether a value of the SRAM23at the address (variable) A is equal to data to be written into the SRAM23(S2). That is to say, the SRAM writing section11determines whether data stored in the address A of the SRAM23is the same as data to be written in the SRAM23. When the SRAM writing section11determines that the value of the SRAM23at the addresses A is equal to the data to be written into the SRAM23(S2: Yes), the process is ended. Since the data stored in the address A of the SRAM23is equal to the data to be written into the SRAM23, namely, the data to be stored in the address A of the SRAM23does not change, data does not have to be written.

When the SRAM writing section11determines that the value of the SRAM23at the address A is not equal to the data to be written into the SRAM23(S2: No), it sets the value of the SRAM23at the address A as writing data (S3). That is to say, the SRAM writing section11writes the data into the region corresponding to the address A of the SRAM23.

The SRAM writing section11then determines whether the variable A corresponding to the address of the SRAM23where the data is written is the address AS0or more (S4). When the SRAM writing section11determines that the variable A is not the address AS0or more (A<AS0), namely, restoration unnecessary data is written in the restoration unnecessary region B (S4: No), the process is ended. Since the SRAM writing section11writes the restoration unnecessary data into the restoration unnecessary region B, the process for writing data into the EEPROM3does not have to be executed.

When the SRAM writing section11determines that the variable A is the address AS0or more (S4: Yes), it determines whether the variable A is the address AS1or more (S5). When the SRAM writing section11determines that the variable A is not the address AS1or more (AS0≦A<AS1), namely, restoration data is written into the non-delay regions D01to D0N (S5: No), it calculates a page number corresponding to the variable (address) A, and sets a variable P corresponding to the page number as the calculated page number (S6). The SRAM writing section11sets a value of a non-delay updating request flag region F0P to 1 (S7). That is to say, the SRAM writing section11sets a flag in the non-delay updating request flag region F0P. For example, when the calculated page number is 2, restoration data is written into a page D02(P=2) of the non-delay region, and a flag is set in the non-delay updating request flag region F02(P=2). In such a manner, the SRAM writing section11sets the updating request flags in the non-delay updating request flag regions F01to F0N, respectively, corresponding to the non-delay regions D01to D0N where the restoration data is written.

When the SRAM writing section11determines that the variable A is the address AS1or more (S5: Yes), it determines whether the variable A is the address AS2or more (S8). When the SRAM writing section11determines that the variable A is not the address AS2or more (AS1≦A<AS2), namely, the restoration data is written into the first delay regions D11to D1n(S8: No), it calculates a page number corresponding to the variable (address) A, and sets the variable P corresponding to the page number as the calculated page number (S9). The SRAM writing section11sets a value of a first delay updating request flag region F1P to 1 (S10). That is to say, the SRAM writing section11sets a flag in the first delay updating request flag region F1P. The SRAM writing section11then sets a value of the first delay updating repression flag region F1S to 1 (S11). That is to say, the SRAM writing section11sets a flag in the first delay updating repression flag region F1S. The SRAM writing section11starts the time counting in the first timer region TIMERD1(S12).

When the SRAM writing section11determines that the variable A is the address AS2or more (S8: Yes), it determines whether the variable A is the address ASf or more (S13). When the SRAM writing section11determines that the variable A is not the address ASf or more, namely, the restoration data is written into the second delay regions D21to D2m(S13: No), it calculates a page number corresponding to the variable (address) A, and sets the variable P corresponding to the page number as the calculated page number (S14). The SRAM writing section11sets a value of a second delay updating request flag region F2P to 1 (S15). That is to say, the SRAM writing section11sets a flag in the second delay updating request flag region F2P. The SRAM writing section11then sets a value of the second delay updating repression flag region F2S to 1 (S16). That is to say, the SRAM writing section11sets a flag in the second delay updating repression flag region F2S. The SRAM writing section11starts the time counting in the second timer region TIMERD2. When the SRAM writing section11determines that the variable A is the address ASf or more, namely, restoration unnecessary data is written into the restoration unnecessary region B (S13: Yes), the process is ended.

The process for calculating a page number (S6, S9, and S14inFIG. 5) is described below with reference to the flowchart shown inFIG. 6. The SRAM writing section11first calculates offset (S21). When the restoration data is written in the non-delay regions D01to D0N (S6), the SRAM writing section11calculates A-AS0. Further, when the restoration data is written into the first delay regions D11to D1n(S9), the SRAM writing section11calculates A-AS1. Further, when the restoration data is written into the second delay regions D21to D2m(S14), the SRAM writing section11calculates A-AS2. The SRAM writing section11divides the calculated offset by a page size of one page, and sets the divided value as the variable p (S22). For example, when the offset is 50 bytes and the page size is 32, 50/32 (=1.5625) is calculated. The number obtained by adding 1 to an integer part of the variable p is set as the page number P (S23). For example, when the variable p=50/32 (=1.5625), 1+1=2 is set as the page number P. In this example, restoration data is written in page2(for example, a page D02in the non-delay region). A function Int(p) shown inFIG. 6is an arithmetic function that returns an integer part of p.

The process for writing restoration data into the EEPROM3is described based on a flowchart shown inFIG. 7. The following process is executed by the CPU21(the EEPROM writing section12) periodically (1 to a few seconds) as a task different from the processes shown inFIG. 5andFIG. 6. The EEPROM writing section12sets a variable i corresponding to the page number to 1 (S31). The EEPROM writing section12determines whether the variable i corresponding to the page number is the number of pages N or less in the non-delay regions D01to D0N (S32). When the EEPROM writing section12determines that the variable i is the number of pages N or less in the non-delay regions D01to D0N (S32: Yes), it checks the non-delay updating request flag region F0i(S33). The EEPROM writing section12sets the variables i to i+1 (S34). This is because a determination is made whether a next page number is the number of pages N or less in D01to D0N at the next step S32. Further, this is because, the non-delay updating request flag region F0icorresponding to the next page number is checked at the next step S33.

While the determination is made that the variable i is the number of pages N or less (S32: Yes), the EEPROM writing section12repeats steps S33and S34. When the EEPROM writing section12determines that the variable i is not the number of pages N or less in the non-delay regions D01to D0N (S32: No), it checks all the non-delay updating request flag regions F01to F0N. For this reason, the EEPROM writing section12determines whether the value of the first delay updating repression flag region F1S is 0 (S35). That is to say, the EEPROM writing section12determines whether a flag is set in the first delay updating repression flag region F1S. When the EEPROM writing section12determines that a value of the first delay region updating repression flag region F1S is 0, namely, a flag is not set in the first delay updating repression flag region F1S (S35: Yes), it sets the variable i corresponding to the page number to 1 (S36). The EEPROM writing section12determines whether the variable i corresponding to the page number is the number of pages n or less in the first delay regions D11to D1n(S37). When the EEPROM writing section12determines that the variable i is the number of pages n or less in the first delay regions D11to D1n(S37: Yes), it checks a first delay updating request flag region F1i(S38). The EEPROM writing section12sets the variables i to i+1 (S39).

While the EEPROM writing section12determines that the variable i is the number of pages n or less (S37: Yes), it repeats the steps S38and S39. When the EEPROM writing section12determines that the variable i is not the number of pages n or less in the first delay regions D11to D1n(S37: No), it checks all the first delay updating request flag regions F11to F1n. For this reason, the EEPROM writing section12determines whether the value of the second delay updating repression flag region F2S is 0 (S40). That is to say, the EEPROM writing section12determines whether a flag is set in the second delay updating repression flag region F2S. Further, when the EEPROM writing section12determines that the value of the first delay region updating repression flag region F1S is not 0, namely, a flag is set in the first delay updating repression flag region F1S (S35: No), it executes a step S40without executing steps S37to S39. That is to say, since a flag is set in the first delay updating repression flag region F1S, the EEPROM writing section12does not check the first delay updating request flag regions F11to F1n.

When the EEPROM writing section12determines that a value of a second delay updating repression flag region F1S is 0, namely, a flag is not set in the second delay updating repression flag region F1S (S40: Yes), it sets the variable i corresponding to the page number to 1 (S41). The EEPROM writing section12determines whether the variable i corresponding to the page number is a page number m or less in the second delay regions D21to D2m(S42). When the EEPROM writing section12determines that the variable i is the number of pages m or less in the second delay regions D21to D2m(S42: Yes), it checks a second delay updating request flag region F2i(S43). The EEPROM writing section12sets the variables i to i+1 (S44).

While the EEPROM writing section12determines that the variable i is the number of pages m or less (S42: Yes), it repeats steps S43and S44. When the EEPROM writing section12determines that the variable i is not the number of pages m or less in the first delay regions D21to D2m(S42: No), it checks all the second delay updating request flag regions F21to F2m. For this reason, the process is ended. Further, when the EEPROM writing section12determines that a value of a second delay updating repression flag region F2S is not 0, namely, a flag is set in the second delay updating repression flag region F2S (S40: No), it executes the step S40without executing the steps S42to S44. That is to say, since a flag is set in the second delay updating repression flag region F2S, the EEPROM writing section12does not check the second delay updating request flag regions F21to F2m.

The process for checking the non-delay updating request flag regions F01to F0N (S33inFIG. 7) is described with reference to a flowchart shown inFIG. 8. The EEPROM writing section12sets the variable p as the page number (i at S33ofFIG. 7) (S51). The EEPROM writing section12determines whether the value of the non-delay updating request flag region F0pis (S52). That is to say, the EEPROM writing section12determines whether a flag is set in the non-delay updating request flag region F0p. When the EEPROM writing section12determines that the value of the non-delay updating request flag region F0pis not 1, namely, a flag is not set in the non-delay updating request flag region F0p(S52: No), it does not have to write the restoration data stored in the non-delay region D0pinto the EEPROM3. For this reason, the process is ended.

When the EEPROM writing section12determines that the value of the non-delay updating request flag region F0pis 1, namely, a flag is set in the non-delay updating request flag region F0p(S52: Yes), it sets the number obtained by multiplying the number obtained by subtracting 1 from the variable p corresponding to the page number by the page size as a variable a (S53). The variable a corresponds to the number of bytes from the address AS0of the SRAM23to a page number (p−1). For example, when the page number is 3 and the page size is 32 bytes, the number of bytes up to the page number 2 is 64 bytes. The EEPROM writing section12sets the variable i corresponding to the number of bytes to 0 (S54). The EEPROM writing section12determines whether the variable i corresponding to the number of bytes is smaller than the page size (S55). When the EEPROM writing section12determines that the variable i is smaller than the page size (S55: Yes), it sets a value of the EEPROM3at the address AE0+a+i as a value of the SRAM23at the address AS0+a+i (S56). That is to say, the EEPROM writing section12writes restoration data stored in the region of the SRAM23at the address AS0+a+i into a region of the EEPROM3at the address AE0+a+i. For example, when the page number is 3 and the page size is 32 bytes in the first process, a value of the EEPROM3at the address AE0+64+0 is a value of the SRAM23at an address AS0+64+0. The EEPROM writing section12then sets the variables i to i+1 (S57).

While the EEPROM writing section12determines that the variable i is smaller than the page size (S55: Yes), it repeats the steps S55to S57. Since the variable i increases one by one, for example, when the page number is 3 and the page size is 32 bytes, a value of the EEPROM3at an address AE0+64+(0 to 32) is a value of the SRAM23at an address AS0+64+(0 to 32). That is to say, the restoration data stored in the non-delay region D03for one page of the page number 3 is written into the EEPROM3.

When the EEPROM writing section12determines that the variable i is not smaller than the page size (S55: No), the process is ended. In such a manner, the EEPROM writing section12writes the restoration data for one page stored in the non-delay region D0pinto the EEPROM3.

The process for checking the first delay updating request flag regions F11to F1n(S38inFIG. 7) is described below with reference to a flowchart shown inFIG. 9. The EEPROM writing section12sets the variable p as the page number (i at S38inFIG. 7) (S61). The EEPROM writing section12then determines whether a value of a first delay updating request flag region F1pis 1 (S62). That is to say, the EEPROM writing section12determines whether a flag is set in the first delay updating request flag region F1p. When the EEPROM writing section12determines that the value of the first delay updating request flag region F1pis not 1, namely, a flag is not set in the first delay updating request flag region F1p(S62: No), it does not have to write the restoration data stored in the first delay region Dip into the EEPROM3. For this reason, the process is ended.

When the EEPROM writing section12determines that the value of the first delay updating request flag region F1pis 1, namely, a flag is set in the first delay updating request flag region F1p(S62: Yes), it sets the number obtained by multiplying the number obtained by subtracting 1 from the variable p corresponding to the page number by the page size as the variable a (S63). The EEPROM writing section12then sets the variable i corresponding to the number of bytes to 0 (S64). The EEPROM writing section12then determines whether the variable i corresponding to the number of bytes is smaller than the page size (S65). When the EEPROM writing section12determines that the variable i is smaller than the page size (S65: Yes), it sets a value of the EEPROM3at an address AE1+a+i as a value of the SRAM.23at an address AS1+a+i (S66). That is to say, the EEPROM writing section12writes restoration data stored in the region of the SRAM23at the address AS1+a+i into a region of the EEPROM3at the address AE1+a+i. The EEPROM writing section12then sets the variable i to i+1 (S67). While the EEPROM writing section12determines that the variable i is smaller than the page size (S65: Yes), it repeats the steps S65to S67. When the EEPROM writing section12determines that the variable i is not smaller than the page size (S65: No), the process is ended. In such a manner, the EEPROM writing section12writes the restoration data for one page stored in the first delay region Dip into the EEPROM3.

The process for checking the second delay updating request flag regions F21to F2m(S43inFIG. 7) is described below with reference to a flowchart shown inFIG. 10. The EEPROM writing section12sets the variable p as the page number (i at S43inFIG. 7) (S71). The EEPROM writing section12then determines whether a value of a second delay updating request flag region F2pis 1 (S72). That is to say, the EEPROM writing section12determines whether a flag is set in the second delay updating request flag region F2p. When the EEPROM writing section12determines that the value of the second delay updating request flag region F2pis not 1, namely, a flag is not set in the second delay updating request flag region F2p(S72: No), it does not have to write restoration data stored in a second delay region D2pinto the EEPROM3. For this reason, the process is ended.

When the EEPROM writing section12determines that the value of the second delay updating request flag region F2pis 1, namely, a flag is set in the second delay updating request flag region F2p(S72: Yes), it sets a number obtained by multiplying a number obtained by subtracting 1 from the variable p corresponding to the page number by the page size, as the variable a (S73). The EEPROM writing section12then sets the variable i corresponding to the number of bytes to 0 (S74). The EEPROM writing section12then determines whether the variable i corresponding to the number of bytes is smaller than the page size (S75). When the EEPROM writing section12determines that the variable i is smaller than the page size (S75: Yes), it sets a value of the EEPROM3at an address AE2+a+i as a value of the SRAM23at an address AS2+a+i (S76). That is to say, the EEPROM writing section12writes restoration data stored in the region of the SRAM23at the address AS2+a+i into the region of the EEPROM3at the address AE2+a+i. The EEPROM writing section12then sets the variable i to i+1 (S77). While the EEPROM writing section12determines that the variable i is smaller than the page size (S75: Yes), it repeats the steps S75to S77. When the EEPROM writing section12determines that that the variable i is not smaller than the page size (S76: No), the process is ended. In such a manner, the EEPROM writing section12writes the restoration data for one page stored in the second delay region D2pinto the EEPROM3.

This embodiment is compared with a conventional technique.

For example, the EEPROM is constituted as follows.

Page size (the number of bytes for one page): 32 bytes

The number of pages: 256 pages (=8192/32)

An SRAM includes a non-delay region, a first delay region, a second delay region, a first timer region, and a second timer region. One timer region requires 4 bytes.

In the case of the conventional technique shown inFIG. 11, a region where restoration data is copied requires 8192 bytes. Further, two timer regions require 8 bytes (=4×2). Therefore, besides the non-delay region, the first delay region, and the second delay region, totally 8200 bytes (=8192+8) are required.

Further, in the case of the conventional technique where a checksum is stored in the SRAM, a checksum is calculated in page unit. As to a checksum of the other one of two dimensions, a checksum of values at the same offset addresses on one page is calculated, and this checksum is calculated for all the pages. In this case, 288 bytes (=256+32) are necessary for storing the checksums. Further, two timer regions require 8 bytes (=4×2). Therefore, besides the non-delay region, the first delay region, and the second delay region, totally 296 bytes (=288+8) are necessary.

In the present embodiment, when the EEPROM is 256 pages, 256 bits=32 bytes are necessary for the non-delay updating request flag region, the first delay updating request flag region, and the second delay updating request flag region. Further, two timer regions require 8 bytes (=4×2). Therefore, besides the non-delay region, the first delay region, and the second delay region, totally 40 bytes (=32+8) are necessary. In comparison with the conventional technique, the capacity of the SRAM necessary for writing restoration data into the EEPROM is the smallest.

As described above, in the present embodiment, the SRAM23is provided with the non-delay updating request flag regions F01to F0N where the updating request flag is set when restoration data is stored in the non-delay regions D01to D0N. Further, when a flag is set in the non-delay updating request flag regions F01to F0N, the EEPROM writing section12writes the restoration data stored in the non-delay regions D01to D0N corresponding to the non-delay updating request flag regions F01to F0N into the EEPROM3. Therefore, since a checksum is not calculated unlike the conventional technique, restoration data can be written into the EEPROM3by a simple process. The simplicity of the process that is simpler than the conventional technique can be understood also by comparingFIG. 2illustrating the process in the present embodiment withFIG. 11illustrating the conventional process.

Further, when a flag is set, “1” that is information with less data amount (1 bit) is stored in the non-delay updating request flag regions F01to F0N. For this reason, a copy of restoration data and a checksum are not stored in the SRAM23unlike the conventional technique. As a result, restoration data can be written in the SRAM23without using a large capacity of the SRAM23.

Further, in the present embodiment, when an updating request flag is set in the delay updating request flag regions F11to F2mand an updating repression flag in the delay updating repression flag regions F1S and F2S is deleted, namely, the counting in the timer regions TIMERD1and TIMERD2continues for over the predetermined time, the EEPROM writing section12writes restoration data stored in the delay regions D11to D2mcorresponding to the delay updating request flag regions F11to F2minto the EEPROM3. That is to say, the EEPROM writing section12performs the delay writing. For this reason, the number of times of writing into the EEPROM3is repressed, and a life of the EEPROM3can be lengthened.

The above has described the embodiment of the present invention, but embodiments applicable to the present invention are not limited to the above embodiment, and thus as illustrated various modifications can be made suitably within the scope of the gist of the present invention.

The above embodiment illustrates the SRAM as the volatile memory. Not limited to this, the volatile memory may be a DRAM (Dynamic Random Access Memory) or the like. Further, the EEPROM is illustrated as the nonvolatile memory. Not limited to this, the nonvolatile memory may be a flash memory or the like.

In the above embodiment, data is written into the SRAM23and the EEPROM3by the CPU21according to the program (software process). Not limited to this, data may be written into the SRAM23and EEPROM3by hardware other than the CPU.

In the above embodiment, when a flag is set in the delay updating repression flag regions F1S and F2S, the EEPROM writing section12does not write the restoration data stored in the delay regions D11to D2minto the EEPROM3. Not limited to this, the delay updating repression flag regions F1S and F2S do not have to be provided in the SRAM23. In this case, the EEPROM writing section12does not write the restoration data stored in the delay regions D11to D2minto the EEPROM3until the timer regions TIMERD1and TIMERD2overflow. When the timer regions TIMERD1and TIMERD2overflow, namely, the counting in the timer regions TIMERD1and TIMERD2continues for over the predetermined time, the restoration data stored in the delay regions D11to D2mmay be written into the EEPROM3.

The above embodiment has described the AV amplifier1as the electronic device to which the present invention is applied. The present invention is not limited to the AV amplifier, and it may be a personal computer or the like as long as the electronic device stores restoration data, which should be stored in the volatile memory even when power supply to a self device is shut off, and writes the restoration data into the nonvolatile memory.

The present invention can be applied to electronic devices such as an AV amplifier and a personal computer.