Display device and a manufacturing method thereof

A display device includes a substrate, first through fourth metal wires, first and second insulating layers, and a compensation pattern. The first metal wire is positioned on the substrate and extends in a first direction. The first insulating layer is positioned on the first metal wire and the substrate. The second metal wire is positioned on the first insulating layer, extends in the first direction, and is adjacent to the first metal wire. The second insulating layer is positioned on the first insulating layer and the second metal wire. The compensation pattern is positioned on the second insulating layer and is disposed between the first metal wire and the second metal wire. The third metal wire and the fourth metal wire are positioned on the second insulating layer and extend in a second direction that is different from the first direction.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims priority under 35 U.S.C. § 119 to the Korean Patent Application No. 10-2015-0160501 filed in the Korean Intellectual Property Office on Nov. 16, 2015, the disclosure of which is incorporated by reference herein in its entirety.

TECHNICAL FIELD

Exemplary embodiments of the present invention relate generally to a display device and a manufacturing method thereof.

DISCUSSION OF RELATED ART

In general, a display device includes a plurality of pixels as units displaying an image, and a plurality of drivers transmitting signals to drive the plurality of pixels. The drivers include a data driver applying a data voltage to a pixel, and a scan driver applying a gate signal. The scan driver and the data driver can be mounted to a printed circuit board (PCB) as a chip and are connected to the display panel, or are directly mounted to the display panel. However a scan driver that does not require high mobility of the thin film transistor channel may use a structure in which the scan driver is not formed as an additional chip but is instead integrated with the display panel.

Scan drivers integrated in the display panel include a plurality of wires. These wires may be formed in the same layer as a wire included in a thin film transistor in a pixel. The wires of the drivers may be adjacent to each other, and an upper surface of an insulating layer may not be flat. Accordingly, a groove may form between the adjacent wires.

SUMMARY

According to an exemplary embodiment of the inventive concept a display device includes a substrate, a first metal wire, a first insulating layer, a second metal wire, a second insulating layer, a compensation pattern, and a third metal wire and a fourth metal wire. The first metal wire is positioned on the substrate and extends in a first direction. The first insulating layer is positioned on the first metal wire and the substrate. The second metal wire is positioned on the first insulating layer and extends in the first direction. The second insulating layer is positioned on the first insulating layer, the second metal wire, and adjacent to the first metal wire. The compensation pattern is positioned on the second insulating layer and disposed between the first metal wire and the second metal wire. The third metal wire and a fourth metal wire is positioned on the second insulating layer and extending in a second direction that is different from the first direction.

In an exemplary embodiment of the inventive concept, the first insulating layer and the second insulating layer may be made of an inorganic insulating material.

In an exemplary embodiment of the inventive concept, a groove may be disposed in the second insulating layer and positioned between the first metal wire and the second metal wire may be further included, and the compensation pattern may be positioned in the groove.

In an exemplary embodiment of the inventive concept, the compensation pattern may extend in the first direction.

In an exemplary embodiment of the inventive concept, the compensation pattern may be made of a material having a different etching rate from that of the second insulating layer.

In an exemplary embodiment of the inventive concept, the compensation pattern may be made of a metal.

In an exemplary embodiment of the inventive concept, the compensation pattern may be made of the same material as the third metal wire and the fourth metal wire.

In an exemplary embodiment of the inventive concept, a thickness of the compensation pattern may be thinner than the thickness of the third metal wire and the fourth metal wire.

In an exemplary embodiment of the inventive concept, a third insulating layer positioned on the second insulating layer and the compensation pattern may be further included, and the third metal wire and the fourth metal wire may be positioned on the third insulating layer.

In an exemplary embodiment of the inventive concept, the thickness of the second insulating layer may be thinner than the thickness of the third insulating layer.

In an exemplary embodiment of the inventive concept, the compensation pattern may be made of a non-metal.

In an exemplary embodiment of the inventive concept, the third metal wire and the fourth metal wire may be positioned directly on the compensation pattern and the second insulating layer.

In an exemplary embodiment of the inventive concept, the display device may include a display region and a non-display region positioned on the edge of the display region, and the first metal wire, the second metal wire, the compensation pattern, the third metal wire, and the fourth metal wire may be positioned in the non-display region.

In an exemplary embodiment of the inventive concept, the display device may include a first semiconductor, a first gate electrode and a storage electrode. The first semiconductor may be positioned on the substrate. The first gate electrode may overlap the first semiconductor. The storage electrode may overlap the first gate electrode. The first semiconductor, the first gate electrode, and the storage electrode may be positioned in the display region. The first insulating layer may be positioned between the first gate electrode and the storage electrode. The first gate electrode may be positioned in a same first layer as the first metal wire. The storage electrode is positioned in a same second layer as the second metal wire.

In an exemplary embodiment of the inventive concept, the display device may include a second semiconductor, a second gate electrode, a data connecting member, a pixel electrode, an organic emission layer, and a common electrode. The second semiconductor may be positioned on the substrate. The second gate electrode may be positioned on the second semiconductor. The data connecting member may be connected to the second semiconductor. The pixel electrode may be connected to the data connecting member. The organic emission layer may be positioned on the pixel electrode. The common electrode may be positioned on the organic emission layer. The second semiconductor, the second gate electrode, the data connecting member, the pixel electrode, the organic emission layer, and the common electrode may be positioned in the display region. The first insulating layer and the second insulating layer may be positioned between the second gate electrode and the data connecting member. The second gate electrode may be positioned in the same first layer as the first metal wire. The data connecting member may be positioned in a same second layer as the third metal wire and the fourth metal wire.

According to an exemplary embodiment of the inventive concept, a method of manufacturing a display device includes forming a first metal wire extending in a first direction on a substrate. A first insulating layer is formed on the first metal wire and the substrate. A second metal wire extending in the first direction is formed on the first insulating layer, and adjacent to the first metal wire. A second insulating layer is formed on the first insulating layer and the second metal wire. A compensation layer is deposited on an entire surface of the second insulating layer. The entire surface of the compensation layer is etched. A third metal wire and a fourth metal wire extending in a second direction different from the first direction is formed on the second insulating layer. The second insulating layer is formed in a groove positioned between the first metal wire and the second metal wire. In the etching of the entire surface of the compensation layer, the compensation pattern remains in the groove.

In an exemplary embodiment of the inventive concept, the first insulating layer and the second insulating layer may be made of an inorganic insulating material.

In an exemplary embodiment of the inventive concept, the compensation pattern may be made of a material having a different etching rate from that of the second insulating layer.

In an exemplary embodiment of the inventive concept, the method may further include forming a third insulating layer on the second insulating layer and the compensation pattern, and the compensation pattern may be made of a metal.

In an exemplary embodiment of the inventive concept, the compensation pattern may be made of a non-metal.

According to an exemplary embodiment of the inventive concept, a display device includes a substrate, a first insulating layer, a first and second groove, a first and second compensation pattern, a first metal wire, and a second insulating layer. The first insulating layer is positioned on the substrate. The first and second grooves are disposed in the first insulating layer and extending in a first direction. The first and second compensation patterns are positioned in the first and second grooves. The first metal wire overlaps the first insulating layer and the first compensation pattern and extends in the first direction. The second insulating layer is positioned on the first insulating layer, the second compensation pattern and the first metal wire.

In an exemplary embodiment of the inventive concept, the display device may include a display region and a non-display region. The first and second compensation pattern and the first metal wire may be positioned in the non-display region.

In an exemplary embodiment of the inventive concept, a thickness of the first and second compensation patterns corresponds to a height of the first insulating layer.

In an exemplary embodiment of the inventive concept, the first and second compensation patterns have a different etching rate from the first insulating layer.

In an exemplary embodiment of the inventive concept, an upper surface of the second insulating layer is substantially flat.

DETAILED DESCRIPTION

A display device according to an exemplary embodiment of the inventive concept will be described with reference toFIG. 1.

FIG. 1is a layout view of a display device according to an exemplary embodiment of the inventive concept.

The display device according to an exemplary embodiment includes a display region DR displaying an image, and a non-display region NR positioned on an edge of the display region DR. A plurality of pixels is disposed in the display region DR. A luminance is controlled for each pixel to display the image. A plurality of drivers driving the plurality of pixels is disposed in the non-display region NR. Since the non-display region NR does not display the image, the non-display region NR may be covered by a light blocking member.

The non-display region NR of the display device according to an exemplary embodiment of the inventive concept will be described with reference toFIG. 2andFIG. 3.

FIG. 2is a layout view of a non-display region of a display device according to an exemplary embodiment of the inventive concept, andFIG. 3is a cross-sectional view of a non-display region of a display device according to an exemplary embodiment taken along lines III-III′, III′-III″, and III″-III′″ ofFIG. 2.

As shown inFIG. 2andFIG. 3, the display device according to an exemplary embodiment includes a substrate110and a first metal wire510positioned on the substrate110.

The substrate110may be made of glass, plastic, or the like. A buffer layer120may be further formed on the substrate110. The buffer layer120may be made of an inorganic insulating material such as a silicon nitride (SiNx) and/or a silicon oxide (SiOx). A first gate insulating layer141may be further formed on the buffer layer120. The first gate insulating layer141may be made of the inorganic insulating material such as a silicon nitride (SiNx) and/or a silicon oxide (SiOx).

The first metal wire510may be disposed on the first gate insulating layer141. The first metal wire510may extend in a first direction. For example, the first direction may be a horizontal direction.

A second gate insulating layer142may be disposed on the first metal wire510and the first gate insulating layer141. The second gate insulating layer142may be made of the inorganic insulating material such as a silicon nitride (SiNx) and/or a silicon oxide (SiOx).

A second metal wire520may be disposed on the second gate insulating layer142. The second metal wire520may extend in the first direction parallel to the first metal wire510. The second metal wire520is positioned to be close to the first metal wire510.

A first interlayer insulating layer161may be disposed on the second metal wire520and the second gate insulating layer142. The first interlayer insulating layer161may be made of the inorganic insulating material such as a silicon nitride (SiNx) and/or a silicon oxide (SiOx). The first interlayer insulating layer161is formed with a groove165. The groove165may be disposed between the first metal wire510and the second metal wire520in a plan view. The groove165is formed along the first direction parallel to the first metal wire510and the second metal wire520.

A compensation pattern600may be positioned on the first interlayer insulating layer161. The compensation pattern600may be positioned in the groove165. The compensation pattern600may extend in the first direction parallel to the first metal wire510and the second metal wire520. The compensation pattern600may have a thickness corresponding to a depth of the groove165. The compensation pattern600may be made of a material having a different etching ratio from that of the first interlayer insulating layer161. For example, the compensation pattern600may be made of a metal.

A second interlayer insulating layer162may be positioned on the compensation pattern600and the first interlayer insulating layer161. The second interlayer insulating layer162may be made of the inorganic insulating material such as a silicon nitride (SiNx) and/or a silicon oxide (SiOx). The first interlayer insulating layer161may be thinner than the second interlayer insulating layer162.

A third metal wire710and a fourth metal wire720may be positioned on the second interlayer insulating layer162. The third metal wire710and the fourth metal wire720may extend in the second direction that is different from the first direction. The second direction may be a direction that is perpendicular to the first direction. For example, the second direction may be a vertical direction. The third metal wire710and the fourth metal wire720may cross the first metal wire510and the second metal wire520in a plan view. The third metal wire710and the fourth metal wire720may be adjacent.

The compensation pattern600may be made of the same material as the third metal wire710and the fourth metal wire720. The compensation pattern600may be positioned on a different layer from that of the third metal wire710and the fourth metal wire720. The thickness of the compensation pattern600may be thinner than the thickness of the third metal wire710and the fourth metal wire720.

A passivation layer180may be positioned on the third metal wire710, the fourth metal wire720, and the second interlayer insulating layer162.

The first metal wire510, the second metal wire520, the compensation pattern600, the third metal wire710, and the fourth metal wire720are positioned in the non-display region NR. A driver may include the first metal wire510, the second metal wire520, the third metal wire710, and the fourth metal wire720. Signals to drive a pixel are applied to the first metal wire510, the second metal wire520, the third metal wire710, and the fourth metal wire720. For example, a driving voltage (ELVDD), a common voltage (ELVSS), and the like may be applied.

In an exemplary embodiment of the inventive concept, the first metal wire510and the second metal wire520may be adjacent and extend in a direction parallel to each other. The first interlayer insulating layer161made of the inorganic insulating material may be positioned on the first metal wire510and the second metal wire520. Accordingly, the upper surface of the first interlayer insulating layer161is not flat and the groove165is formed between the first metal wire510and the second metal wire520. The compensation pattern600is formed in the groove165, and the second interlayer insulating layer162is formed on the compensation pattern600and the first interlayer insulating layer161. Since the groove165is filled by the compensation pattern600, the upper surface of the second interlayer insulating layer162may be substantially flat.

The manufacturing method of the display device according to an exemplary embodiment of the inventive concept will be described with reference toFIG. 4toFIG. 7.

FIG. 4toFIG. 7are process cross-sectional views of a manufacturing method of a display device according to an exemplary embodiment of the inventive concept.FIG. 4toFIG. 7show the manufacturing method of the non-display region of the display device according to an exemplary embodiment. The display region may also be manufactured together therewith when manufacturing the non-display region.

As shown inFIG. 4, the inorganic insulating material such as a silicon nitride (SiNx) and/or a silicon oxide (SiOx) is deposited on the substrate110to form the buffer layer120. The inorganic insulating material such as a silicon nitride (SiNx) and/or a silicon oxide (SiOx) is deposited on the buffer layer120to form the first gate insulating layer141.

A metal material is deposited and patterned on the first gate insulating layer141to form the first metal wire510. The first metal wire510may extend in the first direction. The inorganic insulating material such as a silicon nitride (SiNx) and/or a silicon oxide (SiOx) is deposited on the first metal wire510and the first gate insulating layer141to form the second gate insulating layer142. A metal material is deposited and patterned on the second gate insulating layer142to form the second metal wire520. The second metal wire520may extend in the first direction parallel to the first metal wire510.

The inorganic insulating material such as a silicon nitride (SiNx) and/or a silicon oxide (SiOx) is deposited on the second metal wire520and the second gate insulating layer142to form the first interlayer insulating layer161. The first interlayer insulating layer161includes the groove165. The groove165may be positioned between the first metal wire510and the second metal wire520in a plan view.

As shown inFIG. 5, a compensation layer650may be deposited on the entire surface of the first interlayer insulating layer161. The compensation layer650may be made of material having a different etching rate from that of the first interlayer insulating layer161. For example, the compensation layer650may be made of the metal material. The compensation layer650fills the groove165.

As shown inFIG. 6, the substantially all of a surface of the compensation layer650may be etched. When substantially all of the surface of the compensation layer650is etched without a separate mask, most of the compensation layer650is removed. However, the compensation layer650positioned in the groove165remains, forming the compensation pattern600.

Since the compensation layer650is made of the material having the different etching rate from that of the first interlayer insulating layer161, the portions of the first interlayer insulating layer161are not etched during the etching of the compensation layer650.

As shown inFIG. 7, the inorganic insulating material such as silicon nitride (SiNx) and/or a silicon oxide (SiOx) is deposited on the compensation pattern600and the first interlayer insulating layer161to form the second interlayer insulating layer162. The first interlayer insulating layer161may be thinner than the second interlayer insulating layer162.

Since the first interlayer insulating layer161includes the groove165, the upper surface of the first interlayer insulating layer161is not flat. Since the compensation pattern600is filled inside the groove165of the first interlayer insulating layer161, the upper surface of the second interlayer insulating layer162formed on the first interlayer insulating layer161and the compensation pattern600may be substantially flat.

The metal material is deposited and patterned on the second interlayer insulating layer162to form the third metal wire710and the fourth metal wire720. The third metal wire710and the fourth metal wire720may extend in the second direction that is different from the first direction. The second direction may be a direction that is perpendicular to the first direction.

When the compensation pattern600is made of the metal material, the compensation pattern600may be made of the same material as the third metal wire710and the fourth metal wire720. The compensation pattern600may be thinner than the third metal wire710and the fourth metal wire720.

The passivation layer180is formed on the third metal wire710, the fourth metal wire720, and the second interlayer insulating layer162.

The non-display region of the display device according to an exemplary embodiment of the inventive concept will be described with reference toFIG. 8.

The display device according to an exemplary embodiment of the inventive concept shown inFIG. 8is similar to the display devices according to exemplary embodiments shown inFIG. 1toFIG. 3and the description thereof is omitted. In the present exemplary embodiment of the inventive concept, the second interlayer insulating layer is omitted.

FIG. 8is a cross-sectional view of a non-display region of a display device according to an exemplary embodiment of the inventive concept.

As shown inFIG. 8, the first metal wire510is positioned on the substrate110, the second gate insulating layer142is positioned on the first metal wire510and the first gate insulating layer141. The second metal wire520is positioned on the second gate insulating layer142. The first interlayer insulating layer161is positioned on the second metal wire520and the second gate insulating layer142. The compensation pattern600is positioned in the groove165of the first interlayer insulating layer161.

The compensation pattern600may be made of the material having the different etching rate from that of the first interlayer insulating layer161. In this case, the compensation pattern600may be made of the non-metal material.

In the previous exemplary embodiment (e.g.,FIG. 7), the second interlayer insulating layer is positioned on the compensation pattern600and the first interlayer insulating layer161. According to the present embodiment, the second interlayer insulating layer is omitted. The third metal wire710and the fourth metal wire720are positioned directly on the compensation pattern600and the first interlayer insulating layer161. In an exemplary embodiment of the inventive concept, the compensation pattern600is formed using a metal material, an additional insulating layer may be formed on the compensation pattern600to prevent the compensation pattern600from short-circuiting the third metal wire710and the fourth metal wire720. In an exemplary embodiment of the inventive concept, the compensation pattern600may be made using a non-metal material, and no additional insulating layer is needed on the compensation pattern600. In this exemplary embodiment the compensation pattern600does not short-circuit the third metal wire710and the fourth metal wire720.

The non-display region of the display device according to an exemplary embodiment of the inventive concept will be described with reference toFIG. 9andFIG. 10.

FIG. 9is a layout view of a non-display region of a display device according to an exemplary embodiment of the inventive concept, andFIG. 10is a cross-sectional view of a non-display region of a display device according to exemplary embodiment taken along lines X-X′, X′-X″, and X″-X′″ ofFIG. 9.

As shown inFIG. 9andFIG. 10, in the display device according to an exemplary embodiment of the inventive concept, the first metal wire510is positioned on the substrate110, the second gate insulating layer142is positioned on the first metal wire510and the first gate insulating layer141, and the second metal wire520is positioned on the second gate insulating layer142.

The first interlayer insulating layer161is positioned on the second metal wire520and the second gate insulating layer142. The first interlayer insulating layer161forms the groove165between the first metal wire510and the second metal wire520. The groove165is formed along the first direction parallel to the first metal wire510and the second metal wire520.

The third metal wire710and the fourth metal wire720are positioned on the first interlayer insulating layer161. The metal material is deposited and patterned on the first interlayer insulating layer161to form the third metal wire710and the fourth metal wire720. In this case, the metal material positioned in the groove165is not removed in the etching process, but remains, forming a residue pattern750. The residue pattern750may connect the third metal wire710and the fourth metal wire720and may short the third metal wire710and the fourth metal wire720. The third metal wire710and the fourth metal wire720may transmit different signals, so when the third metal wire710and the fourth metal wire720are shorted, the driver may not operate normally.

In an exemplary embodiment of the inventive concept, the compensation pattern is formed to prevent the third metal wire710and the fourth metal wire720from being short-circuited. In the present exemplary embodiment, the first interlayer insulating layer161may contain multiple grooves165. The compensation pattern600is positioned in one of the grooves165of the first interlayer insulating layer161. As the compensation pattern600is positioned in the groove165of the first interlayer insulating layer161, the residue pattern750may be prevented from being formed in the groove165or the residue pattern750may be removed from the groove165. For example, the residue pattern750may be removed during etching. Accordingly, without a residue pattern750in the groove165the third metal wire710and the fourth metal wire720positioned on the first interlayer insulating layer161, may not be short-circuited.

The display region of the display device according to an exemplary embodiment of the inventive concept will be described with reference toFIG. 11toFIG. 15.

FIG. 11is an equivalent circuit diagram of one pixel of a display region of a display device according to an exemplary embodiment of the inventive concept. The display device according to an exemplary embodiment may be made of an organic light emitting diode display.

As shown inFIG. 11, the display device according to an exemplary embodiment includes a plurality of signal lines151,152,153,171,172, and192and a plurality of pixels PX connected to the plurality of signal lines and arranged substantially as a matrix.

Each pixel PX includes a plurality of transistors T1, T2, T3, T4, T5, and T6connected to the plurality of signal lines151,152,153,171,172, and192, a storage capacitor Cst, and an organic light emitting diode OLD.

The transistors T1, T2, T3, T4, T5, and T6include a driving transistor T1, a switching transistor T2, a compensation transistor T3, an initialization transistor T4, an operation control transistor T5, and a light emission control transistor T6. The signal lines151,152,153,171,172, and192include a scan line151transmitting a scan signal Sn, a previous scan line152transmitting a previous scan signal S(n−1) to the initialization transistor T4, a light emission control line153transmitting a light emission control signal EM to the operation control transistor T5and the light emission control transistor T6, a data line171crossing the scan line151and transmitting a data signal Dm, a driving voltage line172transmitting a driving voltage ELVDD and formed to be almost parallel to the data line171, and an initialization voltage line192transmitting an initialization voltage Vint initializing the driving transistor T1.

A gate electrode G1of the driving transistor T1is connected to one end Cst1of the storage capacitor Cst, a source electrode S1of the driving transistor T1is connected with the driving voltage line172via the operation control transistor T5. A drain electrode D1of the driving transistor T1is electrically connected with an anode of the organic light emitting diode OLD via the emission control transistor T6. The driving transistor T1receives the data signal Dm according to a switching operation of the switching transistor T2to supply a driving current Id to the organic light emitting diode OLD.

A gate electrode G2of the switching transistor T2is connected with the scan line151, a source electrode S2of the switching transistor T2is connected with the data line171, and a drain electrode D2of the switching transistor T2is connected with the source electrode S1of the driving transistor T1. The drain electrode D2of the switching transistor T2is also connected with the driving voltage line172via the operation control transistor T5. The switching transistor T2is turned on according to the scan signal Sn received through the scan line121to perform a switching operation transferring the data signal Dm from the data line171to the source electrode of the driving transistor T1.

A gate electrode G3of the compensation transistor T3is directly connected with the scan line151, a source electrode S3of the compensation transistor T3is connected to the drain electrode D1of the driving transistor T1and with an anode of the organic light emitting diode OLD via the light emission control transistor T6. A drain electrode D3of the compensation transistor T3is connected with one end Cst1of the storage capacitor Cst, the drain electrode D4of the initialization transistor T4, and the gate electrode G1of the driving transistor T1. The compensation transistor T3is turned on according to the scan signal Sn received through the scan line151to connect the gate electrode G1and the drain electrode D1of the driving transistor T1resulting in the driving transistor T1acting as a diode-connected transistor.

A gate electrode G4of the initialization transistor T4is connected with the previous scan line152, a source electrode S4of the initialization transistor T4is connected with the initialization voltage line192. A drain electrode D4of the initialization transistor T4is connected with one end Cst1of the storage capacitor Cst and the gate electrode G1of the driving transistor T1together through the drain electrode D3of the compensation transistor T3. The initialization transistor T4is turned on according to a previous scan signal S(n−1) received through the previous scan line152to transfer the initialization voltage Vint to the gate electrode G1of the driving transistor T1and initialize a voltage of the gate electrode G1of the driving transistor T1.

A gate electrode G5of the operation control transistor T5is connected with the light emission control line153, a source electrode S5of the operation control transistor T5is connected with the driving voltage line172. A drain electrode D5of the operation control transistor T5is connected with the source electrode S1of the driving transistor T1and the drain electrode D2of the switching transistor T2.

A gate electrode G6of the light emission control transistor T6is connected to the light emission control line153, the source electrode S6of the light emission control transistor T6is connected to the drain electrode D1of the driving transistor T1and the source electrode S3of the compensation transistor T3. The drain electrode D6of the first light emission control transistor T6is electrically connected to the anode of the organic light emitting diode OLD. The operation control transistor T5and the light emission control transistor T6are simultaneously turned on according to the light emission control signal EM transmitted to the light emission control line153. When the operation control transistor T5and the light emission control transistor T6are turned-on the driving voltage ELVDD is transmitted through the diode-connected driving transistor T1to the organic light emitting diode OLD.

The other end Cst2of the storage capacitor Cst is connected with the driving voltage line172. A cathode of the organic light emitting diode OLD is connected with a common voltage line741transferring a common voltage ELVSS.

The detailed structure of the organic light emitting diode display according to an exemplary embodiment of the inventive concept shown inFIG. 11will be described with reference toFIG. 12toFIG. 15.

FIG. 12is a layout view of a plurality of transistor and a capacitor of an organic light emitting diode display according to an exemplary embodiment.FIG. 13is a detail layout view ofFIG. 12.FIG. 14is a cross-sectional view of the display device ofFIG. 13taken along a line XIV-XIV.FIG. 15is a cross-sectional view of the display device ofFIG. 13taken along a line XV-XV.

Hereinafter, a detailed planar structure of the organic light emitting diode display device according to the exemplary embodiment will be first described in detail with reference toFIG. 12andFIG. 13. A detailed cross-sectional structure will be described in detail with reference toFIG. 14andFIG. 15.

The organic light emitting diode display according to an exemplary embodiment includes a scan line151, a previous scan line152, and a light emission control line153respectively applying the scan signal Sn, the previous scan signal S(n−1), and the light emission control signal EM. The scan line151, the previous scan line152, and the light emission control line153may be formed along the row direction. A data line171and a driving voltage line172respectively apply the data signal Dm and the driving voltage ELVDD to the pixel PX. Additionally, data line171and a driving voltage line172cross the scan line151, the previous scan line152, and the light emission control line153. The initialization voltage Vint is transmitted from the initialization voltage line192through the initialization transistor T4to the compensation transistor T3. The initialization voltage line192is formed while alternately having a straight portion and an oblique portion.

Each pixel PX may include the driving transistor T1, the switching transistor T2, the compensation transistor T3, the initialization transistor T4, the operation control transistor T5, the light emission control transistor T6, the storage capacitor Cst, and the organic light emitting diode OLD.

The organic light emitting diode OLD is made of a pixel electrode191, an organic emission layer370, and a common electrode270. In this case, the initialization transistor T4may have a dual gate structure transistor to block a leakage current.

Each channel of the driving transistor T1, the switching transistor T2, the compensation transistor T3, the initialization transistor T4, the operation control transistor T5, and the light emission control transistor T6is formed inside one semiconductor130. Additionally, the semiconductor130may be formed to be curved in various shapes. The semiconductor130may be made of a polycrystalline semiconductor material or an oxide semiconductor material.

The semiconductor130includes a channel which is doped with an N-type impurity or a P-type impurity. A source doping part and a drain doping part which are formed at opposite sides of the channel and are doped with an opposite-type doping impurity to the doping impurity doped on the channel. In the exemplary embodiment of the inventive concept, the source doping part and the drain doping part correspond to the source electrode and the drain electrode, respectively. The source electrode and the drain electrode formed in the semiconductor130may be formed by doping only the corresponding regions. Further, in the semiconductor130, a region between source electrodes and drain electrodes of different transistors is doped, and thus the source electrode and the drain electrode may be electrically connected to each other.

The channel includes a driving channel131aformed in the driving transistor T1, a switching channel131bformed in the switching transistor T2, a compensation channel131cformed in the compensation transistor T3, an initialization channel131dformed in the initialization transistor T4, an operation control channel131eformed in the operation control transistor T5, and a light emission control channel131fformed in the light emission control transistor T6.

The driving transistor T1includes the driving channel131a, a driving gate electrode155a, a driving source electrode136a, and a driving drain electrode137a. The driving channel131ais curved and may have a meandering shape or a zigzag shape. As such, by forming the curved driving channel131a, the driving channel131amay be formed in a narrow space. Accordingly, a driving range of the driving gate-source voltage Vgs between the driving gate electrode155aand the driving source electrode136ais increased by the elongated driving channel131a. The driving range of the driving gate-source voltage Vgs means a difference between the maximum driving gate-source voltage of the driving transistor corresponding to the maximum gray and the minimum driving gate-source voltage of the driving transistor corresponding to the minimum gray or the difference between the driving gate-source voltages Vgs for each step for the gray expression. Since the driving range of the gate voltage is increased, a gray scale of light emitted from the organic light emitting diode OLD may be finely controlled by changing the magnitude of the gate voltage. As a result, the resolution and display quality of the organic light emitting diode display device may be increased. Various examples such as ‘reverse S’, ‘S’, ‘M’, and ‘W’ may be implemented by variously modifying the shape of the driving channel131a.

The driving gate electrode155aoverlaps with the driving channel131a. The driving source electrode136aand the driving drain electrode137aare formed at opposite sides of the driving channel131ato be close to the driving channel131a. The driving gate electrode155ais connected to a first data connecting member174through a contact hole61.

The switching transistor T2includes the switching channel131b, a switching gate electrode155b, a switching source electrode136b, and a switching drain electrode137b. The switching gate electrode155bwhich is some of the portion extending downward from the scan line151overlaps the switching channel131b. The switching source electrode136band the switching drain electrode137bare formed to be adjacent to the switching channel131b, and are on opposite sides of the switching channel131b. The switching source electrode136bis connected to the data line171through a contact hole62.

The compensation transistor T3includes the compensation channel131c, a compensation gate electrode155c, a compensation source electrode136c, and a compensation drain electrode137c. The compensation gate electrode155cis a part of the scan line151and overlaps the compensation channel131c. The compensation source electrode136cand the compensation drain electrode137care formed to be adjacent to the compensation channel131c, and are on opposite sides of the compensation channel131c. The compensation drain electrode137cis connected to the first data connecting member174through a contact hole63.

The initialization transistor T4includes the initialization channel131d, an initialization gate electrode155d, an initialization source electrode136d, and an initialization drain electrode137d. The initialization gate electrode155dis a part of the previous scan line152and has a dual gate structure to prevent the leakage current. The initialization gate electrode155doverlaps the initialization channel131d. The initialization source electrode136dand the initialization drain electrode137dare formed to be adjacent to the initialization channel131d, and are on opposite sides of the initialization channel131d. The initialization source electrode136dis connected to a second data connecting member175through a contact hole64.

The operation control transistor T5includes the operation control channel131e, an operation control gate electrode155e, an operation control source electrode136e, and an operation control drain electrode137e. The operation control gate electrode155eis a part of the light emission control line153and overlaps the operation control channel131e. The operation control source electrode136eand the operation control drain electrode137eare formed to be adjacent to the operation control channel131e, and are on opposite sides of the operation control channel131e. The operation control source electrode136eis connected to a part that extends from the driving voltage line172through a contact hole65.

The light emission control transistor T6includes the light emission control channel131f, a light emission control gate electrode155f, a light emission control source electrode136f, and a light emission control drain electrode137f. The light emission control gate electrode155fis a part of the light emission control line153and overlaps the light emission control channel131f. The light emission control source electrode136fand the light emission control drain electrode137fare formed to be adjacent to the light emission control channel131f, and are on opposite sides of the light emission control channel131f. The light emission control drain electrode137fis connected to a third data connecting member179through a contact hole66.

One end of the driving channel131aof the driving transistor T1is connected to the switching drain electrode137band the operation control drain electrode137e. The other end of the driving channel131ais connected to the compensation source electrode136cand the light emission control source electrode136f.

The storage capacitor Cst includes a first storage electrode155aand a second storage electrode156with the second gate insulating layer142disposed between the first storage electrode155aand the second storage electrode156. The first storage electrode155acorresponds to the driving gate electrode155a. The second storage electrode156is a portion extending from a storage line157and occupies a wider area than that of the driving gate electrode155aand substantially covers the driving gate electrode155a.

In an exemplary embodiment of the inventive concept, the second gate insulating layer142is a dielectric material, and the storage capacitance is determined by a charge in the storage capacitor Cst and a voltage between both electrodes155aand156. The driving gate electrode155ais used as the first storage electrode155a, and thus the storage capacitor Cst may be formed in a narrow space due to the driving channel131aoccupying a large area within the pixel.

The first storage electrode155awhich is the driving gate electrode155ais connected to one end of the driving connecting member174through the contact hole61and a storage opening51. The storage opening51is an opening which is formed in the second storage electrode156. Accordingly, the contact hole61connecting one end of the driving connecting member174and the driving gate electrode155ais formed inside the storage opening156. The first driving connecting member174is formed in the same layer as the data line171to be almost parallel to the data line171. The other end of the first driving connecting member174is connected to the compensation drain electrode137cof the compensation transistor T3through the contact hole63. The other end of the first driving connecting member174connects to the initialization drain electrode137dof the initialization transistor T4via the compensation drain electrode137cof the compensation transistor T3. Accordingly, the first driving connecting member174connects the driving gate electrode155aand the compensation drain electrode137cof the compensation transistor T3and the initialization drain electrode137dof the initialization transistor T4to each other.

The storage capacitor Cst stores capacitance charge corresponding to a difference between the driving voltage ELVDD transmitted to the second storage electrode156through the driving voltage line172and the gate voltage Vg of the driving gate electrode155a.

The third data connecting member179is connected to the pixel electrode191through a contact hole81, and the second data connecting member175is connected to the initialization voltage line192through a contact hole82.

Hereinafter, the cross-sectional structures of the display device according to an exemplary embodiment will be described in detail according to a stacking order.

The buffer layer120may be formed on the insulating substrate110. The buffer layer120may be formed on the entire surface of the substrate110including the display region and the non-display region.

The semiconductor130including the channel including the driving channel131a, the switching channel131b, the compensation channel131c, the initialization channel131d, the operation control channel131e, and the light emission control channel131fis formed on the buffer layer120. The driving source electrode136aand the driving drain electrode137aare formed on opposite sides of the driving channel131ain the semiconductor130. The switching source electrode136band the switching drain electrode137bare formed on opposite sides of the switching channel131b. The compensation source electrode136cand the compensation drain electrode137care formed at opposite sides of the compensation channel131c. The initialization source electrode136dand the initialization drain electrode137dare formed at opposite sides of the initialization channel131d. The operation control source electrode136eand the operation control drain electrode137eare formed at opposite sides of the operation control channel131e. The emission control source electrode136fand the emission control drain electrode137fare formed at opposite sides of the emission control channel131f.

The first gate insulating layer141covering the semiconductor130is formed thereon. The first gate insulating layer141is formed on substantially all of the display region and the non-display region.

First gate wires (151,152,153,155a,155b,155c,155d,155e, and155f) including the switching gate electrode155b, the scan line151including the compensation gate electrode155c, the previous scan line152including the initialization gate electrode155d, the light emission control line153including the operation control gate electrode155eand the light emission control gate electrode155f, and the driving gate electrode (the first storage electrode)155aare formed on the first gate insulating layer141. The first gate wires (151,152,153,155a,155b,155c,155d,155e, and155f) may be made of the same material as the first metal wire (referring to510ofFIG. 3) positioned on the non-display region, and may be positioned in the same layer thereof.

The second gate insulating layer142covers the first gate wires (151,152,153,155a,155b,155c,155d,155e, and155f) and the first gate insulating layer141is formed thereon. The second gate insulating layer142is formed on the display region and the non-display region.

Second gate wires157and156are formed on the second gate insulating layer142. The storage line157is parallel to the scan line151and the second storage electrode156is a portion extending from the storage line157. The second gate wires157and156may be made of the same material as the second metal wire (referring to520ofFIG. 3) positioned in the non-display region, and may be positioned in the same layer thereof.

The second storage electrode156is wider than the first storage electrode155asuch that the second storage electrode156may cover the entire driving gate electrode155a. The first storage electrode155ais driving gate electrode.

The first interlayer insulating layer161is formed on the second gate insulating layer142and the second gate wires157and156. The first interlayer insulating layer161is formed on substantially all of the display region and the non-display region.

The first interlayer insulating layer161has contact holes61,62,63,64,65, and66exposing at least part of the upper surface of the semiconductor130or the driving gate electrode155a.

The second interlayer insulating layer162may be formed on the first interlayer insulating layer161. The second interlayer insulating layer162is formed on the display region and the non-display region. In an exemplary embodiment, the second interlayer insulating layer162may be omitted.

Data wires (171,172,174,175, and179) including the data line171, the driving voltage line172, the first data connecting member174, the second data connecting member175, and the third data connecting member179are formed on the second interlayer insulating layer162. The data wires (171,172,174,175, and179) may be made of the same material as the third metal wire (referring to710ofFIG. 3) and the fourth metal wire (referring to720ofFIG. 3) positioned in the non-display region, and may be positioned in the same layer thereof.

In an exemplary embodiment of the inventive concept, the data wires may be formed similarly to the third metal wire and fourth metal wire ofFIG. 8. For example, the driving drain electrode137aand the light emission control line153may form a groove in the upper layers including the second gate insulating layer142, first interlayer insulating layer161, and the second interlayer insulating layer162. A compensation pattern600may be positioned in the groove on the second interlayer insulating layer162. The third data connecting member179may be formed over the compensation pattern600and the interlayer insulating layer162.

The data line171is connected to the switching source electrode136bthrough the contact hole62.

One end of the first data connecting member174is connected to the first storage electrode155athrough the contact hole61, and the other end of the first data connecting member174is connected to the compensation drain electrode137cand the initialization drain electrode137dthrough the contact hole63.

The second data connecting member175parallel to the data line171is connected to the initialization source electrode136dthrough the contact hole64.

The third data connecting member179is connected to the light emission control drain electrode137fthrough the contact hole66.

The passivation layer180is formed on the data wire (171,172,174,175, and179) and the second interlayer insulating layer162. The passivation layer180is formed on substantially all of the display region and the non-display region.

The pixel electrode191and the initialization voltage line192are formed on the passivation layer180. The third data connection member179is connected with the pixel electrode191through the contact hole81formed on the passivation layer180. The second data connection member175is connected with the initialization voltage line192through the contact hole82formed on the passivation layer180.

A pixel definition layer (PDL)350is formed to cover the passivation layer180, the initialization voltage line192, and the edge of the pixel electrode191. The pixel definition layer350has a pixel opening351that exposes the pixel electrode191.

The organic emission layer370is formed on the pixel electrode191exposed by the pixel opening351, and the common electrode270is formed on the organic emission layer370. The common electrode270is formed on the pixel definition layer350to be formed through the plurality of pixels. As such, an organic light emitting diode OLD is formed, which includes the pixel electrode191, the organic emission layer370, and the common electrode270.

An encapsulation member protecting the organic light emitting diode OLD may be formed on the common electrode270. The encapsulation member may be sealed to the substrate110by a sealant and may be formed of various materials such as glass, quartz, ceramic, plastic, or a metal. In a further exemplary embodiment of the inventive concept, a thin film encapsulation layer may be formed on the common electrode270by depositing the inorganic layer and the organic layer without the usage of the sealant.

While the inventive concept has been described in connection with reference to exemplary embodiments thereof, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the appended claims.