Semiconductor device package with a stress relax pattern

A semiconductor device package has a die, a pattern of dielectric material formed on an active surface of the die, a plurality of metal contacts electrically connected to the die and surrounded by the pattern, a mold compound formed around the pattern, the die and the metal contacts, and a redistribution layer formed on a grinded surface of the mold compound and electrically connected to the metal contacts. The dielectric material has a young's modulus lower than a young's modulus of the mold compound, and the dielectric material has a coefficient of thermal expansion lower than a coefficient of thermal expansion of the mold compound.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to packaging a semiconductor device package, and more particularly to a semiconductor device package with a pattern of dielectric material to reduce stress thereon.

2. Description of the Prior Art

Wafer level packaging process is known in the art. In a wafer level packaging process, a wafer with integrated circuits mounted thereon undergoes a series process, such as grinding, die-bonding, molding and so on, and is finally cut into finished products. Wafer level packaging process has been considered as suitable technology for small sized and high-speed package.

In wafer level packaging, the wafer and the dies mounted on the wafer are typically covered with a relatively thick layer of the molding compound. The thick layer of the molding compound results in increased warping of the packaging due to coefficient of thermal expansion (CTE) mismatch, and the thickness of the packaging. It is known that wafer warpage continues to be a concern.

SUMMARY OF THE INVENTION

An embodiment of the present invention provides a method of forming a semiconductor device package. The method comprises disposing a die on a carrier; forming a pattern of dielectric material on an active surface of the die to surround a plurality of metal contacts electrically connected to the die; forming a mold compound around the die, the metal contacts and the pattern; grinding the mold compound to expose the metal contacts; removing the carrier; and forming a redistribution layer on a grinded surface of the mold compound to electrically connect to the metal contacts. The dielectric material has a young's modulus lower than a young's modulus of the mold compound, and the dielectric material has a coefficient of thermal expansion lower than a coefficient of thermal expansion of the mold compound

Another embodiment of the present invention provides a semiconductor device package. The semiconductor device package comprises a die, a plurality of metal contacts, a pattern of dielectric material, a mold compound, and a redistribution layer. The metal contacts electrically connected to the die. The pattern of the dielectric material is formed on an active surface of the die, and the metal contacts are surrounded by the pattern. The mold compound is formed around the pattern, the die and the metal contacts. The redistribution layer is formed on a grinded surface of the mold compound and electrically connected to the metal contacts. The dielectric material has a young's modulus lower than a young's modulus of the mold compound, and the dielectric material has a coefficient of thermal expansion lower than a coefficient of thermal expansion of the mold compound.

DETAILED DESCRIPTION

With reference to the attached drawings, the present invention is described by means of the embodiment(s) below where the attached drawings are simplified for illustration purposes only to illustrate the structures or methods of the present invention by describing the relationships between the components and assembly in the present invention. Therefore, the components shown in the figures are not expressed with the actual numbers, actual shapes, actual dimensions, nor with the actual ratio. Some of the dimensions or dimension ratios have been enlarged or simplified to provide a better illustration. The actual numbers, actual shapes, or actual dimension ratios can be selectively designed and disposed and the detail component layouts may be more complicated.

FIG. 1is a cross-sectional diagram of a fan-out wafer level package (FOWLP)300according to a first embodiment of the present invention.FIG. 2is a planar view of an active surface111of each die110of the FOWLP300along a dotted line301shown inFIG. 1. The FOWLP300may include a plurality of dies110, a plurality of metal contacts120, a plurality of patterns302of dielectric material310, an encapsulant130, and at least a redistribution layer140. Each die110has an outline represented by a die area112inFIG. 2. Each die110has metal contacts120formed on it. And, the metal contacts120may be electrically connected to the corresponding die110. The metal contacts120may be formed through bumping, electroplating, or wire bonding, but is not limited to. Each die110may have a corresponding pattern302disposed on it. Each pattern302may be disposed on the active surface111of a die110and within the die area112. The pattern302is formed to surround the metal contacts120of the die110. The patterns302are used as a stress relax pattern for dispersing the stress induced on the peripheral portion of the active surface111of the corresponding die110. In this way, the warpage of the die110can be suppressed. The pattern302, the dies110and the metal contacts120are encapsulated by an encapsulant130. The encapsulant130may have a grinded surface131where the redistribution layer140is formed. The redistribution layer140is electrically connected to the metal contacts120. The dielectric material310used to form the pattern302has lower young's modulus than young's modulus of the encapsulant130. Furthermore, dielectric material310has a lower coefficient of thermal expansion (CTE) than the encapsulant130. The dielectric material310may have a young's modulus between 0.01 GPa and 5 GPa. The dielectric material310may be epoxy resin, silicon resin, polyimide resin, or a combination thereof. In an exemplary embodiment, the dielectric material310may be a b-stage adhesive.

The fan-out wafer level package (FOWLP)300is formed using the method as illustrated inFIG. 3toFIG. 9using a cross-sectional views. The method comprises a plurality of processing steps. Each of the processing steps is described with a corresponding diagram illustrated inFIG. 3toFIG. 9.

As shown inFIG. 3, a plurality of dies110are temporarily disposed on a carrier500. Each of the plurality of dies110have a plurality of metal contacts120formed on the active surface111.

As shown inFIG. 4, a pattern302is formed on the active surface111of each die110. The pattern302may be a dielectric material310formed on the active surface111using screen printing technique. However, the pattern302may also be formed using photolithography in some other embodiments. The pattern302may surround the metal contacts120of a corresponding die110as shown inFIG. 2. The pattern302may be formed on the corresponding die110before or after the die110is temporarily disposed on the carrier500.

As shown inFIG. 5, an encapsulant130is formed to encapsulate the dies110, the metal contacts120and the patterns302. The encapsulant130may be formed using epoxy molding compound (EMC).

As shown inFIG. 6, the encapsulant130is grinded through grinding process to form a grinded surface131. The grinding process may reduce the thickness of the encapsulant130and allow the grinded surface131to expose surfaces of the metal contacts120and the dielectric material310.

As shown inFIG. 8, the redistribution layer140is formed on the grinded surface131of the encapsulant130. The redistribution layer140is electrically connected to the metal contacts120. The redistribution layer140may comprise a first dielectric layer141, a metal layer142and a second dielectric layer143. The metal layer142may be formed between the first dielectric layer141and the second dielectric layer143. The first dielectric layer141may be formed to have openings exposing a surface of the metal contacts120. And, the openings of the first dielectric layer141are further filled with the conductive material used to form the metal layer142to form the electrical connection between the metal contacts120and the metal layer142. The second dielectric layer143may be formed to have openings exposing at least one part of the metal layer142. A plurality of solder balls150are formed on the openings of the second dielectric layer143to electrically connect solder balls150to the metal contacts120through the metal layer142. The first dielectric layer141and the second dielectric layer143may be polyimide layers.

As shown inFIG. 9, after the formation of the wiring layer140, the mold compound130and the wiring layer140are sawed by a sawing mechanism so as to manufacture a plurality of semiconductor device package350. In the embodiment, each of the device packages350comprises at least one of the dies110.

FIG. 10is a planar view showing a different layout of the patterns302of the dielectric material310according to a second embodiment of the present invention. In the embodiment, each of the patterns302further comprises an additional section310A to form two openings of the pattern302. A portion of the plurality of metal contacts120are formed within a first opening of the pattern302. Another portion of the plurality of metal contacts120are formed within a second opening of the pattern302. In addition, the additional section310A may be formed to form two substantially equal sized openings. Thus, the number of metal contacts120within the openings may be equal to each other. In some other embodiment, there may be odd number of rows of metal contacts120. In this case, one opening may be larger than the other opening. The spaces between the metal contacts120and the pattern302are filled with the mold compound130.

FIG. 11is a planar view showing a different layout of the patterns302of the dielectric material310according to a third embodiment of the present invention. In the embodiment, the pattern302comprises a plurality of openings. Each of the metal contacts120is formed within one of the openings of the pattern302. The spaces between the metal contacts120and the pattern302are filled with the mold compound130.

FIG. 12is a planar view showing a different layout of the patterns302of the dielectric material310according to a fourth embodiment of the present invention. In the embodiment, the metal contacts120are encapsulated by the patterns302before the molding compound130is formed.

According to the embodiments of the present invention, a pattern of the dielectric material is used as a stress relax pattern for releasing the stress concentrated on the surface of the die. The dielectric material has a lower coefficient of thermal expansion (CTE) and lower young's modulus than the mold compound. Therefore, the warpage of the die can be suppressed.