Method (and related apparatus) that reduces cycle time for forming large field integrated circuits

In some embodiments, a method for forming an integrated circuit is provided. The method includes forming a first layer over a semiconductor wafer, the first layer having a first portion and a second portion. The first portion is patterned by projecting a first image field over the first portion of the first layer, where the first portion of the first layer corresponds to the first image field. The second portion is patterned by projecting a second image field over the second portion of the first layer, where the second portion of the first layer corresponds to the second image field. A second layer is formed over the first layer. The second layer is patterned by projecting a third image field over the second layer, where the third image field covers a majority of the first portion and a majority of the second portion of the first layer.

BACKGROUND

Many modern day electronic devices (e.g., digital cameras, optical imaging devices, display panels, etc.) comprise large field integrated circuits (ICs). A large field IC is an IC having a maximum area that is greater than a maximum image field size of the exposure system (e.g., photolithography system). Typically, the large field IC is formed by a step-and-repeat photolithography process that comprises stepping a reticle over a semiconductor wafer. Compared to other ICs, large field ICs may increase the number (or size) of semiconductor devices (e.g., photodetectors, transistors, etc.) on a given die.

DETAILED DESCRIPTION

The present disclosure will now be described with reference to the drawings wherein like reference numerals are used to refer to like elements throughout, and wherein the illustrated structures are not necessarily drawn to scale. It will be appreciated that this detailed description and the corresponding figures do not limit the scope of the present disclosure in any way, and that the detailed description and figures merely provide a few examples to illustrate some ways in which the inventive concepts can manifest themselves.

A large field integrated circuit (IC) often includes a plurality of integrated circuit units (ICUs) (e.g., a first ICU and a second ICU) electrically coupled together. Generally, the large field IC is formed by a step-and-repeat photolithography process that comprises stepping a reticle over a semiconductor wafer. The step-and-repeat photolithography process includes projecting a first image field toward a first region of the semiconductor wafer by passing radiation through the reticle. Thereafter, the reticle is stepped across the semiconductor wafer, such that radiation may be passed through the reticle to project a second image field toward a second region of the semiconductor wafer. This step-and-repeat photolithography process is repeated multiple times with different reticles to form a first ICU over the first region and a second ICU over the second region of the semiconductor wafer. Typically, during formation of the large field IC, the first ICU is field stitched to the second ICU, such that the first ICU is electrically coupled to the second ICU.

Field stitching the first ICU to the second ICU typically includes forming a stitching region between the first ICU and the second ICU. The stitching region is formed by overlapping the first image field and the second image field. For example, during formation of metal line one of the first ICU, the stitching region is patterned a first time by projecting the first image field toward the first region of the semiconductor wafer. Thereafter, during formation of metal line one of the second ICU, the stitching region is patterned a second time by projecting the second image field toward the second region of the semiconductor wafer. Because the first image field and the second image field are overlapped, metal line one of the first ICU may be electrically coupled to metal line one of the second ICU. This process may be repeated to electrically couple various metal lines of the first ICU to various metal lines of the second ICU. Eventually, a wafer dicing process is performed on the semiconductor wafer such that the first ICU and the second ICU are each included on a single die, corresponding to the large field IC.

A challenge with the above method for forming the large field IC is cycle time. Cycle time is an amount of time to process an IC to completion in a fab. Because the field stitching process requires multiple patternings of the stitching area, the semiconductor wafer must be precisely aligned to ensure the first image field is aligned with the second image field, thereby ensuring the first ICU may be electrically coupled to the second ICU. This precision alignment process increases the cycle time for forming the large field IC. In addition, minimum features sizes in the stitching region are typically relaxed to ensure proper alignment of the first image field and the second image field, thereby reducing the density of semiconductor devices (e.g., photodetectors, transistors, conductive lines, conductive vias, etc.) on the large field IC.

In various embodiments, the present application is directed toward a method that reduces the cycle time for forming a large field IC. The method includes forming a first ICU over a first region of a semiconductor wafer, wherein forming the first ICU comprises projecting a first image field over the first region of the semiconductor wafer by passing radiation through a first reticle. A second ICU is formed over a second region of the semiconductor wafer, wherein forming the second ICU comprises projecting a second image field over the second region of the semiconductor wafer by passing radiation through a second reticle. A dielectric layer is formed over both the first ICU and the second ICU. A conductive layer is formed on the dielectric layer. The conductive layer is patterned to form a patterned conductive layer that electrically couples the first ICU to the second ICU, wherein forming the patterned conductive layer comprises projecting a third image field covering a majority of the first region and a majority of the second region of the semiconductor wafer.

By patterning the conductive layer with the third image field that covers a majority of both the first region and the second region of the semiconductor wafer, the first ICU and the second ICU may be electrically coupled together without overlapping the first image field with the second image field. Thus, the field stitching process may not be required (or a reduced number of field stitching process(es) may be required) to form the large field IC. Accordingly, the cycle time for forming the large field IC may be reduced. In addition, because the field stitching process may not be required, minimum features sizes in the stitching region may not need to be relaxed. Accordingly, the density of semiconductor devices on the large field IC may be increased.

FIGS. 1-2illustrate a series of perspective views of some embodiments of a method for forming large field integrated circuits (ICs) with reduced cycle time.

As shown inFIG. 1, a first passivation layer102having a plurality of openings114is formed over a semiconductor wafer104. In some embodiments, the semiconductor wafer104comprises any type of semiconductor body (e.g., monocrystalline silicon/CMOS bulk, silicon-germanium (SiGe), silicon on insulator (SOI), etc.). In some embodiments, the first passivation layer102comprises a plurality of portions (e.g.,106a/106b) arranged in an array having a plurality of rows and columns. For example, the first passivation layer102comprises a first portion106aand a second portion106barranged adjacent to one another in a first row. In further embodiments, the plurality of portions of the first passivation layer102are formed over a plurality of integrated circuit units (ICUs) (not shown), respectively. For example, the first portion of the first passivation layer106amay be formed over a first ICU, and the second portion of the first passivation layer106bmay be formed over a second ICU.

In some embodiments, a process for forming the first passivation layer102comprises forming a dielectric layer (not shown) over the semiconductor wafer104. A first masking layer (not shown) (e.g., a negative/positive photoresist) is formed on the dielectric layer. A first reticle108having a first maximum image field size is positioned at a first location over the first masking layer, the first maximum image field size being a maximum area that the first reticle108may expose to radiation while projecting a first minimum feature size.

In some embodiments, the first minimum feature size may be less than about 0.5 micrometers (μm). More specifically, the first minimum feature size may be less than about 45 nanometers (nm). In some embodiments, the first maximum image field size may be less than about 2,500 square millimeters (mm2). More specifically, the first maximum image field size may be less than or equal to about 858 (mm2). In such embodiments, the first maximum image field size may have a maximum x-axis dimension less than or equal to about 26 mm and a maximum y-axis dimension (e.g., perpendicular to the x-axis dimension) less than or equal to about 33 mm.

Thereafter, radiation110is passed through the first reticle108at the first location, such that a first image field112is projected onto a first portion of the first masking layer. The first image field112comprises a first defined pattern of radiation (e.g., transparently illustrated inFIG. 1) having the first minimum feature size. The radiation110reacts with the first masking layer, such that regions of the first making layer exposed to the radiation110are more (or less) soluble in a developing agent than regions of the first masking layer that are not exposed to the radiation110.

In some embodiments, a size/shape of the first portion of the first masking layer corresponds to the first maximum field size projected onto the first masking layer by the first reticle at the first location. In further embodiments, the first portion of the first masking layer is about vertically aligned with the first portion of the first passivation layer106a. In yet further embodiments, if the first portion of the first masking layer is within a defined overlay tolerance (e.g., about 1 nanometer (nm) to about 300 nm), the first portion of the first masking layer is about vertically aligned with the first portion of the first passivation layer106a.

Subsequently, the first reticle108is stepped across (e.g., via a stepper) the first masking layer to a second location over the first masking layer. Thereafter, radiation110is passed through the first reticle108to project the first image field112of the first reticle108onto a second portion of the first masking layer, thereby reacting with the first masking layer. It will be appreciated that, rather than the first reticle being stepped across to the second location, a different reticle having a maximum image field size that is less than or equal to the first maximum image field size may alternatively be positioned at the second location.

In some embodiments, a size/shape of the second portion of the first masking layer corresponds to the first maximum field size projected onto the first masking layer by the first reticle at the second location. In further embodiments, the second portion of the first masking layer is about vertically aligned with the second portion of the first passivation layer106b. In yet further embodiments, if the second portion of the first masking layer is within the defined overlay tolerance, the second portion of the first masking layer is about vertically aligned with the second portion of the first passivation layer106b.

In some embodiments, the above process is repeated multiple times to project the first image field112onto a plurality of portions of the first making layer, the plurality of portions of the first masking layer being vertically aligned with the plurality of portions of the first passivation layer102. Thereafter, the first masking layer is developed by exposing the first masking layer to the developing agent to remove portions of the first masking layer that were exposed (or not exposed) to radiation110. An etching process (e.g., wet or dry etching) is then performed to remove unmasked portions of the dielectric layer (e.g., portions not covered by the developed first masking layer), thereby forming the first passivation layer102with the plurality of openings114disposed therein. In some embodiments, the openings114expose underlying conductive features (e.g., conductive vias, conductive lines, etc.) of the ICUs. Subsequently, the remaining portions of the first masking layer are stripped from the first passivation layer102.

As shown inFIG. 2, a plurality of patterned conductive layers202are formed extending over multiple portions (e.g.,106a/106b) of the first passivation layer102. For example, one of the patterned conductive layers202extends from one of the openings114disposed in the first portion of the first passivation layer106ato one of the openings114disposed in the second portion of the first passivation layer106b. The patterned conductive layers202are configured to electrically couple the ICUs together. For example, one or more of the patterned conductive layers202electrically couples the first ICU to the second ICU. In some embodiments, the patterned conductive layers202may comprise, for example, copper, aluminum, aluminum-copper, some other conductive material, or a combination of the forgoing. In some embodiments, the patterned conductive layers202are redistribution layers (RDLs).

In some embodiments, a process for forming the patterned conductive layers202comprises forming a conductive layer over the first passivation layer102that at least partially fills the openings114in the first passivation layer102. In some embodiments, the conductive layer may comprise, for example, copper, aluminum, aluminum-copper, some other conductive material, or a combination of the forgoing. A second masking layer (not shown) (e.g., a negative/positive photoresist) is formed on the conductive layer. A second reticle204having a second maximum field size greater than the first maximum field size is positioned at a third location over the second masking layer, the second maximum image field size being a maximum area that the second reticle204may expose to radiation while projecting a second minimum feature size greater than the first minimum feature size.

In some embodiments, the second maximum field size is greater than about 858 mm2. In such embodiments, the second maximum image field size may have a minimum x-axis dimension greater than about 26 mm and a minimum y-axis dimension (e.g., perpendicular to the x-axis dimension) greater than about 33 mm. In further embodiments, the second maximum field size may be greater than or equal to about 2,500 mm2. In such embodiments, the second maximum image field size may have a minimum x-axis dimension greater than or equal to about 50 mm and a minimum y-axis dimension (e.g., perpendicular to the x-axis dimension) greater than or equal to about 50 mm. In further embodiments, the second minimum feature size may be greater than or equal to about 0.5 μm. In yet further embodiments, the second minimum feature size is greater than the first minimum feature size.

Thereafter, radiation110is passed through the second reticle204at the third location, such that a second image field206covering a majority of the first portion106aand a majority of the second portion of the first passivation layer106bis projected onto a first portion of the second masking layer. The second image field206comprises a second defined pattern of radiation (e.g., transparently illustrated inFIG. 2) having the second minimum feature size. The radiation110reacts with the second masking layer, such that regions of the second making layer exposed to the radiation110are more (or less) soluble in a developing agent than regions of the second masking layer that are not exposed to the radiation110.

In some embodiments, a size/shape of the first portion of the second masking layer corresponds to the second maximum field size projected onto the second masking layer by the second reticle at the third location. In further embodiments, the first portion of the second masking layer covers a majority of the first portion106aand a majority of the second portion of the first passivation layer106b. In further embodiments, the first portion of the second masking layer has a perimeter that is enclosed by a combined perimeter of the first portion106aand the second portion of the first passivation layer106b. In other embodiments, the perimeter of the first portion of the second making layer is about vertically aligned with the combined perimeter of the first portion106aand the second portion of the first passivation layer106b.

Subsequently, the second reticle204is stepped across the second masking layer to a fourth location over the second masking layer. Thereafter, radiation110is passed through the second reticle204to project the second image field206onto a second portion of the second masking layer, thereby reacting with the second masking layer. It will be appreciated that, rather than the second reticle204being stepped across to the fourth location, a different reticle having a maximum image field size that is greater than or equal to the second maximum image field size may alternatively be positioned at the fourth location.

In some embodiments, the above process is repeated multiple times to project the second image field206onto a plurality of portions of the second making layer, each of the plurality of portions of the second masking layer covering a majority of multiple portions (e.g.,106a/106b) of the first passivation layer102. Thereafter, the second masking layer is developed by exposing the second masking layer to a developing agent to remove portions of the second masking layer that were exposed (or not exposed) to radiation110. An etching process is then performed to remove unmasked portions of the conductive layer, thereby forming the patterned conductive layers202. In some embodiments, the patterned conductive layers202are formed extending between underlying conductive features of individual ICUs (e.g., extending from the first ICU to the second ICU). Subsequently, the remaining portions of the second masking layer are stripped from the patterned conductive layers202. In further embodiments, forming the patterned conductive layers202forms a plurality of large field ICs208disposed in an array on the semiconductor wafer104, each of the large field ICs208comprising a plurality of ICUs coupled together by one or more patterned conductive layers202.

By forming the patterned conductive layers202with the second image field206, the large field ICs208may be formed without overlapping the first image field projected at the first location with the first image field projected at the second location. Thus, the large field ICs208may be formed without a field stitching process (or by reducing a number of field stitching process(es) needed to form the large field ICs208). Accordingly, the cycle time for forming the large field ICs208may be reduced. In addition, because the large field ICs208may be formed without the field stitching process, minimum features sizes may not needed to be relaxed to compensate for the field stitching process. Accordingly, the density of semiconductor devices on the large field IC may be increased.

FIG. 3illustrates a perspective view of some embodiments of the large field ICs ofFIG. 2being singulated into large field dies.

As shown inFIG. 3, a wafer dicing process302is performed on the semiconductor wafer104singulating the large field ICs208from the semiconductor wafer104to form large field dies304, respectively. In some embodiments, the wafer dicing process302comprises performing a series of cuts into the semiconductor wafer104to form a plurality of scribe lines306. Subsequently, a mechanical force is applied to the semiconductor wafer104to singulate the large field dies304from the semiconductor wafer104. In further embodiments, the cuts may be performed by, for example, mechanical sawing, laser cutting, or the like.

FIG. 4illustrates a perspective view of some embodiments of a large field die ofFIG. 3.

As shown inFIG. 4, the large field die304comprises a semiconductor substrate402. The semiconductor substrate402is a portion of the semiconductor wafer104that was singulated from the semiconductor wafer104during the wafer dicing process302. In further embodiments, the semiconductor substrate402comprises any type of semiconductor body (e.g., monocrystalline silicon/CMOS bulk, silicon-germanium (SiGe), silicon on insulator (SOI), etc.).

Further, the large field die304comprises a first ICU406aand a second ICU406b. In some embodiments, the first ICU406acomprises a first plurality of semiconductor devices (not shown) that are interconnected together by a first plurality of conductive features (e.g., metal lines, metal vias, etc.) (not shown). In further embodiments, the second ICU406bcomprises a second plurality of semiconductor devices (not shown) that are interconnected together by a second plurality of conductive features (not shown).

A metallization structure404is disposed between the semiconductor substrate402and the first passivation layer102. In some embodiments, the metallization structure404comprises the first plurality of conductive features structure and the second plurality of conductive features. In further embodiments, the first ICU406aand the second ICU406bmay be electrically isolated from one another by an isolation region408. In yet further embodiments, the isolation region408may comprise a region of the metallization structure404disposed between the first ICU406aand the second ICU406b, and a region of the semiconductor substrate402disposed between the first ICU406aand the second ICU406b. In yet further embodiments, one or more patterned conductive layers202electrically couples the first ICU406ato the second ICU406bby bridging the isolation region408.

FIG. 5illustrates a cross-sectional view of some embodiments of the large field die ofFIG. 4.

As shown inFIG. 5, a plurality of isolation structures502are disposed in the semiconductor substrate402. In some embodiments, the plurality of isolation structures502may comprise, for example, an oxide (e.g., silicon dioxide (SiO2)), a nitride (e.g., silicon nitride (SiN)), an oxy-nitride (e.g., silicon oxynitride (SiOXNY)), some other dielectric, or a combination of the foregoing. In further embodiments, the plurality of isolation structures502are shallow trench isolation (STI) structures.

A first dielectric layer504is disposed over the semiconductor substrate402. In some embodiments, the first dielectric layer504is disposed on the semiconductor substrate402and the plurality of isolation structures502. In further embodiments, the first dielectric layer504may comprise, for example, an oxide (e.g., SiO2).

A plurality of semiconductor devices506(e.g., a metal-oxide-semiconductor field-effect transistors (MOSFETs)) are disposed over/within the semiconductor substrate402. In some embodiments, each of the plurality of semiconductor devices506comprise a gate electrode508disposed on the first dielectric layer504, and a pair of source/drain regions (not shown) disposed in the semiconductor substrate402on opposite sides of the gate electrode508. In further embodiments, the gate electrodes508may comprise, for example, doped polysilicon, fully-silicided polysilicon, a metal (e.g., aluminum, copper, titanium, tantalum, tungsten, molybdenum, cobalt, etc.), or some other conductive material. In further embodiments, the isolation structures502may be disposed on opposite sides of the semiconductor devices506. In yet further embodiments, regions of the first dielectric layer504disposed directly beneath the gate electrodes508may be referred to as gate dielectrics, respectively.

An interlayer dielectric (ILD) layer510is disposed over the semiconductor devices506and the first dielectric layer504. In some embodiments, the ILD layer510may comprise one or more of a low-k dielectric layer (e.g., a dielectric with a dielectric constant less than about 3.9), an ultra-low-k dielectric layer, an oxide (e.g., SiO2), or the like. In further embodiments, a plurality of conductive contacts512are disposed in the ILD layer510and electrically coupled to the semiconductor devices506. In yet further embodiments, the conductive contacts512may comprise, for example, tungsten, copper, or the like. In further embodiments, an inter-metal dielectric (IMD) layer514is disposed over the ILD layer510. In some embodiments, the IMD layer514may comprise one or more of a low-k dielectric layer, an ultra-low-k dielectric layer, an oxide (e.g., SiO2), or the like.

In some embodiments, a plurality of conductive features516(e.g., metal lines, metal vias, etc.) are disposed in the IMD layer514and electrically coupled to the conductive contacts512. In further embodiments, the conductive features516of the first ICU406aare configured to provide electrical connections between semiconductor devices506of the first ICU406a. In further embodiments, the conductive features516of the second ICU406bare configured to provide electrical connections between semiconductor devices506of the second ICU406b. In further embodiments, the conductive features516may comprise, for example, copper, aluminum, or the like. In yet further embodiments, the metallization structure404may comprise the ILD layer510, the IMD layer514, the conductive contacts512, and the conductive features516.

An isolation region408is disposed between the first ICU406aand the second ICU406b. In some embodiments, the isolation region408electrically isolates the first ICU406afrom the second ICU406b. In further embodiments, the isolation region408may comprise a region disposed between the first ICU406aand the second ICU406bthat extends from a bottom surface of the semiconductor substrate402and a bottom surface of the first passivation layer102.

In some embodiments, the isolation region408may comprise conductive features516, conductive contacts512, and/or gate electrodes508. In further embodiments, some of the conductive features516disposed in the isolation region408may be electrically coupled to the conductive features516of the first ICU406a. In further embodiments, some other conductive features516disposed in the isolation region408may be electrically coupled to the conductive features516of the second ICU406b. In further embodiments, the some of the conductive features516disposed in the isolation region408are not electrically coupled to the some other conductive features516disposed in the isolation region408. In yet further embodiments, the some of the conductive features516disposed in the isolation region408and/or the some other conductive features516disposed in the isolation region408are not electrically coupled to the first ICU406aor the second ICU406b.

In some embodiments, a first peripheral region518ais disposed on a side of the first ICU406aopposite the isolation region408. In further embodiments, a second peripheral region518bis disposed on a side of the second ICU406bopposite the isolation region408. In further embodiments, the first peripheral region518aand the second peripheral region518bmay comprise conductive features516, conductive contacts512, and/or gate electrodes508. In further embodiments, conductive features516of the first peripheral region518amay be electrically coupled to the conductive features516of the first ICU406a. In yet further embodiments, the conductive features516of the second peripheral region518bmay be electrically coupled to the conductive features516of the second ICU406b.

A second passivation layer520is disposed over the IMD layer514and the conductive features516. In some embodiments, the second passivation layer520comprises a second dielectric layer522, a third dielectric layer524, and a fourth dielectric layer526. In further embodiments, the second dielectric layer522may comprise, for example, an oxide (e.g., SiO2). In further embodiments, the third dielectric layer524may comprise, for example, a nitride (e.g., SiN). In further embodiments, the fourth dielectric layer526may comprise for example, an oxide (e.g., SiO2). It will be appreciated that the second passivation layer520may be a single dielectric layer that comprises an oxide (e.g., SiO2), a nitride (e.g., SiN), an oxy-nitride (e.g., SiOXNY), or the like.

A plurality of conductive vias528are electrically coupled to conductive features516of the first ICU406aand the second ICU406b. In some embodiments, the conductive vias528are disposed over/within the second passivation layer520. In some embodiments, the conductive vias528extend from an upper surface of the second passivation layer520to conductive features516of the first ICU406aand the second ICU406b. In further embodiments, the conductive vias528may comprise, for example, aluminum (Al), copper (Cu), tungsten (W), gold (Au), or the like. In yet further embodiments, the conductive vias528that are electrically coupled to the conductive features516of the first ICU406aare not electrically coupled to the conductive vias528of the second ICU406b.

In some embodiments, a minimum feature size of the first ICU406amay be less than or equal to the first minimum feature size. In further embodiments, a minimum feature size of the second ICU406bmay be less than or equal to the first minimum feature size. In further embodiments, the first minimum feature size may be less than about 0.5 micrometers (μm). In further embodiments, the minimum feature size of the first ICU406amay be substantially the same as the minimum feature size of the second ICU406b. In other embodiments, the minimum feature size of the first ICU406amay be different than the minimum feature size of the second ICU406b. In such embodiments, the minimum feature size of the first ICU406aand a minimum feature size of the second ICU406bmay be less than the about 0.5 μm.

In some embodiments, a layout of the first ICU406amay be substantially the same as a layout of the second ICU406b. In other words, the semiconductor devices506, the conductive contacts512, the conductive features516, and the conductive vias528of the first ICU406amay be disposed in a substantially same layout as the semiconductor devices506, the conductive contacts512, the conductive features516, and the conductive vias528of the second ICU406a. In other embodiments, the layout of the first ICU406amay be different than the layout of the second ICU406b. For example, in some embodiments, the first ICU406amay be a first microprocessor core, and the second ICU406bmay be a second ICU core that is identical to the first ICU406a, and the patterned conductive layers202electrically couple the first ICU406ato the second ICU406b.

In some embodiments, the first passivation layer102is disposed over the second passivation layer520. In further embodiments, the first passivation layer102is partially disposed over the conductive vias528. In further embodiments, the first portion of the first passivation layer106ais disposed over the first ICU406a, and the second portion of the first passivation layer106bis disposed over the second ICU406b. In further embodiments, a region of the first passivation layer102is disposed over the isolation region408and continuously covers a region of the first ICU406a, the isolation region408, and a region of the second ICU406b. In yet further embodiments, the region of the first passivation layer102that is disposed over the isolation region408may have an uppermost surface that is disposed over uppermost surfaces of the conductive vias528.

The plurality of patterned conductive layers202are disposed over the first ICU406aand the second ICU406b. In some embodiments, one of the patterned conductive layers202is configured to electrically couple the first ICU406ato the second ICU406b. In some embodiments, the one of the patterned conductive layers202electrically couples the first ICU406ato the second ICU406bby extending vertically from a conductive via528of the first ICU406a, laterally along the region of the first passivation layer102disposed over the isolation region408, and vertically toward a conductive via528of the second ICU406b. In further embodiments, the patterned conductive layers202may comprise, for example, aluminum (Al), copper (Cu), tungsten (W), gold (Au), some other conductive material, or a combination of the foregoing. In yet further embodiments, the patterned conductive layers202are redistribution layers (RDLs).

In some embodiments, a minimum feature size of the patterned conductive layers202is greater than a minimum feature size of both the first ICU406aand the second ICU406b. In further embodiments, the minimum feature size of the patterned conductive layers202is the second minimum feature size. In further embodiments, the second minimum feature size is greater than about 0.5 μm. In yet further embodiments, a width of the patterned conductive layers202may be the second minimum feature size.

In some embodiments, a third passivation layer532is disposed over the first passivation layer102and the patterned conductive layers202. In further embodiments, the third passivation layer may have a substantially planar upper surface. In further embodiments, the third passivation layer532may comprise, for example, an oxide (e.g., SiO2), a nitride (e.g., SiN), an oxy-nitride (e.g., SiOXNY), or the like. In yet further embodiments, the large field IC208comprises the first ICU406a, the second ICU406b, the isolation region408, the patterned conductive layers202, the first passivation layer102, and the third passivation layer532.

FIG. 6illustrates a cross-sectional view of some other embodiments of the large field die ofFIG. 5.

As shown inFIG. 6, in some embodiments, the one of the patterned conductive layers202does not electrically couple the first ICU406ato the second ICU406b. In such embodiments, the large field die304may comprise additional ICU(s) (not shown). In further such embodiments, the one of the patterned conductive layers202may electrically couple the first ICU406aand/or the second ICU406bto the additional ICU(s). For example, the one of the patterned conductive layers202may laterally extend (e.g., into the page ofFIG. 6) over the first passivation layer102to electrically couple the first ICU406ato a third ICU (not shown), and another one of the patterned conductive layers202may extend in parallel with the one of the patterned conductive layers202to electrically couple the second ICU406bto a fourth ICU (not shown).

FIGS. 7-18illustrate a series of cross-sectional views of some embodiments of a method for forming the large field die ofFIG. 5with reduced cycle time.

As shown inFIG. 7, a plurality of upper conductive feature openings702are formed in an upper IMD layer704, the upper IMD layer704having a first portion706and a second portion708. In some embodiments, the upper IMD layer704may comprise one or more of a low-k dielectric layer, an ultra-low-k dielectric layer, an oxide (e.g., (SiO2), or the like. In further embodiments, a process for forming the upper conductive feature openings702comprises performing a first patterning process on the upper IMD layer704. In yet further embodiments, the first patterning process comprises forming a third masking layer (not shown) (e.g., a negative/positive photoresist) on the upper IMD layer704. The third masking layer may be formed by, for example, a spin-on process.

A third reticle710having a third maximum image field size is positioned at a fifth location over the third masking layer, the third maximum image field size being a maximum area that the third reticle710may expose to radiation while projecting a third minimum feature size. In some embodiments, the third minimum feature size may be less than about 0.5 μm. More specifically, the third minimum feature size may be less than about 45 nm. In further embodiments, the third minimum feature size is substantially the same as the first minimum feature size.

In some embodiments, the third maximum image field size may be less than about 2,500 mm2. More specifically, the third maximum image field size may be less than or equal to about 858 mm2. In such embodiments, the third maximum image field size may have a maximum x-axis dimension less than or equal to about 26 mm and a maximum y-axis dimension (e.g., perpendicular to the x-axis dimension) less than or equal to about 33 mm. In further embodiments, the third maximum image field size is substantially the same as the first maximum image field size.

Thereafter, radiation is passed through the third reticle710at the fifth location, such that a third image field is projected onto a first portion of the third masking layer. The third image field comprises a third defined pattern of radiation (e.g., a layout of the upper conductive feature openings702) having the third minimum feature size. The radiation reacts with the third masking layer, such that regions of the third making layer exposed to the radiation are more (or less) soluble in a developing agent than regions of the third masking layer that are not exposed to the radiation.

In some embodiments, a size/shape of the first portion of the third masking layer corresponds to the third maximum field size projected onto the third masking layer at the fifth location. In further embodiments, the first portion of the third masking layer is about vertically aligned with the first portion of the upper IMD layer706. In yet further embodiments, if the first portion of the third masking layer is within a defined overlay tolerance (e.g., about 1 nanometer (nm) to about 300 nm), the first portion of the third masking layer is about vertically aligned with the first portion of the upper IMD layer706.

Subsequently, the third reticle710is stepped across (e.g., via a stepper) the third masking layer to a sixth location over the third masking layer. Thereafter, radiation is passed through the third reticle710to project the third image field onto a second portion of the third masking layer, thereby reacting with the third masking layer. It will be appreciated that, rather than the third reticle being stepped across to the sixth location, a different reticle having a maximum image field size that is less than or equal to the third maximum image field size may alternatively be positioned at the sixth location to project a different image field onto the second portion of the third masking layer.

In some embodiments, a size/shape of the second portion of the third masking layer corresponds to the third maximum field size projected onto the third masking layer by the third reticle710at the sixth location. In further embodiments, the second portion of the third masking layer is about vertically aligned with the second portion of the upper IMD layer708. In yet further embodiments, if the second portion of the third masking layer is within the defined overlay tolerance, the second portion of the third masking layer is about vertically aligned with the second portion of the upper IMD layer708.

Thereafter, the third masking layer is developed by exposing the third masking layer to the developing agent to remove portions of the third masking layer that were exposed (or not exposed) to the radiation. An etching process (e.g., wet or dry etching) is then performed to remove unmasked portions of the upper IMD layer704(e.g., portions not covered by the developed third masking layer), thereby forming the plurality of upper conductive feature openings702in the upper IMD layer704. Subsequently, the remaining portions of the third masking layer are stripped from the upper IMD layer704.

As shown inFIG. 8, a plurality of upper conductive features802are formed in the upper IMD layer704. In some embodiments, a process for forming the upper conductive features802comprises depositing a conductive layer (not shown) on the upper IMD layer704and filling the upper conductive feature openings702(see, e.g.,FIG. 7). Subsequently, a planarization process (e.g., a chemical-mechanical planarization (CMP)) is performed on the conductive layer and into the upper IMD layer704to form the upper conductive features802. In some embodiments, the conductive layer may comprise, for example, copper, aluminum, or the like. In further embodiments, the conductive layer may be deposited by, for example, chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), sputtering, electrochemical plating, electroless plating, some other deposition process, or a combination of the foregoing.

As shown inFIG. 9, a second passivation layer520is formed on the upper IMD layer704and the upper conductive features802, the second passivation layer520having a first portion902and a second portion904. In some embodiments, the first portion of the second passivation layer902is about vertically aligned with the first portion of the upper IMD layer706(see, e.g.,FIG. 7). In further embodiments, the second portion of the second passivation layer904is about vertically aligned with the second portion of the upper IMD layer708(see, e.g.,FIG. 7).

In some embodiments, a process for forming the second passivation layer520comprises depositing or growing a second dielectric layer522on the upper IMD layer704and the upper conductive features802. In further embodiments, a third dielectric layer524is deposited or grown on the second dielectric layer522, and a fourth dielectric layer526is deposited or grown on the third dielectric layer524. In yet further embodiments, the second dielectric layer522, the third dielectric layer524, and the fourth dielectric layer526may be deposited or grown by CVD, PVD, ALD, thermal oxidation, sputtering, some other deposition or growth process, or a combination of the foregoing.

As shown inFIG. 10, a plurality of conductive via openings1002are formed in the second passivation layer520. In some embodiments, a process for forming the plurality of conductive via openings1002comprises performing a second patterning process on the second passivation layer520. In further embodiments, the second patterning process is substantially the same as the first passivation process, but utilizes a fourth reticle1004instead of the third reticle710to project a fourth image field onto a fourth masking layer (not shown). The second patterning process removes unmasked portions of the second passivation layer520, thereby forming the conductive via openings1002in the second passivation layer520.

In some embodiments, the fourth reticle1004has a fourth maximum image field size that is less than about 2,500 mm2. More specifically, the fourth maximum image field size may be less than or equal to about 858 mm2. In such embodiments, the fourth maximum image field size may have a maximum x-axis dimension less than or equal to about 26 mm and a maximum y-axis dimension (e.g., perpendicular to the x-axis dimension) less than or equal to about 33 mm. In further embodiments, the fourth maximum image field size may be substantially the same as the first maximum image field size and/or the third maximum image field size.

In some embodiments, the fourth reticle1004projects a fourth minimum feature size that is less than about 0.5 μm. More specifically, the fourth minimum feature size may be less than about 45 nm. In further embodiments, the fourth minimum feature size is substantially the same as first minimum feature size and/or the third minimum feature size.

As shown inFIG. 11, a first conductive layer1102is formed on the second passivation layer520and at least partially filling the plurality of conductive via openings1002(see, e.g.,FIG. 10). In some embodiments, a first portion of the first conductive layer1104is about vertically aligned with the first portion of the second passivation layer902(see, e.g.,FIG. 10). In further embodiments, a second portion of the first conductive layer1106is about vertically aligned with the second portion of the second passivation layer904(see, e.g.,FIG. 10). In further embodiments, the first conductive layer1102may be formed by, for example, CVD, PVD, ALD, sputtering, electrochemical plating, electroless plating, some other deposition process, or a combination of the foregoing. In yet further embodiments, the first conductive layer1102may comprise, for example, aluminum (Al), copper (Cu), tungsten (W), gold (Au), or the like.

As shown inFIG. 12, a plurality of conductive vias528are formed over/within the second passivation layer520. In some embodiments, formation of the conductive vias528completes formation of a first ICU406aand a second ICU406b. In some embodiments, a process for forming the plurality of conductive vias528comprises performing a third patterning process on the first conductive layer1102(see, e.g.,FIG. 11). In further embodiments, the third patterning process is substantially the same as the first passivation process, but utilizes a fifth reticle1202instead of the third reticle710to project a fifth image field onto a fifth masking layer (not shown). The third patterning process removes unmasked portions of the first conductive layer1102, thereby forming the conductive vias528over/within the second passivation layer520.

In some embodiments, the fifth reticle1202has a fifth maximum image field size that is less than about 2,500 mm2. More specifically, the fifth maximum image field size may be less than or equal to about 858 mm2. In such embodiments, the fifth maximum image field size may have a maximum x-axis dimension less than or equal to about 26 mm and a maximum y-axis dimension (e.g., perpendicular to the x-axis dimension) less than or equal to about 33 mm. In further embodiments, the fifth maximum image field size may be substantially the same as the first, third, and/or fourth maximum image field size.

In some embodiments, the fifth reticle1202projects a fifth minimum feature size that is less than about 0.5 μm. More specifically, the fifth minimum feature size may be less than about 45 nm. In further embodiments, the fifth minimum feature size is substantially the same as the first, third, and/or fourth minimum feature size.

As shown inFIG. 13, a dielectric layer1302is formed over the second passivation layer520and the plurality of conductive vias528, the dielectric layer1302having a first portion1304and a second portion1306. In some embodiments, the first portion of the dielectric layer1304is about vertically aligned with the first portion of the second passivation layer902(see, e.g.,FIG. 9). In further embodiments, the second portion of the dielectric layer1306is about vertically aligned with the second portion of the second passivation layer904(see, e.g.,FIG. 9). In further embodiments, a process for forming the dielectric layer1302comprises depositing or grown the first passivation layer102by CVD, PVD, ALD, thermal oxidation, sputtering, some other deposition or growth process, or a combination of the foregoing. In yet further embodiments, the dielectric layer1302may comprise, for example, an oxide (e.g., SiO2), a nitride (e.g., SiN), an oxy-nitride (e.g., SiOXNY), or the like.

As shown inFIG. 14, a first passivation layer102having a plurality of openings114is formed on the second passivation layer520and the plurality of conductive vias528, the first passivation layer102having a first portion106aand a second portion106b. In some embodiments, the first portion of the first passivation layer106acorresponds to the first portion of the dielectric layer1304(see, e.g.,FIG. 13). In further embodiments, the second portion of the first passivation layer106bcorresponds to the second portion of the dielectric layer1306(see, e.g.,FIG. 9).

In some embodiments, a process for forming the first passivation layer102comprises performing a fourth patterning process on the dielectric layer1302(see, e.g.,FIG. 13). In further embodiments, the fourth patterning process is substantially the same as the first passivation process, but utilizes a first reticle108instead of the third reticle710to project a first image field onto a first masking layer (not shown). The fourth patterning process removes unmasked portions of the dielectric layer1302, thereby forming the first passivation layer102having the plurality of openings disposed therein.

In some embodiments, the first reticle108has a first maximum image field size that is less than about 2,500 mm2. More specifically, the first maximum image field size may be less than or equal to about 858 mm2. In such embodiments, the first maximum image field size may have a maximum x-axis dimension less than or equal to about 26 mm and a maximum y-axis dimension (e.g., perpendicular to the x-axis dimension) less than or equal to about 33 mm. In further embodiments, the first maximum image field size may be substantially the same as the as the first, third, fourth, and/or fifth maximum image field size.

In some embodiments, the first reticle108projects a first minimum feature size that is less than about 0.5 μm. More specifically, the first minimum feature size may be less than about 45 nm. In further embodiments, the first minimum feature size is substantially the same as the first, third, fourth, and/or fifth minimum feature size.

As shown inFIG. 15, a second conductive layer1502is formed over the first passivation layer102and the conductive vias528. In some embodiments, a process for forming the second conductive layer1502comprises depositing the second conductive layer1502on the first passivation layer102and at least partially in the openings114of the first passivation layer102. In further embodiments, the second conductive layer1502is deposited as a continuously layer that extends over the first portion106aand the second portion of the first passivation layer106b. In further embodiments, the second conductive layer1502may be deposited by, for example, CVD, PVD, ALD, sputtering, electrochemical plating, electroless plating, some other deposition process, or a combination of the foregoing. In yet further embodiments, the second conductive layer1502may comprise, for example, aluminum (Al), copper (Cu), tungsten (W), gold (Au), some other conductive material, or a combination of the foregoing.

As shown inFIG. 16, a plurality of patterned conductive layers202are formed on the first passivation layer102and the conductive vias528. In some embodiments, at least one of the patterned conductive layers202electrically couples the first ICU406ato the second ICU406bby bridging a region of the first passivation layer102disposed between the first ICU406aand the second ICU406b. In further embodiments, the region of the first passivation layer102disposed between the first ICU406aand the second ICU406bis disposed over an isolation region408that electrically isolates the first ICU406afrom the second ICU406b. In yet further embodiments, the patterned conductive layers202are redistribution layers (RDLs).

In some embodiments, a process for forming the patterned conductive layers202comprises performing a fifth patterning process on the second conductive layer1502(see, e.g.,FIG. 15). In further embodiments, the fifth patterning process comprises forming a second masking layer (not shown) (e.g., a negative/positive photoresist) on the second conductive layer1502. The second masking layer may be formed by, for example, a spin-on process.

A second reticle204having a second maximum image field size is positioned at a third location over the second masking layer, the second maximum image field size being a maximum area that the second reticle204may expose to radiation while projecting a second minimum feature size. In some embodiments, the second maximum field size is greater than about 858 mm2. In such embodiments, the second maximum image field size may have a minimum x-axis dimension greater than about 26 mm and a minimum y-axis dimension (e.g., perpendicular to the x-axis dimension) greater than about 33 mm. In further embodiments, the second maximum field size may be greater than or equal to about 2,500 mm2. In such embodiments, the second maximum image field size may have a minimum x-axis dimension greater than or equal to about 50 mm and a minimum y-axis dimension (e.g., perpendicular to the x-axis dimension) greater than or equal to about 50 mm. In further embodiments, the second minimum feature size may be greater than or equal to about 0.5 μm. In yet further embodiments, the second minimum feature size may be greater than the first, third, fourth, and fifth minimum feature size.

Thereafter, radiation is passed through the second reticle204at the third location, such that a second image field covering a majority of the first portion106aand a majority of the second portion of the first passivation layer106bis projected onto a first portion of the second masking layer. The second image field comprises a second defined pattern of radiation having the second minimum feature size. The radiation reacts with the second masking layer, such that regions of the second making layer exposed to the radiation are more (or less) soluble in a developing agent than regions of the second masking layer that are not exposed to the radiation.

In some embodiments, a size/shape of the first portion of the second masking layer corresponds to the second maximum field size projected onto the second masking layer at the third location. In further embodiments, the first portion of the second masking layer covers a majority of the first portion106aand a majority of the second portion of the first passivation layer106b. In further embodiments, the first portion of the second masking layer has a perimeter that is enclosed by a combined perimeter of the first portion106aand the second portion of the first passivation layer106b. In other embodiments, the perimeter of the first portion of the second making layer is about vertically aligned with the combined perimeter of the first portion106aand the second portion of the first passivation layer106b.

Thereafter, the second masking layer is developed by exposing the second masking layer to the developing agent to remove portions of the second masking layer that were exposed (or not exposed) to the radiation. An etching process (e.g., wet or dry etching) is then performed to remove unmasked portions of the second conductive layer1502(e.g., portions not covered by the developed second masking layer), thereby forming the plurality of patterned conductive layers202. Subsequently, the remaining portions of the second masking layer are stripped from the patterned conductive layers202.

As shown inFIG. 17, a third passivation layer532is formed over the first passivation layer102and the patterned conductive layers202. In some embodiments, the third passivation layer532may be formed with a substantially planar upper surface. In further embodiments, a process for forming the third passivation layer532may comprise depositing or growing the third passivation layer532by CVD, PVD, ALD, thermal oxidation, sputtering, some other deposition or growth process, or a combination of the foregoing. In yet further embodiments, formation of the third passivation layer532completes formation of the large field IC208.

By forming the patterned conductive layers202with the second image field206, the large field ICs208may be formed without overlapping the first image field projected at the first location with the first image field projected at the second location. Thus, the large field ICs208may be formed without a field stitching process (or by reducing a number of field stitching process(es) needed to form the large field ICs208). Accordingly, the cycle time for forming the large field ICs208may be reduced. In addition, because the large field ICs208may be formed without the field stitching process, minimum features sizes may not needed to be relaxed to compensate for the field stitching process. Accordingly, the density of semiconductor devices on the large field IC may be increased.

As shown inFIG. 18, a large field die304is formed by singulating the large field IC208from a semiconductor wafer104(see, e.g.,FIG. 17). In some embodiments, the large field die304comprises the large field IC208disposed on a semiconductor substrate402. In further embodiments, a process for forming the large field die304comprises performing a series of cuts into the semiconductor wafer104to form a plurality of scribe lines306. Subsequently, a mechanical force is applied to the semiconductor wafer104to singulate the large field die304from the semiconductor wafer104. In further embodiments, the cut may be performed by, for example, mechanical sawing, laser cutting, or the like.

As illustrated inFIG. 19, a flowchart1900of some embodiments of a method for forming a large field die with reduced cycle time is provided. While the flowchart1900ofFIG. 19is illustrated and described herein as a series of acts or events, it will be appreciated that the illustrated ordering of such acts or events is not to be interpreted in a limiting sense. For example, some acts may occur in different orders and/or concurrently with other acts or events apart from those illustrated and/or described herein. Further, not all illustrated acts may be required to implement one or more aspects or embodiments of the description herein, and one or more of the acts depicted herein may be carried out in one or more separate acts and/or phases.

At1902, a large field integrated circuit (IC) is formed on a semiconductor wafer.FIGS. 7-17illustrate a series of cross-sectional view of some embodiments corresponding to act1902.

At1902a, to form the large field IC, a first integrated circuit unit (ICU) and a second integrated circuit are formed on the semiconductor wafer.FIGS. 7-12illustrate a series of cross-sectional view of some embodiments corresponding to act1902a.

At1902b, a dielectric layer is formed over the first ICU and the second ICU, the first dielectric layer having a first portion covering the first ICU and a second portion covering the second ICU.FIG. 13illustrates a cross-sectional view of some embodiments corresponding to act1902b.

At1902c, the first portion of the dielectric layer is patterned by projecting a first image field over the first portion of the dielectric layer.FIG. 14illustrates a cross-sectional view of some embodiments corresponding to act1902c.

At1902d, the second portion of the dielectric layer is patterned by projecting the first image field over the second portion of the dielectric layer, where patterning the first portion and the second portion of the dielectric layer forms a passivation layer having a third portion that corresponds to the first portion of the dielectric layer and a fourth portion that corresponds to the second portion of the dielectric layer.FIG. 14illustrates a cross-sectional view of some embodiments corresponding to act1902d.

At1902e, a conductive layer is formed on the passivation layer.FIG. 15illustrates a cross-sectional view of some embodiments corresponding to act1902e.

At1902f, the conductive layer is patterned by projecting a second image field over the conductive layer, the second image field covering a majority of the third portion and a majority of the fourth portion of the passivation layer. A patterned conductive layer that electrically couples the first ICU to the second ICU is formed by patterning the conductive layer.FIG. 16illustrates a cross-sectional view of some embodiments corresponding to act1902f.

At1904, a large field die is formed by singulating the large field IC from the semiconductor wafer.FIG. 18illustrates a cross-sectional view of some embodiments corresponding to act1904.

In some embodiments, the present application provides a method for forming an integrated circuit. The method includes forming a first layer over a semiconductor wafer, the first layer having a first portion and a second portion. The first portion of the first layer is patterned by passing radiation through a first reticle to project a first image field over the first portion of the first layer, where the first portion of the first layer corresponds to the first image field. The second portion of the first layer is patterned by passing radiation through a second reticle to project a second image field over the second portion of the first layer, where the second portion of the first layer corresponds to the second image field. A second layer is formed over the first layer. The second layer is patterned by passing radiation through a third reticle to project a third image field over the second layer, where the third image field covers a majority of the first portion and a majority of the second portion of the first layer.

In other embodiments, the present application provides a method for forming an integrated circuit. The method includes forming a first integrated circuit unit (ICU) on a first region of a semiconductor wafer by passing radiation through a first reticle to project a first image field toward the first region of the semiconductor wafer, where the first region of the semiconductor wafer corresponds to a maximum image field size of the first reticle. A second ICU is formed on a second region of the semiconductor wafer by passing radiation through a second reticle to project a second image field toward the second region of the semiconductor wafer, where the second region of the semiconductor wafer corresponds to a maximum image field size of the second reticle, and where an isolation region separates and electrically isolates the first ICU from the second ICU. A passivation layer is formed over the first ICU, the isolation region, and the second ICU. A conductive layer is formed over the passivation layer. The conductive layer is patterned by passing radiation through a third reticle to project a third image field toward the semiconductor wafer, where the third image field covers a majority of the first region and a majority of the second region of the semiconductor wafer.

In yet other embodiments, the present application provides an integrated circuit. The integrated circuit includes a semiconductor substrate. A first integrated circuit unit (ICU) is disposed over a first region of the semiconductor substrate. A second ICU is disposed over a second region of the semiconductor substrate. An isolation region is disposed between the first ICU and the second ICU, where the isolation region electrically isolates the first ICU from the second ICU. A passivation layer covers the first ICU, the isolation region, and the second ICU. A patterned conductive layer is disposed over the passivation layer and electrically couples the first ICU to the second ICU, where the patterned conductive layer electrically couples the first ICU to the second ICU by bridging a portion of the passivation layer covering the isolation region.