Structures and methods for fabricating semiconductor devices using fin structures

A shallow trench isolation (STI) structure is formed on a substrate. Part of the STI structure is removed to form a first fin structure and a second fin structure extending above a support structure on the substrate. A first part of the STI structure is located between the first fin structure and the second fin structure and has a first top surface higher than an interface between the first fin structure and the support structure. A second part of the STI structure is located adjacent to the first fin structure and has a second top surface lower than the interface between the first fin structure and the support structure. An etching process is performed to remove part of the first fin structure and the second fin structure. Part of the support structure adjacent to the second part of the STI structure is removed during the etching process.

BACKGROUND

The technology described in this disclosure relates generally to semiconductor devices and more particularly to fabrication of semiconductor devices.

As feature sizes of semiconductor devices continue to shrink, various problems, such as short-channel effects and poor sub-threshold characteristics, often become severe in traditional planar devices. Novel device geometries with enhanced performance, such as FinFETs, have been explored to push toward higher packing densities in devices and circuits. FinFETs usually include semiconductor fin structures formed vertically on a substrate. One or more gate structures are formed over and along the sides of the fin structures to produce faster, more reliable and better-controlled transistors.

DETAILED DESCRIPTION

To enhance device performance, strain in a transistor channel can be adjusted to achieve higher electron mobility (or hole mobility) and thereby conductivity through the channel. For a FinFET, source/drain regions can be formed through epitaxial growth, and volumes of the source/drain regions affect strain in a channel region of the FinFET. Particularly, increasing the volumes of the source/drain regions can increase the strain in the channel region of the FinFET, and thus increase the conductivity through the channel. The present disclosure describes structures and methods for increasing the volumes of certain source/drain regions so as to increase the strain in the channel region of a FinFET.

FIG. 1depicts an example diagram showing a device structure for fabricating semiconductor devices, in accordance with some embodiments. As shown inFIG. 1, the device structure100includes a group of fin structures (e.g., the structures102,104,106and108) formed approximately parallel to each other on a substrate110for fabricating semiconductor devices (e.g., FinFETs). Specifically, the fin structures102,104,106and108extend above support structures112,114,116and118on the substrate110respectively. In addition, the support structures112,114,116and118are separated from each other by shallow trench isolation (STI) structures (e.g., the structure120). A cutline122(e.g., Y-cut) extends across the fin structures102,104,106and108, and another cutline124(e.g., X-cut) extends perpendicular to the cutline122(e.g., Y-cut). In some embodiments, the group of fin structures approximately parallel to each other include two fin structures, three fin structure, or more than four fin structures.

In some embodiments, the substrate110includes silicon, germanium, silicon carbide, gallium arsenide, indium arsenide, indium phosphide, or other suitable materials. The substrate110may include one or more epitaxial layers, may be strained for performance enhancement, and/or may include a silicon-on-insulator structure. The STI structures (e.g., the structure120) include silicon oxide, silicon nitride, silicon oxynitride, fluoride-doped silicate glass (FSG), and/or a low-k dielectric material. The fin structures102,104,106and108include silicon germanium, and the support structures112,114,116and118include silicon.

In certain embodiments, the device structure100is formed through multiple processes. For example, one or more trenches are formed through a dry etching process (e.g., inductively coupled plasma, transformer coupled plasma, electron cyclotron resonance, reactive ion etch) on the substrate110. The trenches are then filled with one or more dielectric materials (e.g., high density plasma oxide, sub-atmospheric chemical-vapor-deposition oxide, or flowable chemical-vapor-deposition oxide) through deposition. A chemical-mechanical polishing (CMP) process is performed to remove part of the dielectric materials.

FIG. 2depicts an example diagram showing a cross-sectional view along the cutline122after the CMP process, in accordance with some embodiments. The dielectric materials on top of the fin structures102,104,106and108are removed during the CMP process. As shown inFIG. 2, part of the STI structure (e.g.,202) between the fin structures102,104,106and108(e.g., “inner” part) has a top surface higher than a top surface of another part of the STI structure (e.g.,204) in regions away from the fin structures102,104,106and108(e.g., “outer” part).

In some embodiments, a well implantation process is performed after the CMP process. For example, boron-based materials can be used for P-well implantation, and phosphorous-based materials or arsenic-based materials can be used for N-well implantation. A well annealing process, such as millisecond annealing, rapid thermal annealing (e.g., from about 1 second to about 3 seconds) and soak annealing (e.g., from about 10 seconds to about 30 seconds), may be carried out at a temperature in a range of about 800° C. to about 1350° C.

The dielectric materials in the STI structure are further removed through an etching process to generate the device structure100, as shown inFIG. 3. For example, the dielectric materials are further removed through a dry etching process using reaction gases (e.g., a mixture of hydrogen fluoride and ammonia, or a mixture of nitrogen trifluoride and ammonia) with or without plasma. In another example, the dielectric materials are further removed through a wet etching process using a diluted hydrogen fluoride solution. As shown inFIG. 3, part of the STI structure (e.g.,302) between the fin structures102,104,106and108(e.g., “inner” part) has a top surface higher than an interface between the fin structure102and the support structure112. Another part of the STI structure (e.g.,304) in regions away from the fin structures102,104,106and108(e.g., “outer” part) has a top surface lower than the interface between the fin structure102and the support structure112. For example, the support structure112is partially exposed on the side adjacent to the outer part of the STI structure (e.g.,304).

A fin-width-reduction process is performed to remove part of the fin structures102,104,106and108, as shown inFIG. 4(A)andFIG. 4(B).FIG. 4(A)depicts an example diagram showing a cross-sectional view along the cutline122, andFIG. 4(B)depicts an example diagram showing a cross-sectional view along the cutline124. As shown inFIG. 4(B), part of the support structure112that is exposed on the side adjacent to the outer part of the STI structure (e.g.,304) is removed. The support structure112is etched at a higher rate than the fin structures102,104,106and108.

In some embodiments, the fin-width-reduction process includes a wet etching process performed using a solution including ammonium hydroxide, ammonium peroxide mixture, hydrochloric acid, diluted hydrofluoric acid, or other suitable materials. The wet etching process is performed at a temperature of about 60° C. for about 270 seconds. In certain embodiments, the fin-width-reduction process includes a dry etching process performed using reaction gases (e.g., CF4, SF6, BCl3, Cl2, HBr, O2, or other suitable gases), such as inductively coupled plasma, transformer coupled plasma, electron cyclotron resonance, and reactive ion etch.

Multiple processes may be performed after the fin-width-reduction process. For example, dummy gate dielectric materials and dummy gate structures (e.g., polysilicon) may be formed. Dummy gate structures are formed using processes such as photolithography, etching, and/or other suitable processes. A seal spacer is formed through deposition and etching. In addition, low-dose drain (LDD) regions are formed through implantation and annealing. Dummy spacers for N-type devices are formed through deposition and etching. N-type strained source/drain (NSSD) etching is performed, and source/drain regions for N-type devices are formed through epitaxial growth. Then, the dummy spacers for N-type devices are removed through etching. Dummy spacers for P-type devices are formed through deposition and etching. P-type strained source/drain (PSSD) etching is performed, and source/drain regions for P-type devices are formed through epitaxial growth.

FIG. 5depicts an example diagram showing a cross-sectional view of the device structure100including source/drain regions, in accordance with some embodiments. As shown inFIG. 5, a hard mask layer (e.g., the layer502), a spacer (e.g., the spacer504), and a gate structure (e.g., the structure506) are formed on each of the fin structures102,104,106and108. In-fin source/drain regions (e.g., the region510) are formed through epitaxial growth between the fin structures102,104,106and108. A fin-end source/drain region512is formed through epitaxial growth between the fin structure102and the outer part of the STI structure (e.g.,304), and another fin-end source/drain region514is formed through epitaxial growth between the fin structure108and another outer part of the STI structure (e.g.,516).

As described above, part of the support structure underneath the fin structure102adjacent to the outer part of the STI structure (e.g.,304) is removed during the fin-width-reduction process. Thus during epitaxial growth of the source/drain regions, the fin-end source/drain region512between the fin structure102and the outer part of the STI structure (e.g.,304) grows much larger than the in-fin source/drain regions. For example, the volume of the fin-end source/drain region512is much larger than the volume of the in-fin source/drain region510. The large volume of the fin-end source/drain region512increases the strain in the channel of a FinFET fabricated from the device structure100, and thus increases the conductivity through the channel. In some embodiments, the height of the fin-end source/drain region512is larger than the height of the in-fin source/drain region510. In certain embodiments, the in-fin source/drain region510includes a top portion of a height H1and a bottom portion of a height H2. The fin-end source/drain region512includes a top portion of a height H3and a bottom portion of a height H4, where H3is larger than H1and H4is larger than H2.

In some embodiments, subsequently, multiple processes are performed to fabricate FinFETs from the device structure100. For example, the dummy spacers for P-type devices are removed through etching. A main spacer is formed through deposition and etching. A source/drain implantation process and an annealing process are performed. Hard mask layers (e.g., silicon dioxide) are removed, and a contact-etch-stop layer (CESL) is formed through deposition. In addition, an inter-layer dielectric (ILD) layer is formed through deposition, and a CMP process is performed to remove part of the ILD layer. The dummy gate structures and the dummy gate dielectric materials are removed. Then, a gate interfacial layer and a gate dielectric material (e.g., one or more high-k materials) are formed through deposition. A metal gate layer is formed through deposition.

FIG. 6depicts another example diagram showing a cross-sectional view of a device structure including source/drain regions, in accordance with some embodiments. As shown inFIG. 6, a single fin structure602is formed between two parts of a STI structure (e.g.,604and606). A hard mask layer608, a spacer610and a gate structure612are formed on the fin structures602. Part of a support structure618underneath the fin structure602adjacent the two parts of a STI structure (e.g.,604and606) is removed during a fin-width-reduction process. Two fin-end source/drain regions614and616are formed through epitaxial growth. A volume of a top portion of the fin-end source/drain region614is smaller than that of a bottom portion of the fin-end source/drain region614. Similarly, a volume of a top portion of the fin-end source/drain region616is smaller than that of a bottom portion of the fin-end source/drain region616. In some embodiments, the top portion of the fin-end source/drain region614has a height H3much smaller than that of the bottom portion of the fin-end source/drain region614.

FIG. 7depicts an example diagram showing a process for fabricating semiconductor devices, in accordance with some embodiments. At802, a STI structure is formed on a substrate. At804, part of the STI structure is removed to form a first fin structure and a second fin structure extending above a support structure on the substrate. A first part of the STI structure is located between the first fin structure and the second fin structure and has a first top surface higher than an interface between the first fin structure and the support structure. A second part of the STI structure is located adjacent to the first fin structure and has a second top surface lower than the interface between the first fin structure and the support structure. At806, an etching process is performed to remove part of the first fin structure and the second fin structure, part of the support structure adjacent to the second part of the STI structure being removed during the etching process. At808, a fin-end source/drain region is formed adjacent to the second part of the STI structure and an in-fin source/drain region is formed adjacent to the first part of the STI structure. A first volume associated with the fin-end source/drain region is larger than a second volume associated with the in-fin source/drain region.

According to one embodiment, a method is provided for fabricating semiconductor devices. A shallow trench isolation (STI) structure is formed on a substrate. Part of the STI structure is removed to form a first fin structure and a second fin structure extending above a support structure on the substrate. A first part of the STI structure is located between the first fin structure and the second fin structure and has a first top surface higher than an interface between the first fin structure and the support structure. A second part of the STI structure is located adjacent to the first fin structure and has a second top surface lower than the interface between the first fin structure and the support structure. An etching process is performed to remove part of the first fin structure and the second fin structure. Part of the support structure adjacent to the second part of the STI structure is removed during the etching process.

According to another embodiment, a device structure includes a first fin structure, a second fin structure, one or more gate structures, a first in-fin source/drain region, and a fin-end source/drain region. The first fin structure is formed on a substrate. The second fin structure is formed on the substrate. The one or more gate structures are formed on the first fin structure and the second fin structure. The first in-fin source/drain region is associated with a first volume and is disposed between the first fin structure and the second fin structure. The fin-end source/drain region is associated with a second volume larger than the first volume. The first fin structure is disposed between the first in-fin source/drain region and the fin-end source/drain region. The gate structures, the first in-fin source/drain region, and the fin-end source/drain region are configured to form one or more transistors.

According to yet another embodiment, a device structure includes a fin structure, a gate structure, a first source/drain region, and a second source/drain region. The fin structure is formed on a substrate. The gate structure is formed on the fin structure. The first source/drain region includes a first top portion associated with a first volume and a first bottom portion associated with a second volume larger than the first volume. The second source/drain region includes a second top portion associated with a third volume and a second bottom portion associated with a fourth volume larger than the third volume. The gate structure, the first source/drain region and the second source/drain region are configured to form a transistor.