METHOD FOR REMOVING EDGE OF SUBSTRATE IN SEMICONDUCTOR STRUCTURE

A method for treating a semiconductor structure includes: forming the semiconductor structure which includes a carrier substrate, a device substrate, a semiconductor device formed on the device substrate, and a bonding layer formed to bond the semiconductor device with the carrier substrate, the device substrate having an upper surface which is faced upwardly, and which is opposite to the semiconductor device; and directing a chemical fluid to impinge the upper surface of the device substrate so as to remove an edge portion of the device substrate.

BACKGROUND

In semiconductor device fabrications, wafer edge trimming is a common practice to protect the wafers from damages during subsequent processing of the wafers and/or the semiconductor devices, yet in some cases, the trimming process may undesirably damage the semiconductor devices. In view of this, the industry has put much efforts in developing different wafer edge trimming methods that provide better protection to the wafers and the semiconductor devices.

DETAILED DESCRIPTION

The present disclosure is directed to a method for treating a semiconductor structure, in which the treatment includes removing an edge portion of a device substrate, thereby obtaining a treated semiconductor structure. The semiconductor structure may be formed by bonding a semiconductor device on a device substrate to a carrier substrate, and by the method described thereafter, the semiconductor device originally formed on the device substrate can be transferred to the carrier substrate.

FIG.1is a flow diagram illustrating the method for treating the semiconductor structure in accordance with some embodiments.FIGS.2to6Billustrate schematic views of the intermediate stages of the method in accordance with some embodiments. Some portions inFIGS.2to6Bare omitted for the sake of brevity. Additional steps can be provided before, after or during the method, and some of the steps described herein may be replaced by other steps or be eliminated.

Referring toFIG.1and the example illustrated inFIG.2, the method begins at step101, where a semiconductor structure100is formed.FIG.2is an enlarged schematic view of the semiconductor structure100in accordance with some embodiments. The semiconductor structure100includes a carrier substrate10, a device substrate20, a semiconductor device30formed on the device substrate20, and a bonding layer40that bonds the semiconductor device30with the carrier substrate10. The device substrate20has a proximate surface and a distal surface relative to the carrier substrate10.

Each of the carrier substrate10and the device substrate20may independently include, for example, but not limited to, elemental semiconductor materials, such as crystalline silicon, diamond, or germanium; compound semiconductor materials, such as silicon carbide, gallium arsenic, indium arsenide, or indium phosphide; or alloy semiconductor materials, such as silicon germanium, silicon germanium carbide, gallium arsenic phosphide, or gallium indium phosphide. In addition, each of the carrier substrate and the device substrate20may be a bulk silicon substrate, a silicon-on-insulator (SOI) substrate, or a germanium-on-insulator (GOI) substrate. Other suitable materials for the carrier substrate10and the device substrate20are within the contemplated scope of the present disclosure. In some embodiments, each of the carrier substrate10and the device substrate20includes silicon.

In some embodiments, the carrier substrate10and the device substrate20may be independently doped by a dopant. In certain embodiments, the dopant is a p-type impurity, for example, but not limited to boron. Other suitable impurities for doping the carrier substrate10and/or the device substrate20are within the contemplated scope of the present disclosure.

In certain embodiments, the carrier substrate10may have a dopant concentration substantially the same as that of the device substrate20. In other embodiments, the carrier substrate10may have a dopant concentration different from that of the device substrate20. In some embodiments, the device substrate20has a dopant concentration higher than that of the carrier substrate10. Such difference in dopant concentration may facilitate step104to be conducted subsequently, and will be further discussed hereinafter.

In some embodiments, the device substrate20and/or the carrier substrate10may each be a 12-inch, or 8-inch wafer. It should be noted that other suitable sizes of the device substrate20and/or the carrier substrate10are within the contemplated scope of the present disclosure.

The semiconductor device30may include a front-end-of-line (FEOL) portion formed on the device substrate20and including, for instance, a logic circuitry with transistors, a memory circuitry having memory elements, passive elements, and/or other suitable elements; a middle-end-of-line (MEOL) portion formed on the FEOL portion and including, for example, metal contacts to be electrically connected to electrodes of the elements in the FEOL portion (for example, but not limited to, gate, source, and drain electrodes of the transistors), interlayer dielectric (ILD) layers among the metal contacts, and or other suitable elements; and a back-end-of-line (BEOL) portion formed on the MEOL portion and including metallization layers (metal lines or vias) formed to electrically connect the metal contacts with an external circuitry out of the semiconductor device30, and additional ILD layers among the metallization layers. The semiconductor device30may be formed using any appropriate materials and/or methods. The semiconductor device30may be any desired semiconductor device, for instance, but not limited to, gate-all around (GAA) nanosheet structure device as shown inFIG.9A. The semiconductor device30may have a predetermined size and thickness according to layout of the design. In some embodiments, the semiconductor device30has a thickness ranging from about 1 μm to about 3 μm.

Within the semiconductor device30, some of the metal components, for instance, the metal contacts, or the metal lines that are made of, e.g., copper, may undesirably cause contamination to other components of the semiconductor device30, therefore, it is important to avoid exposing these metal components in steps to be performed subsequently. In addition, within the semiconductor device30, some other components, for instance, dielectric layers that are made of low k materials, are liable to any dry etching process performed in further processing of the semiconductor structure100, therefore, it is also important to avoid exposing these low k materials in steps to be performed subsequently.

The bonding layer40is formed to bond the semiconductor device30with the carrier substrate10. The bonding layer40may have a thickness ranging from about 250 Å to about 1 μm. In some embodiments, the bonding layer40is an oxide-oxide bonding layer, i.e., each of the semiconductor device30and the carrier substrate10is first formed with, for instance, a silicon dioxide layer. The silicon dioxide layer of each of the semiconductor device30and the carrier substrate10is then subjected to a plasma treatment to break Si—O—Si bond within silicon dioxide into Si—O bonds, followed by rinsing with water to create a plurality of hydrogen bonds among water molecules and O atom of Si—O bonds. The two silicon dioxide layers are then aligned and brought close to each other so as to bond with each other through Si—O—Si covalent bonds. An annealing process is then performed so as to remove water molecules. As such, the two silicon dioxide layers cooperate to form the bonding layer40. Other suitable materials and/or processes for forming the bonding layer40are within the contemplated scope of the present disclosure.

Referring toFIG.1and the example illustrated inFIG.3, the method proceeds to step102, where a sealing element60is formed at a void that is positioned between the carrier substrate10and the device substrate20and that surrounds the semiconductor device30and the bonding layer40. In some embodiments, the semiconductor structure100is first set to rotate, then a sealing element material which is to form the sealing element60is applied around the semiconductor device30and the bonding layer40, thereby forming the sealing element60that fills the void between the carrier substrate and the device substrate20. Example of the sealing element material is, for example, but not limited to, epoxy. Other suitable materials or processes for forming the sealing element60are within the contemplated scope of the present disclosure. The sealing element60is formed to avoid chipping of edge of the device substrate20.

Referring toFIG.1and the example illustrated inFIG.4, the method proceeds to step103, where the distal surface of the device substrate20shown inFIG.3is subjected to a planarization process. Step103is performed to reduce a thickness of the device substrate20. By performing the planarization process, the planarized device substrate, denoted by the numeral20′, has a planarized surface opposite to the proximate surface. In some embodiments, the planarization process is a grinding process performed using, for instance, but not limited to, a metal grinding blade. Other suitable processes or devices for performing the planarization process are within the contemplated scope of the present disclosure. In some embodiments, during the grinding process, a thickness of the planarized device substrate20′ is optically examined by, for instance, but not limited to, a laser system. The grinding process stops when the planarized device substrate20′ remaining in the semiconductor structure100is confirmed to have a predetermined thickness. In some embodiments, the predetermined thickness may range from about 3 μm to about 50 μm. Other suitable methods for examining and monitoring the thickness of the planarized device substrate20′ are within the contemplated scope of the present disclosure.

After step103, the planarized device substrate20′ is said to have an upper surface opposite to the proximate surface. That is, the upper surface is faced upwardly, and is opposite to the semiconductor device30. In addition, the planarized device substrate20′ is said to include a main portion21, and an edge portion22surrounding the main portion21.

Referring toFIG.1and the examples illustrated inFIGS.5A to5C, the method proceeds to step104, where the edge portion22of the device substrate20′ is removed using a chemical fluid51.FIGS.5A and5Bare enlarged schematic views respectively illustrating the semiconductor structure100prior to and after performing intermediate step104, whileFIG.5Cis a schematic view illustrating the semiconductor structure100being retained onto a structure retainer80.

In some embodiments, step104includes the sub-steps of: (i) retaining the semiconductor structure100on the structure retainer80in a manner that the planarized device substrate20′ is faced upwardly; (ii) rotating the semiconductor structure100with the structure retainer80; (iii) directing the chemical fluid51through a nozzle50so as to impinge and etch a peripheral region of the planarized upper surface of the device substrate20′; (iv) rinsing the etched semiconductor structure100with deionized water; and (v) drying the etched semiconductor structure100. During sup-steps (iii) to (v), sub-step (ii) is also performed simultaneously.

In sub-step (i), the semiconductor structure is centrally positioned on the structure retainer80, with the planarized upper surface of the device substrate20′ facing upward. Examples of the structure retainer80are a vacuum chuck and an electrostatic chunk. Other devices suitable for holding the semiconductor structure100are within the contemplated scope of the present disclosure.

In sub-step (ii), in some embodiments, the semiconductor structure100is rotated at a rotational speed ranging from about 30 revolutions per minute (rpm) to about 1500 rpm, for example, but not limited to, 1200 rpm. The semiconductor structure100is rotated about a rotation axis (A) normal to the planarized upper surface of the device substrate20′.

In sub-step (iii), the nozzle50is precisely positioned, so that the chemical fluid51is directed to reach the peripheral region of the planarized upper surface of the device substrate20′. In some embodiments, the nozzle50is positioned to satisfy the following descriptions. As shown inFIGS.5A and5C, there is an imaginary reference line (B) which is tangent to an edge of the carrier substrate10, and which is parallel to the rotational axis (A). A first distance (D1) is a distance between the reference line (B) and a point on the device substrate20′ at which the chemical fluid51reaches the device substrate20′ from the nozzle50. In some embodiments, the first distance (D1) ranges from about 0.7 mm to about 5 mm. In addition, a second distance (D2) is a minimal distance between the semiconductor device30and the reference line (B). In some embodiments, the second distance (D2) ranges from about 0.5 mm to about 4.8 mm, such as, but not limited to, 0.5 mm. In some embodiments, the first distance (D1) is greater than the second distance (D2). In some embodiments, the difference between the first and second distances (D1and D2) ranges from about 0.2 mm to about 4.5 mm. In some embodiments, the peripheral region (that is to be etched away by the chemical fluid51) is the device substrate20′ located within the first distance (D1) from the imaginary reference line (B).

In addition, the nozzle50has an outlet orifice52, (seeFIGS.5F and5G), such that the chemical fluid51is directed to flow along a flow line (L) via the outlet orifice52. As shown inFIG.5A, an included angle (θ) is formed between the flow line (L) and the planarized upper surface.FIG.5Dis a view similar to that ofFIG.5A, but illustrating an included angle (θ) different from that shown inFIG.5A. In some embodiments, the included angle (θ) may range from about 90° to about 160°. In some embodiments, a dimension of the outlet orifice52of the nozzle50ranges from about 0.1 mm to about 1.0 mm. In some embodiments, a flow rate of the chemical fluid51ranges from about 3 mL/min to about 50 mL/min. By virtue of the precise positioning of the nozzle50, in addition to the abovementioned parameters regarding flowing condition of the chemical fluid51, the method disclosed in the present disclosure is capable of removing the edge portion22, leaving the main portion21of the device substrate20′ with a sharp contour.

In some embodiments, the removal of the edge portion22using the chemical fluid51is conducted at a temperature ranging from about room temperature to about 70° C. for a time period ranging from about 30 s to about 3000 s, such as, but not limited to, 155 s. The chemical fluid51is a wet etchant, i.e., the edge portion22is removed by a wet etching process. In some embodiments, the chemical fluid51may be an acid chemical, a base chemical, or a combination thereof.

Examples of the acid chemical are, but not limited to, hydrogen fluoride (HF), nitric acid (HNO3), phosphoric acid (H3PO4), sulfuric acid (H2SO4), acetic acid (CH3COOH), or combinations thereof. In some cases, the acid chemical includes at least HF and HNO3. In other cases, the acid chemical includes one of H3PO4, H2SO4, CH3COOH, or combinations thereof, in addition to HF and HNO3. In an exemplary embodiment, the chemical fluid51is an acid chemical including HF, HNO3and CH3COOH. HF is present in an amount ranging from about 1 weight % (wt %) to about wt % based on 100 wt % of the chemical fluid51. HNO3is present in an amount ranging from about 1 wt % to about 30 wt % based on 100 wt % of the chemical fluid51. CH3COOH is present in an amount ranging from about 0 wt % to about 60 wt % based on 100 wt % of the chemical fluid51. Deionized water makes up the remainder, if any, based on 100 wt % of the chemical fluid51. When the device substrate20′ is subjected to an etching process using the chemical fluid51, the device substrate20′ may be etched at different etching rate by adjusting wt % ratio among different chemical species in the chemical fluid51. Other chemical species suitable for serving as the acid chemical are within the contemplated scope of the present disclosure.

In some embodiments, examples of the base chemical are, but not limited to, potassium hydroxide (KOH), tetramethylammonium hydroxide (TMAH), tetrabutylammonium hydroxide (TBAH), tetraethylammonium hydroxide (TEAH), ammonium hydroxide (NH4OH), or combinations thereof. In some embodiments, each of the species may be present in an amount ranging from about 1 wt % to about 50 wt % based on 100 wt % of the chemical fluid51. Deionized water makes up the remainder, if any, based on 100 wt % of the chemical fluid51. Other chemical species suitable for serving as the base chemical are within the contemplated scope of the present disclosure.

In some other embodiments, in which the chemical fluid51is a combination of both the acid chemical and the base chemical, the acid chemical and the base chemical are employed in a stepwise manner. For example, the acid chemical may be first used, followed by the base chemical.

One may decide to adopt the acid chemical, or the base chemical, or a combination thereof as the chemical fluid51according to practical needs. For instance, when the device substrate20′ including silicon is subjected to the wet etching process using the acid chemical as the chemical fluid51, such device substrate20′ may be etched at a relatively high etching rate, and the removal of edge portion22may be completed within a short period of time. Yet, considering that in some cases, where both the device substrate20′ and the carrier substrate10are made of silicon and thus are liable to be damaged by the chemical fluid51, while this step aims to remove mainly the edge portion22of the device substrate20′ but not the carrier substrate10, it is important to protect the carrier substrate10from damage due to the chemical fluid51. One way is to increase etching selectivity of the chemical fluid51over the device substrate20′, and details will be further discussed in the following paragraphs.

When the device substrate20′ and the carrier substrate10′ are subjected to the wet etching process using the chemical fluid51(no matter the case of using the acid chemical or the base chemical as the chemical fluid51), it is found that the device substrate20′ having a dopant concentration higher than that of the carrier substrate10will be etched at an etching rate higher than that of the carrier substrate10. The dopant may be, for example but not limited to, boron. Therefore, by adjusting dopant concentration of the device substrate20′ to be higher than the dopant concentration of the carrier substrate10, the chemical fluid may have a higher etching selectivity on the device substrate20′ than the carrier substrate10. In some embodiments, when the device substrate20′ is relatively heavily doped, e.g., with a dopant concentration ranging from about 1×1018atom/cm 3 to about 1×1021atom/cm 3, and the carrier substrate10is relatively lightly doped, e.g., with a dopant concentration ranging from about 1×1014atom/cm 3 to about 1×1017atom/cm 3, it is noted that the chemical fluid51exhibits a higher etching selectivity on the heavily doped device substrate20′ than the carrier substrate10. For instance, in some embodiments, the device substrate20′ may be etched by the chemical fluid51at an etching rate ranging from about 100 nm/min to about 20 μm/min, and the carrier substrate10may be etched by the chemical fluid51at an etching rate ranging from about 0 μm/min to about 0.1 μm/min. Such higher etching selectivity may effectively protect the carrier substrate10from being over damaged by the chemical fluid51.

Apart from adjusting dopant concentration of the carrier substrate10, in some embodiments, prior to sub-step (iii), a protective layer70is formed to cover an edge of the carrier substrate10, so as to prevent the carrier substrate10from damage due to etching by the chemical fluid51.FIG.5Eis similar toFIG.5B, except that the protective layer70is formed on the edge of the carrier substrate10.

In some embodiments, the protective layer70may include silicon oxides, or a carbon-including material. The carbon-including material may be represented by a chemical formula of CxHy, wherein x ranges from 1 to 6, and y ranges from 4 to 14. Examples of the carbon-including material are alkane, alkene or alkyne. In some exemplary embodiments, the carbon-including material is C2H6. Other suitable materials for forming the protective layer70are within the contemplated scope of the present disclosure. In some embodiments, the protective layer70includes silicon dioxide. The protective layer70may have a thickness ranging from about 3 nm to about 1 μm. The protective layer70may be formed by, for example, but not limited to, CVD, or spin coating. Other processes suitable for forming the protective layer70are within the contemplated scope of the present disclosure. Such protective layer70may be removed, or may be retained after step104. By forming the protective layer70, it is not necessary to prepare carrier substrate10and the device substrate20′ having different dopant concentration.

In sub-step (iv), the semiconductor structure100is rinsed with deionized water so as to remove any residue of the chemical fluid51on the semiconductor structure100. The rinsing process may be conducted at a temperature ranging from about 10° C. to about for a time period ranging from about 10 s to about 60 s. Other processes and/or materials suitable for removing residue of the chemical fluid51are within the contemplated scope of the present disclosure.

In sub-step (v), the semiconductor structure100is subjected to a drying process. In some embodiments, the drying process may be, for example, but not limited to, a spin drying process. The rotational speed may range from about 30 rpm to about 1500 rpm for a time period ranging from about 10 s to about 60 s. In other embodiments, the drying process may be an isopropyl alcohol (IPA) drying process. Other suitable processes for drying the semiconductor structure100are within the contemplated scope of the present disclosure.

FIG.5Fprovides a schematic view of a system adopted to perform step104in which the semiconductor structure100is shown, and some components therein are not drawn for the sake of brevity. The system includes a chamber53that accommodates the semiconductor structure100on the structure retainer80. The semiconductor structure100is set to rotate with the structure retainer80around the rotation axis (A). The nozzle can be actuated to move so as to precisely adjust position thereof. In sub-step (i), the outlet orifice52of the nozzle50is aligned on a point on the peripheral region of the planarized upper surface of the device substrate20′ of the semiconductor structure100(see alsoFIGS.5A and5D). Therefore, by rotating the semiconductor structure100, the chemical fluid50can be directed to impinge and etch the peripheral region in sub-step (iii), or the deionized water can be directed to rinse the etched semiconductor structure100in sub-step (iv). The system also includes a fan filter unit to supply air or in some embodiments, nitrogen gas to avoid oxidation of silicon material in the device substrate and/or the carrier substrate10of the semiconductor structure100(see alsoFIGS.5A and5D), but are not limited thereto. The system also includes a nitrogen gas supply unit for supplying nitrogen gas flow (denoted by arrows (D) inFIG.5F) around a peripheral region of a bottom surface of the semiconductor structure100. In some embodiments, the nitrogen gas supply unit has two outlets set across a diameter of the semiconductor structure100. Such configuration may avoid any contaminant reaching the main portion21of the device substrate20′, since step104aims to remove mainly the edge portion22. The system also include an exhaust gas evacuation unit, so that any exhaust gas generated during step104may be evacuated therethrough in a direction denoted by an arrow (E) inFIG.5F.

FIG.5Gis a view similar to that ofFIG.5F, but illustrating the system after completing step104. After completing the drying process, the chamber53is opened so as to permit the semiconductor structure100on the structure retainer80to be moved from a lower position, where the semiconductor structure100is represented by dotted lines, to an upper position, where the semiconductor structure100is represented by solid lines, to thereby take out the semiconductor structure100. It should be noted that other systems suitable for performing step104are within the contemplated scope of the present disclosure.

During step104, the edge portion22of the device substrate20′ is removed by the chemical fluid51, the semiconductor device30is unlikely to be affected by the chemical fluid51, and the carrier substrate10is well protected by either being lightly doped (relative to the device substrate20′) or being covered by the protective layer70, and thus, the semiconductor device30and the carrier substrate10may remain substantially intact. In comparison with a mechanical trimming process for removal of the edge portion22, the device substrate20′ is less likely to peel off when the edge portion22is removed using the chemical fluid51.

FIG.6Ashows an edge portion of the carrier substrate10in accordance with some embodiments.FIG.6Bis a view similar to that ofFIG.6A, but illustrating another edge portion of the carrier substrate10which includes a notch101on the edge portion. It is noted that the edge portion with or without the notch101is substantially not affected by the chemical fluid51during removal of the edge portion22of the device substrate20′, and remains intact on the carrier substrate10. The retainment of the notch101is conducive to providing alignment of the carrier substrate10in other steps to be performed subsequently, if any, or in further application of the semiconductor structure100.

In some embodiments, step104may further include a sub-step (vi) to remove the sealing element60shown inFIGS.5A and5D. In some embodiments, the sealing element60is removed by, for instance, but not limited to, a sulfuric peroxide mix (SPM) clean process, in which a mixture of sulfuric acid and hydrogen peroxide is used. Other processes and/or materials suitable for removing the sealing element60are within the contemplated scope of the present disclosure.

After completing step104, the treated semiconductor structure100may be further processed to be utilized in different applications. The following paragraphs provide an exemplary embodiment of further processing and application of the treated semiconductor structure100, in which the semiconductor device30is a GAA nanosheet device (seeFIG.9A). Other further processing and/or applications of the treated semiconductor structure100are within the contemplated scope of the present disclosure.

FIGS.7to8Billustrate schematic views of intermediate stages of the further processing of the semiconductor structure100shown inFIG.5B, so as to obtain a structure shown inFIG.9A. Referring to the examples illustrated inFIGS.5B,7and9A, the device substrate20′ (seeFIGS.5B and7) is removed until shallow trench isolation (STI) sections31are exposed, and semiconductor sections32which alternate with the STI sections31are also exposed (seeFIG.9A). Examples of a material for the semiconductor sections32may be similar to those for the device substrate20, and the semiconductor sections32may be made of a material the same as or different from that of the device substrate20.

In some embodiments, the removal of the device substrate20′ includes a plurality of etching processes and/or planarization processes that are performed in a stepwise manner. In each of the etching process or planarization process, a portion of the device substrate20′ is removed, and a thickness of the device substrate20′ is further reduced. Examples of the etching processes are, for example but not limited to, dry etching and/or wet etching. Example of the planarization process is, for example, but not limited to, a chemical-mechanical planarization (CMP) process. In some embodiments, the planarization process is employed so as to remove the device substrate20′ in a short period of time. In other embodiments, dry etching is employed so as to remove the device substrate20′ at a fair speed and a fair uniformity over the etched surface. In yet other embodiments, wet etching is employed so as to obtain a good uniformity over the etched surface. The wet etchant may include the acid chemical and/or the base chemical as mentioned above. Other suitable processes for removing the device substrate20′ are within the contemplated scope of the present disclosure.

Referring to the examples illustrated inFIGS.7and8A, an oxide layer90is formed over the structure shown inFIG.7. In some embodiments, the oxide layer90includes, for example, but not limited to silicon oxides, such as silicon dioxide. In some embodiments, the oxide layer90is formed by, for example, but not limited to, an atomic layer deposition (ALD) process. The oxide layer90formed by ALD process is found to have a good conformality. Other materials or methods suitable for forming the oxide layer90are within the contemplated scope of the present disclosure.

Referring to the example illustrated inFIGS.8A and8B, a planarization process is performed to remove the oxide layer90that is located on an upper surface of the semiconductor device30, leaving the remaining oxide layer, denoted by the reference numeral90′, that is located on a sidewall of the semiconductor device30, a sidewall of the bonding layer40, and an upper surface of the carrier substrate10. In some embodiments, the planarization process is a CMP process. Other methods suitable for the partial removal of the oxide layer90are within the contemplated scope of the present disclosure.

After the planarization process, the semiconductor device (i.e., the GAA nanosheet device)30is exposed.FIG.9Ais a fragmentary perspective view of the semiconductor structure100after the planarization process, in which the oxide layer90′ is omitted for the sake of brevity. As shown inFIG.9A, the GAA nanosheet device30includes the STI sections31and the semiconductor sections32in an upper part of the GAA nanosheet device30. The GAA nanosheet device30further includes a GAA nanosheet structure33, a MEOL section34and a BEOL section35that are sequentially disposed beneath the STI sections31and the semiconductor sections32in such order. The GAA nanosheet structure33includes a plurality of active portions33A respectively beneath the semiconductor sections32, and a plurality of dummy fins33B respectively beneath the STI sections31. The dummy fins33B may include any suitable dielectric materials. Each of the active portions33A includes a plurality of source/drain regions331and a plurality of stack regions332disposed to alternate with the source/drain regions331. Source/drain region(s) may refer to a source or a drain, individually or collectively dependent upon the context. The source/drain regions331may include an epitaxial semiconductor material doped with impurities. Each of the stack regions332includes a plurality of channel layers333each interconnecting two adjacent ones of the source/drain regions331, a plurality of gate features334alternating with the channel layers333, and a dielectric region330disposed on an upmost one of the gate features334. The channel layers333may include, for example, silicon, but not limited thereto. The dielectric region330may include, for example, silicon nitride, but not limited thereto. Each of the gate features334has a gate electrode335, a gate dielectric336surrounding the gate electrode335, two inner spacers337disposed to separate the gate electrode335and the gate dielectric336from being in contact with two adjacent ones of the source/drain regions331. The gate electrode335may include aluminum, tungsten, copper, other suitable materials, or combinations thereof. The gate dielectric336and the inner spacers337may each include silicon oxide, silicon nitride, silicon oxynitride, high dielectric constant (k) materials, other suitable materials, or combinations thereof. Other suitable materials and processes for forming the GAA nanosheet structure33are within the contemplated scope of the present disclosure.

The semiconductor structure100shown inFIG.9Amay be further subjected to a patterning process (seeFIG.9B), a re-fill process (seeFIG.9C), and a replacement process (seeFIGS.9D and9E) in sequence.FIGS.9B to9Eare partially enlarged views ofFIG.9Abut illustrating the structures respectively after these processes.

Referring toFIGS.9A and9B, in the patterning process, at least one of the semiconductor sections32is patterned to form a patterned semiconductor section321covering at least one of the source/drain portion331of a corresponding one of the active portions33A. In some embodiments, the patterning process may include: (i) forming a patterned mask layer (not shown) to cover a top surface of the structure shown inFIG.9A, the patterned mask layer being a patterned photoresist or a patterned hard mask and having at least one opening corresponding in position to the patterned semiconductor section321; (ii) etching the at least one of the semiconductor sections32through the opening of the patterned mask layer using dry etching, wet etching, other suitable processes, or combinations thereof, to expose the element(s) beneath the at least one of the semiconductor sections32; and (iii) removing the patterned mask layer. Other suitable patterning processes are within the contemplated scope of the present disclosure.

Referring toFIG.9C, in the re-fill process, first and second dielectric materials are sequentially deposited over the structure shown inFIG.9Busing CVD, physical vapor deposition (PVD), ALD or other suitable processes, followed by planarization using, for example, but not limited to, CMP, so that the first and second dielectric materials are respectively formed into a first dielectric layer337A and a second dielectric layer337B. The first and second dielectric layers337A,337B may be made of different dielectric materials. For example, the first dielectric layer337A is made of silicon nitride, and the second dielectric layer337B is made of silicon oxide. Other suitable materials and processes for the re-fill processes are within the contemplated scope of the present disclosure.

Referring toFIGS.9D and9E, in the replacement process, the patterned semiconductor section321is replaced with a barrier layer338and a via contact339(the dotted lines shown inFIG.9Arepresent the positions where the barrier layer338and the via contacts339may be formed). In some embodiments, the replacement process includes: (i) removing the patterned semiconductor section321using dry etching, wet etching, other suitable processes, or combinations thereof, to form a cavity320which exposes the at least one of source/drain portion331of the corresponding active portion33A; (ii) conformally forming a silicon nitride redeposition (SNR) layer for forming the barrier layer338over the structure with the patterned semiconductor section321removed, using, for example, but not limited to, CVD; (iii) selectively removing the SNR layer using, for example, but not limited to, antistrophic etching, to remove the SNR layer on upper surfaces of the STI sections31and the first and second dielectric layers337A,337B and on a bottom of the cavity320, thereby leaving the barrier layer338on inner sidewall surfaces of the cavity320; (iv) conformally depositing a metal material (for example, but not limited to, ruthenium (Ru)) for forming the via contact339over the structure formed with the barrier layer338, using, for example, PVD or other suitable process; and (v) performing a planarization process to remove an excess of the metal material to thereby obtain the via contact339. Other suitable replacement processes are within the contemplated scope of the present disclosure.

In some exemplary embodiments, the semiconductor structure100treated in accordance to the method of the present disclosure is further processed to be applied in the field of GAA nanosheet device. Other suitable further processes and/or application of the semiconductor structure100are within the contemplated scope of the present disclosure.

The embodiments of the present disclosure have the following advantageous features. The edge portion of the device substrate is removed by a wet etching process using the chemical fluid. By using a wet etching process, peeling of the device substrate is unlikely to happen on the main portion remaining in the device substrate. In addition, the carrier substrate may be well protected from damage caused by the chemical fluid. By virtue of controlling dopant concentration of the carrier substrate to be lower than that of the device substrate, the chemical fluid has an etching selectivity on the device substrate higher than that of the carrier substrate, so that the carrier substrate may remain intact. The protective layer may also effectively protect the carrier substrate. Furthermore, since the semiconductor device is substantially not affected by the chemical fluid, any metal e.g., copper, within the semiconductor device is not exposed, so as to effectively prevent any potential contamination of the other components in the semiconductors structure due to diffusion of copper. Additionally, low k materials within the semiconductor device are not exposed, and thus may be free from potential damages caused by any further processing, e.g., dry etching, performed on the semiconductor structure.

In accordance with some embodiments of the present disclosure, a method for treating a semiconductor structure includes: forming the semiconductor structure which includes a carrier substrate, a device substrate, a semiconductor device formed on the device substrate, and a bonding layer formed to bond the semiconductor device with the carrier substrate, the device substrate having an upper surface which is faced upwardly, and which is opposite to the semiconductor device; and directing a chemical fluid to impinge the upper surface of the device substrate so as to remove an edge portion of the device substrate.

In accordance with some embodiments of the present disclosure, the carrier substrate and the device substrate are doped by a dopant in different dopant concentration, and the chemical fluid has a higher etching selectivity over the device substrate than the carrier substrate.

In accordance with some embodiments of the present disclosure, the dopant is a p-type impurity.

In accordance with some embodiments of the present disclosure, a dopant concentration of the device substrate ranges from 1×1018atom/cm3to 1×1021atom/cm3.

In accordance with some embodiments of the present disclosure, a dopant concentration of the carrier substrate ranges from 1×1014atom/cm3to 1×1017atom/cm3.

In accordance with some embodiments of the present disclosure, the chemical fluid includes an acid chemical.

In accordance with some embodiments of the present disclosure, the acid chemical includes hydrogen fluoride (HF), nitric acid (HNO3), phosphoric acid (H3PO4), sulfuric acid (H2SO4), acetic acid (CH3COOH), or combinations thereof.

In accordance with some embodiments of the present disclosure, the chemical fluid includes a base chemical.

In accordance with some embodiments of the present disclosure, the base chemical includes potassium hydroxide (KOH), tetramethylammonium hydroxide (TMAH), tetrabutylammonium hydroxide (TBAH), tetraethylammonium hydroxide (TEAH), ammonium hydroxide (NH4OH), or combinations thereof.

In accordance with some embodiments of the present disclosure, a method for treating a semiconductor structure includes: forming the semiconductor structure which includes a carrier substrate, a device substrate, a semiconductor device formed on the device substrate, and a bonding layer formed to bond the semiconductor device with the carrier substrate, the device substrate having a proximate surface and a distal surface relative to the carrier substrate; performing a planarization process over the distal surface of the device substrate, so that the planarized device substrate has a planarized surface opposite to the proximate surface, and includes a main portion and an edge portion surrounding the main portion; and removing the edge portion of the planarized device substrate using a chemical fluid.

In accordance with some embodiments of the present disclosure, the chemical fluid includes a wet etchant.

In accordance with some embodiments of the present disclosure, wherein removal of the edge portion of the planarized device substrate includes: retaining the semiconductor structure on a structure retainer in a manner that the planarized device substrate is faced upwardly; rotating the semiconductor structure with the structure retainer; and directing the chemical fluid through a nozzle so as to impinge a peripheral region of the planarized surface.

In accordance with some embodiments of the present disclosure, the semiconductor structure is rotated about a rotation axis normal to the planarized surface; a reference line, which is tangent to an edge of the carrier substrate, is parallel to the rotational axis; a first distance is a distance between the reference line and a point on the device substrate at which the chemical fluid reaches the device substrate from the nozzle; a second distance is a minimal distance between the semiconductor device and the reference line; and the first distance is larger than the second distance.

In accordance with some embodiments of the present disclosure, the chemical fluid is directed to flow along a flow line, an included angle between the flow line and the planarized surface ranges from 90° to 160°.

In accordance with some embodiments of the present disclosure, a flow rate of the chemical fluid ranges from 3 mL/min to 50 mL/min.

In accordance with some embodiments of the present disclosure, a dimension of the outlet orifice of the nozzle ranges from 0.1 mm to 1.0 mm.

In accordance with some embodiments of the present disclosure, before performing the planarization process, a sealing element is formed to cover a surface of the semiconductor device exposed from the carrier substrate and the device substrate.

In accordance with some embodiments of the present disclosure, a semiconductor structure includes: a carrier substrate; a device substrate which has a dopant concentration different from that of the carrier substrate; a semiconductor device disposed between the carrier substrate and the device substrate; and a bonding layer disposed between the semiconductor device and the carrier substrate.

In accordance with some embodiments of the present disclosure, each of the carrier substrate and the device substrate is independently doped with a p-type impurity, and the dopant concentration of the device substrate is higher than that of the carrier substrate.

In accordance with some embodiments of the present disclosure, the dopant concentration of the device substrate ranges from 1×1018atom/cm3to 1×1021atom/cm3, and the dopant concentration of the carrier substrate ranges from 1×1014atom/cm3to 1×1017atom/cm3.