Determination of transmitter distortion

The present invention provides a method for determining nonlinear distortion of a transmitter. A test symbol sequence is transmitted from the transmitter under test as an analog output signal. The analog output signal is sampled to produce a first sequence which represents the test symbol sequence as distorted by a linear distortion sequence and a nonlinear distortion sequence. The test symbol sequence is filtered via an adaptive filter to produce a second sequence such that the second sequence is approximately equal to the test symbol sequence as distorted by the linear distortion sequence. The second sequence is subtracted from the first sequence to produce an output sequence substantially equal to the nonlinear distortion sequence.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention generally relates to distortion in transmitters. More particularly, the present invention relates to a method and a system for determining the nonlinear distortion of a transmitter included in a gigabit Ethernet transceiver.

2. Description of Related Art

Receivers that use digital signal processing modules, such as linear equalizers and cancellers, are particularly sensitive to nonlinear distortion that are present in the received signals. Severe nonlinear distortion would cause erroneous decoding of the received signals. The major contributor to the nonlinear distortion in a transmission channel is the corresponding transmitter.

In a Gigabit Ethernet communication system that conforms to the 1000BASE-T standard, two gigabit transceivers are connected via four twisted pairs of Category 5 copper cables and are in full-duplex bi-directional communication with each other. There are four constituent transceivers in each gigabit transceiver. The full-duplex bi-directional communication implies that each constituent transceiver is transmitting simultaneously on the same twisted pair of cable with a corresponding remote constituent transceiver. This simultaneous transmission would stress the analog components of the transmitter of a constituent transceiver. This stress would cause the transmitter to produce more nonlinear distortion. Thus, nonlinear distortion is an important problem in Gigabit Ethernet communication system.

In addition, the bi-directional nature of the Gigabit Ethernet communication system requires the use of echo cancellers in the gigabit transceivers. Since the echo cancellers are very sensitive to nonlinear distortion, nonlinear distortion must be kept, by design of the transmitters, at an acceptable level. The 1000BASE-T standard specifies that the peak nonlinear distortion of each constituent transceiver, when under test with no intervening cable, must be less than 10 millivolts.

Therefore, there is a need for techniques for determining nonlinear distortion of a transmitter, particularly, for a transmitter included in a constituent transceiver of a gigabit Ethernet transceiver.

SUMMARY OF THE INVENTION

The present invention provides a method for determining nonlinear distortion of a transmitter. A test symbol sequence is transmitted from the transmitter under test as an analog output signal. The analog output signal is sampled to produce a first sequence which represents the test symbol sequence as distorted by a linear distortion sequence and a nonlinear distortion sequence. The test symbol sequence is filtered via an adaptive filter to produce a second sequence such that the second sequence is approximately equal to the test symbol sequence as distorted by the linear distortion sequence. The second sequence is subtracted from the first sequence to produce an output sequence substantially equal to the nonlinear distortion sequence.

One embodiment of the invention provides a method for determining nonlinear distortion of a transmitter in the presence of a disturbing sinusoidal signal which simulates a signal transmitted from a remote transceiver in full duplex communication with the transceiver having the transmitter under test. A test symbol sequence is transmitted from the transmitter under test as an analog output signal. The analog output signal is sampled to produce a set of sampled data. A sinusoidal sequence is fitted to the sampled data. The sinusoidal sequence is subtracted from the sampled data to produce a first sequence, the first sequence representing the test symbol sequence as distorted by a linear distortion sequence and a nonlinear distortion sequence. The test symbol sequence is filtered via an adaptive filter to produce a second sequence such that the second sequence is approximately equal to the test symbol sequence as distorted by the linear distortion sequence. The filter coefficients are adapted based on the difference between the first and second sequences. The second sequence is subtracted from the first sequence to produce an output sequence substantially equal to the nonlinear distortion sequence.

DETAILED DESCRIPTION OF THE INVENTION

The present invention provides a method for determining nonlinear distortion of a transmitter. A test symbol sequence is transmitted from the transmitter under test as an analog output signal. The analog output signal is sampled to produce a digital output signal which represents the test symbol sequence distorted by a linear distortion sequence and by a nonlinear distortion sequence. The echo cancellation technique is used to approximately remove the test symbol sequence and the linear distortion sequence. The residual sequence is then a measure of the nonlinear distortion of the transmitter under test.

The present invention can be used to measure the nonlinear distortion of a transmitter in a gigabit transceiver of a Gigabit Ethernet communication system. For ease of explanation, the present invention will be described in detail as applied to this exemplary application. However, this is not to be construed as a limitation of the present invention.

In order to appreciate the advantages of the present invention, it will be beneficial to describe the invention in the context of an exemplary bi-directional communication device, such as an Ethernet transceiver. The particular exemplary implementation chosen is depicted inFIG. 1, which is a simplified block diagram of a multi-pair communication system operating in conformance with the IEEE 802.3ab standard (also termed 1000BASE-T) for 1 gigabit (Gb/s) Ethernet full-duplex communication over four twisted pairs of Category-5 copper wires.

InFIG. 1, the communication system is represented as a point-to-point system in order to simplify the explanation, and includes two main transceiver blocks101and102, coupled together via four twisted-pair cables104a, b, candd.Each of the wire pairs104a, b, c, dis coupled to each of the transceiver blocks101,102through a respective one of four line interface circuits106. Each of the wire pairs104a, b, c, dfacilitates communication of information between corresponding pairs of four pairs of transmitter/receiver circuits (constituent transceivers)108. Each of the constituent transceivers108is coupled between a respective line interface circuit106and a Physical Coding Sublayer (PCS) block110. At each of the transceiver blocks101and102, the four constituent transceivers108are capable of operating simultaneously at 250 megabits of information data per second (Mb/s) each, and are coupled to the corresponding remote constituent transceivers through respective line interface circuits to facilitate full-duplex bi-directional operation. Thus, 1 Gb/s communication throughput of each of the transceiver blocks101and102is achieved by using four 250 Mb/s (125 Mbaud at 2 information data bits per symbol) constituent transceivers108for each of the transceiver blocks101,102and four pairs of twisted copper cables to connect the two transceiver blocks101,102together.

The exemplary communication system ofFIG. 1has a superficial resemblance to a 100BASE-T4 system, but is configured to operate at ten times the bit rate. As such, it should be understood that certain system performance characteristics, such as sampling rates and the like, will be consequently higher and cause a greater degree of power consumption. Also, at gigabit data rates over potentially noisy channels, a proportionately greater degree of signal processing is required in many instances to insure an adequate degree of signal fidelity and quality.

FIG. 2is a simplified block diagram of the functional architecture and internal construction of an exemplary transceiver block, indicated generally at200, such as transceiver101ofFIG. 1. Since the illustrative transceiver application relates to gigabit Ethernet transmission, the transceiver will be referred to as the “gigabit transceiver”. For ease of illustration and description,FIG. 2shows only one of the four 250 Mb/s constituent transceivers which are operating simultaneously (termed herein 4-D operation). However, since the operation of the four constituent transceivers are necessarily interrelated, certain blocks and signal lines in the exemplary embodiment ofFIG. 2perform four-dimensional operations and carry four-dimensional (4-D) signals, respectively. By 4-D, it is meant that the data from the four constituent transceivers are used simultaneously. In order to clarify signal relationships inFIG. 2, thin lines correspond to 1-dimensional functions or signals (i.e., relating to only a single constituent transceiver), and thick lines correspond to 4-D functions or signals (relating to all four constituent transceivers).

Referring toFIG. 2, the gigabit transceiver200includes a Gigabit Medium Independent Interface (GMII) block202subdivided into a receive GMII circuit202R and a transmit GMII circuit202T. The transceiver also includes a Physical Coding Sublayer (PCS) block204, subdivided into a receive PCS circuit204R and a transmit PCS circuit204T, a pulse shaping filter206, a digital-to analog (D/A) converter block208, and a line interface block210, all generally encompassing the transmitter portion of the transceiver.

The receiver portion generally includes a highpass filter212, a programmable gain amplifier (PGA)214, an analog-to-digital (A/D) converter216, an automatic gain control (AGC) block220, a timing recovery block222, a pair-swap multiplexer block224, a demodulator226, an offset canceller228, a near-end crosstalk (NEXT) canceller block230having three constituent NEXT cancellers and an echo canceller232.

The gigabit transceiver200also includes an A/D first-in-first-out buffer (FIFO)218to facilitate proper transfer of data from the analog clock region to the receive clock region, and a loopback FIFO block (LPBK)234to facilitate proper transfer of data from the transmit clock region to the receive clock region. The gigabit transceiver200can optionally include an additional adaptive filter to cancel far-end crosstalk noise (FEXT canceller).

In operational terms, on the transmit path, the transmit section202T of the GMII block receives data from the Media Access Control (MAC) module in byte-wide format at the rate of 125 MHz and passes them to the transmit section204T of the PCS block via the FIFO201. The FIFO201ensures proper data transfer from the MAC layer to the Physical Coding (PHY) layer, since the transmit clock of the PHY layer is not necessarily synchronized with the clock of the MAC layer. In one embodiment, this small FIFO201has from about three to about five memory cells to accommodate the elasticity requirement which is a function of frame size and frequency offset.

The PCS transmit section204T performs certain scrambling operations and, in particular, is responsible for encoding digital data into the requisite codeword representations appropriate for transmission. In, the illustrated embodiment ofFIG. 2, the transmit PCS section204T incorporates a coding engine and signal mapper that implements a trellis coding architecture, such as required by the IEEE 802.3ab specification for gigabit transmission.

In accordance with this encoding architecture, the PCS transmit section204T generates four 1-D symbols, one for each of the four constituent transceivers. The 1-D symbol generated for the constituent transceiver depicted inFIG. 2is filtered by the pulse shaping filter206. This filtering assists in reducing the radiated emission of the output of the transceiver such that it falls within the parameters required by the Federal Communications Commission. The pulse shaping filter206is implemented so as to define a transfer function of 0.75+0.25z−1. This particular implementation is chosen so that the power spectrum of the output of the transceiver falls below the power spectrum of a 100Base-Tx signal. The 100Base-Tx is a widely used and accepted Fast Ethernet standard for 100 Mb/s operation on two pairs of Category-5 twisted pair cables. The output of the pulse shaping filter206is converted to an analog signal by the D/A converter208operating at 125 MHz. The analog signal passes through the line interface block210, and is placed on the corresponding twisted pair cable.

On the receive path, the line interface block210receives an analog signal from the twisted pair cable. The received analog signal is preconditioned by the highpass filter212and the PGA214before being converted to a digital signal by the A/D converter216operating at a sampling rate of 125 MHz. The timing of the A/D converter216is controlled by the output of the timing recovery block222. The resulting digital signal is properly transferred from the analog clock region to the receive clock region by the A/D FIFO218. The output of the A/D FIFO218is also used by the AGC220to control the operation of the PGA214.

The output of the A/D FIFO218, along with the outputs from the A/D FIFOs of the other three constituent transceivers are inputted to the pair-swap multiplexer block224. The pair-swap multiplexer block224uses the 4-D pair-swap control signal from the receive section204R of PCS block to sort out the four input signals and send the correct signals to the respective feedforward equalizers26of the demodulator226. This pair-swapping control is needed for the following reason. The trellis coding methodology used for the gigabit transceivers (101and102ofFIG. 1) is based on the fact that a signal on each twisted pair of wire corresponds to a respective 1-D constellation, and that the signals transmitted over four twisted pairs collectively form a 4-D constellation. Thus, for the decoding to work, each of the four twisted pairs must be uniquely identified with one of the four dimensions. Any undetected swapping of the four pairs would result in erroneous decoding. In an alternate embodiment of the gigabit transceiver, the pair-swapping control is performed by the demodulator226, instead of the combination of the PCS receive section204R and the pair-swap multiplexer block224.

The demodulator226includes a feed-forward equalizer (FFE)26for each constituent transceiver, coupled to a deskew memory circuit36and a decoder circuit38, implemented in the illustrated embodiment as a trellis decoder. The deskew memory circuit36and the trellis decoder38are common to all four constituent transceivers. The FFE26receives the received signal intended for it from the pair-swap multiplexer block224. The FFE26is suitably implemented to include a precursor filter28, a programmable inverse partial response (IPR) filter30, a summing device32, and an adaptive gain stage34. The FFE26is a least-mean-squares (LMS) type adaptive filter which is configured to perform channel equalization as will be described in greater detail below.

The precursor filter28generates a precursor to the input signal2. This precursor is used for timing recovery. The transfer function of the precursor filter28might be represented as −γ+z−1, with γ equal to 1/16 for short cables (less than 80 meters) and ⅛ for long cables (more than 80 m). The determination of the length of a cable is based on the gain of the coarse PGA14of the programmable gain block214.

The programmable IPR filter30compensates the ISI (intersymbol interference) introduced by the partial response pulse shaping in the transmitter section of a remote transceiver which transmitted the analog equivalent of the digital signal2. The transfer function of the IPR filter30may be expressed as 1/(1+Kz−1). In the present example, K has an exemplary value of 0.484375 during startup, and is slowly ramped down to zero after convergence of the decision feedback equalizer included inside the trellis decoder38. The value of K may also be any positive value strictly less than 1.

The summing device32receives the output of the IPR filter30and subtracts therefrom adaptively derived cancellation signals received from the adaptive filter block, namely signals developed by the offset canceller228, the NEXT cancellers230, and the echo canceller232. The offset canceller228is an adaptive filter which generates an estimate of signal offset introduced by component circuitry of the transceiver's analog front end, particularly offsets introduced by the PGA214and the A/D converter216.

The three NEXT cancellers230may also be described as adaptive filters and are used, in the illustrated embodiment, for modeling the NEXT impairments in the received signal caused by interference generated by symbols sent by the three local transmitters of the other three constituent transceivers. These impairments are recognized as being caused by a crosstalk mechanism between neighboring pairs of cables, thus the term near-end crosstalk, or NEXT. Since each receiver has access to the data transmitted by the other three local transmitters, it is possible to approximately replicate the NEXT impairments through filtering. Referring toFIG. 2, the three NEXT cancellers230filter the signals sent by the PCS block to the other three local transmitters and produce three signals replicating the respective NEXT impairments. By subtracting these three signals from the output of the IPR filter30, the NEXT impairments are approximately cancelled.

Due to the bi-directional nature of the channel, each local transmitter causes an echo impairment on the received signal of the local receiver with which it is paired to form a constituent transceiver. In order to remove this impairment, an echo canceller232is provided, which may also be characterized as an adaptive filter, and is used, in the illustrated embodiment, for modeling the signal impairment due to echo. The echo canceller232filters the signal sent by the PCS block to the local transmitter associated with the receiver, and produces an approximate replica of the echo impairment. By subtracting this replica signal from the output of the IPR filter30, the echo impairment is approximately cancelled.

The adaptive gain stage34receives the processed signal from the summing circuit32and fine tunes the signal path gain using a zero-forcing LMS algorithm. Since this adaptive gain stage34trains on the basis of error signals generated by the adaptive filters228,230and232, it provides a more accurate signal gain than the one provided by the PGA214in the analog section.

The output of the adaptive gain stage34, which is also the output of the FFE26, is inputted to the deskew memory circuit36. The deskew memory36is a four-dimensional function block, i.e., it also receives the outputs of the three FFEs of the other three constituent transceivers. There may be a relative skew in the outputs of the four FFEs, which are the four signal samples representing the four symbols to be decoded. This relative skew can be up to 50 nanoseconds, and is due to the variations in the way the copper wire pairs are twisted. In order to correctly decode the four symbols, the four signal samples must be properly aligned. The deskew memory aligns the four signal samples received from the four FFEs, then passes the deskewed four signal samples to a decoder circuit38for decoding.

In the context of the exemplary embodiment, the data received at the local transceiver was encoded before transmission, at the remote transceiver. In the present case, data might be encoded using an 8-state four-dimensional trellis code, and the decoder38might therefore be implemented as a trellis decoder. In the absence of intersymbol interference (ISI), a proper 8-state Viterbi decoder would provide optimal decoding of this code. However, in the case of Gigabit Ethernet, the Category-5 twisted pair cable introduces a significant amount of ISI. In addition, the partial response filter of the remote transmitter on the other end of the communication channel also contributes some ISI. Therefore, the trellis decoder38must decode both the trellis code and the ISI, at the high rate of 125 MHz. In the illustrated embodiment of the gigabit transceiver, the trellis decoder38includes an 8-state Viterbi decoder, and uses a decision-feedback sequence estimation approach to deal with the ISI components.

The 4-D output of the trellis decoder38is provided to the PCS receive section204R. The receive section204R of the PCS block de-scrambles and decodes the symbol stream, then passes the decoded packets and idle stream to the receive section202T of the GMII block which passes them to the MAC module. The 4-D outputs, which are the error and tentative decision, respectively, are provided to the timing recovery block222, whose output controls the sampling time of the A/D converter216. One of the four components of the error and one of the four components of the tentative decision correspond to the receiver shown inFIG. 2, and are provided to the adaptive gain stage34of the FFE26to adjust the gain of the equalizer signal path. The error component portion of the decoder output signal is also provided, as a control signal, to adaptation circuitry incorporated in each of the adaptive filters228,229,230,231and232. Adaptation circuitry is used for the updating and training process of filter coefficients.

In the gigabit transceiver described above (FIG. 2), the nonlinear distortion of each transmitter mainly come from the D/A block208and the line interface210. However, through its action on the D/A block208, the partial response pulse shaping filter206may indirectly contribute some distortion.

The present invention can be used to determine the nonlinear distortion introduced by the transmitter portion of each constituent transceiver in the gigabit transceiver.

FIG. 3is a block diagram of a symbol generator suitable for use in the present invention. The symbol generator300is used to generate a test symbol pattern to be transmitted by the transmitter under test. The test symbol pattern is a sequence of symbols which has statistical properties that allow determination of the amount of nonlinear distortion present in the output of a transmitter under test.

FIG. 4is a block diagram of a system constructed according to the present invention. The system400includes the transmitter402, which is under test, a sampler404, an external symbol generator406identical to the one shown inFIG. 3, a canceller408and an adder410.

The test symbol sequence Snis sent repeatedly to the transmitter402. It is noted that the combination of the D/A converter208and the line interface210ofFIG. 2would be an example of the transmitter402. The transmitter402transmits repeatedly the test symbol sequence S(n) as an analog output signal a(t). The sampler404, i.e., a A/D converter, samples the analog output signal a(t) at an appropriate rate and resolution to produce the sampled signal a(n). The sampled signal a(n) represents the test symbol sequence S(n) as distorted by both the linear and nonlinear distortion characteristics of the transmitter402.

The external symbol generator406produces the same test symbol sequence S(n) as the one being transmitted by the transmitter402. The test symbol sequence S(n) is inputted to a canceller408which is an adaptive filter. In one embodiment, the canceller408is a finite impulse response filter and the adaptation algorithm used to adapt the filter coefficients is a least mean squares (LMS) algorithm. The LMS algorithm is well known in the art. The canceller408outputs a sequence b(n) and uses a feedback signal to adapt its transfer function, in other words, to adapt its coefficients. The sequence b(n) is subtracted from the sequence a(n) via the adder410to produce an error sequence e(n). The error sequence e(n) is used as the feedback signal to adapt the coefficients of the canceller408. The coefficients of the canceller408are adapted so that the mean squared value of e(n) is minimized.

The canceller408correlates the test symbol sequence S(n) with the error sequence e(n) and adapts its coefficients such that the canceller output sequence b(n) reflects this correlation. Since only the linear distortion component in the error sequence e(n) correlates with the test symbol sequence S(n), the canceller output sequence b(n) represents the test symbol sequence S(n) as distorted by only the linear distortion of the transmitter402. Therefore, when the transfer function of the canceller408is fully adapted, i.e., when the canceller coefficients converge, the linear distortion component is removed from the error sequence e(n), and e(n) becomes a measure of the nonlinear distortion of the transmitter402. A peak magnitude value of e(n) is a measurement of the peak distortion of the transmitter402under test.

FIG. 5illustrates an exemplary embodiment500of the canceller408ofFIG. 4. In this exemplary embodiment, the canceller has 2N+1 coefficients denoted by C0through C2N, and a delay line having 2N delay elements denoted conventionally by z−1. The canceller500includes an adaptation module502to train (i.e., adapt) the filter coefficients.

The well-known least mean squares algorithm is used in the training process of the filter coefficients. Referring toFIG. 5and letting e(k) be the k-th sample of the sequence e(n), the filter coefficients are updated as follows:
CN+j(k+1)=CN+j(k)+Δ·e(k)·S(i−j) forj=−N, . . . , −1, 0, 1, . . . ,N
where CN+j(k)is the filter coefficient value after the (k−1)th training, and Δ is the step size of the LMS algorithm. After training, when the coefficients converge, the final value of a coefficient is CN+j, for j=−N, . . . ,N.

FIG. 6is a flowchart of another embodiment of the present invention. In this embodiment600, the processing of the transmitted data are done off-line, i.e., after all the sampled data are collected from the sampler404(FIG. 4).

Process600provides a simple technique to determine the distortion of a transmitter such as the one included in each constituent transceiver of the gigabit transceiver (FIGS. 1 and 2). Process600allows measurement of the transmitter distortion in the presence of a disturbing signal sent from a remote transmitter.

Upon Start, process600initializes all variables (block602). Process600generates the test symbol sequence (block604). In one example, the test symbol sequence has 2047 symbols. Process600loads the sampled measurement data (block608). Process600fits a sinusoidal sequence to the sampled measurement data (block610) using a best fit algorithm then subtracts the sinusoidal sequence from the sampled measurement data to produce the adjusted sampled data (block612). Process600initializes the canceller and inputs the test symbol sequence into the delay line of the canceller (block614). Process600aligns the data in the delay line of canceller to the adjusted sampled data pattern (block616). Process600computes the canceller coefficients that minimize the mean squared error between the output of the canceller and the adjusted sampled data (block618). An exemplary algorithm that can be used for this computation of canceller coefficients is the well known minimum mean squares algorithm. Process600then computes the error sequence as the difference between the adjusted sampled data and the output of the canceller (block620). At this point, process600can go directly to block632to compute the peak distortion of the transmitter.

The blocks622through630are optional. They are used to ensure that any residual of the sinusoidal sequence in the error sequence is removed. The fitting of the sinusoidal sequence to the sampled measurement data may not be completely correct because of the presence of the test symbol sequence and the linear distortion in the sampled measurement data that is not yet removed by the canceller. Thus, there may be residual of the sinusoidal sequence in the error sequence. Thus, in this case, the error sequence may not be a true measure of the nonlinear distortion.

The blocks622through630are also used to ensure that any effect of the sinusoidal sequence on the canceller output is removed. In principle, the canceller function does not get affected by the presence of the sinusoidal sequence in the feedback sequence e(n) (FIG. 4) for the following reason. Since the canceller correlates its input sequence, i.e., the test symbol sequence, with the feedback sequence e(n), and since the sinusoidal sequence does not correlate with the input sequence, the output of the canceller should be unaffected by the sinusoidal sequence and should be the same as for the case where there is no sinusoidal sequence included in e(n). However, in practice, the sinusoidal sequence in e(n) may have some effect on the output of the canceller due to the finite length of the test symbol sequence.

In block622, process600adds the previously removed sinusoidal sequence to the error sequence. Process600refits a sinusoidal sequence to the resulting error sequence (block624). Since most of the non-sinusoidal part of the sampled measurement data has been removed from the resulting error sequence at this point, the fitting of a sinusoidal sequence to the resulting error sequence now yields a near perfect fit. Process600then subtracts the new sinusoidal sequence from the sampled measurement data to produce new adjusted sampled data (block626). Process600recomputes the canceller coefficients so as to minimize the mean squared error between the output of the canceller and the new adjusted sampled data (block628). Process600recomputes the error sequence as the difference between the new adjusted sampled data and the output of the canceller (block630). Process600computes the signal to noise ratio using a fixed known value as the signal value and the mean squared value of the error sequence as the noise value, and computes the peak distortion of the transmitter as the maximum absolute value of the error sequence (block632). Process600then terminates (block634).

FIG. 7illustrates a transmitter test fixture for distortion measurement. Process600can be used as the post-processing module in this test fixture. The transmitter under test702is coupled to a sinewave generator704. This is to simulate the real situation where the local transceiver would be connected in full duplex communication to a remote transceiver. In such a case, the signal sent by the remote transmitter would be a 2.8 volts peak-to-peak sinusoidal signal and would be a disturbing signal to the local transmitter, causing stress to its analog components which in turn produce more nonlinear distortion. The transmitted signal is measured by a high impedance differential probe706(or any equivalent device). The measured signal is filtered by a test filter708. The test filter708may be located between points A and B. The test filter708is used to ensure that the impulse response of the transmitter is limited within the length of the canceller used by the post-processing module712. The filtered signal is sent to a data acquisition module710to be sampled. The sampling rate is provided by the clock signal TX_TCLK which is also the clock signal that controls the transmission rate of the transmitter702. The sampled data are inputted to the post-processing module712. Process600(FIG. 6) can be used as the post-processing module712.

While certain exemplary embodiments have been described in detail and shown in the accompanying drawings, it is to be understood that such embodiments are merely illustrative of and not restrictive on the broad invention. It will thus be recognized that various modifications may be made to the illustrated and other embodiments of the invention described above, without departing from the broad inventive scope thereof. It will be understood, therefore, that the invention is not limited to the particular embodiments or arrangements disclosed, but is rather intended to cover any changes, adaptations or modifications which are within the scope and spirit of the invention as defined by the appended claims.