A converter system includes a first switch and a controller configured to switch the first switch between first and second states based on input and output voltages of the converter system, wherein the controller includes: a timer unit including a first timer configured to determine a first duration based on a target switching frequency of the converter system, and a second timer configured to determine a second duration based on a predetermined duration equal to or greater than a minimum duration of the first state of the first switch and the input and output voltages; and a control logic unit, configured to switch the first switch from the second state to the first state upon expiration of both the first and second durations.

TECHNICAL FIELD

The present disclosure relates to integrated circuits and, more particularly, to a current mode DC-DC converter system.

BACKGROUND

DC-DC converters are widely used to convert an input DC voltage to a desired output DC voltage to drive a load. A current mode DC-DC converter may include a current loop that determines on or off time of a switch in each switching cycle by sensing an inductor current flowing through an inductor that is coupled to a switch node of the DC-DC converter, thereby regulating the inductor current. In a conventional adaptive on-time or off-time current mode DC-DC converter, a pulse-width-modulation (PWM) signal that controls the switch is regulated based on the sensed inductor current, the on-time or off-time determined based on input and output voltages of the DC-DC converter. In a conventional fixed frequency current mode DC-DC converter, the PWM signal is regulated based on the sensed inductor current, and a clock signal with a fixed target frequency.

SUMMARY

The present disclosure relates to integrated circuits and, more particularly, to a DC-DC converter system with a wider range of duty cycle. A DC-DC converter system, for example, a switch mode DC-DC converter, usually includes a switch operable between on and off states based on a frequency signal, for example, a pulse-width-modulation (PWM) signal, to generate an output DC voltage to a load by periodically storing energy from a source that provides an input DC voltage in a magnetic field of an inductor or a transformer and releasing the energy from the magnetic field. The ratio between the output DC voltage and the input DC voltage is proportional to a duty cycle of the PWM signal.

In one example, the present disclosure provides a DC-DC converter system including a first switch coupled to a switching node and operable between first and second states, and a controller, coupled to the first switch, and configured to switch the first switch between the first and second states based on an input voltage and an output voltage of the DC-DC converter system. The controller includes: a timer unit including a first timer configured to determine a first duration based on a target switching frequency of the DC-DC converter system, a second timer configured to determine a second duration based on a predetermined duration substantially equal to or greater than a minimum duration of the first state of the first switch and the input and output voltages, and logic circuitry coupled to the first and second timers and configured to generate an expiration signal upon expiration of both the first and second durations; and a control logic unit, configured to switch the first switch from the second state to the first state based on the expiration signal.

In another example, the present disclosure provides a controller for switching a first switch of a DC-DC converter system. The controller includes: a timer unit including a first timer configured to determine a first duration based on a target switching frequency of the DC-DC converter system, a second timer configured to determine a second duration based on input and output voltages of the DC-DC converter system and a predetermined duration substantially equal to or greater than a minimum duration of a first state of the first switch, and logic circuitry coupled to the first and second timers and configured to generate an expiration signal upon expiration of both the first and second durations; and a control logic unit, configured to switch the first switch from a second state to the first state based on the expiration signal.

In yet another example, the present disclosure provides a DC-DC converter system including: a first switch coupled to a switching node of the DC-DC converter system and a voltage supply node, and operable between first and second states; a first timer including a first capacitive element with a first capacitance, a first timing switching coupled in parallel with the first capacitive element, a first current source coupled in series with the first capacitive element and configured to source or sink a first current to or from the first capacitive element, and a first comparator with a first input terminal coupled to the first capacitive element, a second input terminal configured to receive a first reference voltage, and an output terminal configured to generate a first timer expired signal upon expiration of a first duration determined based on the first capacitance, the first current source and the first reference voltage; a second timer including a second capacitive element with a second capacitance, a second timing switching coupled in parallel with the second capacitive element; a second current source coupled in series with the second capacitive element and configured to source or sink a second current to or from the second capacitive element, and a second comparator with a first input terminal coupled to the second capacitive element, a second input terminal configured to receive a second reference voltage, and an output terminal configured to generate a second timer expired signal upon expiration of a second duration determined based on the second capacitance, the second current source and the second reference voltage; a logic gate coupled to outputs of the first and second comparators, and configured to generate an expiration signal based on expiration of both the first and second durations; and a control logic unit, coupled between the logic gate and a control terminal of the first switch, configured to switch the first switch from the second state to the first state based on the expiration signal.

DETAILED DESCRIPTION

The present disclosure relates to current mode DC-DC converter systems.

Referring now toFIG.1, a schematic block diagram of a DC-DC converter system100in accordance with a first implementation of the present disclosure is shown. More particularly,FIG.1shows an adaptive off-time current mode boost DC-DC converter system with peak current control topology.

The system100includes a first switch102coupled between a switch node SW and a voltage supply node, for example, a ground node GND, and a second switch104coupled between the switch node SW and an output node VOUT of the system100, thereby allowing a current flowing from the switch node SW to the output node VOUT. The first and second switches102and104, also named respectively as low side and high side switches, can be transistors, for example, N-channel MOSFETs that are respectively controlled by gate drive signals LSD_ON and HSD_ON to alternately operable between first and second states, e.g. on and off states, allowing a current to follow from the switch node SW towards the voltage supply node GND, and from the switch node SW towards the output node VOUT. In an alternate example, the second switch104can be replaced by a diode that allows current to flow from the switch node SW to the output node VOUT in a unidirectional manner. The system100also includes an input inductor106coupled between an input node VIN and the switch node SW, and an output capacitive element108coupled between the output node VOUT and the ground node GND.

The system100includes a controller110coupled to the first and second switches102and104to generate a PWM signal to alternately switch on and off the first and second switches102and104through a driver unit112which generates the gate drive signals LSD_ON and HSD_ON based on the PWM signal. In a preferred example, the driver unit112can be either a part of or separate from the controller110.

The controller110includes a sensing unit114configured to generate a control signal Sc based on a difference between a sensing voltage Vs proportional to an inductor current IL through the inductor106and a control voltage Vc proportional to a difference between a reference voltage VREF and a feedback voltage VFB proportional to the output voltage VOUT, generated by an amplifier116. In one example, the sensing unit114includes a comparator118configured to generate the control signal Sc to switch the first switch102from the on state to the off state if the sensing voltage Vs increases to the control voltage Vc. In one example, the sensing voltage Vs is proportional to a current Is flowing through the first switch102and obtained through a current-to-voltage (I/V) unit120, for example, by sensing a voltage across a sensing resistor (not shown) coupled between the first switch102and the ground node GND.

The controller110includes a control logic124configured to switch the first switch102from the on state to the off state through the driver unit112, based on the control signal Sc. However, a minimum duration of the on state, also known as a minimum on-time Ton_min, of the first switch is usually limited due to various factors of the DC-DC converter system100, such as blanking time of inductor current IL sensing, delay caused by the comparator118, the control logic124and/or the driver unit112. The minimum on-time of the first switch102limits the range of a ratio of output voltage VOUT to the input voltage VIN.

The controller110also includes a timer unit122configured to determine a preferred duration of the off state, also known as an off-time Toff, of the first switch102based on a target switching frequency fsw of the DC-DC converter system100, the minimum on-time Ton_min of the first switch, and the input and output voltages VIN and VOUT of the system100.

The timer unit122is further configured to generate an expiration signal STto switch the first switch102from the off state to the on state when the preferred off-time Toff expires. The control logic124is configured to generate the PWM signal based on the control signal Sc and the expiration signal ST. For example, the control logic124can be an edge-triggered SR flip flop that asserts the PWM signal based on the expiration signal STand de-asserts the PWM signal based on the control signal Sc.

FIG.2Ashows an example schematic circuit diagram of a timer unit200, such as the timer unit122of the DC-DC converter system100ofFIG.1. The timer unit200includes a first timer202configured to generate a first timer expired signal ST1based on a first duration T1. In one example, the first duration T1is a nominal duration of the second state, e.g. the off state, of the first switch102determined based on the target switching frequency fsw of the DC-DC converter system100and the input and output voltages VIN and VOUT, such that the DC-DC converter system operating at the target switching frequency fsw converts the input voltage VIN to the output voltage VOUT by keeping the first switch102at the off state for the nominal duration in each target switching cycle T. In the example of the adaptive off-time current mode boost DC-DC converter system with peak current control topology, the first duration T1is determined in accordance with the equation below:

T⁢1=T·VINVOUT(1)
where T is the target switching cycle, T=1/fsw.

In one example, the first timer202includes a first capacitive element204with a capacitance C1. The first capacitive element204is coupled in parallel with a first charging control switch206that is controlled by the gate drive signal LSD_ON, and in series with a first current source208configured to source a first charging current Ic1to the first capacitive element204. In the example ofFIG.2, Ic1=VOUT/R1. Charging the first capacitive element204is triggered upon the first switch102being switched from the on state to the off state. The first timer202includes a first comparator210with an inverting input coupled to a reference voltage generator shown inFIG.2Bto receive a reference voltage Vref1=K·VIN. The first capacitive element204is coupled between a non-inverting input of the first capacitive element210and the ground node GND. The first capacitive element210is configured to generate a first timer expired signal ST1when a voltage across the first capacitive element204increased to the reference voltage K*VIN. Accordingly, the first duration T1is determined by the first timer202in accordance with the equation below:

T⁢1=K·R⁢1·C⁢1·VINVOUT(2)
where K is a number greater than 0, K·R1is resistance of a resistor236of a charging path of the first timer202shown inFIG.2C, and K·R1·C1is configured to be substantially equal to the target switching cycle T=1/fsw of the DC-DC converter system100within acceptable error range resulting from inherent errors of the first capacitive element210and the resistor236. However, the first charging current Ic1and the reference voltage Vref1can be other values as long as meeting the equation below:

The timer unit200also includes a second timer212with a structure similar to that of the first timer202except that a second capacitive element214of the second timer212has a capacitance C2and is charged by a second current source216with a second charging current Ic2, where Ic2=(VOUT−VIN)/R2. The second timer212is configured to be triggered substantially simultaneously with the first timer based on the gate drive signal LSD_ON, and to generate a second timer expired signal ST2based on a second duration T2that is determined based on the minimum on-time Ton_min of the first switch102and the input and output voltages VIN and VOUT. The second duration T2is provided in accordance with the equations below:

T⁢2=K·R⁢2·C⁢2·VINVOUT-VIN(4)
where K·R2is resistance of a resistor242of a charging path of the second timer212shown inFIG.2D, and K·R2·C2is configured to be substantially equal to or slightly greater, e.g. 10 ns greater, than the minimum on-time Ton_min of the first switch102.

In one example, the second timer212includes a second charging switch220configured to be switched off simultaneously with switching off the first charging switch206, and K·R2·C2is configured to be substantially equal to the minimum on-time Ton_min of the first switch102, such that the second duration equals an off-time of the first switch102determined under the condition that the on-time of the first switch102is the minimum on-time Ton_min.

In another example, the second timer212includes a second charging switch220configured to be switched off simultaneously with switching off the first charging switch206, and K·R2·C2is configured to be slightly, e.g. 10 ns, greater, than the minimum on-time Ton_min of the first switch102to ensure the second duration longer than an off-time of the first switch102determined under the condition that the on-time of the first switch102is the minimum on-time Ton_min.

In yet another example, K·R2·C2is configured to be substantially equal to the minimum on-time Ton_min of the first switch102, and the second timer212further includes a delay unit222such that the second charging switch220is configured to be switched off slightly later, e.g. 50 ns or more, than switching off the first charging switch206to ensure the second duration longer than an off-time of the first switch102determined under the condition that the on-time of the first switch102is the minimum on-time Ton_min.

In one example, the second timer212further includes a second comparator224with an inverting input coupled to another reference voltage generator to receive another reference voltage Vref2. The second charging current Ic2and the reference voltage Vref2can be other values as long as meeting the equation below:

The timer unit200also includes a logic gate218configured to generate the expiration signal STupon both the first and second timer expired signals ST1and ST2being asserted. In one example, when VOUT/(R1·C1)>(VOUT−VIN)/(R2·C2), the second duration T2is smaller than the first duration T1, the preferred duration of the off state of the first switch102is determined by the first duration T1, which is the nominal duration of the off state of the first switch102determined based on the target switching frequency fsw and the input and output voltages of the system100. In another example, when VOUT/(R1·C1)<(VOUT−VIN)/(R2·C2), the preferred duration of the off state of the first switch102is determined by the second duration T2, and the duration of the on state of the first switch102is regulated at (VOUT−VIN)/VIN*Toff=K*R2*C2, which is substantially equal to or greater than the minimum on-time Ton_min of the first switch102, therefore the inductor current IL can still be regulated based on the sensing voltage Vs. In such situation, an actual switching cycle of the DC-DC converter system100is configured to be K·R2·C2·VOUT/(VOUT−VIN), with is greater than the target switching cycle of the DC-DC converter system100.

FIG.2Bshows an example schematic circuit diagram of the reference voltage generator226that provides the reference voltage K·VIN. In one example, the reference voltage generator226includes a voltage divider228generating the reference voltage K·VIN proportional to the input voltage VIN.

FIG.2Cshows an example schematic circuit diagram of a current source230, for example, the first current source208of the timer unit200ofFIG.2. The first current source230includes an error amplifier232having an output terminal coupled to a gate node of a transistor234, a non-inverting input terminal configured to receive a reference voltage K·VOUT which can be provided in a similar manner as the reference voltage generator220shown inFIG.2B, and an inverting input terminal coupled to a source node of the transistor234. The first current source230also includes the resistor236coupled between the source node of the transistor234and the ground node GND and having a resistance of K·R1, and a current mirror238coupled to a drain node of the transistor234and configured to mirror a current flowing through the resistor236, which is provided as the first charging current Ic1=VOUT/R1.

FIG.2Dshows an example schematic circuit diagram of another current source240, for example, the second current source216of the timer unit200ofFIG.2. The second current source240has a structure similar to that of the first current source230except that a voltage difference across the resistor242is configured to be VOUT−VIN. The current mirror244is configured to mirror a current flowing through the resistor242, which is provided as the second charging current Ic2=(VOUT−VIN)/R2.

Referring back toFIG.1, the control logic unit124is configured to switch the first switch102from the off state to the on state based on the expiration signal ST. Therefore, the duration of the off state, i.e., the off time Toff, of the first switch102is configured to be a greater one between the first and second duration T1and T2.

In a conventional adaptive off-time current mode boost DC-DC converter system, the off-time Toff of the first switch, e.g. the low side switch, is configured to be a nominal off-time Toff′ determined in accordance with the equation below:
Toff′=T·VIN/VOUT  (6)

Due to the limit of the minimum on-time Ton_min of the system, an on duty cycle range of the system is limited between Ton_min/T and 1, and thus a ratio of VOUT to VIN range is limited between T/(T−Ton_min) and ∞. Similarly, operation ranges of other conventional adaptive on-time/off-time current mode DC-DC converter systems with other topologies are also limited by the nominal off-time and minimum on-time of the system, or a nominal on-time and a minimum-off time of the system. Table 1 lists the operation ranges of conventional adaptive on-time/off-time current mode DC-DC converter systems with different topologies.

In the present disclosure, the proposed adaptive off-time current mode boost DC-DC converter system100dynamically extends the off-time Toff of the first switch102when the off-time determined based on the minimum on-time Ton_min and the input and output voltages VIN and VOUT is greater than the nominal off-time of the DC-DC converter system. As the off-time of the first switch102can be extended to Ton_min·VIN/(VOUT−VIN) when a target ratio of VOUT to VIN is less than T/(T−Ton_min), the range of on duty cycle can be extended between 0 and 1, and the range of VOUT/VIN can be extended between 1 and ∞.

FIG.3shows a schematic block diagram of a DC-DC converter system300in accordance with a second implementation of the present disclosure. More particularly,FIG.3shows an adaptive on-time current mode boost DC-DC converter system with valley current control topology.

The DC-DC converter system300is substantially similar to the DC-DC converter system100ofFIG.1except that the sensing voltage Vs is generated proportional to a current flowing through the second switch304, i.e. the high side switch, the comparator318is configured to generate the control signal Sc when the sensing voltage Vs decreases to the control voltage Vc, and the control logic324is configured to switch on the first switch302based on the control signal Sc and to switch off the first switch302based on the expiration signal STgenerated by the timer unit322.

FIG.4shows an example schematic circuit diagram of a timer unit400, such as the timer unit322of the DC-DC converter system300ofFIG.3. The timer unit400includes a first timer402configured to generate a first timer expired signal ST1based on a first duration T1. In one example, the first duration T1is a nominal duration of the on state, i.e. a nominal on-time Ton, of the first switch302determined based on a target switching frequency fsw of the DC-DC converter system300and input and output voltages VIN and VOUT in accordance with the equation below:

T⁢1=T·VOUT-VINVOUT(6)
where T is the target switching cycle of the system300, T=1/fsw.

The first timer402is configured to determine the first duration T1, i.e., the nominal on-time of the first switch302, in accordance with the equation below:

where K·R1·C1is configured to be substantially equal to a target switching cycle T=1/fsw of the DC-DC converter system300.

The timer unit400also includes a second timer412with a structure similar to that of the first timer402except that the second timer412is configured to generate a second timer expired signal ST2based on a second duration T2provided in accordance with the equations below:

where K·R2·C2is configured to be substantially equal to or slightly greater, e.g. 10 ns greater, than a minimum duration of the off state, i.e., the minimum off-time Toff_min, of the first switch302.

The first and second timer402and412are configured to start timing upon the second switch304being switched from the on state to the off state, i.e, when the first switch302is switched from the off state to the on state. Similar to the timer unit200ofFIG.2, the timer unit400is configured to generate an expiration signal STupon both of the first and second timer expired signals ST2and ST2being asserted.

Similar to the DC-DC converter system100ofFIG.1, as the on-time of the first switch302can be extended to Toff_min·(VOUT−VIN)/VIN when a target ratio of VOUT to VIN is greater than T/Toff_min, the range of on duty cycle can be extended between 0 and 1, and the range of VOUT/VIN can be extended between 1 and ∞.

FIG.5in combination withFIG.6shows a schematic block diagram of a DC-DC converter system500in accordance with a third implementation of the present disclosure. More particularly,FIG.5shows an adaptive on-time current mode buck DC-DC converter system with valley current control topology. Similar to the adaptive on-time current mode boost DC-DC converter system300shown inFIG.3in combination with the timer unit400ofFIG.4, the DC-DC converter system500is configured to switch off the first switch502, i.e. the high side switch, based on an expiration signal STgenerated by the timer unit522. The timer unit522, shown as the timer unit600ofFIG.6in more detail, is configured to generate the expiration signal STto switch off the first switch502upon both of the first and second duration T1and T2respectively determined by the first and second timers expire. The first duration T1is determined based on a nominal duration of the on state, e.g. a nominal on-time Ton, of the first switch602determined based on the switching frequency fsw and the input and output voltages VIN and VOUT of the DC-DC converter system500, and the second duration T2is determined based on the input and output voltages VIN and VOUT and a predetermined duration substantially equal to greater than the minimum duration of the off state, also known as minimum off-time Toff_min, of the first switch502. Similar to the DC-DC converter system300ofFIG.3, as the duration of the on state, i.e., the on-time, of the first switch502can be extended to Toff_min·VOUT/(VIN−VOUT) when a target ratio of VOUT to VIN is greater than 1-Toff_min/T, the range of on duty cycle can be extended between 0 and 1, and the range of VOUT/VIN can be extended between 0 and 1.

FIG.7in combination withFIG.8shows a schematic block diagram of a DC-DC converter system700in accordance with a fourth implementation of the present disclosure. More particularly,FIG.7shows an adaptive off-time current mode buck DC-DC converter system with peak current control topology. Similar to the adaptive on-time current mode buck DC-DC converter system500shown inFIG.5in combination with the timer unit600ofFIG.6, the DC-DC converter system700is configured to switch on the first switch702, i.e. the high side switch, based on the expiration signal STgenerated by the timer unit722. The timer unit722, shown as the timer unit800ofFIG.8in more detail, is configured to generate the expiration signal STto switch on the first switch702when both of the first and second duration T1and T2respectively determined by the first and second timers expire. The first duration T1is determined based on a nominal duration of the off state, i.e. a nominal off-time, of the first switch702which is determined based on the switching frequency fsw and the input and output voltages VIN and VOUT of the DC-DC converter system700, and the second duration T2is determined based on the input and output voltages VIN and VOUT and a predetermined duration substantially equal to greater than the minimum on-time Ton_min of the first switch702. Similar as the DC-DC converter system500ofFIG.5, as the off-time of the first switch702can be extended to Ton_min·(VIN-VOUT)/VOUT when a target ratio of VOUT to VIN is less than Ton_min/T, the range of on duty cycle can be extended between 0 and 1, and the range of VOUT/VIN can be extended between 0 and 1.

Table 2 lists the operation ranges of adaptive on-time/off-time current mode DC-DC converter systems with different topologies in accordance with the first to fourth implementations of the present disclosure.

Referring toFIG.9, a schematic block diagram of a DC-DC converter system900in accordance with a fifth implementation of the present disclosure is shown. More particularly,FIG.9shows a fixed frequency current mode boost DC-DC converter system with peak current control topology. The DC-DC converter system900is substantially similar to the DC-DC converter system100ofFIG.1except that the sensing voltage Vs provided to the comparator918is proportional to a combination of the current flowing through the first switch902and a slope compensation signal, and the control logic924is configured to switch on the first switch902based on a clock signal CLK generated by the timer unit922, for example, a rising edge of the clock signal CLK.

FIG.10shows an example schematic circuit diagram of a timer unit1000, such as the timer unit922of the DC-DC converter system900ofFIG.9. The timer unit1000is substantially similar to the timer unit200ofFIG.2, except that the timer unit922further includes a one-shot signal generator1022coupled to the switches1006and1020to provide a one-shot signal RST based on the clock signal CLK, such that the first and second timers1002and1012start timing upon the first switch902being switched from the off state to the on state. The first timer1002is configured to generate a first timer expired signal ST1based on a first duration T1. In one example, the first duration T1is a target switching cycle T=1/fsw, where fsw is a target switching frequency of the DC-DC converter system900. The first duration T1is provided in accordance with the equations below:
T1=K·R1·C1  (9)
where K·R1·C1is configured to be substantially equal to the target switching cycle T=1/fsw of the DC-DC converter system900.

The timer unit1000also includes a second timer1012configured to generate a second timer expired signal ST2based on a second duration T2that is determined based on a minimum duration of the on state, i.e., a minimum on-time Ton_min, of the first switch902and the input and output voltages VIN and VOUT. In one example, the second duration T2is determined based on the input and output voltages VIN and VOUT, and a predetermined duration substantially equal to greater than the minimum on-time Ton_min of the first switch902. The second duration T2is provided in accordance with the equations below:

where K·R2·C2is configured to be substantially equal to or slightly greater, e.g. 10 ns greater, than the minimum on-time Ton_min of the first switch902.

The timer unit1000further includes a gate logic1018configured to generate, for example, a rising edge, of the clock signal CLK based on the first and second timer expired signals ST2and ST2, wherein the cycle of the clock signal CLK is configured to be the larger one of the first and second duration T1and T2.

In a conventional fixed frequency peak current control mode boost DC-DC converter system, a cycle of a clock signal CLK that periodically switches the first switch from a second state, e.g. the off state, to a first state, e.g. the on state, is fixed by the target switching frequency fsw of the conventional system.

Due to the minimum on-time Ton_min of the conventional system, the on duty cycle range of the system is limited between Ton_min/T and 1-Toff_min/T, and thus a range of a ratio of VOUT to VIN is limited between T/(T−Ton_min) and T/Toff_min. Similarly, operation ranges of other conventional fixed frequency current mode DC-DC converter systems with other topologies are also limited by the target switching cycle and minimum on or off time of the first switch of the system. Table 3 lists the operation ranges of conventional fixed frequency current mode DC-DC converter systems with different topologies.

In the present disclosure, the proposed fixed frequency current mode boost DC-DC converter system900dynamically extends the switching cycle when a switching cycle determined based on the minimum on-time Ton_min and the input and output voltages VIN and VOUT is greater than the target switching cycle of the DC-DC converter system. As the switching cycle can be extended to Ton_min·VOUT/(VOUT−VIN) when a target ratio of VOUT to VIN is less than T/(T−Ton_min), the range of on duty cycle can be extended between 0 and 1-Toff_min/T, and the range of VOUT/VIN can be extended between 1 and T/Toff_min.

FIG.11in combination withFIG.12shows a schematic block diagram of a DC-DC converter system1100in accordance with a sixth implementation of the present disclosure. More particularly,FIG.11shows a fixed current mode boost DC-DC converter system with valley current control topology. Similar to the timer unit1000ofFIG.10, the timer unit1200is configured to generate a clock signal CLK with a cycle determined based on a larger one between the target switching cycle of the DC-DC converter system1100and an adjusted cycle determined based on the input and output voltages VIN and VOUT and a predetermined duration substantially equal to greater than the minimum off time Toff_min of the first switch1102of the DC-DC converter system1100. The control logic1124is configured to switch off the first switch1102upon, for example, a rising edge, of the clock signal CLK.

FIG.13in combination withFIG.14shows a schematic block diagram of a DC-DC converter system1300in accordance with a seventh implementation of the present disclosure. More particularly,FIG.13shows a fixed current mode buck DC-DC converter system with peak current control topology. Similar to the timer unit1000ofFIG.10, the timer unit1400is configured to generate a clock signal CLK with a cycle determined based on a larger one between the target switching cycle of the DC-DC converter system1300and an adjusted cycle determined based on the input and output voltages VIN and VOUT and a predetermined duration substantially equal to greater than the minimum on time Ton_min of the first switch1302of the DC-DC converter system1300. The control logic1324is configured to switch on the first switch1302upon, for example, a rising edge, of the clock signal CLK.

FIG.15in combination withFIG.16shows a schematic block diagram of a DC-DC converter system1500in accordance with an eighth implementation of the present disclosure. More particularly,FIG.15shows a fixed current mode buck DC-DC converter system with valley current control topology. Similar to the timer unit1200ofFIG.12, the timer unit1200is configured to generate a clock signal CLK with a cycle determined based on a larger one between the target switching cycle of the DC-DC converter system1500and an adjusted cycle determined based on the input and output voltages VIN and VOUT and a predetermined duration substantially equal to greater than the minimum on time Toff_min of the first switch1502of the DC-DC converter system1500. The control logic1524is configured to switch off the first switch1502upon, for example, a rising edge, of the clock signal CLK.

Table 4 lists the operation ranges of fixed frequency current mode DC-DC converter systems with different topologies in accordance with the fifth to eighth implementations of the present disclosure.

Referring toFIG.17, a flow chart of a method1700for regulating a DC-DC converter system in accordance with an implementation of the present disclosure is shown. With reference to the DC-DC converter system100ofFIG.1, the DC-DC converter system includes the first switch102coupled between the switch node SW and a voltage supply node, for example, a ground node GND. The inductor106is coupled between the switch node SW and the voltage input node VIN, and second switch104is coupled between the switch node SW and the voltage output node VOUT. The first switch102is configured to periodically allow the inductor current IL to flow there through. Other topologies of current mode DC-DC converter systems with the same mechanism to sensing a load current and regulate the DC-DC converter system are possible as well, such as the DC-DC converter systems300to1500respectively shown inFIGS.3-15.

Starting at step1702, the control logic124generates a PWM signal to switch the first switch102from a first state, e.g. on state, to a second state, e.g. off state, through the driver unit112.

At step1704, the first timer202of the timer unit122starts timing a first duration T1, and substantially simultaneously, the second timer212of the timer unit122starts timing a second duration T2that is determined based on input and output voltages VIN and VOUT of the DC-DC converter system100and a minimum duration of the first state of the first switch102, i.e., the minimum on-time Ton_min, of the first switch102.

In one example, for adaptive off-time/on-time current mode DC-DC converter systems such as the DC-DC converter systems100to700ofFIGS.1,3,5and7with corresponding timer units200to800ofFIGS.2A,4,6and8, the first and second timers202and212are configured to start timing upon the first switch102being switched from the first state to the second state, the first duration T1is a nominal duration of the second state of the first switch102determined based on a target switching frequency fsw of the DC-DC converter system and the input and output voltages, and the second duration T2is an adjusted duration of the second state of the first switch determined based on the input and output voltages VIN and VOUT and a predetermined duration substantially equal to greater than a minimum duration of the first state of the first switch.

In the example with reference to the DC-DC converter system100ofFIG.1, the first duration T1is a nominal duration of the off state, i.e., a nominal off time Toff, of the first switch102, and provided in accordance with the equations below:
T1=T·VIN/VOUT  (11)
where T is a target switching cycle T=1/fsw of the DC-DC converter system100, fsw is a target switching frequency of the DC-DC converter system100.

The second duration T2is an adjusted duration of the off state, i.e., an adjusted off-time, of the first switch102determined based on the input and output voltages VIN and VOUT and a predetermined duration Ton_min′ substantially equal to or greater than a minimum duration of the on state, i.e., a minimum on-time Ton_min, of the first switch102. The second duration T2is provided in accordance with the equations below:

T⁢2=Ton_min′·VOUTVOUT-V⁢I⁢N(12)
where Ton_min′ is the predetermined duration substantially equal to or slightly greater, e.g. 10 ns greater, than the minimum on-time Ton_min of the first switch902.

In another example, for fixed frequency current mode DC-DC converter systems such as the DC-DC converter systems900ofFIG.9with a timer unit1000ofFIG.10, the first and second timers start timing upon the first switch902being switched from the second state to the first state, e.g., for the DC-DC converter system900, from the off state to the on state. The first duration T1is the target switching cycle T of the DC-DC converter system900. The second duration T2is an adjusted switching cycle determined based on the input and output voltages VIN and VOUT and a predetermined duration Ton_min′ substantially equal to or greater than the minimum on time Ton_min of the first switch902. The second duration T2is provided in accordance with the equations below:

T⁢2=Ton_min′·VINVOUT-VIN(13)
where Ton_min′ is the predetermined duration substantially equal to or slightly greater, e.g. 10 ns greater, than the minimum on-time Ton_min of the first switch902.

At step1706, the sensing unit114generates a control signal Sc to switch the first switch102from the first state, e.g. the on state, to the second state, e.g. the off state, based on a difference between a sensed voltage Vs proportional to the inductor current IL and a difference between a reference voltage VREF and a feedback voltage VFB proportional to the output voltage VOUT.

In one example, for DC-DC converter systems with a peak current control topology, such as the DC-DC converter systems100,700,900and1300respectively shown inFIGS.1,7,9and13, switching the first switch from the first state to the second state comprises switching the first switch from the on state to the off state upon a current through the first switch increasing to a peak value determined based on the difference between the feedback voltage VFB of the output voltage VOUT and the reference voltage VREF and expiration of a minimum on-time of the first switch.

In another example, for DC-DC converter systems with a valley current control topology, such as the DC-DC converter systems300,500,1100and1500respectively shown inFIGS.3,5,11and15, switching the first switch from the first state to the second state comprises switching the first switch from an off state to an on state upon a current through the second switch decreasing to a valley value determined based on a difference between the feedback voltage VFB of the output voltage VOUT and a reference voltage VREF and expiration of a minimum off-time of the first switch.

At step1708, the timer unit122generates an expiration signal STto switch the first switch102from the second state to the first state upon expiration of both the first and second timers.

The description of the preferred implementations of the present disclosure has been presented for purposes of illustration and description, but is not intended to be exhaustive or to limit the disclosure to the forms disclosed. Numerous modifications, changes, variations, substitutions, and equivalents will be apparent to those skilled in the art, without departing from the spirit and scope of the present disclosure, as described in the claims.