Memory controller including plurality of address mapping tables, system on chip, and electronic device

A memory controller includes a memory request queue that stores a memory request associated with a memory device including the first memory die and the second memory die having a shared channel, an address converter that selects one of first and second address mapping tables for the first memory die and the second memory die based on a bit of a physical address of the memory request and converts the physical address into a memory address based on the selected address mapping table and a physical layer that transmits the memory address to the memory device through the channel.

CROSS-REFERENCE TO THE RELATED APPLICATIONS

This application is based on and claims priority under 35 U.S.C. § 119 to Korean Patent Application No. 10-2020-0005882 filed on Jan. 16, 2020, in the Korean Intellectual Property Office, the disclosures of which are incorporated by reference herein in their entireties.

BACKGROUND

The inventive concept relates to a memory controller, a system on chip, and an electronic device capable of storing a plurality of address mapping tables.

Recently, a plurality of semiconductor dies are stacked to increase the degree of integration of a memory device. As such, a memory device of a three-dimensional structure may process a large amount of data at a high speed. To implement the three-dimensional structure, a through silicon via (TVS) may be used to stack a plurality of semiconductor dies. However, even though a data processing speed increases, the separation of a processor from a memory causes a latency of data that are transmitted between the processor and the memory. To solve this issue, a processing in memory (PIM) in which the processor and the memory are integrated is on the spotlight.

SUMMARY

Embodiments of the inventive concept provide a memory controller, a system on chip, and an electronic device capable of storing a plurality of address mapping tables.

According to an exemplary aspect of the disclosure, there is provided a memory controller comprising: a memory request queue configured to store a memory request associated with a memory device including a first memory die and a second memory die having a shared channel; an address converter configured to select one of a first address mapping table and a second address mapping table based on a bit of a physical address of the memory request and to convert the physical address into a memory address for the first memory die and the second memory die based on the selected one of the first address mapping table and the second address mapping table; and a physical layer configured to transmit the memory address to the memory device through the shared channel.

According to another exemplary aspect of the disclosure, there is provided a system on chip comprising: a processor configured to generate a memory request; and a memory controller configured to: select one of a first address mapping table and a second address mapping table based on a bit of a physical address of the memory request; convert the physical address into a memory address of a memory device based on the selected one of the first address mapping table and the second address mapping table; and access one of a first memory die or a second memory die through a shared channel based on the memory address.

According to another exemplary aspect of the disclosure, there is provided an electronic device comprising: a memory device comprising a first memory die, a second memory die, and a shared channel for the first memory die and the second memory die; and a system on chip comprising: a processor configured to generate a memory request; and a memory controller configured to: select one of a first address mapping table and a second address mapping table based on a bit of a physical address of the memory request, convert the physical address into a memory address of the memory device based on the selected one of the first address mapping table and the second address mapping table, and access one of the first memory die and the second memory die through the shared channel based on the memory address.

According to another exemplary aspect of the disclosure, there is provided an address converter circuit comprising: an address range register configured to store a bit of a physical address of a memory request; a plurality of address converting circuits, each of the plurality of address converting circuits configured to convert the physical address into a memory address based on one of a plurality of address mapping tables; and a mapping selecting circuit configured to select one of the plurality of address converting circuits based on a value of the bit stored in the address range register.

DETAILED DESCRIPTION

FIG. 1illustrates an electronic device100aaccording to an example embodiment of the inventive concept. The electronic device100amay include a system on chip (SoC)1000, a memory device2000, and an interposer3000. The electronic device100amay be also referred to as a “computing system” or an “electronic system”.

The system on chip1000may execute applications that the electronic device100asupports by using the memory device2000. The system on chip1000may also be referred to as a “host” or an “application processor (AP)”. The system on chip1000may include a memory controller1100that controls the memory device2000and performs an operation to input data to the memory device2000and/or output data from the memory device2000. For example, the memory controller1100may access the memory device2000in a direct memory access (DMA) manner. The memory controller1100may include a physical layer (PHY)1130that is electrically connected with a PHY2930of the memory device2000through the interposer3000.

The memory device2000may include processing in memory or processor in memory (PIM) dies2100to2800and a buffer die2900. Each of the PIM dies2100to2800may be also referred to a “memory die”, a “core die”, a “function in memory (FIM) die”, or a “controlee die”, and the buffer die2900may be also referred to as an “interface die”, a “logic die”, or a “controller die”. A die may be also referred to as a “chip”. The PIM die2100may be stacked on the buffer die2900, and the PIM die2200may be stacked on the PIM die2100. The memory device2000may have a three-dimensional memory structure in which the plurality of dies2100to2900are stacked. To stack the dies2100to2900, the memory device2000may include through silicon vias TSV penetrating the dies2100to2900and micro bumps BP electrically connecting the through silicon vias TSV. The through silicon vias TSV and the micro bumps BP may provide electrical and physical paths between the dies2100to2900in the memory device2000. Here, the number of through silicon vias TSV and the number of micro bumps BP are not limited to the example illustrated inFIG. 1.

The memory device2000may relate to the PIM or FIM and may further perform a data processing operation in addition to reading and writing data. The memory device2000may correspond to a computational memory device including a random access memory (RAM) and a processing element (PE) integrated in the same die. Each of the PIM dies2100to2800of the memory device2000may include a memory cell array MCA that is used to read and write data and includes a plurality of memory cells and a processing element PE that executes a processing operation on data. For example, the PE may be also referred to as a “processor” or a “processing circuit”.

A stack identifier SID0may be allocated to the PIM dies2100to2400, and a stack identifier SID1may be allocated to the PIM dies2500to2800. The stack identifier SID0and SID1may be used to identify or distinguish the plurality of PIM dies2100to2800stacked on the buffer die2900. For example, the memory controller1100may access the PIM dies2100to2400using the stack identifier SID0or the memory controller1100may access the PIM dies2500to2800by using the stack identifier SID1. Here, the total number of PIM dies2100to2800are not limited to the example illustrated inFIG. 1. Also, the number of PIM dies2100to2400per stack identifier SID0and or the number of PIM dies2500to2800per stack identifier SID1are not limited to the example illustrated inFIG. 1.

The buffer die2900may operate as an interface circuit between the memory controller1100and the PIM dies2100to2800. The buffer die2900may receive a command, data, signals, etc. transmitted from the memory controller1100through the interposer3000and may transmit the received command, data, signals, etc. to the PIM dies2100to2800through the through silicon vias TSV and the micro bumps BP. The buffer die2900may receive data output from the PIM dies2100to2800through the through silicon vias TSV and the micro bumps BP and may transmit the received data to the memory controller1100through the interposer3000. The buffer die2900may include the PHY2930, buffering circuits, or interface circuits that receive and amplify the above signals.

In an example embodiment, the memory device2000may be a general-purpose dynamic random access memory (DRAM) such as DDR SDRAM (Double Data Rate Synchronous Dynamic Random Access Memory), a mobile DRAM device such as LPDDR (low power double data rate) SDRAM, a graphics DRAM device such as GDDR (Graphics Double Data Rate) SGRAM (Synchronous Graphics Random Access Memory), or a DRAM device, which provides a high capacity and a high bandwidth, such as Wide I/O, HBM (High Bandwidth Memory), HBM2, HBM3, or HMC (Hybrid Memory Cube).

The interposer3000may connect the system on chip1000and the memory device2000. The interposer3000may provide physical paths that connect the PHY2930of the memory device2000and the PHY1130of the system on chip1000and are formed of conductive materials for an electrical connection. A substrate or a printed circuit board (PCB) may be used instead of the interposer3000.

FIG. 2illustrates an electronic device according to another example embodiment of the inventive concept. An electronic device100bmay include the system on chip1000and the memory device2000. The system on chip1000and the memory device2000in the electronic device100amay be interconnected through the interposer3000, while the memory device2000of the electronic device100bmay be stacked on the system on chip1000. The system on chip1000may further include the through silicon vias TSV that are used to implement an electrical connection with the memory device2000, PHY1130of the system on chip1000, the PHYS2930of the memory device2000may be electrically interconnected through the micro bumps BP.

FIG. 3illustrates a block diagram of a memory controller of a system on chip ofFIGS. 1 and 2. The memory controller1100may include a memory request queue1110, an address converter1120, and the PHY1130. For example, the above components, a memory request queue1110, an address converter1120, and the PHY1130, and other components of the memory controller1100may be implemented by hardware.

The memory request queue1110may receive and store a memory request that is generated within the system on chip1000. A memory request associated with the memory device2000may request an operation (e.g., a read operation, a write operation, a refresh operation, or a processing operation) of the memory device2000and may include a physical address of the memory device2000. The physical address may be used to access the memory device2000and may be limited according to a capacity of the memory device2000. According to an example embodiment, unlike a virtual address, the physical address may be limited according to a capacity of the memory device2000. A speed at which a memory request is generated at the system on chip1000may be higher than a speed at which a memory request is processed by the memory device2000. The memory request queue1110may store a plurality of memory requests.

The address converter1120may convert a physical address PA of a memory request stored in the memory request queue1110into a memory address MA. The memory address MA may be used to access the memory device2000and may indicate a specific area of the memory device2000. According to an example embodiment, the specific area may be a specific die, or a register or memory cells in a specific die. The address converter1120may convert the physical address PA into the memory address MA based on a plurality of address mapping tables. For example, the plurality of address mapping tables may include a first address mapping table AMT1and a first address mapping table AMT2.

For example, the address converter1120may select one of the plurality of address mapping tables AMT1and AMT2based on a logical value (e.g., 0 or 1) of a bit of the physical address PA, which corresponds to the stack identifier SID of the memory address MA, and may convert the physical address PA into the memory address MA based on the selected address mapping table. According to the example embodiment illustrated inFIG. 3, the number of address mapping tables is two, i.e., AMT1and AMT2. As such, the description is given as the number of bits used to select the plurality of address mapping tables AMT1and AMT2is one. However, the number of address mapping tables is not limited to 2, instead the number of address mapping tables is more than 2e. In this case, the number of bits used to select the plurality of address mapping tables AMT1and AMT2may be more than one. For another example, a most significant bit MSB of the physical address PA may be used to select the plurality of address mapping tables AMT1and AMT2.

According to an example embodiment, the address converter1120may check a first logical value of the bit of the physical address PA, which corresponds to the stack identifier SID of the memory address MA, and may select the address mapping table AMT1. The address converter1120may divide or classify bits of the physical address PA into fields F1to F6based on the address mapping table AMT1. A bit of the field F1may correspond to a bit (or an upper bit) above bits of the field F6. For example, the bit of the field F1may be the MSB of the physical address PA. The address mapping table AMT1may map the bit of the field F1onto the stack identifier SID, bits of the field F2onto a row address Row, bits of the field F3onto a column address Column, bits of the fields F4and F5onto a bank address BA0to BA3, and the bits of the field F6being bits (or lower bits) below the fields F1to F5onto a cache line CL. The address converter1120may map the bit of the field F1onto the stack identifier SID, the bits of the field F2onto the row address Row, the bits of the field F3onto the column address Column, and the bits of the fields F4and F5onto the bank address BA0to BA3based on the address mapping table AMT1. The memory address MA may include the stack identifier SID, the bank address BA0to BA3, the row address Row, and the column address Column. The stack identifier SID may be used to identify the PIM dies2100to2800described with reference toFIGS. 1 to 2. The bank address BA0to BA3may be used to identify banks constituting the memory cell array MCA of each of the PIM dies2100to2800. The row address Row and the column address Column may be used to identify memory cells in a bank. The cache line CL may correspond to a unit of a cache in the system on chip1000and may include data associated with the memory device2000(e.g., read data read from the memory device2000or write data to be written in the memory device2000). The bits of the fields F1to F5may constitute the memory address MA. The address mapping table AMT1may map upper bits of the physical address PA onto the stack identifier SID, the row address Row, and the column address Column of the memory address MA and may map lower bits of the physical address PA onto the bank address BA0to BA3of the memory address MA. When the address mapping table AMT1is selected, the bits of the physical address PA converted into the bank address BA0to BA3of the memory address MA may correspond to bits (or lower bits) below the bits of the physical address PA converted into the row address Row and the column address Column of the memory address MA. The number of bits included in each of the fields F1to F6may be one or more.

According to an example embodiment, the address converter1120may check the second logical value of the bit of the physical address PA, which corresponds to the stack identifier SID of the memory address MA, and selects the address mapping table AMT2. The address converter1120may divided or classify bits of the physical address PA into fields F1to F7based on the address mapping table AMT2. The address mapping table AMT2may map the bit of the field F1onto the stack identifier SID, bits of the field F3onto the row address Row, bits of the field F5onto the column address Column, bits of the fields F2, F4, and F6onto the bank address BA0to BA3, and bits of the field F7being bits (or lower bits) below the fields F1to F6onto the cache line CL. The address converter1120may map the bit of the field F1onto the stack identifier SID, the bits of the field F3onto the row address Row, the bits of the field F5onto the column address Column, and the bits of the fields F2, F4, and F6onto the bank address BA0to BA3based on the address mapping table AMT2. The bits of the fields F1to F6may constitute the memory address MA. When not the address mapping table AMT1but the address mapping table AMT2is selected, at least one (being BA1inFIG. 3but being not limited thereto) of the bits of the physical address PA converted into the bank address BA0to BA3of the memory address MA may correspond to a bit (or an upper bit) above the bits of the physical address PA converted into the column address Column of the memory address MA. Also, at least one (being BA0inFIG. 3but being not limited thereto) of the bits of the physical address PA converted into the bank address BA0to BA3of the memory address MA may correspond to a bit (or an upper bit) above the bits of the physical address PA converted into the row address Row of the memory address MA. For example, the bits of the physical address PA converted into the row address Row or the column address Column of the memory address MA may be placed between the bits of the physical address PA converted into the bank address BA0to BA3of the memory address MA. A location on the physical address PA, at which the bit of the field F1converted into the stack identifier SID by the address mapping table AMT1is placed, may be identical to a location on the physical address PA, at which the bit of the field F1converted into the stack identifier SID by the address mapping table AMT2is placed. A location on the physical address PA, at which the bits of the field F6corresponding to the cache line CL are placed according to the address mapping table AMT1, may be identical to a location on the physical address PA, at which the bits of the field F7corresponding to the cache line CL are placed according to the address mapping table AMT2.

According to the example embodiment described above, the address converter1120checks first logical value of the bit of the physical address PA and selects the address mapping table AMT1, and the address converter1120checks the second logical value of the bit of the physical address PA, and selects the address mapping table AMT2. However, the disclosure is not limited thereto. For instance, according to another example embodiment, the address converter1120may check the second logical value of the bit of the physical address PA and select the address mapping table AMT1, and the address converter1120may check a first logical value of the bit of the physical address PA, and select the address mapping table AMT2.

The mapping of the address mapping table AMT1and the mapping of the address mapping table AMT2may be different from each other and may be independent of each other. For example, locations of the bits of the physical address PA converted into the bank address BA0to BA3of the memory address MA by the address mapping table AMT1may be different from locations of the bits of the physical address PA converted into the bank address BA0to BA3of the memory address MA by the address mapping table AMT2. For example, locations on the physical address PA, at which bits corresponding to the bank address BA0to BA3are placed, may be changed according to the address mapping tables AMT1and AMT2.

The address converter1120may simultaneously support the address mapping tables AMT1and AMT2that are different. A way to arrange data in the memory device2000when the address mapping table AMT1is selected may be different from a way to arrange data in the memory device2000when the address mapping table AMT2is selected. For example, the memory controller1100may select the address mapping table AMT1with regard to a PIM die (e.g., the PIM dies2100to2400having SID0ofFIGS. 1 and 2), which is intended to perform a read operation or a write operation without the execution of the PE, from among the plurality of PIM dies2100to2800. In contrast, the memory controller1100may select the address mapping table AMT2with regard to a PIM die (e.g., the PIM dies2500to2800having SID1ofFIGS. 1 and 2), which is intended to execute the PE, from among the plurality of PIM dies2100to2800. According to the exemplary manner of selecting an address mapping table, the arrangement of data in the PIM die performing only the read operation or the write operation may be different from the arrangement of data in the PIM die executing the PE. Accordingly, as the memory controller1100according to an embodiment of the inventive concept dynamically selects one of the address mapping tables AMT1and AMT2depending on whether to execute the PE in the PIM die, the memory controller1100may arrange data to be appropriate for the read operation or the write operation in the PIM die not executing the PE and may arrange data to be appropriate for the execution of the PE in the PIM die executing the PE.

The PHY1130may access the memory device2000based on the memory address MA of the address converter1120. The PHY1130may be also referred to as a “memory interface circuit”. For example, the PHY1130may generate and output command and address signals CA based on a memory request of the memory request queue1110and the memory address MA of the address converter1120. The PHY1130may transmit a memory command and the memory address MA, which are based on the memory request, to the memory device2000. The PHY1130may variously change logical values of the command and address signals CA depending on the memory request of the memory request queue1110and the memory address MA of the address converter1120. The PHY1130may generate and output data input/output signals DQ based on the memory request of the memory request queue1110or may receive the data input/output signals DQ transmitted from the memory device2000. The data input/output signals DQ may include write data to be written in the memory device2000or read data read from the memory device2000.

The command and address signals CA and the data input/output signals DQ may be provided for each of channels CH1to CH4. For example, the memory controller1100may access the PIM dies2100and2500through the channel CH1, may access the PIM dies2200and2600through the channel CH2, may access the PIM dies2300and2700through the channel CH3, and may access the PIM dies2400and2800through the channel CH4. The PIM dies2100and2500may share the channel CH1, the PIM dies2200and2600may share the channel CH2, the PIM dies2300and2700may share the channel CH3, and the PIM dies2400and2800may share the channel CH4.

The memory controller1100may select one of a plurality of PIM dies allocated to one channel, by using the stack identifier SID of the memory controller1100. The memory controller1100may access one of a plurality of PIM dies allocated to one channel based on the memory address MA. For example, when the stack identifier SID has a first logical value (i.e., SID0), the command and address signals CA and the data input/output signals DQ transmitted through the channels CH1to CH4may be associated with the PIM dies2100to2400. For example, when the stack identifier SID has a second logical value (i.e., SID1), the command and address signals CA and the data input/output signals DQ transmitted through the channels CH1to CH4may be associated with the PIM dies2500to2800. For example, the number of PIM dies allocated per channel, the number of channels, the number of channels allocated to one PIM die, etc. are not limited to the example ofFIG. 3. For example, a part (e.g., bits (or upper bits) above the field F1) of bits of the physical address PA may indicate whether the memory address MA is associated with any channel of the channels CH1to CH4and may be used to distinguish the channels CH1to CH4.

FIG. 4illustrates a block diagram of an address converter ofFIG. 3. The address converter1120may include an address range register1121, a mapping selecting circuit1122, and address converting circuits1123_1to1123_2M. For example, the address range register1121, the mapping selecting circuit1122, and the address converting circuits1123_1to1123_2M, and other components of the address converter may be implemented in a hardware manner.

The address range register1121may store a bit PA[N:N−M+1] of a physical address PA[N:0] (N being a natural number, “N+1” corresponding to the number of bits, and M being a natural number). Similar the case ofFIG. 3, in the case where the address converter1120includes two address mapping tables AMT1and AMT2, “M” may be “1”, and the address range register1121may store a bit PA[N]. The address converter1120may include two or more address mapping tables, and the address range register1121may store one or more bits. As described above, the bit PA[N:N−M+1] stored in the address range register1121may be the stack identifier SID of the memory address MA.

The mapping selecting circuit1122may select one of the address converting circuits1123_1to1123_2Mdepending on a value of the bit PA[N:N−M+1] stored in the address range register1121. For example, the mapping selecting circuit1122may activate one of enable signals EN_1to EN_2Mfor enabling the address converting circuits1123_1to1123_2Mdepending on a value of the bit PA[N:N−M+1] stored in the address range register1121and may deactivate the remaining enable signals.

The address converting circuit1123may be activated by the enable signal EN_1and may convert the physical address PA[N:0] into a memory address MA[L:0] (L being a natural number and smaller than N) based on the address mapping table AMT1(being identical to the address mapping table AMT1ofFIG. 3). The address converting circuit1124may be activated by the enable signal EN_2Mand may convert the physical address PA[N:0] into the memory address MA[L:0] based on the address mapping table AMT2(being identical to the address mapping table AMT2ofFIG. 3). The address converter1120may include 2Maddress mapping tables performing different mapping and may include 2Maddress converting circuits1123_1to1123_2Mconverting the physical address PA[N:0] into the memory address MA[L:0] based on the 2Maddress mapping tables, respectively.

FIG. 5illustrates a block diagram of a system on chip ofFIGS. 1 and 2. The system on chip1000may include the memory controller1100, a processor1200, an on-chip memory1300, and a system bus1400.

The memory controller1100may include the memory request queue1110, the address converter1120, the PHY1130, a control register1141, a bank state register1142, a system bus interface circuit1150, a memory command queue1160, a command scheduler1170, a command sequencer1180, a read buffer1191, and a write buffer1192. Detailed description of the memory request queue1110, the address converter1120supporting all the different address mapping tables AMT1and AMT2, and the PHY1130are provided with respect toFIGS. 3 and 4, and thus additional description associated with the memory request queue1110, the address converter1120, and the PHY1130will be omitted to avoid redundancy.

The control register1141may store and provide pieces of control information of the memory request queue1110, the address converter1120, the PHY1130, the control register1141, the bank state register1142, the system bus interface circuit1150, the memory command queue1160, the command scheduler1170, the command sequencer1180, the read buffer1191, and the write buffer1192in the memory controller1100. The control information stored in the control register1141may be changed by the processor1200or by a request of a user. The memory request queue1110, the address converter1120, the PHY1130, the control register1141, the bank state register1142, the system bus interface circuit1150, the memory command queue1160, the command scheduler1170, the command sequencer1180, the read buffer1191, and the write buffer1192may operate based on the pieces of control information stored in the control register1141, respectively.

The bank state register1142may store state information of a plurality of banks (refer toFIGS. 7 and 8for detailed description) in the memory device2000. For example, the state information may indicate whether a bank is activated or whether a bank is precharged.

The system bus interface circuit1150may receive memory requests transmitted from a plurality of cores1210,1220,1230, and1240in the processor1200through the system bus1400based on a communication protocol of the system bus1400. The system bus interface circuit1150may provide, transmit, or write the received memory request to the memory request queue1110. According to another example embodiment, the plurality of cores in the processor1200are not limited to the plurality of cores1210,1220,1230, and1240illustrated inFIG. 5.

The memory command queue1160may store memory commands for memory requests stored in the memory request queue1110and memory addresses converted by the address converter1120. The command scheduler1170may adjust the order of processing memory commands and memory addresses stored in the memory command queue1160based on state information of banks stored in the bank state register1142. The command scheduler1170may perform scheduling on memory commands and memory addresses stored in the memory command queue1160. The command sequencer1180may output or provide memory commands and memory addresses stored in the memory command queue1160to the PHY1130based on the order scheduled by the command scheduler1170.

The PHY1130may include a clock (CK) generator1131, a command and address (CA) generator1132, a receiver1133, and a transmitter1134. The clock generator1131may generate a clock signal CK that is output to the memory device2000. For example, the memory device2000may be a synchronous memory device that operates based on the clock signal CK. The command and address generator1132may receive a memory command and a memory address from the command sequencer1180and may transmit the command and address signals CA including the memory command and the memory address to the memory device2000. The receiver1133may receive the data input/output signals DQ including read data transmitted from the memory device2000. The receiver1133may provide the received read data to the read buffer1191. The transmitter1134may receive write data from the write buffer1192. The transmitter1134may transmit the data input/output signals DQ including the write data to the memory device2000. A channel CH ofFIG. 5may correspond to one of the channels CH1to CH4ofFIG. 3. The PHY1130may generate and output the clock signal CK and the command and address signals CA of each of the channels CH1to CH4and may exchange the data input/output signals DQ of each of the channels CH1to CH4with the memory device2000.

The read buffer1191may store read data provided from the receiver1133. For example, the read buffer1191may provide the system bus interface circuit1150with read data as much as a cache line CL, and the system bus interface circuit1150may transmit the read data to the processor1200or the on-chip memory1300through the system bus1400. The write buffer1192may receive and store write data that are provided from the system bus interface circuit1150so as to be transmitted to the memory device2000. The write buffer1192may provide the transmitter1134with write data as much as a data input/output unit of the memory device2000.

The processor1200may execute various software (e.g., an application program, an operating system, a file system, and a device driver) loaded onto the on-chip memory1300. The processor1200may include a plurality of homogeneous cores or a plurality of heterogeneous cores and may include the plurality of cores1210to1240. For example, each of the cores1210to1240may include at least one of a central processing unit (CPU), an image signal processing unit (ISP), a digital signal processing unit (DSP), a graphics processing unit (GPU), a vision processing unit (VPU), a tensor processing unit (TPU), and a neural processing unit (NPU). Each of the cores1210to1240may generate a memory request associated with the memory device2000. The memory request generated by each of the cores1210to1240may include the physical address PA described above. An application program, an operating system, a file system, a device driver, etc. for driving the electronic device100a/100bmay be loaded onto the on-chip memory1300. For example, the on-chip memory1300may be a static RAM (SRAM) having a data input/output speed higher than the memory device2000or may be a cache memory shared by the cores1210to1240, but the inventive concept is not limited thereto. The system bus1400may provide a communication path between the memory controller1100, the processor1200, and the on-chip memory1300. For example, the system bus1400may be AHB (Advanced High-performance Bus), ASB (Advanced System Bus), APB (Advanced Peripheral Bus), or AXI (Advanced eXtensible Interface) that is based on the AMBA (Advanced Microcontroller Bus Architecture).

FIG. 6illustrates a memory device ofFIGS. 1 and 2in detail. The memory controller1100may access the memory device2000through channels CH1to CHK (K being a natural number of 2 or more). For example, the PIM dies2100and2500may be allocated to the channel CH1, and the PIM dies2400and2800may be allocated to the channel CHk. As in the above description, the remaining dies2200,2300,2600and2700may be allocated to other channels. The PIM dies2100and2500allocated to the same channel CH may be identified by the stack identifier SID0/1. The memory device2000may include paths Path_1to Path_K that respectively correspond to the channels CH1to CHK and through which signals transmitted through the channels CH1to CHK are transmitted. The paths Path_1to Path_K may provide electrical connection paths between the buffer die2900and the PIM dies2100to2800and may include the through silicon vias TSV and the micro bumps BP described with reference toFIGS. 1 and 2.

The PIM die2500may include bank groups BG0to BG3, data buses DB0and DB1, bank controllers BCTRL0and BCTRL1, PE controllers PECTRL0and PECTRL1, a command and address decoder CADEC, and a data input/output circuit DATAIO. Although, only the PIM die2500may be in detail described and illustrated, configurations and operations of the remaining PIM dies2100to2400and2600to2800may be similar or substantially identical to those of the PIM die2500.

The bank groups BG0to BG3may be identified by bank address bits BA2and BA3of a bank address BA0to BA3(or referred to as “bank address bits BA0to BA3”). For example, when BA2=0 and BA3=0, the bank group BG0may be selected. The bank group BG0may include banks BK0to BK3. Banks in one bank group may be identified by bank address bits BA0and BA1of the bank address BA0to BA3. For example, when BA0=0, BA1=0, BA2=0, and BA3=0, the bank BK0may be selected. The memory cell array MCA ofFIGS. 1 and 2may be divided into banks BK0to BK15. Each of banks BK0, BK2, BK4, BK6, BK8, BK10, BK12, and BK14capable of being selected when the bank address bit BA0corresponding to an LSB from among the bank address bits BA0to BA3is “0” may be referred to as a top (or even-numbered) bank. Each of banks BK1, BK3, BK5, BK7, BK9, BK11, BK13, and BK15capable of being selected when the bank address bit BA0corresponding to an LSB from among the bank address bits BA0to BA3is “1” may be referred to as a bottom (or odd-numbered) bank. For example, each of the banks BK0to BK15may include an equal number of memory cells, and each of the bank groups BG0to BG3may include an equal number of banks. For example, the bank groups BG0to BG3may be implemented to be identical, and the banks BK0and BK15may be implemented to be identical.

The bank group BG0may include a PE0and a PE1. For example, the PE0may execute a calculation on data of the banks BK0and BK1, and the PE1may execute a calculation on data of the banks BK2and BK3. The bank group BG1may include a PE2executing a calculation on data of the banks BK4and BK5and a PE3executing a calculation on data of the banks BK6and BK7. As in the bank groups BG0and BG1, the bank groups BG2and BG3may include PE4to PE7. For example, the PE0to the PE7may correspond to the PE of each of the PIM dies2100to2800ofFIGS. 1 and 2or may constitute the PE of each of the PIM dies2100to2800ofFIGS. 1 and 2.

The number of bank groups included in one PIM die2500and the number of banks per bank group are not limited to the example ofFIG. 6. An example is illustrated as one channel CH1is allocated to the PIM die2500and the bank groups BG0to BG3and the banks BK0to BK15are allocated to the channel CH1, but the inventive concept is not limited thereto. A different channel or channels may be further allocated to the PIM die2500, and the PIM die2500may further include bank groups and banks allocated to the different channel(s). For example, the PIM die2500may include the bank groups BG0to BG15and the banks BK0to BK63allocated to four channels CH1to CH4; as in the channel CH1exemplified inFIG. 6, bank groups and banks for each channel may be implemented in the PIM die2500. The description is given as one bank group includes two PEs and one PE is allocated to two banks; however, one bank group may include PEs same as the number of banks, or one PE may be allocated to one bank. In any case, the inventive concept is not limited to the above numerical values.

The data bus DB0may include data input/output paths associated with the bank groups BG0and BG1. For example, data to be written in the banks BK0to BK3or the banks BK4to BK7, data read from the banks BK0to BK3or the banks BK4to BK7, data to be processed by the PE0and the PE1or the PE2and the PE3, data processed by the PE0and the PE1or the PE2and the PE3, etc. may be transmitted through the data bus DB0. The data bus DB1may include data input/output paths associated with the bank groups BG2and BG3. Except for allocated bank groups, the data buses DB0and DB1may be implemented to be identical or may be integrated.

The bank controller BCTRL0may control the banks BK0to BK7of the bank groups BG0and BG1under control of the command and address decoder CADEC. The bank controller BCTRL1may control the banks BK8to BK15of the bank groups BG2and BG3under control of the command and address decoder CADEC. For example, the bank controllers BCTRL0and BCTRL1may activate or precharge the banks BK0to BK15. Except for allocated bank groups, the bank controllers BCTRL0and BCTRL1may be implemented to be identical or may be integrated.

The PE controller PECTRL0may control the PE0to the PE3of the bank groups BG0and BG1under control of the command and address decoder CADEC. The PE controller PECTRL1may control the PE4to the PE7of the bank groups BG2and BG3under control of the command and address decoder CADEC. For example, the PE controllers PECTRL0and PECTRL1may select data to be processed by the PE0to the PE7or data processed by the PE0to the PE7or may control timings at which the PE0to the PE7initiate or terminate calculations. Except for allocated PEs, the PE controllers PECTRL0and PECTRL1may be implemented to be identical or may be integrated.

The command and address decoder CADEC may receive command and address signals CA (refer toFIG. 5) transmitted through the channel CH1and the path Path_1, based on a clock signal CK (refer toFIG. 5) transmitted through the channel CH1and the path Path_1. The command and address decoder CADEC may decode the command and address signals CA. The command and address decoder CADEC may control components of the PIM die2500based on a decoding result.

Under control of the command and address decoder CADEC, the data input/output circuit DATAIO may receive the data input/output signals DQ (refer toFIG. 5) transmitted through the channel CH1and the path Path_1and may provide write data included in the data input/output signals DQ to the banks BK0to BK15of the bank groups BG0to BG3. The data input/output circuit DATAIO may receive read data output from the banks BK0to BK15and the PEs PE0to PE7of the bank groups BG0to BG3and may output the data input/output signals DQ including the read data. The data input/output signals DQ including the read data may be transmitted to the memory controller1100through the path Path_1and the channel CH1.

FIG. 7illustrates a memory device ofFIGS. 1 and 2in detail. A description will be focused on a difference between the memory device2000ofFIG. 6and the memory device2000ofFIG. 7. The memory device2000may include the memory dies2100to2400and the PIM dies2500to2800. Each of the PIM dies2500to2800may be substantially identical to the PIM die2500ofFIG. 6. Each of the memory dies2100to2400may be different from the PIM die2500ofFIG. 6. The memory die2300may include the bank groups BG0to BG3, the banks BK0to BK15, the data buses DB0and DB1, the bank controllers BCTRL0and BCTRL1, the command and address decoder CADEC, and the data input/output circuit DATAIO, which are described with reference toFIG. 6. The memory die2300may not include the PE0to the PE7and the PE controllers PECTRL0and PECTRL1and may not be referred to as a “PIM die”. A configurations and an operation of each of the remaining memory dies2100,2200, and2400may be substantially identical to the memory die2300.

FIG. 8illustrates an example in which a physical address is converted into a memory address by a memory controller ofFIG. 5. The memory controller1100may convert the physical address PA, in which a bit corresponding to a stack identifier has a value of SID0, from among the physical addresses PA into the memory address MA based on the address mapping table AMT1. The memory controller1100may convert the physical address PA, in which a bit corresponding to a stack identifier has a value of SID1, from among the physical addresses PA into the memory address MA based on the address mapping table AMT2different from the address mapping table AMT1. For example, a range of the physical addresses PA, in which a bit corresponding to a stack identifier has a value of SID0, may be from 0x000000 to 0x000FFF, and a range of the physical addresses PA, in which a bit corresponding to a stack identifier has a value of SID1, may be from 0x100000 to 0x100FFF. However, the inventive concept is not limited to the above numerical values.

According to the address mapping table AMT1, bits corresponding to the bank address BA0to BA3from among bits of the physical address PA of “0x000040” may be “0000(2)”. The memory controller1100may map the physical address PA of “0x000040” onto the bank BK0of the bank group BG0based on the address mapping table AMT1. For example, a difference between the physical address PA of “0x000040” and the physical address PA of “0x000080” may correspond to a size of the cache line CL (e.g., 64 bytes). According to the address mapping table AMT1, bits corresponding to the bank address BA0to BA3from among bits of the physical address PA of “0x000080” may be “0100(2)”. The memory controller1100may map the physical address PA of “0x000080” onto the bank BK4of the bank group BG1based on the address mapping table AMT1. As in the above description, the memory controller1100may convert the physical address PA, in which a bit corresponding to a stack identifier has a value of SID0, into the memory address MA based on the address mapping table AMT1. The physical address PA that sequentially increase from “0x000040” to “0x000400” may be mapped onto the banks BK0, BK4, BK8, and BK12corresponding to a top bank T_BK, the banks BK1, BK5, BK9, and BK13corresponding to a bottom bank B_BK, the banks BK2, BK6, BK10, and BK14corresponding to a top bank T_BK, and the banks BK3, BK7, BK11, and BK15corresponding to a bottom bank B_BK.

According to the address mapping table AMT2, bits corresponding to the bank address BA0to BA3from among bits of the physical address PA of “0x100040” may be “0000(2)”. The memory controller1100may map the physical address PA of “0x100040” onto the bank BK0of the bank group BG0based on the address mapping table AMT2. According to the address mapping table AMT2, bits corresponding to the bank address BA0to BA3from among bits of the physical address PA of “0x100080” may be “0100(2)”. The memory controller1100may map the physical address PA of “0x100080” onto the bank BK4of the bank group BG1based on the address mapping table AMT2. As in the above description, the memory controller1100may convert the physical address PA, in which a bit corresponding to a stack identifier has a value of SID1, into the memory address MA based on the address mapping table AMT2. The physical addresses PA that sequentially increase from “0x100040” to “0x100400” may be mapped onto the banks BK0, BK4, BK8, BK12, BK2, BK6, BK10, and BK14corresponding to a top bank T_BK and the banks BK1, BK5, BK9, BK13, BK3, BK7, BK11, and BK15corresponding to a bottom bank B_BK. The physical addresses PA that sequentially increase from “0x100040” to “0x100400” and the physical addresses PA that sequentially increase from “0x000040” to “0x000400” are changed to be identical except for the stack identifier SID0/SID1. Nevertheless, because the address mapping tables AMT1and AMT2are different, the order of mapping banks each corresponding to the physical address PA sequentially increasing from “0x100040” to “0x100400” is different from the order of mapping banks each corresponding to the physical address PA sequentially increasing from “0x000040” to “0x000400”.

FIG. 9illustrates a block diagram of a bank group ofFIG. 6. Although, only bank group BG0is illustrated in detail inFIG. 9, as described above, the remaining bank groups BG1to BG3may be implemented to be similarly or substantially identical to the bank group BG0.

The bank group BG0may include a row decoder RD0and a column decoder CD0. The row decoder RD0may decode the row address Row of the memory address MA and may select and activate a word line WL0of the bank BK0. For example, when the word line WL0is activated, the bank BK0may be in an active state. On the other hand, when the word line WL0is inactivated the bank BK0may be in a precharge state. As described above, state information of the bank BK0may be stored in the bank state register1142. The column decoder CD0may decode the column address Column of the memory address MA and may select and activate a column selection line CSL0of the bank BK0. The bank BK0may include memory cells MC0that are accessed through the word line WL0and the column selection line CSL0. The bank BK0may further include memory cells that are accessed through other word lines and other column selection lines.

The bank group BG0may further include an input/output sense amplifier IOSA0, a write driver WDRV0, a bank local input/output gating circuit BLIOGT0, a bank global input/output gating circuit BGIOGT0, and a data bus input/output gating circuit DBIOGT0. The input/output sense amplifier IOSA0may sense and amplify read data output from the memory cells MC0through cell input/output lines CIO0and may output the read data to bank local input/output lines BLIO0. The write driver WDRV0may receive write data transmitted through the bank local input/output lines BLIO0and may write the write data in the memory cells MC0through the cell input/output lines CIO0. The bank local input/output gating circuit BLIOGT0may electrically connect the write driver WDRV0and the bank local input/output lines BLIO0or may electrically disconnect the write driver WDRV0from the bank local input/output lines BLIO0. The bank local input/output gating circuit BLIOGT0may electrically connect the input/output sense amplifier IOSA0and the bank local input/output lines BLIO0or may electrically disconnect the input/output sense amplifier IOSA0from the bank local input/output lines BLIO0. The bank global input/output gating circuit BGIOGT0may electrically connect the bank local input/output lines BLIO0and bank global input/output lines BGIO0or may electrically disconnect the bank local input/output lines BLIO0from the bank global input/output lines BGIO0. The bank global input/output lines BGIO0may be shared by the banks BK0to BK3in the bank group BG0. The data bus input/output gating circuit DBIOGT0may electrically connect the bank global input/output lines BGIO0and the data bus DB0or may electrically disconnect the bank global input/output lines BGIO0from the data bus DB0. The data bus DB0may be shared by the bank groups BG0and BG1. For example, each of the bank local input/output gating circuit BLIOGT0, the bank global input/output gating circuit BGIOGT0, and the data bus input/output gating circuit DBIOGT0may operate as an input/output multiplexer or switch. The components RD0, CD0, IOSA0, WDRV0, BLIOGT0, and BGIOGT0described above may be for a data input/output of the bank BK0. As in the above description, for data inputs/outputs of the banks BK1to BK3, the bank group BG0may further include row decoders RD1to RD3, column decoders CD1to CD3, input/output sense amplifiers IOSA1to IOSA3, write drivers WDRV1to WDRV3, bank local input/output gating circuits BLIOGT1to BLIOGT3, and bank global input/output gating circuits BGIOGT1to BGIOGT3.

The PE0may include an input multiplexer IMUX, a PE array PEA, a register REG, and an output multiplexer OMUX. The input multiplexer IMUX may receive data (or write data or read data) of the bank BK0through the bank local input/output lines BLIO0, may receive data (or write data or read data) of the bank BK1through bank local input/output lines BLIO1, may data of the bank group BG0through the bank global input/output lines BGIO0, and may receive data of register output lines RO0. The input multiplexer IMUX may provide at least one of the pieces of above data to the PE array PEA based on an input control signal ICTRL0. For example, the above data may be provided to the PE array PEA as operands OPA to OPD. The PE array PEA may execute a calculation on at least one of the pieces of above data based on a processing control signal PCTRL0. For example, the calculation executable by the PE array PEA may be various arithmetic or logic operations such as addition, subtraction, multiplication, division, shift, AND, NAND, OR, NOR, XNOR, and XOR. The register REG may receive and store a calculation result of the PE array PEA through register input lines RIO based on a register control signal RCTRL0. The register REG may output the stored calculation result as data to the register output lines RO0based on the register control signal RCTRL0. The output multiplexer OMUX may output the data stored in the register REG to at least one of the bank local input/output lines BLIO0, the bank local input/output lines BLIO1, register output lines RO0, and the bank global input/output lines BGIO0, based on an output control signal OCTRL0. A configuration and an operation of the PE1may be substantially identical to the PE0except that the PE1is connected with bank local input/output lines BLIO2and BLIO3and receives control signals ICTRL1, PCTRL1, RCTRL1, and OCTRL1.

FIG. 10illustrates a block diagram of a PIM die ofFIG. 6. The command and address decoder CADEC may decode the command and address signals CA and may control the bank controllers BCTRL0and BCTRL1, the PE controllers PECTRL0and PECTRL1, and the data input/output circuit DATAIO. The bank controller BCTRL0may control read and write operations of memory cells of the bank groups BG0and BG1. The bank controller BCTRL1may control read and write operations of memory cells of the bank groups BG2and BG3. Each of the PE controllers PECTRL0and PECTRL1may include a control register storing control information. The PE controller PECTRL0may generate the control signals ICTRL0, ICTRL1, PCTRL0, PCTRL1, RCTRL0, RCTRL1, OCTRL0, and OCTRL1to be provided to the PE0and the PE1of the bank group BG0based on the control information of the control register, under control of the command and address decoder CADEC. The PE controller PECTRL0may generate control signals to be provided to the PE2and the PE3of the bank group BG1based on the control information of the control register under control of the command and address decoder CADEC. The PE controller PECTRL1may generate control signals to be provided to the PE4to the PE7of the bank groups BG2and BG3based on the control information of the control register under control of the command and address decoder CADEC. The data input/output circuit DATAIO may output data of the data input/output signals DQ to the data buses DB0and DB1or may output the data input/output signals DQ including data of the data buses DB0and DB1.

FIGS. 11 and 12illustrate examples in which data in a PIM die are arranged according to address mapping tables ofFIG. 3. InFIGS. 11 and 12, a memory request may be a write command for the memory device2000, memory requests are input to the memory request queue1110, the physical addresses PA of the memory requests sequentially increase from a minimum value (e.g., 0x000000 ofFIG. 8) to a maximum value (e.g., 0xFFFFFF), and each of the banks BK0to BK15includes memory cells MC accessible through four word lines WL[0:3] and four column selection lines CSL[0:3]. However, the inventive concept is not limited to the above numerical values.

The physical address PA having the stack identifier SID0may be converted into the memory address MA by the address mapping table AMT1. The address converter1120may select the address mapping table AMT1, and the PHY1130may access the PIM die2100through the channel CH1and may activate at least one of the banks BK0to BK15of the PIM die2100based on the memory address MA. According to the address mapping table AMT1, bits of the physical address PA, which correspond to the row address Row and the column address Column correspond to upper bits above bits of the physical address PA, which correspond to the bank address BA0to BA3. Referring toFIG. 11, data may be arranged (or written) in order of memory cells MC of the banks BK0, BK4, BK8, BK12, BK1, BK5, BK9, BK13, BK2, BK6, BK10, BK14, BK3, BK7, BK11, and BK15selected by word lines WL[0] and column selection lines CSL[0]. Next, data may be arranged (or written) in order of memory cells MC of the banks BK0, BK4, BK8, BK12, BK1, BK5, BK9, BK13, BK2, BK6, BK10, BK14, BK3, BK7, BK11, and BK15selected by word lines WL[0] and column selection lines CSL[1]. As the above procedure is repeated, data may be arranged in all the memory cells MC in the banks BK0to BK15.

The physical address PA having the stack identifier SID1may be converted into the memory address MA by the address mapping table AMT2. The address converter1120may select the address mapping table AMT2, and the PHY1130may access the PIM die2500through the channel CH1and may activate at least one of the banks BK0to BK15of the PIM die2500and at least one of the PE0to the PE7of the PIM die2500based on the memory address MA. According to the address mapping table AMT2, at least one (refer to BA0or BA1ofFIG. 3) of bits of the physical address PA, which correspond to the bank address BA0to BA3, corresponds to bits above bits of the physical address PA, which correspond to the column address Column. Referring toFIG. 12, data may be written or arranged in the memory cells MC of the bank BK0selected by the word line WL[0] and the column selection line CSL[0]. Next, data may be written or arranged in the memory cells MC of the bank BK0selected by the word line WL[0] and the column selection line CSL[1]. As the above procedure is repeated, data may be written or arranged in the memory cells MC of the bank BK0selected by the word line WL[0]. As in the case where data are arranged in order of memory cells MC of the bank BK0selected by the word line WL[0] and column selection lines CSL[0:3], data may be arranged in order of the memory cells MC of the banks BK4, BK8, BK12, BK2, BK6, BK10, BK14, BK1, BK3, BK5, BK7, BK9, BK11, BK13, and BK15selected by word lines WL[0] and the column selection lines CSL[0:3]. After data are arranged in the memory cells MC of all the banks BK0to BK15selected by the word line WL[0], as in the above description, data may be are arranged in the memory cells MC of all the banks BK0to BK15selected by word lines WL[1:3]. Unlike the data arrangement according to the address mapping table AMT1ofFIG. 11, in the case of the data arrangement according to the address mapping table AMT2ofFIG. 12, after data are completely arranged in the memory cells MC selected by one word line WL[0], the arrangement of data in the memory cells MC selected by the word lines WL[1:3] may be initiated.

FIG. 13illustrates an example of calculations executed by PEs according to data arrangement ofFIG. 12. For example, vector A may be arranged in the banks BK0, BK4, BK8, BK12, BK2, BK6, BK10, and BK14corresponding to the top bank T_BK, and vector B may be arranged in the banks BK1, BK5, BK9, BK13, BK3, BK7, BK11, and BK15corresponding to the bottom bank B_BK. The PE0to the PE7may generate vector C by executing addition on vector A arranged in the banks BK0, BK4, BK8, BK12, BK2, BK6, BK10, and BK14corresponding to the top bank T_BK and vector B arranged in the banks BK1, BK5, BK9, BK13, BK3, BK7, BK11, and BK15corresponding to the bottom bank B_BK. Any other calculations may be executed instead of the addition. Vector C may be stored in the registers REG of the PE0to the PE7. Referring toFIG. 13, because each of the PE0to the PE7is shared by two banks, in that the PE0to the PE7execute calculations, a way to arrange data in all the memory cells MC selected by one word line depending on the address mapping table AMT2may be more advantageous than a way to arrange data in the memory cells MC depending on the address mapping table AMT1. For example, the memory controller1100may apply the address mapping table AMT1to the PIM die2100and the address mapping table AMT2to the PIM die2500, independently of each other. Accordingly, in the case where the processor1200executes PIM calculations by using the PE0to the PE7of the PIM die2500, the memory controller1100may apply the address mapping table AMT1to the PIM die2100and the address mapping table AMT2to the PIM die2500independently of each other, instead of applying the address mapping table AMT2to the PIM dies2100and2500in common, thus preventing the reduction in performance of a normal operation of the processor1200, which is executed by using the PIM die2100in which the PE0to the PE7are not activated. The normal operation may include data input/output operations of the PIM die2100according to a read command or a write command without the execution of the PE0to the PE7. Also, because the memory controller1100supports the different address mapping tables AMT1and AMT2, the overhead that a program executable by the processor1200rearrange data in the case of executing a PIM calculation using the PE0to the PE7of the PIM die2500may be reduced, and parallelizing of a bank level may be utilized in the normal operation.

FIG. 14illustrates an example in which a processor ofFIG. 5accesses a memory controller and a memory controller accesses a memory device. For example, the processor1200may access the memory controller1100in a memory mapped I/O (MMIO) manner. A system address space (or area) may include a space allocated to the memory controller1100. According to an example embodiment, the system address space may further include spaces (or areas) respectively allocated to any other components (e.g., the on-chip memory1300, intellectual property (IP) blocks, and controllers) in the system on chip1000. The processor1200may access and control the memory controller1100and any other components in the system on chip1000by using the same system address space. The processor1200may access a space allocated to the memory controller1100from among the system address space and may write a value in the space allocated to the memory controller1100by using a write instruction. The memory controller1100may respond to the value and, for example, may receive a memory request of the processor1200. The memory controller1100may ignore a value written in the remaining space other than the space allocated to the memory controller1100from among the system address space.

The space allocated to the memory controller1100from among the system address space may be a physical address space, may correspond to the physical address space, or may be mapped onto the physical address space. The physical address space may correspond to a range of the physical addresses PA associated with a memory request. The physical address space may include a space allocated to the control register1141and a space allocated to the memory device2000. The space allocated to the memory controller1100from among the system address space may include a space corresponding to the space allocated to the control register1141from among the physical address space, and the processor1200may change a value (or information) of the control register1141by accessing the space corresponding to the space allocated to the control register1141. As in the above description, the space allocated to the memory controller1100from among the system address space may include a space corresponding to the space allocated to the memory device2000from among the physical address space, and the processor1200may access the memory device2000by accessing the space corresponding to the space allocated to the memory device2000.

The memory controller1100may also access the memory device2000in the MMIO manner. The physical address space may include the space allocated to the memory device2000. The memory controller1100may access the space allocated to the memory device2000from among the physical address space and may convert the physical address PA of the space allocated to the memory device2000from among the physical address space into the memory address MA.

The space allocated to the memory device2000from among the physical address space may be a memory address space, may correspond to the memory address space, or may be mapped onto the memory address space. The memory address space may correspond to a range of the memory addresses MA. The memory address space may include a space allocated to control registers of the PE controllers PECTRL0and PECTRL1and a space allocated to memory cells. The space allocated to the memory device2000from among the physical address space may include a space corresponding to the space allocated to the control registers of the PE controllers PECTRL0and PECTRL1from among the memory address space, and the memory controller1100may change a value (or information) of the control registers of the PE controllers PECTRL0and PECTRL1by accessing the space corresponding to the space allocated to the control registers of the PE controllers PECTRL0and PECTRL1. As in the above description, the space allocated to the memory device2000from among the physical address space may include a space corresponding to the space allocated to the memory cells from among the memory address space, and the memory controller1100may access the memory cells by accessing the space corresponding to the space allocated to the memory cells. Memory cells of each of the banks BK0to BK15of each of the PIM dies2100to2800of the memory device2000and the control registers of the PE controllers PECTRL0and PECTRL1all may be mapped onto a memory address associated with each of the PIM dies2100to2800of the memory device2000.

FIG. 15illustrates an electronic device100caccording to another embodiment of the inventive concept. The electronic device100cmay include the system on chip1000, memory devices2000_1to2000_4, the interposer3000, and a package board4000. Each of the memory devices2000_1to2000_4may correspond to the memory device2000described above, and the number of memory devices2000_1to2000_4is not limited to the example illustrated inFIG. 15. The interposer3000may include paths of a plurality of channels that allow the system on chip1000to access the memory devices2000_1to2000_4. For example, the interposer3000may be stacked on the package board4000. For another example, the system on chip1000and the memory devices2000_1to2000_4may be stacked on the package board4000without the interposer3000.

A memory controller according to an embodiment of the inventive concept may simultaneously support a plurality of address mapping tables for converting a physical address into a memory address. The memory controller may dynamically select the plurality of address mapping tables depending on whether to execute a PE of a PIM die and may optimally arrange data to be appropriate for the execution of the PE.