Routing structure and method of forming the same

The present disclosure provides a routing structure. The routing structure includes a substrate having a first circuit region and a boundary surrounding the first circuit region. The routing structure also includes a first conductive trace coupled to a first conductive pad disposed in the first circuit region. The first conductive trace is inclined with respect to the boundary of the substrate. A method of forming a routing structure is also disclosed.

BACKGROUND

A routing structure may include a plurality of substrate layers, and the substrate layers may have one or more conductive traces disposed thereon and running between terminals of electronic components coupled to the routing structure.

DETAILED DESCRIPTION

Embodiments, or examples, illustrated in the drawings are disclosed below using specific language. It will nevertheless be understood that the embodiments and examples are not intended to be limiting. Any alterations or modifications in the disclosed embodiments, and any further applications of the principles disclosed in this document are contemplated as would normally occur to one of ordinary skill in the pertinent art.

Further, it is understood that several processing steps and/or features of a device may be only briefly described. Also, additional processing steps and/or features can be added, and certain of the following processing steps and/or features can be removed or changed while still implementing the claims. Thus, the following descriptions should be understood to represent examples only, and are not intended to suggest that one or more steps or features are required.

Referring toFIG.1,FIG.1illustrates an exploded perspective view of a routing structure1in accordance with some embodiments of the present disclosure.

The routing structure1includes substrate layers (abbreviated to “substrate” in the other portions of the present disclosure)10and11, conductive traces12and13, and electronic components14aand14b.

In some embodiments, the routing structure1may be included in or applicable to a printed circuit board (PCB), an integrated circuit (IC), a field-programmable gate array (FPGA), a combination thereof, or other semiconductor device packages.

For the purpose of simplicity and clarity, an interconnection structure (such as a redistribution layer (RDL), a through via), a grounding element, and/or a power element may be omitted inFIG.1. For example, the routing structure1may further include an interconnection structure, a grounding element and/or a power element.

In some embodiments, the routing structure1may be a hierarchical routing structure, and the substrate10and the substrate11may be bonded or stacked together as indicated by the dotted arrows. In some embodiments, the number of the substrate in the routing structure1can be adjusted according to design requirements and is not limited to the specific examples in the disclosure. For example, the routing structure1may include N layers of the substrates, and N may be an integer greater than 0.

In some embodiments, the substrate10may be the topmost layer in the routing structure1. In some embodiments, the substrate10may have an active surface configured to receive the electronic components14aand14b. The electronic components14aand14bmay be received on the active surface (not labelled in the figures) of the substrate10.

In some embodiments, the routing structure1may only include the topmost layer (i.e., the substrate10). For example, the other layer (i.e., the substrate11) may be omitted in the routing structure1.

In some embodiments, each of the substrate10and the substrate11may be (or may include), for example, a printed circuit board substrate, such as a paper-based copper clad laminate, a composite copper clad laminate, or a polymer-impregnated glass-fiber-based copper clad laminate. In some embodiments, each of the substrate1and the substrate2may include a silicon substrate, a silicon-germanium substrate, or another semiconductor substrate. Other substances, such as glass, multi-layered or gradient substrates may also be used.

The substrate10includes sides10b1,10b2,10b3, and10b4. The side10b1is connected between the side10b2and the side10b4. The side10b2is connected between the side10b1and the side10b3. The side10b3is connected between the side10b2and the side10b4. The side10b4is connected between the side10b1and the side10b3.

The side10b1is adjacent to the side10b2and the side10b4. The side10b2is adjacent to the side10b1and the side10b3. The side10b3is adjacent to the side10b2and the side10b4. The side10b4is adjacent to the side10b1and the side10b3.

In some embodiments, the sides10b1,10b2,10b3, and10b4may be the outermost sides of the substrate10. For example, sides10b1,10b2,10b3, and10b4may together form a boundary (or a border, or an edge) of the substrate10. The sides10b1,10b2,10b3, and10b4may be collectively referred to as a boundary10bin the other portions of the present disclosure. In other embodiments, the substrate10as shown inFIG.1is a portion of an entire substrate, and the sides10b1,10b2,10b3, and10b4define the boundary10bof a portion of the entire substrate.

Two adjacent sides may define a corner (not labeled in the figures) of the substrate10. For example, there are four corners defined by the sides10b1,10b2,10b3, and10b4of the substrate10. In some embodiments, the boundary10bof the substrate10may be a rectangle, and thus, each of the corners may have a right angle. In other words, two of the adjacent sides (such as the side10b1and the side10b2) may be orthogonal (or perpendicular) to each other.

As can be seen fromFIG.1, several tracks and two circuit regions10aand10bdepicted in dotted lines are on the active surface of the substrate10.

In some embodiments, the tracks may be routes (or paths) defined (or set, or predetermined) to run conductive traces (such as the conductive trace12). In some embodiments, the circuit regions10aand10bmay be regions (or locations) defined (or set, or predetermined) to receive electronic components (such as the electronic components14aand14b). For example, the electronic components14aand14bmay be connected to or bonded to the circuit regions10aand10b, respectively, of the substrate10.

For example, one or more of the tracks may run over conductive pads10p1and10p2in proximity to, adjacent to, or embedded in and exposed at the active surface of the substrate10. For example, the conductive trace12may be disposed on a track run over the conductive pads10p1and10p2, and may be coupled to electrically connected to) the conductive pads10p1and10p2.

The tracks are depicted in dotted lines since the conductive traces may not be formed thereon in the illustrated example ofFIG.1. In some embodiments, the tracks depicted in dotted lines may not be visible in the final product.

In some embodiments, the conductive trace12is inclined (or oblique, or slanted) with respect to the boundary10bof the substrate10. For example, the conductive trace12may have a sloping direction (or angle, or position) with respect to the boundary10bof the substrate10. For example, the conductive trace12may be non-perpendicular to the boundary10bof the substrate10. For example, the conductive trace12may be non-parallel to the boundary10bof the substrate10. For example, the conductive trace12and the boundary10bof the substrate10(e.g., the side10b4) may define an acute angle (annotated as “θ0”).

The substrate11may have a similar structure or layout as the substrate10. For example, the substrate11may include four sides, which together form a boundary (or a border, or an edge) of the substrate11.

Similar to substrate10, several tracks depicted in dotted lines are defined on the substrate11. The substrate11may have a wiring layout different from the substrate10. For example, the tracks on the substrate11may be nonparallel to the tracks on the substrate10. For example, the tracks on the substrate11may be not aligned with the tracks on the substrate10. For example, the tracks on the substrate11and the tracks on the substrate10may be not overlapped from a top view. For example, the tracks on the substrate11and the boundary of the substrate11may define an acute angle, which may be different from the angle θ0.

The conductive trace13on the substrate11may run over conductive pads (not illustrated inFIG.1) in proximity to, adjacent to, or embedded in and exposed at a surface of the substrate11. The conductive trace13on the substrate11may couple to the conductive trace12on the substrate10through a through via (not illustrated inFIG.1).

In some embodiments, the electronic components14aand14bmay be bonded on the substrate10and coupled to the substrate10through the conductive pads10p1and10p2, respectively. In some embodiments, the electronic components14aand14bmay be coupled to each other through the conductive trace12. Although the sides of the electronic components14aand14billustrated inFIG.1are aligned with the boundary10bof the substrate10, the electronic components14aand14bmay face toward any other direction. For example, the sides of the electronic components14aand14bmay be aligned with the conductive trace12.

The electronic components14aand14bdisposed on the active surface of the substrate10may be spaced apart from each other in an oblique direction with respect to the boundary10bof the substrate10. For example, the minimum clear spacing distance between the electronic components14aand14bmay be non-parallel (or non-perpendicular) to the boundary10bof the substrate10. For example, the minimum clear spacing distance between the electronic components14aand14bmay be inclined with respect to the boundary10bof the substrate10.

With the inclined tracks according to the present disclosure, the minimum clear spacing distance between the electronic components14aand14b(and also the conductive pads10p1and10p2) may be overlapped with (or aligned with, or in line with) the inclined tracks. In other words, the conductive trace12may be the shortest routing distance between the electronic components14aand14b(and also the conductive pads10p1and10p2).

In some embodiments, each of the electronic components14aand14bmay be a chip or a die including therein a semiconductor substrate, one or more integrated circuit devices and one or more overlying interconnection structures. The integrated circuit devices may include active devices such as transistors and/or passive devices such resistors, capacitors, inductors, or a combination thereof.

In some comparative approaches, unlike the inclined tracks as shown inFIG.1of the present disclosure, orthogonal tracks (such as tracks parallel or perpendicular to the boundary of the substrate) may be defined to route the conductive traces running between the terminals of the electronic components. Consequently, the conductive traces can only run in the orthogonal directions parallel (or perpendicular) to the boundary of the substrate. As a result, if the electronic components are spaced apart from each other in an oblique direction, the distance of the conductive traces running between terminals of the electronic components may not be reduced, and routing congestion may occur.

In accordance with the embodiments as shown inFIG.1, the tracks may be inclined (or oblique, or slanted) with respect to the boundary of the substrate. Therefore, the routing direction of the tracks may be defined more flexibly, and the conductive traces with a different sloping direction (or angle, or position) may be formed as desired.

As a result, with the inclined tracks, the minimum distance of conductive traces running between terminals of electronic components can be achieved. In addition, since the lines of conductive material can be shorter, the parasitic capacitance may be reduced, and the signal transmission may be facilitated.

In some embodiments, various operations can be performed to form tracks and conductive traces inclined with respect to the boundary of the substrate.

For example, a layout process of a routing structure usually includes the following operations: specifying where to place all electronic components in a substrate layer (i.e., specifying a wiring area); identifying how the connection between every electronic components will be routed (i.e., creating one or more tracks for conductive traces); arranging a power line and/or a ground line, if any; placing the electronic components in the wiring area; synthesizing a clock tree, if any; and creating conductive traces on the one or more of the tracks accordingly.

The track creation operations will be described below with respect toFIG.2A,FIG.2B,FIG.2C,FIG.2D, andFIG.2E.

FIG.2A,FIG.2B,FIG.2C,FIG.2D, andFIG.2Eare top views of a part of a routing structure1in accordance with some embodiments of the present disclosure.

Referring toFIG.2A, the entire active surface of the substrate10is defined as the wiring area. For example, in the illustrated example inFIG.1, the wiring area encompasses the entire active surface of the substrate10such that the sides of the wiring area overlap with the sides10b1,10b2,10b3, and10b4of the substrate10. For example, the sides10b1,10b2,10b3, and10b4(i.e., the outmost boundary of the substrate10) are the outmost boundary of the wiring area.

In the embodiments wherein the entire active surface of the substrate is defined as the wiring area, the track and the conductive trace may intersect with the outmost boundary of the substrate. For example, the conductive trace12as shown inFIG.1intersects with two adjacent sides10b3and10b4of the substrate10. For example, the tracks inFIG.2Aintersect with the sides10b1,10b2,10b3, and10b4.

In some other embodiments, the wiring area may be inside of the outmost boundary or may be smaller than the active surface of the substrate (such as the wiring areas41a,42a, and43aas illustrated inFIG.4).

Subsequently, a reference point (or an origin of coordinates) is defined at a corner of the wiring area. InFIG.2A, the reference point (which is annotated as (X0, Y0)) is defined at the corner between two adjacent sides10b1and10b2of the substrate10.

Since the tracks are set to be inclined in a direction from the left upper corner to the right lower corner, the reference point may be defined at the left lower corner as illustrated inFIG.2A. In some embodiments, the reference point may be defined at the right upper corner as illustrated inFIG.2B.

Next, a distance and an angle for setting the first track may be determined. InFIG.2A, a distance (which is annotated as “offset”) and an angle (which is annotated as “θ0”) are determined for the track10t1.

The distance “offset” may also be referred to as the offset. The offset may be the minimum distance between the reference point (X0, Y0) and the track10t1. In some embodiments, the offset may range from about 0.1 (μm) to about 10.0 μm. In some embodiments, the offset may be adjusted according to the routing requirements. In some embodiments, the angle θ0may be an acute angle, which is smaller than 90 degrees, such as 45 degrees.

Then, a distance for setting the second track may be determined. InFIG.2A, a distance (which is annotated as “pitch”) is determined for the track10t2.

The distance “pitch” may also be referred to as the pitch. The pitch may be the minimum distance between the track10t2and the track10a. In some embodiments, the pitch may be different from the offset. In some embodiments, the pitch may be the same as the offset.

In some embodiments, the track10t2and the track10t1are parallel to each other. In some embodiments, the other tracks are equally spaced. In some embodiments, the pitch may be the minimum distance between the other adjacent tracks (such as the tracks10t3and10t4).

In some embodiments, each of the tracks may intersect with two adjacent sides of the substrate10. For example, the track10t2intersects with the sides10b1and10b2of the substrate10.

In some embodiments, one of the tracks may be a diagonal line of the wiring area. For example, in some embodiments, the track10t3may connected to the left upper corner defined by sides10b1and10b4and the right lower corner defined by sides10b2and10b3.

In some embodiments, one or more of the tracks may run through circuit regions which are predetermined to receive or bond to electronic components. For example, in some embodiments, the track10t4may run through the circuit regions10aand10b, which are predetermined to receive or bond to the electronic components14aand14bas shown inFIG.1.

In some embodiments, the order of the operations described above may be adjusted according to design requirements and/or manufacturing conditions. For example, the offset and the pitch can be determined in the same step. For example, the pitch can be determined before the offset.

After setting the tracks, conductive traces may be disposed on one or more of the tracks, and electronic components may be disposed on the predetermined circuit regions. The final structure through the track creation operations described with respect toFIG.2Amay be similar to the substrate10inFIG.1.

Referring toFIG.2B, the track creation operations for the substrate10inFIG.2Bmay be similar to the track creation operations for the substrate10inFIG.2A, and the differences therebetween are described below.

After defining the wiring area, the reference point (X0, Y0) inFIG.2Bis defined at the right upper corner between the sides10b3and10b4of the substrate10.

Then, a distance and an angle for setting the first track may be determined. The first track10t1inFIG.2Bis adjacent to the right upper corner. The first track10t1intersects with the sides10b3and10b4of the substrate10.

The final structure through the track creation operations described with respect toFIG.2Bmay be similar to the substrate10inFIG.1.

Referring toFIG.2C, the track creation operations for the substrate10inFIG.2Cmay be similar to the track creation operations for the substrate10inFIG.2A, and the differences therebetween are described below.

After defining the wiring area, the reference point (X0, Y0) is defined at the left lower corner between the sides10b1and10b2of the substrate10.

Next, distances for setting the first track may be determined. InFIG.2C, distances (which are annotated as “offset_x” and “offset_y”) are determined for the track10t1.

The distance “offset_x” and the distance “offset_y” may also be referred to as the offset_x and the offset_y.

The offset_x may be the minimum distance between the reference point (X0, Y0) and the intersection of the track10t1and the side10b2. The offset_y may be the minimum distance between the reference point (X0, Y0) and the intersection of the track10t1and the side10b1. In some embodiments, the offset_x and the offset_y may be perpendicular to each other.

Then, distances for setting the second track may be determined. InFIG.2C, distances (which are annotated as “pitch_x” and “pitch_y”) are determined for the track10t2.

The distance “pitch_x” and the distance “pitch_y” may also be referred to as the pitch_x and the pitch_y.

In some embodiments, the pitch_x may be the minimum distance between the10t1and the track10t2in the direction parallel to the side10b2. In some embodiments, the pitch_y may be the minimum distance between the10t1and the track10t2in the direction parallel to the side10b1. In some embodiments, the pitch_x and the pitch_y may be perpendicular to each other.

In some embodiments, the track10t2and the track10t1are parallel to each other. In some embodiments, the other tracks are equally spaced.

In some embodiments, each of the tracks may intersect with two adjacent sides of the substrate10. For example, the track10t2intersects with the sides10b1and10b2of the substrate10.

In some embodiments, the track10t3may be connected to the left upper corner defined by sides10b1and10b4and the right lower corner defined by sides10b2and10b3.

In some embodiments, the track10t4may run through the circuit regions10aand10b, which are predetermined to receive or bond to electronic components.

In some embodiments, the order of the operations described above may be adjusted according to design requirements and/or manufacturing conditions. For example, the offset (the offset_x and the offset_y) and the pitch (the pitch_x and the pitch_y) can be determined in the same step. For example, the pitch can be determined before the offset.

After setting the tracks, conductive traces may be disposed on one or more of the tracks, and electronic components may be disposed on the circuit regions. The final structure through the track creation operations described with respect toFIG.2Cmay be similar to the substrate10inFIG.1.

In some embodiments, the first track may be set by determining an angle (such as the angle θ0inFIG.2A) and an intersection with a side (such as the offset_x or the offset_y inFIG.2C).

Referring toFIG.2DandFIG.2E, the track creation operations described with respect toFIG.2DandFIG.2Emay be similar to the track creation operations described with respect toFIG.2A, and the differences therebetween are described below.

Since the tracks are set to be inclined in a direction from the right upper corner to the left lower corner, the reference point is defined at the right lower corner as illustrated inFIG.2D. In some embodiments, the reference point may be defined at the left upper corner as illustrated inFIG.2E.

After setting the tracks, conductive traces may be disposed on one or more of the tracks. The final structure through the track creation operations described with respect toFIG.2DandFIG.2Emay be similar to the substrate11inFIG.1.

FIG.3illustrates an exploded perspective view of a routing structure3in accordance with some embodiments of the present disclosure. The routing structure3inFIG.3is similar to the routing structure1inFIG.1, and the differences therebetween are described below.

The routing structure3includes a substrate30. Several tracks depicted in dotted lines are defined on a surface of the substrate30. In some embodiments, the tracks are parallel (or perpendicular) to the boundary of the substrate30. For example, the conductive trace31and the boundary of the substrate30may define a right angle (annotated as “θ1”).

The conductive trace31and the conductive trace12are disposed on different substrate layers in the routing structure3. The conductive trace12is inclined with respect to the boundary10bof the substrate10. The conductive trace31is parallel (or perpendicular) to the boundary of the substrate30.

FIG.4illustrates an exploded perspective view of a routing structure4in accordance with some embodiments of the present disclosure. The routing structure4inFIG.4is similar to the routing structure1inFIG.1, and the differences therebetween are described below.

The routing structure4includes a substrate40. The wiring areas41a,42a, and43aare defined inside of the outmost boundary of the substrate40. In other words, each of the wiring areas41a,42a, and43ais smaller than the active surface of the substrate40.

The wiring area41aencompasses the side40b3and the side40b4of the substrate40. A corner of the wiring area41ais overlapped with the corner defined by the side40b3and the side40b4of the substrate40. The wiring area42aencompasses the side40b4of the substrate40. The wiring area43aencompasses the side40b1and the side40b4of the substrate40. A corner of the wiring area43ais overlapped with the corner defined by the side40b1and the side40b1of the substrate40.

The numbers and the locations of the wiring areas in the substrate40may be adjusted according to the design requirements. For example, there may be any numbers of wiring areas defined on the same layer of the substrate40. For example, the wiring areas (such as the wiring areas41a,42a, and43a) may be arranged at any location on the substrate40.

In some embodiments, each of the wiring areas41a,42a, and43adefined by imaginary dash-dot lines may possess a different wiring layout from the other ones. For example, conductive traces on the same layer of the substrate40may have different sloping directions (or angles, or positions with respect to the boundary of the substrate40.

For example, the conductive trace41in the wiring area41ais not parallel to the conductive trace42in the wiring area42a. For example, the conductive trace41in the wiring area41ais not parallel to the conductive trace43in the wiring area43a.

For example, the conductive trace42in the wiring area42ais parallel to the side40b1and the side40b3of the substrate40. The conductive trace42in the wiring area42ais non-parallel to the conductive trace41and the conductive trace43.

For example, a prolongation of the conductive trace41define an acute angle θ2with the side40b4of the substrate40. The conductive trace43and the side40b4of the substrate40define an acute angle θ3different from the acute angle θ2.

For example, a prolongation of the conductive trace41intersects with the side403and the side404of the substrate40. The conductive trace43intersects with the side40b1and the side40b3of the substrate40.

In some embodiments, each of the wiring areas41a,42a, and43amay have their own circuit regions (not shown inFIG.4) configured to receive or bond to electronic components.

Similarly, more than one wiring areas may be defined on the other substrate layer (such as the substrate11inFIG.1).

FIG.5illustrates a top view of a substrate50of a routing structure in accordance with some embodiments of the present disclosure. The part of the substrate50inFIG.5is similar to the substrate10illustrated inFIG.1, and the differences therebetween are described below.

The substrate50includes sides50b1,50b2,50b3, and50b4. Wiring areas51aand52aare defined on the substrate50.

The wiring area51ais surrounded by the sides50b1,50b2,50b3, and50b4.

Two sides of the wiring area51aencompass the side50b1and the side50b2of the substrate50. Another side of the wiring area51aintersects with the side50b1and the side50b2of the substrate50. From a top view, the wiring area51amay be a right triangle.

The wiring area52amay have a missing corner. Two sides of the wiring area52aencompasses the side50b2and the side50b3of the substrate50. A corner of the wiring area52aoverlaps with the corner defined by the side50b2and the side50b3of the substrate50.

In some embodiments, the shape of the wiring area may be defined according to design requirements, and is not limited in the specific examples illustrated in the figures. For example, the wiring area may be a triangle, a square, a pentagon, a circle, an oval, or any shape.

Some embodiments of the present disclosure provide a routing structure. The routing structure includes a substrate having a first circuit region and a boundary surrounding the first circuit region. The routing structure also includes a first conductive trace coupled to a first conductive pad disposed in the first circuit region. The first conductive trace is inclined with respect to the boundary of the substrate.

Some embodiments of the present disclosure provide a method of forming a routing structure. The method includes providing a substrate having a boundary and setting a first track for forming a conductive trace on the substrate. The first track is inclined with respect to the boundary of the substrate.

Some embodiments of the present disclosure provide a method of forming a routing structure. The method includes providing a substrate having a boundary and determining a reference point for setting a first track of a conductive trace on the substrate. The reference point is defined at a corner between two adjacent sides of the boundary of the substrate.

The methods and features of the present disclosure have been sufficiently described in the above examples and descriptions. It should be understood that any modifications or changes without departing from the spirit of the present disclosure are intended to be covered in the protection scope of the present disclosure.

Moreover, the scope of the present application in not intended to be limited to the particular embodiments of the process, machine, manufacture, and composition of matter, means, methods and steps described in the specification. As those skilled in the art will readily appreciate from the present disclosure, processes, machines, manufacture, composition of matter, means, methods or steps presently existing or later to be developed, that perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein, may be utilized according to the present disclosure.

Accordingly, the appended claims are intended to include within their scope: processes, machines, manufacture, compositions of matter, means, methods or steps. In addition, each claim constitutes a separate embodiment, and the combination of various claims and embodiments are within the scope of the present disclosure.