Semiconductor integrated circuit device and method of fabricating the same

A semiconductor integrated circuit device and method of fabricating a semiconductor integrated circuit device, the method including preparing a first conductivity type substrate including a first conductivity type impurity such that the first conductivity type substrate has a first impurity concentration; forming a buried impurity layer using blank implant such that the buried impurity layer includes a first conductivity type impurity and has a second impurity concentration higher than the first impurity concentration; forming an epitaxial layer on the substrate having the buried impurity layer thereon; and forming semiconductor devices and a device isolation region in or on the epitaxial layer.

BACKGROUND

Embodiments relate to a semiconductor integrated circuit device and a method of fabricating the same.

2. Description of the Related Art

Semiconductor integrated circuit devices, e.g., a system-on-chip (SOC), a microcontroller unit (MCU), and a display driver IC (DDI), may include a plurality of peripheral devices, e.g., a processor, a memory, a logic circuit, an audio and image processing circuit, and various interface circuits. Thus, the semiconductor integrated circuit devices may include transistors having various driving voltages. For example, a high voltage driving transistor, an intermediate voltage driving transistor, and a low voltage driving transistor may be included in a semiconductor integrated circuit device.

SUMMARY

Embodiments are directed to a semiconductor integrated circuit device and a method of fabricating the same.

The embodiments may be realized by providing a method of fabricating a semiconductor integrated circuit device, the method including preparing a first conductivity type substrate including a first conductivity type impurity such that the first conductivity type substrate has a first impurity concentration; forming a buried impurity layer using blank implant such that the buried impurity layer includes a first conductivity type impurity and has a second impurity concentration higher than the first impurity concentration; forming an epitaxial layer on the substrate having the buried impurity layer thereon; and forming semiconductor devices and a device isolation region in or on the epitaxial layer.

The epitaxial layer may include a first conductivity type epitaxial layer having a third impurity concentration, and the first conductivity type may be a P-type.

The second impurity concentration may be higher than the third impurity concentration.

The first conductivity type impurity may include boron.

The epitaxial layer may include a second conductivity type epitaxial layer, the first conductivity type may be a P-type, and the second conductivity type may be an N-type.

The method may further include performing a drive-in diffusion process on the buried impurity layer.

The semiconductor device may include a high-voltage semiconductor device driven at about 30 to about 50 V and a low-voltage semiconductor device driven at about 1 to about 5 V, and the device isolation region may be formed between the high-voltage semiconductor device and the low-voltage semiconductor device.

The buried impurity layer may be formed on the substrate.

The embodiments may also be realized by providing a method of fabricating a semiconductor integrated circuit device, the method including preparing a first conductivity type substrate such that the first conductivity type substrate includes a high-voltage device region and a low-voltage device region; implanting a first conductivity type impurity into an entire surface of the substrate at a first dose; diffusing the first conductivity type impurity; forming an epitaxial layer on the first conductivity type impurity diffused substrate; and forming a high-voltage semiconductor device and a low-voltage semiconductor device in the high-voltage device region and the low-voltage device region, respectively.

The first dose may be about 1014atoms/cm2to about 1016atoms/cm2.

The high-voltage semiconductor device may include a high-voltage transistor driven at about 30 to about 50 V, and the low-voltage semiconductor device may include a low-voltage transistor driven at about 1 to about 5 V.

The transistors may include lateral double-diffused metal oxide semiconductor (DMOS) transistors.

The epitaxial layer may include a first conductivity type epitaxial layer, and the first conductivity type may be a P-type.

The first conductivity type impurity may include boron.

The epitaxial layer may include a second conductivity type epitaxial layer, the first conductivity type may be a P-type, and the second conductivity type may be an N-type.

The embodiments may also be realized by providing a semiconductor integrated circuit device including a first conductivity type substrate having a first impurity concentration, the substrate having a high-voltage device region and a low-voltage device region defined therein; a buried impurity layer on an entire surface of the substrate, the buried impurity layer including a first conductivity type impurity and having a second impurity concentration higher than the first impurity concentration, and being formed using blank implant; an epitaxial layer on the buried impurity layer; and high-voltage semiconductor devices and low-voltage semiconductor devices respectively formed in the high-voltage device region and the low-voltage device region formed in or on the epitaxial layer.

The epitaxial layer may include a first conductivity type epitaxial layer having a third impurity concentration, the first conductivity type may be a P-type, and the first conductivity type impurity may include boron.

The second impurity concentration may be higher than the third impurity concentration.

The epitaxial layer may include a second conductivity type epitaxial layer, the first conductivity type may be a P-type, and the second conductivity type may be an N-type.

The high-voltage semiconductor device may include a high-voltage lateral double-diffused metal oxide semiconductor (DMOS) transistor driven at about 30 to about 50 V, and the low-voltage semiconductor device may include a low-voltage lateral double-diffused metal oxide semiconductor (DMOS) transistor driven at about 1 to about 5 V.

DETAILED DESCRIPTION

Korean Patent Application No. 10-2010-0031864, filed on Apr. 7, 2010, in the Korean Intellectual Property Office, and entitled: “Semiconductor Integrated Circuit Device and Fabricating Method of the Same,” is incorporated by reference herein in its entirety.

Hereinafter, a method of fabricating a semiconductor integrated circuit device according to an embodiment will be described with reference toFIGS. 1 through 6.

FIG. 1illustrates a flowchart of a method of fabricating a semiconductor integrated circuit device according to an embodiment.FIGS. 2 through 6illustrate cross-sectional views of stages in the method of fabricating a semiconductor integrated circuit device ofFIG. 1.

WhileFIG. 1illustrates a particular device by way of example to describe the semiconductor integrated circuit device according to an embodiment, the embodiments are not limited thereto; and the embodiments may also be applied to a semiconductor integrated circuit device, e.g., a system-on-chip (SOC) or a microcontroller unit (MCU).

Referring first toFIG. 1, a first conductivity type substrate having a first impurity concentration may be prepared. Then, a buried impurity layer including a first conductivity type impurity, as indicated by reference symbol “PBL” inFIG. 1, having a second impurity concentration higher than the first impurity concentration may be formed using blank implant (S100).

For example, referring toFIG. 2, a high-voltage device region HV_REGION and a low-voltage device region LV_REGION may be defined in the substrate110. In an implementation, the high-voltage device region HV_REGION may include, e.g., a high-voltage digital circuit; and the low-voltage device region LV_REGION may include, e.g., a low-voltage digital circuit and/or an analog circuit. For example, the high-voltage device region HV_REGION may be a potential high-voltage transistor region driven at about 30 to about 50 V (see HP or HN shown inFIG. 6), while the low-voltage device region LV_REGION may be a potential low-voltage transistor region driven at about 1 to about 5 V (see LP or LN shown inFIG. 6). In an implementation, the high-voltage device region HV_REGION and the low-voltage device region LV_REGION may be lateral double-diffused metal oxide semiconductor (DMOS) transistors, but the embodiments are not limited thereto.

Although not shown inFIG. 2, in an implementation, the substrate110may have an intermediate-voltage device region (not shown) further defined therein. For example, the high-voltage device region HV_REGION may be a potential high-voltage transistor region driven at about 30 to about 50 V (see HP or HN shown inFIG. 6), the intermediate-voltage device region (not shown) may be a potential intermediate-voltage transistor region driven at about 5 to about 10 V, and the low-voltage device region LV_REGION may be a potential high-voltage transistor region driven at about 1 to about 5 V (see LP or LN shown inFIG. 6). For example, the high-voltage device region HV_REGION, the intermediate-voltage device region and the low-voltage device region LV_REGION may be lateral double-diffused metal oxide semiconductor (DMOS) transistors, but the embodiments are not limited thereto.

The substrate110may be, e.g., a silicon substrate, a gallium arsenic substrate, a silicon germanium substrate, a ceramic substrate, a quartz substrate, a glass substrate for a display device, or a SOI (Silicon on Insulator) substrate.

Referring toFIG. 3, a first conductivity type impurity, e.g., P-type impurity, may be implanted at a first dose into an entire surface of the high-voltage device region HV_REGION and the low-voltage device region LV_REGION of the substrate110. The first conductivity type impurity (e.g., P-type, impurity) may be implanted into the substrate110without a separate mask, as shown inFIG. 3. The first conductivity type (e.g., P-type impurity) may include, e.g., boron (B); and the first dose may be, e.g., about 1014atoms/cm2to about 1016atoms/cm2.

Referring toFIG. 4, a buried impurity layer136including the first conductivity type impurity (e.g., P-type impurity such as boron) and having a second impurity concentration higher than the first impurity concentration, may be formed on the substrate110by the implantation, e.g., a blank implant. Here, the blank implant may refer to implantation of impurity on the entire surface of the substrate110without using a separate mask.

Referring toFIGS. 1 and 4, the buried impurity layer136formed on the substrate110may be subjected to a “drive-in” diffusion process (S110). For example, the first conductivity type impurity (e.g., P-type, impurity such as boron (B)) included in the buried impurity layer136may be diffused by thermal treatment. The occurrence of defects, e.g., a crack of a potential epitaxial layer (120aofFIG. 5), may be prevented through the above-described process. In addition, it is possible to prevent the first conductivity type impurity (e.g., P-type, impurity such as boron (B)) included in the buried impurity layer136from freely moving toward the epitaxial layer (120aofFIG. 5), which may be referred to as auto-doping.

Referring toFIGS. 1 and 5, a second conductivity type, e.g., N-type, epitaxial layer120ahaving a third impurity concentration (as indicated by reference symbol “N-EPI” inFIG. 1) may be formed on the substrate110having the buried impurity layer136(S120). In an implementation, the third impurity concentration may be smaller than the second impurity concentration of the buried impurity layer136. The epitaxial layer120amay be formed to a thickness such that Double Re-SURF (Double Reduced SURFace electric-field) performance of a the semiconductor integrated circuit device according to an embodiment may be sufficiently demonstrated.

Referring toFIGS. 1 and 6, semiconductor devices (e.g., a first high-voltage transistor HP, a second high-voltage transistor HP, a first low-voltage transistor LP, a second low-voltage transistor LN, etc.) may be formed in or on the epitaxial layer120a(S130). In the following description, a semiconductor device formed in or on the epitaxial layer120amay be described with reference toFIG. 6by way of example, but the embodiments are not limited thereto. Other types of semiconductor devices may also be formed in or on the epitaxial layer120a. For example, although the semiconductor device shown inFIG. 6may be fabricated by a shallow trench isolation (STI) process, a semiconductor device fabricated by a local oxidation (LOCOS) process may also be formed in or on the epitaxial layer120a.

Referring toFIG. 6, a first deep well141and a second deep well142of the second conductivity type, e.g., N-type, may be formed in the high-voltage device region HV_REGION. The first deep well141and the second deep well142may contact the buried impurity layer136, but the embodiments are not limited thereto.

A second conductivity type, e.g., N-type, third deep well144may be formed in the low-voltage device region LV_REGION. The third deep well144may also contact the buried impurity layer136, but the embodiments are not limited thereto. In an implementation, the third deep well144may electrically isolate the buried impurity layer136, a second conductivity type, e.g., N-type, first low-voltage well156including a first low-voltage transistor LP formed therein, and a first conductivity type, e.g., P-type, second low-voltage well164including a second low-voltage transistor LN formed therein, from one another.

A first conductivity type, e.g., P-type, first device isolation well146may be formed between the first high-voltage transistor HN and the second high-voltage transistor HP in the high-voltage device region HV_REGION. The first device isolation well146may contact the buried impurity layer136, but the embodiments are not limited thereto. The first device isolation well146may serve as a device isolation area that electrically isolates the first high-voltage transistor HN and the second high-voltage transistor HP in the high-voltage device region HV_REGION from each other.

A first conductivity type, e.g., P-type, second device isolation well148may be formed between the high-voltage device region HV_REGION and the low-voltage device region LV_REGION. The second device isolation well148may contact the buried impurity layer136, but the embodiments are not limited thereto. The second device isolation well148may serve as a device isolation area that electrically isolates the high-voltage device region HV_REGION and the low-voltage device region LV_REGION from each other.

A first conductivity type, e.g., P-type, first high-voltage well204and a second conductivity type, e.g., N-type, second high-voltage well206may be formed in the first deep well141in the high-voltage device region HV_REGION. A second conductivity type, e.g., N-type, third high-voltage well152and a first conductivity type, e.g., P-type, drift region176may be formed in the second deep well142in the high-voltage device region HV_REGION.

The second conductivity type, e.g., N-type, first low-voltage well156and the first conductivity type, e.g., P-type, second low-voltage well164may be formed in the third deep well144in the low-voltage device region LV_REGION.

A first conductivity type, e.g., P-type, fourth high-voltage well162may be formed in the first device isolation well146between the first high-voltage transistor HN and the second high-voltage transistor HP in the high-voltage device region HV_REGION.

In addition, as shown inFIG. 6, a plurality of trenches200that separate regions of the respective wells from one another may be formed on the substrate110. Further, a field oxide layer (not shown) that defines regions for a first high-voltage transistor HN, a second high-voltage transistor HP, a first low-voltage transistor LP, and a second low-voltage transistor LN may also be formed on the substrate110. As shown, a gate insulation layer and spacers may also be formed on the substrate110.

As described above, the first high-voltage transistor HN may be a high-voltage NLDMOS transistor driven at, e.g., about 30 to about 50 V, and may include a gate electrode203, a drain205, and a source201. In addition, as described above, the second high-voltage transistor HP may also be a high-voltage HLDMOS transistor driven at, e.g., about 30 to about 50 V, and may include a gate electrode172, a drain174, and a source175.

The drains205and174may be formed in the second high-voltage well206and the drift region176, respectively, and may have impurity concentrations higher than the second high-voltage well206and the drift region176. In an implementation, the drift region176may help ensure that a breakdown voltage (BV) for a high voltage is achieved. The sources201and175may be formed in the first high-voltage well201and the third high-voltage well152, respectively.

First and second ohmic contacts202and181may be portions to which driving voltages are applied. The first and second ohmic contacts202and181may be respectively formed in the first and third high-voltage wells204and152in contact with the sources201and175of the first and second high-voltage transistors HN and HP.

The first conductivity type, e.g., P-type, first low-voltage transistor LP may be a low-voltage transistor driven at, e.g., about 1 to about 5 V, and may include a gate electrode191, a source193, and a drain194. The source193and the drain194may be formed in the first low-voltage well156.

In addition, a third ohmic contact182may be a portion to which a power voltage is applied. The third ohmic contact182may be formed in the first low-voltage well156, like the source193and the drain194of the first low-voltage transistor LP. In an implementation, the power voltage may be, e.g., about 1 to about 5 V.

The second conductivity type second low-voltage transistor LN may include a gate electrode192, a drain196, and a source197. The drain196and the source197may be formed in the second low-voltage well164.

A fourth ohmic contact183may be coupled to a ground voltage and may be formed in the second low-voltage well164(like the drain196and the source197of the second low-voltage transistor LN). A fifth ohmic contact185may be coupled to a ground voltage and may be formed in a fourth high-voltage well162.

As described above, although not illustrated, an intermediate voltage device region may be further defined in the substrate110. Accordingly, an intermediate voltage transistor (not shown) driven at, e.g., about 1 to about 5 V, may be further formed in the intermediate voltage device region (not shown).

The gate electrodes203and172and the buried impurity layer136may reduce a surface electric-field. Having both the gate electrodes203and172and the buried impurity layer136reduce the surface electric-field may be referred to as a Double Re-SURF throughout the specification. During operation, the epitaxial layer (120aofFIG. 5) may be fully depleted; and the electric fields between the source201,175and the drain205,174may reach substantially the same level, thereby allowing the high-voltage transistors HN and HP to achieve a high breakdown voltage (BV). Hence, the semiconductor integrated circuit device according to an embodiment may have stable device characteristics.

Next, a fabricating method of a semiconductor integrated circuit device according to another embodiment will be described with reference toFIGS. 7 and 8. In the following description, repeated descriptions of the same or corresponding parts as those of the previous embodiment will be omitted and only differences therebetween will be described herein.

FIG. 7illustrates a flowchart of a method of fabricating a semiconductor integrated circuit device according to another embodiment.FIG. 8illustrates a cross-sectional view of a stage in the method of fabricating a semiconductor integrated circuit device ofFIG. 7.

Referring first toFIG. 7, a first conductivity type substrate having a first impurity concentration may be prepared. Then, a buried impurity layer136including a first conductivity type impurity having a second impurity concentration (higher than the first impurity concentration) may be formed using blank implant (S200). Then, the buried impurity layer136formed on the substrate110may be subjected to a “drive-in” diffusion process (S210).

Referring now toFIGS. 7 and 8, a first conductivity type, e.g., P-type, epitaxial layer120bhaving a third impurity concentration may be formed on the substrate110having the buried impurity layer136(S220). In an implementation, the third impurity concentration may be smaller than the impurity second concentration of the buried impurity layer136. The epitaxial layer120bmay be formed to a thickness such that Double Re-SURF (Double Reduced SURFace electric-field) performance of the semiconductor integrated circuit device according to an embodiment may be sufficiently demonstrated.

Next, referring toFIG. 7together withFIG. 6, semiconductor devices (e.g., a first high-voltage transistor HP, a second high-voltage transistor HP, a first low-voltage transistor LP, a second low-voltage transistor LN, etc.) may be formed in or on the epitaxial layer120b(S230). For example, the fabricating method of a semiconductor integrated circuit device according to the present embodiment may be substantially the same as the fabricating method according to the previous embodiment, except that the first conductivity type, e.g., P-type, epitaxial layer120bmay be formed on the buried impurity layer136.

Next, characteristics of the semiconductor integrated circuit device fabricated by the fabricating method according to an embodiment will be described with reference toFIGS. 9 and 10.

FIGS. 9 and 10illustrate characteristics of the semiconductor integrated circuit device fabricated by the method according to an embodiment. In particular,FIG. 9illustrates a graph showing impurity concentrations along the line A-A′ ofFIG. 6andFIG. 10illustrates a graph showing voltage-current characteristics depending impurity concentrations.

Referring first toFIG. 9, like the semiconductor integrated circuit devices fabricated by the method according to an embodiment, when a buried impurity layer136is formed by blank implant and subjected to a “drive-in” diffusion process (see the plot Q), it may be seen that the impurity concentration of the buried impurity layer136may be higher than that of the substrate110.

In an comparative example, unlike the semiconductor integrated circuit devices fabricated by the fabricating method according to an embodiment, a buried impurity layer may not be formed by blank implant (see the plots P-1, P-2, and P-3). For example, diffusion between the substrate110and the buried impurity layer136may form impurity concentration distributions. Thus, a difference in the impurity concentration between the substrate110and the buried impurity layer136may not be so great. Furthermore, it may be quite difficult to accurately control the impurity concentration distribution in cases represented by the plots P-1to P-3during fabricating semiconductor integrated circuit devices. In addition, if there are changes in the thicknesses of the epitaxial layers (120aofFIGS. 5 and 120bofFIG. 8), it may be more difficult to accurately control the impurity concentration distribution; and the Double Re-SURF performance of the semiconductor integrated circuit device may further degrade and breakdown voltages (BVs) of the semiconductor integrated circuit device may be reduced.

Changes in the BVs depending on the change in the impurity concentration distribution are shown inFIG. 10. As represented by the plots P-1and P-2(the plot P-3representing an ideal state resulting from diffusion), in the cases where accurately controlling the impurity concentration distribution between the substrate110and the buried impurity layer136is quite difficult (e.g., when it is not possible to know to which of the cases represented by the plots P-1, P-2, P-3a state of the semiconductor integrated circuit device manufactured is applied), it is understood that the BV of the semiconductor integrated circuit device may be reduced.

In the semiconductor integrated circuit devices according to an embodiment (see the plot Q), the impurity concentrations of the buried impurity layer136and the substrate110may be accurately controlled using an implantation process, without using a diffusion process. Hence, stable Double Re-SURF performance of the semiconductor integrated circuit device may be realized. Therefore, current characteristics of the semiconductor integrated circuit device may be achieved in a stable manner.

Accordingly, the embodiments provide a method of fabricating a semiconductor integrated circuit device having an improved current characteristic of a semiconductor device.