Method of determining a syschronous signal pattern and method of and device for recording the synchronous signal pattern on a medium

Disclosed are methods of determining and recording a synchronous signal pattern on a medium and also an information recording/reproducing device thereof. The method of determining an optimum synchronous signal pattern includes detecting correlation properties of a VFO pattern and a synchronous signal pattern with a matching filter by inputting the respective samples of the patterns to the matching filter; and determining the sample exhibiting an excellent correlation property as the synchronous signal pattern among the samples. The information recording method includes forming information by sequencing the VFO pattern, the determined synchronous signal pattern and (2, 7)-modulated data; and recording the information on a recording medium. The information recording/reproducing device includes a device for recording, on a recording medium, the information configured by sequencing the VFO pattern, the synchronous signal pattern for identifying the head of information and (2, 7)-modulated data; and a device for reproducing the information. The VFO pattern consists of a repetitive pattern of "0000" or "100" or "010", and the synchronous signal pattern is a binary signal pattern.

BACKGROUND OF THE INVENTION 
1. Field of the Invention 
The present invention relates a method of determining a synchronous signal 
pattern in a format of information to be recorded on a medium in an 
information recording apparatus such as, e.g., an optical disk memory or 
the like and a method of and device for recording the synchronous signal 
pattern determined by the former method on the medium. 
2. Related Background Art 
FIG. 1 shows one example of an ISO-standardized sector format of a WORM 
type or rewritable type optical disk of a 5.25 in. continuous servo 
tracking system. Table 1 shows patterns and meanings of the symbols with 
which the respective portions of FIG. 1 are marked. 
TABLE 1 
______________________________________ 
Symbols Meanings Patterns 
______________________________________ 
SM Sector mark 5-byte length. Pattern is 
"1.sup.10 0.sup.6 1.sup.6 0.sup.14 1.sup.6 0.sup.6 
1.sup.6 0.sup.6 1.sup.10 0.sup.2 1.sup.1 0.sup.2 
1.sup.1 0.sup.2 
1.sup.1 0.sup.1 " (1.sup.a,0.sup.b are code bits 
and 
indicate that "1" continues by 
the number a, while "0" 
continues by the number b. 
This corresponds to code bits 
of Y sequence in modulation. 
VF0123 Continuous data 
VF01-010010010010 . . . 0010 (12 
pattern for bytes) 
PLL lock VF02-100100100100 . . . 0010 (8 
bytes) 
000100100100 . . . 0010 (8 
bytes) 
VF03-VF01 
VF02 indicates that any one 
of two patterns is selected 
by preceding CRC data 
pattern. 
AM Address mark Pattern has 16 code bits and 
is "0100100000000100". 
SYNC Synchronous 3-byte length. Pattern is 
signal of data 
"0100 0010 0100 0010 0010 
portion 0010 0100 0100 1000 0010 
0100 1000". 
ID Address 2 bytes are recorded as a 
track number by (2, 7) 
modulation, and 1 byte is 
recorded as a sector number by 
(2, 7) modulation. 
CRC ID portion error 
2-byte CRC is recorded by 
detection code 
(2, 7) modulation, and 
generating polynomial is 
G(x) = x.sup.16 - x.sup.12 - x.sup.5 - 1 
PA Postamble ID and CRC are recorded by 
variable-length words as in 
(2, 7) modulation. PA is 
therefore used when not 
settled by 2 bytes of CRC 
after modulation. 
ODF Offset detect- 
Consisting of specular 
(Offset ion mark in surface with no groove 
Detection 
tracking error 
and no preformat data 
Flag) detection using 
push-pull 
method 
Gap Gap No data in interval 
of 3-byte length 
FLAG Flag indicating 
Pattern to be set 
that writing continues "100" for 
has been 5 bytes 
executed 
ALPC Test portion 2-byte length is blank 
Auto Las- 
for controll- 
er Power 
ing power level 
Control) 
of laser 
DATA Area for writ- 
Consisting of 1024-byte user 
ing user data 
data, 233-byte CRC, ECC and 
Resync and 12-byte control 
information 
BUFFER Disk rotation- 
No written data 
al fluctuat- 
ion margin 
area 
RESYNC Intra DATA 16 code bits 
area sync 0010 0000 0010 0100 
special code 
______________________________________ 
Referring to Table 1, the VFO pattern is a signal pattern for synchronizing 
a voltage frequency oscillator (VFO) in a phase locked loop (PLL) circuit 
of an information recording/reproducing device. Further, in the example 
given above, the synchronous signal (SYNC) pattern of a data portion has a 
3-byte length and is expressed by 48 code bits such as "0100 0010 0100 
0010 0010 0010 0100 0100 1000 0010 0100 1000". 
This ISO standard synchronous signal pattern is configured to have the 
following two major characteristics. 
(1): The pattern has a sharp auto-correlation. 
(2): The pattern can be generated by (2, 7) modulation, and the modulation 
is completed by 3 bytes without excess and deficiency. 
If the condition (1) is not satisfied, there increases a probability to 
cause a wrong synchronization due to a bit error. When the wrong 
synchronization takes place, the sector thereof cannot absolutely be 
reproduced. 
Whereas if the condition (2) is satisfied, the generation of the 
synchronous signal pattern is facilitated during the recording process, 
and a small-scale circuit may suffice. Further, in the example given 
above, the (2, 7) modulation is used in the data portion. Hence, the 
record of the synchronous signal by the same (2, 7) modulation implies 
that no special consideration is paid to a recording/reproducing signal 
property on the medium and a property of the detection system. 
In contrast with this, we have found out that the correlation property with 
the VFO pattern has a major role when determining a superiority and 
inferiority of the synchronous signal pattern from a sharpness of the 
auto-correlation property. In other words, the conventional method of 
determining the superiority and inferiority of the pattern from the 
sharpness of the auto-correlation property does not give any consideration 
to the correlation property with the VFO pattern. Namely, in the prior 
art, the optimum pattern is determined by considering the sole synchronous 
signal pattern. 
Therefore, in accordance with the conventional determining method, if no 
signal exists in front and in rear of a certain synchronous signal 
pattern, an output of a matching filter exhibits the sharpest peak in some 
cases. Based on the conventional method, such a synchronous signal pattern 
is to be optimal. Supposing that a given VFO pattern is disposed in front 
of the thus determined synchronous signal pattern, however, the output of 
the matching filter does not necessarily indicate that the synchronous 
signal pattern has the sharpest peak among all the patterns depending on a 
combination of the VFO pattern and the synchronous signal pattern in some 
cases. The above-described ISO pattern is an example thereof. 
Besides, we point out the following defects inherent in the prior art. 
That is, in the case of considering a conventional ordinary synchronous 
signal pattern detector, it has a predetermined threshold level with 
respect to the output value of the matching filter. The synchronous signal 
pattern is detected at the first timing when the output value exceeds the 
threshold level. This is a typical method. 
FIG. 2 shows an example of a typical synchronous signal pattern detector. 
Referring to FIG. 2, signals read from a recording medium are sequentially 
inputted to a shift register 13. On the other hand, a predetermined 
correct synchronous pattern is stored in a memory 14. The signal inputted 
to the shift register 13 is compared bitwise or blockwise with the 
synchronous pattern stored in the memory 14. Outputted then from a 
coincidence number adding circuit 15 is a correlation value of the thus 
compared two patterns, i.e., the bit number in which the values coincide 
with each other. This correlation value is compared with a predetermined 
threshold value in a threshold comparison circuit 16. A pulse signal 
indicating that the synchronous pattern has been detected is outputted 
from a pulse output circuit 17 at a timing when the correlation value 
exceeds the threshold value. Upon outputting this pulse signal, a 
reproducing means reproduces the data recorded on the medium subsequently 
to the detected synchronous pattern. 
Herein, if a plurality of synchronous signal pattern detection pulses are 
mistakenly outputted within one sector, the data number becomes incorrect, 
resulting in trouble in terms of the system. Hence, the pulse is generally 
outputted only in the first one detected position within the sector. 
According to this method, after the synchronous signal pattern has been 
once detected, there is no influence, whether the sharp portion of the 
correlation exists afterward or not. Namely, the correlation property may 
not be considered after the correct position. 
SUMMARY OF THE INVENTION 
From the observations given above, we have reached the following 
conclusions. 
(1): A true importance of the synchronous signal pattern of the recording 
and/or reproducing device lies in not an auto-correlation function but a 
sharpness of the correlation property between the recording pattern 
including the VFO pattern and the matching filter. It is therefore 
possible to surely obtain a more optimal synchronous signal pattern than 
in the prior art. 
(2): When looking at the sharpness of the correlation property, there is no 
necessity for considering the sharpness behind (right side) the correct 
position. The time required for obtaining the optimum synchronous signal 
pattern is thereby reduced. 
Accordingly, it is a primary object of the present invention, which 
obviates the problems inherent in the prior art described above, to 
provide a method capable of surely determining an optimum synchronous 
signal pattern. 
Further, it is another object of the present invention to provide an 
information transmitting or recording method, an information 
recording/reproducing device and an information transmitting device which 
are arranged to minimize the possibility to detect an incorrect 
synchronous signal pattern by use of an optimum synchronous signal 
pattern. 
Besides, it is still another object of the present invention to provide an 
information recording medium arranged to minimize the possibility to 
detect the incorrect synchronous signal pattern. 
To accomplish the foregoing objects, there is provided a method of 
determining an optimum synchronous signal pattern among samples of a 
plurality of synchronous patterns different from a predetermined VFO 
pattern in information configured by sequencing the VFO pattern, the 
synchronous signal pattern for identifying the head of information and the 
data, the method comprising the steps of: inputting the respective samples 
of the VFO pattern and synchronous signal pattern to a matching filter so 
as to detect correlation properties of the VFO pattern and the synchronous 
signal pattern with the matching filter; and 
determining the sample exhibiting an excellent correlation property as the 
synchronous signal pattern among the samples. 
In accordance with one embodiment of the present invention, there is 
provided a method of determining an optimum synchronous signal pattern 
among samples of a plurality of synchronous patterns different from a 
predetermined VFO pattern, in information configured by sequencing the VFO 
pattern, the synchronous signal pattern for identifying the head of 
information and the data, the method comprising the steps of: inputting 
the samples of the VFO pattern and the synchronous signal pattern to a 
matching filter; obtaining a difference between a maximum output value of 
the matching filter and the second highest value before outputting the 
maximum value with respect to each of the samples; comparing the output 
value differences obtained corresponding to the samples; and determining 
the sample having a maximum difference between the output values as the 
synchronous signal pattern. 
In accordance with another embodiment of the present invention, there is 
provided a method of determining an optimum synchronous signal pattern 
among samples of a plurality of synchronous patterns different from a 
predetermined VFO pattern, in information configured by sequencing the VFO 
pattern, the synchronous signal pattern for identifying the head of 
information and the data, the method comprising steps of: (a) inputting 
the VFO pattern to a matching filter; (b) inputting one of the samples of 
the plurality of synchronous signal patterns to the matching filter; (c) 
obtaining correlation properties of the samples of the inputted VFO 
pattern and the synchronous signal pattern with the matching filter; (d) 
obtaining a difference value between a maximum value of the correlation 
properties obtained in the step (c) and the second highest value 
preexisting a maximum value exhibiting point; (e) storing the difference 
value obtained in the step (d) in a first memory; (f) storing the sample 
of the synchronous signal pattern inputted in the step (b) in a second 
memory; (g) inputting to the matching filter the sample of the synchronous 
signal pattern different from the sample previously inputted; (h) 
obtaining correlation properties of the sample of the synchronous signal 
pattern inputted in the step (g) and the VFO pattern with the matching 
filter; (i) obtaining a difference value between a maximum value of the 
correlation properties obtained in the step (h) and the second highest 
value preexisting the maximum value exhibiting point; (j) comparing the 
difference value obtained in the step (i) and the difference value stored 
in the memory; (k) replacing the difference value stored in the memory 
with the difference value obtained in the step (i) if the difference value 
obtained in the step (i) is larger than the difference value stored in the 
memory as a result of the comparison, clearing the sample of the 
synchronous signal pattern previously stored in the second memory and 
storing the sample of the synchronous signal pattern inputted in the step 
(g) in the second memory; (l) additionally storing the sample of the 
synchronous signal pattern inputted in the step (g) in the second memory 
without clearing the sample of the synchronous signal pattern previously 
stored in the second memory if the difference value obtained in the step 
(i) is equal to the difference value stored in the memory as a result of 
the comparison; (m) repeating the steps (g)-(l) until all the samples are 
inputted to the matching filter; and (n) determining the sample stored in 
the second memory as the synchronous signal pattern. 
In accordance with the first embodiment of the present invention, there is 
provided an information recording method comprising steps of: forming 
information by sequencing a VFO pattern, a synchronous signal pattern for 
identifying the head of information and (2, 7)-modulated data; and 
recording the formed information on a recording medium, wherein the VFO 
pattern consists of a repetitive pattern of "1000", and the synchronous 
signal pattern is a binary signal pattern obtained by (2, 7)-modulating 
any one of hexadecimal notation representation signals "45A9F3".sub.H, 
"BE57F3".sub.H. "D4BA73".sub.H, "E527CF".sub.H and "F949F3".sub.H. 
In accordance with the second embodiment of the present invention, there is 
provided an information recording method comprising steps of: forming 
information by sequencing a VFO pattern a synchronous signal pattern for 
identifying the head of information and (1, 7)-modulated data; and 
recording the formed information on a recording medium, wherein the VFO 
pattern consists of a repetitive pattern of "100", and the synchronous 
signal pattern is any one of the following patterns: 
"100100010001001010101010000100101001", 
"100101001010010100010101010010001001", 
"100101001010010101010100010010001001" and 
"010101010100100010010100101001001001". 
In accordance with the third embodiment of the present invention, there is 
provided an information recording method comprising steps of: forming 
information by sequencing a VFO pattern, a synchronous signal pattern for 
identifying the head of information and (1, 7)-modulated data; and 
recording the formed information on a recording medium, wherein the VFO 
pattern consists of a repetitive pattern of "010", and the synchronous 
signal pattern is any one of the following patterns: 
"010010100101001010101010001001000100" and 
"010010100101001010101000100010010001". 
In accordance with the first embodiment of the present invention, there is 
provided an information recording/reproducing apparatus comprising: means 
for recording, on a recording medium, information configured by sequencing 
a VFO pattern, a synchronous signal pattern for identifying the head of 
information and (2, 7)-modulated data; and means for reproducing the 
information recorded on the recording medium, wherein the VFO pattern 
consists of a repetitive pattern of "1000", and the synchronous signal 
pattern is a binary signal pattern obtained by (2, 7)-modulating any one 
of hexadecimal notation representation signals "45A9F3".sub.H, 
"BE57F3".sub.H, "D4BA73".sub.H, "E527F".sub.H and "F949F3".sub.H. 
In accordance with the second embodiment of the present invention, there is 
provided an information recording/reproducing apparatus comprising: means 
for recording, on a recording medium, information configured by sequencing 
a VFO pattern, a synchronous signal pattern for identifying the head of 
information and (1, 7)-modulated data; and means for reproducing the 
information recorded on the recording medium, wherein the VFO pattern 
consists of a repetitive pattern of "100", and the synchronous signal 
pattern is any one of the following patterns 
"100100010001001010101010000100101001", 
"100101001010010100010101010010001001", 
"100101001010010101010100010010001001" and 
"010101010100100010010100101001001001". 
In accordance with the third embodiment of the present invention, there is 
provided an information recording/reproducing apparatus comprising: means 
for recording, on a recording medium, information configured by sequencing 
a VFO pattern, a synchronous signal pattern for identifying the head of 
information and (1, 7)-modulated data; and means for reproducing the 
information recorded on the recording medium, wherein the VFO pattern 
consists of a repetitive pattern of "010", and the synchronous signal 
pattern is any one of the following patterns 
"010010100101001010101010001001000100" and 
"010010100101001010101000100010010001". 
In accordance with the first embodiment of the present invention, there is 
provided an information recording medium comprising: a VFO pattern 
recorded on a part of the medium and consisting of a repetitive pattern of 
"1000"; a synchronous signal pattern recorded subsequently to the VFO 
pattern and consisting of a binary signal pattern obtained by (2, 
7)-modulating any one of hexadecimal notation representation signals such 
as "45A9F3".sub.H, "BE57F3".sub.H, "D4BA73".sub.H, "E527CF".sub.H and 
"F949F3".sub.H ; and (2, 7)-modulated data recorded subsequently to the 
synchronous signal pattern. 
In accordance with the second embodiment of the present invention, there is 
provided an information recording medium comprising: a VFO pattern 
recorded on a part of the medium and consisting of a repetitive pattern of 
"100"; a synchronous signal pattern recorded subsequently to the VFO 
pattern and being any one of the following patterns 
"100100010001001010101010000100101001", 
"100101001010010100010101010010001001", 
"100101001010010101010100010010001001" and 
"010101010100100010010100101001001001"; and (1, 7)-modulated data recorded 
subsequently to the synchronous signal pattern. 
In accordance with the third embodiment of the present invention, there is 
provided an information recording medium comprising: a VFO pattern 
recorded on a part of the medium and consisting of a repetitive pattern of 
"010"; a synchronous signal pattern recorded subsequently to the VFO 
pattern and being any one of the following patterns 
"010010100101001010101010001001000100" and 
"010010100101001010101000100010010001"; and (1, 7)-modulated data recorded 
subsequently to the synchronous signal pattern. 
In accordance with the first embodiment of the present invention, there is 
provided an information transmitting method comprising steps of: forming 
information by sequencing a VFO pattern, a synchronous signal pattern for 
identifying the head of information and (1, 7)-modulated data; and 
transmitting the formed information, wherein the VFO pattern consists of a 
repetitive pattern of "100", and the synchronous signal pattern is any one 
of the following patterns "100100010001001010101010000100101001", 
"100101001010010100010101010010001001", 
"100101001010010101010100010010001001" and 
"010101010100100010010100101001001001". 
In accordance with the second embodiment of the present invention, there is 
provided an information transmitting method comprising steps of: forming 
information by sequencing a VFO pattern, a synchronous signal pattern for 
identifying the head of information and (1, 7)-modulated data; and 
transmitting the formed information, wherein the VFO pattern consists of a 
repetitive pattern of "010", and the synchronous signal pattern is any one 
of the following patterns "010010100101001010101010001001000100" and 
"010010100101001010101000100010010001". 
In accordance with the first embodiment of the present invention, there is 
provided an information transmitting apparatus comprising: means for 
transmitting information configured by sequencing a VFO pattern, a 
synchronous signal pattern for identifying the head of information and (1, 
7)-modulated data; and means for receiving the information transmitted 
from the transmitting means, wherein the VFO pattern consists of a 
repetitive pattern of "100", and the synchronous signal pattern is any one 
of the following patterns "100100010001001010101010000100101001", 
"100101001010010100010101010010001001", 
"100101001010010101010100010010001001" and 
"010101010100100010010100101001001001". 
In accordance with the second embodiment of the present invention, there is 
provided an information transmitting apparatus comprising: means for 
transmitting information configured by sequencing a VFO pattern, a 
synchronous signal pattern for identifying the head of information and (1, 
7)-modulated data; and means for receiving the information transmitted 
from the transmitting means, wherein the VFO pattern consists of a 
repetitive pattern of "010", and the synchronous signal pattern is any one 
of the following patterns "010010100101001010101010001001000100" and 
"010010100101001010101000100010010001".

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT 
A preferred embodiment of the present invention will hereinafter be 
described with reference to the accompanying drawings. In this embodiment, 
an obtainment of such a synchronous signal pattern as to satisfy the 
above-described conditions (1), (2) involves the steps of: determining a 
preceding VFO pattern beforehand; obtaining an output value of a matching 
filter in simulation; obtaining a difference in the output value between a 
timing when the output value reaches its maximum and a timing when a 
pre-existing output value reaches the second highest level; obtaining a 
difference between the maximum output value and the second highest output 
value with respect to samples of all the synchronous signal patterns by 
further repeating the simulations; and finding out such a synchronous 
signal pattern that the difference therebetween comes to the maximum. 
FIG. 3 is a block diagram illustrating one embodiment of an apparatus 
employed for determining the synchronous signal pattern according to the 
present invention. Referring to FIG. 3, the reference numeral 20 
designates a VFO pattern input circuit; 21 a pattern S input circuit; 22 a 
(2, 7) modulation circuit; 23 a pattern length determining circuit; 24 a 
matching filter; 25 a correlation property determining circuit; 26 a 
comparison circuit; 27 a first memory; and 28 a second memory. Further, 
the symbols SW.sub.1, SW.sub.2 represent switches. 
FIG. 4 is a flowchart of assistance in explaining the method of determining 
the synchronous signal pattern according to the present invention which 
uses the apparatus of FIG. 3. In the following explanation, the symbol S 
indicates a sample of a synchronous signal pattern represented by a 
hexadecimal notation. The symbol H denotes a difference value between the 
maximum value of a correlation property and the second highest value 
existing before the maximum value, i.e., a sharpness of correlation in an 
optimum synchronous signal pattern. The symbol A shows a set of samples of 
the optimum synchronous signal pattern. 
To start with, in step S1, the VFO pattern is determined. Employed in this 
embodiment is a 12-byte pattern wherein 4 bits of "1000" are repeated 48 
times as the VFO pattern. This VFO pattern is inputted to the matching 
filter 24 from the VFO pattern input circuit 20. 
Executed next in step S2 is initialization of S=000000.sub.H (the subscript 
H herein indicates a hexadecimal number), H=0 and A=null. More 
specifically, a sample outputted from the pattern S input circuit 21 is 
set to "000000".sub.H. Then, "0" is inputted to the first memory, while 
the second memory is cleared. Hereinafter, the pattern S input circuit 21 
increments the pattern S by ones from "000000".sub.H to "FFFFFF".sub.H. 
Every time a different sample is outputted from the pattern S input 
circuit the operations of steps S3-S11 are repeated, thereby determining 
the correlation property. 
In step 83, the sample outputted from the pattern input circuit 21 
undergoes (2, 7) modulation in the modulation circuit 22. This (2, 
7)-modulated sample pattern is inputted to the pattern length determining 
circuit 23 in step S4. The pattern length determining circuit 23 
determines whether or not the inputted pattern is completed by 3 bytes. If 
not completed by 3 bytes, this pattern is not transferred to the matching 
filter. Then, the operation proceeds to step S11, wherein an indication is 
given to the pattern S input circuit 21 to output the next sample. Namely, 
the samples that are excessive or short of characters in the (2, 7) 
modulation are not adopted as synchronous signal patterns. Returning to 
step S3, a test of the next sample is effected. 
In step S4, if the result is "YES"--i.e., the sample pattern is completed 
by 3 bytes, the operation moves to step S5, wherein this sample pattern is 
inputted to the matching filter 24. 
Step S4 is a necessary operation because of the (2, 7) modulation being 
based on a variable-length coding system. If a coding system other than 
the (2, 7) modulation is applied, step S4 is needed on a condition that 
the applied system is defined as a variable-length coding system. 
In step S5, the correlation property is computed. The matching filter 24 
used for computing this correlation is of such a type as to compute the 
most general and universal total bit correlation. To be specific, in this 
filter, all the bits of 3 bytes of the synchronous signal pattern after 
the (2, 7) modulation are compared, and time variations in the coincidence 
number are observed. Then, correlation values (matching filter output 
values) in 53 positions, wherein the starting point is a position in which 
the correlation with the VFO pattern is known serves as a starting point, 
viz., the position disposed 52 clocks (48+4) before DM (SYNC), while the 
terminal point is DM. 
Obtained further in step S5 is a height difference h between a timing ("48" 
in the last) when the maximum correlation value is exhibited and a timing 
when the second highest correlation value is exhibited among the 53 
positions of the thus formed graph. 
FIG. 5 is a correlation graph in which the VFO pattern is a repetition of 
"1000", while the synchronous signal pattern is "BE57F3".sub.H. In the 
Figure, the axis of the ordinate indicates a degree of correlation. If 
this "BE57F3".sub.H is subjected to the (2, 7) modulation, the result is 
"0100 1000 1000 0100 1001 0001 0010 0010 0010 0001 0000 1000". In FIG. 5, 
the timing when the maximum correlation value is the last timing, and a 
correlation value of this timing is "48". A correlation value of the 
timing when the second highest correlation value is exhibited at a timing 
before the last timing is "16". Hence, the difference h between the 
maximum correlation value and the second highest correlation value is a 
parameter representing an intensity of the correlation. 
The timing when the maximum correlation value is shown is the last timing. 
The timing when the second highest correlation value is shown is set in 
terms of time before the timing when exhibiting the maximum correlation 
value. Tests after the last timing are thereby omitted, and the efficiency 
is improved, correspondingly. 
Next, in step S6, the comparison circuit 26 compares the maximum value H of 
the correlation intensities obtained in the past with the value h 
outputted in step S5 from the correlation property determining circuit 25. 
If h&lt;H, this sample is, it cannot be said, optimal as a synchronous signal 
pattern and therefore not adopted. The operation returns to step S3 after 
passing through steps S11, S12. To be specific, an indication signal is 
transmitted from the comparison circuit 26 to the pattern S input circuit 
21. The pattern S input circuit 21 outputs the next sample. If judged as 
"NO" in step S6, the operation moves to step S7. 
When h=H in step S7, it follows that this sample has the same correlation 
intensity as that of the optimum sample determined before it. Hence, the 
operation proceeds to step S10, wherein this sample is added to the set A. 
Namely, the switch SW.sub.1 is closed in response to the indication signal 
from the comparison circuit, and this sample is additionally stored in the 
second memory. 
If judged as "NO" in step S7--i.e., when h&gt;H, it follows that this sample 
exhibits a larger correlation intensity than those of any samples 
determined before it. The operation therefore moves to step S8. In step 
S8, the value h representing the correlation intensity of this sample is 
newly inputted as H. Namely, the switch SW.sub.2 is closed in accordance 
with the indication signal from the comparison circuit 26, and the value 
stored in the first memory 27 is replaced with the value h. Next, in step 
S9, the set A is cleared. More specifically, the second memory 28 is 
cleared in accordance with a clear signal given from the comparison 
circuit 26. Then, in step S10, this sample is stored in the second memory 
28. 
In steps described above, when inputting the sample pattern "000000".sub.H, 
H=0. Hence, the correlation intensity h of the sample pattern 
"000000".sub.H is stored in the first memory 27, while the second memory 
28 stores the sample pattern "000000".sub.H. Then, the determination on 
other samples are performed on the basis of this sample pattern 
"000000".sub.H until the sample having the larger correlation intensity is 
inputted. 
The operations of steps S3 to S11 are repeated until the sample pattern 
exceeds "FFFFFF".sub.H. If it is judged in step S12 that the sample 
pattern exceeds "FFFFFF".sub.H, the operation moves to step S13, wherein 
the correlation intensity H and a set A of the sample patterns are 
outputted from the first and second memories 27, 28. Some sample patterns 
outputted at this time are defined as patterns optimal to the synchronous 
signal pattern. Therefore, any one of the samples of the set A is 
determined as a synchronous signal pattern. 
The description given so far has dealt with an example of determining the 
synchronous signal pattern by the apparatus depicted in FIG. 3. According 
to the present invention, however, it is also possible to effect a 
computer-assisted determination of the synchronous signal pattern by 
setting a program shown in FIG. 4 in the computer. On this occasion, a 
usually employed personal computer may suffice in terms of the scale of 
the computer. 
If the VFO pattern is the repetition of "1000", the synchronous signal 
patterns obtained by the method discussed above may be the following five 
patterns: 
______________________________________ 
45 A9 F3.sub.H 
BE 57 F3.sub.H 
D4 BA 73.sub.H 
E5 27 CF.sub.H 
F9 49 F3.sub.H 
______________________________________ 
All these five patterns are similar to each other. The pulse numbers 
thereof are all 12, and (d, k)=(2, 4). Namely, each pattern has the four 
shortest portions of d=2. Note that d represents the minimum number which 
permits a continuation of 0, and k indicates the maximum number. The 
sample pattern "BE57F3".sub.H illustrated in FIG. 5 has the least 
continuation part of the shortest pattern among the five patterns. 
Referring to FIG. 5, it can be understood that the difference between the 
maximum portion and the second highest portion in the graph is 16. 
The present invention can be changed in a variety of forms within such a 
range that these variant forms do not depart from the gist thereof. 
For instance, this embodiment has dealt with the case where the VFO pattern 
is "0100 1000 1000 0100 1001 0001 0010 0010 0010 0001 0000 1000". The 
present invention is, however, applicable to other VFO patterns. For 
example, it is assumed the VFO pattern is a repetition of "010". 
In the same program of FIG. 1 as that in the preceding example, the VFO 
pattern is conceived as a repetitive pattern of "010", and this pattern is 
inputted to perform the calculation. 
Consequently, H=15, and the number of the set A becomes 5234. In this 
connection, the minimum value of S becomes "00512B".sub.H, while the 
maximum value of S is "BFF9CB".sub.H. FIGS. 7 and 8 are correlation graphs 
of these respective values. 
For a comparison, FIG. 6 shows a correlation graph for a sample pattern 
which becomes "0100 0010 0100 0010 0010 0010 0100 0100 1000 0010 0100 
1000" when the SYNC pattern is "89EACB"H, viz., when effecting the (2, 7) 
modulation, wherein the VFO pattern is the repetition of "010". This 
corresponds to the above-mentioned 5.25 in. WORM type or rewritable type 
ISO format. In the case of FIG. 6, the difference h between the maximum 
point and the second highest point is "13". As this numerical value h 
becomes smaller, the possibility of detecting an error of the synchronous 
signal pattern increases. 
In each of the embodiments of FIGS. 7 and 8, it can be understood that the 
difference between the last maximum point and the second highest point is 
"15". In the pattern of FIG. 6, H=13, and it can be therefore determined 
from these graphs that each of the embodiments of FIGS. 7 and 8 is 
superior to that. 
Further, patterns having the least number of pulses, e.g., 100 pulses are 
selected from 5234 patterns obtained and shown in FIGS. 9A to 9F. These 
patterns are numbered 385. Data words are shown in the left parts of FIGS. 
9A to 9F, while the right parts thereof indicate patterns in which the 
data words are (2, 7)-modulated. 
Besides, in the embodiments discussed above, the matching filter used for 
computing the correlation property comes under such a type as to compute 
the most general and universal total bit correlation. The method of 
obtaining the correlation according to the present invention is not, 
however, limited to this type. Namely, for instance, total bits are 
divided into a plurality of blocks, and a comparison is made for every 
block. It is also thinkable to employ a method of making the determination 
based on a threshold value in accordance with the coincidence block 
number. In this case, a time variation in the coincidence block number may 
be observed. 
The description given so far has dealt with the embodiments in which the 
present invention is applied to the (2, 7) modulation. The present 
invention is, however, applicable to other modulation systems. The 
following is an explanation of an example where the present invention is 
applied to a (1, 7) modulation. 
(1, 7) RLL (Run Length Limited) codes have hitherto been known as those 
used for a data coding system. FIG. 10 is a chart showing one example of a 
code conversion table of such (1, 7) RLL codes. Binary data of bits shown 
in the left column of the table are converted into data indicated by 
channel bits of the right column of the table by means of a coding 
circuit. 
As described above, when recording the (1, 7) RLL coded data on a recording 
medium or transmitting such data, the data are divided into a plurality of 
sectors, and the synchronous patterns are added thereto. FIG. 11 is a 
chart illustrating one example of a format of such sectors. Shown in this 
example is a format where the data are recorded on the recording medium 
such as an optical disk or the like. Referring to FIG. 11, the numerals 
written under the respective blocks indicate the number of bytes. 1 
byte--i.e., 8 bits--corresponds to 12 symbols (codes) in the (1, 7) codes. 
The sector consists of a header field and a recording field. The header 
field contains an address, viz., an information ID. Further, a data field 
of the recording field shows the data to be recorded on the recording 
medium. In FIG. 11, the above-mentioned AD is marked with a symbol AD. VFO 
indicates a constant periodic pattern for synchronizing the clocks during 
reproduction. As (Address Sync.) and DS (Data Sync.) respectively 
represent synchronous signal patterns for recognizing the heads of the 
data and address. Further, PA denotes an area for storing extra characters 
in the (1, 7) code conversion. GAP and BUF designate areas in which 
nothing is recorded. An explanation of MF, FLG and LPT will be omitted, 
because these symbols are not associated directly with the present 
invention. A repetitive pattern of "100100100100" has hitherto been used 
as a VFO pattern. A pattern of "100010100100010100100001001010100000" has 
hitherto been also employed as a DS pattern. This DS pattern is obtained 
by (1, 7)-coding the 3-byte data of "659IE2".sub.H. 
On the other hand, the information recorded on the medium in the 
above-described manner is reproduced by a reproducing means. The 
reproducing means includes a synchronous signal pattern detector. The 
synchronous pattern is detected by this detector, thereby recognizing the 
head position of the data. The data reproduction is thus started. This 
synchronous signal pattern detector has also, as explained earlier, the 
construction shown in, e.g., FIG. 2. 
FIG. 15 illustrates time variations in the output value of a coincidence 
number adding circuit 15 when the circuit depicted in FIG. 2 detects 
signals consisting of the VFO pattern composed of the repetitive pattern 
of "100" and the synchronous pattern of 
"100010100100010100100001001010100000". Referring to FIG. 15, the axis of 
abscissa indicates the time, while axis of ordinate indicates the output 
value of the coincidence number adding circuit 15. In FIG. 15, the 
rightmost bar is a correct detecting point of the synchronous pattern. 
Therefore, if a high correlation value part exists in the left of this 
bar, the possibility of causing the detection error increases, 
correspondingly. 
In the following embodiment, the possibility of detecting an incorrect 
synchronous pattern is minimized by use of a combination of the 
synchronous pattern and VFO pattern exhibiting a good correlation property 
when employing the (1, 7) codes. 
FIG. 12 is a conceptual diagram depicting an information 
recording/reproducing apparatus to which the present invention is applied. 
Referring to FIG. 12, a recording means 1 records, on a recording medium 
3, the information in which the VFO pattern, the synchronous signal 
pattern and the (1, 7) code data are sequenced. In accordance with this 
embodiment, the VFO pattern consists of a repetitive pattern of "100". 
Further, the synchronous pattern is composed of a pattern such as 
"100100010001001010101010000100101001". This synchronous pattern is 
obtained by (1, 7)-coding the 3-byte data of "53EC1F".sub.H. In this 
embodiment, the information is recorded based on an NRZI (Neon Return to 
Zero Inverted) system. However, an RZ (Return to Zero) system may also be 
used. 
The information recorded on the recording medium 3 is read by reproducing 
means 2, whereby reproduction data and reproduction synchronous clocks are 
reproduced. The reproducing means 2 is constructed as shown in a block 
diagram of, e.g., FIG. 13. Referring to FIG. 13, a signal detected by a 
signal detector 4 from a medium 3 is converted into a binary pulse signal 
by a binarizing circuit 5. This binary pulse signal is inputted to a phase 
locked loop (PLL) circuit 6, thereby generating a clock signal. On the 
other hand, an output of the binarizing circuit 5 is synchronized with the 
clock signal by a latch 7. A synchronous signal pattern is detected by a 
synchronous signal pattern detector 8. The synchronous signal pattern 
detector 8 has a construction shown in FIG. 2. When detection pulses are 
outputted from the synchronous signal pattern detector in the 
above-described procedures, the data subsequent to the synchronous signal 
pattern is decoded by a (1, 7) code decoder 9. Then, this decoder 9 
outputs the reproduction data and the reproduction synchronous clocks. 
Herein, FIG. 14 illustrates time variations in the output value of the 
coincidence number adding circuit 15 of FIG. 2 when using the VFO pattern 
and the synchronous signal pattern in accordance with this embodiment. 
Referring to FIG. 14, the axis of abscissa indicates time, while the axis 
of ordinate indicates the output value of the coincidence number adding 
circuit 15. In FIG. 14, the rightmost bar is a correct detecting point of 
the synchronous signal pattern. A difference between this rightmost 
correlation value and the maximum correlation value at other points is 15. 
This value 15 can be conceived as a margin for an error of a threshold 
comparison circuit 16 shown in FIG. 2. More specifically, in this graph, 
the margin for the error of the threshold comparison circuit 16 increases 
with a larger difference in the correlation value between the rightmost 
point and other maximum correlation value points. The possibility to 
mistakenly detect the synchronous signal pattern is thereby reduced. Based 
on this fact, when comparing the conventional example shown in FIG. 15 
with this embodiment, the difference in the correlation value is 9 in the 
conventional example. It can be known that the synchronous signal pattern 
is detectable more accurately in this embodiment than in the conventional 
example. 
FIG. 16 is a chart illustrating the time variation in the correlation value 
in another embodiment of the present invention. The device, the 
reproducing means and the synchronous signal pattern detector in this 
embodiment are all constructed in the same way with the preceding 
embodiment. 
In accordance with this embodiment, the VFO pattern consists of a 
repetitive pattern of "100". Further, the synchronous signal pattern is 
composed of a pattern such as "100101001010010100010101010010001001". As 
obvious from FIG. 16, in this embodiment also, a difference between the 
rightmost correlation value representing a correct detecting point of the 
synchronous signal pattern and the maximum correlation value at points 
other than this detecting point is 15. Hence, when using the synchronous 
signal pattern of this embodiment also, as in the same way with the 
preceding embodiment, there is obtained an effect to prevent the incorrect 
detection of the synchronous signal pattern. 
FIG. 17 is a chart showing the time variations in the correlation value in 
still another embodiment of the present invention. The device, the 
reproducing means and the synchronous signal pattern detector are all 
constructed in the same manner with the preceding embodiment. 
In accordance with this embodiment, the VFO pattern consists of a 
repetitive pattern of "100". Further, the synchronous signal pattern is 
composed of a pattern such as "100101001010010101010100010010001001". As 
obvious from FIG. 17, in this embodiment also, a difference between the 
rightmost correlation value representing a correct detecting point of the 
synchronous signal pattern and the maximum correlation value at points 
other than this detecting point is 15. Hence, when using the synchronous 
signal pattern of this embodiment also, as in the same way with the 
preceding embodiment, there is obtained an effect to prevent the incorrect 
detection of the synchronous signal pattern. 
FIG. 18 is a chart showing the time variations in the correlation value in 
a further embodiment of the present invention. The device, the reproducing 
means and the synchronous signal pattern detector are all constructed in 
the same manner with the preceding embodiment. 
In accordance with this embodiment, the VFO pattern consists of a 
repetitive pattern of "100". Further, the synchronous signal pattern is 
composed of a pattern such as "010101010100100010010100101001001001". As 
obvious from FIG. 18, in this embodiment also, a difference between the 
rightmost correlation value representing a correct detecting point of the 
synchronous signal pattern and the maximum correlation value at points 
other than this detecting point is 15. Hence, when using the synchronous 
signal pattern of this embodiment also, as in the same way with the 
preceding embodiment, there is obtained an effect to prevent the incorrect 
detection of the synchronous signal pattern. 
Under such a condition that [the VFO pattern is a repetitive pattern of 
"100", while the synchronous pattern is a (1, 7)-coded pattern of 3 
bytes], there exists no pattern exhibiting a more preferable correlation 
property than the four synchronous patterns shown in the embodiments of 
FIGS. 14 and 16 through 18. 
If the VFO pattern is a repetitive pattern of "010", the synchronous 
pattern having a large difference between the correlation value at the 
point of detecting the most preferable, i.e., correct synchronous pattern 
and the maximum correlation value at other points is different from the 
pattern in the above-described embodiment. The following is a description 
of such another embodiment of the present invention. 
FIG. 19 is a chart showing the time variations in the correlation value in 
still a further embodiment of the present invention. The device, the 
reproducing means and the synchronous signal pattern detector are all 
constructed in the same manner with the preceding embodiment. 
In accordance with this embodiment, the VFO pattern consists of a 
repetitive pattern of "010". Further, the synchronous signal pattern is 
composed of a pattern such as "010010100101001010101010001001000100". As 
seen from FIG. 19, in this embodiment also, a difference between the 
rightmost correlation value representing a correct detecting point of the 
synchronous signal pattern and the maximum correlation value at points 
other than this detecting point is 15. Hence, when using the synchronous 
signal pattern of this embodiment also, as in the same way with the 
preceding embodiment, there is obtained an effect to prevent the incorrect 
detection of the synchronous signal pattern. 
FIG. 20 is a chart showing the time variations in the correlation value in 
yet another embodiment of the present invention. The apparatus, the 
reproducing means and the synchronous signal pattern detector are all 
constructed in the same manner with the preceding embodiment. 
In accordance with this embodiment, the VFO pattern consists of a 
repetitive pattern of "010". Further, the synchronous signal pattern is 
composed of a pattern such as "010010100101001010101000100010010001". As 
seen from FIG. 20, in this embodiment also, a difference between the 
rightmost correlation value representing a correct detecting point of the 
synchronous signal pattern and the maximum correlation value at points 
other than this detecting point is 15. Hence, when using the synchronous 
signal pattern of this embodiment also, as in the same way with the 
preceding embodiment, there is obtained an effect to prevent the incorrect 
detection of the synchronous signal pattern. 
Under such a condition that [the VFO pattern is a repetitive pattern of 
"010", while the synchronous signal pattern is a (1, 7)-coded pattern of 3 
bytes], there exists no pattern exhibiting a more preferable correlation 
property than the two synchronous patterns shown in the embodiments of 
FIGS. 19 and 20. 
In the embodiments discussed above, DS (Data Sync.) added in front of the 
recording data is exemplified. The present invention is, however, also 
applicable to AS (Address Sync.) added in front of the address data. In 
this case, AS may be conceived as a 3-byte (1, 7) coded pattern. 
The present invention is applicable to all apparatus for recording and 
reproducing the coded signals. For example, when the present invention is 
applied to an optomagnetic disk device, the recording medium 3 of FIG. 12 
is an optomagnetic disk. The recording means 1 concretely corresponds to 
an optical head including an objective lens for condensing beams emitted 
from a semiconductor laser and a laser serving as a light source. Further, 
the signal detector 4 of the reproducing means 2 corresponds to a photo 
detector for receiving the reflected laser beams from the disk through an 
analyzer. 
Besides, the present invention can be also applied to an information 
transmitting apparatus. FIG. 21 is a block diagram illustrating an 
embodiment wherein the present invention is applied to the information 
transmitting apparatus. In FIG. 21, transmitting means 10 transmits the 
information composed of a VFO pattern for synchronizing the clocks, a 
synchronous signal pattern for recognizing the signal head and (1, 7) RLL 
coded data. The transmitted signal is received by receiving means 12 via a 
transmission line 11. The receiving means 12 has the same construction 
with the reproducing means of FIG. 12--i,e., this is constructed as 
depicted in FIG. 13. Then, the receiving means 12 includes a synchronous 
pattern detector constructed of: a memory for storing the signal having 
the same pattern as the synchronous pattern; a circuit for comparing the 
synchronous pattern transmitted from the transmitting means with the 
pattern stored in the memory; a circuit for examining correlation values 
of the two patterns compared; and a circuit for outputting a signal 
indicating a detection of the synchronous pattern when the above-mentioned 
correlation value exceeds a predetermined value. Then, when detecting the 
synchronous pattern, the data subsequent thereto is received. 
The transmitting apparatus described above also utilizes the same 
combination of the VFO pattern and the synchronous signal pattern as that 
in the embodiments of FIGS. 14 and 16 through 20. To be specific, when a 
repetitive pattern of "100" is employed as the VFO pattern transmitted 
from the transmitting means 10, the synchronous signal pattern involves 
the use of any one of patterns such as 
"100100010001001010101010000100101001", 
"100101001010010100010101010010001001", 
"100101001010010101010100010010001001" and 
"010101010100100010010100101001001001". Further, when a repetitive pattern 
of "010" is used as the VFO pattern transmitted from the transmitting 
means 10, the synchronous signal pattern involves the use of any one of 
patterns such as "010010100101001010101010001001000100"and 
"010010100101001010101000100010010001". Obtained also in this embodiment 
is the effect of minimizing the possibility in which the synchronous 
signal pattern detector mistakenly detects the synchronous signal pattern. 
The present invention is applicable to all the apparatus for transmitting 
the coded signals. For instance, when the present invention is applied to 
an optical communication system, the transmission line 11 of FIG. 21 
corresponds to an optical fiber. The transmitting means 10 concretely 
corresponds to an optical transmitter including a semiconductor laser 
serving as a light source and a modulation circuit. Further, the receiving 
means 12 corresponds to an optical receiver including a photo detector for 
receiving the light emerging from the optical fiber and a demodulation 
circuit. 
The present invention is not limited to the embodiments discussed above but 
may be applied in many forms. Besides, the present invention includes all 
such applied examples without departing from the claims.