Repatterned integrated circuit chip package

A repatterned integrated circuit chip package which balances and/or reduces the package capacitance associated with the gain resistor terminals to reduce the degradation of common mode rejection with frequency.

FIELD OF THE INVENTION

This invention relates to a repatterned integrated circuit chip package for reducing common mode error with frequency due to package capacitance and more particularly to such a repatterned integrated circuit chip package for an instrumentation amplifier.

BACKGROUND OF THE INVENTION

Amplifiers, such as for example, instrumentation amplifiers, are used to process normal mode signal and reject common mode signals. A shortcoming of such amplifiers is the degrading of their rejection of common mode signals with increasing frequency.

SUMMARY OF THE INVENTION

It is therefore an object of this invention to provide an improved integrated circuit chip package with repatterned pin connections for reducing common mode error with frequency.

It is a further object of this invention to provide an improved integrated circuit chip package with repatterned pin connections for reducing the effect of package capacitances.

This invention results from the realization that the underlying problem in degradation of common mode signal rejection with frequency is really due to package capacitance which is the parasitic capacitance developed between a power supply pin and a gain resistor pin and thus the common mode rejection could be dramatically improved by decreasing the effect of the package capacitance which can be done in any one or more of the following ways, by subjecting the gain resistor terminal of each amplifier stage to a power supply pin to balance the effect of the package capacitance or by spacing each power supply pin an equal distance from a respective one of the gain resistor pins or by not connecting the gain resistor terminals to external pins where they could be subject to parasitic capacitance coupling to the power supply pins or by separating the power supply pins and gain resistor pins by a greater distance with at least one other pin separating them, or by installing a compensating capacitor in the circuit connected to the other gain resistor terminal to balance the effect of the package capacitance.

This invention features a repatterned integrated circuit chip package including first and second power supply terminals, first and second input terminals, first and second output terminals, and first and second gain resistor terminals. There is a plurality of connection pins on the package for interconnecting with the terminals. The first and second power supply terminals are connected to pins which are equally spaced from the pins to which the first and second gain resistor terminals are connected for balancing the effect of package capacitance and reducing the common mode error with frequency.

This invention also features a repatterned integrated circuit chip package including first and second power supply terminals, first and second input terminals, first and second output terminals, and first and second gain resistor terminals. There are a plurality of connection pins on the package for interconnecting with the terminals. The first and second power supply terminals are connected to pins which are spaced from the first and second gain resistor terminal pins with at least one other of the pins between them, respectively, for reducing package capacitance and reducing the common mode error with frequency.

This invention also features a repatterned integrated circuit chip package including first and second power terminals, first and second input terminals first and second output terminals, and first and second gain resistor terminals. There are a plurality of connection pins on the package for interconnecting with said terminals. The first and second power supply terminals, input and output terminals are connected to selected ones of the pins. But the first and second resistor terminals are unattached to any pins for reducing package capacitance and common error with frequency.

This invention also features a repatterned integrated circuit chip package including first and second power terminals, first and second input terminals, first and second output terminals, and first and second gain resistor terminals. There are a plurality of connection pins on the package for interconnecting with the terminals. A compensating capacitor is connected to one of the gain resistor terminals to balance the effect of the package capacitance of the other gain resistor terminal and reduce the common error with frequency.

In a preferred embodiment one of the output terminals and one of the power supply terminals may be connected together and to a single pin.

DISCLOSURE OF A PREFERRED EMBODIMENT

There is shown inFIG. 1an integrated circuit chip package10according to the prior art, such as an instrumentation amplifier, which typically includes eight pins for external connection numbered1,2,3,4,5,6,7, and8. Pins1and8, labeled RG, are the gain resistor pins to which an external resistance can be connected to set the overall gain of the amplifier. Pins7and4, labeled V+/V−, are meant to connect to the power supply and may be thought of as an AC ground. One of the power supply pins,7or4, for example pin4, labeled V−, may actually be connected to ground or to a reference level. Pins2and3, −input and +input, respectively, provide the input to circuit10while the output is taken across pins5and6labeled Voutand VrefIn fact Vref, pin5, and V−, pin4, may be connected together to provide the reference for both the power supply and output.

The circuit actually borne by integrated circuit chip package10may be any suitable electronic circuit but in this embodiment is shown as an instrumentation amplifier as pictured in more detail inFIG. 2where it can be seen as consisting of three operational amplifiers,12,14, and15. Amplifiers12and14operate as differential to differential amplifiers or single-ended to differential amplifiers. Each amplifier,12and14, has its non-inverting input terminals,16and18, connected to one of the input pins,2and3respectively. Its inverting terminals,20and22, are connected to gain resistance pins1and8, the external gain resistance pins. Resistances24and26function as feedback resistors for amplifiers12and14. Amplifier15has associated with it four resistances,28,30,32, and34, and its terminals,36and38, are connected to the Vout, pin6and the other output pin5, labeled Vref. Power is supplied to the circuit to by +VSterminal40and −VSterminal42, which are connected to pins7and4, respectively. Although these provide power to all three amplifiers, the connections are not shown in the interest of simplicity and clarity.

In actual operation it has been determined that these circuits exhibit a high common mode rejection ratio at low frequencies which falls off rather abruptly as the frequency increases. For example as shown inFIG. 2A, where the common mode rejection ratio is shown on the ordinate in dB and the frequency is indicated along the abscissa, the characteristic50of common mode rejection ratio stays high in the area of52, then abruptly falls off at the knee54, and drops steadily through section56. This can be predicted by the expressionf=(110CMRR⁡(dc)20×2⁢π⁢⁢RF⁢CP),
where RFis the feedback resistance for amplifier14and CPis the package capacitance60awhich affects the gain of amplifier14a. This means that any common mode signals of higher frequency will not be rejected well and will show up in the output signal, causing errors in interpretation.

This problem has been widely recognized, but not fully understood. It is now understood in accordance with this invention, that the cause of this common mode rejection ratio characteristic50is actually a feature of parasitic capacitance called package capacitance. Namely it is the result of the close proximity between an AC ground or DC source and one of the gain resistor terminals. The conditions for this are set by the typical pin pattern in an integrated circuit chip as described with respect to FIG.1. There it can be seen that the V+pin7is immediately adjacent to one of the gain resistor pins8.

Referring now toFIG. 3it can be seen that when pin7is close to pin8the parasitic capacitance CP60aoccurs between those two pins. This introduces a current into the feedback loop of amplifier14awhich unbalances it with respect to the operation of its companion amplifier12a. It can be seen that as the frequency increases and the impedance of the capacitance CP60adecreases the gain of amplifier14awill increase. This increase in gain, not actually reflecting an input signal, causes an error in so far as it shows a differential signal between the output of operational amplifier14aand amplifier12awhich is detected by amplifier15aand presented at the output as an indication of the signal.

Thus, as taught herein, there are a number of ways that the problem can be solved by repatterning the terminal to pin connections. First the gain resistance terminals20aand22acan simply not be connected to pins1and8as shown at breaks21aand23aso that they are not exposed to the power supply +VSon pin7. In another approach the other power supply pin4for power supply −VScan be positioned adjacent pin1as shown in phantom49inFIG. 3so that both gain resistance pins,1and8, have a package capacitance CP. In this way the package capacitance has not been eliminated but it has been balanced so that the output of amplifiers12aand14awill be equally effected which will minimize or eliminate any erroneous differential signal and prevent amplifier15afrom responding to an improper input differential signal.

A third way of solving the problem is shown inFIG. 4where the pins have been repatterned as shown. The gain resistance pins are still pins1and8, the input pins are now pins2and7, the power supply pins are pins3and6and the output pins are pins4and5. In this way the power supply pins6and3, +VSand−VSrespectively, have not only been moved an equal distance away from the gain resistance pins1and8, but they also have placed interstitially of the other pins, namely pins7and2, the input pins, which are not power supply pins or AC ground pins and so there will be no significant capacitive coupling which would give rise to the package capacitance and the incumbent common mode rejection errors. A fourth way to repattern the package is to add a discrete capacitor25,FIG. 3, at one gain resistor terminal to balance the package capacitance on the other gain resistor terminal.

Although thus far the description of the specific embodiment has been with respect to an instrumentation amplifier and to a package which has8pins, neither of these are limitations on the invention as the invention works with any similar circuit to overcome the package capacitance problem and regardless of the number of pins involved. For example as shown inFIG. 5, integrated circuit chip package10bincludes ten pins, numbered1-10. Pins1and10are connected to the input signal, pins2and9are connected to the gain resistance terminals, pins8and3are connected to ground, pins7and4are connected to power supplies V+and V−, and pins6and5are connected to the output Voutand Vref. In this way the power supply pins7and4are not only removed from gain resistance pins9and2, they are removed with another set of pins between them which substantially reduces the capacitive coupling and thus the package capacitance between them. But they are also spaced by approximately an equal amount so that any error that did occur would be balanced and would only minimally affect the differential signal produced. In addition the separating pins8and3, between them are inactive pins merely connected to ground which further serves to isolate the power supply pins7and4from the gain resistor pins9and2. However, since there is a difference in the potential between pins9and2on the one hand, and pins8and3on the other, there can still be some capacitive coupling which could interfere with operation of the circuit. To overcome even this problem the solution shown inFIG. 6is provided wherein the grounding of pins8and3has been eliminated and instead each is driven by a buffer amplifier70and72respectively which maintains the respective pins8and3at the same voltage as the voltage on pins9and2, respectively, so that there is no capacitive coupling and the package capacitance problem is eliminated. Although FIG.6andFIG. 5are shown with ten pins, this is not a necessary limitation as stated previously the number of pins does not affect the invention and could be any number six, ten, twelve, eighteen, or any chosen number n.