Devices having bias temperature instability compensation

Methods are provided for operating a memory device. An exemplary method involves obtaining a standby current through a memory block and adjusting a supply voltage for the memory block based on the obtained standby current. An exemplary memory device includes a block of one or more memory cells, a voltage regulating element coupled to the block to provide a supply voltage to the block, a current sensing element coupled to the block to measure current through the block, and a control module coupled to the voltage regulating element and the current sensing element to adjust the supply voltage provided by the voltage regulating element based on a measured current through the block obtained from the current sensing element.

TECHNICAL FIELD

Embodiments of the subject matter generally relate to electronics, and more particularly, relate to compensating for the effects of bias temperature instability in integrated circuits and other electronic devices.

BACKGROUND

Bias temperature instability (BTI) is a recognized problem facing designers of integrated circuits and other electronic devices. Over time, BTI tends to increase the threshold voltage of transistors of a device, which in turn, may result in a corresponding decrease in performance and/or reliability. For example, in a static random-access memory (SRAM) cell, an increase in the threshold voltage of one or more of the cross-coupled transistors may impair the ability to read and/or write data from/to the SRAM cell without increasing the read and/or write cycle time. Accordingly, it is desirable to compensate for or otherwise mitigate the effects of BTI in electronic devices to maintain performance and reliability.

BRIEF SUMMARY

In an exemplary embodiment, a method is provided for operating a memory device. The method involves obtaining a standby current through a memory block and adjusting a supply voltage for the memory block based on the obtained standby current.

In another embodiment, a method of operating a memory device including one or more memory cells involves obtaining a cumulative leakage current through the one or more memory cells, determining a voltage adjustment amount based on a difference between the cumulative leakage current and a reference current using a model of a relationship between the cumulative leakage current through the one or more memory cells and the supply voltage for the one or more memory cells, and adjusting the supply voltage for the one or more memory cells by the voltage adjustment amount.

In yet another embodiment, an apparatus for a memory device is provided. The memory device includes a block of one or more memory cells, a voltage regulating element coupled to the block to provide a supply voltage to the block, a current sensing element coupled to the block to measure current through the block, and a control module coupled to the voltage regulating element and the current sensing element. The control module adjusts the supply voltage provided by the voltage regulating element based on a measured current through the block obtained from the current sensing element.

DETAILED DESCRIPTION

Embodiments of the subject matter described herein generally relate to methods for operating a memory device to compensate for the effects of bias temperature instability (BTI) within transistors of the memory cells within the memory device. As described in greater detail below, the relationship between the standby leakage current and the supply voltage is determined for a block of memory cells, and during operation of the memory device, the supply voltage for that block of memory cells is adjusted based on a recently obtained standby leakage current through the block to thereby compensate for BTI effects within the memory cells based on changes in the standby leakage current through the memory cells. In this regard, as threshold voltages of transistors of the memory cells increase, the standby leakage current through the block of memory cells decreases, and based on this decrease in standby leakage current, the supply voltage of the block of memory cells is increased by an amount determined using the relationship between the standby leakage current and supply voltage for the block that compensates for the increase in threshold voltages. In this manner, the standby leakage current through the block of memory cells is maintained substantially constant or otherwise above a minimum reference current that ensures that the memory cells can be reliably accessed (e.g., read from and/or written to) within the access cycle time previously established for the block over the lifetime of the memory device.

Turning now toFIG. 1, in an exemplary embodiment, a memory device100includes, without limitation, a memory block102, access circuitry104, a voltage regulating element106, a current sensing element108, a switching element110, and a control module112. In an exemplary embodiment, the memory device100is implemented as an integrated circuit or another electronic device package, wherein the circuit elements and/or electrical components of the memory device100are fabricated or otherwise formed on, mounted to, or provided on a semiconductor substrate (or die) for the integrated circuit. It should be understood thatFIG. 1is a simplified representation of the memory device100for purposes of explanation and ease of description, and that practical embodiments may include other devices and components to provide additional functions and features, and/or the memory device100may be part of a much larger system, as will be understood. For example, a practical embodiment of a memory device may include any number of memory blocks, with each memory block having any number of memory cells as desired to support a particular application. Additionally, although not illustrated inFIG. 1, in practice, the integrated circuit of the memory device100will include numerous physical interfaces that provide electrical connections to/from electrical components external to the integrated circuit from/to elements and/or components of the memory device100.

In an exemplary embodiment, the memory block102includes one or more memory cells130coupled between a node118configured to receive a positive reference (or supply) voltage for the memory block102and a node120configured to receive a negative reference (or ground) voltage for the memory block102. In other words, the supply voltage nodes of the memory cells130are coupled to the memory block supply voltage node118and the ground voltage nodes of the memory cells130are coupled to the memory block ground voltage node120. In exemplary embodiments, the memory cells130are realized as static random-access memory (SRAM) cells, as described in greater detail below in the context ofFIG. 2.

In the illustrated embodiment ofFIG. 1, the access circuitry104generally represents the sense amplifiers, write drivers and/or other circuitry coupled to the bit lines and/or word lines of the memory cells130and configured to support writing data to and/or reading data from the memory cells130. When the memory cells130are not being accessed by the access circuitry104, or in other words, when the memory block102and/or memory cells130are in a standby mode, leakage currents flow through the memory cells130, as described in greater detail below. In this regard, the memory block supply voltage at the memory block supply voltage node118is adjusted based on changes in the leakage current through the memory block102to compensate for the changes in the leakage current, and thereby ensuring the access circuitry104can reliably access the memory cells130within a fixed access duty cycle time (e.g., the read cycle time and/or write cycle time for the memory block102) during operation of the memory device100, as described below.

As illustrated inFIG. 1, in an exemplary embodiment, the memory block supply voltage node118is coupled to the output of the voltage regulating element106. The voltage regulating element106is coupled to a positive reference (or supply) voltage node114for the memory device100and provides a regulated voltage for the memory cells130at the memory block supply voltage node118in response to signals and/or commands from the control module112. As described in greater detail below in the context ofFIG. 3, in exemplary embodiments, the control module112provides signals and/or commands to the voltage regulating element106that are configured to cause the voltage regulating element106to adjust the output voltage at the memory block supply voltage node118to compensate for BTI or other circuit-level effects within the memory cells130of the memory block102. In this regard, during operation of the memory device100, the control module112adjusts the voltage provided by the voltage regulating element106at memory block supply voltage node118to maintain a cumulative standby current through the memory block102(e.g., a sum of the individual leakage currents of the memory cells130) that is substantially constant or otherwise above a reference current value that ensures the memory cells130can be reliably accessed. In practice, the voltage regulating element106may be realized using a programmable voltage divider or other adjustable voltage regulation circuitry capable of supporting the compensation processes described herein.

Still referring toFIG. 1, in an exemplary embodiment, the switching element110is coupled between the memory block ground voltage node120of the memory block102and the negative reference (or ground) voltage node116for the memory device100, and the switching element110is capable of selectively coupling the current sensing element108electrically in series between the memory block ground voltage node120and the memory device ground voltage node116, as described in greater detail below in the context ofFIG. 3. The current sensing element108generally represents the circuitry and/or hardware components configured to sense, measure, or otherwise obtain the magnitude of the electrical current flowing in series between the memory block ground voltage node120and the memory device ground voltage node116when the switching element110couples the current sensing element108between the nodes116,120. In this regard, in the illustrated embodiment, the switching element110includes a first terminal (or node)122coupled to the current sensing element108and a second terminal (or node)124coupled to the memory device ground voltage node116. When the switching element110is in the state where it provides an electrical connection between node122and the memory block ground voltage node120, the current sensing element108is effectively electrically in series between the memory block ground voltage node120and the memory device ground voltage node116so that the cumulative current flowing through the memory cells130of the memory block102flows through or is otherwise capable of being sensed by the108. In practice, the current sensing element108may be realized using a sense resistor or other current sensing circuitry capable of supporting the compensation processes described herein.

In an exemplary embodiment, the control module112represents the hardware, processing logic, circuitry and/or other components of the memory device100that are configured to operate the voltage regulating element106and the switching element110to periodically monitor the standby leakage current consumption of the memory block102, adjust the memory block supply voltage provided by the voltage regulating element106based on changes in the standby leakage current, and perform additional tasks and/or functions associated with the operation of the memory device100described in greater detail below. Depending on the embodiment, the control module112may be implemented or realized with a general purpose processor, a controller, a microprocessor, a microcontroller, a content addressable memory, a digital signal processor, a field programmable gate array, any suitable programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof, designed to perform the functions described herein. For example, in accordance with one or more embodiments, the control module112includes or otherwise accesses a memory or another suitable non-transitory short or long term storage media capable of storing computer-executable programming instructions or other data for execution that, when read and executed by the control module112, cause the control module112to execute and perform one or more of the processes tasks, operations, and/or functions described herein.

Referring now toFIG. 2, and with continued reference toFIG. 1, in an exemplary embodiment, the memory cells130of the memory block102are realized as SRAM cells, such as SRAM cell200. It should be understood thatFIG. 2is a simplified representation of the SRAM cell200for purposes of explanation and ease of description and that practical embodiments may include additional and/or fewer devices and components. In this regard, althoughFIG. 2depicts a six transistor SRAM cell, the subject matter described herein is not intended to be limited to any particular memory cell configuration.

The SRAM cell200illustrated inFIG. 2includes a pair of p-type metal-oxide-semiconductor (PMOS) field-effect transistors202,204and a pair of n-type metal-oxide-semiconductor (NMOS) field-effect transistors206,208arranged in a cross-coupled inverter configuration. In this regard, the PMOS transistors202,204function as pull-up transistors having their source terminals coupled to a node218(e.g., memory block supply voltage node118) configured to receive a positive reference (or supply) voltage for the SRAM cell200and the NMOS transistors206,208function as pull-down transistors having their source terminals coupled to a node220(e.g., memory block ground voltage node120) configured to receive a negative reference (or ground) voltage for the SRAM cell200. The SRAM cell200also includes access transistors210,212to external access circuitry (e.g., access circuitry104) to support reading data from and/or writing data to the SRAM cell200. For example, the source and/or drain terminals of the access transistors210,212may be coupled to the bit lines corresponding to the SRAM cell200and the gate terminals of the access transistors210,212may be coupled to the word line corresponding to the SRAM cell200, wherein the bit lines and word line for the respective SRAM cell200are coupled to external access circuitry (e.g., access circuitry104). As used herein, the standby leakage current of the SRAM cell200should be understood as referring to the current that flows between the supply voltage node218and the ground voltage node220through the cross-coupled transistors202,204,206,208when the access transistors210,212are turned off or otherwise deactivated. In other words, the standby leakage current of the SRAM cell200is the cumulative current flowing through the transistors202,204,206,208,210,212of the SRAM cell200when the access transistors210,212are turned off. In the standby mode, one of the PMOS transistors (e.g., PMOS transistor202) will be turned on and its series coupled NMOS transistor (e.g., NMOS transistor206) will be turned off while the other PMOS transistor (e.g., PMOS transistor204) will be turned off and the other NMOS transistor (e.g., NMOS transistor208) will be turned on, thereby facilitating a standby leakage current flowing between the supply voltage node218and the ground voltage node220through the cross-coupled transistors that are turned on (e.g., PMOS transistor202and NMOS transistor208).

FIG. 3depicts an exemplary compensation process300suitable for implementation by a memory device to compensate for potential effects of BTI in memory cells of the memory device. The various tasks performed in connection with the compensation process300may be performed by software, hardware, firmware, or any combination thereof. For illustrative purposes, the following description may refer to elements mentioned above in connection withFIGS. 1-2. In practice, portions of the compensation process300may be performed by different elements of the memory device100, such as, for example, the access circuitry104, the voltage regulating element106, the current sensing element108, the switching element110, and/or the control module112. It should be appreciated that the compensation process300may include any number of additional or alternative tasks, the tasks need not be performed in the illustrated order and/or the tasks may be performed concurrently, and/or the compensation process300may be incorporated into a more comprehensive procedure or process having additional functionality not described in detail herein. Moreover, one or more of the tasks shown and described in the context ofFIG. 3could be omitted from a practical embodiment of the compensation process300as long as the intended overall functionality remains intact.

Referring toFIG. 3, and with continued reference toFIGS. 1-2, in an exemplary embodiment, the compensation process300begins by obtaining or otherwise determining a relationship between memory block supply voltage and the standby current consumption for a memory block (task302). In an exemplary embodiment, the cumulative standby leakage current through the memory cells130of the memory block102is modeled or otherwise characterized as a function of the memory block supply voltage at memory block supply voltage node118. For example, the standby leakage current through the memory block102may be measured across a range of supply voltages for different configurations of bits stored by the memory cells130and then averaged to obtain a curve (or function) representative of the average standby leakage current through the memory block102as a function of the memory block supply voltage. In this regard, the standby leakage current model accounts for variations across the different memory cells130and variations in the bits of data maintained by the memory cells130. In an exemplary embodiment, the standby leakage current model also accounts for variations in the relationship between the standby leakage current memory block supply voltage due to BTI, for example, by simulating increases in the threshold voltages of the transistors of the memory cells130and calculating or otherwise determining the cumulative standby leakage current across a range of supply voltages and different configurations of bits, which is also utilized when developing the model of the standby leakage current with respect to the memory block supply voltage. The standby leakage current model may also account for variations in the standby leakage current with respect to variations in the temperature of the memory cells130, for example, by calculating or otherwise determining the cumulative standby leakage current across a range of temperatures and utilizing the relationship between standby leakage current and temperature when developing the standby leakage current model. In exemplary embodiments, the standby current through the memory block102is characterized prior to being deployed in the memory device100and the control module112is provisioned with or otherwise configured to store the standby leakage current model for the memory block102(e.g., the curve or function representing the relationship between the cumulative standby leakage current through the memory cells130and the memory block supply voltage at memory block supply voltage node118). In other embodiments, the control module112may determine a standby leakage current model for the memory block102by disabling or otherwise deactivating the access circuitry104(e.g., to ensure the access transistors210,212of the memory cells130,200are turned off), activating the switching element110to provide the current sensing element108in series between the memory device ground voltage node116and memory block ground voltage node120, providing signals and/or commands to vary the voltage output by the voltage regulating element106at memory block supply voltage node118, obtaining the standby current measured (or sensed) by the current sensing element108, and calculating or otherwise determining the standby leakage current model based on the memory block supply voltages provided by the voltage regulating element106and the current measured by the current sensing element108.

After the relationship between memory block supply voltage and standby current for the memory block102is determined, the control module112stores or otherwise maintains the standby leakage current model and configures the voltage regulating element106to provide an initial memory block supply voltage at memory block supply voltage node118that is chosen to achieve one or more desired performance metrics for the memory block102and/or the memory device100. The control module112may also obtain the initial standby current through the memory block102sensed and/or measured by the current sensing element108and store or otherwise maintain the initial standby current in memory along with the standby leakage current model for the memory block102and the initial memory block supply voltage.

In an exemplary embodiment, during operation of the memory device, the compensation process300continues by periodically inverting the bits of data maintained or stored by the memory block (task304). In this regard, when a memory cell130,200maintains a constant logic value, BTI effects may asymmetrically increase the threshold voltages of the transistors of the memory cell130,200. For example, the threshold voltages of pull-up transistor202and pull-down transistor206may increase due to BTI effects while the threshold voltages of the remaining transistors204,208are unchanged or increase by a lesser amount. Asymmetric threshold voltage increases for transistors of a memory cell130,200increases the likelihood of unsuccessfully accessing the memory cell130,200, for example, by increasing the amount of time required to read data from the memory cell130,200. Accordingly, in an exemplary embodiment, the control module112periodically inverts the bits of data maintained by the memory cells130,200of the memory block102if the bits of data maintained by the memory cells130,200have not changed during a preceding time interval to maintain substantially symmetric threshold voltages for the transistors of the memory cells130,200. For example, the memory block102may include or otherwise be associated with a bit that indicates whether the memory block102was written to during a preceding time interval along with a bit that indicates whether the data in the memory block102is inverted. At the end of a particular time interval, the control module112obtains or otherwise checks the bit indicating whether the memory block102was written to during the preceding time interval, and when the bit indicates that the memory block102was not written to during the preceding time interval, the control module112reads or otherwise obtains the bits of data maintained by the memory cells130via the access circuitry104, inverts the obtained bits of data, writes the inverted bits of data to the memory cells130via the access circuitry104, and modifies the other bit of the memory block102to indicate that the data in the memory block102is inverted. Conversely, when the bit indicates that the memory block102was written to during the preceding time interval, the control module112resets the bit for the subsequent time interval. When data is written to a memory block102during the subsequent time interval, the control module112sets the bits to indicate that the memory block102was written to and that the data is not inverted. When data is read from the memory block102during a subsequent time interval, the control module112obtains or otherwise checks the bit that indicates whether the data is inverted, and when the data is inverted, the control module112inverts the bits of data read from the memory block102to their original non-inverted state before providing the data to devices or other elements external to the memory device100(e.g., to a processor coupled the memory device100).

In an exemplary embodiment, the compensation process300continues by periodically obtaining the standby current through the memory block, and based on the obtained standby current, determining an amount by which the memory block supply voltage should be adjusted to compensate for BTI or other circuit-level effects and adjusting the memory block supply voltage by that amount (tasks306,308,310). In this regard, an increase in threshold voltages of the transistors of a memory cell130,200attributable to BTI effects reduces the likelihood of successfully accessing that memory cell130,200during a fixed time period without compensating for the threshold voltage increases. At the same time, an increase in the threshold voltage of a transistor of a memory cell130,200produces a decrease in the leakage current through that transistor for a given supply voltage. Accordingly, based on the decrease in the standby leakage current for the memory block102and the standby leakage current model for the memory block102, the control module112determines an amount by which the memory block supply voltage at memory block supply voltage node118should be increased to compensate for the threshold voltage increases caused by BTI or other circuit-level effects and thereby reduce the likelihood of unsuccessfully accessing one or more of the memory cells130,200. To put it another way, the memory block supply voltage at node118is increased by an amount that ensures the memory cells130,200can be reliably accessed.

As described above, to obtain the cumulative standby leakage current through the memory cells130,200of the memory block102, the control module112disables or otherwise deactivates the access circuitry104and activates the switching element110to couple the current sensing element108in series between the memory device ground voltage node116and the memory block ground voltage node120. In an exemplary embodiment, the control module112determines a difference between the standby current obtained from the current sensing element108and a reference standby current, and based on that difference, utilizes the previously determined relationship between standby current and supply voltage for the memory block102to determine an amount by which the voltage output of the voltage regulating element106should be adjusted to reduce or otherwise eliminate the difference between the measured current through the memory block102and the reference current. In accordance with one embodiment, the reference current is a minimum standby leakage current for the memory block102that is determined based on an access duty cycle for the memory block102. For example, during characterization of the memory block102, a standby leakage current that provides a sufficiently high likelihood of successfully accessing the memory cells130,200may be determined or otherwise identified as a minimum standby leakage current. In other words, the minimum standby leakage current corresponds to a tolerable increase in threshold voltages of the transistors of the memory cells130,200that still allows the memory cells130,200to be accessed within the shortest access duty cycle (e.g., the shortest of the read and write cycle times) for the memory block102with a sufficiently high likelihood of success. When the obtained standby current is less than the minimum standby leakage current, the control module112utilizes the standby leakage current model for the memory block102to determine an amount by which the voltage output of the voltage regulating element106should be increased to ensure that the standby current through the memory block102is greater than or equal to the minimum standby leakage current. In this manner, the voltage adjustment amount compensates for the difference between the obtained standby current and the minimum standby current. After determining the voltage adjustment amount, the control module112signals or otherwise commands the voltage regulating element106to adjust the memory block supply voltage at memory block supply voltage node118by the voltage adjustment amount. Thus, when the threshold voltages of the transistors of the memory cells130,200increase, the memory block supply voltage is increased by a corresponding amount based on the decrease in standby leakage current caused by the threshold voltage increases, thereby ensuring that the memory cells130,200of the memory block102can be accessed within the access duty cycle with a sufficiently high likelihood of success. After the configuring the voltage regulating element106to provide the adjusted memory block supply voltage, the control module112activates the switching element110to decouple the current sensing element108from between nodes116,120and enables the access circuitry104for continued operation of the memory device100with the adjusted memory block supply voltage.

In accordance with one or more alternative embodiment, the reference current is the initial standby leakage current for the memory block102obtained by the control module112when the memory device100initializes or otherwise begins operation. In this regard, when the obtained standby current is less than the initial standby leakage current, the control module112utilizes the standby leakage current model for the memory block102to determine an amount by which the voltage output of the voltage regulating element106should be increased to ensure that the standby current through the memory block102is substantially equal to the initial standby leakage current. In this manner, the voltage adjustment amount compensates for increases in the threshold voltages of the transistors of the memory cells130,200and maintains a substantially constant standby leakage current through the memory block102. In another alternative embodiment, the control module112utilizes the standby leakage current model for the memory block102to calculate or otherwise determine an average amount by which the threshold voltages of the transistors of the memory cells130,200have increased based on the obtained standby leakage current, and then signals or otherwise commands the voltage regulating element106to increase the memory block supply voltage by that amount (e.g., the average threshold voltage increase across the memory cells130,200of the memory block102). In other words, the control module112may increase memory block supply voltage by an amount greater than or equal to the increase in the threshold voltages of the transistors of the memory cells130,200.

Still referring toFIG. 3, after increasing the memory block supply voltage based on decreases in the cumulative standby leakage current through the memory cells to compensate for increases in the threshold voltages of the transistors of the memory cells, the loop defined by tasks304,306,308and may repeat as desired throughout operation of the memory device. In this regard, the control module112periodically inverts the bits of data maintained by the memory cells130,200of the memory block102to ensure increases in the threshold voltages of the transistors of the memory cells130,200attributable to BTI or other effects are substantially symmetrical and periodically increases the memory block supply voltage at memory block supply voltage node118to compensate for any increases in the threshold voltages throughout operation of the memory device100. Thus, the compensation process300reduces the likelihood of BTI or other effects impairing operation of the memory device100over the lifetime of the memory device100and maintains a sufficiently high likelihood of successfully accessing the memory cells130,200without increasing the access duty cycle(s).

For the sake of brevity, conventional techniques related to memory cells, memory accesses or other memory operations, voltage regulation, current sensing, signaling, field-effect transistors, BTI, and other functional aspects of the subject matter may not be described in detail herein. As used herein, a “node” means any internal or external reference point, connection point, junction, signal line, conductive element, or the like, at which a given signal, logic level, voltage, data pattern, current, or quantity is present. Additionally, certain terminology may also be used herein for the purpose of reference only, and thus is not intended to be limiting, and the terms “first”, “second” and other such numerical terms referring to structures do not imply a sequence or order unless clearly indicated by the context. The foregoing description also refers to elements or nodes or features being “connected” or “coupled” together. As used herein, unless expressly stated otherwise, “connected” means that one element is directly joined to (or directly communicates with) another element, and not necessarily mechanically. Likewise, unless expressly stated otherwise, “coupled” means that one element is directly or indirectly joined to (or directly or indirectly communicates with) another element, and not necessarily mechanically. Thus, although the figures depict direct electrical connections between circuit elements and/or terminals, alternative embodiments may employ intervening circuit elements and/or components while functioning in a substantially similar manner.