Memory structure

A memory structure having a memory cell including a first dielectric layer, a gate, a semiconductor layer, a first doped region, a second doped region and a charge storage layer is provided. The first dielectric layer is on the substrate. The gate includes a base portion on the first dielectric layer and a protruding portion disposed on the base portion and partially exposing the base portion. The semiconductor layer is conformally disposed on the gate, and includes a top portion over the protruding portion, a bottom portion over the base portion exposed by the protruding portion and a side portion located at a sidewall of the protruding portion and connecting the top and bottom portions. The first and second doped regions are respectively in the top and bottom portions. The side portion serves as a channel region. The charge storage layer is between the gate and the semiconductor layer.

BACKGROUND OF THE INVENTION

1. Field of Invention

The present invention relates to a memory structure and a fabricating method thereof, and more generally to a memory structure having a vertical channel and a fabricating method thereof.

2. Description of Related Art

A memory is a semiconductor device designed for storing information or data. As the functions of computer microprocessors become more and more powerful, programs and operations executed by software are increasing correspondingly. Consequently, the demand for high storage capacity memories is getting more. Among various types of memory products, a non-volatile memory such as an electrically erasable programmable read only memory (EEPROM) allows multiple-time data programming, reading and erasing operations, and the data stored therein can be retained even after the power of the memory is interrupted. With these advantages, EEPROM has become one of the most widely adopted memories for personal computers and electronic equipment.

In a typical EEPROM, a floating gate and a control gate are made of doped polysilicon. When the memory is programmed, the electrons injected into the floating gate uniformly distributes in the polysilicon floating gate. However, when defects exist in the tunnel oxide layer under the polysilicon floating gate, a leakage current is easily generated in the device, and the reliability of the device is decreased.

In order to solve the leakage problem of the EEPROM, one known method is to adopt a charge trapping layer including a non-conductive material instead of the polysilicon floating gate. Another advantage obtained from replacing the polysilicon floating gate with the charge trapping layer is that the electrons are only stored in a portion of the charge trapping layer adjacent to the source region or drain region while the device is programmed. Therefore, during the programming process, the voltages can be applied to the source region and the control gate respectively. Hence, the electrons are stored in a portion of the charge trapping layer near the source region with a form of Gaussian distribution. Alternatively, the voltages can be applied to the drain region and the control gate respectively. Hence, the electrons are stored in a portion of the charge trapping layer near the drain region with a form of Gaussian distribution. In the other words, there are two storage regions in the charge trapping layer. Consequently, by changing the voltage applied in the control gate and the source/drain regions at the two sides thereof, two groups of electrons with Gaussian distribution, one group of electrons with Gaussian distribution, or no electrons can be present in a single charge trapping layer. Accordingly, the flash memory replacing the floating gate with the charge trapping layer can be written into a single memory cell in four states and is a flash memory with a 2 bits/cell storage.

However, the dimension of a non-volatile memory is scaled down as the degree of integration of a semiconductor device is increased. When the channel length is shortened, a punch through leakage current easily occurs between the source and drain regions, thereby lowering the performance of the memory device. In addition, as the source and drain regions are scaled down, the secondary hot electrons produced from the programming of the selected memory can not be blocked by the source and drain regions, and thus, the secondary hot electrons would inject into the adjacent memory cells. As a result, program disturbance is generated, and the reliability of the memory device is reduced.

SUMMARY OF THE INVENTION

Accordingly, an embodiment of the present invention provides a memory structure to suppress the generation of a punch through leakage current.

Another embodiment of the present invention provides a fabricating method of a memory structure. The formed memory structure can prevent program disturbance caused by the second hot electrons.

An embodiment of the present invention provides a memory structure including a memory cell, and the memory cell includes a first dielectric layer, a gate, a semiconductor layer, a first doped region, a second doped region and a charge storage layer. The first dielectric layer is disposed on a substrate. The gate includes a base portion and a protruding portion. The base portion is disposed on the first dielectric layer. The protruding portion is disposed on the base portion and exposes a portion of the base portion. The semiconductor layer is conformally disposed on the gate and includes a top portion, a bottom portion and a side portion. The top portion is disposed over the protruding portion. The bottom portion is disposed over the base portion exposed by the protruding portion. The side portion is disposed at a sidewall of the protruding portion and connects the top portion and the bottom portion. The first doped region and the second doped region are respectively disposed in the top portion and the bottom portion, wherein the side portion serves as a channel region. The charge storage layer is disposed between the gate and the semiconductor layer.

According to an embodiment of the present invention, the material of the first dielectric layer includes silicon oxide.

According to an embodiment of the present invention, the material of the gate includes doped polysilicon.

According to an embodiment of the present invention, the material of the semiconductor layer includes polysilicon.

According to an embodiment of the present invention, the charge storage layer includes a second dielectric layer, a third dielectric layer and a charge trapping layer. The second dielectric layer is disposed on the gate. The third dielectric layer is disposed on the second dielectric layer. The charge trapping layer is disposed between the second dielectric layer and the third dielectric layer.

According to an embodiment of the present invention, the material of each of the second dielectric layer and the third dielectric layer includes silicon oxide.

According to an embodiment of the present invention, the material of the charge trapping layer includes a high-K material or a nano-crystal material.

According to an embodiment of the present invention, when the memory structure includes a plurality of memory cells, adjacent gates on the same word line are connected to each other through the base portion.

According to an embodiment of the present invention, when the memory structure includes a plurality of memory cells, two adjacent side portions located between two adjacent protruding portions are disposed separately from each other.

According to an embodiment of the present invention, the memory structure further includes a plurality of contacts respectively connected to the first doped region and the second doped region.

Another embodiment of the present invention provides a fabricating method of a memory structure including the following steps. A first dielectric layer is formed on a substrate. A word line is formed on the first dielectric layer, and the word line includes a base portion and a plurality of protruding portions. The base portion is disposed on the first dielectric layer. The protruding portions are disposed on the base portion and expose a portion of the base portion. A charge storage layer is conformally formed on the word line. A semiconductor layer is conformally formed on the charge storage layer, and the semiconductor layer includes a plurality of top portions, a plurality of bottom portions and a plurality of side portions. The top portions are respectively disposed over the protruding portions. The bottom portions are respectively disposed over the base portion exposed by the protruding portions. The side portions are respectively disposed at sidewalls of the protruding portions and connect the top portions and the bottom portions, wherein two adjacent side portions located between two adjacent protruding portions are disposed separately from each other. A first doped region is formed in each top portion and a second doped region is formed in each bottom portion, wherein each side portion serves as a channel region.

According to another embodiment of the present invention, the method of forming the first dielectric layer includes performing a chemical vapour deposition (CVD) process.

According to another embodiment of the present invention, the method of forming the word line includes forming a word line material layer on the first dielectric layer; and removing a portion of the word line material layer.

According to another embodiment of the present invention, the method of forming the charge storage layer includes forming a second dielectric layer on the word line; forming a charge trapping layer on the second dielectric layer; and forming a third dielectric layer on the charge trapping layer.

According to another embodiment of the present invention, the method of forming the semiconductor layer includes forming an amorphous silicon layer with an amorphous silicon process; and performing a solid phase crystallization (SPC) process to the amorphous silicon layer.

According to another embodiment of the present invention, the method of forming the semiconductor process includes performing a CVD process.

According to another embodiment of the present invention, the method of forming the first doped regions and the second doped regions includes performing an ion implantation process.

According to another embodiment of the present invention, the ion implantation process includes a vertical ion implantation process.

According to another embodiment of the present invention, each protruding portion and the base portion form a gate.

According to another embodiment of the present invention, the fabricating method further includes forming a plurality of contacts respectively connected to the first doped regions and the second doped regions.

In view of the above, in the memory structure of an embodiment of the present invention, a channel region is vertical and has a longer channel length, so that the punch through phenomenon can be effectively suppressed, and a punch through leakage current can be further avoided.

Besides, in the fabricating method of the memory structure of an embodiment of the present invention, two adjacent side portions located between two adjacent protruding portions are disposed separately from each other. Accordingly, the secondary hot electrons produced from the programming of the selected memory can be prevented from injecting into the adjacent memory cells, so as to avoid program disturbance caused by the second hot electrons.

DESCRIPTION OF EMBODIMENTS

FIGS. 1A to 1Eschematically illustrate cross-sectional views of a fabricating method of a memory structure according to an embodiment of the present invention.

Referring toFIG. 1A, a dielectric layer102is formed on a substrate100. The dielectric layer102serves as a buffer dielectric layer for separating the substrate100from the subsequently formed word line on the substrate100. The material of the dielectric layer102is silicon oxide, for example. The method of forming the dielectric layer102includes performing a chemical vapour deposition (CVD) process.

Thereafter, a word line material layer104is formed on the dielectric layer102. The word line material layer104includes a conductive material, such as doped polysilicon. The method of forming the word line material layer104includes performing a CVD process.

Afterwards, a patterned photoresist layer106is formed on the word line material layer104. The method of forming the patterned photoresist layer106includes performing a photolithography process.

Referring toFIG. 1B, a portion of the word line material layer104is removed by using the patterned photoresist layer106as a mask, so as to form a word line108on the dielectric layer102. The word line108includes a base portion110and a plurality of protruding portions112. The base portion110is disposed on the dielectric layer102. The protruding portions112are disposed on the base portion110and expose a portion of the base portion110. The method of removing the portion of the word line material layer104includes performing a dry etching process. In addition, the word line108is, for example, formed by the said method, but the present invention is not limited thereto.

The patterned photoresist layer106is then removed. The patterned photoresist layer106is removed by a dry photoresist removing method, for example.

Referring toFIG. 1C, a dielectric layer114is formed on the word line108. The material of the dielectric layer114is silicon oxide, for example. The method of forming the dielectric layer114includes performing a CVD process.

Thereafter, a charge trapping layer116is formed on the dielectric layer114. The material of the charge trapping layer116includes a high-K material or a nano-crystal material. The high-K material is silicon nitride, for example. The nano-crystal material includes nano-crystals of silicon, germanium or other metal. The method of forming the charge trapping layer116includes performing a CVD process.

Afterwards, a dielectric layer118is formed on the charge trapping layer116. The material of the dielectric layer118is silicon oxide, for example. The method of forming the dielectric layer118includes performing a CVD process.

In such manner, a charge storage layer120including the dielectric layer114, the charge trapping layer116and the dielectric layer118is conformally formed on the word line108. In addition, the charge storage layer120is, for example, formed by the said method, but the present invention is not limited thereto.

Referring toFIG. 1D, a semiconductor layer122is conformally formed on the charge storage layer120, and the semiconductor layer122includes a plurality of top portions124, a plurality of bottom portions126and a plurality of side portions128. The top portions124are respectively disposed over the protruding portions112. The bottom portions126are respectively disposed over the base portion110exposed by the protruding portions112. The side portions128are respectively disposed at sidewalls of the protruding portions112and connect the top portions124and the bottom portions126. The charge storage layer120and the semiconductor layer122are sequentially and conformally formed over the word line108having the protruding portions112, so that the semiconductor layer122can have recesses130between two adjacent side portions128between two adjacent protruding portions122, and thus, two adjacent side portions128located between two adjacent protruding portions122are disposed separately from each other.

Further, the material of the semiconductor layer122is polysilicon, for example. The method of forming the semiconductor layer122includes forming an amorphous silicon layer with an amorphous silicon process, and then performing a solid phase crystallization (SPC) process to the amorphous silicon layer. In another embodiment, the method of forming the semiconductor layer122includes performing a CVD process.

Next, a doped region132is formed in each top portion124and a doped region134is formed in each bottom portion126, wherein each side portion128serves as a channel region136. The method of forming the doped regions132and134includes performing an ion implantation process, such as a vertical ion implantation process. Generally speaking, the doped regions134formed by the ion implantation process are formed in the bottom portions126exposed by the recesses130. However, the doped regions134can further diffuse into the bottom portions126below the side portions128by performing an additional thermal process or by a thermal process in the subsequent process.

Referring toFIG. 1E, a dielectric layer142is formed on the semiconductor layer122. The material of the dielectric layer142is silicon oxide, for example. The method of forming the dielectric layer142includes performing a CVD process.

Thereafter, contacts144are formed in the dielectric layer142, and the contacts144are connected to the doped regions132and the doped regions134respectively. The material of the contacts144is conductive material, such as tungsten. The method of forming the contacts144includes forming a plurality of openings in the dielectric layer142, forming a conductive material layer to fill up the openings, and then removing the conductive material layer outside the openings.

In view of the said embodiment, each channel region136formed from the corresponding side portion128is a vertical channel region, so that the channel regions136can be designed to have a longer channel length. Therefore, the punch through phenomenon can be effectively suppressed, and a punch through leakage current can be further avoided.

Besides, two adjacent side portions128located between two adjacent protruding portions122are disposed separately from each other, and thus, the secondary hot electrons produced from the programming of the selected memory can be prevented from injecting into the adjacent memory cells, so as to avoid program disturbance caused by the second hot electrons and further enhance the reliability of the memory device.

In the following, the memory structure of an embodiment of the present invention is illustrated withFIG. 1E.

The memory structure includes a plurality of memory cells138, and each memory cell includes a dielectric layer102, a gate140, a semiconductor layer122, a doped region132, a doped region134and a charge storage layer120. The dielectric layer102is disposed on a substrate100. The gate140is a portion of the word line108and includes a base portion110and a protruding portion112. The base portion110is disposed on the dielectric layer102. Besides, the adjacent gates140on the same word line108are connected to each other through the base portion110. The protruding portion112is disposed on the base portion110and exposes a portion of the base portion110. The semiconductor layer122is conformally disposed on the gate140and includes a top portion124, a bottom portion126and a side portion128. The top portion124is disposed over the protruding portion112. The bottom portion126is disposed over the base portion110exposed by the protruding portion112. The side portion128is disposed at a sidewall of the protruding portion112and connects the top portion124and the bottom portion126. The doped region132and the doped region134are respectively disposed in the top portion124and the bottom portion126. The doped region132and the doped region134can respectively serve as a source region and a drain region (i.e. bit line). The side portion128serves as a channel region. The charge storage layer120is disposed between the gate140and the semiconductor layer122. The charge storage layer120includes a dielectric layer114, a dielectric layer118and a charge trapping layer116. The dielectric layer114is disposed on the gate140. The dielectric layer118is disposed on the dielectric layer114. The charge trapping layer116is disposed between the dielectric layer114and the dielectric layer118. When the memory structure includes a plurality of memory cells138, two adjacent side portions128located between two adjacent protruding portions112are disposed separately from each other. The memory structure can further optionally include at least one of the dielectric layer142and the contacts144. The contacts144are disposed in the dielectric layer142and respectively connected to the doped region132and the doped region134. Moreover, the materials, forming methods and functions of the components of the memory structure have been described in the said embodiment, so that the details are not iterated herein.

In summary, the said embodiment at least has the following advantages:

The memory structure of the said embodiment can suppress the generation of a punch through leakage current.

The memory structure fabricated by the method of the said embodiment can prevent program disturbance caused by the second hot electrons.

The present invention has been disclosed above in the preferred embodiments, but is not limited to those. It is known to persons skilled in the art that some modifications and innovations may be made without departing from the spirit and scope of the present invention. Therefore, the scope of the present invention should be defined by the following claims.