Semiconductor package with bonding wires of reduced loop inductance

A semiconductor package includes a semiconductor device including a plurality of signal pads and a plurality of auxiliary pads which are alternatively arranged in a predetermined direction, and a package board including a plurality of signal bond fingers, a plurality of first power supply voltage bond fingers, and a plurality of second power supply voltage bond fingers. The signal pads are connected respectively to the signal bond fingers by first wires. The first power supply voltage bond fingers and the second power supply voltage bond fingers are connected respectively to the auxiliary pads by second wires. The first wires are disposed between those of the second wires which are connected to the first power supply voltage bond fingers and those of the second wires which are connected to the second power supply voltage bond fingers.

This application is based upon and claims the benefit of priority from Japanese Patent Application No. 2010-252913 filed on Nov. 11, 2010, the content of which is incorporated by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a semiconductor package including a semiconductor device mounted on a package board.

2. Description of the Related Art

The structure of a semiconductor package including a semiconductor device will be described below. First, the structure of the semiconductor device will be described below.FIG. 1of the accompanying drawings is a block diagram showing a structural example of semiconductor device10according to the related art. It is assumed that semiconductor device10is a DRAM (Dynamic Random Access Memory).

As shown inFIG. 1, semiconductor device10includes a plurality of memory cell blocks20-1through20-n(n represents an integer which is 1 or greater) each including a plurality of memory elements, CA pad array31including a plurality of terminals to which address signals and command signals are input from an external source, DQ pad array32including a plurality of terminals which send data to and receive data from an external source, column decoder41and row decoder42for specifying a memory element according to an address signal, and data input/output control circuit45for controlling the inputting and outputting of data.

An address signal is a signal for specifying either one of the memory elements. A command signal is a signal for indicating the writing of data into or the reading of data from the memory elements.

CA pad array31includes command signal pads to which command signals are input from the external source and address signal pads to which address signals are input from the external source. The address signal pads and the command signal pads will be hereinafter collectively referred to as signal pads.

DQ pad array32includes a plurality of data pads which send and receive data. Each of CA pad array31and DQ pad array32includes a power supply voltage pad to which a power supply voltage (Vdd) is applied from an external source and a ground potential pad to which a ground potential (Vss or Gnd) is applied from an external source. The power supply voltage pad will be hereinafter referred to as a Vdd pad, and the ground potential pad as a Vss pad.

InFIG. 1, a receiver circuit for amplifying signals input from an external source and an input/output circuit for amplifying data which are sent to and received from an external source are omitted from illustration.

FIG. 2of the accompanying drawings is a cross-sectional view showing a structural example of a semiconductor package including the semiconductor device shown inFIG. 1.

As shown inFIG. 2, semiconductor device10is mounted on package board50and covered with resin body56. Pads200disposed on the upper surface of semiconductor device10are connected to bond fingers210on package board50by bonding wires (hereinafter simply referred to as “wires”)220. Pads200are one type of the pads included in CA pad array31or DQ pad array32. Bond fingers210are one type of electrically conductive pads which are electrically connected to pads200on semiconductor device10by wires220, and are connected to solder balls51by interconnects52and via plugs54.

Of interconnects52disposed on package board50, the interconnects connected to the command signal pads of CA pad array31are referred to as command interconnects, the interconnects connected to the address signal pads of CA pad array31as address interconnects, and the interconnects connected to the data pads of DQ pad array32as data interconnects.

An example of stacked semiconductor package which is of a PoP (Package on Package) structure with a plurality of semiconductor devices mounted on a printed wiring board is disclosed in JP 2009-38142A. An example of technology relative to a redistribution layer (RDL) referred to in JP 2009-38142A is disclosed in JP 2005-123291A.

FIG. 3of the accompanying drawings is a plan view showing connections between pads on a semiconductor device and bond fingers on a package board.FIG. 3shows a portion of CA pad array31.

As shown inFIG. 3, bond fingers211through216are disposed on package board50in a vertical array as shown. Vdd pad201, address signal pads202through205, and Vss pad206are disposed on semiconductor device10parallel to the pad array of bond fingers211through216.

“V” noted on Vdd pad201and bond finger211indicates that they are the pad and the bond finger to which Vdd is applied. “G” noted on Vss pad206and bond finger216indicates that they are the pad and the bond finger to which Vss is applied. “A1” through “A4” noted on address signal pads202through205and bond fingers211through215indicate that they are the pads and the bond fingers to which address signals A1through A4are transmitted.

Each of address signal pads202through205is connected through interconnects to amplifiers in the receiver circuit.

InFIG. 3, only address signal pads for address signals A1through A4are illustrated, and address signal pads for address signals other than address signals A1through A4and command signal pads are omitted from illustration. For example, address signal pads (not shown) for address signals other than address signals A1through A4and command signal pads (not shown) are disposed below Vss pad206shown inFIG. 3.

Vdd pad201, address signal pads202through205, and Vss pad206are arranged in a single array at a spaced interval between adjacent ones thereof. Bond fingers211through216are disposed at respective vertical positions aligned with Vdd pad201, address signal pads202through205, and Vss pad206, respectively. Vdd pad201and bond finger211are connected to each other by wire221. Vss pad206and bond finger216are connected to each other by wire226. Address signal pads202through205are connected to respective bond fingers212through215by respective wires222through225.

In one array of pads, the ratio of the number of successive signal pads to a Vss pad or a Vdd pad is defined as “SG ratio” which means the ratio between signals and ground (or power supply). In the structural example shown inFIG. 3, since there is one Vdd pad or Vss pad for four address signal pads, the SG ratio is 4:1. The SG ratio of the numbers of bond fingers which connect these pads to the bond fingers is also 4:1. The SG ratio is similarly defined for address signal pads and wires which are not illustrated.

According to the PoP structure, the command interconnects and the address interconnects often extend longer parallel to the principal surface of package board50than the data interconnects due to the interconnect density and interconnect limitations. Furthermore, since each of wires221through226shown inFIG. 3has a parasitic inductance as shown inFIG. 4of the accompanying drawings, and the SG ratio of the CA pad array is 4:1 as described above with reference toFIG. 3, which is smaller than the SG ratio of the DQ pad array, the wires have a low power feeding capability and each develop a parasitic inductance between itself and an adjacent wire. As the bop inductance between S (signal) and G (ground) wires is large, the wires are subject to large noise and jitter.

According to the LPDDR2 (Low Power Double Data Rate 2) standards, since address interconnects transfer signals at a double rate, it is important to reduce such noise and jitter for better signal quality.

SUMMARY

In one embodiment, there is provided a semiconductor package that includes a semiconductor device including a plurality of signal pads and a plurality of auxiliary pads which are alternatively arranged in a predetermined direction, and a package board including a plurality of signal bond fingers arranged in the predetermined direction for supplying signals to the signal pads, a plurality of first power supply voltage bond fingers arranged in the predetermined direction for supplying a first power supply voltage to the auxiliary pads, and a plurality of second power supply voltage bond fingers arranged in the predetermined direction for supplying a second power supply voltage to the auxiliary pads, the semiconductor device being mounted on the package board. The signal pads are connected respectively to the signal bond fingers by first wires. The first power supply voltage bond fingers and the second power supply voltage bond fingers are connected respectively to the auxiliary pads by second wires. The first wires are disposed between those of the second wires which are connected to the first power supply voltage bond fingers and those of the second wires which are connected to the second power supply voltage bond fingers.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Semiconductor packages according to exemplary embodiments of the present invention will be described below. In each of the exemplary embodiments to be described below, it is assumed that a semiconductor device incorporated in the semiconductor package is a DRAM.

The structure of a semiconductor package according to the first exemplary embodiment will be described below.FIG. 5is a plan view illustrative of a structural example of a central portion of the semiconductor package according to the first exemplary embodiment.

FIG. 5shows connections between pads on semiconductor device12and bond fingers on package board60. It is assumed that horizontal directions inFIG. 5are referred to as X-axis directions and vertical directions as Y-axis directions. Semiconductor device12has the structure shown inFIG. 1. The structural details shown inFIG. 1will not be described below, and those details of semiconductor device12which are different from those shown inFIG. 3will be described below.

Semiconductor device12is mounted on package board60. InFIG. 5, a portion of package board60is shown separately to clearly illustrate connections between pads on semiconductor device12and bond fingers on package board60. A planar portion of semiconductor device12in the vicinity of the pads thereon is also shown separately inFIG. 5.

Vdd pads102through104serve as auxiliary pads for a power supply voltage, and Vss pads105through107as auxiliary pads for a ground potential.

Pad array141and pad array142extend parallel to the Y-axis directions, and are disposed in different directions along the X-axis directions. Pad array142is positioned more closely to an outer peripheral edge of semiconductor device12than pad array141. In pad array141, Vdd pad201, address signal pads202through205, and Vdd pad206are successively arranged at a spaced interval between adjacent ones thereof along the Y-axis directions. In pad array142, the Vdd pads and the Vss pads are alternately arranged at a spaced interval between adjacent ones thereof along the Y-axis directions.

Vdd pads102through104and Vss pads105through107of pad array142are fabricated according the RDL technology. Furthermore, interconnects which connect Vdd pads102through104to Vdd pad201and interconnects which connect Vss pads105through107to Vss interconnect136of receiver circuit47are also fabricated according the RDL technology. Interconnects fabricated according the RDL technology will hereinafter be referred to as RDL interconnects. InFIG. 5, the RDL interconnects are indicated by broken lines.

Vdd pads102through104are connected to Vdd pad201by RDL interconnect131. Vss pads105through107are connected to each other by RDL interconnect132. RDL interconnect132is connected to Vss interconnect136of receiver circuit47by RDL interconnects133. Since the auxiliary pads for the power supply voltage are connected to each other by RDL interconnect131, the voltage levels of the wires connected respectively to the auxiliary pads for the power supply voltage can be held more stably. This also holds true for the wires connected respectively to the auxiliary pads for the ground potential.

Package board60includes bond fingers112through117in addition to bond fingers211through216. Bond fingers211through216and bond fingers112through117are fabricated as printed interconnects. Bond fingers211through216are arrayed in bond finger array151, and bond fingers112through117as bond finger array152. In bond finger array151, bond fingers211through216are successively arranged at a spaced interval between adjacent ones thereof along the Y-axis directions. In bond finger array152, bond fingers115,112,116,113,117,114are alternately arranged at a spaced interval between adjacent ones thereof along the Y-axis directions.

“V”, “G”, and “A1” through “A4” noted on the pads and the bond fingers shown inFIG. 5have the same meanings as those described above with reference toFIG. 3, and will not be described below. Bond fingers211,112through114serve as power supply voltage bond fingers for supplying a power supply voltage to semiconductor device12, and bond fingers216,115through117as ground potential bond fingers for supplying a ground potential to semiconductor device12. Bond fingers212through215serve as signal bond fingers for supplying address signals to semiconductor device12. InFIG. 5, address signal pads for address signals other than address signals A1through A4and command signal pads are also omitted from illustration.

The positions in the Y-axis directions of the auxiliary pads of pad array142on semiconductor device12will be compared with the positions of the pads of pad array141below. Vss pad105is disposed between Vdd pad201and address signal pad202. Vdd pad102is disposed between address signal pad202and address signal pad203. Vss pad106is disposed between address signal pad203and address signal pad204. Vdd pad103is disposed between address signal pad204and address signal pad205. Vss pad107is disposed between address signal pad205and Vss pad206. Vdd pad104is disposed below Vss pad206inFIG. 5.

The positions in the Y-axis directions of the bond fingers of bond finger array152on package board60will be compared with the positions of the bond fingers of bond finger array151below. Bond finger115is disposed between bond finger211and bond finger212. Bond finger112is disposed between bond finger212and bond finger213. Bond finger116is disposed between bond finger213and bond finger214. Bond finger113is disposed between bond finger214and bond finger215. Bond finger117is disposed between bond finger215and bond finger216. Bond finger114is disposed below bond finger216inFIG. 5.

The pads on semiconductor device12and the bond fingers on package board60are interconnected as follows: Vdd pads102through104are connected respectively to bond fingers112through114by respective wires122through124. Vss pads105through107are connected respectively to bond fingers115through117by respective wires125through127. Vdd pad201is connected to bond finger211by wire221. Vss pad206is connected to bond finger216by wire226. Address signal pads202through205are connected respectively to bond fingers212through215by respective wires222through225.

Since the Vss pads or Vdd pads as auxiliary pads are disposed between the address signal pads in the Y-axis directions, the signal wires as wires connected to the signal pads and the Vdd wires as wires to which Vdd is applied or the Vss wires as wires to which Vss is applied are alternately arranged in the Y-axis directions. Therefore, the SG ratio is improved to 1:1.

With the semiconductor package according to the present exemplary embodiment, since the SG ratio is improved and the Vdd wires or the Vss wires are disposed next to the signal wires, the loop inductance between S and G wires can be reduced by mutual inductance for faster signal transmission.

The cross-sectional structures of central portions of the semiconductor device according to the present exemplary embodiment will be described below.

FIGS. 6A through 7Bare cross-sectional views showing structural examples of the semiconductor device shown inFIG. 5.FIG. 6Ais a cross-sectional view showing a structural example of Vdd pad201, andFIG. 6Bis a cross-sectional view showing another structural example of Vdd pad201.

As shown inFIG. 6A, semiconductor device12includes circuit forming region72in which semiconductor elements and interconnects are disposed in the vicinity of the surface of semiconductor substrate70. Insulating film74is disposed on semiconductor substrate70. Vdd pad201is disposed on an electrically conductive layer on insulating film74. A multilayer interconnect is disposed between circuit forming region72and the electrically conductive layer on which Vdd pad201is disposed. For the sake of brevity, the multilayer interconnect is omitted from the illustrations in6A through7B, and a detailed description about the multilayer interconnect is omitted.

As shown inFIG. 6A, polyimide film76is disposed on insulating film74as a protective film covering the electrically conductive layer on which Vdd pad201is disposed. Polyimide film76has an opening defined therein through which the upper surface of Vdd pad201is partly exposed for wire bonding between Vdd pad201and bond finger211on package board60.

RDL interconnect131and polyimide film78are formed on polyimide film76according the RDL technology. RDL interconnect131is formed above the electrically conductive layer on which Vdd pad201is disposed. Polyimide film78has opening77defined therein through which RDL interconnect131is partly exposed. Opening77serves the same purpose as the opening defined in polyimide film76, and wire221is connected to RDL interconnect131through opening77. Wire221is connected to Vdd pad201by RDL interconnect131.

Vdd pad201and wire221may be connected to each other by a structure other than the structure shown inFIG. 6A. As shown inFIG. 6B, a Vdd pad may be added to the position of pad array421.

According to the structural example shown inFIG. 6B, polyimide film78has opening79defined therein other than opening77. Wire221is connected to RDL interconnect131through opening79. Wire221is connected to Vdd pad201by RDL interconnect131. The structure shown inFIG. 6Bmay be applied to Vss pad206. Since the Vdd pad in opening79is closer to bond finger211than Vdd pad201, the structure shown inFIG. 6Bmay be made shorter than the structure shown inFIG. 6A.

The cross-sectional structures of other RDL interconnects will be described below with reference toFIGS. 7A and 7B.FIG. 7Ais a cross-sectional view showing a structural example of Vss pad105which is one of the auxiliary pads, andFIG. 7Bis a cross-sectional view showing a structural example of portion X1inFIG. 5.

As shown inFIG. 7A, RDL interconnect132is disposed on polyimide film76. RDL interconnect132is covered with polyimide film78having an opening defined therein which corresponds to Vss pad105. Wire125is connected to Vss pad105. The structure shown inFIG. 7Amay be applied to not only Vss pad105, but also Vss pads106,107, and Vdd pads102through104.

The structural example of portion X1inFIG. 5will be described below. As shown inFIG. 7B, RDL interconnect133is disposed on polyimide film76, and covered with polyimide film78.FIG. 7Balso shows an opening corresponding to Vss pad102, wire122, and RDL interconnect131. RDL interconnect133is connected to Vss interconnect136through an opening defined in polyimide film76. Portion X1of Vss interconnect136may be formed such that the area of its planar pattern is equal to or greater than the area of Vdd pad201to increase the area of the opening in polyimide film76, thereby reducing the contact resistance of RDL interconnect133and Vss interconnect136.

By using the RDL technology as described above, it is possible to form RDL interconnects and auxiliary pads above the electrically conductive layer on which Vdd pad201is disposed, even over circuit forming region72and a region in which a multilayer interconnect, not shown, is formed.

The semiconductor device according to the present exemplary embodiment makes it possible to improve the SG ratio of wires to a DRAM chip by using RDL interconnects. As a result, the loop inductance between S and G wires is reduced for faster signal transmission, as described above.

A semiconductor package according to the second exemplary embodiment is of a structure wherein the mutual inductance between signal wires and Vdd wires is stronger than with the semiconductor package according to the first exemplary embodiment.

The structure of the semiconductor package according to the second exemplary embodiment will be described below.FIG. 8is a plan view illustrative of a structural example of a central portion of the semiconductor package according to the second exemplary embodiment. As withFIG. 5, it is assumed that horizontal directions inFIG. 8are referred to as X-axis directions and vertical directions as Y-axis directions. Semiconductor device14shown inFIG. 8includes RDL interconnects indicated by the broken lines.

Semiconductor device14shown inFIG. 8has the structure shown inFIG. 1. The structural details shown inFIG. 1will not be described below, and those details of semiconductor device14which are different from those shown inFIG. 3or the first exemplary embodiment will be described below.

According to the second exemplary embodiment, the auxiliary pads of pad array142on semiconductor device12shown inFIG. 5are divided into pad array143and pad array144on semiconductor device14. Pad array141,142,143extend parallel to the Y-axis directions, and are disposed in different directions along the X-axis directions. Pad array144is positioned more closely to an outer peripheral edge of semiconductor device14than pad array143.

In pad array143, Vdd pads102through104are successively arranged at a spaced interval between adjacent ones thereof along the Y-axis directions. Vdd pads102through104are connected to each other by RDL interconnect131. In pad array144, Vss pads105through107are successively arranged at a spaced interval between adjacent ones thereof along the Y-axis directions. Vss pads105through107are connected to each other by RDL interconnect132.FIG. 8shows that Vss pads105through107are also connected to each other by RDL interconnect134. However, RDL interconnect134may be dispensed with.

RDL interconnect132is connected to Vss interconnect136by RDL interconnect133. The connection between RDL interconnect133and Vss interconnect136is of the same structure as the connection described with reference toFIG. 7B, and will not be described in detail below. InFIG. 8, RDL interconnect133and RDL interconnect131are shown as crossing each other. They can be electrically insulated from each other by applying the multilayer interconnect technology to RDL interconnects. For example, in the structure shown inFIGS. 6A and 6B, RDL interconnect133may be formed on polyimide film78which covers RDL interconnect131, and may be covered with another polyimide film.

The layout of the bond fingers of each of bond finger arrays151,152on package board60is the same as the layout according to the first exemplary embodiment, and will not be described in detail below.

The positions in the Y-axis directions of the auxiliary pads of semiconductor device14will be compared with the positions of the pads of pad array141below. Vdd pad102is disposed between Vdd pad202and address signal pad203. Vss pad106is disposed between address signal pad203and address signal pad204. Vdd pad103is disposed between address signal pad204and address signal pad205. Vss pad107is disposed between address signal pad205and Vss pad206. Vdd pad104is disposed below Vss pad206inFIG. 8.

With respect to the connections between the pads and the bond fingers, the pads and the bond fingers are connected by wires depending on the types of the pads and the types of the bond fingers, in the same manner as with the first exemplary embodiment. According to the present exemplary embodiment, since pad array143is positioned more remotely from bond finger arrays151,152than pad array141, wires122through124are longer than those according to the first exemplary embodiment. Therefore, wires122,123extend along wires222through225over a greater distance, making it more effective to increase the reduction in the loop inductance.

According to the present exemplary embodiment, since the Vss pads or Vdd pads as auxiliary pads are disposed between the address signal pads in the Y-axis directions, the signal wires and the Vdd wires or the Vss wires are alternately arranged in the Y-axis directions. Therefore, the SG ratio is improved to 1:1.

According to the present exemplary embodiment, furthermore, as the mutual inductance between the signal wires and the Vdd wires is more effective, the loop inductance between S and G wires is reduced.

A semiconductor package according to the third exemplary embodiment is of a structure wherein there are greater intervals at which address signal pads are spaced than the first exemplary embodiment.

The structure of the semiconductor package according to the third exemplary embodiment will be described below.FIG. 9is a plan view illustrative of a structural example of a central portion of the semiconductor package according to the third exemplary embodiment. As withFIG. 5, it is assumed that horizontal directions inFIG. 9are referred to as X-axis directions and vertical directions as Y-axis directions.

Semiconductor device19shown inFIG. 9has the structure shown inFIG. 1. The structural details shown inFIG. 1will not be described below, and those details of semiconductor device19which are different from those shown inFIG. 3or the first exemplary embodiment or the second exemplary embodiment will be described below.

Pad array141includes, in addition to address signal pads202through205, Vdd pad201, and Vdd pad206, Vdd pads102,103and Vss pads105through107as auxiliary pads. Each of address signal pads202through205is disposed between a Vdd pad and a Vss pad as auxiliary pads. Vdd pads102,103are connected to bond fingers112,113by wires122,123. Vss pads105through107are connected to bond fingers115through117by wires125through127.

With the above arrangement, any one of wires222through225by which address signal pads202through205are connected respectively to bond fingers212through215is disposed between a wire connected to a power supply voltage bond finger and a wire connected to a ground potential bond finger.

The present exemplary embodiment is effective in the case where, with respect to the layout of the auxiliary pads, there is sufficient room between the signal pads, but there is no sufficient room between the signal pads and the outer peripheral edge of semiconductor device19.

In the present exemplary embodiment, the auxiliary pads are not connected by RDL interconnects. However, the auxiliary pads may be connected by RDL interconnects which are provided in the same manner as the arrangement shown inFIG. 5.

In the present exemplary embodiment, a single pad array is disposed in the vicinity of the outer peripheral edge of semiconductor device19near package board60. However, if there is sufficient room between the bond fingers on package board60, then a single bond finger array may be disposed on package board60, as with pad array141shown inFIG. 9. In such a case, an address signal bond finger is disposed between a power supply voltage bond finger and a ground potential bond finger.

The present example is concerned with a semiconductor package having a PoP structure in which two semiconductor devices are stacked on a package board.

The structure of the semiconductor package according to the present example will be described below.FIG. 10is a plan view of the semiconductor package according to the present example, andFIG. 11is a side sectional view of the semiconductor package according to the present example. InFIGS. 10 and 11, a resin body which covers semiconductor chips is omitted from illustration. It is assumed that horizontal directions inFIG. 10are referred to as X-axis directions, vertical directions as Y-axis directions, and directions perpendicular to the principal surface of package board62as Z-axis directions.

As shown inFIG. 11, semiconductor chip16aand semiconductor chip16bare successively stacked on package board62. Each of semiconductor chips16a,16bis a DRAM chip. As shown inFIGS. 10 and 11, semiconductor chip16bis displaced in an X-axis direction from a position in full alignment with semiconductor chip16a, in order to expose a pad area of semiconductor chip16a.

According to the present example, each of semiconductor chips16a,16bis of a structure in which the pads of pad array141and the pads of pad array142on semiconductor device12according to the first exemplary embodiment are aligned with each other with respect to their positions in the Y-axis directions. For example, Vss pad206aof pad array141aand Vss pad105aof pad array142aon semiconductor chip16aare aligned with each other with respect to their positions in the Y-axis directions. On semiconductor chip16ashown inFIG. 10, the positions in the Y-axis directions of Vdd pad201aand Vss pad206aare opposite to those on semiconductor device12shown inFIG. 5. However, any one of the positions shown inFIGS. 5 and 10may be employed. This also holds true for semiconductor chip16b.

On semiconductor chip16a, a plurality of Vss pads are connected to each other by RDL interconnection132a, and a plurality of Vdd pads are connected to each other by RDL interconnect131a. These connections are also employed on semiconductor chip16b.

Package board62is similar to package board60according to the first exemplary embodiment except that bond finger arrays151,152are positionally switched around in the X-axis directions. On package board62, the positions in the Y-axis directions of bond fingers211,216of bond finger array151are aligned with those of Vdd pads201a,201band Vss pads206a,206bon semiconductor chips16a,16b.

On package board62, a plurality of ground potential bond fingers are connected to each other by interconnects, and a plurality of power supply voltage bond fingers are connected to each other by interconnects. Some of the ground potential bond fingers are connected to via plugs54.

Connections between the pads on semiconductor chips16a,16band the bond fingers on package board62will be described below.

Address signal bond fingers A1through A4of bond finger array151are connected respectively to address signal pads A1through A4on semiconductor chip16bby wires227. Address signal pads A1through A4on semiconductor chip16bare connected respectively to address signal pads A1through A4on semiconductor chip16aby wires228. With these connections, address signals sent from package board62are supplied through wires227to semiconductor chip16b, and then supplied through wires227, the address signal pad on semiconductor chip16b, and wires228to semiconductor chip16a.

Ground potential bond fingers G and power supply voltage bond fingers V of bond finger array152are connected respectively to the Vss pads and the Vdd pads of pad array142aon semiconductor chip16aby wires128. Vss pad206aon semiconductor chip16aand Vss pad105bon semiconductor chip16bare connected to each other by wire129. Vss pad201aon semiconductor chip16aand Vss pad104bon semiconductor chip16bare connected to each other by wire129.

With the above connections, a power supply voltage supplied from package board62is applied through wires128to semiconductor chip16a, and then is applied through wires128, the Vdd pads and RDL interconnect131aon semiconductor chip16a, and wires129to semiconductor chip16b. A ground potential supplied from package board62is applied through wires128to semiconductor chip16a, and then is applied through wires128, the Vss pads and RDL interconnect132aon semiconductor chip16a, and wires129to semiconductor chip16b.

As shown inFIG. 11, since wires227are connected to upper semiconductor chip16b, rather than lower semiconductor chip16a, wires227extend along a large arc. Furthermore, since bond finger array152is positioned more closely to the outer peripheral edge of semiconductor chip16athan bond finger array151, the distance between bond fingers of bond finger array152and the auxiliary pads of pad array142aon semiconductor chip16ais small which causes the arc of wires128to be smaller than the arc of wires227.

The arcs of wires227,128will be compared with each other as shown inFIG. 11. Portions of the arcs which extend from package board62to the highest points of the arcs are inclined to the X-axis by similar angles, and hence these two arcs are similar in shape to each other. Accordingly, the portions of wires227,218which rise from package board62extend parallel to each other while being electrically insulated from each other. The signal wires extend along the Vdd wires or the Vss wires in the Z-axis directions. In the present example, although the distance between the signal wires and the Vdd wires and the distance between the signal wires and the Vss wires are not completely the same as each other, at least the SG ratio is improved to a level better than 4:1.

According to the present example, the Vdd wires and the Vss wires are positioned as closely to the signal wires as possible to reduce the loop inductance between S and G wires on the semiconductor package on which two semiconductor chips are stacked.

Package board60shown inFIG. 5may also have the positions in the X-axis directions of bond finger arrays151,152switched around, as with those on package board62. In such a case, even though the pads of pad arrays141,142on semiconductor device12are aligned with each other with respect to their positions in the Y-axis directions, as with those on semiconductor chip16a, the signal wires and the Vdd wires or the Vss wires are held out of contact with each other, and the signal wires are positioned closely to the Vdd wires or the Vss wires in the Z-axis directions. Therefore, the present example offers the same advantages as the first exemplary embodiment.

The present example is concerned with another semiconductor package having a PoP structure in which two semiconductor devices are stacked on a package board.

The structure of the semiconductor package according to the present example will be described below. The structural details which are identical to those of Example 1 will not be describe below, and those details which are different from those of Example 1 will be described below.

FIG. 12is a plan view of the semiconductor package according to the present example.FIG. 13is a side sectional view of the semiconductor package according to the present example. InFIGS. 12 and 13, a resin body which covers semiconductor chips is omitted from illustration. It is assumed, as withFIG. 10, that horizontal directions inFIG. 12are referred to as X-axis directions, vertical directions as Y-axis directions, and directions perpendicular to the principal surface of package board62as Z-axis directions.

As shown inFIG. 13, semiconductor chip18aand semiconductor chip18bare successively stacked on package board62. Each of semiconductor chips18a,18bis a DRAM chip. As with Example 1, semiconductor chip18bis displaced in an X-axis direction from a position in full alignment with semiconductor chip18a, in order to expose a pad area of semiconductor chip18a.

According to the present example, semiconductor chip18ais of a structure in which the pads of pad array141aand the pads of pad array142aon semiconductor chip16aaccording to Example 1 have shifted with respect to their positions in the Y-axis directions. For example, Vss pad206aof pad array141aand Vss pad105aof pad array142aon semiconductor chip16ahave their centers of gravity shifted out of alignment with respect to their positions in the Y-axis directions. The center of gravity of a pad having a quadrangular shape refers to a point of intersection between two diagonal lines.

In the Y-axis directions, the center of gravity of each of address signal pads A1through A4of pad array141ais positioned between the centers of gravity of a Vss pad and a Vdd pad which are adjacent each other. In the example shown inFIG. 12, the center of gravity of each of address signal pads A1through A4is positioned intermediate between the centers of gravity of a Vss pad and a Vdd pad which are adjacent each other.

Semiconductor chip18bis of the same structure as semiconductor chip18adescribed above, and will not be described below.

Connections between the pads on semiconductor chips18a,18band the bond fingers on package board62will be described below.

In Example 1, the bond fingers of bond finger array151are connected to the pads of pad array141bon upper semiconductor ship16b. In the present example, however, the bond fingers of bond finger array151are connected to the pads of pad array141aon lower semiconductor ship18a.

Address signal bond fingers A1through A4of bond finger array151are connected respectively to address signal pads A1through A4on semiconductor chip18aby wires229. The other connections are the same as those of Example 1.

With these connections, address signals sent from package board62are supplied through wires229to semiconductor chip18a, and then supplied through wires229, the address signal pad on semiconductor chip18a, and wires228to semiconductor chip18b. A power supply voltage and a ground potential supplied from package board62to each of semiconductor chips18a,18bfollow the same routes as those of Example 1.

As shown inFIG. 13, since wires229are connected to lower semiconductor chip18a, wires229extend along an arc which is smaller than the arc of wires227shown inFIG. 11. As a result, the distance between wires229and wires128is smaller than the distance between wires227and wires128, thereby making it more effective to reduce the loop inductance caused by the Vdd wires and the Vss wires with respect to the signal wires.

As wires229are positioned more closely to wires128than wires227in the Z-axis directions, they may possibly be brought into contact with each other. According to the present example, however, since the center of gravity of each of the signal pads is positioned between the centers of gravity of two adjacent auxiliary pads in the Y-axis directions, wires229and wires128are positionally displaced away from each other in the Y-axis directions. As a result, wires229and wires128are prevented from coming into contact with each other. Furthermore, inasmuch as wires128connected to the Vdd pads and wires128connected to the Vss pads are disposed in sandwiching relation to wires229, the Vdd wires and the Vss wires extend along the signal wires in the Y-axis directions.

According to the present example, the signal pads and the auxiliary pads of the semiconductor package having the two stacked semiconductor chips are arranged in a staggering pattern to position the signal wires parallel to and between the Vdd wires and the Vss wires. As a consequence, the Vdd wires and the Vss wires are positioned more closely to the signal wires to reduce the loop inductance between S and G wires, than in the case of Example 1.

The layout of pads according to the present example may be applied to one from among Example 1, the first and second exemplary embodiments.

According to the present disclosure, since the bonding wires to which the power supply voltage is applied and the bonding wires to which the ground potential is applied are disposed closely to the bonding wires for transmitting signals, the loop inductance between S and G wires can be reduced for faster signal transmission. In each of these exemplary embodiments and examples, the power supply voltage corresponds to a first power supply voltage, and the ground potential corresponds to a second power supply voltage.