Circuit for detecting the disappearing of a periodic signal

A circuit for detecting the disappearing of a periodic input signal, the circuit including a frequency divider receiving the input signal, the frequency divider having two complementary outputs combined with a same reference signal of same frequency as the input signal by means of two respective similar logic gates, the output of a first one of the logic gates being connected to increment a first counter and to reset a second counter similar to the first one, and the output of the second logic gate being connected to increment the second counter and to reset the first counter, and a logic circuit generating a disappearing detection signal when any one of the two counters reaches a predetermined value.

FIELD OF THE INVENTION
 The present invention relates to a circuit for detecting the disappearing
 of a signal, especially of a periodic logic signal.
 BACKGROUND OF THE INVENTION
 Many electronic devices use for their operation one or several periodic
 logic signals, for example to synchronize a phase-locked loop or to be
 used as clock signals. For different reasons, the periodic input signal
 provided to a device may disappear and cause a malfunction of the device.
 Further, in some cases, when for example a CRT control device receives a
 periodic horizontal synchronization signal to generate control signals for
 the tube deviator, the disappearing of the horizontal synchronization
 signal can result in the generation of inappropriate control signals and
 the destruction of the deviator.
 When such periodic signals are compulsory for some devices, a conventional
 solution consists of very clearly specifying in the technical instructions
 of the devices which signals must imperatively be provided during
 operation to avoid damage.
 Although it is always possible to use this solution, it is preferable to
 detect the disappearing of the periodic logic input signal that can cause
 a serious malfunction and, as soon as this detection is achieved, to
 modify the device operation to avoid any risk of damage.
 Further, it is very important to be able to perform this detection very
 fast, to limit damage that may occur between the signal disappearing and
 the detection of this disappearing.
 SUMMARY OF THE INVENTION
 The present invention provides a circuit enabling fast detection of the
 disappearing of a signal, and in one embodiment, for detecting the
 cessation of a periodic logic input signal.
 The circuit for detecting the disappearing of a periodic input signal
 includes a frequency divider receiving the input signal, having two
 complementary inputs combined with a same reference signal of same
 frequency as the input signal by means of two respective similar logic
 gates, the output of a first one of the logic gates being connected to
 increment a first counter and to reset a second counter similar to the
 first one, and the output of the second logic gate being connected to
 increment the second counter and to reset the first counter, wherein a
 logic circuit generates a disappearing detection signal when any one of
 the two counters reaches a predetermined value.
 According to an embodiment of the invention, the frequency divider is a
 divider by two.
 According to an embodiment of the invention, the logic gates are AND gates.
 According to an embodiment of the invention, the counters are shift
 registers, each including three series-connected D flip-flops, and the
 logic circuit is an OR gate connected to the output of the third flip-flop
 of each of the two counters.

DETAILED DESCRIPTION OF THE INVENTION
 FIG. 1 shows a detection circuit 10 receiving a periodic logic input signal
 IN and a periodic logic reference signal REF having the same frequency as
 the input signal. Signal REF can for example be generated at the output of
 a phase-locked loop synchronized on signal IN. The phase existing between
 signals IN and REF can have any value, and the duty cycle of signal REF is
 of no importance.
 The frequency of input signal IN is divided by two by a divider 12
 including a D-type flip-flop, the data input D of which is connected to
 its complemented output Q. A first internal signal CK1 is generated by an
 AND gate 14, a first input of which receives the direct output Q of
 flip-flop 12 and a second input of which receives reference signal REF.
 Signal CK1 rates a first shift register 16 with its rising edges. This
 shift register includes three series-connected D-type flip-flops (D1, D2,
 D3), each provided with a reset terminal R. The reset terminals R of the
 three flip-flops are interconnected, and the first flip-flop D1
 permanently receives a 1 on its data input D. Signal CK1 is also provided
 to reset terminals R of the flip-flops of a second shift register 18
 similar to register 16.
 A second internal signal CK2 is generated by an AND gate 20, which receives
 on a first input the complemented output Q of flip-flop 12 and on a second
 input reference signal REF. Signal CK2 rates shift register 18 with its
 rising edges, and resets register 16. The outputs of registers 16 and 18
 are both provided to an OR gate 22 which provides a signal MISS of
 detection of a disappearing.
 FIG. 2 shows in a left-hand portion A of a timing diagram the normal
 operation of circuit 10, when the latter receives input signal IN and
 reference signal REF. Flip-flop 12 generates on its output Q a signal IN/2
 of frequency twice lower than that of input signal IN. Signal CK1
 corresponds to the logic AND combination of signal IN/2 and of reference
 signal REF. Similarly, signal CK2 corresponds to the logic AND combination
 of the signal complementary of IN/2 generated by output Q of flip-flop 12
 (not shown) and of reference signal REF. Value CNT16 represents the number
 of D flip-flops at 1 of shift register 16. Each rising edge of signal CK2
 resets all the D flip-flops of register 16. Each rising edge of internal
 signal CK1 propagates state 1 by one flip-flop in register 16, that is,
 increments by 1 the number of D flip-flops at 1.
 When input signal IN is present, two rising edges of signal CK1 at most are
 provided to register 16 before a rising edge of signal CK2 resets the
 register. Thus, the number of D flip-flops of register 16, having an
 activated output periodically varies between 0 and 2 during each period of
 signal IN/2. In other words, in normal operation the last flip-flop of
 register 16 is not set to 1.
 Shift register 18 operates in the same way as register 16 with a phase
 shift equal to one period of input signal IN, value CNT18 represents the
 number of D flip-flops at 1 in register 18. Accordingly, gate 22 never
 activates signal MISS, none of the last flip-flops of register 16 and 18
 being set to 1.
 The right-hand portion B of the block diagram shows the disappearing of
 signal IN during a period, T.sub.B, starting at a time t. The transition
 of signal IN/2 which should have occurred at t disappears, and signal IN/2
 keeps, in the period T.sub.B following the disappearing of the input
 signal, the value that it had during the preceding period T.sub.A. As a
 result, signal CK1 and signal CK2 are interchanged all along period
 T.sub.B. As a result, signal CK1 does not reset register 18 at the time t
 when it should have, and register 18 is rated a third time by signal CK2
 before being reset. The third flip-flop of register 18 is thus set to 1,
 and signal MISS of detection of a disappearing is activated.
 When signal IN reappears, the circuit operates normally again, register 18
 is reset, and signal MISS disappears.
 The above-mentioned example illustrates the case where register 18
 generates signal MISS, but it should be noted that the case where register
 16 generates signal MISS can also be encountered, if signal IN disappears
 while signal IN/2 is at 1.
 The example shown in FIG. 1 enables detecting the disappearing of input
 signal IN during at east one period. However, it should be noted that an
 alternative responsive to the disappearing of the input signal after more
 than one period may also be realized by increasing the number of D
 flip-flops of shift registers 16 and 18.
 It should also be noted that in some phase conditions between signals IN
 and REF (for example, if they are in phase), registers 16 and 18 will only
 count to 1 before being reset. In this case, only a disappearing of signal
 IN of duration greater than or equal to two periods will be detected with
 the embodiment of FIG. 1. Finally, it should be noted that the
 disappearing of the signal can leave input IN at a low level (as shown
 previously) or at a high level.
 Of course, the present invention is likely to have various alterations,
 modifications, and improvements which will readily occur to those skilled
 in the art. For example, the shift registers may be replaced with other
 types of counters and the logic OR gate may be replaced with other means
 for checking that a predetermined value is reached by any one of the two
 counters. Similarly, AND gates 14 and 20 may be replaced with other logic
 gates such as OR gates if counters having a reset terminal activated by
 state 0 are for example desired to be used. The present invention divides
 the input signal by two to generate internal signals CK1 and CK2 but
 another type of divider having a different ratio may also be used.
 Such alterations, modifications, and improvements are intended to be part
 of this disclosure, and are intended to be within the spirit and the scope
 of the present invention. Accordingly, the foregoing description is by way
 of example only and is not intended to be limiting. The present invention
 is limited only as defined in the following claims and the equivalents
 thereto.