Low cost and mask reduction method for high voltage devices

Aspects of the present disclosure provides a device comprising a P-type semiconductor substrate, an N-type tub above the semiconductor substrate, a P-type region provided in the N-type tub isolated by one or more P-type isolation structures, and an N-type punch-through stopper provided under the P-type regions isolated by the isolation structure(s). The punch-through stopper is heavily doped compared to the N-type tub. The P-type region has a width between the two isolation structures that is equal to or less than that of the N-type punch-through stopper.

FIELD OF THE DISCLOSURE

This present disclosure relates generally to semiconductor devices, and more particularly to integration of high voltage and low voltages devices onto the same integrated circuit and methods of fabricating the same.

BACKGROUND

Bipolar-CMOS-DMOS (BCD) process technology combines bipolar transistors, complementary metal-oxide-semiconductor (CMOS) devices and double diffused metal-oxide-semiconductor (DMOS) devices on a single chip. Bipolar devices are used for analog circuitry, CMOS devices are for logic circuitry and DMOS devices are for high voltage devices. The BCD device has advantages of high frequency and high power drive capability due to the bipolar transistors, low power consumption and high integration density due to the CMOS transistors, and excellent power controllability due to a low on-resistance between a drain and a source of each DMOS transistor and its large current and high breakdown voltage. Thus, BCD technology is often used for manufacturing high voltage power management integrated circuits or analog system-on-chip applications, with particular applications in wireless handheld electronics and consumer electronics.

Generally in BCD technologies, the highest operating voltage is limited by (1) reach-through breakdown of a vertical structure of P to N junction, (2) high voltage tub to p-substrate or ground and/or (3) other parameters. This vertical junction breakdown is a function of Epi thickness, doping concentration and junction depth. Thus, in addition to isolation of high voltage and low voltage devices, BCD technology requires an N-type stopper for having low voltage devices in a high voltage tub to prevent punch through.FIG. 1Ashows an example of a BCD device10with conventional isolation and punch-through stopper configuration. The device10has an N-type epitaxial (N-epi) layer14disposed on a P-type substrate12. Without showing the detailed structure of the device, a number of P-type regions (P-wells)16and18are provided in the N-epi layer14. A dedicated mask is required to form a buried P-type regions22which extend from the bottoms of N-epi layer14upward into the bottom edge of P-wells18and merge together. Buried P-type regions22also extend downwards into the substrate12, thus, providing isolation of the device10from the rest area of the semiconductor chip where other devices may be formed. Device10further comprises an N-type buried region20under the P-well16to prevent punch through between P-well16and P-type substrate12which limits the maximum operating voltage of the device10. The N-type buried region20requires a dedicated mask to form in the process. Thus, the performance of device10may be optimized by using a certain thickness of N-epi layer14and controlling the depth of P-well16and the lateral distance between N-type buried region20and P-type buried region22.

The manufacturing process would start with the substrate material12and ion implantation for regions20and22to be formed respectively in later steps. A dedicated zero mask is required by etching unused areas of the silicon to leave marks for alignment. The epitaxial layer14is then disposed on top of the substrate material12and multiple N-wells and P-wells are formed extending downwards from the top surface of the epitaxial layer. Additional steps may be carried out to form a specific function such as a bipolar transistor or a MOSFET. It is noted that a P-Epi layer may be used instead of N-Epi layer, but it requires an additional lightly doped N-well region deep enough to convert P- to N-. N Epi can form N-tub by only P-Iso.

Alternatively, a blanket implantation may be carried out to form a P-type buried layer22aon top of the P-type substrate12aas shown inFIG. 1B. In addition, P-well isolation regions18ahave to be deep enough to reach the P-type buried layer22a. With this configuration, one less mask is used. While the configuration ofFIG. 1Bis good enough for the device with a relatively low operating voltage, e.g., less than 40 volts, the configuration ofFIG. 1Ais usually used when the device has a much higher operating voltage, e.g., 100 V or more.

Fabrication of the BCD device may need complex process technologies and a large number of photo masks. Forming the N-type buried region20and P-type buried layer22and lightly doped deep N-well regions (not shown) used to form N tubs requires high temperature long duration diffusion cycles. Furthermore, the epitaxy step is expensive. Therefore conventional BCD process flow is long and is expensive. Thus, manufacturing costs of the BCD device may be increased. Therefore, various process technologies for forming the BCD device may still be required to reduce the manufacturing costs and to improve performance thereof.

It is within this context that embodiments of the present invention arise.

DESCRIPTION OF THE SPECIFIC EMBODIMENTS

Embodiments of the present disclosure present a BCD device with an N-type punch through stopper formed under a P-type layer. The N-type punch through stopper may be formed either by blanket implantation or epitaxy deposition. The N-type punch through stopper under the P-type layer stops punch through to the P-type substrate. In addition, isolation structures for isolation of high voltage devices from low voltage devices may be formed either by high energy and low energy boron implants, and/or low energy boron implants followed by a high temp/long duration drive-in. Such BCD devices may be fabricated with minimal introduction of photo masks and processing steps according to embodiments of the present disclosure. Below describes three embodiments of forming the N-type punch through stopper under a p-type layer.

First Embodiment

FIGS. 2A-2Gare a sequence of cross-sectional schematic diagrams illustrating a method of fabrication of the device according to one embodiment of the present disclosure. As shown inFIG. 2A, the process starts with a P-type semiconductor substrate202as a starting material. The substrate202may be divided into multiple regions for forming devices of different operating voltage ratings. Each region is isolated by isolation structures as discussed below. For the sake of example, figures show a semiconductor device formed between two isolation structures. This is done to illustrate the general fabrication process and is not meant as a limitation on any embodiment of the invention. It is understood that the semiconductor device can be a bipolar transistor, a CMOS device or a DMOS device. It is further understood that any device combination can be integrated together in one single chip using the techniques disclosed in the disclosure below.

A screen oxide (e.g., a layer of silicon dioxide SiO2) is first grown on the P-type substrate202. The thickness of the screen oxide ranges from 200 to 300 Å. The screen oxide stops channeling and acts as a cap to protect the surface of the P-type substrate. A blanket phosphorous implant is then carried out to form an N-type layer204on top of the P-type substrate202as shown inFIG. 2B. The doping concentration of the N-type layer204is about 1×1015cm−3.

InFIG. 2C, a layer206of silicon nitride (SiN) can be deposited on top of the N-type layer204. The thickness of the SiN layer206may be about 1000 Å to about 2000 Å. A photoresist (not shown) is formed on the layer206and patterned as an active area mask. Portions of the layer206exposed to an etchant through openings in the photoresist are etched away to form the SiN pattern206and the etching stops at the surface of the N-type layer204. Next, an isolation mask208is formed to define the isolation regions. That is, the isolation mask208covers the regions that are not to receive the boron implant for isolation structures. As shown inFIG. 2D, the isolation mask208is aligned to the SiN pattern206formed by the active area mask. As such, a zero mask for alignment can be omitted. A boron implant is then carried out to form one or more P-type isolation structures210.

InFIG. 2E, a thermal field oxidation cycle is performed to grow field oxide212and also drives in both Phosphorous and Boron to form an N-type tub204and P-type isolation structures210respectively. That is, the N-type tub204and P-type isolation regions210can be formed by only one masking step using the isolation mask208. It is noted that if shallow trench isolation (STI) is used, a liner oxidation cycle may be used for the drive-in.

A deep N-well (DNW) mask214is formed to define the N buried layer (NBL) regions. A high energy implant is carried out through openings in the mask214to form a buried N-type punch through stopper216as shown inFIG. 2F. The DNW implant receives a low temp short duration diffusion, which preserves a sharply peaked implant profile. The punch though stopper216works as a highly doped N-type buried layer with a doping concentration ranging from about 1×1017cm−3to about 1×1018cm−3. Thereafter, with another photo mask220, a P-type implant (e.g., boron) is carried out with a medium implant energy to form a P-type layer/region218above the deeper N-type punch through stopper216as shown inFIG. 2G. It this example, the P-type region218has a width between two adjacent isolation structures that is less than that of the punch-through stopper216. In some implementations, the P-type layer/region218can be P-WELL for LV NMOS body, P-BASE for VNPN base or P-DRIFT for PLDMOS drain extension. Since two separate masks are used for the N-type implant and P-type implant, the P-type layer218and the N-type punch through stopper216are in different sizes.

According to aspects of the present disclosure, major cost reduction can be obtained by omitting expensive Epitaxy and high temperature long duration diffusion cycles of NBL formation and DNW formation. In particular, a blanket phosphorous implant and field oxide formation can replace these expensive steps while still forming the desired N-tub regions. In addition to avoiding the need for an expensive epitaxial step, the method described with respect to the first embodiment can save cost and by avoiding the need for a zero mask and reducing masking and long duration high temperature diffusion process steps used to form the P-type isolation structures210, N-buried layer punch through stopper216and the P-buried layer218.

FIG. 3is a cross-section schematic diagram illustrating a device with isolation structures and a punch through stopper according to the above embodiment of the present disclosure. Specifically, a device may be formed in the N-type tub204above the N-type punch through stopper216and between two adjacent P-type isolation structures210, wherein the P-type layer218above the punch through stopper216are narrower in width than the punch through stopper216. The N-type punch through stopper216stops punch through or communication between the P-type layer/region218and the P-type substrate202. It is understood that the device can be a bipolar transistor, a CMOS or a DMOS device.FIGS. 4A-4Gshows examples of various devices implemented according to the embodiments of the present disclosure. These devices are well known to one of ordinary skill in the art and thus descriptions of functions and fabrication processes for these devices will be omitted for the sake of brevity.

FIG. 4Ashows the active area of device401is configured as a low voltage CMOS that include an NMOS formed in the P-well region (P-type layer/region)218, and a PMOS formed in the N-well region410. The operating voltage of the NMOS in the P-well region may range from 1-10 volts and may be floated to a higher potential than ground. Such devices have lower noise due to isolation of the device structures.

FIG. 4Bshows an alternative embodiment in which the active area of device402is configured as an N-channel LDMOS that includes an N+ source region420disposed in P-well region218and an N+ drain contact pickup region422disposed in N-well or N-drift region424.

FIG. 4Cshows an alternative embodiment of a double resurf NLDMOS device403formed in the N-type tub204between the two P-type isolation structures210. The active area of device403includes an N+ source region430disposed in the P-well region218and an N+ drain contact pickup region432disposed in N-well region434. The double resurf NLDMOS device403provides low resistance between the source and the drain during the on state (Rds-on) in a lateral device.

FIG. 4Dshows an alternative embodiment of a P-channel LDMOS device404formed in the N-type tub204between the two P-type isolation structures210. A P-channel LDMOS404can be formed in a same way as shown inFIG. 4B, except that the P+ source region440is now disposed in N-well region444provided as the body and P+ drain contact pickup442is now disposed in P-well or P drift region218provided as the drain.

FIG. 4Eshows an alternative embodiment of a high voltage vertical NPN transistor (VNPN)405formed between the two p-type isolation structures210. The active area of device405includes a highly doped N+ region450disposed in the high voltage P-well region (HVPW)218. The highly doped N+ region450, the P-well region218and the N-type regions216and204below the P-well218configures a vertical NPN with N+ region450provided as the emitter, P-well218provided as the base and the N-type regions below the HVPW218provided as the collector. The P+ regions452disposed in HVPW218provide contact pickups to the base while the N-type regions454disposed in top portion of the N-type tub204outside of the HVPW218provide contact pickups to the collector.

FIG. 4Fshows an alternative embodiment in which the active area of device406is configured as a lateral PNP (LPNP) including a P region460provided as the emitter, a P ring462provided as the collector encircling the central P emitter region460, and a N ring464provided as base contact pickup encircling the collector P ring462and the emitter P region460.

FIG. 4Gshows an alternative embodiment of an N-type junction gate field-effect transistor (NJFET)407formed between the two p-type isolation structures210. The active area of the device407includes a highly doped P+ region470disposed in P-well region218provided as the gate. The gate contacts the N-type region216forming a PN junction.

Second Embodiment

FIGS. 5A-5Fare a sequence of a sequence of cross-sectional schematic diagrams illustrating a method of fabrication of the device according to one embodiment of the present disclosure. InFIG. 5A, the process uses a P-type semiconductor substrate502as a starting material. The substrate502may be divided into multiple regions for forming devices of different operating voltage ratings. Each region is isolated by isolation structures as discussed below. For the sake of example, figures show a semiconductor device formed between two isolation structures. This is done to illustrate the general fabrication process and is not meant as a limitation on any embodiment of the invention. It is understood that the semiconductor device can be a bipolar transistor, a CMOS device or a DMOS device. It is further understood that any device combination can be integrated together in one single chip using the techniques disclosed in the disclosure below.

After growing a screen oxide (e.g., a layer of silicon dioxide SiO2) for a thickness of 200 to 300 Å on the P-type substrate502, a blanket phosphorous implant is then carried out to form an N-type layer504on top of the P-type substrate502as shown inFIG. 5B. The doping concentration of the N-type layer204is about 1×1015cm−3.

InFIG. 5C, a layer506of silicon nitride (SiN) can be deposited on top of the N-type layer504. The thickness of the SiN layer506may be about 1000 Å to about 2000 Å. A photoresist (not shown) is formed on the layer506and patterned as an active area mask. Portions of the layer506exposed to an etchant through openings in the photoresist are etched away to form the SiN pattern506and the etching stops at the surface of the N-type layer504. Next, an isolation mask508is formed to define the isolation regions. That is, the isolation mask508covers the regions that are not to receive the boron implant for isolation structures. As shown inFIG. 5D, the isolation mask508is aligned to the SiN pattern506formed by the active area mask. As such, a zero mask for alignment can be omitted. A boron implant is then carried out to form P-type isolation layers510.

InFIG. 5E, a thermal field oxidation cycle is performed to grow field oxide512and also drives in both Phosphorous and Boron to form an N-type tub504and P-type isolation regions510respectively. That is, the N-type tub504and P-type isolation regions510can be formed by only one masking step using the isolation mask508. It is noted that if shallow trench isolation (STI) is used, liner oxidation cycle will work as the drive-in.

FIG. 5Fshows that a highly doped N type implant at higher energy and P type implant at lower energy can be done using one masking step. That is, a deep N-well (DNW) masking step may be omitted. Specifically, with the photo mask514, a high energy N-type implant (e.g., phosphorous) is carried out to form an N-type punch through stopper516, and a P-type implant (e.g., boron) is carried out with a medium implant energy to form a P-type layer/region518above the deeper n-type punch through stopper516. The N-type punch through stopper516is heavily doped with a doping concentration ranging from about 1×1016cm−3to about 1×1018cm−3. The DNW implant then receives a low temp short duration diffusion, which preserves a sharply peaked implant profile. In some implementations, the P-type layer/region518can be P-WELL for LV NMOS body, P-BASE for VNPN base or P-DRIFT for PLDMOS drain extension. It is noted that the N-type punch through stopper516and the P-type layer/region518are of about the same width because one single mask is using for both N-type and P-type implants. In this configuration, the highly doped N type punch through stopper516under the P type layer518stops punch through between the P type layer518and the P-type substrate502.

It is desirable to have a wider N type punch through stopper516than the P type layer518to prevent from punch through from the corner of the P type layer518to the P-type substrate502.FIG. 5F′ illustrates a possible implementation in which an angled implant is used to form a punch though stopper516that is wider than the P-type layer518. Angled implant typically involves directing a beam of ions at the substrate at an angle to the surface of the substrate while rotating the substrate about an axis perpendicular to the surface. By controlling the angle and energy of implant the N-type dopants implanted the punch through stopper516may be made deep enough and wide enough to avoid the punch through.

In another possible implementation, a partial ashing of the photoresist514may be performed between the medium energy P-type implant and the high energy N-type implant as shown inFIG. 5F-1 to 5F-3. Specifically, after the process ofFIG. 5E, a photoresist514is formed on the structure ofFIG. 5Eand is patterned as shown inFIG. 5F-1. A medium energy P-type implant is performed to form the P-type layer518. Next, a partial ashing of the photoresist514is carried out to reduce the thickness of the photoresist514and increase the width of the mask opening as shown inFIG. 5F-2. InFIG. 5F-3, a high energy N-type implant is carried out to form the N type punch through stopper516under the P-type layer518. As shown inFIG. 5F-3, the deeper N type punch through stopper516is wider than the P-type layer518formed above. In an optional further enhancement, an angled implant may be carried out for the N-type implant to make the punch through stopper516even wider as shown inFIG. 5F-4.

FIG. 6is a cross-section schematic diagram illustrating a device600with isolation structures and a punch through stopper according to the above embodiment of the present disclosure. Specifically, a device may be formed in the N-type tub504above the N-type punch through stopper516and between two adjacent P-type isolation structures510, wherein the P-type layer518above the punch through stopper516are about the same size. The N-type punch through stopper516stops punch through between the P-type layer/region518and the P-type substrate502. It is understood that the device can be a bipolar transistor, a CMOS or a DMOS device. Like the method described above with respect to the first embodiment, the method of the second embodiment also avoids the need for a zero mask and an epitaxial layer. In addition, the method described with respect to the second embodiment can save cost and reduce masking steps and avoid long duration high temperature diffusion steps in forming the P-type isolation structures510, N-buried layer punch through stopper516and the P-buried layer518.

FIGS. 7A-7Gshows examples of various devices implemented according to the embodiments of the present disclosure. These devices are well known to one of ordinary skill in the art and thus descriptions of functions and fabrication processes for these devices will be omitted.

FIG. 7Ashows a low voltage CMOS device701formed in the N-type tub504between the two P-type isolation structures510. The active area of device701includes an NMOS formed in the P-well region (P-type layer/region)518, and a PMOS formed in the N-well region710.

FIG. 7Bshows an alternative embodiment in which the active area of device702is configured as an N-channel LDMOS that includes an N+source region720disposed in P-well region518and an N+ drain contact pickup region722disposed in N-well724.

FIG. 7Cshows an alternative embodiment of a double resurf NLDMOS device703formed in the N-type tub504between the two P-type isolation structures510. The active area of device703includes an N+ source region730disposed in the P-well region518and an N+drain contact pickup region732disposed in N-well region734. The double resurf NLDMOS device703provides low resistance between the source and the drain during the on state (Rds-on) with superjunction, but in a lateral device.

FIG. 7Dshows an alternative embodiment of a P-channel LDMOS device704formed in the N-type tub504between the two P-type isolation structures510. A P-channel LDMOS704can be formed in a same way as shown inFIG. 4B, except that the P+ source region740is now disposed in N-well region744provided as the body and P+ drain contact pickup742is now disposed in P-well region518provided as the drain.

FIG. 7Eshows an alternative embodiment of a high voltage vertical NPN transistor (VNPN)705formed between the two p-type isolation structures510. The active area of device705includes a highly doped N+ region750disposed in the high voltage P-well region (HVPW)518. The highly doped N+ region750, the P-well region518and the N-type regions516and504below the P-well518configures a vertical NPN with N+ region750provided as the emitter, P-well518provided as the base and the N-type regions below the HVPW518provided as the collector. The P+ regions752disposed in HVPW5 provide contact pickups to the base while the N-type regions754disposed in top portion of the N-type tub504outside of the HVPW518provide contact pickups to the collector.

FIG. 7Fshows an alternative embodiment in which the active area of device706is configured as a lateral PNP (LPNP) including a P region760provided as the emitter, a P ring462provided as the collector encircling the central P emitter region760, and a N ring764provided as base contact pickup encircling the collector P ring762and the emitter P region760.

FIG. 7Gshows an alternative embodiment of an N-type junction gate field-effect transistor (NJFET)707formed between the two p-type isolation structures510. The active area of the device707includes a highly doped P+ region770disposed in P-well region518provided as the gate. The gate contacts the N region516forming a PN junction.

Third Embodiment

FIGS. 8A-8Fare a sequence of cross-sectional schematic diagrams illustrating a method of fabrication of the device according to one embodiment of the present disclosure. InFIG. 8A, the process uses a P-type semiconductor substrate802as a starting material. The substrate802may be divided into multiple regions for forming devices of different operating voltage ratings. Each region is isolated by isolation structures as discussed below. For the sake of example, figures show a semiconductor device formed between two isolation structures. This is done to illustrate the general fabrication process and is not meant as a limitation on any embodiment of the invention. It is understood that the semiconductor device can be a bipolar transistor, a CMOS device or a DMOS device. It is further understood that any device combination can be integrated together in one single chip using the techniques disclosed in the disclosure below.

Next, instead of performing a blanket implantation, an N-type epitaxial structure is formed on the P-type substrate802by epitaxial deposition. The N-type epitaxial structure may include two or three N-type epitaxial layers. In the example where the N-type epitaxial structure includes two layers as shown inFIG. 8B, the bottom layer804is a more heavily doped layer with a doping concentration ranging from about 1×1016cm−3to about 1×1017cm−3, and a top layer805is a less heavily doped layer with a doping concentration about 1×1015cm−3. The bottom layer804is in a thickness of about 0.5 μm and the top layer806is about 1-2 μm thick. In the example of three-layer structure as shown inFIG. 8B-1, the more heavily doped layer is sandwiched between the two less heavily doped layers803and805. For illustration,FIGS. 8C-8Fonly show cross-sectional schematic diagrams illustrating fabrication of a device with a two-layer N-epi structure.

After growing a screen oxide on the N-type epitaxial structure, a layer806of silicon nitride (SiN) can be deposited on the top. The thickness of the SiN layer806may be about 1000 Å to about 2000 Å. A photoresist (not shown) is formed on the layer806and patterned as an active area mask. Portions of the layer806exposed to an etchant through openings in the photoresist are etched away to form the SiN pattern806as shown inFIG. 8C.

An isolation mask808is formed to define the isolation regions. That is, the isolation mask808covers the regions that are not to receive the boron implant for isolation structures. As shown inFIG. 8D, the isolation mask808is aligned to the SiN pattern806formed by the active area mask. As such, a zero mask for alignment can be omitted. A boron implant is then carried out to form P-type isolation layers810.

InFIG. 8E, a thermal field oxidation cycle is performed to grow field oxide812and also drives in both Phosphorous and Boron to form an N-type tub804and P-type isolation regions810respectively. That is, the N-type tub804and P-type isolation regions810can be formed by only one masking step using the isolation mask808. It is noted that if shallow trench isolation (STI) is used, liner oxidation cycle will work as the drive-in.

InFIG. 8F, with a photo mask814, a P-type implant medium energy can be carried out to form a P-type layer818in the N-type epi layer805. It is noted that an N-type implant is unnecessary in this embodiment. The highly doped N-type epitaxial layer804under the P-type layer818stops punch through between the P-type layer and the P-type substrate802. Thus, a DNW masking step can be omitted. Optimization of thickness and doping concentration of the N-epi structure is very important in this embodiment.

FIG. 9is a cross-section schematic diagram illustrating a device900with isolation structures and a punch through stopper according to the above embodiment of the present disclosure. Specifically, a device900has a three-layer N-epi structure. The heavily doped N-epi layer804is sandwiched between the less heavily doped layers803and805.

A device may be formed in the N-epi layer805above the N-epi layer804and between two adjacent P-type isolation structures810. The N-epi layer804acts as a punch through stopper stops punch through between the P-type layer/region818and the P-type substrate802. It is understood that the device can be a bipolar transistor, a CMOS or a DMOS device.

Although an epitaxial step is used, the method described with respect to the third embodiment can still save cost by avoiding the need for a zero mask and reducing masking steps and avoiding long duration high temperature diffusion steps in forming the P-type isolation structures810, N-buried layer punch through stopper816and the P-buried layer818.

FIGS. 10A-10Eshows examples of various devices implemented according to the embodiments of the present disclosure. These devices are well known to one of ordinary skill in the art and thus descriptions of functions and fabrication processes for these devices will be omitted.

FIG. 10Ashows a low voltage CMOS device1001formed in the N-epi layer805between the two P-type isolation structures810. The active area of device1001includes an NMOS formed in the P-well region (P-type layer/region)818, and a PMOS formed in the N-well region1010.

FIG. 10Bshows an alternative embodiment in which active area of device1002is configured as an N-channel LDMOS that includes an N+ source region1020disposed in P-well region818and an N+ drain contact pickup region1022disposed in N-well1024.

FIG. 10Cshows an alternative embodiment of a double resurf NLDMOS device1003formed in the N-epi layer805between the two P-type isolation structures810. The active area of device1003includes an N+ source region1030disposed in the P-well region818and an N+ drain contact pickup region1032disposed in N-well region1034. The double desurf NLDMOS device1003provides low resistance between the source and the drain during the on state (Rds-on) with superjunction, but in a lateral device.

FIG. 10Dshows an alternative embodiment of a P-channel LDMOS device1004formed in the N-epi layer805between the two P-type isolation structures810. A P-channel LDMOS1004can be formed in a same way as shown inFIG. 4B, except that the P+ source region1040is now disposed in N-well region1044provided as the body and P+ drain contact pickup1042is now disposed in P-well region818provided as the drain.

FIG. 10Eshows an alternative embodiment of a high voltage vertical NPN transistor (VNPN)1005formed between the two p-type isolation structures810. The active area of device1005includes a highly doped N+ region1050disposed in the high voltage P-well region (HVPW)818. The highly doped N+ region1050, the P-well region818and the N epi layers805,804and803below the P-well818configures a vertical NPN with N+ region1050provided as the emitter, P-well818provided as the base and the N epi layers below the HVPW818provided as the collector. The P+ regions1052disposed in HVPW provide contact pickups to the base while the N regions1054disposed in top portion of the N-type layer805outside of the HVPW818provide contact pickups to the collector. In addition, the active area of the device according to the third embodiment may be configured as a later PNP similar to the active area shown inFIG. 7For an N-type junction gate field-effect transistor (NJFET) similar to the active area shown inFIG. 7G.

Aspects of the present disclosure enable integration of bipolar, CMOS, and DMOS devices into a single wafer. This facilitates fabrication of compact devices having, e.g., CMOS elements that implement logic functions, Bipolar elements to implement analog devices, and DMOS elements to implement high voltage devices.

While the above is a complete description of the preferred embodiments of the present invention, it is possible to use various alternatives, modifications, and equivalents. Although certain process steps appear in a certain order in the claims, the steps are not required to be carried out in order in which unless a particular order is specified. Therefore, the scope of the present invention should be determined not with reference to the above description but should, instead, be determined with reference to the appended claims, along with their full scope of equivalents. Any feature, whether preferred or not, may be combined with any other feature, whether preferred or not. In the claims that follow, the indefinite article “A” or “An” refers to a quantity of one or more of the item following the article, except where expressly stated otherwise. The appended claims are not to be interpreted as including means-plus-function limitations, unless such a limitation is explicitly recited in a given claim using the phrase “means for”. Any element in a claim that does not explicitly state “means for” performing a specified function, is not to be interpreted as a “means” or “step” clause as specified in 35 USC §112(f).