The present invention concerns a DBS receiver which serves to combine the functions of variable rate demodulation, convolutional decoding, de-interleaving and block decoding. The demodulation stage includes a novel circuit for clock synchronization. By combining the functions of these components this device provides a higher level of utility as measured in terms of reliability, simplicity, flexibility, cost effectiveness, and integration of board layout while maintaining optimum-quality signal processing.

BACKGROUND OF THE INVENTION 
1. Field of the Invention 
This invention relates to an apparatus for receiving and decoding a signal 
such as that transmitted according to the digital video broadcast standard 
("Specifications of the Baseline Modulation/Channel Coding System for 
Digital Multi-Programme Television by Satellite", European Broadcasting 
Union, January 1994). Such signals are commonly used in satellite 
communications systems which employ error correction to combat signal 
corruption. More specifically, this invention concerns a device with a 
variable rate QPSK/BPSK demodulator and a concatenated 
Viterbi/Reed-Solomon decoder. 
2. Description of the Relevant Art 
Digital broadcast satellite (DEBS) communication systems provide reliable 
long range transmission of information without the need for a pre-existing 
network of transmission lines and routing switches. However, since the 
costs entailed in creating a satellite and placing it in orbit are 
literally astronomical, the economic practicality of these systems depends 
in large part on widespread use of DBS receiver systems. Consequently 
containment of the costs for construction, distribution and maintenance of 
DBS receiver systems plays an important role for the emerging DBS 
technology. 
FIG. 1 shows a standard model for a communications system 124 comprising a 
discrete-time channel 126 interposed between an encoder 128, and a decoder 
130. Discrete-time channel 126 includes a continuous-time channel 140 
interposed between a modulator-demodulator pair 138, 142. In this case the 
continuous-time channel may take the form of the atmosphere through which 
a broadcast signal propagates. The modulator-demodulator pair will 
typically use binary or quadrature phase shift keying as the modulation 
technique. By grouping the continuous-time channel with the 
modulator-demodulator pair, it becomes possible to treat the whole as a 
discrete-time channel which accepts a digital input signal and produces a 
possibly corrupted version of the input signal. Due to the power 
restrictions placed on satellite transmission channels, the probability of 
signal corruption is substantial. 
To make satellite communications feasible, error correction codes are used 
which permit transmitted information to be communicated reliably at high 
data rates. The error correction coding scheme advocated by the standard 
referenced above is a concatenated coding scheme as shown in FIG. 1. 
Encoder 128 is comprised of three subcomponents: an outer encoder 134, an 
interleaver 136, and an inner encoder 132. Outer encoder 134 is a block 
encoder, in this case a Reed-Solomon encoder. Inner encoder 132 is a 
convolutional encoder. The combination of block and convolutional encoding 
is known to increase the error correcting capability of the decoder, and 
the use of an interleaver/de-interleaver pair serves to provide the large 
coding gain necessary to feasibly operate the power-limited satellite 
communications channel. Consequently, a critical part of the DBS receiver 
systems is the error correction decoding device. Hence it would be 
advantageous to provide a reliable yet economical implementation of an 
error correction decoding device as part of a DBS receiver system. 
SUMMARY OF THE INVENTION 
The problems outlined above are in large part solved by a DBS receiver 
which serves to combine the functions of variable rate demodulation, 
convolutional decoding, de-interleaving and block decoding. In one 
embodiment, the DBS receiver comprises a tuner coupled to an 
analog-to-digital converter which in turn is coupled to a single-chip 
receiver. The single-chip receiver comprises a demodulation stage and two 
decoder stages. The demodulation stage includes a novel circuit for clock 
synchronization circuit. By combining the functions of these components 
and adding a novel feedback circuit for clock synchronization, this device 
provides a higher level of utility as measured in terms of reliability, 
simplicity, flexibility, cost effectiveness, and integration of board 
layout while maintaining optimum-quality signal processing. 
Broadly speaking, the present invention contemplates a digital broadcast 
satellite (DBS) receiver system comprising a tuner, an analog to digital 
converter and a receiver chip. The receiver chip comprises a demodulator 
stage, a convolutional decoder stage, and a de-interleaver and block 
decoder stage. The tuner serves to receive a high frequency signal from 
the satellite dish and thereafter produce a baseband signal which is then 
converted to a digital signal by the analog to digital converter. The 
receiver chip completes the receiving process by demodulating and decoding 
the digital signal. In addition, the receiver chip provides feedback 
signals which may be used in negative feedback loops to control the gain, 
carrier, and clock acquisition and tracking.

DETAILED DESCRIPTION OF THE INVENTION 
Turning now to the drawings, FIG. 2 shows a DBS receiver system 10 
comprising a tuner 12, an analog to digital converter 14, a receiver chip 
16, and microprocessor 18. 
Tuner 12 comprises frequency synthesizer 18, analog multiplier 20, 
intermediate frequency bandpass filter 22, gain control amplifier 24, 
automatic gain control loop filter 25, I/Q down converter 26, and voltage 
controlled oscillator 27. Tuner 12 serves to convert a high frequency 
received signal to a baseband signal. Analog to digital converter 14 
serves to convert the analog baseband signal to a digital signal. Receiver 
chip 16 serves to demodulate and decode the digital signal. The frequency 
synthesizer is set to be "tuned" to the high frequency received signal. 
This is accomplished by synthesizing an output signal 30 with a frequency 
which is offset by a fixed amount from the frequency of the desired 
received signal. The fixed amount will be the frequency of a product 
signal which is generated by multiplier 20. 
Multiplier 20 multiplies high frequency signal 28 and output signal 30 from 
frequency synthesizer 18 to effectively shift the frequency of high 
frequency signal 28 to an intermediate frequency in an intermediate 
frequency signal. The product signal at the output of multiplier 20 can be 
expressed as the sum of a desired intermediate frequency signal and other 
undesired byproduct signals. The product signal is coupled to intermediate 
frequency bandpass filter 22 which removes the undesired frequency 
components (and in so doing, removes the undesired byproduct signals) 
leaving only the intermediate frequency signal. 
Output of bandpass filter 22 is coupled to gain control amplifier 24 which 
regulates the amplitude of the intermediate frequency signal. Gain control 
amplifier 24 has an adaptive gain which is set to provide a constant 
amplitude output signal. The regulation mechanism is based on a negative 
feedback signal 32 provided by receiver chip 16. The effect of feedback 
signal 32 is to increase the gain of gain control amplifier 24 when the 
amplitude of the output signal declines below a target level, and to 
decrease the gain when the amplitude exceeds a target level. 
Output of the gain control amplifier 24 is coupled to I/Q down converter 26 
which converts the intermediate frequency signal to a baseband signal. The 
conversion may take place in a similar fashion to the previous frequency 
conversion, but in this case two baseband signals are needed to represent 
the in-phase (I) and quadrature-phase (Q) components of the intermediate 
frequency signal. After the I/Q down conversion process there is typically 
some residual oscillation due to a frequency offset error. However, I/Q 
down converter 26 regulates the offset error using negative feedback 
signal 34 provided by receiver chip 16. The effect of feedback signal 34 
is to fine-tune the frequency of the local oscillator used in the 
down-conversion, thereby eliminating the residual oscillation. 
Output of I/Q down converter 26 is coupled to analog to digital converter 
14 which serves to convert the baseband signal to digital input signal 38. 
The rate at which the analog baseband signal is sampled is governed by a 
feedback signal 36. As will be explained in greater detail later, the 
feedback signal is initially set to provide a theoretically correct 
sampling frequency, and fine-tuned thereafter. The digital input signal 38 
is then coupled to receiver chip 16. 
FIG. 3 shows receiver chip 16 comprising a demodulator stage 40, a 
convolutional decoder stage 42, and a de-interleaver and block decoder 
stage 46. Demodulator stage 40 serves to provide filtering and symbol-rate 
sampling. Convolutional decoder stage 42 serves as the first decoding 
stage of the concatenated decoder. The final decoding stage is provided by 
de-interleaver and block decoder stage 46. 
Demodulator stage 40 comprises a matched filter 48 and a module 50 for 
timing control and gain control. Matched filter 48 filters digital input 
signal 38 to substantially maximize the signal-to-noise ratio of the input 
signal. To accomplish this, the impulse response of the filter is designed 
to be the time-reverse of the shape of a symbol signal. Hence, the filter 
is "matched" to the signal. One common symbol shape is a square root 
raised cosine. 
Output of matched filter 48 is coupled to module 50 which provides feedback 
signals for gain control 32, carrier synchronization 34, and clock 
synchronization 36. As mentioned before, the feedback signal for gain 
control is used to maintain a constant signal amplitude. The carrier 
synchronization feedback signal serves to fine-tune the local oscillator 
of the I/Q down converter to remove any residual oscillation. The clock 
synchronization feedback signal will be treated in greater detail below. 
Demodulator stage 40 may additionally comprise a decimation filter 52 and 
an output decimator 54. Decimation filter 52 and output decimator 54 allow 
for oversampling by analog to digital converter 14. Oversampling is the 
practice of sampling an analog signal at a higher rate than the symbol 
rate. Use of this practice allows the transfer of some filtering 
operations from the analog domain to the digital domain. In general, only 
simple analog filters are practical. For complex filtering operations, 
digital filters are significantly easier to implement and adjust. By 
oversampling and performing the matched filter operation in the digital 
domain, a substantial implementation complexity reduction is achieved. 
Furthermore, the use of oversampling allows relaxed tolerances on the 
analog filters used in the analog-to-digital conversion process, without 
significant impairment to the signal-to-noise ratio. Demodulator stage 40 
allows the rate of oversampling to be varied to accommodate differing data 
rates. 
Prior to the decoding stage, the sampling rate of the signal must be made 
equal to the symbol rate. This is accomplished through a digital lowpass 
filtering operation provided by decimation filter 52, and output decimator 
54 which passes on only one sample per symbol. 
As shown in FIG. 3, convolutional decoder stage 42 comprises de-puncturing 
logic 56 and a Viterbi decoder 58. Viterbi decoder 58 is a decoder for a 
standard industry convolutional code, namely a rate 1/2, constraint-length 
7 code with octal generators (133, 171). Several well-known puncturing 
methods are used to adapt this rate 1/2 code to a rate 2/3, 3/4, or 5/6 
code which can still be decoded by the Viterbi decoder for the rate 1/2 
code. De-puncturing logic 56 performs the necessary adaptation on the 
receiving end. 
Synchronization for input to Viterbi decoder 58 is provided by Viterbi 
synchronization circuit 60, which relies on an estimation of the symbol 
error rate which can be determined from the output of comparator 62. 
Comparator 62 determines the differences between the signal before 
decoding and a re-encoded version of the signal after decoding. Due to the 
error correcting capabilities of the Viterbi decoder, when only a few 
received symbol errors exist, the re-encoded signal should be relatively 
free of symbol errors. When the decoder is out of synchronization, the 
re-encoded signal will contain many symbol errors. Hence, the error rate 
determined by the comparator provides a good synchronization indicator. 
The output symbols from Viterbi decoder 58 are coupled to de-interleaving 
and block decoding stage 46. 
De-interleaving and block decoding stage 46 comprises synchronization 
circuit 66, de-interleaver 68, and block decoder 70. Synchronization 
circuit 66 serves to locate the beginning of an interleaved code word 
block and forward data to de-interleaver 68 accordingly. De-interleaver 68 
and block decoder 70 are implemented with parameters specified in the 
digital video broadcast standard referenced previously. 
Synchronization circuit 66 functions by scanning the Viterbi decoder output 
symbols for the sync bytes of 0047 hex. These bytes mark the beginning of 
a new block, and the synchronizer aligns the data accordingly for the 
subsequent de-interleaver and decoder. 
The output signal of synchronization circuit 66 is coupled to 
de-interleaver 68. De-interleaver 68 functions to disperse symbols which 
are adjacent in the output signal of synchronization circuit 66. The 
dispersion is the inverse of an interleave operation which was performed 
in the original encoding of the signal. One benefit of the dispersion is 
that it breaks up and isolates errors which are part of an error burst. 
This greatly benefits the performance of the block decoder. 
Block decoder 70 performs the final error correction and decoding stage of 
the decoding process. A standard block code family used in these systems 
is the family of Reed-Solomon codes. Reed-Solomon codes provide a powerful 
error correction ability which permits reliable decoding of the 
transmitted information. The decoded information is then provided as 
output 39 from the DBS receiver system. 
FIG. 4 shows a block diagram of a subsystem of module 50 which provides 
feedback signal 36 for clock synchronization. The clock synchronization 
circuit 72 operates in one of two modes: acquisition and tracking. In 
tracking mode, timing error detector 74 measures characteristics of the 
signal output by matched filter 48 and provides a correction signal to 
accumulator 76 which provides a feedback signal representing a weighted 
sum of past correction signals. The feedback signal is buffered and 
amplified by amplifier 78. The feedback signal is then filtered by an 
off-chip, user configurable filter 80 and coupled to voltage controlled 
oscillator 82 as shown. Voltage controlled oscillator 82 is used to 
provide the clock for analog to digital converter 14, thereby closing the 
phase-locked loop. 
A well-known property of phase-locked loops is inordinate non-linearity. 
For correct operation, phase-locked loops must first be placed in an 
initial state closely approximating the correct operating point. In the 
acquisition mode automatic frequency controller 84 serves this function. 
Automatic frequency controller 84 uses a counter and a timer comprised of a 
second counter and a crystal oscillator 86 to determine the output 
frequency of voltage controlled oscillator 82. Using a configurable 
parameter as a timer interval, automatic frequency controller loads the 
second counter and decrements it for every clock cycle of crystal 
oscillator 86 until the counter reaches zero. At the same time the second 
counter is loaded, the first counter is also loaded with the desired 
number of oscillations of voltage controlled oscillator 82 in the timer 
interval. During the timer interval, the first counter is decremented for 
every oscillation of voltage controlled oscillator 82. At the end of the 
timer interval when the second counter has reached zero, the contents of 
the first counter are inspected. If the contents are negative, too many 
oscillations have occurred, and the feedback signal is reduced to reduce 
the oscillation frequency. Similarly, if the contents are positive, not 
enough oscillations have occurred, and the oscillation frequency is 
increased. If the contents are zero or close to zero, then the the output 
frequency of voltage controlled oscillator 82 is within the pull-range of 
the phase-locked loop, i.e. the initial state of the phase-locked loop is 
sufficiently close to the desired operating point. At this point, clock 
synchronization circuit 72 enters the tracking mode. 
The advantages of the receiver system detailed above include a reduced part 
count. The novel clock synchronization circuit permits the use of a single 
voltage controlled oscillator for clocking the analog-to-digital 
converter. In conventional systems, it is necessary to use a bank of 
multiple voltage controlled crystal oscillators which are more accurate 
(and expensive) but have a sharply reduced range of oscillation. This 
advantage is gained through the use of digitally controlled feedback by 
the automatic frequency controller during the initial timing acquisition 
stage. An additional reduction in part count arises from the combination 
of the demodulation and decoding stages onto a single chip. The overall 
part count reduction leads to a significant simplification of board 
layout. Consequently a sharply increased reliability and hence increased 
utility are also obtained. 
Numerous variations and modifications will become apparent to those skilled 
in the art once the above disclosure is fully appreciated. It is intended 
that the following claims be interpreted to embrace all such variations 
and modifications.