Programming and reading circuit for dynamic random access memory

Disclosed herein are related to a memory device. In one aspect, the memory device includes a memory array including a set of memory cells. In one aspect, each of the set of memory cells includes a corresponding transistor and a corresponding capacitor connected in series between a bit line and a select line. In one aspect, the memory device includes a first transistor including a source/drain electrode coupled to a controller and another source/drain electrode coupled to the bit line. In one aspect, the memory device includes a second transistor including a gate electrode coupled to the bit line. In one aspect, the second transistor is configured to conduct current corresponding to data stored by a memory cell of the set of memory cells.

BACKGROUND

Developments in electronic devices, such as computers, portable devices, smart phones, internet of thing (IoT) devices, etc., have prompted increased demands for memory devices. In general, memory devices may be volatile memory devices or non-volatile memory devices. Volatile memory devices can store data while power is provided but may lose the stored data once the power is shut off. Unlike volatile memory devices, non-volatile memory devices may retain data even after the power is shut off but may be slower than the volatile memory devices.

DETAILED DESCRIPTION

Disclosed herein are related to a memory device including a memory array and circuits for programming and reading data stored by the memory array. In one aspect, the memory array includes a set of memory cells. In one aspect, each of the set of memory cells includes a corresponding transistor and a corresponding capacitor connected in series between a bit line and a select line. The set of memory cells may be dynamic random access memory cells. In one aspect, the memory device includes a first transistor including a source/drain electrode coupled to a controller and another source/drain electrode coupled to the bit line. In one aspect, the memory device includes a second transistor including a gate electrode coupled to the bit line. In one aspect, the second transistor is configured to conduct current corresponding to data stored by a memory cell of the set of memory cells.

In one aspect, the first transistor and the second transistor can be controlled or configured to program data by a memory cell of the set of memory cells. For example, to write data to a memory cell, the first transistor and the corresponding transistor of the memory cell can be enabled during a first time period in a programing phase. In addition, during the first time period in the programming phase, a voltage corresponding to the data can be applied to the bit line through the first transistor. For example, a first voltage can be applied to the memory cell to program or store a first logic state (e.g., logic ‘1’) of data. For example, a second voltage lower than the first voltage can be applied to the memory cell to program or store a second logic state (e.g., logic ‘0’) of data.

In one aspect, the first transistor and the second transistor can be controlled or configured to retain or maintain the data stored by the memory cell of the set of memory cells. For example, during a second time period in a retention phase, the first transistor can be enabled, while the corresponding transistor of the memory cell is disabled. In addition, during the second time period in the retention phase, a third voltage between the first voltage and the second voltage can be applied to the bit line through the first transistor. Accordingly, the bit line can be pre-charged to have the third voltage without altering the data stored by the memory cell in the retention phase.

In one aspect, the first transistor and the second transistor can be controlled or configured to read the data stored by the memory cell of the set of memory cells. For example, during a third time period in a reading phase, the first transistor can be disabled, while the corresponding transistor of the memory cell is enabled. In one aspect, during the third time period in the reading phase, a voltage of the bit line can be changed from the third voltage according to the data programmed by the memory cell. For example, if the data stored by the memory cell is the first logic state, then the voltage of the bit line may increase from the third voltage by enabling the corresponding transistor of the memory cell and disabling the first transistor. For example, if the data stored by the memory cell is the second logic state, then the voltage of the bit line may decrease from the third voltage by enabling the corresponding transistor of the memory cell and disabling the first transistor. In one aspect, the second transistor may conduct current according to a change in the voltage of the bit line. Hence, the data programmed by the memory cell can be determined by detecting the current through the second transistor.

Advantageously, the disclosed memory device can be implemented in an area efficient manner. In some cases, a memory device including DRAM memory cells may include complex circuits for programming and reading data. The disclosed memory device implements a first transistor including a source/drain electrode coupled to a bit line of a set of memory cells and a second transistor including a gate electrode coupled to the bit line. By implementing the first transistor and the second transistor having a simple configuration, complex circuits for programming or reading data can be obviated. The first transistor and the second transistor coupled to the bit line can be implemented as a same type of transistors in the DRAM memory cells. Hence, the first transistor and the second transistor coupled to the bit line and the set of memory cells can be implemented in a same layer. By implementing the first transistor and the second transistor in the same layer of the memory cells, the memory device can have a simple configuration and can be implemented in an area efficient manner.

In some embodiments, one or more components can be embodied as one or more transistors. The transistors in this disclosure are shown to have a certain type (N-type or P-type), but embodiments are not limited thereto. The transistors can be any suitable type of transistors including, but not limited to, metal oxide semiconductor field effect transistors (MOSFETs), bipolar junction transistors (BJTs), high voltage transistors, high frequency transistors, FinFETs, planar MOS transistors with raised source/drains, nanosheet FETs, nanowire FETs, or the like. Furthermore, one or more transistors shown or described herein can be embodied as two or more transistors connected in parallel. In one aspect, a transistor includes a source electrode, a drain electrode and a gate electrode. A source electrode and a drain electrode can be interchangeable, according to voltages applied to the source electrode and the drain electrode. Hence, a source electrode or a drain electrode can be referred to as a source/drain electrode herein.

FIG.1is a diagram of a memory device100, in accordance with one embodiment. In some embodiments, the memory device100includes a memory controller105and a memory array120. The memory array120may include a plurality of storage circuits or memory cells125arranged in two- or three-dimensional arrays. Each memory cell125may be coupled to a corresponding word line WL and a corresponding bit line BL. The memory controller105may write data to or read data from the memory array120according to electrical signals through word lines WL and bit lines BL. In other embodiments, the memory device100includes more, fewer, or different components than shown inFIG.1.

The memory array120is a hardware component that stores data. In one aspect, the memory array120is embodied as a semiconductor memory device. The memory array120includes a plurality of storage circuits or memory cells125. The memory array120includes word lines WL0, WL1. . . WLJ, each extending in a first direction (e.g., X-direction) and bit lines BL0, BL1. . . BLK, each extending in a second direction (e.g., Y-direction). The word lines WL and the bit lines BL may be conductive metals or conductive rails. In one configuration, each memory cell125is coupled to a corresponding word line WL and a corresponding bit line BL, and can be operated according to voltages or currents through the corresponding word line WL and the corresponding bit line BL. In some embodiments, each bit line includes bit lines BL, BLB coupled to one or more memory cells125of a group of memory cells125disposed along the second direction (e.g., Y-direction). The bit lines BL, BLB may receive and/or provide differential signals. Each memory cell125may include a volatile memory, a non-volatile memory, or a combination of them. In some embodiments, each memory cell125is embodied as a dynamic random access memory (DRAM) cell or other type of memory cell. In some embodiments, the memory array120includes additional lines (e.g., select lines, reference lines, reference control lines, power rails, etc.).

The memory controller105is a hardware component that controls operations of the memory array120. In some embodiments, the memory controller105includes a bit line controller112, a word line controller114, and a timing controller110. The bit line controller112, the word line controller114, and the timing controller110may be embodied as logic circuits, analog circuits, or a combination of them. In one configuration, the word line controller114is a circuit that provides a voltage or current through one or more word lines WL of the memory array120, and the bit line controller112is a circuit that provides or senses a voltage or current through one or more bit lines BL of the memory array120. In one configuration, the timing controller110is a circuit that provides control signals or clock signals to synchronize operations of the bit line controller112and the word line controller114. In some embodiments, the timing controller110is embodied as or includes a processor and a non-transitory computer readable medium storing instructions when executed by the processor cause the processor to execute one or more functions of the timing controller110or the memory controller105described herein. The bit line controller112may be coupled to bit lines BL of the memory array120, and the word line controller114may be coupled to word lines WL of the memory array120. In some embodiments, the memory controller105includes more, fewer, or different components than shown inFIG.1.

In one example, the timing controller110may generate control signals to coordinate operations of the bit line controller112and the word line controller114. In one approach, to write data to a memory cell125, the timing controller110may cause the word line controller114to apply a voltage or current to the memory cell125through a word line WL coupled to the memory cell125and cause the bit line controller112to apply a voltage or current corresponding to data to be stored to the memory cell125through a bit line BL coupled to the memory cell125. In one approach, to read data from a memory cell125, the timing controller110may cause the word line controller114to apply a voltage or current to the memory cell125through a word line WL coupled to the memory cell125and cause the bit line controller112to sense a voltage or current corresponding to data stored by the memory cell125through a bit line BL coupled to the memory cell125.

FIG.2illustrates a schematic block diagram of a portion200of the memory device100including an example memory array120and circuits (e.g., a driver circuit250, a sensor280, a bit line select transistor T1, and a bit line sense transistor T2) for programming and reading data stored by the memory array120, in accordance with some embodiments. In some embodiments, some of the circuits (e.g., the driver circuit250, the sensor280, the bit line select transistor T1, and the bit line sense transistor T2) for programming and reading data can be implemented as part of the memory controller105. For example, the driver circuit250and the sensor280can be implemented as part of the bit line controller112or the memory controller105. In some embodiments, some of the circuits (e.g., the driver circuit250, the sensor280, the bit line select transistor T1, and the bit line sense transistors T2) can be implemented together with the memory array120. For example, the bit line select transistor T1and the bit line sense transistor T2can be implemented together with or as part of the memory array120.

In some embodiments, the memory array120includes a plurality of sets of memory cells125. In one configuration, the plurality of sets of memory cells125may be connected to a common select line SL. In one configuration, each set of memory cells125may be connected to a corresponding bit line BL. For example, a first set of memory cells125may be connected between a bit line BL0and a common select line SL, and a second set of memory cells125may be connected between a bit line BL1and the common select line SL. In one configuration, memory cells125in different sets of memory cells125can be connected to a corresponding word line WL. For example, memory cells125in a first row in different sets of memory cells125can be coupled to a word line WL0, and memory cells125in a second row in different sets of memory cells125can be coupled to a word line WL1.

In one configuration, each memory cell125may be a DRAM memory cell. Each memory cell125may include an enable transistor222and a storage component228. The enable transistor222can be a BJT, MOSFET, FinFET, GaaFET, or any transistor. The enable transistor222may be an N-type transistor. Examples of the storage component228includes a capacitor, a resistor, or any component that can store data. In one configuration, the enable transistor222and the storage component228are coupled to each other in series between a corresponding bit line BL and the common select line SL. For example, the enable transistor222includes a source electrode coupled to the corresponding bit line BL, a gate electrode coupled to a corresponding word line WL, and a drain electrode coupled to a first end of the storage component. A second end of the storage component can be coupled to the common select line SL. In this configuration, the enable transistor222can be enabled or disabled, according to a voltage applied to the word line WL. For example, the enable transistor222can be enabled, in response to the word line WL having an enable voltage (e.g., VDD or higher). When the enable transistor222is enabled, the first end of the storage component222can be electrically coupled to the bit line BL. For example, the enable transistor222can be disabled, in response to the word line WL having a disable voltage (e.g., 0V or lower). When the enable transistor222is disabled, the first end of the storage component222can be electrically decoupled from the bit line BL.

The driver circuit250is a circuit or a component that can apply a voltage to a bit line BL. In some embodiments, the driver circuit250can be replaced by a different component that can perform the functionalities of the driver circuit250described herein. In some embodiments, the driver circuit250can generate a voltage corresponding to data to store by a memory cell125. For example, the driver circuit250can generate a first voltage (e.g., VDD or 1V) to program a memory cell125to store a first logic state. For example, the driver circuit250can generate a second voltage (e.g., 0V) lower than the first voltage to program the memory cell125to store a second logic state. For example, the driver circuit250can generate a third voltage (e.g., ½ VDD or 0.5V) between the first voltage and the second voltage to retain data stored by the memory cell125. A voltage generated by the driver circuit250can be applied to the bit line BL through the bit line select transistor T1to cause or configure one or more memory cells125to store or retain data.

The bit line select transistor T1is a circuit or a component that can electrically couple a corresponding bit line BL to a driver circuit250. In one aspect, the memory device100includes a plurality of bit line select transistors T1, where each bit line select transistor T1can be coupled between a corresponding bit line BL and a corresponding driver circuit250. InFIG.2, a bit line select transistor T1coupled to the bit line BL0is shown, and other bit line select transistors for other bit lines BL are not shown for simplicity. In some embodiments, the bit line select transistor T1can be replaced by a different component that can perform the functionalities of the bit line select transistor T1described herein. The bit line select transistor T1can be a BJT, MOSFET, FinFET, GaaFET, or any transistor. The bit line select transistor T1may be an N-type transistor. The bit line select transistor T1and the enable transistors222can be of the same type, such that the memory array120and the bit line select transistor T1can be implemented through the same fabrication process in a single layer. In one configuration, the bit line select transistor T1includes a first source/drain electrode coupled to the driver circuit250, a second source/drain electrode coupled to the bit line BL, and a gate electrode coupled to a controller (e.g., memory controller105) to receive a bit line select control signal215. In this configuration, the bit line select transistor T1can be enabled or disabled, according to the bit line select control signal215. For example, the bit line select transistor T1can be enabled, in response to the bit line select control signal215having an enable voltage (e.g., VDD or higher). When the bit line select transistor T1is enabled, the driver circuit250can be electrically coupled to the bit line BL, such that the driver circuit250can apply a voltage to the bit line BL. For example, the bit line select transistor T1can be disabled, in response to the bit line select control signal215having a disable voltage (e.g., 0V or lower). When the bit line select transistor T1is disabled, the driver circuit250can be electrically decoupled from the bit line BL, such that a voltage from the driver circuit250may not be applied to the bit line BL.

The bit line sense transistor T2is a circuit or a component that can sense a voltage at the bit line BL. In one aspect, the memory device100includes a plurality of bit line sense transistors T2, where each bit line sense transistor T2can be coupled between a corresponding bit line BL and a sensor280. InFIG.2, a bit line sense transistor T2coupled to the bit line BL0is shown, and other bit line sense transistors for other bit lines BL are not shown for simplicity. In some embodiments, the bit line sense transistor T2can be replaced by a different component that can perform the functionalities of the bit line sense transistor T2described herein. The bit line sense transistor T2can be a BJT, MOSFET, FinFET, GaaFET, or any transistor. The bit line sense transistor T2may be an N-type transistor. The bit line select transistor T1, the bit line sense transistor T2, and the enable transistors222can be of the same type, such that the memory array120, the bit line select transistor T1, and the bit line sense transistor T2can be implemented through the same fabrication process in a single layer. In one configuration, the bit line sense transistor T2includes a gate electrode coupled to the bit line BL, and a first source/drain electrode coupled to the sensor280. A second source/drain electrode of the bit line sense transistor T2can be coupled to a metal rail providing a ground voltage (e.g., 0V). The sensor280can be a current sensor or a voltage sensor. In this configuration, the bit line sense transistor T2can conduct current, according to a voltage of the bit line BL. Hence, by setting or adjusting a voltage of the bit line BL according to data stored by a memory cell125, the bit line sense transistor T2can conduct current corresponding to the data stored. Moreover, the sensor280can detect the current through bit line sense transistor T2to determine the data stored by the memory cell125.

Advantageously, the disclosed memory device100can be implemented in an area efficient manner. In some cases, a memory device including DRAM memory cells (e.g., memory cells125) may include complex circuits for programming and reading data. The disclosed memory device100implements, for a bit line BL, a bit line select transistor T1and a bit line sense transistor T2having a simple configuration. By implementing the bit line select transistor T1and the bit line sense transistor T2, complex circuits for programming or reading data can be obviated. In one aspect, the bit line select transistor T1, the bit line sense transistor T2, and enable transistors222of the memory cells125can be of a same type. Hence, the bit line select transistor T1, the bit line sense transistor T2, and the enable transistors222of the memory cells125can be implemented in a same layer through the same fabrication process. By implementing the bit line select transistor T1and the bit line sense transistor T2in the same layer of the memory cells125, the memory device100can have a simple configuration and can be implemented in an area efficient manner.

FIG.3illustrates a timing diagram300of operating a memory device100, in accordance with some embodiments. The timing diagram300includes voltage waveforms310,320,330. The voltage waveform310shows a voltage output from a driver circuit250. The voltage waveform320shows a voltage of a word line WL connected to a selected memory cell125. The voltage waveform330shows a voltage of a bit line select control signal215applied to a gate electrode of a bit line select transistor T1coupled to the selected memory cell125. In one approach, the memory device100operates in four phases: an initialization phase, a writing phase, a retention phase, and a reading phase.

In the initialization phase during a first time period, the driver circuit250may generate a ground voltage (or 0V). In the initialization phase, the bit line controller112may apply a reference voltage (e.g., ½ VDD or 0.5V) to the select line SL. In the initialization phase, the word line controller114may generate an enable voltage325(e.g., VDD or higher), and may apply the enable voltage325to a word line WL coupled to a gate electrode of an enable transistor222in a selected memory cell125. In response to the enable voltage325, the enable transistor222in the selected memory cell125can be enabled to electrically couple a storage component228of the selected memory cell125to the bit line BL. In the initialization phase, the memory controller105or the timing controller110may generate an enable voltage335(e.g., VDD or higher), and may apply the enable voltage335to a gate electrode of a bit line select transistor T1coupled to the selected memory cell125. In response to the enable voltage335, the bit line select transistor T1coupled to the selected memory cell125can be enabled to electrically couple the driver circuit250to the bit line BL coupled to the selected memory cell125. Hence, the ground voltage (or 0V) output from the driver circuit250can be applied to the storage component228of the selected memory cell125through the bit line select transistor T1and the enable transistor222of the selected memory cell125. By applying the ground voltage (or 0V) to the storage component228of the selected memory cell125, the storage component228of the selected memory cell125can be initialized or discharged. In some embodiments, initialization can be performed for a set of memory cells125simultaneously by applying the enable voltage325(e.g., VDD or higher) to word lines WL coupled to gate electrodes of enable transistors222in the set of memory cells125.

In the programming phase during a second time period after the first time period for the initialization phase, the driver circuit250may generate a voltage corresponding to a data to store. For example, the driver circuit250can generate a first voltage (e.g., VDD or 1V) to program the selected memory cell125to store a first logic state. For example, the driver circuit250can generate a second voltage (e.g., 0V) lower than the first voltage to program the selected memory cell125to store a second logic state. In the programming phase, the bit line controller112may apply a reference voltage (e.g., ½ VDD or 0.5V) to the select line SL. In the programming phase, the word line controller114may generate the enable voltage325(e.g., VDD or higher), and may apply the enable voltage325to the word line WL coupled to the gate electrode of the enable transistor222in the selected memory cell125. In response to the enable voltage325, the enable transistor222in the selected memory cell125can be enabled to electrically couple the storage component228of the selected memory cell125to the bit line BL. In the programming phase, the word line controller114may generate a disable voltage328(e.g., 0V or lower), and may apply the disable voltage328to a word line WL coupled to a gate electrode of an enable transistor222in an unselected memory cell125of the set of memory cells125. In response to the disable voltage328, the enable transistor222in the unselected memory cell125can be disabled to electrically decouple a storage component228of the unselected memory cell125from the bit line BL to prevent the unselected memory cell125from being programmed. In the programming phase, the memory controller105or the timing controller110may generate the enable voltage335(e.g., VDD or higher), and may apply the enable voltage335to the gate electrode of the bit line select transistor T1coupled to the selected memory cell125. In response to the enable voltage335, the bit line select transistor T1coupled to the selected memory cell125can be enabled to electrically couple the driver circuit250to the bit line BL coupled to the selected memory cell125. Hence, the voltage output from the driver circuit250can be applied to the storage component228of the selected memory cell125through the bit line select transistor T1and the enable transistor222of the selected memory cell125. By applying the voltage corresponding to the data to store to the storage component228, the storage component228can store charges corresponding to the applied voltage.

In the retention phase during a third time period after the second time period for the programming phase, the driver circuit250may generate a reference voltage (e.g., ½ VDD or between the first voltage (e.g., VDD or 1V) and the second voltage (e.g., 0V). In the retention phase, the bit line controller112may apply the reference voltage (e.g., ½ VDD or to the select line SL. In one aspect, retaining data is performed for a set of memory cells125, such that programming or reading data for an individual memory cell125in the set of memory cells125may not be performed. In the retention phase, the word line controller114may generate a disable voltage328(e.g., 0V or lower), and may apply the disable voltage328to word lines WL coupled to gate electrodes of the enable transistors222in a set of memory cells125. In response to the disable voltage328, the enable transistors222in the set of memory cells125can be disabled to electrically decouple the storage components228of the set of memory cells125from the bit line BL. In the retention phase, the memory controller105or the timing controller110may generate the enable voltage335(e.g., VDD or higher), and may apply the enable voltage335to the gate electrode of the bit line select transistor T1coupled to the set of memory cells125. In response to the enable voltage335, the bit line select transistor T1coupled to the set of memory cells125can be enabled to electrically couple the driver circuit250to the bit line BL. Hence, the reference voltage315output from the driver circuit250can be applied to the bit line BL, but not to the storage components228of the set of memory cells125. Accordingly, the bit line BL can be pre-charged to have the reference voltage (e.g., ½ VDD or 0.5V), while the set of memory cells125can retain programmed or stored data.

In the reading phase during a fourth time period after the third time period for the retention phase, the driver circuit250may generate the reference voltage (e.g., ½ VDD or 0.5V) or the ground voltage (e.g., 0V). In the reading phase, the bit line controller112may apply the reference voltage (e.g., ½ VDD or 0.5V) to the select line SL. In the reading phase, the word line controller114may generate the enable voltage325(e.g., VDD or higher), and may apply the enable voltage325to the word line WL coupled to the gate electrode of the enable transistor222in the selected memory cell125. In response to the enable voltage325, the enable transistor222in the selected memory cell125can be enabled to electrically couple the storage component228of the selected memory cell125to the bit line BL. In the reading phase, the word line controller114may generate a disable voltage328(e.g., 0V or lower), and may apply the disable voltage328to a word line WL coupled to a gate electrode of an enable transistor222in an unselected memory cell125of the set of memory cells125. In response to the disable voltage328, the enable transistor222in the unselected memory cell125can be disabled to electrically decouple a storage component228of the unselected memory cell125from the bit line BL to prevent the unselected memory cell125from discharging. In the reading phase, the memory controller105or the timing controller110may generate a disable voltage338(e.g., 0V or lower), and may apply the disable voltage338to the gate electrode of the bit line select transistor T1coupled to the selected memory cell125. In response to the disable voltage338, the bit line select transistor T1can be disabled to electrically decouple the driver circuit250from the bit line BL. Hence, the voltage output from the driver circuit250may not be applied to the storage component228of the selected memory cell125, and the storage component228of the selected memory cell125can discharge according to the data stored. In one aspect, a voltage of the bit line BL can be changed or adjusted, according to the data stored by the selected memory cell125. For example, if the selected memory cell125stored a first logic state, then a voltage of the bit line BL may become higher than the reference voltage (e.g., ½ VDD or 0.5V). For example, if the selected memory cell125stored a second logic state, then a voltage of the bit line BL may become lower than the reference voltage (e.g., ½ VDD or 0.5V). The bit line sense transistor T2can detect a change in a voltage of the bit line BL, and conduct current by an amount corresponding to the voltage of the bit line BL. The sensor280can detect a current through the bit line sense transistor T2, and determine the data stored by the selected memory cell125. After reading data stored by a set of memory cells in the reading phase, the set of memory cells125can be reset in the initialization phase and can be reprogrammed.

FIG.4illustrates a schematic block diagram of a portion400of an example memory array120and circuits (e.g., a driver circuit250, a sensor280, a bit line select transistor T1, a bit line sense transistor T2, and a load transistor T3) for programming and reading data stored by the memory array120, in accordance with some embodiments. The schematic block shown inFIG.4is similar to the schematic block diagram inFIG.2, except the load transistor T3is coupled to a drain electrode of the bit line sense transistor T2and a source electrode of the bit line sense transistor T2is coupled to a metal rail providing the ground voltage (e.g., 0V). Thus, detailed description of duplicated portion thereof is omitted herein for the sake of brevity.

In one configuration, the load transistor T3is a circuit or a component that can act as a resistive load. In some embodiments, the load transistor T3can be replaced by a different component (e.g., resistor or a different transistor) that can perform the functionalities of the load transistor T3described herein. The load transistor T3can be BJT, MOSFET, FinFET, GaaFET, or any transistor. The load transistor T3may be an N-type transistor. The bit line select transistor T1, the bit line sense transistor T2, the load transistor T3, and the enable transistors222can be of the same type, such that the memory array120, the bit line select transistor T1, the bit line sense transistor T2, and the load transistor T3can be implemented through the same fabrication process in a single layer. In one configuration, the load transistor T3includes a source electrode coupled a drain electrode of the bit line sense transistor T2, a gate electrode coupled to a drain electrode of the load transistor T3, and the drain electrode coupled to a metal rail providing a supply voltage (e.g., VDD). In this configuration, the transistor T3can operate as a diode to provide a resistive load and generate a voltage at the drain electrode of the load transistor T2, according to the current through the bit line sense transistor T2. In this embodiment, the sensor280can be implemented as a voltage sensor. By generating the voltage corresponding to the current through the bit line sense transistor T2, the sensor280can be implemented with a simple logic circuit, rather than a complex current sensor.

FIG.5illustrates example layers500of a memory device100, in accordance with some embodiments. In some embodiments, the memory device100is formed in two layers510,520. In one implementation, the layer510includes the memory array120, and the layer520includes circuits (e.g., memory controller105) for operating the memory array120. In one aspect, the bit line select transistor T1, the bit line sense transistor T2, the load transistor T3, or any combination of them can be implemented in the layer510with the memory array120. By implementing the bit line select transistor T1, the bit line sense transistor T2, and/or the load transistor T3as described above with respect toFIG.2orFIG.4in the same layer of the memory array120, circuits (e.g., memory controller105) for operating the memory array120in the layer520can be simplified and formed under the layer510to achieve area efficiency.

FIG.6is a flowchart showing a method600of programming a memory device (e.g., memory device100), in accordance with some embodiments. In some embodiments, the method600is performed by a controller (e.g., memory controller105). In some embodiments, the method600is performed by other entities. In some embodiments, the method600is performed in the programming phase. In some embodiments, the method600includes more, fewer, or different steps than shown inFIG.6. In some embodiments, the method600can be performed in a different order than shown inFIG.6.

In one approach, the controller selects610, from a set of memory cells125, a memory cell125to program. The set of memory cells125may be DRAM memory cells. Each memory cell125of the set of memory cells125may include a corresponding enable transistor222and a corresponding storage component228(e.g., capacitor) coupled in series between a bit line BL and a select line SL. A gate electrode of the selected memory cell125may be coupled to a word line WL, which may be coupled to a gate electrode of a memory cell125in another set of memory cells125. Each memory cell125of the another set of memory cells125may include a corresponding enable transistor222and a corresponding storage component228(e.g., capacitor) coupled in series between another bit line BL and the select line SL.

In one approach, the controller enables620a bit line select transistor T1coupled to the selected memory cell125. In one example, a first bit line select transistor T1can be coupled to a first bit line BL coupled to a first set of memory cells125including the selected memory cell125, and a second bit line select transistor T1can be coupled to a second bit line BL coupled to a second set of memory cells125not including the selected memory cell125. The controller can apply an enable voltage (e.g., enable voltage335) to a gate electrode of the first bit line select transistor T1, such that the first bit line select transistor T1can be enabled. The controller can apply a disable voltage (e.g., disable voltage338) to a gate electrode of the second bit line select transistor T1, such that the second bit line select transistor T1can be disabled.

In one approach, the controller enables630an enable transistor222in the selected memory cell125. The controller can apply an enable voltage (e.g., enable voltage325) to a gate electrode of the enable transistor222in the selected memory cell125, such that the enable transistor222in the selected memory cell125can be enabled. The controller can apply a disable voltage (e.g., disable voltage328) to a gate electrode of an enable transistor222in an unselected memory cell125of the set of memory cells125, such that the enable transistor222in the unselected memory cell125can be disabled.

In one approach, the controller applies640a data voltage to the selected memory cell125through the bit line select transistor T1. For example, the controller can generate a first voltage (e.g., VDD or 1V) as the data voltage to program the selected memory cell125to store a first logic state. For example, the controller can generate a second voltage (e.g., 0V) as the data voltage to program the selected memory cell125to store a second logic state. By enabling the bit line select transistor T1in the step620, the controller can apply the data voltage to the bit line BL coupled to the selected memory cell125. Moreover, by enabling the enable transistor222in the selected memory cell125in the step630, the data voltage can be applied to the storage component228in the selected memory cell125, such that the storage component228can be charged or programmed.

FIG.7is a flowchart showing a method700of retaining data stored by a memory device (e.g., memory device100), in accordance with some embodiments. In some embodiments, the method700is performed by a controller (e.g., memory controller105). In some embodiments, the method700is performed by other entities. In some embodiments, the method700is performed in the retention phase. In some embodiments, the method700includes more, fewer, or different steps than shown inFIG.7. In some embodiments, the method700can be performed in a different order than shown inFIG.7.

In one approach, the controller selects710a set of memory cells125to retain data. In one aspect, retaining data is performed for a set of memory cells125, such that programming or reading data for an individual memory cell125in the set of memory cells125may not be performed.

In one approach, the controller disables720enable transistors222in the set of memory cells125. The controller can apply a disable voltage (e.g., disable voltage328) to gate electrodes of enable transistors222in the set of memory cells125, such that the enable transistors222in the set of memory cells125can be disabled.

In one approach, the controller enables730a bit line select transistor T1coupled to the set of memory cells125. The controller can apply an enable voltage (e.g., enable voltage335) to a gate electrode of the bit line select transistor T1, such that the bit line select transistor T1can be enabled.

In one approach, the controller applies740a reference voltage (e.g., ½ VDD or 0.5V) to the bit line BL through the bit line select transistor T1. The reference voltage can be between the first voltage (e.g., VDD or 1V) corresponding to a first logic state and the second voltage (e.g., GND or 0V) corresponding to a second logic state. Because the bit line select transistor T1is enabled in the step730, the reference voltage can be applied to the bit line BL through the bit line select transistor T1, and the bit line BL can be pre-charged to have the reference voltage (e.g., ½ VDD or 0.5V). Meanwhile, because the enable transistors222in the set of memory cells125are disabled in the step720, storage components228of the set of memory cells125can be electrically decoupled from the bit line BL. Accordingly, the reference voltage may not be applied to the storage components228of the set of memory cells125, thereby allowing the set of memory cells125to maintain data.

FIG.8is a flowchart showing a method800of reading data stored by a memory device (e.g., memory device100), in accordance with some embodiments. In some embodiments, the method800is performed by a controller (e.g., memory controller105). In some embodiments, the method800is performed by other entities. In some embodiments, the method800is performed in the reading phase. In some embodiments, the method800includes more, fewer, or different steps than shown inFIG.8. In some embodiments, the method800can be performed in a different order than shown inFIG.8.

In one approach, the controller selects810, from a set of memory cells125, a memory cell125to read data.

In one approach, the controller disables820a bit line select transistor T1coupled to the selected memory cell125. In one example, the controller can apply a disable voltage (e.g., disable voltage338) to a gate electrode of the bit line select transistor T1, such that the first bit line select transistor T1can be disabled. The controller can apply an enable voltage (e.g., enable voltage335) to a gate electrode of another bit line select transistor T1, such that the another bit line select transistor T1can be enabled.

In one approach, the controller enables830an enable transistor222in the selected memory cell125. The controller can apply an enable voltage (e.g., enable voltage325) to a gate electrode of the enable transistor222in the selected memory cell125, such that the enable transistor222in the selected memory cell125can be enabled. The controller can apply a disable voltage (e.g., disable voltage328) to a gate electrode of an enable transistor222in an unselected memory cell125of the set of memory cells125, such that the enable transistor222in the unselected memory cell125can be disabled.

In one approach, the controller determines840a data stored by the selected memory cell. In one aspect, by disabling the bit line select transistor T1in the step820and enabling the enable transistor222of the selected memory cell125in the step830, a voltage of the bit line BL can be changed or adjusted, according to the data stored by the selected memory cell125. For example, if the selected memory cell125stored a first logic state, then a voltage of the bit line BL may become higher than the reference voltage (e.g., ½ VDD or 0.5V). For example, if the selected memory cell125stored a second logic state, then a voltage of the bit line BL may become lower than the reference voltage (e.g., ½ VDD or 0.5V). In one configuration, the bit line BL is coupled to a gate electrode of the bit line sense transistor T2. Hence, the bit line sense transistor T2can detect a change in a voltage of the bit line BL, and conduct current by an amount corresponding to the voltage of the bit line BL. The sensor280can detect a current through the bit line sense transistor T2, and determine the data stored by the selected memory cell125according to the current through the bit line sense transistor T2.

Advantageously, the disclosed memory device100can be implemented in an area efficient manner. In some cases, a memory device including DRAM memory cells (e.g., memory cells125) may include complex circuits for programming and reading data. The disclosed memory device100implements, for a bit line BL, a bit line select transistor T1and a bit line sense transistor T2having a simple configuration. By implementing the bit line select transistor T1and the bit line sense transistor T2, complex circuits for programming or reading data can be obviated. In one aspect, the bit line select transistor T1, the bit line sense transistor T2, and enable transistors222of the memory cells125can be of a same type. Hence, the bit line select transistor T1, the bit line sense transistor T2, and the enable transistors222of the memory cells125can be implemented in a same layer (e.g.,510) through the same fabrication process. By implementing, the bit line select transistor T1and the bit line sense transistor T2in the same layer of the memory cells125, the memory device100can have a simple configuration and can be implemented in an area efficient manner.

Referring now toFIG.9, an example block diagram of a computing system900is shown, in accordance with some embodiments of the disclosure. The computing system900may be used by a circuit or layout designer for integrated circuit design. A “circuit” as used herein is an interconnection of electrical components such as resistors, transistors, switches, batteries, inductors, or other types of semiconductor devices configured for implementing a desired functionality. The computing system900includes a host device905associated with a memory device910. The host device905may be configured to receive input from one or more input devices915and provide output to one or more output devices920. The host device905may be configured to communicate with the memory device910, the input devices915, and the output devices920via appropriate interfaces925A,925B, and925C, respectively. The computing system900may be implemented in a variety of computing devices such as computers (e.g., desktop, laptop, servers, data centers, etc.), tablets, personal digital assistants, mobile devices, other handheld or portable devices, or any other computing unit suitable for performing schematic design and/or layout design using the host device905.

The input devices915may include any of a variety of input technologies such as a keyboard, stylus, touch screen, mouse, track ball, keypad, microphone, voice recognition, motion recognition, remote controllers, input ports, one or more buttons, dials, joysticks, and any other input peripheral that is associated with the host device905and that allows an external source, such as a user (e.g., a circuit or layout designer), to enter information (e.g., data) into the host device and send instructions to the host device. Similarly, the output devices920may include a variety of output technologies such as external memories, printers, speakers, displays, microphones, light emitting diodes, headphones, video devices, and any other output peripherals that are configured to receive information (e.g., data) from the host device905. The “data” that is either input into the host device905and/or output from the host device may include any of a variety of textual data, circuit data, signal data, semiconductor device data, graphical data, combinations thereof, or other types of analog and/or digital data that is suitable for processing using the computing system900.

The host device905includes or is associated with one or more processing units/processors, such as Central Processing Unit (“CPU”) cores930A . . .730N. The CPU cores930A . . .930N may be implemented as an Application Specific Integrated Circuit (“ASIC”), Field Programmable Gate Array (“FPGA”), or any other type of processing unit. Each of the CPU cores930A . . .930N may be configured to execute instructions for running one or more applications of the host device905. In some embodiments, the instructions and data to run the one or more applications may be stored within the memory device910. The host device905may also be configured to store the results of running the one or more applications within the memory device910. Thus, the host device905may be configured to request the memory device910to perform a variety of operations. For example, the host device905may request the memory device910to read data, write data, update or delete data, and/or perform management or other operations. One such application that the host device905may be configured to run may be a standard cell application935. The standard cell application935may be part of a computer aided design or electronic design automation software suite that may be used by a user of the host device905to use, create, or modify a standard cell of a circuit. In some embodiments, the instructions to execute or run the standard cell application935may be stored within the memory device910. The standard cell application935may be executed by one or more of the CPU cores930A . . .930N using the instructions associated with the standard cell application from the memory device910. In one example, the standard cell application935allows a user to utilize pre-generated schematic and/or layout designs of the memory device100or a portion of the memory device100to aid integrated circuit design. After the layout design of the integrated circuit is complete, multiples of the integrated circuit, for example, including the memory device100, or any portion of the memory device100can be fabricated according to the layout design by a fabrication facility.

Referring still toFIG.9, the memory device910includes a memory controller940that is configured to read data from or write data to a memory array945. The memory array945may include a variety of volatile and/or non-volatile memories. For example, in some embodiments, the memory array945may include NAND flash memory cores. In other embodiments, the memory array945may include NOR flash memory cores, Static Random Access Memory (SRAM) cores, Dynamic Random Access Memory (DRAM) cores, Magnetoresistive Random Access Memory (MRAM) cores, Phase Change Memory (PCM) cores, Resistive Random Access Memory (ReRAM) cores, 3D XPoint memory cores, ferroelectric random-access memory (FeRAM) cores, and other types of memory cores that are suitable for use within the memory array. The memories within the memory array945may be individually and independently controlled by the memory controller940. In other words, the memory controller940may be configured to communicate with each memory within the memory array945individually and independently. By communicating with the memory array945, the memory controller940may be configured to read data from or write data to the memory array in response to instructions received from the host device905. Although shown as being part of the memory device910, in some embodiments, the memory controller940may be part of the host device905or part of another component of the computing system900and associated with the memory device910. The memory controller940may be implemented as a logic circuit in either software, hardware, firmware, or combination thereof to perform the functions described herein. For example, in some embodiments, the memory controller940may be configured to retrieve the instructions associated with the standard cell application935stored in the memory array945of the memory device910upon receiving a request from the host device905.

It is to be understood that only some components of the computing system900are shown and described inFIG.9. However, the computing system900may include other components such as various batteries and power sources, networking interfaces, routers, switches, external memory systems, controllers, etc. Generally speaking, the computing system900may include any of a variety of hardware, software, and/or firmware components that are needed or considered desirable in performing the functions described herein. Similarly, the host device905, the input devices915, the output devices920, and the memory device910including the memory controller940and the memory array945may include other hardware, software, and/or firmware components that are considered necessary or desirable in performing the functions described herein.

In one aspect of the present disclosure, a memory device is disclosed. In some embodiments, the memory device includes a memory array. In some embodiments, the memory array includes a set of memory cells. In some embodiments, each of the set of memory cells includes a corresponding transistor and a corresponding capacitor connected in series between a bit line and a select line. In some embodiments, the memory device includes a first transistor and a second transistor. In some embodiments, the first transistor includes a source/drain electrode coupled to a controller, and another source/drain electrode coupled to the bit line. In some embodiments, the second transistor includes a gate electrode coupled to the bit line. In some embodiments, the second transistor is configured to conduct current corresponding to data stored by a memory cell of the set of memory cells.

In another aspect of the present disclosure, a memory device is disclosed. In some embodiments, the memory device includes a controller. In some embodiments, the memory device includes a first set of memory cells including a first memory cell and a second memory cell coupled in parallel between a first bit line and a select line. In some embodiments, the memory device includes a second set of memory cells including a third memory cell and a fourth memory cell coupled in parallel between a second bit line and the select line. In some embodiments, the memory device includes a first word line coupled to the first memory cell and the third memory cell. In some embodiments, the memory device includes a second word line coupled to the second memory cell and the fourth memory cell. In some embodiments, the memory device includes a first transistor coupled between the controller and the first bit line. In some embodiments, the memory device includes a second transistor including a gate electrode coupled to the first bit line. In some embodiments, the memory device includes a third transistor coupled between the controller and the second bit line. In some embodiments, the memory device includes a fourth transistor including a gate electrode coupled to the second bit line.

In yet another aspect of the present disclosure, a method of operating a memory device is disclosed. In some embodiments, the method includes enabling, by a controller, a first transistor during a first time period to program data to a memory cell of a set of memory cells. In some embodiments, the first transistor includes a source/drain electrode coupled to the controller and another source/drain electrode coupled to a bit line. In some embodiments, the bit line is coupled to the set of memory cells. In some embodiments, each of the set of memory cells includes a corresponding transistor and a corresponding capacitor connected in series between the bit line and a select line. In some embodiments, the bit line is coupled to a gate electrode of a second transistor. In some embodiments, the method includes enabling, by the controller, the corresponding transistor of the memory cell during the first time period. In some embodiments, the method includes applying, by the controller, a voltage corresponding to the data to the source/drain electrode of the first transistor during the first time period.

In some embodiments, the method includes disabling, by the controller, the first transistor during a second time period to read the data stored by the memory cell of the set of memory cells. In some embodiments, the method includes enabling, by the controller, the corresponding transistor of the memory cell during the second time period. In some embodiments, the method includes determining, by the controller, the data stored by the memory cell, according to a current through the second transistor.

In some embodiments, the voltage corresponding to a first logic state of the data is a first voltage, and the voltage corresponding to a second logic state of the data is a second voltage lower than the first voltage. In some embodiments, the method includes enabling, by the controller, the first transistor during a third time period to maintain the data stored by the memory cell. In some embodiments, the method includes applying, by the controller, a third voltage to the source/drain electrode of the first transistor during the third time period. The third voltage may be between the first voltage and the second voltage. In some embodiments, the method includes disabling, by the controller, the corresponding transistor of the memory cell during the third time period. The third time period may be between the first time period and the second time period.

The term “coupled” and variations thereof includes the joining of two members directly or indirectly to one another. The term “electrically coupled” and variations thereof includes the joining of two members directly or indirectly to one another through conductive materials (e.g., metal or copper traces). Such joining may be stationary (e.g., permanent or fixed) or moveable (e.g., removable or releasable). Such joining may be achieved with the two members coupled directly with or to each other, with the two members coupled with each other using a separate intervening member and any additional intermediate members coupled with one another, or with the two members coupled with each other using an intervening member that is integrally formed as a single unitary body with one of the two members. If “coupled” or variations thereof are modified by an additional term (e.g., directly coupled), the generic definition of “coupled” provided above is modified by the plain language meaning of the additional term (e.g., “directly coupled” means the joining of two members without any separate intervening member), resulting in a narrower definition than the generic definition of “coupled” provided above. Such coupling may be mechanical, electrical, or fluidic.