Semiconductor devices including a gate core and a fin active core and methods of fabricating the same

Semiconductor devices and methods of fabricating the same are provided. The methods may include forming an isolation region defining a fin active region, forming a sacrificial field gate pattern on the isolation region and forming a sacrificial fin gate pattern on the fin active region. The method may also include forming a field gate cut zone comprising a first recess exposing a surface of the isolation region and a fin active cut zone comprising a second recess exposing a surface of the fin active region, forming a fin active recess in the second recess of the fin active cut zone and forming a field gate core and a fin active core by forming an insulation material in the first recess of the field gate cut zone and the fin active recess, respectively.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims priority under 35 U.S.C. §119 to Korean Patent Application No. 10-2014-0140977 filed on Oct. 17, 2014, the disclosure of which is hereby incorporated by reference in its entirety.

BACKGROUND

Embodiments of the inventive concept relate to semiconductor devices including a gate core and a fin active core and methods of fabricating the same.

In order to implement a logic circuit including a plurality of fin active regions in a semiconductor device, portions of gate electrodes and portions of fin active regions may be removed at predetermined locations using a fin active cutting process and/or a gate cutting process.

SUMMARY

Some embodiments of the inventive concept provide semiconductor devices including a gate core and a fin active core.

Some embodiments of the inventive concept provide a method of fabricating semiconductor devices including a gate core and a fin active core.

A method of fabricating a semiconductor device may include forming an isolation region defining a fin active region on a substrate, forming a sacrificial field gate pattern on the isolation region and forming a sacrificial fin gate pattern on the fin active region, forming a first interlayer insulating layer between the sacrificial field gate pattern and the sacrificial fin gate pattern, forming a field gate cut zone including a first recess exposing a surface of the isolation region by removing a first portion of the sacrificial field gate pattern and a fin active cut zone including a second recess exposing a surface of the fin active region by removing a first portion of the sacrificial fin gate pattern, forming a fin active recess by removing the fin active region exposed in the second recess of the fin active cut zone, forming a field gate core and a fin active core by forming an insulation material in the first recess of the field gate cut zone and the fin active recess, respectively, forming a field gate electrode opening by removing a second portion of the sacrificial field gate pattern and forming a fin gate electrode opening by removing a second portion of the sacrificial fin gate pattern and forming a field gate pattern in the field gate electrode opening and forming a fin gate pattern in the fin gate electrode opening.

In various embodiments, the method may also include forming a base insulating layer between the fin active region and the sacrificial fin gate pattern using a deposition process.

According to various embodiments, the forming of the isolation region may include forming a trench including a deep trench and a shallow trench in the substrate and forming a trench insulation material filling the deep trench and partially filling the shallow trench.

In various embodiments, the sacrificial field gate pattern and the sacrificial fin gate pattern may include polysilicon, the first interlayer insulating layer may include silicon oxide, and the field gate core and the fin active core may include silicon nitride.

In various embodiments, the method may also include forming a fin gate cut zone including a third recess by removing a third portion of the sacrificial fin gate pattern and forming a fin gate core by forming the insulation material in the third recess of the fin gate cut zone.

According to various embodiments, the method may also include forming a sacrificial dummy gate pattern on the isolation region, forming a dummy gate electrode opening by removing the sacrificial dummy gate pattern and forming a dummy gate pattern in the dummy gate electrode opening.

In various embodiments, the method may further include forming a sacrificial butting gate pattern overlapping both the isolation region and the fin active region, forming a butting gate electrode opening by removing the sacrificial butting gate pattern and forming a butting gate pattern in the butting gate electrode opening.

According to various embodiments, the method may further include forming a source/drain region in the fin active region adjacent the fin gate pattern, forming a contact pattern extending through the first interlayer insulating layer and connecting to the source/drain region, forming a second interlayer insulating layer on the contact pattern and forming a via pattern extending through the second interlayer insulating layer and connecting to the contact pattern.

In various embodiments, the forming of the source/drain region may include performing an epitaxial growth process. The contact pattern may include a silicide layer directly on the source/drain region, a contact barrier layer on the silicide layer, and a contact plug on the contact barrier layer.

A method of fabricating a semiconductor device may include forming an isolation region in a substrate. The substrate may include a field area and an active area, and the isolation region may define a fin active region in the active area. The method may also include forming a sacrificial first field gate pattern on the isolation region of the field area and forming a sacrificial first fin gate pattern and a sacrificial second fin gate pattern on the fin active region and the isolation region of the active area, forming a first field gate cut zone including a first recess exposing the isolation region by removing a portion of the sacrificial first field gate pattern and a fin gate cut zone including a second recess exposing the fin active region by removing a portion of the sacrificial second fin gate pattern, forming a fin active recess by removing a portion of the fin active region exposed in the second recess of the fin gate cut zone, forming a first field gate core, a fin gate core, and a fin active core in the first recess of the first field gate cut zone, the second recess of the fin gate cut zone, and the fin active recess, respectively. The first field gate core, the fin gate core, and the fin active core may include the same material. The method may further include forming a first fin gate electrode opening by removing a portion of the sacrificial first fin gate pattern and forming a first fin gate pattern in the first fin gate electrode opening.

In various embodiments, the method may further include forming a sacrificial second field gate pattern on the isolation region of the field area, forming a second field gate cut zone including a third recess by removing a portion of the sacrificial second field gate pattern and forming a second field gate core in the third recess of the second field gate cut zone.

According to various embodiments, the first field gate core, the fin gate core, and the fin active core may include silicon nitride, and the second field gate core may include silicon oxide.

In various embodiments, the method may also include forming a sacrificial dummy field gate pattern on the isolation region of the field area, forming a dummy field gate electrode opening by removing the sacrificial dummy field gate pattern and forming a dummy field gate pattern in the dummy field gate electrode opening.

According to various embodiments, the method may further include forming a sacrificial butting gate pattern on the isolation region and the fin active region of the active area, forming a butting gate electrode opening by removing the sacrificial butting gate pattern and forming a butting gate pattern in the butting gate electrode opening.

In various embodiments, upper surfaces of the first field gate core, the fin gate core, the fin active core, and the first fin gate pattern may be coplanar.

A semiconductor device may include an isolation region defining a fin active region in a substrate, a first cut field gate pattern on the isolation region and a first fin gate pattern on the fin active region. The first cut field gate pattern may include an insulating first cut field gate core and a conductive first cut field gate electrode. The first fin gate pattern may include an insulating first fin gate core and a conductive first fin gate electrode. An upper surface of the first cut field gate core and an upper surface of the first fin gate core may be coplanar.

In various embodiments, the first cut field gate pattern further may include a first cut field gate barrier layer surrounding side surfaces and a lower surface of the first cut field gate electrode, a first cut field gate insulating layer surrounding side surfaces and a lower surface of the first cut field gate barrier layer and first cut field gate spacers on side surfaces of the first cut field gate core and on the side surfaces of the first cut field gate barrier layer. Upper surfaces of the first cut field gate core, the first cut field gate insulating layer, the first cut field gate barrier layer, the first cut field gate electrode, and the first cut field gate spacers may be coplanar.

According to various embodiments, the device may further include a second cut field gate pattern having an upper surface which is coplanar with the upper surface of the first cut field gate pattern on the isolation region. The second cut field gate pattern may include an insulating second cut field gate core, a conductive second cut field gate electrode, a second cut field gate barrier layer on side surfaces and a lower surface of the second cut field gate electrode, a second cut field gate insulating layer on side surfaces and a lower surface of the second cut field gate barrier layer and second cut field gate spacers on side surfaces of the second cut field gate core and on the side surfaces of the second cut field gate barrier layer.

In various embodiments, the first fin gate pattern further may include a first fin gate barrier layer surrounding side surfaces and a lower surface of the first fin gate electrode, a first fin gate insulating layer surrounding side surfaces and a lower surface of the first fin gate barrier layer and first fin gate spacers on side surfaces of the first fin gate core and on the side surfaces of the first fin gate barrier layer. Upper surfaces of the first fin gate core, the first fin gate insulating layer, the first fin gate barrier layer, the first fin gate electrode, and the first fin gate spacers may be coplanar.

According to various embodiments, the device may further include a second fin gate pattern having an upper surface which is coplanar with the upper surface of the first fin gate pattern on the fin active region. The second fin gate pattern may include an insulating second fin gate core, a conductive second fin gate electrode, a second fin gate barrier layer on side surfaces and a lower surface of the second fin gate electrode, a second fin gate insulating layer on side surfaces and a lower surface of the second fin gate barrier layer and second fin gate spacers on side surfaces of the second fin gate core and on the side surfaces of the second fin gate barrier layer.

In various embodiments, the fin active region which overlaps the second fin gate core may include an insulating fin active core in a fin active recess.

In various embodiments, a lower surface of the first fin gate core may protrude into the isolation region to be lower than a lower surface of the first cut field gate insulating layer.

A semiconductor device may include a substrate including a field area including an isolation region and an active area including a fin active region defined by the isolation region. The fin active region may extend in an X direction. The device may also include a first cut field gate pattern extending in a Y direction on the isolation region of the field area, a field gate cut-zone extending in the X direction and crossing the first cut field gate pattern, a fin gate pattern extending in the Y direction and crossing the fin active region and the isolation region in the active area, a fin gate cut-zone extending in the X direction and crossing the fin gate pattern and a fin active cut-zone extending in the Y direction and overlapping a portion of the fin gate pattern. The Y direction may be different from the X direction. The first cut field gate pattern may include an insulating first cut field gate core in a region which overlaps the field gate cut-zone and a conductive first cut field gate electrode in a region which does not overlap the field gate cut-zone. The fin gate pattern may include an insulating fin gate core in a region which overlaps the fin gate cut-zone, an insulating fin active core in a region which overlaps the fin active cut-zone and a conductive fin gate electrode in a region which does not overlap the fin gate cut-zone and the fin active cut-zone.

In various embodiments, the device may further include a second cut field gate pattern that extends parallel to the first cut field gate pattern on the isolation region of the field area. The second cut field gate pattern may include an insulating second cut field gate core in a region which overlaps the field gate cut-zone and a conductive second cut field gate electrode in a region which does not overlap the field gate cut-zone, the first cut field gate core may include the same material as the fin active core, and the second cut field gate core may include a material different from the fin active core.

According to various embodiments, the device may further include a dummy field gate pattern that extends parallel to the first cut field gate pattern and does not to overlap the field gate cut-zone. The dummy field gate pattern may include a dummy gate insulating layer on the isolation region, a dummy gate barrier layer on the dummy gate insulating layer and a dummy gate electrode on the dummy gate barrier layer.

In various embodiments, the device may further include a butting gate pattern that crosses one end of the fin active region in the active area and does not to overlap the fin active cut-zone. The butting gate pattern may include an insulating butting gate core in a region which overlaps the fin gate cut-zone and a conductive butting gate electrode in a region which does not overlap the fin gate cut-zone.

According to various embodiments, upper surfaces of the first cut field gate core, the fin gate core, and the fin active core may be coplanar.

In various embodiments, the device may further include a source/drain region in the fin active region adjacent the fin gate pattern. The source/drain region may protrude from a surface of the fin active region, and the source/drain region may include one of a silicon germanium (SiGe) layer, a silicon carbide (SiC) layer, or a silicon (Si) layer, which is formed by an epitaxial growth process.

In various embodiments, the device may further include a contact pattern on the source/drain region. The contact pattern may include a silicide layer directly on the source/drain region, a contact barrier layer on the silicide layer and a contact plug on the contact barrier layer.

According to various embodiments, the device may also include a via pattern on the contact pattern. The via pattern may include a via barrier layer on the contact pattern and a via plug on the via barrier layer.

A method of fabricating a semiconductor device may include forming a fin active region in a first region of a substrate. The substrate may include the first region and a second region. The method may also include forming an isolation region in the first region and the second region of the substrate. The isolation region may be adjacent the fin active region. The method may further include forming a first gate line in the first region of the substrate, forming a second gate line extending on the isolation region in the second region of the substrate, concurrently removing a portion of the first gate line disposed on the fin active region to form a first recess in the first gate line and a portion of the second gate line to form a second recess in the second gate line, removing a portion of the fin active region exposed by the first recess of the first gate line to form a third recess in the fin active region and forming a first insulating core pattern in the first and third recesses and a second insulating core pattern in the second recess. The first gate line may traverse the fin active region and may extend on the isolation region.

In various embodiments, the method may further include forming a third gate line in the first region of the substrate, removing a portion of the third gate line disposed on the isolation region to form a fourth recess in the third gate line concurrently with removing the portion of the first gate line to form the first recess and the portion of the second gate line to form the second recess and forming a third insulating core pattern in the third recess. The third gate line may traverse the fin active region and the isolation region.

According to various embodiments, upper surfaces of the first, second and third insulating core patterns may be coplanar.

In various embodiments, the first and second insulating core patterns may include silicon nitride.

According to various embodiments, the method may also include forming a source/drain region in the fin active region adjacent a side of the first gate line before concurrently removing the portion of the first gate line and the portion of the second gate line.

DETAILED DESCRIPTION OF THE EMBODIMENTS

Various embodiments will now be described more fully with reference to the accompanying drawings in which some embodiments are shown. The inventive concept may, however, be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure is thorough and complete and fully conveys the inventive concept to those skilled in the art.

The example embodiments of the inventive concept will be described with reference to cross-sectional views and/or plan views, which are ideal views. Thicknesses of layers and areas are exaggerated for effective description of the technical contents in the drawings. Forms of the embodiments may be modified by the manufacturing technology and/or tolerance. Therefore, the embodiments of the inventive concept are not intended to be limited to illustrated specific forms, and include modifications of forms generated according to manufacturing processes. For example, an etching area illustrated at a right angle may be round or have a predetermined curvature. Therefore, areas illustrated in the drawings have overview properties, and shapes of the areas are illustrated special forms of the areas of a device and are not intended to be limited to the scope of the inventive concept.

Hereinafter, like reference numerals in the drawings denote like elements throughout the specification. Therefore, although like reference numerals or similar reference numerals are not mentioned or described in the drawing, it will be described with reference to the other drawings. Further, although reference numerals are not illustrated, it will be described with reference to the other drawings.

FIG. 1is a layout of a semiconductor device in accordance with some embodiments of the inventive concept.

Referring toFIG. 1, the semiconductor device in accordance with some embodiments of the inventive concept may include an insulating field area FA and a conductive active area AA.

The field area FA may include field gate lines10,20, and30which extend in a Y direction on an isolation region110.

The field gate lines10,20, and30may include cut field gate lines10and20and a dummy field gate line30. The cut field gate lines10and20may include a first cut field gate line10which has a relatively narrow width and a second cut field gate line20which has a relatively wide width. The cut field gate lines10and20each may be separated by a field gate cut-zone CZ1that overlaps the cut field gate lines10and20.

The field gate cut-zone CZ1may separate each of the cut field gate lines10and20and may extend in an X direction. The dummy field gate line30may continuously extend in the Y direction without being separated by the field gate cut-zone CZ1.

The active area AA may include fin active regions130, which extend in parallel in the X direction, the isolation region110, and a first fin gate line40, a second fin gate line50, and a butting gate line60. The first fin gate line40, the second fin gate line50and the butting gate line60extend in the Y direction to cross the fin active regions130and the isolation region110.

The fin active regions130and the isolation region110may be alternately disposed in the Y direction.

The butting gate line60may partially overlap and cross one end portion of each fin active regions130and the isolation region110. For example, the butting gate line60may not completely cross the fin active regions130.

The first and second fin gate lines40and50and the butting gate line60each may be separated by a fin gate cut-zone CZ2that overlaps the first and second fin gate lines40and50and the butting gate line60. The fin gate cut-zone CZ2may extend in the X direction and separate the first and second fin gate lines40and50and the butting gate line60.

Some of the fin active regions130may be separated by a fin active cut-zone CZ3that overlaps the some of the fin active regions130. The fin active cut-zone CZ3may overlap a portion of the second fin gate line50, may extend in the Y direction, and may separate the some of the fin active regions130. The second fin gate line50may not extend or may not be formed in the fin active cut-zone CZ3. For example, a portion of the second fin gate line50, which overlaps the fin active cut-zone CZ3, is removed and is not formed.

The fin gate cut-zone CZ2and the fin active cut-zone CZ3may partially overlap. Alternatively, the fin gate cut-zone CZ2and the fin active cut-zone CZ3may be merged as one cut-zone.

FIGS. 2A to 2Care cross-sectional views of a semiconductor device taken along the lines I-I′, II-II′, and III-III′ ofFIG. 1in accordance with some embodiments of the inventive concept. The gate “lines”10,20,30,40,50, and60ofFIG. 1will be described as gate “patterns.”

Referring toFIGS. 2A to 2C, the semiconductor device in accordance with some embodiments of the inventive concept may include an isolation region110formed in a substrate100including a field area FA and an active area AA, and a fin active region130defined by the isolation region110.

The substrate100may include a silicon wafer.

The isolation region110may include a deep trench111, a shallow trench112, and a trench insulation material113which completely fills the deep trench111and partially fills the shallow trench112. The trench insulation material113may include, for example, silicon oxide. The fin active region130may protrude upward beyond an upper surface of the isolation region110. The fin active region130may be a portion of the substrate100.

A surface insulating layer132may be formed on the fin active region130. The surface insulating layer132may include, for example, oxidized silicon formed by oxidation of a surface of the fin active region130.

The semiconductor device may include cut field gate patterns10and20, and a dummy field gate pattern30, which are formed on the isolation region110of the field area FA. The cut field gate patterns10and20may include a first cut field gate pattern10which has a relatively narrow width and a second cut field gate pattern20which has a relatively wide width. As described with reference toFIG. 1, each of the first and second cut field gate patterns10and20may be separated by the field gate cut-zone CZ1that overlaps the first and second cut field gate patterns10and20.

The semiconductor device may include a first fin gate pattern40, a second fin gate pattern50, and a butting gate pattern60, which are disposed on the isolation region110and the fin active region130of the active area AA. As described with reference toFIG. 1, each of the first and second fin gate patterns40and50and the butting gate pattern60may be separated by the fin gate cut-zone CZ2that overlaps the first and second fin gate patterns40and50and the butting gate pattern60, and a portion of the second fin gate pattern50may be removed by the fin active cut-zone CZ3that overlaps the portion of the second fin gate pattern50.

Referring toFIG. 2A, the first cut field gate pattern10may include a first cut field gate core10C, and the second cut field gate pattern20may include a second cut field gate core20C, in a region which overlaps the field gate cut-zone CZ1ofFIG. 1. Bottoms of the first cut field gate core10C and the second cut field gate core20C may protrude into the isolation region110. For example, the first cut field gate core10C may include silicon nitride and the second cut field gate core20C may include silicon oxide.

The first fin gate pattern40may include a first fin gate insulating layer41, a first fin gate barrier layer42, and a first fin gate electrode43, and the butting gate pattern60may include a butting gate insulating layer61, a butting gate barrier layer62, and a butting gate electrode63in a region which does not overlap the fin gate cut-zone CZ2ofFIG. 1. The semiconductor device may include a fin active core130C in a fin active recess130R. The fin active core130C may include, for example, silicon nitride.

The semiconductor device may further include source/drain regions135which protrude from a surface of the fin active region130and protrude into the fin active region130. The source/drain regions135are adjacent the fin gate patterns40and50in the fin active region130. The source/drain regions135may include, for example, silicon germanium (SiGe), silicon carbide (SiC), or silicon (Si), which is formed by an epitaxial growth process.

The semiconductor device may further include a first interlayer insulating layer171which fills gaps between the first cut field gate pattern10, the second cut field gate pattern20, the dummy field gate pattern30, the first fin gate pattern40, the second fin gate pattern50, and the butting gate pattern60. Upper surfaces of the first cut field gate pattern10, the second cut field gate pattern20, the dummy field gate pattern30, the first fin gate pattern40, the second fin gate pattern50, the butting gate pattern60, and the first interlayer insulating layer171may be coplanar. The first interlayer insulating layer171may include, for example, silicon oxide.

The semiconductor device may further include a first stopper layer181, which is formed on the first cut field gate pattern10, the second cut field gate pattern20, the dummy field gate pattern30, the first fin gate pattern40, the second fin gate pattern50, the butting gate pattern60, and the first interlayer insulating layer171. The first stopper layer181may be formed to extend horizontal and to be flat. The first stopper layer181may include silicon nitride.

The semiconductor device may further include a contact pattern140that connects to the source/drain region135and vertically extends through the first stopper layer181and the first interlayer insulating layer171. The contact pattern140may include a silicide layer141, a contact barrier layer142, and a contact plug143and the contact pattern140may be directly formed on the source/drain region135. The silicide layer141may include a metal silicide such as tungsten silicide (WSi), titanium silicide (TiSi), nickel silicide (NISi), or cobalt silicide (CoSi). The contact barrier layer142may include a barrier metal such as titanium nitride (TiN). The contact plug143may include a metal such as tungsten (W). Upper surfaces of the contact pattern140and the first stopper layer181may be coplanar. The semiconductor device may further include a second stopper layer182, which is formed on the contact pattern140and the first stopper layer181. The second stopper layer182may include, for example, silicon nitride.

The semiconductor device may further include a second interlayer insulating layer172formed on the second stopper layer182. The second interlayer insulating layer172may include, for example, silicon oxide.

The semiconductor device may further include a via pattern150which contacts the contact pattern140and vertically extends through the second interlayer insulating layer172and the second stopper layer182. The via pattern150may include a via barrier layer151and a via plug152. The via barrier layer151may include a barrier metal such as titanium nitride (TiN). The via plug152may include a metal such as tungsten (W).

The semiconductor device may further include a metal interconnection160, which is formed on the via pattern150and the second interlayer insulating layer172. The metal interconnection160may horizontally extend. The metal interconnection160may include a metal such as tungsten (W).

The semiconductor device may further include a third interlayer insulating layer173which covers the metal interconnection160on the second interlayer insulating layer172. The third interlayer insulating layer173may include silicon oxide or silicon nitride.

Referring toFIG. 2B, the first cut field gate pattern10may include a first cut field gate insulating layer11, a first cut field gate barrier layer12, and a first cut field gate electrode13, and the second cut field gate pattern20may include a second cut field gate insulating layer21, a second cut field gate barrier layer22, and a second cut field gate electrode23in a region which does not overlap the field gate cut-zone CZ1ofFIG. 1.

The first fin gate pattern40may include a first fin gate core40C, the second fin gate pattern50may include a second fin gate core50C, and the butting gate pattern60may include a butting gate core60C, in a region which overlaps the fin gate cut-zone CZ2ofFIG. 1.

Referring toFIG. 2C, the second fin gate pattern50may include a second fin gate insulating layer51, a second fin gate barrier layer52, and a second fin gate electrode53, which are formed on the surface insulating layer132on surfaces of the protruding fin regions130, in a region which does not overlap the fin active cut-zone CZ3ofFIG. 1, and may include a second fin gate core50C and a fin active core130C in a region which overlaps the fin active cut-zone CZ3ofFIG. 1. The second fin gate core50C may include, for example, silicon nitride.

The first cut field gate insulating layer11, the second cut field gate insulating layer21, a dummy field gate insulating layer31, the first fin gate insulating layer41, the second fin gate insulating layer51, and the butting gate insulating layer61each may include a metal oxide such as hafnium oxide (HfO), aluminum oxide (AlO), or titanium oxide (TiO).

The first cut field gate barrier layer12, the second cut field gate barrier layer22, a dummy field gate barrier layer32, the first fin gate barrier layer42, the second fin gate barrier layer52, and the butting gate barrier layer62each may include a barrier metal such as titanium nitride (TiN) or tantalum nitride (TaN).

The first cut field gate electrode13, the second cut field gate electrode23, a dummy field gate electrode33, the first fin gate electrode43, the second fin gate electrode53, and the butting gate electrode63each may include tungsten (W), copper (Cu), aluminum (Al) or another metal.

The semiconductor device may include first cut field gate spacers81on side surfaces of the first cut field gate pattern10, a second cut field gate spacer82on a side surface of the second cut field gate pattern20, dummy field gate spacers83on side surfaces of the dummy field gate pattern30, first fin gate spacers84on side surfaces of the first fin gate pattern40, second fin gate spacers85on side surfaces of the second fin gate pattern50, and butting gate spacers86on side surfaces of the butting gate pattern60.

The first cut field gate spacers81may be formed on side surfaces of the first cut field gate insulating layer11and the first cut field gate core10C. The second cut field gate spacer82may be formed on side surfaces of the second cut field gate insulating layer21and the second cut field gate core20C. The dummy field gate spacers83may be formed on side surfaces of the dummy field gate insulating layer31. The first fin gate spacers84may be formed on side surfaces of the first fin gate insulating layer41and the first fin gate core40C. The second fin gate spacers85may be formed on side surfaces of the second fin gate insulating layer51, the second fin gate core50C, and the fin active core130C. The butting gate spacers86may be formed on side surfaces of the butting gate insulating layer61and the butting gate core60C.

A base insulating layer131may be formed between the isolation region110and the first interlayer insulating layer171, and between the isolation region110and the gate spacers81,82,83,84,85, and86. The base insulating layer131may include silicon oxide.

Referring toFIGS. 3A to 3C, the method of fabricating the semiconductor device in accordance with some embodiments of the inventive concept may include providing a substrate100including a field area FA and an active area AA, forming an isolation region110which defines a fin active region130on the substrate100, forming a base insulating layer131on surfaces of the fin active region130and the isolation region110, and forming sacrificial gate patterns71to76and gate spacers81to86on the base insulating layer131.

The substrate100may include one of a single crystal silicon wafer, a silicon germanium (SiGe) wafer, and a silicon on insulator (SOI) wafer.

The isolation region110may include a trench insulation material113which fills a deep trench111and a shallow trench112. The trench insulation material113may completely fill the deep trench111, and partially fill the shallow trench112. The trench insulation material113may include silicon oxide such as Tonen silazane (TOSZ) or un-doped silicate glass (USG).

The base insulating layer131may be conformally formed on the surfaces of the fin active region130and the isolation region110by performing a deposition process such as a chemical vapor deposition (CVD) process or an atomic layered deposition (ALD) process. The base insulating layer131may include silicon oxide.

The sacrificial gate patterns71to76may include a sacrificial first cut field gate pattern71, a sacrificial second cut field gate pattern72, a sacrificial dummy field gate pattern73, a sacrificial first fin gate pattern74, a sacrificial second fin gate pattern75, and a sacrificial butting gate pattern76. The sacrificial gate patterns71to76each may include, for example, polycrystalline silicon. The forming of the gate spacers81to86may include forming a silicon nitride layer by performing an ALD process, and then performing an etch-back process.

Referring toFIGS. 4A to 4C, the method may include forming source/drain regions135and forming a first interlayer insulating layer171between the sacrificial gate patterns71to76.

The forming of the source/drain region135may include forming source/drain recesses135R by removing the base insulating layer131and recessing the fin active region130between the sacrificial fin gate patterns74and75and between the sacrificial fin gate pattern75and the sacrificial butting gate pattern76. The forming of the source/drain region135may also include performing a selectively epitaxial growth (SEG) process. The source/drain region135may include a silicon germanium (SiGe) layer, a silicon carbide (SiC) layer, or a silicon (Si) layer.

The forming of the first interlayer insulating layer171may include forming silicon oxide to cover the sacrificial gate patterns71to76and fill gaps between the sacrificial gate patterns71to76and performing a planarization process such as a chemical mechanical polishing (CMP) process or an etch-back process.

Referring toFIGS. 5A to 5C, the method may include forming a first mask pattern M1, and forming a first field gate cut space S1, a second field gate cut space S2, a fin gate cut space S3, and a fin active cut space S4by removing portions of the sacrificial gate patterns71to76by performing a silicon etching process using the first mask pattern M1as an etch mask. In some embodiments, the first field gate cut space S1, the second field gate cut space S2, the fin gate cut space S3, and the fin active cut space S4may be formed concurrently through the same process. It will be understood that “formed concurrently” refers to formed in a same fabrication step, at approximately (but not necessarily exactly) the same time.

The first mask pattern M1may include a field gate cut opening O1, a fin gate cut opening O2, and a fin active cut opening O3corresponding to the field gate cut-zone CZ1, the fin gate cut-zone CZ2, and the fin active cut-zone CZ3ofFIG. 1, respectively.

The base insulating layer131may be exposed by removing the portions of the sacrificial first cut field gate pattern71, the sacrificial second cut field gate pattern72, the sacrificial first fin gate pattern74, the sacrificial second fin gate pattern75, and the sacrificial butting gate pattern76, which are exposed in the field gate cut opening O1, the fin gate cut opening O2, and the fin active cut opening O3.

The first mask pattern M1may include a hard mask. For example, the first mask pattern M1may include silicon oxide, silicon nitride, or spin on hardmask (SOH).

Upper portions of the first interlayer insulating layer171and the gate spacers81,82,84,85, and86, which are exposed in the field gate cut opening O1, the fin gate cut opening O2, and the fin active cut opening O3may be recessed.

Referring toFIGS. 6A to 6C, the method may include forming a fin active recess130R by removing the base insulating layer131exposed in the fin active cut space S4and recessing the fin active region130.

The isolation region110exposed in the first field gate cut space S1, the second field gate cut space S2, and the fin gate cut space S3may be recessed.

Referring toFIGS. 7A to 7C, the method may include forming an insulating core layer90which completely or partially fills the first and second field gate cut spaces S1and S2, the fin gate cut space S3, the fin active cut space S4, and the fin active recess130R. In some embodiments, the insulating core layer90may be formed semi-conformally.

For example, the first field gate cut space S1, the fin gate cut space S3, the fin active cut space S4, and the fin active recess130R may be completely filled with the core layer90, and the second field gate cut space S2may be partially filled with the core layer90. The core layer90may include, for example, silicon nitride.

Referring toFIGS. 8A to 8C, the method may include forming a first cut field gate core10C, a first fin gate core40C, a second fin gate core50C, a butting gate core60C, and a fin active core130C by partially removing the core layer90by performing a chamfering process.

The core layer90in the second field gate cut space S2may be completely removed. The chamfering process may include an isotropic etch-back process. For example, the core layer90may form the first cut field gate core10C, the first fin gate core40C, the second fin gate core50C, the butting gate core60C, and the fin active core130C, which fill the first field gate cut space S1, the fin gate cut space S3, the fin active cut space S4, the fin active recess130R, by removing portions of the core layer90formed on the first mask pattern M1or the first interlayer insulating layer171.

Referring toFIGS. 9A to 9C, the method may include forming silicon oxide, removing the first mask pattern M1and exposing the sacrificial gate patterns71to76by performing a planarization process such as a CMP process.

Upper surfaces of the remaining sacrificial gate patterns71to76, the first interlayer insulating layer171, the gate spacers81to86, the first cut field gate core10C, the second cut field gate core20C, the first and second fin gate cores40C and50C, the butting gate core60C, and the fin active core130C may be coplanar.

Referring toFIGS. 10A to 10C, the method may include forming gate electrode spaces10S,20S,30S,40S,505, and60S by removing the exposed sacrificial gate patterns71to76by performing a silicon etching process, and forming a thin surface insulating layer132on the surface of the fin active region130exposed in the fin gate electrode spaces40S,50S, and60S by performing a washing process or a wet oxidation process. Therefore, the surface insulating layer132may include oxidized silicon.

Referring toFIGS. 11A to 11C, the method may include forming gate patterns10,20,30,40,50, and60in the gate electrode spaces105,20S,30S,40S,50S, and60S, and forming a first stopper layer181.

The gate patterns10,20,30,40,50, and60may include gate insulating layers11,21,31,41,51, and61, gate barrier layers12,22,32,42,52, and62, and gate electrodes13,23,33,43,53, and63, respectively. The gate insulating layers11,21,31,41,51, and61each may include a metal oxide such as hafnium oxide (HfO) or aluminum oxide (AlO). The gate barrier layers12,22,32,42,52, and62each may include a barrier metal such as titanium nitride (TiN). The gate electrodes13,23,33,43,53, and63each may include a metal compound or a metal alloy including tungsten (W), titanium (Ti), tantalum (Ta), aluminum (Al) and/or nitrogen (N).

The gate insulating layers11,21,31,41,51, and61each may be formed in a “U” shape on the isolation region110, the surface insulating layer132, and the gate spacers81to86. The gate barrier layers12,22,32,42,52, and62each may be formed in a “U” shape on the gate insulating layers11,21,31,41,51, and61. The gate electrodes13,23,33,43,53, and63each may be solid and may be surrounded by the gate barrier layers12,22,32,42,52, and62. The first stopper layer181may have a flat upper surface. The first stopper layer181may include silicon nitride.

Referring toFIGS. 12A to 12C, the method may include forming a second mask pattern M2on the first stopper layer181, forming a contact hole140H which exposes the source/drain region135by etching the first stopper layer181and the first interlayer insulating layer171by performing an etching process using the second mask pattern M2as an etch mask, and forming a silicide layer141on the exposed source/drain region135.

Since the fin active core130C is present, the second mask pattern M2may be formed wider than the contact hole14011and thus a align margin may be increased.

The forming of the silicide layer141may include siliciding a surface of the exposed source/drain region135by performing a silicidation process. Therefore, the silicide layer141may include titanium silicide (TiSi), tungsten silicide (WSi), nickel silicide (NiSi), cobalt silicide (CoSi) or another metal silicide. The second mask pattern M2may include a photoresist or polysilicon. Then, the second mask pattern M2may be removed.

Referring toFIGS. 13A to 13C, the method may include forming a contact pattern140in the contact hole140H using a CMP process, and forming a second stopper layer182on the contact pattern140.

The contact pattern140may include a contact barrier layer142and a contact plug143. The contact barrier layer142may include a barrier metal compound such as titanium nitride (TiN). The contact plug143may include a metal such as tungsten (W). The second stopper layer182may include silicon nitride.

The contact pattern140may be formed through a self-align method. For example, when the CMP process is performed, the fin active core130C may be used as a planarization stop layer even when the first stopper layer181is removed. Further, even when the gate electrodes13,23,33,43,53, and63of the gate patterns10,20,30,40,50, and60are exposed by removing the first stopper layer181, the second stopper layer182may reduce physical and chemical damage to the gate electrodes13,23,33,43,53, and63.

Referring toFIGS. 14A to 14C, the method may include forming a second interlayer insulating layer172on the second stopper layer182, and forming a via pattern150that connects to the contact pattern140and vertically extends through the second interlayer insulating layer172. The second interlayer insulating layer172may include silicon oxide.

The via pattern150may include a via barrier layer151and a via plug152. The via barrier layer151may include a barrier metal compound such as titanium nitride (TiN). The via plug152may include a metal such as tungsten (W).

Then, as described with reference toFIGS. 2A to 2C, the method may include forming a metal interconnection160on the via pattern150, and forming a third interlayer insulating layer173which covers the metal interconnection160.

The metal interconnection160may horizontally extend. The metal interconnection160may include a metal such as tungsten (W). The third interlayer insulating layer173may include silicon oxide or silicon nitride. A stopper layer may be further formed between the second interlayer insulating layer172and the third interlayer insulating layer173.

FIG. 15Ais a diagram illustrating a semiconductor module2200in accordance with some embodiments of the inventive concept. Referring toFIG. 15A, the semiconductor module2200in accordance with some embodiments of the inventive concept may include a processor2220and semiconductor devices2230, which are mounted on a module substrate2210. The processor2220or the semiconductor devices2230may include a semiconductor device in accordance with some embodiments of the inventive concept. Conductive input/output terminals2240may be disposed on at least one side of the module substrate2210.

FIG. 15Bis a block diagram illustrating an electronic system2300in accordance with some embodiments of the inventive concept. Referring toFIG. 15B, the electronic system2300in accordance with some embodiments of the inventive concept may include a body2310, a display unit2360, and an external apparatus2370. The body2310may include a microprocessor unit2320, a power supply2330, a function unit2340, and/or a display controller unit2350. The body2310may include a system board or a motherboard having a PCB or the like, and/or a case. The microprocessor unit2320, the power supply2330, the function unit2340, and the display controller unit2350may be mounted or disposed on an upper surface of the body2310or inside the body2310. The display unit2360may be disposed on the upper surface of the body2310or inside/outside the body2310. The display unit2360may display an image processed by the display controller unit2350. For example, the display unit2360may include a liquid crystal display (LCD), active matrix organic light emitting diodes (AMOLED), or various display panels. The display unit2360may include a touch screen. Therefore, the display unit2360may have an input/output function. The power supply2330may supply a current or a voltage to the microprocessor unit2320, the function unit2340, the display controller unit2350, etc. The power supply2330may include a charging battery, a socket for a dry cell, or a voltage/current converter. The microprocessor unit2320may receive a voltage from the power supply2330to control the function unit2340and the display unit2360. For example, the microprocessor unit2320may include a CPU or an application processor (AP). The function unit2340may include a touch pad, a touch screen, a volatile/non-volatile memory, a memory card controller, a camera, a lighting, an audio and moving picture playback processor, a wireless radio antenna, a speaker, a microphone, a USB port, or a unit having other various functions. The microprocessor unit2320or the function unit2340may include a semiconductor device in accordance with some embodiments of the inventive concept.

Referring toFIG. 15C, an electronic system2400in accordance with some embodiments of the inventive concept may include a microprocessor2414, a memory2412, and a user interface2418which perform data communication using a bus2420. The microprocessor2414may include a CPU or an AP. The electronic system2400may further include a RAM2416in direct communication with the microprocessor2414. The microprocessor2414and/or the RAM2416may be assembled within a single package. The user interface2418may be used to input data to the electronic system2400, or output data from the electronic system2400. For example, the user interface2418may include a touch pad, a touch screen, a keyboard, a mouse, a scanner, a voice detector, a cathode ray tube (CRT) monitor, an LCD, an AMOLED, a plasma display pad (PDP), a printer, a lighting, or various input/output devices. The memory2412may store operational codes of the microprocessor2414, data processed by the microprocessor2414, or data received from the outside. The memory2412may include a memory controller, a hard disk, or a solid state drive (SSD). The microprocessor2414, the RAM2416, and/or the memory2412may include a semiconductor device in accordance with some embodiments of the inventive concept.

Semiconductor devices and methods of fabricating the same in accordance with some embodiments of the inventive concept, a single diffusion break (SDB) structure can be implemented using a fin active cutting method.

Semiconductor devices and methods of fabricating the same in accordance with some embodiments of the inventive concept, a fin active region and a gate pattern are concurrently cut, and the methods thus can be simplified.

Semiconductor devices and methods of fabricating the same in accordance with some embodiments of the inventive concept, an insulation material is formed in a recess in a fin active region adjacent a contact pattern, and the contact pattern thus can be formed by a self-aligned process.

Although a few embodiments have been described, those skilled in the art will readily appreciate that many modifications are possible in embodiments without materially departing from the novel teachings and advantages. Accordingly, all such modifications are intended to be included within the scope of this inventive concept as defined in the claims.