Integrated Circuit Including a Programmable Logic Analyzer with Enhanced and Debugging Capabilities and a Method Therefor

A system including an embedded logic analyzer block having an input receiving a plurality of signals from a system under test, and a trigger event block detecting an occurrence of an event based in part upon the plurality of signals. The system further includes a block with a first input receiving one or more of the plurality of signals, a second input receiving a signal based upon the detection of the occurrence of the event, circuitry generating a distinct set test signals based on the signals at the first input and second input of the block, the distinct set of test signals being different from the plurality of signals appearing at the input of the embedded logic analyzer block, and an output providing the generated distinct set of test signals to the embedded logic analyzer block as additional test signals for at least one of sampling thereof and event triggering.

BACKGROUND

1. Field of the Invention

The present invention relates generally to an embedded logic analyzer, and particularly to a programmable embedded logic analyzer for analyzing an electronic circuit.

2. Description of the Related Art

A logic analyzer is an electronic instrument that is used to capture and display data signals of an electronic circuit. Generally, the logic analyzer captures the data signals that are too fast to be observed by a user. The user observes the data signals captured by the logic analyzer to effectively analyze the electronic circuit and to take preemptive actions or to debug based on the analysis.

Logic Analyzers may be broadly classified as external logic analyzers and embedded logic analyzers. The embedded logic analyzer is generally included within a programmable logic device or an integrated circuit (IC), e.g., a complex programmable logic device (CPLD), field programmable gate array (FPGA), application specific integrated circuit (ASIC), etc. The embedded logic analyzer has the ability to capture large amounts of high speed data signals within the IC.

The embedded logic analyzer may include a memory to store the captured data signals. Usually, the embedded logic analyzer is programmable to capture and store the data signals specified by the user. The data signals stored by the embedded logic analyzer may be transferred to a computer for further analysis. The data signals are generally transferred to the computer through an interface provided on the IC.

FIG. 1is a block diagram of a conventional embedded logic analyzer (ELA)100included within an integrated circuit (not shown). The ELA100includes an interconnect module110to receive a plurality of data signals within the integrated circuit. The interconnect module110is programmable to select a plurality of signals to be sampled and at least one trigger signal to enable sampling from the plurality of received signals. The at least one trigger signal is transferred to a trigger module120. The trigger module120is programmable to set a trigger condition and to detect if the at least one trigger signal satisfies the trigger condition. If the trigger condition is satisfied, the trigger module120initiates a sampling process. Upon the initiation of the sampling process, a memory controller130starts sampling the plurality of signals to be sampled from the interconnect module110. The sampled signals may be stored in a memory140for further analysis. Therefore, the ELA100operates to execute a general code given below:IF (<TRIGGER CONDITION>) THEN (SAMPLE SIGNALS(X)),
wherein the TRIGGER CONDITION is any logical operation or a series of logical operations and the SIGNALS (X) are the plurality of signals to be sampled from the interconnect module110. According to the code executed by the ELA100, when the trigger condition is satisfied, the ELA100samples at least one sampled signal and stores the sampled signal in the memory140.

However, conventional ELAs are limited to sampling when the trigger condition is satisfied. Further, conventional ELAs do not capture, analyze, and/or debug software data or firmware data signals within the IC, and additional instrument(s) may be necessary in order to analyze these types of data. Additionally, in order to program the ELA or to analyze the data stored within the ELA, the user is required to be present at a workstation where the ELA is installed.

It would be desirable therefore to provide an ELA with enhanced analyzing and debugging capabilities to obviate the above-mentioned problems.

SUMMARY OF THE INVENTION

In accordance with an exemplary embodiment, there is disclosed a system including an embedded logic analyzer block having an input receiving a plurality of signals from a system under test, and a trigger event block detecting an occurrence of an event based in part upon the plurality of signals. The system further includes a block with a first input receiving one or more of the plurality of signals, a second input receiving a signal based upon the detection of the occurrence of the event, circuitry generating a distinct set test signals based on the signals at the first input and second input of the block, the distinct set of test signals being different from the plurality of signals appearing at the input of the embedded logic analyzer block, and an output providing the generated distinct set of test signals to the embedded logic analyzer block as additional test signals for at least one of sampling thereof and event triggering.

DETAILED DESCRIPTION

The present invention is directed to a programmable embedded logic analyzer included within an integrated circuit having enhanced analyzing and debugging capabilities.FIG. 2illustrates one embodiment of an embedded logic analyzer (ELA)200disposed on an integrated circuit (IC)260. The ELA200includes an interconnect module210that is programmable to select at least one of a plurality of candidate signals within the IC260. The plurality of candidate signals selected by the interconnect module210may include at least one trigger signal and/or at least one signal to be sampled (i.e., a sampled signal). The interconnect module210routes the at least one trigger signal to a trigger module220. The trigger module220detects if the at least one trigger signal satisfies at least one trigger condition specified by a user. If the trigger condition is satisfied, an output module230performs at least one task. For example, the output module230may modify at least one signal within the IC260.

The IC260includes a plurality of buses265that carry the plurality of candidate signals. The plurality of signals includes at least one sampled signal and at least one trigger signal. The interconnect module210receives the plurality of signals from the plurality of buses265. The interconnect module210is programmable to select at least one sampled signal and/or at least one trigger signal from the plurality of received signals. Essentially, the interconnect module210selects the sampled signal(s) and/or trigger signal(s) specified by a user. In one embodiment, the interconnect module210may be a multiplexer.

The interconnect module210routes the trigger signal to the trigger module220. The trigger module220is programmable to set the trigger condition. The trigger condition may be a single logical operation (e.g., a simple event) or a series of logical operations (e.g., a complex series of events performed by a finite state machine). The trigger module220detects if the at least one trigger condition is satisfied by the trigger signal. If the trigger condition is satisfied, the trigger module220provides information to the output module230.

The output module230performs at least one task from a group of tasks based upon, in response to, or as a result of the satisfaction of the at least one trigger condition. The group of tasks may include modifying at least one signal from the plurality of received signals, modifying the at least one trigger condition, and initiating a sampling process. In one embodiment, the output module230is a field programmable gate array.

If the output module230initiates the sampling process, a sampling controller240starts sampling the sampled signal from the interconnect module210. The sampled signal sampled by the sampling controller240may be stored in a memory250. The signals stored in a memory250may be transferred to a computer (not shown) for analysis. Such signal transfer to the computer may occur through a communication port280such as a USB port. The signals transferred to the computer may then be analyzed by the user.

WhileFIG. 2shows that the memory250resides in the ELA200, it will be appreciated by one of ordinary skill in the art that the memory may be a separate component on the integrated circuit260in another embodiment. In yet another embodiment, the memory may be a located separately from the integrated circuit260, provided that it remains communicatively coupled to the ELA. After analyzing the signals, at least one action within an apparatus300embedding the IC260, as shown inFIG. 3, may be performed by configuring or programming the output module230to perform a specific task based upon the analysis. For example, the user may debug an error or fault or correct the action of a component of the apparatus300. Therefore, the apparatus300can be diagnosed more effectively to ensure proper functioning of the apparatus300. In one embodiment, the apparatus300may be an imaging device such as a printer, a scanner, or a multi-function device which has the ability to print, scan, fax and/or copy.

The output module230may be programmed or configured to modify at least one signal based upon, in response to, or as a result of the satisfied trigger condition. If the satisfied trigger condition indicates an error, the output module230may modify at least one signal from the plurality of signals received by the ELA200to correct the indicated error. For example, if a value of signal ‘X’ has to be 30 for error-free operation of the apparatus300, and if the trigger condition X≠30 is satisfied, the output module230modifies the value of signal X to bring the value of the signal to 30 for error free operation of the apparatus300.

The output module230may also instruct a controller270(shown inFIG. 2) to modify at least one signal from the plurality of signals received by the ELA200to correct the indicated error. For example, the output module230may instruct the controller270to turn off a pulse width modulator (PWM) if the PWM that regulates the speed of a motor is detected to be stuck, thereby preventing damage to the motor. The output module230may also be capable of stopping a direct memory access (DMA) operation. In addition, the output module230may modify the trigger condition, if required. These capabilities of the output module230greatly enhance the debugging power of the ELA200. Therefore, the ELA200generally executes a code given below:IF (<CONDITION>) THEN (<ACTION(S)>),
wherein ACTION(S) is at least any one of the above mentioned actions performed by the output module or the controller, and CONDITION is the trigger condition set by the user.

In one embodiment, as shown inFIG. 4, the IC260includes a network access device400. The network access device400is in communicatively coupled to the ELA200and is connected to a remote host410directly or through a network. The connection may include a wired connection and/or a wireless connection, and the network may be the Internet, a local area network, a wide area network or a metropolitan area network. The remote host410is capable of programming the ELA200within the IC260. The remote host410is also capable of analyzing the sampled signals stored in memory. The remote host410accesses the ELA200through the network access device400.

The ELA200may be programmed to automatically and periodically send the stored sampled signals to the remote host410for analysis. For example, the ELA200embedded within a printer may be programmed to automatically and periodically send an encoder signal to the remote host410. The encoder signal indicates the motion of the motor within the printer. If it is determined that the encoder signals are decaying or going into a bad state, a remote user may provide instruction to service the printer. In one embodiment, the ELA200is programmable to transfer stored data signals to the remote host410if such instruction or command is received from the remote host410.

In another embodiment, as illustrated inFIG. 5, the IC260includes a central processing unit (CPU)500. The CPU500provides a plurality of data signals to the ELA200. The data signals may be hardware, software or firmware signals. The data signals are supplied from the CPU500to the ELA200through an interface. The interface is communicatively coupled to the CPU500and the ELA200. The interface includes a storage medium510and a plurality of communication lines (1-n). The plurality of communication lines are communicatively coupled with the CPU500and the storage medium510. The plurality of communication lines (1-n) are configured to supply the plurality of data signals from the CPU500to the storage medium510. The storage medium510is configured to store the plurality of data signals.

Each data signal from the plurality of data signals is associated with a data field and an address field. The data field provides the value of the data signal to be stored and the address field specifies a location in the storage medium510where the data signal is stored. The storage medium510includes a plurality of memory locations. Each of the plurality of memory locations has a unique address. The plurality of data signals stored in the storage medium510is supplied to the interconnect module210through the plurality of buses on the IC260. Essentially, the storage medium510is in electrical communication with the plurality of buses on the IC260to supply the stored data signals to the interconnect module210.

The stored data signals supplied to the interconnect module210includes the hardware, software and/or firmware data signals. The data signals include a plurality of sampled signals and at least one trigger signal. The interconnect module210selects the plurality of sampled signals and at least one trigger signal from the plurality of received data signals. The trigger signal is supplied to the trigger module220. The trigger module220detects if the trigger signal satisfies at least one trigger condition. If the trigger condition is satisfied, the sampling controller240samples the plurality of sampled signals from the interconnect module210. The plurality of sampled signals is stored in the memory250. The plurality of stored signals along with other stored signals is transferred to the computer for analysis. Therefore, the software, hardware and/or firmware signals can be analyzed simultaneously on the computer.

In another embodiment, as illustrated inFIG. 6, the interface i.e., the plurality of communication lines (1-n) and the storage medium510are disposed on an IC600. The IC600includes the ELA100ofFIG. 1and a CPU610. The CPU610supplies the plurality of data signals to the ELA100. The plurality of data signals includes at least one software or firmware data signal. The plurality of data signals are supplied from the CPU610to the ELA100through the plurality of communication lines (1-n) and the storage medium510. The plurality of communication lines (1-n) is configured to supply the plurality of data signals from the CPU610to the storage medium510. The storage medium510is configured to store the plurality of data signals. The data signals stored in the storage medium510are supplied to the interconnect module110through the plurality of buses on the IC600. Essentially, the storage medium510is in electrical communication with the plurality of buses on the IC600to supply the stored data signals to the interconnect module110.

In yet another embodiment, as illustrated inFIG. 7, the ELA100is disposed on an IC700that includes a processor710. The processor710receives a plurality of signals from a plurality of buses on the IC700. Such signals may be any combination of hardware, software and/or firmware signals (indicated by arrow A) within the IC700. The processor710is communicatively coupled to the ELA100disposed on the IC700. More specifically, processor710may be communicatively coupled to the trigger module120of the ELA100.

In an alternate embodiment, the IC700may be communicatively coupled to the ELA200ofFIG. 2. In this embodiment, the processor710receives at least one trigger signal from the trigger module220to detect if at least one trigger condition is satisfied. If at least one trigger condition is satisfied, the processor710modifies at least one signal from the plurality of data signals received by the processor710. The processor710is also programmable to modify at least one trigger condition in the trigger module220when the at least one trigger condition is satisfied. The processor710is programmable through an interface720provided on the IC700.

The IC700may include the network access device400. The network access device400communicatively couples the IC700to the remote host410. The remote host410can program the ELA100disposed on the IC700. The remote host410can also analyze the sampled signals stored in the ELA100. Therefore, the remote host410can diagnose an apparatus730embedding the ELA100and the network access device400.

FIG. 8is a flowchart illustrating a method for capturing software signals or events within the IC260. The CPU500disposed on the IC260supplies a plurality of software signals to the storage medium510at block800. The storage medium is configured to store the plurality of software signals (block805). The storage medium510sends the stored software signals to the interconnect module210of ELA200at block810. The interconnect module210is programmed to select a plurality of software signals that is to be sampled from the plurality of received software signals (block815). The interconnect module210is also programmed to select at least one software trigger signal from the plurality of received software signals (block820). The user sets within the trigger module220at least one trigger condition for a software event (block825). The trigger module220detects if the set trigger condition is satisfied by the at least one software trigger signal (block830). If the trigger condition is satisfied, the trigger module220initiates the sampling process at block835. Otherwise, the trigger module repeats the detection of a satisfied set trigger condition.

Upon the initiation of the sampling process, the sampling controller240samples the plurality of software signals that is to be sampled from the interconnect module210(block840). The sampled software signals may then be stored in the memory250at block845. The stored software signals may also be transferred to the computer for analysis by a program running on the computer or by a user.

It will be appreciated by one of ordinary skill in the art the present invention is not limited to software signals. Rather other signals, such as hardware and firmware, may be captured instead of and/or in combination with software signals.

FIG. 9illustrates a system integrated circuit900according to another embodiment of the present invention. Integrated circuit900may be disposed in a system905having a plurality of modules M. Integrated circuit900may include an embedded logic analyzer902having an interconnect module210, trigger module220, memory controller240and memory250as described above. Embedded logic analyzer902may be coupled with the system modules M so that embedded logic analyzer902may be used to effectively test or debug system905in which it is disposed.

It is further understood that the phrases “test” and “debug” are intended to include those operations typically performed during development, testing, debugging, system analysis and in-field monitoring and servicing of the system and its system modules M, and is not intended to be limited to only one phase or time period of system activity from design through the usable life of the system.

Integrated circuit900may also include a custom block904which receives one or more signals associated with embedded logic analyzer902. In particular, custom block904may receive as an input one or more signals provided to embedded logic analyzer902from the other modules M of the system. Such signals may include signals that are available for sampling or event triggering by embedded logic analyzer902. Custom block904may generate at its output one or more output signals that are based upon the one or more received input signals and which are fed back into embedded logic analyzer902for sampling or triggering. By providing to embedded logic analyzer902one or more additional signals for sampling and/or event triggering that is based upon signals associated with embedded logic analyzer902, embedded logic analyzer902may more efficiently debug a system in which integrated circuit900is disposed.

Custom block904may include circuitry that is specific to the particular system and/or system modules M which are available for test and/or debug using embedded logic analyzer902. In an exemplary embodiment of the present invention, custom block904is configurable so that the signals generated thereby may be configurable. Having custom block904configurable advantageously allows for substantial flexibility for testing and/or debugging a wide variety of system modules M and system signals generated thereby. Custom block904may be implemented as a FPGA or CPLD. Alternatively, custom block904may be implemented with a processor having memory coupled thereto for storing code for execution by the processor. By having the memory accessible for loading different code, custom block904may provide sufficient flexibility to test and/or debug a substantially large number of different system modules M. In yet another alternative, custom block904may include state machine circuitry that is programmable in part by programming and/or storing information into registers that are located in or associated with the state machine. It is understood that custom block904may be implemented in any number of ways to provide configurable functionality and signal generation.

As shown inFIG. 9, custom block904may receive one or more signals that are provided to embedded logic analyzer902. Such signals provided to embedded logic analyzer902may be received by custom block904by directly coupling one or more inputs of custom block904to one or more inputs of embedded logic analyzer902. In addition or in the alternative, such signals provided to embedded logic analyzer may be received by custom block904by directly coupling one or more inputs of custom block904to one or more outputs of interconnect module210that are to trigger an event and/or to be sampled, as shown in dotted lines inFIG. 9. As further shown inFIG. 9, the output of custom block904may provide to embedded logic analyzer902one or more output signals for event triggering or sampling. Such one or more output signals may be provided to embedded logic analyzer902by directly coupling the output of custom block904to an input of embedded logic analyzer902. In addition or in the alternative, such one or more output signals may be provided to embedded logic analyzer902by directly coupling the output of custom block904to an input of trigger module220and/or an input of memory controller240, as shown in dotted lines inFIG. 9.

Integrated circuit900may further include an interface906which may be used for accessing custom block904and embedded logic analyzer902. In particular, interface906may provide a wired or wireless connection with a network device on a network, such as a remote host (not shown). Interface906may provide the necessary interface between the network device and various blocks in integrated circuit900, including embedded logic analyzer902and custom block904. Embedded logic analyzer902, and particularly interconnect module210and trigger module220, may be controlled, configured and/or programmed using interface906. In addition, the data sampled by embedded logic analyzer902may be downloaded to a network device for analysis via interface906.

As mentioned above, custom block904may be accessible using interface906. For example, in the event custom block904is reconfigurable and/or programmable, custom block904may be configured by a network device using interface906to generate one or more output signals tailored to the particular system modules M being tested or debugged. In addition or in the alternative, custom block904may be controlled by a remote host during system test or debug using interface906. As a result, custom block904may be configured at runtime of a system level test or debug session.

FIG. 9shows custom block904being separate from embedded logic analyzer902in integrated circuit900. It is understood that, alternatively, custom block904may be located within embedded logic analyzer902in integrated circuit900and be coupled to interconnect module100, trigger module220and memory controller240as described above.

FIG. 10illustrates an integrated circuit910of system905according to another exemplary embodiment of the present invention. Integrated circuit910may include embedded logic analyzer902as described above with respect toFIG. 9, having interconnect module210, trigger module220, memory controller240and memory250. Integrated circuit910may also include a custom block920for generating one or more signals for sampling or event triggering by embedded logic analyzer902, based upon signals provided to and/or generated within embedded logic analyzer902.

Like custom block904inFIG. 9, custom block920is coupled to embedded logic analyzer902to receive as an input one or more signals provided to embedded logic analyzer902. Custom block920, like custom block904, may generate one or more output signals based upon one or more received input signals which is provided to embedded logic analyzer902, trigger module220(for event triggering) and/or memory controller240(for selective sampling). Similar to custom block904, custom block920may include circuitry that is specific to the system modules M that are capable of being tested or debugged by embedded logic analyzer902. In one embodiment, the functions performed by custom block920in generating one or more output signals may be configurable and/or programmable using FPGA or CPLD circuitry, a processor executing downloaded test/debug code, state machine circuitry, etc. Interface906may be coupled to custom block920for providing access thereto so that custom block may be controlled, configured and/or programmed using a network device, such as a host device.

Further, custom block920may receive as an input one or more signals generated by trigger module220. In particular, one or more trigger signals generated by trigger module220, which indicates the detection of at least one event, may be provided as an input to custom block920. One or more output signals generated by custom block920may be based upon the one or more trigger signals generated by trigger module220. In this way, an output signal generated by custom block920may be defined based upon signals generated by system modules M under test or debug as well as actions that are defined and executed at runtime of a test or debug session.

For example, a trigger signal generated by trigger module220of embedded logic analyzer902and provided to custom block920may be used to enable signal generating circuitry within custom block920. In one implementation, custom block920may be configured or otherwise programmed as an accumulator to count a number of events, such as the number of words read from memory by a direct memory access (DMA) system module. One testing or debugging the system selects the DMA module to monitor and controls, programs and/or configures trigger module220accordingly using interface906. A trigger program by which trigger module220is configured may include an action to trigger accumulation. Upon detection of the condition of one or more signals provided to trigger module220, a trigger signal generated by trigger module220indicates detection of the condition and enables the accumulator configured within custom block920to begin accumulating.

Trigger module220may also, either via the same trigger signal used to enable custom block920or a different trigger signal, disable custom block920following its enablement. The signal used for disabling may be driven by circuitry that is configurable and/or programmable and detect the occurrence of at least one trigger event relating to one or more signals received by trigger module220. In the event custom block920is configured as an accumulator, following disablement the output of the accumulator is provided to the input of embedded logic analyzer902for selective sampling by memory controller240or event triggering by trigger module220. By controlling the accumulator function within custom block920to accumulate only upon the occurrence of a user specified trigger event and providing the accumulated result to embedded logic analyzer902, substantially less memory is needed to store samples of the output of the accumulator function than would otherwise be necessary in order to count the number of words read by the DMA system module.

The particulars of the trigger event for controlling, enabling and/or disabling custom block902may be configured or programmed at runtime of a test or debug session, like any other trigger event monitored by trigger module220. The trigger event for disabling custom block920, for example, may be based in part upon a predetermined period of time lapsing following its enablement, wherein the predetermined period of time is configured or otherwise programmed at runtime. It is understood, though that the trigger event may be based upon any of a number of functions or operations defined within trigger module220and upon one or more signals received thereby.

It is understood that custom blocks904and920may be utilized in the same integrated circuit chip.FIG. 11illustrates such an integrated circuit940of system905according to an exemplary embodiment of the present invention, including both custom blocks904and920. It is further understood that an integrated circuit may include more than one custom block904and/or more than one custom block920. With respect to including more than one custom block920within a single integrated circuit chip, each custom block920may receive at an input thereof one or more signals from trigger module220. The one or more signals received from trigger module220by each custom block920may be distinct relative to the one or more signals received by the other custom block920. In addition, each custom block920may be separately programmed and/or configured by a host device using interface906.

It is understood that integrated circuits900,910and940may be used in virtually any system which may benefit from an embedded mechanism to facilitate the efficient testing and debugging of the system and the system modules M thereof. For example, a printer, all-in-one printing device or multifunction printer may include integrated circuit900.

Use of custom blocks904and920has been seen to substantially reduce the amount of memory necessary for storing signals sampled by embedded logic analyzer902. For instance, a printer or other imaging device may include a serial interface for providing to the printer printhead print data for an entire print job, which may require gigabytes of storage. If it is desired to know the number of times a specific nozzle in the printhead fires, custom block904or920may be configured to receive the signal from the serial interface and generate a signal indicative of the particular nozzle firing, without any information relating to any other nozzle of the printhead. The generated signal may be provided as an input to embedded logic analyzer902for selectively sampling during a test/debug session. Sampling and storage in memory of the custom generated signal has been seen to occupy only kilobytes of memory, substantially less than the amount of memory needed to sample and store the entire serial interface.

FIG. 12illustrates integrated circuit980of system905according to another example embodiment. Integrated circuit980includes embedded logic analyzer902as described above in other example embodiments. Integrated circuit980further includes deserializer block1310which has a data input receiving a serial signal from an output of interconnect module210; an enable input receiving a signal from an output of trigger module220for controlling deserializer block1310; and an output1320providing parallel data to an input of interconnect module210. In general terms, deserializer block1310selectively receives and converts serial data at its data input to parallel output data for sampling or triggering by embedded logic analyzer902.

Deserializer block1310may include a shift register1311formed from a number N of flip flop circuits1312connected in cascaded arrangement. Flip flop circuits1312receive the same clock signal CLK. The output of each flip flop circuit1312is provided to a parallel block1314so that the output1320thereof provides up to N bits of parallel data. Parallel block1314may include, for example, a register for receiving the parallel output of shift register1311and maintaining same. In an example embodiment, deserializer block1310receives an output of trigger module220for enabling flip flop circuits1312of shift register1311to enable shift register1311to perform a shifting operation. Flip flop circuits1312forming shift register1311may also receive a reset signal, such as from another output of trigger module220, which when asserted resets flip flop circuits1312. In an example embodiment, a custom block1322receives one or more output signals from trigger module220and generates the enable and reset signals for shift register1311. Custom block1322is configurable and may include field programmable circuitry that is configured using interface906.

In an example embodiment, parallel block1314may also receive the enable and reset signal for enabling and resetting, respectively, the register therein. In an example embodiment, deserializer block1310may generate control signals for performing shifting, enabling and resetting operations based upon signals received from trigger module220and upon other control signals.

Deserializer block1310may further include a filter and control block1316disposed at the front end of shift register1311that can be used to filter out glitches caused by the asynchronous nature of external signals provided to deserializer block1310. In an example embodiment, filter and control block1316includes field programmable circuitry to have only a single register stage up to16stages of filtering at the system clock frequency of clock signal CLK. The filtering is performed on both the clock signal CLK and serial data input line in the same amount to keep the signals in synchronicity with each other.

According to an example embodiment, deserializer block1310is configurable to be able to deserialize serial data from any of a number of serial protocols, standards and formats, including I2C, SPI (Serial Peripheral Interface) and those associated with use of a UART (Universal Asynchronous Receiver/Transmitter). Deserializer block1310includes control block1318which is utilized to facilitates the block's configurability to accept a number of different serial protocols and formats. Control block1318is coupled to filter1316, serial shift register1311and parallel block1314. In an example embodiment, control block1318includes field programmable circuitry which may be configured and/or programmed by a user using interface906. In another example embodiment, control block1318is also controlled during a test or debug session via interface906.

Deserializer block1310may receive serial data appearing on a plurality of serial data lines. In an example embodiment, deserializer block1310has four separate serial inputs for handling serial data on up to four serial data lines. In this way, deserializer block1310is capable of deserializing data from pseudo-serial communication protocols.

For serial protocols that use both address and data components, the number of bits to allocate to the address and data are field programmable, up to N bits for each component. In an example embodiment, N is 32, but it is understand that N can be larger or smaller. The number of address bits (A) and the number of data bits (D) are field programmable. If N>=A+D, then both the address and data fields of the serial protocol will be delivered simultaneously in the N-bit parallel output1320from parallel block1314to interconnect module210of embedded logic analyzer902. If N<A+D, then deserializer block1310will separately deliver deserialized address and data values in the least significant bits of the output1320of parallel block1314when each phase is valid.

Deserializer block1310also deserializes serial protocols in which the address is delivered, followed by a field programmable number of data words. In this case, if N>=A+D, then the address will stay resident in output1320of parallel block1314once valid, and the subsequent data words will replace the previous words after each is valid.

As mentioned above, deserializer block1310is configurable to deserialize UART-based protocols, standards and data formats. In the case of a UART-based protocol, two serial data signals are deserialized by deserializer block1310—the signals on the RX and TX lines. In this case, baud rate and sample point are programmed (in terms of system clocks) using interface906.

For a UART-based protocol, if N>=RX bits+TX bits, then both the last valid RX data and the last valid TX data provided to deserializer block1310will be delivered simultaneously in the parallel N bits of the output1320of parallel block1314. If N<=RX +TX, then the last valid word, be it RX or TX, will be delivered to interconnect module210of embedded logic analyzer902. If N>RX, and N>TX, then the most significant bit of output1320will indicate an RX or TX value.

In instances in which deserializer block1310is not automatically capable of deserializing a desired protocol, the enable and reset signals generated by trigger module220allows the user to deserialize in a programmable or field programmable fashion. This can be figured out after the product has been assembled, and gives greater testing a debugging flexibility.

Also, because the parallel output1320is brought into interconnect module210, parallel output1320, or a portion thereof, can be fed into Build In Self Test (BIST) circuitry to enable a much more elegant BIST operation on serial interfaces. The parallel data register of N bits is also visible to the system, thus its contents can be verified by firmware to allow an additional mode of error checking and self test.

Specifically,FIG. 13illustrates system905according to another example embodiment. Here, system905includes deserializer block1310communicatively coupled to embedded logic analyzer902as discussed above and illustrated inFIG. 12. In addition, system905may include a Built-In Self Test (BIST) block1410. BIST block1410cooperates with embedded logic analyzer902for use in a test and/or debug operation, as described in U.S. Pat. No. 8,516,304, entitled “Integrated Circuit Including a Programmable Logic Analyzer with Enhanced Analyzing and Debugging Capabilities and a Method Therefor,” filed Sept. 8, 2010 and assigned to the assignee of the present application, the content of which is hereby incorporated by reference herein in its entirety. InFIG. 14, BIST block1410receives as its data input some or all of the output of interconnect module210. BIST block1410may receive parallel output1320of deserializer block1310after passing through interconnect module210. BIST block1410may be enabled based upon an enable signal generated by custom block1322, as discussed in the above-reference patent. In this way, output1320of deserializer block1310may form part of the signature generated by BIST block1410, thus making more elegant a BIST operation of a serial interface.

It is understood that system905ofFIGS. 12 and 13may utilize multiple deserializer blocks1310in order to simultaneously deserialize multiple serial interfaces, protocols, formats and standards. In this case, each deserializer1310may receive its own unique set of data and control input and output signals.

It is understood that deserializer block1310may be implemented differently from that shown inFIG. 12and described above. For example, deserializer block1310may utilize demultiplexer circuitry for converting serial data to parallel form.

A mechanism for testing and debugging a system may include, in addition to custom blocks904and920(FIGS. 9-11) and deserializer block1310(FIGS. 12 and 13), software to communicate with embedded logic analyzer902and the custom blocks. The software provides the user with the ability to select in-system options for such blocks and control or otherwise program them after the system has been synthesized and/or assembled, such as at runtime of a system test or debug session. The software, including a user interface, provides communication with embedded logic analyzer902and blocks904and920via interface906. The software may be used to receive at a remote device the data sampled and stored by embedded logic analyzer902and display the signals to the remote device user.

It will be apparent to those skilled in the art that various modifications and variations can be made to the present invention without departing from the spirit and scope of the invention. For example, it is understood that the embedded logic analyzer902may include an output module230and controller270found in embedded logic analyzer200ofFIG. 2. In addition or in the alternative, integrated circuit900,910and940may include a CPU500and storage medium510coupled to embedded logic analyzer902as shown inFIGS. 5 and 6. Integrated circuits900,910and940may also include a processor710coupled to trigger module220as shown inFIG. 7. Thus it is intended that the present invention cover the modifications and variations of this invention provided they come within the scope of the appended claims and their equivalents.