Simultaneous grain modulation for BEOL applications

The invention is directed to an improved semiconductor structure, such that within the same insulating layer, Cu interconnects embedded within the same insulating level layer have a different Cu grain size than other Cu interconnects embedded within the same insulating level layer.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The invention relates generally to a semiconductor structure, and more particularly to copper (Cu) interconnects embedded in the same insulating level layer with different copper grain sizes.

2. Description of the Related Art

One problem encountered in semiconductor manufacturing is the manufacture of copper (Cu) interconnects within the same insulating level layer with different Cu grain sizes. Currently, Cu interconnects formed within the same insulating level layer comprise the same Cu grain size. The limitation of a single Cu grain size for interconnects embedded within the same insulating layer is problematic because, for certain applications Cu interconnects perform more advantageously with a smaller Cu grain size, while for other applications Cu interconnects perform more advantageously with a larger Cu grain size. For example, a large Cu grain size results in lower electrical resistivity and longer electromigration lifetime, which is preferred for a high performance related application, while a small Cu grain size results in higher electrical resistivity and shorter electromigration lifetime, which is preferred for electrical-fuse related applications.

With current semiconductor manufacturing techniques to acquire Cu interconnects with Cu grain size optimized for a chosen application, multiple layers of Cu interconnects embedded within an insulating level layer must be created. Each insulating level layer will have embedded Cu interconnects with the same Cu grain size. Creation of a new layer of Cu interconnects to obtain Cu interconnects with different Cu grain sizes doubles the semiconductor processing steps. In addition, creation of a new layer of Cu interconnects with a different Cu grain size, doubles manufacturing costs.

As discussed herein above, a small Cu grain sized Cu interconnect is preferred for electrical-fuse (e-fuse) related applications. Electrically blowable fuses take advantage of the electromigration (EM) effect to open an electrical connection. During programming, voids form at a center fuse element due to high current density, and eventually create an electrically open circuit. It is also known that Cu grain size has a certain level of impact on electromigration resistance. In general, a larger Cu grain size (i.e.: closer to bamboo-type grain microstructure) leads to fewer grain boundaries that have components normal to the electron flow, and a smaller Cu grain size results in lower EM resistance because of more Cu diffusion through the grain boundaries. For e-fuse programming efficiency, a small Cu grain interconnect is ideal.

Further, as discussed herein above, a large grain sized Cu interconnect is preferred for a high performance applications. Large Cu grain size results in a Cu interconnect with lower resistivity. Big Cu grain size results in lower resistivity because there are fewer grain boundaries with a larger Cu grain size (i.e.: closer to bamboo-type grain microstructure). Grain boundaries cause electron scattering. Therefore, fewer grain boundaries results in less electron scattering, which in turn, results in less resistivity and higher conductivity. For better circuit performance with higher conductivity, a Cu interconnect with a large Cu grains is preferred.

FIG. 1depicts prior art Cu interconnects100a,100bembedded in the same insulating level layer12with the same Cu grain size. Note thatFIG. 1depicts parallel pairs of single10and dual damascene20structures at the same insulating level layer12. Both the single10and dual damascene20structures comprise a barrier material14, copper seed24, and electroplated copper26b. Note that the electroplated copper structures26bin100aand100bhave the same small Cu grain size, which is evident by virtue of the multiple grain boundaries in the electroplated copper26bdepicted inFIG. 1. Therefore, as discussed herein above, the Cu interconnects100a,100bdepicted inFIG. 1would be ideal for an e-fuse application.

What is needed in the art are Cu interconnects embedded in the same insulating level layer with divergent Cu grain sizes, such that the Cu grain size for a given Cu interconnect enables such Cu interconnect to most efficiently perform for an intended application for such Cu interconnect without the need for duplicative semiconductor processing steps and associated costs.

BRIEF SUMMARY OF THE INVENTION

The invention is directed to a structure and method for creation of Cu interconnects embedded in the same insulating layer level with different Cu grain sizes.

A first embodiment is directed to a semiconductor structure comprising a first and second opening, a barrier material, a copper grain promotion material, a copper seed, and electroplated copper. The first and second opening are within the same insulating layer. A barrier material is deposited on the insulating layer in the first and second opening. A copper grain promotion material is deposited on the barrier material of the first opening. A copper seed is deposited on the copper grain promotion material of the first opening and on the barrier material of the second opening. Copper is electroplated on the copper seed within the first and second openings. The copper grain promotion material increases grain size of the electroplated copper in the first opening, such that an average grain size of the electroplated copper grown in the first opening is larger than an average grain size of the electroplated copper in the second opening. The first and second opening are within the same insulating level layer.

A second embodiment is directed to a method for a creating a semiconductor structure, comprising a creating, three depositing and an electroplating copper step. The creating step comprises creating a first and second opening within the same insulating layer. A depositing step comprises conformally depositing a barrier material in the first and second opening. A depositing step comprises depositing a copper grain promotion material on the barrier material of the first opening. A depositing step comprises depositing a copper seed on the copper grain promotion material of their first opening and on the barrier material of the second opening. The electroplating step comprises electroplating copper on the copper seed within both the first and second opening. The deposition of the copper grain promotion material of the first opening causes an average grain size of the electroplated copper in the first opening to be larger than an average grain size of the electroplated copper in the second opening. The first and second opening are within the same insulating level layer.

The invention solves the aforementioned problems associated with Cu interconnects embedded within the same insulating layer level. More specifically, the invention enables the creation of Cu interconnects embedded within the same insulating layer level with divergent Cu grain sizes. In so doing, the present invention enables the creation of Cu interconnects embedded within the same insulating layer level that perform most efficiently for the intended application of the Cu interconnect. In addition, semiconductor manufacturing processing steps are reduced in half because multiple insulating layer levels are not required to create Cu interconnects with different Cu grain sizes. Finally, the elimination of unnecessary processing steps reduces semiconductor manufacturing costs by at least fifty percent.

For at least the foregoing reasons, the invention improves semiconductor technology.

DETAILED DESCRIPTION OF THE INVENTION

The invention will now be described with reference to the accompanying figures. In the figures, various aspects of the structures have been depicted and schematically represented in a simplified manner to more clearly describe and illustrate the invention.

By way of overview and introduction, the embodiments of the invention are directed to a Cu interconnect and a method for creating the same. The invention enables a Cu interconnect embedded within the same insulating layer level to have a different Cu grain size than another Cu interconnect embedded within the same insulating layer level.

The invention will be described with reference to theFIGS. 2-6, which depict the formation of an improved semiconductor structure.

FIG. 2depicts the first step of the method of the present invention. More specifically,FIG. 2demonstrates the formation of a first opening200aand second opening200b(not shown untilFIG. 4) in an insulating layer12. Note that the openings200acomprise both a single10and dual damascene20structure. As one of ordinary skill in the art would appreciate, the present invention is not limited to a first opening200comprising both a single10and dual damascene20structure, but instead could comprise either a single10or a dual damascene20structure. The single damascene10structure comprises a line10aopening, while the dual damascene20structure comprised both a line20aopening and a via20bopening. The insulating layer12can be composed of SiO2, SiCOH, or SiLK. Note that the via20bopening is connected to an underlying metal16. The metal16typically comprises Cu or Al(Cu). A capping layer18separates the underlying metal16from the insulating layer12at the interface with the via20bopening, and a barrier layer14separates the metal16from the insulating layer12in which the metal16is embedded. Typical materials for the capping layer18include NBloK, SiC, Si4NH3, and SiO2, while typical materials for the barrier layer14include Ta, Ti, TaN, TiN, WN, Ru, and W. After the first and second openings200a,bare formed in the insulating layer12, the next step of the method of the present invention occurs. Reactive ion etching techniques (RIE) create the first and second opening200a,b.

FIG. 3depicts the second step of the method of the present invention. Once the first and second openings200a,bare formed in the insulating layer12, a barrier layer14is deposited on the sidewalls and bottom of the first and second openings200a,b. As with the barrier layer14discussed with respect toFIG. 2, the barrier layer14deposited in the first and second opening200a,bofFIG. 3typically consists of Ta, Ti, TaN, TiN, WN, Ru, or W. The barrier layer14can be deposited through one of the following techniques, namely, Physical Vapor Deposition (PVD), Chemical Vapor Deposition (CVD), and Atomic Layer Deposition (ALD).

FIG. 4depicts the third step of the method of the present invention. A copper grain promotion material22is deposited on top of the barrier layer14in200a. A mask placed over the second opening200bcan be used to prevent the deposition of the copper grain promotion material22in the second opening200b. The copper grain promotion material22consists of Ru, Ir, Rh, Mo, Re, Hf, Co, Pt, or Nb, and causes the grain size of any copper electroplated in the opening to be 20.0% larger than the average grain size of Cu electroplated in an opening without the copper grain promotion material22. An even larger average grain size percentage increase, such as 50%, will further enhance a Cu interconnect for high performance applications. A 20% average grain size percentage increase, however is the minimum percentage increase that optimizes a Cu interconnect for high performance applications. The copper grain promotion material22can be deposited through PVD, CVD, or ALD.

FIG. 5depicts the fourth step of the method of the present invention. After the copper grain promotion material22has been deposited on top of the barrier layer14in200ainFIG. 4, copper seed24is deposited on the copper grain promotion material22in the first opening200a. The copper seed24can be deposited through PVD, CVD, or ALD. If a mask was used to prevent the deposition of the copper grain promotion material22in the second opening200binFIG. 4, the mask is removed from over the second opening200binFIG. 5, such that copper seed24can also be deposited on the copper grain promotion material22inFIG. 5. The copper seed24comprises either copper or a copper alloy. For perspective, it should be noted that the copper seed has a thickness of between 50 A and 500 A, while the copper grain promotion material has a thickness between 5 A and 80 A.

FIG. 6depicts the final step of the method of the present invention and the structure of the present invention. Once the copper seed24has been deposited on the copper grain promotion material22in200aand onto the barrier layer14in200b, copper is electroplated in both the first200aand second openings200b. Note that the copper grain promotion material22caused the first opening200ato have a grain size that is larger (e.g. closer to bamboo-type microstructure) than the grain size in the second opening that does not include a layer of copper grain promotion material22. More specifically, the copper grain promotion material22caused the first opening200ato have a copper grain size that is 20.0% larger than the grain size of the electroplated copper in the second opening200b. The first200aand second openings200bare embedded in the same insulating level layer. Therefore, the present invention creates Cu interconnects with divergent copper grain sizes and as such, applications that require a Cu interconnect with a large copper grain size, e.g., copper interconnect, are created in the same insulating level layer as applications that require a Cu interconnect with a small copper grain size, e.g. fuses.

While the invention has been particularly described in conjunction with a specific preferred embodiment and other alternative embodiments, it is evident that numerous alternatives, modifications and variations will be apparent to those skilled in the art in light of the foregoing description. It is therefore intended that the appended claims embrace all such alternatives, modifications and variations as falling within the true scope and spirit of the invention.