Semiconductor storage device

According to one embodiment, a semiconductor storage device includes: a memory cell array including a plurality of bit lines; a sense amplifier; a first circuit including a plurality of transistors respectively connected to the plurality of bit lines and the sense amplifier; and a plurality of interconnects which are provided at a position higher than the bit lines in the first circuit and are not directly connected to the first circuit. The semiconductor storage device does not include, at a position higher than the plurality of interconnects, an interconnect which electrically connects two positions in the semiconductor storage device.

FIELD

Embodiments described herein relate generally to a semiconductor storage device.

BACKGROUND

Miniaturization of semiconductor storage devices has been advancing.

DETAILED DESCRIPTION

In general, according to one embodiment, a semiconductor storage device includes: a memory cell array including a plurality of bit lines; a sense amplifier; a first circuit including a plurality of transistors respectively connected to the plurality of bit lines and the sense amplifier; and a plurality of interconnects which are provided at a position higher than the bit lines in the first circuit and are not directly connected to the first circuit. The semiconductor rage device does not include, at a position higher than the plurality of interconnects, an interconnect which electrically connects two positions in the semiconductor storage device.

Hereinafter, embodiments, which have been constructed, will be described with reference to the accompanying drawings. In the description below, structural elements having substantially the same functions and structures are denoted by like signs. A suffix number “−X (X is an arbitrary numeral)” after a numeral, which constitutes a reference sign, is used in order to distinguish elements which are referred to by reference signs including the same numeral and have the same structure. When it is not necessary to distinguish elements which are indicated by reference signs including the same numeral, these elements are referred to by a reference sign including only the numeral. For example, when it is not necessary to distinguish elements with reference signs100-1and100-2, these elements are comprehensively referred to by a reference sign100.

It should be noted that the drawings are schematic ones, and the relationship between a thickness and a planar dimension, the ratio in thickness between layers, etc. are different from real ones. Thus, concrete thicknesses and dimensions should be judged in consideration of descriptions below. In addition, needless to say, the drawings include parts with mutually different relations or ratios of dimensions.

Hereinafter, in the present specification, an XYZ orthogonal coordinate system is introduced for the purpose of convenience in descriptions. In this coordinate system, two directions, which are parallel to a top surface of a semiconductor substrate10(to be described later) and are perpendicular to each other, are defined as a D1(X) direction and a D2(Y) direction, and a direction, which is perpendicular to both the D1direction and D2direction, that is, a direction of stacking of layers, is defined as a D3(Z) direction. In the description below, the expression “height” means a length in the D3direction.

A semiconductor storage device according to an embodiment will be described. Hereinafter, a description is given of an example in which a planar NAND-type flash memory is applied as the semiconductor storage device.

<1-0> Configuration of Memory System

To begin with, the configuration of a memory system including the semiconductor storage device according to the present embodiment will be described with reference toFIG. 1.FIG. 1illustrates the memory system including the semiconductor storage device according to the embodiment, and illustrates, in particular, some components of the storage device and a layout thereof.

As illustrated inFIG. 1, the memory system includes a NAND-type flash memory1and a memory controller2. For example, the memory controller2and NAND-type flash memory1may be combined to constitute a single semiconductor device, for instance, a memory card such as an SD™ card, or an SSD (solid state drive). In addition, the memory system may be configured to further include a host (not shown).

The NAND-type flash memory1includes a plurality of memory cells, and stores data nonvolatilely. The memory controller2is connected to the NAND-type flash memory1by a NAND bus, and is connected to a host by a host bus. In addition, the memory controller2controls the NAND-type flash memory1, and accesses the NAND-type flash memory1in response to an instruction received from the host. The host is, for example, a digital camera or a personal computer, and the host bus is a bus according to, for example, an SD interface.

The NAND bus transmits/receives signals according to a NAND interface. Concrete examples of the signals are a chip enable signal BCE, a command latch enable signal CLE, an address latch enable signal ALE, a write enable signal BWE, a read enable signal RE, BRE, a write protect signal BWP, a data strobe signal DQS, BDQS, a ready/busy signal RB, and input/output signals DQ (DQ0to DQ7). The data strobe signal BDQS is a complementary signal of the data strobe signal DQS.

<1-1> Entire Configuration of the NAND-Type Flash Memory

Referring toFIG. 1toFIG. 5, the configuration of the NAND-type flash memory (semiconductor storage device)1according to the embodiment will be schematically described.FIG. 2is a view illustrating a memory cell array according to the embodiment.FIG. 3is a view illustrating first and second interconnects in addition to the memory system ofFIG. 1.FIG. 4is a view illustrating third interconnects in addition to the memory system ofFIG. 1.FIG. 5is a view illustrating fourth interconnects in addition to the memory system ofFIG. 1.FIGS. 3 to 5illustrate the same configuration, excluding the first to fourth interconnects. In the description below, an example will be described in which the NAND-type flash memory1has two planes. However, this embodiment is also applicable to a NAND-type flash memory1including more than two planes.

FIG. 1also illustrates an example of a layout extending in the D1and D2directions of the NAND-type flash memory1according to the embodiment. As illustrated inFIG. 1, the NAND-type flash memory1includes, on a semiconductor substrate, memory cell arrays100-1and100-2, row decoders110-1,110-2,110-3and110-4, bit line hookup circuits120-1and120-2, sense amplifiers130-1and130-2, a peripheral circuit140, an input/output terminal150, a voltage generator (pump circuit)160, a driver170, hookup regions180-1,180-2,180-3and180-4, and hookup regions181-1,181-2,181-3and181-4.

A first plane includes the memory cell array100-1, row decoders110-1and110-2, bit line hookup circuit120-1, sense amplifier130-1, hookup regions180-1and180-2, and hookup regions181-1and181-2. A second plane includes the memory cell array100-2, row decoders110-3and110-4, bit line hookup circuit120-2, sense amplifier130-2, hookup regions180-3and180-4, and hookup regions181-3and181-4. The peripheral circuit140, input/output terminal150, voltage generator160and driver170are shared by the plural planes.

The input/output terminal150extends along one side (a side along the D1direction) of the NAND-type flash memory1, and is provided in an end region of the NAND-type flash memory1. The memory controller2and NAND-type flash memory1are connected via the input/output terminal150.

The input/output terminal150transmits the data strobe signals DQS and BDQS, input/output signals DQ and ready/busy signal RB to the memory controller2via pads (not shown).

The input/output terminal150generates the data strobe signals DQS and BDQS in accordance with a signal supplied from the peripheral circuit140. The input/output terminal150outputs the data strobe signals DQS and BDQS when outputting the data input/output signals DQ. In addition, at a timing of the data strobe signals DQS and BDQS, the memory controller2receives the data input/output signals DQ.

The input/output signals DQ form, for example, a 8-bit signal. The input/output signals DQ are a substance of data which is transmitted/received between the NAND-type flash memory1and memory controller2, and are a command, address information, write data, read data, etc.

The ready/busy signal RB is a signal which indicates whether the NAND-type flash memory1is in a ready state (a state in which the NAND-type flash memory1can receive an instruction from the memory controller2) or a busy state (a state in which the NAND-type flash memory1cannot receive an instruction from the memory controller2).

In addition, the input/output terminal150receives from the memory controller2, via pads (not shown), the chip enable signal BCE, command latch enable signal CLE, address latch enable signal ALE, write enable signal BWE, read enable signal RE, BRE, write protect signal BWP, and data strobe signal DQS, BDQS.

The chip enable signal BCE is used as a select signal of the NAND-type flash memory1.

The command latch enable signal CLE is a signal which is used when a command is taken in the peripheral circuit140.

The address latch enable signal ALE is a signal which is used when address information or input data is taken in the peripheral circuit140.

The write enable signal BWE is a signal for taking in the NAND-type flash memory1the command, address and data on the input/output terminal150.

The read enable signal RE is a signal which is used when data is serially output from the input/output terminal150. The read enable signal BRE is a complementary signal of RE.

The write protect signal IMP is used in order to protect data from unexpectable erase or write, when an input signal is uncertain, such as when the NAND-type flash memory1powered on or powered off.

Although not illustrated inFIG. 1, Vcc/Vss/Vccq/Vssq pads, etc. for power supply are also provided in the input/output terminal150.

As illustrated inFIG. 9, the input/output terminal also includes first to fourth metal layers (1st Mt to 4th ML). The first metal layer is located at a position higher than a position where, for instance, control gates of transistors on the semiconductor substrate10is provided. The second metal layer is a layer which is located at a position higher than the first metal layer, and in which interconnects or the like that are connected to the first metal layer via contact plugs or the like are provided. The third metal layer is a layer which is located higher than the second metal layer, and in which a bit line or the like is provided. The fourth metal layer is an interconnect layer which is located higher than the third metal layer, and is located at the highest position among the interconnect layers of the NAND flash memory 1. In addition, interconnects located in the fourth metal layer are thicker than interconnects located in the first to third metal layers, and have a lower resistance than the interconnects located in the first to third metal layers.

As illustrated inFIG. 2, the memory cell array100(100-1,100-2) includes a plurality of memory strings MS. Each memory string MS includes a select transistor ST, a plurality of memory cell transistors (also referred to simply as memory cells or the like) MC, and a select transistor ST, which are connected in series. One of the select transistors ST is connected to a source line SL, and the other select transistor ST is connected to a bit line BL. Specifically, each memory string MS is connected to the bit line BL, a plurality of word lines WL, and the source line SL.

Each memory cell transistor MC stores data nonvolatilely, and the data is electrically rewritable. The memory cell transistors MC are arranged, for example, three-dimensionally. The memory cell transistor MC includes, for example, a stacked gate including a control gate electrode and a charge storage layer (e.g. a floating gate electrode), and stores single-level data or multilevel data in accordance with a variation of a threshold of the transistor, which is determined by a charge amount injected in the floating gate electrode. In addition, the memory cell transistor MC may have a MONOS (Metal-Oxide-Nitride-Oxide-Silicon) structure in which electrons are trapped in a nitride film.

A dummy memory cell transistor may be included between a select transistor ST and a memory cell transistor MC. Besides, a select transistor ST or a dummy memory cell transistor may be additionally provided between the plural memory cell transistors MC.

The source line SL and bit line BL may be provided for each of the memory strings MS, or may be shared by the memory strings MS.

The configuration of the memory cell array100is disclosed in U.S. patent application Ser. No. 12/397,711 filed Mar. 3, 2009 and entitled “SEMICONDUCTOR MEMORY DEVICE HAVING PLURALITY OF TYPES OF MEMORIES INTEGRATED ON ONE CHIP”. In addition, the configuration thereof is disclosed in U.S. patent application Ser. No. 13/451,185 filed Apr. 19, 2012 and entitled “SEMICONDUCTOR MEMORY DEVICE INCLUDING STACKED GATE HAVING CHARGE ACCUMULATION LAYER AND CONTROL GATE AND METHOD OF WRITING DATA TO SEMICONDUCTOR MEMORY DEVICE”, in U.S. patent application Ser. No. 12/405,626 filed Mar. 17, 2009 and entitled “NONVOLATILE SEMICONDUCTOR MEMORY ELEMENT, NONVOLATILE SEMICONDUCTOR MEMORY, AND METHOD FOR OPERATING NONVOLATILE SEMICONDUCTOR MEMORY ELEMENT”, and in U.S. patent application Ser. No. 09/956,986 filed Sep. 21, 2001 and entitled “NONVOLATILE SEMICONDUCTOR MEMORY DEVICE HAVING ELEMENT ISOLATING REGION OF TRENCH TYPE AND METHOD OF MANUFACTURING THE SAME”. The entire descriptions of these patent applications are incorporated by reference herein.

Referring back toFIG. 1, the row decoders110-1and110-2extend in the D2direction, and sandwich the memory cell array100-1in the D1direction. The row decoders110-1an110-2select a block BLK of the memory cell array100-1at a time of a read operation, a write operation or an erase operation of data. The row decoders110-1and110-2transfer a voltage, which is necessary in the read operation, write operation or erase operation, to the word line WL and a select gate line SGL of the memory cell array100-1.

The row decoders110-3and110-4extend in the D2direction, and sandwich the memory cell array100-2in the D1direction. Like the row decoders110-1and110-2, the row decoders110-3and110-4select a block BLK of the memory cell array100-2at a time of a read operation, a write operation or an erase operation of data. The row decoders110-3and110-4transfer a voltage, which is necessary in the read operation, write operation or erase operation, to the word line WL and a select gate line SGL of the memory cell array100-2.

The bit line hookup circuit120-1is juxtaposed with the memory cell array100-1in the D2direction and is arranged along the memory cell array100-1. The length in the D2direction of the bit line hookup circuit120-1is S1. In the bit line hookup circuit120-1, transfer transistors, which transfer signals between the bit lines BL in the memory cell array100-1and the sense amplifier130-1, are disposed. In other words, the bit lines BL in the memory cell array100-1are connected to the sense amplifier130-1via the transfer transistors. The bit line hookup circuit120-1controls a connection between the bit lines BL and sense amplifier130-1, based on control signals from a column controller140a.

The bit line hookup circuit120-2is juxtaposed with the memory cell array100-2in the D2direction and arranged along the memory cell array100-2. The length in the D2direction of the bit line hookup circuit120-2is S1. In the bit line hookup circuit120-2, transfer transistors, which transfer signals between the bit lines BL in the memory cell array100-2and the sense amplifier130-2, are disposed. In other words, the bit lines BL in the memory cell array100-2are connected to the sense amplifier130-2via the transfer transistors. The bit line hookup circuit120-2controls a connection between the bit lines BL and sense amplifier130-2, based on control signals from the column controller140a.

The bit line hookup circuits120-1and120-2also include first to fourth metal layers.

The hookup regions180-1and180-2sandwich the bit line hookup circuit120-1in the D1direction, receive word line drive signals from the driver170, and supply the received word line drive signals to the row decoders110-1and110-2. Besides, the hookup regions180-1and180-2include first to fourth metal layers.

The hookup regions180-3and180-4sandwich the bit line hookup circuit120-2in the D1direction, receive word line drive signals from the driver170, and supply the received word line drive signals to the row decoders110-3and110-4. Besides, the hookup regions180-3and180-4include first to fourth metal layers.

The sense amplifier130-1is provided along the bit line hookup circuit120-1, and the sense amplifier130-1and memory cell array100-1sandwich the bit line hook up circuit120-1in the D2direction. The length of the sense amplifier130-1in the D2direction is S2. The sense amplifier130-1includes sense circuits (not shown) which sense-amplify voltages of the bit lines BL in the memory cell array100-1, and data storage circuits (not shown) for latching read-out data or data to be written. The sense amplifier130-1senses data of the memory cell transistors MC in the memory cell array100-1via the bit lines BL. The sense amplifier130-1operates, based on first column control signals (1st COL control signals) and second column control signals (2nd COL control signals).

The sense amplifier130-2is provided along the bit line hookup circuit120-2, and the sense amplifier130-2and memory cell array100-2sandwich the bit line hookup circuit120-2in the D2direction. The length of the sense amplifier130-2in the D2direction is S2. The sense amplifier130-2includes sense circuits (not shown) which sense-amplify voltages of the bit lines BL in the memory cell array100-2, and data storage circuits (not shown) for latching read-out data or data to be written. The sense amplifier130-2senses data of the memory cell transistors MC in the memory cell array100-2via the bit lines BL. The sense amplifier130-2operates, based on first column control signals and second column control signals.

The hookup regions181-1and181-2sandwich the sense amplifier130-1in the D1direction. The hookup regions181-3and181-4sandwich the sense amplifier130-2in the D1direction.

The peripheral circuit140extends in the D1direction, and is provided to neighbor the sense amplifiers130. The peripheral circuit140includes, for example, data transfer circuits (not shown), a control circuit (not shown) and a column controller140a. The length in the D2direction of the peripheral circuit140is S3. The data transfer circuit receives the data of the memory cell transistors MC, which is read out by the sense amplifiers130to the data storage circuit, and transfers the received data to the input/output terminal150. Then, the data is output from the input/output terminal150to the outside (memory controller2or host).

The control circuit controls the NAND-type flash memory1in accordance with a control signal and a command, which are input via the input/output terminal150. Specifically, the control circuit controls the memory cell arrays100, row decoders110, bit line hookup circuits120, sense amplifiers130, input/output buffer, column controller140a, input/output terminal150, voltage generator160, and driver170. Although the control circuit was described as being provided in the peripheral circuit140, the peripheral circuit140itself may be configured as the control circuit.

The column controller140ais provided in the peripheral circuit140near lower portions of the hookup regions181-2and181-3in the D2direction. The column controller140agenerates first and second column control signals. As will be described later with reference toFIG. 3, the first column control signals are supplied to the sense amplifiers130via first interconnects191. The second column control signals are supplied to the sense amplifiers130via the hookup regions181and second interconnects192. The details will be described later.

The peripheral circuit also includes first to fourth metal (4th ML) layers.

The voltage generator160is provided at a region of an end portion of the NAND-type flash memory1and is provided to neighbor the input output terminal150and peripheral circuit140. The length in the D2direction of the voltage generator160is S4. The voltage generator160includes, for example, a charge pump, and increases a power supply voltage as needed, based on an instruction from the control circuit. The voltage generator160supplies the increased voltages (pump outputs) to the components in the NAND-type flash memory1. For example, as will be described later with reference toFIG. 4, the voltage generator160supplies voltages to the peripheral circuit140and driver170via third interconnects193. The voltage generator160also includes first to fourth metal layers.

When the driver170is supplied with the voltages from the voltage generator160, the driver170generates word line drive signals. As will be described later with reference toFIG. 5, the driver170supplies the word line drive signals to the hookup regions180via fourth interconnects (parts of CG lines and SG lines)194. The length in the D2direction of the driver170is S3. The CG line is connected to the word line WL via the row decoder110. The SG line is connected to the select gate line SGL via the row decoder110. The driver170also includes first to fourth metal layers.

Referring toFIGS. 3 to 5, a description will now be given of the transmission of the first and second column control signals from the column controller140a, the increased voltages from the voltage generator160, and the word line drive signals from the driver170.FIGS. 3toFIG. 5illustrate, in addition to the components ofFIG. 1, the paths of the first and second column control signals, increased voltages and word line drive signals. In particular,FIGS. 3toFIG. 5illustrate the first to fourth interconnects191to194among the paths. The first to fourth interconnects191to194are realized by arbitrary ones of the interconnects located in the first to fourth metal layers and contacts which mutually connect a plurality of interconnects used among the interconnects located in the first to fourth metal layers. The first to fourth interconnects191to194will be described later in detail.

The first column control signals are classified into at least first to fourth types. One or more first column control signals belonging to an identical type are supplied along similar paths.

As illustrated inFIG. 3, the first column control signals of the first type are supplied to the sense amplifier130-1via the first interconnects191provided on the hookup regions181-2and180-2, bit line hookup circuit120-1and hookup regions180-1and181-1.

The first column control signals of the second type are supplied to the sense amplifier130-1via the first interconnects191provided on the hookup region181-2.

The first column control signal of the third types are supplied to the sense amplifier130-2via the first interconnects191provided on the hookup region181-3.

The first column control signals of the fourth type are supplied to the sense amplifier130-2via the first interconnects191provided on the hookup regions181-3and180-3, bit line hookup circuit120-2and hookup regions180-4and181-4.

The second column control signals are classified into at least first to fourth types. One or more second column control signals belonging to an identical type are supplied along similar paths.

The second column control signals of the first type are transmitted to the hookup region181-1by the second interconnect192provided on the hookup regions181-2and180-2, bit line hookup circuit120-1and hookup regions180-1and181-1. The hookup region181-1receives the second column control signals of the first type, and supplies the received second column control signals of the first type to the sense amplifier130-1.

The second column control signals of the second type are transmitted to the hookup region181-2by the second interconnects192provided on the hookup region181-2. The hookup region181-2receives the second column control signals of the second type, and supplies the received second column control signals of the second type to the sense amplifier130-1.

The second column control signals of the third type are transmitted to the hookup region181-3by the second interconnects192provided on the hookup region181-3. The hookup region181-3receives the second column control signals of the third type, and supplies the received second column control signals of the third type to the sense amplifier130-2.

The second column control signals of the fourth type are transmitted to the hookup region181-4by the second interconnects192provided on the hookup regions181-3and180-3, bit line hookup circuit120-2and hookup regions180-4and181-4. The hookup region181-4receives the second column control signals of the fourth type, and supplies the received second column control signals of the fourth type to the sense amplifier130-2.

By such transmission of the first and second column control signals, the sense amplifiers130directly or indirectly receive the column control signals from the first interconnects191and second interconnects192.

As illustrated inFIG. 4, some of the voltages from the voltage generator160are supplied to the peripheral circuit140via the third interconnects193provided on the hookup regions181-1and180-1, bit line hookup circuit120-1and hookup regions180-2and181-2. Some of the voltage from the voltage generator160are supplied to the peripheral circuit140via the third interconnects193provided on the hookup regions181-1and180-1, bit line hookup circuit120-1and hookup regions180-2,180-3and181-3. Some of the voltages from the voltage generator160are supplied to the driver170via the third interconnects193provided on the hookup regions181-1and180-1, bit line hookup circuit120-1, hookup regions180-2and180-3, bit line hookup circuit120-2, and hookup regions180-4and181-4.

As illustrated inFIG. 5, some of the word line drive signals from the driver170are supplied to the hookup region180-4via the fourth interconnects194provided on the hookup regions181-4and180-4. Some of the word line drive signals from the driver170are supplied to the hookup region180-3via the fourth interconnects194provided on the hookup regions181-4and180-4, bit line hookup circuit120-2and hookup region180-3. Some of the word line drive signals from the driver170are supplied to the hookup region180-2via the fourth interconnects194provided on the hookup regions181-4and180-4, bit line hookup circuit120-2and hookup regions180-3and180-2. Some of the word line drive signals from the driver170are supplied to the hookup region180-1via the fourth interconnects194provided on the hookup regions181-4and180-4, bit line hookup circuit120-2, hookup regions180-3and180-2, bit line hookup circuit120-1and hookup region180-1.

By the provision of the paths for transmitting the signals and voltages as described above, the first interconnects191, second interconnects192, third interconnects193and fourth interconnects194, which are not connected to the bit line hookup circuit120-1, are provided in the region above the bit line hookup circuit120-1. The first interconnects191, second interconnects192, third interconnects193and fourth interconnects194are located in the fourth metal layer as described above.

Similarly, the first interconnects191, second interconnects192, third interconnects193and fourth interconnects194, which are not connected to the bit line hookup circuit120-2, are provided in the region above the bit line hookup circuit120-2. The first interconnects191, second interconnects192, third interconnects193and fourth interconnects194are located in the fourth metal layer as described above.

<1-2> Sense Amplifier and Bit Line Hookup Circuit

Referring toFIG. 6, the sense amplifier and bit line hookup circuit according to the present embodiment will now be described. As the sense amplifier130described here, a sense amplifier will be described by way of example, which determines data by sensing (current sense method) a current which reads page data (a page is composed of, for example, a plurality of memory cell transistors MT that are connected to an identical word line) by simultaneously driving all bit lines in the memory cell array100.

The bit line hookup circuit120includes a plurality of transistors TF (transfer transistors). In the bit line hookup circuit120, a bit line BL is connected to one end of a transistor TF. The transistor TF is, for example, high breakdown voltage transistor. The other end of the transistor TF is connected to one end of a transistor36in a sense module131.

The sense amplifier130includes a plurality of sense modules131. Transistors in each sense modules131are, for example, low breakdown voltage transistors. The plural sense modules131are connected to the bit lines BL via the transistors TF. The transistor TF controls a connection, based on a control signal BLS from the column controller140a.

The sense module131is composed of a clamp circuit32, a precharge circuit33, a judgment circuit34and latch circuits35A and35B.

The clamp circuit32is composed of N-channel MOS transistors36and37. The transistor36is controlled by a signal LATB, and the transistor37is controlled by a signal BLX. The precharge circuit33is composed of a P-channel MOS transistor38. The transistor38is controlled by a signal FLT. The judgment circuit34is composed of P-channel MOS transistors40and41, N-channel MOS transistors42,52and53and a capacitor39. The transistor40is controlled by a signal STB, and the transistor41is controlled by a signal SEN. In addition, the transistor42is controlled by a signal RST, the transistor52is controlled by a signal LSA, and the transistor53is controlled by a signal LSB.

The latch circuit35A includes two inverters which are flip-flop-connected, namely P-channel MOS transistors43A and44A and N-channel MOS transistors45A and46A. A P-channel MOS transistor47A and an N-channel MOS transistor48A are used in order to activate/inactivate the latch circuit35A. The transistor43A is controlled by a signal LATA, and the transistor44A is controlled by a signal INVA. The transistor45A is controlled by the signal LATA, and the transistor46A is controlled by the signal INVA. The transistor47A is controlled by the signal RST, and the transistor48A is controlled by the signal STB.

The potential of a sense node SEN is latched by the latch circuit35A via the N-channel MOS transistor52. The data latched by the latch circuit35A is not used for a lockout operation for forcibly disconnecting the sense node SEN from the bit line.

The latch circuit35B includes two inverters which are flip-flop-connected, namely P-channel MOS transistors43B and44B and N-channel MOS transistors45B and46B. A P-channel MOS transistor47B and an N-channel MOS transistor483are used in order to activate/inactivate the latch circuit35B. The transistor43B is controlled by a signal LATB, and the transistor44B is controlled by a signal INVB. The transistor45B is controlled by the signal LATB, and the transistor46B is controlled by the signal INVB. The transistor47B is controlled by the signal RST, and the transistor48B is controlled by the signal STB.

The potential of the sense node SEN is latched by the latch circuit35B via the N-channel MOS transistor53. The data latched by the latch circuit35B is used for the lockout operation for forcibly disconnecting the sense node SEN from the bit line.

In the meantime, as the sense module131, various configurations are applicable. For example, the configuration disclosed in U.S. patent application Ser. No. 12/563,296 filed Sep. 21, 2009 and entitled “NONVOLATILE SEMICONDUCTOR MEMORY” is applicable. The entire descriptions of this patent application are incorporated by reference herein.

In addition, as the sense module131, various configurations are applicable. For example, the configuration disclosed in U.S. patent application Ser. No. 15/185,671 filed Jun. 17, 2016 and entitled “SEMICONDUCTOR MEMORY DEVICE” is applicable. The entire descriptions of this patent application are incorporated by reference herein.

<1-3> Interconnect Layer, and Interconnects of Bit Line Hookup Circuit

Referring toFIGS. 7 to 9, the first interconnects191, second interconnects192, third interconnects193, fourth interconnects194and bit line hookup circuit120will now be described in detail. Hereinafter, in some cases, a set of the first interconnects191, second interconnects192, third interconnects193and fourth interconnects194is referred to as “interconnects190”. The description of the interconnects190is also applicable to each of the first interconnects191, second interconnects192, third interconnects193and fourth interconnects194.

FIG. 7schematically illustrates connections between the interconnects190and the components of the NAND-type flash memory1, and also illustrates the positional relationship between the interconnects190and bit lines BL. InFIG. 7, the components in the NAND-type flash memory1are depicted as schematic blocks.

The bit line hookup region120includes a plurality of transistors TF.

Each bit line BL is connected to the memory cell array100and one end of the transistor TF. The other end of the transistor TF is connected to the transistor in the sense amplifier130. The bit lines BL are realized by interconnects121, and the interconnects121are located in, for example, the third metal layer. An interconnect121is connected to a diffusion layer corresponding to the source or drain of the transistor TF provided on the semiconductor substrate10by a contact (not shown) and another interconnect (not shown).

As described above, the first interconnects191, in at least a portion thereof, traverse the bit line hookup circuit120, and connect the column controller140aand sense amplifier130. The second interconnects192, in at least a portion thereof, traverse the bit line hookup circuit120, and connect the column controller140aand hookup circuits181-1to181-4. The third interconnects193, in at least portions thereof, traverse the bit line hookup circuit120, and connect the voltage generator160and peripheral circuit140and connect the voltage generator160and driver170. The fourth interconnects194, in at least a portion thereof, traverse the bit line hookup circuit120, and connect the hookup circuits180-1to180-4and driver170.

Hereinafter, that portion of each of the interconnects190(i.e. first interconnects191, second interconnects192, third interconnects193and fourth interconnects194), which traverses the bit line hookup circuit120, is referred to as “a first portion200”. Specifically, each of the first interconnects191, second interconnects192, third interconnects193and fourth interconnects194includes its own first portion200.

The structure of the interconnects121and interconnects (first portions)200is as illustrated inFIGS. 8 and 9.FIG. 8illustrates a part of the structure of the bit line hookup region120along the D1direction and D2direction.FIG. 9illustrates the structure of the bit line hookup region120along the D1direction and D3direction, and illustrates the structure along line A-A inFIG. 8. In order to make easily understandable the features of the interconnects190in the bit line hookup circuit120,FIG. 8does not illustrate components other than the first portions200of interconnects190and the interconnects121.

As illustrated inFIGS. 8 and 9, in the bit line hookup circuit120, a plurality of interconnects121are provided. The interconnects121are provided above, in the D3direction, region of the semiconductor substrate10and in an insulator122, and are located in the third metal layer. The plural interconnects121extend in parallel to each other, for example, along the D2direction, and are provided at intervals of a length S5.

In the bit line hookup circuit120, the first portions200of the interconnects190are provided on the insulator122and in a region above, in the D3direction, the interconnects121, and are located in the fourth metal layer. The plural interconnects190(the first portions200of the interconnects190) extend in parallel to each other, for example, along the D1direction, and are provided intervals of a length S6(S5<S6). In other words, the interconnects190include portions which extend in parallel over a predetermined section, and such portions are located, for example, on the bit line hookup circuit120, and are the first portions200.

As described above, the interconnects121are located in the third metal layer, and the interconnects190are located in the fourth metal layer. Thus, as is understood fromFIG. 8, when the bit line hookup circuit120is seen from above (from above the semiconductor substrate10), the plural interconnects121and plural interconnects190intersect.

As described above, the interconnects190extend in the D1direction in the bit line hookup circuit120, or in other words, the first portions200of the interconnects190extend in the D1direction. In contrast, some of the interconnects190extend also in the D2direction in the hookup regions180-1,180-2,180-3,180-4,181-1,181-2,181-3and181-4. Besides, some of the interconnects190(e.g. first interconnects191, second interconnects192, third interconnects193) may include bent portions in the hookup regions180(seeFIG. 3andFIG. 4).

The bit line hookup circuit120is provided with contact plugs (not shown) which connect the interconnect121of the third metal layer, which function as the bit lines BL, to the second metal layer.

An insulator123is provided on the interconnects190(first portions200). In addition, an interconnect layer124may be provided on the insulator123. However, interconnects provided on or above the insulator123have different functions from the first to fourth metal layers and belong to different types from the first to fourth metal layers. Specifically, the interconnects located in the first to fourth metal layers, which include the interconnects190, interconnect the components in the inside of the NAND-type flash memory1. In contrast, the interconnect layer124includes, for example, re-distribution layers. Unlike the interconnects located in the first to fourth metal layers, each re-distribution layer is, at least at one end thereof, connected to a component outside the NAND-type flash memory1. Specifically, the re-distribution layer connects, for example, a pad included in the input/output terminal150and a printed wiring board on which the NAND-type flash memory1is provided. Accordingly, in the present embodiment, unlike the first to fourth metal layers, the interconnect layer124including the re-distribution layers is not treated as an interconnect layer. Specifically, even if the re-distribution layer124is provided above the fourth metal layer, the interconnect layer located at the highest position among the interconnect layers of the NAND-type flash memory1is the fourth metal layer. In addition, the interconnects190are interconnects which are located in the fourth metal layer and are thus located at the highest position.

When the interconnect layer124is provided, an insulator125is provided on the interconnect layer124.

Interconnects that are connected to the bit line hookup circuit120may be provided in the fourth metal layer of the bit line hookup circuit120.

According to the above-described embodiment, the interconnects (first interconnects191and second interconnects192) for first and second column control signals, the interconnects (third interconnects193) for transferring voltages which are supplied from the voltage generator160to the peripheral circuit140and driver170, and the interconnects (fourth interconnects194) for the word line drive signals which are supplied from the driver170to the hook up region180, are provided in the upper region in the D3direction of the bit line hookup circuit120. Thereby, the circuit area of the NAND-type flash memory1can be reduced.

Hereinafter, a comparative example will be described in order to make easier the understanding of the advantageous effects of the above-described embodiment.

In the comparative example, a description is given of the case in which the interconnects for transmitting the first and second column control signals, the interconnects for transmitting voltages which are supplied from the voltage generator160and the interconnects for transmitting the word line drive signals from the driver170are provided in a peripheral circuit140b.

Sixth interconnects216for transmitting the first and second column control signals, seventh interconnects217for transmitting the voltages from the voltage generator160and eighth interconnects218for transmitting the word line drive signals from the driver170are provided in the fourth metal layer. The sixth interconnects216, seventh interconnects217and eighth interconnects218need to be disposed in the peripheral circuit140bsuch that the sixth interconnects216, seventh interconnects217and eighth interconnects218reach the destinations of transmission of signals and voltages. As a result, the peripheral circuit140bneeds to have such a space as to make it possible to dispose the sixth interconnects216, seventh interconnects217and eighth interconnects218in the fourth metal layer. Thus, as illustrated inFIG. 10, the length in the D2direction of the peripheral circuit140bneeds to be increased by, for example, length S1.

In this case, the length in the D2direction of the NAND-type flash memory1according to the comparative example is greater by the length S1than the length in the D2direction of the above-described NAND-type flash memory1. In this manner, the decrease in length in the D2direction of the peripheral circuit140bis limited because the arrangement of the sixth interconnects216, seventh interconnects217and eighth interconnects218becomes a bottleneck.

In the embodiment, the first interconnects191and second interconnects192for transmitting the first and second column control signals, the third interconnects193for transmitting the voltages from the voltage generator160and the fourth interconnects194for transmitting the word line drive signals are provided on the bit line hookup circuit120in which the ratio of occupation of the interconnects in the D1-D2plane in the fourth metal layer is originally small. It is thus possible to prevent the circuit area of the NAND-type flash memory1from increasing like the NAND-type flash memory1of the comparative example.

In Modification1, only the different parts from the above-described embodiment will be described with reference toFIG. 11. Modification1differs from the above-described embodiment with respect to the third interconnects193.

As illustrated inFIG. 11, a part of some of the third interconnects193are located in the fourth metal layer on the sense amplifier130. Specifically, some of the voltages from the voltage generator160are supplied to the peripheral circuit140via the third interconnects193provided on the sense amplifier130-1and hookup region181-2. Some of the voltages from the voltage generator160are supplied to the peripheral circuit140via the third interconnects193provided on the sense amplifier130-1and hookup regions181-2and181-3. Some of the voltages from the voltage generator160are supplied to the driver170via the third interconnects193provided on the sense amplifier130-1, hookup regions181-2and181-3, sense amplifier130-2and hookup region181-4.

In Modification2, only the different parts from the above-described embodiment will be described with reference toFIG. 12. Modification2differs from the above-described embodiment with respect to the fourth interconnects194.

As illustrated inFIG. 12, a part of some of the fourth interconnects194are located in the fourth metal layer on the sense amplifier130. Specifically, some of the word line drive signals from the driver170are supplied to the hookup region180-3via the fourth interconnects194provided on the hookup region181-4, sense amplifier130-2and hookup regions181-3and180-3. Some of the word line drive signals from the driver170are supplied to the hookup region180-2via the fourth interconnects194provided on the hookup region181-4, sense amplifier130-2and hookup regions181-3,181-2and180-2. Some of the word line drive signals from the driver170are supplied to the hookup region180-1via the fourth interconnects194provided on the hookup region181-4, sense amplifier130-2, hookup regions181-3and181-2, sense amplifier130-1and hookup regions181-1and180-1.

In addition, in the above-described embodiment, although the bit line hookup circuit120and sense amplifier130were described as different structural elements, the bit line hookup circuit120and sense amplifier130may be configured as a single component.

Besides, in the above-described embodiment, the case was described in which the planar memory is applied as the memory cell array100. However, even when a three-dimensional stacked memory is applied as the memory cell array100, the same advantageous effects as in the above-described embodiment can be obtained.

The layout of the components of the NAND-type flash memory1, which extends in the D1and D2directions, is not limited to the above-described example. In this embodiment, arbitrary layouts are applicable. For example, the arrangement of the peripheral circuit140and sense amplifiers130may be different from the arrangement shown inFIG. 3, etc. as long as the interconnects that are not connected to the bit line hookup circuit120are arranged above the bit line hookup region120. To be more specific, the position of the column controller140amay differ from the position inFIG. 3, etc., and the position of the voltage generator160and/or driver170may differ from the position inFIG. 3, etc.

The configuration of the memory cell array100is disclosed in U.S. patent application Ser. No. 12/407,403 filed 19 Mar. 2009 and entitled “three dimensional stacked nonvolatile semiconductor memory”. In addition, the configuration thereof is disclosed in U.S. patent application Ser. No. 12/406,524 filed 18 Mar. 2009 and entitled “three dimensional stacked nonvolatile semiconductor memory”, in U.S. patent application Ser. No. 13/816,799 filed 22 Sep. 2011 and entitled “nonvolatile semiconductor memory device”, and in U.S. patent application Ser. No. 12/532,030 filed 23 Mar. 2009 and entitled “semiconductor memory and method for manufacturing the same”. The entire descriptions of these patent applications are incorporated by reference herein.

In addition, in each embodiment of the present invention,

(1) in the read operation,

the voltage applied to a word line selected in the read operation of A level is, for example, 0 V to 0.55 V. However, the voltage is not limited to this and may be 0.1 V to 0.24 V, 0.21 V to 0.31 V, 0.31 V to 0.4 V, 0.4 V to 0.5 V, or 0.5 V to 0.55 V.

The voltage applied to a word line selected in the read operation of B level is, for example, 1.5 V to 2.3 V. However, the voltage is not limited to this and may be 1.65 V to 1.8 V, 1.8 V to 1.95 V, 1.95 V to 2.1 V, or 2.1 V to 2.3 V.

The voltage applied to a word line selected in the read operation of C level is, for example, 3.0 V to 4.0 V. However, the voltage is not limited to this and may be 3.0 V to 3.2 V, 3.2 V to 3.4 V, 3.4 V to 3.5 V, 3.5 V to 3.6 V, or 3.6 V to 4.0 V.

The time (tR) of the read operation can be, for example, 25 μs to 38 μs, 38 μs to 70 μs, or 70 μs to 80 μs.

(2) The write operation includes a program operation and a verify operation, as described above. In the write operation,

the voltage first applied to a word line selected at the time of program operation is, for example, 13.7 V to 14.3 V. However, the voltage is not limited to this and may be, for example, 13.7 V to 14.0 V, or 14.0 V to 14.6 V.

The voltage first applied to a selected word line when writing to an odd-numbered word line and the voltage first applied to a selected word line when writing to an even-numbered word line may be different.

When the program operation is performed by the ISPP method (Incremental. Step Pulse Program), the step-up voltage is, for example, 0.5 V.

The voltage applied to a non-selected word line can be, for example, 6.0 V to 7.3 V. However, the voltage is not limited to this and may be, for example, 7.3 V to 8.4 V, or 6.0 V or less.

The pass voltage to be applied may be changed depending on whether the non-selected word line is an odd-numbered word line or an even-numbered word line.

The time (tProg) of the write operation can be, for example, 1700 μs to 1800 μs, 1800 μs to 1900 μs, or 1900 μs to 2000 μs.

(3) In the erase operation,

the voltage first applied to a well formed in the upper portion of a semiconductor substrate and having the memory cell arranged above is, for example, 12 V to 13.6 V. However, the voltage is not limited to this and may be, for example, 13.6 V to 14.8 V, 14.8 V to 19.0 V, 19.0 V to 19.8 V, or 19.8 V to 21 V.

(4) The configuration of the memory cell includes:

a charge accumulation layer arranged on a 4 to 10 nm thick tunnel insulating film on a semiconductor substrate (silicon substrate). The charge accumulation layer can have a stacked structure including a 2 to 3 nm thick insulating film made of, e.g. SiN or SiON, and a 3 to 8 nm thick polysilicon film. A metal such as Ru may be added to polysilicon. An insulating film is formed on the charge accumulation layer. This insulating film includes, for example, a 4 to 10 nm thick silicon oxide film sandwiched between a 3 to 10 nm thick lower high-k film and a 3 to 10 nm thick upper high-k film. The high-k films are made of, for example, HfO. The silicon oxide film can be thicker than the high-k films. A 30 nm to 70 nm thick control electrode is formed on a 3 to 10 nm thick material on the insulating film. A material used to adjust the work. function is a metal oxide film such as TaO or a metal nitride film such as TaN. W or the like can be used for the control electrode.

An air gap can be formed between the memory cells.