Multiplying delay-locked loop using sampling time-to-digital converter

A multiplying delay-locked loop circuit includes a delay chain including a plurality of variable delay circuits connected in series and having a delay chain output, and a feedback loop including circuitry for deriving a digital control signal representing magnitude and sign of phase offset in the delay chain output, for controlling delay in ones of the variable delay circuits. The circuitry for deriving a digital control signal includes a sampling time-to-digital converter (STDC) configured to operate on a time delay between inputs to generate the digital control signal. The STDC subtracts a second difference the signals derived from the delay chain output and output of the feedback divider from a first difference between the signals derived from the delay chain output and output of the feedback divider to provide a difference value, and the difference value indicates sign and magnitude of output offset in the delay chain output.

FIELD OF USE

This disclosure relates to a multiplying delay-locked loop using a sampling time-to-digital converter to control replacement of free-running edges of the delay-locked loop with edges of a reference signal.

BACKGROUND

A delay-locked loop (DLL) may be used to lock a signal to a reference signal—i.e., to generate an output signal that has a constant delay relative to the phase of the input reference signal. In a basic delay-locked loop, the output of a variable delay chain (i.e., a chain of variable delays) is looped back to the input of a phase detector, which also has a reference signal as another input. The phase detector examines the phase difference between the looped delay chain output and the reference signal, and generates a control signal that adjusts the variable delays in the delay chain to align the phase of the delay chain output with the phase of the reference signal. Typically, the phase detector output merely indicates whether the delay chain output is ahead of or behind the reference signal and therefore whether the delay chain output should be retarded or advanced.

A multiplying delay-locked loop (MDLL) similarly uses a chain of variable delays, but the pulse edge of the reference signal (herein referred to as a “reference edge”) is used to replace the edge of a free-running oscillator (e.g., a ring oscillator) within the DLL (herein referred to as a “free-running edge”) at selected intervals (typically the selected interval corresponds to each period of the reference signal, which is normally longer than the period specified by the free-running oscillation frequency of the ring-oscillator—herein referred to as the “free-running period”—unless the multiplier N=1).

Replacing the edge of the MDLL output signal causes a perturbation of the output signal, as a rising or falling edge is moved from where it otherwise would have fallen. Such a perturbation is referred to as a “spur.”

SUMMARY

A multiplying delay-locked loop circuit according to implementations of the subject matter of this disclosure includes a delay chain including a plurality of variable delay circuits connected in series and having a delay chain output, and a feedback loop including circuitry for deriving, from feedback signals supplied by the delay chain, a digital control signal representing magnitude and sign of phase offset in the delay chain output, for controlling delay in ones of the variable delay circuits in the plurality of variable delay circuits.

In one such implementation, the feedback loop further includes a feedback divider for dividing the delay chain output that is fed back for comparison to a reference signal, thereby multiplying output of the multiplying delay-locked loop circuit.

In a variant of such an implementation, the circuitry for deriving a digital control signal includes a sampling time-to-digital converter configured to operate on a time delay between inputs, including signals derived from the delay chain output and output of the feedback divider, to generate the digital control signal as an output.

In such a variant, the sampling time-to-digital converter subtracts a second difference between the one of the signals derived from the delay chain output and output of the feedback divider and the another of the signals derived from the delay chain output and output of the feedback divider, from a first difference between the one of the signals derived from the delay chain output and output of the feedback divider and the another of the signals derived from the delay chain output and output of the feedback divider, to provide a difference value, and the difference value indicates sign and magnitude of output offset in the delay chain output.

In such a variant, the feedback loop further includes an edge generator circuit that derives the signals derived from the delay chain output and output of the feedback divider.

In that variant, the edge generator circuit includes a plurality of flip-flops clocked by the delay chain output, where the plurality of flip-flops includes a first chain of flip-flops, the output of the feedback divider is input to the first chain of flip-flops, one of the signals derived from the delay chain output and the output of the feedback divider is an output of a final flip-flop in the first chain of flip-flops, and another of the signals derived from the delay chain output and the output of the feedback divider is a delayed output of an intermediate flip-flop in the first chain of flip-flops.

In that variant, the plurality of flip-flops may include a second chain of flip-flops, the output of the feedback divider may be input also to the second chain of flip-flops, the first difference may be taken on a rising edge of output of the second chain of flip-flops, and the second difference may be taken on a falling edge of the output of the second chain of flip-flops.

In that same variant the first chain of flip-flops may include three flip-flops, and the second chain of flip-flops may include two flip-flops. In such a variant, the intermediate flip-flop in the first chain of flip-flops may be the second flip-flop in the first chain of flip-flops.

In an alternative variant, the first chain of flip-flops may include three flip-flops. The intermediate flip-flop in the first chain of flip-flops may be the second flip-flop in the first chain of flip-flops.

In another variant, the delay chain includes an input multiplexer having, as a first multiplexer input, the delay chain output and, as a second multiplexer input, a reference signal, output of the input multiplexer is an input to the edge generator circuit, and the multiplying delay-locked loop circuit further comprises selection logic that controls output of the input multiplexer based on the output of the feedback divider and the output of the input multiplexer.

A wireless transceiver may including a multiplying delay-locked loop circuit according to implementations of the subject matter of this disclosure.

A method according to implementations of the subject matter of this disclosure for controlling a multiplying delay-locked loop circuit, where the multiplying delay-locked loop circuit includes a delay chain and having a delay chain output, and a feedback loop including a feedback divider for dividing the delay chain output, includes inputting, to a sampling time-to-digital converter, signals derived from (a) an output of a delay chain having a plurality of variable delay circuits that are connected in series and fed back in a feedback loop to input of the delay chain, and (b) an output of a feedback divider in the feedback loop, the feedback divider being configured to divide the delay chain output thereby multiplying output of the delay-locked loop circuit, and inputting an output signal of the sampling time-to-digital converter as a control signal to ones of the variable delay circuits in the plurality of variable delay circuits.

A variant of such a method may further include using an edge generator to derive the signals derived from the delay chain output and output of the feedback divider for input to the sampling time-to-digital converter.

In such a variant using the edge generator includes inputting the output of the feedback divider to a first chain of flip-flops, using an output of a final flip-flop in the first chain of flip-flops as one of the signals derived from the delay chain output and the output of the feedback divider, and using an output of an intermediate flip-flop in the first chain of flip-flops as another of the signals derived from the delay chain output and the output of the feedback divider.

Such a variant may further include using the sampling time-to-digital converter to subtract a second difference between the one of the signals derived from the delay chain output and output of the feedback divider and the another of the signals derived from the delay chain output and output of the feedback divider, from a first difference between the one of the signals derived from the delay chain output and output of the feedback divider and the another of the signals derived from the delay chain output and output of the feedback divider, to provide a difference value that indicates sign and magnitude of output offset in the delay chain output.

That variant may further include inputting the output of the feedback divider also to a second chain of flip-flops, taking the first difference on a rising edge of output of the second chain of flip-flops, and taking the second difference on a falling edge of the output of the second chain of flip-flops.

Another variant further includes selecting between a reference signal and the delay chain output as an input to the edge generator. In such a variant, the selecting is based on the delay chain output and the output of the feedback divider.

DETAILED DESCRIPTION

In an MDLL, when reference edges are used to replace free-running edges of a ring oscillator, a spur, which may be a significant noise or harmonic distortion component, occurs when an imposed rising or falling edge of the reference signal does not coincide with an existing rising or falling edge of the free-running MDLL output signal. This will frequently be the case, or it would not be necessary to replace the edge in the first place. However, the further the imposed edge is from the existing edge, the worse the spur.

Known circuits—e.g., using phase detectors—generate only an advance or retard signal, advancing or retarding the output signal without regard to the degree of mismatch between the output signal and the reference signal. Some attempts have been made to measure the degree of mismatch and to modulate the advance or retard signal based on that degree of mismatch which could reduce spurs, but the measurements have not been of sufficiently fine resolution to significantly reduce spurs. For example, one attempt used a gated ring oscillator to measure the degree of mismatch. However, the resolution of a gated ring oscillator may be on the order of lops, which is not fine enough relative to the phase error which may be on the order of 1 ps or less.

In accordance with implementations of the subject matter of this disclosure, a sampling time-to-digital converter (“sampling TDC” or “STDC”) is used in the feedback loop of an MDLL to generate a phase-error correction signal with includes both sign (advance or retard) and magnitude. An STDC may be coupled to an edge generator, and configured to compare signals that represent the reference edge and the free-running edge to generate an output, such as a phase-error correction signal that represents the phase difference between the reference edge and the free-running edge. The phase-error correction signal is then configured to be fed back to the input of the MDLL to compensate for the edge difference. An STDC can have a resolution of less than 1 ps. As a result, an STDC-based MDLL has improved (i.e., reduced) spur performance and faster convergence. Moreover, in some implementations the sub-picosecond resolution eliminates the need for loop filtering because the fast convergence of MDLL output results in relatively insignificant harmonic noise components, which lowers power consumption.

One implementation of an MDLL100in accordance with the subject matter of this disclosure is shown inFIG. 1. MDLL100includes a plurality of delays111arranged as a delay chain101. Output signal121of delay chain101is fed back to input multiplexer131, whose other input is reference signal102. Multiplexer131is controlled by signal113from selection logic103.

Output signal121of delay chain101is fed back in a control loop104that includes a divide-by-N feedback divider114, although N=1 is possible. The divide-by-N feedback divider114is configured to generate a feedback signal.141that has a frequency of the loop output signal121divided by N, thus creating a frequency synthesizer for the MDLL100to generate a different frequency from a single reference frequency. If N≠1, division of the feedback signal in control loop104results in output signal121having a frequency equal to the frequency of reference signal102multiplied by N. Divided fed-back output signal141is one of the inputs to selection logic103that controls input multiplexer131. The output of input multiplexer131is the other input to selection logic103.

Selection logic103is configured, by default, to selects the feedback input of multiplexer131as output151, so that selection logic103is almost always comparing the fed-back output signal121to the divided fed-back output signal141. Alternatively, when multiplexer131outputs reference signal102, selection logic103is configured to compare the divided fed-back signal141with reference signal102. For example, whenever a rising edge of the divided fed-back output signal141is “close to” a rising edge of fed-back output signal121(e.g., no further from a rising edged of fed-back output signal121than one period of signal121), the output of selection logic103(i.e., control signal113) may consequently be “close to” a value of ‘1’. As output151is the result of multiplexing reference signal102and loop output121under control of control signal103, selection logic103will select input reference signal102in response to control signal103being “close to” a value of ‘1’. This happens every N periods of fed-back output signal121which is every period of input reference signal102. Thus, even when fed-back output signal121has a “dirty” rising edge—i.e., an irregularly rising “slope” instead of a sharp rising edge of a square-shaped pulse—due to noise components (i.e., spurs), the rising edge of fed-back output signal121is transformed into, and thus is represented by, the “clean” rising edge of reference signal102—e.g., a sharp rising edge of a square-shaped pulse.

Control loop104also includes STDC124which generates the phase error correction signal134that controls each of delays111in delay chain101. STDC124is configured to compare and obtain a time delay between two input signals (e.g., signals144and154) and convert the time delay into a digital output (e.g., signal134) representing the phase difference between the two input signals. One possible implementation of an STDC that may be used as STDC124is shown in copending, commonly-assigned U.S. patent application Ser. No. 15/370,796, filed Dec. 6, 2016, which is hereby incorporated by reference herein in its entirety. For example, STDC124subtracts signal144, indicative of edge information of divided fed-back signal141, from signal154, indicative of a reference edge, to generate phase error correction signal134which represents the magnitude and direction (i.e., sign) of the error between output signal121and reference signal102.

Signal144and signal154are generated by edge generator164whose inputs include the same inputs as selection logic103—i.e., divided fed-back output signal141and the output231of input multiplexer131. One implementation200of edge generator164is shown inFIG. 2, and includes five flip-flops201-205. Each of flip-flops201-205, as well as feedback divider114, is clocked by the output231of input multiplexer131(labelled “VCO” inFIGS. 2 and 3). Divider output206passes through flip-flops201and202to provide DIV signal216. Divider output207, having twice the frequency of divider output206, passes through flip-flops203,204and205to provide disable (DIS) signal217. The output of flip-flop203is double-divided (DIV2×) signal218. The output of flip-flop204is enable (EN) signal219. Digital-to-time conversion of EN signal218at208yields delayed enable (EN_DLY) signal220.

The relationships of the various signals in the circuit ofFIG. 2are shown inFIG. 3. As seen, at each rising edge of DIV signal216, representing one complete cycle of VCO signal231, the ‘ON’ portion of the first period of VCO signal231is lengthened from its normal period T to T+Δ, where Δ represents the perturbation caused by the imposed phase error correction. At each falling edge of DIV signal216, VCO signal231has its normal period T.

Perturbation Δ can be determined by subtracting T from T+Δ. However, if dt is the delay between EN signal219and EN_DLY signal220, it can be seen fromFIG. 3that perturbation Δ also can be determined by subtracting T−dt from T+Δ−dt. That is, the difference between EN_DLY144and DIS154on the falling edge of DIV is subtracted from the difference between EN_DLY and DIS on the rising edge of DIV. “Zooming in” on the error to start with these smaller quantities for the subtraction increases the resolution of the result, without using conventional approaches such as a loop filter to filter the noise components. In this way, power consumption may be reduced. The subtraction T+Δ−dt−(T−dt)=Δ is performed in STDC124, where the differences, at two different times determined by rising and falling edges of DIV signal216, between the inputted time durations of DIS signal217and EN_DLY signal219(shown inFIG. 3) are converted to a digital (binary) value that is error correction signal134, to control delays111in delay chain101.

In STDC124, depending on how close the detected edges of signals144and154are to each other, STDC output134may have a saturated maximum value or a saturated minimum value. Coarse tune signal135, which is derived during calibration of the MDLL by observing the saturated maximum value and the saturated minimum value, is applied to edge generator164to bring STDC output134closer to a midpoint between the maximum and minimum saturation levels.

An implementation of a method400according to the subject matter of this disclosure is diagrammed inFIG. 4. At401, an edge generator is used to derive signals from the delay chain output and the feedback divider output of a multiplying delay-locked loop to be controlled. At402, the signals derived using the edge generator are input to a sampling time-to-digital converter. At403, the output signal of the sampling time-to-digital converter is input as a control signal to each variable delay circuit in the delay chain.

Thus, the apparatus and/or methods described above provide an MDLL with sub-picosecond resolution by utilizing an STDC to fine tune the delay chain of the MDLL. The resulting sub-picosecond resolution provides relatively insignificant noise components and thus fast convergence of the MDLL output. Power consumption is also reduced as loop filtering to filter noise components may be omitted from the MDLL. Such an MDLL may be used anywhere that clock generation is required. For example, such an MDLL501can be used in a wireless transceiver such as a WiFi base station or access point500(FIG. 5), in place of a ring-oscillator-based analog phase-locked loop, providing better phase noise performance for the same power.

As used herein and in the claims which follow, the construction “one of A and B” shall mean “A or B.”

It will be understood that the foregoing is only illustrative of the principles of the invention, and that the invention can be practiced by other than the described embodiments, which are presented for purposes of illustration and not of limitation, and the present invention is limited only by the claims which follow.