RF front-end module for picocell and microcell base station transceivers

An RF module adapted for direct surface mounting to the top surface of the front end of the motherboard of a picocell. The module comprises a printed circuit board having a plurality of direct surface mounted electrical components defining respective signal transmit and receive sections for RF signals. The signal transmit section is defined by at least a transmit bandpass filter, a power amplifier, an isolator, a coupler, and a duplexer. The signal receive section is defined by at least the duplexer, a receive low pass filter, a low-noise amplifier, and a receive bandpass filter. A lid covers selected ones of the electrical components except for at least the power amplifier. A plurality of through-holes defined in the printed circuit board below the amplifier allow for the dissipation of heat created by the amplifier. At least one aperture in the board is adapted to accept a screw or the like for securing the module to the motherboard of the picocell.

FIELD OF THE INVENTION

The invention relates to a module and, more particularly, to a radio frequency module adapted for use on the front end of a picocellular or microcellular communication base station.

BACKGROUND OF THE INVENTION

There are currently three types of cellular communication base stations or systems in use today for the transmission and reception of W-CDMA and UMTS based cellular communication signals, i.e., macrocells, microcells and picocells. Macrocells, which today sit atop cellular towers, operate at approximately 1,000 watts. The coverage of macrocells is in miles. Microcells, which are smaller in size than macrocells, are adapted to sit atop telephone poles, for example, and the coverage is in blocks. Microcells operate at approximately 20 watts. A smaller yet microcell requires about 5 watts of power to operate. Picocells are base stations approximately 8″×18″ in size, are adapted for deployment inside buildings such as shopping malls, office buildings or the like, and output about 0.25 watts of power. The coverage of a picocell is about 50 yards.

All of the picocells and microcells in use today include a “motherboard” upon which various electrical components have been individually mounted by the customer. A front-end portion of the motherboard (i.e., the RF transceiver section thereof located roughly between the picocell antenna and mixers thereof) is currently referred to in the art as the “node B local area front end,” i.e., a portion of the picocell or microcell on which all the radio frequency control electrical components such as, for example, the filters, amplifiers, couplers, inductors and the like have been individually mounted and interconnected.

While the configuration and structure of the current motherboards has proven satisfactory for most applications, certain disadvantages associated with the current front-end RF configuration thereof include performance, the costs associated with a customer's placement of individual RF components onto the motherboard during assembly, and the space which such RF components occupy on such motherboards.

There thus remains the need for increased RF component performance and a reduction in both the cost of these motherboards and the space occupied by the RF components on such motherboards. The present invention provides a compact front-end RF component module which addresses and solves the above-identified needs.

SUMMARY OF THE INVENTION

The present invention relates to a module adapted for use on the front end of a picocell or microcell base station including a printed circuit board having a plurality of electrical components mounted directly thereto and adapted to allow for the transmission and reception of cellular signals between the antenna of the picocell or microcell on one end and the respective input and output pads on the motherboard of the picocell or microcell at the other end.

In one embodiment, the module comprises a plurality of electronic components including a signal transmit section or path which includes at least a transmit bandpass filter, a power amplifier, an isolator, a coupler, and a duplexer; and a signal receive section or path which includes at least the duplexer, a receive low pass filter, an optional attenuator pad, a low noise amplifier, and a receive bandpass filter.

The module further comprises a printed circuit board upon which the various electrical components are direct surface mounted. The printed circuit board in turn is adapted for direct surface mounting to the front end of the motherboard of a picocell. A lid is adapted to cover selected ones of the electrical components mounted to the printed circuit board. The duplexer, receive bandpass filter, and the low noise amplifier are all preferably located under the lid, while the power amplifier and the transmit bandpass filter are preferably located outside the lid. A plurality of through-holes or vias located below the amplifier are adapted to define a sink for heat created by the power amplifier.

An aperture in the board is adapted to accept a screw or the like for securing the module to a customer's motherboard.

Other advantages and features of the present invention will be more readily apparent from the following detailed description of the preferred embodiment of the invention, the accompanying drawings, and the appended claims.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

While this invention is susceptible to embodiments in many different forms, this specification and the accompanying FIGURES disclose only one preferred embodiment as an example of the present invention which is adapted for use in a picocell. The invention is not intended, however, to be limited to the embodiment so described and extends, for example, to microcells as well.

In selected ones of the FIGURES, a single block or cell may indicate several individual components and/or circuits that collectively perform a single function. Likewise, a single line may represent several individual signals or energy transmission paths for performing a particular operation.

FIG. 1is a simplified block diagram of the RF (radio frequency) front-end module, generally designated20, constructed in accordance with the present invention and adapted for use in connection with either a picocell or microcell.

As described in more detail below, the module20utilizes distributed filtering with three filters: a duplexer, a receive bandpass filter, and a transmit bandpass filter. The module20also includes a power amplifier, a low-noise amplifier and other necessary RF components. In the transmit path, module20is adapted to deliver 24 dBm WCDMA power at the antenna port, while achieving a typical ACLR (Adjacent Channel Power Leakage Ratio) of −50 dBc with a PAR (peak to average ratio) of 8 dB. Module20is particularly adapted for the 3G Wideband CDMA market, specifically UMTS (Universal Mobile Telecommunications Service).

Module20is adapted to replace all of the RF components that would be typically individually mounted and used in a UMTS Node B local area front end. Module20is compliant with TS25.104 R6 standards and allows customers to select different values for receiver sensitivity, selectivity, and output power. Moreover, module20is RoHS compliant and lead-free. Some of the features of the module20as described in more detail below include a scalable power amplifier capable of delivering 24 dBm at the antenna port; distributed filters offering excellent isolation and harmonic suppression; and a low noise amplifier with a bypass mode to increase receiver linearity.

Referring now in particular toFIG. 1, it is understood that module20is defined by a plurality of RF electrical components and pins defining respective RF signal transmit and receive sections or paths. Initially, and as shown therein, the lower RF transmit section or path of module20includes a first Tx (transmit) signal input pin #4adapted to be coupled to a corresponding Tx (transmit) signal pad on the motherboard (not shown) of a picocell or microcell. Pin #4in turn is coupled to a Tx BPF (transmit bandpass filter)25which, in turn, is coupled to a PA (power amplifier)26which, in turn, is coupled to an isolator28which, as known in the art, is an electrical device adapted to allow the passage of the signal from the power amplifier26with very low loss but with high loss in the opposite direction from the coupler30so as to isolate the coupler30from the amplifier26and provide protection from any variations in loading conditions or what is referred to in the art as “mis-matching”. Thus, for example, where the load VSWR (voltage standing wave ratio) is 10:1, the isolator28would have 18 dB isolation, thus improving the VSWR to 1.2:1 with an insertion loss of 0.6 dB.

The isolator28is in turn coupled to a coupler30which is adapted to allow a portion of the transmit signal passing therethrough to be split and passed to a power detect pin #13as described in more detail below.

Coupler30in turn is coupled to a duplexer34, of the type made and sold by CTS Corporation of Elkhart, Ind. Duplexer34is adapted to send the transmit signal, generally designated by the arrows33, which has been passed successively in a counter-clockwise direction from Tx input pin #4through Tx bandpass filter25, power amplifier26, isolator28, coupler30, and duplexer34, through the output of duplexer34and antenna pin #12.

VPA (power amplifier supply voltage) pin #2and PA bias pin #3are both coupled to power amplifier26. Antenna pin #12as described below in more detail extends between the top and bottom surfaces of the module20and is adapted to be direct surface mounted into coupling relationship with the antenna pad (not shown) of a picocell or microcell so as to allow for the transmission of the signals which have passed through the RF signal transmission section of module20.

The top receive section or path of the signals being received (i.e., Rx signals) from the picocell or microcell antenna (not shown) and transmitted through the module20will now be described also with reference toFIG. 1which shows the Rx signal being transmitted and passed in a left to right, clockwise direction from the picocell or microcell antenna (not shown) through the module antenna pin #12and then initially through duplexer34.

Duplexer34is, of course, adapted and structured as known in the art to allow the passage of the Rx signal clockwise in the direction of the Rx LPF (low pass) filter36rather than the coupler30. From the low pass filter36, the Rx signal, generally designated by the arrows41, may optionally be passed through a 3 dB attenuator pad37(comprised of resistors R5, R6, and R7as described in more detail below), and then through a LNA (low noise amplifier)39. Low noise amplifier39is coupled to VLNA (LNA supply voltage) pin #9and LNA gain select pin #10.

From the low-noise amplifier39, the Rx signal then travels through an Rx BPF (receive bandpass ceramic filter)40of the type made and sold by CTS Corporation of Elkhart, Ind. From the Rx bandpass filter40, Rx signal41passes into Rx output signal pin #6which, in turn, is adapted to extend between the top and bottom surfaces of the module20as described in more detail below for direct surface coupling to the corresponding Rx output signal pad (not shown) on the motherboard of the picocell or microcell.

In accordance with the present invention, attenuator pad37is optional and may be used to de-sensitize the receive chain and make the receiver more linear, i.e., to decompress the receive chain when the Node B is deployed in an environment, for example, where other devices are operated in close proximity to the picocell. Where more sensitivity is desired at the expense of linearity, pad37may have a different value. Optionally, of course, the pad37can be omitted altogether. All 3 GPP specifications are met even with the 3 dB-pad37in place.

FIGS. 2-7depict one embodiment of a module20adapted and structured to be direct surface mounted to the front end of a picocell.

By way of background, it is understood that module20of the present invention as depicted inFIGS. 5 and 7measures about 25.0 mm in width, 30.5 mm in length, and 6.75 mm max. in height (with the lid secured thereon), and is adapted to be mounted to the motherboard of a picocell measuring about 8 inches by 18 inches which, as described above, is adapted for use as a cellular signal transfer base station inside a building such as a shopping mall or office complex. The typical power output of a picocell is approximately 250 mW. The frequency of the Rx signal received by a picocell is between about 1920-1980 MHz, while the frequency of the Tx signal is between about 2110-2170 MHz. The power amplifier supply voltage is between about 4-9 volts and typically about 8 volts, while the low noise amplifier supply voltage is between about 2.5-5.5 volts and typically about 5.0 volts.

In accordance with the present invention, module20initially comprises a printed circuit board or substrate22which, in the embodiment shown, is preferably made of four layers of GETEK® or the like dielectric material and is about 1 mm (i.e., 0.040 inches) in thickness. Predetermined regions of the substrate22are covered with copper or the like material and solder mask material, both of which have been applied thereto and/or selectively removed therefrom as is known in the art to create the particular copper, dielectric, and solder mask regions shown inFIGS. 5,7and9. The metallization system is preferably ENIG, electroless nickel/immersion gold over copper.

A lid45, which is adapted to cover about two-thirds of the area of the printed circuit board22as described in more detail below, is preferably brass with a Cu/Ni/Sn (copper/nickel/tin) plated material for ROHS compliance purposes. The area of the top of the board22located above copper line or strip47(FIG. 2) on board22defines the portion of board22adapted to be covered by the lid45as described in more detail below. The lid45is adapted to act both as a dust cover and a Faraday shield.

Generally rectangularly-shaped substrate22has a top or upper surface23(FIG. 5), a bottom or lower surface27(FIG. 7) and an outer peripheral circumferential edge defining upper and lower faces or edges42and44and side faces or edges46and48(FIGS. 5 and 7). Although not described in any detail, it is understood that, in a preferred embodiment, substrate22will be comprised of a plurality of stacked laminate layers of suitable dielectric material sandwiched between respective layers of conductive material as is known in the art such as, for example, a bottom RF ground plane layer, an RF intermediate signal layer, a top RF ground layer, and a topmost DC layer plus ground layer.

Castellations35and37are defined and located about the outer peripheral edge of board22. Castellations35define the various ground and DC input/output pins of the module20, while slots or castellations37are adapted to receive the tabs of the lid45as described in more detail below.

Castellations35are defined by metallized semicircular grooves which have been carved out of the respective edges42,44,46and48and extend between the respective top and bottom surfaces23and27of the substrate22. In the embodiment shown, the castellations35are defined by plated through-holes which have been cut in half during manufacturing of the substrates from an array. Castellations35extend along the length of the respective edges of substrate22in spaced-apart and parallel relationship. In the embodiment as shown inFIGS. 5 and 7, the top edge42defines four spaced-apart castellations35, the lower edge44defines three spaced-apart castellations35, and the side edges46and48each define one castellation35.

Each of the side edges46and48defines a pair of spaced-apart metallized castellations37which are diametrically opposed from one another. Each castellation37is defined by an extended or elongated oval-shaped groove which has been carved out of each of the respective substrate side edges46and48respectively. All of the castellations are located above copper line or strip47.

The outer surface of each of the respective castellations35and37is coated as by electroplating or the like, with a layer of copper or the like conductive material which is initially applied to all of the surfaces of the substrate22during the manufacturing of the substrate22as is known in the art and then removed from selected portions of the surfaces to define the copper coated castellations35and37. Castellations35and37and, more specifically, the copper thereon creates an electrical path between top surface23and bottom surface27of substrate22. Castellations37can be connected to ground. The copper extends around both the top and bottom edges of each of the castellations35so as to define a generally arcuate strip or pad of copper or the like conductive material35aon the top surface23of substrate22and surrounding the top edge of each of the respective castellations35(FIG. 5); and a plurality of generally rectangularly-shaped strips35bextending inwardly from the bottom edge of each of the castellations35so as to define a plurality of pads formed on the bottom surface27of substrate22(FIG. 7) which allow the module20to be directly surface mounted by reflow soldering or the like, to corresponding pads located on the surface of the motherboard of the picocell (not shown).

In accordance with the present invention, the pads35aand35bof castellations35defining pin #s2,3,9, and10as described in more detail below are not ground pins and thus are surrounded by regions35c(FIG. 5) and 35d(FIG. 7) respectively of the top and bottom surfaces of the substrate22which are not covered with copper or the like material, i.e., regions of substrate dielectric material.

Each of the castellations37additionally defines strips or pads37a(FIG. 5) and 37b(FIG. 7) of copper or the like conductive material that are formed on the top and bottom surfaces23and27respectively of substrate22and surround the top and bottom peripheral edges respectively of each of the respective castellations37.

Each of the top castellations37additionally defines a corner strip37c(FIG. 5) of copper or the like conductive material extending from the respective copper strips37asurrounding respective upper castellations37and extending around the top corners of the board22, while the strips37aof the respective lower castellations37are connected to the ends of elongate copper strip or line47extending therebetween in a relationship spaced from and parallel to upper and lower board edges42and44respectively. Corner strip37con the left side of substrate22is spaced from the strip35aof castellation35defining the LNA gain select pin #10.

A strip37e(FIG. 5) of copper or the like material extends between and electrically connects the castellation35extending along the left side substrate edge48to the upper castellation37also extending along the left side substrate edge48.

A strip37f(FIG. 5) of copper or the like material extends along the right side substrate edge46between, and in electrical connection with, the castellation35defining ground pin #5and the lower castellation37. Still further, it is understood that an elongate strip37g(FIG. 5) of copper or the like conductive material extends along the top substrate edge42between the right side corner strip37cat one end and the castellation35defining the VLNA pin #9as described in more detail below at the other end. Strip37gis electrically connected to the corner strip37c, the castellation37on the right side substrate edge46and the two castellations35extending along the top peripheral substrate edge42and defining ground pin #s7and8(FIG. 7) as described in more detail below.

The left side end of strip37g, however, is spaced from the castellation35defining VLNA pin #9and is thus not electrically connected thereto. Another short strip37h(FIG. 5) of copper or the like material extends along the top peripheral substrate edge42between and in spaced, non-contacting, relationship with the castellation35defining VLNA pin #9and the castellation35defining LNA gain select pin #10also extending along the top peripheral substrate edge42.

Each of the right and left side edges46and48additionally define and include a pair of spaced-apart conductive vias38which define the respective RF component input/output pin #s4,6,12and13of the module20as also described in more detail below. Vias38extend through the substrate22between the top and bottom surfaces23and27thereof and, as known in the art, define an interior cylindrical surface which has been plated with copper or the like conductive material. In accordance with the present invention, the use of vias38which are spaced from the respective substrate side edges46and48instead of castellations35defined in respective substrate edges46and48insures a constant 50-ohm characteristic impedance. The top openings of each of the vias38are surrounded by regions38a(FIG. 5) of dielectric substrate material, i.e., areas of the substrate22from which the conductive copper material has been removed as by an etching, lasing or the like process known in the art.

The lower openings of each of the vias38on the lower surface27of substrate22are surrounded by generally rectangularly-shaped pads38b(FIG. 7) of copper or the like conductive material. The pads38bin turn are surrounded by regions38cof the lower surface27of substrate22from which the copper material has been removed as known in the art during the manufacture of substrate22.

Thus, and as shown inFIG. 5, the castellations35, castellations37and vias38are all positioned along each of the respective substrate side edges46and48in a spaced-apart relationship wherein one each of the castellations35and vias38is located between the pair of castellations37all above the copper strip47and wherein the lower via38is located below the copper strip47. The lower vias38on respective side edges46and48are diametrically opposed.

As shown inFIGS. 2 and 5, power amplifier26is preferably located in an area of the printed circuit board22below the copper strip47, i.e., an area not intended to be covered by the lid45, so as to allow for the dissipation of heat created by the amplifier26and also to reduce the transfer of heat created by the amplifier26to any of the electrical components located under the lid45.

As also shown inFIGS. 2,5and9, duplexer34, Rx low pass filter36, Rx bandpass filter40, and Rx low noise amplifier39are all mounted on an area of the top surface of the board22above the elongate copper strip47and thus intended to be covered by the lid45.

More specifically, and as shown inFIGS. 5 and 9, Rx bandpass filter40is located in the upper right hand corner of the board22and extends generally longitudinally in a relationship adjacent and parallel to the top longitudinal edge42of board22. Rx O/P pin #6is located adjacent the side board edge46generally opposite the right end face of filter40. Ground pin #s7and8are located along the top edge42in an orientation generally opposite the longitudinal top edge of filter40. Rx bandpass filter40is adapted to work in conjunction with the duplexer34to provide in excess of 65 dB “transmit to receive” isolation. The other function of the filter40is to provide the “blocking” needed to be compliant with the TS25.104R6 standard blocking requirement that leads to a front end attenuation of 15 dB to 20 dB at 1.9 GHz and 2 GHz.

Tx bandpass SAW (surface acoustic wave) filter25is located and seated in the lower right-hand corner of the module20. More specifically, SAW filter25extends generally longitudinally in a relationship parallel to and below and spaced from the copper strip47on board22and in a relationship spaced and adjacent to board edges44and46. Tx input pin #4is located directly above and spaced from the filter25between the filter25and the strip47. The Tx bandpass filter25, in conjunction with the duplexer34, is adapted to attenuate transmit spurious and prevent Rx de-sensitization.

GND (ground) pin #1, VPA pin #2and PA bias pin #3(all defined by respective castellations35) are respectively located along the lower longitudinal edge44of the board22in spaced-apart relationship from left to right.

Tx I/P (transmit input) pin #4, GND (ground) pin #5, and Rx O/P (receive output) pin #6are respectively located along the right side elongate edge46of board22in a spaced-apart relationship from bottom to top. Tx I/P pin #4is located below copper strip47. The Rx O/P pin #6and Tx I/P pin #4are located above copper strip47and are defined by the respective vias38described above, while ground pin #5is defined by one of the castellations35. A castellation37is defined in edge46between strip47and castellation35defining pin #5. Another castellation37is defined in edge46between the via38defining the pin #6and the top substrate edge42.

GND (ground), GND (ground), VLNA (voltage low noise amplifier) and LNA gain select pin #s7,8,9and10, respectively (FIGS. 5 and 7) are located and extend along the top longitudinal edge42of board22in a spaced-apart relationship from right to left. Each of the pin #s7,8,9, and10is defined by a respective castellation35as described above.

GND (ground), antenna, and power detect pins #s11,12, and13respectively extend along the left side edge48of the printed circuit board22from top to bottom and in spaced-apart relationship as viewed from the perspective ofFIGS. 5 and 9. As described above, pin #s12and13are defined by respective vias38, while pin #11is defined by a castellation35. Pin #13is located below the copper strip47. Pin #s12and13are located above the copper strip47.

Duplexer34, which is preferably of a ceramic monoblock construction providing an insertion loss of about 1.3 dB on the receive side and 1.5 dB on the transmit side, is located and positioned on the top surface of the board22in a relationship generally adjacent and parallel to the left side edge48of board22and above and parallel to the copper strip47. RF antenna pin #12is located adjacent board edge48in a relationship and position generally opposite the duplexer34.

Rx low noise amplifer39is located generally in the upper left hand corner of the board22to the left of, and spaced from, the Rx bandpass filter40and above and spaced from the duplexer34in a relationship adjacent to and spaced from the left side edge48of board22. VLNA pin #9and LNA gain select pin #10are defined and located along the board edge42in a relationship and position generally above the Rx low noise amplifer39. The Rx low noise amplifer39has a noise figure of 1.3 dB and a gain of 14 dB typical, or in bypass mode; 4.3 dB NF and −3 dB gain typical. Amplifier39is linear and designed to work within the distributed duplexer architecture.

By way of background, it is known that a local area Node B needs to have a receive sensitivity of at least −107 dBm (12.2 Kbps) in order to meet TS25.104 R6 standard. This equates to a system noise figure of around 19 dB (actual noise figure requirements will vary according to other system impairments). A local area Node B also needs to have a higher input linearity compared to a wide area Node B. In order to meet the TS25.104 R6 standard, a system IIP3 needs to be approximately −10 dBm (a few dBs margin is added for variation in the Rx chain). However, a system IIP3 closer to 0 dB is more likely to be a typical target as deployed environments for local area Node Bs can be very harsh from an interference perspective.

Referring back now toFIG. 5, low pass Rx filter36is located on the top surface of the board22generally between and below the Rx low noise amplifer39and above the duplexer34, and slightly to the right of the right side edge of the amplifier39, in a relationship spaced from and parallel to the amplifier39and duplexer34respectively. Ground pin #11is defined in edge48generally opposite the filter36. Filter36is adapted to reduce harmonic responses of the duplexer34. This ensures that any spurious up to 12.75 GHz are attenuated to −30 dB or better.

The use of filters25,34, and36in combination define a distributed filtering configuration which provides the necessary “blocking” function. By way of background, it is known that one of the most challenging aspects of the UMTS standard, with respect to receiver design, is “blocking”, i.e., preventing the Tx signal from interfering with the Rx signal. In a typical radio system design, the duplexer protects the radio from “blocking” by providing out-of-band attenuation of 30 dB or better with a minimum attenuation of 20 dB from 0 Hz to 1.9 GHz, and 2.0 GHz to 12.75 GHz. This, of course, is difficult for a 60 MHz wide filter having an insertion loss typically less than 1 dB. Most duplexers that can provide this performance have eight poles and can be as large as 11 inches by 9 inches by 3 inches (28 cm×23 cm×7.6 cm). Module20, of course, is not large enough to accommodate such a large duplexer and thus “blocking” and the required close in rejection is accomplished through the use of the three distributed filters25,34and36described above.

In the Tx path, coupler30, isolator28, Tx power amplifier26, and Tx bandpass SAW filter25are all located and seated on the top surface of board22of module20in an area thereof below copper strip47which is not intended to be covered by the lid45.

Isolator28and coupler30are located adjacent and spaced from the left side board edge48, and generally in the lower left-hand corner of the board22, in a relationship wherein the coupler30is located above the isolator28in spaced-apart and parallel relationship thereto. Power amplifier26is located between the coupler30and isolator28on one side and the right side board edge46on the other side. Tx bandpass SAW filter25is located between the power amplifier26and the right side board edge46. Coupler30preferably has a coupling factor of 13.5 dB+/−0.3 dB. Isolator28, which affords protection from variations in loading conditions or mismatching, preferably has about 15 dB of isolation. Power amplifier26preferably is a highly efficient GaAs HBT device with scalable power and capable of delivering the full TS25.104 local area requirements. Power amplifier26preferably dissipates about 6.4 W while delivering about 24 dBm at the antenna port. By changing amplifier bias and supply voltage, reduced output power can be achieved.

The via38defining power detect pin #13is located adjacent the left side edge48of board22in an orientation generally opposite and to the left side of coupler30, while ground pin #1is located along the lower edge44of board22in an orientation generally to the right of and below the isolator28. PA bias pin #3and VPA pin #2are also located along the lower edge44of board22in an orientation generally opposite and below the power amplifier26.

Referring now toFIGS. 6A and 6B, lid45includes a top wall or roof46, a pair of upper and lower walls49aand49b, respectively, and a pair of sidewalls51aand51b, respectively, depending generally perpendicularly downwardly therefrom. The walls49a,49b,51aand51bin turn define lower longitudinal edges53. The lower longitudinal edge53of each of the sidewalls51aand51bin turn defines at least two spaced-apart tabs50projecting downwardly therefrom and adapted to be fitted into the respective through-slots or castellations37for locating and securing the lid45to the board22in a grounded relationship with the board22wherein the lower longitudinal edge53of the respective lid walls49a,49b,51aand51bare seated over copper strip47, the copper pads35aof castellations35, the copper pads37aof castellations37, and the copper strips37c,37e,37f,37hand37gthus providing a grounded lid45.

The lower longitudinal edges53of the respective walls additionally define a plurality of discrete notches54. Specifically, notches54aand54bare defined in the respective sidewalls51aand51bbetween the tabs50. Two additional notches54cand54dare defined in the top wall49aadjacent the sidewall51a, while one additional notch54eis defined in the lower wall49b.

FIG. 8is a schematic diagram of the electrical circuit of the front-end module20of the present invention. The reference and descriptions of each of the electrical components shown therein are identified in Table A below and shown inFIGS. 5 and 9:

The circuit for the Rx (receive) path or portion of the module20will now be described with reference toFIG. 8.

Initially, and although not shown, it is understood that an Rx signal, received through the antenna and antenna pad of the motherboard of the picocell or microcell on which the module20is seated, is initially passed through the lower pad38bof antenna pin #12of module20up through the substrate22and then initially through circuit line118and into the input terminal #3of duplexer34which is located on the top surface of the module20. Input terminal #4of duplexer34is connected to ground through a circuit line117. The Rx signal is adapted to pass through the duplexer34(F1) and its output terminal #1and then through circuit line58and into the input terminal #2of Rx low pass filter36(F3). A second circuit line56at the input end or ground terminal #3of Rx low pass filter36connects the filter36to ground.

Although not described in any detail, it is understood that the term “circuit line” and/or “ground” as used herein will, in certain instances, refer to an appropriate pad or the like circuit element on the surface of the board22.

Rx low pass filter36includes two output circuit lines60and61extending from output terminals #4and #1thereof respectively. The output line60connects the output terminal #4of filter36to ground pin #11. Circuit line60is also connected to ground via circuit line62which is connected to circuit line60at node N1. Node N1is located on circuit line60between the output terminal #4of Rx low pass filter36and ground pin #11. The output line61extends between the output terminal #1of filter36and the input terminal #3of amplifier39(U2).

From the output terminal #1of filter36, the Rx signal passes through circuit line61and through the resistors R5, R6, and R8comprising the optional attenuator pad37defined inFIG. 1. R6extends along circuit line61. R5extends between a node N1aand ground on a circuit line61alocated above resistor R6, while resistor R8extends on a circuit line61bextending between node N1band ground below resistor R6.

A capacitor C14is located on line61between R6and input terminal #3of low noise amplifier39.

Low noise amplifier39has additional terminals #1, #2, #4, #5and #6. Input terminal #2of amplifier39is connected to ground pin #8via node N2on a circuit line61cextending between input terminal #2and ground pin #8. Input terminal #1of amplifier39is connected to VLNA pin #9via a circuit line63. Capacitor C2is connected between a node N3on circuit line63and ground. Capacitor C3, which is connected in parallel with capacitor C2, extends between node N4on circuit line63and ground. Capacitor C3is located between capacitor C2and VLNA pin #9. A resistor R2is connected on circuit line63between node N4and VLNA pin #9. Node N3is located on circuit line63between the input terminal #1of low noise amplifier39and node N4. Node N4is located on circuit line63between node N3and resistor R2. Resistor R2is located on circuit line63between nodes N4and a node N5. Node N5is located on circuit line63between resistor R2and VLNA pin #9.

Resistors R5, R6, and R8are all located on board22above duplexer34. L7, which forms part of the matching network for the low-noise amplifier39, is located on board22above resistor R8. Resistors C2, C3, and C14are all located on board22above R6and to the left of amplifier39. Resistor R2is located on board22between the top substrate edge42and amplifier39and to the right of resistor C3(FIG. 9).

Referring back toFIG. 8, terminal #4(i.e., the Rx signal output terminal) of low noise amplifier39is connected to the input terminal #1of Rx bandpass filter40via a circuit line70. A capacitor C4is connected between a node N6on circuit line70and ground. An inductor L4and capacitor C16are connected in series between a node N7on circuit line70and ground via a circuit line72. An inductor L1and capacitor C13are connected in series on circuit line70between the node N7and the input terminal #1of Rx bandpass filter40. Additionally, a resistor R4is coupled between a node N9on circuit line72and node N5on circuit line63via a circuit line74. Node N6is located on circuit line70between the output terminal #4of low noise amplifier39and node N7. Inductor L1is located on circuit line70between nodes N6and N7. Node N9is located on circuit line72between inductor L4and capacitor C16. Node N5is located on circuit line63between resistor R2and VLNA pin #9.

A capacitor C15is connected between a node N10on circuit line74and ground. Node N10is located on circuit line74between node N9and resistor R4.

Output terminal #5of low noise amplifier39is connected to ground via a circuit line76.

Output terminal #6of low noise amplifier39is connected to gain select pin #10via a circuit line84. A resistor R1is connected on circuit line84between the output terminal #6of the low noise amplifier39and the gain select pin #10. A capacitor C1is connected on a circuit line86between a node N11on circuit line84and ground. Node N11is located on the circuit line86between the resistor R1and gain select pin #10.

As shown inFIG. 9, capacitor C1and resistor R1are located on board22between substrate edge42and amplifier39. Resistor R4, capacitors C15and C16, inductor L4, and capacitor C4, are all located on board22between the right edge of amplifier39and the left edge of duplexer40. Inductor L1and capacitor C13are both located on the board22below the lower left edge corner of duplexer40.

Referring back toFIG. 8, the input terminal #s3,5,7,9,11, and13of filter40(F5) are all connected to ground via a common circuit line. The Rx signal passes through the output terminal #2of Rx bandpass filter40into the Rx output pin #6via a circuit line78. The output terminal #s4,6,8,10,12, and14of filter40are all connected to ground pin #7via a common circuit line81.

The RF transmit signal, on the other hand, is inputted at Tx I/P pin (transmit input) #4and passes immediately through a circuit line85and into the input terminal #1of Tx bandpass SAW filter25(F4). The output of Tx bandpass SAW filter25passes through output terminal #3of filter25and then through a matching network of capacitors C10, C11, C17and C18and then into the input terminal #3of power amplifier26(U1) via a circuit line86extending between the output terminal #3of the Tx bandpass SAW filter25and the input terminal #3of power amplifier26. C18is connected between the output terminal #3of bandpass SAW filter25and a node N12on circuit line86. C17is connected on circuit line86between a node N12aand input terminal #3of Tx amplifier26. Node N12is located between node N12aand output terminal #3of Tx bandpass SAW filter25. Capacitor C10is located on a circuit line88extending between node N12aon circuit line86and ground. Capacitor C11is located on a circuit line89extending between node N12on circuit line86and ground.

A circuit line90extends between a ground output terminal #4of bandpass SAW filter25and ground. A circuit line91extends between input terminal #2of filter25and ground. Ground pin #5connects to circuit line91at node N12b.

Power amplifier26includes additional respective input and output terminals #1, #2, #4, #5, #6, #7and #8. A circuit line92connects the input power amplifier26to VPA bias pin #3. Resistors R3, R10, R11, and R12are all connected in parallel on circuit line92between input terminal #2of power amplifier26and PA bias pin #3. Resistor R3is connected on circuit line92between terminal #2of Tx power amplifier26and PA bias pin #3. Capacitor C6is connected between a node N14on circuit line92and ground. A capacitor C7, in parallel with capacitor C6, is connected between a node N15on circuit line92and ground. Nodes N14and N15are located on circuit line92between resistor series R3, R10, R11, and R12and PA bias pin #3.

The RF output of the power amplifier26passes through terminals #5, #6, #7, and #8thereof through another network of capacitors C8, C21, C12, C9, C22, and C24along a circuit line96and into the input terminal #5of Tx isolator28. Circuit line96extends between output terminal #6of power amplifier26and the input terminal #5of isolator28(F7). Capacitor C21extends on circuit line96between nodes N16and N17on circuit line96. Capacitor C22extends on circuit line96between node N17aand input terminal #5of isolator28. Capacitor C8connects to circuit line96between node N16and ground.

Capacitor C12, which is in parallel relationship with capacitor C8, connects to circuit line96between node N17and ground. Node N17is located on circuit line96between capacitors C21and C22. Node N16is located on circuit line96between capacitor C21and output terminal #6of power amplifier26. Capacitor C9, which is in parallel relationship with capacitor C12, connects to circuit line96at node N17awhich is between node N17and input terminal #5of isolator28. Capacitor C24, which is in parallel relationship with capacitor C9, connects to circuit line96at node N17bwhich is located between node N17aand input terminal #5of Tx isolator28.

A circuit line98extends between the node N16on circuit line96and VPA pin #2. A circuit line100extends between input terminal #4of power amplifier26and node N18on circuit line98. A circuit line101extends between the input terminal #1of power amplifier26and ground. A capacitor C23is located on circuit line101between the input terminal #1and ground.

A capacitor C20on circuit line98extends between a node N20on circuit line98and ground. A capacitor C19, which is in a parallel relationship with capacitor C20, is connected to circuit line98between a node N19and ground. Nodes N19and N20are located on circuit line98between node N18and VPA pin #2. A capacitor C5is located on a circuit line101aextending between a node N21on circuit line98and ground. An inductor L2extends on a circuit line99extending between a node N21aon circuit line101and a node N21bon circuit line101a. Node N21bis located between capacitor C5and node N21. Node N19is located on circuit line98between nodes N18and N20. Node N18on circuit line98is located between node N16and node N21.

Tx isolator28(F7) includes respective input and output terminal #s1through6. Input terminal #6on the input side of the Tx isolator28is connected to ground pin #1via a circuit line104. A circuit line106extends between input terminal #4of Tx isolator28and ground. A circuit line107extends between a node N25on circuit line104and ground. Terminal #3on the output side of isolator28is connected to ground via a circuit line108. Ground terminal #1, also on the output side of isolator28, is connected to ground via a circuit line110. The RF signal output of the isolator28passes through the output terminal #2thereof and then into a circuit line112extending into a node N25aon a circuit line112awhich extends into the input terminal #3of Tx coupler30(F2).

An inductor L5extends on circuit line112abetween a node N25aand ground. Node N25ais located on circuit line112abetween inductor L5and input terminal #3of coupler30.

A portion of the signal passing through Tx coupler30is diverted and outputted through output terminal #4of Tx coupler30and then into power detect pin #13via a circuit line114extending between the output terminal #4of Tx coupler30and power detect pin #13. A circuit line118extends between the output terminal #1of the Tx coupler30and ground. A resistor R7is connected along circuit line118between the output terminal #1of Tx coupler30and ground.

The RF output of Tx coupler30passes through coupler output terminal #2and into the input terminal #2of duplexer34via a circuit line116extending therebetween. An inductor L6extends on a circuit line116abetween a node N25bon circuit line116and ground.

As shown inFIG. 9, resistors R11, R10, R12, R3; capacitors C7, C6, C2; inductor L2; and capacitors C5and C20are all located on the uncovered portion of board22below copper strip47and all extend in a generally co-linear relationship along the lower board edge44from the right side board edge46. More specifically, said components are located generally between the lower board edge44on one side and the Tx bandpass filter25and amplifier26on the other side. Capacitors C10, C11, C17, and C18are also all located on the uncovered portion of board22below copper strip47. Specifically, said components are located on the board22in the space between amplifier26and Tx bandpass filter25.

Capacitors C8, C9, C12, C22, C19, and C24; and inductor L3are also located on an uncovered portion of the board22and, more specifically, the space therein between the isolator28on one side and the amplifier26on the other side.

RF inductors L5and L6and resistor R7are still further also all located on the uncovered portion of board22. More specifically, inductor L5is located in the space between the left side board edge48and isolator28; resistor R7is seated to the right of coupler30; and L6is seated to the right of resistor R7.

FIG. 9additionally depicts the various component connection pads, pins, and printed circuit lines which are all composed of strips and/or regions of copper or the like conductive material which has been appropriately defined and deposited on the top and bottom surfaces23and27of the printed circuit substrate board22as is known in the art.

Although not described herein in any detail, it is understood that the various copper regions and strips identified and described above have been defined and formed thereof as a result of either the subtraction or removal of selected portions of the copper material from the upper and lower surfaces23and27respectively of the substrate22during the substrate manufacturing process and/or as a result of the application of layers or strips of solder mask material over pre-selected portions of the copper layer as is also known in the art.

As shown inFIG. 9, it is understood that selected regions on the board22outside of the bounded dashed areas comprise regions of substrate dielectric material; that other selected regions on the board22bounded by the dashed lines shown therein comprise regions of the board wherein the copper material has been covered with solder mask material; and further that still other selected ones of the regions bounded by solid lines inFIG. 9comprise regions of exposed copper material.

Selected ones of the copper connection pads, strips and regions are used to direct solder attach the terminals of the various electronic components of the module20of the present invention directly to the top surface23of the board22and also to direct solder attach the various terminals and pads on the lower surface27of the board22to the terminals and pads on the top surface of the motherboard of a picocell or microcell. Stated another way, selected ones of the exposed copper pads, strips and regions is adapted to have solder applied thereto as is also known in the art.

More particularly, and referring toFIG. 9, printed circuit board22has a plurality of differently sized and shaped connection copper pads130located below the Rx bandpass filter40, Tx bandpass filter25, low noise amplifier39, low pass filter36, duplexer34, Tx coupler30, isolator28and power amplifier26so as to allow the same to be direct surface solder mounted to the board22. Differently sized and shaped copper connection pads132are also appropriately positioned below each of the resistors, capacitors and inductors comprising the circuit of module20.

Board22additionally defines a first plurality of ground through-holes134which, as known in the art, extend between the top and bottom surfaces23and27respectively of the board22and are adapted to make a grounding electrical connection between the top and bottom surfaces and any intermediate metallized layers comprising the board22. The interior surface of each of the through-holes or vias134is coated with a layer of copper or the like conductive material by electroplating or the like process as known in the art. The through-holes134are dispersed throughout the surface of the substrate22.

As also shown inFIG. 9, a second plurality of through-holes or vias136are defined and formed on the board22beneath the region where the power amplifier26is seated on the board22so as to define a heat sink for the heat created by power amplifier26. Through-holes134are double-plated with copper or the like material for added thermal conductivity and likewise extend through the board22.

Referring back toFIG. 7, it is understood that the lower surface27of substrate22additionally defines a plurality of generally rectangularly-shaped copper pads138. The copper pads138are separated by strips140of solder mask material.

Board22still further defines at least one aperture150defining a through-way for a screw or the like (not shown) adapted to allow the module20to be secured to the heat sink and a customer's motherboard to allow better thermal contact between the motherboard and module20. In the embodiment ofFIG. 9, aperture150is located below copper strip47and to the left of power amplifier26.

The process for assembling a module20involves the following steps. After the substrate/board22has been fabricated, i.e., once all of the appropriate copper castellations, copper strips, copper vias, copper pads, and copper through-holes have been formed thereon, and as described above, Ag/Sn (silver/tin) solder is screen printed onto a 2.6″ by 4.6″ printed circuit board array and, more particularly, onto the surface of each of the appropriate solder pads and strips defined on the array following the application of predetermined layers and strips of solder mask material as known in the art. Solder is applied to the surface of all of the designated copper strips, pads and regions and all of the electrical components including all of the filters defining the module20are then appropriately placed and located on the array.

The lid45is then placed over the appropriate portion of the board22as described above into a soldered coupled relationship wherein the tabs50thereof are fitted into the appropriate castellations/slots37defined in the respective side edges46and48of board22thereby appropriately locating and securing the lid45to the board22in a relationship where the lower edge of the lower wall49bof lid45is seated over the copper strip defining line47, the lower edge of the upper wall49aextends along and adjacent to top board edge42and over the respective copper strips and pads35a,37c,37g, and37has described above defined thereon, and the lower edges of the respective sidewalls51aand51bof lid45are seated over the respective copper strips and pads35a,37a,37cand37eextending along respective opposed board edges46and48. This placement of the lid45into contact with pre-selected areas of the copper strips and pads on the substrate/board22, of course, defines a module20where the lid45is electrically grounded.

It is further understood that the notches54defined in the lower peripheral edge of the walls49and51of lid45are adapted to provide a continuous grounding surface around the lid45, while at the same time providing a gap between the lid45and those selected portions of the board22comprising exposed dielectric material or solder mask material such as, for example, the notches54aand54boverlying the respective vias38defining the antenna pin #12(FIG. 4) and the Rx output pin #6(FIG. 2), the notches54cand54doverlying the regions surrounding pins #8and #9(FIG. 3), and the notch54ewhich overlies selected circuit lines (FIG. 2), i.e., regions not intended to be grounded. The module20is then reflow soldered at a maximum temperature of 260° C. so as to couple all of the components and lid45to the board.

Moreover, and although not shown in any of the FIGURES or described herein in great detail, it is understood that a block of RF signal-absorbing foam material of the type sold by R & F Products of San Marcos, Calif. and measuring about 0.43″L×0.20 W×0.13″H could be seated and suitably secured to the top surface23of the board22in the open area160thereof (FIG. 7) bounded by duplexer34, Rx bandpass filter40, Tx bandpass filter25, and copper strip47for absorbing predetermined levels of the Rx or Tx frequencies passing through the respective transmit and receive sections of the module20, thus minimizing what is known in the art as “cross-talk”.

Finally, the array is then diced up as is known in the art and the individual modules20are then final tested and subsequently “taped and reeled” and readied for shipment.

While the invention has been taught with specific reference to an embodiment of the module adapted for use on the front end of a picocell, it is understood that someone skilled in the art will recognize that changes can be made in form and detail without departing from the spirit and the scope of the invention as defined in the appended claims. The described embodiment is to be considered in all respects only as illustrative and not restrictive.