TECHNIQUES FOR MEMORY ERROR CORRECTION

Methods, systems, and devices for techniques for memory error correction are described. A memory system may support a refresh with error correction code (ECC) operation. The refresh with ECC operation may be indicated in a command from a host device to a memory device, or the memory device may support executing the refresh with ECC operation autonomously, for example as part of a self-refresh operation. The refresh with ECC operation may cause the memory system to, as part of a refresh operation for a row of a memory array, perform an error correction operation on at least a portion of the row. The error correction operation may correct bit errors in a set of data before an additional bit of the set of data is corrupted. The address of the portion of the row may be determined using one or more counters associated with an ECC patrol block.

FIELD OF TECHNOLOGY

The following relates generally to one or more systems for memory and more specifically to techniques for memory error correction.

BACKGROUND

Various types of memory devices and memory cells exist, including magnetic hard disks, random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), static RAM (SRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase change memory (PCM), self-selecting memory, chalcogenide memory technologies, and others. Memory cells may be volatile or non-volatile. Non-volatile memory, e.g., FeRAM, may maintain their stored logic state for extended periods of time even in the absence of an external power source. Volatile memory devices, e.g., DRAM, may lose their stored state if disconnected from an external power source.

DETAILED DESCRIPTION

Data stored in a memory device (e.g., a dynamic random access memory (DRAM) device) may become corrupted over time, for example due to electromagnetic interference, high energy particles (e.g., cosmic rays), memory cell wear and aging, or other error mechanisms. Thus, stored data may in some cases come to include one or more errors, and data stored for a relatively long time may be more likely to contain multiple errors compared to data stored for a relatively short time. In some cases, a single-bit error (SBE) may be correctable, for example using a single-error correction (SEC) error correction code (ECC). However, SBEs that are not corrected may eventually become uncorrectable double-bit errors (DBEs) or other types of multi-bit errors, as after one bit within a set of data becomes corrupted, one or more additional bits within the set of data may subsequently also become corrupted. The disclosure herein may support correcting an SBE before it becomes a DBE or other type of multi-bit error. Further, though examples may be explained herein in the context of correcting SBEs before additional errors occur within a set of data subject to an error detection and correction procedure, it is to be understood that the teachings herein may further be extended to apply to detecting and correcting errors including any quantity of bits (e.g., DBEs) before they become errors including one or more additional bits.

A memory device may include an ECC block that stores parity bits for detecting errors, for example as part of an error correction operation. In some cases, the ECC block may correct errors during access operations, such as read or write operations. That is, the ECC block may perform error correction on data stored in a memory cell or group of memory cells as part of reading the data from or writing the data to the memory cell or group of memory cells. However, some portions of the memory device may not be accessed as often as other portions (i.e., some portions may be “cold”, compared to more frequently accessed “hot” portions), and so SBEs in these portions of the memory device may be more likely to turn into DBEs before such data is accessed.

As described herein, a memory device may perform error correction as part of a refresh operation to periodically perform error correction on each portion of a memory device. For example, a host device may periodically transmit a refresh command with ECC (e.g., REF_wECC) that indicates an ECC check is to be performed, where the refresh with ECC command may be different from a refresh command (i.e., different from a refresh command performed without error correction). The memory device may include an ECC patrol block that includes a counter to indicate a portion of a row (i.e., a quantity of logical columns of the row) on which to perform error correction. In response to receiving the refresh with ECC command, the memory device may activate a row and perform error correction for the portion of the row to check and correct for errors. The ECC patrol block may also increment and reset the counter, so that the ECC block may perform error correction on each portion of each row of the memory device over the course of several refresh with ECC commands. Additionally or alternatively, the memory device may operate in a self-refresh mode, and may perform refresh operations, including the refresh with ECC operation as described herein, without receiving commands from the host system. While examples of the present disclosure may be described with reference to DRAM devices, the techniques described herein may be applied to any memory type.

Features of the disclosure are initially described in the context of systems and dies as described with reference toFIGS.1and2. Features of the disclosure are described in the context a system and a process flow as described with reference toFIGS.3-4. These and other features of the disclosure are further illustrated by and described with reference to an apparatus diagram and flowcharts that relate to techniques for memory error correction as described with reference toFIGS.5-6.

FIG.1illustrates an example of a system100that supports techniques for memory error correction in accordance with examples as disclosed herein. The system100may include a host device105, a memory device110, and a plurality of channels115coupling the host device105with the memory device110. The system100may include one or more memory devices110, but aspects of the one or more memory devices110may be described in the context of a single memory device (e.g., memory device110).

At least portions of the system100may be examples of the host device105. The host device105may be an example of a processor or other circuitry within a device that uses memory to execute processes, such as within a computing device, a mobile computing device, a wireless device, a graphics processing device, a computer, a laptop computer, a tablet computer, a smartphone, a cellular phone, a wearable device, an internet-connected device, a vehicle controller, a system on a chip (SoC), or some other stationary or portable electronic device, among other examples. In some examples, the host device105may refer to the hardware, firmware, software, or a combination thereof that implements the functions of an external memory controller120. In some examples, the external memory controller120may be referred to as a host or a host device105.

The memory device110may be operable to store data for the components of the host device105. In some examples, the memory device110may act as a secondary-type or dependent-type device to the host device105(e.g., responding to and executing commands provided by the host device105through the external memory controller120). Such commands may include one or more of a write command for a write operation, a read command for a read operation, a refresh command for a refresh operation, or other commands.

The host device105may include one or more of an external memory controller120, a processor125, a basic input/output system (BIOS) component130, or other components such as one or more peripheral components or one or more input/output controllers. The components of the host device105may be coupled with one another using a bus135.

The device memory controller155may include circuits, logic, or components operable to control operation of the memory device110. The device memory controller155may include the hardware, the firmware, or the instructions that enable the memory device110to perform various operations and may be operable to receive, transmit, or execute commands, data, or control information related to the components of the memory device110. The device memory controller155may be operable to communicate with one or more of the external memory controller120, the one or more memory dies160, or the processor125. In some examples, the device memory controller155may control operation of the memory device110described herein in conjunction with the local memory controller165of the memory die160.

In some examples, the memory device110may receive data or commands or both from the host device105. For example, the memory device110may receive a write command indicating that the memory device110is to store data for the host device105or a read command indicating that the memory device110is to provide data stored in a memory die160to the host device105.

In some examples, CA channels186may be operable to communicate commands between the host device105and the memory device110including control information associated with the commands (e.g., address information). For example, commands carried by the CA channel186may include a read command with an address of the desired data. In some examples, a CA channel186may include any quantity of signal paths to decode one or more of address or command data (e.g., eight or nine signal paths).

In some examples, data channels190may be operable to communicate one or more of data or control information between the host device105and the memory device110. For example, the data channels190may communicate information (e.g., bi-directional) to be written to the memory device110or information read from the memory device110.

In some examples, the one or more other channels192may include one or more error detection code (EDC) channels. The EDC channels may be operable to communicate error detection signals, such as checksums, to improve system reliability. An EDC channel may include any quantity of signal paths.

The system100may include any quantity of non-transitory computer readable media that support techniques for memory error correction. For example, the host device105, the device memory controller155, or a memory device110may include or otherwise may access one or more non-transitory computer readable media storing instructions (e.g., firmware) for performing the functions ascribed herein to the host device105, device memory controller155, or memory device110. For example, such instructions, if executed by the host device105(e.g., by the external memory controller120), by the device memory controller155, or by a memory device110(e.g., by a local controller165), may cause the host device105, device memory controller155, or memory device110to perform associated functions as described herein.

In some cases, a memory die160may include an ECC block (i.e., an on-die ECC block) used for performing error correction operations (e.g., SEC operations) on data stored on the memory die160. Errors, such as single bit errors (SBEs), may be introduced into the data from electromagnetic radiation, high-energy particles (e.g., from cosmic rays), memory cell wear and age, or a combination thereof, among other examples. If a set of data with a SBE develops one or more additional errors (i.e., a double bit error (DBE) or multiple bit error (MBE)), error correction operations such as SEC and SECDED may not be able to correct the DBE. Thus, it may be advantageous to correct SBEs relatively quickly, and thus mitigate the likelihood of developing DBEs. To correct SBEs, error correction operations may be performed on data during access operations (i.e., read or write operations). However, some regions of data in a memory array170may be accessed more frequently than other regions (i.e., some regions of data may be “hot”, while other regions may be “cold”). Because cold regions of the memory array170are accessed relatively infrequently, the cold regions may be more susceptible to developing DBEs.

In some cases, a memory system100may prevent cold regions from developing

DBEs or MBEs by periodically performing an access operation (e.g., a read operation) on each region of the memory array170, thus preventing any region from becoming cold. However, periodically performing a read operation on each region of the memory array170may introduce system latency and power consumption, for example by consuming bandwidth resources used for communicating data between the host device105and the memory device110. That is, the read operations used to prevent cold regions may prevent other operations from transferring data between the host device105and the memory device110during the read operation. For example, bandwidth resources consumed by read operations used to prevent cold regions may contribute to so-called page conflicts in which two immediately subsequent access operations (e.g., a read followed by a read or write, or a write followed by a read or write) may target different rows (i.e., pages) of the same bank. Such page conflicts cases lead to an increased quantity of row-switching commands and operations (e.g., activate and precharge commands and operations), which in return may degrade efficiency (e.g., overall bus efficiency).

In some examples, a memory system100may perform error correction as part of a refresh operation—e.g., in addition to or as an alternative to performing error correction as part of an access operation (e.g., a read or write operation). For example, the memory system100may be configured to support a refresh command, as well as a refresh with ECC command. The refresh command may cause a region of a memory array170(e.g., a row of a memory array170) to be accessed and the read data written back to the region. Alternatively, a refresh with ECC command may cause the region of the memory array170to be accessed and, along with the read data being writing back to the region, may cause the ECC block to perform an error correction operation on the region or a portion of the region. In some cases, the host system105may be configured to issue the refresh command, the refresh with ECC command, or both, to the memory device110. In other cases, the memory device110may initiate a refresh operation with ECC, for example as part of a self-refresh mode. A memory system100that supports the refresh with ECC command may reduce system latency and power consumption by preventing cold regions from developing multi-bit errors without consuming bandwidth resources used for communicating data between the host system105and the memory device110.

FIG.2illustrates an example of a memory die200that supports techniques for memory error correction in accordance with examples as disclosed herein. The memory die200may be an example of the memory dies160described with reference toFIG.1. In some examples, the memory die200may be referred to as a memory chip, a memory device, or an electronic memory apparatus. The memory die200may include one or more memory cells205that may each be programmable to store different logic states (e.g., programmed to one of a set of two or more possible states). For example, a memory cell205may be operable to store one bit of information at a time (e.g., a logic0or a logic1). In some examples, a memory cell205(e.g., a multi-level memory cell) may be operable to store more than one bit of information at a time (e.g., a logic00, logic01, logic10, a logic11). In some examples, the memory cells205may be arranged in an array, such as a memory array170described with reference toFIG.1.

A memory cell205may store a charge representative of the programmable states in a capacitor. DRAM architectures may include a capacitor that includes a dielectric material to store a charge representative of the programmable state. In other memory architectures, other storage devices and components are possible. For example, nonlinear dielectric materials may be employed. The memory cell205may include a logic storage component, such as capacitor230, and a switching component235. The capacitor230may be an example of a dielectric capacitor or a ferroelectric capacitor. A node of the capacitor230may be coupled with a voltage source240, which may be the cell plate reference voltage, such as Vpl, or may be ground, such as Vss.

The memory die200may include one or more access lines (e.g., one or more word lines210and one or more digit lines215) arranged in a pattern, such as a grid-like pattern. An access line may be a conductive line coupled with a memory cell205and may be used to perform access operations on the memory cell205. In some examples, word lines210may be referred to as row lines. In some examples, digit lines215may be referred to as column lines or bit lines. References to access lines, row lines, column lines, word lines, digit lines, or bit lines, or their analogues, are interchangeable without loss of understanding or operation. Memory cells205may be positioned at intersections of the word lines210and the digit lines215.

Operations such as reading and writing may be performed on the memory cells205by activating or selecting access lines such as one or more of a word line210or a digit line215. By biasing a word line210and a digit line215(e.g., applying a voltage to the word line210or the digit line215), a single memory cell205may be accessed at their intersection. The intersection of a word line210and a digit line215in either a two-dimensional or three-dimensional configuration may be referred to as an address of a memory cell205.

Accessing the memory cells205may be controlled through a row decoder220or a column decoder225. For example, a row decoder220may receive a row address from the local memory controller260and activate a word line210based on (e.g., using) the received row address. A column decoder225may receive a column address from the local memory controller260and may activate a digit line215based on (e.g., using) the received column address.

Selecting or deselecting the memory cell205may be accomplished by activating or deactivating the switching component235using a word line210. The capacitor230may be coupled with the digit line215using the switching component235. For example, the capacitor230may be isolated from digit line215if the switching component235is deactivated, and the capacitor230may be coupled with digit line215if the switching component235is activated.

The sense component245may be operable to detect a state (e.g., a charge) stored on the capacitor230of the memory cell205and determine a logic state of the memory cell205based on (e.g., using) the stored state. The sense component245may include one or more sense amplifiers to amplify or otherwise convert a signal resulting from accessing the memory cell205. The sense component245may compare a signal detected from the memory cell205to a reference250(e.g., a reference voltage). The detected logic state of the memory cell205may be provided as an output of the sense component245(e.g., to an input/output255), and may indicate the detected logic state to another component of a memory device that includes the memory die200.

The local memory controller260may control the accessing of memory cells205through the various components (e.g., row decoder220, column decoder225, sense component245). The local memory controller260may be an example of the local memory controller165described with reference toFIG.1. In some examples, one or more of the row decoder220, column decoder225, and sense component245may be co-located with the local memory controller260. The local memory controller260may be operable to receive one or more of commands or data from one or more different memory controllers (e.g., an external memory controller120associated with a host device105, another controller associated with the memory die200), translate the commands or the data (or both) into information that can be used by the memory die200, perform one or more operations on the memory die200, and communicate data from the memory die200to a host device105based on (e.g., in response to) performing the one or more operations. The local memory controller260may generate row signals and column address signals to activate the target word line210and the target digit line215. The local memory controller260may also generate and control various voltages or currents used during the operation of the memory die200. In general, the amplitude, the shape, or the duration of an applied voltage or current discussed herein may be varied and may be different for the various operations discussed in operating the memory die200.

The local memory controller260may be operable to perform one or more access operations on one or more memory cells205of the memory die200. Examples of access operations may include a write operation, a read operation, a refresh operation, a precharge operation, or an activate operation, among others. In some examples, access operations may be performed by or otherwise coordinated by the local memory controller260in response to various access commands (e.g., from a host device105). The local memory controller260may be operable to perform other access operations not listed here or other operations related to the operating of the memory die200that are not directly related to accessing the memory cells205.

The local memory controller260may be operable to perform a write operation (e.g., a programming operation) on one or more memory cells205of the memory die200. During a write operation, a memory cell205of the memory die200may be programmed to store a desired logic state. The local memory controller260may identify a target memory cell205on which to perform the write operation. The local memory controller260may identify a target word line210and a target digit line215coupled with the target memory cell205(e.g., the address of the target memory cell205). The local memory controller260may activate the target word line210and the target digit line215(e.g., applying a voltage to the word line210or digit line215) to access the target memory cell205. The local memory controller260may apply a specific signal (e.g., write pulse) to the digit line215during the write operation to store a specific state (e.g., charge) in the capacitor230of the memory cell205. The pulse used as part of the write operation may include one or more voltage levels over a duration.

The local memory controller260may be operable to perform a read operation (e.g., a sense operation) on one or more memory cells205of the memory die200. During a read operation, the logic state stored in a memory cell205of the memory die200may be determined. The local memory controller260may identify a target memory cell205on which to perform the read operation. The local memory controller260may identify a target word line210and a target digit line215coupled with the target memory cell205(e.g., the address of the target memory cell205). The local memory controller260may activate the target word line210and the target digit line215(e.g., applying a voltage to the word line210or digit line215) to access the target memory cell205. The target memory cell205may transfer a signal to the sense component245in response to biasing the access lines. The sense component245may amplify the signal. The local memory controller260may activate the sense component245(e.g., latch the sense component) and thereby compare the signal received from the memory cell205to the reference250. Based on (e.g., using) that comparison, the sense component245may determine a logic state that is stored on the memory cell205.

In some examples, a memory die200may be included as part of an automotive or other system that is safety sensitive, stability sensitive, or both. Errors, such as SBEs, may be introduced into the data stored in the memory die200from electromagnetic radiation, high-energy particles (e.g., from cosmic rays), memory cell wear and age, or a combination thereof, among other examples. If a set of data with a SBE develops one or more additional errors, such as DBEs or MBEs, error correction operations such as SEC and SECDED may not be able to correct the errors. Thus, it may be advantageous to correct SBEs relatively quickly, and thus mitigate the likelihood of developing DBEs.

In some cases, the memory die200may include an ECC block275(e.g., an on-die ECC) to perform error correction operations on data stored in the memory die200, which may include error detection operations or capabilities. The ECC block275may perform error correction operations on data during access operations (i.e., read or write operations). However, some regions of data in the memory die200may be accessed more frequently than other regions (i.e., some regions of data may be “hot”, while other regions may be “cold”). Because cold regions of the memory die200are accessed relatively infrequently, the cold regions may be more susceptible to developing DBEs or MBEs.

In some examples, the memory die200may perform error correction as part of a refresh operation—e.g., in the alternative or in addition to performing error correction as part of an access operation (e.g., a read or write operation). For example, the memory die200may be configured to support a refresh command, as well as a refresh with ECC command. Additionally or alternatively, the memory die200may support performing the refresh operation with ECC as part of a self-refresh mode. The refresh operation may cause a region of the memory die200(e.g., a row of memory cells205) to be accessed and written back to the region. Alternatively, a refresh operation with ECC may cause the region of the memory array to be accessed and subsequently may cause the ECC block275to perform an error correction operation on the region or a portion of the region. A memory die200that supports the refresh with ECC operation may reduce system latency and power consumption by preventing cold regions from developing without consuming bandwidth resources used for communicating data between a host system and a memory device.

To perform error correction on a set of data, the ECC block275may be configured to generate, using a code or algorithm, a first set of one or more parity bits associated with the set of data. The first parity bits may be compared with a second set of parity bits which were generated, for example as part of or otherwise in connection with previously writing the set of data, using the same code or algorithm. If no errors have been introduced in the set of data, then the first parity bits and the second parity bits may match. Thus, the ECC block275may be configured to determine whether the set of data contains a data error by comparing the first parity bits with the second parity bits. In some cases, the ECC block275may be configured to correct SBEs detected during the error correction procedure, though ECC schemes supporting detection or correction of other quantities of errors in a set of data may alternatively be implemented by ECC block275.

FIG.3illustrates an example of a system300that supports techniques for memory error correction in accordance with examples as disclosed herein. The system300may include a column decoder225-a,a row decoder220-a,an input/output255-a,a sense component245-a,and an ECC block275-a,which may be examples of the corresponding devices described with reference toFIG.2.

The system300may also include a memory controller301, which may include aspects of a device memory controller or a local memory controller described with reference toFIGS.1and2, and a memory array303, which may include rows and columns of memory cells. The ECC block275-amay perform error correction, such as an SEC operation, on portions of the memory array303. That is, the ECC block275-amay check a first portion of a row for data errors in connection with a refresh operation, and refrain from checking a second portion of the row for data errors in connection with the refresh operation. The memory controller301may include a controller logic component302configured to receive or process commands, such as refresh commands, from a host device. The commands may be decoded by a command/address (C/A) decode component320. For example. the C/A decode component320may be configured to determine whether a command is a refresh command or a refresh with ECC command. The memory controller301may also include a row multiplexer (MUX)321and a column MUX322, which may be configured to issue row and column addresses to the row decoder220-aand the column decoder225-aas part of, for example, a refresh operation. The refresh operation may include accessing a row of the memory array303and refreshing the data stored in the row (e.g., writing the data stored in the row back to the row).

The memory controller301may include a refresh counter305, which may be configured to track and store a value associated with a quantity of refresh operations performed at the memory array303(e.g., since a most recent reset of the refresh counter305). The refresh counter305may indicate a row or set of rows to be refreshed to the row MUX321, which may in turn indicate the row or set of rows to be refreshed to the row decoder220-a and the memory array303. For example, upon receiving a refresh indication330from the controller logic component302, the refresh counter305may issue to the row MUX321an indication311of the row or set of rows to be refreshed based on (e.g., using) the value of the refresh counter305, and the value of the refresh counter305may be incremented. In some cases, the value of the refresh counter305may be reset (e.g., reset to zero) if the incremented value thereof would exceed the quantity of rows in the memory array303or the counter otherwise reaches a threshold value or rolls over. That is, for example, after refreshing each row of the memory array303, the refresh counter305may be reset (e.g., to an initial value). Thus, upon receiving a quantity of refresh indications330equal to the quantity of rows of the memory array303(or set of rows for refresh purposes), each row of the memory array303may be refreshed.

The memory controller may also include an ECC patrol block310. The ECC patrol block310may include a counter315, which may indicate a portion of a row on which error correction is to be performed. For example, the counter315may indicate an address of one or more logical columns of the row on which error correction is to be performed. The quantity of logical columns included in the portion of the row (i.e., a granularity with which the row is divided into portions for ECC patrol purposes, which may correspond to how many portions into which the row is divided) may be configured using a command, through firmware, or through user input, among other examples. In some examples, the portion of a row may correspond to a quantity of columns from which a burst of data is to be read, and may be referred to as a pre-fetch unit. In other examples, the portion of the row may include the entire row of the memory array303, or any quantity of logical columns of the memory array303. The ECC patrol block310may issue an indication of the portion of the row to the column MUX322and the ECC block275-a.The column MUX322may, in response to the indication, issue the indication to the column decoder225-a,which may issue the indication to the input/output255-a,where the input/output255-amay be configured to transfer the address of the portion of the row to the ECC block275-a.The counter315may be reset upon reaching a threshold—e.g., once a value of the counter315corresponds to a last row portion (e.g., last set of columns) within the memory array303, a next incrementing of the counter315may cause the value of the counter to reset (e.g., roll over).

The ECC block275-amay perform error correction on the portion of the row, and issue the results (e.g., an indication of any corrected bits corrected as a result of the error correction) to the memory array as part of the refresh operation (i.e., via the input/output255-aand the sense component245-a). That is, the ECC block275-amay determine whether the portion of the row includes a data error (e.g., an SBE) and, in some examples, correct the data error in the portion of the row. To identify and correct errors in a portion of the row, the ECC block275-amay generate one or more parity bits for the portion of the row and compare the parity bits with parity bits corresponding to the portion of the row that have been previously stored.

The counter315may store and increment a value indicating the portion of the row upon which the ECC block275-ais to perform error correction (i.e., an address counter or column counter). For example, the memory cells of each row of the memory array303may be grouped into a quantity of units (e.g., portions of the row, such as pre-fetch units), which may be indexed, where the indices correspond to possible values of the counter315.

In some examples, upon receiving a refresh with ECC indication335, the ECC patrol block310may also receive an indication311of the value of the refresh counter305, and the ECC patrol block310may be configured to increment the counter315based on the value of the refresh counter305(e.g., based on the refresh counter305being reset). Additionally or alternatively, the ECC patrol block310may be configured to increment the counter315based on the quantity of refresh with ECC indications335received. For example, the ECC patrol block may include an error correction counter316, which may be configured to be incremented each time a refresh with ECC indication335is received, and the ECC patrol block310may be configured to increment the counter315based on the value of the error correction counter316(e.g., based on the error correction counter316being reset).

The quantity of refresh with ECC indications335issued per refresh indication330may be managed by one or both of the host device and the system300. For example, a refresh with ECC indication335may be issued once per period, where the period may represent a quantity of refresh indications330. In some cases, the period may be a quantity p of refresh cycles, where a refresh cycle may be the quantity of refresh operations used to refresh each row of the memory array303. Thus, for example, p multiplied by the quantity of refresh operations in a refresh cycle (e.g., p multiplied by a quantity of refresh operations used to refresh each row of the memory array303one time) may correspond to (e.g., equal) a quantity of regular refresh operations performed in between each successive refresh with ECC operation. In some other cases, the period may be a quantity p of refresh indications330(e.g., for every two refresh indications330, one refresh with ECC indication335may be issued). Thus, a period may in some cases be a fraction of a refresh cycle.

In some cases, the host device may send refresh commands to the system300, for example as part of an auto-refresh mode. In such cases, the host device may include a refresh handler, which may be configured to manually or automatically adjust the quantity p. Additionally or alternatively, the system300may operate using a self-refresh mode, in which the system300performs refresh operations without receiving a refresh command from the host device. If operating in a self-refresh mode, the system300may include a mode register319used to store the quantity p, and may determine the period during a self-refresh operation. In some cases, such as upon a self-refresh entry or self-refresh exit, one refresh with ECC indication335may be issued. That is, a refresh with ECC indication335may executed by the system300or by a refresh handler within a host device upon entering the self-refresh mode and upon exiting the self-refresh mode.

In some examples, the ECC patrol block310may increment the value of the counter315in response to the refresh counter305being reset (i.e., reset to zero) or otherwise reaching some threshold. If a refresh with ECC is performed on each row of the memory array330successively (e.g., if p is zero), then resetting the refresh counter in such fashion may cause the counter315to be reset upon performing the error correction operation on the last (e.g., end) portion of the final row. That is, if the value of the counter315corresponds to the last (e.g., end) portion of the row and the refresh counter305is then reset, the counter315may be reset, and where p is zero, this may mean that refresh with ECC has most recently been performed on the last portion of the final row.

If, however, some quantity of regular refresh operations are performed between successive refresh with ECC operations (e.g., p has a non-zero value), then incrementing the counter315in response to the refresh counter305being reset (i.e., set to zero) or otherwise reaching some threshold may cause the counter315to be reset upon performing the error correction operation on the last (e.g., end) portion of any row. For example, if two regular refresh operations are performed between successive refresh with ECC operations, a refresh with ECC operation may be performed on the end portion of one of the two rows preceding the final row, then the refresh counter305may be reset based on a regular refresh operation corresponding to the final row, and hence a next refresh with ECC operation may be performed on a first portion of the first or second row of the memory array330.

In some examples, the counter315may be incremented in response to refresh with ECC being performed on a certain portion (e.g., corresponding to particular portion index) of all rows of the memory array330(e.g., once refresh with ECC has been performed on the first portion of each row of the memory array, the counter315may be incremented, and then once refresh with ECC has been performed on the second portion of each row of the memory array, the counter315may again be incremented, and so on). For example, if the counter315is incremented in response to the error correction counter316being reset, then the counter315may not increment until refresh with ECC has been performed on a certain portion (e.g., a group of columns) across all rows of the memory array330. If the value of p is zero, this may cause refresh with ECC to be performed sequentially across all rows of the memory array330within each successive portion. If, however, the value of p is non-zero, this may cause refresh with ECC to be performed across the rows of the memory array330within a given portion in non-sequential fashion (e.g., the row being refreshed may change based on the separate incrementing of the refresh counter305, but the value of the counter315—and hence the portion subject to refresh with ECC—may not change until the error correction counter316resets).

By incrementing the value of the refresh counter305and the counter315(and the error correction counter316, if present) as described herein, the ECC block275-amay perform error correction on each portion of each row of the memory array303over time.

FIG.4illustrates an example of a process flow400that supports techniques for memory error correction in accordance with examples as disclosed herein. The process flow400may be performed by components of a memory system, such as a controller (e.g., a memory controller301as described with reference toFIG.3), which may include an ECC patrol block (e.g., the ECC patrol block310). Additionally or alternatively, aspects of the process flow400may be implemented as instructions stored in memory (e.g., firmware stored in a memory coupled with a device memory controller155or a local memory controller165described with reference toFIG.1). For example, the instructions, if executed by a controller (e.g., a device memory controller155or a local controller165), may cause the controller to perform the operations of the process flow400. In the following description of process flow400, the operations may be performed in a different order than the order shown. For example, specific operations may also be left out of process flow400, or other operations may be added to process flow400.

At405, a refresh operation may be identified. For example, the memory controller may receive an external refresh command from a host device to refresh a row of a memory array. Additionally or alternatively, the memory controller may be operating in a self-refresh mode, and the memory controller may be configured to issue refresh indications for the memory array.

In some cases, the memory system may identify a refresh with ECC operation as part of identifying the refresh operation. For example, a refresh with ECC indication may be issued, either based on a refresh with ECC command received from the host device or based on a mode register at the memory controller. In some examples, the refresh with ECC indication may be issued based on a periodicity, as described with reference toFIG.3. Thus, at410, it may be determined whether the refresh operation identified at405is a refresh with ECC operation. For example, the memory controller may determine whether the refresh operation is associated with a refresh command or a refresh with ECC command received from the host device.

In some cases, it may be determined that the refresh operation is a refresh with ECC operation. In such cases, at415, a refresh counter (e.g., the refresh counter305as described with reference toFIG.3) may be incremented. For example, in response to identifying the refresh operation at405, the memory controller may increment the value of the refresh counter to indicate a row of the memory array to be refreshed, as described with reference toFIG.3.

At420, it may be determined whether to reset to refresh counter. For example, the value of the refresh counter may exceed the quantity of rows of the memory array, indicating that the refresh operation identified at405corresponds to a first row of the memory array (i.e., a previous refresh operation may have refreshed the last row of the memory array). Thus, by comparing the value of the refresh counter to a threshold, such as the quantity of rows of the memory device, the value of the refresh counter may be reset at425. That is, in response to determining that the refresh counter exceeds the threshold, the memory controller may reset the refresh counter.

Optionally, at430, it may be determined whether to reset an error correction counter (e.g., the error correction counter316of the ECC patrol block310as described with reference toFIG.3) at the ECC patrol block. For example, if the error correction counter exceeds a threshold, such as the quantity of rows in the memory array, the ECC patrol block may reset (i.e., set to zero) the error correction counter at435.

At440, an address counter (e.g., the counter315of the ECC patrol block310as described with reference toFIG.3) may be incremented. For example, the memory controller may increment the address counter in response to the refresh counter being reset at425. The address counter may identify a portion of the row of memory cells, for example as described with reference toFIG.3.

At445, a row may be accessed. For example, the memory controller may access a row indicated by the value of the refresh counter of the memory controller. Using the value of the address counter and, in some cases, the error correction counter, the memory controller may issue an indication to an ECC block (e.g., the ECC block275-aas described with reference toFIG.3) of a portion of the accessed row on which to perform an error correction operation.

At450, ECC may be performed on a portion of the row accessed at445. For example, the ECC block275-amay perform error correction, such as a SEC operation, on the portion of the row indicated by the refresh counter and the address counter. The error correction may include generating one or more parity bits for the portion of the row and compare the parity bits with parity bits corresponding to the portion of the row that have been previously stored. That is, the ECC block may check a first portion of a row for data errors in connection with a refresh operation, and refrain from checking a second portion of the row for data errors in connection with the refresh operation.

Additionally or alternatively, it may be determined at410that the refresh operation is not a refresh with ECC operation. In such cases, at455, a row may be accessed. For example, the memory controller may access a row indicated by the value of the refresh counter of the memory controller and write back data of the row (e.g., as part of a refresh operation at460).

At460, the row may be refreshed. For example, the memory controller may refresh the row of the memory array indicated by the refresh counter by writing back the data of row after accessing the row. In some cases (i.e., if error correction has been performed), writing back the data may include writing back the data that has been corrected as part of the error correction procedure at450.

Aspects of the process flow400may be implemented by a controller, among other components. Additionally or alternatively, aspects of the process flow400may be implemented as instructions stored in memory (e.g., firmware stored in a memory coupled with a memory system). For example, the instructions, executed by a controller (e.g., an external memory controller120, a device memory controller155, a local memory controller260, or a combination thereof), may cause the controller to perform the operations of the process flow400.

FIG.5shows a block diagram500of a memory device520that supports techniques for memory error correction in accordance with examples as disclosed herein. The memory device520may be an example of aspects of a memory device as described with reference toFIGS.1through4. The memory device520, or various components thereof, may be an example of means for performing various aspects of techniques for memory error correction as described herein. For example, the memory device520may include a command manager525, a row access component530, an error correction manager535, a counter manager540, a period manager545, an address manager550, or any combination thereof. Each of these components may communicate, directly or indirectly, with one another (e.g., via one or more buses).

The command manager525may be configured as or otherwise support a means for identifying, at a memory system, a refresh operation for a row of memory cells within a memory array. The row access component530may be configured as or otherwise support a means for accessing the row of memory cells within the memory array in response to identifying the refresh operation. The error correction manager535may be configured as or otherwise support a means for determining whether the row includes a data error based at least in part on accessing the row in response to identifying the refresh operation. In some examples, the error correction manager535may be configured as or otherwise support a means for correcting the data error using an error correction procedure based at least in part on determining that the row includes the data error.

In some examples, the counter manager540may be configured as or otherwise support a means for incrementing a value of a refresh counter in response to identifying the refresh operation, where accessing the row of memory cells is based at least in part on the value of the refresh counter.

In some examples, the refresh counter is configured to be reset to an initial value based at least in part on the value of the refresh counter satisfying a threshold, and the counter manager540may be configured as or otherwise support a means for incrementing a value of an address counter based at least in part on the value of the refresh counter being reset to the initial value. In some examples, the refresh counter is configured to be reset to an initial value based at least in part on the value of the refresh counter satisfying a threshold, and the address manager550may be configured as or otherwise support a means for accessing at least a portion of data in the row based at least in part on the value of the address counter, where determining whether the row includes the data error includes determining whether at least the portion of data in the row includes the data error based at least in part on accessing at least the portion of data.

In some examples, the counter manager540may be configured as or otherwise support a means for incrementing a value of an error correction counter in response to identifying the refresh operation, where the error correction counter is configured to be reset to an initial value based at least in part on the value of the error correction counter satisfying a threshold. In some examples, the counter manager540may be configured as or otherwise support a means for incrementing a value of an address counter based at least in part on the value of the error correction counter being reset to the initial value. In some examples, the row access component530may be configured as or otherwise support a means for accessing at least a portion of data in the row based at least in part on the value of the address counter, where determining whether the row includes the data error includes determining whether at least the portion of data in the row includes the data error based at least in part on accessing at least the portion of data.

In some examples, the command manager525may be configured as or otherwise support a means for receiving a first refresh command, where identifying the refresh operation is based at least in part on receiving the first refresh command. In some examples, the command manager525may be configured as or otherwise support a means for identifying the first refresh command as a first type of refresh command, where determining whether the row includes the data error is in response to identifying the first refresh command as the first type of refresh command.

In some examples, the command manager525may be configured as or otherwise support a means for receiving a second refresh command. In some examples, the command manager525may be configured as or otherwise support a means for identifying the second refresh command as a second type of refresh command different than the first type of refresh command. In some examples, the error correction manager535may be configured as or otherwise support a means for refraining from performing a second error detection procedure in response to the second refresh command based at least in part on identifying the second refresh command as the second type of refresh command.

In some examples, the period manager545may be configured as or otherwise support a means for identifying a periodicity associated with checking for data errors in connection with refresh operations, the periodicity corresponding to a quantity of intervening refresh operations without error detection between refresh operations with error detection, where determining whether the row includes the data error based at least in part on the periodicity.

In some examples, the period manager545may be configured as or otherwise support a means for identifying the periodicity based at least in part on a value stored at a memory device.

In some examples, the error correction manager535may be configured as or otherwise support a means for determining whether the row includes the data error in response to identifying the refresh operation based at least in part on the refresh operation being an initial refresh operation of a set of self-refresh operations, a final refresh operation of the set of self-refresh operations, an initial refresh operation of a set of commanded refresh operations, or a final refresh operation of the set of commanded refresh operations.

In some examples, the address manager550may be configured as or otherwise support a means for determining an address associated with a portion of data in the row based at least in part on a value of an address counter, where accessing the row of memory cells includes accessing the portion of data. In some examples, the error correction manager535may be configured as or otherwise support a means for generating one or more parity bits for the portion of data based at least in part on accessing the portion of data. In some examples, the error correction manager535may be configured as or otherwise support a means for comparing the one or more generated parity bits for the portion of data with one or more parity bits previously stored for the portion of data, where determining whether the row includes the data error is based at least in part on the comparing.

In some examples, the row access component530may be configured as or otherwise support a means for refreshing the row of memory cells as part of the refresh operation, where determining whether the row includes the data error further includes. In some examples, the error correction manager535may be configured as or otherwise support a means for checking a first portion of the row for data errors in connection with the refresh operation. In some examples, the error correction manager535may be configured as or otherwise support a means for refraining from checking a second portion of the row for data errors in connection with the refresh operation.

In some examples, the row access component530may be configured as or otherwise support a means for identifying a size of the first portion of the row based at least in part on a value stored at a memory device.

In some examples, to support determining whether the row includes the data error, the error correction manager535may be configured as or otherwise support a means for performing a single error correction (SEC) procedure for at least a portion of data stored in the row.

FIG.6shows a flowchart illustrating a method600that supports techniques for memory error correction in accordance with examples as disclosed herein. The operations of method600may be implemented by a memory device or its components as described herein. For example, the operations of method600may be performed by a memory device as described with reference toFIGS.1through5. In some examples, a memory device may execute a set of instructions to control the functional elements of the device to perform the described functions. Additionally or alternatively, the memory device may perform aspects of the described functions using special-purpose hardware.

At605, the method may include identifying, at a memory system, a refresh operation for a row of memory cells within a memory array. The operations of605may be performed in accordance with examples as disclosed herein. In some examples, aspects of the operations of605may be performed by a command manager525as described with reference toFIG.5.

At610, the method may include accessing the row of memory cells within the memory array in response to identifying the refresh operation. The operations of610may be performed in accordance with examples as disclosed herein. In some examples, aspects of the operations of610may be performed by a row access component530as described with reference toFIG.5.

At615, the method may include determining whether the row includes a data error based at least in part on accessing the row in response to identifying the refresh operation. The operations of615may be performed in accordance with examples as disclosed herein. In some examples, aspects of the operations of615may be performed by an error correction manager535as described with reference toFIG.5.

At620, the method may include correcting the data error using an error correction procedure based at least in part on determining that the row includes the data error. The operations of620may be performed in accordance with examples as disclosed herein. In some examples, aspects of the operations of620may be performed by an error correction manager535as described with reference toFIG.5.

In some examples, an apparatus as described herein may perform a method or methods, such as the method600. The apparatus may include, features, circuitry, logic, means, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for identifying, at a memory system, a refresh operation for a row of memory cells within a memory array, accessing the row of memory cells within the memory array in response to identifying the refresh operation, determining whether the row includes a data error based at least in part on accessing the row in response to identifying the refresh operation, and correcting the data error using an error correction procedure based at least in part on determining that the row includes the data error.

Some examples of the method600and the apparatus described herein may further include operations, features, circuitry, logic, means, or instructions for incrementing a value of a refresh counter in response to identifying the refresh operation, where accessing the row of memory cells may be based at least in part on the value of the refresh counter.

In some examples of the method600and the apparatus described herein, the refresh counter may be configured to be reset to an initial value based at least in part on the value of the refresh counter satisfying a threshold, and the method, apparatuses, and non-transitory computer-readable medium may include further operations, features, circuitry, logic, means, or instructions for incrementing a value of an address counter based at least in part on the value of the refresh counter being reset to the initial value and for accessing at least a portion of data in the row based at least in part on the value of the address counter, where determining whether the row includes the data error includes determining whether at least the portion of data in the row includes the data error based at least in part on accessing at least the portion of data.

Some examples of the method600and the apparatus described herein may further include operations, features, circuitry, logic, means, or instructions for incrementing a value of an error correction counter in response to identifying the refresh operation, where the error correction counter may be configured to be reset to an initial value based at least in part on the value of the error correction counter satisfying a threshold, incrementing a value of an address counter based at least in part on the value of the error correction counter being reset to the initial value, and accessing at least a portion of data in the row based at least in part on the value of the address counter, where determining whether the row includes the data error includes determining whether at least the portion of data in the row includes the data error based at least in part on accessing at least the portion of data.

Some examples of the method600and the apparatus described herein may further include operations, features, circuitry, logic, means, or instructions for receiving a first refresh command, where identifying the refresh operation may be based at least in part on receiving the first refresh command, and identifying the first refresh command as a first type of refresh command, where determining whether the row includes the data error may be in response to identifying the first refresh command as the first type of refresh command.

Some examples of the method600and the apparatus described herein may further include operations, features, circuitry, logic, means, or instructions for receiving a second refresh command, identifying the second refresh command as a second type of refresh command different than the first type of refresh command, and refraining from performing a second error detection procedure in response to the second refresh command based at least in part on identifying the second refresh command as the second type of refresh command.

Some examples of the method600and the apparatus described herein may further include operations, features, circuitry, logic, means, or instructions for identifying a periodicity associated with checking for data errors in connection with refresh operations, the periodicity corresponding to a quantity of intervening refresh operations without error detection between refresh operations with error detection, where determining whether the row includes the data error is based at least in part on the periodicity.

Some examples of the method600and the apparatus described herein may further include operations, features, circuitry, logic, means, or instructions for identifying the periodicity based at least in part on a value stored at a memory device.

Some examples of the method600and the apparatus described herein may further include operations, features, circuitry, logic, means, or instructions for determining whether the row includes the data error in response to identifying the refresh operation based at least in part on the refresh operation being an initial refresh operation of a set of self-refresh operations, a final refresh operation of the set of self-refresh operations, an initial refresh operation of a set of commanded refresh operations, or a final refresh operation of the set of commanded refresh operations.

Some examples of the method600and the apparatus described herein may further include operations, features, circuitry, logic, means, or instructions for determining an address associated with a portion of data in the row based at least in part on a value of an address counter, where accessing the row of memory cells includes accessing the portion of data, generating one or more parity bits for the portion of data based at least in part on accessing the portion of data, and comparing the one or more generated parity bits for the portion of data with one or more parity bits previously stored for the portion of data, where determining whether the row includes the data error may be based at least in part on the comparing.

Some examples of the method600and the apparatus described herein may further include operations, features, circuitry, logic, means, or instructions for refreshing the row of memory cells as part of the refresh operation, where determining whether the row includes the data error includes checking a first portion of the row for data errors in connection with the refresh operation, and refraining from checking a second portion of the row for data errors in connection with the refresh operation.

Some examples of the method600and the apparatus described herein may further include operations, features, circuitry, logic, means, or instructions for identifying a size of the first portion of the row based at least in part on a value stored at a memory device.

In some examples of the method600and the apparatus described herein, operations, features, circuitry, logic, means, or instructions for determining whether the row includes the data error may include operations, features, circuitry, logic, means, or instructions for performing an SEC procedure for at least a portion of data stored in the row.

In some examples of the method600and the apparatus described herein, operations, features, circuitry, logic, means, or instructions for determining whether the row includes the data error may include operations, features, circuitry, logic, means, or instructions for performing a single error correction (SEC) procedure for at least a portion of data stored in the row.