MV DEVICE AND METHOD FOR MANUFACTURING SAME

An MV device is disclosed. A gate conductive material layer is segmented into a body gate conductive material layer and two edge gate conductive material layers along a channel length direction. The two edge gate conductive material layers are located on two sides of the body gate conductive material layer and are spaced apart from the body gate conductive material layer by dielectric segmentation structures. The lightly doped drain regions extend under the first side face and the second side face of the gate conductive material layer, to reach under the body gate conductive material layer, such that the channel region becomes located under the body gate conductive material layer; and the edge gate conductive material layers and the dielectric segmentation structures become located above the lightly doped drain regions. The present disclosure also discloses a method for manufacturing an MV device.

CROSS-REFERENCES TO RELATED APPLICATIONS

This application claims the priority to Chinese patent application No. 202211129333.5, filed on Sep. 16, 2022, and entitled “MV DEVICE AND METHOD FOR MANUFACTURING SAME”, the disclosure of which is incorporated herein by reference in entirety.

TECHNICAL FIELD

The present disclosure relates to the field of semiconductor integrated circuit manufacturing, in particular to a medium voltage (MV) device. The present disclosure also relates to a method for manufacturing an MV device.

BACKGROUND

The high voltage (HV) IC device manufacturing process at the 28 nm note platform includes inserting medium and high voltage devices, i.e., a medium voltage device and a high voltage device, on a 28 nm HK platform. After inserting the medium and high voltage devices, a low voltage (LV) device, a medium voltage device, and a high voltage device are integrated together on the same semiconductor substrate. For example, a core device or SRAM device includes the LV device, and an input output (10) device includes the medium voltage device. A working voltage of the LV device reaches a few tenths of a volt or one plus a few tenths of a volt, a working voltage of the medium voltage device reaches several volts, such as 8V, and a working voltage of the high voltage device is higher. The provision of a field oxide is typically required in a drift region of the high voltage device. In an integrated process, the medium voltage device and the core/SRAM device share the same gate spacer, for example, an 8V MV and a 0.9V core/SRAM share the same spacer. Due to hard constraints of a pitch of the SRAM, the gate spacer cannot be too thick. In the present application, the thickness of the spacer refers to a lateral width of the gate spacer. As the result, a gate induced drain leakage (GIDL) in the MV device is severe.

Currently, in the industry, ways to improve the GIDL are mainly by adjusting a lightly doped drain (LDD) region of the MV device, but the improvement is limited with a very small process window.

FIGS.1A-1Dare schematic diagrams of cross sectional structures in various steps of an existing method for manufacturing an MV device. The existing method for manufacturing an MV device includes the following steps:

Step 1. Referring toFIG.1A, a semiconductor substrate101is provided, wherein two lightly doped drain regions102are formed in selected regions of the semiconductor substrate101.

A channel region103is located in a surface region of the semiconductor substrate101between the two lightly doped drain regions102.

Typically, a field oxide layer such as a shallow trench isolation (STI) is also formed on the semiconductor substrate101. The field oxide layer isolates an active region, that is, a region of the semiconductor substrate101surrounded by the field oxide layer forms the active region. A formation region of the MV device is located in a first active region101a, and the first active region101ais composed of the semiconductor substrate101in the region surrounded by the field oxide layer. Typically, an HV device and an LV device are integrated simultaneously on the semiconductor substrate101, and formation regions of the HV device and the LV device are located in respective active regions.

Step 2. Referring to1A, a gate dielectric layer104is formed on a surface of the semiconductor substrate101.

The grown gate dielectric layer104covers the entire surface of the semiconductor substrate101. Typically, after the growth of the gate dielectric layer104, a patterned etching process is required to retain the gate dielectric layer104in only the first active region101a. The gate dielectric layer104in the formation regions of the HV device and the LV device needs to be removed. Formation processes of the HV device and LV device are not described in detail in the description of the present application.

A first patterned etching is performed to form on the gate conductive material layer105, and the first patterned etching forms all side faces of the gate conductive material layer105. The gate conductive material layer105is located in only a formation region of a gate structure after the first patterned etching.

A first side face and a second side face of the gate conductive material layer105are two side faces located in a channel length direction.

A third side face and a fourth side face of the gate conductive material layer105are two side faces located in a channel width direction.

InFIG.2, the channel length direction corresponds to a horizontal direction in a plane shown inFIG.2, and the channel width direction corresponds to a vertical direction in the plane shown inFIG.2.

Step 4. Referring toFIG.1B, a spacer process is performed to form spacers106on all the side faces of the gate conductive material layer105.

The spacer process includes deposition of a spacer dielectric layer and a full etching process.

Step 5. Referring toFIG.1C, the gate dielectric layer104is etched using the spacers106as a self-alignment condition, so that a side face of the gate dielectric layer104is aligned with a side face of the spacers106.

Step 6. Referring toFIG.1D, a self-aligned source drain injection is performed to form source drain implantation regions107on surfaces of the lightly doped drain regions102outside the spacers106at a first side face and a second side face of the gate structure.

FIG.2is a schematic diagram of a top view structure of the MV device shown inFIG.1D, that is,FIG.2is a layout of the MV device made from the existing method. The spacers106typically are formed simultaneously with spacers of the LV device, and a pitch of the LV device is usually reduced, resulting in a thinner thickness of the spacers106, and thereby leading to poor GIDL leakage performance of the MV device.

According to some embodiments in this application, an MV device provided by the present disclosure includes:

a gate structure, wherein the gate structure comprises a gate dielectric layer disposed on a surface of a semiconductor substrate, a gate conductive material layer disposed on a surface of the gate dielectric layer, and a channel region disposed under the gate dielectric layer;spacers, disposed on a first side face and a second side face of the gate conductive material layer in a self-aligned manner, wherein the first side face and the second side face of the gate conductive material layer are disposed along the channel length direction of the channel region;lightly doped drain regions, disposed in the semiconductor substrate and outside the first side face and the second side face of the gate conductive material layer; andsource drain implantation regions, disposed on surfaces of the lightly doped drain regions away from the spacers of the gate conductive material layer.

The gate conductive material layer is segmented into a body gate conductive material layer and edge gate conductive material layers along the channel length direction.

The body gate conductive material layer is located in a middle region, wherein the edge gate conductive material layers are located on two sides of the body gate conductive material layer, and are spaced apart from the body gate conductive material layer by dielectric segmentation structures.

Each of the first side face and the second side face of the gate conductive material layer is an outer surface of one of the edge gate conductive material layers.

The channel region is located between the lightly doped drain regions in the surface of the semiconductor substrate.

In some cases, the dielectric segmentation structures are each composed of a dielectric layer filling a segmentation trench.

The segmentation trench is formed by etching the gate conductive material layer via a patterned etching process on each side face of the gate structure.

In some cases, the dielectric layer of the dielectric segmentation structure comprises a first dielectric layer, wherein the first dielectric layer and the spacers are formed in a simultaneous process.

In some cases, the width of the segmentation trench is less than or equal to twice the thickness of a bottom of one spacer, and wherein the first dielectric layer fills the segmentation trench;

Alternatively, the width of the segmentation trench is greater than twice the thickness of the bottom of the spacer, wherein the first dielectric layer does not fully fill the segmentation trench, and wherein the dielectric segmentation structure further comprises a second dielectric layer, wherein the second dielectric layer and the first dielectric layer together fill the segmentation trench.

In some cases, the first dielectric layer is an oxide layer, a nitride layer, or a stack layer of an oxide layer and a nitride layer.

The second dielectric layer is an oxide layer, a nitride layer, or a stack layer of an oxide layer and a nitride layer.

Materials of the first dielectric layer and the second dielectric layer are the same or different.

In some cases, a formation region of the MV device is located in a first active region, and the first active region is composed of the semiconductor substrate in a region surrounded by a field oxide layer.

A third side face and a fourth side face of the gate conductive material layer are two side faces located in a channel width direction, and along the channel width direction, the third side face and the fourth side face of the gate conductive material layer also extend to the top of the field oxide layer outside the first active region separately.

In some cases, a material of the gate dielectric layer comprises an oxide layer.

In some cases, a material of the gate conductive material layer comprises polysilicon.

In order to solve the above technical problem, the method for manufacturing an MV device provided by the present disclosure includes the following steps:step 1, providing a semiconductor substrate, forming two lightly doped drain regions in selected regions of the semiconductor substrate;forming a channel region in a surface of the semiconductor substrate between the two lightly doped drain regions;step 2, forming a gate dielectric layer on the surface of the semiconductor substrate;step 3, growing a gate conductive material layer on a surface of the gate dielectric layer;performing a first patterning on the gate conductive material layer to form side faces on the gate conductive material layer and a segmentation trench on each side; anddividing the gate conductive material layer into a body gate conductive material layer and two edge gate conductive material layers along a channel length direction, wherein the body gate conductive material layer is located in a middle region, the two edge gate conductive material layers are located on two sides of the body gate conductive material layer, and wherein the two edge gate conductive material layers each is spaced apart from the body gate conductive material layer by the segmentation trench;wherein a first side face and a second side face of the gate conductive material layer are outer surfaces of the edge gate conductive material layers and located along the channel length direction;wherein the lightly doped drain regions extend under the first side face and the second side face of the gate conductive material layer, to reach under the body gate conductive material layer, such that the channel region becomes located under the body gate conductive material layer; andwherein the edge gate conductive material layers and the dielectric segmentation structures become located above the lightly doped drain regions;step 4, forming spacers on side faces of the gate conductive material layer;step 5, filling each of the segmentation trench with a dielectric segmentation structure; andstep 6, forming source drain implantation regions in a self-aligned process on surfaces of the lightly doped drain regions outside the spacers away from the first side face and the second side face of the gate conductive material layer.

In some cases, in step 5, the dielectric segmentation structure comprises a first dielectric layer of the spacers, wherein the first dielectric layer is made in a same process as the spacers are made in step 4.

in ste In some cases, wherein a width of the segmentation trench is less than or equal to twice aa thickness of a bottom of the spacer, and wherein the first dielectric layer fills the segmentation trench to form the dielectric segmentation structure, and wherein step 4 and step 5 are implemented together.

In some cases, the width of the segmentation trench is greater than twice a thickness of a bottom of the spacer, wherein the first dielectric layer does not fully fill the segmentation trench and leaves a gap in the segmentation trench, and wherein step 5 further comprises: forming a second dielectric layer to fill the gap of the segmentation trench, wherein the first dielectric layer and the second dielectric layer are stacked in the segmentation trench.

In some cases, forming the second dielectric layer in step 5 is implemented after step 6; wherein the method further comprises fully filling the gap of the segmentation trench with a photoresist before step 6, and then performing step 6, followed by removing the photoresist from the segmentation trench.

In some cases, the first dielectric layer is an oxide layer, a nitride layer, or a stack layer of an oxide layer and a nitride layer.

The second dielectric layer is an oxide layer, a nitride layer, or a stack layer of an oxide layer and a nitride layer.

Materials of the first dielectric layer and the second dielectric layer are the same or different.

In some cases, a material of the gate dielectric layer comprises an oxide layer.

In some cases, a material of the gate conductive material layer comprises polysilicon.

Regarding the technical problem of the limited thickness of the spacers in the MV device, which is easy to cause a leakage such as a GIDL leakage, the present disclosure improves a process structure of the gate conductive material layer of the gate structure of the MV device. Along the channel length direction, the gate conductive material layer is segmented into the body gate conductive material layer located in the middle region and the edge gate conductive material layers located on the two sides of the body gate conductive material layer by means of the dielectric segmentation structures. The lightly doped drain regions extend laterally to a bottom region of the body gate conductive material layer, that is, the lightly doped drain regions overlap the body gate conductive material layer. As such, the entire region of the channel region between the lightly doped drain regions is covered by the body gate conductive material layer. Therefore, the introduction of the dielectric segmentation structures does not affect the conductivity of the channel region of the device, thereby maintaining a speed of the MV device.

The edge gate conductive material layers and the dielectric division structures are all located in top regions of the lightly doped drain regions, i.e., located in overlap regions of the lightly doped drain regions and the entire gate conductive material layer. As such, the thickness of an isolation layer between the body gate conductive material layer and the source drain implantation region is increased, which is equivalent to increasing the thickness of the spacers. Therefore, an electric field near the source drain implantation region is gentle, thus reducing a leakage current of the MV device, e.g., reducing a GIDL leakage current.

The dielectric segmentation structures of the present disclosure may be achieved by the dielectric layer filling the segmentation trench. The segmentation trench may be formed simultaneously with all the side faces of the gate conductive material layer during a first patterned etching process of the gate conductive material layer, thus requiring no additional lithography process for definition. Moreover, the dielectric layer filling the segmentation trench may also be achieved using the dielectric layer of the spacer process or by stacking the second dielectric layer on the dielectric layer of the spacer process. The second dielectric layer may also be conveniently integrated into a formation process of the dielectric layer following the source drain injection. Accordingly, the dielectric segmentation structures of the present disclosure require no additional process costs. Therefore, the present disclosure also has the advantages of a simple integration process and low process costs.

In addition, the present disclosure can also reduce a gate source capacitance and a gate drain capacitance.

DETAILED DESCRIPTION OF THE DISCLOSURE

FIG.3Dis a schematic diagram of a cross sectional structure of an MV device of an embodiment of the present disclosure.FIG.4is a schematic diagram of a top view structure of the MV device of an embodiment of the present disclosure. The MV device of this embodiment of the present disclosure includes:a gate structure, the gate structure formed by stacking a gate dielectric layer204formed on a surface of a semiconductor substrate201and a gate conductive material layer205.

In this embodiment of the present disclosure, a material of the gate dielectric layer204includes an oxide layer.

A material of the gate conductive material layer205includes polysilicon.

Spacers206are formed on all side faces of the gate conductive material layer205in a self-aligned manner. A first side face and a second side face of the gate conductive material layer205are two side faces located in a channel length direction. The cross sectional structure inFIG.3Dis a cross sectional structure along the channel length direction, so the two side faces of the gate conductive material layer205shown inFIG.3Dare the first side face and the second side face.

In this embodiment of the present disclosure, the gate dielectric layer204at the bottom of the spacers206is retained. In other embodiments, a side face of the gate dielectric layer204is directly aligned with a corresponding side face of the gate conductive material layer205at the top thereof, and the spacers206cover side faces of the gate dielectric layer204.

Lightly doped drain regions202are formed in the semiconductor substrate201outside the first side face and the second side face of the gate conductive material layer205.

Source drain implantation regions207are formed on surfaces of the lightly doped drain regions202outside the spacers206at the first side face and the second side face of the gate conductive material layer205. InFIG.3D, the source drain implantation regions207on two sides of the gate structure present a symmetrical structure, with one serving as a source region and the other as a drain region. The source region and the drain region are both represented by a mark207.

The gate conductive material layer205is segmented into a body gate conductive material layer2051and edge gate conductive material layers2052along the channel length direction. The body gate conductive material layer2051is located in a middle region, the edge gate conductive material layers2052are located on two sides of the body gate conductive material layer2051, and the edge gate conductive material layers2052are spaced apart from the body gate conductive material layer2051by dielectric segmentation structures2053.

The first side face and the second side face of the gate conductive material layer205are composed of outer side faces of the edge gate conductive material layers2052on the two sides of the body gate conductive material layer2051.

A channel region203is located in a surface region of the semiconductor substrate201between the lightly doped drain regions202on the two sides of the gate structure.

At the first side face and the second side face of the gate conductive material layer205, the lightly doped drain regions202also extend to the bottom of the body gate conductive material layer2051. An entire region of the channel region203is covered by the body gate conductive material layer2051, and the edge gate conductive material layers and the dielectric segmentation structures are all located at the top of the lightly doped drain regions202. As such, the top of the channel region203is not covered by the dielectric segmentation structures2053, so the channel conductivity of the MV device is not affected. Since the dielectric segmentation structure2053is located in an edge region of the top of the lightly doped drain regions202, which is equivalent to increasing the thickness of the spacers206, a leakage such as a GIDL leakage of the device may be reduced. The thickness of the spacers206refers to a lateral width of the spacers206.

In this embodiment of the present disclosure, the dielectric segmentation structures2053are each composed of a dielectric layer filling a segmentation trench301.

The segmentation trench301is formed by etching the gate conductive material layer205via a patterned etching process on each side face of the gate structure. Therefore, the formation of the segmentation trench301requires no additional process costs.

The dielectric layer of the dielectric segmentation structure2053includes a first dielectric layer, and process structures of the first dielectric layer and a dielectric layer of the spacers206are the same and formed simultaneously. As such, a formation process of the first dielectric layer of the dielectric segmentation structure2053likewise requires no additional costs.

In some embodiments, the width of the segmentation trench301is less than or equal to twice the thickness of the bottom of dielectric layer of the spacers206, the first dielectric layer fully fills the segmentation trench301, and the dielectric layer of the dielectric segmentation structure2053is composed of the first dielectric layer.

Alternatively, in other embodiments, the width of the segmentation trench301is greater than twice the thickness of the bottom of dielectric layer of the spacers206, the first dielectric layer does not fully fill the segmentation trench301, the dielectric layer of the dielectric segmentation structure2053further includes a second dielectric layer, and the second dielectric layer and the first dielectric layer fully fill the segmentation trench301jointly. The second dielectric layer may be formed separately or formed simultaneously with film layers such as an interlayer film in a subsequent interconnection process.

The first dielectric layer is an oxide layer, a nitride layer, or a stack layer of an oxide layer and a nitride layer.

The second dielectric layer is an oxide layer, a nitride layer, or a stack layer of an oxide layer and a nitride layer.

Materials of the first dielectric layer and the second dielectric layer are the same or different.

In this embodiment of the present disclosure, a formation region of the MV device is located in a first active region201a, and the first active region201ais composed of the semiconductor substrate201in a region surrounded by a field oxide layer. Typically, an HV device and an LV device are integrated simultaneously on the semiconductor substrate201, and formation regions of the HV device and the LV device are located in respective active regions. Each of the active regions is also composed of the semiconductor substrate201in a region surrounded by the field oxide layer.

Referring toFIG.4, a third side face and a fourth side face of the gate conductive material layer205are two side faces located in a channel width direction, and along the channel width direction, the third side face and the fourth side face of the gate conductive material layer205also extend to the top of the field oxide layer outside the first active region201aseparately. InFIG.4, the channel length direction is a horizontal direction in a plane shown inFIG.4, and the channel width direction is a vertical direction in the plane shown inFIG.4.

FIG.4only shows a schematic diagram of one top view structure of the MV device of this embodiment of the present disclosure. In other embodiments, under the condition of ensuring full separation of the body gate conductive material layer2051from the edge gate conductive material layers2052, a layout structure of the segmentation trench301may vary based onFIG.4.FIG.4Ais a schematic diagram of a top view structure of the MV device in another embodiment of the present disclosure. InFIG.4A, the body gate conductive material layer is represented separately by a mark2051a, the edge gate conductive material layers are represented separately by a mark2052a, and the segmentation trench is represented separately by a mark301a. It can be seen that, compared to the layout structure of the segmentation trench301inFIG.4, there is a change in the layout structure of the segmentation trench301inFIG.4A, mainly a change in a structure of the field oxide layer outside the first active region201a, However, the dividing groove301amay also fully separate the body gate conductive material layer2051afrom the edge gate conductive material layers2052a. Therefore, the layout structure shown inFIG.4Ais also applicable to the present application.

Regarding the technical problem of the limited thickness of the spacers206in the MV device, which is easy to cause a leakage such as a GIDL leakage, this embodiment of the present disclosure improves a process structure of the gate conductive material layer205of the gate structure of the MV device. Along the channel length direction, the gate conductive material layer205is segmented into the body gate conductive material layer2051located in the middle region and the edge gate conductive material layers2052located on the two sides of the body gate conductive material layer2051by means of the dielectric segmentation structures2053. The lightly doped drain regions202extend laterally to a bottom region of the body gate conductive material layer, that is, the lightly doped drain regions202overlap the body gate conductive material layer. As such, the entire region of the channel region203between the lightly doped drain regions202is covered by the body gate conductive material layer. Therefore, the introduction of the dielectric segmentation structures2053does not affect the conductivity of the channel region203of the device, thereby maintaining a speed of the MV device.

The edge gate conductive material layers2052and the dielectric division structures2053are all located in top regions of the lightly doped drain regions202, i.e., located in overlap regions of the lightly doped drain regions202and the entire gate conductive material layer205. As such, the thickness of an isolation layer between the body gate conductive material layer2051and the source drain implantation region207is increased, which is equivalent to increasing the thickness of the spacers206. Therefore, an electric field near the source drain implantation region207is gentle, thus reducing a leakage current of the MV device, e.g., reducing a GIDL leakage current.

The dielectric segmentation structures2053of this embodiment of the present disclosure may be achieved by the dielectric layer filling the segmentation trench301. The segmentation trench301may be formed simultaneously with all the side faces of the gate conductive material layer205during a first patterned etching process of the gate conductive material layer205, thus requiring no additional lithography process for definition. Moreover, the dielectric layer filling the segmentation trench301may also be achieved using the dielectric layer of the spacer process or by stacking the second dielectric layer on the dielectric layer of the spacer process. The second dielectric layer may also be conveniently integrated into a formation process of the dielectric layer following the source drain injection. Accordingly, the dielectric segmentation structures2053of this embodiment of the present disclosure require no additional process costs. Therefore, this embodiment of the present disclosure also has the advantages of a simple integration process and low process costs.

In addition, this embodiment of the present disclosure can also reduce a gate source capacitance and a gate drain capacitance.

FIG.5Ais a simulation data of an electric field intensity distribution of the MV device made with the existing method.FIG.5Bis a simulation data of an electric field intensity distribution of the MV device made with the method according to this embodiment of the present disclosure. InFIG.5AandFIG.5B, the simulation data are represented in greyscale colors, with the greyscale representing different electric field intensities. A region near the drain region inFIG.5Ais a region shown in a dashed line oblate401, and a region near the drain region inFIG.5Bis a region shown in a dashed line oblate402. The comparison shows that the electric field intensity distribution in the dashed line oblate402has good continuity, a smaller change magnitude, and a smoother change, leading to a reduction in the leakage of device.

FIG.6Ais a chart comparing the switch-on output characteristic curves of an MV device made from the existing method and an MV made according to an embodiment of the present disclosure. The MV device made from the existing method adopts the structure shown inFIG.1D. InFIG.6A, the MV device of this embodiment of the present disclosure and the MV device made from the existing method are both NMOSs having the same working voltage of 8 V and having the same working condition, i.e., both having the same gate voltage, with sources being grounded and gate source voltages being greater than threshold voltages. An output characteristic curve is a curve of a drain current changing with a drain voltage. A curve403is a switch-on output characteristic curve of the MV device made from the existing method, and a curve404is a switch-on output characteristic curve of the MV device of this embodiment of the present disclosure. It can be seen that curves403and404substantially coincide, indicating that threshold voltages as well as protection currents of both MV devices are substantially the same and operation speeds thereof are also substantially the same.

FIG.6Bis a chart comparing the switch-off output characteristic curves of an MV device made from the existing method and an MV made according to an embodiment of the present disclosure. InFIG.6B, the MV device made from a method of this embodiment of the present disclosure and the MV device made from the existing method e have the same gate voltage, with the sources grounded and the gate source voltages being less than the threshold voltages. A curve405is a switch-off output characteristic curve of the MV device made from existing method, and a curve406is a switch-off output characteristic curve of the MV device of this embodiment of the present disclosure. It can be seen that as the drain voltage increases, a drain current of the curve405increases quickly. At about 8 V, the drain current of the curve405is increased significantly. A drain current at a switch-off moment is a leakage current, and such the leakage current is mainly a GIDL leakage current. Therefore, this embodiment of the present disclosure can reduce the GIDL leakage.

FIGS.3A-3Dare schematic diagrams of cross sectional structures in various steps of a method for manufacturing an MV device of this embodiment of the present disclosure. The method for manufacturing an MV device of this embodiment of the present disclosure includes the following steps:

Step 1. Referring toFIG.3A, a semiconductor substrate201is provided, wherein two lightly doped drain regions202are formed in selected regions of the semiconductor substrate201.

A channel region203is located in a surface region of the semiconductor substrate201between the two lightly doped drain regions202.

In the method of this embodiment of the present disclosure, a field oxide layer such as a shallow trench isolation (STI) is also formed on the semiconductor substrate201. The field oxide layer isolates an active region, that is, a region of the semiconductor substrate201surrounded by the field oxide layer forms the active region. A formation region of the MV device is located in a first active region201a, and the first active region201ais composed of the semiconductor substrate201in the region surrounded by the field oxide layer. Typically, an HV device and an LV device are integrated simultaneously on the semiconductor substrate201, and formation regions of the HV device and the LV device are located in respective active regions.

Step 2. Referring toFIG.3A, a gate dielectric layer204is formed on a surface of the semiconductor substrate201.

The grown gate dielectric layer204covers the entire surface of the semiconductor substrate201. Typically, after the growth of the gate dielectric layer204, a patterned etching process is required to retain the gate dielectric layer204in only the first active region201a. The gate dielectric layer204in the formation regions of the HV device and the LV device needs to be removed. Formation processes of the HV device and LV device are not described in detail in the description of the present application.

In the method of some embodiments, a material of the gate dielectric layer204includes an oxide layer.

In the method of some embodiments, a material of the gate conductive material layer205includes polysilicon.

A first patterned etching is performed on the gate conductive material layer205, and the first patterned etching forms all side faces of the gate conductive material layer205and a segmentation trench301simultaneously.

The gate conductive material layer205is segmented into a body gate conductive material layer2051and edge gate conductive material layers2052along a channel length direction. The body gate conductive material layer2051is located in a middle region, the edge gate conductive material layers2052are located on two sides of the body gate conductive material layer2051, and the edge gate conductive material layers2052are spaced apart from the body gate conductive material layer2051by the segmentation trench301.

A first side face and a second side face of the gate conductive material layer205are two side faces located in the channel length direction and are composed of outer side faces of the edge gate conductive material layers2052on the two sides of the body gate conductive material layer2051.

At the first side face and the second side face of the gate conductive material layer205, the lightly doped drain regions202also extend to the bottom of the body gate conductive material layer2051, an entire region of the channel region203is covered by the body gate conductive material layer2051, and the edge gate conductive material layers2052and the segmentation trench301are all located at the top of the lightly doped drain regions202.

Step 4. Referring toFIG.3B, a spacer process is performed to form spacers206on all the side faces of the gate conductive material layer205.

The spacer process includes deposition of a spacer dielectric layer and a full etching process.

Step 5. Referring toFIG.3B, the segmentation trench301is filled with a dielectric layer to form a dielectric segmentation structure2053.

In the method of this embodiment of the present disclosure, in step 5, the dielectric layer of the dielectric segmentation structure2053comprises a first dielectric layer, and the first dielectric layer is a dielectric layer of the spacers206. A formation process of the first dielectric layer is merged into step 4 and uses the spacer process in step 4 for formation.

In some embodiments, the width of the segmentation trench301is less than or equal to twice the thickness of the bottom of dielectric layer of the spacers206, and the first dielectric layer fully fills the segmentation trench301and constitutes the dielectric segmentation structure2053. Step 4 and step 5 are combined and implemented together.

In the method of this embodiment of the present disclosure, the first dielectric layer is an oxide layer, a nitride layer, or a stack layer of an oxide layer and a nitride layer;

The second dielectric layer is an oxide layer, a nitride layer, or a stack layer of an oxide layer and a nitride layer.

Materials of the first dielectric layer and the second dielectric layer are the same or different.

In the method of this embodiment of the present disclosure, the method further includes: referring toFIG.3C, etching the gate dielectric layer204using the spacers206as a self-alignment condition, so that a side face of the gate dielectric layer204is aligned with a side face of the spacers206. In the method of other embodiments, the bottom gate dielectric layer204is also etched during the first patterned etching in step 3, so that the bottom of the segmentation trench301also penetrates through the gate dielectric layer204. After the spacers206are formed, the spacers206cover side faces of the gate dielectric layer204. After the filling, the dielectric segmentation structure2053also penetrates through the gate dielectric layer204.

Step 6. A self-aligned source drain injection is performed to form source drain implantation regions207on surfaces of the lightly doped drain regions202outside the spacers206at the first side face and the second side face of the gate conductive material layer205.

In other embodiments, the width of the segmentation trench301is greater than twice the thickness of the bottom of dielectric layer of the spacers206. The first dielectric layer does not fully fill the segmentation trench301and forms a gap in the segmentation trench301. Step 5 further includes:forming a second dielectric layer to fully fill the gap of the segmentation trench301, wherein the dielectric segmentation structure2053is formed by stacking the first dielectric layer and the second dielectric layer filling the segmentation trench301.

In an improved method of other embodiment, a formation process of the second dielectric layer in step 5 is implemented after step 6. The method further includes fully filling the gap of the segmentation trench301using a photoresist before step 6, and then step 6 is performed, followed by removing the photoresist in the segmentation trench301. The formation process of the second dielectric layer in step 5 may be implemented after step 6, and a deposition process of the dielectric layer after step 6 may be used to simultaneously form the second dielectric layer. For example, a deposition process of an interlayer film is used to form the second dielectric layer, thereby saving costs of the formation process of the second dielectric layer.

The present disclosure is described in detail above via specific embodiments, but these embodiments are not intended to limit the present disclosure. Without departing from the principle of the present disclosure, those skilled in the art can still make many variations and improvements, which should also be construed as falling into the protection scope of the present disclosure.