Chip packaging structure with heat dissipation layer, flange and sealing pin

Disclosed a chip packaging structure and a manufacturing method thereof. The chip packaging structure comprises: a metal heat dissipation layer; a chip structure comprising a plurality of first electrical contacts on an upper surface of the chip structure; a pin layer comprising a plurality of second electrical contacts and a plurality of separate metal bumps; an encapsulant encapsulating at least one portion of the chip structure, the metal heat dissipation layer and the pin layer, wherein at least one portion of the pin layer is exposed to an upper surface of the encapsulant, and an lower surface of the metal heat dissipation layer is exposed outside the encapsulant. The metal heat dissipation layer includes a flange on the side surface for tightly combining the metal heat dissipation layer and the encapsulant.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims priority to the Chinese Patent Application No. 201711387769.3, filed on Dec. 20, 2017, entitled “chip packaging structure and manufacturing method thereof”, which is incorporated herein by reference in its entirety.

BACKGROUND OF THE DISCLOSURE

Field of the Disclosure

The present disclosure relates to the semiconductor field, and more particularly, to a chip packaging structure and a manufacturing method thereof.

Background of the Disclosure

In a chip structure according to the prior art, a wire-bonding structure or a flip-chip structure is generally used for packaging, and since there is no design for heat dissipation therein, the contact between chips and environment outside the chips becomes a natural heat dissipation path. However, with the progress of science and technology, advanced processes make it possible to produce smaller chips with more complex functions, and as a result, the spaces between pins of the chip packages must be reduced accordingly. Relatively, each pin has to withstand more thermal energy, which is generated by chip operations. After a long-term operation, a large amount of thermal energy is accumulated on the pins, which will damage normal operations of the chips. A typical damage is caused by a phenomenon called electron migration, which is prone to occur on the pins. In addition, the packaging and manufacturing processes by use of the wire-bonding structure or the flip-chip structure is complex, which results in relatively high manufacturing cost.

Therefore, for the process of semiconductor technology, it is essential to provide a chip packaging structure with high heat-dissipation efficiency, which can be made by simple manufacturing process.

SUMMARY OF THE DISCLOSURE

The present disclosure has solved the problem by providing a chip packaging structure and a manufacturing method thereof, wherein a pin layer or a redistribution layer is formed by using a pattern plating process, so that on the premise that the performance of the chip packaging structure is guaranteed, the manufacturing process is simplified and the manufacturing cost is reduced.

According to one aspect of the disclosure, there is provided a chip packaging structure comprising: a metal heat dissipation layer; a chip structure located on an upper surface of the metal heat dissipation layer and comprising a plurality of first electrical contacts on an upper surface of the chip structure; a pin layer comprising a plurality of second electrical contacts and a plurality of separate metal bumps, wherein the plurality of second electrical contacts are located on lower surfaces of the plurality of metal bumps, and the plurality of second electrical contacts are coupled to the plurality of first electrical contacts of the chip structure through a plurality of conductive pillars; and an encapsulant encapsulating at least one portion of the chip structure, the metal heat dissipation layer and the pin layer, wherein at least one portion of the pin layer is exposed to an upper surface of the encapsulant, and a lower surface of the metal heat dissipation layer is exposed outside the encapsulant.

Preferably, the metal heat dissipation layer comprises a flange on its side surface.

Preferably, the flange of the metal heat dissipation layer extends in a direction perpendicular to the side surface of the metal heat dissipation layer and the flange is located inside the encapsulant.

Preferably, the flange of the metal heat dissipation layer extends in a direction parallel to the side surface of the metal heat dissipation layer and the flange is configured to surround the side surface of the metal heat dissipation layer.

Preferably, the chip packaging structure further comprises a sealing pin located on an upper surface of the flange and extending to a periphery of the upper surface of the encapsulant, so that, the metal heat dissipation layer, the flange and the sealing pin form a cavity for housing the encapsulant.

Preferably, an upper surface of the sealing pin and an upper surface of the pin layer are at a same height.

Preferably, the chip packaging structure further comprises a redistribution layer located between the chip structure and pin layer, wherein the redistribution layer extends in a direction parallel to the upper surface of the chip structure, the distribution layer is configured to couple the plurality of first conductive contacts located at a center of the upper surface of the chip structure to the plurality of second electrical contacts of the pin layer through the plurality of conductive pillars, and the plurality of second electrical contacts are located above a center of the chip structure, or above an edge of the chip structure.

Preferably, the plurality of conductive pillars comprise: first conductive pillars configured to electrically couple a lower surface of the redistribution layer to the chip structure; and second conductive pillars configured to electrically couple an upper surface of the redistribution layer to a lower surface of the pin layer.

Preferably, the chip packaging structure further comprises an insulating layer located on the lower surface of the metal heat dissipation layer.

Preferably, the upper surface of the metal heat dissipation layer is connected with the chip structure through an adhesive layer.

Preferably, the encapsulant comprises a first encapsulant and a second encapsulant, the second encapsulant is located on the first encapsulant, the first encapsulant encapsulates the chip structure and the metal heat dissipation layer, and the second encapsulant encapsulates the redistribution layer.

According to another aspect of the disclosure, there is provided a manufacturing method for a chip packaging structure comprising: arranging a metal heat dissipation layer on a substrate, wherein the metal heat dissipation layer comprises a flange on its side surface; attaching a chip structure on an upper surface of the metal heat dissipation layer by using an adhesive layer; forming an encapsulant encapsulating an upper surface of the substrate, the metal heat dissipation layer, the chip structure and a plurality of electrode connection structures; performing mechanical or chemical treatment, to make upper surfaces of the plurality of electrode connecting structures exposed outside the first encapsulant; and arranging a pin layer for electrically coupling to and covering the upper surfaces of the plurality of electrode connection structures.

Preferably, the flange of the metal heat dissipation layer extends perpendicular to the side surface of the metal heat dissipation layer.

Preferably, the step of arranging a pin layer for electrically coupling to and covering the upper surfaces of the plurality of the electrode connection structures comprises: forming a first encapsulant for encapsulating the upper surface of the substrate, the metal heat dissipation layer, the chip structure, and the plurality of electrode connection structures, and exposing the upper surfaces of the plurality of the electrode connection structures; forming a redistribution layer by using a pattern plating process, and coupling the redistribution layer to the upper surfaces of the plurality of electrode connection structures; forming a second encapsulant for encapsulating the redistribution layer; performing perforation or etching, so that at least one portion of an upper surface of the redistribution layer is exposed outside the second encapsulant; and arranging the pin layer for electrically coupling to and covering the exposed portion of the upper surface of the redistribution layer by using a pattern plating process.

Preferably, the flange of the metal heat dissipation layer extends in a direction parallel to the side surface of the metal heat dissipation layer.

Preferably, the manufacturing method comprises: forming the encapsulant for encapsulating the upper surface of the substrate, the metal heat dissipation layer, the chip structure, and the plurality of electrode connection structures, and exposing the upper surfaces of the plurality of electrode connection structures and the upper surface of the flange; and arranging the pin layer for electrically coupling to and covering the upper surfaces of the plurality of electrode connection structures, and arranging a sealing pin for coupling to and covering the upper surface of the flange.

Preferably, the manufacturing method further comprises: forming a first encapsulant for encapsulating the upper surface of the substrate, the metal heat dissipation layer, the chip structure and the plurality of electrode connection structures, and exposing the upper surfaces of the plurality of electrode connection structures and the upper surface of the flange; forming a redistribution layer coupling the redistribution layer to the upper surfaces of plurality of the electrode connection structures by a pattern plating process, and making the flange grow; forming a second encapsulant for encapsulating the redistribution layer and the flange; performing perforation or etching, so that, at least one portion of an upper surface of the redistribution layer and the upper surface of the flange is exposed outside the second encapsulant; arranging the pin layer for electrically coupling to and covering an exposed portion of the redistribution layer, making the flange re-grow, and forming the sealing pin for coupling to and covering the upper surface of the flange, by using a pattern plating process.

Preferably, the manufacturing method further comprises arranging a sealing pin on the upper surface of the flange, the upper surface of the flange and the upper surface of the redistribution layer are at a same height, and an upper surface of the sealing pin and an upper surface of the pin layer are at a same height.

Preferably, the manufacturing method further comprises: removing the substrate and forming an insulating layer on a lower surface of the metal heat dissipation layer.

According to the chip packaging structure of the present disclosure, the pin layer or the redistribution layer are formed by adopting a pattern plating process, and on the premise that the performance of the chip packaging structure is guaranteed, the manufacturing process can be simplified and the manufacturing cost can be reduced. By exposing at least one portion of the metal heat dissipation layer located below the chip structure outside the encapsulant, the heat dissipation performance of the entire chip packaging structure is improved. Extending the redistribution layer in a direction parallel to the upper surfaces of the chip structures is equivalent to increasing a layout area of the electrodes of chip. The electrodes of chip are led above the edge of the chip structure so that the spaces between the external pins are increased. As a result, the abnormal accidents, such as contacts causing a failure on the chip packaging structure, are less likely to happen.

According to one embodiment of the disclosure, the metal heat dissipation layer comprises the flange extending in a direction perpendicular to the side surface of the metal heat dissipation layer, so that the surface area of the metal heat dissipation layer is increased, which can not only further improve the heat dissipation performance of the chip packaging structure, but also enhance the combination force between the metal heat dissipation layer and the encapsulant.

According to another embodiment of the disclosure, the metal heat dissipation layer comprises the flange extending in a direction parallel to the side surface of the metal heat dissipation layer, the flange is configured to surround the side surface of the encapsulant, the metal heat dissipation layer, the flange and the sealing pin form the cavity accommodating the encapsulant, which can not only further improve the heat dissipation performance of the chip packaging structure, but also enhance the combination force between the metal heat dissipation layer and the encapsulant. In addition, a sealing ring formed by the metal heat dissipation layer, the flange and the sealing layer has a good electromagnetic shielding performance, and a good airtightness performance. In applications requiring electromagnetic shielding, the chip packaging structure can be widely used to replace metal cans and ceramic packages in the prior art.

DETAILED DESCRIPTION OF THE DISCLOSURE

Exemplary embodiments of the present disclosure will be described in more details below with reference to the accompanying drawings. In the drawings, like reference numerals denote like members. The figures are not drawn to scale, for the sake of clarity. In addition, some well-known parts may not be shown in the figures.

Many specific details of the present disclosure are described below, such as the structures, materials, dimensions, processes, and techniques of the parts, in order to more clearly understand the present disclosure. However, one skilled in the art will understood that the present disclosure may be practiced without these specific details.

It should be understood that when one layer or region is referred to as being “above” or “on” another layer or region in the description of device structure, it can be directly above or on the other layer or region, or other layers or regions may be intervened therebetween. Moreover, if the device in the figures is turned over, the layer or region will be “under” or “below” the other layer or region.

In contrast, when one layer is referred to as being “directly on” or “on and adjacent to” or “adjoin” another layer or region, there are not intervening layers or regions present. In the present application, when one region is referred to as being “directly in”, it can be directly in another region and adjoins another region, but not in an implantation region of another region.

In the present application, the term “semiconductor structure” means generally the whole semiconductor structure formed at each step of the method for manufacturing the semiconductor device, including all of the layers and regions having been formed. The term of “laterally extending” is referring to extending in a direction substantially perpendicular to the depth direction of the groove.

Many specific details of the present disclosure are described below, such as the structures, materials, dimensions, processes, and techniques of the parts, in order to more clearly understand the present disclosure. However, one skilled in the art will understood that the present disclosure may be practiced without these specific details.

The present disclosure may be presented in various forms, some of which will be described below.

FIG. 1ashows a cross-sectional diagram of a chip packaging structure according to a first embodiment of the present disclosure.

As shown inFIG. 1a, a chip structure140is located on an upper surface of a metal heat dissipation layer120, and the chip structure140is attached to the upper surface of the metal heat dissipation layer120by using an adhesive layer130. The chip structure140comprises a plurality of first electrical contacts141on the upper surface of the chip structure140. A redistribution layer170is located over the chip structure140and is electrically coupled to the first electrical contacts141of the chip structure140by using a plurality of conductive pillars180. A pin layer150is located on the redistribution layer170. The pin layer150includes a plurality of metal bumps and a plurality of second electrical contacts151. The plurality of second electrical contacts151are located below lower surfaces of the plurality of metal bumps. The plurality of second electrical contacts151are electrically coupled to the upper surface of the redistribution layer170by using the plurality of conductive pillars180. The redistribution layer170extends in a direction parallel to the upper surface of the chip structure140. The redistribution layer170is configured to couple the first electrical contacts141located at the center of the upper surface of the chip structure140to the second electrical contacts151of the pin layer150through the conductive pillars180. The second conductive contacts151are located above the center of the chip structure140or above the edge of the chip structure140. The plurality of conductive pillars180includes first conductive pillars180aand second conductive pillar180b. The first conductive pillars180ais configured to electrically couple the lower surface of the redistribution layer170to the chip structure140, and the second conductive pillars180bis configured to electrically couple the upper surface of the redistribution layer170to the lower surface of the pin layer150. An encapsulant160encapsulates chip structure140, the metal heat dissipation layer120, the redistribution layer170and at least one portion of pin layer150. At least one portion of the pin layer150is exposed to the upper surface of the encapsulant160, and the lower surface of the metal heat dissipation layer120is exposed outside the encapsulant160. Specifically, the encapsulant160includes a first encapsulant160aand a second encapsulant160b. The second encapsulant160bis located on the first encapsulant160a. The first encapsulant160aencapsulates chip structure140and at least one portion of metal heat dissipation layer120. The second encapsulant160bencapsulates the redistribution layer170.

Extending the redistribution layer170in a direction parallel to the upper surface of the chip structure, the layout area of the electrodes of chip is equivalent to be increased. The electrodes of chip are led above the edge of the chip structure140so that the spaces between the external pins are increased. As a result, the abnormal accidents, such as contacts causing a failure on the chip packaging structure, are less likely to happen.

The redistribution layer170in the present embodiment is an alternative structure. If the redistribution layer170is not provided in the embodiment, the chip structure140can be directly and electrically coupled to the second electrical contacts151of the pin layer150through the plurality of conductive pillars180.

The metal heat dissipation layer120includes a flange121on its side surface. The flange121extends in a direction perpendicular to the side surface of the metal heat dissipation layer120. The flange121is located in the encapsulant160and is used for tightly combining the metal heat dissipation layer120and the encapsulant160with each other. In the embodiment, the flange121of the metal heat dissipation layer120can be two, which can be distributed up and down, and a groove is formed between the two flanges121. The groove can be filled with the encapsulant160to further improve the heat dissipation of the chip packaging structure and enhance the combination between the metal heat dissipation layer120and the encapsulant160.

FIGS. 1bto 1jshow cross-sectional diagrams of various stages of a manufacturing method for the chip package structure according to the first embodiment of the present disclosure.

As shown inFIG. 1b, the metal heat dissipation layer120is attached to the upper layer of the substrate110by using the adhesive layer. The metal heat dissipation layer120includes the flange121on the side surface. The flange121extends in a direction perpendicular to the side surface of the metal heat dissipation layer120. The extension length of the flange121is not beyond the side surface of the substrate110. The metal heat dissipation layer120in the embodiment may be made of copper, aluminum, or other suitable materials.

Next, as shown inFIG. 1c, the chip structure140is attached to the upper surface of the metal heat dissipation layer120by using the adhesive layer130. The upper surface of the chip structure140has a plurality of electrode connection structures for leading out the electrodes of chip. The structure and components of the electrode connection structures can take a variety of forms. In the present embodiment, the electrode connection structures include a plurality of first electrical contacts141on the upper surface and a plurality of first conductive pillars180arranged on the first electrical contacts141. The adhesive layer130may be made of an insulating adhesive material, for example, epoxy resin. The insulating adhesive material can be added on the metal heat dissipation layer120by using a dispensing process to form an epoxy resin with a certain thickness to ensure the chip performance. The adhesive layer130may also be made of a conductive adhesive material, which be electrically connected to the metal heat dissipation layer120, and has good heat dissipation.

Next, as shown inFIG. 1d, the first encapsulant160ais formed to encapsulate the upper surface of the substrate110, the metal heat dissipation layer120, the chip structure140, and the plurality of first conductive pillars180a. The material of the first encapsulant160amay be polyimide, silicone or epoxy, or other suitable material. The first encapsulant160amay be made by a compression molding process, a transfer molding process, a liquid sealing molding process, or other suitable process.

Next, as shown inFIG. 1e, the upper surfaces of the plurality of first conductive pillars180alocated on the upper surface of the chip structure140are exposed to the upper surface of the first encapsulant160aby a mechanical process such as grinding or drilling, and the upper surfaces of the plurality of first conductive pillars180aand the upper surface of the first encapsulant160aare located in a same plane.

Next, as shown inFIG. 1f, the redistribution layer170is formed on the upper surfaces of the plurality of first conductive pillars180aand the upper surface of the first encapsulant160aby a pattern plating process or other suitable process, so that the chip structure140is electrically coupled to the lower surface of the redistribution layer170through the plurality of first conductive pillars180a. Alternatively, the pin layer is formed on the upper surfaces of the plurality of first conductive pillars180aand the upper surface of the first encapsulant160aby a pattern plating process or other suitable process, so that the chip structure140is electrically coupled to the pin layer through the plurality of first conductive pillars180a. The step of pattern plating process includes: firstly, a first metal layer is formed on the upper surfaces of the plurality of first conductive pillars180aand the upper surface of the first encapsulant160aby using a deposition process, and then a second metal layer is formed on the first metal layer by using an electroplating process.

Next, as shown inFIG. 1g, the second encapsulant160bis formed to encapsulate the redistribution layer170. The second encapsulant160bis located on the first encapsulant160a. The first encapsulant160aand the second encapsulant160bform the encapsulant160. The first encapsulant160aand the second encapsulant160bmay be made of a same material.

Next, as shown inFIG. 1h, at least one portion of the upper surface of the redistribution layer170is exposed outside the second encapsulant160bby drilling or etching, and the upper surface of the second encapsulant160bis higher than the upper surface of the redistribution layer170.

Next, as shown inFIG. 1i, the second conductive pillars180band the pin layer150are formed at the same time by a process such as the above-mentioned pattern plating process or the like. The pin layer150is located on the second conductive pillars180b. The second conductive pillars180bare located inside a through-hole of the second encapsulant160band are coupled to the exposed portion of the upper surface of the redistribution layer170by the second encapsulant160b, so that the chip structure140is electrically coupled to the pin layer150through the redistribution layer170. The pin layer150may be made of a plurality of separate metal bumps.

Next, as shown inFIG. 1j, the substrate110and the adhesive layer between the substrate110and the metal heat dissipation layer120are removed, so that the lower surface of the metal heat dissipation layer120is exposed outside the first encapsulant160a.

Next, as shown inFIG. 1a, insulation layer190is formed on the lower surface of the metal heat dissipation layer120by using chemical treatment or physical coating, such as vapor deposition. The insulation layer190is used to electrically insulate the lower surface of the metal heat dissipation layer120, to prevent static electrons from generating and it is made of a material having a good thermal conductivity, for example, it may be made of polyimide, silicone or epoxy resin, or other suitable material.

In the first embodiment of the present disclosure, the metal heat dissipation layer120arranges the flange extending in a direction perpendicular to the side surface of the metal heat dissipation layer120, so that the surface area of the metal heat dissipation layer120is increases, which can not only further improve the heat dissipation of the chip packaging structure, but also enhance the combination force between the metal heat dissipation layer120and the encapsulant160.

FIG. 2ashows a cross-sectional diagram of a chip package structure according to a second embodiment of the present disclosure.

Referring toFIG. 2a, a chip structure240is located on an upper surface of a metal heat dissipation layer220, and the chip structure240is attached to the upper surface of the metal heat dissipation layer220by using an adhesive layer230. The chip structure240includes a plurality of first electrical contacts241on the upper surface of the chip structure240. A redistribution layer270is located on the chip structure240and is electrically coupled to the first electrical contacts241of the chip structure240through a plurality of conductive pillars280. A pin layer250is on the redistribution layer270. The pin layer250includes a plurality of metal bumps and a plurality of second electrical contacts251. The plurality of second electrical contacts251are located below lower surfaces of the plurality of metal bumps. The second electrical contacts251are electrically coupled to the upper surface of the redistribution layer270through the plurality of conductive pillars280. The redistribution layer270extends in a direction parallel to the upper surface of the chip structure240. The redistribution layer270couple the first electrical contact241located on the center of the upper surface of the chip structure240to the second electrical contacts251of the pin layer located at the center and/or the edge of the upper surface of the chip structure240through the conductive pillars280. The plurality of conductive pillars280includes first conductive pillars280aand second conductive pillars280b. The first conductive pillars280ais configured to electrically couple the lower surface of the redistribution layer270to the chip structure240, and the second conductive pillar280bis configured to electrically couple the upper surface of the redistribution layer270to the lower surface of the pin layer250. The encapsulant260encaplates all of the entire chip structure240, the upper surface of the metal heat dissipation layer220, entire redistribution layer270, and at least one portion of the pin layer250. The encapsulant260may be located on the upper surface of the metal heat dissipation layer220. The lower surface of the220is exposed outside the encapsulant260, and at least one portion of the pin layer250is exposed to the upper surface of the encapsulant260. Specifically, the encapsulant260includes a first encapsulant260aand a second encapsulant260b. Second encapsulant260bis located on the first encapsulant260a. The first encapsulant260aencapsulates the chip structure240, and the second encapsulant260bencapsulates the redistribution layer270.

Extending the redistribution layer270in a direction parallel to the upper surface of the chip structure240is equivalent to increasing the layout area of electrodes. The electrodes of chip are led above the edge of the chip structure240so that the spaces between the external pins are increased. Therefore, abnormal accidents, such as contacts causing a failure on the chip packaging structure, are less likely to happen.

The redistribution layer270in the present embodiment is an alternative structure. If the redistribution layer270is not provided in the embodiment, the chip structure240can be directly coupled to the second electrical contacts251of the pin layer250through the plurality of conductive pillars280.

The metal heat dissipation layer220includes flanges221on the side surface. The flanges221are configured to extend in a direction parallel to the side surface of the metal heat dissipation layer220and surround the side surface of the encapsulant260. Sealing pins222are located on the upper surface of the flanges221and extend to the periphery of the upper surface of the encapsulant260. The upper surface of the sealing pins222and the upper surface of the pin layer250are at a same height. The metal heat dissipating layer220, the flanges221and the sealing pins222form a cavity for accommodating encapsulant260. The encapsulant260is located in the cavity, and the encapsulant260and one portion of the upper surface of the metal heat dissipation layer220, the inner side surface of the flanges221, and one portion of the lower surface of the sealing pins222are connected, thereby improving the heat dissipation performance of the chip package structure and enhancing the combination force between the metal heat dissipation layer220and the encapsulant260. The sealing pins222and the flanges221of the metal heat dissipation layer220may be made of same material.

FIGS. 2bto 2ishow cross-sectional diagrams of various stages of a manufacturing method for the chip package structure according to the second embodiment of the present disclosure.

As shown inFIG. 2b, the metal heat dissipation layer220is attached to the upper surface of the substrate210through an adhesive layer. The metal heat dissipation layer220includes the flanges221on the side surface. The flanges221are configured to extend in a direction parallel to the side surface of the metal heat dissipation layer220, so that the metal heat dissipation layer220and the flanges221form a cavity. The metal heat dissipation layer220in the embodiment may be made of copper, aluminum, or other suitable materials.

Next, as shown inFIG. 2c, the chip structure240is attached to the upper surface of the metal heat dissipation layer220through the adhesive layer230. The chip structure240includes a plurality of first electrical contacts241on the upper surface, and a plurality of first conductive pillars280aare arranged on the first electrical contacts241. The upper surface of the first conductive pillars280aand the upper surface of the flanges221are at a same height. The adhesive layer230may be made of an insulating adhesive material, for example, epoxy resin. The insulating adhesive material may be added on the metal heat dissipation layer220by using a dispensing process to form an epoxy resin with a certain thickness, so that the chip performance is ensured. The adhesive layer230may also be made of a conductive adhesive material, which is electrically coupled to the metal heat dissipation layer220for achieving good heat dissipation performance.

Next, as shown inFIG. 2d, the first encapsulant260ais formed to encapsulate the upper surface of the substrate210and all of the metal heat dissipation layer220, the chip structure240, and the plurality of first conductive pillars280a. The material of the first encapsulant260amay be polyimide, silicone or epoxy resin, or other suitable material. The first encapsulant260amay be made by a compression molding process, a transfer molding process, a liquid sealing molding process, or other suitable process.

Next, as shown inFIG. 2e, the upper surfaces of the plurality of first conductive pillars280alocated on the upper surface of the chip structure240and the upper surface of the flanges221are exposed to the upper surface of the first encapsulant260aby a mechanical process such as grinding or drilling. Preferably, the upper surfaces of the plurality of first conductive pillars280a, the upper surface of the flanges221, and the upper surface of the first encapsulant260aare in a same plane.

Next, as shown inFIG. 2f, the redistribution layer270is formed on the upper surfaces of the plurality of first conductive pillars280aand the upper surface of the first encapsulant260aby using a pattern plating process or other suitable process, so that the chip structure240is electrically coupled to the lower surface of the redistribution layer270through the plurality of first conductive pillars280a. The flanges221are configured to grow by using the pattern plating process or other suitable process. Preferably, after growth the upper surface of the flange221and the upper surface of the redistribution layer270are at a same height. Alternatively, the pin layer is formed on the upper surfaces of the plurality of first conductive pillars280aand the upper surface of the first encapsulant260aby using the pattern plating process or other suitable method, so that the chip structure240is electrically coupled to the pin layer through the plurality of first conductive pillars280a. The step of pattern plating process includes: firstly, a first metal layer is formed on the upper surfaces of the plurality of first conductive pillars280aand the upper surface of the first encapsulant260athrough a deposition process; and then a second metal layer is formed on the first metal layer through an electroplating process.

Next, as shown inFIG. 2g, the second encapsulant260bis formed to encapsulate the redistribution layer270and the flanges221. The second encapsulant260bis located on the first encapsulant260a. The first encapsulant260aand the second encapsulant260bform the encapsulant260.

Next, as shown inFIG. 2h, a through-hole is formed in the second encapsulant by drilling or etching, so that at least one portion of the upper surface of the redistribution layer270and the upper surface of the flanges221are exposed outside the second encapsulant260b, and the upper surface of the second encapsulant260bis higher than the upper surface of the redistribution layer270and the upper surface of the flanges221.

Next, as shown inFIG. 2i, the second conductive pillars280band the pin layer250are formed at the same time by the above-mentioned processes such as the pattern plating process. The pin layer250is located on the second conductive pillars280b. The second conductive pillars280bare located in the through-hole of the second encapsulant260band are coupled to the exposed portion of the upper surface of the redistribution layer270outside the second encapsulant260b, so that the chip structure240is electrically coupled to the pin layer250through the redistribution layer270. The pin layer250may be formed of a plurality of separate metal bumps. The flanges221are configured to grow again by using a pattern plating process or other suitable process. Preferably, after re-growth, the upper surface of flanges221, the upper surfaces of the second encapsulant260band the second conductive pillars280bare at a same height. The sealing sealing pins222are formed on the upper surface of the flange221and extends to the periphery of the upper surface of the encapsulant260. The upper surface of the sealing pin222and the upper surface of the pin layer250are at a same height. The metal heat dissipation layer220, the flanges221, and the sealing pins222form a cavity for accommodating the encapsulant260. The encapsulant260is located in the cavity, and the encapsulant260is connected with one portion of the upper surface of the metal heat dissipation layer220, the inner side surface of the flanges221, and one portion of the lower surface of the sealing pins222.

Next, as shown inFIG. 2a, the substrate210, the adhesive layer between the substrate210and the metal heat dissipation layer220, and the encapsulant260on the outer side surface of the flanges221are removed, so that the lower surface of the metal heat dissipation layer220and the outer side surface of the flanges221are exposed outside the encapsulant260. A protective layer is formed on the lower surface of the metal heat dissipation layer220and the outer side surface of the flanges221by chemical treatment or physical coating, such as vapor deposition. The protective layer may be formed of an inert metal, such as Ni, Au, to prevent the exposed metal heat dissipation layer220and the flanges221from being oxidized.

In the second embodiment of the present disclosure, at the edge of the metal heat dissipation layer220, the flanges221extends in a direction parallel to the side surface of the metal heat dissipation layer220. The flanges221are configured to surround the side surface of the encapsulant260. The metal heat dissipation layer220, the flanges221and the sealing pins222form a cavity for accommodating encapsulant260, which can further improve the heat dissipation performance, the electromagnetic shielding performance, and the airtightness of the chip package structure, and can strengthen the combination force between the metal heat dissipation layer220and the encapsulant260. Therefore, the reliability of the chip product is improved, which can be widely used to replace metallic or ceramic package structures.

According to the chip packaging structure of the present disclosure, the pin layer or the distribution layer are formed by adopting the pattern plating process, and on the premise that the performance of the chip packaging structure is guaranteed, the manufacturing process can be simplified, so that the manufacturing cost is reduced. By exposing at least one portion of the metal heat dissipation layer below the chip structure outside the encapsulant, the heat dissipation performance of the entire chip packaging structure is improved. In addition, the chip packaging structure of the present embodiment is entirely sealed with a metal package, so that it has good-looking appearance and product reliability.

It should also be understood that the relational terms such as “first”, “second”, and the like are used in the context merely for distinguishing one element or operation form the other element or operation, instead of meaning or implying any real relationship or order of these elements or operations. Moreover, the terms “comprise”, “comprising” and the like are used to refer to comprise in nonexclusive sense, so that any process, approach, article or apparatus relevant to an element, if follows the terms, means that not only said element listed here, but also those elements not listed explicitly, or those elements inherently included by the process, approach, article or apparatus relevant to said element. If there is no explicit limitation, the wording “comprise a/an . . . ” does not exclude the fact that other elements can also be included together with the process, approach, article or apparatus relevant to the element.

Although various embodiments of the present disclosure are described above, these embodiments neither present all details, nor imply that the present disclosure is limited to these embodiments. Obviously, many modifications and changes may be made in light of the teaching of the above embodiments. These embodiments are presented and some details are described herein only for explaining the principle of the disclosure and its actual use, so that one skilled person can practice the present disclosure and introduce some modifications in light of the disclosure. The disclosure is intended to cover alternatives, modifications and equivalents that may be included within the spirit and scope of the disclosure as defined by the appended claims.