Risc type microprocessor and information processing apparatus

A RISC type microprocessor for implementing multi-stage pipeline processing. The RISC type microprocessor includes mode allocating means, interrupt controlling means and a jump instruction table. The mode allocating means is used for allocating a first mode for cyclically executing processes corresponding to a plurality of interrupts at predetermined intervals or a second mode for successively executing the processes corresponding to the interrupts. The interrupt controlling means is used for controlling the interrupts corresponding to the mode allocated by the mode allocating means, and is operable to save particular information to a stack upon occurrence of an interrupt and to fetch the particular information from the stack upon completion of the interrupt process. The jump instruction table is used in processing interrupts without stopping the multi-stage pipeline processing.

BACKGROUND OF THE INVENTION
 1. Field of the Invention
 The present invention relates to information processing systems, and in
 particular, to a one-chip microcomputer which employs RISC technology to
 execute interrupt processing and numeric operations at high speed.
 2. Description of the Prior Art
 Conventional RISCs (Reduced Instruction Set Computers) have been developed
 as engines for computers mainly to increase the speed of arithmetic
 operations. The instruction length of the RISCs is normally 32 bits,
 fixed.
 In a one-chip microcomputer employing RISC, since the code efficiency is
 low, interrupt processing is performed by another chip. Thus, the speed of
 the interrupt processing is low. In addition, with a conventional one-chip
 microcomputer, arithmetic operations cannot be performed at high speed.
 OBJECTS AND SUMMARY OF THE INVENTION
 The present invention is made in view of the above problems. The invention
 employs RISC technology in a one-chip microcomputer so as to allow both
 interrupt processing and arithmetic operations to be performed at high
 speed.
 In one illustrative embodiment of the invention, a RISC type microprocessor
 for implementing multi-stage pipeline processing is provided. The RISC
 type microprocessor includes mode allocating means, interrupt controlling
 means and a jump instruction table. The mode allocating means is used for
 allocating a first mode for cyclically executing processes corresponding
 to a plurality of interrupts at predetermined intervals or a second mode
 for successively executing the processes corresponding to the interrupts.
 The interrupt controlling means is used for controlling the interrupts
 corresponding to the mode allocated by the mode allocating means, and is
 operable to save particular information to a stack upon occurrence of an
 interrupt and to fetch the particular information from the stack upon
 completion of the interrupt process. The jump instruction table is used in
 processing interrupts without stopping the multi-stage pipeline
 processing.
 The above, and other, objects, features and advantages of the present
 invention will become readily apparent from the following detailed
 description thereof which is to be read in connection with the
 accompanying drawings.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
 FIG. 1 shows a structure of a one-chip microcomputer employing a RISC type
 microprocessor according to an embodiment of the present invention. A RISC
 (Reduced Instruction Set Computer) 1 included in the one-chip
 microcomputer can input eight external interrupts, a nonmaskable interrupt
 nmi, and a power management interrupt pmi. In addition, the RISC 1 can
 input a reset signal and a clock signal from the outside.
 When the reset signal is input to the RISC 1, it executes a program stored
 in an IPL (Initial Program Loader)-ROM 3. When this program is executed, a
 memory controller 6 gets started through a register of a coprocessor
 (co_pro) 2. Thus, an operating system is loaded from an auxiliary storing
 unit (not shown) to a code buffer 4, a data buffer 5, and a main memory
 (not shown).
 FIG. 2 shows an example of the structure of the RISC 1 shown in FIG. 1. In
 the RISC 1, 32 16-bit fixed-length general purpose registers 11 are
 provided. A bypass circuit 12 (information supplying means) causes flag
 information corresponding to the executed result of a comparison
 instruction to be immediately used in the next conditional branch
 instruction.
 An ALU (Arithmetic and Logic Unit) 13 is composed of a barrel shifter or
 the like. The ALU performs a predetermined logic operation and an
 arithmetic operation. A high speed multiplying device/high speed dividing
 device 14 executes a multiplying process for multiplying 16-bit data by
 16-bit data in one cycle, a dividing process for dividing 32-bit data by
 16-bit data in 13 cycles, and a dividing process for dividing 16-bit data
 by 16-bit data in eight cycles.
 An address calculating portion 15 calculates an address using a program
 counter or the like. An instruction decoder/pipeline controlling portion
 16 (decoding means) interprets instructions read from the memory (e.g.
 16-bit fixed length instructions) and performs a pipeline process with a
 five-staged pipeline.
 11 16-bit dedicated control registers 17 (mode allocating means) are
 provided. The dedicated control registers 17 store status information
 (flag information), interrupt control information, and so forth. An
 interrupt controller 18 controls an interrupt process corresponding to the
 interrupt control information stored in the dedicated control register 17.
 A reset/clock controlling portion 19 generates a reset signal and a clock
 signal and supplies these signals to each portion of the RISC 1.
 FIG. 3 shows a register map of the one-chip microcomputer shown in FIG. 1.
 In this case, two coprocessors (COP0 and COP1) are used. As can be seen
 from the figure, the RISC (CPU) 1 has 32 general purpose registers. 32
 control registers of the first coprocessor (COP0) 2 are used (mapped) as
 internal control registers for the CPU. Thus, the user can use only the
 remaining 32 control registers. In addition, the user can use 64 control
 registers of the second coprocessor (COP1) (not shown in FIG. 1) without
 any restriction.
 The general purpose registers can be used as registers for arithmetic
 operations other than special instructions. A register ACC (R1) can be
 used for an immediate operand and an operand in a bit process. As an
 exception, a register SP (R30) can be used as a stack pointer for a "RET"
 instruction. A register ISP (R31) can be used as a stack pointer for an
 interrupt process, an exception process, and a "RETI" instruction. The
 initial values of these general purpose registers (including the register
 ACC, the register SP, and the register ISP) are undefined.
 As shown in FIG. 3, a total of 128 registers of registers G31 to G0 and C31
 to C0 of the first coprocessor (COP0) 2 and registers G31 to G0 and C31 to
 C0 of the second coprocessor (COP1) can be used. Data transfer among the
 registers of the coprocessors, the general purpose registers, and the
 memory is defined by instructions.
 A total of 96 registers of the registers C31 to C0 of the first coprocessor
 and the registers G31 to G0 and C31 to C0 of the second coprocessor can be
 used as external extension registers. 11 of the registers G31 to G0 of the
 first coprocessor function as control registers for the CPU. The remaining
 21 registers are reserved.
 An SR (Status Register) stores a flag corresponding to the result of an
 arithmetic operation or the like. An MCR (Machine Control Register) is
 used for machine control. For example, data that allocates 32-bit
 divisions is stored in the MCR. An IBR (Interrupt Base Register) stores
 the base address of an interrupt vector table. A JBR (Jump Base Register)
 is used when a special jump instruction is executed and a branch is
 performed. An ICR (Interrupt Control Register) is used for an interrupt
 control. The ICR structures a three-level interrupt stack.
 An IMR0 (Interrupt Mode Register 0) is used for external interrupt mode
 control. For example, a "round robin" mode or "fixed" mode (described
 later) is set by the IMR0. An IMR1 (Interrupt Mode Register 1) is used for
 categorizing eight external interrupts as groups. A DAB0 (Data Address
 Break 0) is used for storing a break address of a data buffer. An IAB1
 (Instruction Address Break 1) is used for storing a break address of an
 instruction buffer. An IAB2 (Instruction Address Break 2), is used for
 storing a break address of an instruction buffer. An XDDD (Extended Divide
 Dividend) is used for storing high order 16 bits of a 32-bit dividend when
 an extended division instruction is executed.
 Each of the first coprocessor and the second coprocessor has around 30
 operation codes that the user can use. These operation codes can be easily
 executed by a "DW" instruction of the assembler. The CPU supports an
 exception process of which the coprocessors are not used. The hardware of
 the coprocessors can be simulated by software.
 FIG. 4 shows an example of the structure of an address space of the RISC 1.
 64 Kbytes can be used for instructions and 64 Kbytes can be used for data.
 To exchange data between the RISC 1 and the external coprocessors, a
 96-word external register can be used. When the RISC 1 receives an
 external reset, the control branches to FF60H and executes an instruction
 stored therein. Vector addresses are allocated every two words (four
 bytes). At the first word, a branch (jump) instruction is set. At the
 second word that is a delay slot, a "nop" (no operation) instruction or
 another instruction is set.
 The base address of the vector address is the value stored in the register
 IBR (high order eight bits). The vector address can be set to any location
 within 256 bytes. An offset value to be branched is set at the vector
 address. Corresponding to the offset value and the base address stored in
 the register IBR (for example, by ORing them), the address to be branched
 is obtained.
 FIGS. 5A to 5G show examples of formats of instructions used in the
 one-chip microcomputer shown in FIG. 1. FIG. 5A shows the format of an MOV
 instruction. The length of the instruction is 16 bits fixed. This format
 is of two-operand type composed of an operation code (OP_CODE) and two
 operands (SCR1/DEST1, SRC2). Since the instruction length is 16 bits
 fixed, the code efficiency is improved.
 FIG. 5B shows the format of an LSI type instruction (immediate
 instruction). FIG. 5C shows the format of a SHIFT type instruction (shift
 instruction). FIG. 5D shows the format of a SYSCALL type instruction
 (branch instruction). FIG. 5E shows the format of a CFC type instruction
 (coprocessor transfer instruction). FIG. 5F shows the format of a JMP type
 instruction (branch instruction). FIG. 5G shows the format of an LI type
 instruction (immediate instruction).
 In addition, a bit process instruction is provided. With the bit process
 instruction, for example, a bit inverting process can be easily performed.
 Thus, when the one-chip microcomputer is used as a controller, the process
 can be effectively performed. Moreover, with the above-described immediate
 instruction, the code efficiency can be further improved.
 FIG. 6 shows operations of a five-staged pipeline as implemented using an
 instruction bus 8, a data bus 9, and a coprocessor bus 7 (transfer means).
 As shown in FIG. 1, the instruction bus 8, the data bus 9, and the
 coprocessor bus 7 are independently structured. In addition, data
 input/output of these buses is independently performed. Each bus is
 connected by an external cache (buffer) and a register of the coprocessor
 2.
 When the bus width is 16 bits, even if such buses are independently
 structured, the total bus width is not large. Thus, as described above,
 the coprocessor bus 7 can be separated from the data bus so as to remove
 the restrictions of the extended coprocessors. Since the coprocessor bus 7
 is separated from the data bus 9, as shown in FIG. 6, a load process or a
 store process of the coprocessor 2 can be performed independently from a
 conventional load process or a store process of the RISC 1. Thus, the
 coprocessor 2 can be released from a critical path. Consequently, the
 coprocessor 2 can freely use the bus (coprocessor bus 7).
 The instruction decoder/pipeline controlling portion 16 determines whether
 an instruction latched on the instruction bus 8 is issued to the RISC 1 or
 the coprocessor 2 when the signal level of the clock signal supplied from
 the reset/clock controlling portion 19 becomes low. When the instruction
 is issued to the RISC 1, the RISC 1 executes the instruction. When the
 instruction is issued to coprocessor 2, the operation corresponding to the
 instruction is performed by the hardware of the coprocessor 2. At this
 point, the RISC 1 does not perform any process.
 FIG. 7 shows timings at which individual buses can be used after an
 instruction is decoded. Thus, the coprocessor 2 can freely use the
 coprocessor bus 7.
 In addition, as the coprocessor 2, the first coprocessor (COP0) and the
 second coprocessor (COP1) can be used. With a RISC instruction, data can
 be transferred between the coprocessors and the general purpose registers
 and between the coprocessors and the memory.
 In the 16-bit fixed length RISC processor, to effectively process an
 interrupt without stopping the five-staged pipeline, a jump instruction
 table is preferably used instead of a so-called interrupt vector table. In
 the address space shown in FIG. 4, as described above, vector addresses
 are set every four bytes. A 96-byte movable instruction table is formed.
 In the table, 24 exceptions can be defined. One exception is defined with
 four bytes. In two bytes (one word) of the four bytes, a jump instruction
 is set. The remaining two bytes (one word) are used as a delay slot. In
 the delay slot, a no-operation instruction or another instruction is set.
 As shown in FIG. 4, only three instruction exceptions, seven internal
 exceptions, two non-maskable interrupts, and eight external interrupts are
 defined. These exceptions and interrupts can be effectively controlled.
 In addition, external interrupts can be defined as follows. In other words,
 the eight external interrupts can be allocated in the "round robin" mode
 or the "fixed" mode. In the "round robin" mode, when the initial value is
 set to 0, the interrupts are cyclically processed in the order of
 interrupt numbers 0, 1, 2, . . . , 7, 0, . . . and so forth at
 predetermined intervals. In this mode, when the initial value is set to 1,
 the interrupts are cyclically processed in the order of the interrupt
 numbers 1, 2, 3, . . . , 7, 0, 1, . . . and so forth at the predetermined
 intervals.
 In the "fixed" mode, when the initial value is set to 0, the interrupts are
 successively processed in the order of the interrupt numbers 0, 1, 2, . .
 . , and 7. In this mode, when the initial value is set to 1, the
 interrupts are successively processed in the order of the interrupt
 numbers 1, 2, 3, . . . , 7, and 0.
 Alternatively, the eight external interrupts can be categorized as two
 groups, "high" and "low". In each of the "high" group and the "low" group,
 the eight interrupts can be allocated priority. In the "high" group or the
 "low" group, the "round robin" mode or the "fixed" mode can be
 independently allocated.
 In the case that the "round robin" mode is allocated to the four external
 interrupts in the "high" group, when the initial value is set to 4, the
 interrupts are cyclically processed in the order of the interrupt numbers
 4, 5, 6, 7, 4, 5, . . . and so forth at the predetermined intervals. In
 this case, when the initial value is set to 5, the interrupts are
 cyclically processed in the order of the interrupt numbers 5, 5, 7, 4, 5,
 6, . . . and so forth at the predetermined intervals.
 In the case that the "fixed" mode is allocated to the four external
 interrupts in the "high" group, when the initial value is set to 4, the
 interrupts are successively processed in the order of the interrupt
 numbers 4, 5, 6, and 7. In this case, when the initial value is set to 5,
 the interrupts are successively processed in the order of the interrupt
 numbers 5, 6, 7, and 4.
 In the case that the "round robin" mode is allocated to the four external
 interrupts in the "low" group, when the initial value is set to 0, the
 interrupts are cyclically processed in the order of the interrupt numbers
 0, 1, 2, 3, 0, . . . and so forth at the predetermined intervals. In this
 case, when the initial value is set to 1, the interrupts are cyclically
 processed in the order of the interrupt numbers 1, 2, 3, 0, 1, . . . and
 so forth at the predetermined intervals.
 In the case that the "fixed" mode is allocated to the four external
 interrupts in the "low" group, when the initial value is set to 0, the
 interrupts are successively processed in the order of the interrupt
 numbers 0, 1, 2, and 3. In this case, when the initial value is set to 1,
 the interrupts are successively processed in the order of the interrupt
 numbers 1, 2, 3, and 0.
 When an interrupt process is executed with the register R31 as the ISP
 (Interrupt Stack Pointer) as shown in FIG. 3, interrupts can be managed in
 multiple levels. In other words, when an interrupt takes place, the PC
 (Program Counter) is saved to a stack so as to prohibit an external
 interrupt. Thus, the interrupt process can be performed at high speed. In
 addition, a support circuit for a RET1 (Return Interrupt) instruction and
 three-leveled interrupts is provided. In other words, a three-leveled
 interrupt stack is provided. For example, regions of several bits are
 formed in the register G3 (ICR) of the COP0 shown in FIG. 3. With these
 regions, the three-leveled interrupt stack is formed. Whenever an
 interrupt is executed, the values of these regions are shifted.
 In a 32-bit fixed length RISC, a conventional conditional branch
 instruction is executed as one instruction. In a classic CISC, after a
 comparison instruction is executed, a conditional branch instruction is
 executed. Thus, the execution time of the comparison instruction and the
 conditional branch instruction is remarkably long. This is because the
 conditional branch is performed with a defined value in the flag register
 corresponding to the compared result of the comparison instruction.
 On the other hand, in a 16-bit fixed length RISC, since the instruction
 length is short, a conditional branch instruction cannot be executed as
 one instruction. Thus, after the comparison instruction is executed, the
 branch instruction is executed.
 The 16-bit fixed length RISC 1 uses a five-staged pipeline. When a defined
 value in the flag register is used, after the comparison instruction is
 executed, until the conditional branch instruction is executed, a pipeline
 delay takes place. To prevent the pipeline delay, a flag corresponding to
 the result of the comparison instruction is generated by the bypass
 circuit 12 so that the result of the comparison instruction can be
 immediately used for the branch instruction. Thus, the conditional branch
 operation can be performed at high speed.
 FIG. 8 shows the structure of a five-staged pipeline. As shown in FIG. 8,
 the five-staged pipeline is composed of an IF (instruction fetch) stage,
 an RF (register fetch) stage, an ALU (arithmetic operation) stage, an MEM
 (memory transfer) stage, and a WB (register write back) stage. When the
 conditional branch instruction is executed, the latest updated flag of the
 pipeline of which the value in the flag register is not defined is used.
 The flag is supplied from the above-described bypass circuit. When the ALU
 is executed, it is determined whether or not the latest flag is valid.
 When the latest flag is valid, the result is read. When the MEM is
 executed, if the latest flag is valid, data that has been loaded or stored
 is used. In such a manner, in each stage of the pipeline, it is determined
 whether the flag is valid.
 FIGS. 9A to 9G show examples of formats of microcodes as an application of
 the formats of 16-bit fixed length instructions. (Generally, microcodes
 are copyright protected, whereas binary codes of CPU instructions are not
 copyright protected.) In the case of the RISC, the instruction scheme is
 formatted as microcode. When several bits (for example, four bits) are
 added to an instruction of the RISC and used for multiple purposes,
 complete formats of microcodes are obtained. The bits 15 to 0 of the
 16-bit fixed instructions are the instruction scheme of the RISC.
 By adding several bits (bit -1 to -4) to a 16-bit fixed length instruction,
 the hardware connected to the CPU (RISC) 1 can be controlled for multiple
 purposes. Thus, the instructions of the RISC can be used as microcodes
 with a bit length of 17 bits to 20 bits.
 To realize a complicated RISC instruction set, a PLA (Programmable Logic
 Array) or the like may be used. However, normally, microcodes are used.
 The formats of the microcodes allow the data bus to effectively work. On
 the other hand, the instruction scheme of the RISC is composed of fixed
 length instructions and it can be treated as formats of microcodes. By
 slightly modifying the instruction scheme of the RISC, a complicated CISC
 instruction set can be realized. In other words, the instruction scheme of
 the RISC allows the data bus to effectively work.
 Thus, as shown in FIG. 10, with the RISC instruction set, the data bus can
 be directly controlled. On the other hand, in the case of the CISC
 instruction set, an instruction is analyzed. Next, the top address of a
 microcode is calculated. The calculated address is supplied to a
 predetermined microcode and then executed. In the microcode format,
 several bits added to the RISC instruction set are for example an
 instruction end bit. In such a manner, the data bus is controlled.
 FIG. 11 shows an example of the structure of a one-chip microcomputer for
 use with a GPS (Global Positioning System). The one-chip microcomputer has
 the above-described RISC type microprocessor, a satellite receiving LSI, a
 RAM, and a ROM that are integrated in one chip. A boot ROM/target ROM
 debugger 33 of the one-chip microcomputer (GPS_LSI) 31 is composed of a
 boot ROM and a target ROM debugger. The boot ROM stores a boot program
 that is executed when the power of the one-chip microcomputer is turned
 on. The target ROM debugger stores a debugger program that is used to
 perform a debugging operation.
 A data RAM 34 stores various types of data necessary for executing various
 processes. A dual port RAM 35 stores data received from a host computer
 (not shown) through a bus 39. In addition, the dual port RAM 35 stores
 data to be sent to the host computer. An instruction RAM/ROM 36 stores
 particular application programs, control programs, and so forth. By
 connecting a PC (Personal Computer) 38 to an SIO (Serial Input/Output) 37,
 programs stored in the instruction RAM/ROM 36 can be debugged.
 FIG. 12 shows an example of the structure of a GPS receiving system as an
 application of the information processing apparatus according to the
 present invention. An antenna 41 receives a radio wave from a GPS
 satellite (not shown) and supplies a signal of the radio wave to a band
 pass filter 42. The band pass filter 42 passes only a predetermined
 frequency of the input signal. An amplifier 43 amplifies the output signal
 of the band pass filter and supplies the resultant signal to a multiplying
 device 46.
 The multiplying device 44 multiplies the output signal of the amplifier 43
 by a C/A code supplied form a C/A (Clear and Acquisition) code generator
 55 and supplies the resultant signal to a band pass filter 45. The band
 pass filter 45 passes only a predetermined frequency of the output signal
 of the multiplying device 44. A multiplying device 46 multiplies the
 output signal of the band pass filter 45 by the output signal of a
 frequency multiplying device 53 (described later) and supplies the
 resultant signal to a band pass filter 47. The band pass filter 47 passes
 only a predetermined frequency of the output signal of the multiplying
 device 46. A multiplying device 48 multiplies the output signal of the
 band pass filter 47 by the output signal of a frequency multiplying device
 54 (described later). A band pass filter 49 passes only a predetermined
 frequency of the output signal of the multiplying device 48.
 A synchronous tracking circuit 50 is composed of a PLL or the like. The
 synchronous tracking circuit 50 detects synchronization and outputs a
 synchronous detection signal and a reproduced carrier wave. A noise
 detection filter 51 detects and removes noise contained in the input
 signal. A synchronous acquiring circuit 52 generates a clock signal
 corresponding to the synchronous detection signal and the reproduced
 carrier wave and supplies the clock to the C/A code generator 55. The
 frequency multiplying devices 53 and 54 extract higher harmonics of the
 input signals, amplify the extracted higher harmonics, and supply the
 resultant signals to the multiplying devices 46 and 48, respectively. The
 C/A code generator 55 generates a C/A code (namely, PN (Pseudo-Noise)
 code) in synchronization with the clock signal supplied from the
 synchronous acquiring circuit 52.
 Next, the operation of the GPS receiving system will be described. The GPS
 radio wave transmitted form the GPS satellite is received by the antenna
 41. The GPS radio wave is converted into a predetermined signal. The
 resultant signal is amplified by the amplifier 43 and then supplied to the
 multiplying device 44. The GPS satellite multiplies the carrier wave by
 the C/A code so as to spread the spectrum. Thus, the receiving side should
 multiply the received signal by the same C/A code as that of the GPS
 satellite so as to obtain a narrow band signal. In other words, the
 multiplying device 44 multiplies the output signal of the amplifier 43 by
 the C/A code generated by the C/A code generator 55 and supplies the
 resultant signal to the band pass filter 45.
 The band pass filter 45 passes only a predetermined frequency of the output
 signal of the multiplying device 44. The resultant signal is supplied to
 the multiplying device 46. The multiplying device 46 multiplies the output
 signal of the band pass filter 45 by the output signal of the frequency
 multiplying device 53 and supplies the resultant signal to the band pass
 filter 47. The band pass filter 47 passes only a predetermined frequency
 of the output signal of the multiplying device 46 and supplies the
 resultant signal to the multiplying device 48.
 The multiplying device 48 multiplies the output signal of the band pass
 filter 47 by the output signal of the frequency multiplying device 54 and
 supplies the resultant signal to the band pass filter 49. The band pass
 filter 49 passes only a predetermined frequency of the output signal of
 the multiplying device 48 and supplies the resultant signal to the
 synchronous tracking circuit 50. The output signal of the synchronous
 tracking circuit 50 is supplied to the noise detection filter 50. The
 noise detection filter 50 removes noise contained in the output signal of
 the synchronous tracking circuit 50. The resultant signal is supplied to
 the synchronous tracking circuit 50 once again. The synchronous tracking
 circuit 50 tracks the synchronization of the output signal of the input
 signal and outputs the synchronous detection signal and the reproduced
 carrier wave.
 The synchronous detection signal and the reproduced carrier wave that are
 output from the synchronous tracking circuit 50 are supplied to the
 synchronous acquiring circuit 52. The synchronous acquiring circuit 52
 generates a clock signal with a predetermined frequency corresponding to
 the synchronous detection signal and the reproduced carrier wave supplied
 from the synchronous tracking circuit 50 and supplies the clock signal to
 the C/A code generator 55. The C/A code generator 55 generates the C/A
 code in synchronization with the clock signal and supplies the C/A code to
 the multiplying device 44. At this point, the phase of the C/A code
 supplied from the C/A code generator 55 is slightly shifted so that the
 phase of the C/A code matches the phase of the received signal.
 In such a manner, the received signal is converted into a base band signal
 and demodulated data is obtained. The demodulated data is supplied from
 the synchronous tracking circuit 50 to the CPU (not shown).
 The above-described GPS receiving system can be realized with one chip. The
 chip can be used as the satellite receiving LSI 32 shown in FIG. 11.
 In this case, the signal received from the GPS satellite to the satellite
 receiving LSI 32 is supplied to the RISC 1. The RISC 1 executes
 predetermined arithmetic operations corresponding to the signal supplied
 from the satellite receiving LSI 32 at high speed and measures the present
 location of the GPS receiving system. Thereafter, the RISC 1 reads map
 information corresponding to the present location from a CD-ROM or the
 like, converts the map information into picture data, and displays a map
 corresponding to the picture data on a CRT (not shown). In addition, the
 RISC 1 can perform two-dimensional or three-dimensional code conversion
 for the picture data corresponding to the traveling direction of the GPS
 receiving system or a user's operation. Moreover, when the GPS receiving
 system approaches an intersection, the RISC 1 can synthesize a particular
 sound signal and output it at a proper timing.
 As described above, when the RISC 1 and the satellite receiving LSI 32 are
 integrated in one chip, a navigation system can be accomplished with one
 chip. In addition, with the one-chip structure, the cost of the system can
 be reduced. Moreover, the power consumption of the system can be
 suppressed.
 In the above-described embodiment, the number of stages of the pipeline is
 five. However, the number of stages of the pipeline is not limited to
 five.
 In the above-described embodiment, the instruction length is 16 bits fixed.
 However, another fixed bit length may be used.
 In the above-described embodiment, when an instruction of the RISC 1 is
 used as a microcode, the number of bits newly added is four. However, any
 number of bits may be added.
 In the above-described embodiment, an example of the structure of the
 one-chip microcomputer using the RISC processor that can be used in the
 GPS receiving system is shown. However, the present invention is not
 limited to the GPS receiving system.
 Indeed, the present invention can be applied for a game machine, a portable
 information communication unit, a multimedia unit such as a KARAOKE unit,
 and other types of units.
 Having described specific preferred embodiments of the present invention
 with reference to the accompanying drawings, it is to be understood that
 the invention is not limited to those precise embodiments, and that
 various changes and modifications may be effected therein by one skilled
 in the art without departing from the scope or the spirit of the invention
 as defined in the appended claims.