Semiconductor device

A gate electrode is formed in a trench formed in a semiconductor substrate. A gate interlayer insulating film is formed to cover the gate electrode and the like. A gate interconnection and an emitter electrode are formed in contact with the gate interlayer insulating film. A glass coating film and a polyimide film are formed to cover the gate interconnection and the emitter electrode. A solder layer is formed to cover the polyimide film. The gate interconnection and the emitter electrode are each formed of a tungsten film, for example.

TECHNICAL FIELD

The present invention relates to semiconductor devices, and more particularly to a power semiconductor device.

BACKGROUND ART

A semiconductor device having a trench gate structure is one form of a power semiconductor device. In a power semiconductor device, a semiconductor element such as a MOSFET (Metal Oxide Semiconductor Field Effect Transistor), an IGBT (Insulated Gate Bipolar Transistor), or a SiC-MOSFET is formed on a semiconductor substrate. An interconnection (for example, a gate interconnection and the like) and an electrode (for example, an emitter electrode and the like) for operating such a semiconductor element are formed in the semiconductor device.

The interconnection and the electrode are disposed at a distance from each other. A protective film is formed to cover a region located between the interconnection and the electrode. Further, a solder layer is formed to cover the protective film. PTD 1 and PTD 2 are examples of patent documents disclosing this type of semiconductor device.

CITATION LIST

Patent Documents

SUMMARY OF INVENTION

Technical Problem

In a conventional semiconductor device, a semiconductor element generates heat during ON operation, and the heat of the semiconductor element is released during OFF operation. A solder layer has a higher coefficient of thermal expansion than that of a protective film. Thus, in the semiconductor device, repeated expansion and contraction of the solder layer causes high stress to act on the protective film. When the stress acts on the protective film, relatively high stress also acts on the interconnection, the electrode or the like covered by the protective film.

When the relatively high stress acts on the interconnection, the electrode or the like, the interconnection disposed at a distance from the electrode may slide into contact with the electrode due to the stress, for example, causing electrical shorting between the interconnection and the electrode.

The present invention was made to solve the aforementioned problem, and has an object to provide a semiconductor device capable of preventing electrical shorting between electric conductors such as an interconnection and an electrode.

Solution to Problem

A first semiconductor device according to the present invention includes a semiconductor substrate, an insulating film, a first electric conductor, a second electric conductor, a protective film, and a solder layer. The insulating film is formed to cover the semiconductor substrate. The first electric conductor is formed on the insulating film. The second electric conductor is formed on the insulating film at a distance from the first electric conductor. The protective film is formed to cover the first electric conductor and the second electric conductor. The solder layer is formed to cover the protective film. The first electric conductor and the second electric conductor each have a Young's modulus of 300 GPa or more.

A second semiconductor device according to the present invention includes a semiconductor substrate, an insulating film, a first electric conductor, a second electric conductor, an embedded body, a protective film, and a solder layer. The insulating film is formed to cover the semiconductor substrate. The first electric conductor is formed on the insulating film. The second electric conductor is formed on the insulating film at a distance from the first electric conductor. The embedded body is formed to fill space between the first electric conductor and the second electric conductor. The protective film is formed to cover the first electric conductor, the second electric conductor and the embedded body. The solder layer is formed to cover the protective film.

A third semiconductor device according to the present invention includes a semiconductor substrate, an insulating film, a first electric conductor, a second electric conductor, a protective film, and a solder layer. The insulating film is formed to cover the semiconductor substrate. The first electric conductor is formed on the insulating film. The second electric conductor is formed on the insulating film at a distance from the first electric conductor. The protective film is formed to cover the first electric conductor and the second electric conductor. The solder layer is formed to cover the protective film. The first electric conductor and the second electric conductor are each provided with an inclined portion.

A fourth semiconductor device according to the present invention includes a semiconductor substrate, an insulating film, a first electric conductor, a second electric conductor, a protective film, and a solder layer. The insulating film is formed to cover the semiconductor substrate. The first electric conductor is formed on the insulating film. The second electric conductor is formed on the insulating film at a distance from the first electric conductor. The protective film is formed to cover the first electric conductor and the second electric conductor. The solder layer is formed to cover the protective film. An upper surface of the second electric conductor is located lower than a lower surface of the first electric conductor.

A fifth semiconductor device according to the present invention includes a semiconductor substrate, an insulating film, a first electric conductor, a second electric conductor, a protective film, and a solder layer. The insulating film is formed to cover the semiconductor substrate. The first electric conductor is formed on the insulating film. The second electric conductor is formed on the insulating film at a distance from the first electric conductor. The protective film is formed to cover the first electric conductor and the second electric conductor. The solder layer is formed to cover the protective film. The first electric conductor and the second electric conductor are each thinner than the solder layer.

Advantageous Effects of Invention

In accordance with the first semiconductor device according to the present invention, the first electric conductor and the second electric conductor each have a Young's modulus of 300 GPa or more. Thus, sliding of the first electric conductor or the second electric conductor can be suppressed, to prevent the first electric conductor and the second electric conductor from coming into contact with each other and being electrically shorted.

In accordance with the second semiconductor device according to the present invention, the embedded body is formed to fill the space between the first electric conductor and the second electric conductor. Thus, the stress acting on the first electric conductor or the second electric conductor can be relaxed, to suppress the sliding of the first electric conductor or the second electric conductor. As a result, the first electric conductor and the second electric conductor can be prevented from coming into contact with each other and being electrically shorted.

In accordance with the third semiconductor device according to the present invention, the first electric conductor and the second electric conductor are each provided with an inclined portion. Thus, the stress acting on the first electric conductor or the second electric conductor can be relaxed, to suppress the sliding of the first electric conductor or the second electric conductor. As a result, the first electric conductor and the second electric conductor can be prevented from coming into contact with each other and being electrically shorted.

In accordance with the fourth semiconductor device according to the present invention, the upper surface of the second electric conductor is located lower than the lower surface of the first electric conductor. Thus, even if the first electric conductor slides, the first electric conductor and the second electric conductor can be kept from coming into contact with each other. As a result, the first electric conductor and the second electric conductor can be prevented from being electrically shorted.

In accordance with the fifth semiconductor device according to the present invention, the first electric conductor and the second electric conductor are each thinner than the solder layer. Thus, the stress acting on the first electric conductor or the second electric conductor can be relaxed, to suppress the sliding of the first electric conductor or the second electric conductor. As a result, the first electric conductor and the second electric conductor can be prevented from coming into contact with each other and being electrically shorted.

DESCRIPTION OF EMBODIMENTS

First Embodiment

Described here is an example of a semiconductor device including a gate interconnection and an emitter electrode which are made of a material harder than aluminum.

As shown inFIGS. 1 and 2, in a semiconductor device1, a P type layer5is formed to a predetermined depth from the surface of a predetermined region (gate pull-up portion) in a semiconductor substrate3. A trench4of a predetermined depth is formed in a predetermined region (cell portion) in P type layer5and semiconductor substrate3. A silicon oxide film6is formed to cover an upper surface of P type layer5.

A gate insulating film7is formed on a bottom surface and a side surface of trench4. A polysilicon film9is formed to cover silicon oxide film6and gate insulating film7. A portion of polysilicon film9that is located in trench4serves as a gate electrode10. Gate electrode10is, for example, a gate electrode of an IGBT as a semiconductor element.

A gate interlayer insulating film11is formed to cover polysilicon film9. Contact holes12are formed to extend through gate interlayer insulating film11. Contacts13(plugs) are formed in contact holes12. A gate interconnection15is formed in contact with contacts13. Gate interconnection15is electrically connected to gate electrode10through contacts13.

An emitter electrode17is formed at a distance from gate interconnection15. Emitter electrode17is, for example, an emitter electrode of an IGBT. As shown inFIG. 1, gate interconnection15is disposed such that it is sandwiched between one emitter electrode17and another emitter electrode. Here, gate interconnection15and emitter electrode17are each formed of a tungsten film14, for example, as a material harder than aluminum.

A glass coating film19(silicon nitride film) as a highly insulating protective film is formed to cover gate interconnection15and the emitter electrode, as well as a region located between gate interconnection15and emitter electrode17. Further, a polyimide film21as a semi-insulating protective film is formed to cover glass coating film19. In addition, a metal film23is formed in contact with emitter electrode17. A solder layer25is formed to cover polyimide film21. Solder layer25is in contact with metal film23. Semiconductor device1according to the first embodiment is configured as described above.

An example of a method of manufacturing above-described semiconductor device1is described next. As shown inFIG. 3, a p type impurity is implanted into a predetermined region (gate pull-up portion) in semiconductor substrate3, to form P type layer5. P type layer5is formed to a predetermined depth from the surface of semiconductor substrate3. Then, a silicon oxide film (not shown) is formed to cover P type layer5and semiconductor substrate3.

Then, a predetermined photolithography process is performed to form a resist pattern (not shown) which exposes the silicon oxide film located in a region (cell portion) where the trench is to be formed, and which covers the other regions. Then, an etching process is performed on the exposed silicon oxide film and semiconductor substrate3with that resist pattern as an etching mask, to form trench4of a predetermined depth (seeFIG. 4). The photoresist pattern is subsequently removed to expose remaining silicon oxide film6, as shown inFIG. 4.

Then, as shown inFIG. 5, a thermal oxidation process is performed, for example, to form gate insulating film7on the bottom surface and the side surface of trench4. Then, as shown inFIG. 6, polysilicon film9is formed to cover gate insulating film7so as to fill trench4, and to cover silicon oxide film6. A portion of polysilicon film9that is formed in trench4serves as gate electrode10.

Then, as shown inFIG. 7, gate interlayer insulating film11such as a silicon oxide film is formed to cover polysilicon film9. Then, as shown inFIG. 8, contact holes12are formed in gate interlayer insulating film11to expose polysilicon film9.

Then, a tungsten film (not shown) is formed by a sputtering process or a CVD (Chemical Vapor Deposition) process, for example, to cover gate interlayer insulating film11. Then, a predetermined photolithography process and an etching process are performed to form gate interconnection15and emitter electrode17, as shown inFIG. 9. Contacts13(plugs) are formed in contact holes12. Gate interconnection15and emitter electrode17are each formed of tungsten film14which is harder than aluminum.

Then, a silicon nitride film (not shown) is formed to cover gate interconnection15and emitter electrode17. Then, a predetermined photolithography process and an etching process are performed to form glass coating film19as a highly insulating protective film, as shown inFIG. 10. Glass coating film19is formed in such a manner as to cover the region located between gate interconnection15and emitter electrode17, and expose a portion of emitter electrode17.

Then, a polyimide film (not shown) is formed to cover glass coating film19and exposed emitter electrode17. Then, a predetermined photolithography process and an etching process are performed to form polyimide film21as a semi-insulating protective film, as shown inFIG. 11. Polyimide film21is formed in such a manner as to cover glass coating film19and expose a portion of emitter electrode17.

Then, as shown inFIG. 12, metal film23is formed in contact with the exposed portion of emitter electrode17. Then, solder layer25is formed to cover polyimide film21. Solder layer25is in contact with metal film23. A main part of semiconductor device1is thus completed.

In semiconductor device1described above, since gate interconnection15and emitter electrode17are each formed of tungsten film14, sliding of gate interconnection15in a lateral direction caused by expansion and contraction of solder layer25can be suppressed. This will be described in comparison with a semiconductor device according to a comparative example.

As shown inFIG. 13, in a semiconductor device101according to a comparative example, gate interconnection15and emitter electrode17are each formed of an aluminum film114. Since the configuration is otherwise similar to that of semiconductor device1shown inFIG. 2, the same components are designated by the same characters and description thereof will not be repeated unless needed.

In semiconductor device101, solder layer25expands and contracts repeatedly with ON operation and OFF operation of semiconductor device101(semiconductor element). Solder layer25has a higher coefficient of thermal expansion than that of polyimide film21and the like. Thus, the repeated expansion and contraction of solder layer25causes high stress to act on polyimide film21and the like, as shown inFIG. 14(see arrows). When the stress acts on polyimide film21and the like, relatively high stress also acts on gate interconnection15covered by polyimide film21and the like and extending with a predetermined width.

In semiconductor device101according to the comparative example, gate interconnection15is made of aluminum which is relatively soft. Thus, as shown inFIG. 15, gate interconnection15slides in the lateral direction due to the stress acting on gate interconnection15. More specifically, a portion of gate interconnection15that is located above an upper surface of glass coating film19covering the region located between gate interconnection15and emitter electrode17slides in the lateral direction, while a portion of gate interconnection15that is located below that upper surface remains. As a result, gate interconnection15may come into contact with emitter electrode17to cause electrical shorting.

In contrast with semiconductor device101according to the comparative example, in semiconductor device1according to the first embodiment, gate interconnection15and emitter electrode17are each formed of tungsten film14which is harder than aluminum. Accordingly, as shown inFIG. 16, the stress acting on gate interconnection15can be opposed, to suppress the sliding of gate interconnection15in the lateral direction. As a result, gate interconnection15can be prevented from coming into contact with emitter electrode17to cause electrical shorting.

Tungsten film14has been described here as an example of a material harder than aluminum. The inventors' evaluation revealed that a material having a predetermined Young's modulus may be employed as a material for gate interconnection15and emitter electrode17. This is described next.

First, it was found that gate interconnection15made of aluminum slides approximately 45 μm due to the stress. Given the fact that aluminum has a Young's modulus of 68.3 Gpa (68.3×109N/m2) as well as this sliding distance, it is estimated that a stress of approximately 3000 N/mm is acting on gate interconnection15.

The space between gate interconnection15and emitter electrode17is approximately 10 μm. Here, it is considered that, even if gate interconnection15slides, electrical shorting is prevented when the sliding distance is shorter than this space. It is then considered that electrical shorting is prevented with gate interconnection15and the like made of a material having a Young's modulus of 300 Gpa (300×109N/m2) or more.

Tungsten film14(W) cited in the first embodiment has a Young's modulus of 345 Gpa (345×109N/m2), which satisfies the aforementioned requirement. Examples of the material for gate interconnection15and the like include, in addition to the tungsten, copper-tungsten (10Cu—W), copper-tungsten (15Cu—W), tungsten-nickel-copper (W-1.8Ni-1.2Cu) and tungsten-nickel-copper (W-3Ni-2Cu).

The copper-tungsten (10Cu—W) has a Young's modulus of 320 Gpa (320×109N/m2). The copper-tungsten (15Cu—W) has a Young's modulus of 310 Gpa (310×109N/m2). The tungsten-nickel-copper (W-1.8Ni-1.2Cu) also has a Young's modulus of 310 Gpa (310×109N/m2). The tungsten-nickel-copper (W-3Ni-2Cu) also has a Young's modulus of 310 Gpa (310×109N/m2). All of these materials have a Young's modulus higher than 300 Gpa (300×109N/m2), which satisfies the aforementioned requirement.

By applying the aforementioned materials as a material for gate interconnection15and emitter electrode17, electrical shorting between gate interconnection15and emitter electrode17can be suppressed. Although gate interconnection15and emitter electrode17have been described by way of example in semiconductor device1according to the first embodiment, the aforementioned materials can be applied to interconnections other than gate interconnection15and electrodes other than emitter electrode17. By applying the aforementioned materials, electrical shorting between an interconnection and an electrode, electrical shorting between interconnections, or electrical shorting between electrodes can be suppressed.

Second Embodiment

Described here is an example of a semiconductor device including a dummy embedded electrode between a gate interconnection and an emitter electrode.

As shown inFIG. 17, in semiconductor device1, gate interconnection15is formed in contact with gate interlayer insulating film11. Emitter electrode17is formed, at a distance from gate interconnection15, in contact with gate interlayer insulating film11. Here, gate interconnection15and emitter electrode17are each formed of an aluminum film16, for example.

Glass coating film19is formed to cover a side surface and an upper surface of gate interconnection15. Glass coating film19is also formed to cover a side surface and a portion of an upper surface of emitter electrode17. A dummy embedded electrode18ais formed to fill a recess (step) located between gate interconnection15and emitter electrode17. Here, dummy embedded electrode18ais formed of an aluminum film, for example.

Glass coating film19is formed to cover embedded electrode18a, gate interconnection15and emitter electrode17. Further, polyimide film21is formed to cover glass coating film19. Solder layer25is formed to cover polyimide film21and the like. Since the configuration is otherwise similar to that of semiconductor device1shown inFIG. 2, the same components are designated by the same characters and description thereof will not be repeated unless needed.

An example of a method of manufacturing above-described semiconductor device1is described next. First, a gate interconnection and an emitter electrode each formed of an aluminum film are formed through steps similar to those shown inFIGS. 3 to 8. Then, a silicon nitride film (not shown) is formed to cover the gate interconnection and the emitter electrode.

Then, a predetermined photolithography process and an etching process are performed to form glass coating film19, as shown inFIG. 18. Glass coating film19is formed to cover the side surface and the upper surface of gate interconnection15, and formed to cover the side surface and a portion of the upper surface of emitter electrode17. In the region (recess or step) located between gate interconnection15and emitter electrode17, the silicon nitride film has been removed to expose gate interlayer insulating film11.

Then, a conductive film (not shown) formed of an aluminum film, for example, is formed to cover the glass coating film in such a manner as to fill the region (recess or step) located between gate interconnection15and emitter electrode17. Then, a predetermined photolithography process and an etching process are performed to leave a portion of the conductive film (conductive film18) embedded in the region (recess or step) located between gate interconnection15and emitter electrode17and remove a portion of the conductive film located in the other regions, as shown inFIG. 19.

Then, as shown inFIG. 20, an etching process is performed on remaining conductive film18to match an upper surface of conductive film18to the position of the upper surface of glass coating film19, to thereby form dummy embedded electrode18a.

Then, as shown inFIG. 21, polyimide film21is formed to cover glass coating film19and embedded electrode18athrough a step similar to that shown inFIG. 11. Then, metal film23is formed in contact with emitter electrode17. Subsequently, solder layer25is formed to cover polyimide film21, to complete a main part of semiconductor device1shown inFIG. 17.

In semiconductor device1described above, dummy embedded electrode18ais formed to fill the region (recess or step) located between gate interconnection15and emitter electrode17. Thus, polyimide film21will not be formed in the recess or the step between gate interconnection15and emitter electrode17. Accordingly, as shown inFIG. 22, the stress acting on polyimide film21with the expansion and contraction of solder layer25can be kept from reaching gate interconnection15and the like. As a result, gate interconnection15can be prevented from coming into contact with emitter electrode17to cause electrical shorting.

In semiconductor device1described above, aluminum (Al) was cited as an example of the material for embedded electrode18a. The material for embedded electrode18ais not limited to aluminum, but tungsten (W) or titanium (Ti) may be used, for example.

Third Embodiment

Described here is an example of a semiconductor device including a gate interconnection and an emitter electrode each provided with an inclined portion.

As shown inFIG. 23, in semiconductor device1, gate interconnection15is formed in contact with gate interlayer insulating film11. Emitter electrode17is formed, at a distance from gate interconnection15, in contact with gate interlayer insulating film11. Each of gate interconnection15and emitter electrode17is provided with an inclined portion. Here, they are provided with a tapered inclined portion. Gate interconnection15and emitter electrode17are each formed of aluminum film16, for example.

Glass coating film19is formed to cover gate interconnection15and the emitter electrode, as well as the region located between gate interconnection15and emitter electrode17. Further, polyimide film21is formed to cover glass coating film19. Solder layer25is formed to cover polyimide film21and the like. Since the configuration is otherwise similar to that of semiconductor device1shown inFIG. 2, the same components are designated by the same characters and description thereof will not be repeated unless needed.

An example of a method of manufacturing above-described semiconductor device1is described next. First, as shown inFIG. 24, aluminum film16is formed by a sputtering process, for example, to cover gate interlayer insulating film11, through steps similar to those shown inFIGS. 3 to 8.

Then, as shown inFIG. 25, a predetermined photolithography process is performed to form a photoresist pattern31for patterning the gate interconnection and the emitter electrode. Photoresist pattern31is formed to expose a portion of aluminum film16that covers a region in the vicinity of the boundary between gate electrode10and P type layer5.

Then, a wet etching process is performed on exposed aluminum film16, with photoresist pattern31as an etching mask. Here, aluminum film16is isotropically etched, whereby a tapered inclined portion is formed on a longitudinal surface (side surface) of the aluminum film. Photoresist pattern31is subsequently removed to expose gate interconnection15and emitter electrode17each provided with the tapered inclined portion, as shown inFIG. 26.

Then, as shown inFIG. 27, glass coating film19is formed through a step similar to that shown inFIG. 10. Then, as shown inFIG. 28, polyimide film21is formed to cover glass coating film19through a step similar to that shown inFIG. 11. Then, metal film23is formed in contact with emitter electrode17. Solder layer25is subsequently formed to cover polyimide film21, to complete a main part of semiconductor device1shown inFIG. 23.

In semiconductor device1described above, each of gate interconnection15and emitter electrode17is provided with the tapered inclined portion. Thus, the stress acting on polyimide film21with the expansion and contraction of solder layer25is partly released by the inclined portions of gate interconnection15and the like. The stress reaching gate interconnection15and the like is thereby weakened. As a result, as shown inFIG. 29, the sliding of gate interconnection15in the lateral direction can be suppressed, to prevent gate interconnection15from coming into contact with emitter electrode17to cause electrical shorting.

Fourth Embodiment

Described here is another example of a semiconductor device including a gate interconnection and an emitter electrode each provided with an inclined portion.

As shown inFIG. 30, in semiconductor device1, gate interconnection15is formed in contact with gate interlayer insulating film11. Emitter electrode17is formed, at a distance from gate interconnection15, in contact with gate interlayer insulating film11. Each of gate interconnection15and emitter electrode17is provided with an inclined portion. Here, they are provided with a stepped inclined portion. Gate interconnection15and emitter electrode17are each formed of aluminum film16, for example.

Glass coating film19is formed to cover gate interconnection15and the emitter electrode, as well as the region located between gate interconnection15and emitter electrode17. Further, polyimide film21is formed to cover glass coating film19. Solder layer25is formed to cover polyimide film21and the like. Since the configuration is otherwise similar to that of semiconductor device1shown inFIG. 2, the same components are designated by the same characters and description thereof will not be repeated unless needed.

An example of a method of manufacturing above-described semiconductor device1is described next. First, as shown inFIG. 31, a pattern of aluminum film16is formed through steps similar to those shown inFIGS. 3 to 9.

Then, as shown inFIG. 32, a predetermined photolithography process is performed to form a photoresist pattern32. Photoresist pattern32is formed to have a size smaller than that of the pattern of aluminum film16. Then, an anisotropic etching process is performed on exposed aluminum film16, with photoresist pattern32as an etching mask, to form a stepped inclined portion on a side wall of aluminum film16. Here, an amount of etching of aluminum film16is controlled by an etching time. Photoresist pattern32is subsequently removed.

Then, as shown inFIG. 33, glass coating film19is formed through a step similar to that shown inFIG. 10. Then, as shown inFIG. 34, polyimide film21is formed to cover glass coating film19through a step similar to that shown inFIG. 11. Then, metal film23is formed in contact with emitter electrode17. Solder layer25is subsequently formed to cover polyimide film21, to complete a main part of semiconductor device1shown inFIG. 30.

In semiconductor device1described above, each of gate interconnection15and emitter electrode17is provided with the stepped inclined portion. Thus, the stress acting on polyimide film21with the expansion and contraction of solder layer25is partly released by the inclined portions of gate interconnection15and the like. The stress reaching gate interconnection15and the like is thereby weakened. As a result, as shown inFIG. 35, the sliding of gate interconnection15in the lateral direction can be suppressed, to prevent gate interconnection15from coming into contact with emitter electrode17to cause electrical shorting.

The above-described method of manufacturing semiconductor device1has described a case where aluminum film16having a predetermined film thickness is formed, and then two anisotropic etching processes are performed to thereby form gate interconnection15and emitter electrode17each having the stepped inclined portion. Alternatively, for example, aluminum films each having a film thickness approximately half the predetermined film thickness may be formed in two steps. In this case, an aluminum film serving as the first layer can be patterned, and then an aluminum film serving as the second layer can be formed and patterned, to thereby form stepped gate interconnection15and emitter electrode17.

Fifth Embodiment

Described here is an example of a semiconductor device including a gate interconnection and an emitter electrode, where an upper surface of the emitter electrode is located lower than a lower surface of the gate interconnection.

As shown inFIG. 36, in semiconductor device1, gate interconnection15is formed in contact with gate interlayer insulating film11. Emitter electrode17is formed, at a distance from gate interconnection15, in contact with gate interlayer insulating film11. A position H1of an upper surface of emitter electrode17is at a position lower than a position H2of a lower surface of gate interconnection15. Gate interconnection15and emitter electrode17are each formed of aluminum film16, for example.

Glass coating film19is formed to cover gate interconnection15and the emitter electrode, as well as the region located between gate interconnection15and emitter electrode17. Further, polyimide film21is formed to cover glass coating film19. Solder layer25is formed to cover polyimide film21and the like. Since the configuration is otherwise similar to that of semiconductor device1shown inFIG. 2, the same components are designated by the same characters and description thereof will not be repeated unless needed.

An example of a method of manufacturing above-described semiconductor device1is described next. First, polysilicon film9(seeFIG. 37) is formed to fill trench4(seeFIG. 37) through steps similar to those shown inFIGS. 3 to 5. Then, as shown inFIG. 37, an etching process is performed on a portion of polysilicon film9that is located in trench4, to thereby lower the position of an upper surface of polysilicon film9as compared to the position of the upper surface of the polysilicon film shown inFIG. 6(see a dotted line).

Then, as shown inFIG. 38, gate interconnection15and emitter electrode17are formed through steps similar to those shown inFIGS. 7 to 9. Gate interconnection15and emitter electrode17are each formed of aluminum film16, for example. Here, the film thickness of aluminum film16is set such that the upper surface of emitter electrode17is located lower than the lower surface of gate interconnection15, in consideration of the position (height) of a base on which gate interconnection15is formed and the position (height) of a base on which emitter electrode17is formed.

Then, as shown inFIG. 39, glass coating film19is formed through a step similar to that shown inFIG. 10. Then, as shown inFIG. 40, polyimide film21is formed to cover glass coating film19through a step similar to that shown inFIG. 11. Then, metal film23is formed in contact with emitter electrode17. Solder layer25is subsequently formed to cover polyimide film21, to complete a main part of semiconductor device1shown inFIG. 36.

In semiconductor device1described above, position H1of the upper surface of emitter electrode17is at a position lower than position H2of the lower surface of gate interconnection15. Thus, the stress acting on polyimide film21with the expansion and contraction of solder layer25reaches gate interconnection15, but hardly reaches emitter electrode17.

In addition, as shown inFIG. 41, even if gate interconnection15slides due to the stress acting on gate interconnection15, since the upper surface of emitter electrode17is located lower than the lower surface of gate interconnection15, gate interconnection15can be prevented from coming into contact with emitter electrode17to cause electrical shorting.

Sixth Embodiment

Described here is an example of a semiconductor device including a gate interconnection and an emitter electrode, where the emitter electrode and the gate interconnection each have a relatively small thickness.

As shown inFIG. 42, in semiconductor device1, gate interconnection15is formed in contact with gate interlayer insulating film11. Emitter electrode17is formed, at a distance from gate interconnection15, in contact with gate interlayer insulating film11. Gate interconnection15and emitter electrode17are each formed to have a thickness smaller than that of solder layer25, for example.

Glass coating film19is formed to cover gate interconnection15and emitter electrode17, as well as the region located between gate interconnection15and emitter electrode17. Further, polyimide film21is formed to cover glass coating film19. Solder layer25is formed to cover polyimide film21and the like. Since the configuration is otherwise similar to that of semiconductor device1shown inFIG. 2, the same components are designated by the same characters and description thereof will not be repeated unless needed.

An example of a method of manufacturing above-described semiconductor device1is described next. First, as shown inFIG. 43, aluminum film16is patterned to form gate interconnection15and emitter electrode17through steps similar to those shown inFIGS. 3 to 9. Here, aluminum film16is formed to have a thickness smaller than that of solder layer25, for example.

Then, as shown inFIG. 44, glass coating film19is formed through a step similar to that shown inFIG. 10. Then, as shown inFIG. 45, polyimide film21is formed to cover glass coating film19through a step similar to that shown inFIG. 11. Then, metal film23is formed in contact with emitter electrode17. Solder layer25is subsequently formed to cover polyimide film21, to complete a main part of semiconductor device1shown inFIG. 42.

In semiconductor device1described above, gate interconnection15and emitter electrode17are each formed to have a relatively small film thickness. Specifically, gate interconnection15and emitter electrode17are each formed to have a film thickness smaller than that of solder layer25, for example. Thus, the stress acting on gate interconnection15and the like with the expansion and contraction of solder layer25is reduced as compared to when the film thickness is relatively great, whereby the stress acting on gate interconnection15and the like is relaxed. As a result, as shown inFIG. 46, the sliding of gate interconnection15in the lateral direction can be suppressed, to prevent gate interconnection15from coming into contact with emitter electrode17to cause electrical shorting.

It should be noted that semiconductor devices1described in the respective embodiments can be combined in various ways as needed. For example, although the second to sixth embodiments have described a case where gate interconnection15and emitter electrode17are each formed of aluminum film16, a metal film having a predetermined Young's modulus such as tungsten film14described in the first embodiment may be applied.

Although gate interconnection15and emitter electrode17have been described by way of example in the semiconductor devices in the above respective embodiments, the structure described in each embodiment can be applied to interconnections other than gate interconnection15and electrodes other than emitter electrode17. By applying such a structure, electrical shorting between an interconnection and an electrode, electrical shorting between interconnections, or electrical shorting between electrodes can be suppressed.

Further, although an IGBT has been cited as an example of the semiconductor element, the structure described in each embodiment can be applied to an electrode, an interconnection and the like of a semiconductor element such as a MOFEST or a SiC-MOS, in addition to the IGBT.

INDUSTRIAL APPLICABILITY

The present invention is effectively utilized for a power semiconductor device having an interconnection and an electrode.

REFERENCE SIGNS LIST