Imaging panel and X-ray imaging system provided with said imaging panel

An aim of the present invention is to make it possible to achieve stable operation of thin film transistors in an imaging panel of an X-ray imaging system that uses an indirect conversion scheme. An imaging panel includes a substrate, thin film transistor, photoelectric conversion element, and bias wiring line. The thin film transistor is formed on the substrate. The photoelectric conversion element is connected to the thin film transistor and irradiated by scintillation light. The bias wiring line is connected to the photoelectric conversion element and applies a reverse bias voltage to the photoelectric conversion element. The thin film transistor includes a semiconductor active layer and a gate electrode. The gate electrode is formed between the substrate and semiconductor active layer. The bias wiring line includes a portion that overlaps the gate electrode and semiconductor active layer as seen from the radiation direction of the scintillation light.

TECHNICAL FIELD

The present invention relates to an imaging panel and X-ray imaging system, and more specifically to an imaging panel that generates images based on scintillation light from X-rays that have passed through a specimen, and an X-ray imaging system having this imaging panel.

BACKGROUND ART

There are X-ray imaging systems that capture images via an imaging panel having a plurality of pixels. X-ray imaging systems include direct conversion schemes and indirect conversion schemes.

In direct conversion schemes, an X-ray conversion film made of amorphous selenium (a-Se) converts incident X-rays into electric charge, for example. The converted electric charge is stored in a capacitor in the pixel. The stored electric charge is read out by operating a thin film transistor in the pixel. Image signals are generated based on the charge that is read out. Images are generated based on the image signals.

In indirect conversion schemes, a scintillator converts incident X-rays into scintillation light, for example. The scintillation light is converted to electric charge by a photoelectric conversion element in the pixel. The converted electric charge is read out by operating a thin film transistor in the pixel. Image signals are generated based on the charge that is read out. Images are generated based on the image signals.

SUMMARY OF THE INVENTION

An aim of the present invention is to make it possible to achieve stable operation of thin film transistors in an imaging panel of an X-ray imaging system that uses an indirect conversion scheme.

An imaging panel of one embodiment of the present invention is an imaging panel for generating an image in accordance with scintillation light obtained from X-rays that have passed through a specimen, the imaging panel including: a substrate; a thin film transistor on the substrate; a photoelectric conversion element connecting to the thin film transistor and receiving the scintillation light; and a bias wiring line connecting to the photoelectric conversion element and applying a reverse bias voltage to the photoelectric conversion element, and the thin film transistor includes: a semiconductor active layer; and a gate electrode between the substrate and semiconductor active layer, and the bias wiring line includes a section that overlaps the gate electrode and the semiconductor active layer as seen from a radiation direction of the scintillation light such that the reverse bias voltage is capacitively coupled to the semiconductor active layer thereunder.

An imaging panel in an embodiment of the present invention makes it possible to achieve stable operation of thin film transistors.

DETAILED DESCRIPTION OF EMBODIMENTS

An imaging panel of one embodiment of the present invention is an imaging panel for generating an image in accordance with scintillation light obtained from X-rays that have passed through a specimen, the imaging panel including: a substrate; a thin film transistor on the substrate; a photoelectric conversion element connecting to the thin film transistor and receiving the scintillation light; and a bias wiring line connecting to the photoelectric conversion element and applying a reverse bias voltage to the photoelectric conversion element, and the thin film transistor includes: a semiconductor active layer; and a gate electrode between the substrate and semiconductor active layer, and the bias wiring line includes a section that overlaps the gate electrode and the semiconductor active layer as seen from a radiation direction of the scintillation light such that the reverse bias voltage is capacitively coupled to the semiconductor active layer thereunder.

In the imaging panel, it is possible for the bias wiring line to shield the semiconductor active layer from light. Thus, it is harder for scintillation light to enter the semiconductor active layer. This results in the characteristics of the thin film transistor being unsusceptible to deterioration. Accordingly, it is possible to stabilize the operation of the thin film transistor.

In the imaging panel, the bias wiring line includes a portion that overlaps the gate electrode. Therefore, it is possible to use this portion as a second gate electrode (backgate electrode). As a result, setting the voltage applied to the backgate electrode as appropriate makes it possible to modify the operating characteristics of the thin film transistor.

The thin film transistor includes a drain electrode connecting to the photoelectric conversion element, and the photoelectric conversion element includes: an n-type semiconductor layer contacting the drain electrode; an intrinsic semiconductor layer contacting the n-type semiconductor layer; and a p-type semiconductor layer contacting the intrinsic semiconductor layer, and the bias wiring line makes a potential of the p-type semiconductor layer lower than a potential of the n-type semiconductor layer.

In order to reduce OFF current (leakage current) of the thin film transistor, a negative charge is applied to the gate electrode when the thin film transistor is to be turned OFF. If this period is long, the threshold voltage of the thin film transistor will shift in the minus direction.

In the aspect described above, it is possible to shift the threshold voltage in the plus direction. By shifting the threshold voltage in the plus direction beforehand, the threshold voltage is not likely to reach the minimum value even if shifted in the minus direction, for example.

The thin film transistor includes a drain electrode connecting to the photoelectric conversion element, and the photoelectric conversion element includes: a p-type semiconductor layer contacting the drain electrode; an intrinsic semiconductor layer contacting the p-type semiconductor layer; and an n-type semiconductor layer contacting the intrinsic semiconductor layer, and the bias wiring line makes a potential of the n-type semiconductor layer higher than a potential of the p-type semiconductor layer.

In such a case, it is possible to shift the threshold voltage of the thin film transistor in the minus direction. This enables a reduction in the voltage for turning ON the thin film transistor (the voltage applied to the gate electrode).

It is preferable that the semiconductor active layer be made of an oxide semiconductor. In such a case, it is possible to achieve high resolution images. The reason for this is as follows.

In a thin film transistor where the semiconductor active layer is made of an oxide semiconductor, the ON current is approximately 20 times greater than conventional thin film transistors, and the OFF current (leakage current) is several orders of magnitude smaller than conventional thin film transistors. Because the ON current is larger, it is possible to reduce the size of the thin film transistor. Because the OFF current is smaller, it is possible to reduce the area of the storage capacitor. As a result, pixel pitch can be reduced, which allows for higher resolution.

The oxide semiconductor is an oxide containing prescribed proportions of indium (In), gallium (Ga), and zinc (Zn), for example.

The thin film transistor further includes: a first insulating film between the gate electrode and the semiconductor active layer and covering the gate electrode; and a second insulating film covering the semiconductor active layer, and the first insulating film and the second insulating film preferably include a silicon oxide film contacting the semiconductor active layer.

Silicon oxide films contain less hydrogen than silicon nitride films. Therefore, reducing the hydrogen contained in the semiconductor active layer makes it possible to prevent negative effects on the characteristics of the thin film transistor.

An X-ray imaging system of one embodiment of the present invention includes: the imaging panel; an X-ray source; and a scintillator between the X-ray source and the imaging panel.

The imaging panel described above makes it possible to stabilize the operation of the thin film transistor.

Specific embodiments of the present invention will be explained below with reference to figures. Portions in the drawings that are the same or similar are assigned the same reference characters and descriptions thereof will not be repeated.

In the X-ray imaging system10, X-rays are radiated from the X-ray source16, and X-rays that have passed through a specimen18enter the scintillator13. The scintillator13emits fluorescent light (scintillation light) when irradiated by the X-rays. The imaging panel12and controller14capture the scintillation light in order to acquire an image.

As shown inFIG. 2A, the imaging panel12includes a plurality of pixels22. As shown inFIG. 2A, the plurality of pixels22are arranged in a matrix pattern. In the example shown inFIG. 2A, sixteen pixels22are arranged in 4 rows×4 columns. The pixels22output signals (light detection signals) that correspond to the intensity of incident scintillation light.

FIG. 3is a cross-sectional view of a general configuration of one of the pixels22of the imaging panel12. The pixel22is formed on a substrate20in the imaging panel12. The substrate20has no particular limitations as long as the substrate is an insulating substrate. The substrate20may be a glass substrate, for example, or a compound resin substrate. The compound resin may be polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polyether sulfone (PES), an acrylic resin, a polyimide, or the like, for example.

As shown inFIG. 2B, the pixel22includes a thin film transistor24, a photodiode26as a photoelectric conversion element, and a backgate electrode50.

As shown inFIG. 3, the thin film transistor24includes a gate electrode28, gate insulating film30, semiconductor active layer32, source electrode34, and drain electrode36.

As shown inFIG. 3, the gate electrode28is formed contacting one surface (hereinafter, main surface) of the substrate20in the thickness direction. The gate electrode28is formed of a metal such as aluminum (Al), tungsten (W), molybdenum (Mo), tantalum (Ta), chromium (Cr), titanium (Ti), or copper (Cu), for example, or alternatively is a nitride of these metals. Alternatively, the gate electrode28may be a plurality of metal films layered together, for example. In the present embodiment, the gate electrode28has a multilayer structure in which a titanium metal film, aluminum metal film, and titanium metal film are layered together in this order. The gate electrode28is formed by using sputtering or the like to form a metal film on the substrate20and then patterning this metal film via photolithography, for example. The thickness of the gate electrode28is 50 nm to 300 nm, for example. The gate electrode28may be constituted by a gate line formed on the substrate20and extending in a prescribed direction, or alternatively the gate electrode may be constituted by a portion extending from the gate line in a direction that differs from the prescribed direction. As shown inFIG. 4, in the present embodiment, the gate electrode28is constituted by a portion extending from a gate line29.

As shown inFIG. 3, the gate insulating film30is formed on the substrate20and covers the gate electrode28. The gate insulating film30includes a silicon nitride film and a silicon oxide film, for example. The silicon nitride film is formed contacting the gate electrode28and substrate20. The silicon oxide film is formed contacting the silicon nitride film. The thickness of the silicon nitride film is 100 nm to 400 nm, for example. The thickness of the silicon oxide film is 50 nm to 100 nm, for example. The gate insulating film30is formed by plasma-enhanced CVD, for example. In order to form a precise insulating film with low gate leakage current at a low temperature, a noble gas element such as argon may be included in the reactive gas and mixed into the insulating film. The gate insulating film30may alternatively be constituted by only the silicon oxide film. Instead of a silicon nitride film, the insulating film may be a silicon nitride oxide film (SiNxOy) (x>y). Instead of a silicon oxide film, the insulating film may be a silicon oxynitride film (SiOxNy) (x>y).

As shown inFIG. 3, the semiconductor active layer32is formed contacting the gate insulating film30. The semiconductor active layer32is an oxide semiconductor. The oxide semiconductor is an oxide containing prescribed proportions of indium (In), gallium (Ga), and zinc (Zn), for example. The oxide semiconductor may be InGaO3(ZnO)5, magnesium zinc oxide (MgxZn1-xO), cadmium zinc oxide (CdxZn1-xO), cadmium oxide (CdO), or an In—Ga—Zn—O amorphous oxide semiconductor (a-IGZO), for example. The oxide semiconductor may be non-crystalline, polycrystalline, or microcrystalline ZnO having a mix of non-crystalline and polycrystalline states, or a material that has had no impurity elements added to this ZnO. The impurity element is one or multiple elements selected from group 1 elements, group 13 elements, group 14 elements, group 15 elements, or group 17 elements. The thickness of the semiconductor active layer32is 30 nm to 100 nm, for example. The semiconductor active layer32is formed by forming a semiconductor layer via sputtering or the like and then using photolithography to pattern the semiconductor layer, for example. After the semiconductor layer has been formed, or after the semiconductor active layer32has been formed, a high-temperature heat treatment (350° C. or greater, for example) may be performed in an environment containing oxygen (e.g., the atmosphere). In such a case, it is possible to reduce oxygen defects in the oxide semiconductor layer.

As shown inFIG. 3, the source electrode34and drain electrode36are formed contacting the semiconductor active layer32and gate insulating film30. As shown inFIG. 4, the source electrode34is connected to the source line35. The source electrode34, source line35, and drain electrode36are formed on the same layer. The source electrode34, source line35, and drain electrode36are formed of a metal such as aluminum (Al), tungsten (W), molybdenum (Mo), tantalum (Ta), chromium (Cr), titanium (Ti), or copper (Cu), for example, or alternatively is a nitride of these metals. The source electrode34, source line35, and drain electrode36may be a plurality of metal films layered together, for example. In the present embodiment, the source electrode34, source line35, and drain electrode36have a multilayer structure in which a titanium metal film, aluminum metal film, and titanium metal film are layered together in this order. The thickness of the source electrode34, source line35, and drain electrode36is 50 nm to 500 nm, for example. The source electrode34, source line35, and drain electrode36are formed by using sputtering or the like to form a metal film on the semiconductor active layer32and gate insulating film30and then patterning this metal film via photolithography, for example. The etching when patterning the metal film may be dry etching or may be wet etching. When etching a metal film formed on a substrate with a wide area, it is preferable to use dry etching (anisotropic etching), which has less line width shifts, or namely less variation in line width.

As shown inFIG. 3, the imaging panel12further includes an insulating film38. The insulating film38covers the semiconductor active layer32, source electrode34, source line35, and drain electrode36. The insulating film38functions as a passivation film. The insulating film38is a silicon oxide film, for example. The insulating film38may be a silicon nitride film, or alternatively may be a silicon nitride film and silicon oxide film that have been layered together. The thickness of the insulating film38is 50 nm to 300 nm, for example. The insulating film38is formed by plasma-enhanced CVD, for example.

After the insulating film38has been formed, a heat treatment may be performed at a temperature of approximately 350 degrees. In such a case, it is possible to reduce defects in the insulating film38.

The insulating film38has formed therein a contact hole381. The contact hole381overlaps the drain electrode36when seen from a direction perpendicular to the main surface of the substrate20. The contact hole381is formed by photolithography, for example.

As shown inFIG. 3, the photodiode26is connected to the drain electrode36via the contact hole381. The entirety of the photodiode26overlaps the drain electrode36when seen from the direction perpendicular to the main surface of the substrate20. The photodiode26includes an n-type amorphous silicon layer26A, an intrinsic amorphous silicon layer26B, and a p-type amorphous silicon layer26C.

The n-type amorphous silicon layer26A is made of amorphous silicon that has been doped by an n-type impurity (phosphorous, for example). The n-type amorphous silicon layer26A is formed contacting the drain electrode36. The thickness of the n-type amorphous silicon layer26A is 20 nm to 100 nm, for example.

The intrinsic amorphous silicon layer26B is made of intrinsic amorphous silicon. The intrinsic amorphous silicon layer26B is formed contacting the n-type amorphous silicon layer26A. The thickness of the intrinsic amorphous silicon layer26B is 200 nm to 2000 nm, for example.

The p-type amorphous silicon layer26C is made of amorphous silicon that has been doped by a p-type impurity (boron, for example). The p-type amorphous silicon layer26C is formed contacting the intrinsic amorphous silicon layer26B. The thickness of the p-type amorphous silicon layer26C is 10 nm to 50 nm, for example.

The photodiode26is formed by plasma-enhanced CVD of the n-type amorphous silicon film, intrinsic amorphous silicon film, and p-type amorphous silicon film in this order, for example. Thereafter, these films are patterned via photolithography. This results in the forming of the photodiode26.

As shown inFIG. 3, the imaging panel12further includes an electrode40. The electrode40is formed contacting the p-type amorphous silicon layer26C of the photodiode22. The electrode40covers all of the p-type amorphous silicon layer26. The electrode40is a transparent conductive film, for example. The transparent conductive film is indium zinc oxide, for example. The electrode40is formed by forming the transparent conductive film via sputtering or the like and then patterning this transparent conductive film via photolithography, for example. The thickness of the electrode40is 50 nm to 500 nm, for example.

As shown inFIG. 3, the imaging panel12further includes a planarizing film44. The planarizing film44is made of a photosensitive resin, for example. The planarizing film44covers the insulating film42and electrode40. The thickness of the planarizing film44is 1000 nm to 4000 nm, for example. The planarizing film44is formed by spin coating, slit coating, or the like, and then a thermal treatment thereafter in a 150 to 250 degree atmosphere, for example. The thermal treatment temperature when curing the planarizing film44differs depending on the material of the planarizing film44. The planarizing film44has formed therein a contact hole441. The contact hole441overlaps the electrode40when seen from the direction perpendicular to the main surface of the substrate20. The contact hole441is formed by photolithography, for example.

As shown inFIGS. 3 and 4, the imaging panel12further includes a wiring line46. The wiring line46is formed on the planarizing film44. As shown inFIG. 4, the wiring line46extends parallel to the source line35. The wiring line46overlaps the semiconductor active layer32when seen from the direction perpendicular to the main surface of the substrate20. As shown inFIG. 4, in the present embodiment, the wiring line46overlaps the portion of the semiconductor active layer32not contacting the source electrode34and drain electrode36when seen from the direction perpendicular to the main surface of the substrate20. As shown inFIG. 4, in the present embodiment, the wiring line46overlaps the portion of the semiconductor active layer32overlapping the gate electrode28when seen from the direction perpendicular to the main surface of the substrate20. As shown inFIG. 4, the wiring line46overlaps the electrode40when seen from the direction perpendicular to the main surface of the substrate20. The wiring line46overlaps the gate electrode28when seen from the direction perpendicular to the main surface of the substrate20. In other words, a portion of the wiring line46, or specifically, the portion overlapping the gate electrode28when viewed from the direction perpendicular to the main surface of the substrate20, functions as the backgate electrode50. The wiring line46is made of a metal such as aluminum (Al), tungsten (W), molybdenum (Mo), tantalum (Ta), chromium (Cr), titanium (Ti), or copper (Cu), or is an alloy of these metals or a metal nitride of these, for example. The wiring line46may be a transparent conductive film, for example. The transparent conductive film is indium zinc oxide, for example. The wiring line46contacts the electrode40via the contact hole441. The thickness of the wiring line46is 50 nm to 500 nm, for example. The wiring line46is formed by forming a conductive film via sputtering or the like and then patterning this conductive film via photolithography, for example.

As shown inFIG. 1, the controller14includes a gate controller14A, signal reader14B, image processor14C, bias controller14D, X-ray controller14E, and timing controller14F. InFIG. 1, the controller14is provided separately from the imaging panel12, but alternatively, a portion or all of the controller14may be provided in the imaging panel12.

As shown inFIG. 2A, the gate controller14A is connected to a plurality of gate lines29. Several of the plurality of pixels22are connected to each of the gate lines29. In the example shown inFIG. 2A, four of the pixels22are connected to each of the gate lines29. The gate controller14A selects one gate line29from the plurality of gate lines29based on the control signal from the timing controller14F. The gate controller14A applies, via the selected gate line29, a prescribed gate voltage to the thin film transistor24of the pixel22connected to the corresponding gate line29(seeFIG. 2B).

As shown inFIG. 2A, the signal reader14B is connected to the plurality of source lines35. Several of the plurality of pixels22are connected to each of the source lines35. In the example shown inFIG. 2A, four of the pixels22are connected to each of the source lines35. The signal reader14B selects one source line35from the plurality of source lines35based on the control signal from the timing controller14F. The signal reader14B reads out light detection signals via the selected source line35. The light detection signals correspond to the electric charge generated by the photodiode26when scintillation light enters the photodiode26. In other words, the magnitude of the light detection signal changes in accordance with the amount of electrical charge generated by the photodiode26. The pixel22for which the light detection signal is read out is connected to the source line35selected by the signal reader14B and connected to the gate line29selected by the gate controller14A. The signal reader14B generates image signals based on the read out light detection signals and outputs the result to the image processor14C.

The image processor14C generates images based on the image signals output from the signal reader14B.

The bias controller14D is connected to the wiring line46. The bias controller14D applies a prescribed voltage to the wiring line46based on the control signal from the timing controller14F. This applies a bias voltage to the photodiode26. This results in the expansion of a depletion layer in the photodiode26.

The X-ray controller14E controls the radiation of X-rays by the X-ray source16based on the control signal from the timing controller14F.

The timing controller14F controls the operation timing of the gate controller14A, signal reader14B, bias controller14D, and X-ray controller14E.

In the X-ray imaging system10, the X-rays radiated from the X-ray source16irradiate the scintillator13via the specimen18. The X-rays that have irradiated the scintillator13are converted to scintillation light. The scintillation light enters the photodiode26. This generates a light detection signal. At such time, the thin film transistor24turns ON, and the light detection signal is read out. An image signal is generated based on the light detection signal that is read out. An image is generated based on the generated image signal.

As shown inFIG. 5, in the X-ray imaging system10, during the radiation period when X-rays are radiated, gate voltages are sequentially applied to the plurality of gate lines29and a negative charge is applied to the wiring line46.

The negative voltage being applied to the wiring line46shifts the threshold of the thin film transistor24in the plus direction. Thus, it is possible to stabilize the operation of the thin film transistor24. The reason for this is as follows.

In order to reduce OFF current (leakage current) of the thin film transistor24, a negative charge is applied to the gate electrode28when the thin film transistor24is to be turned OFF. If the period during which the negative charge is applied is long, the threshold voltage of the thin film transistor24shifts in the minus direction. As a countermeasure, the threshold voltage is shifted in the plus direction beforehand, for example. Thus, even if the threshold voltage shifts in the minus direction, the threshold voltage will not likely reach minimum value. As a result, it is possible to stabilize the operation of the thin film transistor24.

In the X-ray imaging system10, the wiring line46(backgate electrode50) can shield the semiconductor active layer32from light. Thus, it is harder for scintillation light to enter the semiconductor active layer32. This results in the characteristics of the thin film transistor24being unsusceptible to deterioration. Accordingly, it is possible to stabilize the operation of the thin film transistor24.

Next, Embodiment 2 of the present invention will be described with reference toFIGS. 6 and 7. As shown inFIG. 6, in the present embodiment as compared to Embodiment 1, the p-type amorphous silicon layer26C is contacting the drain electrode36and intrinsic amorphous silicon layer26B. The n-type amorphous silicon layer26A contacts the intrinsic amorphous silicon layer26B and the electrode40. As shown inFIG. 7, during the radiation period when X-rays are radiated, gate voltages are sequentially applied to the plurality of gate lines29and a positive voltage is applied to the wiring line46.

In the present embodiment, during the period when the light detection signal is read out, a positive voltage is applied to the wiring line46. This shifts the threshold of the thin film transistor24in the minus direction. Thus, it is possible to reduce the operating voltage of the thin film transistor24(the voltage applied to the gate electrode28).

Next, Embodiment 3 of the present invention will be described with reference toFIGS. 8, 9, and 10. As shown inFIG. 8, the imaging panel12includes an electrode60, electrode62, and insulating film64.

The electrode60is formed contacting the insulating film38. The electrode60contacts the drain electrode36via the contact hole381. The electrode60is made of a metal such as aluminum (Al), tungsten (W), molybdenum (Mo), tantalum (Ta), chromium (Cr), titanium (Ti), or copper (Cu), or is an alloy of these metals or a metal nitride of these, for example. The electrode60may be a transparent conductive film. The transparent conductive film is indium zinc oxide, for example. The electrode60overlaps the photodiode26when seen from the direction perpendicular to the main surface of the substrate20. The thickness of the electrode60is 50 nm to 200 nm, for example. The electrode60is formed by forming a conductive film via sputtering or the like and then patterning this conductive film via photolithography, for example.

The insulating film64covers the insulating film38and electrode60. The insulating film64is a silicon nitride film, for example. The insulating film64may be a silicon oxide film, or alternatively may be a silicon nitride film and silicon oxide film that have been layered together. The thickness of the insulating film64is approximately 50 nm to 300 nm, for example. The insulating film64is formed by plasma-enhanced CVD, for example. The planarizing film44is formed contacting the insulating film64.

The electrode62is formed contacting the insulating film64. The n-type amorphous silicon layer26A is formed contacting the electrode62. In other words, the photodiode26is formed contacting the electrode62. The electrode62is made of a metal such as aluminum (Al), tungsten (W), molybdenum (Mo), tantalum (Ta), chromium (Cr), titanium (Ti), or copper (Cu), or is an alloy of these metals or a metal nitride of these, for example. The electrode62may be a transparent conductive film. The transparent conductive film is indium zinc oxide, for example. The electrode62overlaps the electrode60when seen from the direction perpendicular to the main surface of the substrate20. The thickness of the electrode62is 50 nm to 200 nm, for example. The electrode62is formed by forming a conductive film via sputtering or the like and then patterning this conductive film via photolithography, for example.

A capacitor66is formed by the electrode60, electrode62, and the portion of the insulating film64positioned between these electrodes60and62. As shown inFIG. 9, the capacitor66is connected in series to the photodiode26. The capacitor66is connected to the drain electrode36.

The operation of the X-ray imaging system of the present embodiment will be explained with reference toFIG. 10.

First, the bias controller14D applies a positive voltage to the wiring line46for a prescribed period (storage period). This stores electric charge in the capacitor66via the photodiode26.

After the prescribed period has passed, the bias controller14D applies a negative voltage to the wiring line46. This applies a reverse bias voltage to the photodiode26. As a result, the electric charge remains stored in the capacitor66.

When the voltage applied to the wiring line46switches from positive to negative, the X-ray controller14E causes the X-ray source16to operate and radiate X-rays for a prescribed period (radiation period). After the prescribed period has passed, the X-ray controller14E causes the X-ray source16to operate and ends the X-ray radiation.

The radiated X-rays enter the scintillator13via the specimen18. The X-rays that have entered the scintillator13are converted to scintillation light. The scintillation light enters the photodiode26. At such time, the electric charge stored in the capacitor66flows out via the photodiode26. In other words, when scintillation light has been detected by the photodiode26, the amount of electric charge stored in the capacitor66decreases. In other words, the electric charge stored in the capacitor66corresponds to the intensity of the scintillation light detected by the photodiode26.

Thereafter, the gate controller14A and signal reader14B read out the light detection signal. In other words, the electric charge stored in the capacitor66is read out. The signal reader14B generates image signals based on the light detection signals that have been read out. The image processor14C generates images based on the image signals that have been generated.

In the present embodiment, as shown inFIG. 10, the radiation period when X-rays are radiated is separate from the reading period when the light detection signals are read out. In other words, the light detection signals are read out when X-rays are not being radiated. Namely, X-rays are radiated intermittently. Thus, it is possible to reduce the amount of exposure of the specimen18.

Furthermore, in the present embodiment, the capacitor66is connected in series to the photodiode26. Thus, when the electric charged stored in the capacitor66is read out, it is possible for the photodiode26to prevent the electric charge from leaking. This makes it possible to improve the quality of the images that are generated based on the electric charge that is read out.

Embodiment 4 of the present invention will be described with reference toFIGS. 11 and 12. As shown inFIG. 11, in the present embodiment as compared to Embodiment 3, the p-type amorphous silicon layer26C is contacting the drain electrode36and intrinsic amorphous silicon layer26B. The n-type amorphous silicon layer26A contacts the intrinsic amorphous silicon layer26B and the electrode40.

The operation of the X-ray imaging system of the present embodiment will be explained with reference toFIG. 12.

First, the bias controller14D applies a negative voltage to the wiring line46for a prescribed period (storage period). This stores electric charge in the capacitor66via the photodiode26.

After the prescribed period has passed, the bias controller14D applies a positive voltage to the wiring line46. This applies a reverse bias voltage to the photodiode26. As a result, the electric charge remains stored in the capacitor66.

When the voltage applied to the wiring line46switches from negative to positive, the X-ray controller14E causes the X-ray source16to operate and radiate X-rays for a prescribed period (radiation period). After the prescribed period has passed, the X-ray controller14E causes the X-ray source16to operate and ends the X-ray radiation.

The radiated X-rays enter the scintillator13via the specimen18. The X-rays that have entered the scintillator13are converted to scintillation light. The scintillation light enters the photodiode26. At such time, the electric charge stored in the capacitor66flows out via the photodiode26. In other words, when scintillation light has been detected by the photodiode26, the amount of electric charge stored in the capacitor66decreases. In other words, the electric charge stored in the capacitor66corresponds to the intensity of the scintillation light detected by the photodiode26.

Thereafter, the gate controller14A and signal reader14B read out the light detection signal (reading period). In other words, the electric charge stored in the capacitor66is read out. The signal reader14B generates image signals based on the light detection signals that have been read out. The image processor14C generates images based on the image signals that have been generated.

In the present embodiment, during the reading period, a positive voltage is applied to the wiring line46. This shifts the threshold of the thin film transistor24in the minus direction. Thus, it is possible to reduce the operating voltage of the thin film transistor24(the voltage applied to the gate electrode28).

The embodiments of the present invention have been described above. However, these are merely examples, and the present invention is not at all limited by the embodiments described above.