Semiconductor device

According to one embodiment, a semiconductor device comprises a circuit board and a semiconductor package mounted on the circuit board. The semiconductor package comprises a semiconductor chip, a first connector on a bottom surface of the semiconductor package and electrically connected to the semiconductor chip, and a metal bump coupled to the first connector and electrically connected to a second connector on the circuit board. The first connector has a contact surface facing the second connector. The contact surface has a recessed portion into which the metal bump extends.

CROSS-REFERENCE TO RELATED APPLICATION(S)

This application is based upon and claims the benefit of priority from Japanese Patent Application No. 2019-047570, filed Mar. 14, 2019, the entire contents of which are incorporated herein by reference.

FIELD

BACKGROUND

A semiconductor package, such as a ball grid array (BGA), includes solder balls coupled to lands of the semiconductor package. Such a semiconductor package is typically mounted on a printed circuit board, and the solder balls are connected to wiring on the printed circuit board.

The semiconductor package contains a semiconductor chip of relatively low thermal expansion. However, the printed circuit board is mostly made of resin of relatively high thermal expansion. Consequently, while temperature causes the printed circuit board to expand and contract by a relatively large amount, the semiconductor package is mainly affected by expansion and contraction of the semiconductor chip because its expansion and contraction is relatively small comparatively. Thus, when a printed circuit board expands/contracts in accordance with temperature variations, a large stress is applied to solder balls by which the semiconductor package has been mounted to the printed circuit board. This stress is due to the difference between the expansion/contraction of semiconductor package and the printed circuit board. The solder balls may be broken or detached from the lands of the semiconductor package by this stress.

DETAILED DESCRIPTION

In general, according to one embodiment, a semiconductor device comprises a circuit board and a semiconductor package mounted on the circuit board. The semiconductor package comprises a semiconductor chip, a first connector on a bottom surface of the semiconductor package and electrically connected to the semiconductor chip, and a metal bump coupled to the first connector and electrically connected to a second connector on the circuit board. The first connector has a contact surface facing the second connector. The contact surface has a recessed portion into which the metal bump extends.

Description will now be made of example embodiments of the present disclosure by reference to the drawings. These example embodiments do not limit the present disclosure. In general, the drawings are schematic and/or conceptual diagrams such that depicted dimensions, relative ratios of the dimensions of parts, do not necessarily coincide with actual devices. In the description and the drawings, substantially the same components previously described or explained are denoted with the same reference numerals and repeated description may be omitted.

While performance of portable electronic terminals, such as smartphones, has been increasing, the demand for size reductions and high-speed operation of packaged semiconductor devices is also increasing. To implement high-speed operation, a semiconductor package typically requires a large number of external terminals for power supply, but at the same time, the semiconductor package generally needs to be reduced in size. In view of these demands, solder bumps are inevitably disposed at the edge portions of the semiconductor package in most cases.

When solder bumps are formed at the edge portions of the semiconductor package, the solder bumps are more likely to come off or be broken during a mounting temperature cycle test (TCT) or operations. The reason is that expansion/contraction between a printed circuit board and the semiconductor package due to temperature changes effectively increases nearer the edge portions of the semiconductor package, and stress applied to the solder bumps at the edge portions likewise increases. Embodiments of the present disclosure can prevent or mitigate this type of stress and prevent or limit the breakage or separation of the lands of the semiconductor package and metal bumps.

First Embodiment

FIG. 1is a cross-sectional view of a semiconductor device according to a first embodiment. A semiconductor device1includes a printed circuit board10and a semiconductor package20. It should be noted that inFIG. 1, recess portions27, which are illustrated inFIGS. 2 and 3, are not specifically depicted.

The printed circuit board10includes resin11, wiring12, and lands13. The resin11is, for example, an insulating material, such as glass epoxy resin, and covers the wiring12. The wiring12is made of, for example, conductive metal, such as copper, and is formed in this example as multi-layer wiring in the resin11. The wiring12is electrically connected to the lands13. The lands13are electrically connected to the wiring12and also connected to solder bumps25of the semiconductor package20. The lands13electrically connect the wiring12and the solder bumps25to each other. Thus, the printed circuit board10is electrically connected to the semiconductor package20with the solder bumps25. The lands13may also be referred to as landings, pads, and/or terminals in some contexts.

The semiconductor package20includes a resin substrate21, a semiconductor chip22, lands23, mold resin24, and the solder bumps25. The resin substrate21includes, for example, an insulating material, such as glass epoxy resin and covers wiring26. The wiring26is made of, for example, conductive metal, such as copper, and is formed, in this example, as multi-layer wiring in resin. The wiring26is electrically connected to the lands23. The semiconductor chip22is disposed on a first surface of the resin substrate21and coated with the mold resin24. Semiconductor elements (not separately illustrated), such as transistors, diodes, resistors, and capacitors, are formed on the semiconductor chip22. The semiconductor chip22can be electrically connected to the wiring26with bonding wires via pads connected to the wiring26. The lands23are disposed on a second surface of the resin substrate21that is opposite to the first surface and are coupled to the solder bumps25. The solder bumps25are disposed between the lands23and the lands13and provide electrical connection therebetween.

FIG. 2is a plan view of a bottom surface of the semiconductor package20according to the first embodiment. The bottom surface of the semiconductor package20faces the printed circuit board10, and the lands23and the solder bumps25are disposed on the bottom surface. InFIG. 2, the solder bumps25are indicated with dashed lines, and the lands23and the recess portions27beneath the solder bumps25are illustrated.

The semiconductor package20includes the lands23in a matrix two-dimensionally arranged on the bottom surface. The solder bumps25are each in contact with one of the lands23. A substantially central portion of a contact surface of each of the lands23has a recess portion27, also referred to as a countersink27in some contexts. As viewed from the bottom surface of the semiconductor package20, each recess portion27has a substantially similar shape as the corresponding land23and is inside of the land23. For example, the recess portion27has a substantially circular shape similar to the shape of the land23. In other non-limiting examples, the shapes of the land23and the recess portion27, as viewed from the bottom surface of the semiconductor package20, may be a substantially elliptic shape, a substantially polygonal shape, and a substantially semicircular shape.

FIG. 3is a cross-sectional view of part of the semiconductor package20, taken along the line3-3inFIG. 2. Resin material28, which is a portion of the resin substrate21, covers the bottom surface of the semiconductor package20except for the lands23. Examples of the resin material28include solder resist. The lands23are not fully covered with the resin material28and the solder bumps25are in contact with the exposed portion of the lands23. Additionally, each of the lands23includes a recess portion27, which defines part of a contact surface between the land23and the solder bump25. The contact surface between the land23and the solder bump25is formed by the recess portion27and a peripheral portion29(of the lands23) surrounding the recess portion27. The recess portion27is recessed from the peripheral portion29toward the resin substrate21side, and a stepped portion ST is formed between the recess portion27and the peripheral portion29. The land23is in contact with the solder bump25at the recess portion27and the peripheral portion29. The solder bump25is in contact with a surface of the peripheral portion29, an inner side surface of the recess portion27, and a bottom surface of the recess portion27. The solder bump25is thus considered to be in contact with the stepped portion ST.

With this configuration, the land23and the solder bump25have a contact area that is larger than would be the case if the land23was simply flat. Moreover, the stepped portion ST of the land23serves as an anchor point for the solder bump25, which is considered to increase coupling strength between the solder bumps25and the lands23and prevent the stresses applied to the solder bumps25from making the solder bumps25break or separate from the lands23.

FIGS. 4A to 5Bare conceptual diagrams for illustrating aspects of expansion/contraction of the printed circuit board10and the semiconductor package20in accordance with temperature.FIGS. 4A and 4Billustrate the printed circuit board10and the semiconductor package20when the temperature is increased.

When a temperature of the semiconductor device1is raised to, for example, +125° C., the printed circuit board10and the semiconductor package20expand as indicated with the arrows and dashed lines inFIG. 4A. At this time, the semiconductor package20containing the semiconductor chip22generally expands by a smaller degree than the printed circuit board10due to differences in materials or the like. Consequently, as illustrated inFIG. 4B, stress is applied to the solder bumps25. However, according to this embodiment, the lands23each include a recess portion27to prevent the solder bumps25from coming off or being broken from the lands23.

FIGS. 5A and 5Billustrate a state of the printed circuit board10and the semiconductor package20when the temperature is decreased.

When the temperature of the semiconductor device1is lowered to, for example, −25° C., the printed circuit board10and the semiconductor package20contract as indicated with the arrows and dashed lines inFIG. 5A. At this time, the semiconductor package20containing the semiconductor chip22contracts by a smaller degree than the printed circuit board10due to differences in materials or the like. Consequently, as illustrated inFIG. 5B, stress is applied to the solder bumps25. However, according to this embodiment, the lands23each include a recess portions27which helps prevent the solder bumps25from coming off or being broken from the lands23.

It should be noted that although in this first embodiment, the recess portions27have been formed in all of the lands23; however, in other examples, the recess portions27can be formed in only some of the lands23. For example, the recess portions27may be formed in only those lands23on an outer peripheral (edge) portion of the bottom surface of the semiconductor package20since it is these outer lands23to which a relatively larger stress is applied. In other examples, the recess portions27may be formed in only the lands23at the four corners of the bottom surface of the semiconductor package20. In this case, the recess portions27are not formed in the lands23in the central portion of the bottom surface of the semiconductor package20.

Second Embodiment

FIG. 6is a plan view of a bottom surface of the semiconductor package20according to a second embodiment. In the second embodiment, the recess portions27are deviated from the center of the land23in a direction opposite to the arrows A1. That is, the recess portions27are offset from the center of the respective lands23in a direction toward the center of the semiconductor package20. InFIG. 6, for the central land23, no offset of the recess portion27is depicted. The arrows A1indicate directions of stress that the solder bumps25receive from the printed circuit board10when temperature is increased. The recess portions27are offset in the direction reverse to the stress direction A1. The recess portion27is thus deviated in a direction reverse to tensile stress of the solder bump25. This enhances coupling strength between the solder bumps25and the lands23to increase resistance of the solder bumps25to tensile stress.

FIG. 7is a cross-sectional view of part of the semiconductor package, taken along the line7-7inFIG. 6. The recess portion27is offset in a direction reverse to the stress direction A1relative to the center of the land23. Accordingly, the peripheral portion29of the land23is on primarily on the side of the recess portion27in the stress direction A1. This enables the second embodiment to produce substantially the same effect as the first embodiment. This also enhances coupling strength between the solder bumps25and the lands23.

FIG. 8is a plan view of a bottom surface of a semiconductor package20according to a first modification. In this modification, each of the recess portions27is offset from the center of the respective land23in a direction reverse to the arrows A2. The arrows A2indicate directions of stress that the solder bumps25receive from the printed circuit board10when temperature is decreased. In the lands23, the recess portion27is offset from center in a direction opposite to the stress direction A2. That is, the recess portion27is offset from center of the land23in a direction reverse to contraction stress of the solder bump25. This further enhances coupling strength between the solder bumps25and the lands23to increase resistance of the solder bumps25to contraction stress.

FIG. 9is a cross-sectional view of part of the semiconductor package20, taken along the line9-9inFIG. 8. The recess portion27is offset from the center of the land23in a direction reverse to the stress direction A2. The peripheral portion29of the land23is primarily disposed in the stress direction A2of the recess portion27.

Third Embodiment

FIG. 10is a plan view of a bottom surface of a semiconductor package20according to a third embodiment. The third embodiment differs from the second embodiment in that a plan-view shape of each of the recess portions27is substantially semicircular. The rest of the configuration of the third embodiment may be considered to be substantially the same as the corresponding configuration of the second embodiment, with the semicircular recess portions being positioned according to expected stress directions A1. It should be noted that a cross-sectional view taken along the line7-7inFIG. 10appears substantially the same asFIG. 7.

The semiconductor package20with semicircular recess portions27positioned as depicted inFIG. 10produces substantially the same effect as the second embodiment.

FIG. 11is a plan view of a bottom surface of the semiconductor package20according to a second modification. The second modification differs from the above-described first modification in that a plan-view shape of each of the recess portions27is substantially semicircular. The rest of the configuration of the second modification may be considered substantially the same as the corresponding configuration of the first modification. It should be noted that a cross-sectional view taken along the line9-9inFIG. 11appears substantially the same asFIG. 9.

The semiconductor package20with semicircular recess portions27positioned as depicted inFIG. 11produces substantially the same effect as the first modification.

It should be noted that after exposing the lands23from the resin material28, the recess portions27may be formed by processing exposed surfaces of the lands23by lithography and etching techniques. Lithography and etching techniques enable the recess portions27to have desired shapes and sizes, such as depicted in the various example embodiments of the present disclosure. In some examples, the recess portions27may be selectively formed in only some of the lands23rather than every one of the lands23.

Fourth Embodiment

FIG. 12is a cross-sectional view of part of the semiconductor package20according to a fourth embodiment. The cross-sectional view ofFIG. 12corresponds to a cross-sectional view of the semiconductor package20, taken along the line3-3inFIG. 2.

The resin substrate21according to the fourth embodiment includes through vias30at portions corresponding to the position of the lands23. Each of the through vias30extends through the resin substrate21from the top surface to the bottom surface to electrically connect wiring at the top surface and wiring at the bottom surface of the resin substrate21. The through vias30may be formed for all of the lands23or may be formed for only some of the lands23.

Metal material filled in holes formed for the through vias30may be substantially the same material (e.g., copper) as the lands23. When the metal material is filled in each of the holes for the through vias30, the metal material thus filled is normally left with a recessed portion (depression) at a center position of the hole. In the fourth embodiment, this depression is used as the recess portion27. That is, without using lithography and etching techniques, the recess portions27in this fourth embodiment are formed on surfaces of the through vias30. This formation of a recess portion27on the surface of the through vias30provides an anchoring effect to the solder bumps25.

The through vias30may be connected to the wiring of the semiconductor chip22and the printed circuit board10. Additionally, the through vias30or a subset thereof may be dummy vias without electrical connection to active wiring. In this context, dummy vias are electrically floating or grounded vias not in use for any device operations. When the through vias30are dummy vias, these through vias30can be formed in outer peripheral portions or four corners of the bottom surface of the resin substrate21. In such a case, without adopting lithography and etching techniques, the recess portions27may be formed on the through vias30in the peripheral edge portions or four corners.

Lands23formed with through vias30and lands23without through vias30(e.g., lands23as in the first to third embodiments described above) may coexist in the same device. In a similar manner to the lands23in the first to third embodiments, the lands23as non-through connectors are disposed on the bottom surface of the resin substrate21without extending through the resin substrate21, and are connected to the wiring of the resin substrate21. In this case, because the through vias30include the recess portions27, the other (non-through connector) lands23may simply be flat. Alternatively, recess portions27may be formed in various non-through connector lands23using lithography and etching techniques as described above. When the recess portions27are manufactured in lands23in addition to those lands23with the through vias30, the effect of anchoring the solder bumps25can be enhanced.

When the through vias30are dummy vias and formed in outer peripheral portions and corners of the bottom surface of the resin substrate21, the lands23which are non-through connectors can be disposed in a central portion of the bottom surface of the resin substrate21. The lands23in the central portion may or may not include the recess portions27formed by lithography and etching according to considerations of manufacturing costs and required device performance.

FIGS. 13A to 14Care cross-sectional views of the resin substrate21according to the fourth embodiment, illustrating an example of a method of forming the resin substrate21. It should be noted thatFIGS. 13A to 13Cillustrate an example in which wiring is disposed on the top surface and the bottom surface of the resin substrate21. However, in some examples, the wiring may also be disposed inside of the resin substrate21.

First, as illustrated inFIG. 13A, material of the wiring26is deposited on a top surface and a bottom surface of the resin material28. Examples of the resin material28include solder resist. The wiring26is made of a, conductive material, such as copper.

Next, as illustrated inFIG. 13B, a through via hole40is formed. The through via hole40may be formed, for example, by drilling the resin material28from the top surface to the bottom surface. Alternatively, the through via hole40may be formed using lithography and etching techniques.

Next, as illustrated inFIG. 13C, metal film50is formed on surfaces of the wiring26and inner walls of the through via hole40by electrolytic plating or electroless plating. Thus, the wiring26on the top surface and the bottom surface of the resin material28is electrically connected with the through via hole40.

A metal material60is filled in the through via hole40while other regions are masked with photoresist of the like patterned with lithography to leave the via hole40exposed. Examples of the metal material60include conductive metal such as copper. Though not specifically depicted inFIG. 14C, the recess portions27are formed in a top surface and a bottom surface of the metal material60as described with reference toFIG. 12. In general, no additional processing is required to form the recess portions27in the surfaces of the plated metal material60.

Next, as illustrated inFIG. 14A, photoresist70is patterned using lithography. The photoresist70is patterned to cover the regions where the through vias30, the lands23, and bonding pads) are to be formed.

Next, as illustrated inFIG. 14B, using the patterned photoresist70as a mask, portions of the metal film50and the wiring26are etched. Thus, the metal film50, the wiring26, and the metal material60is left in the regions where the through vias30, the lands23, and the bonding pads are to be formed.

Next, as illustrated inFIG. 15, regions other than where the through vias30, the lands23, and the bonding pads are located are coated with solder resist80. The solder resist80does not cover the through vias30, the lands23, and the bonding pads but covers the rest. Next, as illustrated inFIG. 12, the solder bumps25are respectively formed on the through vias30and the lands23. Thus, the resin substrate21according to the fourth embodiment is formed.

The semiconductor chip22is mounted on the resin substrate21, and then the semiconductor chip22and the bonding pads are connected to each other with metal bonding wire or the like. The semiconductor chip22disposed on the resin substrate21along with any bonding wires are encapsulated within the mold resin24. This completes the semiconductor package20. The semiconductor package20can then be mounted on the printed circuit board10, and the solder bumps25are bonded to the lands13of the printed circuit board10by heat treatment.