Wafer level packaging

A method of wafer level packaging includes providing a substrate including a buried oxide layer and a top oxide layer, and etching the substrate to form openings above the buried oxide layer and a micro-electro-mechanical systems (MEMS) resonator element between the openings, the MEMS resonator element enclosed within the buried oxide layer, the top oxide layer, and sidewall oxide layers. The method further includes filling the openings with polysilicon to form polysilicon electrodes adjacent the MEMS resonator element, removing the top oxide layer and the sidewall oxide layers adjacent the MEMS resonator element, bonding the polysilicon electrodes to one of a complementary metal-oxide semiconductor (CMOS) wafer or a carrier wafer, removing the buried oxide layer adjacent the MEMS resonator element, and bonding the substrate to a capping wafer to seal the MEMS resonator element between the capping wafer and one of the CMOS wafer or the carrier wafer.

BACKGROUND

Wafer level packaging (WLP) technology provides for the packaging of semiconductor devices at a wafer level. WLP is employed in a variety of technologies including 3D-integrated circuits (IC), chip scale package (CSP) devices, and micro-electro-mechanical systems (MEMS). Potential advantages of using WLP technology include enhancing electrical properties, providing for increased density, reducing device sizes, reducing costs, and allowing for additional testing at wafer level. However, there are several limitations to the current WLP technology and the integration of the wafer fabrication and packaging processes it provides. The methods of packaging (e.g., protecting the device and providing interconnections to the outside world) may not be compatible with the fabrication processes that are used to form the devices. Furthermore, solutions often require complicated packaging schemes that suffer area penalties.

DETAILED DESCRIPTION

It is understood that several processing steps and/or features of a device may be only briefly described, such steps and/or features being well known to those of ordinary skill in the art. Also, additional processing steps or features can be added, and certain of the following processing steps or features can be removed and/or changed while still implementing the claims. Thus, the following description should be understood to represent examples only, and are not intended to suggest that one or more steps or features is required.

It is further understood that the present disclosure refers generally to WLP to refer to the packaging of a substrate. The substrates described herein may take various forms including but not limited to wafers (or portions thereof) having integrated circuits including those formed by CMOS-based processes, die, micro-electro-mechanical systems (MEMS) substrates, capping substrates, a single substrate with CMOS devices and MEMS devices formed thereon, and the like. In contrast, a carrier wafer may not include an integrated circuit. Furthermore, as described above, specific embodiments may be described herein which are exemplary only and not intended to be limiting. For example, embodiments that refer to a substrate being a MEMS substrate, a CMOS substrate, or the like are exemplary only and not intended to limit the disclosure to any particular technology.

FIG. 1is a flowchart illustrating a method100for wafer level packaging to provide a stand-alone MEMS device or a monolithic semiconductor device-MEMS device in accordance with an embodiment of the present disclosure. The method100begins at block102where a substrate including a buried oxide layer and a top oxide layer is provided. At block104, the substrate is etched to form openings above the buried oxide layer and a MEMS resonator element between the openings. The MEMS resonator element is enclosed within the buried oxide layer, the top oxide layer, and sidewall oxide layers. At block106, the openings are filled with polysilicon to form polysilicon electrodes adjacent the MEMS resonator element. At block108, the top oxide layer and the sidewall oxide layers adjacent the MEMS resonator element are removed. At block110, the polysilicon electrodes are bonded to a semiconductor device, such as one of a complementary metal-oxide semiconductor (CMOS) wafer or a carrier wafer. At block112, the buried oxide layer adjacent the MEMS resonator element is removed. At block114, the substrate is bonded to a capping wafer to seal the MEMS resonator element between the capping wafer and one of the CMOS wafer or the carrier wafer.

Accordingly, method100provides for bonding of a MEMS device between a capping wafer and semiconductor device, such as a CMOS device or a carrier wafer. However, the MEMS device may be bonded to one of various semiconductor devices, and/or other suitable active and/or passive devices. Example semiconductor devices include integrated circuits including a metal-insulator-semiconductor field effect transistor (MOSFET) including complementary MOSFET (CMOS) features, CIS, and/or other suitable active and/or passive devices. In an embodiment, the semiconductor device includes an integrated circuit (or portion thereof) designed and formed using a CMOS-based process. A substrate including a semiconductor device formed using CMOS technology may be referred to herein as a CMOS substrate or a CMOS wafer. A MEMS device or substrate may be a silicon wafer including MEMS features and/or functionalities. A substrate having a device (e.g., integrated circuit) formed by other semiconductor fabrication technologies is also within the scope of the described method.

In another example, the carrier wafer and/or the capping wafer is a silicon wafer. Alternatively or additionally, the substrate of the MEMS device, the semiconductor device, the carrier wafer, and/or the capping wafer may include other elementary semiconductor, such as germanium, or the substrate may include a compound semiconductor, such as silicon carbide, gallium arsenic, indium arsenide, and/or indium phosphide.

Referring now toFIGS. 2A-2L, cross-sectional views are shown of a stand-alone MEMS device or a monolithic semiconductor device-MEMS device at various stages of fabrication in accordance with an embodiment of the present disclosure.FIG. 2Aillustrates a substrate202including a buried oxide layer204and a top oxide layer208. The portion of substrate202between buried oxide layer204and top oxide layer208is denoted by reference number206. In one example, a MEMS device is formed on a silicon-on-insulator (SOI) wafer. Substrate202,206is comprised of single crystal silicon in one example, but may be comprised of other materials and include other structures as noted above.

FIG. 2Billustrates a patterned etch of the top oxide layer208and substrate206to form openings210above buried oxide layer204and a micro-electro-mechanical systems (MEMS) resonator element212between the openings210. The MEMS resonator element212is enclosed within the buried oxide layer204, the top oxide layer208, and sidewall oxide layers214. In one example, an isotropic oxide etcher with CF4etchant gas may be used in conjunction with a patterned photoresist for the patterned etch of the top oxide layer208and substrate206. In one embodiment, the etch process may etch a portion of buried oxide layer204.

FIG. 2Cillustrates a deposition of polysilicon over the openings210to form a polysilicon layer216that fills openings210. In one example, polysilicon layer216has a thickness between about 3 micron and about 4 micron, and is deposited by one of various techniques, such as chemical vapor deposition (CVD), low pressure CVD (LPCVD), and the like, at a temperature between about 800 degrees Celsius and about 1,000 degrees Celsius.

FIG. 2Dillustrates a planarization of the polysilicon layer216to expose top oxide layer208. In one example, polysilicon layer216is planarized by a chemical mechanical polish (CMP) process.

FIG. 2Eillustrates a patterned etch through polysilicon layer216and substrate206to form openings218and polysilicon electrodes220adjacent the MEMS resonator element212. In one example, the polysilicon electrodes220are each formed to have an “L” shape with one leg disposed within opening210and another leg disposed over substrate206.

FIG. 2Fillustrates the formation of plugs222within openings218for the protection of buried oxide layer204. In one example, photoresist plugs are formed as a low viscosity photoresist layer is deposited and etched to control the height of the plugs222within openings218. As illustrated, plugs222are formed to have a height below polysilicon layer216but may be formed to have other heights as applicable. Subsequent processing then removes top oxide layer208and the sidewall oxide layers214to expose the MEMS resonator element212. In one example, top oxide layer208and sidewall oxide layers214are removed by a vapor hydrogen-fluorine (HF) etch.

FIG. 2Gillustrates the MEMS device after plugs222have been removed. In one example, photoresist plugs may be removed by a plasma etch at temperatures between about 200 degrees Celsius and about 300 degrees Celsius.

FIG. 2Hillustrates the MEMS device bonded to a semiconductor device300, which in one embodiment includes a substrate302, a metal layer304, an interlayer dielectric (ILD)306, openings308, and a cavity310. In one example, the MEMS device is fusion bonded to the semiconductor device300at a temperature less than about 480 degrees Celsius, with a bonding force less than about 5N and a bonding time less than about 10 minutes. In yet another example, the semiconductor device300is a CMOS wafer and the polysilicon layer216of the MEMS device is fusion bonded to the ILD306of the CMOS wafer, which provides a stand-off feature with cavity310, the stand-off feature being configured to provide the appropriate separation between the semiconductor device and the MEMS device to which it is to be bonded to. The MEMS resonator element212provides a reference mass that is used to measure the variable to which the MEMS is directed. Alternatively, the semiconductor device300may be a carrier wafer including a stand-off feature and may not include an integrated circuit. Advantageously, the present disclosure provides a wafer level packaging scheme applicable to the fabrication of both a stand-alone MEMS device or a monolithic semiconductor device-MEMS device.

FIG. 2Iillustrates removal of the substrate202and a subsequent etch through buried oxide layer204, substrate206, and polysilicon electrodes220to form openings224which connect to openings308. In one example, substrate202may be removed by a wet etch process, such as etching in a tetramethylammonium hydroxide (TMAH) wet etch tank. In another example, openings224have a wider diameter than openings308.

FIG. 2Jillustrates the formation of plugs226in openings224and308to provide an electrical connection between polysilicon electrode220and metal layer304of the semiconductor device300. In one example, plugs226are comprised of tungsten and shaped to have a smaller diameter portion disposed within opening308and a wider diameter portion disposed within opening224. Openings218provide for electrical isolation of plugs226. A metal layer is deposited and then etched back to form plugs226within openings224and308, and in one example, a tungsten layer is deposited by CVD at a process temperature less than about 500 degrees Celsius. Other deposition techniques are applicable and may be used.

FIG. 2Killustrates the formation of a bonding layer228on buried oxide layer204, which is subsequently removed adjacent MEMS resonator element212, as shown and described below with respect toFIG. 2L. The bonding layer228may be patterned by a wet etch process in one example. Alternatively, portions of the buried oxide layer204adjacent the MEMS resonator element212may be removed prior to formation of the bonding layer228on a remaining portion of buried oxide layer228.

FIG. 2Lillustrates the removal of buried oxide layer204to release MEMS resonator element212. In one example, buried oxide layer204is removed by a vapor HF etch. Substrate206is then bonded to a capping wafer400to seal the MEMS resonator element212between the capping wafer400and the semiconductor device300. In other words, MEMS device200is sandwiched between capping wafer400and semiconductor device300, which in one example is one of a CMOS wafer or a carrier wafer, and MEMS resonator element212is sealed within a cavity between semiconductor device300and capping wafer400, both of which may include stand-off features for formation of the cavity for the MEMS resonator element212.

According to one aspect, the bonding layer228may be comprised of a metal and/or silicon. Examples of the bonding layer compositions include amorphous silicon, polysilicon, a combination of amorphous silicon and polysilicon, silicon doped with one or more impurities, and other suitable substantially silicon-based compositions. The bonding layer may be formed by physical vapor deposition (PVD), chemical vapor deposition (CVD), evaporation, electron beam evaporation (E-gun), ion beam, energy beam, combinations thereof, and/or other suitable deposition processes. Other manufacturing techniques used to form the bonding layer may include photolithography processing and/or etching to pattern the bonding layer. In another embodiment, the bonding layer228includes aluminum or a substantially aluminum-based bonding layer, which may also be formed by one of various techniques, such as PVD, CVD, or the like as noted above.

Bonding layer228is bonded to capping wafer400by a bonding process. In particular, the bonding layer228is bonded to a surface of the capping wafer400, which in one embodiment may include another bonding layer. Thus, bonding layer228, which may include silicon, is bonded to a bonding layer of the capping wafer, which may include aluminum. In doing so, the bonding layer of the MEMS device300and the bonding layer of the capping wafer400are physically bonded (e.g., coupled). The bonding may be provided by a solid-phase reaction. In one example, bonding layer228is eutectic bonded to capping wafer400with a bonding force greater than about 15 kN at a temperature greater than about 400 degrees Celsius. In another example, bonding layer228may include a metal and the bonding layer of the capping wafer400may include silicon. Accordingly, in one embodiment a substantially silicon-based bonding layer may be provided on a MEMS substrate and a substantially aluminum-based bonding layer may be provided on the capping substrate, and in another embodiment, a substantially silicon-based bonding layer is disposed on the capping substrate and a substantially aluminum-based bonding layer is disposed on the MEMS substrate.

The bonding process may be performed in the presence of a forming gas and/or another controllable environment. Example forming gases include argon, nitrogen (N2), hydrogen (H2), nitrogen/hydrogen mixture, and/or other suitable gases. The forming gases may serve to de-oxidize the bonding layer(s).

In an embodiment, a surface clean is performed prior to the bonding process. In other embodiments, the surface cleaning step may be omitted. The surface clean may include a wet etch, a dry etch, or combinations thereof. Example wet etch/clean processes include exposure to hydrofluoric acid (HF) including dilute HF. Example dry etch processes include argon sputtering and plasma etch processes. The cleaning process may include other suitable processes such as de-ionized water rinses and drying processes (e.g., spin dry). The clean may serve to de-oxidize the bonding layer(s). In an embodiment, a post-bonding thermal process is performed (e.g., anneal). The bonding may be performed by a commercially available wafer bonder, and an alignment process is typically performed prior to the bonding process.

Referring now toFIGS. 3A-3F, cross-sectional views are shown of a stand-alone MEMS device or a monolithic semiconductor device-MEMS device at various stages of fabrication in accordance with another embodiment of the present disclosure.

FIG. 3Aillustrates substrates202,206including buried oxide layer204, polysilicon layer216, openings218, polysilicon electrodes220, and MEMS resonator element212. The structure shown inFIG. 3Ais fabricated by substantially the same steps and processes and include substantially similar structures as illustrated in and described above with respect toFIGS. 2A-2G. As such, the steps and structures for fabrication of the structure shown inFIG. 3Aare not repeated here but are fully applicable in this embodiment.

FIG. 3Billustrates a patterned etch of polysilicon electrode220and substrate206to form an opening230above the buried oxide layer204. Typical photolithographic patterning and etch techniques may be used. Afterwards, an aluminum nitride (AlN) film232is deposited and patterned over the opening230, and in one example the AlN film is deposited in a deposition process temperature below about 550 degrees Celsius, and patterned by a wet etch.

Similar toFIG. 2Habove,FIG. 3Cillustrates the MEMS device bonded to a semiconductor device300, which in one embodiment includes a substrate302, a metal layer304, an interlayer dielectric (ILD)306, openings308, and a cavity310. In one example, the MEMS device is fusion bonded to the semiconductor device300at a temperature less than about 480 degrees Celsius. In yet another example, the semiconductor device300is a CMOS wafer and the polysilicon layer216of the MEMS device is fusion bonded to the ILD306of the CMOS wafer, which provides a stand-off feature with cavity310, the stand-off feature being configured to provide the appropriate separation between the semiconductor device and the MEMS device to which it is to be bonded to. The MEMS resonator element212provides a reference mass that is used to measure the variable to which the MEMS is directed. Alternatively, the semiconductor device300may be a carrier wafer including a stand-off feature and may not include an integrated circuit. Advantageously, the present disclosure provides a wafer level packaging scheme applicable to the fabrication of both a stand-alone MEMS device or a monolithic semiconductor device-MEMS device.

Similar toFIG. 2Iabove,FIG. 3Dillustrates removal of the substrate202and a subsequent etch through buried oxide layer204, substrate206, and polysilicon electrodes220to form openings224which connect to openings308. In one example, substrate202may be removed by a wet etch process, such as etching in a tetramethylammonium hydroxide (TMAH) wet etch tank. In another example, openings224have a wider diameter than openings308.

Similar toFIG. 2Jabove,FIG. 3Eillustrates the formation of plugs226in openings224and308to provide an electrical connection between polysilicon electrode220and metal layer304of the semiconductor device300. In one example, plugs226are comprised of tungsten and shaped to have a smaller diameter portion disposed within opening308and a wider diameter portion disposed within opening224. Openings218provide for electrical isolation of plugs226. A metal layer is deposited and then etched back to form plugs226within openings224and308, and in one example, a tungsten layer is deposited by CVD at a process temperature less than about 500 degrees Celsius. Other deposition techniques are applicable and may be used.

Finally, similar toFIGS. 2K and 2Labove,FIG. 3Fillustrates the formation of a bonding layer228on buried oxide layer204, which is subsequently removed adjacent MEMS resonator element212. The bonding layer228may be patterned by a wet etch process in one example. Alternatively, portions of the buried oxide layer204adjacent the MEMS resonator element212may be removed prior to formation of the bonding layer228on a remaining portion of buried oxide layer228. The removal of buried oxide layer204releases MEMS resonator element212. In one example, buried oxide layer204is removed by a vapor HF etch. Substrate206is then bonded to a capping wafer400to seal the MEMS resonator element212between the capping wafer400and the semiconductor device300. In other words, MEMS device200is sandwiched between capping wafer400and semiconductor device300, which in one example is one of a CMOS wafer or a carrier wafer, and MEMS resonator element212is sealed within a cavity between semiconductor device300and capping wafer400, both of which may include stand-off features for formation of the cavity for the MEMS resonator element212.

Referring now toFIGS. 4A-4L, cross-sectional views are shown of a stand-alone MEMS device or a monolithic semiconductor device-MEMS device at various stages of fabrication in accordance with another embodiment of the present disclosure.

FIG. 4Aillustrates substrates202,206including buried oxide layer204, polysilicon layer216, and MEMS resonator element212enclosed by top oxide layer208, buried oxide layer204, and sidewall oxide layers214.FIG. 4Ais fabricated by substantially the same steps and processes and includes substantially similar structures as illustrated in and described above with respect toFIGS. 2A-2D. As such, the steps and processes for fabrication of the structure shown inFIG. 4Aare not repeated here but are fully applicable in this embodiment.

FIG. 4B-4Eillustrate a patterned etch of the polysilicon layer216and substrate206to form opening218, formation of a plug222within opening218, removal of the top oxide layer208and sidewall oxide layers214, and removal of the plug222, similar to the processes illustrated in and described above with respect toFIGS. 2E-2G. In this embodiment, opening218is formed on only one side of the MEMS resonator element212and an opening234is formed above substrate206on the other side of the MEMS resonator element212.

FIG. 4Fillustrates a further etch of the polysilicon layer216to form opening236and a subsequent deposition and patterning of an aluminum nitride (AlN) film238over the opening236. Polysilicon layer216may be patterned by an isotropic etch to form opening236and the AlN film238may be deposited by one of various processes under a temperature of about 550 degrees Celsius. The AlN film238may then be patterned by a wet etch.

FIG. 4Gillustrates the deposition and patterning of an aluminum film240above the AlN film238. In one example, the aluminum film240is deposited by one of various deposition processes under a temperature of about 250 degrees Celsius, and patterned as an upper electrode by a wet etch process.

Similar toFIG. 2Habove,FIG. 4Hillustrates illustrates the MEMS device bonded to a semiconductor device350, which in one embodiment includes a substrate302, a metal layer304, an interlayer dielectric (ILD)306, openings308, and a cavity310. In one example, the MEMS device is fusion bonded to the semiconductor device350at a temperature less than about 480 degrees Celsius. In yet another example, the semiconductor device350is a CMOS wafer and the polysilicon layer216of the MEMS device is fusion bonded to the ILD306of the CMOS wafer, which provides a stand-off feature with cavity310, the stand-off feature being configured to provide the appropriate separation between the semiconductor device and the MEMS device to which it is to be bonded to. The MEMS resonator element212provides a reference mass that is used to measure the variable to which the MEMS is directed. Alternatively, the semiconductor device350may be a carrier wafer including a stand-off feature and may not include an integrated circuit. Advantageously, the present disclosure provides a wafer level packaging scheme applicable to the fabrication of both a stand-alone MEMS device or a monolithic semiconductor device-MEMS device.

Similar toFIG. 2Iabove,FIG. 4Iillustrates removal of the substrate202and a subsequent etch through buried oxide layer204, substrate206, and polysilicon electrodes220to form openings224which connect to openings308. In one example, substrate202may be removed by a wet etch process, such as etching in a tetramethylammonium hydroxide (TMAH) wet etch tank. In another example, openings224have a wider diameter than openings308.

Similar toFIG. 2Jabove,FIG. 4Jillustrates the formation of plugs226in openings224and308to provide an electrical connection between polysilicon electrode220and metal layer304of the semiconductor device300. In one example, plugs226are comprised of tungsten and shaped to have a smaller diameter portion disposed within opening308and a wider diameter portion disposed within opening224. Openings218provide for electrical isolation of plugs226. A metal layer is deposited and then etched back to form plugs226within openings224and308, and in one example, a tungsten layer is deposited by CVD at a process temperature less than about 500 degrees Celsius. Other deposition techniques are applicable and may be used.

Similar toFIG. 2Kabove,FIG. 4Killustrates the formation of a bonding layer228on buried oxide layer204, which is subsequently removed adjacent MEMS resonator element212. The bonding layer228may be patterned by a wet etch process in one example. Alternatively, portions of the buried oxide layer204adjacent the MEMS resonator element212may be removed prior to formation of the bonding layer228on a remaining portion of buried oxide layer228. The removal of buried oxide layer204releases MEMS resonator element212. In one example, buried oxide layer204is removed by a vapor HF etch.

Finally, similar toFIG. 2Labove,FIG. 4Lillustrates substrate206bonded to a capping wafer400to seal the MEMS resonator element212between the capping wafer400and the semiconductor device300. In other words, MEMS device200is sandwiched between capping wafer400and semiconductor device300, which in one example is one of a CMOS wafer or a carrier wafer, and MEMS resonator element212is sealed within a cavity between semiconductor device300and capping wafer400, both of which may include stand-off features for formation of the cavity for the MEMS resonator element212.

The formation of the piezoelectric on silicon illustrated inFIGS. 3A-3Fmay be advantageously used in various devices such as resonators, actuators (e.g., switches), and energy harvesting devices. The formation of the suspended piezoelectric illustrated inFIGS. 4A-4Lmay be advantageously used in film acoustic wave devices.

One or more of the described embodiments may provide advantages over the prior art. The fusion bonding of a MEMS device to a semiconductor device allows for the creation of a robust electrical and mechanical interface between the two substrates. Further, the eutectic bonding of the MEMS device to a capping wafer allows for the creation of a hermetic seal without area loss and without the addition of any process layers to the semiconductor device, such as a CMOS substrate. The present disclosure further provides for a simple and flexible wafer packaging scheme for the fabrication of both a MEMS stand-alone device and a monolithic MEMS device-semiconductor device.

Although the embodiments illustrated herein may describe and/or illustrate a single bonding layer deposited on a substrate, this is not required and any plurality of layers may be patterned to form one or more bonding regions between substrates or devices.

Thus, the present disclosure provides a method for wafer level packaging to provide a stand-alone micro-electro-mechanical systems (MEMS) device or a monolithic semiconductor device-MEMS device. In one embodiment, a method includes providing a substrate including a buried oxide layer and a top oxide layer, and etching the substrate to form openings above the buried oxide layer and a micro-electro-mechanical systems (MEMS) resonator element between the openings, the MEMS resonator element enclosed within the buried oxide layer, the top oxide layer, and sidewall oxide layers. The method further includes filling the openings with polysilicon to form polysilicon electrodes adjacent the MEMS resonator element, removing the top oxide layer and the sidewall oxide layers adjacent the MEMS resonator element, bonding the polysilicon electrodes to one of a complementary metal-oxide semiconductor (CMOS) wafer or a carrier wafer, removing the buried oxide layer adjacent the MEMS resonator element, and bonding the substrate to a capping wafer to seal the MEMS resonator element between the capping wafer and one of the CMOS wafer or the carrier wafer.

The present disclosure also provides a semiconductor device. In one embodiment, the device includes a micro-electro-mechanical systems (MEMS) device including polysilicon electrodes adjacent a resonator element, one of a complementary metal-oxide semiconductor (CMOS) wafer or a carrier wafer fusion bonded to a first surface of the MEMS device, and a capping wafer eutectically bonded to a second surface of the MEMS device, the resonator element sealed between the capping wafer and one of the CMOS wafer or the carrier wafer.

Although embodiments of the present disclosure have been described in detail, those skilled in the art should understand that they may make various changes, substitutions and alterations herein without departing from the spirit and scope of the present disclosure. Accordingly, all such changes, substitutions and alterations are intended to be included within the scope of the present disclosure as defined in the following claims. In the claims, means-plus-function clauses are intended to cover the structures described herein as performing the recited function and not only structural equivalents, but also equivalent structures.