Data multiplex control facility

A data processing system includes a central processing unit (CPU), an input/output microprocessor, a main memory and a number of mass storage controllers. A block of information is transferred between one of the mass storage controllers and main memory during data multiplex control (DMC) cycles. The CPU includes registers which store the address of main memory into which the next data byte is written or read from and the range indicating the number of data bytes remaining to be transferred. Prior to a DMC cycle the CPU stores address and range information in a mailbox location in an I/O RAM and the I/O microprocessor transfers that information to channel table locations in the I/O RAM. For a DMC operation, the I/O microprocessor transfers the address and range information to the mailbox location and transfers the mass storage information to the mass storage controller. It signals a CPU interrupt and issues a read or write order to the mass storage controller. The CPU then retrieves the address and range information from the mailbox location and initiates a DMC cycle.

RELATED APPLICATIONS 
The following U.S. patent application filed on an even date with the 
instant application and assigned to the same assignee as the instant 
application is related to the instant application and is incorporated 
herein by reference. 
"Speeding Up the Response Time of the Direct Multiplex Control Transfer 
Facility" by James W. Stonier, Thomas L. Murray, Jr., Gary J. Goss and 
Thomas O. Holtey, filed on June 13, 1983 and having U.S. Ser. No. 503,962. 
BACKGROUND OF THE INVENTION 
1. Field of the Invention 
This invention generally relates to data processing systems and more 
specifically to the interchange of data between a mass storage controller 
and the main memory in such data processing systems. 
2. Description of the Prior Art 
A data processing system usually includes a central processing unit (CPU) 
which executes software instructions which are stored at addresses, or 
locations, in main memory. These software instructions are transferred to 
the CPU sequentially under the control of a program counter. The data that 
is processed is transferred into and out of the system by way of 
input/output devices, or peripheral devices such as teletypewriters, 
magnetic disks, magnetic tapes or line printers. Usually the data is 
temporarily stored in the main memory before or after the processing by 
the central processing unit. 
In a system having a plurality of devices coupled over one or more common 
buses, an orderly system must be provided by which bidirectional transfer 
of information may be provided between such devices. This problem becomes 
more complicated when such devices include, for example, one or more 
memory units and various peripheral devices. 
Various methods and apparatus are known in the prior art for 
interconnecting such a system. Such prior art systems range from those 
having common data bus paths to those which have special paths between 
various devices. Such systems also may include a capability for either 
synchronous or asynchronous operation in combination with the bus type. 
Some of these systems, independent of the manner in which such devices are 
connected or operate, require the central processor's control of any such 
data transfer on the bus even though, for example, the transfer may be 
between devices other than the central processor. In addition, these 
systems normally include various parity checking apparatus, priority 
schemes and interrupt structures. One such structural scheme is shown in 
U.S. Pat. No. 3,866,181. A data processing system utilizing a common 
asychronous communication bus is shown in U.S. Pat. No. 3,886,524. Another 
in which all units in the system, including the memory, are connected in 
parallel is shown in U.S. Pat. No. 3,710,324. The manner in which 
addressing is provided in such systems as well as the manner in which, for 
example, any one of the devices may control the data transfer is dependent 
upon the implementation of the system, i.e., whether there is a common 
bus, whether the operation thereof is synchronous or asynchronous, etc. 
The system's response and throughput capability are greatly dependent on 
those various structures. A particular structured scheme is shown in U.S. 
Pat. No. 3,993,981; U.S. Pat. No. 3,995,258; U.S. Pat. No. 3,997,896; U.S. 
Pat. No. 4,000,485; U.S. Pat. No. 4,001,790; and U.S Pat. No. 4,030,075 
which describe an asynchronously operated common bus. 
There are several ways to transfer data between a peripheral device and a 
main memory unit. Two popular methods are implemented by transferring data 
from/to the peripheral device through the CPU to/from main memory or 
directly from/to the peripheral device to/from the main memory. 
Programmed I/O 
In the first method, commonly called programmed I/O, the input/output 
transfer is done under the control of the software program being executed 
within the central processing unit. For example, to input a character from 
a teletypewriter peripheral, a software program executed within the CPU 
would be written such that it would execute one or more software 
instructions to first input the character entered by the teletypewriter 
peripheral into a register within the CPU such as the accumulator, and 
then a subsequent software instruction would store the contents of the 
accumulator into a specified main memory location. Thus, the input 
transfer would have taken place under software control with the data 
passing through the CPU. Similarly, on output the data would first be 
loaded from main memory into the accumulator by one software instruction 
and then output from the accumulator to the teletypewriter peripheral by 
one or more subsequent software input/output instructions. Variations of 
this method are known in which the software program either loops, checking 
the status of an indicator to determine whether the input/output transfer 
has been completed between the CPU and the peripheral device, or 
alternatively, the completion of the transfer may be signalled by a 
software interrupt initiated by the peripheral device. In either case, 
this method is inefficient in that it requires the attention of a software 
program in the CPU to each individual character as it is transferred 
between the peripheral device and the CPU. Nevertheless, this method is 
often used for a low-speed peripheral device because this method usually 
results in the reduction in the amount of logic needed within the 
input/output controller to which the peripheral device is attached. 
Direct Memory Transfers 
Direct memory transfers, the second method, permits large quantities of 
data to be moved between the main memory and the peripheral device with 
greatly increased efficiency. Using the direct memory transfer method, the 
software program within the CPU initiates the transfer of a group of 
information and once initiated the transfer takes place between the 
peripheral device and the main memory without further intervention. Using 
this method, the software program initiates a transfer by indicating the 
peripheral device to which the transfer data to be input from or output to 
the starting address in main memory to which the data is to be transferred 
to or from, the number of characters or words of data to be transferred in 
the group or block. Then, once the transfer is initiated, the transfer 
takes place on a character by character, word by word basis directly 
between the peripheral device and the main memory unit without further 
software intervention. Once the last character or word of the group has 
been transferred, the software in the CPU is notified either by 
continually checking a status indicator or upon receipt of an interrupt 
and the software program may then process the transferred data or initiate 
another transfer. This second method (direct memory transfers) is more 
efficient than the first method (programmed I/O) and frees the CPU for the 
execution of software during the time that the input/output transfer is 
taking place. This increase in efficiency is offset by the additional 
logic required within the system to hold the starting main memory address 
and the number of characters or words (range) of data to be transferred in 
the block. 
There are several places within the data processing system where this added 
logic for direct memory transfer may be placed. For example, this added 
logic is often placed within the input/output controller (IOC) to which 
the peripheral device is attached by placing a starting address register 
and a range counter within the IOC. In this method, which is commonly 
called Direct Memory Access (DMA), when the software initiates the 
transfer, the starting addrass is transferred from the CPU to the starting 
address register within the IOC and the block size (range) is also 
transferred to the range register within the IOC. The IOC then contains 
sufficient logic so that the address may be incremented by one as each 
word is transferred between the peripheral device and the main memory, and 
the range may be, for example, counted down until it reaches zero 
indicating the end of the group has been transferred. In addition, the IOC 
must contain sufficient logic to interface directly with the main memory. 
This interface logic in the IOC may provide the needed read/write main 
memory signals and may provide for the handling of exception conditions 
such as main memory busy, addressing a nonexistent memory location, and 
resolution of conflicts between the IOC and other units (the CPU or 
another IOC) competing for the same resource (such as the system (I/O) bus 
or main memory). 
Thus, it can be seen that the logic within the IOC is increased by having 
to provide the address and range registers along with decrementing and 
incrementing logic and the main memory interface logic. 
An article entitled "DMA Controller Capitalizes on Clock Cycles to Bypass 
CPU" by Joseph Nissim describing direct memory access can be found in the 
January, 1978, issue of Computer Design. 
Data Multiplex Control 
Alternatively, another direct memory transfer method known as Data 
Multiplex Control (DMC) is found on Honeywell Information Systems DDP-516 
computer. In that particular DMC, rather than placing the address range 
registers within the I/O controller, a starting address and ending address 
are contained in two locations within main memory which are dedicated to 
the particular channel to which the peripheral device is attached, there 
being 16 separate channels using a total of 32 locations in main memory. 
In addition, other logic is present within the system which is multiplexed 
between the 16 channels to increment the starting address as each word is 
transferred and to compare the incremented starting address with the 
ending address to see whether the last word of the group is being 
transferred. Using the data multiplex control method, an input/output 
transfer is initiated by the software for storing the starting address 
into the channel's main memory location and then storing the ending 
address into the channel's main memory location using non-I/O software 
instructions. After the starting and ending address main memory locations 
have been initiated, the program then executes one or more I/O software 
instructions which actually initiate the transfer of data between the 
peripheral device and main memory. Once initiated, each time the 
peripheral device determines that it requires another word of data to be 
sent to or from the main memory, it signals the DMC logic on a unique line 
associated with and dedicated to the particular channel on which the 
peripheral device is assigned. The DMC logic then prioritizes these 
transfer request signals among the one or more channels that are 
requesting and requests the CPU to break at the end of the current 
software instruction. 
Once the break request is honored, at the end of the current software 
instruction, software execution is halted and the DMC logic takes over 
control of the system for four main memory cycles. During the first main 
memory cycle, the contents of the starting address location are fetched 
from main memory and stored in the address counter register of the DMC 
logic. The channel number corresponding to the data transfer request from 
the peripheral device is used to determine which main memory location 
contains the starting address for the particular peripheral device making 
the data transfer. During the second main memory cycle, the contents of 
the ending address location in main memory are fetched and compared with 
contents of the address counter register by the DMC logic. If the contents 
are equal, an end-of-range indicator is set and no data transfer takes 
place. During the third main memory cycle, the data transfer takes place 
between the peripheral device and main memory and is controlled by the 
contents of the address counter register within the DMC logic. 
The direction of the transfer, whether input (from the peripheral device to 
main memory) or output (from main memory to the peripheral device), is 
determined by a bit within the main memory location containing the 
starting address. This bit is also transferred to the address counter 
register when the starting address is transferred from memory to the DMC 
logic. During this third main memory cycle, the contents of the address 
counter register are used to address the main memory with the contents of 
the addressed location either being read from main memory and transferred 
to the peripheral device or the word from the peripheral device being 
stored into the addressed location in main memory. During this main memory 
cycle, the contents of the address counter register are incremented by 
one. During the fourth and final main memory cycle, the contents of the 
address counter register are stored in the channel's starting address 
location within main memory. If another data transfer request is waiting, 
another data transfer cycle starts. If no register is waiting, the CPU 
resumes control and the previously halted software program resumes 
execution at the next software instruction. 
During the first main memory cycle, the DMC logic sets a unique device 
address line which informs the peripheral device that the current 
input/output transfer is being conducted on its behalf. There are 16 
device address lines, one of each of the 16 channels, and the setting of 
the line during the first main memory cycle is used by the peripheral 
device's IOC during the third main memory cycle to either place data from 
the peripheral device on the bus for transfer to main memory or to take 
data from the I/O bus, placed there by main memory, and output it to the 
peripheral device. 
During the end of the CPU's execution of a software instruction, the DMC 
logic performs a synchronization cycle. During the synchronization cycle, 
a priority network within the data multiplex control logic determines if 
any channel is making a data transfer request, and if so, determines the 
highest priority request of the one or more channels requesting a 
transfer. If any peripheral connected to the DMC logic is requesting a 
data transfer, the DMC logic informs the CPU that a data transfer break is 
required. 
Although this data multiplex control method of direct transfer is more 
efficient than the programmed control method, it has the disadvantage that 
four separate main memory transfer cycles are required and that the 
software execution is suspended during these four main memory cycles. In 
addition, the data transfer may only occur at the end of the software 
instruction thus lengthening the response to a data transfer request in 
the event of a software instruction which has a long execution time. 
Further, since there must be one data request line and one device address 
line per channel, this method results in the widening of the input/output 
bus connecting the peripherals, device controllers and the central 
processor and main memory by requiring two lines per available channel. 
Direct Memory Access 
Within the Honeywell DDP-516 computer system, the Direct Memory Access 
(DMA) method of direct transfer discussed above is also used for some I/O 
controllers. The DDP-516 DMA provides a direct, high-speed path for a 
periphe device to the main memory for up to four channels. To effect a 
transfer, the DMA logic causes breaks between CPU cycles without regard to 
the end of the software instruction being processed by the CPU. The 
initiation and termination of the DMA cycle is controlled by the 
peripheral device request lines. I/O software instructions are used for 
loading the address and range counters of the DMA control logic and for 
reading the contents of the range counters. The DMA control logic contains 
a priority network for determining the priority of the active DMA requests 
from the peripheral devices and the logic for initiating and controlling 
the DMA cycle. 
The DDP-516 DMA control logic provides the CPU with an alternate memory 
register and an alternate memory address register. DMA data transfers take 
place through the alternate memory register without disturbing the 
contents of the normal CPU memory register. The contents of the CPU memory 
address register are temporarily shuttled into the alternate memory 
address register and then returned upon completion of the DMA cycle. These 
registers give the DDP-516 DMA its cycle-stealing ability and allow it, 
for example, to break between the fetch and execution cycles of a software 
instruction. 
Addresses are multiplexed into the CPU memory address register from one of 
four DMA channels. Each channel has a 16-bit hardware address counter 
which stores the starting address. The high order bit of the starting 
address is used to specify an input or output mode. The remainin 15 bits 
specify the main memory address from or to which the first DMA data 
transfer will take place. 
In addition, each DMA channel has a 16-bit hardware range counter which 
stores the two's complement of the size of the block of data to be 
transferred. Both the address counter and the range counter are 
incremented each time a DMA data transfer takes place. Overflow of the 
range counter signifies completion of the group transfer by generating an 
end-of-range signal which disables the peripheral device and can be used 
to cause a software program interrupt. In addition, the contents of the 
range counter can be read into the CPU under software program control to 
determine, at any time, the number of words remaining to be transferred. 
DMA channels have their address and range information loaded under 
software program control by the I/O bus of the computer system. Unique I/O 
software instructions are provided to load each. 
Peripheral devices are connected to the DMA control logic via the DMA bus. 
Similar to the I/O bus, the DMA bus contains 16 input lines, 16 output 
lines, and various control lines. Data is transferred in parallel directly 
to main memory from the data buffer in the peripheral device interface. 
The DMA has top priority in a system and therefore takes precedence over 
any other operations such as a DMC data transfer request, priority 
interrupt processing, or real-time block incrementation. When a peripheral 
device is ready to transfer data, it makes a DMA request. If two DMA 
requests occur simultaneously, the lowest numbered DMA channel will be 
acknowledged first. 
A DMA request causes a break in the CPU processing of the software at the 
next CPU cycle, if it occurs in sufficient time prior to the start of the 
next CPU cycle. A DMA break can occur between fetch and execute phases of 
a software instruction or it could, for example, happen between DMC data 
transfer cycles. Once the DMA break has been initiated, the DMA cycles 
will continue to occur as long as further DMA requests are received in 
sufficient time prior to the end of the current CPU cycle. A DMA break 
effects the CPU only to the extent that it requires main memory cycles. If 
a DMA request should cause a DMA break during that portion of a software 
instruction not requiring a main memory cycle, the processing of the 
software instruction will continue uninterrupted. DMA data transfers occur 
independently of the software program. However, I/O software instructions 
are provided to load the address counter and range counter in order to set 
up a DMA transfer. I/O software instructions are also provided to monitor 
the range counter in order to determine, at any time, how many words of 
data remain to be transferred between the DMA peripheral device and main 
memory. 
A DMA cycle is activated by a peripheral device DMA request. The DMA 
control logic priority network determines the request priority and enables 
the proper DMA channel logic. The contents of the CPU memory address 
register are transferred to the alternate memory address register for 
preservation. The DMA cycle starts a main memory cycle, which is a read or 
write cycle depending upon the high order bit of the address counter. The 
CPU memory address register is cleared and the contents of the address 
counter representing the address to be accessed in the first DMA cycle are 
placed in the CPU memory address register. The address counter is then 
incremented to form the address for the next DMA cycle. For a DMA read 
cycle, the contents of the addressed memory location are inhibited from 
the CPU memory register and placed in the alternate memory register. The 
alternate memory register is then transferred to the 16 output lines and 
from there to the external peripheral device. For a DMA write cycle, the 
external peripheral device data is transferred from the peripheral device 
to the alternate memory register via the 16 input lines and from the 
alternate memory register to the addressed main memory location. 
If end-of-range is reached, the peripheral device disables its DMA request 
lines and DMA transfers from the channel are terminated. End-of-range is 
detected by the DMA control logic determining if the range counter equals 
all binary ONE's. The contents of the range counter are then incremented. 
The DMA control logic again searches its DMA request lines. If any are 
active, it causes another DMA cycle. If no DMA request exists, the DMA 
control logic returns the control to the CPU after transferring the 
contents of the alternate memory address register into the CPU memory 
address register. 
Thus it can be seen that the Honeywell DDP-516 computer software programmer 
when programming an input/output transfer must be cognizant of whether the 
I/O controller for the peripheral device is a Direct Memory Access (DMA) 
IOC or a Data Multiplex Control (DMC) IOC. This cognizance is required 
because of the way in which the software initiates the data transfer. In 
the case of a DMC type IOC, the software programmer must store the address 
information within the main memory using non-I/O software instructions and 
then initiate the transfer by giving the peripheral devices' IOC a go 
signal using an I/O software instruction; whereas in the case of a DMA 
type IOC, the software programmer sends the address information to the DMA 
by using I/O software instructions and then initiates the data transfer 
with another I/O software instruction. This presents a problem in that, 
for example, a serial line printer because of the relatively low transfer 
rate of the data may be controlled by a DMC type IOC, whereas a high-speed 
line printer may be controlled by a DMA IOC. Because of the difference in 
software programming methods used on the two types of printers, the 
substitution of one type of printer for the other and the consequent 
change in IOC type will also necessitate a software program change. 
U.S. Pat. No. 4,292,668 entitled "Data Processing System Having Data 
Multiplex Control Bus Cycle" improved the DMC data transfer operation by 
having the CPU read an address and range from memory for the transfer of 
each data byte, receiving each data byte and transferring the data byte 
over the data bus and the address over the address bus. 
OBJECTS OF THE INVENTION 
It is an object of the invention to provide improved direct memory transfer 
apparatus and method. 
SUMMARY OF THE INVENTION 
A data processing system includes a central processing unit (CPU) and a 
main memory coupled to a 16-bit data bus and a 21-bit CPU address bus; and 
an input/output microprocessor, an input/output memory (I/O RAM), a floppy 
disk controller and a disk controller coupled to an 8-bit data bus. The 
input/output microprocessor and the I/O RAM are also coupled to a 16-bit 
I/O address bus. 
The CPU and I/O microprocessor communicate with each other through a 
"mailbox" area in the I/O RAM. The 16-bit I/O address and the 21-bit CPU 
address bus are both coupled to drivers, thereby coupling bits 0 through 
15 of each bus. Data bytes are transferred from the 16-bit data bus to the 
8-bit data bus on 2 data cycles. 
This invention relates to the apparatus for transferring a block of data 
between one of the mass storage controllers and main memory during a data 
multiplex control (DMC) cycle. 
Initially the CPU loads the main memory address and range into the mailbox 
and generates an interrupt signal STSTB0+00. The I/O microprocessor 
responds to the interrupt signal to transfer the main memory address and 
range in the mailbox to a channel table in I/O RAM associated with the 
mass storage device involved in the data transfer. The CPU monitors the 
STSTB0+00 signal which indicates when the I/0 microprocessor has completed 
the transfer. The address is the location in main memory in which the 
first data byte is read or written. 
The CPU then loads the disk address into the mailbox and interrupts the I/O 
microprocessor as above. Again the I/O microprocessor transfers the disk 
address from the mailbox to the channel table. The disk address includes 
head, track, sector number and sector size. 
When the DMC channel is available, the I/O microprocessor transfers the 
address and range from the channel table to the mailbox and transfers the 
disk address to the mass storage controller from the channel table. The 
I/O microprocessor then generates a CPU interrupt signal INTRQ0-00 and 
issues a read or write order to the mass storage controller by generating 
enable signal FDCENB-00. 
The CPU responds to the interrupt signal by reading the mailbox and 
transferring the address into an address register in the CPU and 
transferring the range into a range register in the CPU. 
The mass storage controller responds to the enable signal by issuing a 
request signal DMCREQ-00 indicating that the mass storage device is 
conditioned for the data transfer. The CPU responds to the request signal 
by generating a DMC strobe signal DMCSTB-00 which in turn causes a DMC 
cycle signal DMCCYC+00 to be generated which defines the DMC cycle. 
During the DMC cycle, the CPU sends out the main memory address stored in 
the CPU register on the address bus for either reading out the data byte 
from main memory for transfer to the controller or storing the data byte 
received from the controller in main memory. The CPU decrements the range 
on each DMC cycle and, since each main memory address location stores two 
data bytes, the CPU increments the address on alternate DMC cycles. 
This operation is repeated until the range is equal to ZERO. On that last 
cycle, the CPU sends out a DMC end of range signal DMCEOR-00 to generate 
the DMC cycle signal. The main memory address is sent out on the DMC cycle 
for reading or writing the last data byte of the block transfer.

DESCRIPTION OF THE PREFERRED EMBODIMENT 
FIG. 1 is an overall diagram of a data processing system 1 which includes a 
firmware controlled central processor unit (CPU) 2 as an application 
processor and a I/O microprocessor 4 as an input/output processor. 
Systems applications are performed by the CPU 2 executing software programs 
stored in a 64K by 16-bit word main memory 6. The microprograms used by 
the CPU 2 to execute the software instructions are stored in a 4K by 
48-bit word read only memory 2-2. 
Associated with I/O microprocessor 4 are an 8K by 8-bit byte read only 
memory (ROM) 4-2 and a 32K by 8-bit byte random access memory (RAM) 4-6. 
The ROM 4-2 stores the firmware routines necessary for the start up and 
the initialization of the data processing system 1. The RAM 4-6 stores 
tables, communications control programs and firmware for emulating a 
universal asynchronous receive transmit controller (UART) 44, firmware for 
controlling a number of devices including a keyboard 34-2 by means of a 
UART 34, floppy disks by means of a floppy disk controller (FDC) 38, a 
printer 40-2 by means of a UART 46 and a cathode ray tube controller 
(CRTC) 20. The RAM 4-6 also includes a number of address locations, a 
"mailbox", which are used by the CPU 2 and I/O microprocessor 4 to 
communicate with each other. 
CPU 2 and main memory 6 are coupled to each other by a 21-bit address bus 8 
and a 16-bit data bus 16. Data is transferred between CPU 2 and main 
memory 6 over data bus 16 from an address specified by CPU 2. 
Data bus 16 is coupled to bus interchange registers 18. Also coupled to bus 
interchange registers 18 is an 8-bit data bus 14. Bus interchange 
registers 18 receives 16-bit data words from data bus 16 for transfer over 
data bus 14 as two 8-bit bytes, and also receives 8-bit bytes from data 
bus 14 for transfer over data bus 16. The I/O microprocessor 4, RAM 4-6, 
CRTC 20, UART's 34, 44 and 46, and FDC 38 are all coupled in common to 
data bus 14. 
A 16-bit I/O address bus 12 is coupled to address bus 8 by a transceiver 10 
and also coupled to I/O microprocessor 4 and I/O RAM 4-6, thereby enabling 
both CPU 2 and I/O microprocessor 4 to address main memory 6 and RAM 4-6. 
Also coupled to data bus 14 are a peripheral interface adapter 52 for 
controlling a disk drive 52-2, an asynchronous line UART 44 for receiving 
and transmitting data characters via an asynchronous port 48, a 2K by 
8-bit word data random access memory (RAM) 20-4 for storing characters for 
display on a CRT 20-10 and a 2K by 8-bit word attribute random access 
memory (RAM) 20-6 for storing attribute characters. Attribute characters 
are used typically for such CRT 20-10 display functions as underlining 
characters or character fields or causing certain selected characters or 
character fields to blink or be displayed with higher intensity. Character 
codes stored in RAM 20-4 are applied to a 4K by 8-bit word character 
generator random access memory (RAM) 20-2 which generates the codes 
representative of the raster lines of data which display the characters on 
the face of the CRT 20-10. A video support logic 20-8 is coupled to the 
CRTC 20, character generator RAM 20-2 and attribute RAM 20-6 for 
generating the lines of characters on the face of the CRT 20-10. 
The FDC 38 is typically an NEC .mu.PD765 single/double density floppy disk 
controller described in the NEC 1982 Catalog published by NEC Electronics 
USA Inc., Microcomputer Division, One Natick Executive Park, Natick, Mass. 
01760. 
The I/O microprocessor 4 is typically a Motorola MC68B09 8-bit 
microprocessing unit. The PIA 52 is typically a Motorola MC68B21 
peripheral interface adapter. The CRTC 20 is typically a Motorola MC68B45 
CRT controller. 
The I/O microprocessor 4, PIA 52 and CRTC 20 are described in the Motorola 
Microprocessor Data Manual, copyright 1981 by Motorola Semiconductor 
Products Inc., 3501 Bluestein Blvd., Austin, Tx. 78721. 
The UART's 34, 44 and 46 are Signetics 2661 Universal Asynchronous Receive 
Transmit Controllers described in the Signetics MOS Microprocessor Data 
Manual, copyright 1982 by Signetics Corporation, 811 East Arques Avenue, 
Sunnyvale, Ca. 94086. 
This invention relates to the initiation and control by the CPU 2 of the 
data transfer over data bus 14 between the mass storage device, floppy 
disk 1 38-12, floppy disk 2 38-14 or disk drive 52-2 and the I/O RAM 4-6, 
or the main memory 6 over data buses 14 and 16. 
The logic elements and firmware involved in the mass storage memory data 
transfer are known as the data multiplex control (DMC) facilities. The bus 
cycle during which the data is transferred is referred to as a DMC cycle. 
General Description of Operation 
There are three phases of operation to a DMC data transfer. During the 
first phase of operation, the initiation phase, the CPU 2 indicates to the 
I/O microprocessor 4 by means of an input/output load instruction (IOLD) 
and a number of input/output instructions to condition the selected mass 
storage device to either read from the disk or write on the disk a block 
of data bytes. 
The IOLD instruction format as shown in FIG. 2 is transferred from main 
memory 6 to the mailbox 4-8 of I/O RAM 4-6 under the control of CPU 2. The 
IOLD is identified by hexadecimal 09 in bit positions 10 through 15 of 
data bus cycle 1. The channel number as shown in bit positions 0 through 9 
of data bus cycle 1 identify the peripheral device involved in the data 
byte transfer and whether that peripheral device will be in a read mode or 
a write mode. The 16-bit range indicating the number of data bytes in the 
transfer is shown as divided into 2 bytes, range high and range low. This 
is necessary since data bus 14 is an 8-bit bus. Sixteen bits of the 21-bit 
address are shown as divided into 2 bytes, address high and address low. 
The transfer of remainin 5 bits of address is accomplished by the logic as 
shown in FIG. 3. The address identifies the main memory 6 or I/O RAM 4-6 
locations of the data byte being transferred to or from the mass storage 
device. 
There are two I/O instructions as shown in FIG. 2: configuration word A, 
function code hexadecimal 11, as shown in bit positions 18 through 23 of 
the address bus; and configuration word B, function code hexadecimal 13, 
as shown in bit positions 18 through 23 of the address bus. The channel 
numbers as shown in bit positions 8 through 17 of the address bus of 
configuration word A and configuration word B will be the same as the IOLD 
channel numbers described above for the specified mass storage device. A 
third I/O instruction (not shown) having a function code of hexadecimal 07 
is used by the I/O microprocessor 4 to query a flag in the I/O RAM 4-6 
which was set to indicate that a mass storage controller was conditioned 
for a mass storage operation. 
Configuration word A selects the track in bit positions 0 through 7 of the 
data bus and selects the head in bit positions 8 through 15 of the data 
bus. Configuration word B selects the sector around the track in bit 
positions 0 through 7 of the data bus and indicates the sector size in bit 
positions 8 through 15 of the data bus. Note that for the floppy disk 
38-2, the channel number for a read operation onto the disk is hexadecimal 
0400 and the write operation onto the disk is hexadecimal 0401. Similarly, 
for the floppy disk 38-4, the read channel number is hexadecimal 0480 and 
the write channel number is hexadecimal 0481. For the disk drive 52-2, the 
read channel number is hexadecimal 0500 and the write channel number is 
hexadecimal 0501. 
At the conclusion of phase one, therefore, the channel tables 4-10 for the 
specified channel number store the address and range received from the 
IOLD and the location on the disk of the data bytes received from the I/O 
instructions either to be written on or to be read from the disk. 
During the second phase of operation, the CPU 2 controls the transfer of 
data bytes between the floppy disk controller (FDC) 38 or the disk drive 
52-2 and I/O RAM 4-6 or main memory 6. 
During the third phase of operation, the CPU 2 indicates to the FDC 38 or 
the disk drive 52-2 that the last data byte of the data block is being 
transferred and also indicates to the DMC facilities that the data 
transfer is concluded. 
Detailed Description of Operation 
The first phase of operation starts when the CPU 2 while executing its 
application programs executes an instruction calling for a mass 
storage/memory data transfer. 
Referring to FIG. 1, the CPU 2 stores the IOLD in the mailbox 4-8 in I/O 
RAM 4-6 via address buses 8 and 12 and data buses 16 and 14. The CPU 2 
then interrupts I/O microprocessor 4 via signal STSTB0-00, PIA 52 and 
signal UPRNMI-00 to transfer the IOLD stored in the mailbox 4-8 to the 
channel area 4-10 of I/O RAM 4-6. 
Referring to FIG. 3, signal STSTB0-00 is generated as one output signal of 
a flop 60 which is set by signal LIOINT-00 at logical ZERO from a decoder 
53. Decoder 53 is enabled by ROM 2-2 signals ROMD35+00 and ROMD36+00 at 
logical ONE applied to an AND gate 51 to force enable signal STBDCD+00 to 
logical ONE. Signals ROMD37+00, ROMD45+00 and ROMD46+00 at logical ZERO, 
and signal ROMD47+00 at logical ONE applied to decoder 53 forces signal 
LIOINT-00 to logical ZERO thereby setting flop 60. Output signal STSTB0-00 
at logical ZERO is applied to PIA 52 which generates signal UPRNMI-00 at 
logical ZERO thereby interrupting I/O microprocessor 4. Signal TIME05-10 
applied to AND gate 51 and signal TIME02+05 enabling decoder 53 provides 
the timing for the decoder 53 output signals. 
I/O microprocessor 4 transfers the IOLD from mailbox 4-8, FIG. 1, to the 
channel table area 4-10 of I/O RAM 4-6. The particular channel table into 
which the IOLD is stored is identified by the contents of the channel 
number field, bit positions 8 through 17 of the address buses 8 and 12 as 
shown in FIG. 2. 
When flop 60 is reset, CPU 2 tests output signal STSTB0+00 which indicates 
when the I/O microprocessor 4 has completed the transfer of the IOLD from 
mailbox 4-8 to channel table 4-10. Flop 60 is reset on the rise of a 
signal L6INTR-0R from a decoder 76 which is enabled by signal UBUSRD-00 at 
logical ONE and signals UOFFBS+00 and STRBEN-02 at logical ZERO. Signal 
STRBEN-02 is forced to logical ZERO by predetermined address bus signals 
(not shown) generated by I/O microprocessor 4 over address bus 12. Signal 
UBUSRD-00, generated by I/O microprocessor 4, at logical ONE indicates 
that this is not an I/O microprocessor 4 read operation and signal 
UOFFBS+00 indicates that this is not an I/O microprocessor 4 operation. 
Data bus 14 signal DBUS05+IO at logical ZERO and signals DBUS06+IO and 
DBUS07+IO at logical ONE applied to decoder 76 force signal L6INTR-0R to 
logical ZERO. Flop 60 resets at the end of the I/O microprocessor 4 cycle 
on the rise of signal L6INTR-0R. Signal STSTB0+00 from flop 60 returning 
to logical ZERO indicates to CPU 2 that the IOLD has been processed by the 
I/O microprocessor 4. 
The CPU 2 senses the end of the I/O microprocessor 4 transfer of the IOLD 
from the mailbox 4-8 to the channel table 4-10 and loads the mailbox with 
the I/O configuration A instruction information. Again the I/O 
microprocessor 4 is interrupted as described above to store the track 
address and head select information in channel table 4-10. Again the CPU 2 
senses the end of the I/O microprocessor 4 cycle and transfers the I/O 
configuration B instruction information to the mailbox 4-8. The I/O 
microprocessor is again interrupted to transfer the sector number and 
sector size to the channel table 4-10. 
If the DMC channel is available, the I/O microprocessor 4 which keeps track 
of the DMC channel assignments reads the particular channel table 4-10 and 
transfers the track address, head select, sector number and sector size to 
the FDC 38 or the disk drive 52-2. The I/O microprocessor 4 will also 
transfer the address and range information from the particular channel 
table 4-10 to the mailbox 4-8. 
The I/O microprocessor 4 then interrupts the CPU 2 via the INTRQ0-00 
signal. The CPU 2 responds by transferring the address and range from the 
mailbox 4-8 into a 20-bit address register 2-2 and a 16-bit range register 
2-4. 
Interrupt signal INTRQ0-00 is forced to logical ZERO when a flop 77 is set. 
Signal LINTR0-0S, the output of decoder 76, is forced to logical ZERO when 
the data bus 14 signals DBUS05+00, DBUS06+00 and DBUS07+00 are at logical 
ZERO and decoder 76 is enabled as described above. 
CPU 2 is responsive to the INTRQ0-00 interrupt signal to address mailbox 
4-8 of I/O RAM 4-6 to transfer the 20-bit address to register 2-6 and the 
16-bit range to register 2-4. 
The I/O microprocessor 4 issues a read or write order to the FDC 38 or the 
disk drive 52-2. For this example assume the read or write order is issued 
to the FDC 38 by the I/O microprocessor 4 generating a floppy disk enable 
signal FDCENB-00 to FDC 38 by a decoder 41 signal NEDSK-00 and a negative 
AND gate 43. Address bus 12 signals ABUS14+00, ABUS16+00 and ABUS17+00 at 
logical ONE and signal ABUS15+00 at logical ZERO generate signal NEDSK-00 
at logical ZERO. Disk enable signal DSKENB+10 applied to negative AND gate 
43 is at logical ZERO since the disk drive 52-2 was not addressed by I/O 
microprocessor 4. The I/O enable signal IOENBL-1A is at logical ZERO 
indicating that an input/output order is being processed. Also the 
UOFFBS+00 signal is at logical ZERO since the inputs to a NOR gate 74 
indicate that this is not a mailbox 4-8 read or write operation, this is 
not a DMC cycle and this is not a memory refresh operation, i.e., signals 
MAILBX-00, DMCCYC-10 and REFRSH-10 are at logical ONE. 
The FDC 38 responds to the I/O configuration A and configuration B 
instructions by issuing signal FDCDRQ+00 indicating that the floppy disk 1 
38-12 or floppy disk 2 38-14 has responded to its channel number and has 
positioned the head to the proper track on the disk and is ready to either 
receive a data byte from memory, I/O RAM 4-6 or main memory 6 or transmit 
a data byte to memory. 
The FDCDRQ+00 signal is inverted to signal FDCDRQ-10 by and inverter 65 
which is applied to a negative OR gate 68. The output signal DMCREQ-00 
enables a decoder 66. Signal DSKDRQ-00 applied to negative OR gate 68 
indicates if the disk drive 52-2 is requesting a data transfer. 
The state of a flop 67 indicates if the CPU 2 word address stored in 
register 2-6 represents a left byte when set or a right byte when not set. 
The flop 67 will toggle as a block of data bytes are transferred between 
memory and the FDC 38, successive bytes going alternatively into the left 
byte location then the right byte location of a word address. 
Assuming flop 67 is set and signal DMCA20+00 is at logical ONE, then the 
decoder 66 will generate signal DMCRDL-00 at logical ZERO for a read 
operation or signal DMCWTL-00 at logical ZERO for a write operation. 
Assuming a left byte read operation, signal DMCWRT+00 from PIA 52 at 
logical ZERO, signal DMCRDL-00 will remain at logical ZERO and signal 
DATRQ1-00 will pulse in synchronism with the PHAS.A+10 signal applied to a 
driver 64. 
The IOLD instruction as shown in FIG. 2 shows the 16 address bits being 
transferred from CPU 2 to I/O RAM 4-6 over data buses 16 and 14 on data 
bus 16 cycle (3). The remaining five high order address bits, signals 
BYTEXX-R0 and DABSOA+00 through DABSOD-00, bypass the address bus 8 and 
are stored directly in IOLD register 156 under the control of ROM 2-2 
signals ROMD23+00, ROMD24+00 and ROMD25+00 applied to an AND gate 150. 
Output signal MMUDTC+00 sets a flop 152 on the rise of timing signal 
TIME02+00. Output signal MMUDAT+00 is applied to an AND gate 154 to 
generate clock signal IOLDCK+00 at clock signal PHAS.B+10 time. The five 
high order address signals appear as signals UDATA0+UP and UDATA4+UP 
through UDATA7+UP which are applied to I/O microprocessor 4 by signal 
STSRG0+00. Signal STSRG0+00 is generated by CPU 2 address bus signals (not 
shown). 
I/O microprocessor 4 generates signals DBUS05+IO, DBUS06+IO and DBUS07+IO 
in response to signal UDATA0+UP (BYTEXX-R0) to generate data bus 14 
signals DBUS05+IO, DBUS06+IO and DBUS07+IO which are applied to decoder 
76. Output signal DMA20-20 or DMA20-0R is generated to initially set or 
reset flop 67 to indicate that the first data byte of the block transfer 
will be either written into or read from a right byte when flop 67 is 
reset and a left byte when flop 67 is set. 
The second phase of operation starts by the CPU 2 generating a DMCCYC+00 
signal to initiate the DMC cycle. Decoder 53 is enabled by ROM 2-2 signals 
ROMD35+00 and ROMD36+00 at logical ONE applied to AND gate 51 which strobe 
signal STBDCD+00 at logical ONE. Also signal ROMD37+00 at logical ZERO is 
applied to an enable input terminal of decoder 53. Signals ROMD46+00 and 
ROMD47+00 at logical ZERO and signal ROMD45+00 at logical ONE force the 
DMC strobe signal DMCSTB-00 to logical ZERO. Timing signals TIME05-10 at 
logical ONE and TIME02+00 at logical ZERO provide the timing for the 
DMCSTB-00 signal. The DMCSTB-00 signal is stored in a register 56 on the 
next rise of the TIME02+00 signal via an inverter 54 and signal DMCSTB+10. 
The output signal DMCADC+00 is applied to an OR gate 59. The output signal 
DMCADC+0A is stored in a register 57 on the rise of the PHAS.A+10 clock 
signal. The output signal DMCCYC+00 and signal DMCCYC-00 from an inverter 
58 define the DMC cycle. Clock signal LADRCK+00 stores the 20 address 
signals DABS 00-15+00 and DABS A-D+00 in a register 80 from CPU 2 register 
2-6 for transfer out on address bus 8 as signals L6AD00-19+00. Signal 
LADRCK+00 is generated by a ROM 2-2 signal ROMD23+00 which is clocked into 
register 56 by timing signal TIME02+00 to generate signal LADRCY+00 which 
is applied to an OR gate 84. An output signal L6ADOT+00 is applied to an 
AND gate 82 to generate the address clocking signal LADRCK+00 which is 
timed to the PHAS.B+10 clocking signal. 
The address signals DABS 00-15+00 and DABS A-D+00 are placed on the address 
bus 8 as address signals L6AD00-19+00 by register 80 being enabled by 
signal L6ADEN-00, the output of a NOR gate 90. Signal L6ADEN-00 is 
generated by address cycle signal LADRCY+00, stored in register 57 at 
PHAS.A+10 time. Register 57 generates output signal L6BSCY+00 which is 
applied to NOR gate 90 to generate the L6ADEN-00 signal to enable register 
80. Signal L6ADEN-00 is also generated during a memory refresh cycle by 
signal REFRSH+00 applied to NOR gate 90. 
Request signal FDCDRQ-10 is also stored in register 80. The output signal 
FDCDMC-00 is applied to the DMA acknowledge terminal of FDC 38 as signal 
DAKFDC-00 to indicate that the CPU 2 address was sent out on address bus 8 
during the DMC cycle. Signal DAKFDC-00 is generated at logical ONE by a 
negative AND gate 122 when signals DMCCYC-10 and DMCFDC-00 are at logical 
ZERO. Signal FDCDRQ-10 and signal FDCDMC-00 at logical ONE applied to a 
NOR gate 120 forces signal DMCFDC-00 to logical ZERO. This assures that 
signal DAKFDC-00 is applied to FDC 38 after the DMC cycle is concluded. 
CPU 2 generates an L6WRHC+00 signal to indicate a write right byte 
operation by applying ROM 2-2 signals ROMD23+00 and ROMD24+00 at logical 
ONE to an AND gate 116. Also CPU 2 generates an L6WRLC+00 signal to 
indicate a write left byte operation by applying signals ROMD23+00 and 
ROMD25+00 at logical ONE to an AND gate 118. Signals L6WRHC+00 and 
L6WRLC+00 are stored in register 56 at clock signal TIME02+00 time. Output 
signals L6WRHC+0B and L6WRLC+0B are stored in register 57 at clock signal 
PHAS.A time. Output signals L6WRHI+00 and L6WTL0+00 are applied to an OR 
gate 112 to generate an L6WRCY-IO signal indicating a CPU 2 write cycle. 
Output signal UOFFBS+00 from NOR gate 74 is at logical ONE indicating a 
CPU 2 cycle and not an I/O microprocessor 4 cycle during each DMC cycle 
and is applied to an AND/NOR gate 78 as is signal L6WRCY-IO thereby 
forcing output signal UBUSRD-00 to logical ZERO during write cycles. 
Signal UBUSRD-00 is applied to one input terminal 0 of MUX 94 which is 
selected during the DMC cycle since signal DMCCYC-10 applied to select 
terminal 2 is at logical ZERO thereby generating the FDC.WR-00 signal at 
logical ZERO thereby forcing an FDC 38 write DMC cycle. If signal 
L6WRCY-10 is at logical ZERO indicating a CPU 2 read cycle, then output 
signal UBUSRD+10 from an inverter 74 is applied to input terminal 0 of MUX 
92. The MUX 92 output signal FDC.RD-00 at logical ZERO would force an FDC 
38 read DMC cycle. 
When the I/O microprocessor 4 is communicating with the FDC 38, the 
UPREAD+20 signal which is generated by the I/O microprocessor 4 and signal 
UOFFBS-00 from an inverter 97 control the generation of the FDC.RD-00 or 
FDC.WR-00 signal. In this case, signal DMCCYC-10 is at logical ONE thereby 
selecting input terminal 2 of MUX's 92 and 94. For the read cycle, signal 
UBUSRD-00 at logical ZERO is applied to input terminal 2 of MUX 92, 
forcing signal FDC.RD-00 to logical ZERO. For the write cycle, signal 
UBUSRD+10 at logical ZERO is applied to input terminal 2 of MUX 94, 
forcing signal FDC.WR-00 to logical ZERO. MUX 92 is enabled during clock 
signal PHAS.A+10 and MUX 94 is enabled during clock signal TIME02+10, FIG. 
4. 
A ROM 99 generates the low order CPU 2 address signal L6AD20+00. The 
following signals are applied to the input address terminals of ROM 99: 
Signal DMCCYC+00 indicates a DMC cycle; 
Signal L6BSCY+00 which enables ROM 99 indicates a CPU 2 bus cycle; 
Signal L6WTHI+00 indicates a write right byte operation; 
Signal L6WTL0+00 indicates a write left byte operation; 
Signal L6BSA0+00 indicates that this is a CPU 2 operation and not an I/O 
microprocessor 4 operation; and 
Signal L6RD20-00, the output of a NAND gate 100, indicates whether the CPU 
2 sending a left byte or a right byte at DMC cycle time. 
The 21 address bus 8 signals L6AD00-20+00 from register are applied to the 
B terminals of transceiver 10. The 16 address bus 12 signals ABUS05-20+00 
are applied to the A terminals of transceiver 10. The transceiver 10 is 
enabled by output signal ADBSEN-00 from a NOR gate 106 when the CPU 2 is 
not requesting a bus cycle; signal L6BSCY-10, an inverter 124 output, at 
logical ONE; or the CPU 2 is active and the I/O microprocessor 4 is 
inactive, signal L6BSA0+00 at logical ONE. Signal LADOUT-00, the output of 
a negative OR gate 104, establishes the direction from terminals B to 
terminals A of the transceiver 10 when at logical ZERO and from terminals 
A to terminals B. 
During the DMC operation, signal MAILBX-00, the output of NAND gate 102, is 
at logical ZERO since signals BSCY+00 and L6BSA0+00 indicate that CPU 2 is 
active and I/O microprocessor 4 is inactive; therefore the address stored 
in CPU 2 register 2-6 will be transferred from address bus 8 through 
transceiver 10 to address bus 12. Also the transceiver 10 will transfer 
addresses from input terminal B to input terminal A during the memory 
refresh operation when signal REFRSH-10 is at logical ZERO. During I/O 
microprocessor 4 bus cycles, transceiver 10 transfers addresses from input 
terminal A to input terminal B when signal L6BSCY-10 at logical ONE 
indicates that the CPU 2 is not requesting a bus cycle. 
CPU 2 addresses ROM 2-2 via signals RSAD 00-11+00, a register 110 and 
signals RADR 00-11+00. ROM 2-2 output signals ROMD 00-47+00 provide the 
firmware control of the CPU 2 logic. Register 110 sets on the rise of 
signal PH2A0B+00 which is the output of an AND gate 118. Signals PHAS.A-00 
and PHAS.B-00 provide the inputs to AND gate 108. 
In summary, for a floppy disk write operation during the DMC cycle, the 
memory address appears on the address bus 8 to address a left data byte in 
main memory 6 or the address appears on address buses 8 and 12 to address 
a left data byte in I/O RAM 4-6 to place the left data byte on the data 
bus 14 for transfer to FDC 38. For a floppy disk read operation, the data 
byte stored in the FDC 38 is transferred to I/O RAM 4-6 or main memory 6 
during the DMC cycle. 
For the next DMC cycle, flop 67 is reset to address the right byte in 
memory and signal DMCRDH-00 or DMCWTH-00 is selected for the read or write 
operation, respectively. 
The CPU 2 decrements the range for each data byte transferred and generates 
a DMCEOR-00 signal from decoder 53 instead of the normal DMCSTB-00 signal 
during the third phase of operation. Signal DMCEOR-00, in addition to 
generating the DMCCYC-00 cycle via inverter 55, signal DMCEOR+10, register 
56, signal DMCTMC+00, NOR gate 59, signal DMCADC+0A and register 57, also 
generates signal DMC.TC+00 which signals the FDC 38 that this is the last 
data byte being transferred. 
FIG. 4 shows the timing of the DMC operation. The PHAS.A+00 and PHAS.B+00 
signals are the basic timing signals of the DMC operation. The basic 
timing cycle is 649 nanoseconds which is stretched to 767 nanoseconds 
during the DMC cycle by keeping timing signals low for the additional 118 
nanoseconds. 
Assuming the floppy disk read or write operation, signal FDCREQ+goes high 
to indicate that the FDC 38 has a data byte to transfer or is ready to 
receive a data byte to write on a floppy disk. 
Signal FDCDMC-00 low acknowledges signal FDCREQ+. Signal DMCRDL-00 low 
indicates that a left byte is being transferred from main memory 6 or I/O 
RAM 4-6 to FDC 38. Signal DMCRDH-00 low indicates that a right byte is 
being transferred from main memory 6 or I/O RAM 4-6 to FDC 38. 
Signal DATRQX+10 representative of signal DMCWTH-00, DMCWTL-00, DMCRDH-00 
or DMCRDL-00 goes high when accepted by the CPU 2 on the PHAS.A+00 cycle 
in which signal ROMD34+00 is low. 
Signal DMCSTB+00 high indicates a positive response to signal DATRQX-00. 
The CPU 2 accepted signal DATRQX-00 by extending a firmware routine in 
which a bit stored in ROM 2-2 and read out as signal ROMD34+00 is low. 
Signal DMCADC+00 delays the start of the DMC cycle to allow time for the 
address stored in register 2-6 of CPU 2 transferred to a register 80 by 
signal LADRCK+00 prior to being placed on the address bus 8. 
Signal DMCCYC+00 high defines the DMC cycle. 
Signal DMCA20+00 assigns the DMC cycle for transferring the left data byte 
of the data word when high or the right data byte of the data word when 
low over the data bus 14 between FDC 38 or disk drive 52-2 and either I/O 
RAM 4-6 or main memory 6. Signal L6BSCY+00 enables register 80 to place 
the 20 address signals L6AD00-19+00 on the address bus 8. In addition, the 
21st address signal indicating the left or right byte is placed on the 
address bus 8. Note that 16 address signals L6AD05+00 through L6AD20+00 
are placed on address bus 12 by transceiver 10 as address signals 
ABUS05+00 through ABUS20+00, respectively. 
Signal FDC.RD-00 when low results in the FDC 38 transferring the data byte 
to the data bus 14. 
Signal FDC.WR-00 when low results in the FDC 38 receiving the data byte 
from the data bus 14. 
Signal DMCEOR+10 is high for the last data byte of the transfer as 
indicated by the range stored in register 2-4 being decremented to ZERO. 
Signal DMCEOR+10 performs the same logical operations as signal DMCSTB+10 
and in addition sends a signal DMC.TC-10 to the FDC 38 indicating 
end-of-range. 
CPU 2 address bus 8 signals L6AD00-20+00 are applied to bidirectional 
transceiver (XCVR) 10 as are I/O microprocessor 4 bus signals 
ABUS05-20+00. A ROM 99 generates the low order CPU 2 address bus 8 signal 
L6AD20+00 to select the left or right byte of the main memory 6 or I/O ROM 
4-6 data word. The ROM 99 is addressed by the DMC cycle signal DMCCYC+00, 
a CPU 2 write right byte signal L6WTHI+00, a CPU 2 write left byte signal 
L6WTL0+00, a signal L6BSA0+00 indicating that a CPU 2 address is on 
address bus 12, and a 21st address bit output signal L6RD20-00 from a NAND 
gate 100. NAND gate 100 is active during the DMC cycle when signal 
DMCCYC+00 is at logical ONE and when flop 67 is set forcing signal 
DMCA20+00 is at logical ONE indicating a left byte read or Write 
operation. ROM 90 is enabled when signal L6BSCY+00 is at logical ZERO 
indicating that this is not a CPU 2 bus cycle. 
Transceiver 10 is enabled by output signal ADBSEN-00 from a NOR gate 106 at 
logical ZERO. Transceiver 10 is enabled if either this is not a CPU 2 bus 
cycle, signal L6BSCY-10 is at logical ONE, or there is not a CPU 2 address 
on the address bus 8, signal L6BSA0-00 is at logical ONE. Transceiver 10 
is disabled during a CPU 2 bus cycle. 
Transceiver 10 transfers address bus signals from address bus 8 to address 
bus 12 when direction signal LADOUT-00 is at logical ONE and from address 
bus 12 to address bus 8 when signal LADOUT-00 is at logical ZERO. Signal 
LADOUT-00 is at logical ONE when memory is not being refreshed, signal 
REFRSH-10 applied to a negative OR gate 104 is at logical ONE and this is 
not a CPU 2 read mailbox operation, signal MAILBX-00 is at logical ONE. If 
either of signals REFRSH-10 and MAILBX-00 is at logical ZERO then signal 
LADOUT-00 is at logical ZERO. 
Signal MAILBX-00 at logical ZERO indicates a CPU 2 read mailbox 4-8 
operation since signals L6BSCY+00 and L6BSA0+00 applied to a NAND gate 102 
are at logical ONE indicating a CPU 2 bus cycle and a CPU 2 address is on 
address bus 8. 
FIG. 5 shows a flow diagram of the steps of the data transfer between main 
memory 6 and FDC 38 or disk device 52-2 during DMC operation. 
Blocks 5-2, 5-4, 5-6 and 5-8 show the sequence of operations in 
transferring the (a) Address and Range; (b) Configuration A; (c) 
Configuration B; and (d) Task word for a particular channel number from 
CPU 2 to the mailbox 4-8 of I/O RAM 4-6. 
After each instruction word (a), (b), (c) or (d) above, the CPU 2 in block 
5-4 interrupts I/O microprocessor 4 by generating signal STSTB0-00. In 
block 5-6 the I/O microprocessor 4 transfers the instruction word from the 
mailbox 4-8 to the channel table 4-10. Signal STSTB0+00 is tested by the 
CPU 2 in block 5-8 and branches to block 5-2 after each instruction word 
is stored in the channel table to send the next instruction word to the 
mailbox 4-8. 
The Task word sets a task flag bit stored in I/O RAM 4-6 which is tested 
periodically in block 5-12 by the I/O microprocessor 4 when in a 
background operation in block 5-10. The task flag bit is set to indicate 
that the mass storage controller is ready for a read, write or seek 
operation. In block 5-14 the I/O microprocessor 4 tests a read/write flag 
bit in I/O RAM 4-6 which was set by a channel number bit. If this is not a 
read or write operation, then it is a mass storage seek operation; that 
is, the mass storage device will position the head to the proper track and 
the I/O microprocessor 4 firmware will return to background block 5-10. 
If this is a read or write operation, a test is made of the DMC busy flag 
in I/O RAM 4-6. If the DMC cycle is available, the I/O microprocessor 4 in 
block 5-20 will load the mailbox with the range and address. In block 5-22 
the PIA 52 is set up for a read or write operation. In block 5-24 the I/O 
microprocessor 4 interrupts CPU 2 by generating signal INTRQ0-00. 
In block 5-26 the CPU 2 reads the mailbox 4-8 and stores the range and 
address in registers 2-4 and 2-6, respectively. In block 5-27 the CPU 2 
again interrupts the I/O microprocessor 4 by generating signal STSTB0-00. 
The I/O microprocessor 4 in block 5-28 sends a read or write order to the 
mass storage controller by way of the PIA 52. 
In block 5-29 the mass storage controllers generate the request signals 
FDCDRQ-10 and DSKDRQ-00 which are applied to a negative OR gate 68 of FIG. 
3 to generate signal DMCREQ-00. 
In block 5-30 CPU 2 decrements the range and in block 5-32 tests the range. 
If the range does not equal ZERO, then in block 5-34 the CPU 2 transfers 
the address from register 2-6 out on CPU address bus 8 and generates 
signal DMCSTB-00. This in turn becomes DMC cycle signal DMCCYC+00. At the 
same time, the data byte is transferred between the mass storage 
controller and main memory 6. 
If the range equals ZERO indicating that this is the last byte of the 
block, the CPU 2 transfers the address and generates signal DMCEOR-00 
which in turn becomes DMC cycle signal DMCCYC+00. Also signal DMCEOR-00 
causes signal DMC.TC+00 to be applied to the FDC 38 and disk drive 52-2 to 
indicate the end of the block. 
Block 5-38 in conjunction with block 5-36 or 5-34 transfers the data byte 
from or to the specified address. Block 5-40 increments the address stored 
in register 2-6 if it is an odd address, that is, the address of the low 
order byte of the 2 byte data word. In block 5-42 the CPU 2 returns to its 
previous operation before the interrupt. 
Having shown and described a preferred embodiment of the invention, those 
skilled in the art will realize that many variations and modifications may 
be made to affect the described invention and still be within the scope of 
the claimed invention. Thus, many of the elements indicated above may be 
altered or replaced by different elements which will provide the same 
result and fall within the spirit of the claimed invention. It is the 
intention, therefore, to limit the invention only as indicated by the 
scope of the claims.