Semiconductor memory device including initialization signal generation circuit

An initialization signal generation circuit includes: an initialization signal output unit configured to generate an initialization signal which is enabled during at least a portion of an auto refresh operation period of the initialization mode, in response to a flag signal; a refresh signal generation unit configured to generate a preliminary refresh signal and a refresh counting signal having the same period as the auto refresh signal in response to the flag signal and an auto refresh signal; and a counter unit configured to count a counting signal in response to the refresh counting signal and generate a counting initialization signal, which is delayed by at least a pulse width of the refresh counting signal, after a time point where a combination of the counting signal becomes a preset combination.

CROSS-REFERENCES TO RELATED APPLICATIONS

The present application claims priority under 35 U.S.C. 119(a) to Korean Application No. 10-2011-0116136, filed on Nov. 8, 2011, in the Korean intellectual property Office, which is incorporated herein by reference in its entirety.

BACKGROUND

A semiconductor memory device normally starts an operation only when internal setting values are maintained to initial values. Therefore, an initialization (reset) operation for starting the operation of the semiconductor memory device is very important.

Semiconductor memory device having a variety of functions include a plurality of circuits of which the initial conditions should be decided, in order to perform a normal operation. The initialization (reset) operation should be performed before a memory chip is operated. In general, an auto refresh operation is repetitively performed by a counting operation during an initialization mode, thereby initializing a register, a memory cell region or the like.

The auto refresh operation refers to an operation of compensating for a loss caused by a leakage current of a circuit such as a memory cell of a semiconductor memory device, according to an auto refresh signal AREF. During the initialization mode, a normal operation of the semiconductor memory device is not performed. In order for the semiconductor memory device to perform a normal operation, a screen method is required to learn an end time point of the initialization mode.

In such a screen method, the level of an initialization signal DAI (Device Auto Initialization), which transitions at a time point where the initialization mode is ended, is detected through a DQ pad of the semiconductor memory device to screen the end time point of the initialization mode.

In addition, JEDEC (Joint Electron Device Engineering Council) defines a performance time of an initialization (reset) operation according to the specification of a semiconductor memory device. In the case of an LPDDR2 memory device, the initialization operation time thereof is limited to 10 us. Therefore, the LPDDR2 memory device should terminate the initialization operation within 10 us.

The initialization operation of the semiconductor memory device will be described with reference toFIG. 1. In the following descriptions, it is assumed that the auto refresh operation is repeated six times in the initialization mode, and the pulse width of a signal for disabling an initialization signal among internal signals may vary depending on a PVT variation.

First, the semiconductor memory device enters the initialization mode, and a power-up signal PWRUP is enabled to a logic high level after a power-up period where a power supply voltage supplied from outside approaches a target level. Then, when a reset signal RESET is inputted from outside after the power-up period, a flag signal RS_FLAG is enabled to a logic high level, and an initialization signal DAI is enabled to a logic high level.

Next, a first pulse of a preliminary refresh signal AREF_PRE is generated in response to the flag signal RS_FLAG, and a second pulse of the preliminary refresh signal AREF_PRE is generated in response to a falling edge of the auto refresh signal AREF. Furthermore, pulses after the second pulse are also generated in response of falling edges of the auto refresh signal AREF. Furthermore, a refresh initialization signal INIT_AREF and a refresh counting signal AREF_CNT having the same period as the preliminary refresh signal AREF_PRE are generated.

Then, counting signals CNT<1:3> for performing an auto refresh operation six times are counted according to the refresh counting signal AREF_CNT to set up a preset combination, and the counting initialization signal INIT_CNT is then enabled at a time point t0to terminate the counting operation.

Here, when the counting signals CNT<1:3> correspond to the preset combination, it indicates that the counting operation is performed six times to set the counting signals CNT<1:3> to a combination of ‘L, H, H’. When the counting signals CNT<1:3> are set to ‘L, H, H’, it means that the first counting signal CNT<1> is ‘L’, the second counting signal CNT<2> is ‘H’, and the third counting signal CNT<3> is ‘H’.

The initialization signal DAI is disabled when the counting initialization signal INIT_CNT is enabled to a logic high level in a period where the preliminary refresh signal AREF_PRE is at a logic high level.

However, when the preliminary refresh signal AREF_PRE has a large pulse width as shown in a period A ofFIG. 1according to a PVT variation, a pulse of the counting initialization signal INIT_CNT may overlap the pulse of the preliminary refresh signal AREF_PRE generated in response to a fifth falling edge of the auto refresh signal AREF. In this case, a preliminary initialization signal DAI_PRE is disabled, and the initialization signal DAI is disabled at a time point t1within the auto refresh period. Therefore, the auto refresh operation may not be performed sufficiently to a preset level in the initialization mode, and the end time point of the initialization mode may not be screened with precision.

SUMMARY

An embodiment of the present invention relates to a semiconductor memory device including an initialization signal generation circuit, which is capable of accurately setting a level change time point of an initialization signal even though a PVT variation occurs, thereby performing a stable initialization operation.

In one embodiment, an initialization signal generation circuit includes: an initialization signal output unit configured to enter an initialization mode and generate an initialization signal which is enabled during an auto refresh operation period of the initialization mode, in response to a flag signal; a refresh signal generation unit configured to generate a preliminary refresh signal and a refresh counting signal having the same period as the auto refresh signal in response to the flag signal and an auto refresh signal; and a counter unit configured to count a counting signal in response to the refresh counting signal and generate a counting initialization signal which is delayed by a pulse width of the refresh counting signal and then enabled after a time point where a combination of the counting signal becomes a preset combination.

In another embodiment, a semiconductor memory device includes: a flag signal generator configured to generate a flag signal in response to a reset signal inputted from outside in an initialization mode; an auto refresh signal generator configured to receive an idle signal and generate an auto refresh signal including a periodic pulse in the initialization mode; and an initialization signal generator configured to generate an initialization signal which is enabled during an auto refresh operation period of the initialization mode, in response to the flag signal.

DESCRIPTION OF SPECIFIC EMBODIMENTS

Hereinafter, embodiments of the present invention will be described with reference to accompanying drawings. However, the embodiments are for illustrative purposes only and are not intended to limit the scope of the invention.

FIG. 2is a block diagram of a semiconductor memory device in accordance with an embodiment of the present invention.

Referring toFIG. 2, the semiconductor memory device including an initialization signal generation circuit in accordance with an embodiment of the present invention includes a flag signal generator10, an auto refresh signal generator20, and an initialization signal generator30. The flag signal generator10is configured to generate a flag signal RS_FLAG in response to a reset signal RESET inputted from outside in an initialization mode. The auto refresh signal generator20is configured to receive an idle signal IDLE and generate an auto refresh signal AREF including a periodic pulse in the initialization mode. The initialization signal generator30is configured to generate an initialization signal DAI which is enabled during an auto refresh operation period of the initialization mode, in response to the flag signal RS_FLAG. Here, the reset signal RESET is a signal which is inputted from outside when the semiconductor memory device performs an initialization operation, and the idle signal IDLE is a signal which is enabled in a standby state where the semiconductor memory device does not perform a read or write operation. Furthermore, the initialization mode refers to a mode where an auto refresh operation is performed after the semiconductor memory device enters the standby state.

Referring toFIG. 3, the configuration of the flag signal generator10will be described in more detail as follows.

Referring toFIG. 3, the flag signal generator10includes a first pull-up signal generation unit100, a first pull-down signal generation unit110, a first driving unit120, a first latch unit130, and a first buffer unit140. The first pull-up signal generation unit100is configured to generate a first pull-up signal PU<1> which is enabled when the initialization signal DAI is disabled. The first pull-down signal generation unit110is configured to generate a first pull-down signal PD<1> which is enabled in response to the reset signal RESET after a power-up period. The first driving unit120is configured to drive a first node nd10in response to the first pull-up signal PU<1> and the first pull-down signal PD<1>. The first latch unit130is configured to latch a signal of the first node nd10. The first buffer unit140is configured to buffer an output signal of the first latch unit130and output the buffered signal as the flag signal RS_FLAG. Furthermore, the flag signal generator10further includes a first initialization element P11configured to pull-up drive the first node nd10in response to a power-up signal PWRUP which is enabled after the power-up period where a power supply voltage VDD supplied to the semiconductor memory device rises to a target voltage level.

More specifically, the first pull-up signal generation unit100includes a first pulse generator101and a first inverter IV10. The first pulse generator101is configured to receive the initialization signal DAI and generate a pulse having a predetermined width. The first buffer IV10is configured to invert and buffer an output signal of the first pulse generator101and generate the first pull-up signal PU<1>. The second pull-down signal generation unit110includes a second inverter IV11, an SR latch section111, and a third inverter IV12. The second inverter IV11is configured to invert and buffer the reset signal RESET. The SR latch section111is configured to latch an output signal of the second inverter IV11in response to the flag signal RS_FLAG, and buffer and output the latched signal. The third inverter IV12is configured to invert and buffer the output signal of the SR latch section11and output the inverted signal as the first pull-down signal PD<1>. The first driving unit120includes a first pull-up driver P10and a first pull-down driver N10. The first pull-up driver P10is configured to pull-up drive the first node nd10in response to the first pull-up signal PU<1>. The first pull-down driver N10is configured to pull-down drive the first node nd10in response to the first pull-down signal PD<1>. The flag signal generator10configured to such a manner disables the flag signal RS_FLAG in the power-up period, and enables the flag signal RS_FLAG in response to the reset signal RESET inputted from outside in the initialization mode after the power-up period.

The initialization signal generator30includes an initialization signal output unit31, a refresh signal generation unit32, and a counter unit33. The initialization signal output unit31is configured to generate the initialization signal DAI which is enabled during the auto refresh operation period of the initialization mode, in response to the flag signal RS_FLAG. The refresh signal generation unit32is configured to generate a preliminary refresh signal AREF_PRE and a refresh counting signal AREF_CNT including a periodic pulse during the auto refresh operation period, in response to the flag signal RS_FLAG and the auto refresh signal AREF. The counter unit33is configured to count counting signals CNT<1:3> in response to the refresh counting signal AREF_CNT, and generate a counting initialization signal INIT_CNT which is delayed by a pulse width of the refresh counting signal AREF_CNT and then enabled after a time point where a combination of the counting signals CNT<1:3> becomes a preset combination.

The configuration of the initialization signal output unit31will be described in more detail as follows with reference toFIG. 4.

Referring toFIG. 4, the initialization signal output unit31includes a second pull-up signal generation unit ND30, a second pull-down signal generation unit310, a second driving unit311, a second latch unit312, and a second buffer unit313. The second pull-up signal generation unit ND30is configured to perform a NAND operation on the counting initialization signal INIT_CNT and the preliminary refresh signal AREF_PRE and generate a second pull-up signal PU<2>. The second pull-down signal generation unit310is configured to generate a second pull-down signal PD<2> in response to a preliminary initialization signal DAI_PRE and the flag signal RS_FLAG. The second driving unit311is configured to drive a second node nd30in response to the second pull-up signal PU<2> and the second pull-down signal PD<2>. The second latch unit312is configured to latch a signal of the second node nd30and invert and buffer the latched signal to generate a preliminary initialization signal DAI_PRE. The second buffer unit313is configured to buffer the preliminary initialization signal DAI_PRE and output the buffered signal as the initialization signal DAI. Furthermore, the initialization signal generation unit31further includes a second initialization element P31configured to pull-up drive the second node nd30in response to the power-up signal PWRUP which is enabled after the power-up period in which the power supply voltage VDD supplied to the semiconductor memory device rises to a target voltage level.

More specifically, the second pull-up signal generation unit ND30includes a NAND gate configured to perform a NAND operation on the counting initialization signal INIT_CNT and the preliminary refresh signal AREF_PRE and generate the second pull-up signal PU<2>. The second pull-down signal generation unit310includes a NOR gate NR30and a second pulse generator3100. The NOR gate NR30is configured to perform a NOR operation on the preliminary initialization signal DAI_PRE and the flag signal RS_FLAG. The second pulse generator3100is configured to generate the second pull-up signal PU<2> including a pulse having a predetermined width in response to an output signal of the NOR gate NR30. The second driving unit311includes a second pull-up driver P30and a second pull-down driver N30. The second pull-up driver P30is configured to pull-up drive the second node nd30in response to the second pull-up signal PU<2>. The second pull-down driver N30is configured to pull-down drive the second node nd30in response to the second pull-down signal PD<2>. The initialization signal output unit31configured in such a manner enables the initialization signal DAI in response to the flag signal RS_FLAG which is enabled in the initialization mode, and disables the initialization signal DAI according to pulses of the preliminary refresh signal AREF_PRE and the counting initialization signal INIT_CNT which is delayed by the pulse width of the refresh counting signal AREF_CNT and then enabled after the period where the combination of the counting signals CNT<1:3> becomes the preset combination in the initialization mode.

The configuration of the refresh signal generation unit32will be described in more detail as follows with reference toFIG. 5.

Referring toFIG. 5, the refresh signal generation unit32includes a preliminary refresh signal generation unit320and a refresh counting signal generation unit321. The preliminary refresh signal generation unit320is configured to generate the preliminary refresh signal AREF_PRE including a pulse having the same cycle as the auto refresh signal AREF in response to the flag signal RS_FLAG after the power-up period. The refresh counting signal generation unit321is configured to buffer the preliminary refresh signal AREF_PRE and generate the refresh counting signal AREF_CNT. Here, a first pulse of the preliminary refresh signal AREF_PRE is generated with a predetermined pulse width in response to the flag signal RS_FLAG, and a second pulse of the preliminary refresh signal AREF_PRE is generated with the predetermined pulse width in response to a falling edge of the auto refresh signal AREF. Furthermore, pulses after the second pulse of the preliminary refresh signal AREF_PRE are also generated in response to falling edges of the auto refresh signal AREF.

More specifically, the preliminary refresh signal generation unit320includes a first NAND gate ND31, a second NAND gate ND32, a first delay3200, and a third pulse generator3201. The first NAND gate ND31is configured to perform a NAND operation on the preliminary initialization signal DAI_PRE and the auto refresh signal AREF. The second NAND gate ND32is configured to perform a NAND operation on an output signal of the first NAND gate ND31, the flag signal RS_FLAG, and the power-up signal PWRUP. The first delay3200is configured to delay an output signal of the second NAND gate ND32. The third pulse generator3201is configured to generate the preliminary refresh signal AREF_PRE including a periodic pulse in response to an output signal of the first delay3200. The refresh counting signal generation unit321includes a third buffer unit3210, a second delay3211, and a refresh initialization signal generator3212. The third buffer unit3210is configured to buffer and output the preliminary refresh signal AREF_PRE. The second delay3211is configured to delay an output signal of the third buffer unit3210and output the delayed signal as the refresh counting signal AREF_CNT. The refresh initialization signal generator3212is configured to perform a NAND operation on the refresh counting signal AREF_CNT and the initialization signal DAI and generate the refresh initialization signal INIT_AREF. The refresh signal generation unit32configured in such a manner generates the refresh counting signal AREF_CNT, the refresh initialization signal INIT_AREF, and the preliminary refresh signal AREF_PRE including a pulse of the period where the auto refresh operation is repeated, in response to the flag signal RS_FLAG enabled in the initialization mode.

The configuration of the counter unit33will be described in more detail as follows with reference toFIG. 6.

Referring toFIG. 6, the counter unit33includes a counter330and a counting initialization signal generation unit331. The counter330is configured to count counting signals CNT<1:3> and CNTB<1:3> in response to the flag signal RS_FLAG and the refresh counting signal AREF_CNT. The counting initialization signal generation unit331is configured to generate the counting initialization signal INIT_CNT according to the logic level of the refresh counting signal AREF_CNT after a period where a combination of the counting signals CNT<1:3> and CNTB<1:3> becomes a preset combination. Here, the logic level comprises a logic high level and a logic low level. The “logic high level” and “logic low level” refers to, for example, voltage levels and/or voltage ranges that are predetermined to represent the high level or low level and not necessarily any specific values. Such “logic levels” may also be understood to correspond to logical or binary bit values, for example, where a “low logic level” corresponds to a logical “0” and a “high logic level” corresponds to a logical “1” or vice versa depending on specific implementations in the various embodiments. The counter unit33configured in such a manner counts the counting signals CNT<1:3> and CNTB<1:3> by the number of auto refresh operations which are repetitively performed in the initialization mode, and enables the counting initialization signal INIT_CNT according to the logic level of the refresh counting signal AREF_CNT after the period where the counting signals CNT<1:3> and CNTB<1:3> becomes a preset combination. Here, the counting signals CNTB<1:3> are inverted signals of the counting signals CNT<1:3>.

The operation of the semiconductor memory device including the initialization signal generation circuit configured in such a manner will be described with reference toFIG. 7. In the following descriptions, it is assumed that the auto refresh operation is repeated six times in the initialization mode, and the pulse width of the preliminary refresh signal may vary depending on a PVT variation.

First, when the power supply voltage VDD is supplied to the semiconductor memory device, the first initialization element P11of the flag signal generator10outputs the flog signal RS_FLAG having a logic low level, in response to the power-up signal PWRUP having a logic low level in the power-up period where the voltage level of the power supply voltage VDD rises to a target level. Furthermore, the second initialization element P31of the power-up signal PWRUP outputs the initialization signal DAI having a logic low level, in response to the power-up signal PWRUP.

Next, when the reset signal RESET is enabled to a logic low level and inputted from outside after the power-up period, the first pull-down signal generation unit110of the flag signal generator10generates the first pull-down signal PD<1> having a logic high level, and the first pull-down driver N10of the first driving unit120is configured to pull-down drive the first node nd10in response to the high-level first pull-down signal PD<1> such that the flag signal RS_FLAG is enabled to a logic high level. Furthermore, the second pull-down signal generation unit310of the initialization signal output unit31generates the second pull-down signal PD<2> having a logic high level in response to the high-level flag signal RS_FLAG, and the second pull-down driver N30of the second driving section320is configured to pull-down drive the second node nd30in response to the high-level second pull-down signal PD<2> such that the initialization signal DAI is enabled to a logic high level.

Then, after the auto refresh operation is repeated six times to set a combination of the counting signals CNT<1:3> to a preset combination of ‘L, H, H’, the counting initialization signal generation unit331generates the counting initialization signal INIT_CNT having a logic high level at a time point t10where the counting initialization signal INIT_CNT is delayed by the pulse width of the refresh counting signal AREF_CNT generated by buffering the preliminary refresh signal AREF_PRE. That is, although the pulse width of the preliminary refresh signal AREF_PRE may vary according to a PVT variation as shown in a period B ofFIG. 7, the counting initialization signal INIT_CNT is enabled to a logic high level at the time point t10where the refresh counting signal AREF_CNT generated by buffering the preliminary refresh signal AFEF_PRE is enabled to a logic low level. Here, when the counting signals CNT<1:3> are set to ‘L, H, H’, it means that the first counting signal CNT<1> is ‘L’, the second counting signal CNT<2> is ‘H’, and the third counting signal CNT<3> is ‘H’.

Then, the second pull-up signal generation unit ND30of the initialization signal output unit31generate the second pull-up signal PU<2> having a logic low level according to the high-level counting initialization signal INIT_CNT and the pulse of the preliminary refresh signal AREF_PRE which is generated in synchronization with a sixth falling edge of the auto refresh signal AREF at a time point t11. Furthermore, the second pull-up driver P30of the second driving unit311is configured to pull-up drive the second node nd30to a logic high level, in response to the low-level second pull-up signal PU<2>, and the second latch unit312generates the preliminary initialization signal DAI_PRE having a logic low level.

Then, the second buffer unit313of the initialization signal output unit31buffers the preliminary initialization signal DAI_PRE and outputs the initialization signal DAI having a logic low level at a time point t12. That is, after the auto refresh operation is performed six times in the initialization mode, the initialization signal DAI becomes a logic low level.

In accordance with the embodiment of the present invention, the semiconductor memory device may accurately set the level transitioning time point of the initialization signal, even though a PVT variation occurs. Therefore, the semiconductor memory device may perform the auto refresh operation to a desired level in the initialization mode, thereby performing a stable initialization operation. Furthermore, the semiconductor memory device may accurately screen the end time point of the initialization mode.