STATIC RANDOM-ACCESS MEMORY DEVICE WITH THREE-LAYERED CELL DESIGN

The present disclosure relates generally to static random-access memory (SRAM) devices. Specifically, the disclosure proposes a SRAM device with a three-layered SRAM cell design. The SRAM cell comprises a storage comprising four storage transistors, and comprises two access transistors to control access to the storage cell. The SRAM cell further comprises a stack of three layer structures. Two of the storage transistors are formed in a first layer structure of the stack, and two other of the storage transistors are formed in a second layer structure of the stack adjacent to the first layer structure. The two access transistors are formed in a third layer structure of the stack adjacent to the second layer structure. Each layer structure comprises a semiconductor material, the transistors in the layer structure are based on that semiconductor material, and at least two of the three layer structures comprise a different type of semiconductor material.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims foreign priority to European Application 21213663.4, filed Dec. 10, 2021, the content of which is incorporated by reference herein in its entirety.

BACKGROUND

Field

The present disclosure relates generally to static random-access memory (SRAM) devices. Specifically, the disclosure proposes a SRAM device with a three-layered SRAM cell design. The SRAM cell comprises a stack of three layer structures, and storage transistors and access transistors that are distributed among the three layer structures.

Description of the Related Technology

A SRAM device is a type of random-access memory (RAM) device that uses latching circuitry (flip-flop) to store each bit in a SRAM cell (memory cell) of the SRAM device. SRAM devices are volatile memory devices, i.e., the stored data is lost when power is removed from the SRAM device.

The term “static” differentiates SRAM devices from dynamic random-access memory (DRAM) devices, which must be periodically refreshed. SRAM devices are faster and more expensive than DRAM devices. SRAM cells are typically used for a central processing unit (CPU) cache, as they are built of the same basic components as the logic circuitry, namely transistors, so they can be integrated together with the logic circuitry. DRAM devices are typically used for a computer's main memory.

Due to the number of transistors required to implement the SRAM cell (four storage transistors and two access transistors), the storage density of a SRAM device is lower than that of a DRAM device, and its price is higher than that of a DRAM device. In addition, the power consumption of a SRAM device is high when data is being actively read or written. However, SRAM devices are faster and easier to manage than DRAM devices.

SRAM devices may be integrated as RAM or as cache memory in micro-controllers, or as the primary caches in powerful microprocessors, such as the x86 family, and many others, to store registers and parts of the state-machines used in some microprocessors.

A typical SRAM cell design of a SRAM device is shown inFIG.1. As mentioned above, the SRAM cell is made up of six transistors, for example, metal-oxide-semiconductor field-effect transistors (MOSFETs). Each bit is stored by the SRAM device in one SRAM cell, and there particularly in a storage cell including four storage transistors M1, M2, M3and M4. These four storage transistors M1, M2, M3and M4form two cross-coupled inverters, as can be seen inFIG.1. This transistor configuration has two stable states, which can be used to denote “0” and “1” of the stored bit. Two additional access transistors M5and M6serve to control the access to the storage cell during read and write operations.

Because there are six transistors in each SRAM cell of the SRAM device, a footprint of the SRAM cell is comparatively large.

SUMMARY OF CERTAIN INVENTIVE ASPECTS

In view of the above, this disclosure has the objective to reduce the footprint of a SRAM cell. Reducing the footprint of the SRAM cell would allow decreasing the size of the SRAM device as a whole, and thus further densifying SRAM areas in microprocessor chips. Another objective of this disclosure is accordingly to provide a smaller SRAM device, and to reduce the size of chips for the same functionality. However, the reduction of the footprint of the SRAM cell should not have any impact on classical logic circuitry design.

These and other objectives are achieved by the solutions provided in the independent claims. Advantageous implementations are defined in the dependent claims.

The solutions of this disclosure are based on stacking the six transistors of the SRAM cell in a stack of three layer structures, and based on using different types of semiconductor materials for fabricating at least two of the three layer structures.

A first aspect of this disclosure provides a SRAM device comprising: a storage cell for storing a bit, the storage cell comprising four storage transistors; two access transistors configured to control access to the storage cell for storing or reading the bit; and a stack of layer structures comprising three layer structures; wherein two storage transistors of the four storage transistors are formed in a first layer structure of the stack; wherein two other storage transistors of the four storage transistors are formed in a second layer structure of the stack adjacent to the first layer structure; wherein the two access transistors are formed in a third layer structure of the stack adjacent to the second layer structure; wherein each layer structure of the three layer structures comprises a semiconductor material and the transistors in the layer structure are based on the semiconductor material; and wherein at least two of the three layer structures comprise a different type of semiconductor material.

By distributing the six transistors over the stack of the three layer structures, and by using different types of semiconductor materials in at least two of the three layer structures, the footprint of the SRAM cell can be significantly reduced. Further, reducing the footprint of the SRAM cell allows decreasing the size of the SRAM device as a whole. The reduction of the footprint of the SRAM cell as proposed by this disclosure has advantageously no impact on classical logic circuitry design.

Each layer structure of the stack may be based on a single semiconductor material, which is of a certain type of semiconductor material. In this case, one layer structure of the three layer structures is based on a different semiconductor material than at least one of the other layer structures of the three layer structures. Some or each of the layer structures may also be based on more than one semiconductor material, which may be of the same type or may be of different types of semiconductor material. In this case, one layer structure of the three layer structures is based on different types of semiconductor materials than at least one of the other layer structures. For instance, if each layer structure is based on two semiconductor materials, one layer structure may comprise two different types of semiconductor material than at least one of the other two layer structures.

In an implementation of an SRAM device, the type of semiconductor material comprises: a silicon-based semiconductor material, or a two-dimensional (2D) semiconductor material, or an oxide semiconductor material.

This implementation distinguishes different types of semiconductor materials, as can be used in the three layer structures of the SRAM device of the first aspect. At least two of the three layer structures may comprise a different type of semiconductor material of these specific types. Notably, within one type of semiconductor material, there may be differences as well. For instance, a doping concentration or conductivity-type may be different, or certain material concentrations or ratios may be different. However, this is not enough for denoting a different type of semiconductor material in this disclosure. A different type of semiconductor in this disclosure means a different material system.

For example, silicon, silicon germanium, and silicon nitride would belong to the same type of semiconductor material in this disclosure. Likewise, for example, molybdenum disulfide (MoS2), tungsten diselenide (WSe2), and hafnium disulfide (HfS2) would belong to the same type of 2D semiconductor materials. Likewise, for example, indium gallium zinc oxide (IGZO), indium tin oxide (ITO), and indium zinc oxide (IZO) would belong to the same type of oxide semiconductor materials.

In an implementation of the SRAM device, the first layer structure and the second layer structure each comprise a silicon-based semiconductor material; and the third layer structure comprises a 2D semiconductor material and/or an oxide semiconductor material.

That is, in one embodiment, the first layer structure and the second structure can comprise the same type of semiconductor material, while the third layer structure can comprise a different type of semiconductor material. The first and the second layer structure may not comprise a 2D semiconductor material and/or an oxide semiconductor material, and the third layer structure may not comprise a silicon-based semiconductor material.

In an implementation of the SRAM device, with respect to a direction of stacking the layer structures of the stack: the second layer structure can be formed above the first layer structure, and the third layer structure can be formed above the first layer structure and the second layer structure.

For instance, the first layer structure may be formed on or above a substrate, and the second and the third layer structure may be formed on or above the first layer structure. Notably, in this disclosure “formed on” means formed directly on, and “formed above” means formed indirectly on with one or more other layers provided in between.

In an implementation of the SRAM device, the first layer structure and the second layer structure each can comprise a 2D semiconductor material and/or an oxide semiconductor material. The third layer structure can comprise a silicon-based semiconductor material.

That is, again the first layer structure and the second layer structure can comprise the same type of semiconductor material, while the third layer structure can comprise a different type of semiconductor material. The first and the second layer structure may not comprise a silicon-based semiconductor material, and the third layer structure may not comprise 2D semiconductor material and/or oxide semiconductor material.

In an implementation of the SRAM device, with respect to a direction of stacking the layer structures of the stack: the second layer structure can be formed above the third layer structure, and the first layer structure can be formed above the third layer structure and the second layer structure.

For instance, the third layer structure may be formed on or above a substrate, and the second and the first layer structure may be formed on or above the third layer structure.

In an implementation of the SRAM device, the first layer structure can be a doped layer structure of a first-conductivity type, and the second layer structure can be a doped layer structure of a second conductivity-type.

Notably, the first and the second layer structure may thereby be of the same type of semiconductor material or may be of a different type of semiconductor material.

In an implementation of the SRAM device, the first storage transistor and the second storage transistor can constitute a first complementary field effect transistor (CFET); and/or the third storage transistor and the fourth storage transistor can constitute a second CFET.

This allows a further reduction of the size of the SRAM cell, and thus of the SRAM device as a whole.

In an implementation of the SRAM device, the first CFET and/or the second CFET can be an integrated silicon-based nanosheet transistor.

In an implementation of the SRAM device, the SRAM device further can comprise a first vertical element electrically connecting a gate of a first storage transistor of the two storage transistors in the first layer structure to a gate of a second storage transistor of the two other storage transistors in the second layer structure; and/or a second vertical element electrically connecting a gate of a third storage transistor of the two storage transistors in the first layer structure to a gate of a fourth storage transistor of the two other storage transistors in the second layer structure.

In an implementation of the SRAM device, the SRAM device further can comprise: a third vertical element electrically connecting a source/drain of the first storage transistor, a source/drain of the second storage transistor, and a source/drain of a first access transistor of the two access transistors; and/or a fourth vertical element electrically connecting a source/drain of the third storage transistor, a source/drain of the fourth storage transistor, and a source/drain of a second access transistor of the two access transistors.

In an implementation of the SRAM device, the first vertical element can be electrically connected to the fourth vertical element; and/or the second vertical element can be electrically connected to the third vertical element.

The vertical elements of the above implementations can enable connecting the different transistors of the SRAM cell, so that the SRAM cell can be formed in the three layer structures. The wiring used can be substantially reduced by using the vertical elements, which thus contribute to the small footprint of the SRAM cell. At the same time, the reduced footprint may not have an impact on the circuit design of the SRAM cell.

In an implementation of the SRAM device, a source/drain of the first storage transistor and a source/drain of the third storage transistor can be connected to a ground line; and a source/drain of the second storage transistor and a source/drain of the fourth storage transistors can be connected to a supply voltage line.

In an implementation of the SRAM device, the SRAM device further can comprise a wordline arranged above the stack and electrically connected to the gates of the two access transistors or a wordline arranged between the second layer structure and the third layer structure and electrically connected to the gates of the two access transistors. The SRAM device further can comprise: a bitline arranged in the third layer structure and connected to the source/drain of the first access transistor, and a complementary bitline arranged in the third layer structure and connected to the source/drain of the second access transistor.

The arrangement of the ground line, the supply voltage line, the bitline, the complementary bitline, and the wordline can support the reduction of the footprint of the SRAM cell.

A second aspect of this disclosure provides a method for fabricating a static random-access memory, SRAM, device comprising a stack of layer structures comprising three layer structures, the method comprising: forming a first layer structure of the stack, wherein two storage transistors of a storage cell of the SRAM device are formed in the first layer structure; forming a second layer structure of the stack adjacent to the first layer structure, wherein two other storage transistors of the storage cell are formed in the second layer structure; forming a third layer structure of the stack adjacent to the second layer structure, wherein two access transistors are formed in the third layer structure, the two access transistors being configured to control access to the storage cell for storing or reading a bit to or from the storage cell; and wherein each layer structure of the three layer structures comprises a semiconductor material and the transistors in the layer structure are based on the semiconductor material, and wherein at least two of the three layer structures comprise a different type of semiconductor material.

The method of the second aspect achieves the same advantages as the device of the first aspect and may be extended by respective implementations as described above for the device of the first aspect.

In summary, this disclosure proposes an SRAM device, wherein a footprint of one or more SRAM cells is substantially reduced. Several advantages can be achieved by the design of the SRAM cell. For instance, ground line, supply voltage line, bitline(s), and wordline(s) can be organized in a way that substantially reduces the required wiring. This may also reduce the RC delay. Further, the size of the access transistors can be tuned without changing the footprint of the SRAM cell. For instance, a current in the access transistors can be selected differently than a current in the storage transistors. The different types of semiconductor materials, in particular the 2D materials and/or semiconductor oxide materials in at least one layer structure combined with a silicon-based material in at least one layer structure, allow reducing the footprint of the SRAM cell without any impact on the classical logic circuitry design. In fact, the other semiconductor materials added to the silicon-based semiconductor materials may bring additional functionality in back-end-of-line (BEOL) processing.

DETAILED DESCRIPTION OF CERTAIN ILLUSTRATIVE EMBODIMENTS

FIG.2shows an SRAM cell20of an SRAM device according to an embodiment of this disclosure. The SRAM device may have multiple of such SRAM cells20, and each SRAM cell20may be configured to store a bit.

To this end, the SRAM cell20can include a storage cell for storing the bit. The storage cell of the SRAM cell20can include four storage transistors, in particular, it can include a first storage transistor M1, a second storage transistors M2, a third storage transistor M3, and a fourth storage transistor M4. The four storage transistors M1-M4may form two cross-coupled inverters, as in a conventional SRAM cell (see, e.g.,FIG.1).

Further, the SRAM cell20can include two access transistors, in particular, it can include a first access transistor M5and a second access transistor M6. The two access transistors M5and M6are configured to control access to the storage cell for storing or reading the bit, as in a conventional SRAM cell (see, e.g.,FIG.1).

The SRAM cell20can include a stack of layer structures, wherein the stack comprises three layer structures, in particular, it can include a first layer structure21, a second layer structure22, and a third layer structure23. The four storage transistors M1-M4and the two access transistors M5and M6can be formed in and distributed over the stack of the three layer structures21,22, and23.

In particular, two storage transistors—for example, the first storage transistor M1and the third storage transistors M3—of the four storage transistors M1-M4can be formed in the first layer structure21of the stack. The other two storage transistors—in this example, the second storage transistor M2and the fourth storage transistor M4—of the four storage transistors M1-M4can be formed in the second layer structure22of the stack. The second layer structure22can be adjacent to the first layer structure21in the stack. The two access transistors M5and M6can be formed in the third layer structure23of the stack, and the third layer structure23can be adjacent to the second layer structure22of the stack.

Each respective layer structure of the at least three layer structures21,22, and23can comprise a semiconductor material. The respective layer structure of the at least three layer structures21,22and23may be formed from the semiconductor material. The transistors, which can be arranged in the respective layer structure21,22, or23, can be based on said semiconductor material (e.g., formed using the semiconductor material).

At least two of the three layer structures21,22,23can comprise a different type of semiconductor material. For example, the first layer structure21may comprise a first semiconductor material, and the first storage transistor M1and the third storage transistor M3can be based on the first semiconductor material. Further, the second layer structure22may comprise a second semiconductor material22, and the second storage transistor M2and the fourth storage transistor M4can be based on the second semiconductor material. Finally, the third layer structure23may comprise a third semiconductor material22, and the first access transistor M5and the second access transistor M6can be based on the third semiconductor material. For example, the third semiconductor material may be of a different type of semiconductor material than the first semiconductor material and/or than the second semiconductor material.

In some embodiments, the first semiconductor material may form the transistor channels of respectively the first storage transistor M1and the third storage transistor M3. The second semiconductor material may form the transistor channels of respectively the second storage transistor M2and the fourth storage transistor M4. The third semiconductor material may form the transistor channels of respectively the first access transistor M5and the second access transistor M6. Possible types of semiconductor materials, which may be used to form the stack, may include silicon-based semiconductor materials, 2D semiconductor materials, and semiconductor oxide materials. An alternative to the silicon-based semiconductor material may be another group IV semiconductor material, for example, germanium. For example, the third semiconductor material can comprise a 2D semiconductor material. In this case the first semiconductor material and/or the second semiconductor material can comprise a silicon-based semiconductor material and/or an oxide semiconductor material. In another example, the third semiconductor material can comprise a silicon-based semiconductor material. In this case the first semiconductor material and/or the second semiconductor material can comprise a 2D semiconductor material and/or an oxide semiconductor material. In another example, the third semiconductor material can comprise an oxide semiconductor material. In this case the first semiconductor material and/or the second semiconductor material can comprise a 2D semiconductor material and/or a silicon-based semiconductor material.

It is possible that each of the three layer structures21,22, and23is made up of a different type of semiconductor material (e.g., the stack can include at least three different types of semiconductor materials). Generally, however, the stack of layer structures in this disclosure includes at least two different types of semiconductor materials. That is, one layer structure of the stack can comprise one type of semiconductor material, while another layer structure of the stack can comprise another type of semiconductor material. Notably, each layer structure21,22, and23of the stack may itself comprise only one type of semiconductor material or may itself comprise more than one type of semiconductor material. However, two layer structures21,22,23comprising a different type of semiconductor material preferably do not share a type of semiconductor material.

FIGS.3A and3Bshow a first example of the SRAM cell20of a SRAM device according to an embodiment of this disclosure, which builds on the embodiment shown inFIG.2. Like elements inFIG.2,FIG.3A, andFIG.3Bare labelled with the same reference signs and can be implemented likewise. In particular,FIG.3Ashows the SRAM cell20in a sectional view, andFIG.3Bshows a schema of the SRAM cell20.

In the example SRAM cell20ofFIG.3A, the first layer structure21and the second layer structure22each comprise the same type of semiconductor material, and as a particular example, they both comprise a silicon-based semiconductor material. The third layer structure23comprises a different type of semiconductor material than the first and the second layer structure22and23, and in this particular example, it comprises at least one of a 2D semiconductor material and an oxide semiconductor material. The silicon-based semiconductor material may be silicon and/or silicon-germanium. The 2D semiconductor material may be carbon-based, e.g., graphene, or based on boron nitride or transition metal dichalcogenides. The semiconductor oxide material may be IGZO, ITO, or IZO.

With respect to a direction of stacking the three layer structures21,22, and23of the stack (along the vertical direction inFIG.3A), the second layer structure22is arranged above the first layer structure21, and the third layer structure23is arranged above the first layer structure21and the second layer structure22. The first layer structure21may be arranged on a substrate or may be arranged on a base material layer.

In this first example, the SRAM cell20may comprise the four storage transistors M1-M4in the so-called complementary field effect transistor (CFET) architecture. That is, the first storage transistor M1and the second storage transistor M2may constitute a first CFET and the third storage transistor M3and the fourth storage transistor M4may constitute a second CFET. At least one of the first CFET and the second CFET can be an integrated silicon-based nanosheet transistor. That is, the SRAM cell20may be based on one or two heterogeneously integrated silicon nanosheet transistors M1/M2and M3/M4, respectively. The integration of the access transistors M5and M6based on the 2D semiconductor material and/or the semiconductor oxide material may be on top of the storage transistors M1-M4.

FIGS.5A and5Bshow a second example of the SRAM cell20of a SRAM device according to an embodiment of this disclosure, which builds on the embodiment shown inFIG.2. Same elements inFIG.2,FIG.5A, andFIG.5Bare labelled with the same reference signs, and can be implemented likewise. In particular,FIG.5Ashows the SRAM cell in a sectional view, andFIG.5Bshows a schema of the SRAM cell20.

In the SRAM cell ofFIG.5A, the first layer structure21and the second layer structure22each comprise, as another particular example, a 2D semiconductor material and/or an oxide semiconductor material. That is, they may be formed of the same type or of a different type of semiconductor material (in the latter case, one can be based on the 2D semiconductor material, and the other one can be based on the semiconductor oxide material). The third layer structure23can comprise a different type of semiconductor material from the first and/or second layer structures22,23, and in this further particular example, it can comprise a silicon-based semiconductor material. Again, the silicon-based semiconductor material may be silicon and/or silicon-germanium. The 2D semiconductor material may again be carbon-based, e.g., graphene, or based on boron nitride or transition metal dichalcogenides. The semiconductor oxide material may again be IGZO, ITO, or IZO.

With respect to a direction of stacking the layer structures of the stack (along the vertical direction inFIG.5A), the second layer structure22is arranged above the third layer structure23, and the first layer structure21is arranged above the third layer structure23and the second layer structure22. The third layer structure21may be arranged on a substrate, or on a base material layer, or the like.

In this second example, the SRAM cell20may comprise the four storage transistors M1-M4in the CFET architecture. For example, the first storage transistor M1and the second storage transistor M2may constitute a first CFET, and the third storage transistor M3and the fourth storage transistor M4may constitute a second CFET.

FIG.3BandFIG.5Bshow the schema of the respective SRAM cell20ofFIG.3AandFIG.5A, which corresponds to the conventional schema shown inFIG.1. Relevant portions in the schemas of the SRAM cell20are labelled and emphasized with different shadings.FIG.3AandFIG.5Ashow in the sectional view the first and the second example of the SRAM cell20, respectively, with the corresponding relevant parts labelled and emphasized with the same different shadings. The labelled elements in the sectional viewFIG.3AandFIG.5Acorrespond to the labelled wirings between the different transistors M1-M6in the SRAM cell20as shown inFIG.3BandFIG.5B.

It can be seen in bothFIG.3AandFIG.5Athat the SRAM cell20may comprise, in the first example and in the second example, a first vertical element31, a second vertical element32, a third vertical element33, and a fourth vertical element34. Notably, “vertical” is defined to be along the stacking direction of the stack of the three layer structures21,22, and23of the SRAM cell20. “Vertical” may be along the vertical direction (bottom to top) inFIG.3AandFIG.5A, which may correspond to a z-axis of a Cartesian coordinate system. The sectional view of the SRAM cell20can be along the x-axis of this Cartesian coordinate system, and may be “horizontal” (left to right) inFIG.3AandFIG.5A. The y-axis of the Cartesian coordinate system can be into the figure plane inFIG.3AandFIG.5A.

The first vertical element31can electrically connect a gate of the third storage transistor M3in the first layer structure21to a gate of the fourth storage transistor M4in the second layer structure22. The second vertical element32can electrically connect a gate of the first storage transistor M1in the first layer structure21to a gate of the second storage transistor M2in the second layer structure22. The third vertical element can electrically connect a source/drain of the first storage transistor M1, a source/drain of the second storage transistor M2, and a source/drain of the first access transistor M5. The fourth vertical element34can electrically connect a source/drain of the third storage transistor M3, a source/drain of the fourth storage transistor M4, and the source/drain of a second access transistor M6. Each vertical element31,32,33,34accordingly can connect transistor parts that are formed in different layer structures21,22,23of the stack, wherein the different layer structures21,22,23can be arranged along the stacking direction of the stack. For example, the layer three structures21,22,23may be arranged above each along the vertical direction. In this sense, each vertical element can be at least partly vertical, but does not have to be only vertical (in its extension). Further, the first vertical element31can be electrically connected to the fourth vertical element34, and the second vertical element32can be electrically connected to the third vertical element33in the first example or the second example of the SRAM cell20. The electrical connections provided by the vertical elements31-34correspond to the wirings between the transistors M1-M6, which are shown in the schema ofFIG.3BandFIG.5Brespectively.

In addition, it can be seen inFIG.3AandFIG.5Athat the SRAM cell20, in the first and in the second example, has a source/drain of the first storage transistor M1and a source/drain of the third storage transistor M3connected to a ground line39. Further, a source/drain of the second storage transistor M2and a source/drain of the fourth storage transistor M4are connected to a supply voltage line38(also “Vd” or “Vdd” in this disclosure).

Finally, it can be seen inFIG.3AandFIG.5Athat the SRAM cell20, in the first and in the second example, can comprise a wordline35, a bitline36, and a complementary bitline37. The wordline35in the first example can be arranged above the stack, and can be electrically connected to the gates of the two access transistors M5and M6. The wordline35in the second example can be arranged between the second layer structure22and the third layer structure23, and can be electrically connected to the gates of the two access transistors M5and M6. The bitline36can be arranged in the third layer structure23in both examples, and can be connected to the source/drain of the first access transistor M5. The complementary bitline37can be arranged in the third layer structure23in both examples, and can be connected to the source/drain of the second access transistor M6.

The ground line39, supply voltage line38, bitline36, complementary bitline37, and wordline39are also shown in the schema of the SRAM cell20inFIG.3BandFIG.5B.

FIG.4Ashows the first example of the SRAM cell20in a top view, andFIG.4Bshows the same schema as inFIG.3Bfor ease of reference.FIG.6Ashows the second example of the SRAM cell20in a top view, andFIG.6Bshows the same schema as inFIG.5Bfor ease of reference. Like elements inFIGS.3A-4B, as well asFIGS.5A-6Bare labelled likewise and shown in the same shadings. The top views of the SRAM cell20inFIG.4BandFIG.6Bshow the SRAM cell20along the above-mentioned x-axis (left to right) and y-axis (bottom to top) of the Cartesian coordinate system, while the z-axis is into the figure plane.

The dashed squares inFIG.4AandFIG.6Aindicate the final footprint of one SRAM cell20. Notably, in these figures, two SRAM cells20are shown next to each other, which share the same bitline36, wordline35, ground line39and supply voltage line38. As can be seen, the small footprint of the SRAM cell20can be achieved by the stacking of the three layer structures, comprising two transistors each, and the (vertical) connection elements used for connecting the six transistors as shown in the schema of the SRAM cell20.

The two flip-flops (cross-coupled inverters, which are formed by the storage transistors M1-M4) can be integrated in the first layer structure21and the second layer structure22, while the access transistors that may drive (read and write) the flip-flops are integrated in the third layer structure23. In the first example of the SRAM cell20, the access transistors M5and M6may be freely accessible for the wordline and the bitline(s).

The design of the SRAM cell20can enable greatly simplifying the interconnect scheme, as there is no need to connect the ground line39and the supply voltage line38connection to the top of the SRAM cell20(third layer structure23in the first example, first layer structure21in the second example). Instead, they can be connected at the beginning and the end of the SRAM arrays comprising multiple SRAM cells20. Notably, in the integration scheme, the contact to the transistors M1and M3and the gates of the transistors M2and M4may be slightly shifted to make the connection better possible. Finally, since in the first example of the SRAM cell20the access transistors M5and M6are on top of the SRAM cell20, a channel width of these access transistors M5and M6can be fine-tuned to optimize the read and write current of the SRAM cell20, and to fine-tune the switching speed.

FIG.7shows a flow-diagram of a basic method70, which may be used to fabricate the SRAM cell20according to an embodiment of this disclosure, in particular, the embodiment shown inFIG.2. The method70may also be used to fabricate the SRAM device comprising the stack of layer structures comprising the three layer structures21,22, and23.

The method70comprises a step71of forming the first layer structure21of the stack, wherein two storage transistors, e.g., M1and M3, of the storage cell of the SRAM device are formed in the first layer structure21. Further, the method70comprises a step72of forming the second layer structure22of the stack adjacent to the first layer structure21, wherein two other storage transistors, e.g., M2and M4, of the storage cell are formed in the second layer structure22. The method70also comprises a step73of forming the third layer structure of the stack adjacent to the second layer structure22, wherein the two access transistors M5and M6are formed in the third layer structure23. The method70can be performed such that each layer structure of the three layer structures21,22, and23comprises a semiconductor material, wherein the transistors in the layer structure are based on the semiconductor material, and such that at least two of the three layer structures21,22, and23comprise a different type of semiconductor material. Notably, there is no particular order in which the steps71-73are to be performed, and no step has to be completed before another step may be started.

FIG.8A-14Bshow a specific process80for fabricating the first example of the 3-level stacked SRAM cell20shown inFIGS.3A-3BandFIGS.4A-4B.FIGS.8A,9A,10A,11A,12A,13A, and14Ashow over time the sectional view (showing the x-axis and z-axis) of the proposed SRAM cell20.FIGS.8B,9B,10B,11B,12B,13B, and14Bshow over time the top view (showing the x-axis and y-axis, and being indicative of the footprint) of the proposed integrated SRAM cell20.

FIGS.8A and8Bshow a first step of the process80, in which the first layer structure21and the second layer structure22are formed on top of each other. For instance, the first layer structure21and the second layer structure22may be doped to the n-type and the p-Type, respectively, and may be processed like a conventional CFET (e.g., using the Intel Flow). In particular, the first layer structure21and the second layer structure22may each be a silicon nanosheet. Source/drain (S/D) contacts may be processed in the first layer structure21(which may, e.g., be an N-type silicon nanosheet), wherein these S/D contacts are for the first storage transistor M1and the third storage transistor, respectively, which are formed in the first layer structure21. The outer S/D contacts inFIGS.8A and8Bmay be intended for ground (Gr), which may be connected to the S/D of the first storage transistor M1and to the S/D of the third storage transistor M3in the final SRAM cell20.

FIGS.9A and9Bshow a second step of the process80, in which S/D contacts are also made in the second layer structure22(which may, e.g., be a p-type silicon nanosheet), wherein these S/D contacts made in the second layer structure22are connected to the S/D contacts made in the first layer structure21, in the middle of SRAM cell20. The S/D contacts made in the second layer structure22are for the second storage transistor M2and the fourth storage transistor M4, respectively, which are formed in the second layer structure22. The connection may be realized by forming the third vertical element33and the fourth vertical element34. The third vertical element33at this stage of the process80connects the S/D for the first storage transistor M1with the S/D for the second storage transistor M2. The fourth vertical element34at this stage of the process80connects the S/D for the third storage transistor M3and the S/D for the fourth storage transistor M4.

FIGS.10A and10Bshow a third step of the process80, in which gate contacts are processed in the first layer structure21and the second layer structure22, in particular, for the storage transistors M1-M4. The gate contacts are processed by forming the first vertical element31and the second vertical element32. At this stage of the process80, the first vertical element31connects a gate for the first storage transistor M1in the first layer structure21to a gate for the second storage transistor M2in the second layer structure22, and the second vertical element32connects a gate for the third storage transistor M3in the first layer structure21to a gate of the fourth storage transistor M4in the second layer structure22.

FIGS.11A and11Bshow a fourth step of the process80, in which a further S/D contact is formed in the second layer structure. This S/D contact is intended for the supply voltage (Vd), which may be supplied to the S/D of the second storage transistor M2and to the S/D of the fourth storage transistor M4in the final SRAM cell20.

FIGS.12A and12Bshow a fifth step of the process80, in which the storage transistors M1-M4are connected. In particular, the gates of the first and the second storage transistor M1and M2, which are connected to each other by the first vertical element31, are further connected to the S/D contact of the third and the fourth storage transistor M3and M4, which are already connected to each other by the fourth vertical element. The further connection is realized by connecting the first vertical element31to the fourth vertical element34. Further, the S/D contacts of the first and the second storage transistor M1and M2, which are connected to each other by the third vertical element33, are further connected to the gates of the third and the fourth storage transistor M3and M4, which are already connected to each other by the second vertical element. This further connection is realized by connecting the third vertical element33to the second vertical element32.

FIGS.13A and13Bshow a sixth step of the process80, in which the bitline36and the complementary bitline37are formed, and in which further contacts to the storage transistors M1-M$ are processed by vertically extending the third vertical element33and the fourth vertical element34(as also indicated by the squares inFIG.13B).

FIGS.14A and14Bshow a seventh step of the process80, in which the third layer structure23is processed and the wordline35is processed. Processing the third layer structure23includes forming the first and second access transistors M5and M6. The bitline36is connected to the S/D of the first access transistor M5, and the complementary bitline37is connected to the S/D of the second access transistor M6. The wordline35is connected to the gates of the two access transistors M5and M6. This step concludes the processing of the SRAM cell20.

Two or more SRAM cells20may be processed in parallel according to this process80.FIG.14Bshows again that this process80finally achieves a SRAM cell20with a very small footprint. Nevertheless, the SRAM cell20can still be wired according to a conventional SRAM schema, for example as shown inFIG.1.