IC chip package with isolated vias

An IC chip package includes a substrate (2), a chip (5), a plurality of bonding wires (52), and a cover (6). The substrate has a top surface, a receiving chamber (23) having an opening at the top surface, a plurality of solder pads (3) arranged around the top surface and respectively corresponding to the solder pads arranged at a bottom surface opposite to the top surface, and a plurality of vias (4) having conductive material electrically connecting the top solder pads with the bottom solder pads defined therein. The chip is mounted in the receiving chamber, and has a plurality of chip solder pads (51) arranged around a top surface thereof. The bonding wires respectively electrically connect the top solder pads of the substrate with the chip solder pads. The cover is fastened to the top surface of the substrate, and covers the opening.

FIELD OF THE INVENTION

The present invention relates generally to an integrated circuit (IC) chip package, and more particularly to a small sized IC chip package with isolated vias.

BACKGROUND

FIG. 3illustrates an IC chip package according to China Pat. No. 01200427.8 issued on Oct. 31, 2001. The IC chip package is constructed to include a substrate10, a chip12, a cover13, and adhesive means14. The substrate10includes a top side101and a receiving chamber102. The receiving chamber102has an opening at the top side101. The top side101is provided with a plurality of connecting pads arranged around the opening of the receiving chamber102. The substrate10further includes a plurality of plated through holes103provided around a periphery thereof, in order to electrically connect the connecting pads at the top of the substrate10to a bottom of the substrate10. The chip12is fixedly mounted in the receiving chamber102. The chip12is provided with a plurality of connecting pads respectively electrically connected to the connecting pads of the substrate10by means of bonding wires15. The adhesive means14is applied on areas where the bonding wires15connect with the connecting pads of the substrate10. The cover13is fixedly fastened to the adhesive means14, thereby covering the opening of the receiving chamber102. When the IC chip package is installed on a circuit board, tin solder is applied to bottoms of the through holes103. The chip12is thereby electrically connected to a conductive circuit pattern of the circuit board.

In this IC chip package, it is generally difficult to control the amount of the adhesive means14applied. If insufficient adhesive means14is used, the cover13may not properly adhere to the substrate10. Over time, tiny gaps may form between the cover13and the top side101of the substrate10. If this happens, moisture may penetrate inside the receiving chamber102and adversely affect the functioning of the chip12. In addition, the cover13may become detached from the substrate10, which frequently causes complete failure of the IC chip package. On the other hand, if excessive adhesive means14is used, the adhesive means14is liable to overflow down along the through holes103to the bottom of the substrate10. If this happens, the adhesive means14may form insulating coatings on the bottoms of the through holes103, which frequently results in the substrate10being unable to properly electrically connect with the circuit board. Either way, the quality and/or reliability of the IC chip package is liable to be reduced.

Furthermore, the through holes103are exposed to ambient air, and are liable to be affected by oxidation or contamination. This can lead to faulty electrical connection of the substrate10with the circuit board.

What is needed, therefore, is an IC chip package with isolated vias having high quality and reliability.

SUMMARY

In a preferred embodiment, an IC chip package includes a substrate, a chip, a plurality of bonding wires, and a cover. The substrate includes a top surface, a bottom surface opposite to the top surface, a receiving chamber having an opening at the top surface, a plurality of solder pads arranged around the top surface and the bottom surface, and a plurality of vias. The bottom solder pads respectively correspond to the solder pads arranged around the top surface. The vias are defined in the substrate, and having conductive material defined therein in order to electrically connect the top solder pads with the bottom solder pads. The chip is mounted in the receiving chamber of the substrate, and includes a plurality of solder pads arranged around a top surface thereof. The bonding wires respectively electrically connect the top solder pads of the substrate and the solder pads of the chip. The cover is fastened to the top surface of the substrate, and covers the opening.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Referring toFIG. 1andFIG. 2, an electronic package like an IC chip package in accordance with one embodiment of the present invention is shown. The IC chip package includes a substrate2, a plurality of electrical conductors like solder pads3, a plurality of connecting means like vias4, a chip5, a plurality of bonding wires52, and a cover6.

The substrate2is made of a material such as a ceramic material or a fibrous composite material. The substrate2includes a frame substrate21and a board substrate22. The frame substrate21is fixedly mounted on a top surface of the board substrate22to form the substrate2. The top surface of the board substrate22and an inner wall of the frame substrate21cooperatively define a receiving chamber23therebetween. The receiving chamber23includes an opening at a top surface of the substrate2. The opening communicates with an outside, so that the receiving chamber23can receive an electronic component such as the chip5.

The top surface and a bottom surface opposite to the top surface of the substrate2are provided with the solder pads3, in order to electrically connect the chip5on the substrate2with an electronic component such as a circuit board (not shown). The solder pads3include a plurality of top solder pads31as first electrical conductors embedded in the top surface portion of the substrate2. Each top solder pad31corresponds to a respective bottom solder pad32as a second electrical conductor embedded in a peripheral region of a bottom surface portion of the substrate2. An outer end of each top solder pad31is spaced a certain distance from an outer wall of the substrate2.

The vias4are defined in the substrate2between the top solder pads31and the bottom solder pads32. The vias4include a plurality of top via portions41defined in the frame substrate21, and a plurality of bottom via portions42defined in the board substrate22. Each top via portion41corresponds to and communicates with a respective bottom via portion42when the frame substrate21is fixedly mounted on the board substrate22. A top of each top via portion41is covered by a respective top solder pad31, and a bottom of each bottom via portion42is covered by a respective bottom solder pad32. Each via4is filled with or plated with a conductive material, in order to electrically connect the top solder pad31with the corresponding bottom solder pad32. In the illustrated embodiment, each via4further includes an offset like a horizontal intermediate via portion (not labeled) interconnecting the top via portion41with the bottom via portion42. The intermediate via portion is defined in a bottom surface portion of the frame substrate21. Alternatively, the intermediate via portion can be defined in a top surface portion of the board substrate22, or in both the bottom surface portion of the frame substrate21and the top surface portion of the board substrate22. In the illustrated embodiment, each intermediate via portion comprises a termination at the outer wall of the substrate2.

In a further alternative embodiment, each top via portion41is aligned with a corresponding bottom via portion42. That is, there are no intermediate via portions. This facilitates easy manufacturing of the substrate2with the vias4.

The chip5is glued to a bottom of the receiving chamber23. A peripheral region of a top surface of the chip5is provided with a plurality of chip solder pads51.

The bonding wires52are made of conductive material such as gold or aluminum alloy. One end of each bonding wire52is connected to a respective top solder pad31of the substrate2, and the other end of the bonding wire52is connected to a respective chip solder pad51of the chip5. Adhesive is applied to cover the bonding wires52, and areas where the bonding wires52connect with the top and chip solder pads31,51. The adhesive may for example be a silicone, epoxy, acrylic, or polyamide adhesive. The adhesive provides a protective coating for the bonding wires52, and reinforces the connections of the ends of the bonding wires52with the top solder pads31and the chip solder pads51.

The cover6can be an opaque plate member or a transparent plate member. Sides of the cover6can be glued to the top surface of the frame substrate21in order to cover the opening of the receiving chamber23. The chip5is thereby protected from external impact or contamination.

In the preferred embodiments, it is of advantage that the vias4are defined in the substrate2and covered by the top solder pads31and the bottom solder pads32. This helps prevent the adhesive from entering the vias4. In addition, the vias4are isolated from ambient air, so that the conductive material therein is protected from oxidation and contamination. Furthermore, the protective coatings protect the bonding wires5from breakage. Moreover, the top solder pads31are spaced a certain distance from the outer wall of the substrate2. Therefore when the adhesive is applied to cover the areas where the bonding wires5connect with the top solder pads31, there is minimal risk of excess adhesive overflowing down along the outer wall of the substrate2. These benefits help prolong the reliability and useful working lifetime of the IC chip package.