Method for fabricating high voltage drift in semiconductor device

A drift of a high voltage transistor formed using an STI (shallow trench isolation). The method for forming a high voltage drift of a semiconductor device can include forming a pad insulating film on a semiconductor substrate having a high voltage well; and then opening a region of the semiconductor substrate by patterning a portion of the pad insulating film; and then etching the opened region of the semiconductor substrate to form a trench; and then forming a first drift in the semiconductor substrate by performing a first ion implantation process using the patterned pad insulating film as a mask; and then forming a device isolation film by gap-filling a device isolation material in the trench; and then removing the patterned pad insulating film and then forming a gate electrode overlapping a portion of the device isolation film; and then forming a second drift connected to the first drift by performing a second ion implantation process in a region of the semiconductor substrate exposed by the gate electrode.

The present application claims priority under 35 U.S.C. 119 and 35 U.S.C. 365 to Korean Patent Application No. 10-2007-0052058 (filed on May 29, 2007), which is hereby incorporated by reference in its entirety.

BACKGROUND

A semiconductor integrated circuit may have a high voltage control device to which a high voltage is directly applied in order to directly control an external system that uses a high voltage. Such a high voltage control device may be needed in a circuit that requires a high breakdown voltage.

A CMOS device with small power consumption may generally be widely used as a high voltage control device. The CMOS device may include a PMOS (P-type MOS) transistor and an NMOS(N-type MOS) transistor. Each transistor may have a double diffused drain structure having the same conductive type lightly-doped region as a source and a drain formed at a lower part of the source and drain regions to obtain a high breakdown voltage.

In an MOSFET device having such a double diffused drain structure, a high voltage may be applied to a gate electrode and a drain region. Thereupon, a high electric field may be formed between the gate electrode and a substrate or between the drain region and the substrate. Meaning, as a high electric field is formed in a region adjacent to the drain region and the gate electrode, a problem that the breakdown voltage decreases arises.

Accordingly, a MOSFET device having an offset-LOCOS (Local Oxidation of Silicon) structure has been proposed in order to prevent decrease in breakdown voltage that arises in a MOSFET device having a double diffused drain structure.

ExampleFIG. 1illustrates a cross sectional view of a MOSFET having a LOCOS structure and may include Referring toFIG. 1an MOSFET device having an offset-LOCOS structure according to the conventional art includes n+source/drain regions141spaced apart from each other in a predetermined region in P−type semiconductor substrate100. Source/drain region141is disposed in an n−extended drain region acting as a drift region, for example, n−drift region103. Also formed in a surface of substrate100between n+source/drain region141and n−drift region103is channel forming region101. Gate electrodes, i.e., gate insulating film pattern121and gate conductive film pattern122are sequentially disposed on and/or over channel forming region101. N+source/drain regions141are electrically connected to source electrode S and drain electrode D. As a device isolation film of such an MOSFET device, LOCOS device isolation film111is used.

LOCOS device isolation film111plays a role of increasing the thickness of both sides of gate insulating film pattern121. By this, a high electric field applied to both sides of gate insulating film pattern121is distributed to both sides of gate insulating film pattern121at the time of device isolation, thus relieving stress caused by the electric field in these regions. As the thickness of gate insulating film pattern121increases, the electric stress caused by the electric field decreases.

Characteristics of the above MOSFET formed by a LOCOS process are determined by the thickness A of LOCOS device isolation film111, the size B of a channel operating at a high voltage, the size C of channel forming region101operating in a low voltage region, and the size D from the starting point of n−drift region103to the bird's beak S of LOCOS device isolation film111. To adjust the sizes B, C, and D, the size and thickness A of LOCOS device isolation film111function as the largest variable, however, there is a problem that it is generally difficult to adjust the size and thickness A of device isolation film111formed by the LOCOS method. In other words, since it is difficult to control the bird's beak S portion of device isolation film111by the process condition, it is impossible to adjust the thickness A of device isolation film111. Therefore, there is a problem that the characteristics of the MOSFET become worse because the sizes B, C, and D are arbitrarily changed due to the size of the bird's beak S. That is, if the size D becomes larger due to the bird's beak S, a single channel can be formed in conjunction with C, and if the size D becomes smaller, a well breakdown voltage may be a problem. Additionally, because n−drift region103is formed within semiconductor substrate100below device isolation film111, the size and doping concentration of n− drift region103become irregular due to the unevenness of the thickness A of device isolation film111, thereby deteriorating the characteristics of the MOSFET.

SUMMARY

Embodiments relate to a method for forming a high voltage drift of a semiconductor device, which can adjust the size of a channel operating at a high voltage, the size of a channel region operating in a low voltage region, and the size from the starting point of a drift region to the bird's beak of a device isolation film because a device isolation film of a desired size can be formed by forming an STI-type device isolation film in a high voltage transistor region of a semiconductor substrate.

Embodiments relate to a method for forming a high voltage drift of a semiconductor device, which can form a device isolation film of a desired size by device-isolating a high voltage transistor region from other regions and forming a drift in the high voltage transistor region by carrying out an STI process two times at the time of formation of a device isolation film of a semiconductor substrate having a high voltage transistor region and other regions.

Embodiments relate to a method for forming a high voltage drift of a semiconductor device which can include at least one of the following steps: forming a pad insulating film on and/or over a semiconductor substrate having a high voltage well; and then opening a region of the semiconductor substrate by patterning a portion of the pad insulating film; and then etching the opened region of the semiconductor substrate and then forming a trench; and then forming a first drift on and/or over the semiconductor substrate having the trench formed thereon by carrying out a first ion implantation process using the patterned pad insulating film as a mask; and the forming a device isolation film by gap-filling a device isolation material in the trench; and then removing the patterned pad insulating film and then forming a gate electrode so as to be overlapped with a part of the device isolation film; and forming a second drift connected to the first drift by carrying out a second ion implantation process onto a partial region of the semiconductor substrate exposed by the gate electrode.

In accordance with embodiments, the first and second ion implantation processes can preferably be performed under the same process condition, and the trench is formed by isotropic etching. The depth of the trench can be determined depending on a driving voltage of the semiconductor substrate.

Embodiments relate to a method for forming high voltage drift of a semiconductor device which can include at least one of the following steps: forming a pad insulating film on and/or over a semiconductor substrate having a high voltage transistor region; and then opening a region of the semiconductor substrate by patterning a portion of the pad insulating film; and then etching the opened region of the semiconductor substrate and then forming a first trench; and then forming a first drift on the semiconductor substrate having the trench formed thereon by carrying out a first ion implantation process using the patterned pad insulating film as a mask; and then forming a second trench by etching a part of the semiconductor substrate having the first trench in order to separate the high voltage transistor region and a logic region; and then forming first and second device isolation films by gap-filling a device isolation material in the first and second trenches; and then removing the patterned pad insulating film and then forming a gate electrode so as to be overlapped with a part of the first device isolation film; and then forming a second drift connected to the first drift by carrying out a second ion implantation process onto a partial region of the semiconductor substrate exposed by the gate electrode.

In accordance with embodiments, the first and second ion implantation processes can be performed under the same process condition, the first trench is formed by an isotropic etching process, and the depth thereof is determined depending on a driving voltage of the high voltage transistor. The second trench can be formed by an anisotropic etching process.

DESCRIPTION

As illustrated in exampleFIG. 2A, pad insulating film202is formed on and/or over semiconductor substrate200. Pad insulating film202can be formed by using SiN. Photoresist pattern204can then be formed on and/or over pad insulating film202. A P-well region or an N-well region for a high voltage can be formed in semiconductor substrate200. A portion of pad insulating film202may be opening in a predetermined region, i.e., an STI forming region, of substrate200.

Here, a well formation process for a high voltage will be described. A well for a high voltage is formed in semiconductor substrate200by performing an ion implantation process using a well mask, and then carrying out annealing. Next, the predetermined region of semiconductor substrate200, i.e., the STI forming region, can be exposed by etching pad insulating film202exposed by photoresist pattern204. A portion of semiconductor substrate200is isotropically etched by a chemical dry etching process, thereby forming trench T. The thickness of the trench T, i.e., the depth of semiconductor substrate200etched to form trench T, can be determined depending on a driving voltage of the high voltage transistor.

As illustrated in exampleFIG. 2B, to form a drift region, a first ion implantation process can then be carried out on the resultant structure to form a portion of n−drift206in trench T within semiconductor substrate200. Etched pad insulating film202and photoresist pattern204can be used as a first ion implantation process mask. A strip process can then be carried out to remove photoresist pattern204.

As illustrated in exampleFIG. 2C, device isolation film208can then be formed on and/or over n−drift206by depositing a device isolation insulating film so as to completely bury trench T and then carrying out a planarization process in which the pad insulating film202is used as a polishing start point. Device isolation insulating film208can be formed of O3TEOS film. The planarization process can be a CMP (chemical mechanical polishing) process. Pad insulating film202can then be removed by carrying out a wet etching process, such as by using phosphoric acid (H3PO4).

As illustrated in exampleFIG. 2D, gate insulating film210can then be formed on and/or over semiconductor substrate200by an oxidation process such as one of dry oxidation and wet oxidation. A conductive film for a gate electrode can then be formed on and/or over gate insulating film210. The conductive film for the gate electrode can be formed of an undoped or doped polysilicon film. The undoped silicon film can be formed by using SiH4or Si2H6by an LPCVD method. The doped silicon film can be formed by using SiH4and PH3or Si2H6and PH3by an LPCVD method. Continually, a photoresist pattern can be formed on and/or the conductive film by carrying out a mask process for defining a gate electrode. Gate electrode122can then be formed by etching the conductive film by carrying out an RIE (reactive ion etching) process. Gate electrode212can be formed so as to be overlapped a portion of device isolation film208and a portion of gate insulating film210.

As illustrated in exampleFIG. 2E, the photoresist pattern can then be removed by a strip process, and then a second ion implantation process can be carried out onto a region which is opened by gate electrode212and includes device isolation film208, thereby forming second n−drift214connected to first n−drift206and completing the drift. In accordance with embodiments, the second ion implantation process, no ions are implanted into semiconductor substrate200below device isolation film208. The first and second ion implantation processes can preferably be carried out under the same process condition.

An application of the above-described drift formation process in accordance with embodiments to a semiconductor device including a logic region will be described below.

As illustrated in exampleFIG. 3A, pad insulating film302can be formed on and/or over semiconductor substrate300. Pad insulating film302can be formed using SiN. Photoresist pattern304can then be formed in which a partial region of pad insulating film302, i.e., an STI forming region, is opened. A p-well region or an n-well region for a high voltage can be formed in semiconductor substrate300.

A well formation process for a high voltage will be described. A well for a high voltage can be formed in semiconductor substrate300by performing an ion implantation process using a well mask, and then carrying out an annealing process. A predetermined region of semiconductor substrate300, i.e., an STI forming region, can then be exposed by etching pad insulating film302exposed by photoresist pattern304. The predetermined region of semiconductor substrate300can then be isotropically etched by a chemical dry etching process, thereby forming first trench T1. The thickness of first trench T1, i.e., the depth of semiconductor substrate300etched to form the first trench T1, can be determined depending on a driving voltage of the high voltage transistor.

As illustrated in exampleFIG. 3B, a first ion implantation process can then be carried out on the resultant structure to form first n−drift306in first trench T1in semiconductor substrate300. Etched pad insulating film302and photoresist pattern304can be used as a first ion implantation process mask. A strip process can then be carried out to remove photoresist pattern304.

As illustrated in exampleFIG. 3C, etched pad insulating film302can then be patterned by a PEP (photo etching process) for forming second trenches T2to thus, open a portion of semiconductor substrate300in order to form a device-isolate a logic region (or other regions for other functions, for example, a low voltage transistor region) and an EDMOS region. The opened regions of semiconductor substrate300can then be etched, thereby forming second trenches T2. Second trench T2can be a region in which a device isolation film is formed in order to separate an EDMOS forming region and other regions, which can be formed by anisotropically etching a portion of semiconductor substrate300.

As illustrated in exampleFIG. 3D, first device isolation film308and second device isolation film310can then be formed by depositing an insulating film so as to completely bury the first trench T1and second trenches T2and then carrying out a planarization process in which pad insulating film302is used as a polishing start point. The device isolation insulating film can be formed as an O3TEOS film. The planarization process can be a CMP process.

As illustrated in exampleFIG. 3E, pad insulating film302can then be removed by carrying out a wet etching process such as by using phosphoric acid (H3PO4).

As illustrated in exampleFIG. 3F, gate insulating film312can then be formed on and/or over semiconductor substrate300by an oxidation process such as a dry or wet oxidation process. Conductive film314for a gate electrode can then be formed on and/or over gate insulating film312. Conductive film314can be formed of an undoped or doped polysilicon film. The undoped silicon film can be formed by using SiH4or Si2H6by an LPCVD method. The doped silicon film is formed by using SiH4and PH3or Si2H6and PH3by an LPCVD method.

As illustrated in exampleFIG. 3G, a photoresist pattern can then be formed on and/or over conductive film314by carrying out a mask process for defining a gate electrode. Gate electrode316can then be formed by etching conductive film314by carrying out an RIE process. Gate electrode316can be formed so as to be overlapped with a portion of first device isolation film308and gate insulating film312.

As illustrated in exampleFIG. 3H, the photoresist pattern can then be removed by a strip process. A second ion implantation process can then be carried out onto a region which is opened by gate electrode316and includes first device isolation film308, thereby forming second n−drift318connected to first n−drift306and completing the drift. In the second ion implantation process, no ions are implanted in semiconductor substrate300below first device isolation film308. The first and second ion implantation processes can preferably be carried out under the same process condition.

The size B of a channel operating at a high voltage, the size C of a channel region operating in a low voltage region, and the size D from the starting point of a drift region to the bird's beak of a device isolation film can be adjusted because it is possible to form first device isolation film308of a desired size by forming first device isolation film308of a STI type by etching a portion of semiconductor substrate300.

In accordance with embodiments, it is possible to form a drift having a uniform doping concentration because a portion of first n−drift306can be formed in semiconductor substrate300corresponding to first device isolation film308by a first ion implantation process and second n−drift318can be formed in other regions of semiconductor substrate300by a second ion implantation process after formation of gate electrode316.