Advanced seal ring structure and method of making the same

A semiconductor structure includes a substrate having a seal ring region and a circuit region; one or more dielectric layers disposed on the substrate; a connection structure disposed in the one or more dielectric layers in the seal ring region, wherein the connection structure includes a stack of metal layers and metal vias connecting the stack of metal layers; and a metal plug disposed between the substrate and the connection structure in the seal ring region, wherein the metal plug has a multi-step profile in a cross-sectional view.

BACKGROUND

In semiconductor technologies, a semiconductor wafer is processed through various fabrication steps to form integrated circuits (IC). Typically, several circuits or IC dies are formed onto the same semiconductor wafer. The wafer is then diced to cut out the circuits formed thereon. To protect the circuits from moisture degradation, ionic contamination, and dicing processes, a seal ring is formed around each IC die. This seal ring is formed during fabrication of the many layers that comprise the circuits, including both the front-end-of-line (FEOL) processing and back-end-of-line processing (BEOL). The FEOL includes forming transistors, capacitors, diodes, and/or resistors onto the semiconductor substrate. The BEOL includes forming metal layer interconnects and vias that provide routing to the components of the FEOL.

Although existing seal ring structures and fabrication methods have been generally adequate for their intended purposes, improvements are desired. For example, due to the shrinkage of circuits' critical dimension and metal routing density, there is an increased demand for better adhesion between substrate and metal features (such as metal contacts and metal interconnects) and between metal features and dielectric materials for both the circuits and the seal rings. Quality of metal filling is also a critical factor to impact functionality of seal rings. Poor metal filling, such as poor adhesion, seam, or void would impair the designed function of seal rings and cause delamination defects or cracks. Improvements in these areas as well as other improvements of seal rings are desired.

DETAILED DESCRIPTION

Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. Still further, when a number or a range of numbers is described with “about,” “approximate,” and the like, the term encompasses numbers that are within certain variations (such as +/−10% or other variations) of the number described, in accordance with the knowledge of the skilled in the art in view of the specific technology disclosed herein, unless otherwise specified. For example, the term “about 5 nm” may encompass the dimension range from 4.5 nm to 5.5 nm, 4.0 nm to 5.0 nm, etc.

This application generally relates to semiconductor structures and fabrication processes, and more particularly to semiconductor seal ring structures. In an embodiment of the present disclosure, a seal ring structure includes a connection structure and a plurality of metal plugs disposed between a substrate and the connection structure where each metal plug has a multi-step profile. The multi-step profile improves the filling of conductive materials that constitute the metal plugs and improves the adhesion between the metal plugs and the substrate, thereby improving the ability of the seal ring to withstand stress during dicing and improving the seal ring's operational reliability. Each metal plug may be formed into a ring or ring-like structure or multiple segments of a ring or ring-like structure. Each metal plug may be electrically connected to the connection structure using one or more via bars (long vias) or a series of small vias (round vias). In an embodiment, the seal ring structure further includes a plurality of dummy gates. The metal plugs and the dummy gates are alternately arranged to form a plurality of metal plug rings and a plurality of dummy gate rings. Forming the metal plugs and the dummy gates in such alternating manner substantially reduces or eliminates dishing in the seal ring region during chemical mechanical planarization (CMP) processing. In some embodiments, such metal plugs and dummy gates are also formed in an assembly isolation region that is disposed between a seal ring region and a circuit region. Having the metal plugs and the dummy gates in the assembly isolation region balances the topography loading during various processes, including CMP. In some embodiments, multiple (such as four) seal rings are formed in the seal ring region to further improve the seal ring structure's operational reliability. Those of ordinary skill in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein.

Referring now toFIG. 1, a top plan view is illustrated of a semiconductor structure (or semiconductor device)100including one or more circuit elements150(such as transistors, resistors, capacitors, memories, etc.) surrounded by a seal ring structure200.FIG. 2illustrates a cross-sectional view of an embodiment of the semiconductor structure100along the A-A line inFIG. 1, andFIGS. 3, 7, 8, 9, 10, and 11illustrate magnified top plan views of a portion B of the semiconductor structure100according to various embodiments.

Referring toFIG. 2, the semiconductor structure100includes a substrate202. The substrate202is a silicon substrate in the present embodiment. The substrate202may alternatively include other semiconductor materials in various embodiment, such as germanium, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, indium antimonide, SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, GaInAsP, or combinations thereof. The substrate202may include doped active regions such as a P-well and/or an N-well. The substrate202may also further include other features such as a buried layer, and/or an epitaxy layer. Furthermore, the substrate202may be a semiconductor on insulator such as silicon on insulator (SOI). In other embodiments, the semiconductor substrate202may include a doped epitaxy layer, a gradient semiconductor layer, and/or may further include a semiconductor layer overlying another semiconductor layer of a different type such as a silicon layer on a silicon germanium layer. In other examples, a compound semiconductor substrate may include a multilayer silicon structure or a multilayer compound semiconductor structure. The active region may be configured as an NMOS device (e.g., nFET) or a PMOS device (e.g., pFET). The substrate202may include underlying layers, devices, junctions, and other features (not shown).

The substrate202includes a seal ring region, over which the seal ring structure200is formed. The substrate202further includes a circuit region, over which the circuit elements150are formed. The substrate202further includes an assembly isolation region between the seal ring region and the circuit region and a scribe line region surrounding the seal ring region. During dicing, the semiconductor structure100is cut (for example, using a dicing saw or a laser) along the scribe line region, thereby forming a device or semiconductor chip (or an IC die) having the circuit elements150surrounded by the assembly isolation and the seal ring structure200.

The seal ring region further includes two sub seal ring regions, a first sub seal ring region and a second sub seal ring region. The first sub seal ring region is between the second sub seal ring region and the assembly isolation region. The first sub seal ring region is wider than the second sub seal ring region in the present embodiment. For example, the second sub seal ring region may be about 70% to 90% as wide as the first sub seal ring region. The second sub seal ring region is wider than the assembly isolation region. For example, the assembly isolation region may be about 70% to 90% as wide as the second sub seal ring region. In some embodiments, the width of the assembly isolation region may be in a range of about 5 microns to about 6 microns, the width of the first sub seal ring region may be in a range of about 8 microns to about 10 microns, and the width of the second sub seal ring region may be in a range of about 6 microns to about 8 microns.

Seal rings240and242are formed in the first sub seal ring region. Seal rings244and246are formed in the second sub seal ring region. The seal ring structure200includes the seal rings240,242,244, and246. The seal ring240is wider than the seal rings242,244, and246, thus may be referred to as the main seal ring. Seal rings244and246have about the same width. Seal ring242is narrower than the seal rings240,244, and246. Having multiple nested seal rings ensures that at least the inner seal ring(s) is/are protected from cracks during dicing (e.g., die sawing). For example, the seal rings246,244in the second sub seal ring region protect the seal rings242,240in the first sub seal ring region from damages that may occur during dicing.

Each of the seal rings240,242,244, and246includes one or more metal plugs214disposed on the substrate202. Even though not shown inFIG. 2, the substrate202includes active regions (such as N+or P+doped regions) over which the one or more metal plugs214are disposed. In the present embodiment, each metal plug214is formed into a multi-step profile with multiple sections that become wider as the height of the metal plug214increases. Having the multi-step profile improves the metal filling of the metal plugs214and eliminates seams and/or void in the metal plugs214. This greatly enhances the mechanical connection between the seal ring structure200and the substrate202. The aspects of the metal plugs214will be further described in later sections of the present disclosure.

Each of the seal rings240,242,244, and246includes a connection structure250that includes multiple metal layers251stacked one over another and vertically connected by metal vias252. Metal layers251and metal vias252may comprise copper, copper alloys, or other conductive materials and may be formed using damascene or dual damascene processes. Each of the metal layers251and the metal vias252may include a conductive barrier layer (such as TiN or TaN) surrounding a metal core (such as copper). Each of the seal rings240,242,244, and246further includes metal vias215that connect the metal plugs214to the connection structure250. In an embodiment, the vias215include tungsten. In alternative embodiments, the vias215include tungsten, cobalt, titanium, tantalum, ruthenium, or a combination thereof. In an embodiment, each of the metal layers251is formed into a ring or a ring-like structure (such as a substantially square ring) that surrounds the circuit region. In other words, each of the metal layers251is formed into a closed structure and extends along the edges of the area occupied by the circuit elements150. In the present embodiment, a ring or a ring-like structure refers to a closed structure, which may be rectangular, square, substantially rectangular, substantially square, or in other polygonal shapes. In an embodiment, the outer vias252(the vias252that are closest and the furthest, respectively, from the circuit region in each connection structure250) are formed into the shape of a ring surrounding the circuit region. Thus, they are also referred to as via bars. The inner vias252are formed into discrete vias that form a line parallel to the outer vias252. In the present embodiment, each of the seal rings240and244(main seal rings) further includes an aluminum pad264disposed on the connection structure250.

In the present embodiment, the seal rings240,244, and246further include dummy gates208and dummy gate vias209that connect the dummy gates208to the connection structures250. The device100further includes an interlayer210over the substrate202and extends across the circuit region, the assembly isolation region, the seal ring region, and the scribe line. In the assembly isolation region, the device100includes a plurality of metal plugs214′ and a plurality of dummy gates208′ that are disposed on an isolation structure (such as shallow trench isolation)204. The isolation structure204may include silicon oxide, silicon nitride, silicon oxynitride, other suitable isolation material (for example, including silicon, oxygen, nitrogen, carbon, or other suitable isolation constituent), or combinations thereof. Isolation structure204can include different structures, such as shallow trench isolation (STI) structures and/or deep trench isolation (DTI) structures. In some embodiments, the device100may include a connection structure250′ (for example, having various dummy lines and dummy vias) in the assembly isolation. A portion of the connection structure250′ is shown inFIG. 2. In some embodiments, the device100may include a connection structure250″ (for example, having various dummy lines and dummy vias) in the scribe line. A portion of the connection structure250″ is shown inFIG. 2. The metal plugs214,214′ and the dummy gates208and208′ are disposed at least partially in the interlayer210. Having the plurality of dummy gates208,208′ in the seal ring region and in the assembly isolation region substantially reduces or eliminates dishing in the seal ring region during CMP processing of the device200. The dummy gates208,208′ may be formed by depositing various material layers and etching/patterning the various material layers to form gate structures. Each dummy gate208,208′ may include a dummy gate dielectric layer (such as a layer having silicon dioxide, silicon oxynitride, a high-k dielectric layer, and/or other materials) and a dummy gate electrode layer (such as a layer having polysilicon or a metallic material). The dummy gates208,208′ may be formed using a gate first process or a gate last process. The interlayer210may include one or more dielectric materials such as silicon oxide, silicon nitride, or other suitable materials. The interlayer210may be deposited using CVD, ALD, or other suitable processes.

The device100further includes a stack of dielectric layers253over the interlayer210and a stack of dielectric layers255over the dielectric layers253. The connection structures250are disposed within the dielectric layers253,255. In an embodiment, the dielectric layers253are formed of a low-k dielectric material. For example, the dielectric constants (k values) of the dielectric layers253may be lower than 3.0, and even lower than about 2.5, hence may be referred to as extreme low-k (ELK) dielectric layers253. In an embodiment, the dielectric layers253include silicon oxide, silicon nitride, silicon oxynitride, TEOS formed oxide, PSG, BPSG, low-k dielectric material, other suitable dielectric material, or combinations thereof. In an embodiment, the dielectric layers255may be formed of un-doped silicate glass (USG) in order to improve the mechanical property and prevent moisture penetration.

The device100further includes a passivation layer260over the dielectric layers255and another passivation layer262over the passivation layer260. Each of the aluminum pads264includes a top portion that is disposed over the passivation layer260and a bottom portion that penetrates the passivation layer260and electrically connects to the connection structure250. In an example, the top portion of each aluminum pad264may have a width about 3 microns to about 4 microns, and the bottom portion of each aluminum pad264may have a width about 1.5 microns to about 2 microns. In an embodiment, each of the aluminum pads264is formed into a shape of a ring that surrounds the circuit region. Thus, the aluminum pads264may also be referred to as aluminum rings264. Aluminum pads264may be formed simultaneously with the formation of bond pads (not shown) that are exposed on the top surface of IC die. The passivation layer262is disposed over the passivation layer260and the aluminum pads264. Passivation layers260and262may be formed of oxides, nitrides, and combinations thereof, and may be formed of the same or different materials.

A trench261is provided in the passivation layer262between the first and the second sub seal ring regions. Another trench263is provided in the passivation layer262between the scribe line and the second sub seal ring region. In an embodiment, each of the trenches261and263is formed into a shape of a ring surrounding the circuit region. An advantageous feature of the dual trenches261,263is that if a crack occurs in the scribe line during dicing, the crack will be stopped by the trench263. Even if the crack propagates across the trench263, if at all, the stress of the crack is substantially reduced by the trench261, and the seal ring242will effectively prevent any further propagation of the crack and protects the main seal ring240from damages. In an embodiment, each of the trenches261,263is designed to have a width about 1.5 microns to about 2 microns to effectuate the crack prevention function discussed above yet leaving enough passivation layer262to cover and protect the aluminum pads264. The nested seal rings246,244,242,240and the dual trenches263,261jointly ensure the operational reliability of the seal ring structure200. In the present embodiment, the device100further includes a layer266that is disposed over the passivation layer262and extends in the assembly isolation region and the first sub seal ring region. In an embodiment, the layer266includes a material such as organic polyimide and provides stress buffer for protecting the circuit die after package assembly. The layer266is optional and can be omitted from the device100in an alternative embodiment.

FIG. 3illustrates a top plan view of the device100in the seal ring region and in the assembly isolation region, in portion, in the region “B” ofFIG. 1according to an embodiment. Referring toFIG. 3, in the illustrated embodiment, each metal plug214is formed into a rectangular structure from the top view. In an embodiment, each metal plug214is formed as a continuous and closed structure (i.e., a ring) that surrounds the area occupied by the circuit elements150, such as shown inFIG. 4. In such embodiment, the metal plug214is also referred to as a continuous metal ring214(or simply a metal ring214). In another embodiment, each metal plug214is formed as an elongated segment and a line of metal plugs214extend along the edges of the area occupied by the circuit elements150and form a segmented ring, such as shown inFIG. 5. In such embodiments, the line of metal plugs214are also referred to as a segmented metal ring214. In the embodiments shown inFIGS. 3, 4, and 5, the dummy gates208are formed as rectangular structures and are disposed between two metal rings214(FIG. 4) or two segmented metal rings214(FIG. 5) and are distributed substantially evenly along the edges of the area occupied by the circuit elements150. For simplicity,FIG. 4illustrates two metal rings214with dummy gates208therebetween and omits other metal rings and other dummy gates. Similarly,FIG. 5illustrates two segmented metal rings214with dummy gates208therebetween and omits other metal rings and other dummy gates. In the embodiment illustrated inFIG. 3, the metal vias215are formed into the same shape (from the top view) as the metal plugs214that the metal vias215are disposed on. In other words, when the metal plug214is a continuous metal ring, the metal via215disposed thereon is also a continuous metal ring, and when the metal plug214is a segment of a segmented metal ring, the metal via215disposed thereon is also a segment of a segmented metal ring. The metal vias215inFIG. 3are also referred to as via bars215(i.e., bar shaped). In the assembly isolation, the metal plugs214′ and the dummy gates208′ are formed into elongated segments. They may be distributed substantially evenly along the edges of the area occupied by the circuit elements150, such as the distribution of the dummy gates208inFIGS. 4 and 5. In the embodiment illustrated inFIG. 3, the device100does not include vias disposed on the dummy gates208,208′ and the metal plugs214′. In other words, the dummy gates208,208′ and the metal plugs214′ are isolated from the connection structures directly above. In such embodiment, the dummy gates208,208′ and the metal plugs214′ are designed to provide good pattern density and good topography for forming the metal plugs214.

In the embodiment illustrated inFIG. 3, The metal plugs214and the dummy gates208are arranged in an alternating manner along the “x” direction in the seal ring region. Each metal plug214has a width w3, each dummy gate208has a width w1, each metal via215has a width w2, the distance between an edge of the dummy gate208and an adjacent edge of the metal plug214is d1, the distance between two edges of adjacent metal plugs214is d2. The dimensions w1, w2, w3, d1, and d2are measured along the “x” direction. Further, each dummy gate208has a length L1, and two adjacent dummy gates208are spaced by a distance d3, both along the “y” direction. In an embodiment, the width w1is about twice of the width w3. In an example, the width w1may be in a range of 180 nm to about 220 nm, and the width w3may be in a range of 90 nm to about 110 nm. The distance d1may be about the same as the width w3. The distance d3may be about the same as the width w1. The length L1may be about 3 times of the width w1. Further, the width w2may be about 30% to about 45% of the width w3. In the assembly isolation, the dummy gates208′ and the metal plugs214′ are also arranged in an alternating manner along the “x” direction. In a first region labeled as having a width w4, each dummy gate208′ has a width w6, each metal plug214′ has a width w7, each dummy gate208′ and the adjacent metal plug214′ is spaced by a distance d5, and the dummy gate208′ is spaced from the nearest metal plug214in the seal ring region by a distance d4. In an embodiment, the distance d4may be in a range of about 250 nm to about 300 nm. In a second region labeled as having a width w5, each dummy gate208′ has a width w8, each metal plug214′ has a width w9, each dummy gate208′ and the adjacent metal plug214′ is spaced by a distance d6, and the dummy gate208′ is spaced from the circuit region by a distance d7. In an embodiment, the distance d7may be in a range of about 250 nm to about 300 nm. In an embodiment, the width w4is greater than the width w5, but the features in the second region (w5) are wider and spaced from each other further than the features in the first region (w4). For example, the width w4may be in a range of about 3 microns to about 4 microns, the width w5may be in a range of about 1.8 microns to about 2.2 microns, the width w6may be in a range of about 5 nm to 8 nm, the width w7is about 15 nm to about 25 nm, the distance d5is about 10 nm to 16 nm, the width w8is about 32 nm to 40 nm, the width w9is about 25 nm to about 35 nm, and the distance d6is about 20 nm to about 30 nm.

FIG. 6illustrates a cross-sectional view of the metal plug214according to an embodiment of the present disclosure. Referring toFIG. 6, the metal plug214is disposed in a trench where the bottom of the trench is a silicide layer203and sidewalls of the trench are formed of a dielectric layer228. The silicide layer203is formed over the substrate202. In an embodiment, the silicide layer203is formed over a P+or N+doped region of the substrate202. The interlayer210(having dielectric layers212,216, and218) is provided over the substrate202and over outer sidewalls of the dielectric layer228. The silicide layer203may include titanium silicide (TiSi), nickel silicide (NiSi), tungsten silicide (WSi), nickel-platinum silicide (NiPtSi), nickel-platinum-germanium silicide (NiPtGeSi), nickel-germanium silicide (NiGeSi), ytterbium silicide (YbSi), platinum silicide (PtSi), iridium silicide (IrSi), erbium silicide (ErSi), cobalt silicide (CoSi), or other suitable compounds. In an embodiment, the dielectric layer212includes silicon oxide, the dielectric layer216includes silicon nitride, the dielectric layer218includes silicon oxide such as plasma enhanced oxide (PEOX), and the dielectric layer228includes silicon carbonitride (SiCN). The dielectric layers212,216,218, and228may include other dielectric materials in alternative embodiments.

The metal plug214includes a conductive adhesion promoter230, a conductive barrier layer232over the conductive adhesion promoter230, and a metal core (or metal fill layer)234over the conductive barrier layer232and filling in the remaining space of the trench. The conductive barrier layer232functions to prevent metal materials of the metal core234from diffusing into the dielectric layers adjacent the metal plug214. The conductive barrier layer232may include titanium (Ti), tantalum (Ta), or a conductive nitride such as titanium nitride (TiN), titanium aluminum nitride (TiAlN), tungsten nitride (WN), tantalum nitride (TaN), or combinations thereof, and may be formed by CVD, PVD, ALD, and/or other suitable processes. In an embodiment, the conductive adhesion promoter230includes chromium, molybdenum, or other suitable material. In some embodiments, the conductive adhesion promoter230is omitted in the metal plug214. The metal core234may include tungsten (W), cobalt (Co), molybdenum (Mo), ruthenium (Ru), or other metals, and may be formed by CVD, PVD, ALD, plating, or other suitable processes. In the depicted embodiment, the metal plug214includes three sections214a,214b, and214c. The section214bis wider than the section214a, and the section214cis wider than the section214b. This results in a first step transitioning from the section214ato the section214band a second step transitioning from the section214bto the section214c. The metal plug214may include more than two steps in alternative embodiments. Having such multi-step profile improves the metal filling quality of the metal plug214and increases the adhesion between the metal plug214and the substrate202and the interlayer210. In the depicted embodiment, the conductive adhesion promoter230extends along the sidewalls of the lower sections214aand214b, but not the upper section214c. In other words, the section214cis disposed above the conductive adhesion promoter230. In an alternative embodiment, the conductive adhesion promoter230extends along the sidewalls of all three sections214a,214b, and214c. In an embodiment, the metal plug214′ is constructed in the same way as the metal plug214.

FIG. 7illustrates a top plan view of the device100in the seal ring region and in the assembly isolation region, in portion, in the region “B” ofFIG. 1according to an alternative embodiment. The metal plugs214and214′, the metal vias215, and the dummy gates208′ of this embodiment are configured similar to or substantially the same as the embodiment shown inFIG. 3. Unlike the embodiment shown inFIG. 3, the dummy gates208in this embodiment are formed into rings or segmented rings. The dummy gates208are formed with dimensions (widths and lengths) similar to the metal plugs214. Further, the device100includes the vias209disposed over the dummy gates208and connecting the dummy gates208to the connection structure250(seeFIG. 2). In an embodiment, the vias209are formed into the same shape and include the same material as the metal vias215(both are via bars). The dummy gates208and the metal plugs214are substantially evenly distributed in the seal ring region. In this embodiment, the device100does not include vias disposed over the dummy gates208′ and the metal plugs214′.

FIG. 8illustrates a top plan view of the device100in the seal ring region and in the assembly isolation region, in portion, in the region “B” ofFIG. 1according to an alternative embodiment. The metal plugs214and214′, and the dummy gates208and208′ of this embodiment are configured similar to or substantially the same as the embodiment shown inFIG. 7. Unlike the embodiment shown inFIG. 7, the vias215and209are formed as discrete round vias. In an embodiment, the round vias215and209each has a diameter in a range about 20 nm to about 50 nm. The round vias215and209are distributed substantially evenly along the metal plugs214and the dummy gates208, respectively. In this embodiment, the device100does not include vias disposed over the dummy gates208′ and the metal plugs214′.

FIG. 9illustrates a top plan view of the device100in the seal ring region and in the assembly isolation region, in portion, in the region “B” ofFIG. 1according to an alternative embodiment. The seal ring region (including the metal plugs214, the dummy gates208, and the vias215and209) of this embodiment are configured similar to or substantially the same as the embodiment shown inFIG. 7. The assembly isolation of this embodiment is configured differently than the embodiment shown inFIG. 7. In this embodiment, the dummy gates208′ and the metal plugs214′ are configured similar to or substantially the same as the dummy gates208and the metal plugs214(in terms widths, spacing, overall shape, and so on), respectively. Further, the device100in this embodiment includes round vias209′ disposed on the dummy gates208′ and round vias215′ disposed on the metal plugs214′. Even though not shown, the vias209′ and215′ connect the dummy gates208′ and the metal plugs214′ to dummy vias and dummy metal lines in the connection structure250′ in the assembly isolation.

FIG. 10illustrates a top plan view of the device100in the seal ring region and in the assembly isolation region, in portion, in the region “B” ofFIG. 1according to an alternative embodiment. The assembly isolation (including the metal plugs214′, the dummy gates208′, and the vias215′ and209′) of this embodiment are configured similar to or substantially the same as the embodiment shown inFIG. 9. The dummy gates208and the metal plugs214in the seal ring region are also configured similar to or substantially the same as the embodiment shown inFIG. 9. Unlike the embodiments shown inFIG. 9, the vias209are formed into the same shape (from top view) as the dummy gates208(i.e., in the shape of a closed ring or a segmented ring), while the vias215are formed into round vias.

FIG. 11illustrates a top plan view of the device100in the seal ring region and in the assembly isolation region, in portion, in the region “B” ofFIG. 1according to an alternative embodiment. The dummy gates208,208′ and the metal plugs214,214′ of this embodiment are configured similar to or substantially the same as the embodiment shown inFIG. 3. Unlike the embodiment shown inFIG. 3, the vias215of this embodiment are formed into round vias rather than a bar shape as inFIG. 3. In this embodiment, the device100does not include vias disposed over the dummy gates208,208′ and the metal plugs214′. The various embodiments shown inFIGS. 3, 7, 8, 9, 10, and11provide good pattern density and topography for forming the metal plugs214with good uniformity.

FIG. 12illustrates a flow chart of a method500for forming the metal plug214, according to an embodiment of the present disclosure. Additional processing is contemplated by the present disclosure. Additional operations can be provided before, during, and after method500, and some of the operations described can be moved, replaced, or eliminated for additional embodiments of method500.

At operation502, the method500(FIG. 12) etches a trench313into the interlayer210and the substrate202, such as shown inFIG. 13. The trench313has a width w13at the bottom section of the trench and has a depth d13. Operation502may use photolithography to form an etch mask over the interlayer210and then etch the interlayer210and the substrate202through the etch mask to form the trench313. The photolithography may use EUV lithography, DUV lithography, immersion lithography, or other lithography. The etching may include dry etching, wet etching, reactive ion etching (RIE), and/or other suitable processes. For example, a dry etching process may implement an oxygen-containing gas, a fluorine-containing gas (e.g., CF4, SF6, CH2F2, CHF3, and/or C2F6), a chlorine-containing gas (e.g., Cl2, CHCl3, CCl4, and/or BCl3), a bromine-containing gas (e.g., HBr and/or CHBr3), an iodine-containing gas, other suitable gases and/or plasmas, and/or combinations thereof. For example, a wet etching process may comprise etching in diluted hydrofluoric acid (DHF); potassium hydroxide (KOH) solution; ammonia; a solution containing hydrofluoric acid (HF), nitric acid (HNO3), and/or acetic acid (CH3COOH); or other suitable wet etchant. The trench313may be formed into a closed ring such as the shape of the metal plug214inFIG. 4or a segmented ring such as the shape of the metal plug214inFIG. 5. The operation502may form a plurality of trenches313in the seal ring region and the assembly isolation region.

At operation504, the method500(FIG. 12) etches another trench314into the interlayer210and overlying the trench313, such as shown inFIG. 14. The trench314has a width w14at the bottom section of the trench and has a depth d14, wherein the width w14is greater than the width w13and the depth d14is smaller than the depth d13. Operation504may use photolithography to form an etch mask over the interlayer210and then etch the interlayer210through the etch mask to form the trench314. The photolithography may use EUV lithography, DUV lithography, immersion lithography, or other lithography. The etching may include dry etching, wet etching, reactive ion etching (RIE), and/or other suitable processes. In the present embodiment, etching of the trench314stops at the substrate202.

At operation506, the method500(FIG. 12) etches another trench315into the interlayer210and overlying the trench314, such as shown inFIG. 15. The trench315has a width w15at the bottom section of the trench and has a depth d15, wherein the width w15is greater than the width w14and the depth d15is smaller than the depth d14. Operation506may use photolithography to form an etch mask over the interlayer210and then etch the interlayer210through the etch mask to form the trench315. In the present embodiment, etching of the trench315stops at the dielectric layer212. The photolithography may use EUV lithography, DUV lithography, immersion lithography, or other lithography. The etching may include dry etching, wet etching, reactive ion etching (RIE), and/or other suitable processes. Through the operations502,504, and506, a trench316(having three sections from trenches313,314, and315) is formed into the substrate202and the interlayer210. The trench316has a multi-step profile, with its width increasing step-wise along the “z” direction.

At operation508, the method500(FIG. 12) forms a dielectric liner228over the sidewalls of the interlayer210in the trench316, such as shown inFIG. 16. In an embodiment, the operation508may deposit a dielectric layer using atomic layer deposition (ALD) over the surfaces of the interlayer210and the substrate202, and then etches the dielectric layer using anisotropic etching to remove it from the top surface of the interlayer210and the substrate202. The portion of the dielectric layer remaining on the sidewalls of the interlayer210becomes the dielectric liner228.

At operation510, the method500(FIG. 12) forms the silicide feature203, such as shown inFIG. 6. In an embodiment, the operation510includes depositing one or more metals into the trench316, performing an annealing process to the device100to cause reaction between the one or more metals and the substrate202to produce the silicide features203, and removing un-reacted portions of the one or more metals, leaving the silicide features203in the trench316. The one or more metals may include titanium (Ti), tantalum (Ta), tungsten (W), nickel (Ni), platinum (Pt), ytterbium (Yb), iridium (Ir), erbium (Er), cobalt (Co), or a combination thereof (e.g., an alloy of two or more metals) and may be deposited using CVD, PVD, ALD, or other suitable methods. The silicide features203may include titanium silicide (TiSi), nickel silicide (NiSi), tungsten silicide (WSi), nickel-platinum silicide (NiPtSi), nickel-platinum-germanium silicide (NiPtGeSi), nickel-germanium silicide (NiGeSi), ytterbium silicide (YbSi), platinum silicide (PtSi), iridium silicide (IrSi), erbium silicide (ErSi), cobalt silicide (CoSi), or other suitable compounds.

At operation512, the method500(FIG. 12) forms the conductive adhesion promoter230and the conductive barrier layer232in the trench316, such as shown inFIG. 6. In an embodiment, each of the conductive adhesion promoter230and the conductive barrier layer232is deposited to have a substantially uniform thickness, and the remaining space of the trench316still has a multi-step profile. At operation514, the method500(FIG. 12) deposits the metal core234into the remaining space of the trench316. The conductive barrier layer232may include titanium (Ti), tantalum (Ta), or a conductive nitride such as titanium nitride (TiN), titanium aluminum nitride (TiAlN), tungsten nitride (WN), tantalum nitride (TaN), or combinations thereof, and may be formed by CVD, PVD, ALD, and/or other suitable processes. In an embodiment, the conductive adhesion promoter230includes chromium, molybdenum, or other suitable material, and may be deposited using CVD, PVD, ALD, and/or other suitable processes. The metal core234may include tungsten (W), cobalt (Co), molybdenum (Mo), ruthenium (Ru), or other metals, and may be formed by CVD, PVD, ALD, plating, or other suitable processes. At operation516, the method500(FIG. 12) performs further fabrications to the device100. For example, the method500may perform a CMP process to remove excessive materials of the metal plugs214, form the vias215, form the dielectric layers253,255and the connection structure250.

Although not intended to be limiting, embodiments of the present disclosure provide one or more of the following advantages. For example, embodiments of the present disclosure provide various seal ring structures having a connection structure and one or more metal plugs connecting the connection structure to a substrate. The metal plug has a multi-step profile, which improves the filling of the metal plug and improves the adhesion between the metal plug and the substrate. This improves the ability of the seal ring to withstand stress during dicing. In embodiments, the seal ring structure further includes dummy gates that are alternately arranged with the metal plugs to substantially reduce or eliminate dishing in the seal ring region during chemical mechanical planarization (CMP) processing. In some embodiments, such metal plugs and dummy gates are also formed in an assembly isolation region, thereby balancing the topography loading during various processes, including CMP. Further, in some embodiments, multiple (such as four) seal rings are formed in the seal ring region to further improve the seal ring structure's operational reliability. Embodiments of the present disclosure can be readily integrated into existing semiconductor manufacturing processes.

In one example aspect, the present disclosure is directed to a semiconductor structure. The semiconductor structure includes a substrate having a seal ring region and a circuit region; one or more dielectric layers disposed on the substrate; a connection structure disposed in the one or more dielectric layers in the seal ring region, wherein the connection structure includes a stack of metal layers and metal vias connecting the stack of metal layers; and a metal plug disposed between the substrate and the connection structure in the seal ring region, wherein the metal plug has a multi-step profile in a cross-sectional view.

In an embodiment of the semiconductor structure, the metal plug includes a ring structure surrounding the circuit region from a top view. In another embodiment, the metal plug includes multiple segments that surround the circuit region from a top view.

In an embodiment, the semiconductor structure further includes a via bar disposed on the metal plug and connecting the metal plug to the connection structure. In another embodiment, the semiconductor structure further includes multiple vias disposed on the metal plug and connecting the metal plug to the connection structure.

In an embodiment, the semiconductor structure further includes a gate structure adjacent to the metal plug and disposed between the substrate and the connection structure in the seal ring region. In a further embodiment, the semiconductor structure includes a via bar disposed on the gate structure and connecting the gate structure to the connection structure.

In an embodiment of the semiconductor structure, the metal plug includes a conductive adhesion promoter in direct contact with a first dielectric layer on sidewalls of the metal plug, wherein a top portion of the metal plug extends higher than the conductive adhesion promoter.

In some embodiments, the semiconductor structure further includes a silicide layer between the substrate and the metal plug, wherein the metal plug is disposed on the silicide layer. In some embodiments where the substrate further includes an assembly isolation region between the seal ring region and the circuit region, the semiconductor structure further includes dummy vias disposed in the one or more dielectric layers in the assembly isolation region and a second metal plug disposed between the substrate and the dummy vias in the assembly isolation region. In a further embodiment, the second metal plug is isolated from the dummy vias.

In another example aspect, the present disclosure is directed to a semiconductor structure. The semiconductor structure includes a substrate having a seal ring region surrounding a circuit region; dielectric layers disposed on the substrate; and a connection structure disposed in the dielectric layers in the seal ring region, wherein the connection structure includes metal layers in a stacking configuration. The semiconductor structure further includes first metal plugs disposed between the substrate and the connection structure in the seal ring region, wherein each of the first metal plugs includes a cobalt core and a conductive barrier layer surrounding the cobalt core, wherein the cobalt core has at least two steps in a cross-sectional view. The semiconductor structure further includes first metal vias disposed on the first metal plugs and connecting the first metal plugs to the connection structure.

In an embodiment of the semiconductor structure, at least one of the first metal plugs includes a ring structure that surrounds the circuit region from a top view. In another embodiment, the semiconductor structure further includes first gate structures between the substrate and the connection structure in the seal ring region, wherein the first metal plugs and the first gate structures are disposed in an alternating manner. In a further embodiment where the substrate further has an assembly isolation region between the seal ring region and the circuit region, the semiconductor structure further includes second metal plugs and second gate structures over the substrate in the assembly isolation region. In yet another embodiment, at least one of the first metal vias is configured as a ring structure surrounding the circuit region.

In yet another example aspect, the present disclosure is directed to a semiconductor structure. The semiconductor structure includes a substrate having a first seal ring region and a second seal ring region surrounding a circuit region; dielectric layers disposed on the substrate; and multiple seal rings configured in each of the first and the second seal ring regions. Each of the seal rings includes a connection structure disposed in the dielectric layers and having a stack of interconnected metal layers; a metal plug disposed between the substrate and the connection structure, wherein the metal plug includes a metal core that has at least three sections and the three sections become wider as they are further away from the substrate; and a metal via disposed on the metal plug and connecting the metal plug to the connection structure.

In some embodiments, the metal plug includes a conductive adhesion promoter between the metal core and a first dielectric layer surrounding the metal plug, wherein a topmost section of the three sections is above the conductive adhesion promoter. In some embodiments, the metal core includes cobalt. In some embodiments, the metal plug is configured as a ring structure surrounding the circuit region.