Level conversion circuit and serial/parallel conversion circuit with level conversion function

A MOS capacitor receiving a clock signal complementary to a sampling clock signal is provided at an input of a clocked inverter that is activated after sampling an input signal to perform level conversion. A charge pump operation of the MOS capacitor is performed in parallel with the activation of the clocked inverter. The power consumption of and the area occupied by a level conversion circuit converting a voltage amplitude of the input signal are reduced without deteriorating a high-speed operating characteristics.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a level conversion circuit using insulated gate field effect transistors (MOS transistors). In particular, the present invention relates to a level shift circuit having a latch function and used for display devices formed using, for example, liquid-crystal elements or organic electroluminescence (EL) elements. More specifically, the present invention relates to a circuit configuration for latching and level-shifting a pixel data signal applied to a display pixel.

2. Description of the Background Art

In a display device using liquid-crystal elements or organic EL (electroluminescence) elements as display pixel elements, a level conversion circuit is employed for enlarging a signal amplitude. For example, in order to accurately drive the display pixel elements in accordance with a display signal, for achieving gradational display, the amplitude of an image data signal is enlarged to generate the display signal and supply the display signal to the pixel element.

For such a display device, it is generally required to reduce power consumption for preventing heat generation, and to reduce the power consumption in an application such as mobile equipment having a battery as a power source. Prior art document 1 (Japanese Patent Laying-Open No. 2003-115758) discloses a configuration of a level conversion circuit aiming to reduce power consumption.

In the configuration disclosed in the prior art document 1, an input signal is held in a first capacitance element in accordance with a sampling pulse. After this sampling is completed, a MOS drive stage having level conversion function is driven in accordance with the voltage held in the first capacitance element. In accordance with an output signal of the MOS drive stage, a second capacitance element is charged to generate a level-converted signal. With the configuration disclosed in the prior art document 1, it is intended to perform level conversion on the input signal with a smaller number of elements, in addition to reduction in power consumption.

Prior art document 2 (Japanese Patent Laying-Open No. 2002-358055) also discloses a level conversion circuit with an intention to reduce power consumption. In the level conversion circuit disclosed in the prior art document 2, a current-mirror type input buffer circuit for comparing an input signal with a reference voltage is activated for an activation period of a vertical scan start instruction signal, and an output signal of the current-mirror type input buffer circuit is latched by a latch circuit having level conversion function when the vertical scan start instruction signal is inactivated. The current-mirror type input buffer circuit is operated for a minimum necessary period of time, thereafter the output signal thereof is latched by the latch circuit and level conversion is performed by this latch circuit so as to reduce power consumption.

Moreover, prior art document 3 (Japanese Patent Laying-Open No. 2001-320268) discloses a level conversion circuit with the purpose of achieving a high-speed operation in addition to reduction of power consumption. In a configuration disclosed in the prior art document 3, an amplitude-limited control signal is generated in accordance with an input clock signal, and an output drive stage is driven in accordance with the amplitude-limited control signal. In limiting the amplitude, threshold voltage drop of a MOS transistor (insulated gate field effect transistor) is utilized, the output drive stage is constituted of a CMOS inverter, and one of the drive transistors is set to a strongly-on state while the other is set to a weakly-on state. The degree of the on state of the output drive transistors is simply controlled to achieve high-speed operation. Further, a transition period of the potential level on an output node is shortened to reduce the period in which a through current flows and thereby to reduce power consumption.

In addition, the prior art document 4 (Japanese Patent Laying-Open No. 2002-251174) discloses a configuration with the purpose of reducing power consumption of a level conversion circuit for enlarging a signal amplitude in an image display device. In the configuration disclosed in the prior art document 4, an output transistor has a gate clamped by diode-connected a MOS transistor, and further supplied with an input signal via a capacitance element. The gate potential of this output drive transistor is varied through capacitive coupling by the capacitance element and the output drive transistor is driven to an on/off state at a high speed, so that the through current is reduced and power consumption is reduced.

In a display device such as liquid-crystal display device, a thin-film transistor (TFT) is used as a MOS transistor. In this case, in order to prevent deterioration in characteristics of display pixel elements, a low-temperature polysilicon TFT is employed. Such a low-temperature polysilicon TFT is merely subject to annealing or heat treatment at a low temperature. Thus, as compared with a MOS transistor using single-crystal silicon, the crystal quality of the low-temperature polysilicon TFT is inferior. Therefore, in such TFTs, threshold voltage varies to a greater degree for different transistors and the channel resistance (ON resistance) in a conductive state is large.

In the configuration disclosed in the prior art document 1, in a level-converting operation, the output drive transistor is driven, in accordance with the input signal of small amplitude that is held in the first capacitance element, to discharge the voltage held in the second capacitance element. Therefore, the current drivability of the output drive transistor is small, and a level-converted signal of a large amplitude that is held in the second capacitance element cannot be discharged at a high speed, resulting in a problem that a high-speed operation is not ensured.

In the configuration disclosed in the prior art document 2, the current-mirror type buffer circuit is used for identifying the voltage level of the input signal. The input signal is compared with the reference voltage to generate the internal signal according to the result of this comparison, and the internal signal is latched by the latch circuit. Accordingly, the input buffer circuit has a large number of transistor elements, resulting in a problem that the occupied area cannot be reduced. In addition, if the transistor elements have greatly-varied threshold voltages, offset in a comparison stage of the current-mirror type input buffer circuit cannot be compensated for, resulting in a problem that an accurate input signal cannot be generated.

In the configuration disclosed in the prior art document 3, the gate potential of the transistor of the output drive stage for performing level conversion is level-shifted by the diode-connected MOS transistor. The degree of the ON state of the output drive transistors is changed in accordance with the input signal. Accordingly, in the output drive stage, both of charging and discharging drive transistors are in an ON state, resulting in a problem that a through current flows all the time.

In the configuration disclosed in the prior art document 4, the gate potential of the level-converting output drive transistor is clamped by the diode-connected MOS transistor. Through the capacitive coupling of the input signal, the gate potential of the drive transistors is changed. Accordingly, it is required to provide capacitance elements respectively for the high-side drive transistor and the low-side transistor on the node receiving the input signal, resulting in a problem that the load of the input signal increases. Further, the prior art document 4 disclosed a further configuration for driving an internal output node through capacitive coupling of an input signal. Specifically, between the gate of a first drive transistor and the internal output node, a capacitance element receiving the input signal is connected. The internal output node is further coupled to the input signal via a second drive transistor in accordance with an inverted signal of the input signal. Thus, if a skew occurs between the complementary input signals, the signal on the internal output node is coupled via the second drive transistor to the input signal, resulting in a problem that the internal output node cannot sufficiently charged and thus an accurately level-converted signal cannot be generated.

SUMMARY OF THE INVENTION

An object of the present invention is to provide a level conversion circuit capable of converting a signal of small voltage amplitude into a signal of large voltage amplitude at a high speed and with low power consumption as well as a serial/parallel level conversion circuit using the level conversion circuit.

A level conversion circuit according to a first aspect of the present invention includes: a first insulated gate field effect transistor of a first conductivity type for transferring an input signal applied to an input node to a first internal node according to a first clock signal from a first clock input node; a MOS capacitance element formed of an insulated gate field effect transistor and connected between a second clock input node receiving a second clock signal and the first internal node for selectively forming a capacitance according to a potential difference between the first internal node and the second clock input node; and a clocked inverter activated, when the first insulated gate field effect transistor is non-conductive, according to one of the first clock signal and a clock signal corresponding to the first clock signal and the second clock signal, for inverting a potential on the first internal node to generate, on a second internal node, a signal having an amplitude larger than an amplitude of the input signal.

A level conversion circuit according to a second aspect of the present invention includes: a first insulated gate field effect transistor of a first conductivity type for transferring an input signal to a first internal node according to a first clock signal from a first clock input node; a second insulated gate field effect transistor of the first conductivity type for transmitting a second clock signal applied to a second clock input node to a second internal node according to a voltage on the first internal node; a low drive circuit for driving the second internal node to a voltage level of a low-side power supply node according to a clock signal in phase with the first clock signal on the first clock input node; and a clocked inverter for driving a third internal node according to a signal potential on the second internal node when activated in accordance with clock signals in phase with the clock signals on the first clock input node and the second clock input node.

A level conversion circuit according to a third aspect of the present invention includes: a clocked inverter enabled in response to a first clock signal, and inverting and transferring, when enabled, a signal on a first node onto a second node; a first insulated gate field effect transistor made conductive when said clocked inverter is inactive, and transferring, when made conductive, an input signal onto the first node; and a MOS capacitance element formed of an insulated gate field effect transistor and connected between said first node and a third node, for selectively performing a charge pump operation in response to the first clock signal when said clocked inverter is enabled.

A level conversion circuit according to a fourth aspect of the present invention includes: a first insulated gate field effect transistor made conductive in response to a first clock signal and transferring, when made conductive, an input signal onto a first node; a second insulated gate field effect transistor selectively made conductive according to a signal on said first node and transferring, when made conductive, a second clock signal onto a second node; a third insulated gate field effect transistor selectively made conductive according to a third clock signal complementary to said second clock signal and transferring, when made conductive, the second clock signal onto said second node; and a clocked inverter made active in response to the second and third clock signals when said third insulated gate field effect transistor is non-conductive and inverting and transferring the signal on the second node onto a subsequent node.

A serial/parallel conversion circuit with level conversion function according to a fifth aspect of the present invention includes first and second level conversion circuits operating complementarily to each other and a transfer circuit for taking in the output signals of the first and second level conversion circuits to output the taken-in output signals in parallel. The first level conversion circuit includes: a first insulated gate field effect transistor of a first conductivity type for transferring an input signal applied to an input node to a first internal node according to a clock signal from a first clock input node receiving the clock signal corresponding to a first clock signal; a MOS capacitance element connected between a second clock input node receiving a second clock signal and the first internal node for selectively forming a capacitance according to a potential difference between the first internal node and the second clock input node; and a clocked inverter selectively activated, when the first insulated gate field effect transistor is in a non-conductive state, according to the first clock signal and the second clock signal, for inverting a potential on the first internal node to generate, on a second internal node, a signal having an amplitude larger than an amplitude of the input signal.

The second level conversion circuit operates complementarily to the first level conversion circuit according to the first and second clock signals, has the same configuration as the first level conversion circuit, and operates in parallel with the first level conversion circuit to level-convert the input signal. The transfer circuit performs the taking-in and transfer operations according to the clock signal corresponding to the first clock signal and the second clock signals. The first clock signal and the second clock signal each have a cycle twice as long as a cycle at which the input signal is applied.

A serial/parallel conversion circuit with level conversion function according to a sixth aspect of the present invention includes a first and second level conversion circuits operating complementarily to each other and having the same configuration and a transfer circuit taking in respective output signals of the first and second level conversion circuits to output the taken-in signals in parallel. The first level conversion circuit includes: a first insulated gate field effect transistor of a first conductivity type for transferring an input signal to a first internal node according to a first clock signal from a first clock input node; a second insulated gate field effect transistor of the first conductivity type for transmitting a second clock signal applied to a second clock input node to a second internal node according to a voltage on the first internal node; a low drive circuit driving the second internal node to a voltage level on a low-side power supply node according to a clock signal in phase with the clock signal on the first clock input node; and a clocked inverter selectively activated according to clock signals corresponding to the clock signals on the first clock input node and the second clock input node for driving a third internal node according to the signal on the second internal node. To the third internal node, the level-converted signal is output. The first and second level conversion circuits operate in parallel to level-convert the input signal. The transfer circuit performs the take-in and transfer operation according to the first and second clock signals. The first clock signal and the second clock signal each have a cycle twice as long as a cycle at which the input signal is applied.

A serial/parallel conversion circuit with level conversion function according to a seventh aspect of the present invention includes a plurality of level conversion circuits provided in parallel and having a common configuration. The level conversion circuits each include: a first insulated gate field effect transistor of a first conductivity type for transferring an input signal applied to an input node to an internal node according to a first logic level of a clock signal from a first clock input node; a MOS capacitance element connected between the internal node and a second clock input node receiving a clock signal complementary to the clock signal on the first clock input node for selectively forming a capacitance according to a potential difference between the internal node and the second clock input node; and a clocked inverter selectively activated when the first insulated gate field effect transistor is in a non-conductive state, according to the clock signal on the first clock input node and a clock signal complementary to the clock signal on the first clock input node, for inverting a potential on the internal node to generate, on a second internal node, a signal having an amplitude larger than an amplitude of the input signal.

The serial/parallel conversion circuit with level conversion function according to the seventh aspect of the present invention further includes a plurality of output latch circuits, provided corresponding to the respective level conversion circuits, each for latching an output signal of a corresponding level conversion circuit according to a common latch instruction signal; and a clock supply circuit supplying clock signals to respective first clock input nodes of the level conversion circuits, such that the first logic level period of the clock signal at the first clock input node is different from others.

A serial/parallel conversion circuit with level conversion function according to an eighth aspect of the present invention includes a plurality of level conversion circuits provided commonly to an input signal and having a common configuration. The level conversion circuits each include: a first insulated gate field effect transistor of a first conductivity type for transferring the input signal to a first internal node according to a first logic level of a first clock signal from a first clock input node; a second insulated gate field effect transistor of the first conductivity type for transmitting to a second internal node a second clock signal applied to a second clock input node according to a voltage on the first internal node; a low drive circuit for driving the second internal node to a voltage level of a low-side power supply node according to a clock signal in phase with the first clock signal on the first clock input node; and a clocked inverter enabled according to clock signals corresponding to the clock signals on the first and the second clock input nodes, for driving a third internal node according to a signal on the second internal node.

The serial/parallel conversion circuit with level conversion function according to the eighth aspect of the present invention further includes: a plurality of output latch circuits, provided corresponding to the respective level conversion circuits, each for latching an output signal of a corresponding level conversion circuit according to a common latch instruction signal; and a clock supply circuit supplying the clock signals to the respective first clock input nodes of the level conversion circuits such that the first clock signals at the first and second clock nodes of the respective level conversion circuits are different in first logic level period of each clock signal from each other.

A serial/parallel conversion circuit with level conversion function according to a ninth aspect of the present invention includes a plurality of level conversion circuits having the same configuration and coupled commonly to an input node. The level conversion circuits each include: a first insulated gate field effect transistor of a first conductivity type for transferring an input signal applied to the input node to a first internal node according to a first clock signal from a first clock input node; a MOS capacitance element connected between a second clock input node and the first internal node for selectively forming a capacitance according to a potential difference between the first internal node and the second clock input node; and a clocked inverter selectively activated when the first insulated gate field effect transistor is in a non-conductive state, according to the second clock signal from the second clock input node and a clock signal complementary to the second clock signal on the second clock input node, for inverting a potential on the first internal node to generate, on a second internal node, a signal that has an amplitude larger than an amplitude of the input signal.

The serial/parallel conversion circuit with level conversion function according to the eighth aspect of the present invention further includes: a plurality of latch circuits provided, corresponding to the respective level conversion circuits, each for latching an output signal of a corresponding level conversion circuit according to a common latch instruction signal; and a clock supply circuit for supplying clock signals to the respective second clock input nodes of the level conversion circuits such that the respective clocked inverters are activated in different periods of time from each other. The clock signal applied to the second clock input node of each respective level conversion circuit at a preceding stage in a clock supply sequence is inverted and supplied to the first clock input node of a respective level conversion circuit at a subsequent stage in the clock supply sequence.

A serial/parallel conversion circuit with level conversion function according to a tenth aspect of the present invention includes a plurality of level conversoin circuits provided commonly to an input signal and having a common configuration. The level conversion circuits each include: a first insulated gate field effect transistor of a first conductivity type for transferring the input signal to a first internal node according to a clock signal from a first clock input node; a second insulated gate field effect transistor of the first conductivity type for transmitting a second clock signal applied to a second clock input node to a second internal node according to a voltage on the first internal node; a low-side drive circuit for driving the second internal node to a voltage level of a low-side power supply node according to a third clock signal opposite in phase to the second clock signal on the second clock input node; and a clocked inverter selectively activated according to the second and third clock signals for driving, when activated, a third internal node according to a signal on the second internal node.

The serial/parallel conversion circuit with level conversion function according to the tenth aspect of the present invention further includes: a plurality of output latch circuits, provided corresponding to the respective level conversion circuits, each for latching an output signal of a corresponding level conversion circuit according to a latch instruction signal; and a clock supply circuit supplying clock signals to respective second clock input nodes of the level conversion circuits such that each activation period of the clocked inverter is different from others. The clock signal applied to the second clock input node of the level conversion circuit at each respective preceding stage in a clock supply sequence is inverted and supplied to the first clock input node of the level conversion circuit at a respective subsequent stage.

According to the first aspect of the invention, the input signal is held in the MOS capacitance element. Accordingly, when the input signal is sampled, the MOS capacitance element stops the operation as the capacitance element, to cause the voltage held in the MOS capacitance element to change according to the input signal at a high speed. A high-speed level conversion is thus achieved. Further, according to the charged voltage of the MOS capacitance element, the clocked inverter is driven. Then, the clocked inverter can be driven for only a required period of time to reduce current consumption. Moreover, by applying the clock signal on the second clock input node to the MOS capacitance element, the voltage held therein can be boosted through a charge pump operation. It is thus ensured to drive a clocked inverter at a subsequent stage. The period of time in which through current flows in the clocked inverter can be shortened and accordingly current consumption can be reduced.

According to the second aspect of the invention, the input signal is sampled, the second clock signal is transferred to the clocked inverter at the subsequent stage according to the sampled voltage, and the clocked inverter at the subsequent stage drives the internal node according to the transferred signal. With the second clock signal, the second MOS transistor can be operated as a MOS capacitance element so that the gate potential thereof is increased to rapidly change the potential on the internal output node.

According to the third aspect of the invention, similarly to the first aspect of the invention, the input signal is held at the MOS capacitor and the input signal is boosted through charge pump operation of the MOS capacitor. Thus, the input signal can be sampled and level-converted at high speed. In addition, control of conduction/non-conduction of the first insulated gate field effect transistor and the control of charge pump operation by MOS capacitor can be made by separate clock signals, the timing for sampling the input signal can be optimized and thus, level-conversion can be performed accurately with reduced current consumption.

According to the fourth aspect of the invention, the input signal is sampled according to complementary clock signals and the clock signal is transferred to an input of the clocked inverter in accordance with the taken-in input signal. The clocked inverter is activated in parallel with the clock signal transfer and thus, the input signal can be converted into a signal having an amplitude the same as the clock signal. The input signal merely drives the gate of the insulated gate field effect transistor and the load thereof is very small. As a result, the input signal can be taken in and level-converted at high speed.

According to the fifth aspect of the invention, the level conversion circuit of the first aspect is employed and thus the input signal can be frequency-divided and level-converted at high speed.

According to the sixth aspect of the invention, the level conversion circuits of the third aspect are used in parallel and operate complementarily to each other. Thus, the input signal can be frequency-divided and level-converted at high speed.

According to the seventh aspect of the invention, a plurality of level conversion circuits of the first aspect are provided. Respective sampling periods of the level conversoin circuits are made different so that signals applied serially to the input node can be level-converted and converted into parallel signals at high speed.

According to the seventh aspect of the invention, a plurality of level conversion circuits of the fourth aspect are employed. Respective input signals are sampled at the timings different from each other. The input signals applied serially can thus be level-converted to generate parallel signals at high speed.

According to the ninth aspect of the invention, a plurality of level conversion circuits of the first aspect are employed. Further, after the sampling by the level conversion circuit at the preceding stage is completed, the sampling operation by the level conversoin circuit at the subsequent stage is activated. Then, accurate and fast level conversion is achieved and signals applied serially can be converted into parallel signals and output as parallel signals.

According to the tenth aspect of the invention, a plurality of level conversion circuits of the second aspect are provided and the level conversoin circuits perform the sampling operations at different timings from each other in accordance with the sampling clock signals. Further, after the sampling operation by the level conversion circuit at the preceding stage is completed, the sampling operation by the level conversion circuit at the subsequent stage is carried out. Thus, input signals applied serially can accurately be level-converted to generate parallel signals. Moreover, only a selected level conversoin circuit is coupled to the input signal so that the load of the input signal is reduced and accordingly current consumption can be reduced.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

First Embodiment

FIG. 1shows a configuration of a level conversion circuit according to a first embodiment of the present invention. Referring toFIG. 1, the level conversion circuit includes an N-channel MOS transistor (insulated gate field effect transistor)5transmitting an input signal IN applied to an input node DN5to an internal node DN7according to a clock signal /CLK applied to an input node DN4, a MOS-type capacitance element (hereinafter referred to as MOS capacitor)6coupled to internal node DN7and selectively forming a capacitor according to a clock signal CLK from a clock input node DN3, a clocked inverter CIV selectively activated according to clock signals CLK and /CLK and driving, when activated, an internal output node DN6according to the signal on internal node DN7, and an inverter7and a clocked inverter8that constitute a latch circuit latching a signal voltage on internal output node DN6.

When this level conversion circuit is used in a display device (display panel), input signal IN is a signal applied from an external LSI (Large Scale Integrated circuit chip) such as driver IC and is a signal changing between 0 V and 3 V, for example. Clock signals CLK and /CLK are generated in the display device and change between a reference voltage VSS and a power supply voltage VDD. This voltage VDD has a voltage level higher than an H level (logic high level) VIH of input signal IN, and is used as a power supply voltage of the display device, and is 5 V, for example. Voltage VSS is a reference voltage of voltage measurement basis that is a ground voltage, for example.

Clocked inverter CIV includes P-channel MOS transistors1and2connected in series between a high-side power supply node DN1and internal output node DN6as well as N-channel MOS transistors3and4connected in series between internal output node DN6and a low-side power supply node DN2. To the gate of P-channel MOS transistor1, clock signal /CLK is applied. The gates of MOS transistors2and3are commonly connected to internal node DN7. To the gate of N-channel MOS transistor4, clock signal CLK is applied.

MOS capacitor6is constituted of an N-channel MOS transistor having its gate connected to internal node DN7and its source and drain nodes connected to clock input node DN3. When the voltage level of the gate of MOS capacitor6is higher than the voltage level of the source and drain nodes of MOS capacitor6by at least its threshold voltage, a channel is generated between the source and the drain so that MOS capacitor6serves as a capacitance element. When the difference between the gate voltage and the source/drain voltage of MOS capacitor6is not greater than its threshold voltage, no channel is generated. In this case, a capacitor formed by the overlapping region between the source and drain, and gate electrode merely serves as a capacitor to internal node DN7.

Inverter7inverts a voltage on internal output node DN6to transmit the inverted voltage to an internal node DN8. Clocked inverter8inverts the signal on internal node DN8to transmit the inverted signal to internal output node DN6. Like clocked inverter CIV, these inverter7and clocked inverter8are supplied with the voltages VDD and VSS as operating power supply voltages.

FIG. 2Aspecifically shows a configuration of inverter7shown inFIG. 1. Referring toFIG. 2A, inverter7is comprised of a P-channel MOS transistor PQ1and an N-channel MOS transistor NQ1connected between high-side power supply node DN1and low-side power supply node DN2. In other words, inverter7is constituted of a CMOS inverter receiving voltages VDD and VSS as its operating power supply voltages.

FIG. 2Bspecifically shows a configuration of clocked inverter8shown inFIG. 1. Referring toFIG. 2B, clocked inverter8includes P-channel MOS transistors PQ2and PQ3connected in series between high-side power supply node DN1and the output node as well as N-channel MOS transistors NQ2and NQ3connected in series between the output node and low-side power supply node DN2. To respective gates of MOS transistors PQ2and NQ3, clock signals CLK and /CLK are applied. The gates of MOS transistors PQ3and NQ2are connected together to internal output node DN8shown inFIG. 1.

As shown inFIG. 2B, clocked inverter8operates complementarily to clocked inverter CIV. When clocked inverter CIV is in an output high impedance state, the inverter latch comprised of inverter7and clocked inverter8operates to latch the signal on internal output node DN6. On the contrary, when clocked inverter CIV is activated, clocked inverter8is in an output high impedance state, so that internal output node DN6is released from the latched state and is driven by clocked inverter CIV.

FIG. 3is a signal waveform diagram representing an operation of the level conversion circuit shown inFIG. 1.FIG. 3shows an exemplary operation in which an input signal changes between 3 V and 0 V and this signal with the voltage amplitude of 3 V is converted into a signal changing between 5 V and 0 V. Specifically, H level of 3 V of input signal IN is converted into H level of 5 V to be output to internal output node DN6. As for L level, no level conversion is performed since L level of input signal IN and that of the internal signal (signal on output node DN6) are both 0 V.

It is assumed here that N-channel MOS transistors3to5and the N-channel MOS transistor constituting MOS capacitor6each have a threshold voltage of 2 V and P-channel MOS transistors1and2each have a threshold voltage of-2V. The threshold voltage conditions also hold for the components of inverter7and clocked inverter8.

At time t0, input signal IN is at H level (logic high level), clock signal /CLK is at H level and clock signal CLK is at L level (logic low level). In this state, MOS transistor5is turned on so that H level of input signal IN is transmitted to internal node DN7. At this time, clock signal CLK is at L level. Therefore, the voltage difference between internal node DN7and clock input node DN3is 3 V. The voltage difference between internal node DN7and clock input node DN3is greater than the threshold voltage (2 V) of the MOS transistor constituting MOS capacitor6, so that a channel is formed in MOS capacitor6. Accordingly, a capacitance is formed that corresponds to the gate area of the MOS transistor constituting MOS capacitor6, and H level of input signal IN is held in the capacitance of MOS capacitor6.

Clocked inverter CIV has MOS transistors1and4kept in a turned-off state or inactive state, and thus is in an output high impedance state. Clocked inverter8is in an active state to operate as an inverter and thereby holds the state of internal output node DN6in the preceding cycle. InFIG. 3, a signal of H level is transmitted in the preceding cycle to be held on internal output node DN6. Since internal output node DN6is at H level, internal node DN8is at a ground voltage level or L level.

At time t1, after clock signal /CLK falls to L level, clock signal CLK rises to H level. This change in voltage (5 V) of clock signal CLK is transmitted through charge pump operation of MOS capacitor6to internal node DN7so that the voltage on internal node DN7increases by ΔVH. This amount of voltage change ΔVH is represented by the following equation:
ΔVH=(VCH−VCL)·C6H/(C6H+CST)  (1),
where VCH and VCL respectively represent H level (5 V) and L level (0 V) of clock signals CLK and /CLK, C6H represents a capacitance value of capacitor6, and CST represents a capacitance value of a parasitic capacitance (not shown) on internal node DN7. Thus, (VCH−VCL) represents the voltage amplitude of clock signals CLK and /CLK and equation (1) represents that the electric charges injected by MOS capacitor6to internal node DN7is distributed to MOS capacitor6and to the parasitic capacitance (not shown).

For example, it is assumed that C6H is equal to CST (C6H=CST) in equation (1). Then, equation (1) is represented as:
ΔVH=(VCH−VCL)·(1/2)  (2).

Under this condition, the amount of voltage change ΔVH is 0.5 times as large as the voltage amplitude of clock signal CLK (ΔVH=2.5 V). In this case, the voltage level of internal node DN7is 5.5 V. This voltage level is a voltage level that can cause P-channel MOS transistor2and N-channel MOS transistor3in clocked inverter CIV to be turned off and on, respectively, as in the internal circuit operating on power supply voltage VDD. Thus, clocked inverter CIV can be fully activated to accurately generate a binary signal with an amplitude of 5 V.

According to the voltage level of internal node DN7, the voltage level of internal output node DN6falls to L level and inverter7drives to and holds at H level the internal node DN8. At this time, clocked inverter8is in an inactive state and internal node DN6can be driven at a high speed according to the voltage level of internal node DN7.

At time t2, input signal IN changes from H level to L level. At this time t2, clock signals CLK and /CLK are at H level and L level, respectively, and clocked inverters CIV and8are in an active (enable) state and an inactive (disable) state, respectively. The time duration from time t2to time t3at which clock signal /CLK transitions to H level subsequently is a setup time for taking input signal IN into the level conversion circuit. In this setup period, MOS transistor5is in a turned-off state.

At time t3, clock signal CLK falls to L level so that the voltage level of internal node DN7is also caused to fall by a charge pump operation of the capacitance of MOS capacitor6and the voltage level of internal node DN7falls to 3 V or H level of input signal IN.

After clock signal CLK falls to L level, clock signal /CLK rises to H level. Then, MOS transistor5is turned on, input signal IN is transmitted to internal node DN7, and the voltage level of internal node DN7changes to the voltage level (0 V) equal to L level of input signal IN. At this time, clock signal CLK is at L level, the voltage level of clock input node DN3is the ground voltage level and the voltage levels of internal node DN7and clock input node DN3are equal to each other. Thus, no channel is formed in MOS capacitor6. In this state, the capacitance between internal node DN7and clock input node DN3is only the significantly small capacitance formed at the overlapping region of the gate and the drain and source regions of the transistor constituting MOS capacitor6.

According to the rise and fall of clock signals CLK and /CLK respectively, clocked inverter CIV enters inactive state and thus enters output high impedance state. Clocked inverter8is activated to invert the signal of H level on internal node DN8and transmit the inverted signal to output node DN6. Then, internal output node DN6is maintained at L level by the latch circuit comprised of inverter7and clocked inverter8.

At time t4, after clock signal /CLK falls to L level, clock signal CLK rises to H level. At this time, no MOS capacitance is generated in MOS capacitor6, and there is only a minute capacitance present in MOS capacitor6between the gate and the source and drain of the MOS transistor constituting MOS capacitor6. Even if internal node DN7is in an electrically floating state and clock signal CLK is at H level, only this minute capacitance serves to perform a charge pump operation so that voltage level of internal node DN7changes by ΔVL. This amount of voltage change ΔVL is sufficiently smaller than the threshold voltage 2V of MOS transistor3, so that MOS transistor3is kept in turned-off state. Clocked inverter CIV determines the internal node DN7being substantially at L level.

According to fall of clock signal /CLK and rise of clock signal CLK, clocked inverter CIV is activated. Internal output node DN6is driven according to the voltage level of internal node DN7to have the voltage level thereof changed to H level. Internal node DN8is driven by inverter7to L level. At this time, clocked inverter8is in an inactive state and internal output node DN6is driven at a high speed by clocked inverter CIV.

At time t5, the level of input signal IN changes from L level to H level. In this state, clock signal /CLK is at L level, MOS transistor5is in a turned-off state, and internal node DN7is kept at L level (voltage ΔVL level). The time duration from time t5to time t6at which clock signal /CLK rises to H level is a setup time for input signal IN.

At time t6, after clock signal CLK falls to L level and clocked inverter CIV is driven to an inactive state, clock signal /CLK rises to H level. Then, MOS transistor5is turned on and input signal IN is transmitted to internal node DN7. Accordingly, the voltage level of internal node DN7changes to the voltage level (3 V) corresponding to H level of input signal IN. After this, an operation similar to the operation starting at time t0is carried out repeatedly.

Here, at time t6, in response to the fall of clock signal CLK, the voltage level of internal node DN7temporarily falls to the ground voltage level and then is driven to H level (VIH) of input signal IN according to input signal IN.

As discussed above, MOS capacitor6is connected to internal node DN7, input signal IN is transmitted to internal node DN7to bring internal node DN7into an electrically floating state, and then MOS capacitor6is driven by the clock signal to effect the charge pump operation. In this way, the voltage level of internal node DN7can be increased accurately up to the voltage level that allows clocked inverter CIV, which receives the internal power supply voltage VDD as an operating power-supply voltage, to normally operate. When the voltage level of internal node DN7is increased, merely the charge pump operation of the MOS capacitor is used and no current consumption occurs. Similarly, when internal node DN7is driven to L level, generation of the MOS capacitance is prevented. Thus, the voltage level of the internal node can be changed at a high speed and accordingly an internal signal ca be generated though high-speed level conversion of the input signal.

Second Embodiment

FIG. 4shows a configuration of a level conversion circuit according to a second embodiment of the present invention. The configuration of the level conversion circuit shown inFIG. 4differs from that of the level conversion circuit shown inFIG. 1in that, to low-side power supply node DN2of clocked inverter CIV, clock signal /CLK is applied instead of the measurement reference voltage (ground voltage VSS). Other configuration of the level conversion circuit shown inFIG. 4is identical to that of the level conversion circuit shown inFIG. 1. Therefore, like components are denoted by like reference numerals and the detailed description thereof is not repeated.

In the level conversion circuit shown inFIG. 4, clock signal CLK changes with a delay to clock signal /CLK.

FIG. 5is a signal waveform diagram representing an operation of the level conversion circuit shown inFIG. 4in the case where the clock skew large. As shown inFIG. 5, it is assumed now that input signal IN is at L level (0 V), clock signal CLK is at H level and clock signal /CLK is at L level. It is further assumed that, in this state, internal node DN7is kept at the boosted voltage (3 V+ΔVH) level.

Then, it is assumed that, at time ta, clock signal CLK falls from H level to L level while clock signal /CLK is at L level. At this time, MOS transistor5is in a turned-off state, so that through the charge pump operation of MOS capacitor6, the voltage level of internal node DN7decreases to H level (3 V) of input signal IN. Since clock signal /CLK is at L level, P-channel MOS transistor1of clocked inverter CIV is in a turned-on state. If power supply voltage VDD is 5 V, the gate-to-source voltage of MOS transistor2is −2 V. When the threshold voltage of MOS transistor2varies to a large degree and is −1.5 V, for example, MOS transistor2is turned on to and internal node DN6is charged to have the voltage level increased. At this time, if inverter7operates to drive internal node DN8to L level according to the voltage level of internal output node DN6, in clocked inverter8, P-channel MOS transistors for charging are turned on according to L level of clock signal CLK to drive internal output node DN6to H level.

At time t3, clock signal /CLK rises to H level. Responsively, clocked inverter CIV is inactivated and enters an output high impedance state. At this time, even if internal node DN7is driven to L level (ground voltage level) by input signal IN applied via MOS transistor5, internal node DN6is kept at H level since clocked inverter CIV is in the inactive state. Therefore, H level is outputted from internal output node DN6which should be kept at L level in a correct operation, resulting in malfunction. In order to prevent the timing margin of the clock signal from decreasing due to the above-described skew of the clock signals, fall of clock signal CLK is delayed relative to rise of clock signal /CLK.

FIG. 6is a signal waveform diagram representing an operation of the level conversion circuit shown inFIG. 4. With reference toFIG. 6, a description is now given of the operation of the level conversion circuit shown inFIG. 4.

In the period from time t0to time t2, the operation is similar to that represented by the signal waveform diagram shown inFIG. 3. Specifically, at time t2, input signal IN falls from H level to L level and input signal IN is set up.

At this time, internal node DN7is at the voltage level equal to the boosted voltage 3 V+ΔVH, internal output node DN6is at L level and internal node DN8is at H level.

At time t3, internal clock signal /CLK rises from L level to H level. At this time, clock signal CLK is at H level. Accordingly, MOS transistor5is turned on and internal node DN7is driven to the ground voltage level according to input signal IN. In this operation, both of the clock signals CLK and /CLK are at H level, the gate potential and the source potential of MOS transistor4are equal to each other and the MOS transistor3is kept non-conductive according to the voltage level of internal node DN7. P-channel MOS transistor1is kept off. Accordingly, clocked inverter CIV is in an inactive state in the period in which both of the clock signals CLK and /CLK are at H level. Even if the voltage level of internal node DN8lowers, internal output node DN6maintains L level without the influence of such voltage lowering.

At time t3a, clock signal CLK falls to L level. Accordingly, MOS transistor4is driven to a deeply off state. Since internal node DN7is coupled to input node DN5, internal node DN7is kept at the voltage level equal to the voltage level of input signal IN even when clock signal CLK falls.

At time t4, clock signal /CLK falls from H level to L level and thereafter clock signal CLK rises from L level to H level. When clock signal CLK rises to H level, clocked inverter CIV is activated since clock signal /CLK on low-side power supply node DN2is at L level. The voltage level of internal node DN7, however, is L level and no capacitance is formed in MOS capacitor6, so that the voltage level of internal node DN7increases only by voltage ΔVL and is kept at L level. In response to fall of clock signal /CLK at time t4, clocked inverter CIV is activated to drive internal output node DN6to H level (5 V).

At time t5, input signal IN rises from L level to H level.

At time t6, clock signal /CLK rises from L level to H level. At this time, clock signal CLK is kept at H level. Clock signal CLK falls to L level at time t6a. In the period from time t6to time t6a, MOS transistor4of clocked inverter CIV is kept in the turned-off state. Accordingly, the voltage level of internal node DN7increases to the voltage level of 3 V according to H level of input signal IN. Even when MOS transistor3is turned on, the discharge path of clocked inverter CIV is shut off so that the voltage level of internal output node DN6is kept at H level.

At time t6aat which clock signal CLK falls to L level, MOS transistor4of clocked inverter CIV is turned off and the discharge path is surely shut off.

In this way, clock signal CLK is changed with a delay to clock signal /CLK, accurately input signal IN is sampled and level converted, to generate an internal signal. Sampling here refers to the operation of taking in and latching an input signal. In other words, when the condition that clock signal CLK changes with a delay to clock signal /CLK is satisfied, it is insured that the level conversion is accurately performed and the level-converted signal is output and accordingly the level conversion circuit shown inFIG. 4can increase the timing margin.

In order for MOS capacitor6to carry out the charge pump operation and change the voltage level, it is required that MOS transistor5is in a turned-off state and internal node DN7is maintained in an electrically floating state. Thus, by raising clock signal CLK to H level after clock signal /CLK falls, MOS capacitor6can perform the voltage boosting thorough the charge pump operation.

FIG. 7shows an example of a configuration of a section that generates the clock signals in the second embodiment of the present invention. Referring toFIG. 7, the clock signal generation section includes, by way of example, cascaded inverters IV1to IV4of even-numbered stages (four stages inFIG. 7) receiving a main clock signal MCLK. From inverter IV1of the first stage, complementary clock signal /CLK is generated and, from inverter IV4of the last stage, clock signal CLK is generated.

Main clock signal MCLK is an externally applied clock signal to define the clock cycle at which input signal IN is applied. With the configuration of the clock signal generation circuit shown inFIG. 7, clock signal /CLK is delayed by the delay time of inverters IV2to IV4and further inverted to generate clock signal CLK. Clock signal CLK can thus be changed all the time after clock signal /CLK is changed, so that the level conversion of input signal IN can accurately be performed.

Alternatively, clock signals CLK and /CLK may be generated through phase adjustment by means of a circuit such as PLL (Phase Locked Loop).

As discussed above, according to the second embodiment of the present invention, to the low-side power supply node of the clocked inverter that level-converts the input signal, the clock signal defining sampling timing (timing at which the input signal is taken in and latched or the timing at which MOS transistor5is turned off) is applied. Accordingly, the timing margin of the clock signals of the level conversion circuit can be-increased, and the input signal can be taken in to be level-converted accurately to generate an input signal.

Third Embodiment

FIG. 8shows a configuration of a level conversion circuit according to a third embodiment of the present invention. The configuration of the level conversion circuit shown inFIG. 8differs from that of the level conversion circuit shown inFIG. 1or4in that, the gate of P-channel MOS transistor1of clocked inverter CIV that is connected to high-side power supply node DN1is connected to internal node DN7and clock signal /CLK is applied to the gate of P-channel MOS transistor2connected to internal output node DN6. Similarly, clock signal CLK is applied to the gate of N-channel MOS transistor3and the gate of N-channel MOS transistor4connected to low-side power supply node DN2is connected to internal node DN7. Further, to low-side power-supply node DN2, reference voltage VSS or clock signal /CLK is applied. Other configuration of the level conversion circuit shown inFIG. 8is identical to the level conversion circuit shown inFIG. 1or4. Therefore, like components are denoted by like reference numerals and the detailed description thereof is not repeated.

Specifically, clock signals /CLK and CLK are applied to the respective gates of MOS transistors2and3of clocked inverter CIV that are connected to internal output node DN6. In an operation period in which clock signal /CLK is at H level, clock signal CLK is at L level and input signal IN is input, MOS transistors2and3are in a turned-off state. The capacitive coupling between nodes DN6and DN7is thus suppressed sufficiently and any influence of a voltage-level change of internal node DN7on the voltage level of internal output node DN6can be suppressed.

When internal node DN6is in an electrically floating state after sampling, even if the voltage level of internal output node DN6is changed by clocked inverter CIV, the capacitive coupling between nodes DN7and DN6via parasitic capacitances of MOS transistors1and4can be suppressed. The voltage level of internal node DN7can thus be kept at a voltage level according to the sampled input signal.

Further, when MOS transistors2and3are in a turned-off state, only each respective drain junction capacitance is connected to internal output node DN6. Load on internal output node DN6when clocked inverter CIV is inactivated, can be reduced, so that internal output node DN6can be driven at a high speed by clocked inverter8.

As discussed above, according to the third embodiment of the present invention, the MOS transistors receiving the clock signals at their gates are connected to the internal output node of the level-conversion clocked inverter. Accordingly, the capacitive coupling between the internal nodes via the MOS transistors of the level-converting clocked inverter CIV can be mitigated so that the internal node can be maintained in a stable manner at a voltage level according to the sampled input signal.

Fourth Embodiment

FIG. 9shows a configuration of a level conversion circuit according to a fourth embodiment of the present invention. The level conversion circuit shown inFIG. 9differs in configuration from the level conversion circuit shown inFIG. 8in that a clock signal /CLKK is applied via a clock input node DN4ato the gate of sampling N-channel MOS transistor5. H level of this clock signal /CLKK is a voltage level higher than H level of clock signal /CLK. Other specific configuration of the level conversion circuit shown inFIG. 9is identical to the level conversion circuit shown inFIG. 8. Therefore, like components are denoted by like reference numerals and the detailed description thereof is not repeated.

When MOS transistor5has the threshold voltage varied to a large value, H level of clock signal /CLKa would cause a threshold voltage loss, and such a case may possibly result that input signal IN cannot fully be transmitted to internal node DN6. In order to prevent the threshold voltage loss, clock signal /CLKK with its H level made sufficiently high to the degree that the variation of the threshold voltage can be compensated for, is applied to the gate of sampling N-channel MOS transistor5, as shown inFIG. 10. Accordingly, even if the threshold voltage of MOS transistor5varies to some degree, it is ensured that input voltage IN is fully transmitted to internal node DN6.

When clock signal /CLKK of a large amplitude is used, this large-amplitude clock signal /CLKK may be applied to low-side power supply node DN2of clocked inverter CIV. In this way, since it is necessary to supply a ground voltage to low-side power supply node DN2, the degree of freedom of the layout can be improved.

In the configuration of this level conversion circuit shown inFIG. 9, MOS transistors2and3having respective gates receiving clock signals /CLK and CLK are connected to internal output node DN6. The configuration employing this large-amplitude clock signal /CLKK, however, may be used in the configuration shown inFIG. 1or4.

As discussed above, according to the fourth embodiment of the present invention, the clock signal having large amplitude is applied to the gate of the sampling MOS transistor. Even if the threshold voltage varies, input signal IN can surely be transmitted to the internal node without being accompanied by the threshold voltage loss.

Fifth Embodiment

FIG. 11shows a configuration of a level conversion circuit according to a fifth embodiment of the present invention. The level conversion circuit shown inFIG. 11selectively transmits clock signal CLK to internal node (input node of clocked inverter CIV) DN7according to a charged voltage of MOS capacitor6. Specifically, the level conversion circuit shown inFIG. 11includes N-channel MOS transistor5transmitting input signal IN applied to input node DN5to internal node DN9according to complementary clock signal /CLK from clock input node DN4, MOS capacitor6selectively forming a capacitance according to the potential difference between clock signal CLK on clock input node DN3and internal node DN9, N-channel MOS transistor9selectively transmitting clock signal CLK on clock input node DN3to internal node DN7according to the voltage on internal node DN9, N-channel MOS transistor10driving internal node DN7to the voltage level of low-side power supply node DN2according to clock signal /CLK, clocked inverter CIV performing level conversion on a signal to transmit the level-converted signal to internal output node DN6according to the signal on internal node DN7, and clocked inverters7and8constituting a latch circuit latching the signal on internal output node DN6.

Clocked inverter CIV has any of the configurations of clocked inverters of the first to fourth embodiments respectively. Clocked inverter CIV is activated when clock signals CLK and /CLK are at H and L levels, respectively, to drive internal output node DN6according to the signal on internal node DN7. Clocked inverter CIV is in an inactive state and accordingly in an output high impedance state when clock signals CLK and /CLK are at L level and H level, respectively.

Clock signals CLK and /CLK each have the amplitude larger than that of input signal IN. The relation in voltage amplitude as described in connection with the first to fourth embodiments holds between clock signals CLK and /CLK and input signal IN.

Measurement reference voltage VSS is applied to source node DN2aof N-channel MOS transistor10serving as a low drive circuit for driving internal node DN7to L level. As described later, a clock signal may be applied to this source node DN2a.

The latching operation performed by clocked inverter8and inverter7is the same as that described in connection with the first to fourth embodiments.

FIG. 12is a signal waveform diagram representing an operation of the level conversion circuit shown inFIG. 11. The operation of the level conversion circuit shown inFIG. 11is now described with reference toFIG. 12.

It is assumed here that, at time t10, input signal IN is at H level (3 V), clock signal /CLK is at H level (5 V) and clock signal CLK is at L level (0 V). In this state, MOS transistor5is in a turned-on state, and input signal IN is transmitted to internal node DN9so that the level of internal node DN9is at H level (3 V). Clock signal CLK is at L level so that MOS transistor9is turned on and L level (ground voltage level) is transmitted to internal node DN7. Clocked inverter CIV is in an inactive state so that internal output node DN6is maintained by inverter7and clocked inverter8at H level (5 V).

At time t11, clock signal /CLK falls to L level and subsequently clock signal CLK rises to H level. MOS transistor5is turned off and internal node DN9is in a floating state. At this time, MOS capacitor6has a channel generated to operate as a MOS capacitance for supplying electric charges to internal node DN9through its charge pump operation in response to the rise of clock signal CLK. Accordingly, the voltage level of internal node DN9increases by ΔVH. The voltage level resulting from the voltage increase ΔVH on node DN9is a voltage level sufficiently higher than H level of clock signal CLK. MOS transistor9is thus turned on to transmit clock signal CLK of H level to internal node DN7so that the voltage level of internal node DN7attains H level. In this operation, MOS transistor10is in a turned-off state. Since clocked inverter CIV is in the active state, clocked inverter CIV transmits the signal of L level to internal output node DN6according to the H level signal on internal node DN7.

At time t12, input signal IN falls to L level. At this time, clock signal/CLK is at L level, MOS transistor5is in the turned-off state, and a setup is made for a sampling operation of input signal IN.

At time t13, clock signal /CLK rises to H level and input signal IN on input node DN5is transmitted to internal node DN9, so that the voltage level of internal node DN9is L level identical to that of input signal IN. Further, in response to the rise of clock signal /CLK, MOS transistor10is turned on to discharge internal node DN7to ground voltage VSS level. When clock signal CLK falls, MOS transistor5is in the turned-on state and internal node DN9is not in the electrically floating state. Therefore, no charge pump operation by MOS capacitor6is carried out and internal node DN9is kept at L level of input signal IN.

In this state, clocked inverter CIV is in an inactive state, internal node DN7and internal output node DN6are isolated from each other and internal node DN6is kept at L level.

At time t14, clock signal /CLK falls to L level and subsequently clock signal CLK rises to H level. At this time, internal node DN9is at L level so that no channel is generated in MOS capacitor6. Accordingly, in response to the rise of clock signal CLK, the voltage level of internal node DN9increases by ΔVL by a parasitic capacitance of MOS capacitor6. This voltage ΔVL, however, is sufficiently smaller than the threshold voltage of MOS transistor9so that MOS transistor9remains in the turned-off state. Internal node DN7is at L level. In response to the fall of clock signal /CLK, the charging operation of clocked inverter CIV is activated, so that this final output node DN6is driven to H level of 5 V.

At time t15, input signal IN rises from L level to H level again for setup of input signal IN.

At time t16, clock signal /CLK rises to H level and sampling of input signal IN is started. After this, the operation from time t10is repeated.

In the level conversion circuit shown inFIG. 11, node DN9is connected to the gate of MOS transistor9and accordingly the parasitic capacitance of internal node DN9can be made small. Thus, the capacitance value CST of the parasitic capacitance in equation (1) can be decreased, voltage increase amount ΔVH can be large, so that the signal at power supply voltage VDD level can accurately be transmitted to input node DN7of clocked inverter CIV.

In the configuration of the level conversion circuit shown inFIG. 11, clock signal /CLKK of large amplitude maybe applied to the gate of MOS transistor5. To source node DN2aof MOS transistor10constituting the low drive circuit, clock signal CLK may be applied. When internal node DN7is discharged to L level, clock signal /CLK is at H level and clock signal CLK is at L level. Therefore, internal node DN7can surely be driven to L level. At this time, to low-side power supply node DN2of clocked inverter CIV, clock signal /CLK has to be applied (seeFIG. 4, for surely shutting off the discharging path).

As discussed above, according to the fifth embodiment of the present invention, MOS transistor9is driven in accordance with the charged voltage of MOS capacitor6that boosts the sampled input signal, to transmit the clock signal via the internal node to clocked inverter CIV. Accordingly, the parasitic capacitance of internal node DN9to which MOS capacitor6is connected can be reduced. The boosting operation of the sampled input signal can efficiently be performed, the level-converted signal can be transmitted to the clocked inverter, and the level-converted signal can surely be transmitted to the clocked inverter.

Sixth Embodiment

FIG. 13shows a configuration of a level conversion circuit according to a sixth embodiment of the present invention. The level conversion circuit shown inFIG. 6differs in configuration from shown inFIG. 11in that the source and drain nodes of a MOS transistor constituting MOS capacitor6of the level conversion circuit shown inFIG. 13is connected to internal node DN7which in turn is connected to the input of clocked inverter CIV. Other specific configuration of the level conversion circuit shown inFIG. 13are identical to the level conversion circuit shown inFIG. 11. Therefore, like components are denoted by like reference numerals and the detailed description thereof is not repeated.

In the configuration of the level conversion circuit shown inFIG. 13, in the state where internal node DN9is at the H level (3 V) of input signal IN, clock signal /CLK falls to L level and subsequently clock signal CLK rises to H level, and MOS transistor9in a weakly-on state transmits clock signal CLK to internal node DN7so that the voltage level of internal node DN7increases. According to the increase in voltage level of internal node DN7, the voltage level of internal node DN9increases through the capacitive coupling of MOS capacitor6. MOS transistor9enters a further deeply on state so that MOS transistor9transmits H level of clock signal CLK to internal node DN7. By the positive feedback operation of MOS capacitor6, the voltage level of internal node DN7can be increased at high speed.

When internal node DN9is at L level, MOS transistor9remains in the turned-off state. Even if clock signal CLK rises to H level, internal node DN7maintains the floating state of L level.

The level conversion circuit shown inFIG. 13uses no clock signal for driving MOS capacitor6. Therefore, no clock signal line to MOS capacitor6is necessary and thus the layout design is facilitated.

Seventh Embodiment

FIG. 14shows a configuration of a level conversion circuit according to a seventh embodiment of the present invention. The level conversion circuit shown inFIG. 14differs in configuration from the level conversion circuits shown inFIGS. 11 and 13in that no MOS capacitor6is provided. Specifically, in order to operate MOS transistor9having its gate connected to internal node DN9as a MOS capacitor, an N-channel MOS transistor9W with its channel width sufficiently made large is employed. Other specific configuration of the level conversion circuit shown inFIG. 14are identical to the level conversion circuit shown inFIGS. 11 and 13. Therefore, like components are denoted by like reference numerals and the detailed description thereof is not repeated.

In the level conversion circuit shown inFIG. 14, when internal node DN9is at H level while clock signal /CLK falls to L level and thereafter clock signal CLK rises to H level, a channel is formed in MOS transistor9w. A capacitor between this channel region and the gate causes the voltage level of internal node DN9to increase so that clock signal CLK at H level is transmitted to internal node DN7. In other words, the self-bootstrap function of this MOS transistor9wis used to increase the voltage level of internal node DN9according to the rise of clock signal CLK. In this way, clock signal CLK is transmitted to internal node DN7without loss of the threshold voltage of MOS transistor9w.

When internal node DN9is at L level, MOS transistor9wis in a turned-off state. Even if clock signal CLK rises, the voltage level of internal node DN9increases by only a small amount because of the presence of a gate-drain capacitor of MOS transistor9w. Then, MOS transistor9wremains in the turned-off state while internal node DN7is maintained at L level.

In the configuration of the level conversion circuit shown inFIG. 14, MOS transistor9wtransmitting the level-converted signal is operated as a MOS capacitor. Therefore, a separate MOS capacitor for voltage boosting is unnecessary. The layout area is thus reduced and the degree of freedom of layout is improved. Moreover, since the channel width of MOS transistor9wis made large, the current drivability is large so that internal node DN7can be driven to H level at a high speed.

Eighth Embodiment

FIG. 15shows a configuration of a level conversion circuit according to an eighth embodiment of the present invention. The level conversion circuit shown inFIG. 15differs in configuration from the low drive circuit for driving internal node DN7to L level shown inFIG. 14in the following points. Specifically, as this low drive circuit, there are further provided a P-channel MOS transistor11connected between power supply node DN1and internal node DN10and having its gate receiving clock signal CLK from clock input node DN3and an N-channel MOS transistor12connected between internal node DN10and low-side power supply node DN2band having its gate connected to internal node DN7. The gate of MOS transistor10is connected to internal node DN10.

Other specific configuration of the level conversion circuit shown inFIG. 15is identical to the level conversion circuit shown inFIG. 14. Therefore, like components are denoted by like reference numerals and the detailed description thereof is not repeated.

In the configuration of the level conversion circuit shown inFIG. 15, when clock signal CLK is at L level, MOS transistor11is turned on and internal node DN10is driven to H level. Accordingly, MOS transistor10is turned on and internal node DN7is driven to the voltage level on low-side power supply node DN2a, or ground voltage VSS level. Since internal node DN7is connected via MOS transistor10to low-side power supply node DN2a, it can be prevented that internal node DN7enters an electrically floating state when clock signal CLK is at L level. Thus, superimposition of noise on internal node DN7can be prevented.

When clock signal CLK is at L level, clock signal /CLK is at H level. Then, input signal IN is transmitted to internal node DN9. After clock signal /CLK falls to L level and internal node DN9enters an electrically floating state, clock signal CLK rises to H level. Accordingly, MOS transistor11is turned off. When input signal IN is at H level, the voltage level on internal node DN9increases in response to the rise of clock signal CLK. Accordingly, the voltage level on internal node DN7increases to H level (5 V). According to the increase in voltage level of internal node DN7, MOS transistor12transitions to a turned-on state to drive internal node DN10to L level and MOS transistor10is responsively driven to a turned-off state. In this way, sampled input signal IN can surely be level-converted and transmitted to internal node DN7.

When sampled input signal IN is at L level, MOS transistor9wis in a turned-off state and thus clock signal CLK is not transmitted via MOS transistor9wto internal node DN7. In this state, MOS transistor12is in a turned-off state while MOS transistor10remains in a turned-on state. Internal node DN7is kept at voltage VSS level on low-side power supply node DN2a. Accordingly, in this state, it can still be prevented that internal node DN7enters an electrically floating state. Thus, internal node DN7can stably be kept at the ground voltage level.

It is noted that, in the shown configuration, there is a possibility that in response to application of clock signal CLK to low-side power supply node DN2a, clock signal CLK at H level is transmitted via MOS transistor10when internal node DN7is at L level, and the voltage level of internal node DN7is erroneously changed. Therefore, in the configuration shown inFIG. 15, low-side power supply node DN2ais kept at measurement reference voltage VSS level.

In the level conversion circuit shown inFIG. 15, a voltage-boosting MOS capacitor may be connected to internal node DN9.

As discussed above, according to the eighth embodiment of the present invention, the low drive circuit is used to maintain node DN7at L level with low impedance when the L level signal is transmitted to input node DN7of clocked inverter CIV. Thus, a potential increase of internal node DN7due to noise can be prevented and accordingly a malfunction of clocked inverter CIV can be prevented.

Ninth Embodiment

FIG. 16schematically shows a configuration of a serial/parallel conversion circuit with level conversion function according to a ninth embodiment of the present invention. Referring toFIG. 16, the serial/parallel conversion circuit with level conversion function includes a level conversion circuit20for sampling input signal IN according to clock signals /CLK and CLK and converting the voltage level of input signal IN to output the converted signal, a latch circuit22for latching the output signal of level conversion circuit20when clock signal /CLK is at H level, a shift latch circuit24activated when clock signal CLK is at H level for transferring and latching the latched signal of latch circuit22, a shift latch circuit26activated when clock signal /CLK is at H level for shifting and latching the output signal of shift latch circuit24to generate output pixel signals /OTD and OTD, a level conversion circuit30sampling input signal IN according to clock signals CLK and /CLK and level-converting the input signal to output the level-converted signal, and a shift latch circuit32activated when clock signal /CLK is at H level for transferring and latching the output signal of level conversion circuit30to generate output pixel signals OTE and /OTE.

Level conversion circuits20and30operate complementarily to each other and each have any of the configurations of level conversion circuits described in connection with the first to eighth embodiments. Level conversion circuit20samples input signal IN when clock signal /CLK is at H level and level-converts the sampled input signal when clock signal CLK is at H level to output the level-converted signal. Level conversion circuit30samples input signal IN when clock signal CLK is at H level and level-converts the sampled input signal when clock signal /CLK is at H level to generate the level-converted signal.

Input signal IN is applied at a frequency twice as high as that of clock signals CLK and /CLK. When clock signal CLK is at H level, level conversion circuit30performs the sampling operation while level conversion circuit20performs the sampling operation when clock signal /CLK is at H level. From shift latch circuits26and32, pixel signals are output in parallel when clock signal CLK is at H level. Thus, the serial/parallel conversion circuit with level conversion function shown inFIG. 16frequency-divides the input signal IN into a signal at a frequency 0.5 times as high as the original frequency of the input signal. Accordingly, the operating frequency of the circuit in the following stage can be made lower and the operation margin can thus be enlarged.

FIG. 17shows an exemplary configuration of the serial/parallel conversion circuit with level conversion function shown inFIG. 16. Referring toFIG. 17, level conversion circuit20is similar in configuration to the level conversion circuit shown inFIG. 4, and includes an N-channel MOS transistor5arendered conductive when clock signal /CLK is at H level to transfer input signal IN, a MOS capacitor6aperforming a charge pump operation when clock signal CLK rises to H level to supply electric charges to internal node DN7a, and a clocked inverter CIVa activated when clock signals /CLK and CLK are at L and H levels, respectively, to drive internal node DN6according to the signal on internal node DN7a.

As in the previous embodiments, latch circuit22includes CMOS inverter7inverting a signal on internal node DN6and clocked inverter8activated when clock signals CLK and /CLK are at L and H levels, respectively, to invert the output signal of inverter7for driving internal node DN6.

Shift latch circuit24includes a clocked inverter40activated when clock signals CLK and /CLK are at L and H levels, respectively, to invert the signal on internal node DN6and transfer the signal to internal node DN11, an inverter41inverting the signal on internal node DN11, and a clocked inverter42activated when clock signals /CLK and CLK are at L and H levels, respectively, to invert the signal of inverter41and transmit the inverted signal to internal node DN11. These inverter41and clocked inverter42constitute an inverter latch when clocked inverter42is activated.

Shift latch circuit26includes a clocked inverter43activated when clock signals /CLK and CLK are at L and H levels, respectively, to invert the latched signal of shift latch circuit24and transfer the inverted signal to internal node DN13, an inverter44inverting the signal on internal node DN13, a clocked inverter45activated when clock signals CLK and /CLK are at L and H levels, respectively, to invert the signal of inverter44and transfer the inverted signal to internal node DN13, an inverter46inverting the output signal of inverter44to generate output signal /OTD, and an inverter47inverting the signal on internal node DN13to generate output signal OTD.

Level conversion circuit30is similar in configuration to level conversion circuit20, and includes an N-channel MOS transistor5btransmitting input signal IN in response to clock signal CLK, a MOS capacitor6bsupplying electric charges to internal node DN7bin response to a rise of clock signal /CLK, and a clocked inverter CIVb activated when clock signals CLK and /CLK are at L and H levels, respectively, to drive internal node DN17according to the signal on internal node DN7b.

Shift latch circuit32includes a clocked inverter50activated when clock signals /CLK and CLK are at L and H levels, respectively, to invert the signal on internal node DN17and transfer the inverted signal to internal node DN18, an inverter51inverting the signal on internal node DN18, a clocked inverter52activated when clock signals CLK and /CLK are at L and H levels, respectively, to invert the output signal of inverter51and transmit the inverted signal onto internal node DN18, an inverter53inverting the output signal of inverter51to generate output signal OTE, and an inverter54inverting the signal on internal node DN18to generate output signal /OTE.

In the configuration of the serial/parallel conversion circuit with level conversion function shown inFIG. 17, level conversion circuits20and30alternately perform the sampling operation and the level conversion operation according to clock signals CLK and /CLK, and shift latch circuits26and32carry out the operation of taking in the signal and the output operation in parallel. A description is now given of an operation of the serial/parallel conversion circuit with level conversion function shown inFIG. 17with reference to the timing diagram shown inFIG. 18.

At time t30, clock signal CLK rises to H level and clock signal /CLK falls to L level. The transition timing relation between clock signals CLK and /CLK is similar to that described in connection with the first to eighth embodiments. That is, after clock signal /CLK changes, clock signal CLK changes.

In level conversion circuit20, sampling of an input signal D1is completed and then level conversion is carried out by clocked inverter CIVa. Since clocked inverter8is in an inactive state, latch circuit22does not perform the latching operation. At this time, in shift latch circuit24, clocked inverter40is in an inactive state or in a latch state so that the output signal of level conversion circuit20is not taken in. Clocked inverter43at the initial stage of shift latch circuit26is activated so that the output signal of shift latch circuit24is taken in and outputted. In this case, however, the output signal is different from input signal D1and is an invalid signal.

In level conversion circuit30, input signal IN is taken in according to the rise of clock signal CLK. In this state, however, clocked inverter CIVb is in an inactive state and the signal on internal node DN17is an invalid signal. In shift latch circuit32, clocked inverter50at the initial stage is activated and output signal OTE is generated according to the signal on internal node DN17. In this case, however, the signal on internal node DN17is a signal irrelevant to input signal D1and is thus an invalid signal.

While the level conversion by level conversion circuit20and the sampling by level conversion circuit30are carried out in parallel, input signal IN changes to a second signal D2. At this time, as clock signal CLK is at H level, setup of input signal D2for level conversion circuit30is made.

At time t31, when clock signal CLK falls to L level and clock signal /CLK rises to H level, in level conversion circuit20, clocked inverter CIVa enters an output high impedance state. As clocked inverter8is activated, latch circuit22enters a latching state. At this time, clocked inverter40at the initial stage of shift latch circuit24is activated so that the first signal D1on internal node DN6is inverted to be transferred to internal node DN11. Clocked inverter43at the initial stage of shift latch circuit26is in an inactive state or latch state, so that no signal is taken in. The first data signal D1is taken in and the output signal changes in shift latch circuit24.

Level conversion circuit30takes in the second data signal D2in response to the fall of clock signal CLK. At this time, clocked inverter CIVb is in the inactive state and thus the state of internal node DN17does not change. In shift latch circuit32, clocked inverter50is in the inactive state. Thus, shift latch circuit32is in a latch state and its input and output are isolated from each other so that output signals OTE and /OTE do not change.

After setup of a third input signal D3, clock signal CLK rises to H level and clock signal /CLK falls to L level at time t32. Sampling of the third input signal D3by level conversion circuit20is completed. In response to the rise of clock signal CLK, a charge pump operation for internal node DN7ais carried out. At this time, clocked inverter CIVa is activated and level conversion circuit20outputs the level-converted signal of the third input signal D3(when input signal D3is at H level). In response to the rise of clock signal CLK, clocked inverter40at the initial stage of shift latch circuit24is inactivated and holds, at it output, the first data signal D1taken in in the preceding cycle.

In shift latch circuit32, clocked inverter50is activated in response to the rise of clock signal CLK and the fall of clock signal /CLK at time t32, its input and output are electrically coupled, and the shift latch circuit32enters a through state, and the level-converted signal corresponding to input signal D2on internal node DN11is output as output signal OTE. In shift latch circuit26, clocked inverter43at the initial stage is activated. Then, according to the latched signal of shift latch circuit24at the preceding stage, level-converted signal OTD corresponding to the first input signal D1is generated.

It is noted that, “level-converted signal” in the following description refers to “signal outputted from clocked inverter CIVa or CIVb”.

At time t33, clock signal CLK falls and clock signal /CLK rises to H level. Accordingly, clocked inverter CIVa of level conversion circuit20enters an output high impedance state to start sampling of input signal IN. In level conversion circuit30, in response to the rise of clock signal /CLK, a charge pump operation is performed. When input signal D4is at H level, internal node DN7bis boosted to a boosted-voltage level. Clocked inverter CIVb is activated so that a level-converted signal corresponding to the fourth data signal D4is output to internal node DN17. Shift latch circuit24enters a through state so that a level-converted signal corresponding to the third input signal D3is transferred. Since shift latch circuit26is in a latch state, output signals OTD and /OTD do not change.

At time t34, clock signal /CLK falls to L level and clock signal CLK rises to H level. Then, a sampling operation of level conversion circuit30is started while a level conversion operation of level conversion circuit20is carried out. At this time, shift latch circuit24is in a latch state while clocked inverter13at the input initial stage of shift latch circuit26is activated to enter a through state, so that output signal OTD corresponding to the third input signal D3is generated. Concurrently, clocked inverter50of shift latch circuit32is activated so that a level-converted signal corresponding to the fourth input signal D4is output as output signal OTE.

Thus, from level conversion circuit20, odd-numbered signals in an input sequence of input signal IN is output according to a fall of clock signal /CLK at a cycle of 2·Tcy and, from level conversion circuit30, even-numbered signals in the input sequence of input signal IN is output according to a fall of clock signal CLK.

Shift latch circuit24delays the output signal of level conversion circuit20by half a cycle Tcy of clock signals CLK and /CLK and outputs the delayed signal, and shift latch circuit26delays the output signal of shift latch circuit24by half a cycle Tcy of clock signals CLK and /CLK and outputs the delayed signal. Shift latch circuit32delays the output signal of level conversion circuit30by half a cycle Tcy of clock signals CLK and /CLK and outputs the delayed signal.

Thus, an odd-numbered signal of input signal IN is output in each cycle from level conversion circuit20, and an even-numbered signal of input signal IN is output in each cycle from level conversion circuit30according to a fall of clock signal CLK. Consequently, after one clock cycle of clock signals CLK and /CLK has passed since the first input signal D1is provided as input signal IN, even-numbered signals and odd-numbered signals of input signal IN are output in synchronization with a rise of clock signal CLK at a period of one clock cycle, or at a period twice the cycle Tcy of input signal IN. In this way, input signal IN with cycle Tcy can be level-converted to obtain output signals OTD and OTE with a cycle of 2·Tcy.

Thus, even if input signal IN is a high-speed signal, level conversion circuits20and30can be operated at a frequency 0.5 times as high as the frequency of input signal IN. The sampling and level-converting operations are reliably performed to transfer the level-converted signals to the circuitry at the subsequent stage.

Level conversion circuits20and30shown inFIG. 17have the configuration of the level conversion circuit shown inFIG. 3. Alternatively, the configuration of level conversion circuits20and30may any of those shown inFIGS. 1,8and9.

Modification

FIG. 19shows a configuration of a main portion of the serial/parallel conversion circuit with level conversion function according to the ninth embodiment of the present invention. InFIG. 19, the configuration of level conversion circuits20and30of the serial/parallel conversion circuit with level conversion function is shown. Referring toFIG. 19, level conversion circuit20includes N-channel MOS transistor5atransmitting input signal IN to internal node DN9awhen clock signal /CLK is at H level, MOS capacitor6aselectively performing a charge pump operation in response to a rise of clock signal CLK to supply electric charges to internal node DN9a, N-channel MOS transistor9atransmitting clock signal CLK to internal node DN7aaccording to signal potential on internal node DN9a, N-channel MOS transistor10aprecharging internal node DN7ato L level according to clock signal CLK, and clocked inverter CIVa activated when clock signals CLK and /CLK are at H and L levels, respectively, to invert a signal on internal node DN7a.

Level conversion circuit30has its configuration similar to that of level conversion circuit20. Specifically, level conversion circuit30includes N-channel MOS transistor5btransmitting input signal IN to internal node DN9bwhen clock signal CLK is at H level, MOS capacitor6bselectively performing a charge pump operation in response to a rise of clock signal /CLK to supply electric charge to internal node DN9b, N-channel MOS transistor9bselectively transmitting clock signal /CLK to internal node DN7baccording to signal potential on internal node DN9b, N-channel MOS transistor10bturned on when clock signal CLK is at H level, to precharge internal node DN7bto L level, and clocked inverter CIVb activated when clock signals CLK and /CLK are at L and H levels, respectively, to invert a signal on internal node DN7b.

The configuration of level conversion circuits20and30shown inFIG. 19is identical to that of the level conversion circuit shown inFIG. 11. At the following stage of level conversion circuit20, latch circuit22and shift latch circuits24,26shown inFIG. 16are provided while shift latch circuit32shown inFIG. 16is provided at the following stage of level conversion circuit30.

In the configuration of the serial/parallel conversion circuit with level conversion function shown inFIG. 19, level conversion circuits20and30alternately sample and level-converts input signal IN according to clock signals CLK and /CLK. In other words, when clock signal CLK is at H level, level conversion circuit30takes in input signal IN while level conversion circuit20selectively performs a level conversion operation according to the signal taken in and latched this cycle, and clocked inverter CIVa outputs the level-converted signal.

When clock signal /CLK is at H level and clock signal CLK is at L level, level conversion circuit20takes in input signal IN. At this time, clocked inverter CIVa is in an inactive state. In level conversion circuit30, MOS capacitor6performs a selective charge pump operation according to the sampled signal, and clock signal /CLK is selectively transmitted to clocked inverter CIVb via MOS transistor9b. Clocked inverter CIVb is activated and this clocked inverter CIVb generates a level-converted signal.

Thus, with the configuration shown inFIG. 19, input signal IN is taken in alternately by level conversion circuits20and30at the cycle of clock signals CLK and /CLK to perform the level conversion on the signal to generate the internal signal at a cycle twice as long as that of input signal IN.

It is noted that, as the configuration of the level conversion circuits20and30shown inFIG. 19, any of the configurations of other embodiments may be used.

As discussed above, according to the ninth embodiment of the present invention, the level conversion circuits are provided in parallel to the input node. According to complementary clock signals, the level conversion circuits are operated alternately to perform the sampling operation and the level converting operation. It is thus ensured that the cycle of input signal IN is doubled and the level conversion circuit is accordingly carried out.

If output signals OTE and OTD of the serial/parallel conversion circuit with level conversion function are display signals to be supplied to pixels, a horizontal shit register may be used to activate a horizontal driver driving a pixel data line at the same cycle as that of input signal IN so that pixel signals can be written to pixel elements according to the dot sequential system.

Tenth Embodiment

FIG. 20schematically shows a configuration of a serial/parallel conversion circuit with level conversion function according to a tenth embodiment of the present invention. Referring toFIG. 20, the serial/parallel conversion circuit having level conversion function includes level conversion circuits LCK1–LCKn provided in parallel to an input node for taking in and level-converting applied input signal IN according to shift clock signals /SH1–/SHn respectively from a shift register circuit60, latch circuits LLK1–LLKn provided corresponding to level conversion circuits LCK1–LCKn and activated when corresponding shift clock signals /SH1–/SHn are at L level to latch output signals of corresponding level conversion circuits LCK1–LCKn, and shift latch circuits SLK1–SLKn provided correspondingly to level conversion circuits LCK1–LCKn, entering a through state when latch instruction signal LAT is at H level and entering a latch state when latch signal LAT is at L level.

The output signals of shift latch circuits SLK1–SLKn are supplied in parallel to a digital/analog conversion circuit (DAC)65. Output signals PX1–PXm of digital/analog conversion circuit65are supplied to selected pixels of a pixel matrix (not shown). In other words, the serial/parallel conversion circuit with level conversion function shown inFIG. 20converts serially inputted display data IN into parallel signals for a display device formed using liquid-crystal elements or organic ELs, for example. By digital/analog conversion circuit65, analog signals are generated according to input digital data and the generated analog signals are written as pixel display signals to display elements. Digital/analog conversion circuit65generates, from a multi-bit digital signal, a single analog pixel display signal PXi (i=1−m) according to the gradation level of pixel display.

Shift register circuit60performs a shift operation following a supply start instruction signal Vst of input signal IN according to clock signal CLK and sequentially activate the shift clock signals /SH1–/SHn with a phase shift of approximately half a cycle with respect to input signal IN. Level conversion circuits LCK1–LCKn sequentially take in and level-convert input signal IN. After this, according to latch instruction signal LAT, shift latch circuits SLK1–SLKn take in and latch the respective output signals of corresponding level conversion circuits LCK1–LCKn in parallel to output the level-converted signals in parallel to digital/analog conversion circuit65. Then, according to the level-converted signals, digital/analog conversion is performed to generate display signals PX1–PXm for pixel elements.

FIG. 21shows an exemplary configuration of a section for generating a level-converted signal at a first stage of the serial/parallel conversion circuit with level conversion function shown inFIG. 20. InFIG. 21, shift clock signal /SHi from shift register circuit60is supplied as a sampling/level conversion timing signal.

Referring toFIG. 21, level conversion circuit LCKi includes an N-channel MOS transistor70transferring input signal IN to internal node DNi when shift clock signal /SHi is at H level, an inverter71inverting shift clock signal /SHi, a MOS capacitor72selectively performing a charge pump operation to supply electric charges to internal node DNi in response to a rise of output signal SHi of inverter71, and a clocked inverter CIV1selectively activated according to shift clock signals /SHi and SHi to generate a level-converted signal on internal node DNj according to a signal on internal node DNi.

Clocked inverter CIV1is supplied with power supply voltage VDD at a high-side power supply node and is supplied with shift clock signal /SHi at a low-side power supply node.

Latch circuit SLKi includes an inverter73inverting the signal on internal node DNj, and a clocked inverter74selectively activated according to shift clock signals SHi and /SHi to drive internal node DNj according to the output signal of inverter73. Clocked inverter74is activated complementarily to clocked inverter CIV1when shift clock signals SHi and /SHi are at L and H levels, respectively, to invert the output signal of inverter73.

Shift latch circuit SLKi includes a clocked inverter75inverting the signal on internal node DNj according to latch instruction signal LAT and complementary latch instruction signal /LAT, an inverter76inverting the output signal of clocked inverter75, and a clocked inverter77selectively activated according to latch instruction signals LAT and /LAT to invert the output signal of inverter76and transmit the inverted signal to internal node DNk.

Clocked inverter75is activated when latch instruction signals LAT and /LAT are at H and L levels, respectively, while clocked inverter77is activated when latch instruction signals LAT and /LAT are at L and H levels, respectively. When inactive, clocked inverters74,75and77enter an output high impedance state.

To the low-side power supply node of clocked inverter CIV1in level conversion circuit LCKi, shift clock signal /CHi is supplied. Thus, no line for transmitting ground voltage VSS is necessary so that the degree of freedom in interconnection layout design is improved.

The configuration of level conversion circuit LCKi shown inFIG. 21is substantially identical to the configuration of the level conversion circuit shown inFIG. 4. Therefore, when shift clock signal /SHi is at H level, input signal IN is taken in. When shift clock signal /SHi falls to L level, the taken input signal IN is level-converted to be outputted from clocked inverter CIV1to internal node DNj. The signal on internal node DNj is latched by latch circuit LLKi when shift clock signals SHi and /SHi are at L and H levels, respectively.

Shift latch circuit SLki is in a latch state when latch instruction signal LAT is at L level. When latch instruction signal LAT is at H level, shift latch circuit SLKi is in a through state to invert the signal latched by corresponding latch circuit LLKi and output the inverted signal to digital/analog conversion circuit65.

FIG. 22is a timing diagram representing an operation of the serial/parallel conversion circuit with level conversion function shown inFIG. 20. As shown inFIG. 22, shift clock signals /SH1–/SHn are set sequentially to L level for one cycle period of input signal IN with a delay of half a clock cycle relative to input signal IN. Accordingly, input signal IN is taken in with a setup time for each of level conversion circuits LCK1–LCKn in response to a fall of a corresponding one of sampling clock signals /SH1–/SHn. In response to a fall of a corresponding one of sampling clock signals /SH1–/SHn, level conversion circuits LCK1–LCKn each selectively boost the taken-in signal to perform a level conversion operation.

After this, when corresponding sampling clock signals /SH1–/SHn rise to H level, clocked inverters CIV1of level conversion circuits LCK1–LCKn are inactivated to enter an output high impedance state. Therefore, even if input signal IN changes, the change does not affect the level-converted signal and the level-converted signal of input signal IN is latched by corresponding latch circuits LLK1–LLKn.

When the final shift clock signal/SHn rises from L level to H level, latch instruction signal LAT subsequently rises to H level. Shift latch circuits SLK1–SLKn each enter a through state, to generate the signals according to the signals latched by latch circuits LLK1-LLKn for transmitting the generated signals to digital/analog conversion circuit65.

After a predetermined number of input signals IN are taken and after shift clock signal /SHn rises to H level, latch instruction signal LAT is driven to H level at an appropriate timing. Therefore, this latch instruction signal LAT may be generated from the register stage subsequent to the shift register stage generating shift clock signal /SHn in shift register circuit60, or may be generated based on a signal defining an appropriate digital/analog conversion timing.

Shift clock signals /SH1–/SHn are sufficient to be any signals each having a phase difference of the cycle of input signal IN with others, and may be signals different from output signals of shift register circuit60.

Further, in order to generate analog signals for pixel elements of the pixel matrix, the output signals of the serial/parallel conversion circuit with level conversion function are supplied to the digital/analog conversion circuit. The output signals of the serial/parallel conversion circuit, however, may be used for other purposes. In general, the serial/parallel conversion circuit with level conversion function of the present invention can be applied to any circuit portion for performing serial/parallel conversion and having serial input signals and parallel converted signals different in voltage amplitude.

Modification

FIG. 23shows a modification of level conversion circuits LCK1–LCKn shown inFIG. 20. InFIG. 23, a configuration of level conversion circuit LCKi (i=1−n) is shown as an example since level conversion circuits LCK1–LCKn have the same configuration. Referring toFIG. 23, level conversion circuit LCKi includes an N-channel MOS transistor80transferring input signal IN to internal node DNs according to shift clock signal /SHi, an inverter81inverting shift clock signal SHi, an N-channel MOS transistor82selectively transferring output signal SHi of inverter81to internal node DNt according to signal potential on internal node DNs, an N-channel MOS transistor83turned on when shift clock signal /SHi is at H level for precharging internal node DNt to a ground voltage level (low level of shift clock signal SHi), and a clocked inverter CIV2selectively activated according to shift clock signals SHi and /SHi, for inverting, when activated, a signal on internal node DNt.

Clocked inverter CIV2is activated when shift clock signal /SHi is at L level and shift clock signal SHi is at H level, to operate as an inverter.

The configuration of level conversion circuit LCKi shown inFIG. 23is identical to that of the level conversion circuit shown inFIG. 14. Specifically, when shift clock signal /SHi is at H level, input signal IN is taken in. When shift clock signal /SHi falls to L level, MOS transistor80is turned off. Output signal SHi of inverter81rises to H level, and accordingly, through self bootstrap function of MOS transistor82, the voltage level of internal node DNs is increased to fully transfer H level of this signal SHi to internal node DNt (when H level signal is sampled). At this time, clocked inverter CIV2enters an active state, the signal transferred to internal node DNt is inverted and the inverted signal is transferred to and latched by latch circuit LLKi at the following stage shown inFIG. 20.

When shift clock signal /SHi rises from L level to H level, output signal SHi of inverter81falls to L level, clocked inverter CIV2is inactivated and the input and output of clocked inverter CIV2are isolated from each other. In this state, MOS transistor83is in a turned-on state and internal node DNt is precharged to L level. Even if input signals IN are successively supplied to change the voltage level of internal node DNs, internal node DNt is kept at L level because output signal SHi of inverter81is at L level.

Thus, with level conversion circuit LCKi shown inFIG. 23, serial/parallel conversion and level conversion can be performed efficiently.

As discussed above, according to the tenth embodiment of the present invention, level conversion circuits are provided in parallel to carry out the sampling and the level conversion sequentially in a shifted manner. Accordingly, serial input signals can efficiently be converted into parallel signals and the voltage amplitude of the serial input signals can be converted.

Eleventh Embodiment

FIG. 24schematically shows a configuration of a serial/parallel conversion circuit with level conversion function according to an eleventh embodiment of the present invention. The serial/parallel conversion circuit with level conversion function shown inFIG. 24differs in configuration from that shown inFIG. 20in that, by level conversion circuits LCK1–LCKn for level-converting input signal IN, the input signal is sampled according to shift clock signals SH0–SH (n−1) from level conversion circuits at the preceding stages and is level-converted according to a corresponding one of shift clock signals /SH1–/SHn. Other specific configuration of serial/parallel conversion circuit with level conversion function shown inFIG. 24is identical to the configuration shown inFIG. 20. Then, like components are denoted by like reference characters and the description thereof is not repeated.

Level conversion circuits LCK1–LCKn shown inFIG. 24each take in input signal IN when a level conversion circuit at the preceding stage is performing a level conversion operation. After input signal IN is taken in, the shift clock signal at the preceding stage is kept in an inactive state of H level. Accordingly, in level conversion circuits LCK1–LCKn, the MOS transistor at the input stage (MOS transistor70inFIG. 21or MOS transistor80inFIG. 23) turns conductive. Thus, input signal IN is merely required to drive the internal node of a selected level conversion circuit and the capacitance element connected thereto (where a MOS capacitor is provided), so that the load of the input signal can be reduced and accordingly power consumption can be reduced.

FIG. 25shows an exemplary configuration of level conversion circuits LCK1–LCKn shown inFIG. 24. InFIG. 25, the configuration of level conversion circuit LCKi is shown as an example. The level conversion circuit LCKi shown inFIG. 25differs in configuration from level conversion circuit LCKi shown inFIG. 21in that an output signal of inverter90receiving a corresponding shift clock signal /SHi is provided to an electrode node (source and drain nodes) of MOS capacitor72, and also to the gate of N-channel MOS transistor4for controlling activation of clocked inverter CIV1. Further, the output signal of inverter90is applied as a sampling timing signal of level conversion circuit LCK (i+1) at the following stage. To the gate of N-channel MOS transistor70at the input stage, shift timing signal SH (i−1) for level conversion circuit LCK (i−1) at the preceding stage is supplied. Other specific configuration of level conversion circuit LCKi shown inFIG. 25are identical to the configuration shown in FIG.21. Then, like components are denoted by like reference numerals and the description thereof is not repeated.

In addition, the configuration of latch circuit LLKi and shift latch circuit SLKi is identical to that shown inFIG. 24and like components are denoted by like reference numerals and the description thereof is not repeated.

The operation timing of level conversion circuit LCKi shown inFIG. 25is identical to that shown inFIG. 22. Specifically, shift register circuit60operates similarly to shift register circuit60shown inFIG. 20except that it generates sampling timing signal SH0for level conversion circuit LCK1at the initial stage.

FIG. 26is a timing diagram representing an operation of level conversion circuit LCKi shown inFIG. 25. Referring toFIG. 26, the operation of level conversion circuit LCKi shown inFIG. 25is described.

When shift clock signal /SH (i−1) from shift register circuit60falls from H level to L level, inverted shift clock signal (sampling timing signal) SH (i−1) rises from L level to H level. Accordingly, MOS transistor70shown inFIG. 25is turned on and input signal IN is transmitted to internal node DNi. At this time, in level conversion circuit LCK (i−1), a level-converting operation is being performed according to shift clock signal /SH (i−1). In the period in which inverted shift clock signal SH (i−1) is at H level, input signal IN changes to an i-th input signal. Then, when shift clock signal /SH (i−1) rises to H level, inverted shift clock signal SH (i−1) falls to L level so that MOS transistor70shown inFIG. 25is turned off. At this time, shift clock signal /SHi is at L level, clocked inverter CIV1is activated and a selective level conversion operation is performed on the sampled signal. When the level conversion is performed in level conversion circuit LCKi, inverted shift clock signal SHi output from inverter90is at H level. In level conversion circuit LCK (i+1) at the following stage, this inverted shift clock signal SHi is used as a sampling timing signal. Then, MOS transistor70at the input stage is turned on to take in input signal IN. When shift clock signal /SHi rises to H level, clocked inverter CIV1of level conversion circuit LCKi is inactivated and the level-converted signal is latched by latch circuit LLKi at the subsequent stage.

Level conversion circuit LCK (i+1) at the subsequent stage completes its sampling operation and then carries out the level conversion and the latch operation according to shift clock signal /SH (i+1).

In this way, in level conversion circuits LCK1–LCKn, the MOS transistor (transistor70) at the input stage is turned on when input signal IN is to be taken in. After the sampling operation is completed, MOS transistor70at the input stage is held in a turned-off state. Thus, input signal IN is merely coupled to internal node DNi of the selected level conversion circuit all the time so that the load of the input signal can be reduced.

First Modification

FIG. 27shows a modification of the level conversion circuit in the eleventh embodiment of the present invention. Level conversion circuit LCKi shown inFIG. 27differs in configuration from the level conversion circuit shown inFIG. 23in the following points. Specifically, to the gate of MOS transistor80at the input stage, inverted shift clock signal SH (i−1) to the level conversion circuit (LCK (i−1)) at the preceding stage is supplied as a sampling timing signal. Further, inverted shift clock signal SHi from inverter81is supplied, as a sampling timing signal, to the gate of the MOS transistor at the input stage of the level conversion circuit (LCK (i+1)) at the subsequent stage. Other specific configuration of the level conversion circuit shown inFIG. 27is identical to the configuration of level conversion circuit LCKi shown inFIG. 23, and like components are denoted by like reference numerals and the description thereof is not repeated.

In the configuration of level conversion circuit LCKi shown inFIG. 27as well, inverted shift clock signal SH (i−1) rises to H level when level conversion circuit LCKi is selected so that MOS transistor80is turned on and input signal IN is transmitted to internal node DNs. When inverted shift clock signal SH (i−1) falls to L level, MOS transistor80is turned off. Accordingly, shift clock signal /SHi falls to L level, inverted shift clock signal SHi from inverter81rises to H level, and internal node DNt is driven according to the signal transferred to input node DNs. Clocked inverter CIV2is activated to generate a level-converted signal and this signal is latched by a latch circuit (LLKi) (not shown).

When shift clock signal /SHi rises to H level, inverted shift clock signal SHi falls to L level and internal node DNt is maintained at a ground voltage level again. Thus, internal node DNt is prevented from entering a floating state.

Where level conversion circuit LCi shown inFIG. 27is employed, input signal IN is coupled to the internal node of a selected level conversion circuit only, and thus, the load of input signal IN is reduced.

Second Modification

FIG. 28shows another modification of the level conversion circuit in the eleventh embodiment of the present invention. To the level conversion circuit shown inFIG. 28, input signal IN is applied sporadically and the level conversion circuit level-converts this single-shot input signal IN. Specifically, the level conversion circuit shown inFIG. 28includes a MOS transistor100transferring input signal IN according to clock signal CLK1and a level conversion unit102level-converting and latching the signal transferred via MOS transistor100according to clock signals CLK2and /CLK2. Level conversion unit102has the circuit configuration of any of the level conversion circuits of the first to the ninth embodiments except for the MOS transistor at the input stage. When clock signal CLK2is at H level and clock signal /CLK2is at L level, level conversion unit102is activated to convert an H level of the sampled signal into an H level at a voltage level higher than the H level of the sampled signal.

FIG. 29is a signal waveform diagram representing an operation of the level conversion circuit shown inFIG. 28. Referring toFIG. 29, the operation of the level conversion circuit shown inFIG. 28is briefly described.

When clock signal CLK1rises to H level, MOS transistor100is turned on and input signal IN is transferred to level conversion unit102. At this time, clock signals CLK2and /CLK2are at L level and H level, respectively, so that level conversion unit102remains in an inactive state.

When clock signal CLK1falls to L level, MOS transistor100is disabled and the sampling period of input signal IN completes.

After the sampling of input signal IN is completed, subsequently clock signal CLK2rises to H level and clock signal /CLK2falls to L level. Accordingly, level conversion unit102is activated to level-convert the sampled input signal IN and generate an internal signal. When clock signal CLK2falls to L level and clock signal /CLK2rises to H level, level conversion unit102is inactivated again to enter an output high impedance state. At this time, clock signal CLK1is at L level and the level conversion for input signal IN supplied in the “single-shot” manner is completed.

Thus, by setting the respective voltage levels of clock signals CLK1, CLK2and /CLK2in accordance with the timing at which input signal IN is applied, input signal IN can be reliably taken in and level-converted. In particular, generating clock signal CLK1and clock signals CLK2and /CLK2through separate paths ensures such sequence that the input signal is sampled and then level-converted by level conversion unit102.

As discussed above, according to the eleventh embodiment of the present invention, when the serial/parallel conversion and the level conversion are carried out, the input signal is transmitted to only the selected level conversion circuit and the input signal is taken in and then level-converted according to a corresponding clock signal (shift clock signal). The internal node of only the selected level conversion circuit is coupled to input signal IN, so that the load of input signal IN is reduced.

Moreover, when input signal IN applied in the “single-shot” manner is to be level-converted, individual clock signals can be formed through separate paths to increase the timing margin.

The configuration of level conversion circuits LCKi shown inFIGS. 25 and 27may be any of the configurations of other embodiments.

Further, the configuration of the clocked inverter may be the one as shown inFIG. 9in which the MOS transistors coupled to the internal node are coupled to the high-side and low-side power supplies and the MOS transistors having their gates receiving the clock signals are coupled to the output node of the clocked inverter.

The present invention is generally applicable to a level conversion circuit converting the voltage amplitude of an input signal, particularly applicable effectively to display devices using liquid-crystal or organic EL elements requiring the above-described level conversion.

In addition, the level conversion circuit according to the present invention is applicable to an interface between power supplies at respective voltage levels different from each other in a configuration employing a plurality of power supplies as in a system LSI.