Nitride-free spacer or oxide spacer for embedded flash memory

In some embodiments, a semiconductor substrate includes first and second source/drain regions which are separated from one another by a channel region. The channel region includes a first portion adjacent to the first source/drain region and a second portion adjacent the second source/drain region. A select gate is spaced over the first portion of the channel region and is separated from the first portion of the channel region by a select gate dielectric. A memory gate is spaced over the second portion of the channel region and is separated from the second portion of the channel region by a charge-trapping dielectric structure. The charge-trapping dielectric structure extends upwardly alongside the memory gate to separate neighboring sidewalls of the select gate and memory gate from one another. An oxide spacer or nitride-free spacer is arranged in a sidewall recess of the charge-trapping dielectric structure nearest the second source/drain region.

BACKGROUND

Flash memory is an electronic non-volatile computer storage medium that can be electrically erased and reprogrammed quickly. It is used in a wide variety of electronic devices and equipment. Common types of flash memory cells include stacked gate memory cells and split gate memory cells. Compared to stacked gate memory cells, split gate memory cells have higher injection efficiency, less susceptibility to short channel effects, and better over erase immunity.

DETAILED DESCRIPTION

Modern integrated circuits (ICs) often include logic devices and embedded memory disposed on a single substrate or die. One type of embedded memory included in such ICs is split gate flash memory. A split gate memory cell includes a source region and a drain region which are disposed within a semiconductor substrate and which are separated from one another by a channel region. A select gate (SG) is disposed over a first portion of the channel region nearest the drain, and is separated from the channel region by a SG dielectric. A memory gate (MG) is disposed adjacent to a sidewall of the SG and over a second portion of the channel region nearest the source, and is separated from the channel region by a charge-trapping dielectric layer. A nitride spacer, which can be formed as an aside during formation of logic devices on the die, can be disposed along a sidewall of the charge-trapping dielectric layer and over the channel region nearest the source.

During operation, the SG can be activated to enable current flow through the channel region (e.g., cause a stream of negatively charged electrons to flow between the source and drain regions). While the SG is activated, a large positive voltage can be applied to the MG, thereby attracting electrons from the channel region towards the MG. Some of these electrons become lodged in the charge-trapping layer, thereby changing the threshold voltage (Vt) of the memory cell. The resultant Vt corresponds to the data state stored in the cell. For example, if more than a predetermined amount of charge is lodged on the charge-trapping layer (e.g., magnitude of Vt is greater than some predetermined Vt), then the cell is said to store a first data state (e.g., a logical “0”); whereas if less than the predetermined amount of charge is lodged on the charge-trapping layer (e.g., magnitude of Vt is less than the predetermined Vt), then the cell is said to store a second data state (e.g., a logical “1”). By applying suitable bias conditions to the cell, electrons can be placed on (or stripped from) the charge-trapping layer to set corresponding data states for the cell. In this way, data can be written to and read from the memory cells.

Unfortunately, the nitride spacer disposed alongside the charge-trapping dielectric and disposed over the channel region can cause charge storage and removal anomalies. These anomalies tend to rear their head more as the cell undergoes more read and write operations. For example, due to the presence of the nitride spacer over the channel region, the nitride spacer can tend to undesirably trap charge and shift the Vt of the cell from expected values, particularly as the cell ages and has more read and write operations performed thereon.

The present disclosure relates to a split gate flash memory cell where a nitride-free spacer or an oxide spacer, either of which is relatively impervious to charge-trapping, is inserted in a sidewall recess of the charge-trapping layer nearest the source. Thus, this inserted spacer can extend along the sidewall recess of the charge-trapping layer directly over an outer edge portion of the channel region, and can extend upwards along the MG sidewall (or along a MG spacer sidewall), thereby limiting undesired charge-trapping. In some embodiments, if a nitride spacer is still present for the split gate flash memory, the inserted spacer effectively “pushes” the nitride sidewall spacer outwards so the nitride spacer no longer resides over the channel region. In this way, the nitride-free spacer or oxide spacer limits undesirably trapped charge and provides a flash memory cell with good performance over a long period of time.

FIG. 1illustrates a cross-sectional view of some embodiments of an integrated circuit100comprising a pair of split gate memory cells disposed on a semiconductor substrate108. The pair of split gate memory cell includes first and second memory cells102a,102b, which are configured to store separate data states and which are generally mirror images of one another about an axis of symmetry103. Typically, integrated circuit100includes hundreds, thousands, millions, billions, etc., of such memory cells, but only a single pair is illustrated for simplicity and clarity of understanding.

The first and second memory cells102a,102binclude first and second individual source regions104a,104b, respectively, and a common drain region106which is shared between the first and second memory cells. It will be appreciated that although region106is described as a “common drain region” and regions104a,104bare described as being “individual source regions”, the functionality of these regions may be flipped during some modes of operation and/or in some other implementations, such that “the common drain106” may act as a common source region and the “individual source regions104a,104b” may act as individual drain regions. Thus, the terms “source” and “drain” are interchangeable in this regard, and may be referred to generically as “source/drain” regions.

The first and second memory cells102a,102balso include first and second select gates110a,110b, respectively, and first and second memory gates112a,112b, respectively. The first select gate110aand first memory gate112aare arranged over a first channel region114a, which separates the first individual source region104aand the common drain region106. The second select gate110band second memory gate112bare arranged over a second channel region114b, which separates the second individual source region104band the common drain region106.

Select gate dielectric116a,116b, such as silicon dioxide or a high-κ dielectric material, is arranged under the first and second select gates110a,110b, and separates the first and second select gates from the semiconductor substrate108. Charge-trapping dielectric structure118a,118bseparates the first and second memory gates112a,112bfrom the semiconductor substrate108. Thus, the first and second memory gates112a,112bare disposed on a ledge corresponding to upper surface of charge-trapping dielectric structure118a,118b. The charge-trapping dielectric structure118a,118bcan also extend vertically upwards between neighboring sidewalls of the first select gate110aand first memory gate112a, and between neighboring sidewalls of the second select gate110band second memory gate112bto provide isolation there between.

In some embodiments, the charge-trapping dielectric structure118a,118bcomprises a charge-trapping layer119(e.g. a nitride layer or a layer of randomly arranged sphere-like silicon dots) sandwiched between two dielectric layers117,121(e.g., oxide layers). During operation of the first and second memory cells102a,102b, the dielectric layers117,121are structured to promote electron tunneling to and from the charge-trapping layer119, such that the charge-trapping layer119can retain trapped electrons that alter the threshold voltage of the split gate flash memory cells102a,102bin a discrete manner that corresponds to different data states being stored in the split gate flash memory cells102a,102b.

Memory gate sidewall spacers120a,120bare arranged on outer edges of the ledges formed by upper surface of the charge-trapping dielectric structure118a,118b. In some embodiments, the memory gate sidewall spacers120a,120bcomprise first, inner memory gate spacers122and second, outer memory gate spacers124. The first memory gate spacers122are arranged on ledges of the first and second memory gates112a,112band extend along outer sidewalls of the first and second memory gates112a,112b. The second memory gate spacers124are arranged on the charge-trapping dielectric structure118a,118band extend along outer sidewalls of the first memory gate spacers122.

Nitride-free or oxide spacers126a,126bare formed in sidewall recesses of the charge-trapping dielectric structure118a,118b, and can extend upwardly along an outer sidewall of the second memory gate spacers124over an outer edge of the channel regions114a,114bnearest the individual source regions104a,104b. The material of nitride-free or oxide spacers126a,126bcan also be disposed along an inner sidewall of select gates110a,110b(see128a,128b), and can extend into a sidewall recess within SG dielectrics116a,116b. The nitride-free or oxide spacers126a,126bcan each have an upper surface that is tapered to have a first height at the memory gate sidewall spacers120a,120band a second, reduced height nearer the first and second individual source regions104a,104b.

Nitride sidewall spacers130a,130b, such as made of silicon nitride (e.g., Si3N4) or silicon oxynitride (SiOxNy), can extend along outer sidewalls of the nitride-free or oxide spacers126a,126b. An inter-layer dielectric (ILD)132, such as silicon dioxide or a low-κ dielectric material, is disposed over the structure, and contacts134extend downward through the ILD layer132to make contact with a silicide layer136on an upper region of the individual source regions104a,104band common drain region106.

By positioning the oxide spacer layer or the nitride-free spacer126a,126bover an edge portion of channel regions114a,114b; the spacers126a,126b“push” the nitride sidewall spacers130a,130boutwards, which limits undesirable charge-trapping due to the nitride sidewall spacers130a,130b. Thus, Vt degradation over a lifetime of the memory cells102a,102bis limited.

With reference toFIG. 2, a flowchart of some embodiments of a method200for manufacturing an integrated circuit is provided.

At202, a pair of select gates are formed over a semiconductor substrate.

At204, a charge-trapping layer is formed over the pair of select gates and over the semiconductor substrate. A memory gate layer is then formed over the charge-trapping layer.

At206, a first memory gate spacer layer is conformally formed over the memory gate layer.

At208, the first memory gate spacer layer and memory gate layer are etched back to establish memory gate precursors and first memory gate spacers. The memory gate precursors are formed along outer sidewalls of the pair of select gates and between neighboring sidewalls of the select gates. The first memory gate spacers are disposed along ledges in the memory gate precursors, wherein the ledges are on outer sidewalls of the memory gate precursors.

At210, the memory gate precursors are recessed to expose sidewalls of the charge-trapping layer and to form memory gates along the outer sidewalls of the pair of select gates.

At212, second memory gate spacers are formed along outer sidewalls of the first memory gate spacers and along the exposed sidewalls of the charge trapping layer.

At214, the remaining memory gate material is removed from between neighboring sidewalls of the neighboring select gates.

At216, portions of the charge-trapping layer that are not covered by the memory gates and memory gate spacers are removed.

At218, an oxide spacer or nitride-free spacer is formed along outer sidewalls of the second memory gate spacers and along outer sidewalls of the charge-trapping layer. The oxide or nitride-free spacer extends under the second memory gate spacers.

At220, nitride sidewall spacers are formed along inner sidewalls of the select gates and outer sidewalls of the oxide or nitride-free spacer.

At222, an ion implantation operation is carried out to form source/drain regions. A silicide layer, such as a nickel silicide for example, is formed over the source/drain regions.

At224, an ILD layer is formed over the structure. The structure is then planarized, and contacts are formed through the ILD layer to ohmically connect to the source/drain regions.

With reference toFIGS. 3-19, cross-sectional views of a method of forming a pair of split gate memory cells according to some embodiments are provided. AlthoughFIGS. 3-19are described in relation to method200, it will be appreciated that the structures disclosed inFIGS. 3-19are not limited to such a method.

FIG. 3illustrates some embodiments of a cross-sectional view300corresponding to act202.

As shown in cross-sectional view300, a semiconductor substrate108is provided. A select gate dielectric layer116′ is formed on the semiconductor substrate108, and a select gate layer is formed over the select gate dielectric layer116′. A select gate (SG) hard mask302a,302bis then formed over the select gate layer, and an etch is carried out with the SG hard mask in place to form a pair of select gates110a,110b. In some embodiments, the SG hard mask302a,302bis formed by a lithographic process, wherein a layer of photoresist liquid is spun onto the select gate layer and the photoresist is selectively exposed to light through lithography. The exposed resist is then developed and can constitute the SG hard mask302a,302b, or can be used to pattern a nitride layer or another layer(s) to constitute the SG hard mask302a,302b.

The semiconductor substrate108can be n-type or p-type, and can, for example, be a silicon wafer, such as a Si bulk wafer or a silicon-on-insulator (SOI) wafer. If present, an SOI substrate comprises an active layer of high quality silicon, which is separated from a handle wafer by a buried oxide layer. The select gate dielectric layer116′ can be an oxide, such as silicon dioxide, or a high-κ dielectric material. The select gates110a,110bare made of a conductive material, such as doped polysilicon. The SG hard masks302a,302boften include nitrogen, and can be silicon nitride in some embodiments.

FIG. 4illustrates some embodiments of a cross-sectional view400corresponding to act204.

As shown in cross-sectional view400, a charge-trapping layer118′ is formed over an upper surface of the SG hard masks302a,302b, along sidewalls of SG hard masks302a,302b; along sidewalls of select gates110a,110b; and along sidewalls of SG dielectric layer116′. A memory gate (MG) layer112′ is then formed over the upper surfaces and sidewalls of the charge-trapping layer118′.

In some embodiments, the charge-trapping layer118′ can be formed by plasma enhanced chemical vapor deposition (PECVD). In some embodiments, the charge-trapping layer118′ includes a charge-trapping silicon nitride layer sandwiched between two silicon dioxide layers to create a three-layer stack commonly referred to as an “ONO” layer. In other embodiments, the charge-trapping layer118′ may include a silicon-rich nitride film or a layer of silicon nanoparticle dots, or any film that includes, but is not limited to, silicon, oxygen, and nitrogen in various stoichiometries. In some embodiments, the MG layer112′ can be, for example, doped polysilicon or metal. The MG layer112′ can be formed by deposition techniques such as chemical vapor deposition (CVD) or physical vapor deposition (PVD), for example.

FIG. 5illustrates some embodiments of a cross-sectional view500corresponding to act206.

As shown in cross-sectional view500, first memory gate spacer layer122′ is formed over the upper surfaces and sidewalls of the memory gate layer112′. The first memory gate spacer layer122′ can be a conformal layer made of silicon nitride, for example. In some embodiments, the first memory gate spacer layer122′ can be formed by plasma enhanced chemical vapor deposition (PECVD), chemical vapor deposition (CVD) or physical vapor deposition (PVD).

FIG. 6illustrates some embodiments of a cross-sectional view600corresponding to act208.

As shown in cross-sectional view600, first MG spacers122are formed directly along sidewalls of the memory gate precursors112a′,112b′. In some embodiments, the first memory gate spacers122are formed by carrying out an anisotropic etch602to etch the first memory gate spacer layer122′ and the memory gate layer112′ back to form first MG spacers122and memory gates precursors112a′,112b′.

FIG. 7illustrates some embodiments of a cross-sectional view700corresponding to act210.

As shown in cross-sectional view700, a second etch702is performed to recess the memory gate precursors112a′,112b′, thereby forming memory gates112a,112b. The first memory gate spacers122protect the upper corners of the memory gates112a,112bduring second etch702. In some embodiments, the second etch702may be performed using a dry etchant (e.g., an RIE etch, a plasma etch, etc.) or a wet etchant (e.g., hydrofluoric acid). The second etch702recesses the memory gate precursors to a height level substantially equal to that of the select gates110a,110b. An etchant used in the second etch702may be highly-selective to the charge-trapping layer118′, so as to not damage the charge-trapping layer118′.

FIG. 8illustrates some embodiments of a cross-sectional view800corresponding to act212.

As shown in cross-sectional view800, second MG spacers124are formed directly on outer sidewalls of the first memory gate spacers122, and directly over the charge-trapping layer118′. The second MG spacers124extend along outer sidewalls (of the first MG spacers122. In some embodiments, the second memory gate spacers124are formed by depositing a nitride layer over the entire structure and performing an anisotropic etch to form second MG spacers124. In some embodiments, the second MG spacers124comprise silicon nitride. The material of the MG spacers may also reside over memory gates112a,112band on exposed sidewalls of charge-trapping dielectric layer118′.

As shown in cross-sectional view900(FIG. 9), a mask904is patterned over the structure, and with the mask904in place, a third etch902is performed to remove the remaining MG material from between neighboring select gates110a,110b; resulting in the structure ofFIG. 10. In various embodiments, the etchant used in the third etch902may be a dry etchant (e.g., an RIE etch, a plasma etch, etc.) or a wet etchant (e.g., hydrofluoric acid).

As shown in cross-sectional view1000(FIG. 10), the mask904has been removed, and a fourth etch1002is then performed to remove exposed portions of the charge-trapping layer118′ (i.e., portions of the charge-trapping layer118′ not covered by the memory gates112a,112band not covered by first and second MG spacers122,124). In some embodiments, the fourth etch1002may be performed using a dry etchant (e.g., an RIE etch, a plasma etch, etc.) or a wet etchant (e.g., hydrofluoric acid), thereby resulting in the structure ofFIG. 11.

As can be seen fromFIG. 11, the fourth etch1002may remove portions of the charge-trapping dielectric layer118′ to expose upper surface of the semiconductor substrate108. The fourth etch1002may also form outer sidewall recesses1102in the charge trapping dielectric structure118a,118b. These outer sidewall recesses1102may have a rounded cross-sectional profile or a concave cross-sectional profile. In some embodiments, the fourth etch1002may also form inner sidewall recesses1104in the SG dielectric116a,116b. The amount of undercut by which these sidewall recesses undercut the overlying structures may vary widely. For example, in some embodiments, the outer sidewall recesses1102may have an innermost surface that terminates directly under the first MG spacers122, but in other embodiments the outer sidewall recesses1102may have an innermost surface that terminates directly under the second MG spacers124.

FIG. 12illustrates some embodiments of a cross-sectional view1200corresponding to act218.

As shown inFIG. 12, an oxide spacer layer or a nitride-free spacer layer126′ is formed over the structure. The oxide spacer layer or the nitride-free spacer layer126′ can be a conformal layer that fully or partially fills the inner and outer sidewall recesses1102,1104. In some embodiments, the oxide spacer layer is made of silicon dioxide and is formed by chemical vapor deposition (CVD), plasma vapor deposition (PVD), spin on techniques, or other suitable techniques. The nitride-free spacer layer is a dielectric layer that exhibits and absence of nitride.

FIG. 13illustrates some embodiments of a cross-sectional view1300corresponding to act218.

As shown inFIG. 13, a fifth etch1302is carried out to the form an oxide spacer or nitride-free spacer126a,126balong outer sidewalls of the second MG spacers124. The fifth etch may also leave oxide spacers or nitride-free spacers128a,128bon inner sidewall of select gates110a,110b. In some embodiments, the fifth etch1302is an anisotropic etch, such as a highly vertical plasma etch.

FIG. 14illustrates some embodiments of a cross-sectional view1400corresponding to act220.

As shown in cross-sectional view1400, a nitride spacer material130′ is formed over the structure. In some embodiments, the sidewall spacer material130′ can be silicon nitride. In some embodiments, the nitride spacer material130′ is formed concurrently with a sidewall spacer formed along sidewalls of a gate electrode on a logic region of the semiconductor substrate108. The logic region can be separate from a memory region where the split gate memory device are formed.

FIG. 15illustrates some embodiments of a cross-sectional view1500corresponding to act220.

As shown in cross-sectional view1500, the nitride spacer material130′ is etched to form nitride sidewall spacers130a,130bextending along outer sidewalls of the oxide spacer layer or the nitride-free spacer layer126. By positioning the oxide spacers or the nitride-free spacers126a,126bover the channel region between source/drain regions, the spacers126a,126b“push” the nitride sidewall spacer130a,130boutwards; thereby limiting undesirable charge-trapping in the final device.

FIG. 16illustrates some embodiments of a cross-sectional view1600corresponding to act222.

As shown in cross-sectional view1600, an ion implantation1602is carried out to form individual source regions104a,104b, and common drain region106in the semiconductor substrate108. A silicide layer136is formed over the individual source regions104a,104b, and common drain region106to facilitate ohmic connection to the individual source regions and common drain region. Alternatively, rather than ion implantation, individual source regions104a,104b, and common drain region106can be formed by forming a heavily doped layer over the structure, and dopants can be out-diffused from the heavily doped layer into the substrate to form individual source regions104a,104b, and common drain region106. In some embodiments, the individual source regions104a,104band common drain region106are self-aligned to edges of the nitride spacers130a,130bor nitride-free or oxide spacers126,128.

FIG. 17illustrates some embodiments of a cross-sectional view1700corresponding to act224.

As shown in cross-sectional view1700, an interlayer dielectric (ILD) layer132, for example a low-κ material, is formed to fill spaces over the silicide layer136and cover the workpiece. A planarization process is also carried out on the structure ofFIG. 17to reach CMP plane1702, as shown inFIGS. 17-18.

FIG. 18illustrates some embodiments of a cross-sectional view1800corresponding to act224.

As shown inFIG. 18, a planarization process is performed to form select gates110a,110b; memory gates112a,112b; charge-trapping dielectric structure118a,118b; first memory gate spacers122; and second memory gate spacers124. These structures have upper surfaces planarized along a horizontal plane1702. See alsoFIG. 17, which illustrates the horizontal plane1702prior to planarization being carried out. It is duly noted that the spacing of the horizontal plane1702over the upper surface of semiconductor substrate108can vary widely depending on the implementation. For example, in some other embodiments, the horizontal plane1702at which planarization is completed can be higher than illustrated, leaving some or all portions of the SG hard masks302a,302bin place in the final manufactured structure. In other embodiments, however, the horizontal plane1702can be lower than illustrated, removing larger portions of the illustrated structures—for example, possibly removing upper portions of spacers126a,126bto leave spacers126a,126bwith a planar upper surface.

FIG. 19illustrates some embodiments of a cross-sectional view1900corresponding to act224.

As shown in cross-sectional view1900, contacts134are formed through the ILD layer132, extending to the individual source regions104a,104band common drain region106. In some embodiments, the contacts134comprise a metal, such as copper, gold, or tungsten. In some embodiments, the contacts134are formed by performing a patterned etch to create openings in the ILD layer132, followed by filling the openings with a metal.

Thus, the present disclosure relates to an integrated circuit that includes a split gate flash memory cell. In some embodiments, the integrated circuit includes a semiconductor substrate having first and second source/drain regions which are separated from one another by a channel region. The channel region includes a first portion adjacent to the first source/drain region and a second portion adjacent the second source/drain region. A select gate is spaced over the first portion of the channel region and is separated from the first portion of the channel region by a select gate dielectric. A memory gate is spaced over the second portion of the channel region and is separated from the second portion of the channel region by a charge-trapping dielectric structure. The charge-trapping dielectric structure extends upwardly alongside the memory gate to separate neighboring sidewalls of the select gate and memory gate from one another. An oxide spacer or nitride-free spacer is arranged in a sidewall recess of the charge-trapping dielectric structure nearest the second source/drain region.

In other embodiments, the present disclosure relates to an integrated circuit including a pair of split gate flash memory cells. The integrated circuit includes a semiconductor substrate having a common source source/drain region and first and second individual source/drain regions which are separated from the common source/drain region by first and second channel regions, respectively. First and second select gates are spaced over the first and second channel regions, respectively, and are separated from the first and second channel regions by first and second select gate dielectrics, respectively. First and second memory gates are spaced over the first and second channel regions, respectively, and are separated from the semiconductor substrate by a charge-trapping dielectric structure. The charge-trapping dielectric structure extends upwardly along outer sidewalls of the first and second select gates to separate the outer sidewalls of the select gates from inner sidewalls of the memory gates. An oxide spacer or nitride-free spacer is arranged in a sidewall recess of the charge-trapping dielectric structure nearest the first or second individual source/drain region.

In yet another embodiment, the present disclosure relates to a method of forming a split gate memory device. In this method, a pair of select gates is formed over a semiconductor substrate. A charge-trapping layer is formed over the semiconductor substrate and along outer sidewalls of the select gates. Memory gates are formed over the charge-trapping layer. The memory gates are adjacent to the outer sidewalls of the pair of select gates and are separated from the outer sidewalls of the pair of select gates by the charge-trapping layer. Memory gate spacers are formed along outer sidewalls of the memory gates. Portions of the charge-trapping layer not covered by the memory gates and the memory gate spacers are removed to leave sidewall recesses in the charge-trapping layer under outer sidewalls of the memory gate spacers. An oxide spacer or nitride-free spacer is then formed along outer sidewalls of the memory gate spacers. The oxide spacer or nitride-free spacer extends into the sidewall recess in the charge-trapping layer.

It will be appreciated that in this written description, as well as in the claims below, the terms “first”, “second”, “second”, “third” etc. are merely generic identifiers used for ease of description to distinguish between different elements of a figure or a series of figures. In and of themselves, these terms do not imply any temporal ordering or structural proximity for these elements, and are not intended to be descriptive of corresponding elements in different illustrated embodiments and/or un-illustrated embodiments. For example, “a first dielectric layer” described in connection with a first figure may not necessarily correspond to a “first dielectric layer” described in connection with a second figure (e.g., and may even correspond to a “second dielectric layer” in the second figure), and may not necessarily correspond to a “first dielectric layer” in an un-illustrated embodiment.