Semiconductor device and method of manufacturing the same

Disclosed are a semiconductor device, which forms two insulation layers having different patterns by one mask process, and a method of manufacturing the same. In a semiconductor device having double insulation layers, a photosensitive material is included in an upper insulation layer. During a manufacture of the semiconductor device, the photosensitive material is used as a photo resist layer in order to reduce the number of masks.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims priority to and the benefit of Korean Patent Application No. 10-2007-0028164, filed on Mar. 22, 2007, in the Korean Intellectual Property Office, the entire content of which is incorporated herein by reference.

BACKGROUND

1. Field of the Invention

The present invention relates to a semiconductor device and a method of manufacturing the same, more particularly, to a semiconductor device including double insulation layers and a method of manufacturing the same.

2. Discussion of Related Art

A photolithography manufacturing method using masks corresponding to respective insulation layers has been used to form a semiconductor device that includes double insulation layers having different patterns.

An example of a semiconductor device that includes such double insulation layers is an organic light emitting display.FIG. 1is a cross-sectional view showing an organic light emitting display. Referring toFIG. 1, a buffer layer505of an image display portion500is formed on a substrate400. A thin film transistor and an organic light emitting diode are formed on the buffer layer505. Here, the organic light emitting diode is connected to the thin film transistor. A pad of a pad portion600is formed on the buffer layer505.

The thin film transistor includes a semiconductor layer510, a gate insulation layer520, a gate electrode525, an interlayer insulating layer530, and source/drain electrodes541and545. The semiconductor layer510includes source/drain regions511and515. The source/drain electrodes541and545are connected to the source/drain regions511and515, respectively.

An insulation layer550is formed on the thin film transistor. InFIG. 1, the insulation layer550includes a passivation layer550aand a planarization layer550b. The organic light emitting diode is formed on the insulation layer550and connected to the thin film transistor through a via hole555, which is connected to the drain electrode545of the source/drain electrodes541and545of the thin film transistor.

The organic light emitting diode includes an anode electrode560, a cathode electrode590, and an organic layer580. The organic layer580is formed between the anode electrode560and the cathode electrode590. A pixel division film570is formed on (or over) the substrate400and includes an opening portion575for exposing a part of the anode electrode560. The anode electrode560includes a reflection electrode, and the cathode electrode590includes a transmission electrode.

In more detail, the anode electrode560includes a laminate film composed of a reflection film560aand a transparent conductive film560b. In one embodiment, the anode electrode560is formed of an Ag/ITO film. A first conductive pattern527is formed on the gate insulation layer520at the pad portion600. The interlayer insulating layer530is formed on the gate insulation layer520and includes a first opening portion537for exposing a part of a first conductive pattern527. A second conductive pattern547is formed on the interlayer insulating layer530to be connected to the first conductive pattern527through the first opening portion537. The insulation layer550includes a first opening portion557for exposing a part of the second conductive pattern547. As described above, the insulation layer550includes the passivation layer550aand the planarization layer550b.

Here, the pad portion600includes the first conductive pattern527and the second conductive pattern547. The first conductive pattern527is exposed by the first opening portion537formed at the interlayer insulating layer530. The second conductive pattern547is connected to the first conductive pattern527through the first opening portion537, and is exposed by the first opening portion557formed at the insulation layer550. The pad portion600is coated with an amorphous conductive film601for adhesion with a connection circuit (or connection circuit board), such as a Flexible Printed Circuit (FPC).

The first conductive pattern527is formed by the same material as that of the gate electrode525of the thin film transistor, which is formed at the image display portion500. The first conductive pattern527includes metal materials, such as MoW, Al, AlNd, or Cr. The second conductive pattern547is formed by the same material as that of the source/drain electrodes541and545. The second conductive pattern547includes metal materials, such as MoW or Al.

In the above described organic light emitting display, the passivation layer550aand the planarization layer550bare provided between the thin film transistor and the organic light emitting diode as double insulation layers.

The planarization layer550bfunctions to optimize a resonant structure of the organic light emitting diode by planarizing one or more layers that the planarization layer550bis formed on (or with).

The passivation layer550aprovides a position for forming a seal between substrates of the organic light emitting display. Further, the passivation layer550aprevents (or protects from) a wiring opening and/or a short circuit due to a scratch at the pad portion600and improves the dispersion of the transistor through a heat treatment. Here, the passivation layer550aand the planarization layer550bare shaped with different patterns.

Accordingly, to form the planarization layer of the above described organic light emitting display, a first mask process (or masking process) is required. Also, there is a need for an additional (or second) mask process to form the passivation layer.

However, since one or more additional processes, such as an etching process and a washing process, need to be performed due to the additional mask process, the additional mask process increases the overall manufacturing cost (and time) and may also damage the organic light emitting display being manufactured.

SUMMARY OF THE INVENTION

Aspects of embodiments of the present invention are directed to a semiconductor device including two insulation layers having different patterns formed by one (or a single) mask process, and a method of manufacturing the same.

A first embodiment of the present invention provides a semiconductor device including double insulation layers. The double insulation layers include: a first insulation layer having a first pattern; and a second insulation layer on the first insulation layer and including a photosensitive material, the second insulation layer having a second pattern differing from the first pattern and including a material differing from that of the first insulation layer; wherein the double insulation layers further include: a first region in which the first insulation layer and the second insulation layer overlap; a second region in which the first insulation layer is disposed without the second insulation layer; and a third region in which the first and second insulation layers are absent.

A second embodiment of the present invention provides an organic light emitting display including a display region formed on a substrate; a non-display region being electrically connected to the display region in which at least one terminal is disposed; and double insulation layers. The double insulation layers include: a first insulation layer having a first pattern; and a second insulation layer on the first insulation layer and comprising a photosensitive material, the second insulation layer having a second pattern differing from the first pattern and including a material differing from that of the first insulation layer, wherein the display region includes a double-insulation region in which the first insulation layer and the second insulation layer overlap and a non-insulation region in which the first and second insulation layers are absent, and wherein the non-display region comprises a single-insulation region in which the first insulation layer is disposed without the second insulation layer and a non-insulation region in which the first and second insulation layers are absent.

A third embodiment of the present invention provides a method of manufacturing an insulation layer of a semiconductor device including double insulation layers. A formation of the double insulation layers includes: coating a first insulation layer on an entire surface of a substrate; coating a second insulation layer on the first coated insulation layer, the second insulation layer including a photosensitive material and being formed of a material differing from that of the first insulation layer; patterning the second insulation layer to form a first region, a second region, and a third region, wherein, in the first region, the second insulation layer is formed to have a first pattern of a first thickness, wherein, in the second region, the second insulation layer is formed to have a second pattern of a second thickness less than the first thickness, and wherein, in the third region, the second insulation layer is removed to expose the first insulation layer formed at a lower portion of the second insulation layer; etching the first insulation layer of the third region; removing the second pattern of the second insulation layer; and ashing the first pattern of the second insulation layer such that the first pattern of the second insulation layer remains.

A fourth embodiment of the present invention provides a method of manufacturing an organic light emitting display including: a display region formed on a substrate; a non-display region being electrically connected to the display region in which at least one terminal is formed; and double insulation layers. A formation of the double insulation layers includes: forming a first insulation layer; forming a second insulation layer on the first insulation layer, the second insulation layer including a photosensitive material and being formed of a material differing from that of the first insulation layer; patterning the second insulation layer to form a first region, a second region, and a third region, wherein, in the first region, the second insulation layer is formed to have a first pattern of a first thickness, wherein, in the second region, the second insulation layer is formed to have a second pattern of a second thickness less than the first thickness, and wherein, in the third region, the second insulation layer is removed to expose the first insulation layer formed at a lower portion of the second insulation layer; etching the first insulation layer of the third region; removing the second pattern of the second insulation layer; and ashing the first pattern of the second insulation layer such that the first pattern of the second insulation layer remains.

A fifth embodiment of the present invention provides an organic light emitting display having a display region and a non-display region and including: a thin film transistor; a first insulation layer on the thin film transistor having a first pattern; a second insulation layer on the first insulation layer and including a photosensitive material, the second insulation layer having a second pattern differing from the first pattern and comprising a material differing from that of the first insulation layer; and an organic light emitting diode on the second insulating layer, wherein the first insulation layer and the second insulation layer are arranged to have a double-insulation region in which the first insulation layer and the second insulation layer overlap, a non-insulation region in which the first and second insulation layers are absent, and a single-insulation region in which the first insulation layer is disposed without the second insulation layer, wherein the double-insulation region and the non-insulation region are disposed in the display region, and wherein the single-insulation region and the non-insulation region are disposed in the non-display region.

In the semiconductor device according to the present invention, double insulation layers having different patterns are formed by one (or only one) mask, which leads to a reduction in processes and cost.

DETAILED DESCRIPTION

Here, when one element is referred to as being connected to another element, one element may be not only directly connected to the another element but instead may be indirectly connected to the another element via one or more other elements. Also, when an element is referred to as being “on” another element, it can be directly on the another element or be indirectly on the another element with one or more intervening elements interposed therebetween. Further, some of the elements that are not essential to the complete description of the invention have been omitted for clarity. In addition, like reference numerals refer to like elements throughout.

FIG. 2is a cross-sectional schematic view showing a semiconductor device according to an embodiment of the present invention.FIG. 3AtoFIG. 3Eare cross-sectional schematic views of a semiconductor device for illustrating a method of manufacturing the semiconductor device shown inFIG. 2f.

An insulation layer is formed on a substrate10. Here, the substrate10refers to all layers on which the insulation layer is formed. The insulation layer includes a first insulation layer20and a second insulation layer30. The first insulation layer20and the second insulation layer30are arranged to have different patterns and are formed with different materials. Because, the first insulation layer20and the second insulation layer30are arranged to have different patterns, a first region, a second region, and a third region can result. That is, as shown inFIG. 2, both the first and second insulation layers20and30are present at the first region, only the first insulation layer20is present at the second region, and both of the first and second insulation layers20and30are absent at the third region.

To put it another way, the first insulation layer20and the second insulation layer30are overlapped with each other in the first region. Only the first insulation layer20is formed in the second region. The first and second insulation layers20and30are both absent in the third region.

In one embodiment, the first insulation layer20is formed of an inorganic material, which has a different etching characteristic from that of the second insulation layer30. For example, SiO2or SiNXcan be used as the inorganic material of the first insulation layer20.

In one embodiment, the second insulation layer30is formed of an organic material. For example, acryl, poly imide, and/or benzocyclobutanes (BCB) may be used as the organic material of the second insulation layer30.

Also, the second insulation layer30includes a photosensitive material. As described in more detail with reference to a manufacturing method according to an embodiment of the present invention, one reason for using the photosensitive material as the second insulation layer30is so that one mask (or a single mask) can be used to form double (or two different) insulation layers by using the second insulation layer30as a photo resist pattern. In one embodiment, 2,3,4-Trihydroxybenzophenone-orthonaphtoquinone 1,2-diazidesulfonic acid Triester as represented by the following chemical formula can be used as the photosensitive material.

The following is a description of a method of manufacturing the semiconductor device including the double insulation layers.

First, as shown inFIG. 3A, the first insulation layer20is formed. For convenience of the description purposes, hereinafter, the first insulation layer and the second insulation layer in final and intermediate steps are all referred to as the ‘first insulation layer20’ and the ‘second insulation layer30’, respectively. InFIG. 3A, an entire surface of the substrate10is coated with the first insulation layer20.

Next, as shown inFIG. 3B, the second insulation layer30including the photosensitive material is disposed on the first insulation layer20. That is, the second insulation layer30using material different from that of the first insulation layer20is formed on the first insulation layer20. In more detail and as shown inFIG. 3B, after a formation of the first insulation layer20, an entire surface of the first insulation layer20is continuously coated with the second insulation layer30.

Subsequently, the second insulation layer30is patterned to have a first region, a second region, and a third region. Here, in the first region, the second insulation layer30is formed to have a first pattern of a first thickness. In the second region, the second insulation layer30is formed to have a second pattern of a second thickness less than the first thickness, and in the third region, the second insulation layer30is removed to expose the first insulation layer20formed at a lower portion of the second insulation layer30(i.e., by removing the second insulation layer30in the third region, the first insulation layer20formed at the lower portion of the second insulation layer30is exposed).

Referring toFIG. 3C, the patterning step of the second insulation layer30can be achieved by exposing and developing the second insulation layer30using a half tone mask50having different light-shielding degrees according to different regions.

That is, the half tone mask50includes a light-shielding pattern (or a full or high light-shielding pattern) corresponding to the first pattern, a partial light-shielding pattern corresponding to the second pattern, and an opening pattern (or a non-light shielding pattern) corresponding to the third pattern. Accordingly, in one embodiment, the half tone mask50causes the second insulation layer30to have different heights (or thickness) in accordance to different exposure regions.

As discussed and illustrated above, since the first region of the second insulation layer30is not exposed (or minimally exposed) to a developing light by the light-shielding pattern of the half tone mask50, the second insulation layer30is not developed. Because a partial thickness of the second insulating layer30at the second region thereof is exposed to the developing light by the partial light-shielding pattern of the half tone mask50, only a partially exposed part of an upper layer portion of the second insulation layer30is developed. No light-shielding patterns are used in the third region of the second insulation layer30. That is, since an entire thickness of the second insulating layer30at the third region is exposed to the developing light, the entire portion of the second insulation layer30at the third region is all developed. Here, a transmittance degree of the developing light is changed by controlling a thickness of a partial light-shielding pattern in the mask or an exposure time, which allows a thickness of the second insulation layer30to be adjusted.

To put it another way, in the half tone mask50, a laminate structure of a partial light-shielding pattern51and a light-shielding pattern52is formed at a corresponding part of the first region. Further, the half tone mask50on which only the partial light-shielding pattern51is formed may be used at a part corresponding to the second region. However, the present invention is not limited thereto. Here, the partial light-shielding pattern51is formed of a material such as MoSi, which partially transmits light, and the light-shielding pattern52is formed of a material such as chromium (Cr), which blocks (or fully blocks or cuts off) light.

Referring now toFIG. 3D, the first insulation layer20of the third region is etched. The first insulation layer20may be etched by a wet etching method and/or a dry etching method.

Referring now toFIG. 3E, the second pattern of the second insulation layer30at the second region is removed, and the second insulation layer30at the first region is ashed such that the first pattern of the second insulation layer30remains. Here, ashing is referred to as a process to remove a photo resist. In one embodiment of the present invention, because the second insulation layer30is used as a photo resist, a process for removing the second insulation layer30becomes an ashing process.

Hereinafter, as an application example of embodiments of the present invention described above, the following is a description of a method of manufacturing an organic light emitting display according an embodiment of the present invention.

FIG. 4is a plan schematic view showing an organic light emitting display according to an embodiment of the present invention.FIG. 5is a cross-sectional schematic view showing parts A, B, and C of the organic light emitting display ofFIG. 4. The organic light emitting display includes a first substrate, a second substrate300, and a sealing material400. Here, the first substrate is referred to as a total substrate including an organic light emitting diode array. Further, a deposition substrate110is referred to as a substrate in which an organic light emitting diode is formed at an upper portion thereof.

The first substrate includes a display (or pixel) region100aand a non-display (or non-pixel) region100b. The display region100aincludes an organic light emitting diode array on which one or more organic light emitting diodes are formed. Each of the organic light emitting diodes includes a first electrode210, an organic layer220, and a second electrode230. The non-display region100bis formed at a peripheral part of the display region100a. Driver integrated circuits101and102, a sealing material400, and metal wirings170band170care formed in the non-display region100b.

The display region100aincludes a plurality of scan lines S1to Sn arranged in a row direction and a plurality of data lines D1to Dm arranged in a column direction. A plurality of pixels are formed at intersections of the scan lines and the data lines, and receive a signal for driving the organic light emitting diode from the driver integrated circuits101and102.

Furthermore, a driver integrated circuit and metal wirings170band170care formed at the non-display region100b. The driver integrated circuit drives the organic light emitting diode. The metal wirings170band170care electrically connected to the scan lines S1to Sn and the data lines D1to Dm of the display region100a, respectively. In the embodiment of the present invention, the driver integrated circuit includes a data driver101and a scan driver102.

InFIG. 4andFIG. 5, the parts A, B, and C illustrate cross-sectional structures that indicate one section (or portion) of the display region100a, one section in which the sealing material400of the non-display region is positioned, and one section of a pad portion.

The following is an explanation of the structure of the part A. A buffer layer120is formed on the deposition substrate110. Here, the buffer layer120is formed of an insulation material such as silicon oxide (SiO2) and/or silicon nitride (SiNX). The buffer layer120prevents (or protects) the deposition substrate110from being damaged due to heat from an exterior.

A semiconductor layer130is formed on at least one region of the buffer layer120. The semiconductor layer130includes an active region130a, and source and drain regions130band130c. A gate insulation layer140is formed on the semiconductor layer130and the buffer layer120. A gate electrode150is formed on one region of the gate insulation layer140, and has a size corresponding (or substantially corresponding) to a width of the active region130a.

An interlayer insulating layer160is formed on the gate insulation layer140including the gate electrode150. Source and drain electrodes170aare formed on regions (or predetermined regions) of the interlayer insulating layer160.

The source and drain electrodes170aare connected to exposed regions of the source and drain regions130band130b. First insulation layers180a,180b,180c(together referred to as the ‘first insulation layer180’) are formed on the interlayer insulating layer160including the source and drain electrodes170a.

In one embodiment, the first insulation layer180is formed of an inorganic material. The first insulation layer180can also be referred to as the ‘passivation layer’. However, the present invention is not limited thereto.

A second insulation layer190is formed on the first insulation layer180, and is made of a material different from that of the first insulation layer180. The second insulation layer190can also be referred to as the ‘planarization layer’. However, the present invention is not limited thereto. Here, the second insulation layer190is formed of a photo resist layer. For example, a photosensitive material is added to an organic material to form the second insulation layer190. The organic material can be acryl, poly imide, and/or benzocyclobutanes (BCB). Also, as an example, 2,3,4-Trihydroxybenzophenone-orthonaphtoquinone 1,2-diazidesulfonic acid Triester as represented by the following chemical formula can be used as the photosensitive material.

A first electrode210is formed on one region of the second insulation layer190. Here, the first electrode210is connected to one exposed region of one of the source and drain electrodes170aby a via hole penetrating the first insulation layer180and the second insulation layer190.

A pixel defining layer240is formed on the second insulation layer190including the first electrode210, and includes an opening portion for exposing at least one region of the first electrode210. An organic layer220is formed on the opening portion of the pixel defining layer240. A second electrode230is formed on the pixel defining layer240including the organic layer220. Here, a passivation layer can be further formed at an upper portion of the second electrode230.

The second substrate300seals at least the display region100aon which the one or more organic light emitting diodes are formed. In a case in which the organic light emitting display is a top-emission display or a double-sided emission display, the second substrate300is formed of a transparent material. By contrast, in a case in which the organic light emitting display is a bottom-emission display, the second substrate300is formed of an opaque material.

In one embodiment of the present invention, the second substrate300is constructed to be a plate type substrate (or to have a plate shape). The second substrate300seals at least the display region on the deposition substrate110, on which the one or more organic light emitting diodes are formed. In one embodiment, the second substrate300seals all regions on the deposition substrate110except for a data driver and a pad portion.

The sealing material400is formed between the second substrate300and the non-display region100bof the deposition substrate110, and seals the display region100so as to prevent an infiltration of ambient air. The sealing material400may be formed of organic and/or inorganic material. When the inorganic material is used as the sealing material400, it includes an absorber for absorbing a laser and a filler for reducing a thermal expansion coefficient. The inorganic material can be K2O, Fe2O3, Sb2O3, ZnO, P2O5, V2O5, TiO2, Al2O3, B2O3, WO3, SnO, and/or PbO. Here, when the inorganic material is used as the sealing material400, a formation line of the sealing material400overlaps with a metal wiring. In this case, when a laser or infrared rays are irradiated to the sealing material400, the metal wiring may be damaged. Accordingly, in one embodiment of the present invention, the first insulation layer180formed of (or including) an inorganic material is provided (or used) to protect from this metal wiring damage. Further, when the organic material is used as the sealing material400, epoxy resin may be used.

In addition, referring also toFIG. 6E, the part A includes a first region and a third region. The first insulation layer180and the second insulation layer190are formed in the first region as double insulation layers. The first insulation layer180and the second insulation layer190are absent at the third region.

The following is an explanation of a structure of the part B. The part B is a formation position of the sealing material400. The aforementioned buffer layer120is extended and formed on the deposition substrate110. The gate insulation layer140is extended and formed at an upper portion of the buffer layer120. The interlayer insulating layer160is formed at an upper portion of the gate insulation layer140. The first metal wiring170bis formed at an upper portion of the interlayer insulating layer160, and is made of the same (or substantially the same) material as that of the source and drain electrodes170a. Here, in one embodiment, the first metal wiring170bis a power line, but the present invention is not limited thereto. The first insulation layer180is formed on the metal wiring170bto protect the first metal wiring170b. The sealing material400is provided on the insulation layer180. Here, referring also toFIG. 6E, the part B includes a second region and the third region. The first insulation layer180(or only the first insulation layer180) is present in the second region as a single insulation layer. The first insulation layer180and the second insulation layer190are both absent at the third region.

The following is a description of a structure of the part C. The part C is a pad portion, which is connected to a terminal of a flexible printed circuit board (FPCB) for supplying an electric signal from an exterior. The aforementioned buffer layer120is extended and formed on the deposition substrate110. The gate insulation layer140is extended and formed at an upper portion of the buffer layer120. The interlayer insulating layer160is formed at an upper portion of the gate insulation layer140. A second metal wiring170cis formed at an upper portion of the interlayer insulating layer160, and is made of the same material (or substantially the same material) as that of the source and drain electrodes170a. Here, the second metal wiring170ccan be any suitable metal wirings connected from a terminal to a data line, a scan line, or a power line. The first insulation layer180is formed on the second metal wiring170cto expose one section of the second metal wiring170c. Here, referring also toFIG. 6E, the part C includes the second region and the third region. The first insulation layer180is present in the second region, and insulation layers are absent in the third region.

Also,FIG. 5shows that, in the part C, the second metal wiring is formed by the same process (or only the same process) as that of the source and drain electrodes. However, the present invention is not thereby limited. For example, one embodiment of the present invention provides (or further provides) a metal wiring, which is formed during a formation of the gate electrode.

Hereinafter, a method of manufacturing an organic light emitting display according to an embodiment of the present invention will be explained below.

As illustrated earlier with reference to the aforementioned embodiments and referring toFIG. 6A, the buffer layer120, the semiconductor layer130, the gate insulation layer140, the gate electrode150, the interlayer insulating layer160, and the source and drain electrodes170aare sequentially formed on the deposition substrate110in the part A. Also, the first substrate in an intermediate manufacturing state including the buffer layer120, the gate insulation layer140, the interlayer insulating layer160, and the metal wirings170band170care provided inFIG. 6A.

Next, referring toFIG. 6B, the first insulation layer180and the second insulation layer190are formed at an entire surface of the first substrate. Here, inFIG. 6B, after the formation of the first insulation layer180, the second insulation layer190is continuously formed without a separate patterning process.

Subsequently, the second insulation layer190is patterned to have the first region, the second region, and the third region as described above with respect toFIG. 5. Here, in the first region, the second insulation layer190is formed to have a first pattern of a first thickness. In the second region, the second insulation layer190is formed to have a second pattern of a second thickness less than the first thickness. Further, in the third region, the second insulation layer190is removed to expose the first insulation layer180formed at a lower portion of the second insulation layer190(i.e., by removing the second insulation layer190in the third region, the first insulation layer180is exposed).

For example, the first region may be a region between the source electrode and the drain electrode of the part A, and the second region may be regions in the part B and the part C. The third region may be an upper portion of the source and drain electrodes of the part A, and/or an upper portion of a metal wiring of the part C.

Referring toFIG. 6C, the patterning step of the second insulation layer190can be achieved by exposing and developing the second insulation layer190using a half tone mask (e.g., mask50ofFIG. 3C) having different light-shielding degrees according to different regions.

That is, the half tone mask includes a light-shielding pattern corresponding to the first pattern, a partial light-shielding pattern corresponding to the second pattern, and an opening pattern corresponding to the third pattern. Accordingly, in one embodiment, the half tone mask causes the second insulation layer190to have different heights (or thickness) according to different exposure regions.

As discussed and illustrated above, since the first region of the second insulation layer190is not exposed to a developing light by a light-shielding pattern of the half tone mask, the second insulation layer190is not developed. Because a partial thickness of the second insulating layer190at the second region thereof is exposed to the developing light by the partial light-shielding pattern of the half tone mask, only a partially exposed part of an upper layer portion of the second insulation layer190is developed. No light-shielding patterns are used in the third region of the second insulation layer190. That is, since an entire thickness of the second insulation layer190at the third region is exposed to the developing light, the entire portion of the second insulation layer190at the third region is all developed. Here, a transmittance degree of the developing light is changed by controlling a thickness of a partial light-shielding pattern in the mask or an exposure time, which allows a thickness of the second insulation layer190to be adjusted (FIG. 6C).

In a next step, the first insulation layer180of the third region is etched. The first insulation layer180can be etched by a wet etching method and/or a dry etching method. As described above, the third region may be source and drain electrode regions of the part A, a terminal region of a pad portion contacting with an FPCB of the part C, and/or a terminal region of a pad portion contacting with a driver integrated circuit.

Accordingly, referring toFIG. 6Dand as a main process, a layer formed at a lower portion of the third region (for example, the source and drain electrodes of the part A and the metal wiring of the part C) is exposed to an outside. Furthermore, a via hole of an intermediate step penetrating the first insulation layer180and the second insulation layer190is formed in the part A (FIG. 6D).

In a next step, referring toFIG. 6E, the second insulation layer190is ashed. The second insulation layer190remaining at the second region is completely removed. At this time, since the second insulation layer190on the first region is removed to the same degree as the second region, a stepper portion of the second insulation layer190, (seeFIG. 6D) forming an inner surface of the via hole195(penetrating the first insulation layer180and the second insulation layer190), is removed, so that the inner surface of the via hole195is formed to have a smooth surface (seeFIG. 6E).

Thereafter, referring toFIG. 6F, organic light emitting diodes, each having a first electrode, an organic thin film, and a second electrode, are formed in the part A. The second substrate300is provided to face the first substrate and a sealing material is provided in the part B. Further, a terminal of the FPCB is connected to the part C (FIG. 6F).

While the present invention has been described in connection with certain exemplary embodiments, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims, and equivalents thereof. For example, although certain embodiments of the present invention were described as being formed (or obtained) with (or by) a positive photosensitive layer, other embodiments of the present invention can be formed with a negative photosensitive layer.