Apparatus and method for converting single-ended signals to a differential signal, and transceiver employing same

A communication circuit for an Ethernet or other network transceiver includes a first sub-circuit having a first input which receives a composite differential signal including first and second differential signal components, a second input which receives a differential replica transmission signal, and an output which provides a differential receive signal which comprises the composite differential signal minus the differential replica transmission signal. The communication circuit also includes a second sub-circuit which produces first and second single-ended replica transmission signals which together substantially comprise a replica of the first differential signal component of the composite differential signal and a third sub-circuit, which is coupled to the first and second sub-circuits, and which produces the differential replica transmission signal from the first and second single-ended replica transmission signals.

INCORPORATION BY REFERENCE OF RELATED APPLICATIONS

The present application is related to U.S. patent application Ser. No. 09/629,092, entitled “Active Resistive Summer for a Transformer Hybrid,” filed Jul. 31, 2000, and to U.S. patent application Ser. No. 09/920,240, entitled “Active Resistive Summer for a Transformer Hybrid,” filed concurrently herewith, both of which name Pierte Roo (the inventor of the present invention) and Sehat Sutardja as inventors, and each of which is hereby incorporated herein by reference.

BACKGROUND

1. Field of the Invention

The present invention relates generally to communication circuitry, and, more particularly, to a method and apparatus for use in a communication circuit, such as an Ethernet or other network transceiver, for converting single-ended signals to a differential signal.

2. Related Art

In communication transceivers, and particularly in Ethernet transceivers which are capable of transmitting and receiving data at 1000 megabits bits per second, communication is possible in a full-duplex mode. In other words, transmitting and receiving of data can occur simultaneously on a single communication channel. Implementation of such a full-duplex communication channel results in a composite signal (VTX) being present across the output terminals of the transceiver, the composite signal VTXhaving a differential transmission signal component and a differential receive signal component. In such a communication channel, the received signal (VRCV) is derived by simply subtracting the transmitted signal (VT) from the composite signal VTXthat is present at the transceiver output terminals. Hence, VRCV=VTX−VT.

This subtraction can be accomplished by generating a signal (referred to as a replica signal) which substantially replicates the transmitted signal, and canceling or subtracting the generated replica signal from the composite signal VTXat the output terminals of the transceiver. However, the replica signal is generated as two single-elided voltages, such as VTXR+and VTXR−, whereas the composite signal present at the output terminals of the transceiver is a differential signal. Consequently, in order to cancel the replica signal from the composite signal to thereby obtain the received signal, the two single-ended voltage signals must first be converted to a differential signal that can then be subtracted from the composite signal. This conversion, however, requires additional circuitry which adds to the cost and complexity of the transceiver.

SUMMARY

The present invention relates to a method and apparatus for converting the single-ended voltage signals in an Ethernet transceiver into a differential voltage signal, so that the differential voltage signal can be subtracted from the composite signal to produce an accurate receive signal.

According to one aspect of the present invention, a communication circuit is provided for an Ethernet transceiver. The communication circuit preferably includes a first sub-circuit having a first input which receives a composite differential signal including first and second differential signal components, a second input which receives a differential replica transmission signal, and an output which provides a differential receive signal which comprise the composite differential signal minus the differential replica transmission signal. The communication circuit also may include a second sub-circuit which produces first and second single-ended replica transmission signals which together substantially comprise a replica of the first differential signal component of the composite differential signal and a third sub-circuit, which is coupled to the first and second sub-circuits, and which produces the differential replica transmission signal from the first and second single-ended replica transmission signals.

The communication circuit may further include a fourth sub-circuit which is coupled to the first sub-circuit and which produces a time-shift between the first differential signal component of the composite differential signal and the second differential signal component of the composite differential signal. The fourth sub-circuit may comprise a delay circuit which introduces a delay in the first differential signal component relative to the second differential signal component and, more particularly, may introduce a predetermined delay in the differential replica transmission signal relative to the first and second single-ended replica transmission signals from which the differential replica transmission signal is produced. The delay introduced by the fourth sub-circuit preferably substantially matches the predetermined delay introduced by the third sub-circuit. Also preferably, the first and second single-ended replica transmission signals are Class B signals, and the differential replica transmission signal is preferably produced from the first and second single-ended Class B replica transmission signals with a single operational amplifier.

According to another aspect of the invention, a communication circuit for an Ethernet transceiver includes: summing means having a first input for receiving a composite differential signal including first and second differential signal components, a second input for receiving a differential replica transmission signal, and an output for providing a differential receive signal which comprises the composite differential signal minus the differential replica transmission signal; replicating means for producing first and second single-ended replica transmission signals which together substantially comprise a replica of the first differential signal component of the composite differential signal; and converting means coupled to the summing means and the replicating means for producing the differential replica transmission signal from the first and second single-ended replica transmission signals.

According to yet another aspect of the present invention, in an Ethernet transceiver a composite differential signal including first and second differential signal components is received at a first input, a differential replica transmission signal is received at a second input, the composite differential signal and the differential replica transmission signal are combined to thereby provide at an output a differential receive signal which comprises the composite differential signal minus the differential replica transmission signal. The differential replica transmission signal is developed from first and second single-ended replica transmission signals, which together substantially comprise a replica of the first differential transmission signal component of the composite differential signal.

DETAILED DESCRIPTION

While the present invention will be described with respect to an Ethernet controller card for use in general purpose computers, printers, routers, etc, it is to be understood that the present invention may find applicability in other fields such as Internet communications, telecommunications, or any processor-to-processor applications using full-duplex communication. Also, rather than being embodied in discrete card, the method and apparatus of the present invention alternatively may advantageously be incorporated directly into a computer “mother board” or any other suitable hardware configuration, if desired.

Communication in an Ethernet computer network is illustrated inFIG. 1. As shown, an Ethernet communication channel40comprises a first Ethernet transceiver42, a second Ethernet transceiver44, and a two-wire interconnection46between the first Ethernet transceiver42and the second Ethernet transceiver44. For example, the two-wire interconnection46may comprise a single twisted-pair of a Category 5 cable in accordance with IEEE gigabit transmission standard No. 802.3ab. As the Ethernet transceivers42and44may be substantially identical, only one of them is described herein.

The Ethernet transceiver42has a controlled current source48, which is used to inject into the Ethernet transceiver42a control current ITX, which corresponds to a signal to be transmitted from the Ethernet transceiver42to the Ethernet transceiver44. Ethernet transceiver42also has a termination resistance50and a first coil52of a center-tap transformer54. The center-tap transformer54also has a second coil56coupled to the two-wire interconnection46to provide signals transmitted by the first Ethernet transceiver42to the second Ethernet transceiver44. The center-tap transformer54serves to couple AC voltage signals between the Ethernet transceivers42and44while effectively decoupling the Ethernet transceiver42from the Ethernet transceiver44with respect to DC voltage signals. A pair of terminals58,60is provided to measure a voltage VTXpresent across the resistor50as a result of both signals transmitted by the Ethernet transceiver42and signals received by the Ethernet transceiver42from the Ethernet transceiver44via the two-wire interconnection46. The voltage VTXthus comprises a composite differential signal that includes a differential transmission signal component and a differential receive signal component.

As described in more detail below, the differential receive signal component of the composite differential signal VTXis determined in accordance with the present invention by subtracting a replica of the differential transmission signal component from the composite differential signal VTX. In the illustrated embodiment, the Ethernet transceiver42includes the termination resistance50, the center-tap transformer54, and an integrated circuit62containing communications circuitry for implementing the functionality of the Ethernet transceiver42.

An exemplary embodiment of such Ethernet transceiver communications circuitry is illustrated in the schematic ofFIG. 2. As shown inFIG. 2, an integrated circuit70has a pair of output terminals72,74, which are coupled to terminals76,78, respectively, of the winding52of the center-tap transformer54. Current in the winding52of the center-tap transformer54induces a proportional current in the secondary winding (not shown inFIG. 2) of the center-tap transformer54, and that proportional current is communicated over the two-wire interconnection46(FIG. 1) to another Ethernet transceiver coupled thereto. Also coupled between the output terminals72,74is a termination resistance80, which, in the illustrated embodiment ofFIG. 2, comprises a pair of termination resistors82,84. Preferably, the termination resistors82,84have resistance values to substantially match the 1000 ohm characteristic impedance of Category 5 cable in accordance with established standards for Ethernet connections.

The integrated circuit70also includes a transmission signal replicator86or other suitable circuitry for generating first aid second single-ended replica transmission signals VTXR+and VTXR−, which together substantially comprise a replica of the differential transmission component of the composite differential signal VTX. In the illustrated embodiment, the transmission signal replicator86comprises a pair of metal-oxide semiconductor (MOS) transistors88,90.

The transistor88is coupled between the output terminal72and one end of a resistor92, the other end of the resistor92being coupled to ground. Similarly, the transistor90is coupled between the output terminal74and one end of a resistor94, the other end of which is coupled to ground. The gate of each transistor88,90is coupled to and driven by the output of a respective operational amplifier96,98. The operational amplifier96has a non-inverting input100and an inverting input102. The inverting input102of the operational amplifier96receives a feedback signal from the junction of the source of the transistor88and the resistor92. Likewise, the operational amplifier98has a non-inverting input104and an inverting input106, which receives a feedback signal from the junction of the source of the transistor90and the resistor94.

A differential control voltage signal is applied between the non-inverting input100of the operational amplifier96and the non-inverting input104of the operational amplifier98. This differential control voltage signal, when subjected to the voltage-to-current conversion brought about by the transmission signal replicator86, provides the differential transmit signal component at the output terminals72,74. The feedback signal to the inverting input102of the operational amplifier96comprises a first single-ended replica transmit signal VTXR+, and the feedback signal to the inverting input106of the operational amplifier98comprises a second replica transmit signal VTXR−.

The single-ended replica transmit signals VTXR+and VTXR−are converted to a differential replica transmit signal by a converter circuit107, which comprises respective differential operational amplifiers108,110, each provided with suitable input and feedback resistors, as shown inFIG. 2. The outputs of the differential operational amplifiers108and110are coupled to a differential active summer112, which, in the embodiment ofFIG. 2, comprises a differential operational amplifier114with feedback resistors116,118

Because the differential operational amplifiers108and110introduce a delay into the replica transmissions signals VTXR+and VTXR−, the composite differential signal VTXis coupled to the differential active summer112through a further differential operational amplifier120arranged in a unity-gain configuration with input resistors122,124, output resistors126,128, and feedback resistors130,132. This unity-gain operational amplifier simply provides a delay in the composite differential signal VTXwhich preferably substantially matches the delay introduced in the replica transmission signals VTXR+and VTXR−by the operational amplifiers108and110. As will be readily appreciated by those of ordinary skill in the art, the various input, output, and feedback resistance values associated with the operational amplifiers108,110, and120may be selected to ensure that these delays are substantially equal to one another.

An alternative embodiment of a communications circuit in accordance with the present invention is shown in the schematic diagram ofFIG. 3. Because the transmission signal replicator86and the differential active summer112in the embodiment ofFIG. 3are identical to those in the embodiment ofFIG. 2, the details of those sub-circuits are omitted from the description of the embodiment ofFIG. 3. The embodiment ofFIG. 3, however, differs from the embodiment ofFIG. 2in the structure of the sub-circuit provided for converting the single-ended replica transmission signals VTXR+and VTXR−into a differential replica transmission signal VTXR.

More particularly, as shown inFIG. 3, a converter circuit140is coupled to the transmission signal replicator86and to the differential active summer112to produce the differential replica transmission signal VTXRfrom the single-ended replica transmission signals VTXR+and VTXR−. Just as in the embodiment ofFIG. 2, the embodiment ofFIG. 3includes a unity-gain differential operational amplifier150, which provides a delay in the differential composite signal VTXRto substantially match the delay introduced in the differential replica transmission signal VTXRby the converter circuit140. As will be appreciated by those of ordinary skill in the art, the differential operational amplifier150is preferably provided with input, output, and feedback resistors having resistance values which give the differential operational amplifier150a unity-gain value. Accordingly, the differential active summer112receives as input the delayed differential composite signal VTXand the delayed differential replica transmission signal VTXRand subtracts the latter signal from the former to produce at an output of the differential active summer112a differential receive signal which comprises the composite differential signal minus the differential replica transmission signal aid thus corresponds to the signal received by the transceiver70.

The simplification of the converter circuit140in the embodiment ofFIG. 3, compared to the converter circuit107in the embodiment ofFIG. 2, is made possible by the fact that the single-ended replica transmission signals VTXR+and VTXR−produced by the transmission signal replicator86in the illustrated embodiment are characterized by the feature that when VTXR+is asserted then VTXR−is zero (or ground), and when VTXR−is asserted then VTXR+is zero (or ground). It is because the single-ended replica transmission signals VTXR+and VTXR−have this characteristic that the two differential operational amplifiers108and110of the converter circuit107in the embodiment ofFIG. 2can be replaced by the single differential operational amplifier142in the converter circuit140of the embodiment ofFIG. 3.

This reduction in components in the converter circuit140provides not only substantial simplification of the integrated circuit70as a whole, but it also reduces the well-recognized manufacturing problem of component mismatch, such as between the two differential operational amplifiers109and110of the embodiment ofFIG. 2, for example, aid improves common-mode rejection, which, in turn, results in overall improved performance of the transceiver42.

The foregoing description is for the purpose of teaching those skilled in the art the best mode of carrying out the invention and is to be construed as illustrative only. Numerous modifications and alternative embodiments of the invention will be apparent to those skilled in the art in view of this description, and the details of the disclosed structure may be varied substantially without departing from the spirit of the invention. According, the exclusive use of all modifications within the scope of the appended claims is reserved.