E-fuse for use in semiconductor device

An e-fuse for use in a semiconductor device includes first and second electrodes; a gate metal coupling the first and second electrodes with each other; a first oxide layer formed under the gate metal; and a gate oxide layer formed between a bottom end of the gate metal and a top end of the first oxide layer.

CROSS-REFERENCES TO RELATED APPLICATION

The present application claims priority under 35 U.S.C. § 119(a) to Korean application number 10-2017-0119315, filed on Sep. 18, 2017, in the Korean Intellectual Property Office, which is incorporated herein by reference in its entirety.

BACKGROUND

1. Technical Field

Various embodiments generally relate to an e-fuse for use in a semiconductor device, and to a semiconductor device comprising the same.

2. Related Art

In general, semiconductor device fuses are used to achieve various purposes in the field of semiconductor technology. For example, fuses may be used in a repair process in which a failed memory cell is replaced with a redundancy memory cell, and may be used in a constant voltage generation circuit which tunes a voltage or a control circuit for selecting various modes and testing.

Such fuses may be divided into laser fuses and e-fuses depending on a cutting method. Between them, the e-fuses use a method of selectively cutting them by using current. Meanwhile, one of the requirements for improved fuse technology is to reduce the fuse area. In this regard, since a selection element which provides a program current occupies most of the fuse area, it may be required a technique for lowering program current affecting the size of the selection element to thereby reduce the fuse area.

SUMMARY

Various embodiments are directed to an e-fuse for use in a semiconductor device capable of being blown with low program current, thereby improving performance and reducing a fuse area.

In an embodiment, an e-fuse for use in a semiconductor device may include: first and second electrodes; a gate metal coupling the first and second electrodes with each other; a first oxide layer formed under the gate metal; and a gate oxide layer formed between a bottom end of the gate metal and a top end of the first oxide layer.

In an embodiment, an e-fuse for use in a semiconductor device may include: a first gate metal extending from a first electrode; a second gate metal extending from a second electrode to be contacted with the first gate metal; a first oxide layer formed under the first and second gate metals; and a gate oxide layer formed between bottom ends of the first and second gate metals and a top end of the first oxide layer.

In an embodiment, a semiconductor device comprising at least one e-fuse, the e-fuse comprising: first and second electrodes; a gate metal coupling the first and second electrodes with each other; a first oxide layer formed under the gate metal; and a gate oxide layer formed between a bottom end of the gate metal and a top end of the first oxide layer.

According to the embodiments, since the oxide layer is filled under a gate metal to reduce or prevent heat loss, the gate metal may be blown with low program current.

Further, since the gate metal may be blown with low program current, it is possible to reduce an area per bit of an e-fuse.

These and other features and advantages of the present invention will become apparent to those with ordinary skill in the art to which the present invention belongs from the following description in conjunction with the accompanying drawings.

DETAILED DESCRIPTION

Hereinafter, various embodiments will be described in detail with reference to the accompanying drawings to the extent that a person skilled in the art to which the embodiments pertain may easily practice the embodiments. Among the reference numerals presented in the drawings, like reference numerals denote like members.

In describing the present disclosure, when it is determined that the detailed description of the known related art may obscure the gist of the present disclosure, the detailed description thereof will be omitted.

Although the terms such as first and second may be used to describe various components, the components are not limited by the terms, and the terms are used only to distinguish components from other components.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the present invention. As used herein, singular forms are intended to include the plural forms as well, unless the context clearly indicates otherwise.

In the following embodiments, an n-type metal may be defined as a metal which is used in an NMOS (n-type metal oxide semiconductor) transistor, and a p-type metal may be defined as a metal which is used in a PMOS (p-type metal oxide semiconductor) transistor.

FIG. 1is a top view to assist in the explanation of an E-fuse for use in a semiconductor device, in accordance with a first embodiment of the present disclosure.

Referring toFIG. 1, an e-fuse100of a semiconductor device includes first and second electrodes10and20, a gate metal30, and a first oxide layer52.

The first electrode10may be referred to as a cathode, and the second electrode20may be referred to as an anode. Contacts12and22for applying a program voltage in the program of the e-fuse100may be formed on the first and second electrodes10and20. Programming the e-fuse includes flowing a program current through the gate metal30by applying a program voltage to any one of the first and second electrodes10and20and applying a ground voltage to any one of the other of the first and second electrodes10and20.

The gate metal30has a structure which electrically couples the first and second electrodes10and20, is disposed between the first and second electrodes10and20, and is formed of a material capable of being electrically programmed. For instance, the gate metal30may be formed of an n-type or a p-type metal which is used in an NMOS or a PMOS transistor. The gate metal30may be formed of a metallic material such as Al or may be formed of layers of TiN, Ti, Al and AlTiO. The gate metal30may be formed integrally with the first electrode10and the second electrode20.

The gate metal30may have an elongated bar shape extending in a first direction I-I′. The first and second electrodes also may each have an elongated bar shape extending in a second direction II-II′. The second direction II-II′ may be perpendicular to the first direction I-I′.

The first oxide layer52is formed under the gate metal30with a gate oxide layer60disposed therebetween. The first oxide layer52may also be formed under the first and second electrodes10and20with the gate oxide layer60disposed therebetween. The first oxide layer52may reduce or prevent heat loss during the programming of the e-fuse100.

The gate oxide layer60(seeFIG. 2) may be formed between the gate metal30and the first oxide layer52, and between the first and second electrodes and the first oxide layer52. The gate oxide layer60may break down during the programming of the e-fuse100.

As such, the e-fuse100of a semiconductor device may include the first and second electrodes10and20for applying the program voltage, the gate metal30which electrically couples the first and second electrodes10and20, the gate oxide layer60, and the first oxide layer52which is formed under the first electrode10to under the second electrode20.

In the e-fuse100of a semiconductor device configured as mentioned above, when program voltage is applied to the second electrode20and the ground voltage is applied to the first electrode10, the program current flows through the gate metal30due to the potential difference of the first and second electrodes10and20, and electro-migration, thermo-migration and melting phenomena are induced in the gate metal30by the program current. As a result, a void may be formed in the gate metal30and resistance may increase.

Also, in the e-fuse100of a semiconductor device, the gate metal30and a gate oxide layer60(seeFIG. 2) react with each other or the dielectric constant characteristic of the gate oxide layer60may change due to the high temperature of the gate metal30in the programming. Through this, the metal current of the e-fuse100may change significantly before and after the programming.

A driving force by the electro-migration induced in the gate metal30may be changed by changing the sectional area of the gate metal30. While it is illustrated inFIG. 1that the gate metal30has the same sectional area between the first and second electrodes10and20and extends in one direction, this is only for the sake of convenience in explanation, and it is to be noted that the embodiment is not limited thereto. The gate metal30may include a bent portion in correspondence to the positions of the first and second electrodes10and20, and may be formed to have a different sectional area. The bent portion or the variable sectional area may have an advantage of enabling the blowing of the gate metal30by a lower program current.

When program current flows through the gate metal30, Joule's heat may be generated in the gate metal30. The Joule's heat induced by the program current may have a nonuniform temperature distribution in the gate metal30. The non-uniform temperature distribution in the gate metal30may have a highest temperature at the center portion of the gate metal30. The nonuniform temperature distribution may induce the thermo-migration of atoms in the gate metal30. The thermo-migration may include a thermo-migration in which atoms migrate in an anode direction from the center portion of the gate metal30and a thermo-migration in which atoms migrate in a cathode direction from the center portion of the gate metal30.

In this way, when program current flows through the gate metal30, electro-migration, thermo-migration and melting phenomena are induced in the gate metal30, and a driving force by the electro-migration, thermo-migration and melting phenomena blows the gate metal30. If the gate metal30is blown, the metal current of the e-fuse100may change significantly before and after the programming. Also, since the first oxide layer52is filled under the gate metal30to reduce or prevent heat loss, it is possible to blow the gate metal30with low program current. Therefore, since the gate metal30is blown with low program current, it is possible to reduce an area per bit of the e-fuse100.

A silicon nitride layer70and a second oxide layer54shown inFIG. 2are not shown in the top view ofFIG. 1to facilitate the understanding of the structure of the present embodiment. As shown inFIG. 2, the silicon nitride layer70may be formed on the gate metal30and the first and second electrodes10and20, and the second oxide layer54may be formed on the silicon nitride layer70and the first oxide layer52.

FIG. 2is a cross-sectional view taken along the line I-I′ ofFIG. 1.

Referring toFIG. 2, the first oxide layer52is formed under the gate metal30, and the gate oxide layer60is formed between the gate metal30and the first oxide layer52. The first oxide layer52is used for reducing or preventing heat loss in the programming of the e-fuse100. The gate oxide layer60may react with the gate metal30or be changed in its dielectric constant characteristic due to a high temperature in the programming. For instance, the gate oxide layer60may be formed of HfO2.

The silicon nitride layer70may be formed on the gate metal30, and the second oxide layer54is formed on the silicon nitride layer70. For instance, the silicon nitride layer70may be formed of SiN or SiCN.

FIG. 3is a view to assist in the explanation of the change of metal current when programming the e-fuse.FIG. 4is a graph to assist in the explanation of the change of the metal current before and after program.

Referring toFIGS. 3 and 4, in the e-fuse100of a semiconductor device, when program voltage is applied to the second electrode20and the ground voltage is applied to the first electrode10, program current flows through the gate metal30due to the potential difference of the first and second electrodes10and20, and electro-migration, thermo-migration and melting phenomena are induced in the gate metal30by the program current. As a result, a void may be formed in the gate metal30and resistance may increase.

In the case where fusing proceeds in a state where a current density is relatively high in the programming of the e-fuse100, a void may be formed in the center of the gate metal30as the gate metal30is melted at the center thereof having a highest temperature. In the case where fusing proceeds in a state where a current density is relatively low in the programming of the e-fuse100, a void may be formed in a portion of the gate metal30close to the second electrode20due to electro-migration and thermo-migration phenomena.

In this regard, the metal current of the e-fuse100may change significantly before and after the programming. If a void is formed in the gate metal30, gate resistance may increase and thus a voltage actually applied to the gate may decrease, and the metal current may decrease. Moreover, as the characteristics of the gate metal30and the gate oxide layer60are changed by the heat generated in the programming of the gate metal30, the metal current may change.

FIG. 5is a top view of an e-fuse100of a semiconductor device, in accordance with a second embodiment of the present disclosure.FIG. 6is a cross-sectional view taken along the line I-I′ ofFIG. 5. A silicon nitride layer70and a second oxide layer54shown inFIG. 6are not shown in the top view ofFIG. 5to facilitate the understanding of the structure of the present embodiment. As shown inFIG. 6, the silicon nitride layer70may be formed on the gate metal30and first and second electrodes10and20, and the second oxide layer54may be formed on the silicon nitride layer70, the semiconductor layer40and the first oxide layer52.

Referring toFIGS. 5 and 6, the e-fuse100of a semiconductor device may include the first and second electrodes10and20, the gate metal30, the semiconductor layer40, the gate oxide layer60, and the first oxide layer52. The descriptions made above with reference toFIG. 1will replace descriptions for components the same as those of the first embodiment.

The first oxide layer52is formed under the gate metal30with the gate oxide layer disposed therebetween. The first oxide layer52has a smaller length than the metal gate30in the first direction I-I′, and is positioned in correspondence to the center portion of the gate metal30. Hence, side portions of the metal gate30(also referred to herein after as the sides of the metal gate30) extend further in the first direction I-I′ than the first oxide layer52. The first oxide layer52may reduce or prevent heat loss in the programming of the e-fuse100.

The semiconductor layer40is formed under the gate metal30and on both sides of the first oxide layer52, with the gate oxide layer60disposed therebetween. Hence the semiconductor layer overlaps with the first and second electrodes10and20and the sides of the metal gate30.

The gate oxide layer60may be formed between the bottom end of the gate metal30and the top end of the first oxide layer52, and also between the top end of the semiconductor layer40and the bottom ends of the first and second electrodes. The gate oxide layer60may react with the gate metal30or be changed in its dielectric constant characteristic due to a high temperature in the programming, and thereby, may break down. For instance, the gate oxide layer60may be formed of HfO2.

The silicon nitride layer70may be formed on the gate metal30, and the second oxide layer54may be formed on the silicon nitride layer70. For instance, the silicon nitride layer70may be formed of SiN or SiCN.

The e-fuse100may include the first and second electrodes10and20for applying a program voltage, the gate metal30which electrically couples the first and second electrodes10and20, the first oxide layer52which is formed under the gate metal30in correspondence to the center portion of the gate metal30, and the semiconductor layer40which is formed on both sides of the first oxide layer52. The e-fuse100may also include a gate oxide layer60disposed between the first oxide layer52and the metal gate30, and between the semiconductor layer40and the first and second electrodes10and20and the sides of the metal gate30. In the case of programming the gate metal30by forming an oxide under the center portion of the gate metal30corresponding to a fuse link portion, forming portions close to a cathode electrode and an anode electrode by Si and applying voltages to the cathode electrode and the anode electrode, the center portion of the gate metal30retains a high temperature due to the presence of the oxide having low heat conductivity, and the portions close to the cathode and anode electrodes retains a low temperature due to the presence of Si having high heat conductivity. As a consequence, as a temperature gradient is maximized and thus an atomic flux divergence is maximized, the e-fuse100according to the present embodiment may be easily cut.

In the e-fuse100configured as mentioned above, when a program voltage is applied to the second electrode20and a ground voltage is applied to the first electrode10, program current flows through the gate metal30due to the potential difference of the first and second electrodes10and20, and electro-migration and thermo-migration phenomena are induced in the gate metal30by the program current. As a result, a void may be formed in the gate metal30and resistance may increase.

Also, in the e-fuse100for a semiconductor device, the gate metal30and the gate oxide layer60may react with each other or the dielectric constant characteristic of the gate oxide layer60may change due to the high temperature of the gate metal30in the programming. Through this, the metal current of the e-fuse100may change significantly before and after the programming.

In this way, when program current flows through the gate metal30, electro-migration, thermo-migration and melting phenomena are induced in the gate metal30, and a driving force by the electro-migration and thermo-migration phenomena blows the gate metal30. If the gate metal30is blown, the metal current of the e-fuse100may change significantly before and after the programming of the e-fuse100.

According to the present embodiment, since the first oxide layer52is filled under the gate metal30to reduce or prevent heat loss, it is possible to blow the gate metal30with a low program current. Therefore, since the gate metal30is blown with low program current, it is possible to reduce the area per bit of the e-fuse100.

FIG. 7is a top view of an e-fuse100for a semiconductor device, in accordance with a third embodiment of the present disclosure.FIG. 8is a cross-sectional view taken along the line I-I′ ofFIG. 7. A silicon nitride layer70and a second oxide layer54shown inFIG. 8are not shown in the top view ofFIG. 7to facilitate the understanding of the structure of the present embodiment. As shown inFIG. 8, the silicon nitride layer70may be formed on a gate metal30and first and second electrodes10and20, and the second oxide vi layer54may be formed on the silicon nitride layer70and a first oxide layer52.

Referring toFIGS. 7 and 8, the e-fuse100for a semiconductor device may include the first and second electrodes10and20, first and second gate metals32and34, and the first oxide layer52. The e-fuse100may also include gate oxide layer60.

The first and second gate metals32and34have a structure which electrically couples the first and second electrodes10and20, are disposed between the first and second electrodes10and20, and are formed of materials capable of being electrically programmed.

The first and second gate metals32and34may be formed of different metals or may be formed of one or more different metallic materials. For instance, the first gate metal32may be formed of a metallic material such as Al, and the second gate metal34may be formed of a layer of TiN, Ti, Al and AlTiO or a combination thereof. Alternatively, the first and second gate metals32and34may be formed of a layer of TiN, Ti, Al and AlTiO or a combination thereof provided that the first and second metal gates32and34have different specific gravities. The first gate metal32may be formed integrally with the first electrode10, and the second gate metal34may be formed integrally with the second electrode20. The first and second metal gates32and34may be electrically coupled. For example, one end of the first metal gate coupled to one end of the second metal gate34, or alternatively, the first and second gate metals32and34may partially overlap while contacting with each other. The extent of the overlap may differ by design.

The first oxide layer52is formed under the first and second gate metals32and34and under the first and second electrodes10and20. The first oxide layer52may reduce or prevent heat loss in the programming of the e-fuse100.

The gate oxide layer60may be formed between the bottom end of the gate metal30and the top end of the first oxide layer52. The gate oxide layer may also be formed between the bottom ends of the first and second electrodes10and20and the top end of the first oxide layer52.

The gate oxide layer60may react with the gate metal30or be changed in its dielectric constant characteristic due to a high temperature in the programming of the e-fuse100, and thereby, may break down.

The e-fuse100for a semiconductor device according to an embodiment, may include the first and second electrodes10and20for applying a program voltage, the first gate metal32which extends from the first electrode10, the second gate metal34which extends from the second electrode20to be brought into contact with the first gate metal32, and the first oxide layer52which is formed from under the first electrode10to under the second electrode20. The e-fuse may further include, the gate oxide layer60disposed between the first oxide layer52and the gate metal30and between the first oxide layer52and the first and second electrodes10and20.

In the e-fuse100for a semiconductor device configured as mentioned above, the first oxide layer52is filled under the gate metal30to prevent heat loss, hence, it is possible to blow the gate metal30with a low program current. Therefore, since the gate metal30can be blown with a low program current, it is possible to reduce the area per bit of the e-fuse100.

FIG. 9is a top view of an e-fuse100of a semiconductor device, in accordance with a fourth embodiment of the present disclosure.FIG. 10is a cross-sectional view taken along the line ofFIG. 9. A silicon nitride layer70and a second oxide layer54shown inFIG. 10are not shown in the top view ofFIG. 9to facilitate the understanding of the structure of the present embodiment. As shown inFIG. 10, the silicon nitride layer70may be formed on gate metal30and first and second electrodes10and20, and the second oxide layer54may be formed on the silicon nitride layer70, the semiconductor layer40and the first oxide layer52.

Referring toFIGS. 9 and 10, the e-fuse100of a semiconductor device may include the first and second electrodes10and20, first and second gate metals32and34, the semiconductor layer40, gate oxide layer60, and the first oxide layer52. The descriptions made above with reference toFIG. 7will replace descriptions for components the same as those of the third embodiment.

The first oxide layer52is formed under the gate metal30with the gate oxide layer60disposed therebetween. The first oxide layer52may be smaller in length in the first direction I-I′ than the gate metal30and may be positioned in correspondence to the center portion of the gate metal30so that side portions of gate metal30(also referred to as the sides of the gate metal30) may extend further in the first direction I-I′ than the first oxide layer52. The first oxide layer52may reduce or prevent heat loss in the programming of the e-fuse100.

The semiconductor layer40is formed under the first and second gate metals32and34and on both sides of the first oxide layer52.

The gate oxide layer60may be formed between the bottom ends of the gate metal30and the first and second electrodes10and20and the top ends of the first oxide layer52and of the semiconductor layer40. The gate oxide layer60may react with the gate metal30or be changed in its dielectric constant characteristic due to a high temperature in the programming, and thereby, may break down. For instance, the gate oxide layer60may be formed of HfO2.

The silicon nitride layer70may be formed on the gate metal30, and the second oxide layer54is formed on the silicon nitride layer70. For instance, the silicon nitride layer70may be formed of SiN or SiCN.

As such, the e-fuse100for a semiconductor device may include the first and second electrodes10and20for applying a program voltage, the first gate metal32which extends from the first electrode10, the second gate metal34which extends from the second electrode20to be brought into contact with the first gate metal32, the first oxide layer52which is formed under the gate metal30in correspondence to the center portion of the gate metal30, and the semiconductor layer40which is formed on both sides of the first oxide layer52in correspondence to the bottoms of the first and second electrodes10and20. The e-fuse may further include the gate oxide layer60.

In the case of programming the gate metal30by forming an oxide under the center portion of the gate metal30corresponding to a fuse link portion, forming portions close to a cathode electrode and an anode electrode by Si and applying voltages to the cathode electrode and the anode electrode, the center portion of the gate metal30retains a high temperature due to the presence of the oxide having low heat conductivity, and the portions close to the cathode and anode electrodes retains a low temperature due to the presence of Si having high heat conductivity. As a consequence, as a temperature gradient is maximized and thus an atomic flux divergence is maximized, the e-fuse100according to the present embodiment may be easily cut.

In the e-fuse100of a semiconductor device configured as mentioned above, when program voltage is applied to the second electrode20and a ground voltage is applied to the first electrode10, program current flows through the gate metal30due to the potential difference of the first and second electrodes10and20, and electro-migration, thermo-migration and melting phenomena are induced in the gate metal30by the program current. As a result, a void may be formed in the gate metal30and resistance may increase.

Also, in the e-fuse100of a semiconductor device, the gate metal30and the gate oxide layer60may react with each other or the dielectric constant characteristic of the gate oxide layer60may change due to the high temperature of the gate metal30in the programming. Through this, the metal current of the e-fuse100may change significantly before and after the programming.

According to the present embodiment, first oxide layer52is filled under the gate metal30to reduce or prevent heat loss, thus making it possible to blow the gate metal30with a low program current. Therefore, since the gate metal30is blown with low program current, it is possible to reduce an area per bit of the e-fuse100.