Solar cell and solar cell panel including the same

Disclosed is a solar cell including a semiconductor substrate, a first conductive area formed on one surface of the semiconductor substrate, a second conductive area formed on a remaining surface of the semiconductor substrate, a first electrode connected to the first conductive area, and a second electrode connected to the second conductive area. The second electrode includes a pad portion and an electrode portion that include different conductive materials as main components. The pad portion includes at least one pad extending in a given direction, the wire being attached to the pad. The electrode portion and the pad are spaced apart from each other in the given direction so as to form a spacer therebetween.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims the priority benefit of Korean Patent Application No. 10-2015-0106814, filed on Jul. 28, 2015 in the Korean Intellectual Property Office, the content of which is incorporated herein by reference.

BACKGROUND OF THE INVENTION

Field of the Invention

Embodiments of the present invention relate to a solar cell and a solar cell panel including the same, and more particularly, to a solar cell having an improved electrode structure and a solar cell panel including the same.

Description of the Related Art

Recently, due to depletion of existing energy resources, such as oil and coal, interest in alternative sources of energy to replace the existing energy resources is increasing. Most of all, solar cells are popular next generation cells to convert sunlight into electrical energy.

A plurality of solar cells is connected to each other in series or in parallel using ribbons, and is manufactured into a solar cell panel via packaging, which is a process for protecting the solar cells. Because the solar cell panel needs to perform electricity generation for a long term in various environments, considerable long-term reliability is required.

When the solar cells are connected to each other using the ribbons, electrodes in the solar cells need to have a structure suitable for attachment of the ribbons. Otherwise, the attachment between the ribbons and the electrodes may be deteriorated, or manufacturing costs of the electrodes may increase.

SUMMARY OF THE INVENTION

Therefore, the embodiments of the present invention have been made in view of the above problems, and it is an object of the embodiments of the present invention to provide a solar cell and a solar cell panel including the same, which may achieve improved efficiency, productivity, and attachment of ribbons.

According to one aspect of the present invention, the above and other objects can be accomplished by the provision of a solar cell including a semiconductor substrate, a first conductive area formed on one surface of the semiconductor substrate, a second conductive area formed on a remaining surface of the semiconductor substrate, a first electrode connected to the first conductive area, and a second electrode connected to the second conductive area, wherein the second electrode includes a pad portion and an electrode portion that include different conductive materials as main components, wherein the pad portion includes at least one pad extending in a given direction, and wherein the electrode portion and the pad are spaced apart from each other in the given direction so as to form a spacer therebetween.

According to another aspect of the present invention, there is provided a solar cell panel including a plurality of solar cells, and a wire for interconnecting two neighboring solar cells among the solar cells, wherein each of the solar cells includes a semiconductor substrate, a first conductive area formed on one surface of the semiconductor substrate, a second conductive area formed on a remaining surface of the semiconductor substrate, a first electrode connected to the first conductive area, and a second electrode connected to the second conductive area, wherein the second electrode includes a pad portion and an electrode portion that include different conductive materials as main components, wherein the pad portion includes at least one pad extending in a given direction, the wire being attached to the pad, and wherein the electrode portion and the pad are spaced apart from each other in the given direction so as to form a spacer therebetween.

DETAILED DESCRIPTION OF THE EMBODIMENTS

Reference will now be made in detail to the embodiments of the present invention, examples of which are illustrated in the accompanying drawings. However, it will be understood that the present invention should not be limited to the embodiments and may be modified in various ways.

In the drawings, to clearly and briefly explain the embodiments of the present invention, illustration of elements having no connection with the description is omitted, and the same or similar elements are designated by the same reference numerals throughout the specification. In addition, in the drawings, for a more clear explanation, the dimensions of elements, such as thickness, width, and the like, may be exaggerated or reduced, and thus the thickness, width, and the like of the embodiments of the present invention are not limited to the illustration of the drawings.

In the entire specification, when an element is referred to as “including” another element, the element should not be understood as excluding other elements so long as there is no special conflicting description, and the element may include at least one other element. In addition, it will be understood that, when an element such as a layer, film, region or substrate is referred to as being on another element, it can be directly on the other element or intervening elements may also be present. On the other hand, when an element such as a layer, film, region or substrate is referred to as being “directly on” another element, this means that there are no intervening elements therebetween.

Hereinafter, a solar cell and a solar cell panel including the same according to the embodiments of the present invention will be described in detail with reference to the accompanying drawings. Here, the terms “first”, “second”, etc., are merely used in order to distinguish elements from each other, and the embodiments of the present invention are not limited thereto.

FIG. 1is a perspective view illustrating a solar cell panel according to an embodiment of the present invention, andFIG. 2is a sectional view taken along line II-II ofFIG. 1.

Referring toFIGS. 1 and 2, the solar cell panel according to the present embodiment, designated by reference numeral100, includes a plurality of solar cells150, and wires142for electrically interconnecting the solar cells150. Further, the solar cell panel100includes a sealing member130for surrounding and sealing the solar cells150and the wires142for interconnecting the same, a front substrate110disposed on the front surface of the solar cells150above the sealing member130, and a back substrate120disposed on the back surface of the solar cells150above the sealing member130. This will be described below in more detail.

First, each of the solar cells150may include a photoelectric converter for converting sunlight into electrical energy, and an electrode electrically connected to the photoelectric converter for collecting and transmitting current. In addition, the solar cells150may be electrically interconnected in series and/or in parallel by the wires142. Specifically, each wire142electrically interconnects two neighboring solar cells150among the solar cells150.

In addition, bus ribbons145interconnect alternate ends of the wires142, which connect the solar cells150to one another in rows (in other words, constituting solar cell strings). The bus ribbons145may be located on the ends of the solar cell strings so as to cross the solar cell strings. The bus ribbons145may interconnect the solar cell strings adjacent to each other, or may connect the solar cell string(s) to a junction box, which prevents the backflow of current. The material, shape, connection structure, and the like of the bus ribbons145may be altered in various ways, and the embodiment of the present invention is not limited as to them.

The sealing member130may include a first sealing member131disposed on the front surface of the solar cells150interconnected by the wires142, and a second sealing member132disposed on the back surface of the solar cells150. The first sealing member131and the second sealing member132prevent the introduction of moisture and oxygen, and realize a chemical bond between respective elements of the solar cell panel100. The first and second sealing members131and132may be formed of an insulation material having light-transmissive and adhesive properties. In one example, the first sealing member131and the second sealing member132may be formed of ethylene vinyl acetate (EVA) copolymer resin, polyvinyl butyral, silicone resin, ester-based resin, or olefin-based resin. Through, for example, a lamination process using the first and second sealing members131and132, the back substrate120, the second sealing member132, the solar cells150, the first sealing member131, and the front substrate110may be integrated with one another so as to construct the solar cell panel100.

The front substrate110is disposed on the first sealing member131and configures the front surface of the solar cell panel100. The back substrate120is disposed on the second sealing member132and configures the back surface of the solar cell panel100. Each of the front substrate110and the back substrate120may be formed of an insulation material capable of protecting the solar cells150from external shocks, moisture, ultraviolet light, and the like. In addition, the front substrate110may be formed of a light-transmitting material capable of transmitting light, and the back substrate120may be configured as a sheet formed of a light-transmitting material, a material not transmitting light, or a material reflecting light. In one example, the front substrate110may be configured as a glass substrate, and the back substrate120may be a Tedlar/PET/Tedlar (TPT) substrate, or may include a polyvinylidene fluoride (PVDF) resin layer formed on at least one surface of a base film (e.g. a polyethyleneterephthlate (PET) film).

However, the embodiment of the present invention is not limited thereto. Thus, the first and second sealing members131and132, the front substrate110, or the back substrate120may include any of various materials excluding the above-described materials, and may have any of various shapes. For example, the front substrate110or the back substrate120may have any of various shapes (e.g. a substrate, film, or sheet), or may include any of various materials.

One example of the solar cell included in the solar cell panel and the wires connected thereto according to the embodiment of the present invention will be described below in detail with reference toFIG. 3.

FIG. 3is a partial sectional view illustrating one example of the solar cell included in the solar cell panel ofFIG. 1and the wires connected thereto.

Referring toFIG. 3, each solar cell150includes a semiconductor substrate160, conductive areas20and30formed on or over the semiconductor substrate160, and electrodes42and44connected to the conductive areas20and30. The conductive areas20and30may include a first conductive area20of a first conductive type and a second conductive area30of a second conductive type. The electrodes42and44may include a first electrode42connected to the first conductive area20and a second electrode44connected to the second conductive area30. The solar cell150may further include, for example, first and second passivation films22and32, and an anti-reflection film24.

The semiconductor substrate160may be formed of crystalline semiconductors including a single semiconductor material (e.g. group-IV elements). In one example, the semiconductor substrate160may be formed of monocrystalline or polycrystalline semiconductors (e.g. monocrystalline or polycrystalline silicon). More particularly, the semiconductor substrate160may be formed of monocrystalline semiconductors (e.g. a monocrystalline semiconductor wafer, and more specifically, a monocrystalline silicon wafer). The use of the semiconductor substrate10having high crystallinity and thus low defects ensures excellent electrical properties of the solar cell150.

The front surface and/or the back surface of the semiconductor substrate160may be subjected to texturing so as to have protrusions. The protrusions may have a pyramidal shape having irregular sizes, and the outer surface of the protrusions may be (111) faces of semiconductors of the semiconductor substrate160. When the roughness of, for example, the front surface of the semiconductor substrate10is increased by the protrusions formed on the front surface via texturing, the reflectance of light introduced through the front surface of the semiconductor substrate160may be reduced. Accordingly, the quantity of light, which reaches the pn junction formed by a base area10and the first or second conductive area20or30, may be increased, which may minimize the loss of light. The present embodiment illustrates that protrusions are formed on each of the front surface and the back surface of the semiconductor substrate160. However, the embodiment of the present invention is not limited thereto. Accordingly, protrusions may be formed on at least one of the back surface and the front surface of the semiconductor substrate160, and may optionally not be formed on the front surface and the back surface of the semiconductor substrate160.

In the present embodiment, the semiconductor substrate160may include the base area10, which includes a first or second conductive dopant at a relatively low doping concentration, thus being of a first or second conductive type. At this time, the base area10of the semiconductor substrate160may have a lower doping concentration, higher resistance, or lower carrier concentration than one of the first and second conductive areas20and30, which is of the same conductive type as the base area10. In one example, in the present embodiment, the base area10may be of the second conductive type.

In addition, the semiconductor substrate160may include the first conductive area20and the second conductive area30. In the present embodiment, the base area10and the conductive areas20and30, which constitute the semiconductor substrate160, are areas, which have the crystalline structure of the semiconductor substrate160, are of different conductive types, and have different doping concentrations. For example, an area of the semiconductor substrate160, which includes a first conductive dopant and thus is of a first conductive type, may be defined as the first conductive area20, an area of the semiconductor substrate160, which includes a second conductive dopant at a low doping concentration and thus is of a second conductive type, may be defined as the base area10, and an area of the semiconductor substrate160, which includes the second conductive dopant at a higher doping concentration than that in the base area10and thus is of the second conductive type, may be defined as the second conductive area30.

In the present embodiment, the first conductive area may be formed throughout the front surface of the semiconductor substrate160. Here, “formed throughout” includes not only a physically complete formation, but also formation with inevitably excluded parts. In this way, the first conductive area20may be formed to have a sufficient area without separate patterning. In addition,FIG. 3illustrates that the first conductive area20has a homogeneous structure having a uniform doping concentration. However, the embodiment of the present invention is not limited thereto. Thus, in another embodiment, the first conductive area20may have a selective structure. In the selective structure, a portion of the first conductive area20proximate to the first electrode42may have a high doping concentration and low resistance, and the remaining portion of the first conductive area20may have a low doping concentration and high resistance.

In addition, the second conductive area30may have a local structure, which is locally formed so as to correspond to a portion of the second electrode44. Thereby, the second conductive area30may be formed via a simple process. This will be described later in more detail. However, the embodiment of the present invention is not limited thereto, and the second conductive area30may have any of various structures, such as a homogeneous structure or a selective structure.

The first conductive area20may configure an emitter area, which forms a pn junction with the base area10. The second conductive area30may configure a back-surface field area, which forms a back-surface field. The back-surface field area serves to prevent the loss of carriers due to recombination on the surface of the semiconductor substrate160(more accurately, the back surface of the semiconductor substrate160).

In the present embodiment, the conductive areas20and are doped areas, which are formed by doping some inner areas of the semiconductor substrate160with dopants, thus constituting a portion of the semiconductor substrate160. However, the embodiment of the present invention is not limited thereto. Accordingly, at least one of the first conductive area20and the second conductive area30may be configured as an amorphous, microcrystalline or polycrystalline semiconductor layer, which is a separate layer over the semiconductor substrate160. Various alterations are possible.

The first conductive dopant, included in the first conductive area20, may be an n-type or p-type dopant, and the second conductive dopant, included in the base area10and the second conductive area30, may be a p-type or n-type dopant. The p-type dopant may be a group-III element, such as boron (B), aluminum (Al), gallium (ga), or indium (In), and the n-type dopant may be a group-V element, such as phosphorus (P), arsenic (As), bismuth (Bi), or antimony (Sb). The second conductive dopant in the base area10and the second conductive dopant in the second conductive area30may be the same material, or may be different materials.

In one example, the first conductive area20may be of an n-type, and the base area10and the second conductive area30may be of a p-type. As such, the second conductive area30may be easily formed. However, the embodiment of the present invention is not limited thereto. The base area10and the second conductive area30may be of a p-type, and the first conductive area20may be of an n-type.

Insulation films, such as the first and second passivation films22and32and anti-reflection film24, may be formed over the surfaces of the semiconductor substrate160. The insulation films may be configured as undoped insulation films, which include no dopant.

More specifically, the first passivation film22may be formed over (e.g. in contact with) the front surface of the semiconductor substrate160, more accurately, over the first conductive area20formed on the semiconductor substrate160, and the anti-reflection film24may be formed over (e.g. in contact with) the first passivation film22. In addition, the second passivation film32may be formed over (e.g. in contact with) the back surface of the semiconductor substrate160, more accurately, over the second conductive area30formed on the semiconductor substrate160.

The first passivation film22and the anti-reflection film24may substantially be formed throughout the front surface of the semiconductor substrate160excluding a portion corresponding to the first electrode42(more accurately, a portion provided with a first opening102). In the present embodiment, the second passivation film32may be formed on a portion of the semiconductor substrate160, which corresponds to a portion of the second electrode44. The second passivation film32will be described later in more detail.

The first and second passivation films22and32come into contact with the first and second conductive areas20and30for passivation of defects present in the surface or the bulk of the conductive areas20and30. As such, it is possible to increase the open-circuit voltage of the solar cell150by removing recombination sites of minority carriers. The anti-reflection film24reduces the reflectance of light introduced into the front surface of the semiconductor substrate160. This may increase the quantity of light, which reaches the pn junction formed at the interface of the base area10and the first conductive area20. Thereby, the short-circuit current Isc of the solar cell150may be increased. In conclusion, the passivation films22and32and the anti-reflection film24may increase the open-circuit voltage and the short-circuit current of the solar cell150, thereby improving the efficiency of the solar cell150.

In one example, the passivation films22and32or the anti-reflection film24may include a single film or multiple films in the form of a combination of two or more films selected from the group consisting of a silicon nitride film, silicon nitride film containing hydrogen, silicon oxide film, silicon oxide nitride film, aluminum oxide film, MgF2, ZnS, TiO2, and CeO2. In one example, the first or second passivation film22or32may include a silicon oxide film or silicon nitride film having a fixed positive charge when the conductive areas20and30are of an n-type, and may include an aluminum oxide film having a fixed negative charge when the conductive areas20and30are of a p-type. In one example, the anti-reflection film24may include silicon nitride.

However, the embodiment of the present invention is not limited thereto, and the passivation films22and32and the anti-reflection film24may include various materials. In addition, the stacking structure of the insulation films stacked over the front surface and/or the back surface of the semiconductor substrate160may be altered in various ways. For example, the insulation films may be stacked one above another in a stacking sequence different from the above-described stacking sequence. Alternatively, at least one of the first and second passivation films22and32and the anti-reflection film24may be omitted, or other insulation films excluding the first and second passivation films22and32and the anti-reflection film24may be provided. Various other alterations are possible.

The first electrode42is electrically connected to the first conductive area20through the first opening102, which is formed in the insulation films disposed on the front surface of the semiconductor substrate160(e.g. the first passivation film22and the anti-reflection film24). The second electrode44is electrically connected to the second conductive area30through a second opening104, which is formed in the insulation film disposed on the back surface of the semiconductor substrate110(e.g. the second passivation film32). In one example, the first electrode42may come into contact with the first conductive area20, and the second electrode44may come into contact with the second conductive area30.

The first and second electrodes42and44may be formed of various materials (e.g. metal materials) so as to have various shapes. The shapes of the first and second electrodes42and44will be described below with reference toFIG. 2.

As such, in the present embodiment, the first electrode42of the solar cell150may have a given pattern to increase the quantity of light introduced into the front surface, which is the surface to which a relatively large amount of light is introduced. In addition, the second electrode44may be formed throughout the back surface, which is the surface to which a relatively small amount of light is introduced, which may increase reflectance efficiency. Thereby, the quantity of light used in the solar cell150is increased, which may contribute to increase in the efficiency of the solar cell150.

The solar cell150described above is electrically connected to a neighboring solar cell150by the wire142, which is located over (e.g. in contact with) the first electrode42or the second electrode44. This will be described below in more detail with reference toFIGS. 1 to 3andFIG. 4.

FIG. 4is a perspective view schematically illustrating a first solar cell151and a second solar cell152, which are included in the solar cell panel100ofFIG. 1and are connected to each other via the wire142. InFIG. 4, the first and second solar cells151and152are schematically illustrated, and the illustration is focused on the semiconductor substrate160and the electrodes42and44.

As illustrated inFIG. 4, two neighboring solar cells150(e.g. the first solar cell151and the second solar cell152) among the solar cells150may be interconnected by the wire142. At this time, the wire142interconnects the first electrode42, which is disposed on the front surface of the first solar cell151, and the second electrode44, which is disposed on the back surface of the second solar cell152, which is located on one side (the left lower side inFIG. 4) of the first solar cell151. In addition, another wire142ainterconnects the second electrode44, which is disposed on the back surface of the first solar cell151, and the first electrode42, which is disposed on the front surface of another solar cell, which may be located on the other side (the right upper side inFIG. 4) of the first solar cell151. In addition, another wire142binterconnects the first electrode42, which is disposed on the front surface of the second solar cell152, and the second electrode44, which is disposed on the back surface of another solar cell, which may be located on one side (the left lower side inFIG. 4) of the second solar cell152. In this way, the multiple solar cells150may be interconnected to form a single row by the wires142,142aand142b. A following description related to the wire142may be applied to all of the wires142,142aand142b, each of which interconnects two neighboring solar cells150.

In the present embodiment, the wire142may include a first portion, a second portion, and a third portion. The first portion is connected to the first electrode (more specifically, a bus-bar line (see reference numeral42binFIG. 5) of the first electrode42) and extends a long length from a first edge161to a second edge162, which is opposite the first edge161. The second portion is connected to the second electrode44(more specifically, pad portions442of the second electrode44) on the back surface of the second solar cell152and extends a long length from the first edge161to the second edge162, which is opposite the first edge161. The third portion extends from the front surface of the first solar cell151to the back surface of the second solar cell152so as to connect the first portion and the second portion to each other. As such, the wire142may cross a region of the first solar cell151, and then may cross a region of the second solar cell152. When the wire142has a width smaller than the first and second solar cells151and152and is formed so as to correspond to the regions of the first and second solar cells151and152(e.g. the bus-bar line42b), the wire142may effectively interconnect the first and second solar cells151and152despite a small area thereof.

In one example, the wire142may come into contact with the bus-bar line42bof the first electrode42and the pad portion442of the second electrode44so as to extend a long length along the bus-bar line42band the pad portion442. Thereby, the wire142and the first and second electrodes42and44may come into contact with each other at a sufficient area or sufficient length, which may improve electrical properties. However, the embodiment of the present invention is not limited thereto. The first electrode42may have no bus-bar line42b, and in this case, the wire142may be in contact with and be connected to a plurality of finger lines (see reference numeral42ainFIG. 5) so as to cross the finger lines42a. Various other alterations are possible.

When viewing one surface of each solar cell150, the multiple wires142may be provided to improve the electrical connection between neighboring solar cells150. In particular, in the present embodiment, the wire142has a width smaller than a conventional ribbon having a relatively large width (e.g. within a range from 1 mm to 2 mm). As such, a greater number of wires142than the conventional ribbons (e.g. 2˜5 wires) are used on one surface of each solar cell150.

In one example, each wire142may include a core layer1420a, which is formed of a metal, and a solder layer1420b, which is coated over the surface of the core layer1420aat a small thickness and includes a solder material so as to enable soldering with the electrodes42and44. In one example, the core layer1420amay include Ni, Cu, Ag or Al as a main material (e.g., a material included in an amount of 50 weight percents or more, more specifically, 90 weight percents or more). The solder layer1420bmay include Pb, Sn, SnIn, SnBi, SnPb, SnPbAg, SnCuAg or SnCu as a main material. However, the embodiment of the present invention is not limited thereto, and the core layer1420aand the solder layer1420bmay include various other materials.

When the wire142, which has a width smaller than the conventional ribbon, is used, material costs may be considerably reduced. In addition, because the wire142has a width smaller than the ribbon, a sufficient number of wires142may be provided to minimize the movement distance of carriers, which may enhance the output of the solar cell panel100.

In addition, the wire142according to the present embodiment may include a rounded portion. That is, the wire142may have a circular, oval, or curvilinear cross section, or a rounded cross section. Thereby, the wire142may cause reflection or diffused reflection. In this way, light, reflected from the rounded surface of the wire142may be reflected or totally reflected by the front substrate110or the back substrate120, which is disposed on the front surface or the back surface of the solar cell150, to thereby be reintroduced into the solar cell150. This may effectively enhance the output of the solar cell panel100. However, the embodiment of the present invention is not limited thereto. Accordingly, the wire142may have a polygonal shape, such as a rectangular shape, or may have any of various other shapes.

In the present embodiment, the width (or the diameter) of the wire142may range from 250 μm to 500 μm. For reference, in the present embodiment, because the thickness of the solder layer1420bmay be very small thickness and may have any of various values depending on the position of the wire142, the width of the wire142(see reference character W inFIG. 5) may be the width of the core layer1420a. Alternatively, the width W of the wire142may be determined so that the wire142is located over a line portion (see reference numeral421inFIG. 5) so as to pass through the center of the line portion. The wire142having the above-described width may efficiently transfer current, generated in the solar cell150, to an external circuit (e.g. a bus ribbon or a bypass diode of a junction box) or another solar cell150. In the present embodiment, the wires142may be individually positioned over and fixed to the electrodes42and44of the solar cell150without being inserted into, for example, a separate layer or film. When the width W of the wires142is below 250 μm, the strength of the wire142may be insufficient and the connection area between the wires142and the electrodes42and44may be very small, which may result in poor electrical connection and low attachment force. When the width W of the wires142exceeds 500 μm, the cost of the wires142may increase, and the wires142may prevent light from being introduced into the front surface of the solar cell150, thereby increasing shading loss. In addition, the wires142may receive force so as to be spaced apart from the electrodes42and44, which may cause low attachment force between the wires142and the electrodes42and44and may generate cracks in the electrodes42and44or the semiconductor substrate160. In one example, the width W of the wires142may range from 350 μm to 450 μm (more particularly, from 350 μm to 400 μm). With this range, the wires142may achieve increased attachment force for the electrodes42and44and may enhance the output of the solar cell panel100.

At this time, three to thirty-three wires142may be provided on one surface of the solar cell150. More specifically, when the width W of the wires142is 250 μm or more and below 300 μm, the number of the wires142may range from 15 to 33. When the width W of the wires142is 300 μm or more and below 350 μm, the number of the wires142may range from 10 to 33. When the width W of the wires142is 350 μm or more and below 400 μm, the number of the wires142may range from 8 to 33. When the width W of the wires142ranges from 400 μm to 500 μm, the number of the wires142may range from 6 to 33. In addition, when the width W of the wires142is 350 μm or more, the output of the solar cell panel100is no longer increased even if the number of the wires142exceeds 15. In addition, when the number of the wires142increases, this may increase burden on the solar cell150. In consideration of this, when the width W of the wires142is 350 μm or more and below 400 μm, the number of the wires142may range from 8 to 15. When the width W of the wires142ranges from 400 μm to 500 μm, the number of the wires142may range from 6 to 15. At this time, in order to further enhance the output of the solar cell panel100, the number of the wires142may be 10 or more (e.g. 12 or 13). However, the embodiment of the present invention is not limited thereto, and the number of the wires142and the number of the bus-bar lines42bmay have various other values.

At this time, the pitch of the wires142(or the pitch of the bus-bar lines42bor the pad portions442) may range from 4.75 mm to 26.13 mm. This is acquired in consideration of the width W and the number of the wires142. For example, when the width W of the wires142is 250 μm or more and below 300 μm, the pitch of the wires142may range from 4.75 mm to 10.45 mm. When the width W of the wires142is 300 μm or more and below 350 μm, the pitch of the wires142may range from 4.75 mm to 15.68 mm. When the width W of the wires142is 350 μm or more and below 400 μm, the pitch of the wires142may range from 4.75 mm to 19.59 mm. When the width W of the wires142ranges from 400 μm to 500 μm, the pitch of the wires142may range from 4.75 mm to 26.13 mm. More specifically, when the width W of the wires142is 350 μm or more and below 400 μm, the pitch of the wires142may range from 10.45 mm to 19.59 mm. When the width W of the wires142ranges from 400 μm to 500 μm, the pitch of the wires142may range from 10.45 mm to 26.13 mm. However, the embodiment of the present invention is not limited thereto, and the pitch of the wires142and the pitch of the bus-bar lines42bmay have various other values.

The present embodiment exemplifies that the wires142have the above-described width and the rounded shape and are provided in the number described above, thereby enhancing the output of the solar cell panel100. However, the embodiment of the present invention is not limited thereto, and the width W, the number, the pitch, and the shape of the wires142may be altered in various ways.

In the present embodiment, for example, the first electrode42(or the second electrode44), the wire142, and an electrode area (see reference character EA inFIG. 5) may be symmetrically arranged in the first direction (e.g., the direction parallel to the finger lines42a) and the second direction (e.g., the direction parallel to the bus-bar lines42bor the wires142). Thereby, the flow of current may be stabilized. However, the embodiment of the present invention is not limited thereto.

One example of the electrodes42and44of the solar cell150, to which the wires142according to the embodiment of the present invention may be attached, will be described below in detail with reference toFIGS. 1 to 4andFIGS. 5to7. Hereinafter, the first electrode42will be described in detail with reference toFIG. 5, and then the second electrode44will be described in detail with reference toFIGS. 6 and 7.

FIG. 5is a partial front plan view illustrating portion A ofFIG. 4in an enlarged scale.

Referring toFIGS. 1 to 5, in the present embodiment, the first electrode42includes the finger lines42a, which extend in the first direction (e.g., the horizontal direction in the drawings) and are arranged parallel to each other. The first electrode42may further include the bus-bar lines42b, which extend in the second direction (e.g., the vertical direction in the drawings) crossing (e.g. perpendicular to) the finger lines42aand are connected or attached to the wires142. Because the bus-bar lines42bmay be arranged so as to correspond to the wires142, the description related to the number and the pitch of the wires142may be directly applied to the number and the pitch of the bus-bar lines42b. Hereinafter, an area between two neighboring bus-bar lines42bamong the bus-bar lines42bor an area between the bus-bar line42band the edge of the solar cell150is referred to as the electrode area EA. In the present embodiment, because the multiple (e.g. 6 or more) wires142are provided on one surface of the solar cell150, a plurality of electrode areas EA (provided in the number greater than the number of the wires142by one) may be provided.

The finger lines42amay have a consistent width, and may be spaced apart from one another at a consistent pitch. AlthoughFIG. 5illustrates that the finger lines42aare formed parallel to each other in the first direction and are parallel to the main edges (more particularly, the first and second edges161and162) of the solar cell150, the embodiment of the present invention is not limited thereto.

In one example, the finger lines42aof the first electrode42may have the width ranging from 35 μm to 120 μm and may have the pitch ranging from 1.2 mm to 2.8 mm, and the number of the finger lines42amay range from 55 to 130 in the direction crossing the finger lines42a. The width and the pitch of the finger lines42amay be determined based on easy process conditions, and may be limited to minimize shading loss due to the finger lines42awhile ensuring the effective collection of current generated via photoelectric conversion. The thickness of the finger lines42amay be within the range in which the finger lines42amay be formed via an easy process and may have a desired specific resistance. However, the embodiment of the present invention is not limited thereto, and the width and the pitch of the finger lines42amay be changed in various ways depending on, for example, variation in process conditions, the size of the solar cell150, and the constituent material of the finger lines42a.

At this time, the width W of the wires142may be smaller than the pitch of the finger lines42a, and may be greater than the width of the finger lines42a. However, the embodiment of the present invention is not limited thereto, and various alterations are possible.

In one example, the bus-bar lines42bmay be successively formed from the position proximate to the first edge161to the position proximate to the second edge162on a per electrode area EA basis. As mentioned above, the bus-bar lines42bmay be located so as to correspond to the wires142, which are used to connect the respective neighboring solar cells150. The bus-bar lines42bmay correspond to the wires142in a one-to-one ratio. As such, in the present embodiment, the number of the bus-bar-lines42bmay be the same as the number of the wires142on one surface of the solar cell150.

Each bus-bar line42bmay include the line portion421, which has a relatively small width and extends a long length in the direction in which it is connected to the wire142within the electrode area EA, and a pad portion422, which has a width greater than the line portion421so as to increase the area of connection for the wire142. The line portion421having a small width may minimize the area by which light is blocked so as not to be introduced into the solar cell150, and the pad portion422having a large width may increase the attachment force between the wire142and the bus-bar line42band may reduce contact resistance. The pad portion422has a width greater than the line portion421, and thus substantially serves as a region for the attachment of the wire142. The wire142may be attached to the line portion421, or may be simply placed on the line portion421without being attached thereto.

The width of the pad portion422, measured in the first direction, may be greater than the width of each of the line portion421and the finger line42a.

The present embodiment exemplifies that the line portion421of the bus-bar line42bis provided so as to correspond to the wire142. More specifically, although a bus-bar electrode, which is significantly wider than the finger line42a, is provided to correspond to the wire142in the related art, in the present embodiment, the line portion421of the bus-bar line42b, which has a width significantly smaller than the bus-bar electrode, is provided. In the present embodiment, the line portion421may connect the finger lines42ato one another so as to provide a bypass path for carriers when some finger lines42aare disconnected.

In this specification, the bus-bar electrode refers to an electrode portion, which is formed in the direction crossing the finger lines so as to correspond to the ribbon and has a width twelve times or more (usually, fifteen times or more) the width of the finger lines. Two or three bus-bar electrodes are usually provided because the bus-bar electrodes have a relatively large width. In addition, in the present embodiment, the line portion421of the bus-bar line42bmay refer to an electrode portion, which is formed in the direction crossing the finger lines42aso as to correspond to the wire142and has a width ten times or less the width of the finger line42a.

In one example, the width W1of the line portion421may range from 0.5 times to 10 times the width of the finger line42a. When the ratio is below 0.5 times, the width W1of the line portion421may be too small to allow the line portion421to exert sufficient effects. When the ratio exceeds 10 times, the width W1of the line portion421may be excessive, causing increased shading loss. In particular, in the present embodiment, because a great number of wires142are provided, the line portions421are also provided in a great number, which may further increase shading loss. More specifically, the width W1of the line portion421may range from 0.5 times to 7 times the width of the finger line42a. When the ratio is 7 times or less, shading loss may further be reduced. In one example, in terms of shading loss, the width W1of the line portion421may range from 0.5 times to 4 times the width of the finger line42a. More specifically, the width W1of the line portion421may range from 0.5 times to 2 times the width of the finger line42a. With this range, the efficiency of the solar cell150may be greatly increased.

Alternatively, the width W1of the line portion421may be equal to or smaller than the width W of the wire142. This is because the width or area by which the lower surface of the wire142comes into contact with the line portion421is not large when the wire142has a circular, oval or rounded shape. When the line portion421has a relatively small width W1, the area of the first electrode42may be reduced, resulting in a reduction in the manufacturing costs of the first electrode42.

In one example, the ratio of the width W of the wire142to the width W1of the line portion421may range from 1:0.07 to 1:1. When the ratio is below 1:0.07, the width W1of the line portion421is excessively small, causing deterioration in electrical properties. When the ratio exceeds 1:1, the area of the first electrode42is increased, causing increased shading loss and material costs without considerable improvement in the contact between the wire142and the line portion421. In one example, the ratio may range from 1:01 to 1:0.5 (more specifically, from 1:0.1 to 1:0.3) when further considering the shading loss and the material costs.

Alternatively, the width W1of the line portion421may range from 35 μm to 350 μm. When the width W1of the line portion421is below 35 μm, the width W1of the line portion421is excessively small, causing deterioration in electrical properties. When the width W1of the line portion421exceeds 350 μm, the area of the first electrode42is excessive, causing increased shading loss and material costs without considerable improvement in the contact between the wire142and the line portion421. In one example, the width W1of the line portion421may range from 35 μm to 200 μm (more specifically, from 35 μm to 120 μm) when further considering the shading loss and the material costs.

However, the embodiment of the present invention is not limited thereto. Accordingly, the width W1of the line portion421may be changed in various ways within the range in which the line portion421effectively transfers current generated via photoelectric conversion and minimizes shading loss.

In addition, the width of the pad portion422may be greater than the width W1of the line portion421, and may be equal to or greater than the width W of the wire142. Because the pad portion422serves to increase force for the attachment of the wire142by increasing the contact area of the wire142, the width of the pad portion422may be greater than the width of the line portion421, and may be equal to or greater than the width of the wire142.

In one example, the ratio of the width W of the wire142to the width of the pad portion422may range from 1:1 to 1:5. When the ratio is below 1:1, the width of the pad portion422may be insufficient, causing insufficient attachment force between the pad portion422and the wire142. When the ratio exceeds 1:5, the area by which the pad portion422causes shading loss may be increased, resulting in greater shading loss. The ratio may range from 1:2 to 1:4 (more specifically, 1:2.5 to 1:4) when further considering the attachment force and the shading loss.

Alternatively, in one example, the width of the pad portion422may range from 0.25 mm to 2.5 mm. When the width of the pad portion422is below 0.25 mm, the contact area between the pad portion422and the wire142may be insufficient, and consequently, the attachment force between the pad portion422and the wire142may be insufficient. When the width of the pad portion422exceeds 2.5 mm, the area by which the pad portion422causes shading loss may be increased, resulting in greater shading loss. In one example, the width of the pad portion422may range from 0.8 mm to 1.5 mm.

In addition, the length of the pad portion422may be greater than the width of the finger line42a. For example, the length of the pad portion422may range from 0.035 mm to 30 mm. When the length of the pad portion422is below 0.035 mm, the contact area between the pad portion422and the wire142may be insufficient, and consequently, the attachment force between the pad portion422and the wire142may be insufficient. When the length of the pad portion422exceeds 30 mm, the area by which the pad portion422causes shading loss may be increased, resulting in greater shading loss.

Alternatively, in one example, the ratio of the width of the finger line42ato the length of the pad portion422may range from 1:1.1 to 1:20. With this range, the area for attachment between the pad portion422and the wire142is increased, and consequently, the attachment force between the pad portion422and the wire142may be increased.

Alternatively, in one example, the ratio of the width W of the wire142to the length of the pad portion422may range from 1:1 to 1:10. When the ratio is below 1:1, the length of the pad portion422may be insufficient, causing insufficient attachment force between the pad portion422and the wire142. When the ratio exceeds 1:10, the area by which the pad portion422causes shading loss may be increased, resulting in greater shading loss. The ratio may range from 1:3 to 1:6 when further considering the attachment force and the shading loss.

One bus-bar line42bmay include six to twenty-four pad portions422(e.g. twelve to twenty-two pad portions). The pad portions422may be spaced apart from one another. In one example, one pad portion422may be allotted to two to ten finger lines42a. Thereby, the portion in which the contact area between the bus-bar line42band the wire142is increased is provided at a regular interval so as to increase the attachment force between the bus-bar line42band the wire142. Alternatively, the pad portions422may be arranged so that distances between the respective two pad portions422have different values. In particular, the pad portions422may be arranged at a high density on the end of the bus-bar line42b, to which greater force is applied than in the other portion (e.g., the central portion of the bus-bar line42b). Various alterations are possible.

The second conductive area30, the second passivation film32, and the second electrode44will be described in detail with reference toFIGS. 6 and 7.

FIG. 6is a rear plan view illustrating the solar cell150ofFIG. 4, andFIG. 7is a sectional view taken along line VII-VII ofFIG. 6.

Referring toFIGS. 6 and 7, the second electrode44may be formed substantially throughout the back surface of the semiconductor substrate160excluding spacers S. Here, “formed throughout” includes not only a physically complete formation, but also formation with inevitably excluded parts. For example, the second electrode44may be formed throughout the back surface of the semiconductor substrate160so as to be spaced apart from the edge of the back surface by a given distance.

Accordingly, in the present embodiment, the second electrode44has a shape different from the first electrode42, and the area rate of the second electrode44may be greater than the area rate of the first electrode42. For example, assuming that the area of the semiconductor substrate160is 100%, the area rate of the second electrode44may range from 90% to 100% (e.g. from 95% to 100%). However, the embodiment of the present invention is not limited thereto.

Because a smaller quantity of light is introduced into the back surface of the semiconductor substrate160than in the front surface, reflecting light introduced into the front surface of the semiconductor substrate160, into which a relatively great quantity of light is introduced, so as to reuse the light in the solar cell150may be more advantageous in terms of efficiency, compared to introduce light into the back surface of the semiconductor substrate160. Accordingly, in the present embodiment, the second electrode44is formed throughout the back surface of the semiconductor substrate160so that most of light, having passed through the semiconductor substrate160to thereby reach the back surface, is reflected to the front surface of the semiconductor substrate160so as to be reused. Thereby, the efficiency of the solar cell150may be increased.

In the present embodiment, the second electrode44may include a pad portion422and an electrode portion444, which include different conductive materials as main components. At this time, the spacer S may be located between the electrode portion444and the pad portion442(more accurately, a pad442a), which are spaced apart from each other in the second direction.

The pad portion442is the area to which the wire142for connection with a neighboring solar cell150is attached or adhesively bonded. As described above, the wire142, which extends a long length, is attached or adhesively bonded to the bus-bar line42bof the first electrode42of one solar cell150and to the pad portion442of the second electrode44of another neighboring solar cell150, thereby connecting the two neighboring solar cells150to each other.

In addition, the electrode portion444is connected to (e.g. in contact with) the second conductive area30and serves to collect carries produced by the second conductive area30. The electrode portion444may be formed throughout a region excluding the spacers S and the pad portions442. Accordingly, the electrode portion444may be formed throughout the semiconductor substrate160, and may have openings OP for exposing at least a portion of the semiconductor substrate160corresponding to the pad portions442. At this time, when the electrode portion444includes a conductive material that may function as a second conductive dopant as in the present embodiment, the electrode portion444may also serve to form the second conductive area30via thermal diffusion.

The pad portions442may include a conductive material (e.g. a metal material), which exhibit excellent electrical conductivity and excellent attachment force between the pad portion442and the wire142, and the electrode portion444may include a conductive material (e.g. a metal material), which may easily form the second conductive area30in the state in which the second passivation film32is subjected to a fire-through process via thermal treatment. In one example, the pad portions442may include silver, and the electrode portion444may include aluminum, which is a group-III element and may function as a second conductive dopant. The electrode portion444may include, as a main component (a material included in the largest quantity, e.g., a component of 50 weight percent or more), a single conductive material, such as aluminum, or may include, as a main component, an aluminum-silicon alloy, which is produced via reaction with a semiconductor material (e.g. silicon) constituting the semiconductor substrate160. In addition, the pad portions442may include silver as a main component.

In the present embodiment, the area of the electrode portion444may be greater than the area of the pad portions442. Thereby, the electrode portion444, which substantially collects carriers, may have a sufficient area. In addition, when the electrode portion444has a large area, the second conductive area30, which has a shape corresponding to the electrode portion444, may have a large area. Thereby, recombination on the back surface of the semiconductor substrate160may be prevented, which may increase the efficiency of the solar cell150. The pad portion442may be formed only on the portion of the second electrode44connected to the wire142, which may increase the attachment force (tabbing) between the second electrode44and the wire142.

In one example, assuming that the area of the semiconductor substrate160is 100%, the area rate of the pad portions442of the second electrode44may be smaller than the area rate of the first electrode42. For example, assuming that the area of the semiconductor substrate160is 100%, the area rate of the pad portions442may range from 1% to 5% (e.g. from 2% to 3%). This is because each pad portion442has no portion corresponding to the finger lines and is formed so as to correspond to only the wire142. When the area rate of the pad portions442is below 1%, connection between the pad portion442and the wire142may be deteriorated. When the area rate of the pad portions442exceeds 5%, the area of the electrode portion444may be reduced, and consequently, the area of the second conductive area30may be reduced. In order to achieve more excellent effects, the area rate of the pad portion442may range from 2% to 3%.

The width W2(e.g., the width in the first direction) of the pad portion442of the second electrode44may be greater than the width W1of the line portion421of the bus-bar line42bof the first electrode42. This is because the line portion421of the bus-bar line42bis located on the front surface of the semiconductor substrate160, into which light is introduced, and therefore, increase in the width of the line portion421is limited. In one example, the width W2of the pad portion442may range from 1 mm to 2.5 mm, and as described above, the width W1of the line portion421of the bus-bar line42bof the first electrode42may range from 35 μm to 350 μm. This is because the pad portion442and the wire142may be smoothly connected to each other in this range. However, the embodiment of the present invention is not limited thereto, and the width W2of the pad portion442and the width W1of the line portion421of the bus-bar line42bmay have various other values.

In the present embodiment, the pad portion442may be located so as to extend in the second direction (e.g., the direction parallel to the bus-bar line42b, or the direction crossing (e.g. perpendicular to) the finger line42a) (e.g., the vertical direction inFIG. 5). In addition, the multiple pad portions442may be arranged at a constant pitch P in the first direction (e.g., the horizontal direction in the drawing) crossing the longitudinal direction (e.g., the second direction) of the pad portions442. At this time, the pad portions442of the second electrode44may be arranged at positions corresponding to the respective bus-bar lines42bor the respective wires142of the first electrode42in a one-to-one ratio. That is, the bus-bar line42bof the first electrode42and the pad portion442of the second electrode44may be located at substantially the same position with the semiconductor substrate160interposed therebetween.

At this time, each pad portion442located in the second direction may include at least one pad442a, which extends in the second direction. In one example, each pad portion442may include a plurality of pads442aspaced apart from one another in the second direction so as to form a single row. Each pad442amay take the form of an island having a closed shape. In addition, the electrode portion444may be integrally formed in a portion excluding the openings OP, which correspond to the respective pads442ain a one-to-one ratio.

The pad portion442may be formed of a higher price material than the electrode portion444. When the pad portion442includes the pads442aspaced apart from one another as described above, the quantity of a constituent material of the pad portion442may be reduced, resulting in reduced manufacturing costs. In addition, the electrode portion444may have a sufficient area, and consequently, the second conductive area30may have a sufficient area.

In one example, one pad portion442may include one to ten pads442a, thus maintaining excellent connection with the wire142. At this time, one pad portion442includes three to ten pads442aso as to reduce the sum of lengths of the pads442a, which constitute one pad portion422. Thereby, the manufacturing costs of the pad portion442may be reduced. When the number of pads442ais increased, the length of each pad442amay be reduced, which may deteriorate the connection between the pad442aand the wire142. In consideration of this, one pad portion442may include three to six pads442aso as to achieve excellent connection with the wire142and to reduce the manufacturing costs thereof. However, the embodiment of the present invention is not limited thereto, and the number of pads442a, which constitute one pad portion442, may be changed depending on, for example, the size of the semiconductor substrate160, and the constituent material and the width of the wire142.

In addition, the distance D1between the neighboring pads442amay be within a range in which the strength of attachment between the pads442aand the wire142is not reduced. For example, the distance D1between the two neighboring pads442amay range from 2.5 cm to 4.5 cm. This range is determined to minimize the area of the pad portion442without deterioration in the strength of attachment between the pad portion442and the wire142. The pad442a, which is proximate to the edge of the semiconductor substrate160, may be spaced apart from the edge of the semiconductor substrate160by a given distance D2. In one example, the distance D2between the edge of the semiconductor substrate160and the end of the pad442aproximate to the edge may range from 1 cm to 2 cm. When the distance D2is below 1 cm, for example, unnecessary shunt may occur when an alignment error occurs, and the area of the pad portion442may be unnecessarily increased. When the distance D2exceeds 2 cm, the strength of attachment between the pad portion442and the wire142may be greatly reduced on the end of the pad portion442.

The distance D1between the neighboring pads442a, which is greater than the distance D2between the edge of the semiconductor substrate160and the pad442a, is exemplified in the drawings and the above description. This minimizes the area of the pad portion442while minimizing a reduction in the strength of attachment between the pad portion442and the wire142. However, the embodiment of the present invention is not limited thereto, and the distances D1and D2may have various other values.

The electrode portion444may include, in the region excluding the spacers S and the pad portions442, a proximate portion444a, which is proximate to or in contact with the semiconductor substrate160or the second conductive area30, and an overlap portion444b, which overlaps (e.g. in contact with) a portion of the pad portion442. In addition, a portion of the proximate portion444amay be spaced apart from the pad portion442(more specifically, the pad442a) so that the spacer S is located between the pad422aand the proximate portion444a. The overlap portion444bmay be intentionally formed to improve the connection with the pad portion442in consideration of a process error (process margins or process margin of error), and may be naturally formed based on the process error.

When the electrode portion444overlaps a portion of each pad portion442, the proximate portion444aof the electrode portion444may be disposed on (e.g. in contact with) the semiconductor substrate160or the second conductive area30, and the overlap portion444bof the electrode portion444may be spaced apart from the semiconductor substrate160or the second conductive area30and may be disposed on (e.g. in contact with) the pad portion442. That is, the pad portion442may first be formed on the semiconductor substrate160, and thereafter the electrode portion444may be formed. This is because the pad portion442including silver may not be easily peeled off when it is proximate to the semiconductor substrate160, but may be easily peeled off when it is disposed on the electrode portion444during a firing process for forming the second electrode44. The electrode portion444is not well peeled off in both the case where it is proximate to the semiconductor substrate160and the case where it is disposed over the pad portion442. In consideration of this, the entire pad portion442may first be formed so as to be proximate to the semiconductor substrate160, and then a portion of the electrode portion444may be formed over the pad portion442. However, the embodiment of the present invention is not limited thereto, and for example, the shape and stacking structure of the pad portions442and the electrode portion444may be changed in various ways.

In the present embodiment, the opening OP, which is formed in the electrode portion444so as to expose the pad portion442, may have a width W2smaller than the width W3of the pad442a(e.g., the opening OP may have the width W2of the pad portion442), and may have a length L2greater than the length L1of the pad442a(measured in the first direction). Thereby, the electrode portion444is formed over the pad portion442on opposite sides of the pad442ain the width direction so as to form the overlap portion444b. The electrode portion444is spaced apart from the pad portion442on opposite sides of the pad442ain the longitudinal direction so that the spacers S are located on opposite sides of the pad442ain the longitudinal direction. That is, the spacer S, in which the pad442aand the electrode portion444are not formed, is located on either side of the pad442ain the longitudinal direction at a position between the pad442aand the electrode portion444.

When the pad442aand the electrode portion444overlap each other in the width direction of the pad442a, electrical connection may be improved. In addition, a portion of the wire142, which does not come into contact with the electrode portion444due to the difference between the thicknesses of the pad442aand the electrode portion444, may be present in the longitudinal direction of the pad442abetween the pad442aand the electrode portion444. When the spacer S is formed in the non-contact portion, the manufacturing costs thereof may be reduced, and the wire142may be attached to the pad442ausing strong attachment force. This will be described below in more detail.

Referring toFIG. 7, the first thickness T1of the pad442amay be equal to or smaller than the second thickness T2of the electrode portion444. In particular, the first thickness T1may be smaller than the second thickness T2. Because the pad442aincludes, as a main component, a material capable of increasing attachment force for the wire142(e.g. expensive silver), the pad442amay be formed to have a relatively small thickness. In addition, because the electrode portion444includes a relatively cheap material, the electrode portion444may be formed to have a sufficient thickness so that the second electrode44has low resistance. In addition, the fire-through phenomenon acquired by the electrode portion444allows the second conductive area30to have a sufficient thickness so as to be formed at a sufficient area.

In one example, the first thickness T1of the pad442amay range from 5 μm to 15 μm, and the second thickness T2of the electrode portion444may range from 30 μm to 40 μm. These thicknesses are limited so as to effectively perform the role of each layer. When the first thickness T1ranges from 5 μm to 15 μm, excellent connection between the pad442aand the wire142may be acquired. In addition, when the second thickness ranges from 10 μm to 40 μm, the fire-through phenomenon efficiently occurs, thus realizing low resistance.

Alternatively, the difference between the first thickness T1and the second thickness T2(e.g., the value acquired by subtracting the first thickness T1from the second thickness T2) may range from 5 μm to 30 μm. Alternatively, the ratio of the first thickness T1to the difference between the first thickness T1and the second thickness T2may range from 1:0.25 to 1:2, or the ratio of the second thickness T2to the difference between the first thickness T1and the second thickness T2may range from 1:1 to 1:6. This range is limited to reduce manufacturing costs by reducing the first thickness T1and to provide the second electrode44with low resistance by relatively increasing the second thickness T2.

However, the embodiment of the present invention is not limited thereto, and each of the first thickness T1and the second thickness T2may have various other values.

Accordingly, when viewed in cross section, the distance between the wire142, which is attached to the electrode portion444or is placed over the electrode portion444, and the semiconductor substrate160is gradually reduced with decreasing distance to the pad442auntil the wire142comes into contact with the pad442a, and then is gradually increased with decreasing distance to the electrode portion444. Accordingly, because the portion of the wire142on either side of the pad442ahas a gradually reduced or increased distance to the semiconductor substrate160in the second direction, the pad442amay not be in contact with and be attached to this portion of the wire142. In consideration of this, in the present embodiment, the spacers S, in which the electrode portion444and the pad442aare not formed, may be located on opposite sides of the pad442ain the second direction, in order to reduce manufacturing costs by reducing the area of the second electrode44without deterioration in the attachment between the pad442aand the wire142.

At this time, the length L3of the spacer S in the second direction may have a value corresponding to the length of the portion, to which no wire142will be attached, in consideration of the difference between the first thickness T1of the pad442and the second thickness T2of the electrode portion444. That is, as the difference between the first thickness T1and the second thickness T2is increased, the length L3of the spacer S may be increased because the length of the portion, which cannot come into contact with the wire142, is increased. Contrary, as the difference between the first thickness T1and the second thickness T2is reduced, the length L3of the spacer S may be reduced because the length of the portion, which cannot come into contact with the wire142, is reduced. In addition, the length L3of the spacer S concerns with the width W of the wire142attached to the pad442a. More specifically, when the width W of the wire142is small, the length L3of the spacer S may be reduced in order to improve the attachment between the pad442aand the wire142. Contrary, when the width W of the wire142is increased, excellent attachment between the wire142and the pad442amay be achieved even if the length L3of the spacer S is increased.

In the present embodiment, the length L3of the spacer S may be greater than the width W of the wire142, may be greater than the difference between the thicknesses of the electrode portion444and the pad442a, and may be greater than the width W2of the overlap portion444ain the first direction. Thereby, the length L3of the spacer S may be sufficient to reduce the area of the second electrode44, resulting in reduced manufacturing costs.

In one example, the length L3of the spacer S may range from 0.5 mm to 3 mm. When the length L3of the spacer S is below 0.5 mm, reduction in the area of the second electrode44may be insufficient, and therefore, it may be difficult to sufficiently reduce manufacturing costs. When the length L3of the spacer L exceeds 3 mm, the pad442aand the wire142may have difficulty in coming into contact with each other at a sufficient area.

In one example, the width W4by which the overlap portion444band the pad442aoverlap each other may range from 0.05 mm to 2 mm. This range is limited to allow the overlap portion444band the pad442ato overlap each other even if an alignment error occurs. In addition, when the width W4is below 0.05 mm, the contact area between the overlap portion444band the pad442amay be reduced, which may cause high contact resistance. When the width W4exceeds 2 mm, material costs for the formation of the second electrode44may be increased, or the width of the pad442aexposed through the opening OP may be insufficient, which may deteriorate the attachment between the pad442and the wire142.

Alternatively, the ratio of the difference between the first thickness T1and the second thickness T2to the length L3of the spacer S may range from 1:60 to 1:100. When the ratio is below 1:60, reduction in the area of the second electrode44may be insufficient, and it may be difficult to sufficiently reduce manufacturing costs. When the ratio exceeds 1:100, the pad442aand the wire142may have difficulty in coming into contact with each other at a sufficient area. The ratio may range from 1:78 to 1:83 when further considering the contact area between the pad442aand the wire142and manufacturing costs.

Alternatively, the ratio of the width W of the wire142to the length L3of the spacer S may range from 1:10 to 1:15. When the ratio is below 1:10, reduction in the area of the second electrode44may be insufficient, and it may be difficult to sufficiently reduce manufacturing costs. When the ratio exceeds 1:15, the pad442aand the wire142may have difficulty in coming into contact with each other at a sufficient area. The ratio may range from 1:12 to 1:14 when further considering the contact area between the pad442aand the wire142and manufacturing costs.

Alternatively, the ratio of the width W4of the overlap portion444bto the length L3of the spacer S may range from 1:1.5 to 1:60. This ratio may ensure the sufficient length L of the spacer S while minimizing the overlap portion444b, thereby improving the attachment between the pad442aand the wire142. In one example, the ratio may range from 1:2 to 1:10. However, the embodiment of the present invention is not limited thereto, and various alterations are possible.

The length L1of the pad442amay be greater than the width W2of the pad442a, and may be determined to allow the wire142to be attached to the pad442at a sufficient area.

In one example, the ratio of the length L1of the pad442ato the portion of the wire142attached to the pad442amay be 95% or more (e.g., within a range from 95% to 100%, e.g. 100%). Thereby, the wire142may be attached to the entire pad442a, which may improve the attachment between the pad442aand the wire142while minimizing the area of the pad442a.

To this end, in one example, the length L1of the pad442amay range from 2 mm to 7 mm. When the length L1is below 2 mm, the contact area between the pad442aand the wire142may be excessively small. When the length L1exceeds 7 mm, a portion of the pad442amay not be attached to the wire142.

Alternatively, the ratio of the length L1of the pad442ato the length L3of the spacer may range from 1:0.03 to 1:0.45. When the ratio is below 1:0.03, reduction in the area of the second electrode44may be insufficient, and it may be difficult to sufficiently reduce the manufacturing costs thereof. When the ratio exceeds 1:0.45, the pad442aand the wire142may have difficult in achieving a sufficient contact area therebetween.

However, the embodiment of the present invention is not limited thereto, and for example, the ratio and the length L1may be changed in various ways depending on the number of pads442a.

The wire142may widely spread so as to have a rounded shape as the coating layer thereof (see reference numeral142binFIG. 3) spreads over each pad442a, thereby being attached to the pad442a(more particularly, a region of the pad442aexcluding the overlap portion444b). Thereby, the width of a first portion of the wire142disposed over each pad442amay be greater than the width of another portion (e.g., a second portion of the wire142disposed over the spacer S and the electrode portion444). More specifically, the wire142has a consistent width on the spacer S, in which the pad portion442and the electrode portion444are not provided, and is spaced apart from the solar cell150. In addition, because soldering between the wire142and the electrode portion444does not occur, or very slightly occurs, the wire142may be placed over the electrode portion444so as to have a consistent width without being fixed or attached to the electrode portion444. That is, in the present embodiment, the wire142may be attached to only the pad442a. However, the embodiment of the present invention is not limited thereto.

Referring toFIGS. 3 and 7, in the present embodiment, the second passivation film32may be disposed so as to correspond to a portion of the second electrode44excluding, for example, the proximate portion444aof the electrode portion444, e.g., to the portion between the pad442aand the semiconductor substrate160and the spacers S). In addition, the second conductive area30may be formed so as to correspond to the remaining portion of the second electrode44(e.g. the proximate portion444ain which the electrode portion444and the back surface of the semiconductor substrate160are proximate to each other), e.g., to the portion in which the pad442aand the spacer S are not formed.

At this time, the third thickness T3of the second passivation film32may be smaller than the first thickness T1of the pad portion442and the second thickness T2of the electrode portion444. When the third thickness T3is greater than the first thickness T1and the second thickness T2, the fire-through process cannot be efficiently performed, which may deteriorate the connection between the proximate portion444aof the electrode portion444and the second conductive area32, and resistance may be increased due to the small thicknesses of the pad portion442and the electrode portion444. Because the third thickness T3is smaller than the first thickness T1and the second thickness T2, the pad portion442, which is disposed over the second passivation film32, and the proximate portion444aof the electrode portion444, which is not disposed over the second passivation film32, may be located so as to come into contact with each other on at least side surfaces thereof. In addition, the entire pad portion442may come into contact with the second passivation film32, and the side surface of the second passivation film32may come into contact with the electrode portion444.

In one example, the third thickness T3may range from 5 nm to 30 nm. When the third thickness T3is below 5 nm, sufficient passivation may not be achieved. When the third thickness T3exceeds 30 nm, the fire-through process may be not efficiently performed.

As described above, because the area of the proximate portion444ais relatively large, the area of the second passivation film32, formed on the portion excluding the proximate portion444aof the electrode portion444, is smaller than the area of the second conductive area30, which corresponds to the area of the proximate portion444a. For example, assuming that the area of the semiconductor substrate160is 100%, the area of the second passivation film32, which corresponds to the pad portion442and the spacers S, may range from 1% to 5% (e.g. from 2% to 3%).

This is because the electrode portion444includes a material, which can undergo a fire-through process, and the pad portion442includes a material, which cannot undergo the fire-through process, and therefore, during a firing process, the second passivation film32on the pad portion442and the spacer S remains, and the second passivation film32on the proximate portion444ais removed, whereby the constitute material (or constituent material) of the proximate portion444adiffuses to the back surface of the semiconductor substrate160so as to form the second conductive area30.

In the present embodiment, the second electrode44, disposed on the back surface of the semiconductor substrate160, includes the pad portion442and the electrode portion444, and the pad portion442and the electrode portion444are formed of different conductive materials, which may improve both the property required for the pad portion442and the property required for the electrode portion444. At this time, when the spacer S is located in the longitudinal direction of the pad portion442, the area of the second electrode44may be reduced, resulting in reduced manufacturing costs while ensuring the excellent attachment between the pad portion442and the wire142.

In particular, when the wire142having a rounded portion as described above is used, shading loss attributable to diffused reflection may be minimized, and the movement path of carriers may be reduced by increasing the number of the wires142and reducing the pitch between the wires142. Thereby, the efficiency of the solar cell150and the output of the solar cell panel100may be enhanced. However, in this case, the attachment between the wire142and the pad portion442may be deteriorated because the width and the thickness of the wire142are the same or similar to each other. In the present embodiment, even when the wire142having the structure described above is applied, excellent attachment may be maintained by limiting, for example, the dimension of the spacer S.

In addition, through the provision of the overlap portion444b, the electrical connection between the pad portion442and the electrode portion444may be improved. In addition, the second passivation film32is located in a region excluding the proximate portion444aof the electrode portion444so as to correspond to the portion between the semiconductor substrate160and the pad portion442and to the spacers S, which may result in improved passivation effects. In addition, when the second conductive area30is formed so as to correspond to the proximate portion444a, the second conductive area30may be formed so as to have a sufficient area via a simplified method.

As is apparent from the above description, according to the present embodiment, an electrode includes a pad portion and an electrode portion, and the pad portion and the electrode portion are formed of different conductive materials, which may improve both the property required for the pad portion and the property required for the electrode portion. At this time, as a result of forming a spacer in the longitudinal direction of the pad portion, excellent attachment between the pad portion and a wire may be maintained, which may reduce the area of the electrode, and consequently, reduce manufacturing costs. In this way, the efficiency, productivity, and attachment of a solar cell and a solar cell panel including the same may be improved.

The above described features, configurations, effects, and the like are included in at least one of the embodiments of the present invention, and should not be limited to only one embodiment. In addition, the features, configurations, effects, and the like as illustrated in each embodiment may be implemented with regard to other embodiments as they are combined with one another or modified by those skilled in the art. Thus, content related to these combinations and modifications should be construed as including in the scope and spirit of the invention as disclosed in the accompanying claims.