Front side seal to prevent germanium outgassing

A method of manufacturing an integrated circuit having a gate structure above a substrate that includes germanium utilizes at least one layer as a seal. The layer advantageously can prevent back sputtering and outdiffusion. A transistor can be formed in the substrate by doping through the layer. Another layer can be provided below the first layer. Layers of silicon dioxide, silicon carbide, silicon nitride, titanium, titanium nitride, titanium/titanium nitride, tantalum nitride, and silicon carbide can be used.

CROSS-REFERENCE TO RELATED PATENT APPLICATIONS

The present application is related to U.S. application Ser. No. 10/341,863, filed on Jan. 14, 2003 by Ngo et al., entitled “Shallow Trench Isolation For Strained Silicon Process” and assigned to the Assignee of the present application.

FIELD OF THE INVENTION

The present invention relates generally to integrated circuit (IC) fabrication. More particularly, the present invention relates to a design for and a method of reducing contamination during IC fabrication on substrates and layers containing germanium.

BACKGROUND OF THE INVENTION

Strained silicon (SMOS) processes are utilized to increase transistor (MOSFET) performance by increasing the carrier mobility of silicon, thereby reducing resistance and power consumption and increasing drive current, frequency response and operating speed. Strained silicon is typically formed by growing a layer of silicon on a silicon germanium substrate or layer. Germanium can also be implanted, deposited, or otherwise provided to silicon layers to change the lattice structure of the silicon and increase carrier mobility.

The silicon germanium lattice associated with the germanium substrate is generally more widely spaced than a pure silicon lattice, with spacing becoming wider with a higher percentage of germanium. Because the silicon lattice aligns with the larger silicon germanium lattice, a tensile strain is created in the silicon layer. The silicon atoms are essentially pulled apart from one another. Relaxed silicon has a conductive band that contains six equal valance bands. The application of tensile strength to the silicon causes four of the valance bands to increase in energy and two of the valance bands to decrease in energy. As a result of quantum effects, electrons effectively weigh 30 percent less when passing through the lower energy bands. Thus, lower energy bands offer less resistance to electron flow.

In addition, electrons meet with less vibrational energy from the nucleus of the silicon atom, which causes them to scatter at a rate of 500 to 1,000 times less than in relaxed silicon. As a result, carrier mobility is dramatically increased in strained silicon compared to relaxes silicon, providing an increase in mobility of 80 percent or more for electrons and 20 percent or more for holes. The increase in mobility has been found to persist for current fields up to 1.5 megavolt/centimeter. These factors are believed to enable device speed increase of 35 percent without further reduction of device size, or a 25 percent reduction in power consumption without reduction in performance.

The use of germanium in SMOS processes can cause germanium contamination problems for IC structures, layers, and equipment. In one example, germanium outgassing or outdiffusion can contaminate various components associated with the fabrication equipment and integrated circuit structures associating with the processed wafer. Further, germanium outgassing can negatively impact the formation of thin films. In addition, germanium outdiffusion can cause germanium accumulation or “pile-up” at the interface of the liner, thereby causing reliability issues for the STI structure. In another example, germanium resputtering can cause contamination. Germanium resputtering can occur when the IC substrate is subjected to implants, cleaning and doping steps. For example, providing dopants for the source and drain regions can cause germanium resputtering.

Thus, there is a need for an SMOS process which reduces germanium contamination. Further, there is a need for a process of forming source and drain regions that does not promote germanium contamination. Further still, there is a need for an SMOS process which reduces germanium resputtering. Yet further, there is a need for a process and structure that reduces germanium outgassing. Even further, there is a need for a method of siliciding and a transistor architecture which avoids germanium resputtering.

SUMMARY OF THE INVENTION

An exemplary embodiment relates to a method of manufacturing an integrated circuit. The integrated circuit includes a gate structure above a substrate that includes germanium. The method includes forming a first layer above the gate structure and above the substrate, forming a second layer above the first layer, and doping source and drain regions through the first layer and the second layer. Germanium back sputtering is reduced by the method.

Yet another exemplary embodiment relates to a method of forming source and drain regions in a strained semiconductor layer. The method includes providing a first layer comprising at least one of silicon nitride and silicon dioxide above the strained semiconductor layer, providing a second layer above the first layer, and implanting non-neutral dopants into the strained semiconductor layer. The second layer contains nitrogen, titanium, tantalum or carbon. The method also includes annealing the strained semiconductor layer.

Still another exemplary embodiment relates to a method of fabricating a transistor in a germanium containing layer. The method includes providing a gate structure above the germanium containing layer, providing a first layer of insulative material in a low temperature process above the germanium containing layer, doping to form source and drain regions, and annealing to activate dopants in the source and drain regions.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

FIGS. 1 through 7illustrate a method of manufacturing an integrated circuit (IC) in accordance with an exemplary embodiment. The method and IC structure illustrated inFIGS. 1 through 7reduces the germanium contamination during various fabrication processes, including doping. The process includes at least one sealing layer that reduces germanium outdiffusion and back sputtering and can be used as a part of any process that seeks to avoid germanium contamination. Advantageously, the process reduces germanium contamination of fabrication equipment and IC structures associated with silicon germanium substrates and strained silicon or semiconductor layers.

Referring toFIGS. 2 through 7, a cross-sectional view of a portion12of an integrated circuit (IC) is illustrated. Portion12(FIG. 2) is subjected to process100(FIG. 1) to form an IC. The IC can include a transistor with a gate structure and a source and drain region as explained below. Germanium contamination can be reduced through an advantageous process and transistor architecture. The architecture uses at least one sealing layer to prevent germanium from adversely affecting the formation of IC devices.

InFIG. 2, portion12includes a strained silicon layer16provided over a semiconductor substrate14or a germanium containing layer or substrate. Substrate14can be provided above a substrate13.

Substrate13is optional and portion12can be provided with substrate14as the bottom-most layer. Substrate13can be the same material or a different material than substrate14. In one embodiment, substrate13is a semiconductor substrate such as a silicon substrate upon which silicon germanium substrate14has been grown. In another embodiment, substrates13and14are not included and the substrate is comprised of layer16. In such an embodiment, layer16can be a silicon germanium substrate or a strained silicon substrate.

Portion12can be any type of semiconductor device, or portion thereof, made from any of the various semiconductor processes such as a complementary metal oxide semiconductor (CMOS) process, a bipolar process, or another semiconductor process. Portion12may be an entire IC or a portion of an IC including a multitude of electronic component portions.

Substrate14is preferably silicon germanium or another semiconductor material including germanium, and can be doped with P-type dopants or N-type dopants. Substrate14can be an epitaxial layer provided on a semiconductor or an insulative base, such as substrate13. Furthermore, substrate14is preferably a composition of silicon germanium (Si1-xGex, where X is approximately 0.2 and is more generally in the range of 0.1–0.4). Substrate14can be grown or deposited.

In one embodiment, substrate14is grown above substrate13by chemical vapor deposition (CVD) using disilane (Si2H6) and germane (GeH4) as source gases with a substrate temperature of approximately 650° C., a disilane partial pressure of approximately 30 mPa and a germane partial pressure of approximately 60 mPa. Growth of silicon germanium material may be initiated using these ratios, or, alternatively, the partial pressure of germanium may be gradually increased beginning from a lower pressure or zero pressure to form a gradient composition. Alternatively, a silicon layer can be doped by ion implantation with germanium, or other processes can be utilized to form substrate14. Preferably, substrate14is grown by epitaxy to a thickness of less than approximately 5000 Å (and preferably between approximately 1500 Å and 4000 Å).

A strained silicon layer16is formed above substrate14by an epitaxial process. Preferably, layer16is grown by CVD at a temperature of 600–800° C. Layer16can be a pure silicon layer and may have a thickness of between approximately 50 and 150 Å.

The substrate for portion12can be a semiconductor substrate such as silicon, gallium arsenide, germanium, or another substrate material. The substrate can include one or more layers of material and/or features such as lines, interconnects, vias, doped portions, etc., and can further include devices such as transistors, microactuators, microsensors, capacitors, resistors, diodes, etc. The substrate can be an entire IC wafer or part of an IC wafer. The substrate can be part of an integrated circuit such as a memory, a processing unit, an input/output device, etc.

In process100(FIG. 1) at step52, gate structures are formed by providing a gate stack including a gate dielectric layer18above a top surface46of layer16, a gate conductor22, and a bottom anti-reflective (BARC) layer26. Top surface46can be considered a top surface of the substrate or wafer associated with portion12, even though surface46corresponds to the top surface of layer16inFIG. 2. In one embodiment, gate structures are formed directly above substrate14and layer16is not included.

Gate conductor22is preferably a polysilicon layer having a thickness of 1000–2000 Å and deposited by chemical vapor deposition (CVD). Gate conductor22can be deposited as a P-doped or N-doped layer. Alternatively, conductor22can be a metal layer such as a refractory metal layer deposited by CVD or sputtering.

Layer26is preferably an anti-reflective coating material such as silicon oxynitride (SiON) or silicon nitride (Si3N4). Alternative materials for layer26can also be utilized. Layer26serves a dual purpose of providing anti-reflective properties (e.g., as a BARC layer) as well as protecting gate conductor22during etching steps. Layer26is preferably deposited above gate conductor22by chemical vapor deposition (CVD) and has a thickness of between approximately 100 and 300 Å. Alternatively, layer26can be thermally grown.

Photoresist feature24is formed above layer26. Preferably, photoresist feature24is lithographically patterned to form a gate structure from gate conductor22and dielectric layer18.

InFIG. 3, layers26and18and gate conductor22are etched in a conventional process to leave gate structure38(step52of process100). Gate structure38can include spacers23formed in a deposition and etch back process. In one embodiment, spacers23are silicon dioxide, silicon nitride, or another insulating material. In a preferred embodiment, spacers23are silicon nitride and layer26is stripped before spacers23are formed. Substrate14and layer16can be doped to provide appropriate regions such as halo regions, channel regions, and source and drain regions in step52.

In one embodiment, spacers23are not provided until after the sealing layer is provided. In another embodiment, layer16is doped to form shallow source and drain extensions (lightly doped) drains (LDD) before spacers23are provided and before the sealing layer is provided.

InFIG. 4, in accordance with step52of process100, bottom anti-reflective coating layer (BARC)26can be removed from gate conductor22. BARC layer26is preferably removed for appropriate silicidation of gate conductor22. In one embodiment, portions of spacers23are also removed so that a top surface of spacer23is planar with a top surface of gate conductor22. BARC layer26can be removed using either a wet etching process with a phosphoric acid bath or by using a dry etching process.

InFIG. 5, a layer47is provided above top surface46of layer16and gate structure38. In an embodiment in which gate structure38is provided directly above substrate14, layer47is provided above substrate14and gate structure38. Layer47can be a buffer layer. Preferably, layer47is an insulative material suitable for semiconductor processing materials.

In one example, layer47is a 50–400 Å thick layer of silicon dioxide provided above gate structure38and silicon nitride spacers23. Layer47can be a 100 Å thick silicon dioxide layer deposited in a tetraethylorthosilicate (TEOS) process. In another embodiment, layer47can be a masking material such as silicon nitride (Si3N4) or siliconoxynitride (SiON). Layer47provides an interface between layer16and gate structure38and the sealing layer discussed below. The sealing layer can prevent germanium outgassing and germanium resputtering following the implantation and annealing process.

InFIG. 6, a layer64is provided above layer47. Layer64serves as a sealing layer and is provided in accordance with step56of process100. The combination of layers47and64form a sealing structure to prevent germanium outgassing and germanium resputtering. Layer47ensures good seating for layer64.

In one embodiment, layer64is a layer of conductive or semiconductive material having a thickness of between approximately 50 and 200 Å. In one embodiment, layer64can be a layer of tantalum nitride (TaN), titanium nitride (TiN), tungsten nitride (WN), titanium/titanium nitride (Ti/TiN). Layer64can be deposited by sputtering or by CVD. The materials for layer64are chosen for their relatively high temperature stability and etch capabilities. Preferably, layers47and64are deposited in a low temperature process (e.g., less than approximately 800° C.) to reduce germanium outgassing associated with layer16and substrate14. For example, layer64may be deposited using a reactive sputtering or CVD process.

In another alternative embodiment, multiple layers similar to layer64can be provided to enhance the sealing effect. Layer64can have a thickness of between approximately 50 and 300 Å, and preferably approximately 200 Å.

InFIG. 7, the substrate is doped in accordance with step58of process100. Preferably, non-neutral dopants are implanted into layer16or substrate14to form source and drain regions32. Source and drain regions32can include source and drain extensions33provided underneath spacers23. Preferably, the non-neutral dopants include at least one of boron difluoride (BF2), boron (B), arsenic (As), and phosphorous (P). Back sputter of germanium due to the implant represented by arrow66is reduced via the sealing effect associated with layers47and64.

In accordance with step60of process100, layer16is annealed to activate dopants in source and drain regions32. Preferably, a rapid thermal anneal (RTA) is performed at a temperature above approximately 600° C. According to a preferred embodiment, the RTA is performed at a temperature of approximately 1000° C. for a period of between approximately 5 and 10 seconds. Layers47and64advantageously prevent germanium outgassing during annealing.

After high temperature processes associated with portion12are completed, layers47and64can be removed from portion12and conventional integrated circuit processes can be utilized to complete portion12. In one embodiment, layers47and64are removed by dry etching processes. Alternatively, other removal processes can be utilized. In one preferred embodiment, a wet etch process is utilized to remove layer64followed by either a wet etch or a dry etch process to remove layer47.

In one embodiment, portion12can be provided above a silicon-on-insulator (SOI) substrate. The stress in the buried oxide layer associated with the silicon-on-insulator substrate can be modified. The modified stress in the buried oxide layer of the silicon-on-insulator substrate modifies the stress associated with the top silicon layer. The stress in the buried oxide layer can be modified by implanting germanium through the top silicon layer into the buried oxide layer. The stress in the top silicon layer caused by the modified stress in the buried oxide layer improves carrier mobility in the top silicon layer, e.g., forms a strained silicon layer.

In another embodiment, portion12can be provided on a strained silicon-on-insulator substrate manufactured according to an advantageous process. The advantageous process uses plasma enhanced chemical vapor deposition (PECVD) to deposit a silicon dioxide film with compressive stress on a silicon substrate. A handling wafer or handle wafer is oxidized and bonded to the PECVD film and substrate. The substrate is then removed using a Smart Cut™ process, leaving a thin silicon layer on the PECVD oxide. The silicon layer on the PECVD oxide is in tensile stress, thereby operating as a strained layer.

It is understood that although the detailed drawings, specific examples, and particular values given provide exemplary embodiments of the present invention, the exemplary embodiments are for the purpose of illustration only. The method and apparatus in the aforementioned embodiments are not limited to the precise details and descriptions disclosed. For example, although particular sealing materials are described, other types of sealing materials can be utilized. Various changes may be made to the details disclosed without departing from the scope of the invention which is defined by the following claims.