Mask defect analysis for both horizontal and vertical processing effects

A method and system for detecting defects in a physical mask used for fabricating a semiconductor device having multiple layers is disclosed, where each layer has a corresponding mask. The method and system include receiving a digital image of the mask, and automatically detecting edges of the mask in the image using pattern recognition. The detected edges, which are stored in a standard format, are imported along with processing parameters into a process simulator that generates an estimated aerial image of the silicon layout that would be produced by a scanner using the mask and the parameters. The estimated aerial image is then compared to an intended aerial image of the same layer, and any differences found that are greater than predefined tolerances are determined to horizontal defects. In addition, effects that the horizontal defects may have on adjacent layers are analyzed to discover vertical defects.

FIELD OF THE INVENTION

The present invention relates to detecting mask defects in semiconductor masking photolithographic processes, and more particular to analyzing the effects of any detected defects via aerial/latent image simulations using a photograph of the mask as input.

BACKGROUND OF THE INVENTION

An integrated circuit is fabricated by translating a circuit design or layout to a semiconductor substrate. In optical lithography, the layout is first transferred onto a physical template, which is in turn, used to optically project the layout onto a silicon wafer. In transferring the layout to a physical template, a mask is generally created for each layer of the integrated circuit design.

The patterned photomask includes transparent and opaque areas for selectively exposing regions of the photoresist-coated wafer to an energy source. To fabricate a particular layer of the design, the corresponding mask is placed over the wafer and light is shone through the mask from the energy source. The end result is a semiconductor wafer coated with a photoresist layer having the desired pattern that defines the geometries, features, lines and shapes of that layer. The photolithography process is typically followed by an etch process during which the underlying substrate not covered or masked by the photoresist pattern is etched away, leaving the desired pattern in the substrate. This process is then repeated for each layer of the design.

Unfortunately, errors may occur during the manufacture of the masks that result in mask defects. A mask defect is any irregularity in the mask that deviates from the mask design. Using a mask having defects during the photolithography process may produce a circuit pattern on the substrate that fails to accurately represent the intended pattern and that may result in a non-functioning circuit, depending on the severity of the defect. A mask defect that will not result in any appreciable error in a circuit if the mask is used during fabrication is considered a “unprintable” defect, while a severe defect that may result in a fatal error in the circuit is deemed “printable”, causing the mask to be discarded.

As semiconductor devices reach submicron feature sizes, the need to analyze the effects of mask defects has become increasingly important. As is well-known in the art, commercial process simulation software is available that makes it possible to predict the structure of a semiconductor device before actual silicon is available. Examples of process simulation software include TSUPREM-4™ and Taurus-LRC™ by Synopsys, Inc. of Mountain View, Calif. TSUPREM-4 is a 1D/2D process-simulation tool for optimizing IC fabrication processes, and Taurus-LRC is a “lithography rule checker” that verifies that a final mask layout delivers the intended result on silicon. Taurus-LRC also generates the expected silicon layout, which is compared to the intended chip layout. Differences larger than user-defined tolerances are reported as errors.

Process simulation software has also been used in automated inspection systems to detect photomask defects. An example of such a system is disclosed in US Patent Application Publication 2002/0019729 by Chang entitled “Visual Inspection And Verification System,” published Feb. 14, 2002. In this system, an image of a defect portion of a mask and a set of lithography parameters are input to an image simulator. The image simulator generates a simulated image in response to the defect area image and the set of lithography parameters. The simulated image is a simulation of an image that would be printed on a wafer if the wafer were to be exposed to an illumination source directed through the portion of the mask. Chang also discloses generating a second simulated image that is a simulation of the wafer print of the portion of the design mask that corresponds to the portion represented by the defect area image. The first and second simulated images are then compared in order to determine the printability of any identified potential defects on the photolithography mask. A method of determining the process window effect of any identified potential defects is also provided for.

Although the defect detection systems described above are an improvement over visual inspection systems, current methods for detecting mask defects have disadvantages. One disadvantage is related to what is used as the input for the process simulation software. In Chang's system, for example, the mask is scanned with a high-resolution microscope or scanning electron microscope (SEM) and images of areas of the mask around identified potential defects are captured as an image. A digitizing device, such as a frame image grabber, is then used to digitize the data. The process simulation software accepts the digitized data and produces the simulation of a stepper image on a wafer for the physical mask. Chang, however, fails to describe how the features of the mask are extracted from the image. Furthermore, process simulation software typically requires the input data to be in GDSII format, and Chang fails to describe that the digitized data is converted to GDSII format. If the photograph of the mask is not accurately converted, then the input to the image simulation software will be inaccurate, and so will the resulting simulation.

Another problem with current defect detection systems is that although current detection systems can find mask defects, each defect is analyzed for its effect only on the horizontal processing layer on which the defect is located. For example, the conventional approach to analyzing a defect is to generate a simulated image from an image of a physical mask, and compare it with a second simulated image that was produced using the design data of the same mask as input (i.e., a mask that is free from defects). Any differences found are deemed defects and are evaluated for acceptance. Thus, the defects are evaluated to determine the impact the defect will have on the current layer in the circuit, which is known as testing for horizontal or spatial defects. However, as those with ordinary skill in the art will appreciate, mask defects may produce defects that affect adjacent layers in the circuit. Current defect detection systems fail to test for such “vertical effects.”

Accordingly, what is needed is a defect detection system that accurately produces input for a simulation image from a photograph of a physical mask, and that analyzes the printability of the defects in the current horizontal layer as well as the vertically adjacent layers in the circuit design. The present invention addresses such a need.

SUMMARY OF THE INVENTION

The present invention provides a method and system for detecting defects in a physical mask used for fabricating a semiconductor device having multiple layers, where each layer has a corresponding mask. The method and system include receiving a digital image of the mask, and automatically detecting edges of the mask in the image using pattern recognition. The detected edges, which are stored in a standard format, are imported along with processing parameters into a process simulator that generates an estimated aerial image of the silicon layout that would be produced by a scanner using the mask and the parameters. The estimated aerial image is then compared to an intended aerial image of the same layer, and any differences found that are greater than predefined tolerances are determined to be horizontal defects. In addition, the effects that the horizontal defects may have on adjacent layers are analyzed to discover vertical defects.

According to the system and method disclosed herein, the present invention accurately produces input for the process simulator from the image of the physical mask, and analyzes the effects of the defects in the current horizontal layer as well as the vertically adjacent layers in the circuit design.

DETAILED DESCRIPTION

The present invention provides a mask defect detection and analysis system that accurately produces input for a process simulation application from a digital image of a physical mask. The detection system of the present invention also analyzes the printability of the defects in the horizontal layer as well as the vertical layers in the circuit design.

FIG. 1is flow diagram of a mask defect detection and analysis system. The system10includes a graphical user interface (GUI)12, an edge detector14, a process simulator16, a horizontal defect detector18, and a vertical defect detector20. In a preferred embodiment of the present invention, the defect detection and analysis system10is a software application that runs on server in a networked environment (not shown). However, the system may also be adapted to run on other computer systems, such a stand-alone computer PC or workstation.

The process begins with a mask layout database22representing the intended mask design, where the layout typically includes a separate mask for each processing layer in the design. From the mask layout database22, the specified masks are fabricated and images of the masks are taken and stored as digital images in a directory or database. In a preferred embodiment, the physical masks are scanned by an electron microscope or other similar device to produce a set of digitized scanning electron microscope (SEM) images24. Prior to actually using the physical masks to expose a silicon wafer, an operator uses the system10to determine the “printability” of the masks.

When the system10is invoked, the GUI12prompts the operator to select one of the SEM images24on which to perform defect detection and analysis. According to the present invention, rather than inputting the selected SEM image24adirectly into the process simulator16, the SEM image24ais first input to the edge detector14. The edge detector14automatically detects mask edges within the SEM image24ausing pattern recognition. In a preferred embodiment, the edge detector14utilizes a snake algorithm of the present invention to find the mask edges, as explained below.

After the edges of the mask are detected in the SEM image24a, the edges are stored in an edge database26in a standard format, such as GDSII. GDSII is a standard file format for transferring/archiving 2D graphical design data, and is required by the process simulator16. GDSII contains a hierarchy of structures, each structure containing elements (e.g., boundary/polygon, path/polyline, text, box, structure references, and structure array references) that are situated on layers.

The process simulator16imports the edges defining the mask from the edge database26and processing parameters27supplied by the operator through the GUI12, and generates an estimated aerial image28of the silicon layout that would be produced by a scanner using the mask and parameters27. The process simulator16also imports the design data for the selected mask from the mask layout database22and generates an intended aerial image30of the silicon layout that would be produced by a scanner using the mask design. In a preferred embodiment, the estimated aerial image28and the intended aerial image30are stored in first and second databases, respectively, although they could be stored in the same database.

The estimated and intended aerial images28and30are then input to the horizontal defect detector18. The horizontal defect detector18detects defects that could cause errors in the current processing layer by comparing the estimated aerial image28to the intended aerial image30. Any differences that are greater than user-defined tolerances32are defined as horizontal defects. The tolerances preferably define the minimum sizes of defects and the minimum distances that the defects can be to features in the mask.

According to the present invention, if any horizontal defects are found, the vertical defect detector20is then used to analyze the effect that the defects on the current layer have on adjacent processing layers. The GUI12first prompts the operator to select which processing layers are to be analyzed, and receives the operator's selection of layers34. In response, vertical defect detector20inputs the SEM images24corresponding to the selected layers to the process simulator16to generate corresponding estimated aerial images for the selected layers. The vertical defect detector20also inputs the design data for the selected layers from the mask layout22to the process simulator16, which generates intended aerial images30for those layers.

The vertical defect detector20then overlays the estimated aerial image28for the current layer and the estimated aerial images28for the adjacent layers to create an estimated composite aerial image36. The vertical defect detector20also overlays the intended aerial images and generates an intended composite aerial image38. The vertical defect detector20then determines which defects could cause errors in the adjacent layers by comparing the estimated composite aerial image36with the intended composite aerial image38. Any differences that are greater than the user defined tolerances32are defined as vertical defects. The operator may view the output of both the horizontal defect detector18and the vertical defect detector20to determine whether the automatically discovered defects are printable or unprintable.

As stated above, the edges of the masks are accurately found in the mask images24using a snake algorithm. Prior to explaining the snake algorithm used by the edge detector14for finding edges within the SEM images24, a brief description of the input images24will be provided.

FIG. 2Ais a top view of a portion of a sample mask showing two mask features50A and50B, andFIG. 2Bis a cross-sectional view of one of the features50. Sidewalls52defining the mask features50extend out of a substrate by a certain height. In addition, the sidewalls52are typically sloped inward from the bottom of the sidewall52to the top. The bottom of a sidewall52is called the outside edge, and the top of the sidewall52is the inside edge. SEM images24are gray scale images, where pixels defining most of the image have gray values (G), and pixels defining the sidewalls52have white values (W).

According to another aspect of the present invention, The snake algorithm follows edges of the mask through the digital image by iteratively analyzing intensity values of adjacent pixels and selecting the pixels having a highest partial derivative.

Referring now toFIG. 3, a flow chart illustrating the snake algorithm utilized by the edge detector14is shown. The snake algorithm begins finding edges by locating gray/white transitions in the image24. This is accomplished in step100by comparing the pixel values in many rows of the image to discover where one or more white pixel values are preceded and followed by one or more gray pixel values. These transition locations are referred to as “spikes”. In step102, the coordinates of each spike are stored as they are discovered.

After the image24has been scanned for spikes, the algorithm searches the rows adjacent to each spike in an attempt to follow the edges. The algorithm tries to identify the most likely pixel laying in the same general direction as the edge being followed. Following an edge across the image is accomplished in step104by examining the intensity function of several adjacent pixels in the neighboring row and picking the pixel having the highest partial derivative value in the direction perpendicular to the edge.

FIG. 4is a graph of example intensity values for a portion of the pixels in a row of the image, where the highest intensity indicates white and the lowest indicates black. In a preferred embodiment, the partial derivative is found by finding the gradient of the intensity function in the immediate neighborhood of a pixel and multiplying the gradient's magnitude by the sine of the angle between the gradient vector and the direction of the edge.

Referring again toFIG. 3, the algorithm continues following the edge in step106by moving up, down, left, right, or diagonally by one pixel each step. There is a limitation on how tight the algorithm can follow a corner of an edge, but the limitation does not significantly effect edge detection because the corners of features of a real mask image are not sharp. The result of following pixels having the highest partial derivative is that both the outside and inside edges of feature sidewalls52will be found. Once the trail for an edge has ended, the algorithm follows the next edge in the same manner until all edges are traced in step108.

Referring again toFIG. 3, after all the edges are found, in step110, it is determined which groups of edges form individual mask features by dividing the image24into boxes and determining which edges fall within each box. In step112, the edges falling within the same box are paired to form a sidewall. In step114, the pairs of edges that intersect are identified as belonging to the same feature.

In step116, the two edges of each sidewall are labeled as being the outside or inside edge by calculating the length of all edges on each side and determining that the edge set with the longest length is the outside edge set and the other is the inside edge set. In a preferred embodiment, the length is determined from the total coordinate (x, y) span of the edge set.FIG. 5is a diagram illustrating example edge sets. Two pairs of edges intersect if they have an edge in common. Pairs1and2intersect because they share edge B. Hence, they belong to the same feature. Thus, edges A and C are recognized as an edge set for one side of a single feature.

In step118, the outside edges of the features are assigned one color, while the inside edges are assigned another color, and both are overlaid over the SEM image24and displayed to the operator for manual correction. If, for example, a set of edges is identified as inside when it's really outside, the operator may override the decision. In step120, when the operator is done, the inside edges are discarded and the coordinates for the outside edges of each feature are stored in the edge database26in GDSII format.

A method and system for performing mask defect analysis has been disclosed. The present invention has been described in accordance with the embodiments shown, and one of ordinary skill in the art will readily recognize that there could be variations to the embodiments, and any variations would be within the spirit and scope of the present invention. In addition, software written according to the present invention may be stored on a computer-readable medium, such as a removable memory, or transmitted over a network, and loaded into a computer for execution. Accordingly, many modifications may be made by one of ordinary skill in the art without departing from the spirit and scope of the appended claims.