Mixer-based timebase for sampling multiple input signal references asynchronous to each other

Sampling is performed. A strobe signal is generated from a first signal. Multiple sampled signals are sampled using the strobe signal. Each of the multiple sampled signals is synchronous with its own clock reference and each of clock references are asynchronous with respect to each other. Analog-to-digital conversion is performed on each sampled value of each of the multiple sampled signals. For each of the clock references that is not synchronous with the first signal, a phase comparison is performed between the clock reference and the first signal to produce a difference value. The difference value indicates a phase difference between the clock reference and the first signal. Analog-to-digital conversion of the difference value is performed at a frequency determined by the strobe signal.

BACKGROUND

The present invention concerns sampling methods used within electronic instruments such as oscilloscopes and pertains particularly to a mixer-based timebase for sampling multiple input signal references asynchronous to each other. Eye diagram analysis is an important tool for studying the behavior of high-speed digital electrical and optical communications signals. An eye diagram is a way of displaying on an oscilloscope the waveform shapes of all logic one-zero combinations. It is generated by applying a data waveform to the vertical channel of an oscilloscope while triggering from a synchronous clock signal.

Currently, at data rates below about 3 gigabits per second (Gb/s), real-time sampling oscilloscopes are commonly used. A real-time sampling oscilloscope employs a very high speed analog-to-digital (A/D) converter to capture a waveform record consisting of a complete sequence of successive data bits. The advantage of real-time sampling is that it allows visualization of the exact characteristics of a data pattern such as slow risetime or excessive overshoot.

The A/D converter in a real time sampling oscilloscope must sample the waveform much faster than the data rate. Shannon's sampling theorem states that to unambiguously reconstruct a sine wave the sample rate must be at least twice the signal frequency. In reality, since digital data signals are not simple sine waves, an even higher sampling rate must be used. Most commercial real-time sampling oscilloscopes employ sampling rates of 4-10 times the data rate.

Currently, the fastest commercial real-time sampling oscilloscopes on the market today are limited to about 6 gigahertz (GHz) bandwidth and 20 gigasamples (GSamp/s) sample rates. This bandwidth is useful only for data rates up to about 2.5 gigabits (Gb/s). For higher data rates, equivalent-time sampling technology is used.

One type of architecture used in an equivalent-time sampling system utilizes sequential timebase circuitry that performs a sequential timebase operation such as detecting a synchronous trigger event (such as a rising or falling edge in the applied trigger signal) and generating a precision programmable delay between the trigger event and the sample strobe. The precision delay generator is typically divided into a course and fine delay generator. Samples are taken at varying times determined by the timebase delay. Each trigger event causes the oscilloscope to take a single sample of the data waveform and display the sample as a single point on the screen. Each subsequent sample point (following a new trigger event) is increasingly delayed relative to the time of the trigger. After numerous trigger events, the oscilloscope fills the display with a sampled representation of the data pattern.

Another type of architecture used in an equivalent-time sampling system utilizes pseudo-random timebase circuitry that performs pseudo-random timebase operations. In pseudo-random timebase operations, the timing of the samples is typically not related to the repetitive signal input. The position of each sample on the time axis of the oscilloscope display is obtained by measuring the timing of each sample relative to an applied reference signal. See, for example U.S. Pat. No. 4,884,020 where a sinusoidal reference is sampled in quadrature to precisely determine the timing of the samples. For additional background information on random electrical sampling, see, for example, U.S. Pat. Nos. 5,315,627, 4,928,251, 4,719,416, 4,578,667 and 4,495,586.

The components used in timebase circuitry in existing sampling systems are quite complex and expensive. When multiple signals such as parallel optical signals in a very short reach (VSR) application are to be sampled and the signals are asynchronous to each other, these expensive components are generally duplicated. It is desirable, therefore, to more economically implement timebase circuitry for multiple asynchronous signals.

SUMMARY OF THE INVENTION

In accordance with the preferred embodiment of the present invention, sampling is performed. A strobe signal is generated from a first signal. Multiple sampled signals are sampled using the strobe signal. Each of the multiple sampled signals is synchronous with its own clock reference and each of the clock references are asynchronous with respect to each other. Analog-to-digital conversion is performed on each sampled value of each of the multiple sampled signals. For each of the clock references that is not synchronous with the first signal, a phase comparison is performed between the clock reference and the first signal to produce a difference value. The difference value indicates a phase difference between the clock reference and the first signal. Analog-to-digital conversion of the difference value is performed at a frequency determined by the strobe signal.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

FIG. 1shows timebase circuitry that can be used for multiple channels operating asynchronously to one another.

InFIG. 1, a sampler (S)12samples a sample channel signal11. An A/D converter13generates a digital value representing the analog voltage of the sample channel signal11at each sampling time. These digital values are stored for use in signal display and analysis. For example, sampler12is implement by a fast switch and a storage component. In some embodiments, sampler12also can include a step recover diode (SRD) to generate a short sample aperture. A/D converter13includes for example, amplification and filtering capability to accurately capture and convert the signals.

A sampler (S)22samples a sample channel signal21. An A/D converter23generates a digital value representing the analog voltage of the sample channel signal21at each sampling time. These digital values are stored for use in signal display and analysis.

A sampler (S)32samples a sample channel signal31. An A/D converter33generates a digital value representing the analog voltage of the sample channel signal31at each sampling time. These digital values are stored for use in signal display and analysis.

A sampler (S)42samples a sample channel signal41. An A/D converter43generates a digital value representing the analog voltage of the sample channel signal41at each sampling time. These digital values are stored for use in signal display and analysis.

A clock reference14is synchronous with sample channel signal11. A low pass filter (LPF)49, if necessary, can be used to remove any noise and/or harmonics within clock reference14. Low pass filter49can be implemented in hardware. Alternatively, the function of low pass filter49can be implemented in the software used to process information gathered about clock reference14. When clock reference14is a sufficiently clean sinusoid, low pass filter49can be omitted.

Trigger and timebase circuitry15is used to produce a strobe signal used to control timing of samples by sampler12, sampler22, sampler32, sampler42, A/D converter28, A/D converter38and A/D converter48. Trigger and timebase circuitry15includes, for example, a sequential timebase circuit or a pseudo-random timebase circuit.

For example, in alternative embodiments of the present invention, trigger and timebase circuitry15can include a frequency divider that is implemented by a phase locked loop, a counter or some other circuitry that accomplishes division of signal frequency.

WhileFIG. 1shows only sample channel signal11, sample channel signal21, sample channel signal31, sample channel signal41and corresponding timebase portions, as represented by a line16, and lines17, trigger and timebase circuitry15can supply the strobe signal to additional samplers and corresponding timebase portions facilitating the sampling of additional asynchronous sample channel signals. Embodiments of the present invention also can be implemented with only two or three sample channels.

In the embodiment of the present invention shown inFIG. 1, no additional trigger and timebase circuitry in addition to trigger and timebase circuitry15is required to perform equivalent time sampling scope measurements on multiple signals in parallel where each signal is accompanied by a synchronous clock reference, but where the multiple clock references are asynchronous with respect to each other. This is advantageous in the case where, for example, manufacturing tests are performed simultaneously on two or more independent transceiver modules. This is also advantageous in the case where, for example, there are parallel optics modules in which the individual channels are asynchronous with each other. The ability to measure asynchronous signals simultaneously can dramatically reduce manufacturing test time.

To measure asynchronous signals simultaneously, trigger and timebase circuitry15can be duplicated multiple times, one for each of the asynchronous clock references. However, the components used to implement trigger and timebase circuitry15are typically expensive, complicated and sensitive.

In the present invention, therefore, an RF phase detector or mixer is used to determine the relative phase difference between clock reference14and clock references for the other clock references. Trigger and timebase circuitry15determines the timing of the samples within a period of clock reference14, and each mixer determines the relative phase difference between the clock reference14and the other clock references. This phase difference is then used to precisely establish the timing of the sample within a period of clock reference14.

A clock reference24is synchronous with sample channel signal21. A low pass filter (LPF)25is used to remove any noise and/or harmonics within clock reference24. Low pass filter25can be implemented in hardware. Alternatively, the function of low pass filter25can be implemented in the software used to process information gathered about clock reference24. Provided clock reference24is a sufficiently clean sinusoid, low pass filter25may be omitted.

A mixer26performs a mix operation between the frequency signal generated by clock reference14and clock reference24producing an intermediate frequency (IF) that is the sum and difference of frequencies input to mixer26. A low pass filter (LPF)27removes the sum component of the mixed signal, leaving the difference component of the mixed signal. The difference component of the mixed signal indicates the frequency difference between clock reference24and the frequency signal generated by clock reference14. Mixer26and LPF27together function as a phase comparator. While in the frequency domain, the output of the phase comparator is the frequency difference between clock reference24and the frequency signal generated by clock reference14, in the time domain, the output of the phase comparator is the instantaneous phase difference between clock reference24and the frequency signal generated by clock reference14.

A/D converter28generates digital values indicating the frequency difference. When the frequency difference between clock reference24and clock reference14is small, the difference component of the mixed signal will be low frequency, allowing A/D converter28and any other following processing circuitry to operate at low frequency. Low frequency operation allows for a significant cost savings in components.

Typically the frequency difference between the clock references is small when testing multiple devices centered around the same rate (e.g., OC-192 at 9.95328 gigabits per second). Typically when testing a parallel optics device, the clock reference for each of the individual channels will be at the same rate; however they are often not phase locked to each other. Any small drift in frequency or phase between clocks14and24is detected by mixer26and compensated for.

A clock reference34is synchronous with sample channel signal31. A low pass filter (LPF)35is used to remove any noise and/or harmonics within clock reference34. A mixer36performs a mix operation between the frequency signal generated by clock reference14and clock reference34. A low pass filter (LPF)37removes the sum component of the mixed signal, leaving the difference component of the mixed signal. An A/D converter38generates digital values indicating the frequency difference.

A clock reference44is synchronous with sample channel signal41. A low pass filter (LPF)45is used to remove any noise and/or harmonics within clock reference44. A mixer46performs a mix operation between the frequency signal generated by clock reference14and clock reference44. A low pass filter (LPF)47removes the sum component of the mixed signal, leaving the difference component of the mixed signal. An A/D converter48generates digital values indicating the frequency difference.

FIG. 2is a simplified block diagram of sampling circuitry within an electronic device in accordance with another alternative preferred embodiment of the present invention. In the embodiment shown inFIG. 2, a sampling oscillator50and a frequency divider59are used to perform pseudo-random sampling.

A sampler (S)52samples a sample channel signal51. An A/D converter53generates a digital value representing the analog voltage of the sample channel signal51at each sampling time. These digital values are stored for use in signal display and analysis. For example, sampler52is implemented by a fast switch and a storage component. In some embodiments, Sampler52also can include a step recover diode (SRD) to generate a short sample aperture. A/D converter53includes for example, amplification and filtering capability to accurately capture and convert the signal.

A sampler (S)62samples a sample channel signal61. An A/D converter63generates a digital value representing the analog voltage of the sample channel signal61at each sampling time. These digital values are stored for use in signal display and analysis.

A sampler (S)72samples a sample channel signal71. An A/D converter73generates a digital value representing the analog voltage of the sample channel signal71at each sampling time. These digital values are stored for use in signal display and analysis.

Sampling oscillator50generates a high frequency signal that is frequency divided by frequency divider59in order to produce a sampling signal used to control timing of samples by sampler52, sampler62, sampler72, A/D converter58, A/D converter68and A/D converter78. For example, frequency divider59is implemented by a phase locked loop, a counter or some other circuitry that accomplishes division of signal frequency. In this case, for example, the trigger system includes frequency divider59, the sampling signal produced by frequency divider59is a strobe signal and sampling oscillator50produces a signal from which the strobe signal is generated. Provided sampler52, sampler62, sampler72, A/D converter58, A/D converter68and A/D converter78are able to operate within the frequency range of sampling oscillator50, frequency divider59can be omitted. In this case, the signal produced by sampling oscillator50is identical with the strobe signal and the trigger system delivers the first signal as the strobe signal.

WhileFIG. 2shows only sample channel signal51, sample channel signal61, sample channel signal71, and corresponding timebase portions, as represented by a line70, and lines60, frequency divider59can supply the sampling signal to additional samplers and corresponding timebase portions facilitating the sampling of additional asynchronous sample channel signals. Embodiments of the present invention also can be implemented with only two sample channels.

A clock reference54is synchronous with sample channel signal51. A low pass filter (LPF)55is used to remove any noise and/or harmonics within clock reference54. Low pass filter55can be implemented in hardware. Alternatively, the function of low pass filter55can be implemented in the software used to process information gathered about clock reference54. Provided clock reference54is a sufficiently clean sinusoid, low pass filter55may be omitted.

An RF mixer56performs a mix operation between the high frequency signal generated by sampling oscillator50and clock reference54producing an intermediate frequency (IF) that is the sum and difference of frequencies input to mixer56. A low pass filter (LPF)57removes the sum component of the mixed signal, leaving the difference component of the mixed signal. The difference component of the mixed signal indicates the frequency difference between clock reference54and the high frequency signal generated by sampling oscillator50. Mixer56and LPF57together function as a phase comparator. While in the frequency domain, the output of the phase comparator is the frequency difference between clock reference54and the high frequency signal generated by sampling oscillator50, in the time domain, the output of the phase comparator is the instantaneous phase difference between clock reference54and the high frequency signal generated by sampling oscillator50.

An A/D converter58generates digital values indicating the phase difference. When the phase difference between clock reference54and the high frequency signal generated by sampling oscillator50is small, the difference component of the mixed signal will be low frequency, allowing A/D converter58and any other following processing circuitry to operate at low frequency. Low frequency operation allows for a significant cost savings in components.

A clock reference64is synchronous with sample channel signal61. A low pass filter (LPF)65is used to remove any noise and/or harmonics within clock reference64. An RF mixer66performs a mix operation between the high frequency signal generated by sampling oscillator50and clock reference64. A low pass filter (LPF)67removes the sum component of the mixed signal, leaving the difference component of the mixed signal. An A/D converter68generates digital values indicating the phase difference at each time sample channel signal61is sampled.

A clock reference74is synchronous with sample channel signal71. A low pass filter (LPF)75is used to remove any noise and/or harmonics within clock reference74. An RF mixer76performs a mix operation between the high frequency signal generated by sampling oscillator50and clock reference74. A low pass filter (LPF)77removes the sum component of the mixed signal, leaving the difference component of the mixed signal. An A/D converter78generates digital values indicating the phase difference at each time sample channel signal71is sampled.

FIG. 3is a flowchart that describes determination of timing data for each channel from information obtained and stored by the A/D converters. The process starts in a block101.

In a block102, the nominal data rate (also called the bit rate) of the sample channels are determined and sampling oscillator50is set to a corresponding frequency. For example, a user indicates the nominal data rate or it is derived from an incoming signal. For example, the user indicates the nominal data rate is 9.95324 Gb/s as defined by the SONET OC-192 standard. Alternatively, the bit rate can be derived from one of the clock references. For example, for sample channel signal51, the bit rate can be determined by the frequency of clock reference54. For sample channel signal61, the bit rate can be determined by the frequency of clock reference64. For sample channel signal71, the bit rate can be determined by the frequency of clock reference74. When there is no sampling oscillator (as inFIG. 1) it is not necessary to determine a nominal data rate and block102can be omitted.

In a block103, samples of the mixer channel are taken simultaneously with samples of the data channels. For example, A/D converter53captures sampled data channel voltage values of SK(where K ranges from 0 to N). Simultaneously A/D converter58captures sampled mixer channel voltage values of a0, a1, a2, . . . aN.

In a block104, a sinusoid waveform is fitted to the mixer samples (a0, a1, a2, . . . aN). For example, the sinusoidal waveform (IF(t)) has a form as set out in Equation 1 below, where A represents amplitude, (ω represents frequency and t represents time.
IF(t)=A*cos(ω*t)  Equation 1

Where amplitude and/or frequency of clock referenced54,64and74change over time, using a narrow time window of data to calculate the form of the sinusoidal waveform (IF(t)) allows detection of and correction for the change. Thus adjusting the time window can improve accuracy.

In a block105, an inverse of the sinusoidal waveform is calculated. For each sampled mixer channel voltage value (aK) that occurs in the fitted sinusoidal waveform between 0 and π, the inverse (IK) is calculated using Equation 2 below:
IK=arccos(aK/A)  Equation 2

For each sampled mixer channel voltage value (SK) that occurs in the fitted sinusoidal waveform between π and 2π, the inverse (IK) is calculated using Equation 3 below:
IK=2π−arccos(aK/A)  Equation 3

In a block106, for each of the mixer samples (a0, a1, a2, . . . aN), a phase is determined from the inverse of the sinusoidal waveform, calculated in block105.

In a block107, for each of the mixer channel voltage values (a0, a1, a2, . . . aN), the phase calculated in block106is converted to a bit period unit interval (UI). For example, this is accomplished using Equation 4 below.
UI(aK)=(IK)/(2*π)  Equation 4

In a block108, the data samples are used to represent the sampled data.

The sampled data may be displayed. For example, when displaying each data sample, the vertical component is determined by the sampled data channel voltage values of SKand the horizontal component is determined by the bit period interval UI(aK).

Alternatively, the horizontal component may be represented in seconds instead of unit intervals by dividing the unit intervals calculated in Equation 4 by the bit rate (determined in block102) to convert unit intervals to seconds.

The sampled data also can be used for additional measurements and/or manipulated to provide further information about the sample channel signal.

In a block109, the process is completed.

For the sampling circuitry shown inFIG. 2, sampler52, sampler62and sampler72operate at a sampling frequency, for example, of approximately 40 kilohertz (kHz). In such a system, the frequency of the signal received by each of A/D converter58, A/D converter68and A/D converter78, needs to be 20 kHz or less in order to provide adequate resolution of the captured signal.

The foregoing discussion discloses and describes merely exemplary methods and embodiments of the present invention. As will be understood by those familiar with the art, the invention may be embodied in other specific forms without departing from the spirit or essential characteristics thereof. Accordingly, the disclosure of the present invention is intended to be illustrative, but not limiting, of the scope of the invention, which is set forth in the following claims.