Programmable memory and forming method thereof

An array of electrically erasable programmable read only memory (EEPROM) includes a first row of floating gate, a second row of floating gate, two spacers, a first row of word line and a second row of word line. The first row of floating gate and the second row of floating gate are disposed on a substrate along a first direction. The two spacers are disposed between and parallel to the first row of floating gate and the second row of floating gate. The first row of word line is sandwiched by one of the spacers and the adjacent first row of floating gate, and the second row of word line is sandwiched by the other one of the spacers and the adjacent second row of floating gate. The present invention also provides a method of forming said array of electrically erasable programmable read only memory (EEPROM).

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates generally to an array of memory cells and forming method thereof, and more specifically to an array of electrically erasable programmable read only memory (EEPROM) cells and forming method thereof.

2. Description of the Prior Art

Memory devices include volatile memory devices and nonvolatile memory devices. Volatile memory devices can be classified into Dynamic Random Access Memory (DRAM) and Static Random Access Memory (SRAM). Nonvolatile memory devices may include Electrically Erasable Programmable Read Only Memory (EEPROM) devices, Ferroelectric Random Access Memory (FeRAM) devices, Phase-change Random Access Memory (PRAM) devices, Magnetic Random Access Memory (MRAM) devices and Flash Memory devices.

SUMMARY OF THE INVENTION

The present invention provides an array of electrically erasable programmable read only memory (EEPROM) and forming method thereof, which forms word lines between spacers by self-aligning, to avoid the non-uniformity of the widths of the word lines caused by the shiftings while patterning.

The present invention provides an array of electrically erasable programmable read only memory (EEPROM) including a first row of floating gate, a second row of floating gate, two spacers, a first row of word line and a second row of word line. The first row of floating gate and the second row of floating gate are disposed on a substrate along a first direction. The spacers are disposed between and parallel to the first row of floating gate and the second row of floating gate. The first row of word line is sandwiched by one of the spacers and the adjacent first row of floating gate, and the second row of word line is sandwiched by the other one of the spacers and the adjacent second row of floating gate.

The present invention provides an array of electrically erasable programmable read only memory (EEPROM) including a first floating gate, a second floating gate, two spacers, a first word line and a second word line. The first floating gate and the second floating gate are disposed on a substrate. The spacers are disposed between the first floating gate and the second floating gate. The first word line is sandwiched by one of the spacers and the adjacent first floating gate, and the second word line is sandwiched by the other one of the spacers and the adjacent second floating gate.

The present invention provides a method of forming an array of electrically erasable programmable read only memory (EEPROM) including the following steps. A first floating gate, a dummy floating gate and a second floating gate are formed on a substrate. Spacers are formed on sidewalls of the dummy floating gate, and first spacers are formed on sidewalls of the first floating gate and the second floating gate. An electrode layer fills in space between the first floating gate, the dummy floating gate and the second floating gate. The dummy floating gate is removed.

According to the above, the present invention provides an array of electrically erasable programmable read only memory (EEPROM) and forming method thereof, which forms a first floating gate, a dummy floating gate and a second floating gate on a substrate; forms spacers on sidewalls of the dummy floating gate, and forms first spacers on sidewalls of the first floating gate and the second floating gate; fills an electrode layer in space between the first floating gate, the dummy floating gate and the second floating gate. By doing this, a part of the electrode layer between one of the spacers and the adjacent first floating gate serves as a first word line, and a part of the electrode layer between the other one of the spacers and the adjacent second floating gate serves as a second word line. By forming word lines between spacers by self-aligning, the non-uniformity of the widths of the word lines caused by the shiftings while patterning can be avoided.

DETAILED DESCRIPTION

The present invention provides an array of electrically erasable programmable read only memory (EEPROM) with spacers, to form self-aligned word lines and avoid the shiftings of the word lines.

FIG.1schematically depicts a top view of an array of electrically erasable programmable read only memory (EEPROM) according to an embodiment of the present invention.FIG.2schematically depicts a cross-sectional view of an array of electrically erasable programmable read only memory (EEPROM) according to an embodiment of the present invention.FIG.2is a cross-sectional view ofFIG.1along line AA′. Please refer toFIG.1andFIG.2, the array of electrically erasable programmable read only memory (EEPROM) in this embodiment is arranged regularly and repeatedly, so only one part is described.

Please refer toFIGS.1-2, a substrate110is provided, wherein the substrate110may be a semiconductor substrate such as a silicon substrate, a silicon containing substrate, a III-V group-on-silicon (such as GaN-on-silicon) substrate, a graphene-on-silicon substrate, a silicon-on-insulator (SOI) substrate or a substrate containing epitaxial layers. In this embodiment, only the substrate110of an electrically erasable programmable read only memory (EEPROM) area is depicted.

A first row of floating gate122and a second row of floating gate124are disposed on the substrate110along a first direction x. In this embodiment, the first row of floating gate122and the second row of floating gate124are constituted by several island parts. The first row of floating gate122and the second row of floating gate124include stacked structures respectively. In this case, the first row of floating gate122includes a dielectric layer122a, a floating gate layer122band a hard mask122cstacked from bottom to top, and the second row of floating gate124includes a dielectric layer124a, a floating gate layer124band a hard mask124cstacked from bottom to top. The dielectric layer122aand the dielectric layer124amay be oxide layers, the floating gate layer122band the floating gate layer124bmay be polysilicon layers, and the hard mask122cand the hard mask124cmay be nitride layers, but it is not limited thereto. In another embodiment, the stacked structures of the first row of floating gate122and the second row of floating gate124can be replaced by gates. As shown inFIG.9, a gate220includes a dielectric layer222, a bottom floating gate layer224, an oxide/nitride/oxide (ONO) layer226, a control gate layer228and a hard mask229stacked from bottom to top, wherein the dielectric layer222is an oxide layer, the bottom floating gate layer224is a polysilicon layer, the oxide/nitride/oxide (ONO) layer226is an oxide layer, a nitride layer and an oxide layer stacked from bottom to top, the control gate layer228is a polysilicon layer, and the hard mask229is a nitride layer, but it is not limited thereto.

Please refer toFIGS.1-2, spacers20are disposed between and parallel to the first row of floating gate122and the second row of floating gate124. First spacers40are disposed on sidewalls of the first row of floating gate122and the second row of floating gate124. A first row of word line WL1is sandwiched by one of the spacers20and the adjacent first row of floating gate122, and a second row of word line WL2is sandwiched by the other one of the spacers20and the adjacent second row of floating gate124. The spacers20and the first spacers40sandwich the first row of word line WL1and the second row of word line WL2, so the first row of word line WL1and the second row of word line WL2both have cross-sectional views broaden from bottom to top, wherein widths W1of top surfaces T1of the first row of word line WL1and the second row of word line WL2are larger than widths W2of bottom surfaces T2of the first row of word line WL1and the second row of word line WL2. Since the first row of word line WL1and the second row of word line WL2are formed self-alignedly using the spacers20and the first spacers40, the non-uniformity of the width W1of the first row of word line WL1and the width W2of the second row of word line WL2caused by the shiftings while patterning can be avoided.

A first row of erase gate132is disposed right next to the first row of floating gate122opposite to the first row of word line WL1, and a second row of erase gate134is disposed right next to the second row of erase gate134opposite to the second row of word line WL2. Source lines SL are located in the substrate110along the first direction x and right below the first row of erase gate132and the second row of erase gate134. Bit line contacts BLC are disposed between the two spacers20. Bit lines BL are disposed in the substrate110along a second direction y, wherein the second direction y is orthogonal to the first direction x. Each of the bit line contacts BLC contacts the corresponding bit line BL directly.

A method of forming an array of electrically erasable programmable read only memory (EEPROM)100is presented.FIGS.3-8schematically depict cross-sectional views of a method of forming an array of electrically erasable programmable read only memory (EEPROM) according to an embodiment of the present invention. As shown inFIG.3, a first floating gate320a, a dummy floating gate320band a second floating gate320care formed on a substrate310. In this embodiment, a stacked structure ofFIG.9is applied, but the stacked structure can be replaced by a stacked structure ofFIG.2, so that a stacked structure including a first floating gate320a, a dummy floating gate320band a second floating gate320cis provided. The first floating gate320aincludes a dielectric layer322a, a bottom floating gate layer324a, an oxide/nitride/oxide (ONO) layer326a, a control gate layer328aand a hard mask (not shown) stacked from bottom to top. The dummy floating gate320bincludes a dielectric layer322b, a bottom floating gate layer324b, an oxide/nitride/oxide (ONO) layer326b, a control gate layer328band a hard mask (not shown) stacked from bottom to top. The second floating gate320cincludes a dielectric layer322c, a bottom floating gate layer324c, an oxide/nitride/oxide (ONO) layer326c, a control gate layer328cand a hard mask (not shown) stacked from bottom to top. In this embodiment, methods of forming the first floating gate320a, the dummy floating gate320band the second floating gate320cmay include depositing and patterning gate layers such as a dielectric layer, a bottom floating gate layer, an oxide/nitride/oxide (ONO) layer, a control gate layer and a hard mask, to form the first floating gate320a, the dummy floating gate320band the second floating gate320c, but it is not limited thereto.

As shown inFIG.4, spacers P are formed on sidewalls S1of the dummy floating gate320b, and first spacers P1are formed on sidewalls S2of the first floating gate320aand the second floating gate320c. The spacers P and the first spacers P1may include nitride spacers or oxide spacers etc. Thicknesses of the formed spacers P and the formed first spacers P1depend on the density of these stacked structures.

As shown inFIG.5, source lines SL1are located in the substrate110beside the first floating gate320aopposite to the dummy floating gate320b, and in the substrate110beside the second floating gate320copposite to the dummy floating gate320b. A photoresist Q1may be formed to cover parts except for areas for forming the source lines SL1, the source lines SL1are formed by implant processes, and then the photoresist Q1is removed.

As shown inFIG.6, an electrode layer330fills in space between the first floating gate320a, the dummy floating gate320band the second floating gate320c, wherein a part of the electrode layer330between one of the spacers P and the adjacent first floating gate320aserves as a first word line WL3, and a part of the electrode layer330between the other one of the spacers P and the adjacent second floating gate320cserves as a second word line WL4. A part of the electrode layer330right next to the first floating gate320aopposite to the first word line WL3serves as a first erase gate330a, and a part of the electrode layer330right next to the second floating gate320copposite to the second word line WL4serves as a second erase gate330b.

Methods of filling the electrode layer330in space between the first floating gate320a, the dummy floating gate320band the second floating gate320cmay include depositing and planarizing the electrode layer330on the substrate310, and then etching back the electrode layer330, to ensure the first floating gate320a, the dummy floating gate320band the second floating gate320cbeing exposed. The spacers P and the first spacers P1are formed in the present invention, and the first word line WL3and the second word line WL4are self-aligned between the spacers P and the first spacers P1, so that the non-uniformity of the widths of the first word line WL3and the second word line WL4caused by the shiftings while patterning can be avoided.

Then, the dummy floating gate320bis removed to form a recess R, as shown inFIG.7. For example, a photoresist Q2is formed to cover areas except for the dummy floating gate320b, and then the dummy floating gate320bis removed.

As shown inFIG.8, a bit line BL1is formed in the substrate310between the spacers P, wherein the bit line BL1may include a lightly doped region12, a halo implantation region14and a source/drain16. The lightly doped region12, the halo implantation region14and the source/drain16may be formed by implantation processes. Then, the photoresist Q2is removed. The bit line contacts BLC ofFIG.1may be formed on the bit lines BL1.

To summarize, the present invention provides an array of electrically erasable programmable read only memory (EEPROM) and forming method thereof, which forms a first floating gate, a dummy floating gate and a second floating gate on a substrate; forms spacers on sidewalls of the dummy floating gate, and forms first spacers on sidewalls of the first floating gate and the second floating gate; fills an electrode layer in space between the first floating gate, the dummy floating gate and the second floating gate. By doing this, a part of the electrode layer between one of the spacers and the adjacent first floating gate serves as a first word line, and a part of the electrode layer between the other one of the spacers and the adjacent second floating gate serves as a second word line. A part of the electrode layer right next to the first floating gate opposite to the first word line serves as a first erase gate, and a part of the electrode layer right next to the second floating gate opposite to the second word line serves as a second erase gate. By forming word lines between spacers by self-aligning, the non-uniformity of the widths of the word lines caused by the shiftings while patterning can be avoided. After the dummy floating gate is removed, the bit lines and the bit line contacts may be formed between the spacers.