BUFFER CIRCUIT, AND SEMICONDUCTOR APPARATUS CAPABLE OF ADJUSTING A CLOCK RECEIVER AND/OR CHANGING A CLOCK PATH ACCORDING TO FREQUENCY INFORMATION

A semiconductor apparatus includes a frequency control circuit and an internal clock generation circuit. The frequency control circuit generates a frequency information signal based on a command address signal, and generates a frequency control signal by comparing the frequency information signal with a frequency setting signal. The internal clock generation circuit generates an internal clock signal from a system clock signal based on the frequency control signal.

CROSS-REFERENCES TO RELATED APPLICATION

The present application claims priority under 35 U.S.C. § 119(a) to Korean application number 10-2023-0102887, filed on Aug. 7, 2023, in the Korean Intellectual Property Office, which is incorporated herein by reference in its entirety.

BACKGROUND

1. Technical Field

The present disclosure relates to an integrated circuit technology, and more particularly, to a buffer circuit and a semiconductor apparatus capable of adjusting a clock receiver and/or changing a clock path according to frequency information.

2. Related Art

Electronic devices may include many electronic components, and among the electronic devices, a computer system may include many semiconductor apparatuses made of semiconductors. The semiconductor apparatuses constituting the computer system may perform data communication in synchronization with a clock signal. One semiconductor apparatus may transmit data in synchronization with the clock signal, and another semiconductor apparatus connected to the one semiconductor apparatus may receive the data in synchronization with the clock signal.

In order to improve a data communication rate, the frequency of the clock signal used in the computer system continuously increases. In general, a current mode logic (CML) buffer is used for propagation of a clock signal having a high frequency, and a complementary metal-oxide-semiconductor (CMOS) buffer is used for propagation of a clock signal having a low frequency. The CML buffer has large power consumption, and the CMOS buffer is not able to transmit the clock signal having a high frequency without loss. Accordingly, the trade-off relationship between stable propagation of the clock signal and power consumption reduction needs to be optimized according to the frequency of the clock signal used in the computer system.

SUMMARY

A semiconductor apparatus in accordance with an embodiment may include a frequency detector, a first frequency control signal generator, a second frequency control signal generator, and an internal clock generation circuit. The frequency detector may be configured to generate a frequency information signal based on a command address signal. The first frequency control signal generator may be configured to compare a first frequency setting signal with the frequency information signal to generate a first frequency control signal. The second frequency control signal generator may be configured to compare a second frequency setting signal with the frequency information signal to generate a second frequency control signal. The internal clock generation circuit may be configured to generate an internal clock signal from a system clock signal based on the first and second frequency control signals.

A semiconductor apparatus in accordance with an embodiment may include a frequency control circuit and a clock receiver. The frequency control circuit may be configured to generate a frequency information signal based on a command address signal and configured to compare a first frequency setting signal with the frequency information signal to generate a first frequency control signal. The clock receiver may be configured to receive a system clock signal to generate a received clock signal, to increase an AC gain of the clock receiver when the first frequency control signal is enabled, and to increase a DC gain of the clock receiver when the first frequency control signal is disabled.

A semiconductor apparatus in accordance with an embodiment may include a frequency control circuit, a clock receiver, a first clock path, and a second clock path. The frequency control circuit may be configured to generate a frequency information signal based on a command address signal and configured to compare a first frequency setting signal with the frequency information signal to generate a first frequency control signal. The clock receiver may be configured to receive a system clock signal to generate a received clock signal. The first clock path may be configured to buffer the received clock signal at a current mode logic (CML) level to generate a first differential clock signal pair when the first frequency control signal is enabled; and a second clock path configured to buffer the received clock signal at a complementary metal-oxide-semiconductor (CMOS) level to generate a second differential clock signal pair when the first frequency control signal is disabled.

A semiconductor apparatus in accordance with an embodiment may include a clock receiver configured to receive a system clock signal to generate a received clock signal, to increase a gain of the clock receiver when a frequency of the system clock signal is a first frequency, and to increase a gain of the clock receiver when a frequency of the system clock signal is a second frequency. The first frequency may be greater than the second frequency.

DETAILED DESCRIPTION

It will be understood that although the terms first, second, third etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element, but not used to define only the element itself or to mean a particular sequence.

FIG.1is a block diagram illustrating a configuration of a semiconductor system100in accordance with an embodiment of the present disclosure. Referring toFIG.1, the semiconductor system100may include a first semiconductor apparatus110and a second semiconductor apparatus120. The first semiconductor apparatus110may be a master device that provides various control signals required for operating the second semiconductor apparatus120. The second semiconductor apparatus120may be a slave device that performs various operations under the control of the first semiconductor apparatus110. The first semiconductor apparatus110may include various types of host devices. For example, the first semiconductor apparatus110may include a central processing unit (CPU), a graphics processing unit (GPU), a multi-media processor (MMP), a digital signal processor, an application processor (AP), and a memory controller. The second semiconductor apparatus120may be, for example, a memory apparatus, and the memory apparatus may include a volatile memory and a nonvolatile memory. Examples of the volatile memory may include a static RAM (SRAM), a dynamic RAM (DRAM), and a synchronous DRAM (SDRAM), and examples of the nonvolatile memory may include a read only memory (ROM), a programmable ROM (PROM), an electrically erasable and programmable ROM (EEPROM), an erasable programmable ROM (EPROM), a flash memory, a phase change RAM (PRAM), a magnetic RAM (MRAM), a resistive RAM (RRAM), a ferroelectric RAM (FRAM), and the like.

The second semiconductor apparatus120may be coupled to the first semiconductor apparatus110through a plurality of buses. The plurality of buses may be signal transmission paths, links, or channels for transmitting signals. The plurality of buses may include a clock bus101, a command address bus102, a data bus103, and the like. The clock bus101and the command address bus102may be unidirectional buses from the first semiconductor apparatus110to the second semiconductor apparatus120, and the data bus103may be a bidirectional bus. The second semiconductor apparatus120may be coupled to the first semiconductor apparatus110through the clock bus101, and may receive a system clock signal SCK through the clock bus101. In an embodiment, the system clock signal SCK may be transmitted together with a system clock bar signal SCKB. The second semiconductor apparatus120may be coupled to the first semiconductor apparatus110through the command address bus102, and may receive a command address signal CA from the first semiconductor apparatus110through the command address bus102. The command address signal CA may include a plurality of bits. The first semiconductor apparatus110may transmit the command address signal CA based on the system clock signal SCK, and the second semiconductor apparatus120may receive the command address signal CA based on the system clock signal SCK. The first semiconductor apparatus110may transmit the command address signal CA in synchronization with the system clock signal SCK, and the second semiconductor apparatus120may synchronize the command address signal CA with the system clock signal SCK. The second semiconductor apparatus120may be coupled to the first semiconductor apparatus110through the data bus103, and may receive data DQ from the first semiconductor apparatus110through the data bus103or transmit the data DQ to the first semiconductor apparatus110through the data bus103. The first semiconductor apparatus110may transmit the data DQ to the second semiconductor apparatus120or receive the data DQ transmitted from the second semiconductor apparatus120, in synchronization with the system clock signal SCK. The second semiconductor apparatus120may transmit the data DQ to the first semiconductor apparatus110or receive the data DQ transmitted from the first semiconductor apparatus110, in synchronization with the system clock signal SCK.

The first semiconductor apparatus110may include a system clock generation circuit111, a command address generation circuit112, and a data input/output circuit113. The system clock generation circuit111may generate the system clock signal SCK and the system clock bar signal SCKB. The system clock generation circuit111may include any clock generator for generating the system clock signal SCK. For example, the system clock generation circuit111may include an oscillator, a phase locked loop circuit, a delay locked loop circuit, and the like. The system clock generation circuit111may generate the system clock signal SCK having a frequency suitable for communication between the first and second semiconductor apparatuses110and120. The system clock generation circuit111may transmit the system clock signal SCK to the second semiconductor apparatus120through the clock bus101. The system clock generation circuit111may provide the system clock signal SCK to the command address generation circuit112and the data input/output circuit113.

The command address generation circuit112may generate the command address signal CA based on a user's request REQ. The command address generation circuit112may generate the command address signal CA that instructs the second semiconductor apparatus120to perform various operations according to the request REQ. The command address generation circuit112may transmit the command address signal CA to the second semiconductor apparatus120through the command address bus102. The command address generation circuit112may receive the system clock signal SCK, and transmit the command address signal CA to the command address bus102in synchronization with the system clock signal SCK. The first semiconductor apparatus110may provide information related to the frequency of the system clock signal SCK to the second semiconductor apparatus120as the command address signal CA. The command address generation circuit112may generate the command address signal CA having information related to the frequency of the system clock signal SCK. The information related to the frequency of the system clock signal SCK may be related to whether the frequency of the system clock signal SCK is high or low. For example, when the frequency of the system clock signal SCK changes in first to eighth frequency ranges, the command address generation circuit112may generate the command address signal CA having information on any one of the first to eighth frequency ranges to which the frequency of the system clock signal SCK belongs.

The data input/output circuit113may be coupled to the second semiconductor apparatus120through the data bus103, and may transmit the data DQ to the second semiconductor apparatus120through the data bus103or receive the data DQ transmitted from the second semiconductor apparatus120through the data bus103. The data input/output circuit113may generate the data DQ based on internal data DATA1of the first semiconductor apparatus110, and transmit the data DQ to the second semiconductor apparatus120through the data bus103. The data input/output circuit113may receive the data DQ transmitted from the second semiconductor apparatus120through the data bus103, and generate the internal data DATA1based on the data DQ. The data input/output circuit113may receive the system clock signal SCK, and perform a data input/output operation based on the system clock signal SCK. The data input/output circuit113may transmit the internal data DATA1of the first semiconductor apparatus110as the data DQ in synchronization with the system clock signal SCK, and generate the internal data DATA1from the data DQ in synchronization with the system clock signal SCK.

The second semiconductor apparatus120may include a clock receiver121, a clock path circuit122, an internal clock generation circuit123, a command address control circuit124, and a data input/output circuit125. The clock receiver121may be coupled to the clock bus101, and may generate a received clock signal CKR by receiving the system clock signal SCK transmitted through the clock bus101. When the system clock signal SCK is transmitted together with the system clock bar signal SCKB, the clock receiver121may generate the received clock signal CKR by differentially amplifying the system clock signal SCK and the system clock bar signal SCKB. When the system clock signal SCK is transmitted as a single-ended signal, the clock receiver121may generate the received clock signal CKR by differentially amplifying the system clock signal SCK and a reference voltage. The reference voltage may have a voltage level corresponding to the middle of a range in which the system clock signal SCK swings.

The clock path circuit122may receive the received clock signal CKR to generate a reference clock signal RCK. The clock path circuit122may generate the reference clock signal RCK by buffering the received clock signal CKR. The clock path circuit122may include a plurality of clock paths. The clock path circuit122may include at least a first clock path122-1and a second clock path122-2. The first and second clock paths122-1and122-2may have different characteristics. For example, the first clock path122-1may allow a clock signal with a high frequency to propagate without loss and have relatively high power consumption. The second clock path122-2may allow a clock signal with a low frequency to propagate and have relatively low power consumption. The first clock path122-1may be a current mode logic (CML) clock path, and the second clock path122-2may be a complementary metal-oxide-semiconductor (CMOS) clock path. The first clock path122-1may buffer the received clock signal CKR at a CML level, and the second clock path122-2may buffer the received clock signal CKR at a CMOS level. The CML level may be a voltage level range smaller than that of the CMOS level, and a swing range of a signal that swings at a CML level may be smaller than a swing range of a signal that swings at the CMOS level. The clock path circuit122may allow the received clock signal CKR to propagate through one of the first and second clock paths122-1and122-2according to the frequency of the system clock signal SCK. When the frequency of the system clock signal SCK is high, the clock path circuit122may allow the received clock signal CKR to propagate through the first clock path122-1, and when the frequency of the system clock signal SCK is low, the clock path circuit122may allow the received clock signal CKR to propagate through the second clock path122-2. When the frequency of the system clock signal SCK is high, the clock path circuit122may allow the received clock signal CKR with a high frequency to propagate without loss, and when the frequency of the system clock signal SCK is low, the clock path circuit122may allow the received clock signal CKR with a low frequency to propagate while reducing power consumption. The clock path circuit122may output one of the output signal of the first clock path122-1and the output signal of the second clock path122-2as the reference clock signal RCK.

The internal clock generation circuit123may receive the reference clock signal RCK, and generate a plurality of internal clock signals based on the reference clock signal RCK. The internal clock generation circuit123may divide the frequency of the reference clock signal RCK, and generate a plurality of internal clock signals from the divided clock signal. The plurality of internal clock signals may include a command clock signal CCK and a data clock signal DCK. The internal clock generation circuit123may provide the command clock signal CCK to the command address control circuit124, and provide the data clock signal DCK to the data input/output circuit125. In an embodiment, the command clock signal CCK may have a lower frequency than the data clock signal DCK. The internal clock generation circuit123may include at least one division circuit capable of dividing the frequency of the reference clock signal RCK. In an embodiment, the internal clock generation circuit123may include a delay-locked loop circuit and/or a phase-locked loop circuit capable of compensating for a time for which the system clock signal SCK is delayed by the internal circuits of the second semiconductor apparatus120. In an embodiment, the internal clock generation circuit123may include a command clock distribution network capable of distributing the command clock signal CCK to the command address control circuit124. The internal clock generation circuit123may include a data clock distribution network capable of distributing the data clock signal DCK to the data input/output circuit125.

The command address control circuit124may be coupled to the command address bus102, and may receive the command address signal CA transmitted from the first semiconductor apparatus110. The command address control circuit124may receive the command clock signal CCK from the internal clock generation circuit123, and synchronize the command address signal CA with the command clock signal CCK. The command address control circuit124may decode the command address signal CA to generate an internal command signal and an internal address signal so that the second semiconductor apparatus120may perform various operations.

When the command address signal CA including the information related to the frequency of the system clock signal SCK is received from the first semiconductor apparatus110, the command address control circuit124may generate at least one frequency control signal based on the command address signal CA. For example, the command address control circuit124may generate a first frequency control signal FC1, a second frequency control signal FC2, a third frequency control signal FC3, and a fourth frequency control signal FC4based on the command address signal CA. The command address control circuit124may provide the first frequency control signal FC1to the clock receiver121. The clock receiver121may vary a gain of the clock receiver121based on the first frequency control signal FC1. For example, the clock receiver121may change the gain of the clock receiver121to a gain suitable for receiving the system clock signal SCK with a high frequency or a gain suitable for receiving the system clock signal SCK with a low frequency based on the first frequency control signal FC1. The command address control circuit124may provide the second frequency control signal FC2to the clock path circuit122. Based on the second frequency control signal FC2, the clock path circuit122may select a clock path through which the received clock CKR propagates. The clock path circuit122may select one of the first and second clock paths122-1and122-2based on the second frequency control signal FC2, and one of the first and second clock paths122-1and122-2may be activated based on the second frequency control signal FC2.

The command address control circuit124may provide the third frequency control signal FC3to the internal clock generation circuit123. The internal clock generation circuit123may adjust a setup and/or hold margin for generating the data clock signal DCK from the reference clock signal RCK based on the third frequency control signal FC3. The command address control circuit124may provide the fourth frequency control signal FC4to at least one CML buffer included in the second semiconductor apparatus120. For example, the clock receiver121may be a CML buffer and may further receive the fourth frequency control signal FC4. The fourth frequency control signal FC4may also be provided to a CML buffer other than the clock receiver121. The clock receiver121may change the current driving ability of the clock receiver121based on the fourth frequency control signal FC4. The clock receiver121may increase or decrease the current driving ability of generating the received clock signal CKR based on the fourth frequency control signal FC4.

The data input/output circuit125may be coupled to the first semiconductor apparatus110through the data bus103, and may transmit the data DQ to the first semiconductor apparatus110through the data bus103or receive the data DQ transmitted from the first semiconductor apparatus110through the data bus103. The data input/output circuit125may generate the data DQ based on internal data DATA2of the second semiconductor apparatus120, and transmit the data DQ to the first semiconductor apparatus110through the data bus103. The data input/output circuit125may receive the data DQ transmitted from the first semiconductor apparatus110through the data bus103, and generate the internal data DATA2based on the data DQ. The data input/output circuit125may receive the data clock signal DCK generated from the internal clock generation circuit123. The data input/output circuit125may perform an input/output operation of the data DQ based on the data clock signal DCK. The data input/output circuit125may transmit the data DQ to the first semiconductor apparatus110in synchronization with the data clock signal DCK, and receive the data DQ transmitted from the first semiconductor apparatus110in synchronization with the data clock signal DCK.

FIG.2is a block diagram illustrating the configuration of at least a part of a semiconductor apparatus200in accordance with an embodiment of the present disclosure. The semiconductor apparatus200may be applied as the second semiconductor apparatus120illustrated inFIG.1. Referring toFIG.2, the semiconductor apparatus200may include a frequency control circuit211, a clock receiver220, and a clock path circuit230. The frequency control circuit211may generate at least one frequency control signal based on the command address signal CA. The command address signal CA may include the information related to the frequency of the system clock signal SCK. The command address signal CA may be transmitted from the first semiconductor apparatus110illustrated inFIG.1. The semiconductor apparatus200may further include a command address receiver212that receives the command address signal CA. The command address receiver212and the frequency control circuit211may be included in the command address control circuit124illustrated inFIG.1.

The frequency control circuit211may generate a frequency information signal based on the command address signal CA. The frequency information signal may have a plurality of bits and may have different values according to the frequency of the system clock signal SCK. For example, the system clock signal SCK may belong to any one of first to eighth frequency ranges, and the frequency information signal may have different values according to a frequency range to which the frequency of the system clock signal SCK belongs. The first frequency range may be the lowest frequency range, and the eighth frequency range may be the highest frequency range. The first to eighth frequency ranges might not overlap one another. The frequency control circuit211may further receive at least a first frequency setting signal FEN1. The frequency control circuit211may generate a first frequency control signal FC1by comparing the frequency information signal with the first frequency setting signal FEN1. The first frequency setting signal FEN1may specify a target frequency range. The first frequency setting signal FEN1may include information corresponding to at least one of the first to eighth frequency ranges. The first frequency setting signal FEN1may be a signal stored in another circuit of the semiconductor apparatus200. For example, the first frequency setting signal FEN1may be stored in a mode register or a programmable memory cell included in the semiconductor apparatus200. When a frequency corresponding to the frequency information signal (that is, a frequency of the system clock signal SKC) is higher than a frequency corresponding to the first frequency setting signal FEN1, the frequency control circuit211may enable the first frequency control signal FC1. When the frequency corresponding to the frequency information signal is lower than the frequency corresponding to the first frequency setting signal FEN1, the frequency control circuit211may disable the first frequency control signal FC1. For example, the first frequency setting signal FEN1is assumed to specify the fourth frequency range. When the frequency corresponding to the frequency information signal belongs to the first to third frequency ranges, the frequency control circuit211may maintain the first frequency control signal FC1in a disabled state. When the frequency corresponding to the frequency information signal belongs to the fourth to eighth frequency ranges, the frequency control circuit211may enable the first frequency control signal FC1. The first frequency setting signal FEN1may include the same number of bits as the number of bits of the frequency information signal.

The semiconductor apparatus200may further store a second frequency setting signal FEN2, a third frequency setting signal FEN3, and a fourth frequency setting signal FEN4, and the frequency control circuit211may further receive the second frequency setting signal FEN2, the third frequency setting signal FEN3, and the fourth frequency setting signal FEN4. The frequency control circuit211may further generate a second frequency control signal FC2, a third frequency control signal FC3, and a fourth frequency control signal FC4based on the frequency information signal, the second frequency setting signal FEN2, the third frequency setting signal FEN3, and the fourth frequency setting signal FEN4. The frequency control circuit211may generate the second frequency control signal FC2by comparing the frequency information signal with the second frequency setting signal FEN2. The frequency control circuit211may generate the third frequency control signal FC3by comparing the frequency information signal with the third frequency setting signal FEN3. The frequency control circuit211may generate the fourth frequency control signal FC4by comparing the frequency information signal with the fourth frequency setting signal FEN4. The first to fourth frequency setting signals FEN1to FEN4may have different values, or some or all of them may have the same value. Accordingly, the frequency control circuit211may independently enable the first to fourth frequency control signals FC1to FC4according to values of the first to fourth frequency setting signals FEN1to FEN4. For example, when the second frequency setting signal FEN2may specify the third frequency range, the third frequency setting signal FEN3may specify the sixth frequency range, the fourth frequency setting signal FEN4may specify the seventh frequency range, and the frequency corresponding to the frequency information signal belongs to the fifth frequency range, the frequency control circuit211may enable the first and second frequency control signals FC1and FC2and disable the third and fourth frequency control signals FC3and FC4. In an embodiment, the first to fourth frequency setting signals FEN1to FEN4may specify the upper and lower limits of a target frequency range. For example, the fourth frequency setting signal FC4may specify the target frequency range from the third frequency range to the fifth frequency range. In such a case, when the frequency corresponding to the frequency information signal belongs to the third to fifth frequency ranges, the frequency control circuit211may enable the fourth frequency control signal FC4. When the frequency corresponding to the frequency information signal belongs to the first and second frequency ranges or the sixth to eighth frequency ranges, the frequency control circuit211may disable the fourth frequency control signal FC4.

The clock receiver220may receive a system clock signal pair SCK and SCKB to generate a received clock signal pair CKR and CKRB. The clock receiver220may be a component corresponding to the clock receiver121illustrated inFIG.1. The clock receiver220may generate the received clock signal CKR and the received clock bar signal CKRB by differentially amplifying the system clock signal SCK and the system clock bar signal SCKB. The clock receiver220may be a CML buffer. The clock receiver220may receive at least the first frequency control signal FC1. The clock receiver220may vary a gain of the clock receiver220based on the first frequency control signal FC1. When the first frequency control signal FC1is enabled, the clock receiver220may increase an alternating current (AC) gain of the clock receiver220. When the first frequency control signal FC1is disabled, the clock receiver220may increase a direct current (DC) gain of the clock receiver220. When the AC gain of the clock receiver220increases, the clock receiver220may be suitable for differentially amplifying the system clock signal pair SCK and SCKB having a relatively high frequency. When the DC gain of the clock receiver220increases, the clock receiver220may be suitable for differentially amplifying the system clock signal pair SCK and SCKB having a relatively low frequency. The clock receiver220may include various components for adjusting the gain of the clock receiver220, and the various components will be described below. The clock receiver220may further receive the fourth frequency control signal FC4. The clock receiver220may vary the current driving ability of the clock receiver220based on the fourth frequency control signal FC4. When the fourth frequency control signal FC4is enabled, the clock receiver220may increase the current driving ability of the clock receiver220. When the fourth frequency control signal FC4is disabled, the clock receiver220may decrease the current driving ability of the clock receiver220. The current driving ability may be a current driving ability for the clock receiver220to generate the received clock signal pair CKR and CKRB.

The clock path circuit230may receive the received clock signal pair CKR and CKRB from the clock receiver220, and generate a reference clock signal pair RCK and RCKB from the received clock signal pair CKR and CKRB. The clock path circuit230may be a component corresponding to the clock path circuit122illustrated inFIG.1. The clock path circuit230may include a first clock path231and a second clock path232. The first clock path231may be a CML clock path including a CML buffer, and the second clock path232may be a CMOS clock path including a CMOS buffer. The clock path circuit230may generate the reference clock signal pair RCK and RCKB by buffering the received clock signal pair CKR and CKRB through one of the first and second clock paths231and232. The clock path circuit230may receive the second frequency control signal FC2. Based on the second frequency control signal FC2, the clock path circuit230may select a clock path through which the received clock signal pair CKR and CKRB propagates. When the second frequency control signal FC2is enabled, the clock path circuit230may generate the reference clock signal pair RCK and RCKB by allowing the received clock signal pair CKR and CKRB to propagate through the first clock path231. When the second frequency control signal FC2is disabled, the clock path circuit230may generate the reference clock signal pair RCK and RCKB by allowing the received clock signal pair CKR and CKRB to propagate through the second clock path232.

The first clock path231may be activated based on the second frequency control signal FC2. The first clock path231may be activated when the second frequency control signal FC2is enabled and may be deactivated when the second frequency control signal FC2is disabled. The second clock path232may be activated based on the second frequency control signal FC2. The second clock path232may be deactivated when the second frequency control signal FC2is enabled and may be activated when the second frequency control signal FC2is disabled. The first clock path231may include a first buffer231-1and a first level converter231-2. The first buffer231-1may be a CML buffer. The first buffer231-1may receive the received clock signal pair CKR and CKRB, and buffer the received clock signal pair CKR and CKRB to generate an output signal that swings at a CML level. The first buffer231-1may receive the second frequency control signal FC2. The first buffer231-1may be activated when the second frequency control signal FC2is enabled, and may be deactivated when the second frequency control signal FC2is disabled. The first level converter231-1may receive the output signal of the first buffer231-1. The first level converter231-1may convert the output signal into a first differential clock signal pair CKD1and CKD1B that swings at a CMOS level. The first level converter231-2may be a CML to CMOS converter. In an embodiment, the first clock path231may further include one or more CML buffers coupled between the first buffer231-1and the first level converter231-2. In an embodiment, the first buffer231-1may further receive the fourth frequency control signal FC4, and may adjust the current driving ability of the first buffer231-1based on the fourth frequency control signal FC4.

The second clock path232may include a second level converter232-1and a second buffer232-2. The second level converter232-1may receive the received clock signal pair CKR and CKRB and convert the received clock signal pair CKR and CKRB into an output signal that swings at a CMOS level. The second level converter232-1may be a CML to CMOS converter. The second level converter232-1may receive the second frequency control signal FC2. The second level converter232-1may be deactivated when the second frequency control signal FC2is enabled, and may be activated when the second frequency control signal FC2is disabled. The second buffer232-2may be a CMOS buffer. The second buffer232-2may receive the output signal of the second level converter232-1, and buffer the output signal to generate a second differential clock signal pair CKD2and CKD2B. In an embodiment, the second clock path232may further include one or more CMSO buffers coupled between the second level converter232-1and the second buffer232-2.

The clock path circuit230may further include a selection circuit233. The selection circuit233may receive the first differential clock signal pair CKD1and CKD1B and the second differential clock signal pair CKD2and CKD2B from the first and second clock paths231and232, respectively. The selection circuit233may receive the second frequency selection signal FC2. Based on the second frequency selection signal FC2, the selection circuit233may output one of the first differential clock signal pair CKD1and CKD1B and the second differential clock signal pair CKD2and CKD2B as the reference clock signal pair RCK and RCKB. When the second frequency selection signal FC2is enabled, the selection circuit233may output the first differential clock signal pair CKD1and CKD1B as the reference clock signal pair RCK and RCKB. When the second frequency selection signal FC2is disabled, the selection circuit233may output the second differential clock signal pair CKD2and CKD2B as the reference clock signal pair RCK and RCKB. The selection circuit233may include a first input terminal for receiving the first differential clock signal pair CKD1and CKD1B, a second input terminal for receiving the second differential clock signal pair CKD2and CKD2B, and an output terminal for outputting the reference clock signal pair RCK and RCKB, and may include a multiplexer that receives the second frequency control signal FC2as a control signal.

The semiconductor apparatus200may further include an internal clock generation circuit240. The internal clock generation circuit240may be a component corresponding to the internal clock generation circuit123illustrated inFIG.1. The internal clock generation circuit240may receive the received clock signal pair CKR and CKRB and the reference clock signal pair RCK and RCKB, and generate a data clock signal DCK and a command clock signal CCK based on the received clock signal pair CKR and CKRB and the reference clock signal pair RCK and RCKB. The internal clock generation circuit240may include a third level converter241, a first clock divider242, a phase controller243, a data clock generator244, and a command clock generator245. The third level converter241may receive the received clock signal pair CKR and CKRB, and convert the received clock signal pair CKR and CKRB into an output signal that swings at a CMOS level. The third level converter241may be a CML to CMOS converter. The first clock divider242may receive the output signal of the third level converter241. The first clock divider242may generate a plurality of phase clock signals DVCK1by dividing a frequency of the output signal. For example, the plurality of phase clock signals DVCK1may include four phase clock signals sequentially having a phase difference of 90° among them. The plurality of phase clock signals DVCK1may include a first phase clock signal generated from a rising edge of the received clock signal CKR, a second phase clock signal generated from a rising edge of the received clock bar signal CKRB, a third phase clock signal generated from a falling edge of the received clock signal CKR, and a fourth phase clock signal generated from a falling edge of the received clock bar signal CKRB.

The phase controller243may receive the plurality of phase clock signals DVCK1from the first clock divider232and output one of the plurality of phase clock signals DVCK1. The phase controller243may receive the third frequency control signal FC3. The phase controller243may selectively output one of the plurality of phase clock signals DVCK1based on the third frequency control signal FC3. For example, when the third frequency control signal FC3is disabled, the phase controller243may output the first phase clock signal among the plurality of phase clock signals DVCK1. When the third frequency control signal FC3is enabled, the phase controller243may output the fourth phase clock signal among the plurality of phase clock signals DVCK1. The fourth phase clock signal may have a phase ahead of the first phase clock signal. When the third frequency control signal FC3is enabled, the phase controller243may provide the fourth phase clock signal with an earlier phase to the data clock generator244, so that the data clock generator244may increase a setup and/or hold margin for generating the data clock signal DCK.

The data clock generator244may receive the reference clock signal pair RCK and RCKB from the clock path circuit230, and receive the output signal of the phase controller243. The data clock generator244may generate the data clock signal DCK based on the reference clock signal pair RCK and RCKB and the output signal of the phase controller243. The data clock generator244may generate the data clock signal DCK by sampling the output signal of the phase controller243by using the reference clock signal RCK and the reference clock bar signal RCKB. The data clock signal DCK may have a lower frequency than the reference clock signal pair RCK and RCKB, and have the same frequency as the output signal of the phase controller243. The data clock signal DCK may include a plurality of data clock signals sequentially having a phase difference of 90° among them. The data clock signal DCK may include a clock signal generated by sampling the output signal of the phase controller243at the rising edge of the reference clock signal RCK, a clock signal generated by sampling the output signal of the phase controller243at the rising edge of the reference clock bar signal RCKB, a clock signal generated by sampling the output signal of the phase controller243at the falling edge of the reference clock signal RCK, and a clock signal generated by sampling the output signal of the phase controller243at the falling edge of the reference clock bar signal RCKB. The data clock generator244may provide the data clock signal DCK to the data input/output circuit125illustrated inFIG.1.

The command clock generator245may receive the plurality of phase clock signals DVCK1, and divide the frequencies of the plurality of phase clock signals DVCK1to generate a divided clock signal DVCK2. The divided clock signal DVCK2may have a lower frequency than the plurality of phase clock signals DVCK1. The command clock generator245may buffer the divided clock signal DVCK2to generate the command clock signal CCK, and provide the command clock signal CCK to the command address receiver212. The command address receiver212may receive the command address signal CA based on the command clock signal CCK. The command clock generator245may include a second clock divider245-1and a clock distribution circuit245-2. The second clock divider245-1may generate the divided clock signal DVCK2by dividing the frequencies of at least some of the plurality of phase clock signals DVCK1. For example, the second clock divider254-1may generate the divided clock signal by dividing the frequencies of the first and third phase clock signals. The clock distribution circuit245-2may buffer the divided clock signal DVCK2and output the command clock signal CCK.

FIG.3is a diagram illustrating the configuration of a frequency control circuit300in accordance with an embodiment of the present disclosure. The frequency control circuit300may be applied as the frequency control circuit211illustrated inFIG.2. Referring toFIG.3, the frequency control circuit300may include a frequency detector310and a first frequency control signal generator320. The frequency detector310may receive the command address signal CA, and generate a frequency information signal FI<1:n> based on the command address signal CA. The frequency detector310may generate the frequency information signal FI<1:n> by decoding the command address signal CA. Here, n may be an integer of 2 or more. When the frequency information signal FI<1:n> includes 8 bits, the frequency detector310may generate the frequency information signal FI<1:n> by decoding the command address signal CA having 3 bits or more. Hereinafter, a case in which the frequency information signal FI<1:n> includes 8 bits will be described as an example.

The first frequency control signal generator320may receive the frequency information signal FI<1:n> from the frequency detector310, and receive a first frequency setting signal FEN1<1:n>. The first frequency setting signal FEN1<1:n> may include the same number of bits as the number of bits of the frequency information signal FI<1:n>, and the first frequency setting signal FEN1<1:n> may also include 8 bits. The first frequency control signal generator320may compare the frequency information signal FI<1:n> with the first frequency setting signal FEN1<1:n> to generate the first frequency control signal FC1. When a frequency corresponding to the frequency information signal FI<1:n> is higher than a frequency corresponding to the first frequency setting signal FEN1<1:n>, the first frequency control signal generator320may enable the first frequency control signal FC1. When the frequency corresponding to the frequency information signal FI<1:n> is lower than the frequency corresponding to the first frequency setting signal FEN1<1:n>, the first frequency control signal generator320may disable the first frequency control signal FC1.

The frequency control circuit300may further include a second frequency control signal generator330, a third frequency control signal generator340, and a fourth frequency control signal generator350. The second frequency control signal generator330may receive the frequency information signal FI<1:n> from the frequency detector310, and receive a second frequency setting signal FEN2<1:n>. The second frequency setting signal FEN2<1:n> may include 8 bits like the first frequency setting signal FEN1<1:n>. The second frequency control signal generator330may compare the frequency information signal FI<1:n> with the second frequency setting signal FEN2<1:n> to generate the second frequency control signal FC2. When the frequency corresponding to the frequency information signal FI<1:n> is higher than a frequency corresponding to the second frequency setting signal FEN2<1:n>, the second frequency control signal generator330may enable the second frequency control signal FC2. When the frequency corresponding to the frequency information signal FI<1:n> is lower than the frequency corresponding to the second frequency setting signal FEN2<1:n>, the second frequency control signal generator330may disable the second frequency control signal FC2.

The third frequency control signal generator340may receive the frequency information signal FI<1:n> from the frequency detector310, and receive a third frequency setting signal FEN3<1:n>. The third frequency setting signal FEN3<1:n> may include 8 bits like the first frequency setting signal FEN1<1:n>. The third frequency control signal generator340may compare the frequency information signal FI<1:n> with the third frequency setting signal FEN3<1:n> to generate the third frequency control signal FC3. When the frequency corresponding to the frequency information signal FI<1:n> is higher than a frequency corresponding to the third frequency setting signal FEN3<1:n>, the third frequency control signal generator340may enable the third frequency control signal FC3. When the frequency corresponding to the frequency information signal FI<1:n> is lower than the frequency corresponding to the third frequency setting signal FEN3<1:n>, the third frequency control signal generator340may disable the third frequency control signal FC3.

The fourth frequency control signal generator350may receive the frequency information signal FI<1:n> from the frequency detector310, and receive a fourth frequency setting signal FEN4<1:n>. The fourth frequency setting signal FEN4<1:n> may include 8 bits like the first frequency setting signal FEN1<1:n>. The fourth frequency control signal generator350may compare the frequency information signal FI<1:n> with the fourth frequency setting signal FEN4<1:n> to generate the fourth frequency control signal FC4. When the frequency corresponding to the frequency information signal FI<1:n> is higher than a frequency corresponding to the fourth frequency setting signal FEN4<1:n>, the fourth frequency control signal generator350may enable the fourth frequency control signal FC4. When the frequency corresponding to the frequency information signal FI<1:n> is lower than the frequency corresponding to the fourth frequency setting signal FEN4<1:n>, the fourth frequency control signal generator350may disable the fourth frequency control signal FC4.

FIG.4is a diagram illustrating the configuration of the first frequency control signal generator320illustrated inFIG.3.FIG.4may illustrate the configuration of the first frequency control signal generator320for generating the first frequency control signal FC1from the frequency information signal FI<1:8> and the first frequency setting signal FEN1<1:8> each including 8 bits. The configuration of the first frequency control signal generator320may variously vary according to the number of bits included in the frequency information signal FI<1:n> and the first frequency setting signal FEN1<1:n> without departing from the operation principle of the first frequency control signal generator320illustrated inFIG.4. The first frequency control signal generator320may include a first NAND gate411, a second NAND gate412, a third NAND gate413, a fourth NAND gate414, a fifth NAND gate415, a sixth NAND gate416, a seventh NAND gate417, an eighth NAND gate418, a ninth NAND gate421, a tenth NAND gate422, an eleventh NAND gate423, a twelfth NAND gate424, a first NOR gate431, a second NOR gate432, a thirteenth NAND gate440, a third NOR gate450, and an inverter460. The first NAND gate411may receive a first bit FI<1> of the frequency information signal and a first bit FEN1<1> of the first frequency setting signal. The second NAND gate412may receive a second bit FI<2> of the frequency information signal and a second bit FEN1<2> of the first frequency setting signal. The third NAND gate413may receive a third bit FI<3> of the frequency information signal and a third bit FEN1<3> of the first frequency setting signal. The fourth NAND gate414may receive a fourth bit FI<4> of the frequency information signal and a fourth bit FEN1<4> of the first frequency setting signal. The fifth NAND gate415may receive a fifth bit FI<5> of the frequency information signal and a fifth bit FEN1<5> of the first frequency setting signal. The sixth NAND gate416may receive a sixth bit FI<6> of the frequency information signal and a sixth bit FEN1<6> of the first frequency setting signal. The seventh NAND gate417may receive a seventh bit FI<7> of the frequency information signal and a seventh bit FEN1<7> of the first frequency setting signal. The eighth NAND gate418may receive an eighth bit FI<8> of the frequency information signal and an eighth bit FEN1<8> of the first frequency setting signal.

The ninth NAND gate421may receive an output signal of the first NAND gate411and an output signal of the second NAND gate412. The tenth NAND gate422may receive an output signal of the third NAND gate413and an output signal of the fourth NAND gate414. The eleventh NAND gate423may receive an output signal of the fifth NAND gate415and an output signal of the sixth NAND gate416. The twelfth NAND gate424may receive an output signal of the seventh NAND gate417and an output signal of the eighth NAND gate418. The first NOR gate431may receive an output signal of the ninth NAND gate421and an output signal of the tenth NAND gate422. The second NOR gate432may receive output signals of the eleventh NAND gate423and the twelfth NAND gate424. The thirteenth NAND gate440may receive an output signal of the first NOR gate431and an output signal of the second NOR gate432. The third NOR gate450may receive an output signal of the thirteenth NAND gate440and a signal (‘0’, for example, ground voltage) corresponding to a low logic level. The inverter460may invert an output signal of the third NOR gate450and output the first frequency control signal FC1.

The frequency information signal FI<1:8> may specify the frequency range of the system clock signal SCK ofFIGS.1and2. Bits of the frequency information signal FI<1:8> corresponding to a frequency range to which the frequency of the system clock signal SCK belongs among the first to eighth frequency ranges may each have a high logic level. For example, when the frequency of the system clock signal SCK belongs to the fourth frequency range, the fourth bit FI<4> of the frequency information signal may have a high logic level, and the first to third bits FI<1:3> and the fifth to eighth bits FI<5:8> of the frequency information signal may each have a low logic level. The first frequency setting signal FEN1<1:8> may set a target frequency range, and bits of the first frequency setting signal FEN1<1:8> corresponding to a frequency range equal to or greater than the target frequency range may each have a high logic level. For example, when the target frequency range is the fifth to eighth frequency ranges, the fifth to eighth bits FEN1<5:8> of the first frequency setting signal may each have a high logic level and the first to fourth bits FEN1<1:4> of the first frequency setting signal may each have a low logic level.

When a frequency range specified by the first frequency setting signal FEN1<1:8> is the fifth frequency range (that is, the first frequency setting signal FEN1<1:8> has a value of ‘0, 0, 0, 0, 1, 1, 1, 1’) and the frequency corresponding to the frequency information signal FI<1:8> belongs to the fourth frequency range (that is, the frequency information signal FI<1:8> has a value of ‘0, 0, 0, 1, 0, 0, 0, 0’), the output signals of the first to eighth NAND gates411to418may all have a high logic level. The output signals of the ninth to twelfth NAND gates421to424may all have a low logic level, the output signals of the first and second NOR gates431and432may all have a high logic level, and the output signal of the thirteenth NAND gate440may have a low logic level. Accordingly, the first frequency control signal FC1disabled at a low logic level may be generated through the third NOR gate450and the inverter460. When the frequency corresponding to the frequency information signal FI<1:8> belongs to the sixth frequency range, the output signals of the first to fifth NAND gates411to415, the seventh NAND gate417, and the eighth NAND gate418may all have a high logic level, and the output signal of the sixth NAND gate416may have a low logic level. The output signals of the ninth NAND gate421, the tenth NAND gate422, and the twelfth NAND gate424may have a low logic level, but the output signal of the eleventh NAND gate423may have a high logic level. The output signal of the first NOR gate431may have a high logic level, the output signal of the second NOR gate432may have a low logic level, and the output signal of the thirteenth NAND gate440may have a high logic level. Accordingly, the first frequency control signal FC1enabled at a high logic level may be generated through the third NOR gate450and the inverter460. The second frequency control signal generator330, the third frequency control signal generator340, and the fourth frequency control signal generator350ofFIG.3may include substantially the same configuration as the first frequency control signal generator320illustrated inFIG.4, except for receiving the second frequency setting signal FEN1<1:n>, the third frequency setting signal FEN3<1:n>, and the fourth frequency setting signal FEN4<1:n> instead of the first frequency setting signal FEN1<1:n>.

FIG.5is a diagram illustrating changes in the state of the semiconductor apparatus200in accordance with an embodiment of the present disclosure. Referring toFIGS.2,3, and5, the semiconductor apparatus200may have a first state, a second state, a third state, and a fourth state. For example, the first state may be a state in which a first frequency corresponding to the frequency information signal FI<1:n> is lower than a frequency range corresponding to the first to third frequency setting signals FEN1<1:n>, FEN2<1:n>, and FEN3<1:n>, and the first to third frequency control signals FC1to FC3may be disabled at a low logic level. The second state may be a state in which a second frequency corresponding to the frequency information signal FI<1:n> is lower than a frequency range corresponding to the first and second frequency setting signals FEN1<1:n> and FEN2<1:n> and higher than a frequency range corresponding to the third frequency setting signal FEN3<1:n>, and the first and second frequency control signals FC1and FC2may be disabled at a low logic level and the third frequency control signal FC3may be enabled at a high logic level. The third state may be a state in which a third frequency corresponding to the frequency information signal FI<1:n> is higher than the frequency range corresponding to the first and second frequency setting signals FEN1<1:n> and FEN2<1:n> and lower than the frequency range corresponding to the third frequency setting signal FEN3<1:n>, and the first and second frequency control signals FC1and FC2may be enabled at a high logic level and the third frequency control signal FC3may be disabled at a low logic level. The fourth state may be a state in which a fourth frequency corresponding to the frequency information signal FI<1:n> is higher than the frequency range corresponding to the first to third frequency setting signals FEN1<1:n>, FEN2<1:n>, and FEN3<1:n>, and the first to third frequency control signals FC1to FC3may be enabled at a high logic level.

When the semiconductor apparatus200is booted up, the default value of the first frequency control signal FC1within the semiconductor apparatus200may have a low logic level, the default value of the second frequency control signal FC2may have a high logic level, and the default value of the third frequency control signal FC3may have a low logic level. When the boot-up of the semiconductor apparatus200is completed and the command address signal CA including information related to the frequency of the system clock signal SCK is received, the frequency control circuit300may change the state of the semiconductor apparatus200to one of the first to fourth states by changing whether the first to third frequency control signals FC1to FC3are enabled. The command address signal CA including the information related to the frequency of the system clock signal SCK may be provided again at an arbitrary time point until the semiconductor apparatus200is powered off. When the semiconductor apparatus200receives the command address signal CA including the information related to the frequency of the system clock signal SCK, the frequency control circuit300may dynamically change the state of the semiconductor apparatus200from one state to another state by changing whether the first to third frequency control signals FC1to FC3are enabled, based on the command address signal CA. In an embodiment, the state of the semiconductor apparatus200may be changed according to the frequency of the system clock signal SCK, so that power consumption, characteristics, and/or performance of the clock receiver220, the clock path circuit230, and the internal clock generation circuit240may be optimized.

FIG.6is a diagram illustrating the configuration of a buffer circuit600in accordance with an embodiment of the present disclosure. The buffer circuit600may be applied as the clock receiver220illustrated inFIG.2. Referring toFIG.6, the buffer circuit600may operate by receiving a first power supply voltage VH and a second power supply voltage VL, and receive an input signal IN and an input bar signal INB to generate an output signal OUT and an output bar signal OUTB. The first power supply voltage VH may have a higher voltage level than the second power supply voltage VL. When the buffer circuit600is applied as the clock receiver220, the input signal IN and the input bar signal INB may correspond to the system clock signal SCK and the system clock bar signal SCKB, respectively, and the output signal OUT and the output bar signal OUTB may correspond to the received clock signal CKR and the received clock bar signal CKRB, respectively. The buffer circuit600may adjust a gain of the buffer circuit600according to a frequency of the input signal IN. The buffer circuit600may receive a first frequency control signal FC11and a second frequency control signal FC12having enable state changes according to a frequency of the input signal IN. When the buffer circuit600is applied as the clock receiver220, the first and second frequency control signals FC11and FC12may correspond to the first and fourth frequency control signals FC1and FC4, respectively.

The buffer circuit600may include a load circuit610, a first input transistor621, a second input transistor622, a first equalization transistor631, a second equalization transistor632, a capacitor641, a switching transistor642, a first current source651, and a second current source652. The load circuit610may receive the first power supply voltage VH. The load circuit610may be coupled between a node, to which the first power supply voltage VH is supplied, and a first output node ON1and a second output node ON2. The first and second output nodes ON1, ON2may receive the first power supply voltage through the load circuit610. The output signal OUT may be output through the second output node ON2, and the output bar signal OUTB may be output through the first output node ON1. The first input transistor621may be connected between the first output node ON1and the node to which the second power supply voltage VL is supplied, and may receive the input signal IN. The first input transistor621may change a voltage level of the first output node ON1based on the input signal IN. The first input transistor621may be an N-channel MOS transistor. A gate of the first input transistor621may receive the input signal IN, a drain of the first input transistor621may be connected to the first output node ON1, and a source of the first input transistor621may be connected to the node to which the second power supply voltage VL is supplied. The second input transistor622may be connected between the second output node ON2and the node to which the second power supply voltage VL is supplied, and may receive the input bar signal INB. The second input transistor622may change a voltage level of the second output node ON2based on the input bar signal INB. The second input transistor622may be an N-channel MOS transistor. A gate of the second input transistor622may receive the input bar signal INB, a drain of the second input transistor622may be connected to the second output node ON2, and a source of the second input transistor622may be connected to the node to which the second power supply voltage VL is supplied.

The first equalization transistor631may connect the first output node ON1to a first node N1according to the voltage level of the second output node ON2. The first equalization transistor631may be an N-channel MOS transistor. A gate of the first equalization transistor631may be connected to the second output node ON2, a drain of the first equalization transistor631may be connected to the first output node ON1, and a source of the first equalization transistor631may be connected to the first node N1. The second equalization transistor632may connect the second output node ON2to a second node N2according to the voltage level of the first output node ON1. The second equalization transistor632may be an N-channel MOS transistor. A gate of the second equalization transistor632may be connected to the first output node ON1, a drain of the second equalization transistor632may be connected to the second output node ON2, and a source of the second equalization transistor632may be connected to the second node N2. The capacitor641may be connected between the first and second nodes N1and N2. The switching transistor642may selectively connect the first and second nodes N1and N2based on the first frequency control signal FC11. The switching transistor642may be connected between the first and second nodes N1and N2, and may receive a bar signal FC11B of the first frequency control signal. The switching transistor642may be connected in parallel with the capacitor641between the first and second nodes N1and N2. The switching transistor642may be an N-channel MOS transistor. A gate of the switching transistor642may receive the bar signal FC11B of the first frequency control signal, and one of a drain and a source of the switching transistor642may be connected to the first node N1, and the other one of the drain and the source of the switching transistor642may be connected to the second node N2. The first current source651may be connected between the first node N1and the node to which the second power supply voltage VL is supplied. The first current source651may cause current to flow from the first node N1to the node to which the second power supply voltage VL is supplied. The second current source652may be connected between the second node N2and the node to which the second power supply voltage VL is supplied. The second current source652may cause current to flow from the second node N2to the node to which the second power supply voltage VL is supplied.

The switching transistor642may change the characteristics of the buffer circuit600based on the first frequency control signal FC11. The switching transistor642may electrically isolate the first and second nodes N1and N2from each other when the first frequency control signal FC11is enabled, and may connect the first and second nodes N1and N2to each other when the first frequency control signal FC11is disabled. When the switching transistor642is turned off and the first and second nodes N1and N2are not connected to each other, the first and second nodes N1and N2may be connected to each other through the capacitor641. When the first and second nodes N1and N2are connected through the capacitor641, because an equalization operation is performed on the first and second nodes N1and N2through the first and second equalizing transistors631and632and the capacitor641, an AC gain of the buffer circuit600may increase and the buffer circuit600may have characteristics of a band-pass filter and/or a high-pass filter. When the switching transistor642is turned on and the first and second nodes N1and N2are connected to each other, the capacitor641might not affect changes in the voltage levels of the first and second nodes N1and N2. Accordingly, the equalization operation might not be performed, a DC gain of the buffer circuit600may increase, and the buffer circuit600may have characteristics of a low-pass filter. When the frequency of the input signal IN is relatively high, the first frequency control signal FC11may be enabled and the switching transistor642may increase the AC gain of the buffer circuit600, so that the buffer circuit600may have characteristics suitable for amplifying the input signal IN having a high frequency. When the frequency of the input signal IN is relatively low, the first frequency control signal FC11may be disabled and the switching transistor642may increase the DC gain of the buffer circuit600, so that the buffer circuit600may have characteristics suitable for amplifying the input signal IN having a low frequency.

The load circuit610may receive the first frequency control signal FC11. The load circuit610may change a resistance value of the load circuit610based on the first frequency control signal FC11. The load circuit610may decrease the resistance value of the load circuit610when the first frequency control signal FC11is enabled and increase the resistance value of the load circuit610when the first frequency control signal FC11is disabled. When the resistance value of the load circuit610is decreased, the AC gain of the buffer circuit600may increase, and when the resistance value of the load circuit610is increased, the DC gain of the buffer circuit600may increase. The load circuit610may include a first resistor611, a second resistor612, a first load transistor613, a second load transistor614, and a third load transistor615. The first resistor611may be connected between the node to which the first power supply voltage VH is supplied and the first output node ON1. The second resistor612may be connected between the node to which the first power supply voltage VH is supplied and the second output node ON2. The first resistor611may have substantially the same resistance value as the resistance value of the second resistor612. The first load transistor613may connect the node to which the first power supply voltage VH is supplied to the first output node ON1based on the first frequency control signal FC11. The first load transistor613may be a P-channel MOS transistor. A gate of the first load transistor613may receive the bar signal FC11B of the first frequency control signal, and a source of the first load transistor613may be connected to the node to which the first power supply voltage VH is supplied, and a drain of the first load transistor613may be connected to the first output node ON1. The second load transistor614may connect the node to which the first power supply voltage VH is supplied to the second output node ON2based on the first frequency control signal FC11. The second load transistor614may be a P-channel MOS transistor. A gate of the second load transistor614may receive the bar signal FC11B of the first frequency control signal, and a source of the second load transistor614may be connected to the node to which the first power supply voltage VH is supplied, and a drain of the second load transistor614may be connected to the second output node ON2. The third load transistor615may connect the first and second output nodes ON1and ON2to each other based on the first frequency control signal FC11. The third load transistor615may be a P-channel MOS transistor. A gate of the third load transistor615may receive the bar signal FC11B of the first frequency control signal, and one of a source and a drain of the third load transistor615may be connected to the first output node ON1, and the other of the source and the drain of the third load transistor615may be connected to the second output node ON2.

When the first frequency control signal FC11is disabled, the first to third load transistors613to615may all be turned off. When the first to third load transistors613to615are all turned off, the resistance value between the node to which the first power supply voltage VH is supplied and the first output node ON1may be substantially the same as the resistance value of the resistor611, and the resistance value between the node to which the first power supply voltage VH is supplied and the second output node ON2may be substantially the same as the resistance value of the second resistor612. When the first frequency control signal FC11is enabled, the first to third load transistors613to615may all be turned on. When the first to third load transistors613to615are all turned on, the current path from the node to which the first power supply voltage VH is supplied to the first output node ON1may be bypassed to the turned load transistor613, and the current path from the node to which the first power supply voltage VH is supplied to the second output node ON2may be bypassed to the turned-on second load transistor614. The third load transistor615may connect the first and second output nodes ON1and ON2to each other. Accordingly, the first load transistor613and the second load transistor614may be connected in parallel. The resistance value between the node to which the first power supply voltage VH is supplied and the second output node ON2may be a parallel resistance value of a turn-on resistance value of the first and second load transistors613and614. When the first frequency control signal FC11is enabled, the first to third load transistors613to615may decrease the resistance value of the load circuit610and increase the amount of current supplied from the node to which the first power supply voltage VH is supplied to the first and second output nodes ON1and ON2. When the first frequency control signal FC11is disabled, the first to third load transistors613to615may increase the resistance value of the load circuit610and increase the amount of current supplied from the node to which the first power supply voltage VH is supplied to the first and second output nodes ON1and ON2.

The buffer circuit600may further include a third current source653and a fourth current source654. The third current source653may be connected between the first input transistor621and the node to which the second power supply voltage VL is supplied. The third current source653may cause current to flow from the source of the first input transistor621to the node to which the second power supply voltage VL is supplied. The fourth current source654may be connected between the second input transistor622and the node to which the second power supply voltage VL is supplied. The fourth current source654may cause current to flow from the source of the second input transistor622to the node to which the second power supply voltage VL is supplied. The amount of current of the third current source653may be substantially the same as the amount of current of the fourth current source654. The third and fourth current sources653and654may receive the second frequency control signal FC12, and the amount of current of the third current source653and the amount of current of the fourth current source654may be varied based on the second frequency control signal FC12. For example, when the second frequency control signal FC12is enabled, the third and fourth current sources653and654may increase the amount of current of the third current source653and the amount of current of the fourth current source654, respectively. When the second frequency control signal FC12is disabled, the third and fourth current sources653and654may decrease the amount of current of the third current source653and the amount of current of the fourth current source654, respectively. When the amount of current of the third current source653and the amount of current of the fourth current source654are increased, the current driving ability of the buffer circuit600may be increased, thereby increasing the rate of voltage change of the first and second output nodes ON1and ON2and/or the transition slopes of the first and second output nodes ON1and ON2. When the amount of current of the third current source653and the amount of current of the fourth current source654are decreased, the current driving ability of the buffer circuit600may be decreased, thereby decreasing the rate of voltage change of the first and second output nodes ON1and ON2and/or the transition slopes of the first and second output nodes ON1and ON2.

In an embodiment, the first and second current sources651and652may receive the second frequency control signal FC12, and the amount of current of the first current source651and the amount of current of the second current source652may be varied based on the second frequency control signal FC12. For example, when the second frequency control signal FC12is enabled, the first and second current sources651and652may increase the amount of current of the first current source651and the amount of current of the second current source652, respectively. When the second frequency control signal FC12is disabled, the first and second current sources651and652may decrease the amount of current of the first current source651and the amount of current of the second current source652, respectively. When the amount of current of the first current source651and the amount of current of the second current source652are increased, the rate of changes in the voltage levels of the first and second nodes N1and N2may be increased, and the current driving ability of equalizing the first and second output nodes ON1and ON2by the first and second equalizing transistors631and632and the capacitor641may be increased. Accordingly, when the amount of current of the first current source651and the amount of current of the second current source652are increased, the AC gain of the buffer circuit600may be additionally increased.

The buffer circuit600may further include a feedback circuit661, a third input transistor662, and a fourth input transistor663. The feedback circuit661may receive the output signal OUT and the output bar signal OUTB to generate a first feedback signal FP and a second feedback signal FN. The feedback circuit661may generate the first and second feedback signals FP and FN by differentially amplifying the output signal OUT and the output bar signal OUTB. The first feedback signal FP may be changed to the same logic level as the logic level of the output signal OUT, and the second feedback signal FN may be changed to the same logic level as the logic level of the output bar signal. The feedback circuit661may receive the first frequency control signal FC11and be selectively activated based on the first frequency control signal FC11. When the first frequency control signal FC11is enabled, the feedback circuit661may be activated and may generate the first and second feedback signals FP and FN from the output signal OUT and the output bar signal OUTB. When the first frequency control signal FC11is disabled, the feedback circuit661may be deactivated and might not generate the first and second feedback signals FP and FN.

The third input transistor662may receive the second feedback signal FN, and be connected between the first output node ON1and the node to which the second power supply voltage VL is supplied. The third input transistor662may change the voltage level of the first output node ON1based on the second feedback signal FN. The third input transistor662may be an N-channel MOS transistor. A gate of the third input transistor662may receive the second feedback signal FN, a drain of the third input transistor662may be connected to the first output node ON1, and a source of the third input transistor662may be connected to the node to which the second power supply voltage VL is supplied. The fourth input transistor663may receive the first feedback signal FP and be connected between the second output node ON2and the node to which the second power supply voltage VL is supplied. The fourth input transistor663may change the voltage level of the second output node ON2based on the first feedback signal FP. The fourth input transistor663may be an N-channel MOS transistor. A gate of the fourth input transistor663may receive the first feedback signal FP, a drain of the fourth input transistor663may be connected to the second output node ON2, and a source of the fourth input transistor663may be connected to the node to which the second power supply voltage VL is supplied. The third input transistor662may accelerate changes in the voltage level of the first output node ON1based on the second feedback signal FN, and the fourth input transistor663may accelerate changes in the voltage level of the second output node ON2based on the first feedback signal FP. Accordingly, when the first frequency control signal FC11is enabled, the feedback circuit661, the third input transistor662, and the fourth input transistor663may additionally increase the AC gain of the buffer circuit600.

The buffer circuit600may further include a fifth current source655and a sixth current source656. The fifth current source655may be connected between the third input transistor662and the node to which the second power supply voltage VL is supplied. The fifth current source655may cause current to flow from the source of the third input transistor662to the node to which the second power supply voltage VL is supplied. The sixth current source656may be connected between the fourth input transistor663and the node to which the second power supply voltage VL is supplied. The sixth current source656may cause current to flow from the source of the fourth input transistor663to the node to which the second power supply voltage VL is supplied. The amount of current of the fifth current source655may be substantially the same as the amount of current of the sixth current source656. The fifth and sixth current sources655and656may receive the second frequency control signal FC12and the amount of current of the fifth current source655and the amount of current of the sixth current source656may be varied based on the second frequency control signal FC12. For example, when the second frequency control signal FC12is enabled, the fifth and sixth current sources655and656may increase the amount of current of the fifth current source655and the amount of current of the sixth current source656, respectively. When the second frequency control signal FC12is disabled, the fifth and sixth current sources655and656may decrease the amount of current of the fifth current source655and the amount of current of the sixth current source656, respectively. When the amount of current of the fifth current source655and the amount of current of the sixth current source656are increased, the current driving ability of the buffer circuit600may be increased, thereby increasing the rate of voltage change of the first and second output nodes ON1and ON2and/or the transition slopes of the first and second output nodes ON1and ON2. When the amount of current of the fifth current source655and the amount of current of the sixth current source656are decreased, the current driving ability of the buffer circuit600may be decreased, thereby decreasing the rate of voltage change of the first and second output nodes ON1and ON2and/or the transition slopes of the first and second output nodes ON1and ON2.

The buffer circuit600may further include a first transistor671and a second transistor672. The first transistor671may be connected between the fifth current source655and the node to which the second power supply voltage VL is supplied, and may receive the first frequency control signal FC11. The first transistor671may selectively connect the fifth current source655to a node, to which the second power supply voltage VL is supplied, based on the first frequency control signal FC11, thereby selectively activating the current path formed from the first output node ON1to the node to which the second power supply voltage VL is supplied, through the third input transistor662and the fifth current source655. The first transistor671may be an N-channel MOS transistor. A gate of the first transistor671may receive the first frequency control signal FC11, a drain of the first transistor671may be connected to the fifth current source655, and a source of the first transistor671may be connected to the node to which the second power supply voltage VL is supplied. The second transistor672may be connected between the sixth current source656and the node to which the second power supply voltage VL is supplied, and may receive the first frequency control signal FC11. The second transistor672may selectively connect the sixth current source656to a node, to which the second power supply voltage VL is supplied, based on the first frequency control signal FC11, thereby selectively activating the current path formed from the second output node ON2to the node to which the second power supply voltage VL is supplied, through the fourth input transistor663and the sixth current source656. The second transistor672may be an N-channel MOS transistor. A gate of the second transistor672may receive the first frequency control signal FC11, a drain of the second transistor672may be connected to the sixth current source656, and a source of the second transistor672may be connected to the node to which the second power supply voltage VL is supplied.

The buffer circuit600may further include a third transistor673, a fourth transistor674, a fifth transistor675, and a sixth transistor676. The third transistor673may be connected between the third current source653and the node to which the second power supply voltage VL is supplied, and may receive an enable signal EN. The enable signal EN may be a signal that activates the buffer circuit600, and may be a signal that is enabled during a period in which the buffer circuit600operates. When the enable signal EN is enabled, the third transistor673may activate the current path formed from the first output node ON1to the node where the second power supply voltage VL is supplied, through the first input transistor621and the third current source653. The third transistor673may be an N-channel MOS transistor. A gate of the third transistor673may receive the enable signal EN, a drain of the third transistor673may be connected to the third current source653, and a source of the third transistor673may be connected to the node to which the second power supply voltage VL is supplied. The fourth transistor674may be connected between the fourth current source654and the node to which the second power supply voltage VL is supplied, and may receive the enable signal EN. When the enable signal EN is enabled, the fourth transistor674may activate the current path from the second output node ON2to the node to which the second power supply voltage VL is supplied, through the second input transistor622and the fourth current source654. The fourth transistor674may be an N-channel MOS transistor. A gate of the fourth transistor674may receive the enable signal EN, a drain of the fourth transistor674may be connected to the fourth current source654, and a source of the fourth transistor674may be connected to the node to which the second power supply voltage VL is supplied.

The fifth transistor675may be connected between the first current source651and the node to which the second power supply voltage VL is supplied, and may receive the enable signal EN. When the enable signal EN is enabled, the fifth transistor675may activate the current path formed from the first node N1to the node to which the second power supply voltage VL is supplied, through the first current source651. The fifth transistor675may be an N-channel MOS transistor. A gate of the fifth transistor675may receive the enable signal EN, a drain of the fifth transistor675may be connected to the first current source651, and a source of the fifth transistor675may be connected to the node to which the second power supply voltage VL is supplied. The sixth transistor676may be connected between the second current source652and the node to which the second power supply voltage VL is supplied, and may receive the enable signal EN. When the enable signal EN is enabled, the sixth transistor676may activate the current path from the second node N2to the node to which the second power supply voltage VL is supplied, through the second current source652. The sixth transistor676may be an N-channel MOS transistor. A gate of the sixth transistor676may receive the enable signal EN, a drain of the sixth transistor676may be connected to the second current source652, and a source of the sixth transistor676may be connected to the node to which the second power supply voltage VL is supplied.

The buffer circuit600may further include a first inductor681and a second inductor682. The first inductor681may be connected between the load circuit610and the first output node ON1. The first inductor681may be connected between the drain of the first load transistor613and the first output node ON1. The second inductor682may be connected between the load circuit610and the second output node ON2. The second inductor682may be connected between the drain of the second load transistor614and the second output node ON2. When the first and second inductors681and682are provided, the third load transistor615may be connected between the drains of the first and second load transistors613and614. The first inductor681may have substantially the same inductance as the inductance of the second inductor682. In an embodiment, because the first and second inductors681and682may delay times for which current supplied through the load circuit610from the node, to which the first power supply voltage VH is supplied, is supplied to the first and second output nodes ON1and ON2, respectively, when the voltage levels of the first and second output nodes ON1and ON2are transitioned, shunt peaking or inductive peaking may be formed and the AC gain of the buffer circuit600may be increased.

FIG.7is a diagram illustrating the configuration of the feedback circuit661illustrated inFIG.6. Referring toFIG.7, the feedback circuit661may include a first transistor710, a second transistor720, a first amplifier730, and a second amplifier740. The first transistor710may selectively activate the first amplifier730based on the first frequency control signal FC11. The first transistor710may receive the first frequency control signal FC11, and provide the second power supply voltage VL to the first amplifier730based on the first frequency control signal FC11. The first transistor710may be an N-channel MOS transistor, and a gate of the first transistor710may receive the first frequency control signal FC11. When the first frequency control signal FC11is enabled, the first transistor710may activate the first amplifier730by providing the second power supply voltage VL to the first amplifier730. When the first frequency control signal FC11is disabled, the first transistor710may deactivate the first amplifier730without providing the second power supply voltage VL to the first amplifier730. The second transistor720may selectively activate the second amplifier740based on the first frequency control signal FC11. The second transistor720may receive the first frequency control signal FC11, and provide the second power supply voltage VL to the second amplifier740based on the first frequency control signal FC11. The second transistor720may be an N-channel MOS transistor, and a gate of the second transistor720may receive the first frequency control signal FC11. When the first frequency control signal FC11is enabled, the second transistor720may activate the second amplifier740by providing the second power supply voltage VL to the second amplifier740. When the first frequency control signal FC11is disabled, the second transistor720may deactivate the second amplifier740without providing the second power supply voltage VL to the second amplifier740.

The first amplifier730may receive the first power supply voltage VH, and receive the second power supply voltage VL through the first transistor710. The first amplifier730may be activated when the second power supply voltage VL is received through the first transistor710. The first amplifier730may receive the output signal OUT and the output bar signal OUTB. The first amplifier730may output an amplified signal pair by differentially amplifying the output signal OUT and the output bar signal OUTB. The second amplifier740may receive the first power supply voltage VH, and receive the second power supply voltage VL through the second transistor720. The second amplifier740may be activated when the second power supply voltage VL is received through the second transistor720. The second amplifier740may receive the amplified signal pair output from the first amplifier730. The second amplifier740may output the first feedback signal FP and the second feedback signal FN by differentially amplifying the amplified signal pair.

FIG.8is a graph illustrating changes in the gain of the buffer circuit600in accordance with an embodiment of the present disclosure. The operation of the buffer circuit600in accordance with an embodiment of the present disclosure will be described below with reference toFIGS.6to8. When the frequencies of the input signal IN and the input bar signal INB are relatively low, the first frequency control signal FC11may be disabled. When the first frequency control signal FC11is disabled, the switching transistor642may be turned on and may electrically connect the first and second nodes N1and N2. Furthermore, the feedback circuit661may be deactivated based on the first frequency control signal FC11, and the first to third load transistors613to615may increase the resistance value of the load circuit610based on the first frequency control signal FC11. Accordingly, the buffer circuit600may increase the AC gain of the buffer circuit600as indicated by A and have a gain suitable for buffering the input signal IN and the input bar signal INB each having a relatively low frequency. Additionally, when the second frequency control signal FC12is disabled, the first to sixth current sources651to656may decrease the amount of current of the first to sixth current sources651to656, respectively. Accordingly, the buffer circuit600may further increase the DC gain of the buffer circuit600as indicated by B.

When the frequencies of the input signal IN and the input bar signal INB are relatively high, the first frequency control signal FC11may be enabled. When the first frequency control signal FC11is enabled, the switching transistor642may be turned off and the first and second nodes N1and N2may be connected to each other through the capacitor641. The first to third load transistors613to615may all be turned on, and the resistance value of the load circuit610may be decreased. The feedback circuit661may be activated based on the first frequency control signal FC11to generate the first and second feedback signals FP and FN, the voltage level of the second output node ON2may be additionally changed based on the first feedback signal FP, and the voltage level of the first output node ON1may be additionally changed based on the second feedback signal FN. Accordingly, the buffer circuit600may increase the AC gain as indicated by C and have a gain suitable for buffering the input signal IN and the input bar signal INB each having a relatively high frequency. When the second frequency control signal FC12is enabled together, the first to sixth current sources651to656may increase the amount of current of the first to sixth current sources651to656based on the second frequency control signal FC12, respectively. Accordingly, the buffer circuit600may further increase the AC gain of the buffer circuit600as indicated by D.

FIG.9is a diagram illustrating the configuration of the data clock generator244illustrated inFIG.2. Referring toFIG.9, the data clock generator244may include a first latch811, a second latch812, a third latch813, a fourth latch814, a fifth latch815, a sixth latch816, a first inverter821, a second inverter822, a third inverter823, a fourth inverter824, and a fifth inverter825. The first latch811may receive an output signal D of the phase controller243and the reference clock bar signal RCKB. The first latch811may latch the voltage level of the output signal D of the phase controller243in synchronization with the rising edge of the reference clock bar signal RCKB. The second latch812may receive an output signal of the first latch811and the reference clock signal RCK. The second latch812may latch the voltage level of the output signal of the first latch811in synchronization with the rising edge of the reference clock signal RCK. The third latch813may receive an output signal of the second latch812and the reference clock bar signal RCKB. The third latch813may latch the voltage level of the output signal of the second latch812in synchronization with the rising edge of the reference clock bar signal RCKB. The fourth latch814may receive an output signal of the third latch813and the reference clock signal RCK. The fourth latch814may latch the voltage level of the output signal of the third latch813in synchronization with the rising edge of the reference clock signal RCK. The fifth latch815may receive an output signal of the fourth latch814and the reference clock bar signal RCKB. The fifth latch815may latch the voltage level of the output signal of the fourth latch814in synchronization with the rising edge of the reference clock bar signal RCKB. The sixth latch816may receive an output signal of the fifth latch815and the reference clock signal RCK. The sixth latch816may latch the voltage level of the output signal of the fifth latch815in synchronization with the rising edge of the reference clock signal RCK.

The data clock signal DCK may include a first data clock signal DCK1, a second data clock signal DCK2, a third data clock signal DCK3, and a fourth data clock signal DCK4. The first inverter821may receive the output signal of the second latch812. The first inverter821may generate the fourth data clock signal DCK4by inverting the output signal of the second latch812. The second inverter822may receive the output signal of the third latch813. The second inverter822may generate the third data clock signal DCK3by inverting the output signal of the third latch813. The third inverter823may receive the output signal of the fourth latch814. The third inverter823may generate the second data clock signal DCK2by inverting the output signal of the fourth latch814. The fourth inverter824may receive the output signal of the fifth latch815. The fourth inverter824may generate the first data clock signal DCK1by inverting the output signal of the fifth latch815. The fifth inverter825may receive the output signal of the sixth latch816. The first to fourth data clock signals DCK1to DCK4output from the first to fourth inverters821to824may the same frequency as the frequency of the output signal D of the phase controller243and have a lower frequency than the reference clock signal pair RCK and RCKB. The first data clock signal DCK1may have a phase ahead of the second data clock signal DCK2by 90°, and the second data clock signal DCK2may have a phase ahead of the third data clock signal DCK3by 90°. The third data clock signal DCK3may have a phase ahead of the fourth data clock signal DCK4by 90°, and the fourth data clock signal DCK4may have a phase ahead of the first data clock signal DCK1by 90°.

A person skilled in the art to which the present disclosure pertains can understand that the present disclosure may be carried out in other specific forms without changing its technical spirit or essential features. Therefore, it should be understood that the embodiments described above are illustrative in all aspects, not limitative. The scope of the present disclosure is defined by the claims to be described below rather than the detailed description, and it should be construed that all changes or modified forms derived from the meaning and scope of the claims and the equivalent concept thereof are included in the scope of the present disclosure.