Semiconductor arrangement and method of making

A semiconductor arrangement is provided. The semiconductor arrangement includes a first portion and a vertically conductive structure. The first portion includes a first dielectric layer and a first guard ring in the first dielectric layer. The first guard ring includes, in the first dielectric layer, a first metal layer coupled to a first via. The first portion includes a vertical conductive structure passing through the first dielectric layer and proximate by the first guard ring.

BACKGROUND

Semiconductor arrangements are used in a multitude of electronic devices, such as mobile phones, laptops, desktops, tablets, watches, gaming systems, and various other industrial, commercial, and consumer electronics. Semiconductor arrangements generally comprise semiconductor portions and wiring portions formed inside the semiconductor portions.

DETAILED DESCRIPTION

Some embodiments relate to a semiconductor arrangement. In accordance with some embodiments, the semiconductor arrangement includes a first portion including a first passivation layer, a first dielectric layer over the first passivation layer, a first substrate over the first dielectric layer, a first conductive layer over the first substrate, and a first guard ring in the first dielectric layer. The semiconductor arrangement includes a second portion under the first portion. The second portion includes a second passivation layer and a second conductive layer in the second passivation layer. The semiconductor arrangement includes a vertical conductive structure passing through the first substrate, the first dielectric layer, and the first passivation layer. In some embodiments, the vertical conductive structure contacts the first conductive layer and the second conductive layer and is surrounded by the guard ring.

According to some embodiments, the first dielectric layer is an extra low-k (ELK) dielectric having a dielectric constant of about 2.6 or less. According to some embodiments, the guard ring protects, shields, electrically isolates, etc. at least one of the vertical conductive structure or the first dielectric layer. In some embodiments, the guard ring provides support, reinforcement, structural integrity, etc. for at least one of the vertical conductive structure or the first dielectric layer.

FIGS. 1-12illustrate a semiconductor arrangement100at various stages of fabrication, in accordance with some embodiments.

Referring toFIG. 1, a semiconductor arrangement100includes a first portion110and a second portion140, according to some embodiments. In some embodiments, the first portion110and the second portion140are fabricated separately and then placed together. In some embodiments, the first portion110is fabricated, inverted to the orientation illustrated inFIG. 1, and then placed on top of the second portion140.

In some embodiments, the first portion110includes a first passivation layer112, a first dielectric layer114over the first passivation layer112, a second dielectric layer120over the first dielectric layer114, a third dielectric layer122over the second dielectric layer120, a fourth dielectric layer124over the third dielectric layer122, a first interlayer dielectric (ILD) layer126over the fourth dielectric layer124, and a first substrate116over the first ILD layer126. A first guard ring118is in the first dielectric layer114, the second dielectric layer120, the third dielectric layer122, and the fourth dielectric layer124, according to some embodiments. In some embodiments, the first portion110includes more than four dielectric layers. In some embodiments, the first portion110includes fewer than four dielectric layers. In some embodiments, the first guard ring118is in all of the dielectric layers. In some embodiments, the first guard ring118is in fewer than all of the dielectric layers.

In some embodiments, the first passivation layer112includes at least one of AlN, Al2O3, SiO2, or Si3N4, or other suitable materials. In some embodiments, the first passivation layer112includes a chemically inert, corrosion-resistant dielectric material. In some embodiments, the first passivation layer112includes an organic compound having at least one of an N-, P- or S-group molecular structure. In some embodiments, the first passivation layer112has a dielectric constant of about 4.2.

In some embodiments, the first passivation layer112is formed by at least one of physical vapor deposition (PVD), sputtering, chemical vapor deposition (CVD), low pressure CVD (LPCVD), atomic layer chemical vapor deposition (ALCVD), ultrahigh vacuum CVD (UHVCVD), reduced pressure CVD (RPCVD), molecular beam epitaxy (MBE), liquid phase epitaxy (LPE), spin coating, oxidation, a passivation process, or other suitable techniques. In some embodiments, a chemically-stable material is used to produce the first passivation layer112. In some embodiments, the passivation process is a process in which a film covers an underlying material, such as the first dielectric layer114prior to the first portion110being inverted to the orientation illustrated inFIG. 1. In some embodiments, the film inhibits dissolution of the underlying material. In some embodiments, the film reduces chemical reactivity with regard to the underlying material. In some embodiments, the film reduces electrical reactivity with regard to the underlying material. In some embodiments, the passivation process includes at least one of oxidation of a surface of the underlying material or complexing of the surface with an organic compound. In some embodiments, the first passivation layer112inhibits diffusion of at least one of charges, atoms, or ions into the underlying material. In some embodiments, the first passivation layer112mitigates oxidation of the underlying material. In some embodiments, the first passivation layer112protects the underlying material from environmental conditions. In some embodiments, the first passivation layer112acts as a diffusion barrier with regard to the underlying material.

In some embodiments, at least one of the dielectric layers114,120,122, or124includes at least one of a polymer, an oxide, polybenzobisoxazole (PBO), a polyimide (PI), a metal nitride, silicon, germanium, carbide, gallium, arsenide, germanium, arsenic, indium, silicon oxide, sapphire, or other suitable materials. In some embodiments, at least one of the dielectric layers114,120,122, or124electrically insulates inter connect lines in the first portion110. In some embodiments, at least one of the dielectric layers114,120,122, or124is formed by at least one of physical vapor deposition (PVD), sputtering, chemical vapor deposition (CVD), low pressure CVD (LPCVD), atomic layer chemical vapor deposition (ALCVD), ultrahigh vacuum CVD (UHVCVD), reduced pressure CVD (RPCVD), molecular beam epitaxy (MBE), liquid phase epitaxy (LPE), spin coating, oxidation, or other suitable techniques. In some embodiments, at least some of the dielectric layers are formed in a same manner. In some embodiments, at least some of the dielectric layers are formed in different manners.

According to some embodiments, at least one of the dielectric layers114,120,122, or124is an ELK dielectric having a dielectric constant of about 2.6 or less. In some embodiments, at least one of the dielectric layers114,120,122, or124has a dielectric constant less than a dielectric constant of the first passivation layer112.

In some embodiments, the first ILD layer126includes at least one of tetraethylorthosilicate (TEOS), borophosphosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), boron doped silicon glass (BSG), polymeric thermoset material, or other suitable materials. In some embodiments, the first ILD layer126reduces capacitive coupling between adjacent conductive lines. In some embodiments, the first ILD layer126has a dielectric constant of about 4.2. In some embodiments, the first ILD layer126is formed by at least one of physical vapor deposition (PVD), sputtering, chemical vapor deposition (CVD), low pressure CVD (LPCVD), atomic layer chemical vapor deposition (ALCVD), ultrahigh vacuum CVD (UHVCVD), reduced pressure CVD (RPCVD), molecular beam epitaxy (MBE), liquid phase epitaxy (LPE), or other suitable techniques.

In some embodiments, the first substrate116includes at least one of an epitaxial layer, a silicon-on-insulator (SOI) structure, a wafer, or a die formed from a wafer. In some embodiments, the first substrate116includes silicon or other suitable materials.

According to some embodiments, the first guard ring118includes at least one of a metal layer128or a vertical interconnect access (VIA)130. According to some embodiments, at least one of the metal layer128or the VIA130includes at least one of Al, Cu, Sn, Ni, Au, Ag, W, or other suitable material. In some embodiments, at least one of the metal layer128or the VIA130does not include metal. In some embodiments, at least one of the metal layer128or the VIA130is in at least one of the dielectric layers114,120,122, or124. According to some embodiments, the first guard ring118includes alternating layers of the metal layer128and the VIA130. According to some embodiments, at least some of the metal layers128have a same width. In some embodiments, at least some of the metal layers128have different widths. In some embodiments, at least some of the metal layers128have a same height. In some embodiments, at least some of the metal layers128have different heights. In some embodiments, at least some of the metal layers128have different compositions as compared to other metal layers128. In some embodiments, at least some of the VIAs130have a same width. In some embodiments, at least some of the VIAs130have different widths. In some embodiments, at least some of the VIAs130have a same height. In some embodiments, at least some of the VIAs130have different heights. In some embodiments, at least some of the VIAs130have different compositions as compared to other VIAs130.

According to some embodiments, a width of at least some metal layers128is different than a width of at least some VIAs130. In some embodiments, a width of at least some metal layers128is the same as a width of at least some VIAs130. In some embodiments, a height of at least some metal layers128is different than a height of at least some VIAs130. In some embodiments, a height of at least some metal layers128is the same as a height of at least some VIAs130. In some embodiments, the first guard ring118has a width132of about 3 micrometers to about 6 micrometers. In some embodiments, the first guard ring118has a height134of about 0.5 micrometer to about 4 micrometers.

In some embodiments, at least one of the metal layer128or the VIA130is formed by at least one of lithography, etching, physical vapor deposition (PVD), sputtering, chemical vapor deposition (CVD), low pressure CVD (LPCVD), atomic layer chemical vapor deposition (ALCVD), ultrahigh vacuum CVD (UHVCVD), reduced pressure CVD (RPCVD), molecular beam epitaxy (MBE), liquid phase epitaxy (LPE), or other suitable techniques. In the lithography, a light sensitive material, such as a photoresist is formed over a layer to be patterned. Properties, such as solubility, of the photoresist are affected by the light. The photoresist is either a negative photoresist or a positive photoresist. With respect to the negative photoresist, regions of the negative photoresist become insoluble when illuminated by a light source, such that application of a solvent to the negative photoresist during a subsequent development stage removes non-illuminated regions of the negative photoresist. A pattern formed in the negative photoresist is thus a negative of a pattern defined by opaque regions of a template between the light source and the negative photoresist. In the positive photoresist, illuminated regions of the positive photoresist become soluble and are removed via application of the solvent during development. Thus, a pattern formed in the positive photoresist is a positive image of opaque regions of the template between the light source and the positive photoresist. According to some embodiments, an etchant has a selectivity such that the etchant removes or etches away the layer under the photoresist at a greater rate than the etchant removes or etches away the photoresist. Accordingly, an opening in the photoresist allows the etchant to form a corresponding opening in the layer under the photoresist, and thereby transfer a pattern in the photoresist to the layer under the photoresist. The pattern in the layer under the photoresist is filled with one or more materials to form one or more elements, features, etc. and the patterned photoresist is stripped or washed away at least one of before or after the pattern in the layer under the photoresist is filled with the one or more materials. In some embodiments, a dual damascene process is used to form at least one of a metal layer128or a VIA130.

In some embodiments, a metal layer128and a VIA130are formed in the first dielectric layer114, then the second dielectric layer120is formed and a metal layer128and a VIA130are formed in the second dielectric layer120, then the third dielectric layer122is formed and a metal layer128and a VIA130are formed in the third dielectric layer122, then the fourth dielectric layer124is formed and a metal layer128and a VIA130are formed in the fourth dielectric layer124. In some embodiments, such a process is repeated any number of times to form the first guard ring118. In some embodiments, the one or more dielectric layers do not include at least one of a metal layer128or a VIA130. In some embodiments, the first guard ring118is discontinuous in that one or more intervening dielectric layers do not include at least one of a metal layer128or a VIA130. In some embodiments, at least one of one or more of the metal layers128or one or more of the VIAs130are formed prior to at least some of a surrounding dielectric layer, such as at least one of at least some of the first dielectric layer114, at least some of the second dielectric layer120, at least some of the third dielectric layer122, or at least some of the fourth dielectric layer124. In some embodiments, at least some of a layer is formed and patterned to form at least one metal layer128and then at least some of the first dielectric layer114is formed around the at least one metal layer128such that the at least one metal layer128is in the first dielectric layer114. In some embodiments, at least some of a layer is formed and patterned to form at least one VIA130and then at least some of the first dielectric layer114is formed around the at least one VIA130such that the at least one VIA130is in the first dielectric layer114. In some embodiments, at least some of a layer is formed and patterned to form at least one metal layer128and then at least some of the second dielectric layer120is formed around the at least one metal layer128such that the at least one metal layer128is in the second dielectric layer120. In some embodiments, at least some of a layer is formed and patterned to form at least one VIA130and then at least some of the second dielectric layer120is formed around the at least one VIA130such that the at least one VIA130is in the second dielectric layer120. In some embodiments, at least some of a layer is formed and patterned to form at least one metal layer128and then at least some of the third dielectric layer122is formed around the at least one metal layer128such that the at least one metal layer128is in the third dielectric layer122. In some embodiments, at least some of a layer is formed and patterned to form at least one VIA130and then at least some of the third dielectric layer122is formed around the at least one VIA130such that the at least one VIA130is in the third dielectric layer122. In some embodiments, at least some of a layer is formed and patterned to form at least one metal layer128and then at least some of the fourth dielectric layer124is formed around the at least one metal layer128such that the at least one metal layer128is in the fourth dielectric layer124.

In some embodiments, the first portion110includes at least one of one or more conductive elements200or one or more contacts201. In some embodiments, at least some of the conductive elements200include at least one of Al, Cu, Sn, Ni, Au, Ag, W, or other suitable materials. In some embodiments, at least some of the conductive elements200have a same composition as at least one of at least some of the metal layers128or at least some of the VIAs130. In some embodiments, at least some of the conductive elements200have a different composition than at least one of at least some of the metal layers128or at least some of the VIAs130. In some embodiments, at least some of the conductive elements200have different compositions as compared to other conductive elements200. In some embodiments, at least some of the contacts201include at least one of Al, Cu, Sn, Ni, Au, Ag, W, or other suitable materials. In some embodiments, at least some of the contacts201have a same composition as at least one of at least some of the metal layers128, at least some of the VIAs130, or at least some of the conductive elements200. In some embodiments, at least some of the contacts201have a different composition than at least one of at least some of the metal layers128, at least some of the VIAs130, or at least some of the conductive elements200. In some embodiments, at least some of the contacts201have different compositions as compared to other contacts201. In some embodiments, at least one of the conductive element200or the contact201does not include metal. In some embodiments, at least some contacts201are in 0contact with at least some conductive elements200. In some embodiments, a conductive element200serves as a routing line in the semiconductor arrangement100and a contact201that is in touch with the conductive element provides an electrically conductive pathway to the routing line.

According to some embodiments, any of the conductive elements200have any desired shape or size. According to some embodiments, any of the contacts201have any desired shape or size. In some embodiments, at least one of the conductive element200or the contact201is formed by at least one of lithography, etching, physical vapor deposition (PVD), sputtering, chemical vapor deposition (CVD), low pressure CVD (LPCVD), atomic layer chemical vapor deposition (ALCVD), ultrahigh vacuum CVD (UHVCVD), reduced pressure CVD (RPCVD), molecular beam epitaxy (MBE), liquid phase epitaxy (LPE), or other suitable techniques. In some embodiments, a conductive element200is formed in the first dielectric layer114, then the second dielectric layer120is formed and a conductive element200is formed in the second dielectric layer120, then the third dielectric layer122is formed and a conductive element200is formed in the third dielectric layer122, then the fourth dielectric layer124is formed and a conductive element200is formed in the fourth dielectric layer124. In some embodiments, such a process is repeated any number of times. In some embodiments, at least one of the dielectric layers do not include a conductive element200. In some embodiments, the first ILD layer126is formed and a contact201is formed, such as by etching and deposition, in the first ILD layer126. In some embodiments, at least one of one or more of the conductive elements200or one or more of the contacts201are formed prior to at least some of a surrounding layer, such as at least one of at least some of the first dielectric layer114, at least some of the second dielectric layer120, at least some of the third dielectric layer122, at least some of the fourth dielectric layer124, or at least some of the first ILD layer126. In some embodiments, at least some of a layer is formed and patterned to form at least one conductive element200and then at least some of the first dielectric layer114is formed around the at least one conductive element200such that the at least one conductive element200is in the first dielectric layer114. In some embodiments, at least some of a layer is formed and patterned to form at least one conductive element200and then at least some of the second dielectric layer120is formed around the at least one conductive element200such that the at least one conductive element200is in the second dielectric layer120. In some embodiments, at least some of a layer is formed and patterned to form at least one conductive element200and then at least some of the third dielectric layer122is formed around the at least one conductive element200such that the at least one conductive element200is in the third dielectric layer122. In some embodiments, at least some of a layer is formed and patterned to form at least one conductive element200and then at least some of the fourth dielectric layer124is formed around the at least one conductive element200such that the at least one conductive element200is in the fourth dielectric layer124. In some embodiments, at least some of a layer is formed and patterned to form at least one contact201and then at least some of the first ILD layer126is formed around the at least one contact201such that the at least one contact201is in the first ILD layer126.

In some embodiments, the first portion110includes one or more etch stop layers136, such as between adjacent dielectric layers. In some embodiments, an etch stop layer has a different etch selectively relative to an overlying or adjacent layer such that when an etchant etches through the overlying layer the etching process slows or stops upon the etchant encountering the underlying etch stop layer. According to some embodiments, an etch stop layer comprises silicon, carbon, or other suitable materials. In some embodiments, at least some different etch stop layers have different compositions, such as due to the use of different etchants to etch different materials. In some embodiments, the etch stop layer136between the first ILD layer126and the fourth dielectric layer124has a different composition than at least one other etch stop layer136, such as due to a different etchant used to etch the first ILD layer126as compared an etchant used to etch at least one of the fourth dielectric layer124, the third dielectric layer122, the second dielectric layer120, or the first dielectric layer114.

In some embodiments, the second portion140includes a second passivation layer142, a conductive layer144in the second passivation layer142, a transition metal dielectric (TMD) layer146under the second passivation layer142, a first inter-metal dielectric (IMD) layer152under the TMD layer146, a second IMD layer154under the first IMD layer152, a third IMD layer156under the second IMD layer154, a fourth IMD layer158under the third IMD layer156, a second ILD layer160under the fourth IMD layer158, and a second substrate162under the second ILD layer160. In some embodiments, the second portion140includes more than four IMD layers. In some embodiments, the second portion140includes fewer than four IMD layers.

In some embodiments, the second passivation layer142includes at least one of AlN, Al2O3, SiO2, or Si3N4, or other suitable materials. In some embodiments, the second passivation layer142includes a chemically inert, corrosion-resistant dielectric material. In some embodiments, the second passivation layer142includes an organic compound having at least one of an N-, P- or S-group molecular structure. In some embodiments, the second passivation layer142includes heteroatoms. In some embodiments, the second passivation layer142has a dielectric constant of about 4.2. In some embodiments, the second passivation layer142has a same composition as the first passivation layer112. In some embodiments, the second passivation layer142has a different composition than the first passivation layer112. In some embodiments, the second passivation layer142is formed by at least one of a passivation process, physical vapor deposition (PVD), sputtering, chemical vapor deposition (CVD), low pressure CVD (LPCVD), atomic layer chemical vapor deposition (ALCVD), ultrahigh vacuum CVD (UHVCVD), reduced pressure CVD (RPCVD), molecular beam epitaxy (MBE), liquid phase epitaxy (LPE), spin coating, oxidation, or other suitable techniques. In some embodiments, the second passivation layer142is formed in a same manner as the first passivation layer112. In some embodiments, the second passivation layer142is formed in a different manner than the first passivation layer112.

In some embodiments, the conductive layer144includes at least one of Al, Cu, Sn, Ni, Au, Ag, W, or other suitable materials. In some embodiments, the conductive layer144includes a binary alloy of aluminum and copper. In some embodiments, the conductive layer144is embedded in the second passivation layer142so as to be covered on all sides by the second passivation layer142. In some embodiments, the conductive layer144is formed by at least one of lithography, etching, physical vapor deposition (PVD), sputtering, chemical vapor deposition (CVD), low pressure CVD (LPCVD), atomic layer chemical vapor deposition (ALCVD), ultrahigh vacuum CVD (UHVCVD), reduced pressure CVD (RPCVD), molecular beam epitaxy (MBE), liquid phase epitaxy (LPE), or other suitable techniques.

In some embodiments, the TMD layer146includes at least one of Al, Cu, Sn, Ni, Au, Ag, W, or other suitable materials. In some embodiments, the TMD layer146includes an atomically thin layer of a transition metal and a chalcogen. In some embodiments, the transition metal includes at least one of Mo, W, or other suitable materials. In some embodiments, the chalcogen includes at least one of S, Si, Te, or other suitable materials. According to some embodiments, atoms of the transition metal are sandwiched between two layers of chalcogen atoms. In some embodiments, the TMD layer146is formed by at least one of physical vapor deposition (PVD), sputtering, chemical vapor deposition (CVD), low pressure CVD (LPCVD), atomic layer chemical vapor deposition (ALCVD), ultrahigh vacuum CVD (UHVCVD), reduced pressure CVD (RPCVD), molecular beam epitaxy (MBE), liquid phase epitaxy (LPE), or other suitable techniques.

According to some embodiments, at least one of the IMD layers152,154,156, or158includes at least one of a polymer, an oxide, polybenzobisoxazole (PBO), a polyimide (PI), a metal nitride, silicon, germanium, carbide, gallium, arsenide, germanium, arsenic, indium, silicon oxide, sapphire, or other suitable materials. In some embodiments, at least one of the IMD layers152,154,156, or158electrically insulate inter connect lines in the second portion140. In some embodiments, at least one of the IMD layers152,154,156, or158is formed by at least one of physical vapor deposition (PVD), sputtering, chemical vapor deposition (CVD), low pressure CVD (LPCVD), atomic layer chemical vapor deposition (ALCVD), ultrahigh vacuum CVD (UHVCVD), reduced pressure CVD (RPCVD), molecular beam epitaxy (MBE), liquid phase epitaxy (LPE), spin coating, oxidation, or other suitable techniques. In some embodiments, at least some of the IMD layers are formed in a same manner. In some embodiments, at least some of the IMD layers are formed in different manners.

According to some embodiments, at least one of the IMD layers152,154,156, or158has a dielectric constant of about 3 or less. In some embodiments, at least one of the IMD layers152,154,156, or158has a dielectric constant less than a dielectric constant of the second passivation layer142.

In some embodiments, the second ILD layer160includes at least one of tetraethylorthosilicate (TEOS), borophosphosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), boron doped silicon glass (BSG), polymeric thermoset material, or other suitable materials. In some embodiments, the second ILD layer160reduces capacitive coupling between adjacent conductive lines. In some embodiments, the second ILD layer160has a dielectric constant of about 4.2. In some embodiments, the second ILD layer160is formed by at least one of physical vapor deposition (PVD), sputtering, chemical vapor deposition (CVD), low pressure CVD (LPCVD), atomic layer chemical vapor deposition (ALCVD), ultrahigh vacuum CVD (UHVCVD), reduced pressure CVD (RPCVD), molecular beam epitaxy (MBE), liquid phase epitaxy (LPE), or other suitable techniques. In some embodiments, the second ILD layer160is formed in a same manner as the first ILD layer126. In some embodiments, the second ILD layer160is formed in a different manner than the first ILD layer126.

In some embodiments, the second substrate162includes at least one of an epitaxial layer, a silicon-on-insulator (SOI) structure, a wafer, or a die formed from a wafer. In some embodiments, the second substrate162includes silicon or other suitable materials. In some embodiments, the second substrate162has a same composition as the first substrate116. In some embodiments, the second substrate162has a different composition than the first substrate116. In some embodiments, the second portion140includes at least one of one or more conductive elements200, one or more contacts201, or one or more etch stop layers136. In some embodiments, at least some of the conductive elements200in the second portion140at least one of have a same composition, are formed in a same manner, perform a same function, etc. as at least some of the conductive elements200in the first portion110. In some embodiments, at least some of the contacts201in the second portion140at least one of have a same composition, are formed in a same manner, perform a same function, etc. as at least some of the contacts201in the first portion110. In some embodiments, at least some of the etch stop layers136in the second portion140at least one of have a same composition, are formed in a same manner, perform a same function, etc. as at least some of the etch stop layers136in the first portion110.

FIG. 2illustrates the first portion110on the second portion140, according to some embodiments. According to some embodiments, the first passivation layer112contacts the second passivation layer142. According to some embodiments, the first passivation layer112is adhered to the second passivation layer142. According to some embodiments, a delineation persists between the first passivation layer112and the second passivation layer142despite the first passivation layer112being at least one of in contact with or adhered to the second passivation layer142.

Referring toFIG. 3, an opening180is formed in the first portion110and the second portion140. In some embodiments, the opening180is formed so that the opening180is surrounded by the first guard ring118. In some embodiments, the opening180is formed from a top surface of the first substrate116and extends through the first substrate116, the first ILD layer126, the fourth dielectric layer124, the third dielectric layer122, the second dielectric layer120, the first dielectric layer114, the first passivation layer112, and the second passivation layer142. In some embodiments, the opening180exposes the conductive layer144.

In some embodiments, the opening180is formed by at least one of lithography, etching, or other suitable techniques. According to some embodiments, an etchant has a selectivity such that the etchant removes or etches away the first substrate116, the first ILD layer126, the fourth dielectric layer124, the third dielectric layer122, the second dielectric layer120, the first dielectric layer114, the first passivation layer112, and the second passivation layer142at a greater rate than the etchant removes or etches away an overlying patterned photoresist. According to some embodiments, the opening180is defined by sidewalls of the first substrate116, the first ILD layer126, the fourth dielectric layer124, the third dielectric layer122, the second dielectric layer120, the first dielectric layer114, the first passivation layer112, and the second passivation layer142. In some embodiments, the etchant removes or etches away an amount of at least one of the first substrate116, the first ILD layer126, the fourth dielectric layer124, the third dielectric layer122, the second dielectric layer120, the first dielectric layer114, the first passivation layer112, or the second passivation layer142so as to expose at least some of at least one of a metal layer128or a VIA130and thus at least some of the opening180is defined by at least some of at least one of a metal layer128or a VIA130.

In some embodiments, the opening180has a width182and a height184. In some embodiments, the width182is about 0.5 micrometers to about 4 micrometers. In some embodiments, the height184is about 3 micrometers to about 8 micrometers. According to some embodiments, the opening180is defined by tapered sidewalls such that the width182varies along the height184of the opening180. In some embodiments, the width182decreases moving in a direction from the first substrate116to the conductive layer144. According to some embodiments, the opening has any cross sectional profile, such as stair stepped, hourglass, non-tapered, etc., such as from at least one of using one or more etchants or using one or more etching processes, such as directional etching, isotropic etching, anisotropic etching, etc.

Referring toFIG. 4, a conductive material150is formed over the first substrate116and in the opening180. In some embodiments, the conductive material150includes at least one of includes Al, Cu, Sn, Ni, Au, Ag, W, or other suitable materials. In some embodiments, the conductive material is formed by at least one of focused-ion beam (FIB), physical vapor deposition (PVD), sputtering, chemical vapor deposition (CVD), low pressure CVD (LPCVD), atomic layer chemical vapor deposition (ALCVD), ultrahigh vacuum CVD (UHVCVD), reduced pressure CVD (RPCVD), molecular beam epitaxy (MBE), liquid phase epitaxy (LPE), or other suitable techniques.

Referring toFIG. 5, excess conductive material is removed to establish a vertical conductive structure186in the opening180. In some embodiments, removal of the excess material conductive exposes the top surface of the first substrate116. In some embodiments, the vertical conductive structure186has a width188and a height190. According to some embodiments, the width188of the vertical conductive structure186corresponds to the width182of the opening180. According to some embodiments, the height190of the vertical conductive structure186corresponds to the height184of the opening180. According to some embodiments, the vertical conductive structure186has any cross sectional profile. According to some embodiments, the vertical conductive structure186has a cross sectional profile that corresponds to the cross sectional profile of the opening. According to some embodiments, the width188varies along the height190of the vertical conductive structure186. In some embodiments, the width188decreases moving in a direction from the first substrate116to the conductive layer144. According to some embodiments, one or more sidewalls of the vertical conductive structure186are at least one of tapered, stair stepped, non-linear, non-tapered, etc. In some embodiments, the excess conductive material is removed by at least one of chemical mechanical polishing (CMP) or other suitable techniques. In some embodiments, an abrasive slurry is used in the removal of the excess material. In some embodiments, the vertical conductive structure186comprises a through-silicon VIA (TSV). In some embodiments, a TSV is a high-performance interconnect used as an alternative to wire-bond and flip chips. In some embodiments, the TSV is used in creating 3D packages. In some embodiments, the TSV is used to create 3D integrated circuits (ICs). In some embodiments, the TSV is used to shorten lengths of connections. In some embodiments, the vertical conductive structure186comprises a through-organic VIA (TOV).

According to some embodiments, a barrier layer (not shown) is formed over sidewalls, surfaces, etc. defining the opening180prior to the conductive material150. According to some embodiments, the barrier layer is relatively thin and does not fill the opening180, such that the conductive material150is formed over the barrier layer. According to some embodiments, the barrier layer includes at least one of titanium nitride, titanium oxynitride, tantalum nitride, tantalum oxynitride, tungsten nitride, or other suitable materials. In some embodiments, the barrier layer is formed by at least one of focused-ion beam (FIB), physical vapor deposition (PVD), sputtering, chemical vapor deposition (CVD), low pressure CVD (LPCVD), atomic layer chemical vapor deposition (ALCVD), ultrahigh vacuum CVD (UHVCVD), reduced pressure CVD (RPCVD), molecular beam epitaxy (MBE), liquid phase epitaxy (LPE), or other suitable techniques.

FIG. 6illustrates a top-down view of the semiconductor arrangement100ofFIG. 5when the first substrate116, the first ILD layer126, and the etch stop layer136are removed, according to some embodiments. According to some embodiments,FIG. 5corresponds to a cross sectional view taken along line5-5inFIG. 6. In some embodiments, the plurality of conductive elements200exist around the first guard ring118. In some embodiments, conductive elements200are used as wiring inside the semiconductor arrangement100. According to some embodiments, the first guard ring118completely surrounds, encircles, etc. all sides or sidewalls of the vertical conductive structure186. According to some embodiments, the first guard ring118is discontinuous or has a break so as to surround, encircle, etc. some but not all of the vertical conductive structure186.

Although illustrated as generally quadrilateral, according to some embodiments a top profile of at least one of the vertical conductive structure186or the first guard ring118is any desired shape other than quadrilateral, such as at least one of elliptical, polygonal, star shaped, etc.

Referring toFIG. 7, a conductive layer192is formed over the first substrate116and the vertical conductive structure186. In some embodiments, the conductive layer192includes at least one of Al, Cu, Sn, Ni, Au, Ag, W, or other suitable materials. In some embodiments, the conductive layer192has a same composition as at least one of the conductive layer144or the vertical conductive structure186. In some embodiments, the conductive layer192has a different composition than at least one of the conductive layer144or the vertical conductive structure186. In some embodiments, the conductive layer144is formed by at least one of physical vapor deposition (PVD), sputtering, chemical vapor deposition (CVD), low pressure CVD (LPCVD), atomic layer chemical vapor deposition (ALCVD), ultrahigh vacuum CVD (UHVCVD), reduced pressure CVD (RPCVD), molecular beam epitaxy (MBE), liquid phase epitaxy (LPE), or other suitable techniques.

Referring toFIG. 8, the conductive layer192is patterned so that portions of the conductive layer192are removed from the top surface of the first substrate116. In some embodiments, the portions of the conductive layer are removed such that the conductive layer192covers at least some of the vertical conductive structure186. In some embodiments, the conductive layer192is patterned by at least one of lithography, etching, or other suitable techniques. According to some embodiments, the vertical conductive structure186connects the conductive layer192in or on the first portion110of the semiconductor arrangement100to the conductive layer144in the second portion140of the semiconductor arrangement100while being at least partially surrounded, encircled, etc. by the first guard ring118.

FIG. 9, illustrates the semiconductor arrangement100according to some embodiments. In some embodiments a second guard ring194is formed adjacent to, around, concentric to, etc. the first guard ring118. In some embodiments, at least some of the second guard ring194is in contact with at least some of the first guard ring118. In some embodiments, the second guard ring194is not in contact with the first guard ring118.

According to some embodiments, the second guard ring194includes at least one of a metal layer196or a vertical interconnect access (VIA)198. According to some embodiments, at least one of the metal layer196or the VIA198includes at least one of Al, Cu, Sn, Ni, Au, Ag, W, or other suitable materials. In some embodiments, at least one of the metal layer196or the VIA198does not include metal. In some embodiments, the second guard ring194has a same composition as the first guard ring118. In some embodiments, the second guard ring194has a different composition than the first guard ring118.

In some embodiments, at least one of the metal layer196or the VIA198is in at least one of the dielectric layers114,120,122, or124. According to some embodiments, the second guard ring194includes alternating layers of the metal layer196and the VIA198. According to some embodiments, at least some of the metal layers196have a same width. In some embodiments, at least some of the metal layers196have different widths. In some embodiments, at least some of the metal layers196have a same height. In some embodiments, at least some of the metal layers196have different heights. In some embodiments, at least some of the VIAs198have a same width. In some embodiments, at least some of the VIAs198have different widths. In some embodiments, at least some of the VIAs198have a same height. In some embodiments, at least some of the VIAs198have different heights.

According to some embodiments, at least some of the metal layers196have a same width as at least one of at least some of the metal layers128, at least some of the VIAs130, or at least some of the VIAs198. In some embodiments, at least some of the metal layers196have a different width than at least one of at least some of the metal layers128, at least some of the VIAs130, or at least some of the VIAs198. In some embodiments, at least some of the metal layers196have a same height as at least one of at least some of the metal layers128, at least some of the VIAs130, or at least some of the VIAs198. In some embodiments, at least some of the metal layers196have a different height than at least one of at least some of the metal layers128, at least some of the VIAs130, or at least some of the VIAs198. In some embodiments, the second guard ring194has a width137of about 3 micrometers to about 7 micrometers. In some embodiments, the second guard ring194has a height138of about 0.5 micrometer to about 4 micrometers. In some embodiments, the width137of second guard ring194is the same as the width132of the first guard ring118. In some embodiments, the width137of second guard ring194is different than the width132of the first guard ring118. In some embodiments, the height138of second guard ring194is the same as the height134of the first guard ring118. In some embodiments, the height138of second guard ring194is different than the height134of the first guard ring118.

In some embodiments, at least one of the metal layer196or the VIA198is formed by at least one of lithography, etching, physical vapor deposition (PVD), sputtering, chemical vapor deposition (CVD), low pressure CVD (LPCVD), atomic layer chemical vapor deposition (ALCVD), ultrahigh vacuum CVD (UHVCVD), reduced pressure CVD (RPCVD), molecular beam epitaxy (MBE), liquid phase epitaxy (LPE), or other suitable techniques. In some embodiments, at least some of the second guard ring194is formed in a same manner as at least some of the first guard ring118. In some embodiments, at least some of the second guard ring194is formed in a different manner than at least some of the first guard ring118.

In some embodiments, a metal layer196and a VIA198are formed in the first dielectric layer114, then the second dielectric layer120is formed and a metal layer196and a VIA198are formed in the second dielectric layer120, then the third dielectric layer122is formed and a metal layer196and a VIA198are formed in the third dielectric layer122, then the fourth dielectric layer124is formed and a metal layer196and a VIA198are formed in the fourth dielectric layer124. In some embodiments, such a process is repeated any number of times to form the second guard ring194. In some embodiments, one or more dielectric layers do not include at least one of a metal layer196or a VIA198. In some embodiments, the second guard ring194is discontinuous in that one or more intervening dielectric layers do not include at least one of a metal layer196or a VIA198. In some embodiments, a dielectric layer includes some of the second guard ring194but none of the first guard ring118. In some embodiments, a dielectric layer includes none of the second guard ring194but some of the first guard ring118.

FIG. 10illustrates a top-down view of the semiconductor arrangement100ofFIG. 9when the conductive layer192, the first substrate116, the first ILD layer126, and the etch stop layer136are removed, according to some embodiments. According to some embodiments,FIG. 9corresponds to a cross sectional view taken along line9-9inFIG. 10. In some embodiments, the plurality of conductive elements200exist around the first guard ring118and the second guard ring194. In some embodiments, at least some of the plurality of conductive elements200have a same composition as at least one of at least some of the metal layers196or at least some of the VIAs198. In some embodiments, at least some of the plurality of conductive elements200have a different composition than at least one of at least some of the metal layers196or at least some of the VIAs198.

In some embodiments, conductive elements200are used as wiring inside the semiconductor arrangement100. According to some embodiments, the first guard ring118completely surrounds, encircles, etc. all sides or sidewalls of the vertical conductive structure186. According to some embodiments, the first guard ring118is discontinuous or has a break so as to surround, encircle, etc. some but not all of the vertical conductive structure186. According to some embodiments, the second guard ring194completely surrounds, encircles, etc. at least one of all sides or sidewalls of the vertical conductive structure186or all sides or sidewalls of the first guard ring118. According to some embodiments, the second guard ring194is discontinuous or has a break so as to surround, encircle, etc. some but not all of at least one of the vertical conductive structure186or the first guard ring118.

Although illustrated as generally quadrilateral, according to some embodiments a top profile of at least one of the vertical conductive structure186, the first guard ring118, or the second guard ring194is any desired shape other than quadrilateral, such as at least one of elliptical, polygonal, star shaped, etc.

FIG. 11illustrates the semiconductor arrangement100where the metal layers128, the VIAs130, the metal layers196, and the VIAs198have substantially uniform dimensions, such as widths and heights, according to some embodiments. In some embodiments, the first guard ring118is discontinuous in that one or more intervening dielectric layers do not include at least one of a metal layer128or a VIA130. In some embodiments, the second guard ring194is discontinuous in that one or more intervening dielectric layers do not include at least one of a metal layer196or a VIA198.

FIG. 12illustrates a top-down view of the semiconductor arrangement100ofFIG. 11when the conductive layer192, the first substrate116, the first ILD layer126, and the etch stop layer136are removed, according to some embodiments. According to some embodiments,FIG. 11corresponds to a cross sectional view taken along line11-11inFIG. 12.FIG. 12mirrorsFIG. 10given that merely the uppermost metal layer128of the first guard ring118and the uppermost metal layer196of the second guard ring194are visible inFIG. 10and inFIG. 12. According to some embodiments, the first guard ring118completely surrounds, encircles, etc. all sides or sidewalls of the vertical conductive structure186. According to some embodiments, the first guard ring118is discontinuous or has a break so as to surround, encircle, etc. some but not all of the vertical conductive structure186. According to some embodiments, the second guard ring194completely surrounds, encircles, etc. at least one of all sides or sidewalls of the vertical conductive structure186or all sides or sidewalls of the first guard ring118. According to some embodiments, the second guard ring194is discontinuous or has a break so as to surround, encircle, etc. some but not all of at least one of the vertical conductive structure186or the first guard ring118.

Although illustrated as generally quadrilateral, according to some embodiments a top profile of at least one of the vertical conductive structure186, the first guard ring118, or the second guard ring194is any desired shape other than quadrilateral, such as at least one of elliptical, polygonal, star shaped, etc.

According to some embodiments, the first portion110of the semiconductor arrangement100is associated with backside Illumination (BSI) contact image sensors (CIS). In some embodiments, image sensors are turned upside down and color filters and micro-lenses are applied to backsides of pixels for light collection. In some embodiments, such arrangements of elements increase an amount of light captured and thereby improve performance in low-light situations. In some embodiments, the second portion140of the semiconductor arrangement100is associated with an application specific integrated circuit (ASIC).

According to some embodiments, a semiconductor arrangement includes a first portion and a second portion under the first portion. The first portion includes a first passivation layer, a first dielectric layer over the first passivation layer, a first substrate over the first dielectric layer, a first conductive layer over the first substrate, and a first guard ring in the first dielectric layer. The second portion includes a second passivation layer, a second conductive layer in the second passivation layer, a second dielectric layer under the second passivation layer; and a second substrate under the second dielectric layer. The semiconductor arrangement includes a vertical conductive structure passing through the first substrate, the first dielectric layer, and the first passivation layer, wherein the vertical conductive structure contacts the first conductive layer and the second conductive layer and is surrounded by the first guard ring.

In some embodiments, the first passivation layer is in contact with the second passivation layer.

In some embodiments, the vertical conductive structure has a tapered sidewall.

In some embodiments, the first dielectric layer is an extra low-k dielectric.

In some embodiments, the first conductive layer covers portions of the first substrate.

In some embodiments, the first portion includes a second dielectric layer wherein the vertical conductive structure passes through the second dielectric layer and the first guard ring is in the second dielectric layer.

In some embodiments, the first portion includes a second guard ring in the first dielectric layer and surrounding the first guard ring.

In some embodiments, the first guard ring and the second guard ring are not connected to each other.

According to some embodiments, a semiconductor arrangement includes a first portion and a vertical conductive structure. The first portion includes a first dielectric layer and a first guard ring in the first dielectric layer, wherein the first guard ring comprises, in the first dielectric layer, a first metal layer coupled to a first via. The vertical conductive structure passes through the first dielectric layer and is proximate the first guard ring.

In some embodiments, the first portion includes a second dielectric layer wherein the vertical conductive structure passes through the second dielectric layer and the first guard ring is in the second dielectric layer.

In some embodiments, the first guard ring includes, in the second dielectric layer, a second metal layer coupled to a second via.

In some embodiments, the first portion includes a third dielectric layer between the first dielectric layer and the second dielectric layer, the vertical conductive structure passes through the third dielectric layer, and the first guard ring is not in the third dielectric layer.

In some embodiments, the first metal layer has a first width and the first via has a second width less than the first width.

In some embodiments, the first portion includes a second guard ring in the first dielectric layer and around the first guard ring.

In some embodiments, the first portion includes a second dielectric layer and a third dielectric layer, the third dielectric layer is between the first dielectric layer and the second dielectric layer, the vertical conductive structure passes through the second dielectric layer, the vertical conductive structure passes through the third dielectric layer, the first guard ring is in the second dielectric layer but not the third dielectric layer, and the second guard ring is in the third dielectric layer but not the second dielectric layer.

In some embodiments, the first dielectric layer is an extra low-k dielectric.

According to some embodiments, a method for forming a semiconductor arrangement, includes forming a first guard ring in a first dielectric layer and forming a vertical conductive structure having a tapered sidewall and that passes through the first dielectric layer and is surrounded by the first guard ring.

In some embodiments, the method includes forming a second guard ring in the first dielectric layer, wherein the second guard ring surrounds the first guard ring.

In some embodiments, the method includes forming the first guard ring in a second dielectric layer, wherein forming the vertical conductive structure includes forming the vertical conductive structure to pass through the second dielectric layer.

In some embodiments, forming the first guard ring includes forming a first metal layer in the first dielectric layer and forming a first via in the first dielectric layer and in contact with the first metal layer.

It will be appreciated that layers, features, elements, etc. depicted herein are illustrated with particular dimensions relative to one another, such as structural dimensions or orientations, for example, for purposes of simplicity and ease of understanding and that actual dimensions of the same differ substantially from that illustrated herein, in some embodiments. Additionally, a variety of techniques exist for forming the layers, regions, features, elements, etc. mentioned herein, such as at least one of etching techniques, planarization techniques, implanting techniques, doping techniques, spin-on techniques, sputtering techniques, growth techniques, or deposition techniques such as chemical vapor deposition (CVD), for example.