Method of forming a synchronous rectifier controller and structure therefor

In one embodiment, a synchronous rectifier controller is configured to initiate forming an off-time interval for a first period of time responsively to the controller forming a disable state of a switching signal wherein the control circuit maintains the switching signal in the disable state for at least the off-time interval. The controller is also configured to restart forming the off-time interval responsively to a voltage of a synchronous rectifier becoming a first value prior to expiration of the first period of time.

BACKGROUND OF THE INVENTION

The present invention relates, in general, to electronics, and more particularly, to semiconductors, structures thereof, and methods of forming semiconductor devices.

In the past, synchronous rectifiers were used to improve the efficiency of switching power supplies. The synchronous rectifier typically was enabled to assist in discharging an inductor used in the switching power supply. The subsequent disabling of the synchronous rectifier often resulted in multiple voltage transitions at the node to which the synchronous rectifier was connected. These multiple voltage transitions often were referred to as ringing. In some applications, the ringing could cause the synchronous rectifier to be incorrectly re-enabled during the ringing which resulted in inefficient operation of the switching power supply. In some applications, a blanking interval was formed when the synchronous rectifier was disabled and was used to ignore transitions that occur during the blanking interval. Often, the synchronous rectifier was still re-enabled subsequent to the blanking interval thereby still resulting in inefficient operation.

Accordingly, it is desirable to have a synchronous rectifier controller that results in efficient operation even during multiple voltage transitions, that minimizes the effect of the multiple voltage transitions, and that improves operation of the synchronous rectifier.

For simplicity and clarity of the illustration(s), elements in the figures are not necessarily to scale, and the same reference numbers in different figures denote the same elements, unless stated otherwise. Additionally, descriptions and details of well-known steps and elements are omitted for simplicity of the description. As used herein current carrying electrode means an element of a device that carries current through the device such as a source or a drain of an MOS transistor or an emitter or a collector of a bipolar transistor or a cathode or anode of a diode, and a control electrode means an element of the device that controls current through the device such as a gate of an MOS transistor or a base of a bipolar transistor. Although the devices are explained herein as certain N-channel or P-channel devices, or certain N-type or P-type doped regions, a person of ordinary skill in the art will appreciate that complementary devices are also possible in accordance with the present invention. One of ordinary skill in the art understands that the conductivity type refers to the mechanism through which conduction occurs such as through conduction of holes or electrons, therefore, and that conductivity type does not refer to the doping concentration but the doping type, such as P-type of N-type. It will be appreciated by those skilled in the art that the words during, while, and when as used herein relating to circuit operation are not exact terms that mean an action takes place instantly upon an initiating action but that there may be some small but reasonable delay(s), such as various propagation delays, between the reaction that is initiated by the initial action. Additionally, the term while means that a certain action occurs at least within some portion of a duration of the initiating action. The use of the word approximately or substantially means that a value of an element has a parameter that is expected to be close to a stated value or position. However, as is well known in the art there are always minor variances that prevent the values or positions from being exactly as stated. It is well established in the art that variances of up to at least ten per cent (10%) are reasonable variances from the ideal goal of exactly as described. When used in reference to a state of a signal, the term “asserted” means an active state of the signal and the term “negated” means an inactive state of the signal. The actual voltage value or logic state (such as a “1” or a “0”) of the signal depends on whether positive or negative logic is used. Thus, asserted can be either a high voltage or a high logic or a low voltage or low logic depending on whether positive or negative logic is used and negated may be either a low voltage or low state or a high voltage or high logic depending on whether positive or negative logic is used. Herein, a positive logic convention is used, but those skilled in the art understand that a negative logic convention could also be used. The terms first, second, third and the like in the claims or/and in the Detailed Description of the Drawings, as used in a portion of a name of an element are used for distinguishing between similar elements and not necessarily for describing a sequence, either temporally, spatially, in ranking or in any other manner. It is to be understood that the terms so used are interchangeable under appropriate circumstances and that the embodiments described herein are capable of operation in other sequences than described or illustrated herein.

DETAILED DESCRIPTION OF THE DRAWINGS

FIG. 1schematically illustrates a portion of an example of an embodiment of a switching power supply system100that includes a synchronous rectifier or transistor30. System100typically includes a transformer14that has a primary winding15and a secondary winding16which configures system100with a primary side and a secondary side. System100typically receives power between an input terminal11and a common return terminal12. A primary side switching controller18usually is configured to operate a primary side power switch19in order to regulate the value of an output voltage on the secondary side that is formed between an output22and a secondary side common return23to a target value. The output voltage is regulated to a target value within a range of values around the target value. For example, the target value may be five volts (5 v) and the range of values may be plus or minus five percent (5%) around the five volts. Controller18is configured to operate switch19to control current flow through a primary winding15of transformer14in order to regulate the value of the output voltage. Controller18typically includes a feedback (FB) input that receives a feedback signal from a feedback circuit27. The feedback signal typically is representative of the value of the output voltage formed between output22and return23.

The secondary side of system100typically includes a capacitor28that assists in filtering and forming the output voltage. A load21of system100is illustrated in a general manner by a resistor in order to simplify the drawings and descriptions. The secondary side also includes rectifier30and a synchronous rectifier controller135.

Controller135typically is configured to receive operating power to operate the elements within controller135between a voltage input terminal141and a common voltage return terminal140. A sync input138of controller135generally is configured to receive a sync signal from secondary winding16. In the preferred embodiment, the value of the sync signal is also representative of the source-to-drain voltage of rectifier30. Those skilled in the art will also understand that it is desirable to disable rectifier30when the value of the current from winding16is substantially zero and that the value and/or waveform of the sync signal can be used to determine the point at which the value of such current may be near zero. Those skilled in the art will also appreciate that common voltage return terminal140usually is connected to common return23to provide a common reference, such as a ground reference, for controller135. In some embodiments controller135may also include an input that is connected to the source of rectifier30in order to allow controller135to monitor the value of the sync signal. For the example embodiment illustrated inFIG. 1, terminal140is substantially the same as the source of rectifier30. In other embodiments, other elements may be in series between rectifier30and return23. System100may also include an optional resistor32that may be used to modify the value of the sync signal voltage which may adjust the relationship between the threshold voltage of comparators53-54and57relative to the value of the voltage on node17or value of the voltage dropped across rectifier30. Optional resistor32usually would be in series between input138and node17.

Controller135typically includes a driver circuit or driver44that is configured to receive a switching signal45that is used to enable and disable rectifier30. Driver44usually is a non-inverting driver with sufficient drive to supply the load of transistor30. Driver44may be an inverting driver in other embodiments. Driver44provides switching signal45to an output137which generally is connected to a gate of rectifier30. A control logic block or logic150is configured to assist in forming switching signal45. Controller135also includes a first circuit that is configured to initiate enabling rectifier30responsively to the sync signal becoming a first value. In one embodiment, the first circuit includes an on-time control circuit146which also includes a comparator53and an on-timer147. In some embodiments, circuit146may also include a first portion of logic150but may not include a portion of logic150in other embodiments. As will be seen further hereinafter, on-timer147is used to form a minimum time that the switching signal45is asserted, thus, forms a minimum on-time for rectifier30. A second circuit of controller135is configured to initiate disabling rectifier30responsively to the sync signal becoming a second value. In one embodiment, the second circuit includes a comparator54. In some embodiments, the second circuit may also include a second portion of logic150but may not include logic150in other embodiments. An off-time control circuit of controller135usually is configured to form an off-time interval of signal45responsively to the sync signal becoming a third value and is also configured to either extend the off-time interval or to reinitiate forming the off-time interval either prior to the off-time interval expiring or prior to the termination of the ringing, such as prior to a lowest voltage of the ringing being a positive value or the lowest voltage value of the ringing being greater than the first value. In one embodiment, the off-time control circuit includes a comparator57and a first timer or off-timer149. In some embodiments, the off-time control circuit may also include a third portion of logic150but may not include logic150in other embodiments. As will be seen further hereinafter, the off-time control circuit is configured to form a minimum time that controller135controls rectifier30to be disabled, for example, form a minimum off-time for rectifier30. In one embodiment, a current source52may be used to provide an off-set voltage to set a predetermined value for the threshold voltages of comparators54and57. In other embodiments, source52may be omitted.

Controller135may also include a time set input139that may be used to set a predetermined value for one of the time intervals formed by the off-time control circuit. For example, a resistor31may be connected to input139and off-timer149may be configured so that the value of resistor31sets a period of time that is formed by off-timer149. In one embodiment, the first period of time is chosen to be no less than a period of a frequency of the oscillations of the ringing. In other embodiments, the period of time may be formed in other ways such as by a digital timer where input139is used to set a digital value for the timer or as an analog value that off-timer149converts to a digital value. Controller135may also include an optional input that is used by on-timer147in a manner similar to the use of input139by off-timer149.

In some embodiments controller135may include an optional internal regulator42that receives an input voltage on terminal141and provides an internal regulated voltage on an output43that is used for operating elements of controller135such as providing operating power to comparators53-54and57, timers147and149, and logic150.

FIG. 2schematically illustrates a portion of an example of an embodiment of a switching power supply system10that is an alternate embodiment of system100described in the description ofFIG. 1. System10includes an example of a portion of an embodiment of a synchronous rectifier controller35that is an alternate embodiment of controller135that was explained in the description ofFIG. 1. Controller35includes an off-timer60that is an example of one embodiment of off-timer149that was explained in the description ofFIG. 1. Inputs38-41of controller35are similar to inputs138-141of controller135, and an output37is substantially similar to output137of controller135. A control logic block or logic50of controller35is substantially similar to logic150of controller135. An on-time control circuit46is substantially similar to on-time control circuit146of controller135. Circuit46includes comparator53that monitors the voltage drop across rectifier30. In another embodiment, comparator53may monitor the voltage on winding16at a terminal of winding16, such as a node17, that is connected to rectifier30. Circuit46also includes an on-timer47that is substantially similar to on-timer147of controller135.

Off-timer60includes a capacitor72that may be charged in order to form the off-time interval of off-timer60. A current source of off-timer60is configured to form a current66to charge capacitor72. In the preferred embodiment, the current source includes a voltage-to-current converter, configured as an amplifier65and a transistor64, and a current mirror that includes transistors62and63connected in a current mirror configuration. A comparator69is used to determine when capacitor72is charged to a threshold value in order to provide a timing signal70indicating expiration of the off-time interval formed by off-timer60. A reset transistor73is utilized to discharge capacitor72.

FIG. 3is a graph having plots that illustrate some of the signals formed by controller35. The abscissa indicates time and the ordinate indicates increasing value of the illustrated signals. This description has references toFIG. 2andFIG. 3. A plot80illustrates the value of the voltage on node17. In another embodiment, plot80may illustrate the source-to-drain voltage of rectifier30. A plot81illustrates a reset signal59that is formed by comparator57and an inverter58. A plot82illustrates switching signal45, and a plot83illustrates a pause signal75that is formed on an output of an OR gate74. A plot84illustrates timing signal70of off-timer60, and a plot85illustrates the voltage on capacitor72, such as at a node71.

In operation, the primary side switching controller18enables switch19in order to form a current flowing through winding15of transformer14. Switching controller18subsequently disables switch19which interrupts the current flow through winding15. Disabling switch19causes transformer14to couple energy into secondary winding16in order to form a current flowing through winding16to charge capacitor28. Disabling switch19also causes the voltage on node17to abruptly become negative as illustrated by plot80between a time T0and a time T1. On-time control circuit46is configured to monitor the voltage drop across rectifier30, detect the value of the sync signal becoming coming a first value, for example decreasing to value X illustrated by plot80at time T2, and initiate enabling rectifier30responsively to the sync signal becoming the first value. In the preferred embodiment, the value X is just slightly negative, relative to return23, but may be other values in other embodiments such as becoming a zero value for example. As the value of the voltage across rectifier30decreases past the value established at the non-inverting input of comparator53by a voltage reference51, comparator53detects the first value of the sync signal and forms a control signal that is used by logic50to assert signal45and enable rectifier30as illustrated by plot82at time T2. On-timer47forms an on-time interval responsively to the value of the sync signal decreasing to the first value, and controller35is configured to assert signal45for at least the on-time interval formed by on-timer47. This is sometimes referred to a minimum on-time for rectifier30. Enabling rectifier30for at least the on-time interval reduces the effect of oscillations from secondary winding16that may be formed around time T2as a result of enabling rectifier30. In some embodiments, the off-time control circuit may be configured to ignore or blank the value of reset signal59prior to the asserted state of switching signal45, such as between times T1-T2.

Controller35is configured to maintain the enable state of signal45until the voltage at node17increases to a second value, such as increasing to a value Y illustrated by plot80at a time T3. The value of the voltage at node17increasing to the second value may indicate that the energy in winding16is substantially dissipated and/or that the value of the secondary current is nearing zero. The second value typically is also a negative value but usually is less negative than the first value, thus, has a smaller magnitude. In other embodiments, the second value may have other voltage values such as being a positive value. As the value of the voltage drop across rectifier30becomes the second value, comparator54detects the second value of the sync signal and provides a control signal indicating that the second circuit should disable rectifier30. The second circuit uses the control signal from comparator54and negates signal45to form a disable state of switching signal45and to disable rectifier30as illustrated at time T3.

Disabling rectifier30may result in ringing or oscillations at node17such as the examples illustrated by plot80between times T3and T6. The off-time control circuit is configured to form an off-time interval and controller35is configured to prevent rectifier30from being re-enabled for at least this off-time interval. Between times T2-T3, the asserted state of signal45forces pause signal75on the output of OR gate74high which in turn enables transistor73to discharge capacitor72as illustrated by plots83and85at time T2. Transistor73remains enabled by signal45until signal45is negated near time T3. However, comparator57keeps reset signal59asserted, thus, transistor73remains enabled to discharge capacitor72. Disabling rectifier30causes the sync signal to oscillate as illustrated between times T4-T6. As the value of the sync signal increases to a third value, such as the value illustrated as Z, comparator57changes state thereby disabling transistor73. Disabling transistor73allows capacitor72to begin charging for a first period of time to the value represented by the voltage of Reference2or Ref268as illustrated by plot85at time T3. Thus, the off-time control circuit initiates forming the off-time interval responsively to the sync signal becoming the third value, for example as a result of disabling rectifier30, such as illustrated by plot85near time T4. Capacitor72continues to charge to form the off-time interval as illustrated by plot85between time T4and T5. Logic50uses the off-time interval to substantially prevent re-asserting signal45, thus, to substantially prevent re-enabling rectifier30by controller35, for at least the off-time interval in order to reduce the effects of oscillations around the time of disabling rectifier30. In some cases, oscillations may occur prior to expiration of the first period of time formed by off-timer60. For example, the ringing near time T3-T6could have multiple transitions that go below the first value (for example value X), such as illustrated by a dashed line87. Prior art circuits allow the re-enabling rectifier30as a result of this ringing, however, this would reduce the efficiency of a power supply system. Therefore, the off-time control circuit of controller35is configured to restart forming the off-time interval responsively to the sync signal becoming a third value, for example decreasing to the value Z in plot80after previously increasing to the third value. Those skilled in the art will appreciate that in some embodiments comparator57may have some hysteresis such that the first transition of the sync signal increasing to third value may be detected at a slightly different value from the second transition of the sync signal decreasing to third value. In the preferred embodiment, the third value is a positive value that is more positive than the first and second values. In other embodiments, the third value may be less positive or even a negative value. In the preferred embodiment, it is desirable to have the magnitude of the third value to be greater than the magnitude of either of the first or second values. Comparator57of the off-time control circuit detects the value of the sync signal becoming the third value subsequently to the disable state of signal45, for example decreasing to the value Z, and asserts reset signal59, through an inverter58, as illustrated by plot81at a time T5. Asserting reset signal59again enables transistor73to discharge capacitor72as illustrated by plot85at time T5. The value of the sync signal subsequently increases past the third value as illustrated by plot80at a time T6thereby again negating reset signal59and disabling transistor73. Disabling transistor73allows capacitor72to again begin charging, as illustrated by plot85at time T6, thus, to restart forming the off-time interval or to extend the off-time interval. From the foregoing, those skilled in the art will appreciate that controller35is configured to restart forming the off-time interval or extend the off-time interval prior to expiration of the first time period, for example a time period that is formed by at least a portion of a time needed for an uninterrupted charging of capacitor72toward Ref268by current66or prior to the termination of the ringing.

For the example illustrated inFIGS. 2-3, the sync signal does not again transition to less than the third value, thus, after time T6capacitor72continues to charge. Comparator69detects capacitor72charging to Ref268and asserts timing signal70to indicate expiration of the off-time interval near time T7. For the example embodiment illustrated inFIG. 2, timing signal70is asserted by the output of comparator69going low (negative logic for this example, but may be positive logic in other embodiments). Controller35is configured to allow the re-enabling of rectifier30subsequently to expiration of the off-time interval including expiration of restarting or extending the off-time interval.

For other example applications, if the ringing continued after time T5and again transitioned to less than the third value, controller35is configured to again detect the sync signal becoming the third value and to again restart forming the off-time interval or to extend the off-time interval.

The voltage to current converter formed by amplifier65and transistor64receives the voltage from Ref268and forms a current67that flows through resistor31. The value of current67is sufficient to maintain input39at the voltage formed by Ref268. Current67also flows through transistor63of the current mirror formed by transistors62and63. The value of current66used to charge capacitor72is ratioed to the value of current67by the ratio of the current mirrors transistor62and63. The value of current66, thus the time interval of the first period of time, can be set by choosing a value for resistor31. The smaller the value of resistor31, the larger the value of current66and the shorter the time interval of the first period of time. Those skilled in the art will appreciate that once a value is chosen for resistor31, it merely sets a pre-determined fixed time interval.

In order to provide the above described functionality for controller35, an inverting input of comparator53is commonly connected to a non-inverting input of amplifiers54and57and to sync input38. Sync input38is configured to be connected to a drain of rectifier30. A non-inverting input of comparator53is connected to a first terminal of reference51which has a second terminal connected to return40. An inverting input of comparator54is connected to receive a reference voltage, such as a reference voltage from terminal40. An inverting input of comparator57is connected to receive the value of Ref1from an output of Ref156. An output of comparator53is connected to a first input of logic50and to a first input of on-timer47. An output of on-timer47is connected to a second input of logic50. A second input of on-timer47is commonly connected to receive switching signal45from an output of controller logic50and to a first input of OR gate74. An output of comparator54is connected to a third input of logic50. An output of comparator57is connected to an input of inverter58which has an output connected to a second input of gate74. An output of gate74is connected to a gate of transistor73. A source of transistor73is commonly connected to a first terminal of capacitor72and to return terminal40. A second terminal of capacitor72is commonly connected to a drain of transistor62and to an inverting input of comparator69. A non-inverting input of comparator69is connected to an output of Ref268and to a non-inverting input of amplifier65. An output of comparator69is connected to a fourth input of logic50. An inverting input of amplifier65is commonly connected to input39and to a source of transistor64. An output of amplifier65is connected to a gate of transistor64. A drain of transistor64is commonly connected to a drain and gate of transistor63and to a gate of transistor62. A source of transistor63is commonly connected to a source of transistor62and to output43of regulator42. An output of driver44is connected to output37which is configured to be connected to a gate of rectifier30. Voltage input41is connected to an input of regulator42which has a common terminal connected to terminal40.

FIG. 4schematically illustrates an example of an embodiment of a portion of a switching power supply system160that is an alternate embodiment of system100and system10that were explained in the descriptions ofFIG. 1andFIGS. 2-3. System160is similar to system100except that system160includes a synchronous rectifier controller163that is an alternate embodiment of controller135that was explained in the description ofFIG. 1. Controller163is similar to controller135except that controller163includes an off-time control circuit that includes an off-timer176and a reset circuit166.

Off-timer176is configured to initiate forming the off-time interval for a first period of time responsively to negating signal45to initiate disabling rectifier30. Reset circuit166is configured to increase the first period of time formed by off-timer176responsively to the sync signal becoming the third value either prior to termination of the first period of time or prior to the termination of the ringing. As can be seen, reset circuit166detects the sync signal becoming the third value, increases the first period of time responsively to the sync signal becoming the third value, and then re-enables forming the off-time interval.

In operation, assume that rectifier30is enabled and that the value of the sync signal is increasing such as illustrated near time T3inFIG. 3. Comparator54detects the sync signal increasing to the second value, such as the value illustrated in plot80, and provides a control signal that is used by logic150to negate signal45. Off-timer176initiates forming the off-time interval responsively to the negated state of signal45. Reset circuit166is configured to detect the sync signal becoming the third value and to pause timer176to increase the off-time interval.

Circuit166includes a diode168, a zener diode169that is used as to form a reference voltage, and a transistor170that is configured to control the operation of off-timer176. As the value of the sync signal decreases to a value that is less than a threshold voltage established by the voltage of zener diode169, the voltage drop of diode168, and the threshold voltage of transistor170, transistor170becomes enabled. Enabling transistor170couples the value of the voltage on input139to substantially the voltage received on input terminal141or to some voltage that is high enough to pause off-timer176. For example, a voltage this is higher than the voltage applied to input139by off-timer176. Enabling transistor170applies the high voltage to input139and causes off-timer176to suspend timing out the first period of time thereby increasing the off-time interval. In one example embodiment, off-timer176charges a capacitor to form the first time interval. In this example embodiment, enabling transistor170substantially stops current from flowing into the capacitor thereby pausing the charging of the capacitor, thus, increasing the first period of time and increasing the off-time interval.

As the value of the sync voltage continues to increase, such as after time T6(FIG. 3), the value of the voltage applied to the gate of transistor170becomes large enough to prevent enabling transistor170. A resistor173and a capacitor174form an RC network that controls the time required to disable transistor170. In the preferred embodiment, the time constant of the RC network is chosen to be no less than a frequency of the ringing. The time constant may be other values in other embodiments. The time constant delays turning off transistor170for a period of time. In one embodiment, the time constant delays turning off transistor170for at least the period of the frequency of the ringing. Disabling transistor170disables circuit166thereby allowing off-timer176to continue forming the off-time interval from the point it was prior to the increased time formed by circuit166.

In one embodiment, off-timer176may be a portion of an integrated circuit controller and circuit166may be external to the integrated circuit. For example, off-timer176may be a portion of an NCP4303 manufactured by Semiconductor Components Industries, LLC (SCILLC) of Phoenix, Ariz. (DBA ON Semiconductor), and circuit166may be external to the NCP4303.

In one embodiment, off-timer176may include a current source and capacitor that may be substantially similar to theFIG. 2capacitor72, voltage-to-current converter of amplifier65and transistor64, the current mirror of transistors62-63.

In order to facilitate this functionality for controller163, a source of transistor170is commonly connected to output22, a first terminal of capacitor174and a first terminal of resistor173. A gate of transistor170is commonly connected to a second terminal of capacitor174, a second terminal of resistor173, and to a cathode of diode169. An anode of diode169is connected to an anode of diode168. A cathode of diode168is connected to input138, to node17, and to the drain of rectifier30.

FIG. 5schematically illustrates an example of an embodiment of a portion of a synchronous rectifier controller90that is an alternate embodiment of controllers35,135, and136that were explained in the description ofFIGS. 1-4. Controller90is similar to controller35except that controller90includes an off-time control circuit that is configured to initiate forming an off-time interval for a first period of time responsively to controller90initiating a disable state of rectifier30wherein controller90is configured to maintain rectifier30in the disable state for at least the off-time interval. The off-time control circuit is also configured to restart forming the off-time interval responsively to the sync signal becoming the third value prior to expiration of the first time period.

The off-time control circuit of controller90includes a D-type flip-flop or F-flop91, an inverter92, and an AND gate94.

FIG. 6is a graph having plots that illustrate some of the signals formed by controller90. The abscissa indicates time and the ordinate indicates increasing value of the illustrated signals. This description has references toFIGS. 3,5, andFIG. 6. A plot96illustrates a Q output of F-flop91, and a plot97illustrates an output of gate94.

In operation, signal45holds F-flop91reset while signal45is asserted to enable rectifier30(FIG. 2). The reset state of F-flop91negates the output of gate94to prevent reset signal59from affecting pause signal75. As controller90negates signal45to disable rectifier30, such as at time T3, the output of gate74remains negated regardless of the state of reset signal59. Therefore, controller90begins forming the first period of time of the off-time interval responsively to controller90initiating the disable state of rectifier30. At time T4, the sync signal increases to the third value, such value Z, which asserts signal59. The edge of signal59clocks a high level into F-flop91. The high Q output allows signal59to assert signal75and discharge capacitor72. Subsequently at time T6, the sync signal increases past the third value (FIG. 3) and the resulting negated state of reset signal59results in negating signal75to again charge capacitor72. Thus, the off-time control circuit increases the off-time interval or also can be viewed to restart the off-time interval prior to expiration of the first period of time.

FIG. 7schematically illustrates an embodiment of an off-time control circuit180that is an alternate embodiment of the off-time control circuit described in the description ofFIG. 4. Off-time control circuit180includes an off-timer181that is an alternate embodiment of timer176(FIG. 4). Off-timer181includes a current source178that is used to charge a capacitor172in order to form the first period of time of the off-time interval. A transistor182is used to discharge capacitor172, for example discharging capacitor172while rectifier30is enabled. Off-time control circuit180also includes a reset circuit179that is an alternate embodiment of circuit166(FIG. 4). Circuit179includes an additional transistor184. Although transistor184is illustrated as a bipolar transistor, it may be an MOS transistor or another type of switch element in other embodiments.

Assuming that transistor182is disabled, a current source178provides a current183to charge capacitor172. As reset circuit179enables transistor170, transistor170enables transistor184to discharge capacitor172thereby increasing the first period of time to a second period of time. Subsequently disabling transistor170also disables transistor184and allows source178to again generate current183to charge capacitor172. It can therefore be seen that reset circuit179increases the off-time interval by resetting and subsequently re-enabling the charging of capacitor172.

Those skilled in the art will appreciate that a current source such as current source178may also be used as a current source for charging capacitor72that is described in the description ofFIG. 2instead of the current mirror and/or the voltage-to-current converter.

FIG. 8illustrates an enlarged plan view of a portion of an embodiment of a semiconductor device or integrated circuit190that is formed on a semiconductor die191. Any of controllers35,135, or163or portions thereof may be formed on die191. Die191may also include other circuits that are not shown inFIG. 6for simplicity of the drawing. The controller and device or integrated circuit190are formed on die191by semiconductor manufacturing techniques that are well known to those skilled in the art.

Those skilled in the art will appreciate that in one embodiment, a synchronous rectifier controller may comprise: a control circuit, for example driver44and/or a portion of circuit50, configured to form a switching signal with an enable state to enable a synchronous rectifier and with a disable state to disable the synchronous rectifier;

a sync input configured to receive a sync signal that is representative of a voltage drop across the synchronous rectifier;

a first circuit, circuit47for example, configured to initiate the enable state of the switching signal responsively to the sync signal becoming a first value;

a second circuit, for example comparator54and/or a portion of circuit50, configured to initiate the disable state of the switching signal responsively to the sync signal becoming a second value that is greater than the first value;

an off-time control circuit, such as comparator57and circuit60or circuit166, having a first timer circuit that is configured to initiate forming an off-time interval for a first period of time wherein the control circuit maintains the switching signal in the disable state for at least the off-time interval; and

the off-time control circuit configured to restart forming the off-time interval responsively to the sync signal becoming a third value prior, such as value Z, to expiration of the first time period.

In another embodiment, the synchronous rectifier controller may also include that the off-time control circuit maintains the switching signal in the disable state for at least the off-time interval subsequently to forming the disable state of the switching signal, such as maintains the disabled state for at least the off-time interval.

Another embodiment of the synchronous rectifier controller may also include that the off-time control circuit initiates forming the off-time interval responsively to one of the disable state of the switching signal or the sync signal becoming the third value, for example decreases to Z at time T4.

Those skilled in the art will also understand that one embodiment of a method of forming a synchronous rectifier controller may comprise:

configuring the synchronous rectifier controller to initiate disabling a synchronous rectifier responsively to a voltage on a winding of a transformer that is coupled to the synchronous rectifier becoming a first value;

configuring an off-time control circuit, for example circuit66and comparator57or circuit166and timer176or the off-time control circuit of controller90, to form an off-time interval for a first period of time wherein the synchronous rectifier controller maintains the switching signal in the disable state for at least the off-time interval; and

configuring the off-time control circuit to increase the off-time interval by increasing the first period of time to a second period of time responsively to the voltage becoming a different value, for example value Z, prior to termination of ringing of the voltage, such as prior to the end of oscillations after time T3.

In another embodiment, the method may include, configuring the off-time control circuit to form the off-time interval responsively to one of initiating disabling the synchronous rectifier, initiating the disable state of signal45, or responsively to a second value of the voltage on the winding of the transformer, for example value Z after time T3.

In another embodiment, the method may include changing a digital value used to form the first period of time.

Another embodiment of the method may include, configuring the off-time control circuit to increase the off-time interval prior to expiration of the first period of time, such as prior to the voltage on capacitor72reaching the value of Ref2.

Another embodiment of the method may include, configuring the off-time control circuit to restart forming the first period of time prior to the expiration of the first period of time, for example restart charging capacitor72prior to reaching Ref2.

Those skilled in the art will also appreciate that a method of forming a synchronous rectifier controller may comprise:

configuring the synchronous rectifier controller to initiate a disable state a synchronous rectifier, such as negating signal45, responsively to a voltage of the synchronous rectifier becoming a first value;

configuring an off-time control circuit to form an off-time interval, such as at least a portion of the interval needed to charge capacitor72to value Ref2, responsively to the first value of the voltage; and

configuring the off-time control circuit to one of increase the off-time interval or reinitiate forming the off-time interval prior to termination of ringing of the voltage wherein the synchronous rectifier controller maintains the switching signal in the disable state for at least a portion of the off-time interval.

In another embodiment, the method may also include, configuring the off-time control circuit to form a first period of time, such as the time between T3and T5, responsively to the first value of the voltage and to form a second period of time, such as the time between T5and T7, responsively to a second value of the voltage wherein the off-time interval continues until expiration of both the first and the second time periods of time.

Another embodiment of the method may also include, configuring the off-time control circuit to form a first period of time and to one of increase the first period of time to a second period of time, such as increase as by circuit166or increase between time T3to T7, or reinitiate forming the first period of time, such as between time T5to T7, prior to termination of the ringing of the voltage, such as prior to the sync signal voltage no longer going below value Z.

Those skilled in the art will appreciate that in another embodiment, a synchronous rectifier controller may comprise: an enable means for enabling a synchronous rectifier for at least a first period of time;

a disable means for disabling the synchronous rectifier for a first period of time responsively to a first voltage value, for example value Y, of the synchronous rectifier; and

a means, for example the off-time control circuit, to either restart the first period of time, such as comparator57and off-timer60, or to extend the first period of time for a second period of time, for example the time signal59is asserted, responsively to a second voltage value of the synchronous rectifier.

In another embodiment, the synchronous rectifier controller may also include a means to terminate the second period of time, for example either comparator57negating signal59or circuit166disabling transistor170, responsively to the voltage of the synchronous rectifier again reaching the second voltage value.

In view of all of the above, it is evident that a novel device and method is disclosed. Included, among other features, is forming a synchronous rectifier controller to disable a synchronous rectifier for a first time interval in response to a voltage of the synchronous rectifier becoming a first value, value greater than Z for example, and to restart forming the first time interval or to extend the first time interval in response to the voltage of the synchronous rectifier again becoming the first value, less than value Z for example. Configuring the controller to keep the synchronous rectifier disabled for the time formed by restarting or extending the first time interval minimizes the effect of ringing on the system that uses the synchronous rectifier controller and also improves the efficiency of the system.

While the subject matter of the descriptions are described with specific preferred embodiments and example embodiments, the foregoing drawings and descriptions thereof depict only typical and example embodiments of the subject matter and are not therefore to be considered to be limiting of its scope, it is evident that many alternatives and variations will be apparent to those skilled in the art. As will be appreciated by those skilled in the art, the example forms of systems10,100, and160and controllers35,135,163, and180are used as a vehicle to explain the operation method of restarting formation of the first time interval or extending the first time interval. Although the controllers are illustrated in a flyback power supply system application, the controllers may be used in various other well-known types of power supply systems. Although rectifier30is illustrated in one leg of secondary winding16, it may be in the opposite leg or may be in primary side of the system. Those skilled in the art will also appreciate the other detector circuits may be used to detect the first, second, and third values instead of comparators53-54and57. For example, a transistor that is properly biased could also be used as a detector to detect a certain voltage value, thus three different transistors used for the three different values. Although the value of the sync signal is described as being detected by analog comparators, the value may be detected by using digital techniques such as converting the value to a digital number such as with an analog-to-digital converter, and then determining the magnitude of the digital number. Those skilled in the art will appreciate that the alternatives described for any ofFIGS. 1-5may also apply to any other of the drawings. One skilled in the art will understand that the drawings described herein are only schematic and are non-limiting, and that the size of some of the elements may be exaggerated and not drawn on scale for illustrative purposes. The dimensions and the relative dimensions may not correspond to actual reductions to practice of the invention. Further, the polarities of any of the signals may be changed with appropriate changes in the associated logic or polarities of other signals.

As the claims hereinafter reflect, inventive aspects may lie in less than all features of a single foregoing disclosed embodiment. Thus, the hereinafter expressed claims are hereby expressly incorporated into this Detailed Description of the Drawings, with each claim standing on its own as a separate embodiment of an invention. Furthermore, while some embodiments described herein include some but not other features included in other embodiments, combinations of features of different embodiments are meant to be within the scope of the invention, and form different embodiments, as would be understood by those skilled in the art.