Producing a semiconductor device by epitaxial growth

A method of producing a semiconductor device is presented. The method comprises: providing a semiconductor substrate having a surface; epitaxially growing, along a vertical direction (Z) perpendicular to the surface, a back side emitter layer on top of the surface, wherein the back side emitter layer has dopants of a first conductivity type or dopants of a second conductivity type complementary to the first conductivity type; epitaxially growing, along the vertical direction (Z), a drift layer having dopants of the first conductivity type above the back side emitter layer, wherein a dopant concentration of the back side emitter layer is higher than a dopant concentration of the drift layer; and creating, either within or on top of the drift layer, a body region having dopants of the second conductivity type, a transition between the body region and the drift layer forming a pn-junction (Zpn). Epitaxially growing the drift layer includes creating, within the drift layer, a dopant concentration profile (P) of dopants of the first conductivity type along the vertical direction (Z), the dopant concentration profile (P) in the drift layer exhibiting a variation of a concentration of dopants of the first conductivity type along the vertical direction (Z).

CROSS-REFERENCE TO RELATED APPLICATION

This application claims priority to German Application Serial No. 102015208097.8 filed Apr. 30, 2015 and entitled “Producing a Semiconductor Device by Epitaxial Growth”.

TECHNICAL FIELD

This specification refers to embodiments of a method of producing a semiconductor device and to embodiments of a semiconductor device. In particular, this specification refers to embodiments of a method of producing a semiconductor device by epitaxial growth of semiconductor layers.

BACKGROUND

Many functions of modern devices in automotive, consumer and industrial applications, such as converting electrical energy and driving an electric motor or an electric machine, rely on semiconductor devices. For example Insulated Gate Bipolar Transistors (IGBTs), Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) and diodes have been used for various applications including, but not limited to switches in power supplies and power converters.

Often, it is desirable to provide such power semiconductor devices with a soft switch-off behavior, i.e., to avoid, for example, a too early or too sudden break-down of the reverse recovery current during switch-off of a power semiconductor diode. At the same time, it is generally desirable to minimize the switching losses of power semiconductor devices. Such characteristics of a power semiconductor device can, e.g., be relevant for hard switching applications operating at high switching frequencies.

SUMMARY

According to an embodiment, a method of producing a semiconductor device is presented. The method comprises: providing a semiconductor substrate having a surface; epitaxially growing, along a vertical direction perpendicular to the surface, a back side emitter layer on top of the surface, wherein the back side emitter layer has dopants of a first conductivity type or dopants of a second conductivity type complementary to the first conductivity type; epitaxially growing, along the vertical direction, a drift layer having dopants of the first conductivity type above the back side emitter layer, wherein a dopant concentration of the back side emitter layer is higher than a dopant concentration of the drift layer; and creating, either within or on top of the drift layer, a body region having dopants of the second conductivity type, a transition between the body region and the drift layer forming a pn-junction. Epitaxially growing the drift layer includes creating, within the drift layer, a dopant concentration profile of dopants of the first conductivity type along the vertical direction, the dopant concentration profile in the drift layer exhibiting a variation of a concentration of dopants of the first conductivity type along the vertical direction.

According to a further embodiment, a further method of producing a semiconductor device is presented. The further method comprises: providing a semiconductor substrate having a surface; epitaxially growing, along a vertical direction perpendicular to the surface, a back side emitter layer on top of the surface, wherein the back side emitter layer has dopants of a first conductivity type or dopants of a second conductivity type complementary to the first conductivity type; epitaxially growing, along the vertical direction, a buffer layer on top of the back side emitter layer, the buffer layer having dopants of the first conductivity type; epitaxially growing, along the vertical direction, a drift layer having dopants of the first conductivity type on top of the buffer layer, wherein each of a dopant concentration of the back side emitter layer and a dopant concentration of the buffer layer is higher than a dopant concentration of the drift layer; and creating, either within or on top of the drift layer, a body region having dopants of the second conductivity type, a transition between the body region and the drift layer forming a pn-junction. Epitaxially growing the buffer layer includes creating, within the buffer layer, a dopant concentration profile of dopants of the first conductivity type along the vertical direction, the dopant concentration profile in the buffer layer exhibiting a variation of a concentration of dopants of the first conductivity type along the vertical direction.

According to yet a further embodiment, a semiconductor device is presented. The semiconductor device includes a semiconductor body having a front side and a back side, the semiconductor body extending in a vertical direction pointing from the back side to the front side and comprising: an epitaxially grown drift layer having dopants of a first conductivity type; a body region arranged either within or on top of the drift layer and having dopants of a second conductivity type complementary to the first conductivity type, a transition between the body region and the drift layer forming a pn-junction; and an epitaxially grown back side emitter layer arranged in between the drift layer and the back side, the back side emitter layer having dopants of the first or the second conductivity type and a higher dopant concentration than the drift layer. In the drift layer, a dopant concentration profile along the vertical direction exhibits a variation of a concentration of dopants of the first conductivity type along the vertical direction.

DETAILED DESCRIPTION

In the following detailed description, reference is made to the accompanying drawings which form a part hereof and in which are shown by way of illustration of specific embodiments in which the invention may be practiced.

In this regard, directional terminology, such as “top”, “bottom”, “below”, “front”, “behind”, “back”, “leading”, “trailing”, etc., may be used with reference to the orientation of the figures being described. Because parts of embodiments can be positioned in a number of different orientations, the directional terminology is used for purposes of illustration and is in no way limiting. It is to be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present invention. The following detailed description, therefore, is not to be taken in a limiting sense, and the scope of the present invention is defined by the appended claims.

Reference will now be made in detail to various embodiments, one or more examples of which are illustrated in the figures. Each example is provided by way of explanation, and is not meant as a limitation of the invention. For example, features illustrated or described as part of one embodiment can be used on or in conjunction with other embodiments to yield yet a further embodiment. It is intended that the present invention includes such modifications and variations. The examples are described using specific language which should not be construed as limiting the scope of the appended claims. The drawings are not scaled and are for illustrative purposes only. For clarity, the same elements or manufacturing steps have been designated by the same references in the different drawings if not stated otherwise.

The term “horizontal” as used in this specification intends to describe an orientation substantially parallel to a horizontal surface of a semiconductor substrate or of a semiconductor region. This can be for instance the surface of a wafer or a die.

The term “vertical” as used in this specification intends to describe an orientation which is substantially arranged perpendicular to the horizontal surface, i.e., parallel to the normal direction of the surface of the semiconductor substrate or semiconductor region.

In this specification, n-doped may be referred to as “first conductivity type” while p-doped may be referred to as “second conductivity type”. Alternatively, opposite doping relations can be employed so that the first conductivity type can be p-doped and the second conductivity type can be n-doped. For example, an n-doped semiconductor region can be produced by inserting donors into a semiconductor region. Further, a p-doped semiconductor region can be produced by inserting acceptors into a semiconductor region.

In the context of the present specification, the terms “in ohmic contact”, “in electric contact”, “in ohmic connection”, and “electrically connected” intend to describe that there is a low ohmic electric connection or low ohmic current path between two regions, sections, portions or parts of a semiconductor arrangement or between different terminals of one or more devices or between a terminal or a metallization or an electrode and a portion or part of a semiconductor arrangement. Further, in the context of the present specification, the term “in contact” intends to describe that there is a direct physical connection between two elements of the respective semiconductor arrangement; e.g., a transition between two elements being in contact with each other may not include a further intermediate element or the like.

Specific embodiments described in this specification pertain to, without being limited thereto, monolithically integrated semiconductor arrangements having an IGBT, MOSFET or diode structure.

The term “power semiconductor device” as used in this specification intends to describe a semiconductor device on a single chip with high voltage blocking and/or high current-carrying capabilities. Such semiconductor device may be part of a semiconductor arrangement. In other words, said power semiconductor devices are intended for high current, such as in the Ampere range, e.g., up to several hundred Ampere, and/or high voltages, such as above 40 V, 100 V and above.

Further, within this specification, the term “dopant concentration” may refer to an integral dopant concentration or, respectively, to a mean dopant concentration or to a sheet charge carrier concentration of a specific semiconductor region or semiconductor layer. Thus, e.g., a statement saying that a dopant concentration of a specific semiconductor region is higher or lower as compared to a dopant concentration of another semiconductor region may indicate that the respective mean dopant concentrations of said semiconductor regions differ from each other.

Further, within this specification, the term “body region” is not necessarily limited to a body region in a transistor cell, such as a body region of a MOSFET or of an IGBT, but can also refer to an emitter region of a diode, which may form a pn-junction with a drift region of said diode. For example, the term “body region” as used in the following, may designate a p-doped (anode) emitter region of a pin-diode.

FIG. 1schematically illustrates a method2of producing a semiconductor device1according to one or more embodiments. The method2comprises, in a first step20, providing a semiconductor substrate4having a surface40. For example, the semiconductor substrate4is a semiconductor wafer. The semiconductor wafer may be produced, for instance, by a Czochralski method, a Magnetic Czochralski method, or a zone melting method. For instance, such a semiconductor wafer exhibits a diameter of 200 mm, 300 mm, or 450 mm.

As a further step21, the method2may comprise epitaxially growing, along a vertical direction Z perpendicular to the surface40, a back side emitter layer125on top of the surface40. For example, epitaxially growing the back side emitter layer125may comprise a chemical vapor deposition (CVD) process. The epitaxially grown back side emitter layer125has dopants of a first conductivity type or dopants of a second conductivity type complementary to the first conductivity type.

In some embodiments, the back side emitter layer125may further comprise one or more island regions that may exhibit dopants of a type that is complementary to the type of the dopants being present in the remaining section of the back side emitter layer125, which will be explained in more detail with regards toFIG. 1EandFIG. 4B.

The back side emitter layer125may comprise a back side emitter region of a diode or a drain region of a MOSFET to be produced by the method2, which can be, for example n+-doped. In further embodiments, the back side emitter layer125comprises a back side emitter region of an IGBT to be produced by the method2, wherein the back side emitter layer125can be, for example, p+-doped.

A dopant concentration of the back side emitter layer125is, for instance, in the range from 1017cm−3to 1×1020cm−3. Doping of the back side emitter layer125may be achieved, for example, by applying, during the epitaxial growth21of the back side emitter layer125, doping gases, such as phosphine, hydrogen selenide or arsine for n-type doping or diborane for p-type doping within a carrier gas such as hydrogen.

A thickness of the epitaxially grown back side emitter layer125is, for example, in the range from 0.3 μm to 20 μm, from 0.5 μm to 5 μm, or from 1 μm to 3 μm.

For example, the substrate4comprises Magnetic Czochralski silicon. In an embodiment, before epitaxially growing (step21) the back side emitter layer125on top of the substrate4, the surface40is pre-treated with at least one of a wet oxidation process and an application of phosphoryl chloride (commonly called phosphorus oxychloride). A resulting oxide layer on the surface40may be removed afterwards, e.g., by a process known in the art. In this way, a reduction of the number of oxygen precipitations and/or crystal originated particles, which may influence the diffusion of dopants within the epitaxially grown back side emitter layer125, may be achieved.

In another embodiment, the epitaxial growth21of the back side emitter layer125is followed by an implantation of dopants in the back side emitter layer125. For example, the implanted dopants in the back side emitter layer125are of the conductivity type of the dopants being present within the epitaxially grown emitter layer125.

In a variant, the method2further comprises, before epitaxially growing (steps22,23) a subsequent semiconductor layer123,126on top of the back side emitter layer125, implanting dopants in the back side emitter layer125, wherein a lateral variation of a dopant concentration of the back side emitter layer125is realized by at least one masked implantation process.

For example, as a result of said at least one masked implantation, a dopant concentration in the back side emitter layer125may vary within a horizontal plane parallel to the surface40between a substantially central position within the semiconductor device1to be produced and an outer position close to an edge of the semiconductor device1by a factor of at least 1.5 or 2 or even more than 5.

Such lateral variation of the dopant concentration due to the implanted dopants within the back side emitter layer125can be configured in different manners:

For example, the dopant concentration of the back side emitter layer125may gradually or discontinuously increase within the horizontal plane in the back side emitter layer125in a direction from the substantially central position within the semiconductor device1to be produced to the outer position close to the edge of the semiconductor device1. For example, within the horizontal plane in the back side emitter layer125, a dopant concentration at the outer position close to the edge of the semiconductor device1to be produced may be higher than a dopant concentration at the substantially central position within the semiconductor device1to be produced by a factor of at least 1.5 or 2 or even more than 5.

Alternatively, a dopant concentration of the back side emitter layer125may gradually or discontinuously decrease within the horizontal plane in the back side emitter layer125in a direction from the substantially central position within the semiconductor device1to be produced to the outer position close to the edge of the semiconductor device1to be produced. For example, within the horizontal plane in the back side emitter layer125, a dopant concentration at the outer position close to the edge of the semiconductor device1to be produced may be lower than a dopant concentration at the substantially central position within the semiconductor device1to be produced by a factor of at least 1.5 or 2 or even more than 5. For example, such a reduction of the back side emitter125dopant concentration may be provided in a region below a blocking junction termination to be realized on the front side121of the chip12and additionally or alternatively in a region within a transition range between this area below the blocking junction termination and an active area of the semiconductor device1to be produced. For example, a lateral extent of such a region of reduced dopant concentration within the backside emitter layer125corresponds to more than 20% of a diffusion length L of minority carriers or even more than 50%, or even more than 100%, or even more than 200% of said diffusion length L.

For example, a lateral variation (i.e., a variation in a direction in parallel to said surface40) of a dopant concentration inside the back side emitter layer125is achieved via a first dopant implantation followed by a second dopant implantation, wherein, during the first dopant implantation, portions of the back side emitter layer125can be covered by a mask (not illustrated inFIG. 1A).

For example, the semiconductor device1to be produced is an IGBT, wherein the back side emitter region125can be p-doped and may exhibit a reduced dopant concentration underneath an edge termination as compared to a dopant concentration of an active area, so as to improve a dynamic robustness of the IGBT. Alternatively or additionally, small highly p-doped regions may be implanted in the back side emitter layer125in the active area of the IGBT by means of such a masked implantation. The small highly p-doped regions may improve the short circuit robustness of the IGBT. Furthermore, larger highly p-doped areas may be implanted in the back side emitter layer125in the active area of the IGBT, e.g., in order to improve the softness of the turn-off process.

As a further step23, the method2according to the embodiment illustrated inFIG. 1may comprise epitaxially growing, along the vertical direction Z, a drift layer123having dopants of the first conductivity type on top of the back side emitter layer125, wherein a dopant concentration of the back side emitter layer125is higher than a dopant concentration of the drift layer123.

For example, the drift layer123comprises a drift zone, such as an n−-doped drift zone of a pin-diode, an IGBT or a MOSFET to be produced by the method2.

For example, the drift zone123is configured to conduct a load current during a conducting state (on-state) of the semiconductor device1to be produced. Such load current may flow, e.g., in a direction substantially in parallel to the vertical direction Z.

According to an embodiment, a dopant concentration of the back side emitter layer125may be higher than a dopant concentration of the drift layer123by a factor of at least 100. This factor can be even greater than 100, for example greater than 500, or greater than 1000. For example, epitaxially growing (step23) the drift layer123may comprise a CVD process.

Epitaxially growing (step23) the drift layer123may include creating a dopant concentration profile P of dopants of the first conductivity type along the vertical direction Z, wherein the dopant concentration profile P exhibits a variation of a concentration of dopants of the first conductivity type along the vertical direction Z. An example of such dopant concentration profile P is schematically illustrated inFIG. 2, to which it is also referred in the following.

For example, the dopant concentration profile P in the drift layer123exhibits a variation of the dopant concentration by a factor of at least 2. This factor can be even greater than 2, for example greater than 5, or greater than 10. In an embodiment, the dopant concentration profile P in the drift layer123exhibits a maximum400. As depicted inFIG. 2, the maximum400of the dopant concentration profile P can be located inside the drift layer123. The concentration profile P can comprise a gradually increasing section and a gradually decreasing section, wherein the maximum400can be located at a transition from the gradually increasing section to the gradually decreasing section. As illustrated byFIG. 2, the dopant concentration profile P can comprise a section resembling a profile of a turtle shell. In a further embodiment, the dopant concentration profile P can include a substantially Gaussian-shaped section exhibiting a maximum400.

In an embodiment, creating the dopant concentration profile P by epitaxially growing (step23) the drift layer123comprises a time dependent admixture of dopants during the epitaxial process. For example, at least one of phosphorus, arsenic, and antimony dopants may be admixed from the gas phase in a time-dependent manner during the epitaxial process.

As a further step24, the method2in accordance with the embodiment illustrated inFIG. 1Acomprises creating, on top of the drift layer123, a body region124having dopants of the second conductivity type. For instance, the body region124comprises a p-doped anode region124of a pin-diode or a p-body region124of an n-channel IGBT or of an n-channel MOSFET to be produced by the method2. A transition between the body region124and the drift layer123may form a pn-junction Zpn (see alsoFIG. 2). For example, in the semiconductor device1to be produced, the pn-junction Zpn is configured to block a voltage with a space charge region extending into the body region124and the drift zone123. Said voltage may amount to, e.g., at least 40 V, to at least 100 V, to least 1200 V or may even be above 1200 V.

Creating (step24) the body region124may comprise, for example, epitaxially growing the body region124on top of the drift layer123along the vertical direction Z. For instance, the semiconductor device1to be produced may comprise a vertical edge termination (not illustrated), which may not require a horizontal structuring of the body region124, thus allowing for producing the body region124by epitaxial growth. For example, the body region124can exhibit an acceptor concentration of at least 1016cm−3, e.g., for forming a low ohmic front side contact and, at the same time, for ensuring an appropriate threshold voltage of an IGBT or for using the body region124as an emitter of a diode with an appropriate doping level. For example, a dopant concentration (e.g., acceptor concentration) of the body region124is in a range from 5×1016cm−3to 2×1017cm−3.

Alternatively, as illustrated inFIG. 1C, creating (step24) the body region124can comprise at least one of a masked implantation and a diffusion of dopants of the second conductivity type into the drift layer123. In this manner, a body region124in the form of a well may be formed inside the drift layer123. For example, the body region124may comprise a p-well region124of a pin-diode, of an n-channel IGBT, or of an n-channel MOSFET to be produced by method2.

In an embodiment, a maximum of the dopant concentration profile P in the drift region123is higher than a concentration of dopants of the first conductivity type at the pn-junction Zpn by a factor of at least 2.

In a further embodiment, a maximum of the dopant concentration profile P is located closer to a central position Z1between the pn-junction Zpn and a transition Zt between the back side emitter layer125and the drift layer123than to the pn-junction Zpn and to said transition Zt. For example, the maximum of the dopant concentration profile P may be located in the vicinity of the center of total extension of the drift layer123along the vertical direction Z. In other words, both the distance between Z1and Zpn and the distance between Z1and Zt can each be greater than a distance between Z1and said center of the drift layer.

In yet a further embodiment, a full width at half maximum (FWHM) of the dopant concentration profile P in the drift region123amounts to at least 20% of a distance Zt-Zpn between the pn-junction Zpn and the transition Zt between the back side emitter layer125and the drift layer123.

In an embodiment, the method2may further comprise a step25of removing the semiconductor substrate4, e.g., by using a process known in the art. Thereby, a back side122of the semiconductor body12can be exposed at least partially. This is illustrated inFIG. 1A. For example, the semiconductor substrate4may be removed using at least one of a grinding process, a polishing process, and a chemical-mechanical planarization process. In a variant, removing (step25) the semiconductor substrate4may include removing a portion of the back side emitter layer125.

In a further embodiment, the method2comprises, subsequently to removing the semiconductor substrate4, implanting (step26) dopants in the back side emitter layer125(see dashed arrows inFIG. 1A). For example, the implanted dopants are of the conductivity type of the dopants being present within the epitaxially grown back side emitter layer125. For example, the implantation26of dopants is carried out so as to allow for an improved ohmic contact at a transition between the back side emitter layer125and a back side metallization (not illustrated) of the semiconductor device1to be produced.

In another embodiment, the method2comprises creating (step26) a damage region125-3within the back side emitter region125, wherein a conductivity of the damage region125-3is lower than a conductivity of the section of the back side emitter region125outside the damage region125-3. In other words, the created damage region125-3can be configured for reducing a lifetime and/or a mobility of charge carriers in the damage region125-3as compared to a lifetime and/or a mobility of charge carriers in the section of the back side emitter region125outside the damage region125-3. Thereby, an emitter efficiency of the back side emitter region125can be reduced. Creating the damage region125-3may comprise an implantation process, e.g., from the back side122. For example, at least one of argon, phosphorus, antimony, and arsenic is implanted in the back side emitter region125in order to create the damage region125-3.

Thus, the method2of producing a semiconductor device1may further comprise, subsequently to removing (step25) the semiconductor substrate4, at least one of: implanting (step26) dopants in the back side emitter layer125from the back side122and creating (step26) a damage region125-3within the back side emitter region125, wherein a conductivity of the damage region125-3is lower than a conductivity of the section of the back side emitter region125outside the damage region125-3.

In a variant of the method2of producing a semiconductor device, as illustrated inFIG. 1B, the method2further comprises epitaxially growing (step22), along the vertical direction Z, a buffer layer126on top of the back side emitter layer125before epitaxially growing23the drift layer123on top of the buffer layer126. The buffer layer126may have dopants of the first conductivity type, and a dopant concentration of the buffer layer126is higher than a dopant concentration of the drift layer123. In an embodiment, a maximal dopant concentration of the buffer layer126is higher than a maximal dopant concentration of the drift layer123by a factor of at least 2. Except for the buffer layer126, the embodiment of the method2in accordance withFIG. 1Bmay be carried out in manner substantially identical to the manner of carrying out the embodiment of the method2exemplarily illustrated inFIG. 1A.

Further, similar to the embodiment already explained with respect toFIG. 1Aand toFIG. 2, a maximum400of the dopant concentration profile P may be located closer to said central position Z1between the pn-junction Zpn and a transition Zb between the buffer layer126and the drift layer123than to the pn-junction Zpn and to said transition Zb between the back side buffer layer126and the drift layer123, as illustrated inFIG. 2. For example, the maximum400of the dopant concentration profile P may be located in the vicinity of the center of total extension the drift layer123along the vertical direction Z. In other words, both the distance between Z1and Zpn and the distance between Z1and Zb can each be greater than a distance between Z1and said center of the drift layer.

In yet a further embodiment, a full width at half maximum (FWHM) of the dopant concentration profile P in the drift region123amounts to at least 20% of a distance Zb-Zpn between the pn-junction Zpn and a transition Zb between the buffer layer126and the drift layer123, seeFIG. 2.

In accordance with the embodiment of the method2schematically illustrated inFIG. 1B, each of a dopant concentration of the back side emitter layer125and a dopant concentration of the buffer layer126may be higher than a dopant concentration of the drift layer123. Further, epitaxially growing (step22) the buffer layer126may include creating a dopant concentration profile Q of dopants of the first conductivity type along the vertical direction Z, the dopant concentration profile Q exhibiting a variation of a concentration of dopants of the first conductivity type along the vertical direction Z.

The buffer layer126may be configured to avoid a punch-through of an electric field to the back side emitter region123in a blocking state of the semiconductor device1to be produced.

In an embodiment, creating the dopant concentration profile Q by epitaxially growing (step22) the buffer layer126may comprise a time dependent admixture of dopants during the epitaxial process, such as, for example, at least one of phosphorus, arsenic and antimony dopants.

For example, in accordance with the embodiment of the method2explained above with respect toFIG. 1B, at least the process steps21,22,23,24of epitaxially growing the back side emitter layer125, the buffer layer126, the drift layer123, and the body region124may be carried out sequentially within a single deposition process. Variations in dopant types and or dopant concentrations between the respective layers123,124,125,126can be realized, for instance, by the time dependent admixture of dopants during the epitaxial growth of said layers123,124,125,126.

In a variant of the method2, at least the process steps21,22,23of epitaxially growing the back side emitter layer125, the buffer layer126and the drift layer123may be carried out sequentially within a single deposition process.

In a further variant of the method2, at least the process steps22,23of epitaxially growing the buffer layer126and the drift layer123may be carried out sequentially within a single deposition process.

In an embodiment, the dopant concentration profile Q in the buffer layer126may exhibit a maximum410, as illustrated inFIG. 2, which exemplarily and schematically illustrates a section of dopant concentration profile in a vertical cross-section of a semiconductor device1produced with a method as depicted inFIG. 1B. Said maximum410may be located, e.g., in vicinity of a center of the total extension of the buffer layer126along said vertical direction Z. For example, the dopant concentration profile Q in the buffer layer126may exhibit a variation of the dopant concentration by a factor of at least 2.

As depicted inFIG. 3A, which also exemplarily and schematically illustrates a section of dopant concentration profile in a vertical cross-section of a semiconductor device1, the dopant concentration profile Q in the buffer layer126may exhibit a plurality of local maxima411,412,413. In the exemplary embodiment depicted inFIG. 3A, the plurality of local maxima comprises three local maxima411,412,413. In other embodiments, the number of local maxima411,412,413can be two or four, or even five or more than five. For example, the local maxima411,412,413may form field stop peaks. Thus, the dopant concentration profile Q may exhibit a course similar to concentration profiles that can be produced by implantation. The local maxima411,412and413can each be part of substantially Gaussian-shaped sections of the dopant concentration profile Q. As further depicted inFIG. 3A, the local maxima411,412and413can differ in value (height). A distance d between two neighboring of said local maxima411to413is, for example, in the range from 2 μm to 20 μm or in the range from 3 μm to 10 μm.

For example, the dopant concentration profile Q in the buffer layer126can exhibit a local minimum421being located between the neighboring local maxima411and412and a further local minimum422being located between the neighboring local maxima412and413, wherein a dopant concentration at the local minimum421is lower than the dopant concentration of the neighboring local maxima by a factor of at least 2. This factor can be even greater than 2, for example greater than 5, or greater than 10.

According to another embodiment, the dopant concentration profile Q in the buffer layer126exhibits at least one of a step-like increase and a step-like decrease of the dopant concentration along the vertical direction Z. For example, in accordance with the embodiment depicted inFIG. 3C, the dopant concentration profile Q comprises a stair-case section including at least three step-like increases and at least one step-like decrease along the vertical direction Z.

In the context of the present specification, the terms “step-like decrease” or, respectively “step-like increase” may refer to a course of a dopant concentration along the vertical direction Z, wherein, at a section of said course, the dopant concentration changes by a factor of at least 2 within a distance of 1 μm, and remains substantially constant within a subsequent distance of at least 2 μm. Said factor can be even greater than 2, for example greater than 5, or greater than 10.

According to yet a further embodiment that is schematically illustrated inFIG. 3B, the dopant concentration profile Q in the buffer layer126may comprise at least one box-shaped section B, wherein a first edge E1of the at least one box-shaped section B is formed by a step-like increase of the dopant concentration along the vertical direction Z, and wherein a second edge E2of the box-shaped section is formed by a step-like decrease of the dopant concentration along the vertical direction Z.

In an embodiment, the dopant concentration varies along the vertical direction Z by a factor of at least 2 over a distance of 1 μm at the step-like increase and/or at the step-like decrease of the dopant concentration profile Q. This factor can be even greater than 2, for example greater than 5, or greater than 10.

In a variant, the dopant concentration profile Q in the buffer layer126comprises at least one box-shaped section B. For instance, in the exemplary embodiment depicted inFIG. 3B, the dopant concentration profile Q in the buffer layer126comprises three box-shaped sections B. Within the dopant concentration profile Q in the buffer region126, a plurality of box-shaped sections B can be arranged next to each other in many different ways. Thus, it is possible to approximate a variety of continuous dopant concentration profiles.

In accordance with an embodiment of the method2, the edges E1, E2of the box-shaped section B and/or the step-like increases or decreases within the dopant concentration profile Q may be softened by diffusion of dopants during the epitaxial growth22of the buffer layer126and/or during a subsequent high-temperature process step. In other words, the contours of a dopant concentration profile Q may be washed out to a certain extent by diffusion of dopants. For example, a dopant concentration profile Q exhibiting a plurality of substantially Gaussian-shaped peaks as illustrated inFIG. 3Amay be the result of such a softening of the contours of a dopant concentration profile Q as depicted inFIG. 3Bby diffusion of dopants.

In accordance with another embodiment that is schematically illustrated inFIG. 3D, the dopant concentration profile Q in the buffer layer126may comprise at least one substantially linear section L exhibiting one of a substantially linear increase and a substantially linear decrease of the dopant concentration along the vertical direction Z over a distance of at least 50% of the total extension of the buffer layer126along the vertical direction (Z), e.g., for at least 10 μm. For example, in the embodiment depicted inFIG. 3D, the dopant concentration profile Q in the buffer layer126exhibits a substantially linear section L exhibiting a linear decrease of the dopant concentration along at least 95% of the total extension of the buffer layer126along the vertical direction Z. The linear section L can start at a sharply increasing edge S located at the transition Zb between the buffer layer126, wherein the sections S and L may form two sides of a virtual triangle.

In another embodiment, the epitaxial growth22of the buffer layer126is followed by an implantation of dopants in the buffer layer126. For example, the implanted dopants in the buffer layer126are of the first conductivity type.

In a variant, the method2further comprises, before epitaxially growing (step23) the drift layer123on top of the buffer layer126, implanting dopants in the buffer layer126, wherein a lateral variation of a dopant concentration of the buffer layer126is realized by at least one masked implantation process.

For example, as a result of said at least one masked implantation, a dopant concentration in the buffer layer126may vary within a horizontal plane parallel to the surface40between a substantially central position within the semiconductor device1to be produced and an outer position close to an edge of the semiconductor device1to be produced by a factor of at least 2, at least 5, or even more than 5.

Such lateral variation of the dopant concentration due to the implanted dopants within the buffer layer126can be configured in different manners:

For example, the dopant concentration of the buffer layer126may gradually increase within the horizontal plane in the buffer layer126in a direction from the substantially central position within the semiconductor device1to be produced to the outer position close to the edge of the semiconductor device1. For example, within the horizontal plane in the buffer layer126, the dopant concentration at the outer position close to the edge of the semiconductor device1to be produced may be higher than the dopant concentration at the substantially central position within the semiconductor device1to be produced by a factor of at least 2, 5, or even more than 5. For example, such an enhancement of the field stop126dopant concentration may be provided in a region below a blocking junction termination to be realized on the front side121of the semiconductor body12and additionally or alternatively in a region within a transition range between this area below the blocking junction termination and an active area of the semiconductor device1to be produced. For example, a lateral extent of such a region of enhanced dopant concentration within the buffer layer126corresponds to more than 20% of a diffusion length L of minority carriers or even more than 50%, or even more than 100%, or even more than 200% of said diffusion length L.

Alternatively, a dopant concentration of the buffer layer126may gradually decrease within the horizontal plane in the buffer layer126in a direction from the substantially central position within the semiconductor device1to be produced to the outer position close to the edge of the semiconductor device1to be produced. For example, within the horizontal plane in the buffer layer126, the dopant concentration at the outer position close to an edge of the semiconductor device1to be produced may be lower than the dopant concentration at the substantially central position within the semiconductor device1to be produced by a factor of at least 2 or 5, or even more than 5.

A further variant of the methods2of producing a semiconductor device1described above is schematically and exemplary illustrated inFIG. 1D. The method2of producing a semiconductor device1, may further comprise at least one of: epitaxially growing (step21-1) a substantially undoped or lowly doped cap layer127on top of at least one of said epitaxially grown (steps21,22,23,24) semiconductor layers123,124,125,126before epitaxially growing (steps22,23,24) a subsequent semiconductor layer123,124,126on top of the cap layer127; and interrupting the epitaxial growth (steps21,22,23,24) of at least one of said semiconductor layers123,124,125,126at a point and epitaxially growing (step21-1) such a substantially undoped or lowly doped cap layer127on top of a portion of said semiconductor layer123,124,125,126that has been grown up to that point before continuing the epitaxial growth (steps21,22,23,24) of said semiconductor layers123,124,125,126.

For example, as depicted inFIG. 1D, said variant may comprise, after epitaxially growing (step21) the back side emitter layer125, epitaxially growing (step21-1) such a substantially undoped or lowly doped cap layer127on top of the back side emitter layer125. Subsequently, the drift layer123or the buffer layer126can be grown epitaxially (step23) on top of the cap layer127. The cap layer127can, for instance, comprise one of silicon and silicon-germanium.

For example, such a substantially undoped or lowly doped cap layer127may be provided by epitaxial growth after one or more interruptions of the epitaxial growth (steps21,22,23,24) of said semiconductor layers123,124,125,126.

In an embodiment, the cap layer127comprises amorphous silicon, which can be, e.g., recrystallized in a subsequent tempering step at relatively low temperatures in the range between 400° C. and 700° C. or between 450° C. and 600° C.

The cap layer127may be configured to hinder dopants from the relatively highly doped back side emitter layer125to enter the drift layer123or, respectively, the buffer layer126.

In accordance with yet a further embodiment of the method2that is schematically and exemplarily illustrated inFIG. 1E, epitaxially growing (step21) of the back side emitter layer125having dopants of either the first or the second conductivity type is interrupted (step21-2) at a point. A mask150is then created (step21-3) on top of a portion of the back side emitter layer125that has been grown up to that point. Creating the mask150may be achieved by lithographic methods known in the art. Said embodiment of the method2may further comprise creating (step21-4), via an implantation (illustrated by dashed arrows inFIG. 1E) of dopants of a conductivity type complementary to the conductivity type of the dopants being present within the epitaxially grown back side emitter layer125, a plurality of island regions125-1within the back side emitter layer125, wherein a position, shape and extension of the island regions125-1in a horizontal plane may be set by the mask150. For example, in a horizontal cross-section of the back side emitter layer125, the island regions125-1may exhibit a square shape, a rectangular shape, or a strip shape.

In an embodiment, epitaxially growing (step21) the back side emitter layer125may thus comprise: interrupting (step21-2) the epitaxial growth of the back side emitter layer125at a point; creating (step21-3) a mask150on top of a portion of the back side emitter layer125that has been grown up to that point; and creating (step21-4), via an implantation of dopants of a type complementary to the conductivity type of the dopants being present within the epitaxially grown emitter layer125, a plurality of island regions125-1within the back side emitter layer125.

Subsequently to the implantation (step21-4), the mask150may be removed (step21-5), and the epitaxial growth (step21) of the back side emitter layer125may be continued (step21-6).

For example, one of boron, aluminum, and indium can be used as dopant material for the implantation21-4of p-doped island regions125-1, e.g., in an n-doped back side emitter layer125of a diode cell.

In an embodiment, the island regions125-1extend through the whole back side emitter layer125in the vertical direction Z, thereby being in contact with the back side122of the semiconductor body12. For example, for producing a reverse conducting IGBT, donor-type dopant atoms such as, e.g., phosphorus, arsenic or antimony, can be implanted. The resulting n-doped island regions125-1may extend through the whole p-doped back side emitter layer125in the vertical direction Z. Thus, the n-doped island regions125-1may be in contact with the back side122(and possibly a backside metallization to be arranged thereon), thereby functioning as n-short areas of the reverse conducting IGBT to be produced.

As explained above, the back side emitter layer125may be, for example, an n-doped region. In this case, the island regions125-1are p-doped. For example, the dopant concentration of the island regions125-1is higher than the dopant concentration of the back side emitter layer125outside the island regions125-1by a factor of at least 2. In a variant, the dopant concentration of the island regions125-1is higher than the dopant concentration of the back side emitter layer125outside the island regions125-1by a factor of at least 5 or even 10.

For example, the island regions125-1are configured to inject holes during switching-off of the semiconductor device. For example, the island regions125-1may thereby counteract against a too early or too sudden break-down of a reverse-recovery current.

In a further embodiment that is schematically and exemplarily illustrated inFIG. 1F, epitaxially growing (step22) of the buffer layer126is interrupted (step22-2) at a point, and a plurality of island regions126-1inside the buffer layer126are created (step22-4) via a masked implantation according to process steps22-2to22-6that are analogous to the steps21-2to21-6described above with regards toFIG. 1E.

Thus, in said further embodiment of the method2, epitaxially growing (step22) of the buffer layer126can be interrupted (step22-2) at a point. A mask151can then be created (step22-3) on top of a portion of the buffer layer126that has been grown up to that point. Creating the mask151may be achieved by lithographic methods known in the art. Said embodiment of the method2may further comprise creating (step22-4), via an implantation (illustrated by dashed arrows inFIG. 1F) of dopants of a conductivity type complementary to the conductivity type of the dopants being present within the epitaxially grown buffer layer126, a plurality of island regions126-1within the buffer layer126, wherein a position, shape and extension of the island regions126-1in a horizontal plane may be set by the mask151. For example, in a horizontal cross-section of the buffer layer126, the island regions126-1may exhibit a square shape, a rectangular shape, or a strip shape.

Subsequently to the implantation (step22-4), the mask151may be removed (step22-5), and the epitaxial growth (step22) of the buffer layer126may be continued (step22-6).

The island regions126-1in the buffer layer126produced in this manner may comprise dopants of the second conductivity type. For example, the island regions126-1inside the buffer layer126may be p-doped island regions126-1floating within an n-doped buffer layer126of a diode or an IGBT to be produced.

For example, the dopant concentration of the island regions126-1within the buffer layer126is higher than the dopant concentration of the buffer layer126outside the island regions126-1by a factor of at least 2. In a variant, the dopant concentration of the island regions126-1within the buffer layer126is higher than the dopant concentration of the buffer layer126outside the island regions126-1by a factor of at least 5 or even 10.

For example, the island regions126-1inside the buffer layer126are configured to inject holes during switching-off of the semiconductor device. For example, the island regions126-1inside the buffer layer126may thereby counteract against a too early or too sudden break-down of a reverse-recovery current.

FIG. 1Gillustrates yet further optional steps of the methods2of producing a semiconductor device1explained above. In this embodiment, the method2further comprises interrupting (step23-1) epitaxially growing the drift layer123at a point, implanting (step23-2) dopants of the first conductivity type in the portion of the drift layer123that has been grown epitaxially up to that point, and, subsequently, continuing (step23-3) the epitaxial growing23of the drift layer123.

For example, epitaxially growing (step23) of the drift layer123is interrupted for the dopant implantation23-1after about half of a final (total) thickness of the drift layer123has been reached. Implanting dopants may comprise creating, by implantation, a dopant concentration profile having one or more features described above with regard to creating a dopant concentration profile during the epitaxial growth23of the drift layer (see, for example,FIG. 2). For example, a Gaussian-shaped dopant concentration profile may be created in the drift region123by implantation. Creating a Gaussian-shaped profile may further comprise a diffusion of the implanted dopants during a subsequent tempering step. For instance, one of selenium, phosphorus, arsenic, and antimony may be used as dopant material for the implantation23-2.

Alternatively or additionally to creating a dopant concentration profile of dopants of the first conductivity type within the drift layer123, during the implantation step23-2, dopants of the second conductivity type may be implanted, e.g., to realize compensation structures according to the superjunction principle. Such an implantation step23-2may be carried out as a masked implantation or as an unmasked implantation.

The optional method steps explained above with respect toFIG. 1AtoFIG. 1Gmay be combined for forming further embodiments of the method2, as long as the respective method steps are not described as being alternative each other.

FIG. 4AandFIG. 4Beach schematically illustrate a section of a vertical cross-section of a semiconductor device1according to one or more embodiments. Such a semiconductor device1may be produced by carrying out an embodiment of the methods2explained above.

As illustrated inFIG. 4Aand inFIG. 4B, the semiconductor device1includes a semiconductor body12having a front side121and a back side122, wherein the semiconductor body12extends in a vertical direction Z pointing from the back side122to the front side121.

For example, the semiconductor device1is a vertical power semiconductor device1and configured to conduct a load current and/or block a voltage between a first and a second load contact of the semiconductor device1, wherein the first load contact may be electrically connected to the front side121of the semiconductor body12and the second load contact is electrically connected to the back side122of the semiconductor body12.

In an embodiment, the semiconductor device1is one of a diode, an IGBT, and a MOSFET.

The semiconductor body12may be grown epitaxially according to the principles described above with respect toFIGS. 1A to 1G. The semiconductor body12may thus comprise an epitaxially grown drift layer123having dopants of a first conductivity type. For example, the drift layer123comprises a drift zone, such as an n31-doped drift zone of a pin-diode, an IGBT or a MOSFET, configured to conduct a current between the front side121and the back side122of the semiconductor body12. The drift layer123may be grown epitaxially according to the principles described above with respect toFIG. 2. Thus, the above description of examples of the dopant concentration profile P in the drift region123(see alsoFIG. 2) applies likewise to the embodiments of the semiconductor device1illustrated inFIGS. 4A and 4B. For example, in the drift layer123, a dopant concentration profile P along the vertical direction Z can exhibit a variation of the dopant concentration by a factor of at least 2. This factor can be even greater than 2, for example greater than 5, or greater than 10. In another embodiment, a maximum400of the dopant concentration profile P in the drift layer123is higher than a concentration of dopants of the first conductivity type at the pn-junction Zpn by a factor of at least 2.

A body region124having dopants of a second conductivity type complementary to the first conductivity type124can be arranged either within or on top of the drift layer123. For instance, the body region124comprises a p-doped anode region of a pin-diode or a p-body region of an n-channel IGBT or of an n-channel MOSFET. A transition between the body region124and the drift layer123may form a pn-junction Zpn. For example, the pn-junction Zpn is configured to block a voltage between the external load contacts of the semiconductor device12with a space charge region extending into the body region124and the drift zone123.

In an embodiment, the body region124comprises an epitaxially grown semiconductor layer. For example, the body region124has been produced by epitaxial growth, as explained above with respect toFIG. 1A. For instance, the semiconductor device1may comprise a vertical edge termination, which may not require a horizontal structuring of the body region124, thus allowing for producing the body region124by epitaxial growth. Alternatively, the body region124may have been produced by an implantation or a diffusion of dopants of the second conductivity type into the drift layer123, as illustrated inFIG. 1C. In this manner, a body region124in the form of a well may be produced inside the drift layer123. For example, the body region124may comprise a p-well region124of a pin-diode, an n-channel IGBT, or an n-channel MOSFET.

The semiconductor body12may further comprise an epitaxially grown back side emitter layer125arranged in between the drift layer123and the back side122. The back side emitter layer125has dopants of the first and/or dopants of the second conductivity type, wherein a dopant concentration of the back side emitter layer125is higher than a dopant concentration of the drift layer123. In an embodiment, a maximal dopant concentration in the buffer layer126is higher than a maximal dopant concentration in the drift layer123by a factor of at least 2. For example, the back side emitter layer has been produced by epitaxial growth21according to the methods2described above.

The back side emitter layer123may comprise a back side emitter region of a diode or a drain region of a MOSFET, which can be, for example n+-doped. In further embodiments, the back side emitter layer123comprises a back side emitter region of an IGBT, wherein the back side emitter layer can be, for example, p+-doped. As stated above, the dopant concentration of the back side emitter layer125may exhibit a lateral variation. For example, in a p-doped back side emitter layer125of an IGBT, a dopant concentration underneath an edge termination structure may be lower than a dopant concentration of an active area of the IGBT. In this way, an improved dynamic robustness of the IGBT may be achieved.

In an embodiment, the semiconductor device1may further comprise an epitaxially grown buffer layer126in contact with the drift layer123, as shown inFIGS. 4A and 4B. The buffer layer126can be arranged in between the drift layer123and the back side emitter layer125and may have dopants of the first conductivity type at a higher dopant concentration than the drift layer123. The buffer layer126can comprise one or more dopant concentration maxima configured to avoid a punch-through of an electric field to the back side emitter region123in a blocking state of the semiconductor device1. For example, a maximal dopant concentration in the buffer layer126is higher than a maximal dopant concentration in the drift layer123by a factor of at least 2.

The buffer layer126may be grown epitaxially according to the principles described above with respect toFIG. 1B. The above description of examples of a dopant concentration profile Q in the buffer region126(as exemplarily illustrated inFIGS. 3A-3D) applies likewise to the embodiments of the semiconductor device1illustrated inFIGS. 4A and 4B. For example, the buffer layer126comprises a dopant concentration profile Q along the vertical direction Z exhibiting a variation of the dopant concentration by a factor of at least 2. In a further embodiment, a vertical dopant concentration profile Q in the buffer layer126comprises at least one of a step-shaped section, a box-shaped section, a substantially linear section, and a plurality of local maxima (seeFIGS. 3A-3D).

FIG. 4Billustrates an embodiment of the semiconductor device1that comprises a plurality of island regions125-1inside the back side emitter layer125. The island regions125-1may comprise dopants of a conductivity type complementary to the conductivity type of the dopants being present within the epitaxially grown emitter layer125. For example, in a horizontal cross-section of the back side emitter layer125, the island regions125-1may exhibit a square shape, a rectangular shape, a strip shape, or another shape. For example, the semiconductor device1is a pin-diode, and the plurality of p-doped island regions125-1inside the back side emitter layer125are arranged and configured to inject holes during switching-off of the diode, thereby counteracting a too early or too sudden break-down of a reverse-recovery current. The island regions125-1may be produced, e.g., according to steps21-2to21-6, as explained above with respect toFIG. 1E. In a variant, the island regions125-1may extend through the whole back side emitter layer125in the vertical direction Z, thereby being in contact with the back side122and the buffer layer126. For example, in a reverse conducting IGBT, the n-doped island regions125-1may be in contact with the buffer layer126and with a backside metallization arranged on the back side122, thereby functioning as n-short areas of the reverse conducting IGBT1.

Alternatively or additionally, such island regions may be implemented in the buffer layer126, as also shown inFIG. 4B. For example, the island regions may be p-doped island regions126-1floating within an n-doped buffer layer126of a diode or of an IGBT. The island regions126-1in the buffer layer126may, e.g., comprise dopants of the first conductivity type. For example, in a horizontal cross-section of the buffer layer126, the island regions126-1may exhibit a square shape, a rectangular shape, a strip shape, or another shape. For example, the semiconductor device1is a pin-diode or an IGBT, and the plurality of p-doped island regions126-1inside the buffer layer126are arranged and configured to inject holes during switching-off of the semiconductor device1, thereby counteracting a too early or too sudden break-down of a reverse-recovery current. The island regions126-1may be produced, e.g., according to steps22-2to22-6, as explained above with respect toFIG. 1F.

The embodiments described above include the recognition that a substantially soft switch-off behavior of power semiconductor devices, such as diodes, IGBTs and MOSFETs, may be desirable in some applications. At the same time, requirements with regards to a high ruggedness and low switching-losses may need to be considered, e.g., for hard-switching applications operating at high switching frequencies.

In accordance with one or more embodiments, it is proposed to produce both a back side emitter and a drift layer of such a power semiconductor device by epitaxial growth, wherein a vertical dopant concentration profile inside the drift layer exhibits a defined variation of the dopant concentration. The dopant concentration profile comprises, for example, a maximum close to the center of the drift region, thereby enabling a substantially soft switching behavior of the semiconductor device.

In accordance with one or more embodiments, it is further proposed to epitaxially grow a buffer layer on top of the back side emitter layer before growing the drift layer on top of the buffer layer. Epitaxially growing the buffer layer may include creating a vertical dopant concentration profile that exhibits a defined variation of the dopant concentration. For example, the dopant concentration profile in the buffer layer comprises one of a step-shaped section, a box-shaped section, a substantially linear section, and a plurality of local maxima. In accordance with one or more embodiments, a variety of defined dopant concentration profiles in the buffer layer can be produced in this manner, thereby allowing for optimizing the semiconductor device with respect to, e.g., softness, switching losses, and the voltage blocking capability.

In accordance with one or more embodiments, creating a dopant concentration profile inside the drift layer and/or the buffer layer can be achieved by a time dependent admixture of dopants during the epitaxial growth, yielding a relatively precise and reproducible dopant concentration profile as compared to, for instance, a dopant implantation. Furthermore, by creating appropriate vertical dopant concentration profiles in the drift layer and/or the buffer layer, electric fields both at the front side and at the back side of the semiconductor device may be reduced in operation. As a result, the ruggedness of the semiconductor device may be improved considerably.

Producing several or all functional regions of a semiconductor device by epitaxial growth of respective semiconductor layers can have further advantages in terms of, for example, a reduced total thickness variation of the processed semiconductor body, an increased process flexibility and compatibility (e.g., in the choice of substrate materials and wafer diameters), and reduced processing costs.

Features of further embodiments are defined in the dependent claims. The features of further embodiments and the features of the embodiments described above may be combined with each other for forming additional embodiments, as long as said features are not explicitly described as being alternative to each other.

In the above, embodiments pertaining to methods of producing a semiconductor device and, embodiments pertaining to semiconductor devices were explained. For example, these semiconductor arrangements and semiconductor devices are based on silicon (Si). Accordingly, a monocrystalline semiconductor region or layer, e.g., the semiconductor body12and the semiconductor regions123to127of exemplary embodiments, are typically a monocrystalline Si-region or Si-layer.

It should, however, be understood that the semiconductor body12and the semiconductor regions123to127can be made of any semiconductor material suitable for manufacturing a semiconductor device. Examples of such materials include, without being limited thereto, elementary semiconductor materials such as silicon (Si) or germanium (Ge), group IV compound semiconductor materials such as silicon carbide (SiC) or silicon germanium (SiGe), binary, ternary or quaternary III-V semiconductor materials such as gallium nitride (GaN), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium gallium phosphide (InGaPa), aluminum gallium nitride (AlGaN), aluminum indium nitride (AlInN), indium gallium nitride (InGaN), aluminum gallium indium nitride (AlGaInN) or indium gallium arsenide phosphide (InGaAsP), and binary or ternary II-VI semiconductor materials such as cadmium telluride (CdTe) and mercury cadmium telluride (HgCdTe) to name few. The aforementioned semiconductor materials are also referred to as “homojunction semiconductor materials”. When combining two different semiconductor materials a heterojunction semiconductor material is formed. Examples of heterojunction semiconductor materials include, without being limited thereto, aluminum gallium nitride (AlGaN)-aluminum gallium indium nitride (AlGainN), indium gallium nitride (InGaN)-aluminum gallium indium nitride (AlGaInN), indium gallium nitride (InGaN)-gallium nitride (GaN), aluminum gallium nitride (AlGaN)-gallium nitride (GaN), indium gallium nitride (InGaN)-aluminum gallium nitride (AlGaN), silicon-silicon carbide (SixC1-x) and silicon-SiGe heterojunction semiconductor materials.

For power semiconductor devices applications currently mainly Si, SiC, GaAs and GaN materials are used.