NEURAL NETWORK OPERATION METHOD AND APPARATUS

A neural network operation method and apparatus are disclosed, where the network operation method including receiving data for a neural network operation, determining whether a size of the data is less than or equal to a threshold, generating stacked data by stacking a portion of the data based on the determining, and performing the neural network operation in parallel based on the stacked data.

CROSS-REFERENCE TO RELATED APPLICATIONS

BACKGROUND

The following description relates to a neural network operation method and apparatus.

2. Description of Related Art

A neural processing unit (NPU) requires data alignment. In the operation of a multiplier accumulator (MAC) system that has a limit on depth alignment and has a depth-first operation order using an input feature map, an unaligned input channel may be used

When channel input data is unaligned, a conventional neural network operation method may experience the issue of lowered MAC utilization because unaligned channels generate values that do not contribute to final operation.

Due to the values not contributing to final operation, excessive power may be consumed because the NPU is consuming unnecessary cycles and memory overhead may occur because of a weight and a dummy channel of a feature map.

SUMMARY

In one general aspect, there is provided a neural network operation method including receiving data for a neural network operation, determining whether a size of the data is less than or equal to a threshold, generating stacked data by stacking a portion of the data based on the determining, and performing the neural network operation in parallel based on the stacked data.

The generating of the stacked data may include storing a portion of a first feature map included in the data in a first location of a memory, and generating a stacked feature map by stacking a second feature map included in the data at a location adjacent to the first location.

The generating of the stacked data may include generating the stacked data by stacking one or more of channels included in the first feature map and one or more of channels included in the second feature map in a channel direction.

The generating of the stacked data may include generating a stacked kernel by stacking one or more of kernels included in the data.

The generating of the stacked data may include generating a plurality of tiles by segmenting the data to have a predetermined width or a predetermined height, and generating the stacked data by stacking the plurality of tiles.

The generating of the stacked data may include generating the stacked data, in response to determining that segmenting the data is beneficial.

The generating of the stacked data may include generating the stacked data by inputting the data to a direct memory access (DMA) engine.

The generating of the stacked data may include searching for additional data to perform a second neural network operation that is different from a first neural network operation performed based on the data, determining whether the additional data and the data are stackable, and performing the first neural network operation and the second neural network operation in parallel by stacking the additional data and the data based on a result of determining.

The neural network operation method may include receiving subsequent data of the data, determining whether a size of the subsequent data is less than or equal to a predetermined size and whether the subsequent data is stackable, and performing the neural network operation by stacking a portion of the subsequent data based on a result of determining and a dependency between the data and the subsequent data.

In another general aspect, there is provided a neural network operation apparatus including a receiver configured to receive data for a neural network operation, and a processor configured to determine whether a size of the data is less than or equal to a threshold, generate stacked data by stacking a portion of the data, in response to the data being less than or equal to the threshold, and perform the neural network operation in parallel based on the stacked data.

The processor may be configured to store a portion of a first feature map included in the data in a first location of a memory, and generate a stacked feature map by stacking a second feature map included in the data at a location adjacent to the first location.

The processor may be configured to generate the stacked data by stacking one or more of channels included in the first feature map and one or more of channels included in the second feature map in a channel direction.

The processor may be configured to generate a stacked kernel by stacking one or more of kernels included in the data.

The processor may be configured to generate a plurality of tiles by segmenting the data to have a predetermined width or a predetermined height, and generate the stacked data by stacking the plurality of tiles.

The processor may be configured to generate the stacked data, in response to determining whether segmenting the data is beneficial.

The processor may be configured to generate the stacked data by inputting the data to a direct memory access (DMA) engine.

The processor may be configured to search for additional data to perform a second neural network operation that is different from the first neural network operation performed based on the data, determine whether the additional data and the data are stackable, and perform the first neural network operation and the second neural network operation in parallel by stacking the additional data and the data based on a result of determining.

The receiver may be configured to receive subsequent data of the data, wherein the processor may be configured to determine whether a size of the subsequent data is less than or equal to a predetermined size and whether the subsequent data is stackable, and perform the neural network operation by stacking a portion of the subsequent data based on a result of determining and dependency between the data and the subsequent data.

DETAILED DESCRIPTION

Throughout the specification, when a component is described as being “connected to,” or “coupled to” another component, it may be directly “connected to,” or “coupled to” the other component, or there may be one or more other components intervening therebetween. In contrast, when an element is described as being “directly connected to,” or “directly coupled to” another element, there can be no other elements intervening therebetween.

The use of the term “may” herein with respect to an example or embodiment (e.g., as to what an example or embodiment may include or implement) means that at least one example or embodiment exists where such a feature is included or implemented, while all examples are not limited thereto.

Hereinafter, example embodiments will be described in detail with reference to the accompanying drawings. When describing the example embodiments with reference to the accompanying drawings, like reference numerals refer to like components and a repeated description related thereto will be omitted.

FIG.1illustrates an example of a neural network operation apparatus.

Referring toFIG.1, a neural network operation apparatus10may perform a neural network operation. The neural network operation apparatus10may receive data, perform stacking for a portion or all of the data, and perform the neural network operation in parallel using stacked data.

The neural network or an artificial neural network (ANN) may generate mapping between input patterns and output patterns, and may have a generalization capability to generate a relatively correct output with respect to an input pattern that has not been used for training. The neural network may refer to a general model that has an ability to solve a problem, where nodes form the network through synaptic combinations change a connection strength of synapses through training.

The neural network may be a model with a machine learning structure designed to extract feature data from input data and to provide an inference operation based on the feature data. The feature data may be data associated with a feature obtained by abstracting input data. If input data is an image, feature data may be data obtained by abstracting the image and may be represented in a form of, for example, a vector. The neural network may map input data and output data that are in a nonlinear relationship based on deep learning, to perform inference operation. The deep learning, which is a machine learning method used for tasks such as speech recognition or speech transliteration from a big data set, may map input data and output data to each other through supervised and/or unsupervised learning.

The neural network may be implemented as an architecture having a plurality of layers including an input image, feature maps, and an output. In the neural network, the input image may be convoluted with a filter called weights, and as a result, a plurality of feature maps may be output. The output feature maps may be again convoluted as input feature maps with the weights, and a plurality of new feature maps may be output. After the convolution operations are repeatedly performed, the recognition results of features of the input image through the neural network may be finally output.

For example, when an image of a 24×24 pixel size is input to the neural network, the input image may be output as feature maps of 4 channels each having a 20×20 size through a convolution operation with weights. Also, some of the pixel values of the feature maps of 4 channels each having the 20×20 size may be subject to a sub-sampling operation, such as, for example, max-pooling and average-pooling, to output feature maps of 4 channels each having a 10×10 size. In an example, the 10×10 feature maps may be repeatedly subject to convolution operations and sub-sampling operations with weights so that the sizes of the 10×10 feature maps may be reduced, and global features may be output. The neural network may repeatedly perform convolution operations and sub-sampling (or pooling) operations on the several layers to filter robust features, i.e., global features that are capable of representing the input image from the input image, to output the global features, and to input the global features to the fully connected layer, thereby recognizing the input image.

In another example, the neural network may receive an input source sentence, (e.g., voice entry) instead of an input image. In such an example, a convolution operation is performed on the input source sentence with a kernel, and as a result, the feature maps are output. The convolution operation is performed again on the output feature maps as input feature maps, with a kernel, and new feature maps are output. When the convolution operation is repeatedly performed as such, a recognition result with respect to features of the input source sentence may be output through the neural network.

Data input to the input layer is processed through hidden layers, and thus an output value is output from the output layer. In this case, the larger the weight is, the stronger the connectivity between two corresponding nodes becomes. On the other hand, the smaller the weight is, the weaker the connectivity between the two corresponding nodes becomes. For example, a weight may have a value between 0 and 1. When the weight is 0, it may indicate that there is no connectivity between two nodes.

On the other hand, as the connectivity through the weight increases, the connectivity of an artificial neural network may be strengthened and the complexity thereof may increase. As a result, memory allocation for storing the weight increases, and the overall operation speed of the artificial neural network may decrease, and thus the efficiency of the artificial neural network may deteriorate.

In an example, training an artificial neural network may indicate determining and updating weights and biases between layers or weights and biases among a plurality of nodes belonging to different layers adjacent to one another. In an example, weights and biases of a plurality of layered structures, a plurality of layers, or nodes may be collectively referred to as connectivity of an artificial neural network. Therefore, training an artificial neural network may indicate construction and training of the connectivity.

The neural network may include a deep neural network (DNN). The neural network may include a convolutional neural network (CNN), a recurrent neural network (RNN), a perceptron, a multiplayer perceptron, a feed forward (FF), a radial basis network (RBF), a deep feed forward (DFF), a long short-term memory (LSTM), a gated recurrent unit (GRU), an auto encoder (AE), a variational auto encoder (VAE), a denoising auto encoder (DAE), a sparse auto encoder (SAE), a Markov chain (MC), a Hopfield network (HN), a Boltzmann machine (BM), a restricted Boltzmann machine (RBM), a deep belief network (DBN), a deep convolutional network (DCN), a deconvolutional network (DN), a deep convolutional inverse graphics network (DCIGN), a generative adversarial network (GAN), a liquid state machine (LSM), an extreme training machine (ELM), an echo state network (ESN), a deep residual network (DRN), a differentiable neural computer (DNC), a neural turning machine (NTM), a capsule network (CN), a Kohonen network (KN), and an attention network (AN).

The neural network operation apparatus10may be implemented in a personal computer (PC), a data server, or a portable device.

The portable device may be implemented as a laptop computer, a mobile phone, a smart phone, a tablet PC, a mobile internet device (MID), a personal digital assistant (PDA), an enterprise digital assistant (EDA), a digital still camera, a digital video camera, a portable multimedia player (PMP), a personal navigation device or portable navigation device (PND), a handheld game console, an e-book, a smart device, an autonomous vehicle, or a vehicle guidance system. The smart device may be implemented as a smart watch, a smart band, or a smart ring.

The neural network operation apparatus10includes a receiver100and a processor200. The neural network operation apparatus10may further include a memory300.

The receiver100may receive data for a neural network operation. The receiver100may continuously receive data according to the flow of time. The receiver100may receive data and subsequent data of the data for the neural network operation according to the flow of time. The receiver100may include a receiving interface. The receiver100may output the received data to the processor200. The data for the neural network operation may include a model parameter (or, a weight) of the neural network, data input to the neural network, data output from the neural network, or data for training the neural network. For example, the data for the neural network may include a feature map or a kernel.

The processor200may process data stored in the memory300. The processor200may execute a computer-readable code (for example, software) stored in the memory300and instructions triggered by the processor200.

The processor200may be a data processing device implemented by hardware including a circuit having a physical structure to perform desired operations. For example, the desired operations may include code or instructions included in a program.

For example, the hardware-implemented data processing device may include a microprocessor, a central processing unit (CPU), a processor core, a multi-core processor, a multiprocessor, an application-specific integrated circuit (ASIC), and a field-programmable gate array (FPGA). Further details regarding the processor200is provided below.

The processor200may determine whether a size of the data is less than or equal to a size or a threshold. In an example, the size may be predetermined.

The processor200may generate stacked data by stacking a portion of data based on a result of determining whether the size of the data is less than or equal to the predetermined size. The processor200may store a portion of a first feature map included in the data in a first location of the memory300. The processor200may generate a stacked feature map by stacking a second feature map included in the data at a location adjacent to the first location.

The processor200may generate stacked data by stacking one or more of channels included in the first feature map and one or more of channels included in the second feature map in a channel direction.

The processor200may generate a stacked kernel by stacking one or more of kernels included in the data.

The processor200may determine whether segmenting the data is beneficial. The processor200may generate a plurality of tiles by segmenting the data to have a width or a height. In an example, the width and the height may be predetermined. The processor200may generate the stacked data by stacking the plurality of tiles.

The processor200may generate the stacked data by inputting the data to a direct memory access (DMA) engine.

The processor200may search additional data to be used to perform a second neural network operation that is different from a first neural network operation performed based on the data. The processor200may determine whether the additional data and the data are stackable. The processor200may perform the first neural network operation and the second neural network operation by stacking the additional data and the data based on a result of determining.

The processor200may determine whether a size of subsequent data is less than or equal to a predetermined size and whether the subsequent data is stackable. The processor200may perform the neural network operation by stacking a portion of the subsequent data based on a result of determining and a dependency between the data and the subsequent data.

The processor200may perform the neural network operation in parallel based on stacked data.

The processor200may read/write neural network data, for example, text data, voice data, image data, feature map data, kernel data, etc., from/to the memory920and execute a neural network using the read/written data. When the neural network is executed, the processor200may repeatedly perform convolution operations between an input feature map and a kernel, in order to generate data with respect to an output feature map. Here, a number of operations of the convolution operation may be determined, depending on various factors, such as, for example, the number of channels of the input feature map, the number of channels of the kernel, a size of the input feature map, a size of the kernel, and a precision of a value. The neural network may be implemented as a complicated architecture, where the processor200performs the convolution operation with an operation count of up to hundreds of millions to tens of billions, and the frequency at which the processor200accesses the memory300for the convolution operations rapidly increases.

The memory300may store data for an operation or an operation result. The memory300may store executable instructions (or programs) by the processor200. For example, the instructions may include instructions for executing an operation of the processor and/or instructions for performing an operation of each component of the processor.

The memory300may be implemented as a volatile memory device or a non-volatile memory device.

The volatile memory device may be implemented as a dynamic random-access memory (DRAM), a static random-access memory (SRAM), a thyristor RAM (T-RAM), a zero capacitor RAM (Z-RAM), or a twin transistor RAM (TTRAM).

The non-volatile memory device may be implemented as an electrically erasable programmable read-only memory (EEPROM), a flash memory, a magnetic RAM (MRAM), a spin-transfer torque (STT)-MRAM, a conductive bridging RAM(CBRAM), a ferroelectric RAM (FeRAM), a phase change RAM (PRAM), a resistive RAM (RRAM), a nanotube RRAM, a polymer RAM (PoRAM), a nano floating gate Memory (NFGM), a holographic memory, a molecular electronic memory device), or an insulator resistance change memory. Further details regarding the memory300is provided below.

FIG.2illustrates an example of an operation of the neural network training apparatus ofFIG.1.

Referring toFIG.2, a processor (for example, the processor200ofFIG.1) may determine whether a size of data is a predetermined size and may stack the data based on a result of determining. For example, the data may include an input feature map.

The processor200may stack a plurality of independent neural network operations (for example, a convolution operation) having a small number of unaligned input channels. For example, a conventional neural network operation method requires time to perform two convolution operations that have 8×1022×1022 as an output by performing a convolution having a kernel size is 3×3, stride is 1, and padding is 0 for a 2×1024×1024 input.

The processor200may enhance multiplier accumulator (MAC) utilization by fusing a first convolution and a second convolution and may reduce an input feature memory (IFM) footprint.

The processor200may generate stacked data230by stacking a first feature map210and a second feature map220. The processor200may generate a first output250and a second output260in parallel by performing a neural network operation between the stacked data230and a kernel240.

FIG.3illustrates an example of implementation of the neural network operation apparatus ofFIG.1, andFIG.4illustrates an example of operation time of the neural network operation apparatus ofFIG.1.

Referring toFIGS.3and4, a processor (for example, the processor200ofFIG.1) may reduce operation time by stacking a first feature map310and a second feature map320. The processor200may use a DMA as a channel-wise stacker and may reduce operation time by simultaneously performing a plurality of convolution operations using MAC groups (for example, MAC groups #0 to #3) included in a MAC engine360.

The processor200may generate stacked data by inputting data to a DMA engine330.

The processor200may store a portion of the first feature map310included in the data in a first location of a memory (for example, SRAM). The processor200may generate stacked data350by stacking a portion of the second feature map320at a location adjacent to the first location. The processor200may generate the stacked data350by stacking one or more of channels (for example, channel 0 and channel 1 of the first feature map310) included in the first feature map and one or more of channels (for example, channel 0 and channel 1 of the second feature map320) included in the second feature map in a channel direction.

The processor200may generate a stacked kernel340by stacking one or more of kernels included in the data.

The processor200may perform a neural network operation in parallel based on the stacked data350. The processor200may perform a convolution operation with the stacked kernel340by inputting the stacked data350to the MAC engine360.

As an operation result, the processor200may generate convolution outputs370.

In a conventional method, total operation time may be represented by Equation 1.

When the processor200performs a plurality of convolution operations (for example, Conv1and Conv2), total operation time may be represented by Equation 2 and may be reduced by performing optimization through stacking input feature maps (for example, the first feature map310and the second feature map320).

As an example ofFIG.4, the processor200may optimize operation time by stacking a portion of an input feature map (for example, a channel of an input feature map). The processor200may reduce MAC operation execution time by approximately one half by simultaneously performing a first convolution (for example, Conv1) and a second convolution (for example, Conv2) without memory overhead.

FIG.5illustrates an example of stacking operation based on a data dependency.

Referring toFIG.5, a processor (for example, the processor200ofFIG.1) may determine whether segmenting data is beneficial. The processor200may generate a plurality of tiles by segmenting the data to have a width or a height. In an example, the width and height may be predetermined. In another example, the data may be segmented based on a threshold for each of the height and the width. The processor200may generate stacked data by stacking the plurality of tiles.

When an input feature map is sufficiently large, the processor200may stack two tiled portions (for example, tiles) of same shallow convolutions. The stacking method described inFIGS.2to4may be identically applied to a case in which same original convolutions are segmented into a plurality of tiles and stacked.

The processor200may perform stacking for two consecutive convolutions having a small number of unaligned input channels. However, when a dependency between convolution operations is present as an example ofFIG.5, the stacking method described inFIGS.2to4may not be applied because a data dependency interrupts parallel execution.

The processor200may apply a stack optimization technique even when a data dependency is present.

An example ofFIG.5may represent a process of performing optimization for two consecutively tiled convolutional layers of which execution times are dominantly affected by a MAC engine.

In an example ofFIG.5, a data dependency may be represented as follows.

In this case, the processor200may perform stacking for Conv#1Tile#0and Conv#0Tile#1. The processor200may stack Conv#1Tile#1and Conv#0Tile#2.

Performing stacking for a plurality of convolutions may include a stacking process of a kernel and an input feature map used in a convolution operation.

The stack optimization process described above may be similarly applied to a case in which dependencies are more complicated (for example, in case a halo is requiring) than those of an example ofFIG.5, that is, case in which a tiling size greater than or equal to 4 is needed to fill up an execution pipeline.

Through the example tiling and stacking processes ofFIG.5, execution time may be reduced. The processor200may prevent memory reuse such as loading an unnecessary feature map (for example, a second feature map) from a memory (for example, DRAM). The processor200may hide execution time of Conv#1Tile#0and Conv#1Tile#1by stacking the first convolution and the second convolution execution operations.

FIG.6illustrates another example of implementation of the neural network operation apparatus ofFIG.1.

Referring toFIG.6, a neural network operation apparatus (for example, the neural network operation apparatus10ofFIG.1) may include a memory610(for example, the memory300ofFIG.1), a channel-wise stacker630, a MAC hardware650and an output splitter670.

The channel-wise stacker630may stack channel-aligned shallow inputs into one combined input.

The MAC hardware650may perform a MAC operation. The output splitter670may generate an output for a plurality of stacked convolutions by one hardware invocation.

When N shallow aligns are present in the memory610, the channel-wise stacker630may perform optimization for multi-group execution by stacking the N shallows aligns in a compact stacking manner.

Stacked inputs may be processed at once through the MAC hardware650and different outputs for the stacked inputs may be split by the output splitter670.

Through the above-described configuration, the neural network operation apparatus10may reduce memory overhead for a shallow input since the neural network operation apparatus10may reduce a quantity of garbage data in unaligned channels by input channel stacking.

The neural network operation apparatus10may enhance operation speed by processing a plurality of operations at once in parallel.

FIG.7illustrates an example of performing stacking and the neural network operation. The operations inFIG.7may be performed in the sequence and manner as shown, although the order of some operations may be changed or some of the operations omitted without departing from the spirit and scope of the illustrative examples described. Many of the operations shown inFIG.7may be performed in parallel or concurrently. One or more blocks ofFIG.7, and combinations of the blocks, can be implemented by special purpose hardware-based computer, such as a processor, that perform the specified functions, or combinations of special purpose hardware and computer instructions. The description provided with reference toFIGS.1through6also applies to the description ofFIG.7, and are incorporated herein by reference. Thus, a detailed description ofFIGS.1-6will be omitted for conciseness.

Referring toFIG.7, the processor (for example, the processor200ofFIG.1) may determine whether a size of data is less than or equal to a particular size. In an example, the processor may determine whether a size of data is less than or equal to a threshold. For example, in operation711, the processor200may determine whether a convolution operation is for a shallow input feature map channel.

If a convolution is for the shallow input feature map channel, in operation713, the processor200may search for other data independent of the convolution operation of operation711. If the convolution is not for the shallow input feature map channel, in operation715, the processor200may perform general convolution processing.

In operation717, the processor200may determine whether other independent data is discovered. If other independent data is discovered, in operation719, the processor200may determine whether two different convolutions are stackable. If other independent data is not discovered, in operation721, the processor200may determine whether tiling is beneficial.

If two shallow convolutions are stackable, in operation723, the processor200may perform a convolution by stacking an input feature map and a kernel. The processor200may perform a convolution operation based on stacked data using hardware such as a MAC engine by stacking and padding the input feature map and kernel.

If tiling is not beneficial, in operation715, the processor200may perform general convolution processing. If tiling is beneficial, in operation725, the processor200may determine whether a subsequent convolution is shallow and stackable.

If the subsequent convolution is shallow and stackable, in operation727, the processor200may sequentially perform stacking and may determine whether stacking the subsequent convolution is beneficial compared to stacking a same tile in one convolution. If the subsequent convolution is not shallow and not stackable or stacking the subsequent convolution is not beneficial compared to stacking a same tile in one convolution, in operation729, the processor200may process stacked data in hardware such as a MAC engine by tiling in a spatial direction and stacking the convolution kernel.

If stacking the subsequent convolution is beneficial compared to stacking a same tile in one convolution, in operation723, the processor200may perform a convolution by stacking an input feature map and kernel.

As described above, stacking may be performed in three ways. A first case may be stacking two independent convolutions, a second case may be stacking different tiles in a same convolution, and a third case may be stacking a dependent convolution.

If more than one option is available, stacking independent convolutions may be desirable, however, the processor200may determine an optimal stacking method according to software and/or hardware implementation.

Through the above-described stacking methods, hardware utilization rate may be enhanced by processing a neural network operation in parallel on hardware. The processor200may reduce memory footprint for an operation input by using a compactly stacked layout for an input feature map.

FIG.8illustrates an example of an operation of the neural network operation apparatus ofFIG.1. The operations inFIG.8may be performed in the sequence and manner as shown, although the order of some operations may be changed or some of the operations omitted without departing from the spirit and scope of the illustrative examples described. Many of the operations shown inFIG.8may be performed in parallel or concurrently. One or more blocks ofFIG.8, and combinations of the blocks, can be implemented by special purpose hardware-based computer, such as a processor, that perform the specified functions, or combinations of special purpose hardware and computer instructions. The description provided with reference toFIGS.1through7also applies to the description ofFIG.8, and are incorporated herein by reference. Thus, a detailed description ofFIGS.1-7will be omitted for conciseness.

Referring toFIG.8, in operation810, a receiver (for example, the receiver100ofFIG.1) may receive data for a neural network operation. The receiver100may receive subsequent data of the data for the neural network operation.

In operation830, the processor200may determine whether a size of the data is less than or equal to a size. In an example, the size may be predetermined.

In operation850, the processor200may generate stacked data by stacking a portion of the data based on a result of determining whether the size of the data is less than or equal to the size. The processor200may store a portion of a first feature map included in the data in a first location of the memory300. The processor200may generate a stacked feature map by stacking a second feature map included in the data at a location adjacent to the first location.

The processor200may generate stacked data by stacking one or more of channels included in the first feature map and one or more of channels included in the second feature map in a channel direction.

The processor200may generate a stacked kernel by stacking one or more of kernels included in the data.

The processor200may determine whether segmenting the data is beneficial. The processor200may generate a plurality of tiles by segmenting the data to have a width or a height. In an example, the width and height may be predetermined. The processor200may generate the stacked data by stacking the plurality of tiles.

The processor200may generate the stacked data by inputting the data to a DMA engine.

The processor200may search for additional data to be used to perform a second neural network operation that is different from a first neural network operation performed based on the data. The processor200may determine whether the additional data and the data are stackable. The processor200may perform the first neural network operation and the second neural network operation by stacking the additional data and the data based on a result of determining.

The processor200may determine whether a size of the subsequent data is less than or equal to a size and whether the subsequent data is stackable. In an example, the size may be predetermined. The processor200may perform neural network operations by stacking a portion of the subsequent data based on a result of determining and a dependency between the data and the subsequent data.

In operation870, the processor200may perform the neural network operations in parallel based on the stacked data.

The instructions or software to control a processor or computer to implement the hardware components and perform the methods as described above, and any associated data, data files, and data structures, are recorded, stored, or fixed in or on one or more non-transitory computer-readable storage media. Examples of a non-transitory computer-readable storage medium include read-only memory (ROM), random-access programmable read only memory (PROM), electrically erasable programmable read-only memory (EEPROM), random-access memory (RAM), magnetic RAM (MRAM), spin-transfer torque(STT)-MRAM, static random-access memory (SRAM), thyristor RAM (T-RAM), zero capacitor RAM (Z-RAM), twin transistor RAM (TTRAM), conductive bridging RAM(CBRAM), ferroelectric RAM (FeRAM), phase change RAM (PRAM), resistive RAM(RRAM), nanotube RRAM, polymer RAM (PoRAM), nano floating gate Memory(NFGM), holographic memory, molecular electronic memory device), insulator resistance change memory, dynamic random access memory (DRAM), static random access memory (SRAM), flash memory, non-volatile memory, CD-ROMs, CD-Rs, CD+Rs, CD-RWs, CD+RWs, DVD-ROMs, DVD-Rs, DVD+Rs, DVD-RWs, DVD+RWs, DVD-RAMs, BD-ROMs, BD-Rs, BD-R LTHs, BD-REs, blue-ray or optical disk storage, hard disk drive (HDD), solid state drive (SSD), flash memory, a card type memory such as multimedia card micro or a card (for example, secure digital (SD) or extreme digital (XD)), magnetic tapes, floppy disks, magneto-optical data storage devices, optical data storage devices, hard disks, solid-state disks, and any other device that is configured to store the instructions or software and any associated data, data files, and data structures in a non-transitory manner and providing the instructions or software and any associated data, data files, and data structures to a processor or computer so that the processor or computer can execute the instructions. In an example, the instructions or software and any associated data, data files, and data structures are distributed over network-coupled computer systems so that the instructions and software and any associated data, data files, and data structures are stored, accessed, and executed in a distributed fashion by the one or more processors or computers