Forming sensing elements above a semiconductor substrate

An integrated circuit structure includes a substrate and a metallization layer over the substrate. The metallization layer includes a dielectric layer and metal lines in the dielectric layer. The integrated circuit structure further includes a sensing element over the metallization layer. The sensing element may be formed in passivation layers.

TECHNICAL FIELD

This invention relates generally to sensing elements, and more particularly to integrating the sensing elements with integrated circuits.

BACKGROUND

Sensors are typically used for detecting environment parameters, such as light intensity, sound, pressure, and the like. Sensors are also widely used in imaging applications, such as infrared imaging for night vision. Existing sensors are often integrated with integrated circuits, for example, application specific integrated circuits (ASIC), which may in-situ process the sensed signals. For imaging applications, a great amount of processing may be involved. Integrating the sensors with the ASIC is thus advantageous for improving the performance.

Conventionally, image sensors that respond to photons were formed at the surface of (or even “in”) semiconductor substrates.FIG. 1illustrates a cross-sectional view of photo diodes4built in semiconductor substrate2. Photo diodes4may be formed as an array. To suit the requirement of the ASIC, which is formed on the same semiconductor substrate2, a plurality of metallization layers6(sometimes up to nine layers) are formed over photo diodes4. Metallization layers6include dielectric layers, and metal lines formed in the dielectric layers. Further, passivation layer(s)8are formed on metallization layers6.

For photo diodes4to sense photons, the photons (symbolized by arrows10) have to penetrate the dielectric layers in metallization layers6and the passivation layer(s)8. This causes the degradation in the signal strength received by photo diodes4. Further, metallization layers6typically include low-k dielectric layers, and etch stop layers (ESLs) between the low-k dielectric layers. The ESL layers and low-k dielectric layers have different refractive indexes, resulting in the reflection and deflection of the photons. As a result, cross-talk occurs. For example, the non-uniformity of the ESLs and the low-k dielectric materials may cause the non-uniformity in the deflection, and hence photons12, which are destined to photo diode41to be received by photo diode42. The sensed image is thus distorted.

The conventional sensor formation has conflicting requirements with the formation of the ASIC. To reduce the adverse effect caused by layers6and8, it is preferred that inter-layer dielectric (ILD) and inter-metal dielectrics (IMD) are as thin as possible. However, reducing the thicknesses of ILD and IMDs causes process difficulty and possible performance degradation for the ASIC, and may require customized formation processes. New methods for forming sensors are thus needed for solving the above-discussed problems.

SUMMARY OF THE INVENTION

In accordance with one aspect of the present invention, an integrated circuit structure includes a substrate; and a metallization layer over the substrate. The metallization layer includes a dielectric layer, and metal lines in the dielectric layer. The integrated circuit structure further includes a sensing element over the metallization layer. The sensing element may be formed in passivation layers.

In accordance with another aspect of the present invention, an integrated circuit structure includes a semiconductor substrate; a plurality of metallization layers over the semiconductor substrate, wherein each of the metallization layer comprises a low-k dielectric layer, and metal lines in the low-k dielectric layer; a first passivation layer over the plurality of metallization layers; and a sensing element in the first passivation layer.

In accordance with yet another aspect of the present invention, an integrated circuit structure includes a semiconductor substrate; a plurality of metallization layers over the semiconductor substrate; a first passivation layer over the plurality of metallization layers; a bond pad in the first passivation layer; an electrode in the first passivation layer, wherein the bond pad and the electrode are formed of same materials; a sensing element over and electrically connected to the electrode; and a second passivation layer over the first passivation layer. The bond pad is exposed through the second passivation layer.

The advantageous features of the present invention include improved signal strengths of sensed signals, reduced cross-talk, and reduced manufacturing cost.

DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS

A novel method for forming sensing elements is provided. The intermediate stages of manufacturing a preferred embodiment of the present invention are illustrated. The variations of the preferred embodiments are then discussed. Throughout the various views and illustrative embodiments of the present invention, like reference numbers are used to designate like elements.

Referring toFIG. 2, substrate20is provided. Substrate20is preferably a semiconductor substrate formed of commonly used semiconductor materials such as silicon, silicon germanium, and the like. Active and/or passive devices, such as transistors, resistors, capacitors, and the like, may be formed at the surface of substrate20, or over substrate20. These active/passive devices, which are symbolized by region21, may be part of an application specific integrated circuit (ASIC).

Metallization layers34are formed over substrate20. Inter-layer dielectric (ILD) layer22is formed under metallization layers34, and may be formed of borophosphosilicate glass (BPSG) or other dielectric materials. Contacts23are formed in ILD layer22, and connect the integrated circuits to the overlying metallization layers34. Inter-metal dielectrics (IMD) layers26are formed over ILD layer22, and may be formed of low-k dielectric materials, for example, with dielectric constants (k value) less than about 3.9. IMD layers26may also be formed of extra low-k (ELK) dielectric materials, which may have k values of less than about 2.5. Exemplary materials include carbon-containing low-k dielectric materials, which may further include silicon, oxygen, nitrogen, and combinations thereof. The number of IMD layers26depends on the complexity of the application, and may range from two to nine layers. Etch stop layers24separate IMD layers26from each other. Etch stop layers24may be formed of dielectric materials having greater k values than IMD layers26.

Metal lines28and vias30are formed in dielectric layers22and26, and are used to interconnect integrated circuits formed on substrate20, and to connect the subsequently formed sensing elements to the integrated circuits. Metal lines28and vias30may be formed using damascene processes. The formation of dielectric layers22and26, metal lines28, and vias30are known in the art, and hence are not repeated herein.

Referring toFIG. 3, electrode layer38is formed over metallization layers34, and is electrically connected to metal lines28and vias30. Electrode layer38may include layer382and barrier/adhesion layers381and/or383, which are preferably formed of titanium, titanium nitride, tantalum, tantalum nitride, or the like. Layer382may be formed of aluminum, copper, tungsten, or alloys thereof.

Next, as shown inFIG. 4, electrode layer38is patterned to form electrodes40and bond pad42. Preferably, each of the electrodes40and bond pad42is electrically connected to underlying features such as metal lines28. A passivation layer (referred to as passivation layer1hereinafter) is then formed. In an embodiment, passivation layer1is formed of silicon oxide, although it may also be formed of un-doped silicate glass (USG), or other commonly used dielectric materials having higher k values and greater mechanical strengths than the underlying IMD layers26and ILD layer22. A chemical mechanical polish is then performed to level the top surface of passivation layer1.

Referring toFIG. 5, passivation layer1is etched back, exposing electrodes40and bond pad42. Preferably, an over-etch is performed, so that top portions of electrodes40are above the top surface of the remaining passivation layer1. Sensing element46is then formed, as is shown inFIG. 6. The formation of sensing element46may include blanket depositing a sensing material layer, and then patterning the sensing material layer. In an embodiment, sensing element46is connected to two electrodes40. In other embodiments, sensing element46is connected to only one electrode40. Through electrodes40and underlying metal lines28and vias30, sensing element46may be connected to the integrated circuits on substrate20.

Sensing element46may be used for sensing light intensity (photons), and hence may be referred to as image sensor46. Sensing element46may also be used for sensing other environment parameters, such as pressure, sound, temperature, and the like. The materials, shapes, and dimensions are thus determined according to the intended purpose. For example, the dimensions of sensing element46are preferably greater than the wavelength of the sound or light to be sensed. The applicable materials of sensing element46include polymers, resins, or other compound materials. These materials are capable of generating different numbers of electrons (which result in the desirable electrical signal) when the external environments, such as the light intensity, the pressure, or the like, change. Through electrodes40and underlying metal lines28and via30, the electrical signals are transferred to the integrated circuit for further processing. In an exemplary embodiment in which light is to be sensed, sensing element46is formed of PbS.

FIGS. 7A and 7Billustrate the continued formation of passivation layers. In an embodiment, passivation layer1is continually formed to cover sensing element46and bond pad42. An additional passivation layer (referred to as passivation layer2hereinafter) is then formed on passivation layer1. Passivation layer2is preferably formed of a different material than that of passivation layer1. Exemplary materials include silicon nitride and USG. However, other commonly used passivation materials may also be used. In alternative embodiments, only one passivation layer is formed, and after passivation layer1covers sensing element46and bond pad42, no further passivation layer is formed.

FIG. 7Aillustrates an embodiment of the present invention. Passivation layers1and2are etched to expose bond pad42. Sensing element46remains covered by passivation layers1and2. The covered sensing element46is functional for receiving photons, which only need to penetrate the passivation layers1and2before they are sensed by sensing element46. Compared to the conventional scheme in which sensing elements are formed under metallization layers34, the signal received by sensing element46is stronger. In addition, the photons only need to pass at most one interface between different materials (in this case, between passivation layers1and2), and hence the reflection and deflection of the photons are reduced. As a result, the signal cross-talk is reduced. In alternative embodiments in which pressure, sound, or the like are to be sensed, sensing element46is preferably exposed through passivation layers1and2, as is shown inFIG. 7B. In this embodiment, the portions of passivation layers1and2covering sensing element46are removed simultaneously with the removal of the portion of passivation layers1and2over bond pad42.

FIG. 8illustrates an alternative embodiment of the present invention, in which sensing element46is formed under passivation layer1, and in a layer between passivation layer1and ILD22. Although compared to the embodiment shown inFIG. 7A, photons need to penetrate more dielectric layers before they can reach sensing element, the result is still better than forming sensing element46underlying ILD22.

A semiconductor chip may include a plurality of sensing elements46.FIG. 9illustrates a top view f semiconductor chip50, which includes an array of sensing elements46, wherein each of the sensing elements46may have essentially the same structure as shown inFIG. 7Aor7B, and may be formed using essentially the same method as discussed in the preceding paragraphs.

The embodiments of the present invention have several advantageous features. By forming the sensing elements closer to the top surface of semiconductor chips, the signals received by the sensing elements are improved. For image sensors, the cross-talk is reduced since photons are less likely to be reflected and deflected with fewer layers for them to penetrate. Other sensors such as sound or pressure sensors may be conveniently exposed through the top surface of the respective semiconductor chip, resulting in improved performance and reduced manufacturing cost. For ASIC applications, there is no longer the concern for reducing the thicknesses of ILD and IMDs.