Opening hard mask and SOI substrate in single process chamber

Methods for opening a hard mask and a silicon-on-insulator substrate in a single process chamber are disclosed. In one embodiment, the method includes patterning a photoresist over a stack including an anti-reflective coating (ARC) layer, a silicon dioxide (SiO2) based hard mask layer, a silicon nitride pad layer, a silicon dioxide (SiO2) pad layer and the SOI substrate, wherein the SOI substrate includes a silicon-on-insulator layer and a buried silicon dioxide (SiO2) layer; and in a single process chamber: opening the ARC layer; etching the silicon dioxide (SiO2) based hard mask layer; etching the silicon nitride pad layer; etching the silicon dioxide (SiO2) pad layer; and etching the SOI substrate. Etching all layers in a single chamber reduces the turn-around-time, lowers the process cost, facilitates process control and/or improve a trench profile.

BACKGROUND OF THE INVENTION

1. Technical Field

The invention relates generally to etching methods, and more particularly, to methods for opening a hard mask and a silicon-on-insulator (SOI) substrate in a single process chamber.

2. Background Art

Silicon-on-insulator (SOI) substrates are increasingly used with trenches for structures, such as trench capacitors, to provide further improvement of semiconductor device performance. However, forming trenches in an SOI substrate presents a number of challenges. For example, SOI substrate trenches require etching multiple layers including a silicon dioxide (SiO2) based hard mask, a silicon nitride (Si3N4) pad layer, a silicon dioxide (SiO2) pad layer, and the silicon-on-insulator (SOI) layer and a buried silicon dioxide (SiO2) (BOX) layer of the SOI substrate. Because each etch chamber is conventionally designed and optimized to etch a specific material, etching multiple layers usually requires multiple etch process steps performed in multiple chambers in order to achieve a desired trench profile. For example, etching the SOI substrate requires use of another process chamber. Transferring wafers from one chamber to another increases the time required to complete the process. In addition, multiple chambers increase equipment expense. The above-described processes also may result in non-uniform SOI openings across an entire wafer, consumption of photoresist prior to etching of the BOX layer, and inadequate profile control. There is therefore a need in the art for a solution to the problems of the related art.

SUMMARY OF THE INVENTION

Methods for opening a hard mask and a silicon-on-insulator (SOI) substrate in a single process chamber are disclosed. In one embodiment, the method includes patterning a photoresist over a stack including an anti-reflective coating (ARC) layer, a silicon dioxide (SiO2) based hard mask layer, a silicon nitride pad layer, a silicon dioxide (SiO2) pad layer and the SOI substrate, wherein the SOI substrate includes a silicon-on-insulator a layer and a buried silicon dioxide (SiO2) layer; and in a single process chamber: opening the ARC layer; etching the silicon dioxide (SiO2) based hard mask layer; etching the silicon nitride pad layer; etching the silicon dioxide (SiO2) pad layer; and etching the SOI substrate using an etch chemistry including nitrogen (N2). Etching all layers in a single chamber reduces the turn-around-time, lowers the process cost, facilitates process control and/or improves trench profile.

A first aspect of the invention provides a method of opening a hard mask and a silicon-on-insulator (SOI) substrate, the method comprising the steps of: patterning a photoresist over a stack including an anti-reflective coating (ARC) layer, a silicon dioxide (SiO2) based hard mask layer, a silicon nitride pad layer, a silicon dioxide (SiO2) pad layer and the SOI substrate, wherein the SOI substrate includes a silicon-on-insulator (SOI) layer and a buried silicon dioxide (SiO2) layer; and in a single process chamber: opening the ARC layer; etching the silicon dioxide (SiO2) based hard mask layer; etching the silicon nitride pad layer; etching the silicon dioxide (SiO2) pad layer; and etching the SOI substrate.

A second aspect of the invention provides a method of opening a hard mask and a silicon-on-insulator (SOI) substrate, the method comprising the steps of: patterning a photoresist over a stack including an anti-reflective coating (ARC) layer, a silicon dioxide (SiO2) based hard mask layer, a silicon nitride pad layer, a silicon dioxide (SiO2) pad layer and the SOI substrate, wherein the SOI substrate includes a silicon-on-insulator (SOI) layer and a buried silicon dioxide (SiO2) layer; and in a single process chamber: opening the ARC layer; etching the silicon dioxide (SiO2) based hard mask layer; etching the silicon nitride pad layer; etching the silicon dioxide (SiO2) pad layer; and etching the SOI substrate using an etch chemistry including: approximately 90 standard cubic centimeters per minute (sccm) of difluoromethane (CH2F2), approximately 40 sccm of tetrafluoromethane (CF4), approximately 27 sccm of oxygen (O2) and approximately 200 sccm of nitrogen (N2) for the SOI layer.

A third aspect of the invention provides a method of opening a hard mask and a silicon-on-insulator (SOI) substrate, the method comprising the steps of: providing a stack including an anti-reflective coating (ARC) layer, a silicon dioxide (SiO2) based hard mask layer, a silicon nitride pad layer, a silicon dioxide (SiO2) pad layer and the SOI substrate, wherein the SOI substrate includes a silicon-on-insulator (SOI) layer and a buried silicon dioxide (SiO2) layer; patterning a photoresist over the stack; and in a single process chamber: opening the ARC layer; etching the silicon dioxide (SiO2) based hard mask layer; etching the silicon nitride pad layer; etching the silicon dioxide (SiO2) pad layer; and etching the SOI substrate using an chemistry including: approximately 90 standard cubic centimeters per minute (sccm) of difluoromethane (CH2F2), approximately 40 sccm of tetrafluoromethane (CF4), approximately 27 sccm of oxygen (O2) and approximately 200 sccm of nitrogen (N2) for the SOI layer, and approximately 10-30 sccm oxygen (O2), 10-40 sccm hexafluorobutadiene (C4F6) and 900-1200 sccm argon (Ar) for the buried silicon dioxide (SiO2) layer.

The illustrative aspects of the present invention are designed to solve the problems herein described and/or other problems not discussed.

DETAILED DESCRIPTION

Turning to the drawings,FIG. 1shows a first step of one embodiment of a method of opening a hard mask and a silicon-on-insulator (SOI) substrate according to the invention. In a first step, a stack100is provided including an anti-reflective coating (ARC) layer102, a silicon dioxide (SiO2) based hard mask layer104, a silicon nitride pad layer106, a silicon dioxide (SiO2) pad layer108and a silicon-on-insulator (SOI) substrate110. SOI substrate110includes a silicon-on-insulator (SOI) layer112and a buried silicon dioxide (SiO2) (BOX) layer114. SOI substrate110is positioned over a bulk silicon substrate116. As also shown inFIG. 1, the first step may also include patterning a photoresist120over stack100in any now known or later developed fashion.

In a second step, shown inFIG. 2, ARC layer102is opened in any now known or later developed fashion. For example, ARC layer102may be opened by performing an etch130including approximately 100-200 standard cubic centimeters per minute (sccm) of tetrafluoromethane (CF4) with a power of 400-700 Watts and a pressure of 50-150 milli-Torr.

In a third step, shown inFIG. 3, silicon dioxide (SiO2) based hard mask layer104(hereinafter “hard mask layer104”), silicon nitride pad layer106and silicon dioxide (SiO2) pad layer108are etched132in any now known or later developed fashion. Hard mask layer104may include, for , boro-silicate glass (BSG) or other silicon dioxide (SiO2) based hard mask material such as undoped silicon dioxide (SiO2) deposited by any suitable processes such as chemical vapor deposition (CVD) including low pressure CVD, plasma enhanced CVD, or high density plasma CVD. As known in the art, each material may require a different etch chemistry. For example, etch132may include 10-30 sccm oxygen (O2), 10-40 sccm hexafluorobutadiene (C4F6) and 900-1200 sccm argon (Ar) for hard mask layer104, and may include 50-100 sccm difluoromethane (CH2F2), 10-40 sccm oxygen (O2), 40-80 sccm tetrafluoromethane (CF4) and 400-1000 sccm argon (Ar) for pad layers106and108.

In a fourth step, shown inFIGS. 4-5, SOI substrate110is etched134and136. Etching134etches through silicon-on-insulator (SOI) layer112(FIG. 4). In one embodiment of the invention, etching134uses an etch chemistry including nitrogen (N2) rather than the typical carbon monoxide based chemistry. In one embodiment, the etch chemistry includes approximately 80-100 sccm of difluoromethane (CH2F2), approximately 35-45 sccm of tetrafluoromethane (CF4), approximatey 25-30 sccm of oxygen (O2) and approximately 180-220 sccm of nitrogen (N2). More specifically, the etching chemistry may include: approximately 90 sccm of difluoromethane (CH2F2), approximately 40 sccm of tetrafluoromethane (CF4), approximately 27 sccm of oxygen (O2) and approximately 200 sccm of nitrogen (N2). Etching136etches through BOX layer114(FIG. 5). In one embodiment, the etch chemistry may include using approximately 10-30 sccm oxygen (O2), 10-40 sccm hexafluorobutadiene (C4F6) and 900-1200 sccm argon (Ar).

The above-described etching chemistry allows etchings,130,132,134and136to occur in a single process chamber140(FIGS. 2-6).

FIG. 6shows an alternative step in which SOI substrate110etching further includes an overetch step138into bulk silicon substrate116under SOI substrate110. In one embodiment, the overetch step138chemistry may include using approximately 80-100 sccm of difluoromethane (CH2F2), approximately 35-45 sccm of tetrafluoromethane (CF4), approximately 25-30 sccm of oxygen (O2) and approximately 180-220 sccm of nitrogen (N2).

The above-described embodiments allow etching hard mask layer104, silicon nitride pad layer106, silicon dioxide (SiO2) pad layer108, silicon-on-insulator (SOI) substrate110, and overetching into bulk silicon substrate in a single process chamber140by using a photoresist as a single mask which decreases equipment expense and quickens processing. In addition, the above-described embodiments result in a more uniform SOI substrate110opening across an entire wafer, reduce consumption of photoresist120, and/or improve profile control.