A DAC is provided to convert an input word into dual output voltages, and the input word includes a least significant bit and remaining bits. The DAC includes an R-string DAC section and a selecting section. The R-string DAC section is capable of providing an nth and (n+2)th voltage levels according to the remaining bits. The selecting section includes a first multiplexer and a second multiplexer. The first multiplexer is coupled to the R-string DAC section to provide a first output voltage according to a panel polarity signal. The second multiplexer is coupled to the R-string DAC section to provide a second output voltage according to the LSB bit of the N-bit input word. The DAC may further include an operational amplifier to average the dual output voltages for producing an analog output signal.

CROSS-REFERRENCE TO RELATED APPLICATIONS

This application is related to U.S. application Ser. No. 11/168,334, filed on Jun. 29, 2005, which is hereby incorporated by reference in its entirety.

BACKGROUND

1. Field of Invention

The present invention relates to digital-to-analog converters. More particularly, the present invention relates to a digital-to-analog converter having two sections for processing an input word.

1. Description of Related Art

There are many different types of digital-to-analog converters (DAC) available, such as a resistor string (R-string) DAC.FIG. 1illustrates a conventional R-string DAC. An R-string DAC100includes a resistor string of resistors110and a selector120. The selector120includes selecting lines124each of which is composed of switching elements122. Each switching element122is controlled by one of the bits of an input word.

The resistor string is connected between a high reference voltage (VH) and a low reference voltage (VL). Each of the selecting lines124is connected to one of the nodes in the resistor string. Only one of the selecting lines124has switches all turned on by the input word and couples the voltage on the corresponding node in the resistor string to the output node Vo.

For N-bit digital-to-analog conversion, the R-string DAC100requires 2Nselecting lines. Moreover, each of the selected lines124requires N switching elements. Therefore, 2N×N switching elements are required for the N-bit R-string DAC100. The number of switching elements dramatically increases when the bits of the input word are increased, which results in a larger layout area. This is disadvantageous for chip shrinkage and cost reduction.

SUMMARY

It is therefore an aspect of the present invention to provide a DAC, of which the circuit loading is lowered and the layout area is decreased.

According to one embodiment of the present invention, the DAC is provided to convert an input word into dual output voltages, and the input word includes a least significant bit (LSB) and remaining bits. The DAC includes an R-string DAC section and a selecting section. The R-string DAC section is capable of providing an nth and (n+2)th voltage levels according to the remaining bits.

The selecting section includes a first multiplexer and a second multiplexer. The first multiplexer is coupled to the R-string DAC section to provide a first output voltage according to a panel polarity signal. The second multiplexer is coupled to the R-string DAC section to provide a second output voltage according to the LSB bit of the N-bit input word.

The DAC may further include an operational amplifier to average the dual output voltages for producing an analog output signal.

In conclusion, an input word includes an LSB bit and remaining bits. A R-string DAC section is capable of providing an nth and (n+2)th voltage levels according to the remaining bits, which has one less switching element for each of the selected lines results in fewer switching elements needed compared to the conventional N-bit R-string DAC. Therefore, the circuit loading of the DAC is effectively lowered and the layout area is decreased. Further, a selecting section is coupled to the R-string DAC section to provide dual output voltages according to the LSB bit and a panel polarity signal. An operational amplifier may be adopted to average the dual output voltages to produce an analog output signal.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

FIG. 2illustrates one embodiment of the present invention. A DAC200converts an input word into dual output voltages VO1and VO2. An input word includes a least significant bit (LSB) and remaining bits. An 8-bit input word B7B6B5B4B3B2B1B0includes an LSB bit B0and remaining bits B7B6B5B4B3B2B1. The DAC200includes an R-string DAC section202and a selecting section204. The R-string DAC section202is capable of providing an nth and (n+2)th voltage levels according to the remaining bits of the input word. The selection section204provides dual output voltages VO1and VO2. The selection section204includes a first multiplexer208and a second multiplexer210. The first multiplexer208is coupled to the R-string DAC section202. The first multiplexer208provides a first output voltage VO1according to a panel polarity signal (e.g. an MREV signal). The second multiplexer210is coupled to the R-string DAC section202. The second multiplexer210provides a second output voltage VO2according to the LSB bit of the input word.

The DAC200may include an operational amplifier206. The operation amplifier206is coupled to the selecting section204, and averages the dual output voltages VO1and VO2to produce an analog output signal VO.

FIG. 3illustrates one embodiment of the R-string DAC section. An R-string DAC section300includes a voltage generator and a 2-of-N selector302. The voltage generator is capable of providing voltage levels V0, V2, . . . , V254, V256. The voltage levels V0, V2, . . . V256are the even-numbered discrete analog voltages for digital-to-analog conversion of an 8-bit input word. The voltage generator includes resistors308electrically connected in series between a high reference voltage (VH) and a low reference voltage (VL) to provide voltage levels V0, V2, . . . , V254, V256. The 2-of-N selector302is coupled to the voltage generator, and selects an nth voltage level and an (n+2)th voltage level [for example, (V0and V2) or (V252and V254) voltage levels] according to the remaining bits.

More particularly, the 2-of-N selector302has selecting lines304correspondingly coupled to the voltage generator and selects the nth voltage level and the (n+2)th voltage level. For the 8-bit DAC, each of the selecting lines304includes 7 switching elements306[(total number bits of the input word-1) of switching elements], and each of the switching elements306(D7D6D5D4D3D2D1) is controlled by one of the remaining bits (B7B6B5B4B3B2B1). The switching elements306comprise PMOS and NMOS transistors. These transistors are arranged so that two adjacent voltage levels Vnand Vn+2are respectively output to the nodes Vin1and Vin2when the remaining bits (B7B6B5B4B3B2B1) are received, where n is an integer between 0 and 254. More specifically, when the remaining bits 0000000 are received, the voltage levels V0and V2are respectively output as the voltages Vin1and Vin2. When the remaining bits 1111111 are received, the voltage levels V254and V256are respectively output as the voltages Vin1and Vin2.

Referring toFIG. 2, the first input terminal (1) of the first multiplexer208and the second input terminal (0) of the second multiplexer210are coupled to Vin1voltage level, the second input terminal (0) of the first multiplexer208and the first input terminal (1) of the second multiplexer210are coupled to the Vin2voltage level.

The first multiplexer208selects one of the voltages Vin1and Vin2as the first output voltage VO1according to the panel polarity signal MREV signal, and the second multiplexer210selects one of the voltages Vin1and Vin2as the second output voltage VO2according to the LSB bit of the input word. More particularly, the first multiplexer208selects the voltage Vin1as the first output voltage VO1while the panel polarity signal has a high logic level, and the first multiplexer208selects the voltage Vin2as the first output voltage VO1while the panel polarity signal has a low logic level. The second multiplexer210selects the voltage Vin2as the second output voltage VO2while the LSB bit of the input word has a high logic level, the second multiplexer210selects the voltage Vin1as the second output voltage VO2while the LSB bit of the input word has a low logic level.

For clarity, Table 1 shows the voltage levels of the signals Vin1, Vin2, VO1, VO2and VOfor different input words and logic levels of the signal MREV.

Those skilled in the art will appreciate that the MREV signal is the panel polarity signal for data inversion. The MREV signal may be used for the flat display of the mobile phone. Referring to row 2 of Table 1, when the input word is 00,000,000, the Vin1is equal to V0, and the Vin2is equal to V2. The MREV signal has a high logic level so that V0is selected as the first output voltage VO1. V0is selected as the second output voltage VO2since the LSB of the input word is 0.

Referring to row 3 of Table 1, when the input word is 11,111,111, the Vin1is equal to V254, and the Vin2is equal to V256. The MREV signal has a low logic level so that V256is selected as the first output voltage VO1. V256is also selected as the second output voltage VO2since the LSB of the input word is 1.

The operation amplifier206is coupled to the selecting section204, and is capable of averaging the dual output voltages VO1and VO2to produce an analog output signal VO, i.e., the analog output signal VOis equal to (VO1+VO2)/2. For the input word “00000000”, both the voltages VO1and VO2are V0so that VO=(V0+V0)/=V0. For the input word “00000001”, the voltages VO1and VO2are respectively V0and V2so that VO=(V0+V2)/2=V1