Phase change memory elements using energy conversion layers, memory arrays and systems including same, and methods of making and using

A phase change memory element and method of forming the same. The memory element includes a phase change material layer electrically coupled to first and second conductive material layers. A energy conversion layer is formed in association with the phase change material layer, and electrically coupled to a third conductive material layer. An electrically isolating material layer is formed between the phase change material layer and the energy conversion layer.

FIELD OF THE INVENTION

Embodiments of the invention relate to semiconductor devices, and in particular to phase change memory elements, memory arrays and systems including the same, and methods of forming and using the same.

BACKGROUND OF THE INVENTION

Non-volatile memories are important elements of integrated circuits due to their ability to retain data absent a power supply. Phase change materials have been investigated for use in non-volatile memory cells, including chalcogenide alloys, which are capable of stably transitioning between amorphous and crystalline phases. Each phase exhibits a particular resistance state and the resistance states distinguish the logic values of the memory element. Specifically, an amorphous state exhibits a relatively high resistance, and a crystalline state exhibits a relatively low resistance.

A conventional phase change memory element1, illustrated inFIGS. 1A and 1B, has a layer of phase change material8between first and second electrodes2,4, which are supported by a dielectric material6. The phase change material8is set to a particular resistance state according to the amount of current applied through the first and second electrodes2,4. To obtain an amorphous state (FIG. 1B), a relatively high write current pulse (a reset pulse) is applied through the conventional phase change memory element1to melt at least a portion8aof the phase change material8covering the first electrode2for a first period of time. The current is removed and the phase change material8cools rapidly to a temperature below the crystallization temperature, which results in the portion8aof the phase change material8covering the first electrode2having the amorphous state. To obtain a crystalline state (FIG. 1A), a lower current write pulse (a set pulse) is applied to the conventional phase change memory element1for a second period of time (typically longer in duration than the crystallization time of the amorphous phase change material) to heat the amorphous portion of the phase change material8to a temperature below its melting point, but above its crystallization temperature. This causes the amorphous portion8a(FIG. 1B) of the phase change material8to re-crystallize to the crystalline state that is maintained once the current is removed and the phase change memory element1is cooled. The phase change memory element1is read by applying to the electrodes a read voltage, which does not change the phase state of the phase change material8.

A sought after characteristic of non-volatile memory is low power consumption. Oftentimes, however, conventional phase change memory elements require large operating currents. As the phase change memory is scaled down to allow large scale device integration and per-bit current reduction, the programmable volume (e.g., portion8aofFIGS. 1A and 1B) of the phase change cell is shrunk further with an increasing surface-to-volume ratio. The increased surface-to-volume ratio of the programmable volume (e.g., portion8aofFIGS. 1A and 1B) causes increased thermal dissipation through the surface, and larger power density is required to achieve the same local heating in the programmable volume (e.g., portion8aofFIGS. 1A and 1B). Consequently a larger current density is necessary (approximately 1×1012Amps/m2) for the write operation of the phase change cell. The larger current density creates severe critical reliability issues such as electromigration of the phase change material atoms (e.g., germanium-antimony-tellurium (GeSbTe)) that are placed under a high electric field for the conventional phase change memory methodology in which the cell itself acts as the heating element.

It is therefore desirable to provide phase change memory elements with reduced current requirements. For phase change memory elements, it is necessary to have a current density that will heat the phase change material past its melting point and quench it in an amorphous state. One way to increase current density is to decrease the size of the first electrode (first electrode2ofFIGS. 1A and 1B). These methods maximize the current density at the interface between the first electrode2and the phase change material8. Although these conventional solutions are typically successful, it is desirable to further reduce the overall current flow in the phase change memory element, thereby reducing power consumption in certain applications, and possibly to reduce the current density passing through the phase change material to improve its reliability.

Another desired property of phase change memory is its switching reliability and consistency. Conventional phase change memory elements (e.g., phase change memory element1ofFIGS. 1A and 1B) have phase change material layers (e.g., phase change material layer8ofFIGS. 1A and 1B) that are not confined, and have the freedom to extend sideways. Accordingly, the interface between the migrated amorphous portions and crystalline portions of the phase change material may cause reliability issues during programming and reprogramming of the phase change cell.

DETAILED DESCRIPTION OF THE INVENTION

In the following detailed description, reference is made to various specific embodiments of the invention. These embodiments are described with sufficient detail to enable those skilled in the art to practice the invention. It is to be understood that other embodiments may be employed, and that various structural, logical and electrical changes may be made.

The term “substrate” used in the following description may include any supporting structure including, but not limited to, a semiconductor substrate that has an exposed substrate surface. A semiconductor substrate should be understood to include silicon, silicon-on-insulator (SOI), silicon-on-sapphire (SOS), doped and undoped semiconductors, epitaxial layers of silicon supported by a base semiconductor foundation, and other semiconductor structures, including those made of semiconductors other than silicon. When reference is made to a semiconductor substrate or wafer in the following description, previous process steps may have been utilized to form regions or junctions in or over the base semiconductor or foundation. The substrate also need not be semiconductor-based, but may be any support structure suitable for supporting an integrated circuit, including, but not limited to, metals, alloys, glasses, polymers, ceramics, and any other supportive materials as is known in the art.

The invention is now explained with reference to the figures, which illustrate embodiments and throughout which like reference numbers indicate like features.FIGS. 2A and 2Billustrate a first embodiment of a phase change memory element100constructed in accordance with the invention.

The phase change memory element100includes a substrate10having a first dielectric layer12formed thereon, and a first electrode14formed in a via24within the first dielectric layer12. The phase change memory element100also includes a phase change material layer16formed over, and in electrical communication with, the first electrode14. The phase change memory element100also includes a energy conversion layer18that surrounds the phase change material layer16. A material element17is formed between the energy conversion layer18and the phase change material layer16to electrically isolate the two structures. A second dielectric layer20is formed over and around the energy conversion layer18.

The second dielectric material20includes first, second, and third vias29a,29b,29c, which allow for second, third, and fourth electrodes22,26,30, respectively, to be formed therein. A third dielectric layer28is formed to surround the second, third, and fourth electrodes22,26,30. A fourth dielectric layer32is formed over the third dielectric layer28. A metal line30ais formed over the fourth dielectric layer32, and connects with fourth electrode30.

FIG. 2Billustrates a partial top-down view of theFIG. 2Aphase change memory element100. As illustrated, the energy conversion layer18surrounds the material element17, which surrounds the phase change material layer16. The first and second electrodes14,22are in electrical communication with the phase change material layer16. The third electrode26is in electrical communication with a first portion18aof the energy conversion layer18. The fourth electrode is also in electrical communication with a second portion18bof the energy conversion layer18. The second, third, and fourth electrodes22,26,30are illustrated as having a longitudinal extension in a first direction A. The metal line30aruns in a second direction B, perpendicular to the first direction A, and contacts the fourth electrode30, without contacting the second and third electrodes22,26.

In operation, the phase change memory element100has first, second, third, and fourth electrodes14,22,26,30performing different functions. During the read operation of the phase change memory element100, transistors in the periphery that are electrically coupled to the first and second electrodes14,22are simultaneously turned on, and the resistive property of the phase change material layer16is read. For example, a high resistance (corresponding to an amorphous state of the phase change material layer16) may represent a data value of “1.” Conversely, a low resistance (corresponding to a crystalline state of the phase change material layer16) may represent a data value of “0.” The information is read out to peripheral circuitry, as discussed below with respect toFIGS. 7 and 18.

During the write operation of the phase change memory element100, the third and fourth electrodes26,30work in conjunction with one another to switch the state of the phase change material layer16from amorphous to crystalline or vice versa. In operation, transistors in the periphery that are electrically coupled to the third and fourth electrodes26,30are turned on to allow current to flow through the energy conversion layer18(as indicated by the arrows a, b inFIG. 2B), which heats the phase change material layer16to switch the state of the phase change material layer16.

Conventional phase change memory elements (e.g., phase change memory element1ofFIGS. 1A and 1B) typically use a large amount of current (about 1×1012A/m2) that flows from the first electrode2through the phase change material layer8and to the second electrode4for both the write and read operations. The phase change memory element100ofFIGS. 2A and 2Breduces the amount of current that flows through the phase change material layer16by providing the energy conversion layer18in association with third and fourth electrodes26,30to switch the state of the phase change material layer16, rather than applying a current directly through the phase change material layer16. Additionally, the current required to activate the energy conversion layer18can be much lower than the current necessary to change the phase of the phase change material layer16if the current were flowing directly through the phase change material layer16. Accordingly, the overall current requirements for the phase change cell100are reduced.

During the read operation of the phase change memory element100, the current flow (through the first and second electrodes14,22) required to read the resistive state of the phase change material layer16is minimal as compared to that of writing to the phase change material layer16. Therefore, by having separate mechanisms for the read and write operations of the phase change memory element100, the amount of current that flows directly through the phase change material layer16is substantially reduced, which results in reduced reliability issues such as the electromigration of atoms of the phase change material, as discussed above with respect toFIGS. 1A and 1B.

It should be noted that the phase change memory element100is only an example, and is not intended to be limiting in any way. For example, a low resistance state of the phase change material layer16may correspond to a data value of “0”; whereas a high resistance state of the phase change material layer16may correspond to a data value of “1,” and the shapes of the phase change material layer16and energy conversion layer18can have a top-down shape other than circular.

FIGS. 3A-6Billustrate a method of fabricating the phase change memory element100illustrated inFIGS. 2A and 2B. No particular order is required for any of the actions described herein, except for those logically requiring the results of prior actions. Accordingly, while the actions below are described as being performed in a specific order, the order is an example only and can be altered if desired. Although the formation of a single phase change memory element100is shown, it should be appreciated that the phase change memory element100can be one memory element in an array of memory elements, which can be formed concurrently.

FIGS. 3A and 3Billustrate a partial cross sectional view and a partial top down view, respectively, of an intermediate structure100a. The intermediate structure100ais formed by providing a first dielectric layer12over a substrate10. The first dielectric layer12is typically etched to create vias24(FIG. 2B) within which a first electrode14is formed by blanket deposition and then chemical mechanical polishing (CMP) to the surface of the first dielectric layer12. The first electrode14can be formed of any suitable conductive material, such as titanium nitride (TiN), titanium aluminum nitride (TiAlN), titanium tungsten (TiW), platinum (Pt) or tungsten (W), among others.

The phase change material layer16is formed by deposition and patterning of a conformal or a partially conformal phase change material over the first dielectric layer12. The deposited phase change material could be a chalcogenide material, such as, for example, germanium-antimony-tellurium or germanium-telluride layer. The phase change materials could also include other phase change materials such as, for example, GeTe, In—Se, Sb2Te3, GaSb, InSb, As—Te, Al—Te, Ge—Sb—Te, Te—Ge—As, In—Sb—Te, Te—Sn—Se, Ge—Se—Ga, Bi—Se—Sb, Ga—Se—Te, Sn—Sb—Te, In—Sb—Ge, Te—Ge—Sb—S, Te—Ge—Sn—O, Te—Ge—Sn—Au, Pd—Te—Ge—Sn, In—Se—Ti—Co, Ge—Sb—Te—Pd, Ge—Sb—Te—Co, Sb—Te—Bi—Se, Ag—In—Sb—Te, Ge—Sb—Se—Te, Ge—Sn—Sb—Te, Ge—Te—Sn—Ni, Ge—Te—Sn—Pd, and Ge—Te—Sn—Pt.

The phase change material layer16could be patterned to have a substantially disk like top down shape (seeFIG. 3B) having sloped sidewall regions16bto improve the step coverage of the material element deposition, discussed below. It should be noted that the sloped sidewalls16bare optional, and that the sidewalls16bof the phase change material layer16could be vertical relative to a top surface of the first electrode14, linear, non-linear, bowed, sloped such that a top surface of the phase change material layer16has a greater surface area than that of a bottom surface, or any other desired shape. The phase change material layer16could have a metal layer over the top for better electrical contact.

A material element17is formed on an upper surface16aand sidewall regions16bof the phase change material layer16. The material element17self-aligns over the surfaces of the phase change material layer16when deposited. The self-alignment over the phase change material layer16ensures that the phase change material layer16is electrically isolated from the subsequently deposited energy conversion layer18(FIGS. 4A and 4B). The self-alignment of the material layer17with the phase change material layer16may simplify the processing and fabrication of the overall phase change memory element100(FIGS. 2A and 2B), and may also increase throughput. The material element17could be formed of any insulating material such as, but limited to, silicon nitrides; alumina oxides; oxides; high temperature polymers; low dielectric constant materials; insulating glass; or insulating polymers.

FIGS. 4A and 4Billustrate a further step in the fabrication of the phase change memory element100illustrated inFIGS. 2A and 2B. As illustrated, the energy conversion layer18is formed on sidewall regions17bof the material element17. The energy conversion layer18self-aligns over the sidewall regions17bof the material layer17when deposited. The self-alignment over the material layer17simplifies the processing and fabrication of the overall phase change memory element100(FIGS. 2A and 2B), and also increases fabrication throughput.

Although the energy conversion layer18is not formed over an upper surface17aof the material element17, it is not limiting in any way. For example, the energy conversion layer18could be formed over the upper surface17aof the material element17; the energy conversion layer18, however, should be electrically isolated from the phase change material layer16and the second electrode22(FIGS. 2A and 2B) for proper operation. A portion of the material layer17is subsequently etched such that the subsequently formed second electrode22(FIGS. 5A and 5B) is in electrical connection with the phase change material layer16.

FIGS. 5A and 5Billustrate the deposition of the second dielectric layer20over the upper surface17aof the material element17and the first and second regions18a,18bof the energy conversion layer18. The second dielectric layer20is subsequently etched to create first and second vias29a,29btherein. A portion of the upper surface17aof the material element17above the phase change material layer16is also removed such that the first via29aextends to the phase change material layer16. Second and third electrodes22,26fill the first and second vias29a,29bformed within the second dielectric layer20. The second electrode22is formed such that it extends to the phase change material layer16and, thereby, in electrical communication with the phase change material layer16. The second and third electrodes22,26can be formed of any suitable conductive material, such as titanium nitride (TiN), titanium aluminum nitride (TiAlN), titanium tungsten (TiW), platinum (Pt) or tungsten (W), among others.

The second via29bis formed to extend to the first portion18aof the energy conversion layer18. The third electrode26is formed within the second via29bto extend to the first portion18aof the energy conversion layer18such that the third electrode26is in electrical communication with the first portion18aof the energy conversion layer18. A third dielectric layer28is formed over the second dielectric layer20. Contacts22a,26aare formed within the third dielectric layer28as part of the second and third electrodes22,26, respectively. The contacts22a,26aare formed to extend in the first direction A, which is substantially perpendicular to the second direction B. The contacts22a,26aallow electrical communication to peripheral circuitry, including transistors that are activated for either read and/or write operations of the phase change memory element100(FIGS. 2A and 2B), as discussed below with respect toFIG. 7.

FIGS. 6A and 6Billustrate the deposition of the fourth dielectric layer32over the third dielectric layer28. The third via29cis formed to extend from an upper surface of the fourth dielectric layer30to the second portion18bof the energy conversion layer18. The third via29cis subsequently filled with a conductive material to form the fourth electrode30. The fourth electrode30can be formed of any suitable conductive material, such as titanium nitride (TiN), titanium aluminum nitride (TiAlN), titanium tungsten (TiW), platinum (Pt) or tungsten (W), among others. The fourth electrode30should be formed to be electrically isolated from the first, second, and third electrodes14,22,26, and should be in electrical communication with the second portion18bof the energy conversion layer18. As illustrated, a metal line30ais formed over the fourth dielectric layer32, and is in electrical communication with the fourth electrode30. The metal line30ais formed to extend in the second direction B, which is substantially perpendicular to the first direction A. The metal line30aallows electrical communication to peripheral circuitry, including a transistor that is activated for the write operations of the phase change memory element100(FIGS. 2A and 2B), as discussed below with respect toFIG. 7.

FIG. 7illustrates a partial top-down view of an array of phase change memory elements100(illustrated in detail inFIGS. 2A and 2B). The first, second, third, and fourth electrodes14,22,26,30are illustrated schematically, as are first, second, third, and fourth transistors42,44,46,48, respectively; only the phase change material layer16, material element17, and energy conversion layer18of the phase change memory element100are illustrated, for the sake of clarity. In the read operation of the phase change memory element100, the first transistor42is activated to allow current to pass through the first electrode14and the phase change material layer16; the second transistor44is also activated to allow the current to pass from the phase change material layer16through the second electrode22, and the resistance level of the phase change material layer16is read out to a sense amplifier49, which senses the signal associated with the resistance of the phase change cell100.

In the write and/or erase operation, the third transistor46is activated to allow current to pass through the third electrode26and the first portion18a(FIG. 2A) of the energy conversion layer18. The current is allowed to pass from the first portion18a(FIG. 2A) of the energy conversion layer18to the second portion18b(FIG. 2A) of the energy conversion layer18. The current flows through the fourth electrode30when the fourth transistor48is activated. The current flowing from the third electrode26through the energy conversion layer18and out through the fourth electrode30heats up the energy conversion layer18, which can change the phase of the phase change material layer16formed within the energy conversion layer18.

As discussed above with respect toFIGS. 2A and 2B, the current that flows through the phase change material layer16is substantially reduced for programming (phase change) operations in comparison to conventional phase change memory elements (e.g., phase change memory element1ofFIGS. 1A and 1B), which is desired.

FIG. 8illustrates a partial top-down view of an array of phase change memory elements100′ constructed in accordance with a second embodiment of the invention. TheFIG. 8phase change memory element100′ includes the components of phase change memory element100(FIG. 7) with the addition of a diode50(schematically illustrated) between the fourth electrode and the energy conversion layer18. The diode50serves to further isolate the energy conversion layer18from adjacent phase change memory elements100′.

FIGS. 9A and 9Billustrate a partial cross-sectional view and a partial top-down view, respectively, of a phase change memory element200constructed in accordance with another embodiment of the invention. The phase change memory element200is substantially similar to the phase change memory element100illustrated inFIGS. 2A and 2B; the components contained therein, however, have a different configuration within the phase change memory element200.

The phase change memory element200includes a substrate210and a first dielectric layer212having a first electrode214formed therein. An insulating material element217is formed over the first dielectric layer212. A second dielectric layer220, a second electrode230, a third dielectric layer228, a fourth dielectric layer232having a third electrode226formed therein, and a fifth dielectric layer240are all formed over the insulating material element217(at different levels of processing). A fourth electrode222is formed over the fifth dielectric layer240.

A phase change material layer216, a portion of the material element217, and a energy conversion layer218are all contained within a via215such that the phase change material layer216is in electrical communication with both the first and fourth electrodes214,222. The energy conversion layer218surrounds the phase change material layer216in the via215, and portions of the insulating material element217electrically isolate the energy conversion layer218and the phase change material layer216.

FIGS. 10A-14illustrate a method of fabricating the phase change memory element200illustrated inFIGS. 9A and 9B. No particular order is required for any of the actions described herein, except for those logically requiring the results of prior actions. Accordingly, while the actions below are described as being performed in a specific order, the order is an example only and can be altered if desired. Although the formation of a single phase change memory element200is shown, it should be appreciated that the phase change memory element200can be one memory element in an array of memory elements, which can be formed concurrently.

FIGS. 10A and 10Billustrate partial cross-sectional and top-down views of an intermediate structure200a. The intermediate structure200ais formed by forming the first dielectric layer212over the substrate210, and subsequently forming the first electrode214within the first dielectric layer212. The material element217, second dielectric layer220, second electrode230, third dielectric layer228, and fourth dielectric layer232are successively deposited over the first dielectric layer212(at different levels of processing). The fourth dielectric layer232is etched to create trench within which the third electrode226is formed. A fifth dielectric layer240is formed over the fourth dielectric layer232after the third electrode226is deposited.

The second and third electrodes230,226are formed substantially perpendicular to one another, as illustrated inFIG. 10B. The illustrated third electrode226extends in a first direction A; whereas the second electrode230extends in a second direction B.

FIG. 11illustrates a cross-sectional view of theFIG. 10Aintermediate structure200asubsequent to having a via241formed therein; the via241is formed such that portions of the material element217, the first electrode214and each of the second and third electrodes230,226are exposed within the via241.

FIG. 12illustrates the deposition of the energy conversion layer218over the sidewall portions of the via241. The energy conversion layer218self-aligns with the sidewall portions of the via241. The self-alignment may reduce fabrication costs, and increase throughput.

FIG. 13illustrates a further etching step removing a portion of the exposed material element217to extend the via241to the first electrode214, and the deposition of additional material elements217athat self-aligns with the energy conversion layer218. The material elements217aalso encapsulate the energy conversion layer218previously formed on the sidewall regions of the via241.

FIG. 14illustrates the deposition of the phase change material layer216within the via241(FIG. 13) and over a surface240aof the fifth dielectric layer240. The phase change material layer216is deposited over the sidewall regions of the insulating material element217within the via241(FIG. 13), and in electrical communication with the first electrode214formed within the first dielectric layer212. The phase change material layer216self-aligns with the first electrode214. The phase change material layer216over the surface240aof the fifth dielectric layer240is planarized, and a fourth electrode222(FIG. 9A) is deposited over the fifth dielectric layer240such that the fourth electrode222(FIG. 9A) is in electrical communication with the phase change material layer216.

Referring again toFIGS. 9A and 9B, the phase change memory element200operates in a substantially similar way as the phase change memory element100illustrated inFIGS. 2A and 2B. During the read operation of the phase change memory element200, transistors in the periphery that are electrically coupled to the first and fourth electrodes214,222are simultaneously turned on, and the resistive property of the phase change material layer216is read. For example, a high resistance (corresponding to an amorphous state of the phase change material layer216) may represent a data value of “1.” Conversely, a low resistance (corresponding to a crystalline state of the phase change material layer16) may represent a data value of “0.” The information is read out to peripheral circuitry, as discussed above with respect toFIG. 7.

During the write operation of the phase change memory element200, the second and third electrodes230,226work in conjunction with one another to switch the state of the phase change material layer216from amorphous to crystalline or vice versa. In operation, transistors in the periphery that are electrically coupled to the second and third electrodes230,226are turned on to allow current to flow through the energy conversion layer218(as indicated by the arrows inFIG. 9B), which heats the phase change material layer216to switch its state.

It should be noted that the phase change material layer216need not be planarized prior to the deposition of the fourth electrode222(FIG. 9A). For example,FIG. 15illustrates a phase change memory element200′ constructed in accordance with another embodiment of the invention. As illustrated, phase change material layer216′ is formed within the via241(FIG. 12), and over the sidewall regions of the insulating material element217within the via241(FIG. 11) and the surface240a(FIG. 14) of the fifth dielectric layer240. The fourth electrode222is deposited over the phase change material layer216′. The operation of theFIG. 15phase change memory element200′ is substantially similar to the operation of the phase change memory element200.

FIGS. 16A and 16Billustrate a phase change memory element300constructed in accordance with another embodiment of the invention. The phase change memory element300is substantially similar to the phase change memory element illustrated inFIGS. 9A and 9B; the phase change memory element300, however, has the energy conversion layer218, material element217, and phase change material layer216formed within a via241(FIG. 11) located within the second and third electrodes230′,226′, respectively. The placement of the energy conversion layer218within the second and third electrodes230′,226′, may increase the efficiency by which the current passes through the energy conversion layer218, which may reduce the power consumption necessary for the write/erase operation of the phase change memory element300.

FIGS. 17A and 17Billustrate a phase change memory element400constructed in accordance with yet another embodiment of the invention. The phase change memory element400includes a phase change material layer316and first, second, and third electrodes314,330,326. Other material layers within the phase change memory element400include first and second insulating material layers317a,317b, which electrically isolate the phase change material layer316from a energy conversion layer318, and electrically isolate the phase change material layer316from a third electrode326, respectively. The phase change memory element400is fabricated on a first dielectric layer312formed over a substrate310. The first electrode314is formed within the first dielectric layer312. Second and third dielectric layers320,328are also provided as insulating layers between the first electrode314and the energy conversion layer318, and the energy conversion layer318and the phase change material layer316, respectively.

A via is formed within the energy conversion layer318and second and third dielectric layers320,328, which extends to the first electrode314. The first insulating material layer317ais formed on sidewall portions of the via extending to the first electrode314. The phase change material layer316is subsequently formed between the first insulating material layer317aformed in the via such that it is in electrical communication with the first electrode314. The phase change material layer316is also patterned over a surface of the third dielectric layer328such that it is in electrical communication with the second electrode330.

The second insulating layer317bis formed over the patterned phase change material layer316and a portion of the third dielectric material layer328not covered by the phase change material layer316. Fourth, fifth, and sixth dielectric layers332,334,336are formed over the second insulating layer317band portions of the third dielectric layer not covered by the second insulating layer317b. Previous to the formation of the fifth and sixth dielectric material layers334,336, the second electrode330is formed within a via created in the fourth dielectric layer332, second insulating layer317b, phase change material layer316, third dielectric layer328, energy conversion layer318, and the second dielectric material layer320.

The second electrode330is thereby formed in electrical communication with the energy conversion layer318and the phase change material layer316. The second electrode330is formed to extend in a first direction A (FIG. 17B), which is coupled to peripheral circuitry as discussed below with respect toFIG. 18. Subsequent to the formation of the second electrode330and the fifth and sixth dielectric material layers334,336, the third electrode326is formed within a via extending from an upper surface of the sixth dielectric material layer336to the first dielectric material layer312. The third electrode326is formed to be in electrical communication with the energy conversion layer318. The third electrode326is coupled to a metal line326athat extends in a second direction B (FIG. 17B) that is substantially perpendicular to the first direction A; the metal line326ais coupled to peripheral circuitry as discussed below with respect toFIG. 18.

During the read operation of the phase change memory element400, transistors in the periphery that are electrically coupled to the first and second electrodes314,330are simultaneously turned on, and the resistive property of a phase change material layer316is read. For example, a high resistance (corresponding to an amorphous state of the phase change material layer316) may represent a data value of “1.” Conversely, a low resistance (corresponding to a crystalline state of the phase change material layer316) may represent a data value of “0.” The information is read out to peripheral circuitry, as discussed above with respect toFIG. 7.

During the write/erase operation of the phase change memory element400, the second and third electrodes330,326work in conjunction with one another to switch the state of the phase change material layer316from amorphous to crystalline or vice versa. In operation, transistors in the periphery that are electrically coupled to the second and third electrodes330,326are turned on to allow current to flow through a energy conversion layer318, which heats the phase change material layer316to switch its state.

The difference between the phase change memory element400illustrated inFIGS. 17A and 17Band those discussed above (i.e.,FIGS. 2A-16B), is that the gates of the transistors in the periphery corresponding to the first and third electrodes314,326have different applied voltages, thereby having two different currents applied to the energy conversion layer318and the phase change material layer316when writing or reading. For example, the current passing through the second electrode330, the energy conversion layer318, and the third electrode326can be regulated by applying a voltage to the gate of a transistor associated with the third electrode326.

The use of three electrodes314,330,326decreases the fabrication costs associated with using four electrodes, and further reduces the number of material necessary in the fabrication of the phase change memory element400.

FIGS. 18A and 18Billustrate a phase change memory element500constructed in accordance with another embodiment of the invention. The phase change memory element500has first, second, and third electrodes414,430,426, respectively. Other material layers within the phase change memory element500include an insulating material layer417, which electrically isolates phase change material layer416from energy conversion layer418, and electrically isolates the phase change material layer416from the third electrode426. The phase change memory element500also includes material layers420,428,434, and436, which are typically interlayer dielectric material layers.

The phase change material layer416, the insulating material layer417, and the energy conversion layer418are self-aligned with the first electrode414. The self-alignment may simplify the processing and fabrication of the overall phase change memory element500.

During the read operation of the phase change memory element500, transistors in the periphery that are electrically coupled to the first and second electrodes414,430are simultaneously turned on, and the resistive property of a phase change material layer416is read. For example, a high resistance (corresponding to an amorphous state of the phase change material layer416) may represent a data value of “1.” Conversely, a low resistance (corresponding to a crystalline state of the phase change material layer416) may represent a data value of “0.” The information is read out to peripheral circuitry, as discussed above with respect toFIG. 7.

During the write/erase operation of the phase change memory element500, the second and third electrodes430,426work in conjunction with one another to switch the state of the phase change material layer416from amorphous to crystalline or vice versa. In operation, transistors in the periphery that are electrically coupled to the second and third electrodes430,426are turned on to allow current to flow through a energy conversion layer418, which heats the phase change material layer416to switch its state.

Although the phase change memory element500is substantially similar to the phase change memory element400ofFIGS. 17A and 17B, the second electrode430is placed directly upon the phase change material layer416, thereby resulting in a more efficient current transfer, and the energy conversion layer318surrounds the phase change material layer316resulting in more efficient heat transfer. The phase change memory element500is formed in substantially the same manner discussed above with respect toFIGS. 2A-6B.

To conserve the amount of phase change material used in the phase change material element500, a spacer structure520could be used as illustrated inFIGS. 19A and 19B. Phase change material element500ais constructed in accordance with yet another embodiment of the invention. The phase change material element500ahas a spacer structure520that is formed within, and surrounded by, phase change material layer416a. By using the spacer structure520, the volume of phase change material can be significantly reduced in comparison to the phase change material element500illustrated inFIGS. 18A and 18B. Accordingly, the current necessary to change phase of the programmable volume of phase change material layer416afrom amorphous to crystalline is decreased due to the decreased volume of phase change material. Another feature of the illustrated phase change material element500ais the reduced contact area between the phase change material layer416aand first and second electrodes414,430, which also reduces the current necessary to change phase of the programmable volume of phase change material layer416afrom amorphous to crystalline.

The spacer structure520is typically formed of a nitride material; the spacer structure, however, could be formed of any insulating material such as, but not limited to, silicon nitrides; alumina oxides; oxides; high temperature polymers; low dielectric materials; insulating glass; or insulating polymers. It should be noted that the illustrated phase change material element500acould have a configuration in which the energy conversion layer418and the phase change material layer416acould be switched wherein the energy conversion layer418is in electrical contact with the first and second electrodes414,430, and the phase change material layer416ais in electrical contact with second and third electrodes430,426. In the alternate configuration, the phase change material layer416awould be distal to the spacer structure520, and the energy conversion layer418would be proximal to the spacer structure520. The alternate configuration could be applied to any of the foregoing and following phase change memory elements ofFIGS. 2A-21.

FIGS. 20A and 20Billustrate another embodiment of the of the invention. Phase change memory element500bis substantially similar to the phase change memory element500a, with the exception that the phase change memory element500bhas a phase change material layer over a conductive spacer structure520b. The conductive spacer structure520bcould be formed of any conductive material layer, such as titanium nitride (TiN), titanium aluminum nitride (TiAlN), titanium tungsten (TiW), platinum (Pt) or tungsten (W), among others. Additionally, it should be noted that the first electrode414could be formed such that it has a top surface that extends above the top surface of the first dielectric layer412. As illustrated inFIG. 20A, the phase change material layer416bis formed in contact with the second electrode430; however, the illustration is not intended to be limiting. For example, the phase change material layer416bcould be in contact with the first electrode414, and the spacer structure520bcould be in contact with the second electrode430. It should also be noted that the phase change material layer416bcould be formed between two spacer structures, each spacer structure contacting the first and second electrodes414,430, whereby the phase change material layer416bis not in contact with either of the first and second electrodes414,430.

FIG. 21illustrates a phase change memory element600constructed in accordance with yet another embodiment of the of the invention. The phase change memory element600includes first, second, and third electrodes514,530,526, respectively. As illustrated, the first and third electrodes514,526are formed within substrate512, which is formed over substrate310. A phase change material layer516is formed in electrical communication with the first electrode514. The phase change material layer516surrounds a spacer structure620, which allows for the reduction of the phase change material required to form phase change material layer516, the features of which are explained above with respect toFIGS. 19A-20B. The phase change material layer516is also formed in electrical communication with the second electrode530.

An insulating material layer517is formed in a self-aligning manner on the sidewall regions of the phase change material layer516. The insulating material layer517insulates the phase change material layer516from a energy conversion layer518that is formed in a self-aligning manner on the sidewall regions of the insulating material layer517. The energy conversion layer518is formed such that it is in electrical communication with the second and third electrodes530,526.

During the read operation of the phase change memory element600, transistors in the periphery that are electrically coupled to the first and second electrodes514,530are simultaneously turned on, and the resistive property of a phase change material layer516is read. For example, a high resistance (corresponding to an amorphous state of the phase change material layer516) may represent a data value of “1.” Conversely, a low resistance (corresponding to a crystalline state of the phase change material layer516) may represent a data value of “0.” The information is read out to peripheral circuitry, as discussed above with respect toFIG. 7.

During the write/erase operation of the phase change memory element600, the second and third electrodes530,526work in conjunction with one another to switch the state of the phase change material layer516from amorphous to crystalline or vice versa. In operation, transistors in the periphery that are electrically coupled to the second and third electrodes530,526are turned on to allow current to flow through a energy conversion layer518, which heats the phase change material layer516to switch its state.

FIG. 22illustrates a simplified processor system900which includes a memory circuit901having a phase change memory element100constructed in accordance with the invention as described above with respect to the embodiments illustrated inFIGS. 2A-21(e.g., phase change memory element100,100′,200,200′,300,400,500,500a,500b,600). Without being limiting, such a system could include a computer system, camera system, scanner, machine vision, vehicle navigation, video phone, surveillance system, auto focus system, star tracker system, motion detection system, image stabilization system, and other systems employing memory.

The processor system900, which can be any system including one or more processors generally comprises a central processing unit (CPU)902, such as a microprocessor, a digital signal processor, or other programmable digital logic devices, which communicates with an input/output (I/O) device906over a bus904. The memory circuit901communicates with the CPU902over bus904typically through a memory controller.

In the case of a computer system, the processor system900may include peripheral devices such as a compact disc (CD) ROM drive910, which also communicate with CPU902and hard drive905over the bus904. Memory circuit901is preferably constructed as an integrated circuit, which includes a memory array903having at least one phase change memory element100according to the invention. If desired, the memory circuit901may be combined with the processor, for example CPU900, in a single integrated circuit.

The above description and drawings are only to be considered illustrative of examples of embodiments, which achieve the features of the embodiments of the present invention. Modification and substitutions to specific process conditions and structures can be made without departing from the spirit and scope of the present invention. Accordingly, the invention is not to be considered as being limited by the foregoing description and drawings, but is only limited by the appended claims.