Retention detection and/or channel tracking policy in a flash memory based storage system

A method for determining a retention time in a solid state device (SSD), comprising the steps of providing a plurality of write operations to a memory, determining a reference voltage for each of the write operations, determining a difference between (i) the reference voltage after each of the write operations and (ii) a target reference voltage and if the difference is above a predetermined value, generating a flag indicating an excessive retention has occurred.

FIELD OF THE INVENTION

The invention relates to memory devices generally and, more particularly, to a method and/or apparatus for implementing a retention detection and/or channel tracking policy in a flash memory based storage system.

BACKGROUND

Conventional NAND flash memory cells use a floating gate transistor that stores data in a non-volatile fashion by holding a certain amount of electric charge in the floating gate. After a memory cell is programmed, as time goes by, the floating gate gradually loses its charge due to oxide leakage and charge detrapping. Data retention changes the distribution of threshold voltages Vt of the programmed states. Severe data retention changes can lead to read errors. In a flash memory based storage system, such as a solid state drive (SSD), it is important to avoid and/or handle errors caused by retention. Retention is a function of time and temperature. The longer the data stays in the memory without being re-written, the larger the retention effect. The higher the temperature, the larger the retention effect. Retention also becomes more pronounced as flash memory wears. As flash memory technology scales further towards sub-20 nm, and provides an increasing number of bits per cell (MLC, TLC, etc.), controlling retention becomes more challenging. For some applications, such as a SSD drive, retention time on a conventional flash memory can be longer than the maximum retention time specified by memory manufacturers.

SUMMARY

The invention concerns a method for determining a retention time in a solid state device (SSD), comprising the steps of providing a plurality of write operations to a memory, determining a reference voltage for each of the write operations, determining a difference between (i) the reference voltage after each of the write operations and (ii) a target reference voltage and if the difference is above a predetermined value, generating a flag indicating an excessive retention has occurred.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Embodiments of the invention include a method and/or apparatus for providing a retention detection and channel tracking policy that may (i) be used in flash memory based storage systems, (ii) provide a signal processing based approach, (iii) be implemented without tracking time or temperature, (iv) counteract a retention effect that is PEC dependent, (v) provide a DSP based approach, (vi) be integrated with existing channel/VREF tracking procedures, (vii) be implemented with a minimal computational overhead, and/or (viii) be implemented with a low storage overhead.

Referring toFIG. 1, a block diagram of an example apparatus50is shown. The apparatus50generally comprises a block (or circuit)60, a block (or circuit)70and a block (or circuit)80. The circuit70may include a circuit90. The circuit90may be a memory configured to store computer instructions (or firmware). The instructions, when executed, may perform a number of steps. The firmware90may include a tracking module100(to be described in more detail in connection withFIGS. 5 and 6).

A signal (e.g., REQ) may be generated by the circuit60.

The signal REQ may be received by the circuit70. The signal REQ may be a request signal that may be used to access data from the circuit80. A signal (e.g., I/O) may be generated by the circuit70to be presented to/from the circuit80. The signal REQ may include one or more address bits. A signal (e.g., DATA) may be one or more data portions received by the circuit80.

The circuit60is shown implemented as a host circuit. The circuit70reads and writes data to and from the circuit80. The circuit80is generally implemented as a nonvolatile memory circuit. The circuit80may include a number of modules90a-90n. The modules90a-90nmay be implemented as NAND flash chips. In some embodiments, the circuit80may be a NAND flash device. In other embodiments, the circuit70and/or the circuit80may be implemented as all or a portion of a solid state drive having one or more nonvolatile devices. The circuit80is generally operational to store data in a nonvolatile condition. When data is read from the circuit80, the circuit70may access a set of data (e.g., multiple bits) identified in the signal REQ.

In some embodiments, the circuit80may be implemented as a single-level cell (e.g., SLC) type circuit. An SLC type circuit generally stores a single bit per memory cell (e.g., a logical 0 or 1). In other embodiments, the circuit80may be implemented as a multi-level cell (e.g., MLC) type circuit. An MLC type circuit is generally capable of storing multiple (e.g., two) bits per memory cell (e.g., logical 00, 01, 10 or 11). In still other embodiments, the circuit80may implement a triple-level cell (e.g., TLC) type circuit. A TLC circuit may be able to store multiple (e.g., three) bits per memory cell (e.g., a logical 000, 001, 010, 011, 100, 101, 110 or 111).

Embodiments of the invention provide a method for detecting long retention. A VREF/channel tracking policy tracks pre-defined values of program/erase counts (PEC). The VREF parameter is tracked immediately after a program operation is stored, and used for retention detection. During retention detection, tracking is done and the result of the value of the signal VREF is compared to the stored value of the signal VREF immediately after programming. If the drift of the voltage threshold Vt is larger than a predefined threshold, a long retention is detected. In one example, when a long retention has been detected, a flag may be set. Other types of indications to the controller90may be used to indicate that a long retention has been detected.

An optimal value for the signal VREF may be determined for a particular read operation. A dedicated procedure may be performed, generally called a retention test. A comparison of the value of the signal VREF may be made to the result to the value found immediately after the last erase/program operation is performed. If the signal VREF drifts down by a large amount, a long retention is detected. The retention detection leverages the results of the existing channel tracking module. An adjustment may be made on how the channel tracking procedure is triggered and/or how the optimal values of the signal VREF are stored. The adjustment may enable effective retention detection.

In general, the controller70may include an erase/program unit implemented in an R-block configuration. For example, multiple blocks may be read from multiple dies90a-90n. Channel tracking of the signal VREF and/or the retention detection unit is also included in the R-block configuration. The erase/program unit may be implemented as part of the firmware90. The channel tracking module100may track a distribution of the voltage threshold Vt for different states. Various channel parameters can be tracked, such as voltage threshold Vt mean, voltage threshold Vt variance, and/or optimal values of the signal VREF.

Referring toFIG. 2, a more detailed diagram of the controller70is shown. The controller70generally comprises a block (or circuit)82, block (or circuit)84, block (or circuit)86, block (or circuit)88, block (or circuit)90, block (or circuit)92, and a block (or circuit)100. The circuit82may be implemented as a host interface. The circuit84may be implemented as a buffer. The circuit86may be implemented as a decoder, such as an error correction (ECC) decoder. The circuit88may be implemented as a processor, such as a backend processor. The circuit90may be implemented as a processor, such as a digital signal processor (DSP). The circuit92may be implemented as an interface circuit, such as a flash interface circuit. The circuit100may be implement as a channel tracking/VREF tracking module.

Referring toFIG. 3, a diagram illustrating a retention effect of a voltage threshold distribution is shown. The solid lines and the dashed lines represent the distributions of the voltage threshold Vt after and before a retention period.

Referring toFIG. 4, a diagram showing values of the reference voltages signal VREF used in a MLC flash memory during a read operation is shown. The voltage VREF_B is used for lower page reads. The voltage VREF_A and the voltage VREF_C are used for upper page reads. The tracking module100finds the optimal values of the signal VREF to be used in hard-decision reads for the R-block. The particular criterion for determining an optimal value can vary to meet the design criteria of a particular implementation. The most typical criterion is to minimize the raw bit error rate. An example of a tracking process can be found in co-pending patent Ser. No. 13/464,433, the appropriate sections of which are incorporated by reference.

Since the distribution of the threshold voltage Vt changes with a number of factors (e.g., PE cycling, retention, read disturb, etc.), the optimal value for the signal VREF also changes. The tracking module100can choose to initiate the VREF tracking procedure whenever necessary and then store the optimal values for the signal VREF. However, for retention test purposes, access to the optimal value of the signal VREF tracked immediately after the program operation may be used.

Referring toFIG. 5, a table illustrating a format to store the value of the reference voltage parameter VREF is shown. The voltage VREF_CUR is shown representing the value of the signal VREF that is most recent for the tracked R-block. The voltage of a parameter VREF_ORG (e.g., a target reference voltage) is shown tracked immediately after programming.

In one example, the parameter VREF_ORG can be one value of the signal VREF (e.g., VREF_B) or, in another example, multiple values (e.g., VREF_B and VREF_C). The parameter VREF_ORG is a reference value used by the retention test to detect a long retention. The parameter VREF_ORG is also a reference value used by the tracking module100to determine whether the tracking procedure needs to be triggered. For example, a new erase/program operation may eliminate any retention and/or read disturb effect and/or potentially changes the value of the signal VREF. To trigger tracking after programming each R-block is generally inefficient. The voltage VREF_ORG of the module100may be used to reduce the frequency of how often the tracking procedure is invoked.

Referring toFIG. 6, a flow diagram of a method (or process)200illustrating a proposed policy for VREF/channel tracking after programming an R-block is shown. The method200generally comprises a step (or state)202, a decision step (or state)204, a step (or state)206, a step (or state)208, a step (or state)210, a decision step (or state)212, a step (or state)214, and a step (or state)216. The state202may be entered after programming an entire R-block. Next, the method200moves to the decision state204. The decision state204sets a number of values. The decision state204determines whether the value PEC is equal to an initial value after manufacturing (e.g., 1), or whether the value PEC equals some other predefined values. If not, the method200moves to the state206. If so, the method200moves to the state208. In the state206, the method200retrieves current VREF parameters of an R-block. Next, the method200moves to the state210. The state210retrieves the value VREF_CUR stored in the area of parameters. The state210compares the current value to the stored channel parameters. The state210compares to the value VREF_ORG. Next, the method200moves to the decision state212. The decision state212compares an absolute value of the value VREF_CUR minus VREF_ORG. If this absolute value is greater than a threshold, then the method200moves to the state208. If not, the method200moves to the state216. In the state208, the method200immediately starts tracking the channel for the R-block. Next, the method200moves to the state214, that updates the channel parameters.

The pre-defined PEC (program/erase count) values used to trigger tracking can be based on absolute numbers, such as 100, 200, 300, . . . , or as a percentage of device life, such as 10%, 20%, 25%, 30%, . . . of the device life. The values can be equally spaced or unequally spaced throughout the life of the device.

When the PEC is not at one of a number of pre-defined values, tracking is only triggered when there is a non-trivial difference between the signal VREF_ORG and the signal VREF_CUR. The difference can be measured based on a value of the signal VREF (e.g., VREF_B) or averaged over multiple values of the signal VREF.

Referring toFIG. 7, a tracking policy (or method)300for the signal VREF is shown. The method300implements a retention test method/flow for stored parameter VREF_ORG. The method300generally comprises a step (or state)302, a step (or state)304, a step (or state)306, a step (or state)308, a decision step (or state)310, a step (or state)312, a step (or state)314, and a step (or state)316. The step302generally starts a retention test on a given R-block. Next, the state304applies the tracking process to estimate the optimal value VREF for the R-block. Next, the state306sets a value VT_DRIFT as equal to the value VREF_ORG minus the value VREF_CUR_AW. The state308obtains the value VREF_ORG from the stored VREF parameters. Next, the decision state310determines whether a drift in the voltage threshold Vt is larger than a predefined threshold. If so, the method300moves to the state312. If not, the method300moves to the state314. In the state312, the method300declares a long retention as being detected. In the state314, the method300declares a long retention as not being detected. The state316ends the retention test in a given block.

The retention test procedure is normally invoked on an R-block level. The tracking method200and/or300is called to obtain the current optimal value of the signal VREF (e.g., VREF_CUR_NEW) and compared against the original value of the signal VREF (e.g., VREF_ORG). To save the time spent in retention test, the controller70can choose to track a particular one of the values VREF (e.g., VREF_B). Storing the parameter VREF_ORG also reduces the frequency of calling tracking procedures.

The criterion for determining a long retention can be PEC independent. For example, the controller70can choose a “Vt drift threshold” based on various decoder requirements. At the minimum, one VREF_ORG value needs to be stored for each tracking granularity.