Interconnection of semiconductor devices in extreme environment microelectronic integrated circuit chips

A process of fabrication and the resulting integrated circuit device is made of patterned metal electrical interconnections between semiconductor devices residing on and forming extremely harsh environment integrated circuit chips. The process enables more complicated wide band gap semiconductor integrated circuits with more than one level of interconnect to function for prolonged time periods (over 1000 hours) at much higher temperatures (500 C).

FIELD OF THE INVENTION

The invention is in the field of semiconductor devices. In particular, wide band gap semiconductor integrated circuits for use in high temperature and prolonged time period applications.

BACKGROUND

Extending the operating temperature of useful transistor integrated circuits (ICs) well above the effective 300 C limit of silicon-on-insulator technology is expected to enable important improvements to aerospace, automotive, energy production, and other industrial systems. It is difficult to achievestable IC operation over prolonged time periods (e.g. many thousands of hours) at high temperature. Transistors can be implemented using wide band gap semiconductors and have demonstrated the ability to function at 500 Celsius (C). For example, silicon carbide (SiC) or ICs formed by microlithographically interconnecting these transistors on a single semiconductor chip. However, these demonstrations have been limited in either the amount of time that they can function at 500 C, or in circuit complexity. Previously, no IC has been implemented in any semiconductor material with more than 10 transistors interconnected on a single chip has demonstrated operation for more than 200 hours at 500 C.

Processes for interconnecting transistors (or other devices such as resistors) residing on a semiconductor chip using micro lithographical patterning of metal interconnects residing on insulating dielectric materials are well known to those skilled in the art.

In particular,FIG. 1illustrates a prior art “first level” interconnect that is implemented in microscopic dimensions. The first level interconnect electrically connects semiconductor device102with semiconductor device104wherein both devices reside on the same semiconductor chip106. A dielectric layer108overlying on both devices provides for electrical insulation or isolation from other devices and from overlying electrically conductive interconnect metal. At selected locations, patterned vias through the dielectric layer108are formed to enable subsequent deposition of conductive metal110to physically and electrically contact each semiconductor device102,104. The patterning of both vias and interconnect metal112is such that semiconductor device102and semiconductor device104become electrically interconnected for desired circuit functionality while providing device isolation from other circuit elements (devices and/or interconnects) according to the intended circuit design. For more complicated IC's these vias are generally small, yet within that small area provide for sufficient electrical conduction to the semiconductor devices102,104(i.e, form sufficiently low-resistance ohmic contact to the semiconductor device, known in the art).

Conventional IC chips operating at temperatures less than 125 C (such as chips in cell phones and computers) can contain over a million interconnections that are small, and function reproducibly and reliably. However, the prior-art materials and processing ICs used for temperatures less than 125 C cannot reproducibly and reliably withstand 500 C extreme temperatures.FIG. 2illustrates a prior art addition of a second dielectric layer200to create a second interconnect202that electrically connects to the first interconnect112through second via204, that is then over coated by a protective third dielectric layer206.

BRIEF DESCRIPTION

This brief description is provided to introduce a selection of concepts in a simplified form that are described below in the detailed description. This brief description is not intended to be an extensive overview of the claimed subject matter, identify key factors or essential features of the claimed subject matter, nor is it intended to be used to limit the scope of the claimed subject matter.

As discussed above, a process of making patterned metal electrical interconnections between semiconductor devices residing on and forming extremely harsh environment integrated circuit chips for accomplishing prolonged operation in such harsh environment for ICs comprised of more than 10 transistors has not previously existed. The process and device described herein enables more complicated (e.g., over 10 transistors) wide band gap semiconductor integrated circuits with more than one level of interconnect that functions for prolonged time periods (e.g. over 1000 hours) and at much higher temperatures (e.g. temperatures greater than or equal to 500 C) than previously achieved.

The innovation disclosed and claimed herein, in one aspect thereof, comprises systems and fabrication methods of an integrated circuit device. A first semiconductor device and a second semiconductor device are deposited (e.g. constructed) on the substrate using semiconductor processing. A first insulating layer is deposited that covers substantially the first semiconductor device, the second semiconductor device, and the substrate and its lateral extent (substrate lateral area). A patterned photoresist is deposited and patterned over the first insulating layer. The patterned photoresist defines a pattern for a first via to the first semiconductor device through the first insulating layer and a second via for the second semiconductor device through the first insulating layer. The first via and the second via is etched through the first insulating layer using the patterned photoresist as an etch mask that confines etching of the first insulating layer to occur only in regions where there is no overlying photoresist. Except for small-dimension lateral over-etch to be described, the first insulating layer is preserved (not etched) in regions directly beneath photoresist.

A contact metal layer is deposited onto the substrate lateral area including the first semiconductor device and the second semiconductor device and regions with patterned photoresist. A protective layer is deposited onto the substrate lateral area including the contact metal layer and regions with the patterned photoresist. When the patterned photoresist is removed (e.g. using a liquid chemical solvent dissolution process) along with the metals that resided on top of the photoresist, the contact metal layer and protective layer remain in regions on the first and second semiconductor devices where there was no overlying photoresist at the time that contact metal layer and protective layers were deposited. A first interconnect metal layer is deposited and patterned. The first interconnect metal layer electrically connects the first semiconductor device to the second semiconductor device via the contact metal layer and the protective layer.

A second insulating layer is deposited over the substrate lateral area including first interconnect metal layer. A third via is pattern etched through part of the second insulating layer to the first interconnect metal layer. A second interconnect metal layer is deposited and patterned including into the third via deposited over the patterned first interconnect metal layer such that the third via is filled with the second interconnect metal layer. A third insulating layer is deposited over the substrate lateral area including the second interconnect metal layer to complete an integrated circuit.

In aspects of the innovation, an integrated circuit device has a plurality of layers. The layers include a substrate, a first semiconductor device deposited onto a portion of the substrate, and a second semiconductor device deposited onto a second portion of the substrate such that the second semiconductor device is spaced from the first semiconductor device to facilitate intended electrical functionality. A first insulating layer that is deposited and then patterned onto part of the first semiconductor device, part of the second semiconductor device, and the substrate.

A contact metal layer that is patterned onto the part of the first semiconductor device and the part of the second semiconductor that is not covered by the patterned first insulating layer. A protective layer that is patterned onto the contact metal layer. A first patterned interconnect metal layer that electrically connects the first semiconductor to the second semiconductor via the patterned contact metal layer and the patterned protective layer. A second insulating layer that is patterned over the substrate lateral area including part of the first interconnect metal layer, wherein the second insulating layer patterning leaves a second via. A second interconnect metal layer that is deposited and patterned over the substrate lateral area including over the remaining part of the first interconnect metal layer such that the second via is filled with the second interconnect metal layer. A third insulating layer that is deposited and patterned over the substrate lateral area including over the patterned second interconnect metal layer.

In aspects, the innovation provides substantial benefits in terms of integrated circuits that can function over long periods at high temperatures. One advantage resides in using the same photoresist pattern for patterning a dielectric via with a combination of dry and wet etching as well as liftoff patterning of a 500 C durable SiC metal-semiconductor contact and a 500 C durable protective metal over layer. Another advantage resides in deposition and subsequent successful liftoff patterning of successful 500 C prolonged-durability SiC ohmic contact layers (e.g., Ti and Hf demonstrated) and oxidation-resistant high temperature protective cap metal without pre-deposition thermal “bake” sample treatment and with abundant photoresist on the sample.

Another advantage resides in deposition and use of highly dense and uniform and 500 C durable TaSi2 films using close-proximity UHV sputter deposition process and apparatus. Yet another advantage resides in the use of hafnium as a durable high temperature ohmic contact to heavily doped ion implanted 4H—SiC. Still further advantages are apparent and will become apparent to those skilled in the art.

The following description and drawings set forth certain illustrative aspects and implementations. These are indicative of but a few of the various ways in which one or more aspects may be employed. Other aspects, advantages, or novel features of the disclosure will become apparent from the following detailed description when considered in conjunction with the drawings.

DETAILED DESCRIPTION

Embodiments or examples illustrated in the drawings are disclosed below using specific language. It will nevertheless be understood that the embodiments or examples are not intended to be limiting. Any alterations and modifications in the disclosed embodiments and any further applications of the principles disclosed in this document are contemplated as would normally occur to one of ordinary skill in the pertinent art. Described herein are examples of systems, methods, and other embodiments associated with interconnection of semiconductor devices in extreme environment microelectronic integrated circuit chips.

The following process interconnects a semiconductor device to facilitate fabrication of complex integrated circuits that durably function beyond extreme temperatures for extended time periods.FIG. 3illustrates in two semiconductor devices302and304residing on a substrate306. In some embodiments, the semiconductor devices are on a microscopic scale. In some embodiments, the semiconductor used is silicon carbide (SiC). For explanation purposes, a top view and a cross-sectional side view of said devices are illustrated. The top view is meant to show the top layers of the cross sectional view, however for disclosure purposes, some underlying layers may be depicted. It is appreciated that either semiconductor device302,304can be a transistor, resistor, diode, detector, or other semiconductor device. In some embodiments, the top surfaces of the semiconductor devices302,304are heavily doped in selected contact via regions (described in detail infra) to facilitate subsequent formation of ohmic metal-semiconductor (e.g. SiC) contacts. In some embodiments, heavy doping in a semiconductor device can also reside in regions where there are no contacts and/or no vias (described in detail infra).

In some embodiments, the two semiconductor devices302,304are patterned and doped to provide semiconductor device electrical functionality. In an experimental embodiment, the semiconductor devices302,304are 4H—SiC junction field effect transistors (JFETs) and 4H—SiC resistors. It is appreciated that the semiconductor devices302,304can employ different arrangements. For example, semiconductor device302can be one end of a JFET, while semiconductor device304could be one end of a resistor. Alternatively, semiconductor device302can be one end of a JFET and semiconductor device304can be one end of a different JFET. In another example, semiconductor device302can be one end of a resistor, and semiconductor device304can be one end of another resistor.

It is appreciated that such JFET and resistor devices usually have more than one ohmic metal-semiconductor contact. For illustrative simplicity one ohmic contact region/end of each such device are illustrated in the figures instead of an entire JFET or resistor structure.

At this stage of the fabrication, a substrate lateral area that includes the semiconductor devices302,304are covered by a first layer (or layers) of a dielectric insulating material308. It is appreciated that depositing or covering refers to covering the substrate lateral area. The depositing covers all existing features regardless of the underlying structure over the substrate lateral area of a substrate chip/wafer.

The first dielectric308provides for electrical insulation for the circuit. The first dielectric308can insulate the semiconductor devices302,304and substrate308from interconnect layers to be formed as described infra. In some embodiments, the first dielectric308is selected to maximize insulation while minimizing formation of physical cracks due to thermally-induced stresses over the entire operating temperature range of the IC. In some embodiments, the first dielectric308is comprised of an approximately 400 nanometer layer thick silicon dioxide (SiO2) that is grown via thermal oxidation of SiC and resides beneath an approximately 1 micrometer thick SiO2 deposited at 720 C by low-pressure chemical vapor deposition (LPCVD) using a tetraethyl orthosilicate (TEOS) precursor.

FIG. 4illustrates the photolithographic pattern definition of photoresist402that will define uncovered regions404and406devoid of photoresist where vias can form via plug contacts to the semiconductor devices302,304.

FIG. 5andFIG. 6illustrates the removal of the first dielectric308in the uncovered regions404,406by photoresist-patterned etching to form intermediary vias502,504, and final (first and second) vias602,604through the first dielectric308, which exposes selected SiC surfaces of the underlying SiC devices302,304. In some embodiments, the lateral dimensions of the vias502,504,602,604are preferably less than 10 micrometers. In other embodiments, the etching can be accomplished using a combination of dry and/or wet etching, wherein the etching removal of the first dielectric308takes place in regions404,406not protected by the overlying patterned photoresist402.

FIG. 5illustrates the results of a dry reactive ion etching (RIE) process to remove most (e.g. approximately 90%) of the first dielectric layer308to form intermediary first and second vias502,504. The RIE process can provide for steep (e.g. approximately vertical) sidewalls (e.g. an anisotropic etch) that reproduces the lateral pattern of the photoresist402in the etched oxide dielectric, but RIE is not able to stop etching without undesirably altering/damaging the semiconductor device302,304surface if the RIE was permitted to remove all the oxide reaching the semiconductor302,304surface.FIG. 6illustrates removal of the remainder of the first dielectric layer308using a wet buffered oxide etch (BOE). When the BOE finishes the via etch by removing the remaining (approximately 10%) of initial oxide thickness, it stops at the semiconductor device302,304surface. In some embodiments, the BOE leaves a damage-free SiC surface on the semiconductor devices302,304to facilitate subsequent reproducible good ohmic contact formation.

In some embodiments, BOE etching can undercut the lateral photoresist pattern (i.e., make the lateral size of a via larger than the photoresist pattern, as indicated inFIG. 6in simplified fashion) as BOE etching of oxide is more isotropic in nature. However, removing approximately 0.1 microns of material (i.e., the last 10% of oxide thickness because the RIE removed the preceding 90% of oxide thickness) minimizes this effect as BOE etch times are kept relatively short compared to times for a wet BOE for 100% of the via etch. To ensure that liquid BOE reaches the bottom of the via for full desired etch depth (e.g. to overcome microscopic-feature liquid surface tension effects known in the art that might have prevented this), the BOE liquid solution with the wafer immersed can be subjected to ultrasonic agitation during the BOE wet etch.

FIG. 7illustrates a deposition of thin high temperature durable ohmic contact metal layer702followed by thin protective layer of oxidation-resistant high temperature durable interconnect metal704. In some embodiments, the wafer (with the first dielectric308and photoresist402pattern still present) is loaded into a vacuum metal deposition system to deposit the metal layers702,704. In some embodiments, the metal layers702,704are deposited without breaking the vacuum between the deposition of the two or more metal layers. In some embodiments, to minimize native oxide formation that occurs on the freshly exposed SiC surface in room air, this loading preferably takes place less than 1 hour after the BOE wet etch is completed and quenched with deionized water rinsing.

In some embodiments, an ultrahigh vacuum (UHV) sputter deposition can be employed. In other embodiments, the high temperature durable ohmic contact metal702deposited can be made of Titanium or Hafnium. The high temperature durable ohmic contact metal layer702can be approximately 50 nanometers in thickness. It is appreciated that other metals, metal alloys, and multi-level metal/alloy stacks deposited with other vacuum metal deposition methods could be used provided they can be patterned by liftoff and yield desired electrical and physical ohmic contact properties. For example, the following metals can also be employed as thin high temperature contact metals702: Vanadium, Chromium, Zirconium, Niobium, Molybdenum, Tantalum, and Tungsten. It is appreciated that compounds of silicides and carbides of these metal elements could also be employed as high temperature contact metals702with different compound phases and deposition and annealing techniques. The metal deposition process does not damage/degrade the photoresist to the degree that successful subsequent “liftoff patterning” removal of the photoresist and metal that resided on top of said photoresist is precluded.

In some embodiments, to preserve the photoresist liftoff integrity, the target-to-substrate distance used for the UHV sputter was 50 mm, and the substrate was electrically grounded with the vacuum chamber metal during the sputter.

It is appreciated that numerous methods and materials for forming ohmic contacts to SiC are known in the art. Moreover, aspects of the innovation, counter to methods known, do not address any temperature greater than 500 C durable SiC ohmic contact process wherein SiC ohmic contact patterning has been accomplished using only photoresist (i.e., without an additional photoresist-pattern metal etch mask pattern), the same patterned photoresist layer that was used to pattern the first dielectric308, etch vias602,604and without high-temperature vacuum environment pre-sputter bake to mitigate oxygen contamination.

A number of suitable durable ohmic contact metal films to SiC, including Titanium and Hafnium, are known to react with atmospheric oxygen to form metal-oxides that undesirably degrade ohmic contact conductivity and adhesion. To minimize this degradation mechanism, the in-situ deposition (i.e. without breaking vacuum) of an overlying oxidation-resistant metal thin film704to protect the ohmic contact metal from atmospheric oxygen exposure is employed. This overlying protective metal layer704can durably withstand prolonged IC operation for temperatures greater than or equal to 500 C. In some embodiments, the overlying protective metal layer704is made of tantalum silicide (TaSi2) that is approximately 0.2 micrometers thick and sputtered in the same UHV deposition system (without breaking vacuum) as the ohmic contact metal702.

FIG. 8illustrates an intermediary configuration of the IC following both UHV depositions and subsequent liftoff removal of photoresist402leaving behind desired “via plug” pattern of ohmic layer702and protective high temperature metal layer704residing on the SiC device surface302,304at the bottom of the etched vias602,604through the first dielectric308. In some embodiments, the liftoff removal is accomplished using wet chemical solvents to dissolve the photoresist. In some embodiments liftoff removal is followed by a dry plasma photoresist cleaning process. It is appreciated that the fabrication process described andFIG. 8intermediary configuration minimize/protect ohmic layer702from detrimental oxygen exposure.

FIG. 9illustrates the completion of the electrical/physical first level interconnection of the separate semiconductor devices302,304by forming a patterned electrically conductive trace of high temperature (e.g. temperature greater than 500 C) durable metal902between the two via plugs704. In some embodiments, the lateral extent of this patterned interconnect metal902can be larger than the lateral extent of the vias602,604to better protect (e.g. seal) the oxygen sensitive ohmic-contact metal702from atmospheric oxygen. In some embodiments, the high temperature durable metal interconnects are patterned to extend laterally across the substrate lateral area to form electrical connections for integrated circuit function.

In some embodiments, the high temperature durable interconnect metal902is a 0.8 micrometer thick film of tantalum silicide (TaSi2) that is substantially uniform and dense. In this embodiment, the film is blanket-deposited using close-proximity sputtering (e.g. less than 3 cm target-to-substrate distance) in a UHV system. Prior to the sputtering, a one-hour substrate bake at 300 C is employed with subsequent cool-down to less than 100 C to mitigate oxygen (e.g. water vapor) contamination, and the substrate306was electrically floating during the sputter deposition. The film can be laterally patterned using photolithography and dry etching techniques.

FIG. 10illustrates a second overlying dielectric layer (“Dielectric2” as labeled in the FIGURES)1002deposited across the lateral substrate area, including on top of the first metal level interconnect (“Metal1”)902. The second dielectric layer1002can further protect the oxygen-sensitive ohmic contact metal-SiC interface. During prolonged IC operation at 500 C, the second dielectric layer1002can protect the high temperature durable interconnect metal902. For the embodiment where metal902is a 0.8 micrometer thick film of tantalum silicide (TaSi2), it has been observed that TaSi2 detrimentally oxidizes when exposed to air for long time periods at 500 C. When protected from air by dielectric1002, the TaSi2 interconnect does not detrimentally oxidize.

It is appreciated that the intermediary IC structure depicted inFIG. 10forms a single-level interconnect foundation for realizing 500 C durable integrated circuits of limited complexity and functionality. However, modern integrated circuits can be implemented using the advantages (including greatly increased complexity) offered by multiple levels of interconnects. The intermediary IC structure depicted inFIG. 10results in a high-temperature durable first metal level interconnect902that serves as a foundation for an implementation of a second metal level interconnect of extreme high-temperature durability that is illustrated inFIGS. 11-13.

FIG. 11illustrates patterned etching of a third via1102that can facilitate an electrical connection between first-level patterned high temperature interconnect layer902(i.e., “Metal1”) and a second-level patterned high temperature durable interconnect metal layer. In some embodiments, the third via1102is dry etched into the second dielectric1002for maximum lateral pattern accuracy. In some embodiments, the pattern can be “over-etched” to remove some of the underlying first interconnect metal902without harming circuit functionality so long as the first interconnect metal902is not completely removed by the over etch in the third via1102.

FIG. 12illustrates a second high temperature durable metal interconnect1202that is deposited and patterned. The third via1102enables electrical connection where desired between the first interconnect metal902and the second interconnect metal1202. In some embodiments, the second dielectric1002is tetraethyl orthosilicate (TEOS) SiO2 and the high temperature durable interconnect metal1202is 0.8 micrometer thick film that is substantially uniform and dense. The high temperature durable interconnect metal1202can be made of TaSi2 that is blanket-deposited by close-proximity sputtering (e.g. less than 3 cm target-to-substrate distance) in a UHV system. The high temperature durable interconnect metal1202can be laterally patterned by photolithography and dry etching.

It is appreciated to that the first metal interconnect902and the second metal interconnect1202can be deposited in patterns that can extend across the substrate according to a circuit design. The pattern can extend to areas on the substrate where there are no underlying first interconnect metal and/or no underlying devices.

FIG. 13illustrates an overlying third dielectric layer or layers (“Dielectric3”)1302that can be deposited and patterned on top the second interconnect metal1202structure to form the finalized IC structure. The structure depicted with two levels of metal interconnect can successfully enable realization of complicated integrated circuitry that can function for long time periods (e.g. thousands of hours) and at high temperatures (e.g. temperature greater than or equal to 500 C). In some embodiments, the third dielectric layer1302is multiple layers made of approximately 1 micrometer thick SiO2, approximately 67 nm thick Si3N4, and approximately 1 micrometer thick SiO2.

FIG. 14shows a scanning electron micrograph close-up of the cross-section (prepared by focus ion-beamed milling of a sample) of an experimentally implemented high-temperature durable contact via plug implemented using the IC structure ofFIG. 13. It is appreciated that part of theFIG. 13structure is seen in the close-up. The detailed experimentally obtained physical profiles of the via plug metallization layers702,704(Hf and TaSi2) residing on top of phosphorous implant doped 4H—SiC are visible inside the etched oxide via, over-coated by the subsequently deposited first metal TaSi2 interconnect902.

FIG. 15shows a similar cross-sectional micrograph of a specific embodiment of the structure ofFIG. 13. The specific embodiment is an experimental two-level interconnect stack that includes a via plug contact702,704to the SiC device302,304, a first TaSi metal interconnect902, a second metal interconnect1202, a via1102between the first metal interconnect902and second metal interconnect1202, and insulating dielectric layers308,1002,1302that is made of SiO2, silicon nitride, and SiO2 respectively.

FIG. 16illustrates a method1600for fabricating an integrated circuit. At1602, a first semiconductor device and a second semiconductor device are constructed on a substrate. At1604, a first insulating layer is deposited that covers substantially the first semiconductor device, the second semiconductor device, and the substrate and its lateral extent (substantially entire substrate lateral area). At1606, a patterned photoresist is deposited over the first insulating layer. The patterned photoresist defines a pattern for a first via to the first semiconductor device through the first insulating layer and a second via for the second semiconductor device through the first insulating layer. At1608, the first via and the second via is etched through the first insulating layer using the patterned photoresist as an etch mask that confines etching of the first insulating layer to occur in regions where there is no overlying photoresist. Except for small-dimension lateral over-etch to be described, the first insulating layer is preserved (e.g. not etched) in regions directly beneath photoresist.

At1610, a contact metal layer is deposited onto the substrate lateral area including the first semiconductor device and the second semiconductor device and regions with the patterned photoresist. At1612, a protective layer is deposited onto the substrate lateral area including the contact metal layer and regions with the patterned photoresist. At1614, the patterned photoresist is removed along with the metals that resided on top of the photoresist, so that the contact metal layer and protective layer remain in the regions on the first semiconductor device and the second semiconductor device where there was no overlying photoresist at the time that contact metal layer and protective layers were deposited. At1616, a first interconnect metal layer is deposited and patterned. The first interconnect metal layer electrically connects the first semiconductor device to the second semiconductor device via the contact metal layer and the protective layer.

At1618, a second insulating layer is deposited over the substrate lateral area including the first interconnect metal layer. At1620, a third via is pattern etched through part of the second insulating layer to the first interconnect metal layer. At1622, a second interconnect metal layer is deposited and patterned into the third via deposited over the patterned first interconnect metal layer such that the third via is filled with the second interconnect metal layer. At1624, a third insulating layer is deposited over the substrate lateral area including the second interconnect metal layer. It is appreciated that insulating layers and metal layers are patterned according to circuit designs to extend laterally across a substrate chip/wafer.

While for purposes of simplicity of explanation, illustrated methodologies are shown and described as a series of blocks. The methodologies are not limited by the order of the blocks as some blocks can occur in different orders and/or concurrently with other blocks from that shown and described. Moreover, less than all the illustrated blocks may be used to implement an example methodology. Blocks may be combined or separated into multiple components. Furthermore, additional and/or alternative methodologies can employ additional, not illustrated blocks. The methods described herein are limited to statutory subject matter under 35 U.S.C § 101.

Various operations of embodiments are provided herein. The order in which one or more or all of the operations are described should not be construed as to imply that these operations are necessarily order dependent. Alternative ordering will be appreciated based on this description. Further, not all operations may necessarily be present in each embodiment provided herein.

Further, unless specified otherwise, “first”, “second”, or the like are not intended to imply a temporal aspect, a spatial aspect, an ordering, etc. Rather, such terms are merely used as identifiers, names, etc. for features, elements, items, etc. For example, a first channel and a second channel generally correspond to channel A and channel B or two different or two identical channels or the same channel.

Although the disclosure has been shown and described with respect to one or more implementations, equivalent alterations and modifications will occur based on a reading and understanding of this specification and the annexed drawings. The disclosure includes all such modifications and alterations and is limited only by the scope of the following claims.