Semiconductor device having wirings formed by damascene and its manufacture method

A via hole is formed in the interlayer insulating film on a semiconductor substrate, the via hole reaching the bottom of the interlayer insulating film. A filling member fills a lower partial space in the via hole. A wiring trench continuous with the via hole as viewed in plan is formed, the wiring trench reaching partway in a thickness direction. The wiring trench is formed under the condition that an etching rate of the interlayer insulating film is faster than that of the filling member, in such a manner that a height difference between the upper surface of the filling member and the bottom of the wiring trench is half or less than half the maximum size of a plan shape of the via hole. The filling member in the via hole is removed. The inside of the via hole and wiring trench is filled with a conductive member.

CROSS REFERENCE TO RELATED APPLICATION

This application is based on and claims priority of Japanese Patent Application No. 2006-076422 filed on Mar. 20, 2006, the entire contents of which are incorporated herein by reference.

BACKGROUND OF THE INVENTION

A) Field of the Invention

The present invention relates to a semiconductor device and its manufacture method, and more particularly to a semiconductor device having wirings formed by damascene and its manufacture method.

B) Description of the Related Art

Material having a dielectric constant lower than that of silicon oxide and the like is used as the material of an interlayer insulating film of a wiring layer in order to reduce parasitic capacitance. In order to further lower a dielectric constant, a structure is being adopted which does not use an etching stopper film having a relatively high dielectric constant. When wirings are formed by dual damascene, if an etching stopper is omitted between a via hole layer and a wiring trench layer, it becomes difficult to control the shapes of a wiring trench and a via hole.

As via holes and wiring trenches become finer, it becomes difficult to fill via holes and wiring trenches with conductive material at good reproductivity. JP-A-2003-92349 (FIG. 9) discloses a technique of improving filling characteristics by forming an inclined plane on upper edge portions of sidewalls of a via hole and a wiring trench.

JP-A-2001-284449 discloses a technique of depositing a barrier metal film on sidewalls of a via hole and a wiring trench while a barrier metal layer deposited on the bottom of the via hole is sputtered. This technique improves resistance against electromigration of wirings.

JP-A-2004-165336 discloses a method of covering an inner surface of a via hole with a barrier metal film, etching and removing the barrier metal film on the bottoms and depositing again a barrier metal film on the thinned barrier metal film on the inner surfaces other than the bottoms. This method can thin the barrier metal film on the via hole bottom and retain a sufficient thickness of the barrier metal film on the sidewall of the via hole and on the inner surface of a wiring trench.

In a barrier metal film depositing process, yield and wiring reliability can be improved by adopting sputtering combining depositing and etching. It has been found that during sputter-etching of a barrier metal film, the barrier metal film deposited on an inclined plane having an inclination angle of about 45° relative to a substrate surface is etched faster than the barrier metal film deposited on other surfaces. This may be ascribed to that an etching rate becomes maximum at an incidence angle of about 45° of sputtering ions.

If the inner surfaces of a via hole and a wiring trench have an inclined plane having an inclination angle of 45°, the barrier metal film deposited on this inclined plane is thinned. Voids or the like are formed in the via hole and wiring reliability is lowered. If a barrier metal film is again deposited on the thinned barrier metal film by using the method disclosed in JP-2004-165336, the barrier metal layer in other areas becomes too thick.

SUMMARY OF THE INVENTION

An object of the present invention is to provide a semiconductor device manufacture method suppressing wiring reliability from being lowered, even if a barrier metal film is sputter-etched. Another object of the present invention is to provide a semiconductor device having a structure capable of suppressing wiring reliability from being lowered, even if a barrier metal film is sputter-etched.

According to one aspect of the present invention, there is provided a method of manufacturing a semiconductor device comprising steps of:

(a) forming an interlayer insulating film over a semiconductor substrate;

(b) forming a via hole in the interlayer insulating film, the via hole reaching a bottom of the interlayer insulating film;

(c) filling a lower partial space in the via hole with a filling member;

(d) forming a wiring trench continuous with the via hole as viewed in plan, the wiring trench reaching partway in a thickness direction of the interlayer insulating film, the wiring trench being formed under a condition that an etching rate of the interlayer insulating film is faster than an etching rate of the filling member, in such a manner that a height difference between an upper surface of the filling member left in the via hole and a bottom of the wiring trench is half or less than half a maximum size of a plan shape of the via hole;

(e) removing the filling member in the via hole; and

(f) filling an inside of the via hole and the wiring trench with a conductive member.

an interlayer insulating film formed over a semiconductor substrate;

a wiring trench having a depth extending from an upper surface of the interlayer insulating film and reaching partway in a thickness direction of the interlayer insulating film;

a via hole disposed at an end of the wiring trench and reaching a bottom of the interlayer insulating film;

a barrier metal film covering inner surfaces of the wiring trench and the via hole; and

a wiring filling an inside of the wiring trench and the via hole,

wherein a bottom of the wiring trench and a sidewall of the via hole are connected via an inclined plane, and a length of a portion of the inclined plane having an inclination angle range of 40° to 50° relative to a surface of the semiconductor substrate is equal to or shorter than a maximum size of a plan shape of the via hole, in a cross section which is parallel to a longitudinal direction of the wiring trench, passes a center of the via hole and perpendicular to the surface of the semiconductor surface.

According to still another aspect of the present invention, there is provided a semiconductor device comprising:

an interlayer insulating film formed over a semiconductor substrate;

a wiring trench having a depth extending from an upper surface of the interlayer insulating film and reaching partway in a thickness direction of the interlayer insulating film;

a via hole disposed at an end of the wiring trench and reaching a bottom of the interlayer insulating film;

a barrier metal film covering inner surfaces of the wiring trench and the via hole; and

a wiring filling an inside of the wiring trench and the via hole,

wherein a bottom of the wiring trench and a sidewall of the via hole are connected via a stepped plane.

In the step (d), the wiring trench is formed in such a manner that a height difference between the upper surface of the filling member left in the via hole and the bottom of the wiring trench is half or less than half the maximum size of the plan shape of the via hole. Therefore, an inclined plane is hard to be generated at the connection portion between the bottom of the wiring trench and the sidewall of the via hole.

By shortening the length of the inclined plane in the inclination angle range of 40° to 50°, it becomes possible to mitigate the influence of thinning of the barrier metal film and improve the wiring reliability. Wiring reliability can also be improved by involving a stepped plane at the connection portion between the bottom of the wiring trench and the sidewall of the via hole.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

FIG. 1Ais a plan view showing a wiring and a via hole of a semiconductor device according to the embodiment. A relatively thin wiring41extends from an approximately center area of the edge at the end of a relatively bold wiring43along a direction parallel to a longitudinal direction of the bold wiring43. A via hole24having a plan shape of generally a circle is disposed at the distal end of the thin wiring41. For example, a width W1of the bold wiring43is 3 μm, a width W2of the thin wiring41is 140 nm, and a distance L from the end of the bold wiring43to the center of the via hole24is 1 μm. The diameter of the via hole24is equal to the width of the thin wiring41.

With reference toFIGS. 1B to 1L, description will be made on a semiconductor device manufacture method according to the embodiment.FIGS. 1B to 1Lcorrespond to cross sectional views taken along one-dot chain line B1-B1shown inFIG. 1A. Specifically,FIGS. 1B to 1Lcorrespond to cross sections which are parallel to the longitudinal direction of the wirings41and43, pass through the center of the via hole24, and are perpendicular to the surface of the semiconductor substrate.

As shown inFIG. 1B, an isolation insulating film2having a shallow trench isolation (STI) structure is formed in the surface layer of a semiconductor substrate1made of silicon or the like. A MOS transistor3is formed in an active region surrounded by the isolation insulating film2. An interlayer insulating film10made of silicon oxide or the like is formed on the semiconductor substrate1, covering the MOS transistor3. A conductive plug11made of tungsten or the like fills a via hole passing through the interlayer insulating film10. The conductive plug11is connected to the source or drain of the MOS transistor3.

An interlayer insulating film15made of SiOC or the like is further formed on the interlayer insulating film10. A wiring trench is formed in the interlayer insulating film15by single damascene, and a wiring17made of Cu or the like fills the wiring trench. The inner surface of the wiring trench is covered with a barrier metal film16of Ta or the like.

A cap film20made of SiC or the like and having a thickness of 50 nm is formed on the interlayer insulating film15. An interlayer insulating film21made of SiOC or the like and having a thickness of 450 nm and a first hard mask22are deposited on the cap film20in this order. The first hard mask22has a two-layer structure of a lower layer22amade of SiO2and having a thickness of 100 nm and an upper layer22bmade of SiN and having a thickness of 30 nm. These films are deposited, for example, by chemical vapor deposition (CVD). In forming the lower layer22aof the first hard mask22, tetraetoxyorthosilicated (TEOS) and oxygen are used as source gases. Other materials having different etching resistance from that of the interlayer insulating film21may be used as the material of the first hard mask22.

As shown inFIG. 1C, a resist pattern30is formed on the first hard mask22. The resist pattern30has an opening corresponding to a via hole24to be formed in the interlayer insulating film21. By using the resist pattern30as an etching mask, the first hard mask22and interlayer insulating film21are etched to form a via hole24. The cap film20is exposed on the bottom of the via hole24. This etching may be performed by using a magnetically enhanced reactive ion etching (MERIE) system under the following conditions:

After the via hole24is formed, the resist pattern30is removed.

As shown inFIG. 1D, a filling member33made of resist not having photosensitivity is formed on the first hard mask22. The filling member33also fills the via hole24. The surface of the filling member33is generally flat. Other materials having different etching resistance from those of the cap film20, interlayer insulating film21and first hard mask22may be used as the material of the filling member33.

A second hard mask35made of SiO2and having a thickness of 100 nm is formed on the flat surface of the filling member33by CVD using TEOS as source gas. Other materials having different etching resistance from that of the filling member33may be used as the material of the second hard mask35. A resist pattern38is formed on the second hard mask35. The resist pattern38has an opening corresponding to a wiring trench to be formed in the interlayer insulating film21.

As shown inFIG. 1E, by using the resist pattern38as an etching mask, the second hard mask35is etched by using the MERIE system. The etching conditions are as follow:

As shown inFIG. 1F, by using the second hard mask35as an etching mask, the filling member33is etched to an intermediate depth of the via hole24. The etching conditions are as follow:

With this etching, the resist pattern38covering the second hard mask35is also removed, so that the upper surface of the second hard mask35is exposed. The upper surface of the first hard mask22in the area corresponding to the wiring trench is exposed. A portion33A of the filling member is left in the region covered with the second hard mask35, and a portion33B of the filling member is left in a partial region of the via hole24. A preferred height of the filling member33B to be left in the via hole24will be later described in detail.

As shown inFIG. 1G, by using the filling member33A as an etching mask, the first hard mask22is etched by using the MERIE system. The etching conditions are as follow:

This etching exposes the surface of the interlayer insulating film21in the area corresponding to the wiring trench. The second hard mask35left on the filling member33A is also removed.

As shown inFIG. 1H, by using the filling members33A and33B as an etching mask, the interlayer insulating film21is etched partway in the thickness direction by using the MERIE system, under the condition that an etching rate of the interlayer insulating film21is faster than that of the filling member33B. The specific etching conditions are as follows:

This etching forms a wiring trench25. Since the filling members33A and33B are partially etched while the interlayer insulating film21is etched, the filling member33A left on the first hard mask22is thinned and the filling member33B filling the via hole24becomes short in height. It is preferable that the bottom of the wiring trench25is generally on the same level as the upper surface of the filling member33B filling the via hole24, at the time when the wiring trench25is etched to a target depth. More specifically, it is preferable that a height difference between the upper surface of the filling member33B left in the via hole24and the bottom of the wiring trench25is half or less than half the maximum size of the plan shape of the via hole24. To this end, a height of the filling member33B to be left in the via hole24in the process shown inFIG. 1Gis adjusted based on a target depth of the wiring trench25to be formed and a ratio between the etching rate of the interlayer insulating film21and the etching rate of the filling member33B.

After the wiring trench25is formed, the filling members33A and33B are removed by ashing. The ashing conditions are as follows:

As shown inFIG. 1I, the cap film20is exposed on the bottom of the via hole24, and the upper surface of the first hard mask22is exposed.

As shown inFIG. 1J, the cap film20exposed on the bottom of the via hole24is etched by using the MERIE system. The etching conditions are as follows:

While the cap film20is etched, the upper layer22bof the first hard mask22is removed. The surface of the Cu wiring17exposed on the bottom of the via hole24is cleaned by sputtering using Ar or the like.

As shown inFIG. 1K, a barrier metal film40A of Ta or the like is formed by sputtering, covering the inner surface of the wiring trench25, the inner surface of the via hole24and the upper surface of the lower layer22aof the first hard mask22.

FIG. 2is a schematic cross sectional view of a sputtering system. A wafer stage51is disposed in a chamber50, and a wafer52is held on the wafer stage51. A target53is held above the wafer52. The sides of a space between the target53and wafer stage51are magnetically shielded by shields54. A rotary magnetic assembler55is mounted on the target53.

A stage bias power source58supplies a substrate bias power to the wafer stage51. A target power source59supplies a target power to the target53. The substrate bias power and target power are, for example, RF power at a frequency of 13.56 MHz. Gas is supplied into the chamber50from a gas supply source60, and a vacuum pump65evacuates the inside of the chamber50. By controlling the target power and substrate bias power, it is possible to adjust a depositing rate and etching rates of the Ta film.

In the following, description will be made on a method of forming the barrier metal film40A made of Ta. First, a Ta film is deposited under the condition that the depositing rate is faster than the etching rate. The film forming conditions are as follows:

Next, the Ta film deposited on the substrate is re-sputtered under the condition that the etching rate is faster than the depositing rate, e.g., the depositing rate is about 0.5 to 0.9 time as fast as the etching rate. The re-sputtering conditions are as follows:

A thickness of the barrier metal film40A formed under the above-described conditions is 5 to 8 nm on the sidewall of the via hole24, 3 to 5 nm on the bottom of the via hole24, 8 to 13 nm on the sidewall of the wiring trench25, 5 to 10 nm on the bottom of the wiring trench25, and 10 to 15 nm on the first hard mask22.

A Cu seed film is formed by sputtering on the barrier metal film40A, and Cu is electroplated to form a conductive film41A. The via hole24and wiring trench25are filled with the conductive film41A.

As shown inFIG. 1L, CMP is performed until the lower layer22aof the first hard mask is exposed. The barrier metal film40is left on the inner surfaces of the via hole24and wiring trench25to form a wiring41filling the via hole24and wiring trench25.

Next, with reference toFIGS. 3A and 3B, description will be made on the shape of the connection portion between the bottom of the wiring trench25and the sidewall of the via hole24.

FIG. 3Billustrates etching progresses when the filling member33B left in the via hole24is too short in height. At the initial etching stage, since the sidewall of the via hole24near at the upper end is exposed, an inclined plane27is formed at the connection portion between the sidewall of the via hole24and the bottom of the wiring trench25. As the etching progresses for the interlayer insulating film21in the region where the wiring trench25is to be formed, the filling member33B is also etched and it becomes short in height. As the filling member33B becomes short in height, the exposed area of the sidewall of the via hole24increases and the inclined plane27becomes large.

FIG. 3Aillustrates etching progresses while the interlayer insulating film21is etched by the embodiment method. Similar to that shown inFIG. 3B, at the initial etching stage, an inclined plane27is formed at the connection portion between the sidewall of the via hole24and the bottom of the wiring trench25. However, since the exposed area of the via hole24is shallow, the inclined plane27is more gentle than that shown inFIG. 3B. As the etching progresses and the bottom of the wiring trench25comes up with the upper surface of the filling member33B, the inclined plane is hard to be formed further. The inclined plane is formed less if etching is stopped when the bottom of the wiring trench25reaches the same level as the upper surface of the filling member24.

Next, with reference toFIGS. 4A to 4F, description will be made on various surface shapes to be formed at the connection portion between the bottom of the wiring trench25and the sidewall of the via hole24.FIGS. 4A to 4Fcorrespond to cross sectional views taken along one-dot chain line B1-B1shown inFIG. 1A. Specifically,FIGS. 4A to 4Fcorrespond to cross sections which are parallel to the longitudinal direction of the wirings41and43, pass through the center of the via hole24, and are perpendicular to the surface of the semiconductor substrate.

FIG. 4Ashows the state that an inclined plane27ais formed at the connection portion between the bottom of the wiring trench25and the sidewall of the via hole24. An inclination angle of the inclined plane27ato the surface of the semiconductor substrate1is larger than 50°.

FIG. 4Bshows the state that a stepped plane27bis formed at the connection portion between the bottom of the wiring trench25and the sidewall of the via hole24. The stepped plane27bincludes a relatively gentle gradient region continuous with the sidewall of the via hole24and a relatively steep gradient region continuous with the bottom of the wiring trench25. The stepped plane shown inFIG. 4Bhas an inclination angle of almost 0° at the gentle gradient region and almost 90° at the steep gradient region.

A stepped plane27cshown inFIG. 4Chas a shape different from that of the stepped plane27bshown inFIG. 4B. An inclination angle at the gentle gradient region is almost 0° and an inclination angle at the steep gradient region is larger than 50°.

FIG. 4Dshows the state that an inclined plane27dis formed with an inclination angle range of 40° to 50°.FIG. 4Eshows the state that an inclined plane27eis formed including a curved portion in the cross section.FIG. 4Fshows the state that an inclined plane27fis formed with an inclination angle range of 40° to 50° and is larger than the inclined plane27dshown inFIG. 4D.

A difference between these shapes results from a difference between the etching conditions of the process of etching the interlayer insulating film21shown inFIG. 1H, a height difference between the bottom of the wiring trench25and the upper surface of the filling member33B, and other reasons.

FIGS. 5A and 5Bare microscopic photographs showing the cross sections of a wiring trench and a via hole actually formed. These photographs show the state that the inner surfaces of the wiring trench and via hole are covered with a barrier metal film. A Cu wiring is not still deposited.FIG. 5Acorresponds to the state shown inFIG. 4Chaving the stepped plane at the connection portion between the bottom of the wiring trench and the sidewall of the via hole.FIG. 5Bcorresponds to the state shown inFIG. 4Dor4F having the inclined plane with the inclination angle range of 40° to 50° at the connection portion between the bottom of the wiring trench and the sidewall of the via hole.

In order to evaluate stress migration resistance of the samples shown inFIGS. 5A and 5B, the samples were heated to about 200° C. and kept in this condition for 21 days, and a via resistance before heating and a via resistance after leaving it at a raised temperature condition were measured.

FIG. 6is a graph showing a cumulative probability of a rate of resistance rise of a via chain of each sample shown inFIGS. 5A and 5B. The abscissa represents a rate of resistance rise in the unit of “%” and the ordinate represents a cumulative probability. Curves a and b shown inFIG. 6indicate the cumulative probabilities of the samples shown inFIGS. 5A and 5B, respectively.

It can be understood that the sample shown inFIG. 5Bhas a higher rate of via resistance rise than that of the sample shown inFIG. 5A. After the evaluation test, the via hole of the sample shown inFIG. 5Bwas observed. It has been found that the via resistance rises because of voids formed in the via hole. The cause of void generation will be described below.

If the large inclined plane27fhaving the inclination angle of 40° to 50° is formed as shown inFIG. 4F, the barrier metal film40A deposited on the inclined plane27fis thinned by re-sputtering during the process of forming the barrier metal film40A. It can be considered that tight adhesion of the Cu wiring41is degraded in the region where the barrier metal film40A was thinned and voids are likely to be generated. Film thinning amount by re-sputtering is large particularly on the inclined plane having the inclination angle of 40° to 50°.

If the inclination angle of the inclined plane27ais larger than 50° as shown inFIG. 4A, thinning amount of the barrier metal film40A deposited on the inclined plane27aby re-sputtering is less. It is therefore possible to prevent wiring reliability from being lowered. It is also possible to prevent wiring reliability from being lowered even at an inclination angle of the inclined plane smaller than 40°.

If the stepped plane27bis formed at the connection portion between the bottom of the wiring trench25and the sidewall of the via hole24as shown inFIG. 4B, it is also possible to suppress thinning of the barrier metal film40A to be caused by re-sputtering. Thinning suppressing effects of the barrier metal film40A are remarkable if the inclination angle at the gentle gradient region of the stepped plane27bis smaller than 40° and the inclination angle at the steep gradient region is larger than 50°.

If the inclination angle of the inclined plane27dis in the range of 40° to 50° as shown inFIG. 4D, there is a fear of thinning of the barrier metal film40A deposited on the inclined plane. However, if a length of the inclined plane27din the cross section shown inFIG. 4Dis equal to or shorter than the maximum size of the plan shape of the via hole24, the influence of thinning of the barrier metal film40A is less. The maximum size of the plan shape means the diameter of the smallest circle inclusive of the plan shape of the via hole. For example, if the plan shape of the via hole is a circle, the maximum size equals to the diameter, and if the plan shape is a square or a rectangle, the maximum size equals to a length of the diagonal line.

If the inclination angle of the inclined plane27cat the steep gradient region is in the range of 40° to 50° as shown inFIG. 4C, the influence of thinning of the barrier metal film40A is less if the length of the steep gradient region in the cross section shown inFIG. 4Cis equal to or shorter than the maximum size of the plan shape of the via hole24.

If the inclined plane27ehas a curved portion in the cross section as shown inFIG. 4E, it is preferable to set the total length of the region having the inclination angle range of 40° to 50° equal to or shorter than the maximum size of the plan shape of the via hole24.

If the inclined plane27fis large and the length of the inclined plane27fin the cross section is longer than the maximum size of the plan shape of the via hole24as shown inFIG. 4F, stress migration resistance of a wiring is not sufficient and voids are likely to be generated.

According to the evaluation experiments made by the present inventors, it has been found that voids are likely to be generated in a via hole in the structure that a thin wiring extends from one end of a bold wiring and a via hole is disposed at the distal end of the thin wiring as shown inFIG. 1A. Therefore, the effects of adjusting the shape of the connection portion between the bottom of the wiring trench and the sidewall of the via hole so as to form the shapes described in the embodiment, are remarkable particularly for a semiconductor device having the above-described layout of a wiring pattern and a via hole.

The remarkable effects can be expected if the width of the bold wiring43is three or more times as large as the width of the thin wiring41. The remarkable effects can also be expected if the length from the end of the thick wiring43to the center of the via hole24is 1.5 or more times as long as the diameter of the via hole24.

The present invention has been described in connection with the preferred embodiments. The invention is not limited only to the above embodiments. It will be apparent to those skilled in the art that other various modifications, improvements, combinations, and the like can be made.