ELECTRONIC PACKAGE AND CIRCUIT STRUCTURE THEREOF

An electronic package and a circuit structure thereof are provided, in which a circuit layer and an electrical function part are formed on a dielectric layer of the circuit structure, and the dielectric layer has at least one corner at a right angle, where a shape of the electrical function part at the corner and corresponding to the right angle is of a non-right angle shape and/or a routing path of the circuit layer at the corner and corresponding to the right angle is of a non-right angle shape, so that stress concentration can be reduced, thereby preventing the electronic package from warping.

BACKGROUND

1. Technical Field

The present disclosure relates to a semiconductor packaging technology, and more particularly, to an electronic package and a circuit structure thereof.

2. Description of Related Art

With the development of the electronics industry toward high-performance computing (HPC), such as the development of medical technology, the development of cancer drugs, the automatic sensing detection computing of self-driving cars, etc., many high-end electronic products are primary based on high-integration packaging technology (e.g., fan-out packaging).

FIG.1Ais a schematic top view showing a conventional semiconductor package1. As shown inFIG.1A, the semiconductor package1includes: a packaging substrate10, a semiconductor chip11flip-chip bonded on the packaging substrate10, and a packaging colloid (not shown) covering the semiconductor chip11.

Referring toFIG.1BtoFIG.1Eat the same time, the packaging substrate10is a rectangular board with a routing region (e.g., a wiring/tracing region) on its surface to form a circuit layer100electrically connected to the semiconductor chip11.

Moreover, stress concentration regions are prone to be generated around the position where the semiconductor chip11is disposed on the packaging substrate10, such as corners A, B, C, D; and the closer to the corners A, B, C, D, the more concentrated the stress is. Hence, at the corners A, B, C, D, at least one large area of metal sheet101,102is usually formed on an open region around the circuit layer100of the routing region, as shown inFIG.1BtoFIG.1E, so as to disperse the stress.

Furthermore, there is no signal transmission between the metal sheets101,102and the semiconductor chip11, and the metal sheets101,102are not beyond the routing region, such that a certain distance t is kept between the metal sheets101,102and an edge10cof the packaging substrate10.

With the requirements of multi-chip, high number of layers of redistribution layer (RDL), large dimension and high heat dissipation design, etc., multiple semiconductor chips11and other accessories will be carried on the packaging substrate10.

However, the shapes of the conventional metal sheets101,102corresponding to the right angles of the corners A, B, C or the routing path of the circuit layer100corresponding to the right angle of the corner D are in right-angle shapes P1, P2. Therefore, when the semiconductor package1is encountered with temperature cycle or stress changes, the stress is prone to concentrate on the metal sheets101,102, causing the packaging substrate10to warp and even causing the metal sheets101,102to break, which would crack the packaging substrate10or break the semiconductor chip11, thereby reducing the product yield.

Therefore, how to overcome the problems of the above-mentioned prior art has become an urgent problem to be solved at present.

SUMMARY

In view of the aforementioned shortcomings of the prior art, the present disclosure provides a circuit structure, which comprises: a dielectric layer having at least one corner at a right angle; a circuit layer formed on the dielectric layer and at the corner of the dielectric layer; and an electrical function part disposed at the corner of the dielectric layer, wherein a shape of the electrical function part at the corner and corresponding to the right angle is of a non-right angle shape and/or a routing path of the circuit layer at the corner and corresponding to the right angle is of a non-right angle shape.

In the aforementioned circuit structure, the non-right angle shape is a cut shape, an arc chamfer shape, or a multi-corner shape.

In the aforementioned circuit structure, the electrical function part is a metal sheet.

In the aforementioned circuit structure, the dielectric layer comprises a plurality of layers, and the circuit layer and/or the electrical function part are formed between any two adjacent ones of the plurality of dielectric layers.

In the aforementioned circuit structure, the dielectric layer has a rectangular surface having the four corners at right angles.

The present disclosure also provides an electronic package, which comprises: the aforementioned circuit structure; and an electronic element disposed on the circuit structure and electrically connected to the circuit layer.

In the aforementioned electronic package, the electronic element is grounded to the electrical function part.

In the aforementioned electronic package, the electrical function part has a dummy circuit function.

In the aforementioned electronic package, signal is free from being transmitted between the electrical function part and the electronic element.

In the aforementioned electronic package, the present disclosure further comprises an encapsulation layer covering the electronic element.

It can be seen from the above that in the electronic package and the circuit structure thereof of the present disclosure, the stress can be dispersed and the stress concentration can be reduced by the design of the non-right angle shapes of the electrical function parts corresponding to the right angles at the corners and/or the design of the non-right angle shape of the routing path of the circuit layer corresponding to the right angle at the corner. Therefore, compared with the prior art, warpage can be prevented from occurring to the circuit structure in the electronic package of the present disclosure, and problems such as the breakage of the electrical function parts that causes the cracking of the circuit structure or the breakage of the electronic element can also be avoided, so that the circuit layer can be effectively electrically connected to the electronic element, thereby improving product yield and product reliability.

DETAILED DESCRIPTION

The following describes the implementation of the present disclosure with examples. Those skilled in the art can easily understand other advantages and effects of the present disclosure from the contents disclosed in this specification.

It should be understood that, the structures, ratios, sizes, and the like in the accompanying figures are used for illustrative purposes to facilitate the perusal and comprehension of the contents disclosed in the present specification by one skilled in the art, rather than to limit the conditions for practicing the present disclosure. Any modification of the structures, alteration of the ratio relationships, or adjustment of the sizes without affecting the possible effects and achievable proposes should still be deemed as falling within the scope defined by the technical contents disclosed in the present specification. Meanwhile, terms such as “on,” “first,” “second,” “a,” “one,” and the like used herein are merely used for clear explanation rather than limiting the practicable scope of the present disclosure, and thus, alterations or adjustments of the relative relationships thereof without essentially altering the technical contents should still be considered in the practicable scope of the present disclosure.

FIG.2Ais a schematic top view showing an electronic package2of the present disclosure. As shown inFIG.2A, the electronic package2comprises: a circuit structure20, at least one electronic element21disposed on the circuit structure20, and an encapsulation layer23(shown inFIG.3B) covering the electronic element21.

The circuit structure20is a rectangular board, and a surface of the circuit structure20is defined with a routing region (e.g., a wiring/tracing region) for disposing the electronic element21and four corners A, B, C, D. As shown inFIG.2BtoFIG.2E, the routing region and the four corners A, B, C, D are configured with a circuit layer200, and at least one electrical function part201,202having a function of a dummy RDL or a dummy metal block is disposed at each of the four corners A, B, C, D.

In an embodiment, the circuit structure20is, for example, a packaging substrate with a core layer, or a coreless packaging substrate. The circuit structure20comprises at least one dielectric layer20a(as shown inFIG.3B) and the circuit layer200and the electrical function parts201,202bonded to the dielectric layer20a. For instance, an RDL process is used for the circuit structure20, and the material for forming the circuit layer200and the electrical function parts201,202is a metal such as copper, and the material for forming the dielectric layer20ais polybenzoxazole (PBO), polyimide (PI), prepreg (PP), or other dielectric materials.

Moreover, the electrical function parts201,202are metal sheets, and signal can be free from being transmitted between the electrical function parts201,202and the electronic element21according to requirements, and the electrical function parts201,202are not beyond the routing region, such that a certain distance t is kept between the electrical function parts201,202and an edge20cof the circuit structure20.

Furthermore, the electrical function parts201,202at the corners A, B, C of the circuit structure20and corresponding to the right angles are of non-right angle shapes, such as a cut shape R1shown inFIG.2BtoFIG.2D, so that the shapes of the electrical function parts201,202corresponding to the right angles of the corners A, B, C have at least three lines L1, L2, L3so as to facilitate stress dispersion. It should be understood that there are various aspects of the non-right angle shapes, such as an arc chamfer shape or a multi-corner shape (not shown), but the present disclosure is not limited to as such.

Similarly, the routing path of the circuit layer200at the corner D of the circuit structure20and corresponding to the right angle is of a non-right angle shape, such as a cut shape R2shown inFIG.2E, so that the routing path of the circuit layer200corresponding to the right angle of the corner D has at least three connected traces T1, T2, T3so as to facilitate stress dispersion. It should be understood that there are various aspects of the non-right angle shapes, such as an arc chamfer shape or a multi-corner shape (not shown), but the present disclosure is not limited to as such.

Additionally, referring toFIG.3Bat the same time, when the circuit structure20comprises multiple dielectric layers20a,20b, a circuit layer300and the electrical function parts201,202of non-right angle shapes at the corners A, B, C, D can also be disposed on any one of the dielectric layers20a,20b(i.e., not limited to the outermost circuit layer200and electrical function parts201,202).

The electronic element21is an active element, a passive element, or a combination of the active element and the passive element, wherein the active element is a semiconductor chip, and the passive element is a resistor, a capacitor, or an inductor.

In an embodiment, the electronic element21is a semiconductor chip, which is electrically connected to the circuit layer200via a plurality of conductive bumps210(as shown inFIG.3B) in a flip-chip manner; alternatively, the electronic element21can also be electrically connected to the circuit layer200via a plurality of bonding wires (not shown) in a wire-bonding manner; or, the electronic element21can directly contact the circuit layer200to electrically connect the circuit layer200. However, the way in which the electronic element21is electrically connected to the circuit layer200is not limited to the above.

Moreover, the electronic element21can be grounded to the electrical function parts201,202according to requirements. Thus, the functions of the electrical function parts201,202can be adjusted according to requirements without any special limitation.

The encapsulation layer23is made of an insulating material, such as PI, dry film, epoxy resin, epoxy colloid, or molding compound, and the encapsulation layer23can be formed on the circuit structure20by lamination or molding.

Therefore, in the circuit structure20, the shapes of the electrical function parts201,202at the corners A, B, C and corresponding to the right angles are of non-right angle shapes and/or the routing path of the circuit layer200at the corner D and corresponding to the right angle is of a non-right angle shape, such as the cut shapes R1, R2shown inFIG.2BtoFIG.2E, so that stress can be effectively prevented from concentrating at the right angles of the metal layer.

Furthermore, since the shapes of the electrical function parts201,202at the corners A, B, C and corresponding to the right angles are of non-right angle shapes and/or the routing path of the circuit layer200at the corner D and corresponding to the right angle is of a non-right angle shape (such as the cut shapes R1, R2shown inFIG.2BtoFIG.2E), the amount of metal laying at the corners A, B, C, D in the electronic package2can be reduced (for example, the metal can be a conventional metal sheet or a metal material103represented by an RDL as shown inFIG.3A, and a removed metal material303represented by the dotted lines as shown inFIG.3B). That is, the areas of the open regions (i.e., the regions with no metal material) at the corners A, B, C, D are increased, so that the resistance of the PI material (dielectric layer) and the metal material (circuit layer) to the peeling stress is increased, such that the upper dielectric layer20aand the lower dielectric layer20bcan be tightly bonded (i.e., the adhesion between the same material of the high polymer layers is much better than the adhesion between the high polymer layer and the metal layer). As such, the problem of delamination can be prevented from occurring between the upper dielectric layer20aand the lower circuit layer300.

In addition, the design of the non-right angle shapes of the electrical function parts201,202corresponding to the right angles at the corners A, B, C and/or the design of the non-right angle shape of the routing path of the circuit layer200corresponding to the right angle at the corner D can be realized by using the existing manufacturing process and existing equipment without adding additional manufacturing cost and time, thereby facilitating mass production.

To sum up, in the electronic package and the circuit structure thereof of the present disclosure, the stress can be dispersed and the stress concentration can be reduced by the design of the non-right angle shapes of the electrical function parts corresponding to the right angles at the corners and/or the design of the non-right angle shape of the routing path of the circuit layer corresponding to the right angle at the corner. Therefore, warpage can be prevented from occurring to the circuit structure in the electronic package of the present disclosure, and problems such as the breakage of the electrical function parts that causes the cracking of the circuit structure or the breakage of the electronic element can also be avoided, so that the circuit layer can be effectively electrically connected to the electronic element, thereby improving product yield and product reliability.

The above embodiments are provided for illustrating the principles of the present disclosure and its technical effect, and should not be construed as to limit the present disclosure in any way. The above embodiments can be modified by one of ordinary skill in the art without departing from the spirit and scope of the present disclosure. Therefore, the scope claimed of the present disclosure should be defined by the following claims.