Driving circuit, LED head and image forming apparatus

In a driving circuit, a drive transistor supplies drive electric current to record elements to construct an array, and a reference electric current generating circuit that provides a control voltage to the drive transistor and controls the drive electric current, wherein the drive transistor is composed of a first PMOS transistor and a second PMOS transistor that are connected in series; and the reference electric current generating circuit has a resistance element and a operational amplifier that are used to set a reference electric current for deciding the control voltage, wherein an output of the operational amplifier is provided to a control terminal of the first PMOS transistor; and a drive electric current ON/OFF signal to control on/off of the drive electric current is provided to a control terminal of the second PMOS transistor.

FIELD OF THE INVENTION

The invention relates to a driving circuit used in LED head, the LED head using the driving circuit and an image forming apparatus.

BACKGROUND OF THE INVENTION

A driving circuit used by LED head includes a LED driving and outputting section (hereinafter: LED driving and outputting circuit) to individually drive LED elements. A conventional LED driving and outputting circuit is constructed from a series connection of first and second PMOS transistors. A control voltage corresponding to a drive electric current value is supplied to gate of the first PMOS transistor, and a drive ON/OFF instruction signal is inputted to gate of the second PMOS transistor.

As stated in the a patent document 1 of Japan patent publication Hei 11-291550 and a patent document 2 of Japan patent publication 2001-056669, in the conventional LED driving and outputting circuit, because the control voltage corresponding to a drive electric current value is always supplied to the gate of the first PMOS transistor, its drain is kept by a voltage which is approximately equal to a power source voltage. Thereby, when a drive ON instruction signal is inputted to the gate of the second PMOS transistor in order to drive LED element to turn on, with the second PMOS transistor becomes ON, electric charge that keeps the drain in the voltage approximately equal to a power source voltage is discharged via the second PMOS transistor and LED element without any electric current control. As a result, when electric current that flows through LED element rises, peak electric current flows sharp. Because of the excessive peak electric current, the LED element degrades and its life becomes short.

SUMMARY OF THE INVENTION

It is, therefore, an object of the invention to provide a driving circuit capable of solving the above problem.

A first aspect of the invention is to provide a driving circuit. The driving circuit comprises a drive transistor that supplies drive electric current to record elements to construct an array; and a reference electric current generating circuit that provides a control voltage to the drive transistor and controls the drive electric current, wherein the drive transistor is composed of a first drive transistor and a second drive transistor that are connected in series; and the reference electric current generating circuit has a resistance element and a operational amplifier that are used to set a reference electric current for deciding the control voltage, wherein an output of the operational amplifier is provided to a control terminal of the first drive transistor; and a drive electric current ON/OFF signal to control on/off of the drive electric current is provided to a control terminal of the second drive transistor.

A second aspect of the invention is to provide a driving circuit. The driving circuit comprises a driving section that supplies drive electric current to record elements to construct an array; and a reference electric current generating circuit that provides a control voltage to the driving section and controls the drive electric current, wherein the drive section is composed of N series connection circuits that are connected in parallel, each series connection circuit being composed of a first drive transistor, a second drive transistor and a third drive transistor that are connected in series; and the reference electric current generating circuit has a resistance element and a operational amplifier that are used to set a reference electric current for deciding the control voltage, wherein an output of the operational amplifier is provided to a control terminal of the first drive transistor, a drive electric current adjustment signal to adjust an electric current value of the drive electric current is provided to a control terminal of the second drive transistor, and a drive electric current ON/OFF signal to control on/off of the drive electric current is provided to a control terminal of the third drive transistor.

A third aspect of the invention is to provide a driving circuit. The driving circuit comprises a driving section that supplies drive electric current to record elements to construct an array; and a reference electric current generating circuit that provides a control voltage to the driving section and controls the drive electric current, wherein the drive section has a main driving section that is composed of a first drive transistor and a second drive transistor that are connected in series; and a subsidiary driving section that is composed of N series connection circuits that are connected in parallel, each series connection circuit being composed of a first drive transistor, a second drive transistor and a third drive transistor that are connected in series, wherein the reference electric current generating circuit has a resistance element and a operational amplifier that are used to set a reference electric current for deciding the control voltage, wherein an output of the operational amplifier is provided to a control terminal of the first drive transistor, a drive electric current adjustment signal to adjust an electric current value of the drive electric current is provided to a control terminal of the second drive transistor, and a drive electric current ON/OFF signal to control on/off of the drive electric current is provided to a control terminal of the third drive transistor.

Further, the invention provides a LED head comprising the driving circuit of in the first, second and third aspects of the invention.

Furthermore, the invention provides an image apparatus has the LED head comprising the driving circuit of in the first, second and third aspects of the invention.

EFFECT OF THE INVENTION

According to the invention, the drive transistor is constructed by a series connection of a first drive transistor and a second drive transistor, an output of the operational amplifier is supplied to the control terminal of the first drive transistor, and a drive electric current ON/OFF signal to control ON/OFF of drive electric current is supplied to the control terminal of the second drive transistor, further, the output of the operational amplifier is moved for a predetermined time by a delaying circuit. Therefore, when the drive of LED is turned off, the first drive transistor becomes OFF-state; when preparing to drive the drive electric current of LED, the second drive transistor previously becomes ON-state. Therefore, without an accumulation of electric charge for parasitic capacitance of drain terminal of the first drive transistor, through a movement toward drive-ON of LED, the first drive transistor becomes ON-state, even if the drive electric current of LED rises, overshoot does not occur. As a result, it is possible to prevent excessive overshoot from occurring when electric current of LED rises; to prevent degradation of LED that is caused by peak electric current; and to prevent the life of LED from shortening.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Embodiments of the invention will be described in detail hereinbelow with reference to the drawings.

First is to explain whole structure of a controlling system in an image forming apparatus including a driving circuit of the present invention, and explain its operation summary. In the explanation, regarding technology content in problem to be solved, it will be again explained in detail by using drawing.

FIG. 1is a block diagram of a printer controlling system in electrophotographic printer.

As shown byFIG. 1, a printer controlling system in electrophotographic printer comprises a print controlling section1, a driver2, a developing/transferring process use motor3, a driver4, a paper conveyance motor5, a paper inhalation opening sensor6, a paper ejection opening sensor7, a paper remainder amount sensor8, a paper size sensor9, a LED head19, a fixing device22, a fixing device temperature sensor23, a charge use high voltage power source25, a transfer use high voltage power source26, a developing device27and a transferring device28.

The print controlling section1, as a function block to perform a computer control function, is a part that uses RAM, input and output ports, timer and the like to control print process, through a microprocessor (not shown) executes predetermined control program previously stored in a ROM (not shown).

The print controlling section1is furnished inside a printing section of printer; sequences and controls the whole of the printer through control signal SG1, video signal SG2(obtained by arrange dot map data in one dimension) and the like that come from a host controller (not shown); and performs print operation. When the print controlling section1received a print instruction through the control signal SG1, firstly, the print controlling section1uses the fixing device temperature sensor23to detect whether a temperature of the fixing device22with a built-in heater22ais in a usable temperature range; if it is not in the usable temperature range, turns the heater22aon the electric current so as to heat the fixing device22till a usable temperature.

Next, the print controlling section1controls the developing/transferring process use motor (PM)3to rotate via the driver2, at the same time, turns the charge use high voltage power source25on through a charge signal SGC so as to perform a charge of the developing device27. Then, an existence/inexistence and a kind of paper (not shown) that is set are detected by the paper remainder amount sensor8and the paper size sensor9, and a paper conveyance suitable to the paper is started. Here, the paper conveyance motor (PM)5can rotate in two directions via the driver4. Firstly, the paper conveyance motor5rotates along a converse direction to convey the paper only by a predetermined amount till the paper inhalation opening sensor6detected the paper. Continuously, the paper conveyance motor5rotates along a regular direction to convey the paper into a print mechanism inside the printer.

Here is to explain timing about control signals SG1, SG2, SG3, HD-DATA, HD-CLK, HD-LOAD, HD-STB-N that are sent or received by the print controlling section1.

FIG. 2is a timing chart of control signals in embodiment 1.

In the drawing, according to an order from top to bottom, a timing signal SG3, a video signal Sg2, a print data signal HD-DATA, a clock signal HD-CLK, a latch signal HD-LOAD, a strobe signal HD-STB-N are indicated. Through a control signal SG1(not shown) is inputted to the print controlling section1(FIG. 1) from a host controller (not shown), a series of operations described below are started.

At the time that the paper reaches a printable position, the print controlling section1(FIG. 1) sends timing signal SG3(containing main movement synchronized signal and subsidiary movement synchronized signal), and receives video signal SG2. The receiving of the video signal SG2is performed per print line. The video signal SG2that is edited per page in the host controller and is received by the print controlling section1(FIG. 1) is forwarded to the LED head19(FIG. 1) as the print data signal HD-DATA. The LED head19(FIG. 1) is formed by arranging plural LED elements on plural line for print respective dots (pixels).

Then, the print controlling section1(FIG. 1), when received the video signal SG2of one line part, sends the latch signal HD-LOAD to the LED head19(FIG. 1), and controls data that is forwarded via the print data signal HD-DATA to be kept in the LED head19(FIG. 1). Further, even if the print controlling section1is receiving next video signal SG2from the host controller, the print controlling section1(FIG. 1) also can print data kept in the LED head19(FIG. 1) concerning the print data signal HD-DATA. Moreover, the HD-CLK is clock signal for sending the print data signal HD-DATA to the LED head19, the HD-STB-N is strobe signal. The following is continuously explain the printer controlling system in the electrophotographic printer by referring toFIG. 1again.

Information printed by the LED head19, as dots whose electric potential rose, is changed to an electrostatic latent image on a photosensitive drum (not shown) which is charged by minus electric potential. Then, in the developing device27, toner which is charged by minus electric potential and is used for image formation use is absorbed electrically by respective dots so that a toner image is formed.

After that, on the one hand, the toner image is conveyed to the transferring device28; on the other hand, the transfer use high voltage power source26with plus electric potential is turned on by a transfer signal SG4(FIG. 1). The transferring device28transfers the toner image onto paper passing through the interval of the photosensitive drum and the transferring device28.

The paper having the transferred toner image is conveyed to contact with the fixing device22with a built-in heater22a, and the toner image is fixed on the paper by the heat of the fixing device22. The paper having the fixed image is further conveyed to pass the paper ejection opening sensor7from the print mechanism of the printer, and is ejected to the outside of the printer.

To correspond to the detections of the paper size sensor9and the paper inhalation opening sensor6, the print controlling section1supplies voltage outputted from the transfer use high voltage power source26to the transferring device28only when the paper passes the transferring device28. Then, after print ended and the paper passed the paper ejection opening sensor7, the print controlling section1stops supplying voltage outputted from the charge use high voltage power source25to the developing device27together with stopping the rotation of the developing/transferring process use motor3. Hereafter, the above-described operations are repeated. In the above explanation, the driving circuit of the present invention is contained in the LED head19. The following is to explain a summary of the LED head19.

FIG. 3is a block diagram showing a structure of a LED head in embodiment 1.

The drawing shows a connection relation between the LED head19and the print controlling section1. As shown byFIG. 3, the print controlling section1is connected with the LED head19via a connection cable47. (Note: the “->>-” in drawing is circuit symbol to represent connection connector.)

In the following explanation, an example is given about a LED head which can perform print with respect to paper of A4 size in a resolution of 600 dots per one inch. Then, its concrete structure will be explained. In the example, the total number of the LED elements is 4992 dots. For that, 26 LED arrays are arranged, and each array includes 192 LED elements.

In the drawing, CHP(1)˜CHP(26) are LED arrays, the representation of CHP(2)˜CHP(24) is omitted. IC(1)˜IC(26) are driver to correspond to the CHP(1)˜CHP(26). The LED arrays CHP(1)˜CHP(26) are used to drive. Each driver IC is an integrated circuit that integrates driving circuits.

Each driver IC is formed by an identical circuit, two adjoining driver ICs are connected by cascading. LED(1)˜LED(192) are LED elements belonging to LED array CHP(1). In each LED array, 192 LED elements are furnished. Thus, LED(4609)˜LED(4800) belongs to LED array CHP(25) and LED(4801)˜LED(4992) belongs to LED array CHP(1).

Therefore, in the LED head19shown byFIG. 3, on a print wiring board (not shown), 26 LED arrays (CHP(1)˜CHP(26)) and 26 driver ICs (IC(1)˜IC(26)) to respectively drive the CHP(1)˜CHP(26) are arranged and furnished as facing each other. Each driver IC, as one chip, can drive 192 LED elements, thus, 26 chips are connected in cascade so that print data inputted from the outside can be serially forwarded.

Regarding the structure shown byFIG. 3, it is sequentially explained below.

The respective drivers IC(1)˜IC(26) are formed by an identical circuit and are connected in cascade. The driver IC includes a shift register circuit44that receives the clock signal HD-CLK to perform a shift forwarding of print data; a latch circuit43that latches output signal of the shift register circuit44according to the latch signal HD-LOAD; an inverter circuit41; a logical circuit42; a LED driving and outputting circuit40that supplies drive electric current outputted from power source voltage VDD to the LED element (CHP(1) etc.) according to the output signal of the logical circuit42; and a control voltage generating circuit45that generates an instruction voltage so that the drive electric current of the LED driving and outputting circuit40becomes constant. Moreover, it will be explained later that the driving circuit (driver IC) in the embodiment 1 has characters in the LED driving and outputting circuit40, the logical circuit42, and the control voltage generating circuit45.

The strobe signal HD-STB-N is inputted to the inverter circuit41. Further, there is a reference voltage generating circuit46, its power source is connected with the power source voltage VDD, its ground terminal is connected with the ground of the LED head19, its output is connected with the control voltage generating circuits45of the IC(1)˜IC(26) so as to supply a predetermined reference voltage Vref. Moreover, the respective signals of the print data signal HD-DATA, the clock signal HD-CLK, the latch signal HD-LOAD and the strobe signal HD-STB-N are sent from the print controlling section1when printing.

Next, before explaining in detail the LED driving and outputting circuit40and its peripherals circuit in that the present invention is applied, in order to clear the character of the LED driving and outputting circuit40and its peripherals circuit of the present invention, first is to explain in detail a conventional peripherals circuit of the LED driving and outputting circuit40and its circuit operation in a comparison example. In the explanation, a problem to be solved will be mentioned again.

FIG. 4is a diagram showing a peripherals circuit of a LED drive output circuit in a comparison example.

InFIG. 4, a conventional peripherals circuit of the LED driving and outputting circuit40is shown. As shown byFIG. 4, the conventional peripherals circuit includes a LED driving and outputting circuit40, an inverter circuit41, a logical circuit42a, a latch circuit43and a control voltage generating circuit45a.

In the drawing, the logical circuit42ais a NAND circuit. In the driver IC (driving circuit) shown byFIG. 3, because 192 drive output terminals are provided, so in the logical circuit42a, the latch circuit43, PMOS transistors52,53that are described below, respectively, 192 drive terminals are provided. With respect to such structure, the control voltage generating circuit45a, as an inside component element of the driver IC, only has a terminal for each driver IC.

An input D of the latch circuit43is connected with an output of a shift register circuit (not shown, it is equal to the shift register circuit44inFIG. 3), an input G receives a latch signal HD-LOAD. An output Q of the latch circuit43is connected with one input terminal of the logical circuit42.

In the LED driving and outputting circuit40, there are two PMOS transistors52and53. A source terminal of the PMOS transistor52is connected with a power source voltage VDD, a drain terminal of the PMOS transistor52is connected with a source terminal of the PMOS transistor53, a drain terminal of the PMOS transistor53is connected with an anode of a LED (1). A gate terminal of the PMOS transistor53is connected with an output terminal of the logical circuit42a, a gate terminal of the PMOS transistor52is connected with an output terminal of a operational amplifier61that is described below.

In the control voltage generating circuit45a, as shown in drawing, a operational amplifier61has an output voltage an electric potential Vcont; a resistance63has a resistance value Rref. Further, there is a PMOS transistor62, its gate length is equal to that of the PMOS transistor52. VREF is a reference voltage generated by the reference voltage generating circuit46inFIG. 3, and it is supplied to a reversion input terminal of the operational amplifier61.

A source terminal of the PMOS transistor62is connected with the power source voltage VDD, a gate terminal of the PMOS transistor62is connected with an output terminal of the operational amplifier61, a drain terminal of the PMOS transistor62is connected with one end of the resistance63and with a non-reversion input terminal of the operational amplifier61. The operational amplifier61, the PMOS transistor62and the resistance63constructs a feedback control circuit, in which, the electric current flowing through the resistance Rref, that is, the electric current flowing through the PMOS transistor62, is decided only by the values of the Vref and the Rref without depending upon the power source voltage VDD.

The gate electric potentials of the PMOS transistor52and the PMOS transistor62are equal to the Vcont, their source electric potentials also are equal. Because of that, the PMOS transistor52and the PMOS transistor62have equal voltage between gate and source so that they have a relation of current mirror.

Thus, by the reference voltage Vref, it is possible to adjust drain electric current of the PMOS transistor62and the PMOS transistor52, and it is possible to control the drive electric current of the LED (1) belonging to the LED array72at a predetermined value.

Further, the PMOS transistor53is instructed to drive on through the print data latched by the latch circuit43. When the strobe signal HD-STB-N becomes ON, the gate electric potential of the PMOS transistor53is changed to Low level, becomes ON-state. At that time, the drain electric current produced in the PMOS transistor53is decided according to the voltage supplied in between gate and source of the PMOS transistor62or the PMOS transistor52, the PMOS transistor53functions as a switching element to switch on or off the electric current.

Further, in the LED driving and outputting circuit40, there is a condenser54, its one end is connected with the drain terminal of the PMOS transistor52, its other end id connected with ground. The condenser54models and represents the parasitic capacitance generating between the drain terminal of the PMOS transistor52and the source terminal of the PMOS transistor53, when the PMOS transistor52always is in ON-state and the PMOS transistor53is turned off, the electric potential of the drain terminal of the PMOS transistor52approximately is equal to the electric potential VDD, the condenser54is also charged by the electric potential VDD.

Because of that, with the drive state of the LED (1) is changed from OFF to ON, the PMOS transistor53moves from OFF to ON, at that time, the electric charge charged in the condenser54is rapidly discharged toward the LED (1). With an completion of discharging, the anode electric current of the LED (1) becomes an electric current value according to the drive state of the PMOS transistor52, the great overshoot caused by the discharged electric current is inhibited. Regarding the concrete content, it will be explained by using a timing chart.

FIG. 5is a timing chart for explaining operation of a LED drive output circuit in a comparison example.

As shown byFIG. 5, according to the clock signal HD-CLK and the print data signal HD-DATA, print data is forwarded; continuously, according to the latch signal HD-LOAD, the forwarded print data is latched; further, according to the strobe signal HD-STB-N, the LED (1) (FIG. 4) is driven on the basis of the forwarded print data.

As shown by part “A” inFIG. 5, when the strobe signal HD-STB-N drops, the LED (1) (FIG. 4) is started to drive. At that time, as shown by the rise part in electric current waveform, great overshoot occurs. The overshoot waveform is inhibited in a shorter time, then, the electric current is kept in a predetermined electric current value as shown by part “B” inFIG. 5. With the strobe signal HD-STB-N becomes ON, as shown by part “C”, the electric current returns to zero.

The peak value of the overshoot electric current is generated when connectively discharging electric charge that is charged in the parasitic condenser (FIG. 4) toward the LED (1) via the switch formed by the PMOS transistor53. Because of resistance components to limit electric current such as an ON-resistance of the PMOS transistor53, a wiring resistance of the inside of the LED (1) and the like, even if they are very little resistance, the peak electric current value caused by the resistance reaches a value that is several decades times the value assumed as a drive condition of the LED (1).

In the case that such excessive electric current flows through the LED element, even if its continuing time is short, the influence is not small. It will make the LED element degrade and drop light emitting efficiency for a long period. Because the overshoot electric current is caused by some factors to make correct control become difficult such as the ON-resistance of the PMOS transistor53, the wiring resistance of the inside of the LED (1) or the like, in LED head device including plural LED elements, in the case that to use these LED elements for a long time, their degradation statuses are different. As a result, between light emitting powers of these LED elements, difference occurs so that print density becomes uneven, it is not desirable.

The structure of the PMOS transistor52and the PMOS transistor53is used to drive driven-element through furnishing a second transistor that serves as a switch element to control drive state to become ON or OFF, onto a first transistor that controls drive electric current. As similar structure, it is well-known as disclosed by the patent document 2 of Japan patent publication 2001-056669.

The driving circuit of the patent document 2 drives driven-element that is connected with it, through furnishing a first transistor serving as a switching element to control drive state to become ON or OFF and furnishing a second transistor that controls drive electric current onto the first transistor. Though such structure can obtain an effect to reduce overshoot electric current caused when starting to drive the driven element, because the first transistor is intervening, difference occurs in electric current instruction state of the second transistor due to unevenness of ON-resistance of the first transistor, then, new electric current value unevenness occurs in each drive output terminal. Thereby, it is impossible to completely solve such problem.

The above description explained the problem to be solved concerning the present invention. The following is to explain in detail a driving circuit of the present invention in detail.

FIG. 6is a diagram showing a peripherals circuit of a LED drive output circuit in the present invention.

InFIG. 6, a peripherals circuit structure of the LED driving and outputting circuit40of the present invention is shown. As shown byFIG. 6, the peripherals circuit structure of the present invention includes a LED driving and outputting circuit40, an inverter circuit41, a logical circuit42, a latch circuit43and a control voltage generating circuit45. In the drawing, a connection relation between the LED driving and outputting circuit40and the peripherals circuit is shown, as a representation, the LED (1) is expressed to correspond to one dot. The following is to only explain in detail the different part different from the comparison example. Regarding the same part as the comparison example, it is appended the same symbol and its explanation is omitted.

The logical circuit42contains a delay circuit66, a PMOS transistor67to form an inverter, and a NMOS transistor68. An input terminal of the delay circuit66is connected with an output of the inverter circuit41, and is supplied by a positive logic strobe signal STB-P. An output terminal of the delay circuit66is connected with gate terminals of the PMOS transistor67and the NMOS transistor68that construct an inverter.

In the PMOS transistor67and the NMOS transistor68to construct an inverter, a source terminal of the PMOS transistor67is connected with a power source voltage VDD, a drain terminal of the PMOS transistor67is connected with a drain terminal of the NMOS transistor68, a source terminal of the NMOS transistor68is connected with an output terminal of the operational amplifier61. The two gate terminals of the PMOS transistor67and the NMOS transistor68are connected with the output of the delay circuit66. Further, the two drain terminals of the PMOS transistor67and the NMOS transistor68are connected with a gate terminal of the PMOS transistor52. Moreover, the gate electric potential of the PMOS transistor52is marked by Vcont as shown in drawing.

The latch circuit43is connected with the gate of the PMOS transistor53(FIG. 4) via the logical circuit42a(FIG. 4) in comparison example, but is directly connected with the gate of the PMOS transistor53without the logical circuit42in eh present invention.

As compared the control voltage generating circuit45with the control voltage generating circuit45a(FIG. 4) in comparison example, in the control voltage generating circuit45, a NMOS transistor65is inserted between a resistance63and ground. That is, a source terminal of the PMOS transistor62is connected with the power source voltage VDD, a gate terminal of the PMOS transistor62is connected with an output terminal of the operational amplifier61, and a drain terminal of the PMOS transistor62is connected with one end of a resistance63and a non-reversion terminal of the operational amplifier61. Another end of the resistance63is connected with a drain terminal of the NMOS transistor65, a source terminal of the NMOS transistor65is connected with the ground. Further, a trapezoid wave circuit64is connected with a gate terminal of the NMOS transistor65, the positive logic strobe signal STB-P is inputted to an input terminal of the trapezoid wave circuit64.

The operational amplifier61, the PMOS transistor62, the resistance63, and the NMOS transistor65construct a feedback control circuit, in the structure, the electric current that flows through the resistance63and the PMOS transistor62is decided by the Vref, the Rref and the value of ON-resistance of the NMOS transistor65without depending upon the power source voltage VDD. Further, the output of the operational amplifier61is connected with the source terminal of the NMOS transistor68.

In the circuit structure, when preparing to drive the LED (1), the positive logic strobe signal STB-P becomes “High” level. The positive logic strobe signal STB-P is the same as the positive logic strobe signal STB-P which serves as input signal after being delayed by the delay circuit66. At that time, the PMOS transistor67becomes OFF state, and the NMOS transistor68becomes ON state.

In such state, the gate electric potential of the PMOS transistor62is equal to the Vcont, and the source electric potentials of the PMOS transistor62and the PMOS transistor52are equal. In the PMOS transistor62and the PMOS transistor62, because the voltages between gate and source are equal, they have a relation of current mirror. Thus, by the reference voltage Vref, it is possible to adjust drain electric current of the PMOS transistor62and the PMOS transistor52, and it is possible to control the drive electric current of the LED (1) belonging to the LED array72at a predetermined value.

Here is to explain operation when driving the LED (1).

The gate electric potential of the PMOS transistor53is set according to the print data latched by the latch circuit43. When the print data becomes ON so that a drive instruction is formed, the output Q of the latch circuit43becomes “High”, and the output terminal QN becomes “Low” level. Because the output signal of the terminal QN is inputted to the gate of the PMOS transistor53, the PMOS transistor53becomes ON. As stated below, at that time, because the PMOS transistor52does not yet become ON state, the drive electric current of LED does not yet occur.

Next, when the positive logic strobe signal STB-P becomes ON, the output signal of the trapezoid wave circuit64becomes “High” level, the NMOS transistor65becomes ON state, so the another end is connected with the ground. At that time, the drain electric current (Iref) of the PMOS transistor62is mainly decided by the reference voltage Vref and the resistance value Rref, then, electric current having a proportion relation with the drain electric current Iref occurs in the PMOS transistor52. Thus, drive electric current flows through the PMOS transistor53which is in ON state to drive the LED (1) via an output terminal (not shown).

Next, it is to sequentially explain the structures of the drive transistor, the delay element, and the trapezoid wave circuit.

FIG. 7is a cross section of a drive transistor in embodiment 1.

InFIG. 7, the structures of a drive transistor, the PMOS transistor52and the PMOS transistor53are shown. The cross section is obtained along a direction which is orthogonal with wirings of source, gate and drain of the drive transistor.

In the structure, there are an IC chip81, a P type region82which represents a substrate layer, a N type well region83formed in the P type region82, and P type regions84˜86formed in the N type well region83. Further, there is a gate wiring87, it corresponds to the gate of the PMOS transistor52inFIG. 6, and there is a gate wiring88, it corresponds to the gate of the PMOS transistor53inFIG. 6, their gate lengths respectively are “L1” and “L2” as shown byFIG. 7.

Furthermore, there are a metal wiring89which is connected with the P type region84(corresponding to the source terminal of the PMOS transistor52) and with the power source voltage VDD (not shown); a metal wiring90which is connected with the P type region86(corresponding to the drain terminal of the PMOS transistor53) and with a drive output terminal (not shown); and a protective film91covering on the upper surface of the IC chip81.

FIG. 8Ais a diagram showing a logical symbol for explaining a structure of a delaying element;FIG. 8Bis a diagram showing an internal circuit for explaining a structure of a delaying element; andFIG. 8Cis a diagram showing waveforms of input terminal, output terminal and internal node for explaining a structure of a delaying element.

InFIG. 8B, a buffer circuit94, a resistance95, a condenser96and an OR circuit97are shown. An input terminal of the buffer circuit94corresponds to the input terminal A of the delay circuit66, an output terminal of the buffer circuit94is connected with one end of the resistance95; another end of the resistance95is connected with one input terminal of the OR circuit97and one end of the condenser96. Another end of the condenser96is connected with ground. Further, another input terminal of the OR circuit97is connected with the input terminal A, an output terminal of the OR circuit97corresponds to an output terminal Y of the delay circuit66.

In theFIG. 8C, an input waveform A of the input terminal A is shown; an output waveform B of the buffer circuit94is shown; a terminal waveform C of the condenser96is shown; and an output waveform Y of the OR circuit97is shown. As shown by the input waveform A, when a signal A is inputted to the input terminal A, through a little signal delay, the waveform B is outputted.

The signal B is inputted to the one end of the resistance95, then, the charge/discharge waveform C occurs on the basis of a time constant decided by the resistance95and the condenser96. The waveform C is inputted to the one input terminal of the OR circuit97, and the signal A is inputted to another input terminal of the OR circuit97. Then, the OR circuit97performs a logical calculation according to the waveform C and the signal A, and generates the output waveform Y, as shown by the drop part of the output waveform Y, a delay time Td is provided.

FIG. 9Ais a diagram showing a logical symbol of a trapezoid wave circuit for explaining structures of trapezoid wave circuit and its peripherals circuit;FIG. 9Bis a diagram showing an internal structure of a trapezoid wave circuit for explaining structures of trapezoid wave circuit and its peripherals circuit; andFIG. 9Cis a diagram showing waveforms of input terminal, output terminal and internal node for explaining structures of trapezoid wave circuit and its peripherals circuit.

InFIG. 9B, a resistance98and a condenser99are shown. One end of the resistance98is an input terminal of the trapezoid wave circuit64; another end of the resistance98is an output terminal of the trapezoid wave circuit64and is connected with the condenser99and with the gate terminal of the NMOS transistor65.

In theFIG. 9C, a positive logic strobe signal STB-P is an input waveform of the trapezoid wave circuit64. Vg is a gate waveform of the NMOS transistor65. Rds represents a resistance between drain and source of the NMOS transistor65. Y is an output waveform of the delay circuit66shown byFIG. 8. Vcont is a gate terminal waveform of the PMOS transistor52. Iref is electric current flowing to the resistance63.

When the positive logic strobe signal STB-P is inputted and moves to “High” from “Low”, the waveform Vg slowly rises. The waveform Vg is provided to the gate terminal of the NMOS transistor65, the resistance Rds between drain and source slowly decreases from a value of infinity and drops to a value approximately approaching “0” Ohm. The resistance Rds is added to the resistance value Rref of the resistance63to decide the reference electric current Iref. Then, the waveform of the reference electric current Iref is obtained as slowly rising.

Further, at that time, the waveform Y moves to “High” from “Low” so as to make the NMOS transistor68change to ON state from OFF state. As a result, the waveform Vcont occurs a change from an electric potential approximately being equal to the power source voltage VDD to the output electric potential of the operational amplifier61, as shown by the drawing, the Vcont changes by dropping a voltage Vgs between gate and source of the PMOS transistor52.

Next, when the strobe signal STB-P changes from “High” level to “Low” level, the waveform Vg slowly drops. The waveform Vg is provided to the gate terminal of the NMOS transistor65so as to make the resistance Rds between drain and source slowly increase about from “0” Ohm and change to a value of infinity (i.e. OFF state). The resistance Rds between drain and source of the NMOS transistor65and the resistance value Rref of the resistance63are added to decide the reference electric current Iref, as shown by the waveform of the reference electric current Iref, the reference electric current Iref slowly drops.

At that time, the waveform Y has a change to move from “High” to “Low” after a delay time Td, so that the PMOS transistor67inFIG. 6moves to ON state from OFF state, and the NMOS transistor68changes from ON state to OFF state. As a result, the waveform Vcont occurs a change from the output electric potential of the operational amplifier61to an electric potential approximately being equal to the power source voltage VDD, as shown by the drawing, the Vcont changes to rise a voltage Vgs between gate and source of the PMOS transistor52till the electric potential approximately being equal to the power source voltage VDD.

Regarding circuit operation in the case that the strobe signal STB-P is inputted to the peripherals circuit of the LED driving and outputting circuit, moves to “High” from “Low”, and moves again to “Low” from “High”, it is explained again by usingFIG. 6.

When the strobe signal STB-P is inputted to the trapezoid wave circuit64of the control voltage generating circuit45, as shown by the waveform of Vg shown byFIG. 9, the Vg signal slowly rises. The Vg signal is provided to the gate terminal of the NMOS transistor65so as to make the resistance Rds between drain and source slowly decrease about from a value of infinity and drop to a value approximately approaching “0” Ohm.

Then, the resistance Rds between drain and source of the NMOS transistor65and the resistance value Rref of the resistance63are added to decide the reference electric current Iref, as shown by the waveform of the reference electric current Iref, the reference electric current Iref slowly rises. At that time, the waveform Y has a change to move from “Low” to “High”, so that the PMOS transistor67inFIG. 6moves to OFF state from ON state, and the NMOS transistor68changes from OFF state to ON state.

As a result, as shown by the waveform Vcont, the Vcont signal is switched from the electric potential approximately being equal to the power source voltage VDD to the output electric potential of the operational amplifier61, as shown byFIG. 9, the voltage between gate and source of the PMOS transistor52drops from VDD to Vgs. Thereby, the reference electric current Iref rises slowly from about “0” to a predetermined electric current value.

The PMOS transistor52, as a drive transistor of LED, has a current mirror relation with the reference electric current Iref, therefore, LED drive electric current also slowly rises from about “0” to a predetermined electric current value.

Continuously, when the strobe signal STB-P changes from “High” level to “Low” level, as shown byFIG. 9, the waveform Vg slowly drops. The Vg signal of the waveform Vg is provided to the gate terminal of the NMOS transistor65so as to make the resistance Rds between drain and source slowly increase about from “0” Ohm and change to a value of infinity (i.e. OFF state).

The resistance Rds between drain and source of the NMOS transistor65and the resistance value Rref of the resistance63are added to decide the reference electric current Iref, as shown byFIG. 9, a waveform of the reference electric current Iref is obtained that the reference electric current Iref slowly drops.

At that time, the waveform Y shown byFIG. 9has a change to move from “High” to “Low” after a delay time Td, so as to make the PMOS transistor67move to ON state from OFF state, and make the NMOS transistor68change from ON state to OFF state. As a result, the Vcont signal of the waveform Vcont is switched from the output electric potential of the operational amplifier61to an electric potential approximately being equal to the power source voltage VDD, as shown byFIG. 9, the voltage between gate and source of the PMOS transistor52rises from Vgs to the electric potential approximately being equal to the power source voltage VDD. At the same time, the reference electric current Iref slowly drops from a predetermined electric current value to about “0”.

Because the PMOS transistor52, as a drive transistor of LED, has a current mirror relation with the reference electric current Iref, so the LED drive electric current also slowly drops from a predetermined electric current value to about “0”. Thus, a series of operations complete that the LED drive becomes an ON state from an OFF state, and again becomes an OFF state from an ON state. Hereby, the explanation about the peripherals circuit of the LED driving and outputting circuit of the present invention and its circuit operation is finished.

Further, it is to perform a supplement explanation about that the gate length L1of the PMOS transistor52is set to be longer than the gate length L2of the PMOS transistor53as shownFIG. 7.

The gate length L1of the PMOS transistor52is set to be equal to the gate length of the PMOS transistor62. The PMOS transistor52and the PMOS transistor62form a current mirror circuit because their source electric potentials and gate electric potentials are respectively equal. Therefore, the drive electric current of LED (1) is kept in a scale relation with the reference electric current Iref. So it is possible to obtain drive electric current that correspond to the reference voltage Vref.

On the one hand, in the case to drive LED, it is not desirable that the drive electric current of LED changes according to the change of a regular direction voltage of LED. In order to greatly form output impedance of the drive electric current and improve its constant electric current character, the gate length L1of the PMOS transistor52is set into a comparative long size. On the other hand, the PMOS transistor53only performs an action of switch element, it is possible to set the gate length L2into a shortest size allowed in semiconductor manufacturing process, so that the area of the transistor becomes smaller.

Here, the gate electric potential of the PMOS transistor52is kept in an approximate constant electric potential, even if when switching on the drive state of LED or switching off the drive state of LED, on the gate terminal of the PMOS transistor52, charge electric current or discharge electric current does not occur. Thus, because charge electric current or discharge electric current also does not occur on the output terminal of the operational amplifier61, such problem does not occur that the time changes which is used for rising electric current waveform when drive is turned on according to an amount of synchronous drive dot number of LED array chip72.

Explanation of Effect:

As explained above, in the embodiment, a drive element furnished for driving LED serves as a circuit formed from a series connection of first and second PMOS transistors, the first PMOS transistor, as a constant electric current source, has a function to decide drive electric current value of LED, the second PMOS transistor, as a switch element, has a function to shut off the constant electric current source when LED drive is turned off. Further, the movement of ON state/OFF state of the LED drive, as change of electric potential between gate and source of the first PMOS transistor, is instructed to all output terminals. Furthermore, the movement of ON state/OFF state of the second PMOS transistor is performed while the first PMOS transistor is in OFF state. As a result, in the movement of ON state/OFF state of the LED drive, charge electric current or discharge electric current caused by electric charge accumulated in parasitic capacitance does not occur. Therefore, such problem does not occur that the time changes which is used for rising or dropping electric current waveform when drive is turned on or off according to an amount of synchronous drive dot number of LED.

Further, when turning off the drive of LED, in the case that the first PMOS transistor is in OFF state and prepares to drive the drive electric current of LED, the second PMOS transistor previously is in ON state. Therefore, in the parasitic capacitance of the drain terminal of the first PMOS transistor, the accumulation of electric charge does not exist, the first PMOS transistor becomes ON state according to the movement that the drive electric current of LED becomes ON, even if the drive electric current of LED is rising, overshoot does not occur. As a result, it is possible to prevent excessive overshoot from occurring when electric current of LED rises; to prevent degradation of LED that is caused by peak electric current; and to prevent the life of LED from shortening.

Furthermore, because the movement of ON state/OFF state of the second PMOS transistor is performed while the first PMOS transistor is in OFF state, it is possible to prevent noise voltage cause by rapid drive electric current from happening when performing the movement of ON state/OFF state of the second PMOS transistor, so that error operation can be prevented in respective circuits.

In the embodiment 2, the peripherals circuit of the LED driving and outputting circuit that was explained in the above-described embodiment 1 of the present invention, is applied to a driving circuit (driver IC) which has a function to correct light amount unevenness of LED and a circuit to drive LED according to a time division. In the embodiment, there is an objective to reduce element number of whole driving circuit (driver IC). In order to realize the objective, the driving circuit (driver IC) is formed by the following structure. Regarding the technology content for reducing the element number, it will be specifically annotated in the following explanation.

First is to explain a summary of the driving circuit (driver IC) which has a function to correct light amount unevenness of LED and a circuit to drive LED according to a time division. In the explanation of the embodiment, as an example, a LED head is given that can perform a print on a paper of A4 size in a resolution of 600 dots per inch, and its concrete structure is given. In the embodiment, the total number of LED elements is 4992 (i.e. 4992 dots); in order to combining them, 26 LED arrays are arranged; each LED array includes 192 LED elements; in respective elements of each LED array, cathodes of odd-numbered LED elements are connected each other, and cathodes of even-numbered LED elements are connected each other; anodes of two LED elements that are adjoining are connected each other. The odd-numbered LED elements and the even-numbered LED elements are driven according to time division.

FIG. 10is an explanation diagram of driver IC having a correcting function to correct an unevenness of light amount.

In the drawing, CHP(1) and CHP(2) are LED arrays, the representation of CHP(3)˜CHP(26) is omitted. IC(1) and IC(2) are driver to correspond to the CHP(1) and CHP(2). They are formed by an identical circuit, and adjoining driver ICs are connected in cascade. Here, the representation of IC(3)˜IC(26) is omitted.

As shown byFIG. 10, there are LED elements101˜108, in each LED array, 192 LED elements are furnished. Further, there are power MOS transistors109and110. The drain of the power MOS transistor109is connected with cathode of the LED elements101,103,105,107and the like; the drain of the power MOS transistor110is connected with cathode of the LED elements102,104,106,108and the like; the sources of the power MOS transistor109and the power MOS transistor110are connected with ground.

Further, as shown byFIG. 10, the gate terminal signal of the power MOS transistor109is “ODD”, and the gate terminal signal of the power MOS transistor110is “EVEN”. In the structure shown byFIG. 10, there are 4 signal lines for print data signal, thus, in 8 LED elements that are adjoining, data of 4 pixels part of the odd-numbered LED elements or the even-numbered LED elements can be sent synchronously per clock signal.

Therefore, print data signal HD-DATA3˜0outputted from the print controlling section1(FIG. 1) are inputted to the IC(1) and IC(2) together with the differential clock signals HD-CLK-P and HD-CLK-N, then, bit data of 4992 dots part are sequentially forwarded to a shift register circuit formed from flip-flop circuits described below.

Next, latch signal HD-LOAD is inputted to the IC(1) and IC(2), the print data signal HD-DATA3˜0are latched by respective latch circuits furnished to correspond to the flip-flop circuits placed at inside. Continuously, according to the print data signal HD-DATA3˜0and the strobe signal HD-STB-N, in light emitting elements (i.e. light emitting diode (LED)), only the LED element that correspond to “High” level in the print data signal HD-DATA3˜0is turned on a light.

Moreover, VDD is a power source, GND is ground, HD-HSYNC-N is a synchronous signal for setting an initial state for LED drive of odd-numbered LED element or for LED drive of even-numbered LED element, VREF is a reference voltage for instructing a drive electric current value for LED drive and it is generated by a reference voltage generating circuit (not shown) placed inside.

FIGS. 11A and 11Bare block diagrams showing a structure of a LED head in embodiment 2;

In the drawing, the structure of the driver IC shown byFIG. 10is shown in detail. In the structure, FFA(1)˜FFA(25), FFB(1)˜FFB(25), FFC(1)˜FFC(25), FFD(1)˜FFD(25) are flip-flop circuits, they construct shift register circuit. LTA(1)˜LTD(1), . . . , LTA(24)˜LTD(24) are latch elements, all of them construct a latch circuit.

MEM2is a memory circuit, in which, correction data (dot correction data) to correct light amount unevenness of LED, light amount correction data (chip correction data) of each LED, or inherent data of each driver IC are stored.

MUX2is a multiplexer circuit. The multiplexer circuit is furnished for performing a switch between odd-numbered dot correction data and even-numbered dot correction data with respect to dot of two adjoining LED elements according to the dot correction data outputted from the memory circuit MEM2.

DRV is a LED drive use control circuit. SEL is a selector circuit. CTRL1is a control circuit to generate a writing instruction signal when writing correction data into the memory circuit MEM2.

Further, CTRL2is a control circuit to send a switch signal of odd dot data and even dot data to the multiplexer circuit MUX2. ADJ is a control voltage generating circuit to receive the reference voltage VREF outputted from the VREF terminal and make a control voltage occur. The reference voltage VREF is generated by a regulator circuit (not shown), even if the power source voltage VDD occurs a drop for a moment because LED elements connected cathode are all turned on a light, the reference voltage VREF can keep in a predetermined value so that the drive electric current of the LED elements connected cathode does not drop.

201is an input circuit of a small amplitude differential signals CLK-P and CLK-N, for converting small amplitude signal inputted to clock terminals CLKP and CLKN into logical amplitude used in IC.202is a buffer circuit to receive signal of the input circuit201and drive clock signal of the shift register circuit composed of the flip-flop circuits of FFA(1)˜FFA(25), FFB(1)˜FFB(25), FFC(1)˜FFC(25), FFD(1)˜FFD(25).

203˜206are buffer circuits. Further,207˜210also are buffer circuits that receive output signal from SEL block to drive data output terminals DATAO3˜DATAO0.211is a resistance that is a pull-up element which is connected between a strobe terminal and a power source voltage VDD.212and213are inverter circuits,214is a NAND circuit.

The flip-flop circuits FFA(1)˜FFA(25) are connected in cascade. Data input terminal (DATAI0) of driver IC is connected with data input terminal D of FFA(1) via the buffer circuit203. The data outputs of the flip-flop circuit FFA(24) and the flip-flop circuit FFA(25) are inputted to the selector circuit SEL, the output terminal Y0of the selector circuit SEL is connected with the data output terminal (DATAO0) of driver IC via the buffer circuit207.

Likewise, The flip-flop circuits FFB(1)˜FFB(25), FFC(1)˜FFC(25), FFD(1)˜FFD(25) are respectively connected in cascade. Data input terminals (DATAI1, DATAI2, DATAI3) of driver IC are respectively connected with data input terminals D of FFB(1), FFC(1), FFD(1) via the buffer circuits204,205,206.

The data outputs of the flip-flop circuits FFB(24) and FFB(25), the flip-flop circuits FFC(24) and FFC(25), the flip-flop circuits FFD(24) and FFD(25) are respectively inputted to the selector circuit SEL, the output terminals Y1, Y2, Y3of the selector circuit SEL are respectively connected with the data output terminals (DATAO1, DATAO2, DATAO3) of driver IC via the buffer circuits208˜210.

Therefore, the flip-flop circuits of FFA(1)˜FFA(25), FFB(1)˜FFB(25), FFC(1)˜FFC(25), FFD(1)˜FFD(25) construct25a shift register circuit of 25 segments, through the selector circuit SEL, it is possible to switch the shift segment number of the shift register circuit according to 24 segments or 25 segments

The data output terminals (DATAO0, DATAO1, DATAO2, DATAO3) of driver IC are connected with the data input terminals (DATAI0, DATAI1, DATAI2, DATAI3) of driver IC of next segment. Therefore, the shift register circuit composed of all of the driver IC(1)˜driver IC(26) may be a shift register circuit of 24×26 segments or a shift register circuit of 25×26 segments to shift the print data signal HD-DATA3that is inputted to the first segment from the print controlling section1(FIG. 1), synchronously with clock signal.

In the NAND circuit214, strobe signal HD-STB-N corresponding to terminal (STB) and latch signal LOAD-P corresponding to terminal (LOAD) are inputted via the inverter circuits212and213, so that signal is generated to control ON or OFF of drive for the LED drive use circuit DRV.

Next, it is to sequentially explain in detail the memory circuit MEM2, the multiplexer circuit MUX2, the LED drive use circuit DRV, the control voltage generating circuit ADJ, the control circuit CTRL1, the control circuit CTRL2through using respective circuit drawings.

FIG. 12is a diagram showing a circuit structure of a memory circuit MEM2.

In the embodiment, dot correction data for correcting LED light amount has 4 bits so as to perform a light amount correction through adjusting LED drive electric current in 16 segments per dot.

As shown byFIG. 12, there are adjoining two (two dots) memory cells, they are divided to be respectively shown by areas252and252represented by broken line. The area251stores correction data of odd-numbered dot (e.g. dot No. 1), the area252stores correction data of even-numbered dot (e.g. dot No. 2).

The memory circuit MEM2includes a buffer circuit221, an inverter222for generating data signal that is assistant with the buffer circuit221, inverters223˜230to construct correction memory cell, and NMOS transistors231˜246.

Further, the memory circuit MEM2has a correction data input terminal D, an enabling terminal E1to receive an enabling signal E1for allowing a data writing on the side of odd-numbered dot, an enabling terminal E2to receive an enabling signal E2for allowing a data writing on the side of even-numbered dot, memory cell selection terminals W0˜W3, correction data output terminal ODD0˜ODD3concerning the odd-numbered dot, and correction data output terminal EVN0˜EVN3concerning the even-numbered dot.

The correction data input terminal D is respectively connected with data output terminals Q of flip-flop circuits FFA(1), FFB(1), FFC(1), FFD(1), FFA(2), . . . , FFA(24), FFB(24), FFC(24), FFD(24) and the like shown byFIGS. 11A-11B. Further, the writing control signal W0˜W3outputted from the control circuit CTRL1are inputted into the memory cell selection terminals W0˜W3, writing-enabling signal E1and writing-enabling signal E2outputted from the control circuit CTRL1are inputted into the enabling terminal E1and the enabling terminal E2.

The correction data input terminal D of the buffer circuit221is an input terminal of correction data; an output terminal of the buffer circuit221is connected with first terminals of the NMOS transistors231,235,239,243. An input terminal of the inverter222is connected with the output of the buffer circuit221; an output terminal of the inverter222is connected with first terminals of the NMOS transistors234,238,242,246.

The inverters223and224, the inverters225and226, the inverters227and228and the inverters229and230are respectively connected in series to form respective memory cells. The NMOS transistors231and232, the NMOS transistors233and234, the NMOS transistors235and236, the NMOS transistors237and238, the NMOS transistors239and240, the NMOS transistors241and242, the NMOS transistors243and244and the NMOS transistors245and246are respectively connected in series, one end of each series connection is connected with the output of the buffer circuit221or the inverter222.

The gate terminals of the NMOS transistors232and233are connected with the terminal W0, the gate terminals of the NMOS transistors236and237are connected with the terminal W1, the gate terminals of the NMOS transistors240and241are connected with the terminal W2, the gate terminals of the NMOS transistors244and245are connected with the terminal W3. Further, the enabling terminal E1is connected with the gate terminals the NMOS transistors231,234,235,238,239,242,243,246.

The output terminal of the inverter224is connected with the terminal ODD0. The output terminal of the inverter226is connected with the terminal ODD1. The output terminal of the inverter228is connected with the terminal ODD2. The output terminal of the inverter230is connected with the terminal ODD3. The above description relates to the memory cell251, but the memory cell252almost has the same structure as the memory cell252, except the enabling signal is called “E2”, and outputted signal name is called “EVN0˜EVN3”.

FIG. 13is a diagram showing a circuit structure of a multiplexer circuit MUX2.

As shown byFIG. 13, the multiplexer circuit MUX2is composed of 4 independent multiplexer circuits. There are PMOS transistors311˜318. The gates of the PMOS transistors311,313,315,317are connected with a terminal SiN; the gates of the PMOS transistors312,314,316,318are connected with a terminal S2N; the first terminal of the PMOS transistor311is connected with the terminal ODD0, and the first terminal of the PMOS transistor312is connected with the terminal EVN0; the second terminals of the PMOS transistors311and312are connected with the terminal Q0.

The PMOS transistors313˜318has the same connection structure, that is, the first terminal of the PMOS transistor313is connected with the terminal ODD1, the first terminal of the PMOS transistor314is connected with the terminal EVN1, and the second terminals of the PMOS transistors313and314are connected with the terminal Q1. Further, the first terminal of the PMOS transistor315is connected with the terminal ODD2, the first terminal of the PMOS transistor316is connected with the terminal EVN2, and the second terminals of the PMOS transistors315and316are connected with the terminal Q2. Furthermore, the first terminal of the PMOS transistor317is connected with the terminal ODD3, the first terminal of the PMOS transistor318is connected with the terminal EVN3, and the second terminals of the PMOS transistors317and318are connected with the terminal Q3.

The multiplexer circuit adopts a structure capable of reducing element number and preventing hindrance on operation. In the structure, the PMOS transistor is used as switch element, the reason is explained below.

That is, when making signal SiN become “Low” level so as to turn on the PMOS transistor311, if the signal ODD0is “High” level, a voltage being approximately equal to the “High” level is outputted to the terminal Q0. Thus, because of such transfer of “High” level, the PMOS transistor can be used as switch element without any hindrance.

Likewise, when the signal ODD0is in “Low” level (about 0V), the second terminal of the PMOS transistor311does not drop till an electric potential approaching a threshold value of the transistor, that is, till “Low” level (about 0V). Therefore, the transfer function of “Low” level is not complete so that there is a weak point.

In order to eliminate the weak point, in conventional technology, an analog switch is formed as a switch means for data selection through connecting PMOS transistor and NMOS transistor in parallel. In such structure, it is possible to obtain an output electric potential being approximately equal to an input signal electric potential which is prepared to transfer, and a difference between input electric potential and output electric potential does no occur through the switch means intervenes. However, with respect to one data signal line, it is necessary to provide a pair of PMOS transistor and NMOS transistor, as compared with the embodiment, 2 times the element is needed, so there is a problem that chip area of IC more possesses for placing these elements.

With respect to such problem, in the structure of the embodiment, as compared with such circuit using conventional analog switch, though only a half of elements are used, a weak point exists that transfer function of “Low” level is not complete. However, in the LED drive use circuit DRV (described below) of the embodiment, input voltage needs to be approximately equal to VDD electric potential, as “High” level; but, because such “Low” level as about “0” is not needed, so it is sufficient to drop till Vcont electric potential (described below), as “Low” level. Therefore, it is possible to adopt such multiplexer circuit only using PMOS transistor, and circuit operation can be performed without any hindrance. The following is to explain the LED drive use circuit DRV in detail.

FIG. 14is a diagram showing a circuit structure of a LED drive use circuit DRV in embodiment 2.

As shown byFIG. 14, the LED drive use circuit DRV in embodiment 2 includes PMOS transistors320˜324,330˜333,340˜344. The gate lengths of the PMOS transistors340˜344are set to be equal to that of the PMOS transistor62shown byFIG. 6.

The gate widths of the PMOS transistors340˜343are set so that their size ratio is 1:2:4:8 according to bit weights of correction data (bit0˜bit3) outputted from the memory circuit MEM2. Further, the LED drive use circuit DRV has a print data input terminal E (negative logic), an input terminal V, correction data input terminals Q0˜Q3(negative logic), and a drive electric current output terminal DO.

The QN outputs of the latch circuits LTA(1)˜LTD(1), LTA(12)˜LTD(12) are connected to the print data input terminal E. The correction data input terminals Q3˜Q0are connected with the correction data output terminals terminal Q3˜Q0of the multiplexer circuit MUX2shown byFIGS. 11A-11B. The input signals Q3˜Q0are correction data to correct light amount unevenness of LED element per dot.

To the input terminal V, the control voltage Vcont outputted from the control voltage generating circuit ADJ is inputted. The control voltage generating circuit ADJ has the same structure as that in embodiment 1, it is formed by using the control voltage generating circuit ADJ45ofFIG. 6. The drive electric current output terminal DO is an output terminal of driver IC, and is connected with anode of LED element by bonding wire (not shown).

The source terminals of the PMOS transistors340˜344are connected with power source VDD, the drain terminals of the PMOS transistors320˜324are connected with the drive electric current output terminal DO. An electric potential difference between the power source VDD and the control voltage Vcont is approximately equal to an voltage between gate and source when the PMOS transistors340˜344turn on, through changing the voltage, the drain electric current of the PMOS transistors340˜344can be adjusted.

The control voltage generating circuit ADJ is furnished for receiving a reference voltage Vref (not shown) and controlling the control voltage Vcont so that the drain electric current of the PMOS transistors340˜344and the like becomes a predetermined value.

The PMOS transistors340,330and320; the PMOS transistors341,331and321; the PMOS transistors342,332and322; and the PMOS transistors343,333and323are respectively connected through connecting drain terminal with source terminal. Likewise, the PMOS transistors344and324are connected by connecting drain terminal with source terminal.

The PMOS transistor344is a main drive transistor to mainly supply drive electric current to LED element, the PMOS transistors340˜343are subsidiary drive transistors to adjust the drive electric current of LED so as to correct light amount.

The PMOS transistor344(main drive transistor) is driven according to print data. The PMOS transistors340˜343(subsidiary drive transistors) are selectively driven according to the multiplexer output signals Q0˜Q3. As described above, from the terminals Q0˜Q3of multiplexer, data of correction memory are outputted, in the correction memory, correction data is stored for correcting unevenness of light emitting amount of each LED dot.

That is, with the PMOS transistor344(main drive transistor), the PMOS transistors340˜343(subsidiary drive transistors) are selectively driven according to the correction data, then, the drain electric current of the PMOS transistor344(main drive transistor) and the drain electric current of the selected one of the PMOS transistors340˜343(subsidiary drive transistors) are added to form a drive electric current, the drive electric current is outputted from the drive electric current output terminal DO to drive LED.

In the above explanation, there is an attention point. That is, as explained previously, the output of the multiplexer circuit MUX2needs an input voltage that is approximately equal to the power source VDD with respect to “High” level, but does not need to drop electric potential till about “0” voltage with respect to “Low” level. However, as stated above, the PMOS transistors340,330and320; the PMOS transistors341,331and321; the PMOS transistors342,332and322; and the PMOS transistors343,333and323are respectively connected through connecting drain terminal with source terminal; and the PMOS transistors344and324are connected by connecting drain terminal with source terminal. Thereby, the “Low” level is sufficient to drop to Vcont electric potential, such “Low” level as about “0” is not necessary. Therefore, as shown byFIG. 13, it is possible to adopt such multiplexer circuit only using PMOS transistor, and circuit operation is performed without any hindrance.

The following is to explain again the LED drive use circuit DRV.

As stated above, in the LED drive use circuit DRV, the gate widths of the PMOS transistors340˜343are set so that their size ratio is 1:2:4:8, and the correction memory for setting drive on or drive off of these transistors is set by 4 bits. Therefore, the LED drive electric current also has a setting value of 4 bits. Through performs respective combinations, with respect to the setting value, the LED drive electric current can be adjusted to 16 segments. Here, it is to explain the structure of drive transistor.

FIG. 15is a cross section of a drive transistor in embodiment 2.

In the drawing, structures of the PMOS transistors340,330and320; the PMOS transistors341,331and321; the PMOS transistors342,332and322; the PMOS transistors343,333and323, or the like are shown. This is a cross section obtained along a direction which is orthogonal with wirings of source, gate and drain of the drive transistor.

In the drawing, there are an IC chip81, a P type region82which represents a substrate layer, a N type well region83formed in the P type region82, and P type regions84˜86formed in the N type well region83. Further, there are gate wirings87,88,93, the wiring87corresponds to the gate of the PMOS transistor (e.g.343) inFIG. 14, the wiring88corresponds to the gate of the PMOS transistor (e.g.333) inFIG. 14, the wiring93corresponds to the gate of the PMOS transistor (e.g.323) inFIG. 14, their gate lengths respectively are “L1” “L2” and “L3” as shown byFIG. 15.

Moreover, there are a metal wiring89which is connected with the P type region84(e.g. corresponding to the source terminal of the PMOS transistor343) and with the power source voltage VDD (not shown).

Furthermore, there are a metal wiring90which is connected with the P type region86(e.g. corresponding to the drain terminal of the PMOS transistor323) and with a drive output terminal (not shown); and a protective film91covering on the upper surface of the IC chip81.

As shown byFIG. 15, the gate lengths of the PMOS transistors (e.g.340,330,320) ofFIG. 14respectively are “L1” “L2” and “L3”, they are set into: L1>L2, L2=L3.

The gate length of the PMOS transistor340is set to be equal to the gate length of the PMOS transistor62(FIG. 6). The PMOS transistor340and the PMOS transistor62form a current mirror circuit because their source electric potentials and gate electric potentials are respectively equal. Therefore, the drive electric current of LED (1) is kept in a scale relation with the reference electric current Iref. So it is possible to obtain drive electric current that correspond to the reference voltage Vref.

On the one hand, in the case to drive LED, it is not desirable that the drive electric current of LED changes according to the change of a regular direction voltage of LED. In order to greatly form output impedance of the drive electric current to improve its constant electric current character, the gate length of the PMOS transistor344or340˜343(FIG. 14) is set into a comparative long size.

On the other hand, the PMOS transistors330,320(FIG. 14) or the like only performs an action of switch element, it is possible to set the gate length of the PMOS transistors330,320(FIG. 14) or the like into a shortest size allowed in semiconductor manufacturing process, so that the area of the transistor can become smaller.

FIG. 16is a diagram showing a circuit structure of a controlling circuit CTRL1.

In theFIG. 16,361˜365are flip-flop circuits.368is a NOR circuit.369,370are AND circuit.380˜383are AND circuit. The negative logic resetting terminals of the flip-flop circuits361˜365are connected with a terminal LOAD to input latch signal LOAD-P. The clock terminals of the of the flip-flop circuits361˜362are connected with a terminal STB to input STB-P signal.

The output Q of the flip-flop circuits361˜362are connected with an input of the NOR circuit368, an output of the NOR circuit368is connected with the input D of the flip-flop circuit361. The clock terminal of the flip-flop circuit363is connected with the output terminal Q of the flip-flop circuit361. In the flip-flop circuit363, the output QN is connected with the input terminal D.

The output Q of the flip-flop circuit363is connected with one input terminal of the AND circuit370, the output terminal QN of the flip-flop circuit363is connected with one input terminal of the AND circuit369, another input terminals of the AND circuit369and the AND circuit370are connected with the terminal LOAD to input the LOAD-P signal.

Further, the outputs of the AND circuit370and the AND circuit369are respectively connected with the terminal E1and the terminal E2, they are writing enabling signals of the memory circuit MEM2shown byFIGS. 11A-11B. The clock terminals of the flip-flop circuit364and the flip-flop circuit365are connected with the output of the AND circuit370, the terminal D of the flip-flop circuit364is connected with the output terminal Q of the flip-flop circuit365, the input terminal D of the flip-flop circuit365is connected with the output terminal QN of the flip-flop circuit364.

A first input of the AND circuit383is connected with the terminal Q of the flip-flop circuit365, a second input of the AND circuit383is connected with the terminal QN of the flip-flop circuit364. A first input of the AND circuit382is connected with the terminal Q of the flip-flop circuit365, a second input of the AND circuit382is connected with the terminal Q of the flip-flop circuit364. A first input of the AND circuit381is connected with the terminal QN of the flip-flop circuit365, a second input of the AND circuit381is connected with the terminal Q of the flip-flop circuit364. A first input of the AND circuit380is connected with the terminal QN of the flip-flop circuit365, a second input of the AND circuit380is connected with the terminal QN of the flip-flop circuit364.

Third inputs of the AND circuit380˜383are connected with the output Q of the flip-flop circuit362. Output terminals of the AND circuit380˜383are respectively connected with the terminals W0˜w3, they are writing instruction signals toward the memory circuit MEM2shown byFIGS. 11A-11B.

FIG. 17is a diagram showing a circuit structure of a controlling circuit CTRL2.

In the drawing,391is a flip-flop circuit.392and393are buffer circuits. The clock terminal of the flip-flop circuit391is connected with a terminal LOAD to inputs LOAD-P signal, the negative logic resetting terminal R of the flip-flop circuit391is connected with a terminal HSYNC to inputs HSYNC-N signal, the terminal D of the flip-flop circuit391is connected with the terminal QN of itself. The input terminal of the buffer circuit393is connected with the terminal Q of the flip-flop circuit391. The output terminals of the buffer circuit392and the buffer circuit393are respectively connected with the terminals S1N, S2N, they are outputted to the multiplexer circuit MUX2ofFIGS. 11A-11Bas data selection instruction signals.

The LED head explained above in the embodiment 2 performs the following operation.

FIG. 18is a timing chart of control signal in embodiment 2.

In the drawing, according to an order from top to bottom, a synchronous signal HD-HSYNC-N, a print data signal HD-DATA, a clock signal HD-CLK, an latch signal HD-LOAD, a strobe signal HD-STB-N, ODD selection data and EVEN selection data are indicated.

Before a start of time division drive of LED, the synchronous signal HD-HSYNC-N is inputted (part A). Next, in part B, in order to forward odd-numbered LED drive data (Odd print data), the print data signal HD-DATA3˜0are inputted synchronously with the clock signal HD-CLK. Moreover, in the LED head, 26 driver ICs are connected in cascade, each driver IC has 96 LED drive terminals, 4 pixels part of print data is once forwarded according to clock signal of one pulse. Thus, the number of the clock pulse that is necessary for one data forwarding is 96/4×26=24×26=624.

After the data forwarding of odd-numbered dot of one line data is ended in the part B, the latch signal HD-LOAD is inputted as shown by part C, the data that is inputted via a shift register circuit composed of the flip-flop circuits (FFA(1)˜FFD(25)) is latched by the latch circuits (LTA(1)˜LTD(24)). Then, the strobe signal HD-STB-N is inputted for instructing LED drive (part D).

Further, before that, control signals ODD, EVEN of MOS transistors (i.e. power MOS transistors109,110inFIG. 10) to switch on or off a connection toward ground of the common cathode terminal of LED are outputted from terminal KDRV (not shown inFIG. 10) of IC(1), IC(2) ofFIG. 10.

These signals are generated by control circuit (not shown) inside driver IC. Through ODD/EVEN selection instruction data stored in a memory circuit (not shown) that is the same as the memory circuit MEM2, one of control signal ODD and control signal EVEN is selected, and is outputted from the terminal KDRV.

The control signal ODD is selected from the IC(1) inFIG. 10and is outputted from the terminal KDRV to drive gate terminal of the power MOS transistor109; the control signal EVEN is selected from the IC(2) inFIG. 10and is outputted from the terminal KDRV to drive gate terminal of the power MOS transistor110. InFIG. 10, because corresponding MOS transistors are not provided to the terminals KDRV (not shown) of the IC(3)˜IC(26), these terminals KDRV are opened.

InFIG. 10, when the control signal ODD is “High” level and the control signal EVEN is “Low” level, the power MOS transistor109turns on and the power MOS transistor110turns off, a flow path is formed from cathode terminal of LED elements101,103,105,107to ground.

At that time, the power MOS transistor110is in OFF state and a flow path is not formed from cathode terminal of LED elements102,104,106,108to ground. Therefore, in the case that LED drive electric current flows out from the terminal DO1of the driver IC (1), an electric current path is formed to flow through the anode terminal and the cathode terminal of the LED element101and through the drain and the source of the power MOS transistor109, then reach the ground. At that time, the LED element101emits light to form an electrostatic latent image onto a photosensitive drum (not shown) so as to generate print dot.

In the case, because electric current path is not formed in the LED element102, there is no any hindrance for the light emitting state of the LED element (101).

The following is to explain again according toFIG. 18.

In part E, in order to forward even-numbered LED drive data (Even print data), the print data signal HD-DATA3˜0are inputted synchronously with the clock signal HD-CLK.

Moreover, in the LED head, 26 driver ICs are connected in cascade, each driver IC has 96 LED drive terminals, 4 pixels part of print data is once forwarded according to clock signal of one pulse. Thus, the number of the clock pulse that is necessary for one data forwarding is 96/4×26=24×26=624.

After the data forwarding of even-numbered dot of one line data is ended in the part E, the latch signal HD-LOAD is inputted as shown by part F, the data that is inputted via the shift register circuit is latched by the latch circuits (LTA(1)˜LTD(24)). Then, the strobe signal HD-STB-N is inputted for instructing LED drive (part G).

Further, before that, control signals ODD, EVEN of MOS transistors (i.e. power MOS transistors109,110inFIG. 10) to switch on or off a connection toward ground of the common cathode terminal of LED are inputted.

InFIG. 10, when the control signal EVEN is “High” level and the control signal ODD is “Low” level, the power MOS transistor110turns on and the power MOS transistor109turns off, a flow path is formed from cathode terminal of LED elements102,104,106,108to ground.

At that time, a flow path is not formed from cathode terminal of LED elements101,103,105,107to ground. Therefore, in the case that LED drive electric current flows out from the terminal DO1of the driver IC (1), an electric current path is formed to flow through the anode terminal and the cathode terminal of the LED element102and through the drain and the source of the power MOS transistor110, then reach the ground. At that time, the LED element102emits light to form an electrostatic latent image onto a photosensitive drum (not shown) so as to generate print dot.

In the case, because electricity path is not formed in the LED element101, there is no any hindrance for the light emitting state of the LED element (102).

Thus, it is possible to perform LED drive of one line part through driving the odd-numbered LED element and the even-numbered LED element in LED elements according to an order, in a time division way.

FIG. 19is a timing chart of whole operation of embodiment 2.

The drawing relates to a correction data forwarding process with respect to the LED head of the present invention when power source of printer is turned on; and a print data forwarding after the correction data forwarding process.

Before a forwarding start of correction data, the latch signal HD-LOAD is set into “High” level (part I).

Next, regarding the odd-numbered dot, in correction data composed of 4 bits per one dot, the dada of bit3is inputted synchronously with the clock signal HD-CLK, from the print data signal HD-DATA3˜0, and is shifted to the shift register circuit formed by the flip-flop circuits (FFA(1)˜FFD(24)) ofFIGS. 11A-11B.

After shift input is ended, as shown by part A, the strobe signal HD-STB-N of 3 pulses is inputted, operation of circuit shown byFIG. 16is performed. In drawing, the Q1and the Q2are the outputs Q of the flip-flop circuits361and362, likewise, the Q3is the output Q of the flip-flop circuit363, the Q4is the output Q of the flip-flop circuit365, and the Q5is the output Q of the flip-flop circuit364.

Further, the E1and E2are respectively output signals of the AND circuits370and369; the signals W3˜W0are respectively the output signals of the AND circuits383˜380. Furthermore, the signals S1N and S2N are outputted from the buffer circuits392and393ofFIG. 17.

In the part A, when first pulse of the strobe signal HD-STB-N is inputted, as shown by part J, the signal Q1occurs. Continuously, when second pulse of the strobe signal HD-STB-N is inputted, as shown by part K, the signal Q2occurs. Further, whenever the signal Q1rises, the state of the signal Q3reverses, as shown by part L, the signal Q3moves to “High” level.

Following the movement of the signal Q3, the signals E1and E2occur. Following the next rise (second) of the signal E1, signal Q5rises. Further, at the more next rise (third) of the signal E1, signal Q4drops. Furthermore, at the rise (fourth) following the more next rise of the signal E1, the signal Q5drops.

The signals W3˜W0occur to follow the signal Q2, as shown by part O and part P, the signal W3are outputted twice, continuously, the signal W2, the signal W1, the signal W0are respectively outputted twice (two pulses).

Whenever respective pulses of the signals W3˜W0occur, data writing process is performed with respect to the memory circuit MEM2ofFIGS. 11A-11B. When the first pulse of the signals W3˜W0occurs, the data writing process is performed for odd-numbered dot; and when the second pulse of the signals W3˜W0occurs, the data writing process is performed for even-numbered dot.

Data writing instruction signal of the first pulse occurs on the basis of the inputted strobe signal HD-STB-N as shown by part A, part C, part E, part G. Data writing instruction signal of the second pulse occurs on the basis of the inputted strobe signal HD-STB-N as shown by part B, part D, part F, part H.

After all data writing of bit3˜bit0of correction data is ended through the above described process, as shown part Q, the latch signal HD-LOAD is set to “Low” level so as to enable a forwarding of print data to be performed.

When starting to print one line, the synchronous signal HD-HSYNC-N is inputted (part R) for data forwarding of odd-numbered dot. Next, as shown by part U, the print data of odd-numbered dot is forwarded. According to the latch signal HD-LOAD shown by part S, data that is shifted by the shift register circuit (FFA(1)˜FFD(1), . . . , FFA(24)˜FFD(24)) is latched by latch elements (LTA(1)˜LTD(1), . . . , LTA(24)˜LTD(24)).

Further, as shown part W, the strobe signal HD-STB-N moves to “Low” level, light emitting drive of LED element is performed. When print data is in ON state and the strobe signal HD-STB-N becomes “Low” level to correspond to part W and part X, the LED element is driven to emit light. Likewise, as shown by part V, data forwarding of even-numbered dot is performed, and the data is latched by pulse of part T.

FIG. 20is an operation explanation diagram of LED drive use circuit of embodiment 2.

The drawing is to explain operation of LED drive use circuit having a light amount correction function of LED dot. Here, dot correction data Q3˜Q0in drawing are set by concrete data for dot correction of LED.

Corresponding to dot correction data Q3˜Q0, negative logic signals are inputted. For example, output data (ODD3˜ODD0) of correction memory MEM may be set to “1110”. The signals are inputted to the multiplexer circuit MUX2, and is outputted by PMOS switch provided in the multiplexer circuit MUX2, and are inputted as signals Q3˜Q0.

As described above, in the multiplexer circuit using PMOS transistor serving as switch element, there is no any hindrance for the transfer of data whose signal level is “High”. For example, with respect to the data input of about 5V, output voltage of about 5V can be obtained.

As compared with it, when transferring “Low” level, because the electric potential corresponding to a threshold voltage of MOS transistor rises, even if a voltage of about 0V is inputted, an output voltage rises to an electric potential of about 1V.

As a result, when the power source VDD is 5V, the electric potentials of the signals Q3˜Q0respectively are 5V, 5V, 5V, 1V, these voltages are respectively provided to the gates of the PMOS transistors333˜330. Thereby, in the PMOS transistors333˜330, the PMOS transistors333˜331are turned off, the PMOS transistor330is turned on.

At that time, the source electric potential of the PMOS transistor330is higher than a threshold value (about 1V) of the transistor by the gate electric potential of about 1V, so it becomes about 2V. The electric potential also is the drain electric potential of the PMOS transistor340.

The drain electric potential of the PMOS transistor340does not depend upon the electric potential of the drive terminal DO, for example, even if a regular direction voltage changes due to drive state of LED, it is possible to eliminate the change of the drain electric potential of the PMOS transistor340. Also it is possible to drop Vds dependence of drain electric current cause by that drain electric current Id changes slightly since the voltage Vds between drain and source of MOS transistor operating in a saturation area changes. Thereby, it is possible to inhibit the change of the drain electric current of the PMOS transistor340to a negligible degree.

The operation of the circuit composed of the PMOS transistors340and330is obtained by such mechanism as circuit that is known as a cascade constant electric current circuit, it is possible to improve character of drive circuit with the above described structure.

Regarding the print data, the data that if forwarded via the shift register circuit composed of the flip-flop circuits FFA(1)˜FFA(24) and the like ofFIGS. 11A-11Bbecomes ON state; is latched by the latch circuits LTA(1)˜LTA(24); is changed to negative logic data via the output QN of these latch elements and is outputted to the terminal E. Therefore, the signal level of the terminal E is about 0V when it is instructed to print.

The signal inputted to the terminal V is the voltage Vcont outputted from the control voltage generating circuit ADJ ofFIGS. 11A-11B, the control voltage generating circuit ADJ is composed of these components of41, the61˜68inFIG. 6. The voltage Vcont in the process that the LED drive is changed from OFF state to ON state and is changed again to ON state is changed is that explained by usingFIG. 9.

If supposing that the voltage between gate and source the when the PMOS transistors340˜344are turned on is 2V, the voltage Vcont in the process that the LED drive is changed from OFF state to ON state and is changed again to ON state changes from 5V to 3V, and changes again from 3V to 5V (i.e. 5V→3V→5V).

Through the voltage, the state of the PMOS transistors340˜344whose gates are provided by the voltage is changed from OFF to ON, and is changed again from ON to OFF (i.e. OFF→ON→OFF).

However, in the PMOS transistors333˜330, the PMOS transistors333˜331become OFF, the PMOS transistor330becomes ON, and the PMOS transistors320˜324continue ON state. Therefore, as shown by the broken line inFIG. 20, electric current occurs from the PMOS transistor344as electric current “im” and electric current occurs from the PMOS transistor340as electric current “io” so as to drive LED element via the terminal DO. In the above description, such case was explained that the output data (ODD3˜ODD0) of correction memory MEM is “1110”. But, according to the output data from the correction memory MEM2, the ON/OFF states of the PMOS transistors333˜330are set, so it is possible to generate drive electric current of different 16 ways.

Explanation of Effect:

In the embodiment, a correction drive segment for dot correction is formed from a circuit composed of first, second and third PMOS transistors that are connected in series, a control voltage is supplied to the gate of the first PMOS transistor according to a drive electric current value, dot correction data is inputted to the second PMOS transistor, a drive ON/OFF instruction signal is inputted to the gate of the third PMOS transistor. Therefore, it is unnecessary to provide a NAND circuit (for example, the logical circuit42ainFIG. 4) that is necessary in comparison example, as a previous segment circuit of PMOS transistor for performing a dot correction drive with respect to 4 bits part.

In addition, through switching a control voltage that is provided to the gate of the first PMOS transistor, according to the drive ON or drive OFF of LED, when it is LED drive OFF, the first PMOS transistor is turned off so that the electric charge does not continue to charge in the drain terminal. Therefore, it is possible to eliminate the occurrence of great overshoot electric current when starting to drive LED element. As a result, it is possible to prevent the LED element form degrading.

Moreover, the following is to add a postscript regarding the summary structure of LED head to which the present invention is applied.

FIG. 21is an appearance cubic diagram of LED head applying the present invention.

InFIG. 21,301is a rod lens array obtained by arranging plural lenses of rod shape along a left-right direction.302is a holder to hold the rod lens array301and members to form LED head300. The paper size, the paper feeding method, the layout type and the print mode is a connector for connecting cable to supply electric power from the outside of the LED head300and signal used for controlling internal circuit in the LED head300. An arrow D indicates a light output direction.

InFIG. 22,304is a member to load a light emitting unit in the LED head300. Here, the light emitting unit is an assembly body of a wiring substrate305, a driver IC306, and a LED element307. The wiring substrate305is formed by performing a wiring on a substrate such as glass epoxy substrate and is used for mounting and connecting with electric parts. The driver IC306is formed by integrating plural driving circuits of the present invention and is used to drive the LED element307. The LED element307is a light emitting element formed in a thin film shape and is stuck on the surface of the driver IC306in embodiment. The LED element307is furnished to correspond to respective driving circuits of the driver IC306and a great of the LED element307are arranged along the left-right direction of theFIG. 21.

Here, a connection of the LED element307and the driver IC306is realized by electrode wiring closely sticking on the respective surfaces of the LED element307and the driver IC306. A bonding wire308is used to connect pads respectively placed on the wiring substrate305and the driver IC306. The electric power and the signal that are inputted via the connector303are supplied to the driver IC306via the bonding wire308. The base member304is pressed upwardly by a damper (not shown), is held by the holder302and is used to perform a position decision of the LED element307and the rod lens array301. The LED element307is driven by the driver IC306to emit light. The light emitted by the LED element307is outputted along a direction of the arrow D via the rod lens array301to form an image. In the case to use the LED head300as an exposing section of an electrophotographic printer serving as an image forming apparatus, a photosensitive drum is furnished in the direction of the arrow D, and a distance between the LED head300and the photosensitive drum is adjusted for enabling the light emitted by the LED element307to be used to form an image on the surface of the photosensitive drum.

THE UTILIZATION POSSIBILITY IN INDUSTRY

In the embodiment 1 and the embodiment 2, such case was explained that the driving circuit is used in electrophotographic printer using light source of LED. However, the present invention is not be limited by the case. That is, as light source, it is possible to adopt organic EL head using organic EL elements. Then, the present invention also can be applied to the organic EL head having the same structure. Further, the present invention also can be applied to the case to drive array of heat emitting resistances in thermal printer and array of display elements in displaying device.

The present invention is not limited to the foregoing embodiment or example but many modifications and variations are possible within the spirit and scope of the appended claims of the invention.