Semiconductor device generating a refresh signal

A semiconductor device includes a temperature code latch circuit and a period selection circuit. The temperature code latch circuit latches a count code having a logic level combination corresponding to an internal temperature to output the latched count code as a temperature code. The period selection circuit selects a period of a refresh signal in response to the temperature code. A period variation rate of the refresh signal according to variation of the internal temperature is controlled by a first gradient selection signal in a first temperature section and is controlled by a second gradient selection signal in a second temperature section.

CROSS-REFERENCE TO RELATED APPLICATIONS

The present application claims priority under 35 U.S.C §119(a) to Korean Patent Application No. 10-2015-0139722, filed on Oct. 5, 2015, in the Korean Intellectual Property Office, which is incorporated herein by reference in its entirety as set forth in full.

BACKGROUND

1. Technical Field

Embodiments of the present disclosure relate to semiconductor device generating a refresh signal.

2. Related Art

A semiconductor system including a semiconductor device may need a periodic signal to control internal operations thereof. That is, the semiconductor system may execute the internal operations in response to the periodic signal generated in the semiconductor system or from an external device. The periodic signal may include pulses which are created to have a uniform cycle. Thus, the periodic signal may be used to execute iterative internal operations of integrated circuits ICs constituting the semiconductor device.

Volatile memory devices, for example dynamic random access memory (DRAM) devices, may lose their stored data as time elapses even though their power supplies are continuously provided. Thus, all memory cells in the DRAM devices should be refreshed within a data retention time corresponding to a maximum time that the memory cells can retain data. Since the refresh operation is periodically executed, the DRAM devices may need a periodic signal to execute the refresh operation.

An operation speed of the semiconductor devices may vary according to a temperature. That is, the higher the temperature, the slower the operation speed of the semiconductor devices. In contrast, the lower the temperature, the faster the operation speed of the semiconductor devices. If the operation speed of the semiconductor device varies according to the temperature, the reliability of the semiconductor devices may be degraded to the point of causing a malfunction.

DETAILED DESCRIPTION OF THE EMBODIMENTS

Various embodiments are directed to semiconductor devices generating a refresh signal.

According to an embodiment, a semiconductor device includes a temperature code latch circuit and a period selection circuit. The temperature code latch circuit latches a count code having a logic level combination corresponding to an internal temperature to output the latched count code as a temperature code. The period selection circuit selects a period of a refresh signal in response to the temperature code. A period variation rate of the refresh signal according to variation of the internal temperature is controlled by a first gradient selection signal during a first temperature section and is controlled by a second gradient selection signal during a second temperature section.

According to another embodiment, a semiconductor device includes a gradient control circuit and a period selection circuit. The gradient control circuit compares a count code with first to fourth set codes to generate first and second gradient selection signals, in response to a temperature detection signal, a first selection control signal and a second selection control signal. The period selection circuit selects a period of a refresh signal in response to a temperature code. A period variation rate of the refresh signal according to variation of an internal temperature is controlled by the first gradient selection signal during a first temperature section and is controlled by the second gradient selection signal during a second temperature section.

According to another embodiment, a semiconductor device includes a temperature code latch circuit and a period selection circuit. The temperature code latch circuit latches a count code having a logic level combination corresponding to an internal temperature to output the latched count code as a temperature code. The period selection circuit selects a period of a control signal in response to the temperature code. A period variation rate of the control signal according to variation of the internal temperature is controlled by a first gradient selection signal during a first temperature section and is controlled by a second gradient selection signal during a second temperature section

Various embodiments of the present disclosure will be described hereinafter with reference to the accompanying drawings. However, the embodiments described herein are for illustrative purposes only and are not intended to limit the scope of the present disclosure.

As illustrated inFIG. 1, a semiconductor device according to an embodiment may include a temperature sensing circuit1, a temperature code latch circuit2, a gradient control circuit3, a periodic signal generation circuit4, and a period selection circuit5.

The temperature sensing circuit1may generate a temperature detection signal T_DETP in response to a count code CNT_CD<1:3>. The count code CNT_CD<1:3> may be a signal that is sequentially counted and may be provided by an external device or generated in the semiconductor device. A logic level combination of the count code CNT_CD<1:3> may correspond to an internal temperature of the semiconductor device. For example, if the count code CNT_CD<1:3> is sequentially counted from a logic level combination of ‘000’ to a logic level combination of ‘111’, the logic level combination of ‘000’ may mean that the semiconductor device has an internal temperature of 120 degrees Celsius, the logic level combination of ‘011’ may mean that the semiconductor device has an internal temperature of 96 degrees Celsius, and the logic level combination of ‘110’ may mean that the semiconductor device has an internal temperature of 30 degrees Celsius. The temperature sensing circuit1may include a temperature sensor (not shown) that senses the internal temperature of the semiconductor device. The temperature sensing circuit1may generate the temperature detection signal T_DETP including a pulse generated if the count code CNT_CD<1:3>, having a logic level combination corresponding to the internal temperature of the semiconductor device, is input to the temperature sensing circuit1.

The temperature code latch circuit2may generate a temperature code T_CD<1:3> from the count code CNT_CD<1:3> in response to the temperature detection signal T_DETP. More specifically, the temperature code latch circuit2may latch the count code CNT_CD<1:3> to output the latched count code as the temperature code T_CD<1:3>, in synchronization with a time point that a pulse of the temperature detection signal T_DETP is generated. That is, the temperature code latch circuit2may latch the count code CNT_CD<1:3> having a logic level combination corresponding to the internal temperature of the semiconductor device to output the latched count code as the temperature code T_CD<1:3>.

The gradient control circuit3may compare the count code CNT_CD<1:3> with first to fourth set codes SCD1<1:3>, SCD2<1:3>, SCD3<1:3> and SCD4<1:3> to generate first to third gradient selection signals GRD_SEL<1:3>, in response to the temperature detection signal T_DETP, a first selection control signal SEL1_EN and a second selection control signal SEL2_EN. More specifically, the gradient control circuit3may compare the count code CNT_CD<1:3> with the first and second set codes SCD1<1:3> and SCD2<1:3> to generate a first internal signal (INI1ofFIG. 3) and may generate the first gradient selection signal GRD_SEL<1> from the first internal signal INI1in synchronization with the pulse of the temperature detection signal T_DETP while the first selection control signal SEL1_EN is enabled. In addition, the gradient control circuit3may compare the count code CNT_CD<1:3> with the third and fourth set codes SCD3<1:3> and SCD4<1:3> to generate a second internal signal (INI2ofFIG. 4). The gradient control circuit3may generate the second gradient selection signal GRD_SEL<2> from the second internal signal INI2in synchronization with a pulse of the temperature detection signal T_DETP while the second selection control signal SEL2_EN is enabled. Moreover, the gradient control circuit3may generate the third gradient selection signal GRD_SEL<3> in response to the first and second gradient selection signals GRD_SEL<1:2>. Logic levels of the first and second selection control signals SEL1_EN and SEL2_EN are enabled and may be set different according to the embodiments.

The periodic signal generation circuit4may include an oscillator41and a divider42. The oscillator41may generates an oscillation signal OSC corresponding to a periodic signal. The divider42may divide the oscillation signal OSC to generate first to Nthdivided signals X<1:N>. A period (i.e., a cycle time) of the oscillation signal OSC may be set different depending on the embodiment. A period of each of the first to Nthdivided signals X<1:N> may be set to be an integer number times that of the oscillation signal OSC. For example, a period of the Kthdivided signal X<K> may be set to be “K” times that of the oscillation signal OSC. The number “N” of the first to Nthdivided signals X<1:N> may be set different according to the embodiment.

The period selection circuit5may output one of the first to Nthdivided signals X<1:N> as a refresh signal PSRF in response to at least one of the temperature code T_CD<1:3> and the first to third gradient selection signals GRD_SEL<1:3>. The period selection circuit5may generate the refresh signal PSRF whose period is reduced as the internal temperature of the semiconductor device falls. A temperature gradient (i.e., a period of a decreasing rate of the refresh signal PSRF according to a decrease in the internal temperature of the semiconductor device) may be controlled in accordance with the first to third gradient selection signals GRD_SEL<1:3>. For example, the temperature gradient may be set to a maximum value if the first gradient selection signal GRD_SEL<1> is enabled, and the temperature gradient may be set to a minimum value if the third gradient selection signal GRD_SEL<3> is enabled.

Referring toFIG. 2, the gradient control circuit3may include a first selection signal generator31, a second selection signal generator32and a third selection signal generator33.

The first selection signal generator31may generate an enabled first gradient selection signal GRD_SEL<1> from the count code CNT_CD<1:3> and the first and second set codes SCD1<1:3> and SCD2<1:3> in response to the first selection control signal SEL1_EN and the temperature detection signal T_DETP. In one example, the first gradient selection signal GRD_SEL<1> may be enabled synchronously with a time that the count code CNT_CD<1:3> is the same as the first set code SCD1<1:3>. In another example, the first selection signal generator31may compare the count code CNT_CD<1:3> with the first and second set codes SCD1<1:3> and SCD2<1:3> to generate the first internal signal (INI1ofFIG. 3), and the first selection signal generator31may generate the first gradient selection signal GRD_SEL<1> from the first internal signal INI1in synchronization with the pulse of the temperature detection signal T_DETP while the first selection control signal SEL1_EN is enabled. Further, the first gradient selection signal GRD_SEL<1> may be disabled when the count code CNT_CD<1:3> is the same as the second set code SCD2<1:3>.

The second selection signal generator32may generate the second gradient selection signal GRD_SEL<2> from the count code CNT_CD<1:3> and the third and fourth set codes SCD3<1:3> and SCD4<1:3> in response to the second selection control signal SEL2_EN and the temperature detection signal T_DETP. In one example, the second gradient selection signal GRD_SEL<2> may be enabled synchronously with a time that the count code CNT_CD<1:3> is the same as the third set code SCD3<1:3>. More specifically, the second selection signal generator32may compare the count code CNT_CD<1:3> with the third and fourth set codes SCD3<1:3> and SCD4<1:3> to generate the second internal signal (INI2ofFIG. 4) and may generate the second gradient selection signal GRD_SEL<2> based on the second internal signal INI2in synchronization with the pulse of the temperature detection signal T_DETP while the second selection control signal SEL2_EN is enabled. Further, the first gradient selection signal GRD_SEL<1> may be disabled when the count code CNT_CD<1:3> is the same as the fourth set code SCD4<1:3>.

The third selection signal generator33may generate the third gradient selection signal GRD_SEL<3> in response to the first and second gradient selection signals GRD_SEL<1:2>. More specifically, the third selection signal generator33may generate the third gradient selection signal GRD_SEL<3> disabled if at least one of the first and second gradient selection signals GRD_SEL<1:2> is enabled. Meanwhile, the third selection signal generator33may generate the third gradient selection signal GRD_SEL<3> enabled if both of the first and second gradient selection signals GRD_SEL<1:2> are disabled. Logic levels of enabled first, second and third gradient selection signals GRD_SEL<1:3> may be set differently according to the embodiments.

Referring toFIG. 3, the first selection signal generator31may include a first set signal generator311, a first reset signal generator312, a first internal signal generator313, a first latch circuit314and a first buffer315.

The first set signal generator311may generate a first set signal STB1in response to the count code CNT_CD<1:3> and the first set code SCD1<1:3>. More specifically, the first set signal generator311may generate the first set signal STB1, enabled to a logic “low” level, if the count code CNT_CD<1:3> is the same as the first set code SCD1<1:3>. If the count code CNT_CD<1:3> and the first set code SCD1<1:3> are the same, this means that the count code CNT_CD<1> is the same as the first set code SCD1<1>, the count code CNT_CD<2> is the same as the first set code SCD1<2>, and the count code CNT_CD<3> is the same as the first set code SCD1<3>. A logic level of the enabled first set signal STB1may be set different according to the embodiments.

The first reset signal generator312may generate a first reset signal RSTB1in response to the count code CNT_CD<1:3> and the second set code SCD2<1:3>. More specifically, the first reset signal generator312may generate the first reset signal RSTB1, which is enabled to a logic “low” level, if the count code CNT_CD<1:3> is the same as the second set code SCD2<1:3>. If the count code CNT_CD<1:3> and the second set code SCD2<1:3> are the same, this means that the count code CNT_CD<1> is the same as the second set code SCD2<1>, the count code CNT_CD<2> is the same as the second set code SCD2<2>, and the count code CNT_CD<3> is the same as the second set code SCD2<3>. A logic level of the enabled first reset signal RSTB1may be set different according to the embodiments.

The first internal signal generator313may generate the first internal signal INI1in response to the first set signal STB1and the first reset signal RSTB1. More specifically, the first internal signal generator313may generate the first internal signal INI1enabled to a logic “high” level if the first set signal STB1is enabled to a logic “low” level and may generate the first internal signal INI1disabled to a logic “low” level if the first reset signal RSTB1is enabled to a logic “low” level. A logic level of the enabled first internal signal INI1may be set different according to the embodiments.

The first latch circuit314may generate a first latch signal LAT1from the first internal signal INI1in response to the temperature detection signal T_DETP. More specifically, the first latch circuit314may latch the first internal signal INI1in response to the temperature detection signal T_DETP pulse created if a logic level combination of the sequentially counted count code CNT_CD<1:3> corresponds to the internal temperature of the semiconductor device and the first latch circuit314may output the latched first internal signal as the first latch signal LAT1.

The first buffer315may generate the first gradient selection signal GRD_SEL<1> from the first latch signal LAT1in response to the first selection control signal SEL1_EN. More specifically, the first buffer315may buffer the first latch signal LAT1to output the buffered first latch signal as the first gradient selection signal GRD_SEL<1> if the first selection control signal SEL1_EN is enabled to a logic “high” level.

The first selection signal generator31may generate the first internal signal INI1enabled to a logic “high” level during a first temperature section from a time point that the sequentially counted count code CNT_CD<1:3> is the same as the first set code SCD1<1:3> till a time point that the sequentially counted count code CNT_CD<1:3> is the same as the second set code SCD2<1:3>. In addition, the first selection signal generator31may generate the first gradient selection signal GRD_SEL<1>, which is enabled to a logic “high” level, during the first temperature section if the first selection control signal SEL1_EN is enabled to a logic “high” level and the pulse of the temperature detection signal T_DETP is created.

Referring toFIG. 4, the second selection signal generator32may include a second set signal generator321, a second reset signal generator322, a second internal signal generator323, a second latch circuit324and a second buffer325.

The second set signal generator321may generate a second set signal STB2in response to the count code CNT_CD<1:3> and the third set code SCD3<1:3>. More specifically, the second set signal generator321may generate the second set signal STB2which is enabled to a logic “low” level if the count code CNT_CD<1:3> is the same as the third set code SCD3<1:3>. The count code CNT_CD<1:3> being the same as the third set code SCD3<1:3> means that the count code CNT_CD<1> is the same as the third set code SCD3<1>, the count code CNT_CD<2> is the same as the third set code SCD3<2>, and the count code CNT_CD<3> is the same as the third set code SCD3<3>. A logic level of the enabled second set signal STB2may be set to differently according to the embodiments.

The second reset signal generator322may generate a second reset signal RSTB2in response to the count code CNT_CD<1:3> and the fourth set code SCD4<1:3>. More specifically, the second reset signal generator322may generate the second reset signal RSTB2which is enabled to a logic “low” level if the count code CNT_CD<1:3> is the same as the fourth set code SCD4<1:3>. The count code CNT_CD<1:3> being the same as the fourth set code SCD4<1:3> means that the count code CNT_CD<1> is the same as the fourth set code SCD4<1>, the count code CNT_CD<2> is the same as the fourth set code SCD4<2>, and the count code CNT_CD<3> is the same as the fourth set code SCD4<3>. A logic level of the enabled second reset signal RSTB2may be set differently according to the embodiments.

The second internal signal generator323may generate the second internal signal INI2in response to the second set signal STB2and the second reset signal RSTB2. More specifically, the second internal signal generator323may generate the second internal signal INI2which is enabled to a logic “high” level if the second set signal STB2is enabled to a logic “low” level, and the second internal signal generator323may generate the second internal signal INI2which is disabled to a logic “low” level if the second reset signal RSTB2is enabled to a logic “low” level. A logic level of the enabled second internal signal INI2may be set differently according to the embodiments.

The second latch circuit324may generate a second latch signal LAT2from the second internal signal INI2in response to the temperature detection signal T_DETP. More specifically, the second latch circuit324may latch the second internal signal INI2in response to the pulse of the temperature detection signal T_DETP and may output the latched second internal signal as the second latch signal LAT2. The temperature detection signal T_DETP may be created if a logic level combination of the sequentially counted count code CNT_CD<1:3> corresponds to the internal temperature of the semiconductor device.

The second buffer325may generate the second gradient selection signal GRD_SEL<2> from the second latch signal LAT2in response to the second selection control signal SEL2_EN. More specifically, the second buffer325may buffer the second latch signal LAT2to output the buffered second latch signal as the second gradient selection signal GRD_SEL<2> if the second selection control signal SEL2_EN is enabled to a logic “high” level.

The second selection signal generator32may generate the second internal signal INI2which is enabled to a logic “high” level during a second temperature section from a time point that the sequentially counted count code CNT_CD<1:3> is the same as the third set code SCD3<1:3> till a time point that the sequentially counted count code CNT_CD<1:3> is the same as the fourth set code SCD4<1:3>. In addition, the second selection signal generator32may generate the second gradient selection signal GRD_SEL<2>, which is enabled to a logic “high” level, during the second temperature section if the second selection control signal SEL2_EN is enabled to a logic “high” level and the pulse of the temperature detection signal T_DETP is created.

Referring toFIG. 5, the third selection signal generator33may include a NOR gate NOR31. The third selection signal generator33may generate the third gradient selection signal GRD_SEL<3> which is disabled to a logic “low” level if at least one of the first and second gradient selection signals GRD_SEL<1:2> is enabled to a logic “high” level. The third selection signal generator33may generate the third gradient selection signal GRD_SEL<3> enabled to a logic “high” level if both of the first and second gradient selection signals GRD_SEL<1:2> are disabled to a logic “low” level.

An operation of the semiconductor device having the aforementioned configuration will be described hereinafter with reference toFIGS. 6 to 10. In the following description, it may be assumed that the count code CNT_CD<1:3> inputted to the semiconductor device is sequentially counted from a logic level combination of ‘000’ (corresponding to a decimal number ‘0’) to a logic level combination of ‘111’ (corresponding to a decimal number ‘7’). The decimal numbers ‘0’, ‘1’, ‘2’, ‘3’, ‘4’, ‘5’, ‘6’ and ‘7’ of the count code CNT_CD<1:3> may correspond to the internal temperatures ‘T1’, ‘T2’, ‘T3’, ‘T4’, ‘T5’, ‘T6’, ‘T7’ and ‘T8’ of the semiconductor device, respectively.

When the count code CNT_CD<1:3> inputted to the semiconductor device has the decimal numbers of ‘0’, ‘1’ and ‘2’ (corresponding to logic level combinations of ‘000’, ‘001’ and ‘010’), the internal temperature of the semiconductor device may be within the range of a first temperature section (T1˜T4). During the first temperature section (T1˜T4), the first internal signal INI1may be generated to have a logic “high” level and the second internal signal INI2may be generated to have a logic “low” level. When the count code CNT_CD<1:3> inputted to the semiconductor device has the decimal numbers of ‘3’, ‘4’ and ‘5’ (corresponding to logic level combinations of ‘011’, ‘100’ and ‘101’), the internal temperature of the semiconductor device may be within the range of a second temperature section (T4˜T7). During the second temperature section (T4˜T7), both of the first and second internal signals INI1and INI2may be generated to a logic “low” level. When the count code CNT_CD<1:3> inputted to the semiconductor device has the decimal numbers of ‘6’, and ‘7’ (corresponding to logic level combinations of ‘110’ and ‘111’), the internal temperature of the semiconductor device may be within the range of a third temperature section (T7˜T9). During the third temperature section (T7˜T9), the first internal signal INI1may be generated to a logic “low” level and the second internal signal INI2may be generated to a logic “high” level.

Referring toFIG. 6, if the internal temperature of the semiconductor device is a third temperature T3within the range of the first temperature section (T1˜T4), the temperature detection signal T_DETP may be generated to include a pulse created in synchronization with a time point that the count code CNT_CD<1:3> having a decimal number of ‘2’ is inputted to the semiconductor device. In such a case, the first gradient selection signal GRD_SEL<1> may be enabled to a logic “high” level by the first internal signal INI1having a logic “high” level and the pulse of the temperature detection signal T_DETP.

Referring toFIG. 7, if the internal temperature of the semiconductor device is an eighth temperature T8within the range of the third temperature section (T7˜T9), the temperature detection signal T_DETP may be generated to include a pulse created in synchronization with a time point that the count code CNT_CD<1:3> having a decimal number of ‘7’ is inputted to the semiconductor device. In such a case, the second gradient selection signal GRD_SEL<2> may be enabled to a logic “high” level by the second internal signal INI2having a logic “high” level and the pulse of the temperature detection signal T_DETP.

Referring toFIG. 8, if the internal temperature of the semiconductor device is a fifth temperature T5within the range of the second temperature section (T4˜T7), the temperature detection signal T_DETP may be generated to include a pulse created in synchronization with a time point that the count code CNT_CD<1:3> having a decimal number of ‘4’ is inputted to the semiconductor device. In such a case, the third gradient selection signal GRD_SEL<3> may be enabled to a logic “high” level by the first and second internal signals INI1and INI2having a logic “high” level and the pulse of the temperature detection signal T_DETP.

Referring toFIG. 9, period variation rate of the refresh signal PSRF relative to a decrease (from the first temperature T1to the eighth temperature T8) of the internal temperature of the semiconductor device is illustrated. The period variation of the refresh signal PSRF may occur when each of the first to third gradient selection signals GRD_SEL<1:3> is enabled to a logic “high” level. That is, a period of the refresh signal PSRF (i.e., a refresh cycle time) is reduced at the greatest rate if the first gradient selection signal GRD_SEL<1> is generated having a logic “high” level, and a period of the refresh signal PSRF (i.e., a refresh cycle time) is reduced at the least rate if the second gradient selection signal GRD_SEL<2> is generated having a logic “high” level.

Referring toFIG. 10, period variation rate of the refresh signal PSRF relative to a decrease (from the first temperature T1to the eighth temperature T8) of the internal temperature of the semiconductor device is illustrated according to the first to third temperature sections T1˜T4, T4˜T7and T7˜T9. That is, a period variation rate of the refresh signal PSRF lessens as the internal temperature of the semiconductor device decreases from the first temperature section T1˜T4toward the third temperature section T7˜T9.

As described above, a semiconductor device according to an embodiment may generate a refresh signal which is capable of having different temperature gradients according to temperature sections. Thus, a period of the refresh signal may be set according to the temperature sections. In some embodiments, a period of a control signal for controlling various internal operations repeatedly executed in the semiconductor device may be set to temperature sections. The internal operations of the semiconductor device may include a read operation, a write operation and a pre-charge operation.

The semiconductor device described with reference toFIGS. 1 to 10may be applied to an electronic system that includes a memory system, a graphic system, a computing system, a mobile system, or the like. For example, as illustrated inFIG. 11, an electronic system1000according an embodiment may include a data storage circuit1001, a memory controller1002, a buffer memory1003, and an input/output (I/O) interface1004.

The data storage circuit1001may store data which is outputted from the memory controller1002or may read and output the stored data to the memory controller1002, according to a control signal generated from the memory controller1002. The data storage circuit1001may include the semiconductor device illustrated inFIG. 1. Meanwhile, the data storage circuit1001may include a nonvolatile memory that can retain stored data even when its power supply is interrupted. The nonvolatile memory may be a flash memory such as a NOR-type flash memory or a NAND-type flash memory, a phase change random access memory (PRAM), a resistive random access memory (RRAM), a spin transfer torque random access memory (STTRAM), a magnetic random access memory (MRAM), or the like.

The memory controller1002may receive a command outputted from an external device (e.g., a host device) through the I/O interface1004and may decode the command outputted from the host device to control an operation for inputting data into the data storage circuit1001or the buffer memory1003, or for outputting the data stored in the data storage circuit1001or the buffer memory1003. AlthoughFIG. 11illustrates the memory controller1002as a single block, the memory controller1002may include one controller for controlling the data storage circuit1001comprised of a nonvolatile memory and another controller for controlling the buffer memory1003comprised of a volatile memory.

The buffer memory1003may temporarily store data processed by the memory controller1002. That is, the buffer memory1003may temporarily store data outputted from or inputted to the data storage circuit1001. The buffer memory1003may store the data, outputted from the memory controller1002, according to a control signal. The buffer memory1003may read and output the stored data to the memory controller1002. The buffer memory1003may include volatile memory such as a dynamic random access memory (DRAM), a mobile DRAM, or a static random access memory (SRAM).

The I/O interface1004may physically and electrically connect the memory controller1002to the external device (i.e., the host). Thus, the memory controller1002may receive control signals and data supplied from the external device (i.e., the host) through the I/O interface1004and may output the data generated from the memory controller1002to the external device (i.e., the host) through the I/O interface1004. That is, the electronic system1000may communicate with the host through the I/O interface1004. The I/O interface1004may include any one of various interface protocols such as a universal serial bus (USB), a multi-media card (MMC), a peripheral component interconnect-express (PCI-E), a serial attached SCSI (SAS), a serial AT attachment (SATA), a parallel AT attachment (PATA), a small computer system interface (SCSI), an enhanced small device interface (ESDI) and an integrated drive electronics (IDE).

The electronic system1000may be used as an auxiliary storage device of the host or an external storage device. The electronic system1000may include a solid state disk (SSD), a USB memory, a secure digital (SD) card, a mini secure digital (mSD) card, a micro secure digital (micro SD) card, a secure digital high capacity (SDHC) card, a memory stick card, a smart media (SM) card, a multi-media card (MMC), an embedded multi-media card (eMMC), a compact flash (CF) card, or the like.