Non-volatile memory device with a program driver circuit including a voltage limiter

An embodiment non-volatile memory device includes an array of memory cells in rows and columns; a plurality of local bitlines, the memory cells of each column being coupled to a corresponding local bitline; a plurality of main bitlines, each main bitline being coupleable to a corresponding subset of local bitlines; a plurality of program driver circuits, each having a corresponding output node and injecting a programming current in the corresponding output node, each output node coupleable to a corresponding subset of main bitlines. Each program driver circuit further includes a corresponding limiter circuit that is electrically coupled, for each main bitline of the corresponding subset, to a corresponding sense node whose voltage depends, during writing, on the voltage on the corresponding main bitline. Each limiter circuit turns off the corresponding programming current, in case the voltage on any of the corresponding sense nodes overcomes a reference voltage.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims priority to Italian Patent Application No. 102020000012070, filed on May 22, 2020, which application is hereby incorporated herein by reference.

TECHNICAL FIELD

Embodiments of the present invention relate to a non-volatile memory device including a program driver circuit, which includes a voltage limiter.

BACKGROUND

As is known, nowadays non-volatile memories are widely diffused; the non-volatile memories include, as an example, phase-change memories (PCM). In particular, the phase-change memories exploit, in order to store information, the characteristics of materials having the property of switching between phases with different electrical characteristics. These materials may switch between a disorderly/amorphous phase and an orderly, crystalline or polycrystalline phase; different phases are characterized by different values of resistivity and are consequently associated with different values of a datum stored. For instance, it is possible to use elements of Group VI of the periodic table, such as tellurium (Te), selenium (Se), or antimony (Sb), referred to as “chalcogenides” or “chalcogenic materials,” to produce phase-change memory elements. In particular, an alloy made up of germanium (Ge), antimony (Sb), and tellurium (Te), known as GST (having chemical composition Ge2Sb2Te5) currently finds wide use in such memory cells.

Phase change in a memory element may be obtained by locally increasing the temperature of the cells of chalcogenic material. In particular, when the chalcogenic material of a memory cell is in the amorphous state, and thus has a high resistivity (the so-called RESET state), it is possible to apply to the memory cell a current pulse (or a suitable number of current pulses) of a duration, shape and amplitude so as to enable the chalcogenic material to cool slowly. Subjected to this treatment, the chalcogenic material changes state and switches from the high-resistivity state to a low-resistivity state (the so-called SET state). Conversely, when the chalcogenic material is in the SET state, it is possible to apply a current pulse having an appropriate duration and a large amplitude so as to cause the chalcogenic material to return to the high-resistivity amorphous RESET state.

During reading, the state of the chalcogenic material is detected by applying a voltage sufficiently low so as not to cause meaningful heating thereof, and then reading the value of the current flowing in the memory cell through a sense amplifier. Given that the current is proportional to the conductivity of the chalcogenic material, it is possible to determine in which state the material is, and consequently determine the datum stored in the memory cell.

SUMMARY

An aim of embodiments of the present invention is to provide a non-volatile memory device that will overcome at least in part the drawbacks of the prior art.

According to embodiments of the present invention, a memory device is provided as defined in the annexed claims.

DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS

The memory device1comprises a memory array2formed by a plurality of memory cells3, arranged in rows, or wordlines, and columns, or bitlines. Purely by way of example, illustrated inFIG. 1are three wordlines, designated by WL, and three bitlines, designated by BL, which enable addressing of nine memory cells3.

Each memory cell3is formed by a storage element4a, also known as phase-change element (PCE), and by a selector element4b, which are connected in series between a respective bitline BL and a terminal at a reference potential (for example, ground).

The storage element4aincludes an element made of phase-change material (for example, a chalcogenide, such as GST) and is consequently able to store data in the form of levels of resistance associated to the different phases assumed by the material itself.

The selector element4bfunctions as access device and is formed by a bipolar transistor (BJT) of a PNP type, the emitter terminal of which is connected to a first terminal of the storage element4a, while the base terminal is connected to a corresponding wordline WL. The collector terminal of the bipolar transistor is connected to ground. In this regard, each wordline WL is connected to all the base terminals of the bipolar transistors aligned along the corresponding row. Moreover, each bitline BL is connected to the second terminal of the storage elements4aaligned along the corresponding column.

In practice, given a memory cell3, the second terminal of the storage element4aand the base terminal of the bipolar transistor4bform, respectively, a bitline terminal and a wordline terminal of the memory cell3.

The memory device1further comprises a column decoder8and a row decoder10, which enable selection of the memory cells3on the basis of address signals received at input (designated as a whole by AS). The address signals AS can be generated by a control logic CL, which moreover governs the column decoder8and the row decoder10so as to enable reading and writing (also known as programming) of the memory cells3addressed by the address signals AS. The control logic CL supplies to the column decoder8and to the row decoder10also control signals in order to govern the reading/writing operations.

The column decoder8and the row decoder10enable biasing, and hence selection, of the wordlines WL and bitlines BL each time selected so as to select the memory cells3connected to them; in this way, reading and writing of the memory cells3are enabled.

In greater detail, the row decoder10is designed to select, on the basis of the address signals AS, a corresponding wordline WL. The other wordlines WL are de-selected. For this purpose, the row decoder10comprises a decoding stage4and a plurality of driving circuits6.

The decoding stage4receives the address signals AS and governs the driving circuits6according to the address signals AS. Each driving circuit6hence has an input, which is connected to the decoding stage4. Each driving circuit6moreover has an output, which is connected to a corresponding wordline WL.

Each driving circuit6biases, and hence controls, the base terminals of the bipolar transistors4bconnected to the corresponding wordline WL so as to select/de-select the wordline WL according to the address signals AS.

Column decoder8selects, according to the address signals AS, one or more bitlines BL. In practice, the column decoder8co-operates with the row decoder10in such a way that, during the steps of reading or writing of any memory cell3selected, a reading current or a writing current, respectively, flows through the storage element4aof this memory cell3. Furthermore, when a memory cell3is selected, the base terminal of its bipolar transistor4bis set at a voltage approximately null; on the contrary, when a memory cell3is not selected, the base terminal of its bipolar transistor4bis set at a positive voltage.

In particular, the column decoder8is configured for implementing within it two distinct paths towards the bitlines BL of the memory array2each time selected: a reading path, which electrically connects each bitline BL selected to a reading stage17, during the reading step; and a writing path, which electrically connects each bitline BL selected to a writing stage18, during the programming step.

The column decoder8comprises, for each reading and writing path, appropriate selection elements (in particular, transistors), which are connected so as to implement a hierarchical decoding of the addresses in order to select the memory cells3.

As illustrated schematically inFIG. 2, the memory array2is usually organized in a plurality of sectors S, each of which comprises a plurality of memory cells3. Each sector S includes a plurality of respective wordlines WL and a plurality of respective local bitlines, which are designated once again by BL and are distinct from those of the other sectors. In each sector S, the local bitlines BL are connected to the memory cells3of one and the same sector S. In addition, for each set formed by an integer number k (for example, thirty-two) of local bitlines BL, a corresponding main bitline MBL is provided. The main bitlines MBL enable, when selected at a higher hierarchical level, subsequent selection, at a lower hierarchical level, of one or more of the respective local bitlines BL and of the corresponding memory cells3. In addition, different sectors S are traversed by different wordlines WL.

The main bitlines MBL traverse a certain number of sectors S and can be selected in groups at a hierarchical decoding level even higher than the one associated to selection of the local bitlines BL.

In greater detail, the column decoder8comprises: for each sector S, at least one respective first-level decoding circuit (designated by11inFIG. 2and also known as “local column decoder”), which enables connection of the local bitlines BL to the respective main bitlines MBL both during the writing operations and during the reading operations; for each group of sectors S (constituted, in the example ofFIG. 2, by two sectors), a respective second-level decoding circuit (designated by13and also known as “global column decoder”), which enables selection of the main bitlines MBL both during the writing operations and during the reading operations.

The control logic CL sends to the second-level decoding circuit13main column-decoding signals sYN<i>, which are visible inFIG. 3and form part of the aforementioned address signals AS and on the basis of which the second-level decoding circuit13activates an electrical path between a main bitline (here designated by MBL<i>) selected and a sense amplifier45of the reading stage17, via activation of a respective main selection switch (not illustrated).

As mentioned previously,FIG. 3moreover shows how, given each sector S, each main bitline MBL<i> is associated, i.e., electrically coupleable, to a corresponding set of local bitlines, designated by BL<i,j>. It should be noted that, for simplicity, inFIG. 3the main bitlines are all denoted by MBL<i>, even though in actual fact the value of the index “i” varies; likewise, the local bitlines are all denoted by BL<i,j>, even though in actual fact the index “i” depends upon the index of the main bitline to which the local bitline can be coupled, and the index “j” ranges between 0 and k−1, for each value of the index “i”.

Furthermore, given a sector S, the corresponding first-level decoding circuit11is able to address each memory cell3coupled to a local bitline BL<i,j> of the sector S thanks to the presence of local selection switches, which are driven by respective local column-decoding signals sYO<i,j>, which are generated by the control logic CL and also form part of the aforementioned address signals AS. It should be noted that, for simplicity, inFIG. 3the two groups of local column-decoding signals with which the two first-level decoding circuits11are supplied for the two sectors S illustrated herein are both denoted by sYO<i,j>, even though in actual fact they are different, since the control logic CL does not simultaneously select local bitlines belonging to different sectors.

During the step of writing, the first-level decoding circuit11and the second-level decoding circuit13function in the same way as the one described with reference toFIGS. 2 and 3, so as to connect the selected memory cells3to circuits of the writing stage18, which are known as program driver circuits. The program driver circuits are configured to inject suitable programming currents into the selected memory cells3. Furthermore, in general the abovementioned switches of the first-level decoding circuit11and of the second-level decoding circuit13used during the step of reading may be used also during the step of writing, possibly adapting the dynamic range of the abovementioned main column-decoding signals sYN<i> and of the local column-decoding signals sYO<i,j>. As an alternative, the first-level decoding circuit11and the second-level decoding circuit13may use, during the step of writing, switches other than the ones used during the step of reading.

In greater detail,FIG. 4shows a portion of the writing stage18, which includes a program driver circuit19and a current programming circuit20.

The program driver circuit19comprises a current mirror22, which in turn comprises a first and a second mirror transistor24,26, which are P-channel enhancement MOS transistors and have source terminals connected to a supply node, which is set, in use, at a supply voltage VDD, as an example equal to 5V. Furthermore, the gate terminal of the first mirror transistor24is connected to the drain terminal of the first mirror transistor24, which in turn is connected to the current programming circuit20, so as to supply a preliminary programming current I, which is drawn by the current programming circuit20; the preliminary programming current I is directed towards the current programming circuit20and is of the pulsed type. The gate terminal of the second mirror transistor26is connected to the drain terminal of the first mirror transistor24, in a manner such that, in use, a programming current I* flows in the second mirror transistor26, which is equal to w times I, wherein w is the mirroring ratio of the current mirror22; as an example, w may be equal to ten.

The drain terminal of the second mirror transistor26forms an output node Noutof the program driver circuit19, which is coupled, during the step of writing, to the memory cell3which has to be written, i.e., to the selected memory cell3, which is connected to the selected wordline WL and to the selected local bitline BL. For instance, the coupling occurs through interposition of a local selection transistor30and a main selection transistor32, which are P-channel enhancement MOS transistors, are connected in series and form, respectively, the first-level decoding circuit11and the second-level decoding circuit13.

In particular, the drain terminal of the local selection transistor30is connected to the local bitline BL connected to the memory cell3, and thus it is connected to the second terminal of the storage element4aof the memory cell3. The source terminal of the local selection transistor30is connected to the main bitline MBL relating to the abovementioned local bitline BL, and thus it is connected to the drain terminal of the main selection transistor32. The source terminal of the main selection transistor32is connected to the output node Nout, whose voltage is equal, as an example, to 4V, because of the voltage drop along the column caused by the programming current I*. The gate terminals of the local selection transistor30and of the main selection transistor32receive, respectively, a corresponding local column-decoding signal (for brevity designated by sYO) and a corresponding main column-decoding signal (for brevity designated by sYN), which, during the step of writing, assume both the logic value ‘0’ and have voltages which, as an example, are respectively equal to 1.6V and 2.4V. Because of the abovementioned voltage drop, the voltages on the main bitline MBL and on the local bitline BL may thus be respectively equal to, as an example, 3.5V and 3V.

In practice, it happens that the so-called gate-source voltage Vgsand gate-drain voltage Vgdstay below 2V both in the case of the local selection transistor30and the case of the main selection transistor32, thanks to the values of the abovementioned voltages present on the gate terminals. Assuming that the local selection transistor30and the main selection transistor32are formed by means of a technology such that the corresponding oxides are able to withstand a voltage up to 2V, they are not at risk of being damaged.

Unfortunately, it is known that, following the occurrence of writing cycles, so-called “open bits” may appear in the memory array2, i.e., it may happen that one or more memory cells3get damaged, in which case the corresponding storage elements4apermanently behave like an open circuit, thereby preventing the current from flowing through the memory cells3. In this case, it occurs that the programming current I* cannot flow any more through the second mirror transistor26, the local selection transistor30and the main selection transistor32, which are off. Furthermore, the source and drain terminals of the local selection transistor30and of the main selection transistor32, and thus also the main bitline MBL and the local bitline BL, are set at a voltage approximately equal to the supply voltage VDD. Since the gate terminals of the local selection transistor30and of the main selection transistor32are still set at, respectively, the abovementioned voltages equal to 1.6V and 2.4V, it happens that, both in the local selection transistor30and in the main selection transistor32, the gate-source voltage Vgsand the gate-drain voltage Vgdovercome 2V, with a consequent increase of the risk of damaging the local selection transistor30and the main selection transistor32.

In other words, in the presence of open bits, an increase of the voltage occurs in the column decoder8, concurrently with the generation of the pulses of the preliminary programming current I, with consequent generation of the so-called overvoltage stress on the transistors of the column decoder8. That entails a reduction of the reliability of the column decoder8.

FIG. 5shows a memory device100, which will be described with reference to the differences with respect to the memory device1ofFIGS. 1-4, unless otherwise specified. Furthermore, elements already present in the memory device1will be designated by means of the same reference signs, unless otherwise specified.

In detail, the program driver circuit, designated by19′, comprises a current generator transistor34, which is a N-channel enhancement MOS transistor. The gate and drain terminals of current generator transistor34are respectively connected to the current programming control circuit (here designated by20′) and to the gate terminals of the first and second mirror transistors24,26. The current programming circuit20′ is configured to control the gate terminal of the current generator transistor34so that this latter is traversed by the abovementioned preliminary programming current I.

In addition, the program driver circuit19′ comprises a limiter circuit35, which includes a limiting transistor40, which is a P-channel enhancement MOS transistor. The limiter circuit35further includes a control transistor42and a first and a second additional transistors43,44, which are N-channel enhancement MOS transistors, as an example equal to the current generator transistor34. The limiter circuit35further includes a flip-flop circuit46and an inverter circuit48.

In detail, the source terminal of the limiting transistor40is connected to the output node Noutof the program driver circuit19′, whereas its drain terminal forms a control node Nctrland is connected to the drain terminal of the first additional transistor43. A voltage Vclampis present on the gate terminal of the limiting transistor40; the voltage Vclampis generated by a threshold generator circuit50of the memory device100, described in greater detail below. In addition, a voltage Vclamp_outis present on the control node Nctrl.

The gate terminal of the first additional transistor43is connected to the current programming control circuit20′, whereas the source terminal of the first additional transistor43is connected to the drain terminal of the second additional transistor44, the source terminal of which being connected to ground. The gate terminal of the second additional transistor44is set at a voltage VON, which is generated by the control logic CL. In particular, as described in greater detail below, when, during a writing step, the protection conferred by the limiter circuit35is intended to be used, the voltage VONis set to the logic value ‘1’, so that the second additional transistor44is on. To this regard, in the following description, reference will be made to the case in which the limiter circuit35is kept functioning, unless otherwise specified.

The clock input of the flip-flop circuit46is connected to the control node Nctrl, so that the output terminal Q of the flip-flop circuit46is controlled by the voltage Vclamp_out. The data input terminal of the flip-flop circuit46is set at a secondary supply voltage Vd, as an example equal to 1V. The reset input terminal of the flip-flop circuit46may be controlled by a signal sRESET generated by the control logic CL. The output terminal Q of the flip-flop circuit46is connected to the input of the inverter circuit48, the output of which is connected to the gate terminal of the control transistor42; the drain terminal of the control transistor42is connected to the source terminal of the current generator transistor34, whereas the source terminal of the control transistor42is connected to ground.

The threshold generator circuit50includes a dummy circuit52, which includes a dummy local selection transistor30*, a dummy main selection transistor32*, a dummy main bitline MBL*, a dummy local bitline BL* and a dummy memory cell3*, which are arranged in the same way as, respectively, the local selection transistor30, the main selection transistor32, the main bitline MBL, the local bitline BL and the memory cell3, but for the fact that the dummy cell3*, besides including a dummy bipolar transistor4b* which is equal to the bipolar transistors4b, includes a dummy storage element which is formed by a resistor4a*.

In addition, the threshold generator circuit50further comprises a dummy mirror transistor26*, which may be equal to the second mirror transistor26. Furthermore, a voltage V* is set on the gate terminal of the dummy mirror transistor26*, whereas the source terminal of the dummy mirror transistor26* is set at the supply voltage VDD. The drain terminal of the dummy mirror transistor26* forms a dummy output node Nout*, which is connected to the source terminal of the dummy main selection transistor32*.

The voltages on the gate terminals of the dummy local selection transistor30* and the dummy main selection transistor32* are respectively designated by sYO* and sYN*; they are respectively equal to the voltages of the main column-decoding signals sYN and of the local column-decoding signals sYO when these latter respectively select the corresponding main bitlines MBL and the corresponding local bitlines BL during the writing operations. In addition, the base terminal of the dummy bipolar transistor4b* is set at the same voltage present on the selected wordline WL (e.g., it is set to ground).

The threshold generator circuit50further comprises an operational amplifier54, a third additional transistor56, an output transistor58and a bias transistor60.

The output transistor58and the bias transistor60are P-channel enhancement MOS transistors; furthermore, the output transistor58is equal to the limiting transistor40. The source terminal of the bias transistor60is set to the supply voltage VDD, whereas the drain terminal of the bias transistor60is connected to the negative input terminal of the operational amplifier54, the positive input terminal of which is connected to the dummy output node Nout*. The gate terminal of the bias transistor60is set at a voltage Vpbias, which may be linked to the voltage present on the gate terminal of the first additional transistor43. As an example, the voltage Vpbiasmay be such that the bias transistor60is on, and the current which flows through the bias transistor60, and thus through the output transistor58, is equal to, purely as an example, half the current which flows in the first additional transistor43. In any case, the precise value of the current flowing in the bias transistor60is irrelevant.

The source terminal of the output transistor58is connected to the drain terminal of the bias transistor60, and thus also to the negative input terminal of the operational amplifier54. The gate terminal of the output transistor58is connected to output terminal of the operational amplifier54. The drain terminal of the output transistor58is connected to the drain terminal of the third additional transistor56. The source terminal of the third additional transistor56is connected to ground, whereas the gate terminal of the third additional transistor56is set to the voltage VON, so that the third additional transistor56is on during writing, if the open bit detection is being carried out.

From an operative point of view, the operational amplifier54implements a voltage follower scheme and generates, on its output terminal, the voltage Vclamp, which controls the limiting transistor40.

In addition, the voltage V* is generated by means (as an example) of a dedicated current mirror (not shown; as an example, formed within the current programming circuit20′), so that a dummy current I** flows through the dummy mirror transistor26*, the dummy main selection transistor32*, the dummy local selection transistor30* and the resistor4a*. Furthermore, the voltage V* may be set equal to a value such that the dummy current I** is equal to the maximum current which, during any writing operation (i.e., either of the set type or the reset type), flows in the memory cell3to be written, in the absence of open bit. As an example, the dummy current I** may be equal to the maximum current which, during a reset operation, flows in the memory cell3to be written, in case the reset operation requires an higher current than the set operation.

This having been said, it is possible to demonstrate that the following equation holds:
Vclamp=Vbe+R*(I**)+V′+V″−Vth

wherein: Vbeis the emitter-base voltage of the dummy bipolar transistor4b*; R is the resistance of the resistor4a*; I** is the abovementioned dummy current; V′ is the source-drain voltage of the dummy local selection transistor30*; V″ is the source-drain voltage of the dummy main selection transistor32*; and Vthis the threshold voltage of the output transistor58.

Given that each storage element4ahas a value of resistance which varies during the writing step (because of the melting of the phase-change material), the value of the resistance R of the resistor4a* may be set equal to the greatest value of resistance which can be assumed by the storage elements4aduring any writing step (i.e., considering either the set operation and the reset operation).

Without any loss of generality, the memory device100includes, for each main bitline MBL, a corresponding program driver circuit19′; the program driver circuits19′ share the current programming circuit20′ and the threshold generator circuit50. In addition, the threshold generator circuit50generates the voltage Vclampin a manner such that the sum of the voltage Vclampand the threshold voltage Vthof the output transistor58simulates the greatest allowed voltage on the output node Noutin the absence of the open bit.

This having been said, referring to the program driver circuit19′ shown inFIG. 5, and assuming that the control logic CL has performed a reset of the flip-flop circuit46through the signal sRESET, so that the output terminal Q is set to ‘0’, the following occurs.

By referring to the voltage on the output terminal Q of the flip-flop circuit46as the voltage Vint, this voltage Vintis set to ‘0’, as explained before. Therefore, the voltage on the output of the inverter circuit48(hereinafter referred to as nVint) is set to ‘1’, thus the control transistor42is above threshold; as a consequence, the preliminary programming current I flows in the current generator transistor34and the programming current I* is injected by the second mirror transistor26into the output node Nout. Furthermore, the dummy current I** flows in the resistor4a*.

By referring to the voltage Voutto designate the voltage on the output node Nout, the limiting transistor40is off, as long as the voltage Voutis lower than Vclamp+Vth40, with Vth40which designates the threshold voltage of the limiting transistor40, which is equal to the abovementioned voltage Vth. Therefore, the voltage Vclamp+Vth40is equal to the greatest voltage which should be present on the output node Noutin the absence of the open bit.

In view of the above, when the memory cell3functions properly (i.e., there is no open bit), the limiting transistor40is off, because the voltage on the main bitline MBL and on the local bitline BL is limited, as explained with reference toFIG. 4. Therefore, since the first and the second additional transistors43,44are above threshold, the control node Nctrlis connected to ground, and the voltage Vclamp_outis equal to ‘0’, i.e., it stays constant, at a value nearly equal to 0V. Consequently, the voltage Vinton the output terminal Q of the flip-flop46remains equal to ‘0’, and the voltage nVintremains equal to ‘1’.

On the contrary, in case an open bit occurs in the memory cell3, the voltage Vouttends to rise, because, as explained with reference toFIG. 4, the voltages on the main bitline MBL and on the local bitline BL tend, in the absence of any countermeasure, to assume a voltage nearly equal to the supply voltage VDD. Therefore, the voltage Voutovercomes the voltage Vchamp+Vth40, and the limiting transistor40turns on. Consequently, the voltage Vclamp_outbecomes equal to ‘1’, thereby causing a switching of the voltage Vinton the output terminal Q of the flip-flop46, which becomes equal to T. In turn, such a switching causes a switching of the logic value of the voltage nVinton the output terminal of the inverter circuit48, which becomes equal to ‘0’. The control transistor42thus turns off, thereby turning off also the preliminary programming current I and the programming current I*. Therefore, the duration of the pulse of the programming current I* is reduced, as an example to no more than 10 nanoseconds, so as to reduce the duration of the time interval in which the voltages on the main bitline MBL and on the local bitline BL can put at risk the local selection transistor30and the main selection transistor32. In such a way, the local selection transistor30and the main selection transistor32are protected, also in case of occurrence of an open bit in the memory cell3.

From another point of view, the voltage Vclamp_out results from the comparison between the current flowing through the first additional transistor43and the current flowing through the limiting transistor40, this latter being substantially equal to the current flowing through the output transistor58and being thus set by the voltage Vpbias, so that the ratio between the abovementioned currents flowing through the first additional transistor43and the limiting transistor40falls within a predetermined range (e.g., between 0.1 and 10). This having been said, if the current flowing through the first additional transistor43is respectively greater than, or lower than, the current flowing through the limiting transistor40, the voltage Vclamp_out is respectively equal to the logic value ‘0’ or to the logic value ‘1’.

According to the embodiment shown inFIG. 5, the memory device100includes one program driver circuit19′ for each main bitline MBL.FIG. 6shows a further embodiment, in which each program driver circuit (designated by19″) is coupled to more than one main bitline. This embodiment will be described with reference to the differences over the memory device100ofFIG. 5, unless otherwise specified. Furthermore, elements already present in the memory device100will be designated by means of the same reference signs, unless otherwise specified.

In detail, in the memory device (designated by200) ofFIG. 6, each program driver circuit19″ (only one shown inFIG. 6) can be coupled to, as an example, four main bitlines, which are respectively designated by MBL<0>-MBL<3>; the corresponding four main selection transistors32are controlled by the main column-decoding signals sYN<0>-sYN<3>, which are generated by the control logic CL so that only one of them is set to ‘1’, at a time, the others being set to ‘0’. In addition, for each of the main bitlines <1>-MBL<4>, only one of the corresponding k local bitlines BL is shown inFIG. 6; the local column-decoding signals controlling the corresponding four local selection transistors30are respectively designated by sYO′, sYO″, sYO′″ and sYO″″.

In greater detail, the limiter circuit35comprises, for each main bitline, a corresponding limiting transistor; inFIG. 6, the four limiting transistors are respectively designated by40′,40″,40′″ and40″″. Each of the limiting transistors40′-40″″ is a P-channel enhancement MOS transistor, which is equal to the output transistor58.

Each of the limiting transistors40′-40″″ has a source terminal, which is connected to the corresponding main bitline MBL<0>-MBL<3>, and a corresponding drain terminal, which is connected to the drain terminal of the first additional transistor43, i.e., to the control node Nctrl; the voltage on the control node Nctrlis still referred to as voltage Vclamp_out. The gate terminals of the limiting transistors40′-40″″ receive the voltage Vclampgenerated by the threshold generator (designated by250), which is shared among the program driver circuits19″.

As shown inFIG. 7, the threshold generator250is the same as the one shown inFIG. 5, but for the following differences.

In detail, the positive input terminal of the operational amplifier54is connected to the dummy main bitline MBL*. Therefore, the dummy main selection transistor32* is outside the control loop which generates the voltage Vclamp. In addition, in this case the following equation applies:
Vclamp=Vbe+R*(I**)+V′−Vth

In practice, the sum of the voltage Vclampand the threshold voltage Vthof the output transistor58simulates the greatest allowed voltage on the main bit line MBL coupled to the selected memory cell3in the absence of the open bit.

Basically, the memory device200functions in the same way as the memory device100. In particular, as mentioned before, at any time, only one of the main selection transistors32coupled to the main bitlines MBL<0>-MBL<3> is on, i.e., only the main selection transistor32connected to the selected main bitline MBL is on. As an example, in the following it is assumed that the main bitline MBL<0> has been selected. Furthermore, in case an open bit occurs during the writing of one of the memory cells3connected to one of the k local bitlines BL which can be coupled to the main bitline MBL<0>, the voltage on the main bitline MBL<0> (designated by VMBLinFIG. 6) tends to rise; however, when the voltage on the main bitline MBL<0> overcomes the voltage Vclamp+Vth40′(with Vth40′which designates the threshold voltage of the limiting transistor40′), the limiting transistor40′ turns on; the voltage Vclamp+Vth40′is equal to the greatest voltage which should be present on the main bitline MBL<0> in the absence of the open bit. Consequently, the voltage Vclamp_outbecomes equal to ‘1’, thereby causing a switching of the logic value of the voltage Vinton the output terminal Q of the flip-flop circuit46, which becomes equal to ‘1’. Therefore, the preliminary programming current I and the programming current I* are turned off, in the same way as described with reference to the memory device100.

Still with reference to the embodiment ofFIGS. 6-7, the dummy main selection transistor32* does not concur in determining the voltage Vclamp, therefore this latter better emulates the voltage which should be present on the selected main bitline MBL in the absence of the open bit.

Further embodiments are possible, as an example in which the mechanism of injection of the programming current I* in the output node Noutis different from the one previously described.

As an example,FIG. 8shows an embodiment which is the same as the one ofFIGS. 6-7, but for the following differences.

In detail, the selector element of each memory cell3is formed by a corresponding access transistor (here designated by5b), which is a N-channel enhancement MOSFET transistor. Furthermore, the drain terminal of each access transistor5bis connected to the corresponding storage element4a, whereas the source terminal is connected to ground. In case of selection of the corresponding wordline WL, the gate terminal of any access transistor5bis set to ‘1’, in a per se known manner.

The memory device (here designated by300) comprises a current controller20″, which is shared among the program driver circuits (here designated by19′″; only one shown inFIG. 8). Furthermore, each program driver circuit19′″ comprises a driving switch301and an injection transistor302, which is a P-channel enhancement MOSFET transistor.

The source terminal of the injection transistor302is set at the supply voltage VDD, whereas the drain terminal is connected to the output node Nout. The driving switch301is controlled by a voltage Vint′, so as to, alternatively, i) couple the gate terminal of the injection transistor302to the current controller20″ (when Vint′ is equal to the logic value ‘0’) or ii) set it to the supply voltage VDD(when Vint′ is equal to the logic value ‘1’). In particular, when the gate terminal of the injection transistor302is coupled to the current controller20″, the injection transistor302injects the programming current I* in the output node Nout; on the contrary, when the gate terminal of the injection transistor302is set to the supply voltage VDD, the injection transistor302is off.

In addition, the memory device300further comprises a cascode transistor304, a current generator306and a latch circuit308.

The cascode transistor304is a N-channel enhancement MOSFET transistor, whose drain terminal and source terminal are respectively connected to the control node Nctrl, and to the current generator306, this latter being also connected to ground and being configured to generate a bias current Ib.

A first input of the latch circuit308is connected to the source terminal of the cascode transistor304, whereas the second input terminal of the latch circuit308receives the signal sRESET.

In use, the cascode transistor304is kept on by the control logic CL, by setting its gate terminal at a voltage Vcasn, as an example equal to 1.5V. Furthermore, a voltage Vclamp_out′ is present on the first input of the latch circuit308, which has the same logic value of the voltage Vclamp_outon the control node Nctrl. In particular, if the voltage Vclamp_outis respectively equal (as an example) to 0V or 4.5V, the voltage Vclamp_out′ is respectively equal to 0V or 1V, due to the presence of the cascode transistor304.

The latch circuit308generates on its output the abovementioned voltage Vint′, as a function of the voltage

Vclamp_out′, and thus as a function of the voltage Vclamp_out, so—that the voltage Vint′ has the same logic value as the voltage Vclamp_out′.

The threshold generator circuit (here designated by350) is the same as the one ofFIG. 7, but for the following differences.

The gate terminal of the dummy mirror transistor26* is set at the voltage V*, so that that the dummy current I** is equal to the maximum current which, during any writing operation (i.e., either of the set or reset type), flows in the memory cell3to be written.

The voltage Vpbiasis such that the bias transistor60is on, and the current which flows through the bias transistor60is equal to, as an example, half the current which flows in the current generator306.

In addition, in the place of the dummy bipolar transistor4b*, a dummy MOSFET transistor5b* is present, which is equal to the access transistors5b. The gate terminal of the dummy MOSFET transistor5b* is set by the control logic CL at a voltage Ven_clamp, which is the same as the voltage present on the wordlines WL when selected, so as to keep the dummy MOSFET transistor5b* on.

The functioning of the memory device300is the same as the one of the memory device200.

In detail, by considering that the voltage drop on the dummy MOSFET transistor5b* is negligible, the following equation applies:
Vclamp=R*(I**)+V′−Vth

In use, after a reset of the latch circuit308through the signal sRESET, the voltage Vint′ is equal to the logic value ‘0’, so as to force the driving switch301to connect the gate terminal of the injection transistor302to the current controller20″, so as to generate the programming current I*.

Assuming as an example that the main bitline MBL<0> has been selected and assuming that an open bit occurs during the writing of one of the memory cells3connected to one of the k local bitlines BL which can be coupled to the main bitline MBL<0>, the voltage on the main bitline MBL<0> tends to rise; however, when the voltage on the main bitline MBL<0> (designated by VMBLinFIG. 8) overcomes the voltage Vclamp+Vth40′(with Vth40′which designates the threshold voltage of the limiting transistor40′), the limiting transistor40′ turns on. Consequently, the voltages Vclamp_out, Vclamp_out′ and Vint′ become equal to ‘1’; therefore the voltage Vint′ forces the driving switch301to disconnect the gate terminal of the injection transistor302from the current controller20″, and to set it to the supply voltage VDD. In such a way, the injection transistor302turns off, and the programming current I* is turned off, thereby protecting the memory device300. From another point of view, the voltage Vclamp_out′ results from the comparison between the current flowing through the current generator306and the current flowing through the limiting transistor40′ and the cascode transistor304, this latter being substantially equal to the current flowing through the output transistor58and being thus set by the voltage Vpbias, so that the ratio between the currents flowing through the current generator306and the limiting transistor40′ falls within a predetermined range (e.g., between 0.1 and 10). This having been said, if the current flowing through the current generator306is respectively greater than, or lower than, the current flowing through the limiting transistor40′, the voltage Vclamp_out′ is respectively equal to the logic value ‘0’ or to the logic value ‘1’.

The memory device300further comprises a logic gate310of the ‘OR’ type. In particular, in order to detect the occurrence of an open bit in the memory array2, the voltages Vint′ (only one shown inFIG. 8) of all the program driver circuits19′″ are used as inputs of the logic gate310, so that the output of the logic gate310goes to ‘1’ as soon as one of the voltages Vint′ goes to ‘1’. Such a circuit scheme may be implemented also in the embodiment shown inFIGS. 6-7. However, by referring to the output voltage of the abovementioned logic gate310as the signal OpenB_det, such a signal OpenB_det allows detecting the occurrence of an open bit, but it does not allow identifying the group of main bitlines MBL connected to the memory cell3in which the open bit has occurred during the writing. In order to provide also this functionality, it is possible to implement the embodiment shown inFIG. 9, in which the memory device is designated by400.

Without any loss of generality, the embodiment ofFIG. 9makes reference to the embodiment ofFIGS. 6-7, under the assumption that the memory device400includes a first, a second and a third program driver circuits19a″,19b″,19c″ arranged in sequence, each of which is associated to a corresponding group of four main bitlines MBL (not shown), as well as to a corresponding control node Nctrl. In other words, although not shown, each of the first, second and third program driver circuits19a″,19b″,19c″ is coupled to a corresponding portion of the memory array2(not shown inFIG. 9) in the same way as shown inFIG. 6. To this regard, inFIG. 9, for each of the first, second and third program driver circuits19a″,19b″,19c″, the corresponding part other than the corresponding inverter circuit48and the corresponding flip-flop circuit46is schematically shown as a box, designated by499.

The voltages on the control nodes Nctrlof the first, second and third program driver circuits19a″,19b″,19c″ are respectively designated by Vclamp_out_A, Vclamp_out_Band Vclamp_out_C. The voltages on the outputs of the inverter circuits48of the first, second and third program driver circuits19a″,19b″,19c″ are respectively designated by SnVint_A, SnVint_Band SnVint_C; the voltages on the outputs of the flip-flop circuits46of the first, second and third program driver circuits19a″,19b″,19c″ are respectively designated by SVint_A, SVint_Band SVint_C.

In addition, the memory device400includes, for each of the first, second and third program driver circuits19a″,19b″,19c″, a corresponding first multiplexer401and a corresponding second multiplexer402.

In detail, the first and second input terminals of the first multiplexer401of the first program driver circuit19a″ are respectively connected to the secondary supply voltage Vdand to the output of the inverter circuit48of the second program driver circuit19b″, to receive the voltage SnVint_B. The first input terminal of the second multiplexer402of the first program driver circuit19a″ is connected to the corresponding control node Nctrl, to receive the voltage Vclamp_out_A. The second input terminal of the second multiplexer402of the first program driver circuit19a″ receives a clock signal scan_ck, which may be generated by the control logic CL.

The outputs of the first and second multiplexers401,402of the first program driver circuit19a″ are connected, respectively, to the data input terminal and to the clock input terminal of the corresponding flip-flop circuit46.

The first and second input terminals of the first multiplexer401of the second program driver circuit19b″ are respectively connected to the secondary supply voltage Vdand to the output of the inverter circuit48of the third program driver circuit19b″, to receive the voltage SnVint_C. The first input terminal of the second multiplexer402of the second program driver circuit19b″ is connected to the corresponding control node Nctrl, to receive the voltage Vclamp_out_B. The second input terminal of the second multiplexer402of the second program driver circuit19b″ receives the clock signal scan_ck.

The outputs of the first and second multiplexers401,402of the second program driver circuit19b″ are connected, respectively, to the data input terminal and to the clock input terminal of the corresponding flip-flop circuit46.

The first and second input terminals of the first multiplexer401of the third program driver circuit19c″ are respectively connected to the secondary supply voltage Vdand to ground. The first input terminal of the second multiplexer402of the third program driver circuit19c″ is connected to the corresponding control node Nctrl, to receive the voltage Vclamp_out_C. The second input terminal of the second multiplexer402of the third program driver circuit19c″ receives the clock signal scan_ck.

The outputs of the first and second multiplexers401,402of the third program driver circuit19c″ are connected, respectively, to the data input terminal and to the clock input terminal of the corresponding flip-flop circuit46.

All the first and second multiplexers401,402are controlled by means of a signal scan_en generated by the control logic CL, so that, when the signal scan_en is equal to the logic value ‘0’, each of the first and second multiplexers401,402connects its output terminal to its first input terminal, and when the signal scan_en is equal to the logic value ‘1’, each of the first and second multiplexers401,402connects its output terminal to its second input terminal. To this regard, the control logic CL may be controlled (i.e., programmed), in a per se known manner, so as to set the signal scan_en equal to ‘0’ (e.g., in normal use) or to ‘1’ (e.g., during a failure analysis).

In addition, the memory device400includes a logic gate410of the ‘OR’ type, which receives at input the voltages SVint_A, SVint_Band SVint_Cand generates the signal OpenB_det.

Basically, when the control logic CL sets the signal scan_en equal to the logic value ‘0’, the memory device400functions as the memory device200. In this case, the voltages SnVint_A, SnVint_Band SnVint_Care equal to voltages nVintwhich are generated, respectively, by the inverter circuits48of the first, second and third program driver circuits19a″,19b″,19c″; similarly, the voltages SVint_A, SVint_Band SVint_Care equal to voltages Vintwhich are generated, respectively, by the flip-flop circuits46of the first, second and third program driver circuits19a″,19b″,19c″. Therefore, the signal OpenBit_det is equal to ‘0’ in the absence of open bit and is equal to ‘1’ when an open bit occurs, irrespective of the position of the open bit.

In practice, in normal use the signal scan_en is equal to ‘0’, and the control logic CL can detect, based on the signal OpenBit_det, the occurrence of an open bit during a writing step. To this regard, in a per se known manner, during the writing the first, second and third program driver circuits19a″,19b″,19c″ share the same address, i.e., they select and write at the same time respective selected memory cells3which have the same relative position, i.e., are addressed by means of the same pair of local and main column-decoding signals. As an example, by assuming that the shared address corresponds to the U-th main bitline MBL and to the L-th local bitline BL, each of the first, second and third program driver circuits19a″,19b″,19c″ selects the respective main bitline MBL<U> and the respective local bitlines BL<L>, only the local bitline BL<L> which is coupled to the main bitline MBL<U> being traversed by the programming current I*.

In addition, as explained before, the control logic CL can be controlled so as to set the signal scan_en equal to ‘1’, as an example after the detection of the occurrence of an open bit during a writing step involving a selected local bitline BL, a selected main bitline MBL and a selected wordline WL. When the control logic CL sets the signal scan_en equal to the logic value ‘1’, the memory device400implements a scan chain, as described here below.

In detail, the switching of the signal scan_en to ‘1’ implies that the voltages (in particular, the corresponding logic values) on the output terminals Q of the flip-flops46, and thus also on the output terminals of the inverter circuits48, “freeze”, i.e. they do not change, until the control logic CL generates a pulse of the clock signal scan_ck, as described here below. Therefore, also the logic values of the voltages SnVint_A, SnVint_Band SnVint_Cremain stuck to the corresponding logic values which were generated during the abovementioned writing step (i.e., during the last writing step with the signal scan_en equal to ‘0’), until the control logic CL generates a pulse of the clock signal scan_ck.

In addition, the logic values on the data inputs of the flip-flop circuits46of the first and second program driver circuits19a″,19b″ are respectively equal to the logic values of the voltages SnVint_Band SnVint_C, which, as said before, are respectively equal to the voltages nVintwhich were generated by the inverter circuits48of the second and third program driver circuits19b″,19c″ during the abovementioned writing step (i.e., when the signal scan_en was equal to ‘0’); similarly, as said before, the logic value of the voltage SnVint_Ais equal to the logic value of the voltage nVintwhich was generated by the inverter circuit48of the first program driver circuit19a″ during the abovementioned writing step. Therefore, the logic values of the voltages SnVint_A, SnVint_Band SnVint_Cvdepend on whether the open bit occurred in a memory cell3coupled to the corresponding program driver circuit, or not.

This having been said, by referring to the signal scan_out to designate the signal present on the output terminal of the inverter circuit48of the first program driver circuit19a″ when the signal scan_en is equal to ‘1’, it happens as follows.

Each group formed by the flip-flop circuit46, the inverter circuit48and the first and second multiplexers401,402of any of the first, second and third program driver circuits19a″,19b″,19c″ acts as a reconfigurable circuit, which operates in a different mode, based on the logic value of the signal scan_en. Furthermore, when the signal scan_en is equal to ‘1’, the input of each reconfigurable circuit is coupled to the output of the following reconfigurable circuit, so as to receive the logic value present on this latter and transfer this logic value onto its own output, when a pulse of the clock signal scan_ck occurs.

In view of the above, after the switching to ‘1’ of the signal scan_en, the signal scan_out has a first logic value, which is equal to the logic value of the voltage SnVint_A, which is equal to ‘1’ if the open bit occurred in a memory cell3connected to the first program driver circuit19a″, otherwise it is equal to ‘0’.

After a first pulse of the clock signal scan_ck, the signal scan_out has a second logic value, which is the same as the logic value of the voltage SnVint_B, which is equal to ‘1’ if the open bit occurred in a memory cell3connected to the second program driver circuit19b″, otherwise it is equal to ‘0’.

After a second pulse of the clock signal scan_ck, the signal scan_out has a third logic value, which is the same as the logic value of the voltage SnVint_C, whose logic value is equal to ‘1’ if the open bit occurred in a memory cell3connected to the third program driver circuit19c″, otherwise it is equal to ‘0’.

Therefore, based on the abovementioned first, second and third logic values assumed by the signal scan_out, the control logic CL can determine whether the open bit occurred in a memory cell3written either by the first or the second or the third program driver circuits19a″,19b″,19c″; furthermore, by referring to the abovementioned selected main bitline MBL, selected bitline BL (in particular, to the corresponding main column-decoding signal and corresponding local column-decoding signal) and selected wordline WL, the control logic CL can determine the memory cell3in which the open bit occurred.

Although not shown, embodiments are possible, which are the same as the one shown inFIG. 9, but in which the program driver circuits are of the types shown inFIG. 5 or 8; the threshold generator circuit may vary accordingly.

FIG. 10shows an example of application of a memory device (designated by500) according to any of the preceding. In particular,FIG. 10illustrates a portion of an electronic apparatus570, which may, for example, be: a PDA (personal digital assistant); a portable or fixed computer, possibly with wireless data-transfer capacity; a mobile phone; a digital audio player; a photographic camera or a camcorder; or further devices that are able to process, store, transmit, and receiving information.

In detail, the electronic apparatus570comprises: a controller571(for example, provided with a microprocessor, a DSP, or a microcontroller); an input/output device572(for example, provided with a keypad and a display), for input and display of the data; the memory device500; a wireless interface574, for example an antenna, for transmitting and receiving data through a radiofrequency wireless communication network; and a RAM575. All the components of the electronic apparatus570are coupled through a bus576. It is possible to use a battery577as electrical supply source in the electronic apparatus570, which may moreover be provided with a photographic or video camera578. In addition, the controller571can control the memory device500, for example by co-operating with the control logic CL.

The advantages provided by the present memory device are made clear by the above description.

In particular, the present solution allows avoiding the occurrence of overvoltage stresses on the transistors of the column decoder, in case an open bit occurs during a writing step, so as to protect the transistors. Furthermore, the implementation of the threshold generator circuit, which includes a dummy circuit, allows precisely generating a reference voltage which simulates the voltage which occurs in the column decoder, in the absence of open bits.

Basically, the protection is obtained, in each program driver circuit, by sensing, for each main bitline coupleable of the program driver circuit, a corresponding sense node, which, in case of a single main bitline coupleable to the program driver circuit, coincides with the output node Noutof the program driver, and, in case of more than one main bitlines coupleable to the program driver circuit, coincides with the main bitline. In both cases, the voltage on the sense node at least depends on (or may even coincide with) the voltage on the corresponding main bitline, when the selected memory cell coupled to the output node Noutof the program driver circuit (i.e., the cell written by the considered program driver circuit) is coupled to the corresponding main bitline (i.e., and not to the other, if any, main bitlines coupleable to the considered program driver circuit).

In addition, the control logic CL may optimize the writing strategies, based on the detection of possible open bits. As an example, in case of a writing operation of the set type (i.e., to write the logic value ‘1’ in a memory cell storing the logic value ‘0’) with an open bit, the memory cell is always read as zero; therefore, the control logic CL verifies the state and tries to provide more pulses to set the logic value ‘1’. However, the limiter circuit35may turn off the programming current I* during the first pulse and prevent the generation of further pulses of the programming current I*.

Some embodiments also allow not only to protect the memory device, but also to identify the damaged memory cells.

Finally, it is clear that modifications and variations may be made to what has been described and illustrated herein, without thereby departing from the scope of the present invention, as defined in the annexed claims.

As an example, the limiter circuit may be different from the embodiments described above. As an example, embodiments (not shown) are possible, which are respectively the same as corresponding ones described before, but in which an additional transistor is present. This additional transistor may be a N-MOS enhancement transistor, whose drain and source terminals are respectively connected the control node Nctrl, and to ground; furthermore, the gate terminal of this additional transistor is controlled by means of a voltage which is generated by the control logic CL so as to be equal to the logic negation of the voltage VON, so as to force to ground the voltage Vclamp_out, in case of a writing operation in which the limiter circuit is not intended to be used (i.e., when the voltage VONis equal to ‘0’), without affecting the functioning of the limiter circuit when the voltage VON is equal to ‘1’.

In a per known manner, the control logic CL may implement different writing strategies. As an example, the control logic CL may set to ‘1’ the signal sRESET after each writing operation; in this way, the limiter circuit is ready for the following writing operation, as an example on a following address.

Finally, as said before, the memory cells may be of a type different from what has been described.