Manufacturing method of thin film transistor display panel

Provided is a manufacturing method of a thin film transistor array panel including: formation of a gate line including a gate electrode on a substrate; formation of sequentially a gate insulating layer, an active layer, a data metal layer, and a photoresist etching mask pattern on the gate line; etching the data metal layer with the same shape as the photoresist etching mask pattern; etching the active layer by using the photoresist etching mask pattern; formation of a data line including a source electrode and a drain electrode for completing a channel region on the active layer; and formation of a pixel electrode exposing the drain electrode and electrically connected with the drain electrode, in which in the etching of the active layer, a dry-etch process is performed by using gas including at least one of NF3 and H2.

CLAIM OF PRIORITY

This application claims the priority to and all the benefits accruing under 35 U.S.C. §119 of Korean Patent Application No. 10-2015-0000232 filed in the Korean Intellectual Property Office (KIPO) on Jan. 2, 2015, the entire contents of which are incorporated herein by reference.

BACKGROUND OF THE INVENTION

1. Field of Disclosure

The present invention relates to a manufacturing method of a thin film transistor array panel.

2. Description of the Related Art

A display device may use a flat panel display, and as the flat panel display, various display devices such as a liquid crystal display, an organic light emitting diode display, a plasma display device, an electrophoretic display device, and an electrowetting display device may be used.

A representative liquid crystal display among them, which is one of the most common types of flat panel displays currently in use, includes two display panels with field generating electrodes such as a pixel electrode and a common electrode, and a liquid crystal layer interposed therebetween, and includes a backlight unit which provides light onto the display panels sandwiched with the liquid crystal layer therebetween. The liquid crystal display generates an electric field in the liquid crystal layer by applying a voltage to the field generating electrodes, determines directions of liquid crystal molecules of the liquid crystal layer by the generated electric field, and controls an emission amount of light provided by the backlight unit, thereby displaying images.

Generally, a plurality of gate lines which are parallel to each other, and a plurality of source lines which insulatively cross the gate lines are formed on the display panel, and pixels are formed for each region surrounded by the gate lines and the data lines. In each pixel, a pixel electrode and a switching element (thin film transistor) applying a pixel voltage to the pixel electrode are disposed.

The thin film transistor array panel includes a gate electrode which is a part of the gate line, a semiconductor layer forming a channel, and a source electrode and a drain electrode which are a part of the data line. The thin film transistor is a switching element that transfers or blocks an image signal transferred through the data line to the pixel electrode according to a scanning signal transferred through the gate line.

Meanwhile, the gate lines, the data lines, and the switching element are formed by a photolithography process using an exposure mask.

Since the exposure mask forms a large part in manufacturing cost, recently, a four-sheet mask process and a five-sheet mask process have been developed in order to reduce the manufacturing cost and the manufacturing process.

For example, in the four-sheet mask process, a source metal pattern including a source line is formed by sequentially coating a semiconductor layer, an ohmic contact layer, and a metal layer on a base substrate where a gate metal pattern including the gate line is formed and patterning the metal layer by a photolithography process. Subsequently, in the source metal pattern, a channel layer which is patterned to be the same as the source metal pattern, is formed by dry-etching the ohmic contact layer and the semiconductor layer by an etching mask. Generally, in the dry-etch process for forming the channel layer, HCl or SF6gas is used as etching gas.

Meanwhile, in the dry-etch process, since the source metal pattern is exposed to dry-etching gas, the etching gas reacts with the metal material forming the source metal pattern to form reaction by-products. There is a problem in that the reaction by-products formed above remain around the source metal pattern to cause a wiring defect. Particularly, when the source metal pattern includes copper (Cu) having weak chemical resistance, there is a problem in that the above-mentioned reaction by-products are significantly increased.

SUMMARY OF THE INVENTION

The present invention has been made in an effort to provide a manufacturing method of a thin film transistor array panel having advantages of preventing corrosion of a source metal pattern by preventing an etch surface of the source metal pattern from being exposed in a dry-etch process.

An exemplary embodiment of the present invention provides a manufacturing method of a thin film transistor array panel including the formation of a gate line including a gate electrode on a substrate; the sequential formation of a gate insulating layer, an active layer, a data metal layer, and a photoresist etching mask pattern on the gate line; etching of the data metal layer with the same shape as the photoresist etching mask pattern; etching of the active layer by using the photoresist etching mask pattern; the formation of a data line including a source electrode and a drain electrode on the active layer; and the formation of a pixel electrode exposing the drain electrode and electrically connected with the drain electrode, in which in the etching of the active layer, a dry-etch process based on NF3and H2gas series is used.

The active layer may include an intrinsic amorphous silicon layer and an impurity doped amorphous silicon layer sequentially formed on the gate insulating layer.

Etching of the active layer may further include formation of a silicon compound on an etch surface of the data metal layer by the dry-etch process.

The formation of the data line may include exposing a part of the data metal layer by etching the photoresist etching mask pattern with a predetermined thickness through ashing; and formation of a source electrode and a drain electrode of the thin film transistor by etching the exposed data metal layer.

In the formation of the source electrode and the drain electrode of the thin film transistor, the data metal layer may be etched by a wet etching process.

In this case, when the wet etching process for the data metal layer is performed, the silicon compound formed on the etch surface of the data metal layer may prevent the etch surface of the data metal layer from being etched.

Further, at least one of low pressure and high bias power may be set to be satisfied as the ashing condition of the photoresist etching mask pattern.

The manufacturing method may further include etching the impurity doped amorphous silicon layer exposed between the source electrode and the drain electrode of the thin film transistor.

In this case, etching of the impurity doped amorphous silicon layer exposed between the source electrode and the drain electrode of the thin film transistor may be performed by a wet etching process.

Further, in the etching of the impurity doped amorphous silicon layer exposed between the source electrode and the drain electrode of the thin film transistor, the silicon compound formed on the etch surface of the data metal layer may be etched.

According to the exemplary embodiment of the present invention, it is possible to prevent corrosion of the source metal pattern by depositing a silicon compound on a side of a data metal layer during the dry-etch process and preventing an etch surface of the data metal layer from being exposed through the deposited silicon compound, by using a NF3/H2gas-based dry-etch process.

DETAILED DESCRIPTION OF THE INVENTION

Hereinafter, a thin film transistor array panel according to an exemplary embodiment of the present invention will be described in detail with the accompanying drawings

FIG. 1is a plan view illustrating a thin film transistor array panel according to an exemplary embodiment of the present invention, andFIG. 2is a cross-sectional view taken along line II′-II″ ofFIG. 1.

First, referring toFIGS. 1 and 2, the liquid crystal display includes a thin film transistor array panel100, an upper panel200, a liquid crystal layer3interposed between the two display panels100and200, and a backlight unit300positioned below the thin film transistor array panel100. Further, the position of the backlight unit300is not limited to a position facing the thin film transistor array panel100, and the backlight unit300may be disposed at a position facing the upper panel200.

First, the thin film transistor array panel100will be described.

On a first insulation substrate110made of transparent glass or plastic, a plurality of gate lines extended in a first direction and a plurality of data lines extended in a second direction crossing the first direction are positioned. A plurality of pixel units is defined by the gate lines and the data lines on the first insulation substrate110.

The gate line121transfers a gate signal and extends mainly in a horizontal direction. Each gate line121includes a plurality of gate electrodes124protruding from the gate line121and a gate pad129which is a wide end portion for connecting with other layers or a gate driver (not illustrated).

The gate electrode124may be formed with the same metal pattern as the gate line. In the exemplary embodiment of the present invention, illustrated is only the case in which the gate electrode124is constituted by a single layer, but the gate electrode may be constituted by double layers.

As an example, when the gate electrode124is a double layer, the gate electrode124may have a structure in which a lower metal layer made of any one selected from aluminum (Al) and aluminum neodymium (AlNd) and an upper metal layer made of molybdenum (Mo) are sequentially laminated.

The lower metal layer as a layer serving as a passage of an electric signal which is an original function of the wiring is made of aluminum (Al) and aluminum neodymium (AlNd) having low specific resistance.

The upper metal layer as a layer positioned for protecting the lower metal layer serves to prevent hillock of aluminum (Al) caused in a subsequent process at a high temperature and lower contact resistance between the pixel electrode and the lower metal layer.

Next, a gate insulating layer140made of an insulating material such as silicon nitride is positioned on the gate line121. Although not illustrated, the gate insulating layer140may be configured by a lower gate insulating layer that prevents the gate electrode124from being oxidized by being made of an insulating material such as silicon nitride and an upper gate insulating layer for preventing a characteristic from deteriorating due to reaction of the adjacent semiconductor layer154and oxygen by being made of a nitrogen-rich insulating material as compared with the lower gate insulating layer.

Next, a semiconductor layer154made of amorphous silicon, particularly, hydrogenated amorphous silicon or polysilicon is positioned on the gate insulating layer140. In the exemplary embodiment of the present invention, the semiconductor layer154including hydrogenated amorphous silicon (a-Si:H) is preferable.

The semiconductor layer154mainly extends in a vertical direction of a side of the display panel adjacent to the gate driver and includes a plurality of projections protruding toward the gate electrode124.

A plurality of ohmic contact stripes161and ohmic contact islands165are positioned on the projections of the semiconductor layer154. The ohmic contact stripes161have a plurality of projections163, and the projections163and the ohmic contact islands165make pairs and are positioned on the projections of the semiconductor layer154.

On the ohmic contacts161and165and the gate insulating layer140, a plurality of data lines171, a plurality of source electrodes173connected to the plurality of data lines171, and a plurality of drain electrodes175facing the source electrodes173are positioned.

The data line171transfers a data signal and mainly extends in a vertical direction to cross the gate line121. The source electrode173extends toward the gate electrode124to have a U-lettered shape, but it is just an example and the source electrode173may have variously modified shapes.

The drain electrode175is separated from the data line171and extends upward from the center of the U-lettered shape of the source electrode173. An area of the data line171includes a data pad179for connecting with another layer or a data driver (not illustrated).

Although not illustrated, the data line171, the source electrode173, and the drain electrode175may also have double-layered structures of upper and lower layers. The upper layer may be formed of copper (Cu) or a copper alloy, and the lower layer may be formed of one of titanium (Ti), tantalum (Ta), molybdenum (Mo), and alloys thereof.

The data line171, the source electrode173, and the drain electrode175may have tapered sides.

The ohmic contacts161and165exist only between the semiconductor layer154therebelow and the data line171and the drain electrode175thereabove, and serves to decrease contact resistance therebetween. Further, the ohmic contacts161,163, and165may have substantially the same planar pattern as the data line171, the source electrode173, and the drain electrode175.

The projections of the semiconductor layer154have an exposed portion which is not covered by the data line171and the drain electrode175including a space between the source electrode173and the drain electrode175. The semiconductor layer154has substantially the same planar pattern as the ohmic contacts161and165except for the exposed portion of the projections.

One gate electrode124, one source electrode173, and one drain electrode175form one thin film transistor (TFT) together with the projections of the semiconductor154, and a channel of the thin film transistor is formed in the projection between the source electrode173and the drain electrode175.

A passivation layer180is positioned on the data line171, the drain electrode175, and the exposed projection portion of the semiconductor layer154. The passivation layer180is made of an inorganic insulating material such as silicon nitride or silicon oxide, an organic insulating material, a low-dielectric insulator, and the like.

A contact hole181exposing the gate pad129is positioned in the passivation layer180and the gate insulating layer140. Further, in the passivation layer180, a contact hole182exposing the data pad179of the data line171and a contact hole185exposing one end of the drain electrode175are positioned.

The pixel electrode191and contact aids81and82are positioned on the passivation layer180. The pixel electrode191and the contact aids81and82may be made of a transparent conductive material such as ITO or IZO, or reflective metal such as aluminum silver, chromium, or an alloy thereof.

The pixel electrode191is physically and electrically connected to the drain electrode175through the contact hole185, and receives a data voltage from the drain electrode175.

The contact aids81and82are connected with the end portion129(gate pad) of the gate line121and the end portion179(data pad) of the data line171through the contact holes181and182, respectively. The contact aids81and82compensate for adhesion between the gate pad129of the gate line121and the data pad179of the data line171and an external device and protects the gate pad129of the gate line121and the data pad179of the data line171.

Next, the upper panel200will be described with reference toFIG. 2.

A light blocking member220is positioned on a second insulation substrate210made of transparent glass or plastic. The light blocking member220blocks light leakage between the pixel electrodes191and defines an opening region facing the pixel electrode191.

A plurality of color filters230is positioned on the second insulation substrate210and the light blocking member220. Most of the color filters230exist in an area surrounded by the light blocking member220, and the color filters230may be elongated along a column of the pixel electrodes191. Each color filter230may display one of the primary colors such as three primary colors of red, green and blue.

In the exemplary embodiment, it is described that the light blocking member220and the color filters230are positioned on the upper panel200, but at least one of the light blocking member220and the color filters230may instead be positioned on the thin film transistor array panel100.

An overcoat250is positioned on the color filters230and the light blocking member220. The overcoat250may be made of an (organic) insulating material, prevents the color filters230from being exposed, and provides a flat surface. The overcoat250may be omitted.

A common electrode270is positioned on the overcoat250. The common electrode270is made of a transparent conductor such as ITO or IZO and receives a common voltage Vcom.

The liquid crystal layer3interposed between the thin film transistor array panel100and the upper panel200includes liquid crystal molecules having negative dielectric anisotropy, and the liquid crystal molecules may be aligned so that long axes thereof are vertical to the surfaces of the two display panels100and200without applying an electric field.

The pixel electrode191and the common electrode270form a liquid crystal capacitor together with the liquid crystal layer3portion therebetween to maintain the applied voltage even after the thin film transistor is turned off.

The pixel electrode191overlaps with a storage electrode line (not illustrated) to form a storage capacitor to thereby reinforce voltage storage capacity of the liquid crystal capacitor.

In the exemplary embodiment illustrated inFIG. 2, the backlight unit300may include a light source unit, a light guide plate, and the like and supplies light.

FIGS. 3 to 11are process diagrams for describing a part of a manufacturing method of the thin film transistor array panel illustrated inFIG. 2. The detailed description for like constituent elements described above is omitted.

Referring toFIG. 3, a plurality of gate lines121including a gate electrode124and a gate pad (not illustrated) is formed through a photolithography process by laminating the metal layer on the first insulation substrate110made of transparent glass or plastic through sputtering, and the like.

Next, referring toFIG. 4, on the first insulation substrate110with the gate line121, the gate insulating layer140, an intrinsic amorphous silicon layer150, and an impurity doped amorphous silicon layer160are sequentially formed. In this case, in this specification, the intrinsic amorphous silicon layer150and the impurity doped amorphous silicon layer160may be defined by active layers.

In detail, a process of formation the gate insulating layer140and the active layers150and160will be described.

First, the gate insulating layer140is laminated on the gate line121by a chemical vapor deposition (CVD) method. In this case, for example, silane gas (SiH4), hydrogen gas (H2), nitrogen gas (NH3), or the like is supplied into a CVD chamber forming the gate insulating layer140.

After formation of the gate insulating layer140, the intrinsic amorphous silicon layer150made of amorphous silicon (a-Si:H) is laminated by supplying source gas including SiF4gas and SiH4gas in the CVD chamber. Preferably, a deposition temperature in the CVD chamber may be about 150° C. to 350° C., for example, 300° C.

In the process of formation of the semiconductor layer154, in the aforementioned step, for example, the impurity doped amorphous silicon layer160is laminated by supplying silane gas (SiH4), hydrogen gas (H2), nitrogen gas (NH3) and phosphine gas (PH3) in the CVD chamber.

Next, the data metal layer170is sequentially laminated on the impurity doped amorphous silicon layer160by a sputtering method. The data metal layer170may be formed of metal such as chromium, aluminum, tantalum, molybdenum, titanium, tungsten, copper, and silver or alloys thereof, and may be formed by two or more layers having different physical properties.

Preferably, the data metal layer170may be deposited by a sputtering process as a layer made of copper or a copper alloy.

Next, referring toFIG. 5, a photoresist layer PR is laminated on the data metal layer170. In this case, the photoresist layer PR is differentially exposed by using a mask including etching patterns at positions corresponding to desired patterns of the semiconductor layer and the data metal layer. According to the exposure result, as illustrated inFIG. 5, an etching mask pattern400ais disposed on the data metal layer170.

In general, the etching mask pattern is disposed at a position where an intrinsic semiconductor stripe151including the projection portion154, the plurality of ohmic contacts161, the plurality of data lines171including the source electrode173and the end portion179(data pad), and the plurality of drain electrodes175are to be formed. The etching mask pattern400aillustrated InFIG. 5is disposed in a region where the thin film transistor is to be formed, and a height of a portion where the channel region of the thin film transistor is to be formed on the gate electrode124is lower than that of the periphery by about one-half. In addition, although not illustrated, another etching mask pattern is disposed in a region where the linear data line171and the end portion179(data pad) of the data line171are to be formed.

Next, referring toFIG. 6, a first wet etching process in which the data metal layer170is etched by using the mask pattern400aas an etching mask is performed. In the wet etching, since the data metal layer170is isotropically etched by a wet-etchant, under cutting may occur, in which the side of the data layer174generated by the first wet etching process is further depressed than the mask pattern400a. As a result, as illustrated inFIG. 6, the data layer174having the end portion179(data pad) is formed, and an etch surface N is exposed at the side of the data layer174etched by the under cutting.

Next, referring toFIG. 7, an active etching process of etching the intrinsic amorphous silicon layer150and the impurity doped amorphous silicon layer160by using the mask pattern400aas an etching mask, is performed. The active etching process according to the exemplary embodiment of the present invention uses the dry-etch process using NF3/H2gas.

As a result, as illustrated inFIG. 7, the intrinsic amorphous silicon layer150and the impurity doped amorphous silicon layer160are removed from a portion except for the data line including the end portion179(data pad) and a lower portion of the data layer174of the thin film transistor to form the semiconductor154and the ohmic contact164.

As such, since the intrinsic amorphous silicon layer150and the impurity doped amorphous silicon layer160are etched by using the same etching mask pattern400aas the process of formation of the data line (not illustrated) including the end portion179and the data layer174, the semiconductor154has substantially the same planar form as the data line (not illustrated), the data layer174, and the ohmic contact164therebelow.

In addition, in the active etching process according to the exemplary embodiment of the present invention, a silicon compound176using NF3/H2gas used in the active etching process is generated on the etch surface N of the data layer174of the thin film transistor and on the etching mask pattern400a. The silicon compound176using NF3/H2gas may generate (NH4)2SiF6.

In the four-sheet mask process in the related art, as an etching method of removing the intrinsic amorphous silicon layer150and the impurity doped amorphous silicon layer160, a dry etching method using mixed gas such as chlorine-based gas such as HCL gas and Cl2gas and SF6gas is used. The chlorine-based gas reacts with copper (Cu) included in the data layer174on the etch surface N, copper chloride (CuCl(s) and CuCl2(s)) as reaction by-products is generated, and copper chloride (CuCl(s) and CuCl2(s)) remains on the data layer174to cause an increase of wiring resistance and wiring defect. Accordingly, in order to prevent the aforementioned reaction by-products from being generated, chlorine-based gas is omitted, and even in the case of etching using only SF6gas, copper fluoride (CuF2(s)) is generated as the reaction by-products. That is, even in the case of using only SF6gas, the aforementioned defects are caused.

Accordingly, in the active etching process according to exemplary embodiment of the present invention, a structure illustrated inFIG. 7is formed by performing the dry etching process using NF3/H2gas.

Next, as illustrated inFIG. 8, by ashing the photoresist etching mask pattern400aby using oxygen plasma, the height of the etching mask pattern400alaminated on the thin film transistor is decreased to one-half and simultaneously, the remaining etching masks are removed even though not illustrated.

In this case, preferably, in the ashing process according to the exemplary embodiment of the present invention, as ashing conditions for reinforcing an anisotropic property according to a dry etching characteristic, low pressure and high bias power may be used.

Next, as illustrated inFIGS. 9 and 10, a second wet etching process of integrally removing the data metal layer174which remains in the channel region of the thin film transistor and the impurity doped amorphous silicon layer164by using the remaining etching mask pattern400a, is performed. As a result, on the data metal layer174, the source electrode173and the drain electrode175which overlap with the gate electrode124by a predetermined distance from the gate electrode124, are formed.

During the active dry etching process using NF3/H2gas used to produce the structure ofFIG. 6, the silicon compound176is laminated on the etch surface of the data metal layer174and serves as an etching stop layer in the second wet etching process of removing the metal layer. Accordingly, as illustrated inFIG. 9, only a part of an intermediate region of the data layer174is etched and the side may be prevented from being etched according to the etching mask pattern400a. As a result, etch skew may be prevented from occurring when the metal layer is exposed in the etching process.

Further, as illustrated inFIG. 10, in the second wet etching process, the exposed impurity doped amorphous silicon layer164is removed from a separation portion of the source electrode173and the drain electrode175, and as a result, the ohmic contacts163and165are completed and the intrinsic semiconductor154portion therebelow is exposed. In this case, due to the silicon compound176formed on the side of the source electrode173and the drain electrode175, the impurity doped amorphous silicon layer164remaining in the channel region of the thin film transistor may also be etched by using the wet etching method.

Accordingly, the data layer174formed in the channel region of the thin film transistor and the impurity doped amorphous silicon layer164may be removed by the same wet etching process, and the wiring skew may be prevented from being generated through the silicon compound176.

Further, as described above, the data metal layer174may be etched by using the second wet etching process and the amorphous silicon layer164may be etched by using the dry etching process using SF6-based gas.

Next, as illustrated inFIG. 11, the intrinsic semiconductor154, the ohmic contacts163and165which are the impurity doped semiconductor, the source electrode173, and the drain electrode175are completed by removing the etching mask pattern400a.

Thereafter, as illustrated inFIG. 2, after formation of the passivation layer180to cover the semiconductor154, the contact hole185exposing a part of the drain electrode175is formed through the photolithography process. A transparent conductive layer (not illustrated) is deposited on the passivation layer180, and the pixel electrode191electrically connected with the drain electrode is formed through the photolithography process.

Hereinabove, the four-sheet mask process is described, but the present invention is not limited thereto, and of course, the five-sheet mask process may also be used even five-sheet mask process, of course.

FIGS. 12 and 13are diagrams for describing a performance experiment result of a wet etching process with respect to an impurity doped amorphous silicon layer according to the exemplary embodiment of the present invention.

Data illustrated inFIG. 12represent an etch rate E/R per second derived from an a-Si etch rate of the impurity doped amorphous silicon layer measured according to an etching condition of additionally over-etching up to 75 seconds by 6 seconds based on etchant TCE-W02@25° C., 5-line normal deposition, 5-line etching equipment, and a normal etch time of 33 seconds,

FIG. 13illustrates an etch rate E/R per second of the active layer according to a time (seconds) based on the data ofFIG. 12as a graph.

Referring toFIG. 13, during wet etching for the active layer, it can be seen that the etch rate E/R per second is high in an early stage in which the wet etching is performed, but the etch rate E/R per second is reduced with time. It can be seen that the etch rate E/R per second of the impurity doped amorphous silicon layer160positioned above the active layer which first reacts with the etchant is the maximum, but the etch rate E/R per second is saturated with time, and as a result, the intrinsic amorphous silicon layer150may be prevented from being etched during the second wet etching by controlling the thickness of the impurity doped amorphous silicon layer160.

FIGS. 14 and 15are diagrams for describing a performance result of a wet etching process with respect to a gate insulating layer GL/GH of the thin film transistor according to the exemplary embodiment of the present invention.

FIGS. 14 and 15are graphs illustrating a wet etching process result performed under etching conditions of etchant TCE-W02@25° C., GH layer 4000A (7BFCV07_PC02), GL layer 4000A (7BFCV07_PC04), use of etching equipment No. 7BFME03 and No. 7BFME06, and an etch required time of 66 seconds based the measured data.

FIG. 14illustrates a graph of the etch rate E/R per second according to use of the etching equipment No. 7BFME03 and No. 7BFME06 with respect to the first gate insulating layer (GL layer) under the aforementioned etching conditions, andFIG. 15illustrates a graph of the etch rate E/R per second according to use of the etching equipment No. 7BFME03 and No. 7BFME06 with respect to the second gate insulating layer (GH layer) under the aforementioned etching conditions.

As compared with the etch rate E/R per second of 4.00 to 4.65 at the same etching required time of 66 seconds with respect to the active layer illustrated inFIG. 12, it can be seen that a wet etch rate of 0.9 to 1.3 of the first gate insulating layer (GL layer) and a wet etch rate of 2.18 to 3.47 of the second gate insulating layer (GH layer) are smaller than the etch rate for the active layer.

Accordingly, in the manufacturing process of the thin film transistor array panel according to the exemplary embodiment of the present invention described above, even though the wet etching process is used when removing the impurity doped amorphous silicon layer160formed in a partial region on the drain electrode, the gate insulating layer may be prevented from being etched.

FIGS. 16 and 17are experimental graphs for comparing etching process results with respect to a data metal layer and an impurity doped amorphous silicon layer according to the exemplary embodiment of the present invention.

FIG. 16compares results of off leakage current Ioff measured during single wet etching in which the data metal layer170and the impurity doped amorphous silicon layer160are integrally wet etched and wet-dry combined etching in which the data metal layer170is wet-etched and the impurity doped amorphous silicon layer160is dry-etched according to the exemplary embodiment of the present invention.

Referring toFIG. 16, when Ioff in the wet-dry combined etching which is 1.98-12 and Ioff in the single wet etching which is 8.26-13 are compared with each other, it can be seen that during the single wet etching according to the exemplary embodiment of the present invention, the leakage current has a significantly low value as compared with the combined etching. That is, when the data metal layer170is wet-etched, the impurity doped amorphous silicon layer160is integrally wet-etched, and as a result, it can be seen that the off leakage current Ioff amount is improved.

FIG. 17Aillustrates a result of current Id measured in source/drain electrodes during the single wet etching in which the data metal layer170and the impurity doped amorphous silicon layer160are integrally wet-etched when voltage Vg is applied to the gate electrode.FIG. 17Billustrates a result of current Id measured in the source/drain electrodes during the wet-dry combined etching in which the data metal layer170is wet-etched and the impurity doped amorphous silicon layer160is dry-etched when the voltage Vg is applied to the gate electrode.

Referring toFIGS. 17A and 17B, it can be seen that even under the same gate electrode condition, a reduction amount of Id measured during the single wet etching is smaller than that of Id measured during the combined etching with time, and the gate electrode is driven well during the single wet etching. That is, as illustrated inFIG. 15, it can be seen that during the single wet etching, the value of off leakage current Ioff is improved as compared with the combined etching.

The off leakage current Ioff causes fine driving of the switching element even when the switching element is turned off to be the cause of an afterimage. Accordingly, it can be seen that the liquid crystal display of the exemplary embodiment is very advantageous to improvement of the afterimage.

Hereinabove, in the exemplary embodiment, the thin film transistor array panel applied to the liquid crystal display is described, but the description for the thin film transistor array panel100may be applied to any other display devices.

While this invention has been described in connection with what is presently considered to be practical exemplary embodiments, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims. A performance experiment of the thin film transistor array panel will be described.

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