Frequency synthesizer and method for constructing the same

A frequency synthesizer and a method for constructing the same by using the architecture of digital process frequency loop (DPFL) are disclosed. The DPFL frequency synthesizer with the DPFL architecture includes a reference frequency divider counter, an output divider counter, a processor, a memory, a digital to analog converter (DAC), and a voltage Control Oscillator (VCO). The method uses the processor to perform the signal processing to correct the output frequency of the VCO in the frequency domain. The memory stores the nonlinear characteristics of the VCO such that the synthesizer is completely controlled, no uncertain frequency being captured during process, and the frequency resolution of the synthesizer is programmable.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates generally to a frequency synthesizer, and more particularly, to a method for using the architecture of digital process frequency loop (DPFL) with a processor and a DAC (Digital to Analog Converter) to construct an electronic frequency synthesizer.

2. The Prior Arts

The frequency synthesizer has been widely used to generate the target frequency corresponding to system requirement in many electronic applications for years. One of the most common frequency synthesizers is the PLL frequency synthesizer, in which the PLL includes a phase detector and a charge pump or a low pass filter. As well known, the PLL frequency synthesizer in the prior arts was invented in the 1930s.

With reference toFIG. 1, the block diagram of the PLL frequency synthesizer shows that the synthesizer includes a frequency divider1, a phase detector2, a low pass filter/charge pump3, a voltage control oscillator (VCO)4and an output frequency divider5. The synthesizer has a reference frequency fREFas an input signal, which is quite stable. The characteristic of the VCO4is that the output frequency fOof the VCO will change when the input voltage of the VCO changes, as shown inFIG. 4.

The reference frequency with high stability is fed straight to one input of the phase detector2or fed through the frequency divider1that divides down the reference frequency before it feeds to the input of the phase detector2. Another frequency that is generated from the VCO4of the frequency synthesizer also is divided down by the output frequency divider5and feeds into another input of the phase detector2.

The function of the phase detector2is to generate a voltage in proportion to the amount of the phase difference between the two inputs of the phase detector2, when the reference frequency is leading or lagging. The generated voltage then passes through a low pass filter/charge pump3to steer the VCO4to a frequency that will make the two input signals in phase at the input of the phase detector2. As a result, the output frequency of the VCO4is said to lock on to the reference frequency. The phase detector2has no output voltage when the two signals are in phase. It relies on the charge pump3to maintain the input voltage of the VCO4. The charge pump3will lose its voltage because of the leakage current that causes the VCO4to change its frequency until the phase difference is large enough for the phase detector3to realize the difference and start to provide the corresponding voltage to the charge pump3to bring it back to the targeted frequency.

There are two drawbacks in the traditional PLL frequency synthesizer. Firstly, the PLL frequency synthesizer has two variables to deal with, including the frequency and the phase. As well known, the phase difference obtained by the phase detector does not have any information about the frequency or vice versa. Secondly, the VCO starts to react to the voltage when the charge pump is charging. The output frequency divider is continuously counting. Some unwanted frequencies will be unwontedly captured. These unwontedly captured frequencies become smaller and smaller as the output frequency gets closer to the final frequency. It will take several tries to lock.

SUMMARY OF THE INVENTION

A primary objective of the present invention is to provide a method and an apparatus for constructing a frequency synthesizer to overcome the shortcomings in the prior arts. The innovative DPFL of the present invention is used to build an electronic frequency synthesizer. The method uses a time base counter, a frequency counter, a processor, and a DAC, instead of a phase detector in PLL architecture. With digital processing technique, the frequency counter corrects the VCO output in the specified frequency domain. Furthermore, there is no phase relationship between the reference frequency and the output frequency.

Another objective of the present invention is to provide a method and an apparatus for building the DPFL frequency synthesizer with a memory to store the nonlinearity characteristics of the VCO. The DPFL frequency synthesizer first searches all the corresponding values for the DAC to drive the VCO to generate the target frequency within the range of the target frequency. Each value is stored in the memory with the address as value of the target frequency.

A still another objective of the present invention is to provide a method and an apparatus for constructing a DPFL frequency synthesizer with a smaller memory. The DPFL frequency synthesizer includes a coarse memory, a coarse DAC, a vernier memory, a vernier DAC, and a summation amplifier. The LSB voltage of the coarse DAC equals to the full scale of the vernier DAC minus one LSB such that the memory size is greatly reduced.

A yet another objective of the present invention is to provide a method and an apparatus for constructing a DPFL frequency synthesizer, which searches and stores the VCO transfer characteristic, the VCO settling time, and the frequency sustain time of the VCO in advance, and then that stored data is processed by digital processing technique such that all the characteristics of the synthesizer are well known and completely controlled so as to reach the targeted frequency faster. Moreover, better frequency resolution is obtained and signal noise introduced by digital parts can be minimized by closing the counter for a period of the frequency sustain time.

The foregoing and other objectives, features, and advantages of the invention will become apparent from the following, more specific, description of the preferred embodiment of the invention, as illustrated in the accompanying drawings.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

The method of the present invention constructs a DPFL frequency Synthesizer with a processor and a DAC to replace the phase detector and the low pass filter/charge pump of the prior arts.

With reference toFIG. 2, the functional block diagram of the DPFL frequency Synthesizer of the first embodiment according to the present invention is shown. The DPFL frequency Synthesizer includes an N1 counter10, an N2 counter11, a processor9, a DAC7, and a VCO8. The function of the DPFL frequency Synthesizer is to generate an accurate and specified frequency fObased on an stable input reference frequency fREF, as shown inFIG. 2.

The “time base” N1 counter10is either a fixed value counter or a programmable counter. The N2 counter11counts the output frequency of VCO8. Since the time base derives from N1 counter10with respect to fREF, the measured frequency by the N2 counter11is fairly accurate. The measured frequency is sent to the processor9.

FIG. 3is the block diagram of the processor9. The processor9includes a programmed holding register91, a DAC holding register92, a first arithmetic logic unit (ALU)93, and a second ALU94. The programmed holding register91stores the value of the programmed target frequency, which is specified by a control device, such as the processor or the computer. The measured frequency by the N2 counter11is subtracted from the programmed holding register91by the first ALU93and then the subtracted result is added to the value in the DAC holding register92by the second ALU94. The second ALU94sends the added value back to the DAC holding register92, and then the DAC holding register92transfers the updated value to the register in the DAC7.

The DAC holding register92has 3 input ports, including the Hold/Update port, the first input data port, and the second input data port. The first input data port is connected to the output port of the second ALU94, and the second input data port is connected to the output port of the programmed holding register91. The fold/Update port switches the DAC holding register92to the Hold or Update modes. In the Hold mode, the DAC holding register92will hold the output data sent to the DAC7regardless of any change at the first and second input data ports.

In the Update mode, the DAC holding register92will update the output data with respect to the first and second input data. The second input data port is updated only when a new value is written to the programmed holding register91by the system, such as the computer or processor.

If the subtracted result is a positive number, the output frequency of the VCO8is lower than the target frequency. As shown inFIG. 4, the voltage for the DAC7needs to be increased to bring up the output frequency of the VCO8. The second ALU94obtains a new data by adding the output data of the DAC holding register92and the subtracted result from the first ALU93. The new data sent back to the DAC holding register92is larger than the previous data transferred from the programmed holding register91.

The measured result from the N2 counter11always needs to compare with the value in the programmed holding register91to check whether the output frequency of the VCO8reaches the target frequency or not.

Now the output voltage of the DAC7is increased because the output data from the DAC holding register92is updated by the new larger value. Thus, the VCO8starts to increase the output frequency. After the output frequency of the VCO8is settled, the N2 counter11begins the frequency measurement again. The result of the N2 counter11is subtracted from the holding register91by the first ALU93. This time if the subtracted result is a negative number, that means the output frequency of the VCO8is higher than the target frequency. The negative number is then added to the DAC holding register92again by the second ALU94. Consequently, the DAC holding register92obtains an updated smaller data. As a result, the DAC7decreases its voltage and causes the VCO8to reduce the output frequency.

The above process repeats until the measured value of the N2 counter11matches the value in the programmed holding register91. This means that the output frequency of the VCO8reaches the target frequency as desired. The N2 counter11has a value equal to the value in the programmed holding register91and the difference of the subtraction is zero. Therefore the DAC holding register92will not change the stored value because a zero is always added to the DAC holding register92. Once the output frequency of the VCO8drifts off due to any reason, the search process as mentioned above begins again to correct the output frequency of the VCO8to match the target frequency.

Since the DPFL technique does not use the phase detector, the output frequency of the synthesizer does not have any phase relationship with the reference frequency.

As shown inFIG. 4, the transfer characteristic of the voltage and frequency of the VCO8is a nonlinear function. However, the values in the programmed holding register91and DAC holding register92are linear. It is desired to compensate the nonlinearity of the VCO.

With reference toFIG. 5, the second embodiment according to the present invention includes a memory, ROM or nonvolatile memory6in the DPFL synthesizer, which is used to perform translation of the linear function elements to the nonlinear function element of the VCO as mentioned above.

To clearly explain the function of the memory6in the DPFL frequency synthesizer of the second embodiment according to the present invention, assume that the synthesizer has a valid working range of 90 MHz to 100 MHz, which will be used throughout the entire text. Noted that this range is only an example for description and not limited to the present invention.

It also assumes that the following conditions are true and perfect:(1) The programmed holding register91inFIG. 3is 28 bits wide.(2) Time base from the N1 counter10inFIG. 5is 1 second for the purpose to have a resolution of 1 Hz.(3) The N2 counter11inFIG. 5also is 28 bits wide for having a resolution of 1 Hz.(4) The first ALU93and the second ALU94inFIG. 3are 28 bits wide.(5) The DAC holding register92inFIG. 3is 28 bits wide.(6) The DAC register is 28 bits wide and the DAC7is 28 bits DAC inFIG. 5.(7) The VCO8inFIG. 5is stable to 1 Hz.

Consider all the values from 90 Mhz to 100 Mhz with 1 Hz increment for the following discussion, i.e., 90,000,001, 90,000,002, . . . , 100,000,000. The function of the memory6is to store the correct value for the DAC so as to drive the VCO to generate the target frequency as desired.

The Hold/Update port of the DAC holding register92inFIG. 3is set in the Hold mode.

The value of the target frequency is programmed to the programmed holding register91and transferred to the DAC holding register92. Since the DAC holding register92is in the HOLD mode, the output data of the DAC holding register92will not be updated. Initially, a suitable value is written to the DAC register to drive the VCO8to the vicinity of the target frequency by the system. After the VCO8is settled, the N2 counter11begins to measure the output frequency of the VCO8. If the N2 counter11does not match the value in the programmed holding register91, the DAC7will be loaded with a new value from the system, and the N2 counter11repeats the process of measurement as the above mention until the N2 counter11matches the value in programmed holding register91. Now the value in the DAC7register is the right value for the target frequency. This value is read and then stored in the memory6with the value in the programmed holding register91as the memory address.

Sequentially the value in the DAC7is changed for another value as a new target frequency and the entire searching process repeats until all the correct values for the target frequencies from 90 MHz to 100 MHz are found and stored in the memory6. Theoretically the frequency synthesizer should reach the target frequency the first time when the programmed holding register91is programmed.

Now the DAC holding register92is set in the Update mode, and the value of the target frequency of 100 MHz is loaded to the programmed holding register91. The stored value of the programmed holding register91is transferred to the DAC holding register92, which addresses the memory6to fetch the right value for the DAC7to drive the VCO8to generate 100 MHz as desired.

After a period of time for the VCO8to settle at 100 MHz, the value of the target frequency of 90 MHz is programmed to the programmed holding register91. This is the worse case condition that the VCO has to settle to 90 MHz from 100 MHz.

The N2 counter11starts the frequency measurement immediately after the programmed holding register91is written before the VCO8is settled. The result of the measure is stored as RV1. It is anticipated that RV1is not the targeted frequency because the VCO8is not yet settled when the N2 counter11starts. After RV1is stored, the N2 counter11starts again for the second measurement. The result of the second measurement should be 90 MHz because the VCO8should be settled during the first measurement.

The same process is repeated from the beginning by setting the synthesizer to 100 MHz, waiting for it to settle, and then changing the targeted frequency to 90 MHz. This time we wait for 10 μs to start the N2 counter11. Then the process repeats from the beginning and waits for 20 μs, 30 μs, . . . until 90 MHz is measured by the N2 counter11. This is the VCO9settling time t1as shown inFIG. 6.

Another important information is the frequency sustain time t3, as shown inFIG. 6. To find the frequency sustain time t3, a time delay is set by the computer or processor and then check the output frequency with the N2 counter11. By increasing the delay time until the output frequency of the VCO8drifts off the specification, the sustain time t3is found. The purpose of knowing the sustain time is to reduce the digital switching noise derived from the digital parts in the synthesizer, that is the output frequency can sustain for the sustain time and the N2 counter11may be turned off during the sustain time.

Another factor is the t2time. It is under the control of the designer. It is pretty well determined by the resolution requirement for a particular synthesizer. Actually most of the applications do not require this kind of resolution.

The example using 1 Hz resolution shows that it is capable of achieving 1 Hz resolution theoretically. In fact to obtain a 1 Hz resolution at 100 MHz is extremely difficult.

FIG. 7shows that the resolution can be adjusted by changing the time base. The better the resolution, the longer the time for N2 counter11to take the measurement. Using 100 MHz as an example, for the frequency synthesizer with 1 Hz resolution, the measurement takes one second. For 8 Hz resolution, it takes 125 ms. For 256 Hz resolution, it takes only 3.90625 ms. Consequently the DAC, all the counters and ALU width also become less when the resolution is larger in value. Furthermore, it takes a reasonable size memory to store all the frequency values as shown inFIG. 5.

If the synthesizer is a fixed frequency synthesizer, the size of the memory size is not large. For example, a frequency synthesizer only operates at 98 MHz. If the VCO deviates less than 4 KHz from the target frequency, the memory needs to store only 4,096 values. If the frequency synthesizer is a variable synthesizer and has a range from 90 MHz to 100 MHz, the memory size needs to be 10 million deep and 28 hits wide if the resolution is 1 Hz. If the resolution is 10 Hz then the memory depth is reduced by 10 times.

With reference toFIG. 8, the functional block diagram of the DPFL frequency synthesizer of the third embodiment according to the present invention includes the coarse memory60and the vernier memory61instead of the memory6inFIG. 5. The DPFL frequency synthesizer further includes the coarse DAC70and the vernier DAC71, which are connected to the coarse memory60and the vernier memory61, respectively, instead of the DAC7inFIG. 5.

The summing amplifier80is included to add or subtract the output voltage of the vernier DAC71to the output voltage of the coarse DAC70. The LSB voltage of the coarse DAC70equals to the full scale of the voltage of the vernier DAC71minus one LSB.

Assuming that the address of the coarse memory60is 16 bits and the address of the vernier memory61is 12 bits, the above example of 90 MHz to 100 MHz frequency synthesizer shows that the vernier memory61needs a depth of 4096 to store each coarse frequency. Each value of the frequency stored in the coarse memory60is separate by 4096 Hz and the first value starts at 90 MHz. The coarse memory60is reduced to a depth of 2442 by 16 bits wide for the frequency range from 90 MHz to 100 MHz. The vernier memory61remains the same depth of 10 million by 12 bits wide. 4096 vernier memory locations are needed to support each coarse memory location.

It is not so difficult to search the values for the coarse frequencies because of only 2442 values to be searched. However, it would take a long time to search all the vernier values because the 4096 vernier locations for one coarse frequency may not be the same as another 4,096 vernier locations of the other coarse frequency due to the nonlinearity of the VCO transfer characteristic.

A faster approach to find the vernier values for different coarse frequency is to approximate the 4096 steps as a linear function using different slope for different coarse frequency as shown inFIG. 10. This linear approximation would eliminate the tedious searching time.

FIG. 9shows another benefit of the DPFL technique of the present invention used in FM modulation. During the t3time inFIG. 6when the correction is found and before it drifts off, the Hold/Update input port of the DAC holding register92is set in the Hold mode.

By doing so, the DAC holding register92is not updated and holds the same address to the memories, and the VCO8is driven by the same value. The frequency modulation can take place at this time because the modulation voltage is added to the total sum of the coarse DAC70and the vernier DAC71by the modulation amplifier81. By holding off the Hold/Update port of the DAC holding register92, the changes of the modulation frequency are not being corrected. If the time base of the t2time is too long, it may interfere into the modulation time, and thus the t2time can be cut into small segments during the modulation time as t2=t2a+t2b+t2c . . . .

FIG. 10shows the frequency variation when the information is modulated to the carrier frequency. As frequency modulation, the change in the frequency represents the change in volume of the voice or information and the change rate of the carrier frequency represents the frequency of the information, as shown inFIG. 11.

More benefits from the present invention are shown inFIG. 12. The N2counter11is used to measure the modulated FM frequency from the FM receiver which is either IF or RF. The carrier frequency is loaded into the programmed holding register91. The first ALU93subtracts the carrier frequency in the programmed holding register91from the modulated frequency. Therefore, the output of the first ALU93is the demodulated signal.

With the above detailed description, the present invention is more understandable for those skilled in the prior arts. There are 3 main features for the present invention.

Firstly, in accordance with the present invention, the method of DPFL technique only deals with one variable, which is the frequency, but the PLL frequency technique has two variables, one the phase difference and the other is frequency. Unfortunately, any information for one variable does not relate to the other. As a result of reducing to a single variable, the entire functions of the synthesizer are more predictable.

The control of the synthesizer by digital processing technique can be easily tailored to different applications by changing the control algorithm. The digital processing technique can be applied to the frequency synthesizer that does not require the output frequency to maintain a phase relationship with the reference frequency.

Secondly, the DPFL technique of the present invention does not use phase detector and the frequency resolution of the synthesizer is programmable. However, the phase detector used in the PLL technique has certain input resolving power.

Thirdly, the DPFL technique of the present invention does not have an automatic feedback loop but waits for the VCO to settle. Frequency begin capture time is controlled by the processor. There is no uncertain frequency being captured. In the PLL technique the VCO output divider is continuously counting even while the charge pump is being charged. Therefore, the output frequency is changing while the charge pump is charging and the output frequency divider may capture some uncertain frequencies.

While the invention has been particularly shown and described with reference to preferred embodiments thereof, it will be understood by those skilled in the art that the foregoing and the other changes in form and details may be made therein without departing from the spirit and the scope of the invention.